1694 files changed, 215719 insertions, 106462 deletions

diff --git a/gas/COPYING b/gas/COPYING
index c27986e64cde..22c7fc2011fa 100644
--- a/gas/COPYING
+++ b/gas/COPYING
@@ -2,7 +2,7 @@
 		       Version 2, June 1991
 
  Copyright 1989, 1991, 1997 Free Software Foundation, Inc.
-                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+                       51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -305,7 +305,7 @@ the "copyright" line and a pointer to where the full notice is found.
 
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 
 
 Also add information on how to contact you by electronic and paper mail.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 209d3bb95614..1723944a36e8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,622 +1,758 @@
-2005-06-08  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+2006-07-19  Mat Hostetter  <mat@lcs.mit.edu>
 
-	* config/tc-m32r.c (use_parallel): Change default value from 1 to 0.
+	* symbols.c (report_op_error): Fix pasto.  Don't use as_bad_where
+	when file and line unknown.
 
-2004-08-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+2006-06-07  Joseph S. Myers  <joseph@codesourcery.com>
 
-	* config/tc-mips.c (append_insn): Handle delay slots in branch likely
-	correctly.
+	* po/Make-in (pdf, ps): New dummy targets.
 
-2004-07-28  Jason Thorpe  <thorpej@wasabisystems.com>
+2006-06-02  Joseph S. Myers  <joseph@codesourcery.com>
 
-	* config/tc-hppa.h (TARGET_FORMAT): Set to "elf32-hppa-netbsd"
-	for TE_NetBSD.
+	* doc/Makefile.am (TEXI2DVI): Define.
+	* doc/Makefile.in: Regenerate.
+	* doc/c-arc.texi: Fix typo.
 
-2004-05-23  Alan Modra  <amodra@bigpond.net.au>
+2006-05-30  Nick Clifton  <nickc@redhat.com>
 
-	* expr.c (operand, operator): Don't reject '++' and '--'.
+	* po/es.po: Updated Spanish translation.
 
-2004-05-13  Joel Sherrill <joel@oarcorp.com>
+2006-05-25  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* configure.in (or32-*-rtems*): Switch to elf.
-	* configure: Regenerate.
+	* gas/config/tc-m68k.c (m68k_init_arch): Move checking of
+	cfloat/m68881 to correct architecture before using it.
 
-2004-05-13  Nick Clifton  <nickc@redhat.com>
-
-	* po/fr.po: Updated French translation.
-
-2004-05-07  Daniel Jacobowitz  <dan@debian.org>
-
-	* Makefile.am (DIST_SUBDIRS): Define.
-	* aclocal.m4: Regenerate with automake 1.8.4.
-	* Makefile.in: Likewise.
-	* doc/Makefile.in: Likewise.
-
-2004-05-07  Daniel Jacobowitz  <dan@debian.org>
-
-	Merge from mainline:
-	2004-05-05  Jakub Jelinek  <jakub@redhat.com>
-	* tc-s390.h (md_do_align, HANDLE_ALIGN): Remove.
-	(NOP_OPCODE): Define.
-	(s390_align_code): Remove prototype.
-	* tc-s390.c (s390_align_code): Remove.
-
-	2004-04-22  Bruno De Bus <bdebus@elis.ugent.be>
-	* config/tc-arm.h (enum mstate): Move here, add MAP_UNDEFINED
-	state.
-	(TC_SEGMENT_INFO_TYPE): Define to enum mstate.
-	* config/tc-arm.c (enum mstate): Delete from here.
-	(mapping_state): Remove the static mapstate variable and instead
-	store the state in the segment.  This allows a per-section mapping
-	state.  Handle and ignore MAP_UNDEFINED states.
-	(arm_elf_change_section): Get the current mapping state from the
-	new section.
-	(s_ltorg): Set the mapping state to MAP_DATA.
-	(arm_cleanup): Use arm_elf_change_section to get the mapping state
-	for each pool as it is emitted.
-
-	2004-04-22  Nick Clifton  <nickc@redhat.com>
-	* config/tc-arm.h: Formatting tidy ups.
-
-2004-05-07  Alexandre Oliva  <aoliva@redhat.com>
-
-	* config/tc-frv.h (MAX_MEM_FOR_RS_ALIGN_CODE): New.
-	(HANDLE_ALIGN): New.
-
-2004-05-05  Alexandre Oliva  <aoliva@redhat.com>
-
-	* configure.in: Set em=linux for frv-*-*linux*.
-	* configure: Rebuilt.
-	* config/tc-frv.h (TARGET_FORMAT): Use elf32-frvfdpic if...
-	(frv_md_fdpic_enabled): New.
-	* config/tc-frv.c (frv_md_fdpic_enabled): New.
-	(DEFAULT_FDPIC): New.
-	(frv_flags): Use DEFAULT_FDPIC.
-	(frv_pic_flag): Likewise.
-	(OPTION_NOPIC): New.
-	(md_longopts): Add -mnopic.
-	(md_parse_option): Handle it.
-	(md_show_usage): Add -mfdpic and -mnopic.
+2006-05-16  Nick Clifton  <nickc@redhat.com>
+
+	* Import these patches from the mainline:
+
+	2006-05-16  Bjoern Haase  <bjoern.m.haase@web.de>
+
+        * config/tc-avr.h (TC_VALIDATE_FIX): Allow fixups for immediate
+	constant values.
+
+	2006-05-05  Bjoern Haase  <bjoern.m.haase@web.de>
+
+	* gas/config/tc-avr.h (TC_VALIDATE_FIX): Define.  Disable fixups
+	for PMEM related expressions.
+
+2006-05-11  Thiemo Seufer  <ths@mips.com>
+
+	* config/tc-mips.c (append_insn): Don't check the range of j or
+	jal addresses.
+
+2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* dwarf2dbg.c (get_line_subseg): Attach new struct line_seg to end
+	of list rather than beginning.
+
+2006-05-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* write.c (relax_segment): Add pass count arg.  Don't error on
+	negative org/space on first two passes.
+	(relax_seg_info): New struct.
+	(relax_seg, write_object_file): Adjust.
+	* write.h (relax_segment): Update prototype.
+
+2006-05-02  Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-arm.c (do_iwmmxt_wldstbh): Don't multiply offset by 4
+	here.
+	(md_apply_fix3): Multiply offset by 4 here for
+	BFD_RELOC_ARM_CP_OFF_IMM_S2 and BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2006-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (AM_MAKEINFOFLAGS): New.
+	(TEXI2POD): Use AM_MAKEINFOFLAGS.
+	(asconfig.texi): Don't set top_srcdir.
+	* doc/as.texinfo: Don't use top_srcdir.
+	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2006-05-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_optimize_expr): New function.
+	* config/tc-arm.h (md_optimize_expr): Define
+	(arm_optimize_expr): Add prototype.
+	(TC_FORCE_RELOCATION_SUB_SAME): Define.
+
+2006-05-01  James Lemke  <jwlemke@wasabisystems.com>
+
+	* subsegs.c (subseg_set_rest): Always set seginfp->frchainP if NULL.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (widen_spec_list): Use new "WIDE.<opcode>"
+	syntax instead of hardcoded opcodes with ".w18" suffixes.
+	(wide_branch_opcode): New.
+	(build_transition): Use it to check for wide branch opcodes with
+	either ".w18" or ".w15" suffixes.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_create_literal_symbol,
+	xg_assemble_literal, xg_assemble_literal_space): Do not set the
+	frag's is_literal flag.
+
+2006-04-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-relax.c (XCHAL_HAVE_WIDE_BRANCHES): Provide default.
+
+2006-04-16  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* po/POTFILES.in: Regenerated.
+
+2006-04-14  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (emit_single_op): Do not relax MOVI
+	instructions when such transformations have been disabled.
+
+2006-04-10  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Record loop target
+	symbols in RELAX[_CHECK]_ALIGN_NEXT_OPCODE frags.
+	(xtensa_fix_close_loop_end_frags): Use the recorded values instead of
+	decoding the loop instructions.  Remove current_offset variable.
+	(xtensa_fix_short_loop_frags): Likewise.
+	(min_bytes_to_other_loop_end): Remove current_offset argument.
+
+2006-04-09  Arnold Metselaar  <arnold.metselaar@planet.nl>
 
-2004-04-20  Chris Demetriou  <cgd@broadcom.com>
+	* config/tc-z80.c (z80_optimize_expr): Removed; redundant since 2006-04-04.
+	* config/tc-z80.h (z80_optimize_expr, md_optimize_expr): Removed.
 
-	* NEWS: Note that MIPS -membedded-pic option is deprecated.
+2006-04-07  Joerg Wunsch <j.gnu@uriah.heep.sax.de>
 
-2004-04-19  Eric Christopher  <echristo@redhat.com>
+	* gas/config/tc-avr.c (mcu_types): Add support for attiny261,
+	attiny461, attiny861, attiny25, attiny45, attiny85,attiny24,
+	attiny44, attiny84, at90pwm2, at90pwm3, atmega164, atmega324,
+	atmega644, atmega329, atmega3290, atmega649, atmega6490,
+	atmega406, atmega640, atmega1280, atmega1281, at90can32,
+	at90can64, at90usb646, at90usb647, at90usb1286 and
+	at90usb1287.
+	Move atmega48 and atmega88 from AVR_ISA_M8 to AVR_ISA_PWMx.
 
-	* config/tc-mips.c (mips_dwarf2_addr_size): Revert part
-	of previous patch for fix in gcc.
+2006-04-07  Paul Brook  <paul@codesourcery.com>
 
-2004-04-16  Alan Modra  <amodra@bigpond.net.au>
+	* config/tc-arm.c (parse_operands): Set default error message.
 
-	* expr.c (operand): Correct checks for ++ and --.
+2006-04-07  Paul Brook  <paul@codesourcery.com>
 
-2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+	* config/tc-arm.c (parse_tb): Set inst.error before returning FAIL.
 
-	* doc/c-mips.texi (-m{no-,}fix-vr4120): Renamed from
-	-{no-}mfix-vr4122-bugs.
-	* config/tc-mips.c (mips_fix_vr4120): Renamed from mips_fix_4122_bugs.
-	(append_insn, mips_emit_delays): Update accordingly.
-	(OPTION_FIX_VR4120, OPTION_NO_FIX_VR4120): Renamed from *VR4122.
-	(md_longopts): Change -{no-,}mfix-vr4122-bugs to -m{no-,}fix-vr4120.
-	(md_parse_option): Update after above changes.
-	(md_show_usage): Add -mfix-vr4120.
+2006-04-07  Paul Brook  <paul@codesourcery.com>
 
-2004-04-11  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+	* config/tc-arm.c (md_apply_fix): Set H bit on blx instruction.
 
-	* Makefile.am: Remove mips from aout targets.
+2006-04-07  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (THUMB2_LOAD_BIT): Define.
+	(move_or_literal_pool): Handle Thumb-2 instructions.
+	(do_t_ldst): Call move_or_literal_pool for =N addressing modes.
+
+2006-04-07  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 2512.
+	* config/tc-i386.c (match_template): Move 64-bit operand tests
+	inside loop.
+
+2006-04-06  Carlos O'Donell  <carlos@codesourcery.com>
+
+	* po/Make-in: Add install-html target.
+	* Makefile.am: Add install-html and install-html-recursive targets.
 	* Makefile.in: Regenerate.
-	* configure.in: Remove mips-dec-bsd* target.
+	* configure.in: AC_SUBST datarootdir, docdir, htmldir.
 	* configure: Regenerate.
+	* doc/Makefile.am: Add install-html and install-html-am targets.
+	* doc/Makefile.in: Regenerate.
 
-2004-04-09  Daniel Jacobowitz  <drow@mvista.com>
-
-	Merge from mainline:
-	2004-04-07  Alan Modra  <amodra@bigpond.net.au>
-	PR 96
-	* config/tc-ppc.c (ppc_elf_suffix): Add valid32 and valid64 fields
-	to struct map_bfd.  Adjust MAP macro, and define MAP32, MAP64.
-	Update "mapping".  Restrict some @ modifiers to 32 bit.
-
-	2004-04-01  Asgari Jinia  <asgarij@kpitcummins.com>
-	Dhananjay Deshpande <dhananjayd@kpitcummins.com>
-
-	* config/tc-sh.c (dont_adjust_reloc_32): New variable.
-	(sh_fix_adjustable): Avoid adjusting BFD_RELOC_32 when
-	dont_adjust_reloc_32 is set.
-	(md_longopts): Add option -renesas.
-	(md_parse_option, md_show_usage): Likewise.
-	* doc/c-sh.texi: Likewise.
-
-	2004-04-01  Dave Korn  <dk@artimi.com>
-	* config/tc-dlx.c (md_assemble): set fx_no_overflow flag for
-	hi16 and lo16 fixS structs.
-	(md_assemble): generate bit_fixS for RELOC_DLX_LO16 in
-	exactly the same way as for RELOC_DLX_REL16.
-	(machine_ip): properly respect LO flag in the_insn and
-	output RELOC_DLX_LO16 rather than RELOC_DLX_16.
-	(md_apply_fix3): apply RELOC_DLX_LO16.
-
-	2004-03-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
-	* tc-hppa.c (cons_fix_new_hppa): Check for PC relative base type.
-	(pa_comm): Set BSF_OBJECT in symbol flags.
-
-	2004-03-18  Nathan Sidwell  <nathan@codesourcery.com>
-	* read.c (read_a_source_file): Use demand_empty_rest_of_line.
-	(demand_empty_rest_of_line): Issue an error here.
-	(ignore_rest_of_line): Silently skip to end.
-	(demand_copy_string): Issue an error, not warning.
-	(equals): Likewise.
-	* config/obj-elf.c (obj_elf_section_name): Likewise.
-	(obj_elf_section): Likewise.
-	* config/tc-arc.c (arc_extoper): Remove bogus NULL checks.
-	(arc_extinst): Likewise.
-	* config/tc-ia64.c (dot_saveb): Use demand_empty_rest_of_line.
-	(dot_spill): Likewise.
-	(dot_unwabi): Likewise.
-	(dot_prologue): Likewise.
-
-	2004-03-18  Nathan Sidwell  <nathan@codesourcery.com>
-	* expr.c (operand): Reject ++ and --.
-	(operator): Likewise.
-
-	2004-03-12  Bob Wilson  <bob.wilson@acm.org>
-	* read.c (s_leb128): Call md_flush_pending_output.
-
-	2004-03-07  Andreas Schwab  <schwab@suse.de>
-	* doc/c-hppa.texi (HPPA Directives): Fix typo.
-
-	2004-03-07  Richard Henderson  <rth@redhat.com>
-	* dw2gencfi.c (output_cie): Align length to 4 byte boundary.
-	(cfi_finish): Likewise for fde.
-
-	2004-03-05  H.J. Lu  <hongjiu.lu@intel.com>
-	* config/tc-ia64.c (md_assemble): Properly handle NULL
-	align_frag.
-	(ia64_handle_align): Don't abort if failed to add a stop bit.
-
-	2004-03-04  H.J. Lu  <hongjiu.lu@intel.com>
-	* Makefile.in: Regenerated.
-	* aclocal.m4: Likewise.
-	* configure: Likewise.
-	* doc/Makefile.in: Likewise.
-
-	2004-03-03  H.J. Lu  <hongjiu.lu@intel.com>
-	* config/tc-ia64.c (dot_align): New.
-	(ia64_do_align): Make it static.
-	(md_pseudo_table): Use "dot_align" for "align".
-	(ia64_md_do_align): Don't set align_frag here.
-	(ia64_handle_align): Add a stop bit to the previous bundle if
-	needed.
-
-	* config/tc-ia64.h (ia64_do_align): Removed.
-
-	2004-03-02  H.J. Lu  <hongjiu.lu@intel.com>
-	* config/tc-ia64.c (align_frag): New.
-	(md_assemble): Set the tc_frag_data field in align_frag for
-	IA64_OPCODE_FIRST instructions.
-	(ia64_md_do_align): Set align_frag.
-	(ia64_handle_align): Add a stop bit if needed.
-
-	* config/tc-ia64.h (TC_FRAG_TYPE): New.
-	(TC_FRAG_INIT): New.
-
-	2004-02-27  Nick Clifton  <nickc@redhat.com>
-	* config/tc-sh.c (get_operand): Revert previous delta.
-	(tc_gen_reloc): Check for an unknown reloc type before processing
-	the addend.
-
-	2004-02-27  Hannes Reinecke  <hare@suse.de>
-	* config/tc-s390.c (s390_insn): Correct range check for opcode in
-	.insn pseudo operation.
-
-	2004-02-27  Anil Paranjpe  <anilp1@kpitcummins.com>
-	* config/tc-sh.c (get_operand):  In case of #Imm, check has been
-	added for wrong syntax.
-
-	2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
-	* config/tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
-	nibble types to assembler.
-
-	2004-02-25  Fred Fish  <fnf@redhat.com>
-	* config/tc-iq2000.c: Add missing \n\ in multiline string literal.
-
-	2004-02-20  James E Wilson  <wilson@specifixinc.com>
-	* config/tc-ia64.c (slot_index): New arg before_relax.  Use instead of
-	finalize_syms.
-	(fixup_unw_records): New arg before_relax.  Pass to slot_index.
-	(ia64_estimate_size_before_relax): New.
-	(ia64_convert_frag): Pass 0 to fixup_unw_records.  Add comment.
-	(generate_unwind_image): Pass 1 to fixup_unw_records.
-	* config/tc-ia64.h (ia64_estimate_size_before_relax): Declare.
-	(md_estimate_size_before_relax): Call ia64_estimate_size_before_relax.
-
-	2004-02-19  Jakub Jelinek  <jakub@redhat.com>
-	* stabs.c (generate_asm_file): Avoid warning about use of
-	uninitialized variable.
-
-	2004-02-18  David Mosberger  <davidm@hpl.hp.com>
-	* config/tc-ia64.c (ia64_flush_insns): In addition to prologue,
-	body, and endp, allow unwind records which do not have a "t"
-	(time/instruction) field.
-
-2004-03-22  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (xtensa_post_relax_hook): Create literal
-	tables even when use_literal_section flag is not set.
-
-2004-03-22  Hans-Peter Nilsson  <hp@axis.com>
-
-	* doc/c-cris.texi (CRIS-Opts): Document --no-mul-bug-abort,
-	--mul-bug-abort and the default behavior.
-	* config/tc-cris.c (cris_insn_kind): New member CRIS_INSN_MUL.
-	(err_for_dangerous_mul_placement): New variable.
-	(STATE_MUL, OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): New
-	macros.
-	(md_cris_relax_table): Have placeholder for STATE_MUL.
-	(md_longopts): New options --mul-bug-abort and --no-mul-bug-abort.
-	(cris_relax_frag) <case ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: New
-	case doing nothing.
-	(md_estimate_size_before_relax) <case ENCODE_RELAX (STATE_MUL,
-	STATE_BYTE)>: Ditto.
-	(md_convert_frag) <ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: Check
-	alignment and position of this frag, emit error message if
-	suspicious.
-	(md_assemble): For a multiply insn and when checking it,
-	transform the current frag into a special frag for that purpose.
-	(md_parse_option) <case OPTION_MULBUG_ABORT_OFF, case
-	OPTION_MULBUG_ABORT_ON>: Handle new options.
-
-2004-03-19  Bob Wilson  <bob.wilson@acm.org>
-
-	* config/tc-xtensa.c (mark_literal_frags): New function.
-	(xtensa_move_literals): Call mark_literal_frags for all literal
-	segments, including init and fini literal segments.
-	(xtensa_post_relax_hook): Swap use of xt_insn_sec and xt_literal_sec.
-
-2004-03-17  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
-
-	* config/tc-sh.c: Include dw2gencfi.h.
-	(sh_cfi_frame_initial_instructions): New function.
-	(sh_regname_to_dw2regnum): Likewise.
-	* config/tc-sh.h (DWARF2_LINE_MIN_INSN_LENGTH): Move to the end of
-	file.
-	(TARGET_USE_CFIPOP): Define.
-	(tc_cfi_frame_initial_instructions): Likewise.
-	(tc_regname_to_dw2regnum): Likewise.
-	(DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT): Likewise.
-	* Makefile.am: Update dependencies.
-	* Makefile.in: Regenerate.
+2006-04-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* frags.c (frag_offset_fixed_p): Reinitialise offset before
+	second scan.
+
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
 
-2004-03-17  Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+	* config/tc-sparc.c (sparc_target_format): Handle TE_VXWORKS.
+	(GOTT_BASE, GOTT_INDEX): New.
+	(tc_gen_reloc): Don't alter relocations against GOTT_BASE and
+	GOTT_INDEX when generating VxWorks PIC.
+	* configure.tgt (sparc*-*-vxworks*): Remove this special case;
+	use the generic *-*-vxworks* stanza instead.
 
-	* configure.in: Switch sh-*-rtems* to ELF.  Add sh-*-rtemscoff*.
+2006-04-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 997
+	* frags.c (frag_offset_fixed_p): New function.
+	* frags.h (frag_offset_fixed_p): Declare.
+	* expr.c (expr): Use frag_offset_fixed_p when simplifying subtraction.
+	(resolve_expression): Likewise.
+
+2006-04-03  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (init_op_placement_info_table): Check for formats
+	of the same length but different numbers of slots.
+
+2006-03-30  Andreas Schwab  <schwab@suse.de>
+
+	* configure.in: Fix help string for --enable-targets option.
 	* configure: Regenerate.
 
-2004-03-12  Bob Wilson  <bob.wilson@acm.org>
+2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/config/tc-m68k.c (find_cf_chip): Merge into ...
+	(m68k_ip): ... here.  Use for all chips.  Protect against buffer
+	overrun and avoid excessive copying.
+
+	* config/tc-m68k.c (m68000_control_regs, m68010_control_regs,
+	m68020_control_regs, m68040_control_regs, m68060_control_regs,
+	mcf_control_regs, mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs, mcf5249_control_regs, mcf528x_control_regs,
+	mcfv4e_control_regs, m68010_control_regs): Rename and reorder to ...
+	(m68000_ctrl, m68010_ctrl, m68020_ctrl, m68040_ctrl, m68060_ctrl,
+	mcf_ctrl, mcf5208_ctrl, mcf5213_ctrl, mcf5235_ctrl, mcf5249_ctrl, 
+	mcf5216_ctrl, mcf5250_ctrl, mcf5271_ctrl, mcf5272_ctrl,
+	mcf5282_ctrl, mcfv4e_ctrl): ... these.
+	(mcf5275_ctrl, mcf5329_ctrl, mcf5373_ctrl): New.
+	(struct m68k_cpu): Change chip field to control_regs.
+	(current_chip): Remove.
+	(control_regs): New.
+	(m68k_archs, m68k_extensions): Adjust.
+	(m68k_cpus): Reorder to be in cpu number order.  Adjust.
+	(CPU_ALLOW_MC, CPU_ALLOW_NEGATION): Remove.
+	(find_cf_chip): Reimplement for new organization of cpu table.
+	(select_control_regs): Remove.
+	(mri_chip): Adjust.
+	(struct save_opts): Save control regs, not chip.
+	(s_save, s_restore): Adjust.
+	(m68k_lookup_cpu): Give deprecated warning when necessary.
+	(m68k_init_arch): Adjust.
+	(md_show_usage): Adjust for new cpu table organization.
+
+2006-03-25  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/bfin-defs.h (Expr_Node_Type enum): Add Expr_Node_GOT_Reloc.
+	* config/bfin-lex.l: Recognize GOT17M4 and FUNCDESC_GOT17M4.
+	* config/bfin-parse.y: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(GOT17M4, FUNCDESC_GOT17M4): New tokens of type <value>.
+	(any_gotrel): New rule.
+	(got): Use it, and create Expr_Node_GOT_Reloc nodes.
+	* config/tc-bfin.c: Include "libbfd.h", "elf/common.h" and
+	"elf/bfin.h".
+	(DEFAULT_FLAGS, bfin_flags, bfin_pic_flag): New.
+	(bfin_pic_ptr): New function.
+	(md_pseudo_table): Add it for ".picptr".
+	(OPTION_FDPIC): New macro.
+	(md_longopts): Add -mfdpic.
+	(md_parse_option): Handle it.
+	(md_begin): Set BFD flags.
+	(md_apply_fix3, bfin_fix_adjustable): Handle new relocs.
+	(bfin_gen_ldstidxi): Adjust to match the trees that the parser gives
+	us for GOT relocs.
+	* Makefile.am (bfin-parse.o): Update dependencies.
+	(DEPTC_bfin_elf): Likewise.
+	* Makefile.in: Regenerate.
 
-	* read.c (s_leb128): Call md_flush_pending_output.
+2006-03-25  Richard Sandiford  <richard@codesourcery.com>
 
-2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+	* config/tc-m68k.c (m68k_cpus): Change cpu_cf5208 entries to use
+	mcfemac instead of mcfmac.
 
-	* config/tc-i386.c (output_insn): Handle PadLock instructions.
-	* config/tc-i386.h (CpuPadLock): New define.
-	(CpuUnknownFlags): Added CpuPadLock.
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Mark Mitchell  <mark@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
 
-2004-02-26  Eric Christopher  <echristo@redhat.com>
+	* config/tc-mips.c (mips_target_format): Handle vxworks targets.
+	(md_begin): Complain about -G being used for PIC.  Don't change
+	the text, data and bss alignments on VxWorks.
+	(reloc_needs_lo_p): Don't return true for R_MIPS_GOT16 when
+	generating VxWorks PIC.
+	(load_address): Extend SVR4_PIC handling to VXWORKS_PIC.
+	(macro): Likewise, but do not treat la $25 specially for
+	VxWorks PIC, and do not handle jal.
+	(OPTION_MVXWORKS_PIC): New macro.
+	(md_longopts): Add -mvxworks-pic.
+	(md_parse_option): Don't complain about using PIC and -G together here.
+	Handle OPTION_MVXWORKS_PIC.
+	(md_estimate_size_before_relax): Always use the first relaxation
+	sequence on VxWorks.
+	* config/tc-mips.h (VXWORKS_PIC): New.
 
-	* config/tc-mips.c (mips_dwarf2_addr_size): New.
-	* config/tc-mips.h (DWARF2_ADDR_SIZE): Use.
+2006-03-21  Paul Brook  <paul@codesourcery.com>
 
-2004-02-17  Petko Manolov  <petkan@nucleusys.com>
+	* config/tc-arm.c (md_apply_fix): Fix typo in offset mask.
 
-	* config/tc-arm.c (do_mav_dspsc_1): Correct offset of CRn.
-	(do_mav_dspsc_2): Likewise.
-	Fix accumulator registers move opcodes.
+2006-03-21  Sterling Augustine  <sterling@tensilica.com>
 
-2004-02-13  Hannes Reinecke  <hare@suse.de>
-            Jakub Jelinek  <jakub@redhat.com>
+	* config/tc-xtensa.c (enforce_three_byte_loop_align): New flag.
+	(xtensa_setup_hw_workarounds): Set this new flag for older hardware.
+	(get_loop_align_size): New.
+	(xtensa_end): Skip xtensa_mark_narrow_branches when not aligning.
+	(xtensa_mark_zcl_first_insns): Prevent widening of first loop frag.
+	(get_text_align_power): Rewrite to handle inputs in the range 2-8.
+	(get_noop_aligned_address): Use get_loop_align_size.
+	(get_aligned_diff): Likewise.
 
-	* dwarf2dbg.c (get_filenum): Do not read beyond allocated memory.
+2006-03-21  Paul Brook  <paul@codesourcery.com>
 
-2004-02-10  Steve Ellcey  <sje@cup.hp.com>
+	* config/tc-arm.c (insns): Correct opcodes for ldrbt and strbt.
 
-	* config/tc-ia64.h (ia64_frob_symbol): New declaration.
-	(tc_frob_symbol): New macro definition.
-	* config/tc-ia64.c (ia64_frob_symbol): New routine.
+2006-03-20  Paul Brook  <paul@codesourcery.com>
 
-2004-02-09  Daniel Jacobowitz  <drow@mvista.com>
+	* config/tc-arm.c (BAD_BRANCH, BAD_NOT_IT): Define.
+	(do_t_branch): Encode branches inside IT blocks as unconditional.
+	(do_t_cps): New function.
+	(do_t_blx, do_t_bkpt, do_t_branch23, do_t_bx, do_t_bxj, do_t_cpsi,
+	do_t_czb, do_t_it, do_t_setend, do_t_tb): Add IT constaints.
+	(opcode_lookup): Allow conditional suffixes on all instructions in
+	Thumb mode.
+	(md_assemble): Advance condexec state before checking for errors.
+	(insns): Use do_t_cps.
 
-	* config/tc-arm.c (md_begin): Mark .note.gnu.arm.ident as
-	read-only.
+2006-03-20  Paul Brook  <paul@codesourcery.com>
 
-2004-02-09  Nathan Sidwell  <nathan@codesourcery.com>
+	* config/tc-arm.c (output_relax_insn): Call dwarf2_emit_insn before
+	outputting the insn.
 
-	* read.h (IGNORE_OPCODE_CASE): Do not define. Replace with ...
-	(TC_CASE_SENSITIVE): ... this.
-	* read.c: Replace IGNORE_OPCODE_CASE with TC_CASE_SENSITIVE.
-	* doc/internals.texi (TC_CASE_SENSITIVE): Document.
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
 
-2004-02-06  James E Wilson  <wilson@specifixinc.com>
+	* config/tc-vax.c: Update copyright year.
+	* config/tc-vax.h: Likewise.
 
-	* config/tc-ia64.c (dot_endp): Delete call to output_endp.
-	(generate_unwind_image): Re-add it here.
+2006-03-18  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
 
-2004-02-06  Nathan Sidwell  <nathan@codesourcery.com>
+	* config/tc-vax.c (md_chars_to_number): Used only locally, so
+	make it static.
+	* config/tc-vax.h (md_chars_to_number): Remove obsolete declaration.
 
-	* dwarf2dbg.c (DWARF2_ADDR_SIZE): Remove trailing ';'
-	* read.h (SKIP_WHITESPACE): Turn into an expression.
-	* read.c (read_a_source_file): A pseudo is removed by having a
-	NULL handler.
+2006-03-17  Paul Brook  <paul@codesourcery.com>
 
-2004-02-05  James E Wilson  <wilson@specifixinc.com>
+	* config/tc-arm.c (insns): Add ldm and stm.
 
-	* config/tc-ia64.c (output_endp): New.
-	(count_bits): Delete.
-	(ia64_flush_insns, process_one_record, optimize_unw_records): Handle
-	endp unwind records.
-	(fixup_unw_records): Handle endp unwind records.  Delete code for
-	shortening prologue regions not followed by a body record.
-	(dot_endp): Call add_unwind_entry to emit endp unwind record.
-	* config/tc-ia64.h (unw_record_type): Add endp.
+2006-03-17  Ben Elliston  <bje@au.ibm.com>
 
-2004-02-03  James E Wilson  <wilson@specifixinc.com>
+	PR gas/2446
+	* doc/as.texinfo (Ident): Document this directive more thoroughly.
 
-	* config/tc-ia64.c (ia64_convert_frag): Call md_number_to_chars to
-	fill padding bytes with zeroes.
-	(emit_one_bundle): New locals last_ptr, end_ptr.  Rewrite code that
-	sets unwind_record slot_number and slot_frag fields.
+2006-03-16  Paul Brook  <paul@codesourcery.com>
 
-2004-02-02  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+	* config/tc-arm.c (insns): Add "svc".
 
-	* config/tc-mips.c (add_got_offset_hilo): New function.
-	(macro): Use load_register() and add_got_offset_hilo() to load
-	constants instead of hardcoding code sequences throughout.
+2006-03-13  Bob Wilson  <bob.wilson@acm.org>
 
-2004-01-28  H.J. Lu  <hongjiu.lu@intel.com>
+	* config/tc-xtensa.c (xg_translate_sysreg_op): Remove has_underbar
+	flag and avoid double underscore prefixes.
 
-	* config/tc-ia64.c (emit_one_bundle): Add proper indentation.
+2006-03-10  Paul Brook  <paul@codesourcery.com>
 
-2004-01-26  Bernardo Innocenti  <bernie@develer.com>
+	* config/tc-arm.c (md_begin): Handle EABIv5.
+	(arm_eabis): Add EF_ARM_EABI_VER5.
+	* doc/c-arm.texi: Document -meabi=5.
 
-	* config/tc-m68k.h (EXTERN_FORCE_RELOC): Handle m68k-uclinux specially,
-	like m68k-elf.
-	* config/tc-m68k.c (RELAXABLE_SYMBOL): Use EXTERN_FORCE_RELOC instead
-	of hard-coded test for TARGET_OS=elf.
+2006-03-10  Ben Elliston  <bje@au.ibm.com>
 
-2004-01-24  Chris Demetriou  <cgd@broadcom.com>
+	* app.c (do_scrub_chars): Simplify string handling.
 
-	* config/tc-mips.c (hilo_interlocks): Change definition
-	so that MIPS32, MIPS64 and later ISAs are included, along with
-	the already-included machines.  Update comments.
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+	    Paul Brook  <paul@codesourcery.com>
+	    Ricardo Anguiano  <anguiano@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
 
-2004-01-23  Daniel Jacobowitz  <drow@mvista.com>
+	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
+	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
+	R_ARM_ABS12 reloc.
+	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
+	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
+	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
 
-	* config/tc-arm.c (tc_gen_reloc): Improve error message for
-	undefined local labels.
+2006-03-06  Bob Wilson  <bob.wilson@acm.org>
 
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
+	even when using the text-section-literals option.
 
-	* config/tc-mips.c (load_address, macro): Update comments about
-	NewABI GP relaxation.
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
 
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+	* config/tc-m68k.c (m68k_extensions): Allow 'float' on both m68k
+	and cf.
+	(m68k_ip): <case 'J'> Check we have some control regs.
+	(md_parse_option): Allow raw arch switch.
+	(m68k_init_arch): Better detection of arch/cpu mismatch.  Detect
+	whether 68881 or cfloat was meant by -mfloat.
+	(md_show_usage): Adjust extension display.
+	(m68k_elf_final_processing): Adjust.
 
-	* config/tc-mips.c (macro_build): Remove place and counter arguments.
-	(mips_build_lui, macro_build_ldst_constoffset): Likewise.
-	(mips16_macro_build, macro_build_jalr): Remove counter argument.
-	(set_at, load_register, load_address, move_register): Likewise.
-	(load_got_offset, add_got_offset): Likewise.
-	Update all calls and tidy accordingly.
+2006-03-03  Bjoern Haase  <bjoern.m.haase@web.de>
 
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+	* config/tc-avr.c (avr_mod_hash_value): New function.
+	(md_apply_fix, exp_mod): Use BFD_RELOC_HH8_LDI and
+	BFD_RELOC_MS8_LDI for hlo8() and hhi8() 
+	(md_begin): Set linkrelax variable to 1, use avr_mod_hash_value
+	instead of int avr_ldi_expression: use avr_mod_hash_value instead
+	of (int).
+	(tc_gen_reloc): Handle substractions of symbols, if possible do
+	fixups, abort otherwise.	
+	* config/tc-avr.h (TC_LINKRELAX_FIXUP, TC_VALIDATE_FIX,
+	tc_fix_adjustable): Define.
+	
+2006-03-02  James E Wilson  <wilson@specifix.com>
 
-	* config/tc-mips.c (RELAX_ENCODE): Remove WARN argument.
-	(RELAX_FIRST, RELAX_SECOND): Turn into 8-bit quantities.
-	(RELAX_USE_SECOND): Bump to 0x10000.
-	(RELAX_SECOND_LONGER, RELAX_NOMACRO, RELAX_DELAY_SLOT): New flags.
-	(mips_macro_warning): New variable.
-	(md_assemble): Wrap macro expansion in macro_start() and macro_end().
-	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Likewise.
-	(relax_close_frag): Set mips_macro_warning.first_frag.  Adjust use
-	of RELAX_ENCODE.
-	(append_insn): Update mips_macro_warning.sizes.
-	(macro_start, macro_warning, macro_end): New functions.
-	(macro_build): Don't emit warnings here.
-	(macro_build_lui, md_estimate_size_before_relax): ...or here.
-	(md_convert_frag): Check for cases where one macro alternative
-	needs a warning and the other doesn't.  Emit a warning if the
-	longer sequence was chosen.
-
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
-
-	* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): Remove.
-	* config/tc-mips.c (RELAX_ENCODE): Take three arguments: the size of
-	the first sequence, the size of the second sequence, and a flag
-	that says whether we should warn.
-	(RELAX_OLD, RELAX_NEW, RELAX_RELOC[123]): Delete.
-	(RELAX_FIRST, RELAX_SECOND): New.
-	(mips_relax): New variable.
-	(relax_close_frag, relax_start, relax_switch, relax_end): New fns.
-	(append_insn): Remove "place" argument.  Use mips_relax.sequence
-	rather than "place" to check whether we're expanding the second
-	alternative of a relaxable macro.  Remove redundant check for
-	branch relaxation.  If generating a normal insn, and there
-	is not enough room in the current frag, call relax_close_frag()
-	to close it.  Update mips_relax.sizes[].  Emit fixups for the
-	second version of a relaxable macro.  Record the first relaxable
-	fixup in mips_relax.  Remove tc_gen_reloc workaround.
-	(macro_build): Remove all uses of "place".  Use mips_relax.sequence
-	in the same way as in append_insn.
-	(mips16_macro_build): Remove "place" argument.
-	(macro_build_lui): As for macro_build.  Don't drop the add_symbol
-	when generating the second version of a relaxable macro.
-	(load_got_offset, add_got_offset): New functions.
-	(load_address, macro): Use new relaxation machinery.  Remove
-	tc_gen_reloc workarounds.
-	(md_estimate_size_before_relax): Set RELAX_USE_SECOND if the second
-	version of a relaxable macro is needed.  Return -RELAX_SECOND if the
-	first version is needed.
-	(tc_gen_reloc): Remove relaxation handling.
-	(md_convert_frag): Go through the fixups for a relaxable macro and
-	mark those that belong to the unneeded alternative as done.  If the
-	second alternative is needed, adjust the fixup addresses to account
-	for the deleted first alternative.
-
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
-
-	* frags.h (frag_room): Declare.
-	* frags.c (frag_room): New function.
-	* doc/internals.texi: Document it.
-
-2004-01-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
-
-	* config/tc-mips.c (append_insn): Don't do r3900 interlock
-	optimization for -mtune=r3900, as this will break on other CPUs.
-
-2004-01-11  Tom Rix   <tcrix@worldnet.att.net>
-
-	* config/tc-m68hc11.c (build_indexed_byte): movb and movw cannot
-	be relaxed, use fixup.
-	(md_apply_fix3): Use 5 bit reloc from movb and movw fixup.
-
-2004-01-19  Jakub Jelinek  <jakub@redhat.com>
-
-	* config/tc-sparc.c (sparc_ip): Disallow %f32-%f63 for single
-	precision operands.
-
-2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
-
-	* config/tc-mips.c (append_insn): Properly detect variant frags
-	that preclude swapping of relaxed branches.  Correctly swap
-	instructions between frags when dealing with relaxed branches.
-
-2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
-
-	* acinclude.m4: Quote names of macros to be defined by AC_DEFUN
-	throughout.
-	* aclocal.m4: Regenerate.
-	* configure: Regenerate.
+	* config/tc-ia64.c (emit_one_bundle): For IA64_OPCODE_LAST, if we
+	change the template, then clear md.slot[curr].end_of_insn_group.
 
-2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
 
-	* config/tc-h8300.c (build_bytes): Apply relaxation to bit
-	manipulation insns.
+	* macro.c (get_any_string): Don't insert quotes for <>-quoted input.
 
-2004-01-12  Richard Sandiford  <rsandifo@redhat.com>
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
 
-	* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR
-	reloc, reserve space for the delay slot as well as the jalr itself.
+	PR/1070
+	* macro.c (getstring): Don't treat parentheses special anymore.
+	(get_any_string): Don't consider '(' and ')' as quoting anymore.
+	Special-case '(', ')', '[', and ']' when dealing with non-quoting
+	characters.
 
-2004-01-09  Paul Brook  <paul@codesourcery.com>
+2006-02-28  Mat <mat@csail.mit.edu>
 
-	* config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from do_vfp_sp_reg2.
-	(do_vfp_sp2_from_reg2): New function.
-	(insns): Use them.
-	(do_vfp_dp_from_reg2): Check return values properly.
-
-2004-01-08  Ian Lance Taylor  <ian@wasabisystems.com>
-
-	* config/tc-mips.c (warn_nops): Remove static variable.
-	(macro): Remove test of warn_nops.
-	(md_shortops): Remove 'n'.
-	(md_parse_option): Remove 'n' case.
-	(md_show_usage): Remove -n.
-	* doc/as.texinfo (Overview): Remove MIPS -n option.
-	* doc/c-mips.texi (MIPS Opts): Remove mention -n.
-	* NEWS: Mention removal of MIPS -n option.
-
-	* config/tc-mips.c (ISA_HAS_COPROC_DELAYS): Remove.
-	(cop_interlocks): Check ISA level.
-	(cop_mem_interlocks): Define.
-	(reg_needs_delay): Check cop_interlocks rather than
-	ISA_HAS_COPROC_DELAYS.
-	(append_insn): Likewise.  Use cop_mem_interlocks rather than
-	directly checking mips_opts.isa.
-	(mips_emit_delays): Likewise.
-
-2004-01-07  H.J. Lu  <hongjiu.lu@intel.com>
-
-	* config/tc-ia64.c (unwind): Move next_slot_number and
-	next_slot_frag to ...
-	(unw_rec_list): Here.
-	(free_list_records): Removed.
-	(output_unw_records): Likewise.
-	(generate_unwind_image): Make it void.
-	(alloc_record): Initialize next_slot_number and next_slot_frag.
-	(slot_index): Take .org, .space and .align into account.
-	(fixup_unw_records): Don't set slot_number to 0. Use
-	list->next_slot_number and list->next_slot_frag instead of
-	unwind.next_slot_number and unwind.next_slot_frag.
-	(ia64_convert_frag): New.
-	(generate_unwind_image): Generate a rs_machine_dependent frag
-	for unwind record.
-	(emit_one_bundle): Use list->next_slot_number and
-	list->next_slot_frag instead of unwind.next_slot_number and
-	unwind.next_slot_frag.
-
-	* config/tc-ia64.h (md_convert_frag): Defined as
-	ia64_convert_frag.
-	(md_estimate_size_before_relax): Defined as (f)->fr_var.
-
-2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
-
-	2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
-	* config/tc-frv.h (md_apply_fix3): Don't define.
-	* config/tc-frv.c (md_apply_fix3): New.  Shift/truncate %hi/%lo
-	operands.
-	* config/tc-frv.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
-	2003-10-07  Alexandre Oliva  <aoliva@redhat.com>
-	* config/tc-frv.c (line_separator_chars): Add `!'.
-	2003-09-19  Alexandre Oliva  <aoliva@redhat.com>
-	* config/tc-frv.c (md_assemble): Clear insn upfront.
-	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
-	* config/tc-frv.c (OPTION_FDPIC): New macro.
-	(md_longopts): Add mfdpic.
-	(md_parse_option): Handle it.
-	2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
-	* config/tc-frv.c (md_cgen_lookup_reloc) <FRV_OPERAND_D12,
-	FRV_OPERAND_S12>: Use reloc type encoded in fix-up.
-	(frv_pic_ptr): Parse funcdesc.
+	* dwarf2dbg.c (get_filenum): Don't inadvertently decrease files_in_use.
 
-2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+2006-02-27  Jakub Jelinek  <jakub@redhat.com>
 
-	* doc/as.texinfo: Let texi2pod parse asconfig.texi and
-	gasver.texi.  Remove duplicate symbol definitions for texi2pod.
+	* dw2gencfi.c (struct fde_entry, struct cie_entry): Add signal_frame
+	field.
+	(CFI_signal_frame): Define.
+	(cfi_pseudo_table): Add .cfi_signal_frame.
+	(dot_cfi): Handle CFI_signal_frame.
+	(output_cie): Handle cie->signal_frame.
+	(select_cie_for_fde): Don't share CIE if signal_frame flag is
+	different.  Copy signal_frame from FDE to newly created CIE.
+	* doc/as.texinfo: Document .cfi_signal_frame.
 
-2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+2006-02-27  Carlos O'Donell  <carlos@codesourcery.com>
 
-	* Makefile.am (Makefile): Move the dependency on
-	$(BFDDIR)/configure.in to...
-	(CONFIG_STATUS_DEPENDENCIES): ... here.
-	(AUTOMAKE_OPTIONS): Require automake 1.8.
-	* Makefile.in: Regenerate.
-	* doc/Makefile.am (BASEDIR, BFDDIR): Define.
-	(CONFIG_STATUS_DEPENDENCIES): Add a dependency on
-	$(BFDDIR)/configure.in here as well.
+	* doc/Makefile.am: Add html target.
 	* doc/Makefile.in: Regenerate.
+	* po/Make-in: Add html target.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (output_insn): Support Intel Merom New
+	Instructions.
+
+	* config/tc-i386.h (CpuMNI): New.
+	(CpuUnknownFlags): Add CpuMNI.
+
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+	* config/tc-sparc.c (priv_reg_table): Add entry for "gl".
+	(hpriv_reg_table): New table for hyperprivileged registers.
+	(sparc_ip): New cases '$' and '%' for wrhpr/rdhpr hyperprivileged
+	register encoding.
+
+2006-02-24  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.h (md_apply_fix): Define to m32c_apply_fix.
+	(tc_gen_reloc): Don't define.
+	* config/tc-m32c.c (rl_for, relaxable): New convenience macros.
+	(OPTION_LINKRELAX): New.
+	(md_longopts): Add it.
+	(m32c_relax): New.
+	(md_parse_options): Set it.
+	(md_assemble): Emit relaxation relocs as needed.
+	(md_convert_frag): Emit relaxation relocs as needed.
+	(md_cgen_lookup_reloc): Add LAB_8_8 and LAB_8_16.
+	(m32c_apply_fix): New.
+	(tc_gen_reloc): New.
+	(m32c_force_relocation): Force out jump relocs when relaxing.
+	(m32c_fix_adjustable): Return false if relaxing.
+
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* config/arm/tc-arm.c (arm_ext_v6_notm, arm_ext_div, arm_ext_v7,
+	arm_ext_v7a, arm_ext_v7r, arm_ext_v7m): New variables.
+	(struct asm_barrier_opt): Define.
+	(arm_v7m_psr_hsh, arm_barrier_opt_hsh): New variables.
+	(parse_psr): Accept V7M psr names.
+	(parse_barrier): New function.
+	(enum operand_parse_code): Add OP_oBARRIER.
+	(parse_operands): Implement OP_oBARRIER.
+	(do_barrier): New function.
+	(do_dbg, do_pli, do_t_barrier, do_t_dbg, do_t_div): New functions.
+	(do_t_cpsi): Add V7M restrictions.
+	(do_t_mrs, do_t_msr): Validate V7M variants.
+	(md_assemble): Check for NULL variants.
+	(v7m_psrs, barrier_opt_names): New tables.
+	(insns): Add V7 instructions.  Mark V6 instructions absent from V7M.
+	(md_begin): Initialize arm_v7m_psr_hsh and arm_barrier_opt_hsh.
+	(arm_cpu_option_table): Add Cortex-M3, R4 and A8.
+	(arm_arch_option_table): Add armv7, armv7a, armv7r and armv7m.
+	(struct cpu_arch_ver_table): Define.
+	(cpu_arch_ver): New.
+	(aeabi_set_public_attributes): Use cpu_arch_ver.  Set
+	Tag_CPU_arch_profile.
+	* doc/c-arm.texi: Document new cpu and arch options.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (operand_match): Handle IA64_OPND_IMMU5b.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c: Update copyright years.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (specify_resource): Add the rule 17 from
+	SDM 2.2.
+
+2005-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_pld): Remove incorrect write to
+	inst.instruction.
+	(encode_thumb32_addr_mode): Use correct operand.
+
+2006-02-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Fix off-by-one errors.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* Makefile.am: Add xc16x related entry.
+	* Makefile.in: Regenerate.
+	* configure.in: Added xc16x related entry.
+	* configure: Regenerate.
+	* config/tc-xc16x.h: New file
+	* config/tc-xc16x.c: New file
+	* doc/c-xc16x.texi: New file for xc16x
+	* doc/all.texi: Entry for xc16x
+	* doc/Makefile.texi: Added c-xc16x.texi 
+	* NEWS: Announce the support for the new target.
 
-2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+2006-02-16  Nick Hudson  <nick.hudson@dsl.pipex.com>
 
-	* Makefile.am (install, install-info, RECURSIVE_TARGETS): Remove.
-	* Makefile.in: Regenerate.
-	* aclocal.m4: Regenerate.
-	* doc/Makefile.am (install, install-info): Remove.
-	(install-data-local): A new hook for install-info.
-	(AUTOMAKE_OPTIONS): Require automake 1.8.
-	* doc/Makefile.in: Regenerate.
+	* configure.tgt: set emulation for mips-*-netbsd*
 
-2004-01-02  Nutan Singh <nutan@kpitcummins.com>
+2006-02-14  Jakub Jelinek  <jakub@redhat.com>
 
-	* doc/c-sh.texi: Update description about floating point behavior
-	of SH family.
+	* config.in: Rebuilt.
 
-2004-01-02  Bernardo Innocenti  <bernie@develer.com>
+2006-02-13  Bob Wilson  <bob.wilson@acm.org>
 
-	* configure.in: Add m68k-uClinux target.
-	* configure: Regenerate.
+	* config/tc-xtensa.c (xg_add_opcode_fix): Number operands starting
+	from 1, not 0, in error messages.
+	(md_assemble): Simplify special-case check for ENTRY instructions.
+	(tinsn_has_invalid_symbolic_operands): Do not include opcode and
+	operand in error message.
+
+2006-02-13  Joseph S. Myers  <joseph@codesourcery.com>
 
-For older changes see ChangeLog-0203
+	* configure.tgt (arm-*-linux-gnueabi*): Change to
+	arm-*-linux-*eabi*.
+
+2006-02-10  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-crx.c (check_range): Ensure that the sign bit of a
+	32-bit value is propagated into the upper bits of a 64-bit long.
+
+	* config/tc-arc.c (init_opcode_tables): Fix cast.
+	(arc_extoper, md_operand): Likewise.
+
+2006-02-09  David Heine  <dlheine@tensilica.com>
+
+	* config/tc-xtensa.c (xg_assembly_relax): Increment steps_taken for
+	each relaxation step.
+
+2006-02-09  Eric Botcazou  <ebotcazou@libertysurf.fr>
+	
+	* configure.in (CHECK_DECLS): Add vsnprintf.
+	* configure: Regenerate.
+	* messages.c (errno.h, stdarg.h, varargs.h, va_list): Do not
+	include/declare here, but...
+	* as.h: Move code detecting VARARGS idiom to the top.
+	(errno.h, stdarg.h, varargs.h, va_list): ...here.
+	(vsnprintf): Declare if not already declared.
+
+2006-02-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* as.c (close_output_file): New.
+	(main): Register close_output_file with xatexit before
+	dump_statistics. Don't call output_file_close.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-m68k.c (mcf5208_control_regs, mcf5213_control_regs,
+	mcf5329_control_regs): New.
+	(not_current_architecture, selected_arch, selected_cpu): New.
+	(m68k_archs, m68k_extensions): New.
+	(archs): Renamed to ...
+	(m68k_cpus): ... here.  Adjust.
+	(n_arches): Remove.
+	(md_pseudo_table): Add arch and cpu directives.
+	(find_cf_chip, m68k_ip): Adjust table scanning.
+	(no_68851, no_68881): Remove.
+	(md_assemble): Lazily initialize.
+	(select_control_regs): Adjust cpu names. Add 5208, 5213, 5329.
+	(md_init_after_args): Move functionality to m68k_init_arch.
+	(mri_chip): Adjust table scanning.
+	(md_parse_option): Reimplement 'm' processing to add -march & -mcpu
+	options with saner parsing.
+	(m68k_lookup_cpu, m68k_set_arch, m68k_set_cpu, m68k_set_extension,
+	m68k_init_arch): New.
+	(s_m68k_cpu, s_m68k_arch): New.
+	(md_show_usage): Adjust.
+	(m68k_elf_final_processing): Set CF EF flags.
+	* config/tc-m68k.h (m68k_init_after_args): Remove.
+	(tc_init_after_args): Remove.
+	* doc/c-m68k.texi (M68K-Opts): Document -march, -mcpu options.
+	(M68k-Directives): Document .arch and .cpu directives.
+
+2006-02-05  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* config/tc-z80.c (z80_start_line_hook): allow .equ and .defl as 
+	synonyms for equ and defl. 
+	(z80_cons_fix_new): New function.
+	(emit_byte): Disallow relative jumps to absolute locations.
+	(emit_data): Only handle defb, prototype changed, because defb is 
+	now handled as pseudo-op rather than an instruction.
+	(instab): Entries for defb,defw,db,dw moved from here...
+	(md_pseudo_table): ... to here, use generic cons() for defw,dw. 
+	Add entries for def24,def32,d24,d32.
+	(md_assemble): Improved error handling.
+	(md_apply_fix): New case BFD_RELOC_24, set fixP->fx_no_overflow to one.
+	* config/tc-z80.h (TC_CONS_FIX_NEW): Define.
+	(z80_cons_fix_new): Declare.
+	* doc/c-z80.texi (defb, db): Mention warning on overflow. 
+	(def24,d24,def32,d32): New pseudo-ops.
+	
+2006-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_shift): Remove Thumb-1 constraint.
+
+2005-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T2_OPCODE_MASK, T2_DATA_OP_SHIFT, T2_OPCODE_AND,
+	T2_OPCODE_BIC, T2_OPCODE_ORR, T2_OPCODE_ORN, T2_OPCODE_EOR,
+	T2_OPCODE_ADD, T2_OPCODE_ADC, T2_OPCODE_SBC, T2_OPCODE_SUB,
+	T2_OPCODE_RSB): Define.
+	(thumb32_negate_data_op): New function.
+	(md_apply_fix): Use it.
+
+2006-01-31  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (TInsn): Remove record_fix and sub_symbol
+	fields.
+	* config/tc-xtensa.h (xtensa_frag_type): Remove slot_sub_symbols field.
+	* config/tc-xtensa.c (md_apply_fix): Check for unexpected uses of
+	subtracted symbols.
+	(relaxation_requirements): Add pfinish_frag argument and use it to
+	replace setting tinsn->record_fix fields.
+	(xg_assemble_vliw_tokens): Adjust calls to relaxation_requirements
+	and vinsn_to_insnbuf.  Remove references to record_fix and
+	slot_sub_symbols fields.
+	(xtensa_mark_narrow_branches): Delete unused code.
+	(is_narrow_branch_guaranteed_in_range): Handle expr that is not just
+	a symbol.
+	(convert_frag_immed): Adjust vinsn_to_insnbuf call and do not set
+	record_fix fields.
+	(tinsn_immed_from_frag): Remove code for handling slot_sub_symbols.
+	(vinsn_to_insnbuf): Change use of record_fixup argument, replacing use
+	of the record_fix field.  Simplify error messages for unexpected
+	symbolic operands.
+	(set_expr_symbol_offset_diff): Delete.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_reg_parse): Check if reg is non-NULL.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+	Richard Earnshaw <rearnsha@arm.com>
+
+	* config/tc-arm.c: Use arm_feature_set.
+	(arm_ext_*, arm_arch_full, arm_arch_t2, arm_arch_none,
+	arm_cext_iwmmxt, arm_cext_xscale, arm_cext_maverick, fpu_fpa_ext_v1,
+	fpu_fpa_ext_v2, fpu_vfp_ext_v1xd, fpu_vfp_ext_v1, fpu_vfp_ext_v2):
+	New variables.
+	(insns): Use them.
+	(md_atof, opcode_select, opcode_select, md_assemble, md_assemble,
+	md_begin, arm_parse_extension, arm_parse_cpu, arm_parse_arch,
+	arm_parse_fpu, arm_parse_float_abi, aeabi_set_public_attributes,
+	s_arm_cpu, s_arm_arch, s_arm_fpu): Use macros for accessing CPU
+	feature flags.
+	(arm_legacy_option_table, arm_option_cpu_value_table): New types.
+	(arm_opts): Move old cpu/arch options from here...
+	(arm_legacy_opts): ... to here.
+	(md_parse_option): Search arm_legacy_opts.
+	(arm_cpus, arm_archs, arm_extensions, arm_fpus)
+	(arm_float_abis, arm_eabis): Make const.
+
+2006-01-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (md_apply_fix): Set value to zero for PLT relocs.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (asm_1): Check value range for 16 bit immediate
+	in load immediate intruction.
+
+2006-01-21  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-parse.y (value_match): Use correct conversion
+	specifications in template string for __FILE__ and __LINE__.
+	(binary): Ditto.
+	(unary): Ditto.
+
+2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce TLS descriptors for i386 and x86_64.
+	* config/tc-i386.c (tc_i386_fix_adjustable): Handle
+	BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_386_TLS_DESC_CALL,
+	BFD_RELOC_X86_64_GOTPC32_TLSDESC, BFD_RELOC_X86_64_TLSDESC_CALL.
+	(optimize_disp): Emit fix up for BFD_RELOC_386_TLS_DESC_CALL and
+	BFD_RELOC_X86_64_TLSDESC_CALL immediately, and clear the
+	displacement bits.
+	(build_modrm_byte): Set up zero modrm for TLS desc calls.
+	(lex_got): Handle @tlsdesc and @tlscall.
+	(md_apply_fix, tc_gen_reloc): Handle the new relocations.
+
+2006-01-11  Nick Clifton  <nickc@redhat.com>
+
+	Fixes for building on 64-bit hosts:
+	* config/tc-avr.c (mod_index): New union to allow conversion
+	between pointers and integers.
+	(md_begin, avr_ldi_expression): Use it.
+	* config/tc-i370.c (md_assemble): Add cast for argument to print
+	statement.
+	* config/tc-tic54x.c (subsym_substitute): Likewise.
+	* config/tc-mn10200.c (md_assemble): Use a union to convert the
+	opindex field of fr_cgen structure into a pointer so that it can
+	be stored in a frag.
+	* config/tc-mn10300.c (md_assemble): Likewise.
+	* config/tc-frv.c (frv_debug_tomcat): Use %p to print pointer
+	types.
+	* config/tc-v850.c: Replace uses of (int) casts with correct
+	types.
+
+2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2117
+	* symbols.c (snapshot_symbol): Don't change a defined symbol.
+
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR gas/2101
+	* config/tc-mmix.c (mmix_handle_mmixal): Don't treat #[0-9][FB] as
+	a local-label reference.
+
+For older changes see ChangeLog-2005
 
 Local Variables:
 mode: change-log
diff --git a/gas/ChangeLog-0001 b/gas/ChangeLog-0001
index 9d8af6fbe897..b1208c4d78c3 100644
--- a/gas/ChangeLog-0001
+++ b/gas/ChangeLog-0001
@@ -8,8 +8,8 @@
 
 2001-12-31  Jeffrey A Law  (law@redhat.com)
 
-        * config/tc-hppa.c (pa_ip): Handle new 'c' mode completers,
-        'X', 'M', and 'A'.
+	* config/tc-hppa.c (pa_ip): Handle new 'c' mode completers,
+	'X', 'M', and 'A'.
 
 2001-12-21  Jakub Jelinek  <jakub@redhat.com>
 
@@ -7701,3 +7701,10 @@
 	pseudo ops.
 
 For older changes see ChangeLog-9899
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/ChangeLog-0203 b/gas/ChangeLog-0203
index e22a5d5f2d55..63be7bf391f5 100644
--- a/gas/ChangeLog-0203
+++ b/gas/ChangeLog-0203
@@ -14,7 +14,7 @@
 	.byte directive generates a pc-relative relocation.
 
 2003-12-19  Nick Clifton  <nickc@redhat.com>
-            Andreas Schwab  <schwab@suse.de>
+	    Andreas Schwab  <schwab@suse.de>
 
 	* messages.c (as_perror): Save errno around library calls.
 	* input-file.c [BFD_ASSEMBLER]: Set the BFD error to
@@ -29,15 +29,15 @@
 
 2003-12-19  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
 
-        Add m32r-linux and PIC support.  Add new ABI that uses RELA.
-        * configure.in: Add m32r-linux targets.
+	Add m32r-linux and PIC support.  Add new ABI that uses RELA.
+	* configure.in: Add m32r-linux targets.
 	* configure: Regenerate.
-        * config/tc-m32r.c (md_parse_option): Add -KPIC option.
-        (tc_gen_reloc): Added.
-        (debug_sym, md_estimate_size_before_relax, md_convert_frag,
-        md_pcrel_from_section, m32r_fix_adjustable): Changed for PIC.
-        * config/tc-m32r.h (tc_gen_reloc, EXTERN_FORCE_RELOC): Undefined.
-        (TC_HANDLES_FX_DONE, TC_FIX_ADJUSTABLE, TC_RELOC_RTSYM_LOC_FIXUP):
+	* config/tc-m32r.c (md_parse_option): Add -KPIC option.
+	(tc_gen_reloc): Added.
+	(debug_sym, md_estimate_size_before_relax, md_convert_frag,
+	md_pcrel_from_section, m32r_fix_adjustable): Changed for PIC.
+	* config/tc-m32r.h (tc_gen_reloc, EXTERN_FORCE_RELOC): Undefined.
+	(TC_HANDLES_FX_DONE, TC_FIX_ADJUSTABLE, TC_RELOC_RTSYM_LOC_FIXUP):
 	Defined.
 	* doc/c-m32r.texi: Document -KPIC option.
 	* NEWS: Mention the support m32r Linux and PIC.
@@ -68,17 +68,17 @@
 2003-12-17  Nick Clifton  <nickc@redhat.com>
 
 	* config/tc-m32r.c (error_explicit_parallel_conflicts): Rename
-        to 'ignore_parallel_conflicts'.
-        (md_longopts): Change option names as well.
-        (md_parse_option): Separate the	warn_explicit and ignore
-        parallel conflicts options.
-        (md_show_usage): Update descriptions of these options.
-        (first_writes_to_seconds_operands): Do not run this check if
-        ignoring parallel conflicts.
-        (assemble_two_insns): Remove code that checked
-        error_explicit_parallel_conflicts.
-        * doc/c-m32r.texi: Update descriptions of the options.
-        
+	to 'ignore_parallel_conflicts'.
+	(md_longopts): Change option names as well.
+	(md_parse_option): Separate the warn_explicit and ignore
+	parallel conflicts options.
+	(md_show_usage): Update descriptions of these options.
+	(first_writes_to_seconds_operands): Do not run this check if
+	ignoring parallel conflicts.
+	(assemble_two_insns): Remove code that checked
+	error_explicit_parallel_conflicts.
+	* doc/c-m32r.texi: Update descriptions of the options.
+
 2003-12-16  Dmitry Semyonov  <Dmitry.Semyonov@oktet.ru>
 
 	* tc-arm.c (do_adr): Do not adjust pc by -8 if TE_WINCE is
diff --git a/gas/ChangeLog-2004 b/gas/ChangeLog-2004
new file mode 100644
index 000000000000..f4592ca98a7f
--- /dev/null
+++ b/gas/ChangeLog-2004
@@ -0,0 +1,2687 @@
+2004-12-29  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/619
+	* read.c (s_comm_internal): Don't zero end of name until size
+	expression has been parsed.
+
+2004-12-25  Marek Michalkiewicz  <marekm@amelek.gda.pl>
+
+	* config/tc-avr.c (mcu_types): Move attiny{13,2313} from avr4 to avr2.
+
+2004-12-23  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c: Support 'bcop' relaxation (dealt as in 'cmp&branch'
+	case).
+
+2004-12-22  Ian Lance Taylor  <ian@airs.com>
+
+	* configure.tgt: New.
+	* configure.in: Move setting of cpu_type, fmt, etc., to
+	configure.tgt.
+	* Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add
+	$(srcdir)/configure.tgt.
+	* configure, Makefile.in: Rebuild.
+
+2004-12-22  Klaus Rudolph  <lts-rudolph@gmx.de>
+
+	* config/tc-avr.c: Add support for the new R_AVR_LDI, R_AVR_6 and
+	R_AVR_6_ADIW relocs for the LDI, ADIW/SBIW and LDD/STD
+	instructions.
+	(avr_offset_expression): New function to parse offsets for LDI
+	instructions.
+	(avr_operand): Use it.
+	(md_apply_fix3): Generate the relocs.
+
+2004-12-16  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* config/tc-sh64.c (shmedia_md_apply_fix3): Add missing
+	BFD_RELOC_SH_IMMS10BY8 relocation.
+
+	* config/tc-sh64.c (shmedia_build_Mytes): Emit an error message rather
+	than just ignoring bad code.
+
+2004-12-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-v850.c (handle_lo16): New function.
+	(v850_reloc_prefix): Use it to check lo().
+	(md_assemble, md_apply_fix3): Handle BFD_RELOC_V850_LO16_SPLIT_OFFSET.
+
+2004-12-14  P.J. Darcy  <darcypj@us.ibm.com>
+
+	* configure.in: Add s390x-ibm-tpf support.
+	* configure: Regenerate.
+
+2004-12-15 Jan Beulich  <jbeulich@novell.com>
+
+	* config/obj-elf.c (obj_elf_change_section): Only set type and
+	attributes on new sections. Emit warning when type of re-declared
+	section doesn't match.
+
+2004-12-15 Jan Beulich  <jbeulich@novell.com>
+
+	* dw2gencfi.c (dot.cfi.startproc): Clear cur_cfa_offset so
+	'.cfi_startproc simple' doesn't inherit the old value.
+
+2004-12-15  Jan Beulich  <jbeulich@novell.com>
+
+	* dw2gencfi.c (output_cfi_insn): Adjust DW_CFA_def_cfa_sf generation
+	to emit a signed and factored offset. Adjust DW_CFA_def_cfa_offset_sf
+	generation to emit a factored offset.
+
+2004-12-10  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* config/tc-mips.c (macro) [M_LA_AB]: Give an error for a offset
+	which is too large in the case of NO_PIC without 64-bit
+	addresses.
+
+	* config/tc-mips.c (mips_in_shared): New static variable.
+	(macro_build_lui): Permit "_gp" if !mips_in_shared.
+	(md_longopts): Add -mshared and -mno-shared.
+	(md_parse_option): Handle OPTION_MSHARED and OPTION_MNO_SHARED.
+	(s_cpload): Implement !mips_in_shared case.
+	(s_cpsetup): Likewise.
+	* doc/c-mips.texi (MIPS Opts): Document -mno-shared.
+	* NEWS: Mention -mno-shared.
+
+2004-12-09  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_fnend): Use R_ARM_PREL31 relocation
+	for function start.
+
+2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* config/tc-mips.c (append_insn): If we emit a nop during a relax
+	sequence, increase the size of the sequence.
+
+	* config/tc-mips.c (mips_cpu_info_table): Change "9000" entry to
+	use CPU_RM9000.
+
+2004-12-07  Ben Elliston  <bje@gnu.org>
+
+	* read.c (s_align): Use an align_limit temporary to allay a GCC
+	signed/unsigned comparison warning.
+
+2004-12-01  Mark Mitchell  <mark@codesourcery.com>
+
+	* Makefile.am (TARG_ENV_HFILES): Add te-armlinuxeabi.h.
+	* configure.in: Use it for arm*-*-linux-gnueabi*.
+	* config/tc-arm.c: Allow emulation file to set FPU_DEFAULT.
+	* config/te-armlinuxeabi.h: New file.
+	* Makefile.in: Regenerated.
+	* aclocal.m4: Likewise.
+	* configure: Likewise.
+	* doc/Makefile.in: Regenerated.
+
+2004-12-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_switch_section_emit_state): Use subseg_set.
+	(xtensa_restore_emit_state): Likewise.
+
+2004-12-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (ALIGN_LIMIT): Define, increasing limit for BFD_ASSEMBLER.
+	(s_align): Use it.
+
+2004-11-30  Tero Niemela  <tero_niemela@yahoo.com>
+
+	* Makefile.am: Change LOCALEDIR to $(datadir)/share.
+	* Makefile.in: Regenerate.
+
+2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c: Major code cleanup. Remove unused variables and
+	functions, give functions a meaningful name, add comments.
+	(check_range): New function - Replace operand size calculation
+	with range checking.
+	(assemble_insn): Update Algorithm, improve error issuing.
+	(enum op_err): New.
+	(process_label_constant): Bug fix regarding COP_BRANCH_INS relocation
+	handling.
+
+2004-11-29  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (md_pcrel_from_section): Fixed a pcrel relocte
+	miss between different section in the same module.
+	(tc_gen_reloc): Likewise.
+
+2004-11-25  Theodore A. Roth  <troth@openavr.org>
+
+	* gas/config/tc-avr.c (mcu_types): Add support for atmega165,
+	atmega325, atmega3250, atmega645 and atmega6450.
+
+2004-11-25 Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (optimize_imm): Adjust immediates to only those
+	permissible for the selected instruction suffix.
+	(process_suffix): For DefaultSize instructions, suppressing the
+	guessing of a 'q' suffix if the instruction doesn't support it is
+	pointless, because only an 'l' suffix can be guessed in this place.
+
+2004-11-24  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-iq2000.c: Remove support for IQ10 processor.
+	Convert to ISO C90 formatting.
+	* config/tc-iq2000.h: Likewise.
+
+2004-11-23  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-mn10300.c (md_relax_table): More fixes to the offsets
+	in this table.  They should be correct now.
+
+2004-11-23 Jan Beulich <jbeulich@novell.com>
+
+	* config/tc-i386.h (CpuMMX2): Declare. Artificial classifier to
+	indicate the MMX extensions added by both SSE and 3DNow!A.
+	(Cpu3dnowA): Declare.
+	(CpuUnknownFlags): Update.
+	* config/tc-i386.c (cpu_sub_arch_name): Declare.
+	(cpu_arch): i586 and pentium do not imply MMX. i686 and pentiumpro do
+	neither imply SSE nor MMX. k6 implies MMX. k6_2 additionally implies
+	3DNow!. Athlon additionally implies 3DNow!A. Several new
+	entries (those starting with a dot are for sub-arch specification).
+	(set_cpu_arch): Handle sub-arch specifications.
+	(parse_insn): Distinguish between instructions not supported because
+	of insufficient CPU features and because of 64-bit mode.
+	* doc/c-i386.texi: Describe enhanced .arch directive.
+
+2004-11-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_add_opcode_fix): Set fx_no_overflow.
+
+2004-11-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* dwarf2dbg.c (dwarf2_finish): Don't write a .debug_line section
+	without a corresponding .debug_info section.
+
+2004-11-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* read.c (potable): Add "error" and "warning".
+	(s_errwarn): New function.
+	* read.h (s_errwarn): Declare.
+	* doc/as.texinfo (Error, Warning): Document .error and .warning.
+
+2004-11-22  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-tic54x.c (tic54x_adjust_symtab): Adjust call to
+	c_dot_file_symbol.
+
+2004-11-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-msp430.c (struct rcodes_s, MSP430_RLC, msp430_rcodes,
+	struct hcodes_s, msp430_hcodes): From include/opcode/msp430.h.
+
+2004-11-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-coff.c (c_dot_file_symbol): Add "app" param.
+	(coff_adjust_symtab): Adjust call.
+	(crawl_symbols): Likewise.
+	* config/obj-coff.h (c_dot_file_symbol): Add "app" param.
+	(obj_app_file): Adjust.
+
+2004-11-18  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+
+	* configure.in: Enable bfd_assember for the MAXQ port.
+	* configure: Regenerate.
+
+2004-11-12  Bob Wilson  <bob.wilson@acm.org>
+	    Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (finish_vinsn): Clear pending instruction if
+	there is a conflict.
+	(check_t1_t2_reads_and_writes): Check for both reads and writes to
+	interfaces that are related as determined by xtensa_interface_class_id.
+
+2004-11-12  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-mn10300.c (md_relax_table): Fix off by one negative
+	offsets for conditional branches.
+
+2004-11-11  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (MAX_IMMED6): Change value to 65.
+
+2004-11-10  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (update_next_frag_state): Always add a NOP if
+	relaxing at the end of a loop.  Don't mark frags as UNREACHABLE or
+	MAYBE_UNREACHABLE.
+	(relax_frag_immed): Update call to update_next_frag_state.
+
+2004-11-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* obj.h (struct format_ops <app_file>): Add int param.
+	* read.h (s_app_file_string): Likewise.
+	* read.c (s_app_file_string): Likewise.
+	(s_app_file): Adjust s_app_file_string call.
+	* config/tc-mips.c (s_mips_file): Likewise.
+	* config/obj-coff.h (obj_app_file): Add app param.
+	* config/obj-ecoff.h (obj_app_file): Likewise.
+	* config/obj-multi.h (obj_app_file): Likewise.
+	* config/obj-elf.h (elf_file_symbol): Likewise.
+	* config/obj-elf.c (elf_file_symbol): Only emit one file symbol
+	if called for # preprocessor lines.
+
+2004-11-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 528
+	* symbols.c (resolve_symbol_value): Convert weak symbols only
+	for Windows PECOFF.
+	(symbol_equated_reloc_p): Don't equate weaks when relocating
+	only for Windows PECOFF.
+
+2004-11-08  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (print_insn): Check and set insn_addr.
+	* config/tc-crx.h (md_frag_check): Define.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* configure.in: Add support for new target maxq-coff.
+	* configure: Regenerate.
+	* NEWS: Mention new support.
+	* config/tc-maxq.c: New file.
+	* config/tc-maxq.h: New file.
+	* config/obj-coff.h: Add support for maxq-coff.
+
+2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
+
+	* symbols.c (any_external_name): Define.
+	(resolve_symbol_value): Convert weak symbols.
+	(S_SET_EXTERNAL): Support any_external_name.
+	(S_SET_NAME): Qualify parameter const.
+	(symbol_equated_reloc_p): Equate to weaks when relocating.
+	* symbols.h (S_SET_NAME): Qualfiy parameter const.
+	* tc.h (any_external_name): Declare.
+	* config/obj-coff.c ("coff/pe.h"): Include for BFD
+	assemblers also.
+	(weak_is_altname): Declare and define.
+	(weak_name2altname): Same.
+	(weak_altname2name): Same.
+	(weak_uniquify): Same.
+	(weak_altprefix): Define.
+	(obj_coff_weak): Change .weak syntax and handling.
+	(coff_frob_symbol): Fix PE weak symbol alternates.
+	* config/obj-coff.h (USE_UNIQUE): Define.
+	* config/tc-i386.c (md_apply_fix3): Assume weak symbols
+	are in another segment.
+	(tc_gen_reloc): Remove broken addend hack.
+	doc/as.texinfo: Update.
+
+2004-11-05  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (total_frag_text_expansion): New.
+	(md_estimate_size_before_relax): Use it.
+	(find_address_of_next_align_frag): Likewise.
+
+2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c: Rename argument types.
+	(processing_arg_number): Rename to 'cur_arg_num'.
+	(get_number_of_bits): Rename to 'set_operand_size'.
+	(get_operandtype): Rename to 'parse_operand', totally rewrite.
+	(set_cons_rparams): Rename to 'set_operand', totally rewrite.
+	(set_indexmode_parameters): Remove function, integrate its code into
+	'set_operand'.
+	(set_operand_size): Get rid of 'Operand Number' function parameter -
+	use global variable 'cur_arg_num' instead.
+	Use a local 'argument' pointer to reference the current argument.
+	(parse_operand): Likewise.
+	(set_operand): Likewise.
+	(process_label_constant): Likewise.
+
+2004-11-04  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c: Remove XTENSA_SECTION_RENAME ifdefs.
+	(add_section_rename): Delete.  Inlined into...
+	(build_section_rename): ...here.  Use xstrdup instead of strdup.
+	(xtensa_section_rename): Drop "const" from argument and return types.
+	(md_show_usage): Indent to match show_usage().
+	* config/tc-xtensa.h: Remove XTENSA_SECTION_RENAME ifdefs.
+	(tc_canonicalize_section_name): Define.
+	(md_elf_section_rename): Remove unused macro.
+	* doc/as.texinfo (Overview): Document Xtensa --rename-section option.
+	* doc/c-xtensa.texi (Xtensa Options): Likewise.
+	(Frame Directive): Delete.
+
+2004-11-04  Daniel Jacobowitz  <dan@debian.org>
+
+	* configure.in: Remove arm-*-oabi and thumb-*-oabi.
+	* config/tc-arm.c (target_oabi): Delete.
+	(md_apply_fix3, elf32_arm_target_format): Remove target_oabi checks.
+	(arm_opts): Remove moabi.
+	* doc/as.texinfo (Overview): Remove documentation of -moabi.
+	* doc/c-arm.texi (ARM Options): Likewise.
+	* configure: Regenerated.
+
+2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
+
+	* configure.in (crisv32): Recognize.  AC_DEFINE_UNQUOTED
+	DEFAULT_CRIS_ARCH.  Handle crisv32-*-linux-gnu* like
+	cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
+	* configure: Regenerate.
+	* config/tc-cris.c (enum cris_archs): New.
+	(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
+	(cris_insn_ver_valid_for_arch): New functions.
+	(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
+	(cris_arch): New variable.
+	(md_pseudo_table): New pseudo .arch.
+	(err_for_dangerous_mul_placement): Initialize according to
+	DEFAULT_CRIS_ARCH.
+	(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
+	All users changed.
+	(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
+	(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
+	(BRANCH_WF_V32, BRANCH_WB_V32): New.
+	(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
+	use in md_cris_relax_table.
+	(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
+	STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
+	Update and improve head comment.
+	(OPTION_PIC): Define in terms of previous option, OPTION_US.
+	(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
+	(OPTION_ARCH): New.
+	(md_longopts): New option --march=...
+	(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
+	macros.
+	(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
+	(HANDLE_RELAXABLE): New macro.
+	(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
+	cases.  Check for weak symbols and assume not relaxable.  Handle
+	STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
+	STATE_ABS_BRANCH_V32, STATE_LAPC.  Use new variable symbolP, not
+	fragP->fr_symbol.
+	(md_convert_frag): Handle STATE_COND_BRANCH_V32,
+	STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
+	(cris_create_short_jump): Adjust for CRISv32.
+	(cris_relax_frag): Handle new states.
+	(md_create_long_jump): Ditto.  Emit error for common_v10_v32.
+	(md_begin): Define symbols "..asm.arch.cris.v32",
+	"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
+	"..asm.arch.cris.any_v0_v10".  Use cris_insn_ver_valid_for_arch
+	when entering opcode table entry points.
+	(md_assemble): Adjust branch handling for CRISv32.  Handle LAPC
+	relaxation.  In fix_new_exp call for main insn, pass 1 for pcrel
+	parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
+	(cris_process_instruction): Initialize out_insnp->insn_type to
+	CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
+	<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
+	cases.
+	<case 'm'>: Check that modified_char == '.'.
+	<invalid operands>: Consume the rest of the line.
+	When operands don't match, skip over subsequent insns with
+	non-matching version specifier but same mnemonic.
+	<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
+	special registers in CRISv32 are always 32 bit long.
+	<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
+	New cases.
+	(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
+	and compatible.  Recognize "ACR" for v32, unless followed by "+".
+	(get_spec_reg): Consider cris_arch when looking up register.
+	(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
+	v32 or compatible.
+	(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
+	(cris_get_expression): Restore input_line_pointer if failing "early".
+	(get_flags): Consider cris_arch and recognize flags accordingly.
+	(branch_disp): Adjust for CRISv32.
+	(gen_cond_branch_32): Similar.  Emit error for common_v10_v32.
+	(cris_number_to_imm): Use as_bad_where, not as_bad.  Remove
+	related FIXME.  Don't insist on BFD_RELOC_32_PCREL fixup to be
+	resolved.  Don't enter zeros in object file for
+	BFD_RELOC_32_PCREL.
+	<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
+	<case BFD_RELOC_CRIS_SIGNED_8>: New case.
+	(md_parse_option): Break out "return 1".
+	<OPTION_ARCH> New case.
+	(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
+	<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
+	<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
+	<case BFD_RELOC_32_PCREL>: New cases.
+	Addends for non-zero fx_pcrel are too in fx_offset.
+	(md_show_usage): Show --march=<arch>.
+	(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
+	(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
+	(s_syntax) <struct syntaxes>: Properly constify member operand.
+	* config/tc-cris.h (TARGET_MACH): Define.
+	(cris_mach): Declare.
+	* doc/as.texinfo (Overview) <CRIS>: Add --march=...
+	* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
+	(CRIS-Opts): Document --march=...
+	(CRIS-Pseudos): Document .arch.
+
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+	* config/tc-i386.c (set_intel_syntax): Allow % in symbol names when
+	intel syntax and no register prefix, allow $ in symbol names when
+	intel syntax.
+	(set_16bit_gcc_code_flag): Replace literal 'l' by LONG_MNEM_SUFFIX.
+	(intel_float_operand): Add fourth return value indicating math control
+	operations. Make classification more precise.
+	(md_assemble): Complain if memory operand of mov[sz]x has no size
+	specified.
+	(parse_insn): Translate word operands to floating point instructions
+	operating on integers as well as control instructions to short ones
+	as expected by AT&T syntax. Translate 'd' suffix to short one only for
+	floating point instructions operating on non-integer operands.
+	(match_template): Remove fldcw special case. Adjust q-suffix handling
+	to permit it on fild/fistp/fisttp in AT&T mode.
+	(process_suffix): Don't guess DefaultSize insns' suffix from
+	stackop_size for certain floating point control instructions. Guess
+	suffix for branch and [ls][gi]dt based on flag_code. Split error
+	messages for Intel and AT&T syntax, and make the condition more strict
+	for the former. Adjust suppressing of generation of operand size
+	overrides.
+	(intel parser): Allow the full set of MASM operators. Add FWORD, TBYTE,
+	OWORD, and XMMWORD operand size specifiers (TBYTE replaces XWORD). Add
+	more error checking.
+	* config/tc-i386.h (BYTE_PTR WORD_PTR DWORD_PTR QWORD_PTR XWORD_PTR
+	SHORT OFFSET_FLAT FLAT NONE_FOUND): Remove unused defines.
+
+2004-11-03  Hans-Peter Nilsson  <hp@axis.com>
+
+	* symbols.c (colon) [!WORKING_DOT_WORD]: Don't declare
+	md_short_jump_size, md_long_jump_size.
+	* write.c [!WORKING_DOT_WORD]: Ditto.
+	* tc.h [!WORKING_DOT_WORD]: Declare them here.  Drop const
+	qualifier.
+	* config/tc-cris.h (md_short_jump_size, md_long_jump_size): Don't
+	declare.
+	* config/tc-cris.c (md_short_jump_size, md_long_jump_size): Drop
+	const qualifier in these definitions.
+	* config/tc-i370.c, config/tc-m68k.c, config/tc-pdp11.c,
+	config/tc-s390.c, config/tc-tahoe.c, config/tc-vax.c: Ditto.
+
+2004-11-02  Nick Clifton  <nickc@redhat.com>
+
+	* dwarf2dbg.c (dwarf2_finish): Check for the existence of a file
+	table before deciding to produce a .debug_line section to match up
+	with a user provided .debug_info section.
+
+2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (getreg_image): Bug fix, a return value was
+	mistakenly omitted from CRX_C_REGTYPE and CRX_CS_REGTYPE cases.
+
+2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c: Remove global variable 'post_inc_mode'.
+	(get_flags): New function.
+	(get_number_of_bits): Edit comments, update numeric values to
+	supported sizes.
+	(process_label_constant): Don't support the colon
+	format (SYMBOL:[s|m|l]).
+	(set_cons_rparams): Support argument type 'arg_rbase'.
+	(get_operandtype): Bug fix in 'rbase' operand type parsing.
+	(handle_LoadStor): Bug fix, first handle post-increment mode.
+	(getreg_image): Remove redundant code, update according to latest
+	CRX spec.
+	(print_constant): Bug fix relate to 3-word instructions.
+	(assemble_insn): Bug fix, when matching instructions, verify also
+	instruction type (not only mnemonic).
+	Add various error checking.
+	(preprocess_reglist): Support HI/LO and user registers.
+
+2004-10-25  David Mosberger-Tang  <davidm@hpl.hp.com>
+
+	* config/tc-ia64.c (fixup_unw_records): Don't let the "t" value
+	in an epilogue directive go negative.
+
+2004-10-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 474
+	* config/tc-ia64.c (emit_one_bundle): Decrement md.num_slots_in_use
+	after reporting template error during manual bundling. Reported
+	by Michael Dupont, michaelx.dupont@intel.com.
+
+2004-10-25  Daniel Jacobowitz  <dan@debian.org>
+
+	* Makefile.am: Run dep-am.
+	* aclocal.m4: Regenerate with automake 1.9.2.
+	* Makefile.in: Regenerate with automake 1.9.2.
+	* doc/Makefile.in: Likewise.
+
+	* config/tc-arm.c: Include "dw2gencfi.h".
+	(tc_arm_regname_to_dw2regnum, tc_arm_frame_initial_instructions):
+	New functions.
+	* config/tc-arm.h (TARGET_USE_CFIPOP, DWARF2_DEFAULT_RETURN_COLUMN)
+	(DWARF2_CIE_DATA_ALIGNMENT, tc_regname_to_dw2regnum)
+	(tc_cfi_frame_initial_instructions): Define.
+	(tc_arm_regname_to_dw2regnum, tc_arm_frame_initial_instructions):
+	Add prototypes.
+
+2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (assemble_insn): Check unsigned immediate
+	operands validity.
+	Update coprocessor id to be unsigned immediate.
+
+2004-10-18  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
+
+	* config/tc-i386.c (O_secrel): Delete.
+	(tc_pe_dwarf2_emit_offset): New function.
+	* config/tc-i386.h (O_secrel): Define as O_md1.
+	(TC_DWARF2_EMIT_OFFSET): Define.
+
+2004-10-18  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-xstormy16.c (xstormy16_cons_fix_new): Accept and
+	ignore @fptr() directives for 4-byte fixups.
+
+2004-10-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am"
+	* Makefile.in: Regenerate.
+
+2004-10-14  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/c-xtensa.texi (Xtensa Options, Absolute Literals Directive):
+	Remove comments about placement of literal pools.
+	(Literal Directive): Update description of literal placement.
+	(Literal Prefix Directive): Remove statement that this does not apply
+	to absolute-mode literals.  Describe new section naming scheme.
+
+2004-10-12  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_frequency_pseudo): Use set_subseg_freq.
+	(is_entry_opcode, is_movi_opcode, is_the_loop_opcode, is_jx_opcode,
+	is_windowed_return_opcode): Delete.
+	(xtensa_frob_label): Use get_subseg_target_freq.
+	(md_assemble): Inline call to is_entry_opcode.
+	(xtensa_handle_align): Inline call to get_frag_is_literal.
+	(relaxation_requirements): Inline call to is_jx_opcode.
+	(emit_single_op): Inline call to is_movi_opcode.
+	(xg_assemble_vliw_tokens): Inline calls to get_frag_is_insn,
+	get_frag_is_no_transform, is_entry_opcode, and
+	set_frag_is_specific_opcode.  Use get_subseg_total_freq.
+	(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags,
+	xtensa_fix_close_loop_end_frags, relax_frag_immed, convert_frag_immed):
+	Inline calls to get_frag_is_no_transform.
+	(next_instrs_are_b_retw): Inline call to is_windowed_return_opcode.
+	(xtensa_fix_short_loop_frags): Inline calls to is_the_loop_opcode and
+	get_frag_is_no_transform.
+	(convert_frag_immed_finish_loop): Inline calls to get_expression_value
+	and set_frag_is_no_transform.
+	(get_expression_value): Delete.
+	(subseg_map struct): Rename cur_total_freq to total_freq.  Rename
+	cur_target_freq to target_freq.
+	(get_subseg_info): Split out code to create a new map entry into ...
+	(add_subseg_info): ... this new function.
+	(get_last_insn_flags): Check if get_subseg_info succeeded.
+	(set_last_insn_flags): Call add_subseg_info if needed.
+	(get_subseg_total_freq, get_subseg_target_freq, set_subseg_freq): New.
+	(xtensa_reorder_segments): Compute last_sec while counting sections.
+	Remove call to get_last_sec.
+	(get_last_sec): Delete.
+	(cache_literal_section): Inline call to retrieve_literal_seg and its
+	callees, seg_present and add_seg_list.
+	(retrieve_literal_seg, seg_present, add_seg_list): Delete.
+	(get_frag_is_insn, get_frag_is_no_transform,
+	set_frag_is_specific_opcode, set_frag_is_no_transform): Delete.
+	* config/tc-xtensa.h (MAX_SLOTS): Reduce from 31 to 15.
+
+2004-10-12  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c: Use ISO C90 formatting.
+	* config/tc-xtensa.h: Likewise.
+	* config/xtensa-istack.h: Likewise.
+	* config/xtensa-relax.c: Likewise.
+	* config/xtensa-relax.h: Likewise.
+
+2004-10-12  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_begin): Change EF_ARM_EABI_VER3 to
+	EF_ARM_EABI_VER4.
+	(arm_eabis): Ditto.
+	* doc/c-arm.texi: Document that we actually support -meabi=4, not
+	-meabi=3.
+
+2004-10-08  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo (VTableEntry, VTableInherit): Add "directive" to index
+	entries.
+	(Acknowledgements): Use "GAS" instead of AS variable.
+
+2004-10-08  Daniel Jacobowitz  <dan@debian.org>
+
+	* config/tc-i386.c: Include "elf/x86-64.h".
+	(i386_elf_section_type): New function.
+	* config/tc-i386.h (md_elf_section_type): Define.
+	(i386_elf_section_type): New prototype.
+
+2004-10-08  Linus Nielsen Feltzing  <linus@haxx.se>
+
+	* config/m68k-parse.h (enum m68k_register): New control register,
+	MBAR2 (for MCF5249)
+	* config/tc-m68k.c: Correct control register set for MCF5249.
+
+2004-10-07  Bob Wilson  <bob.wilson@acm.org>
+	    Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (absolute_literals_supported): New global flag.
+	(UNREACHABLE_MAX_WIDTH): Define.
+	(XTENSA_FETCH_WIDTH): Delete.
+	(cur_vinsn, xtensa_fetch_width, xt_saved_debug_type, past_xtensa_end,
+	prefer_const16, prefer_l32r): New global variables.
+	(LIT4_SECTION_NAME): Define.
+	(lit4_state struct): Add lit4_seg_name and lit4_seg fields.
+	(XTENSA_PROP_*, GET_XTENSA_PROP_*, SET_XTENSA_PROP_*): Define.
+	(frag_flags struct): New.
+	(xtensa_block_info struct): Move from tc-xtensa.h.  Add flags field.
+	(subseg_map struct): Add cur_total_freq and cur_target_freq fields.
+	(bitfield, bit_is_set, set_bit, clear_bit): Define.
+	(MAX_FORMATS): Define.
+	(op_placement_info struct, op_placement_table): New.
+	(O_pltrel, O_hi16, O_lo16): Define.
+	(directiveE enum): Rename directive_generics to directive_transform.
+	Delete directive_relax.  Add directive_schedule,
+	directive_absolute_literals, and directive_last_directive.
+	(directive_info): Rename "generics" to "transform".  Delete "relax".
+	Add "schedule" and "absolute-literals".
+	(directive_state): Adjust entries to match changes in directive_info.
+	(xtensa_relax_statesE, RELAX_IMMED_MAXSTEPS): Move to tc-xtensa.h.
+	(xtensa_const16_opcode, xtensa_movi_opcode, xtensa_movi_n_opcode,
+	xtensa_l32r_opcode, xtensa_nop_opcode, xtensa_rsr_lcount_opcode): New.
+	(xtensa_j_opcode, xtensa_rsr_opcode): Delete.
+	(align_only_targets, software_a0_b_retw_interlock,
+	software_avoid_b_j_loop_end, maybe_has_b_j_loop_end,
+	software_avoid_short_loop, software_avoid_close_loop_end,
+	software_avoid_all_short_loops, specific_opcode): Delete.
+	(warn_unaligned_branch_targets): New.
+	(workaround_a0_b_retw, workaround_b_j_loop_end, workaround_short_loop,
+	workaround_close_loop_end, workaround_all_short_loops): Default FALSE.
+	(option_[no_]link_relax, option_[no_]transform,
+	option_[no_]absolute_literals, option_warn_unaligned_targets,
+	option_prefer_l32r, option_prefer_const16, option_target_hardware):
+	New enum values.
+	(option_[no_]align_only_targets, option_literal_section_name,
+	option_text_section_name, option_data_section_name,
+	option_bss_section_name, option_eb, option_el): Delete.
+	(md_longopts): Add entries for: [no-]transform, [no-]absolute-literals,
+	warn-unaligned-targets, prefer-l32r, prefer-const16, [no-]link-relax,
+	and target-hardware.  Delete entries for [no-]target-align-only,
+	literal-section-name, text-section-name, data-section-name, and
+	bss-section-name.
+	(md_parse_option): Handle new options and remove old ones.  Accept but
+	ignore [no-]density options.  Warn for [no-]generics and [no-]relax
+	and treat them as [no-]transform.
+	(md_show_usage): Add new options and remove old ones.
+	(xtensa_setup_hw_workarounds): New.
+	(md_pseudo_table): Change "word" entry to use xtensa_elf_cons.  Add
+	"long", "short", "loc" and "frequency" entries.
+	(use_generics): Rename to ...
+	(use_transform): ... this function.  Add past_xtensa_end check.
+	(use_longcalls): Add past_xtensa_end check.
+	(code_density_available, can_relax): Delete.
+	(do_align_targets): New.
+	(get_directive): Accept dashes in directive names.  Warn about
+	[no-]generics and [no-]relax directives and treat them as
+	[no-]transform.
+	(xtensa_begin_directive): Call md_flush_pending_output only for some
+	directives.  Check for directives inside instruction bundles.  Warn
+	about deprecated ".begin literal" usage.  Warn and ignore [no-]density
+	directives.  Handle new directives.  Check generating_literals flag
+	for literal_prefix.
+	(xtensa_end_directive): Check for directives inside instruction
+	bundles.  Warn and ignore [no-]density directives.  Handle new
+	directives.  Call xtensa_set_frag_assembly_state.
+	(xtensa_loc_directive_seen, xtensa_dwarf2_directive_loc,
+	xtensa_dwarf2_emit_insn): New.
+	(xtensa_literal_position): Call md_flush_pending_output.  Do not check
+	use_literal_section flag.
+	(xtensa_literal_pseudo): Call md_flush_pending_output.  Handle absolute
+	literals.  Use xtensa_elf_cons to parse the expression.
+	(xtensa_literal_prefix): Do not check use_literal_section.  Support
+	".lit4" sections for absolute literals.  Change prefix convention to
+	replace ".text" (or ".t" in a linkonce section).  No need to call
+	subseg_set.
+	(xtensa_frequency_pseudo, xtensa_elf_cons, xtensa_elf_suffix): New.
+	(expression_end): Handle closing braces and colons.
+	(PLT_SUFFIX, plt_suffix): Delete.
+	(expression_maybe_register): Use new xtensa-isa.h functions.  Use
+	xtensa_elf_suffix instead of checking for plt suffix, and handle O_lo16
+	and O_hi16 expressions as well.
+	(tokenize_arguments): Handle closing braces and colons.
+	(parse_arguments): Use new xtensa-isa.h functions.  Handle "invisible"
+	operands and paired register syntax.
+	(get_invisible_operands): New.
+	(xg_translate_sysreg_op): Handle new Xtensa LX RSR/WSR/XSR syntax.  Use
+	new xtensa-isa.h functions.
+	(xtensa_translate_old_userreg_ops, xtensa_translate_zero_immed): New.
+	(xg_translate_idioms): Check if inside bundle.  Use use_transform.
+	Handle new Xtensa LX RSR/WSR/XSR syntax.  Remove code to widen density
+	instructions.  Use xtensa_translate_zero_immed.
+	(operand_is_immed, operand_is_pcrel_label): Delete.
+	(get_relaxable_immed): Use new xtensa-isa.h functions.
+	(get_opcode_from_buf): Add slot parameter.  Use new xtensa-isa.h
+	functions.
+	(xtensa_print_insn_table, print_vliw_insn): New.
+	(is_direct_call_opcode): Use new xtensa-isa.h functions.
+	(is_call_opcode, is_loop_opcode, is_conditional_branch_opcode,
+	is_branch_or_jump_opcode): Delete.
+	(is_movi_opcode, decode_reloc, encode_reloc, encode_alt_reloc): New.
+	(opnum_to_reloc, reloc_to_opnum): Delete.
+	(xtensa_insnbuf_set_operand, xtensa_insnbuf_get_operand): Use new
+	xtensa-isa.h functions.  Operate on one slot of an instruction.
+	(xtensa_insnbuf_set_immediate_field, is_negatable_branch,
+	xg_get_insn_size): Delete.
+	(xg_get_build_instr_size): Use xg_get_single_size.
+	(xg_is_narrow_insn, xg_is_single_relaxable_insn): Update calls to
+	xg_build_widen_table.  Use xg_get_single_size.
+	(xg_get_max_narrow_insn_size): Delete.
+	(xg_get_max_insn_widen_size, xg_get_max_insn_widen_literal_size,
+	xg_is_relaxable_insn): Update calls to xg_build_widen_table.  Use
+	xg_get_single_size.
+	(xg_build_to_insn): Record the loc field.  Handle OP_OPERAND_HI16U and
+	OP_OPERAND_LOW16U.  Check xg_valid_literal_expression.
+	(xg_expand_to_stack, xg_expand_narrow): Update calls to
+	xg_build_widen_table.  Use xg_get_single_size.
+	(xg_immeds_fit): Use new xtensa-isa.h functions.  Update call to
+	xg_check_operand.
+	(xg_symbolic_immeds_fit): Likewise.  Also handle O_lo16 and O_hi16, and
+	treat weak symbols conservatively.
+	(xg_check_operand): Use new xtensa-isa.h functions.
+	(is_dnrange): Delete.
+	(xg_assembly_relax): Inline previous calls to tinsn_copy.
+	(xg_finish_frag): Specify separate relax states for the frag and slot0.
+	(is_branch_jmp_to_next, xg_add_branch_and_loop_targets): Use new
+	xtensa-isa.h functions.
+	(xg_instruction_matches_option_term, xg_instruction_matches_or_options,
+	xg_instruction_matches_options): New.
+	(xg_instruction_matches_rule): Handle O_register expressions.  Call
+	xg_instruction_matches_options.
+	(transition_rule_cmp): New.
+	(xg_instruction_match): Update call to xg_build_simplify_table.
+	(xg_build_token_insn): Record loc fields.
+	(xg_simplify_insn): Check is_specific_opcode field and
+	density_supported flag.
+	(xg_expand_assembly_insn): Skip checking code_density_available.  Use
+	new xtensa-isa.h functions.  Call use_transform instead of can_relax.
+	(xg_assemble_literal): Add error handling for O_big.  Call
+	record_alignment.  Handle O_pltrel.
+	(xg_valid_literal_expression): New.
+	(xg_assemble_literal_space): Add slot parameter.  Remove call to
+	set_expr_symbol_offset.  Add call to record_alignment.  Update call to
+	xg_finish_frag.
+	(xg_emit_insn): Delete.
+	(xg_emit_insn_to_buf): Add format parameter.  Update calls to
+	xg_add_opcode_fix and xtensa_insnbuf_to_chars.
+	(xg_add_opcode_fix): Change opcode parameter to tinsn and add format
+	and slot parameters.  Handle new "alternate" relocations for absolute
+	literals and CONST16 instructions.  Check for bad uses of O_lo16 and
+	O_hi16.  Use new xtensa-isa.h functions.
+	(xg_assemble_tokens): Delete.
+	(is_register_writer): Use new xtensa-isa.h functions.
+	(is_bad_loopend_opcode): Check for xtensa_rsr_lcount_opcode instead of
+	old-style RSR from LCOUNT.
+	(next_frag_opcode): Delete.
+	(next_frag_opcode_is_loop, next_frag_format_size, frag_format_size,
+	update_next_frag_state): New.
+	(update_next_frag_nop_state): Delete.
+	(next_frag_pre_opcode_bytes): Use next_frag_opcode_is_loop.
+	(xtensa_mark_literal_pool_location): Check use_literal_section flag and
+	the state of the absolute-literals directive.  Add calls to
+	record_alignment and xtensa_set_frag_assembly_state.  Call
+	xtensa_switch_to_non_abs_literal_fragment instead of
+	xtensa_switch_to_literal_fragment.
+	(build_nop): New.
+	(assemble_nop): Use build_nop.  Update call to xtensa_insnbuf_to_chars.
+	(get_expanded_loop_offset): Change check for undefined opcode to an
+	assertion.
+	(xtensa_set_frag_assembly_state, relaxable_section,
+	xtensa_find_unmarked_state_frags, xtensa_find_unaligned_branch_targets,
+	xtensa_find_unaligned_loops, xg_apply_tentative_value): New.
+	(md_begin): Update call to xtensa_isa_init.  Initialize linkrelax to 1.
+	Set lit4_seg_name.  Call xg_init_vinsn.  Initialize new global opcodes.
+	Call init_op_placement_info_table and xtensa_set_frag_assembly_state.
+	(xtensa_init_fix_data): New.
+	(xtensa_frob_label): Reset label symbol to the current frag.  Check
+	do_align_targets and generating_literals flag.  Propagate frequency
+	info to new alignment frag.  Call xtensa_set_frag_assembly_state.
+	(xtensa_unrecognized_line): New.
+	(xtensa_flush_pending_output): Check if inside a bundle.  Add a call
+	to xtensa_set_frag_assembly_state.
+	(error_reset_cur_vinsn): New.
+	(md_assemble): Remove check for literal frag.  Remove call to
+	istack_init.  Call use_transform instead of use_generics.  Parse
+	explicit instruction format specifiers.  Move code for
+	a0_b_retw_interlock workaround to xg_assemble_vliw_tokens.  Call
+	error_reset_cur_vinsn on errors.  Add call to get_invisible_operands.
+	Add dwarf2_where call.  Remote automatic alignment for ENTRY
+	instructions.  Move call to xtensa_clear_insn_labels to the end.
+	Rearrange to handle bundles.
+	(xtensa_cons_fix_new): Delete.
+	(xtensa_handle_align): New.
+	(xtensa_frag_init): Call xtensa_set_frag_assembly_state.  Remove
+	assignment to is_no_density field.
+	(md_pcrel_from): Use new xtensa-isa.h functions.  Use decode_reloc
+	instead of reloc_to_opnum.  Handle "alternate" relocations.
+	(xtensa_force_relocation, xtensa_check_inside_bundle,
+	xtensa_elf_section_change_hook): New.
+	(xtensa_symbol_new_hook): Delete.
+	(xtensa_fix_adjustable): Check for difference of symbols with an
+	offset.  Check for external and weak symbols.
+	(md_apply_fix3): Remove cases for XTENSA_OP{0,1,2} relocs.
+	(md_estimate_size_before_relax): Return expansion for the first slot.
+	(tc_gen_reloc): Handle difference of symbols by producing
+	XTENSA_DIFF{8,16,32} relocs and by writing the value of the difference
+	into the output.  Handle new XTENSA_SLOT*_OP relocs by storing the
+	tentative values into the output when linkrelax is set.
+	(XTENSA_PROP_SEC_NAME): Define.
+	(xtensa_post_relax_hook): Call xtensa_find_unmarked_state_frags.
+	Create literal tables only if using literal sections.  Create new
+	property tables instead of old instruction tables.  Check for unaligned
+	branch targets and loops.
+	(finish_vinsn, find_vinsn_conflicts, check_t1_t2_reads_and_writes,
+	new_resource_table, clear_resource_table, resize_resource_table,
+	resources_available, reserve_resources, release_resources,
+	opcode_funcUnit_use_unit, opcode_funcUnit_use_stage,
+	resources_conflict, xg_find_narrowest_format, relaxation_requirements,
+	bundle_single_op, emit_single_op, xg_assemble_vliw_tokens): New.
+	(xtensa_end): Call xtensa_flush_pending_output.  Set past_xtensa_end
+	flag.  Update checks for workaround options.  Call
+	xtensa_mark_narrow_branches and xtensa_mark_zcl_first_insns.
+	(xtensa_cleanup_align_frags): Add special case for branch targets.
+	Check for and mark unreachable frags.
+	(xtensa_fix_target_frags): Remove use of align_only_targets flag.
+	Use RELAX_LOOP_END_BYTES in special case for negatable branch at the
+	end of a zero-overhead loop body.
+	(frag_can_negate_branch): Handle instructions with multiple slots.
+	Use new xtensa-isa.h functions
+	(xtensa_mark_narrow_branches, is_narrow_branch_guaranteed_in_range,
+	xtensa_mark_zcl_first_insns): New.
+	(xtensa_fix_a0_b_retw_frags, xtensa_fix_b_j_loop_end_frags): Error if
+	transformations are disabled.
+	(next_instrs_are_b_retw): Use new xtensa-isa.h functions.  Handle
+	multislot instructions.
+	(xtensa_fix_close_loop_end_frags, xtensa_fix_short_loop_frags):
+	Likewise.  Also error if transformations are disabled.
+	(unrelaxed_frag_max_size): New.
+	(unrelaxed_frag_min_insn_count, unrelax_frag_has_b_j): Use new
+	xtensa-isa.h functions.
+	(xtensa_sanity_check, is_empty_loop, is_local_forward_loop): Use
+	xtensa_opcode_is_loop instead of is_loop_opcode.
+	(get_text_align_power): Replace as_fatal with assertion.
+	(get_text_align_fill_size): Iterate instead of using modulus when
+	use_nops is false.
+	(get_noop_aligned_address): Assert that this is for a machine-dependent
+	RELAX_ALIGN_NEXT_OPCODE frag.  Use next_frag_opcode_is_loop,
+	xg_get_single_size, and frag_format_size.
+	(get_widen_aligned_address): Rename to ...
+	(get_aligned_diff): ... this function.  Add max_diff parameter.
+	Remove handling of rs_align/rs_align_code frags.  Use
+	next_frag_format_size, get_text_align_power, get_text_align_fill_size,
+	next_frag_opcode_is_loop, and xg_get_single_size.  Compute max_diff
+	and pass it back to caller.
+	(xtensa_relax_frag): Use relax_frag_loop_align.  Add code for new
+	RELAX_SLOTS, RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN,
+	RELAX_FILL_NOP, and RELAX_UNREACHABLE frag types.  Check relax_seen.
+	(relax_frag_text_align): Rename to ...
+	(relax_frag_loop_align): ... this function.  Assume loops can only be
+	in the first slot of an instruction.
+	(relax_frag_add_nop): Use assemble_nop instead of constructing an OR
+	instruction.  Remove call to frag_wane.
+	(relax_frag_narrow): Rename to ...
+	(relax_frag_for_align): ... this function.  Extend to handle
+	RELAX_FILL_NOP and RELAX_UNREACHABLE, as well as RELAX_SLOTS with
+	RELAX_NARROW for the first slot.
+	(find_address_of_next_align_frag, bytes_to_stretch): New.
+	(future_alignment_required): Use find_address_of_next_align_frag and
+	bytes_to_stretch.  Look ahead to subsequent frags to make smarter
+	alignment decisions.
+	(relax_frag_immed): Add format, slot, and estimate_only parameters.
+	Check if transformations are enabled for b_j_loop_end workaround.
+	Use new xtensa-isa.h functions and handle multislot instructions.
+	Update call to xg_assembly_relax.
+	(md_convert_frag): Handle new RELAX_SLOTS, RELAX_UNREACHABLE,
+	RELAX_MAYBE_UNREACHABLE, RELAX_MAYBE_DESIRE_ALIGN, and RELAX_FILL_NOP
+	frag types.
+	(convert_frag_narrow): Add segP, format and slot parameters.  Call
+	convert_frag_immed for branch instructions.  Adjust calls to
+	tinsn_from_chars, tinsn_immed_from_frag, and xg_emit_insn_to_buf.  Use
+	xg_get_single_size and xg_get_single_format.
+	(convert_frag_fill_nop): New.
+	(convert_frag_immed): Add format and slot parameters.  Handle multislot
+	instructions and use new xtensa-isa.h functions.  Update calls to
+	tinsn_immed_from_frag and xg_assembly_relax.  Check if transformations
+	enabled for b_j_loop_end workaround.  Use build_nop instead of
+	assemble_nop.  Check is_specific_opcode flag.  Check for unreachable
+	frags.  Use xg_get_single_size.  Handle O_pltrel.
+	(fix_new_exp_in_seg): Remove check for old plt flag.
+	(convert_frag_immed_finish_loop): Update calls to tinsn_from_chars and
+	xtensa_insnbuf_to_chars.  Call tinsn_immed_from_frag.  Change check
+	for loop opcode to an assertion.  Mark all frags up to the end of the
+	loop as not transformable.
+	(get_last_insn_flags, set_last_insn_flags): Use get_subseg_info.
+	(get_subseg_info): New.
+	(xtensa_move_literals): Call xtensa_set_frag_assembly_state.  Add null
+	check for dest_seg.
+	(xtensa_switch_to_literal_fragment): Rewrite to handle absolute
+	literals and use xtensa_switch_to_non_abs_literal_fragment otherwise.
+	(xtensa_switch_to_non_abs_literal_fragment): New.
+	(cache_literal_section): Add is_code parameter and pass it through to
+	retrieve_literal_seg.
+	(retrieve_literal_seg): Add is_code parameter and use it to set the
+	flags on the literal section.  Handle case where head parameter is 0.
+	(get_frag_is_no_transform, set_frag_is_specific_opcode,
+	set_frag_is_no_transform): New.
+	(xtensa_create_property_segments): Add end_property_function parameter
+	and pass it through to add_xt_block_frags.  Call bfd_get_section_flags
+	and skip SEC_DEBUGGING and !SEC_ALLOC sections.
+	(xtensa_create_xproperty_segments, section_has_xproperty): New.
+	(add_xt_block_frags): Add end_property_function parameter and call it
+	if it is non-zero.  Call xtensa_frag_flags_init.
+	(xtensa_frag_flags_is_empty, xtensa_frag_flags_init,
+	get_frag_property_flags, frag_flags_to_number,
+	xtensa_frag_flags_combinable, xt_block_aligned_size,
+	xtensa_xt_block_combine, add_xt_prop_frags,
+	init_op_placement_info_table, opcode_fits_format_slot,
+	xg_get_single_size, xg_get_single_format): New.
+	(istack_push): Inline call to tinsn_copy.
+	(tinsn_copy): Delete.
+	(tinsn_has_invalid_symbolic_operands): Handle O_hi16 and O_lo16 and
+	CONST16 opcodes.  Handle O_big, O_illegal, and O_absent.
+	(tinsn_has_complex_operands): Handle O_hi16 and O_lo16.
+	(tinsn_to_insnbuf): Use xg_get_single_format and new xtensa-isa.h
+	functions.  Handle invisible operands.
+	(tinsn_to_slotbuf): New.
+	(tinsn_check_arguments): Use new xtensa-isa.h functions.
+	(tinsn_from_chars): Add slot parameter.  Rewrite using xg_init_vinsn,
+	vinsn_from_chars, and xg_free_vinsn.
+	(tinsn_from_insnbuf): New.
+	(tinsn_immed_from_frag): Add slot parameter and handle multislot
+	instructions.  Handle symbol differences.
+	(get_num_stack_text_bytes): Use xg_get_single_size.
+	(xg_init_vinsn, xg_clear_vinsn, vinsn_has_specific_opcodes,
+	xg_free_vinsn, vinsn_to_insnbuf, vinsn_from_chars, expr_is_register,
+	get_expr_register, set_expr_symbol_offset_diff): New.
+	* config/tc-xtensa.h (MAX_SLOTS): Define.
+	(xtensa_relax_statesE): Move from tc-xtensa.c. Add
+	RELAX_CHECK_ALIGN_NEXT_OPCODE, RELAX_MAYBE_DESIRE_ALIGN, RELAX_SLOTS,
+	RELAX_FILL_NOP, RELAX_UNREACHABLE, RELAX_MAYBE_UNREACHABLE, and
+	RELAX_NONE types.
+	(RELAX_IMMED_MAXSTEPS): Move from tc-xtensa.c.
+	(xtensa_frag_type struct): Add is_assembly_state_set,
+	use_absolute_literals, relax_seen, is_unreachable, is_specific_opcode,
+	is_align, is_text_align, alignment, and is_first_loop_insn fields.
+	Replace is_generics and is_relax fields by is_no_transform field.
+	Delete is_text and is_longcalls fields.  Change text_expansion and
+	literal_expansion to arrays of MAX_SLOTS entries.  Add arrays of
+	per-slot information: literal_frags, slot_subtypes, slot_symbols,
+	slot_sub_symbols, and slot_offsets.  Add fr_prev field.
+	(xtensa_fix_data struct): New.
+	(xtensa_symfield_type struct): Delete plt field.
+	(xtensa_block_info struct): Move definition to tc-xtensa.h.  Add
+	forward declaration here.
+	(xt_section_type enum): Delete xt_insn_sec.  Add xt_prop_sec.
+	(XTENSA_SECTION_RENAME): Undefine.
+	(TC_FIX_TYPE, TC_INIT_FIX_DATA, TC_FORCE_RELOCATION, NO_PSEUDO_DOT,
+	tc_unrecognized_line, md_do_align, md_elf_section_change_hook,
+	HANDLE_ALIGN, TC_LINKRELAX_FIXUP, SUB_SEGMENT_ALIGN): Define.
+	(TC_CONS_FIX_NEW, tc_symbol_new_hook): Delete.
+	(unit_num_copies_func, opcode_num_units_func,
+	opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func): New.
+	(resource_table struct): New.
+	* config/xtensa-istack.h (MAX_INSN_ARGS): Increase from 6 to 10.
+	(TInsn struct): Add keep_wide, loc, fixup, record_fix, subtype,
+	literal_space, symbol, sub_symbol, offset, and literal_frag fields.
+	(tinsn_copy): Delete prototype.
+	(vliw_insn struct): New.
+	* config/xtensa-relax.c (insn_pattern_struct): Add options field.
+	(widen_spec_list): Add option conditions for density and boolean
+	instructions.  Add expansions using CONST16 and conditions for using
+	CONST16 vs. L32R.  Use new Xtensa LX RSR/WSR syntax.  Add entries for
+	predicted branches.
+	(simplify_spec_list): Add option conditions for density instructions.
+	Add entry for NOP instruction.
+	(append_transition): Add cmp function pointer parameter and use it to
+	insert the new entry in order.
+	(operand_function_LOW16U, operand_function_HI16U): New.
+	(xg_has_userdef_op_fn, xg_apply_userdef_op_fn): Handle
+	OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
+	(enter_opname, split_string): Use xstrdup instead of strdup.
+	(init_insn_pattern): Initialize new options field.
+	(clear_req_or_option_list, clear_req_option_list,
+	clone_req_or_option_list, clone_req_option_list, parse_option_cond):
+	New.
+	(parse_insn_pattern): Parse option conditions.
+	(transition_applies): New.
+	(build_transition): Use new xtensa-isa.h functions.  Fix incorrectly
+	swapped last arguments in calls to append_constant_value_condition.
+	Call clone_req_option_list.  Add warning about invalid opcode.
+	Handle LOW16U and HI16U function names.
+	(build_transition_table): Add cmp parameter and use it in calls to
+	append_transition.  Use new xtensa-isa.h functions.  Check
+	transition_applies before adding entries.
+	(xg_build_widen_table, xg_build_simplify_table): Add cmp parameter and
+	pass it through to build_transition_table.
+	* config/xtensa-relax.h (ReqOrOptionList, ReqOrOption, ReqOptionList,
+	ReqOption, transition_cmp_fn): New types.
+	(OpType enum): Add OP_OPERAND_LOW16U and OP_OPERAND_HI16U.
+	(transition_rule struct): Add options field.
+	* doc/as.texinfo (Overview): Update Xtensa options.
+	* doc/c-xtensa.texi (Xtensa Options): Delete --[no-]density,
+	--[no-]relax, and --[no-]generics options.  Update descriptions of
+	--text-section-literals and --[no-]longcalls.  Add
+	--[no-]absolute-literals and --[no-]transform.
+	(Xtensa Syntax): Add description of syntax for FLIX instructions.
+	Remove use of "generic" and "specific" terminology for opcodes.
+	(Xtensa Registers): Generalize the syntax description to include
+	user-defined register files.
+	(Xtensa Automatic Alignment): Update.
+	(Xtensa Branch Relaxation): Mention limitation of unconditional jumps.
+	(Xtensa Call Relaxation): Linker can now remove most of the overhead.
+	(Xtensa Directives): Remove confusing rules about precedence.
+	(Density Directive, Relax Directive): Delete.
+	(Schedule Directive): New.
+	(Generics Directive): Rename to ...
+	(Transform Directive): ... this node.
+	(Literal Directive): Update for absolute literals.  Missing
+	literal_position directive is now an error.
+	(Literal Position Directive): Update for absolute literals.
+	(Freeregs Directive): Delete.
+	(Absolute Literals Directive): New.
+	(Frame Directive): Minor editing.
+	* Makefile.am (DEPTC_xtensa_elf, DEPOBJ_xtensa_elf, DEP_xtensa_elf):
+	Update dependencies.
+	* Makefile.in: Regenerate.
+
+2004-10-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn): Use fix_new rather than fix_new_exp
+	to build the second and third fixups for a composite relocation.
+	(macro_read_relocs): New function.
+	(macro_build): Use it.
+	(s_cpsetup): Pass all three composite relocation codes to macro_build.
+	Simplify fragging code accordingly.
+	(s_gpdword): Use fix_new rather than fix_new_exp for the second part
+	of the composite relocation.  Set fx_tcbit in both fixups.
+
+2004-10-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn): Set fx_tcbit for composite relocs.
+	(md_apply_fix3): Don't treat composite relocs as done.
+
+2004-10-07  Jan Beulich <jbeulich@novell.com>
+
+	* macro.c (macro_expand_body): When ELF, use .LL rather than LL as
+	prefix for symbol names generated from the LOCAL macro directive.
+
+	* dw2gencfi.c (select_cie_for_fde): When separating CIE out from
+	FDE, treat a DW_CFA_remember_state as we do a DW_CFA_advance_loc.
+
+2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (preprocess_reglist): Handle Co-processor
+	Special registers.
+	(md_assemble): Add error checking for Co-Processor instructions.
+	(get_cinv_parameters): Add 'b' option to invalidate the
+	branch-target cache.
+
+2004-10-05  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (unwind): New variable.
+	(vfp_sp_encode_reg): New function.
+	(vfp_sp_reg_required_here): Use it.
+	(vfp_sp_reg_list, vfp_dp_reg_list): Remove.
+	(vfp_parse_reg_list): New function.
+	(s_arm_unwind_fnstart, s_arm_unwind_fnend, s_arm_unwind_cantunwind,
+	s_arm_unwind_personality, s_arm_unwind_personalityindex,
+	s_arm_unwind_handlerdata, s_arm_unwind_save, s_arm_unwind_movsp,
+	s_arm_unwind_pad, s_arm_unwind_setfp, s_arm_unwind_raw): New
+	functions.
+	(md_pseudo_table): Add them.
+	(do_vfp_reg2_from_sp2): Use vfp_parse_reg_list and vfp_sp_encode_reg.
+	(do_vfp_sp2_from_reg2, vfp_sp_ldstm, vfp_dp_ldstm): Ditto.
+	(set_section, add_unwind_adjustsp, flush_pending_unwind,
+	finish_unwind_opcodes, start_unwind_section, create_unwind_entry,
+	require_hashconst, add_unwind_opcode): New functions.
+	* doc/c-arm.texi: Document unwinding opcodes.
+	* NEWS: Mention the new feature.
+
+2004-10-04  Eric Christopher  <echristo@redhat.com>
+
+	* config/tc-mips.c (md_apply_fix3): Remove erroneous assert.
+
+2004-10-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ppc.c (md_apply_fix3): Call S_SET_THREAD_LOCAL for
+	TLS relocations.
+	* config/tc-s390.c (md_apply_fix3): Likewise.
+	* config/tc-sparc.c (md_apply_fix3): Likewise.
+
+2004-10-01  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_elf_section_type): New function.
+	(arm_elf_change_section): Set section link for exidx sections.
+	* config/tc-arm.h (arm_elf_section_type): Add prototype.
+	(md_elf_section_type): Define.
+
+2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
+
+	* config/tc-pdp11.c (md_apply_fix3): Change to sign of the SOB
+	instruction's offset.
+
+2004-10-01  Adam Nemet  <anemet@lnxw.com>
+
+	* (TARGET_FORMAT): Remove LynxOS COFF definition.
+
+2004-10-01  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
+
+	* config/tc-arc.c (tc_gen_reloc): Don't assume fixP->fx_addsy is an
+	asymbol *, instead use symbol_get_bfdsym.
+
+2004-09-30  Linus Nielsen Feltzing  <linus@haxx.se>
+
+	* config/tc-m68k.c (select_control_regs): Add mcf5249.
+
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_smi, do_nop): New functions.
+	(insns): Add ARMv6ZK instructions.
+	(md_apply_fix3): Handle BFD_RELOC_ARM_SMI.
+	(tc_gen_reloc): Ditto.
+	(arm_cpus): Add mpcore and arm1176.
+	(arm_archs): Add armv6{k,z,zk}.
+	* doc/c-arm.texi: Document new cores and architectures.
+
+2004-09-30  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c: Use ISO C90 formatting.
+
+2004-09-30  Vladimir Ivanov  <vladitx@nucleusys.com>
+
+	* config/tc-arm.c (mav_reg_required_here): Allow REG_TYPE_CN
+	as alternative when REG_TYPE_MVF, REG_TYPE_MVD, REG_TYPE_MVFX or
+	REG_TYPE_MVDX is expected.
+
+2004-09-29  Marc Bevand  <m.bevand@gmail.com>
+
+	* doc/c-i386.texi (i386-Mnemonics): Fix typo.
+
+2004-09-21  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (ENCODED_PSP_OFFSET): New.
+	(output_rp_psprel, output_pfs_psprel, output_preds_psprel,
+	output_spill_base, output_unat_psprel, output_lc_psprel,
+	output_fpsr_psprel, output_priunat_psprel, output_bsp_psprel,
+	output_bsprestore_psprel, output_rnat_psprel, output_spill_psprel,
+	output_spill_psprel_p): Use it.
+
+2004-09-20  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (handle_LoadStor): New function.
+	Handle load/stor unique instructions before parsing.
+
+2004-09-17  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_rel31): New funciton.
+	(md_pseudo_table): Add .rel31.
+	(md_apply_fix3): Handle BFD_RELOC_ARM_TARGET2,
+	BFD_RELOC_32_PCREL and BFD_RELOC_ARM_PREL31.
+	(tc_gen_reloc): Handle BFD_RELOC_ARM_PREL31 and BFD_RELOC_ARM_TARGET2.
+	(arm_fix_adjustable): Return 0 for BFD_RELOC_ARM_TARGET2.
+	(arm_parse_reloc): Add (target2).
+
+2004-09-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* configure: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+	* po/gas.pot: Regenerate.
+
+2004-09-14  Hideki IWAMOTO  <h-iwamoto@kit.hi-ho.ne.jp>
+
+	* config/tc-mmix.c [!LLONG_MIN]: Correct #elsif to #elif.
+	[!LLONG_MAX]: Ditto.
+
+2004-09-13  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c: Rename RELABS to TARGET1.
+
+2004-09-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* messages.c (as_internal_value_out_of_range): Cast values passed
+	to as_bad_where or as_warn_where to proper type.
+
+2004-09-11  Theodore A. Roth  <troth@openavr.org>
+
+	* config/tc-avr.c: Add support for
+	atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
+
+2004-09-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* dw2gencfi.c (select_cie_for_fde): When separating CIE out
+	from FDE, treat a CFI_escape as we do a DW_CFA_advance_loc.
+
+2004-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/obj-elf.c (obj_elf_section_type): Handle init_array,
+	fini_array and preinit_array section types.
+	* config/tc-ia64.c (ia64_elf_section_type): Remove init_array
+	and fini_array.
+	* doc/as.texinfo: Document extra section types.
+
+2004-09-02  Mark Mitchell  <mark@codesourcery.com>
+
+	* Makefile.am (TARG_ENV_HFILES): Add te-symbian.h.
+	* Makefile.in: Regenerated.
+	* configure.in: Set em for arm*-*-symbianelf*.
+	* configure: Regenerated.
+	* config/tc-arm.c (elf32_arm_target_format): Use Symbian target
+	vectors when appropriate.
+	* config/te-symbian.h: New file.
+
+2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c (gettrap): Exception vector can be case
+	insensitive.
+	(process_label_constant): Fix a 32-bit displacement bug in branch
+	instructions.
+	(get_operandtype) : Bug fix, wrong operand was used.
+	(process_label_constant): Initialize relocation type to
+	BFD_RELOC_NONE
+
+2004-09-01  Richard Earnshaw < reanrsha@arm.com>
+
+	* tc-arm.c (arm_cpus, arm_fpus): Allow <cpu>-s as well as <cpu>s
+	for synthesizable cores.
+
+	* doc/c-arm.texi (ARM Options): Document canonical names of CPUs.
+
+2004-08-25  Dmitry Diky  <diwil@spec.ru>
+
+	* config/tc-msp430.c:	Clean-up the code.
+	(md_relax_table): New relax table.
+	(mcu_types): Sort MCU types.
+	(md_pseudo_table): Add .profiler pseudo handler.
+	(pow2value): New function.
+	(msp430_profiler): New function.
+	(msp430_operands): Add new insns handlers.
+	(msp430_srcoperand): Add register operand handler, allow complex
+	expressions.
+	(md_estimate_size_before_relax): Rewritten.
+	(md_convert_frag): Rewritten.
+	(msp430_relax_frag): New function.
+	* config/tc-msp430.h (md_relax_frag): define macro
+	* doc/c-msp430.texi: Update information.
+
+2004-08-24  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (std_shortopts): Allow -g to take an optional argument.
+	(parse_args): Pass any switch starting with -g on to the backend
+	for parsing.
+
+2004-08-18  Mark Mitchell  <mark@codesourcery.com>
+
+	* configure.in (arm*-*-symbianelf*): New target.
+	(arm*-*-eabi*): Likewise.
+	* configure: Regenerated.
+
+2004-08-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+	* config/tc-mips.c (append_insn): Handle delay slots in branch likely
+	correctly.
+
+2004-08-18  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/tc-ia64.c (start_unwind_section): Add linkonce_empty
+	argument, don't do anything if current section is not
+	.gnu.linkonce.t.* and linkonce_empty is set.
+	(generate_unwind_image, dot_endp): Adjust callers, call
+	start_unwind_section (*, 1) if nothing will be put into the
+	section.
+
+2004-08-17  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (MD_DEBUG_FORMAT_SELECTOR): Provide default definition.
+	(show_usage): Add -g.
+	(std_longopts): Add --gen-debug.  Alpha sort the table.
+	(parse_args): Print an error message if a switch is not handled.
+	Handle the -g switch, calling md_debug_format_selector() if
+	necessary.
+	* NEWS: Mention new feature.
+	* doc/as.texinfo: Document new switch.
+	* doc/internals.texi: Document behaviour of md_parse_option.
+
+	* config/tc-arm.c (md_parse_option): Do not issue an error message
+	if the switch is not recognised.
+	* config/tc-m68k.c (md_parse_option): Likewise.
+	* config/tc-pdp11.c (md_parse_option): Likewise.
+	* config/tc-v850.c (md_parse_option): Likewise.
+
+	* as.h: Fix up formatting.
+	* tc.h: Likewise.
+
+2004-08-16  Nick Clifton  <nickc@redhat.com>
+
+	* macro.c (macro_set_alternate): Use ISO C90 formatting.
+
+	* configure.in: Sort architecture based tables alphabetically.
+	* configure: Regenerate.
+
+2004-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (tc_ppc_regname_to_dw2regnum <regnames>): Replace
+	{ "cc", 68 }, with { "cr", 70 }.
+
+2004-08-13 Jan Beulich <jbeulich@novell.com>
+	   Nick Clifton <nickc@redhat.com>
+
+	* as.c: Add and handle new --alternate command line option.
+	* macro.c (macro_set_alternate): New.
+	* macro.h (macro_set_alternate): Declare.
+	* read.c: Add and handle new .altmacro and .noaltmacro directives.
+	* doc/as.texinfo: Document new command line option and pseudo-ops
+	as well as insert documentation originating from gasp about
+	alternate macro syntax.
+	* NEWS: Mention new command line option and pseudo-ops.
+
+2004-08-10  Mark Mitchell  <mark@codesourcery.com>
+
+	* expr.c (operand): Handle the "~", "-", and "!" operators applied
+	to bignums.
+
+2004-08-06  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix3, tc_gen_reloc, arm_parse_reloc):
+	Handle new relocations.
+	* include/elf/arm.h (elf_arm_reloc_type): Add new EABI relocations.
+
+2004-08-05  Bob Wilson  <bob.wilson@acm.org>
+
+	* write.c (relax_segment): Use was_address instead of address when
+	setting fr_fix field for align frag due to backwards .org.
+
+2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce SH2a support.
+	2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
+	* config/tc-sh.c (get_specific): Change arch_sh2a_up to
+	arch_sh2a_nofpu_up.
+	2004-02-24  Corinna Vinschen  <vinschen@redhat.com>
+	* config/tc-sh.c (md_parse_option): Add sh2a-nofpu ISA handling.
+	2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
+	* config/tc-sh.c (sh_elf_final_processing): Move sh2a recognition
+	to end of conditional expression.
+	2004-02-20  Corinna Vinschen  <vinschen@redhat.com>
+	* config/tc-sh.c: Add sh2a-nofpu support.
+	2003-12-29  DJ Delorie  <dj@redhat.com>
+	* tc-sh.c: Add sh2a support.
+	(parse_reg): Add tbr.
+	(parse_at): Support @@(disp,tbr).
+	(get_specific): Support sh2a opcodes.
+	(insert4): New, for 4 byte relocs.
+	(build_Mytes): Support sh2a opcodes.
+	(md_apply_fix3_Mytes): Support sh2a opcodes.
+	2003-12-02  Michael Snyder  <msnyder@redhat.com>
+	* config/tc-sh.c (md_parse_option): Handle sh2a.
+	(sh_elf_final_processing): Ditto.
+
+2004-07-27  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* config/tc-hppa.h (TARGET_FORMAT): Set to "elf32-hppa-netbsd"
+	for TE_NetBSD.
+
+2004-07-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_frob_file_before_adjust): Warn if .toc too big.
+	(ppc_arch): Expand comment.
+
+2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* config/tc-crx.c: Support evaluating the difference between two
+	symbols.
+	* config/tc-crx.h: Likewise.
+
+2004-07-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (start_unwind_section): Set the linked-to
+	section.
+	(ia64_elf_section_change_hook): Set the linked-to section for
+	SHT_IA_64_UNWIND.
+
+2004-07-26  Dmitry Diky  <diwil@spec.ru>
+
+	* config/tc-msp430.c: Add new subtargets: msp430x1610,
+	msp430x1611, msp430x1612, msp430x415, msp430x417, msp430xG437,
+	msp430xG438, msp430xG439.
+
+2004-07-25  Daniel Jacobowitz  <dan@debian.org>
+
+	* doc/as.texinfo (Section, PushSection): Correct documentation
+	for ELF.
+
+2004-07-21  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (optimize_imm): Adjust immediates to only those
+	permissible for the selected instruction suffix.
+	(match_template): Don't permit 64-bit general purpose operands in
+	32-bit mode.
+	(finalize_imm): Permit 64-bit immediates.
+	(build_modrm_byte): Don't treat 32-bit addressing in 64-bit mode
+	specially except for the width of the used base and/or index
+	registers.  For 32-bit displacements, use sign-extended
+	relocations only when using 64-bit addressing.
+	Force zero displacement on rip-relative addressing when there is
+	no other displacement.
+	(i386_index_check): Don't treat 32-bit addressing in 64-bit mode
+	specially except for the width of the used base and/or index
+	registers.
+	(parse_register): Disallow Reg64 registers in 32-bit mode.
+
+	* config/tc-i386.c: For DefaultSize instructions, don't guess a 'q'
+	suffix if the instruction doesn't support it.
+
+2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (append_insn): Handle constant expressions with
+	no associated relocation.
+	(mips_ip): Cancel the expression after use for the Q format
+	specifier.
+	(parse_relocation): Return no relocation for unsupported
+	operators.
+	(my_getSmallExpression): Return no relocation if no relocation
+	operators are used.
+
+2004-07-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/obj-som.c (adjust_stab_sections): Add prototype.
+	(obj_som_compiler, obj_som_version, obj_som_copyright,
+	adjust_stab_sections): Add ATTRIBUTE_UNUSED to unused arguments.
+	* config/tc-hppa.c (update_subspace):  Likewise.
+	(is_defined_subspace): Amplify comment.
+	* config/obj-som.h (som_frob_file): Add prototype.
+
+2004-07-19  Christopher Faylor  <cgf@timesys.com>
+	    H.J. Lu  <hongjiu.lu@intel.com>
+
+	* subsegs.c (section_symbol): Don't create a new segment when
+	existing segment is undefined.
+
+2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
+
+	* config/tc-arm.c: Include include/opcode/arm.h.
+	(ARM_EXT_*, ARM_ARCH_*, ARM_ANY, ARM_ALL, COPROC_ANY): Delete.
+	(FPU_FPA_EXT_* FPU_VFP_EXT_*, FPU_ANY, FPU_NONE, FPU_MAVERICK): Delete.
+	(FPU_ARCH_*): Delete.
+	* Makefile.am: Update dependencies.
+	* Makefile.in: Regenerate.
+
+2004-07-15  Nick Clifton  <nickc@redhat.com>
+
+	* configure.in: Accept armbe as a big-endian arm configuration.
+	* configure: Regenerate.
+
+2004-07-13  Thomas Nystrom  <thn@saeab.se>
+
+	* config/tc-i386.c (T_SHIFTOP): New constant.
+	(intel_e05_1): Handle '&', '|' and T_SHIFTOP.
+	(intel_el1): Handle '~'.
+	(intel_get_token): Handle '<>', '&', '|' and '~'.
+
+2004-07-13  Nick Clifton <nickc@redhat.com>
+
+	(md_assemble): Remove spurious newline from end of as_bad error
+	message.
+	(intel_e05_1): Likewise.
+	(intel_e11): Likewise.
+	(intel_match_token): Likewise.
+
+2004-07-11  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-m68k.c: Convert to C90.  Remove redundant
+	declarations.  Indentation fixup.
+	[M68KCOFF]: Include "obj-coff.h" instead of declaring
+	obj_coff_section ourselves.
+
+2004-07-09  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (default_big_endian): New.
+	(dot_byteorder, md_begin): Use it.
+	(md_parse_option): Set it.
+
+2004-07-09  Nick Clifton  <nickc@redhat.com>
+
+	* configure.in: Change sh-sybmian-elf to sh-*-symbianelf.
+	* configure: Regenerate.
+	* NEWS: Change sh-sybmian-elf to sh-*-symbianelf.
+	* config/tc-sh.c (sh_elf_final_processing): Use renamed version of
+	sh_find_elf_flags if necessary.
+
+2004-07-08  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (mips_fix_adjustable): If the full addend is
+	going to be split into more than one in-place addend, return 0
+	for relocations against mergeable sections.  Associate comments
+	with code.
+
+2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* Makefile.am (CPU_TYPES): Add crx.
+	(TARGET_CPU_CFILES): Add config/tc-crx.c.
+	(TARGET_CPU_HFILES): Add config/tc-crx.h.
+	(DEPTC_crx_elf): New target.
+	(DEPOBJ_crx_elf): Likewise.
+	(DEP_crx_elf): Likewise.
+	* Makefile.in: Regenerate.
+	* configure.in: Add crx* target.
+	* configure: Regenerate.
+	* config/tc-crx.c: New file.
+	* config/tc-crx.h: New file.
+	* NEWS: Mention new target.
+
+2004-07-06  Nick Clifton  <nickc@redhat.com>
+
+	* config.in: Undefine TARGET_SYMBIAN by default.
+	* configure.in:
+	* configure: Regenerate. Add sh-symbian-elf target.  If
+	selected define TARGET_SYMBIAN.
+	* config/tc-sh.h (TARGET_FORMAT): Select a Symbian target
+	format if TARGET_SYMBIAN has been defined.
+
+	* output-file.c (output_file_create): Report the target format
+	chosen when bfd_openw reports that it is invalid.
+
+	* config/obj-coff.c (coff_pseudo_table): Only define the weak
+	pseudo for BFD based assemblers.
+
+2004-07-05  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	gas:
+	* config/tc-sh.c (md_assemble): Change isspace to ISSPACE.
+	(md_parse_option): Remove redundant -isa testing.
+	Make bfd_arch variable const.
+	(md_show_usage): Make bfd_arch variable const.
+
+2004-07-03  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Check and set insn_addr.
+	* config/tc-ia64.h (md_frag_check): Define.
+
+2004-07-03  Aaron W. LaFramboise  <aaron98wiridge9@aaronwl.com>
+
+	* config/obj-coff.c (obj_coff_weak): New .weak syntax for PE weak
+	externals.
+	* doc/as.texinfo (Weak): Document PE weak symbols.
+
+2004-07-03  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (HAVE_IN_PLACE_ADDENDS): New macro.
+	(reloc_needs_lo_p): Only return true if HAVE_IN_PLACE_ADDENDS.
+	(mips_frob_file): Rework so that only a single pass through the
+	relocs is needed.  Allow %lo()s to have higher offsets than their
+	corresponding %hi()s or %got()s.
+
+2004-07-02  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (md_apply_fix3:BFD_RELOC_ARM_IMMEDIATE): Do not
+	allow values which have come from undefined symbols.
+	Always consider this fixup to have been processed as a reloc
+	cannot be generated for it.
+
+2004-07-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* frags.h (struct frag): Add has_code and insn_addr fields.
+	* write.c (cvt_frag_to_fill): Invoke md_frag_check.
+	* config/tc-ppc.c (md_assemble): Check and set insn_addr.
+	* config/tc-ppc.h (md_frag_check): Define.
+
+2004-06-28  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* doc/Makefile.am (info): Rename goal to...
+	(info-local): ... this, to preserve implicit dependencies.
+	* doc/Makefile.in: Regenerate with automake 1.8.5.
+
+2004-06-25  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (md_convert_frag): Changed for @PLT.
+	(m32r_cgen_record_fixup_exp): Changed for  @GOTOFF, @GOT.
+	(m32r_fix_adjustable): Changed for  @GOTOFF, @GOT, @PLT.
+	(tc_gen_reloc): Likewise.
+	(m32r_end_of_match): Add for @GOTOFF, @GOT, @PLT.
+	(m32r_parse_name): Likewise.
+	(m32r_cgen_parse_fix_exp): Likewise.
+	* config/tc-m32r.h (md_parse_name): Define for @GOTOFF, @GOT, @PLT.
+	(O_PIC_reloc): Likewise.
+	(TC_CGEN_PARSE_FIX_EXP): Likewise..
+	* cgen.c (gas_cgen_parse_operand): Add TC_CGEN_PARSE_FIX_EXP
+	for @GOTOFF, @GOT, @PLT.
+
+2004-06-21 Jan Beulich  <jbeulich@novell.com>
+
+	* gas/symbols.c: While discarding ordinary local absolute symbols
+	when --strip-local-absolute is in effect, retain file symbols.
+
+2004-06-20  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-m68k.c (mri_chip): Replace current_chip, not augment.
+	(md_parse_option): Likewise.
+
+2004-06-17  Jan Beulich <jbeulich@novell.com>
+
+	* config/tc-i386.c: Deal with LEX_QM the same way as with LEX_AT.
+	* config/te-netware.h: New file.
+	* config/te-ppcnw.h: Delete: Obsolete.
+	* configure.in: Eliminate ill NetWare targets. Make generic
+	NetWare target use proper emulation.
+	* Makefile.am: Eliminate reference to obsolete te-ppcnw.h, add
+	reference to new te-netware.h.
+	* configure: Regenerate.
+	* Makefile.in: Regenerate.
+
+2004-06-15  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* config/tc-s390.c (s390_insn): Avoid incorrect signed/unsigned
+	comparison in .insn pseudo operation.
+
+2004-06-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-coff.c (coff_adjust_section_syms): Use
+	bfd_get_section_size instead of bfd_get_section_size_before_reloc.
+	(coff_frob_section): Likewise.
+	* config/tc-mips.c (md_apply_fix3): Likewise.
+	* config/obj-elf.c (elf_frob_file): Use bfd_set_section_size.
+	(elf_frob_file_after_relocs): Likewise.
+
+2004-06-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/tc-hppa.c (log2): Rename to exact_log2.
+	(pa_next_subseg): Delete unused function.
+	(create_new_space): Mark unused arguments with ATTRIBUTE_UNUSED.
+	(create_new_subspace): Likewise.
+
+	Bug gas/213
+	* config/tc-hppa.c (hppa_fix_adjustable): Allow reduction of fake
+	labels.  Fix warning.
+
+2004-05-28  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-mn10300.h (tc_fix_adjustable): Define.
+	* config/tc-mn10300.c (mn10300_fix_adjustable): Don't adjust debug
+	or non-merged symbols.
+
+2004-05-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (remove_marked_resource): Save, clear and
+	restore the old slot when inserting srlz.i/srlz.d.
+
+2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	* Makefile.am: Regenerate dependecies.
+	* Makefile.in: Regenerate.
+	* config/tc-sh.c (valid_arch): Make unsigned.
+	(preset_target_arch): Likewise.
+	(md_begin): Use new architecture flags system.
+	(get_specific): Likewise.
+	(assemble_ppi): Likewise.
+	(md_assemble): Likewise. Also fix error check for bad opcodes.
+	(md_parse_option): Likewise. Also generate -isa values according
+	to the table in bfd/cpu-sh.c instead of just constants. Also
+	allow <arch>-up ISA variants.
+	(sh_elf_final_processing): Replace if-else chain with a call to
+	sh_find_elf_flags().
+
+2004-05-28  Peter Barada <peter@the-baradas.com>
+
+	* config/gc-m68k.c(m68k_ip): Convert mode 5 addressing
+	with zero offset into mode 2 addressing to save a word.
+
+2004-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (ar_is_in_integer_unit): Removed.
+	(ar_is_only_in_integer_unit): New.
+	(ar_is_only_in_memory_unit): New.
+	(generate_unwind_image): Silence gcc on 32bit host.
+	(md_assemble): Use ar_is_only_in_integer_unit instead of
+	ar_is_in_integer_unit. Check AR access.
+
+2004-05-27  Peter Barada  <peter@the-baradas.com>
+
+	* config/tc-m68k.c (md_begin): Sort the opcode table into
+	alphabetical order.
+	(m68k_compare_opcode): New function to do the sorting.
+
+2004-05-24  Peter Barada  <peter@the-baradas.com>
+
+	* config/m68k-parse.y(operand): Allow for MAC/EMAC mask
+	addressing on MIT style operands.
+	* config/m68k-parse.y(yylex): Allow '-&' for predecrement
+	w/mask addressing.
+	* config/tc-m68k.c(install_operand): Comment 'G' and 'H' type
+	operands.
+
+2004-05-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* expr.c (operand, operator): Don't reject '++' and '--'.
+
+2004-05-20  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn): Use ISA-encoded addresses in MIPS16
+	dwarf tables.
+
+2004-05-17  Adam Nemet  <anemet@lnxw.com>
+
+	* configure.in: Add ppc-*-lynxos*.  Update i386-*-lynxos* to ELF.
+	* configure: Regenerate.
+
+2004-05-13  Paul Brook  <paul@codesourcery.com>
+
+	* dw2gencfi.c (output_cie):  Handle dwarf3 format CIE entries.
+
+2004-05-13  Joel Sherrill <joel@oarcorp.com>
+
+	* configure.in (or32-*-rtems*): Switch to elf.
+	* configure: Regenerate.
+
+2004-05-13  Nick Clifton  <nickc@redhat.com>
+
+	* po/fr.po: Updated French translation.
+
+2004-05-11  Nick Clifton  <nickc@redhat.com>
+
+	* doc/as.texinfo (Section): Document G and T flags to .section
+	directive.  Document the extra arguments that the G flag
+	requires.  Document the #tls flag.
+
+2004-05-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* subsegs.c (section_symbol): Create a new section symbol if
+	the existing one doesn't match.
+	* symbols.c (symbol_set_bfdsym): Don't reset BFD section symbol.
+
+2004-05-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn, mips_emit_delays): Extend -mfix-vr4120
+	to cope with VR4181A errata MD(1) and MD(4).
+
+2004-05-07  Brian Ford  <ford@vss.fsi.com>
+
+	* NEWS: Mention .secrel32 for pe[i]-i386.
+
+2004-05-07  Alexandre Oliva  <aoliva@redhat.com>
+
+	* config/tc-frv.h (MAX_MEM_FOR_RS_ALIGN_CODE): New.
+	(HANDLE_ALIGN): New.
+
+2004-05-06  Daniel Jacobowitz  <dan@debian.org>
+
+	* Makefile.am (DIST_SUBDIRS): Define.
+	* aclocal.m4: Regenerate with automake 1.8.4.
+	* Makefile.in: Likewise.
+	* doc/Makefile.in: Likewise.
+
+2004-05-06  David Mosberger-Tang  <davidm@hpl.hp.com>
+
+	* config/tc-ia64.c (dot_serialize): Declare.
+	(dot_serialize): New function.
+	(md_pseudo_table): Add ".serialize.data" and
+	".serialize.instruction" directives.
+
+2004-05-06  Nick Clifton  <nickc@redhat.com>
+
+	* messages (as_internal_value_out_of_range): Print a message about
+	a value being out of range.  Be consistent about whether the
+	values are printed in decimal or hexadecimal.
+	(as_warn_value_out_of_range): Generate a warning message about an
+	out of range value.
+	(as_bad_value_out_of_range): Generate an error message about an
+	out of range value.
+	* as.h: Prototype the new functions.
+	* config/tc-alpha.c (insert_operand): Use new function.
+	* config/tc-arc.c (arc_insert_operand): Likewise.
+	* config/tc-mn10200.c (mn10200_insert_operand): Likewise.
+	* config/tc-mn10300.c (mn10300_insert_operand): Likewise.
+	* config/tc-ppc.c (ppc_insert_operand): Likewise.
+	* config/tc-s390.c (s390_insert_operand): Likewise.
+	* config/tc-v850.c (v850_insert_operand): Likewise.
+
+2004-05-05  Alexandre Oliva  <aoliva@redhat.com>
+
+	* configure.in: Set em=linux for frv-*-*linux*.
+	* configure: Rebuilt.
+	* config/tc-frv.h (TARGET_FORMAT): Use elf32-frvfdpic if...
+	(frv_md_fdpic_enabled): New.
+	* config/tc-frv.c (frv_md_fdpic_enabled): New.
+	(DEFAULT_FDPIC): New.
+	(frv_flags): Use DEFAULT_FDPIC.
+	(frv_pic_flag): Likewise.
+	(OPTION_NOPIC): New.
+	(md_longopts): Add -mnopic.
+	(md_parse_option): Handle it.
+	(md_show_usage): Add -mfdpic and -mnopic.
+
+2004-05-05  Peter Barada  <peter@the-baradas.com>
+
+	* config/tc-m68k.c: Add find_cf_chip to print list of valid
+	chips for invalid coldfire instructions, rename selectors
+	for ColdFire sub-variants, add 521x,5249,547x,548x and aliases,
+	add current_chip to track which chip is referred to(including save/restore),
+	use current_chip to select control registers, not current_arch.
+	(md_show_usage): Add new chips.
+	* doc/c-m68k.texi: Document new command line switches.
+
+2004-05-05  Jakub Jelinek  <jakub@redhat.com>
+
+	* tc-s390.h (md_do_align, HANDLE_ALIGN): Remove.
+	(NOP_OPCODE): Define.
+	(s390_align_code): Remove prototype.
+	* tc-s390.c (s390_align_code): Remove.
+
+2004-05-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (make_unw_section_name): Removed.
+	(start_unwind_section): New function.
+	(generate_unwind_image): Take const segT instead of const
+	char *.
+	(dot_handlerdata): Adjusted.
+	(dot_endp): Likewise.
+
+2004-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-elf.c (obj_elf_change_section): Allow the
+	".note.GNU-stack" section has SHF_EXECINSTR.
+
+2004-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-elf.c (get_section): Return bfd_boolean.
+	(obj_elf_change_section): Call bfd_get_section_by_name_if
+	instead of bfd_map_over_sections.
+
+2004-04-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-elf.c (get_section): New function.
+	(obj_elf_change_section): Support multiple sections with same
+	name.
+
+2004-04-30  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (create_register_alias): Fix typo checking for
+	case sensitive register aliases.
+	(co_proc_number): Use error message string in all_reg_maps[]
+	array.
+	(cp_reg_required_here): Likewise.
+	(fp_reg_required_here): Likewise.
+
+2004-04-29  Brian Ford  <ford@vss.fsi.com>
+
+	* dwarf2dbg.c (dwarf2_finish): Add SEC_DEBUGGING to section flags.
+
+2004-04-28  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.c (HAVE_32BIT_ADDRESSES, append_insn, macro_build)
+	(load_address, macro, mips_ip, md_parse_option)
+	(mips_force_relocation, mips_validate_fix, md_apply_fix3)
+	(s_change_sec, pic_need_relax, tc_gen_reloc): Remove all
+	embedded-PIC handling, and update comments.
+	(SWITCH_TABLE): Remove.
+	* config/tc-mips.h (DIFF_EXPR_OK): Delete.
+	(enum mips_pic_level): Remove EMBEDDED_PIC.
+	(EXTERN_FORCE_RELOC): Remove embedded-PIC handling.
+	(TC_FORCE_RELOCATION): Update comment.
+	* ecoff.c (ecoff_build_lineno): Add comment about some code that
+	might be safe to remove now that MIPS embedded-PIC is gone.
+
+2004-04-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/obj-som.c (obj_som_init_stab_section): Add new arguments in
+	call to obj_set_subsection_attributes.
+	(obj_som_init_stab_section): Likewise.
+	* config/tc-hppa.c (default_subspace_dict): Add comdat field.
+	(pa_def_subspaces): Provide comdat default.
+	(pa_subspace): Handle new "comdat" parameter.  Set SEC_LINK_ONCE and
+	not SEC_IS_COMMON if section is comdat, common or dup_common.  Update
+	calls to create_new_subspace and update_subspace to pass comdat flag.
+	(create_new_subspace, update_subspace): Add new comdat argument.  Use
+	it in calls to obj_set_subsection_attributes.
+	* doc/c-hppa.texi (.subspa, .nsubspa): Document new comdat parameter
+	and use of comdat, common and dup_comm parameters.
+
+2004-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-elf.c (obj_elf_change_section): Check if the old
+	group name is NULL before comparison.
+
+2004-04-23  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.h (mips_dwarf2_addr_size): Prototype.
+
+2004-04-23  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (s_mipsset): Set default CPU type for .set mipsN.
+
+2004-04-23  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.c (md_longopts): Remove -membedded-pic option.
+	(OPTION_MEMBEDDED_PIC): Remove.
+	(OPTION_TRAP, OPTION_BREAK, OPTION_EB, OPTION_EL)
+	(OPTION_FP32, OPTION_GP32, OPTION_CONSTRUCT_FLOATS)
+	(OPTION_NO_CONSTRUCT_FLOATS, OPTIONS_FP64, OPTION_GP64)
+	(OPTION_RELAX_BRANCH, OPTION_NO_RELAX_BRANCH)
+	(OPTION_ELF_BASE): Renumber.
+	(md_parse_option): Remove OPTION_MEMBEDDED_PIC handling.
+	(md_show_usage): Remove mention of -membedded-pic.
+	* doc/as.texinfo: Remove mention of -membedded-pic.
+
+2004-04-23  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.h (USE_GLOBAL_POINTER_OPT): Remove.
+	* config/tc-mips.c (RDATA_SECTION_NAME, mips_target_format): Remove
+	a.out support.
+	(md_begin, mips_ip, md_parse_option, s_change_sec, s_option,
+	s_abicalls, nopic_need_relax, tc_gen_reloc): Remove uses of
+	USE_GLOBAL_POINTER_OPT.
+
+2004-04-22  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (macro): One more use of load_delay_nop.
+
+2004-04-22  Atsushi Nemoto  <anemo@mba.ocn.ne.jp>
+
+	* config/tc-mips.c (load_delay_nop): New function.
+	(load_address, macro): Use load_delay_nop() to build a nop
+	which can be omitted with gpr_interlocks.
+
+2004-04-22  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (hilo_interlocks, gpr_interlocks,
+	cop_interlocks): Remove superfluous CPU entries.
+
+2004-04-22  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (mav_parse_offset): Value must be multiple of 4.
+
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* NEWS: Added support for EMAC instructions and MAC/EMAC
+	Motorola syntax.
+	* config/m68k-parse.h: Add ACC[123], ACCEXT{01,23}, MAC/EMAC
+	scale factor tokens, trailing_ampersand to mark mask addressing
+	for MAC/EMAC instructions.
+	* config/m68k-parse.y: Add options_ampersand clause, '<<',
+	'>>'.
+	(yylex): Handle '>', '<', and '&' following '+'.
+	* config/tc-m68k.c: Set mcfmac/mcfemac on appropriate ColdFire
+	architectures in archs[].
+	(m68k-ip): Add '4', 'e', 'g', 'i', cases to handle mask addressing
+	for MAC/EMAC instructions, ACC[0123], ACCEXT{01,23}, and '<<'/'>>'
+	respectively.
+	(m68k_ip): Handle trailing '&' on MAC/EMAC insns.
+	(install_operand): Fix 'n' case, Add 'F', 'f', 'G', 'H', 'I', ']'
+	cases.
+	Add EMAC operands to init_table[].
+
+2004-04-22  Bruno De Bus <bdebus@elis.ugent.be>
+
+	* config/tc-arm.h (enum mstate): Move here, add MAP_UNDEFINED
+	state.
+	(TC_SEGMENT_INFO_TYPE): Define to enum mstate.
+	* config/tc-arm.c (enum mstate): Delete from here.
+	(mapping_state): Remove the static mapstate variable and instead
+	store the state in the segment.  This allows a per-section mapping
+	state.  Handle and ignore MAP_UNDEFINED states.
+	(arm_elf_change_section): Get the current mapping state from the
+	new section.
+	(s_ltorg): Set the mapping state to MAP_DATA.
+	(arm_cleanup): Use arm_elf_change_section to get the mapping state
+	for each pool as it is emitted.
+
+2004-04-22  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.h: Formatting tidy ups.
+
+2004-04-20  Chris Demetriou  <cgd@broadcom.com>
+
+	* NEWS: Note that MIPS -membedded-pic option is deprecated.
+
+2004-04-20  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-i386.h [TE_PE] (TC_CONS_FIX_NEW): Define.
+	* config/tc-i386.c (md_pseudo_table) [TE_PE]: Add "secrel32".
+	[TE_PE] (O_secrel): Define.
+	[TE_PE] (x86_pe_cons_fix_new): New.
+	[TE_PE] (pe_directive_secrel): Likewise.
+	(tc_gen_reloc) [TE_PE]: Support BFD_RELOC_32_SECREL.
+
+2004-04-19  Eric Christopher  <echristo@redhat.com>
+
+	* config/tc-mips.c (mips_dwarf2_addr_size): Revert part
+	of previous patch for fix in gcc.
+
+2004-04-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/tc-xtensa.c (xg_assembler_literal): Fix a typo.
+
+2004-04-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* read.c (do_align): Call md_flush_pending_output, if defined.
+
+2004-04-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* expr.c (operand): Correct checks for ++ and --.
+
+2004-04-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-generic.c: Add some comments.
+
+2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+
+	* doc/c-mips.texi (-m{no-,}fix-vr4120): Renamed from
+	-{no-}mfix-vr4122-bugs.
+	* config/tc-mips.c (mips_fix_vr4120): Renamed from mips_fix_4122_bugs.
+	(append_insn, mips_emit_delays): Update accordingly.
+	(OPTION_FIX_VR4120, OPTION_NO_FIX_VR4120): Renamed from *VR4122.
+	(md_longopts): Change -{no-,}mfix-vr4122-bugs to -m{no-,}fix-vr4120.
+	(md_parse_option): Update after above changes.
+	(md_show_usage): Add -mfix-vr4120.
+
+2004-04-13  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/as.texinfo (Sub-Sections): Conditionalize COFF-specific use
+	of .section directive; add a reference to the ELF .subsection
+	directive.
+
+2004-04-13  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (md_assemble): Fixed infinite loop bug
+	in parallel.
+
+2004-04-11  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* Makefile.am: Remove mips from aout targets.
+	* Makefile.in: Regenerate.
+	* configure.in: Remove mips-dec-bsd* target.
+	* configure: Regenerate.
+
+2004-04-07  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 96
+	* config/tc-ppc.c (ppc_elf_suffix): Add valid32 and valid64 fields
+	to struct map_bfd.  Adjust MAP macro, and define MAP32, MAP64.
+	Update "mapping".  Restrict some @ modifiers to 32 bit.
+
+2004-04-01  Asgari Jinia  <asgarij@kpitcummins.com>
+	    Dhananjay Deshpande <dhananjayd@kpitcummins.com>
+
+	* config/tc-sh.c (dont_adjust_reloc_32): New variable.
+	(sh_fix_adjustable): Avoid adjusting BFD_RELOC_32 when
+	dont_adjust_reloc_32 is set.
+	(md_longopts): Add option -renesas.
+	(md_parse_option, md_show_usage): Likewise.
+	* doc/c-sh.texi: Likewise.
+
+2004-04-01  Dave Korn  <dk@artimi.com>
+
+	* config/tc-dlx.c (md_assemble): set fx_no_overflow flag for
+	hi16 and lo16 fixS structs.
+	(md_assemble): generate bit_fixS for RELOC_DLX_LO16 in
+	exactly the same way as for RELOC_DLX_REL16.
+	(machine_ip): properly respect LO flag in the_insn and
+	output RELOC_DLX_LO16 rather than RELOC_DLX_16.
+	(md_apply_fix3): apply RELOC_DLX_LO16.
+
+2004-03-30  Stan Shebs  <shebs@apple.com>
+
+	Remove long-obsolete MPW support.
+	* mpw-config.in, mpw-make.sed, mac-as.r: Remove files.
+	* configure.in: Remove mention of ppc-*-mpw* config.
+	* configure.in: Likewise.
+
+2004-03-30  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (meabi_flags): Make its use conditional upon
+	OBJ_ELF being defined.
+
+2004-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-aout.c (obj_aout_type): Remove #ifdef BFD_ASSEMBLER code.
+
+2004-03-23  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (meabi_flags): New variable.
+	(arm_parse_eabi): New function.
+	(md_begin): Set flags for EABI v3.
+	(arm_eabis): Add.
+	(arm_long_opts): Add meabi.
+	* doc/as.texinfo <ARM>: Document -meabi.
+	* doc/c-arm.texi: Ditto.
+
+2004-03-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_post_relax_hook): Create literal
+	tables even when use_literal_section flag is not set.
+
+2004-03-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-sh.c: Remove trailing whitespace.
+
+2004-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* doc/c-cris.texi (CRIS-Opts): Document --no-mul-bug-abort,
+	--mul-bug-abort and the default behavior.
+	* config/tc-cris.c (cris_insn_kind): New member CRIS_INSN_MUL.
+	(err_for_dangerous_mul_placement): New variable.
+	(STATE_MUL, OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): New
+	macros.
+	(md_cris_relax_table): Have placeholder for STATE_MUL.
+	(md_longopts): New options --mul-bug-abort and --no-mul-bug-abort.
+	(cris_relax_frag) <case ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: New
+	case doing nothing.
+	(md_estimate_size_before_relax) <case ENCODE_RELAX (STATE_MUL,
+	STATE_BYTE)>: Ditto.
+	(md_convert_frag) <ENCODE_RELAX (STATE_MUL, STATE_BYTE)>: Check
+	alignment and position of this frag, emit error message if
+	suspicious.
+	(md_assemble): For a multiply insn and when checking it,
+	transform the current frag into a special frag for that purpose.
+	(md_parse_option) <case OPTION_MULBUG_ABORT_OFF, case
+	OPTION_MULBUG_ABORT_ON>: Handle new options.
+
+2004-03-19  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (mark_literal_frags): New function.
+	(xtensa_move_literals): Call mark_literal_frags for all literal
+	segments, including init and fini literal segments.
+	(xtensa_post_relax_hook): Swap use of xt_insn_sec and xt_literal_sec.
+
+2004-03-19  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* tc-hppa.c (cons_fix_new_hppa): Check for PC relative base type.
+	(pa_comm): Set BSF_OBJECT in symbol flags.
+
+2004-03-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* config.in: Regenerate.
+	* po/gas.pot: Regenerate.
+
+2004-03-18  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* read.c (read_a_source_file): Use demand_empty_rest_of_line.
+	(demand_empty_rest_of_line): Issue an error here.
+	(ignore_rest_of_line): Silently skip to end.
+	(demand_copy_string): Issue an error, not warning.
+	(equals): Likewise.
+	* config/obj-elf.c (obj_elf_section_name): Likewise.
+	(obj_elf_section): Likewise.
+	* config/tc-arc.c (arc_extoper): Remove bogus NULL checks.
+	(arc_extinst): Likewise.
+	* config/tc-ia64.c (dot_saveb): Use demand_empty_rest_of_line.
+	(dot_spill): Likewise.
+	(dot_unwabi): Likewise.
+	(dot_prologue): Likewise.
+
+	* expr.c (operand): Reject ++ and --.
+	(operator): Likewise.
+
+2004-03-17  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c: Include dw2gencfi.h.
+	(sh_cfi_frame_initial_instructions): New function.
+	(sh_regname_to_dw2regnum): Likewise.
+	* config/tc-sh.h (DWARF2_LINE_MIN_INSN_LENGTH): Move to the end of
+	file.
+	(TARGET_USE_CFIPOP): Define.
+	(tc_cfi_frame_initial_instructions): Likewise.
+	(tc_regname_to_dw2regnum): Likewise.
+	(DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT): Likewise.
+	* Makefile.am: Update dependencies.
+	* Makefile.in: Regenerate.
+
+2004-03-17  Ralf Corsepius <corsepiu@faw.uni-ulm.de>
+
+	* configure.in: Switch sh-*-rtems* to ELF.  Add sh-*-rtemscoff*.
+	* configure: Regenerate.
+
+2004-03-12  Bob Wilson  <bob.wilson@acm.org>
+
+	* read.c (s_leb128): Call md_flush_pending_output.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* config/tc-i386.c (output_insn): Handle PadLock instructions.
+	* config/tc-i386.h (CpuPadLock): New define.
+	(CpuUnknownFlags): Added CpuPadLock.
+
+2004-03-07  Andreas Schwab  <schwab@suse.de>
+
+	* doc/c-hppa.texi (HPPA Directives): Fix typo.
+
+2004-03-07  Richard Henderson  <rth@redhat.com>
+
+	* dw2gencfi.c (output_cie): Align length to 4 byte boundary.
+	(cfi_finish): Likewise for fde.
+
+2004-03-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (md_assemble): Properly handle NULL
+	align_frag.
+	(ia64_handle_align): Don't abort if failed to add a stop bit.
+
+2004-03-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.in: Regenerated.
+	* aclocal.m4: Likewise.
+	* configure: Likewise.
+	* doc/Makefile.in: Likewise.
+
+2004-03-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (dot_align): New.
+	(ia64_do_align): Make it static.
+	(md_pseudo_table): Use "dot_align" for "align".
+	(ia64_md_do_align): Don't set align_frag here.
+	(ia64_handle_align): Add a stop bit to the previous bundle if
+	needed.
+
+	* config/tc-ia64.h (ia64_do_align): Removed.
+
+2003-03-03  Andrew Stubbs  <andrew.stubbs@superh.com>
+
+	* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
+	-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
+	(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
+	the most general type or the user specifically requested it.
+	(md_assemble): Add a new error message for when an instruction
+	is understood, but is not allowed due to an -isa option.
+
+2004-03-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (align_frag): New.
+	(md_assemble): Set the tc_frag_data field in align_frag for
+	IA64_OPCODE_FIRST instructions.
+	(ia64_md_do_align): Set align_frag.
+	(ia64_handle_align): Add a stop bit if needed.
+
+	* config/tc-ia64.h (TC_FRAG_TYPE): New.
+	(TC_FRAG_INIT): New.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-frv.c (fr400_audio): New variable.
+	(md_parse_option, md_show_usage): Add -mcpu=fr405 and -mcpu=fr450.
+	(md_parse_option): Set fr400_audio for -mcpu=fr400 and -mcpu=fr405.
+	(target_implements_insn_p): New function.
+	(md_assemble): Report an error if the processor doesn't implement
+	the instruction.
+
+2004-02-27  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (md_longopts): Added -no-bitinst option.
+	(md_parse_option): Ditto.
+	(OPTION_NO_SPECIAL_M32R): Added.
+	(md_show_usage): Document it.
+	(enable_speial_m32r): Changed a default value from 0 to 1.
+	* doc/c-m32r.texi: Document the -no-bitinst option.
+
+2004-02-27  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (get_operand): Revert previous delta.
+	(tc_gen_reloc): Check for an unknown reloc type before processing
+	the addend.
+
+2004-02-27  Hannes Reinecke  <hare@suse.de>
+
+	* config/tc-s390.c (s390_insn): Correct range check for opcode in
+	.insn pseudo operation.
+
+2004-02-27  Anil Paranjpe  <anilp1@kpitcummins.com>
+
+	* config/tc-sh.c (get_operand):  In case of #Imm, check has been
+	added for wrong syntax.
+
+2004-02-26  Eric Christopher  <echristo@redhat.com>
+
+	* config/tc-mips.c (mips_dwarf2_addr_size): New.
+	* config/tc-mips.h (DWARF2_ADDR_SIZE): Use.
+
+2004-02-26  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	* config/tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
+	nibble types to assembler.
+
+2004-02-25  Fred Fish  <fnf@redhat.com>
+
+	* config/tc-iq2000.c: Add missing \n\ in multiline string literal.
+
+2004-02-20  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (slot_index): New arg before_relax.  Use instead of
+	finalize_syms.
+	(fixup_unw_records): New arg before_relax.  Pass to slot_index.
+	(ia64_estimate_size_before_relax): New.
+	(ia64_convert_frag): Pass 0 to fixup_unw_records.  Add comment.
+	(generate_unwind_image): Pass 1 to fixup_unw_records.
+	* config/tc-ia64.h (ia64_estimate_size_before_relax): Declare.
+	(md_estimate_size_before_relax): Call ia64_estimate_size_before_relax.
+
+2004-02-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* stabs.c (generate_asm_file): Avoid warning about use of
+	uninitialized variable.
+
+2004-02-18  David Mosberger  <davidm@hpl.hp.com>
+
+	* config/tc-ia64.c (ia64_flush_insns): In addition to prologue,
+	body, and endp, allow unwind records which do not have a "t"
+	(time/instruction) field.
+
+2004-02-17  Petko Manolov  <petkan@nucleusys.com>
+
+	* config/tc-arm.c (do_mav_dspsc_1): Correct offset of CRn.
+	(do_mav_dspsc_2): Likewise.
+	Fix accumulator registers move opcodes.
+
+2004-02-13  Hannes Reinecke  <hare@suse.de>
+	    Jakub Jelinek  <jakub@redhat.com>
+
+	* dwarf2dbg.c (get_filenum): Do not read beyond allocated memory.
+
+2004-02-10  Steve Ellcey  <sje@cup.hp.com>
+
+	* config/tc-ia64.h (ia64_frob_symbol): New declaration.
+	(tc_frob_symbol): New macro definition.
+	* config/tc-ia64.c (ia64_frob_symbol): New routine.
+
+2004-02-09  Daniel Jacobowitz  <drow@mvista.com>
+
+	* config/tc-arm.c (md_begin): Mark .note.gnu.arm.ident as
+	read-only.
+
+2004-02-09  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* read.h (IGNORE_OPCODE_CASE): Do not define. Replace with ...
+	(TC_CASE_SENSITIVE): ... this.
+	* read.c: Replace IGNORE_OPCODE_CASE with TC_CASE_SENSITIVE.
+	* doc/internals.texi (TC_CASE_SENSITIVE): Document.
+
+2004-02-06  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (dot_endp): Delete call to output_endp.
+	(generate_unwind_image): Re-add it here.
+
+2004-02-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* dwarf2dbg.c (DWARF2_ADDR_SIZE): Remove trailing ';'
+	* read.h (SKIP_WHITESPACE): Turn into an expression.
+	* read.c (read_a_source_file): A pseudo is removed by having a
+	NULL handler.
+
+2004-02-05  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (output_endp): New.
+	(count_bits): Delete.
+	(ia64_flush_insns, process_one_record, optimize_unw_records): Handle
+	endp unwind records.
+	(fixup_unw_records): Handle endp unwind records.  Delete code for
+	shortening prologue regions not followed by a body record.
+	(dot_endp): Call add_unwind_entry to emit endp unwind record.
+	* config/tc-ia64.h (unw_record_type): Add endp.
+
+2004-02-03  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (ia64_convert_frag): Call md_number_to_chars to
+	fill padding bytes with zeroes.
+	(emit_one_bundle): New locals last_ptr, end_ptr.  Rewrite code that
+	sets unwind_record slot_number and slot_frag fields.
+
+2004-02-02  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* config/tc-mips.c (add_got_offset_hilo): New function.
+	(macro): Use load_register() and add_got_offset_hilo() to load
+	constants instead of hardcoding code sequences throughout.
+
+2004-01-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Add proper indentation.
+
+2004-01-26  Bernardo Innocenti  <bernie@develer.com>
+
+	* config/tc-m68k.h (EXTERN_FORCE_RELOC): Handle m68k-uclinux specially,
+	like m68k-elf.
+	* config/tc-m68k.c (RELAXABLE_SYMBOL): Use EXTERN_FORCE_RELOC instead
+	of hard-coded test for TARGET_OS=elf.
+
+2004-01-24  Chris Demetriou  <cgd@broadcom.com>
+
+	* config/tc-mips.c (hilo_interlocks): Change definition
+	so that MIPS32, MIPS64 and later ISAs are included, along with
+	the already-included machines.  Update comments.
+
+2004-01-23  Daniel Jacobowitz  <drow@mvista.com>
+
+	* config/tc-arm.c (tc_gen_reloc): Improve error message for
+	undefined local labels.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (load_address, macro): Update comments about
+	NewABI GP relaxation.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (macro_build): Remove place and counter arguments.
+	(mips_build_lui, macro_build_ldst_constoffset): Likewise.
+	(mips16_macro_build, macro_build_jalr): Remove counter argument.
+	(set_at, load_register, load_address, move_register): Likewise.
+	(load_got_offset, add_got_offset): Likewise.
+	Update all calls and tidy accordingly.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (RELAX_ENCODE): Remove WARN argument.
+	(RELAX_FIRST, RELAX_SECOND): Turn into 8-bit quantities.
+	(RELAX_USE_SECOND): Bump to 0x10000.
+	(RELAX_SECOND_LONGER, RELAX_NOMACRO, RELAX_DELAY_SLOT): New flags.
+	(mips_macro_warning): New variable.
+	(md_assemble): Wrap macro expansion in macro_start() and macro_end().
+	(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Likewise.
+	(relax_close_frag): Set mips_macro_warning.first_frag.  Adjust use
+	of RELAX_ENCODE.
+	(append_insn): Update mips_macro_warning.sizes.
+	(macro_start, macro_warning, macro_end): New functions.
+	(macro_build): Don't emit warnings here.
+	(macro_build_lui, md_estimate_size_before_relax): ...or here.
+	(md_convert_frag): Check for cases where one macro alternative
+	needs a warning and the other doesn't.  Emit a warning if the
+	longer sequence was chosen.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.h (tc_frag_data_type, TC_FRAG_TYPE): Remove.
+	* config/tc-mips.c (RELAX_ENCODE): Take three arguments: the size of
+	the first sequence, the size of the second sequence, and a flag
+	that says whether we should warn.
+	(RELAX_OLD, RELAX_NEW, RELAX_RELOC[123]): Delete.
+	(RELAX_FIRST, RELAX_SECOND): New.
+	(mips_relax): New variable.
+	(relax_close_frag, relax_start, relax_switch, relax_end): New fns.
+	(append_insn): Remove "place" argument.  Use mips_relax.sequence
+	rather than "place" to check whether we're expanding the second
+	alternative of a relaxable macro.  Remove redundant check for
+	branch relaxation.  If generating a normal insn, and there
+	is not enough room in the current frag, call relax_close_frag()
+	to close it.  Update mips_relax.sizes[].  Emit fixups for the
+	second version of a relaxable macro.  Record the first relaxable
+	fixup in mips_relax.  Remove tc_gen_reloc workaround.
+	(macro_build): Remove all uses of "place".  Use mips_relax.sequence
+	in the same way as in append_insn.
+	(mips16_macro_build): Remove "place" argument.
+	(macro_build_lui): As for macro_build.  Don't drop the add_symbol
+	when generating the second version of a relaxable macro.
+	(load_got_offset, add_got_offset): New functions.
+	(load_address, macro): Use new relaxation machinery.  Remove
+	tc_gen_reloc workarounds.
+	(md_estimate_size_before_relax): Set RELAX_USE_SECOND if the second
+	version of a relaxable macro is needed.  Return -RELAX_SECOND if the
+	first version is needed.
+	(tc_gen_reloc): Remove relaxation handling.
+	(md_convert_frag): Go through the fixups for a relaxable macro and
+	mark those that belong to the unneeded alternative as done.  If the
+	second alternative is needed, adjust the fixup addresses to account
+	for the deleted first alternative.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* frags.h (frag_room): Declare.
+	* frags.c (frag_room): New function.
+	* doc/internals.texi: Document it.
+
+2004-01-22  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (append_insn): Don't do r3900 interlock
+	optimization for -mtune=r3900, as this will break on other CPUs.
+
+2004-01-11  Tom Rix   <tcrix@worldnet.att.net>
+
+	* config/tc-m68hc11.c (build_indexed_byte): movb and movw cannot
+	be relaxed, use fixup.
+	(md_apply_fix3): Use 5 bit reloc from movb and movw fixup.
+
+2004-01-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* config/tc-sparc.c (sparc_ip): Disallow %f32-%f63 for single
+	precision operands.
+
+2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* config/tc-mips.c (append_insn): Properly detect variant frags
+	that preclude swapping of relaxed branches.  Correctly swap
+	instructions between frags when dealing with relaxed branches.
+
+2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* acinclude.m4: Quote names of macros to be defined by AC_DEFUN
+	throughout.
+	* aclocal.m4: Regenerate.
+	* configure: Regenerate.
+
+2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* config/tc-h8300.c (build_bytes): Apply relaxation to bit
+	manipulation insns.
+
+2004-01-12  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (macro_build_jalr): When adding an R_MIPS_JALR
+	reloc, reserve space for the delay slot as well as the jalr itself.
+
+2004-01-09  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_vfp_reg2_from_sp2): Rename from do_vfp_sp_reg2.
+	(do_vfp_sp2_from_reg2): New function.
+	(insns): Use them.
+	(do_vfp_dp_from_reg2): Check return values properly.
+
+2004-01-08  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* config/tc-mips.c (warn_nops): Remove static variable.
+	(macro): Remove test of warn_nops.
+	(md_shortops): Remove 'n'.
+	(md_parse_option): Remove 'n' case.
+	(md_show_usage): Remove -n.
+	* doc/as.texinfo (Overview): Remove MIPS -n option.
+	* doc/c-mips.texi (MIPS Opts): Remove mention -n.
+	* NEWS: Mention removal of MIPS -n option.
+
+	* config/tc-mips.c (ISA_HAS_COPROC_DELAYS): Remove.
+	(cop_interlocks): Check ISA level.
+	(cop_mem_interlocks): Define.
+	(reg_needs_delay): Check cop_interlocks rather than
+	ISA_HAS_COPROC_DELAYS.
+	(append_insn): Likewise.  Use cop_mem_interlocks rather than
+	directly checking mips_opts.isa.
+	(mips_emit_delays): Likewise.
+
+2004-01-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (unwind): Move next_slot_number and
+	next_slot_frag to ...
+	(unw_rec_list): Here.
+	(free_list_records): Removed.
+	(output_unw_records): Likewise.
+	(generate_unwind_image): Make it void.
+	(alloc_record): Initialize next_slot_number and next_slot_frag.
+	(slot_index): Take .org, .space and .align into account.
+	(fixup_unw_records): Don't set slot_number to 0. Use
+	list->next_slot_number and list->next_slot_frag instead of
+	unwind.next_slot_number and unwind.next_slot_frag.
+	(ia64_convert_frag): New.
+	(generate_unwind_image): Generate a rs_machine_dependent frag
+	for unwind record.
+	(emit_one_bundle): Use list->next_slot_number and
+	list->next_slot_frag instead of unwind.next_slot_number and
+	unwind.next_slot_frag.
+
+	* config/tc-ia64.h (md_convert_frag): Defined as
+	ia64_convert_frag.
+	(md_estimate_size_before_relax): Defined as (f)->fr_var.
+
+2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	2003-12-19  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.h (md_apply_fix3): Don't define.
+	* config/tc-frv.c (md_apply_fix3): New.  Shift/truncate %hi/%lo
+	operands.
+	* config/tc-frv.h (TC_FORCE_RELOCATION_SUB_LOCAL): Define.
+	2003-10-07  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.c (line_separator_chars): Add `!'.
+	2003-09-19  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.c (md_assemble): Clear insn upfront.
+	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.c (OPTION_FDPIC): New macro.
+	(md_longopts): Add mfdpic.
+	(md_parse_option): Handle it.
+	2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.c (md_cgen_lookup_reloc) <FRV_OPERAND_D12,
+	FRV_OPERAND_S12>: Use reloc type encoded in fix-up.
+	(frv_pic_ptr): Parse funcdesc.
+
+2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* doc/as.texinfo: Let texi2pod parse asconfig.texi and
+	gasver.texi.  Remove duplicate symbol definitions for texi2pod.
+
+2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* Makefile.am (Makefile): Move the dependency on
+	$(BFDDIR)/configure.in to...
+	(CONFIG_STATUS_DEPENDENCIES): ... here.
+	(AUTOMAKE_OPTIONS): Require automake 1.8.
+	* Makefile.in: Regenerate.
+	* doc/Makefile.am (BASEDIR, BFDDIR): Define.
+	(CONFIG_STATUS_DEPENDENCIES): Add a dependency on
+	$(BFDDIR)/configure.in here as well.
+	* doc/Makefile.in: Regenerate.
+
+2004-01-05  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* Makefile.am (install, install-info, RECURSIVE_TARGETS): Remove.
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* doc/Makefile.am (install, install-info): Remove.
+	(install-data-local): A new hook for install-info.
+	(AUTOMAKE_OPTIONS): Require automake 1.8.
+	* doc/Makefile.in: Regenerate.
+
+2004-01-02  Nutan Singh <nutan@kpitcummins.com>
+
+	* doc/c-sh.texi: Update description about floating point behavior
+	of SH family.
+
+2004-01-02  Bernardo Innocenti  <bernie@develer.com>
+
+	* configure.in: Add m68k-uClinux target.
+	* configure: Regenerate.
+
+For older changes see ChangeLog-0203
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/ChangeLog-2005 b/gas/ChangeLog-2005
new file mode 100644
index 000000000000..42ae089d4727
--- /dev/null
+++ b/gas/ChangeLog-2005
@@ -0,0 +1,4292 @@
+2005-12-30  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (op_placement_info_struct): Delete single,
+	single_size, widest, and widest_size fields.  Add narrowest_slot.
+	(xg_emit_insn_to_buf): Remove fmt parameter and compute it here.
+	Use xg_get_single_slot to find the slot.
+	(finish_vinsn): Use emit_single_op instead of bundle_single_op.
+	(bundle_single_op): Rename this to....
+	(bundle_tinsn): ...this function, which builds a vliw_insn but does
+	not call finish_vinsn.
+	(emit_single_op): Use bundle_tinsn instead of bundle_single_op.
+	(relax_frag_immed): Get num_slots from cur_vinsn.
+	(convert_frag_narrow): Update call to xg_emit_insn_to_buf.
+	(convert_frag_immed): Likewise.  Also, get num_slots from cur_vinsn.
+	(init_op_placement_info_table): Set narrowest_slot field.  Remove
+	code for deleted fields.
+	(xg_get_single_size): Return narrowest_size field, not single_size.
+	(xg_get_single_format): Return narrowest field, not single.
+	(xg_get_single_slot): New.
+	(tinsn_to_insnbuf): Rewrite to use tinsn_to_slotbuf.
+	* config/xtensa-relax.c (widen_spec_list): Add wide branch relaxations.
+	(transition_applies): Check wide branch option availability.
+
+2005-12-29  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define.
+
+2005-12-29  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (tinsn_to_slotbuf): Do not zero slotbuf.
+
+2005-12-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* config/tc-mt.c (mt_arch): Default to ms1_16_002.
+	(md_parse_options): Only allow lowercase.
+	(md_show_usage): Update.
+
+2005-12-27  Leif Ekblad  <leif@rdos.net>
+
+	* configure.tgt: Add support for RDOS targets.
+
+2005-12-27  James Troup  <james@nocrew.org>
+
+	PR 1300
+	* config/tc-arm.c (md_apply_fix): Fix casts to match type in
+	printf format.
+
+2005-12-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2005-12-22  Jan Beulich  <jbeulich@novell.com>
+
+	* symbols.h (snapshot_symbol): First parameter is now pointer
+	to pointer to symbolS.
+	* symbols.c (snapshot_symbol): Likewise. Store resulting symbol
+	there. Use symbol_equated_p.
+	* expr.c (resolve_expression): Change first argument to
+	snapshot_symbol. Track possibly changed add_symbol consistently
+	across function. Resolve more special cases with known result.
+	Also update final_val when replacing add_symbol.
+
+2005-12-13  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* config/tc-vax.c: Convert to ISO C90 format.  Fix formatting and
+	white space usage as well.
+
+2005-12-20  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xtensa_mark_narrow_branches): Set
+	is_aligning_branch flag.
+	(find_address_of_next_align_frag): Limit by xtensa_fetch_width.
+	(future_alignment_required): Except for frags with is_aligning_branch
+	flag set, call frag_wane for frags that do not need to be reexamined
+	for aligning.
+	(relax_frag_immed): Replace orig_vinsn with cur_vinsn to fix a leak.
+	(convert_frag_immed): Likewise.
+	(convert_frag_narrow): Check is_aligning_branch flag.
+	* config/tc-xtensa.h (xtensa_frag_type): Add is_aligning_branch flag.
+
+2005-12-20  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (xg_find_narrowest_format): Optimize 1 slot case.
+	(xg_init_vinsn): Remove redundant initialization.
+	(xg_clear_vinsn): Zero all the slots with a single memset.
+	* config/xtensa-istack.h (vliw_insn): Move insnbuf field after slots.
+
+2005-12-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* doc/t-mt.texi: Update MS1 to MT.
+
+2005-12-16  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Second part of ms1 to mt renaming.
+	* configure: Rebuilt.
+	* configure.in (mt): Remove special case.
+	* config/tc-mt.c (opcodes/mt-desc.h, opcodes/mt-opc.h): Change
+	#includes.
+	(mt_insn, mt_mach, mt_mach_bitmask, mt_flags, mt_architectures):
+	Rename, adjust.
+	(md_parse_option, md_show_usage, md_begin, md_assemble,
+	md_cgen_lookup_reloc, md_atof): Adjust.
+	(mt_force_relocation, mt_apply_fix, mt_fix_adjustable): Rename, adjust.
+	* config/tc-mt.h (TC_MT): Rename.
+	(LISTING_HEADER, TARGET_ARCH, TARGET_FORMAT): Adjust.
+	(md_apply_fix): Adjust.
+	(mt_apply_fix, mt_fix_adjustable, mt_force_relocation): Rename.
+	(TC_FORCE_RELOCATION, tc_fix_adjustable): Adjust.
+
+2005-12-14  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (add_prefix): More fine-grained handling of
+	REX prefixes. Or new prefix value into i.prefix instead of
+	assigning.
+
+2005-12-13  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (m32c_md_end): Only pad code sections.
+
+2005-12-12  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_branch): Generate EABI branch relocations.
+	(do_bl): New function.
+	(do_blx): Generate BFD_RELOC_ARM_PCREL_CALL relocation.
+	(do_t_blx): Generate BFD_RELOC_THUMB_PCREL_BRANCH23.
+	(insns): Use do_bl.
+	(md_pcrel_from_section): Add BFD_RELOC_ARM_PCREL_CALL and
+	BFD_RELOC_ARM_PCREL_JUMP.
+	(md_apply_fix): Merge BFD_RELOC_ARM_PCREL_BRANCH and
+	BFD_RELOC_ARM_PCREL_BLX cases.  Handle BFD_RELOC_ARM_PCREL_CALL and
+	BFD_RELOC_ARM_PCREL_JUMP.
+	(tc_gen_reloc): Handle BFD_RELOC_ARM_PCREL_CALL and
+	BFD_RELOC_ARM_PCREL_JUMP.
+	gas/testsuite/
+	* gas/arm/pic.d: Allow R_ARM_CALL relocations.
+
+2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* configure.in: Replace ms1 arch with mt arch.
+	* configure: Rebuilt.
+	* configure.tgt: Replace ms1 arch with mt arch.
+	* config/tc-mt.c: Renamed from tc-ms1.c: Update include files.
+	* doc/Makefile.am (CPU_DOCS): Replace ms1 files with mt files.
+	* doc/Makefile.in: Rebuilt.
+
+2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	Change 32-bit-branch expansion for --pic.
+	* config/tc-cris.c (STATE_COND_BRANCH_PIC): New relaxation state.
+	(md_cris_relax_table): Add entry for STATE_COND_BRANCH_PIC.
+	(cris_any_v0_v10_long_jump_size_pic): New macro.
+	(md_estimate_size_before_relax): Handle STATE_COND_BRANCH_PIC.
+	(md_convert_frag): Similar.
+	(md_create_long_jump): Change 32-bit-branch expansion for --pic.
+	(md_assemble, gen_cond_branch_32): Adjust similarly.
+	(md_parse_option) <case OPTION_PIC>: Adjust md_long_jump_size.
+	<case OPTION_ARCH>: Similar, if --pic.
+
+2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/1874
+	* config/tc-i386.c (match_template): Handle monitor.
+	(process_suffix): Likewise.
+
+2005-12-05  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	Bug gas/1948
+	* symbols.c (colon): Also check if now_seg is bss_section when a symbol
+	is being redefined.
+
+2005-12-02  Arnold Metselaar  <arnoldm@sourceware.org>
+
+	* config/tc-z80.c (emit_ldreg): fix bug in ld rr,<xx>
+
+2005-11-26  Arnold Metselaar  <arnoldm@sourceware.org>
+
+	* config/tc-z80.c (z80_start_line_hook): issue an error when
+	redefining a symbol with equ
+	* doc/as.texinfo(equ<z80>): mention difference with .equiv 
+	* doc/as.texinfo(err): fix typo 
+	* doc/c-z80.texi(equ): redefining a symbol with equ is no longer 
+	allowed
+
+2005-11-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	Bug gas/1896
+	* config/tc-hppa.c (hppa_fix_adjustable): Don't reject for reduction
+	R_HPPA relocations that are 32-bits wide.
+
+2005-11-23  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Thiemo Seufer <ths@networkno.de>
+
+	* config/tc-mips.c (append_insn): Handle BFD_RELOC_16_PCREL_S2.
+	(macro_build): Complain for invalid branch displacements.
+	(mips_validate_fix): Delete.
+	(md_apply_fix): Re-add pcrel support for branches.  Use consistent
+	text for misaligned branch targets.
+	(tc_gen_reloc: Re-add pcrel support for branches.  Handle strange
+	BFD pcrel processing.  Remove error for unresolved branches.
+	* config/tc-mips.h (TC_VALIDATE_FIX, mips_validate_fix): Delete.
+
+2005-11-22  James E Wilson  <wilson@specifix.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Perform last_slot < 0 check
+	even when manual_bundling isn't set.
+
+	* config/tc-ia64.c (slot_index): Emit an error instead of a warning
+	when the frag chain is broken by section switching.
+
+2005-11-18  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/bfin-defs.h (IS_BREG, IS_LREG): New macros.
+	* config/bfin-parse.y (asm_1): Check register type for load immediate
+	instruction.
+
+2005-11-17  Alexandre Oliva  <aoliva@redhat.com>
+
+	* config/tc-ppc.c (ppc_frob_file_before_adjust): Do not reference
+	dotname.
+	* write.c (write_object_file): Do not remove used weakrefd.
+
+2005-11-17  Jan Beulich  <jbeulich@novell.com>
+
+	* dw2gencfi.c (dot_cfi): Put argument parsing for cases
+	DW_CFA_restore and DW_CFA_undefined in a loop.
+
+2005-11-17  Jan Beulich  <jbeulich@novell.com>
+
+
+	* symbols.h (S_CLEAR_VOLATILE): Declare.
+	* symbols.c (colon): Also accept redefinable symbols for
+	redefinition. Clone them before modifying.
+	(S_CLEAR_VOLATILE): Define.
+	* cond.c (s_ifdef): Also test for equated symbols.
+	* read.c (s_comm_internal): Also exclude non-redefinable
+	equated symbols. Clone redefinable ones before modifying.
+	(s_weakref): Clone redefinable symbols before modifying.
+	* doc/internals.texi: Document sy_volatile, sy_forward_ref,
+	S_IS_VOLATILE, S_SET_VOLATILE, S_CLEAR_VOLATILE,
+	S_IS_FORWARD_REF, and S_SET_FORWARD_REF.
+
+2005-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-hppa.c (pa_comm): Set bfd_com_section segment.
+
+2005-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.tgt (i386-*-gnu*): Set em=gnu.
+	* config/te-gnu.h: New file.
+	* config/tc-i386.c: Don't use '/' as comment char for TE_GNU.
+
+2005-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_pe_comm): Set bfd_com_section segment.
+	* config/tc-alpha.c (s_alpha_comm): Likewise.  Also, remove
+	redundant check.
+	* read.c (s_lsym): Remove non-BFD assembler sym handling.
+
+2005-11-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (s_comm_internal): Set bfd_com_section segment.
+	(s_mri_common): Likewise.
+	* write.c (write_object_file): Remove non-BFD assembler common
+	sym handling.
+
+2005-11-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.c (s_arm_unwind_save_core): Don't emit an extra
+	opcode if r4-r15 are not saved.
+
+2005-11-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (S_GET_VALUE): Remove non-BFD assembler recursion guard.
+
+2005-11-14  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (AR_FCR, AR_EFLAG, AR_CSD, AR_SSD, AR_CFLG,
+	AR_FSR, AR_FIR, AR_FDR, AR_CCV, AR_EC): Define.
+	(ar): Use AR_* instead of literals.
+	(CR_DCR, CR_ITM, CR_IVA, CR_PTA, CR_GPTA, CR_LID, CR_ITV,
+	CR_PMV, CR_CMCV): Define.
+	(cr): Use CR_* instead of literals.
+
+2005-11-14  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (md): Rename regsym to indregsym and move
+	it to the end of the structure.
+	(ar): Field regnum is unsigned.
+	(cr): Likewise:
+	(indirect_reg): Likewise.
+	(declare_register_set): Parameter regnum is unsigned.
+	(declare_register): Parameter numregs and base_regnum are
+	unsigned. So is the local loop variable.
+	(md_begin): Restrict scope of local variable regnum, which
+	also is unsigned. Replace loops with function calls where
+	possible. Re-order things so that register groups are kept
+	together. Remove all uses of regsym except for indirect
+	registers. Replace use of regsym by indregsym for indirect
+	registers.
+	(ia64_optimize_expr): Replace use of regsym by indregsym for
+	indirect registers, with appropriate bias.
+
+2005-11-14  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (mips16_ip): Add handling of 'm' and 'M' codes
+	for the MIPS16e save/restore instructions.
+
+2005-11-11  Jan Beulich  <jbeulich@novell.com>
+
+	* doc/Makefile.am: Make asconfig.texi writeable before trying
+	to write to it.
+	* doc/Makefile.in: Refresh.
+
+2005-11-10  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (intel_e11): Don't special-case segment
+	registers in brackets.
+
+2005-11-10  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (BAD_ADDR_MODE): Define.
+	(arm_reg_parse_multi): Return NULL rather than FAIL.
+	(arm_reg_parse): Fix comment, the function returns FAIL rather
+	than NULL if it is unable to parse the register name.
+	(do_ldrex): Use BAD_ADDR_MODE.
+	Change error message for PC-relative addressing.
+	(do_strex): Likewise.
+	(do_t_ldrex): Use BAD_ADDR_MODE.
+	(do_t_strex): Likewise.
+
+2005-11-08   Jean-Jacques Metayer  <jean-jacques.metayer@thomson.net>
+
+	* config/tc-sparc.c (isoctal): Fix thinko.
+
+2005-11-08  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* expr.c (operand <case '$'>): Use DOLLAR_AMBIGU rather than
+	flag_mri_m68k as condition for parsing the '$' as a prefix.
+	* as.h (DOLLAR_AMBIGU): Define if needed.
+
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2 support.
+	* config/tc-ms1.c (ms1_mach_bitmask): Initialize to MS1.
+	(ms1_architectures): Add ms2.
+	(md_parse_option): Add ms2.
+	(md_show_usage): Add ms2.
+	(md_assemble): Add JAL_HAZARD detection logic.
+	(md_cgen_lookup_reloc): Add MS1_OPERAND_LOOPSIZE case.
+	* doc/c-ms1.texi: New.
+	* doc/all.texi: Add MS1.
+	* doc/Makefile.am (CPU_DOCS): Add c-ms1.texi.
+	* doc/Makefile.in: Rebuilt.
+	* doc/Makefile: Rebuilt.
+
+2005-11-07  Steve Ellcey  <sje@cup.hp.com>
+
+	* configure: Regenerate after modifying bfd/warning.m4.
+
+2005-11-07  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	PR gas/1804
+	* config/tc-hppa.c (md_apply_fix): Use number_to_chars_bigendian to
+	output constant data.
+
+2005-11-07  Mark Mitchell  <mark@codesourcery.com>
+
+	* doc/Makefile.am (asconfig.texi): Set top_srcdir.
+	* doc/Makefile.in: Regenerated.
+	* doc/as.texinfo: Document "@FILE".
+
+2005-11-07  Nick Clifton  <nickc@redhat.com>
+
+	PR binutils/1568
+	* config/obj-coff.c (obj_coff_section): Set readonly flag with the
+	'x' attribute.  Remember the actions of the 'w' and 'n' attributes
+	and do not allow the 'x','s' or 'd' attributes to change them.
+
+2005-11-07  John Levon  <levon@movementarian.org>
+
+	* config/tc-i386.h (tc_comment_chars): Define.
+	* config/tc-i386.c (line_comment_chars): Use '/' unconditionally.
+	(i386_comment_chars): Add.
+	(md_parse_options): Process OPTION_DIVIDE.
+	(md_show_usage): Describe --divide option.
+	* doc/c-i386.texi: Document --divide option.
+
+2005-11-07  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* expr.c (op_encoding): Map '=' to O_SINGLE_EQ, if defined.
+	* config/tc-z80.h: Define O_SINGLE_EQ as O_eq.
+
+2005-11-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* macro.c (buffer_and_nest): Skip labels regardless of
+	NO_PSEUDO_DOT and flag_m68k_mri.
+
+2005-11-07  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* expr.c (integer_constant): Match only 'B' as binary suffix if
+	NUMBERS_WITH_SUFFIX and LOCAL_LABELS_FB.  Allow both 'b' and 'B'
+	otherwise.
+
+2005-11-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* read.c (s_weakref): Do not permit redefinitions.
+	* symbols.c (colon): Do not permit redefinitions of equated
+	symbols.
+
+2005-11-01  Thiemo Seufer  <ths@networkno.de>
+
+	PR gas/1299
+	* Makefile.am: Disable -Werror for the itbl-lex.o rule.
+	* Makefile.in: Regenerate.
+
+2005-11-01  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c (md_parse_option): Fix typo in comment.
+
+2005-10-30  Mark Mitchell  <mark@codesourcery.com>
+
+	* as.c (show_usage): Document "@FILE".
+
+2005-10-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am (OBJ_FORMATS): Remove vms.
+	Run "make dep-am".
+	* Makefile.in: Regenerated.
+
+	* dep-in.sed: Replace " ./" with " ".
+
+2005-10-28  Dave Brolley  <brolley@redhat.com>
+
+	Contribute the following change:
+	2005-09-19  Dave Brolley  <brolley@redhat.com>
+
+	* config/tc-m32c.c (default_isa): New static variable.
+	(m32c_isa): Now of type CGEN_BITSET.
+	(md_begin): Pass &m32c_isa to m32c_cgen_cpu_open.
+
+2005-10-28  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (aeabi_set_public_attributes): Use selected_cpu
+	instead of mcpu_cpu_opt.
+
+2005-10-27  Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (find_vinsn_conflicts): Change error messages to
+	refer to "ports" instead of "queues".
+	(check_t1_t2_reads_and_writes): Pass correct interface values to
+	xtensa_interface_inout.
+
+2005-10-27  Jan Beulich  <jbeulich@novell.com>
+
+	* read.c (assign_symbol): Also consider equates already defined.
+	* symbols.c (symbol_clone): Also clone the underlying BFD symbol.
+	* config/obj-coff.h (obj_symbol_clone_hook): New.
+	(coff_obj_symbol_clone_hook): Declare.
+	* config/obj-coff.c (coff_obj_symbol_clone_hook): New.
+
+2005-10-26  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_relax_table, subtype_mappings,
+	md_convert_frag): Add jsr.w support.
+
+	* config/tc-m32c.c (md_assemble): Don't use errmsg as the format
+	itself.
+	(md_cgen_lookup_reloc): Add m32c bitbase operands.  Add 8-s24
+	and imm-8-HI operands.
+
+2005-10-26  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (insns): Correct "sel" entry.
+
+2005-10-26  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (i386_operand): Don't check register prefix here.
+	(parse_real_register): Rename from parse_register.
+	(parse_register): New.
+	(i386_parse_name): New.
+	(md_operand): New.
+	(intel_e11): Don't tolerate registers in offset expressions anymore.
+	(intel_get_token): Don't check register prefix here. Copy the actual
+	register token, not the canonical register name.
+	* config/tc-i386.h (md_operand): Delete.
+	(i386_parse_name): Declare.
+	(md_parse_name): Define.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* Makefile.am: Add Z80 cpu.
+	* Makefile.in: Regenerated.
+	* app.c (do_scrub_chars)<TC_Z80>: Correctly scrub "ex af,af'"
+	and disallow newlines in quoted strings.
+	* configure.tgt: Add z80-*-coff.
+	* config/obj-coff.h: Add format "coff-z80".
+	* doc/Makefile.am: Add c-z80.texi.
+	* doc/Makefile.in: Regenerated.
+	* doc/all.texi: Add Z80.
+	* doc/c-z80.texi: New file
+	* doc/as.texinfo: Add z80 options and some z80-related remarks.
+	* config/tc-z80.c: New file
+	* config/tc-z80.h: New file
+	* NEWS: Mention new support.
+
+2005-10-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* write.c (adjust_reloc_syms): Undo the change made on
+	2005-04-26 to allow local symbol set to undefined symbol.
+
+2005-10-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am (bfin-parse.tab.h): Removed.
+	(bfin-parse.h): Added.
+	* Makefile.in: Regenerated.
+
+2005-10-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/POTFILES.in: Regenerate.
+	* po/gas.pot: Regenerate.
+
+2005-10-24  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* config/tc-bfin.c (Expr_Node_Gen_Reloc): If have symbol + constant,
+	make a single reloc with an offset rather than a stack.
+	* config/tc-bfin.h (MD_APPLY_SYM_VALUE): Define to 0.
+
+2005-10-24  Alexandre Oliva  <aoliva@redhat.com>
+
+	* read.c (potable): Add weakref.
+	(s_weakref): New.
+	* read.h (s_weakref): Declare.
+	* struc-symbol.h (struct symbol): Add sy_weakrefr and sy_weakrefd.
+	* symbols.c (colon): Clear weakrefr.
+	(symbol_find_exact): Rename to, and reimplement in terms of...
+	(symbol_find_exact_noref): ... new function.
+	(symbol_find): Likewise...
+	(symbol_find_noref): ... ditto.
+	(resolve_symbol_value): Resolve weakrefr without setting their
+	values.
+	(S_SET_WEAK): Call hook.
+	(S_GET_VALUE): Follow weakref link.
+	(S_SET_VALUE): Clear weakrefr.
+	(S_IS_WEAK): Follow weakref link.
+	(S_IS_WEAKREFR, S_SET_WEAKREFR, S_CLEAR_WEAKREFR): New.
+	(S_IS_WEAKREFD, S_SET_WEAKREFD, S_CLEAR_WEAKREFD): New.
+	(symbol_set_value_expression, symbol_set_frag): Clear weakrefr.
+	(symbol_mark_used): Follow weakref link.
+	(print_symbol_value_1): Print weak, weakrefr and weakrefd.
+	* symbols.h (symbol_find_noref, symbol_find_exact_noref): Declare.
+	(S_IS_WEAKREFR, S_SET_WEAKREFR, S_CLEAR_WEAKREFR): Declare.
+	(S_IS_WEAKREFD, S_SET_WEAKREFD, S_CLEAR_WEAKREFD): Declare.
+	* write.c (adust_reloc_syms): Follow weakref link.  Do not
+	complain if target is undefined.
+	(write_object_file): Likewise.  Remove weakrefr symbols.  Drop
+	unreferenced weakrefd symbols.
+	* config/obj-coff.c (obj_frob_symbol): Do not force WEAKREFD
+	symbols EXTERNAL.
+	(pecoff_obj_set_weak_hook, pecoff_obj_clear_weak_hook): New.
+	* config/obj-coff.h (obj_set_weak_hook, obj_clear_weak_hook): Define.
+	* doc/as.texinfo: Document weakref.
+	* doc/internals.texi: Document new struct members, internal
+	functions and hooks.
+
+2005-10-24  Jie Zhang  <jie.zhang@analog.com>
+
+	* Makefile.am (bfin-parse.h): Renamed from bfin-parse.tab.h.
+	(EXTRA_DIST): Add bfin-parse.h and bfin-lex.c.
+	* Makefile.in: Regenerate.
+	* config/bfin-lex.l: Include bfin-parse.h instead of bfin-parse.tab.h.
+	* config/tc-bfin.c (md_chars_to_number): Change the type of first
+	argument from unsigned char * to char * to remove signedness warnings.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (enum reg_symbol): Delete IND_MEM.
+	(dot_rot): Change type of num_* variables. Check for positive count.
+	(ia64_optimize_expr): Re-structure.
+	(md_operand): Check for general register.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (declare_register): Call symbol_create.
+	(md_begin): Remove local variables total, ar_base, and cr_base.
+	Start loops for registers at their respective first one. Don't
+	update md.regsym for alias names. Generate alias name tp for r13.
+
+2005-10-21  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_cgen_lookup_reloc): Add more relocs.  Print
+	names unstead of numbers.
+
+2005-10-19  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (append_insn): Convert MIPS16 jr/jalr jumps
+	into jrc/jalrc versions if ISA_MIPS32+ and not doing the swap,
+	hence avoiding to emit a nop.
+
+2005-10-19  Jie Zhang  <jie.zhang@analog.com>
+
+	* config/tc-bfin.c (md_begin): Let the lex_type of '(' be
+	LEX_BEGIN_NAME.
+	(bfin_start_line_hook): Remove the workaround for LSETUP(.
+	(bfin_name_is_register): Remove the workarounds for LSETUP(
+	and SAA(.
+	(bfin_start_label): Ditto.
+
+2005-10-18  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_end_directive): Restore
+	default_lit_sections regardless of use_literal_section.
+
+2005-10-18  Jie Zhang  <jie.zhang@analog.com>
+
+	* Makefile.am (bfin-lex.c): Update ylwrap invocation.
+	* Makefile.in: Regenerated.
+
+2005-10-18  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* doc/as.texinfo (.loc) Fix placement of '@end table'.
+
+2005-10-17  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/xtensa-istack.h (TInsn): Replace dwarf2_line_info with an
+	unsigned line number.  Do not include "dwarf2dbg.h".
+	* config/tc-xtensa.c (md_pseudo_table): Remove entry for "loc".
+	(xtensa_dwarf2_directive_loc, xtensa_dwarf2_emit_insn): Delete.
+	(xg_build_to_insn, xg_build_token_insn): Update TInsn uses.
+	(md_assemble): Use as_where instead of dwarf2_where.
+	(xg_assemble_vliw_tokens): Use unsigned line numbers instead of
+	dwarf2_line_infos.  Change to call new_logical_line followed by
+	dwarf2_emit_insn.
+
+2005-10-14  Mike Frysinger <vapier@gentoo.org>
+
+	* doc/as.texinfo (Section): Add missing ']' to .section example.
+
+2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	PR binutils/941
+	* config/tc-hppa.c (pa_ip): Use as_bad instead of as_fatal when an
+	unknown opcode is found.
+
+2005-10-12  Mark Mitchell  <mark@codesourcery.com>
+
+	* NEWS: Mention @file.
+
+2005-10-12  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-avr.c: Convert to ISO C90 format.  Fix formatting and
+	generally tidy up the code.
+	* config/tc-avr.h: Likewise.
+
+2005-10-12  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_reg_val): Use expression_and_evaluate.
+	(dot_pred_rel): Likewise.
+	(parse_operand): Likewise.
+	(ia64_unrecognized_line): Likewise.
+	(md_operand): Likewise.
+
+2005-10-11  Jan Beulich  <jbeulich@novell.com>
+
+	* expr.h (enum expr_mode): New.
+	(expression): Pass third argument to expr.
+	(expression_and_evaluate): New.
+	(deferred_expression): New.
+	(expr): Add third parameter.
+	(resolve_expression): New.
+	* struc-symbol.h (struct symbol): New members sy_volatile and
+	sy_forward_ref.
+	* symbols.c, symbols.h (symbol_clone): New.
+	(symbol_clone_if_forward_ref): New.
+	(snapshot_symbol): New.
+	(S_IS_VOLATILE): New.
+	(S_IS_FORWARD_REF): New.
+	(S_SET_VOLATILE): New.
+	(S_SET_FORWARD_REF): New.
+	* as.c (macro_expr): Use expression_and_evaluate.
+	* cond.c (s_if): Likewise.
+	(s_elseif): Likewise.
+	* dw2gencfi.c (cfi_parse_reg): Likewise.
+	* expr.c (operand): Add second parameter. Optionally call
+	deferred_expression. Pass mode argument to itself and md_parse_name.
+	Check mode before trying to evaluate symbol. Call
+	symbol_clone_if_forward_ref for both operands.
+	(expr): Add third parameter. Pass mode to operand and itself.
+	Optionally call resolve_expression.
+	(resolve_expression): New.
+	(get_single_number): Pass second argument to operand.
+	* read.c (potable): New entry for .eqv.
+	(read_a_source_file): Handle new == operator.
+	(get_absolute_expr): Use expression_and_evaluate.
+	(s_lsym): Likewise.
+	(assign_symbol): Rename second parameter. Call symbol_clone on
+	legal and illegal redefinition. Call S_SET_VOLATILE and
+	S_SET_FORWARD_REF depending on mode.
+	(s_set): Update description.
+	(s_space): Call resolve_expression.
+	(pseudo_set): Optionally call deferred_expression. Check
+	S_IS_FORWARD_REF before trying to simplify/resolve an expression.
+	(equals): Handle ==.
+	* config/tc-ia64.h (md_parse_name): Add mode parameter.
+	* config/tc-arc.c (arc_parse_cons_expression): Likewise.
+	* config/tc-m32r.h (md_parse_name): Likewise.
+	(m32r_parse_name): Likewise.
+	* config/tc-mmix.h (md_parse_name): Likewise.
+	* config/tc-mn10300.h (md_parse_name): Likewise.
+	(mn10300_parse_name): Likewise.
+	* config/tc-ppc.h (md_parse_name): Likewise.
+	* config/tc-sh.h (md_parse_name): Likewise.
+	(sh_parse_name): Likewise.
+	* config/tc-sh64.h (md_parse_name): Likewise.
+	(sh64_consume_datalabel): Likewise.
+	* config/tc-tic54x.h (md_parse_name): Likewise.
+	* config/tc-m32r.c (m32r_parse_name): Add mode parameter. Check it
+	before trying to evaluate symbol.
+	* config/tc-mn10300.c (mn10300_parse_name): Likewise.
+	* config/tc-sh.c (sh_parse_name): Likewise.
+	* config/tc-sh64.c (sh64_consume_datalabel): Add mode parameter. Pass
+	second argument to operandf. Pass mode parameter to sh_parse_name.
+	* doc/as.texinfo: Document .eqv and the == assignment operator.
+
+2005-10-10  Ian Lance Taylor  <ian@airs.com>
+
+	* Makefile.am (EXTRA_DIST): Remove bfin-lex.l and bfin-defs.h.
+	* Makefile.in: Regenerate.
+
+2005-10-10  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* expr.c (operator): Allow "!=" as a synonym for "<>".
+	* doc/as.texinfo (Infix Op): Mention "!=".
+
+2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/tc-hppa.c (strict): Don't initialize.  Update comment.
+	(pa_ip): Promote from PA 1.0 to 1.1 immediately when 1.1 match is
+	found.  Simplify handling of "ma" and "mb" completers.
+
+2005-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c: Don't provide fallback default for CPU_DEFAULT.
+	(arm_arch_used, thumb_arch_used, selected_cpu, selected_cpu_name):
+	New variables.
+	(arm_cpu_option_table): Add canonical_name.
+	(arm_cpus): Populate canonical_name field.
+	(s_arm_eabi_attribute, s_arm_arch, s_arm_cpu, s_arm_fpu,
+	aeabi_set_public_attributes, arm_md_end): New functions.
+	(md_pseudo_table): Add "cpu", "arch", "fpu" and "eabi_attribute".
+	(md_assemble): Set thumb_arch_used and arm_arch_used.
+	(md_begin): Set defaut cpu if CPU_DEFAULT not defined.
+	* config/tc-arm.h (md_end): Define.
+	* doc/c-arm.texi: Document .cpu, .arch, .fpu and .eabi_attribute.
+
+2005-10-06  Khem Raj  <kraj@mvista.com>
+	    NIIBE Yutaka  <gniibe@m17n.org>
+
+	* config/tc-sh.c (allow_dollar_register_prefix): New variable.
+	(parse_reg_without_prefix): New function.
+	(parse_reg): Check for '$' register prefix if --allow-reg-prefix is
+	set.
+	(option md_longopts): Add allow-reg-prefix option.
+	* doc/c-sh.texi: Document --allow-reg-prefix option.
+	* NEWS: Mention the new switch.
+
+2005-10-03  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* doc/as.texinfo (Infix Ops):  '<' and '>' are not shift
+	operators.
+
+2005-09-30  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_frob_label): Disallow labels in bundles.
+
+2005-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerated.
+	* aclocal.m4: Likewise.
+
+2005-09-30  Mark Mitchell  <mark@codesourcery.com>
+
+	* as.c (main): Use expandargv.
+
+2005-09-30  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-tic4x.c (tic4x_set): Advance input_line_pointer past
+	(removed) comma.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* Makefile.am: Bfin support.
+	* Makefile.in: Regenerated.
+	* aclocal.m4: Regenerated.
+	* configure: Regenerated.
+	* configure.in: Bfin support.
+	* configure.tgt: Bfin support.
+	* config/bfin-aux.h: New file.
+	* config/bfin-defs.h: New file.
+	* config/bfin-lex.l: New file.
+	* config/bfin-parse.y: New file.
+	* config/tc-bfin.c: New file.
+	* config/tc-bfin.h: New file.
+	* doc/Makefile.am: Recognize c-bfin.texi.
+	* doc/Makefile.in: Regenerated.
+	* doc/all.texi: Bfin support.
+	* doc/as.texinfo: Likewise.
+	* doc/c-bfin.texi: Document bfin-specific syntax and
+	directives.
+
+2005-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (opcode_tag): Add OT_cinfix3_legacy.
+	(opcode_lookup): Handle OT_cinfix3_legacy.  Revert earlier change for
+	normal infix conditions.
+	(C3E): Include Thumb-2 definition.
+	(CL, cCL): Define.
+	(insns): Use them for legacy mnemonics.
+
+2005-09-30  Matthias Kurz  <mk@baerlap.north.de>
+
+	* asintl.h: Prevent the inclusion of <libintl.h> from the Solaris
+	version of <locale.h> when ENABLE_NLS is not defined.
+
+2005-09-29  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_operands): Always parse first operand of
+	alloc.
+
+2005-09-29  Arnold Metselaar <arnold.metselaar@planet.nl>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* app.c (do_scrub_chars): Match open and close quote of strings.
+	Remove redundant EOF test in case 7.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (reloc): Disable signedness check for 4-byte
+	relocations in 16- and 32-bit modes.
+	(i386_displacement): Make pc-relative branch handling dependent
+	upon operand (rather than address) size.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* dw2gencfi.c (dot_cfi): Call ignore_rest_of_line when not fully
+	parsing the input.
+	(dot_cfi_startproc): Likewise.
+	(dot_cfi_endproc): Likewise. Also check no extra input was given.
+	(dot_cfi_escape): Likewise.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.h (x86_cons_fix_new): Declare unconditionally.
+	(TC_CONS_FIX_NEW): Define unconditionally.
+	(x86_pe_cons_fix_new): Remove.
+	* config/tc-i386.c (signed_cons): New.
+	(md_pseudo_table): Add slong.
+	(x86_cons_fix_new): Declare unconditionally.
+	(x86_pe_cons_fix_new): Merge into x86_cons_fix_new.
+	(tc_gen_reloc): Also consider BFD_RELOC_X86_64_32S for gotpc
+	conversion.
+
+2005-09-28  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* app.c (do_scrub_chars <LEX_IS_SYMBOL_COMPONENT>): Check for full
+	buffer after copying string.
+
+2005-09-27  Paul Brook  <paul@codesourcery.com>
+
+	* config/arm.c (arm_cpus): Add more cpu names.
+	* doc/c-arm.texi: Document them.
+
+2005-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (pseudo_set): Don't set undefined symbols to expr_section.
+
+2005-09-20  Richard Henderson  <rth@redhat.com>
+
+	* dwarf2dbg.c (process_entries): Fix uninitialized variable warning.
+
+2005-09-20  Richard Henderson  <rth@redhat.com>
+
+	* dwarf2dbg.c (struct line_entry): Replace frag and frag_ofs
+	with label.
+	(dwarf2_loc_mark_labels): New.
+	(dwarf2_gen_line_info_1): Split out of ...
+	(dwarf2_gen_line_info): ... here.  Create the temp symbol here.
+	(dwarf2_emit_label): New.
+	(dwarf2_directive_loc_mark_labels): New.
+	(out_set_addr): Take a symbol instead of frag+ofs.
+	(relax_inc_line_addr): Likewise.
+	(emit_inc_line_addr): Assert delta non-negative.
+	(process_entries): Remove dead code.  Update to work with temp
+	symbols instead of frag+ofs.
+	* dwarf2dbg.h (dwarf2_directive_loc_mark_labels): Declare.
+	(dwarf2_emit_label, dwarf2_loc_mark_labels): Declare.
+	* config/obj-elf.c (elf_pseudo_tab): Add loc_mark_labels.
+	* config/obj-elf.h (obj_frob_label): New.
+	* config/tc-alpha.c (alpha_define_label): Call dwarf2_emit_label.
+	* config/tc-arm.c, config/tc-hppa.c, config/tc-m68k.c,
+	config/tc-mips.c, config/tc-ppc.c, config/tc-sh.c, config/tc-xtensa.c:
+	Similarly in the respective tc_frob_label implementation functions.
+	* config/tc-i386.c (md_pseudo_table): Move file and loc to
+	non-elf section; add loc_mark_labels.
+	* config/tc-ia64.c (struct label_fix): Add dw2_mark_labels.
+	(ia64_flush_insns): Check for marked labels; emit line entry if so.
+	(emit_one_bundle): Similarly.
+	(ia64_frob_label): Record marked labels.
+	* config/tc-m68hc11.h (tc_frob_label): Remove.
+	* config/tc-ms1.c (md_pseudo_table): Remove file and loc.
+	* config/tc-sh.h (tc_frob_label): Pass sym to sh_frob_label.
+	* config/tc-sh64.h (tc_frob_label): Likewise.
+	* doc/as.texinfo (LNS directives): Docuement .loc_mark_blocks.
+
+2005-09-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (pseudo_set): Set segment of expression syms to expr_section.
+
+2005-09-14  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (tc_x86_regname_to_dw2regnum): Add selector
+	registers, floating point control and status words, and mxcsr as
+	well as (for 64-bit code) segment base registers and rflags.
+
+2005-09-09  Dmitry Diky  <diwil@spec.ru>
+
+	* config/tc-msp430.c (msp430_operands): Undo last changes. Instead...
+	(msp430_relax_frag): add a guard check to ensure that final fr_subtype
+	has been reached.
+
+2005-09-08  Chao-ying Fu  <fu@mips.com>
+
+	* doc/as.texinfo: Document -mdsp and -mno-dsp options.
+	* doc/c-mips.texi: Likewise, and document ".set dsp" and ".set nodsp"
+	directives.
+
+2005-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_smi, do_t_smi): Rename ...
+	(do_smc, do_t_smc): ... to this.
+	(insns): Remane smi to smc.
+	(md_apply_fix, tc_gen_reloc): Rename BFD_RELOC_ARM_SMI to
+	BFD_RELOC_ARM_SMC.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* dwarf2dbg.c (dwarf2_where): Set line->isa.
+	(dwarf2_set_isa): New.
+	(dwarf2_directive_loc): Rearrange to allow all options on one line.
+	* dwarf2dbg.h (dwarf2_set_isa): Declare.
+	* doc/as.texinfo: Update .loc documentation.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* dwarf2dbg.c: Include safe-ctype.h.
+	(DWARF2_LINE_OPCODE_BASE): Bump to 13.
+	(current): Initialize.
+	(dwarf2_emit_insn): Clear DWARF2_FLAG_BASIC_BLOCK,
+	DWARF2_FLAG_PROLOGUE_END, DWARF2_FLAG_EPILOGUE_BEGIN.
+	(dwarf2_directive_file): Cope with invalid filename.
+	(dwarf2_directive_loc): Add handling for basic_block, prologue_end,
+	epilogue_begin, is_stmt, isa.
+	(emit_inc_line_addr): Move line_delta == 0, addr_delta == 0 special
+	case down lower.
+	(process_entries): Handle isa, DWARF2_FLAG_PROLOGUE_END,
+	and DWARF2_FLAG_EPILOGUE_BEGIN.
+	(out_debug_line): Emit sizes for DW_LNS_set_prologue_end,
+	DW_LNS_set_epilogue_begin, DW_LNS_set_isa.
+	* dwarf2dbg.h (DWARF2_FLAG_IS_STMT): Rename from DWARF2_FLAG_BEGIN_STMT.
+	(DWARF2_FLAG_BASIC_BLOCK): Rename from DWARF2_FLAG_BEGIN_BLOCK.
+	(DWARF2_FLAG_PROLOGUE_END, DWARF2_FLAG_EPILOGUE_BEGIN): New.
+	(struct dwarf2_line_info): Add isa member.
+	* doc/as.texinfo (LNS directives): New node.
+
+2005-09-07  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (append_insn): Undo last change.  Instead add
+	guard to suppress calling frag_grow if the current instruction is
+	one that allows a delay slot.
+
+2005-09-06  Chao-ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (mips_set_options): Add ase_mt for MT instructions.
+	(mips_opts): Add -1 to initialize ase_mt.
+	(file_ase_mt): New variable for -mmt.
+	(CPU_HAS_MT): New define.
+	(validate_mips_insn): Add supports for +t, +T, !, $, *, &, g operand
+	formats.
+	(mips_ip): Check ase_mt to enable MT instructions.
+	Handle !, $, *, &, +T, +t, g operand formats.
+	For "mftc1", "mfthc1", "cftc1", "mttc1", "mtthc1", "cttc1", we allow
+	odd float registers.
+	(OPTION_MT, OPTION_NO_MT): New define.
+	(OPTION_COMPAT_ARCH_BASE): Change because of inserting MT define.
+	(md_parse_option): Parse OPTION_MT and OPTION_NO_MT.
+	(mips_after_parse_args): Set ase_mt based on CPU.
+	(s_mipsset): Handle ".set mt" and ".set nomt".
+	(mips_elf_final_processing): Remind of adding new flag for MT ASE.
+	(md_show_usage): Show usage of -mmt and -mno-mt.
+	* doc/as.texinfo: Document -mmt and -mno-mt options.
+	* doc/c-mips.texi: Likewise, and document ".set mt" and ".set nomt"
+	directives.
+
+2005-09-06  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_it): Add relax field.
+	(T16_32_TAB): Add addi, addis, add_pc, add_sp, dec_sp, inc_sp,
+	b, bcond, ldr_pc, ldr_pc2, ldr_sp, str_sp, subi, subis.
+	(do_t_add_sub, do_t_addr, do_t_branch, do_t_ldst,
+	do_t_mov_cmp): Allow relaxation.
+	(output_relax_insn): New function.
+	(put_thumb32_insn): New function.
+	(output_inst): Use new functions.
+	(md_assemble): Don't throw error on relaxable instructions.
+	(insns): Change "b" entry from TCE(...) to tCE(...).
+	(md_estimate_size_before_relax): Return 2.
+	(md_convert_frag, relax_immediate, relax_adr, relax_addsub,
+	relax_branch, arm_relax_frag): New functions.
+	(arm_force_relocation): Return 0 for Thumb-2 immediate operand
+	relocations.
+	* config/tc-arm.h (md_convert_frag): Remove definition.
+	(md_relax_frag): Define.
+	(arm_relax_frag): Add prototype.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_rn_rd): Enforce SWP operand constraints.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (encode_arm_cp_address): Use
+	BFD_RELOC_ARM_T32_CP_OFF_IMM in thumb mode.
+	(do_iwmmxt_wldstbh): Use BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 in thumb
+	mode.
+	(md_assemble): Only allow coprocessor instructions when Thumb-2 is
+	available.
+	(cCE, cC3): Define.
+	(insns): Use them for coprocessor instructions.
+	(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM.
+	(get_thumb32_insn): New function.
+	(put_thumb32_insn): New function.
+	(md_apply_fix): Handle BFD_RELOC_ARM_T32_CP_OFF_IMM and
+	BFD_RELOC_ARM_T32_CP_OFF_IMM_S2.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (opcode_lookup): Look for infix opcode when
+	incorrect suffix matches.
+
+2005-09-01  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (append_insn): Correctly handle mips16 case
+	when the frags are different for the 2 instructions we want to
+	swap.  If the lengths of the 2 instructions are not the same, we
+	won't do the swap but emit an nop.
+
+2005-09-01  Dmitry Diky  <diwil@spec.ru>
+
+	* config/tc-msp430.c (msp430_operands): Emit dwarf2_emit_insn()
+	as appropriate. Change frag_variant() to frag_var() for relaxes.
+
+2005-08-29  Nick Clifton  <nickc@redhat.com>
+
+	* write.c (generic_force_reloc): Do not call S_FORCE_RELOC if
+	there is no symbol.
+
+2005-08-26  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (intel_e09): Set JumpAbsolute when seeing a PTR-
+	qualified operand of a branch.
+	(intel_bracket_expr): Set JumpAbsolute here...
+	(intel_e11): ... rather than here.
+
+2005-08-26  Christian Groessler  <chris@groessler.org>
+
+	* configure.tgt: Set bfd_gas also for z8k cpu.
+	* config/tc-z8k.c (s_segm): Use bfd_set_arch_mach to set machine
+	type.
+	(newfix): Adapt to bfd reloc types.
+	(build_bytes): Adapt to bfd reloc types.  Ensure that enough space
+	is available in the current frag.
+	(md_convert_frag): Adapt function parameters.
+	(tc_gen_reloc): New function.
+	(md_section_align): Use bfd_get_section_alignment.
+	(md_apply_fix): Adapt to bfd reloc types.  Fix handling of
+	BFD_RELOC_Z8K_IMM4L, BFD_RELOC_8, BFD_RELOC_16, and BFD_RELOC_32
+	relocations.
+	* config/tc-z8k.h (TARGET_ARCH): Define.
+	(tc_fix_adjustable): Define.
+
+2005-08-25  Chao-ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (mips_set_options): Add ase_dsp for DSP instructions.
+	(mips_opts): Add -1 to initialize ase_dsp.
+	(file_ase_dsp): New variable for -mdsp.
+	(CPU_HAS_DSP): New define.
+	(validate_mips_insn): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, ', :, @
+	operand formats.
+	(mips_ip): Add min_range and max_range for checking singed numbers.
+	Check ase_dsp to enable DSP instructions.
+	Handle 3, 4, 5, 6, 7, 8, 9, 0, ', :, @ operand formats.
+	(OPTION_DSP, OPTION_NO_DSP): New define.
+	(OPTION_COMPAT_ARCH_BASE): Change because of inserting DSP define.
+	(md_parse_option): Parse OPTION_DSP and OPTION_NO_DSP.
+	(mips_after_parse_args): Set ase_dsp based on CPU.
+	(s_mipsset): Handle ".set dsp" and ".set nodsp".
+	(mips_elf_final_processing): Remind of adding new flag for DSP ASE.
+	(md_show_usage): Show usage of -mdsp and -mno-dsp.
+
+2005-08-23  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add 5kf to the table of
+	cpu names.
+
+2005-08-23  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 1036
+	* config/tc-ppc.c (ppc_symbol_chars): Add '%' and '['.
+
+2005-08-23  Phil Edwards  <phil@codesourcery.com>
+
+	* configure.tgt (*-*-vxworks):  Match vxworks* instead.
+
+2005-08-22  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (object_64bit): New.
+	(i386_target_format): Initialize it.
+	(output_disp): Use object_64bit for relocation type determination.
+	(output_imm): Likewise.
+	(i386_validate_fix): Likewise.
+	(tc_gen_reloc): Likewise.
+	(lex_got): Likewise. Remove static mode_name. Change array size
+	of gotrel's rel field, and adjust its initializer. Adjust diagnostic.
+	(x86_cons): Use object_64bit for deciding whether quad fields can
+	have relocations.
+
+2005-08-18  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-h8300.h: Remove TC_RELOC_MANGLE/tc_reloc_mangle.
+	* config/tc-mcore.h: Likewise.
+	* config/tc-z8k.h: Likewise.
+	* config/tc-z8k.c: Likewise.
+	* config/tc-sh.h: Remove TC_RELOC_MANGLE and
+	sh_coff_reloc_mangle declaration.
+	* config/tc-sh.c: (md_apply_fix): Fix comment for case
+	BFD_RELOC_SH_USES.
+
+2005-08-18  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh64.c (sh64_target_format): Check preset_target_arch
+	to confirm that no ISA is specified.
+
+2005-08-18  Nick Clifton  <nickc@redhat.com>
+
+	* write.c (relax_segment): Count the number of frags being
+	processed and use this to compute a maximum limit on the number of
+	iterations that will be allowed when attempting to relax the
+	segment.
+
+2005-08-17  Danny Smith  <dannysmith@users.sourceforge.net>
+
+	* config/obj-coff.c (obj_coff_weak): Set auxiliary record
+	of NT weak externals to IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY.
+
+2005-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_set_cpu): Don't select 64-bit based on
+	default cpu.
+
+2005-08-15  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (do_t_mov_cmp): Fix encoding of i16-bit conditional
+	instructions.
+	(do_t_mvn_tst, do_t_neg, do_t_shift): Ditto.
+
+2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-ppc.c (parse_cpu): Add -me300 support.
+	(md_show_usage): Likewise.
+	* doc/c-ppc.texi (PowerPC-Opts): Document it.
+
+2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* config/tc-s390.c (md_parse_option):  Add cpu type z9-109.
+	(md_gather_operands): Add support for optional operands.
+
+2005-08-12  Dmitry Diky <diwil@spec.ru>
+	* config/tc-msp430.c (msp430_enable_relax): New flag.
+	(msp430_enable_polys): Likewise.
+	(OPTION_RELAX): New option.
+	(OPTION_POLYMORPHS): Likewise.
+	(md_longopts): New long options.
+	(md_show_usage): Updated.
+	(md_parse_option): Add new options handler.
+	(msp430_operands): Add check if polymorph insns are enabled.
+	(msp430_force_relocation_local): New function.
+	(md_apply_fix): Now delete relocs according to new flags combination.
+	(msp430_relax_frag): Convert long branches to short branches only if
+	flag msp430_enable_relax is set.
+	* config/tc-msp430.h (TC_FORCE_RELOCATION_LOCAL): Defined.
+	(msp430_force_relocation_local): Likewise.
+	* doc/c-msp430.texi: Describe new options.
+
+2005-08-11  Ian Lance Taylor  <ian@airs.com>
+
+	* Makefile.am ($(srcdir)/make-gas.com): Remove target.
+	(stamp-mk.com): Likewise.
+	(EXTRA_DIST): Remove make-gas.com from list.
+	(MOSTLYCLEANFILES): Remove stamp-mk.com from list.
+	* Makefile.in: Regenerate.
+
+2005-08-11  Hans-Peter Nilsson  <hp@axis.com>
+
+	* subsegs.c (subseg_change): Move declaration of seginfo to before
+	first statement.
+
+2005-08-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* README-vms: Delete.
+	* config-gas.com: Delete.
+	* makefile.vms: Delete.
+	* vmsconf.sh: Delete.
+	* config/atof-tahoe.c: Delete.
+	* config/m88k-opcode.h: Delete.
+	* config/obj-bout.c: Delete.
+	* config/obj-bout.h: Delete.
+	* config/obj-hp300.c: Delete.
+	* config/obj-hp300.h: Delete.
+	* config/tc-a29k.c: Delete.
+	* config/tc-a29k.h: Delete.
+	* config/tc-h8500.c: Delete.
+	* config/tc-h8500.h: Delete.
+	* config/tc-m88k.c: Delete.
+	* config/tc-m88k.h: Delete.
+	* config/tc-tahoe.c: Delete.
+	* config/tc-tahoe.h: Delete.
+	* config/tc-tic80.c: Delete.
+	* config/tc-tic80.h: Delete.
+	* config/tc-w65.c: Delete.
+	* config/tc-w65.h: Delete.
+	* config/te-aux.h: Delete.
+	* config/te-delt88.h: Delete.
+	* config/te-delta.h: Delete.
+	* config/te-dpx2.h: Delete.
+	* config/te-hp300.h: Delete.
+	* config/te-ic960.h: Delete.
+	* config/vms-a-conf.h: Delete.
+	* doc/c-a29k.texi: Delete.
+	* doc/c-h8500.texi: Delete.
+	* doc/c-m88k.texi: Delete.
+	* README: Remove obsolete examples, and list of supported targets.
+	* Makefile.am: Remove a29k, h8500, m88k, tahoe, tic80, w65,
+	bout and hp300 support.
+	(DEP_FLAGS): Don't define BFD_ASSEMBLER.
+	* configure.in: Remove --enable-bfd-assembler, need_bfd,
+	primary_bfd_gas.
+	* configure.tgt: Remove a29k, h8300-coff, h8500-*, i960 non-elf,
+	m68k non bfd, m88k, or32-coff, tic80-*, vax non-bfd, w65k-*, *-nindy.
+	* as.c: Remove all non-BFD_ASSEMBLER code, support for above targets.
+	* as.h: Likewise.
+	* dw2gencfi.c: Likewise.
+	* dwarf2dbg.c: Likewise.
+	* ehopt.c: Likewise.
+	* input-file.c: Likewise.
+	* listing.c: Likewise.
+	* literal.c: Likewise.
+	* messages.c: Likewise.
+	* obj.h: Likewise.
+	* output-file.c: Likewise.
+	* read.c: Likewise.
+	* stabs.c: Likewise.
+	* struc-symbol.h: Likewise.
+	* subsegs.c: Likewise.
+	* subsegs.h: Likewise.
+	* symbols.c: Likewise.
+	* symbols.h: Likewise.
+	* tc.h: Likewise.
+	* write.c: Likewise.
+	* write.h: Likewise.
+	* config/aout_gnu.h: Likewise.
+	* config/obj-aout.c: Likewise.
+	* config/obj-aout.h: Likewise.
+	* config/obj-coff.c: Likewise.
+	* config/obj-coff.h: Likewise.
+	* config/obj-evax.h: Likewise.
+	* config/obj-ieee.h: Likewise.
+	* config/tc-arm.c: Likewise.
+	* config/tc-arm.h: Likewise.
+	* config/tc-avr.c: Likewise.
+	* config/tc-avr.h: Likewise.
+	* config/tc-crx.h: Likewise.
+	* config/tc-d10v.h: Likewise.
+	* config/tc-d30v.h: Likewise.
+	* config/tc-dlx.h: Likewise.
+	* config/tc-fr30.h: Likewise.
+	* config/tc-frv.h: Likewise.
+	* config/tc-h8300.c: Likewise.
+	* config/tc-h8300.h: Likewise.
+	* config/tc-hppa.h: Likewise.
+	* config/tc-i370.h: Likewise.
+	* config/tc-i386.c: Likewise.
+	* config/tc-i386.h: Likewise.
+	* config/tc-i860.h: Likewise.
+	* config/tc-i960.c: Likewise.
+	* config/tc-i960.h: Likewise.
+	* config/tc-ip2k.h: Likewise.
+	* config/tc-iq2000.h: Likewise.
+	* config/tc-m32c.h: Likewise.
+	* config/tc-m32r.h: Likewise.
+	* config/tc-m68hc11.h: Likewise.
+	* config/tc-m68k.c: Likewise.
+	* config/tc-m68k.h: Likewise.
+	* config/tc-maxq.c: Likewise.
+	* config/tc-maxq.h: Likewise.
+	* config/tc-mcore.c: Likewise.
+	* config/tc-mcore.h: Likewise.
+	* config/tc-mn10200.h: Likewise.
+	* config/tc-mn10300.c: Likewise.
+	* config/tc-mn10300.h: Likewise.
+	* config/tc-ms1.h: Likewise.
+	* config/tc-msp430.c: Likewise.
+	* config/tc-msp430.h: Likewise.
+	* config/tc-ns32k.c: Likewise.
+	* config/tc-ns32k.h: Likewise.
+	* config/tc-openrisc.h: Likewise.
+	* config/tc-or32.c: Likewise.
+	* config/tc-or32.h: Likewise.
+	* config/tc-ppc.c: Likewise.
+	* config/tc-ppc.h: Likewise.
+	* config/tc-s390.h: Likewise.
+	* config/tc-sh.c: Likewise.
+	* config/tc-sh.h: Likewise.
+	* config/tc-sparc.c: Likewise.
+	* config/tc-tic30.c: Likewise.
+	* config/tc-tic30.h: Likewise.
+	* config/tc-tic4x.c: Likewise.
+	* config/tc-tic4x.h: Likewise.
+	* config/tc-tic54x.c: Likewise.
+	* config/tc-tic54x.h: Likewise.
+	* config/tc-v850.h: Likewise.
+	* config/tc-vax.c: Likewise.
+	* config/tc-vax.h: Likewise.
+	* config/tc-xstormy16.h: Likewise.
+	* config/tc-xtensa.h: Likewise.
+	* config/tc-z8k.c: Likewise.
+	* config/tc-z8k.h: Likewise.
+	* config/vms-a-conf.h
+	* doc/Makefile.am: Likewise.
+	* doc/all.texi: Likewise.
+	* doc/as.texinfo: Likewise.
+	* doc/internals.texi: Likewise.
+	* doc/Makefile.in: Regenerate.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* config.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2005-08-09  Nick Clifton  <nickc@redhat.com>
+
+	PR 1070
+	* macro.c (getstring): Do not treat round parentheses exactly the
+	same as angle brackets - the parentheses need to be preserved and
+	passed on to the macro processing code.
+
+2005-08-08  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-msp430.c (MSP430_ISA_21): Define.
+	(mcu_types): Add entries for msp430x21xx variants.
+
+2005-08-08  Nick Clifton  <nickc@redhat.com>
+
+	PR 1070
+	* macro.c (getstring): Treat round parentheses in the same way as
+	angle brackets.
+	(get_any_string): Likewise.
+
+2005-08-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/1118
+	* as.c (parse_args): Handle -al=<FILE>.
+
+2005-08-07  Nick Clifton  <nickc@redhat.com>
+
+	* read.c (s_app_line): Accept a line number of 0 for compatibility
+	with gcc's output for assembler-with-cpp files.
+
+2005-08-05  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (current_it_mask, current_cc): New variables.
+	(do_t_add_sub): Use correct encodings inside IT block.
+	(do_t_arit3c): Ditto.
+	(do_t_it): Simplify logic.  Set current_it_mask and current_cc.
+	(md_assemble): Verify conditional suffixes agains IT blocks.
+
+2005-08-05  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (encode_thumb32_immediate): Only accept shifted
+	constants.
+	(encode_thumb32_shifted_operand): Prohibit register shifts.
+	(encode_thumb32_addr_mode): Fix typo.
+	(insns): Correct thumb2 ldm and stm opcodes.
+
+2005-08-02  Khem Raj  <kraj@mvista.com>
+
+	* config/tc-arm.c (do_iwmmxt_wldstd): Correct the offset range for
+	WLDRD/WSTRD instruction.
+
+2005-08-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (md_apply_fix <ELF>): Don't warn on overflow
+	if emitting a reloc.
+
+2005-07-29  Thiemo Seufer  <ths@networkno.de>
+
+	* config/tc-mips.c (s_mips_globl): Allow multiple symbols per .globl.
+
+2005-07-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (T16_32_TAB): Add "addr". Fix encoding of push and
+	pop.
+	(do_t_addr): Implement 32-bit variant.
+	(do_t_push_pop): Make some errors warnings.  Handle single register
+	32-bit case.
+	(insns): Use tCE for adr.
+	(md_pcrel_from_section): Handle BFD_RELOC_ARM_T32_ADD_PC12.
+	(md_apply_fix): Ditto.
+
+2005-07-29  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (parse_tb): New function.
+	(enum operand_parse_code): Add OP_TB.
+	(parse_operands): Handle OP_TB.
+	(do_t_add_sub_w, do_t_tb): New functions.
+	(insns): Add entries for addw, subw, tbb and tbh.
+	(md_apply_fix): Handle BFD_RELOC_ARM_T32_IMM12.
+
+2005-07-29  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (m32r_check_fixup): Fixed X_op check.
+
+2007-07-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (handle_large_common): Declare only for ELF.
+
+2005-07-27  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.h (unw_r_record): Change type of fr_mem to unsigned
+	int.
+	(unw_p_record): Remove unused/redundant fields imask and rmask.
+	Combine spoff and pspoff into a union. Combine gr and br into a
+	union. Change type of grmask and brmask to unsigned char. Change type
+	of frmask to unsigned int.
+	(unw_x_record): Combine spoff, pspoff, and treg into a union.
+	* config/tc-ia64.c (unwind): New field 'pending_saves'.
+	(check_pending_save): New.
+	(alloc_record): Clear out entire record.
+	(output_psp_gr): Use renamed structure fields.
+	(output_psp_sprel): Likewise.
+	(output_rp_gr): Likewise.
+	(output_rp_br): Likewise.
+	(output_rp_psprel): Likewise.
+	(output_rp_sprel): Likewise.
+	(output_pfs_gr): Likewise.
+	(output_pfs_psprel): Likewise.
+	(output_pfs_sprel): Likewise.
+	(output_preds_gr): Likewise.
+	(output_preds_psprel): Likewise.
+	(output_preds_sprel): Likewise.
+	(output_spill_base): Likewise.
+	(output_unat_gr): Likewise.
+	(output_unat_psprel): Likewise.
+	(output_unat_sprel): Likewise.
+	(output_lc_gr): Likewise.
+	(output_lc_psprel): Likewise.
+	(output_lc_sprel): Likewise.
+	(output_fpsr_gr): Likewise.
+	(output_fpsr_psprel): Likewise.
+	(output_fpsr_sprel): Likewise.
+	(output_priunat_gr): Likewise.
+	(output_priunat_psprel): Likewise.
+	(output_priunat_sprel): Likewise.
+	(output_bsp_gr): Likewise.
+	(output_bsp_psprel): Likewise.
+	(output_bsp_sprel): Likewise.
+	(output_bspstore_gr): Likewise.
+	(output_bspstore_psprel): Likewise.
+	(output_bspstore_sprel): Likewise.
+	(output_rnat_gr): Likewise.
+	(output_rnat_psprel): Likewise.
+	(output_rnat_sprel): Likewise.
+	(output_spill_psprel): Likewise.
+	(output_spill_sprel): Likewise.
+	(output_spill_reg): Likewise.
+	(output_fr_mem): Likewise. Allocate one unwind record per set mask
+	bit.
+	(output_frgr_mem): Likewise.
+	(output_gr_mem): Likewise.
+	(output_br_mem): Likewise.
+	(output_gr_gr): Likewise.
+	(output_br_gr): Likewise.
+	(fixup_unw_records): Likewise.
+	(process_one_record): Use renamed structure fields. For gr_gr and
+	br_gr, collect mask from chain of records before output.
+	(in_prologue): Simplify and eliminate early returns. Call
+	check_pending_save.
+	(in_body): Simplify and eliminate early returns.
+	(dot_body): Call check_pending_save.
+	(md_assemble): Update comment. Deal with pending saves.
+
+2005-07-26  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (optimize_imm): Calculate candidate immediates
+	mask from guessed suffix, but mask out other immediate types only
+	if at least on candidate is valid for the insn.
+
+2005-07-25  DJ Delorie  <dj@redhat.com>
+
+	* config/tc-m32c.c (md_cgen_lookup_reloc): Add 8 bit operands.
+	Support %mod() modifiers from opcodes.
+	* doc/c-m32c.texi (M32C-Modifiers): New section.
+
+2005-07-25  Jan Hubicka  <jh@suse.cz>
+	    H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-elf.c: Include "elf/x86-64.h" if TC_I386 is
+	defined.
+	(elf_com_section_ptr): New.
+	(elf_begin): Set elf_com_section_ptr to bfd_com_section_ptr.
+	(elf_common_parse): Make it global. Use elf_com_section_ptr
+	instead of bfd_com_section_ptr.
+	(obj_elf_change_section): Handle x86-64 large bss sections.
+
+	* config/obj-elf.h (elf_com_section_ptr): New.
+	(elf_common_parse): New.
+
+	* config/tc-i386.c (handle_large_common): New.
+	(md_pseudo_table): Add "largecomm".
+	(x86_64_section_letter): New.
+	(x86_64_section_word): New.
+
+	* config/tc-i386.h (x86_64_section_word): New.
+	(x86_64_section_letter): New.
+	(md_elf_section_letter): New. Defined.
+	(md_elf_section_word): Likewise.
+
+2005-07-21  Ralf Corsepius  <ralf.corsepius@rtems.org>
+
+	* configure.tgt: Remove i386-*-rtemself*.
+	Remove sparc-*-rtemself*.
+
+2005-07-21  Ben Elliston  <bje@gnu.org>
+
+	* config/tc-m68k.h: Remove TE_LYNX conditional code.
+
+2005-07-21  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (encode_thumb32_addr_mode): Don't set
+	inst.reloc.pc_rel.
+
+2005-07-20  Tavis Ormandy <taviso@gentoo.org>
+
+	* messages.c: Use vsnprintf instead of vsprintf.
+
+2005-07-20  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (tc_gen_reloc): Check BFD_RELOC_32_PCREL and
+	BFD_RELOC_16_PCREL to Support R_M32R_REL32.
+
+2005-07-18  Nick Clifton  <nickc@redhat.com>
+
+	* configure.tgt: Restore alpha ordering to list of arches.
+
+2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* tc-hppa.c (pa_ip): Reject match for '#' immediate if not pa20.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (md_begin): Use IS_ELF.
+	(tc_i386_fix_adjustable): Likewise.
+	(md_estimate_size_before_relax): Likewise.
+	(md_apply_fix): Likewise.
+	(i386_target_format): Likewise.
+	(lex_got): Define to NULL when not ELF or when LEX_AT. Check IS_ELF.
+	(i386_immediate): Remove #ifdef LEX_AT.
+	(i386_displacement): Likewise.
+	* config/tc-i386.h (x86_cons): Prototype only when ELF and when not
+	LEX_AT.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (reloc): Convert to ISO C90. Change first
+	parameter to unsigned. Parameter sign now is tristate - zero/
+	positive mean unsigned/signed, negative means signedness doesn't
+	matter. Check field size,
+	signedness, and pcrel-ness are in agreement between relocated field
+	and relocation type. Adjust diagnostics.
+	(optimize_imm): And type mask of operand instead of overwriting it.
+	(lex_got): Convert to ISO C90. Add third parameter. Add new field to
+	local structure and initialize gotrel accordingly. Pass caller as
+	mask of types that the operator can match.
+	(x86_cons_fix_new): Let reloc know that signedness of relocation
+	doesn't matter.
+	(x86_pe_cons_fix_new): Likewise.
+	(x86_cons): Pass additional argument to lex_got.
+	(i386_immediate): New local variable 'types'. Pass its address as
+	additional argument to lex_got. Mask out operand types not supported
+	befoe returning.
+	(i386_displacement): Likewise. Set bigdisp to all types supported in
+	64-bit mode, combining the previously split initialization.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (parse_insn): Reject prefix if unavailable in
+	current mode.
+
+2005-07-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/tc-hppa.c (pa_ip): Search entire mnemonic before considering
+	promoted match.
+
+2005-07-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
+
+	* gas/config/tc-i386.h (CpuVMX): New.
+	(CpuUnknownFlags): Add CpuVMX.
+
+2005-07-14  Jim Blandy  <jimb@redhat.com>
+
+	Add support for the Renesas M32C.
+	* Makefile.am (CPU_TYPES): List m32c.
+	(TARGET_CPU_CFILES): List config/tc-m32c.c.
+	(TARGET_CPU_HFILES): List config/tc-m32c.h.
+	* configure.in: Add case for m32c.
+	* configure.tgt: Add cases for m32c and m32c-*-elf.
+	* configure: Regenerated.
+	* config/tc-m32c.c, config/tc-m32c.h: New files.
+	* doc/Makefile.am (CPU_DOCS): Add c-m32c.texi.
+	* doc/Makefile.in: Regenerated.
+	* doc/all.texi: Set M32C.
+	* doc/as.texinfo: Add text for the M32C-specific options and line
+	comment characters, and refer to c-m32c.texi.
+	* doc/c-m32c.texi: New file.
+
+2005-07-14  Nick Clifton  <nickc@redhat.com>
+
+	PR 1069
+	* config/tc-crx.c (reset_vars): Use strncpy to prevent overflowing
+	the ins_parse buffer.
+
+2005-07-10  Ralf Corsepius <ralf.corsepius@rtems.org>
+
+	* configure.tgt: Remove a29k-*-rtems*, hppa*-*-rtems*,i386-go32-rtems*,
+	i386-*-rtemscoff*, sparc-*-rtemsaout*.
+
+2005-07-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (optimize_disp): Optimize signed 32bit
+	displacements.
+
+2005-07-08  Ben Elliston  <bje@au.ibm.com>
+
+	* frags.h: Remove ANSI_PROTOTYPES conditional code.
+	* config/obj-elf.h: Likewise.
+	* config/tc-h8300.h: Likewise.
+	* config/tc-h8500.h: Likewise.
+	* config/tc-i370.h: Likewise.
+	* config/tc-i386.h: Likewise.
+	* config/tc-m68hc11.h: Likewise.
+	* config/tc-m68k.h: Likewise.
+	* config/tc-ppc.h: Likewise.
+	* config/tc-s390.h: Likewise.
+	* config/tc-sh.h: Likewise.
+	* config/tc-sparc.h: Likewise.
+	* config/tc-tic30.c: Likewise.
+	* config/tc-w65.h: Likewise.
+	* config/tc-xtensa.h: Likewise.
+
+2005-07-08  Hans-Peter Nilsson  <hp@axis.com>
+
+	PR gas/1049
+	* config/tc-cris.h (MD_APPLY_SYM_VALUE): Define.
+
+2005-07-07  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
+
+	* config/tc-tic30.c (debug): Add format attribute.  Fix format
+	bugs.
+
+2005-07-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (cpu_arch): Add sse3.
+
+	* config/tc-i386.h (CpuSSE3): Renamed from ...
+	(CpuPNI): This. Defined as CpuSSE3.
+
+	* doc/c-i386.texi: Document .sse3.
+
+2005-07-06  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (nop): Use zero for L-unit pseudo-nop.
+
+2005-07-05  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-pdp11.c (md_apply_fix): Cast first argument to
+	md_chars_to_numbers to an unsigned pointer in order to avoid a
+	compile time warning.
+
+2005-07-05  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-ppc.c (ppc_target_format): Add VxWorks.
+
+2005-07-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* config/tc-ms1.c: New.
+	* config/tc-ms1.h: New.
+	* testsuite/gas/ms1/allinsn.d: New.
+	* testsuite/gas/ms1/allinsn.s: New.
+	* testsuite/gas/ms1/badinsn.s: New.
+	* testsuite/gas/ms1/badinsn1.s: New.
+	* testsuite/gas/ms1/badoffsethigh.s: New.
+	* testsuite/gas/ms1/badoffsetlow.s: New.
+	* testsuite/gas/ms1/badorder.s: New.
+	* testsuite/gas/ms1/badreg.s: New.
+	* testsuite/gas/ms1/badsignedimmhigh.s: New.
+	* testsuite/gas/ms1/badsignedimmlow.s: New.
+	* testsuite/gas/ms1/badsyntax.s: New.
+	* testsuite/gas/ms1/badsyntax1.s: New.
+	* testsuite/gas/ms1/badunsignedimmhigh.s: New.
+	* testsuite/gas/ms1/badunsignedimmlow.s: New.
+	* testsuite/gas/ms1/errors.exp: New.
+	* testsuite/gas/ms1/ldst.s: New.
+	* testsuite/gas/ms1/misc.d: New.
+	* testsuite/gas/ms1/misc.s: New.
+	* testsuite/gas/ms1/ms1-16-003.d: New.
+	* testsuite/gas/ms1/ms1-16-003.s: New.
+	* testsuite/gas/ms1/ms1.exp: New.
+	* testsuite/gas/ms1/msys.d: New.
+	* testsuite/gas/ms1/msys.s: New.
+	* testsuite/gas/ms1/relocs.d: New.
+	* testsuite/gas/ms1/relocs.exp: New.
+	* testsuite/gas/ms1/relocs1.s: New.
+	* testsuite/gas/ms1/relocs2.s: New.
+
+2005-07-05  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.h (CpuSVME): New.
+	(CpuUnknownFlags): Include CpuSVME.
+	* config/tc-i386.c (cpu_arch): Add .pacifica and .svme. Add opteron
+	as alias of sledgehammer.
+	(md_assemble): Include invlpga in the check for insns with two source
+	operands.
+	(process_operands): Include SVME insns in the check for ignored
+	segment overrides. Adjust diagnostic.
+	(i386_index_check): Special-case SVME insns with memory operands.
+
+2005-07-04  Khem Raj  <kraj@mvista.com>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* tc-arm.c (struct arm_it): Make operands.imm signed to match its
+	use an immediate value.
+	(parse_vfp_reg_list): Make the 2nd parameter an unsigned pointer
+	since the register field of the operands structure is unsigned.
+	(s_arm_unwind_save_vfp): Make "reg" unsigned.
+	(parse_operands): Make the 2ns parameter an unsigned pointer to
+	match its use.
+	(do_ldrd): When using the imm field of the operands structure as a
+	second register field, treat it as unsigned.
+
+2005-07-04  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 1004
+	* config/obj-elf.c (obj_elf_change_section): Use backend
+	get_sec_type_attr.
+
+2005-07-01  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (line_separator_chars): Add '{' and '}'.
+	(output_spill_psprel, output_spill_psprel_p): Combine.
+	(output_spill_sprel, output_spill_sprel_p): Combine.
+	(output_spill_reg, output_spill_regp_p): Combine.
+	(process_one_record): Handle psp_psprel.
+	(parse_predicate_and_operand): New.
+	(convert_expr_to_ab_reg): Two new parameters. Return void. Always
+	initialize output values. Emit diagnostic case here.
+	(convert_expr_to_xy_reg): Likewise. Don't allow r0, f0, and f1.
+	(add_unwind_entry): New second parameter. Allow first parameter to
+	be NULL. Parse optional tag, emit warning about further support for
+	it otherwise being missing. Check end-of-line when requested.
+	(dot_fframe): Clear operand when wrong. Allow tag.
+	(dot_vframe): Likewise.
+	(dot_vframesp): Likewise. Rename parameter, issue warning when psp
+	relative.
+	(dot_vframepsp): Remove.
+	(dot_altrp): Clear operand when wrong. Allow tag.
+	(dot_save): Likewise. Let default case also go through
+	add_unwind_entry.
+	(dot_savemem): Likewise.
+	(dot_restore): Don't return when wrong operand. Allow tag.
+	(dot_spillreg, dot_spillreg_p): Combine. Simplify by using
+	parse_predicate_and_operand and the new arguments to
+	convert_expr_to_ab_reg and convert_expr_to_xy_reg. Don't return
+	when wrong operand. Allow tag.
+	(dot_restorereg, dot_restorereg_p): Likewise.
+	(dot_spillmem, dot_spillmem_p): Likewise.
+	(dot_saveg): Clear operand when wrong. Perform tighter operand
+	checks. Allow tag.
+	(dot_savef): Likewise.
+	(dot_saveb): Likewise.
+	(dot_savegf): Likewise.
+	(dot_spill): Remove end-of-line check. 	Combine. Simplify by using
+	parse_predicate_and_operand and the new arguments to
+	convert_expr_to_ab_reg and convert_expr_to_xy_reg. Don't return
+	when wrong operand. Allow tag.
+	(popcount): New.
+	(dot_label_state): Don't return when wrong operand.
+	(dot_copy_state): Likewise.
+	(dot_unwabi): Likewise. Check if in prologue.
+	(dot_body): Don't call demand_empty_rest_of_line.
+	(dot_prologue): Type of mask and grsave is unsigned. Perform tighter
+	operand checks.
+	(md_pseudo_table): Also use dot_restorereg for .restorereg.p. Also
+	use dot_spillreg for .spillreg.p. Also use dot_spillmem for
+	.spillpsp.p and .spillsp.p. Also use dot_vframesp for .vframepsp.
+	(parse_operand): New second parameter. Don't deal with '}' here
+	anymore. Don't advance past end-of-line.
+	(parse_operands): Pass second argument to parse_operand.
+	(ia64_start_line): Prevent out-of-bounds access through
+	input_line_pointer. Deal with '}' here.
+	(ia64_unrecognized_line): Don't deal with '}' here.
+	(dot_alias): Use ignore_rest_of_line not its deprecated alias
+	discard_rest_of_line.
+
+2005-06-30  Zack Weinberg  <zack@codesourcery.com>
+
+	* config/tc-arm.c (T_OPCODE_BRANCH, encode_arm_addr_mode_2)
+	(encode_arm_addr_mode_3, encode_arm_cp_address, do_blx, do_t_blx)
+	(do_t_branch, insns [b, bl]): Don't encode pipeline offset.
+	(do_branch): Always set inst.reloc.pc_rel.
+	(s_arm_elf_cons): Disallow use of (plt) suffix.
+	(do_adrl): Adjust X_add_number unconditionally.
+	(md_pcrel_from): Rename md_pcrel_from_section, add second segT
+	argument.  Handle all adjustment for pipeline offset here.
+	(md_apply_fix): No need to undo work of md_pcrel_from.  No
+	need to extract pre-encoded pipeline adjustments from various
+	branch instructions.  Generally, assume instructions are already
+	all-bits-zero in the field being fixed up.  Remove all OBJ_ELF
+	special cases.  Handle BFD_RELOC_ARM_PLT32 like
+	BFD_RELOC_ARM_PCREL_BRANCH.
+	(tc_gen_reloc): Remove OBJ_ELF special case.
+	* config/tc-arm.c: Define MD_PCREL_FROM_SECTION.
+
+2005-06-30  Ben Elliston  <bje@gnu.org>
+
+	* Makefile.am (check-DEJAGNU): Don't search for expect.
+	* Makefile.in: Regenerate.
+
+2005-06-30  Ben Elliston  <bje@gnu.org>
+
+	* Makefile.am (EXPECT): Set to expect.
+	(RUNTEST): Likewise, set to runtest.
+	* Makefile.in: Regenerate.
+
+2005-06-23  Ben Elliston  <bje@gnu.org>
+
+	* config/m68k-parse.h: Use ISO C90.
+	* config/m68k-parse.y: Likewise.
+	* config/tc-m68k.h: Likewise.
+
+2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 1013
+	* config/tc-i386.c (md_assemble): Don't call optimize_disp on
+	movabs.
+	(optimize_disp): Optimize only if possible. Don't use 64bit
+	displacement on non-constants and do same on constants if
+	possible.
+
+2005-06-17  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (reloc): Also handle BFD_RELOC_64_PCREL.
+	(tc_i386_fix_adjustable): Include BFD_RELOC_X86_64_GOTOFF64,
+	BFD_RELOC_X86_64_DTPOFF64, and BFD_RELOC_X86_64_TPOFF64.
+	(output_disp): Do GOTPC conversion also for BFD_RELOC_X86_64_32S
+	and BFD_RELOC_32_PCREL. Use BFD_RELOC_X86_64_GOTPC32 instead of
+	aborting.
+	(output_imm): Do GOTPC conversion also for BFD_RELOC_X86_64_32S.
+	Use BFD_RELOC_X86_64_GOTPC32 instead of aborting.
+	(tc_gen_reloc): Do GOTPC conversion also for BFD_RELOC_32_PCREL.
+	Use BFD_RELOC_X86_64_GOTPC32 instead of aborting. Also handle
+	BFD_RELOC_X86_64_GOTOFF64, BFD_RELOC_X86_64_GOTPC32,
+	BFD_RELOC_X86_64_DTPOFF64, and BFD_RELOC_X86_64_TPOFF64. Also
+	convert 8-byte pc-relative relocations.
+	(lex_got): Use BFD_RELOC_X86_64_GOTOFF64 for 64-bit @gotoff.
+	(i386_validate_fix): Likewise.
+	(x86_cons): Also handle quad values in 64-bit mode.
+	(i386_displacement): Also handle BFD_RELOC_X86_64_GOTOFF64.
+	(md_apply_fix): Include BFD_RELOC_X86_64_DTPOFF64 and
+	BFD_RELOC_X86_64_TPOFF64 in the TLS check. Also convert BFD_RELOC_64
+	to pc-relative variant. Also check for BFD_RELOC_64_PCREL.
+
+2005-06-13  Zack Weinberg  <zack@codesourcery.com>
+
+	* config/tc-arm.c (find_real_start): Check S_IS_LOCAL on
+	symbolP as well as for names with a leading dot.  Use ACONCAT.
+	(md_apply_fix): For branch relocations, only replace value
+	with fixP->fx_offset (under #ifdef OBJ_ELF) when !fixP->fx_done.
+	(arm_force_relocation): Remove #ifdef OBJ_ELF case.
+	* config/tc-arm.h (LOCAL_LABEL): Remove unnecessary parentheses.
+	(LOCAL_LABEL_PREFIX): Don't define.
+
+2005-06-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-hppa.c (pa_block): Allocate just one byte for the
+	fill pattern.
+
+2005-06-08  James E Wilson  <wilson@specifixinc.com>
+
+	PR 994
+	* config/tc-ia64.c (slot_index): Revert last change.  If first_frag
+	is NULL, then emit a warning, and return the current index.
+
+2005-06-08  Tomas Hurka  <tom@hukatronic.cz>
+
+	PR 991
+	* config/tc-m68k.c (m68k_ip): Test for insn compatiblity using a
+	temporary copy of the operands array so that changes can be safely
+	backed out if the insn does not match.
+	(m68k_compare_opcode): Shortcut the test when the parameters are
+	the same.  Return 1 if the names match but the second opcode is
+	further on in the array than the first.
+
+2005-06-08  Nick Clifton  <nickc@redhat.com>
+
+	PR 994
+	* config/tc-ia64.c (slot_index): Check for a NULL first_frag.
+
+2005-06-08  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* config/tc-m32r.c (use_parallel): Change default value from 1 to 0.
+
+2005-06-07  Aldy Hernandez  <aldyh@redhat.com>
+	    Michael Snyder  <msnyder@redhat.com>
+	    Stan Cox  <scox@redhat.com>
+
+	* configure.in: Add ms1 case.
+
+	* configure: Regenerate.
+
+	* configure.tgt: Add ms1 case.
+
+2005-06-07  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.h (resource_table): Change units to unsigned chars.
+	* config/tc-xtensa.c (new_resource_table): Likewise.
+	(resize_resource_table): Likewise.
+	(release_resources): Fix assertion for unsigned values.
+
+2005-06-07  Zack Weinberg  <zack@codesourcery.com>
+
+	* cgen.c, cgen.h, tc.h, write.c, config/obj-coff.c
+	* config/tc-a29k.c, config/tc-alpha.c, config/tc-alpha.h
+	* config/tc-arc.c, config/tc-arc.h, config/tc-arm.c
+	* config/tc-arm.h, config/tc-avr.c, config/tc-avr.h
+	* config/tc-cris.c, config/tc-crx.c, config/tc-d10v.c
+	* config/tc-d10v.h, config/tc-d30v.c, config/tc-d30v.h
+	* config/tc-dlx.c, config/tc-dlx.h, config/tc-fr30.h
+	* config/tc-frv.c, config/tc-frv.h, config/tc-h8300.c
+	* config/tc-h8500.c, config/tc-hppa.c, config/tc-hppa.h
+	* config/tc-i370.c, config/tc-i370.h, config/tc-i386.c
+	* config/tc-i386.h, config/tc-i860.c, config/tc-i860.h
+	* config/tc-i960.c, config/tc-i960.h, config/tc-ia64.c
+	* config/tc-ip2k.c, config/tc-ip2k.h, config/tc-iq2000.c
+	* config/tc-iq2000.h, config/tc-m32r.c, config/tc-m32r.h
+	* config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c
+	* config/tc-m68k.h, config/tc-m88k.c, config/tc-maxq.c
+	* config/tc-mcore.c, config/tc-mcore.h, config/tc-mips.c
+	* config/tc-mips.h, config/tc-mmix.c, config/tc-mn10200.c
+	* config/tc-mn10300.c, config/tc-msp430.c, config/tc-ns32k.c
+	* config/tc-openrisc.h, config/tc-or32.c, config/tc-or32.h
+	* config/tc-pdp11.c, config/tc-pj.c, config/tc-pj.h
+	* config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c
+	* config/tc-s390.h, config/tc-sh64.c, config/tc-sh.c
+	* config/tc-sh.h, config/tc-sparc.c, config/tc-sparc.h
+	* config/tc-tahoe.c, config/tc-tic30.c, config/tc-tic4x.c
+	* config/tc-tic54x.c, config/tc-tic80.c, config/tc-v850.c
+	* config/tc-v850.h, config/tc-vax.c, config/tc-vax.h
+	* config/tc-w65.c, config/tc-xstormy16.c, config/tc-xstormy16.h
+	* config/tc-xtensa.c, config/tc-z8k.c:
+	Replace all instances of the string "_apply_fix3" with
+	"_apply_fix".
+	* po/POTFILES.in, po/gas.pot: Regenerate.
+
+2005-06-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	(POTFILES): Remove GAS_CFILES.
+	* Makefile.in: Regenerate.
+
+2005-06-07  David Ung  <davidu@mips.com>
+
+	* config/tc-mips.c (mips_cpu_info_table): Add cpu names m4k, 24k,
+	24kc, 24kf and 24kfx under MIPS32 release 2.
+
+2005-06-04  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (CE, C3, CM, UE, UF): Redefine without reference
+	to their Thumb-enabled equivalents.
+
+2005-06-01  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (load_register): Add leading "0x" to the
+	output of sprintf_vma().
+	(macro): Likewise.
+
+2005-06-01  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (TxCE, TxC3, TxCM, TUE, TUF): Remove redundant
+	test for the presence of thumb version of the parsing functions
+	since they must always exist and the test generates a compile time
+	warning message.
+
+2005-05-31  Richard Henderson  <rth@redhat.com>
+
+	* config/tc-alpha.c (O_lituse_jsrdirect): New.
+	(alpha_reloc_op): Add it.
+	(debug_exp): Handle it.
+	(DUMMY_RELOC_LITUSE_JSRDIRECT): New.
+	(emit_insn): Handle it.
+	* doc/c-alpha.texi (Alpha-Relocs): Document lituse_jsrdirect.
+
+2005-05-31  Christian Groessler  <chris@groessler.org>
+
+	* write.c (dump_section_relocs): Convert to ISO-C.
+	(write_relocs): Avoid signed/unsigned and fprintf argument
+	warnings in debug code.
+
+2005-05-26  Zack Weinberg  <zack@codesourcery.com>
+
+	* config/tc-arm.h (TC_FIX_TYPE): Change to int.
+	(TC_INIT_FIX_DATA): Initialize to 0, not NULL.
+	* config/tc-arm.c (fix_new_arm): Remove now-unnecessary cast.
+	(md_apply_fix3): Delete fix_is_thumb variable; refer to
+	fixP->tc_fix_data directly in the sole place it was used.
+	Explicitly truncate value, *valP, fixP->fx_addnumber, and
+	fixP->fx_offset to 32 bits, for consistent behavior between 32-
+	and 64-bit hosts.
+
+2005-05-27  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (struct proc_pending): New.
+	(unwind): Replace proc_start with proc_pending.
+	(unwind_diagnostic): Check unwind.proc_pending.sym.
+	(dot_proc): Replace unwind.proc_start with unwind.proc_pending.sym.
+	Check if previous proc not closed. Record all entry points.
+	(dot_endp): Replace unwind.proc_start with unwind.proc_pending.sym.
+	Set symbol sizes for entry points recorded in dot_proc. Check
+	arguments for consistency with respective .proc's.
+	(md_assemble): Replace unwind.proc_start with
+	unwind.proc_pending.sym.
+
+2005-05-27  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Restrict scope of ptr, end_ptr,
+	and last_ptr. Check all in-use slots for first one with non-NULL
+	unwind_record. Don't reload end_ptr before second update round.
+
+2005-05-26  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (extra_goodness): Update comment.
+	(md_begin): Add debugging code to print best_template table.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (md_begin): Don't try to match slot 2 of an MLX
+	template.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (ia64_gen_real_reloc_type): Also handle
+	BFD_RELOC_UNUSED when determining the width of the reloc.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_endp): Clear out all three pointers in unwind
+	section entry.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_radix): Rewrite.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (struct unw_rec_list): Remove next_slot_number
+	and next_slot_frag.
+	(alloc_record): Remove references to next_slot_number and
+	next_slot_frag.
+	(emit_one_bundle): Likewise.
+
+2005-05-22  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-v850.c (md_apply_fix3): Pass the address of the
+	message buffer when invoking the insert function.
+
+2005-05-21  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* config/tc-hppa.c (pa_ip): Promote architecture from PA 1.0 to 1.1
+	only if an instruction match is found.
+
+2005-05-20  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_assemble_vliw_tokens): Change subtraction
+	to addition in argument to xtensa_dwarf2_emit_insn.
+
+2005-05-19  Zack Weinberg  <zack@codesourcery.com>
+
+	* Makefile.am: Have 'all' depend on 'info'.
+	* Makefile.in: Regenerate.
+
+2005-05-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_force_relocation): Add BFD_RELOC_24_PLT_PCREL.
+
+2005-05-19  Anton Blanchard  <anton@samba.org>
+
+	* config/tc-ppc.c (parse_cpu): Handle "-mpower5".
+	(md_show_usage): Document it.
+	(ppc_setup_opcodes): Insert POWER5 mnemonics.
+	* doc/c-ppc.texi (PowerPC-Opts): Document "-mpower5".
+
+2005-05-19  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_endp): Don't use global symbol for unwind
+	relocations in unwind section.
+
+2005-05-18  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-v850.c (md_apply_fix3): Only use the insertion routine
+	if one exists.  Ignore any error messages it may produce, just
+	allow it to perform the insertion.
+
+2005-05-17  Zack Weinberg  <zack@codesourcery.com>
+
+	* hash.c (hash_lookup): Add len parameter.  All callers changed.
+	(hash_find_n): New interface.
+	* hash.h: Prototype hash_find_n.
+	* sb.c: Include as.h.
+	(scrub_from_sb, sb_to_scrub, scrub_position): New statics.
+	(sb_scrub_and_add_sb): New interface.
+	* sb.h: Prototype sb_scrub_and_add_sb.
+	* input-scrub.c (input_scrub_include_sb): Use sb_scrub_and_add_sb.
+
+	* config/tc-arm.h (TC_FORCE_RELOCATION_LOCAL): Remove
+	reference to BFD_RELOC_ARM_GOT12 which is never generated.
+	* config/tc-arm.c: Rewrite, adding Thumb-2 support.
+
+2005-05-17  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (gasver.texi): Don't use $<.
+	* doc/Makefile.in: Regenerated.
+
+2005-05-17  Nick Clifton  <nickc@redhat.com>
+
+	PR 876
+	* symbols.c (resolve_symbol_value): Do not move symbols whose
+	value expression has not been resolved or finalized into the
+	absolute section as this will confuse other parts of the assembler
+	into thinking that their value is zero.
+
+2005-05-17  Jan Beulich  <jbeulich@novell.com>
+
+	* read.c (_find_end_of_line): New.
+	(find_end_of_line): New.
+	(HANDLE_CONDITIONAL_ASSEMBLY): Use it.
+	(read_a_source_file): Use it.
+	(s_globl): Use it.
+	(s_macro): Use it.
+	(get_line_sb): Use it.
+	(s_errwarn): Replace discard_rest_of_line by ignore_rest_of_line.
+	(s_comm_internal): Likewise.
+	(s_lsym): Likewise.
+	(s_macro): Likewise.
+	(s_ignore): Use ignore_rest_of_line.
+	* read.h (find_end_of_line): Prototype.
+	(discard_rest_of_line): Remove prototype. #define to
+	ignore_rest_of_line.
+
+2005-05-17  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-v850,h (TC_FIX_TYPE): Define.
+	(TC_INIT_FIX_TYPE): Define.
+	* config/tc-v850.c (md_assemble): When creating a fix record the
+	operand in the tc_fix_data field.
+	(md_apply_fix3): When applying a resolved fix use the operand's
+	insertion procedure to store the value, if the operand has been
+	recorded.
+
+2005-05-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* Makefile.am (m68k-parse.c, itbl-parse.c): Update ylwrap
+	invocation.
+	* Makefile.in: Regenerated.
+
+2005-05-13  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_insnbuf_set_operand): Clarify error
+	message.
+	(xtensa_mark_zcl_first_insns): Fix incorrect nesting of conditional
+	for handling RELAX_CHECK_ALIGN_NEXT_OPCODE.
+
+2005-05-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (md_apply_fix3): Allow pcrel forms of BFD_RELOC_16,
+	BFD_RELOC_LO16, BFD_RELOC_HI16 and BFD_RELOC_HI16_S.
+
+2005-05-10  Michael Matz  <matz@suse.de>
+
+	* frags.c (frag_grow): Don't be too greedy in allocating memory.
+
+	* config/tc-hppa.c (pa_block): Check arguments to .block[z].
+
+2005-05-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR binutils/886
+	* config/tc-mmix.c (mmix_handle_mmixal): Rearrange slightly.
+	Handle label-without-colon before ordinary dot-pseudo as an
+	ordinary label.  Don't leak memory for label-without-colon alone
+	on a line.  Don't mmixal-munge operands for dot-pseudos.
+
+2005-05-10  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (get_any_string): Remove the two last parameters. Replace
+	references to the former expand parameter by using macro_alternate.
+	Simplify loop condition for checking for end-of-string.
+	(get_string): Remove redunant call to sb_skip_white.
+	(do_formals): Remove two last arguments to get_any_string.
+	(macro_expand): Likewise.
+	(expand_irp): Likewise.
+
+2005-05-10  Jan Beulich  <jbeulich@novell.com>
+
+	* read.c (s_macro): Move local variable 'local' to smaller scope.
+	Call sb_kill on it when done.
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (optimize_disp): Discard displacement entirely
+	when zero and not required by encoding constraints.
+
+2005-05-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 936
+	* config/tc-sh64.c (sh64_fake_label): New.
+
+	* config/tc-sh64.h (TC_FAKE_LABEL): New.
+
+	* doc/internals.texi (TC_FAKE_LABEL): Document.
+
+	* write.c (TC_FAKE_LABEL): New.
+	(adjust_reloc_syms): Use it.
+	(write_object_file): Likewise.
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (parse_insn): Disallow use of prefix separator
+	and comma in Intel mode.
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (tc_x86_regname_to_dw2regnum): Correct 64-bit mode
+	names to match ABI. Add more registers for 32-bit and 64-bit modes.
+	Make name array static and const. Adjust lookup to account for NULL
+	entries (standing for unused register numbers).
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (parse_insn): Consider all matching instructions
+	when checking for string instruction after string-only prefix.
+
+2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 940
+	* config/tc-ia64.c (start_unwind_section): Properly check
+	comdat group with SHF_GROUP.
+
+2005-05-06  Bob Wilson  <bob.wilson@acm.org>
+
+	* doc/c-xtensa.texi (Literal Directive): Spelling correction.
+
+2005-05-06  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c: Remove excess whitespace.
+	* config/tc-xtensa.h: Likewise.
+	* config/xtensa-istack.h: Likewise.
+	* config/xtensa-relax.c: Likewise.
+	* config/xtensa-relax.h: Likewise.
+
+2005-05-06  Nick Clifton  <nickc@redhat.com>
+
+	* sb.h: Fix formatting of comments.
+	* sb.c: Fix formatting of comments.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* sb.h (sb_add_buffer): Reintroduce.
+	* sb.c (sb_add_buffer): Likewise.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (new_formal, del_formal): New.
+	(do_formals): Use new_formal. Check for and parse qualifier. Warn if
+	required argument has default value. Stop looking for more formal
+	when there was a vararg one.
+	(macro_expand_body): Use new_formal and del_formal.
+	(macro_expand): Likewise. Initialize local variable err. Don't
+	return immediately when encountering an error. Warn when keyword
+	argument already had a value assigned. Eliminate duplicate clearing
+	of argument value. When current positional argument matches parameter
+	of vararg type, assign to it all the remaining arguments. Issue error
+	when required parameter does not have value.
+	(free_macro): Use del_formal.
+	(expand_irp): Initialize formal type. Free buffers associated with
+	formal prior to returning.
+	* macro.h (struct formal_struct): Add new field 'type' with new
+	enumeration type 'formal_type'.
+	* doc/as.texinfo: Document macro parameter qualifiers.
+	* NEWS: Mention new functionality.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* cond.c (s_ifb): New.
+	* read.c (potable): Add s_ifb as handler for .ifb and .ifnb.
+	* read.h (s_ifb): Prototype.
+	* doc/as.texinfo: Document .ifb and .ifnb.
+
+2005-05-05  Steve Ellcey  <sje@cup.hp.com>
+
+	* config/tc-ia64.c (MIN): Undef.
+
+2005-05-05  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-i386.h (ELF_TARGET_FORMAT): Define for TE_VXWORKS.
+
+2005-05-05  Matt Thomas <matt@3am-software.com>
+
+	* config/tc-vax.c (md_assemble): Don't assume a valueT is 4
+	bytes.
+
+2005-05-05  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	COPYING, app.c, as.c, as.h, asintl.h, atof-generic.c, bignum.h,
+	bit_fix.h, cgen.c, cgen.h, cond.c, debug.c, depend.c, dw2gencfi.c,
+	dw2gencfi.h, dwarf2dbg.c, dwarf2dbg.h, ecoff.c, ecoff.h, ehopt.c,
+	emul-target.h, emul.h, expr.c, expr.h, flonum-copy.c,
+	flonum-konst.c, flonum.h, frags.c, frags.h, hash.c, hash.h,
+	input-file.c, input-file.h, input-scrub.c, itbl-lex.h, itbl-lex.l,
+	itbl-ops.c, itbl-ops.h, itbl-parse.y, listing.c, listing.h,
+	literal.c, macro.c, macro.h, messages.c, obj.h, output-file.c,
+	output-file.h, read.c, read.h, sb.c, sb.h, stabs.c,
+	struc-symbol.h, subsegs.c, subsegs.h, symbols.c, symbols.h, tc.h,
+	write.c, write.h, config/aout_gnu.h, config/atof-ieee.c,
+	config/atof-vax.c, config/itbl-mips.h, config/m68k-parse.h,
+	config/m68k-parse.y, config/m88k-opcode.h, config/obj-aout.c,
+	config/obj-aout.h, config/obj-bout.c, config/obj-bout.h,
+	config/obj-coff.c, config/obj-coff.h, config/obj-ecoff.c,
+	config/obj-ecoff.h, config/obj-elf.c, config/obj-elf.h,
+	config/obj-evax.c, config/obj-evax.h, config/obj-hp300.c,
+	config/obj-hp300.h, config/obj-ieee.c, config/obj-ieee.h,
+	config/obj-multi.h, config/obj-som.c, config/obj-som.h,
+	config/tc-a29k.c, config/tc-a29k.h, config/tc-alpha.c,
+	config/tc-alpha.h, config/tc-arc.c, config/tc-arc.h,
+	config/tc-arm.h, config/tc-avr.c, config/tc-avr.h,
+	config/tc-cris.c, config/tc-cris.h, config/tc-crx.c,
+	config/tc-crx.h, config/tc-d10v.c, config/tc-d10v.h,
+	config/tc-d30v.c, config/tc-d30v.h, config/tc-dlx.c,
+	config/tc-dlx.h, config/tc-fr30.c, config/tc-fr30.h,
+	config/tc-frv.c, config/tc-frv.h, config/tc-generic.c,
+	config/tc-generic.h, config/tc-h8300.c, config/tc-h8300.h,
+	config/tc-h8500.c, config/tc-h8500.h, config/tc-hppa.c,
+	config/tc-hppa.h, config/tc-i370.c, config/tc-i370.h,
+	config/tc-i386.c, config/tc-i386.h, config/tc-i860.c,
+	config/tc-i860.h, config/tc-i960.c, config/tc-i960.h,
+	config/tc-ia64.c, config/tc-ia64.h, config/tc-ip2k.c,
+	config/tc-ip2k.h, config/tc-iq2000.c, config/tc-iq2000.h,
+	config/tc-m32r.c, config/tc-m32r.h, config/tc-m68851.h,
+	config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-m68k.c,
+	config/tc-m68k.h, config/tc-m88k.c, config/tc-m88k.h,
+	config/tc-maxq.c, config/tc-maxq.h, config/tc-mcore.c,
+	config/tc-mcore.h, config/tc-mips.c, config/tc-mips.h,
+	config/tc-mmix.c, config/tc-mmix.h, config/tc-mn10200.c,
+	config/tc-mn10200.h, config/tc-mn10300.c, config/tc-mn10300.h,
+	config/tc-msp430.c, config/tc-msp430.h, config/tc-ns32k.c,
+	config/tc-ns32k.h, config/tc-openrisc.c, config/tc-openrisc.h,
+	config/tc-or32.c, config/tc-or32.h, config/tc-pdp11.c,
+	config/tc-pdp11.h, config/tc-pj.c, config/tc-pj.h,
+	config/tc-ppc.c, config/tc-ppc.h, config/tc-s390.c,
+	config/tc-s390.h, config/tc-sh.c, config/tc-sh.h,
+	config/tc-sh64.c, config/tc-sh64.h, config/tc-sparc.c,
+	config/tc-sparc.h, config/tc-tahoe.c, config/tc-tahoe.h,
+	config/tc-tic30.c, config/tc-tic30.h, config/tc-tic4x.c,
+	config/tc-tic4x.h, config/tc-tic54x.c, config/tc-tic54x.h,
+	config/tc-tic80.c, config/tc-tic80.h, config/tc-v850.c,
+	config/tc-v850.h, config/tc-vax.c, config/tc-vax.h,
+	config/tc-w65.c, config/tc-w65.h, config/tc-xstormy16.c,
+	config/tc-xstormy16.h, config/tc-xtensa.c, config/tc-xtensa.h,
+	config/tc-z8k.c, config/tc-z8k.h, config/te-386bsd.h,
+	config/te-freebsd.h, config/te-hp300.h, config/te-hppa.h,
+	config/te-ic960.h, config/te-irix.h, config/te-nbsd.h,
+	config/te-netware.h, config/te-sparcaout.h, config/te-sun3.h,
+	config/te-tmips.h, config/te-vxworks.h, config/vax-inst.h,
+	config/xtensa-istack.h, config/xtensa-relax.c,
+	config/xtensa-relax.h, doc/fdl.texi
+
+2005-05-05  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-arm.c (arm_opts): Make -mlittle-endian switch set
+	the target_big_endian variable to false.
+
+2005-05-04  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-ecoff.c (ecoff_frob_file_before_fix): Correct section
+	list traversal.  Use bfd_section_list_prepend.
+	* config/tc-mmix.c (mmix_frob_file): Don't needlessly iterate
+	over the section list.
+	* config/tc-xtensa.c (xtensa_remove_section): Delete.
+	(xtensa_insert_section): Delete.
+	(xtensa_move_seg_list_to_beginning): Use bfd_section_list_remove
+	and bfd_section_list_prepend.
+	(xtensa_reorder_seg_list): Use bfd_section_list_remove and
+	bfd_section_list_insert_after.
+
+2005-05-03  Nick Clifton  <nickc@redhat.com>
+
+	* config/obj-ecoff.c (ecoff_frob_file_before_fix): Fix invocations
+	of bfd_section_list... macros.
+	* config/tc-mmix.c (mmix_frob_file): Likewise.
+	* config/tc-xtensa.c (xtensa_remove_section): Likewise.
+	(xtensa_insert_section): Likewise.
+
+	* macro.c (macro_hash): Remove static.
+	* macro.h (macro_hash): Provide an external declaration.
+
+2005-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* write.c (write_object_file): Use bfd_section_double_list_remove
+	to remove sections.
+
+2005-05-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (gasver.texi): Correct quoting.
+	* doc/Makefile.in: Regenerated.
+
+2005-04-29  Ralf Corsepius <ralf.corsepius@rtems.org>
+
+	* configure.tgt: Add h8300*-*-rtemscoff.
+	Switch h8300*-*-rtems* to elf.
+
+2005-04-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* hash.c: Undo the last change.
+	* hash.h: Likewise.
+
+2005-04-29  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am (gasver.texi): Depend on bfd/configure instead
+	of Makefile.
+	(DISTCLEANFILES): Remove.
+	(MAINTAINERCLEANFILES): Add asconfig.texi.
+	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2005-04-29  Ben Elliston  <bje@au.ibm.com>
+
+	* Makefile.am (GAS_CFILES): Remove bignum-copy.c.
+	(GENERIC_OBJS): Likewise, remove bignum-copy.o.
+	(bignum-copy.o): Remove.
+	* Makefile.in: Regenerate.
+	* makefile.vms (OBJS): Remove bignum-copy.obj.
+	* symbols.h (local_symbol_make): Remove declaration.
+	(verify_symbol_chain_2): Likewise.
+	* symbols.c (local_symbol_make): Make static.
+	(max_indent_level): Likewise.
+	(verify_symbol_chain_2): Remove.
+	* macro.c (macro_hash): Make static.
+	* messages.c (fprint_value): Remove.
+	* read.h (get_absolute_expr): Remove.
+	(emit_leb128_expr): Likewise.
+	(do_s_func): Likewise.
+	* read.c (do_s_func): Make static.
+	(emit_leb128_expr): Likewise.
+	(get_absolute_expr): Likewise.
+	* as.h (as_howmuch): Remove declaration.
+	(fprint_value): Likewise.
+	* as.c (myname): Make static.
+	* input-scrub.c (as_howmuch): Remove.
+	(as_1_char): Likewise.
+	* input-file.h (input_file_is_open): Remove.
+	* input-file.c (input_file_is_open): Likewise.
+	* expr.h (expr_build_unary): Remove declaration.
+	(expr_build_binary): Likewise.
+	* expr.c (expr_build_unary): Remove.
+	(expr_build_binary): Likewise.
+	* hash.h (hash_replace): Remove declaration.
+	(hash_delete): Likewise.
+	* hash.c (hash_replace): Remove.
+	(hash_delete): Likewise.
+	* bignum-copy.c (bignum_copy): Move from here ..
+	* config/tc-vax.c (bignum_copy): .. to here.
+	* bignum.h (LOG_TO_BASE_2_OF_10): Remove.
+	(bignum_copy): Remove extern declaration.
+	* sb.h (string_count): Remove extern declaration.
+	(sb_build, sb_add_buffer, sb_print, sb_print_at): Likewise.
+	(sb_name): Likewise.
+	* sb.c (dsize): Replace preprocessor macro with static int.
+	(string_count): Make static.
+	(sb_build, sb_add_buffer, sb_print, sb_print_at): Likewise.
+	(sb_name): Likewise.
+	* config/obj-coff.c (dim_index): Make static.
+	* config/tc-i386.c (GOT_symbol): Likewise.
+	(output_invalid_buf): Likewise.
+	* doc/internals.texi (Warning and error messages): Remove the
+	prototype for fprint_value.
+
+2005-04-27  Ben Elliston  <bje@au.ibm.com>
+
+	* link.cmd: Remove.
+
+2005-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-multi.h (FAKE_LABEL_NAME): Defined.
+
+	* read.c (pseudo_set): Disallow symbol set to common symbol.
+
+	PR 857
+	* write.c (write_object_file): Report common symbol name when
+	disallowing local symbol set to common symbol.
+	(adjust_reloc_syms): Disallow local symbol set to undefined
+	symbol.
+
+2005-04-25  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (macro_expand_body): Replace locals indicator parameters
+	with actual macro_entry. New local variables macro_line and err.
+	Don't return when encountering an error, just record the fact.
+	Detect local symbol name colliding with parameter. Track line number
+	inside of macro expansion.
+	(do_formals): Move local variable name to wider scope. Check
+	parameter of the same name doesn't already exist. In MRI mode, also
+	check it doesn't collide with the argument count pseudo-parameter).
+	(define_macro): Add file and line number parameters. Remove local
+	variable namestr. New local variable error. Initialize macro_entry
+	members file, line, and name. Don't return when encountering an
+	error, just record the fact. Use %s in some diagnostics for read.c
+	to insert the macro name. Free macro_entry on error.
+	(macro_expand): Pass macro_entry to macro_epand_body. Don't return
+	when encountering an error, just record the fact.
+	(expand_irp): Don't return when encountering an error, just record
+	the fact.
+	* macro.h (macro_struct): New members name, file, and line.
+	(define_macro): Add file and line number parameters.
+	* read.c (s_macro): Pass file and line to define_macro. Tag warning
+	regarding pseudo-op redefinition with the file/line that macro
+	definition started at.
+
+2005-04-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (LOOKAHEAD_ALIGNER): Delete macro.
+	(future_alignment_required): Remove ifdefs that use it.
+
+2005-04-22  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_get_build_instr_size): Remove.
+	(xg_is_narrow_insn, xg_expand_narrow): Remove.  Merge into...
+	(xg_is_single_relaxable_insn): ...here.  Add "targ" and "narrow_only"
+	parameters.
+	(xg_assembly_relax, xg_find_narrowest_format, relaxation_requirements,
+	convert_frag_narrow): Use new version of xg_is_single_relaxable_insn.
+
+2005-04-21  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-z8k.c (md_assemble): Fix buffer overrun in operand[]
+	array.
+
+2005-04-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-aout.h (S_IS_EXTERN): Removed.
+	* config/obj-bout.h (S_IS_EXTERN): Likewise.
+	* config/obj-coff.h (S_IS_EXTERN): Likewise.
+	* symbols.c (S_IS_EXTERN): Likewise.
+	* symbols.h (S_IS_EXTERN): Likewise.
+
+	* config/tc-alpha.c (tc_gen_reloc): Replace S_IS_EXTERN with
+	S_IS_EXTERNAL.
+	* config/tc-d10v.c (md_apply_fix3): Likewise.
+	* config/tc-ia64.c (ia64_fix_adjustable): Likewise.
+	* config/tc-iq2000.c (iq2000_fix_adjustable): Likewise.
+	* config/tc-m32r.c (m32r_fix_adjustable): Likewise.
+	* config/tc-mmix.c (mmix_adjust_symtab): Likewise.
+	* config/tc-sh64.c (shmedia_frob_file_before_adjust): Likewise.
+	(shmedia_md_convert_frag): Likewise.
+	* symbols.c (print_symbol_value_1): Likewise.
+	* write.c (write_object_file): Likewise.
+
+2005-04-20  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-xtensa.c (get_aligned_diff): Change type of
+	branch_align to offsetT so that its signedness matches that of
+	target_size.
+
+	* config/tc-mips.c (macro): Use sprintf_vma to convert a > 32 bit
+	number into a readable string.
+	(load_register): Likewise.
+
+2005-04-20  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-ia64.c (specify_resource): Initialize all of tmpl.
+
+2005-04-19  David S. Miller  <davem@davemloft.net>
+
+	* config/tc-sparc.c (md_assemble): If sparc_ip gives us a
+	NULL insn, exit early.  Remove now spurious NULL checks.
+	(sparc_ip): Use as_bad for unknown opcode errors, set *pinsn
+	to NULL and exit.
+
+2005-04-19  Jan Beulich  <jbeulich@novell.com>
+
+	* symbols.h (symbol_find_base): Remove prototype.
+	* symbols.c (save_symbol_name): Remove code section conditional upon
+	STRIP_UNDERSCORE.
+	(symbol_find): Remove.
+	(symbol_find_base): Rename to symbol_find.
+	* subsegs.c (section_symbol): Replace use of symbol_find_base with
+	symbol_find.
+	* config/obj-coff.c (tag_insert): Remove code section conditional
+	upon STRIP_UNDERSCORE.
+	(obj_coff_def): Likewise.
+	(obj_coff_endef): Replace use of symbol_find_base with symbol_find.
+	(coff_frob_symbol): Likewise.
+	(yank_symbols): Likewise.
+	(c_section_symbol): Likewise.
+	* config/obj-coff.h (DO_NOT_STRIP): Remove.
+	* config/tc-arm.c (symbol_locate): Remove code section conditional
+	upon STRIP_UNDERSCORE.
+	* config/tc-h8300.h (DO_NOT_STRIP): Remove.
+	* config/tc-h8500.h (DO_NOT_STRIP): Remove.
+	* config/tc-sh.h (DO_NOT_STRIP): Remove.
+	* config/tc-w65.h (DO_NOT_STRIP): Remove.
+	* config/tc-z8k.h (DO_NOT_STRIP): Remove.
+
+2005-04-19  Andreas Schwab  <schwab@suse.de>
+
+	* config/tc-ia64.c (md_assemble): Fix error message for wrong
+	access to application registers.
+
+2005-04-19  Jan Beulich  <jbeulich@novell.com>
+
+	* config/te-sysv32.h: Remove.
+	* Makefile.am (TARG_ENV_HFILES): Remove reference to
+	config/te-sysv32.h.
+	* Makefile.in (TARG_ENV_HFILES): Likewise.
+
+2005-04-19  Jan Beulich  <jbeulich@novell.com>
+
+	PR/847
+	* config/tc-ia64.c (ia64_canonicalize_symbol_name): Re-allow zero-
+	length symbols.
+
+2005-04-18  Mark Kettenis  <kettenis@gnu.org>
+
+	* config/tc-i386.c (md_begin): Allow hyphens in mnemonics.
+
+2005-04-18  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (normalize_constant_expr): Don't check for
+	HAVE_32BIT_GPRS.
+	(check_absolute_expr): Only call normalize_constant_expr() if
+	HAVE_32BIT_GPRS.
+	(mips_ip): Likewise.
+
+	* config/tc-mips.c (check_absolute_expr): Fix formatting.
+
+2005-04-18  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (free_token): New, freeing all the memory associated with a
+	macro.
+	(do_formals): Move initializers to ...
+	(define_macro): ... here.
+	(delete_macro): Convert passed in name to lower case. Warn when
+	purging macro that doesn't exist. Use hash_jam instead of hash_delete.
+
+2005-04-15  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (normalize_constant_expr): Fix formatting.
+
+2005-04-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/obj-elf.c (obj_elf_struct): New.
+	(elf_pseudo_table). Use it for .offset and .struct.
+
+2005-04-14  Bob Wilson  <bob.wilson@acm.org>
+	    Sterling Augustine  <sterling@tensilica.com>
+
+	* config/tc-xtensa.c (get_aligned_diff): Handle target_size larger
+	than the section alignment.
+
+2005-04-14  Bob Wilson  <bob.wilson@acm.org>
+	    H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-xtensa.h (struct xtensa_frag_type): Add lit_frchain field.
+	* config/tc-xtensa.c (xg_translate_sysreg_op,
+	xtensa_translate_old_userregs_ops,
+	xtensa_find_unaligned_branch_targets,
+	xtensa_find_unaligned_loops, xtensa_fix_close_loop_end_frags,
+	relax_frag_add_nop): Support 64-bit host.
+	(xtensa_mark_literal_pool_location, xtensa_move_literals): Use
+	tc_frag_data lit_frchain and lit_seg fields instead of fr_var.
+
+2005-04-14  Mark Kettenis  <kettenis@gnu.org>
+
+	* configure.tgt: Add support for OpenBSD/sparc ELF.
+
+	* configure.tgt: Set emulation for mips-*-openbsd*.
+	Remove broken mips-dec-openbsd* config.
+	* configure.in: Set default ABI for mips64-*-openbsd*.
+	* configure: Regenerate.
+
+2005-04-14  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (macro) [ldd_std]: Don't attempt the GP
+	optimization for constant addresses.
+
+2005-04-14  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (main): Move parse_args before symbol_begin and frag_init
+	so that the hash table size can be set before it is used.
+	* hash.c: Use an unsigned long type for the size of the hash
+	tables.
+	* hash.h (set_gas_hash_table_size): Update the prototype.
+
+2005-04-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (NO_WERROR): Define.  Use instead of -Wno-error.
+	* acinclude.m4: Include ../bfd/warning.m4.
+	* configure.in: Invoke AM_BINUTILS_WARNINGS.
+	* Makefile.in: Regenerate.
+	* configure: Regenerate.
+	* doc/Makefile.in: Regenerate.
+
+2005-04-13  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* config/tc-mips.c (IS_ZEXT_32BIT_NUM): New macro.
+	(normalize_address_expr): New function to sign-extend address
+	offsets that fit into 32 bits in 32-bit mode.
+	(macro_build_ldst_constoffset): Use normalize_address_expr()
+	instead of a handcoded sequence.
+	(load_register): Likewise.  Report oversized numbers in a useful
+	way.
+	(macro) [ld_st, ldd_std]: Reject all oversized offsets, not only
+	for constant addresses.  Report oversized numbers in a useful way.
+	(mips_ip): Use normalize_address_expr() for addresses.
+
+2005-04-12  Mark Kettenis  <kettenis@gnu.org>
+
+	* config/tc-i386.c (output_insn): Handle VIA PadLock instructions
+	similar to other instructions now that they're marked as ImmExt.
+
+2005-04-12  Nick Clifton  <nickc@redhat.com>
+
+	* hash.c (DEFAULT_SIZE): Delete.  Replace with:
+	(gas_hash_table_size): New static variable.
+	(set_gas_hash_table_size): New function:  Records a requested size
+	for the hash tables.
+	(get_gas_hash_table_size): New function: Return a prime number
+	near the requested size of the hash table.
+	(hash_new): Use get_gas_hash_table_size.
+	* hash.h: Add a prototype for set_gas_hash_table_size.
+	* as.c (show_usage): Add description of new switches: --hash-size
+	and --reduce-memory-overheads.
+	(option_values): Add OPTION_HASH_TABLE_SIZE and
+	OPTION_REDUCE_MEMORY_OVERHEADS.
+	(std_longpopts): Add entries for the new options.
+	(parse_args): Handle the new options.
+	* Makefile.am: Add a dependency of as.c on hash.h.
+	* Makefile.in: Regenerate.
+	* doc/as.texinfo: Document the new switches.
+	* NEWS: Mention the new switches.
+
+2005-04-12  Nick Clifton  <nickc@redhat.com>
+
+	PR gas/818
+	* config/tc-hppa.c (pre_defined_registers): Fix %farg[0-3]
+	synonyms.
+
+2005-04-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am: Run "make dep-am".
+	* Makefile.in: Regenerate.
+
+2005-04-11  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (check_t1_t2_reads_and_writes): Fix typo.
+
+2005-04-11  Mark Kettenis  <kettenis@gnu.org>
+
+	* configure.tgt (generic_target): Add support for OpenBSD/i386 ELF.
+
+2005-04-11  Jan Beulich  <jbeulich@novell.com>
+
+	* NEWS: Mention these changes and their effects.
+	* macro.c (get_token): Use is_name_beginner/is_part_of_name/
+	is_name_ender.
+	(check_macro): Likewise.
+	(buffer_and_nest): Likewise. Permit multiple labels. Don't discard
+	labels together with the closing pseudo-op.
+	(macro_expand_body): Adjust comment. Range-check input before use.
+	Adjust mis-spelled diagnostic. Use is_name_beginner.
+	* read.c (try_macro): New.
+	(read_a_source_file): New static variable last_eol. Don't list
+	macro expansion lines more than once. Call try_macro.
+	(s_macro): Set section of line_label to absolute instead of undefined.
+	* doc/as.texinfo: Add information on the caveats of these changes.
+
+2005-04-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (symbol_X_add_number): Change return type to "offsetT *".
+	* symbols.h (symbol_X_add_number): Update prototype.
+
+2005-04-10  Eric Christopher  <echristo@redhat.com>
+
+	* symbols.c (symbol_X_add_number): Fix warning.
+
+2005-04-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-m68k.c (md_begin): Support 64bit host.
+	(get_num): Support 64bit BFD on 32bit host.
+
+2005-04-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-mips.c (md_apply_fix3): Fix typos in BFD_RELOC_64.
+
+2005-04-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (assign_symbol): Remove const from parm.  Fix xcalloc
+	call.  Don't do the COFF hacks for multi-emulation gas.  Move
+	demand_empty_rest_of_line back to caller.
+	(s_set, equals): demand_empty_rest_of_line here.
+
+	PR gas/827
+	* as.h (rs_dummy): Define.
+	* symbols.c (symbol_X_add_number): New function.
+	* symbols.h (symbol_X_add_number): Declare.
+	* stabs.c (aout_process_stab): Tidy symbol frag setting.
+	* read.c (assign_symbol): New function, split out from s_set.
+	Use symbol_find_or_make.  Leave fr_type of dummy frag as rs_dummy.
+	Fix COFF hacks for multi-emulation gas.
+	(s_set): Call assign_symbol.  Remove "register" keyword.
+	(set_zero_frag): New function.
+	(pseudo_set): Always check for assignment to section syms.
+	Always set segment and frag of symbol, and likewise extern for
+	aout/bout.  Handle assignment of sym=sym+/-const specially.  Don't
+	special case exp.X_add_number non-zero for O_symbol expressions.
+	(equals): Use assign_symbol.
+
+2005-04-08  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xtensa_create_xproperty_segments): Skip
+	SEC_MERGE sections.
+
+2005-04-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-i386.c (tc_gen_reloc): Don't turn
+	BFD_RELOC_X86_64_32S into BFD_RELOC_32.
+
+2005-04-06  Nick Clifton  <nickc@redhat.com>
+
+	* po/rw.po: New translation: Kinyarwanda
+	* configure.in (ALL_LINGUAS): Add rw
+	* configure: Regenerate.
+
+2005-04-05  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (branch_align_power): New.
+	(xtensa_find_unaligned_branch_targets, get_aligned_diff,
+	future_alignment_required): Use branch_align_power to check section
+	alignment as well as xtensa_fetch_width when aligning branch targets.
+
+2005-04-05  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c: Warning fixes throughout.
+	(xtensa_fetch_width): Change to unsigned.
+	(assemble_nop, xtensa_find_unaligned_branch_targets,
+	xtensa_find_unaligned_loops, xg_assemble_vliw_tokens,
+	is_narrow_branch_guaranteed_in_range, xtensa_fix_close_loop_end_frags,
+	min_bytes_to_other_loop_end, unrelaxed_frag_min_size,
+	unrelaxed_frag_max_size, xtensa_fix_short_loop_frags,
+	count_insns_to_loop_end, unrelaxed_frag_min_insn_count,
+	get_text_align_max_fill_size, get_text_align_nop_count,
+	get_text_align_nth_nop_size, get_noop_aligned_address,
+	get_aligned_diff, convert_frag_align_next_opcode,
+	convert_frag_immed_finish_loop, xtensa_create_property_segments,
+	xtensa_create_xproperty_segments, xt_block_aligned_size): Clean up
+	types, avoiding size_t and using offsetT and addressT appropriately.
+	(get_text_align_power): Clean up types.  Avoid incorrect bound.
+	(get_text_align_fill_size): Clean up types.  Restructure for clarity.
+
+2005-04-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (start_unwind_section): Undo the change
+	of 2004-08-18.
+	(generate_unwind_image, dot_endp): Likewise.
+
+2005-04-01 David Mosberger  <davidm@hpl.hp.com>
+
+	* config/tc-ia64.c (ia64_handle_align): Move le_nop and
+	le_nop_stop arrays and initializers to file scope.
+	(md_begin): When generating code for anything other than
+	Itanium 1, use MMI instead of MFI NOP bundles as a filler.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (output_imm): Also set sign flag for 64-bit push
+	immediates.
+
+2005-04-01  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* NEWS: Mention [fdgh]_floating.
+	* config/atof-vax.c: Fix some whitespace.
+	* config/tc-vax.c (md_pseudo_table): Add "[fdgh]_floating".
+
+2005-04-01  Nick Clifton  <nickc@redhat.com>
+
+	* configure.in: Add a check for <unistd.h> providing a prototype
+	for getopt() which is compatible with the one in
+	include/getopt.h.  If so then define HAVE_DECL_GETOPT.
+	* configure: Regenerate.
+	* config.in (HAVE_DECL_GETOPT): Add.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (s_bss): Call obj_elf_section_change_hook.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (md_apply_fix3): Also handle BFD_RELOC_X86_64_32S.
+	(tc_gen_reloc): Handle BFD_RELOC_X86_64_32S in the default case.
+
+2005-03-30  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Rename
+	bfd_elf32_is_arm_mapping_symbol_name to bfd_is_arm_mapping_symbol_name.
+
+2005-03-30  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (mapping_state): Change documentation in function
+	comment to cross-reference spec instead. Change type of mapping symbols
+	to BSF_NO_TYPE.
+	(arm_adjust_symtab): Don't change type of mapping symbols here.
+
+2005-03-30  Aaron W. LaFramboise  <aaron98wiridge9@aaronwl.com>
+
+	* as.h [NEED_DECLARATION_FFS] (ffs): Prototype and alphabetize.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* configure.in: Check for ffs decl and alphabetize.
+
+2005-03-29  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Phil Blundell  <philb@gnu.org>
+
+	* config/tc-arm.c (arm_parse_reloc): Add TLS relocations.
+	(md_apply_fix3): Mark TLS symbols.
+	(tc_gen_reloc): Handle TLS relocations.
+	(arm_fix_adjustable): Ignore TLS relocations.
+	(s_arm_elf_cons): Support expressions after decorated symbols.
+
+2005-03-29  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (marked_pr_dependency): New bitmap, bit N indicates
+	whether personality routine index N has been output for this section.
+	(mapping_state): tc_segment_info_data now struct not enum.
+	(arm_elf_change_section): Likewise, and marked_pr_dependency is now
+	handled on section change.
+	(create_unwind_entry): Previous code to output dependency removed.
+	(s_arm_unwind_fnend): Output dependency if it hasn't been done already
+	for this section.
+	* config/tc-arm.h (TC_SEGMENT_INFO_TYPE): Redefined as struct
+	arm_segment_info_type.
+	(arm_segment_info_type): New struct.
+
+2005-03-28  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (do_align_targets): Update comment.
+	(xtensa_frob_label): Compute "freq" before possibly switching frags.
+	Insert a LOOP_END frag before every loop target, and do not overload
+	DESIRE_ALIGN_IF_TARGET frags with loop end information.
+	(xg_assemble_vliw_tokens): Use do_align_targets.
+	(xtensa_fix_target_frags): Remove code to convert a
+	DESIRE_ALIGN_IF_TARGET frag to a LOOP_END frag when there is a
+	negatable branch at the end of a loop.
+	(frag_can_negate_branch): Delete.
+
+2005-03-28  David Mosberger  <davidm@hpl.hp.com>
+	    H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 803
+	NEWS: Mention "-mtune=[itanium1|itanium2]".
+
+	* config/tc-ia64.c (md): Add tune.
+	(md_parse_option): Accepted "-mtune=[itanium1|itanium2]".
+	(md_show_usage): Add "-mtune=[itanium1|itanium2]".
+	(extra_goodness): Prefer M- and I-unit NOPs for itanium2. F and
+	B unit NOPs are discouraged for McKinley-derived cores.
+	(md_begin): Don't hardcode the "extra_goodness()" function in
+	the comment...
+	(ia64_init): Set md.tune to itanium2.
+
+	* doc/as.texinfo: Add -mtune=[itanium1|itanium2]".
+	* doc/c-ia64.texi: Likewise.
+
+2005-03-27  Ian Lance Taylor  <ian@airs.com>
+
+	* config/obj-coff.c (coff_frob_symbol): When crashing because of a
+	bad C_EFCN symbol, print its name.
+
+2005-03-25  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (use_longcalls): Delete.
+	(xg_symbolic_immeds_fit): Check for direct calls and return TRUE if
+	the use_longcalls flag is set.  Do this before checking the segment.
+	(xg_expand_assembly_insn): Rearrange to use new do_expand flag.  Never
+	expand direct calls at this point.
+	(xtensa_set_frag_assembly_state): Set use_longcalls flag.
+	(xtensa_find_unmarked_state_frags): Likewise.
+	(md_assemble): Do not disable longcalls by setting is_specific_opcode.
+	(xg_assemble_vliw_tokens): Switch frags when use_longcalls changes.
+	(convert_frag_immed): Remove unnecessary check of is_specific_opcode.
+	* config/tc-xtensa.h (xtensa_frag_type): Add use_longcalls flag.
+
+2005-03-25  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* config/tc-mmix.c, config/tc-mmix.h: Convert to ISO C90.
+
+2005-03-25  Hans-Peter Nilsson  <hp@axis.com>
+
+	* config/tc-cris.h: Convert to ISO C90.
+	* config/tc-cris.c: Ditto.
+	(md_estimate_size_before_relax): Remove obsolete comment for
+	parameter "segment_type".
+	(md_begin): Document reason for cast of hash_insert argument.
+	(md_atof): Correct type of parameter "type".
+
+2005-03-24  Nick Clifton  <nickc@redhat.com>
+
+	* write.h (bit_fix_new): Remove redundant prototype.
+	* config/atof-ieee.c: Convert to ISO-C90 and fix formatting.
+	* config/obj-aout.c: Convert to ISO-C90 and fix formatting.
+	* config/obj-aout.h: Convert to ISO-C90 and fix formatting.
+	* config/obj-bout.c: Convert to ISO-C90 and fix formatting.
+	* config/obj-bout.h: Convert to ISO-C90 and fix formatting.
+	* config/obj-ecoff.c: Convert to ISO-C90 and fix formatting.
+	* config/obj-ecoff.h: Convert to ISO-C90 and fix formatting.
+	* config/obj-som.c: Convert to ISO-C90 and fix formatting.
+	* config/obj-som.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-a29k.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-a29k.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-alpha.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-alpha.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-arc.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-arc.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-d10v.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-d10v.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-d30v.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-d30v.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-dlx.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-dlx.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-fr30.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-fr30.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-h8500.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-h8500.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-i370.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-i370.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-i960.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-ip2k.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-ip2k.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-m32r.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-m32r.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-m88k.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-m88k.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-mcore.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-mcore.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-mn10200.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-ns32k.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-ns32k.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-openrisc.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-openrisc.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-or32.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-or32.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-pdp11.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-pj.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-pj.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-tahoe.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-tic80.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-tic80.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-v850.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-v850.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-w65.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-w65.h: Convert to ISO-C90 and fix formatting.
+	* config/tc-xstormy16.c: Convert to ISO-C90 and fix formatting.
+	* config/tc-xstormy16.h: Convert to ISO-C90 and fix formatting.
+
+2005-03-23  Jim Blandy  <jimb@redhat.com>
+
+	* config/tc-arm.c (arm_adjust_symtab): Fetch elf_sym's binding
+	attributes properly.
+
+2005-03-23  Mike Frysinger  <vapier@gentoo.org>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* configure.tgt: Accept any C library to accompany a GNU Linux
+	implementation, not just the GNU C library.
+	* configure.in: Likewise.
+	* configure: Regenerate.
+
+2005-03-23  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-tic30.c: Convert to ISO C90 formatting.
+	* config/tc-tic30.h: Convert to ISO C90 formatting.
+	* config/tc-pdp11.c: Convert to ISO C90 formatting.
+	* config/atof-vax.c: Convert to ISO C90 formatting.
+
+2005-03-21  Maciej W. Rozycki  <macro@mips.com>
+
+	* config/tc-mips.c (mips_frob_file): Sort BFD_RELOC_MIPS16_LO16
+	relocations correctly as well.
+	(mips_fix_adjustable): Don't make BFD_RELOC_MIPS16_LO16
+	relocations in mergeable sections section-relative either.
+
+2005-03-21  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (md_apply_fix3): Recognize XTENSA_PLT relocations.
+
+2005-03-21  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-sh.c (sh_elf_final_processing): Fix compile time
+	warning by providing a prototype for sh_symbian_find_elf_flags.
+
+	* cgen.c (gas_cgen_parse_operand): Fix typo introduced by
+	previous delta.
+
+2005-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.tgt: Handle setting of bfd_gas for fmt=multi targets
+	along with other formats that set bfd_gas.  Remove unnecessary
+	setting of bfd_gas.  Delete strongarm cases in generic_target
+	switch.
+
+2005-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/780
+	* config/tc-m68k.c (TRUNC, SEXT): Define.
+	(issbyte, isubyte, issword, isuword, isbyte, isword): Use the above.
+	(m68k_ip): Truncate or sign extend expressions as appropriate.
+	(get_num): Likewise.
+	(md_apply_fix3): Use SEXT.
+
+2005-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* Makefile.am (OBJ_FORMAT_CFILES): Prune config/obj-vms.c.
+	(OBJ_FORMAT_HFILES): Prune config/obj-vms.h.
+	(obj-vms.o): Delete rule.
+	Run "make dep-am".
+	* Makefile.in: Regenerate.
+	* aclocal.m4: Regenerate.
+	* doc/Makefile.in: Regenerate.
+	* po/POTFILES.in: Regenerate.
+
+2005-03-18  C Jaiprakash  <cjaiprakash@noida.hcltech.com>
+
+	* config/tc-m68k.c (m68k_elf_final_processing): Set file specific
+	flag for coldfire v4e.
+
+2005-03-17  Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (xg_apply_tentative_value): Rename to
+	xg_apply_fix_value and return a value to indicate success.
+	(md_pcrel_from): Skip check of fx_done.  Return 0 if not PC-relative.
+	(xtensa_force_relocation): Remove checks for VTABLE relocs.
+	(xtensa_validate_fix_sub): New.
+	(xtensa_fix_adjustable): Remove check for external or weak symbols.
+	(tc_gen_reloc): Move code to handle difference of symbols and code to
+	apply tentative fix values to ...
+	(md_apply_fix3): ...here.  Enable standard overflow checks for simple
+	8, 16, and 32 bit relocations.  Apply fixes for slot-specific
+	relocations when linkrelax flag is not set.
+	* config/tc-xtensa.h (xtensa_validate_fix_sub): Add prototype.
+	(TC_FORCE_RELOCATION_SUB_SAME, TC_VALIDATE_FIX_SUB): Define.
+
+2005-03-17  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (i386_scale): Beautify error message.
+	(Intel syntax comments): Update.
+	(struct intel_parser_s): Add fields in_offset, in_bracket, and
+	next_operand.
+	(intel_e04_1, intel_e05_1, intel_e05_1, intel_e09_1, intel_e10_1):
+	Remove declarations.
+	(intel_bracket_expr): Declare.
+	(i386_intel_operand): Initialize new intel_parser fields. Wrap most
+	of the function body in a loop allowing to split an operand into two.
+	Replace calls to malloc and checks of it returning non-NULL with
+	calls to xmalloc/xstrdup.
+	(intel_expr): SHORT no longer handled here. Add comment indicating
+	comparison ops need implementation.
+	(intel_e04, intel_e04_1): Combine, replace recursion with loop.
+	Check right operand of - does not specify a register when parsing
+	the address of a memory reference.
+	(intel_e05, intel_e05_1): Combine, replace recursion with loop.
+	Check operands do not specify a register when parsing the address of
+	a memory reference.
+	(intel_e06, intel_e06_1): Likewise.
+	(intel_e09, intel_e09_1): Combine, replace recursion with loop. Also
+	handle SHORT as well as unary + and -. Don't accept : except for
+	segment overrides or in direct far jump/call insns.
+	(intel_brack_expr): New.
+	(intel_e10, intel_e10_1): Combine, replace recursion with loop. Use
+	intel_brack_expr.
+	(intel_e11): Replace chain of if/else-if by switch, alloing fall-
+	through in certain cases. Use intel_brack_expr. Add new diagnostics.
+	Allow symbolic constants as register scale value.
+	(intel_get_token): Replace call to malloc and check of return value
+	with call to xmalloc. Change handling for FLAT to match MASM's.
+	(intel_putback_token): Don't try to back up/free current token if
+	that is T_NIL.
+
+2005-03-16  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* configure.tgt: Set emulation for arm-*-eabi*.
+	* config/tc-arm.c (meabi_flags): Check EABI_DEFAULT.
+	* config/te-armeabi.h: New file.
+	* config/te-armlinuxeabi.h (EABI_DEFAULT): Define.
+	* config/te-symbian.h: Include "te-armeabi.h".
+
+2005-03-16  Nick Clifton  <nickc@redhat.com>
+
+	* cgen.c (gas_cgen_parse_operand): Copy opinfo parameter into a
+	local variable in case it is clobbered by the setjmp.
+
+2005-03-16  Nick Clifton  <nickc@redhat.com>
+	    Ben Elliston  <bje@au.ibm.com>
+
+	* configure.in (werror): New switch: Add -Werror to the
+	compiler command line.  Enabled by default.  Disable via
+	--disable-werror.
+	* configure: Regenerate.
+
+2005-03-16  Nick Clifton  <nickc@redhat.com>
+
+	* config/obj-coff.h: Convert to ISO C90 formatting.
+	* config/obj-coff.c: Convert to ISO C90 formatting.
+
+2005-03-15  Zack Weinberg  <zack@codesourcery.com>
+
+	* config/tc-arm.c (do_mla): Rename to do_mlas, take second
+	is_mls parameter; do not diagnose Rm==Rd when is_mls.
+	(do_mla, do_mls, five_bit_unsigned_immediate, bfci_lsb_and_width)
+	(do_bfc, do_bfi, do_bfx, do_rbit, do_mov16, do_ldsttv4): New functions.
+	(insns): Add ARMv6T2 instructions:
+	bfc bfi mls movw movt rbit sbfx ubfx ldrht ldrsht ldrsbt strht.
+	(arm_archs): Add V6T2 variants.
+
+2005-03-15  Nick Clifton  <nickc@redhat.com>
+
+	* NEWS: Add cutoff for changes in 2.16 release.
+
+2005-03-15  Jan Beulich  <jbeulich@novell.com>
+
+	* expr.c (operand): Merge handling of unary + into that for unary
+	-, !, and ~.
+
+2005-03-14  Eric Christopher  <echristo@redhat.com>
+
+	* config/tc-mips.c: Include dw2gencfi.h.
+	(mips_cfi_frame_initial_instructions): New.
+	* config/tc-mips.h (TARGET_USE_CFIPOP): Define.
+	(tc_cfi_frame_initial_instructions): Ditto.
+	(DWARF2_DEFAULT_RETURN_COLUMN): Ditto.
+	(DWARF2_CIE_DATA_ALIGNMENT): Ditto.
+	* Makefile.am: Update dependencies.
+	* Makefile.in: Regenerate.
+
+2005-03-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/es.po: Commit new Spanish translation.
+
+2005-03-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/tr.po: Commit new Turkish translation.
+
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+	* config/tc-arm.c (tinsns): Add ARMv6K instructions sev, wfe,
+	wfi, yield.
+
+2005-03-11  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config-gas.com: Mark vax-vms as obsolete.
+	* configure.in: Remove fmt=vms support.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* config/obj-vms.h, config/obj-vms.c, config/vms-conf.h: Remove.
+
+2005-03-10  Sterling Augustine  <sterling@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* config/tc-xtensa.c (finish_vinsn): Include the last instruction slot
+	when checking if xg_resolve_literals needs to be called.
+	* config/tc-xtensa.h: Fix spelling typo in a comment.
+
+2005-03-10  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-tic54x.h (tic54x_macro_info): Change parameter type.
+	* config/tc-tic54x.c (tic54x_macro_info): Likewise. Replace hand-
+	crafted structure declarations with the types from macro.h.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (s_cpsetup): Use '__gnu_local_gp' instead of '_gp'
+	for -mno-shared optimization.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (MAX_VR4130_NOPS, MAX_DELAY_NOPS): New macros.
+	(MAX_NOPS): Bump to 4.
+	(mips_fix_vr4130): New variable.
+	(nops_for_vr4130): New function.
+	(nops_for_insn): Use MAX_DELAY_NOPS rather than MAX_NOPS.  Use
+	nops_for_vr4130 if working around VR4130 errata.
+	(OPTION_FIX_VR4130, OPTION_NO_FIX_VR4130): New macros.
+	(md_longopts): Add -mfix-vr4130 and -mno-fix-vr4130.
+	(md_parse_option): Handle them.
+	(md_show_usage): Print them.
+	* doc/c-mips.texi: Document -mfix-vr4130 and -mno-fix-vr4130.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn): Remove cop_interlocks test from
+	branch delay code.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.h (mips_flush_pending_output): Delete.
+	(mips_emit_delays): Declare.
+	(md_flush_pending_output): Use mips_emit_delays.
+	* config/tc-mips.c (mips_no_prev_insn): Remove parameter; always forget
+	the previous instructions.
+	(md_begin, append_insn, md_parse_option): Update callers.
+	(mips_emit_delay): Remove parameter.  Move INSNS != 0 code to
+	start_noreorder.
+	(mips_align, s_change_sec, s_cons, s_float_cons, s_gpword)
+	(s_gpdword): Update callers.
+	(start_noreorder, end_noreorder): New functions.
+	(macro, macro2, mips16_macro, s_mipsset): Use them instead of
+	manipulating mips_opts or prev_nop_frag directly.
+	(mips_flush_pending_output): Delete.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (mips_move_labels): New function, taken from...
+	(append_insn, mips_emit_delays): ...here.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (MAX_NOPS): New macro.
+	(history): Resize to 1 + MAX_NOPS.
+	(fix_vr4120_class): New enumeration.
+	(vr4120_conflicts): New variable.
+	(init_vr4120_conflicts): New function.
+	(md_begin): Call it.
+	(insn_uses_reg): Constify first argument.
+	(classify_vr4120_insn, insns_between, nops_for_insn, nops_for_sequence)
+	(nops_for_insn_or_target): New functions.
+	(append_insn): Use the new nops_for_* functions instead of inline
+	delay checks.  Generalize prev_nop_frag handling to handle an
+	arbitrary history length.  Insert nops into the history buffer
+	once the number of nops in prev_nop_frag is fixed.
+	(emit_delays): Use nops_for_insn instead of inline delay checks.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (append_insn): Remove now-redundant nops != 0
+	check from branch delay code.  Remove unnecessary check for branches.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (dummy_opcode): Delete.
+	(nop_insn, mips16_nop_insn): New variables.
+	(NOP_INSN): New macro.
+	(insn_length, create_insn, install_insn, move_insn, add_fixed_insn)
+	(add_relaxed_insn, insert_into_history, emit_nop): New functions.
+	(md_begin): Initialize nop_insn and mips16_nop_insn.
+	(append_insn): Use the new emit_nop function to add nops, recording
+	them in the history buffer.  Use add_fixed_insn or add_relaxed_insn
+	to reserve room for the instruction and install_insn to install the
+	final form.  Use insert_into_history to record the instruction in
+	the history buffer.  Use move_insn to do delay slot filling.
+	(mips_emit_delays): Use add_fixed_insn instead of the emit_nop macro.
+	(macro_build, mips16_macro_build, macro_build_lui, mips_ip)
+	(mips16_ip): Use create_insn to initialize mips_cl_insns.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (INSERT_BITS, EXTRACT_BITS, INSERT_OPERAND)
+	(EXTRACT_OPERAND, MIPS16_INSERT_OPERAND, MIPS16_EXTRACT_OPERAND): New.
+	(insn_uses_reg, reg_needs_delay, append_insn, macro_build)
+	(mips16_macro_build, macro_build_lui, mips16_macro, mips_ip)
+	(mips16_ip): Use the new macros instead of explicit masks and shifts.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (mips_cl_insn): Replace the valid_p, delay_slot_p
+	and extended_p fields with a single fixed_p field.
+	(append_insn, mips_no_prev_insn): Adjust accordingly.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (mips_cl_insn): Replace reloc_type array with
+	a single mips16_absolute_jump_p bit.
+	(append_insn): Adjust accordingly.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.h (mips_cl_insn): Move definition to...
+	* config/tc-mips.c (mips_cl_insn): ...here.  Add new fields:
+	frag, where, fixp, reloc_type, valid_p, noreorder_p, delay_slot_p
+	and extended_p.
+	(history): New variable.
+	(prev_insn, prev_prev_insn, prev_insn_valid, prev_insn_frag)
+	(prev_insn_where, prev_insn_reloc_type, prev_insn_fixp)
+	(prev_insn_is_delay_slot, prev_insn_unreordered, prev_insn_extended)
+	(prev_prev_insn_unreordered): Delete.
+	(reg_needs_delay, append_insn, mips_no_prev_insn, mips_emit_delays)
+	(macro_start): Replace uses of prev_insn* with the equivalent history[]
+	field.
+
+2005-03-08  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* doc/Makefile.am: Update as.info dependencies.
+	* aclocal.m4, Makefile.in, doc/Makefile.in: Regenerated.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* doc/as.texinfo: Add sentence to indicate redefining a macro is an
+	error, and point to .purgem documentation if someone really needs
+	re-definitions.
+	* NEWS: Mention macro redefinition is now an error.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Track last slot user insn was
+	emitted to. Add more precise diagnostics for non-fitting insns based
+	on that. Eliminate now superfluous special casing of MLX. Clear out
+	slot information when dropping an insn.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_section_name): Rename to...
+	(cross_section): In addition to separating the name from the rest of
+	the arguments, also carry out the operation.
+	(dot_xdata): Use cross_section.
+	(dot_float_cons): Likewise.
+	(dot_xstringer): Likewise.
+	(dot_xdata_ua): Likewise.
+	(dot_float_cons_ua): Likewise. Pass float_cons, not stmt_float_cons.
+
+2005-03-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* po/gas.pot: Regenerate.
+
+2005-03-04  David Daney  <ddaney@avtrex.com>
+
+	* config/tc-mips.c (macro_build_lui): Use '__gnu_local_gp'
+	instead of '_gp' for -mno-shared optimization.
+	(s_cpload): Ditto.
+	(s_abicalls): Document it in the comment.
+	(md_show_usage): Document the -mno-shared option.
+
+2005-03-04  Richard Sandiford  <rsandifo@redhat.com>
+
+	* config/tc-mips.c (mips_set_options): Add sym32 field.
+	(mips_opts): Initialize it.
+	(HAVE_32BIT_ADDRESSES): Set to true if pointers are 32 bits wide.
+	(HAVE_64BIT_ADDRESSES): Redefine as !HAVE_32BIT_ADDRESSES.
+	(HAVE_32BIT_SYMBOLS, HAVE_64BIT_SYMBOLS): New macros.
+	(load_address): Use HAVE_64BIT_SYMBOLS instead of HAVE_64BIT_ADDRESSES
+	when deciding whether to use a symbolic %highest/%higher expansion.
+	(macro): Likewise.  Remove o64/n32 linux hack.  Always use
+	ADDRESS_ADD*_INSN for address addition in the expansion of "dla"
+	and "la".  Handle constants separately from symbolic expressions in
+	the "ld_st:" case, using 64-bit arithmetic if HAVE_64BIT_ADDRESSES
+	and using load_register to load the high part of the address.
+	(OPTION_MSYM32, OPTION_NO_MSYM32): New macros.
+	(OPTION_ELF_BASE): Bump by 2.
+	(md_longopts): Add entries for -msym32 and -mno-sym32.
+	(md_parse_option): Handle them.
+	(usage): Document them.
+	(s_mipsset): Handle ".set sym32" and ".set nosym32".
+	(s_cpload, s_cpsetup): Use HAVE_64BIT_SYMBOLS instead of
+	HAVE_64BIT_ADDRESSES to detect 64-bit values of "_gp".
+	* doc/c-mips.texi: Document ".set sym32", ".set nosym32",
+	-msym32 and -mno-sym32.
+
+2005-03-03  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (load_address): Implement GP optimization
+	for 64bit address space non-PIC. Fix formatting.
+	(macro): Likewise. Simplify code.
+	(md_parse_option): Don't bail out if -G 0 is set for PIC code.
+	(mips_after_parse_args): Simplify code.
+
+2005-03-03  Nick Clifton  <nickc@redhat.com>
+
+	* expr.c (operand): Remove redundant code enclosed by #ifdef
+	RELAX_PAREN_GROUPING....#endif.
+
+	* config/tc-mn10200.c (tc_gen_reloc): Handle the case where the
+	reloc is the difference of two symbols defined in the same
+	section.
+
+	* config/tc-iq2000.c (line_comment_chars): Include the # character
+	as otherwise this breaks #APP/#NO_APP processing.
+
+2005-03-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* config/tc-arc.c(md_assemble): Remove dead code for handling
+	immediate indexing of ld and st .
+
+2005-03-02  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+
+	* config/tc-mips.c (percent_op): Add %tlsgd, %tlsldm, %dtprel_hi,
+	%dtprel_lo, %tprel_hi, %tprel_lo, and %gottprel.
+	(parse_relocation): Check for a word break after a relocation
+	operator.
+	(md_apply_fix3): Handle TLS relocations, and mark thread-local
+	symbols.
+
+2005-03-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-ppc.c (ppc_fix_adjustable <ELF>): Remove bogus checks.
+
+2005-03-02  Jan Beulich  <jbeulich@novell.com>
+
+	* as.c (main): Use unlink_if_ordinary instead of unlink.
+	* messages.c (as_fatal): Likewise.
+
+2005-03-02  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (build_modrm_byte): Add lock prefix for cr8...15
+	accesses.
+	(parse_register): Allow cr8...15 in all modes.
+
+2005-03-02  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-i386.c (intel_e11): If not followed by T_PTR, treat T_BYTE
+	etc. like normal symbol references (T_ID).
+
+2005-03-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* symbols.c (fb_label_name): Fix silly thinko in last change.
+
+2005-03-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* expr.c (integer_constant): Remove TARGET_WORD_SIZE hack.
+	* config/tc-m68k.h (TARGET_WORD_SIZE): Delete.
+
+	* symbols.c (fb_label_name): Allow an augend of 2 for mmix.
+
+2005-03-01  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	PR gas/708
+	* config/tc-arc.c (md_assemble): Initialize suffix for extension
+	suffixes also.
+
+2005-03-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/obj-coff.c (fixup_segment): Delete sy_mri_common assertion.
+
+	* as.h (assert): Warning fix.
+	* expr.c (expr): Correct assertion.
+	* read.c (s_comm_internal): Remove assertion.
+	* write.c (relax_segment): Enable vma assertion only for BFD_ASSEMBLER.
+	(fixup_segment): Remove assertion.
+	* config/tc-dlx.c (machine_ip): Remove untrue assertions.
+	(md_apply_fix3): Likewise.
+	* config/tc-i370.c (md_begin): Correct assertion.
+	(i370_macro): Warning fix for assertion.
+
+2005-03-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* configure.in (AC_C_BIGENDIAN): Invoke.
+	* configure: Regenerate.
+	* write.c (write_object_file <!BFD_ASSEMBLER>): Don't use sizeof
+	host variable to set string header size.
+	* config/obj-aout.c (obj_header_append): Don't use host structs.
+	(obj_symbol_to_chars): Likewise.
+	(obj_emit_strings): Likewise.  Use the passed in output pointer.
+	* config/obj-aout.h (H_GET_FILE_SIZE): Include H_GET_LINENO_SIZE.
+	* config/obj-bout.c (obj_emit_relocations): Use md_reloc_size,
+	not sizeof host struct.
+	(obj_header_append, obj_symbol_to_chars): Don't use host structs.
+	(obj_emit_strings): Likewise.
+	* config/obj-bout.h (EXEC_BYTES_SIZE): Define.
+	(N_TXTOFF, H_GET_FILE_SIZE, H_GET_HEADER_SIZE): Use instead of
+	sizeof host struct.
+	(H_SET_SYMBOL_TABLE_SIZE): Hard code sym size rather than using
+	sizeof host struct.
+	(host_number_to_chars): Define.
+	* config/obj-hp300.c (hp300_header_append): Don't use sizeof
+	host internal struct to set header sizes.
+	* config/tc-i960.c (md_number_to_field): Warning fix.
+	(md_ri_to_chars): Use host byte order.
+	(get_cdisp, md_apply_fix3): Warning fix.
+	* config/tc-m68k.c (md_assemble): Don't use sizeof host short.
+
+2005-02-28  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* doc/c-arc.texi: Update documentation about ARC's extension
+	instructions.
+
+2005-02-27  Svein E. Seldal  <svein@dev.seldal.com>
+
+	* config/tc-tic4x.c (tic4x_gen_to_words): Changed mail
+	address for myself.
+
+2005-02-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* cgen.c: Warning fixes.
+	* config/tc-arc.c: Likewise.
+	* config/tc-arm.c: Likewise.
+	* config/tc-avr.c: Likewise.
+	* config/tc-d10v.c: Likewise.
+	* config/tc-d30v.c: Likewise.
+	* config/tc-frv.c: Likewise.
+	* config/tc-frv.h: Likewise.
+	* config/tc-h8300.c: Likewise.
+	* config/tc-h8500.c: Likewise.
+	* config/tc-i370.c: Likewise.
+	* config/tc-i960.c: Likewise.
+	* config/tc-ia64.c: Likewise.
+	* config/tc-ip2k.c: Likewise.
+	* config/tc-m68hc11.c: Likewise.
+	* config/tc-maxq.c: Likewise.
+	* config/tc-mcore.c: Likewise.
+	* config/tc-mips.c: Likewise.
+	* config/tc-msp430.c: Likewise.
+	* config/tc-pj.c: Likewise.
+	* config/tc-ppc.c: Likewise.
+	* config/tc-ppc.h: Likewise.
+	* config/tc-s390.c: Likewise.
+	* config/tc-sh.c: Likewise.
+	* config/tc-sh64.c: Likewise.
+	* config/tc-tic4x.c: Likewise.
+	* config/tc-tic80.c: Likewise.
+	* config/tc-v850.c: Likewise.
+	* config/tc-vax.c: Likewise.
+	* config/tc-w65.c: Likewise.
+	* config/tc-xstormy16.c: Likewise.
+	* config/tc-z8k.c: Likewise.
+
+2005-02-22  Catherine Moore  <clm@cm00re.com>
+
+	* read.c (read_a_source_file): Reinstate TC_EQUAL_IN_INSN test.
+	* doc/internals.texi (TC_EQUAL_IN_INSN): Reinstate.
+
+2005-02-22  Eric Christopher  <echristo@redhat.com>
+
+	* config/tc-mips.c (struct proc): Change isym to
+	func_sym. New member func_end_sym.
+	(s_mips_ent): Update.
+	(s_mips_end): Ditto. Add code to compute function size.
+
+2005-02-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c: Warning fixes.
+	* config/obj-elf.c: Likewise.
+
+2005-02-22  Maciej W. Rozycki  <macro@mips.com>
+
+	* config/tc-mips.c (append_insn): Call dwarf2_emit_insn() before
+	emitting insn.
+
+2005-02-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/obj-coff.c (obj_coff_section): Replace SEC_SHARED with
+	SEC_COFF_SHARED.
+
+	* config/tc-tic54x.c (tic54x_bss): Replace SEC_BLOCK with
+	SEC_TIC54X_BLOCK.
+	(demand_empty_rest_of_line): Likewise.
+	(tic54x_sblock): Likewise.
+	(tic54x_clink): Replace with SEC_CLINK with SEC_TIC54X_CLINK.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* read.c (address_bytes): New function.
+	(TC_ADDRESS_BYTES): Default for BSD_ASSEMBLER to address_bytes.
+	(potable): Add "dc.a".
+	(cons_worker): Handle "dc.a".
+	* doc/internals.texi (TC_ADDRESS_BYTES): Document.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* input-file.c (input_file_open): Rearrange to avoid warning.
+
+2005-02-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-hppa.h (TC_EQUAL_IN_INSN): Delete.
+	* read.c (read_a_source_file): Remove TC_EQUAL_IN_INSN test.
+	* doc/internals.texi (TC_EQUAL_IN_INSN): Delete.
+
+2005-02-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (macro_build_ldst_constoffset): Fail on $at
+	uses after .set noat.
+	(load_address): Likewise.
+	(macro): Likewise. Don't try to avoid $at use by sacrificing
+	the target register before it is stored, it won't work.
+
+2005-02-17  James E Wilson  <wilson@specifixinc.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Stop filling a bundle if we
+	see an instruction that specifies a template.
+
+2005-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/tc-openrisc.c (openrisc_relax_frag): Delete unused function.
+	* config/tc-sparc.c (sparc_ip): Make op_exp static to silence warnings.
+	* config/tc-tic80.c (build_insn): Init insn[1] to silence warning.
+
+2005-02-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* NEWS: Mention "-mhint.b=[ok|warning|error]".
+
+	* config/tc-ia64.c (md): Add hint_b.
+	(emit_one_bundle): Handle md.hint_b for "hint".
+	(md_parse_option): Accepted "-mhint.b=[ok|warning|error]".
+	(md_show_usage): Add "-mhint.b=[ok|warning|error]".
+	(ia64_init): Set md.hint_b to error.
+	(md_assemble): Handle md.hint_b for "hint.b".
+
+	* doc/as.texinfo: Add "-mhint.b=[ok|warning|error]".
+	* doc/c-ia64.texi: Likewise.
+
+2005-02-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* tc.h (struct relax_type, relax_typeS): Move from here..
+	* as.h: ..to here.  Make rlx_forward and rlx_backward an offsetT.
+	* ecoff.c (ecoff_new_file): Add appfile param.
+	* ecoff.h (ecoff_new_file): Likewise.
+	* itbl-lex.h: New file.
+	* itbl-lex.l: Include itbl-lex.h.
+	* itbl-parse.y: Likewise.
+	(insntbl_line, yyparse, yylex): Move to itbl-lex.h.
+	* read.c (s_app_file_string): Mark appfile possibly unused.
+	* subsegs.c (seg_not_empty_p): Make sec possibly unused.
+	* subsegs.h (struct seg_info_trash): Delete.
+	(seg_info): Use segment_info_type instead.
+	* config/obj-coff.c (struct filename_list): Make filename const char *.
+	* config/obj-ecoff.h (obj_app_file): Pass app to ecoff_new_file.
+	* config/obj-elf.c (elf_file_symbol): Similarly.
+	* config/tc-a29k.c (md_apply_fix3): Make val a valueT.  Don't use
+	signed right shift.
+	* config/tc-arc.c (md_operand): Warning fix.
+	* config/tc-arm.c (arm_parse_reloc): Only define when OBJ_ELF.
+	(md_begin): Rearrange #if defined OBJ_COFF || defined OBJ_ELF.
+	* config/tc-cris.h (TC_IMPLICIT_LCOMM_ALIGNMENT): Use do while.
+	* config/tc-frv.c (frv_force_relocation): Warning fix.
+	* config/tc-m68k.c (md_parse_option): Delete unused var.
+	* config/tc-mcore.c (mylog2): Rename from log2 throughout.
+	* config/tc-sparc.c: Likewise.
+	(s_common): Warning fix.
+	* config/tc-mips.c (append_insn): Use unsigned long long expressions.
+	* config/tc-mmix.c (PUSHJSTUB_MAX, PUSHJSTUB_MIN): Define from
+	addressT.
+	* config/tc-s390.c (s390_insn): Delete test of unsigned >= 0.
+	* config/tc-sh.c (sh_cfi_frame_initial_instructions,
+	sh_regname_to_dw2regnum): Only define for OBJ_ELF.
+	* config/tc-tic4x.c (tic4x_insert_reg): Use ISLOWER.
+	(tic4x_do_align): Use TIC_NOP_OPCODE.
+	* config/tc-tic4x.h (TIC_NOP_OPCODE): Rename from NOP_OPCODE.
+	* config/tc-vax.c: Include netinet/in.h.
+	(tc_headers_hook): Formatting.
+	* config/tc-xstormy16.c (md_pcrel_from_section): Correct parens.
+
+2005-02-17  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (ia64_parse_name): Don't advance 'name' when
+	parsing inN, locN, outN. Set 'idx' to offset register number starts
+	at. Don't handle numbers with leading zeroes or beyond 95. Remove
+	pointless cast.
+
+2005-02-16  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* config/tc-mips.c (load_address): Fix formatting.
+	(macro): Don't use AT if .set noat is in effect. Fix formatting.
+	Catch macros which are unexpandable without AT. Remove duplicate
+	zeroing of used_at.
+	(macro2): Remove duplicate zeroing of used_at.
+
+2005-02-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* dw2gencfi.c (output_cie, output_fde): Use DW_CFA_nop rather
+	than zero.
+
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* config/tc-mips.c (reloc_needs_lo_p): Handle
+	BFD_RELOC_MIPS16_HI16_S.
+	(fixup_has_matching_lo_p): Handle BFD_RELOC_MIPS16_LO16.
+	(append_insn): Add BFD_RELOC_MIPS16_GPREL, BFD_RELOC_MIPS16_HI16_S
+	and BFD_RELOC_MIPS16_LO16 to relocs to suppress overflow
+	complaints on.
+	(mips16_ip): Resolve BFD_RELOC_MIPS16_HI16_S,
+	BFD_RELOC_MIPS16_HI16 and BFD_RELOC_MIPS16_LO16 for constants.
+	Call my_getSmallExpression() to parse percent operators.
+	(percent_op_match, mips_percent_op): Separate definitions.
+	(mips16_percent_op): Define percent operators for the MIPS16 mode.
+	(parse_relocation): Handle the MIPS16 mode using
+	mips16_percent_op.
+	(md_apply_fix3): Handle BFD_RELOC_MIPS16_HI16,
+	BFD_RELOC_MIPS16_HI16_S and BFD_RELOC_MIPS16_LO16.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (md_apply_fix3): Call ia64_gen_real_reloc_type
+	instead of explicitly dealing with the translation; exclude
+	relocations that are already pcrel, however.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c: Include limits.h (if available).
+	(gr_values[0]): Set path to INT_MAX.
+	(dot_reg_val): Don't allow changing value of r0. Limit range of
+	general registers at r127.
+	(specify_resource): Default resource index is -1. Don't set resource
+	index (in case IA64_RS_RSE) without setting the specific flag.
+	(note_register_values): Check operand is O_constant before tracking
+	input value of moves. Add tracking for dep.z with constant inputs.
+	(print_dependency): Resource index of specific resource may be zero.
+	(check_dependencies): Likewise.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_operands): New local variables reg1, reg2,
+	reg_class. Check operands and emit diagnostics for illegal use of
+	registers.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (ia64_gen_real_reloc_type): Define and initialize
+	new variables type, suffix, and width. Handle
+	BFD_RELOC_IA64_DIR(32|64)[LM]SB in FUNC_LT_FPTR_RELATIVE case.
+	Handle BFD_RELOC_IA64_DIR64[LM]SB in FUNC_TP_RELATIVE case. Add
+	FUNC_DTP_MODULE case. Handle BFD_RELOC_IA64_DIR32[LM]SB in
+	FUNC_DTP_RELATIVE case. Return incoming relocation type if
+	BFD_RELOC_IA64_IPLT[LM]SB in FUNC_IPLT_RELOC case. Generate warning
+	if unable to translate relocation type, using the new variables.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.h (ia64_symbol_chars): Declare.
+	(ty_symbol_chars): Define.
+	* config/tc-ia64.c (ia64_symbol_chars): Define.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (ia64_parse_name): Only update next character if
+	input_line_pointer was advanced.
+
+2005-02-14  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* config/tc-sh.c (md_apply_fix3): Add parentheses around &
+	within |.
+
+2005-02-13  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (md_parse_option): Handle -xnone and -xdebugn.
+	(md_show_usage): Add -xnone, -xdebugn, and -xdebugx. Relocate default
+	indicator.
+	(ia64_init): Set md.detect_dv.
+	(ia64_start_line): New static variable warned. Warn only once when
+	encountering explicit stops in automatic mode.
+	* doc/c-ia64.texi: Describe -xnone, -xdebugn, and -xdebugx.
+	* NEWS: Mention new default mode.
+
+2005-02-13  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_rot): Add comment that name strings should
+	be freed when wiping out previous state. Canonicalize names before
+	use. Free name string when detecting redefinition.
+	(dot_pred_rel): Call generic expression parser to process arguments.
+	Handle O_register case for individual predicates and O_subtract for
+	ranges.
+	(ia64_parse_name): Canonicalize name before looking it up in dynamic
+	register hash.
+	(ia64_canonicalize_symbol_name): Strip off all trailing # characters.
+	Warn if multiple found, issue error if resulting symbol name has zero
+	length.
+	(dot_alias): Canonicalize name before use.
+
+2005-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (unwind_diagnostic): Return -1 for warning
+	and 0 for error.
+	(in_procedure): Return -1 for warning.
+	(in_prologue): Likewise.
+	(in_body): Likewise.
+
+2005-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/tc-ia64.c (dot_xdata): Undo the last change.
+	(dot_float_cons): Likewise.
+	(dot_xstringer): Likewise.
+	(dot_xdata_ua): Likewise.
+	(dot_float_cons_ua): Likewise.
+
+2005-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* NEWS: Mention "-munwind-check=[warning|error]".
+
+	* config/tc-ia64.c (md): Add unwind_check.
+	(unwind_diagnostic): New.
+	(in_procedure): Call unwind_diagnostic when a directive isn't
+	in procedure.
+	(in_prologue): Call unwind_diagnostic when a directive isn't in
+	prologue.
+	(in_body): Call unwind_diagnostic when a directive isn't in
+	body region.
+	(dot_endp): Set md.unwind_check to error before calling
+	in_procedure and restore it after. When the name is missing or
+	couldn't be found, use the one from the last .proc if
+	md.unwind_check isn't error. Warn if md.unwind_check is
+	warning.
+	(md_parse_option): Handle "-munwind-check=[warning|error]".
+	(md_show_usage): Add "-munwind-check=[warning|error]".
+	(ia64_init): Set md.unwind_check to warning.
+
+	* doc/as.texinfo: Add "-munwind-check=[none|warning|error]".
+	* doc/c-ia64.texi: Likewise.
+
+2005-02-11  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.h (LEX_AT): Include LEX_BEGIN_NAME.
+	(LEX_QM): Likewise.
+	(ia64_parse_name): New third parameter.
+	(md_parse_name): Pass third argument.
+	* config/tc-ia64.c (pseudo_func): Placeholders use NULL as name.
+	(md_operand): Handling of '@'-prefixed symbols moved from here...
+	(ia64_parse_name): ...to here.
+
+2005-02-11  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (md): Remove last_groups and group_idx.
+	(errata_nop_necessary_p): Remove declaraction and definition.
+	(emit_one_bundle): Don't call errata_nop_necessary_p. Don't
+	update md.group_idx. Don't reset md.last_groups.
+
+2005-02-11  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_section_name): Handle non-quoted first
+	argument.
+	(dot_xdata): Free section name after use.
+	(dot_float_cons): Likewise.
+	(dot_xstringer): Likewise.
+	(dot_xdata_ua): Likewise.
+	(dot_float_cons_ua): Likewise.
+	(md_pseudo_table): Add xdata16 and xdata16.ua.
+
+2005-02-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* doc/all.texi: Add IA64.
+	* doc/as.texinfo: Likewise.
+
+	* doc/c-ia64.texi: Fix typos.
+
+2005-02-10  Julian Brown  <julian@codesourcery.com>
+
+	* config/tc-arm.c (do_t_ldmstm): Change BFD_RELOC_NONE to
+	BFD_RELOC_UNUSED.
+	(do_t_push_pop): Likewise.
+	(md_assemble): Likewise.
+	(md_apply_fix3): Handle BFD_RELOC_NONE correctly, make
+	BFD_RELOC_UNUSED same as previous meaning of BFD_RELOC_NONE.
+	(create_unwind_entry): Output dependency on the required personality
+	routines.
+
+2005-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* as.h (seg_not_empty_p): Return int, not bfd_boolean.
+	* subsegs.c (seg_not_empty_p): Likewise.
+
+2005-02-07  Inderpreet Singh <inderpreetb@noida.hcltech.com>
+
+	* config/tc-maxq.c (md_estimate_size_before_relax): Correct the
+	relative jump calculation.
+	<md_convert_frag) : Likewise.
+	<output_disp): Likewise.
+
+2005-02-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* write.c (write_object_file): Recognize warning-symbol construct
+	and skip object- and target- handling for the second symbol.
+
+2005-02-02  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (dot_pred_rel): Update comment. Handle @-prefixed
+	designators along with quoted ones. Free copy of quoted designator
+	when done.
+
+2005-02-01  Ben Elliston  <bje@au.ibm.com>
+
+	* config/atof-ieee.c, config/obj-coff.c, config/obj-elf.c,
+	config/obj-ieee.c, config/obj-som.c, config/obj-vms.c,
+	config/tc-a29k.c, config/tc-alpha.c, config/tc-arc.c,
+	config/tc-arm.c, config/tc-d30v.c, config/tc-dlx.c,
+	config/tc-fr30.c, config/tc-h8300.c, config/tc-h8500.c,
+	config/tc-i370.c, config/tc-i386.c, config/tc-i960.c,
+	config/tc-ia64.c, config/tc-m32r.c, config/tc-m32r.h,
+	config/tc-m68hc11.c, config/tc-m68hc11.h, config/tc-mips.c,
+	config/tc-mn10200.c, config/tc-msp430.c, config/tc-ns32k.c,
+	config/tc-openrisc.c, config/tc-or32.c, config/tc-pdp11.c,
+	config/tc-pj.c, config/tc-sparc.h, config/tc-tic54x.c,
+	config/tc-tic80.c, config/tc-v850.c, config/tc-w65.c,
+	config/tc-xtensa.c, config/tc-z8k.c, config/xtensa-relax.c: Remove
+	#if 0'd code throughout.
+
+2005-01-31  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (parse_args): Bump copyright date reported by --version to
+	2005.
+
+2005-01-31  Nick Clifton  <nickc@redhat.com>
+
+	* configure.tgt: Remove obsolete targets m68k-lynxos, sparc-lynxos
+	and vax-vms.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (buffer_and_nest): Allow 'from' being NULL; handle anything
+	that can end with .endr in that case. Make requiring/permitting
+	pseudo-ops without leading dot closer to the logic in read.c serving
+	the same purpose.
+	(expand_irp): Don't pass a mnemonic to buffer_and_nest as it will be
+	ignored.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* macro.c (do_formals): Adjust to no longer accept empty parameter
+	names.
+	(define_macro): Adjust to no longer accept empty macro name, garbage
+	following the parameters, or macros that were previously defined.
+	* read.c (s_bad_end): Declare.
+	(potable): Add endm. Handler for endr and endm is s_bad_end.
+	(s_bad_end): Rename from s_bad_endr. Adjust to handle both .endm
+	and .endr.
+	* read.h (s_bad_endr): Remove.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_operands): Parse all specified operands,
+	immediately discarding (but counting) those exceeding the maximum
+	possible amount. Track whether output and input operand counts ever
+	matched, and use this to better indicate which of the operands/
+	operand types was wrong; specifically don't default to pointing to
+	the first operand.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (unwind): Remove proc_end (now an automatic
+	variable in dot_endp). Add body and insn. Make prologue,
+	prologue_mask, body, and insn bitfields.
+	(fixup_unw_records): Remove spurious new-lines from end of diagnostic
+	messages.
+	(in_procedure, in_prologue, in_body): New.
+	(dot_fframe, dot_vframe, dot_vframesp, dot_vframepsp, dot_save,
+	dot_restore, dot_restorereg, dot_restorereg_p, dot_handlerdata,
+	dot_unwentry, dot_altrp, dot_savemem, dot_saveg, dot_savef, dot_saveb,
+	dot_savegf, dot_spill, dot_spillreg, dot_spillmem, dot_spillreg_p,
+	dot_spillmem_p, dot_label_state, dot_copy_state, dot_unwabi,
+	dot_personality): Use the appropriate one of the above.
+	(dot_proc): Clear unwind.proc_start; set to current location only if
+	none of the entry points were valid. Check for non-zero-length entry
+	point names. Check that entry points aren't defined, yet. Clear
+	unwind.prologue, unwind.body, and unwind.insn.
+	(dot_body): Call in_procedure. Check that first directive in procedure
+	had no insns emitted before. Set unwind.body.
+	(dot_prologue): Call in_procedure. Check that not already in prologue.
+	Check that first directive in procedure had no insns emitted before.
+	Clear unwind.body.
+	(dot_endp): Call in_procedure. Declare proc_end. Check for non-zero-
+	length entry point names. Check that entry points became defined.
+	(md_assemble): Set unwind.insn once unwind.proc_start is defined.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Snapshot manual bundling state
+	before actually using it. Don't generate an error in manual bundling
+	mode when looking at an insn requiring slot 2 but not yet at slot 2.
+	Don't generate an error in manual bundling mode when looking at an
+	insn required to be last in its group but the required slot hasn't
+	been reached, yet. Allow conversion from MII to MI;I for bundle
+	consisting of only 2 insns with the stop between them. Suppress
+	various meaningless errors resulting from detecting earlier ones.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (parse_operands): Also handle alloc without first
+	input being ar.pfs.
+
+2005-01-28  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-z8k.c (md_assemble): Improve error detection.
+
+2005-01-28  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (ia64_estimate_size_before_relax): Allocate space
+	for personality routine pointer only if there is one.
+	(ia64_convert_frag): Likewise.
+	(generate_unwind_image): Likewise.
+
+2005-01-27  Christian Groessler  <chris@groessler.org>
+
+	* config/tc-z8k.c (INSERT): Remove, not used anywhere.
+	(md_apply_fix3): Make relative branches out of range an error
+	instead of a warning.  Display correct line number for out of
+	range branches/calls/memory accesses.
+
+2005-01-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* dwarf2dbg.c (dwarf2_finish): Correct logic for determining when
+	to emit .debug_line and other debug sections.
+	* as.h (seg_not_empty_p): Declare.
+	* subsegs.c (seg_not_empty_p): New predicate.
+
+2005-01-27  Andrew Cagney  <cagney@gnu.org>
+
+	* configure: Regenerate to track ../gettext.m4 change.
+
+2005-01-27  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Change "?imbf??" to "?ibmfxx".
+
+2005-01-27  Jan Beulich  <jbeulich@novell.com>
+
+	* config/tc-ia64.c (emit_one_bundle): Add late resolution of move
+	to/from application registers dynamic insns.
+	(md_assemble): Defer resolution of move to/from application registers
+	dynamic insns when they can be issued on either the I- or M-units.
+
+2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	* config/tc-frv.c (md_apply_fix3): Mark TLS symbols as such.
+	2004-12-10  Alexandre Oliva  <aoliva@redhat.com>
+	* config/tc-frv.c (frv_pic_ptr): Add tlsmoff support.
+	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
+	* cgen.c (gas_cgen_parse_operand): Handle
+	CGEN_PARSE_OPERAND_SYMBOLIC.
+	* config/tc-frv.c (md_cgen_lookup_reloc): Handle TLS relocations.
+	(frv_force_relocation): Likewise.  Fix handling of PIC
+	relocations.
+	(md_apply_fix3): Likewise.
+
+2005-01-21  Ben Elliston  <bje@au.ibm.com>
+
+	* as.h: Remove #if 0'd code.
+	* atof-generic.c (atof_generic): Likewise.
+	* ecoff.c (ecoff_directive_frame): Likewise.
+	* frags.h (FRAG_APPEND_1_CHAR): Likewise.
+	* itbl-ops.c (itbl_add_reg): Likewise.
+	* listing.c (calc_hex): Likewise.
+	* read.c (MASK_CHAR): Likewise.
+	* subsegs.c (subsegs_print_statistics): Likewise.
+	* symbols.c (indent): Likewise.
+	* write.c (write_relocs): Likewise.
+	(write_object_file): Likewise.
+	(relax_frag): Likewise.
+
+2005-01-20  Nick Clifton  <nickc@redhat.com>
+
+	* as.c (std_longopts): Add an entry for "--a" in order to prevent
+	getopt_long_only() from considering -a as an abbreviation for
+	--alternate.
+	(parse_args): Fix the parsing of -a=<file>.
+
+2005-01-20  Alan Modra  <amodra@bigpond.net.au>
+
+	PR gas/684
+	* read.c (s_incbin): Adjust default count for skip.  Check validity
+	of count and skip rigorously.
+
+2005-01-19  Fred Fish  <fnf@specifixinc.com>
+
+	* config/tc-mips.c (dummy_opcode): Add init for new struct member.
+
+2005-01-19  Richard Sandiford  <rsandifo@redhat.com>
+
+	* read.c (convert_to_bignum): New function, split out from...
+	(emit_expr): ...here.  Handle the case where X_add_number is
+	positive and the input value is negative.
+	(output_big_sleb128): Fix setting of continuation bit.  Check whether
+	the final byte needs to be sign-extended.  Fix size-shrinking loop.
+	(emit_leb128_expr): When generating a signed leb128, see whether the
+	sign of an O_constant's X_add_number matches the sign of the input
+	value.  Use a bignum if not.
+
+2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* tc-sh.c (md_begin,md_parse_option): Change arch_sh1_up to
+	arch_sh_up in order to match the external name and make the
+	testsuite's job easier.
+
+2005-01-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 659
+	* config/tc-i386.c (i386_scale): Disallow 0 scale.
+
+2005-01-12  Nick Clifton  <nickc@redhat.com>
+
+	* config/tc-iq2000.c (s_iq2000_set): Fix thinko parsing
+	ignored_arguments array.
+
+2005-01-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* write.c (write_object_file): Disallow a symbol equated to
+	common symbol.
+
+2005-01-10  Inderpreet Singh <inderpreetb@noida.hcltech.com>
+
+	* tc-maxq.c: Replace constants 10 and 20 with bfd_mach_maxq10 and
+	bfd_mach_maxq20.
+	(md_pseudo_table): Add new pseudo ops for maxq10 and maxq20.
+	(maxq_target): New function: Set the machine type.
+
+2005-01-06  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (FPU_DEFAULT): Define for TE_VXWORKS.
+	(md_begin): Handle TE_VXWORKS for FP defaults.
+	(md_apply_fix3): Correct rela offsets.
+	(elf32_arm_target_format): Add VxWorks targets.
+
+2005-01-06  Paul Brook  <paul@codesourcery.com>
+
+	* configure.tgt: Set em=vxworks for *-*-vxworks.
+	* config/te-vxworks.h: New File.
+
+2005-01-06  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_cpus): Correct arch field for arm1026ej-s.
+
+2005-01-04  Dmitry Diky  <diwil@spec.ru>
+
+	* config/tc-msp430.c (md_apply_fix3): Fix offset calculation for
+	global label.
+
+2005-01-03  David Mosberger  <davidm@hpl.hp.com>
+
+	* config/tc-ia64.c (md): Add member "loc_directive_seen".
+	(dot_loc): New function.
+	(md_pseudo_table): Add entry to map .loc to dot_loc().
+	(emit_one_bundle): Only call dwarf2_gen_line_info() if we have
+	seen a .loc directive or we're generating DWARF2 debug info for
+	assembly source.
+
+For older changes see ChangeLog-2004
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/ChangeLog-9295 b/gas/ChangeLog-9295
index 713573301528..f51559689eb2 100644
--- a/gas/ChangeLog-9295
+++ b/gas/ChangeLog-9295
@@ -248,7 +248,7 @@ Wed Nov 15 03:52:00 1995  Ken Raeburn  <raeburn@cygnus.com>
 	Mon Jul 31 14:53:19 1995  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
 	* config/tc-i386.h (md_do_align): cast fill and 0x90 to char
- 	before comparing
+	before comparing
 
 	Mon May  1 10:91:49 1995  Alan Modra  <alan@spri.levels.unisa.edu.au>
 
@@ -506,9 +506,9 @@ Mon Oct 23 16:20:04 1995  Ken Raeburn  <raeburn@cygnus.com>
 Mon Oct 23 11:15:44 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
 
 	* config/tc-mips.c: Added mips_4100 control, and support for
- 	accepting the 4100 as a MIPS architecture variant (md_begin,
- 	macro_build, mips_ip, md_parse_option). Adding suitable
- 	command-line OPTIONs, and updating the help text (md_show_usage).
+	accepting the 4100 as a MIPS architecture variant (md_begin,
+	macro_build, mips_ip, md_parse_option). Adding suitable
+	command-line OPTIONs, and updating the help text (md_show_usage).
 	
 Wed Oct 18 13:20:32 1995  Ken Raeburn  <raeburn@cygnus.com>
 
@@ -840,11 +840,11 @@ Wed Sep 27 10:29:13 1995  Kim Knuttila  <krk@nellie>
 	(md_assemble): Initial [toc]x(rtoc) support
 	(ppc_frob_label): Removed some xcoff specific processing from TE_PE
 	(ppc_frob_symbol): Removed some xcoff specific processing from TE_PE
-                           Added support for more predefined sections
-        (ppc_frob_section): Removed some xcoff specific processing from TE_PE
+	Added support for more predefined sections
+	(ppc_frob_section): Removed some xcoff specific processing from TE_PE
 	(ppc_fix_adjustable): Removed from TE_PE mainline
 	(md_apply_fix3): For TE_PE toc entries, we don't need to mess 
-        with fx_addnumber. Removed for the time being.
+	with fx_addnumber. Removed for the time being.
 	(lots): Put back missing assignments to ppc_current_csect.
 
 Tue Sep 26 14:57:59 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
@@ -1066,7 +1066,7 @@ Thu Sep  7 12:33:58 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* expr.c (operand): Handle 08 and 09 in MRI mode.
 	* macro.c (ISSEP): Remove duplicated `"' character.
- 	(get_any_string): Copy some characters for which ISSEP is true:
+	(get_any_string): Copy some characters for which ISSEP is true:
 	';', '>', '(', ')'.  Otherwise we can get in an infinite loop.
 	* read.c (s_space): In MRI mode, the expressions stop at the first
 	unquoted space.
@@ -1146,7 +1146,7 @@ Fri Sep  1 17:02:15 1995  steve chamberlain  <sac@slash.cygnus.com>
 
 Fri Sep  1 08:20:19 1995  James G. Smith  <jsmith@beauty.cygnus.com>
 
-        * config/tc-mips.c (md_parse_option, md_begin, md_show_usage):
+	* config/tc-mips.c (md_parse_option, md_begin, md_show_usage):
 	Add support for "-mcpu=vr4300" as processor identifier.
 
 Thu Aug 31 16:41:06 1995  steve chamberlain  <sac@slash.cygnus.com>
@@ -1157,8 +1157,8 @@ Thu Aug 31 16:41:06 1995  steve chamberlain  <sac@slash.cygnus.com>
 Tue Aug 29 19:42:58 1995  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
 
 	* config/tc-m68k.c (m68k_ip) [case POST/PRE/BASE]: Fix typo when
- 	looking at outer displacement.  Don't set the postindex bit if the
- 	index suppress bit is set (for memory indirect addressing mode).
+	looking at outer displacement.  Don't set the postindex bit if the
+	index suppress bit is set (for memory indirect addressing mode).
 
 Thu Aug 31 06:49:37 1995  Doug Evans  <dje@canuck.cygnus.com>
 
@@ -1539,7 +1539,7 @@ Fri Aug 11 19:16:08 1995  Ian Lance Taylor  <ian@cygnus.com>
 	* doc/gasp.texi: Document -M/--mri.
 
 	* gasp.c: Include ansidecl.h.  Make all local functions static.
-        Add prototypes for all static functions.
+	Add prototypes for all static functions.
 	(mri): New global variable.
 	(sb_add_char): Change parameter c from char to int.
 	(sb_add_string): Make parameter s into a const pointer.
@@ -1843,7 +1843,7 @@ Mon Aug  7 02:54:20 1995  Jeff Law  (law@snake.cs.utah.edu)
 Fri Aug  4 12:29:21 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* expr.c (op_encoding): Make non-const.  Don't set '"' to
-        O_bit_not.
+	O_bit_not.
 	(expr_begin): Set op_encoding['"'] in MRI mode.
 
 Wed Aug  2 18:39:43 1995  Ian Lance Taylor  <ian@cygnus.com>
@@ -2471,7 +2471,7 @@ Wed Jun 21 18:07:59 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 	(md_estimate_size_before_relax) [case TAB (FBRANCH, SZ_UNDEF)]:
 	Turn on long bit.
 	(m68k_ip) [case 'C']: Don't set set long bit, set it in the opcode
- 	table.
+	table.
 	(md_estimate_size_before_relax) [case TAB (PCINDEX, SZ_UNDEF)]:
 	Variable part increases by four, not six.
 	* write.c (fixup_segment) [TC_M68K]: Don't do further pcrel
@@ -4143,7 +4143,7 @@ Tue Dec 13 08:04:15 1994  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-mips.c (macro_build): Accept BFD_RELOC_PCREL* without
 	requiring that the X_op_symbol be in the text_section.
-	(macro): Change the test for a legel expression difference to
+	(macro): Change the test for a legal expression difference to
 	correspond to changes in pseudo_set in read.c.
 
 Fri Dec  9 21:04:17 1994  Ken Raeburn  <raeburn@cujo.cygnus.com>
@@ -13115,3 +13115,10 @@ Mon Feb 17 07:51:06 1992  K. Richard Pixley  (rich at cygnus.com)
 	* nearly everything.  flush ChangeLog, package as gas-1.92.1.
 	  ChangeLog's prior to this are sketchy at best.  I have logs.
 	  They just aren't ChangeLogs.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/ChangeLog-9697 b/gas/ChangeLog-9697
index 7ffff3e6652b..f39e99554e87 100644
--- a/gas/ChangeLog-9697
+++ b/gas/ChangeLog-9697
@@ -4,7 +4,7 @@ Wed Dec 31 12:29:47 1997  Jeffrey A Law  (law@cygnus.com)
 
 Mon Dec 22 13:06:05 1997  Joel Sherrill  <joel@oarcorp.com>
 
-        * configure.in (i386*-go32-rtems*): Fix to be the same as
+	* configure.in (i386*-go32-rtems*): Fix to be the same as
 	i[3456]86-go32.
 	* configure: Rebuild.
 
@@ -96,7 +96,7 @@ Mon Dec 15 15:20:32 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* doc/as.texinfo: Add documentation of m32r processor.
 
-	* doc/c-m32r.texi: New file, documenting m32r specific features.  
+	* doc/c-m32r.texi: New file, documenting m32r specific features.
 
 Mon Dec 15 10:32:28 1997  Jeffrey A Law  (law@cygnus.com)
 
@@ -151,7 +151,7 @@ Sat Nov 22 16:19:22 1997  Richard Henderson  <rth@cygnus.com>
 Sat Nov 22 14:26:09 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-arm.c: Brought up to date with latest changes on arm
-	branch. 
+	branch.
 
 Sat Nov 22 15:50:09 1997  Klaus Kaempf  <kkaempf@progis.de>
 
@@ -171,7 +171,7 @@ Thu Nov 20 15:06:08 1997  Richard Earnshaw <rearnsha@arm.com>
 
 Wed Nov 19 17:44:42 1997  Richard Henderson  <rth@cygnus.com>
 
-        * config/tc-sh.c (parse_reg): Properly quote for fv4.
+	* config/tc-sh.c (parse_reg): Properly quote for fv4.
 
 Wed Nov 19 23:46:18 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -180,7 +180,7 @@ Wed Nov 19 23:46:18 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
 
-	* config/tc-d10v.c (parallel_ok, find_opcode): 
+	* config/tc-d10v.c (parallel_ok, find_opcode):
 	Split OPERAND_FLAG into OPERAND_FFLAG and OPERAND_CFLAG.
 
 Sun Nov 16 10:05:07 1997  Fred Fish  <fnf@cygnus.com>
@@ -191,9 +191,9 @@ Sun Nov 16 10:05:07 1997  Fred Fish  <fnf@cygnus.com>
 Thu Nov 13 13:53:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* configure.in (emulations): Make FreeBSD an aout / i386bsd
- 	variant.
+	variant.
 	* configure: Re-generate.
-	
+
 Thu Nov 13 11:07:14 1997  Gavin Koch  <gavin@cygnus.com>
 
 	* config/tc-mips.c (macro_build): Use the membership field
@@ -255,35 +255,35 @@ Tue Nov  4 16:35:57 1997  Ian Dall  <Ian.Dall@dsto.defence.gov.au>
 	* write.c (print_fixup): Use TC_FIX_DATA_PRINT (if defined) to
 	print out MD fields of fix.
 	* frags.c (frag_var, frag_variant): Use TC_FRAG_INIT macro (if
- 	defined) to initialize MD fields in frag.
+	defined) to initialize MD fields in frag.
 	* as.h (struct frag, ns32k support): Rename ns32k to fr_ns32k.
 	Delete pcrel_adjust.  Add fr_opcode_fragP, fr_opcode_offset.
 	* config/tc-ns32k.h: Add comments. Remove obsolete
- 	BFD_FAST_SECTION_FILL definition, change prototypes for
- 	fix_new_ns32k and fix_new_ns32k_exp to add new arguments
- 	opcode_frag and opcode_offset and remove pcrel_adjust.
+	BFD_FAST_SECTION_FILL definition, change prototypes for
+	fix_new_ns32k and fix_new_ns32k_exp to add new arguments
+	opcode_frag and opcode_offset and remove pcrel_adjust.
 	(TC_FIX_TYPE): add opcode_fragP and opcode_offset fields.
 	(TC_FIX_DATA_PRINT): new macro to print out TC_FIX_TYPE.
 	(TC_FRAG_INIT): new macro to initialize machine dependent field in
- 	frags.
+	frags.
 	(frag_opcode_frag, frag_opcode_offset, frag_bsr): macros to access
- 	MD fields in frag structure.
+	MD fields in frag structure.
 	(fix_im_disp, fix_bit_fixP, fix_opcode_frag, fix_opcode_offset,
- 	fix_bsr): macros to access MD fields in fix structure.
+	fix_bsr): macros to access MD fields in fix structure.
 	* config/tc-ns32k.c: Avoid overlength lines. Align comments.  Don't
- 	use struct opcode_location as these fields are now in the frag
+	use struct opcode_location as these fields are now in the frag
 	structure.
 	(convert_iif): Call frag_more as it is needed instead
- 	of trying to allocate for the whole insn. Avoid call of frag_more
- 	with negative argument.
+	of trying to allocate for the whole insn. Avoid call of frag_more
+	with negative argument.
 	(md_pcrel_adjust, md_fix_pcrel_adjust, md_apply_fix,
 	md_estimate_size_before_relax, md_pcrel_from,
 	tc_aout_fix_to_chars): use accessor macros to get md fields in fix
- 	and frag structures.
+	and frag structures.
 	(fix_new_ns32k, fix_new_ns32k_exp): add new arguments opcode_frag and
 	opcode_offset and remove pcrel_adjust.
 	(convert_iif, cons_fix_new_ns32k): call fix_new_ns32k,
- 	fix_new_ns32k_exp with changed arguments.
+	fix_new_ns32k_exp with changed arguments.
 
 Mon Nov  3 13:30:17 1997  Gavin Koch  <gavin@cygnus.com>
 
@@ -429,8 +429,8 @@ Tue Oct 14 19:12:45 1997  Richard Henderson  <rth@cygnus.com>
 Fri Oct 10 16:09:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* config/tc-d10v.c (parallel_ok): Allow parallel instruction issue
- 	when second instruction is writing to first instructions inputs.
-	
+	when second instruction is writing to first instructions inputs.
+
 Mon Oct 13 15:27:17 1997  Richard Henderson  <rth@cygnus.com>
 
 	* ecoff.c (PAGE_SIZE): Double to 8k as a hack to allow some C++
@@ -439,7 +439,7 @@ Mon Oct 13 15:27:17 1997  Richard Henderson  <rth@cygnus.com>
 Fri Oct 10 17:48:29 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c (md_relax_table): Add support for relaxing
-	unconditional branches.  This patch is courtesy of Jim Wilson. 
+	unconditional branches.  This patch is courtesy of Jim Wilson.
 	(md_convert_frag): Fix relaxing of branches.  This patch is
 	courtesy of Jim Wilson.
 	(md_assemble): Create different fixups for conditional and
@@ -449,7 +449,7 @@ Fri Oct 10 17:48:29 1997  Nick Clifton  <nickc@cygnus.com>
 	branch.  This patch is courtesy of Jim Wilson.
 	(v850_sdata, v850_tdata, v850_zdata, v850_sbss, v850_tbss,
 	v850_zbss, v850_rosdata, v850_rozdata, v850_bss): Add call to
-	obj_elf_section_change_hook(). 
+	obj_elf_section_change_hook().
 	(v850_comm): New function.
 	(md_pseudo_table): Add new pseudo ops .zcomm, .scomm and .tcomm.
 	(md_begin): Add bss flag to seg_info of bss sections.
@@ -472,7 +472,7 @@ Fri Oct 10 11:22:45 1997  Martin M. Hunt  <hunt@cygnus.com>
 Fri Oct 10 11:54:50 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* config/tc-d10v.c (parallel_ok): Flag SP as modified for @-sp
- 	operand - OPERAND_ATMINUS.
+	operand - OPERAND_ATMINUS.
 
 Fri Oct 10 00:47:44 1997  Michael Meissner  <meissner@cygnus.com>
 
@@ -532,7 +532,7 @@ Wed Oct  8 00:04:05 1997  Gavin Koch  <gavin@cygnus.com>
 	* config/tc-mips.c (md_begin): Replace the TARGET_CPU value
 	of mipsr3900 with mipstx39.
 
-	* config/tc-mips.c (mips_ip): Don't print the 'opcode requires 
+	* config/tc-mips.c (mips_ip): Don't print the 'opcode requires
 	-mipsXX message' if the insn isn't an ISA insn.
 
 Tue Oct  7 12:48:30 1997  Doug Evans  <dje@canuck.cygnus.com>
@@ -580,7 +580,7 @@ Thu Sep 25 13:08:02 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 Wed Sep 24 16:54:40 1997  Joel Sherrill  <joel@oarcorp.com>
 
-        * configure.in (sh*-*-rtems*): New target, like sh-*-elf*.
+	* configure.in (sh*-*-rtems*): New target, like sh-*-elf*.
 	* configure: Rebuild.
 
 Wed Sep 24 11:30:25 1997  Ian Lance Taylor  <ian@cygnus.com>
@@ -624,7 +624,7 @@ Thu Sep 18 14:11:56 1997  Nick Clifton  <nickc@cygnus.com>
 	(md_assemble): Produce error message when special data area
 	relocations are used on instructions which do not support them.
 	(md_assemble): Reset processor mask if defined by command line
-	switch. 
+	switch.
 
 Thu Sep 18 11:24:01 1997  Doug Evans  <dje@canuck.cygnus.com>
 
@@ -653,13 +653,13 @@ Thu Sep 18 11:24:01 1997  Doug Evans  <dje@canuck.cygnus.com>
 Wed Sep 17 16:54:20 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c (v850_reloc_prefix): Recoded to use CHECK_ ()
-	macro. 
+	macro.
 	(handle_tdaoff, handle_zdaoff, handle_sdaoff): New functions.
 
 	* config/tc-v850.c (md_assemble): Corrected typo.
 	* config/tc-v850.c Add new sections: call_table_data and
 	call_table_text.
-	(v850_reloc_prefix): Add support for ctoff() relocation prefix. 
+	(v850_reloc_prefix): Add support for ctoff() relocation prefix.
 	(handle_ctoff): New Function.
 
 	* doc/c-v850.texi (V850 Opcodes): Document call table relocations.
@@ -679,7 +679,7 @@ Mon Sep 15 18:33:06 1997  Nick Clifton  <nickc@cygnus.com>
 	* config/tc-v850.c (processor_mask): New variable.
 	(set_machine, md_parse_option): Set processor_mask.
 	(md_assemble): Check that instruction is available to target
-	processor. 
+	processor.
 
 	* config/tc-v850.h (TARGET_PROCESSOR): New constant.
 
@@ -768,7 +768,7 @@ Tue Sep  9 10:19:37 1997  Nick Clifton  <nickc@cygnus.com>
 	* config/tc-v850.c (.v850): New pseudo op.
 	* config/tc-v850.c (.v850e): New pseudo op.
 	* config/tc-v850.c (.v850ea): New pseudo op.
-	
+
 
 Mon Sep  8 23:08:04 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -791,7 +791,7 @@ Mon Sep  8 12:33:40 1997  Nick Clifton  <nickc@cygnus.com>
 	* config/tc-v850.h (TARGET_MACHINE): New constant.
 
 	* config/tc-v850.c (v850_insert_operand): Add
-	-mwarn_unsigned_overflow. 
+	-mwarn_unsigned_overflow.
 	(md_begin): Set BFD machine number based on machine variable.
 	(md_parse_option): Add -mv850, -mv850e and -mv850ea options.
 
@@ -802,15 +802,15 @@ Mon Sep  8 11:20:46 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 Sun Sep  7 00:30:19 1997  Richard Henderson  <rth@cygnus.com>
 
-        * config/tc-alpha.c (md_parse_option): Move m[] out to top level and
-        rename to cpu_types[].
-        (s_alpha_arch): New function.
-        (md_pseudo_table): Add "arch".
+	* config/tc-alpha.c (md_parse_option): Move m[] out to top level and
+	rename to cpu_types[].
+	(s_alpha_arch): New function.
+	(md_pseudo_table): Add "arch".
 
-        * config/tc-alpha.c (md_begin): Merge the two loops through the
-        opcode table.
-        (s_alpha_proc): Add initial SKIP_WHITESPACE.
-        (s_alpha_set): Likewise.  Use get_symbol_end instead local while loop.
+	* config/tc-alpha.c (md_begin): Merge the two loops through the
+	opcode table.
+	(s_alpha_proc): Add initial SKIP_WHITESPACE.
+	(s_alpha_set): Likewise.  Use get_symbol_end instead local while loop.
 
 Sat Sep  6 19:38:12 1997  Fred Fish  <fnf@cygnus.com>
 
@@ -827,14 +827,14 @@ Wed Sep  3 11:21:33 1997  Nick Clifton  <nickc@cygnus.com>
 
 Tue Sep  2 18:32:30 1997  Jeffrey A Law  (law@cygnus.com)
 
-        * config/tc-mn10200.c (md_convert_frag): PC relative instructions arex
+	* config/tc-mn10200.c (md_convert_frag): PC relative instructions arex
 	relative to the next instruction, not the current instruction.
 	(md_assemble): Similarly.
 
 Tue Sep  2 15:58:52 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* doc/c-v850.texi: Explanations of offsets in SDA/ZDA areas
-	correcetd. 
+	correcetd.
 
 	* config/tc-v850.c: Add support for SDA/TDA/ZDA sections.
 	(v850_reloc_prefix): Duplicate code eliminated.  Add code to
@@ -842,12 +842,12 @@ Tue Sep  2 15:58:52 1997  Nick Clifton  <nickc@cygnus.com>
 	(md_assemble): Calculation of the size of a fixups corrected.
 
 	* config/tc-v850.h (ELF_TC_SPECIAL_SECTIONS): Add SDA/TDA/ZDA
-	sections. 	
+	sections.
 
 Tue Sep  2 15:40:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* config/tc-v850.c (md_assemble): Use opcode->name instead of
- 	opcode->opcode as the sentinal. Zero is a valid opcode.
+	opcode->opcode as the sentinal. Zero is a valid opcode.
 
 Tue Aug 26 16:51:14 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -857,7 +857,7 @@ Tue Aug 26 16:51:14 1997  Ian Lance Taylor  <ian@cygnus.com>
 Tue Aug 26 09:46:22 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* doc/c-v850.texi (V850 Opcodes): Correct name for tiny data area
-	pointer. 
+	pointer.
 
 Tue Aug 26 12:23:25 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -898,15 +898,15 @@ Mon Aug 25 14:25:48 1997  Ian Lance Taylor  <ian@cygnus.com>
 Mon Aug 25 11:21:48 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c (md_assemble): Restore input_line_pointer upon
-	exit. 
-	
+	exit.
+
 	* config/tc-v850.c (parse_register_list): Support constant
 	expressions as register lists.
 
 Mon Aug 25 10:19:34 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* doc/c-v850.texi: Change the major node to v850 Machine
-	Dependencies. 
+	Dependencies.
 
 Fri Aug 22 11:16:14 1997  Nick Clifton  <nickc@cygnus.com>
 
@@ -993,8 +993,8 @@ Mon Aug 18 11:26:36 1997  Nick Clifton  <nickc@cygnus.com>
 Mon Aug 18 11:24:21 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c: Remove support_v850e flag and command line
-	option. 
-	
+	option.
+
 	* configure.in (emulations): Add support for v850e target
 
 	* configure (emulations): Add support for v850e target
@@ -1002,8 +1002,8 @@ Mon Aug 18 11:24:21 1997  Nick Clifton  <nickc@cygnus.com>
 Mon Aug 18 11:24:21 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c: Remove support_v850ea flag and command line
-	option. 
-	
+	option.
+
 	* configure.in (emulations): Add support for v850ea target
 
 	* configure (emulations): Add support for v850ea target
@@ -1045,9 +1045,9 @@ Wed Aug 13 18:58:56 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-v850.c (md_assemble, md_show_usage, md_parse_option):
 	Add support for v850e instructions.
-	
+
 	* config/tc-v850.c (md_assemble): Fix error recovery to reload
-	text of entire opcode. 
+	text of entire opcode.
 
 Tue Aug 12 10:27:34 1997  Richard Henderson  <rth@cygnus.com>
 
@@ -1066,7 +1066,7 @@ Mon Aug 11 21:48:00 1997  Richard Henderson  <rth@cygnus.com>
 	functions.
 	* read.h: Update prototypes.
 	* symbols.c (resolve_symbol_value): Streamline quite a bit.  Return
-	the symbol value, add a second FINALIZE argument that prevents 
+	the symbol value, add a second FINALIZE argument that prevents
 	changes from being comitted.  Update all callers.
 	* write.c (cvt_frag_to_fill, relax_segment): Handle rs_leb128.
 	* doc/as.texinfo: Document the new pseudos.
@@ -1137,9 +1137,9 @@ Mon Aug  4 11:28:35 1997  Ian Lance Taylor  <ian@cygnus.com>
 	has an associated external symbol.
 
 Sun Aug  3 23:23:59 1997  Richard Henderson  <rth@cygnus.com>
- 
-        * config/tc-alpha.c (s_alpha_ucons): New function.
-        (md_pseudo_table): Add unaligned data pseudos for DWARF.
+
+	* config/tc-alpha.c (s_alpha_ucons): New function.
+	(md_pseudo_table): Add unaligned data pseudos for DWARF.
 
 Thu Jul 31 15:13:43 1997  Jeffrey A Law  (law@cygnus.com)
 
@@ -1158,10 +1158,10 @@ Tue Jul 29 14:20:43 1997  Jeffrey A Law  (law@cygnus.com)
 
 Mon Jul 28 18:41:41 1997  Rob Savoye  <rob@chinadoll.cygnus.com>
 
-        * configure.in: Use CYGWIN and EXEEXT autoconf macro to look for
-        win32 dependencies.
-        * configure: Regenerated with autoconf 2.12.
-        * Makefile.in: Add $(EXEEXT) to all executables.
+	* configure.in: Use CYGWIN and EXEEXT autoconf macro to look for
+	win32 dependencies.
+	* configure: Regenerated with autoconf 2.12.
+	* Makefile.in: Add $(EXEEXT) to all executables.
 
 Fri Jul 25 10:54:43 1997  Jeffrey A Law  (law@cygnus.com)
 
@@ -1182,9 +1182,9 @@ Thu Jul 24 17:51:29 1997  Ian Lance Taylor  <ian@cygnus.com>
 Thu Jul 24 12:13:19 1997  Fred Fish  <fnf@cygnus.com>
 
 	* config/tc-tic80.c (build_insn): Remove "extended" and replace with
- 	"fx" and "fxfrag".  Add "ffrag".  Change code to initialize and use
+	"fx" and "fxfrag".  Add "ffrag".  Change code to initialize and use
 	the right f/ffrag and fx/fxfrag pairs since instruction may be split
- 	across frags.
+	across frags.
 
 Tue Jul 22 18:38:56 1997  Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE>
 
@@ -1244,7 +1244,7 @@ Mon Jul  7 22:53:08 1997  Ian Lance Taylor  <ian@cygnus.com>
 	BFD_ASSEMBLER, handle one ELF case for COFF as well, and add a PE
 	case.
 	* write.c (fixup_segment): Change special case for i386-coff to
- 	not apply for i386-pe.
+	not apply for i386-pe.
 	* config/obj-coff.c (coff_adjust_section_syms): Only count fixups
 	which were not done.
 	(coff_frob_file_after_relocs): Rename from coff_frob_file.
@@ -1401,14 +1401,14 @@ Wed May 28 15:45:07 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-arm.c (md_begin): Change call to
 	coff_arm_bfd_set_private_flags() to a call to
-	bfd_set_private_flags(). 
+	bfd_set_private_flags().
 
 Wed May 28 16:17:34 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* Makefile.in: Rebuild dependencies.
 
 	* config/tc-i386.c (tc_gen_reloc): Don't try to convert the type
- 	of a BFD_RELOC_RVA reloc.
+	of a BFD_RELOC_RVA reloc.
 
 Wed May 28 10:48:14 1997  Jeffrey A Law  (law@cygnus.com)
 
@@ -1456,11 +1456,11 @@ Wed May 14 09:54:53 1997  Nick Clifton  <nickc@cygnus.com>
 
 	* config/tc-arm.c (global variables): Added 'uses_apcs_26' flag to
 	hold APCS selection.
-  	(md_begin): Added code to generate flags to be set into the COFF
+	(md_begin): Added code to generate flags to be set into the COFF
 	header and the calls to the BFD functions to do this.
-  	(md_parse_option, md_show_usage): Added new command line
+	(md_parse_option, md_show_usage): Added new command line
 	options -mapcs-32, -mapcs-26, -marmv2, -marmv2a, -marmv3,
-	-marmv3m, -marmv4, -marmv4t. 
+	-marmv3m, -marmv4, -marmv4t.
 
 	* config/tc-arm.h (LOCAL_LABEL): Removed the definition of this macro
 	as it is never used.
@@ -1493,7 +1493,7 @@ Thu May  8 11:10:15 1997  Ian Lance Taylor  <ian@cygnus.com>
 Wed May  7 15:39:48 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/obj-coff.c (write_object_file): Just pass NULL to
- 	md_do_align, not the address of a char holding NOP_OPCODE.
+	md_do_align, not the address of a char holding NOP_OPCODE.
 
 	* config/tc-mips.c (macro): Handle constants for M_LI_D and
 	M_LI_DD.
@@ -1540,7 +1540,7 @@ Tue Apr 29 20:23:10 1997  Jim Wilson  <wilson@cygnus.com>
 Tue Apr 29 19:54:36 1997  Richard Henderson  <rth@tamu.edu>
 
 	* config/obj-elf.c (elf_pseudo_table): Add "subsection".
- 	(obj_elf_subsection): New static function.
+	(obj_elf_subsection): New static function.
 
 Tue Apr 29 19:52:47 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -1606,7 +1606,7 @@ Tue Apr 15 18:11:44 1997  Gavin Koch  <gavin@cygnus.com>
 Tue Apr 15 13:04:47 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* Makefile.in (srcroot): Remove.
- 	(INSTALL): Set to @INSTALL@.
+	(INSTALL): Set to @INSTALL@.
 	(INSTALL_XFORM, INSTALL_XFORM1): Remove.
 	(all, dvi): Don't set srcroot.
 	(install): Depend upon as.new, gasp.new, and installdirs.  Use
@@ -1660,7 +1660,7 @@ Mon Apr  7 14:58:22 1997  Jeffrey A Law  (law@cygnus.com)
 Mon Apr  7 10:54:59 1997  Doug Evans  <dje@canuck.cygnus.com>
 
 	* Makefile.in: Regenerate dependencies.
- 	(TARG_CPU): New variable.
+	(TARG_CPU): New variable.
 	(cgen.o): Depend on cgen.h, $(TARG_CPU)-opc.h.
 	(.dep1): Delete creating of cgen-opc.h.
 	(.tcdep): Put proper contents in cgen-opc.h.
@@ -1761,7 +1761,7 @@ Mon Mar 31 23:53:44 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
 
 Mon Mar 31 16:31:04 1997  Joel Sherrill  <joel@oarcorp.com>
 
-        * configure.in (hppa*-*-rtems*): New target, like hppa-*-*elf*.
+	* configure.in (hppa*-*-rtems*): New target, like hppa-*-*elf*.
 	* configure: Rebuild.
 
 Mon Mar 31 14:15:19 1997  Ian Lance Taylor  <ian@cygnus.com>
@@ -1879,7 +1879,7 @@ Mon Mar 24 12:11:18 1997  Ian Lance Taylor  <ian@cygnus.com>
 	(alpha_frob_file_before_adjust): Declare if OBJ_ECOFF.
 	* config/tc-alpha.c (alpha_debug): New static variable.
 	(md_parse_option): Set alpha_debug if -g is seen.
- 	(alpha_frob_file_before_adjust): New function if OBJ_ECOFF.
+	(alpha_frob_file_before_adjust): New function if OBJ_ECOFF.
 
 Sun Mar 23 18:03:31 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
@@ -2030,7 +2030,7 @@ Sat Mar 15 20:27:12 1997  Fred Fish  <fnf@cygnus.com>
 	* NEWS: Note BeOS support.
 	* configure.in: (ppc-*-beos): New target, use coff as object format.
 	* configure: Regenerate with autoconf.
-	
+
 Sat Mar 15 19:14:02 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-mips.c (md_apply_fix): Improve error message for out
@@ -2290,23 +2290,23 @@ Mon Feb 24 18:27:43 1997  Eric Youngdale  <eric@andante.jic.com>
 
 Mon Feb 24 15:19:57 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c: Change pre_defined_registers to 
+	* config/tc-d10v.c: Change pre_defined_registers to
 	d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
 
 Mon Feb 24 10:40:45 1997  Fred Fish  <fnf@cygnus.com>
 
 	* config/obj-coff.c: Fix typo in comment section.
 	* config/tc-tic80.c (md_pseudo_table): Add entry for bss, which takes
- 	an additional alignment argument.
+	an additional alignment argument.
 	(find_opcode): Allow O_symbol relocs for any 32 bit field, not just
- 	base relative ones.
+	base relative ones.
 	(build_insn): Handle O_symbol relocs for any 32 bit field, not just
- 	base relative ones.
+	base relative ones.
 
 Mon Feb 24 02:23:00 1997  Dawn Perchik  <dawn@cygnus.com>
 
 	* Makefile.in: Remove dependancies on itbl-cpu.h.
-	* as.c: Define stubs for itbl_parse and itbl_init if HAVE_ITBL_CPU 
+	* as.c: Define stubs for itbl_parse and itbl_init if HAVE_ITBL_CPU
 	is not defined.
 
 Mon Feb 24 02:03:00 1997  Dawn Perchik  <dawn@cygnus.com>
@@ -2354,10 +2354,10 @@ Sat Feb 22 21:25:00 1997  Dawn Perchik  <dawn@cygnus.com>
 	* as.c: Add itbl support.
 	Add new option "--insttbl" for dynamically extending instruction set.
 	* as.h: Declare insttbl_file_name;
-	the name of file defining extensions to the basic instruction set 
-	* configure.in, configure: Add itbl-parse.o, itbl-lex.o, and 
+	the name of file defining extensions to the basic instruction set
+	* configure.in, configure: Add itbl-parse.o, itbl-lex.o, and
 	itbl-ops.o to extra_objects for mips configuration.
-	Add include file link from itbl-cpu.h to 
+	Add include file link from itbl-cpu.h to
 	config/itbl-${target_cpu_type}.h.
 	* config/tc-mips.c: Allow copz instructions.
 	Add notes for future additions to the itbl support.
@@ -2372,18 +2372,18 @@ Sat Feb 22 20:53:01 1997  Fred Fish  <fnf@cygnus.com>
 	* config/tc-tic80.c (find_opcode): Add code to support O_symbol
 	operands.
 	(build_insn): Grab a frag early so we can use the address in
- 	fixups.  Take one's complement of BITNUM values before insertion
- 	in opcode.  Add code to support O_symbol operands.
+	fixups.  Take one's complement of BITNUM values before insertion
+	in opcode.  Add code to support O_symbol operands.
 	(md_apply_fix): Replace unimplemented warning with implementation.
 	(md_pcrel_from): Ditto.
 	(tc_coff_fix2rtype): Ditto.
 
 Fri Feb 21 14:34:31 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d30v.c (parallel_ok): New function. 
+	* config/tc-d30v.c (parallel_ok): New function.
 	* config/tc-d30v.h: Define TARGET_BYTES_BIG_ENDIAN.
 	* config/tc-d10v.c (md_pcrel_from_section): Return 0 if
-        relocation is in different section.
+	relocation is in different section.
 
 Fri Feb 21 10:08:25 1997  Jim Wilson  <wilson@cygnus.com>
 
@@ -2397,7 +2397,7 @@ Fri Feb 21 11:55:03 1997  Ian Lance Taylor  <ian@cygnus.com>
 	* app.c (LEX_IS_TWOCHAR_COMMENT_2ND): Don't define.
 	(do_scrub_begin): Don't set lex['*'].
 	(do_scrub_chars): When handling LEX_IS_TWOCHAR_COMMENT_1ST, don't
- 	check for LEX_IS_TWOCHAR_COMMENT_2ND.  Instead, just check for
+	check for LEX_IS_TWOCHAR_COMMENT_2ND.  Instead, just check for
 	a literal '*'.
 
 	* configure.in: Set em=svr4 for m68k-*-sysv4*.
@@ -2439,24 +2439,24 @@ Tue Feb 18 18:42:51 1997  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d30v.c, config/tc-d30v.h: New files.
 
- 	* configure: Rebuilt.
-	
+	* configure: Rebuilt.
+
 	* configure.in: Add case for d30v.
 
 Sun Feb 16 17:47:29 1997  Fred Fish  <fnf@cygnus.com>
 
 	* config/tc-alpha.h (md_operand): Define with a null expansion,
 	like all the other targets.
-	* doc/internals.texi (CPU backend): Add missing word in 
+	* doc/internals.texi (CPU backend): Add missing word in
 	md_flush_pending_output description.  Fix typo in md_convert_frag
 	description.
 	* config/tc-tic80: Minor comment additions/changes.
-	
+
 Fri Feb 14 18:09:59 1997  Philippe De Muyter  <phdm@info.ucl.ac.be>
 
 	* config/tc-m68k.c (LOCAL_LABEL): Macro redefined if TE_DELTA.
 	(tc_canonicalize_symbol_name): Macro defined if TE_DELTA.
- 	* config/obj-coff.c (obj_coff_def): Use
+	* config/obj-coff.c (obj_coff_def): Use
 	tc_canonicalize_symbol_name if defined.
 	(obj_coff_tag, obj_coff_val): Likewise.
 	* expr.c (operand): Reject '~' as operator if is_name_beginner.
@@ -2503,7 +2503,7 @@ Thu Feb 13 20:02:16 1997  Fred Fish  <fnf@cygnus.com>
 	tc-mn10200.h, tc-mn10300.h, tc-sh.h, tc-vax.h, tc-w65.h}:
 	Add default definition of zero for TARGET_BYTES_BIG_ENDIAN.
 	* config/{tc-arm.h, tc-hppa.h, tc-i386.h, tc-mips.h, tc-ns32k.h,
- 	tc-ppc.h, tc-sparc.h}: Move definition of TARGET_BYTES_BIG_ENDIAN
+	tc-ppc.h, tc-sparc.h}: Move definition of TARGET_BYTES_BIG_ENDIAN
 	to a location consistent with the rest of the target include files.
 	* config/tc-i386.c: Remove misleading comment.
 	* doc/internals.texi (CPU backend): Add description of function
@@ -2513,7 +2513,7 @@ Thu Feb 13 20:02:16 1997  Fred Fish  <fnf@cygnus.com>
 	Remove custom code that use to parse them.
 	* config/tc-tic80.h: Move definition of TARGET_BYTES_BIG_ENDIAN
 	to a location consistent with the rest of the target include files.
-	
+
 Thu Feb 13 21:44:18 1997  Klaus Kaempf  <kkaempf@progis.de>
 
 	* as.h: GNU c provides unlink() function.
@@ -2541,7 +2541,7 @@ Thu Feb 13 16:29:04 1997  Fred Fish  <fnf@cygnus.com>
 	(DVIPS): Set to dvips.
 	(ps, as.ps, gasp.ps): New targets.
 	(internals.info, gasp.dvi, internals.dvi): Set both TEXINPUTS
- 	and MAKEINFO env variables.
+	and MAKEINFO env variables.
 	(internals.ps): Use DVIPS macro.
 	(clean): Remove core and backup files.
 	(distclean): Remove temporary files from building internals.
@@ -2623,7 +2623,7 @@ Wed Feb 12 14:36:29 1997  Ian Lance Taylor  <ian@cygnus.com>
 	symbol.
 
 	* config/tc-mips.c (append_insn): Warn about an attempt to put an
- 	extended instruction in a delay slot when not reordering.
+	extended instruction in a delay slot when not reordering.
 	(md_convert_frag): Warn if an extended instruction appears in a
 	delay slot.
 
@@ -2659,11 +2659,11 @@ Mon Feb 10 22:06:00 1997  Dawn Perchik  (dawn@cygnus.com)
 
 Mon Feb 10 18:09:00 1997  Dawn Perchik  (dawn@cygnus.com)
 
-	* itbl-ops.c: New file.  Add support for dynamically read 
-	instruction registers, opcodes and formats.  Build internal table 
-	for new instructions and provide callbacks for assembler and 
+	* itbl-ops.c: New file.  Add support for dynamically read
+	instruction registers, opcodes and formats.  Build internal table
+	for new instructions and provide callbacks for assembler and
 	disassembler.
-	* itbl-lex.l, itbl-parse.y: Lex and yacc parsers for instruction 
+	* itbl-lex.l, itbl-parse.y: Lex and yacc parsers for instruction
 	spec table.
 	* itbl-ops.h: New file.  Header file for itbl support.
 	* config/itbl-mips.h: New file.  Mips specific definitions for
@@ -2736,7 +2736,7 @@ Fri Jan 31 10:46:14 1997  Ian Lance Taylor  <ian@cygnus.com>
 	enforce-aligned-data.
 
 	* config/tc-ppc.c (md_pseudo_table): If OBJ_XCOFF, add "long",
- 	"word", and "short".
+	"word", and "short".
 	(ppc_xcoff_cons): New static function.
 
 	* write.c (relax_segment): Give an error if a .space symbol is
@@ -2816,14 +2816,14 @@ Wed Jan 22 10:39:39 1997  Doug Evans  <dje@canuck.cygnus.com>
 Mon Jan 20 10:56:47 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
 
 	* config/tc-m68k.c (m68k_ip): Reject pc-relative addresses for the
- 	'p' operand specifier.
+	'p' operand specifier.
 
 Mon Jan 20 10:39:36 1997  J.T. Conklin  <jtc@cygnus.com>
 
 	* config/tc-m68k.c (HAVE_LONG_BRANCH): New macro, returns true for
- 	m68k family cpus which support long branch addressing modes.
+	m68k family cpus which support long branch addressing modes.
 	(m68k_ip, md_convert_frag_1, md_estimate_size_before_relax,
- 	md_create_long_jump): Use it.
+	md_create_long_jump): Use it.
 
 Mon Jan 20 12:42:06 1997  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -2981,8 +2981,8 @@ Thu Jan  2 13:37:29 1997  Ian Lance Taylor  <ian@cygnus.com>
 	work if valueT is only 32 bits.
 
 	* config/tc-mips.c: Throughout, check target_big_endian rather
- 	than byte_order.
- 	(byte_order): Remove.
+	than byte_order.
+	(byte_order): Remove.
 	(mips_init_after_args): Remove.
 	* config/tc-mips.h (LITTLE_ENDIAN, BIG_ENDIAN): Don't define.
 	(mips_init_after_args): Don't declare.
@@ -3008,9 +3008,9 @@ Tue Dec 31 12:56:41 1996  Ian Lance Taylor  <ian@cygnus.com>
 	* Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
 
 	* config/tc-sparc.c (md_apply_fix3): Rename from md_apply_fix, and
- 	add segment argument.  If OBJ_ELF, treat a relocation against a
- 	symbol in a linkonce section like a relocation against an external
- 	symbol.
+	add segment argument.  If OBJ_ELF, treat a relocation against a
+	symbol in a linkonce section like a relocation against an external
+	symbol.
 	* config/tc-sparc.h (MD_APPLY_FIX3): Define.
 
 Mon Dec 30 11:35:40 1996  Ian Lance Taylor  <ian@cygnus.com>
@@ -3023,14 +3023,14 @@ Fri Dec 27 22:51:51 1996  Fred Fish  <fnf@cygnus.com>
 	includes config.h instead of host.h, tc.h instead of tp.h, and
 	targ-env.h instead of target-environment.h.
 	Also, obj-format.h includes targ-cpu.h instead of
- 	target-processor.h.
+	target-processor.h.
 	* configure.in (case ${generic_target}): Add tic80-*-coff entry.
 	* configure: Rebuild with autoconf.
 	* config/obj-coff.h (coff/tic80.h): Include if TC_TIC80 defined.
 	(TARGET_FORMAT): Define to "coff-tic80".
 	* config/tc-tic80.c: New file for TIc80 support.
 	* config/tc-tic80.h: New file for TIc80 support.
-	
+
 Fri Dec 27 11:42:29 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* doc/as.texinfo (M): Mention explicitly that -M changes macro
@@ -3065,7 +3065,7 @@ Wed Dec 18 10:08:46 1996  Jeffrey A Law  (law@cygnus.com)
 Tue Dec 17 10:59:32 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-mips.c: Undo part of last Friday's alignment changes.
- 	(md_begin): Always align the text section to a four byte
+	(md_begin): Always align the text section to a four byte
 	boundary.
 	(append_insn): Remove call to record_align.
 
@@ -3233,7 +3233,7 @@ Fri Dec  6 00:55:48 1996  Martin  <hunt@cygnus.com>
 	(d10v_cleanup): No longer uses its argument, so make it void.
 
 	* config/tc-d10v.h (d10v_cleanup): Change prototype.
-	
+
 Thu Dec  5 11:03:31 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* write.c (fixup_segment): Don't discard the symbol for a PC
@@ -3325,7 +3325,7 @@ Tue Nov 26 10:33:16 1996  Ian Lance Taylor  <ian@cygnus.com>
 Mon Nov 25 18:02:29 1996  J.T. Conklin  <jtc@beauty.cygnus.com>
 
 	* config/tc-m68k.c (m68k_ip): Implement cases for new <, >, m, n,
- 	o and p operand specifiers.
+	o and p operand specifiers.
 
 Mon Nov 25 10:45:14 1996  Doug Evans  <dje@seba.cygnus.com>
 
@@ -3359,7 +3359,7 @@ Fri Nov 22 15:42:26 1996  Ian Lance Taylor  <ian@cygnus.com>
 Thu Nov 21 11:56:11 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* config/tc-mn10300.h (DIFF_EXPR_OK): Don't define this.
-	(tc_fix_adjustable): Don't adjust relocs against weak symbols or 
+	(tc_fix_adjustable): Don't adjust relocs against weak symbols or
 	pc-relative relocs.
 	* config/tc-mn10300.c (md_begin): Set linkrelax.
 	(md_assemble): Create fixups as needed.
@@ -3399,7 +3399,7 @@ Fri Nov  8 13:55:03 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 	* doc/c-d10v.texi: Add info on @word modifier.
 
 Wed Nov  6 13:46:07 1996  Jeffrey A Law  (law@cygnus.com)
-	
+
 	* config/tc-mn10300.c (mn10300_insert_operand): MN10300_OPERAND_SPLIT
 	operands are assumed to be 32bits.  Use "bits" field to hold the
 	number of bits in the main instruction word for MN10300_OPERAND_SPLIT.
@@ -3556,8 +3556,8 @@ Mon Oct 21 11:38:30 1996  Ian Lance Taylor  <ian@cygnus.com>
 	(tc_gen_reloc): Handle BFD_RELOC_64.
 
 	* config/tc-i386.c (md_apply_fix3): Don't increment value for a PC
- 	relative reloc when BFD_ASSEMBLER and OBJ_AOUT (more ugly gas
- 	reloc hacking).
+	relative reloc when BFD_ASSEMBLER and OBJ_AOUT (more ugly gas
+	reloc hacking).
 
 	* config/obj-aout.h (S_IS_DEFINE): non BFD_ASSEMBLER version:
 	Don't check S_GET_OTHER.
@@ -3744,7 +3744,7 @@ Tue Oct  1 12:37:48 1996  Ian Lance Taylor  <ian@cygnus.com>
 	register numbers.  From Ken Rose <rose@netcom.com>.
 
 	* config/tc-alpha.c: Add some static function prototypes.
- 	(alpha_macros): Move to top of file.  Make static.
+	(alpha_macros): Move to top of file.  Make static.
 	(alpha_num_macros): Move to top of file.
 
 Tue Oct  1 09:36:19 1996  Stu Grossman  (grossman@critters.cygnus.com)
@@ -3768,7 +3768,7 @@ Tue Sep 24 19:05:08 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Tue Sep 24 12:22:18 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c (md_operand): Created.  Allows operands to 
+	* config/tc-d10v.c (md_operand): Created.  Allows operands to
 	start with '#'.
 	* config/tc-d10v.h (md_operand): Undefined.
 
@@ -3795,10 +3795,10 @@ Mon Sep 16 11:41:40 1996  Ian Lance Taylor  <ian@cygnus.com>
 Thu Sep 12 10:25:45 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-arm.c (md_apply_fix3): Update two thumb instruction
- 	slots when processing BL fixups.
+	slots when processing BL fixups.
 
 	* config/tc-arm.c (output_inst): Ensure Thumb BL fixup is marked
- 	on the first half of the instruction.
+	on the first half of the instruction.
 
 Wed Sep 11 00:09:35 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -3828,11 +3828,11 @@ Mon Sep  9 10:57:42 1996  Ian Lance Taylor  <ian@cygnus.com>
 Sat Sep  7 13:25:55 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-mips.c (COUNT_TOP_ZEROES): Added macro to count
- 	leading zeroes.
+	leading zeroes.
 	(load_register): Ensure hi32 bits are not lost during lo32bit
- 	processing. Fix shift offset that was overflowing into the next
- 	instruction field. Add code to generate shorter sequences for
- 	constants with a single contiguous seqeuence of ones.
+	processing. Fix shift offset that was overflowing into the next
+	instruction field. Add code to generate shorter sequences for
+	constants with a single contiguous seqeuence of ones.
 
 Fri Sep  6 17:07:12 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
@@ -3882,8 +3882,8 @@ Wed Sep  4 10:23:20 1996  Ian Lance Taylor  <ian@cygnus.com>
 Wed Sep  4 11:24:29 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-mips.c (load_register): Remove unnecessary code that
- 	was causing the high 32bits of 64bit constants to be lost.
-	
+	was causing the high 32bits of 64bit constants to be lost.
+
 Tue Sep  3 13:52:56 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: Added changes to support function
@@ -3916,22 +3916,22 @@ Fri Aug 30 23:50:08 1996  Jeffrey A Law  (law@cygnus.com)
 Fri Aug 30 18:35:26 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
 
 	* config/tc-v850.c (reg_name_search): Align calling convention to
- 	be like identical function found in tc-ppc.c.
+	be like identical function found in tc-ppc.c.
 	(get_reloc): Removed.
 	(v850_reloc_prefix): New function, parse lo(), hi() and hi0().
 	(md_assemble): emit fixups.
 	(md_pcrel_from): renamed from md_pcrel_from_section, emit proper
- 	displacement.
+	displacement.
 	(md_apply_fix3): handle fixups/relocs.
 	* config/tc-v850.h (MD_PCREL_FROM_SECTION): Removed definition.
-	
+
 Fri Aug 30 18:12:00 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	Add SH ELF support.
 	* configure.in (sh-*-elf*): New target.
 	* config/tc-sh.h (TARGET_ARCH): Define.
 	(WORKING_DOT_WORD): Define.
- 	(TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
+	(TC_COFF_FIX2RTYPE): Only define if OBJ_COFF.
 	(BFD_ARCH, COFF_MAGIC, TC_COUNT_RELOC): Likewise.
 	(TC_RELOC_MANGLE, tc_coff_symbol_emit_hook): Likewise.
 	(DO_NOT_STRIP, NEED_FX_R_TYPE, TC_KEEP_FX_OFFSET): Likewise.
@@ -3975,7 +3975,7 @@ Fri Aug 30 18:12:00 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Fri Aug 30 14:47:38 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c (find_opcode): Fix problem with calculating 
+	* config/tc-d10v.c (find_opcode): Fix problem with calculating
 	branch sizes in across sections.
 
 Fri Aug 30 00:44:13 1996  Jeffrey A Law  (law@cygnus.com)
@@ -4022,7 +4022,7 @@ Mon Aug 26 18:24:51 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 Mon Aug 26 13:39:27 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c (parallel_ok): Fix bug in parallel 
+	* config/tc-d10v.c (parallel_ok): Fix bug in parallel
 	checking code.
 
 Mon Aug 26 14:38:22 1996  Ian Lance Taylor  <ian@cygnus.com>
@@ -4035,7 +4035,7 @@ Mon Aug 26 14:38:22 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Fri Aug 23 11:40:47 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* doc/c-d10v.texi: Fix typo. 
+	* doc/c-d10v.texi: Fix typo.
 
 Fri Aug 23 10:41:32 1996  Jeffrey A Law  (law@cygnus.com)
 
@@ -4060,7 +4060,7 @@ Fri Aug 23 10:41:32 1996  Jeffrey A Law  (law@cygnus.com)
 	(system_register_name): New function.
 	(SYSREG_NAME_CNT): Define.
 	(md_assemble): Handle operands which are system registers.
-	
+
 	* config/tc-v850.c (md_assemble): If we find a register, but the
 	opcode doesn't want a register, then we don't have a match.
 	(md_assemble): Get size of the instruction from the opcode table.
@@ -4077,16 +4077,16 @@ Thu Aug 22 10:20:30 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Thu Aug 22 10:50:00 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c: Fix a reloc bug caused by my last change. 
+	* config/tc-d10v.c: Fix a reloc bug caused by my last change.
 	* doc/c-d10v.texi: Cleanup.
-	
+
 Tue Aug 20 15:15:16 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
 
 	* config/tc-v850.c: New file.
 	* config/tc-v850.h: New file.
 	* configure (v850-*-elf): New target.
 	* configure.in (v850-*-elf): New target.
-	
+
 Wed Aug 21 15:50:54 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* doc/c-d10v.texi: New file.
@@ -4096,7 +4096,7 @@ Wed Aug 21 15:50:54 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 Tue Aug 20 14:10:02 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: All references to defined symbols should
- 	now use the optimal instruction.  .float and .double now work. 
+	now use the optimal instruction.  .float and .double now work.
 
 Mon Aug 19 14:41:36 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -4111,13 +4111,13 @@ Thu Aug 15 16:37:59 1996  Stan Shebs  <shebs@andros.cygnus.com>
 Thu Aug 15 13:24:30 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: Add additional information to the opcode
-        table to help determinine which instructions can be done
-        in parallel. 
+	table to help determinine which instructions can be done
+	in parallel.
 
 Thu Aug 15 17:01:31 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-arm.c: Major changes to add Thumb support, with lots
- 	of change input from <rearnsha@armltd.co.uk>.
+	of change input from <rearnsha@armltd.co.uk>.
 	Reverted to INSN_SIZE macro, rather than insn_size variable.
 	(insns): Added ARM "bx" instruction support.
 	(tinsns): Added Thumb instruction definition structure.
@@ -4128,21 +4128,21 @@ Thu Aug 15 17:01:31 1996  James G. Smith  <jsmith@cygnus.co.uk>
 	(do_ldst): Simpler halfword support.
 	(do_ldmstm): Improved.
 	(reg_list, do_bx, thumb_reg, thumb_add_sub, thumb_shift,
- 	thumb_mov_compare, thumb_load_store, do_t_arit, do_t_add,
- 	do_t_asr, do_t_branch, do_t_bx, do_t_compare, do_t_ldmstm,
- 	do_t_ldrb, do_t_ldrh, do_t_lds, do_t_lsl, do_t_lsr, do_t_mov,
- 	do_t_push_pop, do_t_str, do_t_strb, do_t_strh, do_t_sub, do_t_swi,
- 	do_t_adr): Added.
+	thumb_mov_compare, thumb_load_store, do_t_arit, do_t_add,
+	do_t_asr, do_t_branch, do_t_bx, do_t_compare, do_t_ldmstm,
+	do_t_ldrb, do_t_ldrh, do_t_lds, do_t_lsl, do_t_lsr, do_t_mov,
+	do_t_push_pop, do_t_str, do_t_strb, do_t_strh, do_t_sub, do_t_swi,
+	do_t_adr): Added.
 	(md_apply_fix3): Add support for BFD_RELOC_ARM_THUMB_* relocations.
 	(md_parse_option): Add support for -mthumb.
 	(md_show_usage): Updated to reflect new command line option.
 	(arm_data_in_code, arm_canonicalize_symbol_name): Added.
 	* config/tc-arm.h: Provide TC_FIX_TYPE to allow private ARM
- 	fragment information to be held.
+	fragment information to be held.
 
 Thu Aug 15 16:12:00 1996  Richard Earnshaw (rearnsha@armltd.co.uk)
 
-	* config/tc-arm.c (md_apply_fix3): Also set fixP->fx_done if fx_addsy is 
+	* config/tc-arm.c (md_apply_fix3): Also set fixP->fx_done if fx_addsy is
 	non-null, but is a constant.
 	(fix_new_arm): Call make_expr_symbol to make the expression symbol
 	so that error reporting will work correctly.
@@ -4165,7 +4165,7 @@ Mon Aug 12 16:49:43 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Fri Aug  9 17:48:28 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
-	* config/tc-d10v.c: Fix problem with relocs. 
+	* config/tc-d10v.c: Fix problem with relocs.
 
 Fri Aug  9 14:16:14 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -4243,7 +4243,7 @@ Fri Aug  2 11:23:31 1996  Ian Lance Taylor  <ian@cygnus.com>
 Thu Aug  1 23:51:52 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* config/tc-hppa.c: Revert yesterday's changes.
-	
+
 Wed Jul 31 14:46:11 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: Disable range checking on 16-bit values.
@@ -4260,22 +4260,22 @@ Wed Jul 31 11:45:15 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 Wed Jul 31 15:41:42 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-arm.c: Changed INSN_SIZE to variable insn_size, as
- 	pre-cursor to adding Thumb support. Also added cpu_variant flag
- 	information to each of the asm_flg structures.
+	pre-cursor to adding Thumb support. Also added cpu_variant flag
+	information to each of the asm_flg structures.
 	(md_parse_option): Updated ARM7 parsing to allow 't' for
- 	thumb/halfword support, aswell as 'm' for long multiply.
+	thumb/halfword support, aswell as 'm' for long multiply.
 	(md_show_usage): Updated help message.
 	(md_assemble): Check that instruction flags are applicated to the
- 	current cpu variant.
+	current cpu variant.
 	(md_apply_fix3, tc_gen_reloc): Add BFD_RELOC_ARM_OFFSET_IMM8 and
- 	BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
- 	signextension instructions.
+	BFD_RELOC_ARM_HWLITERAL relocation support for new halfword and
+	signextension instructions.
 	(do_ldst): Generate halfword and signextension variants if
- 	mnemonic flags match.
+	mnemonic flags match.
 	(ldst_extend): Do not allow shifts in the offset field of halfword
- 	or signextension instructions.
+	or signextension instructions.
 	(validate_offset_imm): Provide check on halfword and signextension
- 	immediate range.
+	immediate range.
 	(add_to_lit_pool): Merge identical literal pool values.
 
 Tue Jul 30 14:28:23 1996  Jeffrey A Law  (law@cygnus.com)
@@ -4298,7 +4298,7 @@ Fri Jul 26 11:43:03 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: Added lots of error checking.  Added hacks
 	to support accumulator shifts.
-	
+
 Fri Jul 26 11:56:08 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* symbols.c (S_SET_EXTERNAL): Let .weak override.
@@ -4315,8 +4315,8 @@ Thu Jul 25 12:03:33 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 	* config/tc-d10v.c: Fix packaging bug. Added range checking.
 	Added kludge for divs instruction.  Fixed minor problem with
 	multiple text sections.
-	* config/tc-d10v.h (d10v_cleanup): Change prototype. 
-	
+	* config/tc-d10v.h (d10v_cleanup): Change prototype.
+
 Tue Jul 23 10:49:36 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c (md_apply_fix3): Fix all instruction
@@ -4325,11 +4325,11 @@ Tue Jul 23 10:49:36 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 Mon Jul 22 11:32:36 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 
 	* config/tc-d10v.c: Many changes to get relocs working.
- 	(register_name): No longer creates a symbol for register names.
- 	(pre_defined_registers): moved to opcodes/d10v-opc.c.
+	(register_name): No longer creates a symbol for register names.
+	(pre_defined_registers): moved to opcodes/d10v-opc.c.
 	(d10v_insert_operand): Now works correctly for either container.
-	* config/tc-d10v.h (d10v_cleanup): Declare. 
-	
+	* config/tc-d10v.h (d10v_cleanup): Declare.
+
 Mon Jul 22 14:01:33 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-mips.c (tc_gen_reloc): BFD_RELOC_PCREL_HI16_S and
@@ -4396,7 +4396,7 @@ Wed Jul 17 14:25:13 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
 	* config/tc-d10v.h: New file.
 	* configure (d10v-*-elf): New target.
 	* configure.in (d10v-*-elf): New target.
-	
+
 Fri Jul 12 20:54:19 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
 
 	* config/tc-ppc.c (md_parse_option): Recognize -K PIC.
@@ -4423,9 +4423,9 @@ Wed Jul 10 00:23:30 1996  Ian Lance Taylor  <ian@cygnus.com>
 Mon Jul  8 14:11:49 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-mips.c (mips_regmask_frag): Only define if OBJ_ELF or
- 	OBJ_MAYBE_ELF.
+	OBJ_MAYBE_ELF.
 	(tc_gen_reloc): If fixup was changed to be PC relative, change
- 	reloc type accordingly.  Use name of reloc in error message.
+	reloc type accordingly.  Use name of reloc in error message.
 
 	* as.h: Don't define const or volatile.
 	* flonum.h: Don't define const.
@@ -4442,7 +4442,7 @@ Fri Jul  5 10:32:58 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 	* doc/as.texinfo: Likewise.
 
 	* config/tc-m68k.c (m68k_ip): The coldfire does not support 8x
- 	scale factor.
+	scale factor.
 
 Fri Jul  5 11:07:24 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -4458,14 +4458,14 @@ Thu Jul  4 11:59:46 1996  Ian Lance Taylor  <ian@cygnus.com>
 Thu Jul  4 10:11:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-mips.c (mips_ip): Only perform range check when
- 	dealing with O_constant expressions.
+	dealing with O_constant expressions.
 
 Wed Jul  3 15:02:21 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* m68k-parse.h (m68k_register): Add new coldfile control
 	registers.
 
-	* config/tc-m68k.c (mcf5200_control_regs): New variable, 
+	* config/tc-m68k.c (mcf5200_control_regs): New variable,
 	array of control registers for the coldfire.
 	(cpu_of_arch): Added mcf5200.
 	(archs): Added mcf5200.
@@ -4499,7 +4499,7 @@ Wed Jul  3 16:05:50 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Tue Jul  2 23:02:12 1996  Jeffrey A Law  (law@cygnus.com)
 
-	* config/tc-h8300.c (build_bytes): If an operand type is 
+	* config/tc-h8300.c (build_bytes): If an operand type is
 	marked as SRC_IN_DST retrieve it from the "destination" op.
 
 Sat Jun 29 13:38:31 1996  Ian Lance Taylor  <ian@cygnus.com>
@@ -4558,7 +4558,7 @@ Wed Jun 26 13:21:34 1996  Ian Lance Taylor  <ian@cygnus.com>
 Wed Jun 26 16:23:08 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-mips.c: Added cop_interlocks, to avoid NOP insertion
- 	between co-processor comparisons and branches for the VR4300.
+	between co-processor comparisons and branches for the VR4300.
 
 Mon Jun 24 18:02:50 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
 
@@ -4710,8 +4710,8 @@ Wed Jun 19 11:31:50 1996  Ian Lance Taylor  <ian@cygnus.com>
 	emit relocations against external symbols.
 
 	* config/tc-alpha.c (tc_gen_reloc): Output a sensible error
- 	message if bfd_reloc_type_lookup fails, rather than calling
- 	assert.
+	message if bfd_reloc_type_lookup fails, rather than calling
+	assert.
 
 	* config/tc-alpha.c (alpha_force_relocation): Add
 	BFD_RELOC_12_PCREL to switch.
@@ -4757,7 +4757,7 @@ Tue Jun 18 13:19:51 1996  Jeffrey A. Law  <law@rtl.cygnus.com>
 Mon Jun 17 15:50:53 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* doc/as.texinfo: Reorder chapter of machine dependent options so
- 	that it is sorted by chip name.  
+	that it is sorted by chip name.
 
 	* doc/as.texinfo: Use consistant spelling of Vax.
 	* doc/c-vax.texi: Likewise.
@@ -4822,7 +4822,7 @@ Mon Jun 10 11:45:51 1996  Ian Lance Taylor  <ian@cygnus.com>
 	flag for C_MOS, C_MOE, C_MOU, or C_EOS symbols, since they should
 	have a section of N_ABS rather than N_DEBUG.  If we do a merge,
 	remove the new symbol from the list.
- 	(obj_coff_endef, both versions): Call tag_insert even if there is
+	(obj_coff_endef, both versions): Call tag_insert even if there is
 	an old symbol with the same name, if the old symbol does not
 	happen to be a tag.
 	(coff_frob_symbol): Check SF_GET_TAG, C_EOF, and C_FILE outside of
@@ -4839,7 +4839,7 @@ Mon Jun 10 11:45:51 1996  Ian Lance Taylor  <ian@cygnus.com>
 	defined.
 
 	* app.c (do_scrub_chars): If '/' is LINE_COMMENT_START, check
- 	whether the next character is '*' before checking whether we are
+	whether the next character is '*' before checking whether we are
 	at the start of a line.  Permit LINE_COMMENT_START to start a
 	comment in state 1 (seen some whitespace) as well, to match the
 	documentation.
@@ -4948,7 +4948,7 @@ Thu May 16 15:51:48 1996  Ian Lance Taylor  <ian@cygnus.com>
 	(sh_flush_pending_output): Declare.
 	(md_flush_pending_output): Define.
 	* config/tc-sh.c (md_assemble): If relaxing, emit a R_SH_CODE
- 	reloc before the instruction if necessary.
+	reloc before the instruction if necessary.
 	(sh_frob_label): New function.
 	(sh_flush_pending_output): New function.
 	(sh_coff_frob_file): Ignore ALIGN, CODE, DATA, and LABEL relocs
@@ -4971,7 +4971,7 @@ Wed May 15 12:23:53 1996  Ian Lance Taylor  <ian@cygnus.com>
 Wed May 15 08:33:37 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* config/obj-coff.c (count_entries_in_chain): Ignore Fixups with
-	fx_done set. 
+	fx_done set.
 	(do_relocs_for): Likewise.
 	(fixup_segment): Don't just quit if linkrelax is set.  Try to
 	apply non pc-relative sym1-sym2 fixups, even if linkrelax is
@@ -5018,7 +5018,7 @@ Sat May  4 12:49:35 1996  Jeffrey A Law  (law@cygnus.com)
 Sat May  4 11:26:19 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* Makefile.in: Add subsegs.h to appropriate TARG_CPU_DEP_*
- 	variables.
+	variables.
 
 Fri May  3 17:58:31 1996  Ian Lance Taylor  <ian@cygnus.com>
 
@@ -5068,7 +5068,7 @@ Thu Apr 25 11:39:51 1996  Ian Lance Taylor  <ian@cygnus.com>
 Wed Apr 24 11:28:38 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/tc-m68k.c (m68k_ip): Prevent attempts to use long offsets
- 	in 68000 mode.
+	in 68000 mode.
 
 	* config/obj-coff.c (obj_coff_section): BFD_ASSEMBLER version:
 	call demand_empty_rest_of_line.  Non BFD_ASSEMBLER version:
@@ -5087,7 +5087,7 @@ Mon Apr 22 18:02:37 1996  Doug Evans  <dje@blues.cygnus.com>
 Thu Apr 18 18:58:33 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* config/obj-coff.c: BFD_ASSEMBLER:
- 	(coff_last_bf): New static variable.
+	(coff_last_bf): New static variable.
 	(coff_frob_symbol): Set endndx of a .bf symbol.
 	Non BFD_ASSEMBLER:
 	(obj_coff_endef): Call SF_SET_PROCESS on a .bf symbol.
@@ -5185,7 +5185,7 @@ Fri Apr  5 14:29:23 1996  Ian Lance Taylor  <ian@cygnus.com>
 Fri Apr  5 18:39:28 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* config/tc-mips.c: Allow non-zero offsets from .sdata symbols to
- 	be accessed using the $gp register.
+	be accessed using the $gp register.
 	* config/tc-mips.h (MAX_GPREL_OFFSET): Added.
 
 Wed Apr  3 10:56:14 1996  Doug Evans  <dje@canuck.cygnus.com>
@@ -5324,7 +5324,7 @@ Mon Mar 11 09:59:53 1996  Steve Chamberlain  <sac@slash.cygnus.com>
 	(do_relocs_for, w_symbols, obj_coff_add_segment, do_linenos_for,
 	crawl_symbols, coff_header_append): Loop to SEG_LAST rather than
 	SEG_E9.
-	
+
 Thu Mar  7 15:17:39 1996  Doug Evans  <dje@charmed.cygnus.com>
 
 	* config/tc-sparc.c (sparc_ip): Handle operand char 'O' (neg reg).
@@ -5464,7 +5464,7 @@ Mon Feb 19 02:15:57 1996  Doug Evans  <dje@charmed.cygnus.com>
 Sun Feb 18 15:03:50 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* configure.in: Check for 'do not mix' from native linker before
- 	trying to use -rpath.
+	trying to use -rpath.
 	* configure: Rebuild.
 
 Fri Feb 16 16:53:31 1996  Ian Lance Taylor  <ian@cygnus.com>
@@ -5585,7 +5585,7 @@ Mon Feb 12 15:16:29 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.
 	(NO_RELOC): Define to BFD_RELOC_NONE if BFD_ASSEMBLER, to zero
 	otherwise.
 	* config/tc-m68k.c: Delete definition of NO_RELOC.
- 	(struct m68k_it): Add pic_reloc field.
+	(struct m68k_it): Add pic_reloc field.
 	(add_fix): Copy over pic_reloc field.
 	(md_pseudo_table): Interpret .align parameter as byte count.
 	(mote_pseudo_table): Likewise.
@@ -5599,7 +5599,7 @@ Mon Feb 12 15:16:29 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.
 	(md_begin): Align .text, .data and .bss on 4 byte boundary by
 	default.
 	* write.c (fixup_segment): Don't add symbol value to addend if
- 	TC_M68K and OBJ_ELF.
+	TC_M68K and OBJ_ELF.
 	* config/m68k-parse.y (yylex): Handle @PLTPC, etc.
 	(motorola_operand): Add rule for `(zapc, EXPR)'.
 
@@ -5809,7 +5809,7 @@ Mon Jan 29 12:21:30 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 Fri Jan 26 19:28:52 1996  Kim Knuttila  <krk@cygnus.com>
 
-	* config/tc-ppc.c (md_assemble): Ignore overflow on 
+	* config/tc-ppc.c (md_assemble): Ignore overflow on
 	BFD_RELOC_16_GOTOFF and BFD_RELOC_PPC_TOC16.
 
 Fri Jan 26 16:14:17 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
@@ -5957,3 +5957,10 @@ Tue Jan  2 12:43:23 1996  Jim Wilson  <wilson@chestnut.cygnus.com>
 	not alphanumeric.
 
 For older changes see ChangeLog-9295
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/ChangeLog-9899 b/gas/ChangeLog-9899
index c2e4d897aa0a..ae38e5dd9223 100644
--- a/gas/ChangeLog-9899
+++ b/gas/ChangeLog-9899
@@ -4858,3 +4858,10 @@ Fri Jan  2 16:08:54 1998  Ian Lance Taylor  <ian@cygnus.com>
 	unrecognized characters after an expression.
 
 For older changes see ChangeLog-9697
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/Makefile.am b/gas/Makefile.am
index 7728434af210..08b9842fc6be 100644
--- a/gas/Makefile.am
+++ b/gas/Makefile.am
@@ -16,6 +16,7 @@ YACC = `if [ -f ../bison/bison ] ; then echo ../bison/bison -y -L../bison/bison
 LEX = `if [ -f ../flex/flex ] ; then echo ../flex/flex ; else echo @LEX@ ; fi`
 
 WARN_CFLAGS = @WARN_CFLAGS@
+NO_WERROR = @NO_WERROR@
 AM_CFLAGS = $(WARN_CFLAGS)
 
 MKDEP = gcc -MM
@@ -40,19 +41,19 @@ IT_OBJS=itbl-parse.o itbl-lex.o itbl-ops.o
 # CPU types.  This is only used for dependency information.
 
 CPU_TYPES = \
-	a29k \
 	alpha \
 	arc \
 	arm \
 	avr \
+	bfin \
 	cris \
+	crx \
 	d10v \
 	d30v \
 	dlx \
 	fr30 \
 	frv \
 	h8300 \
-	h8500 \
 	hppa \
 	ia64 \
 	i370 \
@@ -60,10 +61,10 @@ CPU_TYPES = \
 	i860 \
 	i960 \
 	ip2k \
+	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
-	m88k \
 	mcore \
 	mips \
 	mmix \
@@ -80,16 +81,15 @@ CPU_TYPES = \
 	sh \
 	sh64 \
 	sparc \
-	tahoe \
 	tic30 \
 	tic4x \
 	tic54x \
-	tic80 \
 	vax \
-	w65 \
 	v850 \
 	xstormy16 \
+	xc16x \
 	xtensa \
+	z80 \
 	z8k
 
 # Object format types.  This is only used for dependency information.
@@ -97,14 +97,11 @@ CPU_TYPES = \
 
 OBJ_FORMATS = \
 	aout \
-	bout \
 	coff \
 	ecoff \
 	elf \
 	evax \
-	hp300 \
-	ieee \
-	vms
+	ieee
 
 # This is an sh case which sets valid according to whether the CPU
 # type in the shell variable c and the OS type in the shell variable o
@@ -116,13 +113,9 @@ CPU_OBJ_VALID = \
 	case $$o in \
 	aout) \
 	  case $$c in \
-	  a29k | arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tahoe | tic30 | vax) \
+	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	bout) \
-	  case $$c in \
-	  i960) valid=yes ;; \
-	  esac ;; \
 	coff) valid=yes; \
 	  case $$c in \
 	  cris | i860 | mmix | sh64) \
@@ -137,10 +130,6 @@ CPU_OBJ_VALID = \
 	  case $$c in \
 	  alpha) valid=yes ;; \
 	  esac ;; \
-	hp300) \
-	  case $$c in \
-	  m68k) valid=yes ;; \
-	  esac ;; \
 	vms) \
 	  case $$c in \
 	  vax) valid=yes ;; \
@@ -175,7 +164,6 @@ GAS_CFILES = \
 	app.c \
 	as.c \
 	atof-generic.c \
-	bignum-copy.c \
 	cond.c \
 	depend.c \
 	dwarf2dbg.c \
@@ -220,6 +208,7 @@ HFILES = \
 	frags.h \
 	hash.h \
 	input-file.h \
+	itbl-lex.h \
 	itbl-ops.h \
 	listing.h \
 	macro.h \
@@ -236,19 +225,19 @@ HFILES = \
 # CPU files in config.
 
 TARGET_CPU_CFILES = \
-	config/tc-a29k.c \
 	config/tc-alpha.c \
 	config/tc-arc.c \
 	config/tc-arm.c \
 	config/tc-avr.c \
+	config/tc-bfin.c \
 	config/tc-cris.c \
+	config/tc-crx.c \
 	config/tc-d10v.c \
 	config/tc-d30v.c \
 	config/tc-dlx.c \
 	config/tc-fr30.c \
 	config/tc-frv.c \
 	config/tc-h8300.c \
-	config/tc-h8500.c \
 	config/tc-hppa.c \
 	config/tc-ia64.c \
 	config/tc-i370.c \
@@ -256,10 +245,10 @@ TARGET_CPU_CFILES = \
 	config/tc-i860.c \
 	config/tc-i960.c \
 	config/tc-ip2k.c \
+	config/tc-m32c.c \
 	config/tc-m32r.c \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
-	config/tc-m88k.c \
 	config/tc-mcore.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
@@ -276,31 +265,30 @@ TARGET_CPU_CFILES = \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
-	config/tc-tahoe.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
-	config/tc-tic80.c \
 	config/tc-vax.c \
-	config/tc-w65.c \
 	config/tc-v850.c \
 	config/tc-xstormy16.c \
+	config/tc-xc16x.c \
 	config/tc-xtensa.c \
+	config/tc-z80.c \
 	config/tc-z8k.c
 
 TARGET_CPU_HFILES = \
-	config/tc-a29k.h \
 	config/tc-alpha.h \
 	config/tc-arc.h \
 	config/tc-arm.h \
 	config/tc-avr.h \
+	config/tc-bfin.h \
 	config/tc-cris.h \
+	config/tc-crx.h \
 	config/tc-d10v.h \
 	config/tc-d30v.h \
 	config/tc-dlx.h \
 	config/tc-fr30.h \
 	config/tc-frv.h \
 	config/tc-h8300.h \
-	config/tc-h8500.h \
 	config/tc-hppa.h \
 	config/tc-ia64.h \
 	config/tc-i370.h \
@@ -308,10 +296,10 @@ TARGET_CPU_HFILES = \
 	config/tc-i860.h \
 	config/tc-i960.h \
 	config/tc-ip2k.h \
+	config/tc-m32c.h \
 	config/tc-m32r.h \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
-	config/tc-m88k.h \
 	config/tc-mcore.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
@@ -328,47 +316,41 @@ TARGET_CPU_HFILES = \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
-	config/tc-tahoe.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
-	config/tc-tic80.h \
 	config/tc-vax.h \
-	config/tc-w65.h \
 	config/tc-v850.h \
 	config/tc-xstormy16.h \
+	config/tc-xc16x.h \
 	config/tc-xtensa.h \
+	config/tc-z80.h \
 	config/tc-z8k.h
 
 # OBJ files in config
 
 OBJ_FORMAT_CFILES = \
 	config/obj-aout.c \
-	config/obj-bout.c \
 	config/obj-coff.c \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-hp300.c \
 	config/obj-ieee.c \
-	config/obj-som.c \
-	config/obj-vms.c
+	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
 	config/obj-aout.h \
-	config/obj-bout.h \
 	config/obj-coff.h \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-hp300.h \
 	config/obj-ieee.h \
-	config/obj-som.h \
-	config/obj-vms.h
+	config/obj-som.h
 
 # Emulation header files in config
 
 TARG_ENV_HFILES = \
 	config/te-386bsd.h \
+	config/te-armlinuxeabi.h \
 	config/te-aux.h \
 	config/te-delta.h \
 	config/te-delt88.h \
@@ -377,7 +359,6 @@ TARG_ENV_HFILES = \
 	config/te-epoc-pe.h \
 	config/te-generic.h \
 	config/te-go32.h \
-	config/te-hp300.h \
 	config/te-hppa.h \
 	config/te-hppa64.h \
 	config/te-hppalinux64.h \
@@ -391,15 +372,15 @@ TARG_ENV_HFILES = \
 	config/te-macos.h \
 	config/te-nbsd.h \
 	config/te-nbsd532.h \
+	config/te-netware.h \
 	config/te-pc532mach.h \
 	config/te-pe.h \
-	config/te-ppcnw.h \
 	config/te-psos.h \
 	config/te-riscix.h \
 	config/te-sparcaout.h \
 	config/te-sun3.h \
 	config/te-svr4.h \
-	config/te-sysv32.h \
+	config/te-symbian.h \
 	config/te-tmips.h
 
 # Multi files in config
@@ -423,7 +404,6 @@ GENERIC_OBJS = \
 	app.o \
 	as.o \
 	atof-generic.o \
-	bignum-copy.o \
 	cond.o \
 	depend.o \
 	dwarf2dbg.o \
@@ -454,7 +434,7 @@ OBJS = $(CONFIG_OBJS) $(GENERIC_OBJS)
 
 POTFILES = $(MULTI_CFILES) $(TARGET_ENV_HFILES) $(OBJ_FORMAT_HFILES) \
 	$(OBJ_FORMAT_CFILES) $(TARGET_CPU_HFILES) $(TARGET_CPU_CFILES) \
-	$(HFILES) $(CFILES) $(GAS_CFILES)
+	$(HFILES) $(CFILES)
 po/POTFILES.in: @MAINT@ Makefile
 	for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \
 	  && mv tmp $(srcdir)/po/POTFILES.in
@@ -465,14 +445,11 @@ noinst_PROGRAMS = as-new
 noinst_SCRIPTS = $(GDBINIT)
 EXTRA_SCRIPTS = .gdbinit
 
-$(srcdir)/make-gas.com: stamp-mk.com
-stamp-mk.com: vmsconf.sh Makefile
-	sh $(srcdir)/vmsconf.sh $(GENERIC_OBJS) > new-make.com
-	$(SHELL) $(srcdir)/../move-if-change new-make.com $(srcdir)/make-gas.com
-	touch stamp-mk.com
+EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \
+	bfin-parse.c bfin-parse.h bfin-lex.c
 
-EXTRA_DIST = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
 diststuff: $(EXTRA_DIST) info
+all: info
 
 DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h
 
@@ -487,15 +464,15 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(prefix)/share/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(prefix)/share/locale\""
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
 
-DEP_FLAGS = -DBFD_ASSEMBLER -DOBJ_MAYBE_ELF \
+DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
 
 # How to link with both our special library facilities
@@ -524,13 +501,8 @@ $(OBJS): $(INCDIR)/bin-bugs.h $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \
 	as.h asintl.h bignum.h bit_fix.h config.h emul.h expr.h flonum.h \
 	frags.h hash.h listing.h obj.h read.h symbols.h tc.h write.h
 
-EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \
-          echo $${rootme}/../expect/expect ; \
-          else echo expect ; fi`
-
-RUNTEST = `if [ -f $${srcdir}/../dejagnu/runtest ] ; then \
-		echo $${srcdir}/../dejagnu/runtest ; else echo runtest; \
-	   fi`
+EXPECT = expect
+RUNTEST = runtest
 RUNTESTFLAGS=
 
 check-DEJAGNU: site.exp
@@ -544,10 +516,6 @@ check-DEJAGNU: site.exp
 	rootme=`pwd`; export rootme; \
 	srcdir=`cd ${srcdir}; pwd` ; export srcdir ; \
 	EXPECT=${EXPECT} ; export EXPECT ; \
-	if [ -f $(top_builddir)/../expect/expect ]; then \
-	  TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \
-	  export TCL_LIBRARY; \
-	fi; \
 	runtest=$(RUNTEST); \
 	cd testsuite; \
 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
@@ -574,8 +542,6 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 
 obj-aout.o : $(srcdir)/config/obj-aout.c
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-bout.o : $(srcdir)/config/obj-bout.c
-	$(COMPILE) -c $(srcdir)/config/obj-bout.c
 obj-coff.o: $(srcdir)/config/obj-coff.c
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
 obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
@@ -584,16 +550,12 @@ obj-elf.o : $(srcdir)/config/obj-elf.c
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-hp300.o : $(srcdir)/config/obj-hp300.c
-	$(COMPILE) -c $(srcdir)/config/obj-hp300.c
 obj-ieee.o : $(srcdir)/config/obj-ieee.c
 	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
 	$(COMPILE) -c $(srcdir)/config/obj-som.c
-obj-vms.o : $(srcdir)/config/obj-vms.c
-	$(COMPILE) -c $(srcdir)/config/obj-vms.c
 
 e-mipself.o : $(srcdir)/config/e-mipself.c
 	$(COMPILE) -c $(srcdir)/config/e-mipself.c
@@ -615,7 +577,7 @@ xtensa-relax.o: $(srcdir)/config/xtensa-relax.c
 
 # The m68k operand parser.
 
-EXTRA_as_new_SOURCES = config/m68k-parse.y
+EXTRA_as_new_SOURCES = config/m68k-parse.y config/bfin-parse.y
 
 # If m68k-parse.y is in a different directory, then ylwrap will use an
 # absolute path when it invokes yacc, which will cause yacc to put the
@@ -635,27 +597,51 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	   cp config/m68k-parse.y . >/dev/null 2>/dev/null; \
 	  f=m68k-parse.y; \
 	else true; fi; \
-	$(SHELL) $(YLWRAP) "$(YACC)" $$f y.tab.c m68k-parse.c --; \
+	$(SHELL) $(YLWRAP) $$f y.tab.c m68k-parse.c -- $(YACCCOMPILE); \
 	if [ $$f = "m68k-parse.y" ]; then \
 	  rm -f m68k-parse.y; \
 	else true; fi
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
+	$(COMPILE) -c $< $(NO_WERROR)
 
 # Don't let the .y.h rule clobber m68k-parse.h.
 m68k-parse.h: ; @true
 $(srcdir)/config/m68k-parse.h: ; @true
 
+bfin-parse.c: $(srcdir)/config/bfin-parse.y
+	$(SHELL) $(YLWRAP) $(srcdir)/config/bfin-parse.y y.tab.c bfin-parse.c y.tab.h bfin-parse.h -- $(YACCCOMPILE) -d ;
+bfin-parse.h: bfin-parse.c
+bfin-parse.o: bfin-parse.c bfin-parse.h $(srcdir)/config/bfin-defs.h \
+ $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
+
+bfin-defs.h: ; @true
+$(srcdir)/config/bfin-defs.h: ; @true
+
+bfin-lex.c: $(srcdir)/config/bfin-lex.l
+	$(SHELL) $(YLWRAP) $(srcdir)/config/bfin-lex.l lex.yy.c bfin-lex.c -- $(LEXCOMPILE)
+bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
+	$(COMPILE) -c $< $(NO_WERROR)
+
 # The instruction table specification lexical analyzer and parser.
 
 itbl-lex.c: $(srcdir)/itbl-lex.l
-itbl-lex.o: itbl-lex.c itbl-parse.h
 
-itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
+itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
+	$(COMPILE) -c $< $(NO_WERROR)
+
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
+itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
+	$(COMPILE) -c $< $(NO_WERROR)
 
 itbl-ops.o: $(srcdir)/itbl-ops.c $(srcdir)/itbl-ops.h itbl-parse.h
 
 itbl-parse.c itbl-parse.h: $(srcdir)/itbl-parse.y
-	$(SHELL) $(YLWRAP) "$(YACC)" $(srcdir)/itbl-parse.y y.tab.c itbl-parse.c y.tab.h itbl-parse.h -- -d
+	$(SHELL) $(YLWRAP) $(srcdir)/itbl-parse.y y.tab.c itbl-parse.c y.tab.h itbl-parse.h -- $(YACCCOMPILE) -d
 
 # stand-alone itbl assembler & disassembler
 
@@ -680,12 +666,41 @@ cgen.o: cgen.c cgen.h cgen-desc.h subsegs.h \
 
 # Remake the info files.
 
-MOSTLYCLEANFILES = $(STAGESTUFF) core stamp-mk.com \
+MOSTLYCLEANFILES = $(STAGESTUFF) core \
 	testsuite/*.o testsuite/*.out testsuite/gas.log testsuite/gas.sum \
 	testsuite/site.exp site.bak site.exp stage stage1 stage2
 
 CLEANFILES = dep.sed DEPTC DEPTCA DEPOBJ DEPOBJA DEP2 DEP2A DEP1 DEPA DEP DEPDIR
 
+.PHONY: install-html install-html-am install-html-recursive
+
+install-html:	install-html-recursive
+
+install-html-recursive:
+	@failcom='exit 1'; \
+	for f in x $$MAKEFLAGS; do \
+	  case $$f in \
+	    *=* | --[!k]*);; \
+	    *k*) failcom='fail=yes';; \
+	  esac; \
+	done; \
+	dot_seen=no; \
+	target=`echo $@ | sed s/-recursive//`; \
+	list='$(SUBDIRS)'; for subdir in $$list; do \
+	  echo "Making $$target in $$subdir"; \
+	  if test "$$subdir" = "."; then \
+	    dot_seen=yes; \
+	    local_target="$$target-am"; \
+	  else \
+	    local_target="$$target"; \
+	  fi; \
+	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+	  || eval $$failcom; \
+	done; \
+	if test "$$dot_seen" = "no"; then \
+	  $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+	fi; test -z "$$fail"
+
 .PHONY: install-exec-local install-data-local
 .PHONY: install-exec-bindir install-exec-tooldir
 
@@ -791,7 +806,7 @@ de-stage3:
 DEP_FILE_DEPS =  $(CFILES) $(HFILES) $(TARGET_CPU_CFILES) \
 	$(TARGET_CPU_HFILES) $(OBJ_FORMAT_CFILES) $(OBJ_FORMAT_HFILES)
 
-CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt
 
 # Automatic dependency computation.  This is a real pain, because the
 # dependencies change based on target_cpu_type and obj_format.
@@ -973,27 +988,16 @@ dep-am: DEP
 .PHONY: dep dep-in dep-am
 
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_a29k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-a29k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
-DEPTC_a29k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-a29k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/a29k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
-DEPTC_a29k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
 DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
   $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
   $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-alpha.h \
@@ -1004,8 +1008,8 @@ DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(srcdir)/config/atof-vax.c
 DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
   $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
@@ -1015,22 +1019,24 @@ DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
+  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/arm.h
 DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
+  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
 DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1038,8 +1044,24 @@ DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/avr.h
+DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
+  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
+DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
+  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
 DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
@@ -1047,8 +1069,18 @@ DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
 DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h dwarf2dbg.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/cris.h
+DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
+  $(INCDIR)/elf/reloc-macros.h
+DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+  $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1075,31 +1107,34 @@ DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
+  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
 DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
 DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
+  cgen.h
 DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+  cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
-  cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/h8300.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1108,18 +1143,8 @@ DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_h8500_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8500.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8500.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/h8500-opc.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_h8500_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/h8500-opc.h \
-  $(INCDIR)/safe-ctype.h
 DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1148,32 +1173,31 @@ DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
 DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h
+  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_i960_bout = $(INCDIR)/symcat.h $(srcdir)/config/obj-bout.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/i960.h
 DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1181,32 +1205,54 @@ DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/i960.h
 DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h
+  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/libbfd.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
+DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
 DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
+  $(INCDIR)/elf/reloc-macros.h
 DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32r-opc.h cgen.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
+  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1216,8 +1262,8 @@ DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
 DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1237,21 +1283,6 @@ DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
-DEPTC_m68k_hp300 = $(INCDIR)/symcat.h $(srcdir)/config/obj-hp300.h \
-  $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
-DEPTC_m88k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m88k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m88k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(srcdir)/config/m88k-opcode.h
-DEPTC_m88k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/config/m88k-opcode.h
 DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1260,43 +1291,38 @@ DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
-DEPTC_mips_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-mips.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
+  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
   $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
   $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
-  dwarf2dbg.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
+  $(INCDIR)/elf/reloc-macros.h
 DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h
+  $(INCDIR)/safe-ctype.h
 DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1304,7 +1330,7 @@ DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
 DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
@@ -1314,16 +1340,16 @@ DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h
 DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
 DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
   $(INCDIR)/safe-ctype.h
 DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1335,18 +1361,19 @@ DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
 DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
+  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
 DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
 DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h \
@@ -1355,7 +1382,7 @@ DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/opcode/or32.h \
+  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
   $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1367,7 +1394,7 @@ DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
 DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1375,7 +1402,7 @@ DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
 DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1384,9 +1411,9 @@ DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -1396,27 +1423,30 @@ DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
+  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h
+  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h
 DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
   $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h
 DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh64.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
   $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h dw2gencfi.h
+  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
@@ -1430,21 +1460,9 @@ DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h
-DEPTC_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
-DEPTC_tahoe_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tahoe.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
-DEPTC_tahoe_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
 DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
@@ -1455,7 +1473,7 @@ DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
 DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h \
@@ -1464,7 +1482,7 @@ DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/opcode/tic4x.h \
+  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
   subsegs.h $(INCDIR)/obstack.h
 DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
@@ -1478,42 +1496,21 @@ DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   struc-symbol.h $(INCDIR)/opcode/tic54x.h $(srcdir)/config/obj-coff.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h
-DEPTC_tic80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic80.h
-DEPTC_tic80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic80.h
 DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/opcode/vax.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
 DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/vax.h
 DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/elf/vax.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_vax_vms = $(INCDIR)/symcat.h $(srcdir)/config/obj-vms.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
-DEPTC_w65_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-w65.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/w65.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/w65-opc.h
-DEPTC_w65_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/w65-opc.h
+  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
 DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1522,27 +1519,43 @@ DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
-  dwarf2dbg.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/v850.h
 DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
+  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
 DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
+DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
 DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/xtensa-relax.h \
-  $(INCDIR)/xtensa-isa.h $(srcdir)/config/xtensa-istack.h \
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
   dwarf2dbg.h struc-symbol.h
+DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h
+DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
 DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1550,7 +1563,7 @@ DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
   $(BFDDIR)/som.h
@@ -1559,18 +1572,6 @@ DEPTC_i386_multi = $(DEPTC_i386_aout) $(DEPTC_i386_coff) \
 DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_a29k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-a29k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_a29k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-a29k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/a29k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_a29k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1595,8 +1596,8 @@ DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -1616,16 +1617,34 @@ DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
 DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1651,8 +1670,8 @@ DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1660,8 +1679,8 @@ DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1678,17 +1697,8 @@ DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_h8500_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8500.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8500.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_h8500_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1718,8 +1728,8 @@ DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1731,15 +1741,14 @@ DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/aout/aout64.h
 DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_i960_bout = $(INCDIR)/symcat.h $(srcdir)/config/obj-bout.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1747,8 +1756,8 @@ DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1756,8 +1765,17 @@ DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1765,8 +1783,8 @@ DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/m68k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1774,8 +1792,8 @@ DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -1788,19 +1806,6 @@ DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_m68k_hp300 = $(srcdir)/config/obj-aout.c $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/obstack.h
-DEPOBJ_m88k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m88k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m88k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_m88k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1808,11 +1813,8 @@ DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_mips_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-mips.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1831,8 +1833,8 @@ DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
 DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1840,8 +1842,8 @@ DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1849,8 +1851,8 @@ DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1858,8 +1860,8 @@ DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -1870,8 +1872,8 @@ DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1879,8 +1881,8 @@ DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/or32.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1888,8 +1890,8 @@ DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -1900,8 +1902,8 @@ DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1909,8 +1911,8 @@ DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/rs6000.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1918,8 +1920,8 @@ DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
@@ -1928,8 +1930,8 @@ DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1955,20 +1957,8 @@ DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-DEPOBJ_tahoe_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tahoe.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-DEPOBJ_tahoe_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -1979,8 +1969,8 @@ DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/tic4x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
@@ -1988,8 +1978,8 @@ DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h \
@@ -1999,15 +1989,6 @@ DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_tic80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_tic80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -2018,21 +1999,8 @@ DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-DEPOBJ_vax_vms = $(INCDIR)/symcat.h $(srcdir)/config/obj-vms.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-DEPOBJ_w65_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-w65.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/w65.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-DEPOBJ_w65_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -2040,9 +2008,9 @@ DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -2050,13 +2018,28 @@ DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
+  $(INCDIR)/aout/aout64.h
+DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -2064,8 +2047,8 @@ DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
   $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
@@ -2074,14 +2057,6 @@ DEPOBJ_i386_multi = $(DEPOBJ_i386_aout) $(DEPOBJ_i386_coff) \
 DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_a29k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-a29k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_a29k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/a29k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_a29k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h
 DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
@@ -2096,7 +2071,8 @@ DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
   $(INCDIR)/bfdlink.h
 DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
+  dwarf2dbg.h
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_arm_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arm.h \
@@ -2110,12 +2086,28 @@ DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
   $(INCDIR)/bfdlink.h
 DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
+  dwarf2dbg.h
+DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
+  dwarf2dbg.h
+DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h
 DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
@@ -2133,13 +2125,15 @@ DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
   $(INCDIR)/bfdlink.h
 DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h
 DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
+  dwarf2dbg.h
 DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
@@ -2151,13 +2145,8 @@ DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h
-DEP_h8500_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8500.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8500.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_h8500_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
+  dwarf2dbg.h
 DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
@@ -2179,7 +2168,8 @@ DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
   $(INCDIR)/bfdlink.h
 DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
+  dwarf2dbg.h
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
@@ -2187,35 +2177,47 @@ DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
+  dwarf2dbg.h
 DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h
-DEP_i960_bout = $(srcdir)/config/obj-bout.h $(srcdir)/config/tc-i960.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
+  dwarf2dbg.h
 DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
+  dwarf2dbg.h
 DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
+  dwarf2dbg.h
+DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h
 DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
+  dwarf2dbg.h
 DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
+  dwarf2dbg.h
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
@@ -2224,22 +2226,13 @@ DEP_m68k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68k.h \
 DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
-DEP_m68k_hp300 = $(srcdir)/config/obj-hp300.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_m88k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m88k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_m88k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h
-DEP_mips_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-mips.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
+  dwarf2dbg.h
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
@@ -2250,25 +2243,29 @@ DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h
 DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
+  dwarf2dbg.h
 DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
+  dwarf2dbg.h
 DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
+  dwarf2dbg.h
 DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
+  dwarf2dbg.h
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
@@ -2276,19 +2273,22 @@ DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
   $(INCDIR)/bfdlink.h
 DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
+  dwarf2dbg.h
 DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
@@ -2296,25 +2296,29 @@ DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
   $(INCDIR)/bfdlink.h
 DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
+  dwarf2dbg.h
 DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
+  dwarf2dbg.h
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
+  dwarf2dbg.h
 DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
+  dwarf2dbg.h
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
@@ -2333,15 +2337,8 @@ DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h
-DEP_tahoe_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tahoe.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-DEP_tahoe_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-DEP_tahoe_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
+  dwarf2dbg.h
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
@@ -2349,25 +2346,21 @@ DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
+  dwarf2dbg.h
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
   $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
+  dwarf2dbg.h
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
   $(INCDIR)/coff/ti.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
-DEP_tic80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_tic80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
@@ -2375,38 +2368,43 @@ DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
   $(INCDIR)/bfdlink.h
 DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h
-DEP_vax_vms = $(srcdir)/config/obj-vms.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-DEP_w65_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-w65.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/w65.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-DEP_w65_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
+  dwarf2dbg.h
 DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
   $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
   $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
 DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
 DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
+  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
+  dwarf2dbg.h
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
   $(DEP_i386_elf)
@@ -2420,11 +2418,10 @@ as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
   output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
 atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-bignum-copy.o: bignum-copy.c $(INCDIR)/symcat.h
 cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
 depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h dwarf2dbg.h \
-  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
 dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h
@@ -2446,13 +2443,14 @@ input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
 listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h input-file.h subsegs.h
 literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h
 messages.o: messages.c $(INCDIR)/symcat.h
 output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
 read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h
+sb.o: sb.c sb.h $(INCDIR)/symcat.h
 stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
   subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
 subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
diff --git a/gas/Makefile.in b/gas/Makefile.in
index 67ed432b303e..4cc485f9683a 100644
--- a/gas/Makefile.in
+++ b/gas/Makefile.in
@@ -1,8 +1,8 @@
-# Makefile.in generated by automake 1.8.4 from Makefile.am.
+# Makefile.in generated by automake 1.9.6 from Makefile.am.
 # @configure_input@
 
 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-# 2003, 2004  Free Software Foundation, Inc.
+# 2003, 2004, 2005  Free Software Foundation, Inc.
 # This Makefile.in is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
 # with or without modifications, as long as this notice is preserved.
@@ -15,8 +15,6 @@
 @SET_MAKE@
 
 
-SOURCES = $(as_new_SOURCES) $(EXTRA_as_new_SOURCES) $(itbl_test_SOURCES)
-
 srcdir = @srcdir@
 top_srcdir = @top_srcdir@
 VPATH = @srcdir@
@@ -47,14 +45,15 @@ DIST_COMMON = $(srcdir)/../config.guess $(srcdir)/../config.sub NEWS \
 	$(top_srcdir)/configure $(am__configure_deps) \
 	$(srcdir)/config.in $(srcdir)/../mkinstalldirs \
 	$(srcdir)/gdbinit.in $(srcdir)/gdbinit.in \
-	$(top_srcdir)/po/Make-in m68k-parse.c itbl-parse.c itbl-lex.c \
-	$(srcdir)/../ylwrap $(srcdir)/../ltmain.sh \
-	$(srcdir)/../config.guess $(srcdir)/../config.sub
+	$(top_srcdir)/po/Make-in m68k-parse.c bfin-parse.c \
+	itbl-parse.c itbl-lex.c $(srcdir)/../ylwrap \
+	$(srcdir)/../ltmain.sh $(srcdir)/../config.guess \
+	$(srcdir)/../config.sub
 subdir = .
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../gettext.m4 \
-	$(top_srcdir)/configure.in
+	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
+	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
@@ -64,15 +63,15 @@ CONFIG_HEADER = config.h
 CONFIG_CLEAN_FILES = gdb.ini .gdbinit po/Makefile.in
 PROGRAMS = $(noinst_PROGRAMS)
 am__objects_1 = app.$(OBJEXT) as.$(OBJEXT) atof-generic.$(OBJEXT) \
-	bignum-copy.$(OBJEXT) cond.$(OBJEXT) depend.$(OBJEXT) \
-	dwarf2dbg.$(OBJEXT) dw2gencfi.$(OBJEXT) ecoff.$(OBJEXT) \
-	ehopt.$(OBJEXT) expr.$(OBJEXT) flonum-copy.$(OBJEXT) \
-	flonum-konst.$(OBJEXT) flonum-mult.$(OBJEXT) frags.$(OBJEXT) \
-	hash.$(OBJEXT) input-file.$(OBJEXT) input-scrub.$(OBJEXT) \
-	listing.$(OBJEXT) literal.$(OBJEXT) macro.$(OBJEXT) \
-	messages.$(OBJEXT) output-file.$(OBJEXT) read.$(OBJEXT) \
-	sb.$(OBJEXT) stabs.$(OBJEXT) subsegs.$(OBJEXT) \
-	symbols.$(OBJEXT) write.$(OBJEXT)
+	cond.$(OBJEXT) depend.$(OBJEXT) dwarf2dbg.$(OBJEXT) \
+	dw2gencfi.$(OBJEXT) ecoff.$(OBJEXT) ehopt.$(OBJEXT) \
+	expr.$(OBJEXT) flonum-copy.$(OBJEXT) flonum-konst.$(OBJEXT) \
+	flonum-mult.$(OBJEXT) frags.$(OBJEXT) hash.$(OBJEXT) \
+	input-file.$(OBJEXT) input-scrub.$(OBJEXT) listing.$(OBJEXT) \
+	literal.$(OBJEXT) macro.$(OBJEXT) messages.$(OBJEXT) \
+	output-file.$(OBJEXT) read.$(OBJEXT) sb.$(OBJEXT) \
+	stabs.$(OBJEXT) subsegs.$(OBJEXT) symbols.$(OBJEXT) \
+	write.$(OBJEXT)
 am_as_new_OBJECTS = $(am__objects_1)
 as_new_OBJECTS = $(am_as_new_OBJECTS)
 am__DEPENDENCIES_1 = tc-@target_cpu_type@.o
@@ -103,8 +102,6 @@ LTYACCCOMPILE = $(LIBTOOL) --mode=compile $(YACC) $(YFLAGS) \
 YLWRAP = $(top_srcdir)/../ylwrap
 SOURCES = $(as_new_SOURCES) $(EXTRA_as_new_SOURCES) \
 	$(itbl_test_SOURCES)
-DIST_SOURCES = $(as_new_SOURCES) $(EXTRA_as_new_SOURCES) \
-	$(itbl_test_SOURCES)
 RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \
 	html-recursive info-recursive install-data-recursive \
 	install-exec-recursive install-info-recursive \
@@ -173,6 +170,7 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
 PACKAGE = @PACKAGE@
@@ -202,6 +200,8 @@ am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
 am__include = @am__include@
 am__leading_dot = @am__leading_dot@
 am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
 atof = @atof@
 bindir = @bindir@
 build = @build@
@@ -211,6 +211,8 @@ build_os = @build_os@
 build_vendor = @build_vendor@
 cgen_cpu_prefix = @cgen_cpu_prefix@
 datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
 exec_prefix = @exec_prefix@
 extra_objects = @extra_objects@
 host = @host@
@@ -218,6 +220,7 @@ host_alias = @host_alias@
 host_cpu = @host_cpu@
 host_os = @host_os@
 host_vendor = @host_vendor@
+htmldir = @htmldir@
 includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
@@ -269,19 +272,19 @@ IT_OBJS = itbl-parse.o itbl-lex.o itbl-ops.o
 
 # CPU types.  This is only used for dependency information.
 CPU_TYPES = \
-	a29k \
 	alpha \
 	arc \
 	arm \
 	avr \
+	bfin \
 	cris \
+	crx \
 	d10v \
 	d30v \
 	dlx \
 	fr30 \
 	frv \
 	h8300 \
-	h8500 \
 	hppa \
 	ia64 \
 	i370 \
@@ -289,10 +292,10 @@ CPU_TYPES = \
 	i860 \
 	i960 \
 	ip2k \
+	m32c \
 	m32r \
 	m68hc11 \
 	m68k \
-	m88k \
 	mcore \
 	mips \
 	mmix \
@@ -309,16 +312,15 @@ CPU_TYPES = \
 	sh \
 	sh64 \
 	sparc \
-	tahoe \
 	tic30 \
 	tic4x \
 	tic54x \
-	tic80 \
 	vax \
-	w65 \
 	v850 \
 	xstormy16 \
+	xc16x \
 	xtensa \
+	z80 \
 	z8k
 
 
@@ -326,14 +328,11 @@ CPU_TYPES = \
 # We deliberately omit SOM, since it does not work as a cross assembler.
 OBJ_FORMATS = \
 	aout \
-	bout \
 	coff \
 	ecoff \
 	elf \
 	evax \
-	hp300 \
-	ieee \
-	vms
+	ieee
 
 
 # This is an sh case which sets valid according to whether the CPU
@@ -345,13 +344,9 @@ CPU_OBJ_VALID = \
 	case $$o in \
 	aout) \
 	  case $$c in \
-	  a29k | arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tahoe | tic30 | vax) \
+	  arm | cris | i386 | m68k | ns32k | pdp11 | sparc | tic30 | vax) \
 	    valid=yes ;; \
 	  esac ;; \
-	bout) \
-	  case $$c in \
-	  i960) valid=yes ;; \
-	  esac ;; \
 	coff) valid=yes; \
 	  case $$c in \
 	  cris | i860 | mmix | sh64) \
@@ -366,10 +361,6 @@ CPU_OBJ_VALID = \
 	  case $$c in \
 	  alpha) valid=yes ;; \
 	  esac ;; \
-	hp300) \
-	  case $$c in \
-	  m68k) valid=yes ;; \
-	  esac ;; \
 	vms) \
 	  case $$c in \
 	  vax) valid=yes ;; \
@@ -403,7 +394,6 @@ GAS_CFILES = \
 	app.c \
 	as.c \
 	atof-generic.c \
-	bignum-copy.c \
 	cond.c \
 	depend.c \
 	dwarf2dbg.c \
@@ -447,6 +437,7 @@ HFILES = \
 	frags.h \
 	hash.h \
 	input-file.h \
+	itbl-lex.h \
 	itbl-ops.h \
 	listing.h \
 	macro.h \
@@ -463,19 +454,19 @@ HFILES = \
 
 # CPU files in config.
 TARGET_CPU_CFILES = \
-	config/tc-a29k.c \
 	config/tc-alpha.c \
 	config/tc-arc.c \
 	config/tc-arm.c \
 	config/tc-avr.c \
+	config/tc-bfin.c \
 	config/tc-cris.c \
+	config/tc-crx.c \
 	config/tc-d10v.c \
 	config/tc-d30v.c \
 	config/tc-dlx.c \
 	config/tc-fr30.c \
 	config/tc-frv.c \
 	config/tc-h8300.c \
-	config/tc-h8500.c \
 	config/tc-hppa.c \
 	config/tc-ia64.c \
 	config/tc-i370.c \
@@ -483,10 +474,10 @@ TARGET_CPU_CFILES = \
 	config/tc-i860.c \
 	config/tc-i960.c \
 	config/tc-ip2k.c \
+	config/tc-m32c.c \
 	config/tc-m32r.c \
 	config/tc-m68hc11.c \
 	config/tc-m68k.c \
-	config/tc-m88k.c \
 	config/tc-mcore.c \
 	config/tc-mips.c \
 	config/tc-mmix.c \
@@ -503,31 +494,30 @@ TARGET_CPU_CFILES = \
 	config/tc-sh.c \
 	config/tc-sh64.c \
 	config/tc-sparc.c \
-	config/tc-tahoe.c \
 	config/tc-tic30.c \
 	config/tc-tic54x.c \
-	config/tc-tic80.c \
 	config/tc-vax.c \
-	config/tc-w65.c \
 	config/tc-v850.c \
 	config/tc-xstormy16.c \
+	config/tc-xc16x.c \
 	config/tc-xtensa.c \
+	config/tc-z80.c \
 	config/tc-z8k.c
 
 TARGET_CPU_HFILES = \
-	config/tc-a29k.h \
 	config/tc-alpha.h \
 	config/tc-arc.h \
 	config/tc-arm.h \
 	config/tc-avr.h \
+	config/tc-bfin.h \
 	config/tc-cris.h \
+	config/tc-crx.h \
 	config/tc-d10v.h \
 	config/tc-d30v.h \
 	config/tc-dlx.h \
 	config/tc-fr30.h \
 	config/tc-frv.h \
 	config/tc-h8300.h \
-	config/tc-h8500.h \
 	config/tc-hppa.h \
 	config/tc-ia64.h \
 	config/tc-i370.h \
@@ -535,10 +525,10 @@ TARGET_CPU_HFILES = \
 	config/tc-i860.h \
 	config/tc-i960.h \
 	config/tc-ip2k.h \
+	config/tc-m32c.h \
 	config/tc-m32r.h \
 	config/tc-m68hc11.h \
 	config/tc-m68k.h \
-	config/tc-m88k.h \
 	config/tc-mcore.h \
 	config/tc-mips.h \
 	config/tc-mmix.h \
@@ -555,47 +545,41 @@ TARGET_CPU_HFILES = \
 	config/tc-sh.h \
 	config/tc-sh64.h \
 	config/tc-sparc.h \
-	config/tc-tahoe.h \
 	config/tc-tic30.h \
 	config/tc-tic54x.h \
-	config/tc-tic80.h \
 	config/tc-vax.h \
-	config/tc-w65.h \
 	config/tc-v850.h \
 	config/tc-xstormy16.h \
+	config/tc-xc16x.h \
 	config/tc-xtensa.h \
+	config/tc-z80.h \
 	config/tc-z8k.h
 
 
 # OBJ files in config
 OBJ_FORMAT_CFILES = \
 	config/obj-aout.c \
-	config/obj-bout.c \
 	config/obj-coff.c \
 	config/obj-ecoff.c \
 	config/obj-elf.c \
 	config/obj-evax.c \
-	config/obj-hp300.c \
 	config/obj-ieee.c \
-	config/obj-som.c \
-	config/obj-vms.c
+	config/obj-som.c
 
 OBJ_FORMAT_HFILES = \
 	config/obj-aout.h \
-	config/obj-bout.h \
 	config/obj-coff.h \
 	config/obj-ecoff.h \
 	config/obj-elf.h \
 	config/obj-evax.h \
-	config/obj-hp300.h \
 	config/obj-ieee.h \
-	config/obj-som.h \
-	config/obj-vms.h
+	config/obj-som.h
 
 
 # Emulation header files in config
 TARG_ENV_HFILES = \
 	config/te-386bsd.h \
+	config/te-armlinuxeabi.h \
 	config/te-aux.h \
 	config/te-delta.h \
 	config/te-delt88.h \
@@ -604,7 +588,6 @@ TARG_ENV_HFILES = \
 	config/te-epoc-pe.h \
 	config/te-generic.h \
 	config/te-go32.h \
-	config/te-hp300.h \
 	config/te-hppa.h \
 	config/te-hppa64.h \
 	config/te-hppalinux64.h \
@@ -618,15 +601,15 @@ TARG_ENV_HFILES = \
 	config/te-macos.h \
 	config/te-nbsd.h \
 	config/te-nbsd532.h \
+	config/te-netware.h \
 	config/te-pc532mach.h \
 	config/te-pe.h \
-	config/te-ppcnw.h \
 	config/te-psos.h \
 	config/te-riscix.h \
 	config/te-sparcaout.h \
 	config/te-sun3.h \
 	config/te-svr4.h \
-	config/te-sysv32.h \
+	config/te-symbian.h \
 	config/te-tmips.h
 
 
@@ -650,7 +633,6 @@ GENERIC_OBJS = \
 	app.o \
 	as.o \
 	atof-generic.o \
-	bignum-copy.o \
 	cond.o \
 	depend.o \
 	dwarf2dbg.o \
@@ -680,11 +662,13 @@ GENERIC_OBJS = \
 OBJS = $(CONFIG_OBJS) $(GENERIC_OBJS)
 POTFILES = $(MULTI_CFILES) $(TARGET_ENV_HFILES) $(OBJ_FORMAT_HFILES) \
 	$(OBJ_FORMAT_CFILES) $(TARGET_CPU_HFILES) $(TARGET_CPU_CFILES) \
-	$(HFILES) $(CFILES) $(GAS_CFILES)
+	$(HFILES) $(CFILES)
 
 noinst_SCRIPTS = $(GDBINIT)
 EXTRA_SCRIPTS = .gdbinit
-EXTRA_DIST = make-gas.com m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c
+EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \
+	bfin-parse.c bfin-parse.h bfin-lex.c
+
 DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h
 
 # Now figure out from those variables how to compile and link.
@@ -697,14 +681,14 @@ INCDIR = $(BASEDIR)/include
 # Both . and srcdir are used, in that order,
 # so that tm.h and config.h will be found in the compilation
 # subdirectory rather than in the source directory.
-INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(prefix)/share/locale\""
+INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(srcdir)/config -I$(INCDIR) -I$(srcdir)/.. -I$(BFDDIR) -I$(srcdir)/../intl -I../intl -DLOCALEDIR="\"$(datadir)/locale\""
 
 # This should be parallel to INCLUDES, but should replace $(srcdir)
 # with $${srcdir}, and should work in a subdirectory.  This is used
 # when building dependencies, because the dependency building is done
 # in a subdirectory.
-DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(prefix)/share/locale\""
-DEP_FLAGS = -DBFD_ASSEMBLER -DOBJ_MAYBE_ELF \
+DEP_INCLUDES = -D_GNU_SOURCE -I.. -I$${srcdir} -I../../bfd -I$${srcdir}/config -I$${srcdir}/../include -I$${srcdir}/.. -I$${srcdir}/../bfd -I$${srcdir}/../intl -I../../intl -DLOCALEDIR="\"$(datadir)/locale\""
+DEP_FLAGS = -DOBJ_MAYBE_ELF \
 	-I. -I.. -I$${srcdir} -I../../bfd $(DEP_INCLUDES)
 
 
@@ -721,18 +705,12 @@ as_new_LDADD = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
 as_new_DEPENDENCIES = $(TARG_CPU_O) $(OBJ_FORMAT_O) $(ATOF_TARG_O) \
 	$(extra_objects) $(GASLIBS) $(INTLDEPS)
 
-EXPECT = `if [ -f $${rootme}/../expect/expect ] ; then \
-          echo $${rootme}/../expect/expect ; \
-          else echo expect ; fi`
-
-RUNTEST = `if [ -f $${srcdir}/../dejagnu/runtest ] ; then \
-		echo $${srcdir}/../dejagnu/runtest ; else echo runtest; \
-	   fi`
-
+EXPECT = expect
+RUNTEST = runtest
 RUNTESTFLAGS = 
 
 # The m68k operand parser.
-EXTRA_as_new_SOURCES = config/m68k-parse.y
+EXTRA_as_new_SOURCES = config/m68k-parse.y config/bfin-parse.y
 itbl_test_SOURCES = itbl-parse.y itbl-lex.l
 itbl_test_LDADD = itbl-tops.o itbl-test.o $(GASLIBS) @LEXLIB@
 
@@ -740,7 +718,7 @@ itbl_test_LDADD = itbl-tops.o itbl-test.o $(GASLIBS) @LEXLIB@
 CGEN_CPU_PREFIX = @cgen_cpu_prefix@
 
 # Remake the info files.
-MOSTLYCLEANFILES = $(STAGESTUFF) core stamp-mk.com \
+MOSTLYCLEANFILES = $(STAGESTUFF) core \
 	testsuite/*.o testsuite/*.out testsuite/gas.log testsuite/gas.sum \
 	testsuite/site.exp site.bak site.exp stage stage1 stage2
 
@@ -749,33 +727,19 @@ against = stage2
 DEP_FILE_DEPS = $(CFILES) $(HFILES) $(TARGET_CPU_CFILES) \
 	$(TARGET_CPU_HFILES) $(OBJ_FORMAT_CFILES) $(OBJ_FORMAT_HFILES)
 
-CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt
 AMKDEP = #DO NOT PUT ANYTHING BETWEEN THIS LINE AND THE MATCHING WARNING BELOW.
-DEPTC_a29k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-a29k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
-
-DEPTC_a29k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-a29k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/a29k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
-
-DEPTC_a29k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/a29k.h
-
 DEPTC_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
 DEPTC_alpha_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
   $(srcdir)/config/tc-alpha.h ecoff.h $(INCDIR)/coff/sym.h \
   $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
 DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
@@ -788,8 +752,8 @@ DEPTC_alpha_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
 
 DEPTC_alpha_evax = $(INCDIR)/symcat.h $(srcdir)/config/obj-evax.h \
   $(srcdir)/config/tc-alpha.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h $(INCDIR)/safe-ctype.h \
-  $(srcdir)/config/atof-vax.c
+  struc-symbol.h ecoff.h $(INCDIR)/opcode/alpha.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/safe-ctype.h $(srcdir)/config/atof-vax.c
 
 DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-arc.h $(INCDIR)/coff/internal.h \
@@ -801,25 +765,27 @@ DEPTC_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
-  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  dwarf2dbg.h struc-symbol.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/opcode/arc.h $(srcdir)/../opcodes/arc-ext.h \
+  $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/arm.h
 
 DEPTC_arm_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-arm.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/arm.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
+  $(INCDIR)/obstack.h $(INCDIR)/opcode/arm.h
 
 DEPTC_arm_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arm.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  $(INCDIR)/opcode/arm.h $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
 DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-avr.h $(INCDIR)/coff/internal.h \
@@ -829,9 +795,27 @@ DEPTC_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/avr.h
 
+DEPTC_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h struc-symbol.h \
+  $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h dwarf2dbg.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
+  $(srcdir)/config/bfin-aux.h $(INCDIR)/opcode/bfin.h \
+  $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
+
+DEPTC_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h struc-symbol.h $(srcdir)/config/bfin-defs.h \
+  $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h $(srcdir)/config/bfin-aux.h \
+  $(INCDIR)/opcode/bfin.h $(srcdir)/config/bfin-defs.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
+
 DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
@@ -840,8 +824,20 @@ DEPTC_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
 DEPTC_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/cris.h dwarf2dbg.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/cris.h
+
+DEPTC_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h $(INCDIR)/opcode/crx.h $(INCDIR)/elf/crx.h \
+  $(INCDIR)/elf/reloc-macros.h
+
+DEPTC_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/crx.h \
+  $(INCDIR)/elf/crx.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
@@ -874,35 +870,38 @@ DEPTC_dlx_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_dlx_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-dlx.h $(INCDIR)/opcode/dlx.h
+  $(srcdir)/config/tc-dlx.h dwarf2dbg.h $(INCDIR)/opcode/dlx.h
 
 DEPTC_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/fr30-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/fr30-opc.h cgen.h
 
 DEPTC_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/fr30-opc.h cgen.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/fr30-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/fr30-opc.h \
+  cgen.h
 
 DEPTC_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(srcdir)/../opcodes/frv-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
+  cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h $(INCDIR)/elf/common.h \
+  $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_frv_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-frv.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/frv-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/frv-opc.h \
-  cgen.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/frv-opc.h cgen.h $(BFDDIR)/libbfd.h \
+  $(INCDIR)/hashtab.h $(INCDIR)/elf/frv.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-h8300.h $(INCDIR)/coff/internal.h \
@@ -913,21 +912,9 @@ DEPTC_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  subsegs.h $(INCDIR)/obstack.h dwarf2dbg.h $(INCDIR)/opcode/h8300.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/h8300.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/h8.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_h8500_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8500.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8500.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/h8500-opc.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_h8500_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/h8500-opc.h \
-  $(INCDIR)/safe-ctype.h
-
 DEPTC_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
@@ -961,38 +948,36 @@ DEPTC_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h $(INCDIR)/opcode/i370.h $(INCDIR)/elf/i370.h \
   $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-i386.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i386.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/i386.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
   $(INCDIR)/obstack.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/i386.h
+  $(INCDIR)/opcode/i386.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/i386.h \
+  $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/i860.h $(INCDIR)/elf/i860.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_i960_bout = $(INCDIR)/symcat.h $(srcdir)/config/obj-bout.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/i960.h
-
 DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/i960.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \
@@ -1001,36 +986,60 @@ DEPTC_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/i960.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/i960.h
 
 DEPTC_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/common.h \
-  $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h
+  $(srcdir)/../opcodes/ip2k-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
 
 DEPTC_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/ip2k-opc.h \
-  cgen.h $(INCDIR)/elf/ip2k.h $(INCDIR)/elf/reloc-macros.h \
-  $(BFDDIR)/libbfd.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/ip2k-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/ip2k-opc.h cgen.h $(INCDIR)/elf/ip2k.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h
+
+DEPTC_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32c-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32c-opc.h \
+  $(srcdir)/../opcodes/cgen-types.h $(srcdir)/../opcodes/cgen-ops.h \
+  cgen.h $(INCDIR)/elf/common.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
+
+DEPTC_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32c-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/m32c-opc.h $(srcdir)/../opcodes/cgen-types.h \
+  $(srcdir)/../opcodes/cgen-ops.h cgen.h $(INCDIR)/elf/m32c.h \
+  $(INCDIR)/elf/reloc-macros.h $(BFDDIR)/libbfd.h $(INCDIR)/hashtab.h \
+  $(INCDIR)/safe-ctype.h
 
 DEPTC_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/m32r-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
-  cgen.h
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/m32r-opc.h cgen.h $(INCDIR)/elf/m32r.h \
+  $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/m32r-opc.h cgen.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/m32r-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/m32r-opc.h \
+  cgen.h $(INCDIR)/elf/m32r.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
@@ -1042,8 +1051,8 @@ DEPTC_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/m68hc11.h dwarf2dbg.h $(INCDIR)/elf/m68hc11.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/m68hc11.h $(INCDIR)/elf/m68hc11.h \
   $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
@@ -1067,24 +1076,6 @@ DEPTC_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(srcdir)/config/m68k-parse.h $(INCDIR)/elf/m68k.h \
   $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_m68k_hp300 = $(INCDIR)/symcat.h $(srcdir)/config/obj-hp300.h \
-  $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h subsegs.h dwarf2dbg.h dw2gencfi.h \
-  $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/m68k.h $(srcdir)/config/m68k-parse.h
-
-DEPTC_m88k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m88k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m88k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h $(srcdir)/config/m88k-opcode.h
-
-DEPTC_m88k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/config/m88k-opcode.h
-
 DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1094,48 +1085,42 @@ DEPTC_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/mcore-opc.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/elf/mcore.h $(INCDIR)/elf/reloc-macros.h
 
-DEPTC_mips_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-mips.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
-
 DEPTC_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mipspe.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
-  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
+  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
+  $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h ecoff.h \
+  $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
 DEPTC_mips_ecoff = $(INCDIR)/symcat.h $(srcdir)/config/obj-ecoff.h \
   $(srcdir)/config/tc-mips.h ecoff.h $(INCDIR)/coff/sym.h \
   $(INCDIR)/coff/ecoff.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/mips.h itbl-ops.h \
-  dwarf2dbg.h $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h \
-  $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h
+  dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h \
+  $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mips.h \
   subsegs.h $(INCDIR)/obstack.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h $(INCDIR)/elf/mips.h \
-  $(INCDIR)/elf/reloc-macros.h ecoff.h $(INCDIR)/coff/sym.h \
-  $(INCDIR)/coff/ecoff.h
+  $(INCDIR)/opcode/mips.h itbl-ops.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h \
+  ecoff.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/ecoff.h
 
 DEPTC_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/elf/mmix.h \
   $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/mmix.h \
-  $(INCDIR)/safe-ctype.h dwarf2dbg.h
+  $(INCDIR)/safe-ctype.h
 
 DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
@@ -1145,7 +1130,7 @@ DEPTC_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/mn10200.h
 
 DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
@@ -1157,18 +1142,18 @@ DEPTC_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/mn10300.h dwarf2dbg.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/mn10300.h
 
 DEPTC_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/opcode/msp430.h $(INCDIR)/safe-ctype.h dwarf2dbg.h
 
 DEPTC_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/msp430.h \
   $(INCDIR)/safe-ctype.h
 
 DEPTC_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
@@ -1183,20 +1168,21 @@ DEPTC_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/opcode/ns32k.h $(INCDIR)/obstack.h
 
 DEPTC_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
+  $(srcdir)/../opcodes/openrisc-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
+  cgen.h
 
 DEPTC_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/openrisc-opc.h \
-  cgen.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/openrisc-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/openrisc-opc.h cgen.h
 
 DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
@@ -1207,7 +1193,7 @@ DEPTC_or32_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_or32_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-or32.h $(INCDIR)/opcode/or32.h \
+  $(srcdir)/config/tc-or32.h dwarf2dbg.h $(INCDIR)/opcode/or32.h \
   $(INCDIR)/elf/or32.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
@@ -1222,7 +1208,7 @@ DEPTC_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pdp11.h
 
 DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
@@ -1232,7 +1218,7 @@ DEPTC_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/pj.h
 
 DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
@@ -1243,9 +1229,9 @@ DEPTC_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/ppc.h \
-  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
+  $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-s390.h $(INCDIR)/coff/internal.h \
@@ -1257,22 +1243,24 @@ DEPTC_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/opcode/s390.h $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h $(INCDIR)/opcode/s390.h \
+  $(INCDIR)/elf/s390.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/sh.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
-  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h
+  $(INCDIR)/safe-ctype.h struc-symbol.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h
 
 DEPTC_sh_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sh.h \
   subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/sh-opc.h \
   $(INCDIR)/safe-ctype.h struc-symbol.h $(INCDIR)/elf/sh.h \
-  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h
+  $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h dw2gencfi.h \
+  $(INCDIR)/elf/dwarf2.h
 
 DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
@@ -1280,7 +1268,8 @@ DEPTC_sh64_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \
   $(BFDDIR)/elf32-sh64.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/sh64-opc.h \
   $(srcdir)/config/tc-sh.c subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h dw2gencfi.h
+  $(srcdir)/../opcodes/sh-opc.h struc-symbol.h dwarf2dbg.h \
+  dw2gencfi.h $(INCDIR)/elf/dwarf2.h
 
 DEPTC_sparc_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-sparc.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1297,24 +1286,9 @@ DEPTC_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/opcode/sparc.h dw2gencfi.h $(INCDIR)/elf/dwarf2.h \
-  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h \
-  dwarf2dbg.h
-
-DEPTC_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
-
-DEPTC_tahoe_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tahoe.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h \
-  $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
-
-DEPTC_tahoe_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/obstack.h $(INCDIR)/opcode/tahoe.h
+  $(INCDIR)/elf/sparc.h $(INCDIR)/elf/reloc-macros.h
 
 DEPTC_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1328,7 +1302,7 @@ DEPTC_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic30.h
 
 DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
@@ -1339,7 +1313,7 @@ DEPTC_tic4x_coff = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
 DEPTC_tic4x_elf = $(INCDIR)/safe-ctype.h $(INCDIR)/symcat.h \
   $(srcdir)/config/obj-elf.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \
   $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \
-  $(srcdir)/config/tc-tic4x.h $(INCDIR)/opcode/tic4x.h \
+  $(srcdir)/config/tc-tic4x.h dwarf2dbg.h $(INCDIR)/opcode/tic4x.h \
   subsegs.h $(INCDIR)/obstack.h
 
 DEPTC_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
@@ -1356,49 +1330,23 @@ DEPTC_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h \
   $(BFDDIR)/libcoff.h
 
-DEPTC_tic80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic80.h
-
-DEPTC_tic80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/tic80.h
-
 DEPTC_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/opcode/vax.h $(INCDIR)/safe-ctype.h
+  $(INCDIR)/safe-ctype.h $(INCDIR)/opcode/vax.h
 
 DEPTC_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-vax.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
+  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/safe-ctype.h \
+  $(INCDIR)/opcode/vax.h
 
 DEPTC_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h subsegs.h \
-  $(INCDIR)/elf/vax.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_vax_vms = $(INCDIR)/symcat.h $(srcdir)/config/obj-vms.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(srcdir)/config/vax-inst.h \
-  $(INCDIR)/obstack.h subsegs.h $(INCDIR)/opcode/vax.h \
-  $(INCDIR)/safe-ctype.h
-
-DEPTC_w65_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-w65.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/w65.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/w65-opc.h
-
-DEPTC_w65_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/w65-opc.h
+  dwarf2dbg.h $(srcdir)/config/vax-inst.h $(INCDIR)/obstack.h \
+  subsegs.h $(INCDIR)/safe-ctype.h $(INCDIR)/elf/vax.h \
+  $(INCDIR)/elf/reloc-macros.h $(INCDIR)/opcode/vax.h
 
 DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
@@ -1409,31 +1357,50 @@ DEPTC_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(INCDIR)/opcode/v850.h \
-  dwarf2dbg.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(INCDIR)/opcode/v850.h
 
 DEPTC_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h subsegs.h $(INCDIR)/obstack.h \
-  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen.h \
-  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
+  $(srcdir)/../opcodes/xstormy16-desc.h $(INCDIR)/opcode/cgen-bitset.h \
+  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
+  cgen.h
 
 DEPTC_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
-  $(INCDIR)/opcode/cgen.h $(srcdir)/../opcodes/xstormy16-opc.h \
-  cgen.h
+  dwarf2dbg.h subsegs.h $(INCDIR)/obstack.h $(srcdir)/../opcodes/xstormy16-desc.h \
+  $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/xstormy16-opc.h cgen.h
+
+DEPTC_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/../opcodes/xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  $(srcdir)/../opcodes/xc16x-opc.h cgen.h
 
 DEPTC_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h sb.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h $(srcdir)/config/xtensa-relax.h \
-  $(INCDIR)/xtensa-isa.h $(srcdir)/config/xtensa-istack.h \
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h sb.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  $(srcdir)/config/xtensa-relax.h $(srcdir)/config/xtensa-istack.h \
   dwarf2dbg.h struc-symbol.h
 
+DEPTC_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/safe-ctype.h subsegs.h \
+  $(INCDIR)/obstack.h
+
+DEPTC_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h
+
 DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/z8k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1442,7 +1409,7 @@ DEPTC_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPTC_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h $(srcdir)/../opcodes/z8k-opc.h
 
 DEPTC_hppa_som = $(srcdir)/config/tc-hppa.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h \
@@ -1455,21 +1422,6 @@ DEPTC_mips_multi = $(DEPTC_mips_coff) $(DEPTC_mips_ecoff) \
   $(DEPTC_mips_elf)
 
 DEPTC_cris_multi = $(DEPTC_cris_aout) $(DEPTC_cris_elf)
-DEPOBJ_a29k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-a29k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_a29k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-a29k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/a29k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_a29k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
 DEPOBJ_alpha_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-alpha.h $(INCDIR)/coff/internal.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
@@ -1499,8 +1451,8 @@ DEPOBJ_arc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_arc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_arm_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-arm.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1525,8 +1477,19 @@ DEPOBJ_avr_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_avr_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+
+DEPOBJ_bfin_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-bfin.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+
+DEPOBJ_bfin_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-cris.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1535,8 +1498,19 @@ DEPOBJ_cris_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
 DEPOBJ_cris_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+
+DEPOBJ_crx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-crx.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+
+DEPOBJ_crx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_d10v_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-d10v.h $(INCDIR)/coff/internal.h \
@@ -1568,8 +1542,8 @@ DEPOBJ_dlx_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_dlx_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-fr30.h $(INCDIR)/coff/internal.h \
@@ -1579,8 +1553,8 @@ DEPOBJ_fr30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_fr30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_frv_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-frv.h $(INCDIR)/coff/internal.h \
@@ -1601,19 +1575,8 @@ DEPOBJ_h8300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_h8300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_h8500_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-h8500.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/h8500.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_h8500_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_hppa_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-hppa.h $(INCDIR)/coff/internal.h \
@@ -1649,8 +1612,8 @@ DEPOBJ_i370_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i370_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/i370.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 
 DEPOBJ_i386_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
@@ -1665,17 +1628,15 @@ DEPOBJ_i386_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i386_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/x86-64.h $(INCDIR)/elf/reloc-macros.h \
+  $(INCDIR)/aout/aout64.h
 
 DEPOBJ_i860_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_i960_bout = $(INCDIR)/symcat.h $(srcdir)/config/obj-bout.h \
-  $(srcdir)/config/tc-i960.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-i960.h $(INCDIR)/coff/internal.h \
@@ -1685,8 +1646,8 @@ DEPOBJ_i960_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_i960_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ip2k.h $(INCDIR)/coff/internal.h \
@@ -1696,8 +1657,19 @@ DEPOBJ_ip2k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ip2k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+
+DEPOBJ_m32c_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-m32c.h $(INCDIR)/coff/internal.h \
+  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
+  subsegs.h
+
+DEPOBJ_m32c_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m32r.h $(INCDIR)/coff/internal.h \
@@ -1707,8 +1679,8 @@ DEPOBJ_m32r_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_m32r_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-m68hc11.h $(INCDIR)/coff/internal.h \
@@ -1718,8 +1690,8 @@ DEPOBJ_m68hc11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_m68hc11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_m68k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1736,22 +1708,6 @@ DEPOBJ_m68k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_m68k_hp300 = $(srcdir)/config/obj-aout.c $(INCDIR)/symcat.h \
-  $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h $(INCDIR)/aout/aout64.h \
-  $(INCDIR)/obstack.h
-
-DEPOBJ_m88k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-m88k.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/m88k.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_m88k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
 DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mcore.h $(INCDIR)/coff/internal.h \
   $(INCDIR)/coff/mcore.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
@@ -1760,12 +1716,8 @@ DEPOBJ_mcore_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mcore_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_mips_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-mips.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_mips_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mips.h $(INCDIR)/coff/internal.h \
@@ -1788,8 +1740,8 @@ DEPOBJ_mips_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
 DEPOBJ_mmix_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10200.h $(INCDIR)/coff/internal.h \
@@ -1799,8 +1751,8 @@ DEPOBJ_mn10200_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mn10200_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-mn10300.h $(INCDIR)/coff/internal.h \
@@ -1810,8 +1762,8 @@ DEPOBJ_mn10300_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_mn10300_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-msp430.h $(INCDIR)/coff/internal.h \
@@ -1821,8 +1773,8 @@ DEPOBJ_msp430_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_msp430_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_ns32k_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-ns32k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1836,8 +1788,8 @@ DEPOBJ_ns32k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ns32k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-openrisc.h $(INCDIR)/coff/internal.h \
@@ -1847,8 +1799,8 @@ DEPOBJ_openrisc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_openrisc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-or32.h $(INCDIR)/coff/internal.h \
@@ -1858,8 +1810,8 @@ DEPOBJ_or32_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_or32_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_pdp11_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-pdp11.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1873,8 +1825,8 @@ DEPOBJ_pdp11_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_pdp11_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-pj.h $(INCDIR)/coff/internal.h \
@@ -1884,8 +1836,8 @@ DEPOBJ_pj_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_pj_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-ppc.h $(INCDIR)/coff/internal.h \
@@ -1895,8 +1847,8 @@ DEPOBJ_ppc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_ppc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/elf/ppc.h $(INCDIR)/elf/reloc-macros.h \
   $(INCDIR)/aout/aout64.h
 
 DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
@@ -1907,8 +1859,8 @@ DEPOBJ_s390_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_s390_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_sh_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-sh.h $(INCDIR)/coff/internal.h \
@@ -1940,23 +1892,8 @@ DEPOBJ_sparc_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_sparc_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_tahoe_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-tahoe.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
-  $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
-
-DEPOBJ_tahoe_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tahoe.h $(INCDIR)/coff/internal.h \
-  $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h \
-  subsegs.h
-
-DEPOBJ_tahoe_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_tic30_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-tic30.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
@@ -1970,8 +1907,8 @@ DEPOBJ_tic30_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_tic30_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-tic4x.h $(INCDIR)/coff/internal.h \
@@ -1981,8 +1918,8 @@ DEPOBJ_tic4x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_tic4x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_tic54x_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-tic54x.h $(INCDIR)/coff/internal.h \
@@ -1995,17 +1932,6 @@ DEPOBJ_tic54x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
-DEPOBJ_tic80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-tic80.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/tic80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_tic80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
 DEPOBJ_vax_aout = $(INCDIR)/symcat.h $(srcdir)/config/obj-aout.h \
   $(srcdir)/config/tc-vax.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/aout/aout64.h $(INCDIR)/obstack.h
@@ -2018,24 +1944,8 @@ DEPOBJ_vax_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_vax_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
-
-DEPOBJ_vax_vms = $(INCDIR)/symcat.h $(srcdir)/config/obj-vms.h \
-  $(srcdir)/config/tc-vax.h $(INCDIR)/aout/stab_gnu.h \
-  $(INCDIR)/aout/stab.def $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h
-
-DEPOBJ_w65_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
-  $(srcdir)/config/tc-w65.h $(INCDIR)/coff/internal.h \
-  $(INCDIR)/coff/w65.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
-
-DEPOBJ_w65_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-v850.h $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h \
@@ -2045,9 +1955,9 @@ DEPOBJ_v850_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_v850_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/safe-ctype.h \
-  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
-  $(INCDIR)/aout/aout64.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h \
+  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-xstormy16.h $(INCDIR)/coff/internal.h \
@@ -2057,14 +1967,32 @@ DEPOBJ_xstormy16_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_xstormy16_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
+
+DEPOBJ_xc16x_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h \
   $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
   struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_xtensa_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h subsegs.h \
-  $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h $(INCDIR)/safe-ctype.h \
+  subsegs.h $(INCDIR)/obstack.h struc-symbol.h dwarf2dbg.h \
+  $(INCDIR)/aout/aout64.h
+
+DEPOBJ_z80_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
+  $(srcdir)/config/tc-z80.h $(INCDIR)/coff/internal.h \
+  $(INCDIR)/coff/z80.h $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h $(INCDIR)/obstack.h subsegs.h
+
+DEPOBJ_z80_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
   $(srcdir)/config/tc-z8k.h $(INCDIR)/coff/internal.h \
@@ -2074,8 +2002,8 @@ DEPOBJ_z8k_coff = $(INCDIR)/symcat.h $(srcdir)/config/obj-coff.h \
 DEPOBJ_z8k_elf = $(INCDIR)/symcat.h $(srcdir)/config/obj-elf.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
-  $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
-  struc-symbol.h dwarf2dbg.h $(INCDIR)/aout/aout64.h
+  dwarf2dbg.h $(INCDIR)/safe-ctype.h subsegs.h $(INCDIR)/obstack.h \
+  struc-symbol.h $(INCDIR)/aout/aout64.h
 
 DEPOBJ_hppa_som = $(srcdir)/config/obj-som.h subsegs.h \
   $(INCDIR)/obstack.h $(BFDDIR)/libhppa.h $(BFDDIR)/som.h \
@@ -2088,17 +2016,6 @@ DEPOBJ_mips_multi = $(DEPOBJ_mips_coff) $(DEPOBJ_mips_ecoff) \
   $(DEPOBJ_mips_elf)
 
 DEPOBJ_cris_multi = $(DEPOBJ_cris_aout) $(DEPOBJ_cris_elf)
-DEP_a29k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-a29k.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-
-DEP_a29k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-a29k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/a29k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_a29k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-a29k.h
-
 DEP_alpha_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-alpha.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
   $(INCDIR)/bfdlink.h
@@ -2117,7 +2034,8 @@ DEP_arc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-arc.h \
 
 DEP_arc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-arc.h \
+  dwarf2dbg.h
 
 DEP_arm_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-arm.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2136,14 +2054,34 @@ DEP_avr_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-avr.h \
 
 DEP_avr_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-avr.h \
+  dwarf2dbg.h
+
+DEP_bfin_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-bfin.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+
+DEP_bfin_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-bfin.h \
+  dwarf2dbg.h
 
 DEP_cris_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-cris.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
 DEP_cris_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-cris.h \
+  dwarf2dbg.h
+
+DEP_crx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-crx.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+
+DEP_crx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-crx.h \
+  dwarf2dbg.h
 
 DEP_d10v_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-d10v.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2167,7 +2105,8 @@ DEP_dlx_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-dlx.h \
 
 DEP_dlx_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-dlx.h \
+  dwarf2dbg.h
 
 DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2175,7 +2114,8 @@ DEP_fr30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-fr30.h \
 
 DEP_fr30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-fr30.h \
+  dwarf2dbg.h
 
 DEP_frv_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-frv.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2191,15 +2131,8 @@ DEP_h8300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8300.h \
 
 DEP_h8300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h
-
-DEP_h8500_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-h8500.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/h8500.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_h8500_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8500.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-h8300.h \
+  dwarf2dbg.h
 
 DEP_hppa_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-hppa.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2227,7 +2160,8 @@ DEP_i370_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i370.h \
 
 DEP_i370_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i370.h \
+  dwarf2dbg.h
 
 DEP_i386_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-i386.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2238,20 +2172,22 @@ DEP_i386_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i386.h \
 
 DEP_i386_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i386.h \
+  dwarf2dbg.h
 
 DEP_i860_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i860.h \
+  dwarf2dbg.h
 
-DEP_i960_bout = $(srcdir)/config/obj-bout.h $(srcdir)/config/tc-i960.h
 DEP_i960_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-i960.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/i960.h \
   $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_i960_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-i960.h \
+  dwarf2dbg.h
 
 DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2259,7 +2195,17 @@ DEP_ip2k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ip2k.h \
 
 DEP_ip2k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ip2k.h \
+  dwarf2dbg.h
+
+DEP_m32c_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32c.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
+  $(INCDIR)/bfdlink.h
+
+DEP_m32c_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32c.h \
+  dwarf2dbg.h
 
 DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2267,7 +2213,8 @@ DEP_m32r_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m32r.h \
 
 DEP_m32r_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m32r.h \
+  dwarf2dbg.h
 
 DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m68k.h \
@@ -2275,7 +2222,8 @@ DEP_m68hc11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m68hc11.h \
 
 DEP_m68hc11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68hc11.h \
+  dwarf2dbg.h
 
 DEP_m68k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-m68k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2288,27 +2236,14 @@ DEP_m68k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m68k.h
 
-DEP_m68k_hp300 = $(srcdir)/config/obj-hp300.h $(srcdir)/config/obj-aout.h \
-  $(srcdir)/config/tc-m68k.h $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-
-DEP_m88k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-m88k.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/m88k.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_m88k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-m88k.h
-
 DEP_mcore_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mcore.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mcore.h \
   $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
 
 DEP_mcore_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h
-
-DEP_mips_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-mips.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mcore.h \
+  dwarf2dbg.h
 
 DEP_mips_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mips.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/mipspe.h \
@@ -2323,7 +2258,8 @@ DEP_mips_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
 
 DEP_mmix_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mmix.h \
+  dwarf2dbg.h
 
 DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2331,7 +2267,8 @@ DEP_mn10200_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10200.h \
 
 DEP_mn10200_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10200.h \
+  dwarf2dbg.h
 
 DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2339,7 +2276,8 @@ DEP_mn10300_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-mn10300.h \
 
 DEP_mn10300_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-mn10300.h \
+  dwarf2dbg.h
 
 DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2347,7 +2285,8 @@ DEP_msp430_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-msp430.h \
 
 DEP_msp430_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-msp430.h \
+  dwarf2dbg.h
 
 DEP_ns32k_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-ns32k.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2358,7 +2297,8 @@ DEP_ns32k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ns32k.h \
 
 DEP_ns32k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ns32k.h \
+  dwarf2dbg.h
 
 DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2366,7 +2306,8 @@ DEP_openrisc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-openrisc.h \
 
 DEP_openrisc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-openrisc.h \
+  dwarf2dbg.h
 
 DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/or32.h \
@@ -2374,7 +2315,8 @@ DEP_or32_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-or32.h \
 
 DEP_or32_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-or32.h \
+  dwarf2dbg.h
 
 DEP_pdp11_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-pdp11.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2385,7 +2327,8 @@ DEP_pdp11_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pdp11.h \
 
 DEP_pdp11_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pdp11.h \
+  dwarf2dbg.h
 
 DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2393,7 +2336,8 @@ DEP_pj_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-pj.h \
 
 DEP_pj_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-pj.h \
+  dwarf2dbg.h
 
 DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/rs6000.h \
@@ -2401,7 +2345,8 @@ DEP_ppc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-ppc.h \
 
 DEP_ppc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-ppc.h \
+  dwarf2dbg.h
 
 DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2409,7 +2354,8 @@ DEP_s390_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-s390.h \
 
 DEP_s390_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-s390.h \
+  dwarf2dbg.h
 
 DEP_sh_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sh.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sh.h \
@@ -2434,18 +2380,8 @@ DEP_sparc_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-sparc.h \
 
 DEP_sparc_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h
-
-DEP_tahoe_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tahoe.h \
-  $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
-
-DEP_tahoe_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tahoe.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
-  $(INCDIR)/bfdlink.h
-
-DEP_tahoe_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tahoe.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-sparc.h \
+  dwarf2dbg.h
 
 DEP_tic30_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-tic30.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
@@ -2456,7 +2392,8 @@ DEP_tic30_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic30.h \
 
 DEP_tic30_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic30.h \
+  dwarf2dbg.h
 
 DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic4x.h \
@@ -2464,7 +2401,8 @@ DEP_tic4x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic4x.h \
 
 DEP_tic4x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic4x.h \
+  dwarf2dbg.h
 
 DEP_tic54x_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic54x.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic54x.h \
@@ -2474,14 +2412,6 @@ DEP_tic54x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic54x.h
 
-DEP_tic80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-tic80.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/tic80.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_tic80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-tic80.h
-
 DEP_vax_aout = $(srcdir)/config/obj-aout.h $(srcdir)/config/tc-vax.h \
   $(BFDDIR)/libaout.h $(INCDIR)/bfdlink.h
 
@@ -2491,18 +2421,8 @@ DEP_vax_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-vax.h \
 
 DEP_vax_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h
-
-DEP_vax_vms = $(srcdir)/config/obj-vms.h $(srcdir)/config/tc-vax.h \
-  $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
-
-DEP_w65_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-w65.h \
-  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/w65.h \
-  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
-
-DEP_w65_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
-  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-w65.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-vax.h \
+  dwarf2dbg.h
 
 DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
   $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h $(INCDIR)/symcat.h \
@@ -2511,7 +2431,7 @@ DEP_v850_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-v850.h \
 DEP_v850_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-v850.h \
-  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h
+  $(INCDIR)/elf/v850.h $(INCDIR)/elf/reloc-macros.h dwarf2dbg.h
 
 DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h \
@@ -2519,12 +2439,26 @@ DEP_xstormy16_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-xstormy16.h
 
 DEP_xstormy16_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xstormy16.h \
+  dwarf2dbg.h
+
+DEP_xc16x_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xc16x.h 
 
 DEP_xtensa_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
   $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-xtensa.h \
-  $(INCDIR)/xtensa-config.h
+  $(INCDIR)/xtensa-isa.h $(INCDIR)/xtensa-config.h
+
+DEP_z80_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z80.h \
+  $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z80.h \
+  $(INCDIR)/coff/external.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h
+
+DEP_z80_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
+  $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z80.h \
+  dwarf2dbg.h
 
 DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
   $(INCDIR)/symcat.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/z8k.h \
@@ -2532,7 +2466,8 @@ DEP_z8k_coff = $(srcdir)/config/obj-coff.h $(srcdir)/config/tc-z8k.h \
 
 DEP_z8k_elf = $(srcdir)/config/obj-elf.h $(INCDIR)/symcat.h \
   $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h \
-  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h
+  $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(srcdir)/config/tc-z8k.h \
+  dwarf2dbg.h
 
 DEP_hppa_som = $(BFDDIR)/som.h
 DEP_i386_multi = $(DEP_i386_aout) $(DEP_i386_coff) \
@@ -2658,7 +2593,13 @@ uninstall-info-am:
 #     (which will cause the Makefiles to be regenerated when you run `make');
 # (2) otherwise, pass the desired values on the `make' command line.
 $(RECURSIVE_TARGETS):
-	@set fnord $$MAKEFLAGS; amf=$$2; \
+	@failcom='exit 1'; \
+	for f in x $$MAKEFLAGS; do \
+	  case $$f in \
+	    *=* | --[!k]*);; \
+	    *k*) failcom='fail=yes';; \
+	  esac; \
+	done; \
 	dot_seen=no; \
 	target=`echo $@ | sed s/-recursive//`; \
 	list='$(SUBDIRS)'; for subdir in $$list; do \
@@ -2670,7 +2611,7 @@ $(RECURSIVE_TARGETS):
 	    local_target="$$target"; \
 	  fi; \
 	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
-	   || case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
+	  || eval $$failcom; \
 	done; \
 	if test "$$dot_seen" = "no"; then \
 	  $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
@@ -2678,7 +2619,13 @@ $(RECURSIVE_TARGETS):
 
 mostlyclean-recursive clean-recursive distclean-recursive \
 maintainer-clean-recursive:
-	@set fnord $$MAKEFLAGS; amf=$$2; \
+	@failcom='exit 1'; \
+	for f in x $$MAKEFLAGS; do \
+	  case $$f in \
+	    *=* | --[!k]*);; \
+	    *k*) failcom='fail=yes';; \
+	  esac; \
+	done; \
 	dot_seen=no; \
 	case "$@" in \
 	  distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \
@@ -2699,7 +2646,7 @@ maintainer-clean-recursive:
 	    local_target="$$target"; \
 	  fi; \
 	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
-	   || case "$$amf" in *=*) exit 1;; *k*) fail=yes;; *) exit 1;; esac; \
+	  || eval $$failcom; \
 	done && test -z "$$fail"
 tags-recursive:
 	list='$(SUBDIRS)'; for subdir in $$list; do \
@@ -2733,7 +2680,7 @@ TAGS: tags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \
 	fi; \
 	list='$(SUBDIRS)'; for subdir in $$list; do \
 	  if test "$$subdir" = .; then :; else \
-	    test -f $$subdir/TAGS && \
+	    test ! -f $$subdir/TAGS || \
 	      tags="$$tags $$include_option=$$here/$$subdir/TAGS"; \
 	  fi; \
 	done; \
@@ -2744,7 +2691,7 @@ TAGS: tags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \
 	  $(AWK) '    { files[$$0] = 1; } \
 	       END { for (i in files) print i; }'`; \
 	if test -z "$(ETAGS_ARGS)$$tags$$unique"; then :; else \
-	  test -z "$$unique" && unique=$$empty_fix; \
+	  test -n "$$unique" || unique=$$empty_fix; \
 	  $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \
 	    $$tags $$unique; \
 	fi
@@ -2822,15 +2769,16 @@ clean-generic:
 	-test -z "$(CLEANFILES)" || rm -f $(CLEANFILES)
 
 distclean-generic:
-	-rm -f $(CONFIG_CLEAN_FILES)
+	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 	-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
 
 maintainer-clean-generic:
 	@echo "This command is intended for maintainers to use"
 	@echo "it deletes files that may require special tools to rebuild."
-	-rm -f m68k-parse.c
+	-rm -f bfin-parse.c
 	-rm -f itbl-lex.c
 	-rm -f itbl-parse.c
+	-rm -f m68k-parse.c
 clean: clean-recursive
 
 clean-am: clean-generic clean-libtool clean-noinstPROGRAMS \
@@ -2905,12 +2853,8 @@ po/POTFILES.in: @MAINT@ Makefile
 	for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \
 	  && mv tmp $(srcdir)/po/POTFILES.in
 
-$(srcdir)/make-gas.com: stamp-mk.com
-stamp-mk.com: vmsconf.sh Makefile
-	sh $(srcdir)/vmsconf.sh $(GENERIC_OBJS) > new-make.com
-	$(SHELL) $(srcdir)/../move-if-change new-make.com $(srcdir)/make-gas.com
-	touch stamp-mk.com
 diststuff: $(EXTRA_DIST) info
+all: info
 
 $(OBJS): @ALL_OBJ_DEPS@
 
@@ -2933,10 +2877,6 @@ check-DEJAGNU: site.exp
 	rootme=`pwd`; export rootme; \
 	srcdir=`cd ${srcdir}; pwd` ; export srcdir ; \
 	EXPECT=${EXPECT} ; export EXPECT ; \
-	if [ -f $(top_builddir)/../expect/expect ]; then \
-	  TCL_LIBRARY=`cd $(top_srcdir)/../tcl/library && pwd`; \
-	  export TCL_LIBRARY; \
-	fi; \
 	runtest=$(RUNTEST); \
 	cd testsuite; \
 	if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \
@@ -2963,8 +2903,6 @@ ecoff.o : ecoff.c ecoff.h $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h \
 
 obj-aout.o : $(srcdir)/config/obj-aout.c
 	$(COMPILE) -c $(srcdir)/config/obj-aout.c
-obj-bout.o : $(srcdir)/config/obj-bout.c
-	$(COMPILE) -c $(srcdir)/config/obj-bout.c
 obj-coff.o: $(srcdir)/config/obj-coff.c
 	$(COMPILE) -c $(srcdir)/config/obj-coff.c
 obj-ecoff.o : $(srcdir)/config/obj-ecoff.c
@@ -2973,16 +2911,12 @@ obj-elf.o : $(srcdir)/config/obj-elf.c
 	$(COMPILE) -c $(srcdir)/config/obj-elf.c
 obj-evax.o : $(srcdir)/config/obj-evax.c
 	$(COMPILE) -c $(srcdir)/config/obj-evax.c
-obj-hp300.o : $(srcdir)/config/obj-hp300.c
-	$(COMPILE) -c $(srcdir)/config/obj-hp300.c
 obj-ieee.o : $(srcdir)/config/obj-ieee.c
 	$(COMPILE) -c $(srcdir)/config/obj-ieee.c
 obj-multi.o : $(srcdir)/config/obj-multi.c
 	$(COMPILE) -c $(srcdir)/config/obj-multi.c
 obj-som.o : $(srcdir)/config/obj-som.c
 	$(COMPILE) -c $(srcdir)/config/obj-som.c
-obj-vms.o : $(srcdir)/config/obj-vms.c
-	$(COMPILE) -c $(srcdir)/config/obj-vms.c
 
 e-mipself.o : $(srcdir)/config/e-mipself.c
 	$(COMPILE) -c $(srcdir)/config/e-mipself.c
@@ -3020,27 +2954,51 @@ m68k-parse.c: $(srcdir)/config/m68k-parse.y
 	   cp config/m68k-parse.y . >/dev/null 2>/dev/null; \
 	  f=m68k-parse.y; \
 	else true; fi; \
-	$(SHELL) $(YLWRAP) "$(YACC)" $$f y.tab.c m68k-parse.c --; \
+	$(SHELL) $(YLWRAP) $$f y.tab.c m68k-parse.c -- $(YACCCOMPILE); \
 	if [ $$f = "m68k-parse.y" ]; then \
 	  rm -f m68k-parse.y; \
 	else true; fi
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
 m68k-parse.o: m68k-parse.c $(srcdir)/config/m68k-parse.h
+	$(COMPILE) -c $< $(NO_WERROR)
 
 # Don't let the .y.h rule clobber m68k-parse.h.
 m68k-parse.h: ; @true
 $(srcdir)/config/m68k-parse.h: ; @true
 
+bfin-parse.c: $(srcdir)/config/bfin-parse.y
+	$(SHELL) $(YLWRAP) $(srcdir)/config/bfin-parse.y y.tab.c bfin-parse.c y.tab.h bfin-parse.h -- $(YACCCOMPILE) -d ;
+bfin-parse.h: bfin-parse.c
+bfin-parse.o: bfin-parse.c bfin-parse.h $(srcdir)/config/bfin-defs.h \
+ $(INCDIR)/elf/common.h $(INCDIR)/elf/bfin.h $(BFDDIR)/libbfd.h
+
+bfin-defs.h: ; @true
+$(srcdir)/config/bfin-defs.h: ; @true
+
+bfin-lex.c: $(srcdir)/config/bfin-lex.l
+	$(SHELL) $(YLWRAP) $(srcdir)/config/bfin-lex.l lex.yy.c bfin-lex.c -- $(LEXCOMPILE)
+bfin-lex.o: bfin-lex.c bfin-parse.h $(srcdir)/config/bfin-defs.h
+	$(COMPILE) -c $< $(NO_WERROR)
+
 # The instruction table specification lexical analyzer and parser.
 
 itbl-lex.c: $(srcdir)/itbl-lex.l
-itbl-lex.o: itbl-lex.c itbl-parse.h
 
-itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
+itbl-lex.o: itbl-lex.c itbl-parse.h $(srcdir)/itbl-lex.h
+	$(COMPILE) -c $< $(NO_WERROR)
+
+# Disable -Werror, if it has been enabled, since old versions of bison/
+# yacc will produce working code which contain compile time warnings. 
+itbl-parse.o: itbl-parse.c itbl-parse.h $(srcdir)/itbl-ops.h $(srcdir)/itbl-lex.h
+	$(COMPILE) -c $< $(NO_WERROR)
 
 itbl-ops.o: $(srcdir)/itbl-ops.c $(srcdir)/itbl-ops.h itbl-parse.h
 
 itbl-parse.c itbl-parse.h: $(srcdir)/itbl-parse.y
-	$(SHELL) $(YLWRAP) "$(YACC)" $(srcdir)/itbl-parse.y y.tab.c itbl-parse.c y.tab.h itbl-parse.h -- -d
+	$(SHELL) $(YLWRAP) $(srcdir)/itbl-parse.y y.tab.c itbl-parse.c y.tab.h itbl-parse.h -- $(YACCCOMPILE) -d
 
 itbl-tops.o: $(srcdir)/itbl-ops.c $(srcdir)/itbl-ops.h itbl-parse.h
 	$(COMPILE) -o itbl-tops.o -DSTAND_ALONE -c $(srcdir)/itbl-ops.c
@@ -3053,6 +3011,35 @@ cgen.o: cgen.c cgen.h cgen-desc.h subsegs.h \
 	$(srcdir)/../opcodes/$(CGEN_CPU_PREFIX)-desc.h \
 	$(srcdir)/../opcodes/$(CGEN_CPU_PREFIX)-opc.h
 
+.PHONY: install-html install-html-am install-html-recursive
+
+install-html:	install-html-recursive
+
+install-html-recursive:
+	@failcom='exit 1'; \
+	for f in x $$MAKEFLAGS; do \
+	  case $$f in \
+	    *=* | --[!k]*);; \
+	    *k*) failcom='fail=yes';; \
+	  esac; \
+	done; \
+	dot_seen=no; \
+	target=`echo $@ | sed s/-recursive//`; \
+	list='$(SUBDIRS)'; for subdir in $$list; do \
+	  echo "Making $$target in $$subdir"; \
+	  if test "$$subdir" = "."; then \
+	    dot_seen=yes; \
+	    local_target="$$target-am"; \
+	  else \
+	    local_target="$$target"; \
+	  fi; \
+	  (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \
+	  || eval $$failcom; \
+	done; \
+	if test "$$dot_seen" = "no"; then \
+	  $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \
+	fi; test -z "$$fail"
+
 .PHONY: install-exec-local install-data-local
 .PHONY: install-exec-bindir install-exec-tooldir
 
@@ -3337,11 +3324,10 @@ as.o: as.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h \
   output-file.h sb.h macro.h dwarf2dbg.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h $(BFDVER_H)
 atof-generic.o: atof-generic.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h
-bignum-copy.o: bignum-copy.c $(INCDIR)/symcat.h
 cond.o: cond.c $(INCDIR)/symcat.h macro.h sb.h $(INCDIR)/obstack.h
 depend.o: depend.c $(INCDIR)/symcat.h
-dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h dwarf2dbg.h \
-  $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
+dwarf2dbg.o: dwarf2dbg.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
+  dwarf2dbg.h $(INCDIR)/filenames.h subsegs.h $(INCDIR)/obstack.h \
   $(INCDIR)/elf/dwarf2.h
 dw2gencfi.o: dw2gencfi.c $(INCDIR)/symcat.h dw2gencfi.h \
   $(INCDIR)/elf/dwarf2.h
@@ -3363,13 +3349,14 @@ input-scrub.o: input-scrub.c $(INCDIR)/symcat.h input-file.h \
 listing.o: listing.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
   $(INCDIR)/safe-ctype.h input-file.h subsegs.h
 literal.o: literal.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
-macro.o: macro.c $(INCDIR)/safe-ctype.h sb.h macro.h
+macro.o: macro.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
+  sb.h macro.h
 messages.o: messages.c $(INCDIR)/symcat.h
 output-file.o: output-file.c $(INCDIR)/symcat.h output-file.h
 read.o: read.c $(INCDIR)/symcat.h $(INCDIR)/safe-ctype.h \
   subsegs.h $(INCDIR)/obstack.h sb.h macro.h ecoff.h \
   dw2gencfi.h $(INCDIR)/elf/dwarf2.h
-sb.o: sb.c sb.h
+sb.o: sb.c sb.h $(INCDIR)/symcat.h
 stabs.o: stabs.c $(INCDIR)/symcat.h $(INCDIR)/obstack.h \
   subsegs.h ecoff.h $(INCDIR)/aout/stab_gnu.h $(INCDIR)/aout/stab.def
 subsegs.o: subsegs.c $(INCDIR)/symcat.h subsegs.h $(INCDIR)/obstack.h
diff --git a/gas/NEWS b/gas/NEWS
index 1a31e79f560d..4b4d029685ab 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,75 @@
 -*- text -*-
 
+* Support for the Infineon XC16X has been added by KPIT Cummins Infosystems.
+
+* Support for ms2 architecture has been added.
+
+* Support for the Z80 processor family has been added.
+
+* Add support for the "@<file>" syntax to the command line, so that extra
+  switches can be read from <file>.
+
+* The SH target supports a new command line switch --enable-reg-prefix which,
+  if enabled, will allow register names to be optionally prefixed with a $
+  character.  This allows register names to be distinguished from label names.
+  
+* Macros with a variable number of arguments are now supported. See the
+  documentation for how this works.
+
+* Added --reduce-memory-overheads switch to reduce the size of the hash
+  tables used, at the expense of longer assembly times, and
+  --hash-size=<NUMBER> to set the size of the hash tables used by gas.
+
+* Macro names and macro parameter names can now be any identifier that would
+  also be legal as a symbol elsewhere. For macro parameter names, this is
+  known to cause problems in certain sources when the respective target uses
+  characters inconsistently, and thus macro parameter references may no longer
+  be recognized as such (see the documentation for details).
+  
+* Support the .f_floating, .d_floating, .g_floating and .h_floating directives
+  for the VAX target in order to be more compatible with the VAX MACRO
+  assembler.
+
+* New command line option -mtune=[itanium1|itanium2] for IA64 targets.
+
+Changes in 2.16:
+
+* Redefinition of macros now results in an error.
+
+* New command line option -mhint.b=[ok|warning|error] for IA64 targets.
+
+* New command line option -munwind-check=[warning|error] for IA64
+  targets.
+
+* The IA64 port now uses automatic dependency violation removal as its default
+  mode.
+
+* Port to MAXQ processor contributed by HCL Tech.
+
+* Added support for generating unwind tables for ARM ELF targets.
+
+* Add a -g command line option to generate debug information in the target's
+  preferred debug format.
+
+* Support for the crx-elf target added.
+
+* Support for the sh-symbianelf target added.
+
+* Added a pseudo-op (.secrel32) to generate 32 bit section relative relocations
+  on pe[i]-i386; required for this target's DWARF 2 support.
+
+* Support for Motorola MCF521x/5249/547x/548x added.
+
+* Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC
+  instrucitons.
+
+* New command line option -mno-shared for MIPS ELF targets.
+
+* New command line option --alternate and pseudo-ops .altmacro and .noaltmacro
+  added to enter (and leave) alternate macro syntax mode.
+
+Changes in 2.15:
+
 * The MIPS -membedded-pic option (Embedded-PIC code generation) is
   deprecated and will be removed in a future release.
 
diff --git a/gas/README b/gas/README
index 790539582b2c..c249fd97fd32 100644
--- a/gas/README
+++ b/gas/README
@@ -57,14 +57,6 @@ facility to list all supported host and target names or aliases.
 abbreviations to full names; you can read the script, if you wish, or
 you can use it to test your guesses on abbreviations--for example:
 
-     % sh config.sub sun4
-     sparc-sun-sunos411
-     % sh config.sub sun3
-     m68k-sun-sunos411
-     % sh config.sub decstation
-     mips-dec-ultrix42
-     % sh config.sub hp300bsd
-     m68k-hp-bsd
      % sh config.sub i386v
      i386-unknown-sysv
      % sh config.sub i786v
@@ -139,75 +131,6 @@ The `--enable' options recognized by software in the gas distribution are:
      been done, it's already the default.  So generally you won't need to use
      this option.
 
-Supported platforms
-===================
-
-At this point I believe gas to be ANSI only code for most target cpu's.  That
-is, there should be relatively few, if any host system dependencies.  So
-porting (as a cross-assembler) to hosts not yet supported should be fairly
-easy.  Porting to a new target shouldn't be too tough if it's a variant of one
-already supported.
-
-Native assembling should work on:
-
-	sun3
-	sun4
-	386bsd
-	bsd/386
-	delta (m68k-sysv from Motorola)
-	delta88 (m88k-sysv from Motorola)
-	GNU/linux
-	m68k hpux 8.0 (hpux 7.0 may be a problem)
-	vax bsd, ultrix, vms
-	hp9000s300
-	decstation
-	irix 4
-	irix 5
-	miniframe (m68k-sysv from Convergent Technologies)
-	i386-aix (ps/2)
-	hppa (hpux 4.3bsd, osf1)
-	AIX
-	unixware
-	sco 3.2v4.2
-	sco openserver 5.0 (a.k.a. 3.2v5.0 )
-	sparc solaris
-	ns32k (netbsd, lites)
-
-I believe that gas as a cross-assembler can currently be targeted for
-most of the above hosts, plus
-
-        arm
-	decstation-bsd (a.out format, to be used in BSD 4.4)
-	ebmon29k
-	go32 (DOS on i386, with DJGPP -- old a.out version)
-	H8/300, H8/500 (Hitachi)
-	i386-aix (ps/2)
-	i960-coff
-	mips ecoff (decstation-ultrix, iris, mips magnum, mips-idt-ecoff)
-	Mitsubishi d10v and d30v
-	nindy960
-	powerpc EABI
-	SH (Hitachi)
-	sco386
-	TI tic30 and tic80
-	vax bsd or ultrix?
-	vms
-	vxworks68k
-	vxworks960
-	z8000 (Zilog)
-
-MIPS ECOFF support has been added, but GAS will not run a C-style
-preprocessor.  If you want that, rename your file to have a ".S" suffix, and
-run gcc on it.  Or run "gcc -xassembler-with-cpp foo.s".
-
-Support for ELF should work now for sparc, hppa, i386, alpha, m68k,
-MIPS, powerpc.
-
-Support for sequent (ns32k), tahoe, i860 may be suffering from bitrot.
-
-If you try out gas on some host or target not listed above, please let me know
-the results, so I can update the list.
-
 Compiler Support Hacks
 ======================
 
diff --git a/gas/README-vms b/gas/README-vms
deleted file mode 100644
index f3ee10e5e1d2..000000000000
--- a/gas/README-vms
+++ /dev/null
@@ -1,248 +0,0 @@
-	This document explains a couple of things that are specific to VMS.
-There are currently two "chapters", the first deals with cross-assembly 
-issues, and the second deals with the VMS debugger and GNU-CC.
-
-
-***********************************************************************
-****************** Notes for Cross Assembly with VMS ******************
-***********************************************************************
-
-	If you wish to build gas on a non-VMS system to cross-assemble, 
-you should use:
-
-configure ${hosttype} -target=vms
-
-and then follow the usual procedure.  The object files generated on
-Unix will be correct from a binary point of view, but the real trick is
-getting them to the VMS machine.  The format of the object file is
-a variable-length record, but each record contains binary data.  gas
-writes the records in the same format that VMS would expect,
-namely a two-byte count followed by that number of bytes.
-
-	If you try to copy the file to a VMS system using ftp, the ftp
-protocol will screw up the file by looking for nulls (record terminator for
-unix) and it will insert it's own record terminators at that point.  This
-will obviously corrupt the file. 
-
-	If you try to transfer the file with ftp in binary mode, the
-file itself will not be corrupt, but VMS will think that the file contains
-fixed-length records of 512 bytes.  You can use the public-domain FILE 
-utility to change this with a command like:
-
-$FILE foo.o/type=variable
-
-If you do not have this utility available, the following program can be 
-used to perform this task:
-
-	#include <fab.h>
-	
-	#define RME$C_SETRFM 1
-	 
-	struct FAB * fab;
-	
-	main(int argc, char * argv[]){
-		int i, status;
-		fab = (struct FAB*) malloc(sizeof(struct FAB));
-		*fab = cc$rms_fab;	/* initialize FAB*/
-		fab->fab$b_fac = FAB$M_PUT;
-		fab->fab$l_fop |= FAB$M_ESC;
-		fab->fab$l_ctx = RME$C_SETRFM;
-		fab->fab$w_ifi = 0;
-		for(i=1;i<argc;i++){
-		  printf("Setting %s to variable length records.\n",argv[i]);
-		  fab->fab$l_fna = argv[i];
-	       	  fab->fab$b_fns = strlen(argv[i]);
-		  status = sys$open(fab,0,0);
-		  if((status & 7) != 1) lib$signal(status);
-		  fab->fab$b_rfm = FAB$C_VAR;
-		  status = sys$modify(fab,0,0);
-		  if((status & 7) != 1) lib$signal(status);
-		  status = sys$close(fab,0,0);
-		  if((status & 7) != 1) lib$signal(status);
-		};
-	}
-
-	If you have NFS running on the VMS system, what you need to do
-depends upon which NFS software you are running on the VMS system.  There
-are a number of different TCP/IP packages for VMS available, and only very
-limited testing has been performed.   In the tests that has been done so
-far, the contents of the file will always be correct when transferring the
-file via NFS, but the record attributes may or may not be correct. 
-
-	One proprietary TCP/IP/NFS package for VMS is known to 
-automatically fix the record attributes of the object file if you NFS mount
-a unix disk from the VMS system, and if the file has a ".obj" extension on
-the unix system.  Other TCP/IP packages might do this for you as well, but
-they have not been checked.
-
-No matter what method you use to get the file to the VMS system, it is
-always a good idea to check to make sure that it is the correct type by
-doing a "$dir/full" on the object file. The desired record attributes will
-be "None".  Undesirable record attributes will be "Stream-LF" or anything
-else. 
-
-Once you get the files on the VMS system, you can check their integrity 
-with the "$anal/obj" command.  (Naturally at some point you should rename
-the .o files to .obj).  As far as the debugger is concerned, the records 
-will be correct, but the debugger will not be able to find the source files,
-since it only has the file name, and not the full directory specification.
-You must give the debugger some help by telling it which directories to 
-search for the individual files - once you have done this you should be 
-able to proceed normally.
-
-	It is a good idea to use names for your files which will be valid
-under VMS, since otherwise you will have no way of getting the debugger to
-find the source file when deugging.
-
-The reason for this is that the object file normally contins specific
-information that the debugger can use to positively identify a file, and if
-you are assembling on a unix system this information simply does not exist
-in a meaningful way.  You must help the debugger by using the "SET FILE="
-command to tell the debugger where to look for source files. The debugger
-records will be correct, except that the debugger will not be initially
-able to find the source files.  You can use the "SET FILE" command to tell
-the debugger where to look for the source files. 
-
-I have only tested this with a SVr4 i486 machine, and everything seems to
-work OK, with the limited testing that I have done.  Other machines may
-or may not work.  You should read the chapters on cross-compilers in the gcc
-manual before fooling with this.  Since gas does not need to do any floating
-point arithmetic, the floating point constants that are generated here should
-be correct - the only concern is with constant folding in the main compiler.
-The range and precision of floats and doubles are similar on the 486 (with 
-a builtin 80387) and the VAX, although there is a factor of 2 to 4
-difference in the range.  The double, as implemented on the 486, is quite
-similar to the G_FLOAT on the VAX. 
-
-***********************************************************************
-****************** Notes for using GNU CC with the VMS debugger********
-***********************************************************************
-
-
-	1) You should be aware that GNU-C, as with any other decent compiler,
-will do things when optimization is turned on that you may not expect. 
-Sometimes intermediate results are not written to variables, if they are only
-used in one place, and sometimes variables that are not used at all will not be
-written to the symbol table.  Also, parameters to inline functions are often
-inaccessible. You can see the assembly code equivalent by using KP7 in the
-debugger, and from this you can tell if in fact a variable should have the
-value that you expect.  You can find out if a variable lives withing a register
-by doing a 'show symbol/addr'.
-
-	2) Overly complex data types, such as:
-
-int (*(*(*(*(*(* sarr6)[1])[1])[2])[3])[4])[5];
-
-will not be debugged properly, since the debugging record overflows an internal
-debugger buffer.  gcc-as will convert these to *void as far as the debugger
-symbol table is concerned, which will avoid any problems, and the assembler
-will give you a message informing you that this has happened.
-
-	3) You must, of course, compile and link with /debug.  If you link
-without debug, you still get traceback table in the executable, but there is no
-symbol table for variables.
-
-	4) Included in the patches to VMS.C are fixes to two bugs that are
-unrelated to the changes that I have made.  One of these made it impossible to
-debug small programs sometimes, and the other caused the debugger to become
-confused about which routine it was in, and give this incorrect info in
-tracebacks.
-
-	5) If you are using the GNU-C++ compiler, you should modify the
-compiler driver file GNU_CC:[000000]GCC.COM (or GXX.COM).  If you have a
-separate GXX.COM, then you need to change one line in GXX.COM to:
-$ if f$locate("D",p2) .ne. P2_Length then Debug = " ""-G0"""
-                                       Notice zero--->  ^
-If you are using a GCC.COM that does both C and C++, add the following lines to
-GCC.COM:
-
-$!
-$! Use old style debugging records for VMS
-$!
-$ if (Debug.nes."" ).and. Plus then Debug = " ""-G0"""
-
-after the variables Plus and Debug are set.  The reason for this, is that C++
-compiler by default generates debugging records that are more complex,
-with many new syntactical elements that allow for the new features of the
-language.  The -G0 switch tells the C++ compiler to use the old style debugging
-records.  Until the debugger understands C++ there is not any point to try and
-use the expanded syntax.
-
-	6) When you have nested scopes, i.e.:
-main(){
-	int i;
-	{int i;
-		{int i;
-};};}
-and you say "EXAM i" the debugger needs to figure out which variable you
-actually want to reference.  I have arranged things to define a block to the
-debugger when you use brackets to enter a new scope, so in the example above,
-the variables would be described as:
-TEST\main\i
-TEST\main\$0\i
-TEST\main\$0\$0\i
-At each level, the block name is a number with a dollar sign prefix, the
-numbers start with 0 and count upward.  When you say EXAM i, the debugger looks
-at the current PC, and decides which block it is currently in.  It works from
-the innermost level outward until it finds a block that has the variable "i"
-defined.  You can always specify the scope explicitly.
-
-	7)  With C++, there can be a lot of inline functions, and it would be
-rather restrictive to force the user to debug the program by converting all of
-the inline functions to normal functions.  What I have done is to essentially
-"add" (with the debugger) source lines from the include files that contain the
-inline functions.  Thus when you step into an inline function it appears as if
-you have called the function, and you can examine variables and so forth. 
-There are several *very* important differences, however.  First of all, since
-there is no function call involved, you cannot step over the inline function
-call - you always step into it. Secondly, since the same source lines are used
-in many locations, there is a separate copy of the source for *each* usage. 
-Without this, breakpoints do not work, since we must have a 1-to-1 mapping
-between source lines and PC.
-	Since you cannot step over inline function calls, it can be a real pain
-if you are not really interested in what is going on for that function call.
-What I have done is to use the "-D" switch for the assembler to toggle the
-following behavior.  With the "-D" switch, all inline functions are included in
-the object file, and you can debug everything.  Without the "-D" switch
-(default case with VMS implementation), inline functions are included *only* if
-they did not come from system header files (i.e. from GNU_CC_INCLUDE: or
-GNU_GXX_INCLUDE:).  Thus, without the switch the user only debugs his/her own
-inline functions, and not the system ones. (This is especially useful if you do
-a lot of stream I/O in C++).  This probably will not provide enough granularity
-for many users, but for now this is still somewhat experimental, and I would
-like to reflect upon it and get some feedback before I go any further. 
-Possible solutions include an interactive prompting, a logical name, or a new
-command line option in gcc.c (which is then passed through somehow to the guts
-of the assembler).
-	The inline functions from header files appear after the source code
-for the source file.  This has the advantage that the source file itself is
-numbered with the same line numbers that you get with an editor.  In addition,
-the entire header file is not included, since the assembler makes a list of
-the min and max source lines that are used, and only includes those lines from
-the first to the last actually used. (It is easy to change it to include the
-whole file).
-
-	8) When you are debugging C++ objects, the object "this" is refered to
-as "$this".  Actually, the compiler writes it as ".this", but the period is
-not good for the debugger, so I have a routine to convert it to a $.  (It
-actually converts all periods to $, but only for variables, since this was
-intended to allow us to access "this".
-
-	9) If you use the asm("...") keyword for global symbols, you will not
-be able to see that symbol with the debugger.  The reason is that there are two
-records for the symbol stored in the data structures of the assembler.  One
-contains the info such as psect number and offset, and the other one contains
-the information having to do with the data type of the variable.  In order to
-debug as symbol, you need to be able to coorelate these records, and the only
-way to do this is by name.  The record with the storage attributes will take
-the name used in the asm directive, and the record that specifies the data type
-has the actual variable name, and thus when you use the asm directive to change
-a variable name, the symbol becomes invisible.
-
-	10) Older versions of the compiler ( GNU-C 1.37.92 and earlier) place
-global constants in the text psect.  This is unfortunate, since to the linker
-this appears to be an entry point.  I sent a patch to the compiler to RMS,
-which will generate a .const section for these variables, and patched the
-assembler to put these variables into a psect just like that for normal
-variables, except that they are marked NOWRT.  static constants are still
-placed in the text psect, since there is no need for any external access.
diff --git a/gas/acinclude.m4 b/gas/acinclude.m4
index 4a3ccf358bdd..0946e724f126 100644
--- a/gas/acinclude.m4
+++ b/gas/acinclude.m4
@@ -1,3 +1,5 @@
+sinclude(../bfd/warning.m4)
+
 dnl GAS_CHECK_DECL_NEEDED(name, typedefname, typedef, headers)
 AC_DEFUN([GAS_CHECK_DECL_NEEDED],[
 AC_MSG_CHECKING(whether declaration is required for $1)
diff --git a/gas/aclocal.m4 b/gas/aclocal.m4
index c5ef088d3d2d..cd4267338b72 100644
--- a/gas/aclocal.m4
+++ b/gas/aclocal.m4
@@ -1,7 +1,7 @@
-# generated automatically by aclocal 1.8.4 -*- Autoconf -*-
+# generated automatically by aclocal 1.9.6 -*- Autoconf -*-
 
-# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
-# Free Software Foundation, Inc.
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
+# 2005  Free Software Foundation, Inc.
 # This file is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
 # with or without modifications, as long as this notice is preserved.
@@ -11,55 +11,32 @@
 # even the implied warranty of MERCHANTABILITY or FITNESS FOR A
 # PARTICULAR PURPOSE.
 
-#                                                        -*- Autoconf -*-
-# Copyright (C) 2002, 2003  Free Software Foundation, Inc.
-# Generated from amversion.in; do not edit by hand.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+# Copyright (C) 2002, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
 # AM_AUTOMAKE_VERSION(VERSION)
 # ----------------------------
 # Automake X.Y traces this macro to ensure aclocal.m4 has been
 # generated from the m4 files accompanying Automake X.Y.
-AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api_version="1.8"])
+AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api_version="1.9"])
 
 # AM_SET_CURRENT_AUTOMAKE_VERSION
 # -------------------------------
 # Call AM_AUTOMAKE_VERSION so it can be traced.
 # This function is AC_REQUIREd by AC_INIT_AUTOMAKE.
 AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION],
-	 [AM_AUTOMAKE_VERSION([1.8.4])])
-
-# AM_AUX_DIR_EXPAND
+	 [AM_AUTOMAKE_VERSION([1.9.6])])
 
-# Copyright (C) 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# AM_AUX_DIR_EXPAND                                         -*- Autoconf -*-
 
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 2001, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
 # For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets
 # $ac_aux_dir to `$srcdir/foo'.  In other projects, it is set to
@@ -106,26 +83,16 @@ AC_PREREQ([2.50])dnl
 am_aux_dir=`cd $ac_aux_dir && pwd`
 ])
 
-# AM_CONDITIONAL                                              -*- Autoconf -*-
-
-# Copyright (C) 1997, 2000, 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
+# AM_CONDITIONAL                                            -*- Autoconf -*-
 
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 1997, 2000, 2001, 2003, 2004, 2005
+# Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 6
+# serial 7
 
 # AM_CONDITIONAL(NAME, SHELL-CONDITION)
 # -------------------------------------
@@ -145,30 +112,19 @@ else
 fi
 AC_CONFIG_COMMANDS_PRE(
 [if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then
-  AC_MSG_ERROR([conditional "$1" was never defined.
-Usually this means the macro was only invoked conditionally.])
+  AC_MSG_ERROR([[conditional "$1" was never defined.
+Usually this means the macro was only invoked conditionally.]])
 fi])])
 
-# serial 7						-*- Autoconf -*-
 
-# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
+# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
 # Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
+# serial 8
 
 # There are a few dirty hacks below to avoid letting `AC_PROG_CC' be
 # written in clear, in which case automake, when reading aclocal.m4,
@@ -177,7 +133,6 @@ fi])])
 # CC etc. in the Makefile, will ask for an AC_PROG_CC use...
 
 
-
 # _AM_DEPENDENCIES(NAME)
 # ----------------------
 # See how the compiler implements dependency checking.
@@ -317,26 +272,16 @@ AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno])
 AC_SUBST([AMDEPBACKSLASH])
 ])
 
-# Generate code to set up dependency tracking.   -*- Autoconf -*-
-
-# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+# Generate code to set up dependency tracking.              -*- Autoconf -*-
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
+# Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-#serial 2
+#serial 3
 
 # _AM_OUTPUT_DEPENDENCY_COMMANDS
 # ------------------------------
@@ -355,27 +300,21 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS],
   else
     continue
   fi
-  grep '^DEP_FILES *= *[[^ @%:@]]' < "$mf" > /dev/null || continue
-  # Extract the definition of DEP_FILES from the Makefile without
-  # running `make'.
+  # Extract the definition of DEPDIR, am__include, and am__quote
+  # from the Makefile without running `make'.
   DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
   test -z "$DEPDIR" && continue
+  am__include=`sed -n 's/^am__include = //p' < "$mf"`
+  test -z "am__include" && continue
+  am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
   # When using ansi2knr, U may be empty or an underscore; expand it
   U=`sed -n 's/^U = //p' < "$mf"`
-  test -d "$dirpart/$DEPDIR" || mkdir "$dirpart/$DEPDIR"
-  # We invoke sed twice because it is the simplest approach to
-  # changing $(DEPDIR) to its actual value in the expansion.
-  for file in `sed -n '
-    /^DEP_FILES = .*\\\\$/ {
-      s/^DEP_FILES = //
-      :loop
-	s/\\\\$//
-	p
-	n
-	/\\\\$/ b loop
-      p
-    }
-    /^DEP_FILES = / s/^DEP_FILES = //p' < "$mf" | \
+  # Find all dependency output files, they are included files with
+  # $(DEPDIR) in their names.  We invoke sed twice because it is the
+  # simplest approach to changing $(DEPDIR) to its actual value in the
+  # expansion.
+  for file in `sed -n "
+    s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
        sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do
     # Make sure the directory exists.
     test -f "$dirpart/$file" && continue
@@ -401,54 +340,31 @@ AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS],
      [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"])
 ])
 
-# Like AC_CONFIG_HEADER, but automatically create stamp file. -*- Autoconf -*-
-
-# Copyright (C) 1996, 1997, 2000, 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005
+# Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 7
+# serial 8
 
 # AM_CONFIG_HEADER is obsolete.  It has been replaced by AC_CONFIG_HEADERS.
 AU_DEFUN([AM_CONFIG_HEADER], [AC_CONFIG_HEADERS($@)])
 
-# Do all the work for Automake.                            -*- Autoconf -*-
+# Do all the work for Automake.                             -*- Autoconf -*-
 
-# This macro actually does too much some checks are only needed if
-# your package does certain things.  But this isn't really a big deal.
-
-# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
 # Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# serial 12
 
-# serial 11
+# This macro actually does too much.  Some checks are only needed if
+# your package does certain things.  But this isn't really a big deal.
 
 # AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE])
 # AM_INIT_AUTOMAKE([OPTIONS])
@@ -506,7 +422,6 @@ AM_MISSING_PROG(AUTOCONF, autoconf)
 AM_MISSING_PROG(AUTOMAKE, automake-${am__api_version})
 AM_MISSING_PROG(AUTOHEADER, autoheader)
 AM_MISSING_PROG(MAKEINFO, makeinfo)
-AM_MISSING_PROG(AMTAR, tar)
 AM_PROG_INSTALL_SH
 AM_PROG_INSTALL_STRIP
 AC_REQUIRE([AM_PROG_MKDIR_P])dnl
@@ -515,7 +430,9 @@ AC_REQUIRE([AM_PROG_MKDIR_P])dnl
 AC_REQUIRE([AC_PROG_AWK])dnl
 AC_REQUIRE([AC_PROG_MAKE_SET])dnl
 AC_REQUIRE([AM_SET_LEADING_DOT])dnl
-
+_AM_IF_OPTION([tar-ustar], [_AM_PROG_TAR([ustar])],
+              [_AM_IF_OPTION([tar-pax], [_AM_PROG_TAR([pax])],
+	      		     [_AM_PROG_TAR([v7])])])
 _AM_IF_OPTION([no-dependencies],,
 [AC_PROVIDE_IFELSE([AC_PROG_CC],
                   [_AM_DEPENDENCIES(CC)],
@@ -549,51 +466,27 @@ for _am_header in $config_headers :; do
 done
 echo "timestamp for $1" >`AS_DIRNAME([$1])`/stamp-h[]$_am_stamp_count])
 
+# Copyright (C) 2001, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
 # AM_PROG_INSTALL_SH
 # ------------------
 # Define $install_sh.
-
-# Copyright (C) 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
 AC_DEFUN([AM_PROG_INSTALL_SH],
 [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl
 install_sh=${install_sh-"$am_aux_dir/install-sh"}
 AC_SUBST(install_sh)])
 
-#                                                          -*- Autoconf -*-
-# Copyright (C) 2003  Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 1
+# serial 2
 
 # Check whether the underlying file-system supports filenames
 # with a leading dot.  For instance MS-DOS doesn't.
@@ -608,26 +501,14 @@ fi
 rmdir .tst 2>/dev/null
 AC_SUBST([am__leading_dot])])
 
-
-# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003
+# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2005
 # Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
-# serial 4
+# serial 5
 
 # AM_PROG_LEX
 # -----------
@@ -641,28 +522,17 @@ if test "$LEX" = :; then
   LEX=${am_missing_run}flex
 fi])
 
-# Add --enable-maintainer-mode option to configure.
+# Add --enable-maintainer-mode option to configure.         -*- Autoconf -*-
 # From Jim Meyering
 
-# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004
+# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005
 # Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
-# serial 3
+# serial 4
 
 AC_DEFUN([AM_MAINTAINER_MODE],
 [AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles])
@@ -681,26 +551,15 @@ AC_DEFUN([AM_MAINTAINER_MODE],
 
 AU_DEFUN([jm_MAINTAINER_MODE], [AM_MAINTAINER_MODE])
 
-# Check to see how 'make' treats includes.	-*- Autoconf -*-
-
-# Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
+# Check to see how 'make' treats includes.	            -*- Autoconf -*-
 
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 2001, 2002, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 2
+# serial 3
 
 # AM_MAKE_INCLUDE()
 # -----------------
@@ -744,27 +603,16 @@ AC_MSG_RESULT([$_am_result])
 rm -f confinc confmf
 ])
 
-#  -*- Autoconf -*-
+# Fake the existence of programs that GNU maintainers use.  -*- Autoconf -*-
 
+# Copyright (C) 1997, 1999, 2000, 2001, 2003, 2005
+# Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# Copyright (C) 1997, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
-# serial 3
+# serial 4
 
 # AM_MISSING_PROG(NAME, PROGRAM)
 # ------------------------------
@@ -790,27 +638,16 @@ else
 fi
 ])
 
+# Copyright (C) 2003, 2004, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
 # AM_PROG_MKDIR_P
 # ---------------
 # Check whether `mkdir -p' is supported, fallback to mkinstalldirs otherwise.
-
-# Copyright (C) 2003, 2004 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
-
+#
 # Automake 1.8 used `mkdir -m 0755 -p --' to ensure that directories
 # created by `make install' are always world readable, even if the
 # installer happens to have an overly restrictive umask (e.g. 077).
@@ -831,13 +668,21 @@ fi
 # this.)
 AC_DEFUN([AM_PROG_MKDIR_P],
 [if mkdir -p --version . >/dev/null 2>&1 && test ! -d ./--version; then
-  # Keeping the `.' argument allows $(mkdir_p) to be used without
-  # argument.  Indeed, we sometimes output rules like
+  # We used to keeping the `.' as first argument, in order to
+  # allow $(mkdir_p) to be used without argument.  As in
   #   $(mkdir_p) $(somedir)
-  # where $(somedir) is conditionally defined.
-  # (`test -n '$(somedir)' && $(mkdir_p) $(somedir)' is a more
-  # expensive solution, as it forces Make to start a sub-shell.)
-  mkdir_p='mkdir -p -- .'
+  # where $(somedir) is conditionally defined.  However this is wrong
+  # for two reasons:
+  #  1. if the package is installed by a user who cannot write `.'
+  #     make install will fail,
+  #  2. the above comment should most certainly read
+  #     $(mkdir_p) $(DESTDIR)$(somedir)
+  #     so it does not work when $(somedir) is undefined and
+  #     $(DESTDIR) is not.
+  #  To support the latter case, we have to write
+  #     test -z "$(somedir)" || $(mkdir_p) $(DESTDIR)$(somedir),
+  #  so the `.' trick is pointless.
+  mkdir_p='mkdir -p --'
 else
   # On NextStep and OpenStep, the `mkdir' command does not
   # recognize any option.  It will interpret all options as
@@ -856,26 +701,15 @@ else
 fi
 AC_SUBST([mkdir_p])])
 
-# Helper functions for option handling.                    -*- Autoconf -*-
+# Helper functions for option handling.                     -*- Autoconf -*-
 
-# Copyright (C) 2001, 2002, 2003  Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 2001, 2002, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 2
+# serial 3
 
 # _AM_MANGLE_OPTION(NAME)
 # -----------------------
@@ -900,28 +734,16 @@ AC_DEFUN([_AM_SET_OPTIONS],
 AC_DEFUN([_AM_IF_OPTION],
 [m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])])
 
-#
-# Check to make sure that the build environment is sane.
-#
-
-# Copyright (C) 1996, 1997, 2000, 2001, 2003 Free Software Foundation, Inc.
+# Check to make sure that the build environment is sane.    -*- Autoconf -*-
 
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005
+# Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
-# serial 3
+# serial 4
 
 # AM_SANITY_CHECK
 # ---------------
@@ -964,25 +786,14 @@ Check your system clock])
 fi
 AC_MSG_RESULT(yes)])
 
-# AM_PROG_INSTALL_STRIP
-
-# Copyright (C) 2001, 2003 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2, or (at your option)
-# any later version.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-# 02111-1307, USA.
+# Copyright (C) 2001, 2003, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
 
+# AM_PROG_INSTALL_STRIP
+# ---------------------
 # One issue with vendor `install' (even GNU) is that you can't
 # specify the program used to strip binaries.  This is especially
 # annoying in cross-compiling environments, where the build's strip
@@ -1003,4 +814,100 @@ fi
 INSTALL_STRIP_PROGRAM="\${SHELL} \$(install_sh) -c -s"
 AC_SUBST([INSTALL_STRIP_PROGRAM])])
 
+# Check how to create a tarball.                            -*- Autoconf -*-
+
+# Copyright (C) 2004, 2005  Free Software Foundation, Inc.
+#
+# This file is free software; the Free Software Foundation
+# gives unlimited permission to copy and/or distribute it,
+# with or without modifications, as long as this notice is preserved.
+
+# serial 2
+
+# _AM_PROG_TAR(FORMAT)
+# --------------------
+# Check how to create a tarball in format FORMAT.
+# FORMAT should be one of `v7', `ustar', or `pax'.
+#
+# Substitute a variable $(am__tar) that is a command
+# writing to stdout a FORMAT-tarball containing the directory
+# $tardir.
+#     tardir=directory && $(am__tar) > result.tar
+#
+# Substitute a variable $(am__untar) that extract such
+# a tarball read from stdin.
+#     $(am__untar) < result.tar
+AC_DEFUN([_AM_PROG_TAR],
+[# Always define AMTAR for backward compatibility.
+AM_MISSING_PROG([AMTAR], [tar])
+m4_if([$1], [v7],
+     [am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'],
+     [m4_case([$1], [ustar],, [pax],,
+              [m4_fatal([Unknown tar format])])
+AC_MSG_CHECKING([how to create a $1 tar archive])
+# Loop over all known methods to create a tar archive until one works.
+_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none'
+_am_tools=${am_cv_prog_tar_$1-$_am_tools}
+# Do not fold the above two line into one, because Tru64 sh and
+# Solaris sh will not grok spaces in the rhs of `-'.
+for _am_tool in $_am_tools
+do
+  case $_am_tool in
+  gnutar)
+    for _am_tar in tar gnutar gtar;
+    do
+      AM_RUN_LOG([$_am_tar --version]) && break
+    done
+    am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"'
+    am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"'
+    am__untar="$_am_tar -xf -"
+    ;;
+  plaintar)
+    # Must skip GNU tar: if it does not support --format= it doesn't create
+    # ustar tarball either.
+    (tar --version) >/dev/null 2>&1 && continue
+    am__tar='tar chf - "$$tardir"'
+    am__tar_='tar chf - "$tardir"'
+    am__untar='tar xf -'
+    ;;
+  pax)
+    am__tar='pax -L -x $1 -w "$$tardir"'
+    am__tar_='pax -L -x $1 -w "$tardir"'
+    am__untar='pax -r'
+    ;;
+  cpio)
+    am__tar='find "$$tardir" -print | cpio -o -H $1 -L'
+    am__tar_='find "$tardir" -print | cpio -o -H $1 -L'
+    am__untar='cpio -i -H $1 -d'
+    ;;
+  none)
+    am__tar=false
+    am__tar_=false
+    am__untar=false
+    ;;
+  esac
+
+  # If the value was cached, stop now.  We just wanted to have am__tar
+  # and am__untar set.
+  test -n "${am_cv_prog_tar_$1}" && break
+
+  # tar/untar a dummy directory, and stop if the command works
+  rm -rf conftest.dir
+  mkdir conftest.dir
+  echo GrepMe > conftest.dir/file
+  AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar])
+  rm -rf conftest.dir
+  if test -s conftest.tar; then
+    AM_RUN_LOG([$am__untar <conftest.tar])
+    grep GrepMe conftest.dir/file >/dev/null 2>&1 && break
+  fi
+done
+rm -rf conftest.dir
+
+AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool])
+AC_MSG_RESULT([$am_cv_prog_tar_$1])])
+AC_SUBST([am__tar])
+AC_SUBST([am__untar])
+]) # _AM_PROG_TAR
+
 m4_include([acinclude.m4])
diff --git a/gas/app.c b/gas/app.c
index 1dbc49a8cd89..275ad68ebb0b 100644
--- a/gas/app.c
+++ b/gas/app.c
@@ -1,6 +1,6 @@
 /* This is the Assembler Pre-Processor
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2002, 2003
+   1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Modified by Allen Wirfs-Brock, Instantiations Inc 2/90.  */
 /* App, the assembler pre-processor.  This pre-processor strips out excess
@@ -345,6 +345,8 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
   char *fromend;
   int fromlen;
   register int ch, ch2 = 0;
+  /* Character that started the string we're working on.  */
+  static char quotechar;
 
   /*State 0: beginning of normal line
 	  1: After first whitespace on line (flush more white)
@@ -374,6 +376,10 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	 15: After seeing a `(' at state 1, looking for a `)' as
 	     predicate.
 #endif
+#ifdef TC_Z80
+	 16: After seeing an 'a' or an 'A' at the start of a symbol
+	 17: After seeing an 'f' or an 'F' in state 16
+#endif
 	  */
 
   /* I added states 9 and 10 because the MIPS ECOFF assembler uses
@@ -536,11 +542,8 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	    for (s = from; s < fromend; s++)
 	      {
 		ch = *s;
-		/* This condition must be changed if the type of any
-		   other character can be LEX_IS_STRINGQUOTE.  */
 		if (ch == '\\'
-		    || ch == '"'
-		    || ch == '\''
+		    || ch == quotechar
 		    || ch == '\n')
 		  break;
 	      }
@@ -558,12 +561,12 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  ch = GET ();
 	  if (ch == EOF)
 	    {
-	      as_warn (_("end of file in string; inserted '\"'"));
+	      as_warn (_("end of file in string; '%c' inserted"), quotechar);
 	      state = old_state;
 	      UNGET ('\n');
-	      PUT ('"');
+	      PUT (quotechar);
 	    }
-	  else if (lex[ch] == LEX_IS_STRINGQUOTE)
+	  else if (ch == quotechar)
 	    {
 	      state = old_state;
 	      PUT (ch);
@@ -603,8 +606,8 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	      continue;
 
 	    case EOF:
-	      as_warn (_("end of file in string; '\"' inserted"));
-	      PUT ('"');
+	      as_warn (_("end of file in string; '%c' inserted"), quotechar);
+	      PUT (quotechar);
 	      continue;
 
 	    case '"':
@@ -638,10 +641,9 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 
 	case 7:
 	  ch = GET ();
+	  quotechar = ch;
 	  state = 5;
 	  old_state = 8;
-	  if (ch == EOF)
-	    goto fromeof;
 	  PUT (ch);
 	  continue;
 
@@ -667,6 +669,32 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  PUT ('|');
 	  continue;
 #endif
+#ifdef TC_Z80
+	case 16:
+	  /* We have seen an 'a' at the start of a symbol, look for an 'f'.  */
+	  ch = GET ();
+	  if (ch == 'f' || ch == 'F') 
+	    {
+	      state = 17;
+	      PUT (ch);
+	    }
+	  else
+	    {
+	      state = 9;
+	      break;
+	    }
+	case 17:
+	  /* We have seen "af" at the start of a symbol,
+	     a ' here is a part of that symbol.  */
+	  ch = GET ();
+	  state = 9;
+	  if (ch == '\'')
+	    /* Change to avoid warning about unclosed string.  */
+	    PUT ('`');
+	  else
+	    UNGET (ch);
+	  break;
+#endif
 	}
 
       /* OK, we are somewhere in states 0 through 4 or 9 through 11.  */
@@ -975,6 +1003,7 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	  break;
 
 	case LEX_IS_STRINGQUOTE:
+	  quotechar = ch;
 	  if (state == 10)
 	    {
 	      /* Preserve the whitespace in foo "bar".  */
@@ -1243,6 +1272,30 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	      break;
 	    }
 
+#ifdef TC_Z80
+	  /* "af'" is a symbol containing '\''.  */
+	  if (state == 3 && (ch == 'a' || ch == 'A')) 
+	    {
+	      state = 16;
+	      PUT (ch);
+	      ch = GET ();
+	      if (ch == 'f' || ch == 'F') 
+		{
+		  state = 17;
+		  PUT (ch);
+		  break;
+		}
+	      else
+		{
+		  state = 9;
+		  if (!IS_SYMBOL_COMPONENT (ch)) 
+		    {
+		      UNGET (ch);
+		      break;
+		    }
+		}
+	    }
+#endif
 	  if (state == 3)
 	    state = 9;
 
@@ -1282,26 +1335,11 @@ do_scrub_chars (int (*get) (char *, int), char *tostart, int tolen)
 	      if (len > 0)
 		{
 		  PUT (ch);
-		  if (len > 8)
-		    {
-		      memcpy (to, from, len);
-		      to += len;
-		      from += len;
-		    }
-		  else
-		    {
-		      switch (len)
-			{
-			case 8: *to++ = *from++;
-			case 7: *to++ = *from++;
-			case 6: *to++ = *from++;
-			case 5: *to++ = *from++;
-			case 4: *to++ = *from++;
-			case 3: *to++ = *from++;
-			case 2: *to++ = *from++;
-			case 1: *to++ = *from++;
-			}
-		    }
+		  memcpy (to, from, len);
+		  to += len;
+		  from += len;
+		  if (to >= toend)
+		    goto tofull;
 		  ch = GET ();
 		}
 	    }
diff --git a/gas/as.c b/gas/as.c
index 0911aa1fa260..727a1dd40ee5 100644
--- a/gas/as.c
+++ b/gas/as.c
@@ -1,6 +1,6 @@
 /* as.c - GAS main program.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Main program for AS; a 32-bit assembler of GNU.
    Understands command arguments.
@@ -42,10 +42,8 @@
 #include "macro.h"
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
-
-#ifdef BFD_ASSEMBLER
+#include "hash.h"
 #include "bfdver.h"
-#endif
 
 #ifdef HAVE_ITBL_CPU
 #include "itbl-ops.h"
@@ -89,11 +87,16 @@ int listing;
 enum debug_info_type debug_type = DEBUG_UNSPECIFIED;
 int use_gnu_debug_info_extensions = 0;
 
+#ifndef MD_DEBUG_FORMAT_SELECTOR
+#define MD_DEBUG_FORMAT_SELECTOR NULL
+#endif
+static enum debug_info_type (*md_debug_format_selector) (int *) = MD_DEBUG_FORMAT_SELECTOR;
+
 /* Maximum level of macro nesting.  */
 int max_macro_nest = 100;
 
 /* argv[0]  */
-char * myname;
+static char * myname;
 
 /* The default obstack chunk size.  If we set this to zero, the
    obstack code will use whatever will fit in a 4096 byte block.  */
@@ -106,13 +109,11 @@ int debug_memory = 0;
 /* Enable verbose mode.  */
 int verbose = 0;
 
-#ifdef BFD_ASSEMBLER
 segT reg_section;
 segT expr_section;
 segT text_section;
 segT data_section;
 segT bss_section;
-#endif
 
 /* Name of listing file.  */
 static char *listing_filename = NULL;
@@ -123,6 +124,8 @@ static struct itbl_file_list *itbl_files;
 
 static long start_time;
 
+static int flag_macro_alternate;
+
 
 #ifdef USE_EMULATIONS
 #define EMULATION_ENVIRON "AS_EMULATION"
@@ -217,13 +220,8 @@ print_version_id (void)
     return;
   printed = 1;
 
-#ifdef BFD_ASSEMBLER
-  fprintf (stderr, _("GNU assembler version %s (%s) using BFD version %s"),
+  fprintf (stderr, _("GNU assembler version %s (%s) using BFD version %s\n"),
 	   VERSION, TARGET_ALIAS, BFD_VERSION_STRING);
-#else
-  fprintf (stderr, _("GNU assembler version %s (%s)"), VERSION, TARGET_ALIAS);
-#endif
-  fprintf (stderr, "\n");
 }
 
 static void
@@ -245,6 +243,8 @@ Options:\n\
                       	  =FILE  list to FILE (must be last sub-option)\n"));
 
   fprintf (stream, _("\
+  --alternate             initially turn on alternate macro syntax\n"));
+  fprintf (stream, _("\
   -D                      produce assembler debugging messages\n"));
   fprintf (stream, _("\
   --defsym SYM=VAL        define symbol SYM to given value\n"));
@@ -266,7 +266,7 @@ Options:\n\
                           emulate output (default %s)\n"), def_em);
   }
 #endif
-#if defined BFD_ASSEMBLER && (defined OBJ_ELF || defined OBJ_MAYBE_ELF)
+#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
   fprintf (stream, _("\
   --execstack             require executable stack for this object\n"));
   fprintf (stream, _("\
@@ -275,11 +275,15 @@ Options:\n\
   fprintf (stream, _("\
   -f                      skip whitespace and comment preprocessing\n"));
   fprintf (stream, _("\
-  --gstabs                generate stabs debugging information\n"));
+  -g --gen-debug          generate debugging information\n"));
+  fprintf (stream, _("\
+  --gstabs                generate STABS debugging information\n"));
   fprintf (stream, _("\
-  --gstabs+               generate stabs debug info with GNU extensions\n"));
+  --gstabs+               generate STABS debug info with GNU extensions\n"));
   fprintf (stream, _("\
-  --gdwarf2               generate DWARF2 debugging information\n"));
+  --gdwarf-2              generate DWARF2 debugging information\n"));
+  fprintf (stream, _("\
+  --hash-size=<value>     set the hash table size close to <value>\n"));
   fprintf (stream, _("\
   --help                  show this message and exit\n"));
   fprintf (stream, _("\
@@ -303,6 +307,10 @@ Options:\n\
   fprintf (stream, _("\
   -R                      fold data section into text section\n"));
   fprintf (stream, _("\
+  --reduce-memory-overheads \n\
+                          prefer smaller memory use at the cost of longer\n\
+                          assembly times\n"));
+  fprintf (stream, _("\
   --statistics            print various measured statistics from execution\n"));
   fprintf (stream, _("\
   --strip-local-absolute  strip local absolute symbols\n"));
@@ -338,6 +346,8 @@ Options:\n\
   fprintf (stream, _("\
   --listing-cont-lines    set the maximum number of continuation lines used\n\
                           for the output data column of the listing\n"));
+  fprintf (stream, _("\
+  @FILE                   read options from FILE\n")); 
 
   md_show_usage (stream);
 
@@ -374,7 +384,7 @@ parse_args (int * pargc, char *** pargv)
     /* -K is not meaningful if .word is not being hacked.  */
     'K',
 #endif
-    'L', 'M', 'R', 'W', 'Z', 'a', ':', ':', 'D', 'f', 'I', ':', 'o', ':',
+    'L', 'M', 'R', 'W', 'Z', 'a', ':', ':', 'D', 'f', 'g', ':',':', 'I', ':', 'o', ':',
 #ifndef VMS
     /* -v takes an argument on VMS, so we don't make it a generic
        option.  */
@@ -407,59 +417,80 @@ parse_args (int * pargc, char *** pargv)
       OPTION_DEPFILE,
       OPTION_GSTABS,
       OPTION_GSTABS_PLUS,
+      OPTION_GDWARF2,
       OPTION_STRIP_LOCAL_ABSOLUTE,
       OPTION_TRADITIONAL_FORMAT,
-      OPTION_GDWARF2,
       OPTION_WARN,
       OPTION_TARGET_HELP,
       OPTION_EXECSTACK,
       OPTION_NOEXECSTACK,
+      OPTION_ALTERNATE,
+      OPTION_AL,
+      OPTION_HASH_TABLE_SIZE,
+      OPTION_REDUCE_MEMORY_OVERHEADS,
       OPTION_WARN_FATAL
+    /* When you add options here, check that they do
+       not collide with OPTION_MD_BASE.  See as.h.  */
     };
   
   static const struct option std_longopts[] =
   {
-    {"help", no_argument, NULL, OPTION_HELP},
-    /* getopt allows abbreviations, so we do this to stop it from
-       treating -k as an abbreviation for --keep-locals.  Some
-       ports use -k to enable PIC assembly.  */
-    {"keep-locals", no_argument, NULL, 'L'},
-    {"keep-locals", no_argument, NULL, 'L'},
-    {"mri", no_argument, NULL, 'M'},
-    {"nocpp", no_argument, NULL, OPTION_NOCPP},
-    {"statistics", no_argument, NULL, OPTION_STATISTICS},
-    {"version", no_argument, NULL, OPTION_VERSION},
-    {"dump-config", no_argument, NULL, OPTION_DUMPCONFIG},
-    {"verbose", no_argument, NULL, OPTION_VERBOSE},
-    {"emulation", required_argument, NULL, OPTION_EMULATION},
-    {"defsym", required_argument, NULL, OPTION_DEFSYM},
+    /* Note: commas are placed at the start of the line rather than
+       the end of the preceeding line so that it is simpler to
+       selectively add and remove lines from this list.  */
+    {"alternate", no_argument, NULL, OPTION_ALTERNATE}
+    /* The entry for "a" is here to prevent getopt_long_only() from
+       considering that -a is an abbreviation for --alternate.  This is
+       necessary because -a=<FILE> is a valid switch but getopt would
+       normally reject it since --alternate does not take an argument.  */
+    ,{"a", optional_argument, NULL, 'a'}
+    /* Handle -al=<FILE>.  */
+    ,{"al", optional_argument, NULL, OPTION_AL}
+    ,{"defsym", required_argument, NULL, OPTION_DEFSYM}
+    ,{"dump-config", no_argument, NULL, OPTION_DUMPCONFIG}
+    ,{"emulation", required_argument, NULL, OPTION_EMULATION}
+#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
+    ,{"execstack", no_argument, NULL, OPTION_EXECSTACK}
+    ,{"noexecstack", no_argument, NULL, OPTION_NOEXECSTACK}
+#endif
+    ,{"fatal-warnings", no_argument, NULL, OPTION_WARN_FATAL}
+    ,{"gdwarf-2", no_argument, NULL, OPTION_GDWARF2}
+    /* GCC uses --gdwarf-2 but GAS uses to use --gdwarf2,
+       so we keep it here for backwards compatibility.  */
+    ,{"gdwarf2", no_argument, NULL, OPTION_GDWARF2}
+    ,{"gen-debug", no_argument, NULL, 'g'}
+    ,{"gstabs", no_argument, NULL, OPTION_GSTABS}
+    ,{"gstabs+", no_argument, NULL, OPTION_GSTABS_PLUS}
+    ,{"hash-size", required_argument, NULL, OPTION_HASH_TABLE_SIZE}
+    ,{"help", no_argument, NULL, OPTION_HELP}
     /* New option for extending instruction set (see also -t above).
        The "-t file" or "--itbl file" option extends the basic set of
        valid instructions by reading "file", a text file containing a
        list of instruction formats.  The additional opcodes and their
        formats are added to the built-in set of instructions, and
        mnemonics for new registers may also be defined.  */
-    {"itbl", required_argument, NULL, OPTION_INSTTBL},
-    {"listing-lhs-width", required_argument, NULL, OPTION_LISTING_LHS_WIDTH},
-    {"listing-lhs-width2", required_argument, NULL, OPTION_LISTING_LHS_WIDTH2},
-    {"listing-rhs-width", required_argument, NULL, OPTION_LISTING_RHS_WIDTH},
-    {"listing-cont-lines", required_argument, NULL, OPTION_LISTING_CONT_LINES},
-    {"MD", required_argument, NULL, OPTION_DEPFILE},
-    {"gstabs", no_argument, NULL, OPTION_GSTABS},
-    {"gstabs+", no_argument, NULL, OPTION_GSTABS_PLUS},
-    {"strip-local-absolute", no_argument, NULL, OPTION_STRIP_LOCAL_ABSOLUTE},
-    {"traditional-format", no_argument, NULL, OPTION_TRADITIONAL_FORMAT},
-    {"gdwarf2", no_argument, NULL, OPTION_GDWARF2},
-    {"no-warn", no_argument, NULL, 'W'},
-    {"warn", no_argument, NULL, OPTION_WARN},
-    {"target-help", no_argument, NULL, OPTION_TARGET_HELP},
-#if defined BFD_ASSEMBLER && (defined OBJ_ELF || defined OBJ_MAYBE_ELF)
-    {"execstack", no_argument, NULL, OPTION_EXECSTACK},
-    {"noexecstack", no_argument, NULL, OPTION_NOEXECSTACK},
-#endif
-    {"fatal-warnings", no_argument, NULL, OPTION_WARN_FATAL}
-    /* When you add options here, check that they do not collide with
-       OPTION_MD_BASE.  See as.h.  */
+    ,{"itbl", required_argument, NULL, OPTION_INSTTBL}
+    /* getopt allows abbreviations, so we do this to stop it from
+       treating -k as an abbreviation for --keep-locals.  Some
+       ports use -k to enable PIC assembly.  */
+    ,{"keep-locals", no_argument, NULL, 'L'}
+    ,{"keep-locals", no_argument, NULL, 'L'}
+    ,{"listing-lhs-width", required_argument, NULL, OPTION_LISTING_LHS_WIDTH}
+    ,{"listing-lhs-width2", required_argument, NULL, OPTION_LISTING_LHS_WIDTH2}
+    ,{"listing-rhs-width", required_argument, NULL, OPTION_LISTING_RHS_WIDTH}
+    ,{"listing-cont-lines", required_argument, NULL, OPTION_LISTING_CONT_LINES}
+    ,{"MD", required_argument, NULL, OPTION_DEPFILE}
+    ,{"mri", no_argument, NULL, 'M'}
+    ,{"nocpp", no_argument, NULL, OPTION_NOCPP}
+    ,{"no-warn", no_argument, NULL, 'W'}
+    ,{"reduce-memory-overheads", no_argument, NULL, OPTION_REDUCE_MEMORY_OVERHEADS}
+    ,{"statistics", no_argument, NULL, OPTION_STATISTICS}
+    ,{"strip-local-absolute", no_argument, NULL, OPTION_STRIP_LOCAL_ABSOLUTE}
+    ,{"version", no_argument, NULL, OPTION_VERSION}
+    ,{"verbose", no_argument, NULL, OPTION_VERBOSE}
+    ,{"target-help", no_argument, NULL, OPTION_TARGET_HELP}
+    ,{"traditional-format", no_argument, NULL, OPTION_TRADITIONAL_FORMAT}
+    ,{"warn", no_argument, NULL, OPTION_WARN}
   };
 
   /* Construct the option lists from the standard list and the target
@@ -520,6 +551,8 @@ parse_args (int * pargc, char *** pargv)
 		verbose = 1;
 	      break;
 	    }
+	  else
+	    as_bad (_("unrecognized option -%c%s"), optc, optarg ? optarg : "");
 	  /* Fall through.  */
 
 	case '?':
@@ -557,12 +590,8 @@ parse_args (int * pargc, char *** pargv)
 
 	case OPTION_VERSION:
 	  /* This output is intended to follow the GNU standards document.  */
-#ifdef BFD_ASSEMBLER
 	  printf (_("GNU assembler %s\n"), BFD_VERSION_STRING);
-#else
-	  printf (_("GNU assembler %s\n"), VERSION);
-#endif
-	  printf (_("Copyright 2002 Free Software Foundation, Inc.\n"));
+	  printf (_("Copyright 2005 Free Software Foundation, Inc.\n"));
 	  printf (_("\
 This program is free software; you may redistribute it under the terms of\n\
 the GNU General Public License.  This program has absolutely no warranty.\n"));
@@ -602,11 +631,7 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	    if (*s == '\0')
 	      as_fatal (_("bad defsym; format is --defsym name=value"));
 	    *s++ = '\0';
-#ifdef BFD_ASSEMBLER
 	    i = bfd_scan_vma (s, (const char **) NULL, 0);
-#else
-	    i = strtol (s, (char **) NULL, 0);
-#endif
 	    n = xmalloc (sizeof *n);
 	    n->next = defsyms;
 	    n->name = optarg;
@@ -648,6 +673,22 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	  start_dependencies (optarg);
 	  break;
 
+	case 'g':
+	  /* Some backends, eg Alpha and Mips, use the -g switch for their
+	     own purposes.  So we check here for an explicit -g and allow
+	     the backend to decide if it wants to process it.  */
+	  if (   old_argv[optind - 1][1] == 'g'
+	      && md_parse_option (optc, optarg))
+	    continue;
+
+	  if (md_debug_format_selector)
+	    debug_type = md_debug_format_selector (& use_gnu_debug_info_extensions);
+	  else if (IS_ELF)
+	    debug_type = DEBUG_DWARF2;
+	  else
+	    debug_type = DEBUG_STABS;
+	  break;
+
 	case OPTION_GSTABS_PLUS:
 	  use_gnu_debug_info_extensions = 1;
 	  /* Fall through.  */
@@ -680,6 +721,7 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	case OPTION_LISTING_LHS_WIDTH2:
 	  {
 	    int tmp = atoi (optarg);
+
 	    if (tmp > listing_lhs_width)
 	      listing_lhs_width_second = tmp;
 	  }
@@ -716,7 +758,7 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	  flag_fatal_warnings = 1;
 	  break;
 
-#if defined BFD_ASSEMBLER && (defined OBJ_ELF || defined OBJ_MAYBE_ELF)
+#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
 	case OPTION_EXECSTACK:
 	  flag_execstack = 1;
 	  flag_noexecstack = 0;
@@ -731,9 +773,31 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	  flag_always_generate_output = 1;
 	  break;
 
+ 	case OPTION_AL:
+	  listing |= LISTING_LISTING;
+	  if (optarg)
+	    listing_filename = xstrdup (optarg);
+	  break;
+
+ 	case OPTION_ALTERNATE:
+ 	  optarg = old_argv [optind - 1];
+ 	  while (* optarg == '-')
+ 	    optarg ++;
+
+ 	  if (strcmp (optarg, "alternate") == 0)
+ 	    {
+ 	      flag_macro_alternate = 1;
+ 	      break;
+ 	    }
+ 	  optarg ++;
+ 	  /* Fall through.  */
+
 	case 'a':
 	  if (optarg)
 	    {
+	      if (optarg != old_argv[optind] && optarg[-1] == '=')
+		--optarg;
+
 	      if (md_parse_option (optc, optarg) != 0)
 		break;
 
@@ -790,6 +854,7 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	case 'I':
 	  {			/* Include file directory.  */
 	    char *temp = xstrdup (optarg);
+
 	    add_include_dir (temp);
 	    break;
 	  }
@@ -804,6 +869,24 @@ the GNU General Public License.  This program has absolutely no warranty.\n"));
 	case 'X':
 	  /* -X means treat warnings as errors.  */
 	  break;
+
+	case OPTION_REDUCE_MEMORY_OVERHEADS:
+	  /* The only change we make at the moment is to reduce
+	     the size of the hash tables that we use.  */
+	  set_gas_hash_table_size (4051);
+	  break;
+
+	case OPTION_HASH_TABLE_SIZE:
+	  {
+	    unsigned long new_size;
+
+            new_size = strtoul (optarg, NULL, 0);
+            if (new_size)
+              set_gas_hash_table_size (new_size);
+            else
+              as_fatal (_("--hash-size needs a numeric argument"));
+	    break;
+	  }
 	}
     }
 
@@ -847,6 +930,14 @@ dump_statistics (void)
 #endif
 }
 
+#ifndef OBJ_VMS
+static void
+close_output_file (void)
+{
+  output_file_close (out_file_name);
+}
+#endif
+
 /* The interface between the macro code and gas expression handling.  */
 
 static int
@@ -859,7 +950,7 @@ macro_expr (const char *emsg, int idx, sb *in, int *val)
 
   hold = input_line_pointer;
   input_line_pointer = in->ptr + idx;
-  expression (&ex);
+  expression_and_evaluate (&ex);
   idx = input_line_pointer - in->ptr;
   input_line_pointer = hold;
 
@@ -884,44 +975,10 @@ static void
 perform_an_assembly_pass (int argc, char ** argv)
 {
   int saw_a_file = 0;
-#ifdef BFD_ASSEMBLER
   flagword applicable;
-#endif
 
   need_pass_2 = 0;
 
-#ifndef BFD_ASSEMBLER
-#ifdef MANY_SEGMENTS
-  {
-    unsigned int i;
-    for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-      segment_info[i].fix_root = 0;
-  }
-  /* Create the three fixed ones.  */
-  {
-    segT seg;
-
-#ifdef TE_APOLLO
-    seg = subseg_new (".wtext", 0);
-#else
-    seg = subseg_new (".text", 0);
-#endif
-    assert (seg == SEG_E0);
-    seg = subseg_new (".data", 0);
-    assert (seg == SEG_E1);
-    seg = subseg_new (".bss", 0);
-    assert (seg == SEG_E2);
-#ifdef TE_APOLLO
-    create_target_segments ();
-#endif
-  }
-
-#else /* not MANY_SEGMENTS.  */
-  text_fix_root = NULL;
-  data_fix_root = NULL;
-  bss_fix_root = NULL;
-#endif /* not MANY_SEGMENTS.  */
-#else /* BFD_ASSEMBLER.  */
   /* Create the standard sections, and those the assembler uses
      internally.  */
   text_section = subseg_new (TEXT_SECTION_NAME, 0);
@@ -943,12 +1000,10 @@ perform_an_assembly_pass (int argc, char ** argv)
   reg_section = subseg_new ("*GAS `reg' section*", 0);
   expr_section = subseg_new ("*GAS `expr' section*", 0);
 
-#endif /* BFD_ASSEMBLER.  */
-
   subseg_set (text_section, 0);
 
   /* This may add symbol table entries, which requires having an open BFD,
-     and sections already created, in BFD_ASSEMBLER mode.  */
+     and sections already created.  */
   md_begin ();
 
 #ifdef USING_CGEN
@@ -981,7 +1036,6 @@ perform_an_assembly_pass (int argc, char ** argv)
 int
 main (int argc, char ** argv)
 {
-  int macro_alternate;
   int macro_strip_at;
   int keep_it;
 
@@ -1006,6 +1060,8 @@ main (int argc, char ** argv)
   myname = argv[0];
   xmalloc_set_program_name (myname);
 
+  expandargv (&argc, &argv);
+
   START_PROGRESS (myname, 0);
 
 #ifndef OBJ_DEFAULT_OUTPUT_FILE_NAME
@@ -1015,47 +1071,43 @@ main (int argc, char ** argv)
   out_file_name = OBJ_DEFAULT_OUTPUT_FILE_NAME;
 
   hex_init ();
-#ifdef BFD_ASSEMBLER
   bfd_init ();
   bfd_set_error_program_name (myname);
-#endif
 
 #ifdef USE_EMULATIONS
   select_emulation_mode (argc, argv);
 #endif
 
   PROGRESS (1);
+  /* Call parse_args before any of the init/begin functions
+     so that switches like --hash-size can be honored.  */
+  parse_args (&argc, &argv);
   symbol_begin ();
   frag_init ();
   subsegs_begin ();
-  parse_args (&argc, &argv);
   read_begin ();
   input_scrub_begin ();
   expr_begin ();
 
+#ifndef OBJ_VMS /* Does its own file handling.  */
+  /* It has to be called after dump_statistics ().  */
+  xatexit (close_output_file);
+#endif
+
   if (flag_print_statistics)
     xatexit (dump_statistics);
 
-  macro_alternate = 0;
   macro_strip_at = 0;
 #ifdef TC_I960
   macro_strip_at = flag_mri;
 #endif
-#ifdef TC_A29K
-  /* For compatibility with the AMD 29K family macro assembler
-     specification.  */
-  macro_alternate = 1;
-  macro_strip_at = 1;
-#endif
 
-  macro_init (macro_alternate, flag_mri, macro_strip_at, macro_expr);
+  macro_init (flag_macro_alternate, flag_mri, macro_strip_at, macro_expr);
 
   PROGRESS (1);
 
-#ifdef BFD_ASSEMBLER
   output_file_create (out_file_name);
   assert (stdoutput != 0);
-#endif
 
 #ifdef tc_init_after_args
   tc_init_after_args ();
@@ -1090,7 +1142,7 @@ main (int argc, char ** argv)
   md_end ();
 #endif
 
-#if defined BFD_ASSEMBLER && (defined OBJ_ELF || defined OBJ_MAYBE_ELF)
+#if defined OBJ_ELF || defined OBJ_MAYBE_ELF
   if ((flag_execstack || flag_noexecstack)
       && OUTPUT_FLAVOR == bfd_target_elf_flavour)
     {
@@ -1117,13 +1169,11 @@ main (int argc, char ** argv)
   else
     keep_it = 0;
 
-#if defined (BFD_ASSEMBLER) || !defined (BFD)
   /* This used to be done at the start of write_object_file in
      write.c, but that caused problems when doing listings when
      keep_it was zero.  This could probably be moved above md_end, but
      I didn't want to risk the change.  */
   subsegs_finish ();
-#endif
 
   if (keep_it)
     write_object_file ();
@@ -1132,13 +1182,6 @@ main (int argc, char ** argv)
   listing_print (listing_filename);
 #endif
 
-#ifndef OBJ_VMS /* Does its own file handling.  */
-#ifndef BFD_ASSEMBLER
-  if (keep_it)
-#endif
-    output_file_close (out_file_name);
-#endif
-
   if (flag_fatal_warnings && had_warnings () > 0 && had_errors () == 0)
     as_bad (_("%d warnings, treating warnings as errors"), had_warnings ());
 
@@ -1146,7 +1189,7 @@ main (int argc, char ** argv)
     keep_it = 0;
 
   if (!keep_it)
-    unlink (out_file_name);
+    unlink_if_ordinary (out_file_name);
 
   input_scrub_end ();
 
@@ -1162,4 +1205,3 @@ main (int argc, char ** argv)
 
   xexit (EXIT_SUCCESS);
 }
-
diff --git a/gas/as.h b/gas/as.h
index 890ecd8f1056..2f92c2ed7748 100644
--- a/gas/as.h
+++ b/gas/as.h
@@ -1,6 +1,6 @@
 /* as.h - global header file
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,25 +17,24 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef GAS
 #define GAS 1
 /* I think this stuff is largely out of date.  xoxorich.
- *
- * CAPITALISED names are #defined.
- * "lowercaseH" is #defined if "lowercase.h" has been #include-d.
- * "lowercaseT" is a typedef of "lowercase" objects.
- * "lowercaseP" is type "pointer to object of type 'lowercase'".
- * "lowercaseS" is typedef struct ... lowercaseS.
- *
- * #define DEBUG to enable all the "know" assertion tests.
- * #define SUSPECT when debugging hash code.
- * #define COMMON as "extern" for all modules except one, where you #define
- *	COMMON as "".
- * If TEST is #defined, then we are testing a module: #define COMMON as "".
- */
+ 
+   CAPITALISED names are #defined.
+   "lowercaseH" is #defined if "lowercase.h" has been #include-d.
+   "lowercaseT" is a typedef of "lowercase" objects.
+   "lowercaseP" is type "pointer to object of type 'lowercase'".
+   "lowercaseS" is typedef struct ... lowercaseS.
+  
+   #define DEBUG to enable all the "know" assertion tests.
+   #define SUSPECT when debugging hash code.
+   #define COMMON as "extern" for all modules except one, where you #define
+  	COMMON as "".
+   If TEST is #defined, then we are testing a module: #define COMMON as "".  */
 
 #include "config.h"
 #include "bin-bugs.h"
@@ -69,6 +68,19 @@ extern void *alloca ();
 # endif /* HAVE_ALLOCA_H */
 #endif /* __GNUC__ */
 
+/* Prefer varargs for non-ANSI compiler, since some will barf if the
+   ellipsis definition is used with a no-arguments declaration.  */
+#if defined (HAVE_VARARGS_H) && !defined (__STDC__)
+#undef HAVE_STDARG_H
+#endif
+
+#if defined (HAVE_STDARG_H)
+#define USE_STDARG
+#endif
+#if !defined (USE_STDARG) && defined (HAVE_VARARGS_H)
+#define USE_VARARGS
+#endif
+
 /* Now, tend to the rest of the configuration.  */
 
 /* System include files first...  */
@@ -91,6 +103,27 @@ extern void *alloca ();
 #include <sys/types.h>
 #endif
 
+#ifdef HAVE_ERRNO_H
+#include <errno.h>
+#endif
+
+#ifdef USE_STDARG
+#include <stdarg.h>
+#endif
+
+#ifdef USE_VARARGS
+#include <varargs.h>
+#endif
+
+#if !defined (USE_STDARG) && !defined (USE_VARARGS)
+/* Roll our own.  */
+#define va_alist REST
+#define va_dcl
+typedef int * va_list;
+#define va_start(ARGS)	ARGS = &REST
+#define va_end(ARGS)
+#endif
+
 #include "getopt.h"
 /* The first getopt value for machine-independent long options.
    150 isn't special; it's just an arbitrary non-ASCII char value.  */
@@ -105,60 +138,49 @@ extern void *alloca ();
 #if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 6)
 #define __PRETTY_FUNCTION__  ((char*)0)
 #endif
-#if 0
-
-/* Handle lossage with assert.h.  */
-#ifndef BROKEN_ASSERT
-#include <assert.h>
-#else /* BROKEN_ASSERT */
-#ifndef NDEBUG
-#define assert(p) ((p) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0))
-#else
-#define assert(p) ((p), 0)
-#endif
-#endif /* BROKEN_ASSERT */
-
-#else
-
-#define assert(P) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0))
+#define assert(P) \
+  ((void) ((P) ? 0 : (as_assert (__FILE__, __LINE__, __PRETTY_FUNCTION__), 0)))
 #undef abort
 #define abort()		as_abort (__FILE__, __LINE__, __PRETTY_FUNCTION__)
 
-#endif
-
 /* Now GNU header files...  */
 #include "ansidecl.h"
-#ifdef BFD_ASSEMBLER
 #include "bfd.h"
-#endif
 #include "libiberty.h"
 
 /* Define the standard progress macros.  */
 #include "progress.h"
 
 /* This doesn't get taken care of anywhere.  */
-#ifndef __MWERKS__  /* Metrowerks C chokes on the "defined (inline)" */
+#ifndef __MWERKS__  /* Metrowerks C chokes on the "defined (inline)"  */
 #if !defined (__GNUC__) && !defined (inline)
 #define inline
 #endif
 #endif /* !__MWERKS__ */
 
 /* Other stuff from config.h.  */
-#ifdef NEED_DECLARATION_STRSTR
-extern char *strstr ();
+#ifdef NEED_DECLARATION_ENVIRON
+extern char **environ;
 #endif
-#ifdef NEED_DECLARATION_MALLOC
-extern PTR malloc ();
-extern PTR realloc ();
+#ifdef NEED_DECLARATION_ERRNO
+extern int errno;
+#endif
+#ifdef NEED_DECLARATION_FFS
+extern int ffs (int);
 #endif
 #ifdef NEED_DECLARATION_FREE
 extern void free ();
 #endif
-#ifdef NEED_DECLARATION_ERRNO
-extern int errno;
+#ifdef NEED_DECLARATION_MALLOC
+extern PTR malloc ();
+extern PTR realloc ();
 #endif
-#ifdef NEED_DECLARATION_ENVIRON
-extern char **environ;
+#ifdef NEED_DECLARATION_STRSTR
+extern char *strstr ();
+#endif
+
+#if !HAVE_DECL_VSNPRINTF
+extern int vsnprintf(char *, size_t, const char *, va_list);
 #endif
 
 /* This is needed for VMS.  */
@@ -221,33 +243,28 @@ extern char **environ;
 
 /* These are assembler-wide concepts */
 
-#ifdef BFD_ASSEMBLER
 extern bfd *stdoutput;
 typedef bfd_vma addressT;
 typedef bfd_signed_vma offsetT;
-#else
-typedef unsigned long addressT;
-typedef long offsetT;
-#endif
 
 /* Type of symbol value, etc.  For use in prototypes.  */
 typedef addressT valueT;
 
 #ifndef COMMON
 #ifdef TEST
-#define COMMON			/* declare our COMMONs storage here.  */
+#define COMMON			/* Declare our COMMONs storage here.  */
 #else
-#define COMMON extern		/* our commons live elsewhere */
+#define COMMON extern		/* Our commons live elsewhere.  */
 #endif
 #endif
 /* COMMON now defined */
 
 #ifdef DEBUG
 #ifndef know
-#define know(p) assert(p)	/* Verify our assumptions! */
+#define know(p) assert(p)	/* Verify our assumptions!  */
 #endif /* not yet defined */
 #else
-#define know(p)			/* know() checks are no-op.ed */
+#define know(p)			/* know() checks are no-op.ed  */
 #endif
 
 /* input_scrub.c */
@@ -257,90 +274,36 @@ typedef addressT valueT;
 
 /* subsegs.c     Sub-segments. Also, segment(=expression type)s.*/
 
-#ifndef BFD_ASSEMBLER
-
-#ifdef MANY_SEGMENTS
-#include "bfd.h"
-#define N_SEGMENTS 40
-#define SEG_NORMAL(x) ((x) >= SEG_E0 && (x) <= SEG_E39)
-#define SEG_LIST SEG_E0,SEG_E1,SEG_E2,SEG_E3,SEG_E4,SEG_E5,SEG_E6,SEG_E7,SEG_E8,SEG_E9,\
-		 SEG_E10,SEG_E11,SEG_E12,SEG_E13,SEG_E14,SEG_E15,SEG_E16,SEG_E17,SEG_E18,SEG_E19,\
-		 SEG_E20,SEG_E21,SEG_E22,SEG_E23,SEG_E24,SEG_E25,SEG_E26,SEG_E27,SEG_E28,SEG_E29,\
-		 SEG_E30,SEG_E31,SEG_E32,SEG_E33,SEG_E34,SEG_E35,SEG_E36,SEG_E37,SEG_E38,SEG_E39
-#define SEG_TEXT SEG_E0
-#define SEG_DATA SEG_E1
-#define SEG_BSS SEG_E2
-#define SEG_LAST SEG_E39
-#else
-#define N_SEGMENTS 3
-#define SEG_NORMAL(x) ((x) == SEG_TEXT || (x) == SEG_DATA || (x) == SEG_BSS)
-#define SEG_LIST SEG_TEXT,SEG_DATA,SEG_BSS
-#endif
-
-typedef enum _segT {
-  SEG_ABSOLUTE = 0,
-  SEG_LIST,
-  SEG_UNKNOWN,
-  SEG_GOOF,			/* Only happens if AS has a logic error.  */
-  /* Invented so we don't crash printing */
-  /* error message involving weird segment.  */
-  SEG_EXPR,			/* Intermediate expression values.  */
-  SEG_DEBUG,			/* Debug segment */
-  SEG_NTV,			/* Transfert vector preload segment */
-  SEG_PTV,			/* Transfert vector postload segment */
-  SEG_REGISTER			/* Mythical: a register-valued expression */
-} segT;
-
-#define SEG_MAXIMUM_ORDINAL (SEG_REGISTER)
-#else
 typedef asection *segT;
-#define SEG_NORMAL(SEG)		((SEG) != absolute_section	\
+#define SEG_NORMAL(SEG)		(   (SEG) != absolute_section	\
 				 && (SEG) != undefined_section	\
 				 && (SEG) != reg_section	\
 				 && (SEG) != expr_section)
-#endif
 typedef int subsegT;
 
-/* What subseg we are accessing now? */
+/* What subseg we are accessing now?  */
 COMMON subsegT now_subseg;
 
 /* Segment our instructions emit to.  */
 COMMON segT now_seg;
 
-#ifdef BFD_ASSEMBLER
 #define segment_name(SEG)	bfd_get_section_name (stdoutput, SEG)
-#else
-extern char const *const seg_name[];
-#define segment_name(SEG)	seg_name[(int) (SEG)]
-#endif
 
-#ifndef BFD_ASSEMBLER
-extern int section_alignment[];
-#endif
-
-#ifdef BFD_ASSEMBLER
 extern segT reg_section, expr_section;
 /* Shouldn't these be eliminated someday?  */
 extern segT text_section, data_section, bss_section;
 #define absolute_section	bfd_abs_section_ptr
 #define undefined_section	bfd_und_section_ptr
-#else
-#define reg_section		SEG_REGISTER
-#define expr_section		SEG_EXPR
-#define text_section		SEG_TEXT
-#define data_section		SEG_DATA
-#define bss_section		SEG_BSS
-#define absolute_section	SEG_ABSOLUTE
-#define undefined_section	SEG_UNKNOWN
-#endif
 
-/* relax() */
+enum _relax_state
+{
+  /* Dummy frag used by listing code.  */
+  rs_dummy = 0,
 
-enum _relax_state {
   /* Variable chars to be repeated fr_offset times.
      Fr_symbol unused. Used with fr_offset == 0 for a
      constant length frag.  */
-  rs_fill = 1,
+  rs_fill,
 
   /* Align.  The fr_offset field holds the power of 2 to which to
      align.  The fr_var field holds the number of characters in the
@@ -368,7 +331,7 @@ enum _relax_state {
   rs_broken_word,
 #endif
 
-  /* machine-specific relaxable (or similarly alterable) instruction */
+  /* Machine specific relaxable (or similarly alterable) instruction.  */
   rs_machine_dependent,
 
   /* .space directive with expression operand that needs to be computed
@@ -397,8 +360,24 @@ typedef unsigned int relax_substateT;
 /* Enough bits for address, but still an integer type.
    Could be a problem, cross-assembling for 64-bit machines.  */
 typedef addressT relax_addressT;
+
+struct relax_type
+{
+  /* Forward reach. Signed number. > 0.  */
+  offsetT rlx_forward;
+  /* Backward reach. Signed number. < 0.  */
+  offsetT rlx_backward;
+
+  /* Bytes length of this address.  */
+  unsigned char rlx_length;
+
+  /* Next longer relax-state.  0 means there is no 'next' relax-state.  */
+  relax_substateT rlx_more;
+};
+
+typedef struct relax_type relax_typeS;
 
-/* main program "as.c" (command arguments etc) */
+/* main program "as.c" (command arguments etc).  */
 
 COMMON unsigned char flag_no_comments; /* -f */
 COMMON unsigned char flag_debug; /* -D */
@@ -466,7 +445,8 @@ extern int listing;
    This is especially relevant to DWARF2, since the compiler may emit line
    number directives that the assembler resolves.  */
 
-enum debug_info_type {
+enum debug_info_type
+{
   DEBUG_UNSPECIFIED,
   DEBUG_NONE,
   DEBUG_STABS,
@@ -488,7 +468,8 @@ extern int verbose;
    increase malloc calls for monitoring memory allocation.  */
 extern int chunksize;
 
-struct _pseudo_type {
+struct _pseudo_type
+{
   /* assembler mnemonic, lower case, no '.' */
   const char *poc_name;
   /* Do the work */
@@ -499,19 +480,6 @@ struct _pseudo_type {
 
 typedef struct _pseudo_type pseudo_typeS;
 
-/* Prefer varargs for non-ANSI compiler, since some will barf if the
-   ellipsis definition is used with a no-arguments declaration.  */
-#if defined (HAVE_VARARGS_H) && !defined (__STDC__)
-#undef HAVE_STDARG_H
-#endif
-
-#if defined (HAVE_STDARG_H)
-#define USE_STDARG
-#endif
-#if !defined (USE_STDARG) && defined (HAVE_VARARGS_H)
-#define USE_VARARGS
-#endif
-
 #ifdef USE_STDARG
 #if (__GNUC__ >= 2) && !defined(VMS)
 /* for use with -Wformat */
@@ -553,54 +521,48 @@ PRINTF_LIKE (as_warn);
 PRINTF_WHERE_LIKE (as_bad_where);
 PRINTF_WHERE_LIKE (as_warn_where);
 
-void as_assert (const char *, int, const char *);
-void as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
-
-void fprint_value (FILE *file, addressT value);
-void sprint_value (char *buf, addressT value);
-
-int had_errors (void);
-int had_warnings (void);
-
-void print_version_id (void);
-char *app_push (void);
-char *atof_ieee (char *str, int what_kind, LITTLENUM_TYPE * words);
-char *input_scrub_include_file (char *filename, char *position);
-extern void input_scrub_insert_line (const char *line);
-extern void input_scrub_insert_file (char *path);
-char *input_scrub_new_file (char *filename);
-char *input_scrub_next_buffer (char **bufp);
-int do_scrub_chars (int (*get) (char *, int), char *to, int tolen);
-int gen_to_words (LITTLENUM_TYPE * words, int precision,
-			  long exponent_bits);
-int had_err (void);
-int ignore_input (void);
-void cond_finish_check (int);
-void cond_exit_macro (int);
-int seen_at_least_1_file (void);
-void app_pop (char *arg);
-void as_howmuch (FILE * stream);
-void as_perror (const char *gripe, const char *filename);
-void as_where (char **namep, unsigned int *linep);
-void bump_line_counters (void);
-void do_scrub_begin (int);
-void input_scrub_begin (void);
-void input_scrub_close (void);
-void input_scrub_end (void);
-int new_logical_line (char *fname, int line_number);
-void subsegs_begin (void);
-void subseg_change (segT seg, int subseg);
-segT subseg_new (const char *name, subsegT subseg);
-segT subseg_force_new (const char *name, subsegT subseg);
-void subseg_set (segT seg, subsegT subseg);
-#ifdef BFD_ASSEMBLER
-segT subseg_get (const char *, int);
-#endif
-int subseg_text_p (segT);
-
-void start_dependencies (char *);
-void register_dependency (char *);
-void print_dependencies (void);
+void   as_assert (const char *, int, const char *);
+void   as_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
+void   sprint_value (char *, addressT);
+int    had_errors (void);
+int    had_warnings (void);
+void   as_warn_value_out_of_range (char *, offsetT, offsetT, offsetT, char *, unsigned);
+void   as_bad_value_out_of_range (char *, offsetT, offsetT, offsetT, char *, unsigned);
+void   print_version_id (void);
+char * app_push (void);
+char * atof_ieee (char *, int, LITTLENUM_TYPE *);
+char * input_scrub_include_file (char *, char *);
+void   input_scrub_insert_line (const char *);
+void   input_scrub_insert_file (char *);
+char * input_scrub_new_file (char *);
+char * input_scrub_next_buffer (char **bufp);
+int    do_scrub_chars (int (*get) (char *, int), char *, int);
+int    gen_to_words (LITTLENUM_TYPE *, int, long);
+int    had_err (void);
+int    ignore_input (void);
+void   cond_finish_check (int);
+void   cond_exit_macro (int);
+int    seen_at_least_1_file (void);
+void   app_pop (char *);
+void   as_perror (const char *, const char *);
+void   as_where (char **, unsigned int *);
+void   bump_line_counters (void);
+void   do_scrub_begin (int);
+void   input_scrub_begin (void);
+void   input_scrub_close (void);
+void   input_scrub_end (void);
+int    new_logical_line (char *, int);
+void   subsegs_begin (void);
+void   subseg_change (segT, int);
+segT   subseg_new (const char *, subsegT);
+segT   subseg_force_new (const char *, subsegT);
+void   subseg_set (segT, subsegT);
+int    subseg_text_p (segT);
+int    seg_not_empty_p (segT);
+void   start_dependencies (char *);
+void   register_dependency (char *);
+void   print_dependencies (void);
+segT   subseg_get (const char *, int);
 
 struct expressionS;
 struct fix;
@@ -608,21 +570,18 @@ typedef struct symbol symbolS;
 struct relax_type;
 typedef struct frag fragS;
 
-#ifdef BFD_ASSEMBLER
 /* literal.c */
 valueT add_to_literal_pool (symbolS *, valueT, segT, int);
-#endif
 
 int check_eh_frame (struct expressionS *, unsigned int *);
 int eh_frame_estimate_size_before_relax (fragS *);
 int eh_frame_relax_frag (fragS *);
 void eh_frame_convert_frag (fragS *);
-
 int generic_force_reloc (struct fix *);
 
 #include "expr.h"		/* Before targ-*.h */
 
-/* this one starts the chain of target dependant headers */
+/* This one starts the chain of target dependant headers.  */
 #include "targ-env.h"
 
 #ifdef OBJ_MAYBE_ELF
@@ -652,14 +611,19 @@ int generic_force_reloc (struct fix *);
 #ifdef TC_M68K
 /* True if we are assembling in m68k MRI mode.  */
 COMMON int flag_m68k_mri;
+#define DOLLAR_AMBIGU flag_m68k_mri
 #else
 #define flag_m68k_mri 0
 #endif
 
 #ifdef WARN_COMMENTS
-COMMON int warn_comment;
-COMMON unsigned int found_comment;
-COMMON char *found_comment_file;
+COMMON int           warn_comment;
+COMMON unsigned int  found_comment;
+COMMON char *        found_comment_file;
+#endif
+
+#ifndef DOLLAR_AMBIGU
+#define DOLLAR_AMBIGU 0
 #endif
 
 #ifndef NUMBERS_WITH_SUFFIX
diff --git a/gas/asintl.h b/gas/asintl.h
index 41bb21826eee..67ce0dd4fd45 100644
--- a/gas/asintl.h
+++ b/gas/asintl.h
@@ -1,5 +1,5 @@
 /* asintl.h - gas-specific header for gettext code.
-   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2005 Free Software Foundation, Inc.
 
    Written by Tom Tromey <tromey@cygnus.com>
 
@@ -17,10 +17,19 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifdef HAVE_LOCALE_H
+# ifndef ENABLE_NLS
+   /* The Solaris version of locale.h always includes libintl.h.  If we have
+      been configured with --disable-nls then ENABLE_NLS will not be defined
+      and the dummy definitions of bindtextdomain (et al) below will conflict
+      with the defintions in libintl.h.  So we define these values to prevent
+      the bogus inclusion of libintl.h.  */
+#  define _LIBINTL_H
+#  define _LIBGETTEXT_H
+# endif
 # include <locale.h>
 #endif
 
diff --git a/gas/atof-generic.c b/gas/atof-generic.c
index 8c599b571edb..6a5c2f15b3cc 100644
--- a/gas/atof-generic.c
+++ b/gas/atof-generic.c
@@ -1,6 +1,6 @@
 /* atof_generic.c - turn a string of digits into a Flonum
-   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001
-   Free Software Foundation, Inc.
+   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000,
+   2001, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <string.h>
 
@@ -324,19 +324,10 @@ atof_generic (/* return pointer to just AFTER number we read.  */
 		   + 1);	/* Number of destination littlenums.  */
 
       /* Includes guard bits (two littlenums worth) */
-#if 0 /* The integer version below is very close, and it doesn't
-	 require floating point support (which is currently buggy on
-	 the Alpha).  */
-      maximum_useful_digits = (((double) (precision - 2))
-			       * ((double) (LITTLENUM_NUMBER_OF_BITS))
-			       / (LOG_TO_BASE_2_OF_10))
-	+ 2;			/* 2 :: guard digits.  */
-#else
       maximum_useful_digits = (((precision - 2))
 			       * ( (LITTLENUM_NUMBER_OF_BITS))
 			       * 1000000 / 3321928)
 	+ 2;			/* 2 :: guard digits.  */
-#endif
 
       if (number_of_digits_available > maximum_useful_digits)
 	{
@@ -353,13 +344,8 @@ atof_generic (/* return pointer to just AFTER number we read.  */
       decimal_exponent += ((long) number_of_digits_before_decimal
 			   - (long) number_of_digits_to_use);
 
-#if 0
-      more_than_enough_bits_for_digits
-	= ((((double) number_of_digits_to_use) * LOG_TO_BASE_2_OF_10) + 1);
-#else
       more_than_enough_bits_for_digits
 	= (number_of_digits_to_use * 3321928 / 1000000 + 1);
-#endif
 
       more_than_enough_littlenums_for_digits
 	= (more_than_enough_bits_for_digits
diff --git a/gas/bfin-lex.c b/gas/bfin-lex.c
new file mode 100644
index 000000000000..cfc1fe7f30c0
--- /dev/null
+++ b/gas/bfin-lex.c
@@ -0,0 +1,3368 @@
+/* A lexical scanner generated by flex */
+
+/* Scanner skeleton version:
+ * $Header: /cvs/src/src/gas/Attic/bfin-lex.c,v 1.1.2.1 2006/04/16 18:36:43 drow Exp $
+ */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+
+#include <stdio.h>
+#include <errno.h>
+
+/* cfront 1.2 defines "c_plusplus" instead of "__cplusplus" */
+#ifdef c_plusplus
+#ifndef __cplusplus
+#define __cplusplus
+#endif
+#endif
+
+
+#ifdef __cplusplus
+
+#include <stdlib.h>
+#ifndef _WIN32
+#include <unistd.h>
+#endif
+
+/* Use prototypes in function declarations. */
+#define YY_USE_PROTOS
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+#if __STDC__
+
+#define YY_USE_PROTOS
+#define YY_USE_CONST
+
+#endif	/* __STDC__ */
+#endif	/* ! __cplusplus */
+
+#ifdef __TURBOC__
+ #pragma warn -rch
+ #pragma warn -use
+#include <io.h>
+#include <stdlib.h>
+#define YY_USE_CONST
+#define YY_USE_PROTOS
+#endif
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+
+#ifdef YY_USE_PROTOS
+#define YY_PROTO(proto) proto
+#else
+#define YY_PROTO(proto) ()
+#endif
+
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN yy_start = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START ((yy_start - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE yyrestart( yyin )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#define YY_BUF_SIZE 16384
+
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+
+extern int yyleng;
+extern FILE *yyin, *yyout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+/* The funky do-while in the following #define is used to turn the definition
+ * int a single C statement (which needs a semi-colon terminator).  This
+ * avoids problems with code like:
+ *
+ * 	if ( condition_holds )
+ *		yyless( 5 );
+ *	else
+ *		do_something_else();
+ *
+ * Prior to using the do-while the compiler would get upset at the
+ * "else" because it interpreted the "if" statement as being all
+ * done when it reached the ';' after the yyless() call.
+ */
+
+/* Return all but the first 'n' matched characters back to the input stream. */
+
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+		*yy_cp = yy_hold_char; \
+		YY_RESTORE_YY_MORE_OFFSET \
+		yy_c_buf_p = yy_cp = yy_bp + n - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up yytext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, yytext_ptr )
+
+/* The following is because we cannot portably get our hands on size_t
+ * (without autoconf's help, which isn't available because we want
+ * flex-generated scanners to compile on their own).
+ */
+typedef unsigned int yy_size_t;
+
+
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via yyrestart()), so that the user can continue scanning by
+	 * just pointing yyin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+	};
+
+static YY_BUFFER_STATE yy_current_buffer = 0;
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ */
+#define YY_CURRENT_BUFFER yy_current_buffer
+
+
+/* yy_hold_char holds the character lost when yytext is formed. */
+static char yy_hold_char;
+
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+
+
+int yyleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 1;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow yywrap()'s to do buffer switches
+ * instead of setting up a fresh yyin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void yyrestart YY_PROTO(( FILE *input_file ));
+
+void yy_switch_to_buffer YY_PROTO(( YY_BUFFER_STATE new_buffer ));
+void yy_load_buffer_state YY_PROTO(( void ));
+YY_BUFFER_STATE yy_create_buffer YY_PROTO(( FILE *file, int size ));
+void yy_delete_buffer YY_PROTO(( YY_BUFFER_STATE b ));
+void yy_init_buffer YY_PROTO(( YY_BUFFER_STATE b, FILE *file ));
+void yy_flush_buffer YY_PROTO(( YY_BUFFER_STATE b ));
+#define YY_FLUSH_BUFFER yy_flush_buffer( yy_current_buffer )
+
+YY_BUFFER_STATE yy_scan_buffer YY_PROTO(( char *base, yy_size_t size ));
+YY_BUFFER_STATE yy_scan_string YY_PROTO(( yyconst char *yy_str ));
+YY_BUFFER_STATE yy_scan_bytes YY_PROTO(( yyconst char *bytes, int len ));
+
+static void *yy_flex_alloc YY_PROTO(( yy_size_t ));
+static void *yy_flex_realloc YY_PROTO(( void *, yy_size_t ));
+static void yy_flex_free YY_PROTO(( void * ));
+
+#define yy_new_buffer yy_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! yy_current_buffer ) \
+		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
+	yy_current_buffer->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! yy_current_buffer ) \
+		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE ); \
+	yy_current_buffer->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (yy_current_buffer->yy_at_bol)
+
+typedef unsigned char YY_CHAR;
+FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0;
+typedef int yy_state_type;
+extern char *yytext;
+#define yytext_ptr yytext
+
+static yy_state_type yy_get_previous_state YY_PROTO(( void ));
+static yy_state_type yy_try_NUL_trans YY_PROTO(( yy_state_type current_state ));
+static int yy_get_next_buffer YY_PROTO(( void ));
+static void yy_fatal_error YY_PROTO(( yyconst char msg[] ));
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up yytext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	yytext_ptr = yy_bp; \
+	yyleng = (int) (yy_cp - yy_bp); \
+	yy_hold_char = *yy_cp; \
+	*yy_cp = '\0'; \
+	yy_c_buf_p = yy_cp;
+
+#define YY_NUM_RULES 238
+#define YY_END_OF_BUFFER 239
+static yyconst short int yy_accept[559] =
+    {   0,
+        0,    0,    0,    0,  239,  237,  235,  235,  220,  233,
+      219,  218,  200,  201,  216,  214,  211,  210,  203,  232,
+      232,  202,  221,  199,  195,  237,  224,  233,  148,  233,
+      233,  233,  233,  233,  233,  233,  233,  233,   70,  233,
+      233,  233,   54,   19,   18,  233,   12,   10,    8,    7,
+      189,  188,  187,  233,  185,  183,  233,  233,  233,  233,
+      233,  233,  217,  215,  213,  212,    0,  209,  204,    0,
+        0,    0,  232,  234,    0,  232,  234,  198,  196,  222,
+      194,  193,  178,  175,  233,  233,  233,  150,  151,  233,
+      233,  149,    0,  147,  233,  140,  233,  233,  136,  233,
+
+      125,  233,  123,  233,  233,  233,  233,  233,  233,  233,
+      103,  102,  101,  233,  100,   99,  233,  233,   97,  233,
+       95,   94,   93,   91,  233,   85,  233,  233,   77,   86,
+      233,   71,   69,  233,  233,  233,  233,   65,  233,  233,
+      233,   59,  233,   56,  233,  233,   53,  233,  233,  233,
+      233,  233,  233,  233,  233,  233,  233,  233,  233,   25,
+      233,  233,  233,  233,  233,   15,   14,  233,  233,  159,
+      233,  186,  233,  184,  223,  233,  233,   95,  233,  233,
+      233,  205,  207,  206,  208,    0,    0,  232,  232,  232,
+      232,  197,  191,  192,  233,  233,  171,  152,  153,  233,
+
+      233,  162,  163,  233,  154,  156,  232,  233,  233,  233,
+      233,  233,  233,  124,  233,  233,  119,  233,  233,  233,
+      233,  233,  233,  233,  233,  233,  179,   98,  233,  233,
+      233,  233,  233,  233,   80,   83,   78,   81,  233,  233,
+      233,   79,   82,  233,   67,   66,  233,   63,   62,  233,
+      233,  233,  233,  233,  233,  233,  233,  233,  233,   44,
+       39,   38,   37,   36,   35,   34,  233,   32,   31,  233,
+      233,  233,  233,  233,  233,  233,   21,  233,  233,   16,
+       13,  233,    9,  233,  233,  233,  233,  233,  233,  233,
+      236,  190,  170,  168,  177,  176,  169,  167,  174,  173,
+
+      233,  233,  233,  155,  157,  146,  233,  233,  233,  233,
+      139,  138,  233,  127,  233,  233,  118,  233,  233,  233,
+      233,  111,  110,  233,  233,  233,  233,  233,  233,  233,
+      105,  104,  233,  233,  233,   96,  233,   92,   89,   84,
+       74,  233,  233,   68,   64,  233,   61,   60,   58,   57,
+      233,   55,   45,  233,   50,   47,   49,   46,   48,  233,
+      233,   43,   42,  233,  233,  233,  233,  233,   27,   24,
+       23,  233,  233,  233,  233,  233,  233,  228,  233,  227,
+      233,  233,  233,  233,  160,  233,  233,  233,  233,  233,
+      233,  233,  233,  233,  233,  122,  233,  117,  116,  233,
+
+      233,  233,  233,  233,  233,  233,  233,  108,  233,  233,
+      233,  233,  233,  233,  233,  233,  233,  233,    2,  182,
+       52,   41,   40,   33,  233,  233,  233,   30,  233,   22,
+      233,  233,  233,  172,  231,  233,  233,  233,  233,  233,
+      164,  161,  145,  144,  143,  142,  141,  233,  233,  233,
+      233,  126,  121,  233,  233,  233,  233,  233,   51,  233,
+      233,  107,  233,  233,  233,  233,  233,   88,   87,   90,
+      233,  233,   73,   72,   29,  233,  233,  233,   20,  233,
+      233,  233,  229,  233,  226,  165,  166,  233,  233,  233,
+      233,  233,  233,  120,  233,  114,  113,  233,  233,  233,
+
+        5,  106,  233,  180,  233,  233,  233,  233,   28,  233,
+      233,   17,   11,  233,  233,  233,  233,  135,  133,  134,
+      132,  129,  233,  115,  233,    6,  109,  233,  233,    3,
+      233,   76,    1,   26,  230,  225,  137,  130,  131,  233,
+      233,  233,  233,  233,  128,  233,  233,    4,   75,  233,
+      233,  112,  233,  233,  233,  233,  181,    0
+    } ;
+
+static yyconst int yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    4,    1,    5,    6,    7,    8,    1,    9,
+       10,   11,   12,   13,   14,   15,   16,   17,   18,   19,
+       20,   21,   22,   23,   24,   25,   26,   27,   28,   29,
+       30,   31,    1,   32,   33,   34,   35,   36,   37,   38,
+       39,   40,   41,   42,   43,   44,   45,   46,   47,   48,
+       49,   50,   51,   52,   53,   54,   55,   56,   57,   58,
+       59,    1,   60,   61,   62,    1,   63,   64,   35,   36,
+
+       37,   38,   39,   40,   41,   42,   43,   44,   45,   46,
+       65,   48,   49,   66,   51,   67,   53,   54,   55,   56,
+       57,   58,    1,   68,    1,   69,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+static yyconst int yy_meta[70] =
+    {   0,
+        1,    1,    2,    1,    1,    3,    1,    1,    1,    1,
+        1,    1,    1,    1,    3,    1,    4,    4,    4,    4,
+        4,    4,    4,    4,    4,    4,    1,    1,    1,    1,
+        1,    1,    5,    4,    5,    5,    5,    4,    3,    3,
+        3,    3,    3,    3,    3,    3,    3,    3,    3,    3,
+        3,    3,    3,    3,    3,    3,    3,    3,    1,    1,
+        1,    3,    5,    4,    3,    3,    3,    1,    1
+    } ;
+
+static yyconst short int yy_base[565] =
+    {   0,
+        0,    0,   32,   33,  814,  815,  815,  815,  815,    0,
+      815,  783,  815,  815,  782,   60,  815,   61,  800,  113,
+       44,  815,  815,   54,   75,  779,  815,  161,  221,   59,
+       84,   42,   92,  105,  109,  148,  756,  271,  141,   48,
+      110,  322,  372,  421,  153,  757,   60,  787,    0,    0,
+      815,  815,  776,  741,   58,  815,  141,   64,  763,   43,
+       61,    0,  815,  815,  815,  815,  105,  815,  815,  129,
+      792,  210,  225,  235,  472,  275,  815,  772,  815,  815,
+      815,  145,  786,  785,  748,  163,  757,    0,    0,  263,
+      185,    0,    0,  782,  131,    0,  759,   97,  154,  751,
+
+        0,  753,    0,  736,  757,  752,  742,   69,  736,  279,
+      773,  741,    0,  156,    0,    0,  157,  749,  770,  740,
+        0,    0,  732,    0,  737,  766,  196,  199,    0,  153,
+      226,  247,  765,  723,  732,  220,  280,    0,  221,  740,
+      170,  761,  740,    0,  250,  728,  758,  731,  252,  735,
+      257,  308,  260,  248,  269,  288,  281,  729,  730,  753,
+      710,  725,  714,  713,  710,    0,    0,  714,  298,    0,
+      742,  815,  219,  815,  815,  707,  715,  714,  711,  174,
+      712,  815,  815,  815,  815,  744,  138,  356,  408,    0,
+        0,  815,  815,  724,  312,  343,    0,    0,    0,  714,
+
+      711,    0,    0,  249,  700,  699,    0,  232,  369,  695,
+      303,  711,  703,    0,  700,  701,  375,  337,  337,  122,
+      238,  338,  378,  347,  239,  709,  725,    0,  356,  318,
+      705,  722,  692,  363,    0,    0,    0,    0,  691,  390,
+      697,    0,    0,  372,    0,    0,  689,    0,    0,  700,
+      684,  699,  403,  690,  684,  393,  436,  680,  474,  431,
+        0,    0,    0,    0,    0,    0,  684,    0,    0,  398,
+      678,  401,  690,  681,  437,  680,    0,  690,  401,    0,
+        0,  662,    0,  657,  671,  684,  667,  676,  680,  676,
+      705,  815,    0,    0,    0,    0,    0,    0,    0,    0,
+
+      669,  676,  434,    0,    0,    0,  669,  659,  674,  448,
+        0,  659,  466,  694,  673,  670,  439,  661,  411,  654,
+      660,    0,    0,  419,  422,  647,  649,  450,  665,  470,
+        0,    0,  664,  675,  462,    0,  636,    0,  682,    0,
+      634,  642,  656,    0,    0,  656,    0,    0,    0,    0,
+      657,    0,    0,  654,    0,    0,    0,    0,    0,  671,
+      672,    0,    0,  652,  652,  470,  649,  471,  470,    0,
+        0,  650,  646,  632,  637,  614,  640,  617,  627,    0,
+      640,  630,  521,  474,    0,  466,  619,  475,  630,  477,
+      633,  624,  485,  625,  614,    0,  618,    0,    0,  620,
+
+      623,  625,  626,  611,  491,  628,  611,    0,  619,  625,
+      622,  613,  622,  495,  503,  487,  608,  497,    0,    0,
+        0,    0,    0,    0,  615,  517,  603,    0,  612,    0,
+      613,  614,  519,    0,  609,  609,  501,  605,  624,  625,
+        0,    0,    0,    0,    0,    0,    0,  604,  537,  609,
+      595,    0,  623,  597,  508,  510,  594,  588,    0,  590,
+      600,    0,  511,  585,  614,  532,  597,    0,    0,    0,
+      596,  586,    0,    0,    0,  514,  594,  517,    0,  518,
+      574,  583,    0,  593,    0,    0,    0,  589,  544,  315,
+      578,  582,  538,    0,  568,    0,    0,  586,  578,  520,
+
+        0,    0,  575,    0,  551,  554,  563,  564,    0,  521,
+      548,    0,    0,  543,  556,  522,  418,    0,    0,    0,
+        0,    0,  558,    0,  535,    0,    0,  524,  528,    0,
+      424,    0,    0,    0,    0,    0,    0,    0,    0,  403,
+      388,  378,  324,  279,    0,  272,  529,    0,    0,  531,
+      538,    0,  262,  168,   82,   83,    0,  815,  603,  608,
+       92,  613,  615,  617
+    } ;
+
+static yyconst short int yy_def[565] =
+    {   0,
+      558,    1,    1,    1,  558,  558,  558,  558,  558,  559,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  560,
+      561,  558,  558,  558,  558,  558,  558,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      558,  558,  558,   28,  558,  558,  559,   36,   38,   42,
+      559,  559,  558,  558,  558,  558,  558,  558,  558,  558,
+      562,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  563,  559,  559,  559,  559,  559,  559,  559,
+
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  558,  559,  558,  558,  559,  559,  559,  559,  559,
+      559,  558,  558,  558,  558,  562,  562,  558,  558,   75,
+      564,  558,  558,  558,  559,  559,  559,  559,  559,  559,
+
+      559,  559,  559,  559,  559,  559,  563,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      562,  558,  559,  559,  559,  559,  559,  559,  559,  559,
+
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,  559,  559,  559,
+      559,  559,  559,  559,  559,  559,  559,    0,  558,  558,
+      558,  558,  558,  558
+    } ;
+
+static yyconst short int yy_nxt[885] =
+    {   0,
+        6,    7,    8,    9,    6,   10,   11,   12,   13,   14,
+       15,   16,   17,   18,   10,   19,   20,   21,   21,   21,
+       21,   21,   21,   21,   21,   21,   22,   23,   24,   25,
+       26,   27,   28,   29,   30,   31,   32,   33,   34,   35,
+       36,   37,   10,   38,   39,   40,   41,   42,   10,   43,
+       44,   45,   46,   47,   48,   49,   10,   50,   51,   52,
+       53,   10,   54,   29,   41,   43,   45,   55,   56,   57,
+       57,   65,   58,   58,   68,   59,   59,   77,   80,   60,
+       60,   77,   78,   79,   61,   61,  109,  174,   93,   66,
+       69,  100,  180,  101,  137,   76,   93,  110,  138,  177,
+
+      169,  178,  102,  557,   81,  103,  181,   77,  180,  104,
+      170,  168,  137,   93,   93,  105,  182,  106,  183,  219,
+      107,  100,  220,  103,  108,  175,  556,   67,   70,   73,
+       73,   73,   73,   73,   73,   73,   73,   73,   73,  111,
+      184,  113,  185,  211,  112,   93,   74,  106,  187,  116,
+       74,  114,  117,  291,  139,  140,  115,  133,  133,  133,
+      133,  211,  141,  118,  119,  119,  119,  119,   75,  114,
+      322,  115,  323,  134,  193,  194,   74,   83,   84,  198,
+      199,  135,  209,  120,  176,  121,  136,  122,  111,  164,
+      165,  555,  166,  112,   85,   86,  167,  209,  123,  239,
+
+      124,  205,  206,  134,   87,  212,   88,  227,  228,   89,
+      289,   90,  235,  236,   91,  237,  238,  239,   92,  256,
+      212,  252,  227,  228,   85,   93,  188,  188,  188,  188,
+      188,  188,  188,  188,  188,  188,  252,   94,   94,   94,
+       94,  189,  189,  189,  189,  189,  189,  189,  189,  189,
+      189,  188,  188,  188,  188,  188,  188,  188,  188,  188,
+      188,   95,  240,  242,  243,  241,  247,  250,   96,  197,
+       97,  306,  324,  325,  326,  306,   98,   99,  331,  554,
+      268,  303,  332,  284,  247,  250,   97,  126,  126,  126,
+      126,   76,   76,   76,   76,   76,   76,   76,   76,   76,
+
+       76,  255,  201,  259,  127,  128,  202,  129,  261,  267,
+      268,  303,  203,  222,  204,  269,  255,  130,  259,  550,
+      270,  131,  132,  261,  549,  267,  223,  248,  203,  204,
+      224,  249,  272,  269,  127,  130,  271,  132,  142,  142,
+      142,  142,  142,  142,  262,  224,  249,  272,  263,  282,
+      270,  293,  312,  264,  143,  294,  144,  336,  265,  519,
+      548,  336,  520,  266,  282,  145,  295,  296,  312,  321,
+      327,  146,  188,  188,  188,  188,  188,  188,  188,  188,
+      188,  188,  297,  320,  143,  328,  298,  146,  147,  147,
+      147,  147,  147,  147,  147,  147,  330,  299,  300,  321,
+
+      327,  320,  340,  307,  148,  335,  340,  317,  149,  318,
+      329,  344,  330,  308,  319,  344,  547,  150,  151,  309,
+      310,  335,  546,  152,  189,  189,  189,  189,  189,  189,
+      189,  189,  189,  189,  148,  310,  151,  317,  152,  153,
+      329,  342,  349,  401,  352,  545,  349,  365,  360,  361,
+      367,  404,  374,  154,  405,  155,  342,  156,  157,  352,
+      158,  159,  538,  365,  544,  539,  367,  374,  160,  353,
+      362,  161,  162,  401,  363,  353,  370,  163,  398,  353,
+      371,  404,  399,  154,  405,  385,  389,  162,  190,  190,
+      190,  190,  190,  190,  190,  190,  190,  190,  390,  353,
+
+      385,  408,  410,  429,  191,  191,  191,  191,  191,  191,
+      355,  413,  392,  393,  356,  443,  408,  450,  394,  357,
+      471,  426,  428,  472,  358,  442,  445,  413,  447,  359,
+      392,  443,  410,  429,  191,  191,  426,  428,  439,  440,
+      442,  445,  459,  447,  467,  441,  468,  450,  474,  476,
+      471,  481,  484,  469,  489,  490,  491,  459,  470,  496,
+      467,  497,  502,  474,  505,  509,  517,  484,  511,  512,
+      523,  527,  533,  537,  496,  551,  497,  502,  543,  476,
+      509,  481,  552,  511,  512,  542,  527,  533,  537,  553,
+      541,  518,  540,  551,  505,  536,  535,  552,  534,  532,
+
+      523,  531,  530,  529,  553,   62,   62,   62,   72,  528,
+       72,   72,   72,  186,  526,  186,  186,  186,  207,  207,
+      191,  191,  525,  524,  522,  521,  516,  515,  514,  513,
+      510,  508,  507,  506,  504,  503,  501,  500,  499,  498,
+      495,  494,  493,  492,  488,  487,  486,  485,  483,  482,
+      480,  479,  478,  477,  475,  473,  466,  465,  464,  463,
+      462,  461,  460,  458,  457,  456,  455,  454,  453,  452,
+      451,  449,  448,  446,  444,  438,  437,  436,  414,  435,
+      434,  433,  432,  431,  430,  427,  425,  424,  423,  422,
+      421,  420,  419,  418,  417,  416,  415,  414,  412,  411,
+
+      409,  407,  406,  403,  402,  400,  397,  396,  395,  391,
+      388,  387,  386,  384,  383,  187,  382,  381,  380,  379,
+      378,  377,  376,  375,  373,  372,  369,  368,  366,  364,
+      354,  351,  350,  348,  347,  346,  345,  343,  341,  339,
+      338,  337,  334,  333,  316,  315,  314,  313,  311,  305,
+      304,  302,  301,  292,  187,  290,  288,  287,  286,  285,
+      283,  281,  280,  279,  278,  277,  276,  275,  274,  273,
+      260,  258,  257,  256,  254,  253,  251,  246,  245,  244,
+      234,  233,  232,  231,  230,  229,  226,  225,  221,  218,
+      217,  216,  215,  214,  213,  210,  208,  200,  197,  196,
+
+      195,  192,  187,  179,  173,  172,  171,  168,  125,   82,
+       71,   64,   63,  558,    5,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558
+    } ;
+
+static yyconst short int yy_chk[885] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    3,
+        4,   16,    3,    4,   18,    3,    4,   21,   25,    3,
+        4,   21,   24,   24,    3,    4,   32,   55,   31,   16,
+       18,   30,   60,   30,   40,  561,   33,   32,   40,   58,
+
+       47,   58,   30,  556,   25,   30,   61,   21,   60,   30,
+       47,   61,   40,   35,   41,   30,   67,   31,   67,  108,
+       31,   30,  108,   30,   31,   55,  555,   16,   18,   20,
+       20,   20,   20,   20,   20,   20,   20,   20,   20,   33,
+       70,   34,   70,   98,   33,   57,   20,   31,  187,   35,
+       20,   34,   35,  187,   41,   41,   34,   39,   39,   39,
+       39,   98,   41,   35,   36,   36,   36,   36,   20,   34,
+      220,   34,  220,   39,   82,   82,   20,   28,   28,   86,
+       86,   39,   95,   36,   57,   36,   39,   36,   57,   45,
+       45,  554,   45,   57,   28,   28,   45,   95,   36,  130,
+
+       36,   91,   91,   39,   28,   99,   28,  114,  117,   28,
+      180,   28,  127,  127,   28,  128,  128,  130,   28,  180,
+       99,  141,  114,  117,   28,   29,   72,   72,   72,   72,
+       72,   72,   72,   72,   72,   72,  141,   29,   29,   29,
+       29,   73,   73,   73,   73,   73,   73,   73,   73,   73,
+       73,   74,   74,   74,   74,   74,   74,   74,   74,   74,
+       74,   29,  131,  132,  132,  131,  136,  139,   29,  173,
+       29,  208,  221,  221,  221,  208,   29,   29,  225,  553,
+      154,  204,  225,  173,  136,  139,   29,   38,   38,   38,
+       38,   76,   76,   76,   76,   76,   76,   76,   76,   76,
+
+       76,  145,   90,  149,   38,   38,   90,   38,  151,  153,
+      154,  204,   90,  110,   90,  155,  145,   38,  149,  546,
+      156,   38,   38,  151,  544,  153,  110,  137,   90,   90,
+      110,  137,  157,  155,   38,   38,  156,   38,   42,   42,
+       42,   42,   42,   42,  152,  110,  137,  157,  152,  169,
+      156,  195,  211,  152,   42,  195,   42,  230,  152,  490,
+      543,  230,  490,  152,  169,   42,  195,  195,  211,  219,
+      222,   42,  188,  188,  188,  188,  188,  188,  188,  188,
+      188,  188,  196,  218,   42,  222,  196,   42,   43,   43,
+       43,   43,   43,   43,   43,   43,  224,  196,  196,  219,
+
+      222,  218,  234,  209,   43,  229,  234,  217,   43,  217,
+      223,  244,  224,  209,  217,  244,  542,   43,   43,  209,
+      209,  229,  541,   43,  189,  189,  189,  189,  189,  189,
+      189,  189,  189,  189,   43,  209,   43,  217,   43,   44,
+      223,  240,  253,  319,  256,  540,  253,  270,  260,  260,
+      272,  324,  279,   44,  325,   44,  240,   44,   44,  256,
+       44,   44,  517,  270,  531,  517,  272,  279,   44,  257,
+      260,   44,   44,  319,  260,  257,  275,   44,  317,  257,
+      275,  324,  317,   44,  325,  303,  310,   44,   75,   75,
+       75,   75,   75,   75,   75,   75,   75,   75,  310,  257,
+
+      303,  328,  330,  369,   75,   75,   75,   75,   75,   75,
+      259,  335,  313,  313,  259,  386,  328,  393,  313,  259,
+      416,  366,  368,  416,  259,  384,  388,  335,  390,  259,
+      313,  386,  330,  369,   75,   75,  366,  368,  383,  383,
+      384,  388,  405,  390,  414,  383,  415,  393,  418,  426,
+      416,  433,  437,  415,  449,  449,  449,  405,  415,  455,
+      414,  456,  463,  418,  466,  476,  489,  437,  478,  480,
+      493,  500,  510,  516,  455,  547,  456,  463,  529,  426,
+      476,  433,  550,  478,  480,  528,  500,  510,  516,  551,
+      525,  489,  523,  547,  466,  515,  514,  550,  511,  508,
+
+      493,  507,  506,  505,  551,  559,  559,  559,  560,  503,
+      560,  560,  560,  562,  499,  562,  562,  562,  563,  563,
+      564,  564,  498,  495,  492,  491,  488,  484,  482,  481,
+      477,  472,  471,  467,  465,  464,  461,  460,  458,  457,
+      454,  453,  451,  450,  448,  440,  439,  438,  436,  435,
+      432,  431,  429,  427,  425,  417,  413,  412,  411,  410,
+      409,  407,  406,  404,  403,  402,  401,  400,  397,  395,
+      394,  392,  391,  389,  387,  382,  381,  379,  378,  377,
+      376,  375,  374,  373,  372,  367,  365,  364,  361,  360,
+      354,  351,  346,  343,  342,  341,  339,  337,  334,  333,
+
+      329,  327,  326,  321,  320,  318,  316,  315,  314,  312,
+      309,  308,  307,  302,  301,  291,  290,  289,  288,  287,
+      286,  285,  284,  282,  278,  276,  274,  273,  271,  267,
+      258,  255,  254,  252,  251,  250,  247,  241,  239,  233,
+      232,  231,  227,  226,  216,  215,  213,  212,  210,  206,
+      205,  201,  200,  194,  186,  181,  179,  178,  177,  176,
+      171,  168,  165,  164,  163,  162,  161,  160,  159,  158,
+      150,  148,  147,  146,  143,  142,  140,  135,  134,  133,
+      126,  125,  123,  120,  119,  118,  112,  111,  109,  107,
+      106,  105,  104,  102,  100,   97,   94,   87,   85,   84,
+
+       83,   78,   71,   59,   54,   53,   48,   46,   37,   26,
+       19,   15,   12,    5,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558,  558,  558,  558,  558,  558,  558,
+      558,  558,  558,  558
+    } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *yytext;
+#line 1 "bfin-lex.l"
+#define INITIAL 0
+/* bfin-lex.l  ADI Blackfin lexer
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+#line 22 "bfin-lex.l"
+
+#include <stdlib.h>
+#include <string.h>
+#include "bfin-defs.h"
+#include "bfin-parse.h"
+#include "as.h"
+
+static long parse_int (char **end);
+static int parse_halfreg (Register *r, int cl, char *hr);
+static int parse_reg (Register *r, int type, char *rt);
+int yylex (void);
+
+#define _REG yylval.reg
+
+
+/* Define Start States ... Actually we will use exclusion.
+   If no start state is specified it should match any state
+   and <INITIAL> would match some keyword rules only with
+   initial.  */
+#define KEYWORD 1
+
+#line 788 "bfin-lex.c"
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int yywrap YY_PROTO(( void ));
+#else
+extern int yywrap YY_PROTO(( void ));
+#endif
+#endif
+
+#ifndef YY_NO_UNPUT
+static void yyunput YY_PROTO(( int c, char *buf_ptr ));
+#endif
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy YY_PROTO(( char *, yyconst char *, int ));
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen YY_PROTO(( yyconst char * ));
+#endif
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+static int yyinput YY_PROTO(( void ));
+#else
+static int input YY_PROTO(( void ));
+#endif
+#endif
+
+#if YY_STACK_USED
+static int yy_start_stack_ptr = 0;
+static int yy_start_stack_depth = 0;
+static int *yy_start_stack = 0;
+#ifndef YY_NO_PUSH_STATE
+static void yy_push_state YY_PROTO(( int new_state ));
+#endif
+#ifndef YY_NO_POP_STATE
+static void yy_pop_state YY_PROTO(( void ));
+#endif
+#ifndef YY_NO_TOP_STATE
+static int yy_top_state YY_PROTO(( void ));
+#endif
+
+#else
+#define YY_NO_PUSH_STATE 1
+#define YY_NO_POP_STATE 1
+#define YY_NO_TOP_STATE 1
+#endif
+
+#ifdef YY_MALLOC_DECL
+YY_MALLOC_DECL
+#else
+#if __STDC__
+#ifndef __cplusplus
+#include <stdlib.h>
+#endif
+#else
+/* Just try to get by without declaring the routines.  This will fail
+ * miserably on non-ANSI systems for which sizeof(size_t) != sizeof(int)
+ * or sizeof(void*) != sizeof(int).
+ */
+#endif
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO (void) fwrite( yytext, yyleng, 1, yyout )
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+	if ( yy_current_buffer->yy_is_interactive ) \
+		{ \
+		int c = '*', n; \
+		for ( n = 0; n < max_size && \
+			     (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+			buf[n] = (char) c; \
+		if ( c == '\n' ) \
+			buf[n++] = (char) c; \
+		if ( c == EOF && ferror( yyin ) ) \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+		result = n; \
+		} \
+	else \
+		{ \
+		errno=0; \
+		while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \
+			{ \
+			if( errno != EINTR) \
+				{ \
+				YY_FATAL_ERROR( "input in flex scanner failed" ); \
+				break; \
+				} \
+			errno=0; \
+			clearerr(yyin); \
+			} \
+		}
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL int yylex YY_PROTO(( void ))
+#endif
+
+/* Code executed at the beginning of each rule, after yytext and yyleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+	YY_USER_ACTION
+
+YY_DECL
+	{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+
+#line 45 "bfin-lex.l"
+
+#line 952 "bfin-lex.c"
+
+	if ( yy_init )
+		{
+		yy_init = 0;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! yy_start )
+			yy_start = 1;	/* first start state */
+
+		if ( ! yyin )
+			yyin = stdin;
+
+		if ( ! yyout )
+			yyout = stdout;
+
+		if ( ! yy_current_buffer )
+			yy_current_buffer =
+				yy_create_buffer( yyin, YY_BUF_SIZE );
+
+		yy_load_buffer_state();
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+		yy_cp = yy_c_buf_p;
+
+		/* Support of yytext. */
+		*yy_cp = yy_hold_char;
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+		yy_current_state = yy_start;
+yy_match:
+		do
+			{
+			register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+			if ( yy_accept[yy_current_state] )
+				{
+				yy_last_accepting_state = yy_current_state;
+				yy_last_accepting_cpos = yy_cp;
+				}
+			while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+				{
+				yy_current_state = (int) yy_def[yy_current_state];
+				if ( yy_current_state >= 559 )
+					yy_c = yy_meta[(unsigned int) yy_c];
+				}
+			yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+			++yy_cp;
+			}
+		while ( yy_base[yy_current_state] != 815 );
+
+yy_find_action:
+		yy_act = yy_accept[yy_current_state];
+		if ( yy_act == 0 )
+			{ /* have to back up */
+			yy_cp = yy_last_accepting_cpos;
+			yy_current_state = yy_last_accepting_state;
+			yy_act = yy_accept[yy_current_state];
+			}
+
+		YY_DO_BEFORE_ACTION;
+
+
+do_action:	/* This label is used only to access EOF actions. */
+
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+			case 0: /* must back up */
+			/* undo the effects of YY_DO_BEFORE_ACTION */
+			*yy_cp = yy_hold_char;
+			yy_cp = yy_last_accepting_cpos;
+			yy_current_state = yy_last_accepting_state;
+			goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 46 "bfin-lex.l"
+_REG.regno = REG_sftreset;  return REG;
+	YY_BREAK
+case 2:
+YY_RULE_SETUP
+#line 47 "bfin-lex.l"
+_REG.regno = REG_omode;     return REG;
+	YY_BREAK
+case 3:
+YY_RULE_SETUP
+#line 48 "bfin-lex.l"
+_REG.regno = REG_idle_req;  return REG;
+	YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 49 "bfin-lex.l"
+_REG.regno = REG_hwerrcause; return REG;
+	YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 50 "bfin-lex.l"
+_REG.regno = REG_excause;   return REG;
+	YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 51 "bfin-lex.l"
+_REG.regno = REG_emucause;  return REG;
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 52 "bfin-lex.l"
+return Z;
+	YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 53 "bfin-lex.l"
+return X;
+	YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 54 "bfin-lex.l"
+yylval.value = M_W32; return MMOD;
+	YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 55 "bfin-lex.l"
+return W;
+	YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 56 "bfin-lex.l"
+return VIT_MAX;
+	YY_BREAK
+case 12:
+YY_RULE_SETUP
+#line 57 "bfin-lex.l"
+return V; /* Special: V is a statflag and a modifier.  */
+	YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 58 "bfin-lex.l"
+_REG.regno = REG_USP; return REG;
+	YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 59 "bfin-lex.l"
+return TL;
+	YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 60 "bfin-lex.l"
+return TH;
+	YY_BREAK
+case 16:
+YY_RULE_SETUP
+#line 61 "bfin-lex.l"
+yylval.value = M_TFU; return MMOD;
+	YY_BREAK
+case 17:
+YY_RULE_SETUP
+#line 62 "bfin-lex.l"
+return TESTSET;
+	YY_BREAK
+case 18:
+YY_RULE_SETUP
+#line 63 "bfin-lex.l"
+yylval.value = M_T; return MMOD;
+	YY_BREAK
+case 19:
+YY_RULE_SETUP
+#line 64 "bfin-lex.l"
+return S;
+	YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 65 "bfin-lex.l"
+_REG.regno = REG_SYSCFG; return REG;
+	YY_BREAK
+case 21:
+YY_RULE_SETUP
+#line 66 "bfin-lex.l"
+return STI;
+	YY_BREAK
+case 22:
+YY_RULE_SETUP
+#line 67 "bfin-lex.l"
+return SSYNC;
+	YY_BREAK
+case 23:
+YY_RULE_SETUP
+#line 68 "bfin-lex.l"
+_REG.regno = REG_SP; return HALF_REG;
+	YY_BREAK
+case 24:
+YY_RULE_SETUP
+#line 69 "bfin-lex.l"
+_REG.regno = REG_SP | F_REG_HIGH; return HALF_REG;
+	YY_BREAK
+case 25:
+YY_RULE_SETUP
+#line 70 "bfin-lex.l"
+_REG.regno = REG_SP; return REG;
+	YY_BREAK
+case 26:
+YY_RULE_SETUP
+#line 71 "bfin-lex.l"
+return SIGNBITS;
+	YY_BREAK
+case 27:
+YY_RULE_SETUP
+#line 72 "bfin-lex.l"
+return SIGN;
+	YY_BREAK
+case 28:
+YY_RULE_SETUP
+#line 73 "bfin-lex.l"
+_REG.regno = REG_SEQSTAT; return REG;
+	YY_BREAK
+case 29:
+YY_RULE_SETUP
+#line 74 "bfin-lex.l"
+return SEARCH;
+	YY_BREAK
+case 30:
+YY_RULE_SETUP
+#line 75 "bfin-lex.l"
+return SHIFT;
+	YY_BREAK
+case 31:
+YY_RULE_SETUP
+#line 76 "bfin-lex.l"
+return SCO;
+	YY_BREAK
+case 32:
+YY_RULE_SETUP
+#line 78 "bfin-lex.l"
+return SAA;
+	YY_BREAK
+case 33:
+YY_RULE_SETUP
+#line 79 "bfin-lex.l"
+yylval.value = M_S2RND; return MMOD;
+	YY_BREAK
+case 34:
+YY_RULE_SETUP
+#line 80 "bfin-lex.l"
+return RTX;
+	YY_BREAK
+case 35:
+YY_RULE_SETUP
+#line 81 "bfin-lex.l"
+return RTS;
+	YY_BREAK
+case 36:
+YY_RULE_SETUP
+#line 82 "bfin-lex.l"
+return RTN;
+	YY_BREAK
+case 37:
+YY_RULE_SETUP
+#line 83 "bfin-lex.l"
+return RTI;
+	YY_BREAK
+case 38:
+YY_RULE_SETUP
+#line 84 "bfin-lex.l"
+return RTE;
+	YY_BREAK
+case 39:
+YY_RULE_SETUP
+#line 85 "bfin-lex.l"
+return ROT;
+	YY_BREAK
+case 40:
+YY_RULE_SETUP
+#line 86 "bfin-lex.l"
+return RND20;
+	YY_BREAK
+case 41:
+YY_RULE_SETUP
+#line 87 "bfin-lex.l"
+return RND12;
+	YY_BREAK
+case 42:
+YY_RULE_SETUP
+#line 88 "bfin-lex.l"
+return RNDL;
+	YY_BREAK
+case 43:
+YY_RULE_SETUP
+#line 89 "bfin-lex.l"
+return RNDH;
+	YY_BREAK
+case 44:
+YY_RULE_SETUP
+#line 90 "bfin-lex.l"
+return RND;
+	YY_BREAK
+case 45:
+YY_RULE_SETUP
+#line 92 "bfin-lex.l"
+return parse_halfreg(&yylval.reg, T_REG_R, yytext);
+	YY_BREAK
+case 46:
+YY_RULE_SETUP
+#line 94 "bfin-lex.l"
+_REG.regno = REG_RETS; return REG;
+	YY_BREAK
+case 47:
+YY_RULE_SETUP
+#line 95 "bfin-lex.l"
+_REG.regno = REG_RETI; return REG;
+	YY_BREAK
+case 48:
+YY_RULE_SETUP
+#line 96 "bfin-lex.l"
+_REG.regno = REG_RETX; return REG;
+	YY_BREAK
+case 49:
+YY_RULE_SETUP
+#line 97 "bfin-lex.l"
+_REG.regno = REG_RETN; return REG;
+	YY_BREAK
+case 50:
+YY_RULE_SETUP
+#line 98 "bfin-lex.l"
+_REG.regno = REG_RETE; return REG;
+	YY_BREAK
+case 51:
+YY_RULE_SETUP
+#line 99 "bfin-lex.l"
+_REG.regno = REG_EMUDAT; return REG;
+	YY_BREAK
+case 52:
+YY_RULE_SETUP
+#line 100 "bfin-lex.l"
+return RAISE;
+	YY_BREAK
+case 53:
+YY_RULE_SETUP
+#line 102 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_R, yytext);
+	YY_BREAK
+case 54:
+YY_RULE_SETUP
+#line 104 "bfin-lex.l"
+return R;
+	YY_BREAK
+case 55:
+YY_RULE_SETUP
+#line 105 "bfin-lex.l"
+return PRNT;
+	YY_BREAK
+case 56:
+YY_RULE_SETUP
+#line 106 "bfin-lex.l"
+return PC;
+	YY_BREAK
+case 57:
+YY_RULE_SETUP
+#line 107 "bfin-lex.l"
+return PACK;
+	YY_BREAK
+case 58:
+YY_RULE_SETUP
+#line 109 "bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_P, yytext);
+	YY_BREAK
+case 59:
+YY_RULE_SETUP
+#line 110 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_P, yytext);
+	YY_BREAK
+case 60:
+YY_RULE_SETUP
+#line 112 "bfin-lex.l"
+return OUTC;
+	YY_BREAK
+case 61:
+YY_RULE_SETUP
+#line 113 "bfin-lex.l"
+return ONES;
+	YY_BREAK
+case 62:
+YY_RULE_SETUP
+#line 115 "bfin-lex.l"
+return NOT;
+	YY_BREAK
+case 63:
+YY_RULE_SETUP
+#line 116 "bfin-lex.l"
+return NOP;
+	YY_BREAK
+case 64:
+YY_RULE_SETUP
+#line 117 "bfin-lex.l"
+return MNOP;
+	YY_BREAK
+case 65:
+YY_RULE_SETUP
+#line 118 "bfin-lex.l"
+return NS;
+	YY_BREAK
+case 66:
+YY_RULE_SETUP
+#line 121 "bfin-lex.l"
+return MIN;
+	YY_BREAK
+case 67:
+YY_RULE_SETUP
+#line 122 "bfin-lex.l"
+return MAX;
+	YY_BREAK
+case 68:
+YY_RULE_SETUP
+#line 124 "bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_M, yytext);
+	YY_BREAK
+case 69:
+YY_RULE_SETUP
+#line 125 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_M, yytext);
+	YY_BREAK
+case 70:
+YY_RULE_SETUP
+#line 127 "bfin-lex.l"
+return M;
+	YY_BREAK
+case 71:
+YY_RULE_SETUP
+#line 128 "bfin-lex.l"
+return LT;
+	YY_BREAK
+case 72:
+YY_RULE_SETUP
+#line 129 "bfin-lex.l"
+return LSHIFT;
+	YY_BREAK
+case 73:
+YY_RULE_SETUP
+#line 130 "bfin-lex.l"
+return LSETUP;
+	YY_BREAK
+case 74:
+YY_RULE_SETUP
+#line 131 "bfin-lex.l"
+return LOOP;
+	YY_BREAK
+case 75:
+YY_RULE_SETUP
+#line 132 "bfin-lex.l"
+return LOOP_BEGIN;
+	YY_BREAK
+case 76:
+YY_RULE_SETUP
+#line 133 "bfin-lex.l"
+return LOOP_END;
+	YY_BREAK
+case 77:
+YY_RULE_SETUP
+#line 135 "bfin-lex.l"
+return LE;
+	YY_BREAK
+case 78:
+YY_RULE_SETUP
+#line 136 "bfin-lex.l"
+_REG.regno = REG_LC0; return REG;
+	YY_BREAK
+case 79:
+YY_RULE_SETUP
+#line 137 "bfin-lex.l"
+_REG.regno = REG_LT0; return REG;
+	YY_BREAK
+case 80:
+YY_RULE_SETUP
+#line 138 "bfin-lex.l"
+_REG.regno = REG_LB0; return REG;
+	YY_BREAK
+case 81:
+YY_RULE_SETUP
+#line 139 "bfin-lex.l"
+_REG.regno = REG_LC1; return REG;
+	YY_BREAK
+case 82:
+YY_RULE_SETUP
+#line 140 "bfin-lex.l"
+_REG.regno = REG_LT1; return REG;
+	YY_BREAK
+case 83:
+YY_RULE_SETUP
+#line 141 "bfin-lex.l"
+_REG.regno = REG_LB1; return REG;
+	YY_BREAK
+case 84:
+YY_RULE_SETUP
+#line 143 "bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_L, yytext);
+	YY_BREAK
+case 85:
+YY_RULE_SETUP
+#line 144 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_L, yytext);
+	YY_BREAK
+case 86:
+YY_RULE_SETUP
+#line 145 "bfin-lex.l"
+return LO;
+	YY_BREAK
+case 87:
+YY_RULE_SETUP
+#line 146 "bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_S;}
+	YY_BREAK
+case 88:
+YY_RULE_SETUP
+#line 147 "bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_L;}
+	YY_BREAK
+case 89:
+YY_RULE_SETUP
+#line 148 "bfin-lex.l"
+{ BEGIN 0; return JUMP;}
+	YY_BREAK
+case 90:
+YY_RULE_SETUP
+#line 149 "bfin-lex.l"
+{ BEGIN 0; return JUMP_DOT_L; }
+	YY_BREAK
+case 91:
+YY_RULE_SETUP
+#line 150 "bfin-lex.l"
+yylval.value = M_IU;   return MMOD;
+	YY_BREAK
+case 92:
+YY_RULE_SETUP
+#line 151 "bfin-lex.l"
+yylval.value = M_ISS2; return MMOD;
+	YY_BREAK
+case 93:
+YY_RULE_SETUP
+#line 152 "bfin-lex.l"
+yylval.value = M_IS;   return MMOD;
+	YY_BREAK
+case 94:
+YY_RULE_SETUP
+#line 153 "bfin-lex.l"
+yylval.value = M_IH;   return MMOD;
+	YY_BREAK
+case 95:
+YY_RULE_SETUP
+#line 154 "bfin-lex.l"
+return IF;
+	YY_BREAK
+case 96:
+YY_RULE_SETUP
+#line 155 "bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_I, yytext);
+	YY_BREAK
+case 97:
+YY_RULE_SETUP
+#line 156 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_I, yytext);
+	YY_BREAK
+case 98:
+YY_RULE_SETUP
+#line 157 "bfin-lex.l"
+return HLT;
+	YY_BREAK
+case 99:
+YY_RULE_SETUP
+#line 158 "bfin-lex.l"
+return HI;
+	YY_BREAK
+case 100:
+YY_RULE_SETUP
+#line 159 "bfin-lex.l"
+return GT;
+	YY_BREAK
+case 101:
+YY_RULE_SETUP
+#line 160 "bfin-lex.l"
+return GE;
+	YY_BREAK
+case 102:
+YY_RULE_SETUP
+#line 161 "bfin-lex.l"
+yylval.value = M_FU; return MMOD;
+	YY_BREAK
+case 103:
+YY_RULE_SETUP
+#line 162 "bfin-lex.l"
+_REG.regno = REG_FP; return REG;
+	YY_BREAK
+case 104:
+YY_RULE_SETUP
+#line 163 "bfin-lex.l"
+_REG.regno = REG_FP; return HALF_REG;
+	YY_BREAK
+case 105:
+YY_RULE_SETUP
+#line 164 "bfin-lex.l"
+_REG.regno = REG_FP | F_REG_HIGH; return HALF_REG;
+	YY_BREAK
+case 106:
+YY_RULE_SETUP
+#line 166 "bfin-lex.l"
+return EXTRACT;
+	YY_BREAK
+case 107:
+YY_RULE_SETUP
+#line 167 "bfin-lex.l"
+return EXPADJ;
+	YY_BREAK
+case 108:
+YY_RULE_SETUP
+#line 168 "bfin-lex.l"
+return EXCPT;
+	YY_BREAK
+case 109:
+YY_RULE_SETUP
+#line 169 "bfin-lex.l"
+return EMUEXCPT;
+	YY_BREAK
+case 110:
+YY_RULE_SETUP
+#line 170 "bfin-lex.l"
+return DIVS;
+	YY_BREAK
+case 111:
+YY_RULE_SETUP
+#line 171 "bfin-lex.l"
+return DIVQ;
+	YY_BREAK
+case 112:
+YY_RULE_SETUP
+#line 172 "bfin-lex.l"
+return DISALGNEXCPT;
+	YY_BREAK
+case 113:
+YY_RULE_SETUP
+#line 173 "bfin-lex.l"
+return DEPOSIT;
+	YY_BREAK
+case 114:
+YY_RULE_SETUP
+#line 174 "bfin-lex.l"
+return DBGHALT;
+	YY_BREAK
+case 115:
+YY_RULE_SETUP
+#line 175 "bfin-lex.l"
+return DBGCMPLX;
+	YY_BREAK
+case 116:
+YY_RULE_SETUP
+#line 176 "bfin-lex.l"
+return DBGAL;
+	YY_BREAK
+case 117:
+YY_RULE_SETUP
+#line 177 "bfin-lex.l"
+return DBGAH;
+	YY_BREAK
+case 118:
+YY_RULE_SETUP
+#line 178 "bfin-lex.l"
+return DBGA;
+	YY_BREAK
+case 119:
+YY_RULE_SETUP
+#line 179 "bfin-lex.l"
+return DBG;
+	YY_BREAK
+case 120:
+YY_RULE_SETUP
+#line 180 "bfin-lex.l"
+{ _REG.regno = REG_CYCLES2; return REG; }
+	YY_BREAK
+case 121:
+YY_RULE_SETUP
+#line 181 "bfin-lex.l"
+{ _REG.regno = REG_CYCLES; return REG; }
+	YY_BREAK
+case 122:
+YY_RULE_SETUP
+#line 182 "bfin-lex.l"
+return CSYNC;
+	YY_BREAK
+case 123:
+YY_RULE_SETUP
+#line 183 "bfin-lex.l"
+return CO;
+	YY_BREAK
+case 124:
+YY_RULE_SETUP
+#line 184 "bfin-lex.l"
+return CLI;
+	YY_BREAK
+case 125:
+YY_RULE_SETUP
+#line 186 "bfin-lex.l"
+_REG.regno = REG_CC; return CCREG;
+	YY_BREAK
+case 126:
+YY_RULE_SETUP
+#line 187 "bfin-lex.l"
+{ BEGIN 0; return CALL;}
+	YY_BREAK
+case 127:
+YY_RULE_SETUP
+#line 188 "bfin-lex.l"
+{ BEGIN 0; return CALL;}
+	YY_BREAK
+case 128:
+YY_RULE_SETUP
+#line 189 "bfin-lex.l"
+return BYTEUNPACK;
+	YY_BREAK
+case 129:
+YY_RULE_SETUP
+#line 190 "bfin-lex.l"
+return BYTEPACK;
+	YY_BREAK
+case 130:
+YY_RULE_SETUP
+#line 191 "bfin-lex.l"
+return BYTEOP16M;
+	YY_BREAK
+case 131:
+YY_RULE_SETUP
+#line 192 "bfin-lex.l"
+return BYTEOP16P;
+	YY_BREAK
+case 132:
+YY_RULE_SETUP
+#line 193 "bfin-lex.l"
+return BYTEOP3P;
+	YY_BREAK
+case 133:
+YY_RULE_SETUP
+#line 194 "bfin-lex.l"
+return BYTEOP2M;
+	YY_BREAK
+case 134:
+YY_RULE_SETUP
+#line 195 "bfin-lex.l"
+return BYTEOP2P;
+	YY_BREAK
+case 135:
+YY_RULE_SETUP
+#line 196 "bfin-lex.l"
+return BYTEOP1P;
+	YY_BREAK
+case 136:
+YY_RULE_SETUP
+#line 197 "bfin-lex.l"
+return BY;
+	YY_BREAK
+case 137:
+YY_RULE_SETUP
+#line 198 "bfin-lex.l"
+return BXORSHIFT;
+	YY_BREAK
+case 138:
+YY_RULE_SETUP
+#line 199 "bfin-lex.l"
+return BXOR;
+	YY_BREAK
+case 139:
+YY_RULE_SETUP
+#line 201 "bfin-lex.l"
+return BREV;
+	YY_BREAK
+case 140:
+YY_RULE_SETUP
+#line 202 "bfin-lex.l"
+return BP;
+	YY_BREAK
+case 141:
+YY_RULE_SETUP
+#line 203 "bfin-lex.l"
+return BITTST;
+	YY_BREAK
+case 142:
+YY_RULE_SETUP
+#line 204 "bfin-lex.l"
+return BITTGL;
+	YY_BREAK
+case 143:
+YY_RULE_SETUP
+#line 205 "bfin-lex.l"
+return BITSET;
+	YY_BREAK
+case 144:
+YY_RULE_SETUP
+#line 206 "bfin-lex.l"
+return BITMUX;
+	YY_BREAK
+case 145:
+YY_RULE_SETUP
+#line 207 "bfin-lex.l"
+return BITCLR;
+	YY_BREAK
+case 146:
+YY_RULE_SETUP
+#line 208 "bfin-lex.l"
+return parse_halfreg (&yylval.reg, T_REG_B, yytext);
+	YY_BREAK
+case 147:
+YY_RULE_SETUP
+#line 209 "bfin-lex.l"
+return parse_reg (&yylval.reg, T_REG_B, yytext);
+	YY_BREAK
+case 148:
+YY_RULE_SETUP
+#line 210 "bfin-lex.l"
+return B;
+	YY_BREAK
+case 149:
+YY_RULE_SETUP
+#line 211 "bfin-lex.l"
+_REG.regno = S_AZ;   return STATUS_REG;
+	YY_BREAK
+case 150:
+YY_RULE_SETUP
+#line 212 "bfin-lex.l"
+_REG.regno = S_AN;   return STATUS_REG;
+	YY_BREAK
+case 151:
+YY_RULE_SETUP
+#line 213 "bfin-lex.l"
+_REG.regno = S_AQ;   return STATUS_REG;
+	YY_BREAK
+case 152:
+YY_RULE_SETUP
+#line 214 "bfin-lex.l"
+_REG.regno = S_AC0;  return STATUS_REG;
+	YY_BREAK
+case 153:
+YY_RULE_SETUP
+#line 215 "bfin-lex.l"
+_REG.regno = S_AC1;  return STATUS_REG;
+	YY_BREAK
+case 154:
+YY_RULE_SETUP
+#line 216 "bfin-lex.l"
+_REG.regno = S_AV0;  return STATUS_REG;
+	YY_BREAK
+case 155:
+YY_RULE_SETUP
+#line 217 "bfin-lex.l"
+_REG.regno = S_AV0S; return STATUS_REG;
+	YY_BREAK
+case 156:
+YY_RULE_SETUP
+#line 218 "bfin-lex.l"
+_REG.regno = S_AV1;  return STATUS_REG;
+	YY_BREAK
+case 157:
+YY_RULE_SETUP
+#line 219 "bfin-lex.l"
+_REG.regno = S_AV1S; return STATUS_REG;
+	YY_BREAK
+case 158:
+YY_RULE_SETUP
+#line 220 "bfin-lex.l"
+_REG.regno = S_V; return STATUS_REG;
+	YY_BREAK
+case 159:
+YY_RULE_SETUP
+#line 221 "bfin-lex.l"
+_REG.regno = S_VS;   return STATUS_REG;
+	YY_BREAK
+case 160:
+YY_RULE_SETUP
+#line 224 "bfin-lex.l"
+_REG.regno = REG_ASTAT; return REG;
+	YY_BREAK
+case 161:
+YY_RULE_SETUP
+#line 225 "bfin-lex.l"
+return ASHIFT;
+	YY_BREAK
+case 162:
+YY_RULE_SETUP
+#line 226 "bfin-lex.l"
+return ASL;
+	YY_BREAK
+case 163:
+YY_RULE_SETUP
+#line 227 "bfin-lex.l"
+return ASR;
+	YY_BREAK
+case 164:
+YY_RULE_SETUP
+#line 228 "bfin-lex.l"
+return ALIGN8;
+	YY_BREAK
+case 165:
+YY_RULE_SETUP
+#line 229 "bfin-lex.l"
+return ALIGN16;
+	YY_BREAK
+case 166:
+YY_RULE_SETUP
+#line 230 "bfin-lex.l"
+return ALIGN24;
+	YY_BREAK
+case 167:
+YY_RULE_SETUP
+#line 231 "bfin-lex.l"
+return A_ONE_DOT_L;
+	YY_BREAK
+case 168:
+YY_RULE_SETUP
+#line 232 "bfin-lex.l"
+return A_ZERO_DOT_L;
+	YY_BREAK
+case 169:
+YY_RULE_SETUP
+#line 233 "bfin-lex.l"
+return A_ONE_DOT_H;
+	YY_BREAK
+case 170:
+YY_RULE_SETUP
+#line 234 "bfin-lex.l"
+return A_ZERO_DOT_H;
+	YY_BREAK
+case 171:
+YY_RULE_SETUP
+#line 235 "bfin-lex.l"
+return ABS;
+	YY_BREAK
+case 172:
+YY_RULE_SETUP
+#line 236 "bfin-lex.l"
+return ABORT;
+	YY_BREAK
+case 173:
+YY_RULE_SETUP
+#line 237 "bfin-lex.l"
+_REG.regno = REG_A1x; return REG;
+	YY_BREAK
+case 174:
+YY_RULE_SETUP
+#line 238 "bfin-lex.l"
+_REG.regno = REG_A1w; return REG;
+	YY_BREAK
+case 175:
+YY_RULE_SETUP
+#line 239 "bfin-lex.l"
+_REG.regno = REG_A1;  return REG_A_DOUBLE_ONE;
+	YY_BREAK
+case 176:
+YY_RULE_SETUP
+#line 240 "bfin-lex.l"
+_REG.regno = REG_A0x; return REG;
+	YY_BREAK
+case 177:
+YY_RULE_SETUP
+#line 241 "bfin-lex.l"
+_REG.regno = REG_A0w; return REG;
+	YY_BREAK
+case 178:
+YY_RULE_SETUP
+#line 242 "bfin-lex.l"
+_REG.regno = REG_A0;  return REG_A_DOUBLE_ZERO;
+	YY_BREAK
+case 179:
+YY_RULE_SETUP
+#line 243 "bfin-lex.l"
+return GOT;
+	YY_BREAK
+case 180:
+YY_RULE_SETUP
+#line 244 "bfin-lex.l"
+return GOT17M4;
+	YY_BREAK
+case 181:
+YY_RULE_SETUP
+#line 245 "bfin-lex.l"
+return FUNCDESC_GOT17M4;
+	YY_BREAK
+case 182:
+YY_RULE_SETUP
+#line 246 "bfin-lex.l"
+return PLTPC;
+	YY_BREAK
+case 183:
+YY_RULE_SETUP
+#line 249 "bfin-lex.l"
+return TILDA;
+	YY_BREAK
+case 184:
+YY_RULE_SETUP
+#line 250 "bfin-lex.l"
+return _BAR_ASSIGN;
+	YY_BREAK
+case 185:
+YY_RULE_SETUP
+#line 251 "bfin-lex.l"
+return BAR;
+	YY_BREAK
+case 186:
+YY_RULE_SETUP
+#line 252 "bfin-lex.l"
+return _CARET_ASSIGN;
+	YY_BREAK
+case 187:
+YY_RULE_SETUP
+#line 253 "bfin-lex.l"
+return CARET;
+	YY_BREAK
+case 188:
+YY_RULE_SETUP
+#line 254 "bfin-lex.l"
+return RBRACK;
+	YY_BREAK
+case 189:
+YY_RULE_SETUP
+#line 255 "bfin-lex.l"
+return LBRACK;
+	YY_BREAK
+case 190:
+YY_RULE_SETUP
+#line 256 "bfin-lex.l"
+return _GREATER_GREATER_GREATER_THAN_ASSIGN;
+	YY_BREAK
+case 191:
+YY_RULE_SETUP
+#line 257 "bfin-lex.l"
+return _GREATER_GREATER_ASSIGN;
+	YY_BREAK
+case 192:
+YY_RULE_SETUP
+#line 258 "bfin-lex.l"
+return _GREATER_GREATER_GREATER;
+	YY_BREAK
+case 193:
+YY_RULE_SETUP
+#line 259 "bfin-lex.l"
+return GREATER_GREATER;
+	YY_BREAK
+case 194:
+YY_RULE_SETUP
+#line 260 "bfin-lex.l"
+return _ASSIGN_ASSIGN;
+	YY_BREAK
+case 195:
+YY_RULE_SETUP
+#line 261 "bfin-lex.l"
+return ASSIGN;
+	YY_BREAK
+case 196:
+YY_RULE_SETUP
+#line 262 "bfin-lex.l"
+return _LESS_THAN_ASSIGN;
+	YY_BREAK
+case 197:
+YY_RULE_SETUP
+#line 263 "bfin-lex.l"
+return _LESS_LESS_ASSIGN;
+	YY_BREAK
+case 198:
+YY_RULE_SETUP
+#line 264 "bfin-lex.l"
+return LESS_LESS;
+	YY_BREAK
+case 199:
+YY_RULE_SETUP
+#line 265 "bfin-lex.l"
+return LESS_THAN;
+	YY_BREAK
+case 200:
+YY_RULE_SETUP
+#line 266 "bfin-lex.l"
+return LPAREN;
+	YY_BREAK
+case 201:
+YY_RULE_SETUP
+#line 267 "bfin-lex.l"
+return RPAREN;
+	YY_BREAK
+case 202:
+YY_RULE_SETUP
+#line 268 "bfin-lex.l"
+return COLON;
+	YY_BREAK
+case 203:
+YY_RULE_SETUP
+#line 269 "bfin-lex.l"
+return SLASH;
+	YY_BREAK
+case 204:
+YY_RULE_SETUP
+#line 270 "bfin-lex.l"
+return _MINUS_ASSIGN;
+	YY_BREAK
+case 205:
+YY_RULE_SETUP
+#line 271 "bfin-lex.l"
+return _PLUS_BAR_PLUS;
+	YY_BREAK
+case 206:
+YY_RULE_SETUP
+#line 272 "bfin-lex.l"
+return _MINUS_BAR_PLUS;
+	YY_BREAK
+case 207:
+YY_RULE_SETUP
+#line 273 "bfin-lex.l"
+return _PLUS_BAR_MINUS;
+	YY_BREAK
+case 208:
+YY_RULE_SETUP
+#line 274 "bfin-lex.l"
+return _MINUS_BAR_MINUS;
+	YY_BREAK
+case 209:
+YY_RULE_SETUP
+#line 275 "bfin-lex.l"
+return _MINUS_MINUS;
+	YY_BREAK
+case 210:
+YY_RULE_SETUP
+#line 276 "bfin-lex.l"
+return MINUS;
+	YY_BREAK
+case 211:
+YY_RULE_SETUP
+#line 277 "bfin-lex.l"
+return COMMA;
+	YY_BREAK
+case 212:
+YY_RULE_SETUP
+#line 278 "bfin-lex.l"
+return _PLUS_ASSIGN;
+	YY_BREAK
+case 213:
+YY_RULE_SETUP
+#line 279 "bfin-lex.l"
+return _PLUS_PLUS;
+	YY_BREAK
+case 214:
+YY_RULE_SETUP
+#line 280 "bfin-lex.l"
+return PLUS;
+	YY_BREAK
+case 215:
+YY_RULE_SETUP
+#line 281 "bfin-lex.l"
+return _STAR_ASSIGN;
+	YY_BREAK
+case 216:
+YY_RULE_SETUP
+#line 282 "bfin-lex.l"
+return STAR;
+	YY_BREAK
+case 217:
+YY_RULE_SETUP
+#line 283 "bfin-lex.l"
+return _AMPERSAND_ASSIGN;
+	YY_BREAK
+case 218:
+YY_RULE_SETUP
+#line 284 "bfin-lex.l"
+return AMPERSAND;
+	YY_BREAK
+case 219:
+YY_RULE_SETUP
+#line 285 "bfin-lex.l"
+return PERCENT;
+	YY_BREAK
+case 220:
+YY_RULE_SETUP
+#line 286 "bfin-lex.l"
+return BANG;
+	YY_BREAK
+case 221:
+YY_RULE_SETUP
+#line 287 "bfin-lex.l"
+return SEMICOLON;
+	YY_BREAK
+case 222:
+YY_RULE_SETUP
+#line 288 "bfin-lex.l"
+return _ASSIGN_BANG;
+	YY_BREAK
+case 223:
+YY_RULE_SETUP
+#line 289 "bfin-lex.l"
+return DOUBLE_BAR;
+	YY_BREAK
+case 224:
+YY_RULE_SETUP
+#line 290 "bfin-lex.l"
+return AT;
+	YY_BREAK
+case 225:
+YY_RULE_SETUP
+#line 291 "bfin-lex.l"
+return PREFETCH;
+	YY_BREAK
+case 226:
+YY_RULE_SETUP
+#line 292 "bfin-lex.l"
+return UNLINK;
+	YY_BREAK
+case 227:
+YY_RULE_SETUP
+#line 293 "bfin-lex.l"
+return LINK;
+	YY_BREAK
+case 228:
+YY_RULE_SETUP
+#line 294 "bfin-lex.l"
+return IDLE;
+	YY_BREAK
+case 229:
+YY_RULE_SETUP
+#line 295 "bfin-lex.l"
+return IFLUSH;
+	YY_BREAK
+case 230:
+YY_RULE_SETUP
+#line 296 "bfin-lex.l"
+return FLUSHINV;
+	YY_BREAK
+case 231:
+YY_RULE_SETUP
+#line 297 "bfin-lex.l"
+return FLUSH;
+	YY_BREAK
+case 232:
+YY_RULE_SETUP
+#line 298 "bfin-lex.l"
+{
+    yylval.value = parse_int (&yytext);
+    return NUMBER;
+  }
+	YY_BREAK
+case 233:
+YY_RULE_SETUP
+#line 302 "bfin-lex.l"
+{ 
+    yylval.symbol = symbol_find_or_make (yytext);
+    symbol_mark_used (yylval.symbol);
+    return SYMBOL; 
+  }
+	YY_BREAK
+case 234:
+YY_RULE_SETUP
+#line 307 "bfin-lex.l"
+{
+    char *name;
+    char *ref = strdup (yytext);
+    if (ref[1] == 'b' || ref[1] == 'B')
+      {
+        name = fb_label_name ((int) (ref[0] - '0'), 0);
+	yylval.symbol = symbol_find (name);
+
+	if ((yylval.symbol != NULL)
+             && (S_IS_DEFINED (yylval.symbol)))
+          return SYMBOL;
+	as_bad ("backward reference to unknown label %d:", 
+						  (int) (ref[0] - '0')); 
+      }
+    else if (ref[1] == 'f' || ref[1] == 'F')
+      {
+        /* Forward reference.  Expect symbol to be undefined or
+           unknown.  undefined: seen it before.  unknown: never seen
+           it before.
+
+           Construct a local label name, then an undefined symbol.
+           Just return it as never seen before.  */
+
+        name = fb_label_name ((int) (ref[0] - '0'), 1);
+	yylval.symbol = symbol_find_or_make (name);
+	/* We have no need to check symbol properties.  */
+	return SYMBOL;
+      }                                  
+  }                                  
+	YY_BREAK
+case 235:
+YY_RULE_SETUP
+#line 336 "bfin-lex.l"
+;
+	YY_BREAK
+case 236:
+YY_RULE_SETUP
+#line 337 "bfin-lex.l"
+;
+	YY_BREAK
+case 237:
+YY_RULE_SETUP
+#line 338 "bfin-lex.l"
+return yytext[0];
+	YY_BREAK
+case 238:
+YY_RULE_SETUP
+#line 339 "bfin-lex.l"
+ECHO;
+	YY_BREAK
+#line 2260 "bfin-lex.c"
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(KEYWORD):
+	yyterminate();
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - yytext_ptr) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = yy_hold_char;
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed yyin at a new source and called
+			 * yylex().  If so, then we have to assure
+			 * consistency between yy_current_buffer and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			yy_n_chars = yy_current_buffer->yy_n_chars;
+			yy_current_buffer->yy_input_file = yyin;
+			yy_current_buffer->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( yy_c_buf_p <= &yy_current_buffer->yy_ch_buf[yy_n_chars] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			yy_c_buf_p = yytext_ptr + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state();
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = yytext_ptr + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++yy_c_buf_p;
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+				yy_cp = yy_c_buf_p;
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer() )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				yy_did_buffer_switch_on_eof = 0;
+
+				if ( yywrap() )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * yytext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					yy_c_buf_p = yytext_ptr + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! yy_did_buffer_switch_on_eof )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				yy_c_buf_p =
+					yytext_ptr + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state();
+
+				yy_cp = yy_c_buf_p;
+				yy_bp = yytext_ptr + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				yy_c_buf_p =
+				&yy_current_buffer->yy_ch_buf[yy_n_chars];
+
+				yy_current_state = yy_get_previous_state();
+
+				yy_cp = yy_c_buf_p;
+				yy_bp = yytext_ptr + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+	} /* end of yylex */
+
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+
+static int yy_get_next_buffer()
+	{
+	register char *dest = yy_current_buffer->yy_ch_buf;
+	register char *source = yytext_ptr;
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( yy_c_buf_p > &yy_current_buffer->yy_ch_buf[yy_n_chars + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( yy_current_buffer->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( yy_c_buf_p - yytext_ptr - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) (yy_c_buf_p - yytext_ptr) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( yy_current_buffer->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		yy_current_buffer->yy_n_chars = yy_n_chars = 0;
+
+	else
+		{
+		int num_to_read =
+			yy_current_buffer->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+#ifdef YY_USES_REJECT
+			YY_FATAL_ERROR(
+"input buffer overflow, can't enlarge buffer because scanner uses REJECT" );
+#else
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = yy_current_buffer;
+
+			int yy_c_buf_p_offset =
+				(int) (yy_c_buf_p - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					yy_flex_realloc( (void *) b->yy_ch_buf,
+							 b->yy_buf_size + 2 );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			yy_c_buf_p = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = yy_current_buffer->yy_buf_size -
+						number_to_move - 1;
+#endif
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&yy_current_buffer->yy_ch_buf[number_to_move]),
+			yy_n_chars, num_to_read );
+
+		yy_current_buffer->yy_n_chars = yy_n_chars;
+		}
+
+	if ( yy_n_chars == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			yyrestart( yyin );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			yy_current_buffer->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	yy_n_chars += number_to_move;
+	yy_current_buffer->yy_ch_buf[yy_n_chars] = YY_END_OF_BUFFER_CHAR;
+	yy_current_buffer->yy_ch_buf[yy_n_chars + 1] = YY_END_OF_BUFFER_CHAR;
+
+	yytext_ptr = &yy_current_buffer->yy_ch_buf[0];
+
+	return ret_val;
+	}
+
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+static yy_state_type yy_get_previous_state()
+	{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+
+	yy_current_state = yy_start;
+
+	for ( yy_cp = yytext_ptr + YY_MORE_ADJ; yy_cp < yy_c_buf_p; ++yy_cp )
+		{
+		register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+		if ( yy_accept[yy_current_state] )
+			{
+			yy_last_accepting_state = yy_current_state;
+			yy_last_accepting_cpos = yy_cp;
+			}
+		while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+			{
+			yy_current_state = (int) yy_def[yy_current_state];
+			if ( yy_current_state >= 559 )
+				yy_c = yy_meta[(unsigned int) yy_c];
+			}
+		yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+		}
+
+	return yy_current_state;
+	}
+
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+
+#ifdef YY_USE_PROTOS
+static yy_state_type yy_try_NUL_trans( yy_state_type yy_current_state )
+#else
+static yy_state_type yy_try_NUL_trans( yy_current_state )
+yy_state_type yy_current_state;
+#endif
+	{
+	register int yy_is_jam;
+	register char *yy_cp = yy_c_buf_p;
+
+	register YY_CHAR yy_c = 1;
+	if ( yy_accept[yy_current_state] )
+		{
+		yy_last_accepting_state = yy_current_state;
+		yy_last_accepting_cpos = yy_cp;
+		}
+	while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+		{
+		yy_current_state = (int) yy_def[yy_current_state];
+		if ( yy_current_state >= 559 )
+			yy_c = yy_meta[(unsigned int) yy_c];
+		}
+	yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+	yy_is_jam = (yy_current_state == 558);
+
+	return yy_is_jam ? 0 : yy_current_state;
+	}
+
+
+#ifndef YY_NO_UNPUT
+#ifdef YY_USE_PROTOS
+static void yyunput( int c, register char *yy_bp )
+#else
+static void yyunput( c, yy_bp )
+int c;
+register char *yy_bp;
+#endif
+	{
+	register char *yy_cp = yy_c_buf_p;
+
+	/* undo effects of setting up yytext */
+	*yy_cp = yy_hold_char;
+
+	if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = yy_n_chars + 2;
+		register char *dest = &yy_current_buffer->yy_ch_buf[
+					yy_current_buffer->yy_buf_size + 2];
+		register char *source =
+				&yy_current_buffer->yy_ch_buf[number_to_move];
+
+		while ( source > yy_current_buffer->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		yy_current_buffer->yy_n_chars =
+			yy_n_chars = yy_current_buffer->yy_buf_size;
+
+		if ( yy_cp < yy_current_buffer->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+
+	yytext_ptr = yy_bp;
+	yy_hold_char = *yy_cp;
+	yy_c_buf_p = yy_cp;
+	}
+#endif	/* ifndef YY_NO_UNPUT */
+
+
+#ifdef __cplusplus
+static int yyinput()
+#else
+static int input()
+#endif
+	{
+	int c;
+
+	*yy_c_buf_p = yy_hold_char;
+
+	if ( *yy_c_buf_p == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( yy_c_buf_p < &yy_current_buffer->yy_ch_buf[yy_n_chars] )
+			/* This was really a NUL. */
+			*yy_c_buf_p = '\0';
+
+		else
+			{ /* need more input */
+			int offset = yy_c_buf_p - yytext_ptr;
+			++yy_c_buf_p;
+
+			switch ( yy_get_next_buffer() )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					yyrestart( yyin );
+
+					/* fall through */
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( yywrap() )
+						return EOF;
+
+					if ( ! yy_did_buffer_switch_on_eof )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					yy_c_buf_p = yytext_ptr + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) yy_c_buf_p;	/* cast for 8-bit char's */
+	*yy_c_buf_p = '\0';	/* preserve yytext */
+	yy_hold_char = *++yy_c_buf_p;
+
+
+	return c;
+	}
+
+
+#ifdef YY_USE_PROTOS
+void yyrestart( FILE *input_file )
+#else
+void yyrestart( input_file )
+FILE *input_file;
+#endif
+	{
+	if ( ! yy_current_buffer )
+		yy_current_buffer = yy_create_buffer( yyin, YY_BUF_SIZE );
+
+	yy_init_buffer( yy_current_buffer, input_file );
+	yy_load_buffer_state();
+	}
+
+
+#ifdef YY_USE_PROTOS
+void yy_switch_to_buffer( YY_BUFFER_STATE new_buffer )
+#else
+void yy_switch_to_buffer( new_buffer )
+YY_BUFFER_STATE new_buffer;
+#endif
+	{
+	if ( yy_current_buffer == new_buffer )
+		return;
+
+	if ( yy_current_buffer )
+		{
+		/* Flush out information for old buffer. */
+		*yy_c_buf_p = yy_hold_char;
+		yy_current_buffer->yy_buf_pos = yy_c_buf_p;
+		yy_current_buffer->yy_n_chars = yy_n_chars;
+		}
+
+	yy_current_buffer = new_buffer;
+	yy_load_buffer_state();
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (yywrap()) processing, but the only time this flag
+	 * is looked at is after yywrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	yy_did_buffer_switch_on_eof = 1;
+	}
+
+
+#ifdef YY_USE_PROTOS
+void yy_load_buffer_state( void )
+#else
+void yy_load_buffer_state()
+#endif
+	{
+	yy_n_chars = yy_current_buffer->yy_n_chars;
+	yytext_ptr = yy_c_buf_p = yy_current_buffer->yy_buf_pos;
+	yyin = yy_current_buffer->yy_input_file;
+	yy_hold_char = *yy_c_buf_p;
+	}
+
+
+#ifdef YY_USE_PROTOS
+YY_BUFFER_STATE yy_create_buffer( FILE *file, int size )
+#else
+YY_BUFFER_STATE yy_create_buffer( file, size )
+FILE *file;
+int size;
+#endif
+	{
+	YY_BUFFER_STATE b;
+
+	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) yy_flex_alloc( b->yy_buf_size + 2 );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	yy_init_buffer( b, file );
+
+	return b;
+	}
+
+
+#ifdef YY_USE_PROTOS
+void yy_delete_buffer( YY_BUFFER_STATE b )
+#else
+void yy_delete_buffer( b )
+YY_BUFFER_STATE b;
+#endif
+	{
+	if ( ! b )
+		return;
+
+	if ( b == yy_current_buffer )
+		yy_current_buffer = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		yy_flex_free( (void *) b->yy_ch_buf );
+
+	yy_flex_free( (void *) b );
+	}
+
+
+#ifndef _WIN32
+#include <unistd.h>
+#else
+#ifndef YY_ALWAYS_INTERACTIVE
+#ifndef YY_NEVER_INTERACTIVE
+extern int isatty YY_PROTO(( int ));
+#endif
+#endif
+#endif
+
+#ifdef YY_USE_PROTOS
+void yy_init_buffer( YY_BUFFER_STATE b, FILE *file )
+#else
+void yy_init_buffer( b, file )
+YY_BUFFER_STATE b;
+FILE *file;
+#endif
+
+
+	{
+	yy_flush_buffer( b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+#if YY_ALWAYS_INTERACTIVE
+	b->yy_is_interactive = 1;
+#else
+#if YY_NEVER_INTERACTIVE
+	b->yy_is_interactive = 0;
+#else
+	b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+#endif
+#endif
+	}
+
+
+#ifdef YY_USE_PROTOS
+void yy_flush_buffer( YY_BUFFER_STATE b )
+#else
+void yy_flush_buffer( b )
+YY_BUFFER_STATE b;
+#endif
+
+	{
+	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == yy_current_buffer )
+		yy_load_buffer_state();
+	}
+
+
+#ifndef YY_NO_SCAN_BUFFER
+#ifdef YY_USE_PROTOS
+YY_BUFFER_STATE yy_scan_buffer( char *base, yy_size_t size )
+#else
+YY_BUFFER_STATE yy_scan_buffer( base, size )
+char *base;
+yy_size_t size;
+#endif
+	{
+	YY_BUFFER_STATE b;
+
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) yy_flex_alloc( sizeof( struct yy_buffer_state ) );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	yy_switch_to_buffer( b );
+
+	return b;
+	}
+#endif
+
+
+#ifndef YY_NO_SCAN_STRING
+#ifdef YY_USE_PROTOS
+YY_BUFFER_STATE yy_scan_string( yyconst char *yy_str )
+#else
+YY_BUFFER_STATE yy_scan_string( yy_str )
+yyconst char *yy_str;
+#endif
+	{
+	int len;
+	for ( len = 0; yy_str[len]; ++len )
+		;
+
+	return yy_scan_bytes( yy_str, len );
+	}
+#endif
+
+
+#ifndef YY_NO_SCAN_BYTES
+#ifdef YY_USE_PROTOS
+YY_BUFFER_STATE yy_scan_bytes( yyconst char *bytes, int len )
+#else
+YY_BUFFER_STATE yy_scan_bytes( bytes, len )
+yyconst char *bytes;
+int len;
+#endif
+	{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = len + 2;
+	buf = (char *) yy_flex_alloc( n );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" );
+
+	for ( i = 0; i < len; ++i )
+		buf[i] = bytes[i];
+
+	buf[len] = buf[len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = yy_scan_buffer( buf, n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+	}
+#endif
+
+
+#ifndef YY_NO_PUSH_STATE
+#ifdef YY_USE_PROTOS
+static void yy_push_state( int new_state )
+#else
+static void yy_push_state( new_state )
+int new_state;
+#endif
+	{
+	if ( yy_start_stack_ptr >= yy_start_stack_depth )
+		{
+		yy_size_t new_size;
+
+		yy_start_stack_depth += YY_START_STACK_INCR;
+		new_size = yy_start_stack_depth * sizeof( int );
+
+		if ( ! yy_start_stack )
+			yy_start_stack = (int *) yy_flex_alloc( new_size );
+
+		else
+			yy_start_stack = (int *) yy_flex_realloc(
+					(void *) yy_start_stack, new_size );
+
+		if ( ! yy_start_stack )
+			YY_FATAL_ERROR(
+			"out of memory expanding start-condition stack" );
+		}
+
+	yy_start_stack[yy_start_stack_ptr++] = YY_START;
+
+	BEGIN(new_state);
+	}
+#endif
+
+
+#ifndef YY_NO_POP_STATE
+static void yy_pop_state()
+	{
+	if ( --yy_start_stack_ptr < 0 )
+		YY_FATAL_ERROR( "start-condition stack underflow" );
+
+	BEGIN(yy_start_stack[yy_start_stack_ptr]);
+	}
+#endif
+
+
+#ifndef YY_NO_TOP_STATE
+static int yy_top_state()
+	{
+	return yy_start_stack[yy_start_stack_ptr - 1];
+	}
+#endif
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+#ifdef YY_USE_PROTOS
+static void yy_fatal_error( yyconst char msg[] )
+#else
+static void yy_fatal_error( msg )
+char msg[];
+#endif
+	{
+	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+	}
+
+
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up yytext. */ \
+		yytext[yyleng] = yy_hold_char; \
+		yy_c_buf_p = yytext + n; \
+		yy_hold_char = *yy_c_buf_p; \
+		*yy_c_buf_p = '\0'; \
+		yyleng = n; \
+		} \
+	while ( 0 )
+
+
+/* Internal utility routines. */
+
+#ifndef yytext_ptr
+#ifdef YY_USE_PROTOS
+static void yy_flex_strncpy( char *s1, yyconst char *s2, int n )
+#else
+static void yy_flex_strncpy( s1, s2, n )
+char *s1;
+yyconst char *s2;
+int n;
+#endif
+	{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+	}
+#endif
+
+#ifdef YY_NEED_STRLEN
+#ifdef YY_USE_PROTOS
+static int yy_flex_strlen( yyconst char *s )
+#else
+static int yy_flex_strlen( s )
+yyconst char *s;
+#endif
+	{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+	}
+#endif
+
+
+#ifdef YY_USE_PROTOS
+static void *yy_flex_alloc( yy_size_t size )
+#else
+static void *yy_flex_alloc( size )
+yy_size_t size;
+#endif
+	{
+	return (void *) malloc( size );
+	}
+
+#ifdef YY_USE_PROTOS
+static void *yy_flex_realloc( void *ptr, yy_size_t size )
+#else
+static void *yy_flex_realloc( ptr, size )
+void *ptr;
+yy_size_t size;
+#endif
+	{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+	}
+
+#ifdef YY_USE_PROTOS
+static void yy_flex_free( void *ptr )
+#else
+static void yy_flex_free( ptr )
+void *ptr;
+#endif
+	{
+	free( ptr );
+	}
+
+#if YY_MAIN
+int main()
+	{
+	yylex();
+	return 0;
+	}
+#endif
+#line 339 "bfin-lex.l"
+
+static long parse_int (char **end)
+{
+  char fmt = '\0';
+  int not_done = 1;
+  int shiftvalue = 0;
+  char * char_bag;
+  long value = 0;
+  char c;
+  char *arg = *end;
+
+  while (*arg && *arg == ' ')
+    arg++;
+
+  switch (*arg)
+    {
+      case '1':
+      case '2':
+      case '3':
+      case '4':
+      case '5':
+      case '6':
+      case '7':
+      case '8':
+      case '9':
+        fmt = 'd';
+        break;
+
+      case '0':  /* Accept different formated integers hex octal and binary. */
+        {
+	  c = *++arg;
+          arg++;
+	  if (c == 'x' || c == 'X') /* Hex input.  */
+	    fmt = 'h';
+	  else if (c == 'b' || c == 'B')
+	    fmt = 'b';
+	  else if (c == '.')
+	    fmt = 'f';
+	  else
+            {             /* Octal.  */
+	      arg--;
+	      fmt = 'o';
+	    }
+	  break;
+        }
+
+      case 'd':
+      case 'D':
+      case 'h':
+      case 'H':
+      case 'o':
+      case 'O':
+      case 'b':
+      case 'B':
+      case 'f':
+      case 'F':
+        {
+	  fmt = *arg++;
+	  if (*arg == '#')
+	    arg++;
+        }
+    }
+
+  switch (fmt)
+    {
+      case 'h':
+      case 'H':
+        shiftvalue = 4;
+        char_bag = "0123456789ABCDEFabcdef";
+        break;
+
+      case 'o':
+      case 'O':
+        shiftvalue = 3;
+        char_bag = "01234567";
+        break;
+
+      case 'b':
+      case 'B':
+        shiftvalue = 1;
+        char_bag = "01";
+        break;
+
+/* The assembler allows for fractional constants to be created
+   by either the 0.xxxx or the f#xxxx format 
+
+   i.e.   0.5 would result in 0x4000
+
+   note .5 would result in the identifier .5.
+
+   The assembler converts to fractional format 1.15 by the simple rule:
+
+             value = (short) (finput * (1 << 15)).  */
+
+      case 'f':
+      case 'F':
+        {
+          float fval = 0.0;
+          float pos = 10.0;
+          while (1)
+            {
+              int c;
+              c = *arg++;
+
+              if (c >= '0' && c <= '9')
+                {
+                  float digit = (c - '0') / pos;
+                  fval = fval + digit;
+                  pos = pos * 10.0;
+                }
+              else
+                {
+	          *--arg = c;
+                  value = (short) (fval * (1 << 15));
+                  break;
+                }
+            }
+          *end = arg+1;
+          return value;
+        }
+
+      case 'd':
+      case 'D':
+      default:
+        {
+          while (1)
+            {
+              int c;
+              c = *arg++;
+              if (c >= '0' && c <= '9')
+                value = (value * 10) + (c - '0');
+              else
+                {
+                  /* Constants that are suffixed with k|K are multiplied by 1024
+                     This suffix is only allowed on decimal constants. */
+                  if (c == 'k' || c == 'K')
+                    value *= 1024;
+                  else
+                    *--arg = c;
+                  break;
+                }
+            }
+          *end = arg+1;
+          return value;
+        }
+    }
+
+  while (not_done)
+    {
+      char c;
+      c = *arg++;
+      if (c == 0 || !index (char_bag, c))
+	{
+          not_done = 0;
+          *--arg = c;
+        }
+      else
+        {
+          if (c >= 'a' && c <= 'z')
+            c = c - ('a' - '9') + 1;
+          else if (c >= 'A' && c <= 'Z')
+            c = c - ('A' - '9') + 1;
+
+          c -= '0';
+          value = (value << shiftvalue) + c;
+        }
+    }
+  *end = arg+1;
+  return value;
+}
+
+
+static int parse_reg (Register *r, int cl, char *rt)
+{
+  r->regno = cl | (rt[1] - '0');
+  return REG;
+}
+
+static int parse_halfreg (Register *r, int cl, char *rt)
+{
+  r->regno = cl | (rt[1] - '0');
+
+  switch (rt[3])
+    {
+      case 'b':
+      case 'B':
+	return BYTE_DREG;
+
+      case 'l':
+      case 'L':
+	break;
+
+      case 'h':
+      case 'H':
+	r->regno |= F_REG_HIGH;
+	break;
+    }
+
+  return HALF_REG;
+}
+
+/* Our start state is KEYWORD as we have
+   command keywords such as PREFETCH.  */
+
+void 
+set_start_state (void)
+{
+  BEGIN KEYWORD;
+}
+
+
+#ifndef yywrap
+int
+yywrap ()
+{ 
+  return 1;
+}
+#endif
diff --git a/gas/bfin-parse.c b/gas/bfin-parse.c
new file mode 100644
index 000000000000..bc6728b659ba
--- /dev/null
+++ b/gas/bfin-parse.c
@@ -0,0 +1,7491 @@
+/* A Bison parser, made by GNU Bison 2.1.  */
+
+/* Skeleton parser for Yacc-like parsing with Bison,
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* Written by Richard Stallman by simplifying the original so called
+   ``semantic'' parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.1"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     BYTEOP16P = 258,
+     BYTEOP16M = 259,
+     BYTEOP1P = 260,
+     BYTEOP2P = 261,
+     BYTEOP2M = 262,
+     BYTEOP3P = 263,
+     BYTEUNPACK = 264,
+     BYTEPACK = 265,
+     PACK = 266,
+     SAA = 267,
+     ALIGN8 = 268,
+     ALIGN16 = 269,
+     ALIGN24 = 270,
+     VIT_MAX = 271,
+     EXTRACT = 272,
+     DEPOSIT = 273,
+     EXPADJ = 274,
+     SEARCH = 275,
+     ONES = 276,
+     SIGN = 277,
+     SIGNBITS = 278,
+     LINK = 279,
+     UNLINK = 280,
+     REG = 281,
+     PC = 282,
+     CCREG = 283,
+     BYTE_DREG = 284,
+     REG_A_DOUBLE_ZERO = 285,
+     REG_A_DOUBLE_ONE = 286,
+     A_ZERO_DOT_L = 287,
+     A_ZERO_DOT_H = 288,
+     A_ONE_DOT_L = 289,
+     A_ONE_DOT_H = 290,
+     HALF_REG = 291,
+     NOP = 292,
+     RTI = 293,
+     RTS = 294,
+     RTX = 295,
+     RTN = 296,
+     RTE = 297,
+     HLT = 298,
+     IDLE = 299,
+     STI = 300,
+     CLI = 301,
+     CSYNC = 302,
+     SSYNC = 303,
+     EMUEXCPT = 304,
+     RAISE = 305,
+     EXCPT = 306,
+     LSETUP = 307,
+     LOOP = 308,
+     LOOP_BEGIN = 309,
+     LOOP_END = 310,
+     DISALGNEXCPT = 311,
+     JUMP = 312,
+     JUMP_DOT_S = 313,
+     JUMP_DOT_L = 314,
+     CALL = 315,
+     ABORT = 316,
+     NOT = 317,
+     TILDA = 318,
+     BANG = 319,
+     AMPERSAND = 320,
+     BAR = 321,
+     PERCENT = 322,
+     CARET = 323,
+     BXOR = 324,
+     MINUS = 325,
+     PLUS = 326,
+     STAR = 327,
+     SLASH = 328,
+     NEG = 329,
+     MIN = 330,
+     MAX = 331,
+     ABS = 332,
+     DOUBLE_BAR = 333,
+     _PLUS_BAR_PLUS = 334,
+     _PLUS_BAR_MINUS = 335,
+     _MINUS_BAR_PLUS = 336,
+     _MINUS_BAR_MINUS = 337,
+     _MINUS_MINUS = 338,
+     _PLUS_PLUS = 339,
+     SHIFT = 340,
+     LSHIFT = 341,
+     ASHIFT = 342,
+     BXORSHIFT = 343,
+     _GREATER_GREATER_GREATER_THAN_ASSIGN = 344,
+     ROT = 345,
+     LESS_LESS = 346,
+     GREATER_GREATER = 347,
+     _GREATER_GREATER_GREATER = 348,
+     _LESS_LESS_ASSIGN = 349,
+     _GREATER_GREATER_ASSIGN = 350,
+     DIVS = 351,
+     DIVQ = 352,
+     ASSIGN = 353,
+     _STAR_ASSIGN = 354,
+     _BAR_ASSIGN = 355,
+     _CARET_ASSIGN = 356,
+     _AMPERSAND_ASSIGN = 357,
+     _MINUS_ASSIGN = 358,
+     _PLUS_ASSIGN = 359,
+     _ASSIGN_BANG = 360,
+     _LESS_THAN_ASSIGN = 361,
+     _ASSIGN_ASSIGN = 362,
+     GE = 363,
+     LT = 364,
+     LE = 365,
+     GT = 366,
+     LESS_THAN = 367,
+     FLUSHINV = 368,
+     FLUSH = 369,
+     IFLUSH = 370,
+     PREFETCH = 371,
+     PRNT = 372,
+     OUTC = 373,
+     WHATREG = 374,
+     TESTSET = 375,
+     ASL = 376,
+     ASR = 377,
+     B = 378,
+     W = 379,
+     NS = 380,
+     S = 381,
+     CO = 382,
+     SCO = 383,
+     TH = 384,
+     TL = 385,
+     BP = 386,
+     BREV = 387,
+     X = 388,
+     Z = 389,
+     M = 390,
+     MMOD = 391,
+     R = 392,
+     RND = 393,
+     RNDL = 394,
+     RNDH = 395,
+     RND12 = 396,
+     RND20 = 397,
+     V = 398,
+     LO = 399,
+     HI = 400,
+     BITTGL = 401,
+     BITCLR = 402,
+     BITSET = 403,
+     BITTST = 404,
+     BITMUX = 405,
+     DBGAL = 406,
+     DBGAH = 407,
+     DBGHALT = 408,
+     DBG = 409,
+     DBGA = 410,
+     DBGCMPLX = 411,
+     IF = 412,
+     COMMA = 413,
+     BY = 414,
+     COLON = 415,
+     SEMICOLON = 416,
+     RPAREN = 417,
+     LPAREN = 418,
+     LBRACK = 419,
+     RBRACK = 420,
+     STATUS_REG = 421,
+     MNOP = 422,
+     SYMBOL = 423,
+     NUMBER = 424,
+     GOT = 425,
+     GOT17M4 = 426,
+     FUNCDESC_GOT17M4 = 427,
+     AT = 428,
+     PLTPC = 429
+   };
+#endif
+/* Tokens.  */
+#define BYTEOP16P 258
+#define BYTEOP16M 259
+#define BYTEOP1P 260
+#define BYTEOP2P 261
+#define BYTEOP2M 262
+#define BYTEOP3P 263
+#define BYTEUNPACK 264
+#define BYTEPACK 265
+#define PACK 266
+#define SAA 267
+#define ALIGN8 268
+#define ALIGN16 269
+#define ALIGN24 270
+#define VIT_MAX 271
+#define EXTRACT 272
+#define DEPOSIT 273
+#define EXPADJ 274
+#define SEARCH 275
+#define ONES 276
+#define SIGN 277
+#define SIGNBITS 278
+#define LINK 279
+#define UNLINK 280
+#define REG 281
+#define PC 282
+#define CCREG 283
+#define BYTE_DREG 284
+#define REG_A_DOUBLE_ZERO 285
+#define REG_A_DOUBLE_ONE 286
+#define A_ZERO_DOT_L 287
+#define A_ZERO_DOT_H 288
+#define A_ONE_DOT_L 289
+#define A_ONE_DOT_H 290
+#define HALF_REG 291
+#define NOP 292
+#define RTI 293
+#define RTS 294
+#define RTX 295
+#define RTN 296
+#define RTE 297
+#define HLT 298
+#define IDLE 299
+#define STI 300
+#define CLI 301
+#define CSYNC 302
+#define SSYNC 303
+#define EMUEXCPT 304
+#define RAISE 305
+#define EXCPT 306
+#define LSETUP 307
+#define LOOP 308
+#define LOOP_BEGIN 309
+#define LOOP_END 310
+#define DISALGNEXCPT 311
+#define JUMP 312
+#define JUMP_DOT_S 313
+#define JUMP_DOT_L 314
+#define CALL 315
+#define ABORT 316
+#define NOT 317
+#define TILDA 318
+#define BANG 319
+#define AMPERSAND 320
+#define BAR 321
+#define PERCENT 322
+#define CARET 323
+#define BXOR 324
+#define MINUS 325
+#define PLUS 326
+#define STAR 327
+#define SLASH 328
+#define NEG 329
+#define MIN 330
+#define MAX 331
+#define ABS 332
+#define DOUBLE_BAR 333
+#define _PLUS_BAR_PLUS 334
+#define _PLUS_BAR_MINUS 335
+#define _MINUS_BAR_PLUS 336
+#define _MINUS_BAR_MINUS 337
+#define _MINUS_MINUS 338
+#define _PLUS_PLUS 339
+#define SHIFT 340
+#define LSHIFT 341
+#define ASHIFT 342
+#define BXORSHIFT 343
+#define _GREATER_GREATER_GREATER_THAN_ASSIGN 344
+#define ROT 345
+#define LESS_LESS 346
+#define GREATER_GREATER 347
+#define _GREATER_GREATER_GREATER 348
+#define _LESS_LESS_ASSIGN 349
+#define _GREATER_GREATER_ASSIGN 350
+#define DIVS 351
+#define DIVQ 352
+#define ASSIGN 353
+#define _STAR_ASSIGN 354
+#define _BAR_ASSIGN 355
+#define _CARET_ASSIGN 356
+#define _AMPERSAND_ASSIGN 357
+#define _MINUS_ASSIGN 358
+#define _PLUS_ASSIGN 359
+#define _ASSIGN_BANG 360
+#define _LESS_THAN_ASSIGN 361
+#define _ASSIGN_ASSIGN 362
+#define GE 363
+#define LT 364
+#define LE 365
+#define GT 366
+#define LESS_THAN 367
+#define FLUSHINV 368
+#define FLUSH 369
+#define IFLUSH 370
+#define PREFETCH 371
+#define PRNT 372
+#define OUTC 373
+#define WHATREG 374
+#define TESTSET 375
+#define ASL 376
+#define ASR 377
+#define B 378
+#define W 379
+#define NS 380
+#define S 381
+#define CO 382
+#define SCO 383
+#define TH 384
+#define TL 385
+#define BP 386
+#define BREV 387
+#define X 388
+#define Z 389
+#define M 390
+#define MMOD 391
+#define R 392
+#define RND 393
+#define RNDL 394
+#define RNDH 395
+#define RND12 396
+#define RND20 397
+#define V 398
+#define LO 399
+#define HI 400
+#define BITTGL 401
+#define BITCLR 402
+#define BITSET 403
+#define BITTST 404
+#define BITMUX 405
+#define DBGAL 406
+#define DBGAH 407
+#define DBGHALT 408
+#define DBG 409
+#define DBGA 410
+#define DBGCMPLX 411
+#define IF 412
+#define COMMA 413
+#define BY 414
+#define COLON 415
+#define SEMICOLON 416
+#define RPAREN 417
+#define LPAREN 418
+#define LBRACK 419
+#define RBRACK 420
+#define STATUS_REG 421
+#define MNOP 422
+#define SYMBOL 423
+#define NUMBER 424
+#define GOT 425
+#define GOT17M4 426
+#define FUNCDESC_GOT17M4 427
+#define AT 428
+#define PLTPC 429
+
+
+
+
+/* Copy the first part of user declarations.  */
+#line 21 "bfin-parse.y"
+
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <obstack.h>
+
+#include "bfin-aux.h"  // opcode generating auxiliaries
+#include "libbfd.h"
+#include "elf/common.h"
+#include "elf/bfin.h"
+
+#define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
+	bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
+
+#define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+	bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+	                   dst, src0, src1, w0)
+
+#define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+	bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+	                    dst, src0, src1, w0)
+
+#define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
+	bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
+
+#define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
+	bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
+
+#define LDIMMHALF_R(reg, h, s, z, hword) \
+	bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
+
+#define LDIMMHALF_R5(reg, h, s, z, hword) \
+        bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
+
+#define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
+	bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
+
+#define LDST(ptr, reg, aop, sz, z, w)  \
+	bfin_gen_ldst (ptr, reg, aop, sz, z, w)
+
+#define LDSTII(ptr, reg, offset, w, op)  \
+	bfin_gen_ldstii (ptr, reg, offset, w, op)
+
+#define DSPLDST(i, m, reg, aop, w) \
+	bfin_gen_dspldst (i, reg, aop, w, m)
+
+#define LDSTPMOD(ptr, reg, idx, aop, w) \
+	bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
+
+#define LDSTIIFP(offset, reg, w)  \
+	bfin_gen_ldstiifp (reg, offset, w)
+
+#define LOGI2OP(dst, src, opc) \
+	bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
+
+#define ALU2OP(dst, src, opc)  \
+	bfin_gen_alu2op (dst, src, opc)
+
+#define BRCC(t, b, offset) \
+	bfin_gen_brcc (t, b, offset)
+
+#define UJUMP(offset) \
+	bfin_gen_ujump (offset)
+
+#define PROGCTRL(prgfunc, poprnd) \
+	bfin_gen_progctrl (prgfunc, poprnd)
+
+#define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
+	bfin_gen_pushpopmultiple (dr, pr, d, p, w)
+
+#define PUSHPOPREG(reg, w) \
+	bfin_gen_pushpopreg (reg, w)
+
+#define CALLA(addr, s)  \
+	bfin_gen_calla (addr, s)
+
+#define LINKAGE(r, framesize) \
+	bfin_gen_linkage (r, framesize)
+
+#define COMPI2OPD(dst, src, op)  \
+	bfin_gen_compi2opd (dst, src, op)
+
+#define COMPI2OPP(dst, src, op)  \
+	bfin_gen_compi2opp (dst, src, op)
+
+#define DAGMODIK(i, op)  \
+	bfin_gen_dagmodik (i, op)
+
+#define DAGMODIM(i, m, op, br)  \
+	bfin_gen_dagmodim (i, m, op, br)
+
+#define COMP3OP(dst, src0, src1, opc)   \
+	bfin_gen_comp3op (src0, src1, dst, opc)
+
+#define PTR2OP(dst, src, opc)   \
+	bfin_gen_ptr2op (dst, src, opc)
+
+#define CCFLAG(x, y, opc, i, g)  \
+	bfin_gen_ccflag (x, y, opc, i, g)
+
+#define CCMV(src, dst, t) \
+	bfin_gen_ccmv (src, dst, t)
+
+#define CACTRL(reg, a, op) \
+	bfin_gen_cactrl (reg, a, op)
+
+#define LOOPSETUP(soffset, c, rop, eoffset, reg) \
+	bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
+
+#define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
+#define IS_RANGE(bits, expr, sign, mul)    \
+	value_match(expr, bits, sign, mul, 1)
+#define IS_URANGE(bits, expr, sign, mul)    \
+	value_match(expr, bits, sign, mul, 0)
+#define IS_CONST(expr) (expr->type == Expr_Node_Constant)
+#define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
+#define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
+#define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
+
+#define IS_PCREL4(expr) \
+	(value_match (expr, 4, 0, 2, 0))
+
+#define IS_LPPCREL10(expr) \
+	(value_match (expr, 10, 0, 2, 0))
+
+#define IS_PCREL10(expr) \
+	(value_match (expr, 10, 0, 2, 1))
+
+#define IS_PCREL12(expr) \
+	(value_match (expr, 12, 0, 2, 1))
+
+#define IS_PCREL24(expr) \
+	(value_match (expr, 24, 0, 2, 1))
+
+
+static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
+
+extern FILE *errorf;
+extern INSTR_T insn;
+
+static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
+static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
+
+static void notethat (char *format, ...);
+
+char *current_inputline;
+extern char *yytext;
+int yyerror (char *msg);
+
+void error (char *format, ...)
+{
+    va_list ap;
+    char buffer[2000];
+    
+    va_start (ap, format);
+    vsprintf (buffer, format, ap);
+    va_end (ap);
+
+    as_bad (buffer);
+}
+
+int
+yyerror (char *msg)
+{
+  if (msg[0] == '\0')
+    error ("%s", msg);
+
+  else if (yytext[0] != ';')
+    error ("%s. Input text was %s.", msg, yytext);
+  else
+    error ("%s.", msg);
+
+  return -1;
+}
+
+static int
+in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
+{
+  int val = EXPR_VALUE (expr);
+  if (expr->type != Expr_Node_Constant)
+    return 0;
+  if (val < from || val > to)
+    return 0;
+  return (val & mask) == 0;
+}
+
+extern int yylex (void);
+
+#define imm3(x) EXPR_VALUE (x)
+#define imm4(x) EXPR_VALUE (x)
+#define uimm4(x) EXPR_VALUE (x)
+#define imm5(x) EXPR_VALUE (x)
+#define uimm5(x) EXPR_VALUE (x)
+#define imm6(x) EXPR_VALUE (x)
+#define imm7(x) EXPR_VALUE (x)
+#define imm16(x) EXPR_VALUE (x)
+#define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
+#define uimm16(x) EXPR_VALUE (x)
+
+/* Return true if a value is inside a range.  */
+#define IN_RANGE(x, low, high) \
+  (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
+
+/* Auxiliary functions.  */
+
+static void
+neg_value (Expr_Node *expr)
+{
+  expr->value.i_value = -expr->value.i_value;
+}
+
+static int
+valid_dreg_pair (Register *reg1, Expr_Node *reg2)
+{
+  if (!IS_DREG (*reg1))
+    {
+      yyerror ("Dregs expected");
+      return 0;
+    }
+
+  if (reg1->regno != 1 && reg1->regno != 3)
+    {
+      yyerror ("Bad register pair");
+      return 0;
+    }
+
+  if (imm7 (reg2) != reg1->regno - 1)
+    {
+      yyerror ("Bad register pair");
+      return 0;
+    }
+
+  reg1->regno--;
+  return 1;
+}
+
+static int
+check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
+{
+  if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
+      || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
+    return yyerror ("Source multiplication register mismatch");
+
+  return 0;
+}
+
+
+/* Check (vector) mac funcs and ops.  */
+
+static int
+check_macfuncs (Macfunc *aa, Opt_mode *opa,
+		Macfunc *ab, Opt_mode *opb)
+{
+  /* Variables for swapping.  */
+  Macfunc mtmp;
+  Opt_mode otmp;
+
+  /* If a0macfunc comes before a1macfunc, swap them.  */
+	
+  if (aa->n == 0)
+    {
+      /*  (M) is not allowed here.  */
+      if (opa->MM != 0)
+	return yyerror ("(M) not allowed with A0MAC");
+      if (ab->n != 1)
+	return yyerror ("Vector AxMACs can't be same");
+
+      mtmp = *aa; *aa = *ab; *ab = mtmp;
+      otmp = *opa; *opa = *opb; *opb = otmp;
+    }
+  else
+    {
+      if (opb->MM != 0)
+	return yyerror ("(M) not allowed with A0MAC");
+      if (opa->mod != 0)
+	return yyerror ("Bad opt mode");
+      if (ab->n != 0)
+	return yyerror ("Vector AxMACs can't be same");
+    }
+
+  /*  If both ops are != 3, we have multiply_halfregs in both
+  assignment_or_macfuncs.  */
+  if (aa->op == ab->op && aa->op != 3)
+    {
+      if (check_multiply_halfregs (aa, ab) < 0)
+	return -1;
+    }
+  else
+    {
+      /*  Only one of the assign_macfuncs has a half reg multiply
+      Evil trick: Just 'OR' their source register codes:
+      We can do that, because we know they were initialized to 0
+      in the rules that don't use multiply_halfregs.  */
+      aa->s0.regno |= (ab->s0.regno & CODE_MASK);
+      aa->s1.regno |= (ab->s1.regno & CODE_MASK);
+    }
+
+  if (aa->w == ab->w  && aa->P != ab->P)
+    {
+      return yyerror ("macfuncs must differ");
+      if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
+	return yyerror ("Destination Dregs must differ by one");
+    }
+  /* We assign to full regs, thus obey even/odd rules.  */
+  else if ((aa->w && aa->P && IS_EVEN (aa->dst)) 
+	   || (ab->w && ab->P && !IS_EVEN (ab->dst)))
+    return yyerror ("Even/Odd register assignment mismatch");
+  /* We assign to half regs, thus obey hi/low rules.  */
+  else if ( (aa->w && !aa->P && !IS_H (aa->dst)) 
+	    || (ab->w && !aa->P && IS_H (ab->dst)))
+    return yyerror ("High/Low register assignment mismatch");
+
+  /* Make sure first macfunc has got both P flags ORed.  */
+  aa->P |= ab->P;
+
+  /* Make sure mod flags get ORed, too.  */
+  opb->mod |= opa->mod;
+  return 0;	
+}
+
+
+static int
+is_group1 (INSTR_T x)
+{
+  /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
+  if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
+    return 1;
+
+  return 0;
+}
+
+static int
+is_group2 (INSTR_T x)
+{
+  if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
+       && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
+       && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
+       && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
+      || (x->value == 0x0000))
+    return 1;
+  return 0;
+}
+
+
+
+/* Enabling traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 366 "bfin-parse.y"
+typedef union YYSTYPE {
+  INSTR_T instr;
+  Expr_Node *expr;
+  SYMBOL_T symbol;
+  long value;
+  Register reg;
+  Macfunc macfunc;
+  struct { int r0; int s0; int x0; int aop; } modcodes;
+  struct { int r0; } r0;
+  Opt_mode mod;
+} YYSTYPE;
+/* Line 196 of yacc.c.  */
+#line 790 "bfin-parse.c"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+/* Copy the second part of user declarations.  */
+
+
+/* Line 219 of yacc.c.  */
+#line 802 "bfin-parse.c"
+
+#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
+# define YYSIZE_T __SIZE_TYPE__
+#endif
+#if ! defined (YYSIZE_T) && defined (size_t)
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T)
+# define YYSIZE_T unsigned int
+#endif
+
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
+
+#if ! defined (yyoverflow) || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols.  */
+
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
+#   else
+#    define YYSTACK_ALLOC alloca
+#    if defined (__STDC__) || defined (__cplusplus)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     define YYINCLUDED_STDLIB_H
+#    endif
+#   endif
+#  endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+   /* Pacify GCC's `empty if-body' warning. */
+#  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
+#  endif
+# else
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
+#  endif
+#  ifdef __cplusplus
+extern "C" {
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifdef __cplusplus
+}
+#  endif
+# endif
+#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
+
+
+#if (! defined (yyoverflow) \
+     && (! defined (__cplusplus) \
+	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member.  */
+union yyalloc
+{
+  short int yyss;
+  YYSTYPE yyvs;
+  };
+
+/* The size of the maximum gap between one aligned stack and the next.  */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+   N elements.  */
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
+      + YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO.  The source and destination do
+   not overlap.  */
+# ifndef YYCOPY
+#  if defined (__GNUC__) && 1 < __GNUC__
+#   define YYCOPY(To, From, Count) \
+      __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+#  else
+#   define YYCOPY(To, From, Count)		\
+      do					\
+	{					\
+	  YYSIZE_T yyi;				\
+	  for (yyi = 0; yyi < (Count); yyi++)	\
+	    (To)[yyi] = (From)[yyi];		\
+	}					\
+      while (0)
+#  endif
+# endif
+
+/* Relocate STACK from its old location to the new one.  The
+   local variables YYSIZE and YYSTACKSIZE give the old and new number of
+   elements in the stack, and YYPTR gives the new location of the
+   stack.  Advance YYPTR to a properly aligned location for the next
+   stack.  */
+# define YYSTACK_RELOCATE(Stack)					\
+    do									\
+      {									\
+	YYSIZE_T yynewbytes;						\
+	YYCOPY (&yyptr->Stack, Stack, yysize);				\
+	Stack = &yyptr->Stack;						\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+	yyptr += yynewbytes / sizeof (*yyptr);				\
+      }									\
+    while (0)
+
+#endif
+
+#if defined (__STDC__) || defined (__cplusplus)
+   typedef signed char yysigned_char;
+#else
+   typedef short int yysigned_char;
+#endif
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL  149
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   1315
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS  175
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS  47
+/* YYNRULES -- Number of rules. */
+#define YYNRULES  349
+/* YYNRULES -- Number of states. */
+#define YYNSTATES  1024
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   429
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const unsigned char yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12,    13,    14,
+      15,    16,    17,    18,    19,    20,    21,    22,    23,    24,
+      25,    26,    27,    28,    29,    30,    31,    32,    33,    34,
+      35,    36,    37,    38,    39,    40,    41,    42,    43,    44,
+      45,    46,    47,    48,    49,    50,    51,    52,    53,    54,
+      55,    56,    57,    58,    59,    60,    61,    62,    63,    64,
+      65,    66,    67,    68,    69,    70,    71,    72,    73,    74,
+      75,    76,    77,    78,    79,    80,    81,    82,    83,    84,
+      85,    86,    87,    88,    89,    90,    91,    92,    93,    94,
+      95,    96,    97,    98,    99,   100,   101,   102,   103,   104,
+     105,   106,   107,   108,   109,   110,   111,   112,   113,   114,
+     115,   116,   117,   118,   119,   120,   121,   122,   123,   124,
+     125,   126,   127,   128,   129,   130,   131,   132,   133,   134,
+     135,   136,   137,   138,   139,   140,   141,   142,   143,   144,
+     145,   146,   147,   148,   149,   150,   151,   152,   153,   154,
+     155,   156,   157,   158,   159,   160,   161,   162,   163,   164,
+     165,   166,   167,   168,   169,   170,   171,   172,   173,   174
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const unsigned short int yyprhs[] =
+{
+       0,     0,     3,     4,     6,     9,    16,    21,    23,    25,
+      28,    34,    36,    43,    50,    54,    58,    76,    94,   106,
+     118,   130,   143,   156,   169,   175,   179,   183,   187,   196,
+     210,   223,   237,   251,   265,   274,   292,   299,   309,   313,
+     320,   324,   330,   337,   346,   355,   358,   361,   366,   370,
+     373,   378,   382,   389,   394,   402,   410,   414,   418,   425,
+     429,   434,   438,   442,   446,   458,   470,   480,   486,   492,
+     502,   508,   514,   521,   528,   534,   540,   546,   553,   560,
+     566,   568,   572,   576,   580,   584,   589,   594,   604,   614,
+     620,   628,   633,   640,   646,   653,   661,   671,   680,   689,
+     701,   711,   716,   722,   729,   737,   744,   749,   756,   762,
+     769,   776,   781,   790,   801,   812,   825,   831,   838,   844,
+     851,   856,   861,   866,   874,   884,   894,   904,   911,   918,
+     925,   934,   943,   950,   956,   962,   971,   976,   984,   986,
+     988,   990,   992,   994,   996,   998,  1000,  1002,  1004,  1007,
+    1010,  1015,  1020,  1027,  1034,  1037,  1040,  1045,  1048,  1051,
+    1054,  1057,  1060,  1063,  1070,  1077,  1083,  1088,  1092,  1096,
+    1100,  1104,  1108,  1112,  1117,  1120,  1125,  1128,  1133,  1136,
+    1141,  1144,  1152,  1161,  1170,  1178,  1186,  1194,  1204,  1212,
+    1221,  1231,  1240,  1247,  1255,  1264,  1274,  1283,  1291,  1299,
+    1306,  1310,  1322,  1330,  1342,  1350,  1354,  1357,  1359,  1367,
+    1377,  1389,  1393,  1399,  1407,  1409,  1412,  1415,  1420,  1422,
+    1429,  1436,  1443,  1445,  1447,  1448,  1454,  1460,  1464,  1468,
+    1472,  1476,  1477,  1479,  1481,  1483,  1485,  1487,  1488,  1492,
+    1493,  1497,  1501,  1502,  1506,  1510,  1516,  1522,  1523,  1527,
+    1531,  1532,  1536,  1540,  1541,  1545,  1549,  1553,  1559,  1565,
+    1566,  1570,  1571,  1575,  1577,  1579,  1581,  1583,  1584,  1588,
+    1592,  1596,  1602,  1608,  1610,  1612,  1614,  1615,  1619,  1620,
+    1624,  1629,  1634,  1636,  1638,  1640,  1642,  1644,  1646,  1648,
+    1650,  1654,  1658,  1662,  1666,  1672,  1678,  1684,  1690,  1694,
+    1698,  1704,  1710,  1711,  1713,  1715,  1718,  1721,  1724,  1728,
+    1730,  1736,  1742,  1746,  1749,  1752,  1755,  1759,  1761,  1763,
+    1765,  1767,  1771,  1775,  1779,  1783,  1785,  1787,  1789,  1791,
+    1795,  1797,  1799,  1803,  1805,  1807,  1811,  1814,  1817,  1819,
+    1823,  1827,  1831,  1835,  1839,  1843,  1847,  1851,  1855,  1859
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+static const short int yyrhs[] =
+{
+     176,     0,    -1,    -1,   177,    -1,   178,   161,    -1,   178,
+      78,   178,    78,   178,   161,    -1,   178,    78,   178,   161,
+      -1,     1,    -1,   167,    -1,   209,   180,    -1,   209,   180,
+     158,   209,   180,    -1,    56,    -1,    26,    98,   163,   208,
+     179,   162,    -1,    36,    98,   163,   208,   179,   162,    -1,
+      33,    98,    36,    -1,    35,    98,    36,    -1,   163,    26,
+     158,    26,   162,    98,     3,   163,    26,   160,   220,   158,
+      26,   160,   220,   162,   193,    -1,   163,    26,   158,    26,
+     162,    98,     4,   163,    26,   160,   220,   158,    26,   160,
+     220,   162,   193,    -1,   163,    26,   158,    26,   162,    98,
+       9,    26,   160,   220,   193,    -1,   163,    26,   158,    26,
+     162,    98,    20,    26,   163,   192,   162,    -1,    26,    98,
+      34,    71,    35,   158,    26,    98,    32,    71,    33,    -1,
+      26,    98,   179,    71,   179,   158,    26,    98,   179,    70,
+     179,   185,    -1,    26,    98,    26,   202,    26,   158,    26,
+      98,    26,   202,    26,   185,    -1,    26,    98,    26,   201,
+      26,   158,    26,    98,    26,   201,    26,   186,    -1,    26,
+      98,    77,    26,   190,    -1,   206,    77,   179,    -1,    32,
+      98,    36,    -1,    34,    98,    36,    -1,    26,    98,   195,
+     163,    26,   158,    26,   162,    -1,    26,    98,     5,   163,
+      26,   160,   220,   158,    26,   160,   220,   162,   194,    -1,
+      26,    98,     5,   163,    26,   160,   220,   158,    26,   160,
+     220,   162,    -1,    26,    98,     6,   163,    26,   160,   220,
+     158,    26,   160,   220,   162,   203,    -1,    26,    98,     7,
+     163,    26,   160,   220,   158,    26,   160,   220,   162,   203,
+      -1,    26,    98,     8,   163,    26,   160,   220,   158,    26,
+     160,   220,   162,   204,    -1,    26,    98,    10,   163,    26,
+     158,    26,   162,    -1,    36,    98,    36,    98,    22,   163,
+      36,   162,    72,    36,    71,    22,   163,    36,   162,    72,
+      36,    -1,    26,    98,    26,   202,    26,   185,    -1,    26,
+      98,   200,   163,    26,   158,    26,   162,   190,    -1,   206,
+      70,   179,    -1,    36,    98,    36,   202,    36,   185,    -1,
+     206,   206,   220,    -1,   206,   179,   163,   126,   162,    -1,
+      36,    98,    26,   163,   138,   162,    -1,    36,    98,    26,
+     202,    26,   163,   141,   162,    -1,    36,    98,    26,   202,
+      26,   163,   142,   162,    -1,   206,   179,    -1,   206,    26,
+      -1,    26,    98,    36,   187,    -1,    36,    98,   220,    -1,
+     206,   220,    -1,    26,    98,   220,   188,    -1,    36,    98,
+      26,    -1,    26,    98,    26,   201,    26,   184,    -1,    26,
+      98,    29,   187,    -1,   206,    77,   179,   158,   206,    77,
+     179,    -1,   206,    70,   179,   158,   206,    70,   179,    -1,
+     207,   179,   196,    -1,    26,   103,   220,    -1,    26,   104,
+      26,   163,   132,   162,    -1,    26,   103,    26,    -1,   179,
+     104,   179,   196,    -1,    26,   104,    26,    -1,    26,   104,
+     220,    -1,    26,    99,    26,    -1,    12,   163,    26,   160,
+     220,   158,    26,   160,   220,   162,   193,    -1,   206,   179,
+     163,   126,   162,   158,   206,   179,   163,   126,   162,    -1,
+      26,    98,   163,    26,    71,    26,   162,    91,   220,    -1,
+      26,    98,    26,    66,    26,    -1,    26,    98,    26,    68,
+      26,    -1,    26,    98,    26,    71,   163,    26,    91,   220,
+     162,    -1,    28,    98,   179,   107,   179,    -1,    28,    98,
+     179,   112,   179,    -1,    28,    98,    26,   112,    26,   197,
+      -1,    28,    98,    26,   112,   220,   197,    -1,    28,    98,
+      26,   107,    26,    -1,    28,    98,    26,   107,   220,    -1,
+      28,    98,   179,   106,   179,    -1,    28,    98,    26,   106,
+      26,   197,    -1,    28,    98,    26,   106,   220,   197,    -1,
+      26,    98,    26,    65,    26,    -1,   213,    -1,    26,    98,
+      26,    -1,    28,    98,    26,    -1,    26,    98,    28,    -1,
+      28,   105,    28,    -1,    36,    98,   211,   180,    -1,    26,
+      98,   211,   180,    -1,    36,    98,   211,   180,   158,    36,
+      98,   211,   180,    -1,    26,    98,   211,   180,   158,    26,
+      98,   211,   180,    -1,   206,    87,   179,   159,    36,    -1,
+      36,    98,    87,    36,   159,    36,   191,    -1,   206,   179,
+      91,   220,    -1,    26,    98,    26,    91,   220,   189,    -1,
+      36,    98,    36,    91,   220,    -1,    36,    98,    36,    91,
+     220,   191,    -1,    26,    98,    87,    26,   159,    36,   189,
+      -1,    36,    98,    19,   163,    26,   158,    36,   162,   190,
+      -1,    36,    98,    19,   163,    36,   158,    36,   162,    -1,
+      26,    98,    18,   163,    26,   158,    26,   162,    -1,    26,
+      98,    18,   163,    26,   158,    26,   162,   163,   133,   162,
+      -1,    26,    98,    17,   163,    26,   158,    36,   162,   187,
+      -1,   206,   179,    93,   220,    -1,   206,    86,   179,   159,
+      36,    -1,    36,    98,    86,    36,   159,    36,    -1,    26,
+      98,    86,    26,   159,    36,   190,    -1,    26,    98,    85,
+      26,   159,    36,    -1,   206,   179,    92,   220,    -1,    26,
+      98,    26,    92,   220,   190,    -1,    36,    98,    36,    92,
+     220,    -1,    36,    98,    36,    93,   220,   191,    -1,    26,
+      98,    26,    93,   220,   189,    -1,    36,    98,    21,    26,
+      -1,    26,    98,    11,   163,    36,   158,    36,   162,    -1,
+      36,    98,    28,    98,    88,   163,   179,   158,    26,   162,
+      -1,    36,    98,    28,    98,    69,   163,   179,   158,    26,
+     162,    -1,    36,    98,    28,    98,    69,   163,   179,   158,
+     179,   158,    28,   162,    -1,   206,    90,   179,   159,    36,
+      -1,    26,    98,    90,    26,   159,    36,    -1,   206,    90,
+     179,   159,   220,    -1,    26,    98,    90,    26,   159,   220,
+      -1,    36,    98,    23,   179,    -1,    36,    98,    23,    26,
+      -1,    36,    98,    23,    36,    -1,    36,    98,    16,   163,
+      26,   162,   181,    -1,    26,    98,    16,   163,    26,   158,
+      26,   162,   181,    -1,   150,   163,    26,   158,    26,   158,
+     179,   162,   181,    -1,   206,    88,   163,   179,   158,   179,
+     158,    28,   162,    -1,   147,   163,    26,   158,   220,   162,
+      -1,   148,   163,    26,   158,   220,   162,    -1,   146,   163,
+      26,   158,   220,   162,    -1,    28,   105,   149,   163,    26,
+     158,   220,   162,    -1,    28,    98,   149,   163,    26,   158,
+     220,   162,    -1,   157,    64,    28,    26,    98,    26,    -1,
+     157,    28,    26,    98,    26,    -1,   157,    64,    28,    57,
+     220,    -1,   157,    64,    28,    57,   220,   163,   131,   162,
+      -1,   157,    28,    57,   220,    -1,   157,    28,    57,   220,
+     163,   131,   162,    -1,    37,    -1,    39,    -1,    38,    -1,
+      40,    -1,    41,    -1,    42,    -1,    44,    -1,    47,    -1,
+      48,    -1,    49,    -1,    46,    26,    -1,    45,    26,    -1,
+      57,   163,    26,   162,    -1,    60,   163,    26,   162,    -1,
+      60,   163,    27,    71,    26,   162,    -1,    57,   163,    27,
+      71,    26,   162,    -1,    50,   220,    -1,    51,   220,    -1,
+     120,   163,    26,   162,    -1,    57,   220,    -1,    58,   220,
+      -1,    59,   220,    -1,    59,   218,    -1,    60,   220,    -1,
+      60,   218,    -1,    97,   163,    26,   158,    26,   162,    -1,
+      96,   163,    26,   158,    26,   162,    -1,    26,    98,    70,
+      26,   189,    -1,    26,    98,    63,    26,    -1,    26,    95,
+      26,    -1,    26,    95,   220,    -1,    26,    89,    26,    -1,
+      26,    94,    26,    -1,    26,    94,   220,    -1,    26,    89,
+     220,    -1,   114,   164,    26,   165,    -1,   114,   199,    -1,
+     113,   164,    26,   165,    -1,   113,   199,    -1,   115,   164,
+      26,   165,    -1,   115,   199,    -1,   116,   164,    26,   165,
+      -1,   116,   199,    -1,   123,   164,    26,   205,   165,    98,
+      26,    -1,   123,   164,    26,   202,   220,   165,    98,    26,
+      -1,   124,   164,    26,   202,   220,   165,    98,    26,    -1,
+     124,   164,    26,   205,   165,    98,    26,    -1,   124,   164,
+      26,   205,   165,    98,    36,    -1,   164,    26,   202,   220,
+     165,    98,    26,    -1,    26,    98,   124,   164,    26,   202,
+     220,   165,   187,    -1,    36,    98,   124,   164,    26,   205,
+     165,    -1,    26,    98,   124,   164,    26,   205,   165,   187,
+      -1,    26,    98,   124,   164,    26,    84,    26,   165,   187,
+      -1,    36,    98,   124,   164,    26,    84,    26,   165,    -1,
+     164,    26,   205,   165,    98,    26,    -1,   164,    26,    84,
+      26,   165,    98,    26,    -1,   124,   164,    26,    84,    26,
+     165,    98,    36,    -1,    26,    98,   123,   164,    26,   202,
+     220,   165,   187,    -1,    26,    98,   123,   164,    26,   205,
+     165,   187,    -1,    26,    98,   164,    26,    84,    26,   165,
+      -1,    26,    98,   164,    26,   202,   217,   165,    -1,    26,
+      98,   164,    26,   205,   165,    -1,   220,    98,   220,    -1,
+     198,    98,   163,    26,   160,   220,   158,    26,   160,   220,
+     162,    -1,   198,    98,   163,    26,   160,   220,   162,    -1,
+     163,    26,   160,   220,   158,    26,   160,   220,   162,    98,
+     199,    -1,   163,    26,   160,   220,   162,    98,   199,    -1,
+     198,    98,    26,    -1,    24,   220,    -1,    25,    -1,    52,
+     163,   220,   158,   220,   162,    26,    -1,    52,   163,   220,
+     158,   220,   162,    26,    98,    26,    -1,    52,   163,   220,
+     158,   220,   162,    26,    98,    26,    92,   220,    -1,    53,
+     220,    26,    -1,    53,   220,    26,    98,    26,    -1,    53,
+     220,    26,    98,    26,    92,   220,    -1,   154,    -1,   154,
+     179,    -1,   154,    26,    -1,   156,   163,    26,   162,    -1,
+     153,    -1,   155,   163,    36,   158,   220,   162,    -1,   152,
+     163,    26,   158,   220,   162,    -1,   151,   163,    26,   158,
+     220,   162,    -1,    30,    -1,    31,    -1,    -1,   163,   135,
+     158,   136,   162,    -1,   163,   136,   158,   135,   162,    -1,
+     163,   136,   162,    -1,   163,   135,   162,    -1,   163,   121,
+     162,    -1,   163,   122,   162,    -1,    -1,   126,    -1,   127,
+      -1,   128,    -1,   121,    -1,   122,    -1,    -1,   163,   182,
+     162,    -1,    -1,   163,   125,   162,    -1,   163,   126,   162,
+      -1,    -1,   163,   183,   162,    -1,   163,   182,   162,    -1,
+     163,   183,   158,   182,   162,    -1,   163,   182,   158,   183,
+     162,    -1,    -1,   163,   134,   162,    -1,   163,   133,   162,
+      -1,    -1,   163,   133,   162,    -1,   163,   134,   162,    -1,
+      -1,   163,   125,   162,    -1,   163,   126,   162,    -1,   163,
+     143,   162,    -1,   163,   143,   158,   126,   162,    -1,   163,
+     126,   158,   143,   162,    -1,    -1,   163,   143,   162,    -1,
+      -1,   163,   126,   162,    -1,   108,    -1,   111,    -1,   110,
+      -1,   109,    -1,    -1,   163,   137,   162,    -1,   163,   137,
+     162,    -1,   163,   136,   162,    -1,   163,   136,   158,   137,
+     162,    -1,   163,   137,   158,   136,   162,    -1,    13,    -1,
+      14,    -1,    15,    -1,    -1,   163,   136,   162,    -1,    -1,
+     163,   136,   162,    -1,   164,    83,    26,   165,    -1,   164,
+      26,    84,   165,    -1,    75,    -1,    76,    -1,    79,    -1,
+      80,    -1,    81,    -1,    82,    -1,    71,    -1,    70,    -1,
+     163,   140,   162,    -1,   163,   129,   162,    -1,   163,   139,
+     162,    -1,   163,   130,   162,    -1,   163,   140,   158,   137,
+     162,    -1,   163,   129,   158,   137,   162,    -1,   163,   139,
+     158,   137,   162,    -1,   163,   130,   158,   137,   162,    -1,
+     163,   144,   162,    -1,   163,   145,   162,    -1,   163,   144,
+     158,   137,   162,    -1,   163,   145,   158,   137,   162,    -1,
+      -1,    84,    -1,    83,    -1,   179,    98,    -1,   179,   103,
+      -1,   179,   104,    -1,    26,    98,   179,    -1,   210,    -1,
+      26,    98,   163,   210,   162,    -1,    36,    98,   163,   210,
+     162,    -1,    36,    98,   179,    -1,   206,   211,    -1,   208,
+     211,    -1,   207,   211,    -1,    36,    72,    36,    -1,    98,
+      -1,   100,    -1,   102,    -1,   101,    -1,    28,   212,   166,
+      -1,    28,   212,   143,    -1,   166,   212,    28,    -1,   143,
+     212,    28,    -1,   168,    -1,   170,    -1,   171,    -1,   172,
+      -1,   214,   173,   215,    -1,   216,    -1,   220,    -1,   214,
+     173,   174,    -1,   169,    -1,   214,    -1,   163,   221,   162,
+      -1,    63,   221,    -1,    70,   221,    -1,   221,    -1,   221,
+      72,   221,    -1,   221,    73,   221,    -1,   221,    67,   221,
+      -1,   221,    71,   221,    -1,   221,    70,   221,    -1,   221,
+      91,   221,    -1,   221,    92,   221,    -1,   221,    65,   221,
+      -1,   221,    68,   221,    -1,   221,    66,   221,    -1,   219,
+      -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const unsigned short int yyrline[] =
+{
+       0,   567,   567,   568,   580,   582,   615,   642,   653,   657,
+     692,   712,   717,   727,   737,   742,   747,   763,   779,   791,
+     801,   814,   833,   851,   874,   896,   901,   911,   922,   933,
+     947,   962,   978,   994,  1010,  1021,  1035,  1061,  1079,  1084,
+    1090,  1102,  1113,  1124,  1135,  1146,  1157,  1168,  1194,  1208,
+    1218,  1263,  1282,  1293,  1304,  1315,  1326,  1337,  1353,  1370,
+    1386,  1397,  1408,  1439,  1450,  1463,  1474,  1513,  1523,  1533,
+    1553,  1563,  1573,  1583,  1594,  1602,  1612,  1622,  1633,  1657,
+    1668,  1674,  1685,  1696,  1707,  1715,  1736,  1761,  1788,  1822,
+    1836,  1847,  1861,  1895,  1905,  1915,  1940,  1952,  1970,  1981,
+    1992,  2003,  2016,  2027,  2038,  2049,  2060,  2071,  2104,  2114,
+    2127,  2147,  2158,  2169,  2182,  2195,  2206,  2217,  2228,  2239,
+    2249,  2260,  2271,  2283,  2294,  2305,  2316,  2329,  2341,  2353,
+    2364,  2375,  2386,  2398,  2410,  2421,  2432,  2443,  2453,  2459,
+    2465,  2471,  2477,  2483,  2489,  2495,  2501,  2507,  2513,  2524,
+    2535,  2546,  2557,  2568,  2579,  2590,  2596,  2607,  2618,  2629,
+    2640,  2651,  2661,  2674,  2682,  2690,  2714,  2725,  2736,  2747,
+    2758,  2769,  2781,  2794,  2803,  2814,  2825,  2837,  2848,  2859,
+    2870,  2884,  2896,  2911,  2930,  2941,  2959,  2993,  3011,  3028,
+    3039,  3050,  3061,  3082,  3101,  3114,  3128,  3140,  3156,  3196,
+    3229,  3237,  3253,  3272,  3286,  3305,  3321,  3329,  3338,  3349,
+    3361,  3375,  3383,  3393,  3405,  3410,  3415,  3421,  3429,  3435,
+    3441,  3447,  3460,  3464,  3474,  3478,  3483,  3488,  3493,  3500,
+    3504,  3511,  3515,  3520,  3525,  3533,  3537,  3544,  3548,  3556,
+    3561,  3567,  3576,  3581,  3587,  3593,  3599,  3608,  3611,  3615,
+    3622,  3625,  3629,  3636,  3641,  3647,  3653,  3659,  3664,  3672,
+    3675,  3682,  3685,  3692,  3696,  3700,  3704,  3711,  3714,  3721,
+    3726,  3733,  3740,  3752,  3756,  3760,  3767,  3770,  3780,  3783,
+    3792,  3798,  3807,  3811,  3818,  3822,  3826,  3830,  3837,  3841,
+    3848,  3856,  3864,  3872,  3880,  3887,  3894,  3902,  3912,  3917,
+    3922,  3927,  3935,  3938,  3942,  3951,  3958,  3965,  3972,  3987,
+    3993,  4001,  4009,  4027,  4034,  4041,  4051,  4064,  4068,  4072,
+    4076,  4083,  4089,  4095,  4101,  4111,  4120,  4122,  4124,  4128,
+    4136,  4140,  4147,  4153,  4159,  4163,  4167,  4171,  4177,  4183,
+    4187,  4191,  4195,  4199,  4203,  4207,  4211,  4215,  4219,  4223
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "BYTEOP16P", "BYTEOP16M", "BYTEOP1P",
+  "BYTEOP2P", "BYTEOP2M", "BYTEOP3P", "BYTEUNPACK", "BYTEPACK", "PACK",
+  "SAA", "ALIGN8", "ALIGN16", "ALIGN24", "VIT_MAX", "EXTRACT", "DEPOSIT",
+  "EXPADJ", "SEARCH", "ONES", "SIGN", "SIGNBITS", "LINK", "UNLINK", "REG",
+  "PC", "CCREG", "BYTE_DREG", "REG_A_DOUBLE_ZERO", "REG_A_DOUBLE_ONE",
+  "A_ZERO_DOT_L", "A_ZERO_DOT_H", "A_ONE_DOT_L", "A_ONE_DOT_H", "HALF_REG",
+  "NOP", "RTI", "RTS", "RTX", "RTN", "RTE", "HLT", "IDLE", "STI", "CLI",
+  "CSYNC", "SSYNC", "EMUEXCPT", "RAISE", "EXCPT", "LSETUP", "LOOP",
+  "LOOP_BEGIN", "LOOP_END", "DISALGNEXCPT", "JUMP", "JUMP_DOT_S",
+  "JUMP_DOT_L", "CALL", "ABORT", "NOT", "TILDA", "BANG", "AMPERSAND",
+  "BAR", "PERCENT", "CARET", "BXOR", "MINUS", "PLUS", "STAR", "SLASH",
+  "NEG", "MIN", "MAX", "ABS", "DOUBLE_BAR", "_PLUS_BAR_PLUS",
+  "_PLUS_BAR_MINUS", "_MINUS_BAR_PLUS", "_MINUS_BAR_MINUS", "_MINUS_MINUS",
+  "_PLUS_PLUS", "SHIFT", "LSHIFT", "ASHIFT", "BXORSHIFT",
+  "_GREATER_GREATER_GREATER_THAN_ASSIGN", "ROT", "LESS_LESS",
+  "GREATER_GREATER", "_GREATER_GREATER_GREATER", "_LESS_LESS_ASSIGN",
+  "_GREATER_GREATER_ASSIGN", "DIVS", "DIVQ", "ASSIGN", "_STAR_ASSIGN",
+  "_BAR_ASSIGN", "_CARET_ASSIGN", "_AMPERSAND_ASSIGN", "_MINUS_ASSIGN",
+  "_PLUS_ASSIGN", "_ASSIGN_BANG", "_LESS_THAN_ASSIGN", "_ASSIGN_ASSIGN",
+  "GE", "LT", "LE", "GT", "LESS_THAN", "FLUSHINV", "FLUSH", "IFLUSH",
+  "PREFETCH", "PRNT", "OUTC", "WHATREG", "TESTSET", "ASL", "ASR", "B", "W",
+  "NS", "S", "CO", "SCO", "TH", "TL", "BP", "BREV", "X", "Z", "M", "MMOD",
+  "R", "RND", "RNDL", "RNDH", "RND12", "RND20", "V", "LO", "HI", "BITTGL",
+  "BITCLR", "BITSET", "BITTST", "BITMUX", "DBGAL", "DBGAH", "DBGHALT",
+  "DBG", "DBGA", "DBGCMPLX", "IF", "COMMA", "BY", "COLON", "SEMICOLON",
+  "RPAREN", "LPAREN", "LBRACK", "RBRACK", "STATUS_REG", "MNOP", "SYMBOL",
+  "NUMBER", "GOT", "GOT17M4", "FUNCDESC_GOT17M4", "AT", "PLTPC", "$accept",
+  "statement", "asm", "asm_1", "REG_A", "opt_mode", "asr_asl", "sco",
+  "asr_asl_0", "amod0", "amod1", "amod2", "xpmod", "xpmod1", "vsmod",
+  "vmod", "smod", "searchmod", "aligndir", "byteop_mod", "c_align",
+  "w32_or_nothing", "iu_or_nothing", "reg_with_predec", "reg_with_postinc",
+  "min_max", "op_bar_op", "plus_minus", "rnd_op", "b3_op", "post_op",
+  "a_assign", "a_minusassign", "a_plusassign", "assign_macfunc",
+  "a_macfunc", "multiply_halfregs", "cc_op", "ccstat", "symbol",
+  "any_gotrel", "got", "got_or_expr", "pltpc", "eterm", "expr", "expr_1", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const unsigned short int yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,   268,   269,   270,   271,   272,   273,   274,
+     275,   276,   277,   278,   279,   280,   281,   282,   283,   284,
+     285,   286,   287,   288,   289,   290,   291,   292,   293,   294,
+     295,   296,   297,   298,   299,   300,   301,   302,   303,   304,
+     305,   306,   307,   308,   309,   310,   311,   312,   313,   314,
+     315,   316,   317,   318,   319,   320,   321,   322,   323,   324,
+     325,   326,   327,   328,   329,   330,   331,   332,   333,   334,
+     335,   336,   337,   338,   339,   340,   341,   342,   343,   344,
+     345,   346,   347,   348,   349,   350,   351,   352,   353,   354,
+     355,   356,   357,   358,   359,   360,   361,   362,   363,   364,
+     365,   366,   367,   368,   369,   370,   371,   372,   373,   374,
+     375,   376,   377,   378,   379,   380,   381,   382,   383,   384,
+     385,   386,   387,   388,   389,   390,   391,   392,   393,   394,
+     395,   396,   397,   398,   399,   400,   401,   402,   403,   404,
+     405,   406,   407,   408,   409,   410,   411,   412,   413,   414,
+     415,   416,   417,   418,   419,   420,   421,   422,   423,   424,
+     425,   426,   427,   428,   429
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const unsigned char yyr1[] =
+{
+       0,   175,   176,   176,   177,   177,   177,   177,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   178,   178,   178,   178,   178,   178,   178,   178,
+     178,   178,   179,   179,   180,   180,   180,   180,   180,   181,
+     181,   182,   182,   182,   182,   183,   183,   184,   184,   185,
+     185,   185,   186,   186,   186,   186,   186,   187,   187,   187,
+     188,   188,   188,   189,   189,   189,   189,   189,   189,   190,
+     190,   191,   191,   192,   192,   192,   192,   193,   193,   194,
+     194,   194,   194,   195,   195,   195,   196,   196,   197,   197,
+     198,   199,   200,   200,   201,   201,   201,   201,   202,   202,
+     203,   203,   203,   203,   203,   203,   203,   203,   204,   204,
+     204,   204,   205,   205,   205,   206,   207,   208,   209,   209,
+     209,   209,   209,   210,   210,   210,   211,   212,   212,   212,
+     212,   213,   213,   213,   213,   214,   215,   215,   215,   216,
+     217,   217,   218,   219,   219,   219,   219,   219,   220,   221,
+     221,   221,   221,   221,   221,   221,   221,   221,   221,   221
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const unsigned char yyr2[] =
+{
+       0,     2,     0,     1,     2,     6,     4,     1,     1,     2,
+       5,     1,     6,     6,     3,     3,    17,    17,    11,    11,
+      11,    12,    12,    12,     5,     3,     3,     3,     8,    13,
+      12,    13,    13,    13,     8,    17,     6,     9,     3,     6,
+       3,     5,     6,     8,     8,     2,     2,     4,     3,     2,
+       4,     3,     6,     4,     7,     7,     3,     3,     6,     3,
+       4,     3,     3,     3,    11,    11,     9,     5,     5,     9,
+       5,     5,     6,     6,     5,     5,     5,     6,     6,     5,
+       1,     3,     3,     3,     3,     4,     4,     9,     9,     5,
+       7,     4,     6,     5,     6,     7,     9,     8,     8,    11,
+       9,     4,     5,     6,     7,     6,     4,     6,     5,     6,
+       6,     4,     8,    10,    10,    12,     5,     6,     5,     6,
+       4,     4,     4,     7,     9,     9,     9,     6,     6,     6,
+       8,     8,     6,     5,     5,     8,     4,     7,     1,     1,
+       1,     1,     1,     1,     1,     1,     1,     1,     2,     2,
+       4,     4,     6,     6,     2,     2,     4,     2,     2,     2,
+       2,     2,     2,     6,     6,     5,     4,     3,     3,     3,
+       3,     3,     3,     4,     2,     4,     2,     4,     2,     4,
+       2,     7,     8,     8,     7,     7,     7,     9,     7,     8,
+       9,     8,     6,     7,     8,     9,     8,     7,     7,     6,
+       3,    11,     7,    11,     7,     3,     2,     1,     7,     9,
+      11,     3,     5,     7,     1,     2,     2,     4,     1,     6,
+       6,     6,     1,     1,     0,     5,     5,     3,     3,     3,
+       3,     0,     1,     1,     1,     1,     1,     0,     3,     0,
+       3,     3,     0,     3,     3,     5,     5,     0,     3,     3,
+       0,     3,     3,     0,     3,     3,     3,     5,     5,     0,
+       3,     0,     3,     1,     1,     1,     1,     0,     3,     3,
+       3,     5,     5,     1,     1,     1,     0,     3,     0,     3,
+       4,     4,     1,     1,     1,     1,     1,     1,     1,     1,
+       3,     3,     3,     3,     5,     5,     5,     5,     3,     3,
+       5,     5,     0,     1,     1,     2,     2,     2,     3,     1,
+       5,     5,     3,     2,     2,     2,     3,     1,     1,     1,
+       1,     3,     3,     3,     3,     1,     1,     1,     1,     3,
+       1,     1,     3,     1,     1,     3,     2,     2,     1,     3,
+       3,     3,     3,     3,     3,     3,     3,     3,     3,     1
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const unsigned short int yydefact[] =
+{
+       0,     7,     0,     0,   207,     0,     0,   222,   223,     0,
+       0,     0,     0,     0,   138,   140,   139,   141,   142,   143,
+     144,     0,     0,   145,   146,   147,     0,     0,     0,     0,
+      11,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,   218,   214,     0,     0,     0,     0,     0,
+       0,     8,   325,   333,     0,     3,     0,     0,     0,     0,
+       0,     0,   224,   309,    80,   334,   349,     0,   338,     0,
+       0,   206,     0,     0,     0,     0,     0,     0,     0,   317,
+     318,   320,   319,     0,     0,     0,     0,     0,     0,     0,
+     149,   148,   154,   155,     0,     0,     0,   157,   158,   334,
+     160,   159,     0,   162,   161,   336,   337,     0,     0,     0,
+     176,     0,   174,     0,   178,     0,   180,     0,     0,     0,
+     317,     0,     0,     0,     0,     0,     0,     0,   216,   215,
+       0,     0,     0,     0,     0,     0,   302,     0,     0,     1,
+       0,     4,   305,   306,   307,     0,    46,     0,     0,     0,
+       0,     0,     0,     0,    45,     0,   313,    49,   276,   315,
+     314,     0,     9,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,   169,   172,   170,   171,   167,
+     168,     0,     0,     0,     0,     0,     0,   273,   274,   275,
+       0,     0,     0,    81,    83,   247,     0,   247,     0,     0,
+     282,   283,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,   308,     0,     0,   224,   250,    63,    59,    57,    61,
+      62,    82,     0,     0,    84,     0,   322,   321,    26,    14,
+      27,    15,     0,     0,     0,     0,    51,     0,     0,     0,
+       0,     0,     0,   312,   224,    48,     0,   211,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+     302,   302,   324,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,   335,   289,   288,   304,
+     303,     0,     0,     0,   323,     0,   276,   205,     0,     0,
+      38,    25,     0,     0,     0,     0,     0,     0,     0,     0,
+      40,     0,    56,     0,     0,     0,   200,   346,   348,   341,
+     347,   343,   342,   339,   340,   344,   345,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+     288,   284,   285,   286,   287,     0,     0,     0,     0,     0,
+       0,    53,     0,    47,   166,   253,   259,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,   302,
+       0,     0,     0,    86,     0,    50,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,   111,   121,   122,
+     120,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,    85,     0,     0,   150,     0,   332,
+     151,     0,     0,     0,     0,   175,   173,   177,   179,   156,
+     303,     0,     0,   303,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,   217,     0,   136,     0,     0,     0,     0,
+       0,     0,     0,   280,     0,     6,    60,     0,   316,     0,
+       0,     0,     0,     0,     0,    91,   106,   101,     0,     0,
+       0,   228,     0,   227,     0,     0,   224,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,    79,    67,    68,
+       0,   253,   259,   253,   237,   239,     0,     0,     0,     0,
+     165,     0,    24,     0,     0,     0,     0,   302,   302,     0,
+     307,     0,   310,   303,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,   278,   278,    74,    75,   278,   278,     0,
+      76,    70,    71,     0,     0,     0,     0,     0,     0,     0,
+       0,    93,   108,   261,     0,   239,     0,     0,   302,     0,
+     311,     0,     0,   212,     0,     0,     0,     0,   281,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,   133,     0,     0,   134,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,   102,    89,     0,   116,
+     118,    41,   277,     0,     0,     0,     0,    10,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,    92,
+     107,   110,     0,   231,    52,     0,     0,    36,   249,   248,
+       0,     0,     0,     0,     0,   105,   259,   253,   117,   119,
+       0,     0,   303,     0,     0,     0,    12,     0,   334,   330,
+       0,   331,   199,     0,     0,     0,     0,   251,   252,    58,
+       0,    77,    78,    72,    73,     0,     0,     0,     0,     0,
+      42,     0,     0,     0,     0,    94,   109,     0,    39,   103,
+     261,   303,     0,    13,     0,     0,     0,   153,   152,   164,
+     163,     0,     0,     0,     0,     0,   129,   127,   128,     0,
+     221,   220,   219,     0,   132,     0,     0,     0,     0,     0,
+       0,   192,     5,     0,     0,     0,     0,     0,   225,   226,
+       0,   308,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,   232,   233,   234,     0,     0,
+       0,     0,     0,   254,     0,   255,     0,   256,   260,   104,
+      95,     0,   247,     0,     0,   247,     0,   197,     0,   198,
+       0,     0,     0,     0,     0,     0,     0,     0,   123,     0,
+       0,     0,     0,     0,     0,     0,     0,    90,     0,   188,
+       0,   208,   213,     0,   181,     0,     0,   184,   185,     0,
+     137,     0,     0,     0,     0,     0,     0,     0,   204,   193,
+     186,     0,   202,    55,    54,     0,     0,     0,     0,     0,
+       0,     0,    34,   112,     0,   247,    98,     0,     0,   238,
+       0,   240,   241,     0,     0,     0,   247,   196,   247,   247,
+     189,     0,   326,   327,   328,   329,     0,    28,   259,   224,
+     279,   131,   130,     0,     0,   259,    97,    43,    44,     0,
+       0,   262,     0,   191,   224,     0,   182,   194,   183,     0,
+     135,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,   124,   100,     0,    69,     0,
+       0,     0,   258,   257,   195,   190,   187,    66,     0,    37,
+      88,   229,   230,    96,     0,     0,     0,     0,    87,   209,
+     125,     0,     0,     0,     0,     0,     0,   126,     0,   267,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,   114,
+       0,   113,     0,     0,     0,     0,   267,   263,   266,   265,
+     264,     0,     0,     0,     0,     0,    64,     0,     0,     0,
+       0,    99,   242,   239,    20,   239,     0,     0,   210,     0,
+       0,    18,    19,   203,   201,    65,     0,    30,     0,     0,
+       0,   231,    23,    22,    21,   115,     0,     0,     0,   268,
+       0,    29,     0,    31,    32,     0,    33,   235,   236,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
+       0,     0,     0,   244,   231,   243,     0,     0,     0,     0,
+     270,     0,   269,     0,   291,     0,   293,     0,   292,     0,
+     290,     0,   298,     0,   299,     0,     0,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,   246,   245,
+       0,   267,   267,   271,   272,   295,   297,   296,   294,   300,
+     301,    35,    16,    17
+};
+
+/* YYDEFGOTO[NTERM-NUM]. */
+static const short int yydefgoto[] =
+{
+      -1,    64,    65,    66,   364,   172,   748,   718,   960,   604,
+     607,   942,   351,   375,   490,   492,   655,   911,   916,   951,
+     222,   312,   641,    68,   120,   223,   348,   291,   953,   956,
+     292,   365,   366,    71,    72,    73,   170,    94,    74,    75,
+     815,   629,   630,   110,    76,    77,    78
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -903
+static const short int yypact[] =
+{
+     697,  -903,   -94,   277,  -903,   676,   315,  -903,  -903,    23,
+      32,    41,    58,    65,  -903,  -903,  -903,  -903,  -903,  -903,
+    -903,   121,   158,  -903,  -903,  -903,   277,   277,    29,   277,
+    -903,   318,   277,   277,   320,   277,   277,    94,   100,    64,
+     104,   108,   131,   137,   152,   165,   376,   160,   171,   176,
+     182,   219,   238,  -903,   566,   244,   251,    79,    96,    44,
+     376,  -903,  -903,  -903,   350,  -903,   -57,   187,   337,    63,
+     245,   394,   278,  -903,  -903,  -903,  -903,   349,   563,   436,
+     277,  -903,   146,   159,   167,   489,   438,   186,   188,    37,
+    -903,  -903,  -903,    15,  -118,   446,   462,   480,   485,    28,
+    -903,  -903,  -903,  -903,   277,   513,    50,  -903,  -903,   353,
+    -903,  -903,    85,  -903,  -903,  -903,  -903,   521,   534,   537,
+    -903,   542,  -903,   567,  -903,   575,  -903,   578,   583,   585,
+    -903,   619,   590,   598,   630,   651,   656,   680,  -903,  -903,
+     677,   693,    62,   692,   204,   470,   200,   698,   712,  -903,
+     886,  -903,  -903,  -903,   180,    -6,  -903,   419,   302,   180,
+     180,   180,   589,   180,    97,   277,  -903,  -903,   595,  -903,
+    -903,   297,   568,   277,   277,   277,   277,   277,   277,   277,
+     277,   277,   277,   277,   591,  -903,  -903,  -903,  -903,  -903,
+    -903,   599,   600,   601,   603,   605,   606,  -903,  -903,  -903,
+     609,   613,   614,   580,  -903,   615,   688,   -38,   210,   226,
+    -903,  -903,   735,   755,   756,   757,   759,   622,   623,    98,
+     762,   718,   627,   628,   278,   629,  -903,  -903,  -903,   632,
+    -903,   205,   633,   332,  -903,   634,  -903,  -903,  -903,  -903,
+    -903,  -903,   635,   636,   774,   449,   -25,   703,   227,   766,
+     768,   641,   302,  -903,   278,  -903,   648,   709,   647,   743,
+     642,   653,   747,   661,   664,   -62,   -31,   -19,    16,   662,
+     326,   372,  -903,   665,   667,   668,   669,   670,   671,   672,
+     673,   733,   277,    84,   806,   277,  -903,  -903,  -903,  -903,
+     808,   277,   674,   690,  -903,   -16,   595,  -903,   810,   801,
+     683,   684,   679,   699,   180,   700,   277,   277,   277,   730,
+    -903,   721,  -903,   -26,   116,   520,  -903,   441,   616,  -903,
+     457,   313,   313,  -903,  -903,   500,   500,   277,   836,   841,
+     842,   843,   844,   835,   846,   848,   849,   850,   851,   852,
+     716,  -903,  -903,  -903,  -903,   277,   277,   277,   855,   856,
+     316,  -903,   857,  -903,  -903,   722,   723,   725,   732,   734,
+     736,   868,   870,   826,   487,   394,   394,   245,   737,   389,
+     180,   877,   878,   748,   324,  -903,   773,   243,   268,   300,
+     881,   180,   180,   180,   882,   883,   189,  -903,  -903,  -903,
+    -903,   775,   903,   110,   277,   277,   277,   918,   905,   788,
+     789,   924,   245,   790,   793,   277,   927,  -903,   928,  -903,
+    -903,   929,   931,   932,   794,  -903,  -903,  -903,  -903,  -903,
+    -903,   277,   795,   935,   277,   797,   277,   277,   277,   937,
+     277,   277,   277,  -903,   938,   802,   869,   277,   804,   179,
+     803,   805,   871,  -903,   886,  -903,  -903,   811,  -903,   180,
+     180,   936,   940,   815,    72,  -903,  -903,  -903,   816,   817,
+     845,  -903,   853,  -903,   879,   887,   278,   822,   824,   827,
+     829,   830,   828,   833,   834,   837,   838,  -903,  -903,  -903,
+     967,   722,   723,   722,   -66,    92,   832,   854,   839,    95,
+    -903,   860,  -903,   962,   968,   969,   124,   326,   474,   981,
+    -903,   858,  -903,   982,   277,   847,   859,   861,   863,   985,
+     862,   864,   865,   867,   867,  -903,  -903,   867,   867,   873,
+    -903,  -903,  -903,   888,   866,   889,   890,   894,   872,   895,
+     896,   897,  -903,   897,   898,   899,   977,   978,   426,   901,
+    -903,   979,   902,   926,   904,   906,   907,   908,  -903,   880,
+     925,   892,   900,   946,   909,   910,   911,   893,   912,   913,
+     914,  -903,   891,   999,   915,   983,  1041,   984,   986,   987,
+    1051,   919,   277,   988,  1009,  1006,  -903,  -903,   180,  -903,
+    -903,   930,  -903,   933,   934,     2,     6,  -903,  1061,   277,
+     277,   277,   277,  1063,  1054,  1065,  1056,  1067,  1003,  -903,
+    -903,  -903,  1071,   427,  -903,  1072,   455,  -903,  -903,  -903,
+    1073,   939,   190,   209,   941,  -903,   723,   722,  -903,  -903,
+     277,   942,  1074,   277,   943,   944,  -903,   945,   947,  -903,
+     948,  -903,  -903,  1076,  1078,  1079,  1011,  -903,  -903,  -903,
+     975,  -903,  -903,  -903,  -903,   277,   277,   949,  1080,  1081,
+    -903,   497,   180,   180,   989,  -903,  -903,  1082,  -903,  -903,
+     897,  1088,   954,  -903,  1023,  1096,   277,  -903,  -903,  -903,
+    -903,  1025,  1098,  1027,  1028,   191,  -903,  -903,  -903,   180,
+    -903,  -903,  -903,   965,  -903,   997,   357,   970,   971,  1103,
+    1105,  -903,  -903,   246,   180,   180,   974,   180,  -903,  -903,
+     180,  -903,   180,   973,   976,   980,   990,   991,   992,   993,
+     994,   995,   996,   277,  1038,  -903,  -903,  -903,   998,  1039,
+    1000,  1001,  1042,  -903,  1002,  -903,  1013,  -903,  -903,  -903,
+    -903,  1004,   615,  1005,  1007,   615,  1050,  -903,   533,  -903,
+    1044,  1012,  1014,   394,  1015,  1016,  1017,   477,  -903,  1018,
+    1019,  1020,  1021,  1008,  1010,  1022,  1024,  -903,  1026,  -903,
+     394,  1045,  -903,  1118,  -903,  1110,  1121,  -903,  -903,  1030,
+    -903,  1031,  1032,  1033,  1124,  1125,   277,  1126,  -903,  -903,
+    -903,  1127,  -903,  -903,  -903,  1131,   180,   277,  1135,  1138,
+    1139,  1141,  -903,  -903,   949,   615,  1034,  1036,  1145,  -903,
+    1147,  -903,  -903,  1143,  1037,  1040,   615,  -903,   615,   615,
+    -903,   277,  -903,  -903,  -903,  -903,   180,  -903,   723,   278,
+    -903,  -903,  -903,  1043,  1046,   723,  -903,  -903,  -903,   588,
+    1159,  -903,  1115,  -903,   278,  1162,  -903,  -903,  -903,   949,
+    -903,  1163,  1164,  1047,  1048,  1052,  1116,  1049,  1053,  1055,
+    1057,  1060,  1062,  1064,  1066,  -903,  -903,  1068,  -903,   586,
+     624,  1123,  -903,  -903,  -903,  -903,  -903,  -903,  1133,  -903,
+    -903,  -903,  -903,  -903,  1059,  1058,  1069,  1168,  -903,  1114,
+    -903,  1070,  1075,   277,   582,  1112,   277,  -903,  1086,  1077,
+     277,   277,   277,   277,  1083,  1187,  1191,  1190,   180,  -903,
+    1197,  -903,  1156,   277,   277,   277,  1077,  -903,  -903,  -903,
+    -903,  1084,   971,  1085,  1087,  1091,  -903,  1089,  1090,  1092,
+    1093,  -903,  1094,   899,  -903,   899,  1097,  1207,  -903,  1095,
+    1100,  -903,  -903,  -903,  -903,  -903,  1099,  1101,  1102,  1102,
+    1104,   456,  -903,  -903,  -903,  -903,  1106,  1206,  1208,  -903,
+     579,  -903,   229,  -903,  -903,   555,  -903,  -903,  -903,   264,
+     448,  1200,  1108,  1111,   463,   464,   465,   479,   482,   516,
+     517,   518,   596,  -903,   427,  -903,  1113,   277,   277,  1107,
+    -903,  1120,  -903,  1129,  -903,  1136,  -903,  1137,  -903,  1140,
+    -903,  1142,  -903,  1144,  -903,  1122,  1128,  1161,  1130,  1132,
+    1134,  1146,  1148,  1149,  1150,  1151,  1152,  1153,  -903,  -903,
+    1201,  1077,  1077,  -903,  -903,  -903,  -903,  -903,  -903,  -903,
+    -903,  -903,  -903,  -903
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const short int yypgoto[] =
+{
+    -903,  -903,  -903,  -134,    17,  -219,  -716,  -902,   266,  -903,
+    -520,  -903,  -201,  -903,  -443,  -472,  -478,  -903,  -788,  -903,
+    -903,   952,  -275,  -903,   -39,  -903,   380,  -196,   303,  -903,
+    -252,     4,     8,  -162,   955,  -210,   -58,    49,  -903,   -20,
+    -903,  -903,  -903,  1209,  -903,    -3,    25
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -3
+static const short int yytable[] =
+{
+      81,   122,   124,   126,    69,   373,   353,   349,    70,   368,
+     600,   166,   169,   109,   109,   658,   295,    67,   422,   425,
+     297,   150,   414,   102,   103,   236,   105,   224,   107,   108,
+     111,   114,     7,     8,   299,   404,     7,     8,   599,   959,
+     601,   254,   403,   234,   242,   287,   288,   243,   237,   244,
+     392,   245,   398,   414,   246,   656,   247,   367,     7,     8,
+     115,   116,   444,   231,   248,   414,   167,     7,     8,    79,
+     146,   139,   996,   165,   421,   424,   258,   259,   855,   186,
+     188,   190,   225,   145,   228,   230,   164,   168,   281,   156,
+     402,    35,   602,     7,     8,   131,   255,   603,    36,   157,
+     414,   256,   221,   415,   151,   145,   233,   142,   579,   148,
+     436,   261,   262,    35,   249,   250,   253,   505,   931,   282,
+      36,    95,   144,   880,   363,   350,    35,   147,     7,     8,
+      96,   145,   460,   158,   416,    35,   461,   145,   391,    97,
+     159,   437,    36,   143,   729,   445,   417,   100,    35,   160,
+     161,   162,   251,   163,    69,    36,    98,   298,    70,    35,
+     618,    35,   310,    99,   235,   700,    36,    67,    36,   702,
+     316,   296,   185,   504,   730,   300,   301,   302,   303,   529,
+     305,   418,   757,   116,   101,   187,   232,    35,   306,   307,
+     308,   252,   104,   189,    36,   152,    62,    63,   530,   317,
+     318,   319,   320,   321,   322,   323,   324,   325,   326,    35,
+       7,     8,   227,    80,   229,   525,    36,   767,    62,    63,
+     611,   612,    35,  1022,  1023,   526,    80,   768,   119,    36,
+      35,    62,    63,   115,   116,    80,   354,    36,   613,   642,
+      62,    63,   643,   644,   145,   621,   624,   587,    80,    35,
+     605,    35,   355,    62,    63,   606,    36,   117,    36,    80,
+     309,    80,   390,   118,    62,    63,    62,    63,   121,   513,
+     287,   288,   123,    35,   462,     7,     8,   145,   463,   435,
+      36,   157,   439,   289,   290,   152,   662,    80,   441,    35,
+     153,   154,    62,    63,   515,   125,    36,   287,   288,   299,
+     127,   620,   623,   455,   456,   457,    35,   166,   169,    80,
+     571,   377,   378,    36,    62,    63,   128,   379,   394,   395,
+     396,   453,    80,   132,   467,   397,   517,    62,    63,   129,
+      80,    35,     7,     8,   133,    62,    63,   566,    36,   134,
+      35,   567,   481,   482,   483,   135,   869,    36,   724,    80,
+     149,    80,   725,   873,    62,    63,    62,    63,   966,   967,
+     772,   773,   284,    35,   285,    35,   774,   726,   968,   969,
+      36,   727,    36,    80,   514,   516,   518,   775,    62,    63,
+     176,    35,   136,    35,   501,   180,   181,   506,    36,    80,
+      36,   531,   532,   533,    62,    63,   287,   288,   520,   521,
+     522,   137,   542,   943,   781,   944,    80,   140,   782,   289,
+     420,    62,    63,    89,   141,    90,    91,    92,   549,   539,
+      93,   552,   972,   554,   555,   556,   973,   558,   559,   560,
+     157,    80,   313,   314,   564,   155,    62,    63,   381,   382,
+      80,   171,   287,   288,   383,    62,    63,   173,    69,   486,
+     487,   580,    70,   574,   575,   289,   423,   510,   511,   287,
+     288,    67,   184,    80,   226,    80,   573,   573,    62,    63,
+      62,    63,   289,   503,   130,   388,    90,    91,    92,     7,
+       8,   106,   238,   112,   628,   389,    62,    63,    62,    63,
+     368,   299,   403,   619,   191,   192,   193,   194,   239,   195,
+     196,   631,   197,   198,   199,   200,   201,   202,   176,   289,
+     661,   178,   179,   180,   181,   203,   240,   204,   205,     7,
+       8,   241,   174,   206,   176,   207,   260,   178,   179,   180,
+     181,   807,   182,   183,   810,   174,   175,   176,   177,   257,
+     178,   179,   180,   181,   287,   288,   464,   263,   182,   183,
+       7,     8,   208,   715,   716,   717,   465,   289,   622,   209,
+     264,   182,   183,   265,   210,   211,   212,   176,   266,   693,
+     178,   179,   180,   181,   213,   214,   215,   957,   958,   216,
+     720,   721,   715,   716,   717,   152,   704,   705,   706,   707,
+     153,   500,   138,   267,   856,   696,     7,     8,   823,   824,
+     870,   268,   701,   253,   269,   864,   974,   865,   866,   270,
+     975,   271,   217,   218,   874,   878,   273,   731,     7,     8,
+     734,   979,   981,   983,   274,   980,   982,   984,   174,   175,
+     176,   177,   286,   178,   179,   180,   181,   985,   751,   752,
+     987,   986,   745,   746,   988,   337,   338,   272,   339,   778,
+     287,   340,   219,   220,   182,   183,   275,    62,    63,   341,
+     342,   343,   344,   762,   896,   341,   342,   343,   344,   753,
+     754,   345,   346,   347,   989,   991,   993,   276,   990,   992,
+     994,   174,   277,   176,   177,   819,   178,   179,   180,   181,
+     907,   908,   909,   910,   287,   288,   769,    -2,     1,   970,
+     971,   786,   834,   812,   813,   814,   278,   182,   183,     2,
+     797,   783,   784,   279,   573,   964,   965,   957,   958,   280,
+     283,     3,     4,     5,   293,     6,   315,     7,     8,     9,
+      10,    11,    12,    13,    14,    15,    16,    17,    18,    19,
+     294,    20,    21,    22,    23,    24,    25,    26,    27,    28,
+      29,   327,   304,    30,    31,    32,    33,    34,   311,   352,
+      35,   356,   328,   329,   330,    82,   331,    36,   332,   333,
+      83,    84,   334,   845,    85,    86,   335,   336,   350,    87,
+      88,   357,   358,   359,   850,   360,   361,   362,   369,   370,
+     371,   372,   374,    37,    38,   376,   380,   384,   385,   386,
+     387,   393,   399,   849,   400,   401,   405,   406,   867,   407,
+      39,    40,    41,    42,   408,   410,   409,    43,   411,   412,
+      44,    45,   413,   426,   419,   427,   428,   429,   430,   431,
+     432,   434,   438,   868,   440,   433,   447,   448,   451,   442,
+      46,   449,   450,    47,    48,    49,   875,    50,    51,    52,
+      53,    54,    55,    56,    57,   443,   458,   459,   452,   454,
+      58,    59,   468,    60,    61,    62,    63,   469,   470,   471,
+     472,   473,   474,   933,   475,   476,   477,   478,   479,   480,
+     906,   484,   485,   913,   493,   489,   491,   917,   918,   919,
+     920,   494,   488,   495,   497,   496,   498,   499,     2,   502,
+     928,   929,   930,   507,   508,   512,   509,   519,   523,   524,
+       3,     4,     5,   527,     6,   925,     7,     8,     9,    10,
+      11,    12,    13,    14,    15,    16,    17,    18,    19,   528,
+      20,    21,    22,    23,    24,    25,    26,    27,    28,    29,
+     534,   535,    30,    31,    32,    33,    34,   536,   537,    35,
+     538,   541,   540,   543,   544,   545,    36,   546,   547,   548,
+     550,   551,   553,   557,   561,   562,   565,   563,   568,   570,
+     569,   572,   576,   578,   998,   999,   577,   585,   581,   582,
+     588,   583,    37,    38,   589,   586,   593,   590,   584,   591,
+     592,   594,   595,   598,   608,   596,   597,   610,   615,    39,
+      40,    41,    42,   614,   616,   617,    43,   625,   627,    44,
+      45,   636,   632,   659,   660,   664,   609,   633,   666,   634,
+     626,   635,   683,   672,   637,   684,   638,   639,   647,    46,
+     640,   645,    47,    48,    49,   651,    50,    51,    52,    53,
+      54,    55,    56,    57,   675,   671,   646,   648,   649,    58,
+      59,   679,    60,    61,    62,    63,   650,   673,   652,   653,
+     654,   657,   606,   663,   665,   674,   667,   687,   668,   669,
+     670,   676,   677,   678,   680,   681,   682,   691,   685,   694,
+     692,   686,   688,   695,   689,   690,   152,   703,   697,   708,
+     709,   710,   711,   712,   713,   698,   699,   714,   719,   722,
+     733,   723,   740,   728,   741,   742,   736,   732,   735,   743,
+     737,   744,   747,   739,   758,   755,   749,   750,   756,   759,
+     738,   760,   761,   763,   764,   765,   766,   770,   771,   779,
+     776,   780,   785,   787,   788,   777,   798,   800,   789,   805,
+     803,   811,   816,   835,   836,   804,   837,   838,   790,   791,
+     843,   844,   846,   847,   792,   793,   794,   795,   796,   848,
+     799,   851,   801,   802,   852,   853,   829,   854,   830,   806,
+     808,   859,   809,   860,   817,   861,   818,   820,   821,   822,
+     825,   826,   827,   828,   831,   876,   832,   877,   879,   881,
+     882,   833,   839,   840,   897,   841,   842,   857,   858,   862,
+     414,   894,   863,   898,   902,   871,   903,   883,   872,   886,
+     912,   884,   914,   922,   885,   887,   900,   923,   888,   889,
+     890,   899,   891,   924,   892,   926,   893,   927,   936,   946,
+     904,   901,   962,  1010,   963,   905,   976,  1021,   995,   895,
+     915,     0,   954,   113,  1000,   921,   932,   934,   446,   935,
+       0,   937,   938,   947,   939,   940,  1001,   941,   948,   945,
+       0,   949,     0,     0,   950,   952,  1002,   955,   977,   961,
+     466,   978,     0,  1003,  1004,   997,     0,  1005,     0,  1006,
+       0,  1007,     0,     0,  1008,     0,     0,     0,     0,     0,
+    1009,     0,  1011,     0,  1012,     0,  1013,     0,     0,     0,
+       0,     0,     0,     0,     0,     0,     0,     0,  1014,     0,
+    1015,  1016,  1017,  1018,  1019,  1020
+};
+
+static const short int yycheck[] =
+{
+       3,    40,    41,    42,     0,   224,   207,   203,     0,   219,
+     482,    69,    70,    33,    34,   535,   150,     0,   270,   271,
+      26,    78,    84,    26,    27,   143,    29,    85,    31,    32,
+      33,    34,    30,    31,    72,   254,    30,    31,   481,   941,
+     483,    99,   252,    28,    16,    70,    71,    19,   166,    21,
+     246,    23,   248,    84,    26,   533,    28,   219,    30,    31,
+      35,    36,    78,    26,    36,    84,    69,    30,    31,   163,
+      26,    54,   974,    69,   270,   271,    26,    27,   794,    82,
+      83,    84,    85,    58,    87,    88,    69,    70,    26,    26,
+     252,    63,   158,    30,    31,    46,    99,   163,    70,    36,
+      84,   104,    85,   165,   161,    80,    89,    28,    36,    60,
+      26,    26,    27,    63,    86,    87,    99,   369,   906,    57,
+      70,    98,    26,   839,    26,   163,    63,    83,    30,    31,
+      98,   106,   158,    70,   165,    63,   162,   112,   163,    98,
+      77,    57,    70,    64,   616,   161,   165,    26,    63,    86,
+      87,    88,   124,    90,   150,    70,    98,   163,   150,    63,
+      36,    63,   165,    98,   149,   163,    70,   150,    70,   163,
+     173,   154,    26,   369,   617,   158,   159,   160,   161,    69,
+     163,   165,   660,   158,    26,    26,   149,    63,    91,    92,
+      93,   163,   163,    26,    70,    98,   168,   169,    88,   174,
+     175,   176,   177,   178,   179,   180,   181,   182,   183,    63,
+      30,    31,    26,   163,    26,    26,    70,    26,   168,   169,
+     125,   126,    63,  1011,  1012,    36,   163,    36,   164,    70,
+      63,   168,   169,   208,   209,   163,    26,    70,   143,   514,
+     168,   169,   517,   518,   219,   497,   498,   466,   163,    63,
+     158,    63,    26,   168,   169,   163,    70,   163,    70,   163,
+     163,   163,   245,   163,   168,   169,   168,   169,   164,    26,
+      70,    71,   164,    63,   158,    30,    31,   252,   162,   282,
+      70,    36,   285,    83,    84,    98,   538,   163,   291,    63,
+     103,   104,   168,   169,    26,   164,    70,    70,    71,    72,
+     163,   497,   498,   306,   307,   308,    63,   365,   366,   163,
+     444,   106,   107,    70,   168,   169,   164,   112,    91,    92,
+      93,   304,   163,   163,   327,    98,    26,   168,   169,   164,
+     163,    63,    30,    31,   163,   168,   169,   158,    70,   163,
+      63,   162,   345,   346,   347,   163,   818,    70,   158,   163,
+       0,   163,   162,   825,   168,   169,   168,   169,   129,   130,
+       3,     4,   158,    63,   160,    63,     9,   158,   139,   140,
+      70,   162,    70,   163,   377,   378,   379,    20,   168,   169,
+      67,    63,   163,    63,   367,    72,    73,   370,    70,   163,
+      70,   394,   395,   396,   168,   169,    70,    71,   381,   382,
+     383,   163,   405,   923,   158,   925,   163,   163,   162,    83,
+      84,   168,   169,    98,   163,   100,   101,   102,   421,   402,
+     105,   424,   158,   426,   427,   428,   162,   430,   431,   432,
+      36,   163,   135,   136,   437,    98,   168,   169,   106,   107,
+     163,   163,    70,    71,   112,   168,   169,    98,   444,   133,
+     134,   454,   444,   449,   450,    83,    84,   133,   134,    70,
+      71,   444,    26,   163,    26,   163,   449,   450,   168,   169,
+     168,   169,    83,    84,    98,    26,   100,   101,   102,    30,
+      31,   163,    36,   163,   504,    36,   168,   169,   168,   169,
+     700,    72,   702,   496,     5,     6,     7,     8,    36,    10,
+      11,   504,    13,    14,    15,    16,    17,    18,    67,    83,
+      84,    70,    71,    72,    73,    26,    36,    28,    29,    30,
+      31,    36,    65,    34,    67,    36,   173,    70,    71,    72,
+      73,   732,    91,    92,   735,    65,    66,    67,    68,    26,
+      70,    71,    72,    73,    70,    71,    26,    26,    91,    92,
+      30,    31,    63,   126,   127,   128,    36,    83,    84,    70,
+      26,    91,    92,    26,    75,    76,    77,    67,    26,   572,
+      70,    71,    72,    73,    85,    86,    87,   121,   122,    90,
+     125,   126,   126,   127,   128,    98,   589,   590,   591,   592,
+     103,   104,    26,    26,   795,   578,    30,    31,   121,   122,
+     819,    26,   585,   586,    26,   806,   158,   808,   809,    26,
+     162,    26,   123,   124,    26,   834,    26,   620,    30,    31,
+     623,   158,   158,   158,    26,   162,   162,   162,    65,    66,
+      67,    68,   162,    70,    71,    72,    73,   158,   141,   142,
+     158,   162,   645,   646,   162,    65,    66,    28,    68,   688,
+      70,    71,   163,   164,    91,    92,    26,   168,   169,    79,
+      80,    81,    82,   666,   860,    79,    80,    81,    82,   652,
+     653,    91,    92,    93,   158,   158,   158,    26,   162,   162,
+     162,    65,    26,    67,    68,   743,    70,    71,    72,    73,
+     108,   109,   110,   111,    70,    71,   679,     0,     1,   144,
+     145,   697,   760,   170,   171,   172,    26,    91,    92,    12,
+     713,   694,   695,    36,   697,   136,   137,   121,   122,    26,
+      28,    24,    25,    26,    26,    28,   158,    30,    31,    32,
+      33,    34,    35,    36,    37,    38,    39,    40,    41,    42,
+      28,    44,    45,    46,    47,    48,    49,    50,    51,    52,
+      53,   160,   163,    56,    57,    58,    59,    60,   163,    71,
+      63,    26,   163,   163,   163,    89,   163,    70,   163,   163,
+      94,    95,   163,   776,    98,    99,   163,   163,   163,   103,
+     104,    26,    26,    26,   787,    26,   164,   164,    26,    71,
+     163,   163,   163,    96,    97,   163,   163,   163,   163,   163,
+      26,    98,    36,   786,    36,   164,   158,    98,   811,   162,
+     113,   114,   115,   116,    71,   162,   174,   120,    71,   158,
+     123,   124,   158,   158,   162,   158,   158,   158,   158,   158,
+     158,    98,    26,   816,    26,   162,    26,    36,   159,   165,
+     143,   158,   158,   146,   147,   148,   829,   150,   151,   152,
+     153,   154,   155,   156,   157,   165,   126,   136,   159,   159,
+     163,   164,    26,   166,   167,   168,   169,    26,    26,    26,
+      26,    36,    26,   912,    26,    26,    26,    26,    26,   163,
+     883,    26,    26,   886,   159,   163,   163,   890,   891,   892,
+     893,   159,    35,   159,    26,   159,    26,    71,    12,   162,
+     903,   904,   905,    26,    26,   132,   158,    26,    26,    26,
+      24,    25,    26,   138,    28,   898,    30,    31,    32,    33,
+      34,    35,    36,    37,    38,    39,    40,    41,    42,    26,
+      44,    45,    46,    47,    48,    49,    50,    51,    52,    53,
+      22,    36,    56,    57,    58,    59,    60,   159,   159,    63,
+      26,   158,   162,    26,    26,    26,    70,    26,    26,   165,
+     165,    26,   165,    26,    26,   163,   162,    98,   165,    98,
+     165,   160,    36,   158,   977,   978,    36,    98,   162,   162,
+     158,   136,    96,    97,   160,    98,   158,   160,   135,   160,
+     160,   158,   158,    26,   162,   158,   158,   158,    36,   113,
+     114,   115,   116,   143,    36,    36,   120,    26,    26,   123,
+     124,    26,   165,    36,    36,    36,   162,   158,    92,   158,
+     162,   158,   131,    98,   162,    26,   162,   162,   162,   143,
+     163,   158,   146,   147,   148,   163,   150,   151,   152,   153,
+     154,   155,   156,   157,    98,   165,   158,   158,   158,   163,
+     164,   158,   166,   167,   168,   169,   162,   165,   163,   163,
+     163,   163,   163,   162,   162,   165,   162,    26,   162,   162,
+     162,   162,   162,   162,   162,   162,   162,    26,   163,    70,
+     161,    98,    98,    77,    98,    98,    98,    26,   158,    26,
+      36,    26,    36,    26,    91,   162,   162,    26,    26,    26,
+      26,   162,    26,   162,    26,    26,   162,   165,   165,    98,
+     165,   136,   163,   165,    26,   126,    36,    36,    36,   165,
+     173,    98,    26,    98,    26,    98,    98,   162,   131,    26,
+     160,    26,   158,   160,   158,   164,    98,    98,   158,   126,
+      98,    91,    98,    98,    26,   143,    36,    26,   158,   158,
+      26,    26,    26,    26,   162,   162,   162,   162,   162,    28,
+     162,    26,   162,   162,    26,    26,   158,    26,   158,   165,
+     165,    26,   165,    26,   162,    32,   162,   162,   162,   162,
+     162,   162,   162,   162,   162,    26,   162,    72,    26,    26,
+      26,   165,   162,   162,    71,   163,   163,   163,   162,   162,
+      84,   133,   162,    70,    36,   162,    92,   160,   162,   160,
+      98,   163,   126,    26,   162,   162,   158,    26,   163,   162,
+     160,   162,   160,    33,   160,    28,   160,    71,   137,    22,
+     160,   162,    26,    72,    26,   160,    36,    36,   972,   859,
+     163,    -1,   939,    34,   137,   162,   162,   162,   296,   162,
+      -1,   162,   162,   158,   162,   162,   136,   163,   158,   162,
+      -1,   162,    -1,    -1,   163,   163,   137,   163,   160,   163,
+     315,   160,    -1,   137,   137,   162,    -1,   137,    -1,   137,
+      -1,   137,    -1,    -1,   162,    -1,    -1,    -1,    -1,    -1,
+     162,    -1,   162,    -1,   162,    -1,   162,    -1,    -1,    -1,
+      -1,    -1,    -1,    -1,    -1,    -1,    -1,    -1,   162,    -1,
+     162,   162,   162,   162,   162,   162
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const unsigned char yystos[] =
+{
+       0,     1,    12,    24,    25,    26,    28,    30,    31,    32,
+      33,    34,    35,    36,    37,    38,    39,    40,    41,    42,
+      44,    45,    46,    47,    48,    49,    50,    51,    52,    53,
+      56,    57,    58,    59,    60,    63,    70,    96,    97,   113,
+     114,   115,   116,   120,   123,   124,   143,   146,   147,   148,
+     150,   151,   152,   153,   154,   155,   156,   157,   163,   164,
+     166,   167,   168,   169,   176,   177,   178,   179,   198,   206,
+     207,   208,   209,   210,   213,   214,   219,   220,   221,   163,
+     163,   220,    89,    94,    95,    98,    99,   103,   104,    98,
+     100,   101,   102,   105,   212,    98,    98,    98,    98,    98,
+      26,    26,   220,   220,   163,   220,   163,   220,   220,   214,
+     218,   220,   163,   218,   220,   221,   221,   163,   163,   164,
+     199,   164,   199,   164,   199,   164,   199,   163,   164,   164,
+      98,   212,   163,   163,   163,   163,   163,   163,    26,   179,
+     163,   163,    28,    64,    26,   221,    26,    83,   212,     0,
+      78,   161,    98,   103,   104,    98,    26,    36,    70,    77,
+      86,    87,    88,    90,   179,   206,   211,   220,   179,   211,
+     211,   163,   180,    98,    65,    66,    67,    68,    70,    71,
+      72,    73,    91,    92,    26,    26,   220,    26,   220,    26,
+     220,     5,     6,     7,     8,    10,    11,    13,    14,    15,
+      16,    17,    18,    26,    28,    29,    34,    36,    63,    70,
+      75,    76,    77,    85,    86,    87,    90,   123,   124,   163,
+     164,   179,   195,   200,   211,   220,    26,    26,   220,    26,
+     220,    26,   149,   179,    28,   149,   143,   166,    36,    36,
+      36,    36,    16,    19,    21,    23,    26,    28,    36,    86,
+      87,   124,   163,   179,   211,   220,   220,    26,    26,    27,
+     173,    26,    27,    26,    26,    26,    26,    26,    26,    26,
+      26,    26,    28,    26,    26,    26,    26,    26,    26,    36,
+      26,    26,    57,    28,   158,   160,   162,    70,    71,    83,
+      84,   202,   205,    26,    28,   178,   179,    26,   163,    72,
+     179,   179,   179,   179,   163,   179,    91,    92,    93,   163,
+     220,   163,   196,   135,   136,   158,   220,   221,   221,   221,
+     221,   221,   221,   221,   221,   221,   221,   160,   163,   163,
+     163,   163,   163,   163,   163,   163,   163,    65,    66,    68,
+      71,    79,    80,    81,    82,    91,    92,    93,   201,   202,
+     163,   187,    71,   187,    26,    26,    26,    26,    26,    26,
+      26,   164,   164,    26,   179,   206,   207,   208,   210,    26,
+      71,   163,   163,   180,   163,   188,   163,   106,   107,   112,
+     163,   106,   107,   112,   163,   163,   163,    26,    26,    36,
+     179,   163,   202,    98,    91,    92,    93,    98,   202,    36,
+      36,   164,   208,   210,   180,   158,    98,   162,    71,   174,
+     162,    71,   158,   158,    84,   165,   165,   165,   165,   162,
+      84,   202,   205,    84,   202,   205,   158,   158,   158,   158,
+     158,   158,   158,   162,    98,   220,    26,    57,    26,   220,
+      26,   220,   165,   165,    78,   161,   196,    26,    36,   158,
+     158,   159,   159,   179,   159,   220,   220,   220,   126,   136,
+     158,   162,   158,   162,    26,    36,   209,   220,    26,    26,
+      26,    26,    26,    36,    26,    26,    26,    26,    26,    26,
+     163,   220,   220,   220,    26,    26,   133,   134,    35,   163,
+     189,   163,   190,   159,   159,   159,   159,    26,    26,    71,
+     104,   179,   162,    84,   202,   205,   179,    26,    26,   158,
+     133,   134,   132,    26,   220,    26,   220,    26,   220,    26,
+     179,   179,   179,    26,    26,    26,    36,   138,    26,    69,
+      88,   220,   220,   220,    22,    36,   159,   159,    26,   179,
+     162,   158,   220,    26,    26,    26,    26,    26,   165,   220,
+     165,    26,   220,   165,   220,   220,   220,    26,   220,   220,
+     220,    26,   163,    98,   220,   162,   158,   162,   165,   165,
+      98,   178,   160,   179,   206,   206,    36,    36,   158,    36,
+     220,   162,   162,   136,   135,    98,    98,   180,   158,   160,
+     160,   160,   160,   158,   158,   158,   158,   158,    26,   189,
+     190,   189,   158,   163,   184,   158,   163,   185,   162,   162,
+     158,   125,   126,   143,   143,    36,    36,    36,    36,   220,
+     202,   205,    84,   202,   205,    26,   162,    26,   214,   216,
+     217,   220,   165,   158,   158,   158,    26,   162,   162,   162,
+     163,   197,   197,   197,   197,   158,   158,   162,   158,   158,
+     162,   163,   163,   163,   163,   191,   191,   163,   185,    36,
+      36,    84,   205,   162,    36,   162,    92,   162,   162,   162,
+     162,   165,    98,   165,   165,    98,   162,   162,   162,   158,
+     162,   162,   162,   131,    26,   163,    98,    26,    98,    98,
+      98,    26,   161,   220,    70,    77,   179,   158,   162,   162,
+     163,   179,   163,    26,   220,   220,   220,   220,    26,    36,
+      26,    36,    26,    91,    26,   126,   127,   128,   182,    26,
+     125,   126,    26,   162,   158,   162,   158,   162,   162,   190,
+     189,   220,   165,    26,   220,   165,   162,   165,   173,   165,
+      26,    26,    26,    98,   136,   220,   220,   163,   181,    36,
+      36,   141,   142,   179,   179,   126,    36,   191,    26,   165,
+      98,    26,   220,    98,    26,    98,    98,    26,    36,   179,
+     162,   131,     3,     4,     9,    20,   160,   164,   199,    26,
+      26,   158,   162,   179,   179,   158,   206,   160,   158,   158,
+     158,   158,   162,   162,   162,   162,   162,   220,    98,   162,
+      98,   162,   162,    98,   143,   126,   165,   187,   165,   165,
+     187,    91,   170,   171,   172,   215,    98,   162,   162,   211,
+     162,   162,   162,   121,   122,   162,   162,   162,   162,   158,
+     158,   162,   162,   165,   211,    98,    26,    36,    26,   162,
+     162,   163,   163,    26,    26,   220,    26,    26,    28,   179,
+     220,    26,    26,    26,    26,   181,   187,   163,   162,    26,
+      26,    32,   162,   162,   187,   187,   187,   220,   179,   190,
+     180,   162,   162,   190,    26,   179,    26,    72,   180,    26,
+     181,    26,    26,   160,   163,   162,   160,   162,   163,   162,
+     160,   160,   160,   160,   133,   201,   202,    71,    70,   162,
+     158,   162,    36,    92,   160,   160,   220,   108,   109,   110,
+     111,   192,    98,   220,   126,   163,   193,   220,   220,   220,
+     220,   162,    26,    26,    33,   179,    28,    71,   220,   220,
+     220,   193,   162,   199,   162,   162,   137,   162,   162,   162,
+     162,   163,   186,   185,   185,   162,    22,   158,   158,   162,
+     163,   194,   163,   203,   203,   163,   204,   121,   122,   182,
+     183,   163,    26,    26,   136,   137,   129,   130,   139,   140,
+     144,   145,   158,   162,   158,   162,    36,   160,   160,   158,
+     162,   158,   162,   158,   162,   158,   162,   158,   162,   158,
+     162,   158,   162,   158,   162,   183,   182,   162,   220,   220,
+     137,   136,   137,   137,   137,   137,   137,   137,   162,   162,
+      72,   162,   162,   162,   162,   162,   162,   162,   162,   162,
+     162,    36,   193,   193
+};
+
+#define yyerrok		(yyerrstatus = 0)
+#define yyclearin	(yychar = YYEMPTY)
+#define YYEMPTY		(-2)
+#define YYEOF		0
+
+#define YYACCEPT	goto yyacceptlab
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror.  This remains here temporarily
+   to ease the transition to the new meaning of YYERROR, for GCC.
+   Once GCC version 2 has supplanted version 1, this can go.  */
+
+#define YYFAIL		goto yyerrlab
+
+#define YYRECOVERING()  (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value)					\
+do								\
+  if (yychar == YYEMPTY && yylen == 1)				\
+    {								\
+      yychar = (Token);						\
+      yylval = (Value);						\
+      yytoken = YYTRANSLATE (yychar);				\
+      YYPOPSTACK;						\
+      goto yybackup;						\
+    }								\
+  else								\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
+      YYERROR;							\
+    }								\
+while (0)
+
+
+#define YYTERROR	1
+#define YYERRCODE	256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (N)								\
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (0)
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+              (Loc).first_line, (Loc).first_column,	\
+              (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
+/* Enable debugging if requested.  */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+#  include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+#  define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args)			\
+do {						\
+  if (yydebug)					\
+    YYFPRINTF Args;				\
+} while (0)
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
+do {								\
+  if (yydebug)							\
+    {								\
+      YYFPRINTF (stderr, "%s ", Title);				\
+      yysymprint (stderr,					\
+                  Type, Value);	\
+      YYFPRINTF (stderr, "\n");					\
+    }								\
+} while (0)
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_stack_print (short int *bottom, short int *top)
+#else
+static void
+yy_stack_print (bottom, top)
+    short int *bottom;
+    short int *top;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (/* Nothing. */; bottom <= top; ++bottom)
+    YYFPRINTF (stderr, " %d", *bottom);
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_reduce_print (int yyrule)
+#else
+static void
+yy_reduce_print (yyrule)
+    int yyrule;
+#endif
+{
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
+             yyrule - 1, yylno);
+  /* Print the symbols being reduced, and their result.  */
+  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
+    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
+  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (Rule);		\
+} while (0)
+
+/* Nonzero means print parse trace.  It is left uninitialized so that
+   multiple parsers can coexist.  */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks.  */
+#ifndef	YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+   if the built-in stack extension method is used).
+
+   Do not make this value too large; the results are undefined if
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+   evaluated with infinite-precision integer arithmetic.  */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+#  if defined (__GLIBC__) && defined (_STRING_H)
+#   define yystrlen strlen
+#  else
+/* Return the length of YYSTR.  */
+static YYSIZE_T
+#   if defined (__STDC__) || defined (__cplusplus)
+yystrlen (const char *yystr)
+#   else
+yystrlen (yystr)
+     const char *yystr;
+#   endif
+{
+  const char *yys = yystr;
+
+  while (*yys++ != '\0')
+    continue;
+
+  return yys - yystr - 1;
+}
+#  endif
+# endif
+
+# ifndef yystpcpy
+#  if defined (__GLIBC__) && defined (_STRING_H) && defined (_GNU_SOURCE)
+#   define yystpcpy stpcpy
+#  else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+   YYDEST.  */
+static char *
+#   if defined (__STDC__) || defined (__cplusplus)
+yystpcpy (char *yydest, const char *yysrc)
+#   else
+yystpcpy (yydest, yysrc)
+     char *yydest;
+     const char *yysrc;
+#   endif
+{
+  char *yyd = yydest;
+  const char *yys = yysrc;
+
+  while ((*yyd++ = *yys++) != '\0')
+    continue;
+
+  return yyd - 1;
+}
+#  endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      size_t yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+#endif /* YYERROR_VERBOSE */
+
+
+
+#if YYDEBUG
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yysymprint (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+  switch (yytype)
+    {
+      default:
+        break;
+    }
+  YYFPRINTF (yyoutput, ")");
+}
+
+#endif /* ! YYDEBUG */
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+
+      default:
+        break;
+    }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes.  */
+
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM);
+# else
+int yyparse ();
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+
+/* The look-ahead symbol.  */
+int yychar;
+
+/* The semantic value of the look-ahead symbol.  */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far.  */
+int yynerrs;
+
+
+
+/*----------.
+| yyparse.  |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM)
+# else
+int yyparse (YYPARSE_PARAM)
+  void *YYPARSE_PARAM;
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
+int
+yyparse (void)
+#else
+int
+yyparse ()
+    ;
+#endif
+#endif
+{
+  
+  int yystate;
+  int yyn;
+  int yyresult;
+  /* Number of tokens to shift before error messages enabled.  */
+  int yyerrstatus;
+  /* Look-ahead token as an internal (translated) token number.  */
+  int yytoken = 0;
+
+  /* Three stacks and their tools:
+     `yyss': related to states,
+     `yyvs': related to semantic values,
+     `yyls': related to locations.
+
+     Refer to the stacks thru separate pointers, to allow yyoverflow
+     to reallocate them elsewhere.  */
+
+  /* The state stack.  */
+  short int yyssa[YYINITDEPTH];
+  short int *yyss = yyssa;
+  short int *yyssp;
+
+  /* The semantic value stack.  */
+  YYSTYPE yyvsa[YYINITDEPTH];
+  YYSTYPE *yyvs = yyvsa;
+  YYSTYPE *yyvsp;
+
+
+
+#define YYPOPSTACK   (yyvsp--, yyssp--)
+
+  YYSIZE_T yystacksize = YYINITDEPTH;
+
+  /* The variables used to return semantic value and location from the
+     action routines.  */
+  YYSTYPE yyval;
+
+
+  /* When reducing, the number of symbols on the RHS of the reduced
+     rule.  */
+  int yylen;
+
+  YYDPRINTF ((stderr, "Starting parse\n"));
+
+  yystate = 0;
+  yyerrstatus = 0;
+  yynerrs = 0;
+  yychar = YYEMPTY;		/* Cause a token to be read.  */
+
+  /* Initialize stack pointers.
+     Waste one element of value and location stack
+     so that they stay on the same level as the state stack.
+     The wasted elements are never initialized.  */
+
+  yyssp = yyss;
+  yyvsp = yyvs;
+
+  goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate.  |
+`------------------------------------------------------------*/
+ yynewstate:
+  /* In all cases, when you get here, the value and location stacks
+     have just been pushed. so pushing a state here evens the stacks.
+     */
+  yyssp++;
+
+ yysetstate:
+  *yyssp = yystate;
+
+  if (yyss + yystacksize - 1 <= yyssp)
+    {
+      /* Get the current used size of the three stacks, in elements.  */
+      YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+      {
+	/* Give user a chance to reallocate the stack. Use copies of
+	   these so that the &'s don't force the real ones into
+	   memory.  */
+	YYSTYPE *yyvs1 = yyvs;
+	short int *yyss1 = yyss;
+
+
+	/* Each stack pointer address is followed by the size of the
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
+		    &yyss1, yysize * sizeof (*yyssp),
+		    &yyvs1, yysize * sizeof (*yyvsp),
+
+		    &yystacksize);
+
+	yyss = yyss1;
+	yyvs = yyvs1;
+      }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+      goto yyexhaustedlab;
+# else
+      /* Extend the stack our own way.  */
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
+      yystacksize *= 2;
+      if (YYMAXDEPTH < yystacksize)
+	yystacksize = YYMAXDEPTH;
+
+      {
+	short int *yyss1 = yyss;
+	union yyalloc *yyptr =
+	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+	if (! yyptr)
+	  goto yyexhaustedlab;
+	YYSTACK_RELOCATE (yyss);
+	YYSTACK_RELOCATE (yyvs);
+
+#  undef YYSTACK_RELOCATE
+	if (yyss1 != yyssa)
+	  YYSTACK_FREE (yyss1);
+      }
+# endif
+#endif /* no yyoverflow */
+
+      yyssp = yyss + yysize - 1;
+      yyvsp = yyvs + yysize - 1;
+
+
+      YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+		  (unsigned long int) yystacksize));
+
+      if (yyss + yystacksize - 1 <= yyssp)
+	YYABORT;
+    }
+
+  YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+  goto yybackup;
+
+/*-----------.
+| yybackup.  |
+`-----------*/
+yybackup:
+
+/* Do appropriate processing given the current state.  */
+/* Read a look-ahead token if we need one and don't already have one.  */
+/* yyresume: */
+
+  /* First try to decide what to do without reference to look-ahead token.  */
+
+  yyn = yypact[yystate];
+  if (yyn == YYPACT_NINF)
+    goto yydefault;
+
+  /* Not known => get a look-ahead token if don't already have one.  */
+
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
+  if (yychar == YYEMPTY)
+    {
+      YYDPRINTF ((stderr, "Reading a token: "));
+      yychar = YYLEX;
+    }
+
+  if (yychar <= YYEOF)
+    {
+      yychar = yytoken = YYEOF;
+      YYDPRINTF ((stderr, "Now at end of input.\n"));
+    }
+  else
+    {
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+    }
+
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+    goto yydefault;
+  yyn = yytable[yyn];
+  if (yyn <= 0)
+    {
+      if (yyn == 0 || yyn == YYTABLE_NINF)
+	goto yyerrlab;
+      yyn = -yyn;
+      goto yyreduce;
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  /* Shift the look-ahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+  /* Discard the token being shifted unless it is eof.  */
+  if (yychar != YYEOF)
+    yychar = YYEMPTY;
+
+  *++yyvsp = yylval;
+
+
+  /* Count tokens shifted since error; after three, turn off error
+     status.  */
+  if (yyerrstatus)
+    yyerrstatus--;
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state.  |
+`-----------------------------------------------------------*/
+yydefault:
+  yyn = yydefact[yystate];
+  if (yyn == 0)
+    goto yyerrlab;
+  goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction.  |
+`-----------------------------*/
+yyreduce:
+  /* yyn is the number of a rule to reduce with.  */
+  yylen = yyr2[yyn];
+
+  /* If YYLEN is nonzero, implement the default value of the action:
+     `$$ = $1'.
+
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
+     users should not rely upon it.  Assigning to YYVAL
+     unconditionally makes the parser a bit smaller, and it avoids a
+     GCC warning that YYVAL may be used uninitialized.  */
+  yyval = yyvsp[1-yylen];
+
+
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 3:
+#line 569 "bfin-parse.y"
+    {
+	  insn = (yyvsp[0].instr);
+	  if (insn == (INSTR_T) 0)
+	    return NO_INSN_GENERATED;
+	  else if (insn == (INSTR_T) - 1)
+	    return SEMANTIC_ERROR;
+	  else
+	    return INSN_GENERATED;
+	}
+    break;
+
+  case 5:
+#line 583 "bfin-parse.y"
+    {
+	  if (((yyvsp[-5].instr)->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-5].instr), (yyvsp[-3].instr), (yyvsp[-1].instr));
+	      else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-5].instr), (yyvsp[-1].instr), (yyvsp[-3].instr));
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
+	    }
+	  else if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-5].instr), (yyvsp[-1].instr));
+	      else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-1].instr), (yyvsp[-5].instr));
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
+	    }
+	  else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ((yyvsp[-5].instr)) && is_group2 ((yyvsp[-3].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-5].instr), (yyvsp[-3].instr));
+	      else if (is_group2 ((yyvsp[-5].instr)) && is_group1 ((yyvsp[-3].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-3].instr), (yyvsp[-5].instr));
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
+	    }
+	  else
+	    error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
+	}
+    break;
+
+  case 6:
+#line 616 "bfin-parse.y"
+    {
+	  if (((yyvsp[-3].instr)->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), (yyvsp[-1].instr), 0);
+	      else if (is_group2 ((yyvsp[-1].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-3].instr), 0, (yyvsp[-1].instr));
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
+	    }
+	  else if (((yyvsp[-1].instr)->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ((yyvsp[-3].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), (yyvsp[-3].instr), 0);
+	      else if (is_group2 ((yyvsp[-3].instr)))
+		(yyval.instr) = bfin_gen_multi_instr ((yyvsp[-1].instr), 0, (yyvsp[-3].instr));
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
+	    }
+	  else if (is_group1 ((yyvsp[-3].instr)) && is_group2 ((yyvsp[-1].instr)))
+	      (yyval.instr) = bfin_gen_multi_instr (0, (yyvsp[-3].instr), (yyvsp[-1].instr));
+	  else if (is_group2 ((yyvsp[-3].instr)) && is_group1 ((yyvsp[-1].instr)))
+	    (yyval.instr) = bfin_gen_multi_instr (0, (yyvsp[-1].instr), (yyvsp[-3].instr));
+	  else
+	    return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
+	}
+    break;
+
+  case 7:
+#line 643 "bfin-parse.y"
+    {
+	(yyval.instr) = 0;
+	yyerror ("");
+	yyerrok;
+	}
+    break;
+
+  case 8:
+#line 654 "bfin-parse.y"
+    {
+	  (yyval.instr) = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
+	}
+    break;
+
+  case 9:
+#line 658 "bfin-parse.y"
+    {
+	  int op0, op1;
+	  int w0 = 0, w1 = 0;
+	  int h00, h10, h01, h11;
+
+	  if ((yyvsp[-1].macfunc).n == 0)
+	    {
+	      if ((yyvsp[0].mod).MM) 
+		return yyerror ("(m) not allowed with a0 unit");
+	      op1 = 3;
+	      op0 = (yyvsp[-1].macfunc).op;
+	      w1 = 0;
+              w0 = (yyvsp[-1].macfunc).w;
+	      h00 = IS_H ((yyvsp[-1].macfunc).s0);
+              h10 = IS_H ((yyvsp[-1].macfunc).s1);
+	      h01 = h11 = 0;
+	    }
+	  else
+	    {
+	      op1 = (yyvsp[-1].macfunc).op;
+	      op0 = 3;
+	      w1 = (yyvsp[-1].macfunc).w;
+              w0 = 0;
+	      h00 = h10 = 0;
+	      h01 = IS_H ((yyvsp[-1].macfunc).s0);
+              h11 = IS_H ((yyvsp[-1].macfunc).s1);
+	    }
+	  (yyval.instr) = DSP32MAC (op1, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, w1, (yyvsp[-1].macfunc).P, h01, h11, h00, h10,
+			 &(yyvsp[-1].macfunc).dst, op0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, w0);
+	}
+    break;
+
+  case 10:
+#line 693 "bfin-parse.y"
+    {
+	  Register *dst;
+
+	  if (check_macfuncs (&(yyvsp[-4].macfunc), &(yyvsp[-3].mod), &(yyvsp[-1].macfunc), &(yyvsp[0].mod)) < 0) 
+	    return -1;
+	  notethat ("assign_macfunc (.), assign_macfunc (.)\n");
+
+	  if ((yyvsp[-4].macfunc).w)
+	    dst = &(yyvsp[-4].macfunc).dst;
+	  else
+	    dst = &(yyvsp[-1].macfunc).dst;
+
+	  (yyval.instr) = DSP32MAC ((yyvsp[-4].macfunc).op, (yyvsp[-3].mod).MM, (yyvsp[0].mod).mod, (yyvsp[-4].macfunc).w, (yyvsp[-4].macfunc).P,
+			 IS_H ((yyvsp[-4].macfunc).s0),  IS_H ((yyvsp[-4].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+			 dst, (yyvsp[-1].macfunc).op, &(yyvsp[-4].macfunc).s0, &(yyvsp[-4].macfunc).s1, (yyvsp[-1].macfunc).w);
+	}
+    break;
+
+  case 11:
+#line 713 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: DISALGNEXCPT\n");
+	  (yyval.instr) = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
+	}
+    break;
+
+  case 12:
+#line 718 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && !IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
+	      (yyval.instr) = DSP32ALU (11, 0, 0, &(yyvsp[-5].reg), 0, 0, 0, 0, 0);
+	    }
+	  else 
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 13:
+#line 728 "bfin-parse.y"
+    {
+	  if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
+	      (yyval.instr) = DSP32ALU (11, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 14:
+#line 738 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+	  (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
+	}
+    break;
+
+  case 15:
+#line 743 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+	  (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
+	}
+    break;
+
+  case 16:
+#line 749 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG ((yyvsp[-13].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
+	      (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
+	    }
+	}
+    break;
+
+  case 17:
+#line 765 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-15].reg)) || !IS_DREG((yyvsp[-13].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
+	      (yyval.instr) = DSP32ALU (21, 0, &(yyvsp[-15].reg), &(yyvsp[-13].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 1);
+	    }
+	}
+    break;
+
+  case 18:
+#line 780 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
+	      (yyval.instr) = DSP32ALU (24, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, (yyvsp[0].r0).r0, 0, 1);
+	    }
+	}
+    break;
+
+  case 19:
+#line 792 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
+	      (yyval.instr) = DSP32ALU (13, 0, &(yyvsp[-9].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0, (yyvsp[-1].r0).r0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 20:
+#line 803 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-4].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
+	      (yyval.instr) = DSP32ALU (12, 0, &(yyvsp[-10].reg), &(yyvsp[-4].reg), 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 21:
+#line 815 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
+	      && IS_A1 ((yyvsp[-3].reg)) && !IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
+	      (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), 0, 0, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 0);
+	      
+	    }
+	  else if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-5].reg)) && !REG_SAME ((yyvsp[-9].reg), (yyvsp[-7].reg))
+		   && !IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
+	      (yyval.instr) = DSP32ALU (17, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), 0, 0, (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 22:
+#line 834 "bfin-parse.y"
+    {
+	  if ((yyvsp[-8].r0).r0 == (yyvsp[-2].r0).r0) 
+	    return yyerror ("Operators must differ");
+
+	  if (IS_DREG ((yyvsp[-11].reg)) && IS_DREG ((yyvsp[-9].reg)) && IS_DREG ((yyvsp[-7].reg))
+	      && REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) && REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = dregs + dregs,"
+		       "dregs = dregs - dregs (amod1)\n");
+	      (yyval.instr) = DSP32ALU (4, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 23:
+#line 852 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-9].reg), (yyvsp[-3].reg)) || !REG_SAME ((yyvsp[-7].reg), (yyvsp[-1].reg)))
+	    return yyerror ("Differing source registers");
+
+	  if (!IS_DREG ((yyvsp[-11].reg)) || !IS_DREG ((yyvsp[-9].reg)) || !IS_DREG ((yyvsp[-7].reg)) || !IS_DREG ((yyvsp[-5].reg))) 
+	    return yyerror ("Dregs expected");
+
+	
+	  if ((yyvsp[-8].r0).r0 == 1 && (yyvsp[-2].r0).r0 == 2)
+	    {
+	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+	      (yyval.instr) = DSP32ALU (1, 1, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
+	    }
+	  else if ((yyvsp[-8].r0).r0 == 0 && (yyvsp[-2].r0).r0 == 3)
+	    {
+	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+	      (yyval.instr) = DSP32ALU (1, 0, &(yyvsp[-11].reg), &(yyvsp[-5].reg), &(yyvsp[-9].reg), &(yyvsp[-7].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).r0);
+	    }
+	  else
+	    return yyerror ("Bar operand mismatch");
+	}
+    break;
+
+  case 24:
+#line 875 "bfin-parse.y"
+    {
+	  int op;
+
+	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      if ((yyvsp[0].r0).r0)
+		{
+		  notethat ("dsp32alu: dregs = ABS dregs (v)\n");
+		  op = 6;
+		}
+	      else
+		{
+		  /* Vector version of ABS.  */
+		  notethat ("dsp32alu: dregs = ABS dregs\n");
+		  op = 7;
+		}
+	      (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 25:
+#line 897 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: Ax = ABS Ax\n");
+	  (yyval.instr) = DSP32ALU (16, IS_A1 ((yyvsp[-2].reg)), 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[0].reg)));
+	}
+    break;
+
+  case 26:
+#line 902 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32alu: A0.l = reg_half\n");
+	      (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("A0.l = Rx.l expected");
+	}
+    break;
+
+  case 27:
+#line 912 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32alu: A1.l = reg_half\n");
+	      (yyval.instr) = DSP32ALU (9, IS_H ((yyvsp[0].reg)), 0, 0, &(yyvsp[0].reg), 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("A1.l = Rx.l expected");
+	}
+    break;
+
+  case 28:
+#line 923 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
+	      (yyval.instr) = DSP32SHIFT (13, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[-5].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 29:
+#line 934 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-12].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+	      (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, (yyvsp[0].modcodes).r0);
+	    }
+	}
+    break;
+
+  case 30:
+#line 948 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-11].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-7].reg), (yyvsp[-5].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-3].reg), (yyvsp[-1].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+	      (yyval.instr) = DSP32ALU (20, 0, 0, &(yyvsp[-11].reg), &(yyvsp[-7].reg), &(yyvsp[-3].reg), 0, 0, 0);
+	    }
+	}
+    break;
+
+  case 31:
+#line 964 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-12].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
+	      (yyval.instr) = DSP32ALU (22, (yyvsp[0].modcodes).r0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).aop);
+	    }
+	}
+    break;
+
+  case 32:
+#line 980 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-12].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
+	      (yyval.instr) = DSP32ALU (22, (yyvsp[0].modcodes).r0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, (yyvsp[0].modcodes).x0);
+	    }
+	}
+    break;
+
+  case 33:
+#line 996 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-12].reg)))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
+	      (yyval.instr) = DSP32ALU (23, (yyvsp[0].modcodes).x0, 0, &(yyvsp[-12].reg), &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].modcodes).s0, 0, 0);
+	    }
+	}
+    break;
+
+  case 34:
+#line 1011 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
+	      (yyval.instr) = DSP32ALU (24, 0, 0, &(yyvsp[-7].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 35:
+#line 1023 "bfin-parse.y"
+    {
+	  if (IS_HCOMPL ((yyvsp[-16].reg), (yyvsp[-14].reg)) && IS_HCOMPL ((yyvsp[-10].reg), (yyvsp[-3].reg)) && IS_HCOMPL ((yyvsp[-7].reg), (yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32alu:	dregs_hi = dregs_lo ="
+		       "SIGN (dregs_hi) * dregs_hi + "
+		       "SIGN (dregs_lo) * dregs_lo \n");
+
+		(yyval.instr) = DSP32ALU (12, 0, 0, &(yyvsp[-16].reg), &(yyvsp[-10].reg), &(yyvsp[-7].reg), 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 36:
+#line 1036 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      if ((yyvsp[0].modcodes).aop == 0)
+		{
+	          /* No saturation flag specified, generate the 16 bit variant.  */
+		  notethat ("COMP3op: dregs = dregs +- dregs\n");
+		  (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[-2].r0).r0);
+		}
+	      else
+		{
+		 /* Saturation flag specified, generate the 32 bit variant.  */
+                 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
+                 (yyval.instr) = DSP32ALU (4, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
+		}
+	    }
+	  else
+	    if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)) && (yyvsp[-2].r0).r0 == 0)
+	      {
+		notethat ("COMP3op: pregs = pregs + pregs\n");
+		(yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), 5);
+	      }
+	    else
+	      return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 37:
+#line 1062 "bfin-parse.y"
+    {
+	  int op;
+
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
+	    {
+	      if ((yyvsp[0].r0).r0)
+		op = 6;
+	      else
+		op = 7;
+
+	      notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
+	      (yyval.instr) = DSP32ALU (op, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), &(yyvsp[-2].reg), 0, 0, (yyvsp[-6].r0).r0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 38:
+#line 1080 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: Ax = - Ax\n");
+	  (yyval.instr) = DSP32ALU (14, IS_A1 ((yyvsp[-2].reg)), 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[0].reg)));
+	}
+    break;
+
+  case 39:
+#line 1085 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
+	  (yyval.instr) = DSP32ALU (2 | (yyvsp[-2].r0).r0, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg),
+			 (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)));
+	}
+    break;
+
+  case 40:
+#line 1091 "bfin-parse.y"
+    {
+	  if (EXPR_VALUE ((yyvsp[0].expr)) == 0 && !REG_SAME ((yyvsp[-2].reg), (yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: A1 = A0 = 0\n");
+	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Bad value, 0 expected");
+	}
+    break;
+
+  case 41:
+#line 1103 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32alu: Ax = Ax (S)\n");
+	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ((yyvsp[-4].reg)));
+	    }
+	  else
+	    return yyerror ("Registers must be equal");
+	}
+    break;
+
+  case 42:
+#line 1114 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs (RND)\n");
+	      (yyval.instr) = DSP32ALU (12, IS_H ((yyvsp[-5].reg)), 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 43:
+#line 1125 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
+	      (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 0, (yyvsp[-4].r0).r0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 44:
+#line 1136 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
+	      (yyval.instr) = DSP32ALU (5, IS_H ((yyvsp[-7].reg)), 0, &(yyvsp[-7].reg), &(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1, (yyvsp[-4].r0).r0 | 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 45:
+#line 1147 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-1].reg), (yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32alu: An = Am\n");
+	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[-1].reg)), 0, 3);
+	    }
+	  else
+	    return yyerror ("Accu reg arguments must differ");
+	}
+    break;
+
+  case 46:
+#line 1158 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32alu: An = dregs\n");
+	      (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[0].reg), 0, 1, 0, IS_A1 ((yyvsp[-1].reg)) << 1);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 47:
+#line 1169 "bfin-parse.y"
+    {
+	  if (!IS_H ((yyvsp[-1].reg)))
+	    {
+	      if ((yyvsp[-3].reg).regno == REG_A0x && IS_DREG ((yyvsp[-1].reg)))
+		{
+		  notethat ("dsp32alu: A0.x = dregs_lo\n");
+		  (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 1);
+		}
+	      else if ((yyvsp[-3].reg).regno == REG_A1x && IS_DREG ((yyvsp[-1].reg)))
+		{
+		  notethat ("dsp32alu: A1.x = dregs_lo\n");
+		  (yyval.instr) = DSP32ALU (9, 0, 0, 0, &(yyvsp[-1].reg), 0, 0, 0, 3);
+		}
+	      else if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+		{
+		  notethat ("ALU2op: dregs = dregs_lo\n");
+		  (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 10 | ((yyvsp[0].r0).r0 ? 0: 1));
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	  else
+	    return yyerror ("Low reg expected");
+	}
+    break;
+
+  case 48:
+#line 1195 "bfin-parse.y"
+    {
+	  notethat ("LDIMMhalf: pregs_half = imm16\n");
+
+	  if (!IS_DREG ((yyvsp[-2].reg)) && !IS_PREG ((yyvsp[-2].reg)) && !IS_IREG ((yyvsp[-2].reg))
+	      && !IS_MREG ((yyvsp[-2].reg)) && !IS_BREG ((yyvsp[-2].reg)) && !IS_LREG ((yyvsp[-2].reg)))
+	    return yyerror ("Wrong register for load immediate");
+
+	  if (!IS_IMM ((yyvsp[0].expr), 16) && !IS_UIMM ((yyvsp[0].expr), 16))
+	    return yyerror ("Constant out of range");
+
+	  (yyval.instr) = LDIMMHALF_R (&(yyvsp[-2].reg), IS_H ((yyvsp[-2].reg)), 0, 0, (yyvsp[0].expr));
+	}
+    break;
+
+  case 49:
+#line 1209 "bfin-parse.y"
+    {
+	  notethat ("dsp32alu: An = 0\n");
+
+	  if (imm7 ((yyvsp[0].expr)) != 0)
+	    return yyerror ("0 expected");
+
+	  (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ((yyvsp[-1].reg)));
+	}
+    break;
+
+  case 50:
+#line 1219 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-3].reg)) && !IS_PREG ((yyvsp[-3].reg)) && !IS_IREG ((yyvsp[-3].reg))
+	      && !IS_MREG ((yyvsp[-3].reg)) && !IS_BREG ((yyvsp[-3].reg)) && !IS_LREG ((yyvsp[-3].reg)))
+	    return yyerror ("Wrong register for load immediate");
+
+	  if ((yyvsp[0].r0).r0 == 0)
+	    {
+	      /* 7 bit immediate value if possible.
+		 We will check for that constant value for efficiency
+		 If it goes to reloc, it will be 16 bit.  */
+	      if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_DREG ((yyvsp[-3].reg)))
+		{
+		  notethat ("COMPI2opD: dregs = imm7 (x) \n");
+		  (yyval.instr) = COMPI2OPD (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
+		}
+	      else if (IS_CONST ((yyvsp[-1].expr)) && IS_IMM ((yyvsp[-1].expr), 7) && IS_PREG ((yyvsp[-3].reg)))
+		{
+		  notethat ("COMPI2opP: pregs = imm7 (x)\n");
+		  (yyval.instr) = COMPI2OPP (&(yyvsp[-3].reg), imm7 ((yyvsp[-1].expr)), 0);
+		}
+	      else
+		{
+		  if (IS_CONST ((yyvsp[-1].expr)) && !IS_IMM ((yyvsp[-1].expr), 16))
+		    return yyerror ("Immediate value out of range");
+
+		  notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+		  /* reg, H, S, Z.   */
+		  (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 1, 0, (yyvsp[-1].expr));
+		} 
+	    }
+	  else
+	    {
+	      /* (z) There is no 7 bit zero extended instruction.
+	      If the expr is a relocation, generate it.   */
+
+	      if (IS_CONST ((yyvsp[-1].expr)) && !IS_UIMM ((yyvsp[-1].expr), 16))
+		return yyerror ("Immediate value out of range");
+
+	      notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+	      /* reg, H, S, Z.  */
+	      (yyval.instr) = LDIMMHALF_R5 (&(yyvsp[-3].reg), 0, 0, 1, (yyvsp[-1].expr));
+	    }
+	}
+    break;
+
+  case 51:
+#line 1264 "bfin-parse.y"
+    {
+	  if (IS_H ((yyvsp[-2].reg)))
+	    return yyerror ("Low reg expected");
+
+	  if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A0x)
+	    {
+	      notethat ("dsp32alu: dregs_lo = A0.x\n");
+	      (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), 0, 0, 0, 0, 0);
+	    }
+	  else if (IS_DREG ((yyvsp[-2].reg)) && (yyvsp[0].reg).regno == REG_A1x)
+	    {
+	      notethat ("dsp32alu: dregs_lo = A1.x\n");
+	      (yyval.instr) = DSP32ALU (10, 0, 0, &(yyvsp[-2].reg), 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 52:
+#line 1283 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
+	      (yyval.instr) = DSP32ALU (0, 0, 0, &(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-1].reg), (yyvsp[0].modcodes).s0, (yyvsp[0].modcodes).x0, (yyvsp[-2].r0).r0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 53:
+#line 1294 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ALU2op: dregs = dregs_byte\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 12 | ((yyvsp[0].r0).r0 ? 0: 1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 54:
+#line 1305 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
+	      (yyval.instr) = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 55:
+#line 1316 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-6].reg), (yyvsp[-4].reg)) && REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)) && !REG_SAME ((yyvsp[-6].reg), (yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
+	      (yyval.instr) = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 56:
+#line 1327 "bfin-parse.y"
+    {
+	  if (!IS_A1 ((yyvsp[-2].reg)) && IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: A0 -= A1\n");
+	      (yyval.instr) = DSP32ALU (11, 0, 0, 0, 0, 0, (yyvsp[0].r0).r0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 57:
+#line 1338 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 4)
+	    {
+	      notethat ("dagMODik: iregs -= 4\n");
+	      (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 3);
+	    }
+	  else if (IS_IREG ((yyvsp[-2].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 2)
+	    {
+	      notethat ("dagMODik: iregs -= 2\n");
+	      (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 1);
+	    }
+	  else
+	    return yyerror ("Register or value mismatch");
+	}
+    break;
+
+  case 58:
+#line 1354 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dagMODim: iregs += mregs (opt_brev)\n");
+	      /* i, m, op, br.  */
+	      (yyval.instr) = DAGMODIM (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 0, 1);
+	    }
+	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("PTR2op: pregs += pregs (BREV )\n");
+	      (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 5);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 59:
+#line 1371 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dagMODim: iregs -= mregs\n");
+	      (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1, 0);
+	    }
+	  else if (IS_PREG ((yyvsp[-2].reg)) && IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("PTR2op: pregs -= pregs\n");
+	      (yyval.instr) = PTR2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 60:
+#line 1387 "bfin-parse.y"
+    {
+	  if (!IS_A1 ((yyvsp[-3].reg)) && IS_A1 ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32alu: A0 += A1 (W32)\n");
+	      (yyval.instr) = DSP32ALU (11, 0, 0, 0, 0, 0, (yyvsp[0].r0).r0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 61:
+#line 1398 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-2].reg)) && IS_MREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dagMODim: iregs += mregs\n");
+	      (yyval.instr) = DAGMODIM (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0, 0);
+	    }
+	  else
+	    return yyerror ("iregs += mregs expected");
+	}
+    break;
+
+  case 62:
+#line 1409 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-2].reg)))
+	    {
+	      if (EXPR_VALUE ((yyvsp[0].expr)) == 4)
+		{
+		  notethat ("dagMODik: iregs += 4\n");
+		  (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 2);
+		}
+	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+		{
+		  notethat ("dagMODik: iregs += 2\n");
+		  (yyval.instr) = DAGMODIK (&(yyvsp[-2].reg), 0);
+		}
+	      else
+		return yyerror ("iregs += [ 2 | 4 ");
+	    }
+	  else if (IS_PREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
+	    {
+	      notethat ("COMPI2opP: pregs += imm7\n");
+	      (yyval.instr) = COMPI2OPP (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
+	    }
+	  else if (IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 7))
+	    {
+	      notethat ("COMPI2opD: dregs += imm7\n");
+	      (yyval.instr) = COMPI2OPD (&(yyvsp[-2].reg), imm7 ((yyvsp[0].expr)), 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 63:
+#line 1440 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ALU2op: dregs *= dregs\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 64:
+#line 1451 "bfin-parse.y"
+    {
+	  if (!valid_dreg_pair (&(yyvsp[-8].reg), (yyvsp[-6].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&(yyvsp[-4].reg), (yyvsp[-2].expr)))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
+	      (yyval.instr) = DSP32ALU (18, 0, 0, 0, &(yyvsp[-8].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0, 0);
+	    }
+	}
+    break;
+
+  case 65:
+#line 1464 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-10].reg), (yyvsp[-9].reg)) && REG_SAME ((yyvsp[-4].reg), (yyvsp[-3].reg)) && !REG_SAME ((yyvsp[-10].reg), (yyvsp[-4].reg)))
+	    {
+	      notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
+	      (yyval.instr) = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 66:
+#line 1475 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg))
+	      && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
+	    {
+	      if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
+		{
+		  notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
+		  (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 4);
+		}
+	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+		{
+		  notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
+		  (yyval.instr) = ALU2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 5);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg))
+		   && REG_SAME ((yyvsp[-8].reg), (yyvsp[-5].reg)))
+	    {
+	      if (EXPR_VALUE ((yyvsp[0].expr)) == 1)
+		{
+		  notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
+		  (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 6);
+		}
+	      else if (EXPR_VALUE ((yyvsp[0].expr)) == 2)
+		{
+		  notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
+		  (yyval.instr) = PTR2OP (&(yyvsp[-8].reg), &(yyvsp[-3].reg), 7);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 67:
+#line 1514 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("COMP3op: dregs = dregs | dregs\n");
+	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 3);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 68:
+#line 1524 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("COMP3op: dregs = dregs ^ dregs\n");
+	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 4);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 69:
+#line 1534 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+		{
+		  notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
+		  (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 6);
+		}
+	      else if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+		{
+		  notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
+		  (yyval.instr) = COMP3OP (&(yyvsp[-8].reg), &(yyvsp[-6].reg), &(yyvsp[-3].reg), 7);
+		}
+	      else
+		  return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 70:
+#line 1554 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
+	    {
+	      notethat ("CCflag: CC = A0 == A1\n");
+	      (yyval.instr) = CCFLAG (0, 0, 5, 0, 0);
+	    }
+	  else
+	    return yyerror ("CC register expected");
+	}
+    break;
+
+  case 71:
+#line 1564 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
+	    {
+	      notethat ("CCflag: CC = A0 < A1\n");
+	      (yyval.instr) = CCFLAG (0, 0, 6, 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 72:
+#line 1574 "bfin-parse.y"
+    {
+	  if (REG_CLASS((yyvsp[-3].reg)) == REG_CLASS((yyvsp[-1].reg)))
+	    {
+	      notethat ("CCflag: CC = dpregs < dpregs\n");
+	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Compare only of same register class");
+	}
+    break;
+
+  case 73:
+#line 1584 "bfin-parse.y"
+    {
+	  if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
+	      || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
+	    {
+	      notethat ("CCflag: CC = dpregs < (u)imm3\n");
+	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), (yyvsp[0].r0).r0, 1, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Bad constant value");
+	}
+    break;
+
+  case 74:
+#line 1595 "bfin-parse.y"
+    {
+	  if (REG_CLASS((yyvsp[-2].reg)) == REG_CLASS((yyvsp[0].reg)))
+	    {
+	      notethat ("CCflag: CC = dpregs == dpregs\n");
+	      (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), (yyvsp[0].reg).regno & CODE_MASK, 0, 0, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
+	    } 
+	}
+    break;
+
+  case 75:
+#line 1603 "bfin-parse.y"
+    {
+	  if (IS_IMM ((yyvsp[0].expr), 3))
+	    {
+	      notethat ("CCflag: CC = dpregs == imm3\n");
+	      (yyval.instr) = CCFLAG (&(yyvsp[-2].reg), imm3 ((yyvsp[0].expr)), 0, 1, IS_PREG ((yyvsp[-2].reg)) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Bad constant range");
+	}
+    break;
+
+  case 76:
+#line 1613 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-2].reg), (yyvsp[0].reg)))
+	    {
+	      notethat ("CCflag: CC = A0 <= A1\n");
+	      (yyval.instr) = CCFLAG (0, 0, 7, 0, 0);
+	    }
+	  else
+	    return yyerror ("CC register expected");
+	}
+    break;
+
+  case 77:
+#line 1623 "bfin-parse.y"
+    {
+	  if (REG_CLASS((yyvsp[-3].reg)) == REG_CLASS((yyvsp[-1].reg)))
+	    {
+	      notethat ("CCflag: CC = pregs <= pregs (..)\n");
+	      (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK,
+			   1 + (yyvsp[0].r0).r0, 0, IS_PREG ((yyvsp[-3].reg)) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Compare only of same register class");
+	}
+    break;
+
+  case 78:
+#line 1634 "bfin-parse.y"
+    {
+	  if (((yyvsp[0].r0).r0 == 1 && IS_IMM ((yyvsp[-1].expr), 3))
+	      || ((yyvsp[0].r0).r0 == 3 && IS_UIMM ((yyvsp[-1].expr), 3)))
+	    {
+	      if (IS_DREG ((yyvsp[-3].reg)))
+		{
+		  notethat ("CCflag: CC = dregs <= (u)imm3\n");
+		  /*    x       y     opc     I     G   */
+		  (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), 1 + (yyvsp[0].r0).r0, 1, 0);
+		}
+	      else if (IS_PREG ((yyvsp[-3].reg)))
+		{
+		  notethat ("CCflag: CC = pregs <= (u)imm3\n");
+		  /*    x       y     opc     I     G   */
+		  (yyval.instr) = CCFLAG (&(yyvsp[-3].reg), imm3 ((yyvsp[-1].expr)), 1 + (yyvsp[0].r0).r0, 1, 1);
+		}
+	      else
+		return yyerror ("Dreg or Preg expected");
+	    }
+	  else
+	    return yyerror ("Bad constant value");
+	}
+    break;
+
+  case 79:
+#line 1658 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("COMP3op: dregs = dregs & dregs\n");
+	      (yyval.instr) = COMP3OP (&(yyvsp[-4].reg), &(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 80:
+#line 1669 "bfin-parse.y"
+    {
+	  notethat ("CC2stat operation\n");
+	  (yyval.instr) = bfin_gen_cc2stat ((yyvsp[0].modcodes).r0, (yyvsp[0].modcodes).x0, (yyvsp[0].modcodes).s0);
+	}
+    break;
+
+  case 81:
+#line 1675 "bfin-parse.y"
+    {
+	  if (IS_ALLREG ((yyvsp[-2].reg)) && IS_ALLREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("REGMV: allregs = allregs\n");
+	      (yyval.instr) = bfin_gen_regmv (&(yyvsp[0].reg), &(yyvsp[-2].reg));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 82:
+#line 1686 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("CC2dreg: CC = dregs\n");
+	      (yyval.instr) = bfin_gen_cc2dreg (1, &(yyvsp[0].reg));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 83:
+#line 1697 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("CC2dreg: dregs = CC\n");
+	      (yyval.instr) = bfin_gen_cc2dreg (0, &(yyvsp[-2].reg));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 84:
+#line 1708 "bfin-parse.y"
+    {
+	  notethat ("CC2dreg: CC =! CC\n");
+	  (yyval.instr) = bfin_gen_cc2dreg (3, 0);
+	}
+    break;
+
+  case 85:
+#line 1716 "bfin-parse.y"
+    {
+	  notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
+
+	  if (!IS_H ((yyvsp[-3].reg)) && (yyvsp[0].mod).MM)
+	    return yyerror ("(M) not allowed with MAC0");
+
+	  if (IS_H ((yyvsp[-3].reg)))
+	    {
+	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
+			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
+	    }
+	  else
+	    {
+	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 0,
+			      0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 
+			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
+		}	
+	}
+    break;
+
+  case 86:
+#line 1737 "bfin-parse.y"
+    {
+	  /* Odd registers can use (M).  */
+	  if (!IS_DREG ((yyvsp[-3].reg)))
+	    return yyerror ("Dreg expected");
+
+	  if (!IS_EVEN ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
+
+	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
+			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 0, 0,
+			      &(yyvsp[-3].reg), 0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 0);
+	    }
+	  else if ((yyvsp[0].mod).MM == 0)
+	    {
+	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
+	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 0, 1,
+			      0, 0, IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), 
+			      &(yyvsp[-3].reg),  0, &(yyvsp[-1].macfunc).s0, &(yyvsp[-1].macfunc).s1, 1);
+	    }
+	  else
+	    return yyerror ("Register or mode mismatch");
+	}
+    break;
+
+  case 87:
+#line 1763 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg))) 
+	    return yyerror ("Dregs expected");
+
+	  if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
+	    return -1;
+
+	  if (IS_H ((yyvsp[-8].reg)) && !IS_H ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
+		       "dregs_lo = multiply_halfregs opt_mode\n");
+	      (yyval.instr) = DSP32MULT (0, (yyvsp[-5].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+			      IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+	    }
+	  else if (!IS_H ((yyvsp[-8].reg)) && IS_H ((yyvsp[-3].reg)) && (yyvsp[-5].mod).MM == 0)
+	    {
+	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 0,
+			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
+			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+	    }
+	  else
+	    return yyerror ("Multfunc Register or mode mismatch");
+	}
+    break;
+
+  case 88:
+#line 1789 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-8].reg)) || !IS_DREG ((yyvsp[-3].reg))) 
+	    return yyerror ("Dregs expected");
+
+	  if (check_multiply_halfregs (&(yyvsp[-6].macfunc), &(yyvsp[-1].macfunc)) < 0)
+	    return -1;
+
+	  notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
+		   "dregs = multiply_halfregs opt_mode\n");
+	  if (IS_EVEN ((yyvsp[-8].reg)))
+	    {
+	      if ((yyvsp[-3].reg).regno - (yyvsp[-8].reg).regno != 1 || (yyvsp[-5].mod).MM != 0)
+		return yyerror ("Dest registers or mode mismatch");
+
+	      /*   op1       MM      mmod  */
+	      (yyval.instr) = DSP32MULT (0, 0, (yyvsp[0].mod).mod, 1, 1,
+			      IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1), IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1),
+			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+	      
+	    }
+	  else
+	    {
+	      if ((yyvsp[-8].reg).regno - (yyvsp[-3].reg).regno != 1)
+		return yyerror ("Dest registers mismatch");
+	      
+	      (yyval.instr) = DSP32MULT (0, (yyvsp[0].mod).MM, (yyvsp[0].mod).mod, 1, 1,
+			      IS_H ((yyvsp[-6].macfunc).s0), IS_H ((yyvsp[-6].macfunc).s1), IS_H ((yyvsp[-1].macfunc).s0), IS_H ((yyvsp[-1].macfunc).s1),
+			      &(yyvsp[-8].reg), 0, &(yyvsp[-6].macfunc).s0, &(yyvsp[-6].macfunc).s1, 1);
+	    }
+	}
+    break;
+
+  case 89:
+#line 1823 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_DREG ((yyvsp[0].reg)) && !IS_H ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 0, IS_A1 ((yyvsp[-4].reg)));
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 90:
+#line 1837 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-6].reg), (yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 91:
+#line 1848 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
+	      (yyval.instr) = DSP32SHIFTIMM (3, 0, imm5 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+    break;
+
+  case 92:
+#line 1862 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      if ((yyvsp[0].modcodes).r0)
+		{
+		  /*  Vector?  */
+		  notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
+		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), imm4 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
+		}
+	      else
+		{
+		  notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
+		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0 ? 1 : 2, 0);
+		}
+	    }
+	  else if ((yyvsp[0].modcodes).s0 == 0 && IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      if (EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+		{
+		  notethat ("PTR2op: pregs = pregs << 2\n");
+		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 1);
+		}
+	      else if (EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+		{
+		  notethat ("COMP3op: pregs = pregs << 1\n");
+		  (yyval.instr) = COMP3OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), &(yyvsp[-3].reg), 5);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+    break;
+
+  case 93:
+#line 1896 "bfin-parse.y"
+    {
+	  if (IS_UIMM ((yyvsp[0].expr), 4))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+	      (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-4].reg), imm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+    break;
+
+  case 94:
+#line 1906 "bfin-parse.y"
+    {
+	  if (IS_UIMM ((yyvsp[-1].expr), 4))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+	      (yyval.instr) = DSP32SHIFTIMM (0x0, &(yyvsp[-5].reg), imm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+    break;
+
+  case 95:
+#line 1916 "bfin-parse.y"
+    {
+	  int op;
+
+	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-1].reg)))
+	    {
+	      if ((yyvsp[0].modcodes).r0)
+		{
+		  op = 1;
+		  notethat ("dsp32shift: dregs = ASHIFT dregs BY "
+			   "dregs_lo (V, .)\n");
+		}
+	      else
+		{
+		  
+		  op = 2;
+		  notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
+		}
+	      (yyval.instr) = DSP32SHIFT (op, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 96:
+#line 1941 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-8].reg)) && IS_DREG_L ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
+	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+    break;
+
+  case 97:
+#line 1953 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
+	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+	    }
+	  else if (IS_DREG_L ((yyvsp[-7].reg)) && IS_DREG_H ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
+	      (yyval.instr) = DSP32SHIFT (7, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 3, 0);
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+    break;
+
+  case 98:
+#line 1971 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
+	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 99:
+#line 1982 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-10].reg)) && IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
+	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-10].reg), &(yyvsp[-4].reg), &(yyvsp[-6].reg), 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 100:
+#line 1993 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG_L ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
+	      (yyval.instr) = DSP32SHIFT (10, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 101:
+#line 2004 "bfin-parse.y"
+    {
+	  if (!REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
+	      (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 0, IS_A1 ((yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Shift value range error");
+	}
+    break;
+
+  case 102:
+#line 2017 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 1, IS_A1 ((yyvsp[-4].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 103:
+#line 2028 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (0, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-5].reg), (yyvsp[-2].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 104:
+#line 2039 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG_L ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
+	      (yyval.instr) = DSP32SHIFT ((yyvsp[0].r0).r0 ? 1: 2, &(yyvsp[-6].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 105:
+#line 2050 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 106:
+#line 2061 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-3].reg), (yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6) >= 0)
+	    {
+	      notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
+	      (yyval.instr) = DSP32SHIFTIMM (3, 0, -imm6 ((yyvsp[0].expr)), 0, 1, IS_A1 ((yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Accu register expected");
+	}
+    break;
+
+  case 107:
+#line 2072 "bfin-parse.y"
+    {
+	  if ((yyvsp[0].r0).r0 == 1)
+	    {
+	      if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+		{
+		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
+		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	  else
+	    {
+	      if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+		{
+		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
+		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -imm6 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), 2, 0);
+		}
+	      else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 2)
+		{
+		  notethat ("PTR2op: pregs = pregs >> 2\n");
+		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 3);
+		}
+	      else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)) && EXPR_VALUE ((yyvsp[-1].expr)) == 1)
+		{
+		  notethat ("PTR2op: pregs = pregs >> 1\n");
+		  (yyval.instr) = PTR2OP (&(yyvsp[-5].reg), &(yyvsp[-3].reg), 4);
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	}
+    break;
+
+  case 108:
+#line 2105 "bfin-parse.y"
+    {
+	  if (IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
+	      (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-4].reg), -uimm5 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 2, HL2 ((yyvsp[-4].reg), (yyvsp[-2].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 109:
+#line 2115 "bfin-parse.y"
+    {
+	  if (IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
+	      (yyval.instr) = DSP32SHIFTIMM (0, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg),
+				  (yyvsp[0].modcodes).s0, HL2 ((yyvsp[-5].reg), (yyvsp[-3].reg)));
+	    }
+	  else
+	    return yyerror ("Register or modifier mismatch");
+	}
+    break;
+
+  case 110:
+#line 2128 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      if ((yyvsp[0].modcodes).r0)
+		{
+		  /* Vector?  */
+		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
+		  (yyval.instr) = DSP32SHIFTIMM (1, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+		}
+	      else
+		{
+		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
+		  (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), -uimm5 ((yyvsp[-1].expr)), &(yyvsp[-3].reg), (yyvsp[0].modcodes).s0, 0);
+		}
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 111:
+#line 2148 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = ONES dregs\n");
+	      (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 112:
+#line 2159 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
+	      (yyval.instr) = DSP32SHIFT (4, &(yyvsp[-7].reg), &(yyvsp[-1].reg), &(yyvsp[-3].reg), HL2 ((yyvsp[-3].reg), (yyvsp[-1].reg)), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 113:
+#line 2170 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-9].reg))
+	      && (yyvsp[-3].reg).regno == REG_A0
+	      && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
+	      (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 114:
+#line 2183 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-9].reg))
+	      && (yyvsp[-3].reg).regno == REG_A0
+	      && IS_DREG ((yyvsp[-1].reg)) && !IS_H ((yyvsp[-9].reg)) && !IS_A1 ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
+	      (yyval.instr) = DSP32SHIFT (11, &(yyvsp[-9].reg), &(yyvsp[-1].reg), 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 115:
+#line 2196 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-11].reg)) && !IS_H ((yyvsp[-11].reg)) && !REG_SAME ((yyvsp[-5].reg), (yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
+	      (yyval.instr) = DSP32SHIFT (12, &(yyvsp[-11].reg), 0, 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 116:
+#line 2207 "bfin-parse.y"
+    {
+	  if (REG_SAME ((yyvsp[-4].reg), (yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (3, 0, &(yyvsp[0].reg), 0, 2, IS_A1 ((yyvsp[-4].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 117:
+#line 2218 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_DREG_L ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (2, &(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-2].reg), 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 118:
+#line 2229 "bfin-parse.y"
+    {
+	  if (IS_IMM ((yyvsp[0].expr), 6))
+	    {
+	      notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
+	      (yyval.instr) = DSP32SHIFTIMM (3, 0, imm6 ((yyvsp[0].expr)), 0, 2, IS_A1 ((yyvsp[-4].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 119:
+#line 2240 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_DREG ((yyvsp[-2].reg)) && IS_IMM ((yyvsp[0].expr), 6))
+	    {
+	      (yyval.instr) = DSP32SHIFTIMM (2, &(yyvsp[-5].reg), imm6 ((yyvsp[0].expr)), &(yyvsp[-2].reg), 3, IS_A1 ((yyvsp[-5].reg)));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 120:
+#line 2250 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
+	      (yyval.instr) = DSP32SHIFT (6, &(yyvsp[-3].reg), 0, 0, IS_A1 ((yyvsp[0].reg)), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 121:
+#line 2261 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
+	      (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 122:
+#line 2272 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
+	      (yyval.instr) = DSP32SHIFT (5, &(yyvsp[-3].reg), 0, &(yyvsp[0].reg), 1 + IS_H ((yyvsp[0].reg)), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 123:
+#line 2284 "bfin-parse.y"
+    {
+	  if (IS_DREG_L ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
+	      (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-6].reg), 0, &(yyvsp[-2].reg), ((yyvsp[0].r0).r0 ? 0 : 1), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 124:
+#line 2295 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
+	      (yyval.instr) = DSP32SHIFT (9, &(yyvsp[-8].reg), &(yyvsp[-2].reg), &(yyvsp[-4].reg), 2 | ((yyvsp[0].r0).r0 ? 0 : 1), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 125:
+#line 2306 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-6].reg)) && IS_DREG ((yyvsp[-4].reg)) && !IS_A1 ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
+	      (yyval.instr) = DSP32SHIFT (8, 0, &(yyvsp[-6].reg), &(yyvsp[-4].reg), (yyvsp[0].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 126:
+#line 2317 "bfin-parse.y"
+    {
+	  if (!IS_A1 ((yyvsp[-8].reg)) && !IS_A1 ((yyvsp[-5].reg)) && IS_A1 ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
+	      (yyval.instr) = DSP32SHIFT (12, 0, 0, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 127:
+#line 2330 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 4);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 128:
+#line 2342 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 129:
+#line 2354 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 130:
+#line 2365 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch or value error");
+	}
+    break;
+
+  case 131:
+#line 2376 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_UIMM ((yyvsp[-1].expr), 5))
+	    {
+	      notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-3].reg), uimm5 ((yyvsp[-1].expr)), 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch or value error");
+	}
+    break;
+
+  case 132:
+#line 2387 "bfin-parse.y"
+    {
+	  if ((IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg)))
+	      && (IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg))))
+	    {
+	      notethat ("ccMV: IF ! CC gregs = gregs\n");
+	      (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 133:
+#line 2399 "bfin-parse.y"
+    {
+	  if ((IS_DREG ((yyvsp[0].reg)) || IS_PREG ((yyvsp[0].reg)))
+	      && (IS_DREG ((yyvsp[-2].reg)) || IS_PREG ((yyvsp[-2].reg))))
+	    {
+	      notethat ("ccMV: IF CC gregs = gregs\n");
+	      (yyval.instr) = CCMV (&(yyvsp[0].reg), &(yyvsp[-2].reg), 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 134:
+#line 2411 "bfin-parse.y"
+    {
+	  if (IS_PCREL10 ((yyvsp[0].expr)))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      (yyval.instr) = BRCC (0, 0, (yyvsp[0].expr));
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+    break;
+
+  case 135:
+#line 2422 "bfin-parse.y"
+    {
+	  if (IS_PCREL10 ((yyvsp[-3].expr)))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      (yyval.instr) = BRCC (0, 1, (yyvsp[-3].expr));
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+    break;
+
+  case 136:
+#line 2433 "bfin-parse.y"
+    {
+	  if (IS_PCREL10 ((yyvsp[0].expr)))
+	    {
+	      notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
+	      (yyval.instr) = BRCC (1, 0, (yyvsp[0].expr));
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+    break;
+
+  case 137:
+#line 2444 "bfin-parse.y"
+    {
+	  if (IS_PCREL10 ((yyvsp[-3].expr)))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      (yyval.instr) = BRCC (1, 1, (yyvsp[-3].expr));
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+    break;
+
+  case 138:
+#line 2454 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: NOP\n");
+	  (yyval.instr) = PROGCTRL (0, 0);
+	}
+    break;
+
+  case 139:
+#line 2460 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: RTS\n");
+	  (yyval.instr) = PROGCTRL (1, 0);
+	}
+    break;
+
+  case 140:
+#line 2466 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: RTI\n");
+	  (yyval.instr) = PROGCTRL (1, 1);
+	}
+    break;
+
+  case 141:
+#line 2472 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: RTX\n");
+	  (yyval.instr) = PROGCTRL (1, 2);
+	}
+    break;
+
+  case 142:
+#line 2478 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: RTN\n");
+	  (yyval.instr) = PROGCTRL (1, 3);
+	}
+    break;
+
+  case 143:
+#line 2484 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: RTE\n");
+	  (yyval.instr) = PROGCTRL (1, 4);
+	}
+    break;
+
+  case 144:
+#line 2490 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: IDLE\n");
+	  (yyval.instr) = PROGCTRL (2, 0);
+	}
+    break;
+
+  case 145:
+#line 2496 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: CSYNC\n");
+	  (yyval.instr) = PROGCTRL (2, 3);
+	}
+    break;
+
+  case 146:
+#line 2502 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: SSYNC\n");
+	  (yyval.instr) = PROGCTRL (2, 4);
+	}
+    break;
+
+  case 147:
+#line 2508 "bfin-parse.y"
+    {
+	  notethat ("ProgCtrl: EMUEXCPT\n");
+	  (yyval.instr) = PROGCTRL (2, 5);
+	}
+    break;
+
+  case 148:
+#line 2514 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ProgCtrl: CLI dregs\n");
+	      (yyval.instr) = PROGCTRL (3, (yyvsp[0].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Dreg expected for CLI");
+	}
+    break;
+
+  case 149:
+#line 2525 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ProgCtrl: STI dregs\n");
+	      (yyval.instr) = PROGCTRL (4, (yyvsp[0].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Dreg expected for STI");
+	}
+    break;
+
+  case 150:
+#line 2536 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ProgCtrl: JUMP (pregs )\n");
+	      (yyval.instr) = PROGCTRL (5, (yyvsp[-1].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect jump");
+	}
+    break;
+
+  case 151:
+#line 2547 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ProgCtrl: CALL (pregs )\n");
+	      (yyval.instr) = PROGCTRL (6, (yyvsp[-1].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect call");
+	}
+    break;
+
+  case 152:
+#line 2558 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ProgCtrl: CALL (PC + pregs )\n");
+	      (yyval.instr) = PROGCTRL (7, (yyvsp[-1].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect call");
+	}
+    break;
+
+  case 153:
+#line 2569 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ProgCtrl: JUMP (PC + pregs )\n");
+	      (yyval.instr) = PROGCTRL (8, (yyvsp[-1].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect jump");
+	}
+    break;
+
+  case 154:
+#line 2580 "bfin-parse.y"
+    {
+	  if (IS_UIMM ((yyvsp[0].expr), 4))
+	    {
+	      notethat ("ProgCtrl: RAISE uimm4\n");
+	      (yyval.instr) = PROGCTRL (9, uimm4 ((yyvsp[0].expr)));
+	    }
+	  else
+	    return yyerror ("Bad value for RAISE");
+	}
+    break;
+
+  case 155:
+#line 2591 "bfin-parse.y"
+    {
+		notethat ("ProgCtrl: EMUEXCPT\n");
+		(yyval.instr) = PROGCTRL (10, uimm4 ((yyvsp[0].expr)));
+	}
+    break;
+
+  case 156:
+#line 2597 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("ProgCtrl: TESTSET (pregs )\n");
+	      (yyval.instr) = PROGCTRL (11, (yyvsp[-1].reg).regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Preg expected");
+	}
+    break;
+
+  case 157:
+#line 2608 "bfin-parse.y"
+    {
+	  if (IS_PCREL12 ((yyvsp[0].expr)))
+	    {
+	      notethat ("UJUMP: JUMP pcrel12\n");
+	      (yyval.instr) = UJUMP ((yyvsp[0].expr));
+	    }
+	  else
+	    return yyerror ("Bad value for relative jump");
+	}
+    break;
+
+  case 158:
+#line 2619 "bfin-parse.y"
+    {
+	  if (IS_PCREL12 ((yyvsp[0].expr)))
+	    {
+	      notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
+	      (yyval.instr) = UJUMP((yyvsp[0].expr));
+	    }
+	  else
+	    return yyerror ("Bad value for relative jump");
+	}
+    break;
+
+  case 159:
+#line 2630 "bfin-parse.y"
+    {
+	  if (IS_PCREL24 ((yyvsp[0].expr)))
+	    {
+	      notethat ("CALLa: jump.l pcrel24\n");
+	      (yyval.instr) = CALLA ((yyvsp[0].expr), 0);
+	    }
+	  else
+	    return yyerror ("Bad value for long jump");
+	}
+    break;
+
+  case 160:
+#line 2641 "bfin-parse.y"
+    {
+	  if (IS_PCREL24 ((yyvsp[0].expr)))
+	    {
+	      notethat ("CALLa: jump.l pcrel24\n");
+	      (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
+	    }
+	  else
+	    return yyerror ("Bad value for long jump");
+	}
+    break;
+
+  case 161:
+#line 2652 "bfin-parse.y"
+    {
+	  if (IS_PCREL24 ((yyvsp[0].expr)))
+	    {
+	      notethat ("CALLa: CALL pcrel25m2\n");
+	      (yyval.instr) = CALLA ((yyvsp[0].expr), 1);
+	    }
+	  else
+	    return yyerror ("Bad call address");
+	}
+    break;
+
+  case 162:
+#line 2662 "bfin-parse.y"
+    {
+	  if (IS_PCREL24 ((yyvsp[0].expr)))
+	    {
+	      notethat ("CALLa: CALL pcrel25m2\n");
+	      (yyval.instr) = CALLA ((yyvsp[0].expr), 2);
+	    }
+	  else
+	    return yyerror ("Bad call address");
+	}
+    break;
+
+  case 163:
+#line 2675 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 8);
+	  else
+	    return yyerror ("Bad registers for DIVQ");
+	}
+    break;
+
+  case 164:
+#line 2683 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[-1].reg), 9);
+	  else
+	    return yyerror ("Bad registers for DIVS");
+	}
+    break;
+
+  case 165:
+#line 2691 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[-1].reg)))
+	    {
+	      if ((yyvsp[0].modcodes).r0 == 0 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 0)
+		{
+		  notethat ("ALU2op: dregs = - dregs\n");
+		  (yyval.instr) = ALU2OP (&(yyvsp[-4].reg), &(yyvsp[-1].reg), 14);
+		}
+	      else if ((yyvsp[0].modcodes).r0 == 1 && (yyvsp[0].modcodes).s0 == 0 && (yyvsp[0].modcodes).aop == 3)
+		{
+		  notethat ("dsp32alu: dregs = - dregs (.)\n");
+		  (yyval.instr) = DSP32ALU (15, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
+		}
+	      else
+		{
+		  notethat ("dsp32alu: dregs = - dregs (.)\n");
+		  (yyval.instr) = DSP32ALU (7, 0, 0, &(yyvsp[-4].reg), &(yyvsp[-1].reg), 0, (yyvsp[0].modcodes).s0, 0, 3);
+		}
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 166:
+#line 2715 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-3].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ALU2op: dregs = ~dregs\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-3].reg), &(yyvsp[0].reg), 15);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 167:
+#line 2726 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ALU2op: dregs >>= dregs\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 1);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 168:
+#line 2737 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("LOGI2op: dregs >>= uimm5\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 6);
+	    }
+	  else
+	    return yyerror ("Dregs expected or value error");
+	}
+    break;
+
+  case 169:
+#line 2748 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ALU2op: dregs >>>= dregs\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 170:
+#line 2759 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("ALU2op: dregs <<= dregs\n");
+	      (yyval.instr) = ALU2OP (&(yyvsp[-2].reg), &(yyvsp[0].reg), 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 171:
+#line 2770 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("LOGI2op: dregs <<= uimm5\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 7);
+	    }
+	  else
+	    return yyerror ("Dregs expected or const value error");
+	}
+    break;
+
+  case 172:
+#line 2782 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_UIMM ((yyvsp[0].expr), 5))
+	    {
+	      notethat ("LOGI2op: dregs >>>= uimm5\n");
+	      (yyval.instr) = LOGI2OP ((yyvsp[-2].reg), uimm5 ((yyvsp[0].expr)), 5);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 173:
+#line 2795 "bfin-parse.y"
+    {
+	  notethat ("CaCTRL: FLUSH [ pregs ]\n");
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 2);
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 174:
+#line 2804 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 2);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 175:
+#line 2815 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 176:
+#line 2826 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 177:
+#line 2838 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("CaCTRL: IFLUSH [ pregs ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 3);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 178:
+#line 2849 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 3);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+    break;
+
+  case 179:
+#line 2860 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("CaCTRL: PREFETCH [ pregs ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[-1].reg), 0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for PREFETCH");
+	}
+    break;
+
+  case 180:
+#line 2871 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
+	      (yyval.instr) = CACTRL (&(yyvsp[0].reg), 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for PREFETCH");
+	}
+    break;
+
+  case 181:
+#line 2885 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
+	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 2, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+    break;
+
+  case 182:
+#line 2897 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-5].reg)) && IS_RANGE(16, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 1) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
+	      if ((yyvsp[-4].r0).r0)
+		neg_value ((yyvsp[-3].expr));
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 2, 0, (yyvsp[-3].expr));
+	    }
+	  else
+	    return yyerror ("Register mismatch or const size wrong");
+	}
+    break;
+
+  case 183:
+#line 2912 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-5].reg)) && IS_URANGE (4, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 2) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
+	      (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), (yyvsp[-3].expr), 1, 1);
+	    }
+	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_RANGE(16, (yyvsp[-3].expr), (yyvsp[-4].r0).r0, 2) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
+	      if ((yyvsp[-4].r0).r0)
+		neg_value ((yyvsp[-3].expr));
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 1, 0, (yyvsp[-3].expr));
+	    }
+	  else
+	    return yyerror ("Bad register(s) or wrong constant size");
+	}
+    break;
+
+  case 184:
+#line 2931 "bfin-parse.y"
+    {
+	  if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
+	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1, 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for STORE");
+	}
+    break;
+
+  case 185:
+#line 2942 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-4].reg)))
+	    {
+	      notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
+	      (yyval.instr) = DSPLDST (&(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
+	    }
+	  else if ((yyvsp[-3].modcodes).x0 == 2 && IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[0].reg), &(yyvsp[-4].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
+	      
+	    }
+	  else
+	    return yyerror ("Bad register(s) for STORE");
+	}
+    break;
+
+  case 186:
+#line 2960 "bfin-parse.y"
+    {
+	  Expr_Node *tmp = (yyvsp[-3].expr);
+	  int ispreg = IS_PREG ((yyvsp[0].reg));
+
+	  if (!IS_PREG ((yyvsp[-5].reg)))
+	    return yyerror ("Preg expected for indirect");
+
+	  if (!IS_DREG ((yyvsp[0].reg)) && !ispreg)
+	    return yyerror ("Bad source register for STORE");
+
+	  if ((yyvsp[-4].r0).r0)
+	    tmp = unary (Expr_Op_Type_NEG, tmp);
+
+	  if (in_range_p (tmp, 0, 63, 3))
+	    {
+	      notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
+	      (yyval.instr) = LDSTII (&(yyvsp[-5].reg), &(yyvsp[0].reg), tmp, 1, ispreg ? 3 : 0);
+	    }
+	  else if ((yyvsp[-5].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+	    {
+	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+	      tmp = unary (Expr_Op_Type_NEG, tmp);
+	      (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[0].reg), 1);
+	    }
+	  else if (in_range_p (tmp, -131072, 131071, 3))
+	    {
+	      notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-5].reg), &(yyvsp[0].reg), 1, 0, ispreg ? 1: 0, tmp);
+	    }
+	  else
+	    return yyerror ("Displacement out of range for store");
+	}
+    break;
+
+  case 187:
+#line 2994 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_URANGE (4, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 2))
+	    {
+	      notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
+	      (yyval.instr) = LDSTII (&(yyvsp[-4].reg), &(yyvsp[-8].reg), (yyvsp[-2].expr), 0, 1 << (yyvsp[0].r0).r0);
+	    }
+	  else if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_RANGE(16, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 2))
+	    {
+	      notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
+	      if ((yyvsp[-3].r0).r0)
+		neg_value ((yyvsp[-2].expr));
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 1, (yyvsp[0].r0).r0, (yyvsp[-2].expr));
+	    }
+	  else
+	    return yyerror ("Bad register or constant for LOAD");
+	}
+    break;
+
+  case 188:
+#line 3012 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dspLDST: dregs_half = W [ iregs ]\n");
+	      (yyval.instr) = DSPLDST(&(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), &(yyvsp[-6].reg), (yyvsp[-1].modcodes).x0, 0);
+	    }
+	  else if ((yyvsp[-1].modcodes).x0 == 2 && IS_DREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-2].reg), &(yyvsp[-6].reg), &(yyvsp[-2].reg), 1 + IS_H ((yyvsp[-6].reg)), 0);
+	    }
+	  else
+	    return yyerror ("Bad register or post_op for LOAD");
+	}
+    break;
+
+  case 189:
+#line 3029 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
+	      (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 1, (yyvsp[0].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+    break;
+
+  case 190:
+#line 3040 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_PREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-4].reg), &(yyvsp[-8].reg), &(yyvsp[-2].reg), 3, (yyvsp[0].r0).r0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+    break;
+
+  case 191:
+#line 3051 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-7].reg), &(yyvsp[-1].reg), 1 + IS_H ((yyvsp[-7].reg)), 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+    break;
+
+  case 192:
+#line 3062 "bfin-parse.y"
+    {
+	  if (IS_IREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
+	      (yyval.instr) = DSPLDST(&(yyvsp[-4].reg), 0, &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 1);
+	    }
+	  else if (IS_PREG ((yyvsp[-4].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDST: [ pregs <post_op> ] = dregs\n");
+	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 0, 1);
+	    }
+	  else if (IS_PREG ((yyvsp[-4].reg)) && IS_PREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LDST: [ pregs <post_op> ] = pregs\n");
+	      (yyval.instr) = LDST (&(yyvsp[-4].reg), &(yyvsp[0].reg), (yyvsp[-3].modcodes).x0, 0, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+    break;
+
+  case 193:
+#line 3083 "bfin-parse.y"
+    {
+	  if (! IS_DREG ((yyvsp[0].reg)))
+	    return yyerror ("Expected Dreg for last argument");
+
+	  if (IS_IREG ((yyvsp[-5].reg)) && IS_MREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
+	      (yyval.instr) = DSPLDST(&(yyvsp[-5].reg), (yyvsp[-3].reg).regno & CODE_MASK, &(yyvsp[0].reg), 3, 1);
+	    }
+	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+    break;
+
+  case 194:
+#line 3102 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[0].reg)))
+	    return yyerror ("Expect Dreg as last argument");
+	  if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-5].reg), &(yyvsp[0].reg), &(yyvsp[-3].reg), 1 + IS_H ((yyvsp[0].reg)), 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+    break;
+
+  case 195:
+#line 3115 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-8].reg)) && IS_PREG ((yyvsp[-4].reg)) && IS_RANGE(16, (yyvsp[-2].expr), (yyvsp[-3].r0).r0, 1))
+	    {
+	      notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
+		       (yyvsp[0].r0).r0 ? 'X' : 'Z');
+	      if ((yyvsp[-3].r0).r0)
+		neg_value ((yyvsp[-2].expr));
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-4].reg), &(yyvsp[-8].reg), 0, 2, (yyvsp[0].r0).r0, (yyvsp[-2].expr));
+	    }
+	  else
+	    return yyerror ("Bad register or value for LOAD");
+	}
+    break;
+
+  case 196:
+#line 3129 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-7].reg)) && IS_PREG ((yyvsp[-3].reg)))
+	    {
+	      notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
+		       (yyvsp[0].r0).r0 ? 'X' : 'Z');
+	      (yyval.instr) = LDST (&(yyvsp[-3].reg), &(yyvsp[-7].reg), (yyvsp[-2].modcodes).x0, 2, (yyvsp[0].r0).r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+    break;
+
+  case 197:
+#line 3141 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-6].reg)) && IS_IREG ((yyvsp[-3].reg)) && IS_MREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
+	      (yyval.instr) = DSPLDST(&(yyvsp[-3].reg), (yyvsp[-1].reg).regno & CODE_MASK, &(yyvsp[-6].reg), 3, 0);
+	    }
+	  else if (IS_DREG ((yyvsp[-6].reg)) && IS_PREG ((yyvsp[-3].reg)) && IS_PREG ((yyvsp[-1].reg)))
+	    {
+	      notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
+	      (yyval.instr) = LDSTPMOD (&(yyvsp[-3].reg), &(yyvsp[-6].reg), &(yyvsp[-1].reg), 0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+    break;
+
+  case 198:
+#line 3157 "bfin-parse.y"
+    {
+	  Expr_Node *tmp = (yyvsp[-1].expr);
+	  int ispreg = IS_PREG ((yyvsp[-6].reg));
+	  int isgot = IS_RELOC((yyvsp[-1].expr));
+
+	  if (!IS_PREG ((yyvsp[-3].reg)))
+	    return yyerror ("Preg expected for indirect");
+
+	  if (!IS_DREG ((yyvsp[-6].reg)) && !ispreg)
+	    return yyerror ("Bad destination register for LOAD");
+
+	  if ((yyvsp[-2].r0).r0)
+	    tmp = unary (Expr_Op_Type_NEG, tmp);
+
+	  if(isgot){
+	      notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1: 0, tmp);
+	  }
+	  else if (in_range_p (tmp, 0, 63, 3))
+	    {
+	      notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
+	      (yyval.instr) = LDSTII (&(yyvsp[-3].reg), &(yyvsp[-6].reg), tmp, 0, ispreg ? 3 : 0);
+	    }
+	  else if ((yyvsp[-3].reg).regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+	    {
+	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+	      tmp = unary (Expr_Op_Type_NEG, tmp);
+	      (yyval.instr) = LDSTIIFP (tmp, &(yyvsp[-6].reg), 0);
+	    }
+	  else if (in_range_p (tmp, -131072, 131071, 3))
+	    {
+	      notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
+	      (yyval.instr) = LDSTIDXI (&(yyvsp[-3].reg), &(yyvsp[-6].reg), 0, 0, ispreg ? 1: 0, tmp);
+	      
+	    }
+	  else
+	    return yyerror ("Displacement out of range for load");
+	}
+    break;
+
+  case 199:
+#line 3197 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-5].reg)) && IS_IREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
+	      (yyval.instr) = DSPLDST (&(yyvsp[-2].reg), 0, &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0);
+	    }
+	  else if (IS_DREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("LDST: dregs = [ pregs <post_op> ]\n");
+	      (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 0, 0);
+	    }
+	  else if (IS_PREG ((yyvsp[-5].reg)) && IS_PREG ((yyvsp[-2].reg)))
+	    {
+	      if (REG_SAME ((yyvsp[-5].reg), (yyvsp[-2].reg)) && (yyvsp[-1].modcodes).x0 != 2)
+		return yyerror ("Pregs can't be same");
+
+	      notethat ("LDST: pregs = [ pregs <post_op> ]\n");
+	      (yyval.instr) = LDST (&(yyvsp[-2].reg), &(yyvsp[-5].reg), (yyvsp[-1].modcodes).x0, 0, 1, 0);
+	    }
+	  else if ((yyvsp[-2].reg).regno == REG_SP && IS_ALLREG ((yyvsp[-5].reg)) && (yyvsp[-1].modcodes).x0 == 0)
+	    {
+	      notethat ("PushPopReg: allregs = [ SP ++ ]\n");
+	      (yyval.instr) = PUSHPOPREG (&(yyvsp[-5].reg), 0);
+	    }
+	  else
+	    return yyerror ("Bad register or value");
+	}
+    break;
+
+  case 200:
+#line 3230 "bfin-parse.y"
+    {
+	  bfin_equals ((yyvsp[-2].expr));
+	  (yyval.instr) = 0;
+	}
+    break;
+
+  case 201:
+#line 3238 "bfin-parse.y"
+    {
+	  if ((yyvsp[-10].reg).regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+	  if ((yyvsp[-7].reg).regno == REG_R7
+	      && IN_RANGE ((yyvsp[-5].expr), 0, 7)
+	      && (yyvsp[-3].reg).regno == REG_P5
+	      && IN_RANGE ((yyvsp[-1].expr), 0, 5))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-5].expr)), imm5 ((yyvsp[-1].expr)), 1, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopMultiple");
+	}
+    break;
+
+  case 202:
+#line 3254 "bfin-parse.y"
+    {
+	  if ((yyvsp[-6].reg).regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if ((yyvsp[-3].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-1].expr), 0, 7))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-1].expr)), 0, 1, 0, 1);
+	    }
+	  else if ((yyvsp[-3].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-1].expr), 0, 6))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-1].expr)), 0, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopMultiple");
+	}
+    break;
+
+  case 203:
+#line 3273 "bfin-parse.y"
+    {
+	  if ((yyvsp[0].reg).regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+	  if ((yyvsp[-9].reg).regno == REG_R7 && (IN_RANGE ((yyvsp[-7].expr), 0, 7))
+	      && (yyvsp[-5].reg).regno == REG_P5 && (IN_RANGE ((yyvsp[-3].expr), 0, 6)))
+	    {
+	      notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-7].expr)), imm5 ((yyvsp[-3].expr)), 1, 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register range for PushPopMultiple");
+	}
+    break;
+
+  case 204:
+#line 3287 "bfin-parse.y"
+    {
+	  if ((yyvsp[0].reg).regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if ((yyvsp[-5].reg).regno == REG_R7 && IN_RANGE ((yyvsp[-3].expr), 0, 7))
+	    {
+	      notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (imm5 ((yyvsp[-3].expr)), 0, 1, 0, 0);
+	    }
+	  else if ((yyvsp[-5].reg).regno == REG_P5 && IN_RANGE ((yyvsp[-3].expr), 0, 6))
+	    {
+	      notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
+	      (yyval.instr) = PUSHPOPMULTIPLE (0, imm5 ((yyvsp[-3].expr)), 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register range for PushPopMultiple");
+	}
+    break;
+
+  case 205:
+#line 3306 "bfin-parse.y"
+    {
+	  if ((yyvsp[-2].reg).regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if (IS_ALLREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("PushPopReg: [ -- SP ] = allregs\n");
+	      (yyval.instr) = PUSHPOPREG (&(yyvsp[0].reg), 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopReg");
+	}
+    break;
+
+  case 206:
+#line 3322 "bfin-parse.y"
+    {
+	  if (IS_URANGE (16, (yyvsp[0].expr), 0, 4))
+	    (yyval.instr) = LINKAGE (0, uimm16s4 ((yyvsp[0].expr)));
+	  else
+	    return yyerror ("Bad constant for LINK");
+	}
+    break;
+
+  case 207:
+#line 3330 "bfin-parse.y"
+    {
+		notethat ("linkage: UNLINK\n");
+		(yyval.instr) = LINKAGE (1, 0);
+	}
+    break;
+
+  case 208:
+#line 3339 "bfin-parse.y"
+    {
+	  if (IS_PCREL4 ((yyvsp[-4].expr)) && IS_LPPCREL10 ((yyvsp[-2].expr)) && IS_CREG ((yyvsp[0].reg)))
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
+	      (yyval.instr) = LOOPSETUP ((yyvsp[-4].expr), &(yyvsp[0].reg), 0, (yyvsp[-2].expr), 0);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	  
+	}
+    break;
+
+  case 209:
+#line 3350 "bfin-parse.y"
+    {
+	  if (IS_PCREL4 ((yyvsp[-6].expr)) && IS_LPPCREL10 ((yyvsp[-4].expr))
+	      && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
+	      (yyval.instr) = LOOPSETUP ((yyvsp[-6].expr), &(yyvsp[-2].reg), 1, (yyvsp[-4].expr), &(yyvsp[0].reg));
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	}
+    break;
+
+  case 210:
+#line 3362 "bfin-parse.y"
+    {
+	  if (IS_PCREL4 ((yyvsp[-8].expr)) && IS_LPPCREL10 ((yyvsp[-6].expr))
+	      && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg)) 
+	      && EXPR_VALUE ((yyvsp[0].expr)) == 1)
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
+	      (yyval.instr) = LOOPSETUP ((yyvsp[-8].expr), &(yyvsp[-4].reg), 3, (yyvsp[-6].expr), &(yyvsp[-2].reg));
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	}
+    break;
+
+  case 211:
+#line 3376 "bfin-parse.y"
+    {
+	  if (!IS_RELOC ((yyvsp[-1].expr)))
+	    return yyerror ("Invalid expression in loop statement");
+	  if (!IS_CREG ((yyvsp[0].reg)))
+            return yyerror ("Invalid loop counter register");
+	(yyval.instr) = bfin_gen_loop ((yyvsp[-1].expr), &(yyvsp[0].reg), 0, 0);
+	}
+    break;
+
+  case 212:
+#line 3384 "bfin-parse.y"
+    {
+	  if (IS_RELOC ((yyvsp[-3].expr)) && IS_PREG ((yyvsp[0].reg)) && IS_CREG ((yyvsp[-2].reg)))
+	    {
+	      notethat ("Loop: LOOP expr counters = pregs\n");
+	      (yyval.instr) = bfin_gen_loop ((yyvsp[-3].expr), &(yyvsp[-2].reg), 1, &(yyvsp[0].reg));
+	    }
+	  else
+	    return yyerror ("Bad register or values for LOOP");
+	}
+    break;
+
+  case 213:
+#line 3394 "bfin-parse.y"
+    {
+	  if (IS_RELOC ((yyvsp[-5].expr)) && IS_PREG ((yyvsp[-2].reg)) && IS_CREG ((yyvsp[-4].reg)) && EXPR_VALUE ((yyvsp[0].expr)) == 1)
+	    {
+	      notethat ("Loop: LOOP expr counters = pregs >> 1\n");
+	      (yyval.instr) = bfin_gen_loop ((yyvsp[-5].expr), &(yyvsp[-4].reg), 3, &(yyvsp[-2].reg));
+	    }
+	  else
+	    return yyerror ("Bad register or values for LOOP");
+	}
+    break;
+
+  case 214:
+#line 3406 "bfin-parse.y"
+    {
+	  notethat ("pseudoDEBUG: DBG\n");
+	  (yyval.instr) = bfin_gen_pseudodbg (3, 7, 0);
+	}
+    break;
+
+  case 215:
+#line 3411 "bfin-parse.y"
+    {
+	  notethat ("pseudoDEBUG: DBG REG_A\n");
+	  (yyval.instr) = bfin_gen_pseudodbg (3, IS_A1 ((yyvsp[0].reg)), 0);
+	}
+    break;
+
+  case 216:
+#line 3416 "bfin-parse.y"
+    {
+	  notethat ("pseudoDEBUG: DBG allregs\n");
+	  (yyval.instr) = bfin_gen_pseudodbg (0, (yyvsp[0].reg).regno & CODE_MASK, (yyvsp[0].reg).regno & CLASS_MASK);
+	}
+    break;
+
+  case 217:
+#line 3422 "bfin-parse.y"
+    {
+	  if (!IS_DREG ((yyvsp[-1].reg)))
+	    return yyerror ("Dregs expected");
+	  notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
+	  (yyval.instr) = bfin_gen_pseudodbg (3, 6, (yyvsp[-1].reg).regno & CODE_MASK);
+	}
+    break;
+
+  case 218:
+#line 3430 "bfin-parse.y"
+    {
+	  notethat ("psedoDEBUG: DBGHALT\n");
+	  (yyval.instr) = bfin_gen_pseudodbg (3, 5, 0);
+	}
+    break;
+
+  case 219:
+#line 3436 "bfin-parse.y"
+    {
+	  notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
+	  (yyval.instr) = bfin_gen_pseudodbg_assert (IS_H ((yyvsp[-3].reg)), &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+	}
+    break;
+
+  case 220:
+#line 3442 "bfin-parse.y"
+    {
+	  notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
+	  (yyval.instr) = bfin_gen_pseudodbg_assert (3, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+	}
+    break;
+
+  case 221:
+#line 3448 "bfin-parse.y"
+    {
+	  notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
+	  (yyval.instr) = bfin_gen_pseudodbg_assert (2, &(yyvsp[-3].reg), uimm16 ((yyvsp[-1].expr)));
+	}
+    break;
+
+  case 222:
+#line 3461 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[0].reg);
+	}
+    break;
+
+  case 223:
+#line 3465 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[0].reg);
+	}
+    break;
+
+  case 224:
+#line 3474 "bfin-parse.y"
+    {
+	(yyval.mod).MM = 0;
+	(yyval.mod).mod = 0;
+	}
+    break;
+
+  case 225:
+#line 3479 "bfin-parse.y"
+    {
+	(yyval.mod).MM = 1;
+	(yyval.mod).mod = (yyvsp[-1].value);
+	}
+    break;
+
+  case 226:
+#line 3484 "bfin-parse.y"
+    {
+	(yyval.mod).MM = 1;
+	(yyval.mod).mod = (yyvsp[-3].value);
+	}
+    break;
+
+  case 227:
+#line 3489 "bfin-parse.y"
+    {
+	(yyval.mod).MM = 0;
+	(yyval.mod).mod = (yyvsp[-1].value);
+	}
+    break;
+
+  case 228:
+#line 3494 "bfin-parse.y"
+    {
+	(yyval.mod).MM = 1;
+	(yyval.mod).mod = 0;
+	}
+    break;
+
+  case 229:
+#line 3501 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 230:
+#line 3505 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 231:
+#line 3511 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 232:
+#line 3516 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 1;
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 233:
+#line 3521 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 1;
+	}
+    break;
+
+  case 234:
+#line 3526 "bfin-parse.y"
+    {	
+	(yyval.modcodes).s0 = 1;
+	(yyval.modcodes).x0 = 1;
+	}
+    break;
+
+  case 235:
+#line 3534 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 236:
+#line 3538 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 237:
+#line 3544 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 238:
+#line 3549 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+	}
+    break;
+
+  case 239:
+#line 3556 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	(yyval.modcodes).aop = 0;
+	}
+    break;
+
+  case 240:
+#line 3562 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	(yyval.modcodes).aop = 1;
+	}
+    break;
+
+  case 241:
+#line 3568 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 1;
+	(yyval.modcodes).x0 = 0;
+	(yyval.modcodes).aop = 1;
+	}
+    break;
+
+  case 242:
+#line 3576 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 243:
+#line 3582 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 244:
+#line 3588 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+	}
+    break;
+
+  case 245:
+#line 3594 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 2 + (yyvsp[-3].r0).r0;
+	(yyval.modcodes).s0 = (yyvsp[-1].modcodes).s0;
+	(yyval.modcodes).x0 = (yyvsp[-1].modcodes).x0;
+	}
+    break;
+
+  case 246:
+#line 3600 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 2 + (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = (yyvsp[-3].modcodes).s0;
+	(yyval.modcodes).x0 = (yyvsp[-3].modcodes).x0;
+	}
+    break;
+
+  case 247:
+#line 3608 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 248:
+#line 3612 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 249:
+#line 3616 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 250:
+#line 3622 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 251:
+#line 3626 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 252:
+#line 3630 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 253:
+#line 3636 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).aop = 0;
+	}
+    break;
+
+  case 254:
+#line 3642 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).aop = 3;
+	}
+    break;
+
+  case 255:
+#line 3648 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = 1;
+	(yyval.modcodes).aop = 3;
+	}
+    break;
+
+  case 256:
+#line 3654 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 0;
+	(yyval.modcodes).aop = 3;
+	}
+    break;
+
+  case 257:
+#line 3660 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 258:
+#line 3665 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 259:
+#line 3672 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 260:
+#line 3676 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 261:
+#line 3682 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 0;
+	}
+    break;
+
+  case 262:
+#line 3686 "bfin-parse.y"
+    {
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 263:
+#line 3693 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 264:
+#line 3697 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 265:
+#line 3701 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 3;
+	}
+    break;
+
+  case 266:
+#line 3705 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 2;
+	}
+    break;
+
+  case 267:
+#line 3711 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 268:
+#line 3715 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 269:
+#line 3722 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 270:
+#line 3727 "bfin-parse.y"
+    {
+	if ((yyvsp[-1].value) != M_T)
+	  return yyerror ("Bad modifier");
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 0;
+	}
+    break;
+
+  case 271:
+#line 3734 "bfin-parse.y"
+    {
+	if ((yyvsp[-3].value) != M_T)
+	  return yyerror ("Bad modifier");
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 272:
+#line 3741 "bfin-parse.y"
+    {
+	if ((yyvsp[-1].value) != M_T)
+	  return yyerror ("Bad modifier");
+	(yyval.modcodes).r0 = 1;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 273:
+#line 3753 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 274:
+#line 3757 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 275:
+#line 3761 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 2;
+	}
+    break;
+
+  case 276:
+#line 3767 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 277:
+#line 3771 "bfin-parse.y"
+    {
+	  if ((yyvsp[-1].value) == M_W32)
+	    (yyval.r0).r0 = 1;
+	  else
+	    return yyerror ("Only (W32) allowed");
+	}
+    break;
+
+  case 278:
+#line 3780 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 279:
+#line 3784 "bfin-parse.y"
+    {
+	  if ((yyvsp[-1].value) == M_IU)
+	    (yyval.r0).r0 = 3;
+	  else
+	    return yyerror ("(IU) expected");
+	}
+    break;
+
+  case 280:
+#line 3793 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[-1].reg);
+	}
+    break;
+
+  case 281:
+#line 3799 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[-2].reg);
+	}
+    break;
+
+  case 282:
+#line 3808 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 283:
+#line 3812 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 284:
+#line 3819 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 285:
+#line 3823 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 286:
+#line 3827 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 2;
+	}
+    break;
+
+  case 287:
+#line 3831 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 3;
+	}
+    break;
+
+  case 288:
+#line 3838 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 289:
+#line 3842 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 290:
+#line 3849 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 1;	/* HL.  */
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 0;	/* aop.  */
+	}
+    break;
+
+  case 291:
+#line 3857 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 1;	/* HL.  */
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 1;	/* aop.  */
+	}
+    break;
+
+  case 292:
+#line 3865 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 0;	/* HL.  */
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 0;	/* aop.  */
+	}
+    break;
+
+  case 293:
+#line 3873 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 0;	/* HL.  */
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 1;
+	}
+    break;
+
+  case 294:
+#line 3881 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 1;	/* HL.  */
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 0;	/* aop.  */
+	}
+    break;
+
+  case 295:
+#line 3888 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 1;	/* HL.  */
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 1;	/* aop.  */
+	}
+    break;
+
+  case 296:
+#line 3895 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 0;	/* HL.  */
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 0;	/* aop.  */
+	}
+    break;
+
+  case 297:
+#line 3903 "bfin-parse.y"
+    {
+	  (yyval.modcodes).r0 = 0;	/* HL.  */
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* x.  */
+	  (yyval.modcodes).aop = 1;	/* aop.  */
+	}
+    break;
+
+  case 298:
+#line 3913 "bfin-parse.y"
+    {
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* HL.  */
+	}
+    break;
+
+  case 299:
+#line 3918 "bfin-parse.y"
+    {
+	  (yyval.modcodes).s0 = 0;	/* s.  */
+	  (yyval.modcodes).x0 = 1;	/* HL.  */
+	}
+    break;
+
+  case 300:
+#line 3923 "bfin-parse.y"
+    {
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 0;	/* HL.  */
+	}
+    break;
+
+  case 301:
+#line 3928 "bfin-parse.y"
+    {
+	  (yyval.modcodes).s0 = 1;	/* s.  */
+	  (yyval.modcodes).x0 = 1;	/* HL.  */
+	}
+    break;
+
+  case 302:
+#line 3935 "bfin-parse.y"
+    {
+	(yyval.modcodes).x0 = 2;
+	}
+    break;
+
+  case 303:
+#line 3939 "bfin-parse.y"
+    {
+	(yyval.modcodes).x0 = 0;
+	}
+    break;
+
+  case 304:
+#line 3943 "bfin-parse.y"
+    {
+	(yyval.modcodes).x0 = 1;
+	}
+    break;
+
+  case 305:
+#line 3952 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[-1].reg);
+	}
+    break;
+
+  case 306:
+#line 3959 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[-1].reg);
+	}
+    break;
+
+  case 307:
+#line 3966 "bfin-parse.y"
+    {
+	(yyval.reg) = (yyvsp[-1].reg);
+	}
+    break;
+
+  case 308:
+#line 3973 "bfin-parse.y"
+    {
+	  (yyval.macfunc).w = 1;
+          (yyval.macfunc).P = 1;
+          (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
+	  (yyval.macfunc).op = 3;
+          (yyval.macfunc).dst = (yyvsp[-2].reg);
+	  (yyval.macfunc).s0.regno = 0;
+          (yyval.macfunc).s1.regno = 0;
+
+	  if (IS_A1 ((yyvsp[0].reg)) && IS_EVEN ((yyvsp[-2].reg)))
+	    return yyerror ("Cannot move A1 to even register");
+	  else if (!IS_A1 ((yyvsp[0].reg)) && !IS_EVEN ((yyvsp[-2].reg)))
+	    return yyerror ("Cannot move A0 to odd register");
+	}
+    break;
+
+  case 309:
+#line 3988 "bfin-parse.y"
+    {
+	  (yyval.macfunc) = (yyvsp[0].macfunc);
+	  (yyval.macfunc).w = 0; (yyval.macfunc).P = 0;
+	  (yyval.macfunc).dst.regno = 0;
+	}
+    break;
+
+  case 310:
+#line 3994 "bfin-parse.y"
+    {
+	  (yyval.macfunc) = (yyvsp[-1].macfunc);
+	  (yyval.macfunc).w = 1;
+          (yyval.macfunc).P = 1;
+          (yyval.macfunc).dst = (yyvsp[-4].reg);
+	}
+    break;
+
+  case 311:
+#line 4002 "bfin-parse.y"
+    {
+	  (yyval.macfunc) = (yyvsp[-1].macfunc);
+	  (yyval.macfunc).w = 1;
+	  (yyval.macfunc).P = 0;
+          (yyval.macfunc).dst = (yyvsp[-4].reg);
+	}
+    break;
+
+  case 312:
+#line 4010 "bfin-parse.y"
+    {
+	  (yyval.macfunc).w = 1;
+	  (yyval.macfunc).P = 0;
+	  (yyval.macfunc).n = IS_A1 ((yyvsp[0].reg));
+	  (yyval.macfunc).op = 3;
+          (yyval.macfunc).dst = (yyvsp[-2].reg);
+	  (yyval.macfunc).s0.regno = 0;
+          (yyval.macfunc).s1.regno = 0;
+
+	  if (IS_A1 ((yyvsp[0].reg)) && !IS_H ((yyvsp[-2].reg)))
+	    return yyerror ("Cannot move A1 to low half of register");
+	  else if (!IS_A1 ((yyvsp[0].reg)) && IS_H ((yyvsp[-2].reg)))
+	    return yyerror ("Cannot move A0 to high half of register");
+	}
+    break;
+
+  case 313:
+#line 4028 "bfin-parse.y"
+    {
+	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+	  (yyval.macfunc).op = 0;
+	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+	}
+    break;
+
+  case 314:
+#line 4035 "bfin-parse.y"
+    {
+	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+	  (yyval.macfunc).op = 1;
+	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+	}
+    break;
+
+  case 315:
+#line 4042 "bfin-parse.y"
+    {
+	  (yyval.macfunc).n = IS_A1 ((yyvsp[-1].reg));
+	  (yyval.macfunc).op = 2;
+	  (yyval.macfunc).s0 = (yyvsp[0].macfunc).s0;
+	  (yyval.macfunc).s1 = (yyvsp[0].macfunc).s1;
+	}
+    break;
+
+  case 316:
+#line 4052 "bfin-parse.y"
+    {
+	  if (IS_DREG ((yyvsp[-2].reg)) && IS_DREG ((yyvsp[0].reg)))
+	    {
+	      (yyval.macfunc).s0 = (yyvsp[-2].reg);
+              (yyval.macfunc).s1 = (yyvsp[0].reg);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+    break;
+
+  case 317:
+#line 4065 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 0;
+	}
+    break;
+
+  case 318:
+#line 4069 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 1;
+	}
+    break;
+
+  case 319:
+#line 4073 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 2;
+	}
+    break;
+
+  case 320:
+#line 4077 "bfin-parse.y"
+    {
+	(yyval.r0).r0 = 3;
+	}
+    break;
+
+  case 321:
+#line 4084 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = (yyvsp[0].reg).regno;
+	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = 0;
+	}
+    break;
+
+  case 322:
+#line 4090 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0x18;
+	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = 0;
+	}
+    break;
+
+  case 323:
+#line 4096 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = (yyvsp[-2].reg).regno;
+	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 324:
+#line 4102 "bfin-parse.y"
+    {
+	(yyval.modcodes).r0 = 0x18;
+	(yyval.modcodes).x0 = (yyvsp[-1].r0).r0;
+	(yyval.modcodes).s0 = 1;
+	}
+    break;
+
+  case 325:
+#line 4112 "bfin-parse.y"
+    {
+	Expr_Node_Value val;
+	val.s_value = S_GET_NAME((yyvsp[0].symbol));
+	(yyval.expr) = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
+	}
+    break;
+
+  case 326:
+#line 4121 "bfin-parse.y"
+    { (yyval.value) = BFD_RELOC_BFIN_GOT; }
+    break;
+
+  case 327:
+#line 4123 "bfin-parse.y"
+    { (yyval.value) = BFD_RELOC_BFIN_GOT17M4; }
+    break;
+
+  case 328:
+#line 4125 "bfin-parse.y"
+    { (yyval.value) = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
+    break;
+
+  case 329:
+#line 4129 "bfin-parse.y"
+    {
+	Expr_Node_Value val;
+	val.i_value = (yyvsp[0].value);
+	(yyval.expr) = Expr_Node_Create (Expr_Node_GOT_Reloc, val, (yyvsp[-2].expr), NULL);
+	}
+    break;
+
+  case 330:
+#line 4137 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[0].expr);
+	}
+    break;
+
+  case 331:
+#line 4141 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[0].expr);
+	}
+    break;
+
+  case 332:
+#line 4148 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[-2].expr);
+	}
+    break;
+
+  case 333:
+#line 4154 "bfin-parse.y"
+    {
+	Expr_Node_Value val;
+	val.i_value = (yyvsp[0].value);
+	(yyval.expr) = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
+	}
+    break;
+
+  case 334:
+#line 4160 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[0].expr);
+	}
+    break;
+
+  case 335:
+#line 4164 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[-1].expr);
+	}
+    break;
+
+  case 336:
+#line 4168 "bfin-parse.y"
+    {
+	(yyval.expr) = unary (Expr_Op_Type_COMP, (yyvsp[0].expr));
+	}
+    break;
+
+  case 337:
+#line 4172 "bfin-parse.y"
+    {
+	(yyval.expr) = unary (Expr_Op_Type_NEG, (yyvsp[0].expr));
+	}
+    break;
+
+  case 338:
+#line 4178 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[0].expr);
+	}
+    break;
+
+  case 339:
+#line 4184 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Mult, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 340:
+#line 4188 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Div, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 341:
+#line 4192 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Mod, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 342:
+#line 4196 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Add, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 343:
+#line 4200 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Sub, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 344:
+#line 4204 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Lshift, (yyvsp[-2].expr), (yyvsp[0].expr));	
+	}
+    break;
+
+  case 345:
+#line 4208 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_Rshift, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 346:
+#line 4212 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_BAND, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 347:
+#line 4216 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_LOR, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 348:
+#line 4220 "bfin-parse.y"
+    {
+	(yyval.expr) = binary (Expr_Op_Type_BOR, (yyvsp[-2].expr), (yyvsp[0].expr));
+	}
+    break;
+
+  case 349:
+#line 4224 "bfin-parse.y"
+    {
+	(yyval.expr) = (yyvsp[0].expr);
+	}
+    break;
+
+
+      default: break;
+    }
+
+/* Line 1126 of yacc.c.  */
+#line 7065 "bfin-parse.c"
+
+  yyvsp -= yylen;
+  yyssp -= yylen;
+
+
+  YY_STACK_PRINT (yyss, yyssp);
+
+  *++yyvsp = yyval;
+
+
+  /* Now `shift' the result of the reduction.  Determine what state
+     that goes to, based on the state we popped back to and the rule
+     number reduced by.  */
+
+  yyn = yyr1[yyn];
+
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+    yystate = yytable[yystate];
+  else
+    yystate = yydefgoto[yyn - YYNTOKENS];
+
+  goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+  /* If not already recovering from an error, report this error.  */
+  if (!yyerrstatus)
+    {
+      ++yynerrs;
+#if YYERROR_VERBOSE
+      yyn = yypact[yystate];
+
+      if (YYPACT_NINF < yyn && yyn < YYLAST)
+	{
+	  int yytype = YYTRANSLATE (yychar);
+	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+	  YYSIZE_T yysize = yysize0;
+	  YYSIZE_T yysize1;
+	  int yysize_overflow = 0;
+	  char *yymsg = 0;
+#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
+	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+	  int yyx;
+
+#if 0
+	  /* This is so xgettext sees the translatable formats that are
+	     constructed on the fly.  */
+	  YY_("syntax error, unexpected %s");
+	  YY_("syntax error, unexpected %s, expecting %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+#endif
+	  char *yyfmt;
+	  char const *yyf;
+	  static char const yyunexpected[] = "syntax error, unexpected %s";
+	  static char const yyexpecting[] = ", expecting %s";
+	  static char const yyor[] = " or %s";
+	  char yyformat[sizeof yyunexpected
+			+ sizeof yyexpecting - 1
+			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+			   * (sizeof yyor - 1))];
+	  char const *yyprefix = yyexpecting;
+
+	  /* Start YYX at -YYN if negative to avoid negative indexes in
+	     YYCHECK.  */
+	  int yyxbegin = yyn < 0 ? -yyn : 0;
+
+	  /* Stay within bounds of both yycheck and yytname.  */
+	  int yychecklim = YYLAST - yyn;
+	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+	  int yycount = 1;
+
+	  yyarg[0] = yytname[yytype];
+	  yyfmt = yystpcpy (yyformat, yyunexpected);
+
+	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	      {
+		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+		  {
+		    yycount = 1;
+		    yysize = yysize0;
+		    yyformat[sizeof yyunexpected - 1] = '\0';
+		    break;
+		  }
+		yyarg[yycount++] = yytname[yyx];
+		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+		yysize_overflow |= yysize1 < yysize;
+		yysize = yysize1;
+		yyfmt = yystpcpy (yyfmt, yyprefix);
+		yyprefix = yyor;
+	      }
+
+	  yyf = YY_(yyformat);
+	  yysize1 = yysize + yystrlen (yyf);
+	  yysize_overflow |= yysize1 < yysize;
+	  yysize = yysize1;
+
+	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
+	    yymsg = (char *) YYSTACK_ALLOC (yysize);
+	  if (yymsg)
+	    {
+	      /* Avoid sprintf, as that infringes on the user's name space.
+		 Don't have undefined behavior even if the translation
+		 produced a string with the wrong number of "%s"s.  */
+	      char *yyp = yymsg;
+	      int yyi = 0;
+	      while ((*yyp = *yyf))
+		{
+		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		    {
+		      yyp += yytnamerr (yyp, yyarg[yyi++]);
+		      yyf += 2;
+		    }
+		  else
+		    {
+		      yyp++;
+		      yyf++;
+		    }
+		}
+	      yyerror (yymsg);
+	      YYSTACK_FREE (yymsg);
+	    }
+	  else
+	    {
+	      yyerror (YY_("syntax error"));
+	      goto yyexhaustedlab;
+	    }
+	}
+      else
+#endif /* YYERROR_VERBOSE */
+	yyerror (YY_("syntax error"));
+    }
+
+
+
+  if (yyerrstatus == 3)
+    {
+      /* If just tried and failed to reuse look-ahead token after an
+	 error, discard it.  */
+
+      if (yychar <= YYEOF)
+        {
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+        }
+      else
+	{
+	  yydestruct ("Error: discarding", yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
+    }
+
+  /* Else will try to reuse look-ahead token after shifting the error
+     token.  */
+  goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
+
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (0)
+     goto yyerrorlab;
+
+yyvsp -= yylen;
+  yyssp -= yylen;
+  yystate = *yyssp;
+  goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
+
+  for (;;)
+    {
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
+
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
+
+
+      yydestruct ("Error: popping", yystos[yystate], yyvsp);
+      YYPOPSTACK;
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
+    }
+
+  if (yyn == YYFINAL)
+    YYACCEPT;
+
+  *++yyvsp = yylval;
+
+
+  /* Shift the error token. */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+  yystate = yyn;
+  goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here.  |
+`-------------------------------------*/
+yyacceptlab:
+  yyresult = 0;
+  goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here.  |
+`-----------------------------------*/
+yyabortlab:
+  yyresult = 1;
+  goto yyreturn;
+
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
+  yyresult = 2;
+  /* Fall through.  */
+#endif
+
+yyreturn:
+  if (yychar != YYEOF && yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK;
+    }
+#ifndef yyoverflow
+  if (yyss != yyssa)
+    YYSTACK_FREE (yyss);
+#endif
+  return yyresult;
+}
+
+
+#line 4230 "bfin-parse.y"
+
+
+EXPR_T
+mkexpr (int x, SYMBOL_T s)
+{
+  EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
+  e->value = x;
+  EXPR_SYMBOL(e) = s;
+  return e;
+}
+
+static int
+value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
+{
+  long umax = (1L << sz) - 1;
+  long min = -1L << (sz - 1);
+  long max = (1L << (sz - 1)) - 1;
+	
+  long v = EXPR_VALUE (expr);
+
+  if ((v % mul) != 0)
+    {
+      error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); 
+      return 0;
+    }
+
+  v /= mul;
+
+  if (sign)
+    v = -v;
+
+  if (issigned)
+    {
+      if (v >= min && v <= max) return 1;
+
+#ifdef DEBUG
+      fprintf(stderr, "signed value %lx out of range\n", v * mul);
+#endif
+      return 0;
+    }
+  if (v <= umax && v >= 0) 
+    return 1;
+#ifdef DEBUG
+  fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
+#endif
+  return 0;
+}
+
+/* Return the expression structure that allows symbol operations.
+   If the left and right children are constants, do the operation.  */
+static Expr_Node *
+binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
+{
+  if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
+    {
+      switch (op)
+	{
+        case Expr_Op_Type_Add: 
+	  x->value.i_value += y->value.i_value;
+	  break;
+        case Expr_Op_Type_Sub: 
+	  x->value.i_value -= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Mult: 
+	  x->value.i_value *= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Div: 
+	  if (y->value.i_value == 0)
+	    error ("Illegal Expression:  Division by zero.");
+	  else
+	    x->value.i_value /= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Mod: 
+	  x->value.i_value %= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Lshift: 
+	  x->value.i_value <<= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Rshift: 
+	  x->value.i_value >>= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BAND: 
+	  x->value.i_value &= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BOR: 
+	  x->value.i_value |= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BXOR: 
+	  x->value.i_value ^= y->value.i_value;
+	  break;
+        case Expr_Op_Type_LAND: 
+	  x->value.i_value = x->value.i_value && y->value.i_value;
+	  break;
+        case Expr_Op_Type_LOR: 
+	  x->value.i_value = x->value.i_value || y->value.i_value;
+	  break;
+
+	default:
+	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
+	}
+      return x;
+    }
+  else
+    {
+    /* Create a new expression structure.  */
+    Expr_Node_Value val;
+    val.op_value = op;
+    return Expr_Node_Create (Expr_Node_Binop, val, x, y);
+  }
+}
+
+static Expr_Node *
+unary (Expr_Op_Type op, Expr_Node *x) 
+{
+  if (x->type == Expr_Node_Constant)
+    {
+      switch (op)
+	{
+	case Expr_Op_Type_NEG: 
+	  x->value.i_value = -x->value.i_value;
+	  break;
+	case Expr_Op_Type_COMP:
+	  x->value.i_value = ~x->value.i_value;
+	  break;
+	default:
+	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
+	}
+      return x;
+    }
+  else
+    {
+      /* Create a new expression structure.  */
+      Expr_Node_Value val;
+      val.op_value = op;
+      return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
+    }
+}
+
+int debug_codeselection = 0;
+static void
+notethat (char *format, ...)
+{
+  va_list ap;
+  va_start (ap, format);
+  if (debug_codeselection)
+    {
+      vfprintf (errorf, format, ap);
+    }
+  va_end (ap);
+}
+
+#ifdef TEST
+main (int argc, char **argv)
+{
+  yyparse();
+}
+#endif
+
+
diff --git a/gas/bfin-parse.h b/gas/bfin-parse.h
new file mode 100644
index 000000000000..06403c81ec03
--- /dev/null
+++ b/gas/bfin-parse.h
@@ -0,0 +1,406 @@
+/* A Bison parser, made by GNU Bison 2.1.  */
+
+/* Skeleton parser for Yacc-like parsing with Bison,
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     BYTEOP16P = 258,
+     BYTEOP16M = 259,
+     BYTEOP1P = 260,
+     BYTEOP2P = 261,
+     BYTEOP2M = 262,
+     BYTEOP3P = 263,
+     BYTEUNPACK = 264,
+     BYTEPACK = 265,
+     PACK = 266,
+     SAA = 267,
+     ALIGN8 = 268,
+     ALIGN16 = 269,
+     ALIGN24 = 270,
+     VIT_MAX = 271,
+     EXTRACT = 272,
+     DEPOSIT = 273,
+     EXPADJ = 274,
+     SEARCH = 275,
+     ONES = 276,
+     SIGN = 277,
+     SIGNBITS = 278,
+     LINK = 279,
+     UNLINK = 280,
+     REG = 281,
+     PC = 282,
+     CCREG = 283,
+     BYTE_DREG = 284,
+     REG_A_DOUBLE_ZERO = 285,
+     REG_A_DOUBLE_ONE = 286,
+     A_ZERO_DOT_L = 287,
+     A_ZERO_DOT_H = 288,
+     A_ONE_DOT_L = 289,
+     A_ONE_DOT_H = 290,
+     HALF_REG = 291,
+     NOP = 292,
+     RTI = 293,
+     RTS = 294,
+     RTX = 295,
+     RTN = 296,
+     RTE = 297,
+     HLT = 298,
+     IDLE = 299,
+     STI = 300,
+     CLI = 301,
+     CSYNC = 302,
+     SSYNC = 303,
+     EMUEXCPT = 304,
+     RAISE = 305,
+     EXCPT = 306,
+     LSETUP = 307,
+     LOOP = 308,
+     LOOP_BEGIN = 309,
+     LOOP_END = 310,
+     DISALGNEXCPT = 311,
+     JUMP = 312,
+     JUMP_DOT_S = 313,
+     JUMP_DOT_L = 314,
+     CALL = 315,
+     ABORT = 316,
+     NOT = 317,
+     TILDA = 318,
+     BANG = 319,
+     AMPERSAND = 320,
+     BAR = 321,
+     PERCENT = 322,
+     CARET = 323,
+     BXOR = 324,
+     MINUS = 325,
+     PLUS = 326,
+     STAR = 327,
+     SLASH = 328,
+     NEG = 329,
+     MIN = 330,
+     MAX = 331,
+     ABS = 332,
+     DOUBLE_BAR = 333,
+     _PLUS_BAR_PLUS = 334,
+     _PLUS_BAR_MINUS = 335,
+     _MINUS_BAR_PLUS = 336,
+     _MINUS_BAR_MINUS = 337,
+     _MINUS_MINUS = 338,
+     _PLUS_PLUS = 339,
+     SHIFT = 340,
+     LSHIFT = 341,
+     ASHIFT = 342,
+     BXORSHIFT = 343,
+     _GREATER_GREATER_GREATER_THAN_ASSIGN = 344,
+     ROT = 345,
+     LESS_LESS = 346,
+     GREATER_GREATER = 347,
+     _GREATER_GREATER_GREATER = 348,
+     _LESS_LESS_ASSIGN = 349,
+     _GREATER_GREATER_ASSIGN = 350,
+     DIVS = 351,
+     DIVQ = 352,
+     ASSIGN = 353,
+     _STAR_ASSIGN = 354,
+     _BAR_ASSIGN = 355,
+     _CARET_ASSIGN = 356,
+     _AMPERSAND_ASSIGN = 357,
+     _MINUS_ASSIGN = 358,
+     _PLUS_ASSIGN = 359,
+     _ASSIGN_BANG = 360,
+     _LESS_THAN_ASSIGN = 361,
+     _ASSIGN_ASSIGN = 362,
+     GE = 363,
+     LT = 364,
+     LE = 365,
+     GT = 366,
+     LESS_THAN = 367,
+     FLUSHINV = 368,
+     FLUSH = 369,
+     IFLUSH = 370,
+     PREFETCH = 371,
+     PRNT = 372,
+     OUTC = 373,
+     WHATREG = 374,
+     TESTSET = 375,
+     ASL = 376,
+     ASR = 377,
+     B = 378,
+     W = 379,
+     NS = 380,
+     S = 381,
+     CO = 382,
+     SCO = 383,
+     TH = 384,
+     TL = 385,
+     BP = 386,
+     BREV = 387,
+     X = 388,
+     Z = 389,
+     M = 390,
+     MMOD = 391,
+     R = 392,
+     RND = 393,
+     RNDL = 394,
+     RNDH = 395,
+     RND12 = 396,
+     RND20 = 397,
+     V = 398,
+     LO = 399,
+     HI = 400,
+     BITTGL = 401,
+     BITCLR = 402,
+     BITSET = 403,
+     BITTST = 404,
+     BITMUX = 405,
+     DBGAL = 406,
+     DBGAH = 407,
+     DBGHALT = 408,
+     DBG = 409,
+     DBGA = 410,
+     DBGCMPLX = 411,
+     IF = 412,
+     COMMA = 413,
+     BY = 414,
+     COLON = 415,
+     SEMICOLON = 416,
+     RPAREN = 417,
+     LPAREN = 418,
+     LBRACK = 419,
+     RBRACK = 420,
+     STATUS_REG = 421,
+     MNOP = 422,
+     SYMBOL = 423,
+     NUMBER = 424,
+     GOT = 425,
+     GOT17M4 = 426,
+     FUNCDESC_GOT17M4 = 427,
+     AT = 428,
+     PLTPC = 429
+   };
+#endif
+/* Tokens.  */
+#define BYTEOP16P 258
+#define BYTEOP16M 259
+#define BYTEOP1P 260
+#define BYTEOP2P 261
+#define BYTEOP2M 262
+#define BYTEOP3P 263
+#define BYTEUNPACK 264
+#define BYTEPACK 265
+#define PACK 266
+#define SAA 267
+#define ALIGN8 268
+#define ALIGN16 269
+#define ALIGN24 270
+#define VIT_MAX 271
+#define EXTRACT 272
+#define DEPOSIT 273
+#define EXPADJ 274
+#define SEARCH 275
+#define ONES 276
+#define SIGN 277
+#define SIGNBITS 278
+#define LINK 279
+#define UNLINK 280
+#define REG 281
+#define PC 282
+#define CCREG 283
+#define BYTE_DREG 284
+#define REG_A_DOUBLE_ZERO 285
+#define REG_A_DOUBLE_ONE 286
+#define A_ZERO_DOT_L 287
+#define A_ZERO_DOT_H 288
+#define A_ONE_DOT_L 289
+#define A_ONE_DOT_H 290
+#define HALF_REG 291
+#define NOP 292
+#define RTI 293
+#define RTS 294
+#define RTX 295
+#define RTN 296
+#define RTE 297
+#define HLT 298
+#define IDLE 299
+#define STI 300
+#define CLI 301
+#define CSYNC 302
+#define SSYNC 303
+#define EMUEXCPT 304
+#define RAISE 305
+#define EXCPT 306
+#define LSETUP 307
+#define LOOP 308
+#define LOOP_BEGIN 309
+#define LOOP_END 310
+#define DISALGNEXCPT 311
+#define JUMP 312
+#define JUMP_DOT_S 313
+#define JUMP_DOT_L 314
+#define CALL 315
+#define ABORT 316
+#define NOT 317
+#define TILDA 318
+#define BANG 319
+#define AMPERSAND 320
+#define BAR 321
+#define PERCENT 322
+#define CARET 323
+#define BXOR 324
+#define MINUS 325
+#define PLUS 326
+#define STAR 327
+#define SLASH 328
+#define NEG 329
+#define MIN 330
+#define MAX 331
+#define ABS 332
+#define DOUBLE_BAR 333
+#define _PLUS_BAR_PLUS 334
+#define _PLUS_BAR_MINUS 335
+#define _MINUS_BAR_PLUS 336
+#define _MINUS_BAR_MINUS 337
+#define _MINUS_MINUS 338
+#define _PLUS_PLUS 339
+#define SHIFT 340
+#define LSHIFT 341
+#define ASHIFT 342
+#define BXORSHIFT 343
+#define _GREATER_GREATER_GREATER_THAN_ASSIGN 344
+#define ROT 345
+#define LESS_LESS 346
+#define GREATER_GREATER 347
+#define _GREATER_GREATER_GREATER 348
+#define _LESS_LESS_ASSIGN 349
+#define _GREATER_GREATER_ASSIGN 350
+#define DIVS 351
+#define DIVQ 352
+#define ASSIGN 353
+#define _STAR_ASSIGN 354
+#define _BAR_ASSIGN 355
+#define _CARET_ASSIGN 356
+#define _AMPERSAND_ASSIGN 357
+#define _MINUS_ASSIGN 358
+#define _PLUS_ASSIGN 359
+#define _ASSIGN_BANG 360
+#define _LESS_THAN_ASSIGN 361
+#define _ASSIGN_ASSIGN 362
+#define GE 363
+#define LT 364
+#define LE 365
+#define GT 366
+#define LESS_THAN 367
+#define FLUSHINV 368
+#define FLUSH 369
+#define IFLUSH 370
+#define PREFETCH 371
+#define PRNT 372
+#define OUTC 373
+#define WHATREG 374
+#define TESTSET 375
+#define ASL 376
+#define ASR 377
+#define B 378
+#define W 379
+#define NS 380
+#define S 381
+#define CO 382
+#define SCO 383
+#define TH 384
+#define TL 385
+#define BP 386
+#define BREV 387
+#define X 388
+#define Z 389
+#define M 390
+#define MMOD 391
+#define R 392
+#define RND 393
+#define RNDL 394
+#define RNDH 395
+#define RND12 396
+#define RND20 397
+#define V 398
+#define LO 399
+#define HI 400
+#define BITTGL 401
+#define BITCLR 402
+#define BITSET 403
+#define BITTST 404
+#define BITMUX 405
+#define DBGAL 406
+#define DBGAH 407
+#define DBGHALT 408
+#define DBG 409
+#define DBGA 410
+#define DBGCMPLX 411
+#define IF 412
+#define COMMA 413
+#define BY 414
+#define COLON 415
+#define SEMICOLON 416
+#define RPAREN 417
+#define LPAREN 418
+#define LBRACK 419
+#define RBRACK 420
+#define STATUS_REG 421
+#define MNOP 422
+#define SYMBOL 423
+#define NUMBER 424
+#define GOT 425
+#define GOT17M4 426
+#define FUNCDESC_GOT17M4 427
+#define AT 428
+#define PLTPC 429
+
+
+
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 366 "bfin-parse.y"
+typedef union YYSTYPE {
+  INSTR_T instr;
+  Expr_Node *expr;
+  SYMBOL_T symbol;
+  long value;
+  Register reg;
+  Macfunc macfunc;
+  struct { int r0; int s0; int x0; int aop; } modcodes;
+  struct { int r0; } r0;
+  Opt_mode mod;
+} YYSTYPE;
+/* Line 1447 of yacc.c.  */
+#line 398 "bfin-parse.h"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+extern YYSTYPE yylval;
+
+
+
diff --git a/gas/bignum-copy.c b/gas/bignum-copy.c
deleted file mode 100644
index 56974722f51f..000000000000
--- a/gas/bignum-copy.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/* bignum_copy.c - copy a bignum
-   Copyright 1987, 1990, 1991, 1992, 1993, 2000
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#include "as.h"
-
-/*
- *			bignum_copy ()
- *
- * Copy a bignum from in to out.
- * If the output is shorter than the input, copy lower-order littlenums.
- * Return 0 or the number of significant littlenums dropped.
- * Assumes littlenum arrays are densely packed: no unused chars between
- * the littlenums. Uses memcpy() to move littlenums, and wants to
- * know length (in chars) of the input bignum.
- */
-
-/* void */
-int
-bignum_copy (register LITTLENUM_TYPE *in,
-	     register int in_length,	/* in sizeof(littlenum)s */
-	     register LITTLENUM_TYPE *out,
-	     register int out_length	/* in sizeof(littlenum)s */)
-{
-  int significant_littlenums_dropped;
-
-  if (out_length < in_length)
-    {
-      LITTLENUM_TYPE *p;	/* -> most significant (non-zero) input
-				      littlenum.  */
-
-      memcpy ((void *) out, (void *) in,
-	      (unsigned int) out_length << LITTLENUM_SHIFT);
-      for (p = in + in_length - 1; p >= in; --p)
-	{
-	  if (*p)
-	    break;
-	}
-      significant_littlenums_dropped = p - in - in_length + 1;
-
-      if (significant_littlenums_dropped < 0)
-	{
-	  significant_littlenums_dropped = 0;
-	}
-    }
-  else
-    {
-      memcpy ((char *) out, (char *) in,
-	      (unsigned int) in_length << LITTLENUM_SHIFT);
-
-      if (out_length > in_length)
-	{
-	  memset ((char *) (out + in_length),
-		  '\0',
-		  (unsigned int) (out_length - in_length) << LITTLENUM_SHIFT);
-	}
-
-      significant_littlenums_dropped = 0;
-    }
-
-  return (significant_littlenums_dropped);
-}				/* bignum_copy() */
-
-/* end of bignum-copy.c */
diff --git a/gas/bignum.h b/gas/bignum.h
index fbb77ffe7e18..d9e0429ddeb0 100644
--- a/gas/bignum.h
+++ b/gas/bignum.h
@@ -1,5 +1,5 @@
 /* bignum.h-arbitrary precision integers
-   Copyright 1987, 1992 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,7 +15,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /***********************************************************************\
  *									*
@@ -39,14 +39,3 @@
 #endif
 
 typedef unsigned short LITTLENUM_TYPE;
-
-/* JF truncated this to get around a problem with GCC */
-#define	LOG_TO_BASE_2_OF_10 (3.3219280948873623478703194294893901758651)
-/* WARNING: I haven't checked that the trailing digits are correct! */
-
-/* lengths are in sizeof(littlenum)s */
-
-int bignum_copy (LITTLENUM_TYPE * in, int in_length,
-		 LITTLENUM_TYPE * out, int out_length);
-
-/* end of bignum.h */
diff --git a/gas/bit_fix.h b/gas/bit_fix.h
index 1676d2c5f0bd..64be49b430a4 100644
--- a/gas/bit_fix.h
+++ b/gas/bit_fix.h
@@ -1,5 +1,5 @@
 /* bit_fix.h
-   Copyright 1987, 1992, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 2000, 2001, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* The bit_fix was implemented to support machines that need variables
    to be inserted in bitfields other than 1, 2 and 4 bytes.
diff --git a/gas/cgen.c b/gas/cgen.c
index 5ce7f4c99ecb..363c05e5318a 100644
--- a/gas/cgen.c
+++ b/gas/cgen.c
@@ -1,5 +1,5 @@
 /* GAS interface for targets using CGEN: Cpu tools GENerator.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free Software
-   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <setjmp.h>
 #include "ansidecl.h"
@@ -225,7 +225,7 @@ gas_cgen_swap_fixups (i)
    At this point we do not use a bfd_reloc_code_real_type for
    operands residing in the insn, but instead just use the
    operand index.  This lets us easily handle fixups for any
-   operand type.  We pick a BFD reloc type in md_apply_fix3.  */
+   operand type.  We pick a BFD reloc type in md_apply_fix.  */
 
 fixS *
 gas_cgen_record_fixup (frag, where, insn, length, operand, opinfo, symbol, offset)
@@ -264,7 +264,7 @@ gas_cgen_record_fixup (frag, where, insn, length, operand, opinfo, symbol, offse
    At this point we do not use a bfd_reloc_code_real_type for
    operands residing in the insn, but instead just use the
    operand index.  This lets us easily handle fixups for any
-   operand type.  We pick a BFD reloc type in md_apply_fix3.  */
+   operand type.  We pick a BFD reloc type in md_apply_fix.  */
 
 fixS *
 gas_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
@@ -320,9 +320,11 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
   /* These are volatile to survive the setjmp.  */
   char * volatile hold;
   enum cgen_parse_operand_result * volatile resultP_1;
+  volatile int opinfo_1;
 #else
   static char *hold;
   static enum cgen_parse_operand_result *resultP_1;
+  int opinfo_1;
 #endif
   const char *errmsg;
   expressionS exp;
@@ -336,6 +338,7 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
   resultP_1 = resultP;
   hold = input_line_pointer;
   input_line_pointer = (char *) *strP;
+  opinfo_1 = opinfo;
 
   /* We rely on md_operand to longjmp back to us.
      This is done via gas_cgen_md_operand.  */
@@ -355,6 +358,10 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
   *strP = input_line_pointer;
   input_line_pointer = hold;
 
+#ifdef TC_CGEN_PARSE_FIX_EXP
+  opinfo_1 = TC_CGEN_PARSE_FIX_EXP (opinfo_1, & exp);
+#endif 
+
   /* FIXME: Need to check `want'.  */
 
   switch (exp.X_op)
@@ -368,6 +375,8 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
       *resultP = CGEN_PARSE_OPERAND_RESULT_ERROR;
       break;
     case O_constant:
+      if (want == CGEN_PARSE_OPERAND_SYMBOLIC)
+	goto de_fault;
       *valueP = exp.X_add_number;
       *resultP = CGEN_PARSE_OPERAND_RESULT_NUMBER;
       break;
@@ -375,8 +384,9 @@ gas_cgen_parse_operand (cd, want, strP, opindex, opinfo, resultP, valueP)
       *valueP = exp.X_add_number;
       *resultP = CGEN_PARSE_OPERAND_RESULT_REGISTER;
       break;
+    de_fault:
     default:
-      queue_fixup (opindex, opinfo, &exp);
+      queue_fixup (opindex, opinfo_1, &exp);
       *valueP = 0;
       *resultP = CGEN_PARSE_OPERAND_RESULT_QUEUED;
       break;
@@ -515,7 +525,7 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
   /* If we're recording insns as numbers (rather than a string of bytes),
      target byte order handling is deferred until now.  */
 #if CGEN_INT_INSN_P
-  cgen_put_insn_value (gas_cgen_cpu_desc, f, length, *buf);
+  cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf);
 #else
   memcpy (f, buf, byte_len);
 #endif
@@ -570,7 +580,7 @@ gas_cgen_finish_insn (insn, buf, length, relax_p, result)
    should handle them all.  */
 
 void
-gas_cgen_md_apply_fix3 (fixP, valP, seg)
+gas_cgen_md_apply_fix (fixP, valP, seg)
      fixS *   fixP;
      valueT * valP;
      segT     seg ATTRIBUTE_UNUSED;
@@ -609,17 +619,19 @@ gas_cgen_md_apply_fix3 (fixP, valP, seg)
 #if CGEN_INT_INSN_P
 	  {
 	    CGEN_INSN_INT insn_value =
-	      cgen_get_insn_value (cd, where, CGEN_INSN_BITSIZE (insn));
+	      cgen_get_insn_value (cd, (unsigned char *) where,
+				   CGEN_INSN_BITSIZE (insn));
 
 	    /* ??? 0 is passed for `pc'.  */
 	    errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields,
 						   &insn_value, (bfd_vma) 0);
-	    cgen_put_insn_value (cd, where, CGEN_INSN_BITSIZE (insn),
-				 insn_value);
+	    cgen_put_insn_value (cd, (unsigned char *) where,
+				 CGEN_INSN_BITSIZE (insn), insn_value);
 	  }
 #else
 	  /* ??? 0 is passed for `pc'.  */
-	  errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields, where,
+	  errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields,
+						 (unsigned char *) where,
 						 (bfd_vma) 0);
 #endif
 	  if (errmsg)
diff --git a/gas/cgen.h b/gas/cgen.h
index 8cf72af4b39b..acb9f48d459b 100644
--- a/gas/cgen.h
+++ b/gas/cgen.h
@@ -1,5 +1,6 @@
 /* GAS cgen support.
-   Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef GAS_CGEN_H
 #define GAS_CGEN_H
@@ -79,8 +80,8 @@ extern fixS * gas_cgen_record_fixup_exp (fragS *, int, const CGEN_INSN *,
 					 int, const CGEN_OPERAND *, int,
 					 expressionS *);
 
-/* md_apply_fix3 handler */
-extern void gas_cgen_md_apply_fix3 (fixS *, valueT *, segT);
+/* md_apply_fix handler */
+extern void gas_cgen_md_apply_fix (fixS *, valueT *, segT);
 
 /* tc_gen_reloc handler */
 extern arelent *gas_cgen_tc_gen_reloc (asection *, fixS *);
diff --git a/gas/cond.c b/gas/cond.c
index 870a7d5bf5c8..d6c32acc2532 100644
--- a/gas/cond.c
+++ b/gas/cond.c
@@ -1,6 +1,6 @@
 /* cond.c - conditional assembly pseudo-ops, and .include
-   Copyright 1990, 1991, 1992, 1993, 1995, 1997, 1998, 2000, 2001
-   Free Software Foundation, Inc.
+   Copyright 1990, 1991, 1992, 1993, 1995, 1997, 1998, 2000, 2001, 2002,
+   2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 #include "macro.h"
@@ -102,7 +102,7 @@ s_ifdef (int test_defined)
 	 considered to be undefined.  */
       is_defined =
 	symbolP != NULL
-	&& S_IS_DEFINED (symbolP)
+	&& (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
 	&& S_GET_SEGMENT (symbolP) != reg_section;
 
       cframe.ignoring = ! (test_defined ^ is_defined);
@@ -144,7 +144,7 @@ s_if (int arg)
     }
   else
     {
-      expression (&operand);
+      expression_and_evaluate (&operand);
       if (operand.X_op != O_constant)
 	as_bad (_("non-constant expression in \".if\" statement"));
     }
@@ -181,6 +181,40 @@ s_if (int arg)
   demand_empty_rest_of_line ();
 }
 
+/* Performs the .ifb (test_blank == 1) and
+   the .ifnb (test_blank == 0) pseudo op.  */
+
+void
+s_ifb (int test_blank)
+{
+  struct conditional_frame cframe;
+
+  initialize_cframe (&cframe);
+  
+  if (cframe.dead_tree)
+    cframe.ignoring = 1;
+  else
+    {
+      int is_eol;
+
+      SKIP_WHITESPACE ();
+      is_eol = is_end_of_line[(unsigned char) *input_line_pointer];
+      cframe.ignoring = (test_blank == !is_eol);
+    }
+
+  current_cframe = ((struct conditional_frame *)
+		    obstack_copy (&cond_obstack, &cframe,
+				  sizeof (cframe)));
+
+  if (LISTING_SKIP_COND ()
+      && cframe.ignoring
+      && (cframe.previous_cframe == NULL
+	  || ! cframe.previous_cframe->ignoring))
+    listing_list (2);
+
+  ignore_rest_of_line ();
+}
+
 /* Get a string for the MRI IFC or IFNC pseudo-ops.  */
 
 static char *
@@ -306,7 +340,7 @@ s_elseif (int arg)
       /* Leading whitespace is part of operand.  */
       SKIP_WHITESPACE ();
 
-      expression (&operand);
+      expression_and_evaluate (&operand);
       if (operand.X_op != O_constant)
 	as_bad (_("non-constant expression in \".elseif\" statement"));
 
diff --git a/gas/config-gas.com b/gas/config-gas.com
deleted file mode 100644
index cf5248af5da9..000000000000
--- a/gas/config-gas.com
+++ /dev/null
@@ -1,186 +0,0 @@
-$!config-gas.com
-$! This file sets things up to build gas on a VMS system to generate object
-$! files for a VMS system.  We do not use the configure script, since we
-$! do not have /bin/sh to execute it.
-$!
-$!
-$ gas_host="vms"
-$ arch_indx = 1 + ((f$getsyi("CPU").ge.128).and.1)	! vax==1, alpha==2
-$ arch = f$element(arch_indx,"|","|VAX|Alpha|")
-$ if arch.eqs."VAX"
-$ then
-$  cpu_type="vax"
-$  obj_format="vms"
-$  atof="vax"
-$ else
-$  cpu_type="alpha"
-$  obj_format="evax"
-$  atof="ieee"
-$ endif
-$ emulation="generic"
-$!
-$	DELETE	= "delete/noConfirm"
-$	ECHO	= "write sys$output"
-$!
-$! Target specific information
-$ call make "targ-cpu.h" "[.config]tc-''cpu_type'.h"
-$ call make "targ-env.h" "[.config]te-''emulation'.h"
-$!
-$! Code to handle the object file format.
-$ call make "obj-format.h" "[.config]obj-''obj_format'.h"
-$!
-$! (not currently used for vax or alpha)
-$ call make "itbl-cpu.h" "[.config]itbl-''cpu_type'.h"
-$!
-$!
-$! Create the file version.opt, which helps identify the executable.
-$!
-$if f$trnlnm("IFILE$").nes."" then  close/noLog ifile$
-$search CONFIGURE.IN "AM_INIT_AUTOMAKE"/Exact/Output=config-gas-tmp.tmp
-$open ifile$ config-gas-tmp.tmp
-$read ifile$ line
-$close ifile$
-$DELETE config-gas-tmp.tmp;*
-$! Discard "AM_INIT_AUTOMAKE(gas, " and ")" parts.
-$ijk=f$locate(",",line)+2
-$line=f$extract(ijk,f$length(line)-ijk,line)
-$ijk=f$locate(")",line)
-$line=f$extract(0,ijk,line)
-$!
-$ if f$search("version.opt").nes."" then DELETE version.opt;*
-$copy _NL: version.opt
-$open/Append ifile$ version.opt
-$write ifile$ "identification="+""""+line+""""
-$close ifile$
-$!
-$! Now write config.h.
-$!
-$ if f$search("config.h").nes."" then DELETE config.h;*
-$copy _NL: config.h
-$open/Append ifile$ config.h
-$write ifile$ "/* config.h.  Generated by config-gas.com. */
-$write ifile$ "#ifndef VERSION"
-$write ifile$ "#define VERSION      """,line,""""
-$write ifile$ "#endif"
-$write ifile$ "/*--*/"
-$if arch .eqs. "VAX"
-$then
-$append [.config]vms-conf.h ifile$:
-$else
-$ append [.config]vms-a-conf.h ifile$:
-$endif
-$close ifile$
-$ECHO "Created config.h."
-$!
-$! Check for, and possibly make, header file <unistd.h>.
-$!
-$ if f$search("tmp-chk-h.*").nes."" then  DELETE tmp-chk-h.*;*
-$!can't use simple `#include HDR' with `gcc /Define="HDR=<foo.h>"'
-$!because the 2.6.[0-3] preprocessor handles it wrong (VMS-specific gcc bug)
-$ create tmp-chk-h.c
-int tmp_chk_h;	/* guarantee non-empty output */
-#ifdef HAVE_STDIO_H
-#include <stdio.h>
-#endif
-#ifdef HAVE_UNISTD_H
-#include <unistd.h>
-#endif
-#ifdef HAVE_UNIXIO_H
-#include <unixio.h>
-#endif
-#ifdef HAVE_UNIXLIB_H
-#include <unixlib.h>
-#endif
-$ on warning then  continue
-$ CHECK = "call tmp_chk_h"
-$ CHECK "HAVE_STDIO_H"
-$ if .not.$status
-$ then	type sys$input:
-
-? could not compile <stdio.h>.
-
-  If you're compiling with DEC C or VAX C, create config.status as an
-  empty file and start gnu make again.
-
-  If you're compiling with GNU C, there is some setup problem and
-  gas configuration cannot proceed.
-
-$	DELETE tmp-chk-h.c;*
-$	exit %x002C
-$ endif
-$!
-$ CHECK "HAVE_UNISTD_H"
-$ if .not.$status
-$ then
-$  if f$trnlnm("HFILE$").nes."" then  close/noLog hfile$
-$  CHECK "HAVE_UNIXIO_H"
-$  got_unixio = ($status .and. 1)
-$  CHECK "HAVE_UNIXLIB_H"
-$  got_unixlib = ($status .and. 1)
-$  create []unistd.h	!with rudimentary contents
-/* <unistd.h> substitute for building gas */
-#ifndef UNISTD_H
-#define UNISTD_H
-
-$  open/Append hfile$ []unistd.h
-$  if got_unixio
-$  then  write hfile$ "#include <unixio.h>"
-$  else  append sys$input: hfile$:
-/* some of the routines normally prototyped in <unixio.h> */
-extern int creat(), open(), close(), read(), write();
-extern int access(), dup(), dup2(), fstat(), stat();
-extern long lseek();
-$  endif
-$  write hfile$ ""
-$  if got_unixlib
-$  then  write hfile$ "#include <unixlib.h>"
-$  else  append sys$input: hfile$:
-/* some of the routines normally prototyped in <unixlib.h> */
-extern char *sbrk(), *getcwd(), *cuserid();
-extern int brk(), chdir(), chmod(), chown(), mkdir();
-extern unsigned getuid(), umask();
-$  endif
-$  append sys$input: hfile$:
-
-#endif /*UNISTD_H*/
-$  close hfile$
-$  ECHO "Created ""[]unistd.h""."
-$ endif !gcc '#include <unistd.h>' failed
-$ DELETE tmp-chk-h.c;*
-$
-$tmp_chk_h: subroutine
-$  set noOn
-$  hname = f$edit("<" + (p1 - "HAVE_" - "_H") + ".h>","LOWERCASE")
-$  write sys$output "Checking for ''hname'."
-$  if f$search("tmp-chk-h.obj").nes."" then  DELETE tmp-chk-h.obj;*
-$  define/noLog sys$error _NL:	!can't use /User_Mode here due to gcc
-$  define/noLog sys$output _NL:	! driver's use of multiple image activation
-$  gcc /Include=([],[-.include]) /Define=("''p1'") tmp-chk-h.c
-$!can't just check $status; gcc 2.6.[0-3] preprocessor doesn't set it correctly
-$  ok = (($status.and.1).and.(f$search("tmp-chk-h.obj").nes."")) .or. %x10000000
-$  deassign sys$error	!restore, more or less
-$  deassign sys$output
-$  if ok then  DELETE tmp-chk-h.obj;*
-$  exit ok
-$ endsubroutine !tmp_chk_h
-$
-$!
-$! Done
-$!
-$ if f$search("config.status") .nes. "" then DELETE config.status;*
-$ open/write cfile []config.status
-$ write cfile "Links are now set up for use with a "+arch+" running VMS."
-$ close cfile
-$ type []config.status
-$exit
-$!
-$!
-$make: subroutine
-$  if f$search(p1).nes."" then DELETE 'p1';*
-$  create 'p1'
-$  if f$trnlnm("IFILE$").nes."" then  close/noLog ifile$
-$  open/Append ifile$ 'p1'
-$  write ifile$ "#include ""''f$string(p2 - "[.config]")'"""
-$  close ifile$
-$  ECHO "Created ''p1' for ''p2'."
-$endsubroutine !make
diff --git a/gas/config.in b/gas/config.in
index fe2bc3fbcfbc..b15d8024aba2 100644
--- a/gas/config.in
+++ b/gas/config.in
@@ -1,188 +1,203 @@
-/* config.in.  Generated automatically from configure.in by autoheader.  */
+/* config.in.  Generated from configure.in by autoheader.  */
 
-/* Define if using alloca.c.  */
-#undef C_ALLOCA
+/* Define if using AIX 5.2 value for C_WEAKEXT. */
+#undef AIX_WEAK_SUPPORT
 
-/* Define to empty if the keyword does not work.  */
-#undef const
+/* assert broken? */
+#undef BROKEN_ASSERT
 
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
+/* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP
+   systems. This function is required for `alloca.c' support on those systems.
+   */
 #undef CRAY_STACKSEG_END
 
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
+/* Compiling cross-assembler? */
+#undef CROSS_COMPILE
 
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
+/* Define to 1 if using `alloca.c'. */
+#undef C_ALLOCA
 
-/* Define if you have a working `mmap' system call.  */
-#undef HAVE_MMAP
+/* Default architecture. */
+#undef DEFAULT_ARCH
 
-/* Define as __inline if that's what the C compiler calls it.  */
-#undef inline
+/* Default CRIS architecture. */
+#undef DEFAULT_CRIS_ARCH
 
-/* Define to `long' if <sys/types.h> doesn't define.  */
-#undef off_t
+/* Default emulation. */
+#undef DEFAULT_EMULATION
 
-/* Define to `unsigned' if <sys/types.h> doesn't define.  */
-#undef size_t
+/* Supported emulations. */
+#undef EMULATIONS
 
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#undef STACK_DIRECTION
+/* Define to 1 if NLS is requested */
+#undef ENABLE_NLS
 
-/* Define if you have the ANSI C header files.  */
-#undef STDC_HEADERS
+/* Define to 1 if you have `alloca', as a function or macro. */
+#undef HAVE_ALLOCA
 
-/* Define if lex declares yytext as a char * by default, not a char[].  */
-#undef YYTEXT_POINTER
+/* Define to 1 if you have <alloca.h> and it should be used (not on Ultrix).
+   */
+#undef HAVE_ALLOCA_H
 
-/* Define if you have the __argz_count function.  */
-#undef HAVE___ARGZ_COUNT
+/* Define to 1 if you have the <argz.h> header file. */
+#undef HAVE_ARGZ_H
 
-/* Define if you have the __argz_next function.  */
-#undef HAVE___ARGZ_NEXT
+/* Define to 1 if you have the `dcgettext' function. */
+#undef HAVE_DCGETTEXT
 
-/* Define if you have the __argz_stringify function.  */
-#undef HAVE___ARGZ_STRINGIFY
+/* Is the prototype for getopt in <unistd.h> in the expected format? */
+#undef HAVE_DECL_GETOPT
 
-/* Define if you have the dcgettext function.  */
-#undef HAVE_DCGETTEXT
+/* Define to 1 if you have the declaration of `vsnprintf', and to 0 if you
+   don't. */
+#undef HAVE_DECL_VSNPRINTF
 
-/* Define if you have the getcwd function.  */
+/* Define to 1 if you have the <errno.h> header file. */
+#undef HAVE_ERRNO_H
+
+/* Define to 1 if you have the `getcwd' function. */
 #undef HAVE_GETCWD
 
-/* Define if you have the getpagesize function.  */
+/* Define to 1 if you have the `getpagesize' function. */
 #undef HAVE_GETPAGESIZE
 
-/* Define if you have the munmap function.  */
-#undef HAVE_MUNMAP
-
-/* Define if you have the putenv function.  */
-#undef HAVE_PUTENV
-
-/* Define if you have the remove function.  */
-#undef HAVE_REMOVE
+/* Define as 1 if you have gettext and don't want to use GNU gettext. */
+#undef HAVE_GETTEXT
 
-/* Define if you have the sbrk function.  */
-#undef HAVE_SBRK
+/* Define to 1 if you have the <inttypes.h> header file. */
+#undef HAVE_INTTYPES_H
 
-/* Define if you have the setenv function.  */
-#undef HAVE_SETENV
+/* Define if your locale.h file contains LC_MESSAGES. */
+#undef HAVE_LC_MESSAGES
 
-/* Define if you have the setlocale function.  */
-#undef HAVE_SETLOCALE
+/* Define to 1 if you have the <limits.h> header file. */
+#undef HAVE_LIMITS_H
 
-/* Define if you have the stpcpy function.  */
-#undef HAVE_STPCPY
+/* Define to 1 if you have the <locale.h> header file. */
+#undef HAVE_LOCALE_H
 
-/* Define if you have the strcasecmp function.  */
-#undef HAVE_STRCASECMP
+/* Define to 1 if you have the <malloc.h> header file. */
+#undef HAVE_MALLOC_H
 
-/* Define if you have the strchr function.  */
-#undef HAVE_STRCHR
+/* Define to 1 if you have the <memory.h> header file. */
+#undef HAVE_MEMORY_H
 
-/* Define if you have the unlink function.  */
-#undef HAVE_UNLINK
+/* Define to 1 if you have a working `mmap' system call. */
+#undef HAVE_MMAP
 
-/* Define if you have the <argz.h> header file.  */
-#undef HAVE_ARGZ_H
+/* Define to 1 if you have the `munmap' function. */
+#undef HAVE_MUNMAP
 
-/* Define if you have the <errno.h> header file.  */
-#undef HAVE_ERRNO_H
+/* Define to 1 if you have the <nl_types.h> header file. */
+#undef HAVE_NL_TYPES_H
 
-/* Define if you have the <limits.h> header file.  */
-#undef HAVE_LIMITS_H
+/* Define to 1 if you have the `putenv' function. */
+#undef HAVE_PUTENV
 
-/* Define if you have the <locale.h> header file.  */
-#undef HAVE_LOCALE_H
+/* Define to 1 if you have the `remove' function. */
+#undef HAVE_REMOVE
 
-/* Define if you have the <malloc.h> header file.  */
-#undef HAVE_MALLOC_H
+/* Define to 1 if you have the `sbrk' function. */
+#undef HAVE_SBRK
 
-/* Define if you have the <memory.h> header file.  */
-#undef HAVE_MEMORY_H
+/* Define to 1 if you have the `setenv' function. */
+#undef HAVE_SETENV
 
-/* Define if you have the <nl_types.h> header file.  */
-#undef HAVE_NL_TYPES_H
+/* Define to 1 if you have the `setlocale' function. */
+#undef HAVE_SETLOCALE
 
-/* Define if you have the <stdarg.h> header file.  */
+/* Define to 1 if you have the <stdarg.h> header file. */
 #undef HAVE_STDARG_H
 
-/* Define if you have the <stdlib.h> header file.  */
+/* Define to 1 if you have the <stdint.h> header file. */
+#undef HAVE_STDINT_H
+
+/* Define to 1 if you have the <stdlib.h> header file. */
 #undef HAVE_STDLIB_H
 
-/* Define if you have the <string.h> header file.  */
-#undef HAVE_STRING_H
+/* Define if you have the stpcpy function */
+#undef HAVE_STPCPY
+
+/* Define to 1 if you have the `strcasecmp' function. */
+#undef HAVE_STRCASECMP
 
-/* Define if you have the <strings.h> header file.  */
+/* Define to 1 if you have the `strchr' function. */
+#undef HAVE_STRCHR
+
+/* Define to 1 if you have the <strings.h> header file. */
 #undef HAVE_STRINGS_H
 
-/* Define if you have the <sys/param.h> header file.  */
+/* Define to 1 if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define to 1 if you have the <sys/param.h> header file. */
 #undef HAVE_SYS_PARAM_H
 
-/* Define if you have the <sys/types.h> header file.  */
+/* Define to 1 if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define to 1 if you have the <sys/types.h> header file. */
 #undef HAVE_SYS_TYPES_H
 
-/* Define if you have the <unistd.h> header file.  */
+/* Define to 1 if you have the <unistd.h> header file. */
 #undef HAVE_UNISTD_H
 
-/* Define if you have the <values.h> header file.  */
+/* Define to 1 if you have the `unlink' function. */
+#undef HAVE_UNLINK
+
+/* Define to 1 if you have the <values.h> header file. */
 #undef HAVE_VALUES_H
 
-/* Define if you have the <varargs.h> header file.  */
+/* Define to 1 if you have the <varargs.h> header file. */
 #undef HAVE_VARARGS_H
 
-/* Name of package */
-#undef PACKAGE
+/* Define to 1 if you have the `__argz_count' function. */
+#undef HAVE___ARGZ_COUNT
 
-/* Version number of package */
-#undef VERSION
+/* Define to 1 if you have the `__argz_next' function. */
+#undef HAVE___ARGZ_NEXT
 
-/* Define if defaulting to ELF on SCO 5. */
-#undef SCO_ELF
+/* Define to 1 if you have the `__argz_stringify' function. */
+#undef HAVE___ARGZ_STRINGIFY
 
-/* Using strict COFF? */
-#undef STRICTCOFF
+/* Using i386 COFF? */
+#undef I386COFF
 
-/* Define if default target is PowerPC Solaris. */
-#undef TARGET_SOLARIS_COMMENT
+/* Using m68k COFF? */
+#undef M68KCOFF
 
-/* Define as 1 if big endian. */
-#undef TARGET_BYTES_BIG_ENDIAN
+/* Using m88k COFF? */
+#undef M88KCOFF
 
-/* Default CPU for MIPS targets.  */
+/* Default CPU for MIPS targets. */
 #undef MIPS_CPU_STRING_DEFAULT
 
-/* Allow use of E_MIPS_ABI_O32 on MIPS targets.  */
-#undef USE_E_MIPS_ABI_O32
-
-/* Generate 64-bit code by default on MIPS targets.  */
+/* Generate 64-bit code by default on MIPS targets. */
 #undef MIPS_DEFAULT_64BIT
 
-/* Choose a default ABI for MIPS targets.  */
+/* Choose a default ABI for MIPS targets. */
 #undef MIPS_DEFAULT_ABI
 
-/* Default architecture. */
-#undef DEFAULT_ARCH
+/* Define if environ is not declared in system header files. */
+#undef NEED_DECLARATION_ENVIRON
 
-/* Using cgen code? */
-#undef USING_CGEN
+/* Define if errno is not declared in system header files. */
+#undef NEED_DECLARATION_ERRNO
 
-/* Using i386 COFF? */
-#undef I386COFF
+/* Define if ffs is not declared in system header files. */
+#undef NEED_DECLARATION_FFS
 
-/* Using m68k COFF? */
-#undef M68KCOFF
+/* Define if free is not declared in system header files. */
+#undef NEED_DECLARATION_FREE
 
-/* Using m88k COFF? */
-#undef M88KCOFF
+/* Define if malloc is not declared in system header files. */
+#undef NEED_DECLARATION_MALLOC
+
+/* Define if sbrk is not declared in system header files. */
+#undef NEED_DECLARATION_SBRK
+
+/* Define if strstr is not declared in system header files. */
+#undef NEED_DECLARATION_STRSTR
 
 /* a.out support? */
 #undef OBJ_MAYBE_AOUT
@@ -202,81 +217,102 @@
 /* generic support? */
 #undef OBJ_MAYBE_GENERIC
 
-/* HP300 support? */
-#undef OBJ_MAYBE_HP300
-
 /* IEEE support? */
 #undef OBJ_MAYBE_IEEE
 
 /* SOM support? */
 #undef OBJ_MAYBE_SOM
 
-/* VMS support? */
-#undef OBJ_MAYBE_VMS
+/* Name of package */
+#undef PACKAGE
 
-/* Use emulation support? */
-#undef USE_EMULATIONS
+/* Define to the address where bug reports for this package should be sent. */
+#undef PACKAGE_BUGREPORT
 
-/* Supported emulations. */
-#undef EMULATIONS
+/* Define to the full name of this package. */
+#undef PACKAGE_NAME
 
-/* Default emulation. */
-#undef DEFAULT_EMULATION
+/* Define to the full name and version of this package. */
+#undef PACKAGE_STRING
+
+/* Define to the one symbol short name of this package. */
+#undef PACKAGE_TARNAME
+
+/* Define to the version of this package. */
+#undef PACKAGE_VERSION
+
+/* Define if defaulting to ELF on SCO 5. */
+#undef SCO_ELF
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+	STACK_DIRECTION > 0 => grows toward higher addresses
+	STACK_DIRECTION < 0 => grows toward lower addresses
+	STACK_DIRECTION = 0 => direction of growth unknown */
+#undef STACK_DIRECTION
 
-/* old COFF support? */
-#undef MANY_SEGMENTS
+/* Define to 1 if you have the ANSI C header files. */
+#undef STDC_HEADERS
 
-/* Use BFD interface? */
-#undef BFD_ASSEMBLER
+/* Using strict COFF? */
+#undef STRICTCOFF
 
 /* Target alias. */
 #undef TARGET_ALIAS
 
+/* Define as 1 if big endian. */
+#undef TARGET_BYTES_BIG_ENDIAN
+
 /* Canonical target. */
 #undef TARGET_CANONICAL
 
 /* Target CPU. */
 #undef TARGET_CPU
 
-/* Target vendor. */
-#undef TARGET_VENDOR
-
 /* Target OS. */
 #undef TARGET_OS
 
-/* Define if you have the stpcpy function */
-#undef HAVE_STPCPY
+/* Define if default target is PowerPC Solaris. */
+#undef TARGET_SOLARIS_COMMENT
 
-/* Define if your locale.h file contains LC_MESSAGES. */
-#undef HAVE_LC_MESSAGES
+/* Define if target is Symbian OS. */
+#undef TARGET_SYMBIAN
 
-/* Define to 1 if NLS is requested */
-#undef ENABLE_NLS
+/* Target vendor. */
+#undef TARGET_VENDOR
 
-/* Define as 1 if you have gettext and don't want to use GNU gettext. */
-#undef HAVE_GETTEXT
+/* Use emulation support? */
+#undef USE_EMULATIONS
 
-/* Compiling cross-assembler? */
-#undef CROSS_COMPILE
+/* Allow use of E_MIPS_ABI_O32 on MIPS targets. */
+#undef USE_E_MIPS_ABI_O32
 
-/* assert broken? */
-#undef BROKEN_ASSERT
+/* Using cgen code? */
+#undef USING_CGEN
 
-/* Define if strstr is not declared in system header files. */
-#undef NEED_DECLARATION_STRSTR
+/* Version number of package */
+#undef VERSION
 
-/* Define if malloc is not declared in system header files. */
-#undef NEED_DECLARATION_MALLOC
+/* Define to 1 if your processor stores words with the most significant byte
+   first (like Motorola and SPARC, unlike Intel and VAX). */
+#undef WORDS_BIGENDIAN
 
-/* Define if free is not declared in system header files. */
-#undef NEED_DECLARATION_FREE
+/* Define to 1 if `lex' declares `yytext' as a `char *' by default, not a
+   `char[]'. */
+#undef YYTEXT_POINTER
 
-/* Define if sbrk is not declared in system header files. */
-#undef NEED_DECLARATION_SBRK
+/* Define to empty if `const' does not conform to ANSI C. */
+#undef const
 
-/* Define if environ is not declared in system header files. */
-#undef NEED_DECLARATION_ENVIRON
+/* Define to `__inline__' or `__inline' if that's what the C compiler
+   calls it, or to nothing if 'inline' is not supported under any name.  */
+#ifndef __cplusplus
+#undef inline
+#endif
 
-/* Define if errno is not declared in system header files. */
-#undef NEED_DECLARATION_ERRNO
+/* Define to `long' if <sys/types.h> does not define. */
+#undef off_t
 
+/* Define to `unsigned' if <sys/types.h> does not define. */
+#undef size_t
diff --git a/gas/config/aout_gnu.h b/gas/config/aout_gnu.h
index 0942fd34a9b9..e17fda9465bc 100644
--- a/gas/config/aout_gnu.h
+++ b/gas/config/aout_gnu.h
@@ -1,6 +1,6 @@
 /* This file is aout_gnu.h
 
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 2000
+   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 2000, 2002
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,7 +17,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #ifndef __A_OUT_GNU_H__
 #define __A_OUT_GNU_H__
@@ -26,15 +26,15 @@
    relocations, and one which uses extended relocations.
 
    Today, the extended reloc uses are
-   TC_SPARC, TC_A29K
+   TC_SPARC
 
    each must define the enum reloc_type
 
 */
 
-#define USE_EXTENDED_RELOC (defined(TC_SPARC) || defined(TC_A29K))
+#define USE_EXTENDED_RELOC defined(TC_SPARC)
 
-#if defined(TC_SPARC) || defined(TC_A29K)
+#if defined(TC_SPARC)
 enum reloc_type
   {
     RELOC_8, RELOC_16, RELOC_32,/* simple relocations */
@@ -62,7 +62,7 @@ enum reloc_type
     NO_RELOC
   };
 
-#endif /* TC_SPARC or TC_A29K */
+#endif /* TC_SPARC */
 
 #define __GNU_EXEC_MACROS__
 
diff --git a/gas/config/atof-ieee.c b/gas/config/atof-ieee.c
index 0ad39c9b3011..bf842e1717db 100644
--- a/gas/config/atof-ieee.c
+++ b/gas/config/atof-ieee.c
@@ -1,5 +1,5 @@
 /* atof_ieee.c - turn a Flonum into an IEEE floating point number
-   Copyright 1987, 1992, 1994, 1996, 1997, 1998, 1999, 2000, 2001
+   Copyright 1987, 1992, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,29 +16,25 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
 /* Flonums returned here.  */
 extern FLONUM_TYPE generic_floating_point_number;
 
-static int next_bits PARAMS ((int));
-static void unget_bits PARAMS ((int));
-static void make_invalid_floating_point_number PARAMS ((LITTLENUM_TYPE *));
-
 extern const char EXP_CHARS[];
 /* Precision in LittleNums.  */
 /* Don't count the gap in the m68k extended precision format.  */
-#define MAX_PRECISION (5)
-#define F_PRECISION (2)
-#define D_PRECISION (4)
-#define X_PRECISION (5)
-#define P_PRECISION (5)
+#define MAX_PRECISION  5
+#define F_PRECISION    2
+#define D_PRECISION    4
+#define X_PRECISION    5
+#define P_PRECISION    5
 
 /* Length in LittleNums of guard bits.  */
-#define GUARD (2)
+#define GUARD          2
 
 #ifndef TC_LARGEST_EXPONENT_IS_NORMAL
 #define TC_LARGEST_EXPONENT_IS_NORMAL(PRECISION) 0
@@ -86,13 +82,13 @@ static int littlenums_left;
 static LITTLENUM_TYPE *littlenum_pointer;
 
 static int
-next_bits (number_of_bits)
-     int number_of_bits;
+next_bits (int number_of_bits)
 {
   int return_value;
 
   if (!littlenums_left)
-    return (0);
+    return 0;
+
   if (number_of_bits >= bits_left_in_littlenum)
     {
       return_value = mask[bits_left_in_littlenum] & *littlenum_pointer;
@@ -120,8 +116,7 @@ next_bits (number_of_bits)
 /* Num had better be less than LITTLENUM_NUMBER_OF_BITS.  */
 
 static void
-unget_bits (num)
-     int num;
+unget_bits (int num)
 {
   if (!littlenums_left)
     {
@@ -141,8 +136,7 @@ unget_bits (num)
 }
 
 static void
-make_invalid_floating_point_number (words)
-     LITTLENUM_TYPE *words;
+make_invalid_floating_point_number (LITTLENUM_TYPE *words)
 {
   as_bad (_("cannot create floating-point number"));
   /* Zero the leftmost bit.  */
@@ -165,10 +159,9 @@ make_invalid_floating_point_number (words)
 /* Returns pointer past text consumed.  */
 
 char *
-atof_ieee (str, what_kind, words)
-     char *str;			/* Text to convert to binary.  */
-     int what_kind;		/* 'd', 'f', 'g', 'h'.  */
-     LITTLENUM_TYPE *words;	/* Build the binary here.  */
+atof_ieee (char *str,			/* Text to convert to binary.  */
+	   int what_kind,		/* 'd', 'f', 'g', 'h'.  */
+	   LITTLENUM_TYPE *words)	/* Build the binary here.  */
 {
   /* Extra bits for zeroed low-order bits.
      The 1st MAX_PRECISION are zeroed, the last contain flonum bits.  */
@@ -242,7 +235,7 @@ atof_ieee (str, what_kind, words)
 		    &generic_floating_point_number))
     {
       make_invalid_floating_point_number (words);
-      return (NULL);
+      return NULL;
     }
   gen_to_words (words, precision, exponent_bits);
 
@@ -256,10 +249,7 @@ atof_ieee (str, what_kind, words)
 /* Turn generic_floating_point_number into a real float/double/extended.  */
 
 int
-gen_to_words (words, precision, exponent_bits)
-     LITTLENUM_TYPE *words;
-     int precision;
-     long exponent_bits;
+gen_to_words (LITTLENUM_TYPE *words, int precision, long exponent_bits)
 {
   int return_value = 0;
 
@@ -673,35 +663,11 @@ gen_to_words (words, precision, exponent_bits)
 	     but return a floating exception because we can't encode
 	     the number.  */
 	  *words &= ~(1 << (LITTLENUM_NUMBER_OF_BITS - 1));
-#if 0
-	  make_invalid_floating_point_number (words);
-	  return return_value;
-#endif
 	}
     }
   return return_value;
 }
 
-#if 0
-/* Unused.  */
-/* This routine is a real kludge.  Someone really should do it better,
-   but I'm too lazy, and I don't understand this stuff all too well
-   anyway. (JF)  */
-
-static void
-int_to_gen (x)
-     long x;
-{
-  char buf[20];
-  char *bufp;
-
-  sprintf (buf, "%ld", x);
-  bufp = &buf[0];
-  if (atof_generic (&bufp, ".", EXP_CHARS, &generic_floating_point_number))
-    as_bad (_("Error converting number to floating point (Exponent overflow?)"));
-}
-#endif
-
 #ifdef TEST
 char *
 print_gen (gen)
diff --git a/gas/config/atof-tahoe.c b/gas/config/atof-tahoe.c
deleted file mode 100644
index 11bea1004419..000000000000
--- a/gas/config/atof-tahoe.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/* atof_tahoe.c - turn a string into a Tahoe floating point number
-   Copyright 1987, 1993, 2000 Free Software Foundation, Inc.
-
-/* This is really a simplified version of atof_vax.c. I glommed it wholesale
-   and then shaved it down. I don't even know how it works. (Don't you find
-   my honesty refreshing?  Devon E Bowen <bowen@cs.buffalo.edu>
-
-   I don't allow uppercase letters in the precision descriptors.
-   i.e. 'f' and 'd' are allowed but 'F' and 'D' aren't.  */
-
-#include "as.h"
-
-/* Precision in LittleNums.  */
-#define MAX_PRECISION (4)
-#define D_PRECISION (4)
-#define F_PRECISION (2)
-
-/* Precision in chars.  */
-#define D_PRECISION_CHARS (8)
-#define F_PRECISION_CHARS (4)
-
-/* Length in LittleNums of guard bits.  */
-#define GUARD (2)
-
-static const long int mask[] =
-{
-  0x00000000,
-  0x00000001,
-  0x00000003,
-  0x00000007,
-  0x0000000f,
-  0x0000001f,
-  0x0000003f,
-  0x0000007f,
-  0x000000ff,
-  0x000001ff,
-  0x000003ff,
-  0x000007ff,
-  0x00000fff,
-  0x00001fff,
-  0x00003fff,
-  0x00007fff,
-  0x0000ffff,
-  0x0001ffff,
-  0x0003ffff,
-  0x0007ffff,
-  0x000fffff,
-  0x001fffff,
-  0x003fffff,
-  0x007fffff,
-  0x00ffffff,
-  0x01ffffff,
-  0x03ffffff,
-  0x07ffffff,
-  0x0fffffff,
-  0x1fffffff,
-  0x3fffffff,
-  0x7fffffff,
-  0xffffffff
-};
-
-/* Shared between flonum_gen2tahoe and next_bits.  */
-static int bits_left_in_littlenum;
-static LITTLENUM_TYPE *littlenum_pointer;
-static LITTLENUM_TYPE *littlenum_end;
-
-#if __STDC__ == 1
-
-int flonum_gen2tahoe (int format_letter, FLONUM_TYPE * f,
-		      LITTLENUM_TYPE * words);
-
-#else /* not __STDC__  */
-
-int flonum_gen2tahoe ();
-
-#endif /* not __STDC__  */
-
-static int
-next_bits (number_of_bits)
-     int number_of_bits;
-{
-  int return_value;
-
-  if (littlenum_pointer < littlenum_end)
-    return 0;
-  if (number_of_bits >= bits_left_in_littlenum)
-    {
-      return_value = mask[bits_left_in_littlenum] & *littlenum_pointer;
-      number_of_bits -= bits_left_in_littlenum;
-      return_value <<= number_of_bits;
-      bits_left_in_littlenum = LITTLENUM_NUMBER_OF_BITS - number_of_bits;
-      littlenum_pointer--;
-      if (littlenum_pointer >= littlenum_end)
-	return_value |= ((*littlenum_pointer) >> (bits_left_in_littlenum)) &
-	  mask[number_of_bits];
-    }
-  else
-    {
-      bits_left_in_littlenum -= number_of_bits;
-      return_value = mask[number_of_bits] &
-	((*littlenum_pointer) >> bits_left_in_littlenum);
-    }
-  return return_value;
-}
-
-static void
-make_invalid_floating_point_number (words)
-     LITTLENUM_TYPE *words;
-{
-  /* Floating Reserved Operand Code.  */
-  *words = 0x8000;
-}
-
-static int			/* 0 means letter is OK.  */
-what_kind_of_float (letter, precisionP, exponent_bitsP)
-     /* In: lowercase please. What kind of float?  */
-     char letter;
-
-     /* Number of 16-bit words in the float.  */
-     int *precisionP;
-
-     /* Number of exponent bits.  */
-     long int *exponent_bitsP;
-{
-  int retval;			/* 0: OK.  */
-
-  retval = 0;
-  switch (letter)
-    {
-    case 'f':
-      *precisionP = F_PRECISION;
-      *exponent_bitsP = 8;
-      break;
-
-    case 'd':
-      *precisionP = D_PRECISION;
-      *exponent_bitsP = 8;
-      break;
-
-    default:
-      retval = 69;
-      break;
-    }
-  return (retval);
-}
-
-/* Warning: This returns 16-bit LITTLENUMs, because that is what the
-   VAX thinks in.  It is up to the caller to figure out any alignment
-   problems and to conspire for the bytes/word to be emitted in the
-   right order. Bigendians beware!  */
-
-char *				/* Return pointer past text consumed.  */
-atof_tahoe (str, what_kind, words)
-     char *str;			/* Text to convert to binary.  */
-     char what_kind;		/* 'd', 'f', 'g', 'h' */
-     LITTLENUM_TYPE *words;	/* Build the binary here.  */
-{
-  FLONUM_TYPE f;
-  LITTLENUM_TYPE bits[MAX_PRECISION + MAX_PRECISION + GUARD];
-  /* Extra bits for zeroed low-order bits.  */
-  /* The 1st MAX_PRECISION are zeroed, the last contain flonum bits.  */
-  char *return_value;
-  int precision;		/* Number of 16-bit words in the format.  */
-  long int exponent_bits;
-
-  return_value = str;
-  f.low = bits + MAX_PRECISION;
-  f.high = NULL;
-  f.leader = NULL;
-  f.exponent = NULL;
-  f.sign = '\0';
-
-  if (what_kind_of_float (what_kind, &precision, &exponent_bits))
-    {
-      /* We lost.  */
-      return_value = NULL;
-      make_invalid_floating_point_number (words);
-    }
-  if (return_value)
-    {
-      memset (bits, '\0', sizeof (LITTLENUM_TYPE) * MAX_PRECISION);
-
-      /* Use more LittleNums than seems necessary:
-	 the highest flonum may have 15 leading 0 bits, so could be
-	 useless.  */
-      f.high = f.low + precision - 1 + GUARD;
-
-      if (atof_generic (&return_value, ".", "eE", &f))
-	{
-	  make_invalid_floating_point_number (words);
-	  /* We lost.  */
-	  return_value = NULL;
-	}
-      else
-	{
-	  if (flonum_gen2tahoe (what_kind, &f, words))
-	    return_value = NULL;
-	}
-    }
-  return return_value;
-}
-
-/* In: a flonum, a Tahoe floating point format.
-   Out: a Tahoe floating-point bit pattern.  */
-
-int				/* 0: OK.  */
-flonum_gen2tahoe (format_letter, f, words)
-     char format_letter;	/* One of 'd' 'f'.  */
-     FLONUM_TYPE *f;
-     LITTLENUM_TYPE *words;	/* Deliver answer here.  */
-{
-  LITTLENUM_TYPE *lp;
-  int precision;
-  long int exponent_bits;
-  int return_value;		/* 0 == OK.  */
-
-  return_value =
-    what_kind_of_float (format_letter, &precision, &exponent_bits);
-  if (return_value != 0)
-    {
-      make_invalid_floating_point_number (words);
-    }
-  else
-    {
-      if (f->low > f->leader)
-	{
-	  /* 0.0e0 seen.  */
-	  memset (words, '\0', sizeof (LITTLENUM_TYPE) * precision);
-	}
-      else
-	{
-	  long int exponent_1;
-	  long int exponent_2;
-	  long int exponent_3;
-	  long int exponent_4;
-	  int exponent_skippage;
-	  LITTLENUM_TYPE word1;
-
-	  /* JF: Deal with new Nan, +Inf and -Inf codes.  */
-	  if (f->sign != '-' && f->sign != '+')
-	    {
-	      make_invalid_floating_point_number (words);
-	      return return_value;
-	    }
-	  /* All tahoe floating_point formats have:
-	     Bit 15 is sign bit.
-	     Bits 14:n are excess-whatever exponent.
-	     Bits n-1:0 (if any) are most significant bits of fraction.
-	     Bits 15:0 of the next word are the next most significant bits.
-	     And so on for each other word.
-
-	     So we need: number of bits of exponent, number of bits of
-	     mantissa.  */
-
-	  bits_left_in_littlenum = LITTLENUM_NUMBER_OF_BITS;
-	  littlenum_pointer = f->leader;
-	  littlenum_end = f->low;
-
-	  /* Seek (and forget) 1st significant bit.  */
-	  for (exponent_skippage = 0;
-	       !next_bits (1);
-	       exponent_skippage++)
-	    ;
-
-	  exponent_1 = f->exponent + f->leader + 1 - f->low;
-
-	  /* Radix LITTLENUM_RADIX, point just higher than f -> leader.  */
-	  exponent_2 = exponent_1 * LITTLENUM_NUMBER_OF_BITS;
-
-	  /* Radix 2.  */
-	  exponent_3 = exponent_2 - exponent_skippage;
-
-	  /* Forget leading zeros, forget 1st bit.  */
-	  exponent_4 = exponent_3 + (1 << (exponent_bits - 1));
-
-	  /* Offset exponent.  */
-
-	  if (exponent_4 & ~mask[exponent_bits])
-	    {
-	      /* Exponent overflow. Lose immediately.  */
-
-	      make_invalid_floating_point_number (words);
-
-	      /* We leave return_value alone: admit we read the
-	        number, but return a floating exception because we
-	        can't encode the number.  */
-	    }
-	  else
-	    {
-	      lp = words;
-
-	      /* Word 1.  Sign, exponent and perhaps high bits.  */
-	      /* Assume 2's complement integers.  */
-	      word1 = ((exponent_4 & mask[exponent_bits])
-		       << (15 - exponent_bits))
-		| ((f->sign == '+') ? 0 : 0x8000)
-		| next_bits (15 - exponent_bits);
-	      *lp++ = word1;
-
-	      /* The rest of the words are just mantissa bits.  */
-	      for (; lp < words + precision; lp++)
-		*lp = next_bits (LITTLENUM_NUMBER_OF_BITS);
-
-	      if (next_bits (1))
-		{
-		  /* Since the NEXT bit is a 1, round UP the mantissa.
-		     The cunning design of these hidden-1 floats permits
-		     us to let the mantissa overflow into the exponent, and
-		     it 'does the right thing'. However, we lose if the
-		     highest-order bit of the lowest-order word flips.
-		     Is that clear?  */
-
-		  unsigned long int carry;
-
-		  /* #if (sizeof(carry)) < ((sizeof(bits[0]) *
-		     BITS_PER_CHAR) + 2) Please allow at least 1 more
-		     bit in carry than is in a LITTLENUM.  We need
-		     that extra bit to hold a carry during a LITTLENUM
-		     carry propagation. Another extra bit (kept 0)
-		     will assure us that we don't get a sticky sign
-		     bit after shifting right, and that permits us to
-		     propagate the carry without any masking of bits.
-		     #endif  */
-		  for (carry = 1, lp--;
-		       carry && (lp >= words);
-		       lp--)
-		    {
-		      carry = *lp + carry;
-		      *lp = carry;
-		      carry >>= LITTLENUM_NUMBER_OF_BITS;
-		    }
-
-		  if ((word1 ^ *words)
-		      & (1 << (LITTLENUM_NUMBER_OF_BITS - 1)))
-		    {
-		      make_invalid_floating_point_number (words);
-		      /* We leave return_value alone: admit we read
-			 the number, but return a floating exception
-			 because we can't encode the number.  */
-		    }
-		}		/* if (we needed to round up)  */
-	    }			/* if (exponent overflow)  */
-	}			/* if (0.0e0)  */
-    }				/* if (float_type was OK)  */
-  return return_value;
-}
-
-/* In:	input_line_pointer -> the 1st character of a floating-point
- *		number.
- *	1 letter denoting the type of statement that wants a
- *		binary floating point number returned.
- *	Address of where to build floating point literal.
- *		Assumed to be 'big enough'.
- *	Address of where to return size of literal (in chars).
- *
- * Out:	Input_line_pointer -> of next char after floating number.
- *	Error message, or 0.
- *	Floating point literal.
- *	Number of chars we used for the literal.  */
-
-char *
-md_atof (what_statement_type, literalP, sizeP)
-     char what_statement_type;
-     char *literalP;
-     int *sizeP;
-{
-  LITTLENUM_TYPE words[MAX_PRECISION];
-  register char kind_of_float;
-  register int number_of_chars;
-  register LITTLENUM_TYPE *littlenum_pointer;
-
-  switch (what_statement_type)
-    {
-    case 'f':			/* .ffloat  */
-    case 'd':			/* .dfloat  */
-      kind_of_float = what_statement_type;
-      break;
-
-    default:
-      kind_of_float = 0;
-      break;
-    }
-
-  if (kind_of_float)
-    {
-      register LITTLENUM_TYPE *limit;
-
-      input_line_pointer = atof_tahoe (input_line_pointer,
-				       kind_of_float,
-				       words);
-      /* The atof_tahoe() builds up 16-bit numbers.
-	 Since the assembler may not be running on
-	 a different-endian machine, be very careful about
-	 converting words to chars.  */
-      number_of_chars = (kind_of_float == 'f' ? F_PRECISION_CHARS :
-			 (kind_of_float == 'd' ? D_PRECISION_CHARS : 0));
-      know (number_of_chars <= MAX_PRECISION * sizeof (LITTLENUM_TYPE));
-      limit = words + (number_of_chars / sizeof (LITTLENUM_TYPE));
-      for (littlenum_pointer = words;
-	   littlenum_pointer < limit;
-	   littlenum_pointer++)
-	{
-	  md_number_to_chars (literalP, *littlenum_pointer,
-			      sizeof (LITTLENUM_TYPE));
-	  literalP += sizeof (LITTLENUM_TYPE);
-	}
-    }
-  else
-    {
-      number_of_chars = 0;
-    }
-
-  *sizeP = number_of_chars;
-  return kind_of_float ? 0 : _("Bad call to md_atof()");
-}
diff --git a/gas/config/atof-vax.c b/gas/config/atof-vax.c
index 7c9f04e7fd1c..75756904fb89 100644
--- a/gas/config/atof-vax.c
+++ b/gas/config/atof-vax.c
@@ -1,5 +1,5 @@
 /* atof_vax.c - turn a Flonum into a VAX floating point number
-   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000
+   Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,42 +16,33 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
-static int atof_vax_sizeof PARAMS ((int));
-static int next_bits PARAMS ((int));
-static void make_invalid_floating_point_number PARAMS ((LITTLENUM_TYPE *));
-static int what_kind_of_float PARAMS ((int, int *, long *));
-static char *atof_vax PARAMS ((char *, int, LITTLENUM_TYPE *));
-
 /* Precision in LittleNums.  */
-#define MAX_PRECISION (8)
-#define H_PRECISION (8)
-#define G_PRECISION (4)
-#define D_PRECISION (4)
-#define F_PRECISION (2)
+#define MAX_PRECISION	8
+#define H_PRECISION	8
+#define G_PRECISION	4
+#define D_PRECISION	4
+#define F_PRECISION	2
 
 /* Length in LittleNums of guard bits.  */
-#define GUARD (2)
+#define GUARD		2
 
-int flonum_gen2vax PARAMS ((int format_letter, FLONUM_TYPE * f,
-			    LITTLENUM_TYPE * words));
+int flonum_gen2vax (int, FLONUM_TYPE *, LITTLENUM_TYPE *);
 
 /* Number of chars in flonum type 'letter'.  */
+
 static int
-atof_vax_sizeof (letter)
-     int letter;
+atof_vax_sizeof (int letter)
 {
   int return_value;
 
-  /*
-   * Permitting uppercase letters is probably a bad idea.
-   * Please use only lower-cased letters in case the upper-cased
-   * ones become unsupported!
-   */
+  /* Permitting uppercase letters is probably a bad idea.
+     Please use only lower-cased letters in case the upper-cased
+     ones become unsupported!  */
   switch (letter)
     {
     case 'f':
@@ -75,8 +66,9 @@ atof_vax_sizeof (letter)
       return_value = 0;
       break;
     }
-  return (return_value);
-}				/* atof_vax_sizeof */
+
+  return return_value;
+}
 
 static const long mask[] =
 {
@@ -116,14 +108,13 @@ static const long mask[] =
 };
 
 
-/* Shared between flonum_gen2vax and next_bits */
+/* Shared between flonum_gen2vax and next_bits.  */
 static int bits_left_in_littlenum;
 static LITTLENUM_TYPE *littlenum_pointer;
 static LITTLENUM_TYPE *littlenum_end;
 
 static int
-next_bits (number_of_bits)
-     int number_of_bits;
+next_bits (int number_of_bits)
 {
   int return_value;
 
@@ -144,23 +135,22 @@ next_bits (number_of_bits)
       bits_left_in_littlenum -= number_of_bits;
       return_value = mask[number_of_bits] & ((*littlenum_pointer) >> bits_left_in_littlenum);
     }
-  return (return_value);
+  return return_value;
 }
 
 static void
-make_invalid_floating_point_number (words)
-     LITTLENUM_TYPE *words;
+make_invalid_floating_point_number (LITTLENUM_TYPE *words)
 {
-  *words = 0x8000;		/* Floating Reserved Operand Code */
+  *words = 0x8000;		/* Floating Reserved Operand Code.  */
 }
+
 
 static int			/* 0 means letter is OK.  */
-what_kind_of_float (letter, precisionP, exponent_bitsP)
-     int letter;		/* In: lowercase please. What kind of float? */
-     int *precisionP;		/* Number of 16-bit words in the float.  */
-     long *exponent_bitsP;	/* Number of exponent bits.  */
+what_kind_of_float (int letter,			/* In: lowercase please. What kind of float?  */
+		    int *precisionP,		/* Number of 16-bit words in the float.  */
+		    long *exponent_bitsP)	/* Number of exponent bits.  */
 {
-  int retval;			/* 0: OK.  */
+  int retval;
 
   retval = 0;
   switch (letter)
@@ -189,29 +179,24 @@ what_kind_of_float (letter, precisionP, exponent_bitsP)
       retval = 69;
       break;
     }
-  return (retval);
+  return retval;
 }
 
-/***********************************************************************\
- *									*
- *	Warning: this returns 16-bit LITTLENUMs, because that is	*
- *	what the VAX thinks in. It is up to the caller to figure	*
- *	out any alignment problems and to conspire for the bytes/word	*
- *	to be emitted in the right order. Bigendians beware!		*
- *									*
- \***********************************************************************/
-
-static char *				/* Return pointer past text consumed.  */
-atof_vax (str, what_kind, words)
-     char *str;			/* Text to convert to binary.  */
-     int what_kind;		/* 'd', 'f', 'g', 'h' */
-     LITTLENUM_TYPE *words;	/* Build the binary here.  */
+/* Warning: this returns 16-bit LITTLENUMs, because that is
+   what the VAX thinks in. It is up to the caller to figure
+   out any alignment problems and to conspire for the bytes/word
+   to be emitted in the right order. Bigendians beware!  */
+
+static char *
+atof_vax (char *str,			/* Text to convert to binary.  */
+	  int what_kind,		/* 'd', 'f', 'g', 'h'  */
+	  LITTLENUM_TYPE *words)	/* Build the binary here.  */
 {
   FLONUM_TYPE f;
   LITTLENUM_TYPE bits[MAX_PRECISION + MAX_PRECISION + GUARD];
-  /* Extra bits for zeroed low-order bits.  */
-  /* The 1st MAX_PRECISION are zeroed, */
-  /* the last contain flonum bits.  */
+  /* Extra bits for zeroed low-order bits.
+     The 1st MAX_PRECISION are zeroed,
+     the last contain flonum bits.  */
   char *return_value;
   int precision;		/* Number of 16-bit words in the format.  */
   long exponent_bits;
@@ -225,7 +210,7 @@ atof_vax (str, what_kind, words)
 
   if (what_kind_of_float (what_kind, &precision, &exponent_bits))
     {
-      return_value = NULL;	/* We lost.  */
+      return_value = NULL;
       make_invalid_floating_point_number (words);
     }
 
@@ -233,37 +218,30 @@ atof_vax (str, what_kind, words)
     {
       memset (bits, '\0', sizeof (LITTLENUM_TYPE) * MAX_PRECISION);
 
-      /* Use more LittleNums than seems */
-      /* necessary: the highest flonum may have */
-      /* 15 leading 0 bits, so could be useless.  */
+      /* Use more LittleNums than seems
+         necessary: the highest flonum may have
+         15 leading 0 bits, so could be useless.  */
       f.high = f.low + precision - 1 + GUARD;
 
       if (atof_generic (&return_value, ".", "eE", &f))
 	{
 	  make_invalid_floating_point_number (words);
-	  return_value = NULL;	/* we lost */
-	}
-      else
-	{
-	  if (flonum_gen2vax (what_kind, &f, words))
-	    {
-	      return_value = NULL;
-	    }
+	  return_value = NULL;
 	}
+      else if (flonum_gen2vax (what_kind, &f, words))
+	return_value = NULL;
     }
-  return (return_value);
-}				/* atof_vax() */
+
+  return return_value;
+}
 
-/*
- * In: a flonum, a vax floating point format.
- * Out: a vax floating-point bit pattern.
- */
-
-int				/* 0: OK.  */
-flonum_gen2vax (format_letter, f, words)
-     int format_letter;		/* One of 'd' 'f' 'g' 'h'.  */
-     FLONUM_TYPE *f;
-     LITTLENUM_TYPE *words;	/* Deliver answer here.  */
+/* In: a flonum, a vax floating point format.
+   Out: a vax floating-point bit pattern.  */
+
+int
+flonum_gen2vax (int format_letter,	/* One of 'd' 'f' 'g' 'h'.  */
+		FLONUM_TYPE *f,
+		LITTLENUM_TYPE *words)	/* Deliver answer here.  */
 {
   LITTLENUM_TYPE *lp;
   int precision;
@@ -273,16 +251,14 @@ flonum_gen2vax (format_letter, f, words)
   return_value = what_kind_of_float (format_letter, &precision, &exponent_bits);
 
   if (return_value != 0)
-    {
-      make_invalid_floating_point_number (words);
-    }
+    make_invalid_floating_point_number (words);
+
   else
     {
       if (f->low > f->leader)
-	{
-	  /* 0.0e0 seen.  */
-	  memset (words, '\0', sizeof (LITTLENUM_TYPE) * precision);
-	}
+	/* 0.0e0 seen.  */
+	memset (words, '\0', sizeof (LITTLENUM_TYPE) * precision);
+
       else
 	{
 	  long exponent_1;
@@ -292,49 +268,31 @@ flonum_gen2vax (format_letter, f, words)
 	  int exponent_skippage;
 	  LITTLENUM_TYPE word1;
 
-	  /* JF: Deal with new Nan, +Inf and -Inf codes */
+	  /* JF: Deal with new Nan, +Inf and -Inf codes.  */
 	  if (f->sign != '-' && f->sign != '+')
 	    {
 	      make_invalid_floating_point_number (words);
 	      return return_value;
 	    }
-	  /*
-			 * All vaxen floating_point formats (so far) have:
-			 * Bit 15 is sign bit.
-			 * Bits 14:n are excess-whatever exponent.
-			 * Bits n-1:0 (if any) are most significant bits of fraction.
-			 * Bits 15:0 of the next word are the next most significant bits.
-			 * And so on for each other word.
-			 *
-			 * All this to be compatible with a KF11?? (Which is still faster
-			 * than lots of vaxen I can think of, but it also has higher
-			 * maintenance costs ... sigh).
-			 *
-			 * So we need: number of bits of exponent, number of bits of
-			 * mantissa.
-			 */
-
-#ifdef NEVER			/******* This zeroing seems redundant - Dean 3may86 **********/
-	  /*
-			 * No matter how few bits we got back from the atof()
-			 * routine, add enough zero littlenums so the rest of the
-			 * code won't run out of "significant" bits in the mantissa.
-			 */
-	  {
-	    LITTLENUM_TYPE *ltp;
-	    for (ltp = f->leader + 1;
-		 ltp <= f->low + precision;
-		 ltp++)
-	      {
-		*ltp = 0;
-	      }
-	  }
-#endif
+
+	  /* All vaxen floating_point formats (so far) have:
+	     Bit 15 is sign bit.
+	     Bits 14:n are excess-whatever exponent.
+	     Bits n-1:0 (if any) are most significant bits of fraction.
+	     Bits 15:0 of the next word are the next most significant bits.
+	     And so on for each other word.
+
+	     All this to be compatible with a KF11?? (Which is still faster
+	     than lots of vaxen I can think of, but it also has higher
+	     maintenance costs ... sigh).
+
+	     So we need: number of bits of exponent, number of bits of
+	     mantissa.  */
 
 	  bits_left_in_littlenum = LITTLENUM_NUMBER_OF_BITS;
 	  littlenum_pointer = f->leader;
 	  littlenum_end = f->low;
-	  /* Seek (and forget) 1st significant bit */
+	  /* Seek (and forget) 1st significant bit.  */
 	  for (exponent_skippage = 0;
 	       !next_bits (1);
 	       exponent_skippage++);;
@@ -350,24 +308,19 @@ flonum_gen2vax (format_letter, f, words)
 
 	  if (exponent_4 & ~mask[exponent_bits])
 	    {
-	      /*
-				 * Exponent overflow. Lose immediately.
-				 */
-
+	      /* Exponent overflow. Lose immediately.  */
 	      make_invalid_floating_point_number (words);
 
-	      /*
-				 * We leave return_value alone: admit we read the
-				 * number, but return a floating exception
-				 * because we can't encode the number.
-				 */
+	      /* We leave return_value alone: admit we read the
+	         number, but return a floating exception
+	         because we can't encode the number.  */
 	    }
 	  else
 	    {
 	      lp = words;
 
-	      /* Word 1. Sign, exponent and perhaps high bits.  */
-	      /* Assume 2's complement integers.  */
+	      /* Word 1. Sign, exponent and perhaps high bits.
+	         Assume 2's complement integers.  */
 	      word1 = (((exponent_4 & mask[exponent_bits]) << (15 - exponent_bits))
 		       | ((f->sign == '+') ? 0 : 0x8000)
 		       | next_bits (15 - exponent_bits));
@@ -375,32 +328,26 @@ flonum_gen2vax (format_letter, f, words)
 
 	      /* The rest of the words are just mantissa bits.  */
 	      for (; lp < words + precision; lp++)
-		{
-		  *lp = next_bits (LITTLENUM_NUMBER_OF_BITS);
-		}
+		*lp = next_bits (LITTLENUM_NUMBER_OF_BITS);
 
 	      if (next_bits (1))
 		{
-		  /*
-					 * Since the NEXT bit is a 1, round UP the mantissa.
-					 * The cunning design of these hidden-1 floats permits
-					 * us to let the mantissa overflow into the exponent, and
-					 * it 'does the right thing'. However, we lose if the
-					 * highest-order bit of the lowest-order word flips.
-					 * Is that clear?
-					 */
-
+		  /* Since the NEXT bit is a 1, round UP the mantissa.
+		     The cunning design of these hidden-1 floats permits
+		     us to let the mantissa overflow into the exponent, and
+		     it 'does the right thing'. However, we lose if the
+		     highest-order bit of the lowest-order word flips.
+		     Is that clear?  */
 		  unsigned long carry;
 
 		  /*
-					  #if (sizeof(carry)) < ((sizeof(bits[0]) * BITS_PER_CHAR) + 2)
-					  Please allow at least 1 more bit in carry than is in a LITTLENUM.
-					  We need that extra bit to hold a carry during a LITTLENUM carry
-					  propagation. Another extra bit (kept 0) will assure us that we
-					  don't get a sticky sign bit after shifting right, and that
-					  permits us to propagate the carry without any masking of bits.
-					  #endif
-					  */
+		    #if (sizeof(carry)) < ((sizeof(bits[0]) * BITS_PER_CHAR) + 2)
+		    Please allow at least 1 more bit in carry than is in a LITTLENUM.
+		    We need that extra bit to hold a carry during a LITTLENUM carry
+		    propagation. Another extra bit (kept 0) will assure us that we
+		    don't get a sticky sign bit after shifting right, and that
+		    permits us to propagate the carry without any masking of bits.
+		    #endif   */
 		  for (carry = 1, lp--;
 		       carry && (lp >= words);
 		       lp--)
@@ -413,68 +360,61 @@ flonum_gen2vax (format_letter, f, words)
 		  if ((word1 ^ *words) & (1 << (LITTLENUM_NUMBER_OF_BITS - 1)))
 		    {
 		      make_invalid_floating_point_number (words);
-		      /*
-						 * We leave return_value alone: admit we read the
-						 * number, but return a floating exception
-						 * because we can't encode the number.
-						 */
+		      /* We leave return_value alone: admit we read the
+		         number, but return a floating exception
+		         because we can't encode the number.  */
 		    }
-		}		/* if (we needed to round up) */
-	    }			/* if (exponent overflow) */
-	}			/* if (0.0e0) */
-    }				/* if (float_type was OK) */
-  return (return_value);
-}				/* flonum_gen2vax() */
-
-/* JF this used to be in vax.c but this looks like a better place for it */
-
-/*
- *		md_atof()
- *
- * In:	input_line_pointer->the 1st character of a floating-point
- *		number.
- *	1 letter denoting the type of statement that wants a
- *		binary floating point number returned.
- *	Address of where to build floating point literal.
- *		Assumed to be 'big enough'.
- *	Address of where to return size of literal (in chars).
- *
- * Out:	Input_line_pointer->of next char after floating number.
- *	Error message, or 0.
- *	Floating point literal.
- *	Number of chars we used for the literal.
- */
-
-#define MAXIMUM_NUMBER_OF_LITTLENUMS (8)	/* For .hfloats.  */
+		}
+	    }
+	}
+    }
+  return return_value;
+}
+
+/* JF this used to be in vax.c but this looks like a better place for it.  */
+
+/* In:	input_line_pointer->the 1st character of a floating-point
+  		number.
+  	1 letter denoting the type of statement that wants a
+  		binary floating point number returned.
+  	Address of where to build floating point literal.
+  		Assumed to be 'big enough'.
+  	Address of where to return size of literal (in chars).
+  
+   Out:	Input_line_pointer->of next char after floating number.
+  	Error message, or 0.
+  	Floating point literal.
+  	Number of chars we used for the literal.  */
+
+#define MAXIMUM_NUMBER_OF_LITTLENUMS  8 	/* For .hfloats.  */
 
 char *
-md_atof (what_statement_type, literalP, sizeP)
-     int what_statement_type;
-     char *literalP;
-     int *sizeP;
+md_atof (int what_statement_type,
+	 char *literalP,
+	 int *sizeP)
 {
   LITTLENUM_TYPE words[MAXIMUM_NUMBER_OF_LITTLENUMS];
-  register char kind_of_float;
-  register int number_of_chars;
-  register LITTLENUM_TYPE *littlenumP;
+  char kind_of_float;
+  int number_of_chars;
+  LITTLENUM_TYPE *littlenumP;
 
   switch (what_statement_type)
     {
-    case 'F':			/* .float */
-    case 'f':			/* .ffloat */
+    case 'F':
+    case 'f':
       kind_of_float = 'f';
       break;
 
-    case 'D':			/* .double */
-    case 'd':			/* .dfloat */
+    case 'D':
+    case 'd':
       kind_of_float = 'd';
       break;
 
-    case 'g':			/* .gfloat */
+    case 'g':
       kind_of_float = 'g';
       break;
 
-    case 'h':			/* .hfloat */
+    case 'h':
       kind_of_float = 'h';
       break;
 
@@ -485,17 +425,15 @@ md_atof (what_statement_type, literalP, sizeP)
 
   if (kind_of_float)
     {
-      register LITTLENUM_TYPE *limit;
+      LITTLENUM_TYPE *limit;
 
       input_line_pointer = atof_vax (input_line_pointer,
 				     kind_of_float,
 				     words);
-      /*
-       * The atof_vax() builds up 16-bit numbers.
-       * Since the assembler may not be running on
-       * a little-endian machine, be very careful about
-       * converting words to chars.
-       */
+      /* The atof_vax() builds up 16-bit numbers.
+         Since the assembler may not be running on
+         a little-endian machine, be very careful about
+         converting words to chars.  */
       number_of_chars = atof_vax_sizeof (kind_of_float);
       know (number_of_chars <= MAXIMUM_NUMBER_OF_LITTLENUMS * sizeof (LITTLENUM_TYPE));
       limit = words + (number_of_chars / sizeof (LITTLENUM_TYPE));
@@ -506,12 +444,8 @@ md_atof (what_statement_type, literalP, sizeP)
 	};
     }
   else
-    {
-      number_of_chars = 0;
-    };
+    number_of_chars = 0;
 
   *sizeP = number_of_chars;
   return kind_of_float ? NULL : _("Bad call to md_atof()");
 }
-
-/* end of atof-vax.c */
diff --git a/gas/config/bfin-aux.h b/gas/config/bfin-aux.h
new file mode 100755
index 000000000000..be6b63a65ec5
--- /dev/null
+++ b/gas/config/bfin-aux.h
@@ -0,0 +1,151 @@
+/* bfin-aux.h ADI Blackfin Header file for gas

+   Copyright 2005

+   Free Software Foundation, Inc.

+

+   This file is part of GAS, the GNU Assembler.

+

+   GAS is free software; you can redistribute it and/or modify

+   it under the terms of the GNU General Public License as published by

+   the Free Software Foundation; either version 2, or (at your option)

+   any later version.

+

+   GAS is distributed in the hope that it will be useful,

+   but WITHOUT ANY WARRANTY; without even the implied warranty of

+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+   GNU General Public License for more details.

+

+   You should have received a copy of the GNU General Public License

+   along with GAS; see the file COPYING.  If not, write to the Free

+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

+   02110-1301, USA.  */

+

+#include "bfin-defs.h"

+

+#define REG_T Register *

+

+INSTR_T

+bfin_gen_dsp32mac (int op1, int mm, int mmod, int w1, int p,

+              int h01, int h11, int h00, int h10,

+	      int op0, REG_T dst, REG_T src0, REG_T src1, int w0);

+

+INSTR_T

+bfin_gen_dsp32mult (int op1, int mm, int mmod, int w1, int p,

+               int h01, int h11, int h00, int h10,

+	       int op0, REG_T dst, REG_T src0, REG_T src1, int w0);

+

+INSTR_T

+bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,

+              REG_T dst0, REG_T dst1, REG_T src0, REG_T src1);

+

+INSTR_T

+bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, REG_T src1,

+                int sop, int hls);

+

+INSTR_T

+bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, REG_T src1,

+                   int sop, int hls);

+

+INSTR_T

+bfin_gen_ldimmhalf (REG_T reg, int h, int s, int z, Expr_Node *hword,

+               int reloc);

+

+INSTR_T

+bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int w, int sz, int z,

+              Expr_Node *offset);

+

+INSTR_T

+bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int z, int w);

+

+INSTR_T

+bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node *offset, int w, int op);

+

+INSTR_T

+bfin_gen_ldstiifp (REG_T reg, Expr_Node *offset, int w);

+

+INSTR_T

+bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int w, REG_T idx);

+

+INSTR_T

+bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int w, int m);

+

+INSTR_T

+bfin_gen_alu2op (REG_T dst, REG_T src, int opc);

+

+INSTR_T

+bfin_gen_compi2opd (REG_T dst, int src, int op);

+

+INSTR_T

+bfin_gen_compi2opp (REG_T dst, int src, int op);

+

+INSTR_T

+bfin_gen_dagmodik (REG_T i, int op);

+

+INSTR_T

+bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br);

+

+INSTR_T

+bfin_gen_ptr2op (REG_T dst, REG_T src, int opc);

+

+INSTR_T

+bfin_gen_logi2op (int dst, int src, int opc);

+

+INSTR_T

+bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc);

+

+INSTR_T

+bfin_gen_ccmv (REG_T src, REG_T dst, int t);

+

+INSTR_T

+bfin_gen_ccflag (REG_T x, int y, int opc, int i, int g);

+

+INSTR_T

+bfin_gen_cc2stat (int cbit, int op, int d);

+

+INSTR_T

+bfin_gen_regmv (REG_T src, REG_T dst);

+

+INSTR_T

+bfin_gen_cc2dreg (int op, REG_T reg);

+

+INSTR_T

+bfin_gen_brcc (int t, int b, Expr_Node *offset);

+

+INSTR_T

+bfin_gen_ujump (Expr_Node *offset);

+

+INSTR_T

+bfin_gen_cactrl (REG_T reg, int a, int op);

+

+INSTR_T

+bfin_gen_progctrl (int prgfunc, int poprnd);

+

+INSTR_T

+bfin_gen_loopsetup (Expr_Node *soffset, REG_T c, int rop,

+               Expr_Node *eoffset, REG_T reg);

+

+INSTR_T

+bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg);

+

+INSTR_T

+bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int w);

+

+INSTR_T

+bfin_gen_pushpopreg (REG_T reg, int w);

+

+INSTR_T

+bfin_gen_calla (Expr_Node *addr, int s);

+

+INSTR_T

+bfin_gen_linkage (int r, int framesize);

+

+INSTR_T

+bfin_gen_pseudodbg (int fn, int reg, int grp);

+

+INSTR_T

+bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected);

+

+bfd_boolean

+bfin_resource_conflict (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);

+

+INSTR_T

+bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2);

diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h
new file mode 100644
index 000000000000..48bacb3ed7d4
--- /dev/null
+++ b/gas/config/bfin-defs.h
@@ -0,0 +1,386 @@
+/* bfin-defs.h ADI Blackfin gas header file
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef BFIN_PARSE_H
+#define BFIN_PARSE_H  
+
+#include <bfd.h>
+#include "as.h"
+
+#define PCREL	1
+#define CODE_FRAG_SIZE 4096  /* 1 page.  */  
+
+
+/* Definition for all status bits.  */
+typedef enum
+{
+  c_0,
+  c_1,
+  c_4,
+  c_2,
+  c_uimm2,
+  c_uimm3,
+  c_imm3,
+  c_pcrel4, 
+  c_imm4,
+  c_uimm4s4,
+  c_uimm4,
+  c_uimm4s2,
+  c_negimm5s4,
+  c_imm5,
+  c_uimm5,
+  c_imm6,  
+  c_imm7,
+  c_imm8,
+  c_uimm8,
+  c_pcrel8,
+  c_uimm8s4,
+  c_pcrel8s4,
+  c_lppcrel10,
+  c_pcrel10, 
+  c_pcrel12,
+  c_imm16s4,
+  c_luimm16,
+  c_imm16,
+  c_huimm16,
+  c_rimm16,
+  c_imm16s2,
+  c_uimm16s4, 
+  c_uimm16,
+  c_pcrel24 
+} const_forms_t;
+
+
+/* High-Nibble: group code, low nibble: register code.  */
+
+
+#define T_REG_R       0x00
+#define T_REG_P       0x10
+#define T_REG_I       0x20
+#define T_REG_B       0x30
+#define T_REG_L       0x34
+#define T_REG_M       0x24
+#define T_REG_A       0x40
+
+/* All registers above this value don't
+   belong to a usuable register group.  */
+#define T_NOGROUP     0xa0
+
+/* Flags.  */
+#define F_REG_ALL    0x1000
+#define F_REG_HIGH   0x2000  /* Half register: high half.  */
+
+enum machine_registers
+{
+  REG_R0    = T_REG_R, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7, 
+  REG_P0    = T_REG_P, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
+  REG_I0    = T_REG_I, REG_I1, REG_I2, REG_I3,
+  REG_M0    = T_REG_M, REG_M1, REG_M2, REG_M3, 
+  REG_B0    = T_REG_B, REG_B1, REG_B2, REG_B3,
+  REG_L0    = T_REG_L, REG_L1, REG_L2, REG_L3, 
+  REG_A0x   = T_REG_A, REG_A0w, REG_A1x, REG_A1w,
+  REG_ASTAT = 0x46,
+  REG_RETS  = 0x47,
+  REG_LC0   = 0x60, REG_LT0, REG_LB0,  REG_LC1, REG_LT1, REG_LB1,
+              REG_CYCLES, REG_CYCLES2,
+  REG_USP   = 0x70, REG_SEQSTAT, REG_SYSCFG,
+	      REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, 
+
+/* These don't have groups.  */
+  REG_sftreset = T_NOGROUP, REG_omode, REG_excause, REG_emucause,
+	         REG_idle_req, REG_hwerrcause,
+  REG_A0       = 0xc0, REG_A1, REG_CC,
+/* Pseudo registers, used only for distinction from symbols.  */
+		 REG_RL0, REG_RL1, REG_RL2, REG_RL3,
+		 REG_RL4, REG_RL5, REG_RL6, REG_RL7, 
+		 REG_RH0, REG_RH1, REG_RH2, REG_RH3,
+		 REG_RH4, REG_RH5, REG_RH6, REG_RH7, 
+		 REG_LASTREG
+};
+
+/* Status register flags.  */
+
+enum statusflags
+{
+  S_AZ = 0,
+  S_AN,
+  S_AQ = 6,
+  S_AC0 = 12,
+  S_AC1,
+  S_AV0 = 16,
+  S_AV0S,
+  S_AV1,
+  S_AV1S,
+  S_V = 24,
+  S_VS = 25
+}; 
+
+
+enum reg_class
+{
+  rc_dregs_lo,
+  rc_dregs_hi,
+  rc_dregs,
+  rc_dregs_pair,
+  rc_pregs,
+  rc_spfp,
+  rc_dregs_hilo,
+  rc_accum_ext,
+  rc_accum_word,
+  rc_accum,
+  rc_iregs,
+  rc_mregs,
+  rc_bregs,
+  rc_lregs,
+  rc_dpregs,
+  rc_gregs,
+  rc_regs,
+  rc_statbits,
+  rc_ignore_bits,
+  rc_ccstat,
+  rc_counters,
+  rc_dregs2_sysregs1,
+  rc_open,
+  rc_sysregs2,
+  rc_sysregs3,
+  rc_allregs,
+  LIM_REG_CLASSES
+};
+
+/* mmod field.  */
+#define M_S2RND 1
+#define M_T     2
+#define M_W32   3
+#define M_FU    4
+#define M_TFU   6
+#define M_IS    8
+#define M_ISS2  9
+#define M_IH    11
+#define M_IU    12
+
+/* Register type checking macros.  */
+
+#define CODE_MASK  0x07
+#define CLASS_MASK 0xf0
+
+#define REG_SAME(a, b)   ((a).regno == (b).regno)
+#define REG_EQUAL(a, b)  (((a).regno & CODE_MASK) == ((b).regno & CODE_MASK))
+#define REG_CLASS(a)     ((a.regno) & 0xf0)
+#define IS_A1(a)         ((a).regno == REG_A1)
+#define IS_H(a)          ((a).regno & F_REG_HIGH ? 1: 0)
+#define IS_EVEN(r)       (r.regno % 2 == 0)
+#define IS_HCOMPL(a, b)  (REG_EQUAL(a, b) && \
+                         ((a).regno & F_REG_HIGH) != ((b).regno & F_REG_HIGH))
+
+/* register type checking.  */
+#define _TYPECHECK(r, x) (((r).regno & CLASS_MASK) == T_REG_##x)
+
+#define IS_DREG(r)       _TYPECHECK(r, R)
+#define IS_DREG_H(r)     (_TYPECHECK(r, R) && IS_H(r))
+#define IS_DREG_L(r)     (_TYPECHECK(r, R) && !IS_H(r))
+#define IS_PREG(r)       _TYPECHECK(r, P)
+#define IS_IREG(r)       (((r).regno & 0xf4) == T_REG_I)
+#define IS_MREG(r)       (((r).regno & 0xf4) == T_REG_M)
+#define IS_BREG(r)       (((r).regno & 0xf4) == T_REG_B)
+#define IS_LREG(r)       (((r).regno & 0xf4) == T_REG_L)
+#define IS_CREG(r)       ((r).regno == REG_LC0 || (r).regno == REG_LC1)
+#define IS_ALLREG(r)     ((r).regno < T_NOGROUP)
+
+/* Expression value macros.  */
+
+typedef enum
+{ 
+  ones_compl,
+  twos_compl,
+  mult,
+  divide,
+  mod,
+  add,
+  sub,
+  lsh,
+  rsh,
+  logand,
+  logior,
+  logxor
+} expr_opcodes_t;
+
+struct expressionS;
+
+#define SYMBOL_T       symbolS*
+ 
+struct expression_cell
+{
+  int value;
+  SYMBOL_T symbol;
+};
+
+/* User Type Definitions.  */
+struct bfin_insn
+{
+  unsigned long value;
+  struct bfin_insn *next;
+  struct expression_cell *exp;
+  int pcrel;
+  int reloc;
+};
+    
+#define INSTR_T struct bfin_insn*
+#define EXPR_T  struct expression_cell* 
+
+typedef struct expr_node_struct Expr_Node;
+ 
+extern INSTR_T gencode (unsigned long x);
+extern INSTR_T conscode (INSTR_T head, INSTR_T tail);   
+extern INSTR_T conctcode (INSTR_T head, INSTR_T tail);
+extern INSTR_T note_reloc
+       (INSTR_T code, Expr_Node *, int reloc,int pcrel);
+extern INSTR_T note_reloc1
+       (INSTR_T code, const char * sym, int reloc, int pcrel);
+extern INSTR_T note_reloc2
+       (INSTR_T code, const char *symbol, int reloc, int value, int pcrel);
+ 
+/* Types of expressions.  */
+typedef enum 
+{
+  Expr_Node_Binop,		/* Binary operator.  */
+  Expr_Node_Unop,		/* Unary operator.  */
+  Expr_Node_Reloc,		/* Symbol to be relocated.  */
+  Expr_Node_GOT_Reloc,		/* Symbol to be relocated using the GOT.  */
+  Expr_Node_Constant 		/* Constant.  */
+} Expr_Node_Type;
+
+/* Types of operators.  */
+typedef enum 
+{
+  Expr_Op_Type_Add,
+  Expr_Op_Type_Sub,
+  Expr_Op_Type_Mult,
+  Expr_Op_Type_Div,
+  Expr_Op_Type_Mod,
+  Expr_Op_Type_Lshift,
+  Expr_Op_Type_Rshift,
+  Expr_Op_Type_BAND,		/* Bitwise AND.  */
+  Expr_Op_Type_BOR,		/* Bitwise OR.  */
+  Expr_Op_Type_BXOR,		/* Bitwise exclusive OR.  */
+  Expr_Op_Type_LAND,		/* Logical AND.  */
+  Expr_Op_Type_LOR,		/* Logical OR.  */
+  Expr_Op_Type_NEG,
+  Expr_Op_Type_COMP		/* Complement.  */
+} Expr_Op_Type;
+
+/* The value that can be stored ... depends on type.  */
+typedef union
+{
+  const char *s_value;		/* if relocation symbol, the text.  */
+  int i_value;			/* if constant, the value.  */
+  Expr_Op_Type op_value;	/* if operator, the value.  */
+} Expr_Node_Value;
+
+/* The expression node.  */
+struct expr_node_struct
+{
+  Expr_Node_Type 	type;
+  Expr_Node_Value	value;
+  Expr_Node		*Left_Child;
+  Expr_Node		*Right_Child;
+};
+
+
+/* Operations on the expression node.  */
+Expr_Node *Expr_Node_Create (Expr_Node_Type type, 
+		         Expr_Node_Value value, 
+			 Expr_Node *Left_Child, 
+			 Expr_Node *Right_Child);
+
+/* Generate the reloc structure as a series of instructions.  */
+INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
+ 
+#define MKREF(x)	mkexpr (0,x)
+#define ALLOCATE(x)	malloc (x)
+ 
+#define NULL_CODE ((INSTR_T) 0)
+
+#ifndef EXPR_VALUE
+#define EXPR_VALUE(x)  (((x)->type == Expr_Node_Constant) ? ((x)->value.i_value) : 0)
+#endif
+#ifndef EXPR_SYMBOL
+#define EXPR_SYMBOL(x) ((x)->symbol)
+#endif
+
+
+typedef long reg_t;
+
+
+typedef struct _register
+{
+  reg_t regno;       /* Register ID as defined in machine_registers.  */
+  int   flags;
+} Register;
+
+
+typedef struct _macfunc
+{
+  char n;
+  char op;
+  char w;
+  char P;
+  Register dst;
+  Register s0;
+  Register s1;
+} Macfunc;
+
+typedef struct _opt_mode
+{
+  int MM;
+  int mod;
+} Opt_mode;
+
+typedef enum
+{
+  SEMANTIC_ERROR,
+  NO_INSN_GENERATED,
+  INSN_GENERATED
+} parse_state;
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int debug_codeselection;
+
+void error (char *format, ...);
+void warn (char *format, ...);
+int  semantic_error (char *syntax);
+void semantic_error_2 (char *syntax);
+
+EXPR_T mkexpr (int, SYMBOL_T);
+
+extern void bfin_equals (Expr_Node *sym);
+/* Defined in bfin-lex.l.  */
+void set_start_state (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* BFIN_PARSE_H */
+
diff --git a/gas/config/bfin-lex.l b/gas/config/bfin-lex.l
new file mode 100644
index 000000000000..3a0077cd9854
--- /dev/null
+++ b/gas/config/bfin-lex.l
@@ -0,0 +1,556 @@
+/* bfin-lex.l  ADI Blackfin lexer
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+%{
+
+#include <stdlib.h>
+#include <string.h>
+#include "bfin-defs.h"
+#include "bfin-parse.h"
+#include "as.h"
+
+static long parse_int (char **end);
+static int parse_halfreg (Register *r, int cl, char *hr);
+static int parse_reg (Register *r, int type, char *rt);
+int yylex (void);
+
+#define _REG yylval.reg
+
+
+%}
+
+/* Define Start States ... Actually we will use exclusion.
+   If no start state is specified it should match any state
+   and <INITIAL> would match some keyword rules only with
+   initial.  */
+%s KEYWORD
+
+%%
+[sS][fF][tT][rR][eE][sS][eE][tT]        _REG.regno = REG_sftreset;  return REG;
+[oO][mM][oO][dD][eE]                    _REG.regno = REG_omode;     return REG;
+[iI][dD][lL][eE]_[rR][eE][qQ]           _REG.regno = REG_idle_req;  return REG;
+[hH][wW][eE][rR][rR][cC][aA][uU][sS][eE] _REG.regno = REG_hwerrcause; return REG;
+[eE][xX][cC][aA][uU][sS][eE]            _REG.regno = REG_excause;   return REG;
+[eE][mM][uU][cC][aA][uU][sS][eE]	_REG.regno = REG_emucause;  return REG;
+[zZ]                                    return Z;
+[xX]                                    return X;
+[wW]32                                  yylval.value = M_W32; return MMOD;
+[wW]                                    return W;
+[vV][iI][tT]_[mM][aA][xX]               return VIT_MAX;
+[vV]               return V; /* Special: V is a statflag and a modifier.  */
+[uU][sS][pP]       _REG.regno = REG_USP; return REG;
+[tT][lL]                                return TL;
+[tT][hH]                                return TH;
+[tT][fF][uU]                            yylval.value = M_TFU; return MMOD;
+[tT][eE][sS][tT][sS][eE][tT]            return TESTSET;
+[tT]                                    yylval.value = M_T; return MMOD;
+[sS]                                                        return S;
+[sS][yY][sS][cC][fF][gG]       _REG.regno = REG_SYSCFG; return REG;
+[sS][tT][iI]                            return STI;
+[sS][sS][yY][nN][cC]                    return SSYNC;
+[sS][pP]"."[lL]                         _REG.regno = REG_SP; return HALF_REG;
+[sS][pP]"."[hH]                         _REG.regno = REG_SP | F_REG_HIGH; return HALF_REG;
+[sS][pP]                                _REG.regno = REG_SP; return REG;
+[sS][iI][gG][nN][bB][iI][tT][sS]        return SIGNBITS;
+[sS][iI][gG][nN]                        return SIGN;
+[sS][eE][qQ][sS][tT][aA][tT]     _REG.regno = REG_SEQSTAT; return REG;
+[sS][eE][aA][rR][cC][hH]                return SEARCH;
+[sS][hH][iI][fF][tT]                    return SHIFT;
+[sS][cC][oO]                            return SCO;
+
+[sS][aA][aA]                            return SAA;
+[sS]2[rR][nN][dD]                       yylval.value = M_S2RND; return MMOD;
+[rR][tT][xX]                            return RTX;
+[rR][tT][sS]                            return RTS;
+[rR][tT][nN]                            return RTN;
+[rR][tT][iI]                            return RTI;
+[rR][tT][eE]                            return RTE;
+[rR][oO][tT]                            return ROT;
+[rR][nN][dD]20                          return RND20;
+[rR][nN][dD]12                          return RND12;
+[rR][nN][dD][lL]                        return RNDL;
+[rR][nN][dD][hH]                        return RNDH;
+[rR][nN][dD]                            return RND;
+
+[rR][0-7]"."[lLhHbB]  return parse_halfreg(&yylval.reg, T_REG_R, yytext);
+
+[rR][eE][tT][sS]		_REG.regno = REG_RETS; return REG;
+[rR][eE][tT][iI]		_REG.regno = REG_RETI; return REG;
+[rR][eE][tT][xX]		_REG.regno = REG_RETX; return REG;
+[rR][eE][tT][nN]		_REG.regno = REG_RETN; return REG;
+[rR][eE][tT][eE]		_REG.regno = REG_RETE; return REG;
+[eE][mM][uU][dD][aA][tT]	_REG.regno = REG_EMUDAT; return REG;
+[rR][aA][iI][sS][eE]		return RAISE;
+
+[rR][0-7]           return parse_reg (&yylval.reg, T_REG_R, yytext);
+
+[rR]      return R;
+[pP][rR][nN][tT]                        return PRNT;
+[pP][cC]                                return PC;
+[pP][aA][cC][kK]                        return PACK;
+
+[pP][0-5]"."[lLhH]  return parse_halfreg (&yylval.reg, T_REG_P, yytext);
+[pP][0-5]           return parse_reg (&yylval.reg, T_REG_P, yytext);
+
+[oO][uU][tT][cC]                        return OUTC;
+[oO][nN][eE][sS]                        return ONES;
+
+[nN][oO][tT]                            return NOT;
+[nN][oO][pP]                            return NOP;
+[mM][nN][oO][pP]                        return MNOP;
+[nN][sS]                                return NS;
+
+
+[mM][iI][nN]                            return MIN;
+[mM][aA][xX]                            return MAX;
+
+[mM][0-3]"."[lLhH]  return parse_halfreg (&yylval.reg, T_REG_M, yytext);
+[mM][0-3]           return parse_reg (&yylval.reg, T_REG_M, yytext);
+
+[mM]                                    return M;
+[lL][tT]                                return LT;
+[lL][sS][hH][iI][fF][tT]                return LSHIFT;
+[lL][sS][eE][tT][uU][pP]                return LSETUP;
+[lL][oO][oO][pP]			return LOOP;
+[lL][oO][oO][pP]_[bB][eE][gG][iI][nN]	return LOOP_BEGIN;
+[lL][oO][oO][pP]_[eE][nN][dD]		return LOOP_END;
+
+[lL][eE]                                return LE;
+[lL][cC]0 _REG.regno = REG_LC0; return REG;
+[lL][tT]0 _REG.regno = REG_LT0; return REG;
+[lL][bB]0 _REG.regno = REG_LB0; return REG;
+[lL][cC]1 _REG.regno = REG_LC1; return REG;
+[lL][tT]1 _REG.regno = REG_LT1; return REG;
+[lL][bB]1 _REG.regno = REG_LB1; return REG;
+
+[lL][0-3]"."[lLhH]  return parse_halfreg (&yylval.reg, T_REG_L, yytext);
+[lL][0-3]           return parse_reg (&yylval.reg, T_REG_L, yytext);
+[lL][oO]                                return LO;
+[jJ][uU][mM][pP]"."[sS]                 { BEGIN 0; return JUMP_DOT_S;}
+[jJ][uU][mM][pP]"."[lL]                 { BEGIN 0; return JUMP_DOT_L;}
+[jJ][uU][mM][pP]                        { BEGIN 0; return JUMP;}
+[jJ][uU][mM][pP]"."[xX]                 { BEGIN 0; return JUMP_DOT_L; }
+[iI][uU]                                yylval.value = M_IU;   return MMOD;
+[iI][sS][sS]2                           yylval.value = M_ISS2; return MMOD;
+[iI][sS]                                yylval.value = M_IS;   return MMOD;
+[iI][hH]                                yylval.value = M_IH;   return MMOD;
+[iI][fF]                                return IF;
+[iI][0-3]"."[lLhH]  return parse_halfreg (&yylval.reg, T_REG_I, yytext);
+[iI][0-3]           return parse_reg (&yylval.reg, T_REG_I, yytext);
+[hH][lL][tT]                            return HLT;
+[hH][iI]                                return HI;
+[gG][tT]                                return GT;
+[gG][eE]                                return GE;
+[fF][uU]                                yylval.value = M_FU; return MMOD;
+[fF][pP]         _REG.regno = REG_FP; return REG;
+[fF][pP]"."[lL]  _REG.regno = REG_FP; return HALF_REG;
+[fF][pP]"."[hH]  _REG.regno = REG_FP | F_REG_HIGH; return HALF_REG;
+
+[eE][xX][tT][rR][aA][cC][tT]            return EXTRACT;
+[eE][xX][pP][aA][dD][jJ]                return EXPADJ;
+[eE][xX][cC][pP][tT]                    return EXCPT;
+[eE][mM][uU][eE][xX][cC][pP][tT]        return EMUEXCPT;
+[dD][iI][vV][sS]                        return DIVS;
+[dD][iI][vV][qQ]                        return DIVQ;
+[dD][iI][sS][aA][lL][gG][nN][eE][xX][cC][pP][tT]  return DISALGNEXCPT;
+[dD][eE][pP][oO][sS][iI][tT]            return DEPOSIT;
+[dD][bB][gG][hH][aA][lL][tT]            return DBGHALT;
+[dD][bB][gG][cC][mM][pP][lL][xX]        return DBGCMPLX;
+[dD][bB][gG][aA][lL]                    return DBGAL;
+[dD][bB][gG][aA][hH]                    return DBGAH;
+[dD][bB][gG][aA]                        return DBGA;
+[dD][bB][gG]                            return DBG;
+[cC][yY][cC][lL][eE][sS]2  { _REG.regno = REG_CYCLES2; return REG; }
+[cC][yY][cC][lL][eE][sS]  { _REG.regno = REG_CYCLES; return REG; }
+[cC][sS][yY][nN][cC]                    return CSYNC;
+[cC][oO]                                return CO;
+[cC][lL][iI]                            return CLI;
+
+[cC][cC]     _REG.regno = REG_CC; return CCREG;
+[cC][aA][lL][lL]"."[xX]                 { BEGIN 0; return CALL;}
+[cC][aA][lL][lL]                        { BEGIN 0; return CALL;}
+[bB][yY][tT][eE][uU][nN][pP][aA][cC][kK] return BYTEUNPACK;
+[bB][yY][tT][eE][pP][aA][cC][kK]        return BYTEPACK;
+[bB][yY][tT][eE][oO][pP]16[mM]          return BYTEOP16M;
+[bB][yY][tT][eE][oO][pP]16[pP]          return BYTEOP16P;
+[bB][yY][tT][eE][oO][pP]3[pP]           return BYTEOP3P;
+[bB][yY][tT][eE][oO][pP]2[mM]           return BYTEOP2M;
+[bB][yY][tT][eE][oO][pP]2[pP]           return BYTEOP2P;
+[bB][yY][tT][eE][oO][pP]1[pP]           return BYTEOP1P;
+[bB][yY]                                return BY;
+[bB][xX][oO][rR][sS][hH][iI][fF][tT]    return BXORSHIFT;
+[bB][xX][oO][rR]                        return BXOR;
+
+[bB][rR][eE][vV]                        return BREV;
+[bB][pP]                                return BP;
+[bB][iI][tT][tT][sS][tT]                return BITTST;
+[bB][iI][tT][tT][gG][lL]                return BITTGL;
+[bB][iI][tT][sS][eE][tT]                return BITSET;
+[bB][iI][tT][mM][uU][xX]                return BITMUX;
+[bB][iI][tT][cC][lL][rR]                return BITCLR;
+[bB][0-3]"."[lLhH]  return parse_halfreg (&yylval.reg, T_REG_B, yytext);
+[bB][0-3]           return parse_reg (&yylval.reg, T_REG_B, yytext);
+[bB]                                    return B;
+[aA][zZ]  _REG.regno = S_AZ;   return STATUS_REG;
+[aA][nN]  _REG.regno = S_AN;   return STATUS_REG;
+[aA][qQ]  _REG.regno = S_AQ;   return STATUS_REG;
+[aA][cC]0 _REG.regno = S_AC0;  return STATUS_REG;
+[aA][cC]1 _REG.regno = S_AC1;  return STATUS_REG;
+[aA][vV]0 _REG.regno = S_AV0;  return STATUS_REG;
+[aA][vV]0[sS] _REG.regno = S_AV0S; return STATUS_REG;
+[aA][vV]1 _REG.regno = S_AV1;  return STATUS_REG;
+[aA][vV]1[sS] _REG.regno = S_AV1S; return STATUS_REG;
+[vV] _REG.regno = S_V; return STATUS_REG;
+[vV][sS]  _REG.regno = S_VS;   return STATUS_REG;
+
+
+[aA][sS][tT][aA][tT]   _REG.regno = REG_ASTAT; return REG;
+[aA][sS][hH][iI][fF][tT]                return ASHIFT;
+[aA][sS][lL]                            return ASL;
+[aA][sS][rR]                            return ASR;
+[aA][lL][iI][gG][nN]8                   return ALIGN8;
+[aA][lL][iI][gG][nN]16                  return ALIGN16;
+[aA][lL][iI][gG][nN]24                  return ALIGN24;
+[aA]1"."[lL]    return A_ONE_DOT_L;
+[aA]0"."[lL]    return A_ZERO_DOT_L;
+[aA]1"."[hH]    return A_ONE_DOT_H;
+[aA]0"."[hH]    return A_ZERO_DOT_H;
+[aA][bB][sS]                            return ABS;
+abort                                   return ABORT;
+[aA]1"."[xX]    _REG.regno = REG_A1x; return REG;
+[aA]1"."[wW]    _REG.regno = REG_A1w; return REG;
+[aA]1           _REG.regno = REG_A1;  return REG_A_DOUBLE_ONE;
+[aA]0"."[xX]    _REG.regno = REG_A0x; return REG;
+[aA]0"."[wW]    _REG.regno = REG_A0w; return REG;
+[aA]0           _REG.regno = REG_A0;  return REG_A_DOUBLE_ZERO;
+[Gg][Oo][Tt]	return GOT;
+[Gg][Oo][Tt]"17"[Mm]"4" return GOT17M4;
+[Ff][Uu][Nn][Cc][Dd][Ee][Ss][Cc]"_"[Gg][Oo][Tt]"17"[Mm]"4" return FUNCDESC_GOT17M4;
+[Pp][Ll][Tt][Pp][Cc]	return PLTPC;
+
+
+"~"                     return TILDA;
+"|="                    return _BAR_ASSIGN;
+"|"                     return BAR;
+"^="                    return _CARET_ASSIGN;
+"^"                     return CARET;
+"]"                     return RBRACK;
+"["                     return LBRACK;
+">>>="                  return _GREATER_GREATER_GREATER_THAN_ASSIGN;
+">>="                   return _GREATER_GREATER_ASSIGN;
+">>>"                   return _GREATER_GREATER_GREATER;
+">>"                    return GREATER_GREATER;
+"=="                    return _ASSIGN_ASSIGN;
+"="                     return ASSIGN;
+"<="                    return _LESS_THAN_ASSIGN;
+"<<="                   return _LESS_LESS_ASSIGN;
+"<<"                    return LESS_LESS;
+"<"                     return LESS_THAN;
+"("                     return LPAREN;
+")"                     return RPAREN;
+":"                     return COLON;
+"/"                     return SLASH;
+"-="                    return _MINUS_ASSIGN;
+"+|+"					return _PLUS_BAR_PLUS;
+"-|+"					return _MINUS_BAR_PLUS;
+"+|-"					return _PLUS_BAR_MINUS;
+"-|-"					return _MINUS_BAR_MINUS;
+"--"                    return _MINUS_MINUS;
+"-"                     return MINUS;
+","                     return COMMA;
+"+="                    return _PLUS_ASSIGN;
+"++"                    return _PLUS_PLUS;
+"+"                     return PLUS;
+"*="                    return _STAR_ASSIGN;
+"*"                     return STAR;
+"&="                    return _AMPERSAND_ASSIGN;
+"&"                     return AMPERSAND;
+"%"                     return PERCENT;
+"!"                     return BANG;
+";"                     return SEMICOLON;
+"=!"			return _ASSIGN_BANG;
+"||"			return DOUBLE_BAR;
+"@"			return AT;
+<KEYWORD>[pP][rR][eE][fF][eE][tT][cC][hH]        return PREFETCH;
+<KEYWORD>[uU][nN][lL][iI][nN][kK]                return UNLINK;
+<KEYWORD>[lL][iI][nN][kK]                        return LINK;
+<KEYWORD>[iI][dD][lL][eE]                        return IDLE;
+<KEYWORD>[iI][fF][lL][uU][sS][hH]                return IFLUSH;
+<KEYWORD>[fF][lL][uU][sS][hH][iI][nN][vV]        return FLUSHINV;
+<KEYWORD>[fF][lL][uU][sS][hH]                    return FLUSH;
+([0-9]+)|(0[xX][0-9a-fA-F]+)|([bhfodBHOFD]#[0-9a-fA-F]+)|(0.[0-9]+) {
+    yylval.value = parse_int (&yytext);
+    return NUMBER;
+  }
+[A-Za-z_$.][A-Za-z0-9_$.]* { 
+    yylval.symbol = symbol_find_or_make (yytext);
+    symbol_mark_used (yylval.symbol);
+    return SYMBOL; 
+  }
+[0-9][bfBF] {
+    char *name;
+    char *ref = strdup (yytext);
+    if (ref[1] == 'b' || ref[1] == 'B')
+      {
+        name = fb_label_name ((int) (ref[0] - '0'), 0);
+	yylval.symbol = symbol_find (name);
+
+	if ((yylval.symbol != NULL)
+             && (S_IS_DEFINED (yylval.symbol)))
+          return SYMBOL;
+	as_bad ("backward reference to unknown label %d:", 
+						  (int) (ref[0] - '0')); 
+      }
+    else if (ref[1] == 'f' || ref[1] == 'F')
+      {
+        /* Forward reference.  Expect symbol to be undefined or
+           unknown.  undefined: seen it before.  unknown: never seen
+           it before.
+
+           Construct a local label name, then an undefined symbol.
+           Just return it as never seen before.  */
+
+        name = fb_label_name ((int) (ref[0] - '0'), 1);
+	yylval.symbol = symbol_find_or_make (name);
+	/* We have no need to check symbol properties.  */
+	return SYMBOL;
+      }                                  
+  }                                  
+[ \t\n]                                    ;
+"/*".*"*/"                                 ;
+.                                          return yytext[0];
+%%
+static long parse_int (char **end)
+{
+  char fmt = '\0';
+  int not_done = 1;
+  int shiftvalue = 0;
+  char * char_bag;
+  long value = 0;
+  char c;
+  char *arg = *end;
+
+  while (*arg && *arg == ' ')
+    arg++;
+
+  switch (*arg)
+    {
+      case '1':
+      case '2':
+      case '3':
+      case '4':
+      case '5':
+      case '6':
+      case '7':
+      case '8':
+      case '9':
+        fmt = 'd';
+        break;
+
+      case '0':  /* Accept different formated integers hex octal and binary. */
+        {
+	  c = *++arg;
+          arg++;
+	  if (c == 'x' || c == 'X') /* Hex input.  */
+	    fmt = 'h';
+	  else if (c == 'b' || c == 'B')
+	    fmt = 'b';
+	  else if (c == '.')
+	    fmt = 'f';
+	  else
+            {             /* Octal.  */
+	      arg--;
+	      fmt = 'o';
+	    }
+	  break;
+        }
+
+      case 'd':
+      case 'D':
+      case 'h':
+      case 'H':
+      case 'o':
+      case 'O':
+      case 'b':
+      case 'B':
+      case 'f':
+      case 'F':
+        {
+	  fmt = *arg++;
+	  if (*arg == '#')
+	    arg++;
+        }
+    }
+
+  switch (fmt)
+    {
+      case 'h':
+      case 'H':
+        shiftvalue = 4;
+        char_bag = "0123456789ABCDEFabcdef";
+        break;
+
+      case 'o':
+      case 'O':
+        shiftvalue = 3;
+        char_bag = "01234567";
+        break;
+
+      case 'b':
+      case 'B':
+        shiftvalue = 1;
+        char_bag = "01";
+        break;
+
+/* The assembler allows for fractional constants to be created
+   by either the 0.xxxx or the f#xxxx format 
+
+   i.e.   0.5 would result in 0x4000
+
+   note .5 would result in the identifier .5.
+
+   The assembler converts to fractional format 1.15 by the simple rule:
+
+             value = (short) (finput * (1 << 15)).  */
+
+      case 'f':
+      case 'F':
+        {
+          float fval = 0.0;
+          float pos = 10.0;
+          while (1)
+            {
+              int c;
+              c = *arg++;
+
+              if (c >= '0' && c <= '9')
+                {
+                  float digit = (c - '0') / pos;
+                  fval = fval + digit;
+                  pos = pos * 10.0;
+                }
+              else
+                {
+	          *--arg = c;
+                  value = (short) (fval * (1 << 15));
+                  break;
+                }
+            }
+          *end = arg+1;
+          return value;
+        }
+
+      case 'd':
+      case 'D':
+      default:
+        {
+          while (1)
+            {
+              int c;
+              c = *arg++;
+              if (c >= '0' && c <= '9')
+                value = (value * 10) + (c - '0');
+              else
+                {
+                  /* Constants that are suffixed with k|K are multiplied by 1024
+                     This suffix is only allowed on decimal constants. */
+                  if (c == 'k' || c == 'K')
+                    value *= 1024;
+                  else
+                    *--arg = c;
+                  break;
+                }
+            }
+          *end = arg+1;
+          return value;
+        }
+    }
+
+  while (not_done)
+    {
+      char c;
+      c = *arg++;
+      if (c == 0 || !index (char_bag, c))
+	{
+          not_done = 0;
+          *--arg = c;
+        }
+      else
+        {
+          if (c >= 'a' && c <= 'z')
+            c = c - ('a' - '9') + 1;
+          else if (c >= 'A' && c <= 'Z')
+            c = c - ('A' - '9') + 1;
+
+          c -= '0';
+          value = (value << shiftvalue) + c;
+        }
+    }
+  *end = arg+1;
+  return value;
+}
+
+
+static int parse_reg (Register *r, int cl, char *rt)
+{
+  r->regno = cl | (rt[1] - '0');
+  return REG;
+}
+
+static int parse_halfreg (Register *r, int cl, char *rt)
+{
+  r->regno = cl | (rt[1] - '0');
+
+  switch (rt[3])
+    {
+      case 'b':
+      case 'B':
+	return BYTE_DREG;
+
+      case 'l':
+      case 'L':
+	break;
+
+      case 'h':
+      case 'H':
+	r->regno |= F_REG_HIGH;
+	break;
+    }
+
+  return HALF_REG;
+}
+
+/* Our start state is KEYWORD as we have
+   command keywords such as PREFETCH.  */
+
+void 
+set_start_state (void)
+{
+  BEGIN KEYWORD;
+}
+
+
+#ifndef yywrap
+int
+yywrap ()
+{ 
+  return 1;
+}
+#endif
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
new file mode 100644
index 000000000000..917c2d27ba0f
--- /dev/null
+++ b/gas/config/bfin-parse.y
@@ -0,0 +1,4387 @@
+/* bfin-parse.y  ADI Blackfin parser
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+%{
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <obstack.h>
+
+#include "bfin-aux.h"  // opcode generating auxiliaries
+#include "libbfd.h"
+#include "elf/common.h"
+#include "elf/bfin.h"
+
+#define DSP32ALU(aopcde, HL, dst1, dst0, src0, src1, s, x, aop) \
+	bfin_gen_dsp32alu (HL, aopcde, aop, s, x, dst0, dst1, src0, src1)
+
+#define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+	bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+	                   dst, src0, src1, w0)
+
+#define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
+	bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
+	                    dst, src0, src1, w0)
+
+#define DSP32SHIFT(sopcde, dst0, src0, src1, sop, hls)  \
+	bfin_gen_dsp32shift (sopcde, dst0, src0, src1, sop, hls)
+
+#define DSP32SHIFTIMM(sopcde, dst0, immag, src1, sop, hls)  \
+	bfin_gen_dsp32shiftimm (sopcde, dst0, immag, src1, sop, hls)
+
+#define LDIMMHALF_R(reg, h, s, z, hword) \
+	bfin_gen_ldimmhalf (reg, h, s, z, hword, 1)
+
+#define LDIMMHALF_R5(reg, h, s, z, hword) \
+        bfin_gen_ldimmhalf (reg, h, s, z, hword, 2)
+
+#define LDSTIDXI(ptr, reg, w, sz, z, offset)  \
+	bfin_gen_ldstidxi (ptr, reg, w, sz, z, offset)
+
+#define LDST(ptr, reg, aop, sz, z, w)  \
+	bfin_gen_ldst (ptr, reg, aop, sz, z, w)
+
+#define LDSTII(ptr, reg, offset, w, op)  \
+	bfin_gen_ldstii (ptr, reg, offset, w, op)
+
+#define DSPLDST(i, m, reg, aop, w) \
+	bfin_gen_dspldst (i, reg, aop, w, m)
+
+#define LDSTPMOD(ptr, reg, idx, aop, w) \
+	bfin_gen_ldstpmod (ptr, reg, aop, w, idx)
+
+#define LDSTIIFP(offset, reg, w)  \
+	bfin_gen_ldstiifp (reg, offset, w)
+
+#define LOGI2OP(dst, src, opc) \
+	bfin_gen_logi2op (opc, src, dst.regno & CODE_MASK)
+
+#define ALU2OP(dst, src, opc)  \
+	bfin_gen_alu2op (dst, src, opc)
+
+#define BRCC(t, b, offset) \
+	bfin_gen_brcc (t, b, offset)
+
+#define UJUMP(offset) \
+	bfin_gen_ujump (offset)
+
+#define PROGCTRL(prgfunc, poprnd) \
+	bfin_gen_progctrl (prgfunc, poprnd)
+
+#define PUSHPOPMULTIPLE(dr, pr, d, p, w) \
+	bfin_gen_pushpopmultiple (dr, pr, d, p, w)
+
+#define PUSHPOPREG(reg, w) \
+	bfin_gen_pushpopreg (reg, w)
+
+#define CALLA(addr, s)  \
+	bfin_gen_calla (addr, s)
+
+#define LINKAGE(r, framesize) \
+	bfin_gen_linkage (r, framesize)
+
+#define COMPI2OPD(dst, src, op)  \
+	bfin_gen_compi2opd (dst, src, op)
+
+#define COMPI2OPP(dst, src, op)  \
+	bfin_gen_compi2opp (dst, src, op)
+
+#define DAGMODIK(i, op)  \
+	bfin_gen_dagmodik (i, op)
+
+#define DAGMODIM(i, m, op, br)  \
+	bfin_gen_dagmodim (i, m, op, br)
+
+#define COMP3OP(dst, src0, src1, opc)   \
+	bfin_gen_comp3op (src0, src1, dst, opc)
+
+#define PTR2OP(dst, src, opc)   \
+	bfin_gen_ptr2op (dst, src, opc)
+
+#define CCFLAG(x, y, opc, i, g)  \
+	bfin_gen_ccflag (x, y, opc, i, g)
+
+#define CCMV(src, dst, t) \
+	bfin_gen_ccmv (src, dst, t)
+
+#define CACTRL(reg, a, op) \
+	bfin_gen_cactrl (reg, a, op)
+
+#define LOOPSETUP(soffset, c, rop, eoffset, reg) \
+	bfin_gen_loopsetup (soffset, c, rop, eoffset, reg)
+
+#define HL2(r1, r0)  (IS_H (r1) << 1 | IS_H (r0))
+#define IS_RANGE(bits, expr, sign, mul)    \
+	value_match(expr, bits, sign, mul, 1)
+#define IS_URANGE(bits, expr, sign, mul)    \
+	value_match(expr, bits, sign, mul, 0)
+#define IS_CONST(expr) (expr->type == Expr_Node_Constant)
+#define IS_RELOC(expr) (expr->type != Expr_Node_Constant)
+#define IS_IMM(expr, bits)  value_match (expr, bits, 0, 1, 1)
+#define IS_UIMM(expr, bits)  value_match (expr, bits, 0, 1, 0)
+
+#define IS_PCREL4(expr) \
+	(value_match (expr, 4, 0, 2, 0))
+
+#define IS_LPPCREL10(expr) \
+	(value_match (expr, 10, 0, 2, 0))
+
+#define IS_PCREL10(expr) \
+	(value_match (expr, 10, 0, 2, 1))
+
+#define IS_PCREL12(expr) \
+	(value_match (expr, 12, 0, 2, 1))
+
+#define IS_PCREL24(expr) \
+	(value_match (expr, 24, 0, 2, 1))
+
+
+static int value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned);
+
+extern FILE *errorf;
+extern INSTR_T insn;
+
+static Expr_Node *binary (Expr_Op_Type, Expr_Node *, Expr_Node *);
+static Expr_Node *unary  (Expr_Op_Type, Expr_Node *);
+
+static void notethat (char *format, ...);
+
+char *current_inputline;
+extern char *yytext;
+int yyerror (char *msg);
+
+void error (char *format, ...)
+{
+    va_list ap;
+    char buffer[2000];
+    
+    va_start (ap, format);
+    vsprintf (buffer, format, ap);
+    va_end (ap);
+
+    as_bad (buffer);
+}
+
+int
+yyerror (char *msg)
+{
+  if (msg[0] == '\0')
+    error ("%s", msg);
+
+  else if (yytext[0] != ';')
+    error ("%s. Input text was %s.", msg, yytext);
+  else
+    error ("%s.", msg);
+
+  return -1;
+}
+
+static int
+in_range_p (Expr_Node *expr, int from, int to, unsigned int mask)
+{
+  int val = EXPR_VALUE (expr);
+  if (expr->type != Expr_Node_Constant)
+    return 0;
+  if (val < from || val > to)
+    return 0;
+  return (val & mask) == 0;
+}
+
+extern int yylex (void);
+
+#define imm3(x) EXPR_VALUE (x)
+#define imm4(x) EXPR_VALUE (x)
+#define uimm4(x) EXPR_VALUE (x)
+#define imm5(x) EXPR_VALUE (x)
+#define uimm5(x) EXPR_VALUE (x)
+#define imm6(x) EXPR_VALUE (x)
+#define imm7(x) EXPR_VALUE (x)
+#define imm16(x) EXPR_VALUE (x)
+#define uimm16s4(x) ((EXPR_VALUE (x)) >> 2)
+#define uimm16(x) EXPR_VALUE (x)
+
+/* Return true if a value is inside a range.  */
+#define IN_RANGE(x, low, high) \
+  (((EXPR_VALUE(x)) >= (low)) && (EXPR_VALUE(x)) <= ((high)))
+
+/* Auxiliary functions.  */
+
+static void
+neg_value (Expr_Node *expr)
+{
+  expr->value.i_value = -expr->value.i_value;
+}
+
+static int
+valid_dreg_pair (Register *reg1, Expr_Node *reg2)
+{
+  if (!IS_DREG (*reg1))
+    {
+      yyerror ("Dregs expected");
+      return 0;
+    }
+
+  if (reg1->regno != 1 && reg1->regno != 3)
+    {
+      yyerror ("Bad register pair");
+      return 0;
+    }
+
+  if (imm7 (reg2) != reg1->regno - 1)
+    {
+      yyerror ("Bad register pair");
+      return 0;
+    }
+
+  reg1->regno--;
+  return 1;
+}
+
+static int
+check_multiply_halfregs (Macfunc *aa, Macfunc *ab)
+{
+  if ((!REG_EQUAL (aa->s0, ab->s0) && !REG_EQUAL (aa->s0, ab->s1))
+      || (!REG_EQUAL (aa->s1, ab->s1) && !REG_EQUAL (aa->s1, ab->s0)))
+    return yyerror ("Source multiplication register mismatch");
+
+  return 0;
+}
+
+
+/* Check (vector) mac funcs and ops.  */
+
+static int
+check_macfuncs (Macfunc *aa, Opt_mode *opa,
+		Macfunc *ab, Opt_mode *opb)
+{
+  /* Variables for swapping.  */
+  Macfunc mtmp;
+  Opt_mode otmp;
+
+  /* If a0macfunc comes before a1macfunc, swap them.  */
+	
+  if (aa->n == 0)
+    {
+      /*  (M) is not allowed here.  */
+      if (opa->MM != 0)
+	return yyerror ("(M) not allowed with A0MAC");
+      if (ab->n != 1)
+	return yyerror ("Vector AxMACs can't be same");
+
+      mtmp = *aa; *aa = *ab; *ab = mtmp;
+      otmp = *opa; *opa = *opb; *opb = otmp;
+    }
+  else
+    {
+      if (opb->MM != 0)
+	return yyerror ("(M) not allowed with A0MAC");
+      if (opa->mod != 0)
+	return yyerror ("Bad opt mode");
+      if (ab->n != 0)
+	return yyerror ("Vector AxMACs can't be same");
+    }
+
+  /*  If both ops are != 3, we have multiply_halfregs in both
+  assignment_or_macfuncs.  */
+  if (aa->op == ab->op && aa->op != 3)
+    {
+      if (check_multiply_halfregs (aa, ab) < 0)
+	return -1;
+    }
+  else
+    {
+      /*  Only one of the assign_macfuncs has a half reg multiply
+      Evil trick: Just 'OR' their source register codes:
+      We can do that, because we know they were initialized to 0
+      in the rules that don't use multiply_halfregs.  */
+      aa->s0.regno |= (ab->s0.regno & CODE_MASK);
+      aa->s1.regno |= (ab->s1.regno & CODE_MASK);
+    }
+
+  if (aa->w == ab->w  && aa->P != ab->P)
+    {
+      return yyerror ("macfuncs must differ");
+      if (aa->w && (aa->dst.regno - ab->dst.regno != 1))
+	return yyerror ("Destination Dregs must differ by one");
+    }
+  /* We assign to full regs, thus obey even/odd rules.  */
+  else if ((aa->w && aa->P && IS_EVEN (aa->dst)) 
+	   || (ab->w && ab->P && !IS_EVEN (ab->dst)))
+    return yyerror ("Even/Odd register assignment mismatch");
+  /* We assign to half regs, thus obey hi/low rules.  */
+  else if ( (aa->w && !aa->P && !IS_H (aa->dst)) 
+	    || (ab->w && !aa->P && IS_H (ab->dst)))
+    return yyerror ("High/Low register assignment mismatch");
+
+  /* Make sure first macfunc has got both P flags ORed.  */
+  aa->P |= ab->P;
+
+  /* Make sure mod flags get ORed, too.  */
+  opb->mod |= opa->mod;
+  return 0;	
+}
+
+
+static int
+is_group1 (INSTR_T x)
+{
+  /* Group1 is dpsLDST, LDSTpmod, LDST, LDSTiiFP, LDSTii.  */
+  if ((x->value & 0xc000) == 0x8000 || (x->value == 0x0000))
+    return 1;
+
+  return 0;
+}
+
+static int
+is_group2 (INSTR_T x)
+{
+  if ((((x->value & 0xfc00) == 0x9c00)  /* dspLDST.  */
+       && !((x->value & 0xfde0) == 0x9c60)  /* dagMODim.  */
+       && !((x->value & 0xfde0) == 0x9ce0)  /* dagMODim with bit rev.  */
+       && !((x->value & 0xfde0) == 0x9d60)) /* pick dagMODik.  */
+      || (x->value == 0x0000))
+    return 1;
+  return 0;
+}
+
+%}
+
+%union {
+  INSTR_T instr;
+  Expr_Node *expr;
+  SYMBOL_T symbol;
+  long value;
+  Register reg;
+  Macfunc macfunc;
+  struct { int r0; int s0; int x0; int aop; } modcodes;
+  struct { int r0; } r0;
+  Opt_mode mod;
+}
+
+
+/* Tokens.  */
+
+/* Vector Specific.  */
+%token BYTEOP16P BYTEOP16M
+%token BYTEOP1P BYTEOP2P BYTEOP2M BYTEOP3P
+%token BYTEUNPACK BYTEPACK
+%token PACK
+%token SAA
+%token ALIGN8 ALIGN16 ALIGN24
+%token VIT_MAX
+%token EXTRACT DEPOSIT EXPADJ SEARCH
+%token ONES SIGN SIGNBITS
+
+/* Stack.  */
+%token LINK UNLINK
+
+/* Registers.  */
+%token REG
+%token PC
+%token CCREG BYTE_DREG
+%token REG_A_DOUBLE_ZERO REG_A_DOUBLE_ONE
+%token A_ZERO_DOT_L A_ZERO_DOT_H A_ONE_DOT_L A_ONE_DOT_H
+%token HALF_REG
+
+/* Progctrl.  */
+%token NOP
+%token RTI RTS RTX RTN RTE
+%token HLT IDLE
+%token STI CLI
+%token CSYNC SSYNC
+%token EMUEXCPT
+%token RAISE EXCPT
+%token LSETUP
+%token LOOP
+%token LOOP_BEGIN
+%token LOOP_END
+%token DISALGNEXCPT
+%token JUMP JUMP_DOT_S JUMP_DOT_L
+%token CALL
+
+/* Emulator only.  */
+%token ABORT
+
+/* Operators.  */
+%token NOT TILDA BANG
+%token AMPERSAND BAR
+%token PERCENT
+%token CARET
+%token BXOR
+
+%token MINUS PLUS STAR SLASH
+%token NEG
+%token MIN MAX ABS
+%token DOUBLE_BAR
+%token _PLUS_BAR_PLUS _PLUS_BAR_MINUS _MINUS_BAR_PLUS _MINUS_BAR_MINUS
+%token _MINUS_MINUS _PLUS_PLUS
+
+/* Shift/rotate ops.  */
+%token SHIFT LSHIFT ASHIFT BXORSHIFT
+%token _GREATER_GREATER_GREATER_THAN_ASSIGN
+%token ROT
+%token LESS_LESS GREATER_GREATER  
+%token _GREATER_GREATER_GREATER
+%token _LESS_LESS_ASSIGN _GREATER_GREATER_ASSIGN
+%token DIVS DIVQ
+
+/* In place operators.  */
+%token ASSIGN _STAR_ASSIGN
+%token _BAR_ASSIGN _CARET_ASSIGN _AMPERSAND_ASSIGN
+%token _MINUS_ASSIGN _PLUS_ASSIGN
+
+/* Assignments, comparisons.  */
+%token _ASSIGN_BANG _LESS_THAN_ASSIGN _ASSIGN_ASSIGN
+%token GE LT LE GT
+%token LESS_THAN
+
+/* Cache.  */
+%token FLUSHINV FLUSH
+%token IFLUSH PREFETCH
+
+/* Misc.  */
+%token PRNT
+%token OUTC
+%token WHATREG
+%token TESTSET
+
+/* Modifiers.  */
+%token ASL ASR
+%token B W
+%token NS S CO SCO
+%token TH TL
+%token BP
+%token BREV
+%token X Z
+%token M MMOD
+%token R RND RNDL RNDH RND12 RND20
+%token V
+%token LO HI
+
+/* Bit ops.  */
+%token BITTGL BITCLR BITSET BITTST BITMUX
+
+/* Debug.  */
+%token DBGAL DBGAH DBGHALT DBG DBGA DBGCMPLX
+
+/* Semantic auxiliaries.  */
+
+%token IF COMMA BY
+%token COLON SEMICOLON
+%token RPAREN LPAREN LBRACK RBRACK
+%token STATUS_REG
+%token MNOP
+%token SYMBOL NUMBER
+%token GOT GOT17M4 FUNCDESC_GOT17M4
+%token AT PLTPC
+
+/* Types.  */
+%type <instr> asm
+%type <value> MMOD
+%type <mod> opt_mode
+
+%type <value> NUMBER
+%type <r0> aligndir
+%type <modcodes> byteop_mod
+%type <reg> a_assign
+%type <reg> a_plusassign
+%type <reg> a_minusassign
+%type <macfunc> multiply_halfregs
+%type <macfunc> assign_macfunc 
+%type <macfunc> a_macfunc 
+%type <expr> expr_1
+%type <instr> asm_1
+%type <r0> vmod
+%type <modcodes> vsmod
+%type <modcodes> ccstat
+%type <r0> cc_op
+%type <reg> CCREG
+%type <reg> reg_with_postinc
+%type <reg> reg_with_predec
+
+%type <r0> searchmod
+%type <expr> symbol
+%type <symbol> SYMBOL
+%type <expr> eterm
+%type <reg> REG
+%type <reg> BYTE_DREG
+%type <reg> REG_A_DOUBLE_ZERO
+%type <reg> REG_A_DOUBLE_ONE
+%type <reg> REG_A
+%type <reg> STATUS_REG 
+%type <expr> expr
+%type <r0> xpmod
+%type <r0> xpmod1
+%type <modcodes> smod 
+%type <modcodes> b3_op
+%type <modcodes> rnd_op
+%type <modcodes> post_op
+%type <reg> HALF_REG
+%type <r0> iu_or_nothing
+%type <r0> plus_minus
+%type <r0> asr_asl
+%type <r0> asr_asl_0
+%type <modcodes> sco
+%type <modcodes> amod0
+%type <modcodes> amod1
+%type <modcodes> amod2
+%type <r0> op_bar_op
+%type <r0> w32_or_nothing
+%type <r0> c_align
+%type <r0> min_max
+%type <expr> got
+%type <expr> got_or_expr
+%type <expr> pltpc
+%type <value> any_gotrel GOT GOT17M4 FUNCDESC_GOT17M4
+
+/* Precedence rules.  */
+%left BAR
+%left CARET
+%left AMPERSAND
+%left LESS_LESS GREATER_GREATER
+%left PLUS MINUS
+%left STAR SLASH PERCENT
+
+%right ASSIGN
+
+%right TILDA BANG
+%start statement
+%%
+statement: 
+	| asm
+	{
+	  insn = $1;
+	  if (insn == (INSTR_T) 0)
+	    return NO_INSN_GENERATED;
+	  else if (insn == (INSTR_T) - 1)
+	    return SEMANTIC_ERROR;
+	  else
+	    return INSN_GENERATED;
+	}
+	;
+
+asm: asm_1 SEMICOLON
+	/* Parallel instructions.  */
+	| asm_1 DOUBLE_BAR asm_1 DOUBLE_BAR asm_1 SEMICOLON
+	{
+	  if (($1->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ($3) && is_group2 ($5))
+		$$ = bfin_gen_multi_instr ($1, $3, $5);
+	      else if (is_group2 ($3) && is_group1 ($5))
+		$$ = bfin_gen_multi_instr ($1, $5, $3);
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
+	    }
+	  else if (($3->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ($1) && is_group2 ($5))
+		$$ = bfin_gen_multi_instr ($3, $1, $5);
+	      else if (is_group2 ($1) && is_group1 ($5))
+		$$ = bfin_gen_multi_instr ($3, $5, $1);
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
+	    }
+	  else if (($5->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ($1) && is_group2 ($3))
+		$$ = bfin_gen_multi_instr ($5, $1, $3);
+	      else if (is_group2 ($1) && is_group1 ($3))
+		$$ = bfin_gen_multi_instr ($5, $3, $1);
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
+	    }
+	  else
+	    error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
+	}
+
+	| asm_1 DOUBLE_BAR asm_1 SEMICOLON
+	{
+	  if (($1->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ($3))
+		$$ = bfin_gen_multi_instr ($1, $3, 0);
+	      else if (is_group2 ($3))
+		$$ = bfin_gen_multi_instr ($1, 0, $3);
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 2 must be the 16-bit instruction group");
+	    }
+	  else if (($3->value & 0xf800) == 0xc000)
+	    {
+	      if (is_group1 ($1))
+		$$ = bfin_gen_multi_instr ($3, $1, 0);
+	      else if (is_group2 ($1))
+		$$ = bfin_gen_multi_instr ($3, 0, $1);
+	      else
+		return yyerror ("Wrong 16 bit instructions groups, slot 1 must be the 16-bit instruction group");
+	    }
+	  else if (is_group1 ($1) && is_group2 ($3))
+	      $$ = bfin_gen_multi_instr (0, $1, $3);
+	  else if (is_group2 ($1) && is_group1 ($3))
+	    $$ = bfin_gen_multi_instr (0, $3, $1);
+	  else
+	    return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be the 16-bit instruction group");
+	}
+	| error
+	{
+	$$ = 0;
+	yyerror ("");
+	yyerrok;
+	}
+	;
+
+/* DSPMAC.  */
+
+asm_1:   
+	MNOP
+	{
+	  $$ = DSP32MAC (3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0);
+	}
+	| assign_macfunc opt_mode
+	{
+	  int op0, op1;
+	  int w0 = 0, w1 = 0;
+	  int h00, h10, h01, h11;
+
+	  if ($1.n == 0)
+	    {
+	      if ($2.MM) 
+		return yyerror ("(m) not allowed with a0 unit");
+	      op1 = 3;
+	      op0 = $1.op;
+	      w1 = 0;
+              w0 = $1.w;
+	      h00 = IS_H ($1.s0);
+              h10 = IS_H ($1.s1);
+	      h01 = h11 = 0;
+	    }
+	  else
+	    {
+	      op1 = $1.op;
+	      op0 = 3;
+	      w1 = $1.w;
+              w0 = 0;
+	      h00 = h10 = 0;
+	      h01 = IS_H ($1.s0);
+              h11 = IS_H ($1.s1);
+	    }
+	  $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
+			 &$1.dst, op0, &$1.s0, &$1.s1, w0);
+	}
+
+
+/* VECTOR MACs.  */
+
+	| assign_macfunc opt_mode COMMA assign_macfunc opt_mode
+	{
+	  Register *dst;
+
+	  if (check_macfuncs (&$1, &$2, &$4, &$5) < 0) 
+	    return -1;
+	  notethat ("assign_macfunc (.), assign_macfunc (.)\n");
+
+	  if ($1.w)
+	    dst = &$1.dst;
+	  else
+	    dst = &$4.dst;
+
+	  $$ = DSP32MAC ($1.op, $2.MM, $5.mod, $1.w, $1.P,
+			 IS_H ($1.s0),  IS_H ($1.s1), IS_H ($4.s0), IS_H ($4.s1),
+			 dst, $4.op, &$1.s0, &$1.s1, $4.w);
+	}
+
+/* DSPALU.  */
+
+	| DISALGNEXCPT
+	{
+	  notethat ("dsp32alu: DISALGNEXCPT\n");
+	  $$ = DSP32ALU (18, 0, 0, 0, 0, 0, 0, 0, 3);
+	}
+	| REG ASSIGN LPAREN a_plusassign REG_A RPAREN
+	{
+	  if (IS_DREG ($1) && !IS_A1 ($4) && IS_A1 ($5))
+	    {
+	      notethat ("dsp32alu: dregs = ( A0 += A1 )\n");
+	      $$ = DSP32ALU (11, 0, 0, &$1, 0, 0, 0, 0, 0);
+	    }
+	  else 
+	    return yyerror ("Register mismatch");
+	}	
+	| HALF_REG ASSIGN LPAREN a_plusassign REG_A RPAREN
+	{
+	  if (!IS_A1 ($4) && IS_A1 ($5))
+	    {
+	      notethat ("dsp32alu: dregs_half = ( A0 += A1 )\n");
+	      $$ = DSP32ALU (11, IS_H ($1), 0, &$1, 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+	| A_ZERO_DOT_H ASSIGN HALF_REG
+	{
+	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+	  $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
+	}
+	| A_ONE_DOT_H ASSIGN HALF_REG
+	{
+	  notethat ("dsp32alu: A_ZERO_DOT_H = dregs_hi\n");
+	  $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
+	}
+	| LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
+	  COLON expr COMMA REG COLON expr RPAREN aligndir
+	{
+	  if (!IS_DREG ($2) || !IS_DREG ($4))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$13, $15))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16P (dregs_pair , dregs_pair ) (half)\n");
+	      $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 0);
+	    }
+	}
+
+	| LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLON expr COMMA
+	  REG COLON expr RPAREN aligndir 
+	{
+	  if (!IS_DREG ($2) || !IS_DREG($4))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$13, $15))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEOP16M (dregs_pair , dregs_pair ) (aligndir)\n");
+	      $$ = DSP32ALU (21, 0, &$2, &$4, &$9, &$13, $17.r0, 0, 1);
+	    }
+	}
+
+	| LPAREN REG COMMA REG RPAREN ASSIGN BYTEUNPACK REG COLON expr aligndir
+	{
+	  if (!IS_DREG ($2) || !IS_DREG ($4))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$8, $10))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = BYTEUNPACK dregs_pair (aligndir)\n");
+	      $$ = DSP32ALU (24, 0, &$2, &$4, &$8, 0, $11.r0, 0, 1);
+	    }
+	}
+	| LPAREN REG COMMA REG RPAREN ASSIGN SEARCH REG LPAREN searchmod RPAREN
+	{
+	  if (IS_DREG ($2) && IS_DREG ($4) && IS_DREG ($8))
+	    {
+	      notethat ("dsp32alu: (dregs , dregs ) = SEARCH dregs (searchmod)\n");
+	      $$ = DSP32ALU (13, 0, &$2, &$4, &$8, 0, 0, 0, $10.r0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+	| REG ASSIGN A_ONE_DOT_L PLUS A_ONE_DOT_H COMMA
+	  REG ASSIGN A_ZERO_DOT_L PLUS A_ZERO_DOT_H
+	{
+	  if (IS_DREG ($1) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32alu: dregs = A1.l + A1.h, dregs = A0.l + A0.h  \n");
+	      $$ = DSP32ALU (12, 0, &$1, &$7, 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+
+	| REG ASSIGN REG_A PLUS REG_A COMMA REG ASSIGN REG_A MINUS REG_A amod1 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
+	      && IS_A1 ($9) && !IS_A1 ($11))
+	    {
+	      notethat ("dsp32alu: dregs = A1 + A0 , dregs = A1 - A0 (amod1)\n");
+	      $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 0);
+	      
+	    }
+	  else if (IS_DREG ($1) && IS_DREG ($7) && !REG_SAME ($3, $5)
+		   && !IS_A1 ($9) && IS_A1 ($11))
+	    {
+	      notethat ("dsp32alu: dregs = A0 + A1 , dregs = A0 - A1 (amod1)\n");
+	      $$ = DSP32ALU (17, 0, &$1, &$7, 0, 0, $12.s0, $12.x0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN REG plus_minus REG COMMA REG ASSIGN REG plus_minus REG amod1
+	{
+	  if ($4.r0 == $10.r0) 
+	    return yyerror ("Operators must differ");
+
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5)
+	      && REG_SAME ($3, $9) && REG_SAME ($5, $11))
+	    {
+	      notethat ("dsp32alu: dregs = dregs + dregs,"
+		       "dregs = dregs - dregs (amod1)\n");
+	      $$ = DSP32ALU (4, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+/*  Bar Operations.  */
+
+	| REG ASSIGN REG op_bar_op REG COMMA REG ASSIGN REG op_bar_op REG amod2 
+	{
+	  if (!REG_SAME ($3, $9) || !REG_SAME ($5, $11))
+	    return yyerror ("Differing source registers");
+
+	  if (!IS_DREG ($1) || !IS_DREG ($3) || !IS_DREG ($5) || !IS_DREG ($7)) 
+	    return yyerror ("Dregs expected");
+
+	
+	  if ($4.r0 == 1 && $10.r0 == 2)
+	    {
+	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+	      $$ = DSP32ALU (1, 1, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
+	    }
+	  else if ($4.r0 == 0 && $10.r0 == 3)
+	    {
+	      notethat ("dsp32alu:  dregs = dregs .|. dregs , dregs = dregs .|. dregs (amod2)\n");
+	      $$ = DSP32ALU (1, 0, &$1, &$7, &$3, &$5, $12.s0, $12.x0, $12.r0);
+	    }
+	  else
+	    return yyerror ("Bar operand mismatch");
+	}
+
+	| REG ASSIGN ABS REG vmod
+	{
+	  int op;
+
+	  if (IS_DREG ($1) && IS_DREG ($4))
+	    {
+	      if ($5.r0)
+		{
+		  notethat ("dsp32alu: dregs = ABS dregs (v)\n");
+		  op = 6;
+		}
+	      else
+		{
+		  /* Vector version of ABS.  */
+		  notethat ("dsp32alu: dregs = ABS dregs\n");
+		  op = 7;
+		}
+	      $$ = DSP32ALU (op, 0, 0, &$1, &$4, 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	| a_assign ABS REG_A
+	{
+	  notethat ("dsp32alu: Ax = ABS Ax\n");
+	  $$ = DSP32ALU (16, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
+	}
+	| A_ZERO_DOT_L ASSIGN HALF_REG
+	{
+	  if (IS_DREG_L ($3))
+	    {
+	      notethat ("dsp32alu: A0.l = reg_half\n");
+	      $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("A0.l = Rx.l expected");
+	}
+	| A_ONE_DOT_L ASSIGN HALF_REG
+	{
+	  if (IS_DREG_L ($3))
+	    {
+	      notethat ("dsp32alu: A1.l = reg_half\n");
+	      $$ = DSP32ALU (9, IS_H ($3), 0, 0, &$3, 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("A1.l = Rx.l expected");
+	}
+
+	| REG ASSIGN c_align LPAREN REG COMMA REG RPAREN
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32shift: dregs = ALIGN8 (dregs , dregs )\n");
+	      $$ = DSP32SHIFT (13, &$1, &$7, &$5, $3.r0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+ 	| REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN byteop_mod
+	{
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$5, $7))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+	      $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, $13.s0, 0, $13.r0);
+	    }
+	}
+ 	| REG ASSIGN BYTEOP1P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
+	{
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$5, $7))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP1P (dregs_pair , dregs_pair ) (T)\n");
+	      $$ = DSP32ALU (20, 0, 0, &$1, &$5, &$9, 0, 0, 0);
+	    }
+	}
+
+	| REG ASSIGN BYTEOP2P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
+	  rnd_op
+	{
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$5, $7))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
+	      $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, $13.x0, $13.aop);
+	    }
+	}
+
+	| REG ASSIGN BYTEOP2M LPAREN REG COLON expr COMMA REG COLON expr RPAREN
+	  rnd_op
+	{
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$5, $7))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP2P (dregs_pair , dregs_pair ) (rnd_op)\n");
+	      $$ = DSP32ALU (22, $13.r0, 0, &$1, &$5, &$9, $13.s0, 0, $13.x0);
+	    }
+	}
+
+	| REG ASSIGN BYTEOP3P LPAREN REG COLON expr COMMA REG COLON expr RPAREN
+	  b3_op
+	{
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dregs expected");
+	  else if (!valid_dreg_pair (&$5, $7))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$9, $11))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: dregs = BYTEOP3P (dregs_pair , dregs_pair ) (b3_op)\n");
+	      $$ = DSP32ALU (23, $13.x0, 0, &$1, &$5, &$9, $13.s0, 0, 0);
+	    }
+	}
+
+	| REG ASSIGN BYTEPACK LPAREN REG COMMA REG RPAREN
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32alu: dregs = BYTEPACK (dregs , dregs )\n");
+	      $$ = DSP32ALU (24, 0, 0, &$1, &$5, &$7, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| HALF_REG ASSIGN HALF_REG ASSIGN SIGN LPAREN HALF_REG RPAREN STAR
+	  HALF_REG PLUS SIGN LPAREN HALF_REG RPAREN STAR HALF_REG 
+	{
+	  if (IS_HCOMPL ($1, $3) && IS_HCOMPL ($7, $14) && IS_HCOMPL ($10, $17))
+	    {
+	      notethat ("dsp32alu:	dregs_hi = dregs_lo ="
+		       "SIGN (dregs_hi) * dregs_hi + "
+		       "SIGN (dregs_lo) * dregs_lo \n");
+
+		$$ = DSP32ALU (12, 0, 0, &$1, &$7, &$10, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	| REG ASSIGN REG plus_minus REG amod1 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      if ($6.aop == 0)
+		{
+	          /* No saturation flag specified, generate the 16 bit variant.  */
+		  notethat ("COMP3op: dregs = dregs +- dregs\n");
+		  $$ = COMP3OP (&$1, &$3, &$5, $4.r0);
+		}
+	      else
+		{
+		 /* Saturation flag specified, generate the 32 bit variant.  */
+                 notethat ("dsp32alu: dregs = dregs +- dregs (amod1)\n");
+                 $$ = DSP32ALU (4, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
+		}
+	    }
+	  else
+	    if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($5) && $4.r0 == 0)
+	      {
+		notethat ("COMP3op: pregs = pregs + pregs\n");
+		$$ = COMP3OP (&$1, &$3, &$5, 5);
+	      }
+	    else
+	      return yyerror ("Dregs expected");
+	}
+	| REG ASSIGN min_max LPAREN REG COMMA REG RPAREN vmod
+	{
+	  int op;
+
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      if ($9.r0)
+		op = 6;
+	      else
+		op = 7;
+
+	      notethat ("dsp32alu: dregs = {MIN|MAX} (dregs, dregs)\n");
+	      $$ = DSP32ALU (op, 0, 0, &$1, &$5, &$7, 0, 0, $3.r0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| a_assign MINUS REG_A
+	{
+	  notethat ("dsp32alu: Ax = - Ax\n");
+	  $$ = DSP32ALU (14, IS_A1 ($1), 0, 0, 0, 0, 0, 0, IS_A1 ($3));
+	}
+	| HALF_REG ASSIGN HALF_REG plus_minus HALF_REG amod1
+	{
+	  notethat ("dsp32alu: dregs_lo = dregs_lo +- dregs_lo (amod1)\n");
+	  $$ = DSP32ALU (2 | $4.r0, IS_H ($1), 0, &$1, &$3, &$5,
+			 $6.s0, $6.x0, HL2 ($3, $5));
+	}
+	| a_assign a_assign expr
+	{
+	  if (EXPR_VALUE ($3) == 0 && !REG_SAME ($1, $2))
+	    {
+	      notethat ("dsp32alu: A1 = A0 = 0\n");
+	      $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Bad value, 0 expected");
+	}
+
+	/* Saturating.  */
+	| a_assign REG_A LPAREN S RPAREN
+	{
+	  if (REG_SAME ($1, $2))
+	    {
+	      notethat ("dsp32alu: Ax = Ax (S)\n");
+	      $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Registers must be equal");
+	}
+
+	| HALF_REG ASSIGN REG LPAREN RND RPAREN
+	{
+	  if (IS_DREG ($3))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs (RND)\n");
+	      $$ = DSP32ALU (12, IS_H ($1), 0, &$1, &$3, 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| HALF_REG ASSIGN REG plus_minus REG LPAREN RND12 RPAREN
+	{
+	  if (IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs (+-) dregs (RND12)\n");
+	      $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 0, $4.r0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| HALF_REG ASSIGN REG plus_minus REG LPAREN RND20 RPAREN
+	{
+	  if (IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("dsp32alu: dregs_half = dregs -+ dregs (RND20)\n");
+	      $$ = DSP32ALU (5, IS_H ($1), 0, &$1, &$3, &$5, 0, 1, $4.r0 | 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| a_assign REG_A 
+	{
+	  if (!REG_SAME ($1, $2))
+	    {
+	      notethat ("dsp32alu: An = Am\n");
+	      $$ = DSP32ALU (8, 0, 0, 0, 0, 0, IS_A1 ($1), 0, 3);
+	    }
+	  else
+	    return yyerror ("Accu reg arguments must differ");
+	}
+
+	| a_assign REG
+	{
+	  if (IS_DREG ($2))
+	    {
+	      notethat ("dsp32alu: An = dregs\n");
+	      $$ = DSP32ALU (9, 0, 0, 0, &$2, 0, 1, 0, IS_A1 ($1) << 1);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG ASSIGN HALF_REG xpmod
+	{
+	  if (!IS_H ($3))
+	    {
+	      if ($1.regno == REG_A0x && IS_DREG ($3))
+		{
+		  notethat ("dsp32alu: A0.x = dregs_lo\n");
+		  $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 1);
+		}
+	      else if ($1.regno == REG_A1x && IS_DREG ($3))
+		{
+		  notethat ("dsp32alu: A1.x = dregs_lo\n");
+		  $$ = DSP32ALU (9, 0, 0, 0, &$3, 0, 0, 0, 3);
+		}
+	      else if (IS_DREG ($1) && IS_DREG ($3))
+		{
+		  notethat ("ALU2op: dregs = dregs_lo\n");
+		  $$ = ALU2OP (&$1, &$3, 10 | ($4.r0 ? 0: 1));
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	  else
+	    return yyerror ("Low reg expected");
+	}
+
+	| HALF_REG ASSIGN expr
+	{
+	  notethat ("LDIMMhalf: pregs_half = imm16\n");
+
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
+	  if (!IS_IMM ($3, 16) && !IS_UIMM ($3, 16))
+	    return yyerror ("Constant out of range");
+
+	  $$ = LDIMMHALF_R (&$1, IS_H ($1), 0, 0, $3);
+	}
+
+	| a_assign expr
+	{
+	  notethat ("dsp32alu: An = 0\n");
+
+	  if (imm7 ($2) != 0)
+	    return yyerror ("0 expected");
+
+	  $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 0, 0, IS_A1 ($1));
+	}
+
+	| REG ASSIGN expr xpmod1
+	{
+	  if (!IS_DREG ($1) && !IS_PREG ($1) && !IS_IREG ($1)
+	      && !IS_MREG ($1) && !IS_BREG ($1) && !IS_LREG ($1))
+	    return yyerror ("Wrong register for load immediate");
+
+	  if ($4.r0 == 0)
+	    {
+	      /* 7 bit immediate value if possible.
+		 We will check for that constant value for efficiency
+		 If it goes to reloc, it will be 16 bit.  */
+	      if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_DREG ($1))
+		{
+		  notethat ("COMPI2opD: dregs = imm7 (x) \n");
+		  $$ = COMPI2OPD (&$1, imm7 ($3), 0);
+		}
+	      else if (IS_CONST ($3) && IS_IMM ($3, 7) && IS_PREG ($1))
+		{
+		  notethat ("COMPI2opP: pregs = imm7 (x)\n");
+		  $$ = COMPI2OPP (&$1, imm7 ($3), 0);
+		}
+	      else
+		{
+		  if (IS_CONST ($3) && !IS_IMM ($3, 16))
+		    return yyerror ("Immediate value out of range");
+
+		  notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+		  /* reg, H, S, Z.   */
+		  $$ = LDIMMHALF_R5 (&$1, 0, 1, 0, $3);
+		} 
+	    }
+	  else
+	    {
+	      /* (z) There is no 7 bit zero extended instruction.
+	      If the expr is a relocation, generate it.   */
+
+	      if (IS_CONST ($3) && !IS_UIMM ($3, 16))
+		return yyerror ("Immediate value out of range");
+
+	      notethat ("LDIMMhalf: regs = luimm16 (x)\n");
+	      /* reg, H, S, Z.  */
+	      $$ = LDIMMHALF_R5 (&$1, 0, 0, 1, $3);
+	    }
+	}
+
+	| HALF_REG ASSIGN REG
+	{
+	  if (IS_H ($1))
+	    return yyerror ("Low reg expected");
+
+	  if (IS_DREG ($1) && $3.regno == REG_A0x)
+	    {
+	      notethat ("dsp32alu: dregs_lo = A0.x\n");
+	      $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 0);
+	    }
+	  else if (IS_DREG ($1) && $3.regno == REG_A1x)
+	    {
+	      notethat ("dsp32alu: dregs_lo = A1.x\n");
+	      $$ = DSP32ALU (10, 0, 0, &$1, 0, 0, 0, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN REG op_bar_op REG amod0 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("dsp32alu: dregs = dregs .|. dregs (amod0)\n");
+	      $$ = DSP32ALU (0, 0, 0, &$1, &$3, &$5, $6.s0, $6.x0, $4.r0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN BYTE_DREG xpmod
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      notethat ("ALU2op: dregs = dregs_byte\n");
+	      $$ = ALU2OP (&$1, &$3, 12 | ($4.r0 ? 0: 1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign ABS REG_A COMMA a_assign ABS REG_A
+	{
+	  if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
+	    {
+	      notethat ("dsp32alu: A1 = ABS A1 , A0 = ABS A0\n");
+	      $$ = DSP32ALU (16, 0, 0, 0, 0, 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign MINUS REG_A COMMA a_assign MINUS REG_A
+	{
+	  if (REG_SAME ($1, $3) && REG_SAME ($5, $7) && !REG_SAME ($1, $5))
+	    {
+	      notethat ("dsp32alu: A1 = - A1 , A0 = - A0\n");
+	      $$ = DSP32ALU (14, 0, 0, 0, 0, 0, 0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_minusassign REG_A w32_or_nothing
+	{
+	  if (!IS_A1 ($1) && IS_A1 ($2))
+	    {
+	      notethat ("dsp32alu: A0 -= A1\n");
+	      $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $3.r0, 0, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG _MINUS_ASSIGN expr
+	{
+	  if (IS_IREG ($1) && EXPR_VALUE ($3) == 4)
+	    {
+	      notethat ("dagMODik: iregs -= 4\n");
+	      $$ = DAGMODIK (&$1, 3);
+	    }
+	  else if (IS_IREG ($1) && EXPR_VALUE ($3) == 2)
+	    {
+	      notethat ("dagMODik: iregs -= 2\n");
+	      $$ = DAGMODIK (&$1, 1);
+	    }
+	  else
+	    return yyerror ("Register or value mismatch");
+	}
+
+	| REG _PLUS_ASSIGN REG LPAREN BREV RPAREN
+	{
+	  if (IS_IREG ($1) && IS_MREG ($3))
+	    {
+	      notethat ("dagMODim: iregs += mregs (opt_brev)\n");
+	      /* i, m, op, br.  */
+	      $$ = DAGMODIM (&$1, &$3, 0, 1);
+	    }
+	  else if (IS_PREG ($1) && IS_PREG ($3))
+	    {
+	      notethat ("PTR2op: pregs += pregs (BREV )\n");
+	      $$ = PTR2OP (&$1, &$3, 5);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG _MINUS_ASSIGN REG
+	{
+	  if (IS_IREG ($1) && IS_MREG ($3))
+	    {
+	      notethat ("dagMODim: iregs -= mregs\n");
+	      $$ = DAGMODIM (&$1, &$3, 1, 0);
+	    }
+	  else if (IS_PREG ($1) && IS_PREG ($3))
+	    {
+	      notethat ("PTR2op: pregs -= pregs\n");
+	      $$ = PTR2OP (&$1, &$3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG_A _PLUS_ASSIGN REG_A w32_or_nothing
+	{
+	  if (!IS_A1 ($1) && IS_A1 ($3))
+	    {
+	      notethat ("dsp32alu: A0 += A1 (W32)\n");
+	      $$ = DSP32ALU (11, 0, 0, 0, 0, 0, $4.r0, 0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG _PLUS_ASSIGN REG
+	{
+	  if (IS_IREG ($1) && IS_MREG ($3))
+	    {
+	      notethat ("dagMODim: iregs += mregs\n");
+	      $$ = DAGMODIM (&$1, &$3, 0, 0);
+	    }
+	  else
+	    return yyerror ("iregs += mregs expected");
+	}
+
+	| REG _PLUS_ASSIGN expr
+	{
+	  if (IS_IREG ($1))
+	    {
+	      if (EXPR_VALUE ($3) == 4)
+		{
+		  notethat ("dagMODik: iregs += 4\n");
+		  $$ = DAGMODIK (&$1, 2);
+		}
+	      else if (EXPR_VALUE ($3) == 2)
+		{
+		  notethat ("dagMODik: iregs += 2\n");
+		  $$ = DAGMODIK (&$1, 0);
+		}
+	      else
+		return yyerror ("iregs += [ 2 | 4 ");
+	    }
+	  else if (IS_PREG ($1) && IS_IMM ($3, 7))
+	    {
+	      notethat ("COMPI2opP: pregs += imm7\n");
+	      $$ = COMPI2OPP (&$1, imm7 ($3), 1);
+	    }
+	  else if (IS_DREG ($1) && IS_IMM ($3, 7))
+	    {
+	      notethat ("COMPI2opD: dregs += imm7\n");
+	      $$ = COMPI2OPD (&$1, imm7 ($3), 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+ 	| REG _STAR_ASSIGN REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      notethat ("ALU2op: dregs *= dregs\n");
+	      $$ = ALU2OP (&$1, &$3, 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| SAA LPAREN REG COLON expr COMMA REG COLON expr RPAREN aligndir
+	{
+	  if (!valid_dreg_pair (&$3, $5))
+	    return yyerror ("Bad dreg pair");
+	  else if (!valid_dreg_pair (&$7, $9))
+	    return yyerror ("Bad dreg pair");
+	  else
+	    {
+	      notethat ("dsp32alu: SAA (dregs_pair , dregs_pair ) (aligndir)\n");
+	      $$ = DSP32ALU (18, 0, 0, 0, &$3, &$7, $11.r0, 0, 0);
+	    }
+	}
+
+	| a_assign REG_A LPAREN S RPAREN COMMA a_assign REG_A LPAREN S RPAREN
+	{
+	  if (REG_SAME ($1, $2) && REG_SAME ($7, $8) && !REG_SAME ($1, $7))
+	    {
+	      notethat ("dsp32alu: A1 = A1 (S) , A0 = A0 (S)\n");
+	      $$ = DSP32ALU (8, 0, 0, 0, 0, 0, 1, 0, 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN LPAREN REG PLUS REG RPAREN LESS_LESS expr
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6)
+	      && REG_SAME ($1, $4))
+	    {
+	      if (EXPR_VALUE ($9) == 1)
+		{
+		  notethat ("ALU2op: dregs = (dregs + dregs) << 1\n");
+		  $$ = ALU2OP (&$1, &$6, 4);
+		}
+	      else if (EXPR_VALUE ($9) == 2)
+		{
+		  notethat ("ALU2op: dregs = (dregs + dregs) << 2\n");
+		  $$ = ALU2OP (&$1, &$6, 5);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else if (IS_PREG ($1) && IS_PREG ($4) && IS_PREG ($6)
+		   && REG_SAME ($1, $4))
+	    {
+	      if (EXPR_VALUE ($9) == 1)
+		{
+		  notethat ("PTR2op: pregs = (pregs + pregs) << 1\n");
+		  $$ = PTR2OP (&$1, &$6, 6);
+		}
+	      else if (EXPR_VALUE ($9) == 2)
+		{
+		  notethat ("PTR2op: pregs = (pregs + pregs) << 2\n");
+		  $$ = PTR2OP (&$1, &$6, 7);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+			
+/*  COMP3 CCFLAG.  */
+	| REG ASSIGN REG BAR REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("COMP3op: dregs = dregs | dregs\n");
+	      $$ = COMP3OP (&$1, &$3, &$5, 3);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	| REG ASSIGN REG CARET REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("COMP3op: dregs = dregs ^ dregs\n");
+	      $$ = COMP3OP (&$1, &$3, &$5, 4);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	| REG ASSIGN REG PLUS LPAREN REG LESS_LESS expr RPAREN
+	{
+	  if (IS_PREG ($1) && IS_PREG ($3) && IS_PREG ($6))
+	    {
+	      if (EXPR_VALUE ($8) == 1)
+		{
+		  notethat ("COMP3op: pregs = pregs + (pregs << 1)\n");
+		  $$ = COMP3OP (&$1, &$3, &$6, 6);
+		}
+	      else if (EXPR_VALUE ($8) == 2)
+		{
+		  notethat ("COMP3op: pregs = pregs + (pregs << 2)\n");
+		  $$ = COMP3OP (&$1, &$3, &$6, 7);
+		}
+	      else
+		  return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	| CCREG ASSIGN REG_A _ASSIGN_ASSIGN REG_A
+	{
+	  if (!REG_SAME ($3, $5))
+	    {
+	      notethat ("CCflag: CC = A0 == A1\n");
+	      $$ = CCFLAG (0, 0, 5, 0, 0);
+	    }
+	  else
+	    return yyerror ("CC register expected");
+	}
+	| CCREG ASSIGN REG_A LESS_THAN REG_A
+	{
+	  if (!REG_SAME ($3, $5))
+	    {
+	      notethat ("CCflag: CC = A0 < A1\n");
+	      $$ = CCFLAG (0, 0, 6, 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+	| CCREG ASSIGN REG LESS_THAN REG iu_or_nothing
+	{
+	  if (REG_CLASS($3) == REG_CLASS($5))
+	    {
+	      notethat ("CCflag: CC = dpregs < dpregs\n");
+	      $$ = CCFLAG (&$3, $5.regno & CODE_MASK, $6.r0, 0, IS_PREG ($3) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Compare only of same register class");
+	}
+	| CCREG ASSIGN REG LESS_THAN expr iu_or_nothing
+	{
+	  if (($6.r0 == 1 && IS_IMM ($5, 3))
+	      || ($6.r0 == 3 && IS_UIMM ($5, 3)))
+	    {
+	      notethat ("CCflag: CC = dpregs < (u)imm3\n");
+	      $$ = CCFLAG (&$3, imm3 ($5), $6.r0, 1, IS_PREG ($3) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Bad constant value");
+	}
+	| CCREG ASSIGN REG _ASSIGN_ASSIGN REG
+	{
+	  if (REG_CLASS($3) == REG_CLASS($5))
+	    {
+	      notethat ("CCflag: CC = dpregs == dpregs\n");
+	      $$ = CCFLAG (&$3, $5.regno & CODE_MASK, 0, 0, IS_PREG ($3) ? 1 : 0);
+	    } 
+	}
+	| CCREG ASSIGN REG _ASSIGN_ASSIGN expr
+	{
+	  if (IS_IMM ($5, 3))
+	    {
+	      notethat ("CCflag: CC = dpregs == imm3\n");
+	      $$ = CCFLAG (&$3, imm3 ($5), 0, 1, IS_PREG ($3) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Bad constant range");
+	}
+	| CCREG ASSIGN REG_A _LESS_THAN_ASSIGN REG_A
+	{
+	  if (!REG_SAME ($3, $5))
+	    {
+	      notethat ("CCflag: CC = A0 <= A1\n");
+	      $$ = CCFLAG (0, 0, 7, 0, 0);
+	    }
+	  else
+	    return yyerror ("CC register expected");
+	}
+	| CCREG ASSIGN REG _LESS_THAN_ASSIGN REG iu_or_nothing
+	{
+	  if (REG_CLASS($3) == REG_CLASS($5))
+	    {
+	      notethat ("CCflag: CC = pregs <= pregs (..)\n");
+	      $$ = CCFLAG (&$3, $5.regno & CODE_MASK,
+			   1 + $6.r0, 0, IS_PREG ($3) ? 1 : 0);
+	    }
+	  else
+	    return yyerror ("Compare only of same register class");
+	}
+	| CCREG ASSIGN REG _LESS_THAN_ASSIGN expr iu_or_nothing
+	{
+	  if (($6.r0 == 1 && IS_IMM ($5, 3))
+	      || ($6.r0 == 3 && IS_UIMM ($5, 3)))
+	    {
+	      if (IS_DREG ($3))
+		{
+		  notethat ("CCflag: CC = dregs <= (u)imm3\n");
+		  /*    x       y     opc     I     G   */
+		  $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 0);
+		}
+	      else if (IS_PREG ($3))
+		{
+		  notethat ("CCflag: CC = pregs <= (u)imm3\n");
+		  /*    x       y     opc     I     G   */
+		  $$ = CCFLAG (&$3, imm3 ($5), 1 + $6.r0, 1, 1);
+		}
+	      else
+		return yyerror ("Dreg or Preg expected");
+	    }
+	  else
+	    return yyerror ("Bad constant value");
+	}
+
+	| REG ASSIGN REG AMPERSAND REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_DREG ($5))
+	    {
+	      notethat ("COMP3op: dregs = dregs & dregs\n");
+	      $$ = COMP3OP (&$1, &$3, &$5, 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| ccstat
+	{
+	  notethat ("CC2stat operation\n");
+	  $$ = bfin_gen_cc2stat ($1.r0, $1.x0, $1.s0);
+	}
+
+	| REG ASSIGN REG
+	{
+	  if (IS_ALLREG ($1) && IS_ALLREG ($3))
+	    {
+	      notethat ("REGMV: allregs = allregs\n");
+	      $$ = bfin_gen_regmv (&$3, &$1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| CCREG ASSIGN REG
+	{
+	  if (IS_DREG ($3))
+	    {
+	      notethat ("CC2dreg: CC = dregs\n");
+	      $$ = bfin_gen_cc2dreg (1, &$3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN CCREG
+	{
+	  if (IS_DREG ($1))
+	    {
+	      notethat ("CC2dreg: dregs = CC\n");
+	      $$ = bfin_gen_cc2dreg (0, &$1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| CCREG _ASSIGN_BANG CCREG
+	{
+	  notethat ("CC2dreg: CC =! CC\n");
+	  $$ = bfin_gen_cc2dreg (3, 0);
+	}
+			
+/* DSPMULT.  */
+
+	| HALF_REG ASSIGN multiply_halfregs opt_mode
+	{
+	  notethat ("dsp32mult: dregs_half = multiply_halfregs (opt_mode)\n");
+
+	  if (!IS_H ($1) && $4.MM)
+	    return yyerror ("(M) not allowed with MAC0");
+
+	  if (IS_H ($1))
+	    {
+	      $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 0,
+			      IS_H ($3.s0), IS_H ($3.s1), 0, 0,
+			      &$1, 0, &$3.s0, &$3.s1, 0);
+	    }
+	  else
+	    {
+	      $$ = DSP32MULT (0, 0, $4.mod, 0, 0,
+			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
+			      &$1, 0, &$3.s0, &$3.s1, 1);
+		}	
+	}
+
+	| REG ASSIGN multiply_halfregs opt_mode 
+	{
+	  /* Odd registers can use (M).  */
+	  if (!IS_DREG ($1))
+	    return yyerror ("Dreg expected");
+
+	  if (!IS_EVEN ($1))
+	    {
+	      notethat ("dsp32mult: dregs = multiply_halfregs (opt_mode)\n");
+
+	      $$ = DSP32MULT (0, $4.MM, $4.mod, 1, 1,
+			      IS_H ($3.s0), IS_H ($3.s1), 0, 0,
+			      &$1, 0, &$3.s0, &$3.s1, 0);
+	    }
+	  else if ($4.MM == 0)
+	    {
+	      notethat ("dsp32mult: dregs = multiply_halfregs opt_mode\n");
+	      $$ = DSP32MULT (0, 0, $4.mod, 0, 1,
+			      0, 0, IS_H ($3.s0), IS_H ($3.s1), 
+			      &$1,  0, &$3.s0, &$3.s1, 1);
+	    }
+	  else
+	    return yyerror ("Register or mode mismatch");
+	}
+
+	| HALF_REG ASSIGN multiply_halfregs opt_mode COMMA
+          HALF_REG ASSIGN multiply_halfregs opt_mode
+	{
+	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
+	    return yyerror ("Dregs expected");
+
+	  if (check_multiply_halfregs (&$3, &$8) < 0)
+	    return -1;
+
+	  if (IS_H ($1) && !IS_H ($6))
+	    {
+	      notethat ("dsp32mult: dregs_hi = multiply_halfregs mxd_mod, "
+		       "dregs_lo = multiply_halfregs opt_mode\n");
+	      $$ = DSP32MULT (0, $4.MM, $9.mod, 1, 0,
+			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			      &$1, 0, &$3.s0, &$3.s1, 1);
+	    }
+	  else if (!IS_H ($1) && IS_H ($6) && $4.MM == 0)
+	    {
+	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 0,
+			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			      &$1, 0, &$3.s0, &$3.s1, 1);
+	    }
+	  else
+	    return yyerror ("Multfunc Register or mode mismatch");
+	}
+
+	| REG ASSIGN multiply_halfregs opt_mode COMMA REG ASSIGN multiply_halfregs opt_mode 
+	{
+	  if (!IS_DREG ($1) || !IS_DREG ($6)) 
+	    return yyerror ("Dregs expected");
+
+	  if (check_multiply_halfregs (&$3, &$8) < 0)
+	    return -1;
+
+	  notethat ("dsp32mult: dregs = multiply_halfregs mxd_mod, "
+		   "dregs = multiply_halfregs opt_mode\n");
+	  if (IS_EVEN ($1))
+	    {
+	      if ($6.regno - $1.regno != 1 || $4.MM != 0)
+		return yyerror ("Dest registers or mode mismatch");
+
+	      /*   op1       MM      mmod  */
+	      $$ = DSP32MULT (0, 0, $9.mod, 1, 1,
+			      IS_H ($8.s0), IS_H ($8.s1), IS_H ($3.s0), IS_H ($3.s1),
+			      &$1, 0, &$3.s0, &$3.s1, 1);
+	      
+	    }
+	  else
+	    {
+	      if ($1.regno - $6.regno != 1)
+		return yyerror ("Dest registers mismatch");
+	      
+	      $$ = DSP32MULT (0, $9.MM, $9.mod, 1, 1,
+			      IS_H ($3.s0), IS_H ($3.s1), IS_H ($8.s0), IS_H ($8.s1),
+			      &$1, 0, &$3.s0, &$3.s1, 1);
+	    }
+	}
+
+
+/* SHIFTs.  */
+	| a_assign ASHIFT REG_A BY HALF_REG
+	{
+	  if (!REG_SAME ($1, $3))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_DREG ($5) && !IS_H ($5))
+	    {
+	      notethat ("dsp32shift: A0 = ASHIFT A0 BY dregs_lo\n");
+	      $$ = DSP32SHIFT (3, 0, &$5, 0, 0, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| HALF_REG ASSIGN ASHIFT HALF_REG BY HALF_REG smod
+	{
+	  if (IS_DREG ($6) && !IS_H ($6))
+	    {
+	      notethat ("dsp32shift: dregs_half = ASHIFT dregs_half BY dregs_lo\n");
+	      $$ = DSP32SHIFT (0, &$1, &$6, &$4, $7.s0, HL2 ($1, $4));
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| a_assign REG_A LESS_LESS expr
+	{
+	  if (!REG_SAME ($1, $2))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_UIMM ($4, 5))
+	    {
+	      notethat ("dsp32shiftimm: A0 = A0 << uimm5\n");
+	      $$ = DSP32SHIFTIMM (3, 0, imm5 ($4), 0, 0, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+
+	| REG ASSIGN REG LESS_LESS expr vsmod
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
+	    {
+	      if ($6.r0)
+		{
+		  /*  Vector?  */
+		  notethat ("dsp32shiftimm: dregs = dregs << expr (V, .)\n");
+		  $$ = DSP32SHIFTIMM (1, &$1, imm4 ($5), &$3, $6.s0 ? 1 : 2, 0);
+		}
+	      else
+		{
+		  notethat ("dsp32shiftimm: dregs =  dregs << uimm5 (.)\n");
+		  $$ = DSP32SHIFTIMM (2, &$1, imm6 ($5), &$3, $6.s0 ? 1 : 2, 0);
+		}
+	    }
+	  else if ($6.s0 == 0 && IS_PREG ($1) && IS_PREG ($3))
+	    {
+	      if (EXPR_VALUE ($5) == 2)
+		{
+		  notethat ("PTR2op: pregs = pregs << 2\n");
+		  $$ = PTR2OP (&$1, &$3, 1);
+		}
+	      else if (EXPR_VALUE ($5) == 1)
+		{
+		  notethat ("COMP3op: pregs = pregs << 1\n");
+		  $$ = COMP3OP (&$1, &$3, &$3, 5);
+		}
+	      else
+		return yyerror ("Bad shift value");
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+	| HALF_REG ASSIGN HALF_REG LESS_LESS expr
+	{
+	  if (IS_UIMM ($5, 4))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+	      $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+	| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod 
+	{
+	  if (IS_UIMM ($5, 4))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+	      $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+	    }
+	  else
+	    return yyerror ("Bad shift value");
+	}
+	| REG ASSIGN ASHIFT REG BY HALF_REG vsmod
+	{
+	  int op;
+
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG ($6) && !IS_H ($6))
+	    {
+	      if ($7.r0)
+		{
+		  op = 1;
+		  notethat ("dsp32shift: dregs = ASHIFT dregs BY "
+			   "dregs_lo (V, .)\n");
+		}
+	      else
+		{
+		  
+		  op = 2;
+		  notethat ("dsp32shift: dregs = ASHIFT dregs BY dregs_lo (.)\n");
+		}
+	      $$ = DSP32SHIFT (op, &$1, &$6, &$4, $7.s0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+/*  EXPADJ.  */
+	| HALF_REG ASSIGN EXPADJ LPAREN REG COMMA HALF_REG RPAREN vmod
+	{
+	  if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs , dregs_lo )\n");
+	      $$ = DSP32SHIFT (7, &$1, &$7, &$5, $9.r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+
+
+	| HALF_REG ASSIGN EXPADJ LPAREN HALF_REG COMMA HALF_REG RPAREN
+	{
+	  if (IS_DREG_L ($1) && IS_DREG_L ($5) && IS_DREG_L ($7))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_lo, dregs_lo)\n");
+	      $$ = DSP32SHIFT (7, &$1, &$7, &$5, 2, 0);
+	    }
+	  else if (IS_DREG_L ($1) && IS_DREG_H ($5) && IS_DREG_L ($7))
+	    {
+	      notethat ("dsp32shift: dregs_lo = EXPADJ (dregs_hi, dregs_lo)\n");
+	      $$ = DSP32SHIFT (7, &$1, &$7, &$5, 3, 0);
+	    }
+	  else
+	    return yyerror ("Bad shift value or register");
+	}
+
+/* DEPOSIT.  */
+
+	| REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs )\n");
+	      $$ = DSP32SHIFT (10, &$1, &$7, &$5, 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN DEPOSIT LPAREN REG COMMA REG RPAREN LPAREN X RPAREN
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32shift: dregs = DEPOSIT (dregs , dregs ) (X)\n");
+	      $$ = DSP32SHIFT (10, &$1, &$7, &$5, 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN EXTRACT LPAREN REG COMMA HALF_REG RPAREN xpmod 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG_L ($7))
+	    {
+	      notethat ("dsp32shift: dregs = EXTRACT (dregs, dregs_lo ) (.)\n");
+	      $$ = DSP32SHIFT (10, &$1, &$7, &$5, $9.r0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign REG_A _GREATER_GREATER_GREATER expr
+	{
+	  if (!REG_SAME ($1, $2))
+	    return yyerror ("Aregs must be same");
+
+	  if (IS_UIMM ($4, 5))
+	    {
+	      notethat ("dsp32shiftimm: Ax = Ax >>> uimm5\n");
+	      $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 0, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Shift value range error");
+	}
+	| a_assign LSHIFT REG_A BY HALF_REG
+	{
+	  if (REG_SAME ($1, $3) && IS_DREG_L ($5))
+	    {
+	      notethat ("dsp32shift: Ax = LSHIFT Ax BY dregs_lo\n");
+	      $$ = DSP32SHIFT (3, 0, &$5, 0, 1, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN LSHIFT HALF_REG BY HALF_REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
+	    {
+	      notethat ("dsp32shift: dregs_lo = LSHIFT dregs_hi BY dregs_lo\n");
+	      $$ = DSP32SHIFT (0, &$1, &$6, &$4, 2, HL2 ($1, $4));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN LSHIFT REG BY HALF_REG vmod
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
+	    {
+	      notethat ("dsp32shift: dregs = LSHIFT dregs BY dregs_lo (V )\n");
+	      $$ = DSP32SHIFT ($7.r0 ? 1: 2, &$1, &$6, &$4, 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN SHIFT REG BY HALF_REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
+	    {
+	      notethat ("dsp32shift: dregs = SHIFT dregs BY dregs_lo\n");
+	      $$ = DSP32SHIFT (2, &$1, &$6, &$4, 2, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign REG_A GREATER_GREATER expr
+	{
+	  if (REG_SAME ($1, $2) && IS_IMM ($4, 6) >= 0)
+	    {
+	      notethat ("dsp32shiftimm: Ax = Ax >> imm6\n");
+	      $$ = DSP32SHIFTIMM (3, 0, -imm6 ($4), 0, 1, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Accu register expected");
+	}
+
+	| REG ASSIGN REG GREATER_GREATER expr vmod
+	{
+	  if ($6.r0 == 1)
+	    {
+	      if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
+		{
+		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5 (V)\n");
+		  $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, 2, 0);
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	  else
+	    {
+	      if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
+		{
+		  notethat ("dsp32shiftimm: dregs = dregs >> uimm5\n");
+		  $$ = DSP32SHIFTIMM (2, &$1, -imm6 ($5), &$3, 2, 0);
+		}
+	      else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 2)
+		{
+		  notethat ("PTR2op: pregs = pregs >> 2\n");
+		  $$ = PTR2OP (&$1, &$3, 3);
+		}
+	      else if (IS_PREG ($1) && IS_PREG ($3) && EXPR_VALUE ($5) == 1)
+		{
+		  notethat ("PTR2op: pregs = pregs >> 1\n");
+		  $$ = PTR2OP (&$1, &$3, 4);
+		}
+	      else
+	        return yyerror ("Register mismatch");
+	    }
+	}
+	| HALF_REG ASSIGN HALF_REG GREATER_GREATER expr
+	{
+	  if (IS_UIMM ($5, 5))
+	    {
+	      notethat ("dsp32shiftimm:  dregs_half =  dregs_half >> uimm5\n");
+	      $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3, 2, HL2 ($1, $3));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+	| HALF_REG ASSIGN HALF_REG _GREATER_GREATER_GREATER expr smod
+	{
+	  if (IS_UIMM ($5, 5))
+	    {
+	      notethat ("dsp32shiftimm: dregs_half = dregs_half >>> uimm5\n");
+	      $$ = DSP32SHIFTIMM (0, &$1, -uimm5 ($5), &$3,
+				  $6.s0, HL2 ($1, $3));
+	    }
+	  else
+	    return yyerror ("Register or modifier mismatch");
+	}
+
+
+	| REG ASSIGN REG _GREATER_GREATER_GREATER expr vsmod
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3) && IS_UIMM ($5, 5))
+	    {
+	      if ($6.r0)
+		{
+		  /* Vector?  */
+		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (V, .)\n");
+		  $$ = DSP32SHIFTIMM (1, &$1, -uimm5 ($5), &$3, $6.s0, 0);
+		}
+	      else
+		{
+		  notethat ("dsp32shiftimm: dregs  =  dregs >>> uimm5 (.)\n");
+		  $$ = DSP32SHIFTIMM (2, &$1, -uimm5 ($5), &$3, $6.s0, 0);
+		}
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN ONES REG
+	{
+	  if (IS_DREG_L ($1) && IS_DREG ($4))
+	    {
+	      notethat ("dsp32shift: dregs_lo = ONES dregs\n");
+	      $$ = DSP32SHIFT (6, &$1, 0, &$4, 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN PACK LPAREN HALF_REG COMMA HALF_REG RPAREN
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32shift: dregs = PACK (dregs_hi , dregs_hi )\n");
+	      $$ = DSP32SHIFT (4, &$1, &$7, &$5, HL2 ($5, $7), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN CCREG ASSIGN BXORSHIFT LPAREN REG_A COMMA REG RPAREN 
+	{
+	  if (IS_DREG ($1)
+	      && $7.regno == REG_A0
+	      && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXORSHIFT (A0 , dregs )\n");
+	      $$ = DSP32SHIFT (11, &$1, &$9, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG RPAREN
+	{
+	  if (IS_DREG ($1)
+	      && $7.regno == REG_A0
+	      && IS_DREG ($9) && !IS_H ($1) && !IS_A1 ($7))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , dregs)\n");
+	      $$ = DSP32SHIFT (11, &$1, &$9, 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN CCREG ASSIGN BXOR LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
+	{
+	  if (IS_DREG ($1) && !IS_H ($1) && !REG_SAME ($7, $9))
+	    {
+	      notethat ("dsp32shift: dregs_lo = CC = BXOR (A0 , A1 , CC)\n");
+	      $$ = DSP32SHIFT (12, &$1, 0, 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign ROT REG_A BY HALF_REG
+	{
+	  if (REG_SAME ($1, $3) && IS_DREG_L ($5))
+	    {
+	      notethat ("dsp32shift: Ax = ROT Ax BY dregs_lo\n");
+	      $$ = DSP32SHIFT (3, 0, &$5, 0, 2, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN ROT REG BY HALF_REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_DREG_L ($6))
+	    {
+	      notethat ("dsp32shift: dregs = ROT dregs BY dregs_lo\n");
+	      $$ = DSP32SHIFT (2, &$1, &$6, &$4, 3, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign ROT REG_A BY expr 
+	{
+	  if (IS_IMM ($5, 6))
+	    {
+	      notethat ("dsp32shiftimm: An = ROT An BY imm6\n");
+	      $$ = DSP32SHIFTIMM (3, 0, imm6 ($5), 0, 2, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN ROT REG BY expr 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4) && IS_IMM ($6, 6))
+	    {
+	      $$ = DSP32SHIFTIMM (2, &$1, imm6 ($6), &$4, 3, IS_A1 ($1));
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN SIGNBITS REG_A
+	{
+	  if (IS_DREG_L ($1))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS An\n");
+	      $$ = DSP32SHIFT (6, &$1, 0, 0, IS_A1 ($4), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN SIGNBITS REG
+	{
+	  if (IS_DREG_L ($1) && IS_DREG ($4))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs\n");
+	      $$ = DSP32SHIFT (5, &$1, 0, &$4, 0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| HALF_REG ASSIGN SIGNBITS HALF_REG
+	{
+	  if (IS_DREG_L ($1))
+	    {
+	      notethat ("dsp32shift: dregs_lo = SIGNBITS dregs_lo\n");
+	      $$ = DSP32SHIFT (5, &$1, 0, &$4, 1 + IS_H ($4), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+	
+	/* The ASR bit is just inverted here. */
+	| HALF_REG ASSIGN VIT_MAX LPAREN REG RPAREN asr_asl 
+	{
+	  if (IS_DREG_L ($1) && IS_DREG ($5))
+	    {
+	      notethat ("dsp32shift: dregs_lo = VIT_MAX (dregs) (..)\n");
+	      $$ = DSP32SHIFT (9, &$1, 0, &$5, ($7.r0 ? 0 : 1), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| REG ASSIGN VIT_MAX LPAREN REG COMMA REG RPAREN asr_asl 
+	{
+	  if (IS_DREG ($1) && IS_DREG ($5) && IS_DREG ($7))
+	    {
+	      notethat ("dsp32shift: dregs = VIT_MAX (dregs, dregs) (ASR)\n");
+	      $$ = DSP32SHIFT (9, &$1, &$7, &$5, 2 | ($9.r0 ? 0 : 1), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| BITMUX LPAREN REG COMMA REG COMMA REG_A RPAREN asr_asl
+	{
+	  if (IS_DREG ($3) && IS_DREG ($5) && !IS_A1 ($7))
+	    {
+	      notethat ("dsp32shift: BITMUX (dregs , dregs , A0) (ASR)\n");
+	      $$ = DSP32SHIFT (8, 0, &$3, &$5, $9.r0, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| a_assign BXORSHIFT LPAREN REG_A COMMA REG_A COMMA CCREG RPAREN
+	{
+	  if (!IS_A1 ($1) && !IS_A1 ($4) && IS_A1 ($6))
+	    {
+	      notethat ("dsp32shift: A0 = BXORSHIFT (A0 , A1 , CC )\n");
+	      $$ = DSP32SHIFT (12, 0, 0, 0, 0, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+
+/* LOGI2op:	BITCLR (dregs, uimm5).  */
+	| BITCLR LPAREN REG COMMA expr RPAREN
+	{
+	  if (IS_DREG ($3) && IS_UIMM ($5, 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      $$ = LOGI2OP ($3, uimm5 ($5), 4);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+/* LOGI2op:	BITSET (dregs, uimm5).  */
+	| BITSET LPAREN REG COMMA expr RPAREN
+	{
+	  if (IS_DREG ($3) && IS_UIMM ($5, 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      $$ = LOGI2OP ($3, uimm5 ($5), 2);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+/* LOGI2op:	BITTGL (dregs, uimm5).  */
+	| BITTGL LPAREN REG COMMA expr RPAREN
+	{
+	  if (IS_DREG ($3) && IS_UIMM ($5, 5))
+	    {
+	      notethat ("LOGI2op: BITCLR (dregs , uimm5 )\n");
+	      $$ = LOGI2OP ($3, uimm5 ($5), 3);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| CCREG _ASSIGN_BANG BITTST LPAREN REG COMMA expr RPAREN
+	{
+	  if (IS_DREG ($5) && IS_UIMM ($7, 5))
+	    {
+	      notethat ("LOGI2op: CC =! BITTST (dregs , uimm5 )\n");
+	      $$ = LOGI2OP ($5, uimm5 ($7), 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch or value error");
+	}
+
+	| CCREG ASSIGN BITTST LPAREN REG COMMA expr RPAREN
+	{
+	  if (IS_DREG ($5) && IS_UIMM ($7, 5))
+	    {
+	      notethat ("LOGI2op: CC = BITTST (dregs , uimm5 )\n");
+	      $$ = LOGI2OP ($5, uimm5 ($7), 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch or value error");
+	}
+
+	| IF BANG CCREG REG ASSIGN REG
+	{
+	  if ((IS_DREG ($4) || IS_PREG ($4))
+	      && (IS_DREG ($6) || IS_PREG ($6)))
+	    {
+	      notethat ("ccMV: IF ! CC gregs = gregs\n");
+	      $$ = CCMV (&$6, &$4, 0);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| IF CCREG REG ASSIGN REG
+	{
+	  if ((IS_DREG ($5) || IS_PREG ($5))
+	      && (IS_DREG ($3) || IS_PREG ($3)))
+	    {
+	      notethat ("ccMV: IF CC gregs = gregs\n");
+	      $$ = CCMV (&$5, &$3, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+	| IF BANG CCREG JUMP expr
+	{
+	  if (IS_PCREL10 ($5))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      $$ = BRCC (0, 0, $5);
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+
+	| IF BANG CCREG JUMP expr LPAREN BP RPAREN
+	{
+	  if (IS_PCREL10 ($5))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      $$ = BRCC (0, 1, $5);
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+
+	| IF CCREG JUMP expr
+	{
+	  if (IS_PCREL10 ($4))
+	    {
+	      notethat ("BRCC: IF CC JUMP  pcrel11m2\n");
+	      $$ = BRCC (1, 0, $4);
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+
+	| IF CCREG JUMP expr LPAREN BP RPAREN
+	{
+	  if (IS_PCREL10 ($4))
+	    {
+	      notethat ("BRCC: IF !CC JUMP  pcrel11m2\n");
+	      $$ = BRCC (1, 1, $4);
+	    }
+	  else
+	    return yyerror ("Bad jump offset");
+	}
+	| NOP
+	{
+	  notethat ("ProgCtrl: NOP\n");
+	  $$ = PROGCTRL (0, 0);
+	}
+
+	| RTS
+	{
+	  notethat ("ProgCtrl: RTS\n");
+	  $$ = PROGCTRL (1, 0);
+	}
+
+	| RTI
+	{
+	  notethat ("ProgCtrl: RTI\n");
+	  $$ = PROGCTRL (1, 1);
+	}
+
+	| RTX
+	{
+	  notethat ("ProgCtrl: RTX\n");
+	  $$ = PROGCTRL (1, 2);
+	}
+
+	| RTN
+	{
+	  notethat ("ProgCtrl: RTN\n");
+	  $$ = PROGCTRL (1, 3);
+	}
+
+	| RTE
+	{
+	  notethat ("ProgCtrl: RTE\n");
+	  $$ = PROGCTRL (1, 4);
+	}
+
+	| IDLE
+	{
+	  notethat ("ProgCtrl: IDLE\n");
+	  $$ = PROGCTRL (2, 0);
+	}
+
+	| CSYNC
+	{
+	  notethat ("ProgCtrl: CSYNC\n");
+	  $$ = PROGCTRL (2, 3);
+	}
+
+	| SSYNC
+	{
+	  notethat ("ProgCtrl: SSYNC\n");
+	  $$ = PROGCTRL (2, 4);
+	}
+
+	| EMUEXCPT
+	{
+	  notethat ("ProgCtrl: EMUEXCPT\n");
+	  $$ = PROGCTRL (2, 5);
+	}
+
+	| CLI REG
+	{
+	  if (IS_DREG ($2))
+	    {
+	      notethat ("ProgCtrl: CLI dregs\n");
+	      $$ = PROGCTRL (3, $2.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Dreg expected for CLI");
+	}
+
+	| STI REG
+	{
+	  if (IS_DREG ($2))
+	    {
+	      notethat ("ProgCtrl: STI dregs\n");
+	      $$ = PROGCTRL (4, $2.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Dreg expected for STI");
+	}
+
+	| JUMP LPAREN REG RPAREN
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("ProgCtrl: JUMP (pregs )\n");
+	      $$ = PROGCTRL (5, $3.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect jump");
+	}
+
+	| CALL LPAREN REG RPAREN
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("ProgCtrl: CALL (pregs )\n");
+	      $$ = PROGCTRL (6, $3.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect call");
+	}
+
+	| CALL LPAREN PC PLUS REG RPAREN
+	{
+	  if (IS_PREG ($5))
+	    {
+	      notethat ("ProgCtrl: CALL (PC + pregs )\n");
+	      $$ = PROGCTRL (7, $5.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect call");
+	}
+
+	| JUMP LPAREN PC PLUS REG RPAREN
+	{
+	  if (IS_PREG ($5))
+	    {
+	      notethat ("ProgCtrl: JUMP (PC + pregs )\n");
+	      $$ = PROGCTRL (8, $5.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Bad register for indirect jump");
+	}
+
+	| RAISE expr
+	{
+	  if (IS_UIMM ($2, 4))
+	    {
+	      notethat ("ProgCtrl: RAISE uimm4\n");
+	      $$ = PROGCTRL (9, uimm4 ($2));
+	    }
+	  else
+	    return yyerror ("Bad value for RAISE");
+	}
+
+	| EXCPT expr
+	{
+		notethat ("ProgCtrl: EMUEXCPT\n");
+		$$ = PROGCTRL (10, uimm4 ($2));
+	}
+
+	| TESTSET LPAREN REG RPAREN
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("ProgCtrl: TESTSET (pregs )\n");
+	      $$ = PROGCTRL (11, $3.regno & CODE_MASK);
+	    }
+	  else
+	    return yyerror ("Preg expected");
+	}
+
+	| JUMP expr
+	{
+	  if (IS_PCREL12 ($2))
+	    {
+	      notethat ("UJUMP: JUMP pcrel12\n");
+	      $$ = UJUMP ($2);
+	    }
+	  else
+	    return yyerror ("Bad value for relative jump");
+	}
+
+	| JUMP_DOT_S expr
+	{
+	  if (IS_PCREL12 ($2))
+	    {
+	      notethat ("UJUMP: JUMP_DOT_S pcrel12\n");
+	      $$ = UJUMP($2);
+	    }
+	  else
+	    return yyerror ("Bad value for relative jump");
+	}
+
+	| JUMP_DOT_L expr
+	{
+	  if (IS_PCREL24 ($2))
+	    {
+	      notethat ("CALLa: jump.l pcrel24\n");
+	      $$ = CALLA ($2, 0);
+	    }
+	  else
+	    return yyerror ("Bad value for long jump");
+	}
+
+	| JUMP_DOT_L pltpc
+	{
+	  if (IS_PCREL24 ($2))
+	    {
+	      notethat ("CALLa: jump.l pcrel24\n");
+	      $$ = CALLA ($2, 2);
+	    }
+	  else
+	    return yyerror ("Bad value for long jump");
+	}
+
+	| CALL expr
+	{
+	  if (IS_PCREL24 ($2))
+	    {
+	      notethat ("CALLa: CALL pcrel25m2\n");
+	      $$ = CALLA ($2, 1);
+	    }
+	  else
+	    return yyerror ("Bad call address");
+	}
+	| CALL pltpc
+	{
+	  if (IS_PCREL24 ($2))
+	    {
+	      notethat ("CALLa: CALL pcrel25m2\n");
+	      $$ = CALLA ($2, 2);
+	    }
+	  else
+	    return yyerror ("Bad call address");
+	}
+
+/* ALU2ops.  */
+/* ALU2op:	DIVQ (dregs, dregs).  */
+	| DIVQ LPAREN REG COMMA REG RPAREN
+	{
+	  if (IS_DREG ($3) && IS_DREG ($5))
+	    $$ = ALU2OP (&$3, &$5, 8);
+	  else
+	    return yyerror ("Bad registers for DIVQ");
+	}
+
+	| DIVS LPAREN REG COMMA REG RPAREN
+	{
+	  if (IS_DREG ($3) && IS_DREG ($5))
+	    $$ = ALU2OP (&$3, &$5, 9);
+	  else
+	    return yyerror ("Bad registers for DIVS");
+	}
+
+	| REG ASSIGN MINUS REG vsmod
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4))
+	    {
+	      if ($5.r0 == 0 && $5.s0 == 0 && $5.aop == 0)
+		{
+		  notethat ("ALU2op: dregs = - dregs\n");
+		  $$ = ALU2OP (&$1, &$4, 14);
+		}
+	      else if ($5.r0 == 1 && $5.s0 == 0 && $5.aop == 3)
+		{
+		  notethat ("dsp32alu: dregs = - dregs (.)\n");
+		  $$ = DSP32ALU (15, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
+		}
+	      else
+		{
+		  notethat ("dsp32alu: dregs = - dregs (.)\n");
+		  $$ = DSP32ALU (7, 0, 0, &$1, &$4, 0, $5.s0, 0, 3);
+		}
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG ASSIGN TILDA REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($4))
+	    {
+	      notethat ("ALU2op: dregs = ~dregs\n");
+	      $$ = ALU2OP (&$1, &$4, 15);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG _GREATER_GREATER_ASSIGN REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      notethat ("ALU2op: dregs >>= dregs\n");
+	      $$ = ALU2OP (&$1, &$3, 1);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG _GREATER_GREATER_ASSIGN expr
+	{
+	  if (IS_DREG ($1) && IS_UIMM ($3, 5))
+	    {
+	      notethat ("LOGI2op: dregs >>= uimm5\n");
+	      $$ = LOGI2OP ($1, uimm5 ($3), 6);
+	    }
+	  else
+	    return yyerror ("Dregs expected or value error");
+	}
+
+	| REG _GREATER_GREATER_GREATER_THAN_ASSIGN REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      notethat ("ALU2op: dregs >>>= dregs\n");
+	      $$ = ALU2OP (&$1, &$3, 0);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG _LESS_LESS_ASSIGN REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      notethat ("ALU2op: dregs <<= dregs\n");
+	      $$ = ALU2OP (&$1, &$3, 2);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+	| REG _LESS_LESS_ASSIGN expr
+	{
+	  if (IS_DREG ($1) && IS_UIMM ($3, 5))
+	    {
+	      notethat ("LOGI2op: dregs <<= uimm5\n");
+	      $$ = LOGI2OP ($1, uimm5 ($3), 7);
+	    }
+	  else
+	    return yyerror ("Dregs expected or const value error");
+	}
+
+
+	| REG _GREATER_GREATER_GREATER_THAN_ASSIGN expr
+	{
+	  if (IS_DREG ($1) && IS_UIMM ($3, 5))
+	    {
+	      notethat ("LOGI2op: dregs >>>= uimm5\n");
+	      $$ = LOGI2OP ($1, uimm5 ($3), 5);
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+
+/* Cache Control.  */
+
+	| FLUSH LBRACK REG RBRACK
+	{
+	  notethat ("CaCTRL: FLUSH [ pregs ]\n");
+	  if (IS_PREG ($3))
+	    $$ = CACTRL (&$3, 0, 2);
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+	| FLUSH reg_with_postinc
+	{
+	  if (IS_PREG ($2))
+	    {
+	      notethat ("CaCTRL: FLUSH [ pregs ++ ]\n");
+	      $$ = CACTRL (&$2, 1, 2);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+	| FLUSHINV LBRACK REG RBRACK
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("CaCTRL: FLUSHINV [ pregs ]\n");
+	      $$ = CACTRL (&$3, 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+	| FLUSHINV reg_with_postinc
+	{
+	  if (IS_PREG ($2))
+	    {
+	      notethat ("CaCTRL: FLUSHINV [ pregs ++ ]\n");
+	      $$ = CACTRL (&$2, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+/* CaCTRL:	IFLUSH [pregs].  */
+	| IFLUSH LBRACK REG RBRACK
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("CaCTRL: IFLUSH [ pregs ]\n");
+	      $$ = CACTRL (&$3, 0, 3);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+	| IFLUSH reg_with_postinc
+	{
+	  if (IS_PREG ($2))
+	    {
+	      notethat ("CaCTRL: IFLUSH [ pregs ++ ]\n");
+	      $$ = CACTRL (&$2, 1, 3);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for FLUSH");
+	}
+
+	| PREFETCH LBRACK REG RBRACK
+	{
+	  if (IS_PREG ($3))
+	    {
+	      notethat ("CaCTRL: PREFETCH [ pregs ]\n");
+	      $$ = CACTRL (&$3, 0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for PREFETCH");
+	}
+
+	| PREFETCH reg_with_postinc
+	{
+	  if (IS_PREG ($2))
+	    {
+	      notethat ("CaCTRL: PREFETCH [ pregs ++ ]\n");
+	      $$ = CACTRL (&$2, 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for PREFETCH");
+	}
+
+/* LOAD/STORE.  */
+/* LDST:	B [ pregs <post_op> ] = dregs.  */
+
+	| B LBRACK REG post_op RBRACK ASSIGN REG
+	{
+	  if (IS_PREG ($3) && IS_DREG ($7))
+	    {
+	      notethat ("LDST: B [ pregs <post_op> ] = dregs\n");
+	      $$ = LDST (&$3, &$7, $4.x0, 2, 0, 1);
+	    }
+	  else
+	    return yyerror ("Register mismatch");
+	}
+
+/* LDSTidxI:	B [ pregs + imm16 ] = dregs.  */
+	| B LBRACK REG plus_minus expr RBRACK ASSIGN REG
+	{
+	  if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 1) && IS_DREG ($8))
+	    {
+	      notethat ("LDST: B [ pregs + imm16 ] = dregs\n");
+	      if ($4.r0)
+		neg_value ($5);
+	      $$ = LDSTIDXI (&$3, &$8, 1, 2, 0, $5);
+	    }
+	  else
+	    return yyerror ("Register mismatch or const size wrong");
+	}
+
+
+/* LDSTii:	W [ pregs + uimm4s2 ] = dregs.  */
+	| W LBRACK REG plus_minus expr RBRACK ASSIGN REG
+	{
+	  if (IS_PREG ($3) && IS_URANGE (4, $5, $4.r0, 2) && IS_DREG ($8))
+	    {
+	      notethat ("LDSTii: W [ pregs +- uimm5m2 ] = dregs\n");
+	      $$ = LDSTII (&$3, &$8, $5, 1, 1);
+	    }
+	  else if (IS_PREG ($3) && IS_RANGE(16, $5, $4.r0, 2) && IS_DREG ($8))
+	    {
+	      notethat ("LDSTidxI: W [ pregs + imm17m2 ] = dregs\n");
+	      if ($4.r0)
+		neg_value ($5);
+	      $$ = LDSTIDXI (&$3, &$8, 1, 1, 0, $5);
+	    }
+	  else
+	    return yyerror ("Bad register(s) or wrong constant size");
+	}
+
+/* LDST:	W [ pregs <post_op> ] = dregs.  */
+	| W LBRACK REG post_op RBRACK ASSIGN REG
+	{
+	  if (IS_PREG ($3) && IS_DREG ($7))
+	    {
+	      notethat ("LDST: W [ pregs <post_op> ] = dregs\n");
+	      $$ = LDST (&$3, &$7, $4.x0, 1, 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register(s) for STORE");
+	}
+
+	| W LBRACK REG post_op RBRACK ASSIGN HALF_REG
+	{
+	  if (IS_IREG ($3))
+	    {
+	      notethat ("dspLDST: W [ iregs <post_op> ] = dregs_half\n");
+	      $$ = DSPLDST (&$3, 1 + IS_H ($7), &$7, $4.x0, 1);
+	    }
+	  else if ($4.x0 == 2 && IS_PREG ($3) && IS_DREG ($7))
+	    {
+	      notethat ("LDSTpmod: W [ pregs <post_op>] = dregs_half\n");
+	      $$ = LDSTPMOD (&$3, &$7, &$3, 1 + IS_H ($7), 1);
+	      
+	    }
+	  else
+	    return yyerror ("Bad register(s) for STORE");
+	}
+
+/* LDSTiiFP:	[ FP - const ] = dpregs.  */
+	| LBRACK REG plus_minus expr RBRACK ASSIGN REG
+	{
+	  Expr_Node *tmp = $4;
+	  int ispreg = IS_PREG ($7);
+
+	  if (!IS_PREG ($2))
+	    return yyerror ("Preg expected for indirect");
+
+	  if (!IS_DREG ($7) && !ispreg)
+	    return yyerror ("Bad source register for STORE");
+
+	  if ($3.r0)
+	    tmp = unary (Expr_Op_Type_NEG, tmp);
+
+	  if (in_range_p (tmp, 0, 63, 3))
+	    {
+	      notethat ("LDSTii: dpregs = [ pregs + uimm6m4 ]\n");
+	      $$ = LDSTII (&$2, &$7, tmp, 1, ispreg ? 3 : 0);
+	    }
+	  else if ($2.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+	    {
+	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+	      tmp = unary (Expr_Op_Type_NEG, tmp);
+	      $$ = LDSTIIFP (tmp, &$7, 1);
+	    }
+	  else if (in_range_p (tmp, -131072, 131071, 3))
+	    {
+	      notethat ("LDSTidxI: [ pregs + imm18m4 ] = dpregs\n");
+	      $$ = LDSTIDXI (&$2, &$7, 1, 0, ispreg ? 1: 0, tmp);
+	    }
+	  else
+	    return yyerror ("Displacement out of range for store");
+	}
+
+	| REG ASSIGN W LBRACK REG plus_minus expr RBRACK xpmod
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5) && IS_URANGE (4, $7, $6.r0, 2))
+	    {
+	      notethat ("LDSTii: dregs = W [ pregs + uimm4s2 ] (.)\n");
+	      $$ = LDSTII (&$5, &$1, $7, 0, 1 << $9.r0);
+	    }
+	  else if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 2))
+	    {
+	      notethat ("LDSTidxI: dregs = W [ pregs + imm17m2 ] (.)\n");
+	      if ($6.r0)
+		neg_value ($7);
+	      $$ = LDSTIDXI (&$5, &$1, 0, 1, $9.r0, $7);
+	    }
+	  else
+	    return yyerror ("Bad register or constant for LOAD");
+	}	
+
+	| HALF_REG ASSIGN W LBRACK REG post_op RBRACK
+	{
+	  if (IS_IREG ($5))
+	    {
+	      notethat ("dspLDST: dregs_half = W [ iregs ]\n");
+	      $$ = DSPLDST(&$5, 1 + IS_H ($1), &$1, $6.x0, 0);
+	    }
+	  else if ($6.x0 == 2 && IS_DREG ($1) && IS_PREG ($5))
+	    {
+	      notethat ("LDSTpmod: dregs_half = W [ pregs ]\n");
+	      $$ = LDSTPMOD (&$5, &$1, &$5, 1 + IS_H ($1), 0);
+	    }
+	  else
+	    return yyerror ("Bad register or post_op for LOAD");
+	}
+
+
+	| REG ASSIGN W LBRACK REG post_op RBRACK xpmod
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5))
+	    {
+	      notethat ("LDST: dregs = W [ pregs <post_op> ] (.)\n");
+	      $$ = LDST (&$5, &$1, $6.x0, 1, $8.r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+
+	| REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK xpmod
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
+	    {
+	      notethat ("LDSTpmod: dregs = W [ pregs ++ pregs ] (.)\n");
+	      $$ = LDSTPMOD (&$5, &$1, &$7, 3, $9.r0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+
+	| HALF_REG ASSIGN W LBRACK REG _PLUS_PLUS REG RBRACK
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5) && IS_PREG ($7))
+	    {
+	      notethat ("LDSTpmod: dregs_half = W [ pregs ++ pregs ]\n");
+	      $$ = LDSTPMOD (&$5, &$1, &$7, 1 + IS_H ($1), 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+
+	| LBRACK REG post_op RBRACK ASSIGN REG
+	{
+	  if (IS_IREG ($2) && IS_DREG ($6))
+	    {
+	      notethat ("dspLDST: [ iregs <post_op> ] = dregs\n");
+	      $$ = DSPLDST(&$2, 0, &$6, $3.x0, 1);
+	    }
+	  else if (IS_PREG ($2) && IS_DREG ($6))
+	    {
+	      notethat ("LDST: [ pregs <post_op> ] = dregs\n");
+	      $$ = LDST (&$2, &$6, $3.x0, 0, 0, 1);
+	    }
+	  else if (IS_PREG ($2) && IS_PREG ($6))
+	    {
+	      notethat ("LDST: [ pregs <post_op> ] = pregs\n");
+	      $$ = LDST (&$2, &$6, $3.x0, 0, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+
+	| LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN REG
+	{
+	  if (! IS_DREG ($7))
+	    return yyerror ("Expected Dreg for last argument");
+
+	  if (IS_IREG ($2) && IS_MREG ($4))
+	    {
+	      notethat ("dspLDST: [ iregs ++ mregs ] = dregs\n");
+	      $$ = DSPLDST(&$2, $4.regno & CODE_MASK, &$7, 3, 1);
+	    }
+	  else if (IS_PREG ($2) && IS_PREG ($4))
+	    {
+	      notethat ("LDSTpmod: [ pregs ++ pregs ] = dregs\n");
+	      $$ = LDSTPMOD (&$2, &$7, &$4, 0, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+			
+	| W LBRACK REG _PLUS_PLUS REG RBRACK ASSIGN HALF_REG
+	{
+	  if (!IS_DREG ($8))
+	    return yyerror ("Expect Dreg as last argument");
+	  if (IS_PREG ($3) && IS_PREG ($5))
+	    {
+	      notethat ("LDSTpmod: W [ pregs ++ pregs ] = dregs_half\n");
+	      $$ = LDSTPMOD (&$3, &$8, &$5, 1 + IS_H ($8), 1);
+	    }
+	  else
+	    return yyerror ("Bad register for STORE");
+	}
+
+	| REG ASSIGN B LBRACK REG plus_minus expr RBRACK xpmod
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5) && IS_RANGE(16, $7, $6.r0, 1))
+	    {
+	      notethat ("LDSTidxI: dregs = B [ pregs + imm16 ] (%c)\n",
+		       $9.r0 ? 'X' : 'Z');
+	      if ($6.r0)
+		neg_value ($7);
+	      $$ = LDSTIDXI (&$5, &$1, 0, 2, $9.r0, $7);
+	    }
+	  else
+	    return yyerror ("Bad register or value for LOAD");
+	}
+
+	| REG ASSIGN B LBRACK REG post_op RBRACK xpmod
+	{
+	  if (IS_DREG ($1) && IS_PREG ($5))
+	    {
+	      notethat ("LDST: dregs = B [ pregs <post_op> ] (%c)\n",
+		       $8.r0 ? 'X' : 'Z');
+	      $$ = LDST (&$5, &$1, $6.x0, 2, $8.r0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+			
+	| REG ASSIGN LBRACK REG _PLUS_PLUS REG RBRACK
+	{
+	  if (IS_DREG ($1) && IS_IREG ($4) && IS_MREG ($6))
+	    {
+	      notethat ("dspLDST: dregs = [ iregs ++ mregs ]\n");
+	      $$ = DSPLDST(&$4, $6.regno & CODE_MASK, &$1, 3, 0);
+	    }
+	  else if (IS_DREG ($1) && IS_PREG ($4) && IS_PREG ($6))
+	    {
+	      notethat ("LDSTpmod: dregs = [ pregs ++ pregs ]\n");
+	      $$ = LDSTPMOD (&$4, &$1, &$6, 0, 0);
+	    }
+	  else
+	    return yyerror ("Bad register for LOAD");
+	}
+
+	| REG ASSIGN LBRACK REG plus_minus got_or_expr RBRACK
+	{
+	  Expr_Node *tmp = $6;
+	  int ispreg = IS_PREG ($1);
+	  int isgot = IS_RELOC($6);
+
+	  if (!IS_PREG ($4))
+	    return yyerror ("Preg expected for indirect");
+
+	  if (!IS_DREG ($1) && !ispreg)
+	    return yyerror ("Bad destination register for LOAD");
+
+	  if ($5.r0)
+	    tmp = unary (Expr_Op_Type_NEG, tmp);
+
+	  if(isgot){
+	      notethat ("LDSTidxI: dpregs = [ pregs + sym@got ]\n");
+	      $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
+	  }
+	  else if (in_range_p (tmp, 0, 63, 3))
+	    {
+	      notethat ("LDSTii: dpregs = [ pregs + uimm7m4 ]\n");
+	      $$ = LDSTII (&$4, &$1, tmp, 0, ispreg ? 3 : 0);
+	    }
+	  else if ($4.regno == REG_FP && in_range_p (tmp, -128, 0, 3))
+	    {
+	      notethat ("LDSTiiFP: dpregs = [ FP - uimm7m4 ]\n");
+	      tmp = unary (Expr_Op_Type_NEG, tmp);
+	      $$ = LDSTIIFP (tmp, &$1, 0);
+	    }
+	  else if (in_range_p (tmp, -131072, 131071, 3))
+	    {
+	      notethat ("LDSTidxI: dpregs = [ pregs + imm18m4 ]\n");
+	      $$ = LDSTIDXI (&$4, &$1, 0, 0, ispreg ? 1: 0, tmp);
+	      
+	    }
+	  else
+	    return yyerror ("Displacement out of range for load");
+	}
+
+	| REG ASSIGN LBRACK REG post_op RBRACK
+	{
+	  if (IS_DREG ($1) && IS_IREG ($4))
+	    {
+	      notethat ("dspLDST: dregs = [ iregs <post_op> ]\n");
+	      $$ = DSPLDST (&$4, 0, &$1, $5.x0, 0);
+	    }
+	  else if (IS_DREG ($1) && IS_PREG ($4))
+	    {
+	      notethat ("LDST: dregs = [ pregs <post_op> ]\n");
+	      $$ = LDST (&$4, &$1, $5.x0, 0, 0, 0);
+	    }
+	  else if (IS_PREG ($1) && IS_PREG ($4))
+	    {
+	      if (REG_SAME ($1, $4) && $5.x0 != 2)
+		return yyerror ("Pregs can't be same");
+
+	      notethat ("LDST: pregs = [ pregs <post_op> ]\n");
+	      $$ = LDST (&$4, &$1, $5.x0, 0, 1, 0);
+	    }
+	  else if ($4.regno == REG_SP && IS_ALLREG ($1) && $5.x0 == 0)
+	    {
+	      notethat ("PushPopReg: allregs = [ SP ++ ]\n");
+	      $$ = PUSHPOPREG (&$1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register or value");
+	}
+
+
+
+/* Expression Assignment.  */
+
+	| expr ASSIGN expr
+	{
+	  bfin_equals ($1);
+	  $$ = 0;
+	}
+
+
+/*  PushPopMultiple.  */
+	| reg_with_predec ASSIGN LPAREN REG COLON expr COMMA REG COLON expr RPAREN
+	{
+	  if ($1.regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+	  if ($4.regno == REG_R7
+	      && IN_RANGE ($6, 0, 7)
+	      && $8.regno == REG_P5
+	      && IN_RANGE ($10, 0, 5))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim , P5 : reglim )\n");
+	      $$ = PUSHPOPMULTIPLE (imm5 ($6), imm5 ($10), 1, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopMultiple");
+	}
+
+	| reg_with_predec ASSIGN LPAREN REG COLON expr RPAREN
+	{
+	  if ($1.regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if ($4.regno == REG_R7 && IN_RANGE ($6, 0, 7))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (R7 : reglim )\n");
+	      $$ = PUSHPOPMULTIPLE (imm5 ($6), 0, 1, 0, 1);
+	    }
+	  else if ($4.regno == REG_P5 && IN_RANGE ($6, 0, 6))
+	    {
+	      notethat ("PushPopMultiple: [ -- SP ] = (P5 : reglim )\n");
+	      $$ = PUSHPOPMULTIPLE (0, imm5 ($6), 0, 1, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopMultiple");
+	}
+
+	| LPAREN REG COLON expr COMMA REG COLON expr RPAREN ASSIGN reg_with_postinc
+	{
+	  if ($11.regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+	  if ($2.regno == REG_R7 && (IN_RANGE ($4, 0, 7))
+	      && $6.regno == REG_P5 && (IN_RANGE ($8, 0, 6)))
+	    {
+	      notethat ("PushPopMultiple: (R7 : reglim , P5 : reglim ) = [ SP ++ ]\n");
+	      $$ = PUSHPOPMULTIPLE (imm5 ($4), imm5 ($8), 1, 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register range for PushPopMultiple");
+	}
+
+	| LPAREN REG COLON expr RPAREN ASSIGN reg_with_postinc
+	{
+	  if ($7.regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if ($2.regno == REG_R7 && IN_RANGE ($4, 0, 7))
+	    {
+	      notethat ("PushPopMultiple: (R7 : reglim ) = [ SP ++ ]\n");
+	      $$ = PUSHPOPMULTIPLE (imm5 ($4), 0, 1, 0, 0);
+	    }
+	  else if ($2.regno == REG_P5 && IN_RANGE ($4, 0, 6))
+	    {
+	      notethat ("PushPopMultiple: (P5 : reglim ) = [ SP ++ ]\n");
+	      $$ = PUSHPOPMULTIPLE (0, imm5 ($4), 0, 1, 0);
+	    }
+	  else
+	    return yyerror ("Bad register range for PushPopMultiple");
+	}
+
+	| reg_with_predec ASSIGN REG
+	{
+	  if ($1.regno != REG_SP)
+	    yyerror ("Stack Pointer expected");
+
+	  if (IS_ALLREG ($3))
+	    {
+	      notethat ("PushPopReg: [ -- SP ] = allregs\n");
+	      $$ = PUSHPOPREG (&$3, 1);
+	    }
+	  else
+	    return yyerror ("Bad register for PushPopReg");
+	}
+
+/* Linkage.  */
+
+	| LINK expr
+	{
+	  if (IS_URANGE (16, $2, 0, 4))
+	    $$ = LINKAGE (0, uimm16s4 ($2));
+	  else
+	    return yyerror ("Bad constant for LINK");
+	}
+		
+	| UNLINK
+	{
+		notethat ("linkage: UNLINK\n");
+		$$ = LINKAGE (1, 0);
+	}
+
+
+/* LSETUP.  */
+
+	| LSETUP LPAREN expr COMMA expr RPAREN REG
+	{
+	  if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5) && IS_CREG ($7))
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters\n");
+	      $$ = LOOPSETUP ($3, &$7, 0, $5, 0);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	  
+	}
+	| LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG
+	{
+	  if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
+	      && IS_PREG ($9) && IS_CREG ($7))
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs\n");
+	      $$ = LOOPSETUP ($3, &$7, 1, $5, &$9);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	}
+
+	| LSETUP LPAREN expr COMMA expr RPAREN REG ASSIGN REG GREATER_GREATER expr
+	{
+	  if (IS_PCREL4 ($3) && IS_LPPCREL10 ($5)
+	      && IS_PREG ($9) && IS_CREG ($7) 
+	      && EXPR_VALUE ($11) == 1)
+	    {
+	      notethat ("LoopSetup: LSETUP (pcrel4 , lppcrel10 ) counters = pregs >> 1\n");
+	      $$ = LOOPSETUP ($3, &$7, 3, $5, &$9);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LSETUP");
+	}
+
+/* LOOP.  */
+	| LOOP expr REG
+	{
+	  if (!IS_RELOC ($2))
+	    return yyerror ("Invalid expression in loop statement");
+	  if (!IS_CREG ($3))
+            return yyerror ("Invalid loop counter register");
+	$$ = bfin_gen_loop ($2, &$3, 0, 0);
+	}
+	| LOOP expr REG ASSIGN REG
+	{
+	  if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3))
+	    {
+	      notethat ("Loop: LOOP expr counters = pregs\n");
+	      $$ = bfin_gen_loop ($2, &$3, 1, &$5);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LOOP");
+	}
+	| LOOP expr REG ASSIGN REG GREATER_GREATER expr
+	{
+	  if (IS_RELOC ($2) && IS_PREG ($5) && IS_CREG ($3) && EXPR_VALUE ($7) == 1)
+	    {
+	      notethat ("Loop: LOOP expr counters = pregs >> 1\n");
+	      $$ = bfin_gen_loop ($2, &$3, 3, &$5);
+	    }
+	  else
+	    return yyerror ("Bad register or values for LOOP");
+	}
+/* pseudoDEBUG.  */
+
+	| DBG
+	{
+	  notethat ("pseudoDEBUG: DBG\n");
+	  $$ = bfin_gen_pseudodbg (3, 7, 0);
+	}
+	| DBG REG_A
+	{
+	  notethat ("pseudoDEBUG: DBG REG_A\n");
+	  $$ = bfin_gen_pseudodbg (3, IS_A1 ($2), 0);
+	}
+	| DBG REG
+	{
+	  notethat ("pseudoDEBUG: DBG allregs\n");
+	  $$ = bfin_gen_pseudodbg (0, $2.regno & CODE_MASK, $2.regno & CLASS_MASK);
+	}
+
+	| DBGCMPLX LPAREN REG RPAREN
+	{
+	  if (!IS_DREG ($3))
+	    return yyerror ("Dregs expected");
+	  notethat ("pseudoDEBUG: DBGCMPLX (dregs )\n");
+	  $$ = bfin_gen_pseudodbg (3, 6, $3.regno & CODE_MASK);
+	}
+	
+	| DBGHALT
+	{
+	  notethat ("psedoDEBUG: DBGHALT\n");
+	  $$ = bfin_gen_pseudodbg (3, 5, 0);
+	}
+
+	| DBGA LPAREN HALF_REG COMMA expr RPAREN
+	{
+	  notethat ("pseudodbg_assert: DBGA (dregs_lo , uimm16 )\n");
+	  $$ = bfin_gen_pseudodbg_assert (IS_H ($3), &$3, uimm16 ($5));
+	}
+		
+	| DBGAH LPAREN REG COMMA expr RPAREN
+	{
+	  notethat ("pseudodbg_assert: DBGAH (dregs , uimm16 )\n");
+	  $$ = bfin_gen_pseudodbg_assert (3, &$3, uimm16 ($5));
+	}
+
+	| DBGAL LPAREN REG COMMA expr RPAREN
+	{
+	  notethat ("psedodbg_assert: DBGAL (dregs , uimm16 )\n");
+	  $$ = bfin_gen_pseudodbg_assert (2, &$3, uimm16 ($5));
+	}
+
+
+;
+
+/*  AUX RULES.  */
+
+/*  Register rules.  */
+
+REG_A:	REG_A_DOUBLE_ZERO
+	{
+	$$ = $1;
+	}
+	| REG_A_DOUBLE_ONE
+	{
+	$$ = $1;
+	}
+	;
+
+
+/*  Modifiers. */
+
+opt_mode:
+	{
+	$$.MM = 0;
+	$$.mod = 0;
+	}
+	| LPAREN M COMMA MMOD RPAREN
+	{
+	$$.MM = 1;
+	$$.mod = $4;
+	}
+	| LPAREN MMOD COMMA M RPAREN
+	{
+	$$.MM = 1;
+	$$.mod = $2;
+	}
+	| LPAREN MMOD RPAREN
+	{
+	$$.MM = 0;
+	$$.mod = $2;
+	}
+	| LPAREN M RPAREN
+	{
+	$$.MM = 1;
+	$$.mod = 0;
+	}
+	;
+
+asr_asl: LPAREN ASL RPAREN
+	{
+	$$.r0 = 1;
+	}
+	| LPAREN ASR RPAREN
+	{
+	$$.r0 = 0;
+	}
+	;
+
+sco:
+	{
+	$$.s0 = 0;
+	$$.x0 = 0;
+	}
+	| S
+	{
+	$$.s0 = 1;
+	$$.x0 = 0;
+	}
+	| CO
+	{
+	$$.s0 = 0;
+	$$.x0 = 1;
+	}
+	| SCO
+	{	
+	$$.s0 = 1;
+	$$.x0 = 1;
+	}
+	;
+
+asr_asl_0:
+	ASL
+	{
+	$$.r0 = 1;
+	}
+	| ASR
+	{
+	$$.r0 = 0;
+	}
+	;
+
+amod0:
+	{
+	$$.s0 = 0;
+	$$.x0 = 0;
+	}
+	| LPAREN sco RPAREN
+	{
+	$$.s0 = $2.s0;
+	$$.x0 = $2.x0;
+	}
+	;
+
+amod1:
+	{
+	$$.s0 = 0;
+	$$.x0 = 0;
+	$$.aop = 0;
+	}
+	| LPAREN NS RPAREN
+	{
+	$$.s0 = 0;
+	$$.x0 = 0;
+	$$.aop = 1;
+	}
+	| LPAREN S RPAREN
+	{
+	$$.s0 = 1;
+	$$.x0 = 0;
+	$$.aop = 1;
+	}
+	;
+
+amod2:
+	{
+	$$.r0 = 0;
+	$$.s0 = 0;
+	$$.x0 = 0;
+	}
+	| LPAREN asr_asl_0 RPAREN
+	{
+	$$.r0 = 2 + $2.r0;
+	$$.s0 = 0;
+	$$.x0 = 0;
+	}
+	| LPAREN sco RPAREN
+	{
+	$$.r0 = 0;
+	$$.s0 = $2.s0;
+	$$.x0 = $2.x0;
+	}
+	| LPAREN asr_asl_0 COMMA sco RPAREN
+	{
+	$$.r0 = 2 + $2.r0;
+	$$.s0 = $4.s0;
+	$$.x0 = $4.x0;
+	}
+	| LPAREN sco COMMA asr_asl_0 RPAREN
+	{
+	$$.r0 = 2 + $4.r0;
+	$$.s0 = $2.s0;
+	$$.x0 = $2.x0;
+	}
+	;
+
+xpmod:
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN Z RPAREN
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN X RPAREN
+	{
+	$$.r0 = 1;
+	}
+	;
+
+xpmod1:
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN X RPAREN
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN Z RPAREN
+	{
+	$$.r0 = 1;
+	}
+	;
+
+vsmod:
+	{
+	$$.r0 = 0;
+	$$.s0 = 0;
+	$$.aop = 0;
+	}
+	| LPAREN NS RPAREN
+	{
+	$$.r0 = 0;
+	$$.s0 = 0;
+	$$.aop = 3;
+	}
+	| LPAREN S RPAREN
+	{
+	$$.r0 = 0;
+	$$.s0 = 1;
+	$$.aop = 3;
+	}
+	| LPAREN V RPAREN
+	{
+	$$.r0 = 1;
+	$$.s0 = 0;
+	$$.aop = 3;
+	}
+	| LPAREN V COMMA S RPAREN
+	{
+	$$.r0 = 1;
+	$$.s0 = 1;
+	}
+	| LPAREN S COMMA V RPAREN
+	{
+	$$.r0 = 1;
+	$$.s0 = 1;
+	}
+	;
+
+vmod:
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN V RPAREN
+	{
+	$$.r0 = 1;
+	}
+	;
+
+smod:
+	{
+	$$.s0 = 0;
+	}
+	| LPAREN S RPAREN
+	{
+	$$.s0 = 1;
+	}
+	;
+
+searchmod:
+	  GE
+	{
+	$$.r0 = 1;
+	}
+	| GT
+	{
+	$$.r0 = 0;
+	}
+	| LE
+	{
+	$$.r0 = 3;
+	}
+	| LT
+	{
+	$$.r0 = 2;
+	}
+	;
+
+aligndir:
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN R RPAREN
+	{
+	$$.r0 = 1;
+	}
+	;
+
+byteop_mod:
+	LPAREN R RPAREN
+	{
+	$$.r0 = 0;
+	$$.s0 = 1;
+	}
+	| LPAREN MMOD RPAREN
+	{
+	if ($2 != M_T)
+	  return yyerror ("Bad modifier");
+	$$.r0 = 1;
+	$$.s0 = 0;
+	}
+	| LPAREN MMOD COMMA R RPAREN
+	{
+	if ($2 != M_T)
+	  return yyerror ("Bad modifier");
+	$$.r0 = 1;
+	$$.s0 = 1;
+	}
+	| LPAREN R COMMA MMOD RPAREN
+	{
+	if ($4 != M_T)
+	  return yyerror ("Bad modifier");
+	$$.r0 = 1;
+	$$.s0 = 1;
+	}
+	;
+
+
+
+c_align:
+	ALIGN8
+	{
+	$$.r0 = 0;
+	}
+	| ALIGN16
+	{
+	$$.r0 = 1;
+	}
+	| ALIGN24
+	{
+	$$.r0 = 2;
+	}
+	;
+
+w32_or_nothing:
+	{
+	$$.r0 = 0;
+	}
+	| LPAREN MMOD RPAREN
+	{
+	  if ($2 == M_W32)
+	    $$.r0 = 1;
+	  else
+	    return yyerror ("Only (W32) allowed");
+	}
+	;
+
+iu_or_nothing:
+	{
+	$$.r0 = 1;
+	}
+	| LPAREN MMOD RPAREN
+	{
+	  if ($2 == M_IU)
+	    $$.r0 = 3;
+	  else
+	    return yyerror ("(IU) expected");
+	}
+	;
+
+reg_with_predec: LBRACK _MINUS_MINUS REG RBRACK
+	{
+	$$ = $3;
+	}
+	;
+
+reg_with_postinc: LBRACK REG _PLUS_PLUS RBRACK
+	{
+	$$ = $2;
+	}
+	;
+
+/* Operators.  */
+
+min_max:
+	MIN
+	{
+	$$.r0 = 1;
+	}
+	| MAX
+	{
+	$$.r0 = 0;
+	}
+	;
+ 
+op_bar_op:
+	_PLUS_BAR_PLUS
+	{
+	$$.r0 = 0;
+	}
+	| _PLUS_BAR_MINUS
+	{
+	$$.r0 = 1;
+	}
+	| _MINUS_BAR_PLUS
+	{
+	$$.r0 = 2;
+	}
+	| _MINUS_BAR_MINUS
+	{
+	$$.r0 = 3;
+	}
+	;
+
+plus_minus:
+	PLUS
+	{
+	$$.r0 = 0;
+	}
+	| MINUS
+	{
+	$$.r0 = 1;
+	}
+	;
+
+rnd_op:
+	LPAREN RNDH RPAREN
+	{
+	  $$.r0 = 1;	/* HL.  */
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 0;	/* aop.  */
+	}
+
+	| LPAREN TH RPAREN
+	{
+	  $$.r0 = 1;	/* HL.  */
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 1;	/* aop.  */
+	}
+
+	| LPAREN RNDL RPAREN
+	{
+	  $$.r0 = 0;	/* HL.  */
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 0;	/* aop.  */
+	}
+
+	| LPAREN TL RPAREN
+	{
+	  $$.r0 = 0;	/* HL.  */
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 1;
+	}
+
+	| LPAREN RNDH COMMA R RPAREN
+	{
+	  $$.r0 = 1;	/* HL.  */
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 0;	/* aop.  */
+	}
+	| LPAREN TH COMMA R RPAREN
+	{
+	  $$.r0 = 1;	/* HL.  */
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 1;	/* aop.  */
+	}
+	| LPAREN RNDL COMMA R RPAREN
+	{
+	  $$.r0 = 0;	/* HL.  */
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 0;	/* aop.  */
+	}
+
+	| LPAREN TL COMMA R RPAREN
+	{
+	  $$.r0 = 0;	/* HL.  */
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 0;	/* x.  */
+	  $$.aop = 1;	/* aop.  */
+	}
+	;
+
+b3_op:
+	LPAREN LO RPAREN
+	{
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 0;	/* HL.  */
+	}
+	| LPAREN HI RPAREN
+	{
+	  $$.s0 = 0;	/* s.  */
+	  $$.x0 = 1;	/* HL.  */
+	}
+	| LPAREN LO COMMA R RPAREN
+	{
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 0;	/* HL.  */
+	}
+	| LPAREN HI COMMA R RPAREN
+	{
+	  $$.s0 = 1;	/* s.  */
+	  $$.x0 = 1;	/* HL.  */
+	}
+	;
+
+post_op:
+	{
+	$$.x0 = 2;
+	} 
+	| _PLUS_PLUS 
+	{
+	$$.x0 = 0;
+	}
+	| _MINUS_MINUS
+	{
+	$$.x0 = 1;
+	}
+	;
+
+/* Assignments, Macfuncs.  */
+
+a_assign:
+	REG_A ASSIGN
+	{
+	$$ = $1;
+	}
+	;
+
+a_minusassign:
+	REG_A _MINUS_ASSIGN
+	{
+	$$ = $1;
+	}
+	;
+
+a_plusassign:
+	REG_A _PLUS_ASSIGN
+	{
+	$$ = $1;
+	}
+	;
+
+assign_macfunc:
+	REG ASSIGN REG_A
+	{
+	  $$.w = 1;
+          $$.P = 1;
+          $$.n = IS_A1 ($3);
+	  $$.op = 3;
+          $$.dst = $1;
+	  $$.s0.regno = 0;
+          $$.s1.regno = 0;
+
+	  if (IS_A1 ($3) && IS_EVEN ($1))
+	    return yyerror ("Cannot move A1 to even register");
+	  else if (!IS_A1 ($3) && !IS_EVEN ($1))
+	    return yyerror ("Cannot move A0 to odd register");
+	}
+	| a_macfunc
+	{
+	  $$ = $1;
+	  $$.w = 0; $$.P = 0;
+	  $$.dst.regno = 0;
+	}
+	| REG ASSIGN LPAREN a_macfunc RPAREN
+	{
+	  $$ = $4;
+	  $$.w = 1;
+          $$.P = 1;
+          $$.dst = $1;
+	}
+
+	| HALF_REG ASSIGN LPAREN a_macfunc RPAREN
+	{
+	  $$ = $4;
+	  $$.w = 1;
+	  $$.P = 0;
+          $$.dst = $1;
+	}
+
+	| HALF_REG ASSIGN REG_A
+	{
+	  $$.w = 1;
+	  $$.P = 0;
+	  $$.n = IS_A1 ($3);
+	  $$.op = 3;
+          $$.dst = $1;
+	  $$.s0.regno = 0;
+          $$.s1.regno = 0;
+
+	  if (IS_A1 ($3) && !IS_H ($1))
+	    return yyerror ("Cannot move A1 to low half of register");
+	  else if (!IS_A1 ($3) && IS_H ($1))
+	    return yyerror ("Cannot move A0 to high half of register");
+	}
+	;
+
+a_macfunc:
+	a_assign multiply_halfregs
+	{
+	  $$.n = IS_A1 ($1);
+	  $$.op = 0;
+	  $$.s0 = $2.s0;
+	  $$.s1 = $2.s1;
+	}
+	| a_plusassign multiply_halfregs
+	{
+	  $$.n = IS_A1 ($1);
+	  $$.op = 1;
+	  $$.s0 = $2.s0;
+	  $$.s1 = $2.s1;
+	}
+	| a_minusassign multiply_halfregs
+	{
+	  $$.n = IS_A1 ($1);
+	  $$.op = 2;
+	  $$.s0 = $2.s0;
+	  $$.s1 = $2.s1;
+	}
+	;
+
+multiply_halfregs:
+	HALF_REG STAR HALF_REG
+	{
+	  if (IS_DREG ($1) && IS_DREG ($3))
+	    {
+	      $$.s0 = $1;
+              $$.s1 = $3;
+	    }
+	  else
+	    return yyerror ("Dregs expected");
+	}
+	;
+
+cc_op:
+	ASSIGN
+	{
+	$$.r0 = 0;
+	}
+	| _BAR_ASSIGN
+	{
+	$$.r0 = 1;
+	}
+	| _AMPERSAND_ASSIGN
+	{
+	$$.r0 = 2;
+	}
+	| _CARET_ASSIGN
+	{
+	$$.r0 = 3;
+	}
+	;
+
+ccstat:
+	CCREG cc_op STATUS_REG
+	{
+	$$.r0 = $3.regno;
+	$$.x0 = $2.r0;
+	$$.s0 = 0;
+	}
+	| CCREG cc_op V
+	{
+	$$.r0 = 0x18;
+	$$.x0 = $2.r0;
+	$$.s0 = 0;
+	}
+	| STATUS_REG cc_op CCREG
+	{
+	$$.r0 = $1.regno;
+	$$.x0 = $2.r0;
+	$$.s0 = 1;
+	}
+	| V cc_op CCREG
+	{
+	$$.r0 = 0x18;
+	$$.x0 = $2.r0;
+	$$.s0 = 1;
+	}
+	;
+
+/* Expressions and Symbols.  */
+
+symbol: SYMBOL
+	{
+	Expr_Node_Value val;
+	val.s_value = S_GET_NAME($1);
+	$$ = Expr_Node_Create (Expr_Node_Reloc, val, NULL, NULL);
+	}
+	;
+
+any_gotrel:
+	GOT
+	{ $$ = BFD_RELOC_BFIN_GOT; }
+	| GOT17M4
+	{ $$ = BFD_RELOC_BFIN_GOT17M4; }
+	| FUNCDESC_GOT17M4
+	{ $$ = BFD_RELOC_BFIN_FUNCDESC_GOT17M4; }
+	;
+
+got:	symbol AT any_gotrel
+	{
+	Expr_Node_Value val;
+	val.i_value = $3;
+	$$ = Expr_Node_Create (Expr_Node_GOT_Reloc, val, $1, NULL);
+	}
+	;
+
+got_or_expr:	got
+	{
+	$$ = $1;
+	}
+	| expr
+	{
+	$$ = $1;
+	}
+	;
+
+pltpc :
+	symbol AT PLTPC
+	{
+	$$ = $1;
+	}
+	;
+
+eterm: NUMBER
+	{
+	Expr_Node_Value val;
+	val.i_value = $1;
+	$$ = Expr_Node_Create (Expr_Node_Constant, val, NULL, NULL);
+	}
+	| symbol
+	{
+	$$ = $1;
+	}
+	| LPAREN expr_1 RPAREN
+	{
+	$$ = $2;
+	}
+	| TILDA expr_1
+	{
+	$$ = unary (Expr_Op_Type_COMP, $2);
+	}
+	| MINUS expr_1 %prec TILDA
+	{
+	$$ = unary (Expr_Op_Type_NEG, $2);
+	}
+	;
+
+expr: expr_1
+	{
+	$$ = $1;
+	}
+	;
+
+expr_1: expr_1 STAR expr_1
+	{
+	$$ = binary (Expr_Op_Type_Mult, $1, $3);
+	}
+	| expr_1 SLASH expr_1
+	{
+	$$ = binary (Expr_Op_Type_Div, $1, $3);
+	}
+	| expr_1 PERCENT expr_1
+	{
+	$$ = binary (Expr_Op_Type_Mod, $1, $3);
+	}
+	| expr_1 PLUS expr_1
+	{
+	$$ = binary (Expr_Op_Type_Add, $1, $3);
+	}
+	| expr_1 MINUS expr_1
+	{
+	$$ = binary (Expr_Op_Type_Sub, $1, $3);
+	}
+	| expr_1 LESS_LESS expr_1
+	{
+	$$ = binary (Expr_Op_Type_Lshift, $1, $3);	
+	}
+	| expr_1 GREATER_GREATER expr_1
+	{
+	$$ = binary (Expr_Op_Type_Rshift, $1, $3);
+	}
+	| expr_1 AMPERSAND expr_1
+	{
+	$$ = binary (Expr_Op_Type_BAND, $1, $3);
+	}
+	| expr_1 CARET expr_1
+	{
+	$$ = binary (Expr_Op_Type_LOR, $1, $3);
+	}
+	| expr_1 BAR expr_1
+	{
+	$$ = binary (Expr_Op_Type_BOR, $1, $3);
+	}
+	| eterm	
+	{
+	$$ = $1;
+	}
+	;
+
+
+%%
+
+EXPR_T
+mkexpr (int x, SYMBOL_T s)
+{
+  EXPR_T e = (EXPR_T) ALLOCATE (sizeof (struct expression_cell));
+  e->value = x;
+  EXPR_SYMBOL(e) = s;
+  return e;
+}
+
+static int
+value_match (Expr_Node *expr, int sz, int sign, int mul, int issigned)
+{
+  long umax = (1L << sz) - 1;
+  long min = -1L << (sz - 1);
+  long max = (1L << (sz - 1)) - 1;
+	
+  long v = EXPR_VALUE (expr);
+
+  if ((v % mul) != 0)
+    {
+      error ("%s:%d: Value Error -- Must align to %d\n", __FILE__, __LINE__, mul); 
+      return 0;
+    }
+
+  v /= mul;
+
+  if (sign)
+    v = -v;
+
+  if (issigned)
+    {
+      if (v >= min && v <= max) return 1;
+
+#ifdef DEBUG
+      fprintf(stderr, "signed value %lx out of range\n", v * mul);
+#endif
+      return 0;
+    }
+  if (v <= umax && v >= 0) 
+    return 1;
+#ifdef DEBUG
+  fprintf(stderr, "unsigned value %lx out of range\n", v * mul);
+#endif
+  return 0;
+}
+
+/* Return the expression structure that allows symbol operations.
+   If the left and right children are constants, do the operation.  */
+static Expr_Node *
+binary (Expr_Op_Type op, Expr_Node *x, Expr_Node *y)
+{
+  if (x->type == Expr_Node_Constant && y->type == Expr_Node_Constant)
+    {
+      switch (op)
+	{
+        case Expr_Op_Type_Add: 
+	  x->value.i_value += y->value.i_value;
+	  break;
+        case Expr_Op_Type_Sub: 
+	  x->value.i_value -= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Mult: 
+	  x->value.i_value *= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Div: 
+	  if (y->value.i_value == 0)
+	    error ("Illegal Expression:  Division by zero.");
+	  else
+	    x->value.i_value /= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Mod: 
+	  x->value.i_value %= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Lshift: 
+	  x->value.i_value <<= y->value.i_value;
+	  break;
+        case Expr_Op_Type_Rshift: 
+	  x->value.i_value >>= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BAND: 
+	  x->value.i_value &= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BOR: 
+	  x->value.i_value |= y->value.i_value;
+	  break;
+        case Expr_Op_Type_BXOR: 
+	  x->value.i_value ^= y->value.i_value;
+	  break;
+        case Expr_Op_Type_LAND: 
+	  x->value.i_value = x->value.i_value && y->value.i_value;
+	  break;
+        case Expr_Op_Type_LOR: 
+	  x->value.i_value = x->value.i_value || y->value.i_value;
+	  break;
+
+	default:
+	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
+	}
+      return x;
+    }
+  else
+    {
+    /* Create a new expression structure.  */
+    Expr_Node_Value val;
+    val.op_value = op;
+    return Expr_Node_Create (Expr_Node_Binop, val, x, y);
+  }
+}
+
+static Expr_Node *
+unary (Expr_Op_Type op, Expr_Node *x) 
+{
+  if (x->type == Expr_Node_Constant)
+    {
+      switch (op)
+	{
+	case Expr_Op_Type_NEG: 
+	  x->value.i_value = -x->value.i_value;
+	  break;
+	case Expr_Op_Type_COMP:
+	  x->value.i_value = ~x->value.i_value;
+	  break;
+	default:
+	  error ("%s:%d: Internal compiler error\n", __FILE__, __LINE__); 
+	}
+      return x;
+    }
+  else
+    {
+      /* Create a new expression structure.  */
+      Expr_Node_Value val;
+      val.op_value = op;
+      return Expr_Node_Create (Expr_Node_Unop, val, x, NULL);
+    }
+}
+
+int debug_codeselection = 0;
+static void
+notethat (char *format, ...)
+{
+  va_list ap;
+  va_start (ap, format);
+  if (debug_codeselection)
+    {
+      vfprintf (errorf, format, ap);
+    }
+  va_end (ap);
+}
+
+#ifdef TEST
+main (int argc, char **argv)
+{
+  yyparse();
+}
+#endif
+
diff --git a/gas/config/itbl-mips.h b/gas/config/itbl-mips.h
index 8ecb9ecc4ecd..cfa072f298a0 100644
--- a/gas/config/itbl-mips.h
+++ b/gas/config/itbl-mips.h
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Defines for Mips itbl cop support */
 
diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h
index c82e69fc65a0..e7af8536a805 100644
--- a/gas/config/m68k-parse.h
+++ b/gas/config/m68k-parse.h
@@ -1,6 +1,6 @@
 /* m68k-parse.h -- header file for m68k assembler
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
-   2003 Free Software Foundation, Inc.
+   2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef M68K_PARSE_H
 #define M68K_PARSE_H
@@ -84,7 +84,12 @@ enum m68k_register
   ZPC,				/* Hack for Program space, but 0 addressing */
   SR,				/* Status Reg */
   CCR,				/* Condition code Reg */
-  ACC,				/* Accumulator Reg */
+  ACC,				/* Accumulator Reg0 (EMAC or ACC on MAC).  */
+  ACC1,				/* Accumulator Reg 1 (EMAC).  */
+  ACC2,				/* Accumulator Reg 2 (EMAC).  */
+  ACC3,				/* Accumulator Reg 3 (EMAC).  */
+  ACCEXT01,			/* Accumulator extension 0&1 (EMAC).  */
+  ACCEXT23,			/* Accumulator extension 2&3 (EMAC).  */
   MACSR,			/* MAC Status Reg */
   MASK,				/* Modulus Reg */
 
@@ -119,6 +124,7 @@ enum m68k_register
   MBAR0, MBAR1,			/* mcfv4e added these.  */
   ACR0, ACR1, ACR2, ACR3,       /* mcf5200 added these.  */
   FLASHBAR, RAMBAR,  		/* mcf528x added these.  */
+  MBAR2,  		        /* mcf5249 added this.  */
   MBAR,
 #define last_movec_reg MBAR
   /* End of movec ordering constraints.  */
@@ -295,6 +301,8 @@ enum m68k_operand_type
   BASE,
   POST,
   PRE,
+  LSH,  /* MAC/EMAC scalefactor '<<'.  */
+  RSH,  /* MAC/EMAC scalefactor '>>'.  */
   REGLST
 };
 
@@ -322,13 +330,16 @@ struct m68k_op
 
   /* The outer displacement.  */
   struct m68k_exp odisp;
+
+  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
+  int trailing_ampersand;
 };
 
 #endif /* ! defined (M68K_PARSE_H) */
 
 /* The parsing function.  */
 
-extern int m68k_ip_op PARAMS ((char *, struct m68k_op *));
+extern int m68k_ip_op (char *, struct m68k_op *);
 
 /* Whether register prefixes are optional.  */
 extern int flag_reg_prefix_optional;
diff --git a/gas/config/m68k-parse.y b/gas/config/m68k-parse.y
index 813bfaad2c11..2140dda80161 100644
--- a/gas/config/m68k-parse.y
+++ b/gas/config/m68k-parse.y
@@ -1,5 +1,6 @@
 /* m68k.y -- bison grammar for m68k operand parsing
-   Copyright 1995, 1996, 1997, 1998, 2001 Free Software Foundation, Inc.
+   Copyright 1995, 1996, 1997, 1998, 2001, 2003, 2004, 2005
+   Free Software Foundation, Inc.
    Written by Ken Raeburn and Ian Lance Taylor, Cygnus Support
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This file holds a bison grammar to parse m68k operands.  The m68k
    has a complicated operand syntax, and gas supports two main
@@ -35,7 +36,7 @@
    etc), as well as gratuitously global symbol names If other parser
    generators (bison, byacc, etc) produce additional global names that
    conflict at link time, then those parser generators need to be
-   fixed instead of adding those names to this list. */
+   fixed instead of adding those names to this list.  */
 
 #define	yymaxdepth m68k_maxdepth
 #define	yyparse	m68k_parse
@@ -82,9 +83,9 @@
 
 /* Internal functions.  */
 
-static enum m68k_register m68k_reg_parse PARAMS ((char **));
-static int yylex PARAMS ((void));
-static void yyerror PARAMS ((const char *));
+static enum m68k_register m68k_reg_parse (char **);
+static int yylex (void);
+static void yyerror (const char *);
 
 /* The parser sets fields pointed to by this global variable.  */
 static struct m68k_op *op;
@@ -98,6 +99,7 @@ static struct m68k_op *op;
   struct m68k_exp exp;
   unsigned long mask;
   int onereg;
+  int trailing_ampersand;
 }
 
 %token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
@@ -109,6 +111,7 @@ static struct m68k_op *op;
 %type <exp> optcexpr optexprc
 %type <mask> reglist ireglist reglistpair
 %type <onereg> reglistreg
+%type <trailing_ampersand> optional_ampersand
 
 %%
 
@@ -116,14 +119,38 @@ static struct m68k_op *op;
 
 operand:
 	  generic_operand
-	| motorola_operand
-	| mit_operand
+	| motorola_operand optional_ampersand
+		{
+		  op->trailing_ampersand = $2;
+		}
+	| mit_operand optional_ampersand
+		{
+		  op->trailing_ampersand = $2;
+		}
+	;
+
+/* A trailing ampersand(for MAC/EMAC mask addressing).  */
+optional_ampersand:
+	/* empty */
+		{ $$ = 0; }
+	| '&'
+		{ $$ = 1; }
 	;
 
 /* A generic operand.  */
 
 generic_operand:
-	  DR
+	  '<' '<'
+		{
+		  op->mode = LSH;
+		}
+
+	| '>' '>'
+		{
+		  op->mode = RSH;
+		}
+
+	| DR
 		{
 		  op->mode = DREG;
 		  op->reg = $1;
@@ -757,19 +784,21 @@ yylex ()
     case '/':
     case '[':
     case ']':
+    case '<':
+    case '>':
       return *str++;
     case '+':
       /* It so happens that a '+' can only appear at the end of an
-         operand.  If it appears anywhere else, it must be a unary
-         plus on an expression.  */
-      if (str[1] == '\0')
+	 operand, or if it is trailed by an '&'(see mac load insn).
+	 If it appears anywhere else, it must be a unary.  */
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       break;
     case '-':
       /* A '-' can only appear in -(ar), rn-rn, or ar@-.  If it
          appears anywhere else, it must be a unary minus on an
-         expression.  */
-      if (str[1] == '\0')
+         expression, unless it it trailed by a '&'(see mac load insn).  */
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       s = str + 1;
       if (*s == '(')
diff --git a/gas/config/m88k-opcode.h b/gas/config/m88k-opcode.h
deleted file mode 100644
index 8055b5e430ec..000000000000
--- a/gas/config/m88k-opcode.h
+++ /dev/null
@@ -1,559 +0,0 @@
-/* m88k-opcode.h -- Instruction information for the Motorola 88000
-   Contributed by Devon Bowen of Buffalo University
-   and Torbjorn Granlund of the Swedish Institute of Computer Science.
-   Copyright 1989, 1990, 1991, 1993, 2000 Free Software Foundation, Inc.
-
-This file is part of GAS, the GNU Assembler.
-
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 1, or (at your option)
-any later version.
-
-GAS is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#if !defined(__STDC__) && !defined(const)
-#define const
-#endif
-
-/*
-  Character codes for op_spec field below.
-  Reserved for self-matching: [ ] ,
-
-  d = GRF Destination register (21:5)
-  x = XRF register prefix.  Makes next d, 1, or 2, match an extended register.
-  1 = Source register 1 (16:5)
-  2 = Source register 2 (0:5)
-  3 = Both source registers (same value) (0:5 and 16:5)
-  I = IMM16 (0:16)
-  b = bit field spec. (0:10)
-  p = 16 bit pc displ. (0:16)
-  P = 26 bit pc displ. (0:26)
-  B = bb0/bb1 condition (21:5)
-  M = bcnd condition (21:5)
-  f = fcr (5:6)
-  c = cr (5:6)
-  V = VEC9 (0:9)
-  o = O6 field of "prot" insn (10:7)
-  ? = Give warning for this insn/operand combination
- */
-
-/* instruction descriptor structure */
-
-struct m88k_opcode
-{
-  unsigned int opcode;
-  char *name;
-  char *op_spec;
-};
-
-/* and introducing... the Motorola 88100 and 88110 instruction sets...  */
-
-/* By default, include the 88110 instructions.  */
-#define MC88110
-
-#if defined (MC88110)
-#define _MC88100(OPCODE,MNEM,OP_SPEC)
-#define _MC88110(OPCODE,MNEM,OP_SPEC) {OPCODE,MNEM,OP_SPEC},
-#else
-#define _MC88100(OPCODE,MNEM,OP_SPEC) {OPCODE,MNEM,OP_SPEC},
-#define _MC88110(OPCODE,MNEM,OP_SPEC)
-#endif
-
-#define _MC88xxx(OPCODE,MNEM,OP_SPEC) {OPCODE,MNEM,OP_SPEC},
-
-/* Equal mnemonics must be adjacent.
-   More specific operand specification must go before more general.
-   For example, "d,1,2" must go before "d,1,I" as a register for s2
-   would otherwise be considered a variable name.  */
-
-static struct m88k_opcode m88k_opcodes[] =
-{
-  /*	   Opcode	Mnemonic	Opspec */
-
-  _MC88xxx (0xf4007000, "add",		"d,1,2")
-  _MC88xxx (0x70000000, "add",		"d,1,I")
-  _MC88xxx (0xf4007200, "add.ci",	"d,1,2")
-  _MC88xxx (0xf4007300, "add.cio",	"d,1,2")
-  _MC88xxx (0xf4007100, "add.co",	"d,1,2")
-  _MC88xxx (0xf4006000, "addu",		"d,1,2")
-  _MC88xxx (0x60000000, "addu",		"d,1,I")
-  _MC88xxx (0xf4006200, "addu.ci",	"d,1,2")
-  _MC88xxx (0xf4006300, "addu.cio",	"d,1,2")
-  _MC88xxx (0xf4006100, "addu.co",	"d,1,2")
-  _MC88xxx (0xf4004000, "and",		"d,1,2")
-  _MC88xxx (0x40000000, "and",		"d,1,I")
-  _MC88xxx (0xf4004400, "and.c",	"d,1,2")
-  _MC88xxx (0x44000000, "and.u",	"d,1,I")
-  _MC88xxx (0xd0000000, "bb0",		"B,1,p")
-  _MC88xxx (0xd4000000, "bb0.n",	"B,1,p")
-  _MC88xxx (0xd8000000, "bb1",		"B,1,p")
-  _MC88xxx (0xdc000000, "bb1.n",	"B,1,p")
-  _MC88xxx (0xe8000000, "bcnd",		"M,1,p")
-  _MC88xxx (0xec000000, "bcnd.n",	"M,1,p")
-  _MC88xxx (0xc0000000, "br",		"P")
-  _MC88xxx (0xc4000000, "br.n",		"P")
-  _MC88xxx (0xc8000000, "bsr",		"P")
-  _MC88xxx (0xcc000000, "bsr.n",	"P")
-  _MC88xxx (0xf4008000, "clr",		"d,1,2")
-  _MC88xxx (0xf0008000, "clr",		"d,1,b")
-  _MC88xxx (0xf4007c00, "cmp",		"d,1,2")
-  _MC88xxx (0x7c000000, "cmp",		"d,1,I")
-  _MC88xxx (0xf4007800, "div",		"d,1,2")
-  _MC88xxx (0x78000000, "div",		"d,1,I")
-  _MC88xxx (0xf4007800, "divs",		"d,1,2")
-  _MC88xxx (0x78000000, "divs",		"d,1,I")
-  _MC88110 (0xf4006900, "divu.d",	"d,1,2")
-  _MC88xxx (0xf4006800, "divu",		"d,1,2")
-  _MC88xxx (0x68000000, "divu",		"d,1,I")
-  _MC88xxx (0xf4009000, "ext",		"d,1,2")
-  _MC88xxx (0xf0009000, "ext",		"d,1,b")
-  _MC88xxx (0xf4009800, "extu",		"d,1,2")
-  _MC88xxx (0xf0009800, "extu",		"d,1,b")
-  _MC88xxx (0x84002800, "fadd.sss",	"d,1,2")
-  _MC88110 (0x8400a800, "fadd.sss",	"xd,x1,x2")
-  _MC88xxx (0x84002880, "fadd.ssd",	"d,1,2")
-  _MC88110 (0x8400a820, "fadd.ssd",	"xd,x1,x2")
-  _MC88110 (0x8400a840, "fadd.ssx",	"xd,x1,x2")
-  _MC88xxx (0x84002a00, "fadd.sds",	"d,1,2")
-  _MC88110 (0x8400a880, "fadd.sds",	"xd,x1,x2")
-  _MC88xxx (0x84002a80, "fadd.sdd",	"d,1,2")
-  _MC88110 (0x8400a8a0, "fadd.sdd",	"xd,x1,x2")
-  _MC88110 (0x8400a8c0, "fadd.sdx",	"xd,x1,x2")
-  _MC88110 (0x8400a900, "fadd.sxs",	"xd,x1,x2")
-  _MC88110 (0x8400a920, "fadd.sxd",	"xd,x1,x2")
-  _MC88110 (0x8400a940, "fadd.sxx",	"xd,x1,x2")
-  _MC88xxx (0x84002820, "fadd.dss",	"d,1,2")
-  _MC88110 (0x8400aa00, "fadd.dss",	"xd,x1,x2")
-  _MC88xxx (0x840028a0, "fadd.dsd",	"d,1,2")
-  _MC88110 (0x8400aa20, "fadd.dsd",	"xd,x1,x2")
-  _MC88110 (0x8400aa40, "fadd.dsx",	"xd,x1,x2")
-  _MC88xxx (0x84002a20, "fadd.dds",	"d,1,2")
-  _MC88110 (0x8400aa80, "fadd.dds",	"xd,x1,x2")
-  _MC88xxx (0x84002aa0, "fadd.ddd",	"d,1,2")
-  _MC88110 (0x8400aaa0, "fadd.ddd",	"xd,x1,x2")
-  _MC88110 (0x8400aac0, "fadd.ddx",	"xd,x1,x2")
-  _MC88110 (0x8400ab00, "fadd.dxs",	"xd,x1,x2")
-  _MC88110 (0x8400ab20, "fadd.dxd",	"xd,x1,x2")
-  _MC88110 (0x8400ab40, "fadd.dxx",	"xd,x1,x2")
-  _MC88110 (0x8400ac00, "fadd.xss",	"xd,x1,x2")
-  _MC88110 (0x8400ac20, "fadd.xsd",	"xd,x1,x2")
-  _MC88110 (0x8400ac40, "fadd.xsx",	"xd,x1,x2")
-  _MC88110 (0x8400ac80, "fadd.xds",	"xd,x1,x2")
-  _MC88110 (0x8400aca0, "fadd.xdd",	"xd,x1,x2")
-  _MC88110 (0x8400acc0, "fadd.xdx",	"xd,x1,x2")
-  _MC88110 (0x8400ad00, "fadd.xxs",	"xd,x1,x2")
-  _MC88110 (0x8400ad20, "fadd.xxd",	"xd,x1,x2")
-  _MC88110 (0x8400ad40, "fadd.xxx",	"xd,x1,x2")
-  _MC88xxx (0x84003a80, "fcmp.sdd",	"d,1,2")
-  _MC88110 (0x8400ba80, "fcmp.sdd",	"d,x1,x2")
-  _MC88xxx (0x84003a00, "fcmp.sds",	"d,1,2")
-  _MC88110 (0x8400ba00, "fcmp.sds",	"d,x1,x2")
-  _MC88110 (0x8400bb00, "fcmp.sdx",	"d,x1,x2")
-  _MC88xxx (0x84003880, "fcmp.ssd",	"d,1,2")
-  _MC88110 (0x8400b880, "fcmp.ssd",	"d,x1,x2")
-  _MC88xxx (0x84003800, "fcmp.sss",	"d,1,2")
-  _MC88110 (0x8400b800, "fcmp.sss",	"d,x1,x2")
-  _MC88110 (0x8400b900, "fcmp.ssx",	"d,x1,x2")
-  _MC88110 (0x8400bc80, "fcmp.sxd",	"d,x1,x2")
-  _MC88110 (0x8400bc00, "fcmp.sxs",	"d,x1,x2")
-  _MC88110 (0x8400bd00, "fcmp.sxx",	"d,x1,x2")
-  _MC88110 (0x84003aa0, "fcmpu.sdd",	"d,1,2")
-  _MC88110 (0x8400baa0, "fcmpu.sdd",	"d,x1,x2")
-  _MC88110 (0x84003a20, "fcmpu.sds",	"d,1,2")
-  _MC88110 (0x8400ba20, "fcmpu.sds",	"d,x1,x2")
-  _MC88110 (0x8400bb20, "fcmpu.sdx",	"d,x1,x2")
-  _MC88110 (0x840038a0, "fcmpu.ssd",	"d,1,2")
-  _MC88110 (0x8400b8a0, "fcmpu.ssd",	"d,x1,x2")
-  _MC88110 (0x84003820, "fcmpu.sss",	"d,1,2")
-  _MC88110 (0x8400b820, "fcmpu.sss",	"d,x1,x2")
-  _MC88110 (0x8400b920, "fcmpu.ssx",	"d,x1,x2")
-  _MC88110 (0x8400bca0, "fcmpu.sxd",	"d,x1,x2")
-  _MC88110 (0x8400bc20, "fcmpu.sxs",	"d,x1,x2")
-  _MC88110 (0x8400bd20, "fcmpu.sxx",	"d,x1,x2")
-  _MC88110 (0x84000880, "fcvt.ds",	"d,2")
-  _MC88110 (0x84008880, "fcvt.ds",	"xd,x2")
-  _MC88110 (0x840088c0, "fcvt.dx",	"xd,x2")
-  _MC88110 (0x84000820, "fcvt.sd",	"d,2")
-  _MC88110 (0x84008820, "fcvt.sd",	"xd,x2")
-  _MC88110 (0x84008840, "fcvt.sx",	"xd,x2")
-  _MC88110 (0x84008920, "fcvt.xd",	"xd,x2")
-  _MC88110 (0x84008900, "fcvt.xs",	"xd,x2")
-  _MC88xxx (0x84007000, "fdiv.sss",	"d,1,2")
-  _MC88110 (0x8400f000, "fdiv.sss",	"xd,x1,x2")
-  _MC88xxx (0x84007080, "fdiv.ssd",	"d,1,2")
-  _MC88110 (0x8400f020, "fdiv.ssd",	"xd,x1,x2")
-  _MC88110 (0x8400f040, "fdiv.ssx",	"xd,x1,x2")
-  _MC88xxx (0x84007200, "fdiv.sds",	"d,1,2")
-  _MC88110 (0x8400f080, "fdiv.sds",	"xd,x1,x2")
-  _MC88xxx (0x84007280, "fdiv.sdd",	"d,1,2")
-  _MC88110 (0x8400f0a0, "fdiv.sdd",	"xd,x1,x2")
-  _MC88110 (0x8400f0c0, "fdiv.sdx",	"xd,x1,x2")
-  _MC88110 (0x8400f100, "fdiv.sxs",	"xd,x1,x2")
-  _MC88110 (0x8400f120, "fdiv.sxd",	"xd,x1,x2")
-  _MC88110 (0x8400f140, "fdiv.sxx",	"xd,x1,x2")
-  _MC88xxx (0x84007020, "fdiv.dss",	"d,1,2")
-  _MC88110 (0x8400f200, "fdiv.dss",	"xd,x1,x2")
-  _MC88xxx (0x840070a0, "fdiv.dsd",	"d,1,2")
-  _MC88110 (0x8400f220, "fdiv.dsd",	"xd,x1,x2")
-  _MC88110 (0x8400f240, "fdiv.dsx",	"xd,x1,x2")
-  _MC88xxx (0x84007220, "fdiv.dds",	"d,1,2")
-  _MC88110 (0x8400f280, "fdiv.dds",	"xd,x1,x2")
-  _MC88xxx (0x840072a0, "fdiv.ddd",	"d,1,2")
-  _MC88110 (0x8400f2a0, "fdiv.ddd",	"xd,x1,x2")
-  _MC88110 (0x8400f2c0, "fdiv.ddx",	"xd,x1,x2")
-  _MC88110 (0x8400f300, "fdiv.dxs",	"xd,x1,x2")
-  _MC88110 (0x8400f320, "fdiv.dxd",	"xd,x1,x2")
-  _MC88110 (0x8400f340, "fdiv.dxx",	"xd,x1,x2")
-  _MC88110 (0x8400f400, "fdiv.xss",	"xd,x1,x2")
-  _MC88110 (0x8400f420, "fdiv.xsd",	"xd,x1,x2")
-  _MC88110 (0x8400f440, "fdiv.xsx",	"xd,x1,x2")
-  _MC88110 (0x8400f480, "fdiv.xds",	"xd,x1,x2")
-  _MC88110 (0x8400f4a0, "fdiv.xdd",	"xd,x1,x2")
-  _MC88110 (0x8400f4c0, "fdiv.xdx",	"xd,x1,x2")
-  _MC88110 (0x8400f500, "fdiv.xxs",	"xd,x1,x2")
-  _MC88110 (0x8400f520, "fdiv.xxd",	"xd,x1,x2")
-  _MC88110 (0x8400f540, "fdiv.xxx",	"xd,x1,x2")
-  _MC88xxx (0xf400ec00, "ff0",		"d,2")
-  _MC88xxx (0xf400e800, "ff1",		"d,2")
-  _MC88xxx (0x80004800, "fldcr",	"d,f")
-  _MC88xxx (0x84002020, "flt.ds",	"d,2")
-  _MC88110 (0x84002220, "flt.ds",	"xd,2")
-  _MC88xxx (0x84002000, "flt.ss",	"d,2")
-  _MC88110 (0x84002200, "flt.ss",	"xd,2")
-  _MC88110 (0x84002240, "flt.xs",	"xd,2")
-  _MC88xxx (0x84000000, "fmul.sss",	"d,1,2")
-  _MC88110 (0x84008000, "fmul.sss",	"xd,x1,x2")
-  _MC88xxx (0x84000080, "fmul.ssd",	"d,1,2")
-  _MC88110 (0x84008020, "fmul.ssd",	"xd,x1,x2")
-  _MC88110 (0x84008040, "fmul.ssx",	"xd,x1,x2")
-  _MC88xxx (0x84000200, "fmul.sds",	"d,1,2")
-  _MC88110 (0x84008080, "fmul.sds",	"xd,x1,x2")
-  _MC88xxx (0x84000280, "fmul.sdd",	"d,1,2")
-  _MC88110 (0x840080a0, "fmul.sdd",	"xd,x1,x2")
-  _MC88110 (0x840080c0, "fmul.sdx",	"xd,x1,x2")
-  _MC88110 (0x84008100, "fmul.sxs",	"xd,x1,x2")
-  _MC88110 (0x84008120, "fmul.sxd",	"xd,x1,x2")
-  _MC88110 (0x84008140, "fmul.sxx",	"xd,x1,x2")
-  _MC88xxx (0x84000020, "fmul.dss",	"d,1,2")
-  _MC88110 (0x84008200, "fmul.dss",	"xd,x1,x2")
-  _MC88xxx (0x840000a0, "fmul.dsd",	"d,1,2")
-  _MC88110 (0x84008220, "fmul.dsd",	"xd,x1,x2")
-  _MC88110 (0x84008240, "fmul.dsx",	"xd,x1,x2")
-  _MC88xxx (0x84000220, "fmul.dds",	"d,1,2")
-  _MC88110 (0x84008280, "fmul.dds",	"xd,x1,x2")
-  _MC88xxx (0x840002a0, "fmul.ddd",	"d,1,2")
-  _MC88110 (0x840082a0, "fmul.ddd",	"xd,x1,x2")
-  _MC88110 (0x840082c0, "fmul.ddx",	"xd,x1,x2")
-  _MC88110 (0x84008300, "fmul.dxs",	"xd,x1,x2")
-  _MC88110 (0x84008320, "fmul.dxd",	"xd,x1,x2")
-  _MC88110 (0x84008340, "fmul.dxx",	"xd,x1,x2")
-  _MC88110 (0x84008400, "fmul.xss",	"xd,x1,x2")
-  _MC88110 (0x84008420, "fmul.xsd",	"xd,x1,x2")
-  _MC88110 (0x84008440, "fmul.xsx",	"xd,x1,x2")
-  _MC88110 (0x84008480, "fmul.xds",	"xd,x1,x2")
-  _MC88110 (0x840084a0, "fmul.xdd",	"xd,x1,x2")
-  _MC88110 (0x840084c0, "fmul.xdx",	"xd,x1,x2")
-  _MC88110 (0x84008500, "fmul.xxs",	"xd,x1,x2")
-  _MC88110 (0x84008520, "fmul.xxd",	"xd,x1,x2")
-  _MC88110 (0x84008540, "fmul.xxx",	"xd,x1,x2")
-  _MC88110 (0x840078a0, "fsqrt.dd",	"d,2")
-  _MC88110 (0x8400f8a0, "fsqrt.dd",	"xd,x2")
-  _MC88110 (0x84007880, "fsqrt.ds",	"d,2")
-  _MC88110 (0x8400f880, "fsqrt.ds",	"xd,x2")
-  _MC88110 (0x8400f8c0, "fsqrt.dx",	"xd,x2")
-  _MC88110 (0x84007820, "fsqrt.sd",	"d,2")
-  _MC88110 (0x8400f820, "fsqrt.sd",	"xd,x2")
-  _MC88110 (0x84007800, "fsqrt.ss",	"d,2")
-  _MC88110 (0x8400f800, "fsqrt.ss",	"xd,x2")
-  _MC88110 (0x8400f840, "fsqrt.sx",	"xd,x2")
-  _MC88110 (0x8400f920, "fsqrt.xd",	"xd,x2")
-  _MC88110 (0x8400f900, "fsqrt.xs",	"xd,x2")
-  _MC88110 (0x8400f940, "fsqrt.xx",	"xd,x2")
-  _MC88xxx (0x80008800, "fstcr",	"3,f")
-  _MC88xxx (0x84003000, "fsub.sss",	"d,1,2")
-  _MC88110 (0x8400b000, "fsub.sss",	"xd,x1,x2")
-  _MC88xxx (0x84003080, "fsub.ssd",	"d,1,2")
-  _MC88110 (0x8400b020, "fsub.ssd",	"xd,x1,x2")
-  _MC88110 (0x8400b040, "fsub.ssx",	"xd,x1,x2")
-  _MC88xxx (0x84003200, "fsub.sds",	"d,1,2")
-  _MC88110 (0x8400b080, "fsub.sds",	"xd,x1,x2")
-  _MC88xxx (0x84003280, "fsub.sdd",	"d,1,2")
-  _MC88110 (0x8400b0a0, "fsub.sdd",	"xd,x1,x2")
-  _MC88110 (0x8400b0c0, "fsub.sdx",	"xd,x1,x2")
-  _MC88110 (0x8400b100, "fsub.sxs",	"xd,x1,x2")
-  _MC88110 (0x8400b120, "fsub.sxd",	"xd,x1,x2")
-  _MC88110 (0x8400b140, "fsub.sxx",	"xd,x1,x2")
-  _MC88xxx (0x84003020, "fsub.dss",	"d,1,2")
-  _MC88110 (0x8400b200, "fsub.dss",	"xd,x1,x2")
-  _MC88xxx (0x840030a0, "fsub.dsd",	"d,1,2")
-  _MC88110 (0x8400b220, "fsub.dsd",	"xd,x1,x2")
-  _MC88110 (0x8400b240, "fsub.dsx",	"xd,x1,x2")
-  _MC88xxx (0x84003220, "fsub.dds",	"d,1,2")
-  _MC88110 (0x8400b280, "fsub.dds",	"xd,x1,x2")
-  _MC88xxx (0x840032a0, "fsub.ddd",	"d,1,2")
-  _MC88110 (0x8400b2a0, "fsub.ddd",	"xd,x1,x2")
-  _MC88110 (0x8400b2c0, "fsub.ddx",	"xd,x1,x2")
-  _MC88110 (0x8400b300, "fsub.dxs",	"xd,x1,x2")
-  _MC88110 (0x8400b320, "fsub.dxd",	"xd,x1,x2")
-  _MC88110 (0x8400b340, "fsub.dxx",	"xd,x1,x2")
-  _MC88110 (0x8400b400, "fsub.xss",	"xd,x1,x2")
-  _MC88110 (0x8400b420, "fsub.xsd",	"xd,x1,x2")
-  _MC88110 (0x8400b440, "fsub.xsx",	"xd,x1,x2")
-  _MC88110 (0x8400b480, "fsub.xds",	"xd,x1,x2")
-  _MC88110 (0x8400b4a0, "fsub.xdd",	"xd,x1,x2")
-  _MC88110 (0x8400b4c0, "fsub.xdx",	"xd,x1,x2")
-  _MC88110 (0x8400b500, "fsub.xxs",	"xd,x1,x2")
-  _MC88110 (0x8400b520, "fsub.xxd",	"xd,x1,x2")
-  _MC88110 (0x8400b540, "fsub.xxx",	"xd,x1,x2")
-  _MC88xxx (0x8000c800, "fxcr",		"d,3,f")
-  _MC88xxx (0x8400fc01, "illop1",	"")
-  _MC88xxx (0x8400fc02, "illop2",	"")
-  _MC88xxx (0x8400fc03, "illop3",	"")
-  _MC88xxx (0x84004880, "int.sd",	"d,2")
-  _MC88110 (0x8400c880, "int.sd",	"d,x2")
-  _MC88xxx (0x84004800, "int.ss",	"d,2")
-  _MC88110 (0x8400c800, "int.ss",	"d,x2")
-  _MC88110 (0x8400c900, "int.sx",	"d,x2")
-  _MC88xxx (0xf400c000, "jmp",		"2")
-  _MC88xxx (0xf400c400, "jmp.n",	"2")
-  _MC88xxx (0xf400c800, "jsr",		"2")
-  _MC88xxx (0xf400cc00, "jsr.n",	"2")
-  _MC88xxx (0xf4001400, "ld",		"d,1,2")
-  _MC88xxx (0xf4001600, "ld",		"d,1[2]")
-  _MC88xxx (0x14000000, "ld",		"d,1,I")
-  _MC88110 (0xf0001600, "ld",		"xd,1[2]")
-  _MC88110 (0xf0001400, "ld",		"xd,1,2")
-  _MC88110 (0x04000000, "ld",		"xd,1,I")
-  _MC88xxx (0xf4001e00, "ld.b",		"d,1[2]")
-  _MC88xxx (0xf4001c00, "ld.b",		"d,1,2")
-  _MC88xxx (0x1c000000, "ld.b",		"d,1,I")
-  _MC88xxx (0xf4001d00, "ld.b.usr",	"d,1,2")
-  _MC88xxx (0xf4001f00, "ld.b.usr",	"d,1[2]")
-  _MC88xxx (0xf4000e00, "ld.bu",	"d,1[2]")
-  _MC88xxx (0xf4000c00, "ld.bu",	"d,1,2")
-  _MC88xxx (0x0c000000, "ld.bu",	"d,1,I")
-  _MC88xxx (0xf4000d00, "ld.bu.usr",	"d,1,2")
-  _MC88xxx (0xf4000f00, "ld.bu.usr",	"d,1[2]")
-  _MC88xxx (0xf4001200, "ld.d",		"d,1[2]")
-  _MC88xxx (0xf4001000, "ld.d",		"d,1,2")
-  _MC88xxx (0x10000000, "ld.d",		"d,1,I")
-  _MC88110 (0xf0001200, "ld.d",		"xd,1[2]")
-  _MC88110 (0xf0001000, "ld.d",		"xd,1,2")
-  _MC88110 (0x00000000, "ld.d",		"xd,1,I")
-  _MC88xxx (0xf4001100, "ld.d.usr",	"d,1,2")
-  _MC88xxx (0xf4001300, "ld.d.usr",	"d,1[2]")
-  _MC88110 (0xf0001100, "ld.d.usr",	"xd,1,2")
-  _MC88110 (0xf0001300, "ld.d.usr",	"xd,1[2]")
-  _MC88xxx (0xf4001a00, "ld.h",		"d,1[2]")
-  _MC88xxx (0xf4001800, "ld.h",		"d,1,2")
-  _MC88xxx (0x18000000, "ld.h",		"d,1,I")
-  _MC88xxx (0xf4001900, "ld.h.usr",	"d,1,2")
-  _MC88xxx (0xf4001b00, "ld.h.usr",	"d,1[2]")
-  _MC88xxx (0xf4000a00, "ld.hu",	"d,1[2]")
-  _MC88xxx (0xf4000800, "ld.hu",	"d,1,2")
-  _MC88xxx (0x08000000, "ld.hu",	"d,1,I")
-  _MC88xxx (0xf4000900, "ld.hu.usr",	"d,1,2")
-  _MC88xxx (0xf4000b00, "ld.hu.usr",	"d,1[2]")
-  _MC88xxx (0xf4001500, "ld.usr",	"d,1,2")
-  _MC88xxx (0xf4001700, "ld.usr",	"d,1[2]")
-  _MC88110 (0xf0001500, "ld.usr",	"xd,1,2")
-  _MC88110 (0xf0001700, "ld.usr",	"xd,1[2]")
-  _MC88110 (0xf0001a00, "ld.x",		"xd,1[2]")
-  _MC88110 (0xf0001800, "ld.x",		"xd,1,2")
-  _MC88110 (0x3c000000, "ld.x",		"xd,1,I")
-  _MC88110 (0xf0001900, "ld.x.usr",	"xd,1,2")
-  _MC88110 (0xf0001b00, "ld.x.usr",	"xd,1[2]")
-  _MC88xxx (0xf4003600, "lda",		"d,1[2]")
-  _MC88xxx (0xf4006000, "lda",		"?d,1,2")	/* Output addu */
-  _MC88xxx (0x60000000, "lda",		"?d,1,I")	/* Output addu */
-  _MC88xxx (0xf4006000, "lda.b",	"?d,1[2]")	/* Output addu */
-  _MC88xxx (0xf4006000, "lda.b",	"?d,1,2")	/* Output addu */
-  _MC88xxx (0x60000000, "lda.b",	"?d,1,I")	/* Output addu */
-  _MC88xxx (0xf4003200, "lda.d",	"d,1[2]")
-  _MC88xxx (0xf4006000, "lda.d",	"?d,1,2")	/* Output addu */
-  _MC88xxx (0x60000000, "lda.d",	"?d,1,I")	/* Output addu */
-  _MC88110 (0xf4003e00, "lda.x",	"d,1[2]")
-  _MC88xxx (0xf4003a00, "lda.h",	"d,1[2]")
-  _MC88xxx (0xf4006000, "lda.h",	"?d,1,2")	/* Output addu */
-  _MC88xxx (0x60000000, "lda.h",	"?d,1,I")	/* Output addu */
-  _MC88xxx (0x80004000, "ldcr",		"d,c")
-  _MC88xxx (0xf400a000, "mak",		"d,1,2")
-  _MC88xxx (0xf000a000, "mak",		"d,1,b")
-  _MC88xxx (0x48000000, "mask",		"d,1,I")
-  _MC88xxx (0x4c000000, "mask.u",	"d,1,I")
-  _MC88110 (0x8400c000, "mov.s",	"d,x2")
-  _MC88110 (0x84004200, "mov.s",	"xd,2")
-  _MC88110 (0x8400c080, "mov.d",	"d,x2")
-  _MC88110 (0x84004280, "mov.d",	"xd,2")
-  _MC88110 (0x8400c300, "mov",		"xd,x2")
-  _MC88xxx (0xf4006c00, "mul",		"d,1,2")
-  _MC88xxx (0x6c000000, "mul",		"d,1,I")
-  _MC88xxx (0xf4006e00, "muls",		"d,1,2")
-  _MC88xxx (0x6c000000, "muls",		"d,1,I")
-  _MC88xxx (0xf4006c00, "mulu",		"d,1,2")	/* synonym for mul */
-  _MC88xxx (0x6c000000, "mulu",		"d,1,I")	/* synonym for mul */
-  _MC88110 (0xf4006d00, "mulu.d",	"d,1,2")
-  _MC88xxx (0x84005080, "nint.sd",	"d,2")
-  _MC88110 (0x8400d080, "nint.sd",	"d,x2")
-  _MC88xxx (0x84005000, "nint.ss",	"d,2")
-  _MC88110 (0x8400d000, "nint.ss",	"d,x2")
-  _MC88110 (0x8400d100, "nint.sx",	"d,x2")
-  _MC88xxx (0xf4005800, "or",		"d,1,2")
-  _MC88xxx (0x58000000, "or",		"d,1,I")
-  _MC88xxx (0xf4005c00, "or.c",		"d,1,2")
-  _MC88xxx (0x5c000000, "or.u",		"d,1,I")
-  _MC88110 (0x88002020, "padd.b",	"d,1,2")
-  _MC88110 (0x88002040, "padd.h",	"d,1,2")
-  _MC88110 (0x88002060, "padd",		"d,1,2")
-  _MC88110 (0x880020a0, "padds.u.b",	"d,1,2")
-  _MC88110 (0x880020c0, "padds.u.h",	"d,1,2")
-  _MC88110 (0x880020e0, "padds.u",	"d,1,2")
-  _MC88110 (0x88002120, "padds.us.b",	"d,1,2")
-  _MC88110 (0x88002140, "padds.us.h",	"d,1,2")
-  _MC88110 (0x88002160, "padds.us",	"d,1,2")
-  _MC88110 (0x880021a0, "padds.s.b",	"d,1,2")
-  _MC88110 (0x880021c0, "padds.s.h",	"d,1,2")
-  _MC88110 (0x880021e0, "padds.s",	"d,1,2")
-  _MC88110 (0x88003860, "pcmp",		"d,1,2")
-  _MC88110 (0x88000000, "pmul",		"d,1,2")
-  _MC88110 (0x88006420, "ppack.32.b",	"d,1,2")
-  _MC88110 (0x88006240, "ppack.16.h",	"d,1,2")
-  _MC88110 (0x88006440, "ppack.32.h",	"d,1,2")
-  _MC88110 (0x88006160, "ppack.8",	"d,1,2")
-  _MC88110 (0x88006260, "ppack.16",	"d,1,2")
-  _MC88110 (0x88006460, "ppack.32",	"d,1,2")
-  _MC88110 (0x88007800, "prot",		"d,1,2")
-  _MC88110 (0x88007000, "prot",		"d,1,o")
-  _MC88110 (0x88003020, "psub.b",	"d,1,2")
-  _MC88110 (0x88003040, "psub.h",	"d,1,2")
-  _MC88110 (0x88003060, "psub",		"d,1,2")
-  _MC88110 (0x880030a0, "psubs.u.b",	"d,1,2")
-  _MC88110 (0x880030c0, "psubs.u.h",	"d,1,2")
-  _MC88110 (0x880030e0, "psubs.u",	"d,1,2")
-  _MC88110 (0x88003120, "psubs.us.b",	"d,1,2")
-  _MC88110 (0x88003140, "psubs.us.h",	"d,1,2")
-  _MC88110 (0x88003160, "psubs.us",	"d,1,2")
-  _MC88110 (0x880031a0, "psubs.s.b",	"d,1,2")
-  _MC88110 (0x880031c0, "psubs.s.h",	"d,1,2")
-  _MC88110 (0x880031e0, "psubs.s",	"d,1,2")
-  _MC88110 (0x88006800, "punpk.n",	"d,1")
-  _MC88110 (0x88006820, "punpk.b",	"d,1")
-  _MC88110 (0x88006840, "punpk.h",	"d,1")
-  _MC88xxx (0xf400a800, "rot",		"d,1,2")
-  _MC88xxx (0xf000a800, "rot",		"d,1,b")
-  _MC88xxx (0xf400fc00, "rte",		"")
-  _MC88xxx (0xf4008800, "set",		"d,1,2")
-  _MC88xxx (0xf0008800, "set",		"d,1,b")
-  _MC88xxx (0xf4002600, "st",		"d,1[2]")
-  _MC88xxx (0xf4002400, "st",		"d,1,2")
-  _MC88xxx (0x24000000, "st",		"d,1,I")
-  _MC88110 (0xf0002600, "st",		"xd,1[2]")
-  _MC88110 (0xf0002400, "st",		"xd,1,2")
-  _MC88110 (0x34000000, "st",		"xd,1,I")
-  _MC88xxx (0xf4002e00, "st.b",		"d,1[2]")
-  _MC88xxx (0xf4002c00, "st.b",		"d,1,2")
-  _MC88xxx (0x2c000000, "st.b",		"d,1,I")
-  _MC88xxx (0xf4002d00, "st.b.usr",	"d,1,2")
-  _MC88xxx (0xf4002f00, "st.b.usr",	"d,1[2]")
-  _MC88110 (0xf4002d80, "st.b.usr.wt",	"d,1,2")
-  _MC88110 (0xf4002f80, "st.b.usr.wt",	"d,1[2]")
-  _MC88110 (0xf4002c80, "st.b.wt",	"d,1,2")
-  _MC88110 (0xf4002e80, "st.b.wt",	"d,1[2]")
-  _MC88xxx (0xf4002200, "st.d",		"d,1[2]")
-  _MC88xxx (0xf4002000, "st.d",		"d,1,2")
-  _MC88xxx (0x20000000, "st.d",		"d,1,I")
-  _MC88110 (0xf0002200, "st.d",		"xd,1[2]")
-  _MC88110 (0xf0002000, "st.d",		"xd,1,2")
-  _MC88110 (0x30000000, "st.d",		"xd,1,I")
-  _MC88xxx (0xf4002100, "st.d.usr",	"d,1,2")
-  _MC88xxx (0xf4002300, "st.d.usr",	"d,1[2]")
-  _MC88110 (0xf0002100, "st.d.usr",	"xd,1,2")
-  _MC88110 (0xf0002300, "st.d.usr",	"xd,1[2]")
-  _MC88110 (0xf4002180, "st.d.usr.wt",	"d,1,2")
-  _MC88110 (0xf4002380, "st.d.usr.wt",	"d,1[2]")
-  _MC88110 (0xf0002180, "st.d.usr.wt",	"xd,1,2")
-  _MC88110 (0xf0002380, "st.d.usr.wt",	"xd,1[2]")
-  _MC88110 (0xf4002080, "st.d.wt",	"d,1,2")
-  _MC88110 (0xf4002280, "st.d.wt",	"d,1[2]")
-  _MC88110 (0xf0002080, "st.d.wt",	"xd,1,2")
-  _MC88110 (0xf0002280, "st.d.wt",	"xd,1[2]")
-  _MC88xxx (0xf4002a00, "st.h",		"d,1[2]")
-  _MC88xxx (0xf4002800, "st.h",		"d,1,2")
-  _MC88xxx (0x28000000, "st.h",		"d,1,I")
-  _MC88xxx (0xf4002900, "st.h.usr",	"d,1,2")
-  _MC88xxx (0xf4002b00, "st.h.usr",	"d,1[2]")
-  _MC88110 (0xf4002980, "st.h.usr.wt",	"d,1,2")
-  _MC88110 (0xf4002b80, "st.h.usr.wt",	"d,1[2]")
-  _MC88110 (0xf4002880, "st.h.wt",	"d,1,2")
-  _MC88110 (0xf4002a80, "st.h.wt",	"d,1[2]")
-  _MC88xxx (0xf4002500, "st.usr",	"d,1,2")
-  _MC88xxx (0xf4002700, "st.usr",	"d,1[2]")
-  _MC88110 (0xf0002500, "st.usr",	"xd,1,2")
-  _MC88110 (0xf0002700, "st.usr",	"xd,1[2]")
-  _MC88110 (0xf4002580, "st.usr.wt",	"d,1,2")
-  _MC88110 (0xf4002780, "st.usr.wt",	"d,1[2]")
-  _MC88110 (0xf0002580, "st.usr.wt",	"xd,1,2")
-  _MC88110 (0xf0002780, "st.usr.wt",	"xd,1[2]")
-  _MC88110 (0xf4002480, "st.wt",	"d,1,2")
-  _MC88110 (0xf4002680, "st.wt",	"d,1[2]")
-  _MC88110 (0xf0002480, "st.wt",	"xd,1,2")
-  _MC88110 (0xf0002680, "st.wt",	"xd,1[2]")
-  _MC88110 (0xf0002a00, "st.x",		"xd,1[2]")
-  _MC88110 (0xf0002800, "st.x",		"xd,1,2")
-  _MC88110 (0x38000000, "st.x",		"xd,1,I")
-  _MC88110 (0xf0002900, "st.x.usr",	"xd,1,2")
-  _MC88110 (0xf0002b00, "st.x.usr",	"xd,1[2]")
-  _MC88110 (0xf0002980, "st.x.usr.wt",	"xd,1,2")
-  _MC88110 (0xf0002b80, "st.x.usr.wt",	"xd,1[2]")
-  _MC88110 (0xf0002880, "st.x.wt",	"xd,1,2")
-  _MC88110 (0xf0002a80, "st.x.wt",	"xd,1[2]")
-  _MC88xxx (0x80008000, "stcr",		"3,c")
-  _MC88xxx (0xf4007400, "sub",		"d,1,2")
-  _MC88xxx (0x74000000, "sub",		"d,1,I")
-  _MC88xxx (0xf4007600, "sub.ci",	"d,1,2")
-  _MC88xxx (0xf4007700, "sub.cio",	"d,1,2")
-  _MC88xxx (0xf4007500, "sub.co",	"d,1,2")
-  _MC88xxx (0xf4006400, "subu",		"d,1,2")
-  _MC88xxx (0x64000000, "subu",		"d,1,I")
-  _MC88xxx (0xf4006600, "subu.ci",	"d,1,2")
-  _MC88xxx (0xf4006700, "subu.cio",	"d,1,2")
-  _MC88xxx (0xf4006500, "subu.co",	"d,1,2")
-  _MC88xxx (0xf000d000, "tb0",		"B,1,V")
-  _MC88xxx (0xf000d800, "tb1",		"B,1,V")
-  _MC88xxx (0xf400f800, "tbnd",		"1,2")
-  _MC88xxx (0xf8000000, "tbnd",		"1,I")
-  _MC88xxx (0xf000e800, "tcnd",		"M,1,V")
-  _MC88xxx (0x84005880, "trnc.sd",	"d,2")
-  _MC88110 (0x8400d880, "trnc.sd",	"d,x2")
-  _MC88xxx (0x84005800, "trnc.ss",	"d,2")
-  _MC88110 (0x8400d800, "trnc.ss",	"d,x2")
-  _MC88110 (0x8400d900, "trnc.sx",	"d,x2")
-  _MC88xxx (0x8000c000, "xcr",		"d,3,c")
-  _MC88xxx (0xf4000600, "xmem",		"d,1[2]")
-  _MC88xxx (0xf4000400, "xmem",		"d,1,2")
-  _MC88100 (0x04000000, "xmem",		"?d,1,I")
-  _MC88xxx (0xf4000200, "xmem.bu",	"d,1[2]")
-  _MC88xxx (0xf4000000, "xmem.bu",	"d,1,2")
-  _MC88100 (0x00000000, "xmem.bu",	"?d,1,I")
-  _MC88xxx (0xf4000300, "xmem.bu.usr",	"d,1[2]")
-  _MC88xxx (0xf4000100, "xmem.bu.usr",	"d,1,2")
-  _MC88100 (0x00000100, "xmem.bu.usr",	"?d,1,I")
-  _MC88xxx (0xf4000700, "xmem.usr",	"d,1[2]")
-  _MC88xxx (0xf4000500, "xmem.usr",	"d,1,2")
-  _MC88100 (0x04000100, "xmem.usr",	"?d,1,I")
-  _MC88xxx (0xf4005000, "xor",		"d,1,2")
-  _MC88xxx (0x50000000, "xor",		"d,1,I")
-  _MC88xxx (0xf4005400, "xor.c",	"d,1,2")
-  _MC88xxx (0x54000000, "xor.u",	"d,1,I")
-  _MC88xxx (0x00000000, "",		0)
-};
-
-#define NUMOPCODES ((sizeof m88k_opcodes)/(sizeof m88k_opcodes[0]))
diff --git a/gas/config/obj-aout.c b/gas/config/obj-aout.c
index 6e5fd29191a1..e99e63d9574a 100644
--- a/gas/config/obj-aout.c
+++ b/gas/config/obj-aout.c
@@ -1,110 +1,33 @@
 /* a.out object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
-   2001, 2002 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
-This file is part of GAS, the GNU Assembler.
+   This file is part of GAS, the GNU Assembler.
 
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as
-published by the Free Software Foundation; either version 2,
-or (at your option) any later version.
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as
+   published by the Free Software Foundation; either version 2,
+   or (at your option) any later version.
 
-GAS is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
+   GAS is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+   the GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define OBJ_HEADER "obj-aout.h"
 
 #include "as.h"
-#ifdef BFD_ASSEMBLER
 #undef NO_RELOC
 #include "aout/aout64.h"
-#endif
 #include "obstack.h"
 
-#ifndef BFD_ASSEMBLER
-/* in: segT   out: N_TYPE bits */
-const short seg_N_TYPE[] =
-{
-  N_ABS,
-  N_TEXT,
-  N_DATA,
-  N_BSS,
-  N_UNDF,			/* unknown */
-  N_UNDF,			/* error */
-  N_UNDF,			/* expression */
-  N_UNDF,			/* debug */
-  N_UNDF,			/* ntv */
-  N_UNDF,			/* ptv */
-  N_REGISTER,			/* register */
-};
-
-const segT N_TYPE_seg[N_TYPE + 2] =
-{				/* N_TYPE == 0x1E = 32-2 */
-  SEG_UNKNOWN,			/* N_UNDF == 0 */
-  SEG_GOOF,
-  SEG_ABSOLUTE,			/* N_ABS == 2 */
-  SEG_GOOF,
-  SEG_TEXT,			/* N_TEXT == 4 */
-  SEG_GOOF,
-  SEG_DATA,			/* N_DATA == 6 */
-  SEG_GOOF,
-  SEG_BSS,			/* N_BSS == 8 */
-  SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_REGISTER,			/* dummy N_REGISTER for regs = 30 */
-  SEG_GOOF,
-};
-#endif
-
-static void obj_aout_line PARAMS ((int));
-static void obj_aout_weak PARAMS ((int));
-static void obj_aout_type PARAMS ((int));
-
-const pseudo_typeS aout_pseudo_table[] =
-{
-  {"line", obj_aout_line, 0},	/* source code line number */
-  {"ln", obj_aout_line, 0},	/* coff line number that we use anyway */
-
-  {"weak", obj_aout_weak, 0},	/* mark symbol as weak.  */
-
-  {"type", obj_aout_type, 0},
-
-  /* coff debug pseudos (ignored) */
-  {"def", s_ignore, 0},
-  {"dim", s_ignore, 0},
-  {"endef", s_ignore, 0},
-  {"ident", s_ignore, 0},
-  {"line", s_ignore, 0},
-  {"ln", s_ignore, 0},
-  {"scl", s_ignore, 0},
-  {"size", s_ignore, 0},
-  {"tag", s_ignore, 0},
-  {"val", s_ignore, 0},
-  {"version", s_ignore, 0},
-
-  {"optim", s_ignore, 0},	/* For sun386i cc (?) */
-
-  /* other stuff */
-  {"ABORT", s_abort, 0},
-
-  {NULL, NULL, 0}		/* end sentinel */
-};				/* aout_pseudo_table */
-
-#ifdef BFD_ASSEMBLER
-
 void
-obj_aout_frob_symbol (sym, punt)
-     symbolS *sym;
-     int *punt ATTRIBUTE_UNUSED;
+obj_aout_frob_symbol (symbolS *sym, int *punt ATTRIBUTE_UNUSED)
 {
   flagword flags;
   asection *sec;
@@ -184,23 +107,18 @@ obj_aout_frob_symbol (sym, punt)
 	}
     }
   else
-    {
-      symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
-    }
+    symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
 
   aout_symbol (symbol_get_bfdsym (sym))->type = type;
 
   /* Double check weak symbols.  */
-  if (S_IS_WEAK (sym))
-    {
-      if (S_IS_COMMON (sym))
-	as_bad (_("Symbol `%s' can not be both weak and common"),
-		S_GET_NAME (sym));
-    }
+  if (S_IS_WEAK (sym) && S_IS_COMMON (sym))
+    as_bad (_("Symbol `%s' can not be both weak and common"),
+	    S_GET_NAME (sym));
 }
 
 void
-obj_aout_frob_file_before_fix ()
+obj_aout_frob_file_before_fix (void)
 {
   /* Relocation processing may require knowing the VMAs of the sections.
      Since writing to a section will cause the BFD back end to compute the
@@ -208,166 +126,29 @@ obj_aout_frob_file_before_fix ()
   bfd_byte b = 0;
   bfd_boolean x = TRUE;
   if (bfd_section_size (stdoutput, text_section) != 0)
-    {
-      x = bfd_set_section_contents (stdoutput, text_section, &b, (file_ptr) 0,
-				    (bfd_size_type) 1);
-    }
+    x = bfd_set_section_contents (stdoutput, text_section, &b, (file_ptr) 0,
+				  (bfd_size_type) 1);
   else if (bfd_section_size (stdoutput, data_section) != 0)
-    {
-      x = bfd_set_section_contents (stdoutput, data_section, &b, (file_ptr) 0,
-				    (bfd_size_type) 1);
-    }
-  assert (x);
-}
-
-#else /* ! BFD_ASSEMBLER */
-
-/* Relocation.  */
-
-/*
- *		emit_relocations()
- *
- * Crawl along a fixS chain. Emit the segment's relocations.
- */
-void
-obj_emit_relocations (where, fixP, segment_address_in_file)
-     char **where;
-     fixS *fixP;		/* Fixup chain for this segment.  */
-     relax_addressT segment_address_in_file;
-{
-  for (; fixP; fixP = fixP->fx_next)
-    if (fixP->fx_done == 0)
-      {
-	symbolS *sym;
-
-	sym = fixP->fx_addsy;
-	while (sym->sy_value.X_op == O_symbol
-	       && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym)))
-	  sym = sym->sy_value.X_add_symbol;
-	fixP->fx_addsy = sym;
-
-	if (! sym->sy_resolved && ! S_IS_DEFINED (sym))
-	  {
-	    char *file;
-	    unsigned int line;
-
-	    if (expr_symbol_where (sym, &file, &line))
-	      as_bad_where (file, line, _("unresolved relocation"));
-	    else
-	      as_bad (_("bad relocation: symbol `%s' not in symbol table"),
-		      S_GET_NAME (sym));
-	  }
-
-	tc_aout_fix_to_chars (*where, fixP, segment_address_in_file);
-	*where += md_reloc_size;
-      }
-}
-
-#ifndef obj_header_append
-/* Aout file generation & utilities */
-void
-obj_header_append (where, headers)
-     char **where;
-     object_headers *headers;
-{
-  tc_headers_hook (headers);
-
-#ifdef CROSS_COMPILE
-  md_number_to_chars (*where, headers->header.a_info, sizeof (headers->header.a_info));
-  *where += sizeof (headers->header.a_info);
-  md_number_to_chars (*where, headers->header.a_text, sizeof (headers->header.a_text));
-  *where += sizeof (headers->header.a_text);
-  md_number_to_chars (*where, headers->header.a_data, sizeof (headers->header.a_data));
-  *where += sizeof (headers->header.a_data);
-  md_number_to_chars (*where, headers->header.a_bss, sizeof (headers->header.a_bss));
-  *where += sizeof (headers->header.a_bss);
-  md_number_to_chars (*where, headers->header.a_syms, sizeof (headers->header.a_syms));
-  *where += sizeof (headers->header.a_syms);
-  md_number_to_chars (*where, headers->header.a_entry, sizeof (headers->header.a_entry));
-  *where += sizeof (headers->header.a_entry);
-  md_number_to_chars (*where, headers->header.a_trsize, sizeof (headers->header.a_trsize));
-  *where += sizeof (headers->header.a_trsize);
-  md_number_to_chars (*where, headers->header.a_drsize, sizeof (headers->header.a_drsize));
-  *where += sizeof (headers->header.a_drsize);
-
-#else /* CROSS_COMPILE */
-
-  append (where, (char *) &headers->header, sizeof (headers->header));
-#endif /* CROSS_COMPILE */
-
-}
-#endif /* ! defined (obj_header_append) */
-
-void
-obj_symbol_to_chars (where, symbolP)
-     char **where;
-     symbolS *symbolP;
-{
-  md_number_to_chars ((char *) &(S_GET_OFFSET (symbolP)), S_GET_OFFSET (symbolP), sizeof (S_GET_OFFSET (symbolP)));
-  md_number_to_chars ((char *) &(S_GET_DESC (symbolP)), S_GET_DESC (symbolP), sizeof (S_GET_DESC (symbolP)));
-  md_number_to_chars ((char *) &(symbolP->sy_symbol.n_value), S_GET_VALUE (symbolP), sizeof (symbolP->sy_symbol.n_value));
+    x = bfd_set_section_contents (stdoutput, data_section, &b, (file_ptr) 0,
+				  (bfd_size_type) 1);
 
-  append (where, (char *) &symbolP->sy_symbol, sizeof (obj_symbol_type));
-}
-
-void
-obj_emit_symbols (where, symbol_rootP)
-     char **where;
-     symbolS *symbol_rootP;
-{
-  symbolS *symbolP;
-
-  /* Emit all symbols left in the symbol chain.  */
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Used to save the offset of the name. It is used to point
-	 to the string in memory but must be a file offset.  */
-      register char *temp;
-
-      temp = S_GET_NAME (symbolP);
-      S_SET_OFFSET (symbolP, symbolP->sy_name_offset);
-
-      /* Any symbol still undefined and is not a dbg symbol is made N_EXT.  */
-      if (!S_IS_DEBUG (symbolP) && !S_IS_DEFINED (symbolP))
-	S_SET_EXTERNAL (symbolP);
-
-      /* Adjust the type of a weak symbol.  */
-      if (S_GET_WEAK (symbolP))
-	{
-	  switch (S_GET_TYPE (symbolP))
-	    {
-	    case N_UNDF: S_SET_TYPE (symbolP, N_WEAKU); break;
-	    case N_ABS:	 S_SET_TYPE (symbolP, N_WEAKA); break;
-	    case N_TEXT: S_SET_TYPE (symbolP, N_WEAKT); break;
-	    case N_DATA: S_SET_TYPE (symbolP, N_WEAKD); break;
-	    case N_BSS:  S_SET_TYPE (symbolP, N_WEAKB); break;
-	    default: as_bad (_("%s: bad type for weak symbol"), temp); break;
-	    }
-	}
-
-      obj_symbol_to_chars (where, symbolP);
-      S_SET_NAME (symbolP, temp);
-    }
+  assert (x);
 }
 
-#endif /* ! BFD_ASSEMBLER */
-
 static void
-obj_aout_line (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_aout_line (int ignore ATTRIBUTE_UNUSED)
 {
   /* Assume delimiter is part of expression.
      BSD4.2 as fails with delightful bug, so we
      are not being incompatible here.  */
   new_logical_line ((char *) NULL, (int) (get_absolute_expression ()));
   demand_empty_rest_of_line ();
-}				/* obj_aout_line() */
+}
 
 /* Handle .weak.  This is a GNU extension.  */
 
 static void
-obj_aout_weak (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_aout_weak (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int c;
@@ -399,8 +180,7 @@ obj_aout_weak (ignore)
    we can't parse it.  */
 
 static void
-obj_aout_type (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_aout_type (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int c;
@@ -419,17 +199,9 @@ obj_aout_type (ignore)
 	{
 	  ++input_line_pointer;
 	  if (strncmp (input_line_pointer, "object", 6) == 0)
-#ifdef BFD_ASSEMBLER
-	    aout_symbol (symbol_get_bfdsym (sym))->other = 1;
-#else
-	  S_SET_OTHER (sym, 1);
-#endif
+	    S_SET_OTHER (sym, 1);
 	  else if (strncmp (input_line_pointer, "function", 8) == 0)
-#ifdef BFD_ASSEMBLER
-	    aout_symbol (symbol_get_bfdsym (sym))->other = 2;
-#else
-	  S_SET_OTHER (sym, 2);
-#endif
+	    S_SET_OTHER (sym, 2);
 	}
     }
 
@@ -437,271 +209,136 @@ obj_aout_type (ignore)
   s_ignore (0);
 }
 
-#ifndef BFD_ASSEMBLER
-
-void
-obj_crawl_symbol_chain (headers)
-     object_headers *headers;
-{
-  symbolS *symbolP;
-  symbolS **symbolPP;
-  int symbol_number = 0;
-
-  tc_crawl_symbol_chain (headers);
-
-  symbolPP = &symbol_rootP;	/*->last symbol chain link.  */
-  while ((symbolP = *symbolPP) != NULL)
-    {
-      if (symbolP->sy_mri_common)
-	{
-	  if (S_IS_EXTERNAL (symbolP))
-	    as_bad (_("%s: global symbols not supported in common sections"),
-		    S_GET_NAME (symbolP));
-	  *symbolPP = symbol_next (symbolP);
-	  continue;
-	}
-
-      if (flag_readonly_data_in_text && (S_GET_SEGMENT (symbolP) == SEG_DATA))
-	{
-	  S_SET_SEGMENT (symbolP, SEG_TEXT);
-	}			/* if pushing data into text */
-
-      resolve_symbol_value (symbolP);
-
-      /* Skip symbols which were equated to undefined or common
-	 symbols.  Also skip defined uncommon symbols which can
-	 be resolved since in this case they should have been
-	 resolved to a non-symbolic constant.  */
-      if (symbolP->sy_value.X_op == O_symbol
-	  && (! S_IS_DEFINED (symbolP)
-	      || S_IS_COMMON (symbolP)
-	      || symbol_resolved_p (symbolP)))
-	{
-	  *symbolPP = symbol_next (symbolP);
-	  continue;
-	}
-
-      /* OK, here is how we decide which symbols go out into the brave
-	 new symtab.  Symbols that do are:
-
-	 * symbols with no name (stabd's?)
-	 * symbols with debug info in their N_TYPE
-
-	 Symbols that don't are:
-	 * symbols that are registers
-	 * symbols with \1 as their 3rd character (numeric labels)
-	 * "local labels" as defined by S_LOCAL_NAME(name) if the -L
-	 switch was passed to gas.
-
-	 All other symbols are output.  We complain if a deleted
-	 symbol was marked external.  */
-
-      if (!S_IS_REGISTER (symbolP)
-	  && (!S_GET_NAME (symbolP)
-	      || S_IS_DEBUG (symbolP)
-	      || !S_IS_DEFINED (symbolP)
-	      || S_IS_EXTERNAL (symbolP)
-	      || (S_GET_NAME (symbolP)[0] != '\001'
-		  && (flag_keep_locals || !S_LOCAL_NAME (symbolP)))))
-	{
-	  symbolP->sy_number = symbol_number++;
-
-	  /* The + 1 after strlen account for the \0 at the
-			   end of each string */
-	  if (!S_IS_STABD (symbolP))
-	    {
-	      /* Ordinary case.  */
-	      symbolP->sy_name_offset = string_byte_count;
-	      string_byte_count += strlen (S_GET_NAME (symbolP)) + 1;
-	    }
-	  else			/* .Stabd case.  */
-	    symbolP->sy_name_offset = 0;
-	  symbolPP = &symbolP->sy_next;
-	}
-      else
-	{
-	  if (S_IS_EXTERNAL (symbolP) || !S_IS_DEFINED (symbolP))
-	    /* This warning should never get triggered any more.
-	       Well, maybe if you're doing twisted things with
-	       register names...  */
-	    {
-	      as_bad (_("Local symbol %s never defined."), decode_local_label_name (S_GET_NAME (symbolP)));
-	    }			/* oops.  */
-
-	  /* Unhook it from the chain */
-	  *symbolPP = symbol_next (symbolP);
-	}			/* if this symbol should be in the output */
-    }				/* for each symbol */
-
-  H_SET_SYMBOL_TABLE_SIZE (headers, symbol_number);
-}
-
-/*
- * Find strings by crawling along symbol table chain.
- */
-
-void
-obj_emit_strings (where)
-     char **where;
-{
-  symbolS *symbolP;
-
-#ifdef CROSS_COMPILE
-  /* Gotta do md_ byte-ordering stuff for string_byte_count first - KWK */
-  md_number_to_chars (*where, string_byte_count, sizeof (string_byte_count));
-  *where += sizeof (string_byte_count);
-#else /* CROSS_COMPILE */
-  append (where, (char *) &string_byte_count, (unsigned long) sizeof (string_byte_count));
-#endif /* CROSS_COMPILE */
-
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      if (S_GET_NAME (symbolP))
-	append (&next_object_file_charP, S_GET_NAME (symbolP),
-		(unsigned long) (strlen (S_GET_NAME (symbolP)) + 1));
-    }				/* walk symbol chain */
-}
-
-#ifndef AOUT_VERSION
-#define AOUT_VERSION 0
-#endif
-
-void
-obj_pre_write_hook (headers)
-     object_headers *headers;
-{
-  H_SET_DYNAMIC (headers, 0);
-  H_SET_VERSION (headers, AOUT_VERSION);
-  H_SET_MACHTYPE (headers, AOUT_MACHTYPE);
-  tc_aout_pre_write_hook (headers);
-}
-
-#endif /* ! BFD_ASSEMBLER */
-
-#ifdef BFD_ASSEMBLER
-
 /* Support for an AOUT emulation.  */
 
-static void aout_pop_insert PARAMS ((void));
-static int obj_aout_s_get_other PARAMS ((symbolS *));
-static void obj_aout_s_set_other PARAMS ((symbolS *, int));
-static int obj_aout_s_get_desc PARAMS ((symbolS *));
-static void obj_aout_s_set_desc PARAMS ((symbolS *, int));
-static int obj_aout_s_get_type PARAMS ((symbolS *));
-static void obj_aout_s_set_type PARAMS ((symbolS *, int));
-static int obj_aout_separate_stab_sections PARAMS ((void));
-static int obj_aout_sec_sym_ok_for_reloc PARAMS ((asection *));
-static void obj_aout_process_stab PARAMS ((segT, int, const char *, int, int, int));
-
 static void
-aout_pop_insert ()
+aout_pop_insert (void)
 {
   pop_insert (aout_pseudo_table);
 }
 
 static int
-obj_aout_s_get_other (sym)
-     symbolS *sym;
+obj_aout_s_get_other (symbolS *sym)
 {
   return aout_symbol (symbol_get_bfdsym (sym))->other;
 }
 
 static void
-obj_aout_s_set_other (sym, o)
-     symbolS *sym;
-     int o;
+obj_aout_s_set_other (symbolS *sym, int o)
 {
   aout_symbol (symbol_get_bfdsym (sym))->other = o;
 }
 
 static int
-obj_aout_sec_sym_ok_for_reloc (sec)
-     asection *sec ATTRIBUTE_UNUSED;
+obj_aout_sec_sym_ok_for_reloc (asection *sec ATTRIBUTE_UNUSED)
 {
   return obj_sec_sym_ok_for_reloc (sec);
 }
 
 static void
-obj_aout_process_stab (seg, w, s, t, o, d)
-     segT seg ATTRIBUTE_UNUSED;
-     int w;
-     const char *s;
-     int t;
-     int o;
-     int d;
+obj_aout_process_stab (segT seg ATTRIBUTE_UNUSED,
+		       int w,
+		       const char *s,
+		       int t,
+		       int o,
+		       int d)
 {
   aout_process_stab (w, s, t, o, d);
 }
 
 static int
-obj_aout_s_get_desc (sym)
-     symbolS *sym;
+obj_aout_s_get_desc (symbolS *sym)
 {
   return aout_symbol (symbol_get_bfdsym (sym))->desc;
 }
 
 static void
-obj_aout_s_set_desc (sym, d)
-     symbolS *sym;
-     int d;
+obj_aout_s_set_desc (symbolS *sym, int d)
 {
   aout_symbol (symbol_get_bfdsym (sym))->desc = d;
 }
 
 static int
-obj_aout_s_get_type (sym)
-     symbolS *sym;
+obj_aout_s_get_type (symbolS *sym)
 {
   return aout_symbol (symbol_get_bfdsym (sym))->type;
 }
 
 static void
-obj_aout_s_set_type (sym, t)
-     symbolS *sym;
-     int t;
+obj_aout_s_set_type (symbolS *sym, int t)
 {
   aout_symbol (symbol_get_bfdsym (sym))->type = t;
 }
 
 static int
-obj_aout_separate_stab_sections ()
+obj_aout_separate_stab_sections (void)
 {
   return 0;
 }
 
 /* When changed, make sure these table entries match the single-format
    definitions in obj-aout.h.  */
+
 const struct format_ops aout_format_ops =
 {
   bfd_target_aout_flavour,
-  1,	/* dfl_leading_underscore */
-  0,	/* emit_section_symbols */
-  0,	/* begin */
-  0,	/* app_file */
+  1,	/* dfl_leading_underscore.  */
+  0,	/* emit_section_symbols.  */
+  0,	/* begin.  */
+  0,	/* app_file.  */
   obj_aout_frob_symbol,
-  0,	/* frob_file */
-  0,	/* frob_file_before_adjust */
+  0,	/* frob_file.  */
+  0,	/* frob_file_before_adjust.  */
   obj_aout_frob_file_before_fix,
-  0,	/* frob_file_after_relocs */
-  0,	/* s_get_size */
-  0,	/* s_set_size */
-  0,	/* s_get_align */
-  0,	/* s_set_align */
+  0,	/* frob_file_after_relocs.  */
+  0,	/* s_get_size.  */
+  0,	/* s_set_size.  */
+  0,	/* s_get_align.  */
+  0,	/* s_set_align.  */
   obj_aout_s_get_other,
   obj_aout_s_set_other,
   obj_aout_s_get_desc,
   obj_aout_s_set_desc,
   obj_aout_s_get_type,
   obj_aout_s_set_type,
-  0,	/* copy_symbol_attributes */
-  0,	/* generate_asm_lineno */
+  0,	/* copy_symbol_attributes.  */
+  0,	/* generate_asm_lineno.  */
   obj_aout_process_stab,
   obj_aout_separate_stab_sections,
-  0,	/* init_stab_section */
+  0,	/* init_stab_section.  */
   obj_aout_sec_sym_ok_for_reloc,
   aout_pop_insert,
-  0,	/* ecoff_set_ext */
-  0,	/* read_begin_hook */
-  0 	/* symbol_new_hook */
+  0,	/* ecoff_set_ext.  */
+  0,	/* read_begin_hook.  */
+  0 	/* symbol_new_hook.  */
+};
+
+const pseudo_typeS aout_pseudo_table[] =
+{
+  {"line", obj_aout_line, 0},	/* Source code line number.  */
+  {"ln", obj_aout_line, 0},	/* COFF line number that we use anyway.  */
+
+  {"weak", obj_aout_weak, 0},	/* Mark symbol as weak.  */
+
+  {"type", obj_aout_type, 0},
+
+  /* coff debug pseudos (ignored) */
+  {"def", s_ignore, 0},
+  {"dim", s_ignore, 0},
+  {"endef", s_ignore, 0},
+  {"ident", s_ignore, 0},
+  {"line", s_ignore, 0},
+  {"ln", s_ignore, 0},
+  {"scl", s_ignore, 0},
+  {"size", s_ignore, 0},
+  {"tag", s_ignore, 0},
+  {"val", s_ignore, 0},
+  {"version", s_ignore, 0},
+
+  {"optim", s_ignore, 0},	/* For sun386i cc (?).  */
+
+  /* other stuff */
+  {"ABORT", s_abort, 0},
+
+  {NULL, NULL, 0}
 };
-#endif /* BFD_ASSEMBLER */
diff --git a/gas/config/obj-aout.h b/gas/config/obj-aout.h
index 23a2907acc56..4acc4201eb9c 100644
--- a/gas/config/obj-aout.h
+++ b/gas/config/obj-aout.h
@@ -1,6 +1,6 @@
 /* obj-aout.h, a.out object file format for gas, the assembler.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000,
-   2002, 2003 Free Software Foundation, Inc.
+   2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,56 +16,30 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Tag to validate a.out object file format processing */
 #define OBJ_AOUT 1
 
 #include "targ-cpu.h"
 
-#ifdef BFD_ASSEMBLER
-
 #include "bfd/libaout.h"
 
 #define OUTPUT_FLAVOR bfd_target_aout_flavour
 
-#else /* ! BFD_ASSEMBLER */
-
-#ifndef VMS
-#include "aout_gnu.h"		/* Needed to define struct nlist. Sigh.  */
-#else
-#include "a_out.h"
-#endif
-
-#ifndef AOUT_MACHTYPE
-#define AOUT_MACHTYPE 0
-#endif /* AOUT_MACHTYPE */
-
-extern const short seg_N_TYPE[];
-extern const segT N_TYPE_seg[];
-
-#ifndef DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE	(OMAGIC)
-#endif /* DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE */
-
-#endif /* ! BFD_ASSEMBLER */
-
 extern const pseudo_typeS aout_pseudo_table[];
 
 #ifndef obj_pop_insert
 #define obj_pop_insert() pop_insert (aout_pseudo_table)
 #endif
 
-/* SYMBOL TABLE */
-/* Symbol table entry data type */
+/* Symbol table entry data type.  */
 
-typedef struct nlist obj_symbol_type;	/* Symbol table entry */
+typedef struct nlist obj_symbol_type;	/* Symbol table entry.  */
 
 /* Symbol table macros and constants */
 
-#ifdef BFD_ASSEMBLER
-
 #define S_SET_OTHER(S,V) \
   (aout_symbol (symbol_get_bfdsym (S))->other = (V))
 #define S_SET_TYPE(S,T) \
@@ -83,170 +57,11 @@ asection *text_section, *data_section, *bss_section;
 
 #define obj_frob_symbol(S,PUNT)	obj_aout_frob_symbol (S, &PUNT)
 #define obj_frob_file_before_fix() obj_aout_frob_file_before_fix ()
-extern void obj_aout_frob_symbol PARAMS ((symbolS *, int *));
-extern void obj_aout_frob_file_before_fix PARAMS ((void));
-
-#define obj_sec_sym_ok_for_reloc(SEC)	(1)
-
-#else
-
-/* We use the sy_obj field to record whether a symbol is weak.  */
-#define OBJ_SYMFIELD_TYPE char
-
-/*
- *  Macros to extract information from a symbol table entry.
- *  This syntactic indirection allows independence regarding a.out or coff.
- *  The argument (s) of all these macros is a pointer to a symbol table entry.
- */
-
-/* True if the symbol is external */
-#define S_IS_EXTERNAL(s)	((s)->sy_symbol.n_type & N_EXT)
-
-/* True if symbol has been defined, ie is in N_{TEXT,DATA,BSS,ABS} or N_EXT */
-#define S_IS_DEFINED(s) \
-  (S_GET_TYPE (s) != N_UNDF || S_GET_DESC (s) != 0)
-
-#define S_IS_COMMON(s) \
-  (S_GET_TYPE (s) == N_UNDF && S_GET_VALUE (s) != 0)
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) \
-  (!SEG_NORMAL (S_GET_SEGMENT (s)))
-
-#define S_IS_REGISTER(s)	((s)->sy_symbol.n_type == N_REGISTER)
-
-/* True if a debug special symbol entry */
-#define S_IS_DEBUG(s)		((s)->sy_symbol.n_type & N_STAB)
-/* True if a symbol is local symbol name */
-#define S_IS_LOCAL(s) 					\
-  ((S_GET_NAME (s) 					\
-    && !S_IS_DEBUG (s) 					\
-    && (strchr (S_GET_NAME (s), '\001') != NULL		\
-        || strchr (S_GET_NAME (s), '\002') != NULL	\
-        || (S_LOCAL_NAME(s) && !flag_keep_locals)))	\
-   || (flag_strip_local_absolute			\
-       && ! S_IS_EXTERNAL(s)				\
-       && S_GET_SEGMENT (s) == absolute_section))
-/* True if a symbol is not defined in this file */
-#define S_IS_EXTERN(s)		((s)->sy_symbol.n_type & N_EXT)
-/* True if the symbol has been generated because of a .stabd directive */
-#define S_IS_STABD(s)		(S_GET_NAME(s) == (char *)0)
 
-/* Accessors */
-/* The name of the symbol */
-#define S_GET_NAME(s)		((s)->sy_symbol.n_un.n_name)
-/* The pointer to the string table */
-#define S_GET_OFFSET(s)		((s)->sy_symbol.n_un.n_strx)
-/* The type of the symbol */
-#define S_GET_TYPE(s)		((s)->sy_symbol.n_type & N_TYPE)
-/* The numeric value of the segment */
-#define S_GET_SEGMENT(s)	(N_TYPE_seg[S_GET_TYPE(s)])
-/* The n_other expression value */
-#define S_GET_OTHER(s)		((s)->sy_symbol.n_other)
-/* The n_desc expression value */
-#define S_GET_DESC(s)		((s)->sy_symbol.n_desc)
-/* Whether the symbol is weak.  */
-#define S_GET_WEAK(s)		((s)->sy_obj)
+extern void obj_aout_frob_symbol (symbolS *, int *);
+extern void obj_aout_frob_file_before_fix (void);
 
-/* Modifiers */
-/* Assume that a symbol cannot be simultaneously in more than on segment */
-/* set segment */
-#define S_SET_SEGMENT(s,seg)	((s)->sy_symbol.n_type &= ~N_TYPE,(s)->sy_symbol.n_type|=SEGMENT_TO_SYMBOL_TYPE(seg))
-/* The symbol is external */
-#define S_SET_EXTERNAL(s)	((s)->sy_symbol.n_type |= N_EXT)
-/* The symbol is not external */
-#define S_CLEAR_EXTERNAL(s)	((s)->sy_symbol.n_type &= ~N_EXT)
-/* Set the name of the symbol */
-#define S_SET_NAME(s,v)		((s)->sy_symbol.n_un.n_name = (v))
-/* Set the offset in the string table */
-#define S_SET_OFFSET(s,v)	((s)->sy_symbol.n_un.n_strx = (v))
-/* Set the n_type field */
-#define S_SET_TYPE(s,t)		((s)->sy_symbol.n_type = (t))
-/* Set the n_other expression value */
-#define S_SET_OTHER(s,v)	((s)->sy_symbol.n_other = (v))
-/* Set the n_desc expression value */
-#define S_SET_DESC(s,v)		((s)->sy_symbol.n_desc = (v))
-/* Mark the symbol as weak.  This causes n_type to be adjusted when
-   the symbol is written out.  */
-#define S_SET_WEAK(s)		((s)->sy_obj = 1)
-
-/* File header macro and type definition */
-
-#define H_GET_FILE_SIZE(h)	(H_GET_HEADER_SIZE(h) \
-				 + H_GET_TEXT_SIZE(h) \
-				 + H_GET_DATA_SIZE(h) \
-				 + H_GET_SYMBOL_TABLE_SIZE(h) \
-				 + H_GET_TEXT_RELOCATION_SIZE(h) \
-				 + H_GET_DATA_RELOCATION_SIZE(h) \
-				 + H_GET_STRING_SIZE(h))
-
-#define H_GET_HEADER_SIZE(h)		(EXEC_BYTES_SIZE)
-#define H_GET_TEXT_SIZE(h)		((h)->header.a_text)
-#define H_GET_DATA_SIZE(h)		((h)->header.a_data)
-#define H_GET_BSS_SIZE(h)		((h)->header.a_bss)
-#define H_GET_TEXT_RELOCATION_SIZE(h)	((h)->header.a_trsize)
-#define H_GET_DATA_RELOCATION_SIZE(h)	((h)->header.a_drsize)
-#define H_GET_SYMBOL_TABLE_SIZE(h)	((h)->header.a_syms)
-#define H_GET_ENTRY_POINT(h)		((h)->header.a_entry)
-#define H_GET_STRING_SIZE(h)		((h)->string_table_size)
-#define H_GET_LINENO_SIZE(h)		(0)
-
-#define H_GET_DYNAMIC(h)		((h)->header.a_info >> 31)
-#define H_GET_VERSION(h)		(((h)->header.a_info >> 24) & 0x7f)
-#define H_GET_MACHTYPE(h)		(((h)->header.a_info >> 16) & 0xff)
-#define H_GET_MAGIC_NUMBER(h)		((h)->header.a_info & 0xffff)
-
-#define H_SET_DYNAMIC(h,v)		((h)->header.a_info = (((v) << 31) \
-							       | (H_GET_VERSION(h) << 24) \
-							       | (H_GET_MACHTYPE(h) << 16) \
-							       | (H_GET_MAGIC_NUMBER(h))))
-
-#define H_SET_VERSION(h,v)		((h)->header.a_info = ((H_GET_DYNAMIC(h) << 31) \
-							       | ((v) << 24) \
-							       | (H_GET_MACHTYPE(h) << 16) \
-							       | (H_GET_MAGIC_NUMBER(h))))
-
-#define H_SET_MACHTYPE(h,v)		((h)->header.a_info = ((H_GET_DYNAMIC(h) << 31) \
-							       | (H_GET_VERSION(h) << 24) \
-							       | ((v) << 16) \
-							       | (H_GET_MAGIC_NUMBER(h))))
-
-#define H_SET_MAGIC_NUMBER(h,v)		((h)->header.a_info = ((H_GET_DYNAMIC(h) << 31) \
-							       | (H_GET_VERSION(h) << 24) \
-							       | (H_GET_MACHTYPE(h) << 16) \
-							       | ((v))))
-
-#define H_SET_TEXT_SIZE(h,v)		((h)->header.a_text = md_section_align(SEG_TEXT, (v)))
-#define H_SET_DATA_SIZE(h,v)		((h)->header.a_data = md_section_align(SEG_DATA, (v)))
-#define H_SET_BSS_SIZE(h,v)		((h)->header.a_bss = md_section_align(SEG_BSS, (v)))
-
-#define H_SET_RELOCATION_SIZE(h,t,d)	(H_SET_TEXT_RELOCATION_SIZE((h),(t)),\
-					 H_SET_DATA_RELOCATION_SIZE((h),(d)))
-
-#define H_SET_TEXT_RELOCATION_SIZE(h,v)	((h)->header.a_trsize = (v))
-#define H_SET_DATA_RELOCATION_SIZE(h,v)	((h)->header.a_drsize = (v))
-#define H_SET_SYMBOL_TABLE_SIZE(h,v)	((h)->header.a_syms = (v) * 12)
-
-#define H_SET_ENTRY_POINT(h,v)		((h)->header.a_entry = (v))
-#define H_SET_STRING_SIZE(h,v)		((h)->string_table_size = (v))
-
-typedef struct
-  {
-    struct exec header;		/* a.out header */
-    long string_table_size;	/* names + '\0' + sizeof (int) */
-  }
-
-object_headers;
-
-/* line numbering stuff.  */
-#define OBJ_EMIT_LINENO(a, b, c)	{;}
-
-struct fix;
-void tc_aout_fix_to_chars PARAMS ((char *where, struct fix *fixP, relax_addressT segment_address));
-
-#endif
+#define obj_sec_sym_ok_for_reloc(SEC)	1
 
 #define obj_read_begin_hook()	{;}
 #define obj_symbol_new_hook(s)	{;}
diff --git a/gas/config/obj-bout.c b/gas/config/obj-bout.c
deleted file mode 100644
index 88ea0f1c7c69..000000000000
--- a/gas/config/obj-bout.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/* b.out object file format
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1996, 2000, 2001, 2002
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 2,
-   or (at your option) any later version.
-
-   GAS is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-   the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#include "as.h"
-#include "obstack.h"
-
-/* In: segT   Out: N_TYPE bits  */
-const short seg_N_TYPE[] =
-{
-  N_ABS,
-  N_TEXT,
-  N_DATA,
-  N_BSS,
-  N_UNDF,			/* unknown  */
-  N_UNDF,			/* error  */
-  N_UNDF,			/* expression  */
-  N_UNDF,			/* debug  */
-  N_UNDF,			/* ntv  */
-  N_UNDF,			/* ptv  */
-  N_REGISTER,			/* register  */
-};
-
-const segT N_TYPE_seg[N_TYPE + 2] =
-{				/* N_TYPE == 0x1E = 32-2  */
-  SEG_UNKNOWN,			/* N_UNDF == 0  */
-  SEG_GOOF,
-  SEG_ABSOLUTE,			/* N_ABS == 2  */
-  SEG_GOOF,
-  SEG_TEXT,			/* N_TEXT == 4  */
-  SEG_GOOF,
-  SEG_DATA,			/* N_DATA == 6  */
-  SEG_GOOF,
-  SEG_BSS,			/* N_BSS == 8  */
-  SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_REGISTER,			/* dummy N_REGISTER for regs = 30  */
-  SEG_GOOF,
-};
-
-static void obj_bout_line PARAMS ((int));
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  {"line", obj_bout_line, 0},	/* Source code line number.  */
-
-/* coff debugging directives.  Currently ignored silently.  */
-  {"def", s_ignore, 0},
-  {"dim", s_ignore, 0},
-  {"endef", s_ignore, 0},
-  {"ln", s_ignore, 0},
-  {"scl", s_ignore, 0},
-  {"size", s_ignore, 0},
-  {"tag", s_ignore, 0},
-  {"type", s_ignore, 0},
-  {"val", s_ignore, 0},
-
-/* other stuff we don't handle */
-  {"ABORT", s_ignore, 0},
-  {"ident", s_ignore, 0},
-
-  {NULL, NULL, 0}		/* End sentinel.  */
-};
-
-/* Relocation.  */
-
-/* Crawl along a fixS chain. Emit the segment's relocations.  */
-
-void
-obj_emit_relocations (where, fixP, segment_address_in_file)
-     char **where;
-     fixS *fixP;		/* Fixup chain for this segment.  */
-     relax_addressT segment_address_in_file;
-{
-  for (; fixP; fixP = fixP->fx_next)
-    {
-      if (fixP->fx_done == 0
-	  || fixP->fx_r_type != NO_RELOC)
-	{
-	  symbolS *sym;
-
-	  sym = fixP->fx_addsy;
-	  while (sym->sy_value.X_op == O_symbol
-		 && (! S_IS_DEFINED (sym) || S_IS_COMMON (sym)))
-	    sym = sym->sy_value.X_add_symbol;
-	  fixP->fx_addsy = sym;
-
-	  tc_bout_fix_to_chars (*where, fixP, segment_address_in_file);
-	  *where += sizeof (struct relocation_info);
-	}			/* if there's a symbol  */
-    }				/* for each fixup  */
-}
-
-/* Aout file generation & utilities .  */
-
-/* Convert a lvalue to machine dependent data.  */
-
-void
-obj_header_append (where, headers)
-     char **where;
-     object_headers *headers;
-{
-  /* Always leave in host byte order.  */
-
-  headers->header.a_talign = section_alignment[SEG_TEXT];
-
-  /* Force to at least 2.  */
-  if (headers->header.a_talign < 2)
-    {
-      headers->header.a_talign = 2;
-    }
-
-  headers->header.a_dalign = section_alignment[SEG_DATA];
-  headers->header.a_balign = section_alignment[SEG_BSS];
-
-  headers->header.a_tload = 0;
-  headers->header.a_dload =
-    md_section_align (SEG_DATA, H_GET_TEXT_SIZE (headers));
-
-  headers->header.a_relaxable = linkrelax;
-
-#ifdef CROSS_COMPILE
-  md_number_to_chars (*where, headers->header.a_magic, sizeof (headers->header.a_magic));
-  *where += sizeof (headers->header.a_magic);
-  md_number_to_chars (*where, headers->header.a_text, sizeof (headers->header.a_text));
-  *where += sizeof (headers->header.a_text);
-  md_number_to_chars (*where, headers->header.a_data, sizeof (headers->header.a_data));
-  *where += sizeof (headers->header.a_data);
-  md_number_to_chars (*where, headers->header.a_bss, sizeof (headers->header.a_bss));
-  *where += sizeof (headers->header.a_bss);
-  md_number_to_chars (*where, headers->header.a_syms, sizeof (headers->header.a_syms));
-  *where += sizeof (headers->header.a_syms);
-  md_number_to_chars (*where, headers->header.a_entry, sizeof (headers->header.a_entry));
-  *where += sizeof (headers->header.a_entry);
-  md_number_to_chars (*where, headers->header.a_trsize, sizeof (headers->header.a_trsize));
-  *where += sizeof (headers->header.a_trsize);
-  md_number_to_chars (*where, headers->header.a_drsize, sizeof (headers->header.a_drsize));
-  *where += sizeof (headers->header.a_drsize);
-  md_number_to_chars (*where, headers->header.a_tload, sizeof (headers->header.a_tload));
-  *where += sizeof (headers->header.a_tload);
-  md_number_to_chars (*where, headers->header.a_dload, sizeof (headers->header.a_dload));
-  *where += sizeof (headers->header.a_dload);
-  md_number_to_chars (*where, headers->header.a_talign, sizeof (headers->header.a_talign));
-  *where += sizeof (headers->header.a_talign);
-  md_number_to_chars (*where, headers->header.a_dalign, sizeof (headers->header.a_dalign));
-  *where += sizeof (headers->header.a_dalign);
-  md_number_to_chars (*where, headers->header.a_balign, sizeof (headers->header.a_balign));
-  *where += sizeof (headers->header.a_balign);
-  md_number_to_chars (*where, headers->header.a_relaxable, sizeof (headers->header.a_relaxable));
-  *where += sizeof (headers->header.a_relaxable);
-#else /* ! CROSS_COMPILE */
-  append (where, (char *) &headers->header, sizeof (headers->header));
-#endif /* ! CROSS_COMPILE */
-}
-
-void
-obj_symbol_to_chars (where, symbolP)
-     char **where;
-     symbolS *symbolP;
-{
-  md_number_to_chars ((char *) &(S_GET_OFFSET (symbolP)),
-		      S_GET_OFFSET (symbolP),
-		      sizeof (S_GET_OFFSET (symbolP)));
-
-  md_number_to_chars ((char *) &(S_GET_DESC (symbolP)),
-		      S_GET_DESC (symbolP),
-		      sizeof (S_GET_DESC (symbolP)));
-
-  md_number_to_chars ((char *) &symbolP->sy_symbol.n_value,
-		      S_GET_VALUE (symbolP),
-		      sizeof (symbolP->sy_symbol.n_value));
-
-  append (where, (char *) &symbolP->sy_symbol, sizeof (obj_symbol_type));
-}
-
-void
-obj_emit_symbols (where, symbol_rootP)
-     char **where;
-     symbolS *symbol_rootP;
-{
-  symbolS *symbolP;
-
-  /* Emit all symbols left in the symbol chain.  */
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Used to save the offset of the name.  It is used to point to
-	 the string in memory but must be a file offset.  */
-      char *temp;
-
-      temp = S_GET_NAME (symbolP);
-      S_SET_OFFSET (symbolP, symbolP->sy_name_offset);
-
-      /* Any symbol still undefined and is not a dbg symbol is made N_EXT.  */
-      if (!S_IS_DEBUG (symbolP) && !S_IS_DEFINED (symbolP))
-	S_SET_EXTERNAL (symbolP);
-
-      obj_symbol_to_chars (where, symbolP);
-      S_SET_NAME (symbolP, temp);
-    }
-}
-
-void
-obj_symbol_new_hook (symbolP)
-     symbolS *symbolP;
-{
-  S_SET_OTHER (symbolP, 0);
-  S_SET_DESC (symbolP, 0);
-}
-
-static void
-obj_bout_line (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  /* Assume delimiter is part of expression.  */
-  /* BSD4.2 as fails with delightful bug, so we are not being
-     incompatible here.  */
-  new_logical_line ((char *) NULL, (int) (get_absolute_expression ()));
-  demand_empty_rest_of_line ();
-}
-
-void
-obj_read_begin_hook ()
-{
-}
-
-void
-obj_crawl_symbol_chain (headers)
-     object_headers *headers;
-{
-  symbolS **symbolPP;
-  symbolS *symbolP;
-  int symbol_number = 0;
-
-  tc_crawl_symbol_chain (headers);
-
-  symbolPP = &symbol_rootP;	/* -> last symbol chain link.  */
-  while ((symbolP = *symbolPP) != NULL)
-    {
-      if (flag_readonly_data_in_text && (S_GET_SEGMENT (symbolP) == SEG_DATA))
-	{
-	  S_SET_SEGMENT (symbolP, SEG_TEXT);
-	}			/* if pushing data into text  */
-
-      resolve_symbol_value (symbolP);
-
-      /* Skip symbols which were equated to undefined or common
-	 symbols.  */
-      if (symbolP->sy_value.X_op == O_symbol
-	  && (! S_IS_DEFINED (symbolP) || S_IS_COMMON (symbolP)))
-	{
-	  *symbolPP = symbol_next (symbolP);
-	  continue;
-	}
-
-      /* OK, here is how we decide which symbols go out into the
-	 brave new symtab.  Symbols that do are:
-
-	 * symbols with no name (stabd's?)
-	 * symbols with debug info in their N_TYPE
-
-	 Symbols that don't are:
-	 * symbols that are registers
-	 * symbols with \1 as their 3rd character (numeric labels)
-	 * "local labels" as defined by S_LOCAL_NAME(name)
-	 if the -L switch was passed to gas.
-
-	 All other symbols are output.  We complain if a deleted
-	 symbol was marked external.  */
-
-      if (1
-	  && !S_IS_REGISTER (symbolP)
-	  && (!S_GET_NAME (symbolP)
-	      || S_IS_DEBUG (symbolP)
-#ifdef TC_I960
-      /* FIXME-SOON this ifdef seems highly dubious to me.  xoxorich.  */
-	      || !S_IS_DEFINED (symbolP)
-	      || S_IS_EXTERNAL (symbolP)
-#endif /* TC_I960 */
-	      || (S_GET_NAME (symbolP)[0] != '\001'
-		  && (flag_keep_locals || !S_LOCAL_NAME (symbolP)))))
-	{
-	  symbolP->sy_number = symbol_number++;
-
-	  /* The + 1 after strlen account for the \0 at the end of
-	     each string.  */
-	  if (!S_IS_STABD (symbolP))
-	    {
-	      /* Ordinary case.  */
-	      symbolP->sy_name_offset = string_byte_count;
-	      string_byte_count += strlen (S_GET_NAME (symbolP)) + 1;
-	    }
-	  else			/* .Stabd case.  */
-	    symbolP->sy_name_offset = 0;
-	  symbolPP = &(symbolP->sy_next);
-	}
-      else
-	{
-	  if (S_IS_EXTERNAL (symbolP) || !S_IS_DEFINED (symbolP))
-	    {
-	      as_bad (_("Local symbol %s never defined"),
-		      S_GET_NAME (symbolP));
-	    }			/* Oops.  */
-
-	  /* Unhook it from the chain.  */
-	  *symbolPP = symbol_next (symbolP);
-	}			/* if this symbol should be in the output  */
-    }				/* for each symbol  */
-
-  H_SET_SYMBOL_TABLE_SIZE (headers, symbol_number);
-}
-
-/* Find strings by crawling along symbol table chain.  */
-
-void
-obj_emit_strings (where)
-     char **where;
-{
-  symbolS *symbolP;
-
-#ifdef CROSS_COMPILE
-  /* Gotta do md_ byte-ordering stuff for string_byte_count first - KWK */
-  md_number_to_chars (*where, string_byte_count, sizeof (string_byte_count));
-  *where += sizeof (string_byte_count);
-#else /* CROSS_COMPILE */
-  append (where, (char *) &string_byte_count,
-	  (unsigned long) sizeof (string_byte_count));
-#endif /* CROSS_COMPILE */
-
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      if (S_GET_NAME (symbolP))
-	append (where, S_GET_NAME (symbolP),
-		(unsigned long) (strlen (S_GET_NAME (symbolP)) + 1));
-    }				/* Walk symbol chain.  */
-}
diff --git a/gas/config/obj-bout.h b/gas/config/obj-bout.h
deleted file mode 100644
index aaa9d9beb7bc..000000000000
--- a/gas/config/obj-bout.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/* b.out object file format
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000,
-   2002, 2003 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 2,
-   or (at your option) any later version.
-
-   GAS is distributed in the hope that it will be useful, but
-   WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-   the GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public
-   License along with GAS; see the file COPYING.  If not, write
-   to the Free Software Foundation, 59 Temple Place - Suite 330, Cambridge, MA
-   02139, USA.  */
-
-/*
- * This file is a modified version of 'a.out.h'.  It is to be used in all GNU
- * tools modified to support the i80960 b.out format (or tools that operate on
- * object files created by such tools).
- *
- * All i80960 development is done in a CROSS-DEVELOPMENT environment.  I.e.,
- * object code is generated on, and executed under the direction of a symbolic
- * debugger running on, a host system.  We do not want to be subject to the
- * vagaries of which host it is or whether it supports COFF or a.out format, or
- * anything else.  We DO want to:
- *
- *	o always generate the same format object files, regardless of host.
- *
- *	o have an 'a.out' header that we can modify for our own purposes
- *	  (the 80960 is typically an embedded processor and may require
- *	  enhanced linker support that the normal a.out.h header can't
- *	  accommodate).
- *
- * As for byte-ordering, the following rules apply:
- *
- *	o Text and data that is actually downloaded to the target is always
- *	  in i80960 (little-endian) order.
- *
- *	o All other numbers (in the header, symbols, relocation directives)
- *	  are in host byte-order:  object files CANNOT be lifted from a
- *	  little-end host and used on a big-endian (or vice versa) without
- *	  modification.
- * ==> THIS IS NO LONGER TRUE USING BFD.  WE CAN GENERATE ANY BYTE ORDER
- *     FOR THE HEADER, AND READ ANY BYTE ORDER.  PREFERENCE WOULD BE TO
- *     USE LITTLE-ENDIAN BYTE ORDER THROUGHOUT, REGARDLESS OF HOST.  <==
- *
- *	o The downloader ('comm960') takes care to generate a pseudo-header
- *	  with correct (i80960) byte-ordering before shipping text and data
- *	  off to the NINDY monitor in the target systems.  Symbols and
- *	  relocation info are never sent to the target.
- */
-
-#define OBJ_BOUT 1
-
-#define OUTPUT_FLAVOR bfd_target_aout_flavour
-
-#include "targ-cpu.h"
-
-#define OBJ_DEFAULT_OUTPUT_FILE_NAME	"b.out"
-
-extern const short seg_N_TYPE[];
-extern const segT N_TYPE_seg[];
-
-#define BMAGIC	0415
-/* We don't accept the following (see N_BADMAG macro).
- * They're just here so GNU code will compile.
- */
-#define	OMAGIC	0407		/* old impure format */
-#define	NMAGIC	0410		/* read-only text */
-#define	ZMAGIC	0413		/* demand load format */
-
-#ifndef DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE	(BMAGIC)
-#endif /* DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE */
-
-/* FILE HEADER
- *	All 'lengths' are given as a number of bytes.
- *	All 'alignments' are for relinkable files only;  an alignment of
- *		'n' indicates the corresponding segment must begin at an
- *		address that is a multiple of (2**n).
- */
-struct exec
-  {
-    /* Standard stuff */
-    unsigned long a_magic;	/* Identifies this as a b.out file	*/
-    unsigned long a_text;	/* Length of text			*/
-    unsigned long a_data;	/* Length of data			*/
-    unsigned long a_bss;	/* Length of runtime uninitialized data area */
-    unsigned long a_syms;	/* Length of symbol table		*/
-    unsigned long a_entry;	/* Runtime start address		*/
-    unsigned long a_trsize;	/* Length of text relocation info	*/
-    unsigned long a_drsize;	/* Length of data relocation info	*/
-
-    /* Added for i960 */
-    unsigned long a_tload;	/* Text runtime load address		*/
-    unsigned long a_dload;	/* Data runtime load address		*/
-    unsigned char a_talign;	/* Alignment of text segment		*/
-    unsigned char a_dalign;	/* Alignment of data segment		*/
-    unsigned char a_balign;	/* Alignment of bss segment		*/
-    unsigned char a_relaxable;	/* Contains enough info to relax     */
-  };
-
-#define N_BADMAG(x)	(((x).a_magic)!=BMAGIC)
-#define N_TXTOFF(x)	( sizeof (struct exec) )
-#define N_DATOFF(x)	( N_TXTOFF(x) + (x).a_text )
-#define N_TROFF(x)	( N_DATOFF(x) + (x).a_data )
-#define N_DROFF(x)	( N_TROFF(x) + (x).a_trsize )
-#define N_SYMOFF(x)	( N_DROFF(x) + (x).a_drsize )
-#define N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
-
-/* A single entry in the symbol table
- */
-struct nlist
-  {
-    union
-      {
-	char *n_name;
-	struct nlist *n_next;
-	long n_strx;		/* Index into string table	*/
-      }
-    n_un;
-    unsigned char n_type;	/* See below				*/
-    char n_other;		/* Used in i80960 support -- see below	*/
-    short n_desc;
-    unsigned long n_value;
-  };
-
-typedef struct nlist obj_symbol_type;
-
-/* Legal values of n_type
- */
-#define N_UNDF	0		/* Undefined symbol	*/
-#define N_ABS	2		/* Absolute symbol	*/
-#define N_TEXT	4		/* Text symbol		*/
-#define N_DATA	6		/* Data symbol		*/
-#define N_BSS	8		/* BSS symbol		*/
-#define N_FN	31		/* Filename symbol	*/
-
-#define N_EXT	1		/* External symbol (OR'd in with one of above)	*/
-#define N_TYPE	036		/* Mask for all the type bits			*/
-#define N_STAB	0340		/* Mask for all bits used for SDB entries 	*/
-
-#ifndef CUSTOM_RELOC_FORMAT
-struct relocation_info
-  {
-    int r_address;		/* File address of item to be relocated	*/
-    unsigned
-      r_index:24,		/* Index of symbol on which relocation is based*/
-      r_pcrel:1,		/* 1 => relocate PC-relative; else absolute
-		 *	On i960, pc-relative implies 24-bit
-		 *	address, absolute implies 32-bit.
-		 */
-      r_length:2,		/* Number of bytes to relocate:
-		 *	0 => 1 byte
-		 *	1 => 2 bytes
-		 *	2 => 4 bytes -- only value used for i960
-		 */
-      r_extern:1, r_bsr:1,	/* Something for the GNU NS32K assembler */
-      r_disp:1,			/* Something for the GNU NS32K assembler */
-      r_callj:1,		/* 1 if relocation target is an i960 'callj' */
-      nuthin:1;			/* Unused				*/
-  };
-
-#endif /* CUSTOM_RELOC_FORMAT */
-
-/*
- *  Macros to extract information from a symbol table entry.
- *  This syntactic indirection allows independence regarding a.out or coff.
- *  The argument (s) of all these macros is a pointer to a symbol table entry.
- */
-
-/* Predicates */
-/* True if the symbol is external */
-#define S_IS_EXTERNAL(s)	((s)->sy_symbol.n_type & N_EXT)
-
-/* True if symbol has been defined, ie is in N_{TEXT,DATA,BSS,ABS} or N_EXT */
-#define S_IS_DEFINED(s)		((S_GET_TYPE(s) != N_UNDF) || (S_GET_DESC(s) != 0))
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) \
-  (!SEG_NORMAL (S_GET_SEGMENT (s)))
-
-#define S_IS_COMMON(s) \
-  (S_GET_TYPE (s) == N_UNDF && S_GET_VALUE (s) != 0)
-
-#define S_IS_REGISTER(s)	((s)->sy_symbol.n_type == N_REGISTER)
-
-/* True if a debug special symbol entry */
-#define S_IS_DEBUG(s)		((s)->sy_symbol.n_type & N_STAB)
-/* True if a symbol is local symbol name */
-#define S_IS_LOCAL(s) 					\
-  ((S_GET_NAME (s) 					\
-    && !S_IS_DEBUG (s) 					\
-    && (strchr (S_GET_NAME (s), '\001') != NULL		\
-        || strchr (S_GET_NAME (s), '\002') != NULL	\
-        || (S_LOCAL_NAME(s) && !flag_keep_locals)))	\
-   || (flag_strip_local_absolute			\
-       && !S_IS_EXTERNAL(s)				\
-       && S_GET_SEGMENT(s) == absolute_section))
-/* True if a symbol is not defined in this file */
-#define S_IS_EXTERN(s)		((s)->sy_symbol.n_type & N_EXT)
-/* True if the symbol has been generated because of a .stabd directive */
-#define S_IS_STABD(s)		(S_GET_NAME(s) == NULL)
-
-/* Accessors */
-/* The name of the symbol */
-#define S_GET_NAME(s)		((s)->sy_symbol.n_un.n_name)
-/* The pointer to the string table */
-#define S_GET_OFFSET(s)		((s)->sy_symbol.n_un.n_strx)
-/* The type of the symbol */
-#define S_GET_TYPE(s)		((s)->sy_symbol.n_type & N_TYPE)
-/* The numeric value of the segment */
-#define S_GET_SEGMENT(s)	(N_TYPE_seg[S_GET_TYPE(s)])
-/* The n_other expression value */
-#define S_GET_OTHER(s)		((s)->sy_symbol.n_other)
-/* The n_desc expression value */
-#define S_GET_DESC(s)		((s)->sy_symbol.n_desc)
-
-/* Modifiers */
-/* Assume that a symbol cannot be simultaneously in more than on segment */
-/* set segment */
-#define S_SET_SEGMENT(s,seg)	((s)->sy_symbol.n_type &= ~N_TYPE,(s)->sy_symbol.n_type|=SEGMENT_TO_SYMBOL_TYPE(seg))
-/* The symbol is external */
-#define S_SET_EXTERNAL(s)	((s)->sy_symbol.n_type |= N_EXT)
-/* The symbol is not external */
-#define S_CLEAR_EXTERNAL(s)	((s)->sy_symbol.n_type &= ~N_EXT)
-/* Set the name of the symbol */
-#define S_SET_NAME(s,v)		((s)->sy_symbol.n_un.n_name = (v))
-/* Set the offset in the string table */
-#define S_SET_OFFSET(s,v)	((s)->sy_symbol.n_un.n_strx = (v))
-/* Set the n_other expression value */
-#define S_SET_OTHER(s,v)	((s)->sy_symbol.n_other = (v))
-/* Set the n_desc expression value */
-#define S_SET_DESC(s,v)		((s)->sy_symbol.n_desc = (v))
-/* Set the n_type value */
-#define S_SET_TYPE(s,v)		((s)->sy_symbol.n_type = (v))
-
-/* File header macro and type definition */
-
-#define H_GET_FILE_SIZE(h)	(sizeof (struct exec) + \
-				 H_GET_TEXT_SIZE(h) + H_GET_DATA_SIZE(h) + \
-				 H_GET_SYMBOL_TABLE_SIZE(h) + \
-				 H_GET_TEXT_RELOCATION_SIZE(h) + \
-				 H_GET_DATA_RELOCATION_SIZE(h) + \
-				 (h)->string_table_size)
-
-#define H_GET_HEADER_SIZE(h)		(sizeof (struct exec))
-#define H_GET_TEXT_SIZE(h)		((h)->header.a_text)
-#define H_GET_DATA_SIZE(h)		((h)->header.a_data)
-#define H_GET_BSS_SIZE(h)		((h)->header.a_bss)
-#define H_GET_TEXT_RELOCATION_SIZE(h)	((h)->header.a_trsize)
-#define H_GET_DATA_RELOCATION_SIZE(h)	((h)->header.a_drsize)
-#define H_GET_SYMBOL_TABLE_SIZE(h)	((h)->header.a_syms)
-#define H_GET_MAGIC_NUMBER(h)		((h)->header.a_info)
-#define H_GET_ENTRY_POINT(h)		((h)->header.a_entry)
-#define H_GET_STRING_SIZE(h)		((h)->string_table_size)
-#define H_GET_LINENO_SIZE(h)		(0)
-
-#ifdef EXEC_MACHINE_TYPE
-#define H_GET_MACHINE_TYPE(h)		((h)->header.a_machtype)
-#endif /* EXEC_MACHINE_TYPE */
-#ifdef EXEC_VERSION
-#define H_GET_VERSION(h)		((h)->header.a_version)
-#endif /* EXEC_VERSION */
-
-#define H_SET_TEXT_SIZE(h,v)		((h)->header.a_text = (v))
-#define H_SET_DATA_SIZE(h,v)		((h)->header.a_data = (v))
-#define H_SET_BSS_SIZE(h,v)		((h)->header.a_bss = (v))
-
-#define H_SET_RELOCATION_SIZE(h,t,d)	(H_SET_TEXT_RELOCATION_SIZE((h),(t)),\
-					 H_SET_DATA_RELOCATION_SIZE((h),(d)))
-
-#define H_SET_TEXT_RELOCATION_SIZE(h,v)	((h)->header.a_trsize = (v))
-#define H_SET_DATA_RELOCATION_SIZE(h,v)	((h)->header.a_drsize = (v))
-#define H_SET_SYMBOL_TABLE_SIZE(h,v)	((h)->header.a_syms = (v) * \
-					 sizeof (struct nlist))
-
-#define H_SET_MAGIC_NUMBER(h,v)		((h)->header.a_magic = (v))
-
-#define H_SET_ENTRY_POINT(h,v)		((h)->header.a_entry = (v))
-#define H_SET_STRING_SIZE(h,v)		((h)->string_table_size = (v))
-#ifdef EXEC_MACHINE_TYPE
-#define H_SET_MACHINE_TYPE(h,v)		((h)->header.a_machtype = (v))
-#endif /* EXEC_MACHINE_TYPE */
-#ifdef EXEC_VERSION
-#define H_SET_VERSION(h,v)		((h)->header.a_version = (v))
-#endif /* EXEC_VERSION */
-
-typedef struct
-  {
-    struct exec header;		/* a.out header */
-    long string_table_size;	/* names + '\0' + sizeof (int) */
-  }
-
-object_headers;
-
-/* unused hooks.  */
-#define OBJ_EMIT_LINENO(a, b, c)	{;}
-#define obj_pre_write_hook(a)		{;}
-
-#if __STDC__
-struct fix;
-#endif
-extern void tc_aout_fix_to_chars PARAMS ((char *where,
-					  struct fix *fixP,
-					  relax_addressT segment_address));
-extern void tc_bout_fix_to_chars PARAMS ((char *where,
-					  struct fix *fixP,
-					  relax_addressT segment_address));
-
-#define AOUT_STABS
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index bd08c2b5f8b7..a5a76ff3da0a 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -1,6 +1,6 @@
 /* coff object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define OBJ_HEADER "obj-coff.h"
 
@@ -26,14 +26,21 @@
 #include "obstack.h"
 #include "subsegs.h"
 
+#ifdef TE_PE
+#include "coff/pe.h"
+#endif
+
+#define streq(a,b)     (strcmp ((a), (b)) == 0)
+#define strneq(a,b,n)  (strncmp ((a), (b), (n)) == 0)
+
 /* I think this is probably always correct.  */
 #ifndef KEEP_RELOC_INFO
 #define KEEP_RELOC_INFO
 #endif
 
-/* The BFD_ASSEMBLER version of obj_coff_section will use this macro to set
-   a new section's attributes when a directive has no valid flags or the
-   "w" flag is used. This default should be appropriate for most.  */
+/* obj_coff_section will use this macro to set a new section's
+   attributes when a directive has no valid flags or the "w" flag is
+   used.  This default should be appropriate for most.  */
 #ifndef TC_COFF_SECTION_DEFAULT_ATTRIBUTES
 #define TC_COFF_SECTION_DEFAULT_ATTRIBUTES (SEC_LOAD | SEC_DATA)
 #endif
@@ -41,6 +48,10 @@
 /* This is used to hold the symbol built by a sequence of pseudo-ops
    from .def and .endef.  */
 static symbolS *def_symbol_in_progress;
+#ifdef TE_PE
+/* PE weak alternate symbols begin with this string.  */
+static const char weak_altprefix[] = ".weak.";
+#endif /* TE_PE */
 
 typedef struct
   {
@@ -52,48 +63,23 @@ typedef struct
   }
 stack;
 
-static stack *stack_init PARAMS ((unsigned long, unsigned long));
-static char *stack_push PARAMS ((stack *, char *));
-static char *stack_pop PARAMS ((stack *));
-static void tag_init PARAMS ((void));
-static void tag_insert PARAMS ((const char *, symbolS *));
-static symbolS *tag_find PARAMS ((char *));
-static symbolS *tag_find_or_make PARAMS ((char *));
-static void obj_coff_bss PARAMS ((int));
-static void obj_coff_weak PARAMS ((int));
-const char *s_get_name PARAMS ((symbolS * s));
-static void obj_coff_ln PARAMS ((int));
-static void obj_coff_def PARAMS ((int));
-static void obj_coff_endef PARAMS ((int));
-static void obj_coff_dim PARAMS ((int));
-static void obj_coff_line PARAMS ((int));
-static void obj_coff_size PARAMS ((int));
-static void obj_coff_scl PARAMS ((int));
-static void obj_coff_tag PARAMS ((int));
-static void obj_coff_val PARAMS ((int));
-static void obj_coff_type PARAMS ((int));
-static void obj_coff_ident PARAMS ((int));
-#ifdef BFD_ASSEMBLER
-static void obj_coff_loc PARAMS((int));
-#endif
 
-/* stack stuff */
+/* Stack stuff.  */
 
 static stack *
-stack_init (chunk_size, element_size)
-     unsigned long chunk_size;
-     unsigned long element_size;
+stack_init (unsigned long chunk_size,
+	    unsigned long element_size)
 {
   stack *st;
 
-  st = (stack *) malloc (sizeof (stack));
+  st = malloc (sizeof (* st));
   if (!st)
-    return 0;
+    return NULL;
   st->data = malloc (chunk_size);
   if (!st->data)
     {
       free (st);
-      return 0;
+      return NULL;
     }
   st->pointer = 0;
   st->size = chunk_size;
@@ -102,27 +88,14 @@ stack_init (chunk_size, element_size)
   return st;
 }
 
-#if 0
-/* Not currently used.  */
-static void
-stack_delete (st)
-     stack *st;
-{
-  free (st->data);
-  free (st);
-}
-#endif
-
 static char *
-stack_push (st, element)
-     stack *st;
-     char *element;
+stack_push (stack *st, char *element)
 {
   if (st->pointer + st->element_size >= st->size)
     {
       st->size += st->chunk_size;
-      if ((st->data = xrealloc (st->data, st->size)) == (char *) 0)
-	return (char *) 0;
+      if ((st->data = xrealloc (st->data, st->size)) == NULL)
+	return NULL;
     }
   memcpy (st->data + st->pointer, element, st->element_size);
   st->pointer += st->element_size;
@@ -130,58 +103,45 @@ stack_push (st, element)
 }
 
 static char *
-stack_pop (st)
-     stack *st;
+stack_pop (stack *st)
 {
   if (st->pointer < st->element_size)
     {
       st->pointer = 0;
-      return (char *) 0;
+      return NULL;
     }
   st->pointer -= st->element_size;
   return st->data + st->pointer;
 }
 
-/*
- * Maintain a list of the tagnames of the structures.
- */
+/* Maintain a list of the tagnames of the structures.  */
 
 static struct hash_control *tag_hash;
 
 static void
-tag_init ()
+tag_init (void)
 {
   tag_hash = hash_new ();
 }
 
 static void
-tag_insert (name, symbolP)
-     const char *name;
-     symbolS *symbolP;
+tag_insert (const char *name, symbolS *symbolP)
 {
   const char *error_string;
 
   if ((error_string = hash_jam (tag_hash, name, (char *) symbolP)))
-    {
-      as_fatal (_("Inserting \"%s\" into structure table failed: %s"),
-		name, error_string);
-    }
+    as_fatal (_("Inserting \"%s\" into structure table failed: %s"),
+	      name, error_string);
 }
 
 static symbolS *
-tag_find (name)
-     char *name;
+tag_find (char *name)
 {
-#ifdef STRIP_UNDERSCORE
-  if (*name == '_')
-    name++;
-#endif /* STRIP_UNDERSCORE */
   return (symbolS *) hash_find (tag_hash, name);
 }
 
 static symbolS *
-tag_find_or_make (name)
-     char *name;
+tag_find_or_make (char *name)
 {
   symbolS *symbolP;
 
@@ -191,10 +151,8 @@ tag_find_or_make (name)
 			    0, &zero_address_frag);
 
       tag_insert (S_GET_NAME (symbolP), symbolP);
-#ifdef BFD_ASSEMBLER
       symbol_table_insert (symbolP);
-#endif
-    }				/* not found */
+    }
 
   return symbolP;
 }
@@ -203,8 +161,7 @@ tag_find_or_make (name)
    compatibility with earlier versions of gas.  */
 
 static void
-obj_coff_bss (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_bss (int ignore ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer == '\n')
     subseg_new (".bss", get_absolute_expression ());
@@ -212,67 +169,20 @@ obj_coff_bss (ignore)
     s_lcomm (0);
 }
 
-/* Handle .weak.  This is a GNU extension.  */
-
-static void
-obj_coff_weak (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  char *name;
-  int c;
-  symbolS *symbolP;
-
-  do
-    {
-      name = input_line_pointer;
-      c = get_symbol_end ();
-      symbolP = symbol_find_or_make (name);
-      *input_line_pointer = c;
-      SKIP_WHITESPACE ();
-
-#if defined BFD_ASSEMBLER || defined S_SET_WEAK
-      S_SET_WEAK (symbolP);
-#endif
-
-#ifdef TE_PE
-      S_SET_STORAGE_CLASS (symbolP, C_NT_WEAK);
-#else
-      S_SET_STORAGE_CLASS (symbolP, C_WEAKEXT);
-#endif
-
-      if (c == ',')
-	{
-	  input_line_pointer++;
-	  SKIP_WHITESPACE ();
-	  if (*input_line_pointer == '\n')
-	    c = '\n';
-	}
-    }
-  while (c == ',');
-
-  demand_empty_rest_of_line ();
-}
-
-#ifdef BFD_ASSEMBLER
-
-static segT fetch_coff_debug_section PARAMS ((void));
-static void SA_SET_SYM_TAGNDX PARAMS ((symbolS *, symbolS *));
-static int S_GET_DATA_TYPE PARAMS ((symbolS *));
-void c_symbol_merge PARAMS ((symbolS *, symbolS *));
-static void add_lineno PARAMS ((fragS *, addressT, int));
-
 #define GET_FILENAME_STRING(X) \
-((char*) (&((X)->sy_symbol.ost_auxent->x_file.x_n.x_offset))[1])
+  ((char *) (&((X)->sy_symbol.ost_auxent->x_file.x_n.x_offset))[1])
 
 /* @@ Ick.  */
 static segT
-fetch_coff_debug_section ()
+fetch_coff_debug_section (void)
 {
   static segT debug_section;
+
   if (!debug_section)
     {
       const asymbol *s;
-      s = bfd_make_debug_symbol (stdoutput, (char *) 0, 0);
+
+      s = bfd_make_debug_symbol (stdoutput, NULL, 0);
       assert (s != 0);
       debug_section = s->section;
     }
@@ -280,9 +190,7 @@ fetch_coff_debug_section ()
 }
 
 void
-SA_SET_SYM_ENDNDX (sym, val)
-     symbolS *sym;
-     symbolS *val;
+SA_SET_SYM_ENDNDX (symbolS *sym, symbolS *val)
 {
   combined_entry_type *entry, *p;
 
@@ -293,9 +201,7 @@ SA_SET_SYM_ENDNDX (sym, val)
 }
 
 static void
-SA_SET_SYM_TAGNDX (sym, val)
-     symbolS *sym;
-     symbolS *val;
+SA_SET_SYM_TAGNDX (symbolS *sym, symbolS *val)
 {
   combined_entry_type *entry, *p;
 
@@ -306,32 +212,26 @@ SA_SET_SYM_TAGNDX (sym, val)
 }
 
 static int
-S_GET_DATA_TYPE (sym)
-     symbolS *sym;
+S_GET_DATA_TYPE (symbolS *sym)
 {
   return coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_type;
 }
 
 int
-S_SET_DATA_TYPE (sym, val)
-     symbolS *sym;
-     int val;
+S_SET_DATA_TYPE (symbolS *sym, int val)
 {
   coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_type = val;
   return val;
 }
 
 int
-S_GET_STORAGE_CLASS (sym)
-     symbolS *sym;
+S_GET_STORAGE_CLASS (symbolS *sym)
 {
   return coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_sclass;
 }
 
 int
-S_SET_STORAGE_CLASS (sym, val)
-     symbolS *sym;
-     int val;
+S_SET_STORAGE_CLASS (symbolS *sym, int val)
 {
   coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_sclass = val;
   return val;
@@ -339,35 +239,28 @@ S_SET_STORAGE_CLASS (sym, val)
 
 /* Merge a debug symbol containing debug information into a normal symbol.  */
 
-void
-c_symbol_merge (debug, normal)
-     symbolS *debug;
-     symbolS *normal;
+static void
+c_symbol_merge (symbolS *debug, symbolS *normal)
 {
   S_SET_DATA_TYPE (normal, S_GET_DATA_TYPE (debug));
   S_SET_STORAGE_CLASS (normal, S_GET_STORAGE_CLASS (debug));
 
   if (S_GET_NUMBER_AUXILIARY (debug) > S_GET_NUMBER_AUXILIARY (normal))
-    {
-      /* take the most we have */
-      S_SET_NUMBER_AUXILIARY (normal, S_GET_NUMBER_AUXILIARY (debug));
-    }
+    /* Take the most we have.  */
+    S_SET_NUMBER_AUXILIARY (normal, S_GET_NUMBER_AUXILIARY (debug));
 
   if (S_GET_NUMBER_AUXILIARY (debug) > 0)
-    {
-      /* Move all the auxiliary information.  */
-      memcpy (SYM_AUXINFO (normal), SYM_AUXINFO (debug),
-	      (S_GET_NUMBER_AUXILIARY (debug)
-	       * sizeof (*SYM_AUXINFO (debug))));
-    }
+    /* Move all the auxiliary information.  */
+    memcpy (SYM_AUXINFO (normal), SYM_AUXINFO (debug),
+	    (S_GET_NUMBER_AUXILIARY (debug)
+	     * sizeof (*SYM_AUXINFO (debug))));
 
   /* Move the debug flags.  */
   SF_SET_DEBUG_FIELD (normal, SF_GET_DEBUG_FIELD (debug));
 }
 
 void
-c_dot_file_symbol (filename)
-     const char *filename;
+c_dot_file_symbol (const char *filename, int appfile ATTRIBUTE_UNUSED)
 {
   symbolS *symbolP;
 
@@ -383,24 +276,24 @@ c_dot_file_symbol (filename)
 #ifndef NO_LISTING
   {
     extern int listing;
+
     if (listing)
-      {
-	listing_source_file (filename);
-      }
+      listing_source_file (filename);
   }
 #endif
 
-  /* Make sure that the symbol is first on the symbol chain */
+  /* Make sure that the symbol is first on the symbol chain.  */
   if (symbol_rootP != symbolP)
     {
       symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
       symbol_insert (symbolP, symbol_rootP, &symbol_rootP, &symbol_lastP);
-    }				/* if not first on the list */
+    }
 }
 
-/* Line number handling */
+/* Line number handling.  */
 
-struct line_no {
+struct line_no
+{
   struct line_no *next;
   fragS *frag;
   alent l;
@@ -417,11 +310,10 @@ static symbolS *line_fsym;
 
 
 void
-coff_obj_symbol_new_hook (symbolP)
-     symbolS *symbolP;
+coff_obj_symbol_new_hook (symbolS *symbolP)
 {
   long   sz = (OBJ_COFF_MAX_AUXENTRIES + 1) * sizeof (combined_entry_type);
-  char * s  = (char *) xmalloc (sz);
+  char * s  = xmalloc (sz);
 
   memset (s, 0, sz);
   coffsymbol (symbol_get_bfdsym (symbolP))->native = (combined_entry_type *) s;
@@ -437,31 +329,36 @@ coff_obj_symbol_new_hook (symbolP)
     SF_SET_LOCAL (symbolP);
 }
 
+void
+coff_obj_symbol_clone_hook (symbolS *newsymP, symbolS *orgsymP)
+{
+  long sz = (OBJ_COFF_MAX_AUXENTRIES + 1) * sizeof (combined_entry_type);
+  combined_entry_type * s = xmalloc (sz);
+
+  memcpy (s, coffsymbol (symbol_get_bfdsym (orgsymP))->native, sz);
+  coffsymbol (symbol_get_bfdsym (newsymP))->native = s;
+
+  SF_SET (newsymP, SF_GET (orgsymP));
+}
+
 
-/*
- * Handle .ln directives.
- */
+/* Handle .ln directives.  */
 
 static symbolS *current_lineno_sym;
 static struct line_no *line_nos;
-/* @@ Blindly assume all .ln directives will be in the .text section...  */
+/* FIXME:  Blindly assume all .ln directives will be in the .text section.  */
 int coff_n_line_nos;
 
 static void
-add_lineno (frag, offset, num)
-     fragS *frag;
-     addressT offset;
-     int num;
+add_lineno (fragS * frag, addressT offset, int num)
 {
-  struct line_no *new_line =
-    (struct line_no *) xmalloc (sizeof (struct line_no));
+  struct line_no * new_line = xmalloc (sizeof (* new_line));
+
   if (!current_lineno_sym)
-    {
-      abort ();
-    }
+    abort ();
 
 #ifndef OBJ_XCOFF
-  /* The native aix assembler accepts negative line number */
+  /* The native aix assembler accepts negative line number.  */
 
   if (num <= 0)
     {
@@ -479,8 +376,7 @@ add_lineno (frag, offset, num)
 }
 
 void
-coff_add_linesym (sym)
-     symbolS *sym;
+coff_add_linesym (symbolS *sym)
 {
   if (line_nos)
     {
@@ -493,8 +389,7 @@ coff_add_linesym (sym)
 }
 
 static void
-obj_coff_ln (appline)
-     int appline;
+obj_coff_ln (int appline)
 {
   int l;
 
@@ -534,8 +429,7 @@ obj_coff_ln (appline)
    compatibility.  */
 
 static void
-obj_coff_loc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_loc (int ignore ATTRIBUTE_UNUSED)
 {
   int lineno;
 
@@ -582,8 +476,7 @@ obj_coff_loc (ignore)
 /* Handle the .ident pseudo-op.  */
 
 static void
-obj_coff_ident (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_ident (int ignore ATTRIBUTE_UNUSED)
 {
   segT current_seg = now_seg;
   subsegT current_subseg = now_subseg;
@@ -608,32 +501,26 @@ obj_coff_ident (ignore)
   subseg_set (current_seg, current_subseg);
 }
 
-/*
- *			def()
- *
- * Handle .def directives.
- *
- * One might ask : why can't we symbol_new if the symbol does not
- * already exist and fill it with debug information.  Because of
- * the C_EFCN special symbol. It would clobber the value of the
- * function symbol before we have a chance to notice that it is
- * a C_EFCN. And a second reason is that the code is more clear this
- * way. (at least I think it is :-).
- *
- */
+/* Handle .def directives.
+
+   One might ask : why can't we symbol_new if the symbol does not
+   already exist and fill it with debug information.  Because of
+   the C_EFCN special symbol. It would clobber the value of the
+   function symbol before we have a chance to notice that it is
+   a C_EFCN. And a second reason is that the code is more clear this
+   way. (at least I think it is :-).  */
 
 #define SKIP_SEMI_COLON()	while (*input_line_pointer++ != ';')
 #define SKIP_WHITESPACES()	while (*input_line_pointer == ' ' || \
-				       *input_line_pointer == '\t') \
-    input_line_pointer++;
+				       *input_line_pointer == '\t')  \
+                                  input_line_pointer++;
 
 static void
-obj_coff_def (what)
-     int what ATTRIBUTE_UNUSED;
+obj_coff_def (int what ATTRIBUTE_UNUSED)
 {
-  char name_end;		/* Char after the end of name */
-  char *symbol_name;		/* Name of the debug symbol */
-  char *symbol_name_copy;	/* Temporary copy of the name */
+  char name_end;		/* Char after the end of name.  */
+  char *symbol_name;		/* Name of the debug symbol.  */
+  char *symbol_name_copy;	/* Temporary copy of the name.  */
   unsigned int symbol_name_length;
 
   if (def_symbol_in_progress != NULL)
@@ -641,16 +528,11 @@ obj_coff_def (what)
       as_warn (_(".def pseudo-op used inside of .def/.endef: ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   SKIP_WHITESPACES ();
 
   symbol_name = input_line_pointer;
-#ifdef STRIP_UNDERSCORE
-  if (symbol_name[0] == '_' && symbol_name[1] != 0)
-    symbol_name++;
-#endif /* STRIP_UNDERSCORE */
-
   name_end = get_symbol_end ();
   symbol_name_length = strlen (symbol_name);
   symbol_name_copy = xmalloc (symbol_name_length + 1);
@@ -659,7 +541,7 @@ obj_coff_def (what)
   symbol_name_copy = tc_canonicalize_symbol_name (symbol_name_copy);
 #endif
 
-  /* Initialize the new symbol */
+  /* Initialize the new symbol.  */
   def_symbol_in_progress = symbol_make (symbol_name_copy);
   symbol_set_frag (def_symbol_in_progress, &zero_address_frag);
   S_SET_VALUE (def_symbol_in_progress, 0);
@@ -675,19 +557,17 @@ obj_coff_def (what)
 unsigned int dim_index;
 
 static void
-obj_coff_endef (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_endef (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *symbolP = NULL;
 
-  /* DIM BUG FIX sac@cygnus.com */
   dim_index = 0;
   if (def_symbol_in_progress == NULL)
     {
       as_warn (_(".endef pseudo-op used outside of .def/.endef: ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   /* Set the section number according to storage class.  */
   switch (S_GET_STORAGE_CLASS (def_symbol_in_progress))
@@ -696,7 +576,7 @@ obj_coff_endef (ignore)
     case C_ENTAG:
     case C_UNTAG:
       SF_SET_TAG (def_symbol_in_progress);
-      /* intentional fallthrough */
+      /* Fall through.  */
     case C_FILE:
     case C_TPDEF:
       SF_SET_DEBUG (def_symbol_in_progress);
@@ -705,13 +585,14 @@ obj_coff_endef (ignore)
 
     case C_EFCN:
       SF_SET_LOCAL (def_symbol_in_progress);	/* Do not emit this symbol.  */
-      /* intentional fallthrough */
+      /* Fall through.  */
     case C_BLOCK:
-      SF_SET_PROCESS (def_symbol_in_progress);	/* Will need processing before writing */
-      /* intentional fallthrough */
+      SF_SET_PROCESS (def_symbol_in_progress);	/* Will need processing before writing.  */
+      /* Fall through.  */
     case C_FCN:
       {
 	const char *name;
+
 	S_SET_SEGMENT (def_symbol_in_progress, text_section);
 
 	name = S_GET_NAME (def_symbol_in_progress);
@@ -802,7 +683,7 @@ obj_coff_endef (ignore)
 #endif
     case C_STAT:
     case C_LABEL:
-      /* Valid but set somewhere else (s_comm, s_lcomm, colon) */
+      /* Valid but set somewhere else (s_comm, s_lcomm, colon).  */
       break;
 
     default:
@@ -812,7 +693,7 @@ obj_coff_endef (ignore)
       as_warn (_("unexpected storage class %d"),
 	       S_GET_STORAGE_CLASS (def_symbol_in_progress));
       break;
-    }				/* switch on storage class */
+    }
 
   /* Now that we have built a debug symbol, try to find if we should
      merge with an existing symbol or not.  If a symbol is C_EFCN or
@@ -835,14 +716,13 @@ obj_coff_endef (ignore)
 
   if (S_GET_STORAGE_CLASS (def_symbol_in_progress) == C_EFCN
       || S_GET_STORAGE_CLASS (def_symbol_in_progress) == C_LABEL
-      || (!strcmp (bfd_get_section_name (stdoutput,
-					 S_GET_SEGMENT (def_symbol_in_progress)),
-		   "*DEBUG*")
+      || (streq (bfd_get_section_name (stdoutput,
+				       S_GET_SEGMENT (def_symbol_in_progress)),
+		 "*DEBUG*")
 	  && !SF_GET_TAG (def_symbol_in_progress))
       || S_GET_SEGMENT (def_symbol_in_progress) == absolute_section
       || ! symbol_constant_p (def_symbol_in_progress)
-      || (symbolP = symbol_find_base (S_GET_NAME (def_symbol_in_progress),
-				      DO_NOT_STRIP)) == NULL
+      || (symbolP = symbol_find (S_GET_NAME (def_symbol_in_progress))) == NULL
       || SF_GET_TAG (def_symbol_in_progress) != SF_GET_TAG (symbolP))
     {
       /* If it already is at the end of the symbol list, do nothing */
@@ -859,7 +739,7 @@ obj_coff_endef (ignore)
 	 into the old one.  This is not mandatory. The linker can
 	 handle duplicate symbols correctly. But I guess that it save
 	 a *lot* of space if the assembly file defines a lot of
-	 symbols. [loic] */
+	 symbols. [loic]  */
 
       /* The debug entry (def_symbol_in_progress) is merged into the
 	 previous definition.  */
@@ -876,7 +756,7 @@ obj_coff_endef (ignore)
 	  /* For functions, and tags, and static symbols, the symbol
 	     *must* be where the debug symbol appears.  Move the
 	     existing symbol to the current place.  */
-	  /* If it already is at the end of the symbol list, do nothing */
+	  /* If it already is at the end of the symbol list, do nothing.  */
 	  if (def_symbol_in_progress != symbol_lastP)
 	    {
 	      symbol_remove (def_symbol_in_progress, &symbol_rootP, &symbol_lastP);
@@ -889,8 +769,7 @@ obj_coff_endef (ignore)
     {
       symbolS *oldtag;
 
-      oldtag = symbol_find_base (S_GET_NAME (def_symbol_in_progress),
-				 DO_NOT_STRIP);
+      oldtag = symbol_find (S_GET_NAME (def_symbol_in_progress));
       if (oldtag == NULL || ! SF_GET_TAG (oldtag))
 	tag_insert (S_GET_NAME (def_symbol_in_progress),
 		    def_symbol_in_progress);
@@ -903,20 +782,18 @@ obj_coff_endef (ignore)
       SF_SET_PROCESS (def_symbol_in_progress);
 
       if (symbolP == NULL)
-	{
-	  /* That is, if this is the first time we've seen the
-	     function...  */
-	  symbol_table_insert (def_symbol_in_progress);
-	} /* definition follows debug */
-    } /* Create the line number entry pointing to the function being defined */
+	/* That is, if this is the first time we've seen the
+	   function.  */
+	symbol_table_insert (def_symbol_in_progress);
+
+    }
 
   def_symbol_in_progress = NULL;
   demand_empty_rest_of_line ();
 }
 
 static void
-obj_coff_dim (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_dim (int ignore ATTRIBUTE_UNUSED)
 {
   int dim_index;
 
@@ -925,7 +802,7 @@ obj_coff_dim (ignore)
       as_warn (_(".dim pseudo-op used outside of .def/.endef: ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
 
@@ -943,7 +820,7 @@ obj_coff_dim (ignore)
 
 	default:
 	  as_warn (_("badly formed .dim directive ignored"));
-	  /* intentional fallthrough */
+	  /* Fall through.  */
 	case '\n':
 	case ';':
 	  dim_index = DIMNUM;
@@ -955,8 +832,7 @@ obj_coff_dim (ignore)
 }
 
 static void
-obj_coff_line (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_line (int ignore ATTRIBUTE_UNUSED)
 {
   int this_base;
 
@@ -968,7 +844,7 @@ obj_coff_line (ignore)
     }
 
   this_base = get_absolute_expression ();
-  if (!strcmp (".bf", S_GET_NAME (def_symbol_in_progress)))
+  if (streq (".bf", S_GET_NAME (def_symbol_in_progress)))
     coff_line_base = this_base;
 
   S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
@@ -977,7 +853,7 @@ obj_coff_line (ignore)
   demand_empty_rest_of_line ();
 
 #ifndef NO_LISTING
-  if (strcmp (".bf", S_GET_NAME (def_symbol_in_progress)) == 0)
+  if (streq (".bf", S_GET_NAME (def_symbol_in_progress)))
     {
       extern int listing;
 
@@ -988,15 +864,14 @@ obj_coff_line (ignore)
 }
 
 static void
-obj_coff_size (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_size (int ignore ATTRIBUTE_UNUSED)
 {
   if (def_symbol_in_progress == NULL)
     {
       as_warn (_(".size pseudo-op used outside of .def/.endef ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
   SA_SET_SYM_SIZE (def_symbol_in_progress, get_absolute_expression ());
@@ -1004,23 +879,21 @@ obj_coff_size (ignore)
 }
 
 static void
-obj_coff_scl (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_scl (int ignore ATTRIBUTE_UNUSED)
 {
   if (def_symbol_in_progress == NULL)
     {
       as_warn (_(".scl pseudo-op used outside of .def/.endef ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   S_SET_STORAGE_CLASS (def_symbol_in_progress, get_absolute_expression ());
   demand_empty_rest_of_line ();
 }
 
 static void
-obj_coff_tag (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_tag (int ignore ATTRIBUTE_UNUSED)
 {
   char *symbol_name;
   char name_end;
@@ -1045,9 +918,7 @@ obj_coff_tag (ignore)
   SA_SET_SYM_TAGNDX (def_symbol_in_progress,
 		     tag_find_or_make (symbol_name));
   if (SA_GET_SYM_TAGNDX (def_symbol_in_progress) == 0L)
-    {
-      as_warn (_("tag not found for .tag %s"), symbol_name);
-    }				/* not defined */
+    as_warn (_("tag not found for .tag %s"), symbol_name);
 
   SF_SET_TAGGED (def_symbol_in_progress);
   *input_line_pointer = name_end;
@@ -1056,37 +927,33 @@ obj_coff_tag (ignore)
 }
 
 static void
-obj_coff_type (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_type (int ignore ATTRIBUTE_UNUSED)
 {
   if (def_symbol_in_progress == NULL)
     {
       as_warn (_(".type pseudo-op used outside of .def/.endef ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   S_SET_DATA_TYPE (def_symbol_in_progress, get_absolute_expression ());
 
   if (ISFCN (S_GET_DATA_TYPE (def_symbol_in_progress)) &&
       S_GET_STORAGE_CLASS (def_symbol_in_progress) != C_TPDEF)
-    {
-      SF_SET_FUNCTION (def_symbol_in_progress);
-    }				/* is a function */
+    SF_SET_FUNCTION (def_symbol_in_progress);
 
   demand_empty_rest_of_line ();
 }
 
 static void
-obj_coff_val (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_val (int ignore ATTRIBUTE_UNUSED)
 {
   if (def_symbol_in_progress == NULL)
     {
       as_warn (_(".val pseudo-op used outside of .def/.endef ignored."));
       demand_empty_rest_of_line ();
       return;
-    }				/* if not inside .def/.endef */
+    }
 
   if (is_name_beginner (*input_line_pointer))
     {
@@ -1096,13 +963,13 @@ obj_coff_val (ignore)
 #ifdef tc_canonicalize_symbol_name
   symbol_name = tc_canonicalize_symbol_name (symbol_name);
 #endif
-      if (!strcmp (symbol_name, "."))
+      if (streq (symbol_name, "."))
 	{
+	  /* If the .val is != from the .def (e.g. statics).  */
 	  symbol_set_frag (def_symbol_in_progress, frag_now);
 	  S_SET_VALUE (def_symbol_in_progress, (valueT) frag_now_fix ());
-	  /* If the .val is != from the .def (e.g. statics) */
 	}
-      else if (strcmp (S_GET_NAME (def_symbol_in_progress), symbol_name))
+      else if (! streq (S_GET_NAME (def_symbol_in_progress), symbol_name))
 	{
 	  expressionS exp;
 
@@ -1130,19 +997,156 @@ obj_coff_val (ignore)
   else
     {
       S_SET_VALUE (def_symbol_in_progress, get_absolute_expression ());
-    }				/* if symbol based */
+    }
 
   demand_empty_rest_of_line ();
 }
 
+#ifdef TE_PE
+
+/* Return nonzero if name begins with weak alternate symbol prefix.  */
+
+static int
+weak_is_altname (const char * name)
+{
+  return strneq (name, weak_altprefix, sizeof (weak_altprefix) - 1);
+}
+
+/* Return the name of the alternate symbol
+   name corresponding to a weak symbol's name.  */
+
+static const char *
+weak_name2altname (const char * name)
+{
+  char *alt_name;
+
+  alt_name = xmalloc (sizeof (weak_altprefix) + strlen (name));
+  strcpy (alt_name, weak_altprefix);
+  return strcat (alt_name, name);
+}
+
+/* Return the name of the weak symbol corresponding to an
+   alterate symbol.  */
+
+static const char *
+weak_altname2name (const char * name)
+{
+  char * weak_name;
+  char * dot;
+
+  assert (weak_is_altname (name));
+
+  weak_name = xstrdup (name + 6);
+  if ((dot = strchr (weak_name, '.')))
+    *dot = 0;
+  return weak_name;
+}
+
+/* Make a weak symbol name unique by
+   appending the name of an external symbol.  */
+
+static const char *
+weak_uniquify (const char * name)
+{
+  char *ret;
+  const char * unique = "";
+
+#ifdef USE_UNIQUE
+  if (an_external_name != NULL)
+    unique = an_external_name;
+#endif
+  assert (weak_is_altname (name));
+
+  if (strchr (name + sizeof (weak_altprefix), '.'))
+    return name;
+
+  ret = xmalloc (strlen (name) + strlen (unique) + 2);
+  strcpy (ret, name);
+  strcat (ret, ".");
+  strcat (ret, unique);
+  return ret;
+}
+
+void
+pecoff_obj_set_weak_hook (symbolS *symbolP)
+{
+  symbolS *alternateP;
+
+  /* See _Microsoft Portable Executable and Common Object
+     File Format Specification_, section 5.5.3.
+     Create a symbol representing the alternate value.
+     coff_frob_symbol will set the value of this symbol from
+     the value of the weak symbol itself.  */
+  S_SET_STORAGE_CLASS (symbolP, C_NT_WEAK);
+  S_SET_NUMBER_AUXILIARY (symbolP, 1);
+  SA_SET_SYM_FSIZE (symbolP, IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY);
+
+  alternateP = symbol_find_or_make (weak_name2altname (S_GET_NAME (symbolP)));
+  S_SET_EXTERNAL (alternateP);
+  S_SET_STORAGE_CLASS (alternateP, C_NT_WEAK);
+
+  SA_SET_SYM_TAGNDX (symbolP, alternateP);
+}
+
 void
-coff_obj_read_begin_hook ()
+pecoff_obj_clear_weak_hook (symbolS *symbolP)
+{
+  symbolS *alternateP;
+
+  S_SET_STORAGE_CLASS (symbolP, 0);
+  SA_SET_SYM_FSIZE (symbolP, 0);
+
+  alternateP = symbol_find (weak_name2altname (S_GET_NAME (symbolP)));
+  S_CLEAR_EXTERNAL (alternateP);
+}
+
+#endif  /* TE_PE */
+
+/* Handle .weak.  This is a GNU extension in formats other than PE. */
+
+static void
+obj_coff_weak (int ignore ATTRIBUTE_UNUSED)
+{
+  char *name;
+  int c;
+  symbolS *symbolP;
+
+  do
+    {
+      name = input_line_pointer;
+      c = get_symbol_end ();
+      if (*name == 0)
+	{
+	  as_warn (_("badly formed .weak directive ignored"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      c = 0;
+      symbolP = symbol_find_or_make (name);
+      *input_line_pointer = c;
+      SKIP_WHITESPACE ();
+      S_SET_WEAK (symbolP);
+
+      if (c == ',')
+	{
+	  input_line_pointer++;
+	  SKIP_WHITESPACE ();
+	  if (*input_line_pointer == '\n')
+	    c = '\n';
+	}
+
+    }
+  while (c == ',');
+
+  demand_empty_rest_of_line ();
+}
+
+void
+coff_obj_read_begin_hook (void)
 {
   /* These had better be the same.  Usually 18 bytes.  */
-#ifndef BFD_HEADERS
   know (sizeof (SYMENT) == sizeof (AUXENT));
   know (SYMESZ == AUXESZ);
-#endif
   tag_init ();
 }
 
@@ -1152,9 +1156,7 @@ static symbolS *coff_last_bf;
 #endif
 
 void
-coff_frob_symbol (symp, punt)
-     symbolS *symp;
-     int *punt;
+coff_frob_symbol (symbolS *symp, int *punt)
 {
   static symbolS *last_tagP;
   static stack *block_stack;
@@ -1168,19 +1170,79 @@ coff_frob_symbol (symp, punt)
     }
 
   if (current_lineno_sym)
-    coff_add_linesym ((symbolS *) 0);
+    coff_add_linesym (NULL);
 
   if (!block_stack)
     block_stack = stack_init (512, sizeof (symbolS*));
 
-  if (S_IS_WEAK (symp))
-    {
 #ifdef TE_PE
-      S_SET_STORAGE_CLASS (symp, C_NT_WEAK);
-#else
-      S_SET_STORAGE_CLASS (symp, C_WEAKEXT);
-#endif
+  if (S_GET_STORAGE_CLASS (symp) == C_NT_WEAK
+      && ! S_IS_WEAK (symp)
+      && weak_is_altname (S_GET_NAME (symp)))
+    {
+      /* This is a weak alternate symbol.  All processing of
+	 PECOFFweak symbols is done here, through the alternate.  */
+      symbolS *weakp = symbol_find_noref (weak_altname2name
+					  (S_GET_NAME (symp)), 1);
+
+      assert (weakp);
+      assert (S_GET_NUMBER_AUXILIARY (weakp) == 1);
+
+      if (! S_IS_WEAK (weakp))
+	{
+	  /* The symbol was turned from weak to strong.  Discard altname.  */
+	  *punt = 1;
+	  return;
+	}
+      else if (symbol_equated_p (weakp))
+	{
+	  /* The weak symbol has an alternate specified; symp is unneeded.  */
+	  S_SET_STORAGE_CLASS (weakp, C_NT_WEAK);
+	  SA_SET_SYM_TAGNDX (weakp,
+	    symbol_get_value_expression (weakp)->X_add_symbol);
+
+	  S_CLEAR_EXTERNAL (symp);
+	  *punt = 1;
+	  return;
+	}
+      else
+	{
+	  /* The weak symbol has been assigned an alternate value.
+             Copy this value to symp, and set symp as weakp's alternate.  */
+	  if (S_GET_STORAGE_CLASS (weakp) != C_NT_WEAK)
+	    {
+	      S_SET_STORAGE_CLASS (symp, S_GET_STORAGE_CLASS (weakp));
+	      S_SET_STORAGE_CLASS (weakp, C_NT_WEAK);
+	    }
+
+	  if (S_IS_DEFINED (weakp))
+	    {
+	      /* This is a defined weak symbol.  Copy value information
+	         from the weak symbol itself to the alternate symbol.  */
+	      symbol_set_value_expression (symp,
+					   symbol_get_value_expression (weakp));
+	      symbol_set_frag (symp, symbol_get_frag (weakp));
+	      S_SET_SEGMENT (symp, S_GET_SEGMENT (weakp));
+	    }
+	  else
+	    {
+	      /* This is an undefined weak symbol.
+		 Define the alternate symbol to zero.  */
+	      S_SET_VALUE (symp, 0);
+	      S_SET_SEGMENT (symp, absolute_section);
+	    }
+
+	  S_SET_NAME (symp, weak_uniquify (S_GET_NAME (symp)));
+	  S_SET_STORAGE_CLASS (symp, C_EXT);
+
+	  S_SET_VALUE (weakp, 0);
+	  S_SET_SEGMENT (weakp, undefined_section);
+	}
     }
+#else /* TE_PE */
+  if (S_IS_WEAK (symp))
+    S_SET_STORAGE_CLASS (symp, C_WEAKEXT);
+#endif /* TE_PE */
 
   if (!S_IS_DEFINED (symp)
       && !S_IS_WEAK (symp)
@@ -1194,8 +1256,8 @@ coff_frob_symbol (symp, punt)
       if (!SF_GET_LOCAL (symp)
 	  && !SF_GET_STATICS (symp)
 	  && S_GET_STORAGE_CLASS (symp) != C_LABEL
-	  && symbol_constant_p(symp)
-	  && (real = symbol_find_base (S_GET_NAME (symp), DO_NOT_STRIP))
+	  && symbol_constant_p (symp)
+	  && (real = symbol_find_noref (S_GET_NAME (symp), 1))
 	  && S_GET_STORAGE_CLASS (real) == C_NULL
 	  && real != symp)
 	{
@@ -1207,7 +1269,10 @@ coff_frob_symbol (symp, punt)
       if (!S_IS_DEFINED (symp) && !SF_GET_LOCAL (symp))
 	{
 	  assert (S_GET_VALUE (symp) == 0);
-	  S_SET_EXTERNAL (symp);
+	  if (S_IS_WEAKREFD (symp))
+	    *punt = 1;
+	  else
+	    S_SET_EXTERNAL (symp);
 	}
       else if (S_GET_STORAGE_CLASS (symp) == C_NULL)
 	{
@@ -1222,7 +1287,7 @@ coff_frob_symbol (symp, punt)
 	{
 	  if (S_GET_STORAGE_CLASS (symp) == C_BLOCK)
 	    {
-	      if (!strcmp (S_GET_NAME (symp), ".bb"))
+	      if (streq (S_GET_NAME (symp), ".bb"))
 		stack_push (block_stack, (char *) &symp);
 	      else
 		{
@@ -1251,7 +1316,8 @@ coff_frob_symbol (symp, punt)
 	  if (S_GET_STORAGE_CLASS (symp) == C_EFCN)
 	    {
 	      if (coff_last_function == 0)
-		as_fatal (_("C_EFCN symbol out of scope"));
+		as_fatal (_("C_EFCN symbol for %s out of scope"),
+			  S_GET_NAME (symp));
 	      SA_SET_SYM_FSIZE (coff_last_function,
 				(long) (S_GET_VALUE (symp)
 					- S_GET_VALUE (coff_last_function)));
@@ -1267,8 +1333,6 @@ coff_frob_symbol (symp, punt)
 
       if (SF_GET_FUNCTION (symp))
 	symbol_get_bfdsym (symp)->flags |= BSF_FUNCTION;
-
-      /* more ...  */
     }
 
   /* Double check weak symbols.  */
@@ -1286,7 +1350,7 @@ coff_frob_symbol (symp, punt)
      order to call SA_SET_SYM_ENDNDX correctly.  */
   if (! symbol_used_in_reloc_p (symp)
       && ((symbol_get_bfdsym (symp)->flags & BSF_SECTION_SYM) != 0
-	  || (! S_IS_EXTERNAL (symp)
+	  || (! (S_IS_EXTERNAL (symp) || S_IS_WEAK (symp))
 	      && ! symbol_get_tc (symp)->output
 	      && S_GET_STORAGE_CLASS (symp) != C_FILE)))
     *punt = 1;
@@ -1314,7 +1378,7 @@ coff_frob_symbol (symp, punt)
 #ifndef OBJ_XCOFF
   if (! *punt
       && S_GET_STORAGE_CLASS (symp) == C_FCN
-      && strcmp (S_GET_NAME (symp), ".bf") == 0)
+      && streq (S_GET_NAME (symp), ".bf"))
     {
       if (coff_last_bf != NULL)
 	SA_SET_SYM_ENDNDX (coff_last_bf, symp);
@@ -1335,7 +1399,7 @@ coff_frob_symbol (symp, punt)
       /* We need i entries for line numbers, plus 1 for the first
 	 entry which BFD will override, plus 1 for the last zero
 	 entry (a marker for BFD).  */
-      l = (alent *) xmalloc ((i + 2) * sizeof (alent));
+      l = xmalloc ((i + 2) * sizeof (* l));
       coffsymbol (symbol_get_bfdsym (symp))->lineno = l;
       l[i + 1].line_number = 0;
       l[i + 1].u.sym = NULL;
@@ -1350,10 +1414,9 @@ coff_frob_symbol (symp, punt)
 }
 
 void
-coff_adjust_section_syms (abfd, sec, x)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec;
-     PTR x ATTRIBUTE_UNUSED;
+coff_adjust_section_syms (bfd *abfd ATTRIBUTE_UNUSED,
+			  asection *sec,
+			  void * x ATTRIBUTE_UNUSED)
 {
   symbolS *secsym;
   segment_info_type *seginfo = seg_info (sec);
@@ -1364,7 +1427,7 @@ coff_adjust_section_syms (abfd, sec, x)
   if (seginfo == NULL)
     return;
 
-  if (!strcmp (sec->name, ".text"))
+  if (streq (sec->name, ".text"))
     nlnno = coff_n_line_nos;
   else
     nlnno = 0;
@@ -1379,13 +1442,14 @@ coff_adjust_section_syms (abfd, sec, x)
 	fixp = fixp->fx_next;
       }
   }
-  if (bfd_get_section_size_before_reloc (sec) == 0
+  if (bfd_get_section_size (sec) == 0
       && nrelocs == 0
       && nlnno == 0
       && sec != text_section
       && sec != data_section
       && sec != bss_section)
     return;
+
   secsym = section_symbol (sec);
   /* This is an estimate; we'll plug in the real value using
      SET_SECTION_RELOCS later */
@@ -1394,9 +1458,9 @@ coff_adjust_section_syms (abfd, sec, x)
 }
 
 void
-coff_frob_file_after_relocs ()
+coff_frob_file_after_relocs (void)
 {
-  bfd_map_over_sections (stdoutput, coff_adjust_section_syms, (char*) 0);
+  bfd_map_over_sections (stdoutput, coff_adjust_section_syms, NULL);
 }
 
 /* Implement the .section pseudo op:
@@ -1419,10 +1483,9 @@ coff_frob_file_after_relocs ()
    .section directive to be parsed in both ELF and COFF formats.  */
 
 void
-obj_coff_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_coff_section (int ignore ATTRIBUTE_UNUSED)
 {
-  /* Strip out the section name */
+  /* Strip out the section name.  */
   char *section_name;
   char c;
   char *name;
@@ -1459,38 +1522,81 @@ obj_coff_section (ignore)
 	exp = get_absolute_expression ();
       else
 	{
-	  ++input_line_pointer;
-	  while (*input_line_pointer != '"'
-		 && ! is_end_of_line[(unsigned char) *input_line_pointer])
+	  unsigned char attr;
+	  int readonly_removed = 0;
+	  int load_removed = 0;
+
+	  while (attr = *++input_line_pointer,
+		 attr != '"'
+		 && ! is_end_of_line[attr])
 	    {
-	      switch (*input_line_pointer)
+	      switch (attr)
 		{
-		case 'b': flags |= SEC_ALLOC; flags &=~ SEC_LOAD; break;
-		case 'n': flags &=~ SEC_LOAD; flags |= SEC_NEVER_LOAD; break;
+		case 'b':
+		  /* Uninitialised data section.  */
+		  flags |= SEC_ALLOC;
+		  flags &=~ SEC_LOAD;
+		  break;
+
+		case 'n':
+		  /* Section not loaded.  */
+		  flags &=~ SEC_LOAD;
+		  flags |= SEC_NEVER_LOAD;
+		  load_removed = 1;
+		  break;
+
+		case 's':
+		  /* Shared section.  */
+		  flags |= SEC_COFF_SHARED;
+		  /* Fall through.  */
+		case 'd':
+		  /* Data section.  */
+		  flags |= SEC_DATA;
+		  if (! load_removed)
+		    flags |= SEC_LOAD;
+		  flags &=~ SEC_READONLY;
+		  break;
+
+		case 'w':
+		  /* Writable section.  */
+		  flags &=~ SEC_READONLY;
+		  readonly_removed = 1;
+		  break;
 
-		case 's': flags |= SEC_SHARED; /* fall through */
-		case 'd': flags |= SEC_DATA | SEC_LOAD; /* fall through */
-		case 'w': flags &=~ SEC_READONLY; break;
+		case 'a':
+		  /* Ignore.  Here for compatibility with ELF.  */
+		  break;
 
-		case 'a': break; /* For compatibility with ELF.  */
-		case 'x': flags |= SEC_CODE | SEC_LOAD; break;
-		case 'r': flags |= SEC_DATA | SEC_LOAD | SEC_READONLY; break;
+		case 'r': /* Read-only section.  Implies a data section.  */
+		  readonly_removed = 0;
+		  /* Fall through.  */
+		case 'x': /* Executable section.  */
+		  /* If we are setting the 'x' attribute or if the 'r'
+		     attribute is being used to restore the readonly status
+		     of a code section (eg "wxr") then set the SEC_CODE flag,
+		     otherwise set the SEC_DATA flag.  */
+		  flags |= (attr == 'x' || (flags & SEC_CODE) ? SEC_CODE : SEC_DATA);
+		  if (! load_removed)
+		    flags |= SEC_LOAD;
+		  /* Note - the READONLY flag is set here, even for the 'x'
+		     attrbiute in order to be compatible with the MSVC
+		     linker.  */
+		  if (! readonly_removed)
+		    flags |= SEC_READONLY;
+		  break;
 
 		case 'i': /* STYP_INFO */
 		case 'l': /* STYP_LIB */
 		case 'o': /* STYP_OVER */
-		  as_warn (_("unsupported section attribute '%c'"),
-			   *input_line_pointer);
+		  as_warn (_("unsupported section attribute '%c'"), attr);
 		  break;
 
 		default:
-		  as_warn(_("unknown section attribute '%c'"),
-			  *input_line_pointer);
+		  as_warn (_("unknown section attribute '%c'"), attr);
 		  break;
 		}
-	      ++input_line_pointer;
 	    }
-	  if (*input_line_pointer == '"')
+	  if (attr == '"')
 	    ++input_line_pointer;
 	}
     }
@@ -1509,7 +1615,7 @@ obj_coff_section (ignore)
       /* Add SEC_LINK_ONCE and SEC_LINK_DUPLICATES_DISCARD to .gnu.linkonce
          sections so adjust_reloc_syms in write.c will correctly handle
          relocs which refer to non-local symbols in these sections.  */
-      if (strncmp (name, ".gnu.linkonce", sizeof (".gnu.linkonce") - 1) == 0)
+      if (strneq (name, ".gnu.linkonce", sizeof (".gnu.linkonce") - 1))
 	flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
 #endif
 
@@ -1520,10 +1626,10 @@ obj_coff_section (ignore)
     }
   else if (flags != SEC_NO_FLAGS)
     {
-      /* This section's attributes have already been set. Warn if the
+      /* This section's attributes have already been set.  Warn if the
          attributes don't match.  */
       flagword matchflags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
-			     | SEC_DATA | SEC_SHARED | SEC_NEVER_LOAD);
+			     | SEC_DATA | SEC_COFF_SHARED | SEC_NEVER_LOAD);
       if ((flags ^ oldflags) & matchflags)
 	as_warn (_("Ignoring changed section attributes for %s"), name);
     }
@@ -1532,16 +1638,15 @@ obj_coff_section (ignore)
 }
 
 void
-coff_adjust_symtab ()
+coff_adjust_symtab (void)
 {
   if (symbol_rootP == NULL
       || S_GET_STORAGE_CLASS (symbol_rootP) != C_FILE)
-    c_dot_file_symbol ("fake");
+    c_dot_file_symbol ("fake", 0);
 }
 
 void
-coff_frob_section (sec)
-     segT sec;
+coff_frob_section (segT sec)
 {
   segT strsec;
   char *p;
@@ -1554,7 +1659,7 @@ coff_frob_section (sec)
      supposedly because standard COFF has no other way of encoding alignment
      for sections.  If your COFF flavor has a different way of encoding
      section alignment, then skip this step, as TICOFF does.  */
-  size = bfd_get_section_size_before_reloc (sec);
+  size = bfd_get_section_size (sec);
   mask = ((bfd_vma) 1 << align_power) - 1;
 #if !defined(TICOFF)
   if (size & mask)
@@ -1594,22 +1699,22 @@ coff_frob_section (sec)
       SA_SET_SCN_SCNLEN (secsym, size);
     }
 
-  /* @@ these should be in a "stabs.h" file, or maybe as.h */
+  /* FIXME: These should be in a "stabs.h" file, or maybe as.h.  */
 #ifndef STAB_SECTION_NAME
 #define STAB_SECTION_NAME ".stab"
 #endif
 #ifndef STAB_STRING_SECTION_NAME
 #define STAB_STRING_SECTION_NAME ".stabstr"
 #endif
-  if (strcmp (STAB_STRING_SECTION_NAME, sec->name))
+  if (! streq (STAB_STRING_SECTION_NAME, sec->name))
     return;
 
   strsec = sec;
   sec = subseg_get (STAB_SECTION_NAME, 0);
   /* size is already rounded up, since other section will be listed first */
-  size = bfd_get_section_size_before_reloc (strsec);
+  size = bfd_get_section_size (strsec);
 
-  n_entries = bfd_get_section_size_before_reloc (sec) / 12 - 1;
+  n_entries = bfd_get_section_size (sec) / 12 - 1;
 
   /* Find first non-empty frag.  It should be large enough.  */
   fragp = seg_info (sec)->frchainP->frch_root;
@@ -1624,8 +1729,7 @@ coff_frob_section (sec)
 }
 
 void
-obj_coff_init_stab_section (seg)
-     segT seg;
+obj_coff_init_stab_section (segT seg)
 {
   char *file;
   char *p;
@@ -1637,7 +1741,7 @@ obj_coff_init_stab_section (seg)
   /* Zero it out.  */
   memset (p, 0, 12);
   as_where (&file, (unsigned int *) NULL);
-  stabstr_name = (char *) xmalloc (strlen (seg->name) + 4);
+  stabstr_name = xmalloc (strlen (seg->name) + 4);
   strcpy (stabstr_name, seg->name);
   strcat (stabstr_name, "str");
   stroff = get_stab_string_offset (file, stabstr_name);
@@ -1646,3009 +1750,73 @@ obj_coff_init_stab_section (seg)
 }
 
 #ifdef DEBUG
-/* for debugging */
 const char *
-s_get_name (s)
-     symbolS *s;
+s_get_name (symbolS *s)
 {
   return ((s == NULL) ? "(NULL)" : S_GET_NAME (s));
 }
 
 void
-symbol_dump ()
+symbol_dump (void)
 {
   symbolS *symbolP;
 
   for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      printf (_("0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"),
-	     (unsigned long) symbolP,
-	     S_GET_NAME(symbolP),
-	     (long) S_GET_DATA_TYPE(symbolP),
-	     S_GET_STORAGE_CLASS(symbolP),
-	     (int) S_GET_SEGMENT(symbolP));
-    }
+    printf (_("0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"),
+	    (unsigned long) symbolP,
+	    S_GET_NAME (symbolP),
+	    (long) S_GET_DATA_TYPE (symbolP),
+	    S_GET_STORAGE_CLASS (symbolP),
+	    (int) S_GET_SEGMENT (symbolP));
 }
 
 #endif /* DEBUG */
 
-#else /* not BFD_ASSEMBLER */
-
-#include "frags.h"
-/* This is needed because we include internal bfd things.  */
-#include <time.h>
-
-#include "libbfd.h"
-#include "libcoff.h"
-
-#ifdef TE_PE
-#include "coff/pe.h"
-#endif
-
-/* The NOP_OPCODE is for the alignment fill value.  Fill with nop so
-   that we can stick sections together without causing trouble.  */
-#ifndef NOP_OPCODE
-#define NOP_OPCODE 0x00
-#endif
-
-/* The zeroes if symbol name is longer than 8 chars */
-#define S_SET_ZEROES(s,v)		((s)->sy_symbol.ost_entry.n_zeroes = (v))
-
-#define MIN(a,b) ((a) < (b)? (a) : (b))
-
-/* This vector is used to turn a gas internal segment number into a
-   section number suitable for insertion into a coff symbol table.
-   This must correspond to seg_info_off_by_4.  */
-
-const short seg_N_TYPE[] =
-{				/* in: segT   out: N_TYPE bits */
-  C_ABS_SECTION,
-  1,    2,  3,   4,    5,   6,   7,   8,   9,  10,
-  11,  12,  13,  14,  15,  16,  17,  18,  19,  20,
-  21,  22,  23,  24,  25,  26,  27,  28,  29,  30,
-  31,  32,  33,  34,  35,  36,  37,  38,  39,  40,
-  C_UNDEF_SECTION,		/* SEG_UNKNOWN */
-  C_UNDEF_SECTION,		/* SEG_GOOF */
-  C_UNDEF_SECTION,		/* SEG_EXPR */
-  C_DEBUG_SECTION,		/* SEG_DEBUG */
-  C_NTV_SECTION,		/* SEG_NTV */
-  C_PTV_SECTION,		/* SEG_PTV */
-  C_REGISTER_SECTION,		/* SEG_REGISTER */
-};
-
-int function_lineoff = -1;	/* Offset in line#s where the last function
-				   started (the odd entry for line #0) */
-
-/* Structure used to keep the filenames which
-   are too long around so that we can stick them
-   into the string table.  */
-struct filename_list
-{
-  char *filename;
-  struct filename_list *next;
-};
-
-static struct filename_list *filename_list_head;
-static struct filename_list *filename_list_tail;
-
-static symbolS *last_line_symbol;
-
-/* Add 4 to the real value to get the index and compensate the
-   negatives. This vector is used by S_GET_SEGMENT to turn a coff
-   section number into a segment number.  */
-
-bfd *abfd;
-static symbolS *previous_file_symbol;
-static int line_base;
-
-void c_symbol_merge PARAMS ((symbolS *, symbolS *));
-symbolS *c_section_symbol PARAMS ((char *, int));
-void obj_coff_section PARAMS ((int));
-void do_relocs_for PARAMS ((bfd *, object_headers *, unsigned long *));
-char * symbol_to_chars PARAMS ((bfd *, char *, symbolS *));
-void w_strings PARAMS ((char *));
-
-static void fixup_segment PARAMS ((segment_info_type *, segT));
-static void fixup_mdeps PARAMS ((fragS *, object_headers *, segT));
-static void fill_section PARAMS ((bfd *,  object_headers *, unsigned long *));
-static int c_line_new PARAMS ((symbolS *, long, int, fragS *));
-static void w_symbols PARAMS ((bfd *, char *, symbolS *));
-static void adjust_stab_section PARAMS ((bfd *, segT));
-static void obj_coff_lcomm PARAMS ((int));
-static void obj_coff_text PARAMS ((int));
-static void obj_coff_data PARAMS ((int));
-static unsigned int count_entries_in_chain PARAMS ((unsigned int));
-static void coff_header_append PARAMS ((bfd *, object_headers *));
-static unsigned int yank_symbols PARAMS ((void));
-static unsigned int glue_symbols PARAMS ((symbolS **, symbolS **));
-static unsigned int tie_tags PARAMS ((void));
-static void crawl_symbols PARAMS ((object_headers *, bfd *));
-static void do_linenos_for PARAMS ((bfd *, object_headers *, unsigned long *));
-static void remove_subsegs PARAMS ((void));
-
-
-
-/* When not using BFD_ASSEMBLER, we permit up to 40 sections.
-
-   This array maps a COFF section number into a gas section number.
-   Because COFF uses negative section numbers, you must add 4 to the
-   COFF section number when indexing into this array; this is done via
-   the SEG_INFO_FROM_SECTION_NUMBER macro.  This must correspond to
-   seg_N_TYPE.  */
-
-static const segT seg_info_off_by_4[] =
-{
- SEG_PTV,
- SEG_NTV,
- SEG_DEBUG,
- SEG_ABSOLUTE,
- SEG_UNKNOWN,
- SEG_E0,  SEG_E1,  SEG_E2,  SEG_E3,  SEG_E4,
- SEG_E5,  SEG_E6,  SEG_E7,  SEG_E8,  SEG_E9,
- SEG_E10, SEG_E11, SEG_E12, SEG_E13, SEG_E14,
- SEG_E15, SEG_E16, SEG_E17, SEG_E18, SEG_E19,
- SEG_E20, SEG_E21, SEG_E22, SEG_E23, SEG_E24,
- SEG_E25, SEG_E26, SEG_E27, SEG_E28, SEG_E29,
- SEG_E30, SEG_E31, SEG_E32, SEG_E33, SEG_E34,
- SEG_E35, SEG_E36, SEG_E37, SEG_E38, SEG_E39,
- (segT) 40,
- (segT) 41,
- (segT) 42,
- (segT) 43,
- (segT) 44,
- (segT) 45,
- (segT) 0,
- (segT) 0,
- (segT) 0,
- SEG_REGISTER
-};
-
-#define SEG_INFO_FROM_SECTION_NUMBER(x) (seg_info_off_by_4[(x)+4])
-
-static relax_addressT relax_align PARAMS ((relax_addressT, long));
-
-static relax_addressT
-relax_align (address, alignment)
-     relax_addressT address;
-     long alignment;
-{
-  relax_addressT mask;
-  relax_addressT new_address;
-
-  mask = ~((~0) << alignment);
-  new_address = (address + mask) & (~mask);
-  return (new_address - address);
-}
-
-segT
-s_get_segment (x)
-     symbolS * x;
-{
-  return SEG_INFO_FROM_SECTION_NUMBER (x->sy_symbol.ost_entry.n_scnum);
-}
-
-static unsigned int size_section PARAMS ((bfd *, unsigned int));
-
-/* Calculate the size of the frag chain and fill in the section header
-   to contain all of it, also fill in the addr of the sections.  */
-
-static unsigned int
-size_section (abfd, idx)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     unsigned int idx;
-{
-
-  unsigned int size = 0;
-  fragS *frag = segment_info[idx].frchainP->frch_root;
-
-  while (frag)
-    {
-      size = frag->fr_address;
-      if (frag->fr_address != size)
-	{
-	  fprintf (stderr, _("Out of step\n"));
-	  size = frag->fr_address;
-	}
-
-      switch (frag->fr_type)
-	{
-#ifdef TC_COFF_SIZEMACHDEP
-	case rs_machine_dependent:
-	  size += TC_COFF_SIZEMACHDEP (frag);
-	  break;
-#endif
-	case rs_space:
-	case rs_fill:
-	case rs_org:
-	  size += frag->fr_fix;
-	  size += frag->fr_offset * frag->fr_var;
-	  break;
-	case rs_align:
-	case rs_align_code:
-	case rs_align_test:
-	  {
-	    addressT off;
-
-	    size += frag->fr_fix;
-	    off = relax_align (size, frag->fr_offset);
-	    if (frag->fr_subtype != 0 && off > frag->fr_subtype)
-	      off = 0;
-	    size += off;
-	  }
-	  break;
-	default:
-	  BAD_CASE (frag->fr_type);
-	  break;
-	}
-      frag = frag->fr_next;
-    }
-  segment_info[idx].scnhdr.s_size = size;
-  return size;
-}
-
-static unsigned int
-count_entries_in_chain (idx)
-     unsigned int idx;
-{
-  unsigned int nrelocs;
-  fixS *fixup_ptr;
-
-  /* Count the relocations.  */
-  fixup_ptr = segment_info[idx].fix_root;
-  nrelocs = 0;
-  while (fixup_ptr != (fixS *) NULL)
-    {
-      if (fixup_ptr->fx_done == 0 && TC_COUNT_RELOC (fixup_ptr))
-	{
-#if defined(TC_A29K) || defined(TC_OR32)
-	  if (fixup_ptr->fx_r_type == RELOC_CONSTH)
-	    nrelocs += 2;
-	  else
-	    nrelocs++;
-#else
-	  nrelocs++;
-#endif
-	}
-
-      fixup_ptr = fixup_ptr->fx_next;
-    }
-  return nrelocs;
-}
-
-#ifdef TE_AUX
-
-static int compare_external_relocs PARAMS ((const PTR, const PTR));
-
-/* AUX's ld expects relocations to be sorted.  */
-
-static int
-compare_external_relocs (x, y)
-     const PTR x;
-     const PTR y;
-{
-  struct external_reloc *a = (struct external_reloc *) x;
-  struct external_reloc *b = (struct external_reloc *) y;
-  bfd_vma aadr = bfd_getb32 (a->r_vaddr);
-  bfd_vma badr = bfd_getb32 (b->r_vaddr);
-  return (aadr < badr ? -1 : badr < aadr ? 1 : 0);
-}
-
-#endif
-
-/* Output all the relocations for a section.  */
-
-void
-do_relocs_for (abfd, h, file_cursor)
-     bfd * abfd;
-     object_headers * h;
-     unsigned long *file_cursor;
-{
-  unsigned int nrelocs;
-  unsigned int idx;
-  unsigned long reloc_start = *file_cursor;
-
-  for (idx = SEG_E0; idx < SEG_LAST; idx++)
-    {
-      if (segment_info[idx].scnhdr.s_name[0])
-	{
-	  struct external_reloc *ext_ptr;
-	  struct external_reloc *external_reloc_vec;
-	  unsigned int external_reloc_size;
-	  unsigned int base = segment_info[idx].scnhdr.s_paddr;
-	  fixS *fix_ptr = segment_info[idx].fix_root;
-	  nrelocs = count_entries_in_chain (idx);
-
-	  if (nrelocs)
-	    /* Bypass this stuff if no relocs.  This also incidentally
-	       avoids a SCO bug, where free(malloc(0)) tends to crash.  */
-	    {
-	      external_reloc_size = nrelocs * RELSZ;
-	      external_reloc_vec =
-		(struct external_reloc *) malloc (external_reloc_size);
-
-	      ext_ptr = external_reloc_vec;
-
-	      /* Fill in the internal coff style reloc struct from the
-		 internal fix list.  */
-	      while (fix_ptr)
-		{
-		  struct internal_reloc intr;
-
-		  /* Only output some of the relocations.  */
-		  if (fix_ptr->fx_done == 0 && TC_COUNT_RELOC (fix_ptr))
-		    {
-#ifdef TC_RELOC_MANGLE
-		      TC_RELOC_MANGLE (&segment_info[idx], fix_ptr, &intr,
-				       base);
-#else
-		      symbolS *dot;
-		      symbolS *symbol_ptr = fix_ptr->fx_addsy;
-
-		      intr.r_type = TC_COFF_FIX2RTYPE (fix_ptr);
-		      intr.r_vaddr =
-			base + fix_ptr->fx_frag->fr_address + fix_ptr->fx_where;
-
-#ifdef TC_KEEP_FX_OFFSET
-		      intr.r_offset = fix_ptr->fx_offset;
-#else
-		      intr.r_offset = 0;
-#endif
-
-		      while (symbol_ptr->sy_value.X_op == O_symbol
-			     && (! S_IS_DEFINED (symbol_ptr)
-				 || S_IS_COMMON (symbol_ptr)))
-			{
-			  symbolS *n;
-
-			  /* We must avoid looping, as that can occur
-                             with a badly written program.  */
-			  n = symbol_ptr->sy_value.X_add_symbol;
-			  if (n == symbol_ptr)
-			    break;
-			  symbol_ptr = n;
-			}
-
-		      /* Turn the segment of the symbol into an offset.  */
-		      if (symbol_ptr)
-			{
-			  resolve_symbol_value (symbol_ptr);
-			  if (! symbol_ptr->sy_resolved)
-			    {
-			      char *file;
-			      unsigned int line;
-
-			      if (expr_symbol_where (symbol_ptr, &file, &line))
-				as_bad_where (file, line,
-					      _("unresolved relocation"));
-			      else
-				as_bad (_("bad relocation: symbol `%s' not in symbol table"),
-					S_GET_NAME (symbol_ptr));
-			    }
-
-			  dot = segment_info[S_GET_SEGMENT (symbol_ptr)].dot;
-			  if (dot)
-			    intr.r_symndx = dot->sy_number;
-			  else
-			    intr.r_symndx = symbol_ptr->sy_number;
-			}
-		      else
-			intr.r_symndx = -1;
-#endif
-		      (void) bfd_coff_swap_reloc_out (abfd, &intr, ext_ptr);
-		      ext_ptr++;
-#if defined(TC_A29K)
-		      /* The 29k has a special kludge for the high 16 bit
-			 reloc.  Two relocations are emitted, R_IHIHALF,
-			 and R_IHCONST. The second one doesn't contain a
-			 symbol, but uses the value for offset.  */
-		      if (intr.r_type == R_IHIHALF)
-			{
-			  /* Now emit the second bit.  */
-			  intr.r_type = R_IHCONST;
-			  intr.r_symndx = fix_ptr->fx_addnumber;
-			  (void) bfd_coff_swap_reloc_out (abfd, &intr, ext_ptr);
-			  ext_ptr++;
-			}
-#endif
-#if defined(TC_OR32)
-		      /* The or32 has a special kludge for the high 16 bit
-			 reloc.  Two relocations are emitted, R_IHIHALF,
-			 and R_IHCONST. The second one doesn't contain a
-			 symbol, but uses the value for offset.  */
-		      if (intr.r_type == R_IHIHALF)
-			{
-			  /* Now emit the second bit.  */
-			  intr.r_type = R_IHCONST;
-			  intr.r_symndx = fix_ptr->fx_addnumber;
-			  (void) bfd_coff_swap_reloc_out (abfd, & intr, ext_ptr);
-			  ext_ptr ++;
-			}
-#endif
-		    }
-
-		  fix_ptr = fix_ptr->fx_next;
-		}
-#ifdef TE_AUX
-	      /* Sort the reloc table.  */
-	      qsort ((PTR) external_reloc_vec, nrelocs,
-		     sizeof (struct external_reloc), compare_external_relocs);
-#endif
-	      /* Write out the reloc table.  */
-	      bfd_bwrite ((PTR) external_reloc_vec,
-			  (bfd_size_type) external_reloc_size, abfd);
-	      free (external_reloc_vec);
-
-	      /* Fill in section header info.  */
-	      segment_info[idx].scnhdr.s_relptr = *file_cursor;
-	      *file_cursor += external_reloc_size;
-	      segment_info[idx].scnhdr.s_nreloc = nrelocs;
-	    }
-	  else
-	    {
-	      /* No relocs.  */
-	      segment_info[idx].scnhdr.s_relptr = 0;
-	    }
-	}
-    }
-
-  /* Set relocation_size field in file headers.  */
-  H_SET_RELOCATION_SIZE (h, *file_cursor - reloc_start, 0);
-}
-
-/* Run through a frag chain and write out the data to go with it, fill
-   in the scnhdrs with the info on the file positions.  */
-
-static void
-fill_section (abfd, h, file_cursor)
-     bfd * abfd;
-     object_headers *h ATTRIBUTE_UNUSED;
-     unsigned long *file_cursor;
-{
-  unsigned int i;
-  unsigned int paddr = 0;
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      unsigned int offset = 0;
-      struct internal_scnhdr *s = &(segment_info[i].scnhdr);
-
-      PROGRESS (1);
-
-      if (s->s_name[0])
-	{
-	  fragS *frag = segment_info[i].frchainP->frch_root;
-	  char *buffer = NULL;
-
-	  if (s->s_size == 0)
-	    s->s_scnptr = 0;
-	  else
-	    {
-	      buffer = xmalloc (s->s_size);
-	      s->s_scnptr = *file_cursor;
-	    }
-	  know (s->s_paddr == paddr);
-
-	  if (strcmp (s->s_name, ".text") == 0)
-	    s->s_flags |= STYP_TEXT;
-	  else if (strcmp (s->s_name, ".data") == 0)
-	    s->s_flags |= STYP_DATA;
-	  else if (strcmp (s->s_name, ".bss") == 0)
-	    {
-	      s->s_scnptr = 0;
-	      s->s_flags |= STYP_BSS;
-
-	      /* @@ Should make the i386 and a29k coff targets define
-		 COFF_NOLOAD_PROBLEM, and have only one test here.  */
-#ifndef TC_I386
-#ifndef TC_A29K
-#ifndef TC_OR32
-#ifndef COFF_NOLOAD_PROBLEM
-	      /* Apparently the SVR3 linker (and exec syscall) and UDI
-		 mondfe progrem are confused by noload sections.  */
-	      s->s_flags |= STYP_NOLOAD;
-#endif
-#endif
-#endif
-#endif
-	    }
-	  else if (strcmp (s->s_name, ".lit") == 0)
-	    s->s_flags = STYP_LIT | STYP_TEXT;
-	  else if (strcmp (s->s_name, ".init") == 0)
-	    s->s_flags |= STYP_TEXT;
-	  else if (strcmp (s->s_name, ".fini") == 0)
-	    s->s_flags |= STYP_TEXT;
-	  else if (strncmp (s->s_name, ".comment", 8) == 0)
-	    s->s_flags |= STYP_INFO;
-
-	  while (frag)
-	    {
-	      unsigned int fill_size;
-	      switch (frag->fr_type)
-		{
-		case rs_machine_dependent:
-		  if (frag->fr_fix)
-		    {
-		      memcpy (buffer + frag->fr_address,
-			      frag->fr_literal,
-			      (unsigned int) frag->fr_fix);
-		      offset += frag->fr_fix;
-		    }
-
-		  break;
-		case rs_space:
-		case rs_fill:
-		case rs_align:
-		case rs_align_code:
-		case rs_align_test:
-		case rs_org:
-		  if (frag->fr_fix)
-		    {
-		      memcpy (buffer + frag->fr_address,
-			      frag->fr_literal,
-			      (unsigned int) frag->fr_fix);
-		      offset += frag->fr_fix;
-		    }
-
-		  fill_size = frag->fr_var;
-		  if (fill_size && frag->fr_offset > 0)
-		    {
-		      unsigned int count;
-		      unsigned int off = frag->fr_fix;
-		      for (count = frag->fr_offset; count; count--)
-			{
-			  if (fill_size + frag->fr_address + off <= s->s_size)
-			    {
-			      memcpy (buffer + frag->fr_address + off,
-				      frag->fr_literal + frag->fr_fix,
-				      fill_size);
-			      off += fill_size;
-			      offset += fill_size;
-			    }
-			}
-		    }
-		  break;
-		case rs_broken_word:
-		  break;
-		default:
-		  abort ();
-		}
-	      frag = frag->fr_next;
-	    }
-
-	  if (s->s_size != 0)
-	    {
-	      if (s->s_scnptr != 0)
-		{
-		  bfd_bwrite (buffer, s->s_size, abfd);
-		  *file_cursor += s->s_size;
-		}
-	      free (buffer);
-	    }
-	  paddr += s->s_size;
-	}
-    }
-}
-
-/* Coff file generation & utilities.  */
-
-static void
-coff_header_append (abfd, h)
-     bfd * abfd;
-     object_headers * h;
-{
-  unsigned int i;
-  char buffer[1000];
-  char buffero[1000];
-#ifdef COFF_LONG_SECTION_NAMES
-  unsigned long string_size = 4;
-#endif
-
-  bfd_seek (abfd, (file_ptr) 0, 0);
-
-#ifndef OBJ_COFF_OMIT_OPTIONAL_HEADER
-  H_SET_MAGIC_NUMBER (h, COFF_MAGIC);
-  H_SET_VERSION_STAMP (h, 0);
-  H_SET_ENTRY_POINT (h, 0);
-  H_SET_TEXT_START (h, segment_info[SEG_E0].frchainP->frch_root->fr_address);
-  H_SET_DATA_START (h, segment_info[SEG_E1].frchainP->frch_root->fr_address);
-  H_SET_SIZEOF_OPTIONAL_HEADER (h, bfd_coff_swap_aouthdr_out(abfd, &h->aouthdr,
-							     buffero));
-#else /* defined (OBJ_COFF_OMIT_OPTIONAL_HEADER) */
-  H_SET_SIZEOF_OPTIONAL_HEADER (h, 0);
-#endif /* defined (OBJ_COFF_OMIT_OPTIONAL_HEADER) */
-
-  i = bfd_coff_swap_filehdr_out (abfd, &h->filehdr, buffer);
-
-  bfd_bwrite (buffer, (bfd_size_type) i, abfd);
-  bfd_bwrite (buffero, (bfd_size_type) H_GET_SIZEOF_OPTIONAL_HEADER (h), abfd);
-
-  for (i = SEG_E0; i < SEG_LAST; i++)
-    {
-      if (segment_info[i].scnhdr.s_name[0])
-	{
-	  unsigned int size;
-
-#ifdef COFF_LONG_SECTION_NAMES
-	  /* Support long section names as found in PE.  This code
-             must coordinate with that in write_object_file and
-             w_strings.  */
-	  if (strlen (segment_info[i].name) > SCNNMLEN)
-	    {
-	      memset (segment_info[i].scnhdr.s_name, 0, SCNNMLEN);
-	      sprintf (segment_info[i].scnhdr.s_name, "/%lu", string_size);
-	      string_size += strlen (segment_info[i].name) + 1;
-	    }
-#endif
-	  size = bfd_coff_swap_scnhdr_out (abfd,
-					   &(segment_info[i].scnhdr),
-					   buffer);
-	  if (size == 0)
-	    as_bad (_("bfd_coff_swap_scnhdr_out failed"));
-	  bfd_bwrite (buffer, (bfd_size_type) size, abfd);
-	}
-    }
-}
-
-char *
-symbol_to_chars (abfd, where, symbolP)
-     bfd * abfd;
-     char *where;
-     symbolS * symbolP;
-{
-  unsigned int numaux = symbolP->sy_symbol.ost_entry.n_numaux;
-  unsigned int i;
-  valueT val;
-
-  /* Turn any symbols with register attributes into abs symbols.  */
-  if (S_GET_SEGMENT (symbolP) == reg_section)
-    S_SET_SEGMENT (symbolP, absolute_section);
-
-  /* At the same time, relocate all symbols to their output value.  */
-#ifndef TE_PE
-  val = (segment_info[S_GET_SEGMENT (symbolP)].scnhdr.s_paddr
-	 + S_GET_VALUE (symbolP));
-#else
-  val = S_GET_VALUE (symbolP);
-#endif
-
-  S_SET_VALUE (symbolP, val);
-
-  symbolP->sy_symbol.ost_entry.n_value = val;
-
-  where += bfd_coff_swap_sym_out (abfd, &symbolP->sy_symbol.ost_entry,
-				  where);
-
-  for (i = 0; i < numaux; i++)
-    {
-      where += bfd_coff_swap_aux_out (abfd,
-				      &symbolP->sy_symbol.ost_auxent[i],
-				      S_GET_DATA_TYPE (symbolP),
-				      S_GET_STORAGE_CLASS (symbolP),
-				      i, numaux, where);
-    }
-
-  return where;
-}
-
-void
-coff_obj_symbol_new_hook (symbolP)
-     symbolS *symbolP;
-{
-  char underscore = 0;		/* Symbol has leading _  */
-
-  /* Effective symbol.  */
-  /* Store the pointer in the offset.  */
-  S_SET_ZEROES (symbolP, 0L);
-  S_SET_DATA_TYPE (symbolP, T_NULL);
-  S_SET_STORAGE_CLASS (symbolP, 0);
-  S_SET_NUMBER_AUXILIARY (symbolP, 0);
-  /* Additional information.  */
-  symbolP->sy_symbol.ost_flags = 0;
-  /* Auxiliary entries.  */
-  memset ((char *) &symbolP->sy_symbol.ost_auxent[0], 0, AUXESZ);
-
-  if (S_IS_STRING (symbolP))
-    SF_SET_STRING (symbolP);
-  if (!underscore && S_IS_LOCAL (symbolP))
-    SF_SET_LOCAL (symbolP);
-}
-
-/* Handle .ln directives.  */
-
-static void
-obj_coff_ln (appline)
-     int appline;
-{
-  int l;
-
-  if (! appline && def_symbol_in_progress != NULL)
-    {
-      /* Wrong context.  */
-      as_warn (_(".ln pseudo-op inside .def/.endef: ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  l = get_absolute_expression ();
-  c_line_new (0, frag_now_fix (), l, frag_now);
-
-  if (appline)
-    new_logical_line ((char *) NULL, l - 1);
-
-#ifndef NO_LISTING
-  {
-    extern int listing;
-
-    if (listing)
-      {
-	if (! appline)
-	  l += line_base - 1;
-	listing_source_line ((unsigned int) l);
-      }
-
-  }
-#endif
-  demand_empty_rest_of_line ();
-}
-
-/* Handle .def directives.
- 
-  One might ask : why can't we symbol_new if the symbol does not
-  already exist and fill it with debug information.  Because of
-  the C_EFCN special symbol. It would clobber the value of the
-  function symbol before we have a chance to notice that it is
-  a C_EFCN. And a second reason is that the code is more clear this
-  way. (at least I think it is :-).  */
-
-#define SKIP_SEMI_COLON()	while (*input_line_pointer++ != ';')
-#define SKIP_WHITESPACES()	while (*input_line_pointer == ' ' || \
-				      *input_line_pointer == '\t') \
-                                         input_line_pointer++;
-
-static void
-obj_coff_def (what)
-     int what ATTRIBUTE_UNUSED;
-{
-  char name_end;		/* Char after the end of name.  */
-  char *symbol_name;		/* Name of the debug symbol.  */
-  char *symbol_name_copy;	/* Temporary copy of the name.  */
-  unsigned int symbol_name_length;
-
-  if (def_symbol_in_progress != NULL)
-    {
-      as_warn (_(".def pseudo-op used inside of .def/.endef: ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  SKIP_WHITESPACES ();
-
-  def_symbol_in_progress = (symbolS *) obstack_alloc (&notes, sizeof (*def_symbol_in_progress));
-  memset (def_symbol_in_progress, 0, sizeof (*def_symbol_in_progress));
-
-  symbol_name = input_line_pointer;
-  name_end = get_symbol_end ();
-  symbol_name_length = strlen (symbol_name);
-  symbol_name_copy = xmalloc (symbol_name_length + 1);
-  strcpy (symbol_name_copy, symbol_name);
-#ifdef tc_canonicalize_symbol_name
-  symbol_name_copy = tc_canonicalize_symbol_name (symbol_name_copy);
-#endif
-
-  /* Initialize the new symbol.  */
-#ifdef STRIP_UNDERSCORE
-  S_SET_NAME (def_symbol_in_progress, (*symbol_name_copy == '_'
-				       ? symbol_name_copy + 1
-				       : symbol_name_copy));
-#else /* STRIP_UNDERSCORE */
-  S_SET_NAME (def_symbol_in_progress, symbol_name_copy);
-#endif /* STRIP_UNDERSCORE */
-  /* free(symbol_name_copy); */
-  def_symbol_in_progress->sy_name_offset = (unsigned long) ~0;
-  def_symbol_in_progress->sy_number = ~0;
-  def_symbol_in_progress->sy_frag = &zero_address_frag;
-  S_SET_VALUE (def_symbol_in_progress, 0);
-
-  if (S_IS_STRING (def_symbol_in_progress))
-    SF_SET_STRING (def_symbol_in_progress);
-
-  *input_line_pointer = name_end;
-
-  demand_empty_rest_of_line ();
-}
-
-unsigned int dim_index;
-
-static void
-obj_coff_endef (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  symbolS *symbolP = 0;
-  /* DIM BUG FIX sac@cygnus.com */
-  dim_index = 0;
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".endef pseudo-op used outside of .def/.endef: ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  /* Set the section number according to storage class.  */
-  switch (S_GET_STORAGE_CLASS (def_symbol_in_progress))
-    {
-    case C_STRTAG:
-    case C_ENTAG:
-    case C_UNTAG:
-      SF_SET_TAG (def_symbol_in_progress);
-      /* Intentional fallthrough.  */
-
-    case C_FILE:
-    case C_TPDEF:
-      SF_SET_DEBUG (def_symbol_in_progress);
-      S_SET_SEGMENT (def_symbol_in_progress, SEG_DEBUG);
-      break;
-
-    case C_EFCN:
-      /* Do not emit this symbol.  */
-      SF_SET_LOCAL (def_symbol_in_progress);
-      /* Intentional fallthrough. */
-      
-    case C_BLOCK:
-      /* Will need processing before writing.  */
-      SF_SET_PROCESS (def_symbol_in_progress);
-      /* Intentional fallthrough.  */
-
-    case C_FCN:
-      S_SET_SEGMENT (def_symbol_in_progress, SEG_E0);
-
-      if (strcmp (S_GET_NAME (def_symbol_in_progress), ".bf") == 0)
-	{			/* .bf */
-	  if (function_lineoff < 0)
-	    fprintf (stderr, _("`.bf' symbol without preceding function\n"));
-
-	  SA_GET_SYM_LNNOPTR (last_line_symbol) = function_lineoff;
-
-	  SF_SET_PROCESS (last_line_symbol);
-	  SF_SET_ADJ_LNNOPTR (last_line_symbol);
-	  SF_SET_PROCESS (def_symbol_in_progress);
-	  function_lineoff = -1;
-	}
-
-      /* Value is always set to .  */
-      def_symbol_in_progress->sy_frag = frag_now;
-      S_SET_VALUE (def_symbol_in_progress, (valueT) frag_now_fix ());
-      break;
-
-#ifdef C_AUTOARG
-    case C_AUTOARG:
-#endif /* C_AUTOARG */
-    case C_AUTO:
-    case C_REG:
-    case C_MOS:
-    case C_MOE:
-    case C_MOU:
-    case C_ARG:
-    case C_REGPARM:
-    case C_FIELD:
-    case C_EOS:
-      SF_SET_DEBUG (def_symbol_in_progress);
-      S_SET_SEGMENT (def_symbol_in_progress, absolute_section);
-      break;
-
-    case C_EXT:
-    case C_WEAKEXT:
-#ifdef TE_PE
-    case C_NT_WEAK:
-#endif
-    case C_STAT:
-    case C_LABEL:
-      /* Valid but set somewhere else (s_comm, s_lcomm, colon).  */
-      break;
-
-    case C_USTATIC:
-    case C_EXTDEF:
-    case C_ULABEL:
-      as_warn (_("unexpected storage class %d"), S_GET_STORAGE_CLASS (def_symbol_in_progress));
-      break;
-    }
-
-  /* Now that we have built a debug symbol, try to find if we should
-     merge with an existing symbol or not.  If a symbol is C_EFCN or
-     absolute_section or untagged SEG_DEBUG it never merges.  We also
-     don't merge labels, which are in a different namespace, nor
-     symbols which have not yet been defined since they are typically
-     unique, nor do we merge tags with non-tags.  */
-
-  /* Two cases for functions.  Either debug followed by definition or
-     definition followed by debug.  For definition first, we will
-     merge the debug symbol into the definition.  For debug first, the
-     lineno entry MUST point to the definition function or else it
-     will point off into space when crawl_symbols() merges the debug
-     symbol into the real symbol.  Therefor, let's presume the debug
-     symbol is a real function reference.  */
-
-  /* FIXME-SOON If for some reason the definition label/symbol is
-     never seen, this will probably leave an undefined symbol at link
-     time.  */
-
-  if (S_GET_STORAGE_CLASS (def_symbol_in_progress) == C_EFCN
-      || S_GET_STORAGE_CLASS (def_symbol_in_progress) == C_LABEL
-      || (S_GET_SEGMENT (def_symbol_in_progress) == SEG_DEBUG
-	  && !SF_GET_TAG (def_symbol_in_progress))
-      || S_GET_SEGMENT (def_symbol_in_progress) == absolute_section
-      || def_symbol_in_progress->sy_value.X_op != O_constant
-      || (symbolP = symbol_find_base (S_GET_NAME (def_symbol_in_progress), DO_NOT_STRIP)) == NULL
-      || (SF_GET_TAG (def_symbol_in_progress) != SF_GET_TAG (symbolP)))
-    {
-      symbol_append (def_symbol_in_progress, symbol_lastP, &symbol_rootP,
-		     &symbol_lastP);
-    }
-  else
-    {
-      /* This symbol already exists, merge the newly created symbol
-	 into the old one.  This is not mandatory. The linker can
-	 handle duplicate symbols correctly. But I guess that it save
-	 a *lot* of space if the assembly file defines a lot of
-	 symbols. [loic] */
-
-      /* The debug entry (def_symbol_in_progress) is merged into the
-	 previous definition.  */
-
-      c_symbol_merge (def_symbol_in_progress, symbolP);
-      /* FIXME-SOON Should *def_symbol_in_progress be free'd? xoxorich.  */
-      def_symbol_in_progress = symbolP;
-
-      if (SF_GET_FUNCTION (def_symbol_in_progress)
-	  || SF_GET_TAG (def_symbol_in_progress)
-	  || S_GET_STORAGE_CLASS (def_symbol_in_progress) == C_STAT)
-	{
-	  /* For functions, and tags, and static symbols, the symbol
-	     *must* be where the debug symbol appears.  Move the
-	     existing symbol to the current place.  */
-	  /* If it already is at the end of the symbol list, do nothing.  */
-	  if (def_symbol_in_progress != symbol_lastP)
-	    {
-	      symbol_remove (def_symbol_in_progress, &symbol_rootP,
-			     &symbol_lastP);
-	      symbol_append (def_symbol_in_progress, symbol_lastP,
-			     &symbol_rootP, &symbol_lastP);
-	    }
-	}
-    }
-
-  if (SF_GET_TAG (def_symbol_in_progress))
-    {
-      symbolS *oldtag;
-
-      oldtag = symbol_find_base (S_GET_NAME (def_symbol_in_progress),
-				 DO_NOT_STRIP);
-      if (oldtag == NULL || ! SF_GET_TAG (oldtag))
-	tag_insert (S_GET_NAME (def_symbol_in_progress),
-		    def_symbol_in_progress);
-    }
-
-  if (SF_GET_FUNCTION (def_symbol_in_progress))
-    {
-      know (sizeof (def_symbol_in_progress) <= sizeof (long));
-      function_lineoff
-	= c_line_new (def_symbol_in_progress, 0, 0, &zero_address_frag);
-
-      SF_SET_PROCESS (def_symbol_in_progress);
-
-      if (symbolP == NULL)
-	{
-	  /* That is, if this is the first time we've seen the
-	     function...  */
-	  symbol_table_insert (def_symbol_in_progress);
-	}
-    }
-
-  def_symbol_in_progress = NULL;
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_dim (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  int dim_index;
-
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".dim pseudo-op used outside of .def/.endef: ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
-
-  for (dim_index = 0; dim_index < DIMNUM; dim_index++)
-    {
-      SKIP_WHITESPACES ();
-      SA_SET_SYM_DIMEN (def_symbol_in_progress, dim_index,
-			get_absolute_expression ());
-
-      switch (*input_line_pointer)
-	{
-	case ',':
-	  input_line_pointer++;
-	  break;
-
-	default:
-	  as_warn (_("badly formed .dim directive ignored"));
-	  /* Intentional fallthrough.  */
-
-	case '\n':
-	case ';':
-	  dim_index = DIMNUM;
-	  break;
-	}
-    }
-
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_line (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  int this_base;
-  const char *name;
-
-  if (def_symbol_in_progress == NULL)
-    {
-      obj_coff_ln (0);
-      return;
-    }
-
-  name = S_GET_NAME (def_symbol_in_progress);
-  this_base = get_absolute_expression ();
-
-  /* Only .bf symbols indicate the use of a new base line number; the
-     line numbers associated with .ef, .bb, .eb are relative to the
-     start of the containing function.  */
-  if (!strcmp (".bf", name))
-    {
-#if 0 /* XXX Can we ever have line numbers going backwards?  */
-      if (this_base > line_base)
-#endif
-	line_base = this_base;
-
-#ifndef NO_LISTING
-      {
-	extern int listing;
-	if (listing)
-	  listing_source_line ((unsigned int) line_base);
-      }
-#endif
-    }
-
-  S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
-  SA_SET_SYM_LNNO (def_symbol_in_progress, this_base);
-
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_size (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".size pseudo-op used outside of .def/.endef ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
-  SA_SET_SYM_SIZE (def_symbol_in_progress, get_absolute_expression ());
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_scl (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".scl pseudo-op used outside of .def/.endef ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  S_SET_STORAGE_CLASS (def_symbol_in_progress, get_absolute_expression ());
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_tag (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  char *symbol_name;
-  char name_end;
-
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".tag pseudo-op used outside of .def/.endef ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  S_SET_NUMBER_AUXILIARY (def_symbol_in_progress, 1);
-  symbol_name = input_line_pointer;
-  name_end = get_symbol_end ();
-#ifdef tc_canonicalize_symbol_name
-  symbol_name = tc_canonicalize_symbol_name (symbol_name);
-#endif
-
-  /* Assume that the symbol referred to by .tag is always defined.
-     This was a bad assumption.  I've added find_or_make. xoxorich.  */
-  SA_SET_SYM_TAGNDX (def_symbol_in_progress,
-		     (long) tag_find_or_make (symbol_name));
-  if (SA_GET_SYM_TAGNDX (def_symbol_in_progress) == 0L)
-    as_warn (_("tag not found for .tag %s"), symbol_name);
-
-  SF_SET_TAGGED (def_symbol_in_progress);
-  *input_line_pointer = name_end;
-
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_type (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".type pseudo-op used outside of .def/.endef ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  S_SET_DATA_TYPE (def_symbol_in_progress, get_absolute_expression ());
-
-  if (ISFCN (S_GET_DATA_TYPE (def_symbol_in_progress)) &&
-      S_GET_STORAGE_CLASS (def_symbol_in_progress) != C_TPDEF)
-    SF_SET_FUNCTION (def_symbol_in_progress);
-
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_val (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  if (def_symbol_in_progress == NULL)
-    {
-      as_warn (_(".val pseudo-op used outside of .def/.endef ignored."));
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  if (is_name_beginner (*input_line_pointer))
-    {
-      char *symbol_name = input_line_pointer;
-      char name_end = get_symbol_end ();
-
-#ifdef tc_canonicalize_symbol_name
-  symbol_name = tc_canonicalize_symbol_name (symbol_name);
-#endif
-
-      if (!strcmp (symbol_name, "."))
-	{
-	  def_symbol_in_progress->sy_frag = frag_now;
-	  S_SET_VALUE (def_symbol_in_progress, (valueT) frag_now_fix ());
-	  /* If the .val is != from the .def (e.g. statics).  */
-	}
-      else if (strcmp (S_GET_NAME (def_symbol_in_progress), symbol_name))
-	{
-	  def_symbol_in_progress->sy_value.X_op = O_symbol;
-	  def_symbol_in_progress->sy_value.X_add_symbol =
-	    symbol_find_or_make (symbol_name);
-	  def_symbol_in_progress->sy_value.X_op_symbol = NULL;
-	  def_symbol_in_progress->sy_value.X_add_number = 0;
-
-	  /* If the segment is undefined when the forward reference is
-	     resolved, then copy the segment id from the forward
-	     symbol.  */
-	  SF_SET_GET_SEGMENT (def_symbol_in_progress);
-
-	  /* FIXME: gcc can generate address expressions here in
-	     unusual cases (search for "obscure" in sdbout.c).  We
-	     just ignore the offset here, thus generating incorrect
-	     debugging information.  We ignore the rest of the line
-	     just below.  */
-	}
-      /* Otherwise, it is the name of a non debug symbol and
-	 its value will be calculated later.  */
-      *input_line_pointer = name_end;
-
-      /* FIXME: this is to avoid an error message in the
-	 FIXME case mentioned just above.  */
-      while (! is_end_of_line[(unsigned char) *input_line_pointer])
-	++input_line_pointer;
-    }
-  else
-    {
-      S_SET_VALUE (def_symbol_in_progress,
-		   (valueT) get_absolute_expression ());
-    }				/* if symbol based */
-
-  demand_empty_rest_of_line ();
-}
-
-#ifdef TE_PE
-
-/* Handle the .linkonce pseudo-op.  This is parsed by s_linkonce in
-   read.c, which then calls this object file format specific routine.  */
-
-void
-obj_coff_pe_handle_link_once (type)
-     enum linkonce_type type;
-{
-  seg_info (now_seg)->scnhdr.s_flags |= IMAGE_SCN_LNK_COMDAT;
-
-  /* We store the type in the seg_info structure, and use it to set up
-     the auxiliary entry for the section symbol in c_section_symbol.  */
-  seg_info (now_seg)->linkonce = type;
-}
-
-#endif /* TE_PE */
-
-void
-coff_obj_read_begin_hook ()
-{
-  /* These had better be the same.  Usually 18 bytes.  */
-#ifndef BFD_HEADERS
-  know (sizeof (SYMENT) == sizeof (AUXENT));
-  know (SYMESZ == AUXESZ);
-#endif
-  tag_init ();
-}
-
-/* This function runs through the symbol table and puts all the
-   externals onto another chain.  */
-
-/* The chain of globals.  */
-symbolS *symbol_globalP;
-symbolS *symbol_global_lastP;
-
-/* The chain of externals.  */
-symbolS *symbol_externP;
-symbolS *symbol_extern_lastP;
-
-stack *block_stack;
-symbolS *last_functionP;
-static symbolS *last_bfP;
-symbolS *last_tagP;
-
-static unsigned int
-yank_symbols ()
-{
-  symbolS *symbolP;
-  unsigned int symbol_number = 0;
-  unsigned int last_file_symno = 0;
-
-  struct filename_list *filename_list_scan = filename_list_head;
-
-  for (symbolP = symbol_rootP;
-       symbolP;
-       symbolP = symbolP ? symbol_next (symbolP) : symbol_rootP)
-    {
-      if (symbolP->sy_mri_common)
-	{
-	  if (S_GET_STORAGE_CLASS (symbolP) == C_EXT
-#ifdef TE_PE
-	      || S_GET_STORAGE_CLASS (symbolP) == C_NT_WEAK
-#endif
-	      || S_GET_STORAGE_CLASS (symbolP) == C_WEAKEXT)
-	    as_bad (_("%s: global symbols not supported in common sections"),
-		    S_GET_NAME (symbolP));
-	  symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-	  continue;
-	}
-
-      if (!SF_GET_DEBUG (symbolP))
-	{
-	  /* Debug symbols do not need all this rubbish.  */
-	  symbolS *real_symbolP;
-
-	  /* L* and C_EFCN symbols never merge.  */
-	  if (!SF_GET_LOCAL (symbolP)
-	      && !SF_GET_STATICS (symbolP)
-	      && S_GET_STORAGE_CLASS (symbolP) != C_LABEL
-	      && symbolP->sy_value.X_op == O_constant
-	      && (real_symbolP = symbol_find_base (S_GET_NAME (symbolP), DO_NOT_STRIP))
-	      && real_symbolP != symbolP)
-	    {
-	      /* FIXME-SOON: where do dups come from?
-		 Maybe tag references before definitions? xoxorich.  */
-	      /* Move the debug data from the debug symbol to the
-		 real symbol. Do NOT do the opposite (i.e. move from
-		 real symbol to debug symbol and remove real symbol from the
-		 list.) Because some pointers refer to the real symbol
-		 whereas no pointers refer to the debug symbol.  */
-	      c_symbol_merge (symbolP, real_symbolP);
-	      /* Replace the current symbol by the real one.  */
-	      /* The symbols will never be the last or the first
-		 because : 1st symbol is .file and 3 last symbols are
-		 .text, .data, .bss.  */
-	      symbol_remove (real_symbolP, &symbol_rootP, &symbol_lastP);
-	      symbol_insert (real_symbolP, symbolP, &symbol_rootP, &symbol_lastP);
-	      symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-	      symbolP = real_symbolP;
-	    }
-
-	  if (flag_readonly_data_in_text && (S_GET_SEGMENT (symbolP) == SEG_E1))
-	    S_SET_SEGMENT (symbolP, SEG_E0);
-
-	  resolve_symbol_value (symbolP);
-
-	  if (S_GET_STORAGE_CLASS (symbolP) == C_NULL)
-	    {
-	      if (!S_IS_DEFINED (symbolP) && !SF_GET_LOCAL (symbolP))
-		{
-		  S_SET_EXTERNAL (symbolP);
-		}
-
-	      else if (S_GET_SEGMENT (symbolP) == SEG_E0)
-		S_SET_STORAGE_CLASS (symbolP, C_LABEL);
-
-	      else
-		S_SET_STORAGE_CLASS (symbolP, C_STAT);
-	    }
-
-	  /* Mainly to speed up if not -g.  */
-	  if (SF_GET_PROCESS (symbolP))
-	    {
-	      /* Handle the nested blocks auxiliary info.  */
-	      if (S_GET_STORAGE_CLASS (symbolP) == C_BLOCK)
-		{
-		  if (!strcmp (S_GET_NAME (symbolP), ".bb"))
-		    stack_push (block_stack, (char *) &symbolP);
-		  else
-		    {
-		      /* .eb */
-		      symbolS *begin_symbolP;
-
-		      begin_symbolP = *(symbolS **) stack_pop (block_stack);
-		      if (begin_symbolP == (symbolS *) 0)
-			as_warn (_("mismatched .eb"));
-		      else
-			SA_SET_SYM_ENDNDX (begin_symbolP, symbol_number + 2);
-		    }
-		}
-	      /* If we are able to identify the type of a function, and we
-	       are out of a function (last_functionP == 0) then, the
-	       function symbol will be associated with an auxiliary
-	       entry.  */
-	      if (last_functionP == (symbolS *) 0 &&
-		  SF_GET_FUNCTION (symbolP))
-		{
-		  last_functionP = symbolP;
-
-		  if (S_GET_NUMBER_AUXILIARY (symbolP) < 1)
-		    S_SET_NUMBER_AUXILIARY (symbolP, 1);
-
-		  /* Clobber possible stale .dim information.  */
-#if 0
-		  /* Iffed out by steve - this fries the lnnoptr info too.  */
-		  bzero (symbolP->sy_symbol.ost_auxent[0].x_sym.x_fcnary.x_ary.x_dimen,
-			 sizeof (symbolP->sy_symbol.ost_auxent[0].x_sym.x_fcnary.x_ary.x_dimen));
-#endif
-		}
-	      if (S_GET_STORAGE_CLASS (symbolP) == C_FCN)
-		{
-		  if (strcmp (S_GET_NAME (symbolP), ".bf") == 0)
-		    {
-		      if (last_bfP != NULL)
-			SA_SET_SYM_ENDNDX (last_bfP, symbol_number);
-		      last_bfP = symbolP;
-		    }
-		}
-	      else if (S_GET_STORAGE_CLASS (symbolP) == C_EFCN)
-		{
-		  /* I don't even know if this is needed for sdb. But
-		     the standard assembler generates it, so...  */
-		  if (last_functionP == (symbolS *) 0)
-		    as_fatal (_("C_EFCN symbol out of scope"));
-		  SA_SET_SYM_FSIZE (last_functionP,
-				    (long) (S_GET_VALUE (symbolP) -
-					    S_GET_VALUE (last_functionP)));
-		  SA_SET_SYM_ENDNDX (last_functionP, symbol_number);
-		 last_functionP = (symbolS *) 0;
-		}
-	    }
-	}
-      else if (SF_GET_TAG (symbolP))
-	{
-	  /* First descriptor of a structure must point to
-	     the first slot after the structure description.  */
-	  last_tagP = symbolP;
-
-	}
-      else if (S_GET_STORAGE_CLASS (symbolP) == C_EOS)
-	{
-	  /* +2 take in account the current symbol.  */
-	  SA_SET_SYM_ENDNDX (last_tagP, symbol_number + 2);
-	}
-      else if (S_GET_STORAGE_CLASS (symbolP) == C_FILE)
-	{
-	  /* If the filename was too long to fit in the
-	     auxent, put it in the string table.  */
-	  if (SA_GET_FILE_FNAME_ZEROS (symbolP) == 0
-	      && SA_GET_FILE_FNAME_OFFSET (symbolP) != 0)
-	    {
-	      SA_SET_FILE_FNAME_OFFSET (symbolP, string_byte_count);
-	      string_byte_count += strlen (filename_list_scan->filename) + 1;
-	      filename_list_scan = filename_list_scan->next;
-	    }
-	  if (S_GET_VALUE (symbolP))
-	    {
-	      S_SET_VALUE (symbolP, last_file_symno);
-	      last_file_symno = symbol_number;
-	    }
-	}
-
-#ifdef tc_frob_coff_symbol
-      tc_frob_coff_symbol (symbolP);
-#endif
-
-      /* We must put the external symbols apart. The loader
-	 does not bomb if we do not. But the references in
-	 the endndx field for a .bb symbol are not corrected
-	 if an external symbol is removed between .bb and .be.
-	 I.e in the following case :
-	 [20] .bb endndx = 22
-	 [21] foo external
-	 [22] .be
-	 ld will move the symbol 21 to the end of the list but
-	 endndx will still be 22 instead of 21.  */
-
-      if (SF_GET_LOCAL (symbolP))
-	{
-	  /* Remove C_EFCN and LOCAL (L...) symbols.  */
-	  /* Next pointer remains valid.  */
-	  symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-
-	}
-      else if (symbolP->sy_value.X_op == O_symbol
-	       && (! S_IS_DEFINED (symbolP) || S_IS_COMMON (symbolP)))
-	{
-	  /* Skip symbols which were equated to undefined or common
-	     symbols.  */
-	  symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-	}
-      else if (!S_IS_DEFINED (symbolP)
-	       && !S_IS_DEBUG (symbolP)
-	       && !SF_GET_STATICS (symbolP)
-	       && (S_GET_STORAGE_CLASS (symbolP) == C_EXT
-#ifdef TE_PE
-		   || S_GET_STORAGE_CLASS (symbolP) == C_NT_WEAK
-#endif
-		   || S_GET_STORAGE_CLASS (symbolP) == C_WEAKEXT))
-	{
-	  /* If external, Remove from the list.  */
-	  symbolS *hold = symbol_previous (symbolP);
-
-	  symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-	  symbol_clear_list_pointers (symbolP);
-	  symbol_append (symbolP, symbol_extern_lastP, &symbol_externP, &symbol_extern_lastP);
-	  symbolP = hold;
-	}
-      else if (! S_IS_DEBUG (symbolP)
-	       && ! SF_GET_STATICS (symbolP)
-	       && ! SF_GET_FUNCTION (symbolP)
-	       && (S_GET_STORAGE_CLASS (symbolP) == C_EXT
-#ifdef TE_PE
-		   || S_GET_STORAGE_CLASS (symbolP) == C_NT_WEAK
-#endif
-		   || S_GET_STORAGE_CLASS (symbolP) == C_NT_WEAK))
-	{
-	  symbolS *hold = symbol_previous (symbolP);
-
-	  /* The O'Reilly COFF book says that defined global symbols
-             come at the end of the symbol table, just before
-             undefined global symbols.  */
-	  symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-	  symbol_clear_list_pointers (symbolP);
-	  symbol_append (symbolP, symbol_global_lastP, &symbol_globalP,
-			 &symbol_global_lastP);
-	  symbolP = hold;
-	}
-      else
-	{
-	  if (SF_GET_STRING (symbolP))
-	    {
-	      symbolP->sy_name_offset = string_byte_count;
-	      string_byte_count += strlen (S_GET_NAME (symbolP)) + 1;
-	    }
-	  else
-	    {
-	      symbolP->sy_name_offset = 0;
-	    }
-
-	  symbolP->sy_number = symbol_number;
-	  symbol_number += 1 + S_GET_NUMBER_AUXILIARY (symbolP);
-	}
-    }
-
-  return symbol_number;
-}
-
-static unsigned int
-glue_symbols (head, tail)
-     symbolS **head;
-     symbolS **tail;
-{
-  unsigned int symbol_number = 0;
-
-  while (*head != NULL)
-    {
-      symbolS *tmp = *head;
-
-      /* Append.  */
-      symbol_remove (tmp, head, tail);
-      symbol_append (tmp, symbol_lastP, &symbol_rootP, &symbol_lastP);
-
-      /* Process.  */
-      if (SF_GET_STRING (tmp))
-	{
-	  tmp->sy_name_offset = string_byte_count;
-	  string_byte_count += strlen (S_GET_NAME (tmp)) + 1;
-	}
-      else
-	{
-	  /* Fix "long" names.  */
-	  tmp->sy_name_offset = 0;
-	}
-
-      tmp->sy_number = symbol_number;
-      symbol_number += 1 + S_GET_NUMBER_AUXILIARY (tmp);
-    }
-
-  return symbol_number;
-}
-
-static unsigned int
-tie_tags ()
-{
-  unsigned int symbol_number = 0;
-  symbolS *symbolP;
-
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      symbolP->sy_number = symbol_number;
-
-      if (SF_GET_TAGGED (symbolP))
-	{
-	  SA_SET_SYM_TAGNDX
-	    (symbolP,
-	     ((symbolS *) SA_GET_SYM_TAGNDX (symbolP))->sy_number);
-	}
-
-      symbol_number += 1 + S_GET_NUMBER_AUXILIARY (symbolP);
-    }
-
-  return symbol_number;
-}
-
-
-static void
-crawl_symbols (h, abfd)
-     object_headers *h;
-     bfd *abfd ATTRIBUTE_UNUSED;
-{
-  unsigned int i;
-
-  /* Initialize the stack used to keep track of the matching .bb .be.  */
-
-  block_stack = stack_init (512, sizeof (symbolS *));
-
-  /* The symbol list should be ordered according to the following sequence
-     order :
-     . .file symbol
-     . debug entries for functions
-     . fake symbols for the sections, including .text .data and .bss
-     . defined symbols
-     . undefined symbols
-     But this is not mandatory. The only important point is to put the
-     undefined symbols at the end of the list.  */
-
-  /* Is there a .file symbol ? If not insert one at the beginning.  */
-  if (symbol_rootP == NULL
-      || S_GET_STORAGE_CLASS (symbol_rootP) != C_FILE)
-    c_dot_file_symbol ("fake");
-
-  /* Build up static symbols for the sections, they are filled in later.  */
-
-  for (i = SEG_E0; i < SEG_LAST; i++)
-    if (segment_info[i].scnhdr.s_name[0])
-      segment_info[i].dot = c_section_symbol ((char *) segment_info[i].name,
-					      i - SEG_E0 + 1);
-
-  /* Take all the externals out and put them into another chain.  */
-  H_SET_SYMBOL_TABLE_SIZE (h, yank_symbols ());
-  /* Take the externals and glue them onto the end.  */
-  H_SET_SYMBOL_TABLE_SIZE (h,
-			   (H_GET_SYMBOL_COUNT (h)
-			    + glue_symbols (&symbol_globalP,
-					    &symbol_global_lastP)
-			    + glue_symbols (&symbol_externP,
-					    &symbol_extern_lastP)));
-
-  H_SET_SYMBOL_TABLE_SIZE (h, tie_tags ());
-  know (symbol_globalP == NULL);
-  know (symbol_global_lastP == NULL);
-  know (symbol_externP == NULL);
-  know (symbol_extern_lastP == NULL);
-}
-
-/* Find strings by crawling along symbol table chain.  */
-
-void
-w_strings (where)
-     char *where;
-{
-  symbolS *symbolP;
-  struct filename_list *filename_list_scan = filename_list_head;
-
-  /* Gotta do md_ byte-ordering stuff for string_byte_count first - KWK.  */
-  md_number_to_chars (where, (valueT) string_byte_count, 4);
-  where += 4;
-
-#ifdef COFF_LONG_SECTION_NAMES
-  /* Support long section names as found in PE.  This code must
-     coordinate with that in coff_header_append and write_object_file.  */
-  {
-    unsigned int i;
-
-    for (i = SEG_E0; i < SEG_LAST; i++)
-      {
-	if (segment_info[i].scnhdr.s_name[0]
-	    && strlen (segment_info[i].name) > SCNNMLEN)
-	  {
-	    unsigned int size;
-
-	    size = strlen (segment_info[i].name) + 1;
-	    memcpy (where, segment_info[i].name, size);
-	    where += size;
-	  }
-      }
-  }
-#endif /* COFF_LONG_SECTION_NAMES */
-
-  for (symbolP = symbol_rootP;
-       symbolP;
-       symbolP = symbol_next (symbolP))
-    {
-      unsigned int size;
-
-      if (SF_GET_STRING (symbolP))
-	{
-	  size = strlen (S_GET_NAME (symbolP)) + 1;
-	  memcpy (where, S_GET_NAME (symbolP), size);
-	  where += size;
-	}
-      if (S_GET_STORAGE_CLASS (symbolP) == C_FILE
-	  && SA_GET_FILE_FNAME_ZEROS (symbolP) == 0
-	  && SA_GET_FILE_FNAME_OFFSET (symbolP) != 0)
-	{
-	  size = strlen (filename_list_scan->filename) + 1;
-	  memcpy (where, filename_list_scan->filename, size);
-	  filename_list_scan = filename_list_scan ->next;
-	  where += size;
-	}
-    }
-}
-
-static void
-do_linenos_for (abfd, h, file_cursor)
-     bfd * abfd;
-     object_headers * h;
-     unsigned long *file_cursor;
-{
-  unsigned int idx;
-  unsigned long start = *file_cursor;
-
-  for (idx = SEG_E0; idx < SEG_LAST; idx++)
-    {
-      segment_info_type *s = segment_info + idx;
-
-      if (s->scnhdr.s_nlnno != 0)
-	{
-	  struct lineno_list *line_ptr;
-
-	  struct external_lineno *buffer =
-	  (struct external_lineno *) xmalloc (s->scnhdr.s_nlnno * LINESZ);
-
-	  struct external_lineno *dst = buffer;
-
-	  /* Run through the table we've built and turn it into its external
-	     form, take this chance to remove duplicates.  */
-
-	  for (line_ptr = s->lineno_list_head;
-	       line_ptr != (struct lineno_list *) NULL;
-	       line_ptr = line_ptr->next)
-	    {
-	      if (line_ptr->line.l_lnno == 0)
-		{
-		  /* Turn a pointer to a symbol into the symbols' index,
-		     provided that it has been initialised.  */
-		  if (line_ptr->line.l_addr.l_symndx)
-		    line_ptr->line.l_addr.l_symndx =
-		      ((symbolS *) line_ptr->line.l_addr.l_symndx)->sy_number;
-		}
-	      else
-		line_ptr->line.l_addr.l_paddr += ((struct frag *) (line_ptr->frag))->fr_address;
-
-	      (void) bfd_coff_swap_lineno_out (abfd, &(line_ptr->line), dst);
-	      dst++;
-	    }
-
-	  s->scnhdr.s_lnnoptr = *file_cursor;
-
-	  bfd_bwrite (buffer, (bfd_size_type) s->scnhdr.s_nlnno * LINESZ, abfd);
-	  free (buffer);
-
-	  *file_cursor += s->scnhdr.s_nlnno * LINESZ;
-	}
-    }
-
-  H_SET_LINENO_SIZE (h, *file_cursor - start);
-}
-
-/* Now we run through the list of frag chains in a segment and
-   make all the subsegment frags appear at the end of the
-   list, as if the seg 0 was extra long.  */
-
-static void
-remove_subsegs ()
-{
-  unsigned int i;
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      frchainS *head = segment_info[i].frchainP;
-      fragS dummy;
-      fragS *prev_frag = &dummy;
-
-      while (head && head->frch_seg == i)
-	{
-	  prev_frag->fr_next = head->frch_root;
-	  prev_frag = head->frch_last;
-	  head = head->frch_next;
-	}
-      prev_frag->fr_next = 0;
-    }
-}
-
-unsigned long machine;
-int coff_flags;
-
-#ifndef SUB_SEGMENT_ALIGN
-#ifdef HANDLE_ALIGN
-/* The last subsegment gets an alignment corresponding to the alignment
-   of the section.  This allows proper nop-filling at the end of
-   code-bearing sections.  */
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)					\
-  (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
-   ? get_recorded_alignment (SEG) : 0)
-#else
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 1
-#endif
-#endif
-
-extern void
-write_object_file ()
-{
-  int i;
-  const char *name;
-  struct frchain *frchain_ptr;
-
-  object_headers headers;
-  unsigned long file_cursor;
-  bfd *abfd;
-  unsigned int addr;
-  abfd = bfd_openw (out_file_name, TARGET_FORMAT);
-
-  if (abfd == 0)
-    {
-      as_perror (_("FATAL: Can't create %s"), out_file_name);
-      exit (EXIT_FAILURE);
-    }
-  bfd_set_format (abfd, bfd_object);
-  bfd_set_arch_mach (abfd, BFD_ARCH, machine);
-
-  string_byte_count = 4;
-
-  /* Run through all the sub-segments and align them up.  Also
-     close any open frags.  We tack a .fill onto the end of the
-     frag chain so that any .align's size can be worked by looking
-     at the next frag.  */
-  for (frchain_ptr = frchain_root;
-       frchain_ptr != (struct frchain *) NULL;
-       frchain_ptr = frchain_ptr->frch_next)
-    {
-      int alignment;
-
-      subseg_set (frchain_ptr->frch_seg, frchain_ptr->frch_subseg);
-
-      alignment = SUB_SEGMENT_ALIGN (now_seg, frchain_ptr);
-
-#ifdef md_do_align
-      md_do_align (alignment, (char *) NULL, 0, 0, alignment_done);
-#endif
-      if (subseg_text_p (now_seg))
-	frag_align_code (alignment, 0);
-      else
-	frag_align (alignment, 0, 0);
-
-#ifdef md_do_align
-    alignment_done:
-#endif
-
-      frag_wane (frag_now);
-      frag_now->fr_fix = 0;
-      know (frag_now->fr_next == NULL);
-    }
-
-  remove_subsegs ();
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    relax_segment (segment_info[i].frchainP->frch_root, i);
-
-  /* Relaxation has completed.  Freeze all syms.  */
-  finalize_syms = 1;
-
-  H_SET_NUMBER_OF_SECTIONS (&headers, 0);
-
-  /* Find out how big the sections are, and set the addresses.  */
-  addr = 0;
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      long size;
-
-      segment_info[i].scnhdr.s_paddr = addr;
-      segment_info[i].scnhdr.s_vaddr = addr;
-
-      if (segment_info[i].scnhdr.s_name[0])
-	{
-	  H_SET_NUMBER_OF_SECTIONS (&headers,
-				    H_GET_NUMBER_OF_SECTIONS (&headers) + 1);
-
-#ifdef COFF_LONG_SECTION_NAMES
-	  /* Support long section names as found in PE.  This code
-	     must coordinate with that in coff_header_append and
-	     w_strings.  */
-	  {
-	    unsigned int len;
-
-	    len = strlen (segment_info[i].name);
-	    if (len > SCNNMLEN)
-	      string_byte_count += len + 1;
-	  }
-#endif /* COFF_LONG_SECTION_NAMES */
-	}
-
-      size = size_section (abfd, (unsigned int) i);
-      addr += size;
-
-      /* I think the section alignment is only used on the i960; the
-	 i960 needs it, and it should do no harm on other targets.  */
-#ifdef ALIGNMENT_IN_S_FLAGS
-      segment_info[i].scnhdr.s_flags |= (section_alignment[i] & 0xF) << 8;
-#else
-      segment_info[i].scnhdr.s_align = 1 << section_alignment[i];
-#endif
-
-      if (i == SEG_E0)
-	H_SET_TEXT_SIZE (&headers, size);
-      else if (i == SEG_E1)
-	H_SET_DATA_SIZE (&headers, size);
-      else if (i == SEG_E2)
-	H_SET_BSS_SIZE (&headers, size);
-    }
-
-  /* Turn the gas native symbol table shape into a coff symbol table.  */
-  crawl_symbols (&headers, abfd);
-
-  if (string_byte_count == 4)
-    string_byte_count = 0;
-
-  H_SET_STRING_SIZE (&headers, string_byte_count);
-
-#ifdef tc_frob_file
-  tc_frob_file ();
-#endif
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      fixup_mdeps (segment_info[i].frchainP->frch_root, &headers, i);
-      fixup_segment (&segment_info[i], i);
-    }
-
-  /* Look for ".stab" segments and fill in their initial symbols
-     correctly.  */
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      name = segment_info[i].name;
-
-      if (name != NULL
-	  && strncmp (".stab", name, 5) == 0
-	  && strncmp (".stabstr", name, 8) != 0)
-	adjust_stab_section (abfd, i);
-    }
-
-  file_cursor = H_GET_TEXT_FILE_OFFSET (&headers);
-
-  bfd_seek (abfd, (file_ptr) file_cursor, 0);
-
-  /* Plant the data.  */
-  fill_section (abfd, &headers, &file_cursor);
-
-  do_relocs_for (abfd, &headers, &file_cursor);
-
-  do_linenos_for (abfd, &headers, &file_cursor);
-
-  H_SET_FILE_MAGIC_NUMBER (&headers, COFF_MAGIC);
-#ifndef OBJ_COFF_OMIT_TIMESTAMP
-  H_SET_TIME_STAMP (&headers, (long)time((time_t *)0));
-#else
-  H_SET_TIME_STAMP (&headers, 0);
-#endif
-#ifdef TC_COFF_SET_MACHINE
-  TC_COFF_SET_MACHINE (&headers);
-#endif
-
-#ifndef COFF_FLAGS
-#define COFF_FLAGS 0
-#endif
-
-#ifdef KEEP_RELOC_INFO
-  H_SET_FLAGS (&headers, ((H_GET_LINENO_SIZE(&headers) ? 0 : F_LNNO) |
-			  COFF_FLAGS | coff_flags));
-#else
-  H_SET_FLAGS (&headers, ((H_GET_LINENO_SIZE(&headers)     ? 0 : F_LNNO)   |
-			  (H_GET_RELOCATION_SIZE(&headers) ? 0 : F_RELFLG) |
-			  COFF_FLAGS | coff_flags));
-#endif
-
-  {
-    unsigned int symtable_size = H_GET_SYMBOL_TABLE_SIZE (&headers);
-    char *buffer1 = xmalloc (symtable_size + string_byte_count + 1);
-
-    H_SET_SYMBOL_TABLE_POINTER (&headers, bfd_tell (abfd));
-    w_symbols (abfd, buffer1, symbol_rootP);
-    if (string_byte_count > 0)
-      w_strings (buffer1 + symtable_size);
-    bfd_bwrite (buffer1, (bfd_size_type) symtable_size + string_byte_count,
-		abfd);
-    free (buffer1);
-  }
-
-  coff_header_append (abfd, &headers);
-#if 0
-  /* Recent changes to write need this, but where it should
-     go is up to Ken..  */
-  if (!bfd_close_all_done (abfd))
-    as_fatal (_("Can't close %s: %s"), out_file_name,
-	      bfd_errmsg (bfd_get_error ()));
-#else
-  {
-    extern bfd *stdoutput;
-    stdoutput = abfd;
-  }
-#endif
-
-}
-
-/* Add a new segment.  This is called from subseg_new via the
-   obj_new_segment macro.  */
-
-segT
-obj_coff_add_segment (name)
-     const char *name;
-{
-  unsigned int i;
-
-#ifndef COFF_LONG_SECTION_NAMES
-  char buf[SCNNMLEN + 1];
-
-  strncpy (buf, name, SCNNMLEN);
-  buf[SCNNMLEN] = '\0';
-  name = buf;
-#endif
-
-  for (i = SEG_E0; i < SEG_LAST && segment_info[i].scnhdr.s_name[0]; i++)
-    if (strcmp (name, segment_info[i].name) == 0)
-      return (segT) i;
-
-  if (i == SEG_LAST)
-    {
-      as_bad (_("Too many new sections; can't add \"%s\""), name);
-      return now_seg;
-    }
-
-  /* Add a new section.  */
-  strncpy (segment_info[i].scnhdr.s_name, name,
-	   sizeof (segment_info[i].scnhdr.s_name));
-  segment_info[i].scnhdr.s_flags = STYP_REG;
-  segment_info[i].name = xstrdup (name);
-
-  return (segT) i;
-}
-
-/* Implement the .section pseudo op:
-  	.section name {, "flags"}
-                  ^         ^
-                  |         +--- optional flags: 'b' for bss
-                  |                              'i' for info
-                  +-- section name               'l' for lib
-                                                 'n' for noload
-                                                 'o' for over
-                                                 'w' for data
-  						 'd' (apparently m88k for data)
-                                                 'x' for text
-  						 'r' for read-only data
-   But if the argument is not a quoted string, treat it as a
-   subsegment number.  */
-
-void
-obj_coff_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  /* Strip out the section name.  */
-  char *section_name, *name;
-  char c;
-  unsigned int exp;
-  long flags;
-
-  if (flag_mri)
-    {
-      char type;
-
-      s_mri_sect (&type);
-      flags = 0;
-      if (type == 'C')
-	flags = STYP_TEXT;
-      else if (type == 'D')
-	flags = STYP_DATA;
-      segment_info[now_seg].scnhdr.s_flags |= flags;
-
-      return;
-    }
-
-  section_name = input_line_pointer;
-  c = get_symbol_end ();
-
-  name = xmalloc (input_line_pointer - section_name + 1);
-  strcpy (name, section_name);
-
-  *input_line_pointer = c;
-
-  exp = 0;
-  flags = 0;
-
-  SKIP_WHITESPACE ();
-  if (*input_line_pointer == ',')
-    {
-      ++input_line_pointer;
-      SKIP_WHITESPACE ();
-
-      if (*input_line_pointer != '"')
-	exp = get_absolute_expression ();
-      else
-	{
-	  ++input_line_pointer;
-	  while (*input_line_pointer != '"'
-		 && ! is_end_of_line[(unsigned char) *input_line_pointer])
-	    {
-	      switch (*input_line_pointer)
-		{
-		case 'b': flags |= STYP_BSS;    break;
-		case 'i': flags |= STYP_INFO;   break;
-		case 'l': flags |= STYP_LIB;    break;
-		case 'n': flags |= STYP_NOLOAD; break;
-		case 'o': flags |= STYP_OVER;   break;
-		case 'd':
-		case 'w': flags |= STYP_DATA;   break;
-		case 'x': flags |= STYP_TEXT;   break;
-		case 'r': flags |= STYP_LIT;	break;
-		default:
-		  as_warn(_("unknown section attribute '%c'"),
-			  *input_line_pointer);
-		  break;
-		}
-	      ++input_line_pointer;
-	    }
-	  if (*input_line_pointer == '"')
-	    ++input_line_pointer;
-	}
-    }
-
-  subseg_new (name, (subsegT) exp);
-
-  segment_info[now_seg].scnhdr.s_flags |= flags;
-
-  demand_empty_rest_of_line ();
-}
-
-static void
-obj_coff_text (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  subseg_new (".text", get_absolute_expression ());
-}
-
-static void
-obj_coff_data (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  if (flag_readonly_data_in_text)
-    subseg_new (".text", get_absolute_expression () + 1000);
-  else
-    subseg_new (".data", get_absolute_expression ());
-}
-
-static void
-obj_coff_ident (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  segT current_seg = now_seg;		/* Save current seg.  */
-  subsegT current_subseg = now_subseg;
-
-  subseg_new (".comment", 0);		/* .comment seg.  */
-  stringer (1);				/* Read string.  */
-  subseg_set (current_seg, current_subseg);	/* Restore current seg.  */
-}
-
-void
-c_symbol_merge (debug, normal)
-     symbolS *debug;
-     symbolS *normal;
-{
-  S_SET_DATA_TYPE (normal, S_GET_DATA_TYPE (debug));
-  S_SET_STORAGE_CLASS (normal, S_GET_STORAGE_CLASS (debug));
-
-  if (S_GET_NUMBER_AUXILIARY (debug) > S_GET_NUMBER_AUXILIARY (normal))
-    S_SET_NUMBER_AUXILIARY (normal, S_GET_NUMBER_AUXILIARY (debug));
-
-  if (S_GET_NUMBER_AUXILIARY (debug) > 0)
-    memcpy ((char *) &normal->sy_symbol.ost_auxent[0],
-	    (char *) &debug->sy_symbol.ost_auxent[0],
-	    (unsigned int) (S_GET_NUMBER_AUXILIARY (debug) * AUXESZ));
-
-  /* Move the debug flags.  */
-  SF_SET_DEBUG_FIELD (normal, SF_GET_DEBUG_FIELD (debug));
-}
-
-static int
-c_line_new (symbol, paddr, line_number, frag)
-     symbolS * symbol;
-     long paddr;
-     int line_number;
-     fragS * frag;
-{
-  struct lineno_list *new_line =
-  (struct lineno_list *) xmalloc (sizeof (struct lineno_list));
-
-  segment_info_type *s = segment_info + now_seg;
-  new_line->line.l_lnno = line_number;
-
-  if (line_number == 0)
-    {
-      last_line_symbol = symbol;
-      new_line->line.l_addr.l_symndx = (long) symbol;
-    }
-  else
-    {
-      new_line->line.l_addr.l_paddr = paddr;
-    }
-
-  new_line->frag = (char *) frag;
-  new_line->next = (struct lineno_list *) NULL;
-
-  if (s->lineno_list_head == (struct lineno_list *) NULL)
-    s->lineno_list_head = new_line;
-  else
-    s->lineno_list_tail->next = new_line;
-
-  s->lineno_list_tail = new_line;
-  return LINESZ * s->scnhdr.s_nlnno++;
-}
-
-void
-c_dot_file_symbol (filename)
-     char *filename;
-{
-  symbolS *symbolP;
-
-  symbolP = symbol_new (".file",
-			SEG_DEBUG,
-			0,
-			&zero_address_frag);
-
-  S_SET_STORAGE_CLASS (symbolP, C_FILE);
-  S_SET_NUMBER_AUXILIARY (symbolP, 1);
-
-  if (strlen (filename) > FILNMLEN)
-    {
-      /* Filename is too long to fit into an auxent,
-	 we stick it into the string table instead.  We keep
-	 a linked list of the filenames we find so we can emit
-	 them later.  */
-      struct filename_list *f = ((struct filename_list *)
-				 xmalloc (sizeof (struct filename_list)));
-
-      f->filename = filename;
-      f->next = 0;
-
-      SA_SET_FILE_FNAME_ZEROS (symbolP, 0);
-      SA_SET_FILE_FNAME_OFFSET (symbolP, 1);
-
-      if (filename_list_tail)
-	filename_list_tail->next = f;
-      else
-	filename_list_head = f;
-      filename_list_tail = f;
-    }
-  else
-    {
-      SA_SET_FILE_FNAME (symbolP, filename);
-    }
-#ifndef NO_LISTING
-  {
-    extern int listing;
-    if (listing)
-      listing_source_file (filename);
-  }
-#endif
-  SF_SET_DEBUG (symbolP);
-  S_SET_VALUE (symbolP, (valueT) previous_file_symbol);
-
-  previous_file_symbol = symbolP;
-
-  /* Make sure that the symbol is first on the symbol chain.  */
-  if (symbol_rootP != symbolP)
-    {
-      symbol_remove (symbolP, &symbol_rootP, &symbol_lastP);
-      symbol_insert (symbolP, symbol_rootP, &symbol_rootP, &symbol_lastP);
-    }
-}
-
-/* Build a 'section static' symbol.  */
-
-symbolS *
-c_section_symbol (name, idx)
-     char *name;
-     int idx;
-{
-  symbolS *symbolP;
-
-  symbolP = symbol_find_base (name, DO_NOT_STRIP);
-  if (symbolP == NULL)
-    symbolP = symbol_new (name, idx, 0, &zero_address_frag);
-  else
-    {
-      /* Mmmm.  I just love violating interfaces.  Makes me feel...dirty.  */
-      S_SET_SEGMENT (symbolP, idx);
-      symbolP->sy_frag = &zero_address_frag;
-    }
-
-  S_SET_STORAGE_CLASS (symbolP, C_STAT);
-  S_SET_NUMBER_AUXILIARY (symbolP, 1);
-
-  SF_SET_STATICS (symbolP);
-
-#ifdef TE_DELTA
-  /* manfred@s-direktnet.de: section symbols *must* have the LOCAL bit cleared,
-     which is set by the new definition of LOCAL_LABEL in tc-m68k.h.  */
-  SF_CLEAR_LOCAL (symbolP);
-#endif
-#ifdef TE_PE
-  /* If the .linkonce pseudo-op was used for this section, we must
-     store the information in the auxiliary entry for the section
-     symbol.  */
-  if (segment_info[idx].linkonce != LINKONCE_UNSET)
-    {
-      int type;
-
-      switch (segment_info[idx].linkonce)
-	{
-	default:
-	  abort ();
-	case LINKONCE_DISCARD:
-	  type = IMAGE_COMDAT_SELECT_ANY;
-	  break;
-	case LINKONCE_ONE_ONLY:
-	  type = IMAGE_COMDAT_SELECT_NODUPLICATES;
-	  break;
-	case LINKONCE_SAME_SIZE:
-	  type = IMAGE_COMDAT_SELECT_SAME_SIZE;
-	  break;
-	case LINKONCE_SAME_CONTENTS:
-	  type = IMAGE_COMDAT_SELECT_EXACT_MATCH;
-	  break;
-	}
-
-      SYM_AUXENT (symbolP)->x_scn.x_comdat = type;
-    }
-#endif /* TE_PE */
-
-  return symbolP;
-}
-
-static void
-w_symbols (abfd, where, symbol_rootP)
-     bfd * abfd;
-     char *where;
-     symbolS * symbol_rootP;
-{
-  symbolS *symbolP;
-  unsigned int i;
-
-  /* First fill in those values we have only just worked out.  */
-  for (i = SEG_E0; i < SEG_LAST; i++)
-    {
-      symbolP = segment_info[i].dot;
-      if (symbolP)
-	{
-	  SA_SET_SCN_SCNLEN (symbolP, segment_info[i].scnhdr.s_size);
-	  SA_SET_SCN_NRELOC (symbolP, segment_info[i].scnhdr.s_nreloc);
-	  SA_SET_SCN_NLINNO (symbolP, segment_info[i].scnhdr.s_nlnno);
-	}
-    }
-
-  /* Emit all symbols left in the symbol chain.  */
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Used to save the offset of the name. It is used to point
-	 to the string in memory but must be a file offset.  */
-      char *temp;
-
-      /* We can't fix the lnnoptr field in yank_symbols with the other
-         adjustments, because we have to wait until we know where they
-         go in the file.  */
-      if (SF_GET_ADJ_LNNOPTR (symbolP))
-	SA_GET_SYM_LNNOPTR (symbolP) +=
-	  segment_info[S_GET_SEGMENT (symbolP)].scnhdr.s_lnnoptr;
-
-      tc_coff_symbol_emit_hook (symbolP);
-
-      temp = S_GET_NAME (symbolP);
-      if (SF_GET_STRING (symbolP))
-	{
-	  S_SET_OFFSET (symbolP, symbolP->sy_name_offset);
-	  S_SET_ZEROES (symbolP, 0);
-	}
-      else
-	{
-	  memset (symbolP->sy_symbol.ost_entry.n_name, 0, SYMNMLEN);
-	  strncpy (symbolP->sy_symbol.ost_entry.n_name, temp, SYMNMLEN);
-	}
-      where = symbol_to_chars (abfd, where, symbolP);
-      S_SET_NAME (symbolP, temp);
-    }
-}
-
-static void
-obj_coff_lcomm (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  s_lcomm(0);
-  return;
-#if 0
-  char *name;
-  char c;
-  int temp;
-  char *p;
-
-  symbolS *symbolP;
-
-  name = input_line_pointer;
-
-  c = get_symbol_end ();
-  p = input_line_pointer;
-  *p = c;
-  SKIP_WHITESPACE ();
-  if (*input_line_pointer != ',')
-    {
-      as_bad (_("Expected comma after name"));
-      ignore_rest_of_line ();
-      return;
-    }
-  if (*input_line_pointer == '\n')
-    {
-      as_bad (_("Missing size expression"));
-      return;
-    }
-  input_line_pointer++;
-  if ((temp = get_absolute_expression ()) < 0)
-    {
-      as_warn (_("lcomm length (%d.) <0! Ignored."), temp);
-      ignore_rest_of_line ();
-      return;
-    }
-  *p = 0;
-
-  symbolP = symbol_find_or_make (name);
-
-  if (S_GET_SEGMENT (symbolP) == SEG_UNKNOWN &&
-      S_GET_VALUE (symbolP) == 0)
-    {
-      if (! need_pass_2)
-	{
-	  char *p;
-	  segT current_seg = now_seg; 	/* Save current seg.  */
-	  subsegT current_subseg = now_subseg;
-
-	  subseg_set (SEG_E2, 1);
-	  symbolP->sy_frag = frag_now;
-	  p = frag_var(rs_org, 1, 1, (relax_substateT)0, symbolP,
-		       (offsetT) temp, (char *) 0);
-	  *p = 0;
-	  subseg_set (current_seg, current_subseg); /* Restore current seg.  */
-	  S_SET_SEGMENT (symbolP, SEG_E2);
-	  S_SET_STORAGE_CLASS (symbolP, C_STAT);
-	}
-    }
-  else
-    as_bad (_("Symbol %s already defined"), name);
-
-  demand_empty_rest_of_line ();
-#endif
-}
-
-static void
-fixup_mdeps (frags, h, this_segment)
-     fragS *frags;
-     object_headers *h ATTRIBUTE_UNUSED;
-     segT this_segment;
-{
-  subseg_change (this_segment, 0);
-
-  while (frags)
-    {
-      switch (frags->fr_type)
-	{
-	case rs_align:
-	case rs_align_code:
-	case rs_align_test:
-	case rs_org:
-#ifdef HANDLE_ALIGN
-	  HANDLE_ALIGN (frags);
-#endif
-	  frags->fr_type = rs_fill;
-	  frags->fr_offset =
-	    ((frags->fr_next->fr_address - frags->fr_address - frags->fr_fix)
-	     / frags->fr_var);
-	  break;
-	case rs_machine_dependent:
-	  md_convert_frag (h, this_segment, frags);
-	  frag_wane (frags);
-	  break;
-	default:
-	  ;
-	}
-      frags = frags->fr_next;
-    }
-}
-
-#if 1
-
-#ifndef TC_FORCE_RELOCATION
-#define TC_FORCE_RELOCATION(fix) 0
-#endif
-
-static void
-fixup_segment (segP, this_segment_type)
-     segment_info_type * segP;
-     segT this_segment_type;
-{
-  fixS * fixP;
-  symbolS *add_symbolP;
-  symbolS *sub_symbolP;
-  long add_number;
-  int size;
-  char *place;
-  long where;
-  char pcrel;
-  fragS *fragP;
-  segT add_symbol_segment = absolute_section;
-
-  for (fixP = segP->fix_root; fixP; fixP = fixP->fx_next)
-    {
-      fragP = fixP->fx_frag;
-      know (fragP);
-      where = fixP->fx_where;
-      place = fragP->fr_literal + where;
-      size = fixP->fx_size;
-      add_symbolP = fixP->fx_addsy;
-      sub_symbolP = fixP->fx_subsy;
-      add_number = fixP->fx_offset;
-      pcrel = fixP->fx_pcrel;
-
-      /* We want function-relative stabs to work on systems which
-	 may use a relaxing linker; thus we must handle the sym1-sym2
-	 fixups function-relative stabs generates.
-
-	 Of course, if you actually enable relaxing in the linker, the
-	 line and block scoping information is going to be incorrect
-	 in some cases.  The only way to really fix this is to support
-	 a reloc involving the difference of two symbols.  */
-      if (linkrelax
-	  && (!sub_symbolP || pcrel))
-	continue;
-
-#ifdef TC_I960
-      if (fixP->fx_tcbit && SF_GET_CALLNAME (add_symbolP))
-	{
-	  /* Relocation should be done via the associated 'bal' entry
-	     point symbol.  */
-
-	  if (!SF_GET_BALNAME (tc_get_bal_of_call (add_symbolP)))
-	    {
-	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("No 'bal' entry point for leafproc %s"),
-			    S_GET_NAME (add_symbolP));
-	      continue;
-	    }
-	  fixP->fx_addsy = add_symbolP = tc_get_bal_of_call (add_symbolP);
-	}
-#endif
-
-      /* Make sure the symbols have been resolved; this may not have
-         happened if these are expression symbols.  */
-      if (add_symbolP != NULL && ! add_symbolP->sy_resolved)
-	resolve_symbol_value (add_symbolP);
-
-      if (add_symbolP != NULL)
-	{
-	  /* If this fixup is against a symbol which has been equated
-	     to another symbol, convert it to the other symbol.  */
-	  if (add_symbolP->sy_value.X_op == O_symbol
-	      && (! S_IS_DEFINED (add_symbolP)
-		  || S_IS_COMMON (add_symbolP)))
-	    {
-	      while (add_symbolP->sy_value.X_op == O_symbol
-		     && (! S_IS_DEFINED (add_symbolP)
-			 || S_IS_COMMON (add_symbolP)))
-		{
-		  symbolS *n;
-
-		  /* We must avoid looping, as that can occur with a
-		     badly written program.  */
-		  n = add_symbolP->sy_value.X_add_symbol;
-		  if (n == add_symbolP)
-		    break;
-		  add_number += add_symbolP->sy_value.X_add_number;
-		  add_symbolP = n;
-		}
-	      fixP->fx_addsy = add_symbolP;
-	      fixP->fx_offset = add_number;
-	    }
-	}
-
-      if (sub_symbolP != NULL && ! sub_symbolP->sy_resolved)
-	resolve_symbol_value (sub_symbolP);
-
-      if (add_symbolP != NULL
-	  && add_symbolP->sy_mri_common)
-	{
-	  know (add_symbolP->sy_value.X_op == O_symbol);
-	  add_number += S_GET_VALUE (add_symbolP);
-	  fixP->fx_offset = add_number;
-	  add_symbolP = fixP->fx_addsy = add_symbolP->sy_value.X_add_symbol;
-	}
-
-      if (add_symbolP)
-	add_symbol_segment = S_GET_SEGMENT (add_symbolP);
-
-      if (sub_symbolP)
-	{
-	  if (add_symbolP == NULL || add_symbol_segment == absolute_section)
-	    {
-	      if (add_symbolP != NULL)
-		{
-		  add_number += S_GET_VALUE (add_symbolP);
-		  add_symbolP = NULL;
-		  fixP->fx_addsy = NULL;
-		}
-
-	      /* It's just -sym.  */
-	      if (S_GET_SEGMENT (sub_symbolP) == absolute_section)
-		{
-		  add_number -= S_GET_VALUE (sub_symbolP);
-		  fixP->fx_subsy = 0;
-		  fixP->fx_done = 1;
-		}
-	      else
-		{
-#ifndef TC_M68K
-		  as_bad_where (fixP->fx_file, fixP->fx_line,
-				_("Negative of non-absolute symbol %s"),
-				S_GET_NAME (sub_symbolP));
-#endif
-		  add_number -= S_GET_VALUE (sub_symbolP);
-		}		/* not absolute */
-
-	      /* if sub_symbol is in the same segment that add_symbol
-		 and add_symbol is either in DATA, TEXT, BSS or ABSOLUTE.  */
-	    }
-	  else if (S_GET_SEGMENT (sub_symbolP) == add_symbol_segment
-		   && SEG_NORMAL (add_symbol_segment))
-	    {
-	      /* Difference of 2 symbols from same segment.  Can't
-		 make difference of 2 undefineds: 'value' means
-		 something different for N_UNDF.  */
-#ifdef TC_I960
-	      /* Makes no sense to use the difference of 2 arbitrary symbols
-	         as the target of a call instruction.  */
-	      if (fixP->fx_tcbit)
-		as_bad_where (fixP->fx_file, fixP->fx_line,
-			      _("callj to difference of 2 symbols"));
-#endif /* TC_I960 */
-	      add_number += S_GET_VALUE (add_symbolP) -
-		S_GET_VALUE (sub_symbolP);
-	      add_symbolP = NULL;
-
-	      if (!TC_FORCE_RELOCATION (fixP))
-		{
-		  fixP->fx_addsy = NULL;
-		  fixP->fx_subsy = NULL;
-		  fixP->fx_done = 1;
-#ifdef TC_M68K /* is this right? */
-		  pcrel = 0;
-		  fixP->fx_pcrel = 0;
-#endif
-		}
-	    }
-	  else
-	    {
-	      /* Different segments in subtraction.  */
-	      know (!(S_IS_EXTERNAL (sub_symbolP) && (S_GET_SEGMENT (sub_symbolP) == absolute_section)));
-
-	      if ((S_GET_SEGMENT (sub_symbolP) == absolute_section))
-		add_number -= S_GET_VALUE (sub_symbolP);
-
-#ifdef DIFF_EXPR_OK
-	      else if (S_GET_SEGMENT (sub_symbolP) == this_segment_type
-#if 0 /* Okay for 68k, at least...  */
-		       && !pcrel
-#endif
-		       )
-		{
-		  /* Make it pc-relative.  */
-		  add_number += (md_pcrel_from (fixP)
-				 - S_GET_VALUE (sub_symbolP));
-		  pcrel = 1;
-		  fixP->fx_pcrel = 1;
-		  sub_symbolP = 0;
-		  fixP->fx_subsy = 0;
-		}
-#endif
-	      else
-		{
-		  as_bad_where (fixP->fx_file, fixP->fx_line,
-				_("Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."),
-				segment_name (S_GET_SEGMENT (sub_symbolP)),
-				S_GET_NAME (sub_symbolP),
-				(long) (fragP->fr_address + where));
-		}
-	    }
-	}
-
-      if (add_symbolP)
-	{
-	  if (add_symbol_segment == this_segment_type && pcrel)
-	    {
-	      /* This fixup was made when the symbol's segment was
-	         SEG_UNKNOWN, but it is now in the local segment.
-	         So we know how to do the address without relocation.  */
-#ifdef TC_I960
-	      /* reloc_callj() may replace a 'call' with a 'calls' or a 'bal',
-	         in which cases it modifies *fixP as appropriate.  In the case
-	         of a 'calls', no further work is required, and *fixP has been
-	         set up to make the rest of the code below a no-op.  */
-	      reloc_callj (fixP);
-#endif /* TC_I960 */
-
-	      add_number += S_GET_VALUE (add_symbolP);
-	      add_number -= md_pcrel_from (fixP);
-
-	      /* We used to do
-		   add_number -= segP->scnhdr.s_vaddr;
-		 if defined (TC_I386) || defined (TE_LYNX).  I now
-		 think that was an error propagated from the case when
-		 we are going to emit the relocation.  If we are not
-		 going to emit the relocation, then we just want to
-		 set add_number to the difference between the symbols.
-		 This is a case that would only arise when there is a
-		 PC relative reference from a section other than .text
-		 to a symbol defined in the same section, and the
-		 reference is not relaxed.  Since jump instructions on
-		 the i386 are relaxed, this could only arise with a
-		 call instruction.  */
-
-	      pcrel = 0;	/* Lie. Don't want further pcrel processing.  */
-	      if (!TC_FORCE_RELOCATION (fixP))
-		{
-		  fixP->fx_addsy = NULL;
-		  fixP->fx_done = 1;
-		}
-	    }
-	  else
-	    {
-	      switch (add_symbol_segment)
-		{
-		case absolute_section:
-#ifdef TC_I960
-		  /* See comment about reloc_callj() above.  */
-		  reloc_callj (fixP);
-#endif /* TC_I960 */
-		  add_number += S_GET_VALUE (add_symbolP);
-		  add_symbolP = NULL;
-
-		  if (!TC_FORCE_RELOCATION (fixP))
-		    {
-		      fixP->fx_addsy = NULL;
-		      fixP->fx_done = 1;
-		    }
-		  break;
-		default:
-
-#if defined(TC_A29K) || (defined(TE_PE) && defined(TC_I386)) || defined(TC_M88K) || defined(TC_OR32)
-		  /* This really should be handled in the linker, but
-		     backward compatibility forbids.  */
-		  add_number += S_GET_VALUE (add_symbolP);
-#else
-		  add_number += S_GET_VALUE (add_symbolP) +
-		    segment_info[S_GET_SEGMENT (add_symbolP)].scnhdr.s_paddr;
-#endif
-		  break;
-
-		case SEG_UNKNOWN:
-#ifdef TC_I960
-		  if ((int) fixP->fx_bit_fixP == 13)
-		    {
-		      /* This is a COBR instruction.  They have only a
-		         13-bit displacement and are only to be used
-		         for local branches: flag as error, don't generate
-		         relocation.  */
-		      as_bad_where (fixP->fx_file, fixP->fx_line,
-				    _("can't use COBR format with external label"));
-		      fixP->fx_addsy = NULL;
-		      fixP->fx_done = 1;
-		      continue;
-		    }
-#endif /* TC_I960 */
-#if ((defined (TC_I386) || defined (TE_LYNX) || defined (TE_AUX)) && !defined(TE_PE)) || defined (COFF_COMMON_ADDEND)
-		  /* 386 COFF uses a peculiar format in which the
-		     value of a common symbol is stored in the .text
-		     segment (I've checked this on SVR3.2 and SCO
-		     3.2.2) Ian Taylor <ian@cygnus.com>.  */
-		  /* This is also true for 68k COFF on sysv machines
-		     (Checked on Motorola sysv68 R3V6 and R3V7.1, and also on
-		     UNIX System V/M68000, Release 1.0 from ATT/Bell Labs)
-		     Philippe De Muyter <phdm@info.ucl.ac.be>.  */
-		  if (S_IS_COMMON (add_symbolP))
-		    add_number += S_GET_VALUE (add_symbolP);
-#endif
-		  break;
-
-		}
-	    }
-	}
-
-      if (pcrel)
-	{
-#if !defined(TC_M88K) && !(defined(TE_PE) && defined(TC_I386)) && !defined(TC_A29K) && !defined(TC_OR32)
-	  /* This adjustment is not correct on the m88k, for which the
-	     linker does all the computation.  */
-	  add_number -= md_pcrel_from (fixP);
-#endif
-	  if (add_symbolP == 0)
-	    fixP->fx_addsy = &abs_symbol;
-#if defined (TC_I386) || defined (TE_LYNX) || defined (TC_I960) || defined (TC_M68K)
-	  /* On the 386 we must adjust by the segment vaddr as well.
-	     Ian Taylor.
-
-	     I changed the i960 to work this way as well.  This is
-	     compatible with the current GNU linker behaviour.  I do
-	     not know what other i960 COFF assemblers do.  This is not
-	     a common case: normally, only assembler code will contain
-	     a PC relative reloc, and only branches which do not
-	     originate in the .text section will have a non-zero
-	     address.
-
-	     I changed the m68k to work this way as well.  This will
-	     break existing PC relative relocs from sections which do
-	     not start at address 0, but it will make ld -r work.
-	     Ian Taylor, 4 Oct 96.  */
-
-	  add_number -= segP->scnhdr.s_vaddr;
-#endif
-	}
-
-      md_apply_fix3 (fixP, (valueT *) & add_number, this_segment_type);
-
-      if (!fixP->fx_bit_fixP && ! fixP->fx_no_overflow)
-	{
-#ifndef TC_M88K
-	  /* The m88k uses the offset field of the reloc to get around
-	     this problem.  */
-	  if ((size == 1
-	       && ((add_number & ~0xFF)
-		   || (fixP->fx_signed && (add_number & 0x80)))
-	       && ((add_number & ~0xFF) != (-1 & ~0xFF)
-		   || (add_number & 0x80) == 0))
-	      || (size == 2
-		  && ((add_number & ~0xFFFF)
-		      || (fixP->fx_signed && (add_number & 0x8000)))
-		  && ((add_number & ~0xFFFF) != (-1 & ~0xFFFF)
-		      || (add_number & 0x8000) == 0)))
-	    {
-	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("Value of %ld too large for field of %d bytes at 0x%lx"),
-			    (long) add_number, size,
-			    (unsigned long) (fragP->fr_address + where));
-	    }
-#endif
-#ifdef WARN_SIGNED_OVERFLOW_WORD
-	  /* Warn if a .word value is too large when treated as a
-	     signed number.  We already know it is not too negative.
-	     This is to catch over-large switches generated by gcc on
-	     the 68k.  */
-	  if (!flag_signed_overflow_ok
-	      && size == 2
-	      && add_number > 0x7fff)
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("Signed .word overflow; switch may be too large; %ld at 0x%lx"),
-			  (long) add_number,
-			  (unsigned long) (fragP->fr_address + where));
-#endif
-	}
-    }
-}
-
-#endif
-
-/* The first entry in a .stab section is special.  */
-
-void
-obj_coff_init_stab_section (seg)
-     segT seg;
-{
-  char *file;
-  char *p;
-  char *stabstr_name;
-  unsigned int stroff;
-
-  /* Make space for this first symbol.  */
-  p = frag_more (12);
-  /* Zero it out.  */
-  memset (p, 0, 12);
-  as_where (&file, (unsigned int *) NULL);
-  stabstr_name = (char *) alloca (strlen (segment_info[seg].name) + 4);
-  strcpy (stabstr_name, segment_info[seg].name);
-  strcat (stabstr_name, "str");
-  stroff = get_stab_string_offset (file, stabstr_name);
-  know (stroff == 1);
-  md_number_to_chars (p, stroff, 4);
-}
-
-/* Fill in the counts in the first entry in a .stab section.  */
-
-static void
-adjust_stab_section(abfd, seg)
-     bfd *abfd;
-     segT seg;
-{
-  segT stabstrseg = SEG_UNKNOWN;
-  const char *secname, *name2;
-  char *name;
-  char *p = NULL;
-  int i, strsz = 0, nsyms;
-  fragS *frag = segment_info[seg].frchainP->frch_root;
-
-  /* Look for the associated string table section.  */
-
-  secname = segment_info[seg].name;
-  name = (char *) alloca (strlen (secname) + 4);
-  strcpy (name, secname);
-  strcat (name, "str");
-
-  for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-    {
-      name2 = segment_info[i].name;
-      if (name2 != NULL && strncmp(name2, name, 8) == 0)
-	{
-	  stabstrseg = i;
-	  break;
-	}
-    }
-
-  /* If we found the section, get its size.  */
-  if (stabstrseg != SEG_UNKNOWN)
-    strsz = size_section (abfd, stabstrseg);
-
-  nsyms = size_section (abfd, seg) / 12 - 1;
-
-  /* Look for the first frag of sufficient size for the initial stab
-     symbol, and collect a pointer to it.  */
-  while (frag && frag->fr_fix < 12)
-    frag = frag->fr_next;
-  assert (frag != 0);
-  p = frag->fr_literal;
-  assert (p != 0);
-
-  /* Write in the number of stab symbols and the size of the string
-     table.  */
-  bfd_h_put_16 (abfd, (bfd_vma) nsyms, (bfd_byte *) p + 6);
-  bfd_h_put_32 (abfd, (bfd_vma) strsz, (bfd_byte *) p + 8);
-}
-
-#endif /* not BFD_ASSEMBLER */
-
 const pseudo_typeS coff_pseudo_table[] =
 {
+  {"ABORT", s_abort, 0},
+  {"appline", obj_coff_ln, 1},
+  /* We accept the .bss directive for backward compatibility with
+     earlier versions of gas.  */
+  {"bss", obj_coff_bss, 0},
   {"def", obj_coff_def, 0},
   {"dim", obj_coff_dim, 0},
   {"endef", obj_coff_endef, 0},
+  {"ident", obj_coff_ident, 0},
   {"line", obj_coff_line, 0},
   {"ln", obj_coff_ln, 0},
-#ifdef BFD_ASSEMBLER
-  {"loc", obj_coff_loc, 0},
-#endif
-  {"appline", obj_coff_ln, 1},
   {"scl", obj_coff_scl, 0},
+  {"sect", obj_coff_section, 0},
+  {"sect.s", obj_coff_section, 0},
+  {"section", obj_coff_section, 0},
+  {"section.s", obj_coff_section, 0},
+  /* FIXME: We ignore the MRI short attribute.  */
   {"size", obj_coff_size, 0},
   {"tag", obj_coff_tag, 0},
   {"type", obj_coff_type, 0},
   {"val", obj_coff_val, 0},
-  {"section", obj_coff_section, 0},
-  {"sect", obj_coff_section, 0},
-  /* FIXME: We ignore the MRI short attribute.  */
-  {"section.s", obj_coff_section, 0},
-  {"sect.s", obj_coff_section, 0},
-  /* We accept the .bss directive for backward compatibility with
-     earlier versions of gas.  */
-  {"bss", obj_coff_bss, 0},
-  {"weak", obj_coff_weak, 0},
-  {"ident", obj_coff_ident, 0},
-#ifndef BFD_ASSEMBLER
-  {"use", obj_coff_section, 0},
-  {"text", obj_coff_text, 0},
-  {"data", obj_coff_data, 0},
-  {"lcomm", obj_coff_lcomm, 0},
-#else
-  {"optim", s_ignore, 0},	/* For sun386i cc (?) */
-#endif
   {"version", s_ignore, 0},
-  {"ABORT", s_abort, 0},
-#if defined( TC_M88K ) || defined ( TC_TIC4X )
-  /* The m88k and tic4x uses sdef instead of def.  */
+  {"loc", obj_coff_loc, 0},
+  {"optim", s_ignore, 0},	/* For sun386i cc (?) */
+  {"weak", obj_coff_weak, 0},
+#if defined TC_TIC4X
+  /* The tic4x uses sdef instead of def.  */
   {"sdef", obj_coff_def, 0},
 #endif
-  {NULL, NULL, 0}		/* end sentinel */
-};				/* coff_pseudo_table */
+  {NULL, NULL, 0}
+};
 
-#ifdef BFD_ASSEMBLER
 
 /* Support for a COFF emulation.  */
 
-static void coff_pop_insert PARAMS ((void));
-static int coff_separate_stab_sections PARAMS ((void));
-
 static void
-coff_pop_insert ()
+coff_pop_insert (void)
 {
   pop_insert (coff_pseudo_table);
 }
 
 static int
-coff_separate_stab_sections ()
+coff_separate_stab_sections (void)
 {
   return 1;
 }
@@ -4686,5 +1854,3 @@ const struct format_ops coff_format_ops =
   coff_obj_read_begin_hook,
   coff_obj_symbol_new_hook
 };
-
-#endif
diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h
index 520055268c28..6fcbc9f06cbb 100644
--- a/gas/config/obj-coff.h
+++ b/gas/config/obj-coff.h
@@ -1,6 +1,6 @@
 /* coff object file format
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -17,24 +17,14 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef OBJ_FORMAT_H
 #define OBJ_FORMAT_H
 
 #define OBJ_COFF 1
 
-#ifndef BFD_ASSEMBLER
-
-#define WORKING_DOT_WORD
-#define WARN_SIGNED_OVERFLOW_WORD
-#define OBJ_COFF_OMIT_OPTIONAL_HEADER
-#define BFD_HEADERS
-#define BFD
-
-#endif
-
 #include "targ-cpu.h"
 
 #include "bfd.h"
@@ -85,11 +75,6 @@
 #endif
 #endif
 
-#ifdef TC_A29K
-#include "coff/a29k.h"
-#define TARGET_FORMAT "coff-a29k-big"
-#endif
-
 #ifdef TC_OR32
 #include "coff/or32.h"
 #define TARGET_FORMAT "coff-or32-big"
@@ -100,6 +85,11 @@
 #define TARGET_FORMAT "coff-Intel-little"
 #endif
 
+#ifdef TC_Z80
+#include "coff/z80.h"
+#define TARGET_FORMAT "coff-z80"
+#endif
+
 #ifdef TC_Z8K
 #include "coff/z8k.h"
 #define TARGET_FORMAT "coff-z8k"
@@ -115,6 +105,11 @@
 #define TARGET_FORMAT "coff-h8500"
 #endif
 
+#ifdef TC_MAXQ20
+#include "coff/maxq.h"
+#define TARGET_FORMAT "coff-maxq"
+#endif
+
 #ifdef TC_SH
 
 #ifdef TE_PE
@@ -142,16 +137,6 @@
 #define TARGET_FORMAT "pe-mips"
 #endif
 
-#ifdef TC_M88K
-#include "coff/m88k.h"
-#define TARGET_FORMAT "coff-m88kbcs"
-#endif
-
-#ifdef TC_W65
-#include "coff/w65.h"
-#define TARGET_FORMAT "coff-w65"
-#endif
-
 #ifdef TC_TIC30
 #include "coff/tic30.h"
 #define TARGET_FORMAT "coff-tic30"
@@ -167,12 +152,6 @@
 #define TARGET_FORMAT "coff1-c54x"
 #endif
 
-#ifdef TC_TIC80
-#include "coff/tic80.h"
-#define TARGET_FORMAT "coff-tic80"
-#define ALIGNMENT_IN_S_FLAGS 1
-#endif
-
 #ifdef TC_MCORE
 #include "coff/mcore.h"
 #ifndef TARGET_FORMAT
@@ -180,65 +159,26 @@
 #endif
 #endif
 
-/* Targets may also set this.  Also, if BFD_ASSEMBLER is defined, this
-   will already have been defined.  */
-#undef SYMBOLS_NEED_BACKPOINTERS
-#define SYMBOLS_NEED_BACKPOINTERS 1
+#ifdef TE_PE
+/* PE weak symbols need USE_UNIQUE.  */
+#define USE_UNIQUE 1
+
+#define obj_set_weak_hook pecoff_obj_set_weak_hook
+#define obj_clear_weak_hook pecoff_obj_clear_weak_hook
+#endif
 
 #ifndef OBJ_COFF_MAX_AUXENTRIES
 #define OBJ_COFF_MAX_AUXENTRIES 1
-#endif /* OBJ_COFF_MAX_AUXENTRIES */
+#endif
 
-extern void coff_obj_symbol_new_hook PARAMS ((symbolS *));
 #define obj_symbol_new_hook coff_obj_symbol_new_hook
-
-extern void coff_obj_read_begin_hook PARAMS ((void));
+#define obj_symbol_clone_hook coff_obj_symbol_clone_hook
 #define obj_read_begin_hook coff_obj_read_begin_hook
 
-/* This file really contains two implementations of the COFF back end.
-   They are in the process of being merged, but this is only a
-   preliminary, mechanical merging.  Many definitions that are
-   identical between the two are still found in both versions.
-
-   The first version, with BFD_ASSEMBLER defined, uses high-level BFD
-   interfaces and data structures.  The second version, with
-   BFD_ASSEMBLER not defined, also uses BFD, but mostly for swapping
-   data structures and for doing the actual I/O.  The latter defines
-   the preprocessor symbols BFD and BFD_HEADERS.  Try not to let this
-   confuse you.
-
-   These two are in the process of being merged, and eventually the
-   BFD_ASSEMBLER version should take over completely.  Release timing
-   issues and namespace problems convinced me to merge the two
-   together in this fashion, a little sooner than I would have liked.
-   The real merge should be much better done by the time the next
-   release comes out.
-
-   For now, the structure of this file is:
-	<common>
-	#ifdef BFD_ASSEMBLER
-	<one version>
-	#else
-	<other version>
-	#endif
-	<common>
-   Unfortunately, the common portions are very small at the moment,
-   and many declarations or definitions are duplicated.  The structure
-   of obj-coff.c is similar.
-
-   See doc/internals.texi for a brief discussion of the history, if
-   you care.
-
-   Ken Raeburn, 5 May 1994.  */
-
-#ifdef BFD_ASSEMBLER
-
 #include "bfd/libcoff.h"
 
 #define OUTPUT_FLAVOR bfd_target_coff_flavour
 
-/* SYMBOL TABLE */
-
 /* Alter the field names, for now, until we've fixed up the other
    references to use the new name.  */
 #ifdef TC_I960
@@ -260,23 +200,14 @@ extern void coff_obj_read_begin_hook PARAMS ((void));
 #define SYM_AUXINFO(S) \
   (&coffsymbol (symbol_get_bfdsym (S))->native[1])
 
-#define DO_NOT_STRIP	0
-
-extern void obj_coff_section PARAMS ((int));
-
 /* The number of auxiliary entries.  */
 #define S_GET_NUMBER_AUXILIARY(s) \
   (coffsymbol (symbol_get_bfdsym (s))->native->u.syment.n_numaux)
 /* The number of auxiliary entries.  */
-#define S_SET_NUMBER_AUXILIARY(s,v)	(S_GET_NUMBER_AUXILIARY (s) = (v))
+#define S_SET_NUMBER_AUXILIARY(s, v)	(S_GET_NUMBER_AUXILIARY (s) = (v))
 
 /* True if a symbol name is in the string table, i.e. its length is > 8.  */
-#define S_IS_STRING(s)		(strlen(S_GET_NAME(s)) > 8 ? 1 : 0)
-
-extern int S_SET_DATA_TYPE PARAMS ((symbolS *, int));
-extern int S_SET_STORAGE_CLASS PARAMS ((symbolS *, int));
-extern int S_GET_STORAGE_CLASS PARAMS ((symbolS *));
-extern void SA_SET_SYM_ENDNDX PARAMS ((symbolS *, symbolS *));
+#define S_IS_STRING(s)		(strlen (S_GET_NAME (s)) > 8 ? 1 : 0)
 
 /* Auxiliary entry macros. SA_ stands for symbol auxiliary.  */
 /* Omit the tv related fields.  */
@@ -294,15 +225,15 @@ extern void SA_SET_SYM_ENDNDX PARAMS ((symbolS *, symbolS *));
 #define SA_GET_SCN_NRELOC(s)	(SYM_AUXENT (s)->x_scn.x_nreloc)
 #define SA_GET_SCN_NLINNO(s)	(SYM_AUXENT (s)->x_scn.x_nlinno)
 
-#define SA_SET_SYM_LNNO(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_lnno=(v))
-#define SA_SET_SYM_SIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_size=(v))
-#define SA_SET_SYM_FSIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_fsize=(v))
-#define SA_SET_SYM_LNNOPTR(s,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_lnnoptr=(v))
-#define SA_SET_SYM_DIMEN(s,i,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_ary.x_dimen[(i)]=(v))
-#define SA_SET_FILE_FNAME(s,v)	strncpy(SYM_AUXENT (s)->x_file.x_fname,(v),FILNMLEN)
-#define SA_SET_SCN_SCNLEN(s,v)	(SYM_AUXENT (s)->x_scn.x_scnlen=(v))
-#define SA_SET_SCN_NRELOC(s,v)	(SYM_AUXENT (s)->x_scn.x_nreloc=(v))
-#define SA_SET_SCN_NLINNO(s,v)	(SYM_AUXENT (s)->x_scn.x_nlinno=(v))
+#define SA_SET_SYM_LNNO(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_lnno = (v))
+#define SA_SET_SYM_SIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_size = (v))
+#define SA_SET_SYM_FSIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_fsize = (v))
+#define SA_SET_SYM_LNNOPTR(s,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_lnnoptr = (v))
+#define SA_SET_SYM_DIMEN(s,i,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_ary.x_dimen[(i)] = (v))
+#define SA_SET_FILE_FNAME(s,v)	strncpy (SYM_AUXENT (s)->x_file.x_fname, (v), FILNMLEN)
+#define SA_SET_SCN_SCNLEN(s,v)	(SYM_AUXENT (s)->x_scn.x_scnlen = (v))
+#define SA_SET_SCN_NRELOC(s,v)	(SYM_AUXENT (s)->x_scn.x_nreloc = (v))
+#define SA_SET_SCN_NLINNO(s,v)	(SYM_AUXENT (s)->x_scn.x_nlinno = (v))
 
 /* Internal use only definitions. SF_ stands for symbol flags.
 
@@ -312,31 +243,31 @@ extern void SA_SET_SYM_ENDNDX PARAMS ((symbolS *, symbolS *));
    more on the balname/callname hack, see tc-i960.h.  b.out is done
    differently.  */
 
-#define SF_I960_MASK	(0x000001ff)	/* Bits 0-8 are used by the i960 port.  */
-#define SF_SYSPROC	(0x0000003f)	/* bits 0-5 are used to store the sysproc number */
-#define SF_IS_SYSPROC	(0x00000040)	/* bit 6 marks symbols that are sysprocs */
-#define SF_BALNAME	(0x00000080)	/* bit 7 marks BALNAME symbols */
-#define SF_CALLNAME	(0x00000100)	/* bit 8 marks CALLNAME symbols */
-
-#define SF_NORMAL_MASK	(0x0000ffff)	/* bits 12-15 are general purpose.  */
-
-#define SF_STATICS	(0x00001000)	/* Mark the .text & all symbols */
-#define SF_DEFINED	(0x00002000)	/* Symbol is defined in this file */
-#define SF_STRING	(0x00004000)	/* Symbol name length > 8 */
-#define SF_LOCAL	(0x00008000)	/* Symbol must not be emitted */
-
-#define SF_DEBUG_MASK	(0xffff0000)	/* bits 16-31 are debug info */
-
-#define SF_FUNCTION	(0x00010000)	/* The symbol is a function */
-#define SF_PROCESS	(0x00020000)	/* Process symbol before write */
-#define SF_TAGGED	(0x00040000)	/* Is associated with a tag */
-#define SF_TAG		(0x00080000)	/* Is a tag */
-#define SF_DEBUG	(0x00100000)	/* Is in debug or abs section */
-#define SF_GET_SEGMENT	(0x00200000)	/* Get the section of the forward symbol.  */
+#define SF_I960_MASK	0x000001ff	/* Bits 0-8 are used by the i960 port.  */
+#define SF_SYSPROC	0x0000003f	/* bits 0-5 are used to store the sysproc number.  */
+#define SF_IS_SYSPROC	0x00000040	/* bit 6 marks symbols that are sysprocs.  */
+#define SF_BALNAME	0x00000080	/* bit 7 marks BALNAME symbols.  */
+#define SF_CALLNAME	0x00000100	/* bit 8 marks CALLNAME symbols.  */
+				  
+#define SF_NORMAL_MASK	0x0000ffff	/* bits 12-15 are general purpose.  */
+				  
+#define SF_STATICS	0x00001000	/* Mark the .text & all symbols.  */
+#define SF_DEFINED	0x00002000	/* Symbol is defined in this file.  */
+#define SF_STRING	0x00004000	/* Symbol name length > 8.  */
+#define SF_LOCAL	0x00008000	/* Symbol must not be emitted.  */
+				  
+#define SF_DEBUG_MASK	0xffff0000	/* bits 16-31 are debug info.  */
+				  
+#define SF_FUNCTION	0x00010000	/* The symbol is a function.  */
+#define SF_PROCESS	0x00020000	/* Process symbol before write.  */
+#define SF_TAGGED	0x00040000	/* Is associated with a tag.  */
+#define SF_TAG		0x00080000	/* Is a tag.  */
+#define SF_DEBUG	0x00100000	/* Is in debug or abs section.  */
+#define SF_GET_SEGMENT	0x00200000	/* Get the section of the forward symbol.  */
 /* All other bits are unused.  */
 
 /* Accessors.  */
-#define SF_GET(s)		(*symbol_get_obj (s))
+#define SF_GET(s)		(* symbol_get_obj (s))
 #define SF_GET_DEBUG(s)		(symbol_get_bfdsym (s)->flags & BSF_DEBUGGING)
 #define SF_SET_DEBUG(s)		(symbol_get_bfdsym (s)->flags |= BSF_DEBUGGING)
 #define SF_GET_NORMAL_FIELD(s)	(SF_GET (s) & SF_NORMAL_MASK)
@@ -351,15 +282,15 @@ extern void SA_SET_SYM_ENDNDX PARAMS ((symbolS *, symbolS *));
 #define SF_GET_TAGGED(s)	(SF_GET (s) & SF_TAGGED)
 #define SF_GET_TAG(s)		(SF_GET (s) & SF_TAG)
 #define SF_GET_GET_SEGMENT(s)	(SF_GET (s) & SF_GET_SEGMENT)
-#define SF_GET_I960(s)		(SF_GET (s) & SF_I960_MASK)	/* used by i960 */
-#define SF_GET_BALNAME(s)	(SF_GET (s) & SF_BALNAME)	/* used by i960 */
-#define SF_GET_CALLNAME(s)	(SF_GET (s) & SF_CALLNAME)	/* used by i960 */
-#define SF_GET_IS_SYSPROC(s)	(SF_GET (s) & SF_IS_SYSPROC)	/* used by i960 */
-#define SF_GET_SYSPROC(s)	(SF_GET (s) & SF_SYSPROC)	/* used by i960 */
+#define SF_GET_I960(s)		(SF_GET (s) & SF_I960_MASK)	/* Used by i960.  */
+#define SF_GET_BALNAME(s)	(SF_GET (s) & SF_BALNAME)	/* Used by i960.  */
+#define SF_GET_CALLNAME(s)	(SF_GET (s) & SF_CALLNAME)	/* Used by i960.  */
+#define SF_GET_IS_SYSPROC(s)	(SF_GET (s) & SF_IS_SYSPROC)	/* Used by i960.  */
+#define SF_GET_SYSPROC(s)	(SF_GET (s) & SF_SYSPROC)	/* Used by i960.  */
 
 /* Modifiers.  */
 #define SF_SET(s,v)		(SF_GET (s) = (v))
-#define SF_SET_NORMAL_FIELD(s,v) (SF_GET (s) |= ((v) & SF_NORMAL_MASK))
+#define SF_SET_NORMAL_FIELD(s,v)(SF_GET (s) |= ((v) & SF_NORMAL_MASK))
 #define SF_SET_DEBUG_FIELD(s,v)	(SF_GET (s) |= ((v) & SF_DEBUG_MASK))
 #define SF_SET_FILE(s)		(SF_GET (s) |= SF_FILE)
 #define SF_SET_STATICS(s)	(SF_GET (s) |= SF_STATICS)
@@ -372,47 +303,38 @@ extern void SA_SET_SYM_ENDNDX PARAMS ((symbolS *, symbolS *));
 #define SF_SET_TAGGED(s)	(SF_GET (s) |= SF_TAGGED)
 #define SF_SET_TAG(s)		(SF_GET (s) |= SF_TAG)
 #define SF_SET_GET_SEGMENT(s)	(SF_GET (s) |= SF_GET_SEGMENT)
-#define SF_SET_I960(s,v)	(SF_GET (s) |= ((v) & SF_I960_MASK))	/* used by i960 */
-#define SF_SET_BALNAME(s)	(SF_GET (s) |= SF_BALNAME)	/* used by i960 */
-#define SF_SET_CALLNAME(s)	(SF_GET (s) |= SF_CALLNAME)	/* used by i960 */
-#define SF_SET_IS_SYSPROC(s)	(SF_GET (s) |= SF_IS_SYSPROC)	/* used by i960 */
-#define SF_SET_SYSPROC(s,v)	(SF_GET (s) |= ((v) & SF_SYSPROC))	/* used by i960 */
+#define SF_SET_I960(s,v)	(SF_GET (s) |= ((v) & SF_I960_MASK))	/* Used by i960.  */
+#define SF_SET_BALNAME(s)	(SF_GET (s) |= SF_BALNAME)		/* Used by i960.  */
+#define SF_SET_CALLNAME(s)	(SF_GET (s) |= SF_CALLNAME)		/* Used by i960.  */
+#define SF_SET_IS_SYSPROC(s)	(SF_GET (s) |= SF_IS_SYSPROC)		/* Used by i960.  */
+#define SF_SET_SYSPROC(s,v)	(SF_GET (s) |= ((v) & SF_SYSPROC))	/* Used by i960.  */
+
 
-/* --------------  Line number handling ------- */
+/*  Line number handling.  */
 extern int text_lineno_number;
 extern int coff_line_base;
 extern int coff_n_line_nos;
+extern symbolS *coff_last_function;
 
-#define obj_emit_lineno(WHERE,LINE,FILE_START)	abort ()
-extern void coff_add_linesym PARAMS ((symbolS *));
-
-void c_dot_file_symbol PARAMS ((const char *filename));
-#define obj_app_file c_dot_file_symbol
-
-extern void coff_frob_symbol PARAMS ((symbolS *, int *));
-extern void coff_adjust_symtab PARAMS ((void));
-extern void coff_frob_section PARAMS ((segT));
-extern void coff_adjust_section_syms PARAMS ((bfd *, asection *, PTR));
-extern void coff_frob_file_after_relocs PARAMS ((void));
-#define obj_frob_symbol(S,P) 	coff_frob_symbol(S,&P)
+#define obj_emit_lineno(WHERE, LINE, FILE_START)	abort ()
+#define obj_app_file(name, app)      c_dot_file_symbol (name, app)
+#define obj_frob_symbol(S,P) 	     coff_frob_symbol (S, & P)
+#define obj_frob_section(S)	     coff_frob_section (S)
+#define obj_frob_file_after_relocs() coff_frob_file_after_relocs ()
 #ifndef obj_adjust_symtab
-#define obj_adjust_symtab()	coff_adjust_symtab()
+#define obj_adjust_symtab()	     coff_adjust_symtab ()
 #endif
-#define obj_frob_section(S)	coff_frob_section (S)
-#define obj_frob_file_after_relocs() coff_frob_file_after_relocs ()
-
-extern symbolS *coff_last_function;
 
 /* Forward the segment of a forwarded symbol, handle assignments that
    just copy symbol values, etc.  */
 #ifndef OBJ_COPY_SYMBOL_ATTRIBUTES
 #ifndef TE_I386AIX
-#define OBJ_COPY_SYMBOL_ATTRIBUTES(dest,src) \
+#define OBJ_COPY_SYMBOL_ATTRIBUTES(dest, src) \
   (SF_GET_GET_SEGMENT (dest) \
    ? (S_SET_SEGMENT (dest, S_GET_SEGMENT (src)), 0) \
    : 0)
 #else
-#define OBJ_COPY_SYMBOL_ATTRIBUTES(dest,src) \
+#define OBJ_COPY_SYMBOL_ATTRIBUTES(dest, src) \
   (SF_GET_GET_SEGMENT (dest) && S_GET_SEGMENT (dest) == SEG_UNKNOWN \
    ? (S_SET_SEGMENT (dest, S_GET_SEGMENT (src)), 0) \
    : 0)
@@ -427,452 +349,6 @@ hey ! Where is the C_LEAFSTAT definition ? i960 - coff support is depending on i
 #endif /* no C_LEAFSTAT */
 #endif /* TC_I960 */
 
-#else /* not BFD_ASSEMBLER */
-
-#if defined TC_A29K || defined TC_OR32
-/* Allow translate from aout relocs to coff relocs.  */
-#define NO_RELOC 20
-#define RELOC_32 1
-#define RELOC_8 2
-#define RELOC_CONST 3
-#define RELOC_CONSTH 4
-#define RELOC_JUMPTARG 5
-#define RELOC_BASE22 6
-#define RELOC_HI22 7
-#define RELOC_LO10 8
-#define RELOC_BASE13 9
-#define RELOC_WDISP22 10
-#define RELOC_WDISP30 11
-#endif
-
-extern const segT N_TYPE_seg[];
-
-/* Magic number of paged executable.  */
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE	0x8300
-
-/* SYMBOL TABLE */
-
-/* Symbol table entry data type.  */
-
-typedef struct
-{
-  /* Basic symbol */
-  struct internal_syment ost_entry;
-  /* Auxiliary entry.  */
-  union internal_auxent ost_auxent[OBJ_COFF_MAX_AUXENTRIES];
-  /* obj_coff internal use only flags.  */
-  unsigned int ost_flags;
-} obj_symbol_type;
-
-#ifndef DO_NOT_STRIP
-#define DO_NOT_STRIP	0
-#endif
-/* Symbol table macros and constants.  */
-
-/* Possible and useful section number in symbol table
-   The values of TEXT, DATA and BSS may not be portable.  */
-
-#define C_ABS_SECTION		N_ABS
-#define C_UNDEF_SECTION		N_UNDEF
-#define C_DEBUG_SECTION		N_DEBUG
-#define C_NTV_SECTION		N_TV
-#define C_PTV_SECTION		P_TV
-#define C_REGISTER_SECTION	50
-
-/* Macros to extract information from a symbol table entry.
-   This syntactic indirection allows independence regarding a.out or coff.
-   The argument (s) of all these macros is a pointer to a symbol table entry.  */
-
-/* Predicates.  */
-/* True if the symbol is external.  */
-#define S_IS_EXTERNAL(s)  \
-  ((s)->sy_symbol.ost_entry.n_scnum == C_UNDEF_SECTION)
-
-/* True if symbol has been defined, ie :
-   section > 0 (DATA, TEXT or BSS)
-   section == 0 and value > 0 (external bss symbol).  */
-#define S_IS_DEFINED(s) \
-  ((s)->sy_symbol.ost_entry.n_scnum > C_UNDEF_SECTION \
-   || ((s)->sy_symbol.ost_entry.n_scnum == C_UNDEF_SECTION \
-       && S_GET_VALUE (s) > 0) \
-   || ((s)->sy_symbol.ost_entry.n_scnum == C_ABS_SECTION))
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) \
-  (!SEG_NORMAL (S_GET_SEGMENT (s)) || (strict && S_IS_WEAK (s)))
-
-/* True if a debug special symbol entry.  */
-#define S_IS_DEBUG(s) \
-  ((s)->sy_symbol.ost_entry.n_scnum == C_DEBUG_SECTION)
-
-/* True if a symbol is local symbol name.  */
-/* A symbol name whose name includes ^A is a gas internal pseudo symbol.  */
-#define S_IS_LOCAL(s) \
-  ((s)->sy_symbol.ost_entry.n_scnum == C_REGISTER_SECTION \
-   || (S_LOCAL_NAME(s) && ! flag_keep_locals && ! S_IS_DEBUG (s)) \
-   || strchr (S_GET_NAME (s), '\001') != NULL \
-   || strchr (S_GET_NAME (s), '\002') != NULL \
-   || (flag_strip_local_absolute \
-       && !S_IS_EXTERNAL(s) \
-       && (s)->sy_symbol.ost_entry.n_scnum == C_ABS_SECTION))
-
-/* True if a symbol is not defined in this file.  */
-#define S_IS_EXTERN(s)		((s)->sy_symbol.ost_entry.n_scnum == 0 \
-				 && S_GET_VALUE (s) == 0)
-
-/* True if a symbol can be multiply defined (bss symbols have this def
-   though it is bad practice).  */
-#define S_IS_COMMON(s)		((s)->sy_symbol.ost_entry.n_scnum == 0 \
-				 && S_GET_VALUE (s) != 0)
-
-/* True if a symbol name is in the string table, i.e. its length is > 8.  */
-#define S_IS_STRING(s)		(strlen(S_GET_NAME(s)) > 8 ? 1 : 0)
-
-/* True if a symbol is defined as weak.  */
-#ifdef TE_PE
-#define S_IS_WEAK(s) \
-  ((s)->sy_symbol.ost_entry.n_sclass == C_NT_WEAK \
-   || (s)->sy_symbol.ost_entry.n_sclass == C_WEAKEXT)
-#else
-#define S_IS_WEAK(s) \
-  ((s)->sy_symbol.ost_entry.n_sclass == C_WEAKEXT)
-#endif
-
-/* Accessors.  */
-/* The name of the symbol.  */
-#define S_GET_NAME(s)		((char*) (s)->sy_symbol.ost_entry.n_offset)
-
-/* The pointer to the string table.  */
-#define S_GET_OFFSET(s)         ((s)->sy_symbol.ost_entry.n_offset)
-
-/* The numeric value of the segment.  */
-#define S_GET_SEGMENT(s)   s_get_segment(s)
-
-/* The data type.  */
-#define S_GET_DATA_TYPE(s)	((s)->sy_symbol.ost_entry.n_type)
-
-/* The storage class.  */
-#define S_GET_STORAGE_CLASS(s)	((s)->sy_symbol.ost_entry.n_sclass)
-
-/* The number of auxiliary entries.  */
-#define S_GET_NUMBER_AUXILIARY(s)	((s)->sy_symbol.ost_entry.n_numaux)
-
-/* Modifiers.  */
-/* Set the name of the symbol.  */
-#define S_SET_NAME(s,v) \
-  ((s)->sy_symbol.ost_entry.n_offset = (unsigned long) (v))
-
-/* Set the offset of the symbol.  */
-#define S_SET_OFFSET(s,v) \
-  ((s)->sy_symbol.ost_entry.n_offset = (v))
-
-/* The numeric value of the segment.  */
-#define S_SET_SEGMENT(s,v) \
-  ((s)->sy_symbol.ost_entry.n_scnum = SEGMENT_TO_SYMBOL_TYPE(v))
-
-/* The data type.  */
-#define S_SET_DATA_TYPE(s,v) \
-  ((s)->sy_symbol.ost_entry.n_type = (v))
-
-/* The storage class.  */
-#define S_SET_STORAGE_CLASS(s,v) \
-  ((s)->sy_symbol.ost_entry.n_sclass = (v))
-
-/* The number of auxiliary entries.  */
-#define S_SET_NUMBER_AUXILIARY(s,v) \
-  ((s)->sy_symbol.ost_entry.n_numaux = (v))
-
-/* Additional modifiers.  */
-/* The symbol is external (does not mean undefined).  */
-#define S_SET_EXTERNAL(s) \
-  { S_SET_STORAGE_CLASS(s, C_EXT) ; SF_CLEAR_LOCAL(s); }
-
-/* Auxiliary entry macros. SA_ stands for symbol auxiliary.  */
-/* Omit the tv related fields.  */
-/* Accessors.  */
-#define SYM_AUXENT(S)	(&(S)->sy_symbol.ost_auxent[0])
-
-#define SA_GET_SYM_TAGNDX(s)	(SYM_AUXENT (s)->x_sym.x_tagndx.l)
-#define SA_GET_SYM_LNNO(s)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_lnno)
-#define SA_GET_SYM_SIZE(s)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_size)
-#define SA_GET_SYM_FSIZE(s)	(SYM_AUXENT (s)->x_sym.x_misc.x_fsize)
-#define SA_GET_SYM_LNNOPTR(s)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_lnnoptr)
-#define SA_GET_SYM_ENDNDX(s)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_endndx.l)
-#define SA_GET_SYM_DIMEN(s,i)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_ary.x_dimen[(i)])
-#define SA_GET_FILE_FNAME(s)	(SYM_AUXENT (s)->x_file.x_fname)
-#define SA_GET_FILE_FNAME_OFFSET(s)  (SYM_AUXENT (s)->x_file.x_n.x_offset)
-#define SA_GET_FILE_FNAME_ZEROS(s)   (SYM_AUXENT (s)->x_file.x_n.x_zeroes)
-#define SA_GET_SCN_SCNLEN(s)	(SYM_AUXENT (s)->x_scn.x_scnlen)
-#define SA_GET_SCN_NRELOC(s)	(SYM_AUXENT (s)->x_scn.x_nreloc)
-#define SA_GET_SCN_NLINNO(s)	(SYM_AUXENT (s)->x_scn.x_nlinno)
-
-/* Modifiers.  */
-#define SA_SET_SYM_TAGNDX(s,v)	(SYM_AUXENT (s)->x_sym.x_tagndx.l=(v))
-#define SA_SET_SYM_LNNO(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_lnno=(v))
-#define SA_SET_SYM_SIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_lnsz.x_size=(v))
-#define SA_SET_SYM_FSIZE(s,v)	(SYM_AUXENT (s)->x_sym.x_misc.x_fsize=(v))
-#define SA_SET_SYM_LNNOPTR(s,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_lnnoptr=(v))
-#define SA_SET_SYM_ENDNDX(s,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_fcn.x_endndx.l=(v))
-#define SA_SET_SYM_DIMEN(s,i,v)	(SYM_AUXENT (s)->x_sym.x_fcnary.x_ary.x_dimen[(i)]=(v))
-#define SA_SET_FILE_FNAME(s,v)	strncpy(SYM_AUXENT (s)->x_file.x_fname,(v),FILNMLEN)
-#define SA_SET_FILE_FNAME_OFFSET(s,v) (SYM_AUXENT (s)->x_file.x_n.x_offset=(v))
-#define SA_SET_FILE_FNAME_ZEROS(s,v)  (SYM_AUXENT (s)->x_file.x_n.x_zeroes=(v))
-#define SA_SET_SCN_SCNLEN(s,v)	(SYM_AUXENT (s)->x_scn.x_scnlen=(v))
-#define SA_SET_SCN_NRELOC(s,v)	(SYM_AUXENT (s)->x_scn.x_nreloc=(v))
-#define SA_SET_SCN_NLINNO(s,v)	(SYM_AUXENT (s)->x_scn.x_nlinno=(v))
-
-/* Internal use only definitions. SF_ stands for symbol flags.
-
-   These values can be assigned to sy_symbol.ost_flags field of a symbolS.
-
-   You'll break i960 if you shift the SYSPROC bits anywhere else.  for
-   more on the balname/callname hack, see tc-i960.h.  b.out is done
-   differently.  */
-
-#define SF_I960_MASK	(0x000001ff)	/* Bits 0-8 are used by the i960 port.  */
-#define SF_SYSPROC	(0x0000003f)	/* bits 0-5 are used to store the sysproc number */
-#define SF_IS_SYSPROC	(0x00000040)	/* bit 6 marks symbols that are sysprocs */
-#define SF_BALNAME	(0x00000080)	/* bit 7 marks BALNAME symbols */
-#define SF_CALLNAME	(0x00000100)	/* bit 8 marks CALLNAME symbols */
-
-#define SF_NORMAL_MASK	(0x0000ffff)	/* bits 12-15 are general purpose.  */
-
-#define SF_STATICS	(0x00001000)	/* Mark the .text & all symbols */
-#define SF_DEFINED	(0x00002000)	/* Symbol is defined in this file */
-#define SF_STRING	(0x00004000)	/* Symbol name length > 8 */
-#define SF_LOCAL	(0x00008000)	/* Symbol must not be emitted */
-
-#define SF_DEBUG_MASK	(0xffff0000)	/* bits 16-31 are debug info */
-
-#define SF_FUNCTION	(0x00010000)	/* The symbol is a function */
-#define SF_PROCESS	(0x00020000)	/* Process symbol before write */
-#define SF_TAGGED	(0x00040000)	/* Is associated with a tag */
-#define SF_TAG		(0x00080000)	/* Is a tag */
-#define SF_DEBUG	(0x00100000)	/* Is in debug or abs section */
-#define SF_GET_SEGMENT	(0x00200000)	/* Get the section of the forward symbol.  */
-#define SF_ADJ_LNNOPTR	(0x00400000)	/* Has a lnnoptr */
-/* All other bits are unused.  */
-
-/* Accessors.  */
-#define SF_GET(s)		((s)->sy_symbol.ost_flags)
-#define SF_GET_NORMAL_FIELD(s)	(SF_GET (s) & SF_NORMAL_MASK)
-#define SF_GET_DEBUG_FIELD(s)	(SF_GET (s) & SF_DEBUG_MASK)
-#define SF_GET_FILE(s)		(SF_GET (s) & SF_FILE)
-#define SF_GET_STATICS(s)	(SF_GET (s) & SF_STATICS)
-#define SF_GET_DEFINED(s)	(SF_GET (s) & SF_DEFINED)
-#define SF_GET_STRING(s)	(SF_GET (s) & SF_STRING)
-#define SF_GET_LOCAL(s)		(SF_GET (s) & SF_LOCAL)
-#define SF_GET_FUNCTION(s)      (SF_GET (s) & SF_FUNCTION)
-#define SF_GET_PROCESS(s)	(SF_GET (s) & SF_PROCESS)
-#define SF_GET_DEBUG(s)		(SF_GET (s) & SF_DEBUG)
-#define SF_GET_TAGGED(s)	(SF_GET (s) & SF_TAGGED)
-#define SF_GET_TAG(s)		(SF_GET (s) & SF_TAG)
-#define SF_GET_GET_SEGMENT(s)	(SF_GET (s) & SF_GET_SEGMENT)
-#define SF_GET_ADJ_LNNOPTR(s)	(SF_GET (s) & SF_ADJ_LNNOPTR)
-#define SF_GET_I960(s)		(SF_GET (s) & SF_I960_MASK)	/* used by i960 */
-#define SF_GET_BALNAME(s)	(SF_GET (s) & SF_BALNAME)	/* used by i960 */
-#define SF_GET_CALLNAME(s)	(SF_GET (s) & SF_CALLNAME)	/* used by i960 */
-#define SF_GET_IS_SYSPROC(s)	(SF_GET (s) & SF_IS_SYSPROC)	/* used by i960 */
-#define SF_GET_SYSPROC(s)	(SF_GET (s) & SF_SYSPROC)	/* used by i960 */
-
-/* Modifiers.  */
-#define SF_SET(s,v)		(SF_GET (s) = (v))
-#define SF_SET_NORMAL_FIELD(s,v) (SF_GET (s) |= ((v) & SF_NORMAL_MASK))
-#define SF_SET_DEBUG_FIELD(s,v)	(SF_GET (s) |= ((v) & SF_DEBUG_MASK))
-#define SF_SET_FILE(s)		(SF_GET (s) |= SF_FILE)
-#define SF_SET_STATICS(s)	(SF_GET (s) |= SF_STATICS)
-#define SF_SET_DEFINED(s)	(SF_GET (s) |= SF_DEFINED)
-#define SF_SET_STRING(s)	(SF_GET (s) |= SF_STRING)
-#define SF_SET_LOCAL(s)		(SF_GET (s) |= SF_LOCAL)
-#define SF_CLEAR_LOCAL(s)	(SF_GET (s) &= ~SF_LOCAL)
-#define SF_SET_FUNCTION(s)      (SF_GET (s) |= SF_FUNCTION)
-#define SF_SET_PROCESS(s)	(SF_GET (s) |= SF_PROCESS)
-#define SF_SET_DEBUG(s)		(SF_GET (s) |= SF_DEBUG)
-#define SF_SET_TAGGED(s)	(SF_GET (s) |= SF_TAGGED)
-#define SF_SET_TAG(s)		(SF_GET (s) |= SF_TAG)
-#define SF_SET_GET_SEGMENT(s)	(SF_GET (s) |= SF_GET_SEGMENT)
-#define SF_SET_ADJ_LNNOPTR(s)	(SF_GET (s) |= SF_ADJ_LNNOPTR)
-#define SF_SET_I960(s,v)	(SF_GET (s) |= ((v) & SF_I960_MASK))	/* used by i960 */
-#define SF_SET_BALNAME(s)	(SF_GET (s) |= SF_BALNAME)	/* used by i960 */
-#define SF_SET_CALLNAME(s)	(SF_GET (s) |= SF_CALLNAME)	/* used by i960 */
-#define SF_SET_IS_SYSPROC(s)	(SF_GET (s) |= SF_IS_SYSPROC)	/* used by i960 */
-#define SF_SET_SYSPROC(s,v)	(SF_GET (s) |= ((v) & SF_SYSPROC))	/* used by i960 */
-
-/* File header macro and type definition.  */
-
-/* File position calculators. Beware to use them when all the
-   appropriate fields are set in the header.  */
-
-#ifdef OBJ_COFF_OMIT_OPTIONAL_HEADER
-#define OBJ_COFF_AOUTHDRSZ (0)
-#else
-#define OBJ_COFF_AOUTHDRSZ (AOUTHDRSZ)
-#endif /* OBJ_COFF_OMIT_OPTIONAL_HEADER */
-
-#define H_GET_FILE_SIZE(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ + \
-	   H_GET_TEXT_SIZE(h) + H_GET_DATA_SIZE(h) + \
-	   H_GET_RELOCATION_SIZE(h) + H_GET_LINENO_SIZE(h) + \
-	   H_GET_SYMBOL_TABLE_SIZE(h) + \
-	   (h)->string_table_size)
-#define H_GET_TEXT_FILE_OFFSET(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ)
-#define H_GET_DATA_FILE_OFFSET(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ + \
-	   H_GET_TEXT_SIZE(h))
-#define H_GET_BSS_FILE_OFFSET(h) 0
-#define H_GET_RELOCATION_FILE_OFFSET(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ + \
-	   H_GET_TEXT_SIZE(h) + H_GET_DATA_SIZE(h))
-#define H_GET_LINENO_FILE_OFFSET(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ + \
-	   H_GET_TEXT_SIZE(h) + H_GET_DATA_SIZE(h) + \
-	   H_GET_RELOCATION_SIZE(h))
-#define H_GET_SYMBOL_TABLE_FILE_OFFSET(h) \
-    (long) (FILHSZ + OBJ_COFF_AOUTHDRSZ + \
-	   H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ + \
-	   H_GET_TEXT_SIZE(h) + H_GET_DATA_SIZE(h) + \
-	   H_GET_RELOCATION_SIZE(h) + H_GET_LINENO_SIZE(h))
-
-/* Accessors.  */
-/* aouthdr.  */
-#define H_GET_MAGIC_NUMBER(h)           ((h)->aouthdr.magic)
-#define H_GET_VERSION_STAMP(h)		((h)->aouthdr.vstamp)
-#define H_GET_TEXT_SIZE(h)              ((h)->aouthdr.tsize)
-#define H_GET_DATA_SIZE(h)              ((h)->aouthdr.dsize)
-#define H_GET_BSS_SIZE(h)               ((h)->aouthdr.bsize)
-#define H_GET_ENTRY_POINT(h)            ((h)->aouthdr.entry)
-#define H_GET_TEXT_START(h)		((h)->aouthdr.text_start)
-#define H_GET_DATA_START(h)		((h)->aouthdr.data_start)
-/* filehdr.  */
-#define H_GET_FILE_MAGIC_NUMBER(h)	((h)->filehdr.f_magic)
-#define H_GET_NUMBER_OF_SECTIONS(h)	((h)->filehdr.f_nscns)
-#define H_GET_TIME_STAMP(h)		((h)->filehdr.f_timdat)
-#define H_GET_SYMBOL_TABLE_POINTER(h)	((h)->filehdr.f_symptr)
-#define H_GET_SYMBOL_COUNT(h)		((h)->filehdr.f_nsyms)
-#define H_GET_SYMBOL_TABLE_SIZE(h)	(H_GET_SYMBOL_COUNT(h) * SYMESZ)
-#define H_GET_SIZEOF_OPTIONAL_HEADER(h)	((h)->filehdr.f_opthdr)
-#define H_GET_FLAGS(h)			((h)->filehdr.f_flags)
-/* Extra fields to achieve bsd a.out compatibility and for convenience.  */
-#define H_GET_RELOCATION_SIZE(h)   	((h)->relocation_size)
-#define H_GET_STRING_SIZE(h)            ((h)->string_table_size)
-#define H_GET_LINENO_SIZE(h)            ((h)->lineno_size)
-
-#ifndef OBJ_COFF_OMIT_OPTIONAL_HEADER
-#define H_GET_HEADER_SIZE(h)		(sizeof (FILHDR) \
-					 + sizeof (AOUTHDR)\
-					 + (H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ))
-#else /* OBJ_COFF_OMIT_OPTIONAL_HEADER */
-#define H_GET_HEADER_SIZE(h)		(sizeof (FILHDR) \
-					 + (H_GET_NUMBER_OF_SECTIONS(h) * SCNHSZ))
-#endif /* OBJ_COFF_OMIT_OPTIONAL_HEADER */
-
-#define H_GET_TEXT_RELOCATION_SIZE(h)	(text_section_header.s_nreloc * RELSZ)
-#define H_GET_DATA_RELOCATION_SIZE(h)	(data_section_header.s_nreloc * RELSZ)
-
-/* Modifiers.  */
-/* aouthdr.  */
-#define H_SET_MAGIC_NUMBER(h,v)         ((h)->aouthdr.magic = (v))
-#define H_SET_VERSION_STAMP(h,v)	((h)->aouthdr.vstamp = (v))
-#define H_SET_TEXT_SIZE(h,v)            ((h)->aouthdr.tsize = (v))
-#define H_SET_DATA_SIZE(h,v)            ((h)->aouthdr.dsize = (v))
-#define H_SET_BSS_SIZE(h,v)             ((h)->aouthdr.bsize = (v))
-#define H_SET_ENTRY_POINT(h,v)          ((h)->aouthdr.entry = (v))
-#define H_SET_TEXT_START(h,v)		((h)->aouthdr.text_start = (v))
-#define H_SET_DATA_START(h,v)		((h)->aouthdr.data_start = (v))
-/* filehdr.  */
-#define H_SET_FILE_MAGIC_NUMBER(h,v)	((h)->filehdr.f_magic = (v))
-#define H_SET_NUMBER_OF_SECTIONS(h,v)	((h)->filehdr.f_nscns = (v))
-#define H_SET_TIME_STAMP(h,v)		((h)->filehdr.f_timdat = (v))
-#define H_SET_SYMBOL_TABLE_POINTER(h,v)	((h)->filehdr.f_symptr = (v))
-#define H_SET_SYMBOL_TABLE_SIZE(h,v)    ((h)->filehdr.f_nsyms = (v))
-#define H_SET_SIZEOF_OPTIONAL_HEADER(h,v) ((h)->filehdr.f_opthdr = (v))
-#define H_SET_FLAGS(h,v)		((h)->filehdr.f_flags = (v))
-/* Extra fields to achieve bsd a.out compatibility and for convenience.  */
-#define H_SET_RELOCATION_SIZE(h,t,d) 	((h)->relocation_size = (t)+(d))
-#define H_SET_STRING_SIZE(h,v)          ((h)->string_table_size = (v))
-#define H_SET_LINENO_SIZE(h,v)          ((h)->lineno_size = (v))
-
-/* Segment flipping.  */
-
-typedef struct
-{
-  struct internal_aouthdr aouthdr;	/* a.out header */
-  struct internal_filehdr filehdr;	/* File header, not machine dep.  */
-  long string_table_size;		/* names + '\0' + sizeof (int) */
-  long relocation_size;			/* Cumulated size of relocation
-					   information for all sections in
-					   bytes.  */
-  long lineno_size;			/* Size of the line number information
-					   table in bytes.  */
-} object_headers;
-
-struct lineno_list
-{
-  struct bfd_internal_lineno line;
-  char *frag;			/* Frag to which the line number is related.  */
-  struct lineno_list *next;	/* Forward chain pointer.  */
-};
-
-#define obj_segment_name(i) (segment_info[(int) (i)].scnhdr.s_name)
-
-#define obj_add_segment(s) obj_coff_add_segment (s)
-
-extern segT obj_coff_add_segment PARAMS ((const char *));
-
-extern void obj_coff_section PARAMS ((int));
-
-extern void c_dot_file_symbol PARAMS ((char *filename));
-#define obj_app_file c_dot_file_symbol
-extern void obj_extra_stuff PARAMS ((object_headers * headers));
-
-extern segT s_get_segment PARAMS ((symbolS *ptr));
-
-extern void c_section_header PARAMS ((struct internal_scnhdr * header,
-				      char *name,
-				      long core_address,
-				      long size,
-				      long data_ptr,
-				      long reloc_ptr,
-				      long lineno_ptr,
-				      long reloc_number,
-				      long lineno_number,
-				      long alignment));
-
-#ifndef tc_coff_symbol_emit_hook
-void tc_coff_symbol_emit_hook PARAMS ((symbolS *));
-#endif
-
-/* Sanity check.  */
-
-#ifdef TC_I960
-#ifndef C_LEAFSTAT
-hey ! Where is the C_LEAFSTAT definition ? i960 - coff support is depending on it.
-#endif /* no C_LEAFSTAT */
-#endif /* TC_I960 */
-extern struct internal_scnhdr data_section_header;
-extern struct internal_scnhdr text_section_header;
-
-/* Forward the segment of a forwarded symbol.  */
-#define OBJ_COPY_SYMBOL_ATTRIBUTES(dest,src) \
-  (SF_GET_GET_SEGMENT (dest) \
-   ? (S_SET_SEGMENT (dest, S_GET_SEGMENT (src)), 0) \
-   : 0)
-
-#ifdef TE_PE
-#define obj_handle_link_once(t) obj_coff_pe_handle_link_once (t)
-extern void obj_coff_pe_handle_link_once ();
-#endif
-
-#endif /* not BFD_ASSEMBLER */
-
 extern const pseudo_typeS coff_pseudo_table[];
 
 #ifndef obj_pop_insert
@@ -896,11 +372,43 @@ extern const pseudo_typeS coff_pseudo_table[];
 
 /* We need 12 bytes at the start of the section to hold some initial
    information.  */
-extern void obj_coff_init_stab_section PARAMS ((segT));
 #define INIT_STAB_SECTION(seg) obj_coff_init_stab_section (seg)
 
 /* Store the number of relocations in the section aux entry.  */
 #define SET_SECTION_RELOCS(sec, relocs, n) \
   SA_SET_SCN_NRELOC (section_symbol (sec), n)
 
+#define obj_app_file(name, app) c_dot_file_symbol (name, app)
+
+extern int  S_SET_DATA_TYPE              (symbolS *, int);
+extern int  S_SET_STORAGE_CLASS          (symbolS *, int);
+extern int  S_GET_STORAGE_CLASS          (symbolS *);
+extern void SA_SET_SYM_ENDNDX            (symbolS *, symbolS *);
+extern void coff_add_linesym             (symbolS *);
+extern void c_dot_file_symbol            (const char *, int);
+extern void coff_frob_symbol             (symbolS *, int *);
+extern void coff_adjust_symtab           (void);
+extern void coff_frob_section            (segT);
+extern void coff_adjust_section_syms     (bfd *, asection *, void *);
+extern void coff_frob_file_after_relocs  (void);
+extern void coff_obj_symbol_new_hook     (symbolS *);
+extern void coff_obj_symbol_clone_hook   (symbolS *, symbolS *);
+extern void coff_obj_read_begin_hook     (void);
+#ifdef TE_PE
+extern void pecoff_obj_set_weak_hook     (symbolS *);
+extern void pecoff_obj_clear_weak_hook   (symbolS *);
+#endif
+extern void obj_coff_section             (int);
+extern segT obj_coff_add_segment         (const char *);
+extern void obj_coff_section             (int);
+extern void c_dot_file_symbol            (const char *, int);
+extern segT s_get_segment                (symbolS *);
+#ifndef tc_coff_symbol_emit_hook
+extern void tc_coff_symbol_emit_hook     (symbolS *);
+#endif
+extern void obj_coff_pe_handle_link_once (void);
+extern void obj_coff_init_stab_section   (segT);
+extern void c_section_header             (struct internal_scnhdr *,
+					  char *, long, long, long, long,
+					  long, long, long, long);
 #endif /* OBJ_FORMAT_H */
diff --git a/gas/config/obj-ecoff.c b/gas/config/obj-ecoff.c
index 69f8d9a89ab8..c1d2c647f0f9 100644
--- a/gas/config/obj-ecoff.c
+++ b/gas/config/obj-ecoff.c
@@ -1,6 +1,6 @@
 /* ECOFF object file format.
-   Copyright 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002
-   Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002,
+   2005  Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    This file was put together by Ian Lance Taylor <ian@cygnus.com>.
 
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define OBJ_HEADER "obj-ecoff.h"
 #include "as.h"
@@ -31,80 +31,13 @@
    gas directory.  This file mostly just arranges to call that one at
    the right times.  */
 
-static int ecoff_sec_sym_ok_for_reloc PARAMS ((asection *));
-static void obj_ecoff_frob_symbol PARAMS ((symbolS *, int *));
-static void ecoff_pop_insert PARAMS ((void));
-static int ecoff_separate_stab_sections PARAMS ((void));
-
-/* These are the pseudo-ops we support in this file.  Only those
-   relating to debugging information are supported here.
-
-   The following pseudo-ops from the Kane and Heinrich MIPS book
-   should be defined here, but are currently unsupported: .aent,
-   .bgnb, .endb, .verstamp, .vreg.
-
-   The following pseudo-ops from the Kane and Heinrich MIPS book are
-   MIPS CPU specific, and should be defined by tc-mips.c: .alias,
-   .extern, .galive, .gjaldef, .gjrlive, .livereg, .noalias, .option,
-   .rdata, .sdata, .set.
-
-   The following pseudo-ops from the Kane and Heinrich MIPS book are
-   not MIPS CPU specific, but are also not ECOFF specific.  I have
-   only listed the ones which are not already in read.c.  It's not
-   completely clear where these should be defined, but tc-mips.c is
-   probably the most reasonable place: .asciiz, .asm0, .endr, .err,
-   .half, .lab, .repeat, .struct, .weakext.  */
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  /* COFF style debugging information. .ln is not used; .loc is used
-     instead.  */
-  { "def",	ecoff_directive_def,	0 },
-  { "dim",	ecoff_directive_dim,	0 },
-  { "endef",	ecoff_directive_endef,	0 },
-  { "file",	ecoff_directive_file,	0 },
-  { "scl",	ecoff_directive_scl,	0 },
-  { "size",	ecoff_directive_size,	0 },
-  { "esize",	ecoff_directive_size,	0 },
-  { "tag",	ecoff_directive_tag,	0 },
-  { "type",	ecoff_directive_type,	0 },
-  { "etype",	ecoff_directive_type,	0 },
-  { "val",	ecoff_directive_val,	0 },
-
-  /* ECOFF specific debugging information.  */
-  { "begin",	ecoff_directive_begin,	0 },
-  { "bend",	ecoff_directive_bend,	0 },
-  { "end",	ecoff_directive_end,	0 },
-  { "ent",	ecoff_directive_ent,	0 },
-  { "fmask",	ecoff_directive_fmask,	0 },
-  { "frame",	ecoff_directive_frame,	0 },
-  { "loc",	ecoff_directive_loc,	0 },
-  { "mask",	ecoff_directive_mask,	0 },
-
-  /* Other ECOFF directives.  */
-  { "extern",	ecoff_directive_extern,	0 },
-
-#ifndef TC_MIPS
-  /* For TC_MIPS, tc-mips.c adds this.  */
-  { "weakext",	ecoff_directive_weakext, 0 },
-#endif
-
-  /* These are used on Irix.  I don't know how to implement them.  */
-  { "bgnb",	s_ignore,		0 },
-  { "endb",	s_ignore,		0 },
-  { "verstamp",	s_ignore,		0 },
-
-  /* Sentinel.  */
-  { NULL,	s_ignore,		0 }
-};
-
 /* Set section VMAs and GP values before reloc processing.  */
 
 void
-ecoff_frob_file_before_fix ()
+ecoff_frob_file_before_fix (void)
 {
   bfd_vma addr;
-  asection **sec;
+  asection *sec;
 
   /* Set the section VMA values.  We force the .sdata and .sbss
      sections to the end to ensure that their VMA addresses are close
@@ -128,7 +61,8 @@ ecoff_frob_file_before_fix ()
 
      I don't know if section ordering on the MIPS is important.  */
 
-  static const char *const names[] = {
+  static const char *const names[] =
+  {
     /* text segment */
     ".text", ".rdata", ".init", ".fini",
     /* data segment */
@@ -144,22 +78,21 @@ ecoff_frob_file_before_fix ()
 
   addr = 0;
   for (i = 0; i < n_names; i++)
-    secs[i] = 0;
+    secs[i] = NULL;
 
-  for (sec = &stdoutput->sections; *sec != (asection *) NULL; )
+  for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
     {
       for (i = 0; i < n_names; i++)
-	if (!strcmp ((*sec)->name, names[i]))
+	if (!strcmp (sec->name, names[i]))
 	  {
-	    secs[i] = *sec;
+	    secs[i] = sec;
 	    bfd_section_list_remove (stdoutput, sec);
 	    break;
 	  }
       if (i == n_names)
 	{
-	  bfd_set_section_vma (stdoutput, *sec, addr);
-	  addr += bfd_section_size (stdoutput, *sec);
-	  sec = &(*sec)->next;
+	  bfd_set_section_vma (stdoutput, sec, addr);
+	  addr += bfd_section_size (stdoutput, sec);
 	}
     }
   for (i = 0; i < n_names; i++)
@@ -170,7 +103,7 @@ ecoff_frob_file_before_fix ()
       }
   for (i = n_names - 1; i >= 0; i--)
     if (secs[i])
-      bfd_section_list_insert (stdoutput, &stdoutput->sections, secs[i]);
+      bfd_section_list_prepend (stdoutput, secs[i]);
 
   /* Fill in the register masks.  */
   {
@@ -203,7 +136,7 @@ ecoff_frob_file_before_fix ()
 /* Swap out the symbols and debugging information for BFD.  */
 
 void
-ecoff_frob_file ()
+ecoff_frob_file (void)
 {
   const struct ecoff_debug_swap * const debug_swap
     = &ecoff_backend (stdoutput)->debug_swap;
@@ -221,7 +154,7 @@ ecoff_frob_file ()
   set = buf;
 #define SET(ptr, count, type, size) \
   if (hdr->count == 0) \
-    ecoff_data (stdoutput)->debug_info.ptr = (type) NULL; \
+    ecoff_data (stdoutput)->debug_info.ptr = NULL; \
   else \
     { \
       ecoff_data (stdoutput)->debug_info.ptr = (type) set; \
@@ -229,16 +162,16 @@ ecoff_frob_file ()
     }
 
   SET (line, cbLine, unsigned char *, sizeof (unsigned char));
-  SET (external_dnr, idnMax, PTR, debug_swap->external_dnr_size);
-  SET (external_pdr, ipdMax, PTR, debug_swap->external_pdr_size);
-  SET (external_sym, isymMax, PTR, debug_swap->external_sym_size);
-  SET (external_opt, ioptMax, PTR, debug_swap->external_opt_size);
+  SET (external_dnr, idnMax, void *, debug_swap->external_dnr_size);
+  SET (external_pdr, ipdMax, void *, debug_swap->external_pdr_size);
+  SET (external_sym, isymMax, void *, debug_swap->external_sym_size);
+  SET (external_opt, ioptMax, void *, debug_swap->external_opt_size);
   SET (external_aux, iauxMax, union aux_ext *, sizeof (union aux_ext));
   SET (ss, issMax, char *, sizeof (char));
   SET (ssext, issExtMax, char *, sizeof (char));
-  SET (external_rfd, crfd, PTR, debug_swap->external_rfd_size);
-  SET (external_fdr, ifdMax, PTR, debug_swap->external_fdr_size);
-  SET (external_ext, iextMax, PTR, debug_swap->external_ext_size);
+  SET (external_rfd, crfd, void *, debug_swap->external_rfd_size);
+  SET (external_fdr, ifdMax, void *, debug_swap->external_fdr_size);
+  SET (external_ext, iextMax, void *, debug_swap->external_ext_size);
 #undef SET
 }
 
@@ -247,9 +180,7 @@ ecoff_frob_file ()
    information to be stored in the native field of the symbol.  */
 
 void
-obj_ecoff_set_ext (sym, ext)
-     symbolS *sym;
-     EXTR *ext;
+obj_ecoff_set_ext (symbolS *sym, EXTR *ext)
 {
   const struct ecoff_debug_swap * const debug_swap
     = &ecoff_backend (stdoutput)->debug_swap;
@@ -264,62 +195,121 @@ obj_ecoff_set_ext (sym, ext)
 }
 
 static int
-ecoff_sec_sym_ok_for_reloc (sec)
-     asection *sec ATTRIBUTE_UNUSED;
+ecoff_sec_sym_ok_for_reloc (asection *sec ATTRIBUTE_UNUSED)
 {
   return 1;
 }
 
 static void
-obj_ecoff_frob_symbol (sym, puntp)
-     symbolS *sym;
-     int *puntp ATTRIBUTE_UNUSED;
+obj_ecoff_frob_symbol (symbolS *sym, int *puntp ATTRIBUTE_UNUSED)
 {
   ecoff_frob_symbol (sym);
 }
 
 static void
-ecoff_pop_insert ()
+ecoff_pop_insert (void)
 {
   pop_insert (obj_pseudo_table);
 }
 
 static int
-ecoff_separate_stab_sections ()
+ecoff_separate_stab_sections (void)
 {
   return 0;
 }
 
+/* These are the pseudo-ops we support in this file.  Only those
+   relating to debugging information are supported here.
+
+   The following pseudo-ops from the Kane and Heinrich MIPS book
+   should be defined here, but are currently unsupported: .aent,
+   .bgnb, .endb, .verstamp, .vreg.
+
+   The following pseudo-ops from the Kane and Heinrich MIPS book are
+   MIPS CPU specific, and should be defined by tc-mips.c: .alias,
+   .extern, .galive, .gjaldef, .gjrlive, .livereg, .noalias, .option,
+   .rdata, .sdata, .set.
+
+   The following pseudo-ops from the Kane and Heinrich MIPS book are
+   not MIPS CPU specific, but are also not ECOFF specific.  I have
+   only listed the ones which are not already in read.c.  It's not
+   completely clear where these should be defined, but tc-mips.c is
+   probably the most reasonable place: .asciiz, .asm0, .endr, .err,
+   .half, .lab, .repeat, .struct, .weakext.  */
+
+const pseudo_typeS obj_pseudo_table[] =
+{
+  /* COFF style debugging information. .ln is not used; .loc is used
+     instead.  */
+  { "def",	ecoff_directive_def,	0 },
+  { "dim",	ecoff_directive_dim,	0 },
+  { "endef",	ecoff_directive_endef,	0 },
+  { "file",	ecoff_directive_file,	0 },
+  { "scl",	ecoff_directive_scl,	0 },
+  { "size",	ecoff_directive_size,	0 },
+  { "esize",	ecoff_directive_size,	0 },
+  { "tag",	ecoff_directive_tag,	0 },
+  { "type",	ecoff_directive_type,	0 },
+  { "etype",	ecoff_directive_type,	0 },
+  { "val",	ecoff_directive_val,	0 },
+
+  /* ECOFF specific debugging information.  */
+  { "begin",	ecoff_directive_begin,	0 },
+  { "bend",	ecoff_directive_bend,	0 },
+  { "end",	ecoff_directive_end,	0 },
+  { "ent",	ecoff_directive_ent,	0 },
+  { "fmask",	ecoff_directive_fmask,	0 },
+  { "frame",	ecoff_directive_frame,	0 },
+  { "loc",	ecoff_directive_loc,	0 },
+  { "mask",	ecoff_directive_mask,	0 },
+
+  /* Other ECOFF directives.  */
+  { "extern",	ecoff_directive_extern,	0 },
+
+#ifndef TC_MIPS
+  /* For TC_MIPS, tc-mips.c adds this.  */
+  { "weakext",	ecoff_directive_weakext, 0 },
+#endif
+
+  /* These are used on Irix.  I don't know how to implement them.  */
+  { "bgnb",	s_ignore,		0 },
+  { "endb",	s_ignore,		0 },
+  { "verstamp",	s_ignore,		0 },
+
+  /* Sentinel.  */
+  { NULL,	s_ignore,		0 }
+};
+
 const struct format_ops ecoff_format_ops =
 {
   bfd_target_ecoff_flavour,
-  0,	/* dfl_leading_underscore */
+  0,	/* dfl_leading_underscore.  */
 
   /* FIXME: A comment why emit_section_symbols is different here (1) from
      the single-format definition (0) would be in order.  */
-  1,	/* emit_section_symbols */
-  0,	/* begin */
+  1,	/* emit_section_symbols.  */
+  0,	/* begin.  */
   ecoff_new_file,
   obj_ecoff_frob_symbol,
   ecoff_frob_file,
-  0,	/* frob_file_before_adjust */
+  0,	/* frob_file_before_adjust.  */
   ecoff_frob_file_before_fix,
-  0,	/* frob_file_after_relocs */
-  0,	/* s_get_size */
-  0,	/* s_set_size */
-  0,	/* s_get_align */
-  0,	/* s_set_align */
-  0,	/* s_get_other */
-  0,	/* s_set_other */
-  0,	/* s_get_desc */
-  0,	/* s_set_desc */
-  0,	/* s_get_type */
-  0,	/* s_set_type */
-  0,	/* copy_symbol_attributes */
+  0,	/* frob_file_after_relocs.  */
+  0,	/* s_get_size.  */
+  0,	/* s_set_size.  */
+  0,	/* s_get_align.  */
+  0,	/* s_set_align.  */
+  0,	/* s_get_other.  */
+  0,	/* s_set_other.  */
+  0,	/* s_get_desc.  */
+  0,	/* s_set_desc.  */
+  0,	/* s_get_type.  */
+  0,	/* s_set_type.  */
+  0,	/* copy_symbol_attributes.  */
   ecoff_generate_asm_lineno,
   ecoff_stab,
   ecoff_separate_stab_sections,
-  0,	/* init_stab_section */
+  0,	/* init_stab_section.  */
   ecoff_sec_sym_ok_for_reloc,
   ecoff_pop_insert,
   ecoff_set_ext,
diff --git a/gas/config/obj-ecoff.h b/gas/config/obj-ecoff.h
index 54ee0438db39..fdec4bc14280 100644
--- a/gas/config/obj-ecoff.h
+++ b/gas/config/obj-ecoff.h
@@ -1,5 +1,5 @@
 /* ECOFF object file format header file.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1999, 2002
+   Copyright 1993, 1994, 1995, 1996, 1997, 1999, 2002, 2004, 2005
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    Written by Ian Lance Taylor <ian@cygnus.com>.
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define OBJ_ECOFF 1
 
@@ -50,12 +50,10 @@ struct ecoff_sy_obj
 #define obj_frob_symbol(symp, punt) ecoff_frob_symbol (symp)
 
 /* Set section VMAs and GP.  */
-extern void ecoff_frob_file_before_fix PARAMS ((void));
 #define obj_frob_file_before_fix() ecoff_frob_file_before_fix ()
 
 /* This is used to write the symbolic data in the format that BFD
    expects it.  */
-extern void ecoff_frob_file PARAMS ((void));
 #define obj_frob_file() ecoff_frob_file ()
 
 /* We use the ECOFF functions as our hooks.  */
@@ -63,7 +61,7 @@ extern void ecoff_frob_file PARAMS ((void));
 #define obj_symbol_new_hook ecoff_symbol_new_hook
 
 /* Record file switches in the ECOFF symbol table.  */
-#define obj_app_file(name) ecoff_new_file (name)
+#define obj_app_file(name, app) ecoff_new_file (name, app)
 
 /* At the moment we don't want to do any stabs processing in read.c.  */
 #define OBJ_PROCESS_STAB(seg, what, string, type, other, desc) \
@@ -73,4 +71,7 @@ extern void ecoff_frob_file PARAMS ((void));
 #define obj_sec_sym_ok_for_reloc(SEC)	1
 
 #define obj_ecoff_set_ext ecoff_set_ext
-extern void obj_ecoff_set_ext PARAMS ((symbolS *, EXTR *));
+
+extern void ecoff_frob_file_before_fix (void);
+extern void ecoff_frob_file (void);
+extern void obj_ecoff_set_ext (symbolS *, EXTR *);
diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index 14d48f2ee74d..f922149cae0d 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -1,6 +1,6 @@
 /* ELF object file format
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define OBJ_HEADER "obj-elf.h"
 #include "as.h"
@@ -53,6 +53,10 @@
 #include "elf/i370.h"
 #endif
 
+#ifdef TC_I386
+#include "elf/x86-64.h"
+#endif
+
 static void obj_elf_line (int);
 static void obj_elf_size (int);
 static void obj_elf_type (int);
@@ -65,6 +69,7 @@ static void obj_elf_subsection (int);
 static void obj_elf_popsection (int);
 static void obj_elf_tls_common (int);
 static void obj_elf_lcomm (int);
+static void obj_elf_struct (int);
 
 static const pseudo_typeS elf_pseudo_table[] =
 {
@@ -110,9 +115,12 @@ static const pseudo_typeS elf_pseudo_table[] =
   /* These are used for dwarf2.  */
   { "file", (void (*) (int)) dwarf2_directive_file, 0 },
   { "loc",  dwarf2_directive_loc,  0 },
+  { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
 
   /* We need to trap the section changing calls to handle .previous.  */
   {"data", obj_elf_data, 0},
+  {"offset", obj_elf_struct, 0},
+  {"struct", obj_elf_struct, 0},
   {"text", obj_elf_text, 0},
 
   {"tls_common", obj_elf_tls_common, 0},
@@ -171,6 +179,8 @@ static const pseudo_typeS ecoff_debug_pseudo_table[] =
 
 /* This is called when the assembler starts.  */
 
+asection *elf_com_section_ptr;
+
 void
 elf_begin (void)
 {
@@ -183,6 +193,7 @@ elf_begin (void)
   symbol_table_insert (section_symbol (s));
   s = bfd_get_section_by_name (stdoutput, BSS_SECTION_NAME);
   symbol_table_insert (section_symbol (s));
+  elf_com_section_ptr = bfd_com_section_ptr;
 }
 
 void
@@ -236,32 +247,38 @@ elf_sec_sym_ok_for_reloc (asection *sec)
 }
 
 void
-elf_file_symbol (const char *s)
+elf_file_symbol (const char *s, int appfile)
 {
-  symbolS *sym;
+  if (!appfile
+      || symbol_rootP == NULL
+      || symbol_rootP->bsym == NULL
+      || (symbol_rootP->bsym->flags & BSF_FILE) == 0)
+    {
+      symbolS *sym;
 
-  sym = symbol_new (s, absolute_section, 0, NULL);
-  symbol_set_frag (sym, &zero_address_frag);
-  symbol_get_bfdsym (sym)->flags |= BSF_FILE;
+      sym = symbol_new (s, absolute_section, 0, NULL);
+      symbol_set_frag (sym, &zero_address_frag);
+      symbol_get_bfdsym (sym)->flags |= BSF_FILE;
 
-  if (symbol_rootP != sym)
-    {
-      symbol_remove (sym, &symbol_rootP, &symbol_lastP);
-      symbol_insert (sym, symbol_rootP, &symbol_rootP, &symbol_lastP);
+      if (symbol_rootP != sym)
+	{
+	  symbol_remove (sym, &symbol_rootP, &symbol_lastP);
+	  symbol_insert (sym, symbol_rootP, &symbol_rootP, &symbol_lastP);
 #ifdef DEBUG
-      verify_symbol_chain (symbol_rootP, symbol_lastP);
+	  verify_symbol_chain (symbol_rootP, symbol_lastP);
 #endif
+	}
     }
 
 #ifdef NEED_ECOFF_DEBUG
-  ecoff_new_file (s);
+  ecoff_new_file (s, appfile);
 #endif
 }
 
 /* Called from read.c:s_comm after we've parsed .comm symbol, size.
    Parse a possible alignment value.  */
 
-static symbolS *
+symbolS *
 elf_common_parse (int ignore ATTRIBUTE_UNUSED, symbolS *symbolP, addressT size)
 {
   addressT align = 0;
@@ -325,7 +342,7 @@ elf_common_parse (int ignore ATTRIBUTE_UNUSED, symbolS *symbolP, addressT size)
       S_SET_VALUE (symbolP, size);
       S_SET_ALIGN (symbolP, align);
       S_SET_EXTERNAL (symbolP);
-      S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
+      S_SET_SEGMENT (symbolP, elf_com_section_ptr);
     }
 
   symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
@@ -469,6 +486,18 @@ struct section_stack
 
 static struct section_stack *section_stack;
 
+static bfd_boolean
+get_section (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *inf)
+{
+  const char *gname = inf;
+  const char *group_name = elf_group_name (sec);
+  
+  return (group_name == gname
+	  || (group_name != NULL
+	      && gname != NULL
+	      && strcmp (group_name, gname) == 0));
+}
+
 /* Handle the .section pseudo-op.  This code supports two different
    syntaxes.
 
@@ -499,6 +528,7 @@ obj_elf_change_section (const char *name,
   asection *old_sec;
   segT sec;
   flagword flags;
+  const struct elf_backend_data *bed;
   const struct bfd_elf_special_section *ssect;
 
 #ifdef md_flush_pending_output
@@ -520,9 +550,18 @@ obj_elf_change_section (const char *name,
   previous_section = now_seg;
   previous_subsection = now_subseg;
 
-  old_sec = bfd_get_section_by_name (stdoutput, name);
-  sec = subseg_new (name, 0);
-  ssect = _bfd_elf_get_sec_type_attr (stdoutput, name);
+  old_sec = bfd_get_section_by_name_if (stdoutput, name, get_section,
+					(void *) group_name);
+  if (old_sec)
+    {
+      sec = old_sec;
+      subseg_set (sec, 0);
+    }
+  else
+    sec = subseg_force_new (name, 0);
+
+  bed = get_elf_backend_data (stdoutput);
+  ssect = (*bed->get_sec_type_attr) (stdoutput, sec);
 
   if (ssect != NULL)
     {
@@ -538,7 +577,16 @@ obj_elf_change_section (const char *name,
 		 .section .init_array,"aw",@progbits
 
 		 for __attribute__ ((section (".init_array"))).
+		 "@progbits" is incorrect.  Also for x86-64 large bss
+		 sections, gcc, as of 2005-07-06, will emit
+
+		 .section .lbss,"aw",@progbits
+
 		 "@progbits" is incorrect.  */
+#ifdef TC_I386
+	      && (bed->s->arch_size != 64
+		  || !(ssect->attr & SHF_X86_64_LARGE))
+#endif
 	      && ssect->type != SHT_INIT_ARRAY
 	      && ssect->type != SHT_FINI_ARRAY
 	      && ssect->type != SHT_PREINIT_ARRAY)
@@ -580,10 +628,15 @@ obj_elf_change_section (const char *name,
 		       || strcmp (name, ".strtab") == 0
 		       || strcmp (name, ".symtab") == 0))
 	    override = TRUE;
+	  /* .note.GNU-stack can have SHF_EXECINSTR.  */
+	  else if (attr == SHF_EXECINSTR
+		   && strcmp (name, ".note.GNU-stack") == 0)
+	    override = TRUE;
 	  else
 	    {
-	      as_warn (_("setting incorrect section attributes for %s"),
-		       name);
+	      if (group_name == NULL)
+		as_warn (_("setting incorrect section attributes for %s"),
+			 name);
 	      override = TRUE;
 	    }
 	}
@@ -591,11 +644,6 @@ obj_elf_change_section (const char *name,
 	attr |= ssect->attr;
     }
 
-  if (type != SHT_NULL)
-    elf_section_type (sec) = type;
-  if (attr != 0)
-    elf_section_flags (sec) = attr;
-
   /* Convert ELF type and flags to BFD flags.  */
   flags = (SEC_RELOC
 	   | ((attr & SHF_WRITE) ? 0 : SEC_READONLY)
@@ -609,16 +657,20 @@ obj_elf_change_section (const char *name,
   flags = md_elf_section_flags (flags, attr, type);
 #endif
 
+  if (linkonce)
+    flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
+
   if (old_sec == NULL)
     {
       symbolS *secsym;
 
+      elf_section_type (sec) = type;
+      elf_section_flags (sec) = attr;
+
       /* Prevent SEC_HAS_CONTENTS from being inadvertently set.  */
       if (type == SHT_NOBITS)
 	seg_info (sec)->bss = 1;
 
-      if (linkonce)
-	flags |= SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD;
       bfd_set_section_flags (stdoutput, sec, flags);
       if (flags & SEC_MERGE)
 	sec->entsize = entsize;
@@ -631,22 +683,26 @@ obj_elf_change_section (const char *name,
       else
 	symbol_table_insert (section_symbol (sec));
     }
-  else if (attr != 0)
+  else
     {
-      /* If section attributes are specified the second time we see a
-	 particular section, then check that they are the same as we
-	 saw the first time.  */
-      if (((old_sec->flags ^ flags)
-	   & (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
-	      | SEC_EXCLUDE | SEC_SORT_ENTRIES | SEC_MERGE | SEC_STRINGS
-	      | SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD
-	      | SEC_THREAD_LOCAL)))
-	as_warn (_("ignoring changed section attributes for %s"), name);
-      if ((flags & SEC_MERGE) && old_sec->entsize != (unsigned) entsize)
-	as_warn (_("ignoring changed section entity size for %s"), name);
-      if ((attr & SHF_GROUP) != 0
-	  && strcmp (elf_group_name (old_sec), group_name) != 0)
-	as_warn (_("ignoring new section group for %s"), name);
+      if (type != SHT_NULL
+	  && (unsigned) type != elf_section_type (old_sec))
+	as_warn (_("ignoring changed section type for %s"), name);
+
+      if (attr != 0)
+	{
+	  /* If section attributes are specified the second time we see a
+	     particular section, then check that they are the same as we
+	     saw the first time.  */
+	  if (((old_sec->flags ^ flags)
+	       & (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
+		  | SEC_EXCLUDE | SEC_SORT_ENTRIES | SEC_MERGE | SEC_STRINGS
+		  | SEC_LINK_ONCE | SEC_LINK_DUPLICATES_DISCARD
+		  | SEC_THREAD_LOCAL)))
+	    as_warn (_("ignoring changed section attributes for %s"), name);
+	  if ((flags & SEC_MERGE) && old_sec->entsize != (unsigned) entsize)
+	    as_warn (_("ignoring changed section entity size for %s"), name);
+	}
     }
 
 #ifdef md_elf_section_change_hook
@@ -748,6 +804,12 @@ obj_elf_section_type (char *str, size_t len)
     return SHT_NOBITS;
   if (len == 4 && strncmp (str, "note", 4) == 0)
     return SHT_NOTE;
+  if (len == 10 && strncmp (str, "init_array", 10) == 0)
+    return SHT_INIT_ARRAY;
+  if (len == 10 && strncmp (str, "fini_array", 10) == 0)
+    return SHT_FINI_ARRAY;
+  if (len == 13 && strncmp (str, "preinit_array", 13) == 0)
+    return SHT_PREINIT_ARRAY;
 
 #ifdef md_elf_section_type
   {
@@ -996,6 +1058,24 @@ obj_elf_text (int i)
 #endif
 }
 
+/* Change to the *ABS* section.  */
+
+void
+obj_elf_struct (int i)
+{
+#ifdef md_flush_pending_output
+  md_flush_pending_output ();
+#endif
+
+  previous_section = now_seg;
+  previous_subsection = now_subseg;
+  s_struct (i);
+
+#ifdef md_elf_section_change_hook
+  md_elf_section_change_hook ();
+#endif
+}
+
 static void
 obj_elf_subsection (int ignore ATTRIBUTE_UNUSED)
 {
@@ -1775,17 +1855,6 @@ elf_frob_symbol (symbolS *symp, int *puntp)
       && (symbol_get_bfdsym (symp)->flags & BSF_FUNCTION) == 0)
     symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
 #endif
-
-#if 0 /* TC_PPC */
-  /* If TC_PPC is defined, we used to force the type of a symbol to be
-     BSF_OBJECT if it was otherwise unset.  This was required by some
-     version of VxWorks.  Thomas de Lellis <tdel@windriver.com> says
-     that this is no longer needed, so it is now commented out.  */
-  if ((symbol_get_bfdsym (symp)->flags
-       & (BSF_FUNCTION | BSF_FILE | BSF_SECTION_SYM)) == 0
-      && S_IS_DEFINED (symp))
-    symbol_get_bfdsym (symp)->flags |= BSF_OBJECT;
-#endif
 }
 
 struct group_list
@@ -1864,6 +1933,7 @@ elf_frob_file (void)
       flagword flags;
       struct symbol *sy;
       int has_sym;
+      bfd_size_type size;
 
       flags = SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_GROUP;
       for (s = list.head[i]; s != NULL; s = elf_next_in_group (s))
@@ -1904,8 +1974,9 @@ elf_frob_file (void)
       if (has_sym)
 	elf_group_id (s) = sy->bsym;
 
-      s->_raw_size = 4 * (list.elt_count[i] + 1);
-      s->contents = frag_more (s->_raw_size);
+      size = 4 * (list.elt_count[i] + 1);
+      bfd_set_section_size (stdoutput, s, size);
+      s->contents = (unsigned char *) frag_more (size);
       frag_now->fr_fix = frag_now_fix_octets ();
     }
 
@@ -2014,7 +2085,8 @@ elf_frob_file_after_relocs (void)
 	 to force the ELF backend to allocate a file position, and then
 	 write out the data.  FIXME: Is this really the best way to do
 	 this?  */
-      sec->_raw_size = bfd_ecoff_debug_size (stdoutput, &debug, debug_swap);
+      bfd_set_section_size
+	(stdoutput, sec, bfd_ecoff_debug_size (stdoutput, &debug, debug_swap));
 
       /* Pass BUF to bfd_set_section_contents because this will
 	 eventually become a call to fwrite, and ISO C prohibits
diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h
index e71379721a26..7ff9ef09aa3c 100644
--- a/gas/config/obj-elf.h
+++ b/gas/config/obj-elf.h
@@ -1,6 +1,6 @@
 /* ELF object file format.
    Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-   2002, 2003 Free Software Foundation, Inc.
+   2002, 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* HP PA-RISC support was contributed by the Center for Software Science
    at the University of Utah.  */
@@ -156,10 +156,17 @@ extern void elf_frob_file_before_adjust (void);
 #endif
 extern void elf_frob_file_after_relocs (void);
 
+/* If the target doesn't have special processing for labels, take care of
+   dwarf2 output at the object file level.  */
+#ifndef tc_frob_label
+#include "dwarf2dbg.h"
+#define obj_frob_label  dwarf2_emit_label
+#endif
+
 #ifndef obj_app_file
 #define obj_app_file elf_file_symbol
 #endif
-extern void elf_file_symbol (const char *);
+extern void elf_file_symbol (const char *, int);
 
 extern void obj_elf_section_change_hook (void);
 
@@ -241,10 +248,11 @@ extern void elf_pop_insert (void);
 
 #ifndef OBJ_MAYBE_ELF
 #define obj_ecoff_set_ext elf_ecoff_set_ext
-#ifdef ANSI_PROTOTYPES
 struct ecoff_extr;
-#endif
 extern void elf_ecoff_set_ext (symbolS *, struct ecoff_extr *);
 #endif
+extern asection *elf_com_section_ptr;
+extern symbolS * elf_common_parse (int ignore ATTRIBUTE_UNUSED, symbolS *symbolP,
+				   addressT size);
 
 #endif /* _OBJ_ELF_H */
diff --git a/gas/config/obj-evax.c b/gas/config/obj-evax.c
index c2b5c873deac..e72cb69f3af9 100644
--- a/gas/config/obj-evax.c
+++ b/gas/config/obj-evax.c
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
-   MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #define OBJ_HEADER "obj-evax.h"
 
diff --git a/gas/config/obj-evax.h b/gas/config/obj-evax.h
index 98d704a186e2..413a837cb3de 100644
--- a/gas/config/obj-evax.h
+++ b/gas/config/obj-evax.h
@@ -1,5 +1,5 @@
 /* This file is obj-evax.h
-   Copyright 1996, 2000 Free Software Foundation, Inc.
+   Copyright 1996, 2000, 2005 Free Software Foundation, Inc.
    Contributed by Klaus Kämpf (kkaempf@progis.de) of
      proGIS Software, Aachen, Germany.
 
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston,
-   MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /*
  * This file is obj-evax.h and is intended to be a template for
@@ -31,9 +31,7 @@
 /* include whatever target cpu is appropriate.  */
 #include "targ-cpu.h"
 
-#ifdef BFD_ASSEMBLER
 #define OUTPUT_FLAVOR bfd_target_evax_flavour
-#endif
 
 /*
  * SYMBOLS
@@ -58,8 +56,6 @@ obj_symbol_type;		/* should be the format's symbol structure */
 
 typedef void *object_headers;
 
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE (0)	/* your magic number */
-
 #define OBJ_EMIT_LINENO(a,b,c)	/* must be *something*.  This no-op's it out.  */
 
 #define obj_symbol_new_hook(s)        {;}
diff --git a/gas/config/obj-hp300.c b/gas/config/obj-hp300.c
deleted file mode 100644
index 2fc0f2559290..000000000000
--- a/gas/config/obj-hp300.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/* This file is obj-hp300.h
-   Copyright 1993, 2000 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#include "config/obj-aout.c"
-
-/* Aout file generation & utilities */
-void
-hp300_header_append (where, headers)
-     char **where;
-     object_headers *headers;
-{
-  tc_headers_hook (headers);
-
-#define DO(FIELD)	\
-  { \
-    md_number_to_chars (*where, headers->header.FIELD, sizeof (headers->header.FIELD)); \
-    *where += sizeof (headers->header.FIELD); \
-  }
-
-  DO (a_info);
-  DO (a_spare1);
-  DO (a_spare2);
-  DO (a_text);
-  DO (a_data);
-  DO (a_bss);
-  DO (a_trsize);
-  DO (a_drsize);
-  DO (a_spare3);
-  DO (a_spare4);
-  DO (a_spare5);
-  DO (a_entry);
-  DO (a_spare6);
-  DO (a_spare7);
-  DO (a_syms);
-  DO (a_spare8);
-}
diff --git a/gas/config/obj-hp300.h b/gas/config/obj-hp300.h
deleted file mode 100644
index 8ff1f6778437..000000000000
--- a/gas/config/obj-hp300.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* This file is obj-hp300.h
-   Copyright 1993, 2000 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define __STRUCT_EXEC_OVERRIDE__
-
-struct exec_bytes
-{
-  unsigned char a_info[4];   /* a_machtype/a_magic */
-  unsigned char a_spare1[4];
-  unsigned char a_spare2[4];
-  unsigned char a_text[4];   /* length of text, in bytes */
-  unsigned char a_data[4];   /* length of data, in bytes */
-  unsigned char a_bss[4];    /* length of uninitialized data area for file, in bytes */
-  unsigned char a_trsize[4]; /* length of relocation info for text, in bytes */
-  unsigned char a_drsize[4]; /* length of relocation info for data, in bytes */
-  unsigned char a_spare3[4]; /* HP = pascal interface size */
-  unsigned char a_spare4[4]; /* HP = symbol table size */
-  unsigned char a_spare5[4]; /* HP = debug name table size */
-  unsigned char a_entry[4];  /* start address */
-  unsigned char a_spare6[4]; /* HP = source line table size */
-  unsigned char a_spare7[4]; /* HP = value table size */
-  unsigned char a_syms[4];   /* length of symbol table data in file, in bytes */
-  unsigned char a_spare8[4];
-};
-
-/* How big the "struct exec" is on disk */
-#define EXEC_BYTES_SIZE (16 * 4)
-
-struct exec
-{
-  unsigned long a_info;
-  unsigned long a_spare1;
-  unsigned long a_spare2;
-  unsigned long a_text;
-  unsigned long a_data;
-  unsigned long a_bss;
-  unsigned long a_trsize;
-  unsigned long a_drsize;
-  unsigned long a_spare3;
-  unsigned long a_spare4;
-  unsigned long a_spare5;
-  unsigned long a_entry;
-  unsigned long a_spare6;
-  unsigned long a_spare7;
-  unsigned long a_syms;
-  unsigned long a_spare8;
-};
-
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE	(OMAGIC)
-#define AOUT_VERSION	0x02
-#define AOUT_MACHTYPE	0x0c
-#define OMAGIC		0x106
-
-#define obj_header_append	hp300_header_append
-#include "config/obj-aout.h"
diff --git a/gas/config/obj-ieee.c b/gas/config/obj-ieee.c
index 02f43393d688..bac46757c131 100644
--- a/gas/config/obj-ieee.c
+++ b/gas/config/obj-ieee.c
@@ -1,5 +1,5 @@
 /* obj-format for ieee-695 records.
-   Copyright 1991, 1992, 1993, 1994, 1997, 2000
+   Copyright 1991, 1992, 1993, 1994, 1997, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Created by Steve Chamberlain <steve@cygnus.com>.  */
 
@@ -209,12 +209,6 @@ do_relocs_for (idx)
 	  reloc_ptr_vector[i] = to;
 	  to->howto = (reloc_howto_type *) (from->fx_r_type);
 
-#if 0
-	  /* We can't represent complicated things in a reloc yet.  */
-	  if (from->fx_addsy == 0 || from->fx_subsy != 0)
-	    abort ();
-#endif
-
 	  s = &(from->fx_addsy->sy_symbol.sy);
 	  to->address = ((char *) (from->fx_frag->fr_address +
 				   from->fx_where))
@@ -561,21 +555,7 @@ write_object_file ()
       fragS **prev_frag_ptr_ptr;
       struct frchain *next_frchain_ptr;
 
-#if 0
-      struct frag **head_ptr = segment_info[i].frag_root;
-#endif
-
       segment_info[i].frag_root = segment_info[i].frchainP->frch_root;
-#if 0
-      /* I'm not sure what this is for.  */
-      for (frchain_ptr = segment_info[i].frchainP->frch_root;
-	   frchain_ptr != (struct frchain *) NULL;
-	   frchain_ptr = frchain_ptr->frch_next)
-	{
-	  *head_ptr = frchain_ptr;
-	  head_ptr = &frchain_ptr->next;
-	}
-#endif
     }
 
   for (i = SEG_E0; i < SEG_UNKNOWN; i++)
diff --git a/gas/config/obj-ieee.h b/gas/config/obj-ieee.h
index c0bd628a5443..29654296e83f 100644
--- a/gas/config/obj-ieee.h
+++ b/gas/config/obj-ieee.h
@@ -16,10 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define BFD 1
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "bfd.h"
 
@@ -43,8 +41,6 @@ typedef struct
   }
 object_headers;
 
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE 1
-
 int lineno_rootP;
 
 #define IEEE_STYLE
diff --git a/gas/config/obj-multi.h b/gas/config/obj-multi.h
index 37d9fe828b4a..70faf103be7f 100644
--- a/gas/config/obj-multi.h
+++ b/gas/config/obj-multi.h
@@ -1,5 +1,5 @@
 /* Multiple object format emulation.
-   Copyright 1995, 1996, 1997, 1999, 2000, 2002
+   Copyright 1995, 1996, 1997, 1999, 2000, 2002, 2004
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef _OBJ_MULTI_H
 #define _OBJ_MULTI_H
@@ -37,9 +37,9 @@
 	 ? (*this_format->begin) ()			\
 	 : (void) 0)
 
-#define obj_app_file(NAME)				\
+#define obj_app_file(NAME, APPFILE)			\
 	(this_format->app_file				\
-	 ? (*this_format->app_file) (NAME)		\
+	 ? (*this_format->app_file) (NAME, APPFILE)	\
 	 : (void) 0)
 
 #define obj_frob_symbol(S,P)				\
@@ -146,6 +146,8 @@
 
 #define EMIT_SECTION_SYMBOLS (this_format->emit_section_symbols)
 
+#define FAKE_LABEL_NAME (this_emulation->fake_label_name)
+
 #ifdef OBJ_MAYBE_ELF
 /* We need OBJ_SYMFIELD_TYPE so that symbol_get_obj is defined in symbol.c
    We also need various STAB defines for stab.c  */
diff --git a/gas/config/obj-som.c b/gas/config/obj-som.c
index 454042a4f419..571330efcb42 100644
--- a/gas/config/obj-som.c
+++ b/gas/config/obj-som.c
@@ -1,5 +1,6 @@
 /* SOM object file format.
-   Copyright 1993, 1994, 1998, 2000, 2002 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1998, 2000, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.
 
    Written by the Center for Software Science at the University of Utah
    and by Cygnus Support.  */
@@ -26,14 +27,6 @@
 #include "aout/stab_gnu.h"
 #include "obstack.h"
 
-static void obj_som_weak PARAMS ((int));
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  {"weak", obj_som_weak, 0},
-  {NULL, NULL, 0}
-};
-
 static int version_seen = 0;
 static int copyright_seen = 0;
 static int compiler_seen = 0;
@@ -41,7 +34,7 @@ static int compiler_seen = 0;
 /* Unused by SOM.  */
 
 void
-obj_read_begin_hook ()
+obj_read_begin_hook (void)
 {
 }
 
@@ -51,8 +44,7 @@ obj_read_begin_hook ()
    string is "sourcefile language version" and is delimited by blanks.  */
 
 void
-obj_som_compiler (unused)
-     int unused;
+obj_som_compiler (int unused ATTRIBUTE_UNUSED)
 {
   char *buf;
   char c;
@@ -128,8 +120,7 @@ obj_som_compiler (unused)
 /* Handle a .version directive.  */
 
 void
-obj_som_version (unused)
-     int unused;
+obj_som_version (int unused ATTRIBUTE_UNUSED)
 {
   char *version, c;
 
@@ -174,8 +165,7 @@ obj_som_version (unused)
    If you care about copyright strings that much, you fix it.  */
 
 void
-obj_som_copyright (unused)
-     int unused;
+obj_som_copyright (int unused ATTRIBUTE_UNUSED)
 {
   char *copyright, c;
 
@@ -223,8 +213,7 @@ obj_som_copyright (unused)
    which BFD does not understand.  */
 
 void
-obj_som_init_stab_section (seg)
-     segT seg;
+obj_som_init_stab_section (segT seg)
 {
   segT saved_seg = now_seg;
   segT space;
@@ -248,7 +237,7 @@ obj_som_init_stab_section (seg)
      (just created above).  Also set some attributes which BFD does
      not understand.  In particular, access bits, sort keys, and load
      quadrant.  */
-  obj_set_subsection_attributes (seg, space, 0x1f, 73, 0);
+  obj_set_subsection_attributes (seg, space, 0x1f, 73, 0, 0, 0, 0);
   bfd_set_section_alignment (stdoutput, seg, 2);
 
   /* Make some space for the first special stab entry and zero the memory.
@@ -271,7 +260,7 @@ obj_som_init_stab_section (seg)
      not understand.  In particular, access bits, sort keys, and load
      quadrant.  */
   seg = bfd_get_section_by_name (stdoutput, "$GDB_STRINGS$");
-  obj_set_subsection_attributes (seg, space, 0x1f, 72, 0);
+  obj_set_subsection_attributes (seg, space, 0x1f, 72, 0, 0, 0, 0);
   bfd_set_section_alignment (stdoutput, seg, 2);
 
   subseg_set (saved_seg, saved_subseg);
@@ -280,10 +269,7 @@ obj_som_init_stab_section (seg)
 /* Fill in the counts in the first entry in a .stabs section.  */
 
 static void
-adjust_stab_sections (abfd, sec, xxx)
-     bfd *abfd;
-     asection *sec;
-     PTR xxx;
+adjust_stab_sections (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 {
   asection *strsec;
   char *p;
@@ -310,14 +296,13 @@ adjust_stab_sections (abfd, sec, xxx)
    stab entry and to set the starting address for each code subspace.  */
 
 void
-som_frob_file ()
+som_frob_file (void)
 {
   bfd_map_over_sections (stdoutput, adjust_stab_sections, (PTR) 0);
 }
 
 static void
-obj_som_weak (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+obj_som_weak (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   int c;
@@ -331,9 +316,6 @@ obj_som_weak (ignore)
       *input_line_pointer = c;
       SKIP_WHITESPACE ();
       S_SET_WEAK (symbolP);
-#if 0
-      symbol_get_obj (symbolP)->local = 1;
-#endif
       if (c == ',')
 	{
 	  input_line_pointer++;
@@ -345,3 +327,9 @@ obj_som_weak (ignore)
   while (c == ',');
   demand_empty_rest_of_line ();
 }
+
+const pseudo_typeS obj_pseudo_table[] =
+{
+  {"weak", obj_som_weak, 0},
+  {NULL, NULL, 0}
+};
diff --git a/gas/config/obj-som.h b/gas/config/obj-som.h
index 23d79eb2b118..85f3f72bb404 100644
--- a/gas/config/obj-som.h
+++ b/gas/config/obj-som.h
@@ -1,5 +1,6 @@
 /* SOM object file format.
-   Copyright 1993, 1994, 1995, 1998, 2000 Free Software Foundation, Inc.
+   Copyright 1993, 1994, 1995, 1998, 2000, 2004, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.
 
    Written by the Center for Software Science at the University of Utah
    and by Cygnus Support.  */
@@ -38,11 +39,12 @@
 /* should be conditional on address size!  */
 #define som_symbol(asymbol) ((som_symbol_type *) (&(asymbol)->the_bfd))
 
-extern void som_file_symbol PARAMS ((char *));
-extern void obj_som_version PARAMS ((int));
-extern void obj_som_init_stab_section PARAMS ((segT));
-extern void obj_som_copyright PARAMS ((int));
-extern void obj_som_compiler PARAMS ((int));
+extern void som_file_symbol           (char *);
+extern void som_frob_file             (void);
+extern void obj_som_version           (int);
+extern void obj_som_init_stab_section (segT);
+extern void obj_som_copyright         (int);
+extern void obj_som_compiler          (int);
 
 #define obj_symbol_new_hook(s) {;}
 
diff --git a/gas/config/obj-vms.c b/gas/config/obj-vms.c
deleted file mode 100644
index 18b4fd409620..000000000000
--- a/gas/config/obj-vms.c
+++ /dev/null
@@ -1,4933 +0,0 @@
-/* vms.c -- Write out a VAX/VMS object file
-   Copyright 1987, 1988, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001,
-   2002, 2003
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* Written by David L. Kashtan */
-/* Modified by Eric Youngdale to write VMS debug records for program
-   variables */
-
-/* Want all of obj-vms.h (as obj-format.h, via targ-env.h, via as.h).  */
-#define WANT_VMS_OBJ_DEFS
-
-#include "as.h"
-#include "config.h"
-#include "safe-ctype.h"
-#include "subsegs.h"
-#include "obstack.h"
-#include <fcntl.h>
-
-/* What we do if there is a goof.  */
-#define error as_fatal
-
-#ifdef VMS			/* These are of no use if we are cross assembling.  */
-#include <fab.h>		/* Define File Access Block.  */
-#include <nam.h>		/* Define NAM Block.  */
-#include <xab.h>		/* Define XAB - all different types.  */
-extern int sys$open(), sys$close(), sys$asctim();
-#endif
-
-/* Version string of the compiler that produced the code we are
-   assembling.  (And this assembler, if we do not have compiler info).  */
-char *compiler_version_string;
-
-extern int flag_hash_long_names;	/* -+ */
-extern int flag_one;			/* -1; compatibility with gcc 1.x */
-extern int flag_show_after_trunc;	/* -H */
-extern int flag_no_hash_mixed_case;	/* -h NUM */
-
-/* Flag that determines how we map names.  This takes several values, and
-   is set with the -h switch.  A value of zero implies names should be
-   upper case, and the presence of the -h switch inhibits the case hack.
-   No -h switch at all sets vms_name_mapping to 0, and allows case hacking.
-   A value of 2 (set with -h2) implies names should be
-   all lower case, with no case hack.  A value of 3 (set with -h3) implies
-   that case should be preserved.  */
-
-/* If the -+ switch is given, then the hash is appended to any name that is
-   longer than 31 characters, regardless of the setting of the -h switch.  */
-
-char vms_name_mapping = 0;
-
-static symbolS *Entry_Point_Symbol = 0;	/* Pointer to "_main" */
-
-/* We augment the "gas" symbol structure with this.  */
-
-struct VMS_Symbol
-{
-  struct VMS_Symbol *Next;
-  symbolS *Symbol;
-  int Size;
-  int Psect_Index;
-  int Psect_Offset;
-};
-
-struct VMS_Symbol *VMS_Symbols = 0;
-struct VMS_Symbol *Ctors_Symbols = 0;
-struct VMS_Symbol *Dtors_Symbols = 0;
-
-/* We need this to keep track of the various input files, so that we can
-   give the debugger the correct source line.  */
-
-struct input_file
-{
-  struct input_file *next;
-  struct input_file *same_file_fpnt;
-  int file_number;
-  int max_line;
-  int min_line;
-  int offset;
-  char flag;
-  char *name;
-  symbolS *spnt;
-};
-
-static struct input_file *file_root = (struct input_file *) NULL;
-
-/* Styles of PSECTS (program sections) that we generate; just shorthand
-   to avoid lists of section attributes.  Used by VMS_Psect_Spec().  */
-enum ps_type
-{
-  ps_TEXT, ps_DATA, ps_COMMON, ps_CONST, ps_CTORS, ps_DTORS
-};
-
-/* This enum is used to keep track of the various types of variables that
-   may be present.  */
-
-enum advanced_type
-{
-  BASIC, POINTER, ARRAY, ENUM, STRUCT, UNION, FUNCTION, VOID, ALIAS, UNKNOWN
-};
-
-/* This structure contains the information from the stabs directives, and the
-   information is filled in by VMS_typedef_parse.  Everything that is needed
-   to generate the debugging record for a given symbol is present here.
-   This could be done more efficiently, using nested struct/unions, but for
-   now I am happy that it works.  */
-
-struct VMS_DBG_Symbol
-{
-  struct VMS_DBG_Symbol *next;
-  /* Description of what this is.  */
-  enum advanced_type advanced;
-  /* This record is for this type.  */
-  int dbx_type;
-  /* For advanced types this is the type referred to.  I.e., the type
-     a pointer points to, or the type of object that makes up an
-     array.  */
-  int type2;
-  /* Use this type when generating a variable def.  */
-  int VMS_type;
-  /* Used for arrays - this will be present for all.  */
-  int index_min;
-  /* Entries, but will be meaningless for non-arrays.  */
-  int index_max;
-  /* Size in bytes of the data type.  For an array, this is the size
-     of one element in the array.  */
-  int data_size;
-  /* Number of the structure/union/enum - used for ref.  */
-  int struc_numb;
-};
-
-#define SYMTYPLST_SIZE (1<<4)	/* 16; Must be power of two.  */
-#define SYMTYP_HASH(x) ((unsigned) (x) & (SYMTYPLST_SIZE - 1))
-
-struct VMS_DBG_Symbol *VMS_Symbol_type_list[SYMTYPLST_SIZE];
-
-/* We need this structure to keep track of forward references to
-   struct/union/enum that have not been defined yet.  When they are
-   ultimately defined, then we can go back and generate the TIR
-   commands to make a back reference.  */
-
-struct forward_ref
-{
-  struct forward_ref *next;
-  int dbx_type;
-  int struc_numb;
-  char resolved;
-};
-
-struct forward_ref *f_ref_root = (struct forward_ref *) NULL;
-
-/* This routine is used to compare the names of certain types to various
-   fixed types that are known by the debugger.  */
-
-#define type_check(X)  !strcmp (symbol_name, X)
-
-/* This variable is used to keep track of the name of the symbol we are
-   working on while we are parsing the stabs directives.  */
-
-static const char *symbol_name;
-
-/* We use this counter to assign numbers to all of the structures, unions
-   and enums that we define.  When we actually declare a variable to the
-   debugger, we can simply do it by number, rather than describing the
-   whole thing each time.  */
-
-static int structure_count = 0;
-
-/* This variable is used to indicate that we are making the last attempt to
-   parse the stabs, and that we should define as much as we can, and ignore
-   the rest.  */
-
-static int final_pass;
-
-/* This variable is used to keep track of the current structure number
-   for a given variable.  If this is < 0, that means that the structure
-   has not yet been defined to the debugger.  This is still cool, since
-   the VMS object language has ways of fixing things up after the fact,
-   so we just make a note of this, and generate fixups at the end.  */
-
-static int struct_number;
-
-/* This is used to distinguish between D_float and G_float for telling
-   the debugger about doubles.  gcc outputs the same .stabs regardless
-   of whether -mg is used to select alternate doubles.  */
-
-static int vax_g_doubles = 0;
-
-/* Local symbol references (used to handle N_ABS symbols; gcc does not
-   generate those, but they're possible with hand-coded assembler input)
-   are always made relative to some particular environment.  If the current
-   input has any such symbols, then we expect this to get incremented
-   exactly once and end up having all of them be in environment #0.  */
-
-static int Current_Environment = -1;
-
-/* Every object file must specify an module name, which is also used by
-   traceback records.  Set in Write_VMS_MHD_Records().  */
-
-static char Module_Name[255+1];
-
-/* Variable descriptors are used tell the debugger the data types of certain
-   more complicated variables (basically anything involving a structure,
-   union, enum, array or pointer).  Some non-pointer variables of the
-   basic types that the debugger knows about do not require a variable
-   descriptor.
-
-   Since it is impossible to have a variable descriptor longer than 128
-   bytes by virtue of the way that the VMS object language is set up,
-   it makes not sense to make the arrays any longer than this, or worrying
-   about dynamic sizing of the array.
-
-   These are the arrays and counters that we use to build a variable
-   descriptor.  */
-
-#define MAX_DEBUG_RECORD 128
-static char Local[MAX_DEBUG_RECORD];	/* Buffer for variable descriptor.  */
-static char Asuffix[MAX_DEBUG_RECORD];	/* Buffer for array descriptor.  */
-static int Lpnt;		/* Index into Local.  */
-static int Apoint;		/* Index into Asuffix.  */
-static char overflow;		/* Flag to indicate we have written too much.  */
-static int total_len;		/* Used to calculate the total length of
-				   variable descriptor plus array descriptor
-				   - used for len byte.  */
-
-/* Flag if we have told user about finding global constants in the text
-   section.  */
-static int gave_compiler_message = 0;
-
-/* Global data (Object records limited to 512 bytes by VAX-11 "C" runtime).  */
-
-static int VMS_Object_File_FD;		/* File Descriptor for object file.  */
-static char Object_Record_Buffer[512];	/* Buffer for object file records.  */
-static size_t Object_Record_Offset;	/* Offset to end of data.  */
-static int Current_Object_Record_Type;	/* Type of record in above.  */
-
-/* Macros for moving data around.  Must work on big-endian systems.  */
-
-#ifdef VMS  /* These are more efficient for VMS->VMS systems.  */
-#define COPY_LONG(dest,val)	( *(long *) (dest) = (val) )
-#define COPY_SHORT(dest,val)	( *(short *) (dest) = (val) )
-#else
-#define COPY_LONG(dest,val)	md_number_to_chars ((dest), (val), 4)
-#define COPY_SHORT(dest,val)	md_number_to_chars ((dest), (val), 2)
-#endif
-
-/* Macros for placing data into the object record buffer.  */
-
-#define PUT_LONG(val) \
-	( COPY_LONG (&Object_Record_Buffer[Object_Record_Offset], (val)), \
-	  Object_Record_Offset += 4 )
-
-#define PUT_SHORT(val) \
-	( COPY_SHORT (&Object_Record_Buffer[Object_Record_Offset], (val)), \
-	  Object_Record_Offset += 2 )
-
-#define PUT_CHAR(val) (Object_Record_Buffer[Object_Record_Offset++] = (val))
-
-#define PUT_COUNTED_STRING(cp)			\
-  do 						\
-    { 						\
-      const char *p = (cp);			\
-      						\
-      PUT_CHAR ((char) strlen (p)); 		\
-      while (*p)				\
-	PUT_CHAR (*p++);			\
-    }						\
-  while (0)
-
-/* Macro for determining if a Name has psect attributes attached
-   to it.   */
-
-#define PSECT_ATTRIBUTES_STRING		"$$PsectAttributes_"
-#define PSECT_ATTRIBUTES_STRING_LENGTH	18
-
-#define HAS_PSECT_ATTRIBUTES(Name) \
-		(strncmp ((*Name == '_' ? Name + 1 : Name), \
-			  PSECT_ATTRIBUTES_STRING, \
-			  PSECT_ATTRIBUTES_STRING_LENGTH) == 0)
-
-
- /* in: segT   out: N_TYPE bits */
-const short seg_N_TYPE[] =
-{
-  N_ABS,
-  N_TEXT,
-  N_DATA,
-  N_BSS,
-  N_UNDF,			/* unknown */
-  N_UNDF,			/* error */
-  N_UNDF,			/* expression */
-  N_UNDF,			/* debug */
-  N_UNDF,			/* ntv */
-  N_UNDF,			/* ptv */
-  N_REGISTER,			/* register */
-};
-
-const segT N_TYPE_seg[N_TYPE + 2] =
-{				/* N_TYPE == 0x1E = 32-2 */
-  SEG_UNKNOWN,			/* N_UNDF == 0 */
-  SEG_GOOF,
-  SEG_ABSOLUTE,			/* N_ABS == 2 */
-  SEG_GOOF,
-  SEG_TEXT,			/* N_TEXT == 4 */
-  SEG_GOOF,
-  SEG_DATA,			/* N_DATA == 6 */
-  SEG_GOOF,
-  SEG_BSS,			/* N_BSS == 8 */
-  SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_GOOF, SEG_GOOF, SEG_GOOF, SEG_GOOF,
-  SEG_REGISTER,			/* dummy N_REGISTER for regs = 30 */
-  SEG_GOOF,
-};
-
-
-/* The following code defines the special types of pseudo-ops that we
-   use with VMS.  */
-
-unsigned char const_flag = IN_DEFAULT_SECTION;
-
-static void
-s_const (int arg)
-{
-  /* Since we don't need `arg', use it as our scratch variable so that
-     we won't get any "not used" warnings about it.  */
-  arg = get_absolute_expression ();
-  subseg_set (SEG_DATA, (subsegT) arg);
-  const_flag = 1;
-  demand_empty_rest_of_line ();
-}
-
-const pseudo_typeS obj_pseudo_table[] =
-{
-  {"const", s_const, 0},
-  {0, 0, 0},
-};				/* obj_pseudo_table */
-
-/* Routine to perform RESOLVE_SYMBOL_REDEFINITION().  */
-
-int
-vms_resolve_symbol_redef (symbolS *sym)
-{
-  /* If the new symbol is .comm AND it has a size of zero,
-     we ignore it (i.e. the old symbol overrides it).  */
-  if (SEGMENT_TO_SYMBOL_TYPE ((int) now_seg) == (N_UNDF | N_EXT)
-      && frag_now_fix () == 0)
-    {
-      as_warn (_("compiler emitted zero-size common symbol `%s' already defined"),
-	       S_GET_NAME (sym));
-      return 1;
-    }
-  /* If the old symbol is .comm and it has a size of zero,
-     we override it with the new symbol value.  */
-  if (S_IS_EXTERNAL (sym) && S_IS_DEFINED (sym) && S_GET_VALUE (sym) == 0)
-    {
-      as_warn (_("compiler redefined zero-size common symbol `%s'"),
-	       S_GET_NAME (sym));
-      sym->sy_frag  = frag_now;
-      S_SET_OTHER (sym, const_flag);
-      S_SET_VALUE (sym, frag_now_fix ());
-      /* Keep N_EXT bit.  */
-      sym->sy_symbol.n_type |= SEGMENT_TO_SYMBOL_TYPE ((int) now_seg);
-      return 1;
-    }
-
-  return 0;
-}
-
-/* `tc_frob_label' handler for colon(symbols.c), used to examine the
-   dummy label(s) gcc inserts at the beginning of each file it generates.
-   gcc 1.x put "gcc_compiled."; gcc 2.x (as of 2.7) puts "gcc2_compiled."
-   and "__gnu_language_<name>" and possibly "__vax_<type>_doubles".  */
-
-void
-vms_check_for_special_label (symbolS *symbolP)
-{
-  /* Special labels only occur prior to explicit section directives.  */
-  if ((const_flag & IN_DEFAULT_SECTION) != 0)
-    {
-      char *sym_name = S_GET_NAME (symbolP);
-
-      if (*sym_name == '_')
-	++sym_name;
-
-      if (!strcmp (sym_name, "__vax_g_doubles"))
-	vax_g_doubles = 1;
-#if 0	/* not necessary */
-      else if (!strcmp (sym_name, "__vax_d_doubles"))
-	vax_g_doubles = 0;
-#endif
-#if 0	/* These are potential alternatives to tc-vax.c's md_parse_options().  */
-      else if (!strcmp (sym_name, "gcc_compiled."))
-	flag_one = 1;
-      else if (!strcmp (sym_name, "__gnu_language_cplusplus"))
-	flag_hash_long_names = 1;
-#endif
-    }
-}
-
-void
-obj_read_begin_hook (void)
-{
-}
-
-void
-obj_crawl_symbol_chain (object_headers *headers)
-{
-  symbolS *symbolP;
-  symbolS **symbolPP;
-  int symbol_number = 0;
-
-  symbolPP = &symbol_rootP;	/* -> last symbol chain link.  */
-  while ((symbolP = *symbolPP) != NULL)
-    {
-      resolve_symbol_value (symbolP);
-
-     /* OK, here is how we decide which symbols go out into the
-	brave new symtab.  Symbols that do are:
-
-	* symbols with no name (stabd's?)
-	* symbols with debug info in their N_TYPE
-	* symbols with \1 as their 3rd character (numeric labels)
-	* "local labels" needed for PIC fixups
-
-	Symbols that don't are:
-	* symbols that are registers
-
-	All other symbols are output.  We complain if a deleted
-	symbol was marked external.  */
-
-      if (!S_IS_REGISTER (symbolP))
-	{
-	  symbolP->sy_number = symbol_number++;
-	  symbolP->sy_name_offset = 0;
-	  symbolPP = &symbolP->sy_next;
-	}
-      else
-	{
-	  if (S_IS_EXTERNAL (symbolP) || !S_IS_DEFINED (symbolP))
-	    as_bad (_("Local symbol %s never defined"),
-		    S_GET_NAME (symbolP));
-
-	  /* Unhook it from the chain.  */
-	  *symbolPP = symbol_next (symbolP);
-	}
-    }
-
-  H_SET_STRING_SIZE (headers, string_byte_count);
-  H_SET_SYMBOL_TABLE_SIZE (headers, symbol_number);
-}
-
-
-/* VMS OBJECT FILE HACKING ROUTINES.  */
-
-/* Create the VMS object file.  */
-
-static void
-Create_VMS_Object_File (void)
-{
-#ifdef eunice
-  VMS_Object_File_FD = creat (out_file_name, 0777, "var");
-#else
-#ifndef VMS
-  VMS_Object_File_FD = creat (out_file_name, 0777);
-#else	/* VMS */
-  VMS_Object_File_FD = creat (out_file_name, 0, "rfm=var",
-			      "ctx=bin", "mbc=16", "deq=64", "fop=tef",
-			      "shr=nil");
-#endif	/* !VMS */
-#endif	/* !eunice */
-  /* Deal with errors.  */
-  if (VMS_Object_File_FD < 0)
-    as_fatal (_("Couldn't create VMS object file \"%s\""), out_file_name);
-  /* Initialize object file hacking variables.  */
-  Object_Record_Offset = 0;
-  Current_Object_Record_Type = -1;
-}
-
-/* Flush the object record buffer to the object file.  */
-
-static void
-Flush_VMS_Object_Record_Buffer (void)
-{
-  /* If the buffer is empty, there's nothing to do.  */
-  if (Object_Record_Offset == 0)
-    return;
-
-#ifndef VMS			/* For cross-assembly purposes.  */
-  {
-    char RecLen[2];
-
-    /* "Variable-length record" files have a two byte length field
-       prepended to each record.  It's normally out-of-band, and native
-       VMS output will insert it automatically for this type of file.
-       When cross-assembling, we must write it explicitly.  */
-    md_number_to_chars (RecLen, Object_Record_Offset, 2);
-    if (write (VMS_Object_File_FD, RecLen, 2) != 2)
-      error (_("I/O error writing VMS object file (length prefix)"));
-    /* We also need to force the actual record to be an even number of
-       bytes.  For native output, that's automatic; when cross-assembling,
-       pad with a NUL byte if length is odd.  Do so _after_ writing the
-       pre-padded length.  Since our buffer is defined with even size,
-       an odd offset implies that it has some room left.  */
-    if ((Object_Record_Offset & 1) != 0)
-      Object_Record_Buffer[Object_Record_Offset++] = '\0';
-  }
-#endif /* not VMS */
-
-  /* Write the data to the file.  */
-  if ((size_t) write (VMS_Object_File_FD, Object_Record_Buffer,
-		      Object_Record_Offset) != Object_Record_Offset)
-    error (_("I/O error writing VMS object file"));
-
-  /* The buffer is now empty.  */
-  Object_Record_Offset = 0;
-}
-
-/* Declare a particular type of object file record.  */
-
-static void
-Set_VMS_Object_File_Record (int Type)
-{
-  /* If the type matches, we are done.  */
-  if (Type == Current_Object_Record_Type)
-    return;
-  /* Otherwise: flush the buffer.  */
-  Flush_VMS_Object_Record_Buffer ();
-  /* Remember the new type.  */
-  Current_Object_Record_Type = Type;
-}
-
-/* Close the VMS Object file.  */
-
-static void
-Close_VMS_Object_File (void)
-{
-  /* Flush (should never be necessary) and reset saved record-type context.  */
-  Set_VMS_Object_File_Record (-1);
-
-#ifndef VMS			/* For cross-assembly purposes.  */
-  {
-    char RecLen[2];
-    int minus_one = -1;
-
-    /* Write a 2 byte record-length field of -1 into the file, which
-       means end-of-block when read, hence end-of-file when occurring
-       in the file's last block.  It is only needed for variable-length
-       record files transferred to VMS as fixed-length record files
-       (typical for binary FTP; NFS shouldn't need it, but it won't hurt).  */
-    md_number_to_chars (RecLen, minus_one, 2);
-    write (VMS_Object_File_FD, RecLen, 2);
-  }
-#else
-    /* When written on a VMS system, the file header (cf inode) will record
-       the actual end-of-file position and no inline marker is needed.  */
-#endif
-
-  close (VMS_Object_File_FD);
-}
-
-/* Text Information and Relocation routines. */
-
-/* Stack Psect base followed by signed, varying-sized offset.
-   Common to several object records.  */
-
-static void
-vms_tir_stack_psect (int Psect_Index, int Offset, int Force)
-{
-  int psect_width, offset_width;
-
-  psect_width = ((unsigned) Psect_Index > 255) ? 2 : 1;
-  offset_width = (Force || Offset > 32767 || Offset < -32768) ? 4
-		 : (Offset > 127 || Offset < -128) ? 2 : 1;
-#define Sta_P(p,o) (((o)<<1) | ((p)-1))
-  /* Byte or word psect; byte, word, or longword offset.  */
-  switch (Sta_P(psect_width,offset_width))
-    {
-      case Sta_P(1,1):	PUT_CHAR (TIR_S_C_STA_PB);
-			PUT_CHAR ((char) (unsigned char) Psect_Index);
-			PUT_CHAR ((char) Offset);
-			break;
-      case Sta_P(1,2):	PUT_CHAR (TIR_S_C_STA_PW);
-			PUT_CHAR ((char) (unsigned char) Psect_Index);
-			PUT_SHORT (Offset);
-			break;
-      case Sta_P(1,4):	PUT_CHAR (TIR_S_C_STA_PL);
-			PUT_CHAR ((char) (unsigned char) Psect_Index);
-			PUT_LONG (Offset);
-			break;
-      case Sta_P(2,1):	PUT_CHAR (TIR_S_C_STA_WPB);
-			PUT_SHORT (Psect_Index);
-			PUT_CHAR ((char) Offset);
-			break;
-      case Sta_P(2,2):	PUT_CHAR (TIR_S_C_STA_WPW);
-			PUT_SHORT (Psect_Index);
-			PUT_SHORT (Offset);
-			break;
-      case Sta_P(2,4):	PUT_CHAR (TIR_S_C_STA_WPL);
-			PUT_SHORT (Psect_Index);
-			PUT_LONG (Offset);
-			break;
-    }
-#undef Sta_P
-}
-
-/* Store immediate data in current Psect.  */
-
-static void
-VMS_Store_Immediate_Data (const char *Pointer, int Size, int Record_Type)
-{
-  int i;
-
-  Set_VMS_Object_File_Record (Record_Type);
-  /* We can only store as most 128 bytes at a time due to the way that
-     TIR commands are encoded.  */
-  while (Size > 0)
-    {
-      i = (Size > 128) ? 128 : Size;
-      Size -= i;
-      /* If we cannot accommodate this record, flush the buffer.  */
-      if ((Object_Record_Offset + i + 1) >= sizeof Object_Record_Buffer)
-	Flush_VMS_Object_Record_Buffer ();
-      /* If the buffer is empty we must insert record type.  */
-      if (Object_Record_Offset == 0)
-	PUT_CHAR (Record_Type);
-      /* Store the count.  The Store Immediate TIR command is implied by
-         a negative command byte, and the length of the immediate data
-         is abs(command_byte).  So, we write the negated length value.  */
-      PUT_CHAR ((char) (-i & 0xff));
-      /* Now store the data.  */
-      while (--i >= 0)
-	PUT_CHAR (*Pointer++);
-    }
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Make a data reference.  */
-
-static void
-VMS_Set_Data (int Psect_Index, int Offset, int Record_Type, int Force)
-{
-  Set_VMS_Object_File_Record (Record_Type);
-  /* If the buffer is empty we must insert the record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (Record_Type);
-  /* Stack the Psect base with its offset.  */
-  vms_tir_stack_psect (Psect_Index, Offset, Force);
-  /* Set relocation base.  */
-  PUT_CHAR (TIR_S_C_STO_PIDR);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Make a debugger reference to a struct, union or enum.  */
-
-static void
-VMS_Store_Struct (int Struct_Index)
-{
-  /* We are writing a debug record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_DBG);
-  /* If the buffer is empty we must insert the record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_DBG);
-  PUT_CHAR (TIR_S_C_STA_UW);
-  PUT_SHORT (Struct_Index);
-  PUT_CHAR (TIR_S_C_CTL_STKDL);
-  PUT_CHAR (TIR_S_C_STO_L);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Make a debugger reference to partially define a struct, union or enum.  */
-
-static void
-VMS_Def_Struct (int Struct_Index)
-{
-  /* We are writing a debug record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_DBG);
-  /* If the buffer is empty we must insert the record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_DBG);
-  PUT_CHAR (TIR_S_C_STA_UW);
-  PUT_SHORT (Struct_Index);
-  PUT_CHAR (TIR_S_C_CTL_DFLOC);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-static void
-VMS_Set_Struct (int Struct_Index)
-{
-  Set_VMS_Object_File_Record (OBJ_S_C_DBG);
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_DBG);
-  PUT_CHAR (TIR_S_C_STA_UW);
-  PUT_SHORT (Struct_Index);
-  PUT_CHAR (TIR_S_C_CTL_STLOC);
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Traceback Information routines.  */
-
-/* Write the Traceback Module Begin record.  */
-
-static void
-VMS_TBT_Module_Begin (void)
-{
-  char *cp, *cp1;
-  int Size;
-  char Local[256];
-
-  /* Arrange to store the data locally (leave room for size byte).  */
-  cp = &Local[1];
-  /* Begin module.  */
-  *cp++ = DST_S_C_MODBEG;
-  *cp++ = 0;		/* flags; not used */
-  /* Language type == "C"
-    (FIXME:  this should be based on the input...)  */
-  COPY_LONG (cp, DST_S_C_C);
-  cp += 4;
-  /* Store the module name.  */
-  *cp++ = (char) strlen (Module_Name);
-  cp1 = Module_Name;
-  while (*cp1)
-    *cp++ = *cp1++;
-  /* Now we can store the record size.  */
-  Size = (cp - Local);
-  Local[0] = Size - 1;
-  /* Put it into the object record.  */
-  VMS_Store_Immediate_Data (Local, Size, OBJ_S_C_TBT);
-}
-
-/* Write the Traceback Module End record.  */
-
-static void
-VMS_TBT_Module_End (void)
-{
-  char Local[2];
-
-  /* End module.  */
-  Local[0] = 1;
-  Local[1] = DST_S_C_MODEND;
-  /* Put it into the object record.  */
-  VMS_Store_Immediate_Data (Local, 2, OBJ_S_C_TBT);
-}
-
-/* Write a Traceback Routine Begin record.  */
-
-static void
-VMS_TBT_Routine_Begin (symbolS *symbolP, int Psect)
-{
-  char *cp, *cp1;
-  char *Name;
-  int Offset;
-  int Size;
-  char Local[512];
-
-  /* Strip the leading "_" from the name.  */
-  Name = S_GET_NAME (symbolP);
-  if (*Name == '_')
-    Name++;
-  /* Get the text psect offset.  */
-  Offset = S_GET_VALUE (symbolP);
-  /* Set the record size.  */
-  Size = 1 + 1 + 4 + 1 + strlen (Name);
-  Local[0] = Size;
-  /* DST type "routine begin".  */
-  Local[1] = DST_S_C_RTNBEG;
-  /* Uses CallS/CallG.  */
-  Local[2] = 0;
-  /* Store the data so far.  */
-  VMS_Store_Immediate_Data (Local, 3, OBJ_S_C_TBT);
-  /* Make sure we are still generating a OBJ_S_C_TBT record.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_TBT);
-  /* Stack the address.  */
-  vms_tir_stack_psect (Psect, Offset, 0);
-  /* Store the data reference.  */
-  PUT_CHAR (TIR_S_C_STO_PIDR);
-  /* Store the counted string as data.  */
-  cp = Local;
-  cp1 = Name;
-  Size = strlen (cp1) + 1;
-  *cp++ = Size - 1;
-  while (*cp1)
-    *cp++ = *cp1++;
-  VMS_Store_Immediate_Data (Local, Size, OBJ_S_C_TBT);
-}
-
-/* Write a Traceback Routine End record.
-
-   We *must* search the symbol table to find the next routine, since the
-   assembler has a way of reassembling the symbol table OUT OF ORDER Thus
-   the next routine in the symbol list is not necessarily the next one in
-   memory.  For debugging to work correctly we must know the size of the
-   routine.  */
-
-static void
-VMS_TBT_Routine_End (int Max_Size, symbolS *sp)
-{
-  symbolS *symbolP;
-  unsigned long Size = 0x7fffffff;
-  char Local[16];
-  valueT sym_value, sp_value = S_GET_VALUE (sp);
-
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      if (!S_IS_DEBUG (symbolP) && S_GET_TYPE (symbolP) == N_TEXT)
-	{
-	  if (*S_GET_NAME (symbolP) == 'L')
-	    continue;
-	  sym_value = S_GET_VALUE (symbolP);
-	  if (sym_value > sp_value && sym_value < Size)
-	    Size = sym_value;
-
-	  /* Dummy labels like "gcc_compiled." should no longer reach here.  */
-#if 0
-	  else
-	    /* Check if gcc_compiled. has size of zero.  */
-	    if (sym_value == sp_value &&
-		sp != symbolP &&
-		(!strcmp (S_GET_NAME (sp), "gcc_compiled.") ||
-		 !strcmp (S_GET_NAME (sp), "gcc2_compiled.")))
-	      Size = sym_value;
-#endif
-	}
-    }
-  if (Size == 0x7fffffff)
-    Size = Max_Size;
-  Size -= sp_value;		/* and get the size of the routine */
-  /* Record Size.  */
-  Local[0] = 6;
-  /* DST type is "routine end".  */
-  Local[1] = DST_S_C_RTNEND;
-  Local[2] = 0;		/* unused */
-  /* Size of routine.  */
-  COPY_LONG (&Local[3], Size);
-  /* Store the record.  */
-  VMS_Store_Immediate_Data (Local, 7, OBJ_S_C_TBT);
-}
-
-/* Write a Traceback Block Begin record.  */
-
-static void
-VMS_TBT_Block_Begin (symbolS *symbolP, int Psect, char *Name)
-{
-  char *cp, *cp1;
-  int Offset;
-  int Size;
-  char Local[512];
-
-  /* Set the record size.  */
-  Size = 1 + 1 + 4 + 1 + strlen (Name);
-  Local[0] = Size;
-  /* DST type is "begin block"; we simulate with a phony routine.  */
-  Local[1] = DST_S_C_BLKBEG;
-  /* Uses CallS/CallG.  */
-  Local[2] = 0;
-  /* Store the data so far.  */
-  VMS_Store_Immediate_Data (Local, 3, OBJ_S_C_DBG);
-  /* Make sure we are still generating a debug record.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_DBG);
-  /* Now get the symbol address.  */
-  PUT_CHAR (TIR_S_C_STA_WPL);
-  PUT_SHORT (Psect);
-  /* Get the text psect offset.  */
-  Offset = S_GET_VALUE (symbolP);
-  PUT_LONG (Offset);
-  /* Store the data reference.  */
-  PUT_CHAR (TIR_S_C_STO_PIDR);
-  /* Store the counted string as data.  */
-  cp = Local;
-  cp1 = Name;
-  Size = strlen (cp1) + 1;
-  *cp++ = Size - 1;
-  while (*cp1)
-    *cp++ = *cp1++;
-  VMS_Store_Immediate_Data (Local, Size, OBJ_S_C_DBG);
-}
-
-/* Write a Traceback Block End record.  */
-
-static void
-VMS_TBT_Block_End (valueT Size)
-{
-  char Local[16];
-
-  Local[0] = 6;		/* record length */
-  /* DST type is "block end"; simulate with a phony end routine.  */
-  Local[1] = DST_S_C_BLKEND;
-  Local[2] = 0;		/* unused, must be zero */
-  COPY_LONG (&Local[3], Size);
-  VMS_Store_Immediate_Data (Local, 7, OBJ_S_C_DBG);
-}
-
-
-/* Write a Line number <-> Program Counter correlation record.  */
-
-static void
-VMS_TBT_Line_PC_Correlation (int Line_Number, int Offset,
-			     int Psect, int Do_Delta)
-{
-  char *cp;
-  char Local[64];
-
-  if (Do_Delta == 0)
-    {
-      /* If not delta, set our PC/Line number correlation.  */
-      cp = &Local[1];	/* Put size in Local[0] later.  */
-      /* DST type is "Line Number/PC correlation".  */
-      *cp++ = DST_S_C_LINE_NUM;
-      /* Set Line number.  */
-      if (Line_Number - 1 <= 255)
-	{
-	  *cp++ = DST_S_C_SET_LINUM_B;
-	  *cp++ = (char) (Line_Number - 1);
-	}
-      else if (Line_Number - 1 <= 65535)
-	{
-	  *cp++ = DST_S_C_SET_LINE_NUM;
-	  COPY_SHORT (cp, Line_Number - 1),  cp += 2;
-	}
-      else
-	{
-	  *cp++ = DST_S_C_SET_LINUM_L;
-	  COPY_LONG (cp, Line_Number - 1),  cp += 4;
-	}
-      /* Set PC.  */
-      *cp++ = DST_S_C_SET_ABS_PC;
-      /* Store size now that we know it, then output the data.  */
-      Local[0] = cp - &Local[1];
-	/* Account for the space that TIR_S_C_STO_PIDR will use for the PC.  */
-	Local[0] += 4;		/* size includes length of another longword */
-      VMS_Store_Immediate_Data (Local, cp - Local, OBJ_S_C_TBT);
-      /* Make sure we are still generating a OBJ_S_C_TBT record.  */
-      if (Object_Record_Offset == 0)
-	PUT_CHAR (OBJ_S_C_TBT);
-      vms_tir_stack_psect (Psect, Offset, 0);
-      PUT_CHAR (TIR_S_C_STO_PIDR);
-      /* Do a PC offset of 0 to register the line number.  */
-      Local[0] = 2;
-      Local[1] = DST_S_C_LINE_NUM;
-      Local[2] = 0;		/* Increment PC by 0 and register line # */
-      VMS_Store_Immediate_Data (Local, 3, OBJ_S_C_TBT);
-    }
-  else
-    {
-      if (Do_Delta < 0)
-	{
-	  /* When delta is negative, terminate the line numbers.  */
-	  Local[0] = 1 + 1 + 4;
-	  Local[1] = DST_S_C_LINE_NUM;
-	  Local[2] = DST_S_C_TERM_L;
-	  COPY_LONG (&Local[3], Offset);
-	  VMS_Store_Immediate_Data (Local, 7, OBJ_S_C_TBT);
-	  return;
-	}
-      /* Do a PC/Line delta.  */
-      cp = &Local[1];
-      *cp++ = DST_S_C_LINE_NUM;
-      if (Line_Number > 1)
-	{
-	  /* We need to increment the line number.  */
-	  if (Line_Number - 1 <= 255)
-	    {
-	      *cp++ = DST_S_C_INCR_LINUM;
-	      *cp++ = Line_Number - 1;
-	    }
-	  else if (Line_Number - 1 <= 65535)
-	    {
-	      *cp++ = DST_S_C_INCR_LINUM_W;
-	      COPY_SHORT (cp, Line_Number - 1),  cp += 2;
-	    }
-	  else
-	    {
-	      *cp++ = DST_S_C_INCR_LINUM_L;
-	      COPY_LONG (cp, Line_Number - 1),  cp += 4;
-	    }
-	}
-      /* Increment the PC.  */
-      if (Offset <= 128)
-	{
-	  /* Small offsets are encoded as negative numbers, rather than the
-	     usual non-negative type code followed by another data field.  */
-	  *cp++ = (char) -Offset;
-	}
-      else if (Offset <= 65535)
-	{
-	  *cp++ = DST_S_C_DELTA_PC_W;
-	  COPY_SHORT (cp, Offset),  cp += 2;
-	}
-      else
-	{
-	  *cp++ = DST_S_C_DELTA_PC_L;
-	  COPY_LONG (cp, Offset),  cp += 4;
-	}
-      /* Set size now that be know it, then output the data.  */
-      Local[0] = cp - &Local[1];
-      VMS_Store_Immediate_Data (Local, cp - Local, OBJ_S_C_TBT);
-    }
-}
-
-
-/* Describe a source file to the debugger.  */
-
-static int
-VMS_TBT_Source_File (char *Filename, int ID_Number)
-{
-  char *cp;
-  int len, rfo, ffb, ebk;
-  char cdt[8];
-  char Local[512];
-#ifdef VMS			/* Used for native assembly */
-  unsigned Status;
-  struct FAB fab;		/* RMS file access block */
-  struct NAM nam;		/* file name information */
-  struct XABDAT xabdat;		/* date+time fields */
-  struct XABFHC xabfhc;		/* file header characteristics */
-  char resultant_string_buffer[255 + 1];
-
-  /* Set up RMS structures:  */
-  /* FAB -- file access block */
-  memset ((char *) &fab, 0, sizeof fab);
-  fab.fab$b_bid = FAB$C_BID;
-  fab.fab$b_bln = (unsigned char) sizeof fab;
-  fab.fab$l_fna = Filename;
-  fab.fab$b_fns = (unsigned char) strlen (Filename);
-  fab.fab$l_nam = (char *) &nam;
-  fab.fab$l_xab = (char *) &xabdat;
-  /* NAM -- file name block.  */
-  memset ((char *) &nam, 0, sizeof nam);
-  nam.nam$b_bid = NAM$C_BID;
-  nam.nam$b_bln = (unsigned char) sizeof nam;
-  nam.nam$l_rsa = resultant_string_buffer;
-  nam.nam$b_rss = (unsigned char) (sizeof resultant_string_buffer - 1);
-  /* XABs -- extended attributes blocks.  */
-  memset ((char *) &xabdat, 0, sizeof xabdat);
-  xabdat.xab$b_cod = XAB$C_DAT;
-  xabdat.xab$b_bln = (unsigned char) sizeof xabdat;
-  xabdat.xab$l_nxt = (char *) &xabfhc;
-  memset ((char *) &xabfhc, 0, sizeof xabfhc);
-  xabfhc.xab$b_cod = XAB$C_FHC;
-  xabfhc.xab$b_bln = (unsigned char) sizeof xabfhc;
-  xabfhc.xab$l_nxt = 0;
-
-  /* Get the file information.  */
-  Status = sys$open (&fab);
-  if (!(Status & 1))
-    {
-      as_tsktsk (_("Couldn't find source file \"%s\", status=%%X%x"),
-		 Filename, Status);
-      return 0;
-    }
-  sys$close (&fab);
-  /* Now extract fields of interest.  */
-  memcpy (cdt, (char *) &xabdat.xab$q_cdt, 8);	/* creation date */
-  ebk = xabfhc.xab$l_ebk;		/* end-of-file block */
-  ffb = xabfhc.xab$w_ffb;		/* first free byte of last block */
-  rfo = xabfhc.xab$b_rfo;		/* record format */
-  len = nam.nam$b_rsl;			/* length of Filename */
-  resultant_string_buffer[len] = '\0';
-  Filename = resultant_string_buffer;	/* full filename */
-#else				/* Cross-assembly */
-  /* [Perhaps we ought to use actual values derived from stat() here?]  */
-  memset (cdt, 0, 8);			/* null VMS quadword binary time */
-  ebk = ffb = rfo = 0;
-  len = strlen (Filename);
-  if (len > 255)	/* a single byte is used as count prefix */
-    {
-      Filename += (len - 255);		/* tail end is more significant */
-      len = 255;
-    }
-#endif /* VMS */
-
-  cp = &Local[1];			/* fill in record length later */
-  *cp++ = DST_S_C_SOURCE;		/* DST type is "source file" */
-  *cp++ = DST_S_C_SRC_FORMFEED;		/* formfeeds count as source records */
-  *cp++ = DST_S_C_SRC_DECLFILE;		/* declare source file */
-  know (cp == &Local[4]);
-  *cp++ = 0;				/* fill in this length below */
-  *cp++ = 0;				/* flags; must be zero */
-  COPY_SHORT (cp, ID_Number),  cp += 2;	/* file ID number */
-  memcpy (cp, cdt, 8),  cp += 8;	/* creation date+time */
-  COPY_LONG (cp, ebk),  cp += 4;	/* end-of-file block */
-  COPY_SHORT (cp, ffb),  cp += 2;	/* first free byte of last block */
-  *cp++ = (char) rfo;			/* RMS record format */
-  /* Filename.  */
-  *cp++ = (char) len;
-  while (--len >= 0)
-    *cp++ = *Filename++;
-  /* Library module name (none).  */
-  *cp++ = 0;
-  /* Now that size is known, fill it in and write out the record.  */
-  Local[4] = cp - &Local[5];		/* source file declaration size */
-  Local[0] = cp - &Local[1];		/* TBT record size */
-  VMS_Store_Immediate_Data (Local, cp - Local, OBJ_S_C_TBT);
-  return 1;
-}
-
-/* Traceback information is described in terms of lines from compiler
-   listing files, not lines from source files.  We need to set up the
-   correlation between listing line numbers and source line numbers.
-   Since gcc's .stabn directives refer to the source lines, we just
-   need to describe a one-to-one correspondence.  */
-
-static void
-VMS_TBT_Source_Lines (int ID_Number, int Starting_Line_Number,
-		      int Number_Of_Lines)
-{
-  char *cp;
-  int chunk_limit;
-  char Local[128];	/* room enough to describe 1310700 lines...  */
-
-  cp = &Local[1];	/* Put size in Local[0] later.  */
-  *cp++ = DST_S_C_SOURCE;		/* DST type is "source file".  */
-  *cp++ = DST_S_C_SRC_SETFILE;		/* Set Source File.  */
-  COPY_SHORT (cp, ID_Number),  cp += 2;	/* File ID Number.  */
-  /* Set record number and define lines.  Since no longword form of
-     SRC_DEFLINES is available, we need to be able to cope with any huge
-     files a chunk at a time.  It doesn't matter for tracebacks, since
-     unspecified lines are mapped one-to-one and work out right, but it
-     does matter within the debugger.  Without this explicit mapping,
-     it will complain about lines not existing in the module.  */
-  chunk_limit = (sizeof Local - 5) / 6;
-  if (Number_Of_Lines > 65535 * chunk_limit)	/* avoid buffer overflow */
-    Number_Of_Lines = 65535 * chunk_limit;
-  while (Number_Of_Lines > 65535)
-    {
-      *cp++ = DST_S_C_SRC_SETREC_L;
-      COPY_LONG (cp, Starting_Line_Number),  cp += 4;
-      *cp++ = DST_S_C_SRC_DEFLINES_W;
-      COPY_SHORT (cp, 65535),  cp += 2;
-      Starting_Line_Number += 65535;
-      Number_Of_Lines -= 65535;
-    }
-  /* Set record number and define lines, normal case.  */
-  if (Starting_Line_Number <= 65535)
-    {
-      *cp++ = DST_S_C_SRC_SETREC_W;
-      COPY_SHORT (cp, Starting_Line_Number),  cp += 2;
-    }
-  else
-    {
-      *cp++ = DST_S_C_SRC_SETREC_L;
-      COPY_LONG (cp, Starting_Line_Number),  cp += 4;
-    }
-  *cp++ = DST_S_C_SRC_DEFLINES_W;
-  COPY_SHORT (cp, Number_Of_Lines),  cp += 2;
-  /* Set size now that be know it, then output the data.  */
-  Local[0] = cp - &Local[1];
-  VMS_Store_Immediate_Data (Local, cp - Local, OBJ_S_C_TBT);
-}
-
-
-/* Debugger Information support routines. */
-
-/* This routine locates a file in the list of files.  If an entry does
-   not exist, one is created.  For include files, a new entry is always
-   created such that inline functions can be properly debugged.  */
-
-static struct input_file *
-find_file (symbolS *sp)
-{
-  struct input_file *same_file = 0;
-  struct input_file *fpnt, *last = 0;
-  char *sp_name;
-
-  for (fpnt = file_root; fpnt; fpnt = fpnt->next)
-    {
-      if (fpnt->spnt == sp)
-	return fpnt;
-      last = fpnt;
-    }
-  sp_name = S_GET_NAME (sp);
-  for (fpnt = file_root; fpnt; fpnt = fpnt->next)
-    {
-      if (strcmp (sp_name, fpnt->name) == 0)
-	{
-	  if (fpnt->flag == 1)
-	    return fpnt;
-	  same_file = fpnt;
-	  break;
-	}
-    }
-  fpnt = xmalloc (sizeof (struct input_file));
-  if (!file_root)
-    file_root = fpnt;
-  else
-    last->next = fpnt;
-  fpnt->next = 0;
-  fpnt->name = sp_name;
-  fpnt->min_line = 0x7fffffff;
-  fpnt->max_line = 0;
-  fpnt->offset = 0;
-  fpnt->flag = 0;
-  fpnt->file_number = 0;
-  fpnt->spnt = sp;
-  fpnt->same_file_fpnt = same_file;
-  return fpnt;
-}
-
-/* This routine converts a number string into an integer, and stops when
-   it sees an invalid character.  The return value is the address of the
-   character just past the last character read.  No error is generated.  */
-
-static char *
-cvt_integer (char *str, int *rtn)
-{
-  int ival = 0, sgn = 1;
-
-  if (*str == '-')
-    sgn = -1,  ++str;
-  while (*str >= '0' && *str <= '9')
-    ival = 10 * ival + *str++ - '0';
-  *rtn = sgn * ival;
-  return str;
-}
-
-
-/* The following functions and definitions are used to generate object
-   records that will describe program variables to the VMS debugger.
-
-   This file contains many of the routines needed to output debugging info
-   into the object file that the VMS debugger needs to understand symbols.
-   These routines are called very late in the assembly process, and thus
-   we can be fairly lax about changing things, since the GSD and the TIR
-   sections have already been output.  */
-
-/* This routine fixes the names that are generated by C++, ".this" is a good
-   example.  The period does not work for the debugger, since it looks like
-   the syntax for a structure element, and thus it gets mightily confused.
-
-   We also use this to strip the PsectAttribute hack from the name before we
-   write a debugger record.  */
-
-static char *
-fix_name (char *pnt)
-{
-  char *pnt1;
-
-  /* Kill any leading "_".  */
-  if (*pnt == '_')
-    pnt++;
-
-  /* Is there a Psect Attribute to skip??  */
-  if (HAS_PSECT_ATTRIBUTES (pnt))
-    {
-      /* Yes: Skip it.  */
-      pnt += PSECT_ATTRIBUTES_STRING_LENGTH;
-      while (*pnt)
-	{
-	  if ((pnt[0] == '$') && (pnt[1] == '$'))
-	    {
-	      pnt += 2;
-	      break;
-	    }
-	  pnt++;
-	}
-    }
-
-  /* Here we fix the .this -> $this conversion.  */
-  for (pnt1 = pnt; *pnt1 != 0; pnt1++)
-    if (*pnt1 == '.')
-      *pnt1 = '$';
-
-  return pnt;
-}
-
-/* When defining a structure, this routine is called to find the name of
-   the actual structure.  It is assumed that str points to the equal sign
-   in the definition, and it moves backward until it finds the start of the
-   name.  If it finds a 0, then it knows that this structure def is in the
-   outermost level, and thus symbol_name points to the symbol name.  */
-
-static char *
-get_struct_name (char *str)
-{
-  char *pnt;
-  pnt = str;
-  while ((*pnt != ':') && (*pnt != '\0'))
-    pnt--;
-  if (*pnt == '\0')
-    return (char *) symbol_name;
-  *pnt-- = '\0';
-  while ((*pnt != ';') && (*pnt != '='))
-    pnt--;
-  if (*pnt == ';')
-    return pnt + 1;
-  while ((*pnt < '0') || (*pnt > '9'))
-    pnt++;
-  while ((*pnt >= '0') && (*pnt <= '9'))
-    pnt++;
-  return pnt;
-}
-
-/* Search symbol list for type number dbx_type.
-   Return a pointer to struct.  */
-
-static struct VMS_DBG_Symbol *
-find_symbol (int dbx_type)
-{
-  struct VMS_DBG_Symbol *spnt;
-
-  spnt = VMS_Symbol_type_list[SYMTYP_HASH (dbx_type)];
-  while (spnt)
-    {
-      if (spnt->dbx_type == dbx_type)
-	break;
-      spnt = spnt->next;
-    }
-  if (!spnt || spnt->advanced != ALIAS)
-    return spnt;
-  return find_symbol (spnt->type2);
-}
-
-#if 0		/* obsolete */
-/* This routine puts info into either Local or Asuffix, depending on the sign
-   of size.  The reason is that it is easier to build the variable descriptor
-   backwards, while the array descriptor is best built forwards.  In the end
-   they get put together, if there is not a struct/union/enum along the way.  */
-
-static void
-push (int value, int size1)
-{
-  if (size1 < 0)
-    {
-      size1 = -size1;
-      if (Lpnt < size1)
-	{
-	  overflow = 1;
-	  Lpnt = 1;
-	  return;
-	}
-      Lpnt -= size1;
-      md_number_to_chars (&Local[Lpnt + 1], value, size1);
-    }
-  else
-    {
-      if (Apoint + size1 >= MAX_DEBUG_RECORD)
-	{
-	  overflow = 1;
-	  Apoint = MAX_DEBUG_RECORD - 1;
-	  return;
-	}
-      md_number_to_chars (&Asuffix[Apoint], value, size1);
-      Apoint += size1;
-    }
-}
-#endif
-
-static void
-fpush (int value, int size)
-{
-  if (Apoint + size >= MAX_DEBUG_RECORD)
-    {
-      overflow = 1;
-      Apoint = MAX_DEBUG_RECORD - 1;
-      return;
-    }
-  if (size == 1)
-    Asuffix[Apoint++] = (char) value;
-  else
-    {
-      md_number_to_chars (&Asuffix[Apoint], value, size);
-      Apoint += size;
-    }
-}
-
-static void
-rpush (int value, int size)
-{
-  if (Lpnt < size)
-    {
-      overflow = 1;
-      Lpnt = 1;
-      return;
-    }
-  if (size == 1)
-      Local[Lpnt--] = (char) value;
-  else
-    {
-      Lpnt -= size;
-      md_number_to_chars (&Local[Lpnt + 1], value, size);
-    }
-}
-
-/* This routine generates the array descriptor for a given array.  */
-
-static void
-array_suffix (struct VMS_DBG_Symbol *spnt2)
-{
-  struct VMS_DBG_Symbol *spnt;
-  struct VMS_DBG_Symbol *spnt1;
-  int rank;
-  int total_size;
-
-  rank = 0;
-  spnt = spnt2;
-  while (spnt->advanced != ARRAY)
-    {
-      spnt = find_symbol (spnt->type2);
-      if (!spnt)
-	return;
-    }
-  spnt1 = spnt;
-  total_size = 1;
-  while (spnt1->advanced == ARRAY)
-    {
-      rank++;
-      total_size *= (spnt1->index_max - spnt1->index_min + 1);
-      spnt1 = find_symbol (spnt1->type2);
-    }
-  total_size = total_size * spnt1->data_size;
-  fpush (spnt1->data_size, 2);	/* element size */
-  if (spnt1->VMS_type == DBG_S_C_ADVANCED_TYPE)
-    fpush (0, 1);
-  else
-    fpush (spnt1->VMS_type, 1);	/* element type */
-  fpush (DSC_K_CLASS_A, 1);	/* descriptor class */
-  fpush (0, 4);			/* base address */
-  fpush (0, 1);			/* scale factor -- not applicable */
-  fpush (0, 1);			/* digit count -- not applicable */
-  fpush (0xc0, 1);		/* flags: multiplier block & bounds present */
-  fpush (rank, 1);		/* number of dimensions */
-  fpush (total_size, 4);
-  fpush (0, 4);			/* pointer to element [0][0]...[0] */
-  spnt1 = spnt;
-  while (spnt1->advanced == ARRAY)
-    {
-      fpush (spnt1->index_max - spnt1->index_min + 1, 4);
-      spnt1 = find_symbol (spnt1->type2);
-    }
-  spnt1 = spnt;
-  while (spnt1->advanced == ARRAY)
-    {
-      fpush (spnt1->index_min, 4);
-      fpush (spnt1->index_max, 4);
-      spnt1 = find_symbol (spnt1->type2);
-    }
-}
-
-/* This routine generates the start of a variable descriptor based upon
-   a struct/union/enum that has yet to be defined.  We define this spot as
-   a new location, and save four bytes for the address.  When the struct is
-   finally defined, then we can go back and plug in the correct address.  */
-
-static void
-new_forward_ref (int dbx_type)
-{
-  struct forward_ref *fpnt;
-
-  fpnt = xmalloc (sizeof (struct forward_ref));
-  fpnt->next = f_ref_root;
-  f_ref_root = fpnt;
-  fpnt->dbx_type = dbx_type;
-  fpnt->struc_numb = ++structure_count;
-  fpnt->resolved = 'N';
-  rpush (DST_K_TS_IND, 1);	/* indirect type specification */
-  total_len = 5;
-  rpush (total_len, 2);
-  struct_number = -fpnt->struc_numb;
-}
-
-/* This routine generates the variable descriptor used to describe non-basic
-   variables.  It calls itself recursively until it gets to the bottom of it
-   all, and then builds the descriptor backwards.  It is easiest to do it
-   this way since we must periodically write length bytes, and it is easiest
-   if we know the value when it is time to write it.  */
-
-static int
-gen1 (struct VMS_DBG_Symbol *spnt, int array_suffix_len)
-{
-  struct VMS_DBG_Symbol *spnt1;
-  int i;
-
-  switch (spnt->advanced)
-    {
-    case VOID:
-      rpush (DBG_S_C_VOID, 1);
-      total_len += 1;
-      rpush (total_len, 2);
-      return 0;
-    case BASIC:
-    case FUNCTION:
-      if (array_suffix_len == 0)
-	{
-	  rpush (spnt->VMS_type, 1);
-	  rpush (DBG_S_C_BASIC, 1);
-	  total_len = 2;
-	  rpush (total_len, 2);
-	  return 1;
-	}
-      rpush (0, 4);
-      rpush (DST_K_VFLAGS_DSC, 1);
-      rpush (DST_K_TS_DSC, 1);	/* Descriptor type specification.  */
-      total_len = -2;
-      return 1;
-    case STRUCT:
-    case UNION:
-    case ENUM:
-      struct_number = spnt->struc_numb;
-      if (struct_number < 0)
-	{
-	  new_forward_ref (spnt->dbx_type);
-	  return 1;
-	}
-      rpush (DBG_S_C_STRUCT, 1);
-      total_len = 5;
-      rpush (total_len, 2);
-      return 1;
-    case POINTER:
-      spnt1 = find_symbol (spnt->type2);
-      i = 1;
-      if (!spnt1)
-	new_forward_ref (spnt->type2);
-      else
-	i = gen1 (spnt1, 0);
-      if (i)
-	{
-	  /* (*void) is a special case, do not put pointer suffix.  */
-	  rpush (DBG_S_C_POINTER, 1);
-	  total_len += 3;
-	  rpush (total_len, 2);
-	}
-      return 1;
-    case ARRAY:
-      spnt1 = spnt;
-      while (spnt1->advanced == ARRAY)
-	{
-	  spnt1 = find_symbol (spnt1->type2);
-	  if (!spnt1)
-	    {
-	      as_tsktsk (_("debugger forward reference error, dbx type %d"),
-			 spnt->type2);
-	      return 0;
-	    }
-	}
-      /* It is too late to generate forward references, so the user
-	 gets a message.  This should only happen on a compiler error.  */
-      (void) gen1 (spnt1, 1);
-      i = Apoint;
-      array_suffix (spnt);
-      array_suffix_len = Apoint - i;
-      switch (spnt1->advanced)
-	{
-	case BASIC:
-	case FUNCTION:
-	  break;
-	default:
-	  rpush (0, 2);
-	  total_len += 2;
-	  rpush (total_len, 2);
-	  rpush (DST_K_VFLAGS_DSC, 1);
-	  rpush (1, 1);		/* Flags: element value spec included.  */
-	  rpush (1, 1);		/* One dimension.  */
-	  rpush (DBG_S_C_COMPLEX_ARRAY, 1);
-	}
-      total_len += array_suffix_len + 8;
-      rpush (total_len, 2);
-      break;
-    default:
-      break;
-    }
-  return 0;
-}
-
-/* This generates a suffix for a variable.  If it is not a defined type yet,
-   then dbx_type contains the type we are expecting so we can generate a
-   forward reference.  This calls gen1 to build most of the descriptor, and
-   then it puts the icing on at the end.  It then dumps whatever is needed
-   to get a complete descriptor (i.e. struct reference, array suffix).  */
-
-static void
-generate_suffix (struct VMS_DBG_Symbol *spnt, int dbx_type)
-{
-  static const char pvoid[6] =
-    {
-      5,		/* record.length == 5 */
-      DST_K_TYPSPEC,	/* record.type == 1 (type specification) */
-      0,		/* name.length == 0, no name follows */
-      1, 0,		/* type.length == 1 {2 bytes, little endian} */
-      DBG_S_C_VOID	/* type.type == 5 (pointer to unspecified) */
-    };
-  int i;
-
-  Apoint = 0;
-  Lpnt = MAX_DEBUG_RECORD - 1;
-  total_len = 0;
-  struct_number = 0;
-  overflow = 0;
-  if (!spnt)
-    new_forward_ref (dbx_type);
-  else
-    {
-      if (spnt->VMS_type != DBG_S_C_ADVANCED_TYPE)
-	return;		/* no suffix needed */
-      gen1 (spnt, 0);
-    }
-  rpush (0, 1);		/* no name (len==0) */
-  rpush (DST_K_TYPSPEC, 1);
-  total_len += 4;
-  rpush (total_len, 1);
-  /* If the variable descriptor overflows the record, output a descriptor
-     for a pointer to void.  */
-  if ((total_len >= MAX_DEBUG_RECORD) || overflow)
-    {
-      as_warn (_("Variable descriptor %d too complicated.  Defined as `void *'."),
-		spnt->dbx_type);
-      VMS_Store_Immediate_Data (pvoid, 6, OBJ_S_C_DBG);
-      return;
-    }
-  i = 0;
-  while (Lpnt < MAX_DEBUG_RECORD - 1)
-    Local[i++] = Local[++Lpnt];
-  Lpnt = i;
-  /* We use this for reference to structure that has already been defined.  */
-  if (struct_number > 0)
-    {
-      VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-      Lpnt = 0;
-      VMS_Store_Struct (struct_number);
-    }
-  /* We use this for a forward reference to a structure that has yet to
-     be defined.  We store four bytes of zero to make room for the actual
-     address once it is known.  */
-  if (struct_number < 0)
-    {
-      struct_number = -struct_number;
-      VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-      Lpnt = 0;
-      VMS_Def_Struct (struct_number);
-      COPY_LONG (&Local[Lpnt], 0L);
-      Lpnt += 4;
-      VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-      Lpnt = 0;
-    }
-  i = 0;
-  while (i < Apoint)
-    Local[Lpnt++] = Asuffix[i++];
-  if (Lpnt != 0)
-    VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-  Lpnt = 0;
-}
-
-/* "novel length" type doesn't work for simple atomic types.  */
-#define USE_BITSTRING_DESCRIPTOR(t) ((t)->advanced == BASIC)
-#undef SETUP_BASIC_TYPES
-
-/* This routine generates a type description for a bitfield.  */
-
-static void
-bitfield_suffix (struct VMS_DBG_Symbol *spnt, int width)
-{
-  Local[Lpnt++] = 13;			/* rec.len==13 */
-  Local[Lpnt++] = DST_K_TYPSPEC;	/* a type specification record */
-  Local[Lpnt++] = 0;			/* not named */
-  COPY_SHORT (&Local[Lpnt], 9);		/* typ.len==9 */
-  Lpnt += 2;
-  Local[Lpnt++] = DST_K_TS_NOV_LENG;	/* This type is a "novel length"
-					   incarnation of some other type.  */
-  COPY_LONG (&Local[Lpnt], width);	/* size in bits == novel length */
-  Lpnt += 4;
-  VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-  Lpnt = 0;
-  /* assert( spnt->struc_numb > 0 ); */
-  VMS_Store_Struct (spnt->struc_numb);	/* output 4 more bytes */
-}
-
-/* Formally define a builtin type, so that it can serve as the target of
-   an indirect reference.  It makes bitfield_suffix() easier by avoiding
-   the need to use a forward reference for the first occurrence of each
-   type used in a bitfield.  */
-
-static void
-setup_basic_type (struct VMS_DBG_Symbol *spnt ATTRIBUTE_UNUSED)
-{
-#ifdef SETUP_BASIC_TYPES
-  /* This would be very useful if "novel length" fields actually worked
-     with basic types like they do with enumerated types.  However,
-     they do not, so this isn't worth doing just so that you can use
-     EXAMINE/TYPE=(__long_long_int) instead of EXAMINE/QUAD.  */
-  char *p;
-#ifndef SETUP_SYNONYM_TYPES
-  /* This determines whether compatible things like `int' and `long int'
-     ought to have distinct type records rather than sharing one.  */
-  struct VMS_DBG_Symbol *spnt2;
-
-  /* First check whether this type has already been seen by another name.  */
-  for (spnt2 = VMS_Symbol_type_list[SYMTYP_HASH (spnt->VMS_type)];
-       spnt2;
-       spnt2 = spnt2->next)
-    if (spnt2 != spnt && spnt2->VMS_type == spnt->VMS_type)
-      {
-	spnt->struc_numb = spnt2->struc_numb;
-	return;
-      }
-#endif
-
-  /* `structure number' doesn't really mean `structure'; it means an index
-     into a linker maintained set of saved locations which can be referenced
-     again later.  */
-  spnt->struc_numb = ++structure_count;
-  VMS_Def_Struct (spnt->struc_numb);	/* remember where this type lives */
-  /* define the simple scalar type */
-  Local[Lpnt++] = 6 + strlen (symbol_name) + 2;	/* rec.len */
-  Local[Lpnt++] = DST_K_TYPSPEC;	/* rec.typ==type specification */
-  Local[Lpnt++] = strlen (symbol_name) + 2;
-  Local[Lpnt++] = '_';			/* prefix name with "__" */
-  Local[Lpnt++] = '_';
-  for (p = symbol_name; *p; p++)
-    Local[Lpnt++] = *p == ' ' ? '_' : *p;
-  COPY_SHORT (&Local[Lpnt], 2);		/* typ.len==2 */
-  Lpnt += 2;
-  Local[Lpnt++] = DST_K_TS_ATOM;	/* typ.kind is simple type */
-  Local[Lpnt++] = spnt->VMS_type;	/* typ.type */
-  VMS_Store_Immediate_Data (Local, Lpnt, OBJ_S_C_DBG);
-  Lpnt = 0;
-#endif	/* SETUP_BASIC_TYPES */
-}
-
-/* This routine generates a symbol definition for a C symbol for the
-   debugger.  It takes a psect and offset for global symbols; if psect < 0,
-   then this is a local variable and the offset is relative to FP.  In this
-   case it can be either a variable (Offset < 0) or a parameter (Offset > 0).  */
-
-static void
-VMS_DBG_record (struct VMS_DBG_Symbol *spnt, int Psect,
-		int Offset, char *Name)
-{
-  char *Name_pnt;
-  int len;
-  int i = 0;
-
-  /* If there are bad characters in name, convert them.  */
-  Name_pnt = fix_name (Name);
-
-  len = strlen (Name_pnt);
-  if (Psect < 0)
-    {
-      /* This is a local variable, referenced to SP.  */
-      Local[i++] = 7 + len;
-      Local[i++] = spnt->VMS_type;
-      Local[i++] = (Offset > 0) ? DBG_C_FUNCTION_PARAM : DBG_C_LOCAL_SYM;
-      COPY_LONG (&Local[i], Offset);
-      i += 4;
-    }
-  else
-    {
-      Local[i++] = 7 + len;
-      Local[i++] = spnt->VMS_type;
-      Local[i++] = DST_K_VALKIND_ADDR;
-      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-      i = 0;
-      VMS_Set_Data (Psect, Offset, OBJ_S_C_DBG, 0);
-    }
-  Local[i++] = len;
-  while (*Name_pnt != '\0')
-    Local[i++] = *Name_pnt++;
-  VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-  if (spnt->VMS_type == DBG_S_C_ADVANCED_TYPE)
-    generate_suffix (spnt, 0);
-}
-
-/* This routine parses the stabs entries in order to make the definition
-   for the debugger of local symbols and function parameters.  */
-
-static void
-VMS_local_stab_Parse (symbolS *sp)
-{
-  struct VMS_DBG_Symbol *spnt;
-  char *pnt;
-  char *pnt1;
-  char *str;
-  int dbx_type;
-
-  dbx_type = 0;
-  str = S_GET_NAME (sp);
-  pnt = (char *) strchr (str, ':');
-  if (!pnt)
-    return;
-  
-  /* Save this for later, and skip colon.  */
-  pnt1 = pnt++;
-
-  /* Ignore static constants.  */
-  if (*pnt == 'c')
-    return;
-  
-  /* There is one little catch that we must be aware of.  Sometimes function
-     parameters are optimized into registers, and the compiler, in its
-     infiite wisdom outputs stabs records for *both*.  In general we want to
-     use the register if it is present, so we must search the rest of the
-     symbols for this function to see if this parameter is assigned to a
-     register.  */
-  {
-    symbolS *sp1;
-    char *str1;
-    char *pnt2;
-
-    if (*pnt == 'p')
-      {
-	for (sp1 = symbol_next (sp); sp1; sp1 = symbol_next (sp1))
-	  {
-	    if (!S_IS_DEBUG (sp1))
-	      continue;
-	    if (S_GET_RAW_TYPE (sp1) == N_FUN)
-	      {
-		pnt2 = (char *) strchr (S_GET_NAME (sp1), ':') + 1;
-		if (*pnt2 == 'F' || *pnt2 == 'f')
-		  break;
-	      }
-	    if (S_GET_RAW_TYPE (sp1) != N_RSYM)
-	      continue;
-	    str1 = S_GET_NAME (sp1);	/* and get the name */
-	    pnt2 = str;
-	    while (*pnt2 != ':')
-	      {
-		if (*pnt2 != *str1)
-		  break;
-		pnt2++;
-		str1++;
-	      }
-	    if (*str1 == ':' && *pnt2 == ':')
-	      return;	/* They are the same!  Let's skip this one.  */
-	  }
-
-	/* Skip p in case no register.  */
-	pnt++;
-      }
-  }
-
-  pnt = cvt_integer (pnt, &dbx_type);
-
-  spnt = find_symbol (dbx_type);
-  if (!spnt)
-    /* Dunno what this is.  */
-    return;
-  
-  *pnt1 = '\0';
-  VMS_DBG_record (spnt, -1, S_GET_VALUE (sp), str);
-
-  /* ...and restore the string.  */
-  *pnt1 = ':';
-}
-
-/* This routine parses a stabs entry to find the information required
-   to define a variable.  It is used for global and static variables.
-   Basically we need to know the address of the symbol.  With older
-   versions of the compiler, const symbols are treated differently, in
-   that if they are global they are written into the text psect.  The
-   global symbol entry for such a const is actually written as a program
-   entry point (Yuk!!), so if we cannot find a symbol in the list of
-   psects, we must search the entry points as well.  static consts are
-   even harder, since they are never assigned a memory address.  The
-   compiler passes a stab to tell us the value, but I am not sure what
-   to do with it.  */
-
-static void
-VMS_stab_parse (symbolS *sp, int expected_type,
-		int type1, int type2, int Text_Psect)
-{
-  char *pnt;
-  char *pnt1;
-  char *str;
-  symbolS *sp1;
-  struct VMS_DBG_Symbol *spnt;
-  struct VMS_Symbol *vsp;
-  int dbx_type;
-
-  dbx_type = 0;
-  str = S_GET_NAME (sp);
-
-  pnt = (char *) strchr (str, ':');
-  if (!pnt)
-    /* No colon present.  */
-    return;
-  
-  /* Save this for later. */
-  pnt1 = pnt;
-  pnt++;
-  if (*pnt == expected_type)
-    {
-      pnt = cvt_integer (pnt + 1, &dbx_type);
-      spnt = find_symbol (dbx_type);
-      if (!spnt)
-	return;		/*Dunno what this is*/
-      /* Now we need to search the symbol table to find the psect and
-         offset for this variable.  */
-      *pnt1 = '\0';
-      vsp = VMS_Symbols;
-      while (vsp)
-	{
-	  pnt = S_GET_NAME (vsp->Symbol);
-	  if (pnt && *pnt++ == '_'
-	      /* make sure name is the same and symbol type matches */
-	      && strcmp (pnt, str) == 0
-	      && (S_GET_RAW_TYPE (vsp->Symbol) == type1
-		  || S_GET_RAW_TYPE (vsp->Symbol) == type2))
-	    break;
-	  vsp = vsp->Next;
-	}
-      if (vsp)
-	{
-	  VMS_DBG_record (spnt, vsp->Psect_Index, vsp->Psect_Offset, str);
-	  *pnt1 = ':';		/* and restore the string */
-	  return;
-	}
-      /* The symbol was not in the symbol list, but it may be an
-         "entry point" if it was a constant.  */
-      for (sp1 = symbol_rootP; sp1; sp1 = symbol_next (sp1))
-	{
-	  /* Dispatch on STAB type.  */
-	  if (S_IS_DEBUG (sp1) || (S_GET_TYPE (sp1) != N_TEXT))
-	    continue;
-	  pnt = S_GET_NAME (sp1);
-	  if (*pnt == '_')
-	    pnt++;
-	  if (strcmp (pnt, str) == 0)
-	    {
-	      if (!gave_compiler_message && expected_type == 'G')
-		{
-		  char *long_const_msg = _("\
-***Warning - the assembly code generated by the compiler has placed \n\
- global constant(s) in the text psect.  These will not be available to \n\
- other modules, since this is not the correct way to handle this. You \n\
- have two options: 1) get a patched compiler that does not put global \n\
- constants in the text psect, or 2) remove the 'const' keyword from \n\
- definitions of global variables in your source module(s).  Don't say \n\
- I didn't warn you! \n");
-
-		  as_tsktsk (long_const_msg);
-		  gave_compiler_message = 1;
-		}
-	      VMS_DBG_record (spnt,
-			      Text_Psect,
-			      S_GET_VALUE (sp1),
-			      str);
-	      *pnt1 = ':';
-	      /* Fool assembler to not output this as a routine in the TBT.  */
-	      pnt1 = S_GET_NAME (sp1);
-	      *pnt1 = 'L';
-	      S_SET_NAME (sp1, pnt1);
-	      return;
-	    }
-	}
-    }
-
-  /* ...and restore the string.  */
-  *pnt1 = ':';
-}
-
-/* Simpler interfaces into VMS_stab_parse().  */
-
-static void
-VMS_GSYM_Parse (symbolS *sp, int Text_Psect)
-{				/* Global variables */
-  VMS_stab_parse (sp, 'G', (N_UNDF | N_EXT), (N_DATA | N_EXT), Text_Psect);
-}
-
-static void
-VMS_LCSYM_Parse (symbolS *sp, int Text_Psect)
-{
-  VMS_stab_parse (sp, 'S', N_BSS, -1, Text_Psect);
-}
-
-static void
-VMS_STSYM_Parse (symbolS *sp, int Text_Psect)
-{
-  VMS_stab_parse (sp, 'S', N_DATA, -1, Text_Psect);
-}
-
-/* For register symbols, we must figure out what range of addresses
-   within the psect are valid.  We will use the brackets in the stab
-   directives to give us guidance as to the PC range that this variable
-   is in scope.  I am still not completely comfortable with this but
-   as I learn more, I seem to get a better handle on what is going on.
-   Caveat Emptor.  */
-
-static void
-VMS_RSYM_Parse (symbolS *sp, symbolS *Current_Routine ATTRIBUTE_UNUSED,
-		int Text_Psect)
-{
-  symbolS *symbolP;
-  struct VMS_DBG_Symbol *spnt;
-  char *pnt;
-  char *pnt1;
-  char *str;
-  int dbx_type;
-  int len;
-  int i = 0;
-  int bcnt = 0;
-  int Min_Offset = -1;		/* min PC of validity */
-  int Max_Offset = 0;		/* max PC of validity */
-
-  for (symbolP = sp; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Dispatch on STAB type.  */
-      switch (S_GET_RAW_TYPE (symbolP))
-	{
-	case N_LBRAC:
-	  if (bcnt++ == 0)
-	    Min_Offset = S_GET_VALUE (symbolP);
-	  break;
-	case N_RBRAC:
-	  if (--bcnt == 0)
-	    Max_Offset = S_GET_VALUE (symbolP) - 1;
-	  break;
-	}
-      if ((Min_Offset != -1) && (bcnt == 0))
-	break;
-      if (S_GET_RAW_TYPE (symbolP) == N_FUN)
-	{
-	  pnt = (char *) strchr (S_GET_NAME (symbolP), ':') + 1;
-	  if (*pnt == 'F' || *pnt == 'f') break;
-	}
-    }
-
-  /* Check to see that the addresses were defined.  If not, then there
-     were no brackets in the function, and we must try to search for
-     the next function.  Since functions can be in any order, we should
-     search all of the symbol list to find the correct ending address.  */
-  if (Min_Offset == -1)
-    {
-      int Max_Source_Offset;
-      int This_Offset;
-
-      Min_Offset = S_GET_VALUE (sp);
-      Max_Source_Offset = Min_Offset;	/* just in case no N_SLINEs found */
-      for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-	switch (S_GET_RAW_TYPE (symbolP))
-	  {
-	  case N_TEXT | N_EXT:
-	    This_Offset = S_GET_VALUE (symbolP);
-	    if (This_Offset > Min_Offset && This_Offset < Max_Offset)
-	      Max_Offset = This_Offset;
-	    break;
-	  case N_SLINE:
-	    This_Offset = S_GET_VALUE (symbolP);
-	    if (This_Offset > Max_Source_Offset)
-	      Max_Source_Offset = This_Offset;
-	    break;
-	  }
-      /* If this is the last routine, then we use the PC of the last source
-         line as a marker of the max PC for which this reg is valid.  */
-      if (Max_Offset == 0x7fffffff)
-	Max_Offset = Max_Source_Offset;
-    }
-
-  dbx_type = 0;
-  str = S_GET_NAME (sp);
-  if ((pnt = (char *) strchr (str, ':')) == 0)
-    return;			/* no colon present */
-  pnt1 = pnt;			/* save this for later*/
-  pnt++;
-  if (*pnt != 'r')
-    return;
-  pnt = cvt_integer (pnt + 1, &dbx_type);
-  spnt = find_symbol (dbx_type);
-  if (!spnt)
-    return;			/*Dunno what this is yet*/
-  *pnt1 = '\0';
-  pnt = fix_name (S_GET_NAME (sp));	/* if there are bad characters in name, convert them */
-  len = strlen (pnt);
-  Local[i++] = 25 + len;
-  Local[i++] = spnt->VMS_type;
-  Local[i++] = DST_K_VFLAGS_TVS;	/* trailing value specified */
-  COPY_LONG (&Local[i], 1 + len);	/* relative offset, beyond name */
-  i += 4;
-  Local[i++] = len;			/* name length (ascic prefix) */
-  while (*pnt != '\0')
-    Local[i++] = *pnt++;
-  Local[i++] = DST_K_VS_FOLLOWS;	/* value specification follows */
-  COPY_SHORT (&Local[i], 15);		/* length of rest of record */
-  i += 2;
-  Local[i++] = DST_K_VS_ALLOC_SPLIT;	/* split lifetime */
-  Local[i++] = 1;			/* one binding follows */
-  VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-  i = 0;
-  VMS_Set_Data (Text_Psect, Min_Offset, OBJ_S_C_DBG, 1);
-  VMS_Set_Data (Text_Psect, Max_Offset, OBJ_S_C_DBG, 1);
-  Local[i++] = DST_K_VALKIND_REG;		/* nested value spec */
-  COPY_LONG (&Local[i], S_GET_VALUE (sp));
-  i += 4;
-  VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-  *pnt1 = ':';
-  if (spnt->VMS_type == DBG_S_C_ADVANCED_TYPE)
-    generate_suffix (spnt, 0);
-}
-
-/* This function examines a structure definition, checking all of the elements
-   to make sure that all of them are fully defined.  The only thing that we
-   kick out are arrays of undefined structs, since we do not know how big
-   they are.  All others we can handle with a normal forward reference.  */
-
-static int
-forward_reference (char *pnt)
-{
-  struct VMS_DBG_Symbol *spnt, *spnt1;
-  int i;
-
-  pnt = cvt_integer (pnt + 1, &i);
-  if (*pnt == ';')
-    return 0;			/* no forward references */
-  do
-    {
-      pnt = (char *) strchr (pnt, ':');
-      pnt = cvt_integer (pnt + 1, &i);
-      spnt = find_symbol (i);
-      while (spnt && (spnt->advanced == POINTER || spnt->advanced == ARRAY))
-	{
-	  spnt1 = find_symbol (spnt->type2);
-	  if (spnt->advanced == ARRAY && !spnt1)
-	    return 1;
-	  spnt = spnt1;
-	}
-      pnt = cvt_integer (pnt + 1, &i);
-      pnt = cvt_integer (pnt + 1, &i);
-    } while (*++pnt != ';');
-  return 0;			/* no forward references found */
-}
-
-/* Used to check a single element of a structure on the final pass.  */
-
-static int
-final_forward_reference (struct VMS_DBG_Symbol *spnt)
-{
-  struct VMS_DBG_Symbol *spnt1;
-
-  while (spnt && (spnt->advanced == POINTER || spnt->advanced == ARRAY))
-    {
-      spnt1 = find_symbol (spnt->type2);
-      if (spnt->advanced == ARRAY && !spnt1)
-	return 1;
-      spnt = spnt1;
-    }
-  return 0;	/* no forward references found */
-}
-
-/* This routine parses the stabs directives to find any definitions of dbx
-   type numbers.  It makes a note of all of them, creating a structure
-   element of VMS_DBG_Symbol that describes it.  This also generates the
-   info for the debugger that describes the struct/union/enum, so that
-   further references to these data types will be by number
-
-   We have to process pointers right away, since there can be references
-   to them later in the same stabs directive.  We cannot have forward
-   references to pointers, (but we can have a forward reference to a
-   pointer to a structure/enum/union) and this is why we process them
-   immediately.  After we process the pointer, then we search for defs
-   that are nested even deeper.
-
-   8/15/92: We have to process arrays right away too, because there can
-   be multiple references to identical array types in one structure
-   definition, and only the first one has the definition.  */
-
-static int
-VMS_typedef_parse (char *str)
-{
-  char *pnt;
-  char *pnt1;
-  const char *pnt2;
-  int i;
-  int dtype;
-  struct forward_ref *fpnt;
-  int i1, i2, i3, len;
-  struct VMS_DBG_Symbol *spnt;
-  struct VMS_DBG_Symbol *spnt1;
-
-  /* check for any nested def's */
-  pnt = (char *) strchr (str + 1, '=');
-  if (pnt && str[1] != '*' && (str[1] != 'a' || str[2] != 'r')
-      && VMS_typedef_parse (pnt) == 1)
-    return 1;
-  /* now find dbx_type of entry */
-  pnt = str - 1;
-  if (*pnt == 'c')
-    {				/* check for static constants */
-      *str = '\0';		/* for now we ignore them */
-      return 0;
-    }
-  while ((*pnt <= '9') && (*pnt >= '0'))
-    pnt--;
-  pnt++;			/* and get back to the number */
-  cvt_integer (pnt, &i1);
-  spnt = find_symbol (i1);
-  /* First see if this has been defined already, due to forward reference.  */
-  if (!spnt)
-    {
-      i2 = SYMTYP_HASH (i1);
-      spnt = xmalloc (sizeof (struct VMS_DBG_Symbol));
-      spnt->next = VMS_Symbol_type_list[i2];
-      VMS_Symbol_type_list[i2] = spnt;
-      spnt->dbx_type = i1;	/* and save the type */
-      spnt->type2 = spnt->VMS_type = spnt->data_size = 0;
-      spnt->index_min = spnt->index_max = spnt->struc_numb = 0;
-    }
-
-  /* For structs and unions, do a partial parse, otherwise we sometimes get
-     circular definitions that are impossible to resolve.  We read enough
-     info so that any reference to this type has enough info to be resolved.  */
-
-  /* Point to character past equal sign.  */
-  pnt = str + 1;
-
-  if (*pnt >= '0' && *pnt <= '9')
-    {
-      if (type_check ("void"))
-	{			/* this is the void symbol */
-	  *str = '\0';
-	  spnt->advanced = VOID;
-	  return 0;
-	}
-      if (type_check ("unknown type"))
-	{
-	  *str = '\0';
-	  spnt->advanced = UNKNOWN;
-	  return 0;
-	}
-      pnt1 = cvt_integer (pnt, &i1);
-      if (i1 != spnt->dbx_type)
-	{
-	  spnt->advanced = ALIAS;
-	  spnt->type2 = i1;
-	  strcpy (str, pnt1);
-	  return 0;
-	}
-      as_tsktsk (_("debugginer output: %d is an unknown untyped variable."),
-		 spnt->dbx_type);
-      return 1;			/* do not know what this is */
-    }
-
-  /* Point to character past equal sign.  */
-  pnt = str + 1;
-
-  switch (*pnt)
-    {
-    case 'r':
-      spnt->advanced = BASIC;
-      if (type_check ("int"))
-	{
-	  spnt->VMS_type = DBG_S_C_SLINT;
-	  spnt->data_size = 4;
-	}
-      else if (type_check ("long int"))
-	{
-	  spnt->VMS_type = DBG_S_C_SLINT;
-	  spnt->data_size = 4;
-	}
-      else if (type_check ("unsigned int"))
-	{
-	  spnt->VMS_type = DBG_S_C_ULINT;
-	  spnt->data_size = 4;
-	}
-      else if (type_check ("long unsigned int"))
-	{
-	  spnt->VMS_type = DBG_S_C_ULINT;
-	  spnt->data_size = 4;
-	}
-      else if (type_check ("short int"))
-	{
-	  spnt->VMS_type = DBG_S_C_SSINT;
-	  spnt->data_size = 2;
-	}
-      else if (type_check ("short unsigned int"))
-	{
-	  spnt->VMS_type = DBG_S_C_USINT;
-	  spnt->data_size = 2;
-	}
-      else if (type_check ("char"))
-	{
-	  spnt->VMS_type = DBG_S_C_SCHAR;
-	  spnt->data_size = 1;
-	}
-      else if (type_check ("signed char"))
-	{
-	  spnt->VMS_type = DBG_S_C_SCHAR;
-	  spnt->data_size = 1;
-	}
-      else if (type_check ("unsigned char"))
-	{
-	  spnt->VMS_type = DBG_S_C_UCHAR;
-	  spnt->data_size = 1;
-	}
-      else if (type_check ("float"))
-	{
-	  spnt->VMS_type = DBG_S_C_REAL4;
-	  spnt->data_size = 4;
-	}
-      else if (type_check ("double"))
-	{
-	  spnt->VMS_type = vax_g_doubles ? DBG_S_C_REAL8_G : DBG_S_C_REAL8;
-	  spnt->data_size = 8;
-	}
-      else if (type_check ("long double"))
-	{
-	  /* same as double, at least for now */
-	  spnt->VMS_type = vax_g_doubles ? DBG_S_C_REAL8_G : DBG_S_C_REAL8;
-	  spnt->data_size = 8;
-	}
-      else if (type_check ("long long int"))
-	{
-	  spnt->VMS_type = DBG_S_C_SQUAD;	/* signed quadword */
-	  spnt->data_size = 8;
-	}
-      else if (type_check ("long long unsigned int"))
-	{
-	  spnt->VMS_type = DBG_S_C_UQUAD;	/* unsigned quadword */
-	  spnt->data_size = 8;
-	}
-      else if (type_check ("complex float"))
-	{
-	  spnt->VMS_type = DBG_S_C_COMPLX4;
-	  spnt->data_size = 2 * 4;
-	}
-      else if (type_check ("complex double"))
-	{
-	  spnt->VMS_type = vax_g_doubles ? DBG_S_C_COMPLX8_G : DBG_S_C_COMPLX8;
-	  spnt->data_size = 2 * 8;
-	}
-      else if (type_check ("complex long double"))
-	{
-	  /* same as complex double, at least for now */
-	  spnt->VMS_type = vax_g_doubles ? DBG_S_C_COMPLX8_G : DBG_S_C_COMPLX8;
-	  spnt->data_size = 2 * 8;
-	}
-      else
-	{
-	  /* Shouldn't get here, but if we do, something
-	     more substantial ought to be done...  */
-	  spnt->VMS_type = 0;
-	  spnt->data_size = 0;
-	}
-      if (spnt->VMS_type != 0)
-	setup_basic_type (spnt);
-      pnt1 = (char *) strchr (str, ';') + 1;
-      break;
-    case 's':
-    case 'u':
-      spnt->advanced = (*pnt == 's') ? STRUCT : UNION;
-      spnt->VMS_type = DBG_S_C_ADVANCED_TYPE;
-      pnt1 = cvt_integer (pnt + 1, &spnt->data_size);
-      if (!final_pass && forward_reference (pnt))
-	{
-	  spnt->struc_numb = -1;
-	  return 1;
-	}
-      spnt->struc_numb = ++structure_count;
-      pnt1--;
-      pnt = get_struct_name (str);
-      VMS_Def_Struct (spnt->struc_numb);
-      i = 0;
-      for (fpnt = f_ref_root; fpnt; fpnt = fpnt->next)
-	if (fpnt->dbx_type == spnt->dbx_type)
-	  {
-	    fpnt->resolved = 'Y';
-	    VMS_Set_Struct (fpnt->struc_numb);
-	    VMS_Store_Struct (spnt->struc_numb);
-	    i++;
-	  }
-      if (i > 0)
-	VMS_Set_Struct (spnt->struc_numb);
-      i = 0;
-      Local[i++] = 11 + strlen (pnt);
-      Local[i++] = DBG_S_C_STRUCT_START;
-      Local[i++] = DST_K_VFLAGS_NOVAL;	/* structure definition only */
-      COPY_LONG (&Local[i], 0L);	/* hence value is unused */
-      i += 4;
-      Local[i++] = strlen (pnt);
-      pnt2 = pnt;
-      while (*pnt2 != '\0')
-	Local[i++] = *pnt2++;
-      i2 = spnt->data_size * 8;	/* number of bits */
-      COPY_LONG (&Local[i], i2);
-      i += 4;
-      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-      i = 0;
-      if (pnt != symbol_name)
-	{
-	  pnt += strlen (pnt);
-	  /* Replace colon for later.  */
-	  *pnt = ':';
-	}
-
-      while (*++pnt1 != ';')
-	{
-	  pnt = (char *) strchr (pnt1, ':');
-	  *pnt = '\0';
-	  pnt2 = pnt1;
-	  pnt1 = cvt_integer (pnt + 1, &dtype);
-	  pnt1 = cvt_integer (pnt1 + 1, &i2);
-	  pnt1 = cvt_integer (pnt1 + 1, &i3);
-	  spnt1 = find_symbol (dtype);
-	  len = strlen (pnt2);
-	  if (spnt1 && (spnt1->advanced == BASIC || spnt1->advanced == ENUM)
-	      && ((i3 != spnt1->data_size * 8) || (i2 % 8 != 0)))
-	    {			/* bitfield */
-	      if (USE_BITSTRING_DESCRIPTOR (spnt1))
-		{
-		  /* This uses a type descriptor, which doesn't work if
-		     the enclosing structure has been placed in a register.
-		     Also, enum bitfields degenerate to simple integers.  */
-		  int unsigned_type = (spnt1->VMS_type == DBG_S_C_ULINT
-				    || spnt1->VMS_type == DBG_S_C_USINT
-				    || spnt1->VMS_type == DBG_S_C_UCHAR
-				    || spnt1->VMS_type == DBG_S_C_UQUAD
-				    || spnt1->advanced == ENUM);
-		  Apoint = 0;
-		  fpush (19 + len, 1);
-		  fpush (unsigned_type ? DBG_S_C_UBITU : DBG_S_C_SBITU, 1);
-		  fpush (DST_K_VFLAGS_DSC, 1);	/* specified by descriptor */
-		  fpush (1 + len, 4);	/* relative offset to descriptor */
-		  fpush (len, 1);		/* length byte (ascic prefix) */
-		  while (*pnt2 != '\0')	/* name bytes */
-		    fpush (*pnt2++, 1);
-		  fpush (i3, 2);	/* dsc length == size of bitfield */
-					/* dsc type == un?signed bitfield */
-		  fpush (unsigned_type ? DBG_S_C_UBITU : DBG_S_C_SBITU, 1);
-		  fpush (DSC_K_CLASS_UBS, 1);	/* dsc class == unaligned bitstring */
-		  fpush (0x00, 4);		/* dsc pointer == zeroes */
-		  fpush (i2, 4);	/* start position */
-		  VMS_Store_Immediate_Data (Asuffix, Apoint, OBJ_S_C_DBG);
-		  Apoint = 0;
-		}
-	      else
-		{
-		  /* Use a "novel length" type specification, which works
-		     right for register structures and for enum bitfields
-		     but results in larger object modules.  */
-		  Local[i++] = 7 + len;
-		  Local[i++] = DBG_S_C_ADVANCED_TYPE;	/* type spec follows */
-		  Local[i++] = DBG_S_C_STRUCT_ITEM;	/* value is a bit offset */
-		  COPY_LONG (&Local[i], i2);		/* bit offset */
-		  i += 4;
-		  Local[i++] = strlen (pnt2);
-		  while (*pnt2 != '\0')
-		    Local[i++] = *pnt2++;
-		  VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-		  i = 0;
-		  bitfield_suffix (spnt1, i3);
-	     }
-	    }
-	  else /* Not a bitfield.  */
-	    {
-	      /* Check if this is a forward reference.  */
-	      if (final_pass && final_forward_reference (spnt1))
-		{
-		  as_tsktsk (_("debugger output: structure element `%s' has undefined type"),
-			   pnt2);
-		  continue;
-		}
-	      Local[i++] = 7 + len;
-	      Local[i++] = spnt1 ? spnt1->VMS_type : DBG_S_C_ADVANCED_TYPE;
-	      Local[i++] = DBG_S_C_STRUCT_ITEM;
-	      COPY_LONG (&Local[i], i2);		/* bit offset */
-	      i += 4;
-	      Local[i++] = strlen (pnt2);
-	      while (*pnt2 != '\0')
-		Local[i++] = *pnt2++;
-	      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-	      i = 0;
-	      if (!spnt1)
-		generate_suffix (spnt1, dtype);
-	      else if (spnt1->VMS_type == DBG_S_C_ADVANCED_TYPE)
-		generate_suffix (spnt1, 0);
-	    }
-	}
-      pnt1++;
-      Local[i++] = 0x01;	/* length byte */
-      Local[i++] = DBG_S_C_STRUCT_END;
-      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-      i = 0;
-      break;
-    case 'e':
-      spnt->advanced = ENUM;
-      spnt->VMS_type = DBG_S_C_ADVANCED_TYPE;
-      spnt->struc_numb = ++structure_count;
-      spnt->data_size = 4;
-      VMS_Def_Struct (spnt->struc_numb);
-      i = 0;
-      for (fpnt = f_ref_root; fpnt; fpnt = fpnt->next)
-	if (fpnt->dbx_type == spnt->dbx_type)
-	  {
-	    fpnt->resolved = 'Y';
-	    VMS_Set_Struct (fpnt->struc_numb);
-	    VMS_Store_Struct (spnt->struc_numb);
-	    i++;
-	  }
-      if (i > 0)
-	VMS_Set_Struct (spnt->struc_numb);
-      i = 0;
-      len = strlen (symbol_name);
-      Local[i++] = 3 + len;
-      Local[i++] = DBG_S_C_ENUM_START;
-      Local[i++] = 4 * 8;		/* enum values are 32 bits */
-      Local[i++] = len;
-      pnt2 = symbol_name;
-      while (*pnt2 != '\0')
-	Local[i++] = *pnt2++;
-      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-      i = 0;
-      while (*++pnt != ';')
-	{
-	  pnt1 = (char *) strchr (pnt, ':');
-	  *pnt1++ = '\0';
-	  pnt1 = cvt_integer (pnt1, &i1);
-	  len = strlen (pnt);
-	  Local[i++] = 7 + len;
-	  Local[i++] = DBG_S_C_ENUM_ITEM;
-	  Local[i++] = DST_K_VALKIND_LITERAL;
-	  COPY_LONG (&Local[i], i1);
-	  i += 4;
-	  Local[i++] = len;
-	  pnt2 = pnt;
-	  while (*pnt != '\0')
-	    Local[i++] = *pnt++;
-	  VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-	  i = 0;
-	  pnt = pnt1;		/* Skip final semicolon */
-	}
-      Local[i++] = 0x01;	/* len byte */
-      Local[i++] = DBG_S_C_ENUM_END;
-      VMS_Store_Immediate_Data (Local, i, OBJ_S_C_DBG);
-      i = 0;
-      pnt1 = pnt + 1;
-      break;
-    case 'a':
-      spnt->advanced = ARRAY;
-      spnt->VMS_type = DBG_S_C_ADVANCED_TYPE;
-      pnt = (char *) strchr (pnt, ';');
-      if (!pnt)
-	return 1;
-      pnt1 = cvt_integer (pnt + 1, &spnt->index_min);
-      pnt1 = cvt_integer (pnt1 + 1, &spnt->index_max);
-      pnt1 = cvt_integer (pnt1 + 1, &spnt->type2);
-      pnt = (char *) strchr (str + 1, '=');
-      if (pnt && VMS_typedef_parse (pnt) == 1)
-	return 1;
-      break;
-    case 'f':
-      spnt->advanced = FUNCTION;
-      spnt->VMS_type = DBG_S_C_FUNCTION_ADDR;
-      /* this masquerades as a basic type*/
-      spnt->data_size = 4;
-      pnt1 = cvt_integer (pnt + 1, &spnt->type2);
-      break;
-    case '*':
-      spnt->advanced = POINTER;
-      spnt->VMS_type = DBG_S_C_ADVANCED_TYPE;
-      spnt->data_size = 4;
-      pnt1 = cvt_integer (pnt + 1, &spnt->type2);
-      pnt = (char *) strchr (str + 1, '=');
-      if (pnt && VMS_typedef_parse (pnt) == 1)
-	return 1;
-      break;
-    default:
-      spnt->advanced = UNKNOWN;
-      spnt->VMS_type = 0;
-      as_tsktsk (_("debugger output: %d is an unknown type of variable."),
-		 spnt->dbx_type);
-      return 1;			/* unable to decipher */
-    }
-  /* This removes the evidence of the definition so that the outer levels
-     of parsing do not have to worry about it.  */
-  pnt = str;
-  while (*pnt1 != '\0')
-    *pnt++ = *pnt1++;
-  *pnt = '\0';
-  return 0;
-}
-
-/* This is the root routine that parses the stabs entries for definitions.
-   it calls VMS_typedef_parse, which can in turn call itself.  We need to
-   be careful, since sometimes there are forward references to other symbol
-   types, and these cannot be resolved until we have completed the parse.
-
-   Also check and see if we are using continuation stabs, if we are, then
-   paste together the entire contents of the stab before we pass it to
-   VMS_typedef_parse.  */
-
-static void
-VMS_LSYM_Parse (void)
-{
-  char *pnt;
-  char *pnt1;
-  char *pnt2;
-  char *str;
-  char *parse_buffer = 0;
-  char fixit[10];
-  int incomplete, pass, incom1;
-  struct forward_ref *fpnt;
-  symbolS *sp;
-
-  pass = 0;
-  final_pass = 0;
-  incomplete = 0;
-  do
-    {
-      incom1 = incomplete;
-      incomplete = 0;
-      for (sp = symbol_rootP; sp; sp = symbol_next (sp))
-	{
-	  /* Deal with STAB symbols.  */
-	  if (S_IS_DEBUG (sp))
-	    {
-	      /* Dispatch on STAB type.  */
-	      switch (S_GET_RAW_TYPE (sp))
-		{
-		case N_GSYM:
-		case N_LCSYM:
-		case N_STSYM:
-		case N_PSYM:
-		case N_RSYM:
-		case N_LSYM:
-		case N_FUN:	/* Sometimes these contain typedefs. */
-		  str = S_GET_NAME (sp);
-		  symbol_name = str;
-		  pnt = str + strlen (str) - 1;
-		  if (*pnt == '?')  /* Continuation stab.  */
-		    {
-		      symbolS *spnext;
-		      int tlen = 0;
-
-		      spnext = sp;
-		      do
-			{
-			  tlen += strlen (str) - 1;
-			  spnext = symbol_next (spnext);
-			  str = S_GET_NAME (spnext);
-			  pnt = str + strlen (str) - 1;
-			}
-		      while (*pnt == '?');
-
-		      tlen += strlen (str);
-		      parse_buffer = xmalloc (tlen + 1);
-		      strcpy (parse_buffer, S_GET_NAME (sp));
-		      pnt2 = parse_buffer + strlen (parse_buffer) - 1;
-		      *pnt2 = '\0';
-		      spnext = sp;
-
-		      do
-			{
-			  spnext = symbol_next (spnext);
-			  str = S_GET_NAME (spnext);
-			  strcat (pnt2, str);
-			  pnt2 +=  strlen (str) - 1;
-			  *str = '\0';  /* Erase this string  */
-			  /* S_SET_NAME (spnext, str); */
-			  if (*pnt2 != '?') break;
-			  *pnt2 = '\0';
-			}
-		      while (1);
-
-		      str = parse_buffer;
-		      symbol_name = str;
-		    }
-
-		  if ((pnt = (char *) strchr (str, ':')) != 0)
-		    {
-		      *pnt = '\0';
-		      pnt1 = pnt + 1;
-		      if ((pnt2 = (char *) strchr (pnt1, '=')) != 0)
-			incomplete += VMS_typedef_parse (pnt2);
-		      if (parse_buffer)
-			{
-			  /*  At this point the parse buffer should just
-			      contain name:nn.  If it does not, then we
-			      are in real trouble.  Anyway, this is always
-			      shorter than the original line.  */
-			  pnt2 = S_GET_NAME (sp);
-			  strcpy (pnt2, parse_buffer);
-			  /* S_SET_NAME (sp, pnt2); */
-			  free (parse_buffer),  parse_buffer = 0;
-			}
-		      /* Put back colon to restore dbx_type.  */
-		      *pnt = ':';
-		    }
-		  break;
-		}
-	    }
-	}
-      pass++;
-
-      /* Make one last pass, if needed, and define whatever we can
-         that is left.  */
-      if (final_pass == 0 && incomplete == incom1)
-	{
-	  final_pass = 1;
-	  incom1++;	/* Force one last pass through.  */
-	}
-    }
-  while (incomplete != 0 && incomplete != incom1);
-
-  if (incomplete != 0)
-    as_tsktsk (_("debugger output: Unable to resolve %d circular references."),
-	       incomplete);
-
-  fpnt = f_ref_root;
-  symbol_name = "\0";
-  while (fpnt)
-    {
-      if (fpnt->resolved != 'Y')
-	{
-	  if (find_symbol (fpnt->dbx_type))
-	    {
-	      as_tsktsk (_("debugger forward reference error, dbx type %d"),
-			 fpnt->dbx_type);
-	      break;
-	    }
-	  fixit[0] = 0;
-	  sprintf (&fixit[1], "%d=s4;", fpnt->dbx_type);
-	  pnt2 = (char *) strchr (&fixit[1], '=');
-	  VMS_typedef_parse (pnt2);
-	}
-      fpnt = fpnt->next;
-    }
-}
-
-static void
-Define_Local_Symbols (symbolS *s0P, symbolS *s2P, symbolS *Current_Routine,
-		      int Text_Psect)
-{
-  symbolS *s1P;		/* Each symbol from s0P .. s2P (exclusive).  */
-
-  for (s1P = symbol_next (s0P); s1P != s2P; s1P = symbol_next (s1P))
-    {
-      if (!s1P)
-	break;		/* and return */
-      if (S_GET_RAW_TYPE (s1P) == N_FUN)
-	{
-	  char *pnt = (char *) strchr (S_GET_NAME (s1P), ':') + 1;
-	  if (*pnt == 'F' || *pnt == 'f') break;
-	}
-      if (!S_IS_DEBUG (s1P))
-	continue;
-      /* Dispatch on STAB type.  */
-      switch (S_GET_RAW_TYPE (s1P))
-	{
-	default:
-	  /* Not left or right brace.  */
-	  continue;
-
-	case N_LSYM:
-	case N_PSYM:
-	  VMS_local_stab_Parse (s1P);
-	  break;
-
-	case N_RSYM:
-	  VMS_RSYM_Parse (s1P, Current_Routine, Text_Psect);
-	  break;
-	}
-    }
-}
-
-/* This function crawls the symbol chain searching for local symbols that
-   need to be described to the debugger.  When we enter a new scope with
-   a "{", it creates a new "block", which helps the debugger keep track
-   of which scope we are currently in.  */
-
-static symbolS *
-Define_Routine (symbolS *s0P, int Level, symbolS *Current_Routine,
-		int Text_Psect)
-{
-  symbolS *s1P;
-  valueT Offset;
-  int rcount = 0;
-
-  for (s1P = symbol_next (s0P); s1P != 0; s1P = symbol_next (s1P))
-    {
-      if (S_GET_RAW_TYPE (s1P) == N_FUN)
-	{
-	  char *pnt = (char *) strchr (S_GET_NAME (s1P), ':') + 1;
-	  if (*pnt == 'F' || *pnt == 'f') break;
-	}
-      if (!S_IS_DEBUG (s1P))
-	continue;
-      /* Dispatch on STAB type.  */
-      switch (S_GET_RAW_TYPE (s1P))
-	{
-	default:
-	  continue;
-
-	case N_LBRAC:
-	  if (Level != 0)
-	    {
-	      char str[10];
-	      sprintf (str, "$%d", rcount++);
-	      VMS_TBT_Block_Begin (s1P, Text_Psect, str);
-	    }
-	  /* Side-effect: fully resolve symbol.  */
-	  Offset = S_GET_VALUE (s1P);
-	  Define_Local_Symbols (s0P, s1P, Current_Routine, Text_Psect);
-	  s1P = Define_Routine (s1P, Level + 1, Current_Routine, Text_Psect);
-	  if (Level != 0)
-	    VMS_TBT_Block_End (S_GET_VALUE (s1P) - Offset);
-	  s0P = s1P;
-	  break;
-
-	case N_RBRAC:
-	  return s1P;
-	}
-    }
-
-  /* We end up here if there were no brackets in this function.
-     Define everything.  */
-  Define_Local_Symbols (s0P, (symbolS *)0, Current_Routine, Text_Psect);
-  return s1P;
-}
-
-
-#ifndef VMS
-#include <sys/types.h>
-#include <time.h>
-static void get_VMS_time_on_unix (char *);
-
-/* Manufacture a VMS-like time string on a Unix based system.  */
-static void
-get_VMS_time_on_unix (char *Now)
-{
-  char *pnt;
-  time_t timeb;
-
-  time (&timeb);
-  pnt = ctime (&timeb);
-  pnt[3] = 0;
-  pnt[7] = 0;
-  pnt[10] = 0;
-  pnt[16] = 0;
-  pnt[24] = 0;
-  sprintf (Now, "%2s-%3s-%s %s", pnt + 8, pnt + 4, pnt + 20, pnt + 11);
-}
-#endif /* not VMS */
-
-/* Write the MHD (Module Header) records.  */
-
-static void
-Write_VMS_MHD_Records (void)
-{
-  const char *cp;
-  char *cp1;
-  int i;
-#ifdef VMS
-  struct { unsigned short len, mbz; char *ptr; } Descriptor;
-#endif
-  char Now[17+1];
-
-  /* We are writing a module header record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_HDR);
-  /* MAIN MODULE HEADER RECORD.  */
-  /* Store record type and header type.  */
-  PUT_CHAR (OBJ_S_C_HDR);
-  PUT_CHAR (MHD_S_C_MHD);
-  /* Structure level is 0.  */
-  PUT_CHAR (OBJ_S_C_STRLVL);
-  /* Maximum record size is size of the object record buffer.  */
-  PUT_SHORT (sizeof (Object_Record_Buffer));
-
-  /* FIXME:  module name and version should be user
-	     specifiable via `.ident' and/or `#pragma ident'.  */
-
-  /* Get module name (the FILENAME part of the object file).  */
-  cp = out_file_name;
-  cp1 = Module_Name;
-  while (*cp)
-    {
-      if (*cp == ']' || *cp == '>' || *cp == ':' || *cp == '/')
-	{
-	  cp1 = Module_Name;
-	  cp++;
-	  continue;
-	}
-      *cp1++ = TOUPPER (*cp++);
-    }
-  *cp1 = '\0';
-
-  /* Limit it to 31 characters and store in the object record.  */
-  while (--cp1 >= Module_Name)
-    if (*cp1 == '.')
-      *cp1 = '\0';
-  if (strlen (Module_Name) > 31)
-    {
-      if (flag_hash_long_names)
-	as_tsktsk (_("Module name truncated: %s\n"), Module_Name);
-      Module_Name[31] = '\0';
-    }
-  PUT_COUNTED_STRING (Module_Name);
-  /* Module Version is "V1.0".  */
-  PUT_COUNTED_STRING ("V1.0");
-  /* Creation time is "now" (17 chars of time string): "dd-MMM-yyyy hh:mm".  */
-#ifndef VMS
-  get_VMS_time_on_unix (Now);
-#else /* VMS */
-  Descriptor.len = sizeof Now - 1;
-  Descriptor.mbz = 0;		/* type & class unspecified */
-  Descriptor.ptr = Now;
-  (void) sys$asctim ((unsigned short *)0, &Descriptor, (long *)0, 0);
-#endif /* VMS */
-  for (i = 0; i < 17; i++)
-    PUT_CHAR (Now[i]);
-  /* Patch time is "never" (17 zeros).  */
-  for (i = 0; i < 17; i++)
-    PUT_CHAR (0);
-  /* Force this to be a separate output record.  */
-  Flush_VMS_Object_Record_Buffer ();
-
-  /* LANGUAGE PROCESSOR NAME.  */
-
-  /* Store record type and header type.  */
-  PUT_CHAR (OBJ_S_C_HDR);
-  PUT_CHAR (MHD_S_C_LNM);
-
-  /* Store language processor name and version (not a counted string!).
-     This is normally supplied by the gcc driver for the command line
-     which invokes gas.  If absent, we fall back to gas's version.  */
-  
-  cp = compiler_version_string;
-  if (cp == 0)
-    {
-      cp = "GNU AS  V";
-      while (*cp)
-	PUT_CHAR (*cp++);
-      cp = VERSION;
-    }
-  while (*cp >= ' ')
-    PUT_CHAR (*cp++);
-  /* Force this to be a separate output record.  */
-  Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Write the EOM (End Of Module) record.  */
-
-static void
-Write_VMS_EOM_Record (int Psect, valueT Offset)
-{
-  /* We are writing an end-of-module record
-     (this assumes that the entry point will always be in a psect
-     represented by a single byte, which is the case for code in
-     Text_Psect==0).  */
-  
-  Set_VMS_Object_File_Record (OBJ_S_C_EOM);
-  PUT_CHAR (OBJ_S_C_EOM);	/* Record type.  */
-  PUT_CHAR (0);			/* Error severity level (we ignore it).  */
-  /* Store the entry point, if it exists.  */
-  if (Psect >= 0)
-    {
-      PUT_CHAR (Psect);
-      PUT_LONG (Offset);
-    }
-  /* Flush the record; this will be our final output.  */
-  Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* This hash routine borrowed from GNU-EMACS, and strengthened slightly
-   ERY.  */
-
-static int
-hash_string (const char *ptr)
-{
-  const unsigned char *p = (unsigned char *) ptr;
-  const unsigned char *end = p + strlen (ptr);
-  unsigned char c;
-  int hash = 0;
-
-  while (p != end)
-    {
-      c = *p++;
-      hash = ((hash << 3) + (hash << 15) + (hash >> 28) + c);
-    }
-  return hash;
-}
-
-/* Generate a Case-Hacked VMS symbol name (limited to 31 chars).  */
-
-static void
-VMS_Case_Hack_Symbol (const char *In, char *Out)
-{
-  long int init;
-  long int result;
-  char *pnt = 0;
-  char *new_name;
-  const char *old_name;
-  int i;
-  int destructor = 0;		/* Hack to allow for case sens in a destructor.  */
-  int truncate = 0;
-  int Case_Hack_Bits = 0;
-  int Saw_Dollar = 0;
-  static char Hex_Table[16] =
-  {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F'};
-
-  /* Kill any leading "_".  */
-  if ((In[0] == '_') && ((In[1] > '9') || (In[1] < '0')))
-    In++;
-
-  new_name = Out;		/* Save this for later.  */
-
-#if 0
-  if ((In[0] == '_') && (In[1] == '$') && (In[2] == '_'))
-    destructor = 1;
-#endif
-
-  /* We may need to truncate the symbol, save the hash for later.  */
-  result = (strlen (In) > 23) ? hash_string (In) : 0;
-  /* Is there a Psect Attribute to skip?  */
-  if (HAS_PSECT_ATTRIBUTES (In))
-    {
-      /* Yes: Skip it.  */
-      In += PSECT_ATTRIBUTES_STRING_LENGTH;
-      while (*In)
-	{
-	  if ((In[0] == '$') && (In[1] == '$'))
-	    {
-	      In += 2;
-	      break;
-	    }
-	  In++;
-	}
-    }
-
-  old_name = In;
-#if 0
-  if (strlen (In) > 31 && flag_hash_long_names)
-    as_tsktsk ("Symbol name truncated: %s\n", In);
-#endif
-  /* Do the case conversion.  */
-  /* Maximum of 23 chars */
-  i = 23;
-  while (*In && (--i >= 0))
-    {
-      Case_Hack_Bits <<= 1;
-      if (*In == '$')
-	Saw_Dollar = 1;
-      if ((destructor == 1) && (i == 21))
-	Saw_Dollar = 0;
-
-      switch (vms_name_mapping)
-	{
-	case 0:
-	  if (ISUPPER (*In))
-	    {
-	      *Out++ = *In++;
-	      Case_Hack_Bits |= 1;
-	    }
-	  else
-	    *Out++ = TOUPPER (*In++);
-	  break;
-
-	case 3:
-	  *Out++ = *In++;
-	  break;
-
-	case 2:
-	  if (ISLOWER (*In))
-	    *Out++ = *In++;
-	  else
-	    *Out++ = TOLOWER (*In++);
-	  break;
-	}
-    }
-  /* If we saw a dollar sign, we don't do case hacking.  */
-  if (flag_no_hash_mixed_case || Saw_Dollar)
-    Case_Hack_Bits = 0;
-
-  /* If we have more than 23 characters and everything is lowercase
-     we can insert the full 31 characters.  */
-  if (*In)
-    {
-      /* We have more than 23 characters
-         If we must add the case hack, then we have truncated the str.  */
-      pnt = Out;
-      truncate = 1;
-      if (Case_Hack_Bits == 0)
-	{
-	  /* And so far they are all lower case:
-	     Check up to 8 more characters
-	     and ensure that they are lowercase.  */
-	  for (i = 0; (In[i] != 0) && (i < 8); i++)
-	    if (ISUPPER (In[i]) && !Saw_Dollar && !flag_no_hash_mixed_case)
-	      break;
-
-	  if (In[i] == 0)
-	    truncate = 0;
-
-	  if ((i == 8) || (In[i] == 0))
-	    {
-	      /* They are:  Copy up to 31 characters
-	         to the output string.  */
-	      i = 8;
-	      while ((--i >= 0) && (*In))
-		switch (vms_name_mapping){
-		case 0: *Out++ = TOUPPER (*In++);
-		  break;
-		case 3: *Out++ = *In++;
-		  break;
-		case 2: *Out++ = TOLOWER (*In++);
-		  break;
-		}
-	    }
-	}
-    }
-  /* If there were any uppercase characters in the name we
-     take on the case hacking string.  */
-
-  /* Old behavior for regular GNU-C compiler.  */
-  if (!flag_hash_long_names)
-    truncate = 0;
-  if ((Case_Hack_Bits != 0) || (truncate == 1))
-    {
-      if (truncate == 0)
-	{
-	  *Out++ = '_';
-	  for (i = 0; i < 6; i++)
-	    {
-	      *Out++ = Hex_Table[Case_Hack_Bits & 0xf];
-	      Case_Hack_Bits >>= 4;
-	    }
-	  *Out++ = 'X';
-	}
-      else
-	{
-	  Out = pnt;		/* Cut back to 23 characters maximum.  */
-	  *Out++ = '_';
-	  for (i = 0; i < 7; i++)
-	    {
-	      init = result & 0x01f;
-	      *Out++ = (init < 10) ? ('0' + init) : ('A' + init - 10);
-	      result = result >> 5;
-	    }
-	}
-    }
-  /* Done.  */
-  *Out = 0;
-  if (truncate == 1 && flag_hash_long_names && flag_show_after_trunc)
-    as_tsktsk (_("Symbol %s replaced by %s\n"), old_name, new_name);
-}
-
-
-/* Scan a symbol name for a psect attribute specification.  */
-
-#define GLOBALSYMBOL_BIT	0x10000
-#define GLOBALVALUE_BIT		0x20000
-
-static void
-VMS_Modify_Psect_Attributes (const char *Name, int *Attribute_Pointer)
-{
-  int i;
-  const char *cp;
-  int Negate;
-  static const struct
-  {
-    const char *Name;
-    int Value;
-  } Attributes[] =
-  {
-    {"PIC", GPS_S_M_PIC},
-    {"LIB", GPS_S_M_LIB},
-    {"OVR", GPS_S_M_OVR},
-    {"REL", GPS_S_M_REL},
-    {"GBL", GPS_S_M_GBL},
-    {"SHR", GPS_S_M_SHR},
-    {"EXE", GPS_S_M_EXE},
-    {"RD", GPS_S_M_RD},
-    {"WRT", GPS_S_M_WRT},
-    {"VEC", GPS_S_M_VEC},
-    {"GLOBALSYMBOL", GLOBALSYMBOL_BIT},
-    {"GLOBALVALUE", GLOBALVALUE_BIT},
-    {0, 0}
-  };
-
-  /* Kill leading "_".  */
-  if (*Name == '_')
-    Name++;
-  /* Check for a PSECT attribute list.  */
-  if (!HAS_PSECT_ATTRIBUTES (Name))
-    return;
-  /* Skip the attribute list indicator.  */
-  Name += PSECT_ATTRIBUTES_STRING_LENGTH;
-  /* Process the attributes ("_" separated, "$" terminated).  */
-  while (*Name != '$')
-    {
-      /* Assume not negating.  */
-      Negate = 0;
-      /* Check for "NO".  */
-      if ((Name[0] == 'N') && (Name[1] == 'O'))
-	{
-	  /* We are negating (and skip the NO).  */
-	  Negate = 1;
-	  Name += 2;
-	}
-      /* Find the token delimiter.  */
-      cp = Name;
-      while (*cp && (*cp != '_') && (*cp != '$'))
-	cp++;
-      /* Look for the token in the attribute list.  */
-      for (i = 0; Attributes[i].Name; i++)
-	{
-	  /* If the strings match, set/clear the attr.  */
-	  if (strncmp (Name, Attributes[i].Name, cp - Name) == 0)
-	    {
-	      /* Set or clear.  */
-	      if (Negate)
-		*Attribute_Pointer &=
-		  ~Attributes[i].Value;
-	      else
-		*Attribute_Pointer |=
-		  Attributes[i].Value;
-	      /* Done.  */
-	      break;
-	    }
-	}
-      /* Now skip the attribute.  */
-      Name = cp;
-      if (*Name == '_')
-	Name++;
-    }
-}
-
-
-#define GBLSYM_REF 0
-#define GBLSYM_DEF 1
-#define GBLSYM_VAL 2
-#define GBLSYM_LCL 4	/* not GBL after all...  */
-#define GBLSYM_WEAK 8
-
-/* Define a global symbol (or possibly a local one).  */
-
-static void
-VMS_Global_Symbol_Spec (const char *Name, int Psect_Number, int Psect_Offset, int Flags)
-{
-  char Local[32];
-
-  /* We are writing a GSD record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_GSD);
-
-  /* If the buffer is empty we must insert the GSD record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_GSD);
-
-  /* We are writing a Global (or local) symbol definition subrecord.  */
-  PUT_CHAR ((Flags & GBLSYM_LCL) != 0 ? GSD_S_C_LSY :
-	    ((unsigned) Psect_Number <= 255) ? GSD_S_C_SYM : GSD_S_C_SYMW);
-
-  /* Data type is undefined.  */
-  PUT_CHAR (0);
-
-  /* Switch on Definition/Reference.  */
-  if ((Flags & GBLSYM_DEF) == 0)
-    {
-      /* Reference.  */
-      PUT_SHORT (((Flags & GBLSYM_VAL) == 0) ? GSY_S_M_REL : 0);
-      if ((Flags & GBLSYM_LCL) != 0)	/* local symbols have extra field */
-	PUT_SHORT (Current_Environment);
-    }
-  else
-    {
-      int sym_flags;
-
-      /* Definition
-         [ assert (LSY_S_M_DEF == GSY_S_M_DEF && LSY_S_M_REL == GSY_S_M_REL); ].  */
-      sym_flags = GSY_S_M_DEF;
-      if (Flags & GBLSYM_WEAK)
-	sym_flags |= GSY_S_M_WEAK;
-      if ((Flags & GBLSYM_VAL) == 0)
-	sym_flags |= GSY_S_M_REL;
-      PUT_SHORT (sym_flags);
-      if ((Flags & GBLSYM_LCL) != 0)	/* local symbols have extra field */
-	PUT_SHORT (Current_Environment);
-
-      /* Psect Number.  */
-      if ((Flags & GBLSYM_LCL) == 0 && (unsigned) Psect_Number <= 255)
-	PUT_CHAR (Psect_Number);
-      else
-	PUT_SHORT (Psect_Number);
-
-      /* Offset.  */
-      PUT_LONG (Psect_Offset);
-    }
-
-  /* Finally, the global symbol name.  */
-  VMS_Case_Hack_Symbol (Name, Local);
-  PUT_COUNTED_STRING (Local);
-
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-/* Define an environment to support local symbol references.
-   This is just to mollify the linker; we don't actually do
-   anything useful with it.  */
-
-static void
-VMS_Local_Environment_Setup (const char *Env_Name)
-{
-  /* We are writing a GSD record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_GSD);
-  /* If the buffer is empty we must insert the GSD record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_GSD);
-  /* We are writing an ENV subrecord.  */
-  PUT_CHAR (GSD_S_C_ENV);
-
-  ++Current_Environment;	/* index of environment being defined */
-
-  /* ENV$W_FLAGS:  we are defining the next environment.  It's not nested.  */
-  PUT_SHORT (ENV_S_M_DEF);
-  /* ENV$W_ENVINDX:  index is always 0 for non-nested definitions.  */
-  PUT_SHORT (0);
-
-  /* ENV$B_NAMLNG + ENV$T_NAME:  environment name in ASCIC format.  */
-  if (!Env_Name) Env_Name = "";
-  PUT_COUNTED_STRING ((char *)Env_Name);
-
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Define a psect.  */
-
-static int
-VMS_Psect_Spec (const char *Name, int Size, enum ps_type Type, struct VMS_Symbol *vsp)
-{
-  char Local[32];
-  int Psect_Attributes;
-
-  /* Generate the appropriate PSECT flags given the PSECT type.  */
-  switch (Type)
-    {
-    case ps_TEXT:
-      /* Text psects are PIC,noOVR,REL,noGBL,SHR,EXE,RD,noWRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_REL|GPS_S_M_SHR|GPS_S_M_EXE
-			  |GPS_S_M_RD);
-      break;
-    case ps_DATA:
-      /* Data psects are PIC,noOVR,REL,noGBL,noSHR,noEXE,RD,WRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_REL|GPS_S_M_RD|GPS_S_M_WRT);
-      break;
-    case ps_COMMON:
-      /* Common block psects are:  PIC,OVR,REL,GBL,noSHR,noEXE,RD,WRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_OVR|GPS_S_M_REL|GPS_S_M_GBL
-			  |GPS_S_M_RD|GPS_S_M_WRT);
-      break;
-    case ps_CONST:
-      /* Const data psects are:  PIC,OVR,REL,GBL,noSHR,noEXE,RD,noWRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_OVR|GPS_S_M_REL|GPS_S_M_GBL
-			  |GPS_S_M_RD);
-      break;
-    case ps_CTORS:
-      /* Ctor psects are PIC,noOVR,REL,GBL,noSHR,noEXE,RD,noWRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_REL|GPS_S_M_GBL|GPS_S_M_RD);
-      break;
-    case ps_DTORS:
-      /* Dtor psects are PIC,noOVR,REL,GBL,noSHR,noEXE,RD,noWRT.  */
-      Psect_Attributes = (GPS_S_M_PIC|GPS_S_M_REL|GPS_S_M_GBL|GPS_S_M_RD);
-      break;
-    default:
-      /* impossible */
-      error (_("Unknown VMS psect type (%ld)"), (long) Type);
-      break;
-    }
-  /* Modify the psect attributes according to any attribute string.  */
-  if (vsp && S_GET_TYPE (vsp->Symbol) == N_ABS)
-    Psect_Attributes |= GLOBALVALUE_BIT;
-  else if (HAS_PSECT_ATTRIBUTES (Name))
-    VMS_Modify_Psect_Attributes (Name, &Psect_Attributes);
-  /* Check for globalref/def/val.  */
-  if ((Psect_Attributes & GLOBALVALUE_BIT) != 0)
-    {
-      /* globalvalue symbols were generated before. This code
-         prevents unsightly psect buildup, and makes sure that
-         fixup references are emitted correctly.  */
-      vsp->Psect_Index = -1;	/* to catch errors */
-      S_SET_TYPE (vsp->Symbol, N_UNDF);		/* make refs work */
-      return 1;			/* decrement psect counter */
-    }
-
-  if ((Psect_Attributes & GLOBALSYMBOL_BIT) != 0)
-    {
-      switch (S_GET_RAW_TYPE (vsp->Symbol))
-	{
-	case N_UNDF | N_EXT:
-	  VMS_Global_Symbol_Spec (Name, vsp->Psect_Index,
-				  vsp->Psect_Offset, GBLSYM_REF);
-	  vsp->Psect_Index = -1;
-	  S_SET_TYPE (vsp->Symbol, N_UNDF);
-	  /* Return and indicate no psect.  */
-	  return 1;
-	  
-	case N_DATA | N_EXT:
-	  VMS_Global_Symbol_Spec (Name, vsp->Psect_Index,
-				  vsp->Psect_Offset, GBLSYM_DEF);
-	  /* In this case we still generate the psect. */
-	  break;
-	  
-	default:
-	  as_fatal (_("Globalsymbol attribute for symbol %s was unexpected."),
-		    Name);
-	  break;
-	}
-    }
-
-  /* Clear out the globalref/def stuff.  */
-  Psect_Attributes &= 0xffff;
-  /* We are writing a GSD record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_GSD);
-  /* If the buffer is empty we must insert the GSD record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_GSD);
-  /* We are writing a PSECT definition subrecord.  */
-  PUT_CHAR (GSD_S_C_PSC);
-  /* Psects are always LONGWORD aligned.  */
-  PUT_CHAR (2);
-  /* Specify the psect attributes.  */
-  PUT_SHORT (Psect_Attributes);
-  /* Specify the allocation.  */
-  PUT_LONG (Size);
-  /* Finally, the psect name.  */
-  VMS_Case_Hack_Symbol (Name, Local);
-  PUT_COUNTED_STRING (Local);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-  return 0;
-}
-
-
-/* Given the pointer to a symbol we calculate how big the data at the
-   symbol is.  We do this by looking for the next symbol (local or global)
-   which will indicate the start of another datum.  */
-
-static offsetT
-VMS_Initialized_Data_Size (symbolS *s0P, unsigned End_Of_Data)
-{
-  symbolS *s1P;
-  valueT s0P_val = S_GET_VALUE (s0P), s1P_val,
-	 nearest_val = (valueT) End_Of_Data;
-
-  /* Find the nearest symbol what follows this one.  */
-  for (s1P = symbol_rootP; s1P; s1P = symbol_next (s1P))
-    {
-      /* The data type must match.  */
-      if (S_GET_TYPE (s1P) != N_DATA)
-	continue;
-      s1P_val = S_GET_VALUE (s1P);
-      if (s1P_val > s0P_val && s1P_val < nearest_val)
-	nearest_val = s1P_val;
-    }
-  /* Calculate its size.  */
-  return (offsetT) (nearest_val - s0P_val);
-}
-
-/* Check symbol names for the Psect hack with a globalvalue, and then
-   generate globalvalues for those that have it.  */
-
-static void
-VMS_Emit_Globalvalues (unsigned text_siz, unsigned data_siz,
-		       char *Data_Segment)
-{
-  symbolS *sp;
-  char *stripped_name, *Name;
-  int Size;
-  int Psect_Attributes;
-  int globalvalue;
-  int typ, abstyp;
-
-  /* Scan the symbol table for globalvalues, and emit def/ref when
-     required.  These will be caught again later and converted to
-     N_UNDF.  */
-  for (sp = symbol_rootP; sp; sp = sp->sy_next)
-    {
-      typ = S_GET_RAW_TYPE (sp);
-      abstyp = ((typ & ~N_EXT) == N_ABS);
-      /* See if this is something we want to look at.  */
-      if (!abstyp &&
-	  typ != (N_DATA | N_EXT) &&
-	  typ != (N_UNDF | N_EXT))
-	continue;
-      /* See if this has globalvalue specification.  */
-      Name = S_GET_NAME (sp);
-
-      if (abstyp)
-	{
-	  stripped_name = 0;
-	  Psect_Attributes = GLOBALVALUE_BIT;
-	}
-      else if (HAS_PSECT_ATTRIBUTES (Name))
-	{
-	  stripped_name = xmalloc (strlen (Name) + 1);
-	  strcpy (stripped_name, Name);
-	  Psect_Attributes = 0;
-	  VMS_Modify_Psect_Attributes (stripped_name, &Psect_Attributes);
-	}
-      else
-	continue;
-
-      if ((Psect_Attributes & GLOBALVALUE_BIT) != 0)
-	{
-	  switch (typ)
-	    {
-	    case N_ABS:
-	      /* Local symbol references will want
-		 to have an environment defined.  */
-	      if (Current_Environment < 0)
-		VMS_Local_Environment_Setup (".N_ABS");
-	      VMS_Global_Symbol_Spec (Name, 0,
-				      S_GET_VALUE (sp),
-				      GBLSYM_DEF|GBLSYM_VAL|GBLSYM_LCL);
-	      break;
-	    case N_ABS | N_EXT:
-	      VMS_Global_Symbol_Spec (Name, 0,
-				      S_GET_VALUE (sp),
-				      GBLSYM_DEF|GBLSYM_VAL);
-	      break;
-	    case N_UNDF | N_EXT:
-	      VMS_Global_Symbol_Spec (stripped_name, 0, 0, GBLSYM_VAL);
-	      break;
-	    case N_DATA | N_EXT:
-	      Size = VMS_Initialized_Data_Size (sp, text_siz + data_siz);
-	      if (Size > 4)
-		error (_("Invalid data type for globalvalue"));
-	      globalvalue = md_chars_to_number (Data_Segment +
-		     S_GET_VALUE (sp) - text_siz , Size);
-	      /* Three times for good luck.  The linker seems to get confused
-	         if there are fewer than three */
-	      VMS_Global_Symbol_Spec (stripped_name, 0, 0, GBLSYM_VAL);
-	      VMS_Global_Symbol_Spec (stripped_name, 0, globalvalue,
-				      GBLSYM_DEF|GBLSYM_VAL);
-	      VMS_Global_Symbol_Spec (stripped_name, 0, globalvalue,
-				      GBLSYM_DEF|GBLSYM_VAL);
-	      break;
-	    default:
-	      as_warn (_("Invalid globalvalue of %s"), stripped_name);
-	      break;
-	    }
-	}
-
-      if (stripped_name)
-	free (stripped_name);
-    }
-
-}
-
-
-/* Define a procedure entry pt/mask.  */
-
-static void
-VMS_Procedure_Entry_Pt (char *Name, int Psect_Number, int Psect_Offset,
-			int Entry_Mask)
-{
-  char Local[32];
-
-  /* We are writing a GSD record.  */
-  Set_VMS_Object_File_Record (OBJ_S_C_GSD);
-  /* If the buffer is empty we must insert the GSD record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (OBJ_S_C_GSD);
-  /* We are writing a Procedure Entry Pt/Mask subrecord.  */
-  PUT_CHAR (((unsigned) Psect_Number <= 255) ? GSD_S_C_EPM : GSD_S_C_EPMW);
-  /* Data type is undefined.  */
-  PUT_CHAR (0);
-  /* Flags = "RELOCATABLE" and "DEFINED".  */
-  PUT_SHORT (GSY_S_M_DEF | GSY_S_M_REL);
-  /* Psect Number.  */
-  if ((unsigned) Psect_Number <= 255)
-    PUT_CHAR (Psect_Number);
-  else
-    PUT_SHORT (Psect_Number);
-  /* Offset.  */
-  PUT_LONG (Psect_Offset);
-  /* Entry mask.  */
-  PUT_SHORT (Entry_Mask);
-  /* Finally, the global symbol name.  */
-  VMS_Case_Hack_Symbol (Name, Local);
-  PUT_COUNTED_STRING (Local);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Set the current location counter to a particular Psect and Offset.  */
-
-static void
-VMS_Set_Psect (int Psect_Index, int Offset, int Record_Type)
-{
-  /* We are writing a "Record_Type" record.  */
-  Set_VMS_Object_File_Record (Record_Type);
-  /* If the buffer is empty we must insert the record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (Record_Type);
-  /* Stack the Psect base + Offset.  */
-  vms_tir_stack_psect (Psect_Index, Offset, 0);
-  /* Set relocation base.  */
-  PUT_CHAR (TIR_S_C_CTL_SETRB);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Store repeated immediate data in current Psect.  */
-
-static void
-VMS_Store_Repeated_Data (int Repeat_Count, char *Pointer, int Size,
-			 int Record_Type)
-{
-  /* Ignore zero bytes/words/longwords.  */
-  switch (Size)
-    {
-    case 4:
-      if (Pointer[3] != 0 || Pointer[2] != 0) break;
-      /* else FALLTHRU */
-    case 2:
-      if (Pointer[1] != 0) break;
-      /* else FALLTHRU */
-    case 1:
-      if (Pointer[0] != 0) break;
-      /* zero value */
-      return;
-    default:
-      break;
-    }
-  /* If the data is too big for a TIR_S_C_STO_RIVB sub-record
-     then we do it manually.  */
-  if (Size > 255)
-    {
-      while (--Repeat_Count >= 0)
-	VMS_Store_Immediate_Data (Pointer, Size, Record_Type);
-      return;
-    }
-  /* We are writing a "Record_Type" record.  */
-  Set_VMS_Object_File_Record (Record_Type);
-  /* If the buffer is empty we must insert record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (Record_Type);
-  /* Stack the repeat count.  */
-  PUT_CHAR (TIR_S_C_STA_LW);
-  PUT_LONG (Repeat_Count);
-  /* And now the command and its data.  */
-  PUT_CHAR (TIR_S_C_STO_RIVB);
-  PUT_CHAR (Size);
-  while (--Size >= 0)
-    PUT_CHAR (*Pointer++);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Store a Position Independent Reference.  */
-
-static void
-VMS_Store_PIC_Symbol_Reference (symbolS *Symbol, int Offset, int PC_Relative,
-				int Psect, int Psect_Offset, int Record_Type)
-{
-  struct VMS_Symbol *vsp = Symbol->sy_obj;
-  char Local[32];
-  int local_sym = 0;
-
-  /* We are writing a "Record_Type" record.  */
-  Set_VMS_Object_File_Record (Record_Type);
-  /* If the buffer is empty we must insert record type.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (Record_Type);
-  /* Set to the appropriate offset in the Psect.
-     For a Code reference we need to fix the operand
-     specifier as well, so back up 1 byte;
-     for a Data reference we just store HERE.  */
-  VMS_Set_Psect (Psect,
-		 PC_Relative ? Psect_Offset - 1 : Psect_Offset,
-		 Record_Type);
-  /* Make sure we are still generating a "Record Type" record.  */
-  if (Object_Record_Offset == 0)
-    PUT_CHAR (Record_Type);
-  /* Dispatch on symbol type (so we can stack its value).  */
-  switch (S_GET_RAW_TYPE (Symbol))
-    {
-      /* Global symbol.  */
-    case N_ABS:
-      local_sym = 1;
-      /*FALLTHRU*/
-    case N_ABS | N_EXT:
-#ifdef	NOT_VAX_11_C_COMPATIBLE
-    case N_UNDF | N_EXT:
-    case N_DATA | N_EXT:
-#endif	/* NOT_VAX_11_C_COMPATIBLE */
-    case N_UNDF:
-    case N_TEXT | N_EXT:
-      /* Get the symbol name (case hacked).  */
-      VMS_Case_Hack_Symbol (S_GET_NAME (Symbol), Local);
-      /* Stack the global symbol value.  */
-      if (!local_sym)
-	{
-	  PUT_CHAR (TIR_S_C_STA_GBL);
-	}
-      else
-	{
-	  /* Local symbols have an extra field.  */
-	  PUT_CHAR (TIR_S_C_STA_LSY);
-	  PUT_SHORT (Current_Environment);
-	}
-      PUT_COUNTED_STRING (Local);
-      if (Offset)
-	{
-	  /* Stack the longword offset.  */
-	  PUT_CHAR (TIR_S_C_STA_LW);
-	  PUT_LONG (Offset);
-	  /* Add the two, leaving the result on the stack.  */
-	  PUT_CHAR (TIR_S_C_OPR_ADD);
-	}
-      break;
-      /* Uninitialized local data.  */
-    case N_BSS:
-      /* Stack the Psect (+offset).  */
-      vms_tir_stack_psect (vsp->Psect_Index,
-			   vsp->Psect_Offset + Offset,
-			   0);
-      break;
-      /* Local text.  */
-    case N_TEXT:
-      /* Stack the Psect (+offset).  */
-      vms_tir_stack_psect (vsp->Psect_Index,
-			   S_GET_VALUE (Symbol) + Offset,
-			   0);
-      break;
-      /* Initialized local or global data.  */
-    case N_DATA:
-#ifndef	NOT_VAX_11_C_COMPATIBLE
-    case N_UNDF | N_EXT:
-    case N_DATA | N_EXT:
-#endif	/* NOT_VAX_11_C_COMPATIBLE */
-      /* Stack the Psect (+offset).  */
-      vms_tir_stack_psect (vsp->Psect_Index,
-			   vsp->Psect_Offset + Offset,
-			   0);
-      break;
-    }
-  /* Store either a code or data reference.  */
-  PUT_CHAR (PC_Relative ? TIR_S_C_STO_PICR : TIR_S_C_STO_PIDR);
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Check in the text area for an indirect pc-relative reference
-   and fix it up with addressing mode 0xff [PC indirect]
-
-   THIS SHOULD BE REPLACED BY THE USE OF TIR_S_C_STO_PIRR IN THE
-   PIC CODE GENERATING FIXUP ROUTINE.  */
-
-static void
-VMS_Fix_Indirect_Reference (int Text_Psect, addressT Offset,
-			    fragS *fragP, fragS *text_frag_root)
-{
-  /* The addressing mode byte is 1 byte before the address.  */
-  Offset--;
-  /* Is it in THIS frag?  */
-  if ((Offset < fragP->fr_address) ||
-      (Offset >= (fragP->fr_address + fragP->fr_fix)))
-    {
-      /* We need to search for the fragment containing this
-         Offset.  */
-      for (fragP = text_frag_root; fragP; fragP = fragP->fr_next)
-	{
-	  if ((Offset >= fragP->fr_address) &&
-	      (Offset < (fragP->fr_address + fragP->fr_fix)))
-	    break;
-	}
-      /* If we couldn't find the frag, things are BAD!  */
-      if (fragP == 0)
-	error (_("Couldn't find fixup fragment when checking for indirect reference"));
-    }
-  /* Check for indirect PC relative addressing mode.  */
-  if (fragP->fr_literal[Offset - fragP->fr_address] == (char) 0xff)
-    {
-      static char Address_Mode = (char) 0xff;
-
-      /* Yes: Store the indirect mode back into the image
-         to fix up the damage done by STO_PICR.  */
-      VMS_Set_Psect (Text_Psect, Offset, OBJ_S_C_TIR);
-      VMS_Store_Immediate_Data (&Address_Mode, 1, OBJ_S_C_TIR);
-    }
-}
-
-
-/* If the procedure "main()" exists we have to add the instruction
-   "jsb c$main_args" at the beginning to be compatible with VAX-11 "C".
-
-   FIXME:  the macro name `HACK_DEC_C_STARTUP' should be renamed
-	   to `HACK_VAXCRTL_STARTUP' because Digital's compiler
- 	   named "DEC C" uses run-time library "DECC$SHR", but this
- 	   startup code is for "VAXCRTL", the library for Digital's
- 	   older "VAX C".  Also, this extra code isn't needed for
- 	   supporting gcc because it already generates the VAXCRTL
- 	   startup call when compiling main().  The reference to
- 	   `flag_hash_long_names' looks very suspicious too;
- 	   probably an old-style command line option was inadvertently
- 	   overloaded here, then blindly converted into the new one.  */
-void
-vms_check_for_main (void)
-{
-  symbolS *symbolP;
-#ifdef	HACK_DEC_C_STARTUP	/* JF */
-  struct frchain *frchainP;
-  fragS *fragP;
-  fragS **prev_fragPP;
-  struct fix *fixP;
-  fragS *New_Frag;
-  int i;
-#endif	/* HACK_DEC_C_STARTUP */
-
-  symbolP = (symbolS *) symbol_find ("_main");
-  if (symbolP && !S_IS_DEBUG (symbolP) &&
-      S_IS_EXTERNAL (symbolP) && (S_GET_TYPE (symbolP) == N_TEXT))
-    {
-#ifdef	HACK_DEC_C_STARTUP
-      if (!flag_hash_long_names)
-	{
-#endif
-	  /* Remember the entry point symbol.  */
-	  Entry_Point_Symbol = symbolP;
-#ifdef HACK_DEC_C_STARTUP
-	}
-      else
-	{
-	  /* Scan all the fragment chains for the one with "_main"
-	     (Actually we know the fragment from the symbol, but we need
-	     the previous fragment so we can change its pointer).  */
-	  frchainP = frchain_root;
-	  while (frchainP)
-	    {
-	      /* Scan all the fragments in this chain, remembering
-	         the "previous fragment".  */
-	      prev_fragPP = &frchainP->frch_root;
-	      fragP = frchainP->frch_root;
-	      while (fragP && (fragP != frchainP->frch_last))
-		{
-		  /* Is this the fragment ?  */
-		  if (fragP == symbolP->sy_frag)
-		    {
-		      /* Yes: Modify the fragment by replacing
-		         it with a new fragment.  */
-		      New_Frag =
-			xmalloc (sizeof (*New_Frag) +
-				 fragP->fr_fix +
-				 fragP->fr_var +
-				 5);
-		      /* The fragments are the same except
-		        	that the "fixed" area is larger.  */
-		      *New_Frag = *fragP;
-		      New_Frag->fr_fix += 6;
-		      /* Copy the literal data opening a hole
-		         2 bytes after "_main" (i.e. just after
-		         the entry mask).  Into which we place
-		         the JSB instruction.  */
-		      New_Frag->fr_literal[0] = fragP->fr_literal[0];
-		      New_Frag->fr_literal[1] = fragP->fr_literal[1];
-		      New_Frag->fr_literal[2] = 0x16;	/* Jsb */
-		      New_Frag->fr_literal[3] = 0xef;
-		      New_Frag->fr_literal[4] = 0;
-		      New_Frag->fr_literal[5] = 0;
-		      New_Frag->fr_literal[6] = 0;
-		      New_Frag->fr_literal[7] = 0;
-		      for (i = 2; i < fragP->fr_fix + fragP->fr_var; i++)
-			New_Frag->fr_literal[i + 6] =
-			  fragP->fr_literal[i];
-		      /* Now replace the old fragment with the
-		         newly generated one.  */
-		      *prev_fragPP = New_Frag;
-		      /* Remember the entry point symbol.  */
-		      Entry_Point_Symbol = symbolP;
-		      /* Scan the text area fixup structures
-		         as offsets in the fragment may have changed.  */
-		      for (fixP = text_fix_root; fixP; fixP = fixP->fx_next)
-			{
-			  /* Look for references to this fragment.  */
-			  if (fixP->fx_frag == fragP)
-			    {
-			      /* Change the fragment pointer.  */
-			      fixP->fx_frag = New_Frag;
-			      /* If the offset is after	the entry mask we need
-			         to account for the JSB	instruction we just
-			         inserted.  */
-			      if (fixP->fx_where >= 2)
-				fixP->fx_where += 6;
-			    }
-			}
-		      /* Scan the symbols as offsets in the
-		        fragment may have changed.  */
-		      for (symbolP = symbol_rootP;
-			   symbolP;
-			   symbolP = symbol_next (symbolP))
-			{
-			  /* Look for references to this fragment.  */
-			  if (symbolP->sy_frag == fragP)
-			    {
-			      /* Change the fragment pointer.  */
-			      symbolP->sy_frag = New_Frag;
-			      /* If the offset is after	the entry mask we need
-			         to account for the JSB	instruction we just
-			         inserted.  */
-			      if (S_GET_VALUE (symbolP) >= 2)
-				S_SET_VALUE (symbolP,
-					     S_GET_VALUE (symbolP) + 6);
-			    }
-			}
-		      /*  Make a symbol reference to "_c$main_args" so we
-			  can get its address inserted into the	JSB
-			  instruction.  */
-		      symbolP = xmalloc (sizeof (*symbolP));
-		      S_SET_NAME (symbolP, "_C$MAIN_ARGS");
-		      S_SET_TYPE (symbolP, N_UNDF);
-		      S_SET_OTHER (symbolP, 0);
-		      S_SET_DESC (symbolP, 0);
-		      S_SET_VALUE (symbolP, 0);
-		      symbolP->sy_name_offset = 0;
-		      symbolP->sy_number = 0;
-		      symbolP->sy_obj = 0;
-		      symbolP->sy_frag = New_Frag;
-		      symbolP->sy_resolved = 0;
-		      symbolP->sy_resolving = 0;
-		      /* This actually inserts at the beginning of the list.  */
-		      symbol_append (symbol_rootP, symbolP,
-				     &symbol_rootP, &symbol_lastP);
-
-		      symbol_rootP = symbolP;
-		      /* Generate a text fixup structure
-		         to get "_c$main_args" stored into the
-		         JSB instruction.  */
-		      fixP = xmalloc (sizeof (*fixP));
-		      fixP->fx_frag = New_Frag;
-		      fixP->fx_where = 4;
-		      fixP->fx_addsy = symbolP;
-		      fixP->fx_subsy = 0;
-		      fixP->fx_offset = 0;
-		      fixP->fx_size = 4;
-		      fixP->fx_pcrel = 1;
-		      fixP->fx_next = text_fix_root;
-		      text_fix_root = fixP;
-		      /* Now make sure we exit from the loop.  */
-		      frchainP = 0;
-		      break;
-		    }
-		  /* Try the next fragment.  */
-		  prev_fragPP = &fragP->fr_next;
-		  fragP = fragP->fr_next;
-		}
-	      /* Try the next fragment chain.  */
-	      if (frchainP)
-		frchainP = frchainP->frch_next;
-	    }
-	}
-#endif /* HACK_DEC_C_STARTUP */
-    }
-}
-
-
-/* Beginning of vms_write_object_file().  */
-
-static
-struct vms_obj_state
-{
-  /* Next program section index to use.  */
-  int	psect_number;
-
-  /* Psect index for code.  Always ends up #0.  */
-  int	text_psect;
-
-  /* Psect index for initialized static variables.  */
-  int	data_psect;
-
-  /* Psect index for uninitialized static variables.  */
-  int	bss_psect;
-
-  /* Psect index for static constructors.  */
-  int	ctors_psect;
-
-  /* Psect index for static destructors.  */
-  int	dtors_psect;
-
-  /* Number of bytes used for local symbol data.  */
-  int	local_initd_data_size;
-
-  /* Dynamic buffer for initialized data.  */
-  char *data_segment;
-
-} vms_obj_state;
-
-#define Psect_Number		vms_obj_state.psect_number
-#define Text_Psect		vms_obj_state.text_psect
-#define Data_Psect		vms_obj_state.data_psect
-#define Bss_Psect		vms_obj_state.bss_psect
-#define Ctors_Psect		vms_obj_state.ctors_psect
-#define Dtors_Psect		vms_obj_state.dtors_psect
-#define Local_Initd_Data_Size	vms_obj_state.local_initd_data_size
-#define Data_Segment		vms_obj_state.data_segment
-
-#define IS_GXX_VTABLE(symP) (strncmp (S_GET_NAME (symP), "__vt.", 5) == 0)
-#define IS_GXX_XTOR(symP) (strncmp (S_GET_NAME (symP), "__GLOBAL_.", 10) == 0)
-#define XTOR_SIZE 4
-
-
-/* Perform text segment fixups.  */
-
-static void
-vms_fixup_text_section (unsigned text_siz ATTRIBUTE_UNUSED,
-			struct frag *text_frag_root,
-			struct frag *data_frag_root)
-{
-  fragS *fragP;
-  struct fix *fixP;
-  offsetT dif;
-
-  /* Scan the text fragments.  */
-  for (fragP = text_frag_root; fragP; fragP = fragP->fr_next)
-    {
-      /* Stop if we get to the data fragments.  */
-      if (fragP == data_frag_root)
-	break;
-      /* Ignore fragments with no data.  */
-      if ((fragP->fr_fix == 0) && (fragP->fr_var == 0))
-	continue;
-      /* Go to the appropriate offset in the Text Psect.  */
-      VMS_Set_Psect (Text_Psect, fragP->fr_address, OBJ_S_C_TIR);
-      /* Store the "fixed" part.  */
-      if (fragP->fr_fix)
-	VMS_Store_Immediate_Data (fragP->fr_literal,
-				  fragP->fr_fix,
-				  OBJ_S_C_TIR);
-      /* Store the "variable" part.  */
-      if (fragP->fr_var && fragP->fr_offset)
-	VMS_Store_Repeated_Data (fragP->fr_offset,
-				 fragP->fr_literal + fragP->fr_fix,
-				 fragP->fr_var,
-				 OBJ_S_C_TIR);
-    }
-
-  /* Now we go through the text segment fixups and generate
-     TIR records to fix up addresses within the Text Psect.  */
-  for (fixP = text_fix_root; fixP; fixP = fixP->fx_next)
-    {
-      /* We DO handle the case of "Symbol - Symbol" as
-	 long as it is in the same segment.  */
-      if (fixP->fx_subsy && fixP->fx_addsy)
-	{
-	  /* They need to be in the same segment.  */
-	  if (S_GET_RAW_TYPE (fixP->fx_subsy) !=
-	      S_GET_RAW_TYPE (fixP->fx_addsy))
-	    error (_("Fixup data addsy and subsy don't have the same type"));
-	  /* And they need to be in one that we can check the psect on.  */
-	  if ((S_GET_TYPE (fixP->fx_addsy) != N_DATA) &&
-		    (S_GET_TYPE (fixP->fx_addsy) != N_TEXT))
-	    error (_("Fixup data addsy and subsy don't have an appropriate type"));
-	  /* This had better not be PC relative!  */
-	  if (fixP->fx_pcrel)
-	    error (_("Fixup data is erroneously \"pcrel\""));
-	  /* Subtract their values to get the difference.  */
-	  dif = S_GET_VALUE (fixP->fx_addsy) - S_GET_VALUE (fixP->fx_subsy);
-	  md_number_to_chars (Local, (valueT)dif, fixP->fx_size);
-	  /* Now generate the fixup object records;
-	     set the psect and store the data.  */
-	  VMS_Set_Psect (Text_Psect,
-			 fixP->fx_where + fixP->fx_frag->fr_address,
-			 OBJ_S_C_TIR);
-	  VMS_Store_Immediate_Data (Local,
-				    fixP->fx_size,
-				    OBJ_S_C_TIR);
-	  continue;
-	}
-      /* Size will HAVE to be "long".  */
-      if (fixP->fx_size != 4)
-	error (_("Fixup datum is not a longword"));
-      /* Symbol must be "added" (if it is ever
-	 subtracted we can fix this assumption).  */
-      if (fixP->fx_addsy == 0)
-	error (_("Fixup datum is not \"fixP->fx_addsy\""));
-      /* Store the symbol value in a PIC fashion.  */
-      VMS_Store_PIC_Symbol_Reference (fixP->fx_addsy,
-				      fixP->fx_offset,
-				      fixP->fx_pcrel,
-				      Text_Psect,
-				    fixP->fx_where + fixP->fx_frag->fr_address,
-				      OBJ_S_C_TIR);
-	  /* Check for indirect address reference, which has to be fixed up
-	     (as the linker will screw it up with TIR_S_C_STO_PICR).  */
-      if (fixP->fx_pcrel)
-	VMS_Fix_Indirect_Reference (Text_Psect,
-				    fixP->fx_where + fixP->fx_frag->fr_address,
-				    fixP->fx_frag,
-				    text_frag_root);
-    }
-}
-
-
-/* Create a buffer holding the data segment.  */
-
-static void
-synthesize_data_segment (unsigned data_siz, unsigned text_siz,
-			 struct frag *data_frag_root)
-{
-  fragS *fragP;
-  char *fill_literal;
-  long fill_size, count, i;
-
-  /* Allocate the data segment.  */
-  Data_Segment = xmalloc (data_siz);
-  
-  /* Run through the data fragments, filling in the segment.  */
-  for (fragP = data_frag_root; fragP; fragP = fragP->fr_next)
-    {
-      i = fragP->fr_address - text_siz;
-      if (fragP->fr_fix)
-	memcpy (Data_Segment + i, fragP->fr_literal, fragP->fr_fix);
-      i += fragP->fr_fix;
-
-      if ((fill_size = fragP->fr_var) != 0)
-	{
-	  fill_literal = fragP->fr_literal + fragP->fr_fix;
-	  for (count = fragP->fr_offset; count; count--)
-	    {
-	      memcpy (Data_Segment + i, fill_literal, fill_size);
-	      i += fill_size;
-	    }
-	}
-    }
-}
-
-/* Perform data segment fixups.  */
-
-static void
-vms_fixup_data_section (unsigned int data_siz ATTRIBUTE_UNUSED,
-			unsigned int text_siz)
-{
-  struct VMS_Symbol *vsp;
-  struct fix *fixP;
-  symbolS *sp;
-  addressT fr_address;
-  offsetT dif;
-  valueT val;
-
-  /* Run through all the data symbols and store the data.  */
-  for (vsp = VMS_Symbols; vsp; vsp = vsp->Next)
-    {
-      /* Ignore anything other than data symbols.  */
-      if (S_GET_TYPE (vsp->Symbol) != N_DATA)
-	continue;
-      /* Set the Psect + Offset.  */
-      VMS_Set_Psect (vsp->Psect_Index,
-		       vsp->Psect_Offset,
-		       OBJ_S_C_TIR);
-      /* Store the data.  */
-      val = S_GET_VALUE (vsp->Symbol);
-      VMS_Store_Immediate_Data (Data_Segment + val - text_siz,
-				vsp->Size,
-				OBJ_S_C_TIR);
-    }			/* N_DATA symbol loop */
-
-  /* Now we go through the data segment fixups and generate
-     TIR records to fix up addresses within the Data Psects.  */
-  for (fixP = data_fix_root; fixP; fixP = fixP->fx_next)
-    {
-      /* Find the symbol for the containing datum.  */
-      for (vsp = VMS_Symbols; vsp; vsp = vsp->Next)
-	{
-	  /* Only bother with Data symbols.  */
-	  sp = vsp->Symbol;
-	  if (S_GET_TYPE (sp) != N_DATA)
-	    continue;
-	  /* Ignore symbol if After fixup.  */
-	  val = S_GET_VALUE (sp);
-	  fr_address = fixP->fx_frag->fr_address;
-	  if (val > fixP->fx_where + fr_address)
-	    continue;
-	  /* See if the datum is here.  */
-	  if (val + vsp->Size <= fixP->fx_where + fr_address)
-	    continue;
-	  /* We DO handle the case of "Symbol - Symbol" as
-	     long as it is in the same segment.  */
-	  if (fixP->fx_subsy && fixP->fx_addsy)
-	    {
-	      /* They need to be in the same segment.  */
-	      if (S_GET_RAW_TYPE (fixP->fx_subsy) !=
-		  S_GET_RAW_TYPE (fixP->fx_addsy))
-		error (_("Fixup data addsy and subsy don't have the same type"));
-	      /* And they need to be in one that we can check the psect on.  */
-	      if ((S_GET_TYPE (fixP->fx_addsy) != N_DATA) &&
-		  (S_GET_TYPE (fixP->fx_addsy) != N_TEXT))
-		error (_("Fixup data addsy and subsy don't have an appropriate type"));
-	      /* This had better not be PC relative!  */
-	      if (fixP->fx_pcrel)
-		error (_("Fixup data is erroneously \"pcrel\""));
-	      /* Subtract their values to get the difference.  */
-	      dif = S_GET_VALUE (fixP->fx_addsy) - S_GET_VALUE (fixP->fx_subsy);
-	      md_number_to_chars (Local, (valueT)dif, fixP->fx_size);
-	      /* Now generate the fixup object records;
-	         set the psect and store the data.  */
-	      VMS_Set_Psect (vsp->Psect_Index,
-			     fr_address + fixP->fx_where
-				 - val + vsp->Psect_Offset,
-			     OBJ_S_C_TIR);
-	      VMS_Store_Immediate_Data (Local,
-					fixP->fx_size,
-					OBJ_S_C_TIR);
-		  break;	/* done with this fixup */
-		}
-	  /* Size will HAVE to be "long".  */
-	  if (fixP->fx_size != 4)
-	    error (_("Fixup datum is not a longword"));
-	  /* Symbol must be "added" (if it is ever
-	     subtracted we can fix this assumption).  */
-	  if (fixP->fx_addsy == 0)
-	    error (_("Fixup datum is not \"fixP->fx_addsy\""));
-	  /* Store the symbol value in a PIC fashion.  */
-	  VMS_Store_PIC_Symbol_Reference (fixP->fx_addsy,
-					  fixP->fx_offset,
-					  fixP->fx_pcrel,
-					  vsp->Psect_Index,
-					  fr_address + fixP->fx_where
-					      - val + vsp->Psect_Offset,
-					  OBJ_S_C_TIR);
-	  /* Done with this fixup.  */
-	  break;
-	}
-    }
-}
-
-/* Perform ctors/dtors segment fixups.  */
-
-static void
-vms_fixup_xtors_section (struct VMS_Symbol *symbols,
-			 int sect_no ATTRIBUTE_UNUSED)
-{
-  struct VMS_Symbol *vsp;
-
-  /* Run through all the symbols and store the data.  */
-  for (vsp = symbols; vsp; vsp = vsp->Next)
-    {
-      symbolS *sp;
-
-      /* Set relocation base.  */
-      VMS_Set_Psect (vsp->Psect_Index, vsp->Psect_Offset, OBJ_S_C_TIR);
-
-      sp = vsp->Symbol;
-      /* Stack the Psect base with its offset.  */
-      VMS_Set_Data (Text_Psect, S_GET_VALUE (sp), OBJ_S_C_TIR, 0);
-    }
-  /* Flush the buffer if it is more than 75% full.  */
-  if (Object_Record_Offset > (sizeof (Object_Record_Buffer) * 3 / 4))
-    Flush_VMS_Object_Record_Buffer ();
-}
-
-
-/* Define symbols for the linker.  */
-
-static void
-global_symbol_directory (unsigned text_siz, unsigned data_siz)
-{
-  fragS *fragP;
-  symbolS *sp;
-  struct VMS_Symbol *vsp;
-  int Globalref, define_as_global_symbol;
-
-#if 0
-  /* The g++ compiler does not write out external references to
-     vtables correctly.  Check for this and holler if we see it
-     happening.  If that compiler bug is ever fixed we can remove
-     this.
-
-     (Jun'95: gcc 2.7.0's cc1plus still exhibits this behavior.)
-
-     This was reportedly fixed as of June 2, 1998.   */
-
-  for (sp = symbol_rootP; sp; sp = symbol_next (sp))
-    if (S_GET_RAW_TYPE (sp) == N_UNDF && IS_GXX_VTABLE (sp))
-      {
-	S_SET_TYPE (sp, N_UNDF | N_EXT);
-	S_SET_OTHER (sp, 1);
-	as_warn (_("g++ wrote an extern reference to `%s' as a routine.\nI will fix it, but I hope that it was note really a routine."),
-		 S_GET_NAME (sp));
-      }
-#endif
-
-  /* Now scan the symbols and emit the appropriate GSD records.  */
-  for (sp = symbol_rootP; sp; sp = symbol_next (sp))
-    {
-      define_as_global_symbol = 0;
-      vsp = 0;
-      /* Dispatch on symbol type.  */
-      switch (S_GET_RAW_TYPE (sp))
-	{
-
-	/* Global uninitialized data.  */
-	case N_UNDF | N_EXT:
-	  /* Make a VMS data symbol entry.  */
-	  vsp = xmalloc (sizeof *vsp);
-	  vsp->Symbol = sp;
-	  vsp->Size = S_GET_VALUE (sp);
-	  vsp->Psect_Index = Psect_Number++;
-	  vsp->Psect_Offset = 0;
-	  vsp->Next = VMS_Symbols;
-	  VMS_Symbols = vsp;
-	  sp->sy_obj = vsp;
-	  /* Make the psect for this data.  */
-	  Globalref = VMS_Psect_Spec (S_GET_NAME (sp),
-				      vsp->Size,
-				      S_GET_OTHER (sp) ? ps_CONST : ps_COMMON,
-				      vsp);
-	  if (Globalref)
-	    Psect_Number--;
-#ifdef	NOT_VAX_11_C_COMPATIBLE
-	  define_as_global_symbol = 1;
-#else
-	  /* See if this is an external vtable.  We want to help the
-	     linker find these things in libraries, so we make a symbol
-	     reference.  This is not compatible with VAX-C usage for
-	     variables, but since vtables are only used internally by
-	     g++, we can get away with this hack.  */
-	  define_as_global_symbol = IS_GXX_VTABLE (sp);
-#endif
-	  break;
-
-	/* Local uninitialized data.  */
-	case N_BSS:
-	  /* Make a VMS data symbol entry.  */
-	  vsp = xmalloc (sizeof *vsp);
-	  vsp->Symbol = sp;
-	  vsp->Size = 0;
-	  vsp->Psect_Index = Bss_Psect;
-	  vsp->Psect_Offset = S_GET_VALUE (sp) - bss_address_frag.fr_address;
-	  vsp->Next = VMS_Symbols;
-	  VMS_Symbols = vsp;
-	  sp->sy_obj = vsp;
-	  break;
-
-	/* Global initialized data.  */
-	case N_DATA | N_EXT:
-	  /* Make a VMS data symbol entry.  */
-	  vsp = xmalloc (sizeof *vsp);
-	  vsp->Symbol = sp;
-	  vsp->Size = VMS_Initialized_Data_Size (sp, text_siz + data_siz);
-	  vsp->Psect_Index = Psect_Number++;
-	  vsp->Psect_Offset = 0;
-	  vsp->Next = VMS_Symbols;
-	  VMS_Symbols = vsp;
-	  sp->sy_obj = vsp;
-	  /* Make its psect.  */
-	  Globalref = VMS_Psect_Spec (S_GET_NAME (sp),
-				      vsp->Size,
-				      S_GET_OTHER (sp) ? ps_CONST : ps_COMMON,
-				      vsp);
-	  if (Globalref)
-	    Psect_Number--;
-#ifdef	NOT_VAX_11_C_COMPATIBLE
-	  define_as_global_symbol = 1;
-#else
-	  /* See N_UNDF|N_EXT above for explanation.  */
-	  define_as_global_symbol = IS_GXX_VTABLE (sp);
-#endif
-	  break;
-
-	/* Local initialized data.  */
-	case N_DATA:
-	  {
-	    char *sym_name = S_GET_NAME (sp);
-
-	    /* Always suppress local numeric labels.  */
-	    if (sym_name && strcmp (sym_name, FAKE_LABEL_NAME) == 0)
-	      break;
-
-	    /* Make a VMS data symbol entry.  */
-	    vsp = xmalloc (sizeof *vsp);
-	    vsp->Symbol = sp;
-	    vsp->Size = VMS_Initialized_Data_Size (sp, text_siz + data_siz);
-	    vsp->Psect_Index = Data_Psect;
-	    vsp->Psect_Offset = Local_Initd_Data_Size;
-	    Local_Initd_Data_Size += vsp->Size;
-	    vsp->Next = VMS_Symbols;
-	    VMS_Symbols = vsp;
-	    sp->sy_obj = vsp;
-	  }
-	  break;
-
-	/* Global Text definition.  */
-	case N_TEXT | N_EXT:
-	  {
-
-	    if (IS_GXX_XTOR (sp))
-	      {
-		vsp = xmalloc (sizeof *vsp);
-		vsp->Symbol = sp;
-		vsp->Size = XTOR_SIZE;
-		sp->sy_obj = vsp;
-		switch ((S_GET_NAME (sp))[10])
-		  {
-		    case 'I':
-		      vsp->Psect_Index = Ctors_Psect;
-		      vsp->Psect_Offset = (Ctors_Symbols==0)?0:(Ctors_Symbols->Psect_Offset+XTOR_SIZE);
-		      vsp->Next = Ctors_Symbols;
-		      Ctors_Symbols = vsp;
-		      break;
-		    case 'D':
-		      vsp->Psect_Index = Dtors_Psect;
-		      vsp->Psect_Offset = (Dtors_Symbols==0)?0:(Dtors_Symbols->Psect_Offset+XTOR_SIZE);
-		      vsp->Next = Dtors_Symbols;
-		      Dtors_Symbols = vsp;
-		      break;
-		    case 'G':
-		      as_warn (_("Can't handle global xtors symbols yet."));
-		      break;
-		    default:
-		      as_warn (_("Unknown %s"), S_GET_NAME (sp));
-		      break;
-		  }
-	      }
-	    else
-	      {
-		unsigned short Entry_Mask;
-
-		/* Get the entry mask.  */
-		fragP = sp->sy_frag;
-		/* First frag might be empty if we're generating listings.
-		   So skip empty rs_fill frags.  */
-		while (fragP && fragP->fr_type == rs_fill && fragP->fr_fix == 0)
-		  fragP = fragP->fr_next;
-
-		/* If first frag doesn't contain the data, what do we do?
-		   If it's possibly smaller than two bytes, that would
-		   imply that the entry mask is not stored where we're
-		   expecting it.
-
-		   If you can find a test case that triggers this, report
-		   it (and tell me what the entry mask field ought to be),
-		   and I'll try to fix it.  KR */
-		if (fragP->fr_fix < 2)
-		  abort ();
-
-		Entry_Mask = (fragP->fr_literal[0] & 0x00ff) |
-			     ((fragP->fr_literal[1] & 0x00ff) << 8);
-		/* Define the procedure entry point.  */
-		VMS_Procedure_Entry_Pt (S_GET_NAME (sp),
-				    Text_Psect,
-				    S_GET_VALUE (sp),
-				    Entry_Mask);
-	      }
-	    break;
-	  }
-
-	/* Local Text definition.  */
-	case N_TEXT:
-	  /* Make a VMS data symbol entry.  */
-	  if (Text_Psect != -1)
-	    {
-	      vsp = xmalloc (sizeof *vsp);
-	      vsp->Symbol = sp;
-	      vsp->Size = 0;
-	      vsp->Psect_Index = Text_Psect;
-	      vsp->Psect_Offset = S_GET_VALUE (sp);
-	      vsp->Next = VMS_Symbols;
-	      VMS_Symbols = vsp;
-	      sp->sy_obj = vsp;
-	    }
-	  break;
-
-	/* Global Reference.  */
-	case N_UNDF:
-	  /* Make a GSD global symbol reference record.  */
-	  VMS_Global_Symbol_Spec (S_GET_NAME (sp),
-				  0,
-				  0,
-				  GBLSYM_REF);
-	  break;
-
-	/* Absolute symbol.  */
-	case N_ABS:
-	case N_ABS | N_EXT:
-	  /* gcc doesn't generate these;
-	     VMS_Emit_Globalvalue handles them though.	*/
-	  vsp = xmalloc (sizeof *vsp);
-	  vsp->Symbol = sp;
-	  vsp->Size = 4;		/* always assume 32 bits */
-	  vsp->Psect_Index = 0;
-	  vsp->Psect_Offset = S_GET_VALUE (sp);
-	  vsp->Next = VMS_Symbols;
-	  VMS_Symbols = vsp;
-	  sp->sy_obj = vsp;
-	  break;
-
-	/* Anything else.  */
-	default:
-	  /* Ignore STAB symbols, including .stabs emitted by g++.  */
-	  if (S_IS_DEBUG (sp) || (S_GET_TYPE (sp) == 22))
-	    break;
-	  /*
-	   *	Error otherwise.
-	   */
-	  as_tsktsk (_("unhandled stab type %d"), S_GET_TYPE (sp));
-	  break;
-	}
-
-      /* Global symbols have different linkage than external variables.  */
-      if (define_as_global_symbol)
-	VMS_Global_Symbol_Spec (S_GET_NAME (sp),
-				vsp->Psect_Index,
-				0,
-				GBLSYM_DEF);
-    }
-}
-
-
-/* Output debugger symbol table information for symbols which
-   are local to a specific routine.  */
-
-static void
-local_symbols_DST (symbolS *s0P, symbolS *Current_Routine)
-{
-  symbolS *s1P;
-  char *s0P_name, *pnt0, *pnt1;
-
-  s0P_name = S_GET_NAME (s0P);
-  if (*s0P_name++ != '_')
-    return;
-
-  for (s1P = Current_Routine; s1P; s1P = symbol_next (s1P))
-    {
-#if 0		/* redundant; RAW_TYPE != N_FUN suffices */
-      if (!S_IS_DEBUG (s1P))
-	continue;
-#endif
-      if (S_GET_RAW_TYPE (s1P) != N_FUN)
-	continue;
-      pnt0 = s0P_name;
-      pnt1 = S_GET_NAME (s1P);
-      /* We assume the two strings are never exactly equal...  */
-      while (*pnt0++ == *pnt1++)
-	{
-	}
-      /* Found it if s0P name is exhausted and s1P name has ":F" or ":f" next.
-	 Note:  both pointers have advanced one past the non-matching char.  */
-      if ((*pnt1 == 'F' || *pnt1 == 'f') && *--pnt1 == ':' && *--pnt0 == '\0')
-	{
-	  Define_Routine (s1P, 0, Current_Routine, Text_Psect);
-	  return;
-	}
-    }
-}
-
-/* Construct and output the debug symbol table.  */
-
-static void
-vms_build_DST (unsigned text_siz)
-{
-  symbolS *symbolP;
-  symbolS *Current_Routine = 0;
-  struct input_file *Cur_File = 0;
-  offsetT Cur_Offset = -1;
-  int Cur_Line_Number = 0;
-  int File_Number = 0;
-  int Debugger_Offset = 0;
-  int file_available;
-  int dsc;
-  offsetT val;
-
-  /* Write the Traceback Begin Module record.  */
-  VMS_TBT_Module_Begin ();
-
-  /* Output debugging info for global variables and static variables
-     that are not specific to one routine.  We also need to examine
-     all stabs directives, to find the definitions to all of the
-     advanced data types, and this is done by VMS_LSYM_Parse.  This
-     needs to be done before any definitions are output to the object
-     file, since there can be forward references in the stabs
-     directives.  When through with parsing, the text of the stabs
-     directive is altered, with the definitions removed, so that later
-     passes will see directives as they would be written if the type
-     were already defined.
-
-     We also look for files and include files, and make a list of
-     them.  We examine the source file numbers to establish the actual
-     lines that code was generated from, and then generate offsets.  */
-  VMS_LSYM_Parse ();
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Only deal with STAB symbols here.  */
-      if (!S_IS_DEBUG (symbolP))
-	continue;
-      /* Dispatch on STAB type.  */
-      switch (S_GET_RAW_TYPE (symbolP))
-	{
-	case N_SLINE:
-	  dsc = S_GET_DESC (symbolP);
-	  if (dsc > Cur_File->max_line)
-	    Cur_File->max_line = dsc;
-	  if (dsc < Cur_File->min_line)
-	    Cur_File->min_line = dsc;
-	  break;
-	case N_SO:
-	  Cur_File = find_file (symbolP);
-	  Cur_File->flag = 1;
-	  Cur_File->min_line = 1;
-	  break;
-	case N_SOL:
-	  Cur_File = find_file (symbolP);
-	  break;
-	case N_GSYM:
-	  VMS_GSYM_Parse (symbolP, Text_Psect);
-	  break;
-	case N_LCSYM:
-	  VMS_LCSYM_Parse (symbolP, Text_Psect);
-	  break;
-	case N_FUN:		/* For static constant symbols */
-	case N_STSYM:
-	  VMS_STSYM_Parse (symbolP, Text_Psect);
-	  break;
-	default:
-	  break;
-	}
-    }
-
-  /* Now we take a quick sweep through the files and assign offsets
-     to each one.  This will essentially be the starting line number to
-     the debugger for each file.  Output the info for the debugger to
-     specify the files, and then tell it how many lines to use.  */
-  for (Cur_File = file_root; Cur_File; Cur_File = Cur_File->next)
-    {
-      if (Cur_File->max_line == 0)
-	continue;
-      if ((strncmp (Cur_File->name, "GNU_GXX_INCLUDE:", 16) == 0) &&
-	  !flag_debug)
-	continue;
-      if ((strncmp (Cur_File->name, "GNU_CC_INCLUDE:", 15) == 0) &&
-	  !flag_debug)
-	continue;
-      /* show a few extra lines at the start of the region selected */
-      if (Cur_File->min_line > 2)
-	Cur_File->min_line -= 2;
-      Cur_File->offset = Debugger_Offset - Cur_File->min_line + 1;
-      Debugger_Offset += Cur_File->max_line - Cur_File->min_line + 1;
-      if (Cur_File->same_file_fpnt)
-	{
-	  Cur_File->file_number = Cur_File->same_file_fpnt->file_number;
-	}
-      else
-	{
-	  Cur_File->file_number = ++File_Number;
-	  file_available = VMS_TBT_Source_File (Cur_File->name,
-						Cur_File->file_number);
-	  if (!file_available)
-	    {
-	      Cur_File->file_number = 0;
-	      File_Number--;
-	      continue;
-	    }
-	}
-      VMS_TBT_Source_Lines (Cur_File->file_number,
-			    Cur_File->min_line,
-			    Cur_File->max_line - Cur_File->min_line + 1);
-  }			/* for */
-  Cur_File = (struct input_file *) NULL;
-
-  /* Scan the symbols and write out the routines
-     (this makes the assumption that symbols are in
-     order of ascending text segment offset).  */
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-      /* Deal with text symbols.  */
-      if (!S_IS_DEBUG (symbolP) && S_GET_TYPE (symbolP) == N_TEXT)
-	{
-	  /* Ignore symbols starting with "L", as they are local symbols.  */
-	  if (*S_GET_NAME (symbolP) == 'L')
-	    continue;
-	  /* If there is a routine start defined, terminate it.  */
-	  if (Current_Routine)
-	    VMS_TBT_Routine_End (text_siz, Current_Routine);
-
-	  /* Check for & skip dummy labels like "gcc_compiled.".
-	   * They're identified by the IN_DEFAULT_SECTION flag.  */
-	  if ((S_GET_OTHER (symbolP) & IN_DEFAULT_SECTION) != 0 &&
-	      S_GET_VALUE (symbolP) == 0)
-	    continue;
-	  /* Store the routine begin traceback info.  */
-	  VMS_TBT_Routine_Begin (symbolP, Text_Psect);
-	  Current_Routine = symbolP;
-	  /* Define symbols local to this routine.  */
-	  local_symbols_DST (symbolP, Current_Routine);
-	  /* Done.  */
-	  continue;
-
-	}
-      /* Deal with STAB symbols.  */
-      else if (S_IS_DEBUG (symbolP))
-	{
-	  /* Dispatch on STAB type.  */
-	  switch (S_GET_RAW_TYPE (symbolP))
-	    {
-	      /* Line number.  */
-	    case N_SLINE:
-	      /* Offset the line into the correct portion of the file.  */
-	      if (Cur_File->file_number == 0)
-		break;
-	      val = S_GET_VALUE (symbolP);
-	      /* Sometimes the same offset gets several source lines
-		 assigned to it.  We should be selective about which
-		 lines we allow, we should prefer lines that are in
-		 the main source file when debugging inline functions.  */
-	      if (val == Cur_Offset && Cur_File->file_number != 1)
-		break;
-
-	      /* Calculate actual debugger source line.  */
-	      dsc = S_GET_DESC (symbolP) + Cur_File->offset;
-	      S_SET_DESC (symbolP, dsc);
-	      /* Define PC/Line correlation.  */
-	      if (Cur_Offset == -1)
-		{
-		  /* First N_SLINE; set up initial correlation.  */
-		  VMS_TBT_Line_PC_Correlation (dsc,
-					       val,
-					       Text_Psect,
-					       0);
-		}
-	      else if ((dsc - Cur_Line_Number) <= 0)
-		{
-		  /* Line delta is not +ve, we need to close the line and
-		     start a new PC/Line correlation.  */
-		  VMS_TBT_Line_PC_Correlation (0,
-					       val - Cur_Offset,
-					       0,
-					       -1);
-		  VMS_TBT_Line_PC_Correlation (dsc,
-					       val,
-					       Text_Psect,
-					       0);
-		}
-	      else
-		{
-		  /* Line delta is +ve, all is well.  */
-		  VMS_TBT_Line_PC_Correlation (dsc - Cur_Line_Number,
-					       val - Cur_Offset,
-					       0,
-					       1);
-		}
-	      /* Update the current line/PC info.  */
-	      Cur_Line_Number = dsc;
-	      Cur_Offset = val;
-	      break;
-
-		/* Source file.  */
-	    case N_SO:
-	      /* Remember that we had a source file and emit
-		 the source file debugger record.  */
-	      Cur_File = find_file (symbolP);
-	      break;
-
-	    case N_SOL:
-	      /* We need to make sure that we are really in the actual
-		 source file when we compute the maximum line number.
-		 Otherwise the debugger gets really confused.  */
-	      Cur_File = find_file (symbolP);
-	      break;
-
-	    default:
-	      break;
-	    }
-	}
-    }
-
-    /* If there is a routine start defined, terminate it
-       (and the line numbers).  */
-    if (Current_Routine)
-      {
-	/* Terminate the line numbers.  */
-	VMS_TBT_Line_PC_Correlation (0,
-				     text_siz - S_GET_VALUE (Current_Routine),
-				     0,
-				     -1);
-	/* Terminate the routine.  */
-	VMS_TBT_Routine_End (text_siz, Current_Routine);
-      }
-
-  /* Write the Traceback End Module TBT record.  */
-  VMS_TBT_Module_End ();
-}
-
-
-/* Write a VAX/VMS object file (everything else has been done!).  */
-
-void
-vms_write_object_file (unsigned text_siz, unsigned data_siz, unsigned bss_siz,
-		       fragS *text_frag_root, fragS *data_frag_root)
-{
-  struct VMS_Symbol *vsp;
-
-  /* Initialize program section indices; values get updated later.  */
-  Psect_Number = 0;		/* next Psect Index to use */
-  Text_Psect = -1;		/* Text Psect Index   */
-  Data_Psect = -2;		/* Data Psect Index   JF: Was -1 */
-  Bss_Psect = -3;		/* Bss Psect Index    JF: Was -1 */
-  Ctors_Psect = -4;		/* Ctors Psect Index  */
-  Dtors_Psect = -5;		/* Dtors Psect Index  */
-  /* Initialize other state variables.  */
-  Data_Segment = 0;
-  Local_Initd_Data_Size = 0;
-
-  /* Create the actual output file and populate it with required
-     "module header" information.  */
-  Create_VMS_Object_File ();
-  Write_VMS_MHD_Records ();
-
-  /* Create the Data segment:
-
-     Since this is REALLY hard to do any other way,
-     we actually manufacture the data segment and
-     then store the appropriate values out of it.
-     We need to generate this early, so that globalvalues
-     can be properly emitted.  */
-  if (data_siz > 0)
-    synthesize_data_segment (data_siz, text_siz, data_frag_root);
-
-  /* Global Symbol Directory.  */
-
-  /* Emit globalvalues now.  We must do this before the text psect is
-     defined, or we will get linker warnings about multiply defined
-     symbols.  All of the globalvalues "reference" psect 0, although
-     it really does not have anything to do with it.  */
-  VMS_Emit_Globalvalues (text_siz, data_siz, Data_Segment);
-  /* Define the Text Psect.  */
-  Text_Psect = Psect_Number++;
-  VMS_Psect_Spec ("$code", text_siz, ps_TEXT, 0);
-  /* Define the BSS Psect.  */
-  if (bss_siz > 0)
-    {
-      Bss_Psect = Psect_Number++;
-      VMS_Psect_Spec ("$uninitialized_data", bss_siz, ps_DATA, 0);
-    }
-  /* Define symbols to the linker.  */
-  global_symbol_directory (text_siz, data_siz);
-  /* Define the Data Psect.  */
-  if (data_siz > 0 && Local_Initd_Data_Size > 0)
-    {
-      Data_Psect = Psect_Number++;
-      VMS_Psect_Spec ("$data", Local_Initd_Data_Size, ps_DATA, 0);
-      /* Local initialized data (N_DATA) symbols need to be updated to the
-         proper value of Data_Psect now that it's actually been defined.
-         (A dummy value was used in global_symbol_directory() above.)  */
-      for (vsp = VMS_Symbols; vsp; vsp = vsp->Next)
-	if (vsp->Psect_Index < 0 && S_GET_RAW_TYPE (vsp->Symbol) == N_DATA)
-	  vsp->Psect_Index = Data_Psect;
-    }
-
-  if (Ctors_Symbols != 0)
-    {
-      char *ps_name = "$ctors";
-      Ctors_Psect = Psect_Number++;
-      VMS_Psect_Spec (ps_name, Ctors_Symbols->Psect_Offset + XTOR_SIZE,
-		      ps_CTORS, 0);
-      VMS_Global_Symbol_Spec (ps_name, Ctors_Psect,
-				  0, GBLSYM_DEF|GBLSYM_WEAK);
-      for (vsp = Ctors_Symbols; vsp; vsp = vsp->Next)
-	vsp->Psect_Index = Ctors_Psect;
-    }
-
-  if (Dtors_Symbols != 0)
-    {
-      char *ps_name = "$dtors";
-      Dtors_Psect = Psect_Number++;
-      VMS_Psect_Spec (ps_name, Dtors_Symbols->Psect_Offset + XTOR_SIZE,
-		      ps_DTORS, 0);
-      VMS_Global_Symbol_Spec (ps_name, Dtors_Psect,
-				  0, GBLSYM_DEF|GBLSYM_WEAK);
-      for (vsp = Dtors_Symbols; vsp; vsp = vsp->Next)
-	vsp->Psect_Index = Dtors_Psect;
-    }
-
-  /* Text Information and Relocation Records.  */
-
-  /* Write the text segment data.  */
-  if (text_siz > 0)
-    vms_fixup_text_section (text_siz, text_frag_root, data_frag_root);
-  /* Write the data segment data, then discard it.  */
-  if (data_siz > 0)
-    {
-      vms_fixup_data_section (data_siz, text_siz);
-      free (Data_Segment),  Data_Segment = 0;
-    }
-
-  if (Ctors_Symbols != 0)
-    vms_fixup_xtors_section (Ctors_Symbols, Ctors_Psect);
-
-  if (Dtors_Symbols != 0)
-    vms_fixup_xtors_section (Dtors_Symbols, Dtors_Psect);
-
-  /* Debugger Symbol Table Records.  */
-
-  vms_build_DST (text_siz);
-
-  /* Wrap things up.  */
-
-  /* Write the End Of Module record.  */
-  if (Entry_Point_Symbol)
-    Write_VMS_EOM_Record (Text_Psect, S_GET_VALUE (Entry_Point_Symbol));
-  else
-    Write_VMS_EOM_Record (-1, (valueT) 0);
-
-  /* All done, close the object file.  */
-  Close_VMS_Object_File ();
-}
diff --git a/gas/config/obj-vms.h b/gas/config/obj-vms.h
deleted file mode 100644
index bd75896b4e6c..000000000000
--- a/gas/config/obj-vms.h
+++ /dev/null
@@ -1,554 +0,0 @@
-/* VMS object file format
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000,
-   2002, 2003 Free Software Foundation, Inc.
-
-This file is part of GAS, the GNU Assembler.
-
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as
-published by the Free Software Foundation; either version 2,
-or (at your option) any later version.
-
-GAS is distributed in the hope that it will be useful, but
-WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
-the GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
-
-/* Tag to validate a.out object file format processing */
-#define OBJ_VMS 1
-
-#include "targ-cpu.h"
-
-#define LONGWORD_ALIGNMENT	2
-
-/* This macro controls subsection alignment within a section.
- *
- * Under VAX/VMS, the linker (and PSECT specifications)
- * take care of correctly aligning the segments.
- * Doing the alignment here (on initialized data) can
- * mess up the calculation of global data PSECT sizes.
- */
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)	\
-  (((SEG) == data_section) ? 0 : LONGWORD_ALIGNMENT)
-
-/* This flag is used to remember whether we are in the const or the
-   data section.  By and large they are identical, but we set a no-write
-   bit for psects in the const section.  */
-
-extern unsigned char const_flag;
-
-/* This is overloaded onto const_flag, for convenience.  It's used to flag
-   dummy labels like "gcc2_compiled."  which occur before the first .text
-   or .data section directive.  */
-
-#define IN_DEFAULT_SECTION 0x80
-
-/* These are defined in obj-vms.c.  */
-extern const short seg_N_TYPE[];
-extern const segT N_TYPE_seg[];
-
-#undef NO_RELOC
-enum reloc_type
-  {
-    NO_RELOC, RELOC_32
-  };
-
-#define N_BADMAG(x)	(0)
-#define N_TXTOFF(x)	( sizeof (struct exec) )
-#define N_DATOFF(x)	( N_TXTOFF(x) + (x).a_text )
-#define N_TROFF(x)	( N_DATOFF(x) + (x).a_data )
-#define N_DROFF(x)	( N_TROFF(x) + (x).a_trsize )
-#define N_SYMOFF(x)	( N_DROFF(x) + (x).a_drsize )
-#define N_STROFF(x)	( N_SYMOFF(x) + (x).a_syms )
-
-/* We use this copy of the exec header for VMS.  We do not actually use it, but
-   what we actually do is let gas fill in the relevant slots, and when we get
-   around to writing an obj file, we just pick out what we need.  */
-
-struct exec
-{
-  unsigned long a_text;		/* length of text, in bytes */
-  unsigned long a_data;		/* length of data, in bytes */
-  unsigned long a_bss;		/* length of uninitialized data area for file, in bytes */
-  unsigned long a_trsize;	/* length of relocation info for text, in bytes */
-  unsigned long a_drsize;	/* length of relocation info for data, in bytes */
-  unsigned long a_entry;	/* start address */
-  unsigned long a_syms;		/* length of symbol table data in file, in bytes */
-};
-
-typedef struct
-  {
-    struct exec header;		/* a.out header */
-    long string_table_size;	/* names + '\0' + sizeof (int) */
-  }
-object_headers;
-
-/* A single entry in the symbol table
- * (this started as a clone of bout.h's nlist, but much was unneeded).
- */
-struct nlist
-  {
-    char *n_name;
-    unsigned char n_type;	/* See below				*/
-    unsigned char n_other;	/* used for const_flag and "default section" */
-    unsigned	: 16;		/* padding for alignment */
-    int n_desc;			/* source line number for N_SLINE stabs */
-  };
-
-/* Legal values of n_type (see aout/stab.def for the majority of the codes).
- */
-#define N_UNDF	0		/* Undefined symbol	*/
-#define N_ABS	2		/* Absolute symbol	*/
-#define N_TEXT	4		/* Text symbol		*/
-#define N_DATA	6		/* Data symbol		*/
-#define N_BSS	8		/* BSS symbol		*/
-#define N_FN	31		/* Filename symbol	*/
-
-#define N_EXT	1		/* External symbol (OR'd in with one of above)	*/
-#define N_TYPE	036		/* Mask for all the type bits			*/
-
-#define N_STAB	0340		/* Mask for all bits used for SDB entries 	*/
-
-#include "aout/stab_gnu.h"
-
-/* SYMBOL TABLE */
-/* Symbol table entry data type */
-
-typedef struct nlist obj_symbol_type;	/* Symbol table entry */
-
-/* Symbol table macros and constants */
-
-#define OBJ_SYMFIELD_TYPE struct VMS_Symbol *
-
-/*
- *  Macros to extract information from a symbol table entry.
- *  This syntactic indirection allows independence regarding a.out or coff.
- *  The argument (s) of all these macros is a pointer to a symbol table entry.
- */
-
-/* True if the symbol is external */
-#define S_IS_EXTERNAL(s)	((s)->sy_symbol.n_type & N_EXT)
-
-/* True if symbol has been defined, ie is in N_{TEXT,DATA,BSS,ABS} or N_EXT */
-#define S_IS_DEFINED(s)		(S_GET_TYPE(s) != N_UNDF)
-
-#define S_IS_COMMON(s)	(S_GET_TYPE(s) == N_UNDF && S_GET_VALUE(s) != 0)
-
-/* Return true for symbols that should not be reduced to section
-   symbols or eliminated from expressions, because they may be
-   overridden by the linker.  */
-#define S_FORCE_RELOC(s, strict) \
-  (!SEG_NORMAL (S_GET_SEGMENT (s)))
-
-#define S_IS_REGISTER(s)	((s)->sy_symbol.n_type == N_REGISTER)
-
-/* True if a debug special symbol entry */
-#define S_IS_DEBUG(s)		((s)->sy_symbol.n_type & N_STAB)
-/* True if a symbol is local symbol name */
-/* A symbol name whose name begin with ^A is a gas internal pseudo symbol
-   nameless symbols come from .stab directives.  */
-#define S_IS_LOCAL(s)		(S_GET_NAME(s) && \
-				 !S_IS_DEBUG(s) && \
-				 (strchr(S_GET_NAME(s), '\001') != 0 || \
-				  strchr(S_GET_NAME(s), '\002') != 0 || \
-				  (S_LOCAL_NAME(s) && !flag_keep_locals)))
-/* True if a symbol is not defined in this file */
-#define S_IS_EXTERN(s)		((s)->sy_symbol.n_type & N_EXT)
-/* True if the symbol has been generated because of a .stabd directive */
-#define S_IS_STABD(s)		(S_GET_NAME(s) == (char *)0)
-
-/* Accessors */
-/* The name of the symbol */
-#define S_GET_NAME(s)		((s)->sy_symbol.n_name)
-/* The pointer to the string table */
-#define S_GET_OFFSET(s)		((s)->sy_name_offset)
-/* The raw type of the symbol */
-#define S_GET_RAW_TYPE(s)		((s)->sy_symbol.n_type)
-/* The type of the symbol */
-#define S_GET_TYPE(s)		((s)->sy_symbol.n_type & N_TYPE)
-/* The numeric value of the segment */
-#define S_GET_SEGMENT(s)	(N_TYPE_seg[S_GET_TYPE(s)])
-/* The n_other expression value */
-#define S_GET_OTHER(s)		((s)->sy_symbol.n_other)
-/* The n_desc expression value */
-#define S_GET_DESC(s)		((s)->sy_symbol.n_desc)
-
-/* Modifiers */
-/* Assume that a symbol cannot be simultaneously in more than on segment */
-/* set segment */
-#define S_SET_SEGMENT(s,seg)	((s)->sy_symbol.n_type &= ~N_TYPE,(s)->sy_symbol.n_type|=SEGMENT_TO_SYMBOL_TYPE(seg))
-/* The symbol is external */
-#define S_SET_EXTERNAL(s)	((s)->sy_symbol.n_type |= N_EXT)
-/* The symbol is not external */
-#define S_CLEAR_EXTERNAL(s)	((s)->sy_symbol.n_type &= ~N_EXT)
-/* Set the name of the symbol */
-#define S_SET_NAME(s,v)		((s)->sy_symbol.n_name = (v))
-/* Set the offset in the string table */
-#define S_SET_OFFSET(s,v)	((s)->sy_name_offset = (v))
-/* Set the n_other expression value */
-#define S_SET_OTHER(s,v)	((s)->sy_symbol.n_other = (v))
-/* Set the n_desc expression value */
-#define S_SET_DESC(s,v)		((s)->sy_symbol.n_desc = (v))
-/* Set the n_type expression value */
-#define S_SET_TYPE(s,v)		((s)->sy_symbol.n_type = (v))
-
-/* File header macro and type definition */
-
-#define H_GET_TEXT_SIZE(h)		((h)->header.a_text)
-#define H_GET_DATA_SIZE(h)		((h)->header.a_data)
-#define H_GET_BSS_SIZE(h)		((h)->header.a_bss)
-
-#define H_SET_TEXT_SIZE(h,v)		((h)->header.a_text = md_section_align(SEG_TEXT, (v)))
-#define H_SET_DATA_SIZE(h,v)		((h)->header.a_data = md_section_align(SEG_DATA, (v)))
-#define H_SET_BSS_SIZE(h,v)		((h)->header.a_bss = md_section_align(SEG_BSS, (v)))
-
-#define H_SET_STRING_SIZE(h,v)		((h)->string_table_size = (v))
-#define H_SET_SYMBOL_TABLE_SIZE(h,v)	((h)->header.a_syms = (v) * \
-					 sizeof (struct nlist))
-
-/* line numbering stuff.  */
-#define OBJ_EMIT_LINENO(a, b, c)	{;}
-
-#define obj_symbol_new_hook(s)	{;}
-
-/* Force structure tags into scope so that their use in prototypes
-   will never be their first occurrence.  */
-struct fix;
-struct frag;
-
-/* obj-vms routines visible to the rest of gas.  */
-
-extern void tc_aout_fix_to_chars PARAMS ((char *,struct fix *,relax_addressT));
-
-extern int vms_resolve_symbol_redef PARAMS ((symbolS *));
-#define RESOLVE_SYMBOL_REDEFINITION(X)	vms_resolve_symbol_redef(X)
-
-/* Compiler-generated label "__vax_g_doubles" is used to augment .stabs.  */
-extern void vms_check_for_special_label PARAMS ((symbolS *));
-#define obj_frob_label(X) vms_check_for_special_label(X)
-
-extern void vms_check_for_main PARAMS ((void));
-
-extern void vms_write_object_file PARAMS ((unsigned,unsigned,unsigned,
-					   struct frag *,struct frag *));
-
-/* VMS executables are nothing like a.out, but the VMS port of gcc uses
-   a.out format stabs which obj-vms.c then translates.  */
-
-#define AOUT_STABS
-
-
-#ifdef WANT_VMS_OBJ_DEFS
-
-/* The rest of this file contains definitions for constants used within
-   the actual VMS object file.  We do not use a $ in the symbols (as per
-   usual VMS convention) since System V gags on it.  */
-
-#define	OBJ_S_C_HDR	0
-#define	OBJ_S_C_HDR_MHD	0
-#define	OBJ_S_C_HDR_LNM	1
-#define	OBJ_S_C_HDR_SRC	2
-#define	OBJ_S_C_HDR_TTL	3
-#define	OBJ_S_C_HDR_CPR	4
-#define	OBJ_S_C_HDR_MTC	5
-#define	OBJ_S_C_HDR_GTX	6
-#define	OBJ_S_C_GSD	1
-#define	OBJ_S_C_GSD_PSC	0
-#define	OBJ_S_C_GSD_SYM	1
-#define	OBJ_S_C_GSD_EPM	2
-#define	OBJ_S_C_GSD_PRO	3
-#define	OBJ_S_C_GSD_SYMW	4
-#define	OBJ_S_C_GSD_EPMW	5
-#define	OBJ_S_C_GSD_PROW	6
-#define	OBJ_S_C_GSD_IDC	7
-#define	OBJ_S_C_GSD_ENV	8
-#define	OBJ_S_C_GSD_LSY	9
-#define	OBJ_S_C_GSD_LEPM	10
-#define	OBJ_S_C_GSD_LPRO	11
-#define	OBJ_S_C_GSD_SPSC	12
-#define	OBJ_S_C_TIR	2
-#define	OBJ_S_C_EOM	3
-#define	OBJ_S_C_DBG	4
-#define	OBJ_S_C_TBT	5
-#define	OBJ_S_C_LNK	6
-#define	OBJ_S_C_EOMW	7
-#define	OBJ_S_C_MAXRECTYP	7
-#define	OBJ_S_K_SUBTYP	1
-#define	OBJ_S_C_SUBTYP	1
-#define	OBJ_S_C_MAXRECSIZ	2048
-#define	OBJ_S_C_STRLVL	0
-#define	OBJ_S_C_SYMSIZ	31
-#define	OBJ_S_C_STOREPLIM	-1
-#define	OBJ_S_C_PSCALILIM	9
-
-#define	MHD_S_C_MHD	0
-#define	MHD_S_C_LNM	1
-#define	MHD_S_C_SRC	2
-#define	MHD_S_C_TTL	3
-#define	MHD_S_C_CPR	4
-#define	MHD_S_C_MTC	5
-#define	MHD_S_C_GTX	6
-#define	MHD_S_C_MAXHDRTYP	6
-
-#define	GSD_S_K_ENTRIES	1
-#define	GSD_S_C_ENTRIES	1
-#define	GSD_S_C_PSC	0
-#define	GSD_S_C_SYM	1
-#define	GSD_S_C_EPM	2
-#define	GSD_S_C_PRO	3
-#define	GSD_S_C_SYMW	4
-#define	GSD_S_C_EPMW	5
-#define	GSD_S_C_PROW	6
-#define	GSD_S_C_IDC	7
-#define	GSD_S_C_ENV	8
-#define	GSD_S_C_LSY	9
-#define	GSD_S_C_LEPM	10
-#define	GSD_S_C_LPRO	11
-#define	GSD_S_C_SPSC	12
-#define	GSD_S_C_SYMV	13
-#define	GSD_S_C_EPMV	14
-#define	GSD_S_C_PROV	15
-#define	GSD_S_C_MAXRECTYP	15
-
-#define	GSY_S_M_WEAK	1
-#define	GSY_S_M_DEF	2
-#define	GSY_S_M_UNI	4
-#define	GSY_S_M_REL	8
-
-#define	LSY_S_M_DEF	2
-#define	LSY_S_M_REL	8
-
-#define	ENV_S_M_DEF	1
-#define	ENV_S_M_NESTED	2
-
-#define	GPS_S_M_PIC	1
-#define	GPS_S_M_LIB	2
-#define	GPS_S_M_OVR	4
-#define	GPS_S_M_REL	8
-#define	GPS_S_M_GBL	16
-#define	GPS_S_M_SHR	32
-#define	GPS_S_M_EXE	64
-#define	GPS_S_M_RD	128
-#define	GPS_S_M_WRT	256
-#define	GPS_S_M_VEC	512
-#define	GPS_S_K_NAME	9
-#define	GPS_S_C_NAME	9
-
-#define	TIR_S_C_STA_GBL	0
-#define	TIR_S_C_STA_SB	1
-#define	TIR_S_C_STA_SW	2
-#define	TIR_S_C_STA_LW	3
-#define	TIR_S_C_STA_PB	4
-#define	TIR_S_C_STA_PW	5
-#define	TIR_S_C_STA_PL	6
-#define	TIR_S_C_STA_UB	7
-#define	TIR_S_C_STA_UW	8
-#define	TIR_S_C_STA_BFI	9
-#define	TIR_S_C_STA_WFI	10
-#define	TIR_S_C_STA_LFI	11
-#define	TIR_S_C_STA_EPM	12
-#define	TIR_S_C_STA_CKARG	13
-#define	TIR_S_C_STA_WPB	14
-#define	TIR_S_C_STA_WPW	15
-#define	TIR_S_C_STA_WPL	16
-#define	TIR_S_C_STA_LSY	17
-#define	TIR_S_C_STA_LIT	18
-#define	TIR_S_C_STA_LEPM	19
-#define	TIR_S_C_MAXSTACOD	19
-#define	TIR_S_C_MINSTOCOD	20
-#define	TIR_S_C_STO_SB	20
-#define	TIR_S_C_STO_SW	21
-#define	TIR_S_C_STO_L	22
-#define	TIR_S_C_STO_BD	23
-#define	TIR_S_C_STO_WD	24
-#define	TIR_S_C_STO_LD	25
-#define	TIR_S_C_STO_LI	26
-#define	TIR_S_C_STO_PIDR	27
-#define	TIR_S_C_STO_PICR	28
-#define	TIR_S_C_STO_RSB	29
-#define	TIR_S_C_STO_RSW	30
-#define	TIR_S_C_STO_RL	31
-#define	TIR_S_C_STO_VPS	32
-#define	TIR_S_C_STO_USB	33
-#define	TIR_S_C_STO_USW	34
-#define	TIR_S_C_STO_RUB	35
-#define	TIR_S_C_STO_RUW	36
-#define	TIR_S_C_STO_B	37
-#define	TIR_S_C_STO_W	38
-#define	TIR_S_C_STO_RB	39
-#define	TIR_S_C_STO_RW	40
-#define	TIR_S_C_STO_RIVB	41
-#define	TIR_S_C_STO_PIRR	42
-#define	TIR_S_C_MAXSTOCOD	42
-#define	TIR_S_C_MINOPRCOD	50
-#define	TIR_S_C_OPR_NOP	50
-#define	TIR_S_C_OPR_ADD	51
-#define	TIR_S_C_OPR_SUB	52
-#define	TIR_S_C_OPR_MUL	53
-#define	TIR_S_C_OPR_DIV	54
-#define	TIR_S_C_OPR_AND	55
-#define	TIR_S_C_OPR_IOR	56
-#define	TIR_S_C_OPR_EOR	57
-#define	TIR_S_C_OPR_NEG	58
-#define	TIR_S_C_OPR_COM	59
-#define	TIR_S_C_OPR_INSV	60
-#define	TIR_S_C_OPR_ASH	61
-#define	TIR_S_C_OPR_USH	62
-#define	TIR_S_C_OPR_ROT	63
-#define	TIR_S_C_OPR_SEL	64
-#define	TIR_S_C_OPR_REDEF	65
-#define	TIR_S_C_OPR_DFLIT	66
-#define	TIR_S_C_MAXOPRCOD	66
-#define	TIR_S_C_MINCTLCOD	80
-#define	TIR_S_C_CTL_SETRB	80
-#define	TIR_S_C_CTL_AUGRB	81
-#define	TIR_S_C_CTL_DFLOC	82
-#define	TIR_S_C_CTL_STLOC	83
-#define	TIR_S_C_CTL_STKDL	84
-#define	TIR_S_C_MAXCTLCOD	84
-
-/*
- *	Debugger symbol definitions:  These are done by hand, as no
- *					machine-readable version seems
- *					to be available.
- */
-#define DST_S_C_C	  7	/* Language == "C"	*/
-#define DST_S_C_CXX	 15	/* Language == "C++"	*/
-#define DST_S_C_VERSION	153
-#define	DST_S_C_SOURCE	155	/* Source file		*/
-#define DST_S_C_PROLOG	162
-#define	DST_S_C_BLKBEG	176	/* Beginning of block	*/
-#define	DST_S_C_BLKEND	177	/* End of block	*/
-#define DST_S_C_ENTRY	181
-#define DST_S_C_PSECT	184
-#define	DST_S_C_LINE_NUM	185	/* Line Number		*/
-#define DST_S_C_LBLORLIT	186
-#define DST_S_C_LABEL	187
-#define	DST_S_C_MODBEG	188	/* Beginning of module	*/
-#define	DST_S_C_MODEND	189	/* End of module	*/
-#define	DST_S_C_RTNBEG	190	/* Beginning of routine	*/
-#define	DST_S_C_RTNEND	191	/* End of routine	*/
-#define	DST_S_C_DELTA_PC_W	1	/* Incr PC	*/
-#define	DST_S_C_INCR_LINUM	2	/* Incr Line #	*/
-#define	DST_S_C_INCR_LINUM_W	3	/* Incr Line #	*/
-#define DST_S_C_SET_LINUM_INCR	4
-#define DST_S_C_SET_LINUM_INCR_W	5
-#define DST_S_C_RESET_LINUM_INCR	6
-#define DST_S_C_BEG_STMT_MODE	7
-#define DST_S_C_END_STMT_MODE	8
-#define	DST_S_C_SET_LINE_NUM	9	/* Set Line #	*/
-#define DST_S_C_SET_PC		10
-#define DST_S_C_SET_PC_W		11
-#define DST_S_C_SET_PC_L		12
-#define DST_S_C_SET_STMTNUM	13
-#define DST_S_C_TERM		14	/* End of lines	*/
-#define DST_S_C_TERM_W		15	/* End of lines	*/
-#define	DST_S_C_SET_ABS_PC	16	/* Set PC	*/
-#define	DST_S_C_DELTA_PC_L	17	/* Incr PC	*/
-#define DST_S_C_INCR_LINUM_L	18	/* Incr Line #	*/
-#define DST_S_C_SET_LINUM_B	19	/* Set Line #	*/
-#define DST_S_C_SET_LINUM_L	20	/* Set Line #	*/
-#define	DST_S_C_TERM_L		21	/* End of lines	*/
-/* these are used with DST_S_C_SOURCE */
-#define DST_S_C_SRC_DECLFILE	 1	/* Declare source file */
-#define DST_S_C_SRC_SETFILE	 2	/* Set source file */
-#define DST_S_C_SRC_SETREC_L	 3	/* Set record, longword value */
-#define DST_S_C_SRC_SETREC_W	 4	/* Set record, word value */
-#define DST_S_C_SRC_DEFLINES_W	10	/* # of line, word counter */
-#define DST_S_C_SRC_DEFLINES_B	11	/* # of line, byte counter */
-#define DST_S_C_SRC_FORMFEED	16	/* ^L counts as a record */
-/* the following are the codes for the various data types.  Anything not on
- * the list is included under 'advanced_type'
- */
-#define DBG_S_C_UCHAR		0x02
-#define DBG_S_C_USINT		0x03
-#define DBG_S_C_ULINT		0x04
-#define DBG_S_C_UQUAD		0x05
-#define DBG_S_C_SCHAR		0x06
-#define DBG_S_C_SSINT		0x07
-#define DBG_S_C_SLINT		0x08
-#define DBG_S_C_SQUAD		0x09
-#define DBG_S_C_REAL4		0x0a
-#define DBG_S_C_REAL8		0x0b		/* D_float double */
-#define DBG_S_C_COMPLX4		0x0c		/* 2xF_float complex float */
-#define DBG_S_C_COMPLX8		0x0d		/* 2xD_float complex double */
-#define DBG_S_C_REAL8_G		0x1b		/* G_float double */
-#define DBG_S_C_COMPLX8_G	0x1d		/* 2xG_float complex double */
-#define DBG_S_C_FUNCTION_ADDR	0x17
-#define DBG_S_C_ADVANCED_TYPE	0xa3
-/*  Some of these are just for future reference.  [pr]
- */
-#define DBG_S_C_UBITA		0x01	/* unsigned, aligned bit field */
-#define DBG_S_C_UBITU		0x22	/* unsigned, unaligned bit field */
-#define DBG_S_C_SBITA		0x29	/* signed, aligned bit field */
-#define DBG_S_C_SBITU		0x2a	/* signed, unaligned bit field */
-#define DBG_S_C_CSTRING		0x2e	/* asciz ('\0' terminated) string */
-#define DBG_S_C_WCHAR		0x38	/* wchar_t */
-/*  These are descriptor class codes.
- */
-#define DSC_K_CLASS_S		0x01	/* static (fixed length) */
-#define DSC_K_CLASS_D		0x02	/* dynamic string (not via malloc!) */
-#define DSC_K_CLASS_A		0x04	/* array */
-#define DSC_K_CLASS_UBS		0x0d	/* unaligned bit string */
-/*  These are the codes that are used to generate the definitions of struct
- *  union and enum records
- */
-#define DBG_S_C_ENUM_ITEM		0xa4
-#define DBG_S_C_ENUM_START		0xa5
-#define DBG_S_C_ENUM_END		0xa6
-#define DBG_S_C_STRUCT_ITEM		DST_K_VFLAGS_BITOFFS	/* 0xff */
-#define DBG_S_C_STRUCT_START		0xab
-#define DBG_S_C_STRUCT_END		0xac
-#define DST_K_TYPSPEC			0xaf		/* type specification */
-/* These codes are used in the generation of the symbol definition records
- */
-#define DST_K_VFLAGS_NOVAL		0x80	/* struct definition only */
-#define DST_K_VFLAGS_DSC		0xfa	/* descriptor used */
-#define DST_K_VFLAGS_TVS		0xfb	/* trailing value specified */
-#define DST_K_VS_FOLLOWS		0xfd	/* value spec follows */
-#define DST_K_VFLAGS_BITOFFS		0xff	/* value contains bit offset */
-#define DST_K_VALKIND_LITERAL	0
-#define DST_K_VALKIND_ADDR	1
-#define DST_K_VALKIND_DESC	2
-#define DST_K_VALKIND_REG	3
-#define DST_K_REG_VAX_AP	0x0c	/* R12 */
-#define DST_K_REG_VAX_FP	0x0d	/* R13 */
-#define DST_K_REG_VAX_SP	0x0e	/* R14 */
-#define DST_V_VALKIND		0	/* offset of valkind field */
-#define DST_V_INDIRECT		2	/* offset to indirect bit */
-#define DST_V_DISP		3	/* offset to displacement bit */
-#define DST_V_REGNUM		4	/* offset to register number */
-#define DST_M_INDIRECT		(1<<DST_V_INDIRECT)
-#define DST_M_DISP		(1<<DST_V_DISP)
-#define DBG_C_FUNCTION_PARAM	/* 0xc9 */	\
-	(DST_K_VALKIND_ADDR|DST_M_DISP|(DST_K_REG_VAX_AP<<DST_V_REGNUM))
-#define DBG_C_LOCAL_SYM		/* 0xd9 */	\
-	(DST_K_VALKIND_ADDR|DST_M_DISP|(DST_K_REG_VAX_FP<<DST_V_REGNUM))
-/* Kinds of value specifications
- */
-#define DST_K_VS_ALLOC_SPLIT	3	/* split lifetime */
-/* Kinds of type specifications
- */
-#define DST_K_TS_ATOM		0x01	/* atomic type specification */
-#define DST_K_TS_DSC		0x02	/* descriptor type spec */
-#define DST_K_TS_IND		0x03	/* indirect type specification */
-#define DST_K_TS_TPTR		0x04	/* typed pointer type spec */
-#define DST_K_TS_PTR		0x05	/* pointer type spec */
-#define DST_K_TS_ARRAY		0x07	/* array type spec */
-#define DST_K_TS_NOV_LENG	0x0e	/* novel length type spec */
-/*  These are the codes that are used in the suffix records to determine the
- *  actual data type
- */
-#define DBG_S_C_BASIC			DST_K_TS_ATOM
-#define DBG_S_C_BASIC_ARRAY		DST_K_TS_DSC
-#define DBG_S_C_STRUCT			DST_K_TS_IND
-#define DBG_S_C_POINTER			DST_K_TS_TPTR
-#define DBG_S_C_VOID			DST_K_TS_PTR
-#define DBG_S_C_COMPLEX_ARRAY		DST_K_TS_ARRAY
-
-#endif	/* WANT_VMS_OBJ_DEFS */
diff --git a/gas/config/tc-a29k.c b/gas/config/tc-a29k.c
deleted file mode 100644
index ab501645d836..000000000000
--- a/gas/config/tc-a29k.c
+++ /dev/null
@@ -1,1297 +0,0 @@
-/* tc-a29k.c -- Assemble for the AMD 29000.
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 2000, 2001, 2002
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* John Gilmore has reorganized this module somewhat, to make it easier
-   to convert it to new machines' assemblers as desired.  There was too
-   much bloody rewriting required before.  There still probably is.  */
-
-#include "as.h"
-#include "safe-ctype.h"
-
-#include "opcode/a29k.h"
-
-/* Make it easier to clone this machine desc into another one.  */
-#define	machine_opcode	a29k_opcode
-#define	machine_opcodes	a29k_opcodes
-#define	machine_ip	a29k_ip
-#define	machine_it	a29k_it
-
-#define	IMMEDIATE_BIT	0x01000000	/* Turns RB into Immediate */
-#define	ABSOLUTE_BIT	0x01000000	/* Turns PC-relative to Absolute */
-#define	CE_BIT		0x00800000	/* Coprocessor enable in LOAD */
-#define	UI_BIT		0x00000080	/* Unsigned integer in CONVERT */
-
-/* handle of the OPCODE hash table */
-static struct hash_control *op_hash = NULL;
-
-struct machine_it
-  {
-    char *error;
-    unsigned long opcode;
-    struct nlist *nlistp;
-    expressionS exp;
-    int pcrel;
-    int reloc_offset;		/* Offset of reloc within insn */
-
-    int reloc;
-  }
-the_insn;
-
-static void machine_ip PARAMS ((char *str));
-/* static void print_insn PARAMS ((struct machine_it *insn)); */
-#ifndef OBJ_COFF
-static void s_data1 PARAMS ((void));
-static void s_use PARAMS ((int));
-#endif
-static void insert_sreg PARAMS ((char *, int));
-static void define_some_regs PARAMS ((void));
-static char *parse_operand PARAMS ((char *, expressionS *, int));
-
-const pseudo_typeS
-md_pseudo_table[] =
-{
-  {"align", s_align_bytes, 4},
-  {"block", s_space, 0},
-  {"cputype", s_ignore, 0},	/* CPU as 29000 or 29050 */
-  {"reg", s_lsym, 0},		/* Register equate, same as equ */
-  {"space", s_ignore, 0},	/* Listing control */
-  {"sect", s_ignore, 0},	/* Creation of coff sections */
-#ifndef OBJ_COFF
-  /* We can do this right with coff.  */
-  {"use", s_use, 0},
-#endif
-  {"word", cons, 4},
-  {NULL, 0, 0},
-};
-
-#if defined(BFD_HEADERS)
-#ifdef RELSZ
-const int md_reloc_size = RELSZ;	/* Coff headers */
-#else
-const int md_reloc_size = 12;		/* something else headers */
-#endif
-#else
-const int md_reloc_size = 12;		/* Not bfdized*/
-#endif
-
-/* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful */
-const char comment_chars[] = ";";
-
-/* This array holds the chars that only start a comment at the beginning of
-   a line.  If the line seems to have the form '# 123 filename'
-   .line and .file directives will appear in the pre-processed output */
-/* Note that input_file.c hand checks for '#' at the beginning of the
-   first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.  */
-/* Also note that comments like this one will always work */
-const char line_comment_chars[] = "#";
-
-/* We needed an unused char for line separation to work around the
-   lack of macros, using sed and such.  */
-const char line_separator_chars[] = "@";
-
-/* Chars that can be used to separate mant from exp in floating point nums */
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or    0d1.2345e12 */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
-
-/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
-   changed in read.c.  Ideally it shouldn't have to know about it at
-   all, but nothing is ideal around here.  */
-
-/*
- *  anull bit - causes the branch delay slot instructions to not be executed
- */
-#define ANNUL       (1 << 29)
-
-#ifndef OBJ_COFF
-
-static void
-s_use (ignore)
-     int ignore;
-{
-  if (strncmp (input_line_pointer, ".text", 5) == 0)
-    {
-      input_line_pointer += 5;
-      s_text (0);
-      return;
-    }
-  if (strncmp (input_line_pointer, ".data", 5) == 0)
-    {
-      input_line_pointer += 5;
-      s_data (0);
-      return;
-    }
-  if (strncmp (input_line_pointer, ".data1", 6) == 0)
-    {
-      input_line_pointer += 6;
-      s_data1 ();
-      return;
-    }
-  /* Literals can't go in the text segment because you can't read from
-     instruction memory on some 29k's.  So, into initialized data.  */
-  if (strncmp (input_line_pointer, ".lit", 4) == 0)
-    {
-      input_line_pointer += 4;
-      subseg_set (SEG_DATA, 200);
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-  as_bad (_("Unknown segment type"));
-  demand_empty_rest_of_line ();
-}
-
-static void
-s_data1 ()
-{
-  subseg_set (SEG_DATA, 1);
-  demand_empty_rest_of_line ();
-}
-
-#endif /* OBJ_COFF */
-
-/* Install symbol definition that maps REGNAME to REGNO.
-   FIXME-SOON:  These are not recognized in mixed case.  */
-
-static void
-insert_sreg (regname, regnum)
-     char *regname;
-     int regnum;
-{
-  /* FIXME-SOON, put something in these syms so they won't be output
-     to the symbol table of the resulting object file.  */
-
-  /* Must be large enough to hold the names of the special registers.  */
-  char buf[80];
-  int i;
-
-  symbol_table_insert (symbol_new (regname, SEG_REGISTER, (valueT) regnum,
-				   &zero_address_frag));
-  for (i = 0; regname[i]; i++)
-    buf[i] = TOUPPER (regname[i]);
-  buf[i] = '\0';
-
-  symbol_table_insert (symbol_new (buf, SEG_REGISTER, (valueT) regnum,
-				   &zero_address_frag));
-}
-
-/* Install symbol definitions for assorted special registers.
-   See ASM29K Ref page 2-9.  */
-
-static void
-define_some_regs ()
-{
-#define SREG	256
-
-  /* Protected special-purpose register names */
-  insert_sreg ("vab", SREG + 0);
-  insert_sreg ("ops", SREG + 1);
-  insert_sreg ("cps", SREG + 2);
-  insert_sreg ("cfg", SREG + 3);
-  insert_sreg ("cha", SREG + 4);
-  insert_sreg ("chd", SREG + 5);
-  insert_sreg ("chc", SREG + 6);
-  insert_sreg ("rbp", SREG + 7);
-  insert_sreg ("tmc", SREG + 8);
-  insert_sreg ("tmr", SREG + 9);
-  insert_sreg ("pc0", SREG + 10);
-  insert_sreg ("pc1", SREG + 11);
-  insert_sreg ("pc2", SREG + 12);
-  insert_sreg ("mmu", SREG + 13);
-  insert_sreg ("lru", SREG + 14);
-
-  /* Additional protected special-purpose registers for the 29050 */
-  insert_sreg ("rsn",  SREG + 15);
-  insert_sreg ("rma0", SREG + 16);
-  insert_sreg ("rmc0", SREG + 17);
-  insert_sreg ("rma1", SREG + 18);
-  insert_sreg ("rmc1", SREG + 19);
-  insert_sreg ("spc0", SREG + 20);
-  insert_sreg ("spc1", SREG + 21);
-  insert_sreg ("spc2", SREG + 22);
-  insert_sreg ("iba0", SREG + 23);
-  insert_sreg ("ibc0", SREG + 24);
-  insert_sreg ("iba1", SREG + 25);
-  insert_sreg ("ibc1", SREG + 26);
-
-  /* Additional registers for the 29040.  */
-  insert_sreg ("dba", SREG + 27);
-  insert_sreg ("dbc", SREG + 28);
-  insert_sreg ("cir", SREG + 29);
-  insert_sreg ("cdr", SREG + 30);
-
-  /* Unprotected special-purpose register names */
-  insert_sreg ("ipc", SREG + 128);
-  insert_sreg ("ipa", SREG + 129);
-  insert_sreg ("ipb", SREG + 130);
-  insert_sreg ("q", SREG + 131);
-  insert_sreg ("alu", SREG + 132);
-  insert_sreg ("bp", SREG + 133);
-  insert_sreg ("fc", SREG + 134);
-  insert_sreg ("cr", SREG + 135);
-  insert_sreg ("fpe", SREG + 160);
-  insert_sreg ("inte", SREG + 161);
-  insert_sreg ("fps", SREG + 162);
-  /*  "",    SREG+163);	  Reserved */
-  insert_sreg ("exop", SREG + 164);
-}
-
-/* This function is called once, at assembler startup time.  It should
-   set up all the tables, etc., that the MD part of the assembler will
-   need.  */
-void
-md_begin ()
-{
-  register const char *retval = NULL;
-  int lose = 0;
-  register int skipnext = 0;
-  register unsigned int i;
-  register char *strend, *strend2;
-
-  /* Hash up all the opcodes for fast use later.  */
-
-  op_hash = hash_new ();
-
-  for (i = 0; i < num_opcodes; i++)
-    {
-      const char *name = machine_opcodes[i].name;
-
-      if (skipnext)
-	{
-	  skipnext = 0;
-	  continue;
-	}
-
-      /* Hack to avoid multiple opcode entries.  We pre-locate all the
-	 variations (b/i field and P/A field) and handle them.  */
-
-      if (!strcmp (name, machine_opcodes[i + 1].name))
-	{
-	  if ((machine_opcodes[i].opcode & 0x01000000) != 0
-	      || (machine_opcodes[i + 1].opcode & 0x01000000) == 0
-	      || ((machine_opcodes[i].opcode | 0x01000000)
-		  != machine_opcodes[i + 1].opcode))
-	    goto bad_table;
-	  strend = machine_opcodes[i].args + strlen (machine_opcodes[i].args) - 1;
-	  strend2 = machine_opcodes[i + 1].args + strlen (machine_opcodes[i + 1].args) - 1;
-	  switch (*strend)
-	    {
-	    case 'b':
-	      if (*strend2 != 'i')
-		goto bad_table;
-	      break;
-	    case 'P':
-	      if (*strend2 != 'A')
-		goto bad_table;
-	      break;
-	    default:
-	    bad_table:
-	      fprintf (stderr, "internal error: can't handle opcode %s\n",
-		       name);
-	      lose = 1;
-	    }
-
-	  /* OK, this is an i/b or A/P pair.  We skip the
-	     higher-valued one, and let the code for operand checking
-	     handle OR-ing in the bit.  */
-	  skipnext = 1;
-	}
-
-      retval = hash_insert (op_hash, name, (PTR) &machine_opcodes[i]);
-      if (retval != NULL)
-	{
-	  fprintf (stderr, "internal error: can't hash `%s': %s\n",
-		   machine_opcodes[i].name, retval);
-	  lose = 1;
-	}
-    }
-
-  if (lose)
-    as_fatal (_("Broken assembler.  No assembly attempted."));
-
-  define_some_regs ();
-}
-
-/* Assemble a single instruction.  Its label has already been handled
-   by the generic front end.  We just parse opcode and operands, and
-   produce the bytes of data and relocation.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  char *toP;
-
-  know (str);
-  machine_ip (str);
-  toP = frag_more (4);
-  /* put out the opcode */
-  md_number_to_chars (toP, the_insn.opcode, 4);
-
-  /* put out the symbol-dependent stuff */
-  if (the_insn.reloc != NO_RELOC)
-    {
-      fix_new_exp (frag_now,
-		   (toP - frag_now->fr_literal + the_insn.reloc_offset),
-		   4,		/* size */
-		   &the_insn.exp,
-		   the_insn.pcrel,
-		   the_insn.reloc);
-    }
-}
-
-static char *
-parse_operand (s, operandp, opt)
-     char *s;
-     expressionS *operandp;
-     int opt;
-{
-  char *save = input_line_pointer;
-  char *new;
-
-  input_line_pointer = s;
-  expression (operandp);
-  if (operandp->X_op == O_absent && ! opt)
-    as_bad (_("missing operand"));
-  new = input_line_pointer;
-  input_line_pointer = save;
-  return new;
-}
-
-/* Instruction parsing.  Takes a string containing the opcode.
-   Operands are at input_line_pointer.  Output is in the_insn.
-   Warnings or errors are generated.  */
-
-static void
-machine_ip (str)
-     char *str;
-{
-  char *s;
-  const char *args;
-  struct machine_opcode *insn;
-  char *argsStart;
-  unsigned long opcode;
-  expressionS the_operand;
-  expressionS *operand = &the_operand;
-  unsigned int reg;
-
-  /* Must handle `div0' opcode.  */
-  s = str;
-  if (ISALPHA (*s))
-    for (; ISALNUM (*s); ++s)
-      *s = TOLOWER (*s);
-
-  switch (*s)
-    {
-    case '\0':
-      break;
-
-    case ' ':			/* FIXME-SOMEDAY more whitespace */
-      *s++ = '\0';
-      break;
-
-    default:
-      as_bad (_("Unknown opcode: `%s'"), str);
-      return;
-    }
-  if ((insn = (struct machine_opcode *) hash_find (op_hash, str)) == NULL)
-    {
-      as_bad (_("Unknown opcode `%s'."), str);
-      return;
-    }
-  argsStart = s;
-  opcode = insn->opcode;
-  memset (&the_insn, '\0', sizeof (the_insn));
-  the_insn.reloc = NO_RELOC;
-
-  /* Build the opcode, checking as we go to make sure that the
-     operands match.
-
-     If an operand matches, we modify the_insn or opcode appropriately,
-     and do a "continue".  If an operand fails to match, we "break".  */
-
-  if (insn->args[0] != '\0')
-    {
-      /* Prime the pump.  */
-      s = parse_operand (s, operand, insn->args[0] == 'I');
-    }
-
-  for (args = insn->args;; ++args)
-    {
-      switch (*args)
-	{
-
-	case '\0':		/* end of args */
-	  if (*s == '\0')
-	    {
-	      /* We are truly done.  */
-	      the_insn.opcode = opcode;
-	      return;
-	    }
-	  as_bad (_("Too many operands: %s"), s);
-	  break;
-
-	case ',':		/* Must match a comma */
-	  if (*s++ == ',')
-	    {
-	      /* Parse next operand.  */
-	      s = parse_operand (s, operand, args[1] == 'I');
-	      continue;
-	    }
-	  break;
-
-	case 'v':		/* Trap numbers (immediate field) */
-	  if (operand->X_op == O_constant)
-	    {
-	      if (operand->X_add_number < 256)
-		{
-		  opcode |= (operand->X_add_number << 16);
-		  continue;
-		}
-	      else
-		{
-		  as_bad (_("Immediate value of %ld is too large"),
-			  (long) operand->X_add_number);
-		  continue;
-		}
-	    }
-	  the_insn.reloc = RELOC_8;
-	  the_insn.reloc_offset = 1;	/* BIG-ENDIAN Byte 1 of insn */
-	  the_insn.exp = *operand;
-	  continue;
-
-	case 'b':		/* A general register or 8-bit immediate */
-	case 'i':
-	  /* We treat the two cases identically since we mashed
-	     them together in the opcode table.  */
-	  if (operand->X_op == O_register)
-	    goto general_reg;
-
-	  /* Make sure the 'i' case really exists.  */
-	  if ((insn->opcode | IMMEDIATE_BIT) != (insn + 1)->opcode)
-	    break;
-
-	  opcode |= IMMEDIATE_BIT;
-	  if (operand->X_op == O_constant)
-	    {
-	      if (operand->X_add_number < 256)
-		{
-		  opcode |= operand->X_add_number;
-		  continue;
-		}
-	      else
-		{
-		  as_bad (_("Immediate value of %ld is too large"),
-			  (long) operand->X_add_number);
-		  continue;
-		}
-	    }
-	  the_insn.reloc = RELOC_8;
-	  the_insn.reloc_offset = 3;	/* BIG-ENDIAN Byte 3 of insn */
-	  the_insn.exp = *operand;
-	  continue;
-
-	case 'a':		/* next operand must be a register */
-	case 'c':
-	general_reg:
-	  /* lrNNN or grNNN or %%expr or a user-def register name */
-	  if (operand->X_op != O_register)
-	    break;		/* Only registers */
-	  know (operand->X_add_symbol == 0);
-	  know (operand->X_op_symbol == 0);
-	  reg = operand->X_add_number;
-	  if (reg >= SREG)
-	    break;		/* No special registers */
-
-	  /* Got the register, now figure out where it goes in the
-	     opcode.  */
-	  switch (*args)
-	    {
-	    case 'a':
-	      opcode |= reg << 8;
-	      continue;
-
-	    case 'b':
-	    case 'i':
-	      opcode |= reg;
-	      continue;
-
-	    case 'c':
-	      opcode |= reg << 16;
-	      continue;
-	    }
-	  as_fatal (_("failed sanity check."));
-	  break;
-
-	case 'x':		/* 16 bit constant, zero-extended */
-	case 'X':		/* 16 bit constant, one-extended */
-	  if (operand->X_op == O_constant)
-	    {
-	      opcode |= (operand->X_add_number & 0xFF) << 0 |
-		((operand->X_add_number & 0xFF00) << 8);
-	      continue;
-	    }
-	  the_insn.reloc = RELOC_CONST;
-	  the_insn.exp = *operand;
-	  continue;
-
-	case 'h':
-	  if (operand->X_op == O_constant)
-	    {
-	      opcode |= (operand->X_add_number & 0x00FF0000) >> 16 |
-		(((unsigned long) operand->X_add_number
-		  /* avoid sign ext */  & 0xFF000000) >> 8);
-	      continue;
-	    }
-	  the_insn.reloc = RELOC_CONSTH;
-	  the_insn.exp = *operand;
-	  continue;
-
-	case 'P':		/* PC-relative jump address */
-	case 'A':		/* Absolute jump address */
-	  /* These two are treated together since we folded the
-	     opcode table entries together.  */
-	  if (operand->X_op == O_constant)
-	    {
-	      /* Make sure the 'A' case really exists.  */
-	      if ((insn->opcode | ABSOLUTE_BIT) != (insn + 1)->opcode)
-		break;
-	      {
-		bfd_vma v, mask;
-		mask = 0x1ffff;
-		v = operand->X_add_number & ~ mask;
-		if (v)
-		  as_bad ("call/jmp target out of range");
-	      }
-	      opcode |= ABSOLUTE_BIT |
-		(operand->X_add_number & 0x0003FC00) << 6 |
-		((operand->X_add_number & 0x000003FC) >> 2);
-	      continue;
-	    }
-	  the_insn.reloc = RELOC_JUMPTARG;
-	  the_insn.exp = *operand;
-	  the_insn.pcrel = 1;	/* Assume PC-relative jump */
-	  /* FIXME-SOON, Do we figure out whether abs later, after
-             know sym val? */
-	  continue;
-
-	case 'e':		/* Coprocessor enable bit for LOAD/STORE insn */
-	  if (operand->X_op == O_constant)
-	    {
-	      if (operand->X_add_number == 0)
-		continue;
-	      if (operand->X_add_number == 1)
-		{
-		  opcode |= CE_BIT;
-		  continue;
-		}
-	    }
-	  break;
-
-	case 'n':		/* Control bits for LOAD/STORE instructions */
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 128)
-	    {
-	      opcode |= (operand->X_add_number << 16);
-	      continue;
-	    }
-	  break;
-
-	case 's':		/* Special register number */
-	  if (operand->X_op != O_register)
-	    break;		/* Only registers */
-	  if (operand->X_add_number < SREG)
-	    break;		/* Not a special register */
-	  opcode |= (operand->X_add_number & 0xFF) << 8;
-	  continue;
-
-	case 'u':		/* UI bit of CONVERT */
-	  if (operand->X_op == O_constant)
-	    {
-	      if (operand->X_add_number == 0)
-		continue;
-	      if (operand->X_add_number == 1)
-		{
-		  opcode |= UI_BIT;
-		  continue;
-		}
-	    }
-	  break;
-
-	case 'r':		/* RND bits of CONVERT */
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 8)
-	    {
-	      opcode |= operand->X_add_number << 4;
-	      continue;
-	    }
-	  break;
-
-	case 'I':		/* ID bits of INV and IRETINV.  */
-	  /* This operand is optional.  */
-	  if (operand->X_op == O_absent)
-	    continue;
-	  else if (operand->X_op == O_constant
-		   && operand->X_add_number < 4)
-	    {
-	      opcode |= operand->X_add_number << 16;
-	      continue;
-	    }
-	  break;
-
-	case 'd':		/* FD bits of CONVERT */
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 4)
-	    {
-	      opcode |= operand->X_add_number << 2;
-	      continue;
-	    }
-	  break;
-
-	case 'f':		/* FS bits of CONVERT */
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 4)
-	    {
-	      opcode |= operand->X_add_number << 0;
-	      continue;
-	    }
-	  break;
-
-	case 'C':
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 4)
-	    {
-	      opcode |= operand->X_add_number << 16;
-	      continue;
-	    }
-	  break;
-
-	case 'F':
-	  if (operand->X_op == O_constant &&
-	      operand->X_add_number < 16)
-	    {
-	      opcode |= operand->X_add_number << 18;
-	      continue;
-	    }
-	  break;
-
-	default:
-	  BAD_CASE (*args);
-	}
-      /* Types or values of args don't match.  */
-      as_bad ("Invalid operands");
-      return;
-    }
-}
-
-/* This is identical to the md_atof in m68k.c.  I think this is right,
-   but I'm not sure.
-
-   Turn a string in input_line_pointer into a floating point constant
-   of type TYPE, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.  */
-
-/* Equal to MAX_PRECISION in atof-ieee.c */
-#define MAX_LITTLENUMS 6
-
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return "Bad call to MD_ATOF()";
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  for (wordP = words; prec--;)
-    {
-      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return 0;
-}
-
-/*
- * Write out big-endian.
- */
-void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
-{
-  number_to_chars_bigendian (buf, val, n);
-}
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = *valP;
-  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-
-  fixP->fx_addnumber = val;	/* Remember value for emit_reloc.  */
-
-  know (fixP->fx_size == 4);
-  know (fixP->fx_r_type < NO_RELOC);
-
-  /* This is a hack.  There should be a better way to handle this.  */
-  if (fixP->fx_r_type == RELOC_WDISP30 && fixP->fx_addsy)
-    val += fixP->fx_where + fixP->fx_frag->fr_address;
-
-  switch (fixP->fx_r_type)
-    {
-    case RELOC_32:
-      buf[0] = val >> 24;
-      buf[1] = val >> 16;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_8:
-      buf[0] = val;
-      break;
-
-    case RELOC_WDISP30:
-      val = (val >> 2) + 1;
-      buf[0] |= (val >> 24) & 0x3f;
-      buf[1] = (val >> 16);
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_HI22:
-      buf[1] |= (val >> 26) & 0x3f;
-      buf[2] = val >> 18;
-      buf[3] = val >> 10;
-      break;
-
-    case RELOC_LO10:
-      buf[2] |= (val >> 8) & 0x03;
-      buf[3] = val;
-      break;
-
-    case RELOC_BASE13:
-      buf[2] |= (val >> 8) & 0x1f;
-      buf[3] = val;
-      break;
-
-    case RELOC_WDISP22:
-      val = (val >> 2) + 1;
-      /* FALLTHROUGH */
-    case RELOC_BASE22:
-      buf[1] |= (val >> 16) & 0x3f;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_JUMPTARG:	/* 00XX00XX pattern in a word */
-      if (!fixP->fx_done)
-	{
-	  /* The linker tries to support both AMD and old GNU style
-             R_IREL relocs.  That means that if the addend is exactly
-             the negative of the address within the section, the
-             linker will not handle it correctly.  */
-	  if (fixP->fx_pcrel
-	      && val != 0
-	      && val == - (fixP->fx_frag->fr_address + fixP->fx_where))
-	    as_bad_where
-	      (fixP->fx_file, fixP->fx_line,
-	       "the linker will not handle this relocation correctly");
-	}
-      else if (fixP->fx_pcrel)
-	{
-	  long v = val >> 17;
-
-	  if (v != 0 && v != -1)
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  "call/jmp target out of range");
-	}
-      else
-	/* This case was supposed to be handled in machine_ip.  */
-	abort ();
-      buf[1] = val >> 10;	/* Holds bits 0003FFFC of address */
-      buf[3] = val >> 2;
-      break;
-
-    case RELOC_CONST:		/* 00XX00XX pattern in a word */
-      buf[1] = val >> 8;	/* Holds bits 0000XXXX */
-      buf[3] = val;
-      break;
-
-    case RELOC_CONSTH:		/* 00XX00XX pattern in a word */
-      buf[1] = val >> 24;	/* Holds bits XXXX0000 */
-      buf[3] = val >> 16;
-      break;
-
-    case NO_RELOC:
-    default:
-      as_bad (_("bad relocation type: 0x%02x"), fixP->fx_r_type);
-      break;
-    }
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-}
-
-#ifdef OBJ_COFF
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-
-  switch (fixP->fx_r_type)
-    {
-    case RELOC_32:
-      return (R_WORD);
-    case RELOC_8:
-      return (R_BYTE);
-    case RELOC_CONST:
-      return (R_ILOHALF);
-    case RELOC_CONSTH:
-      return (R_IHIHALF);
-    case RELOC_JUMPTARG:
-      return (R_IREL);
-    default:
-      printf (_("need %o3\n"), fixP->fx_r_type);
-      abort ();
-    }				/* switch on type */
-
-  return (0);
-}
-
-#endif /* OBJ_COFF */
-
-/* should never be called for 29k */
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     register fragS *fragP ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("a29k_convert_frag\n"));
-}
-
-/* should never be called for a29k */
-int
-md_estimate_size_before_relax (fragP, segtype)
-     register fragS *fragP ATTRIBUTE_UNUSED;
-     segT segtype ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("a29k_estimate_size_before_relax\n"));
-  return 0;
-}
-
-#if 0
-/* for debugging only */
-static void
-print_insn (insn)
-     struct machine_it *insn;
-{
-  char *Reloc[] =
-  {
-    "RELOC_8",
-    "RELOC_16",
-    "RELOC_32",
-    "RELOC_DISP8",
-    "RELOC_DISP16",
-    "RELOC_DISP32",
-    "RELOC_WDISP30",
-    "RELOC_WDISP22",
-    "RELOC_HI22",
-    "RELOC_22",
-    "RELOC_13",
-    "RELOC_LO10",
-    "RELOC_SFA_BASE",
-    "RELOC_SFA_OFF13",
-    "RELOC_BASE10",
-    "RELOC_BASE13",
-    "RELOC_BASE22",
-    "RELOC_PC10",
-    "RELOC_PC22",
-    "RELOC_JMP_TBL",
-    "RELOC_SEGOFF16",
-    "RELOC_GLOB_DAT",
-    "RELOC_JMP_SLOT",
-    "RELOC_RELATIVE",
-    "NO_RELOC"
-  };
-
-  if (insn->error)
-    {
-      fprintf (stderr, "ERROR: %s\n");
-    }
-  fprintf (stderr, "opcode=0x%08x\n", insn->opcode);
-  fprintf (stderr, "reloc = %s\n", Reloc[insn->reloc]);
-  fprintf (stderr, "exp =  {\n");
-  fprintf (stderr, "\t\tX_add_symbol = %s\n",
-	   insn->exp.X_add_symbol ?
-	   (S_GET_NAME (insn->exp.X_add_symbol) ?
-	    S_GET_NAME (insn->exp.X_add_symbol) : "???") : "0");
-  fprintf (stderr, "\t\tX_op_symbol = %s\n",
-	   insn->exp.X_op_symbol ?
-	   (S_GET_NAME (insn->exp.X_op_symbol) ?
-	    S_GET_NAME (insn->exp.X_op_symbol) : "???") : "0");
-  fprintf (stderr, "\t\tX_add_number = %d\n",
-	   insn->exp.X_add_number);
-  fprintf (stderr, "}\n");
-}
-
-#endif
-
-/* Translate internal representation of relocation info to target format.
-
-   On sparc/29k: first 4 bytes are normal unsigned long address, next three
-   bytes are index, most sig. byte first.  Byte 7 is broken up with
-   bit 7 as external, bits 6 & 5 unused, and the lower
-   five bits as relocation type.  Next 4 bytes are long addend.  */
-/* Thanx and a tip of the hat to Michael Bloom, mb@ttidca.tti.com */
-
-#ifdef OBJ_AOUT
-
-void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
-{
-  long r_symbolnum;
-
-  know (fixP->fx_r_type < NO_RELOC);
-  know (fixP->fx_addsy != NULL);
-
-  md_number_to_chars (where,
-       fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
-		      4);
-
-  r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
-		 ? S_GET_TYPE (fixP->fx_addsy)
-		 : fixP->fx_addsy->sy_number);
-
-  where[4] = (r_symbolnum >> 16) & 0x0ff;
-  where[5] = (r_symbolnum >> 8) & 0x0ff;
-  where[6] = r_symbolnum & 0x0ff;
-  where[7] = (((!S_IS_DEFINED (fixP->fx_addsy)) << 7) & 0x80) | (0 & 0x60) | (fixP->fx_r_type & 0x1F);
-  /* Also easy */
-  md_number_to_chars (&where[8], fixP->fx_addnumber, 4);
-}
-
-#endif /* OBJ_AOUT */
-
-const char *md_shortopts = "";
-struct option md_longopts[] = {
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
-{
-}
-
-/* This is called when a line is unrecognized.  This is used to handle
-   definitions of a29k style local labels.  */
-
-int
-a29k_unrecognized_line (c)
-     int c;
-{
-  int lab;
-  char *s;
-
-  if (c != '$'
-      || ! ISDIGIT (input_line_pointer[0]))
-    return 0;
-
-  s = input_line_pointer;
-
-  lab = 0;
-  while (ISDIGIT (*s))
-    {
-      lab = lab * 10 + *s - '0';
-      ++s;
-    }
-
-  if (*s != ':')
-    {
-      /* Not a label definition.  */
-      return 0;
-    }
-
-  if (dollar_label_defined (lab))
-    {
-      as_bad (_("label \"$%d\" redefined"), lab);
-      return 0;
-    }
-
-  define_dollar_label (lab);
-  colon (dollar_label_name (lab, 0));
-  input_line_pointer = s + 1;
-
-  return 1;
-}
-
-/* Default the values of symbols known that should be "predefined".  We
-   don't bother to predefine them unless you actually use one, since there
-   are a lot of them.  */
-
-symbolS *
-md_undefined_symbol (name)
-     char *name;
-{
-  long regnum;
-  char testbuf[5 + /*SLOP*/ 5];
-
-  if (name[0] == 'g' || name[0] == 'G'
-      || name[0] == 'l' || name[0] == 'L'
-      || name[0] == 's' || name[0] == 'S')
-    {
-      /* Perhaps a global or local register name */
-      if (name[1] == 'r' || name[1] == 'R')
-	{
-	  long maxreg;
-
-	  /* Parse the number, make sure it has no extra zeroes or
-	     trailing chars.  */
-	  regnum = atol (&name[2]);
-
-	  if (name[0] == 's' || name[0] == 'S')
-	    maxreg = 255;
-	  else
-	    maxreg = 127;
-	  if (regnum > maxreg)
-	    return NULL;
-
-	  sprintf (testbuf, "%ld", regnum);
-	  if (strcmp (testbuf, &name[2]) != 0)
-	    return NULL;	/* gr007 or lr7foo or whatever */
-
-	  /* We have a wiener!  Define and return a new symbol for it.  */
-	  if (name[0] == 'l' || name[0] == 'L')
-	    regnum += 128;
-	  else if (name[0] == 's' || name[0] == 'S')
-	    regnum += SREG;
-	  return (symbol_new (name, SEG_REGISTER, (valueT) regnum,
-			      &zero_address_frag));
-	}
-    }
-
-  return NULL;
-}
-
-/* Parse an operand that is machine-specific.  */
-
-void
-md_operand (expressionP)
-     expressionS *expressionP;
-{
-
-  if (input_line_pointer[0] == '%' && input_line_pointer[1] == '%')
-    {
-      /* We have a numeric register expression.  No biggy.  */
-      input_line_pointer += 2;	/* Skip %% */
-      (void) expression (expressionP);
-      if (expressionP->X_op != O_constant
-	  || expressionP->X_add_number > 255)
-	as_bad (_("Invalid expression after %%%%\n"));
-      expressionP->X_op = O_register;
-    }
-  else if (input_line_pointer[0] == '&')
-    {
-      /* We are taking the 'address' of a register...this one is not
-	 in the manual, but it *is* in traps/fpsymbol.h!  What they
-	 seem to want is the register number, as an absolute number.  */
-      input_line_pointer++;	/* Skip & */
-      (void) expression (expressionP);
-      if (expressionP->X_op != O_register)
-	as_bad (_("Invalid register in & expression"));
-      else
-	expressionP->X_op = O_constant;
-    }
-  else if (input_line_pointer[0] == '$'
-	   && ISDIGIT (input_line_pointer[1]))
-    {
-      long lab;
-      char *name;
-      symbolS *sym;
-
-      /* This is a local label.  */
-      ++input_line_pointer;
-      lab = (long) get_absolute_expression ();
-      if (dollar_label_defined (lab))
-	{
-	  name = dollar_label_name (lab, 0);
-	  sym = symbol_find (name);
-	}
-      else
-	{
-	  name = dollar_label_name (lab, 1);
-	  sym = symbol_find_or_make (name);
-	}
-
-      expressionP->X_op = O_symbol;
-      expressionP->X_add_symbol = sym;
-      expressionP->X_add_number = 0;
-    }
-  else if (input_line_pointer[0] == '$')
-    {
-      char *s;
-      char type;
-      int fieldnum, fieldlimit;
-      LITTLENUM_TYPE floatbuf[8];
-
-      /* $float(), $doubleN(), or $extendN() convert floating values
-	 to integers.  */
-
-      s = input_line_pointer;
-
-      ++s;
-
-      fieldnum = 0;
-      if (strncmp (s, "double", sizeof "double" - 1) == 0)
-	{
-	  s += sizeof "double" - 1;
-	  type = 'd';
-	  fieldlimit = 2;
-	}
-      else if (strncmp (s, "float", sizeof "float" - 1) == 0)
-	{
-	  s += sizeof "float" - 1;
-	  type = 'f';
-	  fieldlimit = 1;
-	}
-      else if (strncmp (s, "extend", sizeof "extend" - 1) == 0)
-	{
-	  s += sizeof "extend" - 1;
-	  type = 'x';
-	  fieldlimit = 4;
-	}
-      else
-	{
-	  return;
-	}
-
-      if (ISDIGIT (*s))
-	{
-	  fieldnum = *s - '0';
-	  ++s;
-	}
-      if (fieldnum >= fieldlimit)
-	return;
-
-      SKIP_WHITESPACE ();
-      if (*s != '(')
-	return;
-      ++s;
-      SKIP_WHITESPACE ();
-
-      s = atof_ieee (s, type, floatbuf);
-      if (s == NULL)
-	return;
-      s = s;
-
-      SKIP_WHITESPACE ();
-      if (*s != ')')
-	return;
-      ++s;
-      SKIP_WHITESPACE ();
-
-      input_line_pointer = s;
-      expressionP->X_op = O_constant;
-      expressionP->X_unsigned = 1;
-      expressionP->X_add_number = ((floatbuf[fieldnum * 2]
-				    << LITTLENUM_NUMBER_OF_BITS)
-				   + floatbuf[fieldnum * 2 + 1]);
-    }
-}
-
-/* Round up a section size to the appropriate boundary.  */
-valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
-{
-  return size;			/* Byte alignment is fine */
-}
-
-/* Exactly what point is a PC-relative offset relative TO?
-   On the 29000, they're relative to the address of the instruction,
-   which we have set up as the address of the fixup too.  */
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  return fixP->fx_where + fixP->fx_frag->fr_address;
-}
diff --git a/gas/config/tc-a29k.h b/gas/config/tc-a29k.h
deleted file mode 100644
index 7f3f1b2425f6..000000000000
--- a/gas/config/tc-a29k.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* tc-a29k.h -- Assemble for the AMD 29000.
-   Copyright 1989, 1990, 1991, 1992, 1993, 1995, 1998
-   Free Software Foundation, Inc.
-
-This file is part of GAS, the GNU Assembler.
-
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GAS is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
-
-#define TC_A29K
-
-#define TARGET_BYTES_BIG_ENDIAN	1
-
-#define WORKING_DOT_WORD
-
-#define LEX_DOLLAR 1
-
-#define tc_unrecognized_line(c) a29k_unrecognized_line (c)
-extern int a29k_unrecognized_line PARAMS ((int));
-
-#define tc_headers_hook(a)		;	/* not used */
-#define tc_headers_hook(a)		;	/* not used */
-#define tc_crawl_symbol_chain(a)	;	/* not used */
-#define tc_coff_symbol_emit_hook(a)	;	/* not used */
-
-#define AOUT_MACHTYPE 101
-#define TC_COFF_FIX2RTYPE(fix_ptr) tc_coff_fix2rtype(fix_ptr)
-#define BFD_ARCH bfd_arch_a29k
-#define COFF_MAGIC SIPFBOMAGIC
-/* Should the reloc be output ?
-	on the 29k, this is true only if there is a symbol attached.
-	on the h8, this is always true, since no fixup is done
-*/
-#define TC_COUNT_RELOC(x) (x->fx_addsy)
-#define TC_CONS_RELOC RELOC_32
-
-#define COFF_FLAGS F_AR32W
-#define reloc_type int
-#define NEED_FX_R_TYPE
-
-#define ZERO_BASED_SEGMENTS
-
-/* end of tc-a29k.h */
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index 93600473ffcf..3765b08c73a5 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -1,6 +1,6 @@
 /* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU.
    Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by Carnegie Mellon University, 1993.
    Written by Alessandro Forin, based on earlier gas-1.38 target CPU files.
    Modified by Ken Raeburn for gas-2.x and ECOFF support.
@@ -21,34 +21,32 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/*
- * Mach Operating System
- * Copyright (c) 1993 Carnegie Mellon University
- * All Rights Reserved.
- *
- * Permission to use, copy, modify and distribute this software and its
- * documentation is hereby granted, provided that both the copyright
- * notice and this permission notice appear in all copies of the
- * software, derivative works or modified versions, and any portions
- * thereof, and that both notices appear in supporting documentation.
- *
- * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
- * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
- * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
- *
- * Carnegie Mellon requests users of this software to return to
- *
- *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
- *  School of Computer Science
- *  Carnegie Mellon University
- *  Pittsburgh PA 15213-3890
- *
- * any improvements or extensions that they make and grant Carnegie the
- * rights to redistribute these changes.
- */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* Mach Operating System
+   Copyright (c) 1993 Carnegie Mellon University
+   All Rights Reserved.
+
+   Permission to use, copy, modify and distribute this software and its
+   documentation is hereby granted, provided that both the copyright
+   notice and this permission notice appear in all copies of the
+   software, derivative works or modified versions, and any portions
+   thereof, and that both notices appear in supporting documentation.
+
+   CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
+   CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
+   ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+
+   Carnegie Mellon requests users of this software to return to
+
+    Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
+    School of Computer Science
+    Carnegie Mellon University
+    Pittsburgh PA 15213-3890
+
+   any improvements or extensions that they make and grant Carnegie the
+   rights to redistribute these changes.  */
 
 #include "as.h"
 #include "subsegs.h"
@@ -60,18 +58,17 @@
 #ifdef OBJ_ELF
 #include "elf/alpha.h"
 #include "dwarf2dbg.h"
-#include "dw2gencfi.h"
 #endif
 
+#include "dw2gencfi.h"
 #include "safe-ctype.h"
 
 /* Local types.  */
 
-#define TOKENIZE_ERROR -1
-#define TOKENIZE_ERROR_REPORT -2
-
-#define MAX_INSN_FIXUPS 2
-#define MAX_INSN_ARGS 5
+#define TOKENIZE_ERROR 		-1
+#define TOKENIZE_ERROR_REPORT	-2
+#define MAX_INSN_FIXUPS		 2
+#define MAX_INSN_ARGS		 5
 
 struct alpha_fixup
 {
@@ -101,39 +98,40 @@ enum alpha_macro_arg
 struct alpha_macro
 {
   const char *name;
-  void (*emit) PARAMS ((const expressionS *, int, const PTR));
-  const PTR arg;
+  void (*emit) (const expressionS *, int, const void *);
+  const void * arg;
   enum alpha_macro_arg argsets[16];
 };
 
 /* Extra expression types.  */
 
-#define O_pregister	O_md1	/* O_register, in parentheses */
-#define O_cpregister	O_md2	/* + a leading comma */
+#define O_pregister	O_md1	/* O_register, in parentheses.  */
+#define O_cpregister	O_md2	/* + a leading comma.  */
 
 /* The alpha_reloc_op table below depends on the ordering of these.  */
-#define O_literal	O_md3	/* !literal relocation */
-#define O_lituse_addr	O_md4	/* !lituse_addr relocation */
-#define O_lituse_base	O_md5	/* !lituse_base relocation */
-#define O_lituse_bytoff	O_md6	/* !lituse_bytoff relocation */
-#define O_lituse_jsr	O_md7	/* !lituse_jsr relocation */
-#define O_lituse_tlsgd	O_md8	/* !lituse_tlsgd relocation */
-#define O_lituse_tlsldm	O_md9	/* !lituse_tlsldm relocation */
-#define O_gpdisp	O_md10	/* !gpdisp relocation */
-#define O_gprelhigh	O_md11	/* !gprelhigh relocation */
-#define O_gprellow	O_md12	/* !gprellow relocation */
-#define O_gprel		O_md13	/* !gprel relocation */
-#define O_samegp	O_md14	/* !samegp relocation */
-#define O_tlsgd		O_md15	/* !tlsgd relocation */
-#define O_tlsldm	O_md16	/* !tlsldm relocation */
-#define O_gotdtprel	O_md17	/* !gotdtprel relocation */
-#define O_dtprelhi	O_md18	/* !dtprelhi relocation */
-#define O_dtprello	O_md19	/* !dtprello relocation */
-#define O_dtprel	O_md20	/* !dtprel relocation */
-#define O_gottprel	O_md21	/* !gottprel relocation */
-#define O_tprelhi	O_md22	/* !tprelhi relocation */
-#define O_tprello	O_md23	/* !tprello relocation */
-#define O_tprel		O_md24	/* !tprel relocation */
+#define O_literal	O_md3		/* !literal relocation.  */
+#define O_lituse_addr	O_md4		/* !lituse_addr relocation.  */
+#define O_lituse_base	O_md5		/* !lituse_base relocation.  */
+#define O_lituse_bytoff	O_md6		/* !lituse_bytoff relocation.  */
+#define O_lituse_jsr	O_md7		/* !lituse_jsr relocation.  */
+#define O_lituse_tlsgd	O_md8		/* !lituse_tlsgd relocation.  */
+#define O_lituse_tlsldm	O_md9		/* !lituse_tlsldm relocation.  */
+#define O_lituse_jsrdirect O_md10	/* !lituse_jsrdirect relocation.  */
+#define O_gpdisp	O_md11		/* !gpdisp relocation.  */
+#define O_gprelhigh	O_md12		/* !gprelhigh relocation.  */
+#define O_gprellow	O_md13		/* !gprellow relocation.  */
+#define O_gprel		O_md14		/* !gprel relocation.  */
+#define O_samegp	O_md15		/* !samegp relocation.  */
+#define O_tlsgd		O_md16		/* !tlsgd relocation.  */
+#define O_tlsldm	O_md17		/* !tlsldm relocation.  */
+#define O_gotdtprel	O_md18		/* !gotdtprel relocation.  */
+#define O_dtprelhi	O_md19		/* !dtprelhi relocation.  */
+#define O_dtprello	O_md20		/* !dtprello relocation.  */
+#define O_dtprel	O_md21		/* !dtprel relocation.  */
+#define O_gottprel	O_md22		/* !gottprel relocation.  */
+#define O_tprelhi	O_md23		/* !tprelhi relocation.  */
+#define O_tprello	O_md24		/* !tprello relocation.  */
+#define O_tprel		O_md25		/* !tprel relocation.  */
 
 #define DUMMY_RELOC_LITUSE_ADDR		(BFD_RELOC_UNUSED + 1)
 #define DUMMY_RELOC_LITUSE_BASE		(BFD_RELOC_UNUSED + 2)
@@ -141,6 +139,7 @@ struct alpha_macro
 #define DUMMY_RELOC_LITUSE_JSR		(BFD_RELOC_UNUSED + 4)
 #define DUMMY_RELOC_LITUSE_TLSGD	(BFD_RELOC_UNUSED + 5)
 #define DUMMY_RELOC_LITUSE_TLSLDM	(BFD_RELOC_UNUSED + 6)
+#define DUMMY_RELOC_LITUSE_JSRDIRECT	(BFD_RELOC_UNUSED + 7)
 
 #define USER_RELOC_P(R) ((R) >= O_literal && (R) <= O_tprel)
 
@@ -206,89 +205,6 @@ struct alpha_macro
 				 (t).X_op = O_constant,			\
 				 (t).X_add_number = (n))
 
-/* Prototypes for all local functions.  */
-
-static struct alpha_reloc_tag *get_alpha_reloc_tag PARAMS ((long));
-static void alpha_adjust_relocs PARAMS ((bfd *, asection *, PTR));
-
-static int tokenize_arguments PARAMS ((char *, expressionS *, int));
-static const struct alpha_opcode *find_opcode_match
-  PARAMS ((const struct alpha_opcode *, const expressionS *, int *, int *));
-static const struct alpha_macro *find_macro_match
-  PARAMS ((const struct alpha_macro *, const expressionS *, int *));
-static unsigned insert_operand
-  PARAMS ((unsigned, const struct alpha_operand *, offsetT, char *, unsigned));
-static void assemble_insn
-  PARAMS ((const struct alpha_opcode *, const expressionS *, int,
-	   struct alpha_insn *, bfd_reloc_code_real_type));
-static void emit_insn PARAMS ((struct alpha_insn *));
-static void assemble_tokens_to_insn
-  PARAMS ((const char *, const expressionS *, int, struct alpha_insn *));
-static void assemble_tokens
-  PARAMS ((const char *, const expressionS *, int, int));
-
-static long load_expression
-  PARAMS ((int, const expressionS *, int *, expressionS *));
-
-static void emit_ldgp PARAMS ((const expressionS *, int, const PTR));
-static void emit_division PARAMS ((const expressionS *, int, const PTR));
-static void emit_lda PARAMS ((const expressionS *, int, const PTR));
-static void emit_ldah PARAMS ((const expressionS *, int, const PTR));
-static void emit_ir_load PARAMS ((const expressionS *, int, const PTR));
-static void emit_loadstore PARAMS ((const expressionS *, int, const PTR));
-static void emit_jsrjmp PARAMS ((const expressionS *, int, const PTR));
-static void emit_ldX PARAMS ((const expressionS *, int, const PTR));
-static void emit_ldXu PARAMS ((const expressionS *, int, const PTR));
-static void emit_uldX PARAMS ((const expressionS *, int, const PTR));
-static void emit_uldXu PARAMS ((const expressionS *, int, const PTR));
-static void emit_ldil PARAMS ((const expressionS *, int, const PTR));
-static void emit_stX PARAMS ((const expressionS *, int, const PTR));
-static void emit_ustX PARAMS ((const expressionS *, int, const PTR));
-static void emit_sextX PARAMS ((const expressionS *, int, const PTR));
-static void emit_retjcr PARAMS ((const expressionS *, int, const PTR));
-
-static void s_alpha_text PARAMS ((int));
-static void s_alpha_data PARAMS ((int));
-#ifndef OBJ_ELF
-static void s_alpha_comm PARAMS ((int));
-static void s_alpha_rdata PARAMS ((int));
-#endif
-#ifdef OBJ_ECOFF
-static void s_alpha_sdata PARAMS ((int));
-#endif
-#ifdef OBJ_ELF
-static void s_alpha_section PARAMS ((int));
-static void s_alpha_ent PARAMS ((int));
-static void s_alpha_end PARAMS ((int));
-static void s_alpha_mask PARAMS ((int));
-static void s_alpha_frame PARAMS ((int));
-static void s_alpha_prologue PARAMS ((int));
-static void s_alpha_file PARAMS ((int));
-static void s_alpha_loc PARAMS ((int));
-static void s_alpha_stab PARAMS ((int));
-static void s_alpha_coff_wrapper PARAMS ((int));
-static void s_alpha_usepv PARAMS ((int));
-#endif
-#ifdef OBJ_EVAX
-static void s_alpha_section PARAMS ((int));
-#endif
-static void s_alpha_gprel32 PARAMS ((int));
-static void s_alpha_float_cons PARAMS ((int));
-static void s_alpha_proc PARAMS ((int));
-static void s_alpha_set PARAMS ((int));
-static void s_alpha_base PARAMS ((int));
-static void s_alpha_align PARAMS ((int));
-static void s_alpha_stringer PARAMS ((int));
-static void s_alpha_space PARAMS ((int));
-static void s_alpha_ucons PARAMS ((int));
-static void s_alpha_arch PARAMS ((int));
-
-static void create_literal_section PARAMS ((const char *, segT *, symbolS **));
-#ifndef OBJ_ELF
-static void select_gp_value PARAMS ((void));
-#endif
-static void alpha_align PARAMS ((int, char *, symbolS *, int));
-
 /* Generic assembler global variables which must be defined by all
    targets.  */
 
@@ -308,12 +224,8 @@ const char EXP_CHARS[] = "eE";
 
 /* Characters which mean that a number is a floating point constant,
    as in 0d1.0.  */
-#if 0
-const char FLT_CHARS[] = "dD";
-#else
 /* XXX: Do all of these really get used on the alpha??  */
 char FLT_CHARS[] = "rRsSfFdDxXpP";
-#endif
 
 #ifdef OBJ_EVAX
 const char *md_shortopts = "Fm:g+1h:HG:";
@@ -454,11 +366,12 @@ static int g_switch_value = 8;
 
 #ifdef OBJ_EVAX
 /* Collect information about current procedure here.  */
-static struct {
-  symbolS *symbol;	/* proc pdesc symbol */
+static struct
+{
+  symbolS *symbol;	/* Proc pdesc symbol.  */
   int pdsckind;
-  int framereg;		/* register for frame pointer */
-  int framesize;	/* size of frame */
+  int framereg;		/* Register for frame pointer.  */
+  int framesize;	/* Size of frame.  */
   int rsa_offset;
   int ra_save;
   int fp_save;
@@ -491,37 +404,38 @@ static int alpha_flag_show_after_trunc = 0;		/* -H */
 
 static const struct alpha_reloc_op_tag
 {
-  const char *name;				/* string to lookup */
-  size_t length;				/* size of the string */
-  operatorT op;					/* which operator to use */
-  bfd_reloc_code_real_type reloc;		/* relocation before frob */
-  unsigned int require_seq : 1;			/* require a sequence number */
-  unsigned int allow_seq : 1;			/* allow a sequence number */
+  const char *name;				/* String to lookup.  */
+  size_t length;				/* Size of the string.  */
+  operatorT op;					/* Which operator to use.  */
+  bfd_reloc_code_real_type reloc;		/* Relocation before frob.  */
+  unsigned int require_seq : 1;			/* Require a sequence number.  */
+  unsigned int allow_seq : 1;			/* Allow a sequence number.  */
 }
 alpha_reloc_op[] =
 {
-  DEF(literal, BFD_RELOC_ALPHA_ELF_LITERAL, 0, 1),
-  DEF(lituse_addr, DUMMY_RELOC_LITUSE_ADDR, 1, 1),
-  DEF(lituse_base, DUMMY_RELOC_LITUSE_BASE, 1, 1),
-  DEF(lituse_bytoff, DUMMY_RELOC_LITUSE_BYTOFF, 1, 1),
-  DEF(lituse_jsr, DUMMY_RELOC_LITUSE_JSR, 1, 1),
-  DEF(lituse_tlsgd, DUMMY_RELOC_LITUSE_TLSGD, 1, 1),
-  DEF(lituse_tlsldm, DUMMY_RELOC_LITUSE_TLSLDM, 1, 1),
-  DEF(gpdisp, BFD_RELOC_ALPHA_GPDISP, 1, 1),
-  DEF(gprelhigh, BFD_RELOC_ALPHA_GPREL_HI16, 0, 0),
-  DEF(gprellow, BFD_RELOC_ALPHA_GPREL_LO16, 0, 0),
-  DEF(gprel, BFD_RELOC_GPREL16, 0, 0),
-  DEF(samegp, BFD_RELOC_ALPHA_BRSGP, 0, 0),
-  DEF(tlsgd, BFD_RELOC_ALPHA_TLSGD, 0, 1),
-  DEF(tlsldm, BFD_RELOC_ALPHA_TLSLDM, 0, 1),
-  DEF(gotdtprel, BFD_RELOC_ALPHA_GOTDTPREL16, 0, 0),
-  DEF(dtprelhi, BFD_RELOC_ALPHA_DTPREL_HI16, 0, 0),
-  DEF(dtprello, BFD_RELOC_ALPHA_DTPREL_LO16, 0, 0),
-  DEF(dtprel, BFD_RELOC_ALPHA_DTPREL16, 0, 0),
-  DEF(gottprel, BFD_RELOC_ALPHA_GOTTPREL16, 0, 0),
-  DEF(tprelhi, BFD_RELOC_ALPHA_TPREL_HI16, 0, 0),
-  DEF(tprello, BFD_RELOC_ALPHA_TPREL_LO16, 0, 0),
-  DEF(tprel, BFD_RELOC_ALPHA_TPREL16, 0, 0),
+  DEF (literal, BFD_RELOC_ALPHA_ELF_LITERAL, 0, 1),
+  DEF (lituse_addr, DUMMY_RELOC_LITUSE_ADDR, 1, 1),
+  DEF (lituse_base, DUMMY_RELOC_LITUSE_BASE, 1, 1),
+  DEF (lituse_bytoff, DUMMY_RELOC_LITUSE_BYTOFF, 1, 1),
+  DEF (lituse_jsr, DUMMY_RELOC_LITUSE_JSR, 1, 1),
+  DEF (lituse_tlsgd, DUMMY_RELOC_LITUSE_TLSGD, 1, 1),
+  DEF (lituse_tlsldm, DUMMY_RELOC_LITUSE_TLSLDM, 1, 1),
+  DEF (lituse_jsrdirect, DUMMY_RELOC_LITUSE_JSRDIRECT, 1, 1),
+  DEF (gpdisp, BFD_RELOC_ALPHA_GPDISP, 1, 1),
+  DEF (gprelhigh, BFD_RELOC_ALPHA_GPREL_HI16, 0, 0),
+  DEF (gprellow, BFD_RELOC_ALPHA_GPREL_LO16, 0, 0),
+  DEF (gprel, BFD_RELOC_GPREL16, 0, 0),
+  DEF (samegp, BFD_RELOC_ALPHA_BRSGP, 0, 0),
+  DEF (tlsgd, BFD_RELOC_ALPHA_TLSGD, 0, 1),
+  DEF (tlsldm, BFD_RELOC_ALPHA_TLSLDM, 0, 1),
+  DEF (gotdtprel, BFD_RELOC_ALPHA_GOTDTPREL16, 0, 0),
+  DEF (dtprelhi, BFD_RELOC_ALPHA_DTPREL_HI16, 0, 0),
+  DEF (dtprello, BFD_RELOC_ALPHA_DTPREL_LO16, 0, 0),
+  DEF (dtprel, BFD_RELOC_ALPHA_DTPREL16, 0, 0),
+  DEF (gottprel, BFD_RELOC_ALPHA_GOTTPREL16, 0, 0),
+  DEF (tprelhi, BFD_RELOC_ALPHA_TPREL_HI16, 0, 0),
+  DEF (tprello, BFD_RELOC_ALPHA_TPREL_LO16, 0, 0),
+  DEF (tprel, BFD_RELOC_ALPHA_TPREL16, 0, 0),
 };
 
 #undef DEF
@@ -530,27 +444,27 @@ static const int alpha_num_reloc_op
   = sizeof (alpha_reloc_op) / sizeof (*alpha_reloc_op);
 #endif /* RELOC_OP_P */
 
-/* Maximum # digits needed to hold the largest sequence # */
+/* Maximum # digits needed to hold the largest sequence #.  */
 #define ALPHA_RELOC_DIGITS 25
 
 /* Structure to hold explicit sequence information.  */
 struct alpha_reloc_tag
 {
-  fixS *master;			/* the literal reloc */
-  fixS *slaves;			/* head of linked list of lituses */
-  segT segment;			/* segment relocs are in or undefined_section*/
-  long sequence;		/* sequence # */
-  unsigned n_master;		/* # of literals */
-  unsigned n_slaves;		/* # of lituses */
-  unsigned saw_tlsgd : 1;	/* true if ... */
+  fixS *master;			/* The literal reloc.  */
+  fixS *slaves;			/* Head of linked list of lituses.  */
+  segT segment;			/* Segment relocs are in or undefined_section.  */
+  long sequence;		/* Sequence #.  */
+  unsigned n_master;		/* # of literals.  */
+  unsigned n_slaves;		/* # of lituses.  */
+  unsigned saw_tlsgd : 1;	/* True if ...  */
   unsigned saw_tlsldm : 1;
   unsigned saw_lu_tlsgd : 1;
   unsigned saw_lu_tlsldm : 1;
-  unsigned multi_section_p : 1;	/* true if more than one section was used */
-  char string[1];		/* printable form of sequence to hash with */
+  unsigned multi_section_p : 1;	/* True if more than one section was used.  */
+  char string[1];		/* Printable form of sequence to hash with.  */
 };
 
-/* Hash table to link up literals with the appropriate lituse */
+/* Hash table to link up literals with the appropriate lituse.  */
 static struct hash_control *alpha_literal_hash;
 
 /* Sequence numbers for internal use by macros.  */
@@ -599,1075 +513,23 @@ cpu_types[] =
   { 0, 0 }
 };
 
-/* The macro table */
-
-static const struct alpha_macro alpha_macros[] =
-{
-/* Load/Store macros */
-  { "lda",	emit_lda, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldah",	emit_ldah, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
-
-  { "ldl",	emit_ir_load, "ldl",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldl_l",	emit_ir_load, "ldl_l",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldq",	emit_ir_load, "ldq",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldq_l",	emit_ir_load, "ldq_l",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldq_u",	emit_ir_load, "ldq_u",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldf",	emit_loadstore, "ldf",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldg",	emit_loadstore, "ldg",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "lds",	emit_loadstore, "lds",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldt",	emit_loadstore, "ldt",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-
-  { "ldb",	emit_ldX, (PTR) 0,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldbu",	emit_ldXu, (PTR) 0,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldw",	emit_ldX, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ldwu",	emit_ldXu, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-
-  { "uldw",	emit_uldX, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "uldwu",	emit_uldXu, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "uldl",	emit_uldX, (PTR) 2,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "uldlu",	emit_uldXu, (PTR) 2,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "uldq",	emit_uldXu, (PTR) 3,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-
-  { "ldgp",	emit_ldgp, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_PIR, MACRO_EOA } },
-
-  { "ldi",	emit_lda, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
-  { "ldil",	emit_ldil, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
-  { "ldiq",	emit_lda, NULL,
-    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
-#if 0
-  { "ldif"	emit_ldiq, NULL,
-    { MACRO_FPR, MACRO_EXP, MACRO_EOA } },
-  { "ldid"	emit_ldiq, NULL,
-    { MACRO_FPR, MACRO_EXP, MACRO_EOA } },
-  { "ldig"	emit_ldiq, NULL,
-    { MACRO_FPR, MACRO_EXP, MACRO_EOA } },
-  { "ldis"	emit_ldiq, NULL,
-    { MACRO_FPR, MACRO_EXP, MACRO_EOA } },
-  { "ldit"	emit_ldiq, NULL,
-    { MACRO_FPR, MACRO_EXP, MACRO_EOA } },
-#endif
-
-  { "stl",	emit_loadstore, "stl",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stl_c",	emit_loadstore, "stl_c",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stq",	emit_loadstore, "stq",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stq_c",	emit_loadstore, "stq_c",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stq_u",	emit_loadstore, "stq_u",
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stf",	emit_loadstore, "stf",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stg",	emit_loadstore, "stg",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "sts",	emit_loadstore, "sts",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stt",	emit_loadstore, "stt",
-    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-
-  { "stb",	emit_stX, (PTR) 0,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "stw",	emit_stX, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ustw",	emit_ustX, (PTR) 1,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ustl",	emit_ustX, (PTR) 2,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-  { "ustq",	emit_ustX, (PTR) 3,
-    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
-
-/* Arithmetic macros */
-#if 0
-  { "absl"	emit_absl, 1, { IR } },
-  { "absl"	emit_absl, 2, { IR, IR } },
-  { "absl"	emit_absl, 2, { EXP, IR } },
-  { "absq"	emit_absq, 1, { IR } },
-  { "absq"	emit_absq, 2, { IR, IR } },
-  { "absq"	emit_absq, 2, { EXP, IR } },
-#endif
-
-  { "sextb",	emit_sextX, (PTR) 0,
-    { MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EOA,
-      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },
-  { "sextw",	emit_sextX, (PTR) 1,
-    { MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EOA,
-      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },
-
-  { "divl",	emit_division, "__divl",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "divlu",	emit_division, "__divlu",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "divq",	emit_division, "__divq",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "divqu",	emit_division, "__divqu",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "reml",	emit_division, "__reml",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "remlu",	emit_division, "__remlu",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "remq",	emit_division, "__remq",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-  { "remqu",	emit_division, "__remqu",
-    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_IR, MACRO_EOA,
-      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
-      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
-
-  { "jsr",	emit_jsrjmp, "jsr",
-    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
-      MACRO_PIR, MACRO_EOA,
-      MACRO_IR,  MACRO_EXP, MACRO_EOA,
-      MACRO_EXP, MACRO_EOA } },
-  { "jmp",	emit_jsrjmp, "jmp",
-    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
-      MACRO_PIR, MACRO_EOA,
-      MACRO_IR,  MACRO_EXP, MACRO_EOA,
-      MACRO_EXP, MACRO_EOA } },
-  { "ret",	emit_retjcr, "ret",
-    { MACRO_IR, MACRO_EXP, MACRO_EOA,
-      MACRO_IR, MACRO_EOA,
-      MACRO_PIR, MACRO_EXP, MACRO_EOA,
-      MACRO_PIR, MACRO_EOA,
-      MACRO_EXP, MACRO_EOA,
-      MACRO_EOA } },
-  { "jcr",	emit_retjcr, "jcr",
-    { MACRO_IR, MACRO_EXP, MACRO_EOA,
-      MACRO_IR, MACRO_EOA,
-      MACRO_PIR, MACRO_EXP, MACRO_EOA,
-      MACRO_PIR, MACRO_EOA,
-      MACRO_EXP, MACRO_EOA,
-      MACRO_EOA } },
-  { "jsr_coroutine",	emit_retjcr, "jcr",
-    { MACRO_IR, MACRO_EXP, MACRO_EOA,
-      MACRO_IR, MACRO_EOA,
-      MACRO_PIR, MACRO_EXP, MACRO_EOA,
-      MACRO_PIR, MACRO_EOA,
-      MACRO_EXP, MACRO_EOA,
-      MACRO_EOA } },
-};
-
-static const unsigned int alpha_num_macros
-  = sizeof (alpha_macros) / sizeof (*alpha_macros);
-
-/* Public interface functions */
-
-/* This function is called once, at assembler startup time.  It sets
-   up all the tables, etc. that the MD part of the assembler will
-   need, that can be determined before arguments are parsed.  */
-
-void
-md_begin ()
-{
-  unsigned int i;
-
-  /* Verify that X_op field is wide enough.  */
-  {
-    expressionS e;
-    e.X_op = O_max;
-    assert (e.X_op == O_max);
-  }
-
-  /* Create the opcode hash table.  */
-  alpha_opcode_hash = hash_new ();
-  for (i = 0; i < alpha_num_opcodes;)
-    {
-      const char *name, *retval, *slash;
-
-      name = alpha_opcodes[i].name;
-      retval = hash_insert (alpha_opcode_hash, name, (PTR) &alpha_opcodes[i]);
-      if (retval)
-	as_fatal (_("internal error: can't hash opcode `%s': %s"),
-		  name, retval);
-
-      /* Some opcodes include modifiers of various sorts with a "/mod"
-	 syntax, like the architecture manual suggests.  However, for
-	 use with gcc at least, we also need access to those same opcodes
-	 without the "/".  */
-
-      if ((slash = strchr (name, '/')) != NULL)
-	{
-	  char *p = xmalloc (strlen (name));
-	  memcpy (p, name, slash - name);
-	  strcpy (p + (slash - name), slash + 1);
-
-	  (void) hash_insert (alpha_opcode_hash, p, (PTR) &alpha_opcodes[i]);
-	  /* Ignore failures -- the opcode table does duplicate some
-	     variants in different forms, like "hw_stq" and "hw_st/q".  */
-	}
-
-      while (++i < alpha_num_opcodes
-	     && (alpha_opcodes[i].name == name
-		 || !strcmp (alpha_opcodes[i].name, name)))
-	continue;
-    }
-
-  /* Create the macro hash table.  */
-  alpha_macro_hash = hash_new ();
-  for (i = 0; i < alpha_num_macros;)
-    {
-      const char *name, *retval;
-
-      name = alpha_macros[i].name;
-      retval = hash_insert (alpha_macro_hash, name, (PTR) &alpha_macros[i]);
-      if (retval)
-	as_fatal (_("internal error: can't hash macro `%s': %s"),
-		  name, retval);
-
-      while (++i < alpha_num_macros
-	     && (alpha_macros[i].name == name
-		 || !strcmp (alpha_macros[i].name, name)))
-	continue;
-    }
-
-  /* Construct symbols for each of the registers.  */
-  for (i = 0; i < 32; ++i)
-    {
-      char name[4];
-
-      sprintf (name, "$%d", i);
-      alpha_register_table[i] = symbol_create (name, reg_section, i,
-					       &zero_address_frag);
-    }
-  for (; i < 64; ++i)
-    {
-      char name[5];
-
-      sprintf (name, "$f%d", i - 32);
-      alpha_register_table[i] = symbol_create (name, reg_section, i,
-					       &zero_address_frag);
-    }
-
-  /* Create the special symbols and sections we'll be using.  */
-
-  /* So .sbss will get used for tiny objects.  */
-  bfd_set_gp_size (stdoutput, g_switch_value);
-
-#ifdef OBJ_ECOFF
-  create_literal_section (".lita", &alpha_lita_section, &alpha_lita_symbol);
-
-  /* For handling the GP, create a symbol that won't be output in the
-     symbol table.  We'll edit it out of relocs later.  */
-  alpha_gp_symbol = symbol_create ("<GP value>", alpha_lita_section, 0x8000,
-				   &zero_address_frag);
-#endif
-
-#ifdef OBJ_EVAX
-  create_literal_section (".link", &alpha_link_section, &alpha_link_symbol);
-#endif
-
-#ifdef OBJ_ELF
-  if (ECOFF_DEBUGGING)
-    {
-      segT sec = subseg_new (".mdebug", (subsegT) 0);
-      bfd_set_section_flags (stdoutput, sec, SEC_HAS_CONTENTS | SEC_READONLY);
-      bfd_set_section_alignment (stdoutput, sec, 3);
-    }
-#endif /* OBJ_ELF */
-
-  /* Create literal lookup hash table.  */
-  alpha_literal_hash = hash_new ();
-
-  subseg_set (text_section, 0);
-}
-
-/* The public interface to the instruction assembler.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  char opname[32];			/* Current maximum is 13.  */
-  expressionS tok[MAX_INSN_ARGS];
-  int ntok, trunclen;
-  size_t opnamelen;
-
-  /* Split off the opcode.  */
-  opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/46819");
-  trunclen = (opnamelen < sizeof (opname) - 1
-	      ? opnamelen
-	      : sizeof (opname) - 1);
-  memcpy (opname, str, trunclen);
-  opname[trunclen] = '\0';
-
-  /* Tokenize the rest of the line.  */
-  if ((ntok = tokenize_arguments (str + opnamelen, tok, MAX_INSN_ARGS)) < 0)
-    {
-      if (ntok != TOKENIZE_ERROR_REPORT)
-	as_bad (_("syntax error"));
-
-      return;
-    }
-
-  /* Finish it off.  */
-  assemble_tokens (opname, tok, ntok, alpha_macros_on);
-}
-
-/* Round up a section's size to the appropriate boundary.  */
-
-valueT
-md_section_align (seg, size)
-     segT seg;
-     valueT size;
-{
-  int align = bfd_get_section_alignment (stdoutput, seg);
-  valueT mask = ((valueT) 1 << align) - 1;
-
-  return (size + mask) & ~mask;
-}
-
-/* Turn a string in input_line_pointer into a floating point constant
-   of type TYPE, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.  */
-
-/* Equal to MAX_PRECISION in atof-ieee.c.  */
-#define MAX_LITTLENUMS 6
-
-extern char *vax_md_atof PARAMS ((int, char *, int *));
-
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-      /* VAX floats */
-    case 'G':
-      /* VAX md_atof doesn't like "G" for some reason.  */
-      type = 'g';
-    case 'F':
-    case 'D':
-      return vax_md_atof (type, litP, sizeP);
-
-      /* IEEE floats */
-    case 'f':
-      prec = 2;
-      break;
-
-    case 'd':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to MD_ATOF()");
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-
-  for (wordP = words + prec - 1; prec--;)
-    {
-      md_number_to_chars (litP, (long) (*wordP--), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-
-  return 0;
-}
-
-/* Take care of the target-specific command-line options.  */
-
-int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
-{
-  switch (c)
-    {
-    case 'F':
-      alpha_nofloats_on = 1;
-      break;
-
-    case OPTION_32ADDR:
-      alpha_addr32_on = 1;
-      break;
-
-    case 'g':
-      alpha_debug = 1;
-      break;
-
-    case 'G':
-      g_switch_value = atoi (arg);
-      break;
-
-    case 'm':
-      {
-	const struct cpu_type *p;
-	for (p = cpu_types; p->name; ++p)
-	  if (strcmp (arg, p->name) == 0)
-	    {
-	      alpha_target_name = p->name, alpha_target = p->flags;
-	      goto found;
-	    }
-	as_warn (_("Unknown CPU identifier `%s'"), arg);
-      found:;
-      }
-      break;
-
-#ifdef OBJ_EVAX
-    case '+':			/* For g++.  Hash any name > 63 chars long.  */
-      alpha_flag_hash_long_names = 1;
-      break;
-
-    case 'H':			/* Show new symbol after hash truncation */
-      alpha_flag_show_after_trunc = 1;
-      break;
-
-    case 'h':			/* for gnu-c/vax compatibility.  */
-      break;
-#endif
-
-    case OPTION_RELAX:
-      alpha_flag_relax = 1;
-      break;
-
-#ifdef OBJ_ELF
-    case OPTION_MDEBUG:
-      alpha_flag_mdebug = 1;
-      break;
-    case OPTION_NO_MDEBUG:
-      alpha_flag_mdebug = 0;
-      break;
-#endif
-
-    default:
-      return 0;
-    }
-
-  return 1;
-}
-
-/* Print a description of the command-line options that we accept.  */
-
-void
-md_show_usage (stream)
-     FILE *stream;
-{
-  fputs (_("\
-Alpha options:\n\
--32addr			treat addresses as 32-bit values\n\
--F			lack floating point instructions support\n\
--mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n\
-			specify variant of Alpha architecture\n\
--m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n\
-			these variants include PALcode opcodes\n"),
-	stream);
-#ifdef OBJ_EVAX
-  fputs (_("\
-VMS options:\n\
--+			hash encode (don't truncate) names longer than 64 characters\n\
--H			show new symbol after hash truncation\n"),
-	stream);
-#endif
-}
-
-/* Decide from what point a pc-relative relocation is relative to,
-   relative to the pc-relative fixup.  Er, relatively speaking.  */
-
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
-  switch (fixP->fx_r_type)
-    {
-    case BFD_RELOC_23_PCREL_S2:
-    case BFD_RELOC_ALPHA_HINT:
-    case BFD_RELOC_ALPHA_BRSGP:
-      return addr + 4;
-    default:
-      return addr;
-    }
-}
-
-/* Attempt to simplify or even eliminate a fixup.  The return value is
-   ignored; perhaps it was once meaningful, but now it is historical.
-   To indicate that a fixup has been eliminated, set fixP->fx_done.
-
-   For ELF, here it is that we transform the GPDISP_HI16 reloc we used
-   internally into the GPDISP reloc used externally.  We had to do
-   this so that we'd have the GPDISP_LO16 reloc as a tag to compute
-   the distance to the "lda" instruction for setting the addend to
-   GPDISP.  */
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg;
-{
-  char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
-  valueT value = * valP;
-  unsigned image, size;
-
-  switch (fixP->fx_r_type)
-    {
-      /* The GPDISP relocations are processed internally with a symbol
-	 referring to the current function's section;  we need to drop
-	 in a value which, when added to the address of the start of
-	 the function, gives the desired GP.  */
-    case BFD_RELOC_ALPHA_GPDISP_HI16:
-      {
-	fixS *next = fixP->fx_next;
-
-	/* With user-specified !gpdisp relocations, we can be missing
-	   the matching LO16 reloc.  We will have already issued an
-	   error message.  */
-	if (next)
-	  fixP->fx_offset = (next->fx_frag->fr_address + next->fx_where
-			     - fixP->fx_frag->fr_address - fixP->fx_where);
-
-	value = (value - sign_extend_16 (value)) >> 16;
-      }
-#ifdef OBJ_ELF
-      fixP->fx_r_type = BFD_RELOC_ALPHA_GPDISP;
-#endif
-      goto do_reloc_gp;
-
-    case BFD_RELOC_ALPHA_GPDISP_LO16:
-      value = sign_extend_16 (value);
-      fixP->fx_offset = 0;
-#ifdef OBJ_ELF
-      fixP->fx_done = 1;
-#endif
-
-    do_reloc_gp:
-      fixP->fx_addsy = section_symbol (seg);
-      md_number_to_chars (fixpos, value, 2);
-      break;
-
-    case BFD_RELOC_16:
-      if (fixP->fx_pcrel)
-	fixP->fx_r_type = BFD_RELOC_16_PCREL;
-      size = 2;
-      goto do_reloc_xx;
-    case BFD_RELOC_32:
-      if (fixP->fx_pcrel)
-	fixP->fx_r_type = BFD_RELOC_32_PCREL;
-      size = 4;
-      goto do_reloc_xx;
-    case BFD_RELOC_64:
-      if (fixP->fx_pcrel)
-	fixP->fx_r_type = BFD_RELOC_64_PCREL;
-      size = 8;
-    do_reloc_xx:
-      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
-	{
-	  md_number_to_chars (fixpos, value, size);
-	  goto done;
-	}
-      return;
-
-#ifdef OBJ_ECOFF
-    case BFD_RELOC_GPREL32:
-      assert (fixP->fx_subsy == alpha_gp_symbol);
-      fixP->fx_subsy = 0;
-      /* FIXME: inherited this obliviousness of `value' -- why? */
-      md_number_to_chars (fixpos, -alpha_gp_value, 4);
-      break;
-#else
-    case BFD_RELOC_GPREL32:
-#endif
-    case BFD_RELOC_GPREL16:
-    case BFD_RELOC_ALPHA_GPREL_HI16:
-    case BFD_RELOC_ALPHA_GPREL_LO16:
-      return;
-
-    case BFD_RELOC_23_PCREL_S2:
-      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
-	{
-	  image = bfd_getl32 (fixpos);
-	  image = (image & ~0x1FFFFF) | ((value >> 2) & 0x1FFFFF);
-	  goto write_done;
-	}
-      return;
-
-    case BFD_RELOC_ALPHA_HINT:
-      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
-	{
-	  image = bfd_getl32 (fixpos);
-	  image = (image & ~0x3FFF) | ((value >> 2) & 0x3FFF);
-	  goto write_done;
-	}
-      return;
-
-#ifdef OBJ_ELF
-    case BFD_RELOC_ALPHA_BRSGP:
-      return;
-
-    case BFD_RELOC_ALPHA_TLSGD:
-    case BFD_RELOC_ALPHA_TLSLDM:
-    case BFD_RELOC_ALPHA_GOTDTPREL16:
-    case BFD_RELOC_ALPHA_DTPREL_HI16:
-    case BFD_RELOC_ALPHA_DTPREL_LO16:
-    case BFD_RELOC_ALPHA_DTPREL16:
-    case BFD_RELOC_ALPHA_GOTTPREL16:
-    case BFD_RELOC_ALPHA_TPREL_HI16:
-    case BFD_RELOC_ALPHA_TPREL_LO16:
-    case BFD_RELOC_ALPHA_TPREL16:
-      if (fixP->fx_addsy)
-	S_SET_THREAD_LOCAL (fixP->fx_addsy);
-      return;
-#endif
-
-#ifdef OBJ_ECOFF
-    case BFD_RELOC_ALPHA_LITERAL:
-      md_number_to_chars (fixpos, value, 2);
-      return;
-#endif
-    case BFD_RELOC_ALPHA_ELF_LITERAL:
-    case BFD_RELOC_ALPHA_LITUSE:
-    case BFD_RELOC_ALPHA_LINKAGE:
-    case BFD_RELOC_ALPHA_CODEADDR:
-      return;
-
-    case BFD_RELOC_VTABLE_INHERIT:
-    case BFD_RELOC_VTABLE_ENTRY:
-      return;
-
-    default:
-      {
-	const struct alpha_operand *operand;
-
-	if ((int) fixP->fx_r_type >= 0)
-	  as_fatal (_("unhandled relocation type %s"),
-		    bfd_get_reloc_code_name (fixP->fx_r_type));
-
-	assert (-(int) fixP->fx_r_type < (int) alpha_num_operands);
-	operand = &alpha_operands[-(int) fixP->fx_r_type];
-
-	/* The rest of these fixups only exist internally during symbol
-	   resolution and have no representation in the object file.
-	   Therefore they must be completely resolved as constants.  */
-
-	if (fixP->fx_addsy != 0
-	    && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("non-absolute expression in constant field"));
-
-	image = bfd_getl32 (fixpos);
-	image = insert_operand (image, operand, (offsetT) value,
-				fixP->fx_file, fixP->fx_line);
-      }
-      goto write_done;
-    }
-
-  if (fixP->fx_addsy != 0 || fixP->fx_pcrel != 0)
-    return;
-  else
-    {
-      as_warn_where (fixP->fx_file, fixP->fx_line,
-		     _("type %d reloc done?\n"), (int) fixP->fx_r_type);
-      goto done;
-    }
-
-write_done:
-  md_number_to_chars (fixpos, image, 4);
-
-done:
-  fixP->fx_done = 1;
-}
-
-/* Look for a register name in the given symbol.  */
-
-symbolS *
-md_undefined_symbol (name)
-     char *name;
-{
-  if (*name == '$')
-    {
-      int is_float = 0, num;
-
-      switch (*++name)
-	{
-	case 'f':
-	  if (name[1] == 'p' && name[2] == '\0')
-	    return alpha_register_table[AXP_REG_FP];
-	  is_float = 32;
-	  /* FALLTHRU */
-
-	case 'r':
-	  if (!ISDIGIT (*++name))
-	    break;
-	  /* FALLTHRU */
-
-	case '0': case '1': case '2': case '3': case '4':
-	case '5': case '6': case '7': case '8': case '9':
-	  if (name[1] == '\0')
-	    num = name[0] - '0';
-	  else if (name[0] != '0' && ISDIGIT (name[1]) && name[2] == '\0')
-	    {
-	      num = (name[0] - '0') * 10 + name[1] - '0';
-	      if (num >= 32)
-		break;
-	    }
-	  else
-	    break;
-
-	  if (!alpha_noat_on && (num + is_float) == AXP_REG_AT)
-	    as_warn (_("Used $at without \".set noat\""));
-	  return alpha_register_table[num + is_float];
-
-	case 'a':
-	  if (name[1] == 't' && name[2] == '\0')
-	    {
-	      if (!alpha_noat_on)
-		as_warn (_("Used $at without \".set noat\""));
-	      return alpha_register_table[AXP_REG_AT];
-	    }
-	  break;
-
-	case 'g':
-	  if (name[1] == 'p' && name[2] == '\0')
-	    return alpha_register_table[alpha_gp_register];
-	  break;
-
-	case 's':
-	  if (name[1] == 'p' && name[2] == '\0')
-	    return alpha_register_table[AXP_REG_SP];
-	  break;
-	}
-    }
-  return NULL;
-}
-
-#ifdef OBJ_ECOFF
-/* @@@ Magic ECOFF bits.  */
-
-void
-alpha_frob_ecoff_data ()
-{
-  select_gp_value ();
-  /* $zero and $f31 are read-only */
-  alpha_gprmask &= ~1;
-  alpha_fprmask &= ~1;
-}
-#endif
-
-/* Hook to remember a recently defined label so that the auto-align
-   code can adjust the symbol after we know what alignment will be
-   required.  */
-
-void
-alpha_define_label (sym)
-     symbolS *sym;
-{
-  alpha_insn_label = sym;
-}
-
-/* Return true if we must always emit a reloc for a type and false if
-   there is some hope of resolving it at assembly time.  */
-
-int
-alpha_force_relocation (f)
-     fixS *f;
-{
-  if (alpha_flag_relax)
-    return 1;
-
-  switch (f->fx_r_type)
-    {
-    case BFD_RELOC_ALPHA_GPDISP_HI16:
-    case BFD_RELOC_ALPHA_GPDISP_LO16:
-    case BFD_RELOC_ALPHA_GPDISP:
-    case BFD_RELOC_ALPHA_LITERAL:
-    case BFD_RELOC_ALPHA_ELF_LITERAL:
-    case BFD_RELOC_ALPHA_LITUSE:
-    case BFD_RELOC_GPREL16:
-    case BFD_RELOC_GPREL32:
-    case BFD_RELOC_ALPHA_GPREL_HI16:
-    case BFD_RELOC_ALPHA_GPREL_LO16:
-    case BFD_RELOC_ALPHA_LINKAGE:
-    case BFD_RELOC_ALPHA_CODEADDR:
-    case BFD_RELOC_ALPHA_BRSGP:
-    case BFD_RELOC_ALPHA_TLSGD:
-    case BFD_RELOC_ALPHA_TLSLDM:
-    case BFD_RELOC_ALPHA_GOTDTPREL16:
-    case BFD_RELOC_ALPHA_DTPREL_HI16:
-    case BFD_RELOC_ALPHA_DTPREL_LO16:
-    case BFD_RELOC_ALPHA_DTPREL16:
-    case BFD_RELOC_ALPHA_GOTTPREL16:
-    case BFD_RELOC_ALPHA_TPREL_HI16:
-    case BFD_RELOC_ALPHA_TPREL_LO16:
-    case BFD_RELOC_ALPHA_TPREL16:
-      return 1;
-
-    default:
-      break;
-    }
-
-  return generic_force_reloc (f);
-}
-
-/* Return true if we can partially resolve a relocation now.  */
-
-int
-alpha_fix_adjustable (f)
-     fixS *f;
-{
-  /* Are there any relocation types for which we must generate a reloc
-     but we can adjust the values contained within it?  */
-  switch (f->fx_r_type)
-    {
-    case BFD_RELOC_ALPHA_GPDISP_HI16:
-    case BFD_RELOC_ALPHA_GPDISP_LO16:
-    case BFD_RELOC_ALPHA_GPDISP:
-      return 0;
-
-    case BFD_RELOC_ALPHA_LITERAL:
-    case BFD_RELOC_ALPHA_ELF_LITERAL:
-    case BFD_RELOC_ALPHA_LITUSE:
-    case BFD_RELOC_ALPHA_LINKAGE:
-    case BFD_RELOC_ALPHA_CODEADDR:
-      return 1;
-
-    case BFD_RELOC_VTABLE_ENTRY:
-    case BFD_RELOC_VTABLE_INHERIT:
-      return 0;
-
-    case BFD_RELOC_GPREL16:
-    case BFD_RELOC_GPREL32:
-    case BFD_RELOC_ALPHA_GPREL_HI16:
-    case BFD_RELOC_ALPHA_GPREL_LO16:
-    case BFD_RELOC_23_PCREL_S2:
-    case BFD_RELOC_32:
-    case BFD_RELOC_64:
-    case BFD_RELOC_ALPHA_HINT:
-      return 1;
-
-    case BFD_RELOC_ALPHA_TLSGD:
-    case BFD_RELOC_ALPHA_TLSLDM:
-    case BFD_RELOC_ALPHA_GOTDTPREL16:
-    case BFD_RELOC_ALPHA_DTPREL_HI16:
-    case BFD_RELOC_ALPHA_DTPREL_LO16:
-    case BFD_RELOC_ALPHA_DTPREL16:
-    case BFD_RELOC_ALPHA_GOTTPREL16:
-    case BFD_RELOC_ALPHA_TPREL_HI16:
-    case BFD_RELOC_ALPHA_TPREL_LO16:
-    case BFD_RELOC_ALPHA_TPREL16:
-      /* ??? No idea why we can't return a reference to .tbss+10, but
-	 we're preventing this in the other assemblers.  Follow for now.  */
-      return 0;
-
-#ifdef OBJ_ELF
-    case BFD_RELOC_ALPHA_BRSGP:
-      /* If we have a BRSGP reloc to a local symbol, adjust it to BRADDR and
-         let it get resolved at assembly time.  */
-      {
-	symbolS *sym = f->fx_addsy;
-	const char *name;
-	int offset = 0;
-
-	if (generic_force_reloc (f))
-	  return 0;
-
-	switch (S_GET_OTHER (sym) & STO_ALPHA_STD_GPLOAD)
-	  {
-	  case STO_ALPHA_NOPV:
-	    break;
-	  case STO_ALPHA_STD_GPLOAD:
-	    offset = 8;
-	    break;
-	  default:
-	    if (S_IS_LOCAL (sym))
-	      name = "<local>";
-	    else
-	      name = S_GET_NAME (sym);
-	    as_bad_where (f->fx_file, f->fx_line,
-		_("!samegp reloc against symbol without .prologue: %s"),
-		name);
-	    break;
-	  }
-	f->fx_r_type = BFD_RELOC_23_PCREL_S2;
-	f->fx_offset += offset;
-	return 1;
-      }
-#endif
-
-    default:
-      return 1;
-    }
-  /*NOTREACHED*/
-}
-
-/* Generate the BFD reloc to be stuck in the object file from the
-   fixup used internally in the assembler.  */
-
-arelent *
-tc_gen_reloc (sec, fixp)
-     asection *sec ATTRIBUTE_UNUSED;
-     fixS *fixp;
-{
-  arelent *reloc;
-
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
-
-  /* Make sure none of our internal relocations make it this far.
-     They'd better have been fully resolved by this point.  */
-  assert ((int) fixp->fx_r_type > 0);
-
-  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
-  if (reloc->howto == NULL)
-    {
-      as_bad_where (fixp->fx_file, fixp->fx_line,
-		    _("cannot represent `%s' relocation in object file"),
-		    bfd_get_reloc_code_name (fixp->fx_r_type));
-      return NULL;
-    }
-
-  if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
-    {
-      as_fatal (_("internal error? cannot generate `%s' relocation"),
-		bfd_get_reloc_code_name (fixp->fx_r_type));
-    }
-  assert (!fixp->fx_pcrel == !reloc->howto->pc_relative);
-
-#ifdef OBJ_ECOFF
-  if (fixp->fx_r_type == BFD_RELOC_ALPHA_LITERAL)
-    {
-      /* Fake out bfd_perform_relocation. sigh.  */
-      reloc->addend = -alpha_gp_value;
-    }
-  else
-#endif
-    {
-      reloc->addend = fixp->fx_offset;
-#ifdef OBJ_ELF
-      /* Ohhh, this is ugly.  The problem is that if this is a local global
-         symbol, the relocation will entirely be performed at link time, not
-         at assembly time.  bfd_perform_reloc doesn't know about this sort
-         of thing, and as a result we need to fake it out here.  */
-      if ((S_IS_EXTERN (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)
-	   || (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE)
-	   || (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_THREAD_LOCAL))
-	  && !S_IS_COMMON (fixp->fx_addsy))
-	reloc->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value;
-#endif
-    }
-
-  return reloc;
-}
-
-/* Parse a register name off of the input_line and return a register
-   number.  Gets md_undefined_symbol above to do the register name
-   matching for us.
-
-   Only called as a part of processing the ECOFF .frame directive.  */
-
-int
-tc_get_register (frame)
-     int frame ATTRIBUTE_UNUSED;
-{
-  int framereg = AXP_REG_SP;
-
-  SKIP_WHITESPACE ();
-  if (*input_line_pointer == '$')
-    {
-      char *s = input_line_pointer;
-      char c = get_symbol_end ();
-      symbolS *sym = md_undefined_symbol (s);
-
-      *strchr (s, '\0') = c;
-      if (sym && (framereg = S_GET_VALUE (sym)) <= 31)
-	goto found;
-    }
-  as_warn (_("frame reg expected, using $%d."), framereg);
-
-found:
-  note_gpreg (framereg);
-  return framereg;
-}
-
-/* This is called before the symbol table is processed.  In order to
-   work with gcc when using mips-tfile, we must keep all local labels.
-   However, in other cases, we want to discard them.  If we were
-   called with -g, but we didn't see any debugging information, it may
-   mean that gcc is smuggling debugging information through to
-   mips-tfile, in which case we must generate all local labels.  */
-
-#ifdef OBJ_ECOFF
-
-void
-alpha_frob_file_before_adjust ()
-{
-  if (alpha_debug != 0
-      && ! ecoff_debugging_seen)
-    flag_keep_locals = 1;
-}
+/* Some instruction sets indexed by lg(size).  */
+static const char * const sextX_op[] = { "sextb", "sextw", "sextl", NULL };
+static const char * const insXl_op[] = { "insbl", "inswl", "insll", "insql" };
+static const char * const insXh_op[] = { NULL,    "inswh", "inslh", "insqh" };
+static const char * const extXl_op[] = { "extbl", "extwl", "extll", "extql" };
+static const char * const extXh_op[] = { NULL,    "extwh", "extlh", "extqh" };
+static const char * const mskXl_op[] = { "mskbl", "mskwl", "mskll", "mskql" };
+static const char * const mskXh_op[] = { NULL,    "mskwh", "msklh", "mskqh" };
+static const char * const stX_op[] = { "stb", "stw", "stl", "stq" };
+static const char * const ldXu_op[] = { "ldbu", "ldwu", NULL, NULL };
 
-#endif /* OBJ_ECOFF */
+static void assemble_insn (const struct alpha_opcode *, const expressionS *, int, struct alpha_insn *, bfd_reloc_code_real_type);
+static void emit_insn (struct alpha_insn *);
+static void assemble_tokens (const char *, const expressionS *, int, int);
 
 static struct alpha_reloc_tag *
-get_alpha_reloc_tag (sequence)
-     long sequence;
+get_alpha_reloc_tag (long sequence)
 {
   char buffer[ALPHA_RELOC_DIGITS];
   struct alpha_reloc_tag *info;
@@ -1680,13 +542,12 @@ get_alpha_reloc_tag (sequence)
       size_t len = strlen (buffer);
       const char *errmsg;
 
-      info = (struct alpha_reloc_tag *)
-	xcalloc (sizeof (struct alpha_reloc_tag) + len, 1);
+      info = xcalloc (sizeof (struct alpha_reloc_tag) + len, 1);
 
       info->segment = now_seg;
       info->sequence = sequence;
       strcpy (info->string, buffer);
-      errmsg = hash_insert (alpha_literal_hash, info->string, (PTR) info);
+      errmsg = hash_insert (alpha_literal_hash, info->string, (void *) info);
       if (errmsg)
 	as_fatal (errmsg);
     }
@@ -1694,22 +555,10 @@ get_alpha_reloc_tag (sequence)
   return info;
 }
 
-/* Before the relocations are written, reorder them, so that user
-   supplied !lituse relocations follow the appropriate !literal
-   relocations, and similarly for !gpdisp relocations.  */
-
-void
-alpha_before_fix ()
-{
-  if (alpha_literal_hash)
-    bfd_map_over_sections (stdoutput, alpha_adjust_relocs, NULL);
-}
-
 static void
-alpha_adjust_relocs (abfd, sec, ptr)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec;
-     PTR ptr ATTRIBUTE_UNUSED;
+alpha_adjust_relocs (bfd *abfd ATTRIBUTE_UNUSED,
+		     asection *sec,
+		     void * ptr ATTRIBUTE_UNUSED)
 {
   segment_info_type *seginfo = seg_info (sec);
   fixS **prevP;
@@ -1823,7 +672,7 @@ alpha_adjust_relocs (abfd, sec, ptr)
 	  fixp->tc_fix_data.info->master->fx_next = fixp->fx_next;
 	  fixp->fx_next = fixp->tc_fix_data.info->master;
 	  fixp = fixp->fx_next;
-	  /* FALLTHRU */
+	  /* Fall through.  */
 
 	case BFD_RELOC_ALPHA_ELF_LITERAL:
 	  if (fixp->tc_fix_data.info
@@ -1858,12 +707,21 @@ alpha_adjust_relocs (abfd, sec, ptr)
 	}
     }
 }
+
+/* Before the relocations are written, reorder them, so that user
+   supplied !lituse relocations follow the appropriate !literal
+   relocations, and similarly for !gpdisp relocations.  */
+
+void
+alpha_before_fix (void)
+{
+  if (alpha_literal_hash)
+    bfd_map_over_sections (stdoutput, alpha_adjust_relocs, NULL);
+}
 
 #ifdef DEBUG_ALPHA
 static void
-debug_exp (tok, ntok)
-     expressionS tok[];
-     int ntok;
+debug_exp (expressionS tok[], int ntok)
 {
   int i;
 
@@ -1915,6 +773,7 @@ debug_exp (tok, ntok)
 	case O_lituse_jsr:		name = "O_lituse_jsr";		break;
 	case O_lituse_tlsgd:		name = "O_lituse_tlsgd";	break;
 	case O_lituse_tlsldm:		name = "O_lituse_tlsldm";	break;
+	case O_lituse_jsrdirect:	name = "O_lituse_jsrdirect";	break;
 	case O_gpdisp:			name = "O_gpdisp";		break;
 	case O_gprelhigh:		name = "O_gprelhigh";		break;
 	case O_gprellow:		name = "O_gprellow";		break;
@@ -1945,10 +804,9 @@ debug_exp (tok, ntok)
 /* Parse the arguments to an opcode.  */
 
 static int
-tokenize_arguments (str, tok, ntok)
-     char *str;
-     expressionS tok[];
-     int ntok;
+tokenize_arguments (char *str,
+		    expressionS tok[],
+		    int ntok)
 {
   expressionS *end_tok = tok + ntok;
   char *old_input_line_pointer;
@@ -2134,11 +992,10 @@ err_report:
    syntax match.  */
 
 static const struct alpha_opcode *
-find_opcode_match (first_opcode, tok, pntok, pcpumatch)
-     const struct alpha_opcode *first_opcode;
-     const expressionS *tok;
-     int *pntok;
-     int *pcpumatch;
+find_opcode_match (const struct alpha_opcode *first_opcode,
+		   const expressionS *tok,
+		   int *pntok,
+		   int *pcpumatch)
 {
   const struct alpha_opcode *opcode = first_opcode;
   int ntok = *pntok;
@@ -2237,529 +1094,6 @@ find_opcode_match (first_opcode, tok, pntok, pcpumatch)
   return NULL;
 }
 
-/* Search forward through all variants of a macro looking for a syntax
-   match.  */
-
-static const struct alpha_macro *
-find_macro_match (first_macro, tok, pntok)
-     const struct alpha_macro *first_macro;
-     const expressionS *tok;
-     int *pntok;
-{
-  const struct alpha_macro *macro = first_macro;
-  int ntok = *pntok;
-
-  do
-    {
-      const enum alpha_macro_arg *arg = macro->argsets;
-      int tokidx = 0;
-
-      while (*arg)
-	{
-	  switch (*arg)
-	    {
-	    case MACRO_EOA:
-	      if (tokidx == ntok)
-		return macro;
-	      else
-		tokidx = 0;
-	      break;
-
-	      /* Index register.  */
-	    case MACRO_IR:
-	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
-		  || !is_ir_num (tok[tokidx].X_add_number))
-		goto match_failed;
-	      ++tokidx;
-	      break;
-
-	      /* Parenthesized index register.  */
-	    case MACRO_PIR:
-	      if (tokidx >= ntok || tok[tokidx].X_op != O_pregister
-		  || !is_ir_num (tok[tokidx].X_add_number))
-		goto match_failed;
-	      ++tokidx;
-	      break;
-
-	      /* Optional parenthesized index register.  */
-	    case MACRO_OPIR:
-	      if (tokidx < ntok && tok[tokidx].X_op == O_pregister
-		  && is_ir_num (tok[tokidx].X_add_number))
-		++tokidx;
-	      break;
-
-	      /* Leading comma with a parenthesized index register.  */
-	    case MACRO_CPIR:
-	      if (tokidx >= ntok || tok[tokidx].X_op != O_cpregister
-		  || !is_ir_num (tok[tokidx].X_add_number))
-		goto match_failed;
-	      ++tokidx;
-	      break;
-
-	      /* Floating point register.  */
-	    case MACRO_FPR:
-	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
-		  || !is_fpr_num (tok[tokidx].X_add_number))
-		goto match_failed;
-	      ++tokidx;
-	      break;
-
-	      /* Normal expression.  */
-	    case MACRO_EXP:
-	      if (tokidx >= ntok)
-		goto match_failed;
-	      switch (tok[tokidx].X_op)
-		{
-		case O_illegal:
-		case O_absent:
-		case O_register:
-		case O_pregister:
-		case O_cpregister:
-		case O_literal:
-		case O_lituse_base:
-		case O_lituse_bytoff:
-		case O_lituse_jsr:
-		case O_gpdisp:
-		case O_gprelhigh:
-		case O_gprellow:
-		case O_gprel:
-		case O_samegp:
-		  goto match_failed;
-
-		default:
-		  break;
-		}
-	      ++tokidx;
-	      break;
-
-	    match_failed:
-	      while (*arg != MACRO_EOA)
-		++arg;
-	      tokidx = 0;
-	      break;
-	    }
-	  ++arg;
-	}
-    }
-  while (++macro - alpha_macros < (int) alpha_num_macros
-	 && !strcmp (macro->name, first_macro->name));
-
-  return NULL;
-}
-
-/* Insert an operand value into an instruction.  */
-
-static unsigned
-insert_operand (insn, operand, val, file, line)
-     unsigned insn;
-     const struct alpha_operand *operand;
-     offsetT val;
-     char *file;
-     unsigned line;
-{
-  if (operand->bits != 32 && !(operand->flags & AXP_OPERAND_NOOVERFLOW))
-    {
-      offsetT min, max;
-
-      if (operand->flags & AXP_OPERAND_SIGNED)
-	{
-	  max = (1 << (operand->bits - 1)) - 1;
-	  min = -(1 << (operand->bits - 1));
-	}
-      else
-	{
-	  max = (1 << operand->bits) - 1;
-	  min = 0;
-	}
-
-      if (val < min || val > max)
-	{
-	  const char *err =
-	    _("operand out of range (%s not between %d and %d)");
-	  char buf[sizeof (val) * 3 + 2];
-
-	  sprint_value (buf, val);
-	  if (file)
-	    as_warn_where (file, line, err, buf, min, max);
-	  else
-	    as_warn (err, buf, min, max);
-	}
-    }
-
-  if (operand->insert)
-    {
-      const char *errmsg = NULL;
-
-      insn = (*operand->insert) (insn, val, &errmsg);
-      if (errmsg)
-	as_warn (errmsg);
-    }
-  else
-    insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
-
-  return insn;
-}
-
-/* Turn an opcode description and a set of arguments into
-   an instruction and a fixup.  */
-
-static void
-assemble_insn (opcode, tok, ntok, insn, reloc)
-     const struct alpha_opcode *opcode;
-     const expressionS *tok;
-     int ntok;
-     struct alpha_insn *insn;
-     bfd_reloc_code_real_type reloc;
-{
-  const struct alpha_operand *reloc_operand = NULL;
-  const expressionS *reloc_exp = NULL;
-  const unsigned char *argidx;
-  unsigned image;
-  int tokidx = 0;
-
-  memset (insn, 0, sizeof (*insn));
-  image = opcode->opcode;
-
-  for (argidx = opcode->operands; *argidx; ++argidx)
-    {
-      const struct alpha_operand *operand = &alpha_operands[*argidx];
-      const expressionS *t = (const expressionS *) 0;
-
-      if (operand->flags & AXP_OPERAND_FAKE)
-	{
-	  /* fake operands take no value and generate no fixup */
-	  image = insert_operand (image, operand, 0, NULL, 0);
-	  continue;
-	}
-
-      if (tokidx >= ntok)
-	{
-	  switch (operand->flags & AXP_OPERAND_OPTIONAL_MASK)
-	    {
-	    case AXP_OPERAND_DEFAULT_FIRST:
-	      t = &tok[0];
-	      break;
-	    case AXP_OPERAND_DEFAULT_SECOND:
-	      t = &tok[1];
-	      break;
-	    case AXP_OPERAND_DEFAULT_ZERO:
-	      {
-		static expressionS zero_exp;
-		t = &zero_exp;
-		zero_exp.X_op = O_constant;
-		zero_exp.X_unsigned = 1;
-	      }
-	      break;
-	    default:
-	      abort ();
-	    }
-	}
-      else
-	t = &tok[tokidx++];
-
-      switch (t->X_op)
-	{
-	case O_register:
-	case O_pregister:
-	case O_cpregister:
-	  image = insert_operand (image, operand, regno (t->X_add_number),
-				  NULL, 0);
-	  break;
-
-	case O_constant:
-	  image = insert_operand (image, operand, t->X_add_number, NULL, 0);
-	  assert (reloc_operand == NULL);
-	  reloc_operand = operand;
-	  reloc_exp = t;
-	  break;
-
-	default:
-	  /* This is only 0 for fields that should contain registers,
-	     which means this pattern shouldn't have matched.  */
-	  if (operand->default_reloc == 0)
-	    abort ();
-
-	  /* There is one special case for which an insn receives two
-	     relocations, and thus the user-supplied reloc does not
-	     override the operand reloc.  */
-	  if (operand->default_reloc == BFD_RELOC_ALPHA_HINT)
-	    {
-	      struct alpha_fixup *fixup;
-
-	      if (insn->nfixups >= MAX_INSN_FIXUPS)
-		as_fatal (_("too many fixups"));
-
-	      fixup = &insn->fixups[insn->nfixups++];
-	      fixup->exp = *t;
-	      fixup->reloc = BFD_RELOC_ALPHA_HINT;
-	    }
-	  else
-	    {
-	      if (reloc == BFD_RELOC_UNUSED)
-		reloc = operand->default_reloc;
-
-	      assert (reloc_operand == NULL);
-	      reloc_operand = operand;
-	      reloc_exp = t;
-	    }
-	  break;
-	}
-    }
-
-  if (reloc != BFD_RELOC_UNUSED)
-    {
-      struct alpha_fixup *fixup;
-
-      if (insn->nfixups >= MAX_INSN_FIXUPS)
-	as_fatal (_("too many fixups"));
-
-      /* ??? My but this is hacky.  But the OSF/1 assembler uses the same
-	 relocation tag for both ldah and lda with gpdisp.  Choose the
-	 correct internal relocation based on the opcode.  */
-      if (reloc == BFD_RELOC_ALPHA_GPDISP)
-	{
-	  if (strcmp (opcode->name, "ldah") == 0)
-	    reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
-	  else if (strcmp (opcode->name, "lda") == 0)
-	    reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
-	  else
-	    as_bad (_("invalid relocation for instruction"));
-	}
-
-      /* If this is a real relocation (as opposed to a lituse hint), then
-	 the relocation width should match the operand width.  */
-      else if (reloc < BFD_RELOC_UNUSED)
-	{
-	  reloc_howto_type *reloc_howto
-	    = bfd_reloc_type_lookup (stdoutput, reloc);
-	  if (reloc_howto->bitsize != reloc_operand->bits)
-	    {
-	      as_bad (_("invalid relocation for field"));
-	      return;
-	    }
-	}
-
-      fixup = &insn->fixups[insn->nfixups++];
-      if (reloc_exp)
-	fixup->exp = *reloc_exp;
-      else
-	fixup->exp.X_op = O_absent;
-      fixup->reloc = reloc;
-    }
-
-  insn->insn = image;
-}
-
-/* Actually output an instruction with its fixup.  */
-
-static void
-emit_insn (insn)
-     struct alpha_insn *insn;
-{
-  char *f;
-  int i;
-
-  /* Take care of alignment duties.  */
-  if (alpha_auto_align_on && alpha_current_align < 2)
-    alpha_align (2, (char *) NULL, alpha_insn_label, 0);
-  if (alpha_current_align > 2)
-    alpha_current_align = 2;
-  alpha_insn_label = NULL;
-
-  /* Write out the instruction.  */
-  f = frag_more (4);
-  md_number_to_chars (f, insn->insn, 4);
-
-#ifdef OBJ_ELF
-  dwarf2_emit_insn (4);
-#endif
-
-  /* Apply the fixups in order.  */
-  for (i = 0; i < insn->nfixups; ++i)
-    {
-      const struct alpha_operand *operand = (const struct alpha_operand *) 0;
-      struct alpha_fixup *fixup = &insn->fixups[i];
-      struct alpha_reloc_tag *info = NULL;
-      int size, pcrel;
-      fixS *fixP;
-
-      /* Some fixups are only used internally and so have no howto.  */
-      if ((int) fixup->reloc < 0)
-	{
-	  operand = &alpha_operands[-(int) fixup->reloc];
-	  size = 4;
-	  pcrel = ((operand->flags & AXP_OPERAND_RELATIVE) != 0);
-	}
-      else if (fixup->reloc > BFD_RELOC_UNUSED
-	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_HI16
-	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_LO16)
-	{
-	  size = 2;
-	  pcrel = 0;
-	}
-      else
-	{
-	  reloc_howto_type *reloc_howto
-	    = bfd_reloc_type_lookup (stdoutput, fixup->reloc);
-	  assert (reloc_howto);
-
-	  size = bfd_get_reloc_size (reloc_howto);
-	  assert (size >= 1 && size <= 4);
-
-	  pcrel = reloc_howto->pc_relative;
-	}
-
-      fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size,
-			  &fixup->exp, pcrel, fixup->reloc);
-
-      /* Turn off complaints that the addend is too large for some fixups,
-         and copy in the sequence number for the explicit relocations.  */
-      switch (fixup->reloc)
-	{
-	case BFD_RELOC_ALPHA_HINT:
-	case BFD_RELOC_GPREL32:
-	case BFD_RELOC_GPREL16:
-	case BFD_RELOC_ALPHA_GPREL_HI16:
-	case BFD_RELOC_ALPHA_GPREL_LO16:
-	case BFD_RELOC_ALPHA_GOTDTPREL16:
-	case BFD_RELOC_ALPHA_DTPREL_HI16:
-	case BFD_RELOC_ALPHA_DTPREL_LO16:
-	case BFD_RELOC_ALPHA_DTPREL16:
-	case BFD_RELOC_ALPHA_GOTTPREL16:
-	case BFD_RELOC_ALPHA_TPREL_HI16:
-	case BFD_RELOC_ALPHA_TPREL_LO16:
-	case BFD_RELOC_ALPHA_TPREL16:
-	  fixP->fx_no_overflow = 1;
-	  break;
-
-	case BFD_RELOC_ALPHA_GPDISP_HI16:
-	  fixP->fx_no_overflow = 1;
-	  fixP->fx_addsy = section_symbol (now_seg);
-	  fixP->fx_offset = 0;
-
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  if (++info->n_master > 1)
-	    as_bad (_("too many ldah insns for !gpdisp!%ld"), insn->sequence);
-	  if (info->segment != now_seg)
-	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
-		    insn->sequence);
-	  fixP->tc_fix_data.info = info;
-	  break;
-
-	case BFD_RELOC_ALPHA_GPDISP_LO16:
-	  fixP->fx_no_overflow = 1;
-
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  if (++info->n_slaves > 1)
-	    as_bad (_("too many lda insns for !gpdisp!%ld"), insn->sequence);
-	  if (info->segment != now_seg)
-	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
-		    insn->sequence);
-	  fixP->tc_fix_data.info = info;
-	  info->slaves = fixP;
-	  break;
-
-	case BFD_RELOC_ALPHA_LITERAL:
-	case BFD_RELOC_ALPHA_ELF_LITERAL:
-	  fixP->fx_no_overflow = 1;
-
-	  if (insn->sequence == 0)
-	    break;
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  info->master = fixP;
-	  info->n_master++;
-	  if (info->segment != now_seg)
-	    info->multi_section_p = 1;
-	  fixP->tc_fix_data.info = info;
-	  break;
-
-#ifdef RELOC_OP_P
-	case DUMMY_RELOC_LITUSE_ADDR:
-	  fixP->fx_offset = LITUSE_ALPHA_ADDR;
-	  goto do_lituse;
-	case DUMMY_RELOC_LITUSE_BASE:
-	  fixP->fx_offset = LITUSE_ALPHA_BASE;
-	  goto do_lituse;
-	case DUMMY_RELOC_LITUSE_BYTOFF:
-	  fixP->fx_offset = LITUSE_ALPHA_BYTOFF;
-	  goto do_lituse;
-	case DUMMY_RELOC_LITUSE_JSR:
-	  fixP->fx_offset = LITUSE_ALPHA_JSR;
-	  goto do_lituse;
-	case DUMMY_RELOC_LITUSE_TLSGD:
-	  fixP->fx_offset = LITUSE_ALPHA_TLSGD;
-	  goto do_lituse;
-	case DUMMY_RELOC_LITUSE_TLSLDM:
-	  fixP->fx_offset = LITUSE_ALPHA_TLSLDM;
-	  goto do_lituse;
-	do_lituse:
-	  fixP->fx_addsy = section_symbol (now_seg);
-	  fixP->fx_r_type = BFD_RELOC_ALPHA_LITUSE;
-
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSGD)
-	    info->saw_lu_tlsgd = 1;
-	  else if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSLDM)
-	    info->saw_lu_tlsldm = 1;
-	  if (++info->n_slaves > 1)
-	    {
-	      if (info->saw_lu_tlsgd)
-		as_bad (_("too many lituse insns for !lituse_tlsgd!%ld"),
-		        insn->sequence);
-	      else if (info->saw_lu_tlsldm)
-		as_bad (_("too many lituse insns for !lituse_tlsldm!%ld"),
-		        insn->sequence);
-	    }
-	  fixP->tc_fix_data.info = info;
-	  fixP->tc_fix_data.next_reloc = info->slaves;
-	  info->slaves = fixP;
-	  if (info->segment != now_seg)
-	    info->multi_section_p = 1;
-	  break;
-
-	case BFD_RELOC_ALPHA_TLSGD:
-	  fixP->fx_no_overflow = 1;
-
-	  if (insn->sequence == 0)
-	    break;
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  if (info->saw_tlsgd)
-	    as_bad (_("duplicate !tlsgd!%ld"), insn->sequence);
-	  else if (info->saw_tlsldm)
-	    as_bad (_("sequence number in use for !tlsldm!%ld"),
-		    insn->sequence);
-	  else
-	    info->saw_tlsgd = 1;
-	  fixP->tc_fix_data.info = info;
-	  break;
-
-	case BFD_RELOC_ALPHA_TLSLDM:
-	  fixP->fx_no_overflow = 1;
-
-	  if (insn->sequence == 0)
-	    break;
-	  info = get_alpha_reloc_tag (insn->sequence);
-	  if (info->saw_tlsldm)
-	    as_bad (_("duplicate !tlsldm!%ld"), insn->sequence);
-	  else if (info->saw_tlsgd)
-	    as_bad (_("sequence number in use for !tlsgd!%ld"),
-		    insn->sequence);
-	  else
-	    info->saw_tlsldm = 1;
-	  fixP->tc_fix_data.info = info;
-	  break;
-#endif
-	default:
-	  if ((int) fixup->reloc < 0)
-	    {
-	      if (operand->flags & AXP_OPERAND_NOOVERFLOW)
-		fixP->fx_no_overflow = 1;
-	    }
-	  break;
-	}
-    }
-}
-
 /* Given an opcode name and a pre-tokenized set of arguments, assemble
    the insn, but do not emit it.
 
@@ -2767,15 +1101,14 @@ emit_insn (insn)
    than one insn in an insn structure.  */
 
 static void
-assemble_tokens_to_insn (opname, tok, ntok, insn)
-     const char *opname;
-     const expressionS *tok;
-     int ntok;
-     struct alpha_insn *insn;
+assemble_tokens_to_insn (const char *opname,
+			 const expressionS *tok,
+			 int ntok,
+			 struct alpha_insn *insn)
 {
   const struct alpha_opcode *opcode;
 
-  /* search opcodes */
+  /* Search opcodes.  */
   opcode = (const struct alpha_opcode *) hash_find (alpha_opcode_hash, opname);
   if (opcode)
     {
@@ -2796,208 +1129,27 @@ assemble_tokens_to_insn (opname, tok, ntok, insn)
     as_bad (_("unknown opcode `%s'"), opname);
 }
 
-/* Given an opcode name and a pre-tokenized set of arguments, take the
-   opcode all the way through emission.  */
-
-static void
-assemble_tokens (opname, tok, ntok, local_macros_on)
-     const char *opname;
-     const expressionS *tok;
-     int ntok;
-     int local_macros_on;
-{
-  int found_something = 0;
-  const struct alpha_opcode *opcode;
-  const struct alpha_macro *macro;
-  int cpumatch = 1;
-  bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
-
-#ifdef RELOC_OP_P
-  /* If a user-specified relocation is present, this is not a macro.  */
-  if (ntok && USER_RELOC_P (tok[ntok - 1].X_op))
-    {
-      reloc = ALPHA_RELOC_TABLE (tok[ntok - 1].X_op)->reloc;
-      ntok--;
-    }
-  else
-#endif
-  if (local_macros_on)
-    {
-      macro = ((const struct alpha_macro *)
-	       hash_find (alpha_macro_hash, opname));
-      if (macro)
-	{
-	  found_something = 1;
-	  macro = find_macro_match (macro, tok, &ntok);
-	  if (macro)
-	    {
-	      (*macro->emit) (tok, ntok, macro->arg);
-	      return;
-	    }
-	}
-    }
-
-  /* Search opcodes.  */
-  opcode = (const struct alpha_opcode *) hash_find (alpha_opcode_hash, opname);
-  if (opcode)
-    {
-      found_something = 1;
-      opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch);
-      if (opcode)
-	{
-	  struct alpha_insn insn;
-	  assemble_insn (opcode, tok, ntok, &insn, reloc);
-
-	  /* Copy the sequence number for the reloc from the reloc token.  */
-	  if (reloc != BFD_RELOC_UNUSED)
-	    insn.sequence = tok[ntok].X_add_number;
-
-	  emit_insn (&insn);
-	  return;
-	}
-    }
-
-  if (found_something)
-    {
-      if (cpumatch)
-	as_bad (_("inappropriate arguments for opcode `%s'"), opname);
-      else
-	as_bad (_("opcode `%s' not supported for target %s"), opname,
-		alpha_target_name);
-    }
-  else
-    as_bad (_("unknown opcode `%s'"), opname);
-}
-
-/* Some instruction sets indexed by lg(size).  */
-static const char * const sextX_op[] = { "sextb", "sextw", "sextl", NULL };
-static const char * const insXl_op[] = { "insbl", "inswl", "insll", "insql" };
-static const char * const insXh_op[] = { NULL,    "inswh", "inslh", "insqh" };
-static const char * const extXl_op[] = { "extbl", "extwl", "extll", "extql" };
-static const char * const extXh_op[] = { NULL,    "extwh", "extlh", "extqh" };
-static const char * const mskXl_op[] = { "mskbl", "mskwl", "mskll", "mskql" };
-static const char * const mskXh_op[] = { NULL,    "mskwh", "msklh", "mskqh" };
-static const char * const stX_op[] = { "stb", "stw", "stl", "stq" };
-static const char * const ldXu_op[] = { "ldbu", "ldwu", NULL, NULL };
-
-/* Implement the ldgp macro.  */
+/* Build a BFD section with its flags set appropriately for the .lita,
+   .lit8, or .lit4 sections.  */
 
 static void
-emit_ldgp (tok, ntok, unused)
-     const expressionS *tok;
-     int ntok ATTRIBUTE_UNUSED;
-     const PTR unused ATTRIBUTE_UNUSED;
-{
-#ifdef OBJ_AOUT
-FIXME
-#endif
-#if defined(OBJ_ECOFF) || defined(OBJ_ELF)
-  /* from "ldgp r1,n(r2)", generate "ldah r1,X(R2); lda r1,Y(r1)"
-     with appropriate constants and relocations.  */
-  struct alpha_insn insn;
-  expressionS newtok[3];
-  expressionS addend;
-
-#ifdef OBJ_ECOFF
-  if (regno (tok[2].X_add_number) == AXP_REG_PV)
-    ecoff_set_gp_prolog_size (0);
-#endif
-
-  newtok[0] = tok[0];
-  set_tok_const (newtok[1], 0);
-  newtok[2] = tok[2];
-
-  assemble_tokens_to_insn ("ldah", newtok, 3, &insn);
-
-  addend = tok[1];
-
-#ifdef OBJ_ECOFF
-  if (addend.X_op != O_constant)
-    as_bad (_("can not resolve expression"));
-  addend.X_op = O_symbol;
-  addend.X_add_symbol = alpha_gp_symbol;
-#endif
-
-  insn.nfixups = 1;
-  insn.fixups[0].exp = addend;
-  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
-  insn.sequence = next_sequence_num;
-
-  emit_insn (&insn);
-
-  set_tok_preg (newtok[2], tok[0].X_add_number);
-
-  assemble_tokens_to_insn ("lda", newtok, 3, &insn);
-
-#ifdef OBJ_ECOFF
-  addend.X_add_number += 4;
-#endif
-
-  insn.nfixups = 1;
-  insn.fixups[0].exp = addend;
-  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
-  insn.sequence = next_sequence_num--;
-
-  emit_insn (&insn);
-#endif /* OBJ_ECOFF || OBJ_ELF */
-}
-
-#ifdef OBJ_EVAX
-
-/* Add symbol+addend to link pool.
-   Return offset from basesym to entry in link pool.
-
-   Add new fixup only if offset isn't 16bit.  */
-
-valueT
-add_to_link_pool (basesym, sym, addend)
-     symbolS *basesym;
-     symbolS *sym;
-     offsetT addend;
+create_literal_section (const char *name,
+			segT *secp,
+			symbolS **symp)
 {
   segT current_section = now_seg;
   int current_subsec = now_subseg;
-  valueT offset;
-  bfd_reloc_code_real_type reloc_type;
-  char *p;
-  segment_info_type *seginfo = seg_info (alpha_link_section);
-  fixS *fixp;
-
-  offset = - *symbol_get_obj (basesym);
-
-  /* @@ This assumes all entries in a given section will be of the same
-     size...  Probably correct, but unwise to rely on.  */
-  /* This must always be called with the same subsegment.  */
-
-  if (seginfo->frchainP)
-    for (fixp = seginfo->frchainP->fix_root;
-	 fixp != (fixS *) NULL;
-	 fixp = fixp->fx_next, offset += 8)
-      {
-	if (fixp->fx_addsy == sym && fixp->fx_offset == addend)
-	  {
-	    if (range_signed_16 (offset))
-	      {
-		return offset;
-	      }
-	  }
-      }
-
-  /* Not found in 16bit signed range.  */
-
-  subseg_set (alpha_link_section, 0);
-  p = frag_more (8);
-  memset (p, 0, 8);
-
-  fix_new (frag_now, p - frag_now->fr_literal, 8, sym, addend, 0,
-	   BFD_RELOC_64);
+  segT new_sec;
 
+  *secp = new_sec = subseg_new (name, 0);
   subseg_set (current_section, current_subsec);
-  seginfo->literal_pool_size += 8;
-  return offset;
-}
+  bfd_set_section_alignment (stdoutput, new_sec, 4);
+  bfd_set_section_flags (stdoutput, new_sec,
+			 SEC_RELOC | SEC_ALLOC | SEC_LOAD | SEC_READONLY
+			 | SEC_DATA);
 
-#endif /* OBJ_EVAX */
+  S_CLEAR_EXTERNAL (*symp = section_symbol (new_sec));
+}
 
 /* Load a (partial) expression into a target register.
 
@@ -3021,11 +1173,10 @@ add_to_link_pool (basesym, sym, addend)
    sequence number to use.  */
 
 static long
-load_expression (targreg, exp, pbasereg, poffset)
-     int targreg;
-     const expressionS *exp;
-     int *pbasereg;
-     expressionS *poffset;
+load_expression (int targreg,
+		 const expressionS *exp,
+		 int *pbasereg,
+		 expressionS *poffset)
 {
   long emit_lituse = 0;
   offsetT addend = exp->X_add_number;
@@ -3051,15 +1202,13 @@ load_expression (targreg, exp, pbasereg, poffset)
 	    addend = 0;
 	  }
 	else
-	  {
-	    lit = add_to_literal_pool (exp->X_add_symbol, 0,
-				       alpha_lita_section, 8);
-	  }
+	  lit = add_to_literal_pool (exp->X_add_symbol, 0,
+				     alpha_lita_section, 8);
 
 	if (lit >= 0x8000)
 	  as_fatal (_("overflow in literal (.lita) table"));
 
-	/* emit "ldq r, lit(gp)" */
+	/* Emit "ldq r, lit(gp)".  */
 
 	if (basereg != alpha_gp_register && targreg == basereg)
 	  {
@@ -3072,6 +1221,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 	  }
 	else
 	  set_tok_reg (newtok[0], targreg);
+
 	set_tok_sym (newtok[1], alpha_lita_symbol, lit);
 	set_tok_preg (newtok[2], alpha_gp_register);
 
@@ -3082,7 +1232,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 	insn.sequence = emit_lituse = next_sequence_num--;
 #endif /* OBJ_ECOFF */
 #ifdef OBJ_ELF
-	/* emit "ldq r, gotoff(gp)" */
+	/* Emit "ldq r, gotoff(gp)".  */
 
 	if (basereg != alpha_gp_register && targreg == basereg)
 	  {
@@ -3107,9 +1257,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 	    addend = 0;
 	  }
 	else
-	  {
-	    set_tok_sym (newtok[1], exp->X_add_symbol, 0);
-	  }
+	  set_tok_sym (newtok[1], exp->X_add_symbol, 0);
 
 	set_tok_preg (newtok[2], alpha_gp_register);
 
@@ -3151,10 +1299,9 @@ load_expression (targreg, exp, pbasereg, poffset)
 		addend = 0;
 	      }
 	    else
-	      {
-		link = add_to_link_pool (alpha_evax_proc.symbol,
-					 exp->X_add_symbol, 0);
-	      }
+	      link = add_to_link_pool (alpha_evax_proc.symbol,
+				       exp->X_add_symbol, 0);
+
 	    set_tok_reg (newtok[0], targreg);
 	    set_tok_const (newtok[1], link);
 	    set_tok_preg (newtok[2], basereg);
@@ -3167,14 +1314,13 @@ load_expression (targreg, exp, pbasereg, poffset)
 #ifndef OBJ_EVAX
 	if (basereg != alpha_gp_register && basereg != AXP_REG_ZERO)
 	  {
-	    /* emit "addq r, base, r" */
+	    /* Emit "addq r, base, r".  */
 
 	    set_tok_reg (newtok[1], basereg);
 	    set_tok_reg (newtok[2], targreg);
 	    assemble_tokens ("addq", newtok, 3, 0);
 	  }
 #endif
-
 	basereg = targreg;
       }
       break;
@@ -3215,9 +1361,8 @@ load_expression (targreg, exp, pbasereg, poffset)
       long seq_num = next_sequence_num--;
 
       /* For 64-bit addends, just put it in the literal pool.  */
-
 #ifdef OBJ_EVAX
-      /* emit "ldq targreg, lit(basereg)"  */
+      /* Emit "ldq targreg, lit(basereg)".  */
       lit = add_to_link_pool (alpha_evax_proc.symbol,
 			      section_symbol (absolute_section), addend);
       set_tok_reg (newtok[0], targreg);
@@ -3244,7 +1389,7 @@ load_expression (targreg, exp, pbasereg, poffset)
       if (lit >= 0x8000)
 	as_fatal (_("overflow in literal (.lit8) table"));
 
-      /* emit "lda litreg, .lit8+0x8000" */
+      /* Emit "lda litreg, .lit8+0x8000".  */
 
       if (targreg == basereg)
 	{
@@ -3278,7 +1423,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 
       emit_insn (&insn);
 
-      /* emit "ldq litreg, lit(litreg)" */
+      /* Emit "ldq litreg, lit(litreg)".  */
 
       set_tok_const (newtok[1], lit);
       set_tok_preg (newtok[2], newtok[0].X_add_number);
@@ -3294,7 +1439,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 
       emit_insn (&insn);
 
-      /* emit "addq litreg, base, target" */
+      /* Emit "addq litreg, base, target".  */
 
       if (basereg != AXP_REG_ZERO)
 	{
@@ -3312,7 +1457,7 @@ load_expression (targreg, exp, pbasereg, poffset)
     {
       offsetT low, high, extra, tmp;
 
-      /* for 32-bit operands, break up the addend */
+      /* For 32-bit operands, break up the addend.  */
 
       low = sign_extend_16 (addend);
       tmp = addend - low;
@@ -3332,7 +1477,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 
       if (extra)
 	{
-	  /* emit "ldah r, extra(r) */
+	  /* Emit "ldah r, extra(r).  */
 	  set_tok_const (newtok[1], extra);
 	  assemble_tokens ("ldah", newtok, 3, 0);
 	  set_tok_preg (newtok[2], basereg = targreg);
@@ -3340,7 +1485,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 
       if (high)
 	{
-	  /* emit "ldah r, high(r) */
+	  /* Emit "ldah r, high(r).  */
 	  set_tok_const (newtok[1], high);
 	  assemble_tokens ("ldah", newtok, 3, 0);
 	  basereg = targreg;
@@ -3349,7 +1494,7 @@ load_expression (targreg, exp, pbasereg, poffset)
 
       if ((low && !poffset) || (!poffset && basereg != targreg))
 	{
-	  /* emit "lda r, low(base)" */
+	  /* Emit "lda r, low(base)".  */
 	  set_tok_const (newtok[1], low);
 	  assemble_tokens ("lda", newtok, 3, 0);
 	  basereg = targreg;
@@ -3369,10 +1514,9 @@ load_expression (targreg, exp, pbasereg, poffset)
    large constants.  */
 
 static void
-emit_lda (tok, ntok, unused)
-     const expressionS *tok;
-     int ntok;
-     const PTR unused ATTRIBUTE_UNUSED;
+emit_lda (const expressionS *tok,
+	  int ntok,
+	  const void * unused ATTRIBUTE_UNUSED)
 {
   int basereg;
 
@@ -3388,10 +1532,9 @@ emit_lda (tok, ntok, unused)
    as an implied base register.  */
 
 static void
-emit_ldah (tok, ntok, unused)
-     const expressionS *tok;
-     int ntok ATTRIBUTE_UNUSED;
-     const PTR unused ATTRIBUTE_UNUSED;
+emit_ldah (const expressionS *tok,
+	   int ntok ATTRIBUTE_UNUSED,
+	   const void * unused ATTRIBUTE_UNUSED)
 {
   expressionS newtok[3];
 
@@ -3402,15 +1545,455 @@ emit_ldah (tok, ntok, unused)
   assemble_tokens ("ldah", newtok, 3, 0);
 }
 
+/* Called internally to handle all alignment needs.  This takes care
+   of eliding calls to frag_align if'n the cached current alignment
+   says we've already got it, as well as taking care of the auto-align
+   feature wrt labels.  */
+
+static void
+alpha_align (int n,
+	     char *pfill,
+	     symbolS *label,
+	     int force ATTRIBUTE_UNUSED)
+{
+  if (alpha_current_align >= n)
+    return;
+
+  if (pfill == NULL)
+    {
+      if (subseg_text_p (now_seg))
+	frag_align_code (n, 0);
+      else
+	frag_align (n, 0, 0);
+    }
+  else
+    frag_align (n, *pfill, 0);
+
+  alpha_current_align = n;
+
+  if (label != NULL && S_GET_SEGMENT (label) == now_seg)
+    {
+      symbol_set_frag (label, frag_now);
+      S_SET_VALUE (label, (valueT) frag_now_fix ());
+    }
+
+  record_alignment (now_seg, n);
+
+  /* ??? If alpha_flag_relax && force && elf, record the requested alignment
+     in a reloc for the linker to see.  */
+}
+
+/* Actually output an instruction with its fixup.  */
+
+static void
+emit_insn (struct alpha_insn *insn)
+{
+  char *f;
+  int i;
+
+  /* Take care of alignment duties.  */
+  if (alpha_auto_align_on && alpha_current_align < 2)
+    alpha_align (2, (char *) NULL, alpha_insn_label, 0);
+  if (alpha_current_align > 2)
+    alpha_current_align = 2;
+  alpha_insn_label = NULL;
+
+  /* Write out the instruction.  */
+  f = frag_more (4);
+  md_number_to_chars (f, insn->insn, 4);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (4);
+#endif
+
+  /* Apply the fixups in order.  */
+  for (i = 0; i < insn->nfixups; ++i)
+    {
+      const struct alpha_operand *operand = (const struct alpha_operand *) 0;
+      struct alpha_fixup *fixup = &insn->fixups[i];
+      struct alpha_reloc_tag *info = NULL;
+      int size, pcrel;
+      fixS *fixP;
+
+      /* Some fixups are only used internally and so have no howto.  */
+      if ((int) fixup->reloc < 0)
+	{
+	  operand = &alpha_operands[-(int) fixup->reloc];
+	  size = 4;
+	  pcrel = ((operand->flags & AXP_OPERAND_RELATIVE) != 0);
+	}
+      else if (fixup->reloc > BFD_RELOC_UNUSED
+	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_HI16
+	       || fixup->reloc == BFD_RELOC_ALPHA_GPDISP_LO16)
+	{
+	  size = 2;
+	  pcrel = 0;
+	}
+      else
+	{
+	  reloc_howto_type *reloc_howto
+	    = bfd_reloc_type_lookup (stdoutput, fixup->reloc);
+	  assert (reloc_howto);
+
+	  size = bfd_get_reloc_size (reloc_howto);
+	  assert (size >= 1 && size <= 4);
+
+	  pcrel = reloc_howto->pc_relative;
+	}
+
+      fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size,
+			  &fixup->exp, pcrel, fixup->reloc);
+
+      /* Turn off complaints that the addend is too large for some fixups,
+         and copy in the sequence number for the explicit relocations.  */
+      switch (fixup->reloc)
+	{
+	case BFD_RELOC_ALPHA_HINT:
+	case BFD_RELOC_GPREL32:
+	case BFD_RELOC_GPREL16:
+	case BFD_RELOC_ALPHA_GPREL_HI16:
+	case BFD_RELOC_ALPHA_GPREL_LO16:
+	case BFD_RELOC_ALPHA_GOTDTPREL16:
+	case BFD_RELOC_ALPHA_DTPREL_HI16:
+	case BFD_RELOC_ALPHA_DTPREL_LO16:
+	case BFD_RELOC_ALPHA_DTPREL16:
+	case BFD_RELOC_ALPHA_GOTTPREL16:
+	case BFD_RELOC_ALPHA_TPREL_HI16:
+	case BFD_RELOC_ALPHA_TPREL_LO16:
+	case BFD_RELOC_ALPHA_TPREL16:
+	  fixP->fx_no_overflow = 1;
+	  break;
+
+	case BFD_RELOC_ALPHA_GPDISP_HI16:
+	  fixP->fx_no_overflow = 1;
+	  fixP->fx_addsy = section_symbol (now_seg);
+	  fixP->fx_offset = 0;
+
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  if (++info->n_master > 1)
+	    as_bad (_("too many ldah insns for !gpdisp!%ld"), insn->sequence);
+	  if (info->segment != now_seg)
+	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
+		    insn->sequence);
+	  fixP->tc_fix_data.info = info;
+	  break;
+
+	case BFD_RELOC_ALPHA_GPDISP_LO16:
+	  fixP->fx_no_overflow = 1;
+
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  if (++info->n_slaves > 1)
+	    as_bad (_("too many lda insns for !gpdisp!%ld"), insn->sequence);
+	  if (info->segment != now_seg)
+	    as_bad (_("both insns for !gpdisp!%ld must be in the same section"),
+		    insn->sequence);
+	  fixP->tc_fix_data.info = info;
+	  info->slaves = fixP;
+	  break;
+
+	case BFD_RELOC_ALPHA_LITERAL:
+	case BFD_RELOC_ALPHA_ELF_LITERAL:
+	  fixP->fx_no_overflow = 1;
+
+	  if (insn->sequence == 0)
+	    break;
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  info->master = fixP;
+	  info->n_master++;
+	  if (info->segment != now_seg)
+	    info->multi_section_p = 1;
+	  fixP->tc_fix_data.info = info;
+	  break;
+
+#ifdef RELOC_OP_P
+	case DUMMY_RELOC_LITUSE_ADDR:
+	  fixP->fx_offset = LITUSE_ALPHA_ADDR;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_BASE:
+	  fixP->fx_offset = LITUSE_ALPHA_BASE;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_BYTOFF:
+	  fixP->fx_offset = LITUSE_ALPHA_BYTOFF;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_JSR:
+	  fixP->fx_offset = LITUSE_ALPHA_JSR;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_TLSGD:
+	  fixP->fx_offset = LITUSE_ALPHA_TLSGD;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_TLSLDM:
+	  fixP->fx_offset = LITUSE_ALPHA_TLSLDM;
+	  goto do_lituse;
+	case DUMMY_RELOC_LITUSE_JSRDIRECT:
+	  fixP->fx_offset = LITUSE_ALPHA_JSRDIRECT;
+	  goto do_lituse;
+	do_lituse:
+	  fixP->fx_addsy = section_symbol (now_seg);
+	  fixP->fx_r_type = BFD_RELOC_ALPHA_LITUSE;
+
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSGD)
+	    info->saw_lu_tlsgd = 1;
+	  else if (fixup->reloc == DUMMY_RELOC_LITUSE_TLSLDM)
+	    info->saw_lu_tlsldm = 1;
+	  if (++info->n_slaves > 1)
+	    {
+	      if (info->saw_lu_tlsgd)
+		as_bad (_("too many lituse insns for !lituse_tlsgd!%ld"),
+		        insn->sequence);
+	      else if (info->saw_lu_tlsldm)
+		as_bad (_("too many lituse insns for !lituse_tlsldm!%ld"),
+		        insn->sequence);
+	    }
+	  fixP->tc_fix_data.info = info;
+	  fixP->tc_fix_data.next_reloc = info->slaves;
+	  info->slaves = fixP;
+	  if (info->segment != now_seg)
+	    info->multi_section_p = 1;
+	  break;
+
+	case BFD_RELOC_ALPHA_TLSGD:
+	  fixP->fx_no_overflow = 1;
+
+	  if (insn->sequence == 0)
+	    break;
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  if (info->saw_tlsgd)
+	    as_bad (_("duplicate !tlsgd!%ld"), insn->sequence);
+	  else if (info->saw_tlsldm)
+	    as_bad (_("sequence number in use for !tlsldm!%ld"),
+		    insn->sequence);
+	  else
+	    info->saw_tlsgd = 1;
+	  fixP->tc_fix_data.info = info;
+	  break;
+
+	case BFD_RELOC_ALPHA_TLSLDM:
+	  fixP->fx_no_overflow = 1;
+
+	  if (insn->sequence == 0)
+	    break;
+	  info = get_alpha_reloc_tag (insn->sequence);
+	  if (info->saw_tlsldm)
+	    as_bad (_("duplicate !tlsldm!%ld"), insn->sequence);
+	  else if (info->saw_tlsgd)
+	    as_bad (_("sequence number in use for !tlsgd!%ld"),
+		    insn->sequence);
+	  else
+	    info->saw_tlsldm = 1;
+	  fixP->tc_fix_data.info = info;
+	  break;
+#endif
+	default:
+	  if ((int) fixup->reloc < 0)
+	    {
+	      if (operand->flags & AXP_OPERAND_NOOVERFLOW)
+		fixP->fx_no_overflow = 1;
+	    }
+	  break;
+	}
+    }
+}
+
+/* Insert an operand value into an instruction.  */
+
+static unsigned
+insert_operand (unsigned insn,
+		const struct alpha_operand *operand,
+		offsetT val,
+		char *file,
+		unsigned line)
+{
+  if (operand->bits != 32 && !(operand->flags & AXP_OPERAND_NOOVERFLOW))
+    {
+      offsetT min, max;
+
+      if (operand->flags & AXP_OPERAND_SIGNED)
+	{
+	  max = (1 << (operand->bits - 1)) - 1;
+	  min = -(1 << (operand->bits - 1));
+	}
+      else
+	{
+	  max = (1 << operand->bits) - 1;
+	  min = 0;
+	}
+
+      if (val < min || val > max)
+	as_warn_value_out_of_range (_("operand"), val, min, max, file, line);
+    }
+
+  if (operand->insert)
+    {
+      const char *errmsg = NULL;
+
+      insn = (*operand->insert) (insn, val, &errmsg);
+      if (errmsg)
+	as_warn (errmsg);
+    }
+  else
+    insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
+
+  return insn;
+}
+
+/* Turn an opcode description and a set of arguments into
+   an instruction and a fixup.  */
+
+static void
+assemble_insn (const struct alpha_opcode *opcode,
+	       const expressionS *tok,
+	       int ntok,
+	       struct alpha_insn *insn,
+	       bfd_reloc_code_real_type reloc)
+{
+  const struct alpha_operand *reloc_operand = NULL;
+  const expressionS *reloc_exp = NULL;
+  const unsigned char *argidx;
+  unsigned image;
+  int tokidx = 0;
+
+  memset (insn, 0, sizeof (*insn));
+  image = opcode->opcode;
+
+  for (argidx = opcode->operands; *argidx; ++argidx)
+    {
+      const struct alpha_operand *operand = &alpha_operands[*argidx];
+      const expressionS *t = (const expressionS *) 0;
+
+      if (operand->flags & AXP_OPERAND_FAKE)
+	{
+	  /* Fake operands take no value and generate no fixup.  */
+	  image = insert_operand (image, operand, 0, NULL, 0);
+	  continue;
+	}
+
+      if (tokidx >= ntok)
+	{
+	  switch (operand->flags & AXP_OPERAND_OPTIONAL_MASK)
+	    {
+	    case AXP_OPERAND_DEFAULT_FIRST:
+	      t = &tok[0];
+	      break;
+	    case AXP_OPERAND_DEFAULT_SECOND:
+	      t = &tok[1];
+	      break;
+	    case AXP_OPERAND_DEFAULT_ZERO:
+	      {
+		static expressionS zero_exp;
+		t = &zero_exp;
+		zero_exp.X_op = O_constant;
+		zero_exp.X_unsigned = 1;
+	      }
+	      break;
+	    default:
+	      abort ();
+	    }
+	}
+      else
+	t = &tok[tokidx++];
+
+      switch (t->X_op)
+	{
+	case O_register:
+	case O_pregister:
+	case O_cpregister:
+	  image = insert_operand (image, operand, regno (t->X_add_number),
+				  NULL, 0);
+	  break;
+
+	case O_constant:
+	  image = insert_operand (image, operand, t->X_add_number, NULL, 0);
+	  assert (reloc_operand == NULL);
+	  reloc_operand = operand;
+	  reloc_exp = t;
+	  break;
+
+	default:
+	  /* This is only 0 for fields that should contain registers,
+	     which means this pattern shouldn't have matched.  */
+	  if (operand->default_reloc == 0)
+	    abort ();
+
+	  /* There is one special case for which an insn receives two
+	     relocations, and thus the user-supplied reloc does not
+	     override the operand reloc.  */
+	  if (operand->default_reloc == BFD_RELOC_ALPHA_HINT)
+	    {
+	      struct alpha_fixup *fixup;
+
+	      if (insn->nfixups >= MAX_INSN_FIXUPS)
+		as_fatal (_("too many fixups"));
+
+	      fixup = &insn->fixups[insn->nfixups++];
+	      fixup->exp = *t;
+	      fixup->reloc = BFD_RELOC_ALPHA_HINT;
+	    }
+	  else
+	    {
+	      if (reloc == BFD_RELOC_UNUSED)
+		reloc = operand->default_reloc;
+
+	      assert (reloc_operand == NULL);
+	      reloc_operand = operand;
+	      reloc_exp = t;
+	    }
+	  break;
+	}
+    }
+
+  if (reloc != BFD_RELOC_UNUSED)
+    {
+      struct alpha_fixup *fixup;
+
+      if (insn->nfixups >= MAX_INSN_FIXUPS)
+	as_fatal (_("too many fixups"));
+
+      /* ??? My but this is hacky.  But the OSF/1 assembler uses the same
+	 relocation tag for both ldah and lda with gpdisp.  Choose the
+	 correct internal relocation based on the opcode.  */
+      if (reloc == BFD_RELOC_ALPHA_GPDISP)
+	{
+	  if (strcmp (opcode->name, "ldah") == 0)
+	    reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
+	  else if (strcmp (opcode->name, "lda") == 0)
+	    reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
+	  else
+	    as_bad (_("invalid relocation for instruction"));
+	}
+
+      /* If this is a real relocation (as opposed to a lituse hint), then
+	 the relocation width should match the operand width.  */
+      else if (reloc < BFD_RELOC_UNUSED)
+	{
+	  reloc_howto_type *reloc_howto
+	    = bfd_reloc_type_lookup (stdoutput, reloc);
+	  if (reloc_howto->bitsize != reloc_operand->bits)
+	    {
+	      as_bad (_("invalid relocation for field"));
+	      return;
+	    }
+	}
+
+      fixup = &insn->fixups[insn->nfixups++];
+      if (reloc_exp)
+	fixup->exp = *reloc_exp;
+      else
+	fixup->exp.X_op = O_absent;
+      fixup->reloc = reloc;
+    }
+
+  insn->insn = image;
+}
+
 /* Handle all "simple" integer register loads -- ldq, ldq_l, ldq_u,
    etc.  They differ from the real instructions in that they do simple
    expressions like the lda macro.  */
 
 static void
-emit_ir_load (tok, ntok, opname)
-     const expressionS *tok;
-     int ntok;
-     const PTR opname;
+emit_ir_load (const expressionS *tok,
+	      int ntok,
+	      const void * opname)
 {
   int basereg;
   long lituse;
@@ -3446,10 +2029,9 @@ emit_ir_load (tok, ntok, opname)
    Again, we handle simple expressions.  */
 
 static void
-emit_loadstore (tok, ntok, opname)
-     const expressionS *tok;
-     int ntok;
-     const PTR opname;
+emit_loadstore (const expressionS *tok,
+		int ntok,
+		const void * opname)
 {
   int basereg;
   long lituse;
@@ -3494,10 +2076,9 @@ emit_loadstore (tok, ntok, opname)
 /* Load a half-word or byte as an unsigned value.  */
 
 static void
-emit_ldXu (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_ldXu (const expressionS *tok,
+	   int ntok,
+	   const void * vlgsize)
 {
   if (alpha_target & AXP_OPCODE_BWX)
     emit_ir_load (tok, ntok, ldXu_op[(long) vlgsize]);
@@ -3517,12 +2098,10 @@ emit_ldXu (tok, ntok, vlgsize)
       else
 	basereg = tok[2].X_add_number;
 
-      /* emit "lda $at, exp" */
-
+      /* Emit "lda $at, exp".  */
       lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL);
 
-      /* emit "ldq_u targ, 0($at)" */
-
+      /* Emit "ldq_u targ, 0($at)".  */
       newtok[0] = tok[0];
       set_tok_const (newtok[1], 0);
       set_tok_preg (newtok[2], basereg);
@@ -3539,8 +2118,7 @@ emit_ldXu (tok, ntok, vlgsize)
 
       emit_insn (&insn);
 
-      /* emit "extXl targ, $at, targ" */
-
+      /* Emit "extXl targ, $at, targ".  */
       set_tok_reg (newtok[1], basereg);
       newtok[2] = newtok[0];
       assemble_tokens_to_insn (extXl_op[(long) vlgsize], newtok, 3, &insn);
@@ -3561,10 +2139,9 @@ emit_ldXu (tok, ntok, vlgsize)
 /* Load a half-word or byte as a signed value.  */
 
 static void
-emit_ldX (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_ldX (const expressionS *tok,
+	  int ntok,
+	  const void * vlgsize)
 {
   emit_ldXu (tok, ntok, vlgsize);
   assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1);
@@ -3574,10 +2151,9 @@ emit_ldX (tok, ntok, vlgsize)
    value.  */
 
 static void
-emit_uldXu (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_uldXu (const expressionS *tok,
+	    int ntok,
+	    const void * vlgsize)
 {
   long lgsize = (long) vlgsize;
   expressionS newtok[3];
@@ -3585,40 +2161,34 @@ emit_uldXu (tok, ntok, vlgsize)
   if (alpha_noat_on)
     as_bad (_("macro requires $at register while noat in effect"));
 
-  /* emit "lda $at, exp" */
-
+  /* Emit "lda $at, exp".  */
   memcpy (newtok, tok, sizeof (expressionS) * ntok);
   newtok[0].X_add_number = AXP_REG_AT;
   assemble_tokens ("lda", newtok, ntok, 1);
 
-  /* emit "ldq_u $t9, 0($at)" */
-
+  /* Emit "ldq_u $t9, 0($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_const (newtok[1], 0);
   set_tok_preg (newtok[2], AXP_REG_AT);
   assemble_tokens ("ldq_u", newtok, 3, 1);
 
-  /* emit "ldq_u $t10, size-1($at)" */
-
+  /* Emit "ldq_u $t10, size-1($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_const (newtok[1], (1 << lgsize) - 1);
   assemble_tokens ("ldq_u", newtok, 3, 1);
 
-  /* emit "extXl $t9, $at, $t9" */
-
+  /* Emit "extXl $t9, $at, $t9".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_reg (newtok[1], AXP_REG_AT);
   set_tok_reg (newtok[2], AXP_REG_T9);
   assemble_tokens (extXl_op[lgsize], newtok, 3, 1);
 
-  /* emit "extXh $t10, $at, $t10" */
-
+  /* Emit "extXh $t10, $at, $t10".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_reg (newtok[2], AXP_REG_T10);
   assemble_tokens (extXh_op[lgsize], newtok, 3, 1);
 
-  /* emit "or $t9, $t10, targ" */
-
+  /* Emit "or $t9, $t10, targ".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_reg (newtok[1], AXP_REG_T10);
   newtok[2] = tok[0];
@@ -3630,10 +2200,9 @@ emit_uldXu (tok, ntok, vlgsize)
    don't have to do the sign extension.  */
 
 static void
-emit_uldX (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_uldX (const expressionS *tok,
+	   int ntok,
+	   const void * vlgsize)
 {
   emit_uldXu (tok, ntok, vlgsize);
   assemble_tokens (sextX_op[(long) vlgsize], tok, 1, 1);
@@ -3642,10 +2211,9 @@ emit_uldX (tok, ntok, vlgsize)
 /* Implement the ldil macro.  */
 
 static void
-emit_ldil (tok, ntok, unused)
-     const expressionS *tok;
-     int ntok;
-     const PTR unused ATTRIBUTE_UNUSED;
+emit_ldil (const expressionS *tok,
+	   int ntok,
+	   const void * unused ATTRIBUTE_UNUSED)
 {
   expressionS newtok[2];
 
@@ -3658,10 +2226,9 @@ emit_ldil (tok, ntok, unused)
 /* Store a half-word or byte.  */
 
 static void
-emit_stX (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_stX (const expressionS *tok,
+	  int ntok,
+	  const void * vlgsize)
 {
   int lgsize = (int) (long) vlgsize;
 
@@ -3683,12 +2250,10 @@ emit_stX (tok, ntok, vlgsize)
       else
 	basereg = tok[2].X_add_number;
 
-      /* emit "lda $at, exp" */
-
+      /* Emit "lda $at, exp".  */
       lituse = load_expression (AXP_REG_AT, &tok[1], &basereg, NULL);
 
-      /* emit "ldq_u $t9, 0($at)" */
-
+      /* Emit "ldq_u $t9, 0($at)".  */
       set_tok_reg (newtok[0], AXP_REG_T9);
       set_tok_const (newtok[1], 0);
       set_tok_preg (newtok[2], basereg);
@@ -3705,8 +2270,7 @@ emit_stX (tok, ntok, vlgsize)
 
       emit_insn (&insn);
 
-      /* emit "insXl src, $at, $t10" */
-
+      /* Emit "insXl src, $at, $t10".  */
       newtok[0] = tok[0];
       set_tok_reg (newtok[1], basereg);
       set_tok_reg (newtok[2], AXP_REG_T10);
@@ -3723,8 +2287,7 @@ emit_stX (tok, ntok, vlgsize)
 
       emit_insn (&insn);
 
-      /* emit "mskXl $t9, $at, $t9" */
-
+      /* Emit "mskXl $t9, $at, $t9".  */
       set_tok_reg (newtok[0], AXP_REG_T9);
       newtok[2] = newtok[0];
       assemble_tokens_to_insn (mskXl_op[lgsize], newtok, 3, &insn);
@@ -3740,13 +2303,11 @@ emit_stX (tok, ntok, vlgsize)
 
       emit_insn (&insn);
 
-      /* emit "or $t9, $t10, $t9" */
-
+      /* Emit "or $t9, $t10, $t9".  */
       set_tok_reg (newtok[1], AXP_REG_T10);
       assemble_tokens ("or", newtok, 3, 1);
 
-      /* emit "stq_u $t9, 0($at) */
-
+      /* Emit "stq_u $t9, 0($at).  */
       set_tok_const(newtok[1], 0);
       set_tok_preg (newtok[2], AXP_REG_AT);
       assemble_tokens_to_insn ("stq_u", newtok, 3, &insn);
@@ -3767,80 +2328,68 @@ emit_stX (tok, ntok, vlgsize)
 /* Store an integer to an unaligned address.  */
 
 static void
-emit_ustX (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_ustX (const expressionS *tok,
+	   int ntok,
+	   const void * vlgsize)
 {
   int lgsize = (int) (long) vlgsize;
   expressionS newtok[3];
 
-  /* emit "lda $at, exp" */
-
+  /* Emit "lda $at, exp".  */
   memcpy (newtok, tok, sizeof (expressionS) * ntok);
   newtok[0].X_add_number = AXP_REG_AT;
   assemble_tokens ("lda", newtok, ntok, 1);
 
-  /* emit "ldq_u $9, 0($at)" */
-
+  /* Emit "ldq_u $9, 0($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_const (newtok[1], 0);
   set_tok_preg (newtok[2], AXP_REG_AT);
   assemble_tokens ("ldq_u", newtok, 3, 1);
 
-  /* emit "ldq_u $10, size-1($at)" */
-
+  /* Emit "ldq_u $10, size-1($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_const (newtok[1], (1 << lgsize) - 1);
   assemble_tokens ("ldq_u", newtok, 3, 1);
 
-  /* emit "insXl src, $at, $t11" */
-
+  /* Emit "insXl src, $at, $t11".  */
   newtok[0] = tok[0];
   set_tok_reg (newtok[1], AXP_REG_AT);
   set_tok_reg (newtok[2], AXP_REG_T11);
   assemble_tokens (insXl_op[lgsize], newtok, 3, 1);
 
-  /* emit "insXh src, $at, $t12" */
-
+  /* Emit "insXh src, $at, $t12".  */
   set_tok_reg (newtok[2], AXP_REG_T12);
   assemble_tokens (insXh_op[lgsize], newtok, 3, 1);
 
-  /* emit "mskXl $t9, $at, $t9" */
-
+  /* Emit "mskXl $t9, $at, $t9".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   newtok[2] = newtok[0];
   assemble_tokens (mskXl_op[lgsize], newtok, 3, 1);
 
-  /* emit "mskXh $t10, $at, $t10" */
-
+  /* Emit "mskXh $t10, $at, $t10".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   newtok[2] = newtok[0];
   assemble_tokens (mskXh_op[lgsize], newtok, 3, 1);
 
-  /* emit "or $t9, $t11, $t9" */
-
+  /* Emit "or $t9, $t11, $t9".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_reg (newtok[1], AXP_REG_T11);
   newtok[2] = newtok[0];
   assemble_tokens ("or", newtok, 3, 1);
 
-  /* emit "or $t10, $t12, $t10" */
-
+  /* Emit "or $t10, $t12, $t10".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_reg (newtok[1], AXP_REG_T12);
   newtok[2] = newtok[0];
   assemble_tokens ("or", newtok, 3, 1);
 
-  /* emit "stq_u $t9, 0($at)" */
-
+  /* Emit "stq_u $t9, 0($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T9);
   set_tok_const (newtok[1], 0);
   set_tok_preg (newtok[2], AXP_REG_AT);
   assemble_tokens ("stq_u", newtok, 3, 1);
 
-  /* emit "stq_u $t10, size-1($at)" */
-
+  /* Emit "stq_u $t10, size-1($at)".  */
   set_tok_reg (newtok[0], AXP_REG_T10);
   set_tok_const (newtok[1], (1 << lgsize) - 1);
   assemble_tokens ("stq_u", newtok, 3, 1);
@@ -3850,10 +2399,9 @@ emit_ustX (tok, ntok, vlgsize)
    implemented as "addl $31, $r, $t" in the opcode table.  */
 
 static void
-emit_sextX (tok, ntok, vlgsize)
-     const expressionS *tok;
-     int ntok;
-     const PTR vlgsize;
+emit_sextX (const expressionS *tok,
+	    int ntok,
+	    const void * vlgsize)
 {
   long lgsize = (long) vlgsize;
 
@@ -3864,15 +2412,13 @@ emit_sextX (tok, ntok, vlgsize)
       int bitshift = 64 - 8 * (1 << lgsize);
       expressionS newtok[3];
 
-      /* emit "sll src,bits,dst" */
-
+      /* Emit "sll src,bits,dst".  */
       newtok[0] = tok[0];
       set_tok_const (newtok[1], bitshift);
       newtok[2] = tok[ntok - 1];
       assemble_tokens ("sll", newtok, 3, 1);
 
-      /* emit "sra dst,bits,dst" */
-
+      /* Emit "sra dst,bits,dst".  */
       newtok[0] = newtok[2];
       assemble_tokens ("sra", newtok, 3, 1);
     }
@@ -3886,13 +2432,12 @@ emit_sextX (tok, ntok, vlgsize)
    Don't clobber PV and RA.  */
 
 static void
-emit_division (tok, ntok, symname)
-     const expressionS *tok;
-     int ntok;
-     const PTR symname;
+emit_division (const expressionS *tok,
+	       int ntok,
+	       const void * symname)
 {
   /* DIVISION and MODULUS. Yech.
-   
+
      Convert
         OP x,y,result
      to
@@ -3901,7 +2446,7 @@ emit_division (tok, ntok, symname)
         lda AT,__OP
         jsr AT,(AT),0
         mov R0,result
-    
+
      with appropriate optimizations if R0,R16,R17 are the registers
      specified by the compiler.  */
 
@@ -3921,7 +2466,6 @@ emit_division (tok, ntok, symname)
   if (yr == AXP_REG_R16 && xr == AXP_REG_R17)
     {
       /* They are in exactly the wrong order -- swap through AT.  */
-
       if (alpha_noat_on)
 	as_bad (_("macro requires $at register while noat in effect"));
 
@@ -3985,10 +2529,9 @@ emit_division (tok, ntok, symname)
 #else /* !OBJ_EVAX */
 
 static void
-emit_division (tok, ntok, symname)
-     const expressionS *tok;
-     int ntok;
-     const PTR symname;
+emit_division (const expressionS *tok,
+	       int ntok,
+	       const void * symname)
 {
   /* DIVISION and MODULUS. Yech.
      Convert
@@ -3999,7 +2542,7 @@ emit_division (tok, ntok, symname)
         mov y,t11
         jsr t9,(pv),__OP
         mov t12,result
-    
+
      with appropriate optimizations if t10,t11,t12 are the registers
      specified by the compiler.  */
 
@@ -4092,10 +2635,9 @@ FIXME
    everything.  */
 
 static void
-emit_jsrjmp (tok, ntok, vopname)
-     const expressionS *tok;
-     int ntok;
-     const PTR vopname;
+emit_jsrjmp (const expressionS *tok,
+	     int ntok,
+	     const void * vopname)
 {
   const char *opname = (const char *) vopname;
   struct alpha_insn insn;
@@ -4114,7 +2656,7 @@ emit_jsrjmp (tok, ntok, vopname)
       (tok[tokidx].X_op == O_pregister || tok[tokidx].X_op == O_cpregister))
     r = regno (tok[tokidx++].X_add_number);
 #ifdef OBJ_EVAX
-  /* keep register if jsr $n.<sym>  */
+  /* Keep register if jsr $n.<sym>.  */
 #else
   else
     {
@@ -4152,10 +2694,9 @@ emit_jsrjmp (tok, ntok, vopname)
    counterparts in that everything can be defaulted.  */
 
 static void
-emit_retjcr (tok, ntok, vopname)
-     const expressionS *tok;
-     int ntok;
-     const PTR vopname;
+emit_retjcr (const expressionS *tok,
+	     int ntok,
+	     const void * vopname)
 {
   const char *opname = (const char *) vopname;
   expressionS newtok[3];
@@ -4183,6 +2724,482 @@ emit_retjcr (tok, ntok, vopname)
 
   assemble_tokens (opname, newtok, 3, 0);
 }
+
+/* Implement the ldgp macro.  */
+
+static void
+emit_ldgp (const expressionS *tok,
+	   int ntok ATTRIBUTE_UNUSED,
+	   const void * unused ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_AOUT
+FIXME
+#endif
+#if defined(OBJ_ECOFF) || defined(OBJ_ELF)
+  /* from "ldgp r1,n(r2)", generate "ldah r1,X(R2); lda r1,Y(r1)"
+     with appropriate constants and relocations.  */
+  struct alpha_insn insn;
+  expressionS newtok[3];
+  expressionS addend;
+
+#ifdef OBJ_ECOFF
+  if (regno (tok[2].X_add_number) == AXP_REG_PV)
+    ecoff_set_gp_prolog_size (0);
+#endif
+
+  newtok[0] = tok[0];
+  set_tok_const (newtok[1], 0);
+  newtok[2] = tok[2];
+
+  assemble_tokens_to_insn ("ldah", newtok, 3, &insn);
+
+  addend = tok[1];
+
+#ifdef OBJ_ECOFF
+  if (addend.X_op != O_constant)
+    as_bad (_("can not resolve expression"));
+  addend.X_op = O_symbol;
+  addend.X_add_symbol = alpha_gp_symbol;
+#endif
+
+  insn.nfixups = 1;
+  insn.fixups[0].exp = addend;
+  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_HI16;
+  insn.sequence = next_sequence_num;
+
+  emit_insn (&insn);
+
+  set_tok_preg (newtok[2], tok[0].X_add_number);
+
+  assemble_tokens_to_insn ("lda", newtok, 3, &insn);
+
+#ifdef OBJ_ECOFF
+  addend.X_add_number += 4;
+#endif
+
+  insn.nfixups = 1;
+  insn.fixups[0].exp = addend;
+  insn.fixups[0].reloc = BFD_RELOC_ALPHA_GPDISP_LO16;
+  insn.sequence = next_sequence_num--;
+
+  emit_insn (&insn);
+#endif /* OBJ_ECOFF || OBJ_ELF */
+}
+
+/* The macro table.  */
+
+static const struct alpha_macro alpha_macros[] =
+{
+/* Load/Store macros.  */
+  { "lda",	emit_lda, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldah",	emit_ldah, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
+
+  { "ldl",	emit_ir_load, "ldl",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldl_l",	emit_ir_load, "ldl_l",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldq",	emit_ir_load, "ldq",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldq_l",	emit_ir_load, "ldq_l",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldq_u",	emit_ir_load, "ldq_u",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldf",	emit_loadstore, "ldf",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldg",	emit_loadstore, "ldg",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "lds",	emit_loadstore, "lds",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldt",	emit_loadstore, "ldt",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+
+  { "ldb",	emit_ldX, (void *) 0,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldbu",	emit_ldXu, (void *) 0,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldw",	emit_ldX, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ldwu",	emit_ldXu, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+
+  { "uldw",	emit_uldX, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "uldwu",	emit_uldXu, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "uldl",	emit_uldX, (void *) 2,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "uldlu",	emit_uldXu, (void *) 2,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "uldq",	emit_uldXu, (void *) 3,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+
+  { "ldgp",	emit_ldgp, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_PIR, MACRO_EOA } },
+
+  { "ldi",	emit_lda, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
+  { "ldil",	emit_ldil, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
+  { "ldiq",	emit_lda, NULL,
+    { MACRO_IR, MACRO_EXP, MACRO_EOA } },
+
+  { "stl",	emit_loadstore, "stl",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stl_c",	emit_loadstore, "stl_c",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stq",	emit_loadstore, "stq",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stq_c",	emit_loadstore, "stq_c",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stq_u",	emit_loadstore, "stq_u",
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stf",	emit_loadstore, "stf",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stg",	emit_loadstore, "stg",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "sts",	emit_loadstore, "sts",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stt",	emit_loadstore, "stt",
+    { MACRO_FPR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+
+  { "stb",	emit_stX, (void *) 0,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "stw",	emit_stX, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ustw",	emit_ustX, (void *) 1,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ustl",	emit_ustX, (void *) 2,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+  { "ustq",	emit_ustX, (void *) 3,
+    { MACRO_IR, MACRO_EXP, MACRO_OPIR, MACRO_EOA } },
+
+/* Arithmetic macros.  */
+
+  { "sextb",	emit_sextX, (void *) 0,
+    { MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EOA,
+      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },
+  { "sextw",	emit_sextX, (void *) 1,
+    { MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EOA,
+      /* MACRO_EXP, MACRO_IR, MACRO_EOA */ } },
+
+  { "divl",	emit_division, "__divl",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "divlu",	emit_division, "__divlu",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "divq",	emit_division, "__divq",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "divqu",	emit_division, "__divqu",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "reml",	emit_division, "__reml",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "remlu",	emit_division, "__remlu",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "remq",	emit_division, "__remq",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+  { "remqu",	emit_division, "__remqu",
+    { MACRO_IR, MACRO_IR, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_IR, MACRO_EOA,
+      /* MACRO_IR, MACRO_EXP, MACRO_IR, MACRO_EOA,
+      MACRO_IR, MACRO_EXP, MACRO_EOA */ } },
+
+  { "jsr",	emit_jsrjmp, "jsr",
+    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
+      MACRO_PIR, MACRO_EOA,
+      MACRO_IR,  MACRO_EXP, MACRO_EOA,
+      MACRO_EXP, MACRO_EOA } },
+  { "jmp",	emit_jsrjmp, "jmp",
+    { MACRO_PIR, MACRO_EXP, MACRO_EOA,
+      MACRO_PIR, MACRO_EOA,
+      MACRO_IR,  MACRO_EXP, MACRO_EOA,
+      MACRO_EXP, MACRO_EOA } },
+  { "ret",	emit_retjcr, "ret",
+    { MACRO_IR, MACRO_EXP, MACRO_EOA,
+      MACRO_IR, MACRO_EOA,
+      MACRO_PIR, MACRO_EXP, MACRO_EOA,
+      MACRO_PIR, MACRO_EOA,
+      MACRO_EXP, MACRO_EOA,
+      MACRO_EOA } },
+  { "jcr",	emit_retjcr, "jcr",
+    { MACRO_IR,  MACRO_EXP, MACRO_EOA,
+      MACRO_IR,  MACRO_EOA,
+      MACRO_PIR, MACRO_EXP, MACRO_EOA,
+      MACRO_PIR, MACRO_EOA,
+      MACRO_EXP, MACRO_EOA,
+      MACRO_EOA } },
+  { "jsr_coroutine",	emit_retjcr, "jcr",
+    { MACRO_IR,  MACRO_EXP, MACRO_EOA,
+      MACRO_IR,  MACRO_EOA,
+      MACRO_PIR, MACRO_EXP, MACRO_EOA,
+      MACRO_PIR, MACRO_EOA,
+      MACRO_EXP, MACRO_EOA,
+      MACRO_EOA } },
+};
+
+static const unsigned int alpha_num_macros
+  = sizeof (alpha_macros) / sizeof (*alpha_macros);
+
+/* Search forward through all variants of a macro looking for a syntax
+   match.  */
+
+static const struct alpha_macro *
+find_macro_match (const struct alpha_macro *first_macro,
+		  const expressionS *tok,
+		  int *pntok)
+
+{
+  const struct alpha_macro *macro = first_macro;
+  int ntok = *pntok;
+
+  do
+    {
+      const enum alpha_macro_arg *arg = macro->argsets;
+      int tokidx = 0;
+
+      while (*arg)
+	{
+	  switch (*arg)
+	    {
+	    case MACRO_EOA:
+	      if (tokidx == ntok)
+		return macro;
+	      else
+		tokidx = 0;
+	      break;
+
+	      /* Index register.  */
+	    case MACRO_IR:
+	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
+		  || !is_ir_num (tok[tokidx].X_add_number))
+		goto match_failed;
+	      ++tokidx;
+	      break;
+
+	      /* Parenthesized index register.  */
+	    case MACRO_PIR:
+	      if (tokidx >= ntok || tok[tokidx].X_op != O_pregister
+		  || !is_ir_num (tok[tokidx].X_add_number))
+		goto match_failed;
+	      ++tokidx;
+	      break;
+
+	      /* Optional parenthesized index register.  */
+	    case MACRO_OPIR:
+	      if (tokidx < ntok && tok[tokidx].X_op == O_pregister
+		  && is_ir_num (tok[tokidx].X_add_number))
+		++tokidx;
+	      break;
+
+	      /* Leading comma with a parenthesized index register.  */
+	    case MACRO_CPIR:
+	      if (tokidx >= ntok || tok[tokidx].X_op != O_cpregister
+		  || !is_ir_num (tok[tokidx].X_add_number))
+		goto match_failed;
+	      ++tokidx;
+	      break;
+
+	      /* Floating point register.  */
+	    case MACRO_FPR:
+	      if (tokidx >= ntok || tok[tokidx].X_op != O_register
+		  || !is_fpr_num (tok[tokidx].X_add_number))
+		goto match_failed;
+	      ++tokidx;
+	      break;
+
+	      /* Normal expression.  */
+	    case MACRO_EXP:
+	      if (tokidx >= ntok)
+		goto match_failed;
+	      switch (tok[tokidx].X_op)
+		{
+		case O_illegal:
+		case O_absent:
+		case O_register:
+		case O_pregister:
+		case O_cpregister:
+		case O_literal:
+		case O_lituse_base:
+		case O_lituse_bytoff:
+		case O_lituse_jsr:
+		case O_gpdisp:
+		case O_gprelhigh:
+		case O_gprellow:
+		case O_gprel:
+		case O_samegp:
+		  goto match_failed;
+
+		default:
+		  break;
+		}
+	      ++tokidx;
+	      break;
+
+	    match_failed:
+	      while (*arg != MACRO_EOA)
+		++arg;
+	      tokidx = 0;
+	      break;
+	    }
+	  ++arg;
+	}
+    }
+  while (++macro - alpha_macros < (int) alpha_num_macros
+	 && !strcmp (macro->name, first_macro->name));
+
+  return NULL;
+}
+
+/* Given an opcode name and a pre-tokenized set of arguments, take the
+   opcode all the way through emission.  */
+
+static void
+assemble_tokens (const char *opname,
+		 const expressionS *tok,
+		 int ntok,
+		 int local_macros_on)
+{
+  int found_something = 0;
+  const struct alpha_opcode *opcode;
+  const struct alpha_macro *macro;
+  int cpumatch = 1;
+  bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
+
+#ifdef RELOC_OP_P
+  /* If a user-specified relocation is present, this is not a macro.  */
+  if (ntok && USER_RELOC_P (tok[ntok - 1].X_op))
+    {
+      reloc = ALPHA_RELOC_TABLE (tok[ntok - 1].X_op)->reloc;
+      ntok--;
+    }
+  else
+#endif
+  if (local_macros_on)
+    {
+      macro = ((const struct alpha_macro *)
+	       hash_find (alpha_macro_hash, opname));
+      if (macro)
+	{
+	  found_something = 1;
+	  macro = find_macro_match (macro, tok, &ntok);
+	  if (macro)
+	    {
+	      (*macro->emit) (tok, ntok, macro->arg);
+	      return;
+	    }
+	}
+    }
+
+  /* Search opcodes.  */
+  opcode = (const struct alpha_opcode *) hash_find (alpha_opcode_hash, opname);
+  if (opcode)
+    {
+      found_something = 1;
+      opcode = find_opcode_match (opcode, tok, &ntok, &cpumatch);
+      if (opcode)
+	{
+	  struct alpha_insn insn;
+	  assemble_insn (opcode, tok, ntok, &insn, reloc);
+
+	  /* Copy the sequence number for the reloc from the reloc token.  */
+	  if (reloc != BFD_RELOC_UNUSED)
+	    insn.sequence = tok[ntok].X_add_number;
+
+	  emit_insn (&insn);
+	  return;
+	}
+    }
+
+  if (found_something)
+    {
+      if (cpumatch)
+	as_bad (_("inappropriate arguments for opcode `%s'"), opname);
+      else
+	as_bad (_("opcode `%s' not supported for target %s"), opname,
+		alpha_target_name);
+    }
+  else
+    as_bad (_("unknown opcode `%s'"), opname);
+}
+
+#ifdef OBJ_EVAX
+
+/* Add symbol+addend to link pool.
+   Return offset from basesym to entry in link pool.
+
+   Add new fixup only if offset isn't 16bit.  */
+
+valueT
+add_to_link_pool (symbolS *basesym,
+		  symbolS *sym,
+		  offsetT addend)
+{
+  segT current_section = now_seg;
+  int current_subsec = now_subseg;
+  valueT offset;
+  bfd_reloc_code_real_type reloc_type;
+  char *p;
+  segment_info_type *seginfo = seg_info (alpha_link_section);
+  fixS *fixp;
+
+  offset = - *symbol_get_obj (basesym);
+
+  /* @@ This assumes all entries in a given section will be of the same
+     size...  Probably correct, but unwise to rely on.  */
+  /* This must always be called with the same subsegment.  */
+
+  if (seginfo->frchainP)
+    for (fixp = seginfo->frchainP->fix_root;
+	 fixp != (fixS *) NULL;
+	 fixp = fixp->fx_next, offset += 8)
+      {
+	if (fixp->fx_addsy == sym && fixp->fx_offset == addend)
+	  {
+	    if (range_signed_16 (offset))
+	      {
+		return offset;
+	      }
+	  }
+      }
+
+  /* Not found in 16bit signed range.  */
+
+  subseg_set (alpha_link_section, 0);
+  p = frag_more (8);
+  memset (p, 0, 8);
+
+  fix_new (frag_now, p - frag_now->fr_literal, 8, sym, addend, 0,
+	   BFD_RELOC_64);
+
+  subseg_set (current_section, current_subsec);
+  seginfo->literal_pool_size += 8;
+  return offset;
+}
+
+#endif /* OBJ_EVAX */
 
 /* Assembler directives.  */
 
@@ -4190,8 +3207,7 @@ emit_retjcr (tok, ntok, vopname)
    clears alpha_insn_label and restores auto alignment.  */
 
 static void
-s_alpha_text (i)
-     int i;
+s_alpha_text (int i)
 
 {
 #ifdef OBJ_ELF
@@ -4208,8 +3224,7 @@ s_alpha_text (i)
    clears alpha_insn_label and restores auto alignment.  */
 
 static void
-s_alpha_data (i)
-     int i;
+s_alpha_data (int i)
 {
 #ifdef OBJ_ELF
   obj_elf_data (i);
@@ -4227,15 +3242,13 @@ s_alpha_data (i)
    openVMS constructs a section for every common symbol.  */
 
 static void
-s_alpha_comm (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_comm (int ignore ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT temp;
-  register symbolS *symbolP;
-
+  symbolS *symbolP;
 #ifdef OBJ_EVAX
   segT current_section = now_seg;
   int current_subsec = now_subseg;
@@ -4245,7 +3258,7 @@ s_alpha_comm (ignore)
   name = input_line_pointer;
   c = get_symbol_end ();
 
-  /* just after name is now '\0' */
+  /* Just after name is now '\0'.  */
   p = input_line_pointer;
   *p = c;
 
@@ -4275,7 +3288,7 @@ s_alpha_comm (ignore)
   *p = c;
 
 #ifdef OBJ_EVAX
-  /* alignment might follow  */
+  /* Alignment might follow.  */
   if (*input_line_pointer == ',')
     {
       offsetT align;
@@ -4318,10 +3331,10 @@ s_alpha_comm (ignore)
       subseg_set (new_seg, 0);
       p = frag_more (temp);
       new_seg->flags |= SEC_IS_COMMON;
-      if (! S_IS_DEFINED (symbolP))
-	S_SET_SEGMENT (symbolP, new_seg);
+      S_SET_SEGMENT (symbolP, new_seg);
 #else
       S_SET_VALUE (symbolP, (valueT) temp);
+      S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
 #endif
       S_SET_EXTERNAL (symbolP);
     }
@@ -4343,8 +3356,7 @@ s_alpha_comm (ignore)
    clears alpha_insn_label and restores auto alignment.  */
 
 static void
-s_alpha_rdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_rdata (int ignore ATTRIBUTE_UNUSED)
 {
   int temp;
 
@@ -4364,8 +3376,7 @@ s_alpha_rdata (ignore)
    clears alpha_insn_label and restores auto alignment.  */
 
 static void
-s_alpha_sdata (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_sdata (int ignore ATTRIBUTE_UNUSED)
 {
   int temp;
 
@@ -4403,8 +3414,7 @@ static struct alpha_elf_frame_data *cur_frame_data;
    clears alpha_insn_label and restores auto alignment.  */
 
 static void
-s_alpha_section (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_section (int ignore ATTRIBUTE_UNUSED)
 {
   obj_elf_section (ignore);
 
@@ -4414,8 +3424,7 @@ s_alpha_section (ignore)
 }
 
 static void
-s_alpha_ent (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+s_alpha_ent (int dummy ATTRIBUTE_UNUSED)
 {
   if (ECOFF_DEBUGGING)
     ecoff_directive_ent (0);
@@ -4467,8 +3476,7 @@ s_alpha_ent (dummy)
 }
 
 static void
-s_alpha_end (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+s_alpha_end (int dummy ATTRIBUTE_UNUSED)
 {
   if (ECOFF_DEBUGGING)
     ecoff_directive_end (0);
@@ -4517,8 +3525,7 @@ s_alpha_end (dummy)
 }
 
 static void
-s_alpha_mask (fp)
-     int fp;
+s_alpha_mask (int fp)
 {
   if (ECOFF_DEBUGGING)
     {
@@ -4570,8 +3577,7 @@ s_alpha_mask (fp)
 }
 
 static void
-s_alpha_frame (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+s_alpha_frame (int dummy ATTRIBUTE_UNUSED)
 {
   if (ECOFF_DEBUGGING)
     ecoff_directive_frame (0);
@@ -4609,8 +3615,7 @@ s_alpha_frame (dummy)
 }
 
 static void
-s_alpha_prologue (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_prologue (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *sym;
   int arg;
@@ -4654,8 +3659,7 @@ s_alpha_prologue (ignore)
 static char *first_file_directive;
 
 static void
-s_alpha_file (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_file (int ignore ATTRIBUTE_UNUSED)
 {
   /* Save the first .file directive we see, so that we can change our
      minds about whether ecoff debugging should or shouldn't be enabled.  */
@@ -4681,8 +3685,7 @@ s_alpha_file (ignore)
 }
 
 static void
-s_alpha_loc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_loc (int ignore ATTRIBUTE_UNUSED)
 {
   if (ECOFF_DEBUGGING)
     ecoff_directive_loc (0);
@@ -4691,8 +3694,7 @@ s_alpha_loc (ignore)
 }
 
 static void
-s_alpha_stab (n)
-     int n;
+s_alpha_stab (int n)
 {
   /* If we've been undecided about mdebug, make up our minds in favour.  */
   if (alpha_flag_mdebug < 0)
@@ -4718,8 +3720,7 @@ s_alpha_stab (n)
 }
 
 static void
-s_alpha_coff_wrapper (which)
-     int which;
+s_alpha_coff_wrapper (int which)
 {
   static void (* const fns[]) PARAMS ((int)) = {
     ecoff_directive_begin,
@@ -4866,7 +3867,7 @@ s_alpha_usepv (int unused ATTRIBUTE_UNUSED)
       as_bad (_("unknown argument for .usepv"));
       other = 0;
     }
-  
+
   *input_line_pointer = which_end;
   demand_empty_rest_of_line ();
 
@@ -4877,7 +3878,7 @@ s_alpha_usepv (int unused ATTRIBUTE_UNUSED)
 /* Standard calling conventions leaves the CFA at $30 on entry.  */
 
 void
-alpha_cfi_frame_initial_instructions ()
+alpha_cfi_frame_initial_instructions (void)
 {
   cfi_add_CFA_def_cfa_register (30);
 }
@@ -4887,8 +3888,7 @@ alpha_cfi_frame_initial_instructions ()
 /* Handle the section specific pseudo-op.  */
 
 static void
-s_alpha_section (secid)
-     int secid;
+s_alpha_section (int secid)
 {
   int temp;
 #define EVAX_SECTION_COUNT 5
@@ -4912,8 +3912,7 @@ s_alpha_section (secid)
 /* Parse .ent directives.  */
 
 static void
-s_alpha_ent (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_ent (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *symbol;
   expressionS symexpr;
@@ -4948,8 +3947,7 @@ s_alpha_ent (ignore)
 /* Parse .frame <framreg>,<framesize>,RA,<rsa_offset> directives.  */
 
 static void
-s_alpha_frame (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_frame (int ignore ATTRIBUTE_UNUSED)
 {
   long val;
 
@@ -4980,8 +3978,7 @@ s_alpha_frame (ignore)
 }
 
 static void
-s_alpha_pdesc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_pdesc (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char name_end;
@@ -5036,17 +4033,14 @@ s_alpha_pdesc (ignore)
   name_end = get_symbol_end ();
 
   if (strncmp (name, "stack", 5) == 0)
-    {
-      alpha_evax_proc.pdsckind = PDSC_S_K_KIND_FP_STACK;
-    }
+    alpha_evax_proc.pdsckind = PDSC_S_K_KIND_FP_STACK;
+
   else if (strncmp (name, "reg", 3) == 0)
-    {
-      alpha_evax_proc.pdsckind = PDSC_S_K_KIND_FP_REGISTER;
-    }
+    alpha_evax_proc.pdsckind = PDSC_S_K_KIND_FP_REGISTER;
+
   else if (strncmp (name, "null", 4) == 0)
-    {
-      alpha_evax_proc.pdsckind = PDSC_S_K_KIND_NULL;
-    }
+    alpha_evax_proc.pdsckind = PDSC_S_K_KIND_NULL;
+
   else
     {
       as_fatal (_("unknown procedure kind"));
@@ -5131,10 +4125,9 @@ s_alpha_pdesc (ignore)
 /* Support for crash debug on vms.  */
 
 static void
-s_alpha_name (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_name (int ignore ATTRIBUTE_UNUSED)
 {
-  register char *p;
+  char *p;
   expressionS exp;
   segment_info_type *seginfo = seg_info (alpha_link_section);
 
@@ -5167,8 +4160,7 @@ s_alpha_name (ignore)
 }
 
 static void
-s_alpha_linkage (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_linkage (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS exp;
   char *p;
@@ -5193,8 +4185,7 @@ s_alpha_linkage (ignore)
 }
 
 static void
-s_alpha_code_address (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_code_address (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS exp;
   char *p;
@@ -5205,9 +4196,7 @@ s_alpha_code_address (ignore)
 
   expression (&exp);
   if (exp.X_op != O_symbol)
-    {
-      as_fatal (_("No symbol after .code_address"));
-    }
+    as_fatal (_("No symbol after .code_address"));
   else
     {
       p = frag_more (8);
@@ -5219,8 +4208,7 @@ s_alpha_code_address (ignore)
 }
 
 static void
-s_alpha_fp_save (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_fp_save (int ignore ATTRIBUTE_UNUSED)
 {
 
   alpha_evax_proc.fp_save = tc_get_register (1);
@@ -5229,8 +4217,7 @@ s_alpha_fp_save (ignore)
 }
 
 static void
-s_alpha_mask (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_mask (int ignore ATTRIBUTE_UNUSED)
 {
   long val;
 
@@ -5248,8 +4235,7 @@ s_alpha_mask (ignore)
 }
 
 static void
-s_alpha_fmask (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_fmask (int ignore ATTRIBUTE_UNUSED)
 {
   long val;
 
@@ -5267,8 +4253,7 @@ s_alpha_fmask (ignore)
 }
 
 static void
-s_alpha_end (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_end (int ignore ATTRIBUTE_UNUSED)
 {
   char c;
 
@@ -5279,8 +4264,7 @@ s_alpha_end (ignore)
 }
 
 static void
-s_alpha_file (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_file (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *s;
   int length;
@@ -5302,8 +4286,7 @@ s_alpha_file (ignore)
 /* Handle the .gprel32 pseudo op.  */
 
 static void
-s_alpha_gprel32 (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_gprel32 (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS e;
   char *p;
@@ -5357,8 +4340,7 @@ s_alpha_gprel32 (ignore)
    correctly aligned.  */
 
 static void
-s_alpha_float_cons (type)
-     int type;
+s_alpha_float_cons (int type)
 {
   int log_size;
 
@@ -5397,8 +4379,7 @@ s_alpha_float_cons (type)
    parse it.  */
 
 static void
-s_alpha_proc (is_static)
-     int is_static ATTRIBUTE_UNUSED;
+s_alpha_proc (int is_static ATTRIBUTE_UNUSED)
 {
   char *name;
   char c;
@@ -5406,7 +4387,7 @@ s_alpha_proc (is_static)
   symbolS *symbolP;
   int temp;
 
-  /* Takes ".proc name,nargs"  */
+  /* Takes ".proc name,nargs".  */
   SKIP_WHITESPACE ();
   name = input_line_pointer;
   c = get_symbol_end ();
@@ -5436,8 +4417,7 @@ s_alpha_proc (is_static)
    the assembler features.  */
 
 static void
-s_alpha_set (x)
-     int x ATTRIBUTE_UNUSED;
+s_alpha_set (int x ATTRIBUTE_UNUSED)
 {
   char *name, ch, *s;
   int yesno = 1;
@@ -5473,21 +4453,13 @@ s_alpha_set (x)
    the $gp register.  */
 
 static void
-s_alpha_base (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_base (int ignore ATTRIBUTE_UNUSED)
 {
-#if 0
-  if (first_32bit_quadrant)
-    {
-      /* not fatal, but it might not work in the end */
-      as_warn (_("File overrides no-base-register option."));
-      first_32bit_quadrant = 0;
-    }
-#endif
-
   SKIP_WHITESPACE ();
+
   if (*input_line_pointer == '$')
-    {				/* $rNN form */
+    {
+      /* $rNN form.  */
       input_line_pointer++;
       if (*input_line_pointer == 'r')
 	input_line_pointer++;
@@ -5508,8 +4480,7 @@ s_alpha_base (ignore)
    way the MIPS port does: .align 0 turns off auto alignment.  */
 
 static void
-s_alpha_align (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_alpha_align (int ignore ATTRIBUTE_UNUSED)
 {
   int align;
   char fill, *pfill;
@@ -5552,8 +4523,7 @@ s_alpha_align (ignore)
 /* Hook the normal string processor to reset known alignment.  */
 
 static void
-s_alpha_stringer (terminate)
-     int terminate;
+s_alpha_stringer (int terminate)
 {
   alpha_current_align = 0;
   alpha_insn_label = NULL;
@@ -5563,8 +4533,7 @@ s_alpha_stringer (terminate)
 /* Hook the normal space processing to reset known alignment.  */
 
 static void
-s_alpha_space (ignore)
-     int ignore;
+s_alpha_space (int ignore)
 {
   alpha_current_align = 0;
   alpha_insn_label = NULL;
@@ -5574,8 +4543,7 @@ s_alpha_space (ignore)
 /* Hook into cons for auto-alignment.  */
 
 void
-alpha_cons_align (size)
-     int size;
+alpha_cons_align (int size)
 {
   int log_size;
 
@@ -5594,8 +4562,7 @@ alpha_cons_align (size)
    pseudos.  We just turn off auto-alignment and call down to cons.  */
 
 static void
-s_alpha_ucons (bytes)
-     int bytes;
+s_alpha_ucons (int bytes)
 {
   int hold = alpha_auto_align_on;
   alpha_auto_align_on = 0;
@@ -5606,8 +4573,7 @@ s_alpha_ucons (bytes)
 /* Switch the working cpu type.  */
 
 static void
-s_alpha_arch (ignored)
-     int ignored ATTRIBUTE_UNUSED;
+s_alpha_arch (int ignored ATTRIBUTE_UNUSED)
 {
   char *name, ch;
   const struct cpu_type *p;
@@ -5633,9 +4599,7 @@ found:
 /* print token expression with alpha specific extension.  */
 
 static void
-alpha_print_token (f, exp)
-     FILE *f;
-     const expressionS *exp;
+alpha_print_token (FILE *f, const expressionS *exp)
 {
   switch (exp->X_op)
     {
@@ -5660,9 +4624,10 @@ alpha_print_token (f, exp)
 
 /* The target specific pseudo-ops which we support.  */
 
-const pseudo_typeS md_pseudo_table[] = {
+const pseudo_typeS md_pseudo_table[] =
+{
 #ifdef OBJ_ECOFF
-  {"comm", s_alpha_comm, 0},	/* osf1 compiler does this */
+  {"comm", s_alpha_comm, 0},	/* OSF1 compiler does this.  */
   {"rdata", s_alpha_rdata, 0},
 #endif
   {"text", s_alpha_text, 0},
@@ -5769,29 +4734,6 @@ const pseudo_typeS md_pseudo_table[] = {
   {NULL, 0, 0},
 };
 
-/* Build a BFD section with its flags set appropriately for the .lita,
-   .lit8, or .lit4 sections.  */
-
-static void
-create_literal_section (name, secp, symp)
-     const char *name;
-     segT *secp;
-     symbolS **symp;
-{
-  segT current_section = now_seg;
-  int current_subsec = now_subseg;
-  segT new_sec;
-
-  *secp = new_sec = subseg_new (name, 0);
-  subseg_set (current_section, current_subsec);
-  bfd_set_section_alignment (stdoutput, new_sec, 4);
-  bfd_set_section_flags (stdoutput, new_sec,
-			 SEC_RELOC | SEC_ALLOC | SEC_LOAD | SEC_READONLY
-			 | SEC_DATA);
-
-  S_CLEAR_EXTERNAL (*symp = section_symbol (new_sec));
-}
-
 #ifdef OBJ_ECOFF
 
 /* @@@ GP selection voodoo.  All of this seems overly complicated and
@@ -5799,10 +4741,10 @@ create_literal_section (name, secp, symp)
 static inline void maybe_set_gp PARAMS ((asection *));
 
 static inline void
-maybe_set_gp (sec)
-     asection *sec;
+maybe_set_gp (asection *sec)
 {
   bfd_vma vma;
+
   if (!sec)
     return;
   vma = bfd_get_section_vma (foo, sec);
@@ -5811,7 +4753,7 @@ maybe_set_gp (sec)
 }
 
 static void
-select_gp_value ()
+select_gp_value (void)
 {
   assert (alpha_gp_value == 0);
 
@@ -5821,12 +4763,6 @@ select_gp_value ()
 
   /* Select the smallest VMA of these existing sections.  */
   maybe_set_gp (alpha_lita_section);
-#if 0
-  /* These were disabled before -- should we use them?  */
-  maybe_set_gp (sdata);
-  maybe_set_gp (lit8_sec);
-  maybe_set_gp (lit4_sec);
-#endif
 
 /* @@ Will a simple 0x8000 work here?  If not, why not?  */
 #define GP_ADJUSTMENT	(0x8000 - 0x10)
@@ -5845,9 +4781,7 @@ select_gp_value ()
 /* Map 's' to SHF_ALPHA_GPREL.  */
 
 int
-alpha_elf_section_letter (letter, ptr_msg)
-     int letter;
-     char **ptr_msg;
+alpha_elf_section_letter (int letter, char **ptr_msg)
 {
   if (letter == 's')
     return SHF_ALPHA_GPREL;
@@ -5859,9 +4793,7 @@ alpha_elf_section_letter (letter, ptr_msg)
 /* Map SHF_ALPHA_GPREL to SEC_SMALL_DATA.  */
 
 flagword
-alpha_elf_section_flags (flags, attr, type)
-     flagword flags;
-     int attr, type ATTRIBUTE_UNUSED;
+alpha_elf_section_flags (flagword flags, int attr, int type ATTRIBUTE_UNUSED)
 {
   if (attr & SHF_ALPHA_GPREL)
     flags |= SEC_SMALL_DATA;
@@ -5869,54 +4801,15 @@ alpha_elf_section_flags (flags, attr, type)
 }
 #endif /* OBJ_ELF */
 
-/* Called internally to handle all alignment needs.  This takes care
-   of eliding calls to frag_align if'n the cached current alignment
-   says we've already got it, as well as taking care of the auto-align
-   feature wrt labels.  */
-
-static void
-alpha_align (n, pfill, label, force)
-     int n;
-     char *pfill;
-     symbolS *label;
-     int force ATTRIBUTE_UNUSED;
-{
-  if (alpha_current_align >= n)
-    return;
-
-  if (pfill == NULL)
-    {
-      if (subseg_text_p (now_seg))
-	frag_align_code (n, 0);
-      else
-	frag_align (n, 0, 0);
-    }
-  else
-    frag_align (n, *pfill, 0);
-
-  alpha_current_align = n;
-
-  if (label != NULL && S_GET_SEGMENT (label) == now_seg)
-    {
-      symbol_set_frag (label, frag_now);
-      S_SET_VALUE (label, (valueT) frag_now_fix ());
-    }
-
-  record_alignment (now_seg, n);
-
-  /* ??? If alpha_flag_relax && force && elf, record the requested alignment
-     in a reloc for the linker to see.  */
-}
-
 /* This is called from HANDLE_ALIGN in write.c.  Fill in the contents
    of an rs_align_code fragment.  */
 
 void
-alpha_handle_align (fragp)
-     fragS *fragp;
+alpha_handle_align (fragS *fragp)
 {
   static char const unop[4] = { 0x00, 0x00, 0xfe, 0x2f };
-  static char const nopunop[8] = {
+  static char const nopunop[8] =
+  {
     0x1f, 0x04, 0xff, 0x47,
     0x00, 0x00, 0xfe, 0x2f
   };
@@ -5952,6 +4845,866 @@ alpha_handle_align (fragp)
   fragp->fr_fix += fix;
   fragp->fr_var = 8;
 }
+
+/* Public interface functions.  */
+
+/* This function is called once, at assembler startup time.  It sets
+   up all the tables, etc. that the MD part of the assembler will
+   need, that can be determined before arguments are parsed.  */
+
+void
+md_begin (void)
+{
+  unsigned int i;
+
+  /* Verify that X_op field is wide enough.  */
+  {
+    expressionS e;
+
+    e.X_op = O_max;
+    assert (e.X_op == O_max);
+  }
+
+  /* Create the opcode hash table.  */
+  alpha_opcode_hash = hash_new ();
+
+  for (i = 0; i < alpha_num_opcodes;)
+    {
+      const char *name, *retval, *slash;
+
+      name = alpha_opcodes[i].name;
+      retval = hash_insert (alpha_opcode_hash, name, (void *) &alpha_opcodes[i]);
+      if (retval)
+	as_fatal (_("internal error: can't hash opcode `%s': %s"),
+		  name, retval);
+
+      /* Some opcodes include modifiers of various sorts with a "/mod"
+	 syntax, like the architecture manual suggests.  However, for
+	 use with gcc at least, we also need access to those same opcodes
+	 without the "/".  */
+
+      if ((slash = strchr (name, '/')) != NULL)
+	{
+	  char *p = xmalloc (strlen (name));
+
+	  memcpy (p, name, slash - name);
+	  strcpy (p + (slash - name), slash + 1);
+
+	  (void) hash_insert (alpha_opcode_hash, p, (void *) &alpha_opcodes[i]);
+	  /* Ignore failures -- the opcode table does duplicate some
+	     variants in different forms, like "hw_stq" and "hw_st/q".  */
+	}
+
+      while (++i < alpha_num_opcodes
+	     && (alpha_opcodes[i].name == name
+		 || !strcmp (alpha_opcodes[i].name, name)))
+	continue;
+    }
+
+  /* Create the macro hash table.  */
+  alpha_macro_hash = hash_new ();
+
+  for (i = 0; i < alpha_num_macros;)
+    {
+      const char *name, *retval;
+
+      name = alpha_macros[i].name;
+      retval = hash_insert (alpha_macro_hash, name, (void *) &alpha_macros[i]);
+      if (retval)
+	as_fatal (_("internal error: can't hash macro `%s': %s"),
+		  name, retval);
+
+      while (++i < alpha_num_macros
+	     && (alpha_macros[i].name == name
+		 || !strcmp (alpha_macros[i].name, name)))
+	continue;
+    }
+
+  /* Construct symbols for each of the registers.  */
+  for (i = 0; i < 32; ++i)
+    {
+      char name[4];
+
+      sprintf (name, "$%d", i);
+      alpha_register_table[i] = symbol_create (name, reg_section, i,
+					       &zero_address_frag);
+    }
+
+  for (; i < 64; ++i)
+    {
+      char name[5];
+
+      sprintf (name, "$f%d", i - 32);
+      alpha_register_table[i] = symbol_create (name, reg_section, i,
+					       &zero_address_frag);
+    }
+
+  /* Create the special symbols and sections we'll be using.  */
+
+  /* So .sbss will get used for tiny objects.  */
+  bfd_set_gp_size (stdoutput, g_switch_value);
+
+#ifdef OBJ_ECOFF
+  create_literal_section (".lita", &alpha_lita_section, &alpha_lita_symbol);
+
+  /* For handling the GP, create a symbol that won't be output in the
+     symbol table.  We'll edit it out of relocs later.  */
+  alpha_gp_symbol = symbol_create ("<GP value>", alpha_lita_section, 0x8000,
+				   &zero_address_frag);
+#endif
+
+#ifdef OBJ_EVAX
+  create_literal_section (".link", &alpha_link_section, &alpha_link_symbol);
+#endif
+
+#ifdef OBJ_ELF
+  if (ECOFF_DEBUGGING)
+    {
+      segT sec = subseg_new (".mdebug", (subsegT) 0);
+      bfd_set_section_flags (stdoutput, sec, SEC_HAS_CONTENTS | SEC_READONLY);
+      bfd_set_section_alignment (stdoutput, sec, 3);
+    }
+#endif
+
+  /* Create literal lookup hash table.  */
+  alpha_literal_hash = hash_new ();
+
+  subseg_set (text_section, 0);
+}
+
+/* The public interface to the instruction assembler.  */
+
+void
+md_assemble (char *str)
+{
+  /* Current maximum is 13.  */
+  char opname[32];
+  expressionS tok[MAX_INSN_ARGS];
+  int ntok, trunclen;
+  size_t opnamelen;
+
+  /* Split off the opcode.  */
+  opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/46819");
+  trunclen = (opnamelen < sizeof (opname) - 1
+	      ? opnamelen
+	      : sizeof (opname) - 1);
+  memcpy (opname, str, trunclen);
+  opname[trunclen] = '\0';
+
+  /* Tokenize the rest of the line.  */
+  if ((ntok = tokenize_arguments (str + opnamelen, tok, MAX_INSN_ARGS)) < 0)
+    {
+      if (ntok != TOKENIZE_ERROR_REPORT)
+	as_bad (_("syntax error"));
+
+      return;
+    }
+
+  /* Finish it off.  */
+  assemble_tokens (opname, tok, ntok, alpha_macros_on);
+}
+
+/* Round up a section's size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, seg);
+  valueT mask = ((valueT) 1 << align) - 1;
+
+  return (size + mask) & ~mask;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+extern char *vax_md_atof (int, char *, int *);
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  char *t;
+
+  switch (type)
+    {
+      /* VAX floats.  */
+    case 'G':
+      /* VAX md_atof doesn't like "G" for some reason.  */
+      type = 'g';
+    case 'F':
+    case 'D':
+      return vax_md_atof (type, litP, sizeP);
+
+      /* IEEE floats.  */
+    case 'f':
+      prec = 2;
+      break;
+
+    case 'd':
+      prec = 4;
+      break;
+
+    case 'x':
+    case 'X':
+      prec = 6;
+      break;
+
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to MD_ATOF()");
+    }
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  for (wordP = words + prec - 1; prec--;)
+    {
+      md_number_to_chars (litP, (long) (*wordP--), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+/* Take care of the target-specific command-line options.  */
+
+int
+md_parse_option (int c, char *arg)
+{
+  switch (c)
+    {
+    case 'F':
+      alpha_nofloats_on = 1;
+      break;
+
+    case OPTION_32ADDR:
+      alpha_addr32_on = 1;
+      break;
+
+    case 'g':
+      alpha_debug = 1;
+      break;
+
+    case 'G':
+      g_switch_value = atoi (arg);
+      break;
+
+    case 'm':
+      {
+	const struct cpu_type *p;
+
+	for (p = cpu_types; p->name; ++p)
+	  if (strcmp (arg, p->name) == 0)
+	    {
+	      alpha_target_name = p->name, alpha_target = p->flags;
+	      goto found;
+	    }
+	as_warn (_("Unknown CPU identifier `%s'"), arg);
+      found:;
+      }
+      break;
+
+#ifdef OBJ_EVAX
+    case '+':			/* For g++.  Hash any name > 63 chars long.  */
+      alpha_flag_hash_long_names = 1;
+      break;
+
+    case 'H':			/* Show new symbol after hash truncation.  */
+      alpha_flag_show_after_trunc = 1;
+      break;
+
+    case 'h':			/* For gnu-c/vax compatibility.  */
+      break;
+#endif
+
+    case OPTION_RELAX:
+      alpha_flag_relax = 1;
+      break;
+
+#ifdef OBJ_ELF
+    case OPTION_MDEBUG:
+      alpha_flag_mdebug = 1;
+      break;
+    case OPTION_NO_MDEBUG:
+      alpha_flag_mdebug = 0;
+      break;
+#endif
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+/* Print a description of the command-line options that we accept.  */
+
+void
+md_show_usage (FILE *stream)
+{
+  fputs (_("\
+Alpha options:\n\
+-32addr			treat addresses as 32-bit values\n\
+-F			lack floating point instructions support\n\
+-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n\
+			specify variant of Alpha architecture\n\
+-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n\
+			these variants include PALcode opcodes\n"),
+	stream);
+#ifdef OBJ_EVAX
+  fputs (_("\
+VMS options:\n\
+-+			hash encode (don't truncate) names longer than 64 characters\n\
+-H			show new symbol after hash truncation\n"),
+	stream);
+#endif
+}
+
+/* Decide from what point a pc-relative relocation is relative to,
+   relative to the pc-relative fixup.  Er, relatively speaking.  */
+
+long
+md_pcrel_from (fixS *fixP)
+{
+  valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_23_PCREL_S2:
+    case BFD_RELOC_ALPHA_HINT:
+    case BFD_RELOC_ALPHA_BRSGP:
+      return addr + 4;
+    default:
+      return addr;
+    }
+}
+
+/* Attempt to simplify or even eliminate a fixup.  The return value is
+   ignored; perhaps it was once meaningful, but now it is historical.
+   To indicate that a fixup has been eliminated, set fixP->fx_done.
+
+   For ELF, here it is that we transform the GPDISP_HI16 reloc we used
+   internally into the GPDISP reloc used externally.  We had to do
+   this so that we'd have the GPDISP_LO16 reloc as a tag to compute
+   the distance to the "lda" instruction for setting the addend to
+   GPDISP.  */
+
+void
+md_apply_fix (fixS *fixP, valueT * valP, segT seg)
+{
+  char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+  valueT value = * valP;
+  unsigned image, size;
+
+  switch (fixP->fx_r_type)
+    {
+      /* The GPDISP relocations are processed internally with a symbol
+	 referring to the current function's section;  we need to drop
+	 in a value which, when added to the address of the start of
+	 the function, gives the desired GP.  */
+    case BFD_RELOC_ALPHA_GPDISP_HI16:
+      {
+	fixS *next = fixP->fx_next;
+
+	/* With user-specified !gpdisp relocations, we can be missing
+	   the matching LO16 reloc.  We will have already issued an
+	   error message.  */
+	if (next)
+	  fixP->fx_offset = (next->fx_frag->fr_address + next->fx_where
+			     - fixP->fx_frag->fr_address - fixP->fx_where);
+
+	value = (value - sign_extend_16 (value)) >> 16;
+      }
+#ifdef OBJ_ELF
+      fixP->fx_r_type = BFD_RELOC_ALPHA_GPDISP;
+#endif
+      goto do_reloc_gp;
+
+    case BFD_RELOC_ALPHA_GPDISP_LO16:
+      value = sign_extend_16 (value);
+      fixP->fx_offset = 0;
+#ifdef OBJ_ELF
+      fixP->fx_done = 1;
+#endif
+
+    do_reloc_gp:
+      fixP->fx_addsy = section_symbol (seg);
+      md_number_to_chars (fixpos, value, 2);
+      break;
+
+    case BFD_RELOC_16:
+      if (fixP->fx_pcrel)
+	fixP->fx_r_type = BFD_RELOC_16_PCREL;
+      size = 2;
+      goto do_reloc_xx;
+
+    case BFD_RELOC_32:
+      if (fixP->fx_pcrel)
+	fixP->fx_r_type = BFD_RELOC_32_PCREL;
+      size = 4;
+      goto do_reloc_xx;
+
+    case BFD_RELOC_64:
+      if (fixP->fx_pcrel)
+	fixP->fx_r_type = BFD_RELOC_64_PCREL;
+      size = 8;
+
+    do_reloc_xx:
+      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
+	{
+	  md_number_to_chars (fixpos, value, size);
+	  goto done;
+	}
+      return;
+
+#ifdef OBJ_ECOFF
+    case BFD_RELOC_GPREL32:
+      assert (fixP->fx_subsy == alpha_gp_symbol);
+      fixP->fx_subsy = 0;
+      /* FIXME: inherited this obliviousness of `value' -- why?  */
+      md_number_to_chars (fixpos, -alpha_gp_value, 4);
+      break;
+#else
+    case BFD_RELOC_GPREL32:
+#endif
+    case BFD_RELOC_GPREL16:
+    case BFD_RELOC_ALPHA_GPREL_HI16:
+    case BFD_RELOC_ALPHA_GPREL_LO16:
+      return;
+
+    case BFD_RELOC_23_PCREL_S2:
+      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
+	{
+	  image = bfd_getl32 (fixpos);
+	  image = (image & ~0x1FFFFF) | ((value >> 2) & 0x1FFFFF);
+	  goto write_done;
+	}
+      return;
+
+    case BFD_RELOC_ALPHA_HINT:
+      if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
+	{
+	  image = bfd_getl32 (fixpos);
+	  image = (image & ~0x3FFF) | ((value >> 2) & 0x3FFF);
+	  goto write_done;
+	}
+      return;
+
+#ifdef OBJ_ELF
+    case BFD_RELOC_ALPHA_BRSGP:
+      return;
+
+    case BFD_RELOC_ALPHA_TLSGD:
+    case BFD_RELOC_ALPHA_TLSLDM:
+    case BFD_RELOC_ALPHA_GOTDTPREL16:
+    case BFD_RELOC_ALPHA_DTPREL_HI16:
+    case BFD_RELOC_ALPHA_DTPREL_LO16:
+    case BFD_RELOC_ALPHA_DTPREL16:
+    case BFD_RELOC_ALPHA_GOTTPREL16:
+    case BFD_RELOC_ALPHA_TPREL_HI16:
+    case BFD_RELOC_ALPHA_TPREL_LO16:
+    case BFD_RELOC_ALPHA_TPREL16:
+      if (fixP->fx_addsy)
+	S_SET_THREAD_LOCAL (fixP->fx_addsy);
+      return;
+#endif
+
+#ifdef OBJ_ECOFF
+    case BFD_RELOC_ALPHA_LITERAL:
+      md_number_to_chars (fixpos, value, 2);
+      return;
+#endif
+    case BFD_RELOC_ALPHA_ELF_LITERAL:
+    case BFD_RELOC_ALPHA_LITUSE:
+    case BFD_RELOC_ALPHA_LINKAGE:
+    case BFD_RELOC_ALPHA_CODEADDR:
+      return;
+
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_VTABLE_ENTRY:
+      return;
+
+    default:
+      {
+	const struct alpha_operand *operand;
+
+	if ((int) fixP->fx_r_type >= 0)
+	  as_fatal (_("unhandled relocation type %s"),
+		    bfd_get_reloc_code_name (fixP->fx_r_type));
+
+	assert (-(int) fixP->fx_r_type < (int) alpha_num_operands);
+	operand = &alpha_operands[-(int) fixP->fx_r_type];
+
+	/* The rest of these fixups only exist internally during symbol
+	   resolution and have no representation in the object file.
+	   Therefore they must be completely resolved as constants.  */
+
+	if (fixP->fx_addsy != 0
+	    && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("non-absolute expression in constant field"));
+
+	image = bfd_getl32 (fixpos);
+	image = insert_operand (image, operand, (offsetT) value,
+				fixP->fx_file, fixP->fx_line);
+      }
+      goto write_done;
+    }
+
+  if (fixP->fx_addsy != 0 || fixP->fx_pcrel != 0)
+    return;
+  else
+    {
+      as_warn_where (fixP->fx_file, fixP->fx_line,
+		     _("type %d reloc done?\n"), (int) fixP->fx_r_type);
+      goto done;
+    }
+
+write_done:
+  md_number_to_chars (fixpos, image, 4);
+
+done:
+  fixP->fx_done = 1;
+}
+
+/* Look for a register name in the given symbol.  */
+
+symbolS *
+md_undefined_symbol (char *name)
+{
+  if (*name == '$')
+    {
+      int is_float = 0, num;
+
+      switch (*++name)
+	{
+	case 'f':
+	  if (name[1] == 'p' && name[2] == '\0')
+	    return alpha_register_table[AXP_REG_FP];
+	  is_float = 32;
+	  /* Fall through.  */
+
+	case 'r':
+	  if (!ISDIGIT (*++name))
+	    break;
+	  /* Fall through.  */
+
+	case '0': case '1': case '2': case '3': case '4':
+	case '5': case '6': case '7': case '8': case '9':
+	  if (name[1] == '\0')
+	    num = name[0] - '0';
+	  else if (name[0] != '0' && ISDIGIT (name[1]) && name[2] == '\0')
+	    {
+	      num = (name[0] - '0') * 10 + name[1] - '0';
+	      if (num >= 32)
+		break;
+	    }
+	  else
+	    break;
+
+	  if (!alpha_noat_on && (num + is_float) == AXP_REG_AT)
+	    as_warn (_("Used $at without \".set noat\""));
+	  return alpha_register_table[num + is_float];
+
+	case 'a':
+	  if (name[1] == 't' && name[2] == '\0')
+	    {
+	      if (!alpha_noat_on)
+		as_warn (_("Used $at without \".set noat\""));
+	      return alpha_register_table[AXP_REG_AT];
+	    }
+	  break;
+
+	case 'g':
+	  if (name[1] == 'p' && name[2] == '\0')
+	    return alpha_register_table[alpha_gp_register];
+	  break;
+
+	case 's':
+	  if (name[1] == 'p' && name[2] == '\0')
+	    return alpha_register_table[AXP_REG_SP];
+	  break;
+	}
+    }
+  return NULL;
+}
+
+#ifdef OBJ_ECOFF
+/* @@@ Magic ECOFF bits.  */
+
+void
+alpha_frob_ecoff_data (void)
+{
+  select_gp_value ();
+  /* $zero and $f31 are read-only.  */
+  alpha_gprmask &= ~1;
+  alpha_fprmask &= ~1;
+}
+#endif
+
+/* Hook to remember a recently defined label so that the auto-align
+   code can adjust the symbol after we know what alignment will be
+   required.  */
+
+void
+alpha_define_label (symbolS *sym)
+{
+  alpha_insn_label = sym;
+#ifdef OBJ_ELF
+  dwarf2_emit_label (sym);
+#endif
+}
+
+/* Return true if we must always emit a reloc for a type and false if
+   there is some hope of resolving it at assembly time.  */
+
+int
+alpha_force_relocation (fixS *f)
+{
+  if (alpha_flag_relax)
+    return 1;
+
+  switch (f->fx_r_type)
+    {
+    case BFD_RELOC_ALPHA_GPDISP_HI16:
+    case BFD_RELOC_ALPHA_GPDISP_LO16:
+    case BFD_RELOC_ALPHA_GPDISP:
+    case BFD_RELOC_ALPHA_LITERAL:
+    case BFD_RELOC_ALPHA_ELF_LITERAL:
+    case BFD_RELOC_ALPHA_LITUSE:
+    case BFD_RELOC_GPREL16:
+    case BFD_RELOC_GPREL32:
+    case BFD_RELOC_ALPHA_GPREL_HI16:
+    case BFD_RELOC_ALPHA_GPREL_LO16:
+    case BFD_RELOC_ALPHA_LINKAGE:
+    case BFD_RELOC_ALPHA_CODEADDR:
+    case BFD_RELOC_ALPHA_BRSGP:
+    case BFD_RELOC_ALPHA_TLSGD:
+    case BFD_RELOC_ALPHA_TLSLDM:
+    case BFD_RELOC_ALPHA_GOTDTPREL16:
+    case BFD_RELOC_ALPHA_DTPREL_HI16:
+    case BFD_RELOC_ALPHA_DTPREL_LO16:
+    case BFD_RELOC_ALPHA_DTPREL16:
+    case BFD_RELOC_ALPHA_GOTTPREL16:
+    case BFD_RELOC_ALPHA_TPREL_HI16:
+    case BFD_RELOC_ALPHA_TPREL_LO16:
+    case BFD_RELOC_ALPHA_TPREL16:
+      return 1;
+
+    default:
+      break;
+    }
+
+  return generic_force_reloc (f);
+}
+
+/* Return true if we can partially resolve a relocation now.  */
+
+int
+alpha_fix_adjustable (fixS *f)
+{
+  /* Are there any relocation types for which we must generate a
+     reloc but we can adjust the values contained within it?   */
+  switch (f->fx_r_type)
+    {
+    case BFD_RELOC_ALPHA_GPDISP_HI16:
+    case BFD_RELOC_ALPHA_GPDISP_LO16:
+    case BFD_RELOC_ALPHA_GPDISP:
+      return 0;
+
+    case BFD_RELOC_ALPHA_LITERAL:
+    case BFD_RELOC_ALPHA_ELF_LITERAL:
+    case BFD_RELOC_ALPHA_LITUSE:
+    case BFD_RELOC_ALPHA_LINKAGE:
+    case BFD_RELOC_ALPHA_CODEADDR:
+      return 1;
+
+    case BFD_RELOC_VTABLE_ENTRY:
+    case BFD_RELOC_VTABLE_INHERIT:
+      return 0;
+
+    case BFD_RELOC_GPREL16:
+    case BFD_RELOC_GPREL32:
+    case BFD_RELOC_ALPHA_GPREL_HI16:
+    case BFD_RELOC_ALPHA_GPREL_LO16:
+    case BFD_RELOC_23_PCREL_S2:
+    case BFD_RELOC_32:
+    case BFD_RELOC_64:
+    case BFD_RELOC_ALPHA_HINT:
+      return 1;
+
+    case BFD_RELOC_ALPHA_TLSGD:
+    case BFD_RELOC_ALPHA_TLSLDM:
+    case BFD_RELOC_ALPHA_GOTDTPREL16:
+    case BFD_RELOC_ALPHA_DTPREL_HI16:
+    case BFD_RELOC_ALPHA_DTPREL_LO16:
+    case BFD_RELOC_ALPHA_DTPREL16:
+    case BFD_RELOC_ALPHA_GOTTPREL16:
+    case BFD_RELOC_ALPHA_TPREL_HI16:
+    case BFD_RELOC_ALPHA_TPREL_LO16:
+    case BFD_RELOC_ALPHA_TPREL16:
+      /* ??? No idea why we can't return a reference to .tbss+10, but
+	 we're preventing this in the other assemblers.  Follow for now.  */
+      return 0;
+
+#ifdef OBJ_ELF
+    case BFD_RELOC_ALPHA_BRSGP:
+      /* If we have a BRSGP reloc to a local symbol, adjust it to BRADDR and
+         let it get resolved at assembly time.  */
+      {
+	symbolS *sym = f->fx_addsy;
+	const char *name;
+	int offset = 0;
+
+	if (generic_force_reloc (f))
+	  return 0;
+
+	switch (S_GET_OTHER (sym) & STO_ALPHA_STD_GPLOAD)
+	  {
+	  case STO_ALPHA_NOPV:
+	    break;
+	  case STO_ALPHA_STD_GPLOAD:
+	    offset = 8;
+	    break;
+	  default:
+	    if (S_IS_LOCAL (sym))
+	      name = "<local>";
+	    else
+	      name = S_GET_NAME (sym);
+	    as_bad_where (f->fx_file, f->fx_line,
+		_("!samegp reloc against symbol without .prologue: %s"),
+		name);
+	    break;
+	  }
+	f->fx_r_type = BFD_RELOC_23_PCREL_S2;
+	f->fx_offset += offset;
+	return 1;
+      }
+#endif
+
+    default:
+      return 1;
+    }
+}
+
+/* Generate the BFD reloc to be stuck in the object file from the
+   fixup used internally in the assembler.  */
+
+arelent *
+tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED,
+	      fixS *fixp)
+{
+  arelent *reloc;
+
+  reloc = xmalloc (sizeof (* reloc));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
+  /* Make sure none of our internal relocations make it this far.
+     They'd better have been fully resolved by this point.  */
+  assert ((int) fixp->fx_r_type > 0);
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("cannot represent `%s' relocation in object file"),
+		    bfd_get_reloc_code_name (fixp->fx_r_type));
+      return NULL;
+    }
+
+  if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
+    as_fatal (_("internal error? cannot generate `%s' relocation"),
+	      bfd_get_reloc_code_name (fixp->fx_r_type));
+
+  assert (!fixp->fx_pcrel == !reloc->howto->pc_relative);
+
+#ifdef OBJ_ECOFF
+  if (fixp->fx_r_type == BFD_RELOC_ALPHA_LITERAL)
+    /* Fake out bfd_perform_relocation. sigh.  */
+    reloc->addend = -alpha_gp_value;
+  else
+#endif
+    {
+      reloc->addend = fixp->fx_offset;
+#ifdef OBJ_ELF
+      /* Ohhh, this is ugly.  The problem is that if this is a local global
+         symbol, the relocation will entirely be performed at link time, not
+         at assembly time.  bfd_perform_reloc doesn't know about this sort
+         of thing, and as a result we need to fake it out here.  */
+      if ((S_IS_EXTERNAL (fixp->fx_addsy) || S_IS_WEAK (fixp->fx_addsy)
+	   || (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE)
+	   || (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_THREAD_LOCAL))
+	  && !S_IS_COMMON (fixp->fx_addsy))
+	reloc->addend -= symbol_get_bfdsym (fixp->fx_addsy)->value;
+#endif
+    }
+
+  return reloc;
+}
+
+/* Parse a register name off of the input_line and return a register
+   number.  Gets md_undefined_symbol above to do the register name
+   matching for us.
+
+   Only called as a part of processing the ECOFF .frame directive.  */
+
+int
+tc_get_register (int frame ATTRIBUTE_UNUSED)
+{
+  int framereg = AXP_REG_SP;
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer == '$')
+    {
+      char *s = input_line_pointer;
+      char c = get_symbol_end ();
+      symbolS *sym = md_undefined_symbol (s);
+
+      *strchr (s, '\0') = c;
+      if (sym && (framereg = S_GET_VALUE (sym)) <= 31)
+	goto found;
+    }
+  as_warn (_("frame reg expected, using $%d."), framereg);
+
+found:
+  note_gpreg (framereg);
+  return framereg;
+}
+
+/* This is called before the symbol table is processed.  In order to
+   work with gcc when using mips-tfile, we must keep all local labels.
+   However, in other cases, we want to discard them.  If we were
+   called with -g, but we didn't see any debugging information, it may
+   mean that gcc is smuggling debugging information through to
+   mips-tfile, in which case we must generate all local labels.  */
+
+#ifdef OBJ_ECOFF
+
+void
+alpha_frob_file_before_adjust (void)
+{
+  if (alpha_debug != 0
+      && ! ecoff_debugging_seen)
+    flag_keep_locals = 1;
+}
+
+#endif /* OBJ_ECOFF */
 
 /* The Alpha has support for some VAX floating point types, as well as for
    IEEE floating point.  We consider IEEE to be the primary floating point
diff --git a/gas/config/tc-alpha.h b/gas/config/tc-alpha.h
index 939a14f296e6..42e004e41482 100644
--- a/gas/config/tc-alpha.h
+++ b/gas/config/tc-alpha.h
@@ -1,5 +1,6 @@
 /* This file is tc-alpha.h
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   2005
    Free Software Foundation, Inc.
    Written by Ken Raeburn <raeburn@cygnus.com>.
 
@@ -17,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_ALPHA
 
@@ -49,8 +50,8 @@
 struct fix;
 struct alpha_reloc_tag;
 
-extern int alpha_force_relocation PARAMS ((struct fix *));
-extern int alpha_fix_adjustable PARAMS ((struct fix *));
+extern int alpha_force_relocation (struct fix *);
+extern int alpha_fix_adjustable   (struct fix *);
 
 extern unsigned long alpha_gprmask, alpha_fprmask;
 extern valueT alpha_gp_value;
@@ -59,7 +60,7 @@ extern valueT alpha_gp_value;
 #define tc_fix_adjustable(FIX)		alpha_fix_adjustable (FIX)
 #define RELOC_REQUIRES_SYMBOL
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define md_convert_frag(b,s,f)		as_fatal ("alpha convert_frag\n")
@@ -97,32 +98,32 @@ extern valueT alpha_gp_value;
 
 #define md_number_to_chars		number_to_chars_littleendian
 
-extern int tc_get_register PARAMS ((int frame));
-extern void alpha_frob_ecoff_data PARAMS ((void));
+extern int tc_get_register (int);
+extern void alpha_frob_ecoff_data (void);
 
 #define tc_frob_label(sym) alpha_define_label (sym)
-extern void alpha_define_label PARAMS ((symbolS *));
+extern void alpha_define_label (symbolS *);
 
 #define md_cons_align(nbytes) alpha_cons_align (nbytes)
-extern void alpha_cons_align PARAMS ((int));
+extern void alpha_cons_align (int);
 
 #define HANDLE_ALIGN(fragp) alpha_handle_align (fragp)
-extern void alpha_handle_align PARAMS ((struct frag *));
+extern void alpha_handle_align (struct frag *);
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (3 + 4 + 8)
 
 #ifdef OBJ_ECOFF
 #define tc_frob_file_before_adjust() alpha_frob_file_before_adjust ()
-extern void alpha_frob_file_before_adjust PARAMS ((void));
+extern void alpha_frob_file_before_adjust (void);
 #endif
 
-#define DIFF_EXPR_OK   /* foo-. gets turned into PC relative relocs */
+#define DIFF_EXPR_OK   /* foo-. gets turned into PC relative relocs.  */
 
 #ifdef OBJ_ELF
 #define md_elf_section_letter		alpha_elf_section_letter
-extern int alpha_elf_section_letter PARAMS ((int, char **));
+extern int alpha_elf_section_letter (int, char **);
 #define md_elf_section_flags		alpha_elf_section_flags
-extern flagword alpha_elf_section_flags PARAMS ((flagword, int, int));
+extern flagword alpha_elf_section_flags (flagword, int, int);
 #endif
 
 /* Whether to add support for explicit !relocation_op!sequence_number.  At the
@@ -137,11 +138,11 @@ extern flagword alpha_elf_section_flags PARAMS ((flagword, int, int));
    relocations.  Also convert the gas-internal relocations to the
    appropriate linker relocations.  */
 #define tc_frob_file_before_fix() alpha_before_fix ()
-extern void alpha_before_fix PARAMS ((void));
+extern void alpha_before_fix (void);
 
 #ifdef OBJ_ELF
 #define md_end  alpha_elf_md_end
-extern void alpha_elf_md_end PARAMS ((void));
+extern void alpha_elf_md_end (void);
 #endif
 
 /* New fields for supporting explicit relocations (such as !literal to mark
@@ -152,15 +153,15 @@ extern void alpha_elf_md_end PARAMS ((void));
 
 struct alpha_fix_tag
 {
-  struct fix *next_reloc;		/* next !lituse or !gpdisp */
-  struct alpha_reloc_tag *info;		/* other members with same sequence */
+  struct fix *next_reloc;		/* Next !lituse or !gpdisp.  */
+  struct alpha_reloc_tag *info;		/* Other members with same sequence.  */
 };
 
 /* Initialize the TC_FIX_TYPE field.  */
 #define TC_INIT_FIX_DATA(FIX)						\
 do {									\
-  FIX->tc_fix_data.next_reloc = (struct fix *) 0;			\
-  FIX->tc_fix_data.info = (struct alpha_reloc_tag *) 0;			\
+  FIX->tc_fix_data.next_reloc = NULL;					\
+  FIX->tc_fix_data.info = NULL;						\
 } while (0)
 
 /* Work with DEBUG5 to print fields in tc_fix_type.  */
@@ -175,7 +176,7 @@ do {									\
 #define TARGET_USE_CFIPOP 1
 
 #define tc_cfi_frame_initial_instructions alpha_cfi_frame_initial_instructions
-extern void alpha_cfi_frame_initial_instructions(void);
+extern void alpha_cfi_frame_initial_instructions (void);
 
 #define DWARF2_LINE_MIN_INSN_LENGTH	4
 #define DWARF2_DEFAULT_RETURN_COLUMN	26
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 60cfa34652ad..525b54083fb9 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -1,6 +1,6 @@
 /* tc-arc.c -- Assembler for the ARC
-   Copyright 1994, 1995, 1997, 1999, 2000, 2001, 2002
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006  Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "libiberty.h"
@@ -31,31 +31,12 @@
 #include "elf/arc.h"
 #include "dwarf2dbg.h"
 
-extern int arc_get_mach PARAMS ((char *));
-extern int arc_operand_type PARAMS ((int));
-extern int arc_insn_not_jl PARAMS ((arc_insn));
-extern int arc_limm_fixup_adjust PARAMS ((arc_insn));
-extern int arc_get_noshortcut_flag PARAMS ((void));
-extern int arc_set_ext_seg PARAMS ((void));
-extern void arc_code_symbol PARAMS ((expressionS *));
-
-static arc_insn arc_insert_operand PARAMS ((arc_insn,
-					    const struct arc_operand *, int,
-					    const struct arc_operand_value *,
-					    offsetT, char *, unsigned int));
-static void arc_common PARAMS ((int));
-static void arc_extinst PARAMS ((int));
-static void arc_extoper PARAMS ((int));
-static void arc_option PARAMS ((int));
-static int  get_arc_exp_reloc_type PARAMS ((int, int, expressionS *,
-					   expressionS *));
-
-static void init_opcode_tables PARAMS ((int));
-
-const struct suffix_classes {
+const struct suffix_classes
+{
   char *name;
   int  len;
-} suffixclass[] = {
+} suffixclass[] =
+{
   { "SUFFIX_COND|SUFFIX_FLAG",23 },
   { "SUFFIX_FLAG", 11 },
   { "SUFFIX_COND", 11 },
@@ -64,11 +45,13 @@ const struct suffix_classes {
 
 #define MAXSUFFIXCLASS (sizeof (suffixclass) / sizeof (struct suffix_classes))
 
-const struct syntax_classes {
+const struct syntax_classes
+{
   char *name;
   int  len;
   int  class;
-} syntaxclass[] = {
+} syntaxclass[] =
+{
   { "SYNTAX_3OP|OP1_MUST_BE_IMM", 26, SYNTAX_3OP|OP1_MUST_BE_IMM|SYNTAX_VALID },
   { "OP1_MUST_BE_IMM|SYNTAX_3OP", 26, OP1_MUST_BE_IMM|SYNTAX_3OP|SYNTAX_VALID },
   { "SYNTAX_2OP|OP1_IMM_IMPLIED", 26, SYNTAX_2OP|OP1_IMM_IMPLIED|SYNTAX_VALID },
@@ -79,28 +62,6 @@ const struct syntax_classes {
 
 #define MAXSYNTAXCLASS (sizeof (syntaxclass) / sizeof (struct syntax_classes))
 
-const pseudo_typeS md_pseudo_table[] = {
-  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
-  { "comm", arc_common, 0 },
-  { "common", arc_common, 0 },
-  { "lcomm", arc_common, 1 },
-  { "lcommon", arc_common, 1 },
-  { "2byte", cons, 2 },
-  { "half", cons, 2 },
-  { "short", cons, 2 },
-  { "3byte", cons, 3 },
-  { "4byte", cons, 4 },
-  { "word", cons, 4 },
-  { "option", arc_option, 0 },
-  { "cpu", arc_option, 0 },
-  { "block", s_space, 0 },
-  { "extcondcode", arc_extoper, 0 },
-  { "extcoreregister", arc_extoper, 1 },
-  { "extauxregister", arc_extoper, 2 },
-  { "extinstruction", arc_extinst, 0 },
-  { NULL, 0, 0 },
-};
-
 /* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#;";
@@ -144,21 +105,27 @@ static int cpu_tables_init_p = 0;
 static struct hash_control *arc_suffix_hash = NULL;
 
 const char *md_shortopts = "";
-struct option md_longopts[] = {
-#define OPTION_EB (OPTION_MD_BASE + 0)
+
+enum options
+{
+  OPTION_EB = OPTION_MD_BASE,
+  OPTION_EL,
+  OPTION_ARC5,
+  OPTION_ARC6,
+  OPTION_ARC7,
+  OPTION_ARC8,
+  OPTION_ARC
+};
+
+struct option md_longopts[] =
+{
   { "EB", no_argument, NULL, OPTION_EB },
-#define OPTION_EL (OPTION_MD_BASE + 1)
   { "EL", no_argument, NULL, OPTION_EL },
-#define OPTION_ARC5 (OPTION_MD_BASE + 2)
   { "marc5", no_argument, NULL, OPTION_ARC5 },
   { "pre-v6", no_argument, NULL, OPTION_ARC5 },
-#define OPTION_ARC6 (OPTION_MD_BASE + 3)
   { "marc6", no_argument, NULL, OPTION_ARC6 },
-#define OPTION_ARC7 (OPTION_MD_BASE + 4)
   { "marc7", no_argument, NULL, OPTION_ARC7 },
-#define OPTION_ARC8 (OPTION_MD_BASE + 5)
   { "marc8", no_argument, NULL, OPTION_ARC8 },
-#define OPTION_ARC (OPTION_MD_BASE + 6)
   { "marc", no_argument, NULL, OPTION_ARC },
   { NULL, no_argument, NULL, 0 }
 };
@@ -173,9 +140,7 @@ struct arc_operand_value *get_ext_suffix (char *s);
    See if it's a processor-specific option.  */
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -207,8 +172,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, "\
 ARC Options:\n\
@@ -223,7 +187,7 @@ ARC Options:\n\
    command.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   /* The endianness can be chosen "at the factory".  */
   target_big_endian = byte_order == BIG_ENDIAN;
@@ -239,9 +203,9 @@ md_begin ()
 
 /* Initialize the various opcode and operand tables.
    MACH is one of bfd_mach_arc_xxx.  */
+
 static void
-init_opcode_tables (mach)
-     int mach;
+init_opcode_tables (int mach)
 {
   int i;
   char *last;
@@ -262,7 +226,7 @@ init_opcode_tables (mach)
   for (i = 0; i < arc_suffixes_count; i++)
     {
       if (strcmp (arc_suffixes[i].name, last) != 0)
-	hash_insert (arc_suffix_hash, arc_suffixes[i].name, (PTR) (arc_suffixes + i));
+	hash_insert (arc_suffix_hash, arc_suffixes[i].name, (void *) (arc_suffixes + i));
       last = arc_suffixes[i].name;
     }
 
@@ -282,7 +246,7 @@ init_opcode_tables (mach)
 	 output registers into the object file's symbol table.  */
       symbol_table_insert (symbol_create (arc_reg_names[i].name,
 					  reg_section,
-					  (int) &arc_reg_names[i],
+					  (valueT) &arc_reg_names[i],
 					  &zero_address_frag));
     }
 
@@ -294,14 +258,13 @@ init_opcode_tables (mach)
    If REG is non-NULL, it is a register number and ignore VAL.  */
 
 static arc_insn
-arc_insert_operand (insn, operand, mods, reg, val, file, line)
-     arc_insn insn;
-     const struct arc_operand *operand;
-     int mods;
-     const struct arc_operand_value *reg;
-     offsetT val;
-     char *file;
-     unsigned int line;
+arc_insert_operand (arc_insn insn,
+		    const struct arc_operand *operand,
+		    int mods,
+		    const struct arc_operand_value *reg,
+		    offsetT val,
+		    char *file,
+		    unsigned int line)
 {
   if (operand->bits != 32)
     {
@@ -328,17 +291,7 @@ arc_insert_operand (insn, operand, mods, reg, val, file, line)
 	test = val;
 
       if (test < (offsetT) min || test > (offsetT) max)
-	{
-	  const char *err =
-	    "operand out of range (%s not between %ld and %ld)";
-	  char buf[100];
-
-	  sprint_value (buf, test);
-	  if (file == (char *) NULL)
-	    as_warn (err, buf, min, max);
-	  else
-	    as_warn_where (file, line, err, buf, min, max);
-	}
+	as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
     }
 
   if (operand->insert)
@@ -361,7 +314,8 @@ arc_insert_operand (insn, operand, mods, reg, val, file, line)
    we go, because that would require us to first create the frag, and
    that would screw up references to ``.''.  */
 
-struct arc_fixup {
+struct arc_fixup
+{
   /* index into `arc_operands'  */
   int opindex;
   expressionS exp;
@@ -371,524 +325,81 @@ struct arc_fixup {
 
 #define MAX_SUFFIXES 5
 
-/* This routine is called for each instruction to be assembled.  */
+/* Compute the reloc type of an expression.
+   The possibly modified expression is stored in EXPNEW.
 
-void
-md_assemble (str)
-     char *str;
-{
-  const struct arc_opcode *opcode;
-  const struct arc_opcode *std_opcode;
-  struct arc_opcode *ext_opcode;
-  char *start;
-  const char *last_errmsg = 0;
-  arc_insn insn;
-  static int init_tables_p = 0;
+   This is used to convert the expressions generated by the %-op's into
+   the appropriate operand type.  It is called for both data in instructions
+   (operands) and data outside instructions (variables, debugging info, etc.).
 
-  /* Opcode table initialization is deferred until here because we have to
-     wait for a possible .option command.  */
-  if (!init_tables_p)
-    {
-      init_opcode_tables (arc_mach_type);
-      init_tables_p = 1;
-    }
+   Currently supported %-ops:
 
-  /* Skip leading white space.  */
-  while (ISSPACE (*str))
-    str++;
+   %st(symbol): represented as "symbol >> 2"
+                "st" is short for STatus as in the status register (pc)
 
-  /* The instructions are stored in lists hashed by the first letter (though
-     we needn't care how they're hashed).  Get the first in the list.  */
+   DEFAULT_TYPE is the type to use if no special processing is required.
 
-  ext_opcode = arc_ext_opcodes;
-  std_opcode = arc_opcode_lookup_asm (str);
+   DATA_P is non-zero for data or limm values, zero for insn operands.
+   Remember that the opcode "insertion fns" cannot be used on data, they're
+   only for inserting operands into insns.  They also can't be used for limm
+   values as the insertion routines don't handle limm values.  When called for
+   insns we return fudged reloc types (real_value - BFD_RELOC_UNUSED).  When
+   called for data or limm values we use real reloc types.  */
 
-  /* Keep looking until we find a match.  */
+static int
+get_arc_exp_reloc_type (int data_p,
+			int default_type,
+			expressionS *exp,
+			expressionS *expnew)
+{
+  /* If the expression is "symbol >> 2" we must change it to just "symbol",
+     as fix_new_exp can't handle it.  Similarly for (symbol - symbol) >> 2.
+     That's ok though.  What's really going on here is that we're using
+     ">> 2" as a special syntax for specifying BFD_RELOC_ARC_B26.  */
 
-  start = str;
-  for (opcode = (ext_opcode ? ext_opcode : std_opcode);
-       opcode != NULL;
-       opcode = (ARC_OPCODE_NEXT_ASM (opcode)
-		 ? ARC_OPCODE_NEXT_ASM (opcode)
-		 : (ext_opcode ? ext_opcode = NULL, std_opcode : NULL)))
+  if (exp->X_op == O_right_shift
+      && exp->X_op_symbol != NULL
+      && exp->X_op_symbol->sy_value.X_op == O_constant
+      && exp->X_op_symbol->sy_value.X_add_number == 2
+      && exp->X_add_number == 0)
     {
-      int past_opcode_p, fc, num_suffixes;
-      int fix_up_at = 0;
-      char *syn;
-      struct arc_fixup fixups[MAX_FIXUPS];
-      /* Used as a sanity check.  If we need a limm reloc, make sure we ask
-	 for an extra 4 bytes from frag_more.  */
-      int limm_reloc_p;
-      int ext_suffix_p;
-      const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES];
-
-      /* Is this opcode supported by the selected cpu?  */
-      if (! arc_opcode_supported (opcode))
-	continue;
-
-      /* Scan the syntax string.  If it doesn't match, try the next one.  */
-
-      arc_opcode_init_insert ();
-      insn = opcode->value;
-      fc = 0;
-      past_opcode_p = 0;
-      num_suffixes = 0;
-      limm_reloc_p = 0;
-      ext_suffix_p = 0;
-
-      /* We don't check for (*str != '\0') here because we want to parse
-	 any trailing fake arguments in the syntax string.  */
-      for (str = start, syn = opcode->syntax; *syn != '\0';)
+      if (exp->X_add_symbol != NULL
+	  && (exp->X_add_symbol->sy_value.X_op == O_constant
+	      || exp->X_add_symbol->sy_value.X_op == O_symbol))
 	{
-	  int mods;
-	  const struct arc_operand *operand;
-
-	  /* Non operand chars must match exactly.  */
-	  if (*syn != '%' || *++syn == '%')
-	    {
-	      /* Handle '+' specially as we want to allow "ld r0,[sp-4]".  */
-	      /* ??? The syntax has changed to [sp,-4].  */
-	      if (0 && *syn == '+' && *str == '-')
-		{
-		  /* Skip over syn's +, but leave str's - alone.
-		     That makes the case identical to "ld r0,[sp+-4]".  */
-		  ++syn;
-		}
-	      else if (*str == *syn)
-		{
-		  if (*syn == ' ')
-		    past_opcode_p = 1;
-		  ++syn;
-		  ++str;
-		}
-	      else
-		break;
-	      continue;
-	    }
-
-	  /* We have an operand.  Pick out any modifiers.  */
-	  mods = 0;
-	  while (ARC_MOD_P (arc_operands[arc_operand_map[(int) *syn]].flags))
-	    {
-	      mods |= arc_operands[arc_operand_map[(int) *syn]].flags & ARC_MOD_BITS;
-	      ++syn;
-	    }
-	  operand = arc_operands + arc_operand_map[(int) *syn];
-	  if (operand->fmt == 0)
-	    as_fatal ("unknown syntax format character `%c'", *syn);
-
-	  if (operand->flags & ARC_OPERAND_FAKE)
-	    {
-	      const char *errmsg = NULL;
-	      if (operand->insert)
-		{
-		  insn = (*operand->insert) (insn, operand, mods, NULL, 0, &errmsg);
-		  if (errmsg != (const char *) NULL)
-		    {
-		      last_errmsg = errmsg;
-		      if (operand->flags & ARC_OPERAND_ERROR)
-			{
-			  as_bad (errmsg);
-			  return;
-			}
-		      else if (operand->flags & ARC_OPERAND_WARN)
-			as_warn (errmsg);
-		      break;
-		    }
-		  if (limm_reloc_p
-		      && (operand->flags && operand->flags & ARC_OPERAND_LIMM)
-		      && (operand->flags &
-			  (ARC_OPERAND_ABSOLUTE_BRANCH | ARC_OPERAND_ADDRESS)))
-		    {
-		      fixups[fix_up_at].opindex = arc_operand_map[operand->fmt];
-		    }
-		}
-	      ++syn;
-	    }
-	  /* Are we finished with suffixes?  */
-	  else if (!past_opcode_p)
-	    {
-	      int found;
-	      char c;
-	      char *s, *t;
-	      const struct arc_operand_value *suf, *suffix_end;
-	      const struct arc_operand_value *suffix = NULL;
-
-	      if (!(operand->flags & ARC_OPERAND_SUFFIX))
-		abort ();
-
-	      /* If we're at a space in the input string, we want to skip the
-		 remaining suffixes.  There may be some fake ones though, so
-		 just go on to try the next one.  */
-	      if (*str == ' ')
-		{
-		  ++syn;
-		  continue;
-		}
-
-	      s = str;
-	      if (mods & ARC_MOD_DOT)
-		{
-		  if (*s != '.')
-		    break;
-		  ++s;
-		}
-	      else
-		{
-		  /* This can happen in "b.nd foo" and we're currently looking
-		     for "%q" (ie: a condition code suffix).  */
-		  if (*s == '.')
-		    {
-		      ++syn;
-		      continue;
-		    }
-		}
-
-	      /* Pick the suffix out and look it up via the hash table.  */
-	      for (t = s; *t && ISALNUM (*t); ++t)
-		continue;
-	      c = *t;
-	      *t = '\0';
-	      if ((suf = get_ext_suffix (s)))
-		ext_suffix_p = 1;
-	      else
-		suf = hash_find (arc_suffix_hash, s);
-	      if (!suf)
-		{
-		  /* This can happen in "blle foo" and we're currently using
-		     the template "b%q%.n %j".  The "bl" insn occurs later in
-		     the table so "lle" isn't an illegal suffix.  */
-		  *t = c;
-		  break;
-		}
-
-	      /* Is it the right type?  Note that the same character is used
-		 several times, so we have to examine all of them.  This is
-		 relatively efficient as equivalent entries are kept
-		 together.  If it's not the right type, don't increment `str'
-		 so we try the next one in the series.  */
-	      found = 0;
-	      if (ext_suffix_p && arc_operands[suf->type].fmt == *syn)
-		{
-		  /* Insert the suffix's value into the insn.  */
-		  *t = c;
-		  if (operand->insert)
-		    insn = (*operand->insert) (insn, operand,
-					       mods, NULL, suf->value,
-					       NULL);
-		  else
-		    insn |= suf->value << operand->shift;
-
-		  str = t;
-		  found = 1;
-		}
-	      else
-		{
-		  *t = c;
-		  suffix_end = arc_suffixes + arc_suffixes_count;
-		  for (suffix = suf;
-		       suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
-		       ++suffix)
-		    {
-		      if (arc_operands[suffix->type].fmt == *syn)
-			{
-			  /* Insert the suffix's value into the insn.  */
-			  if (operand->insert)
-			    insn = (*operand->insert) (insn, operand,
-						       mods, NULL, suffix->value,
-						       NULL);
-			  else
-			    insn |= suffix->value << operand->shift;
-
-			  str = t;
-			  found = 1;
-			  break;
-			}
-		    }
-		}
-	      ++syn;
-	      if (!found)
-		/* Wrong type.  Just go on to try next insn entry.  */
-		;
-	      else
-		{
-		  if (num_suffixes == MAX_SUFFIXES)
-		    as_bad ("too many suffixes");
-		  else
-		    insn_suffixes[num_suffixes++] = suffix;
-		}
-	    }
-	  else
-	    /* This is either a register or an expression of some kind.  */
-	    {
-	      char *hold;
-	      const struct arc_operand_value *reg = NULL;
-	      long value = 0;
-	      expressionS exp;
-
-	      if (operand->flags & ARC_OPERAND_SUFFIX)
-		abort ();
-
-	      /* Is there anything left to parse?
-		 We don't check for this at the top because we want to parse
-		 any trailing fake arguments in the syntax string.  */
-	      if (is_end_of_line[(unsigned char) *str])
-		break;
-
-	      /* Parse the operand.  */
-	      hold = input_line_pointer;
-	      input_line_pointer = str;
-	      expression (&exp);
-	      str = input_line_pointer;
-	      input_line_pointer = hold;
-
-	      if (exp.X_op == O_illegal)
-		as_bad ("illegal operand");
-	      else if (exp.X_op == O_absent)
-		as_bad ("missing operand");
-	      else if (exp.X_op == O_constant)
-		{
-		  value = exp.X_add_number;
-		}
-	      else if (exp.X_op == O_register)
-		{
-		  reg = (struct arc_operand_value *) exp.X_add_number;
-		}
-#define IS_REG_DEST_OPERAND(o) ((o) == 'a')
-	      else if (IS_REG_DEST_OPERAND (*syn))
-		as_bad ("symbol as destination register");
-	      else
-		{
-		  if (!strncmp (str, "@h30", 4))
-		    {
-		      arc_code_symbol (&exp);
-		      str += 4;
-		    }
-		  /* We need to generate a fixup for this expression.  */
-		  if (fc >= MAX_FIXUPS)
-		    as_fatal ("too many fixups");
-		  fixups[fc].exp = exp;
-		  /* We don't support shimm relocs. break here to force
-		     the assembler to output a limm.  */
-#define IS_REG_SHIMM_OFFSET(o) ((o) == 'd')
-		  if (IS_REG_SHIMM_OFFSET (*syn))
-		    break;
-		  /* If this is a register constant (IE: one whose
-		     register value gets stored as 61-63) then this
-		     must be a limm.  */
-		  /* ??? This bit could use some cleaning up.
-		     Referencing the format chars like this goes
-		     against style.  */
-		  if (IS_SYMBOL_OPERAND (*syn))
-		    {
-		      const char *junk;
-		      limm_reloc_p = 1;
-		      /* Save this, we don't yet know what reloc to use.  */
-		      fix_up_at = fc;
-		      /* Tell insert_reg we need a limm.  This is
-			 needed because the value at this point is
-			 zero, a shimm.  */
-		      /* ??? We need a cleaner interface than this.  */
-		      (*arc_operands[arc_operand_map['Q']].insert)
-			(insn, operand, mods, reg, 0L, &junk);
-		    }
-		  else
-		    fixups[fc].opindex = arc_operand_map[(int) *syn];
-		  ++fc;
-		  value = 0;
-		}
-
-	      /* Insert the register or expression into the instruction.  */
-	      if (operand->insert)
-		{
-		  const char *errmsg = NULL;
-		  insn = (*operand->insert) (insn, operand, mods,
-					     reg, (long) value, &errmsg);
-		  if (errmsg != (const char *) NULL)
-		    {
-		      last_errmsg = errmsg;
-		      if (operand->flags & ARC_OPERAND_ERROR)
-			{
-			  as_bad (errmsg);
-			  return;
-			}
-		      else if (operand->flags & ARC_OPERAND_WARN)
-			as_warn (errmsg);
-		      break;
-		    }
-		}
-	      else
-		insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
-
-	      ++syn;
-	    }
+	  *expnew = *exp;
+	  expnew->X_op = O_symbol;
+	  expnew->X_op_symbol = NULL;
+	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
 	}
-
-      /* If we're at the end of the syntax string, we're done.  */
-      /* FIXME: try to move this to a separate function.  */
-      if (*syn == '\0')
+      else if (exp->X_add_symbol != NULL
+	       && exp->X_add_symbol->sy_value.X_op == O_subtract)
 	{
-	  int i;
-	  char *f;
-	  long limm, limm_p;
-
-	  /* For the moment we assume a valid `str' can only contain blanks
-	     now.  IE: We needn't try again with a longer version of the
-	     insn and it is assumed that longer versions of insns appear
-	     before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
-
-	  while (ISSPACE (*str))
-	    ++str;
-
-	  if (!is_end_of_line[(unsigned char) *str])
-	    as_bad ("junk at end of line: `%s'", str);
-
-	  /* Is there a limm value?  */
-	  limm_p = arc_opcode_limm_p (&limm);
-
-	  /* Perform various error and warning tests.  */
-
-	  {
-	    static int in_delay_slot_p = 0;
-	    static int prev_insn_needs_cc_nop_p = 0;
-	    /* delay slot type seen */
-	    int delay_slot_type = ARC_DELAY_NONE;
-	    /* conditional execution flag seen */
-	    int conditional = 0;
-	    /* 1 if condition codes are being set */
-	    int cc_set_p = 0;
-	    /* 1 if conditional branch, including `b' "branch always" */
-	    int cond_branch_p = opcode->flags & ARC_OPCODE_COND_BRANCH;
-
-	    for (i = 0; i < num_suffixes; ++i)
-	      {
-		switch (arc_operands[insn_suffixes[i]->type].fmt)
-		  {
-		  case 'n':
-		    delay_slot_type = insn_suffixes[i]->value;
-		    break;
-		  case 'q':
-		    conditional = insn_suffixes[i]->value;
-		    break;
-		  case 'f':
-		    cc_set_p = 1;
-		    break;
-		  }
-	      }
-
-	    /* Putting an insn with a limm value in a delay slot is supposed to
-	       be legal, but let's warn the user anyway.  Ditto for 8 byte
-	       jumps with delay slots.  */
-	    if (in_delay_slot_p && limm_p)
-	      as_warn ("8 byte instruction in delay slot");
-	    if (delay_slot_type != ARC_DELAY_NONE
-		&& limm_p && arc_insn_not_jl (insn)) /* except for jl  addr */
-	      as_warn ("8 byte jump instruction with delay slot");
-	    in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p;
-
-	    /* Warn when a conditional branch immediately follows a set of
-	       the condition codes.  Note that this needn't be done if the
-	       insn that sets the condition codes uses a limm.  */
-	    if (cond_branch_p && conditional != 0 /* 0 = "always" */
-		&& prev_insn_needs_cc_nop_p && arc_mach_type == bfd_mach_arc_5)
-	      as_warn ("conditional branch follows set of flags");
-	    prev_insn_needs_cc_nop_p =
-	      /* FIXME: ??? not required:
-		 (delay_slot_type != ARC_DELAY_NONE) &&  */
-	      cc_set_p && !limm_p;
-	  }
-
-	  /* Write out the instruction.
-	     It is important to fetch enough space in one call to `frag_more'.
-	     We use (f - frag_now->fr_literal) to compute where we are and we
-	     don't want frag_now to change between calls.  */
-	  if (limm_p)
-	    {
-	      f = frag_more (8);
-	      md_number_to_chars (f, insn, 4);
-	      md_number_to_chars (f + 4, limm, 4);
-	      dwarf2_emit_insn (8);
-	    }
-	  else if (limm_reloc_p)
-	    {
-	      /* We need a limm reloc, but the tables think we don't.  */
-	      abort ();
-	    }
-	  else
-	    {
-	      f = frag_more (4);
-	      md_number_to_chars (f, insn, 4);
-	      dwarf2_emit_insn (4);
-	    }
-
-	  /* Create any fixups.  */
-	  for (i = 0; i < fc; ++i)
-	    {
-	      int op_type, reloc_type;
-	      expressionS exptmp;
-	      const struct arc_operand *operand;
-
-	      /* Create a fixup for this operand.
-		 At this point we do not use a bfd_reloc_code_real_type for
-		 operands residing in the insn, but instead just use the
-		 operand index.  This lets us easily handle fixups for any
-		 operand type, although that is admittedly not a very exciting
-		 feature.  We pick a BFD reloc type in md_apply_fix3.
-
-		 Limm values (4 byte immediate "constants") must be treated
-		 normally because they're not part of the actual insn word
-		 and thus the insertion routines don't handle them.  */
-
-	      if (arc_operands[fixups[i].opindex].flags & ARC_OPERAND_LIMM)
-		{
-		  /* Modify the fixup addend as required by the cpu.  */
-		  fixups[i].exp.X_add_number += arc_limm_fixup_adjust (insn);
-		  op_type = fixups[i].opindex;
-		  /* FIXME: can we add this data to the operand table?  */
-		  if (op_type == arc_operand_map['L']
-		      || op_type == arc_operand_map['s']
-		      || op_type == arc_operand_map['o']
-		      || op_type == arc_operand_map['O'])
-		    reloc_type = BFD_RELOC_32;
-		  else if (op_type == arc_operand_map['J'])
-		    reloc_type = BFD_RELOC_ARC_B26;
-		  else
-		    abort ();
-		  reloc_type = get_arc_exp_reloc_type (1, reloc_type,
-						       &fixups[i].exp,
-						       &exptmp);
-		}
-	      else
-		{
-		  op_type = get_arc_exp_reloc_type (0, fixups[i].opindex,
-						    &fixups[i].exp, &exptmp);
-		  reloc_type = op_type + (int) BFD_RELOC_UNUSED;
-		}
-	      operand = &arc_operands[op_type];
-	      fix_new_exp (frag_now,
-			   ((f - frag_now->fr_literal)
-			    + (operand->flags & ARC_OPERAND_LIMM ? 4 : 0)), 4,
-			   &exptmp,
-			   (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0,
-			   (bfd_reloc_code_real_type) reloc_type);
-	    }
-
-	  /* All done.  */
-	  return;
+	  *expnew = exp->X_add_symbol->sy_value;
+	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
 	}
-
-      /* Try the next entry.  */
     }
 
-  if (NULL == last_errmsg)
-    as_bad ("bad instruction `%s'", start);
-  else
-    as_bad (last_errmsg);
+  *expnew = *exp;
+  return default_type;
 }
 
+static int
+arc_set_ext_seg (void)
+{
+  if (!arcext_section)
+    {
+      arcext_section = subseg_new (".arcextmap", 0);
+      bfd_set_section_flags (stdoutput, arcext_section,
+			     SEC_READONLY | SEC_HAS_CONTENTS);
+    }
+  else
+    subseg_set (arcext_section, 0);
+  return 1;
+}
+
 static void
-arc_extoper (opertype)
-     int opertype;
+arc_extoper (int opertype)
 {
   char *name;
   char *mode;
@@ -1031,8 +542,7 @@ arc_extoper (opertype)
       return;
     }
 
-  ext_oper = (struct arc_ext_operand_value *) \
-    xmalloc (sizeof (struct arc_ext_operand_value));
+  ext_oper = xmalloc (sizeof (struct arc_ext_operand_value));
 
   if (opertype)
     {
@@ -1040,7 +550,7 @@ arc_extoper (opertype)
       if ((symbolP = symbol_find (name)))
 	{
 	  if (S_GET_SEGMENT (symbolP) == reg_section)
-	    S_SET_VALUE (symbolP, (int) &ext_oper->operand);
+	    S_SET_VALUE (symbolP, (valueT) &ext_oper->operand);
 	  else
 	    {
 	      as_bad ("attempt to override symbol: %s", name);
@@ -1054,7 +564,8 @@ arc_extoper (opertype)
 	{
 	  /* If its not there, add it.  */
 	  symbol_table_insert (symbol_create (name, reg_section,
-					      (int) &ext_oper->operand, &zero_address_frag));
+					      (valueT) &ext_oper->operand,
+					      &zero_address_frag));
 	}
     }
 
@@ -1128,10 +639,9 @@ arc_extoper (opertype)
 }
 
 static void
-arc_extinst (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+arc_extinst (int ignore ATTRIBUTE_UNUSED)
 {
-  unsigned char syntax[129];
+  char syntax[129];
   char *name;
   char *p;
   char c;
@@ -1294,7 +804,7 @@ arc_extinst (ignore)
     strcat (syntax, "%F");
   strcat (syntax, "%S%L");
 
-  ext_op = (struct arc_opcode *) xmalloc (sizeof (struct arc_opcode));
+  ext_op = xmalloc (sizeof (struct arc_opcode));
   ext_op->syntax = xstrdup (syntax);
 
   ext_op->mask  = I (-1) | ((0x3 == opcode) ? C (-1) : 0);
@@ -1332,23 +842,8 @@ arc_extinst (ignore)
   demand_empty_rest_of_line ();
 }
 
-int
-arc_set_ext_seg ()
-{
-  if (!arcext_section)
-    {
-      arcext_section = subseg_new (".arcextmap", 0);
-      bfd_set_section_flags (stdoutput, arcext_section,
-			     SEC_READONLY | SEC_HAS_CONTENTS);
-    }
-  else
-    subseg_set (arcext_section, 0);
-  return 1;
-}
-
 static void
-arc_common (localScope)
-     int localScope;
+arc_common (int localScope)
 {
   char *name;
   char c;
@@ -1459,9 +954,9 @@ arc_common (localScope)
 /* Select the cpu we're assembling for.  */
 
 static void
-arc_option (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+arc_option (int ignore ATTRIBUTE_UNUSED)
 {
+  extern int arc_get_mach (char *);
   int mach;
   char c;
   char *cpu;
@@ -1515,10 +1010,7 @@ arc_option (ignore)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -1559,10 +1051,7 @@ md_atof (type, litP, sizeP)
    endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -1573,9 +1062,7 @@ md_number_to_chars (buf, val, n)
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segment, size)
-     segT segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
 
@@ -1585,9 +1072,8 @@ md_section_align (segment, size)
 /* We don't have any form of relaxing.  */
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   as_fatal (_("md_estimate_size_before_relax\n"));
   return 1;
@@ -1596,21 +1082,20 @@ md_estimate_size_before_relax (fragp, seg)
 /* Convert a machine dependent frag.  We never generate these.  */
 
 void
-md_convert_frag (abfd, sec, fragp)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragp ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragp ATTRIBUTE_UNUSED)
 {
   as_fatal (_("md_convert_frag\n"));
 }
 
-void
-arc_code_symbol (expressionP)
-     expressionS *expressionP;
+static void
+arc_code_symbol (expressionS *expressionP)
 {
   if (expressionP->X_op == O_symbol && expressionP->X_add_number == 0)
     {
       expressionS two;
+
       expressionP->X_op = O_right_shift;
       expressionP->X_add_symbol->sy_value.X_op = O_constant;
       two.X_op = O_constant;
@@ -1625,6 +1110,7 @@ arc_code_symbol (expressionP)
 	   && expressionP->X_add_number == 0)
     {
       expressionS two;
+
       expressionP->X_add_symbol = make_expr_symbol (expressionP);
       expressionP->X_op = O_right_shift;
       two.X_op = O_constant;
@@ -1633,10 +1119,7 @@ arc_code_symbol (expressionP)
       expressionP->X_op_symbol = make_expr_symbol (&two);
     }
   else
-    {
-      as_bad ("expression too complex code symbol");
-      return;
-    }
+    as_bad ("expression too complex code symbol");
 }
 
 /* Parse an operand that is machine-specific.
@@ -1650,55 +1133,56 @@ arc_code_symbol (expressionP)
    to achieve the same effect.  */
 
 void
-md_operand (expressionP)
-     expressionS *expressionP;
+md_operand (expressionS *expressionP)
 {
   char *p = input_line_pointer;
 
-  if (*p == '%')
-    if (strncmp (p, "%st(", 4) == 0)
-      {
-	input_line_pointer += 4;
-	expression (expressionP);
-	if (*input_line_pointer != ')')
-	  {
-	    as_bad ("missing ')' in %%-op");
-	    return;
-	  }
-	++input_line_pointer;
-	arc_code_symbol (expressionP);
-      }
-    else
-      {
-	/* It could be a register.  */
-	int i, l;
-	struct arc_ext_operand_value *ext_oper = arc_ext_operands;
-	p++;
+  if (*p != '%')
+    return;
 
-	while (ext_oper)
-	  {
-	    l = strlen (ext_oper->operand.name);
-	    if (!strncmp (p, ext_oper->operand.name, l) && !ISALNUM (*(p + l)))
-	      {
-		input_line_pointer += l + 1;
-		expressionP->X_op = O_register;
-		expressionP->X_add_number = (int) &ext_oper->operand;
-		return;
-	      }
-	    ext_oper = ext_oper->next;
-	  }
-	for (i = 0; i < arc_reg_names_count; i++)
-	  {
-	    l = strlen (arc_reg_names[i].name);
-	    if (!strncmp (p, arc_reg_names[i].name, l) && !ISALNUM (*(p + l)))
-	      {
-		input_line_pointer += l + 1;
-		expressionP->X_op = O_register;
-		expressionP->X_add_number = (int) &arc_reg_names[i];
-		break;
-	      }
-	  }
-      }
+  if (strncmp (p, "%st(", 4) == 0)
+    {
+      input_line_pointer += 4;
+      expression (expressionP);
+      if (*input_line_pointer != ')')
+	{
+	  as_bad ("missing ')' in %%-op");
+	  return;
+	}
+      ++input_line_pointer;
+      arc_code_symbol (expressionP);
+    }
+  else
+    {
+      /* It could be a register.  */
+      int i, l;
+      struct arc_ext_operand_value *ext_oper = arc_ext_operands;
+      p++;
+
+      while (ext_oper)
+	{
+	  l = strlen (ext_oper->operand.name);
+	  if (!strncmp (p, ext_oper->operand.name, l) && !ISALNUM (*(p + l)))
+	    {
+	      input_line_pointer += l + 1;
+	      expressionP->X_op = O_register;
+	      expressionP->X_add_number = (offsetT) &ext_oper->operand;
+	      return;
+	    }
+	  ext_oper = ext_oper->next;
+	}
+      for (i = 0; i < arc_reg_names_count; i++)
+	{
+	  l = strlen (arc_reg_names[i].name);
+	  if (!strncmp (p, arc_reg_names[i].name, l) && !ISALNUM (*(p + l)))
+	    {
+	      input_line_pointer += l + 1;
+	      expressionP->X_op = O_register;
+	      expressionP->X_add_number = (offsetT) &arc_reg_names[i];
+	      break;
+	    }
+	}
+    }
 }
 
 /* We have no need to default values of symbols.
@@ -1706,8 +1190,7 @@ md_operand (expressionP)
    them all in the symbol table to begin with.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -1720,9 +1203,8 @@ md_undefined_symbol (name)
    `label' will be right shifted by 2.  */
 
 void
-arc_parse_cons_expression (exp, nbytes)
-     expressionS *exp;
-     unsigned int nbytes ATTRIBUTE_UNUSED;
+arc_parse_cons_expression (expressionS *exp,
+			   unsigned int nbytes ATTRIBUTE_UNUSED)
 {
   char *p = input_line_pointer;
   int code_symbol_fix = 0;
@@ -1733,7 +1215,7 @@ arc_parse_cons_expression (exp, nbytes)
 	code_symbol_fix = 1;
 	strcpy (p, ";   ");
       }
-  expr (0, exp);
+  expression_and_evaluate (exp);
   if (code_symbol_fix)
     {
       arc_code_symbol (exp);
@@ -1744,11 +1226,10 @@ arc_parse_cons_expression (exp, nbytes)
 /* Record a fixup for a cons expression.  */
 
 void
-arc_cons_fix_new (frag, where, nbytes, exp)
-     fragS *frag;
-     int where;
-     int nbytes;
-     expressionS *exp;
+arc_cons_fix_new (fragS *frag,
+		  int where,
+		  int nbytes,
+		  expressionS *exp)
 {
   if (nbytes == 4)
     {
@@ -1774,73 +1255,12 @@ arc_cons_fix_new (frag, where, nbytes, exp)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   /* Return the address of the delay slot.  */
   return fixP->fx_frag->fr_address + fixP->fx_where + fixP->fx_size;
 }
 
-/* Compute the reloc type of an expression.
-   The possibly modified expression is stored in EXPNEW.
-
-   This is used to convert the expressions generated by the %-op's into
-   the appropriate operand type.  It is called for both data in instructions
-   (operands) and data outside instructions (variables, debugging info, etc.).
-
-   Currently supported %-ops:
-
-   %st(symbol): represented as "symbol >> 2"
-                "st" is short for STatus as in the status register (pc)
-
-   DEFAULT_TYPE is the type to use if no special processing is required.
-
-   DATA_P is non-zero for data or limm values, zero for insn operands.
-   Remember that the opcode "insertion fns" cannot be used on data, they're
-   only for inserting operands into insns.  They also can't be used for limm
-   values as the insertion routines don't handle limm values.  When called for
-   insns we return fudged reloc types (real_value - BFD_RELOC_UNUSED).  When
-   called for data or limm values we use real reloc types.  */
-
-static int
-get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
-     int data_p;
-     int default_type;
-     expressionS *exp;
-     expressionS *expnew;
-{
-  /* If the expression is "symbol >> 2" we must change it to just "symbol",
-     as fix_new_exp can't handle it.  Similarly for (symbol - symbol) >> 2.
-     That's ok though.  What's really going on here is that we're using
-     ">> 2" as a special syntax for specifying BFD_RELOC_ARC_B26.  */
-
-  if (exp->X_op == O_right_shift
-      && exp->X_op_symbol != NULL
-      && exp->X_op_symbol->sy_value.X_op == O_constant
-      && exp->X_op_symbol->sy_value.X_add_number == 2
-      && exp->X_add_number == 0)
-    {
-      if (exp->X_add_symbol != NULL
-	  && (exp->X_add_symbol->sy_value.X_op == O_constant
-	      || exp->X_add_symbol->sy_value.X_op == O_symbol))
-	{
-	  *expnew = *exp;
-	  expnew->X_op = O_symbol;
-	  expnew->X_op_symbol = NULL;
-	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
-	}
-      else if (exp->X_add_symbol != NULL
-	       && exp->X_add_symbol->sy_value.X_op == O_subtract)
-	{
-	  *expnew = exp->X_add_symbol->sy_value;
-	  return data_p ? BFD_RELOC_ARC_B26 : arc_operand_map['J'];
-	}
-    }
-
-  *expnew = *exp;
-  return default_type;
-}
-
 /* Apply a fixup to the object code.  This is called for all the
    fixups we generated by the call to fix_new_exp, above.  In the call
    above we used a reloc code which was the largest legal reloc code
@@ -1850,14 +1270,8 @@ get_arc_exp_reloc_type (data_p, default_type, exp, expnew)
    that, we determine the correct reloc code and put it back in the fixup.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg;
+md_apply_fix (fixS *fixP, valueT * valP, segT seg)
 {
-#if 0
-  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-#endif
   valueT value = * valP;
 
   if (fixP->fx_addsy == (symbolS *) NULL)
@@ -1900,10 +1314,8 @@ md_apply_fix3 (fixP, valP, seg)
 	bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
 
       if (fixP->fx_done)
-	{
-	  /* Nothing else to do here.  */
-	  return;
-	}
+	/* Nothing else to do here.  */
+	return;
 
       /* Determine a BFD reloc value based on the operand information.
 	 We are only prepared to turn a few of the operands into relocs.
@@ -1956,12 +1368,6 @@ md_apply_fix3 (fixP, valP, seg)
 	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
 			      value, 4);
 	  break;
-#if 0
-	case BFD_RELOC_64:
-	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
-			      value, 8);
-	  break;
-#endif
 	case BFD_RELOC_ARC_B26:
 	  /* If !fixP->fx_done then `value' is an implicit addend.
 	     We must shift it right by 2 in this case as well because the
@@ -1981,15 +1387,15 @@ md_apply_fix3 (fixP, valP, seg)
    format.  */
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
+	      fixS *fixP)
 {
   arelent *reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
 
-  reloc->sym_ptr_ptr = &fixP->fx_addsy->bsym;
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
   if (reloc->howto == (reloc_howto_type *) NULL)
@@ -2010,3 +1416,520 @@ tc_gen_reloc (section, fixP)
 
   return reloc;
 }
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
+  { "comm", arc_common, 0 },
+  { "common", arc_common, 0 },
+  { "lcomm", arc_common, 1 },
+  { "lcommon", arc_common, 1 },
+  { "2byte", cons, 2 },
+  { "half", cons, 2 },
+  { "short", cons, 2 },
+  { "3byte", cons, 3 },
+  { "4byte", cons, 4 },
+  { "word", cons, 4 },
+  { "option", arc_option, 0 },
+  { "cpu", arc_option, 0 },
+  { "block", s_space, 0 },
+  { "extcondcode", arc_extoper, 0 },
+  { "extcoreregister", arc_extoper, 1 },
+  { "extauxregister", arc_extoper, 2 },
+  { "extinstruction", arc_extinst, 0 },
+  { NULL, 0, 0 },
+};
+
+/* This routine is called for each instruction to be assembled.  */
+
+void
+md_assemble (char *str)
+{
+  const struct arc_opcode *opcode;
+  const struct arc_opcode *std_opcode;
+  struct arc_opcode *ext_opcode;
+  char *start;
+  const char *last_errmsg = 0;
+  arc_insn insn;
+  static int init_tables_p = 0;
+
+  /* Opcode table initialization is deferred until here because we have to
+     wait for a possible .option command.  */
+  if (!init_tables_p)
+    {
+      init_opcode_tables (arc_mach_type);
+      init_tables_p = 1;
+    }
+
+  /* Skip leading white space.  */
+  while (ISSPACE (*str))
+    str++;
+
+  /* The instructions are stored in lists hashed by the first letter (though
+     we needn't care how they're hashed).  Get the first in the list.  */
+
+  ext_opcode = arc_ext_opcodes;
+  std_opcode = arc_opcode_lookup_asm (str);
+
+  /* Keep looking until we find a match.  */
+  start = str;
+  for (opcode = (ext_opcode ? ext_opcode : std_opcode);
+       opcode != NULL;
+       opcode = (ARC_OPCODE_NEXT_ASM (opcode)
+		 ? ARC_OPCODE_NEXT_ASM (opcode)
+		 : (ext_opcode ? ext_opcode = NULL, std_opcode : NULL)))
+    {
+      int past_opcode_p, fc, num_suffixes;
+      int fix_up_at = 0;
+      char *syn;
+      struct arc_fixup fixups[MAX_FIXUPS];
+      /* Used as a sanity check.  If we need a limm reloc, make sure we ask
+	 for an extra 4 bytes from frag_more.  */
+      int limm_reloc_p;
+      int ext_suffix_p;
+      const struct arc_operand_value *insn_suffixes[MAX_SUFFIXES];
+
+      /* Is this opcode supported by the selected cpu?  */
+      if (! arc_opcode_supported (opcode))
+	continue;
+
+      /* Scan the syntax string.  If it doesn't match, try the next one.  */
+      arc_opcode_init_insert ();
+      insn = opcode->value;
+      fc = 0;
+      past_opcode_p = 0;
+      num_suffixes = 0;
+      limm_reloc_p = 0;
+      ext_suffix_p = 0;
+
+      /* We don't check for (*str != '\0') here because we want to parse
+	 any trailing fake arguments in the syntax string.  */
+      for (str = start, syn = opcode->syntax; *syn != '\0';)
+	{
+	  int mods;
+	  const struct arc_operand *operand;
+
+	  /* Non operand chars must match exactly.  */
+	  if (*syn != '%' || *++syn == '%')
+	    {
+	     if (*str == *syn)
+		{
+		  if (*syn == ' ')
+		    past_opcode_p = 1;
+		  ++syn;
+		  ++str;
+		}
+	      else
+		break;
+	      continue;
+	    }
+
+	  /* We have an operand.  Pick out any modifiers.  */
+	  mods = 0;
+	  while (ARC_MOD_P (arc_operands[arc_operand_map[(int) *syn]].flags))
+	    {
+	      mods |= arc_operands[arc_operand_map[(int) *syn]].flags & ARC_MOD_BITS;
+	      ++syn;
+	    }
+	  operand = arc_operands + arc_operand_map[(int) *syn];
+	  if (operand->fmt == 0)
+	    as_fatal ("unknown syntax format character `%c'", *syn);
+
+	  if (operand->flags & ARC_OPERAND_FAKE)
+	    {
+	      const char *errmsg = NULL;
+	      if (operand->insert)
+		{
+		  insn = (*operand->insert) (insn, operand, mods, NULL, 0, &errmsg);
+		  if (errmsg != (const char *) NULL)
+		    {
+		      last_errmsg = errmsg;
+		      if (operand->flags & ARC_OPERAND_ERROR)
+			{
+			  as_bad (errmsg);
+			  return;
+			}
+		      else if (operand->flags & ARC_OPERAND_WARN)
+			as_warn (errmsg);
+		      break;
+		    }
+		  if (limm_reloc_p
+		      && (operand->flags && operand->flags & ARC_OPERAND_LIMM)
+		      && (operand->flags &
+			  (ARC_OPERAND_ABSOLUTE_BRANCH | ARC_OPERAND_ADDRESS)))
+		    {
+		      fixups[fix_up_at].opindex = arc_operand_map[operand->fmt];
+		    }
+		}
+	      ++syn;
+	    }
+	  /* Are we finished with suffixes?  */
+	  else if (!past_opcode_p)
+	    {
+	      int found;
+	      char c;
+	      char *s, *t;
+	      const struct arc_operand_value *suf, *suffix_end;
+	      const struct arc_operand_value *suffix = NULL;
+
+	      if (!(operand->flags & ARC_OPERAND_SUFFIX))
+		abort ();
+
+	      /* If we're at a space in the input string, we want to skip the
+		 remaining suffixes.  There may be some fake ones though, so
+		 just go on to try the next one.  */
+	      if (*str == ' ')
+		{
+		  ++syn;
+		  continue;
+		}
+
+	      s = str;
+	      if (mods & ARC_MOD_DOT)
+		{
+		  if (*s != '.')
+		    break;
+		  ++s;
+		}
+	      else
+		{
+		  /* This can happen in "b.nd foo" and we're currently looking
+		     for "%q" (ie: a condition code suffix).  */
+		  if (*s == '.')
+		    {
+		      ++syn;
+		      continue;
+		    }
+		}
+
+	      /* Pick the suffix out and look it up via the hash table.  */
+	      for (t = s; *t && ISALNUM (*t); ++t)
+		continue;
+	      c = *t;
+	      *t = '\0';
+	      if ((suf = get_ext_suffix (s)))
+		ext_suffix_p = 1;
+	      else
+		suf = hash_find (arc_suffix_hash, s);
+	      if (!suf)
+		{
+		  /* This can happen in "blle foo" and we're currently using
+		     the template "b%q%.n %j".  The "bl" insn occurs later in
+		     the table so "lle" isn't an illegal suffix.  */
+		  *t = c;
+		  break;
+		}
+
+	      /* Is it the right type?  Note that the same character is used
+		 several times, so we have to examine all of them.  This is
+		 relatively efficient as equivalent entries are kept
+		 together.  If it's not the right type, don't increment `str'
+		 so we try the next one in the series.  */
+	      found = 0;
+	      if (ext_suffix_p && arc_operands[suf->type].fmt == *syn)
+		{
+		  /* Insert the suffix's value into the insn.  */
+		  *t = c;
+		  if (operand->insert)
+		    insn = (*operand->insert) (insn, operand,
+					       mods, NULL, suf->value,
+					       NULL);
+		  else
+		    insn |= suf->value << operand->shift;
+		  suffix = suf;
+		  str = t;
+		  found = 1;
+		}
+	      else
+		{
+		  *t = c;
+		  suffix_end = arc_suffixes + arc_suffixes_count;
+		  for (suffix = suf;
+		       suffix < suffix_end && strcmp (suffix->name, suf->name) == 0;
+		       ++suffix)
+		    {
+		      if (arc_operands[suffix->type].fmt == *syn)
+			{
+			  /* Insert the suffix's value into the insn.  */
+			  if (operand->insert)
+			    insn = (*operand->insert) (insn, operand,
+						       mods, NULL, suffix->value,
+						       NULL);
+			  else
+			    insn |= suffix->value << operand->shift;
+
+			  str = t;
+			  found = 1;
+			  break;
+			}
+		    }
+		}
+	      ++syn;
+	      if (!found)
+		/* Wrong type.  Just go on to try next insn entry.  */
+		;
+	      else
+		{
+		  if (num_suffixes == MAX_SUFFIXES)
+		    as_bad ("too many suffixes");
+		  else
+		    insn_suffixes[num_suffixes++] = suffix;
+		}
+	    }
+	  else
+	    /* This is either a register or an expression of some kind.  */
+	    {
+	      char *hold;
+	      const struct arc_operand_value *reg = NULL;
+	      long value = 0;
+	      expressionS exp;
+
+	      if (operand->flags & ARC_OPERAND_SUFFIX)
+		abort ();
+
+	      /* Is there anything left to parse?
+		 We don't check for this at the top because we want to parse
+		 any trailing fake arguments in the syntax string.  */
+	      if (is_end_of_line[(unsigned char) *str])
+		break;
+
+	      /* Parse the operand.  */
+	      hold = input_line_pointer;
+	      input_line_pointer = str;
+	      expression (&exp);
+	      str = input_line_pointer;
+	      input_line_pointer = hold;
+
+	      if (exp.X_op == O_illegal)
+		as_bad ("illegal operand");
+	      else if (exp.X_op == O_absent)
+		as_bad ("missing operand");
+	      else if (exp.X_op == O_constant)
+		value = exp.X_add_number;
+	      else if (exp.X_op == O_register)
+		reg = (struct arc_operand_value *) exp.X_add_number;
+#define IS_REG_DEST_OPERAND(o) ((o) == 'a')
+	      else if (IS_REG_DEST_OPERAND (*syn))
+		as_bad ("symbol as destination register");
+	      else
+		{
+		  if (!strncmp (str, "@h30", 4))
+		    {
+		      arc_code_symbol (&exp);
+		      str += 4;
+		    }
+		  /* We need to generate a fixup for this expression.  */
+		  if (fc >= MAX_FIXUPS)
+		    as_fatal ("too many fixups");
+		  fixups[fc].exp = exp;
+		  /* We don't support shimm relocs. break here to force
+		     the assembler to output a limm.  */
+#define IS_REG_SHIMM_OFFSET(o) ((o) == 'd')
+		  if (IS_REG_SHIMM_OFFSET (*syn))
+		    break;
+		  /* If this is a register constant (IE: one whose
+		     register value gets stored as 61-63) then this
+		     must be a limm.  */
+		  /* ??? This bit could use some cleaning up.
+		     Referencing the format chars like this goes
+		     against style.  */
+		  if (IS_SYMBOL_OPERAND (*syn))
+		    {
+		      const char *junk;
+		      limm_reloc_p = 1;
+		      /* Save this, we don't yet know what reloc to use.  */
+		      fix_up_at = fc;
+		      /* Tell insert_reg we need a limm.  This is
+			 needed because the value at this point is
+			 zero, a shimm.  */
+		      /* ??? We need a cleaner interface than this.  */
+		      (*arc_operands[arc_operand_map['Q']].insert)
+			(insn, operand, mods, reg, 0L, &junk);
+		    }
+		  else
+		    fixups[fc].opindex = arc_operand_map[(int) *syn];
+		  ++fc;
+		  value = 0;
+		}
+
+	      /* Insert the register or expression into the instruction.  */
+	      if (operand->insert)
+		{
+		  const char *errmsg = NULL;
+		  insn = (*operand->insert) (insn, operand, mods,
+					     reg, (long) value, &errmsg);
+		  if (errmsg != (const char *) NULL)
+		    {
+		      last_errmsg = errmsg;
+		      if (operand->flags & ARC_OPERAND_ERROR)
+			{
+			  as_bad (errmsg);
+			  return;
+			}
+		      else if (operand->flags & ARC_OPERAND_WARN)
+			as_warn (errmsg);
+		      break;
+		    }
+		}
+	      else
+		insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+
+	      ++syn;
+	    }
+	}
+
+      /* If we're at the end of the syntax string, we're done.  */
+      /* FIXME: try to move this to a separate function.  */
+      if (*syn == '\0')
+	{
+	  int i;
+	  char *f;
+	  long limm, limm_p;
+
+	  /* For the moment we assume a valid `str' can only contain blanks
+	     now.  IE: We needn't try again with a longer version of the
+	     insn and it is assumed that longer versions of insns appear
+	     before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+
+	  while (ISSPACE (*str))
+	    ++str;
+
+	  if (!is_end_of_line[(unsigned char) *str])
+	    as_bad ("junk at end of line: `%s'", str);
+
+	  /* Is there a limm value?  */
+	  limm_p = arc_opcode_limm_p (&limm);
+
+	  /* Perform various error and warning tests.  */
+
+	  {
+	    static int in_delay_slot_p = 0;
+	    static int prev_insn_needs_cc_nop_p = 0;
+	    /* delay slot type seen */
+	    int delay_slot_type = ARC_DELAY_NONE;
+	    /* conditional execution flag seen */
+	    int conditional = 0;
+	    /* 1 if condition codes are being set */
+	    int cc_set_p = 0;
+	    /* 1 if conditional branch, including `b' "branch always" */
+	    int cond_branch_p = opcode->flags & ARC_OPCODE_COND_BRANCH;
+
+	    for (i = 0; i < num_suffixes; ++i)
+	      {
+		switch (arc_operands[insn_suffixes[i]->type].fmt)
+		  {
+		  case 'n':
+		    delay_slot_type = insn_suffixes[i]->value;
+		    break;
+		  case 'q':
+		    conditional = insn_suffixes[i]->value;
+		    break;
+		  case 'f':
+		    cc_set_p = 1;
+		    break;
+		  }
+	      }
+
+	    /* Putting an insn with a limm value in a delay slot is supposed to
+	       be legal, but let's warn the user anyway.  Ditto for 8 byte
+	       jumps with delay slots.  */
+	    if (in_delay_slot_p && limm_p)
+	      as_warn ("8 byte instruction in delay slot");
+	    if (delay_slot_type != ARC_DELAY_NONE
+		&& limm_p && arc_insn_not_jl (insn)) /* except for jl  addr */
+	      as_warn ("8 byte jump instruction with delay slot");
+	    in_delay_slot_p = (delay_slot_type != ARC_DELAY_NONE) && !limm_p;
+
+	    /* Warn when a conditional branch immediately follows a set of
+	       the condition codes.  Note that this needn't be done if the
+	       insn that sets the condition codes uses a limm.  */
+	    if (cond_branch_p && conditional != 0 /* 0 = "always" */
+		&& prev_insn_needs_cc_nop_p && arc_mach_type == bfd_mach_arc_5)
+	      as_warn ("conditional branch follows set of flags");
+	    prev_insn_needs_cc_nop_p =
+	      /* FIXME: ??? not required:
+		 (delay_slot_type != ARC_DELAY_NONE) &&  */
+	      cc_set_p && !limm_p;
+	  }
+
+	  /* Write out the instruction.
+	     It is important to fetch enough space in one call to `frag_more'.
+	     We use (f - frag_now->fr_literal) to compute where we are and we
+	     don't want frag_now to change between calls.  */
+	  if (limm_p)
+	    {
+	      f = frag_more (8);
+	      md_number_to_chars (f, insn, 4);
+	      md_number_to_chars (f + 4, limm, 4);
+	      dwarf2_emit_insn (8);
+	    }
+	  else if (limm_reloc_p)
+	    /* We need a limm reloc, but the tables think we don't.  */
+	    abort ();
+	  else
+	    {
+	      f = frag_more (4);
+	      md_number_to_chars (f, insn, 4);
+	      dwarf2_emit_insn (4);
+	    }
+
+	  /* Create any fixups.  */
+	  for (i = 0; i < fc; ++i)
+	    {
+	      int op_type, reloc_type;
+	      expressionS exptmp;
+	      const struct arc_operand *operand;
+
+	      /* Create a fixup for this operand.
+		 At this point we do not use a bfd_reloc_code_real_type for
+		 operands residing in the insn, but instead just use the
+		 operand index.  This lets us easily handle fixups for any
+		 operand type, although that is admittedly not a very exciting
+		 feature.  We pick a BFD reloc type in md_apply_fix.
+
+		 Limm values (4 byte immediate "constants") must be treated
+		 normally because they're not part of the actual insn word
+		 and thus the insertion routines don't handle them.  */
+
+	      if (arc_operands[fixups[i].opindex].flags & ARC_OPERAND_LIMM)
+		{
+		  /* Modify the fixup addend as required by the cpu.  */
+		  fixups[i].exp.X_add_number += arc_limm_fixup_adjust (insn);
+		  op_type = fixups[i].opindex;
+		  /* FIXME: can we add this data to the operand table?  */
+		  if (op_type == arc_operand_map['L']
+		      || op_type == arc_operand_map['s']
+		      || op_type == arc_operand_map['o']
+		      || op_type == arc_operand_map['O'])
+		    reloc_type = BFD_RELOC_32;
+		  else if (op_type == arc_operand_map['J'])
+		    reloc_type = BFD_RELOC_ARC_B26;
+		  else
+		    abort ();
+		  reloc_type = get_arc_exp_reloc_type (1, reloc_type,
+						       &fixups[i].exp,
+						       &exptmp);
+		}
+	      else
+		{
+		  op_type = get_arc_exp_reloc_type (0, fixups[i].opindex,
+						    &fixups[i].exp, &exptmp);
+		  reloc_type = op_type + (int) BFD_RELOC_UNUSED;
+		}
+	      operand = &arc_operands[op_type];
+	      fix_new_exp (frag_now,
+			   ((f - frag_now->fr_literal)
+			    + (operand->flags & ARC_OPERAND_LIMM ? 4 : 0)), 4,
+			   &exptmp,
+			   (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) != 0,
+			   (bfd_reloc_code_real_type) reloc_type);
+	    }
+	  return;
+	}
+    }
+
+  if (NULL == last_errmsg)
+    as_bad ("bad instruction `%s'", start);
+  else
+    as_bad (last_errmsg);
+}
diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h
index 884d375546ad..4c3d9c2cdd07 100644
--- a/gas/config/tc-arc.h
+++ b/gas/config/tc-arc.h
@@ -1,5 +1,5 @@
 /* tc-arc.h - Macros and type defines for the ARC.
-   Copyright 1994, 1995, 1997, 2000, 2001, 2002
+   Copyright 1994, 1995, 1997, 2000, 2001, 2002, 2005
    Free Software Foundation, Inc.
    Contributed by Doug Evans (dje@cygnus.com).
 
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_ARC 1
 
@@ -45,28 +45,27 @@
 
 /* The endianness of the target format may change based on command
    line arguments.  */
-extern const char *arc_target_format;
-#define DEFAULT_TARGET_FORMAT "elf32-littlearc"
-#define TARGET_FORMAT arc_target_format
-#define DEFAULT_BYTE_ORDER LITTLE_ENDIAN
+extern const char * arc_target_format;
 
+#define DEFAULT_TARGET_FORMAT  "elf32-littlearc"
+#define TARGET_FORMAT          arc_target_format
+#define DEFAULT_BYTE_ORDER     LITTLE_ENDIAN
 #define WORKING_DOT_WORD
-
-#define LISTING_HEADER "ARC GAS "
+#define LISTING_HEADER         "ARC GAS "
 
 /* The ARC needs to parse reloc specifiers in .word.  */
 
-extern void arc_parse_cons_expression PARAMS ((struct expressionS *, unsigned));
+extern void arc_parse_cons_expression (struct expressionS *, unsigned);
 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \
-arc_parse_cons_expression (EXP, NBYTES)
+  arc_parse_cons_expression (EXP, NBYTES)
 
-extern void arc_cons_fix_new PARAMS ((struct frag *, int, int, struct expressionS *));
+extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *);
 #define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
-arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
+  arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
 
 #define DWARF2_LINE_MIN_INSN_LENGTH 4
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 2ed5196f7429..ae420b353471 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -1,5 +1,6 @@
 /* tc-arm.c -- Assemble for the ARM
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005
    Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
@@ -16,16 +17,16 @@
 
    GAS is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <string.h>
-#define  NO_RELOC 0
+#define	 NO_RELOC 0
 #include "as.h"
 #include "safe-ctype.h"
 
@@ -36,86 +37,58 @@
 #include "symbols.h"
 #include "listing.h"
 
+#include "opcode/arm.h"
+
 #ifdef OBJ_ELF
 #include "elf/arm.h"
 #include "dwarf2dbg.h"
+#include "dw2gencfi.h"
 #endif
 
-/* XXX Set this to 1 after the next binutils release */
+/* XXX Set this to 1 after the next binutils release.  */
 #define WARN_DEPRECATED 0
 
-/* The following bitmasks control CPU extensions:  */
-#define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
-#define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
-#define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
-#define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
-#define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
-#define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
-#define ARM_EXT_V4T	 0x00000040	/* Thumb v1.               */
-#define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
-#define ARM_EXT_V5T	 0x00000100	/* Thumb v2.               */
-#define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
-#define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
-#define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
-#define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
-
-/* Co-processor space extensions.  */
-#define ARM_CEXT_XSCALE   0x00800000	/* Allow MIA etc.          */
-#define ARM_CEXT_MAVERICK 0x00400000	/* Use Cirrus/DSP coprocessor.  */
-#define ARM_CEXT_IWMMXT   0x00200000    /* Intel Wireless MMX technology coprocessor.   */
-
-/* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
-   defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
-   ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
-   three more to cover cores prior to ARM6.  Finally, there are cores which
-   implement further extensions in the co-processor space.  */
-#define ARM_ARCH_V1			  ARM_EXT_V1
-#define ARM_ARCH_V2	(ARM_ARCH_V1	| ARM_EXT_V2)
-#define ARM_ARCH_V2S	(ARM_ARCH_V2	| ARM_EXT_V2S)
-#define ARM_ARCH_V3	(ARM_ARCH_V2S	| ARM_EXT_V3)
-#define ARM_ARCH_V3M	(ARM_ARCH_V3	| ARM_EXT_V3M)
-#define ARM_ARCH_V4xM	(ARM_ARCH_V3	| ARM_EXT_V4)
-#define ARM_ARCH_V4	(ARM_ARCH_V3M	| ARM_EXT_V4)
-#define ARM_ARCH_V4TxM	(ARM_ARCH_V4xM	| ARM_EXT_V4T)
-#define ARM_ARCH_V4T	(ARM_ARCH_V4	| ARM_EXT_V4T)
-#define ARM_ARCH_V5xM	(ARM_ARCH_V4xM	| ARM_EXT_V5)
-#define ARM_ARCH_V5	(ARM_ARCH_V4	| ARM_EXT_V5)
-#define ARM_ARCH_V5TxM	(ARM_ARCH_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
-#define ARM_ARCH_V5T	(ARM_ARCH_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
-#define ARM_ARCH_V5TExP	(ARM_ARCH_V5T	| ARM_EXT_V5ExP)
-#define ARM_ARCH_V5TE	(ARM_ARCH_V5TExP | ARM_EXT_V5E)
-#define ARM_ARCH_V5TEJ	(ARM_ARCH_V5TE	| ARM_EXT_V5J)
-#define ARM_ARCH_V6     (ARM_ARCH_V5TEJ | ARM_EXT_V6)
-
-/* Processors with specific extensions in the co-processor space.  */
-#define ARM_ARCH_XSCALE	(ARM_ARCH_V5TE	| ARM_CEXT_XSCALE)
-#define ARM_ARCH_IWMMXT	(ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT)
-
-/* Some useful combinations:  */
-#define ARM_ANY		0x0000ffff	/* Any basic core.  */
-#define ARM_ALL		0x00ffffff	/* Any core + co-processor */
-#define CPROC_ANY	0x00ff0000	/* Any co-processor */
-#define FPU_ANY		0xff000000	/* Note this is ~ARM_ALL.  */
-
-
-#define FPU_FPA_EXT_V1	 0x80000000	/* Base FPA instruction set.  */
-#define FPU_FPA_EXT_V2	 0x40000000	/* LFM/SFM.		      */
-#define FPU_VFP_EXT_NONE 0x20000000	/* Use VFP word-ordering.     */
-#define FPU_VFP_EXT_V1xD 0x10000000	/* Base VFP instruction set.  */
-#define FPU_VFP_EXT_V1	 0x08000000	/* Double-precision insns.    */
-#define FPU_VFP_EXT_V2	 0x04000000	/* ARM10E VFPr1.	      */
-#define FPU_MAVERICK	 0x02000000	/* Cirrus Maverick.	      */
-#define FPU_NONE	 0
-
-#define FPU_ARCH_FPE	 FPU_FPA_EXT_V1
-#define FPU_ARCH_FPA	(FPU_ARCH_FPE | FPU_FPA_EXT_V2)
-
-#define FPU_ARCH_VFP       FPU_VFP_EXT_NONE
-#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE)
-#define FPU_ARCH_VFP_V1   (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1)
-#define FPU_ARCH_VFP_V2	  (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2)
-
-#define FPU_ARCH_MAVERICK  FPU_MAVERICK
+#ifdef OBJ_ELF
+/* Must be at least the size of the largest unwind opcode (currently two).  */
+#define ARM_OPCODE_CHUNK_SIZE 8
+
+/* This structure holds the unwinding state.  */
+
+static struct
+{
+  symbolS *	  proc_start;
+  symbolS *	  table_entry;
+  symbolS *	  personality_routine;
+  int		  personality_index;
+  /* The segment containing the function.  */
+  segT		  saved_seg;
+  subsegT	  saved_subseg;
+  /* Opcodes generated from this function.  */
+  unsigned char * opcodes;
+  int		  opcode_count;
+  int		  opcode_alloc;
+  /* The number of bytes pushed to the stack.  */
+  offsetT	  frame_size;
+  /* We don't add stack adjustment opcodes immediately so that we can merge
+     multiple adjustments.  We can also omit the final adjustment
+     when using a frame pointer.  */
+  offsetT	  pending_offset;
+  /* These two fields are set by both unwind_movsp and unwind_setfp.  They
+     hold the reg+offset to use when restoring sp from a frame pointer.	 */
+  offsetT	  fp_offset;
+  int		  fp_reg;
+  /* Nonzero if an unwind_setfp directive has been seen.  */
+  unsigned	  fp_used:1;
+  /* Nonzero if the last opcode restores sp from fp_reg.  */
+  unsigned	  sp_restored:1;
+} unwind;
+
+/* Bit N indicates that an R_ARM_NONE relocation has been output for
+   __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
+   emitted only once per section, to save unnecessary bloat.  */
+static unsigned int marked_pr_dependency = 0;
+
+#endif /* OBJ_ELF */
 
 enum arm_float_abi
 {
@@ -124,195 +97,200 @@ enum arm_float_abi
   ARM_FLOAT_ABI_SOFT
 };
 
-/* Types of processor to assemble for.  */
-#define ARM_1		ARM_ARCH_V1
-#define ARM_2		ARM_ARCH_V2
-#define ARM_3		ARM_ARCH_V2S
-#define ARM_250		ARM_ARCH_V2S
-#define ARM_6		ARM_ARCH_V3
-#define ARM_7		ARM_ARCH_V3
-#define ARM_8		ARM_ARCH_V4
-#define ARM_9		ARM_ARCH_V4T
-#define ARM_STRONG	ARM_ARCH_V4
-#define ARM_CPU_MASK	0x0000000f              /* XXX? */
-
+/* Types of processor to assemble for.	*/
 #ifndef CPU_DEFAULT
 #if defined __XSCALE__
-#define CPU_DEFAULT	(ARM_ARCH_XSCALE)
+#define CPU_DEFAULT	ARM_ARCH_XSCALE
 #else
 #if defined __thumb__
-#define CPU_DEFAULT 	(ARM_ARCH_V5T)
-#else
-#define CPU_DEFAULT 	ARM_ANY
+#define CPU_DEFAULT	ARM_ARCH_V5T
 #endif
 #endif
 #endif
 
-#ifdef TE_LINUX
-#define FPU_DEFAULT FPU_ARCH_FPA
-#endif
-
-#ifdef TE_NetBSD
-#ifdef OBJ_ELF
-#define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, but VFP order.  */
-#else
-/* Legacy a.out format.  */
-#define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
-#endif
-#endif
-
-/* For backwards compatibility we default to the FPA.  */
 #ifndef FPU_DEFAULT
-#define FPU_DEFAULT FPU_ARCH_FPA
-#endif
-
-#define streq(a, b)           (strcmp (a, b) == 0)
-#define skip_whitespace(str)  while (*(str) == ' ') ++(str)
-
-static unsigned long cpu_variant;
-static int target_oabi = 0;
+# ifdef TE_LINUX
+#  define FPU_DEFAULT FPU_ARCH_FPA
+# elif defined (TE_NetBSD)
+#  ifdef OBJ_ELF
+#   define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, but VFP order.  */
+#  else
+    /* Legacy a.out format.  */
+#   define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
+#  endif
+# elif defined (TE_VXWORKS)
+#  define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, VFP order.  */
+# else
+   /* For backwards compatibility, default to FPA.  */
+#  define FPU_DEFAULT FPU_ARCH_FPA
+# endif
+#endif /* ifndef FPU_DEFAULT */
+
+#define streq(a, b)	      (strcmp (a, b) == 0)
+
+static arm_feature_set cpu_variant;
+static arm_feature_set arm_arch_used;
+static arm_feature_set thumb_arch_used;
 
 /* Flags stored in private area of BFD structure.  */
-static int uses_apcs_26      = FALSE;
-static int atpcs             = FALSE;
+static int uses_apcs_26	     = FALSE;
+static int atpcs	     = FALSE;
 static int support_interwork = FALSE;
 static int uses_apcs_float   = FALSE;
-static int pic_code          = FALSE;
+static int pic_code	     = FALSE;
 
 /* Variables that we set while parsing command-line options.  Once all
    options have been read we re-process these values to set the real
    assembly flags.  */
-static int legacy_cpu = -1;
-static int legacy_fpu = -1;
-
-static int mcpu_cpu_opt = -1;
-static int mcpu_fpu_opt = -1;
-static int march_cpu_opt = -1;
-static int march_fpu_opt = -1;
-static int mfpu_opt = -1;
-static int mfloat_abi_opt = -1;
-
-/* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful.  */
-const char comment_chars[] = "@";
-
-/* This array holds the chars that only start a comment at the beginning of
-   a line.  If the line seems to have the form '# 123 filename'
-   .line and .file directives will appear in the pre-processed output.  */
-/* Note that input_file.c hand checks for '#' at the beginning of the
-   first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.  */
-/* Also note that comments like this one will always work.  */
-const char line_comment_chars[] = "#";
-
-const char line_separator_chars[] = ";";
-
-/* Chars that can be used to separate mant
-   from exp in floating point numbers.  */
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant.  */
-/* As in 0f12.456  */
-/* or    0d1.2345e12  */
+static const arm_feature_set *legacy_cpu = NULL;
+static const arm_feature_set *legacy_fpu = NULL;
+
+static const arm_feature_set *mcpu_cpu_opt = NULL;
+static const arm_feature_set *mcpu_fpu_opt = NULL;
+static const arm_feature_set *march_cpu_opt = NULL;
+static const arm_feature_set *march_fpu_opt = NULL;
+static const arm_feature_set *mfpu_opt = NULL;
+
+/* Constants for known architecture features.  */
+static const arm_feature_set fpu_default = FPU_DEFAULT;
+static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
+static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
+static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
+static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
+static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
+static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
+
+#ifdef CPU_DEFAULT
+static const arm_feature_set cpu_default = CPU_DEFAULT;
+#endif
 
-const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
+static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
+static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
+static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
+static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
+static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
+static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
+static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
+static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
+static const arm_feature_set arm_ext_v4t_5 =
+  ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
+static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
+static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
+static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
+static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
+static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
+static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
+static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
+static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
+static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
+static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
+static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
+static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
+static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
+static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
+
+static const arm_feature_set arm_arch_any = ARM_ANY;
+static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
+static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
+static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
+
+static const arm_feature_set arm_cext_iwmmxt =
+  ARM_FEATURE (0, ARM_CEXT_IWMMXT);
+static const arm_feature_set arm_cext_xscale =
+  ARM_FEATURE (0, ARM_CEXT_XSCALE);
+static const arm_feature_set arm_cext_maverick =
+  ARM_FEATURE (0, ARM_CEXT_MAVERICK);
+static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
+static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
+static const arm_feature_set fpu_vfp_ext_v1xd =
+  ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
+static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
+static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
 
-/* Prefix characters that indicate the start of an immediate
-   value.  */
-#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
+static int mfloat_abi_opt = -1;
+/* Record user cpu selection for object attributes.  */
+static arm_feature_set selected_cpu = ARM_ARCH_NONE;
+/* Must be long enough to hold any of the names in arm_cpus.  */
+static char selected_cpu_name[16];
+#ifdef OBJ_ELF
+# ifdef EABI_DEFAULT
+static int meabi_flags = EABI_DEFAULT;
+# else
+static int meabi_flags = EF_ARM_EABI_UNKNOWN;
+# endif
+#endif
 
 #ifdef OBJ_ELF
-/* Pre-defined "_GLOBAL_OFFSET_TABLE_"  */
+/* Pre-defined "_GLOBAL_OFFSET_TABLE_"	*/
 symbolS * GOT_symbol;
 #endif
 
-/* Size of relocation record.  */
-const int md_reloc_size = 8;
-
 /* 0: assemble for ARM,
    1: assemble for Thumb,
    2: assemble for Thumb even though target CPU does not support thumb
       instructions.  */
 static int thumb_mode = 0;
 
-typedef struct arm_fix
-{
-  int thumb_mode;
-} arm_fix_data;
+/* If unified_syntax is true, we are processing the new unified
+   ARM/Thumb syntax.  Important differences from the old ARM mode:
+
+     - Immediate operands do not require a # prefix.
+     - Conditional affixes always appear at the end of the
+       instruction.  (For backward compatibility, those instructions
+       that formerly had them in the middle, continue to accept them
+       there.)
+     - The IT instruction may appear, and if it does is validated
+       against subsequent conditional affixes.  It does not generate
+       machine code.
+
+   Important differences from the old Thumb mode:
+
+     - Immediate operands do not require a # prefix.
+     - Most of the V6T2 instructions are only available in unified mode.
+     - The .N and .W suffixes are recognized and honored (it is an error
+       if they cannot be honored).
+     - All instructions set the flags if and only if they have an 's' affix.
+     - Conditional affixes may be used.  They are validated against
+       preceding IT instructions.  Unlike ARM mode, you cannot use a
+       conditional affix except in the scope of an IT instruction.  */
+
+static bfd_boolean unified_syntax = FALSE;
 
 struct arm_it
 {
-  const char *  error;
+  const char *	error;
   unsigned long instruction;
-  int           size;
+  int		size;
+  int		size_req;
+  int		cond;
+  /* Set to the opcode if the instruction needs relaxation.
+     Zero if the instruction is not relaxed.  */
+  unsigned long	relax;
   struct
   {
     bfd_reloc_code_real_type type;
-    expressionS              exp;
-    int                      pc_rel;
+    expressionS		     exp;
+    int			     pc_rel;
   } reloc;
-};
-
-struct arm_it inst;
 
-enum asm_shift_index
-{
-  SHIFT_LSL = 0,
-  SHIFT_LSR,
-  SHIFT_ASR,
-  SHIFT_ROR,
-  SHIFT_RRX
-};
-
-struct asm_shift_properties
-{
-  enum asm_shift_index index;
-  unsigned long        bit_field;
-  unsigned int         allows_0  : 1;
-  unsigned int         allows_32 : 1;
-};
-
-static const struct asm_shift_properties shift_properties [] =
-{
-  { SHIFT_LSL, 0,    1, 0},
-  { SHIFT_LSR, 0x20, 0, 1},
-  { SHIFT_ASR, 0x40, 0, 1},
-  { SHIFT_ROR, 0x60, 0, 0},
-  { SHIFT_RRX, 0x60, 0, 0}
-};
-
-struct asm_shift_name
-{
-  const char *                        name;
-  const struct asm_shift_properties * properties;
-};
-
-static const struct asm_shift_name shift_names [] =
-{
-  { "asl", shift_properties + SHIFT_LSL },
-  { "lsl", shift_properties + SHIFT_LSL },
-  { "lsr", shift_properties + SHIFT_LSR },
-  { "asr", shift_properties + SHIFT_ASR },
-  { "ror", shift_properties + SHIFT_ROR },
-  { "rrx", shift_properties + SHIFT_RRX },
-  { "ASL", shift_properties + SHIFT_LSL },
-  { "LSL", shift_properties + SHIFT_LSL },
-  { "LSR", shift_properties + SHIFT_LSR },
-  { "ASR", shift_properties + SHIFT_ASR },
-  { "ROR", shift_properties + SHIFT_ROR },
-  { "RRX", shift_properties + SHIFT_RRX }
+  struct
+  {
+    unsigned reg;
+    signed int imm;
+    unsigned present	: 1;  /* Operand present.  */
+    unsigned isreg	: 1;  /* Operand was a register.  */
+    unsigned immisreg	: 1;  /* .imm field is a second register.  */
+    unsigned hasreloc	: 1;  /* Operand has relocation suffix.  */
+    unsigned writeback	: 1;  /* Operand has trailing !  */
+    unsigned preind	: 1;  /* Preindexed address.  */
+    unsigned postind	: 1;  /* Postindexed address.  */
+    unsigned negative	: 1;  /* Index register was negated.  */
+    unsigned shifted	: 1;  /* Shift applied to operation.  */
+    unsigned shift_kind : 3;  /* Shift operation (enum shift_kind).  */
+  } operands[6];
 };
 
-/* Any kind of shift is accepted.  */
-#define NO_SHIFT_RESTRICT 1
-/* The shift operand must be an immediate value, not a register.  */
-#define SHIFT_IMMEDIATE	  0
-/* The shift must be LSL or ASR and the operand must be an immediate.  */
-#define SHIFT_LSL_OR_ASR_IMMEDIATE 2
-/* The shift must be ASR and the operand must be an immediate.  */
-#define SHIFT_ASR_IMMEDIATE 3
-/* The shift must be LSL and the operand must be an immediate.  */
-#define SHIFT_LSL_IMMEDIATE 4
+static struct arm_it inst;
 
 #define NUM_FLOAT_VALS 8
 
@@ -321,7 +299,7 @@ const char * fp_const[] =
   "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
 };
 
-/* Number of littlenums required to hold an extended precision number.  */
+/* Number of littlenums required to hold an extended precision number.	*/
 #define MAX_LITTLENUMS 6
 
 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
@@ -329,246 +307,52 @@ LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
 #define FAIL	(-1)
 #define SUCCESS (0)
 
-/* Whether a Co-processor load/store operation accepts write-back forms.  */
-#define CP_WB_OK 1
-#define CP_NO_WB 0
-
 #define SUFF_S 1
 #define SUFF_D 2
 #define SUFF_E 3
 #define SUFF_P 4
 
-#define CP_T_X   0x00008000
-#define CP_T_Y   0x00400000
-#define CP_T_Pre 0x01000000
-#define CP_T_UD  0x00800000
-#define CP_T_WB  0x00200000
+#define CP_T_X	 0x00008000
+#define CP_T_Y	 0x00400000
 
-#define CONDS_BIT        0x00100000
-#define LOAD_BIT         0x00100000
+#define CONDS_BIT	 0x00100000
+#define LOAD_BIT	 0x00100000
 
 #define DOUBLE_LOAD_FLAG 0x00000001
 
 struct asm_cond
 {
-  const char *  template;
+  const char *	template;
   unsigned long value;
 };
 
-#define COND_ALWAYS 0xe0000000
-#define COND_MASK   0xf0000000
+#define COND_ALWAYS 0xE
 
-static const struct asm_cond conds[] =
+struct asm_psr
 {
-  {"eq", 0x00000000},
-  {"ne", 0x10000000},
-  {"cs", 0x20000000}, {"hs", 0x20000000},
-  {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
-  {"mi", 0x40000000},
-  {"pl", 0x50000000},
-  {"vs", 0x60000000},
-  {"vc", 0x70000000},
-  {"hi", 0x80000000},
-  {"ls", 0x90000000},
-  {"ge", 0xa0000000},
-  {"lt", 0xb0000000},
-  {"gt", 0xc0000000},
-  {"le", 0xd0000000},
-  {"al", 0xe0000000},
-  {"nv", 0xf0000000}
+  const char *template;
+  unsigned long field;
 };
 
-struct asm_psr
+struct asm_barrier_opt
 {
   const char *template;
-  bfd_boolean cpsr;
-  unsigned long field;
+  unsigned long value;
 };
 
 /* The bit that distinguishes CPSR and SPSR.  */
 #define SPSR_BIT   (1 << 22)
 
-/* How many bits to shift the PSR_xxx bits up by.  */
-#define PSR_SHIFT  16
-
-#define PSR_c   (1 << 0)
-#define PSR_x   (1 << 1)
-#define PSR_s   (1 << 2)
-#define PSR_f   (1 << 3)
-
-static const struct asm_psr psrs[] =
-{
-  {"CPSR",	TRUE,  PSR_c | PSR_f},
-  {"CPSR_all",	TRUE,  PSR_c | PSR_f},
-  {"SPSR",	FALSE, PSR_c | PSR_f},
-  {"SPSR_all",	FALSE, PSR_c | PSR_f},
-  {"CPSR_flg",	TRUE,  PSR_f},
-  {"CPSR_f",    TRUE,  PSR_f},
-  {"SPSR_flg",	FALSE, PSR_f},
-  {"SPSR_f",    FALSE, PSR_f},
-  {"CPSR_c",	TRUE,  PSR_c},
-  {"CPSR_ctl",	TRUE,  PSR_c},
-  {"SPSR_c",	FALSE, PSR_c},
-  {"SPSR_ctl",	FALSE, PSR_c},
-  {"CPSR_x",    TRUE,  PSR_x},
-  {"CPSR_s",    TRUE,  PSR_s},
-  {"SPSR_x",    FALSE, PSR_x},
-  {"SPSR_s",    FALSE, PSR_s},
-  /* Combinations of flags.  */
-  {"CPSR_fs",	TRUE, PSR_f | PSR_s},
-  {"CPSR_fx",	TRUE, PSR_f | PSR_x},
-  {"CPSR_fc",	TRUE, PSR_f | PSR_c},
-  {"CPSR_sf",	TRUE, PSR_s | PSR_f},
-  {"CPSR_sx",	TRUE, PSR_s | PSR_x},
-  {"CPSR_sc",	TRUE, PSR_s | PSR_c},
-  {"CPSR_xf",	TRUE, PSR_x | PSR_f},
-  {"CPSR_xs",	TRUE, PSR_x | PSR_s},
-  {"CPSR_xc",	TRUE, PSR_x | PSR_c},
-  {"CPSR_cf",	TRUE, PSR_c | PSR_f},
-  {"CPSR_cs",	TRUE, PSR_c | PSR_s},
-  {"CPSR_cx",	TRUE, PSR_c | PSR_x},
-  {"CPSR_fsx",	TRUE, PSR_f | PSR_s | PSR_x},
-  {"CPSR_fsc",	TRUE, PSR_f | PSR_s | PSR_c},
-  {"CPSR_fxs",	TRUE, PSR_f | PSR_x | PSR_s},
-  {"CPSR_fxc",	TRUE, PSR_f | PSR_x | PSR_c},
-  {"CPSR_fcs",	TRUE, PSR_f | PSR_c | PSR_s},
-  {"CPSR_fcx",	TRUE, PSR_f | PSR_c | PSR_x},
-  {"CPSR_sfx",	TRUE, PSR_s | PSR_f | PSR_x},
-  {"CPSR_sfc",	TRUE, PSR_s | PSR_f | PSR_c},
-  {"CPSR_sxf",	TRUE, PSR_s | PSR_x | PSR_f},
-  {"CPSR_sxc",	TRUE, PSR_s | PSR_x | PSR_c},
-  {"CPSR_scf",	TRUE, PSR_s | PSR_c | PSR_f},
-  {"CPSR_scx",	TRUE, PSR_s | PSR_c | PSR_x},
-  {"CPSR_xfs",	TRUE, PSR_x | PSR_f | PSR_s},
-  {"CPSR_xfc",	TRUE, PSR_x | PSR_f | PSR_c},
-  {"CPSR_xsf",	TRUE, PSR_x | PSR_s | PSR_f},
-  {"CPSR_xsc",	TRUE, PSR_x | PSR_s | PSR_c},
-  {"CPSR_xcf",	TRUE, PSR_x | PSR_c | PSR_f},
-  {"CPSR_xcs",	TRUE, PSR_x | PSR_c | PSR_s},
-  {"CPSR_cfs",	TRUE, PSR_c | PSR_f | PSR_s},
-  {"CPSR_cfx",	TRUE, PSR_c | PSR_f | PSR_x},
-  {"CPSR_csf",	TRUE, PSR_c | PSR_s | PSR_f},
-  {"CPSR_csx",	TRUE, PSR_c | PSR_s | PSR_x},
-  {"CPSR_cxf",	TRUE, PSR_c | PSR_x | PSR_f},
-  {"CPSR_cxs",	TRUE, PSR_c | PSR_x | PSR_s},
-  {"CPSR_fsxc",	TRUE, PSR_f | PSR_s | PSR_x | PSR_c},
-  {"CPSR_fscx",	TRUE, PSR_f | PSR_s | PSR_c | PSR_x},
-  {"CPSR_fxsc",	TRUE, PSR_f | PSR_x | PSR_s | PSR_c},
-  {"CPSR_fxcs",	TRUE, PSR_f | PSR_x | PSR_c | PSR_s},
-  {"CPSR_fcsx",	TRUE, PSR_f | PSR_c | PSR_s | PSR_x},
-  {"CPSR_fcxs",	TRUE, PSR_f | PSR_c | PSR_x | PSR_s},
-  {"CPSR_sfxc",	TRUE, PSR_s | PSR_f | PSR_x | PSR_c},
-  {"CPSR_sfcx",	TRUE, PSR_s | PSR_f | PSR_c | PSR_x},
-  {"CPSR_sxfc",	TRUE, PSR_s | PSR_x | PSR_f | PSR_c},
-  {"CPSR_sxcf",	TRUE, PSR_s | PSR_x | PSR_c | PSR_f},
-  {"CPSR_scfx",	TRUE, PSR_s | PSR_c | PSR_f | PSR_x},
-  {"CPSR_scxf",	TRUE, PSR_s | PSR_c | PSR_x | PSR_f},
-  {"CPSR_xfsc",	TRUE, PSR_x | PSR_f | PSR_s | PSR_c},
-  {"CPSR_xfcs",	TRUE, PSR_x | PSR_f | PSR_c | PSR_s},
-  {"CPSR_xsfc",	TRUE, PSR_x | PSR_s | PSR_f | PSR_c},
-  {"CPSR_xscf",	TRUE, PSR_x | PSR_s | PSR_c | PSR_f},
-  {"CPSR_xcfs",	TRUE, PSR_x | PSR_c | PSR_f | PSR_s},
-  {"CPSR_xcsf",	TRUE, PSR_x | PSR_c | PSR_s | PSR_f},
-  {"CPSR_cfsx",	TRUE, PSR_c | PSR_f | PSR_s | PSR_x},
-  {"CPSR_cfxs",	TRUE, PSR_c | PSR_f | PSR_x | PSR_s},
-  {"CPSR_csfx",	TRUE, PSR_c | PSR_s | PSR_f | PSR_x},
-  {"CPSR_csxf",	TRUE, PSR_c | PSR_s | PSR_x | PSR_f},
-  {"CPSR_cxfs",	TRUE, PSR_c | PSR_x | PSR_f | PSR_s},
-  {"CPSR_cxsf",	TRUE, PSR_c | PSR_x | PSR_s | PSR_f},
-  {"SPSR_fs",	FALSE, PSR_f | PSR_s},
-  {"SPSR_fx",	FALSE, PSR_f | PSR_x},
-  {"SPSR_fc",	FALSE, PSR_f | PSR_c},
-  {"SPSR_sf",	FALSE, PSR_s | PSR_f},
-  {"SPSR_sx",	FALSE, PSR_s | PSR_x},
-  {"SPSR_sc",	FALSE, PSR_s | PSR_c},
-  {"SPSR_xf",	FALSE, PSR_x | PSR_f},
-  {"SPSR_xs",	FALSE, PSR_x | PSR_s},
-  {"SPSR_xc",	FALSE, PSR_x | PSR_c},
-  {"SPSR_cf",	FALSE, PSR_c | PSR_f},
-  {"SPSR_cs",	FALSE, PSR_c | PSR_s},
-  {"SPSR_cx",	FALSE, PSR_c | PSR_x},
-  {"SPSR_fsx",	FALSE, PSR_f | PSR_s | PSR_x},
-  {"SPSR_fsc",	FALSE, PSR_f | PSR_s | PSR_c},
-  {"SPSR_fxs",	FALSE, PSR_f | PSR_x | PSR_s},
-  {"SPSR_fxc",	FALSE, PSR_f | PSR_x | PSR_c},
-  {"SPSR_fcs",	FALSE, PSR_f | PSR_c | PSR_s},
-  {"SPSR_fcx",	FALSE, PSR_f | PSR_c | PSR_x},
-  {"SPSR_sfx",	FALSE, PSR_s | PSR_f | PSR_x},
-  {"SPSR_sfc",	FALSE, PSR_s | PSR_f | PSR_c},
-  {"SPSR_sxf",	FALSE, PSR_s | PSR_x | PSR_f},
-  {"SPSR_sxc",	FALSE, PSR_s | PSR_x | PSR_c},
-  {"SPSR_scf",	FALSE, PSR_s | PSR_c | PSR_f},
-  {"SPSR_scx",	FALSE, PSR_s | PSR_c | PSR_x},
-  {"SPSR_xfs",	FALSE, PSR_x | PSR_f | PSR_s},
-  {"SPSR_xfc",	FALSE, PSR_x | PSR_f | PSR_c},
-  {"SPSR_xsf",	FALSE, PSR_x | PSR_s | PSR_f},
-  {"SPSR_xsc",	FALSE, PSR_x | PSR_s | PSR_c},
-  {"SPSR_xcf",	FALSE, PSR_x | PSR_c | PSR_f},
-  {"SPSR_xcs",	FALSE, PSR_x | PSR_c | PSR_s},
-  {"SPSR_cfs",	FALSE, PSR_c | PSR_f | PSR_s},
-  {"SPSR_cfx",	FALSE, PSR_c | PSR_f | PSR_x},
-  {"SPSR_csf",	FALSE, PSR_c | PSR_s | PSR_f},
-  {"SPSR_csx",	FALSE, PSR_c | PSR_s | PSR_x},
-  {"SPSR_cxf",	FALSE, PSR_c | PSR_x | PSR_f},
-  {"SPSR_cxs",	FALSE, PSR_c | PSR_x | PSR_s},
-  {"SPSR_fsxc",	FALSE, PSR_f | PSR_s | PSR_x | PSR_c},
-  {"SPSR_fscx",	FALSE, PSR_f | PSR_s | PSR_c | PSR_x},
-  {"SPSR_fxsc",	FALSE, PSR_f | PSR_x | PSR_s | PSR_c},
-  {"SPSR_fxcs",	FALSE, PSR_f | PSR_x | PSR_c | PSR_s},
-  {"SPSR_fcsx",	FALSE, PSR_f | PSR_c | PSR_s | PSR_x},
-  {"SPSR_fcxs",	FALSE, PSR_f | PSR_c | PSR_x | PSR_s},
-  {"SPSR_sfxc",	FALSE, PSR_s | PSR_f | PSR_x | PSR_c},
-  {"SPSR_sfcx",	FALSE, PSR_s | PSR_f | PSR_c | PSR_x},
-  {"SPSR_sxfc",	FALSE, PSR_s | PSR_x | PSR_f | PSR_c},
-  {"SPSR_sxcf",	FALSE, PSR_s | PSR_x | PSR_c | PSR_f},
-  {"SPSR_scfx",	FALSE, PSR_s | PSR_c | PSR_f | PSR_x},
-  {"SPSR_scxf",	FALSE, PSR_s | PSR_c | PSR_x | PSR_f},
-  {"SPSR_xfsc",	FALSE, PSR_x | PSR_f | PSR_s | PSR_c},
-  {"SPSR_xfcs",	FALSE, PSR_x | PSR_f | PSR_c | PSR_s},
-  {"SPSR_xsfc",	FALSE, PSR_x | PSR_s | PSR_f | PSR_c},
-  {"SPSR_xscf",	FALSE, PSR_x | PSR_s | PSR_c | PSR_f},
-  {"SPSR_xcfs",	FALSE, PSR_x | PSR_c | PSR_f | PSR_s},
-  {"SPSR_xcsf",	FALSE, PSR_x | PSR_c | PSR_s | PSR_f},
-  {"SPSR_cfsx",	FALSE, PSR_c | PSR_f | PSR_s | PSR_x},
-  {"SPSR_cfxs",	FALSE, PSR_c | PSR_f | PSR_x | PSR_s},
-  {"SPSR_csfx",	FALSE, PSR_c | PSR_s | PSR_f | PSR_x},
-  {"SPSR_csxf",	FALSE, PSR_c | PSR_s | PSR_x | PSR_f},
-  {"SPSR_cxfs",	FALSE, PSR_c | PSR_x | PSR_f | PSR_s},
-  {"SPSR_cxsf",	FALSE, PSR_c | PSR_x | PSR_s | PSR_f},
-};
-
-enum wreg_type
-  {
-    IWMMXT_REG_WR = 0,
-    IWMMXT_REG_WC = 1,
-    IWMMXT_REG_WR_OR_WC = 2,
-    IWMMXT_REG_WCG
-  };
-
-enum iwmmxt_insn_type
-{
-  check_rd,
-  check_wr,
-  check_wrwr,
-  check_wrwrwr,
-  check_wrwrwcg,
-  check_tbcst,
-  check_tmovmsk,
-  check_tmia,
-  check_tmcrr,
-  check_tmrrc,
-  check_tmcr,
-  check_tmrc,
-  check_tinsr,
-  check_textrc,
-  check_waligni,
-  check_textrm,
-  check_wshufh
-};
+/* The individual PSR flag bits.  */
+#define PSR_c	(1 << 16)
+#define PSR_x	(1 << 17)
+#define PSR_s	(1 << 18)
+#define PSR_f	(1 << 19)
 
-enum vfp_dp_reg_pos
+struct reloc_entry
 {
-  VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
+  char *name;
+  bfd_reloc_code_real_type reloc;
 };
 
 enum vfp_sp_reg_pos
@@ -581,1666 +365,101 @@ enum vfp_ldstm_type
   VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
 };
 
-/* VFP system registers.  */
-struct vfp_reg
-{
-  const char *name;
-  unsigned long regno;
-};
-
-static const struct vfp_reg vfp_regs[] =
+/* ARM register categories.  This includes coprocessor numbers and various
+   architecture extensions' registers.	*/
+enum arm_reg_type
 {
-  {"fpsid", 0x00000000},
-  {"FPSID", 0x00000000},
-  {"fpscr", 0x00010000},
-  {"FPSCR", 0x00010000},
-  {"fpexc", 0x00080000},
-  {"FPEXC", 0x00080000}
+  REG_TYPE_RN,
+  REG_TYPE_CP,
+  REG_TYPE_CN,
+  REG_TYPE_FN,
+  REG_TYPE_VFS,
+  REG_TYPE_VFD,
+  REG_TYPE_VFC,
+  REG_TYPE_MVF,
+  REG_TYPE_MVD,
+  REG_TYPE_MVFX,
+  REG_TYPE_MVDX,
+  REG_TYPE_MVAX,
+  REG_TYPE_DSPSC,
+  REG_TYPE_MMXWR,
+  REG_TYPE_MMXWC,
+  REG_TYPE_MMXWCG,
+  REG_TYPE_XSCALE,
 };
 
 /* Structure for a hash table entry for a register.  */
 struct reg_entry
 {
-  const char * name;
-  int          number;
-  bfd_boolean  builtin;
-};
-
-/* Some well known registers that we refer to directly elsewhere.  */
-#define REG_SP  13
-#define REG_LR  14
-#define REG_PC	15
-
-#define wr_register(reg)  ((reg ^ WR_PREFIX) >= 0 && (reg ^ WR_PREFIX) <= 15)
-#define wc_register(reg)  ((reg ^ WC_PREFIX) >= 0 && (reg ^ WC_PREFIX) <= 15)
-#define wcg_register(reg) ((reg ^ WC_PREFIX) >= 8 && (reg ^ WC_PREFIX) <= 11)
-
-/* These are the standard names.  Users can add aliases with .req.
-   and delete them with .unreq.  */
-
-/* Integer Register Numbers.  */
-static const struct reg_entry rn_table[] =
-{
-  {"r0",  0, TRUE},  {"r1",  1, TRUE},      {"r2",  2, TRUE},      {"r3",  3, TRUE},
-  {"r4",  4, TRUE},  {"r5",  5, TRUE},      {"r6",  6, TRUE},      {"r7",  7, TRUE},
-  {"r8",  8, TRUE},  {"r9",  9, TRUE},      {"r10", 10, TRUE},     {"r11", 11, TRUE},
-  {"r12", 12, TRUE}, {"r13", REG_SP, TRUE}, {"r14", REG_LR, TRUE}, {"r15", REG_PC, TRUE},
-  /* ATPCS Synonyms.  */
-  {"a1",  0, TRUE},  {"a2",  1, TRUE},      {"a3",  2, TRUE},      {"a4",  3, TRUE},
-  {"v1",  4, TRUE},  {"v2",  5, TRUE},      {"v3",  6, TRUE},      {"v4",  7, TRUE},
-  {"v5",  8, TRUE},  {"v6",  9, TRUE},      {"v7",  10, TRUE},     {"v8",  11, TRUE},
-  /* Well-known aliases.  */
-  {"wr",  7, TRUE},  {"sb",  9, TRUE},      {"sl",  10, TRUE},     {"fp",  11, TRUE},
-  {"ip",  12, TRUE}, {"sp",  REG_SP, TRUE}, {"lr",  REG_LR, TRUE}, {"pc",  REG_PC, TRUE},
-  {NULL, 0, TRUE}
-};
-
-#define WR_PREFIX 0x200
-#define WC_PREFIX 0x400
-
-static const struct reg_entry iwmmxt_table[] =
-{
-  /* Intel Wireless MMX technology register names.  */
-  {  "wr0", 0x0 | WR_PREFIX, TRUE},   {"wr1", 0x1 | WR_PREFIX, TRUE},
-  {  "wr2", 0x2 | WR_PREFIX, TRUE},   {"wr3", 0x3 | WR_PREFIX, TRUE},
-  {  "wr4", 0x4 | WR_PREFIX, TRUE},   {"wr5", 0x5 | WR_PREFIX, TRUE},
-  {  "wr6", 0x6 | WR_PREFIX, TRUE},   {"wr7", 0x7 | WR_PREFIX, TRUE},
-  {  "wr8", 0x8 | WR_PREFIX, TRUE},   {"wr9", 0x9 | WR_PREFIX, TRUE},
-  { "wr10", 0xa | WR_PREFIX, TRUE},  {"wr11", 0xb | WR_PREFIX, TRUE},
-  { "wr12", 0xc | WR_PREFIX, TRUE},  {"wr13", 0xd | WR_PREFIX, TRUE},
-  { "wr14", 0xe | WR_PREFIX, TRUE},  {"wr15", 0xf | WR_PREFIX, TRUE},
-  { "wcid", 0x0 | WC_PREFIX, TRUE},  {"wcon", 0x1 | WC_PREFIX, TRUE},
-  {"wcssf", 0x2 | WC_PREFIX, TRUE}, {"wcasf", 0x3 | WC_PREFIX, TRUE},
-  {"wcgr0", 0x8 | WC_PREFIX, TRUE}, {"wcgr1", 0x9 | WC_PREFIX, TRUE},
-  {"wcgr2", 0xa | WC_PREFIX, TRUE}, {"wcgr3", 0xb | WC_PREFIX, TRUE},
-
-  {  "wR0", 0x0 | WR_PREFIX, TRUE},   {"wR1", 0x1 | WR_PREFIX, TRUE},
-  {  "wR2", 0x2 | WR_PREFIX, TRUE},   {"wR3", 0x3 | WR_PREFIX, TRUE},
-  {  "wR4", 0x4 | WR_PREFIX, TRUE},   {"wR5", 0x5 | WR_PREFIX, TRUE},
-  {  "wR6", 0x6 | WR_PREFIX, TRUE},   {"wR7", 0x7 | WR_PREFIX, TRUE},
-  {  "wR8", 0x8 | WR_PREFIX, TRUE},   {"wR9", 0x9 | WR_PREFIX, TRUE},
-  { "wR10", 0xa | WR_PREFIX, TRUE},  {"wR11", 0xb | WR_PREFIX, TRUE},
-  { "wR12", 0xc | WR_PREFIX, TRUE},  {"wR13", 0xd | WR_PREFIX, TRUE},
-  { "wR14", 0xe | WR_PREFIX, TRUE},  {"wR15", 0xf | WR_PREFIX, TRUE},
-  { "wCID", 0x0 | WC_PREFIX, TRUE},  {"wCon", 0x1 | WC_PREFIX, TRUE},
-  {"wCSSF", 0x2 | WC_PREFIX, TRUE}, {"wCASF", 0x3 | WC_PREFIX, TRUE},
-  {"wCGR0", 0x8 | WC_PREFIX, TRUE}, {"wCGR1", 0x9 | WC_PREFIX, TRUE},
-  {"wCGR2", 0xa | WC_PREFIX, TRUE}, {"wCGR3", 0xb | WC_PREFIX, TRUE},
-  {NULL, 0, TRUE}
+  const char   *name;
+  unsigned char number;
+  unsigned char type;
+  unsigned char builtin;
 };
 
-/* Co-processor Numbers.  */
-static const struct reg_entry cp_table[] =
-{
-  {"p0",  0, TRUE},  {"p1",  1, TRUE},  {"p2",  2, TRUE},  {"p3", 3, TRUE},
-  {"p4",  4, TRUE},  {"p5",  5, TRUE},  {"p6",  6, TRUE},  {"p7", 7, TRUE},
-  {"p8",  8, TRUE},  {"p9",  9, TRUE},  {"p10", 10, TRUE}, {"p11", 11, TRUE},
-  {"p12", 12, TRUE}, {"p13", 13, TRUE}, {"p14", 14, TRUE}, {"p15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-/* Co-processor Register Numbers.  */
-static const struct reg_entry cn_table[] =
-{
-  {"c0",   0, TRUE},  {"c1",   1, TRUE},  {"c2",   2, TRUE},  {"c3",   3, TRUE},
-  {"c4",   4, TRUE},  {"c5",   5, TRUE},  {"c6",   6, TRUE},  {"c7",   7, TRUE},
-  {"c8",   8, TRUE},  {"c9",   9, TRUE},  {"c10",  10, TRUE}, {"c11",  11, TRUE},
-  {"c12",  12, TRUE}, {"c13",  13, TRUE}, {"c14",  14, TRUE}, {"c15",  15, TRUE},
-  /* Not really valid, but kept for back-wards compatibility.  */
-  {"cr0",  0, TRUE},  {"cr1",  1, TRUE},  {"cr2",  2, TRUE},  {"cr3",  3, TRUE},
-  {"cr4",  4, TRUE},  {"cr5",  5, TRUE},  {"cr6",  6, TRUE},  {"cr7",  7, TRUE},
-  {"cr8",  8, TRUE},  {"cr9",  9, TRUE},  {"cr10", 10, TRUE}, {"cr11", 11, TRUE},
-  {"cr12", 12, TRUE}, {"cr13", 13, TRUE}, {"cr14", 14, TRUE}, {"cr15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-/* FPA Registers.  */
-static const struct reg_entry fn_table[] =
-{
-  {"f0", 0, TRUE},   {"f1", 1, TRUE},   {"f2", 2, TRUE},   {"f3", 3, TRUE},
-  {"f4", 4, TRUE},   {"f5", 5, TRUE},   {"f6", 6, TRUE},   {"f7", 7, TRUE},
-  {NULL, 0, TRUE}
-};
-
-/* VFP SP Registers.  */
-static const struct reg_entry sn_table[] =
-{
-  {"s0",  0, TRUE},  {"s1",  1, TRUE},  {"s2",  2, TRUE},  {"s3", 3, TRUE},
-  {"s4",  4, TRUE},  {"s5",  5, TRUE},  {"s6",  6, TRUE},  {"s7", 7, TRUE},
-  {"s8",  8, TRUE},  {"s9",  9, TRUE},  {"s10", 10, TRUE}, {"s11", 11, TRUE},
-  {"s12", 12, TRUE}, {"s13", 13, TRUE}, {"s14", 14, TRUE}, {"s15", 15, TRUE},
-  {"s16", 16, TRUE}, {"s17", 17, TRUE}, {"s18", 18, TRUE}, {"s19", 19, TRUE},
-  {"s20", 20, TRUE}, {"s21", 21, TRUE}, {"s22", 22, TRUE}, {"s23", 23, TRUE},
-  {"s24", 24, TRUE}, {"s25", 25, TRUE}, {"s26", 26, TRUE}, {"s27", 27, TRUE},
-  {"s28", 28, TRUE}, {"s29", 29, TRUE}, {"s30", 30, TRUE}, {"s31", 31, TRUE},
-  {NULL, 0, TRUE}
-};
-
-/* VFP DP Registers.  */
-static const struct reg_entry dn_table[] =
-{
-  {"d0",  0, TRUE},  {"d1",  1, TRUE},  {"d2",  2, TRUE},  {"d3", 3, TRUE},
-  {"d4",  4, TRUE},  {"d5",  5, TRUE},  {"d6",  6, TRUE},  {"d7", 7, TRUE},
-  {"d8",  8, TRUE},  {"d9",  9, TRUE},  {"d10", 10, TRUE}, {"d11", 11, TRUE},
-  {"d12", 12, TRUE}, {"d13", 13, TRUE}, {"d14", 14, TRUE}, {"d15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-/* Maverick DSP coprocessor registers.  */
-static const struct reg_entry mav_mvf_table[] =
-{
-  {"mvf0",  0, TRUE},  {"mvf1",  1, TRUE},  {"mvf2",  2, TRUE},  {"mvf3",  3, TRUE},
-  {"mvf4",  4, TRUE},  {"mvf5",  5, TRUE},  {"mvf6",  6, TRUE},  {"mvf7",  7, TRUE},
-  {"mvf8",  8, TRUE},  {"mvf9",  9, TRUE},  {"mvf10", 10, TRUE}, {"mvf11", 11, TRUE},
-  {"mvf12", 12, TRUE}, {"mvf13", 13, TRUE}, {"mvf14", 14, TRUE}, {"mvf15", 15, TRUE},
-  {NULL, 0, TRUE}
+/* Diagnostics used when we don't get a register of the expected type.	*/
+const char *const reg_expected_msgs[] =
+{
+  N_("ARM register expected"),
+  N_("bad or missing co-processor number"),
+  N_("co-processor register expected"),
+  N_("FPA register expected"),
+  N_("VFP single precision register expected"),
+  N_("VFP double precision register expected"),
+  N_("VFP system register expected"),
+  N_("Maverick MVF register expected"),
+  N_("Maverick MVD register expected"),
+  N_("Maverick MVFX register expected"),
+  N_("Maverick MVDX register expected"),
+  N_("Maverick MVAX register expected"),
+  N_("Maverick DSPSC register expected"),
+  N_("iWMMXt data register expected"),
+  N_("iWMMXt control register expected"),
+  N_("iWMMXt scalar register expected"),
+  N_("XScale accumulator register expected"),
 };
 
-static const struct reg_entry mav_mvd_table[] =
-{
-  {"mvd0",  0, TRUE},  {"mvd1",  1, TRUE},  {"mvd2",  2, TRUE},  {"mvd3",  3, TRUE},
-  {"mvd4",  4, TRUE},  {"mvd5",  5, TRUE},  {"mvd6",  6, TRUE},  {"mvd7",  7, TRUE},
-  {"mvd8",  8, TRUE},  {"mvd9",  9, TRUE},  {"mvd10", 10, TRUE}, {"mvd11", 11, TRUE},
-  {"mvd12", 12, TRUE}, {"mvd13", 13, TRUE}, {"mvd14", 14, TRUE}, {"mvd15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-static const struct reg_entry mav_mvfx_table[] =
-{
-  {"mvfx0",  0, TRUE},  {"mvfx1",  1, TRUE},  {"mvfx2",  2, TRUE},  {"mvfx3",  3, TRUE},
-  {"mvfx4",  4, TRUE},  {"mvfx5",  5, TRUE},  {"mvfx6",  6, TRUE},  {"mvfx7",  7, TRUE},
-  {"mvfx8",  8, TRUE},  {"mvfx9",  9, TRUE},  {"mvfx10", 10, TRUE}, {"mvfx11", 11, TRUE},
-  {"mvfx12", 12, TRUE}, {"mvfx13", 13, TRUE}, {"mvfx14", 14, TRUE}, {"mvfx15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-static const struct reg_entry mav_mvdx_table[] =
-{
-  {"mvdx0",  0, TRUE},  {"mvdx1",  1, TRUE},  {"mvdx2",  2, TRUE},  {"mvdx3",  3, TRUE},
-  {"mvdx4",  4, TRUE},  {"mvdx5",  5, TRUE},  {"mvdx6",  6, TRUE},  {"mvdx7",  7, TRUE},
-  {"mvdx8",  8, TRUE},  {"mvdx9",  9, TRUE},  {"mvdx10", 10, TRUE}, {"mvdx11", 11, TRUE},
-  {"mvdx12", 12, TRUE}, {"mvdx13", 13, TRUE}, {"mvdx14", 14, TRUE}, {"mvdx15", 15, TRUE},
-  {NULL, 0, TRUE}
-};
-
-static const struct reg_entry mav_mvax_table[] =
-{
-  {"mvax0", 0, TRUE}, {"mvax1", 1, TRUE}, {"mvax2", 2, TRUE}, {"mvax3", 3, TRUE},
-  {NULL, 0, TRUE}
-};
-
-static const struct reg_entry mav_dspsc_table[] =
-{
-  {"dspsc", 0, TRUE},
-  {NULL, 0, TRUE}
-};
-
-struct reg_map
-{
-  const struct reg_entry *names;
-  int max_regno;
-  struct hash_control *htab;
-  const char *expected;
-};
-
-struct reg_map all_reg_maps[] =
-{
-  {rn_table,        15, NULL, N_("ARM register expected")},
-  {cp_table,        15, NULL, N_("bad or missing co-processor number")},
-  {cn_table,        15, NULL, N_("co-processor register expected")},
-  {fn_table,         7, NULL, N_("FPA register expected")},
-  {sn_table,	    31, NULL, N_("VFP single precision register expected")},
-  {dn_table,	    15, NULL, N_("VFP double precision register expected")},
-  {mav_mvf_table,   15, NULL, N_("Maverick MVF register expected")},
-  {mav_mvd_table,   15, NULL, N_("Maverick MVD register expected")},
-  {mav_mvfx_table,  15, NULL, N_("Maverick MVFX register expected")},
-  {mav_mvdx_table,  15, NULL, N_("Maverick MVDX register expected")},
-  {mav_mvax_table,   3, NULL, N_("Maverick MVAX register expected")},
-  {mav_dspsc_table,  0, NULL, N_("Maverick DSPSC register expected")},
-  {iwmmxt_table,    23, NULL, N_("Intel Wireless MMX technology register expected")},
-};
-
-/* Enumeration matching entries in table above.  */
-enum arm_reg_type
-{
-  REG_TYPE_RN = 0,
-#define REG_TYPE_FIRST REG_TYPE_RN
-  REG_TYPE_CP = 1,
-  REG_TYPE_CN = 2,
-  REG_TYPE_FN = 3,
-  REG_TYPE_SN = 4,
-  REG_TYPE_DN = 5,
-  REG_TYPE_MVF = 6,
-  REG_TYPE_MVD = 7,
-  REG_TYPE_MVFX = 8,
-  REG_TYPE_MVDX = 9,
-  REG_TYPE_MVAX = 10,
-  REG_TYPE_DSPSC = 11,
-  REG_TYPE_IWMMXT = 12,
-
-  REG_TYPE_MAX = 13
-};
-
-/* Functions called by parser.  */
-/* ARM instructions.  */
-static void do_arit		PARAMS ((char *));
-static void do_cmp		PARAMS ((char *));
-static void do_mov		PARAMS ((char *));
-static void do_ldst		PARAMS ((char *));
-static void do_ldstt		PARAMS ((char *));
-static void do_ldmstm		PARAMS ((char *));
-static void do_branch		PARAMS ((char *));
-static void do_swi		PARAMS ((char *));
-
-/* Pseudo Op codes.  */
-static void do_adr		PARAMS ((char *));
-static void do_adrl		PARAMS ((char *));
-static void do_empty		PARAMS ((char *));
-
-/* ARM v2.  */
-static void do_mul		PARAMS ((char *));
-static void do_mla		PARAMS ((char *));
-
-/* ARM v2S.  */
-static void do_swap		PARAMS ((char *));
-
-/* ARM v3.  */
-static void do_msr		PARAMS ((char *));
-static void do_mrs		PARAMS ((char *));
-
-/* ARM v3M.  */
-static void do_mull		PARAMS ((char *));
-
-/* ARM v4.  */
-static void do_ldstv4		PARAMS ((char *));
-
-/* ARM v4T.  */
-static void do_bx               PARAMS ((char *));
-
-/* ARM v5T.  */
-static void do_blx		PARAMS ((char *));
-static void do_bkpt		PARAMS ((char *));
-static void do_clz		PARAMS ((char *));
-static void do_lstc2		PARAMS ((char *));
-static void do_cdp2		PARAMS ((char *));
-static void do_co_reg2		PARAMS ((char *));
-
-/* ARM v5TExP.  */
-static void do_smla		PARAMS ((char *));
-static void do_smlal		PARAMS ((char *));
-static void do_smul		PARAMS ((char *));
-static void do_qadd		PARAMS ((char *));
-
-/* ARM v5TE.  */
-static void do_pld		PARAMS ((char *));
-static void do_ldrd		PARAMS ((char *));
-static void do_co_reg2c		PARAMS ((char *));
-
-/* ARM v5TEJ.  */
-static void do_bxj		PARAMS ((char *));
-
-/* ARM V6. */
-static void do_cps              PARAMS ((char *));
-static void do_cpsi             PARAMS ((char *));
-static void do_ldrex            PARAMS ((char *));
-static void do_pkhbt            PARAMS ((char *));
-static void do_pkhtb            PARAMS ((char *));
-static void do_qadd16           PARAMS ((char *));
-static void do_rev              PARAMS ((char *));
-static void do_rfe              PARAMS ((char *));
-static void do_sxtah            PARAMS ((char *));
-static void do_sxth             PARAMS ((char *));
-static void do_setend           PARAMS ((char *));
-static void do_smlad            PARAMS ((char *));
-static void do_smlald           PARAMS ((char *));
-static void do_smmul            PARAMS ((char *));
-static void do_ssat             PARAMS ((char *));
-static void do_usat             PARAMS ((char *));
-static void do_srs              PARAMS ((char *));
-static void do_ssat16           PARAMS ((char *));
-static void do_usat16           PARAMS ((char *));
-static void do_strex            PARAMS ((char *));
-static void do_umaal            PARAMS ((char *));
-
-static void do_cps_mode         PARAMS ((char **));
-static void do_cps_flags        PARAMS ((char **, int));
-static int do_endian_specifier  PARAMS ((char *));
-static void do_pkh_core         PARAMS ((char *, int));
-static void do_sat              PARAMS ((char **, int));
-static void do_sat16            PARAMS ((char **, int));
-
-/* Coprocessor Instructions.  */
-static void do_cdp		PARAMS ((char *));
-static void do_lstc		PARAMS ((char *));
-static void do_co_reg		PARAMS ((char *));
-
-/* FPA instructions.  */
-static void do_fpa_ctrl		PARAMS ((char *));
-static void do_fpa_ldst		PARAMS ((char *));
-static void do_fpa_ldmstm	PARAMS ((char *));
-static void do_fpa_dyadic	PARAMS ((char *));
-static void do_fpa_monadic	PARAMS ((char *));
-static void do_fpa_cmp		PARAMS ((char *));
-static void do_fpa_from_reg	PARAMS ((char *));
-static void do_fpa_to_reg	PARAMS ((char *));
-
-/* VFP instructions.  */
-static void do_vfp_sp_monadic	PARAMS ((char *));
-static void do_vfp_dp_monadic	PARAMS ((char *));
-static void do_vfp_sp_dyadic	PARAMS ((char *));
-static void do_vfp_dp_dyadic	PARAMS ((char *));
-static void do_vfp_reg_from_sp  PARAMS ((char *));
-static void do_vfp_sp_from_reg  PARAMS ((char *));
-static void do_vfp_reg2_from_sp2 PARAMS ((char *));
-static void do_vfp_sp2_from_reg2 PARAMS ((char *));
-static void do_vfp_reg_from_dp  PARAMS ((char *));
-static void do_vfp_reg2_from_dp PARAMS ((char *));
-static void do_vfp_dp_from_reg  PARAMS ((char *));
-static void do_vfp_dp_from_reg2 PARAMS ((char *));
-static void do_vfp_reg_from_ctrl PARAMS ((char *));
-static void do_vfp_ctrl_from_reg PARAMS ((char *));
-static void do_vfp_sp_ldst	PARAMS ((char *));
-static void do_vfp_dp_ldst	PARAMS ((char *));
-static void do_vfp_sp_ldstmia	PARAMS ((char *));
-static void do_vfp_sp_ldstmdb	PARAMS ((char *));
-static void do_vfp_dp_ldstmia	PARAMS ((char *));
-static void do_vfp_dp_ldstmdb	PARAMS ((char *));
-static void do_vfp_xp_ldstmia	PARAMS ((char *));
-static void do_vfp_xp_ldstmdb	PARAMS ((char *));
-static void do_vfp_sp_compare_z	PARAMS ((char *));
-static void do_vfp_dp_compare_z	PARAMS ((char *));
-static void do_vfp_dp_sp_cvt	PARAMS ((char *));
-static void do_vfp_sp_dp_cvt	PARAMS ((char *));
-
-/* XScale.  */
-static void do_xsc_mia		PARAMS ((char *));
-static void do_xsc_mar		PARAMS ((char *));
-static void do_xsc_mra		PARAMS ((char *));
-
-/* Maverick.  */
-static void do_mav_binops	PARAMS ((char *, int, enum arm_reg_type,
-					 enum arm_reg_type));
-static void do_mav_binops_1a	PARAMS ((char *));
-static void do_mav_binops_1b	PARAMS ((char *));
-static void do_mav_binops_1c	PARAMS ((char *));
-static void do_mav_binops_1d	PARAMS ((char *));
-static void do_mav_binops_1e	PARAMS ((char *));
-static void do_mav_binops_1f	PARAMS ((char *));
-static void do_mav_binops_1g	PARAMS ((char *));
-static void do_mav_binops_1h	PARAMS ((char *));
-static void do_mav_binops_1i	PARAMS ((char *));
-static void do_mav_binops_1j	PARAMS ((char *));
-static void do_mav_binops_1k	PARAMS ((char *));
-static void do_mav_binops_1l	PARAMS ((char *));
-static void do_mav_binops_1m	PARAMS ((char *));
-static void do_mav_binops_1n	PARAMS ((char *));
-static void do_mav_binops_1o	PARAMS ((char *));
-static void do_mav_binops_2a	PARAMS ((char *));
-static void do_mav_binops_2b	PARAMS ((char *));
-static void do_mav_binops_2c	PARAMS ((char *));
-static void do_mav_binops_3a	PARAMS ((char *));
-static void do_mav_binops_3b	PARAMS ((char *));
-static void do_mav_binops_3c	PARAMS ((char *));
-static void do_mav_binops_3d	PARAMS ((char *));
-static void do_mav_triple	PARAMS ((char *, int, enum arm_reg_type,
-					 enum arm_reg_type,
-					 enum arm_reg_type));
-static void do_mav_triple_4a	PARAMS ((char *));
-static void do_mav_triple_4b	PARAMS ((char *));
-static void do_mav_triple_5a	PARAMS ((char *));
-static void do_mav_triple_5b	PARAMS ((char *));
-static void do_mav_triple_5c	PARAMS ((char *));
-static void do_mav_triple_5d	PARAMS ((char *));
-static void do_mav_triple_5e	PARAMS ((char *));
-static void do_mav_triple_5f	PARAMS ((char *));
-static void do_mav_triple_5g	PARAMS ((char *));
-static void do_mav_triple_5h	PARAMS ((char *));
-static void do_mav_quad		PARAMS ((char *, int, enum arm_reg_type,
-					 enum arm_reg_type,
-					 enum arm_reg_type,
-					 enum arm_reg_type));
-static void do_mav_quad_6a	PARAMS ((char *));
-static void do_mav_quad_6b	PARAMS ((char *));
-static void do_mav_dspsc_1	PARAMS ((char *));
-static void do_mav_dspsc_2	PARAMS ((char *));
-static void do_mav_shift	PARAMS ((char *, enum arm_reg_type,
-					 enum arm_reg_type));
-static void do_mav_shift_1	PARAMS ((char *));
-static void do_mav_shift_2	PARAMS ((char *));
-static void do_mav_ldst		PARAMS ((char *, enum arm_reg_type));
-static void do_mav_ldst_1	PARAMS ((char *));
-static void do_mav_ldst_2	PARAMS ((char *));
-static void do_mav_ldst_3	PARAMS ((char *));
-static void do_mav_ldst_4	PARAMS ((char *));
-
-static int mav_reg_required_here	PARAMS ((char **, int,
-						 enum arm_reg_type));
-static int mav_parse_offset	PARAMS ((char **, int *));
-
-static void fix_new_arm		PARAMS ((fragS *, int, short, expressionS *,
-					 int, int));
-static int arm_reg_parse	PARAMS ((char **, struct hash_control *));
-static enum arm_reg_type arm_reg_parse_any PARAMS ((char *));
-static const struct asm_psr * arm_psr_parse PARAMS ((char **));
-static void symbol_locate	PARAMS ((symbolS *, const char *, segT, valueT,
-					 fragS *));
-static int add_to_lit_pool	PARAMS ((void));
-static unsigned validate_immediate PARAMS ((unsigned));
-static unsigned validate_immediate_twopart PARAMS ((unsigned int,
-						    unsigned int *));
-static int validate_offset_imm	PARAMS ((unsigned int, int));
-static void opcode_select	PARAMS ((int));
-static void end_of_line		PARAMS ((char *));
-static int reg_required_here	PARAMS ((char **, int));
-static int psr_required_here	PARAMS ((char **));
-static int co_proc_number	PARAMS ((char **));
-static int cp_opc_expr		PARAMS ((char **, int, int));
-static int cp_reg_required_here	PARAMS ((char **, int));
-static int fp_reg_required_here	PARAMS ((char **, int));
-static int vfp_sp_reg_required_here PARAMS ((char **, enum vfp_sp_reg_pos));
-static int vfp_dp_reg_required_here PARAMS ((char **, enum vfp_dp_reg_pos));
-static void vfp_sp_ldstm	PARAMS ((char *, enum vfp_ldstm_type));
-static void vfp_dp_ldstm	PARAMS ((char *, enum vfp_ldstm_type));
-static long vfp_sp_reg_list	PARAMS ((char **, enum vfp_sp_reg_pos));
-static long vfp_dp_reg_list	PARAMS ((char **));
-static int vfp_psr_required_here PARAMS ((char **str));
-static const struct vfp_reg *vfp_psr_parse PARAMS ((char **str));
-static int cp_address_offset	PARAMS ((char **));
-static int cp_address_required_here	PARAMS ((char **, int));
-static int my_get_float_expression	PARAMS ((char **));
-static int skip_past_comma	PARAMS ((char **));
-static int walk_no_bignums	PARAMS ((symbolS *));
-static int negate_data_op	PARAMS ((unsigned long *, unsigned long));
-static int data_op2		PARAMS ((char **));
-static int fp_op2		PARAMS ((char **));
-static long reg_list		PARAMS ((char **));
-static void thumb_load_store	PARAMS ((char *, int, int));
-static int decode_shift		PARAMS ((char **, int));
-static int ldst_extend		PARAMS ((char **));
-static int ldst_extend_v4		PARAMS ((char **));
-static void thumb_add_sub	PARAMS ((char *, int));
-static void insert_reg		PARAMS ((const struct reg_entry *,
-					 struct hash_control *));
-static void thumb_shift		PARAMS ((char *, int));
-static void thumb_mov_compare	PARAMS ((char *, int));
-static void build_arm_ops_hsh	PARAMS ((void));
-static void set_constant_flonums	PARAMS ((void));
-static valueT md_chars_to_number	PARAMS ((char *, int));
-static void build_reg_hsh	PARAMS ((struct reg_map *));
-static void insert_reg_alias	PARAMS ((char *, int, struct hash_control *));
-static int create_register_alias	PARAMS ((char *, char *));
-static void output_inst		PARAMS ((const char *));
-static int accum0_required_here PARAMS ((char **));
-static int ld_mode_required_here PARAMS ((char **));
-static void do_branch25         PARAMS ((char *));
-static symbolS * find_real_start PARAMS ((symbolS *));
-#ifdef OBJ_ELF
-static bfd_reloc_code_real_type	arm_parse_reloc PARAMS ((void));
-#endif
-
-static int wreg_required_here   PARAMS ((char **, int, enum wreg_type));
-static void do_iwmmxt_byte_addr PARAMS ((char *));
-static void do_iwmmxt_tandc     PARAMS ((char *));
-static void do_iwmmxt_tbcst     PARAMS ((char *));
-static void do_iwmmxt_textrc    PARAMS ((char *));
-static void do_iwmmxt_textrm    PARAMS ((char *));
-static void do_iwmmxt_tinsr     PARAMS ((char *));
-static void do_iwmmxt_tmcr      PARAMS ((char *));
-static void do_iwmmxt_tmcrr     PARAMS ((char *));
-static void do_iwmmxt_tmia      PARAMS ((char *));
-static void do_iwmmxt_tmovmsk   PARAMS ((char *));
-static void do_iwmmxt_tmrc      PARAMS ((char *));
-static void do_iwmmxt_tmrrc     PARAMS ((char *));
-static void do_iwmmxt_torc      PARAMS ((char *));
-static void do_iwmmxt_waligni   PARAMS ((char *));
-static void do_iwmmxt_wmov      PARAMS ((char *));
-static void do_iwmmxt_word_addr PARAMS ((char *));
-static void do_iwmmxt_wrwr      PARAMS ((char *));
-static void do_iwmmxt_wrwrwcg   PARAMS ((char *));
-static void do_iwmmxt_wrwrwr    PARAMS ((char *));
-static void do_iwmmxt_wshufh    PARAMS ((char *));
-static void do_iwmmxt_wzero     PARAMS ((char *));
-static int cp_byte_address_offset         PARAMS ((char **));
-static int cp_byte_address_required_here  PARAMS ((char **));
+/* Some well known registers that we refer to directly elsewhere.  */
+#define REG_SP	13
+#define REG_LR	14
+#define REG_PC	15
 
 /* ARM instructions take 4bytes in the object file, Thumb instructions
    take 2:  */
-#define INSN_SIZE       4
-
-/* "INSN<cond> X,Y" where X:bit12, Y:bit16.  */
-#define MAV_MODE1	0x100c
-
-/* "INSN<cond> X,Y" where X:bit16, Y:bit12.  */
-#define MAV_MODE2	0x0c10
-
-/* "INSN<cond> X,Y" where X:bit12, Y:bit16.  */
-#define MAV_MODE3	0x100c
-
-/* "INSN<cond> X,Y,Z" where X:16, Y:0, Z:12.  */
-#define MAV_MODE4	0x0c0010
-
-/* "INSN<cond> X,Y,Z" where X:12, Y:16, Z:0.  */
-#define MAV_MODE5	0x00100c
-
-/* "INSN<cond> W,X,Y,Z" where W:5, X:12, Y:16, Z:0.  */
-#define MAV_MODE6	0x00100c05
+#define INSN_SIZE	4
 
 struct asm_opcode
 {
   /* Basic string to match.  */
-  const char * template;
-
-  /* Basic instruction code.  */
-  unsigned long value;
-
-  /* Offset into the template where the condition code (if any) will be.
-     If zero, then the instruction is never conditional.  */
-  unsigned cond_offset;
-
-  /* Which architecture variant provides this instruction.  */
-  unsigned long variant;
-
-  /* Function to call to parse args.  */
-  void (* parms) PARAMS ((char *));
-};
-
-static const struct asm_opcode insns[] =
-{
-  /* Core ARM Instructions.  */
-  {"and",        0xe0000000, 3,  ARM_EXT_V1,       do_arit},
-  {"ands",       0xe0100000, 3,  ARM_EXT_V1,       do_arit},
-  {"eor",        0xe0200000, 3,  ARM_EXT_V1,       do_arit},
-  {"eors",       0xe0300000, 3,  ARM_EXT_V1,       do_arit},
-  {"sub",        0xe0400000, 3,  ARM_EXT_V1,       do_arit},
-  {"subs",       0xe0500000, 3,  ARM_EXT_V1,       do_arit},
-  {"rsb",        0xe0600000, 3,  ARM_EXT_V1,       do_arit},
-  {"rsbs",       0xe0700000, 3,  ARM_EXT_V1,       do_arit},
-  {"add",        0xe0800000, 3,  ARM_EXT_V1,       do_arit},
-  {"adds",       0xe0900000, 3,  ARM_EXT_V1,       do_arit},
-  {"adc",        0xe0a00000, 3,  ARM_EXT_V1,       do_arit},
-  {"adcs",       0xe0b00000, 3,  ARM_EXT_V1,       do_arit},
-  {"sbc",        0xe0c00000, 3,  ARM_EXT_V1,       do_arit},
-  {"sbcs",       0xe0d00000, 3,  ARM_EXT_V1,       do_arit},
-  {"rsc",        0xe0e00000, 3,  ARM_EXT_V1,       do_arit},
-  {"rscs",       0xe0f00000, 3,  ARM_EXT_V1,       do_arit},
-  {"orr",        0xe1800000, 3,  ARM_EXT_V1,       do_arit},
-  {"orrs",       0xe1900000, 3,  ARM_EXT_V1,       do_arit},
-  {"bic",        0xe1c00000, 3,  ARM_EXT_V1,       do_arit},
-  {"bics",       0xe1d00000, 3,  ARM_EXT_V1,       do_arit},
-
-  {"tst",        0xe1100000, 3,  ARM_EXT_V1,       do_cmp},
-  {"tsts",       0xe1100000, 3,  ARM_EXT_V1,       do_cmp},
-  {"tstp",       0xe110f000, 3,  ARM_EXT_V1,       do_cmp},
-  {"teq",        0xe1300000, 3,  ARM_EXT_V1,       do_cmp},
-  {"teqs",       0xe1300000, 3,  ARM_EXT_V1,       do_cmp},
-  {"teqp",       0xe130f000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmp",        0xe1500000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmps",       0xe1500000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmpp",       0xe150f000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmn",        0xe1700000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmns",       0xe1700000, 3,  ARM_EXT_V1,       do_cmp},
-  {"cmnp",       0xe170f000, 3,  ARM_EXT_V1,       do_cmp},
-
-  {"mov",        0xe1a00000, 3,  ARM_EXT_V1,       do_mov},
-  {"movs",       0xe1b00000, 3,  ARM_EXT_V1,       do_mov},
-  {"mvn",        0xe1e00000, 3,  ARM_EXT_V1,       do_mov},
-  {"mvns",       0xe1f00000, 3,  ARM_EXT_V1,       do_mov},
-
-  {"ldr",        0xe4100000, 3,  ARM_EXT_V1,       do_ldst},
-  {"ldrb",       0xe4500000, 3,  ARM_EXT_V1,       do_ldst},
-  {"ldrt",       0xe4300000, 3,  ARM_EXT_V1,       do_ldstt},
-  {"ldrbt",      0xe4700000, 3,  ARM_EXT_V1,       do_ldstt},
-  {"str",        0xe4000000, 3,  ARM_EXT_V1,       do_ldst},
-  {"strb",       0xe4400000, 3,  ARM_EXT_V1,       do_ldst},
-  {"strt",       0xe4200000, 3,  ARM_EXT_V1,       do_ldstt},
-  {"strbt",      0xe4600000, 3,  ARM_EXT_V1,       do_ldstt},
-
-  {"stmia",      0xe8800000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmib",      0xe9800000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmda",      0xe8000000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmdb",      0xe9000000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmfd",      0xe9000000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmfa",      0xe9800000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmea",      0xe8800000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"stmed",      0xe8000000, 3,  ARM_EXT_V1,       do_ldmstm},
-
-  {"ldmia",      0xe8900000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmib",      0xe9900000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmda",      0xe8100000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmdb",      0xe9100000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmfd",      0xe8900000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmfa",      0xe8100000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmea",      0xe9100000, 3,  ARM_EXT_V1,       do_ldmstm},
-  {"ldmed",      0xe9900000, 3,  ARM_EXT_V1,       do_ldmstm},
-
-  {"swi",        0xef000000, 3,  ARM_EXT_V1,       do_swi},
-#ifdef TE_WINCE
-  /* XXX This is the wrong place to do this.  Think multi-arch.  */
-  {"bl",         0xeb000000, 2,  ARM_EXT_V1,       do_branch},
-  {"b",          0xea000000, 1,  ARM_EXT_V1,       do_branch},
-#else
-  {"bl",         0xebfffffe, 2,  ARM_EXT_V1,       do_branch},
-  {"b",          0xeafffffe, 1,  ARM_EXT_V1,       do_branch},
-#endif
-
-  /* Pseudo ops.  */
-  {"adr",        0xe28f0000, 3,  ARM_EXT_V1,       do_adr},
-  {"adrl",       0xe28f0000, 3,  ARM_EXT_V1,       do_adrl},
-  {"nop",        0xe1a00000, 3,  ARM_EXT_V1,       do_empty},
-
-  /* ARM 2 multiplies.  */
-  {"mul",        0xe0000090, 3,  ARM_EXT_V2,       do_mul},
-  {"muls",       0xe0100090, 3,  ARM_EXT_V2,       do_mul},
-  {"mla",        0xe0200090, 3,  ARM_EXT_V2,       do_mla},
-  {"mlas",       0xe0300090, 3,  ARM_EXT_V2,       do_mla},
-
-  /* Generic coprocessor instructions.  */
-  {"cdp",        0xee000000, 3,  ARM_EXT_V2,       do_cdp},
-  {"ldc",        0xec100000, 3,  ARM_EXT_V2,       do_lstc},
-  {"ldcl",       0xec500000, 3,  ARM_EXT_V2,       do_lstc},
-  {"stc",        0xec000000, 3,  ARM_EXT_V2,       do_lstc},
-  {"stcl",       0xec400000, 3,  ARM_EXT_V2,       do_lstc},
-  {"mcr",        0xee000010, 3,  ARM_EXT_V2,       do_co_reg},
-  {"mrc",        0xee100010, 3,  ARM_EXT_V2,       do_co_reg},
-
-  /* ARM 3 - swp instructions.  */
-  {"swp",        0xe1000090, 3,  ARM_EXT_V2S,      do_swap},
-  {"swpb",       0xe1400090, 3,  ARM_EXT_V2S,      do_swap},
-
-  /* ARM 6 Status register instructions.  */
-  {"mrs",        0xe10f0000, 3,  ARM_EXT_V3,       do_mrs},
-  {"msr",        0xe120f000, 3,  ARM_EXT_V3,       do_msr},
-  /* ScottB: our code uses     0xe128f000 for msr.
-     NickC:  but this is wrong because the bits 16 through 19 are
-             handled by the PSR_xxx defines above.  */
-
-  /* ARM 7M long multiplies.  */
-  {"smull",      0xe0c00090, 5,  ARM_EXT_V3M,      do_mull},
-  {"smulls",     0xe0d00090, 5,  ARM_EXT_V3M,      do_mull},
-  {"umull",      0xe0800090, 5,  ARM_EXT_V3M,      do_mull},
-  {"umulls",     0xe0900090, 5,  ARM_EXT_V3M,      do_mull},
-  {"smlal",      0xe0e00090, 5,  ARM_EXT_V3M,      do_mull},
-  {"smlals",     0xe0f00090, 5,  ARM_EXT_V3M,      do_mull},
-  {"umlal",      0xe0a00090, 5,  ARM_EXT_V3M,      do_mull},
-  {"umlals",     0xe0b00090, 5,  ARM_EXT_V3M,      do_mull},
-
-  /* ARM Architecture 4.  */
-  {"ldrh",       0xe01000b0, 3,  ARM_EXT_V4,       do_ldstv4},
-  {"ldrsh",      0xe01000f0, 3,  ARM_EXT_V4,       do_ldstv4},
-  {"ldrsb",      0xe01000d0, 3,  ARM_EXT_V4,       do_ldstv4},
-  {"strh",       0xe00000b0, 3,  ARM_EXT_V4,       do_ldstv4},
-
-  /* ARM Architecture 4T.  */
-  /* Note: bx (and blx) are required on V5, even if the processor does
-     not support Thumb.  */
-  {"bx",         0xe12fff10, 2,  ARM_EXT_V4T | ARM_EXT_V5, do_bx},
-
-  /*  ARM Architecture 5T.  */
-  /* Note: blx has 2 variants, so the .value is set dynamically.
-     Only one of the variants has conditional execution.  */
-  {"blx",        0xe0000000, 3,  ARM_EXT_V5,       do_blx},
-  {"clz",        0xe16f0f10, 3,  ARM_EXT_V5,       do_clz},
-  {"bkpt",       0xe1200070, 0,  ARM_EXT_V5,       do_bkpt},
-  {"ldc2",       0xfc100000, 0,  ARM_EXT_V5,       do_lstc2},
-  {"ldc2l",      0xfc500000, 0,  ARM_EXT_V5,       do_lstc2},
-  {"stc2",       0xfc000000, 0,  ARM_EXT_V5,       do_lstc2},
-  {"stc2l",      0xfc400000, 0,  ARM_EXT_V5,       do_lstc2},
-  {"cdp2",       0xfe000000, 0,  ARM_EXT_V5,       do_cdp2},
-  {"mcr2",       0xfe000010, 0,  ARM_EXT_V5,       do_co_reg2},
-  {"mrc2",       0xfe100010, 0,  ARM_EXT_V5,       do_co_reg2},
-
-  /*  ARM Architecture 5TExP.  */
-  {"smlabb",     0xe1000080, 6,  ARM_EXT_V5ExP,    do_smla},
-  {"smlatb",     0xe10000a0, 6,  ARM_EXT_V5ExP,    do_smla},
-  {"smlabt",     0xe10000c0, 6,  ARM_EXT_V5ExP,    do_smla},
-  {"smlatt",     0xe10000e0, 6,  ARM_EXT_V5ExP,    do_smla},
-
-  {"smlawb",     0xe1200080, 6,  ARM_EXT_V5ExP,    do_smla},
-  {"smlawt",     0xe12000c0, 6,  ARM_EXT_V5ExP,    do_smla},
-
-  {"smlalbb",    0xe1400080, 7,  ARM_EXT_V5ExP,    do_smlal},
-  {"smlaltb",    0xe14000a0, 7,  ARM_EXT_V5ExP,    do_smlal},
-  {"smlalbt",    0xe14000c0, 7,  ARM_EXT_V5ExP,    do_smlal},
-  {"smlaltt",    0xe14000e0, 7,  ARM_EXT_V5ExP,    do_smlal},
-
-  {"smulbb",     0xe1600080, 6,  ARM_EXT_V5ExP,    do_smul},
-  {"smultb",     0xe16000a0, 6,  ARM_EXT_V5ExP,    do_smul},
-  {"smulbt",     0xe16000c0, 6,  ARM_EXT_V5ExP,    do_smul},
-  {"smultt",     0xe16000e0, 6,  ARM_EXT_V5ExP,    do_smul},
-
-  {"smulwb",     0xe12000a0, 6,  ARM_EXT_V5ExP,    do_smul},
-  {"smulwt",     0xe12000e0, 6,  ARM_EXT_V5ExP,    do_smul},
-
-  {"qadd",       0xe1000050, 4,  ARM_EXT_V5ExP,    do_qadd},
-  {"qdadd",      0xe1400050, 5,  ARM_EXT_V5ExP,    do_qadd},
-  {"qsub",       0xe1200050, 4,  ARM_EXT_V5ExP,    do_qadd},
-  {"qdsub",      0xe1600050, 5,  ARM_EXT_V5ExP,    do_qadd},
-
-  /*  ARM Architecture 5TE.  */
-  {"pld",        0xf450f000, 0,  ARM_EXT_V5E,      do_pld},
-  {"ldrd",       0xe00000d0, 3,  ARM_EXT_V5E,      do_ldrd},
-  {"strd",       0xe00000f0, 3,  ARM_EXT_V5E,      do_ldrd},
-
-  {"mcrr",       0xec400000, 4,  ARM_EXT_V5E,      do_co_reg2c},
-  {"mrrc",       0xec500000, 4,  ARM_EXT_V5E,      do_co_reg2c},
-
-  /*  ARM Architecture 5TEJ.  */
-  {"bxj",	 0xe12fff20, 3,  ARM_EXT_V5J,	   do_bxj},
-
-  /*  ARM V6.  */
-  { "cps",       0xf1020000, 0,  ARM_EXT_V6,       do_cps},
-  { "cpsie",     0xf1080000, 0,  ARM_EXT_V6,       do_cpsi},
-  { "cpsid",     0xf10C0000, 0,  ARM_EXT_V6,       do_cpsi},
-  { "ldrex",     0xe1900f9f, 5,  ARM_EXT_V6,       do_ldrex},
-  { "mcrr2",     0xfc400000, 0,  ARM_EXT_V6,       do_co_reg2c},
-  { "mrrc2",     0xfc500000, 0,  ARM_EXT_V6,       do_co_reg2c},
-  { "pkhbt",     0xe6800010, 5,  ARM_EXT_V6,       do_pkhbt},
-  { "pkhtb",     0xe6800050, 5,  ARM_EXT_V6,       do_pkhtb},
-  { "qadd16",    0xe6200f10, 6,  ARM_EXT_V6,       do_qadd16},
-  { "qadd8",     0xe6200f90, 5,  ARM_EXT_V6,       do_qadd16},
-  { "qaddsubx",  0xe6200f30, 8,  ARM_EXT_V6,       do_qadd16},
-  { "qsub16",    0xe6200f70, 6,  ARM_EXT_V6,       do_qadd16},
-  { "qsub8",     0xe6200ff0, 5,  ARM_EXT_V6,       do_qadd16},
-  { "qsubaddx",  0xe6200f50, 8,  ARM_EXT_V6,       do_qadd16},
-  { "sadd16",    0xe6100f10, 6,  ARM_EXT_V6,       do_qadd16},
-  { "sadd8",     0xe6100f90, 5,  ARM_EXT_V6,       do_qadd16},
-  { "saddsubx",  0xe6100f30, 8,  ARM_EXT_V6,       do_qadd16},
-  { "shadd16",   0xe6300f10, 7,  ARM_EXT_V6,       do_qadd16},
-  { "shadd8",    0xe6300f90, 6,  ARM_EXT_V6,       do_qadd16},
-  { "shaddsubx", 0xe6300f30, 9,  ARM_EXT_V6,       do_qadd16},
-  { "shsub16",   0xe6300f70, 7,  ARM_EXT_V6,       do_qadd16},
-  { "shsub8",    0xe6300ff0, 6,  ARM_EXT_V6,       do_qadd16},
-  { "shsubaddx", 0xe6300f50, 9,  ARM_EXT_V6,       do_qadd16},
-  { "ssub16",    0xe6100f70, 6,  ARM_EXT_V6,       do_qadd16},
-  { "ssub8",     0xe6100ff0, 5,  ARM_EXT_V6,       do_qadd16},
-  { "ssubaddx",  0xe6100f50, 8,  ARM_EXT_V6,       do_qadd16},
-  { "uadd16",    0xe6500f10, 6,  ARM_EXT_V6,       do_qadd16},
-  { "uadd8",     0xe6500f90, 5,  ARM_EXT_V6,       do_qadd16},
-  { "uaddsubx",  0xe6500f30, 8,  ARM_EXT_V6,       do_qadd16},
-  { "uhadd16",   0xe6700f10, 7,  ARM_EXT_V6,       do_qadd16},
-  { "uhadd8",    0xe6700f90, 6,  ARM_EXT_V6,       do_qadd16},
-  { "uhaddsubx", 0xe6700f30, 9,  ARM_EXT_V6,       do_qadd16},
-  { "uhsub16",   0xe6700f70, 7,  ARM_EXT_V6,       do_qadd16},
-  { "uhsub8",    0xe6700ff0, 6,  ARM_EXT_V6,       do_qadd16},
-  { "uhsubaddx", 0xe6700f50, 9,  ARM_EXT_V6,       do_qadd16},
-  { "uqadd16",   0xe6600f10, 7,  ARM_EXT_V6,       do_qadd16},
-  { "uqadd8",    0xe6600f90, 6,  ARM_EXT_V6,       do_qadd16},
-  { "uqaddsubx", 0xe6600f30, 9,  ARM_EXT_V6,       do_qadd16},
-  { "uqsub16",   0xe6600f70, 7,  ARM_EXT_V6,       do_qadd16},
-  { "uqsub8",    0xe6600ff0, 6,  ARM_EXT_V6,       do_qadd16},
-  { "uqsubaddx", 0xe6600f50, 9,  ARM_EXT_V6,       do_qadd16},
-  { "usub16",    0xe6500f70, 6,  ARM_EXT_V6,       do_qadd16},
-  { "usub8",     0xe6500ff0, 5,  ARM_EXT_V6,       do_qadd16},
-  { "usubaddx",  0xe6500f50, 8,  ARM_EXT_V6,       do_qadd16},
-  { "rev",       0xe6bf0f30, 3,  ARM_EXT_V6,       do_rev},
-  { "rev16",     0xe6bf0fb0, 5,  ARM_EXT_V6,       do_rev},
-  { "revsh",     0xe6ff0fb0, 5,  ARM_EXT_V6,       do_rev},
-  { "rfeia",     0xf8900a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfeib",     0xf9900a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfeda",     0xf8100a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfedb",     0xf9100a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfefd",     0xf8900a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfefa",     0xf9900a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfeea",     0xf8100a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "rfeed",     0xf9100a00, 0,  ARM_EXT_V6,       do_rfe},
-  { "sxtah",     0xe6b00070, 5,  ARM_EXT_V6,       do_sxtah},
-  { "sxtab16",   0xe6800070, 7,  ARM_EXT_V6,       do_sxtah},
-  { "sxtab",     0xe6a00070, 5,  ARM_EXT_V6,       do_sxtah},
-  { "sxth",      0xe6bf0070, 4,  ARM_EXT_V6,       do_sxth},
-  { "sxtb16",    0xe68f0070, 6,  ARM_EXT_V6,       do_sxth},
-  { "sxtb",      0xe6af0070, 4,  ARM_EXT_V6,       do_sxth},
-  { "uxtah",     0xe6f00070, 5,  ARM_EXT_V6,       do_sxtah},
-  { "uxtab16",   0xe6c00070, 7,  ARM_EXT_V6,       do_sxtah},
-  { "uxtab",     0xe6e00070, 5,  ARM_EXT_V6,       do_sxtah},
-  { "uxth",      0xe6ff0070, 4,  ARM_EXT_V6,       do_sxth},
-  { "uxtb16",    0xe6cf0070, 6,  ARM_EXT_V6,       do_sxth},
-  { "uxtb",      0xe6ef0070, 4,  ARM_EXT_V6,       do_sxth},
-  { "sel",       0xe68000b0, 3,  ARM_EXT_V6,       do_qadd16},
-  { "setend",    0xf1010000, 0,  ARM_EXT_V6,       do_setend},
-  { "smlad",     0xe7000010, 5,  ARM_EXT_V6,       do_smlad},
-  { "smladx",    0xe7000030, 6,  ARM_EXT_V6,       do_smlad},
-  { "smlald",    0xe7400010, 6,  ARM_EXT_V6,       do_smlald},
-  { "smlaldx",   0xe7400030, 7,  ARM_EXT_V6,       do_smlald},
-  { "smlsd",     0xe7000050, 5,  ARM_EXT_V6,       do_smlad},
-  { "smlsdx",    0xe7000070, 6,  ARM_EXT_V6,       do_smlad},
-  { "smlsld",    0xe7400050, 6,  ARM_EXT_V6,       do_smlald},
-  { "smlsldx",   0xe7400070, 7,  ARM_EXT_V6,       do_smlald},
-  { "smmla",     0xe7500010, 5,  ARM_EXT_V6,       do_smlad},
-  { "smmlar",    0xe7500030, 6,  ARM_EXT_V6,       do_smlad},
-  { "smmls",     0xe75000d0, 5,  ARM_EXT_V6,       do_smlad},
-  { "smmlsr",    0xe75000f0, 6,  ARM_EXT_V6,       do_smlad},
-  { "smmul",     0xe750f010, 5,  ARM_EXT_V6,       do_smmul},
-  { "smmulr",    0xe750f030, 6,  ARM_EXT_V6,       do_smmul},
-  { "smuad",     0xe700f010, 5,  ARM_EXT_V6,       do_smmul},
-  { "smuadx",    0xe700f030, 6,  ARM_EXT_V6,       do_smmul},
-  { "smusd",     0xe700f050, 5,  ARM_EXT_V6,       do_smmul},
-  { "smusdx",    0xe700f070, 6,  ARM_EXT_V6,       do_smmul},
-  { "srsia",     0xf8cd0500, 0,  ARM_EXT_V6,       do_srs},
-  { "srsib",     0xf9cd0500, 0,  ARM_EXT_V6,       do_srs},
-  { "srsda",     0xf84d0500, 0,  ARM_EXT_V6,       do_srs},
-  { "srsdb",     0xf94d0500, 0,  ARM_EXT_V6,       do_srs},
-  { "ssat",      0xe6a00010, 4,  ARM_EXT_V6,       do_ssat},
-  { "ssat16",    0xe6a00f30, 6,  ARM_EXT_V6,       do_ssat16},
-  { "strex",     0xe1800f90, 5,  ARM_EXT_V6,       do_strex},
-  { "umaal",     0xe0400090, 5,  ARM_EXT_V6,       do_umaal},
-  { "usad8",     0xe780f010, 5,  ARM_EXT_V6,       do_smmul},
-  { "usada8",    0xe7800010, 6,  ARM_EXT_V6,       do_smlad},
-  { "usat",      0xe6e00010, 4,  ARM_EXT_V6,       do_usat},
-  { "usat16",    0xe6e00f30, 6,  ARM_EXT_V6,       do_usat16},
-
-  /* Core FPA instruction set (V1).  */
-  {"wfs",        0xee200110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
-  {"rfs",        0xee300110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
-  {"wfc",        0xee400110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
-  {"rfc",        0xee500110, 3,  FPU_FPA_EXT_V1,   do_fpa_ctrl},
-
-  {"ldfs",       0xec100100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"ldfd",       0xec108100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"ldfe",       0xec500100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"ldfp",       0xec508100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-
-  {"stfs",       0xec000100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"stfd",       0xec008100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"stfe",       0xec400100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-  {"stfp",       0xec408100, 3,  FPU_FPA_EXT_V1,   do_fpa_ldst},
-
-  {"mvfs",       0xee008100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfsp",      0xee008120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfsm",      0xee008140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfsz",      0xee008160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfd",       0xee008180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfdp",      0xee0081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfdm",      0xee0081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfdz",      0xee0081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfe",       0xee088100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfep",      0xee088120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfem",      0xee088140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mvfez",      0xee088160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"mnfs",       0xee108100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfsp",      0xee108120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfsm",      0xee108140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfsz",      0xee108160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfd",       0xee108180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfdp",      0xee1081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfdm",      0xee1081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfdz",      0xee1081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfe",       0xee188100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfep",      0xee188120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfem",      0xee188140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"mnfez",      0xee188160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"abss",       0xee208100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"abssp",      0xee208120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"abssm",      0xee208140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"abssz",      0xee208160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absd",       0xee208180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absdp",      0xee2081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absdm",      0xee2081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absdz",      0xee2081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"abse",       0xee288100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absep",      0xee288120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absem",      0xee288140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"absez",      0xee288160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"rnds",       0xee308100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndsp",      0xee308120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndsm",      0xee308140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndsz",      0xee308160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndd",       0xee308180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rnddp",      0xee3081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rnddm",      0xee3081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rnddz",      0xee3081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rnde",       0xee388100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndep",      0xee388120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndem",      0xee388140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"rndez",      0xee388160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"sqts",       0xee408100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtsp",      0xee408120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtsm",      0xee408140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtsz",      0xee408160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtd",       0xee408180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtdp",      0xee4081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtdm",      0xee4081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtdz",      0xee4081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqte",       0xee488100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtep",      0xee488120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtem",      0xee488140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sqtez",      0xee488160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"logs",       0xee508100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logsp",      0xee508120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logsm",      0xee508140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logsz",      0xee508160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logd",       0xee508180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logdp",      0xee5081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logdm",      0xee5081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logdz",      0xee5081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"loge",       0xee588100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logep",      0xee588120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logem",      0xee588140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"logez",      0xee588160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"lgns",       0xee608100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnsp",      0xee608120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnsm",      0xee608140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnsz",      0xee608160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnd",       0xee608180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgndp",      0xee6081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgndm",      0xee6081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgndz",      0xee6081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgne",       0xee688100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnep",      0xee688120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnem",      0xee688140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"lgnez",      0xee688160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"exps",       0xee708100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expsp",      0xee708120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expsm",      0xee708140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expsz",      0xee708160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expd",       0xee708180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expdp",      0xee7081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expdm",      0xee7081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expdz",      0xee7081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expe",       0xee788100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expep",      0xee788120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expem",      0xee788140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"expdz",      0xee788160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"sins",       0xee808100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinsp",      0xee808120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinsm",      0xee808140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinsz",      0xee808160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sind",       0xee808180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sindp",      0xee8081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sindm",      0xee8081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sindz",      0xee8081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sine",       0xee888100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinep",      0xee888120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinem",      0xee888140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"sinez",      0xee888160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"coss",       0xee908100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cossp",      0xee908120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cossm",      0xee908140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cossz",      0xee908160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosd",       0xee908180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosdp",      0xee9081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosdm",      0xee9081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosdz",      0xee9081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cose",       0xee988100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosep",      0xee988120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosem",      0xee988140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"cosez",      0xee988160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"tans",       0xeea08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tansp",      0xeea08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tansm",      0xeea08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tansz",      0xeea08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tand",       0xeea08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tandp",      0xeea081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tandm",      0xeea081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tandz",      0xeea081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tane",       0xeea88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tanep",      0xeea88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tanem",      0xeea88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"tanez",      0xeea88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"asns",       0xeeb08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnsp",      0xeeb08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnsm",      0xeeb08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnsz",      0xeeb08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnd",       0xeeb08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asndp",      0xeeb081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asndm",      0xeeb081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asndz",      0xeeb081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asne",       0xeeb88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnep",      0xeeb88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnem",      0xeeb88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"asnez",      0xeeb88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"acss",       0xeec08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acssp",      0xeec08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acssm",      0xeec08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acssz",      0xeec08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsd",       0xeec08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsdp",      0xeec081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsdm",      0xeec081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsdz",      0xeec081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acse",       0xeec88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsep",      0xeec88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsem",      0xeec88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"acsez",      0xeec88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"atns",       0xeed08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnsp",      0xeed08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnsm",      0xeed08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnsz",      0xeed08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnd",       0xeed08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atndp",      0xeed081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atndm",      0xeed081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atndz",      0xeed081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atne",       0xeed88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnep",      0xeed88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnem",      0xeed88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"atnez",      0xeed88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"urds",       0xeee08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdsp",      0xeee08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdsm",      0xeee08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdsz",      0xeee08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdd",       0xeee08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urddp",      0xeee081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urddm",      0xeee081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urddz",      0xeee081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urde",       0xeee88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdep",      0xeee88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdem",      0xeee88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"urdez",      0xeee88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"nrms",       0xeef08100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmsp",      0xeef08120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmsm",      0xeef08140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmsz",      0xeef08160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmd",       0xeef08180, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmdp",      0xeef081a0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmdm",      0xeef081c0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmdz",      0xeef081e0, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrme",       0xeef88100, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmep",      0xeef88120, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmem",      0xeef88140, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-  {"nrmez",      0xeef88160, 3,  FPU_FPA_EXT_V1,   do_fpa_monadic},
-
-  {"adfs",       0xee000100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfsp",      0xee000120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfsm",      0xee000140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfsz",      0xee000160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfd",       0xee000180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfdp",      0xee0001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfdm",      0xee0001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfdz",      0xee0001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfe",       0xee080100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfep",      0xee080120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfem",      0xee080140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"adfez",      0xee080160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"sufs",       0xee200100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufsp",      0xee200120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufsm",      0xee200140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufsz",      0xee200160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufd",       0xee200180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufdp",      0xee2001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufdm",      0xee2001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufdz",      0xee2001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufe",       0xee280100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufep",      0xee280120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufem",      0xee280140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"sufez",      0xee280160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"rsfs",       0xee300100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfsp",      0xee300120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfsm",      0xee300140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfsz",      0xee300160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfd",       0xee300180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfdp",      0xee3001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfdm",      0xee3001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfdz",      0xee3001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfe",       0xee380100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfep",      0xee380120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfem",      0xee380140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rsfez",      0xee380160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"mufs",       0xee100100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufsp",      0xee100120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufsm",      0xee100140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufsz",      0xee100160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufd",       0xee100180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufdp",      0xee1001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufdm",      0xee1001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufdz",      0xee1001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufe",       0xee180100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufep",      0xee180120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufem",      0xee180140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"mufez",      0xee180160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"dvfs",       0xee400100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfsp",      0xee400120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfsm",      0xee400140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfsz",      0xee400160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfd",       0xee400180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfdp",      0xee4001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfdm",      0xee4001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfdz",      0xee4001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfe",       0xee480100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfep",      0xee480120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfem",      0xee480140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"dvfez",      0xee480160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"rdfs",       0xee500100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfsp",      0xee500120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfsm",      0xee500140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfsz",      0xee500160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfd",       0xee500180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfdp",      0xee5001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfdm",      0xee5001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfdz",      0xee5001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfe",       0xee580100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfep",      0xee580120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfem",      0xee580140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rdfez",      0xee580160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"pows",       0xee600100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powsp",      0xee600120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powsm",      0xee600140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powsz",      0xee600160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powd",       0xee600180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powdp",      0xee6001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powdm",      0xee6001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powdz",      0xee6001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powe",       0xee680100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powep",      0xee680120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powem",      0xee680140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"powez",      0xee680160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"rpws",       0xee700100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwsp",      0xee700120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwsm",      0xee700140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwsz",      0xee700160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwd",       0xee700180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwdp",      0xee7001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwdm",      0xee7001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwdz",      0xee7001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwe",       0xee780100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwep",      0xee780120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwem",      0xee780140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rpwez",      0xee780160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"rmfs",       0xee800100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfsp",      0xee800120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfsm",      0xee800140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfsz",      0xee800160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfd",       0xee800180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfdp",      0xee8001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfdm",      0xee8001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfdz",      0xee8001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfe",       0xee880100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfep",      0xee880120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfem",      0xee880140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"rmfez",      0xee880160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"fmls",       0xee900100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlsp",      0xee900120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlsm",      0xee900140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlsz",      0xee900160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmld",       0xee900180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmldp",      0xee9001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmldm",      0xee9001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmldz",      0xee9001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmle",       0xee980100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlep",      0xee980120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlem",      0xee980140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fmlez",      0xee980160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"fdvs",       0xeea00100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvsp",      0xeea00120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvsm",      0xeea00140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvsz",      0xeea00160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvd",       0xeea00180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvdp",      0xeea001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvdm",      0xeea001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvdz",      0xeea001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdve",       0xeea80100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvep",      0xeea80120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvem",      0xeea80140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"fdvez",      0xeea80160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"frds",       0xeeb00100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdsp",      0xeeb00120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdsm",      0xeeb00140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdsz",      0xeeb00160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdd",       0xeeb00180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frddp",      0xeeb001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frddm",      0xeeb001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frddz",      0xeeb001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frde",       0xeeb80100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdep",      0xeeb80120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdem",      0xeeb80140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"frdez",      0xeeb80160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"pols",       0xeec00100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polsp",      0xeec00120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polsm",      0xeec00140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polsz",      0xeec00160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"pold",       0xeec00180, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"poldp",      0xeec001a0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"poldm",      0xeec001c0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"poldz",      0xeec001e0, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"pole",       0xeec80100, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polep",      0xeec80120, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polem",      0xeec80140, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-  {"polez",      0xeec80160, 3,  FPU_FPA_EXT_V1,   do_fpa_dyadic},
-
-  {"cmf",        0xee90f110, 3,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-  {"cmfe",       0xeed0f110, 3,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-  {"cnf",        0xeeb0f110, 3,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-  {"cnfe",       0xeef0f110, 3,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-  /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should
-     not be an optional suffix, but part of the instruction.  To be
-     compatible, we accept either.  */
-  {"cmfe",       0xeed0f110, 4,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-  {"cnfe",       0xeef0f110, 4,  FPU_FPA_EXT_V1,   do_fpa_cmp},
-
-  {"flts",       0xee000110, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltsp",      0xee000130, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltsm",      0xee000150, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltsz",      0xee000170, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltd",       0xee000190, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltdp",      0xee0001b0, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltdm",      0xee0001d0, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltdz",      0xee0001f0, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"flte",       0xee080110, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltep",      0xee080130, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltem",      0xee080150, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
-  {"fltez",      0xee080170, 3,  FPU_FPA_EXT_V1,   do_fpa_from_reg},
+  const char *template;
 
-  /* The implementation of the FIX instruction is broken on some
-     assemblers, in that it accepts a precision specifier as well as a
-     rounding specifier, despite the fact that this is meaningless.
-     To be more compatible, we accept it as well, though of course it
-     does not set any bits.  */
-  {"fix",        0xee100110, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixp",       0xee100130, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixm",       0xee100150, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixz",       0xee100170, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixsp",      0xee100130, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixsm",      0xee100150, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixsz",      0xee100170, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixdp",      0xee100130, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixdm",      0xee100150, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixdz",      0xee100170, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixep",      0xee100130, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixem",      0xee100150, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
-  {"fixez",      0xee100170, 3,  FPU_FPA_EXT_V1,   do_fpa_to_reg},
+  /* Parameters to instruction.	 */
+  unsigned char operands[8];
 
-  /* Instructions that were new with the real FPA, call them V2.  */
-  {"lfm",        0xec100200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-  {"lfmfd",      0xec900200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-  {"lfmea",      0xed100200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-  {"sfm",        0xec000200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-  {"sfmfd",      0xed000200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-  {"sfmea",      0xec800200, 3,  FPU_FPA_EXT_V2,   do_fpa_ldmstm},
-
-  /* VFP V1xD (single precision).  */
-  /* Moves and type conversions.  */
-  {"fcpys",   0xeeb00a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fmrs",    0xee100a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_sp},
-  {"fmsr",    0xee000a10, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_from_reg},
-  {"fmstat",  0xeef1fa10, 6, FPU_VFP_EXT_V1xD, do_empty},
-  {"fsitos",  0xeeb80ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fuitos",  0xeeb80a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"ftosis",  0xeebd0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"ftosizs", 0xeebd0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"ftouis",  0xeebc0a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"ftouizs", 0xeebc0ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fmrx",    0xeef00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_reg_from_ctrl},
-  {"fmxr",    0xeee00a10, 4, FPU_VFP_EXT_V1xD, do_vfp_ctrl_from_reg},
-
-  /* Memory operations.  */
-  {"flds",    0xed100a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
-  {"fsts",    0xed000a00, 4, FPU_VFP_EXT_V1xD, do_vfp_sp_ldst},
-  {"fldmias", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
-  {"fldmfds", 0xec900a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
-  {"fldmdbs", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
-  {"fldmeas", 0xed300a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
-  {"fldmiax", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
-  {"fldmfdx", 0xec900b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
-  {"fldmdbx", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
-  {"fldmeax", 0xed300b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
-  {"fstmias", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
-  {"fstmeas", 0xec800a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmia},
-  {"fstmdbs", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
-  {"fstmfds", 0xed200a00, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_ldstmdb},
-  {"fstmiax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
-  {"fstmeax", 0xec800b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmia},
-  {"fstmdbx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
-  {"fstmfdx", 0xed200b00, 7, FPU_VFP_EXT_V1xD, do_vfp_xp_ldstmdb},
+  /* Conditional tag - see opcode_lookup.  */
+  unsigned int tag : 4;
 
-  /* Monadic operations.  */
-  {"fabss",   0xeeb00ac0, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fnegs",   0xeeb10a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fsqrts",  0xeeb10ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-
-  /* Dyadic operations.  */
-  {"fadds",   0xee300a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fsubs",   0xee300a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fmuls",   0xee200a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fdivs",   0xee800a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fmacs",   0xee000a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fmscs",   0xee100a00, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fnmuls",  0xee200a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fnmacs",  0xee000a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
-  {"fnmscs",  0xee100a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_dyadic},
+  /* Basic instruction code.  */
+  unsigned int avalue : 28;
 
-  /* Comparisons.  */
-  {"fcmps",   0xeeb40a40, 5, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fcmpzs",  0xeeb50a40, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
-  {"fcmpes",  0xeeb40ac0, 6, FPU_VFP_EXT_V1xD, do_vfp_sp_monadic},
-  {"fcmpezs", 0xeeb50ac0, 7, FPU_VFP_EXT_V1xD, do_vfp_sp_compare_z},
+  /* Thumb-format instruction code.  */
+  unsigned int tvalue;
 
-  /* VFP V1 (Double precision).  */
-  /* Moves and type conversions.  */
-  {"fcpyd",   0xeeb00b40, 5, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-  {"fcvtds",  0xeeb70ac0, 6, FPU_VFP_EXT_V1,   do_vfp_dp_sp_cvt},
-  {"fcvtsd",  0xeeb70bc0, 6, FPU_VFP_EXT_V1,   do_vfp_sp_dp_cvt},
-  {"fmdhr",   0xee200b10, 5, FPU_VFP_EXT_V1,   do_vfp_dp_from_reg},
-  {"fmdlr",   0xee000b10, 5, FPU_VFP_EXT_V1,   do_vfp_dp_from_reg},
-  {"fmrdh",   0xee300b10, 5, FPU_VFP_EXT_V1,   do_vfp_reg_from_dp},
-  {"fmrdl",   0xee100b10, 5, FPU_VFP_EXT_V1,   do_vfp_reg_from_dp},
-  {"fsitod",  0xeeb80bc0, 6, FPU_VFP_EXT_V1,   do_vfp_dp_sp_cvt},
-  {"fuitod",  0xeeb80b40, 6, FPU_VFP_EXT_V1,   do_vfp_dp_sp_cvt},
-  {"ftosid",  0xeebd0b40, 6, FPU_VFP_EXT_V1,   do_vfp_sp_dp_cvt},
-  {"ftosizd", 0xeebd0bc0, 7, FPU_VFP_EXT_V1,   do_vfp_sp_dp_cvt},
-  {"ftouid",  0xeebc0b40, 6, FPU_VFP_EXT_V1,   do_vfp_sp_dp_cvt},
-  {"ftouizd", 0xeebc0bc0, 7, FPU_VFP_EXT_V1,   do_vfp_sp_dp_cvt},
-
-  /* Memory operations.  */
-  {"fldd",    0xed100b00, 4, FPU_VFP_EXT_V1,   do_vfp_dp_ldst},
-  {"fstd",    0xed000b00, 4, FPU_VFP_EXT_V1,   do_vfp_dp_ldst},
-  {"fldmiad", 0xec900b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmia},
-  {"fldmfdd", 0xec900b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmia},
-  {"fldmdbd", 0xed300b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmdb},
-  {"fldmead", 0xed300b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmdb},
-  {"fstmiad", 0xec800b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmia},
-  {"fstmead", 0xec800b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmia},
-  {"fstmdbd", 0xed200b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmdb},
-  {"fstmfdd", 0xed200b00, 7, FPU_VFP_EXT_V1,   do_vfp_dp_ldstmdb},
+  /* Which architecture variant provides this instruction.  */
+  const arm_feature_set *avariant;
+  const arm_feature_set *tvariant;
 
-  /* Monadic operations.  */
-  {"fabsd",   0xeeb00bc0, 5, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-  {"fnegd",   0xeeb10b40, 5, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-  {"fsqrtd",  0xeeb10bc0, 6, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-
-  /* Dyadic operations.  */
-  {"faddd",   0xee300b00, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fsubd",   0xee300b40, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fmuld",   0xee200b00, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fdivd",   0xee800b00, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fmacd",   0xee000b00, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fmscd",   0xee100b00, 5, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fnmuld",  0xee200b40, 6, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fnmacd",  0xee000b40, 6, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
-  {"fnmscd",  0xee100b40, 6, FPU_VFP_EXT_V1,   do_vfp_dp_dyadic},
+  /* Function to call to encode instruction in ARM format.  */
+  void (* aencode) (void);
 
-  /* Comparisons.  */
-  {"fcmpd",   0xeeb40b40, 5, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-  {"fcmpzd",  0xeeb50b40, 6, FPU_VFP_EXT_V1,   do_vfp_dp_compare_z},
-  {"fcmped",  0xeeb40bc0, 6, FPU_VFP_EXT_V1,   do_vfp_dp_monadic},
-  {"fcmpezd", 0xeeb50bc0, 7, FPU_VFP_EXT_V1,   do_vfp_dp_compare_z},
-
-  /* VFP V2.  */
-  {"fmsrr",   0xec400a10, 5, FPU_VFP_EXT_V2,   do_vfp_sp2_from_reg2},
-  {"fmrrs",   0xec500a10, 5, FPU_VFP_EXT_V2,   do_vfp_reg2_from_sp2},
-  {"fmdrr",   0xec400b10, 5, FPU_VFP_EXT_V2,   do_vfp_dp_from_reg2},
-  {"fmrrd",   0xec500b10, 5, FPU_VFP_EXT_V2,   do_vfp_reg2_from_dp},
-
-  /* Intel XScale extensions to ARM V5 ISA.  (All use CP0).  */
-  {"mia",        0xee200010, 3,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"miaph",      0xee280010, 5,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"miabb",      0xee2c0010, 5,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"miabt",      0xee2d0010, 5,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"miatb",      0xee2e0010, 5,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"miatt",      0xee2f0010, 5,  ARM_CEXT_XSCALE,   do_xsc_mia},
-  {"mar",        0xec400000, 3,  ARM_CEXT_XSCALE,   do_xsc_mar},
-  {"mra",        0xec500000, 3,  ARM_CEXT_XSCALE,   do_xsc_mra},
-
-  /* Intel Wireless MMX technology instructions.  */
-  {"tandcb",     0xee130130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
-  {"tandch",     0xee530130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
-  {"tandcw",     0xee930130, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tandc},
-  {"tbcstb",     0xee400010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
-  {"tbcsth",     0xee400050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
-  {"tbcstw",     0xee400090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tbcst},
-  {"textrcb",    0xee130170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
-  {"textrch",    0xee530170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
-  {"textrcw",    0xee930170, 7, ARM_CEXT_IWMMXT, do_iwmmxt_textrc},
-  {"textrmub",   0xee100070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"textrmuh",   0xee500070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"textrmuw",   0xee900070, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"textrmsb",   0xee100078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"textrmsh",   0xee500078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"textrmsw",   0xee900078, 8, ARM_CEXT_IWMMXT, do_iwmmxt_textrm},
-  {"tinsrb",     0xee600010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
-  {"tinsrh",     0xee600050, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
-  {"tinsrw",     0xee600090, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tinsr},
-  {"tmcr",       0xee000110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmcr},
-  {"tmcrr",      0xec400000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmcrr},
-  {"tmia",       0xee200010, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmiaph",     0xee280010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmiabb",     0xee2c0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmiabt",     0xee2d0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmiatb",     0xee2e0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmiatt",     0xee2f0010, 6, ARM_CEXT_IWMMXT, do_iwmmxt_tmia},
-  {"tmovmskb",   0xee100030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
-  {"tmovmskh",   0xee500030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
-  {"tmovmskw",   0xee900030, 8, ARM_CEXT_IWMMXT, do_iwmmxt_tmovmsk},
-  {"tmrc",       0xee100110, 4, ARM_CEXT_IWMMXT, do_iwmmxt_tmrc},
-  {"tmrrc",      0xec500000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_tmrrc},
-  {"torcb",      0xee130150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
-  {"torch",      0xee530150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
-  {"torcw",      0xee930150, 5, ARM_CEXT_IWMMXT, do_iwmmxt_torc},
-  {"waccb",      0xee0001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wacch",      0xee4001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"waccw",      0xee8001c0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"waddbss",    0xee300180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddb",      0xee000180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddbus",    0xee100180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddhss",    0xee700180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddh",      0xee400180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddhus",    0xee500180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddwss",    0xeeb00180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddw",      0xee800180, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waddwus",    0xee900180, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"waligni",    0xee000020, 7, ARM_CEXT_IWMMXT, do_iwmmxt_waligni},
-  {"walignr0",   0xee800020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"walignr1",   0xee900020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"walignr2",   0xeea00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"walignr3",   0xeeb00020, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wand",       0xee200000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wandn",      0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wavg2b",     0xee800000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wavg2br",    0xee900000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wavg2h",     0xeec00000, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wavg2hr",    0xeed00000, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpeqb",    0xee000060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpeqh",    0xee400060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpeqw",    0xee800060, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtub",   0xee100060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtuh",   0xee500060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtuw",   0xee900060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtsb",   0xee300060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtsh",   0xee700060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wcmpgtsw",   0xeeb00060, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wldrb",      0xec100000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
-  {"wldrh",      0xec100100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
-  {"wldrw",      0xec100200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
-  {"wldrd",      0xec100300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
-  {"wmacs",      0xee600100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmacsz",     0xee700100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmacu",      0xee400100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmacuz",     0xee500100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmadds",     0xeea00100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaddu",     0xee800100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxsb",     0xee200160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxsh",     0xee600160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxsw",     0xeea00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxub",     0xee000160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxuh",     0xee400160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmaxuw",     0xee800160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminsb",     0xee300160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminsh",     0xee700160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminsw",     0xeeb00160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminub",     0xee100160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminuh",     0xee500160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wminuw",     0xee900160, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmov",       0xee000000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wmov},
-  {"wmulsm",     0xee300100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmulsl",     0xee200100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmulum",     0xee100100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wmulul",     0xee000100, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wor",        0xee000000, 3, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackhss",   0xee700080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackhus",   0xee500080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackwss",   0xeeb00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackwus",   0xee900080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackdss",   0xeef00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wpackdus",   0xeed00080, 8, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wrorh",      0xee700040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wrorhg",     0xee700148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wrorw",      0xeeb00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wrorwg",     0xeeb00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wrord",      0xeef00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wrordg",     0xeef00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsadb",      0xee000120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsadbz",     0xee100120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsadh",      0xee400120, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsadhz",     0xee500120, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wshufh",     0xee0001e0, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wshufh},
-  {"wsllh",      0xee500040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsllhg",     0xee500148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsllw",      0xee900040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsllwg",     0xee900148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wslld",      0xeed00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wslldg",     0xeed00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsrah",      0xee400040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsrahg",     0xee400148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsraw",      0xee800040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsrawg",     0xee800148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsrad",      0xeec00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsradg",     0xeec00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsrlh",      0xee600040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsrlhg",     0xee600148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsrlw",      0xeea00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsrlwg",     0xeea00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wsrld",      0xeee00040, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsrldg",     0xeee00148, 6, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwcg},
-  {"wstrb",      0xec000000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
-  {"wstrh",      0xec000100, 5, ARM_CEXT_IWMMXT, do_iwmmxt_byte_addr},
-  {"wstrw",      0xec000200, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
-  {"wstrd",      0xec000300, 5, ARM_CEXT_IWMMXT, do_iwmmxt_word_addr},
-  {"wsubbss",    0xee3001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubb",      0xee0001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubbus",    0xee1001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubhss",    0xee7001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubh",      0xee4001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubhus",    0xee5001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubwss",    0xeeb001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubw",      0xee8001a0, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wsubwus",    0xee9001a0, 7, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckehub", 0xee0000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckehuh", 0xee4000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckehuw", 0xee8000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckehsb", 0xee2000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckehsh", 0xee6000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckehsw", 0xeea000c0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckihb",  0xee1000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckihh",  0xee5000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckihw",  0xee9000c0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckelub", 0xee0000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckeluh", 0xee4000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckeluw", 0xee8000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckelsb", 0xee2000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckelsh", 0xee6000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckelsw", 0xeea000e0, 10, ARM_CEXT_IWMMXT, do_iwmmxt_wrwr},
-  {"wunpckilb",  0xee1000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckilh",  0xee5000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wunpckilw",  0xee9000e0, 9, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wxor",       0xee100000, 4, ARM_CEXT_IWMMXT, do_iwmmxt_wrwrwr},
-  {"wzero",      0xee300000, 5, ARM_CEXT_IWMMXT, do_iwmmxt_wzero},
-
-  /* Cirrus Maverick instructions.  */
-  {"cfldrs",     0xec100400, 6,  ARM_CEXT_MAVERICK, do_mav_ldst_1},
-  {"cfldrd",     0xec500400, 6,  ARM_CEXT_MAVERICK, do_mav_ldst_2},
-  {"cfldr32",    0xec100500, 7,  ARM_CEXT_MAVERICK, do_mav_ldst_3},
-  {"cfldr64",    0xec500500, 7,  ARM_CEXT_MAVERICK, do_mav_ldst_4},
-  {"cfstrs",     0xec000400, 6,  ARM_CEXT_MAVERICK, do_mav_ldst_1},
-  {"cfstrd",     0xec400400, 6,  ARM_CEXT_MAVERICK, do_mav_ldst_2},
-  {"cfstr32",    0xec000500, 7,  ARM_CEXT_MAVERICK, do_mav_ldst_3},
-  {"cfstr64",    0xec400500, 7,  ARM_CEXT_MAVERICK, do_mav_ldst_4},
-  {"cfmvsr",     0xee000450, 6,  ARM_CEXT_MAVERICK, do_mav_binops_2a},
-  {"cfmvrs",     0xee100450, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1a},
-  {"cfmvdlr",    0xee000410, 7,  ARM_CEXT_MAVERICK, do_mav_binops_2b},
-  {"cfmvrdl",    0xee100410, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1b},
-  {"cfmvdhr",    0xee000430, 7,  ARM_CEXT_MAVERICK, do_mav_binops_2b},
-  {"cfmvrdh",    0xee100430, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1b},
-  {"cfmv64lr",   0xee000510, 8,  ARM_CEXT_MAVERICK, do_mav_binops_2c},
-  {"cfmvr64l",   0xee100510, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1c},
-  {"cfmv64hr",   0xee000530, 8,  ARM_CEXT_MAVERICK, do_mav_binops_2c},
-  {"cfmvr64h",   0xee100530, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1c},
-  {"cfmval32",   0xee200440, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3a},
-  {"cfmv32al",   0xee100440, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3b},
-  {"cfmvam32",   0xee200460, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3a},
-  {"cfmv32am",   0xee100460, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3b},
-  {"cfmvah32",   0xee200480, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3a},
-  {"cfmv32ah",   0xee100480, 8,  ARM_CEXT_MAVERICK, do_mav_binops_3b},
-  {"cfmva32",    0xee2004a0, 7,  ARM_CEXT_MAVERICK, do_mav_binops_3a},
-  {"cfmv32a",    0xee1004a0, 7,  ARM_CEXT_MAVERICK, do_mav_binops_3b},
-  {"cfmva64",    0xee2004c0, 7,  ARM_CEXT_MAVERICK, do_mav_binops_3c},
-  {"cfmv64a",    0xee1004c0, 7,  ARM_CEXT_MAVERICK, do_mav_binops_3d},
-  {"cfmvsc32",   0xee2004e0, 8,  ARM_CEXT_MAVERICK, do_mav_dspsc_1},
-  {"cfmv32sc",   0xee1004e0, 8,  ARM_CEXT_MAVERICK, do_mav_dspsc_2},
-  {"cfcpys",     0xee000400, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1d},
-  {"cfcpyd",     0xee000420, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1e},
-  {"cfcvtsd",    0xee000460, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1f},
-  {"cfcvtds",    0xee000440, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1g},
-  {"cfcvt32s",   0xee000480, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1h},
-  {"cfcvt32d",   0xee0004a0, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1i},
-  {"cfcvt64s",   0xee0004c0, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1j},
-  {"cfcvt64d",   0xee0004e0, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1k},
-  {"cfcvts32",   0xee100580, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1l},
-  {"cfcvtd32",   0xee1005a0, 8,  ARM_CEXT_MAVERICK, do_mav_binops_1m},
-  {"cftruncs32", 0xee1005c0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1l},
-  {"cftruncd32", 0xee1005e0, 10, ARM_CEXT_MAVERICK, do_mav_binops_1m},
-  {"cfrshl32",   0xee000550, 8,  ARM_CEXT_MAVERICK, do_mav_triple_4a},
-  {"cfrshl64",   0xee000570, 8,  ARM_CEXT_MAVERICK, do_mav_triple_4b},
-  {"cfsh32",     0xee000500, 6,  ARM_CEXT_MAVERICK, do_mav_shift_1},
-  {"cfsh64",     0xee200500, 6,  ARM_CEXT_MAVERICK, do_mav_shift_2},
-  {"cfcmps",     0xee100490, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5a},
-  {"cfcmpd",     0xee1004b0, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5b},
-  {"cfcmp32",    0xee100590, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5c},
-  {"cfcmp64",    0xee1005b0, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5d},
-  {"cfabss",     0xee300400, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1d},
-  {"cfabsd",     0xee300420, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1e},
-  {"cfnegs",     0xee300440, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1d},
-  {"cfnegd",     0xee300460, 6,  ARM_CEXT_MAVERICK, do_mav_binops_1e},
-  {"cfadds",     0xee300480, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5e},
-  {"cfaddd",     0xee3004a0, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5f},
-  {"cfsubs",     0xee3004c0, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5e},
-  {"cfsubd",     0xee3004e0, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5f},
-  {"cfmuls",     0xee100400, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5e},
-  {"cfmuld",     0xee100420, 6,  ARM_CEXT_MAVERICK, do_mav_triple_5f},
-  {"cfabs32",    0xee300500, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1n},
-  {"cfabs64",    0xee300520, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1o},
-  {"cfneg32",    0xee300540, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1n},
-  {"cfneg64",    0xee300560, 7,  ARM_CEXT_MAVERICK, do_mav_binops_1o},
-  {"cfadd32",    0xee300580, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5g},
-  {"cfadd64",    0xee3005a0, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5h},
-  {"cfsub32",    0xee3005c0, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5g},
-  {"cfsub64",    0xee3005e0, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5h},
-  {"cfmul32",    0xee100500, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5g},
-  {"cfmul64",    0xee100520, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5h},
-  {"cfmac32",    0xee100540, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5g},
-  {"cfmsc32",    0xee100560, 7,  ARM_CEXT_MAVERICK, do_mav_triple_5g},
-  {"cfmadd32",   0xee000600, 8,  ARM_CEXT_MAVERICK, do_mav_quad_6a},
-  {"cfmsub32",   0xee100600, 8,  ARM_CEXT_MAVERICK, do_mav_quad_6a},
-  {"cfmadda32",  0xee200600, 9,  ARM_CEXT_MAVERICK, do_mav_quad_6b},
-  {"cfmsuba32",  0xee300600, 9,  ARM_CEXT_MAVERICK, do_mav_quad_6b},
+  /* Function to call to encode instruction in Thumb format.  */
+  void (* tencode) (void);
 };
 
 /* Defines for various bits that we will want to toggle.  */
 #define INST_IMMEDIATE	0x02000000
 #define OFFSET_REG	0x02000000
-#define HWOFFSET_IMM    0x00400000
+#define HWOFFSET_IMM	0x00400000
 #define SHIFT_BY_REG	0x00000010
 #define PRE_INDEX	0x01000000
 #define INDEX_UP	0x00800000
@@ -2253,6 +472,9 @@ static const struct asm_opcode insns[] =
 
 #define DATA_OP_SHIFT	21
 
+#define T2_OPCODE_MASK	0xfe1fffff
+#define T2_DATA_OP_SHIFT 21
+
 /* Codes to distinguish the arithmetic instructions.  */
 #define OPCODE_AND	0
 #define OPCODE_EOR	1
@@ -2271,40 +493,16 @@ static const struct asm_opcode insns[] =
 #define OPCODE_BIC	14
 #define OPCODE_MVN	15
 
-/* Thumb v1 (ARMv4T).  */
-static void do_t_nop		PARAMS ((char *));
-static void do_t_arit		PARAMS ((char *));
-static void do_t_add		PARAMS ((char *));
-static void do_t_asr		PARAMS ((char *));
-static void do_t_branch9	PARAMS ((char *));
-static void do_t_branch12	PARAMS ((char *));
-static void do_t_branch23	PARAMS ((char *));
-static void do_t_bx		PARAMS ((char *));
-static void do_t_compare	PARAMS ((char *));
-static void do_t_ldmstm		PARAMS ((char *));
-static void do_t_ldr		PARAMS ((char *));
-static void do_t_ldrb		PARAMS ((char *));
-static void do_t_ldrh		PARAMS ((char *));
-static void do_t_lds		PARAMS ((char *));
-static void do_t_lsl		PARAMS ((char *));
-static void do_t_lsr		PARAMS ((char *));
-static void do_t_mov		PARAMS ((char *));
-static void do_t_push_pop	PARAMS ((char *));
-static void do_t_str		PARAMS ((char *));
-static void do_t_strb		PARAMS ((char *));
-static void do_t_strh		PARAMS ((char *));
-static void do_t_sub		PARAMS ((char *));
-static void do_t_swi		PARAMS ((char *));
-static void do_t_adr		PARAMS ((char *));
-
-/* Thumb v2 (ARMv5T).  */
-static void do_t_blx		PARAMS ((char *));
-static void do_t_bkpt		PARAMS ((char *));
-
-/* ARM V6.  */
-static void do_t_cps            PARAMS ((char *));
-static void do_t_cpy            PARAMS ((char *));
-static void do_t_setend         PARAMS ((char *));;
+#define T2_OPCODE_AND	0
+#define T2_OPCODE_BIC	1
+#define T2_OPCODE_ORR	2
+#define T2_OPCODE_ORN	3
+#define T2_OPCODE_EOR	4
+#define T2_OPCODE_ADD	8
+#define T2_OPCODE_ADC	10
+#define T2_OPCODE_SBC	11
+#define T2_OPCODE_SUB	13
+#define T2_OPCODE_RSB	14
 
 #define T_OPCODE_MUL 0x4340
 #define T_OPCODE_TST 0x4200
@@ -2326,7 +524,8 @@ static void do_t_setend         PARAMS ((char *));;
 
 #define T_OPCODE_ASR_R	0x4100
 #define T_OPCODE_LSL_R	0x4080
-#define T_OPCODE_LSR_R  0x40c0
+#define T_OPCODE_LSR_R	0x40c0
+#define T_OPCODE_ROR_R	0x41c0
 #define T_OPCODE_ASR_I	0x1000
 #define T_OPCODE_LSL_I	0x0000
 #define T_OPCODE_LSR_I	0x0800
@@ -2356,546 +555,865 @@ static void do_t_setend         PARAMS ((char *));;
 #define T_OPCODE_PUSH	0xb400
 #define T_OPCODE_POP	0xbc00
 
-#define T_OPCODE_BRANCH 0xe7fe
-
-static int thumb_reg		PARAMS ((char ** str, int hi_lo));
+#define T_OPCODE_BRANCH 0xe000
 
 #define THUMB_SIZE	2	/* Size of thumb instruction.  */
-#define THUMB_REG_LO	0x1
-#define THUMB_REG_HI	0x2
-#define THUMB_REG_ANY	0x3
+#define THUMB_PP_PC_LR 0x0100
+#define THUMB_LOAD_BIT 0x0800
+#define THUMB2_LOAD_BIT 0x00100000
+
+#define BAD_ARGS	_("bad arguments to instruction")
+#define BAD_PC		_("r15 not allowed here")
+#define BAD_COND	_("instruction cannot be conditional")
+#define BAD_OVERLAP	_("registers may not be the same")
+#define BAD_HIREG	_("lo register required")
+#define BAD_THUMB32	_("instruction not supported in Thumb16 mode")
+#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode");
+#define BAD_BRANCH	_("branch must be last instruction in IT block")
+#define BAD_NOT_IT	_("instruction not allowed in IT block")
+
+static struct hash_control *arm_ops_hsh;
+static struct hash_control *arm_cond_hsh;
+static struct hash_control *arm_shift_hsh;
+static struct hash_control *arm_psr_hsh;
+static struct hash_control *arm_v7m_psr_hsh;
+static struct hash_control *arm_reg_hsh;
+static struct hash_control *arm_reloc_hsh;
+static struct hash_control *arm_barrier_opt_hsh;
 
-#define THUMB_H1	0x0080
-#define THUMB_H2	0x0040
+/* Stuff needed to resolve the label ambiguity
+   As:
+     ...
+     label:   <insn>
+   may differ from:
+     ...
+     label:
+	      <insn>
+*/
 
-#define THUMB_ASR 0
-#define THUMB_LSL 1
-#define THUMB_LSR 2
+symbolS *  last_label_seen;
+static int label_is_thumb_function_name = FALSE;
+
+/* Literal pool structure.  Held on a per-section
+   and per-sub-section basis.  */
 
-#define THUMB_MOVE 0
-#define THUMB_COMPARE 1
-#define THUMB_CPY 2
+#define MAX_LITERAL_POOL_SIZE 1024
+typedef struct literal_pool
+{
+  expressionS	 literals [MAX_LITERAL_POOL_SIZE];
+  unsigned int	 next_free_entry;
+  unsigned int	 id;
+  symbolS *	 symbol;
+  segT		 section;
+  subsegT	 sub_section;
+  struct literal_pool * next;
+} literal_pool;
 
-#define THUMB_LOAD 0
-#define THUMB_STORE 1
+/* Pointer to a linked list of literal pools.  */
+literal_pool * list_of_pools = NULL;
 
-#define THUMB_PP_PC_LR 0x0100
+/* State variables for IT block handling.  */
+static bfd_boolean current_it_mask = 0;
+static int current_cc;
 
-/* These three are used for immediate shifts, do not alter.  */
-#define THUMB_WORD 2
-#define THUMB_HALFWORD 1
-#define THUMB_BYTE 0
+
+/* Pure syntax.	 */
 
-struct thumb_opcode
-{
-  /* Basic string to match.  */
-  const char * template;
+/* This array holds the chars that always start a comment.  If the
+   pre-processor is disabled, these aren't very useful.	 */
+const char comment_chars[] = "@";
 
-  /* Basic instruction code.  */
-  unsigned long value;
+/* This array holds the chars that only start a comment at the beginning of
+   a line.  If the line seems to have the form '# 123 filename'
+   .line and .file directives will appear in the pre-processed output.	*/
+/* Note that input_file.c hand checks for '#' at the beginning of the
+   first line of the input file.  This is because the compiler outputs
+   #NO_APP at the beginning of its output.  */
+/* Also note that comments like this one will always work.  */
+const char line_comment_chars[] = "#";
 
-  int size;
+const char line_separator_chars[] = ";";
 
-  /* Which CPU variants this exists for.  */
-  unsigned long variant;
+/* Chars that can be used to separate mant
+   from exp in floating point numbers.	*/
+const char EXP_CHARS[] = "eE";
 
-  /* Function to call to parse args.  */
-  void (* parms) PARAMS ((char *));
-};
+/* Chars that mean this number is a floating point constant.  */
+/* As in 0f12.456  */
+/* or	 0d1.2345e12  */
 
-static const struct thumb_opcode tinsns[] =
-{
-  /* Thumb v1 (ARMv4T).  */
-  {"adc",	0x4140,		2,	ARM_EXT_V4T, do_t_arit},
-  {"add",	0x0000,		2,	ARM_EXT_V4T, do_t_add},
-  {"and",	0x4000,		2,	ARM_EXT_V4T, do_t_arit},
-  {"asr",	0x0000,		2,	ARM_EXT_V4T, do_t_asr},
-  {"b",		T_OPCODE_BRANCH, 2,	ARM_EXT_V4T, do_t_branch12},
-  {"beq",	0xd0fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bne",	0xd1fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bcs",	0xd2fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bhs",	0xd2fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bcc",	0xd3fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bul",	0xd3fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"blo",	0xd3fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bmi",	0xd4fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bpl",	0xd5fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bvs",	0xd6fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bvc",	0xd7fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bhi",	0xd8fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bls",	0xd9fe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bge",	0xdafe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"blt",	0xdbfe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bgt",	0xdcfe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"ble",	0xddfe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bal",	0xdefe,		2,	ARM_EXT_V4T, do_t_branch9},
-  {"bic",	0x4380,		2,	ARM_EXT_V4T, do_t_arit},
-  {"bl",	0xf7fffffe,	4,	ARM_EXT_V4T, do_t_branch23},
-  {"bx",	0x4700,		2,	ARM_EXT_V4T, do_t_bx},
-  {"cmn",	T_OPCODE_CMN,	2,	ARM_EXT_V4T, do_t_arit},
-  {"cmp",	0x0000,		2,	ARM_EXT_V4T, do_t_compare},
-  {"eor",	0x4040,		2,	ARM_EXT_V4T, do_t_arit},
-  {"ldmia",	0xc800,		2,	ARM_EXT_V4T, do_t_ldmstm},
-  {"ldr",	0x0000,		2,	ARM_EXT_V4T, do_t_ldr},
-  {"ldrb",	0x0000,		2,	ARM_EXT_V4T, do_t_ldrb},
-  {"ldrh",	0x0000,		2,	ARM_EXT_V4T, do_t_ldrh},
-  {"ldrsb",	0x5600,		2,	ARM_EXT_V4T, do_t_lds},
-  {"ldrsh",	0x5e00,		2,	ARM_EXT_V4T, do_t_lds},
-  {"ldsb",	0x5600,		2,	ARM_EXT_V4T, do_t_lds},
-  {"ldsh",	0x5e00,		2,	ARM_EXT_V4T, do_t_lds},
-  {"lsl",	0x0000,		2,	ARM_EXT_V4T, do_t_lsl},
-  {"lsr",	0x0000,		2,	ARM_EXT_V4T, do_t_lsr},
-  {"mov",	0x0000,		2,	ARM_EXT_V4T, do_t_mov},
-  {"mul",	T_OPCODE_MUL,	2,	ARM_EXT_V4T, do_t_arit},
-  {"mvn",	T_OPCODE_MVN,	2,	ARM_EXT_V4T, do_t_arit},
-  {"neg",	T_OPCODE_NEG,	2,	ARM_EXT_V4T, do_t_arit},
-  {"orr",	0x4300,		2,	ARM_EXT_V4T, do_t_arit},
-  {"pop",	0xbc00,		2,	ARM_EXT_V4T, do_t_push_pop},
-  {"push",	0xb400,		2,	ARM_EXT_V4T, do_t_push_pop},
-  {"ror",	0x41c0,		2,	ARM_EXT_V4T, do_t_arit},
-  {"sbc",	0x4180,		2,	ARM_EXT_V4T, do_t_arit},
-  {"stmia",	0xc000,		2,	ARM_EXT_V4T, do_t_ldmstm},
-  {"str",	0x0000,		2,	ARM_EXT_V4T, do_t_str},
-  {"strb",	0x0000,		2,	ARM_EXT_V4T, do_t_strb},
-  {"strh",	0x0000,		2,	ARM_EXT_V4T, do_t_strh},
-  {"swi",	0xdf00,		2,	ARM_EXT_V4T, do_t_swi},
-  {"sub",	0x0000,		2,	ARM_EXT_V4T, do_t_sub},
-  {"tst",	T_OPCODE_TST,	2,	ARM_EXT_V4T, do_t_arit},
-  /* Pseudo ops:  */
-  {"adr",       0x0000,         2,      ARM_EXT_V4T, do_t_adr},
-  {"nop",       0x46C0,         2,      ARM_EXT_V4T, do_t_nop},      /* mov r8,r8  */
-  /* Thumb v2 (ARMv5T).  */
-  {"blx",	0,		0,	ARM_EXT_V5T, do_t_blx},
-  {"bkpt",	0xbe00,		2,	ARM_EXT_V5T, do_t_bkpt},
-
-  /* ARM V6.  */
-  {"cpsie",	0xb660,		2,	ARM_EXT_V6,  do_t_cps},
-  {"cpsid",     0xb670,		2,	ARM_EXT_V6,  do_t_cps},
-  {"cpy",	0x4600,		2,	ARM_EXT_V6,  do_t_cpy},
-  {"rev",	0xba00,		2,	ARM_EXT_V6,  do_t_arit},
-  {"rev16",	0xba40,		2,	ARM_EXT_V6,  do_t_arit},
-  {"revsh",	0xbac0,		2,	ARM_EXT_V6,  do_t_arit},
-  {"setend",	0xb650,		2,	ARM_EXT_V6,  do_t_setend},
-  {"sxth",	0xb200,		2,	ARM_EXT_V6,  do_t_arit},
-  {"sxtb",	0xb240,		2,	ARM_EXT_V6,  do_t_arit},
-  {"uxth",	0xb280,		2,	ARM_EXT_V6,  do_t_arit},
-  {"uxtb",	0xb2c0,		2,	ARM_EXT_V6,  do_t_arit},
-};
+const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
 
-#define BAD_ARGS 	_("bad arguments to instruction")
-#define BAD_PC 		_("r15 not allowed here")
-#define BAD_COND 	_("instruction is not conditional")
-#define ERR_NO_ACCUM	_("acc0 expected")
+/* Prefix characters that indicate the start of an immediate
+   value.  */
+#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
 
-static struct hash_control * arm_ops_hsh   = NULL;
-static struct hash_control * arm_tops_hsh  = NULL;
-static struct hash_control * arm_cond_hsh  = NULL;
-static struct hash_control * arm_shift_hsh = NULL;
-static struct hash_control * arm_psr_hsh   = NULL;
+/* Separator character handling.  */
 
-/* This table describes all the machine specific pseudo-ops the assembler
-   has to support.  The fields are:
-     pseudo-op name without dot
-     function to call to execute this pseudo-op
-     Integer arg to pass to the function.  */
+#define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
 
-static void s_req PARAMS ((int));
-static void s_unreq PARAMS ((int));
-static void s_align PARAMS ((int));
-static void s_bss PARAMS ((int));
-static void s_even PARAMS ((int));
-static void s_ltorg PARAMS ((int));
-static void s_arm PARAMS ((int));
-static void s_thumb PARAMS ((int));
-static void s_code PARAMS ((int));
-static void s_force_thumb PARAMS ((int));
-static void s_thumb_func PARAMS ((int));
-static void s_thumb_set PARAMS ((int));
-#ifdef OBJ_ELF
-static void s_arm_elf_cons PARAMS ((int));
-#endif
+static inline int
+skip_past_char (char ** str, char c)
+{
+  if (**str == c)
+    {
+      (*str)++;
+      return SUCCESS;
+    }
+  else
+    return FAIL;
+}
+#define skip_past_comma(str) skip_past_char (str, ',')
 
-static int my_get_expression PARAMS ((expressionS *, char **));
+/* Arithmetic expressions (possibly involving symbols).	 */
 
-const pseudo_typeS md_pseudo_table[] =
+/* Return TRUE if anything in the expression is a bignum.  */
+
+static int
+walk_no_bignums (symbolS * sp)
 {
-  /* Never called because '.req' does not start a line.  */
-  { "req",         s_req,         0 },
-  { "unreq",       s_unreq,       0 },
-  { "bss",         s_bss,         0 },
-  { "align",       s_align,       0 },
-  { "arm",         s_arm,         0 },
-  { "thumb",       s_thumb,       0 },
-  { "code",        s_code,        0 },
-  { "force_thumb", s_force_thumb, 0 },
-  { "thumb_func",  s_thumb_func,  0 },
-  { "thumb_set",   s_thumb_set,   0 },
-  { "even",        s_even,        0 },
-  { "ltorg",       s_ltorg,       0 },
-  { "pool",        s_ltorg,       0 },
-#ifdef OBJ_ELF
-  { "word",        s_arm_elf_cons, 4 },
-  { "long",        s_arm_elf_cons, 4 },
-#else
-  { "word",        cons, 4},
-#endif
-  { "extend",      float_cons, 'x' },
-  { "ldouble",     float_cons, 'x' },
-  { "packed",      float_cons, 'p' },
-  { 0, 0, 0 }
-};
+  if (symbol_get_value_expression (sp)->X_op == O_big)
+    return 1;
 
-/* Other internal functions.  */
-static int arm_parse_extension PARAMS ((char *, int *));
-static int arm_parse_cpu PARAMS ((char *));
-static int arm_parse_arch PARAMS ((char *));
-static int arm_parse_fpu PARAMS ((char *));
-static int arm_parse_float_abi PARAMS ((char *));
-#if 0 /* Suppressed - for now.  */
-#if defined OBJ_COFF || defined OBJ_ELF
-static void arm_add_note PARAMS ((const char *, const char *, unsigned int));
-#endif
+  if (symbol_get_value_expression (sp)->X_add_symbol)
+    {
+      return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
+	      || (symbol_get_value_expression (sp)->X_op_symbol
+		  && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
+    }
+
+  return 0;
+}
+
+static int in_my_get_expression = 0;
+
+/* Third argument to my_get_expression.	 */
+#define GE_NO_PREFIX 0
+#define GE_IMM_PREFIX 1
+#define GE_OPT_PREFIX 2
+
+static int
+my_get_expression (expressionS * ep, char ** str, int prefix_mode)
+{
+  char * save_in;
+  segT	 seg;
+
+  /* In unified syntax, all prefixes are optional.  */
+  if (unified_syntax)
+    prefix_mode = GE_OPT_PREFIX;
+
+  switch (prefix_mode)
+    {
+    case GE_NO_PREFIX: break;
+    case GE_IMM_PREFIX:
+      if (!is_immediate_prefix (**str))
+	{
+	  inst.error = _("immediate expression requires a # prefix");
+	  return FAIL;
+	}
+      (*str)++;
+      break;
+    case GE_OPT_PREFIX:
+      if (is_immediate_prefix (**str))
+	(*str)++;
+      break;
+    default: abort ();
+    }
+
+  memset (ep, 0, sizeof (expressionS));
+
+  save_in = input_line_pointer;
+  input_line_pointer = *str;
+  in_my_get_expression = 1;
+  seg = expression (ep);
+  in_my_get_expression = 0;
+
+  if (ep->X_op == O_illegal)
+    {
+      /* We found a bad expression in md_operand().  */
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      if (inst.error == NULL)
+	inst.error = _("bad expression");
+      return 1;
+    }
+
+#ifdef OBJ_AOUT
+  if (seg != absolute_section
+      && seg != text_section
+      && seg != data_section
+      && seg != bss_section
+      && seg != undefined_section)
+    {
+      inst.error = _("bad segment");
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return 1;
+    }
 #endif
 
-/* Stuff needed to resolve the label ambiguity
-   As:
-     ...
-     label:   <insn>
-   may differ from:
-     ...
-     label:
-              <insn>
-*/
+  /* Get rid of any bignums now, so that we don't generate an error for which
+     we can't establish a line number later on.	 Big numbers are never valid
+     in instructions, which is where this routine is always called.  */
+  if (ep->X_op == O_big
+      || (ep->X_add_symbol
+	  && (walk_no_bignums (ep->X_add_symbol)
+	      || (ep->X_op_symbol
+		  && walk_no_bignums (ep->X_op_symbol)))))
+    {
+      inst.error = _("invalid constant");
+      *str = input_line_pointer;
+      input_line_pointer = save_in;
+      return 1;
+    }
 
-symbolS *  last_label_seen;
-static int label_is_thumb_function_name = FALSE;
+  *str = input_line_pointer;
+  input_line_pointer = save_in;
+  return 0;
+}
 
-/* Literal Pool stuff.  */
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.
 
-#define MAX_LITERAL_POOL_SIZE 1024
+   Note that fp constants aren't represent in the normal way on the ARM.
+   In big endian mode, things are as expected.	However, in little endian
+   mode fp constants are big-endian word-wise, and little-endian byte-wise
+   within the words.  For example, (double) 1.1 in big endian mode is
+   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
+   the byte sequence 99 99 f1 3f 9a 99 99 99.
 
-/* Literal pool structure.  Held on a per-section
-   and per-sub-section basis.  */
-typedef struct literal_pool
+   ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
+
+char *
+md_atof (int type, char * litP, int * sizeP)
 {
-  expressionS    literals [MAX_LITERAL_POOL_SIZE];
-  unsigned int   next_free_entry;
-  unsigned int   id;
-  symbolS *      symbol;
-  segT           section;
-  subsegT        sub_section;
-  struct literal_pool * next;
-} literal_pool;
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  char *t;
+  int i;
 
-/* Pointer to a linked list of literal pools.  */
-literal_pool * list_of_pools = NULL;
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
 
-static literal_pool * find_literal_pool PARAMS ((void));
-static literal_pool * find_or_make_literal_pool PARAMS ((void));
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
 
-static literal_pool *
-find_literal_pool ()
+    case 'x':
+    case 'X':
+      prec = 6;
+      break;
+
+    case 'p':
+    case 'P':
+      prec = 6;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("bad call to MD_ATOF()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * 2;
+
+  if (target_big_endian)
+    {
+      for (i = 0; i < prec; i++)
+	{
+	  md_number_to_chars (litP, (valueT) words[i], 2);
+	  litP += 2;
+	}
+    }
+  else
+    {
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
+	for (i = prec - 1; i >= 0; i--)
+	  {
+	    md_number_to_chars (litP, (valueT) words[i], 2);
+	    litP += 2;
+	  }
+      else
+	/* For a 4 byte float the order of elements in `words' is 1 0.
+	   For an 8 byte float the order is 1 0 3 2.  */
+	for (i = 0; i < prec; i += 2)
+	  {
+	    md_number_to_chars (litP, (valueT) words[i + 1], 2);
+	    md_number_to_chars (litP + 2, (valueT) words[i], 2);
+	    litP += 4;
+	  }
+    }
+
+  return 0;
+}
+
+/* We handle all bad expressions here, so that we can report the faulty
+   instruction in the error message.  */
+void
+md_operand (expressionS * expr)
 {
-  literal_pool * pool;
+  if (in_my_get_expression)
+    expr->X_op = O_illegal;
+}
 
-  for (pool = list_of_pools; pool != NULL; pool = pool->next)
+/* Immediate values.  */
+
+/* Generic immediate-value read function for use in directives.
+   Accepts anything that 'expression' can fold to a constant.
+   *val receives the number.  */
+#ifdef OBJ_ELF
+static int
+immediate_for_directive (int *val)
+{
+  expressionS exp;
+  exp.X_op = O_illegal;
+
+  if (is_immediate_prefix (*input_line_pointer))
     {
-      if (pool->section == now_seg
-	  && pool->sub_section == now_subseg)
-	break;
+      input_line_pointer++;
+      expression (&exp);
     }
 
-  return pool;
+  if (exp.X_op != O_constant)
+    {
+      as_bad (_("expected #constant"));
+      ignore_rest_of_line ();
+      return FAIL;
+    }
+  *val = exp.X_add_number;
+  return SUCCESS;
 }
+#endif
 
-static literal_pool *
-find_or_make_literal_pool ()
+/* Register parsing.  */
+
+/* Generic register parser.  CCP points to what should be the
+   beginning of a register name.  If it is indeed a valid register
+   name, advance CCP over it and return the reg_entry structure;
+   otherwise return NULL.  Does not issue diagnostics.	*/
+
+static struct reg_entry *
+arm_reg_parse_multi (char **ccp)
 {
-  /* Next literal pool ID number.  */
-  static unsigned int latest_pool_num = 1;
-  literal_pool *      pool;
+  char *start = *ccp;
+  char *p;
+  struct reg_entry *reg;
 
-  pool = find_literal_pool ();
+#ifdef REGISTER_PREFIX
+  if (*start != REGISTER_PREFIX)
+    return NULL;
+  start++;
+#endif
+#ifdef OPTIONAL_REGISTER_PREFIX
+  if (*start == OPTIONAL_REGISTER_PREFIX)
+    start++;
+#endif
 
-  if (pool == NULL)
+  p = start;
+  if (!ISALPHA (*p) || !is_name_beginner (*p))
+    return NULL;
+
+  do
+    p++;
+  while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
+
+  reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
+
+  if (!reg)
+    return NULL;
+
+  *ccp = p;
+  return reg;
+}
+
+/* As above, but the register must be of type TYPE, and the return
+   value is the register number or FAIL.  */
+
+static int
+arm_reg_parse (char **ccp, enum arm_reg_type type)
+{
+  char *start = *ccp;
+  struct reg_entry *reg = arm_reg_parse_multi (ccp);
+
+  if (reg && reg->type == type)
+    return reg->number;
+
+  /* Alternative syntaxes are accepted for a few register classes.  */
+  switch (type)
     {
-      /* Create a new pool.  */
-      pool = (literal_pool *) xmalloc (sizeof (* pool));
-      if (! pool)
-	return NULL;
+    case REG_TYPE_MVF:
+    case REG_TYPE_MVD:
+    case REG_TYPE_MVFX:
+    case REG_TYPE_MVDX:
+      /* Generic coprocessor register names are allowed for these.  */
+      if (reg && reg->type == REG_TYPE_CN)
+	return reg->number;
+      break;
 
-      pool->next_free_entry = 0;
-      pool->section         = now_seg;
-      pool->sub_section     = now_subseg;
-      pool->next            = list_of_pools;
-      pool->symbol          = NULL;
+    case REG_TYPE_CP:
+      /* For backward compatibility, a bare number is valid here.  */
+      {
+	unsigned long processor = strtoul (start, ccp, 10);
+	if (*ccp != start && processor <= 15)
+	  return processor;
+      }
 
-      /* Add it to the list.  */
-      list_of_pools = pool;
+    case REG_TYPE_MMXWC:
+      /* WC includes WCG.  ??? I'm not sure this is true for all
+	 instructions that take WC registers.  */
+      if (reg && reg->type == REG_TYPE_MMXWCG)
+	return reg->number;
+      break;
+
+    default:
+      break;
     }
 
-  /* New pools, and emptied pools, will have a NULL symbol.  */
-  if (pool->symbol == NULL)
+  *ccp = start;
+  return FAIL;
+}
+
+/* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
+static long
+parse_reg_list (char ** strp)
+{
+  char * str = * strp;
+  long	 range = 0;
+  int	 another_range;
+
+  /* We come back here if we get ranges concatenated by '+' or '|'.  */
+  do
     {
-      pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
-				    (valueT) 0, &zero_address_frag);
-      pool->id = latest_pool_num ++;
+      another_range = 0;
+
+      if (*str == '{')
+	{
+	  int in_range = 0;
+	  int cur_reg = -1;
+
+	  str++;
+	  do
+	    {
+	      int reg;
+
+	      if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
+		{
+		  inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+		  return FAIL;
+		}
+
+	      if (in_range)
+		{
+		  int i;
+
+		  if (reg <= cur_reg)
+		    {
+		      inst.error = _("bad range in register list");
+		      return FAIL;
+		    }
+
+		  for (i = cur_reg + 1; i < reg; i++)
+		    {
+		      if (range & (1 << i))
+			as_tsktsk
+			  (_("Warning: duplicated register (r%d) in register list"),
+			   i);
+		      else
+			range |= 1 << i;
+		    }
+		  in_range = 0;
+		}
+
+	      if (range & (1 << reg))
+		as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
+			   reg);
+	      else if (reg <= cur_reg)
+		as_tsktsk (_("Warning: register range not in ascending order"));
+
+	      range |= 1 << reg;
+	      cur_reg = reg;
+	    }
+	  while (skip_past_comma (&str) != FAIL
+		 || (in_range = 1, *str++ == '-'));
+	  str--;
+
+	  if (*str++ != '}')
+	    {
+	      inst.error = _("missing `}'");
+	      return FAIL;
+	    }
+	}
+      else
+	{
+	  expressionS expr;
+
+	  if (my_get_expression (&expr, &str, GE_NO_PREFIX))
+	    return FAIL;
+
+	  if (expr.X_op == O_constant)
+	    {
+	      if (expr.X_add_number
+		  != (expr.X_add_number & 0x0000ffff))
+		{
+		  inst.error = _("invalid register mask");
+		  return FAIL;
+		}
+
+	      if ((range & expr.X_add_number) != 0)
+		{
+		  int regno = range & expr.X_add_number;
+
+		  regno &= -regno;
+		  regno = (1 << regno) - 1;
+		  as_tsktsk
+		    (_("Warning: duplicated register (r%d) in register list"),
+		     regno);
+		}
+
+	      range |= expr.X_add_number;
+	    }
+	  else
+	    {
+	      if (inst.reloc.type != 0)
+		{
+		  inst.error = _("expression too complex");
+		  return FAIL;
+		}
+
+	      memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
+	      inst.reloc.type = BFD_RELOC_ARM_MULTI;
+	      inst.reloc.pc_rel = 0;
+	    }
+	}
+
+      if (*str == '|' || *str == '+')
+	{
+	  str++;
+	  another_range = 1;
+	}
     }
+  while (another_range);
 
-  /* Done.  */
-  return pool;
+  *strp = str;
+  return range;
 }
 
-/* Add the literal in the global 'inst'
-   structure to the relevent literal pool.  */
+/* Parse a VFP register list.  If the string is invalid return FAIL.
+   Otherwise return the number of registers, and set PBASE to the first
+   register.  Double precision registers are matched if DP is nonzero.	*/
+
 static int
-add_to_lit_pool ()
+parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
 {
-  literal_pool * pool;
-  unsigned int entry;
+  int base_reg;
+  int new_base;
+  int regtype;
+  int max_regs;
+  int count = 0;
+  int warned = 0;
+  unsigned long mask = 0;
+  int i;
 
-  pool = find_or_make_literal_pool ();
+  if (**str != '{')
+    return FAIL;
 
-  /* Check if this literal value is already in the pool.  */
-  for (entry = 0; entry < pool->next_free_entry; entry ++)
-    {
-      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
-	  && (inst.reloc.exp.X_op == O_constant)
-	  && (pool->literals[entry].X_add_number
-	      == inst.reloc.exp.X_add_number)
-	  && (pool->literals[entry].X_unsigned
-	      == inst.reloc.exp.X_unsigned))
-	break;
+  (*str)++;
 
-      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
-          && (inst.reloc.exp.X_op == O_symbol)
-          && (pool->literals[entry].X_add_number
-	      == inst.reloc.exp.X_add_number)
-          && (pool->literals[entry].X_add_symbol
-	      == inst.reloc.exp.X_add_symbol)
-          && (pool->literals[entry].X_op_symbol
-	      == inst.reloc.exp.X_op_symbol))
-        break;
+  if (dp)
+    {
+      regtype = REG_TYPE_VFD;
+      max_regs = 16;
+    }
+  else
+    {
+      regtype = REG_TYPE_VFS;
+      max_regs = 32;
     }
 
-  /* Do we need to create a new entry?  */
-  if (entry == pool->next_free_entry)
+  base_reg = max_regs;
+
+  do
     {
-      if (entry >= MAX_LITERAL_POOL_SIZE)
+      new_base = arm_reg_parse (str, regtype);
+      if (new_base == FAIL)
 	{
-	  inst.error = _("literal pool overflow");
+	  inst.error = gettext (reg_expected_msgs[regtype]);
 	  return FAIL;
 	}
 
-      pool->literals[entry] = inst.reloc.exp;
-      pool->next_free_entry += 1;
+      if (new_base < base_reg)
+	base_reg = new_base;
+
+      if (mask & (1 << new_base))
+	{
+	  inst.error = _("invalid register list");
+	  return FAIL;
+	}
+
+      if ((mask >> new_base) != 0 && ! warned)
+	{
+	  as_tsktsk (_("register list not in ascending order"));
+	  warned = 1;
+	}
+
+      mask |= 1 << new_base;
+      count++;
+
+      if (**str == '-') /* We have the start of a range expression */
+	{
+	  int high_range;
+
+	  (*str)++;
+
+	  if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
+	    {
+	      inst.error = gettext (reg_expected_msgs[regtype]);
+	      return FAIL;
+	    }
+
+	  if (high_range <= new_base)
+	    {
+	      inst.error = _("register range not in ascending order");
+	      return FAIL;
+	    }
+
+	  for (new_base++; new_base <= high_range; new_base++)
+	    {
+	      if (mask & (1 << new_base))
+		{
+		  inst.error = _("invalid register list");
+		  return FAIL;
+		}
+
+	      mask |= 1 << new_base;
+	      count++;
+	    }
+	}
     }
+  while (skip_past_comma (str) != FAIL);
 
-  inst.reloc.exp.X_op         = O_symbol;
-  inst.reloc.exp.X_add_number = ((int) entry) * 4 - 8;
-  inst.reloc.exp.X_add_symbol = pool->symbol;
+  (*str)++;
 
-  return SUCCESS;
+  /* Sanity check -- should have raised a parse error above.  */
+  if (count == 0 || count > max_regs)
+    abort ();
+
+  *pbase = base_reg;
+
+  /* Final test -- the registers must be consecutive.  */
+  mask >>= base_reg;
+  for (i = 0; i < count; i++)
+    {
+      if ((mask & (1u << i)) == 0)
+	{
+	  inst.error = _("non-contiguous register range");
+	  return FAIL;
+	}
+    }
+
+  return count;
 }
 
-/* Can't use symbol_new here, so have to create a symbol and then at
-   a later date assign it a value. Thats what these functions do.  */
+/* Parse an explicit relocation suffix on an expression.  This is
+   either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
+   arm_reloc_hsh contains no entries, so this function can only
+   succeed if there is no () after the word.  Returns -1 on error,
+   BFD_RELOC_UNUSED if there wasn't any suffix.	 */
+static int
+parse_reloc (char **str)
+{
+  struct reloc_entry *r;
+  char *p, *q;
+
+  if (**str != '(')
+    return BFD_RELOC_UNUSED;
+
+  p = *str + 1;
+  q = p;
+
+  while (*q && *q != ')' && *q != ',')
+    q++;
+  if (*q != ')')
+    return -1;
+
+  if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
+    return -1;
+
+  *str = q + 1;
+  return r->reloc;
+}
+
+/* Directives: register aliases.  */
 
 static void
-symbol_locate (symbolP, name, segment, valu, frag)
-     symbolS *    symbolP;
-     const char * name;		/* It is copied, the caller can modify.  */
-     segT         segment;	/* Segment identifier (SEG_<something>).  */
-     valueT       valu;		/* Symbol value.  */
-     fragS *      frag;		/* Associated fragment.  */
+insert_reg_alias (char *str, int number, int type)
 {
-  unsigned int name_length;
-  char * preserved_copy_of_name;
+  struct reg_entry *new;
+  const char *name;
 
-  name_length = strlen (name) + 1;   /* +1 for \0.  */
-  obstack_grow (&notes, name, name_length);
-  preserved_copy_of_name = obstack_finish (&notes);
-#ifdef STRIP_UNDERSCORE
-  if (preserved_copy_of_name[0] == '_')
-    preserved_copy_of_name++;
-#endif
+  if ((new = hash_find (arm_reg_hsh, str)) != 0)
+    {
+      if (new->builtin)
+	as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
 
-#ifdef tc_canonicalize_symbol_name
-  preserved_copy_of_name =
-    tc_canonicalize_symbol_name (preserved_copy_of_name);
-#endif
+      /* Only warn about a redefinition if it's not defined as the
+	 same register.	 */
+      else if (new->number != number || new->type != type)
+	as_warn (_("ignoring redefinition of register alias '%s'"), str);
 
-  S_SET_NAME (symbolP, preserved_copy_of_name);
+      return;
+    }
 
-  S_SET_SEGMENT (symbolP, segment);
-  S_SET_VALUE (symbolP, valu);
-  symbol_clear_list_pointers (symbolP);
+  name = xstrdup (str);
+  new = xmalloc (sizeof (struct reg_entry));
 
-  symbol_set_frag (symbolP, frag);
+  new->name = name;
+  new->number = number;
+  new->type = type;
+  new->builtin = FALSE;
 
-  /* Link to end of symbol chain.  */
-  {
-    extern int symbol_table_frozen;
-    if (symbol_table_frozen)
-      abort ();
-  }
+  if (hash_insert (arm_reg_hsh, name, (PTR) new))
+    abort ();
+}
 
-  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
+/* Look for the .req directive.	 This is of the form:
 
-  obj_symbol_new_hook (symbolP);
+	new_register_name .req existing_register_name
 
-#ifdef tc_symbol_new_hook
-  tc_symbol_new_hook (symbolP);
+   If we find one, or if it looks sufficiently like one that we want to
+   handle any error here, return non-zero.  Otherwise return zero.  */
+
+static int
+create_register_alias (char * newname, char *p)
+{
+  struct reg_entry *old;
+  char *oldname, *nbuf;
+  size_t nlen;
+
+  /* The input scrubber ensures that whitespace after the mnemonic is
+     collapsed to single spaces.  */
+  oldname = p;
+  if (strncmp (oldname, " .req ", 6) != 0)
+    return 0;
+
+  oldname += 6;
+  if (*oldname == '\0')
+    return 0;
+
+  old = hash_find (arm_reg_hsh, oldname);
+  if (!old)
+    {
+      as_warn (_("unknown register '%s' -- .req ignored"), oldname);
+      return 1;
+    }
+
+  /* If TC_CASE_SENSITIVE is defined, then newname already points to
+     the desired alias name, and p points to its end.  If not, then
+     the desired alias name is in the global original_case_string.  */
+#ifdef TC_CASE_SENSITIVE
+  nlen = p - newname;
+#else
+  newname = original_case_string;
+  nlen = strlen (newname);
 #endif
 
-#ifdef DEBUG_SYMS
-  verify_symbol_chain (symbol_rootP, symbol_lastP);
-#endif /* DEBUG_SYMS  */
-}
+  nbuf = alloca (nlen + 1);
+  memcpy (nbuf, newname, nlen);
+  nbuf[nlen] = '\0';
 
-/* Check that an immediate is valid.
-   If so, convert it to the right format.  */
+  /* Create aliases under the new name as stated; an all-lowercase
+     version of the new name; and an all-uppercase version of the new
+     name.  */
+  insert_reg_alias (nbuf, old->number, old->type);
 
-static unsigned int
-validate_immediate (val)
-     unsigned int val;
-{
-  unsigned int a;
-  unsigned int i;
+  for (p = nbuf; *p; p++)
+    *p = TOUPPER (*p);
 
-#define rotate_left(v, n) (v << n | v >> (32 - n))
+  if (strncmp (nbuf, newname, nlen))
+    insert_reg_alias (nbuf, old->number, old->type);
 
-  for (i = 0; i < 32; i += 2)
-    if ((a = rotate_left (val, i)) <= 0xff)
-      return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
+  for (p = nbuf; *p; p++)
+    *p = TOLOWER (*p);
 
-  return FAIL;
+  if (strncmp (nbuf, newname, nlen))
+    insert_reg_alias (nbuf, old->number, old->type);
+
+  return 1;
+}
+
+/* Should never be called, as .req goes between the alias and the
+   register name, not at the beginning of the line.  */
+static void
+s_req (int a ATTRIBUTE_UNUSED)
+{
+  as_bad (_("invalid syntax for .req directive"));
 }
 
-/* Check to see if an immediate can be computed as two separate immediate
-   values, added together.  We already know that this value cannot be
-   computed by just one ARM instruction.  */
+/* The .unreq directive deletes an alias which was previously defined
+   by .req.  For example:
 
-static unsigned int
-validate_immediate_twopart (val, highpart)
-     unsigned int   val;
-     unsigned int * highpart;
+       my_alias .req r11
+       .unreq my_alias	  */
+
+static void
+s_unreq (int a ATTRIBUTE_UNUSED)
 {
-  unsigned int a;
-  unsigned int i;
+  char * name;
+  char saved_char;
 
-  for (i = 0; i < 32; i += 2)
-    if (((a = rotate_left (val, i)) & 0xff) != 0)
-      {
-	if (a & 0xff00)
-	  {
-	    if (a & ~ 0xffff)
-	      continue;
-	    * highpart = (a  >> 8) | ((i + 24) << 7);
-	  }
-	else if (a & 0xff0000)
-	  {
-	    if (a & 0xff000000)
-	      continue;
-	    * highpart = (a >> 16) | ((i + 16) << 7);
-	  }
-	else
-	  {
-	    assert (a & 0xff000000);
-	    * highpart = (a >> 24) | ((i + 8) << 7);
-	  }
+  name = input_line_pointer;
 
-	return (a & 0xff) | (i << 7);
-      }
+  while (*input_line_pointer != 0
+	 && *input_line_pointer != ' '
+	 && *input_line_pointer != '\n')
+    ++input_line_pointer;
 
-  return FAIL;
-}
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
 
-static int
-validate_offset_imm (val, hwse)
-     unsigned int val;
-     int hwse;
-{
-  if ((hwse && val > 255) || val > 4095)
-    return FAIL;
-  return val;
+  if (!*name)
+    as_bad (_("invalid syntax for .unreq directive"));
+  else
+    {
+      struct reg_entry *reg = hash_find (arm_reg_hsh, name);
+
+      if (!reg)
+	as_bad (_("unknown register alias '%s'"), name);
+      else if (reg->builtin)
+	as_warn (_("ignoring attempt to undefine built-in register '%s'"),
+		 name);
+      else
+	{
+	  hash_delete (arm_reg_hsh, name);
+	  free ((char *) reg->name);
+	  free (reg);
+	}
+    }
+
+  *input_line_pointer = saved_char;
+  demand_empty_rest_of_line ();
 }
 
-
+/* Directives: Instruction set selection.  */
+
 #ifdef OBJ_ELF
 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
-   (This text is taken from version B-02 of the spec):
-
-      4.4.7 Mapping and tagging symbols
-
-      A section of an ARM ELF file can contain a mixture of ARM code,
-      Thumb code, and data.  There are inline transitions between code
-      and data at literal pool boundaries. There can also be inline
-      transitions between ARM code and Thumb code, for example in
-      ARM-Thumb inter-working veneers.  Linkers, machine-level
-      debuggers, profiling tools, and disassembly tools need to map
-      images accurately. For example, setting an ARM breakpoint on a
-      Thumb location, or in a literal pool, can crash the program
-      being debugged, ruining the debugging session.
-
-      ARM ELF entities are mapped (see section 4.4.7.1 below) and
-      tagged (see section 4.4.7.2 below) using local symbols (with
-      binding STB_LOCAL).  To assist consumers, mapping and tagging
-      symbols should be collated first in the symbol table, before
-      other symbols with binding STB_LOCAL.
-
-      To allow properly collated mapping and tagging symbols to be
-      skipped by consumers that have no interest in them, the first
-      such symbol should have the name $m and its st_value field equal
-      to the total number of mapping and tagging symbols (including
-      the $m) in the symbol table.
-
-      4.4.7.1 Mapping symbols
-
-      $a    Labels the first byte of a sequence of ARM instructions.
-            Its type is STT_FUNC.
-
-      $d    Labels the first byte of a sequence of data items.
-            Its type is STT_OBJECT.
-
-      $t    Labels the first byte of a sequence of Thumb instructions.
-            Its type is STT_FUNC.
-
-      This list of mapping symbols may be extended in the future.
-
-      Section-relative mapping symbols
-
-      Mapping symbols defined in a section define a sequence of
-      half-open address intervals that cover the address range of the
-      section. Each interval starts at the address defined by a
-      mapping symbol, and continues up to, but not including, the
-      address defined by the next (in address order) mapping symbol or
-      the end of the section. A corollary is that there must be a
-      mapping symbol defined at the beginning of each section.
-      Consumers can ignore the size of a section-relative mapping
-      symbol. Producers can set it to 0.
-
-      Absolute mapping symbols
-
-      Because of the need to crystallize a Thumb address with the
-      Thumb-bit set, absolute symbol of type STT_FUNC (symbols of type
-      STT_FUNC defined in section SHN_ABS) need to be mapped with $a
-      or $t.
-
-      The extent of a mapping symbol defined in SHN_ABS is [st_value,
-      st_value + st_size), or [st_value, st_value + 1) if st_size = 0,
-      where [x, y) denotes the half-open address range from x,
-      inclusive, to y, exclusive.
-
-      In the absence of a mapping symbol, a consumer can interpret a
-      function symbol with an odd value as the Thumb code address
-      obtained by clearing the least significant bit of the
-      value. This interpretation is deprecated, and it may not work in
-      the future.
-
-   Note - the Tagging symbols ($b, $f, $p $m) have been dropped from
-   the EABI (which is still under development), so they are not
-   implemented here.  */
+   (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
+   Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
+   and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped.  */
 
 static enum mstate mapstate = MAP_UNDEFINED;
 
@@ -2917,28 +1435,28 @@ mapping_state (enum mstate state)
     {
     case MAP_DATA:
       symname = "$d";
-      type = BSF_OBJECT;
+      type = BSF_NO_FLAGS;
       break;
     case MAP_ARM:
       symname = "$a";
-      type = BSF_FUNCTION;
+      type = BSF_NO_FLAGS;
       break;
     case MAP_THUMB:
       symname = "$t";
-      type = BSF_FUNCTION;
+      type = BSF_NO_FLAGS;
       break;
     case MAP_UNDEFINED:
-      return;     
+      return;
     default:
       abort ();
     }
 
-  seg_info (now_seg)->tc_segment_info_data = state;
+  seg_info (now_seg)->tc_segment_info_data.mapstate = state;
 
   symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
   symbol_table_insert (symbolP);
   symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
-  
+
   switch (state)
     {
     case MAP_ARM:
@@ -2946,239 +1464,140 @@ mapping_state (enum mstate state)
       ARM_SET_THUMB (symbolP, 0);
       ARM_SET_INTERWORK (symbolP, support_interwork);
       break;
-      
+
     case MAP_THUMB:
       THUMB_SET_FUNC (symbolP, 1);
       ARM_SET_THUMB (symbolP, 1);
       ARM_SET_INTERWORK (symbolP, support_interwork);
       break;
-      
+
     case MAP_DATA:
     default:
       return;
     }
 }
+#else
+#define mapping_state(x) /* nothing */
+#endif
 
-/* When we change sections we need to issue a new mapping symbol.  */
+/* Find the real, Thumb encoded start of a Thumb function.  */
 
-void
-arm_elf_change_section (void)
+static symbolS *
+find_real_start (symbolS * symbolP)
 {
-  flagword flags;
-
-  if (!SEG_NORMAL (now_seg))
-    return;
+  char *       real_start;
+  const char * name = S_GET_NAME (symbolP);
+  symbolS *    new_target;
 
-  flags = bfd_get_section_flags (stdoutput, now_seg);
+  /* This definition must agree with the one in gcc/config/arm/thumb.c.	 */
+#define STUB_NAME ".real_start_of"
 
-  /* We can ignore sections that only contain debug info.  */
-  if ((flags & SEC_ALLOC) == 0)
-    return;
+  if (name == NULL)
+    abort ();
 
-  mapstate = seg_info (now_seg)->tc_segment_info_data;
-}
-#else
-#define mapping_state(a)
-#endif /* OBJ_ELF */
-
+  /* The compiler may generate BL instructions to local labels because
+     it needs to perform a branch to a far away location. These labels
+     do not have a corresponding ".real_start_of" label.  We check
+     both for S_IS_LOCAL and for a leading dot, to give a way to bypass
+     the ".real_start_of" convention for nonlocal branches.  */
+  if (S_IS_LOCAL (symbolP) || name[0] == '.')
+    return symbolP;
 
-static void
-s_req (a)
-     int a ATTRIBUTE_UNUSED;
-{
-  as_bad (_("invalid syntax for .req directive"));
-}
+  real_start = ACONCAT ((STUB_NAME, name, NULL));
+  new_target = symbol_find (real_start);
 
-/* The .unreq directive deletes an alias which was previously defined
-   by .req.  For example:
+  if (new_target == NULL)
+    {
+      as_warn ("Failed to find real start of function: %s\n", name);
+      new_target = symbolP;
+    }
 
-       my_alias .req r11
-       .unreq my_alias    */
+  return new_target;
+}
 
 static void
-s_unreq (int a ATTRIBUTE_UNUSED)
+opcode_select (int width)
 {
-  char *name;
-  char saved_char;
-
-  skip_whitespace (input_line_pointer);
-  name = input_line_pointer;
+  switch (width)
+    {
+    case 16:
+      if (! thumb_mode)
+	{
+	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+	    as_bad (_("selected processor does not support THUMB opcodes"));
 
-  while (*input_line_pointer != 0
-	 && *input_line_pointer != ' '
-	 && *input_line_pointer != '\n')
-    ++input_line_pointer;
+	  thumb_mode = 1;
+	  /* No need to force the alignment, since we will have been
+	     coming from ARM mode, which is word-aligned.  */
+	  record_alignment (now_seg, 1);
+	}
+      mapping_state (MAP_THUMB);
+      break;
 
-  saved_char = *input_line_pointer;
-  *input_line_pointer = 0;
+    case 32:
+      if (thumb_mode)
+	{
+	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
+	    as_bad (_("selected processor does not support ARM opcodes"));
 
-  if (*name)
-    {
-      enum arm_reg_type req_type = arm_reg_parse_any (name);
+	  thumb_mode = 0;
 
-      if (req_type != REG_TYPE_MAX)
-	{
-	  char *temp_name = name;
-	  int req_no = arm_reg_parse (&temp_name, all_reg_maps[req_type].htab);
+	  if (!need_pass_2)
+	    frag_align (2, 0, 0);
 
-	  if (req_no != FAIL)
-	    {
-	      struct reg_entry *req_entry;
-
-	      /* Check to see if this alias is a builtin one.  */
-	      req_entry = hash_delete (all_reg_maps[req_type].htab, name);
-
-	      if (!req_entry)
-		as_bad (_("unreq: missing hash entry for \"%s\""), name);
-	      else if (req_entry->builtin)
-		/* FIXME: We are deleting a built in register alias which
-		   points to a const data structure, so we only need to
-		   free up the memory used by the key in the hash table.
-		   Unfortunately we have not recorded this value, so this
-		   is a memory leak.  */
-		  /* FIXME: Should we issue a warning message ?  */
-		;
-	      else
-		{
-		  /* Deleting a user defined alias.  We need to free the
-		     key and the value, but fortunately the key is the same
-		     as the value->name field.  */
-		  free ((char *) req_entry->name);
-		  free (req_entry);
-		}
-	    }
-          else
-            as_bad (_(".unreq: unrecognized symbol \"%s\""), name);
+	  record_alignment (now_seg, 1);
 	}
-      else
-        as_bad (_(".unreq: unrecognized symbol \"%s\""), name);
-    }
-  else
-    as_bad (_("invalid syntax for .unreq directive"));
+      mapping_state (MAP_ARM);
+      break;
 
-  *input_line_pointer = saved_char;
-  demand_empty_rest_of_line ();
+    default:
+      as_bad (_("invalid instruction size selected (%d)"), width);
+    }
 }
 
 static void
-s_bss (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_arm (int ignore ATTRIBUTE_UNUSED)
 {
-  /* We don't support putting frags in the BSS segment, we fake it by
-     marking in_bss, then looking at s_skip for clues.  */
-  subseg_set (bss_section, 0);
+  opcode_select (32);
   demand_empty_rest_of_line ();
-  mapping_state (MAP_DATA);
 }
 
 static void
-s_even (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_thumb (int ignore ATTRIBUTE_UNUSED)
 {
-  /* Never make frag if expect extra pass.  */
-  if (!need_pass_2)
-    frag_align (1, 0, 0);
-
-  record_alignment (now_seg, 1);
-
+  opcode_select (16);
   demand_empty_rest_of_line ();
 }
 
 static void
-s_ltorg (ignored)
-     int ignored ATTRIBUTE_UNUSED;
+s_code (int unused ATTRIBUTE_UNUSED)
 {
-  unsigned int entry;
-  literal_pool * pool;
-  char sym_name[20];
-
-  pool = find_literal_pool ();
-  if (pool == NULL
-      || pool->symbol == NULL
-      || pool->next_free_entry == 0)
-    return;
-
-  mapping_state (MAP_DATA);
-
-  /* Align pool as you have word accesses.
-     Only make a frag if we have to.  */
-  if (!need_pass_2)
-    frag_align (2, 0, 0);
-
-  record_alignment (now_seg, 2);
-
-  sprintf (sym_name, "$$lit_\002%x", pool->id);
-
-  symbol_locate (pool->symbol, sym_name, now_seg,
-		 (valueT) frag_now_fix (), frag_now);
-  symbol_table_insert (pool->symbol);
-
-  ARM_SET_THUMB (pool->symbol, thumb_mode);
-
-#if defined OBJ_COFF || defined OBJ_ELF
-  ARM_SET_INTERWORK (pool->symbol, support_interwork);
-#endif
-
-  for (entry = 0; entry < pool->next_free_entry; entry ++)
-    /* First output the expression in the instruction to the pool.  */
-    emit_expr (&(pool->literals[entry]), 4); /* .word  */
-
-  /* Mark the pool as empty.  */
-  pool->next_free_entry = 0;
-  pool->symbol = NULL;
-}
-
-/* Same as s_align_ptwo but align 0 => align 2.  */
-
-static void
-s_align (unused)
-     int unused ATTRIBUTE_UNUSED;
-{
-  register int temp;
-  register long temp_fill;
-  long max_alignment = 15;
+  int temp;
 
   temp = get_absolute_expression ();
-  if (temp > max_alignment)
-    as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
-  else if (temp < 0)
+  switch (temp)
     {
-      as_bad (_("alignment negative. 0 assumed."));
-      temp = 0;
-    }
+    case 16:
+    case 32:
+      opcode_select (temp);
+      break;
 
-  if (*input_line_pointer == ',')
-    {
-      input_line_pointer++;
-      temp_fill = get_absolute_expression ();
+    default:
+      as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
     }
-  else
-    temp_fill = 0;
-
-  if (!temp)
-    temp = 2;
-
-  /* Only make a frag if we HAVE to.  */
-  if (temp && !need_pass_2)
-    frag_align (temp, (int) temp_fill, 0);
-  demand_empty_rest_of_line ();
-
-  record_alignment (now_seg, temp);
 }
 
 static void
-s_force_thumb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_force_thumb (int ignore ATTRIBUTE_UNUSED)
 {
   /* If we are not already in thumb mode go into it, EVEN if
      the target processor does not support thumb instructions.
      This is used by gcc/config/arm/lib1funcs.asm for example
      to compile interworking support functions even if the
-     target processor should not support interworking.  */
+     target processor should not support interworking.	*/
   if (! thumb_mode)
     {
       thumb_mode = 2;
-
       record_alignment (now_seg, 1);
     }
 
@@ -3186,44 +1605,37 @@ s_force_thumb (ignore)
 }
 
 static void
-s_thumb_func (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_thumb_func (int ignore ATTRIBUTE_UNUSED)
 {
-  if (! thumb_mode)
-    opcode_select (16);
+  s_thumb (0);
 
   /* The following label is the name/address of the start of a Thumb function.
-     We need to know this for the interworking support.  */
+     We need to know this for the interworking support.	 */
   label_is_thumb_function_name = TRUE;
-
-  demand_empty_rest_of_line ();
 }
 
 /* Perform a .set directive, but also mark the alias as
    being a thumb function.  */
 
 static void
-s_thumb_set (equiv)
-     int equiv;
+s_thumb_set (int equiv)
 {
   /* XXX the following is a duplicate of the code for s_set() in read.c
      We cannot just call that code as we need to get at the symbol that
      is created.  */
-  register char *    name;
-  register char      delim;
-  register char *    end_name;
-  register symbolS * symbolP;
+  char *    name;
+  char	    delim;
+  char *    end_name;
+  symbolS * symbolP;
 
   /* Especial apologies for the random logic:
      This just grew, and could be parsed much more simply!
      Dean - in haste.  */
-  name      = input_line_pointer;
-  delim     = get_symbol_end ();
+  name	    = input_line_pointer;
+  delim	    = get_symbol_end ();
   end_name  = input_line_pointer;
   *end_name = delim;
 
-  SKIP_WHITESPACE ();
-
   if (*input_line_pointer != ',')
     {
       *end_name = 0;
@@ -3248,11 +1660,11 @@ s_thumb_set (equiv)
 #ifndef NO_LISTING
       /* When doing symbol listings, play games with dummy fragments living
 	 outside the normal fragment chain to record the file and line info
-         for this symbol.  */
+	 for this symbol.  */
       if (listing & LISTING_SYMBOLS)
 	{
 	  extern struct list_info_struct * listing_tail;
-	  fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
+	  fragS * dummy_frag = xmalloc (sizeof (fragS));
 
 	  memset (dummy_frag, 0, sizeof (fragS));
 	  dummy_frag->fr_type = rs_fill;
@@ -3283,7 +1695,7 @@ s_thumb_set (equiv)
 
   demand_empty_rest_of_line ();
 
-  /* XXX Now we come to the Thumb specific bit of code.  */
+  /* XXX Now we come to the Thumb specific bit of code.	 */
 
   THUMB_SET_FUNC (symbolP, 1);
   ARM_SET_THUMB (symbolP, 1);
@@ -3292,3374 +1704,3250 @@ s_thumb_set (equiv)
 #endif
 }
 
+/* Directives: Mode selection.  */
+
+/* .syntax [unified|divided] - choose the new unified syntax
+   (same for Arm and Thumb encoding, modulo slight differences in what
+   can be represented) or the old divergent syntax for each mode.  */
 static void
-opcode_select (width)
-     int width;
+s_syntax (int unused ATTRIBUTE_UNUSED)
 {
-  switch (width)
-    {
-    case 16:
-      if (! thumb_mode)
-	{
-	  if (! (cpu_variant & ARM_EXT_V4T))
-	    as_bad (_("selected processor does not support THUMB opcodes"));
-
-	  thumb_mode = 1;
-	  /* No need to force the alignment, since we will have been
-             coming from ARM mode, which is word-aligned.  */
-	  record_alignment (now_seg, 1);
-	}
-      mapping_state (MAP_THUMB);
-      break;
-
-    case 32:
-      if (thumb_mode)
-	{
-	  if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
-	    as_bad (_("selected processor does not support ARM opcodes"));
-
-	  thumb_mode = 0;
-
-	  if (!need_pass_2)
-	    frag_align (2, 0, 0);
+  char *name, delim;
 
-	  record_alignment (now_seg, 1);
-	}
-      mapping_state (MAP_ARM);
-      break;
+  name = input_line_pointer;
+  delim = get_symbol_end ();
 
-    default:
-      as_bad (_("invalid instruction size selected (%d)"), width);
+  if (!strcasecmp (name, "unified"))
+    unified_syntax = TRUE;
+  else if (!strcasecmp (name, "divided"))
+    unified_syntax = FALSE;
+  else
+    {
+      as_bad (_("unrecognized syntax mode \"%s\""), name);
+      return;
     }
-}
-
-static void
-s_arm (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  opcode_select (32);
+  *input_line_pointer = delim;
   demand_empty_rest_of_line ();
 }
 
-static void
-s_thumb (ignore)
-     int ignore ATTRIBUTE_UNUSED;
-{
-  opcode_select (16);
-  demand_empty_rest_of_line ();
-}
+/* Directives: sectioning and alignment.  */
+
+/* Same as s_align_ptwo but align 0 => align 2.	 */
 
 static void
-s_code (unused)
-     int unused ATTRIBUTE_UNUSED;
+s_align (int unused ATTRIBUTE_UNUSED)
 {
-  register int temp;
+  int temp;
+  long temp_fill;
+  long max_alignment = 15;
 
   temp = get_absolute_expression ();
-  switch (temp)
+  if (temp > max_alignment)
+    as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
+  else if (temp < 0)
     {
-    case 16:
-    case 32:
-      opcode_select (temp);
-      break;
+      as_bad (_("alignment negative. 0 assumed."));
+      temp = 0;
+    }
 
-    default:
-      as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
+  if (*input_line_pointer == ',')
+    {
+      input_line_pointer++;
+      temp_fill = get_absolute_expression ();
     }
+  else
+    temp_fill = 0;
+
+  if (!temp)
+    temp = 2;
+
+  /* Only make a frag if we HAVE to.  */
+  if (temp && !need_pass_2)
+    frag_align (temp, (int) temp_fill, 0);
+  demand_empty_rest_of_line ();
+
+  record_alignment (now_seg, temp);
 }
 
 static void
-end_of_line (str)
-     char *str;
+s_bss (int ignore ATTRIBUTE_UNUSED)
 {
-  skip_whitespace (str);
-
-  if (*str != '\0' && !inst.error)
-    inst.error = _("garbage following instruction");
+  /* We don't support putting frags in the BSS segment, we fake it by
+     marking in_bss, then looking at s_skip for clues.	*/
+  subseg_set (bss_section, 0);
+  demand_empty_rest_of_line ();
+  mapping_state (MAP_DATA);
 }
 
-static int
-skip_past_comma (str)
-     char ** str;
+static void
+s_even (int ignore ATTRIBUTE_UNUSED)
 {
-  char * p = * str, c;
-  int comma = 0;
-
-  while ((c = *p) == ' ' || c == ',')
-    {
-      p++;
-      if (c == ',' && comma++)
-	return FAIL;
-    }
+  /* Never make frag if expect extra pass.  */
+  if (!need_pass_2)
+    frag_align (1, 0, 0);
 
-  if (c == '\0')
-    return FAIL;
+  record_alignment (now_seg, 1);
 
-  *str = p;
-  return comma ? SUCCESS : FAIL;
+  demand_empty_rest_of_line ();
 }
 
-/* A standard register must be given at this point.
-   SHIFT is the place to put it in inst.instruction.
-   Restores input start point on error.
-   Returns the reg#, or FAIL.  */
+/* Directives: Literal pools.  */
 
-static int
-reg_required_here (str, shift)
-     char ** str;
-     int     shift;
+static literal_pool *
+find_literal_pool (void)
 {
-  static char buff [128]; /* XXX  */
-  int         reg;
-  char *      start = * str;
+  literal_pool * pool;
 
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_RN].htab)) != FAIL)
+  for (pool = list_of_pools; pool != NULL; pool = pool->next)
     {
-      if (shift >= 0)
-	inst.instruction |= reg << shift;
-      return reg;
+      if (pool->section == now_seg
+	  && pool->sub_section == now_subseg)
+	break;
     }
 
-  /* Restore the start point, we may have got a reg of the wrong class.  */
-  *str = start;
-
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  sprintf (buff, _("register expected, not '%.100s'"), start);
-  inst.error = buff;
-
-  return FAIL;
-}
-
-/* A Intel Wireless MMX technology register
-   must be given at this point.
-   Shift is the place to put it in inst.instruction.
-   Restores input start point on err.
-   Returns the reg#, or FAIL.  */
-
-static int
-wreg_required_here (str, shift, reg_type)
-     char ** str;
-     int     shift;
-     enum wreg_type reg_type;
-{
-  static char buff [128];
-  int    reg;
-  char * start = *str;
-
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_IWMMXT].htab)) != FAIL)
-    {
-      if (wr_register (reg)
-	  && (reg_type == IWMMXT_REG_WR || reg_type == IWMMXT_REG_WR_OR_WC))
-        {
-          if (shift >= 0)
-            inst.instruction |= (reg ^ WR_PREFIX) << shift;
-          return reg;
-        }
-      else if (wc_register (reg)
-	       && (reg_type == IWMMXT_REG_WC || reg_type == IWMMXT_REG_WR_OR_WC))
-        {
-          if (shift >= 0)
-            inst.instruction |= (reg ^ WC_PREFIX) << shift;
-          return reg;
-        }
-      else if ((wcg_register (reg) && reg_type == IWMMXT_REG_WCG))
-        {
-          if (shift >= 0)
-            inst.instruction |= ((reg ^ WC_PREFIX) - 8) << shift;
-          return reg;
-        }
-    }
-
-  /* Restore the start point, we may have got a reg of the wrong class.  */
-  *str = start;
-
-  /* In the few cases where we might be able to accept
-     something else this error can be overridden.  */
-  sprintf (buff, _("Intel Wireless MMX technology register expected, not '%.100s'"), start);
-  inst.error = buff;
-
-  return FAIL;
+  return pool;
 }
 
-static const struct asm_psr *
-arm_psr_parse (ccp)
-     register char ** ccp;
+static literal_pool *
+find_or_make_literal_pool (void)
 {
-  char * start = * ccp;
-  char   c;
-  char * p;
-  const struct asm_psr * psr;
+  /* Next literal pool ID number.  */
+  static unsigned int latest_pool_num = 1;
+  literal_pool *      pool;
 
-  p = start;
+  pool = find_literal_pool ();
 
-  /* Skip to the end of the next word in the input stream.  */
-  do
+  if (pool == NULL)
     {
-      c = *p++;
-    }
-  while (ISALPHA (c) || c == '_');
-
-  /* Terminate the word.  */
-  *--p = 0;
-
-  /* CPSR's and SPSR's can now be lowercase.  This is just a convenience
-     feature for ease of use and backwards compatibility.  */
-  if (!strncmp (start, "cpsr", 4))
-    strncpy (start, "CPSR", 4);
-  else if (!strncmp (start, "spsr", 4))
-    strncpy (start, "SPSR", 4);
+      /* Create a new pool.  */
+      pool = xmalloc (sizeof (* pool));
+      if (! pool)
+	return NULL;
 
-  /* Now locate the word in the psr hash table.  */
-  psr = (const struct asm_psr *) hash_find (arm_psr_hsh, start);
+      pool->next_free_entry = 0;
+      pool->section	    = now_seg;
+      pool->sub_section	    = now_subseg;
+      pool->next	    = list_of_pools;
+      pool->symbol	    = NULL;
 
-  /* Restore the input stream.  */
-  *p = c;
+      /* Add it to the list.  */
+      list_of_pools = pool;
+    }
 
-  /* If we found a valid match, advance the
-     stream pointer past the end of the word.  */
-  *ccp = p;
+  /* New pools, and emptied pools, will have a NULL symbol.  */
+  if (pool->symbol == NULL)
+    {
+      pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
+				    (valueT) 0, &zero_address_frag);
+      pool->id = latest_pool_num ++;
+    }
 
-  return psr;
+  /* Done.  */
+  return pool;
 }
 
-/* Parse the input looking for a PSR flag.  */
+/* Add the literal in the global 'inst'
+   structure to the relevent literal pool.  */
 
 static int
-psr_required_here (str)
-     char ** str;
+add_to_lit_pool (void)
 {
-  char * start = * str;
-  const struct asm_psr * psr;
+  literal_pool * pool;
+  unsigned int entry;
 
-  psr = arm_psr_parse (str);
+  pool = find_or_make_literal_pool ();
 
-  if (psr)
+  /* Check if this literal value is already in the pool.  */
+  for (entry = 0; entry < pool->next_free_entry; entry ++)
     {
-      /* If this is the SPSR that is being modified, set the R bit.  */
-      if (! psr->cpsr)
-	inst.instruction |= SPSR_BIT;
-
-      /* Set the psr flags in the MSR instruction.  */
-      inst.instruction |= psr->field << PSR_SHIFT;
+      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+	  && (inst.reloc.exp.X_op == O_constant)
+	  && (pool->literals[entry].X_add_number
+	      == inst.reloc.exp.X_add_number)
+	  && (pool->literals[entry].X_unsigned
+	      == inst.reloc.exp.X_unsigned))
+	break;
 
-      return SUCCESS;
+      if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
+	  && (inst.reloc.exp.X_op == O_symbol)
+	  && (pool->literals[entry].X_add_number
+	      == inst.reloc.exp.X_add_number)
+	  && (pool->literals[entry].X_add_symbol
+	      == inst.reloc.exp.X_add_symbol)
+	  && (pool->literals[entry].X_op_symbol
+	      == inst.reloc.exp.X_op_symbol))
+	break;
     }
 
-  /* In the few cases where we might be able to accept
-     something else this error can be overridden.  */
-  inst.error = _("flag for {c}psr instruction expected");
-
-  /* Restore the start point.  */
-  *str = start;
-  return FAIL;
-}
-
-static int
-co_proc_number (str)
-     char **str;
-{
-  int processor, pchar;
-  char *start;
-
-  skip_whitespace (*str);
-  start = *str;
-
-  /* The data sheet seems to imply that just a number on its own is valid
-     here, but the RISC iX assembler seems to accept a prefix 'p'.  We will
-     accept either.  */
-  if ((processor = arm_reg_parse (str, all_reg_maps[REG_TYPE_CP].htab))
-      == FAIL)
+  /* Do we need to create a new entry?	*/
+  if (entry == pool->next_free_entry)
     {
-      *str = start;
-
-      pchar = *(*str)++;
-      if (pchar >= '0' && pchar <= '9')
-	{
-	  processor = pchar - '0';
-	  if (**str >= '0' && **str <= '9')
-	    {
-	      processor = processor * 10 + *(*str)++ - '0';
-	      if (processor > 15)
-		{
-		  inst.error = _("illegal co-processor number");
-		  return FAIL;
-		}
-	    }
-	}
-      else
+      if (entry >= MAX_LITERAL_POOL_SIZE)
 	{
-	  inst.error = _("bad or missing co-processor number");
+	  inst.error = _("literal pool overflow");
 	  return FAIL;
 	}
+
+      pool->literals[entry] = inst.reloc.exp;
+      pool->next_free_entry += 1;
     }
 
-  inst.instruction |= processor << 8;
+  inst.reloc.exp.X_op	      = O_symbol;
+  inst.reloc.exp.X_add_number = ((int) entry) * 4;
+  inst.reloc.exp.X_add_symbol = pool->symbol;
+
   return SUCCESS;
 }
 
-static int
-cp_opc_expr (str, where, length)
-     char ** str;
-     int where;
-     int length;
-{
-  expressionS expr;
-
-  skip_whitespace (* str);
+/* Can't use symbol_new here, so have to create a symbol and then at
+   a later date assign it a value. Thats what these functions do.  */
 
-  memset (&expr, '\0', sizeof (expr));
+static void
+symbol_locate (symbolS *    symbolP,
+	       const char * name,	/* It is copied, the caller can modify.	 */
+	       segT	    segment,	/* Segment identifier (SEG_<something>).  */
+	       valueT	    valu,	/* Symbol value.  */
+	       fragS *	    frag)	/* Associated fragment.	 */
+{
+  unsigned int name_length;
+  char * preserved_copy_of_name;
 
-  if (my_get_expression (&expr, str))
-    return FAIL;
-  if (expr.X_op != O_constant)
-    {
-      inst.error = _("bad or missing expression");
-      return FAIL;
-    }
+  name_length = strlen (name) + 1;   /* +1 for \0.  */
+  obstack_grow (&notes, name, name_length);
+  preserved_copy_of_name = obstack_finish (&notes);
 
-  if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
-    {
-      inst.error = _("immediate co-processor expression too large");
-      return FAIL;
-    }
+#ifdef tc_canonicalize_symbol_name
+  preserved_copy_of_name =
+    tc_canonicalize_symbol_name (preserved_copy_of_name);
+#endif
 
-  inst.instruction |= expr.X_add_number << where;
-  return SUCCESS;
-}
+  S_SET_NAME (symbolP, preserved_copy_of_name);
 
-static int
-cp_reg_required_here (str, where)
-     char ** str;
-     int     where;
-{
-  int    reg;
-  char * start = *str;
+  S_SET_SEGMENT (symbolP, segment);
+  S_SET_VALUE (symbolP, valu);
+  symbol_clear_list_pointers (symbolP);
 
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_CN].htab)) != FAIL)
-    {
-      inst.instruction |= reg << where;
-      return reg;
-    }
+  symbol_set_frag (symbolP, frag);
 
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  inst.error = _("co-processor register expected");
+  /* Link to end of symbol chain.  */
+  {
+    extern int symbol_table_frozen;
 
-  /* Restore the start point.  */
-  *str = start;
-  return FAIL;
-}
+    if (symbol_table_frozen)
+      abort ();
+  }
 
-static int
-fp_reg_required_here (str, where)
-     char ** str;
-     int     where;
-{
-  int    reg;
-  char * start = * str;
+  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
 
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_FN].htab)) != FAIL)
-    {
-      inst.instruction |= reg << where;
-      return reg;
-    }
+  obj_symbol_new_hook (symbolP);
 
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  inst.error = _("floating point register expected");
+#ifdef tc_symbol_new_hook
+  tc_symbol_new_hook (symbolP);
+#endif
 
-  /* Restore the start point.  */
-  *str = start;
-  return FAIL;
+#ifdef DEBUG_SYMS
+  verify_symbol_chain (symbol_rootP, symbol_lastP);
+#endif /* DEBUG_SYMS  */
 }
 
-static int
-cp_address_offset (str)
-     char ** str;
+
+static void
+s_ltorg (int ignored ATTRIBUTE_UNUSED)
 {
-  int offset;
+  unsigned int entry;
+  literal_pool * pool;
+  char sym_name[20];
 
-  skip_whitespace (* str);
+  pool = find_literal_pool ();
+  if (pool == NULL
+      || pool->symbol == NULL
+      || pool->next_free_entry == 0)
+    return;
 
-  if (! is_immediate_prefix (**str))
-    {
-      inst.error = _("immediate expression expected");
-      return FAIL;
-    }
+  mapping_state (MAP_DATA);
 
-  (*str)++;
+  /* Align pool as you have word accesses.
+     Only make a frag if we have to.  */
+  if (!need_pass_2)
+    frag_align (2, 0, 0);
 
-  if (my_get_expression (& inst.reloc.exp, str))
-    return FAIL;
+  record_alignment (now_seg, 2);
 
-  if (inst.reloc.exp.X_op == O_constant)
-    {
-      offset = inst.reloc.exp.X_add_number;
+  sprintf (sym_name, "$$lit_\002%x", pool->id);
 
-      if (offset & 3)
-	{
-	  inst.error = _("co-processor address must be word aligned");
-	  return FAIL;
-	}
+  symbol_locate (pool->symbol, sym_name, now_seg,
+		 (valueT) frag_now_fix (), frag_now);
+  symbol_table_insert (pool->symbol);
 
-      if (offset > 1023 || offset < -1023)
-	{
-	  inst.error = _("offset too large");
-	  return FAIL;
-	}
+  ARM_SET_THUMB (pool->symbol, thumb_mode);
 
-      if (offset >= 0)
-	inst.instruction |= INDEX_UP;
-      else
-	offset = -offset;
+#if defined OBJ_COFF || defined OBJ_ELF
+  ARM_SET_INTERWORK (pool->symbol, support_interwork);
+#endif
 
-      inst.instruction |= offset >> 2;
-    }
-  else
-    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+  for (entry = 0; entry < pool->next_free_entry; entry ++)
+    /* First output the expression in the instruction to the pool.  */
+    emit_expr (&(pool->literals[entry]), 4); /* .word  */
 
-  return SUCCESS;
+  /* Mark the pool as empty.  */
+  pool->next_free_entry = 0;
+  pool->symbol = NULL;
 }
 
-static int
-cp_address_required_here (str, wb_ok)
-     char ** str;
-     int wb_ok;
+#ifdef OBJ_ELF
+/* Forward declarations for functions below, in the MD interface
+   section.  */
+static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
+static valueT create_unwind_entry (int);
+static void start_unwind_section (const segT, int);
+static void add_unwind_opcode (valueT, int);
+static void flush_pending_unwind (void);
+
+/* Directives: Data.  */
+
+static void
+s_arm_elf_cons (int nbytes)
 {
-  char * p = * str;
-  int    pre_inc = 0;
-  int    write_back = 0;
+  expressionS exp;
+
+#ifdef md_flush_pending_output
+  md_flush_pending_output ();
+#endif
 
-  if (*p == '[')
+  if (is_it_end_of_statement ())
     {
-      int reg;
+      demand_empty_rest_of_line ();
+      return;
+    }
 
-      p++;
-      skip_whitespace (p);
+#ifdef md_cons_align
+  md_cons_align (nbytes);
+#endif
 
-      if ((reg = reg_required_here (& p, 16)) == FAIL)
-	return FAIL;
+  mapping_state (MAP_DATA);
+  do
+    {
+      int reloc;
+      char *base = input_line_pointer;
 
-      skip_whitespace (p);
+      expression (& exp);
 
-      if (*p == ']')
+      if (exp.X_op != O_symbol)
+	emit_expr (&exp, (unsigned int) nbytes);
+      else
 	{
-	  p++;
-
-	  skip_whitespace (p);
-
-	  if (*p == '\0')
+	  char *before_reloc = input_line_pointer;
+	  reloc = parse_reloc (&input_line_pointer);
+	  if (reloc == -1)
 	    {
-	      /* As an extension to the official ARM syntax we allow:
-		 
-		   [Rn]
-		   
-	         as a short hand for:
-
-		   [Rn,#0]  */
-	      inst.instruction |= PRE_INDEX | INDEX_UP;
-	      *str = p;
-	      return SUCCESS;
+	      as_bad (_("unrecognized relocation suffix"));
+	      ignore_rest_of_line ();
+	      return;
 	    }
-	  
-	  if (skip_past_comma (& p) == FAIL)
+	  else if (reloc == BFD_RELOC_UNUSED)
+	    emit_expr (&exp, (unsigned int) nbytes);
+	  else
 	    {
-	      inst.error = _("comma expected after closing square bracket");
-	      return FAIL;
-	    }
+	      reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
+	      int size = bfd_get_reloc_size (howto);
 
-	  skip_whitespace (p);
-
-	  if (*p == '#')
-	    {
-	      if (wb_ok)
+	      if (reloc == BFD_RELOC_ARM_PLT32)
 		{
-		  /* [Rn], #expr  */
-		  write_back = WRITE_BACK;
-
-		  if (reg == REG_PC)
-		    {
-		      inst.error = _("pc may not be used in post-increment");
-		      return FAIL;
-		    }
-
-		  if (cp_address_offset (& p) == FAIL)
-		    return FAIL;
+		  as_bad (_("(plt) is only valid on branch targets"));
+		  reloc = BFD_RELOC_UNUSED;
+		  size = 0;
 		}
-	      else
-		pre_inc = PRE_INDEX | INDEX_UP;
-	    }
-	  else if (*p == '{')
-	    {
-	      int option;
-
-	      /* [Rn], {<expr>}  */
-	      p++;
-
-	      skip_whitespace (p);
-
-	      if (my_get_expression (& inst.reloc.exp, & p))
-		return FAIL;
-
-	      if (inst.reloc.exp.X_op == O_constant)
-		{
-		  option = inst.reloc.exp.X_add_number;
-
-		  if (option > 255 || option < 0)
-		    {
-		      inst.error = _("'option' field too large");
-		      return FAIL;
-		    }
 
-		  skip_whitespace (p);
-
-		  if (*p != '}')
-		    {
-		      inst.error = _("'}' expected at end of 'option' field");
-		      return FAIL;
-		    }
-		  else
-		    {
-		      p++;
-		      inst.instruction |= option;
-		      inst.instruction |= INDEX_UP;
-		    }
-		}
+	      if (size > nbytes)
+		as_bad (_("%s relocations do not fit in %d bytes"),
+			howto->name, nbytes);
 	      else
 		{
-		  inst.error = _("non-constant expressions for 'option' field not supported");
-		  return FAIL;
+		  /* We've parsed an expression stopping at O_symbol.
+		     But there may be more expression left now that we
+		     have parsed the relocation marker.  Parse it again.
+		     XXX Surely there is a cleaner way to do this.  */
+		  char *p = input_line_pointer;
+		  int offset;
+		  char *save_buf = alloca (input_line_pointer - base);
+		  memcpy (save_buf, base, input_line_pointer - base);
+		  memmove (base + (input_line_pointer - before_reloc),
+			   base, before_reloc - base);
+
+		  input_line_pointer = base + (input_line_pointer-before_reloc);
+		  expression (&exp);
+		  memcpy (base, save_buf, p - base);
+
+		  offset = nbytes - size;
+		  p = frag_more ((int) nbytes);
+		  fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
+			       size, &exp, 0, reloc);
 		}
 	    }
-	  else
-	    {
-	      inst.error = _("# or { expected after comma");
-	      return FAIL;	      
-	    }
 	}
-      else
-	{
-	  /* '['Rn, #expr']'[!]  */
-
-	  if (skip_past_comma (& p) == FAIL)
-	    {
-	      inst.error = _("pre-indexed expression expected");
-	      return FAIL;
-	    }
-
-	  pre_inc = PRE_INDEX;
-
-	  if (cp_address_offset (& p) == FAIL)
-	    return FAIL;
-
-	  skip_whitespace (p);
+    }
+  while (*input_line_pointer++ == ',');
 
-	  if (*p++ != ']')
-	    {
-	      inst.error = _("missing ]");
-	      return FAIL;
-	    }
+  /* Put terminator back into stream.  */
+  input_line_pointer --;
+  demand_empty_rest_of_line ();
+}
 
-	  skip_whitespace (p);
 
-	  if (wb_ok && *p == '!')
-	    {
-	      if (reg == REG_PC)
-		{
-		  inst.error = _("pc may not be used with write-back");
-		  return FAIL;
-		}
+/* Parse a .rel31 directive.  */
 
-	      p++;
-	      write_back = WRITE_BACK;
-	    }
-	}
-    }
-  else
-    {
-      if (my_get_expression (&inst.reloc.exp, &p))
-	return FAIL;
+static void
+s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
+{
+  expressionS exp;
+  char *p;
+  valueT highbit;
 
-      inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
-      inst.reloc.exp.X_add_number -= 8;  /* PC rel adjust.  */
-      inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = PRE_INDEX;
-    }
+  highbit = 0;
+  if (*input_line_pointer == '1')
+    highbit = 0x80000000;
+  else if (*input_line_pointer != '0')
+    as_bad (_("expected 0 or 1"));
 
-  inst.instruction |= write_back | pre_inc;
-  *str = p;
-  return SUCCESS;
-}
+  input_line_pointer++;
+  if (*input_line_pointer != ',')
+    as_bad (_("missing comma"));
+  input_line_pointer++;
 
-static int
-cp_byte_address_offset (str)
-     char ** str;
-{
-  int offset;
+#ifdef md_flush_pending_output
+  md_flush_pending_output ();
+#endif
 
-  skip_whitespace (* str);
+#ifdef md_cons_align
+  md_cons_align (4);
+#endif
 
-  if (! is_immediate_prefix (**str))
-    {
-      inst.error = _("immediate expression expected");
-      return FAIL;
-    }
+  mapping_state (MAP_DATA);
 
-  (*str)++;
-  
-  if (my_get_expression (& inst.reloc.exp, str))
-    return FAIL;
-  
-  if (inst.reloc.exp.X_op == O_constant)
-    {
-      offset = inst.reloc.exp.X_add_number;
-      
-      if (offset > 255 || offset < -255)
-        {
-          inst.error = _("offset too large");
-          return FAIL;
-        }
-
-      if (offset >= 0)
-        inst.instruction |= INDEX_UP;
-      else
-        offset = -offset;
+  expression (&exp);
 
-      inst.instruction |= offset;
-    }
-  else
-    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+  p = frag_more (4);
+  md_number_to_chars (p, highbit, 4);
+  fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
+	       BFD_RELOC_ARM_PREL31);
 
-  return SUCCESS;
+  demand_empty_rest_of_line ();
 }
 
-static int
-cp_byte_address_required_here (str)
-     char ** str;
-{
-  char * p = * str;
-  int    pre_inc = 0;
-  int    write_back = 0;
+/* Directives: AEABI stack-unwind tables.  */
 
-  if (*p == '[')
-    {
-      int reg;
+/* Parse an unwind_fnstart directive.  Simply records the current location.  */
 
-      p++;
-      skip_whitespace (p);
-
-      if ((reg = reg_required_here (& p, 16)) == FAIL)
-        return FAIL;
-
-      skip_whitespace (p);
+static void
+s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+  /* Mark the start of the function.  */
+  unwind.proc_start = expr_build_dot ();
 
-      if (*p == ']')
-        {
-          p++;
-          
-          if (skip_past_comma (& p) == SUCCESS)
-            {
-              /* [Rn], #expr */
-              write_back = WRITE_BACK;
-              
-              if (reg == REG_PC)
-                {
-                  inst.error = _("pc may not be used in post-increment");
-                  return FAIL;
-                }
-
-              if (cp_byte_address_offset (& p) == FAIL)
-                return FAIL;
-            }
-          else
-            pre_inc = PRE_INDEX | INDEX_UP;
-        }
-      else
-        {
-          /* '['Rn, #expr']'[!] */
-
-          if (skip_past_comma (& p) == FAIL)
-            {
-              inst.error = _("pre-indexed expression expected");
-              return FAIL;
-            }
-
-          pre_inc = PRE_INDEX;
-          
-          if (cp_byte_address_offset (& p) == FAIL)
-            return FAIL;
-
-          skip_whitespace (p);
-
-          if (*p++ != ']')
-            {
-              inst.error = _("missing ]");
-              return FAIL;
-            }
-
-          skip_whitespace (p);
-
-          if (*p == '!')
-            {
-              if (reg == REG_PC)
-                {
-                  inst.error = _("pc may not be used with write-back");
-                  return FAIL;
-                }
-
-              p++;
-              write_back = WRITE_BACK;
-            }
-        }
-    }
-  else
-    {
-      if (my_get_expression (&inst.reloc.exp, &p))
-        return FAIL;
+  /* Reset the rest of the unwind info.	 */
+  unwind.opcode_count = 0;
+  unwind.table_entry = NULL;
+  unwind.personality_routine = NULL;
+  unwind.personality_index = -1;
+  unwind.frame_size = 0;
+  unwind.fp_offset = 0;
+  unwind.fp_reg = 13;
+  unwind.fp_used = 0;
+  unwind.sp_restored = 0;
+}
 
-      inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM_S2;
-      inst.reloc.exp.X_add_number -= 8;  /* PC rel adjust.  */
-      inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = PRE_INDEX;
-    }
 
-  inst.instruction |= write_back | pre_inc;
-  *str = p;
-  return SUCCESS;
-}
+/* Parse a handlerdata directive.  Creates the exception handling table entry
+   for the function.  */
 
 static void
-do_empty (str)
-     char * str;
+s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
 {
-  /* Do nothing really.  */
-  end_of_line (str);
+  demand_empty_rest_of_line ();
+  if (unwind.table_entry)
+    as_bad (_("dupicate .handlerdata directive"));
+
+  create_unwind_entry (1);
 }
 
+/* Parse an unwind_fnend directive.  Generates the index table entry.  */
+
 static void
-do_mrs (str)
-     char *str;
+s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
 {
-  int skip = 0;
+  long where;
+  char *ptr;
+  valueT val;
 
-  /* Only one syntax.  */
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 12) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  demand_empty_rest_of_line ();
 
-  if (skip_past_comma (&str) == FAIL)
-    {
-      inst.error = _("comma expected after register name");
-      return;
-    }
+  /* Add eh table entry.  */
+  if (unwind.table_entry == NULL)
+    val = create_unwind_entry (0);
+  else
+    val = 0;
 
-  skip_whitespace (str);
+  /* Add index table entry.  This is two words.	 */
+  start_unwind_section (unwind.saved_seg, 1);
+  frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
 
-  if (   strcmp (str, "CPSR") == 0
-      || strcmp (str, "SPSR") == 0
-	 /* Lower case versions for backwards compatibility.  */
-      || strcmp (str, "cpsr") == 0
-      || strcmp (str, "spsr") == 0)
-    skip = 4;
-
-  /* This is for backwards compatibility with older toolchains.  */
-  else if (   strcmp (str, "cpsr_all") == 0
-	   || strcmp (str, "spsr_all") == 0)
-    skip = 8;
+  ptr = frag_more (8);
+  where = frag_now_fix () - 8;
+
+  /* Self relative offset of the function start.  */
+  fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
+	   BFD_RELOC_ARM_PREL31);
+
+  /* Indicate dependency on EHABI-defined personality routines to the
+     linker, if it hasn't been done already.  */
+  if (unwind.personality_index >= 0 && unwind.personality_index < 3
+      && !(marked_pr_dependency & (1 << unwind.personality_index)))
+    {
+      static const char *const name[] = {
+	"__aeabi_unwind_cpp_pr0",
+	"__aeabi_unwind_cpp_pr1",
+	"__aeabi_unwind_cpp_pr2"
+      };
+      symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
+      fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
+      marked_pr_dependency |= 1 << unwind.personality_index;
+      seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
+	= marked_pr_dependency;
+    }
+
+  if (val)
+    /* Inline exception table entry.  */
+    md_number_to_chars (ptr + 4, val, 4);
   else
-    {
-      inst.error = _("CPSR or SPSR expected");
-      return;
-    }
+    /* Self relative offset of the table entry.	 */
+    fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
+	     BFD_RELOC_ARM_PREL31);
 
-  if (* str == 's' || * str == 'S')
-    inst.instruction |= SPSR_BIT;
-  str += skip;
-
-  end_of_line (str);
+  /* Restore the original section.  */
+  subseg_set (unwind.saved_seg, unwind.saved_subseg);
 }
 
-/* Two possible forms:
-      "{C|S}PSR_<field>, Rm",
-      "{C|S}PSR_f, #expression".  */
+
+/* Parse an unwind_cantunwind directive.  */
 
 static void
-do_msr (str)
-     char * str;
+s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
 {
-  skip_whitespace (str);
+  demand_empty_rest_of_line ();
+  if (unwind.personality_routine || unwind.personality_index != -1)
+    as_bad (_("personality routine specified for cantunwind frame"));
 
-  if (psr_required_here (& str) == FAIL)
-    return;
+  unwind.personality_index = -2;
+}
 
-  if (skip_past_comma (& str) == FAIL)
-    {
-      inst.error = _("comma missing after psr flags");
-      return;
-    }
 
-  skip_whitespace (str);
+/* Parse a personalityindex directive.	*/
 
-  if (reg_required_here (& str, 0) != FAIL)
-    {
-      inst.error = NULL;
-      end_of_line (str);
-      return;
-    }
+static void
+s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
+{
+  expressionS exp;
 
-  if (! is_immediate_prefix (* str))
-    {
-      inst.error =
-	_("only a register or immediate value can follow a psr flag");
-      return;
-    }
+  if (unwind.personality_routine || unwind.personality_index != -1)
+    as_bad (_("duplicate .personalityindex directive"));
 
-  str ++;
-  inst.error = NULL;
+  expression (&exp);
 
-  if (my_get_expression (& inst.reloc.exp, & str))
+  if (exp.X_op != O_constant
+      || exp.X_add_number < 0 || exp.X_add_number > 15)
     {
-      inst.error =
-	_("only a register or immediate value can follow a psr flag");
+      as_bad (_("bad personality routine number"));
+      ignore_rest_of_line ();
       return;
     }
 
-#if 0  /* The first edition of the ARM architecture manual stated that
-	  writing anything other than the flags with an immediate operation
-	  had UNPREDICTABLE effects.  This constraint was removed in the
-	  second edition of the specification.  */
-  if ((cpu_variant & ARM_EXT_V5) != ARM_EXT_V5
-      && inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
-    {
-      inst.error = _("immediate value cannot be used to set this field");
-      return;
-    }
-#endif
+  unwind.personality_index = exp.X_add_number;
 
-  inst.instruction |= INST_IMMEDIATE;
+  demand_empty_rest_of_line ();
+}
 
-  if (inst.reloc.exp.X_add_symbol)
-    {
-      inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
-      inst.reloc.pc_rel = 0;
-    }
-  else
-    {
-      unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
 
-      if (value == (unsigned) FAIL)
-	{
-	  inst.error = _("invalid constant");
-	  return;
-	}
+/* Parse a personality directive.  */
 
-      inst.instruction |= value;
-    }
+static void
+s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
+{
+  char *name, *p, c;
+
+  if (unwind.personality_routine || unwind.personality_index != -1)
+    as_bad (_("duplicate .personality directive"));
 
-  inst.error = NULL;
-  end_of_line (str);
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = input_line_pointer;
+  unwind.personality_routine = symbol_find_or_make (name);
+  *p = c;
+  demand_empty_rest_of_line ();
 }
 
-/* Long Multiply Parser
-   UMULL RdLo, RdHi, Rm, Rs
-   SMULL RdLo, RdHi, Rm, Rs
-   UMLAL RdLo, RdHi, Rm, Rs
-   SMLAL RdLo, RdHi, Rm, Rs.  */
+
+/* Parse a directive saving core registers.  */
 
 static void
-do_mull (str)
-     char * str;
+s_arm_unwind_save_core (void)
 {
-  int rdlo, rdhi, rm, rs;
-
-  /* Only one format "rdlo, rdhi, rm, rs".  */
-  skip_whitespace (str);
+  valueT op;
+  long range;
+  int n;
 
-  if ((rdlo = reg_required_here (&str, 12)) == FAIL)
+  range = parse_reg_list (&input_line_pointer);
+  if (range == FAIL)
     {
-      inst.error = BAD_ARGS;
+      as_bad (_("expected register list"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (skip_past_comma (&str) == FAIL
-      || (rdhi = reg_required_here (&str, 16)) == FAIL)
+  demand_empty_rest_of_line ();
+
+  /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
+     into .unwind_save {..., sp...}.  We aren't bothered about the value of
+     ip because it is clobbered by calls.  */
+  if (unwind.sp_restored && unwind.fp_reg == 12
+      && (range & 0x3000) == 0x1000)
     {
-      inst.error = BAD_ARGS;
-      return;
+      unwind.opcode_count--;
+      unwind.sp_restored = 0;
+      range = (range | 0x2000) & ~0x1000;
+      unwind.pending_offset = 0;
     }
 
-  if (skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
+  /* Pop r4-r15.  */
+  if (range & 0xfff0)
     {
-      inst.error = BAD_ARGS;
-      return;
+      /* See if we can use the short opcodes.  These pop a block of up to 8
+	 registers starting with r4, plus maybe r14.  */
+      for (n = 0; n < 8; n++)
+	{
+	  /* Break at the first non-saved register.	 */
+	  if ((range & (1 << (n + 4))) == 0)
+	    break;
+	}
+      /* See if there are any other bits set.  */
+      if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
+	{
+	  /* Use the long form.  */
+	  op = 0x8000 | ((range >> 4) & 0xfff);
+	  add_unwind_opcode (op, 2);
+	}
+      else
+	{
+	  /* Use the short form.  */
+	  if (range & 0x4000)
+	    op = 0xa8; /* Pop r14.	*/
+	  else
+	    op = 0xa0; /* Do not pop r14.  */
+	  op |= (n - 1);
+	  add_unwind_opcode (op, 1);
+	}
     }
 
-  /* rdhi, rdlo and rm must all be different.  */
-  if (rdlo == rdhi || rdlo == rm || rdhi == rm)
-    as_tsktsk (_("rdhi, rdlo and rm must all be different"));
-
-  if (skip_past_comma (&str) == FAIL
-      || (rs = reg_required_here (&str, 8)) == FAIL)
+  /* Pop r0-r3.	 */
+  if (range & 0xf)
     {
-      inst.error = BAD_ARGS;
-      return;
+      op = 0xb100 | (range & 0xf);
+      add_unwind_opcode (op, 2);
     }
 
-  if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
+  /* Record the number of bytes pushed.	 */
+  for (n = 0; n < 16; n++)
     {
-      inst.error = BAD_PC;
-      return;
+      if (range & (1 << n))
+	unwind.frame_size += 4;
     }
-
-  end_of_line (str);
 }
 
+
+/* Parse a directive saving FPA registers.  */
+
 static void
-do_mul (str)
-     char * str;
+s_arm_unwind_save_fpa (int reg)
 {
-  int rd, rm;
-
-  /* Only one format "rd, rm, rs".  */
-  skip_whitespace (str);
+  expressionS exp;
+  int num_regs;
+  valueT op;
 
-  if ((rd = reg_required_here (&str, 16)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  /* Get Number of registers to transfer.  */
+  if (skip_past_comma (&input_line_pointer) != FAIL)
+    expression (&exp);
+  else
+    exp.X_op = O_illegal;
 
-  if (rd == REG_PC)
+  if (exp.X_op != O_constant)
     {
-      inst.error = BAD_PC;
+      as_bad (_("expected , <constant>"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  num_regs = exp.X_add_number;
 
-  if (rm == REG_PC)
+  if (num_regs < 1 || num_regs > 4)
     {
-      inst.error = BAD_PC;
+      as_bad (_("number of registers must be in the range [1:4]"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (rm == rd)
-    as_tsktsk (_("rd and rm should be different in mul"));
+  demand_empty_rest_of_line ();
 
-  if (skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 8)) == FAIL)
+  if (reg == 4)
     {
-      inst.error = BAD_ARGS;
-      return;
+      /* Short form.  */
+      op = 0xb4 | (num_regs - 1);
+      add_unwind_opcode (op, 1);
     }
-
-  if (rm == REG_PC)
+  else
     {
-      inst.error = BAD_PC;
-      return;
+      /* Long form.  */
+      op = 0xc800 | (reg << 4) | (num_regs - 1);
+      add_unwind_opcode (op, 2);
     }
-
-  end_of_line (str);
+  unwind.frame_size += num_regs * 12;
 }
 
-static void
-do_mla (str)
-     char * str;
-{
-  int rd, rm;
-
-  /* Only one format "rd, rm, rs, rn".  */
-  skip_whitespace (str);
 
-  if ((rd = reg_required_here (&str, 16)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+/* Parse a directive saving VFP registers.  */
 
-  if (rd == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+static void
+s_arm_unwind_save_vfp (void)
+{
+  int count;
+  unsigned int reg;
+  valueT op;
 
-  if (rm == REG_PC)
+  count = parse_vfp_reg_list (&input_line_pointer, &reg, 1);
+  if (count == FAIL)
     {
-      inst.error = BAD_PC;
+      as_bad (_("expected register list"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (rm == rd)
-    as_tsktsk (_("rd and rm should be different in mla"));
+  demand_empty_rest_of_line ();
 
-  if (skip_past_comma (&str) == FAIL
-      || (rd = reg_required_here (&str, 8)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 12)) == FAIL)
+  if (reg == 8)
     {
-      inst.error = BAD_ARGS;
-      return;
+      /* Short form.  */
+      op = 0xb8 | (count - 1);
+      add_unwind_opcode (op, 1);
     }
-
-  if (rd == REG_PC || rm == REG_PC)
+  else
     {
-      inst.error = BAD_PC;
-      return;
+      /* Long form.  */
+      op = 0xb300 | (reg << 4) | (count - 1);
+      add_unwind_opcode (op, 2);
     }
-
-  end_of_line (str);
+  unwind.frame_size += count * 8 + 4;
 }
 
-/* Expects *str -> the characters "acc0", possibly with leading blanks.
-   Advances *str to the next non-alphanumeric.
-   Returns 0, or else FAIL (in which case sets inst.error).
 
-  (In a future XScale, there may be accumulators other than zero.
-  At that time this routine and its callers can be upgraded to suit.)  */
+/* Parse a directive saving iWMMXt data registers.  */
 
-static int
-accum0_required_here (str)
-     char ** str;
+static void
+s_arm_unwind_save_mmxwr (void)
 {
-  static char buff [128];	/* Note the address is taken.  Hence, static.  */
-  char * p = * str;
-  char   c;
-  int result = 0;		/* The accum number.  */
-
-  skip_whitespace (p);
-
-  *str = p;			/* Advance caller's string pointer too.  */
-  c = *p++;
-  while (ISALNUM (c))
-    c = *p++;
+  int reg;
+  int hi_reg;
+  int i;
+  unsigned mask = 0;
+  valueT op;
 
-  *--p = 0;			/* Aap nul into input buffer at non-alnum.  */
+  if (*input_line_pointer == '{')
+    input_line_pointer++;
 
-  if (! ( streq (*str, "acc0") || streq (*str, "ACC0")))
+  do
     {
-      sprintf (buff, _("acc0 expected, not '%.100s'"), *str);
-      inst.error = buff;
-      result = FAIL;
-    }
+      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
 
-  *p = c;			/* Unzap.  */
-  *str = p;			/* Caller's string pointer to after match.  */
-  return result;
-}
-
-/* Expects **str -> after a comma. May be leading blanks.
-   Advances *str, recognizing a load  mode, and setting inst.instruction.
-   Returns rn, or else FAIL (in which case may set inst.error
-   and not advance str)
+      if (reg == FAIL)
+	{
+	  as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
+	  goto error;
+	}
 
-   Note: doesn't know Rd, so no err checks that require such knowledge.  */
+      if (mask >> reg)
+	as_tsktsk (_("register list not in ascending order"));
+      mask |= 1 << reg;
 
-static int
-ld_mode_required_here (string)
-     char ** string;
-{
-  char * str = * string;
-  int    rn;
-  int    pre_inc = 0;
-
-  skip_whitespace (str);
+      if (*input_line_pointer == '-')
+	{
+	  input_line_pointer++;
+	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
+	  if (hi_reg == FAIL)
+	    {
+	      as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
+	      goto error;
+	    }
+	  else if (reg >= hi_reg)
+	    {
+	      as_bad (_("bad register range"));
+	      goto error;
+	    }
+	  for (; reg < hi_reg; reg++)
+	    mask |= 1 << reg;
+	}
+    }
+  while (skip_past_comma (&input_line_pointer) != FAIL);
 
-  if (* str == '[')
-    {
-      str++;
+  if (*input_line_pointer == '}')
+    input_line_pointer++;
 
-      skip_whitespace (str);
+  demand_empty_rest_of_line ();
 
-      if ((rn = reg_required_here (& str, 16)) == FAIL)
-	return FAIL;
+  /* Generate any deferred opcodes becuuse we're going to be looking at
+     the list.	*/
+  flush_pending_unwind ();
 
-      skip_whitespace (str);
+  for (i = 0; i < 16; i++)
+    {
+      if (mask & (1 << i))
+	unwind.frame_size += 8;
+    }
 
-      if (* str == ']')
+  /* Attempt to combine with a previous opcode.	 We do this because gcc
+     likes to output separate unwind directives for a single block of
+     registers.	 */
+  if (unwind.opcode_count > 0)
+    {
+      i = unwind.opcodes[unwind.opcode_count - 1];
+      if ((i & 0xf8) == 0xc0)
 	{
-	  str ++;
-
-	  if (skip_past_comma (& str) == SUCCESS)
+	  i &= 7;
+	  /* Only merge if the blocks are contiguous.  */
+	  if (i < 6)
 	    {
-	      /* [Rn],... (post inc) */
-	      if (ldst_extend_v4 (&str) == FAIL)
-		return FAIL;
+	      if ((mask & 0xfe00) == (1 << 9))
+		{
+		  mask |= ((1 << (i + 11)) - 1) & 0xfc00;
+		  unwind.opcode_count--;
+		}
 	    }
-	  else 	      /* [Rn] */
+	  else if (i == 6 && unwind.opcode_count >= 2)
 	    {
-	      skip_whitespace (str);
+	      i = unwind.opcodes[unwind.opcode_count - 2];
+	      reg = i >> 4;
+	      i &= 0xf;
 
-	      if (* str == '!')
+	      op = 0xffff << (reg - 1);
+	      if (reg > 0
+		  || ((mask & op) == (1u << (reg - 1))))
 		{
-		  str ++;
-		  inst.instruction |= WRITE_BACK;
+		  op = (1 << (reg + i + 1)) - 1;
+		  op &= ~((1 << reg) - 1);
+		  mask |= op;
+		  unwind.opcode_count -= 2;
 		}
-
-	      inst.instruction |= INDEX_UP | HWOFFSET_IMM;
-	      pre_inc = 1;
 	    }
 	}
-      else	  /* [Rn,...] */
+    }
+
+  hi_reg = 15;
+  /* We want to generate opcodes in the order the registers have been
+     saved, ie. descending order.  */
+  for (reg = 15; reg >= -1; reg--)
+    {
+      /* Save registers in blocks.  */
+      if (reg < 0
+	  || !(mask & (1 << reg)))
 	{
-	  if (skip_past_comma (& str) == FAIL)
+	  /* We found an unsaved reg.  Generate opcodes to save the
+	     preceeding block.	*/
+	  if (reg != hi_reg)
 	    {
-	      inst.error = _("pre-indexed expression expected");
-	      return FAIL;
+	      if (reg == 9)
+		{
+		  /* Short form.  */
+		  op = 0xc0 | (hi_reg - 10);
+		  add_unwind_opcode (op, 1);
+		}
+	      else
+		{
+		  /* Long form.	 */
+		  op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
+		  add_unwind_opcode (op, 2);
+		}
 	    }
+	  hi_reg = reg - 1;
+	}
+    }
 
-	  pre_inc = 1;
+  return;
+error:
+  ignore_rest_of_line ();
+}
 
-	  if (ldst_extend_v4 (&str) == FAIL)
-	    return FAIL;
+static void
+s_arm_unwind_save_mmxwcg (void)
+{
+  int reg;
+  int hi_reg;
+  unsigned mask = 0;
+  valueT op;
 
-	  skip_whitespace (str);
+  if (*input_line_pointer == '{')
+    input_line_pointer++;
 
-	  if (* str ++ != ']')
-	    {
-	      inst.error = _("missing ]");
-	      return FAIL;
-	    }
+  do
+    {
+      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
+
+      if (reg == FAIL)
+	{
+	  as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
+	  goto error;
+	}
 
-	  skip_whitespace (str);
+      reg -= 8;
+      if (mask >> reg)
+	as_tsktsk (_("register list not in ascending order"));
+      mask |= 1 << reg;
 
-	  if (* str == '!')
+      if (*input_line_pointer == '-')
+	{
+	  input_line_pointer++;
+	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
+	  if (hi_reg == FAIL)
+	    {
+	      as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
+	      goto error;
+	    }
+	  else if (reg >= hi_reg)
 	    {
-	      str ++;
-	      inst.instruction |= WRITE_BACK;
+	      as_bad (_("bad register range"));
+	      goto error;
 	    }
+	  for (; reg < hi_reg; reg++)
+	    mask |= 1 << reg;
 	}
     }
-  else if (* str == '=')	/* ldr's "r,=label" syntax */
-    /* We should never reach here, because <text> = <expression> is
-       caught gas/read.c read_a_source_file() as a .set operation.  */
-    return FAIL;
-  else				/* PC +- 8 bit immediate offset.  */
-    {
-      if (my_get_expression (& inst.reloc.exp, & str))
-	return FAIL;
+  while (skip_past_comma (&input_line_pointer) != FAIL);
 
-      inst.instruction            |= HWOFFSET_IMM;	/* The I bit.  */
-      inst.reloc.type              = BFD_RELOC_ARM_OFFSET_IMM8;
-      inst.reloc.exp.X_add_number -= 8;  		/* PC rel adjust.  */
-      inst.reloc.pc_rel            = 1;
-      inst.instruction            |= (REG_PC << 16);
+  if (*input_line_pointer == '}')
+    input_line_pointer++;
 
-      rn = REG_PC;
-      pre_inc = 1;
-    }
+  demand_empty_rest_of_line ();
 
-  inst.instruction |= (pre_inc ? PRE_INDEX : 0);
-  * string = str;
+  /* Generate any deferred opcodes becuuse we're going to be looking at
+     the list.	*/
+  flush_pending_unwind ();
 
-  return rn;
+  for (reg = 0; reg < 16; reg++)
+    {
+      if (mask & (1 << reg))
+	unwind.frame_size += 4;
+    }
+  op = 0xc700 | mask;
+  add_unwind_opcode (op, 2);
+  return;
+error:
+  ignore_rest_of_line ();
 }
 
-/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
-   SMLAxy{cond} Rd,Rm,Rs,Rn
-   SMLAWy{cond} Rd,Rm,Rs,Rn
-   Error if any register is R15.  */
+
+/* Parse an unwind_save directive.  */
 
 static void
-do_smla (str)
-     char *        str;
+s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
 {
-  int rd, rm, rs, rn;
-
-  skip_whitespace (str);
-
-  if ((rd = reg_required_here (& str, 16)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rs = reg_required_here (& str, 8)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rn = reg_required_here (& str, 12)) == FAIL)
-    inst.error = BAD_ARGS;
-
-  else if (rd == REG_PC || rm == REG_PC || rs == REG_PC || rn == REG_PC)
-    inst.error = BAD_PC;
-
-  else
-    end_of_line (str);
-}
+  char *peek;
+  struct reg_entry *reg;
+  bfd_boolean had_brace = FALSE;
 
-/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
-   SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
-   Error if any register is R15.
-   Warning if Rdlo == Rdhi.  */
+  /* Figure out what sort of save we have.  */
+  peek = input_line_pointer;
 
-static void
-do_smlal (str)
-     char *        str;
-{
-  int rdlo, rdhi, rm, rs;
+  if (*peek == '{')
+    {
+      had_brace = TRUE;
+      peek++;
+    }
 
-  skip_whitespace (str);
+  reg = arm_reg_parse_multi (&peek);
 
-  if ((rdlo = reg_required_here (& str, 12)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rdhi = reg_required_here (& str, 16)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rs = reg_required_here (& str, 8)) == FAIL)
+  if (!reg)
     {
-      inst.error = BAD_ARGS;
+      as_bad (_("register expected"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
+  switch (reg->type)
     {
-      inst.error = BAD_PC;
+    case REG_TYPE_FN:
+      if (had_brace)
+	{
+	  as_bad (_("FPA .unwind_save does not take a register list"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      s_arm_unwind_save_fpa (reg->number);
       return;
-    }
 
-  if (rdlo == rdhi)
-    as_tsktsk (_("rdhi and rdlo must be different"));
+    case REG_TYPE_RN:	  s_arm_unwind_save_core ();   return;
+    case REG_TYPE_VFD:	   s_arm_unwind_save_vfp ();	return;
+    case REG_TYPE_MMXWR:  s_arm_unwind_save_mmxwr ();  return;
+    case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
 
-  end_of_line (str);
+    default:
+      as_bad (_(".unwind_save does not support this kind of register"));
+      ignore_rest_of_line ();
+    }
 }
 
-/* ARM V5E (El Segundo) signed-multiply (argument parse)
-   SMULxy{cond} Rd,Rm,Rs
-   Error if any register is R15.  */
+
+/* Parse an unwind_movsp directive.  */
 
 static void
-do_smul (str)
-     char *        str;
+s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
 {
-  int rd, rm, rs;
+  int reg;
+  valueT op;
 
-  skip_whitespace (str);
+  reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
+  if (reg == FAIL)
+    {
+      as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
+      ignore_rest_of_line ();
+      return;
+    }
+  demand_empty_rest_of_line ();
+
+  if (reg == REG_SP || reg == REG_PC)
+    {
+      as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
+      return;
+    }
 
-  if ((rd = reg_required_here (& str, 16)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rs = reg_required_here (& str, 8)) == FAIL)
-    inst.error = BAD_ARGS;
+  if (unwind.fp_reg != REG_SP)
+    as_bad (_("unexpected .unwind_movsp directive"));
 
-  else if (rd == REG_PC || rm == REG_PC || rs == REG_PC)
-    inst.error = BAD_PC;
+  /* Generate opcode to restore the value.  */
+  op = 0x90 | reg;
+  add_unwind_opcode (op, 1);
 
-  else
-    end_of_line (str);
+  /* Record the information for later.	*/
+  unwind.fp_reg = reg;
+  unwind.fp_offset = unwind.frame_size;
+  unwind.sp_restored = 1;
 }
 
-/* ARM V5E (El Segundo) saturating-add/subtract (argument parse)
-   Q[D]{ADD,SUB}{cond} Rd,Rm,Rn
-   Error if any register is R15.  */
+/* Parse an unwind_pad directive.  */
 
 static void
-do_qadd (str)
-     char *        str;
+s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
 {
-  int rd, rm, rn;
+  int offset;
 
-  skip_whitespace (str);
+  if (immediate_for_directive (&offset) == FAIL)
+    return;
 
-  if ((rd = reg_required_here (& str, 12)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rn = reg_required_here (& str, 16)) == FAIL)
-    inst.error = BAD_ARGS;
+  if (offset & 3)
+    {
+      as_bad (_("stack increment must be multiple of 4"));
+      ignore_rest_of_line ();
+      return;
+    }
 
-  else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
-    inst.error = BAD_PC;
+  /* Don't generate any opcodes, just record the details for later.  */
+  unwind.frame_size += offset;
+  unwind.pending_offset += offset;
 
-  else
-    end_of_line (str);
+  demand_empty_rest_of_line ();
 }
 
-/* ARM V5E (el Segundo)
-   MCRRcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
-   MRRCcc <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
-
-   These are equivalent to the XScale instructions MAR and MRA,
-   respectively, when coproc == 0, opcode == 0, and CRm == 0.
-
-   Result unpredicatable if Rd or Rn is R15.  */
+/* Parse an unwind_setfp directive.  */
 
 static void
-do_co_reg2c (str)
-     char *        str;
+s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
 {
-  int rd, rn;
+  int sp_reg;
+  int fp_reg;
+  int offset;
 
-  skip_whitespace (str);
+  fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
+  if (skip_past_comma (&input_line_pointer) == FAIL)
+    sp_reg = FAIL;
+  else
+    sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
 
-  if (co_proc_number (& str) == FAIL)
+  if (fp_reg == FAIL || sp_reg == FAIL)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+      as_bad (_("expected <reg>, <reg>"));
+      ignore_rest_of_line ();
       return;
     }
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_opc_expr (& str, 4, 4) == FAIL)
+  /* Optional constant.	 */
+  if (skip_past_comma (&input_line_pointer) != FAIL)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      if (immediate_for_directive (&offset) == FAIL)
+	return;
     }
+  else
+    offset = 0;
+
+  demand_empty_rest_of_line ();
 
-  if (skip_past_comma (& str) == FAIL
-      || (rd = reg_required_here (& str, 12)) == FAIL)
+  if (sp_reg != 13 && sp_reg != unwind.fp_reg)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+      as_bad (_("register must be either sp or set by a previous"
+		"unwind_movsp directive"));
       return;
     }
 
-  if (skip_past_comma (& str) == FAIL
-      || (rn = reg_required_here (& str, 16)) == FAIL)
+  /* Don't generate any opcodes, just record the information for later.	 */
+  unwind.fp_reg = fp_reg;
+  unwind.fp_used = 1;
+  if (sp_reg == 13)
+    unwind.fp_offset = unwind.frame_size - offset;
+  else
+    unwind.fp_offset -= offset;
+}
+
+/* Parse an unwind_raw directive.  */
+
+static void
+s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
+{
+  expressionS exp;
+  /* This is an arbitary limit.	 */
+  unsigned char op[16];
+  int count;
+
+  expression (&exp);
+  if (exp.X_op == O_constant
+      && skip_past_comma (&input_line_pointer) != FAIL)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      unwind.frame_size += exp.X_add_number;
+      expression (&exp);
     }
+  else
+    exp.X_op = O_illegal;
 
-  /* Unpredictable result if rd or rn is R15.  */
-  if (rd == REG_PC || rn == REG_PC)
-    as_tsktsk
-      (_("Warning: instruction unpredictable when using r15"));
-
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 0) == FAIL)
+  if (exp.X_op != O_constant)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+      as_bad (_("expected <offset>, <opcode>"));
+      ignore_rest_of_line ();
       return;
     }
 
-  end_of_line (str);
-}
-
-/* ARM V5 count-leading-zeroes instruction (argument parse)
-     CLZ{<cond>} <Rd>, <Rm>
-     Condition defaults to COND_ALWAYS.
-     Error if Rd or Rm are R15.  */
+  count = 0;
 
-static void
-do_clz (str)
-     char *        str;
-{
-  int rd, rm;
+  /* Parse the opcode.	*/
+  for (;;)
+    {
+      if (count >= 16)
+	{
+	  as_bad (_("unwind opcode too long"));
+	  ignore_rest_of_line ();
+	}
+      if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
+	{
+	  as_bad (_("invalid unwind opcode"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      op[count++] = exp.X_add_number;
 
-  skip_whitespace (str);
+      /* Parse the next byte.  */
+      if (skip_past_comma (&input_line_pointer) == FAIL)
+	break;
 
-  if (((rd = reg_required_here (& str, 12)) == FAIL)
-      || (skip_past_comma (& str) == FAIL)
-      || ((rm = reg_required_here (& str, 0)) == FAIL))
-    inst.error = BAD_ARGS;
+      expression (&exp);
+    }
 
-  else if (rd == REG_PC || rm == REG_PC )
-    inst.error = BAD_PC;
+  /* Add the opcode bytes in reverse order.  */
+  while (count--)
+    add_unwind_opcode (op[count], 1);
 
-  else
-    end_of_line (str);
+  demand_empty_rest_of_line ();
 }
 
-/* ARM V5 (argument parse)
-     LDC2{L} <coproc>, <CRd>, <addressing mode>
-     STC2{L} <coproc>, <CRd>, <addressing mode>
-     Instruction is not conditional, and has 0xf in the condition field.
-     Otherwise, it's the same as LDC/STC.  */
+
+/* Parse a .eabi_attribute directive.  */
 
 static void
-do_lstc2 (str)
-     char *        str;
+s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
 {
-  skip_whitespace (str);
+  expressionS exp;
+  bfd_boolean is_string;
+  int tag;
+  unsigned int i = 0;
+  char *s = NULL;
+  char saved_char;
 
-  if (co_proc_number (& str) == FAIL)
+  expression (& exp);
+  if (exp.X_op != O_constant)
+    goto bad;
+
+  tag = exp.X_add_number;
+  if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
+    is_string = 1;
+  else
+    is_string = 0;
+
+  if (skip_past_comma (&input_line_pointer) == FAIL)
+    goto bad;
+  if (tag == 32 || !is_string)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+      expression (& exp);
+      if (exp.X_op != O_constant)
+	{
+	  as_bad (_("expected numeric constant"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      i = exp.X_add_number;
     }
-  else if (skip_past_comma (& str) == FAIL
-	   || cp_reg_required_here (& str, 12) == FAIL)
+  if (tag == Tag_compatibility
+      && skip_past_comma (&input_line_pointer) == FAIL)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+      as_bad (_("expected comma"));
+      ignore_rest_of_line ();
+      return;
     }
-  else if (skip_past_comma (& str) == FAIL
-	   || cp_address_required_here (&str, CP_WB_OK) == FAIL)
+  if (is_string)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      skip_whitespace(input_line_pointer);
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      input_line_pointer++;
+      s = input_line_pointer;
+      while (*input_line_pointer && *input_line_pointer != '"')
+	input_line_pointer++;
+      if (*input_line_pointer != '"')
+	goto bad_string;
+      saved_char = *input_line_pointer;
+      *input_line_pointer = 0;
     }
   else
-    end_of_line (str);
-}
-
-/* ARM V5 (argument parse)
-     CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>, <opcode_2>
-     Instruction is not conditional, and has 0xf in the condition field.
-     Otherwise, it's the same as CDP.  */
-
-static void
-do_cdp2 (str)
-     char *        str;
-{
-  skip_whitespace (str);
-
-  if (co_proc_number (& str) == FAIL)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      s = NULL;
+      saved_char = 0;
     }
+  
+  if (tag == Tag_compatibility)
+    elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
+  else if (is_string)
+    elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
+  else
+    elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_opc_expr (& str, 20,4) == FAIL)
+  if (s)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      *input_line_pointer = saved_char;
+      input_line_pointer++;
     }
+  demand_empty_rest_of_line ();
+  return;
+bad_string:
+  as_bad (_("bad string constant"));
+  ignore_rest_of_line ();
+  return;
+bad:
+  as_bad (_("expected <tag> , <value>"));
+  ignore_rest_of_line ();
+}
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void s_arm_arch (int);
+static void s_arm_cpu (int);
+static void s_arm_fpu (int);
+#endif /* OBJ_ELF */
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 16) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+/* This table describes all the machine specific pseudo-ops the assembler
+   has to support.  The fields are:
+     pseudo-op name without dot
+     function to call to execute this pseudo-op
+     Integer arg to pass to the function.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* Never called because '.req' does not start a line.	 */
+  { "req",	   s_req,	  0 },
+  { "unreq",	   s_unreq,	  0 },
+  { "bss",	   s_bss,	  0 },
+  { "align",	   s_align,	  0 },
+  { "arm",	   s_arm,	  0 },
+  { "thumb",	   s_thumb,	  0 },
+  { "code",	   s_code,	  0 },
+  { "force_thumb", s_force_thumb, 0 },
+  { "thumb_func",  s_thumb_func,  0 },
+  { "thumb_set",   s_thumb_set,	  0 },
+  { "even",	   s_even,	  0 },
+  { "ltorg",	   s_ltorg,	  0 },
+  { "pool",	   s_ltorg,	  0 },
+  { "syntax",	   s_syntax,	  0 },
+#ifdef OBJ_ELF
+  { "word",	   s_arm_elf_cons, 4 },
+  { "long",	   s_arm_elf_cons, 4 },
+  { "rel31",	   s_arm_rel31,	  0 },
+  { "fnstart",		s_arm_unwind_fnstart,	0 },
+  { "fnend",		s_arm_unwind_fnend,	0 },
+  { "cantunwind",	s_arm_unwind_cantunwind, 0 },
+  { "personality",	s_arm_unwind_personality, 0 },
+  { "personalityindex",	s_arm_unwind_personalityindex, 0 },
+  { "handlerdata",	s_arm_unwind_handlerdata, 0 },
+  { "save",		s_arm_unwind_save,	0 },
+  { "movsp",		s_arm_unwind_movsp,	0 },
+  { "pad",		s_arm_unwind_pad,	0 },
+  { "setfp",		s_arm_unwind_setfp,	0 },
+  { "unwind_raw",	s_arm_unwind_raw,	0 },
+  { "cpu",		s_arm_cpu,		0 },
+  { "arch",		s_arm_arch,		0 },
+  { "fpu",		s_arm_fpu,		0 },
+  { "eabi_attribute",	s_arm_eabi_attribute,	0 },
+#else
+  { "word",	   cons, 4},
+#endif
+  { "extend",	   float_cons, 'x' },
+  { "ldouble",	   float_cons, 'x' },
+  { "packed",	   float_cons, 'p' },
+  { 0, 0, 0 }
+};
+
+/* Parser functions used exclusively in instruction operands.  */
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 0) == FAIL)
+/* Generic immediate-value read function for use in insn parsing.
+   STR points to the beginning of the immediate (the leading #);
+   VAL receives the value; if the value is outside [MIN, MAX]
+   issue an error.  PREFIX_OPT is true if the immediate prefix is
+   optional.  */
+
+static int
+parse_immediate (char **str, int *val, int min, int max,
+		 bfd_boolean prefix_opt)
+{
+  expressionS exp;
+  my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
+  if (exp.X_op != O_constant)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.error = _("constant expression required");
+      return FAIL;
     }
 
-  if (skip_past_comma (& str) == SUCCESS)
+  if (exp.X_add_number < min || exp.X_add_number > max)
     {
-      if (cp_opc_expr (& str, 5, 3) == FAIL)
-	{
-	  if (!inst.error)
-	    inst.error = BAD_ARGS;
-	  return;
-	}
+      inst.error = _("immediate value out of range");
+      return FAIL;
     }
 
-  end_of_line (str);
+  *val = exp.X_add_number;
+  return SUCCESS;
 }
 
-/* ARM V5 (argument parse)
-     MCR2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
-     MRC2 <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>, <opcode_2>
-     Instruction is not conditional, and has 0xf in the condition field.
-     Otherwise, it's the same as MCR/MRC.  */
+/* Returns the pseudo-register number of an FPA immediate constant,
+   or FAIL if there isn't a valid constant here.  */
 
-static void
-do_co_reg2 (str)
-     char *        str;
+static int
+parse_fpa_immediate (char ** str)
 {
-  skip_whitespace (str);
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  char *	 save_in;
+  expressionS	 exp;
+  int		 i;
+  int		 j;
 
-  if (co_proc_number (& str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  /* First try and match exact strings, this is to guarantee
+     that some formats will work even for cross assembly.  */
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_opc_expr (& str, 21, 3) == FAIL)
+  for (i = 0; fp_const[i]; i++)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
+	{
+	  char *start = *str;
 
-  if (skip_past_comma (& str) == FAIL
-      || reg_required_here (& str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+	  *str += strlen (fp_const[i]);
+	  if (is_end_of_line[(unsigned char) **str])
+	    return i + 8;
+	  *str = start;
+	}
     }
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 16) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  /* Just because we didn't get a match doesn't mean that the constant
+     isn't valid, just that it is in a format that we don't
+     automatically recognize.  Try parsing it with the standard
+     expression routines.  */
+
+  memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
 
-  if (skip_past_comma (& str) == FAIL
-      || cp_reg_required_here (& str, 0) == FAIL)
+  /* Look for a raw floating point number.  */
+  if ((save_in = atof_ieee (*str, 'x', words)) != NULL
+      && is_end_of_line[(unsigned char) *save_in])
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      for (i = 0; i < NUM_FLOAT_VALS; i++)
+	{
+	  for (j = 0; j < MAX_LITTLENUMS; j++)
+	    {
+	      if (words[j] != fp_values[i][j])
+		break;
+	    }
+
+	  if (j == MAX_LITTLENUMS)
+	    {
+	      *str = save_in;
+	      return i + 8;
+	    }
+	}
     }
 
-  if (skip_past_comma (& str) == SUCCESS)
+  /* Try and parse a more complex expression, this will probably fail
+     unless the code uses a floating point prefix (eg "0f").  */
+  save_in = input_line_pointer;
+  input_line_pointer = *str;
+  if (expression (&exp) == absolute_section
+      && exp.X_op == O_big
+      && exp.X_add_number < 0)
     {
-      if (cp_opc_expr (& str, 5, 3) == FAIL)
+      /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
+	 Ditto for 15.	*/
+      if (gen_to_words (words, 5, (long) 15) == 0)
 	{
-	  if (!inst.error)
-	    inst.error = BAD_ARGS;
-	  return;
+	  for (i = 0; i < NUM_FLOAT_VALS; i++)
+	    {
+	      for (j = 0; j < MAX_LITTLENUMS; j++)
+		{
+		  if (words[j] != fp_values[i][j])
+		    break;
+		}
+
+	      if (j == MAX_LITTLENUMS)
+		{
+		  *str = input_line_pointer;
+		  input_line_pointer = save_in;
+		  return i + 8;
+		}
+	    }
 	}
     }
 
-  end_of_line (str);
+  *str = input_line_pointer;
+  input_line_pointer = save_in;
+  inst.error = _("invalid FPA immediate expression");
+  return FAIL;
 }
 
-/* ARM v5TEJ.  Jump to Jazelle code.  */
-static void
-do_bxj (str)
-     char * str;
+/* Shift operands.  */
+enum shift_kind
 {
-  int reg;
+  SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
+};
 
-  skip_whitespace (str);
+struct asm_shift_name
+{
+  const char	  *name;
+  enum shift_kind  kind;
+};
 
-  if ((reg = reg_required_here (&str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+/* Third argument to parse_shift.  */
+enum parse_shift_mode
+{
+  NO_SHIFT_RESTRICT,		/* Any kind of shift is accepted.  */
+  SHIFT_IMMEDIATE,		/* Shift operand must be an immediate.	*/
+  SHIFT_LSL_OR_ASR_IMMEDIATE,	/* Shift must be LSL or ASR immediate.	*/
+  SHIFT_ASR_IMMEDIATE,		/* Shift must be ASR immediate.	 */
+  SHIFT_LSL_IMMEDIATE,		/* Shift must be LSL immediate.	 */
+};
 
-  /* Note - it is not illegal to do a "bxj pc".  Useless, but not illegal.  */
-  if (reg == REG_PC)
-    as_tsktsk (_("use of r15 in bxj is not really useful"));
+/* Parse a <shift> specifier on an ARM data processing instruction.
+   This has three forms:
 
-  end_of_line (str);
-}
+     (LSL|LSR|ASL|ASR|ROR) Rs
+     (LSL|LSR|ASL|ASR|ROR) #imm
+     RRX
 
-/* ARM V6 umaal (argument parse). */
+   Note that ASL is assimilated to LSL in the instruction encoding, and
+   RRX to ROR #0 (which cannot be written as such).  */
 
-static void
-do_umaal (str)
-     char *str;
+static int
+parse_shift (char **str, int i, enum parse_shift_mode mode)
 {
+  const struct asm_shift_name *shift_name;
+  enum shift_kind shift;
+  char *s = *str;
+  char *p = s;
+  int reg;
 
-  int rdlo, rdhi, rm, rs;
+  for (p = *str; ISALPHA (*p); p++)
+    ;
 
-  skip_whitespace (str);
-  if ((rdlo = reg_required_here (& str, 12)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rdhi = reg_required_here (& str, 16)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rs = reg_required_here (& str, 8)) == FAIL)
+  if (p == *str)
     {
-      inst.error = BAD_ARGS;
-      return;      
+      inst.error = _("shift expression expected");
+      return FAIL;
     }
 
-  if (rdlo == REG_PC || rdhi == REG_PC || rm == REG_PC || rs == REG_PC)
+  shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
+
+  if (shift_name == NULL)
     {
-      inst.error = BAD_PC;
-      return;
+      inst.error = _("shift expression expected");
+      return FAIL;
     }
 
-  end_of_line (str);
-}
+  shift = shift_name->kind;
 
-/* ARM V6 strex (argument parse). */
+  switch (mode)
+    {
+    case NO_SHIFT_RESTRICT:
+    case SHIFT_IMMEDIATE:   break;
 
-static void 
-do_strex (str)
-     char *str;
-{
-  int rd, rm, rn;
+    case SHIFT_LSL_OR_ASR_IMMEDIATE:
+      if (shift != SHIFT_LSL && shift != SHIFT_ASR)
+	{
+	  inst.error = _("'LSL' or 'ASR' required");
+	  return FAIL;
+	}
+      break;
 
-  /* Parse Rd, Rm,. */
-  skip_whitespace (str);
-  if ((rd = reg_required_here (& str, 12)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || (rm = reg_required_here (& str, 0)) == FAIL
-      || skip_past_comma (& str) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  if (rd == REG_PC || rm == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
-  if (rd == rm)
-    {
-      inst.error = _("Rd equal to Rm or Rn yields unpredictable results");
-      return;
-    }
+    case SHIFT_LSL_IMMEDIATE:
+      if (shift != SHIFT_LSL)
+	{
+	  inst.error = _("'LSL' required");
+	  return FAIL;
+	}
+      break;
 
-  /* Skip past '['. */
-  if ((strlen (str) >= 1) 
-      && strncmp (str, "[", 1) == 0)
-    str+=1;
-  skip_whitespace (str);  
+    case SHIFT_ASR_IMMEDIATE:
+      if (shift != SHIFT_ASR)
+	{
+	  inst.error = _("'ASR' required");
+	  return FAIL;
+	}
+      break;
 
-  /* Parse Rn. */
-  if ((rn = reg_required_here (& str, 16)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  else if (rn == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
+    default: abort ();
     }
-  if (rd == rn)
+
+  if (shift != SHIFT_RRX)
     {
-      inst.error = _("Rd equal to Rm or Rn yields unpredictable results");
-      return;
-    }
-  skip_whitespace (str);  
+      /* Whitespace can appear here if the next thing is a bare digit.	*/
+      skip_whitespace (p);
 
-  /* Skip past ']'. */
-  if ((strlen (str) >= 1) 
-      && strncmp (str, "]", 1) == 0)
-    str+=1;
-  
-  end_of_line (str);
+      if (mode == NO_SHIFT_RESTRICT
+	  && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
+	{
+	  inst.operands[i].imm = reg;
+	  inst.operands[i].immisreg = 1;
+	}
+      else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+	return FAIL;
+    }
+  inst.operands[i].shift_kind = shift;
+  inst.operands[i].shifted = 1;
+  *str = p;
+  return SUCCESS;
 }
 
-/* ARM V6 ssat (argument parse). */
-
-static void
-do_ssat (str)
-     char* str;
-{
-  do_sat (&str, /*bias=*/-1);
-  end_of_line (str);
-}
+/* Parse a <shifter_operand> for an ARM data processing instruction:
 
-/* ARM V6 usat (argument parse). */
+      #<immediate>
+      #<immediate>, <rotate>
+      <Rm>
+      <Rm>, <shift>
 
-static void
-do_usat (str)
-     char* str;
-{
-  do_sat (&str, /*bias=*/0);
-  end_of_line (str);
-}
+   where <shift> is defined by parse_shift above, and <rotate> is a
+   multiple of 2 between 0 and 30.  Validation of immediate operands
+   is deferred to md_apply_fix.  */
 
-static void
-do_sat (str, bias)
-     char **str;
-     int    bias;
+static int
+parse_shifter_operand (char **str, int i)
 {
-  int rd, rm;
+  int value;
   expressionS expr;
 
-  skip_whitespace (*str);
-  
-  /* Parse <Rd>, field. */
-  if ((rd = reg_required_here (str, 12)) == FAIL
-      || skip_past_comma (str) == FAIL)
+  if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
     {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  if (rd == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
+      inst.operands[i].reg = value;
+      inst.operands[i].isreg = 1;
 
-  /* Parse #<immed>,  field. */
-  if (is_immediate_prefix (**str))
-    (*str)++;
-  else
-    {
-      inst.error = _("immediate expression expected");
-      return;
-    }
-  if (my_get_expression (&expr, str))
-    {
-      inst.error = _("bad expression");
-      return;
-    }
-  if (expr.X_op != O_constant)
-    {
-      inst.error = _("constant expression expected");
-      return;
-    }
-  if (expr.X_add_number + bias < 0
-      || expr.X_add_number + bias > 31)
-    {
-      inst.error = _("immediate value out of range");
-      return;
-    }
-  inst.instruction |= (expr.X_add_number + bias) << 16;
-  if (skip_past_comma (str) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+      /* parse_shift will override this if appropriate */
+      inst.reloc.exp.X_op = O_constant;
+      inst.reloc.exp.X_add_number = 0;
 
-  /* Parse <Rm> field. */
-  if ((rm = reg_required_here (str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
+      if (skip_past_comma (str) == FAIL)
+	return SUCCESS;
+
+      /* Shift operation on register.  */
+      return parse_shift (str, i, NO_SHIFT_RESTRICT);
     }
-  if (rm == REG_PC)
+
+  if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
+    return FAIL;
+
+  if (skip_past_comma (str) == SUCCESS)
     {
-      inst.error = BAD_PC;
-      return;
+      /* #x, y -- ie explicit rotation by Y.  */
+      if (my_get_expression (&expr, str, GE_NO_PREFIX))
+	return FAIL;
+
+      if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
+	{
+	  inst.error = _("constant expression expected");
+	  return FAIL;
+	}
+
+      value = expr.X_add_number;
+      if (value < 0 || value > 30 || value % 2 != 0)
+	{
+	  inst.error = _("invalid rotation");
+	  return FAIL;
+	}
+      if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
+	{
+	  inst.error = _("invalid constant");
+	  return FAIL;
+	}
+
+      /* Convert to decoded value.  md_apply_fix will put it back.  */
+      inst.reloc.exp.X_add_number
+	= (((inst.reloc.exp.X_add_number << (32 - value))
+	    | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
     }
 
-  if (skip_past_comma (str) == SUCCESS)
-    decode_shift (str, SHIFT_LSL_OR_ASR_IMMEDIATE);
+  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+  inst.reloc.pc_rel = 0;
+  return SUCCESS;
 }
 
-/* ARM V6 ssat16 (argument parse). */
+/* Parse all forms of an ARM address expression.  Information is written
+   to inst.operands[i] and/or inst.reloc.
 
-static void
-do_ssat16 (str)
-     char *str;
-{
-  do_sat16 (&str, /*bias=*/-1);
-  end_of_line (str);
-}
+   Preindexed addressing (.preind=1):
 
-static void
-do_usat16 (str)
-     char *str;
-{
-  do_sat16 (&str, /*bias=*/0);
-  end_of_line (str);
-}
+   [Rn, #offset]       .reg=Rn .reloc.exp=offset
+   [Rn, +/-Rm]	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
+   [Rn, +/-Rm, shift]  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
+		       .shift_kind=shift .reloc.exp=shift_imm
 
-static void
-do_sat16 (str, bias)
-     char **str;
-     int bias;
-{
-  int rd, rm;
-  expressionS expr;
+   These three may have a trailing ! which causes .writeback to be set also.
 
-  skip_whitespace (*str);
+   Postindexed addressing (.postind=1, .writeback=1):
 
-  /* Parse the <Rd> field. */
-  if ((rd = reg_required_here (str, 12)) == FAIL
-      || skip_past_comma (str) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  if (rd == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
+   [Rn], #offset       .reg=Rn .reloc.exp=offset
+   [Rn], +/-Rm	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
+   [Rn], +/-Rm, shift  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
+		       .shift_kind=shift .reloc.exp=shift_imm
 
-  /* Parse #<immed>, field. */
-  if (is_immediate_prefix (**str))
-    (*str)++;
-  else
-    {
-      inst.error = _("immediate expression expected");
-      return;
-    }
-  if (my_get_expression (&expr, str))
+   Unindexed addressing (.preind=0, .postind=0):
+
+   [Rn], {option}      .reg=Rn .imm=option .immisreg=0
+
+   Other:
+
+   [Rn]{!}	       shorthand for [Rn,#0]{!}
+   =immediate	       .isreg=0 .reloc.exp=immediate
+   label	       .reg=PC .reloc.pc_rel=1 .reloc.exp=label
+
+  It is the caller's responsibility to check for addressing modes not
+  supported by the instruction, and to set inst.reloc.type.  */
+
+static int
+parse_address (char **str, int i)
+{
+  char *p = *str;
+  int reg;
+
+  if (skip_past_char (&p, '[') == FAIL)
     {
-      inst.error = _("bad expression");
-      return;
+      if (skip_past_char (&p, '=') == FAIL)
+	{
+	  /* bare address - translate to PC-relative offset */
+	  inst.reloc.pc_rel = 1;
+	  inst.operands[i].reg = REG_PC;
+	  inst.operands[i].isreg = 1;
+	  inst.operands[i].preind = 1;
+	}
+      /* else a load-constant pseudo op, no special treatment needed here */
+
+      if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
+	return FAIL;
+
+      *str = p;
+      return SUCCESS;
     }
-  if (expr.X_op != O_constant)
+
+  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
-      inst.error = _("constant expression expected");
-      return;
+      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+      return FAIL;
     }
-  if (expr.X_add_number + bias < 0
-      || expr.X_add_number + bias > 15)
+  inst.operands[i].reg = reg;
+  inst.operands[i].isreg = 1;
+
+  if (skip_past_comma (&p) == SUCCESS)
     {
-      inst.error = _("immediate value out of range");
-      return;
+      inst.operands[i].preind = 1;
+
+      if (*p == '+') p++;
+      else if (*p == '-') p++, inst.operands[i].negative = 1;
+
+      if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
+	{
+	  inst.operands[i].imm = reg;
+	  inst.operands[i].immisreg = 1;
+
+	  if (skip_past_comma (&p) == SUCCESS)
+	    if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
+	      return FAIL;
+	}
+      else
+	{
+	  if (inst.operands[i].negative)
+	    {
+	      inst.operands[i].negative = 0;
+	      p--;
+	    }
+	  if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+	    return FAIL;
+	}
     }
-  inst.instruction |= (expr.X_add_number + bias) << 16;
-  if (skip_past_comma (str) == FAIL)
+
+  if (skip_past_char (&p, ']') == FAIL)
     {
-      inst.error = BAD_ARGS;
-      return;
+      inst.error = _("']' expected");
+      return FAIL;
     }
 
-  /* Parse <Rm> field. */
-  if ((rm = reg_required_here (str, 0)) == FAIL)
+  if (skip_past_char (&p, '!') == SUCCESS)
+    inst.operands[i].writeback = 1;
+
+  else if (skip_past_comma (&p) == SUCCESS)
     {
-      inst.error = BAD_ARGS;
-      return;
+      if (skip_past_char (&p, '{') == SUCCESS)
+	{
+	  /* [Rn], {expr} - unindexed, with option */
+	  if (parse_immediate (&p, &inst.operands[i].imm,
+			       0, 255, TRUE) == FAIL)
+	    return FAIL;
+
+	  if (skip_past_char (&p, '}') == FAIL)
+	    {
+	      inst.error = _("'}' expected at end of 'option' field");
+	      return FAIL;
+	    }
+	  if (inst.operands[i].preind)
+	    {
+	      inst.error = _("cannot combine index with option");
+	      return FAIL;
+	    }
+	  *str = p;
+	  return SUCCESS;
+	}
+      else
+	{
+	  inst.operands[i].postind = 1;
+	  inst.operands[i].writeback = 1;
+
+	  if (inst.operands[i].preind)
+	    {
+	      inst.error = _("cannot combine pre- and post-indexing");
+	      return FAIL;
+	    }
+
+	  if (*p == '+') p++;
+	  else if (*p == '-') p++, inst.operands[i].negative = 1;
+
+	  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
+	    {
+	      inst.operands[i].imm = reg;
+	      inst.operands[i].immisreg = 1;
+
+	      if (skip_past_comma (&p) == SUCCESS)
+		if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
+		  return FAIL;
+	    }
+	  else
+	    {
+	      if (inst.operands[i].negative)
+		{
+		  inst.operands[i].negative = 0;
+		  p--;
+		}
+	      if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
+		return FAIL;
+	    }
+	}
     }
-  if (rm == REG_PC)
+
+  /* If at this point neither .preind nor .postind is set, we have a
+     bare [Rn]{!}, which is shorthand for [Rn,#0]{!}.  */
+  if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
     {
-      inst.error = BAD_PC;
-      return;
+      inst.operands[i].preind = 1;
+      inst.reloc.exp.X_op = O_constant;
+      inst.reloc.exp.X_add_number = 0;
     }
+  *str = p;
+  return SUCCESS;
 }
 
-/* ARM V6 srs (argument parse). */
+/* Miscellaneous. */
 
-static void
-do_srs (str)
-     char* str;
+/* Parse a PSR flag operand.  The value returned is FAIL on syntax error,
+   or a bitmask suitable to be or-ed into the ARM msr instruction.  */
+static int
+parse_psr (char **str)
 {
-  char *exclam;
-  skip_whitespace (str);
-  exclam = strchr (str, '!');
-  if (exclam)
-    *exclam = '\0';
-  do_cps_mode (&str);
-  if (exclam)
-    *exclam = '!';
-  if (*str == '!') 
+  char *p;
+  unsigned long psr_field;
+  const struct asm_psr *psr;
+  char *start;
+
+  /* CPSR's and SPSR's can now be lowercase.  This is just a convenience
+     feature for ease of use and backwards compatibility.  */
+  p = *str;
+  if (strncasecmp (p, "SPSR", 4) == 0)
+    psr_field = SPSR_BIT;
+  else if (strncasecmp (p, "CPSR", 4) == 0)
+    psr_field = 0;
+  else
     {
-      inst.instruction |= WRITE_BACK;
-      str++;
-    }
-  end_of_line (str);
-}
+      start = p;
+      do
+	p++;
+      while (ISALNUM (*p) || *p == '_');
 
-/* ARM V6 SMMUL (argument parse). */
+      psr = hash_find_n (arm_v7m_psr_hsh, start, p - start);
+      if (!psr)
+	return FAIL;
 
-static void
-do_smmul (str)
-     char* str;
-{
-  int rd, rm, rs;
-  
-  skip_whitespace (str);
-  if ((rd = reg_required_here (&str, 16)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rs = reg_required_here (&str, 8)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
+      *str = p;
+      return psr->field;
     }
 
-  if (rd == REG_PC 
-      || rm == REG_PC
-      || rs == REG_PC)
+  p += 4;
+  if (*p == '_')
     {
-      inst.error = BAD_PC;
-      return;
-    }
+      /* A suffix follows.  */
+      p++;
+      start = p;
 
-  end_of_line (str);
-  
-}
+      do
+	p++;
+      while (ISALNUM (*p) || *p == '_');
 
-/* ARM V6 SMLALD (argument parse). */
+      psr = hash_find_n (arm_psr_hsh, start, p - start);
+      if (!psr)
+	goto error;
 
-static void
-do_smlald (str)
-    char* str;
-{
-  int rdlo, rdhi, rm, rs;
-  skip_whitespace (str);
-  if ((rdlo = reg_required_here (&str, 12)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rdhi = reg_required_here (&str, 16)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rs = reg_required_here (&str, 8)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
+      psr_field |= psr->field;
     }
-
-  if (rdlo == REG_PC 
-      || rdhi == REG_PC 
-      || rm == REG_PC
-      || rs == REG_PC)
+  else
     {
-      inst.error = BAD_PC;
-      return;
+      if (ISALNUM (*p))
+	goto error;    /* Garbage after "[CS]PSR".  */
+
+      psr_field |= (PSR_c | PSR_f);
     }
+  *str = p;
+  return psr_field;
 
-  end_of_line (str);
+ error:
+  inst.error = _("flag for {c}psr instruction expected");
+  return FAIL;
 }
 
-/* ARM V6 SMLAD (argument parse).  Signed multiply accumulate dual. 
-   smlad{x}{<cond>} Rd, Rm, Rs, Rn */
+/* Parse the flags argument to CPSI[ED].  Returns FAIL on error, or a
+   value suitable for splatting into the AIF field of the instruction.	*/
 
-static void 
-do_smlad (str)
-     char *str;
+static int
+parse_cps_flags (char **str)
 {
-  int rd, rm, rs, rn;
-  
-  skip_whitespace (str);
-  if ((rd = reg_required_here (&str, 16)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rs = reg_required_here (&str, 8)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rn = reg_required_here (&str, 12)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  
-  if (rd == REG_PC 
-      || rn == REG_PC 
-      || rs == REG_PC
-      || rm == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
+  int val = 0;
+  int saw_a_flag = 0;
+  char *s = *str;
 
-  end_of_line (str);
-} 
+  for (;;)
+    switch (*s++)
+      {
+      case '\0': case ',':
+	goto done;
 
-/* ARM V6 SETEND (argument parse).  Sets the E bit in the CPSR while
-   preserving the other bits.
+      case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
+      case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
+      case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
 
-   setend <endian_specifier>, where <endian_specifier> is either 
-   BE or LE. */
+      default:
+	inst.error = _("unrecognized CPS flag");
+	return FAIL;
+      }
 
-static void 
-do_setend (str)
-     char *str;
-{
-  if (do_endian_specifier (str))
-    inst.instruction |= 0x200;
+ done:
+  if (saw_a_flag == 0)
+    {
+      inst.error = _("missing CPS flags");
+      return FAIL;
+    }
+
+  *str = s - 1;
+  return val;
 }
 
-/* Returns true if the endian-specifier indicates big-endianness.  */
+/* Parse an endian specifier ("BE" or "LE", case insensitive);
+   returns 0 for big-endian, 1 for little-endian, FAIL for an error.  */
 
 static int
-do_endian_specifier (str)
-     char *str;
+parse_endian_specifier (char **str)
 {
-  int big_endian = 0;
+  int little_endian;
+  char *s = *str;
 
-  skip_whitespace (str);
-  if (strlen (str) < 2)
-    inst.error = _("missing endian specifier");
-  else if (strncasecmp (str, "BE", 2) == 0)
+  if (strncasecmp (s, "BE", 2))
+    little_endian = 0;
+  else if (strncasecmp (s, "LE", 2))
+    little_endian = 1;
+  else
     {
-      str += 2;
-      big_endian = 1;
+      inst.error = _("valid endian specifiers are be or le");
+      return FAIL;
     }
-  else if (strncasecmp (str, "LE", 2) == 0)
-    str += 2;
-  else
-    inst.error = _("valid endian specifiers are be or le");
 
-  end_of_line (str);
+  if (ISALNUM (s[2]) || s[2] == '_')
+    {
+      inst.error = _("valid endian specifiers are be or le");
+      return FAIL;
+    }
 
-  return big_endian;
+  *str = s + 2;
+  return little_endian;
 }
 
-/* ARM V6 SXTH.
-
-   SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
-   Condition defaults to COND_ALWAYS.
-   Error if any register uses R15. */
+/* Parse a rotation specifier: ROR #0, #8, #16, #24.  *val receives a
+   value suitable for poking into the rotate field of an sxt or sxta
+   instruction, or FAIL on error.  */
 
-static void 
-do_sxth (str)
-     char *str;
+static int
+parse_ror (char **str)
 {
-  int rd, rm;
-  expressionS expr;
-  int rotation_clear_mask = 0xfffff3ff;
-  int rotation_eight_mask = 0x00000400;
-  int rotation_sixteen_mask = 0x00000800;
-  int rotation_twenty_four_mask = 0x00000c00;
-  
-  skip_whitespace (str);
-  if ((rd = reg_required_here (&str, 12)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  int rot;
+  char *s = *str;
 
-  else if (rd == REG_PC || rm == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
-  
-  /* Zero out the rotation field. */
-  inst.instruction &= rotation_clear_mask;
-  
-  /* Check for lack of optional rotation field. */
-  if (skip_past_comma (&str) == FAIL)
-    {
-      end_of_line (str);
-      return;
-    }
-  
-  /* Move past 'ROR'. */
-  skip_whitespace (str);
-  if (strncasecmp (str, "ROR", 3) == 0)
-    str+=3;
+  if (strncasecmp (s, "ROR", 3) == 0)
+    s += 3;
   else
     {
       inst.error = _("missing rotation field after comma");
-      return;
-    }
-  
-  /* Get the immediate constant. */
-  skip_whitespace (str);
-  if (is_immediate_prefix (* str))
-    str++;
-  else
-    {
-      inst.error = _("immediate expression expected");
-      return;
-    }
-  
-  if (my_get_expression (&expr, &str))
-    {
-      inst.error = _("bad expression");
-      return;
+      return FAIL;
     }
 
-  if (expr.X_op != O_constant)
+  if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
+    return FAIL;
+
+  switch (rot)
     {
-      inst.error = _("constant expression expected");
-      return;
+    case  0: *str = s; return 0x0;
+    case  8: *str = s; return 0x1;
+    case 16: *str = s; return 0x2;
+    case 24: *str = s; return 0x3;
+
+    default:
+      inst.error = _("rotation can only be 0, 8, 16, or 24");
+      return FAIL;
     }
-  
-  switch (expr.X_add_number) 
-    {
-    case 0:
-      /* Rotation field has already been zeroed. */
-      break;
-    case 8:
-      inst.instruction |= rotation_eight_mask;
-      break;
+}
 
-    case 16:
-      inst.instruction |= rotation_sixteen_mask;
-      break;
-      
-    case 24:
-      inst.instruction |= rotation_twenty_four_mask;
-      break;
+/* Parse a conditional code (from conds[] below).  The value returned is in the
+   range 0 .. 14, or FAIL.  */
+static int
+parse_cond (char **str)
+{
+  char *p, *q;
+  const struct asm_cond *c;
 
-    default:
-      inst.error = _("rotation can be 8, 16, 24 or 0 when field is ommited");
-      break;
+  p = q = *str;
+  while (ISALPHA (*q))
+    q++;
+
+  c = hash_find_n (arm_cond_hsh, p, q - p);
+  if (!c)
+    {
+      inst.error = _("condition required");
+      return FAIL;
     }
 
-  end_of_line (str);
-  
+  *str = q;
+  return c->value;
 }
 
-/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
-   extends it to 32-bits, and adds the result to a value in another
-   register.  You can specify a rotation by 0, 8, 16, or 24 bits
-   before extracting the 16-bit value.
-   SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
-   Condition defaults to COND_ALWAYS.
-   Error if any register uses R15. */
+/* Parse an option for a barrier instruction.  Returns the encoding for the
+   option, or FAIL.  */
+static int
+parse_barrier (char **str)
+{
+  char *p, *q;
+  const struct asm_barrier_opt *o;
 
-static void 
-do_sxtah (str)
-     char *str;
+  p = q = *str;
+  while (ISALPHA (*q))
+    q++;
+
+  o = hash_find_n (arm_barrier_opt_hsh, p, q - p);
+  if (!o)
+    return FAIL;
+
+  *str = q;
+  return o->value;
+}
+
+/* Parse the operands of a table branch instruction.  Similar to a memory
+   operand.  */
+static int
+parse_tb (char **str)
 {
-  int rd, rn, rm;
-  expressionS expr;
-  int rotation_clear_mask = 0xfffff3ff;
-  int rotation_eight_mask = 0x00000400;
-  int rotation_sixteen_mask = 0x00000800;
-  int rotation_twenty_four_mask = 0x00000c00;
-  
-  skip_whitespace (str);
-  if ((rd = reg_required_here (&str, 12)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rn = reg_required_here (&str, 16)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  char * p = *str;
+  int reg;
 
-  else if (rd == REG_PC || rn == REG_PC || rm == REG_PC)
+  if (skip_past_char (&p, '[') == FAIL)
     {
-      inst.error = BAD_PC;
-      return;
+      inst.error = _("'[' expected");
+      return FAIL;
     }
-  
-  /* Zero out the rotation field. */
-  inst.instruction &= rotation_clear_mask;
-  
-  /* Check for lack of optional rotation field. */
-  if (skip_past_comma (&str) == FAIL)
+
+  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
-      end_of_line (str);
-      return;
+      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+      return FAIL;
     }
-  
-  /* Move past 'ROR'. */
-  skip_whitespace (str);
-  if (strncasecmp (str, "ROR", 3) == 0)
-    str+=3;
-  else
+  inst.operands[0].reg = reg;
+
+  if (skip_past_comma (&p) == FAIL)
     {
-      inst.error = _("missing rotation field after comma");
-      return;
+      inst.error = _("',' expected");
+      return FAIL;
     }
   
-  /* Get the immediate constant. */
-  skip_whitespace (str);
-  if (is_immediate_prefix (* str))
-    str++;
-  else
+  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
     {
-      inst.error = _("immediate expression expected");
-      return;
+      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
+      return FAIL;
     }
-  
-  if (my_get_expression (&expr, &str))
+  inst.operands[0].imm = reg;
+
+  if (skip_past_comma (&p) == SUCCESS)
     {
-      inst.error = _("bad expression");
-      return;
+      if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
+	return FAIL;
+      if (inst.reloc.exp.X_add_number != 1)
+	{
+	  inst.error = _("invalid shift");
+	  return FAIL;
+	}
+      inst.operands[0].shifted = 1;
     }
 
-  if (expr.X_op != O_constant)
+  if (skip_past_char (&p, ']') == FAIL)
     {
-      inst.error = _("constant expression expected");
-      return;
+      inst.error = _("']' expected");
+      return FAIL;
     }
-  
-  switch (expr.X_add_number) 
-    {
-    case 0:
-      /* Rotation field has already been zeroed. */
-      break;
+  *str = p;
+  return SUCCESS;
+}
 
-    case 8:
-      inst.instruction |= rotation_eight_mask;
-      break;
+/* Matcher codes for parse_operands.  */
+enum operand_parse_code
+{
+  OP_stop,	/* end of line */
+
+  OP_RR,	/* ARM register */
+  OP_RRnpc,	/* ARM register, not r15 */
+  OP_RRnpcb,	/* ARM register, not r15, in square brackets */
+  OP_RRw,	/* ARM register, not r15, optional trailing ! */
+  OP_RCP,	/* Coprocessor number */
+  OP_RCN,	/* Coprocessor register */
+  OP_RF,	/* FPA register */
+  OP_RVS,	/* VFP single precision register */
+  OP_RVD,	/* VFP double precision register */
+  OP_RVC,	/* VFP control register */
+  OP_RMF,	/* Maverick F register */
+  OP_RMD,	/* Maverick D register */
+  OP_RMFX,	/* Maverick FX register */
+  OP_RMDX,	/* Maverick DX register */
+  OP_RMAX,	/* Maverick AX register */
+  OP_RMDS,	/* Maverick DSPSC register */
+  OP_RIWR,	/* iWMMXt wR register */
+  OP_RIWC,	/* iWMMXt wC register */
+  OP_RIWG,	/* iWMMXt wCG register */
+  OP_RXA,	/* XScale accumulator register */
+
+  OP_REGLST,	/* ARM register list */
+  OP_VRSLST,	/* VFP single-precision register list */
+  OP_VRDLST,	/* VFP double-precision register list */
+
+  OP_I7,	/* immediate value 0 .. 7 */
+  OP_I15,	/*		   0 .. 15 */
+  OP_I16,	/*		   1 .. 16 */
+  OP_I31,	/*		   0 .. 31 */
+  OP_I31w,	/*		   0 .. 31, optional trailing ! */
+  OP_I32,	/*		   1 .. 32 */
+  OP_I63s,	/*		 -64 .. 63 */
+  OP_I255,	/*		   0 .. 255 */
+  OP_Iffff,	/*		   0 .. 65535 */
+
+  OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
+  OP_I7b,	/*			       0 .. 7 */
+  OP_I15b,	/*			       0 .. 15 */
+  OP_I31b,	/*			       0 .. 31 */
+
+  OP_SH,	/* shifter operand */
+  OP_ADDR,	/* Memory address expression (any mode) */
+  OP_EXP,	/* arbitrary expression */
+  OP_EXPi,	/* same, with optional immediate prefix */
+  OP_EXPr,	/* same, with optional relocation suffix */
+
+  OP_CPSF,	/* CPS flags */
+  OP_ENDI,	/* Endianness specifier */
+  OP_PSR,	/* CPSR/SPSR mask for msr */
+  OP_COND,	/* conditional code */
+  OP_TB,	/* Table branch.  */
+
+  OP_RRnpc_I0,	/* ARM register or literal 0 */
+  OP_RR_EXr,	/* ARM register or expression with opt. reloc suff. */
+  OP_RR_EXi,	/* ARM register or expression with imm prefix */
+  OP_RF_IF,	/* FPA register or immediate */
+  OP_RIWR_RIWC, /* iWMMXt R or C reg */
+
+  /* Optional operands.	 */
+  OP_oI7b,	 /* immediate, prefix optional, 0 .. 7 */
+  OP_oI31b,	 /*				0 .. 31 */
+  OP_oIffffb,	 /*				0 .. 65535 */
+  OP_oI255c,	 /*	  curly-brace enclosed, 0 .. 255 */
+
+  OP_oRR,	 /* ARM register */
+  OP_oRRnpc,	 /* ARM register, not the PC */
+  OP_oSHll,	 /* LSL immediate */
+  OP_oSHar,	 /* ASR immediate */
+  OP_oSHllar,	 /* LSL or ASR immediate */
+  OP_oROR,	 /* ROR 0/8/16/24 */
+  OP_oBARRIER,	 /* Option argument for a barrier instruction.  */
+
+  OP_FIRST_OPTIONAL = OP_oI7b
+};
 
-    case 16:
-      inst.instruction |= rotation_sixteen_mask;
-      break;
-      
-    case 24:
-      inst.instruction |= rotation_twenty_four_mask;
-      break;
+/* Generic instruction operand parser.	This does no encoding and no
+   semantic validation; it merely squirrels values away in the inst
+   structure.  Returns SUCCESS or FAIL depending on whether the
+   specified grammar matched.  */
+static int
+parse_operands (char *str, const unsigned char *pattern)
+{
+  unsigned const char *upat = pattern;
+  char *backtrack_pos = 0;
+  const char *backtrack_error = 0;
+  int i, val, backtrack_index = 0;
+
+#define po_char_or_fail(chr) do {		\
+  if (skip_past_char (&str, chr) == FAIL)	\
+    goto bad_args;				\
+} while (0)
+
+#define po_reg_or_fail(regtype) do {			\
+  val = arm_reg_parse (&str, regtype);			\
+  if (val == FAIL)					\
+    {							\
+      inst.error = _(reg_expected_msgs[regtype]);	\
+      goto failure;					\
+    }							\
+  inst.operands[i].reg = val;				\
+  inst.operands[i].isreg = 1;				\
+} while (0)
+
+#define po_reg_or_goto(regtype, label) do {	\
+  val = arm_reg_parse (&str, regtype);		\
+  if (val == FAIL)				\
+    goto label;					\
+						\
+  inst.operands[i].reg = val;			\
+  inst.operands[i].isreg = 1;			\
+} while (0)
+
+#define po_imm_or_fail(min, max, popt) do {			\
+  if (parse_immediate (&str, &val, min, max, popt) == FAIL)	\
+    goto failure;						\
+  inst.operands[i].imm = val;					\
+} while (0)
+
+#define po_misc_or_fail(expr) do {		\
+  if (expr)					\
+    goto failure;				\
+} while (0)
 
-    default:
-      inst.error = _("rotation can be 8, 16, 24 or 0 when field is ommited");
-      break;
-    }
+  skip_whitespace (str);
 
-  end_of_line (str);
-  
-}
-   
+  for (i = 0; upat[i] != OP_stop; i++)
+    {
+      if (upat[i] >= OP_FIRST_OPTIONAL)
+	{
+	  /* Remember where we are in case we need to backtrack.  */
+	  assert (!backtrack_pos);
+	  backtrack_pos = str;
+	  backtrack_error = inst.error;
+	  backtrack_index = i;
+	}
+
+      if (i > 0)
+	po_char_or_fail (',');
+
+      switch (upat[i])
+	{
+	  /* Registers */
+	case OP_oRRnpc:
+	case OP_RRnpc:
+	case OP_oRR:
+	case OP_RR:    po_reg_or_fail (REG_TYPE_RN);	  break;
+	case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);	  break;
+	case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);	  break;
+	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
+	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
+	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
+	case OP_RVC:   po_reg_or_fail (REG_TYPE_VFC);	  break;
+	case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);	  break;
+	case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);	  break;
+	case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);	  break;
+	case OP_RMDX:  po_reg_or_fail (REG_TYPE_MVDX);	  break;
+	case OP_RMAX:  po_reg_or_fail (REG_TYPE_MVAX);	  break;
+	case OP_RMDS:  po_reg_or_fail (REG_TYPE_DSPSC);	  break;
+	case OP_RIWR:  po_reg_or_fail (REG_TYPE_MMXWR);	  break;
+	case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);	  break;
+	case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
+	case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
+
+	case OP_RRnpcb:
+	  po_char_or_fail ('[');
+	  po_reg_or_fail  (REG_TYPE_RN);
+	  po_char_or_fail (']');
+	  break;
 
-/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
-   word at the specified address and the following word
-   respectively. 
-   Unconditionally executed.
-   Error if Rn is R15.   
-*/
+	case OP_RRw:
+	  po_reg_or_fail (REG_TYPE_RN);
+	  if (skip_past_char (&str, '!') == SUCCESS)
+	    inst.operands[i].writeback = 1;
+	  break;
 
-static void
-do_rfe (str)
-     char *str;
-{
-  int rn;
+	  /* Immediates */
+	case OP_I7:	 po_imm_or_fail (  0,	   7, FALSE);	break;
+	case OP_I15:	 po_imm_or_fail (  0,	  15, FALSE);	break;
+	case OP_I16:	 po_imm_or_fail (  1,	  16, FALSE);	break;
+	case OP_I31:	 po_imm_or_fail (  0,	  31, FALSE);	break;
+	case OP_I32:	 po_imm_or_fail (  1,	  32, FALSE);	break;
+	case OP_I63s:	 po_imm_or_fail (-64,	  63, FALSE);	break;
+	case OP_I255:	 po_imm_or_fail (  0,	 255, FALSE);	break;
+	case OP_Iffff:	 po_imm_or_fail (  0, 0xffff, FALSE);	break;
+
+	case OP_I4b:	 po_imm_or_fail (  1,	   4, TRUE);	break;
+	case OP_oI7b:
+	case OP_I7b:	 po_imm_or_fail (  0,	   7, TRUE);	break;
+	case OP_I15b:	 po_imm_or_fail (  0,	  15, TRUE);	break;
+	case OP_oI31b:
+	case OP_I31b:	 po_imm_or_fail (  0,	  31, TRUE);	break;
+	case OP_oIffffb: po_imm_or_fail (  0, 0xffff, TRUE);	break;
+
+	  /* Immediate variants */
+	case OP_oI255c:
+	  po_char_or_fail ('{');
+	  po_imm_or_fail (0, 255, TRUE);
+	  po_char_or_fail ('}');
+	  break;
 
-  skip_whitespace (str);
-  
-  if ((rn = reg_required_here (&str, 16)) == FAIL)
-    return;
+	case OP_I31w:
+	  /* The expression parser chokes on a trailing !, so we have
+	     to find it first and zap it.  */
+	  {
+	    char *s = str;
+	    while (*s && *s != ',')
+	      s++;
+	    if (s[-1] == '!')
+	      {
+		s[-1] = '\0';
+		inst.operands[i].writeback = 1;
+	      }
+	    po_imm_or_fail (0, 31, TRUE);
+	    if (str == s - 1)
+	      str = s;
+	  }
+	  break;
 
-  if (rn == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
+	  /* Expressions */
+	case OP_EXPi:	EXPi:
+	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+					      GE_OPT_PREFIX));
+	  break;
 
-  skip_whitespace (str);
-  
-  if (*str == '!')
-    {
-      inst.instruction |= WRITE_BACK;
-      str++;
-    }
-  end_of_line (str);
-}
+	case OP_EXP:
+	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+					      GE_NO_PREFIX));
+	  break;
 
-/* ARM V6 REV (Byte Reverse Word) reverses the byte order in a 32-bit
-   register (argument parse).
-   REV{<cond>} Rd, Rm.
-   Condition defaults to COND_ALWAYS.
-   Error if Rd or Rm are R15. */ 
+	case OP_EXPr:	EXPr:
+	  po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
+					      GE_NO_PREFIX));
+	  if (inst.reloc.exp.X_op == O_symbol)
+	    {
+	      val = parse_reloc (&str);
+	      if (val == -1)
+		{
+		  inst.error = _("unrecognized relocation suffix");
+		  goto failure;
+		}
+	      else if (val != BFD_RELOC_UNUSED)
+		{
+		  inst.operands[i].imm = val;
+		  inst.operands[i].hasreloc = 1;
+		}
+	    }
+	  break;
 
-static void
-do_rev (str)
-     char* str;
-{
-  int rd, rm;
+	  /* Register or expression */
+	case OP_RR_EXr:	  po_reg_or_goto (REG_TYPE_RN, EXPr); break;
+	case OP_RR_EXi:	  po_reg_or_goto (REG_TYPE_RN, EXPi); break;
 
-  skip_whitespace (str);
+	  /* Register or immediate */
+	case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0);   break;
+	I0:		  po_imm_or_fail (0, 0, FALSE);	      break;
+
+	case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
+	IF:
+	  if (!is_immediate_prefix (*str))
+	    goto bad_args;
+	  str++;
+	  val = parse_fpa_immediate (&str);
+	  if (val == FAIL)
+	    goto failure;
+	  /* FPA immediates are encoded as registers 8-15.
+	     parse_fpa_immediate has already applied the offset.  */
+	  inst.operands[i].reg = val;
+	  inst.operands[i].isreg = 1;
+	  break;
+
+	  /* Two kinds of register */
+	case OP_RIWR_RIWC:
+	  {
+	    struct reg_entry *rege = arm_reg_parse_multi (&str);
+	    if (rege->type != REG_TYPE_MMXWR
+		&& rege->type != REG_TYPE_MMXWC
+		&& rege->type != REG_TYPE_MMXWCG)
+	      {
+		inst.error = _("iWMMXt data or control register expected");
+		goto failure;
+	      }
+	    inst.operands[i].reg = rege->number;
+	    inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
+	  }
+	  break;
 
-  if ((rd = reg_required_here (&str, 12)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    inst.error = BAD_ARGS;
+	  /* Misc */
+	case OP_CPSF:	 val = parse_cps_flags (&str);		break;
+	case OP_ENDI:	 val = parse_endian_specifier (&str);	break;
+	case OP_oROR:	 val = parse_ror (&str);		break;
+	case OP_PSR:	 val = parse_psr (&str);		break;
+	case OP_COND:	 val = parse_cond (&str);		break;
+	case OP_oBARRIER:val = parse_barrier (&str);		break;
 
-  else if (rd == REG_PC || rm == REG_PC)
-    inst.error = BAD_PC;
+	case OP_TB:
+	  po_misc_or_fail (parse_tb (&str));
+	  break;
 
-  else
-    end_of_line (str);
-}
+	  /* Register lists */
+	case OP_REGLST:
+	  val = parse_reg_list (&str);
+	  if (*str == '^')
+	    {
+	      inst.operands[1].writeback = 1;
+	      str++;
+	    }
+	  break;
 
-/* ARM V6 Perform Two Sixteen Bit Integer Additions. (argument parse).
-   QADD16{<cond>} <Rd>, <Rn>, <Rm>  
-   Condition defaults to COND_ALWAYS.
-   Error if Rd, Rn or Rm are R15.  */
+	case OP_VRSLST:
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
+	  break;
 
-static void
-do_qadd16 (str) 
-     char* str;
-{
-  int rd, rm, rn;
+	case OP_VRDLST:
+	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
+	  break;
 
-  skip_whitespace (str);
+	  /* Addressing modes */
+	case OP_ADDR:
+	  po_misc_or_fail (parse_address (&str, i));
+	  break;
 
-  if ((rd = reg_required_here (&str, 12)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rn = reg_required_here (&str, 16)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (rm = reg_required_here (&str, 0)) == FAIL)
-    inst.error = BAD_ARGS;
+	case OP_SH:
+	  po_misc_or_fail (parse_shifter_operand (&str, i));
+	  break;
 
-  else if (rd == REG_PC || rm == REG_PC || rn == REG_PC)
-    inst.error = BAD_PC;
+	case OP_oSHll:
+	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
+	  break;
 
-  else
-    end_of_line (str);
-}
+	case OP_oSHar:
+	  po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
+	  break;
 
-/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
-   PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>} 
-   Condition defaults to COND_ALWAYS.
-   Error if Rd, Rn or Rm are R15.  */
+	case OP_oSHllar:
+	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
+	  break;
 
-static void 
-do_pkhbt (str)
-     char* str;
-{
-  do_pkh_core (str, SHIFT_LSL_IMMEDIATE);
-}
+	default:
+	  as_fatal ("unhandled operand code %d", upat[i]);
+	}
 
-/* ARM V6 PKHTB (Argument Parse). */
+      /* Various value-based sanity checks and shared operations.  We
+	 do not signal immediate failures for the register constraints;
+	 this allows a syntax error to take precedence.	 */
+      switch (upat[i])
+	{
+	case OP_oRRnpc:
+	case OP_RRnpc:
+	case OP_RRnpcb:
+	case OP_RRw:
+	case OP_RRnpc_I0:
+	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
+	    inst.error = BAD_PC;
+	  break;
 
-static void 
-do_pkhtb (str)
-     char* str;
-{
-  do_pkh_core (str, SHIFT_ASR_IMMEDIATE);
-}
+	case OP_CPSF:
+	case OP_ENDI:
+	case OP_oROR:
+	case OP_PSR:
+	case OP_COND:
+	case OP_oBARRIER:
+	case OP_REGLST:
+	case OP_VRSLST:
+	case OP_VRDLST:
+	  if (val == FAIL)
+	    goto failure;
+	  inst.operands[i].imm = val;
+	  break;
 
-static void
-do_pkh_core (str, shift)
-     char* str;
-     int shift;
-{
-  int rd, rn, rm;
+	default:
+	  break;
+	}
 
-  skip_whitespace (str);
-  if (((rd = reg_required_here (&str, 12)) == FAIL)
-      || (skip_past_comma (&str) == FAIL)
-      || ((rn = reg_required_here (&str, 16)) == FAIL)
-      || (skip_past_comma (&str) == FAIL)
-      || ((rm = reg_required_here (&str, 0)) == FAIL))
-    {
+      /* If we get here, this operand was successfully parsed.	*/
+      inst.operands[i].present = 1;
+      continue;
+
+    bad_args:
       inst.error = BAD_ARGS;
-      return;
-    }
 
-  else if (rd == REG_PC || rn == REG_PC || rm == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
+    failure:
+      if (!backtrack_pos)
+	{
+	  /* The parse routine should already have set inst.error, but set a
+	     defaut here just in case.  */
+	  if (!inst.error)
+	    inst.error = _("syntax error");
+	  return FAIL;
+	}
 
-  /* Check for optional shift immediate constant. */
-  if (skip_past_comma (&str) == FAIL) 
-    {
-      if (shift == SHIFT_ASR_IMMEDIATE)
+      /* Do not backtrack over a trailing optional argument that
+	 absorbed some text.  We will only fail again, with the
+	 'garbage following instruction' error message, which is
+	 probably less helpful than the current one.  */
+      if (backtrack_index == i && backtrack_pos != str
+	  && upat[i+1] == OP_stop)
 	{
-	  /* If the shift specifier is ommited, turn the instruction
-	     into pkhbt rd, rm, rn.  First, switch the instruction
-	     code, and clear the rn and rm fields.  */
-	  inst.instruction &= 0xfff0f010;
-	  /* Now, re-encode the registers.  */
-	  inst.instruction |= (rm << 16) | rn;
+	  if (!inst.error)
+	    inst.error = _("syntax error");
+	  return FAIL;
 	}
-      return;
+
+      /* Try again, skipping the optional argument at backtrack_pos.  */
+      str = backtrack_pos;
+      inst.error = backtrack_error;
+      inst.operands[backtrack_index].present = 0;
+      i = backtrack_index;
+      backtrack_pos = 0;
     }
 
-  decode_shift (&str, shift);
+  /* Check that we have parsed all the arguments.  */
+  if (*str != '\0' && !inst.error)
+    inst.error = _("garbage following instruction");
+
+  return inst.error ? FAIL : SUCCESS;
 }
 
-/* ARM V6 Load Register Exclusive instruction (argument parse).
-   LDREX{<cond>} <Rd, [<Rn>]
-   Condition defaults to COND_ALWAYS.
-   Error if Rd or Rn are R15. 
-   See ARMARMv6 A4.1.27: LDREX. */
+#undef po_char_or_fail
+#undef po_reg_or_fail
+#undef po_reg_or_goto
+#undef po_imm_or_fail
+
+/* Shorthand macro for instruction encoding functions issuing errors.  */
+#define constraint(expr, err) do {		\
+  if (expr)					\
+    {						\
+      inst.error = err;				\
+      return;					\
+    }						\
+} while (0)
 
+/* Functions for operand encoding.  ARM, then Thumb.  */
 
-static void
-do_ldrex (str)
-     char * str;
+#define rotate_left(v, n) (v << n | v >> (32 - n))
+
+/* If VAL can be encoded in the immediate field of an ARM instruction,
+   return the encoded form.  Otherwise, return FAIL.  */
+
+static unsigned int
+encode_arm_immediate (unsigned int val)
 {
-  int rd, rn;
+  unsigned int a, i;
 
-  skip_whitespace (str);
+  for (i = 0; i < 32; i += 2)
+    if ((a = rotate_left (val, i)) <= 0xff)
+      return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
 
-  /* Parse Rd. */
-  if (((rd = reg_required_here (&str, 12)) == FAIL)
-      || (skip_past_comma (&str) == FAIL))
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  else if (rd == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
-  skip_whitespace (str);  
+  return FAIL;
+}
 
-  /* Skip past '['. */
-  if ((strlen (str) >= 1) 
-      &&strncmp (str, "[", 1) == 0)
-    str+=1;
-  skip_whitespace (str);  
+/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
+   return the encoded form.  Otherwise, return FAIL.  */
+static unsigned int
+encode_thumb32_immediate (unsigned int val)
+{
+  unsigned int a, i;
 
-  /* Parse Rn. */
-  if ((rn = reg_required_here (&str, 16)) == FAIL)
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
-  else if (rn == REG_PC)
+  if (val <= 0xff)
+    return val;
+
+  for (i = 1; i <= 24; i++)
     {
-      inst.error = BAD_PC;
-      return;
+      a = val >> i;
+      if ((val & ~(0xff << i)) == 0)
+	return ((val >> i) & 0x7f) | ((32 - i) << 7);
     }
-  skip_whitespace (str);  
 
-  /* Skip past ']'. */
-  if ((strlen (str) >= 1) 
-      && strncmp (str, "]", 1) == 0)
-    str+=1;
-  
-  end_of_line (str);
-}
+  a = val & 0xff;
+  if (val == ((a << 16) | a))
+    return 0x100 | a;
+  if (val == ((a << 24) | (a << 16) | (a << 8) | a))
+    return 0x300 | a;
 
-/* ARM V6 change processor state instruction (argument parse)
-      CPS, CPSIE, CSPID . */
+  a = val & 0xff00;
+  if (val == ((a << 16) | a))
+    return 0x200 | (a >> 8);
 
-static void
-do_cps (str)
-     char * str;
-{
-  do_cps_mode (&str);
-  end_of_line (str);
+  return FAIL;
 }
+/* Encode a VFP SP register number into inst.instruction.  */
 
 static void
-do_cpsi (str)
-     char * str;
+encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
 {
-  do_cps_flags (&str, /*thumb_p=*/0);
-
-  if (skip_past_comma (&str) == SUCCESS)
+  switch (pos)
     {
-      skip_whitespace (str);
-      do_cps_mode (&str);
-    }
-  end_of_line (str);
-}
+    case VFP_REG_Sd:
+      inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
+      break;
 
-static void
-do_cps_mode (str)
-     char **str;
-{
-  expressionS expr;
+    case VFP_REG_Sn:
+      inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
+      break;
 
-  skip_whitespace (*str);
+    case VFP_REG_Sm:
+      inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
+      break;
 
-  if (! is_immediate_prefix (**str))
-    {
-      inst.error = _("immediate expression expected");
-      return;
+    default:
+      abort ();
     }
+}
 
-  (*str)++; /* Strip off the immediate signifier. */
-  if (my_get_expression (&expr, str))
+/* Encode a <shift> in an ARM-format instruction.  The immediate,
+   if any, is handled by md_apply_fix.	 */
+static void
+encode_arm_shift (int i)
+{
+  if (inst.operands[i].shift_kind == SHIFT_RRX)
+    inst.instruction |= SHIFT_ROR << 5;
+  else
     {
-      inst.error = _("bad expression");
-      return;
+      inst.instruction |= inst.operands[i].shift_kind << 5;
+      if (inst.operands[i].immisreg)
+	{
+	  inst.instruction |= SHIFT_BY_REG;
+	  inst.instruction |= inst.operands[i].imm << 8;
+	}
+      else
+	inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
     }
+}
 
-  if (expr.X_op != O_constant)
-    {
-      inst.error = _("constant expression expected");
-      return;
-    }
-  
-  /* The mode is a 5 bit field.  Valid values are 0-31. */
-  if (((unsigned) expr.X_add_number) > 31
-      || (inst.reloc.exp.X_add_number) < 0)
+static void
+encode_arm_shifter_operand (int i)
+{
+  if (inst.operands[i].isreg)
     {
-      inst.error = _("invalid constant");
-      return;
+      inst.instruction |= inst.operands[i].reg;
+      encode_arm_shift (i);
     }
-  
-  inst.instruction |= expr.X_add_number;
+  else
+    inst.instruction |= INST_IMMEDIATE;
 }
 
+/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3.  */
 static void
-do_cps_flags (str, thumb_p)
-     char **str;
-     int    thumb_p;
+encode_arm_addr_mode_common (int i, bfd_boolean is_t)
 {
-  struct cps_flag { 
-    char character;
-    unsigned long arm_value;
-    unsigned long thumb_value;
-  };
-  static struct cps_flag flag_table[] = {
-    {'a', 0x100, 0x4 },
-    {'i', 0x080, 0x2 },
-    {'f', 0x040, 0x1 }
-  };
-
-  int saw_a_flag = 0;
+  assert (inst.operands[i].isreg);
+  inst.instruction |= inst.operands[i].reg << 16;
 
-  skip_whitespace (*str);
-
-  /* Get the a, f and i flags. */
-  while (**str && **str != ',')
+  if (inst.operands[i].preind)
     {
-      struct cps_flag *p;
-      struct cps_flag *q = flag_table + sizeof (flag_table)/sizeof (*p);
-      for (p = flag_table; p < q; ++p)
-	if (strncasecmp (*str, &p->character, 1) == 0)
-	  {
-	    inst.instruction |= (thumb_p ? p->thumb_value : p->arm_value);
-	    saw_a_flag = 1;
-	    break;
-	  }
-      if (p == q)
+      if (is_t)
 	{
-	  inst.error = _("unrecognized flag");
+	  inst.error = _("instruction does not accept preindexed addressing");
 	  return;
 	}
-      (*str)++;
-    }
-  if (!saw_a_flag) 
-    inst.error = _("no 'a', 'i', or 'f' flags for 'cps'");
-}
-
-/* THUMB V5 breakpoint instruction (argument parse)
-	BKPT <immed_8>.  */
-
-static void
-do_t_bkpt (str)
-     char * str;
-{
-  expressionS expr;
-  unsigned long number;
-
-  skip_whitespace (str);
-
-  /* Allow optional leading '#'.  */
-  if (is_immediate_prefix (*str))
-    str ++;
+      inst.instruction |= PRE_INDEX;
+      if (inst.operands[i].writeback)
+	inst.instruction |= WRITE_BACK;
 
-  memset (& expr, '\0', sizeof (expr));
-  if (my_get_expression (& expr, & str)
-      || (expr.X_op != O_constant
-	  /* As a convenience we allow 'bkpt' without an operand.  */
-	  && expr.X_op != O_absent))
+    }
+  else if (inst.operands[i].postind)
     {
-      inst.error = _("bad expression");
-      return;
+      assert (inst.operands[i].writeback);
+      if (is_t)
+	inst.instruction |= WRITE_BACK;
     }
-
-  number = expr.X_add_number;
-
-  /* Check it fits an 8 bit unsigned.  */
-  if (number != (number & 0xff))
+  else /* unindexed - only for coprocessor */
     {
-      inst.error = _("immediate value out of range");
+      inst.error = _("instruction does not accept unindexed addressing");
       return;
     }
 
-  inst.instruction |= number;
-
-  end_of_line (str);
+  if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
+      && (((inst.instruction & 0x000f0000) >> 16)
+	  == ((inst.instruction & 0x0000f000) >> 12)))
+    as_warn ((inst.instruction & LOAD_BIT)
+	     ? _("destination register same as write-back base")
+	     : _("source register same as write-back base"));
 }
 
-/* ARM V5 branch-link-exchange (argument parse) for BLX(1) only.
-   Expects inst.instruction is set for BLX(1).
-   Note: this is cloned from do_branch, and the reloc changed to be a
-	new one that can cope with setting one extra bit (the H bit).  */
-
+/* inst.operands[i] was set up by parse_address.  Encode it into an
+   ARM-format mode 2 load or store instruction.	 If is_t is true,
+   reject forms that cannot be used with a T instruction (i.e. not
+   post-indexed).  */
 static void
-do_branch25 (str)
-     char *        str;
+encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
 {
-  if (my_get_expression (& inst.reloc.exp, & str))
-    return;
+  encode_arm_addr_mode_common (i, is_t);
 
-#ifdef OBJ_ELF
-  {
-    char * save_in;
-
-    /* ScottB: February 5, 1998 */
-    /* Check to see of PLT32 reloc required for the instruction.  */
-
-    /* arm_parse_reloc() works on input_line_pointer.
-       We actually want to parse the operands to the branch instruction
-       passed in 'str'.  Save the input pointer and restore it later.  */
-    save_in = input_line_pointer;
-    input_line_pointer = str;
-
-    if (inst.reloc.exp.X_op == O_symbol
-	&& *str == '('
-	&& arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
-      {
-	inst.reloc.type   = BFD_RELOC_ARM_PLT32;
-	inst.reloc.pc_rel = 0;
-	/* Modify str to point to after parsed operands, otherwise
-	   end_of_line() will complain about the (PLT) left in str.  */
-	str = input_line_pointer;
-      }
-    else
-      {
-	inst.reloc.type   = BFD_RELOC_ARM_PCREL_BLX;
-	inst.reloc.pc_rel = 1;
-      }
-
-    input_line_pointer = save_in;
-  }
-#else
-  inst.reloc.type   = BFD_RELOC_ARM_PCREL_BLX;
-  inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF */
-
-  end_of_line (str);
+  if (inst.operands[i].immisreg)
+    {
+      inst.instruction |= INST_IMMEDIATE;  /* yes, this is backwards */
+      inst.instruction |= inst.operands[i].imm;
+      if (!inst.operands[i].negative)
+	inst.instruction |= INDEX_UP;
+      if (inst.operands[i].shifted)
+	{
+	  if (inst.operands[i].shift_kind == SHIFT_RRX)
+	    inst.instruction |= SHIFT_ROR << 5;
+	  else
+	    {
+	      inst.instruction |= inst.operands[i].shift_kind << 5;
+	      inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+	    }
+	}
+    }
+  else /* immediate offset in inst.reloc */
+    {
+      if (inst.reloc.type == BFD_RELOC_UNUSED)
+	inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
+    }
 }
 
-/* ARM V5 branch-link-exchange instruction (argument parse)
-     BLX <target_addr>		ie BLX(1)
-     BLX{<condition>} <Rm>	ie BLX(2)
-   Unfortunately, there are two different opcodes for this mnemonic.
-   So, the insns[].value is not used, and the code here zaps values
-	into inst.instruction.
-   Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
-
+/* inst.operands[i] was set up by parse_address.  Encode it into an
+   ARM-format mode 3 load or store instruction.	 Reject forms that
+   cannot be used with such instructions.  If is_t is true, reject
+   forms that cannot be used with a T instruction (i.e. not
+   post-indexed).  */
 static void
-do_blx (str)
-     char *        str;
+encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
 {
-  char * mystr = str;
-  int rm;
-
-  skip_whitespace (mystr);
-  rm = reg_required_here (& mystr, 0);
+  if (inst.operands[i].immisreg && inst.operands[i].shifted)
+    {
+      inst.error = _("instruction does not accept scaled register index");
+      return;
+    }
 
-  /* The above may set inst.error.  Ignore his opinion.  */
-  inst.error = 0;
+  encode_arm_addr_mode_common (i, is_t);
 
-  if (rm != FAIL)
+  if (inst.operands[i].immisreg)
     {
-      /* Arg is a register.
-	 Use the condition code our caller put in inst.instruction.
-	 Pass ourselves off as a BX with a funny opcode.  */
-      inst.instruction |= 0x012fff30;
-      do_bx (str);
+      inst.instruction |= inst.operands[i].imm;
+      if (!inst.operands[i].negative)
+	inst.instruction |= INDEX_UP;
     }
-  else
+  else /* immediate offset in inst.reloc */
     {
-      /* This must be is BLX <target address>, no condition allowed.  */
-      if (inst.instruction != COND_ALWAYS)
-	{
-	  inst.error = BAD_COND;
-	  return;
-	}
-
-      inst.instruction = 0xfafffffe;
-
-      /* Process like a B/BL, but with a different reloc.
-	 Note that B/BL expecte fffffe, not 0, offset in the opcode table.  */
-      do_branch25 (str);
+      inst.instruction |= HWOFFSET_IMM;
+      if (inst.reloc.type == BFD_RELOC_UNUSED)
+	inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
     }
 }
 
-/* ARM V5 Thumb BLX (argument parse)
-	BLX <target_addr>	which is BLX(1)
-	BLX <Rm>		which is BLX(2)
-   Unfortunately, there are two different opcodes for this mnemonic.
-   So, the tinsns[].value is not used, and the code here zaps values
-	into inst.instruction.	*/
+/* inst.operands[i] was set up by parse_address.  Encode it into an
+   ARM-format instruction.  Reject all forms which cannot be encoded
+   into a coprocessor load/store instruction.  If wb_ok is false,
+   reject use of writeback; if unind_ok is false, reject use of
+   unindexed addressing.  If reloc_override is not 0, use it instead
+   of BFD_ARM_CP_OFF_IMM.  */
 
-static void
-do_t_blx (str)
-     char * str;
+static int
+encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
 {
-  char * mystr = str;
-  int rm;
+  inst.instruction |= inst.operands[i].reg << 16;
 
-  skip_whitespace (mystr);
-  inst.instruction = 0x4780;
+  assert (!(inst.operands[i].preind && inst.operands[i].postind));
 
-  /* Note that this call is to the ARM register recognizer.  BLX(2)
-     uses the ARM register space, not the Thumb one, so a call to
-     thumb_reg() would be wrong.  */
-  rm = reg_required_here (& mystr, 3);
-  inst.error = 0;
-
-  if (rm != FAIL)
+  if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
     {
-      /* It's BLX(2).  The .instruction was zapped with rm & is final.  */
-      inst.size = 2;
+      assert (!inst.operands[i].writeback);
+      if (!unind_ok)
+	{
+	  inst.error = _("instruction does not support unindexed addressing");
+	  return FAIL;
+	}
+      inst.instruction |= inst.operands[i].imm;
+      inst.instruction |= INDEX_UP;
+      return SUCCESS;
     }
-  else
-    {
-      /* No ARM register.  This must be BLX(1).  Change the .instruction.  */
-      inst.instruction = 0xf7ffeffe;
-      inst.size = 4;
 
-      if (my_get_expression (& inst.reloc.exp, & mystr))
-	return;
+  if (inst.operands[i].preind)
+    inst.instruction |= PRE_INDEX;
 
-      inst.reloc.type   = BFD_RELOC_THUMB_PCREL_BLX;
-      inst.reloc.pc_rel = 1;
+  if (inst.operands[i].writeback)
+    {
+      if (inst.operands[i].reg == REG_PC)
+	{
+	  inst.error = _("pc may not be used with write-back");
+	  return FAIL;
+	}
+      if (!wb_ok)
+	{
+	  inst.error = _("instruction does not support writeback");
+	  return FAIL;
+	}
+      inst.instruction |= WRITE_BACK;
     }
 
-  end_of_line (mystr);
+  if (reloc_override)
+    inst.reloc.type = reloc_override;
+  else if (thumb_mode)
+    inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
+  else
+    inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
+  return SUCCESS;
 }
 
-/* ARM V5 breakpoint instruction (argument parse)
-     BKPT <16 bit unsigned immediate>
-     Instruction is not conditional.
-	The bit pattern given in insns[] has the COND_ALWAYS condition,
-	and it is an error if the caller tried to override that.  */
-
-static void
-do_bkpt (str)
-     char *        str;
-{
-  expressionS expr;
-  unsigned long number;
+/* inst.reloc.exp describes an "=expr" load pseudo-operation.
+   Determine whether it can be performed with a move instruction; if
+   it can, convert inst.instruction to that move instruction and
+   return 1; if it can't, convert inst.instruction to a literal-pool
+   load and return 0.  If this is not a valid thing to do in the
+   current context, set inst.error and return 1.
 
-  skip_whitespace (str);
+   inst.operands[i] describes the destination register.	 */
 
-  /* Allow optional leading '#'.  */
-  if (is_immediate_prefix (* str))
-    str++;
+static int
+move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
+{
+  unsigned long tbit;
 
-  memset (& expr, '\0', sizeof (expr));
+  if (thumb_p)
+    tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
+  else
+    tbit = LOAD_BIT;
 
-  if (my_get_expression (& expr, & str)
-      || (expr.X_op != O_constant
-	  /* As a convenience we allow 'bkpt' without an operand.  */
-	  && expr.X_op != O_absent))
+  if ((inst.instruction & tbit) == 0)
     {
-      inst.error = _("bad expression");
-      return;
+      inst.error = _("invalid pseudo operation");
+      return 1;
     }
-
-  number = expr.X_add_number;
-
-  /* Check it fits a 16 bit unsigned.  */
-  if (number != (number & 0xffff))
+  if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
     {
-      inst.error = _("immediate value out of range");
-      return;
+      inst.error = _("constant expression expected");
+      return 1;
     }
+  if (inst.reloc.exp.X_op == O_constant)
+    {
+      if (thumb_p)
+	{
+	  if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
+	    {
+	      /* This can be done with a mov(1) instruction.  */
+	      inst.instruction	= T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
+	      inst.instruction |= inst.reloc.exp.X_add_number;
+	      return 1;
+	    }
+	}
+      else
+	{
+	  int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
+	  if (value != FAIL)
+	    {
+	      /* This can be done with a mov instruction.  */
+	      inst.instruction &= LITERAL_MASK;
+	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
+	      inst.instruction |= value & 0xfff;
+	      return 1;
+	    }
 
-  /* Top 12 of 16 bits to bits 19:8.  */
-  inst.instruction |= (number & 0xfff0) << 4;
-
-  /* Bottom 4 of 16 bits to bits 3:0.  */
-  inst.instruction |= number & 0xf;
+	  value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
+	  if (value != FAIL)
+	    {
+	      /* This can be done with a mvn instruction.  */
+	      inst.instruction &= LITERAL_MASK;
+	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
+	      inst.instruction |= value & 0xfff;
+	      return 1;
+	    }
+	}
+    }
 
-  end_of_line (str);
+  if (add_to_lit_pool () == FAIL)
+    {
+      inst.error = _("literal pool insertion failed");
+      return 1;
+    }
+  inst.operands[1].reg = REG_PC;
+  inst.operands[1].isreg = 1;
+  inst.operands[1].preind = 1;
+  inst.reloc.pc_rel = 1;
+  inst.reloc.type = (thumb_p
+		     ? BFD_RELOC_ARM_THUMB_OFFSET
+		     : (mode_3
+			? BFD_RELOC_ARM_HWLITERAL
+			: BFD_RELOC_ARM_LITERAL));
+  return 0;
 }
 
-/* THUMB CPS instruction (argument parse).  */
+/* Functions for instruction encoding, sorted by subarchitecture.
+   First some generics; their names are taken from the conventional
+   bit positions for register arguments in ARM format instructions.  */
 
 static void
-do_t_cps (str)
-     char *str;
+do_noargs (void)
 {
-  do_cps_flags (&str, /*thumb_p=*/1);
-  end_of_line (str);
 }
 
-/* THUMB CPY instruction (argument parse).  */
-
 static void
-do_t_cpy (str)
-     char *str;
+do_rd (void)
 {
-  thumb_mov_compare (str, THUMB_CPY);
+  inst.instruction |= inst.operands[0].reg << 12;
 }
 
-/* THUMB SETEND instruction (argument parse).  */
-
 static void
-do_t_setend (str)
-     char *str;
+do_rd_rm (void)
 {
-  if (do_endian_specifier (str))
-    inst.instruction |= 0x8;
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
 }
 
-static unsigned long check_iwmmxt_insn PARAMS ((char *, enum iwmmxt_insn_type, int));
-
-/* Parse INSN_TYPE insn STR having a possible IMMEDIATE_SIZE immediate.  */
-
-static unsigned long
-check_iwmmxt_insn (str, insn_type, immediate_size)
-     char * str;
-     enum iwmmxt_insn_type insn_type;
-     int immediate_size;
+static void
+do_rd_rn (void)
 {
-  int reg = 0;
-  const char *  inst_error;
-  expressionS expr;
-  unsigned long number;
-
-  inst_error = inst.error;
-  if (!inst.error)
-    inst.error = BAD_ARGS;
-  skip_whitespace (str);
-
-  switch (insn_type)
-    {
-    case check_rd:
-      if ((reg = reg_required_here (&str, 12)) == FAIL)
-	return FAIL;
-      break;
-      
-    case check_wr:
-       if ((wreg_required_here (&str, 0, IWMMXT_REG_WR)) == FAIL)
-	 return FAIL;
-       break;
-       
-    case check_wrwr:
-      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_wrwrwr:
-      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_wrwrwcg:
-      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 0, IWMMXT_REG_WCG) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tbcst:
-      if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 12) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmovmsk:
-      if ((reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmia:
-      if ((wreg_required_here (&str, 5, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 0) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 12) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmcrr:
-      if ((wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 16) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmrrc:
-      if ((reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 16) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmcr:
-      if ((wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 12) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tmrc:
-      if ((reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WC) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_tinsr:
-      if ((wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_textrc:
-      if ((reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_waligni:
-      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 0, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_textrm:
-      if ((reg_required_here (&str, 12) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL))
-	return FAIL;
-      break;
-      
-    case check_wshufh:
-      if ((wreg_required_here (&str, 12, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL
-	   || wreg_required_here (&str, 16, IWMMXT_REG_WR) == FAIL
-	   || skip_past_comma (&str) == FAIL))
-	return FAIL;
-      break;
-    }
-  
-  if (immediate_size == 0)
-    {
-      end_of_line (str);
-      inst.error = inst_error;
-      return reg;
-    }
-  else
-    {
-      skip_whitespace (str);      
-  
-      /* Allow optional leading '#'. */
-      if (is_immediate_prefix (* str))
-        str++;
-
-      memset (& expr, '\0', sizeof (expr));
-  
-      if (my_get_expression (& expr, & str) || (expr.X_op != O_constant))
-        {
-          inst.error = _("bad or missing expression");
-          return FAIL;
-        }
-  
-      number = expr.X_add_number;
-  
-      if (number != (number & immediate_size))
-        {
-          inst.error = _("immediate value out of range");
-          return FAIL;
-        }
-      end_of_line (str);
-      inst.error = inst_error;
-      return number;
-    }
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
 }
 
 static void
-do_iwmmxt_byte_addr (str)
-     char * str;
+do_rn_rd (void)
 {
-  int op = (inst.instruction & 0x300) >> 8;
-  int reg;
-
-  inst.instruction &= ~0x300;
-  inst.instruction |= (op & 1) << 22 | (op & 2) << 7;  
-
-  skip_whitespace (str);
-
-  if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || cp_byte_address_required_here (&str) == FAIL)
-    {
-      if (! inst.error)
-        inst.error = BAD_ARGS;
-    }
-  else
-    end_of_line (str);
-
-  if (wc_register (reg))
-    {
-      as_bad (_("non-word size not supported with control register"));
-      inst.instruction |=  0xf0000100;
-      inst.instruction &= ~0x00400000;
-    }
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg << 12;
 }
 
 static void
-do_iwmmxt_tandc (str)
-     char * str;
+do_rd_rm_rn (void)
 {
-  int reg;
-
-  reg = check_iwmmxt_insn (str, check_rd, 0);
-
-  if (reg != REG_PC && !inst.error)
-    inst.error = _("only r15 allowed here");
+  unsigned Rn = inst.operands[2].reg;
+  /* Enforce resutrictions on SWP instruction.  */
+  if ((inst.instruction & 0x0fbfffff) == 0x01000090)
+    constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
+		_("Rn must not overlap other operands"));
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= Rn << 16;
 }
 
 static void
-do_iwmmxt_tbcst (str)
-     char * str;
+do_rd_rn_rm (void)
 {
-  check_iwmmxt_insn (str, check_tbcst, 0);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
 }
 
 static void
-do_iwmmxt_textrc (str)
-     char * str;
+do_rm_rd_rn (void)
 {
-  unsigned long number;
-
-  if ((number = check_iwmmxt_insn (str, check_textrc, 7)) == (unsigned long) FAIL)
-    return;
-
-  inst.instruction |= number & 0x7;
+  inst.instruction |= inst.operands[0].reg;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
 }
 
 static void
-do_iwmmxt_textrm (str)
-     char * str;
+do_imm0 (void)
 {
-  unsigned long number;
-
-  if ((number = check_iwmmxt_insn (str, check_textrm, 7)) == (unsigned long) FAIL)
-    return;
-
-  inst.instruction |= number & 0x7;
+  inst.instruction |= inst.operands[0].imm;
 }
 
 static void
-do_iwmmxt_tinsr (str)
-     char * str;
+do_rd_cpaddr (void)
 {
-  unsigned long number;
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_cp_address (1, TRUE, TRUE, 0);
+}
 
-  if ((number = check_iwmmxt_insn (str, check_tinsr, 7)) == (unsigned long) FAIL)
-    return;
+/* ARM instructions, in alphabetical order by function name (except
+   that wrapper functions appear immediately after the function they
+   wrap).  */
 
-  inst.instruction |= number & 0x7;
-}
+/* This is a pseudo-op of the form "adr rd, label" to be converted
+   into a relative address of the form "add rd, pc, #label-.-8".  */
 
 static void
-do_iwmmxt_tmcr (str)
-     char * str;
+do_adr (void)
 {
-  check_iwmmxt_insn (str, check_tmcr, 0);
-}
+  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
 
-static void
-do_iwmmxt_tmcrr (str)
-     char * str;
-{
-  check_iwmmxt_insn (str, check_tmcrr, 0);
+  /* Frag hacking will turn this into a sub instruction if the offset turns
+     out to be negative.  */
+  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+  inst.reloc.pc_rel = 1;
+  inst.reloc.exp.X_add_number -= 8;
 }
 
-static void
-do_iwmmxt_tmia (str)
-     char * str;
-{
-  check_iwmmxt_insn (str, check_tmia, 0);
-}
+/* This is a pseudo-op of the form "adrl rd, label" to be converted
+   into a relative address of the form:
+   add rd, pc, #low(label-.-8)"
+   add rd, rd, #high(label-.-8)"  */
 
 static void
-do_iwmmxt_tmovmsk (str)
-     char * str;
+do_adrl (void)
 {
-  check_iwmmxt_insn (str, check_tmovmsk, 0);
+  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
+
+  /* Frag hacking will turn this into a sub instruction if the offset turns
+     out to be negative.  */
+  inst.reloc.type	       = BFD_RELOC_ARM_ADRL_IMMEDIATE;
+  inst.reloc.pc_rel	       = 1;
+  inst.size		       = INSN_SIZE * 2;
+  inst.reloc.exp.X_add_number -= 8;
 }
 
 static void
-do_iwmmxt_tmrc (str)
-     char * str;
+do_arit (void)
 {
-  check_iwmmxt_insn (str, check_tmrc, 0);
+  if (!inst.operands[1].present)
+    inst.operands[1].reg = inst.operands[0].reg;
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  encode_arm_shifter_operand (2);
 }
 
 static void
-do_iwmmxt_tmrrc (str)
-     char * str;
+do_barrier (void)
 {
-  check_iwmmxt_insn (str, check_tmrrc, 0);
+  if (inst.operands[0].present)
+    {
+      constraint ((inst.instruction & 0xf0) != 0x40
+		  && inst.operands[0].imm != 0xf,
+		  "bad barrier type");
+      inst.instruction |= inst.operands[0].imm;
+    }
+  else
+    inst.instruction |= 0xf;
 }
 
 static void
-do_iwmmxt_torc (str)
-     char * str;
+do_bfc (void)
 {
-  check_iwmmxt_insn (str, check_rd, 0);
+  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
+  constraint (msb > 32, _("bit-field extends past end of register"));
+  /* The instruction encoding stores the LSB and MSB,
+     not the LSB and width.  */
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].imm << 7;
+  inst.instruction |= (msb - 1) << 16;
 }
 
 static void
-do_iwmmxt_waligni (str)
-     char * str;
+do_bfi (void)
 {
-  unsigned long number;
+  unsigned int msb;
 
-  if ((number = check_iwmmxt_insn (str, check_waligni, 7)) == (unsigned long) FAIL)
-    return;
+  /* #0 in second position is alternative syntax for bfc, which is
+     the same instruction but with REG_PC in the Rm field.  */
+  if (!inst.operands[1].isreg)
+    inst.operands[1].reg = REG_PC;
 
-  inst.instruction |= ((number & 0x7) << 20);
+  msb = inst.operands[2].imm + inst.operands[3].imm;
+  constraint (msb > 32, _("bit-field extends past end of register"));
+  /* The instruction encoding stores the LSB and MSB,
+     not the LSB and width.  */
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].imm << 7;
+  inst.instruction |= (msb - 1) << 16;
 }
 
 static void
-do_iwmmxt_wmov (str)
-     char * str;
+do_bfx (void)
 {
-  if (check_iwmmxt_insn (str, check_wrwr, 0) == (unsigned long) FAIL)
-    return;
-  
-  inst.instruction |= ((inst.instruction >> 16) & 0xf);
+  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
+	      _("bit-field extends past end of register"));
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].imm << 7;
+  inst.instruction |= (inst.operands[3].imm - 1) << 16;
 }
 
+/* ARM V5 breakpoint instruction (argument parse)
+     BKPT <16 bit unsigned immediate>
+     Instruction is not conditional.
+	The bit pattern given in insns[] has the COND_ALWAYS condition,
+	and it is an error if the caller tried to override that.  */
+
 static void
-do_iwmmxt_word_addr (str)
-     char * str;
+do_bkpt (void)
 {
-  int op = (inst.instruction & 0x300) >> 8;
-  int reg;
-
-  inst.instruction &= ~0x300;
-  inst.instruction |= (op & 1) << 22 | (op & 2) << 7;  
+  /* Top 12 of 16 bits to bits 19:8.  */
+  inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
 
-  skip_whitespace (str);
+  /* Bottom 4 of 16 bits to bits 3:0.  */
+  inst.instruction |= inst.operands[0].imm & 0xf;
+}
 
-  if ((reg = wreg_required_here (&str, 12, IWMMXT_REG_WR_OR_WC)) == FAIL
-      || skip_past_comma (& str) == FAIL
-      || cp_address_required_here (& str, CP_WB_OK) == FAIL)
+static void
+encode_branch (int default_reloc)
+{
+  if (inst.operands[0].hasreloc)
     {
-      if (! inst.error)
-        inst.error = BAD_ARGS;
+      constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
+		  _("the only suffix valid here is '(plt)'"));
+      inst.reloc.type	= BFD_RELOC_ARM_PLT32;
     }
   else
-    end_of_line (str);
-
-  if (wc_register (reg))
     {
-      if ((inst.instruction & COND_MASK) != COND_ALWAYS)
-	as_bad (_("conditional execution not supported with control register"));
-      if (op != 2)
-	as_bad (_("non-word size not supported with control register"));
-      inst.instruction |=  0xf0000100;
-      inst.instruction &= ~0x00400000;
+      inst.reloc.type = default_reloc;
     }
+  inst.reloc.pc_rel = 1;
 }
 
 static void
-do_iwmmxt_wrwr (str)
-     char * str;
+do_branch (void)
 {
-  check_iwmmxt_insn (str, check_wrwr, 0);
+#ifdef OBJ_ELF
+  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
+    encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
+  else
+#endif
+    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
 }
 
 static void
-do_iwmmxt_wrwrwcg (str)
-     char * str;
+do_bl (void)
 {
-  check_iwmmxt_insn (str, check_wrwrwcg, 0);
+#ifdef OBJ_ELF
+  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
+    {
+      if (inst.cond == COND_ALWAYS)
+	encode_branch (BFD_RELOC_ARM_PCREL_CALL);
+      else
+	encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
+    }
+  else
+#endif
+    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
 }
 
-static void
-do_iwmmxt_wrwrwr (str)
-     char * str;
-{
-  check_iwmmxt_insn (str, check_wrwrwr, 0);
-}
+/* ARM V5 branch-link-exchange instruction (argument parse)
+     BLX <target_addr>		ie BLX(1)
+     BLX{<condition>} <Rm>	ie BLX(2)
+   Unfortunately, there are two different opcodes for this mnemonic.
+   So, the insns[].value is not used, and the code here zaps values
+	into inst.instruction.
+   Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
 
 static void
-do_iwmmxt_wshufh (str)
-     char * str;
+do_blx (void)
 {
-  unsigned long number;
-
-  if ((number = check_iwmmxt_insn (str, check_wshufh, 0xff)) == (unsigned long) FAIL)
-    return;
+  if (inst.operands[0].isreg)
+    {
+      /* Arg is a register; the opcode provided by insns[] is correct.
+	 It is not illegal to do "blx pc", just useless.  */
+      if (inst.operands[0].reg == REG_PC)
+	as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
 
-  inst.instruction |= ((number & 0xf0) << 16) | (number & 0xf);
+      inst.instruction |= inst.operands[0].reg;
+    }
+  else
+    {
+      /* Arg is an address; this instruction cannot be executed
+	 conditionally, and the opcode must be adjusted.  */
+      constraint (inst.cond != COND_ALWAYS, BAD_COND);
+      inst.instruction = 0xfa000000;
+#ifdef OBJ_ELF
+      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
+	encode_branch (BFD_RELOC_ARM_PCREL_CALL);
+      else
+#endif
+	encode_branch (BFD_RELOC_ARM_PCREL_BLX);
+    }
 }
 
 static void
-do_iwmmxt_wzero (str)
-     char * str;
+do_bx (void)
 {
-  if (check_iwmmxt_insn (str, check_wr, 0) == (unsigned long) FAIL)
-    return;
+  if (inst.operands[0].reg == REG_PC)
+    as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
 
-  inst.instruction |= ((inst.instruction & 0xf) << 12) | ((inst.instruction & 0xf) << 16);
+  inst.instruction |= inst.operands[0].reg;
 }
 
-/* Xscale multiply-accumulate (argument parse)
-     MIAcc   acc0,Rm,Rs
-     MIAPHcc acc0,Rm,Rs
-     MIAxycc acc0,Rm,Rs.  */
+
+/* ARM v5TEJ.  Jump to Jazelle code.  */
 
 static void
-do_xsc_mia (str)
-     char * str;
+do_bxj (void)
 {
-  int rs;
-  int rm;
-
-  if (accum0_required_here (& str) == FAIL)
-    inst.error = ERR_NO_ACCUM;
-
-  else if (skip_past_comma (& str) == FAIL
-	   || (rm = reg_required_here (& str, 0)) == FAIL)
-    inst.error = BAD_ARGS;
-
-  else if (skip_past_comma (& str) == FAIL
-	   || (rs = reg_required_here (& str, 12)) == FAIL)
-    inst.error = BAD_ARGS;
-
-  /* inst.instruction has now been zapped with both rm and rs.  */
-  else if (rm == REG_PC || rs == REG_PC)
-    inst.error = BAD_PC;	/* Undefined result if rm or rs is R15.  */
+  if (inst.operands[0].reg == REG_PC)
+    as_tsktsk (_("use of r15 in bxj is not really useful"));
 
-  else
-    end_of_line (str);
+  inst.instruction |= inst.operands[0].reg;
 }
 
-/* Xscale move-accumulator-register (argument parse)
-
-     MARcc   acc0,RdLo,RdHi.  */
-
+/* Co-processor data operation:
+      CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
+      CDP2	<coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}	 */
 static void
-do_xsc_mar (str)
-     char * str;
+do_cdp (void)
 {
-  int rdlo, rdhi;
-
-  if (accum0_required_here (& str) == FAIL)
-    inst.error = ERR_NO_ACCUM;
-
-  else if (skip_past_comma (& str) == FAIL
-	   || (rdlo = reg_required_here (& str, 12)) == FAIL)
-    inst.error = BAD_ARGS;
-
-  else if (skip_past_comma (& str) == FAIL
-	   || (rdhi = reg_required_here (& str, 16)) == FAIL)
-    inst.error = BAD_ARGS;
-
-  /* inst.instruction has now been zapped with both rdlo and rdhi.  */
-  else if (rdlo == REG_PC || rdhi == REG_PC)
-    inst.error = BAD_PC;	/* Undefined result if rdlo or rdhi is R15.  */
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm << 20;
+  inst.instruction |= inst.operands[2].reg << 12;
+  inst.instruction |= inst.operands[3].reg << 16;
+  inst.instruction |= inst.operands[4].reg;
+  inst.instruction |= inst.operands[5].imm << 5;
+}
 
-  else
-    end_of_line (str);
+static void
+do_cmp (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  encode_arm_shifter_operand (1);
 }
 
-/* Xscale move-register-accumulator (argument parse)
+/* Transfer between coprocessor and ARM registers.
+   MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
+   MRC2
+   MCR{cond}
+   MCR2
 
-     MRAcc   RdLo,RdHi,acc0.  */
+   No special properties.  */
 
 static void
-do_xsc_mra (str)
-     char * str;
+do_co_reg (void)
 {
-  int rdlo;
-  int rdhi;
-
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm << 21;
+  inst.instruction |= inst.operands[2].reg << 12;
+  inst.instruction |= inst.operands[3].reg << 16;
+  inst.instruction |= inst.operands[4].reg;
+  inst.instruction |= inst.operands[5].imm << 5;
+}
 
-  if ((rdlo = reg_required_here (& str, 12)) == FAIL)
-    inst.error = BAD_ARGS;
+/* Transfer between coprocessor register and pair of ARM registers.
+   MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
+   MCRR2
+   MRRC{cond}
+   MRRC2
 
-  else if (skip_past_comma (& str) == FAIL
-	   || (rdhi = reg_required_here (& str, 16)) == FAIL)
-    inst.error = BAD_ARGS;
+   Two XScale instructions are special cases of these:
 
-  else if  (skip_past_comma (& str) == FAIL
-	    || accum0_required_here (& str) == FAIL)
-    inst.error = ERR_NO_ACCUM;
+     MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
+     MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
 
-  /* inst.instruction has now been zapped with both rdlo and rdhi.  */
-  else if (rdlo == rdhi)
-    inst.error = BAD_ARGS;	/* Undefined result if 2 writes to same reg.  */
+   Result unpredicatable if Rd or Rn is R15.  */
 
-  else if (rdlo == REG_PC || rdhi == REG_PC)
-    inst.error = BAD_PC;	/* Undefined result if rdlo or rdhi is R15.  */
-  else
-    end_of_line (str);
+static void
+do_co_reg2c (void)
+{
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm << 4;
+  inst.instruction |= inst.operands[2].reg << 12;
+  inst.instruction |= inst.operands[3].reg << 16;
+  inst.instruction |= inst.operands[4].reg;
 }
 
-/* ARMv5TE: Preload-Cache
-
-    PLD <addr_mode>
-
-  Syntactically, like LDR with B=1, W=0, L=1.  */
-
 static void
-do_pld (str)
-     char * str;
+do_cpsi (void)
 {
-  int rd;
-
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].imm << 6;
+  inst.instruction |= inst.operands[1].imm;
+}
 
-  if (* str != '[')
-    {
-      inst.error = _("'[' expected after PLD mnemonic");
-      return;
-    }
+static void
+do_dbg (void)
+{
+  inst.instruction |= inst.operands[0].imm;
+}
 
-  ++str;
-  skip_whitespace (str);
+static void
+do_it (void)
+{
+  /* There is no IT instruction in ARM mode.  We
+     process it but do not generate code for it.  */
+  inst.size = 0;
+}
 
-  if ((rd = reg_required_here (& str, 16)) == FAIL)
-    return;
+static void
+do_ldmstm (void)
+{
+  int base_reg = inst.operands[0].reg;
+  int range = inst.operands[1].imm;
 
-  skip_whitespace (str);
+  inst.instruction |= base_reg << 16;
+  inst.instruction |= range;
 
-  if (*str == ']')
-    {
-      /* [Rn], ... ?  */
-      ++str;
-      skip_whitespace (str);
+  if (inst.operands[1].writeback)
+    inst.instruction |= LDM_TYPE_2_OR_3;
 
-      /* Post-indexed addressing is not allowed with PLD.  */
-      if (skip_past_comma (&str) == SUCCESS)
-	{
-	  inst.error
-	    = _("post-indexed expression used in preload instruction");
-	  return;
-	}
-      else if (*str == '!') /* [Rn]! */
-	{
-	  inst.error = _("writeback used in preload instruction");
-	  ++str;
-	}
-      else /* [Rn] */
-	inst.instruction |= INDEX_UP | PRE_INDEX;
-    }
-  else /* [Rn, ...] */
+  if (inst.operands[0].writeback)
     {
-      if (skip_past_comma (& str) == FAIL)
-	{
-	  inst.error = _("pre-indexed expression expected");
-	  return;
-	}
-
-      if (ldst_extend (&str) == FAIL)
-	return;
-
-      skip_whitespace (str);
-
-      if (* str != ']')
+      inst.instruction |= WRITE_BACK;
+      /* Check for unpredictable uses of writeback.  */
+      if (inst.instruction & LOAD_BIT)
 	{
-	  inst.error = _("missing ]");
-	  return;
+	  /* Not allowed in LDM type 2.	 */
+	  if ((inst.instruction & LDM_TYPE_2_OR_3)
+	      && ((range & (1 << REG_PC)) == 0))
+	    as_warn (_("writeback of base register is UNPREDICTABLE"));
+	  /* Only allowed if base reg not in list for other types.  */
+	  else if (range & (1 << base_reg))
+	    as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
 	}
-
-      ++ str;
-      skip_whitespace (str);
-
-      if (* str == '!') /* [Rn]! */
+      else /* STM.  */
 	{
-	  inst.error = _("writeback used in preload instruction");
-	  ++ str;
+	  /* Not allowed for type 2.  */
+	  if (inst.instruction & LDM_TYPE_2_OR_3)
+	    as_warn (_("writeback of base register is UNPREDICTABLE"));
+	  /* Only allowed if base reg not in list, or first in list.  */
+	  else if ((range & (1 << base_reg))
+		   && (range & ((1 << base_reg) - 1)))
+	    as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
 	}
-
-      inst.instruction |= PRE_INDEX;
     }
-
-  end_of_line (str);
 }
 
 /* ARMv5TE load-consecutive (argument parse)
@@ -6669,5496 +4957,6618 @@ do_pld (str)
      STRccD R, mode.  */
 
 static void
-do_ldrd (str)
-     char * str;
+do_ldrd (void)
 {
-  int rd;
-  int rn;
-
-  skip_whitespace (str);
+  constraint (inst.operands[0].reg % 2 != 0,
+	      _("first destination register must be even"));
+  constraint (inst.operands[1].present
+	      && inst.operands[1].reg != inst.operands[0].reg + 1,
+	      _("can only load two consecutive registers"));
+  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
+  constraint (!inst.operands[2].isreg, _("'[' expected"));
 
-  if ((rd = reg_required_here (& str, 12)) == FAIL)
+  if (!inst.operands[1].present)
+    inst.operands[1].reg = inst.operands[0].reg + 1;
+  
+  if (inst.instruction & LOAD_BIT)
     {
-      inst.error = BAD_ARGS;
-      return;
-    }
+      /* encode_arm_addr_mode_3 will diagnose overlap between the base
+	 register and the first register written; we have to diagnose
+	 overlap between the base and the second register written here.	 */
 
-  if (skip_past_comma (& str) == FAIL
-      || (rn = ld_mode_required_here (& str)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      if (inst.operands[2].reg == inst.operands[1].reg
+	  && (inst.operands[2].writeback || inst.operands[2].postind))
+	as_warn (_("base register written back, and overlaps "
+		   "second destination register"));
 
-  /* inst.instruction has now been zapped with Rd and the addressing mode.  */
-  if (rd & 1)		/* Unpredictable result if Rd is odd.  */
-    {
-      inst.error = _("destination register must be even");
-      return;
+      /* For an index-register load, the index register must not overlap the
+	 destination (even if not write-back).	*/
+      else if (inst.operands[2].immisreg
+	       && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
+		   || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
+	as_warn (_("index register overlaps destination register"));
     }
 
-  if (rd == REG_LR)
-    {
-      inst.error = _("r14 not allowed here");
-      return;
-    }
-
-  if (((rd == rn) || (rd + 1 == rn))
-      && ((inst.instruction & WRITE_BACK)
-	  || (!(inst.instruction & PRE_INDEX))))
-    as_warn (_("pre/post-indexing used when modified address register is destination"));
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
+}
 
-  /* For an index-register load, the index register must not overlap the
-     destination (even if not write-back).  */
-  if ((inst.instruction & V4_STR_BIT) == 0
-      && (inst.instruction & HWOFFSET_IMM) == 0)
-    {
-      int rm = inst.instruction & 0x0000000f;
+static void
+do_ldrex (void)
+{
+  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
+	      || inst.operands[1].postind || inst.operands[1].writeback
+	      || inst.operands[1].immisreg || inst.operands[1].shifted
+	      || inst.operands[1].negative
+	      /* This can arise if the programmer has written
+		   strex rN, rM, foo
+		 or if they have mistakenly used a register name as the last
+		 operand,  eg:
+		   strex rN, rM, rX
+		 It is very difficult to distinguish between these two cases
+		 because "rX" might actually be a label. ie the register
+		 name has been occluded by a symbol of the same name. So we
+		 just generate a general 'bad addressing mode' type error
+		 message and leave it up to the programmer to discover the
+		 true cause and fix their mistake.  */
+	      || (inst.operands[1].reg == REG_PC),
+	      BAD_ADDR_MODE);
 
-      if (rm == rd || (rm == rd + 1))
-	as_warn (_("ldrd destination registers must not overlap index register"));
-    }
+  constraint (inst.reloc.exp.X_op != O_constant
+	      || inst.reloc.exp.X_add_number != 0,
+	      _("offset must be zero in ARM encoding"));
 
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.reloc.type = BFD_RELOC_UNUSED;
 }
 
-/* Returns the index into fp_values of a floating point number,
-   or -1 if not in the table.  */
-
-static int
-my_get_float_expression (str)
-     char ** str;
+static void
+do_ldrexd (void)
 {
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  char *         save_in;
-  expressionS    exp;
-  int            i;
-  int            j;
+  constraint (inst.operands[0].reg % 2 != 0,
+	      _("even register required"));
+  constraint (inst.operands[1].present
+	      && inst.operands[1].reg != inst.operands[0].reg + 1,
+	      _("can only load two consecutive registers"));
+  /* If op 1 were present and equal to PC, this function wouldn't
+     have been called in the first place.  */
+  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
 
-  memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
-
-  /* Look for a raw floating point number.  */
-  if ((save_in = atof_ieee (*str, 'x', words)) != NULL
-      && is_end_of_line[(unsigned char) *save_in])
-    {
-      for (i = 0; i < NUM_FLOAT_VALS; i++)
-	{
-	  for (j = 0; j < MAX_LITTLENUMS; j++)
-	    {
-	      if (words[j] != fp_values[i][j])
-		break;
-	    }
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
+}
 
-	  if (j == MAX_LITTLENUMS)
-	    {
-	      *str = save_in;
-	      return i;
-	    }
-	}
-    }
+static void
+do_ldst (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  if (!inst.operands[1].isreg)
+    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
+      return;
+  encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
+}
 
-  /* Try and parse a more complex expression, this will probably fail
-     unless the code uses a floating point prefix (eg "0f").  */
-  save_in = input_line_pointer;
-  input_line_pointer = *str;
-  if (expression (&exp) == absolute_section
-      && exp.X_op == O_big
-      && exp.X_add_number < 0)
+static void
+do_ldstt (void)
+{
+  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
+     reject [Rn,...].  */
+  if (inst.operands[1].preind)
     {
-      /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
-	 Ditto for 15.  */
-      if (gen_to_words (words, 5, (long) 15) == 0)
-	{
-	  for (i = 0; i < NUM_FLOAT_VALS; i++)
-	    {
-	      for (j = 0; j < MAX_LITTLENUMS; j++)
-		{
-		  if (words[j] != fp_values[i][j])
-		    break;
-		}
+      constraint (inst.reloc.exp.X_op != O_constant ||
+		  inst.reloc.exp.X_add_number != 0,
+		  _("this instruction requires a post-indexed address"));
 
-	      if (j == MAX_LITTLENUMS)
-		{
-		  *str = input_line_pointer;
-		  input_line_pointer = save_in;
-		  return i;
-		}
-	    }
-	}
+      inst.operands[1].preind = 0;
+      inst.operands[1].postind = 1;
+      inst.operands[1].writeback = 1;
     }
-
-  *str = input_line_pointer;
-  input_line_pointer = save_in;
-  return -1;
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
 }
 
-/* Return TRUE if anything in the expression is a bignum.  */
+/* Halfword and signed-byte load/store operations.  */
 
-static int
-walk_no_bignums (sp)
-     symbolS * sp;
+static void
+do_ldstv4 (void)
 {
-  if (symbol_get_value_expression (sp)->X_op == O_big)
-    return 1;
+  inst.instruction |= inst.operands[0].reg << 12;
+  if (!inst.operands[1].isreg)
+    if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
+      return;
+  encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
+}
 
-  if (symbol_get_value_expression (sp)->X_add_symbol)
+static void
+do_ldsttv4 (void)
+{
+  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
+     reject [Rn,...].  */
+  if (inst.operands[1].preind)
     {
-      return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
-	      || (symbol_get_value_expression (sp)->X_op_symbol
-		  && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
-    }
+      constraint (inst.reloc.exp.X_op != O_constant ||
+		  inst.reloc.exp.X_add_number != 0,
+		  _("this instruction requires a post-indexed address"));
 
-  return 0;
+      inst.operands[1].preind = 0;
+      inst.operands[1].postind = 1;
+      inst.operands[1].writeback = 1;
+    }
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
 }
 
-static int in_my_get_expression = 0;
+/* Co-processor register load/store.
+   Format: <LDC|STC>{cond}[L] CP#,CRd,<address>	 */
+static void
+do_lstc (void)
+{
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 12;
+  encode_arm_cp_address (2, TRUE, TRUE, 0);
+}
 
-static int
-my_get_expression (ep, str)
-     expressionS * ep;
-     char ** str;
+static void
+do_mlas (void)
 {
-  char * save_in;
-  segT   seg;
+  /* This restriction does not apply to mls (nor to mla in v6, but
+     that's hard to detect at present).	 */
+  if (inst.operands[0].reg == inst.operands[1].reg
+      && !(inst.instruction & 0x00400000))
+    as_tsktsk (_("rd and rm should be different in mla"));
 
-  save_in = input_line_pointer;
-  input_line_pointer = *str;
-  in_my_get_expression = 1;
-  seg = expression (ep);
-  in_my_get_expression = 0;
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 8;
+  inst.instruction |= inst.operands[3].reg << 12;
 
-  if (ep->X_op == O_illegal)
-    {
-      /* We found a bad expression in md_operand().  */
-      *str = input_line_pointer;
-      input_line_pointer = save_in;
-      return 1;
-    }
+}
 
-#ifdef OBJ_AOUT
-  if (seg != absolute_section
-      && seg != text_section
-      && seg != data_section
-      && seg != bss_section
-      && seg != undefined_section)
-    {
-      inst.error = _("bad_segment");
-      *str = input_line_pointer;
-      input_line_pointer = save_in;
-      return 1;
-    }
-#endif
+static void
+do_mov (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_shifter_operand (1);
+}
 
-  /* Get rid of any bignums now, so that we don't generate an error for which
-     we can't establish a line number later on.  Big numbers are never valid
-     in instructions, which is where this routine is always called.  */
-  if (ep->X_op == O_big
-      || (ep->X_add_symbol
-	  && (walk_no_bignums (ep->X_add_symbol)
-	      || (ep->X_op_symbol
-		  && walk_no_bignums (ep->X_op_symbol)))))
-    {
-      inst.error = _("invalid constant");
-      *str = input_line_pointer;
-      input_line_pointer = save_in;
-      return 1;
-    }
+/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>.	 */
+static void
+do_mov16 (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  /* The value is in two pieces: 0:11, 16:19.  */
+  inst.instruction |= (inst.operands[1].imm & 0x00000fff);
+  inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
+}
 
-  *str = input_line_pointer;
-  input_line_pointer = save_in;
-  return 0;
+static void
+do_mrs (void)
+{
+  /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
+  constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
+	      != (PSR_c|PSR_f),
+	      _("'CPSR' or 'SPSR' expected"));
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
 }
 
-/* We handle all bad expressions here, so that we can report the faulty
-   instruction in the error message.  */
-void
-md_operand (expr)
-     expressionS *expr;
+/* Two possible forms:
+      "{C|S}PSR_<field>, Rm",
+      "{C|S}PSR_f, #expression".  */
+
+static void
+do_msr (void)
 {
-  if (in_my_get_expression)
+  inst.instruction |= inst.operands[0].imm;
+  if (inst.operands[1].isreg)
+    inst.instruction |= inst.operands[1].reg;
+  else
     {
-      expr->X_op = O_illegal;
-      if (inst.error == NULL)
-	inst.error = _("bad expression");
+      inst.instruction |= INST_IMMEDIATE;
+      inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+      inst.reloc.pc_rel = 0;
     }
 }
 
-/* KIND indicates what kind of shifts are accepted.  */
-
-static int
-decode_shift (str, kind)
-     char ** str;
-     int     kind;
+static void
+do_mul (void)
 {
-  const struct asm_shift_name * shift;
-  char * p;
-  char   c;
+  if (!inst.operands[2].present)
+    inst.operands[2].reg = inst.operands[0].reg;
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 8;
 
-  skip_whitespace (* str);
+  if (inst.operands[0].reg == inst.operands[1].reg)
+    as_tsktsk (_("rd and rm should be different in mul"));
+}
 
-  for (p = * str; ISALPHA (* p); p ++)
-    ;
+/* Long Multiply Parser
+   UMULL RdLo, RdHi, Rm, Rs
+   SMULL RdLo, RdHi, Rm, Rs
+   UMLAL RdLo, RdHi, Rm, Rs
+   SMLAL RdLo, RdHi, Rm, Rs.  */
 
-  if (p == * str)
-    {
-      inst.error = _("shift expression expected");
-      return FAIL;
-    }
+static void
+do_mull (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].reg << 8;
 
-  c = * p;
-  * p = '\0';
-  shift = (const struct asm_shift_name *) hash_find (arm_shift_hsh, * str);
-  * p = c;
+  /* rdhi, rdlo and rm must all be different.  */
+  if (inst.operands[0].reg == inst.operands[1].reg
+      || inst.operands[0].reg == inst.operands[2].reg
+      || inst.operands[1].reg == inst.operands[2].reg)
+    as_tsktsk (_("rdhi, rdlo and rm must all be different"));
+}
 
-  if (shift == NULL)
+static void
+do_nop (void)
+{
+  if (inst.operands[0].present)
     {
-      inst.error = _("shift expression expected");
-      return FAIL;
+      /* Architectural NOP hints are CPSR sets with no bits selected.  */
+      inst.instruction &= 0xf0000000;
+      inst.instruction |= 0x0320f000 + inst.operands[0].imm;
     }
+}
 
-  assert (shift->properties->index == shift_properties[shift->properties->index].index);
+/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
+   PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
+   Condition defaults to COND_ALWAYS.
+   Error if Rd, Rn or Rm are R15.  */
 
-  if (kind == SHIFT_LSL_OR_ASR_IMMEDIATE
-      && shift->properties->index != SHIFT_LSL
-      && shift->properties->index != SHIFT_ASR)
-    {
-      inst.error = _("'LSL' or 'ASR' required");
-      return FAIL;
-    }
-  else if (kind == SHIFT_LSL_IMMEDIATE
-	   && shift->properties->index != SHIFT_LSL)
-    {
-      inst.error = _("'LSL' required");
-      return FAIL;
-    }
-  else if (kind == SHIFT_ASR_IMMEDIATE
-	   && shift->properties->index != SHIFT_ASR)
-    {
-      inst.error = _("'ASR' required");
-      return FAIL;
-    }
-    
-  if (shift->properties->index == SHIFT_RRX)
-    {
-      * str = p;
-      inst.instruction |= shift->properties->bit_field;
-      return SUCCESS;
-    }
+static void
+do_pkhbt (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  if (inst.operands[3].present)
+    encode_arm_shift (3);
+}
 
-  skip_whitespace (p);
+/* ARM V6 PKHTB (Argument Parse).  */
 
-  if (kind == NO_SHIFT_RESTRICT && reg_required_here (& p, 8) != FAIL)
+static void
+do_pkhtb (void)
+{
+  if (!inst.operands[3].present)
     {
-      inst.instruction |= shift->properties->bit_field | SHIFT_BY_REG;
-      * str = p;
-      return SUCCESS;
+      /* If the shift specifier is omitted, turn the instruction
+	 into pkhbt rd, rm, rn. */
+      inst.instruction &= 0xfff00010;
+      inst.instruction |= inst.operands[0].reg << 12;
+      inst.instruction |= inst.operands[1].reg;
+      inst.instruction |= inst.operands[2].reg << 16;
     }
-  else if (! is_immediate_prefix (* p))
+  else
     {
-      inst.error = (NO_SHIFT_RESTRICT
-		    ? _("shift requires register or #expression")
-		    : _("shift requires #expression"));
-      * str = p;
-      return FAIL;
+      inst.instruction |= inst.operands[0].reg << 12;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.operands[2].reg;
+      encode_arm_shift (3);
     }
+}
 
-  inst.error = NULL;
-  p ++;
-
-  if (my_get_expression (& inst.reloc.exp, & p))
-    return FAIL;
-
-  /* Validate some simple #expressions.  */
-  if (inst.reloc.exp.X_op == O_constant)
-    {
-      unsigned num = inst.reloc.exp.X_add_number;
-
-      /* Reject operations greater than 32.  */
-      if (num > 32
-	  /* Reject a shift of 0 unless the mode allows it.  */
-	  || (num == 0 && shift->properties->allows_0 == 0)
-	  /* Reject a shift of 32 unless the mode allows it.  */
-	  || (num == 32 && shift->properties->allows_32 == 0)
-	  )
-	{
-	  /* As a special case we allow a shift of zero for
-	     modes that do not support it to be recoded as an
-	     logical shift left of zero (ie nothing).  We warn
-	     about this though.  */
-	  if (num == 0)
-	    {
-	      as_warn (_("shift of 0 ignored."));
-	      shift = & shift_names[0];
-	      assert (shift->properties->index == SHIFT_LSL);
-	    }
-	  else
-	    {
-	      inst.error = _("invalid immediate shift");
-	      return FAIL;
-	    }
-	}
+/* ARMv5TE: Preload-Cache
 
-      /* Shifts of 32 are encoded as 0, for those shifts that
-	 support it.  */
-      if (num == 32)
-	num = 0;
+    PLD <addr_mode>
 
-      inst.instruction |= (num << 7) | shift->properties->bit_field;
-    }
-  else
-    {
-      inst.reloc.type   = BFD_RELOC_ARM_SHIFT_IMM;
-      inst.reloc.pc_rel = 0;
-      inst.instruction |= shift->properties->bit_field;
-    }
+  Syntactically, like LDR with B=1, W=0, L=1.  */
 
-  * str = p;
-  return SUCCESS;
+static void
+do_pld (void)
+{
+  constraint (!inst.operands[0].isreg,
+	      _("'[' expected after PLD mnemonic"));
+  constraint (inst.operands[0].postind,
+	      _("post-indexed expression used in preload instruction"));
+  constraint (inst.operands[0].writeback,
+	      _("writeback used in preload instruction"));
+  constraint (!inst.operands[0].preind,
+	      _("unindexed addressing used in preload instruction"));
+  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
 }
 
-/* Do those data_ops which can take a negative immediate constant
-   by altering the instruction.  A bit of a hack really.
-        MOV <-> MVN
-        AND <-> BIC
-        ADC <-> SBC
-        by inverting the second operand, and
-        ADD <-> SUB
-        CMP <-> CMN
-        by negating the second operand.  */
+/* ARMv7: PLI <addr_mode>  */
+static void
+do_pli (void)
+{
+  constraint (!inst.operands[0].isreg,
+	      _("'[' expected after PLI mnemonic"));
+  constraint (inst.operands[0].postind,
+	      _("post-indexed expression used in preload instruction"));
+  constraint (inst.operands[0].writeback,
+	      _("writeback used in preload instruction"));
+  constraint (!inst.operands[0].preind,
+	      _("unindexed addressing used in preload instruction"));
+  encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
+  inst.instruction &= ~PRE_INDEX;
+}
 
-static int
-negate_data_op (instruction, value)
-     unsigned long * instruction;
-     unsigned long   value;
+static void
+do_push_pop (void)
 {
-  int op, new_inst;
-  unsigned long negated, inverted;
+  inst.operands[1] = inst.operands[0];
+  memset (&inst.operands[0], 0, sizeof inst.operands[0]);
+  inst.operands[0].isreg = 1;
+  inst.operands[0].writeback = 1;
+  inst.operands[0].reg = REG_SP;
+  do_ldmstm ();
+}
 
-  negated = validate_immediate (-value);
-  inverted = validate_immediate (~value);
+/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
+   word at the specified address and the following word
+   respectively.
+   Unconditionally executed.
+   Error if Rn is R15.	*/
 
-  op = (*instruction >> DATA_OP_SHIFT) & 0xf;
-  switch (op)
-    {
-      /* First negates.  */
-    case OPCODE_SUB:             /* ADD <-> SUB  */
-      new_inst = OPCODE_ADD;
-      value = negated;
-      break;
+static void
+do_rfe (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  if (inst.operands[0].writeback)
+    inst.instruction |= WRITE_BACK;
+}
 
-    case OPCODE_ADD:
-      new_inst = OPCODE_SUB;
-      value = negated;
-      break;
+/* ARM V6 ssat (argument parse).  */
 
-    case OPCODE_CMP:             /* CMP <-> CMN  */
-      new_inst = OPCODE_CMN;
-      value = negated;
-      break;
+static void
+do_ssat (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= (inst.operands[1].imm - 1) << 16;
+  inst.instruction |= inst.operands[2].reg;
 
-    case OPCODE_CMN:
-      new_inst = OPCODE_CMP;
-      value = negated;
-      break;
+  if (inst.operands[3].present)
+    encode_arm_shift (3);
+}
 
-      /* Now Inverted ops.  */
-    case OPCODE_MOV:             /* MOV <-> MVN  */
-      new_inst = OPCODE_MVN;
-      value = inverted;
-      break;
+/* ARM V6 usat (argument parse).  */
 
-    case OPCODE_MVN:
-      new_inst = OPCODE_MOV;
-      value = inverted;
-      break;
+static void
+do_usat (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].imm << 16;
+  inst.instruction |= inst.operands[2].reg;
 
-    case OPCODE_AND:             /* AND <-> BIC  */
-      new_inst = OPCODE_BIC;
-      value = inverted;
-      break;
+  if (inst.operands[3].present)
+    encode_arm_shift (3);
+}
 
-    case OPCODE_BIC:
-      new_inst = OPCODE_AND;
-      value = inverted;
-      break;
+/* ARM V6 ssat16 (argument parse).  */
 
-    case OPCODE_ADC:              /* ADC <-> SBC  */
-      new_inst = OPCODE_SBC;
-      value = inverted;
-      break;
+static void
+do_ssat16 (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= ((inst.operands[1].imm - 1) << 16);
+  inst.instruction |= inst.operands[2].reg;
+}
 
-    case OPCODE_SBC:
-      new_inst = OPCODE_ADC;
-      value = inverted;
-      break;
+static void
+do_usat16 (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].imm << 16;
+  inst.instruction |= inst.operands[2].reg;
+}
 
-      /* We cannot do anything.  */
-    default:
-      return FAIL;
-    }
+/* ARM V6 SETEND (argument parse).  Sets the E bit in the CPSR while
+   preserving the other bits.
 
-  if (value == (unsigned) FAIL)
-    return FAIL;
+   setend <endian_specifier>, where <endian_specifier> is either
+   BE or LE.  */
 
-  *instruction &= OPCODE_MASK;
-  *instruction |= new_inst << DATA_OP_SHIFT;
-  return value;
+static void
+do_setend (void)
+{
+  if (inst.operands[0].imm)
+    inst.instruction |= 0x200;
 }
 
-static int
-data_op2 (str)
-     char ** str;
+static void
+do_shift (void)
 {
-  int value;
-  expressionS expr;
-
-  skip_whitespace (* str);
+  unsigned int Rm = (inst.operands[1].present
+		     ? inst.operands[1].reg
+		     : inst.operands[0].reg);
 
-  if (reg_required_here (str, 0) != FAIL)
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= Rm;
+  if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */
     {
-      if (skip_past_comma (str) == SUCCESS)
-	/* Shift operation on register.  */
-	return decode_shift (str, NO_SHIFT_RESTRICT);
-
-      return SUCCESS;
+      inst.instruction |= inst.operands[2].reg << 8;
+      inst.instruction |= SHIFT_BY_REG;
     }
   else
-    {
-      /* Immediate expression.  */
-      if (is_immediate_prefix (**str))
-	{
-	  (*str)++;
-	  inst.error = NULL;
-
-	  if (my_get_expression (&inst.reloc.exp, str))
-	    return FAIL;
-
-	  if (inst.reloc.exp.X_add_symbol)
-	    {
-	      inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
-	      inst.reloc.pc_rel = 0;
-	    }
-	  else
-	    {
-	      if (skip_past_comma (str) == SUCCESS)
-		{
-		  /* #x, y -- ie explicit rotation by Y.  */
-		  if (my_get_expression (&expr, str))
-		    return FAIL;
+    inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
+}
 
-		  if (expr.X_op != O_constant)
-		    {
-		      inst.error = _("constant expression expected");
-		      return FAIL;
-		    }
+static void
+do_smc (void)
+{
+  inst.reloc.type = BFD_RELOC_ARM_SMC;
+  inst.reloc.pc_rel = 0;
+}
 
-		  /* Rotate must be a multiple of 2.  */
-		  if (((unsigned) expr.X_add_number) > 30
-		      || (expr.X_add_number & 1) != 0
-		      || ((unsigned) inst.reloc.exp.X_add_number) > 255)
-		    {
-		      inst.error = _("invalid constant");
-		      return FAIL;
-		    }
-		  inst.instruction |= INST_IMMEDIATE;
-		  inst.instruction |= inst.reloc.exp.X_add_number;
-		  inst.instruction |= expr.X_add_number << 7;
-		  return SUCCESS;
-		}
+static void
+do_swi (void)
+{
+  inst.reloc.type = BFD_RELOC_ARM_SWI;
+  inst.reloc.pc_rel = 0;
+}
 
-	      /* Implicit rotation, select a suitable one.  */
-	      value = validate_immediate (inst.reloc.exp.X_add_number);
+/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
+   SMLAxy{cond} Rd,Rm,Rs,Rn
+   SMLAWy{cond} Rd,Rm,Rs,Rn
+   Error if any register is R15.  */
 
-	      if (value == FAIL)
-		{
-		  /* Can't be done.  Perhaps the code reads something like
-		     "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK.  */
-		  if ((value = negate_data_op (&inst.instruction,
-					       inst.reloc.exp.X_add_number))
-		      == FAIL)
-		    {
-		      inst.error = _("invalid constant");
-		      return FAIL;
-		    }
-		}
+static void
+do_smla (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 8;
+  inst.instruction |= inst.operands[3].reg << 12;
+}
 
-	      inst.instruction |= value;
-	    }
+/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
+   SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
+   Error if any register is R15.
+   Warning if Rdlo == Rdhi.  */
 
-	  inst.instruction |= INST_IMMEDIATE;
-	  return SUCCESS;
-	}
+static void
+do_smlal (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].reg << 8;
 
-      (*str)++;
-      inst.error = _("register or shift expression expected");
-      return FAIL;
-    }
+  if (inst.operands[0].reg == inst.operands[1].reg)
+    as_tsktsk (_("rdhi and rdlo must be different"));
 }
 
-static int
-fp_op2 (str)
-     char ** str;
-{
-  skip_whitespace (* str);
+/* ARM V5E (El Segundo) signed-multiply (argument parse)
+   SMULxy{cond} Rd,Rm,Rs
+   Error if any register is R15.  */
 
-  if (fp_reg_required_here (str, 0) != FAIL)
-    return SUCCESS;
-  else
-    {
-      /* Immediate expression.  */
-      if (*((*str)++) == '#')
-	{
-	  int i;
+static void
+do_smul (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 8;
+}
 
-	  inst.error = NULL;
+/* ARM V6 srs (argument parse).	 */
 
-	  skip_whitespace (* str);
+static void
+do_srs (void)
+{
+  inst.instruction |= inst.operands[0].imm;
+  if (inst.operands[0].writeback)
+    inst.instruction |= WRITE_BACK;
+}
 
-	  /* First try and match exact strings, this is to guarantee
-	     that some formats will work even for cross assembly.  */
+/* ARM V6 strex (argument parse).  */
 
-	  for (i = 0; fp_const[i]; i++)
-	    {
-	      if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
-		{
-		  char *start = *str;
+static void
+do_strex (void)
+{
+  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
+	      || inst.operands[2].postind || inst.operands[2].writeback
+	      || inst.operands[2].immisreg || inst.operands[2].shifted
+	      || inst.operands[2].negative
+	      /* See comment in do_ldrex().  */
+	      || (inst.operands[2].reg == REG_PC),
+	      BAD_ADDR_MODE);
 
-		  *str += strlen (fp_const[i]);
-		  if (is_end_of_line[(unsigned char) **str])
-		    {
-		      inst.instruction |= i + 8;
-		      return SUCCESS;
-		    }
-		  *str = start;
-		}
-	    }
+  constraint (inst.operands[0].reg == inst.operands[1].reg
+	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
 
-	  /* Just because we didn't get a match doesn't mean that the
-	     constant isn't valid, just that it is in a format that we
-	     don't automatically recognize.  Try parsing it with
-	     the standard expression routines.  */
-	  if ((i = my_get_float_expression (str)) >= 0)
-	    {
-	      inst.instruction |= i + 8;
-	      return SUCCESS;
-	    }
+  constraint (inst.reloc.exp.X_op != O_constant
+	      || inst.reloc.exp.X_add_number != 0,
+	      _("offset must be zero in ARM encoding"));
 
-	  inst.error = _("invalid floating point immediate expression");
-	  return FAIL;
-	}
-      inst.error =
-	_("floating point register or immediate expression expected");
-      return FAIL;
-    }
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 16;
+  inst.reloc.type = BFD_RELOC_UNUSED;
 }
 
 static void
-do_arit (str)
-     char * str;
+do_strexd (void)
 {
-  skip_whitespace (str);
+  constraint (inst.operands[1].reg % 2 != 0,
+	      _("even register required"));
+  constraint (inst.operands[2].present
+	      && inst.operands[2].reg != inst.operands[1].reg + 1,
+	      _("can only store two consecutive registers"));
+  /* If op 2 were present and equal to PC, this function wouldn't
+     have been called in the first place.  */
+  constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
 
-  if (reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 16) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || data_op2 (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  constraint (inst.operands[0].reg == inst.operands[1].reg
+	      || inst.operands[0].reg == inst.operands[1].reg + 1
+	      || inst.operands[0].reg == inst.operands[3].reg,
+	      BAD_OVERLAP);
 
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[3].reg << 16;
 }
 
+/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
+   extends it to 32-bits, and adds the result to a value in another
+   register.  You can specify a rotation by 0, 8, 16, or 24 bits
+   before extracting the 16-bit value.
+   SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
+   Condition defaults to COND_ALWAYS.
+   Error if any register uses R15.  */
+
 static void
-do_adr (str)
-     char * str;
+do_sxtah (void)
 {
-  /* This is a pseudo-op of the form "adr rd, label" to be converted
-     into a relative address of the form "add rd, pc, #label-.-8".  */
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 10;
+}
 
-  if (reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || my_get_expression (&inst.reloc.exp, &str))
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+/* ARM V6 SXTH.
 
-  /* Frag hacking will turn this into a sub instruction if the offset turns
-     out to be negative.  */
-  inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
-#ifndef TE_WINCE
-  inst.reloc.exp.X_add_number -= 8; /* PC relative adjust.  */
-#endif
-  inst.reloc.pc_rel = 1;
+   SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
+   Condition defaults to COND_ALWAYS.
+   Error if any register uses R15.  */
 
-  end_of_line (str);
+static void
+do_sxth (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].imm << 10;
 }
+
+/* VFP instructions.  In a logical order: SP variant first, monad
+   before dyad, arithmetic then move then load/store.  */
 
 static void
-do_adrl (str)
-     char * str;
+do_vfp_sp_monadic (void)
 {
-  /* This is a pseudo-op of the form "adrl rd, label" to be converted
-     into a relative address of the form:
-     add rd, pc, #low(label-.-8)"
-     add rd, rd, #high(label-.-8)"  */
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+}
 
-  skip_whitespace (str);
+static void
+do_vfp_sp_dyadic (void)
+{
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
+  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+}
 
-  if (reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || my_get_expression (&inst.reloc.exp, &str))
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+static void
+do_vfp_sp_compare_z (void)
+{
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+}
 
-      return;
-    }
+static void
+do_vfp_dp_sp_cvt (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
+}
 
-  end_of_line (str);
-  /* Frag hacking will turn this into a sub instruction if the offset turns
-     out to be negative.  */
-  inst.reloc.type              = BFD_RELOC_ARM_ADRL_IMMEDIATE;
-#ifndef TE_WINCE  
-  inst.reloc.exp.X_add_number -= 8; /* PC relative adjust  */
-#endif
-  inst.reloc.pc_rel            = 1;
-  inst.size                    = INSN_SIZE * 2;
+static void
+do_vfp_sp_dp_cvt (void)
+{
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  inst.instruction |= inst.operands[1].reg;
 }
 
 static void
-do_cmp (str)
-     char * str;
+do_vfp_reg_from_sp (void)
 {
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
+}
 
-  if (reg_required_here (&str, 16) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_vfp_reg2_from_sp2 (void)
+{
+  constraint (inst.operands[2].imm != 2,
+	      _("only two consecutive VFP SP registers allowed here"));
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || data_op2 (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_vfp_sp_from_reg (void)
+{
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
+  inst.instruction |= inst.operands[1].reg << 12;
+}
 
-  end_of_line (str);
+static void
+do_vfp_sp2_from_reg2 (void)
+{
+  constraint (inst.operands[0].imm != 2,
+	      _("only two consecutive VFP SP registers allowed here"));
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
 }
 
 static void
-do_mov (str)
-     char * str;
+do_vfp_sp_ldst (void)
 {
-  skip_whitespace (str);
+  encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
+  encode_arm_cp_address (1, FALSE, TRUE, 0);
+}
 
-  if (reg_required_here (&str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_vfp_dp_ldst (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_cp_address (1, FALSE, TRUE, 0);
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || data_op2 (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
 
-  end_of_line (str);
+static void
+vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
+{
+  if (inst.operands[0].writeback)
+    inst.instruction |= WRITE_BACK;
+  else
+    constraint (ldstm_type != VFP_LDSTMIA,
+		_("this addressing mode requires base-register writeback"));
+  inst.instruction |= inst.operands[0].reg << 16;
+  encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
+  inst.instruction |= inst.operands[1].imm;
 }
 
-static int
-ldst_extend (str)
-     char ** str;
+static void
+vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
 {
-  int add = INDEX_UP;
-
-  switch (**str)
-    {
-    case '#':
-    case '$':
-      (*str)++;
-      if (my_get_expression (& inst.reloc.exp, str))
-	return FAIL;
+  int count;
 
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  int value = inst.reloc.exp.X_add_number;
-
-	  if (value < -4095 || value > 4095)
-	    {
-	      inst.error = _("address offset too large");
-	      return FAIL;
-	    }
+  if (inst.operands[0].writeback)
+    inst.instruction |= WRITE_BACK;
+  else
+    constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
+		_("this addressing mode requires base-register writeback"));
 
-	  if (value < 0)
-	    {
-	      value = -value;
-	      add = 0;
-	    }
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg << 12;
 
-	  inst.instruction |= add | value;
-	}
-      else
-	{
-	  inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
-	  inst.reloc.pc_rel = 0;
-	}
-      return SUCCESS;
+  count = inst.operands[1].imm << 1;
+  if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
+    count += 1;
 
-    case '-':
-      add = 0;
-      /* Fall through.  */
+  inst.instruction |= count;
+}
 
-    case '+':
-      (*str)++;
-      /* Fall through.  */
+static void
+do_vfp_sp_ldstmia (void)
+{
+  vfp_sp_ldstm (VFP_LDSTMIA);
+}
 
-    default:
-      if (reg_required_here (str, 0) == FAIL)
-	return FAIL;
+static void
+do_vfp_sp_ldstmdb (void)
+{
+  vfp_sp_ldstm (VFP_LDSTMDB);
+}
 
-      inst.instruction |= add | OFFSET_REG;
-      if (skip_past_comma (str) == SUCCESS)
-	return decode_shift (str, SHIFT_IMMEDIATE);
+static void
+do_vfp_dp_ldstmia (void)
+{
+  vfp_dp_ldstm (VFP_LDSTMIA);
+}
 
-      return SUCCESS;
-    }
+static void
+do_vfp_dp_ldstmdb (void)
+{
+  vfp_dp_ldstm (VFP_LDSTMDB);
 }
 
 static void
-do_ldst (str)
-     char *        str;
+do_vfp_xp_ldstmia (void)
 {
-  int pre_inc = 0;
-  int conflict_reg;
-  int value;
+  vfp_dp_ldstm (VFP_LDSTMIAX);
+}
 
-  skip_whitespace (str);
+static void
+do_vfp_xp_ldstmdb (void)
+{
+  vfp_dp_ldstm (VFP_LDSTMDBX);
+}
+
+/* FPA instructions.  Also in a logical order.	*/
 
-  if ((conflict_reg = reg_required_here (&str, 12)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_fpa_cmp (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+}
 
-  if (skip_past_comma (&str) == FAIL)
+static void
+do_fpa_ldmstm (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  switch (inst.operands[1].imm)
     {
-      inst.error = _("address expected");
-      return;
+    case 1: inst.instruction |= CP_T_X;		 break;
+    case 2: inst.instruction |= CP_T_Y;		 break;
+    case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
+    case 4:					 break;
+    default: abort ();
     }
 
-  if (*str == '[')
+  if (inst.instruction & (PRE_INDEX | INDEX_UP))
     {
-      int reg;
-
-      str++;
-
-      skip_whitespace (str);
-
-      if ((reg = reg_required_here (&str, 16)) == FAIL)
-	return;
-
-      /* Conflicts can occur on stores as well as loads.  */
-      conflict_reg = (conflict_reg == reg);
-
-      skip_whitespace (str);
-
-      if (*str == ']')
-	{
-	  str ++;
+      /* The instruction specified "ea" or "fd", so we can only accept
+	 [Rn]{!}.  The instruction does not really support stacking or
+	 unstacking, so we have to emulate these by setting appropriate
+	 bits and offsets.  */
+      constraint (inst.reloc.exp.X_op != O_constant
+		  || inst.reloc.exp.X_add_number != 0,
+		  _("this instruction does not support indexing"));
 
-	  if (skip_past_comma (&str) == SUCCESS)
-	    {
-	      /* [Rn],... (post inc)  */
-	      if (ldst_extend (&str) == FAIL)
-		return;
-	      if (conflict_reg)
-		as_warn (_("%s register same as write-back base"),
-			 ((inst.instruction & LOAD_BIT)
-			  ? _("destination") : _("source")));
-	    }
-	  else
-	    {
-	      /* [Rn]  */
-	      skip_whitespace (str);
+      if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
+	inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
 
-	      if (*str == '!')
-		{
-		  if (conflict_reg)
-		    as_warn (_("%s register same as write-back base"),
-			     ((inst.instruction & LOAD_BIT)
-			      ? _("destination") : _("source")));
-		  str++;
-		  inst.instruction |= WRITE_BACK;
-		}
+      if (!(inst.instruction & INDEX_UP))
+	inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
 
-	      inst.instruction |= INDEX_UP;
-	      pre_inc = 1;
-	    }
-	}
-      else
+      if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
 	{
-	  /* [Rn,...]  */
-	  if (skip_past_comma (&str) == FAIL)
-	    {
-	      inst.error = _("pre-indexed expression expected");
-	      return;
-	    }
-
-	  pre_inc = 1;
-	  if (ldst_extend (&str) == FAIL)
-	    return;
-
-	  skip_whitespace (str);
-
-	  if (*str++ != ']')
-	    {
-	      inst.error = _("missing ]");
-	      return;
-	    }
-
-	  skip_whitespace (str);
-
-	  if (*str == '!')
-	    {
-	      if (conflict_reg)
-		as_warn (_("%s register same as write-back base"),
-			 ((inst.instruction & LOAD_BIT)
-			  ? _("destination") : _("source")));
-	      str++;
-	      inst.instruction |= WRITE_BACK;
-	    }
+	  inst.operands[2].preind = 0;
+	  inst.operands[2].postind = 1;
 	}
     }
-  else if (*str == '=')
-    {
-      if ((inst.instruction & LOAD_BIT) == 0)
-	{
-	  inst.error = _("invalid pseudo operation");
-	  return;
-	}
-
-      /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op.  */
-      str++;
 
-      skip_whitespace (str);
+  encode_arm_cp_address (2, TRUE, TRUE, 0);
+}
+
+/* iWMMXt instructions: strictly in alphabetical order.	 */
 
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
+static void
+do_iwmmxt_tandorc (void)
+{
+  constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
+}
 
-      if (inst.reloc.exp.X_op != O_constant
-	  && inst.reloc.exp.X_op != O_symbol)
-	{
-	  inst.error = _("constant expression expected");
-	  return;
-	}
+static void
+do_iwmmxt_textrc (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].imm;
+}
 
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  value = validate_immediate (inst.reloc.exp.X_add_number);
+static void
+do_iwmmxt_textrm (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].imm;
+}
 
-	  if (value != FAIL)
-	    {
-	      /* This can be done with a mov instruction.  */
-	      inst.instruction &= LITERAL_MASK;
-	      inst.instruction |= (INST_IMMEDIATE
-				   | (OPCODE_MOV << DATA_OP_SHIFT));
-	      inst.instruction |= value & 0xfff;
-	      end_of_line (str);
-	      return;
-	    }
+static void
+do_iwmmxt_tinsr (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].imm;
+}
 
-	  value = validate_immediate (~inst.reloc.exp.X_add_number);
+static void
+do_iwmmxt_tmia (void)
+{
+  inst.instruction |= inst.operands[0].reg << 5;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 12;
+}
 
-	  if (value != FAIL)
-	    {
-	      /* This can be done with a mvn instruction.  */
-	      inst.instruction &= LITERAL_MASK;
-	      inst.instruction |= (INST_IMMEDIATE
-				   | (OPCODE_MVN << DATA_OP_SHIFT));
-	      inst.instruction |= value & 0xfff;
-	      end_of_line (str);
-	      return;
-	    }
-	}
+static void
+do_iwmmxt_waligni (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 20;
+}
 
-      /* Insert into literal pool.  */
-      if (add_to_lit_pool () == FAIL)
-	{
-	  if (!inst.error)
-	    inst.error = _("literal pool insertion failed");
-	  return;
-	}
+static void
+do_iwmmxt_wmov (void)
+{
+  /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+}
 
-      /* Change the instruction exp to point to the pool.  */
-      inst.reloc.type = BFD_RELOC_ARM_LITERAL;
-      inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = 1;
-    }
+static void
+do_iwmmxt_wldstbh (void)
+{
+  int reloc;
+  inst.instruction |= inst.operands[0].reg << 12;
+  if (thumb_mode)
+    reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
   else
-    {
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
+    reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
+  encode_arm_cp_address (1, TRUE, FALSE, reloc);
+}
 
-      inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
-#ifndef TE_WINCE
-      /* PC rel adjust.  */
-      inst.reloc.exp.X_add_number -= 8;
-#endif
-      inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = 1;
+static void
+do_iwmmxt_wldstw (void)
+{
+  /* RIWR_RIWC clears .isreg for a control register.  */
+  if (!inst.operands[0].isreg)
+    {
+      constraint (inst.cond != COND_ALWAYS, BAD_COND);
+      inst.instruction |= 0xf0000000;
     }
 
-  inst.instruction |= (pre_inc ? PRE_INDEX : 0);
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_cp_address (1, TRUE, TRUE, 0);
 }
 
 static void
-do_ldstt (str)
-     char *        str;
+do_iwmmxt_wldstd (void)
 {
-  int conflict_reg;
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_arm_cp_address (1, TRUE, FALSE, 0);
+}
 
-  skip_whitespace (str);
+static void
+do_iwmmxt_wshufh (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
+  inst.instruction |= (inst.operands[2].imm & 0x0f);
+}
 
-  if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_iwmmxt_wzero (void)
+{
+  /* WZERO reg is an alias for WANDN reg, reg, reg.  */
+  inst.instruction |= inst.operands[0].reg;
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[0].reg << 16;
+}
+
+/* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
+   operations first, then control, shift, and load/store.  */
 
-  if (skip_past_comma (& str) == FAIL)
-    {
-      inst.error = _("address expected");
-      return;
-    }
+/* Insns like "foo X,Y,Z".  */
 
-  if (*str == '[')
-    {
-      int reg;
+static void
+do_mav_triple (void)
+{
+  inst.instruction |= inst.operands[0].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 12;
+}
 
-      str++;
+/* Insns like "foo W,X,Y,Z".
+    where W=MVAX[0:3] and X,Y,Z=MVFX[0:15].  */
 
-      skip_whitespace (str);
+static void
+do_mav_quad (void)
+{
+  inst.instruction |= inst.operands[0].reg << 5;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
+  inst.instruction |= inst.operands[3].reg;
+}
 
-      if ((reg = reg_required_here (&str, 16)) == FAIL)
-	return;
+/* cfmvsc32<cond> DSPSC,MVDX[15:0].  */
+static void
+do_mav_dspsc (void)
+{
+  inst.instruction |= inst.operands[1].reg << 12;
+}
 
-      /* ldrt/strt always use post-indexed addressing, so if the base is
-	 the same as Rd, we warn.  */
-      if (conflict_reg == reg)
-	as_warn (_("%s register same as write-back base"),
-		 ((inst.instruction & LOAD_BIT)
-		  ? _("destination") : _("source")));
+/* Maverick shift immediate instructions.
+   cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
+   cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0].  */
 
-      skip_whitespace (str);
+static void
+do_mav_shift (void)
+{
+  int imm = inst.operands[2].imm;
 
-      if (*str == ']')
-	{
-	  str ++;
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
 
-	  if (skip_past_comma (&str) == SUCCESS)
-	    {
-	      /* [Rn],... (post inc)  */
-	      if (ldst_extend (&str) == FAIL)
-		return;
-	    }
-	  else
-	    {
-	      /* [Rn]  */
-	      skip_whitespace (str);
+  /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
+     Bits 5-7 of the insn should have bits 4-6 of the immediate.
+     Bit 4 should be 0.	 */
+  imm = (imm & 0xf) | ((imm & 0x70) << 1);
 
-	      /* Skip a write-back '!'.  */
-	      if (*str == '!')
-		str++;
+  inst.instruction |= imm;
+}
+
+/* XScale instructions.	 Also sorted arithmetic before move.  */
 
-	      inst.instruction |= INDEX_UP;
-	    }
-	}
-      else
-	{
-	  inst.error = _("post-indexed expression expected");
-	  return;
-	}
-    }
-  else
-    {
-      inst.error = _("post-indexed expression expected");
-      return;
-    }
+/* Xscale multiply-accumulate (argument parse)
+     MIAcc   acc0,Rm,Rs
+     MIAPHcc acc0,Rm,Rs
+     MIAxycc acc0,Rm,Rs.  */
 
-  end_of_line (str);
+static void
+do_xsc_mia (void)
+{
+  inst.instruction |= inst.operands[1].reg;
+  inst.instruction |= inst.operands[2].reg << 12;
 }
 
-static int
-ldst_extend_v4 (str)
-     char ** str;
+/* Xscale move-accumulator-register (argument parse)
+
+     MARcc   acc0,RdLo,RdHi.  */
+
+static void
+do_xsc_mar (void)
 {
-  int add = INDEX_UP;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
+}
 
-  switch (**str)
-    {
-    case '#':
-    case '$':
-      (*str)++;
-      if (my_get_expression (& inst.reloc.exp, str))
-	return FAIL;
+/* Xscale move-register-accumulator (argument parse)
 
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  int value = inst.reloc.exp.X_add_number;
+     MRAcc   RdLo,RdHi,acc0.  */
 
-	  if (value < -255 || value > 255)
-	    {
-	      inst.error = _("address offset too large");
-	      return FAIL;
-	    }
+static void
+do_xsc_mra (void)
+{
+  constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+}
+
+/* Encoding functions relevant only to Thumb.  */
 
-	  if (value < 0)
-	    {
-	      value = -value;
-	      add = 0;
-	    }
+/* inst.operands[i] is a shifted-register operand; encode
+   it into inst.instruction in the format used by Thumb32.  */
 
-	  /* Halfword and signextension instructions have the
-             immediate value split across bits 11..8 and bits 3..0.  */
-	  inst.instruction |= (add | HWOFFSET_IMM
-			       | ((value >> 4) << 8) | (value & 0xF));
-	}
-      else
-	{
-	  inst.instruction |= HWOFFSET_IMM;
-	  inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
-	  inst.reloc.pc_rel = 0;
-	}
-      return SUCCESS;
+static void
+encode_thumb32_shifted_operand (int i)
+{
+  unsigned int value = inst.reloc.exp.X_add_number;
+  unsigned int shift = inst.operands[i].shift_kind;
 
-    case '-':
-      add = 0;
-      /* Fall through.  */
+  constraint (inst.operands[i].immisreg,
+	      _("shift by register not allowed in thumb mode"));
+  inst.instruction |= inst.operands[i].reg;
+  if (shift == SHIFT_RRX)
+    inst.instruction |= SHIFT_ROR << 4;
+  else
+    {
+      constraint (inst.reloc.exp.X_op != O_constant,
+		  _("expression too complex"));
 
-    case '+':
-      (*str)++;
-      /* Fall through.  */
+      constraint (value > 32
+		  || (value == 32 && (shift == SHIFT_LSL
+				      || shift == SHIFT_ROR)),
+		  _("shift expression is too large"));
 
-    default:
-      if (reg_required_here (str, 0) == FAIL)
-	return FAIL;
+      if (value == 0)
+	shift = SHIFT_LSL;
+      else if (value == 32)
+	value = 0;
 
-      inst.instruction |= add;
-      return SUCCESS;
+      inst.instruction |= shift << 4;
+      inst.instruction |= (value & 0x1c) << 10;
+      inst.instruction |= (value & 0x03) << 6;
     }
 }
 
-/* Halfword and signed-byte load/store operations.  */
+
+/* inst.operands[i] was set up by parse_address.  Encode it into a
+   Thumb32 format load or store instruction.  Reject forms that cannot
+   be used with such instructions.  If is_t is true, reject forms that
+   cannot be used with a T instruction; if is_d is true, reject forms
+   that cannot be used with a D instruction.  */
+
 static void
-do_ldstv4 (str)
-     char *        str;
+encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
 {
-  int pre_inc = 0;
-  int conflict_reg;
-  int value;
+  bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
 
-  skip_whitespace (str);
+  constraint (!inst.operands[i].isreg,
+	      _("Instruction does not support =N addresses"));
 
-  if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
+  inst.instruction |= inst.operands[i].reg << 16;
+  if (inst.operands[i].immisreg)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      constraint (is_pc, _("cannot use register index with PC-relative addressing"));
+      constraint (is_t || is_d, _("cannot use register index with this instruction"));
+      constraint (inst.operands[i].negative,
+		  _("Thumb does not support negative register indexing"));
+      constraint (inst.operands[i].postind,
+		  _("Thumb does not support register post-indexing"));
+      constraint (inst.operands[i].writeback,
+		  _("Thumb does not support register indexing with writeback"));
+      constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
+		  _("Thumb supports only LSL in shifted register indexing"));
 
-  if (skip_past_comma (& str) == FAIL)
-    {
-      inst.error = _("address expected");
-      return;
+      inst.instruction |= inst.operands[i].imm;
+      if (inst.operands[i].shifted)
+	{
+	  constraint (inst.reloc.exp.X_op != O_constant,
+		      _("expression too complex"));
+	  constraint (inst.reloc.exp.X_add_number < 0
+		      || inst.reloc.exp.X_add_number > 3,
+		      _("shift out of range"));
+	  inst.instruction |= inst.reloc.exp.X_add_number << 4;
+	}
+      inst.reloc.type = BFD_RELOC_UNUSED;
     }
-
-  if (*str == '[')
+  else if (inst.operands[i].preind)
     {
-      int reg;
-
-      str++;
+      constraint (is_pc && inst.operands[i].writeback,
+		  _("cannot use writeback with PC-relative addressing"));
+      constraint (is_t && inst.operands[i].writeback,
+		  _("cannot use writeback with this instruction"));
 
-      skip_whitespace (str);
+      if (is_d)
+	{
+	  inst.instruction |= 0x01000000;
+	  if (inst.operands[i].writeback)
+	    inst.instruction |= 0x00200000;
+	}
+      else
+	{
+	  inst.instruction |= 0x00000c00;
+	  if (inst.operands[i].writeback)
+	    inst.instruction |= 0x00000100;
+	}
+      inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+    }
+  else if (inst.operands[i].postind)
+    {
+      assert (inst.operands[i].writeback);
+      constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
+      constraint (is_t, _("cannot use post-indexing with this instruction"));
 
-      if ((reg = reg_required_here (&str, 16)) == FAIL)
-	return;
+      if (is_d)
+	inst.instruction |= 0x00200000;
+      else
+	inst.instruction |= 0x00000900;
+      inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+    }
+  else /* unindexed - only for coprocessor */
+    inst.error = _("instruction does not accept unindexed addressing");
+}
+
+/* Table of Thumb instructions which exist in both 16- and 32-bit
+   encodings (the latter only in post-V6T2 cores).  The index is the
+   value used in the insns table below.  When there is more than one
+   possible 16-bit encoding for the instruction, this table always
+   holds variant (1).
+   Also contains several pseudo-instructions used during relaxation.  */
+#define T16_32_TAB				\
+  X(adc,   4140, eb400000),			\
+  X(adcs,  4140, eb500000),			\
+  X(add,   1c00, eb000000),			\
+  X(adds,  1c00, eb100000),			\
+  X(addi,  0000, f1000000),			\
+  X(addis, 0000, f1100000),			\
+  X(add_pc,000f, f20f0000),			\
+  X(add_sp,000d, f10d0000),			\
+  X(adr,   000f, f20f0000),			\
+  X(and,   4000, ea000000),			\
+  X(ands,  4000, ea100000),			\
+  X(asr,   1000, fa40f000),			\
+  X(asrs,  1000, fa50f000),			\
+  X(b,     e000, f000b000),			\
+  X(bcond, d000, f0008000),			\
+  X(bic,   4380, ea200000),			\
+  X(bics,  4380, ea300000),			\
+  X(cmn,   42c0, eb100f00),			\
+  X(cmp,   2800, ebb00f00),			\
+  X(cpsie, b660, f3af8400),			\
+  X(cpsid, b670, f3af8600),			\
+  X(cpy,   4600, ea4f0000),			\
+  X(dec_sp,80dd, f1bd0d00),			\
+  X(eor,   4040, ea800000),			\
+  X(eors,  4040, ea900000),			\
+  X(inc_sp,00dd, f10d0d00),			\
+  X(ldmia, c800, e8900000),			\
+  X(ldr,   6800, f8500000),			\
+  X(ldrb,  7800, f8100000),			\
+  X(ldrh,  8800, f8300000),			\
+  X(ldrsb, 5600, f9100000),			\
+  X(ldrsh, 5e00, f9300000),			\
+  X(ldr_pc,4800, f85f0000),			\
+  X(ldr_pc2,4800, f85f0000),			\
+  X(ldr_sp,9800, f85d0000),			\
+  X(lsl,   0000, fa00f000),			\
+  X(lsls,  0000, fa10f000),			\
+  X(lsr,   0800, fa20f000),			\
+  X(lsrs,  0800, fa30f000),			\
+  X(mov,   2000, ea4f0000),			\
+  X(movs,  2000, ea5f0000),			\
+  X(mul,   4340, fb00f000),                     \
+  X(muls,  4340, ffffffff), /* no 32b muls */	\
+  X(mvn,   43c0, ea6f0000),			\
+  X(mvns,  43c0, ea7f0000),			\
+  X(neg,   4240, f1c00000), /* rsb #0 */	\
+  X(negs,  4240, f1d00000), /* rsbs #0 */	\
+  X(orr,   4300, ea400000),			\
+  X(orrs,  4300, ea500000),			\
+  X(pop,   bc00, e8bd0000), /* ldmia sp!,... */	\
+  X(push,  b400, e92d0000), /* stmdb sp!,... */	\
+  X(rev,   ba00, fa90f080),			\
+  X(rev16, ba40, fa90f090),			\
+  X(revsh, bac0, fa90f0b0),			\
+  X(ror,   41c0, fa60f000),			\
+  X(rors,  41c0, fa70f000),			\
+  X(sbc,   4180, eb600000),			\
+  X(sbcs,  4180, eb700000),			\
+  X(stmia, c000, e8800000),			\
+  X(str,   6000, f8400000),			\
+  X(strb,  7000, f8000000),			\
+  X(strh,  8000, f8200000),			\
+  X(str_sp,9000, f84d0000),			\
+  X(sub,   1e00, eba00000),			\
+  X(subs,  1e00, ebb00000),			\
+  X(subi,  8000, f1a00000),			\
+  X(subis, 8000, f1b00000),			\
+  X(sxtb,  b240, fa4ff080),			\
+  X(sxth,  b200, fa0ff080),			\
+  X(tst,   4200, ea100f00),			\
+  X(uxtb,  b2c0, fa5ff080),			\
+  X(uxth,  b280, fa1ff080),			\
+  X(nop,   bf00, f3af8000),			\
+  X(yield, bf10, f3af8001),			\
+  X(wfe,   bf20, f3af8002),			\
+  X(wfi,   bf30, f3af8003),			\
+  X(sev,   bf40, f3af9004), /* typo, 8004? */
+
+/* To catch errors in encoding functions, the codes are all offset by
+   0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
+   as 16-bit instructions.  */
+#define X(a,b,c) T_MNEM_##a
+enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
+#undef X
+
+#define X(a,b,c) 0x##b
+static const unsigned short thumb_op16[] = { T16_32_TAB };
+#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
+#undef X
+
+#define X(a,b,c) 0x##c
+static const unsigned int thumb_op32[] = { T16_32_TAB };
+#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
+#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
+#undef X
+#undef T16_32_TAB
+
+/* Thumb instruction encoders, in alphabetical order.  */
+
+/* ADDW or SUBW.  */
+static void
+do_t_add_sub_w (void)
+{
+  int Rd, Rn;
+
+  Rd = inst.operands[0].reg;
+  Rn = inst.operands[1].reg;
+
+  constraint (Rd == 15, _("PC not allowed as destination"));
+  inst.instruction |= (Rn << 16) | (Rd << 8);
+  inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
+}
+
+/* Parse an add or subtract instruction.  We get here with inst.instruction
+   equalling any of THUMB_OPCODE_add, adds, sub, or subs.  */
+
+static void
+do_t_add_sub (void)
+{
+  int Rd, Rs, Rn;
 
-      /* Conflicts can occur on stores as well as loads.  */
-      conflict_reg = (conflict_reg == reg);
+  Rd = inst.operands[0].reg;
+  Rs = (inst.operands[1].present
+	? inst.operands[1].reg    /* Rd, Rs, foo */
+	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
 
-      skip_whitespace (str);
+  if (unified_syntax)
+    {
+      bfd_boolean flags;
+      bfd_boolean narrow;
+      int opcode;
 
-      if (*str == ']')
+      flags = (inst.instruction == T_MNEM_adds
+	       || inst.instruction == T_MNEM_subs);
+      if (flags)
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
+      if (!inst.operands[2].isreg)
 	{
-	  str ++;
-
-	  if (skip_past_comma (&str) == SUCCESS)
-	    {
-	      /* [Rn],... (post inc)  */
-	      if (ldst_extend_v4 (&str) == FAIL)
-		return;
-	      if (conflict_reg)
-		as_warn (_("%s register same as write-back base"),
-			 ((inst.instruction & LOAD_BIT)
-			  ? _("destination") : _("source")));
-	    }
-	  else
+	  opcode = 0;
+	  if (inst.size_req != 4)
 	    {
-	      /* [Rn]  */
-	      inst.instruction |= HWOFFSET_IMM;
-
-	      skip_whitespace (str);
-
-	      if (*str == '!')
+	      int add;
+
+	      add = (inst.instruction == T_MNEM_add
+		     || inst.instruction == T_MNEM_adds);
+	      /* Attempt to use a narrow opcode, with relaxation if
+	         appropriate.  */
+	      if (Rd == REG_SP && Rs == REG_SP && !flags)
+		opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
+	      else if (Rd <= 7 && Rs == REG_SP && add && !flags)
+		opcode = T_MNEM_add_sp;
+	      else if (Rd <= 7 && Rs == REG_PC && add && !flags)
+		opcode = T_MNEM_add_pc;
+	      else if (Rd <= 7 && Rs <= 7 && narrow)
 		{
-		  if (conflict_reg)
-		    as_warn (_("%s register same as write-back base"),
-			     ((inst.instruction & LOAD_BIT)
-			      ? _("destination") : _("source")));
-		  str++;
-		  inst.instruction |= WRITE_BACK;
+		  if (flags)
+		    opcode = add ? T_MNEM_addis : T_MNEM_subis;
+		  else
+		    opcode = add ? T_MNEM_addi : T_MNEM_subi;
 		}
-
-	      inst.instruction |= INDEX_UP;
-	      pre_inc = 1;
+	      if (opcode)
+		{
+		  inst.instruction = THUMB_OP16(opcode);
+		  inst.instruction |= (Rd << 4) | Rs;
+		  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+		  if (inst.size_req != 2)
+		    inst.relax = opcode;
+		}
+	      else
+		constraint (inst.size_req == 2, BAD_HIREG);
+	    }
+	  if (inst.size_req == 4
+	      || (inst.size_req != 2 && !opcode))
+	    {
+	      /* ??? Convert large immediates to addw/subw.  */
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	    }
 	}
       else
 	{
-	  /* [Rn,...]  */
-	  if (skip_past_comma (&str) == FAIL)
+	  Rn = inst.operands[2].reg;
+	  /* See if we can do this with a 16-bit instruction.  */
+	  if (!inst.operands[2].shifted && inst.size_req != 4)
 	    {
-	      inst.error = _("pre-indexed expression expected");
-	      return;
-	    }
-
-	  pre_inc = 1;
-	  if (ldst_extend_v4 (&str) == FAIL)
-	    return;
+	      if (Rd > 7 || Rs > 7 || Rn > 7)
+		narrow = FALSE;
 
-	  skip_whitespace (str);
-
-	  if (*str++ != ']')
-	    {
-	      inst.error = _("missing ]");
-	      return;
-	    }
-
-	  skip_whitespace (str);
+	      if (narrow)
+		{
+		  inst.instruction = ((inst.instruction == T_MNEM_adds
+				       || inst.instruction == T_MNEM_add)
+				      ? T_OPCODE_ADD_R3
+				      : T_OPCODE_SUB_R3);
+		  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
+		  return;
+		}
 
-	  if (*str == '!')
-	    {
-	      if (conflict_reg)
-		as_warn (_("%s register same as write-back base"),
-			 ((inst.instruction & LOAD_BIT)
-			  ? _("destination") : _("source")));
-	      str++;
-	      inst.instruction |= WRITE_BACK;
+	      if (inst.instruction == T_MNEM_add)
+		{
+		  if (Rd == Rs)
+		    {
+		      inst.instruction = T_OPCODE_ADD_HI;
+		      inst.instruction |= (Rd & 8) << 4;
+		      inst.instruction |= (Rd & 7);
+		      inst.instruction |= Rn << 3;
+		      return;
+		    }
+		  /* ... because addition is commutative! */
+		  else if (Rd == Rn)
+		    {
+		      inst.instruction = T_OPCODE_ADD_HI;
+		      inst.instruction |= (Rd & 8) << 4;
+		      inst.instruction |= (Rd & 7);
+		      inst.instruction |= Rs << 3;
+		      return;
+		    }
+		}
 	    }
+	  /* If we get here, it can't be done in 16 bits.  */
+	  constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
+		      _("shift must be constant"));
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= Rd << 8;
+	  inst.instruction |= Rs << 16;
+	  encode_thumb32_shifted_operand (2);
 	}
     }
-  else if (*str == '=')
+  else
     {
-      if ((inst.instruction & LOAD_BIT) == 0)
-	{
-	  inst.error = _("invalid pseudo operation");
-	  return;
-	}
-
-      /* XXX Does this work correctly for half-word/byte ops?  */
-      /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op.  */
-      str++;
-
-      skip_whitespace (str);
-
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
+      constraint (inst.instruction == T_MNEM_adds
+		  || inst.instruction == T_MNEM_subs,
+		  BAD_THUMB32);
 
-      if (inst.reloc.exp.X_op != O_constant
-	  && inst.reloc.exp.X_op != O_symbol)
+      if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
 	{
-	  inst.error = _("constant expression expected");
+	  constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
+		      || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
+		      BAD_HIREG);
+
+	  inst.instruction = (inst.instruction == T_MNEM_add
+			      ? 0x0000 : 0x8000);
+	  inst.instruction |= (Rd << 4) | Rs;
+	  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
 	  return;
 	}
 
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  value = validate_immediate (inst.reloc.exp.X_add_number);
+      Rn = inst.operands[2].reg;
+      constraint (inst.operands[2].shifted, _("unshifted register required"));
 
-	  if (value != FAIL)
-	    {
-	      /* This can be done with a mov instruction.  */
-	      inst.instruction &= LITERAL_MASK;
-	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
-	      inst.instruction |= value & 0xfff;
-	      end_of_line (str);
-	      return;
-	    }
-
-	  value = validate_immediate (~ inst.reloc.exp.X_add_number);
-
-	  if (value != FAIL)
-	    {
-	      /* This can be done with a mvn instruction.  */
-	      inst.instruction &= LITERAL_MASK;
-	      inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
-	      inst.instruction |= value & 0xfff;
-	      end_of_line (str);
-	      return;
-	    }
+      /* We now have Rd, Rs, and Rn set to registers.  */
+      if (Rd > 7 || Rs > 7 || Rn > 7)
+	{
+	  /* Can't do this for SUB.	 */
+	  constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
+	  inst.instruction = T_OPCODE_ADD_HI;
+	  inst.instruction |= (Rd & 8) << 4;
+	  inst.instruction |= (Rd & 7);
+	  if (Rs == Rd)
+	    inst.instruction |= Rn << 3;
+	  else if (Rn == Rd)
+	    inst.instruction |= Rs << 3;
+	  else
+	    constraint (1, _("dest must overlap one source register"));
 	}
-
-      /* Insert into literal pool.  */
-      if (add_to_lit_pool () == FAIL)
+      else
 	{
-	  if (!inst.error)
-	    inst.error = _("literal pool insertion failed");
-	  return;
+	  inst.instruction = (inst.instruction == T_MNEM_add
+			      ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
+	  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
 	}
+    }
+}
 
-      /* Change the instruction exp to point to the pool.  */
-      inst.instruction |= HWOFFSET_IMM;
-      inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
+static void
+do_t_adr (void)
+{
+  if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
+    {
+      /* Defer to section relaxation.  */
+      inst.relax = inst.instruction;
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 4;
+    }
+  else if (unified_syntax && inst.size_req != 2)
+    {
+      /* Generate a 32-bit opcode.  */
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
       inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = 1;
     }
   else
     {
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
-
-      inst.instruction |= HWOFFSET_IMM;
-      inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
-#ifndef TE_WINCE
-      /* PC rel adjust.  */
-      inst.reloc.exp.X_add_number -= 8;
-#endif
+      /* Generate a 16-bit opcode.  */
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+      inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
       inst.reloc.pc_rel = 1;
-      inst.instruction |= (REG_PC << 16);
-      pre_inc = 1;
-    }
 
-  inst.instruction |= (pre_inc ? PRE_INDEX : 0);
-  end_of_line (str);
+      inst.instruction |= inst.operands[0].reg << 4;
+    }
 }
 
-static long
-reg_list (strp)
-     char ** strp;
+/* Arithmetic instructions for which there is just one 16-bit
+   instruction encoding, and it allows only two low registers.
+   For maximal compatibility with ARM syntax, we allow three register
+   operands even when Thumb-32 instructions are not available, as long
+   as the first two are identical.  For instance, both "sbc r0,r1" and
+   "sbc r0,r0,r1" are allowed.  */
+static void
+do_t_arit3 (void)
 {
-  char * str = * strp;
-  long   range = 0;
-  int    another_range;
+  int Rd, Rs, Rn;
 
-  /* We come back here if we get ranges concatenated by '+' or '|'.  */
-  do
-    {
-      another_range = 0;
+  Rd = inst.operands[0].reg;
+  Rs = (inst.operands[1].present
+	? inst.operands[1].reg    /* Rd, Rs, foo */
+	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
+  Rn = inst.operands[2].reg;
 
-      if (*str == '{')
+  if (unified_syntax)
+    {
+      if (!inst.operands[2].isreg)
 	{
-	  int in_range = 0;
-	  int cur_reg = -1;
+	  /* For an immediate, we always generate a 32-bit opcode;
+	     section relaxation will shrink it later if possible.  */
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	  inst.instruction |= Rd << 8;
+	  inst.instruction |= Rs << 16;
+	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	{
+	  bfd_boolean narrow;
 
-	  str++;
-	  do
-	    {
-	      int reg;
+	  /* See if we can do this with a 16-bit instruction.  */
+	  if (THUMB_SETS_FLAGS (inst.instruction))
+	    narrow = current_it_mask == 0;
+	  else
+	    narrow = current_it_mask != 0;
 
-	      skip_whitespace (str);
+	  if (Rd > 7 || Rn > 7 || Rs > 7)
+	    narrow = FALSE;
+	  if (inst.operands[2].shifted)
+	    narrow = FALSE;
+	  if (inst.size_req == 4)
+	    narrow = FALSE;
 
-	      if ((reg = reg_required_here (& str, -1)) == FAIL)
-		return FAIL;
+	  if (narrow
+	      && Rd == Rs)
+	    {
+	      inst.instruction = THUMB_OP16 (inst.instruction);
+	      inst.instruction |= Rd;
+	      inst.instruction |= Rn << 3;
+	      return;
+	    }
 
-	      if (in_range)
-		{
-		  int i;
+	  /* If we get here, it can't be done in 16 bits.  */
+	  constraint (inst.operands[2].shifted
+		      && inst.operands[2].immisreg,
+		      _("shift must be constant"));
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= Rd << 8;
+	  inst.instruction |= Rs << 16;
+	  encode_thumb32_shifted_operand (2);
+	}
+    }
+  else
+    {
+      /* On its face this is a lie - the instruction does set the
+	 flags.  However, the only supported mnemonic in this mode
+	 says it doesn't.  */
+      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
 
-		  if (reg <= cur_reg)
-		    {
-		      inst.error = _("bad range in register list");
-		      return FAIL;
-		    }
+      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
+		  _("unshifted register required"));
+      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
+      constraint (Rd != Rs,
+		  _("dest and source1 must be the same register"));
 
-		  for (i = cur_reg + 1; i < reg; i++)
-		    {
-		      if (range & (1 << i))
-			as_tsktsk
-			  (_("Warning: duplicated register (r%d) in register list"),
-			   i);
-		      else
-			range |= 1 << i;
-		    }
-		  in_range = 0;
-		}
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= Rd;
+      inst.instruction |= Rn << 3;
+    }
+}
 
-	      if (range & (1 << reg))
-		as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
-			   reg);
-	      else if (reg <= cur_reg)
-		as_tsktsk (_("Warning: register range not in ascending order"));
+/* Similarly, but for instructions where the arithmetic operation is
+   commutative, so we can allow either of them to be different from
+   the destination operand in a 16-bit instruction.  For instance, all
+   three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
+   accepted.  */
+static void
+do_t_arit3c (void)
+{
+  int Rd, Rs, Rn;
 
-	      range |= 1 << reg;
-	      cur_reg = reg;
-	    }
-	  while (skip_past_comma (&str) != FAIL
-		 || (in_range = 1, *str++ == '-'));
-	  str--;
-	  skip_whitespace (str);
+  Rd = inst.operands[0].reg;
+  Rs = (inst.operands[1].present
+	? inst.operands[1].reg    /* Rd, Rs, foo */
+	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
+  Rn = inst.operands[2].reg;
 
-	  if (*str++ != '}')
-	    {
-	      inst.error = _("missing `}'");
-	      return FAIL;
-	    }
+  if (unified_syntax)
+    {
+      if (!inst.operands[2].isreg)
+	{
+	  /* For an immediate, we always generate a 32-bit opcode;
+	     section relaxation will shrink it later if possible.  */
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	  inst.instruction |= Rd << 8;
+	  inst.instruction |= Rs << 16;
+	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
 	}
       else
 	{
-	  expressionS expr;
+	  bfd_boolean narrow;
 
-	  if (my_get_expression (&expr, &str))
-	    return FAIL;
+	  /* See if we can do this with a 16-bit instruction.  */
+	  if (THUMB_SETS_FLAGS (inst.instruction))
+	    narrow = current_it_mask == 0;
+	  else
+	    narrow = current_it_mask != 0;
 
-	  if (expr.X_op == O_constant)
-	    {
-	      if (expr.X_add_number
-		  != (expr.X_add_number & 0x0000ffff))
-		{
-		  inst.error = _("invalid register mask");
-		  return FAIL;
-		}
+	  if (Rd > 7 || Rn > 7 || Rs > 7)
+	    narrow = FALSE;
+	  if (inst.operands[2].shifted)
+	    narrow = FALSE;
+	  if (inst.size_req == 4)
+	    narrow = FALSE;
 
-	      if ((range & expr.X_add_number) != 0)
+	  if (narrow)
+	    {
+	      if (Rd == Rs)
 		{
-		  int regno = range & expr.X_add_number;
-
-		  regno &= -regno;
-		  regno = (1 << regno) - 1;
-		  as_tsktsk
-		    (_("Warning: duplicated register (r%d) in register list"),
-		     regno);
+		  inst.instruction = THUMB_OP16 (inst.instruction);
+		  inst.instruction |= Rd;
+		  inst.instruction |= Rn << 3;
+		  return;
 		}
-
-	      range |= expr.X_add_number;
-	    }
-	  else
-	    {
-	      if (inst.reloc.type != 0)
+	      if (Rd == Rn)
 		{
-		  inst.error = _("expression too complex");
-		  return FAIL;
+		  inst.instruction = THUMB_OP16 (inst.instruction);
+		  inst.instruction |= Rd;
+		  inst.instruction |= Rs << 3;
+		  return;
 		}
-
-	      memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
-	      inst.reloc.type = BFD_RELOC_ARM_MULTI;
-	      inst.reloc.pc_rel = 0;
 	    }
-	}
 
-      skip_whitespace (str);
-
-      if (*str == '|' || *str == '+')
-	{
-	  str++;
-	  another_range = 1;
+	  /* If we get here, it can't be done in 16 bits.  */
+	  constraint (inst.operands[2].shifted
+		      && inst.operands[2].immisreg,
+		      _("shift must be constant"));
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= Rd << 8;
+	  inst.instruction |= Rs << 16;
+	  encode_thumb32_shifted_operand (2);
 	}
     }
-  while (another_range);
-
-  *strp = str;
-  return range;
-}
-
-static void
-do_ldmstm (str)
-     char * str;
-{
-  int base_reg;
-  long range;
-
-  skip_whitespace (str);
-
-  if ((base_reg = reg_required_here (&str, 16)) == FAIL)
-    return;
-
-  if (base_reg == REG_PC)
+  else
     {
-      inst.error = _("r15 not allowed as base register");
-      return;
-    }
+      /* On its face this is a lie - the instruction does set the
+	 flags.  However, the only supported mnemonic in this mode
+	 says it doesn't.  */
+      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
 
-  skip_whitespace (str);
+      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
+		  _("unshifted register required"));
+      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
 
-  if (*str == '!')
-    {
-      inst.instruction |= WRITE_BACK;
-      str++;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || (range = reg_list (&str)) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= Rd;
 
-  if (*str == '^')
-    {
-      str++;
-      inst.instruction |= LDM_TYPE_2_OR_3;
+      if (Rd == Rs)
+	inst.instruction |= Rn << 3;
+      else if (Rd == Rn)
+	inst.instruction |= Rs << 3;
+      else
+	constraint (1, _("dest must overlap one source register"));
     }
+}
 
-  if (inst.instruction & WRITE_BACK)
+static void
+do_t_barrier (void)
+{
+  if (inst.operands[0].present)
     {
-      /* Check for unpredictable uses of writeback.  */
-      if (inst.instruction & LOAD_BIT)
-	{
-	  /* Not allowed in LDM type 2.  */
-	  if ((inst.instruction & LDM_TYPE_2_OR_3)
-	      && ((range & (1 << REG_PC)) == 0))
-	    as_warn (_("writeback of base register is UNPREDICTABLE"));
-	  /* Only allowed if base reg not in list for other types.  */
-	  else if (range & (1 << base_reg))
-	    as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
-	}
-      else /* STM.  */
-	{
-	  /* Not allowed for type 2.  */
-	  if (inst.instruction & LDM_TYPE_2_OR_3)
-	    as_warn (_("writeback of base register is UNPREDICTABLE"));
-	  /* Only allowed if base reg not in list, or first in list.  */
-	  else if ((range & (1 << base_reg))
-		   && (range & ((1 << base_reg) - 1)))
-	    as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
-	}
+      constraint ((inst.instruction & 0xf0) != 0x40
+		  && inst.operands[0].imm != 0xf,
+		  "bad barrier type");
+      inst.instruction |= inst.operands[0].imm;
     }
-
-  inst.instruction |= range;
-  end_of_line (str);
+  else
+    inst.instruction |= 0xf;
 }
 
 static void
-do_swi (str)
-     char * str;
+do_t_bfc (void)
 {
-  skip_whitespace (str);
-
-  /* Allow optional leading '#'.  */
-  if (is_immediate_prefix (*str))
-    str++;
-
-  if (my_get_expression (& inst.reloc.exp, & str))
-    return;
-
-  inst.reloc.type = BFD_RELOC_ARM_SWI;
-  inst.reloc.pc_rel = 0;
-  end_of_line (str);
+  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
+  constraint (msb > 32, _("bit-field extends past end of register"));
+  /* The instruction encoding stores the LSB and MSB,
+     not the LSB and width.  */
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
+  inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
+  inst.instruction |= msb - 1;
 }
 
 static void
-do_swap (str)
-     char * str;
+do_t_bfi (void)
 {
-  int reg;
-
-  skip_whitespace (str);
-
-  if ((reg = reg_required_here (&str, 12)) == FAIL)
-    return;
-
-  if (reg == REG_PC)
-    {
-      inst.error = _("r15 not allowed in swap");
-      return;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || (reg = reg_required_here (&str, 0)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  if (reg == REG_PC)
-    {
-      inst.error = _("r15 not allowed in swap");
-      return;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || *str++ != '[')
-    {
-      inst.error = BAD_ARGS;
-      return;
-    }
+  unsigned int msb;
 
-  skip_whitespace (str);
+  /* #0 in second position is alternative syntax for bfc, which is
+     the same instruction but with REG_PC in the Rm field.  */
+  if (!inst.operands[1].isreg)
+    inst.operands[1].reg = REG_PC;
 
-  if ((reg = reg_required_here (&str, 16)) == FAIL)
-    return;
-
-  if (reg == REG_PC)
-    {
-      inst.error = BAD_PC;
-      return;
-    }
-
-  skip_whitespace (str);
-
-  if (*str++ != ']')
-    {
-      inst.error = _("missing ]");
-      return;
-    }
-
-  end_of_line (str);
+  msb = inst.operands[2].imm + inst.operands[3].imm;
+  constraint (msb > 32, _("bit-field extends past end of register"));
+  /* The instruction encoding stores the LSB and MSB,
+     not the LSB and width.  */
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
+  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
+  inst.instruction |= msb - 1;
 }
 
 static void
-do_branch (str)
-     char * str;
+do_t_bfx (void)
 {
-  if (my_get_expression (&inst.reloc.exp, &str))
-    return;
+  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
+	      _("bit-field extends past end of register"));
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
+  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
+  inst.instruction |= inst.operands[3].imm - 1;
+}
 
-#ifdef OBJ_ELF
-  {
-    char * save_in;
-
-    /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
-       required for the instruction.  */
-
-    /* arm_parse_reloc () works on input_line_pointer.
-       We actually want to parse the operands to the branch instruction
-       passed in 'str'.  Save the input pointer and restore it later.  */
-    save_in = input_line_pointer;
-    input_line_pointer = str;
-    if (inst.reloc.exp.X_op == O_symbol
-	&& *str == '('
-	&& arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
-      {
-	inst.reloc.type   = BFD_RELOC_ARM_PLT32;
-	inst.reloc.pc_rel = 0;
-	/* Modify str to point to after parsed operands, otherwise
-	   end_of_line() will complain about the (PLT) left in str.  */
-	str = input_line_pointer;
-      }
-    else
-      {
-	inst.reloc.type   = BFD_RELOC_ARM_PCREL_BRANCH;
-	inst.reloc.pc_rel = 1;
-      }
-    input_line_pointer = save_in;
-  }
-#else
-  inst.reloc.type   = BFD_RELOC_ARM_PCREL_BRANCH;
-  inst.reloc.pc_rel = 1;
-#endif /* OBJ_ELF  */
+/* ARM V5 Thumb BLX (argument parse)
+	BLX <target_addr>	which is BLX(1)
+	BLX <Rm>		which is BLX(2)
+   Unfortunately, there are two different opcodes for this mnemonic.
+   So, the insns[].value is not used, and the code here zaps values
+	into inst.instruction.
 
-  end_of_line (str);
-}
+   ??? How to take advantage of the additional two bits of displacement
+   available in Thumb32 mode?  Need new relocation?  */
 
 static void
-do_bx (str)
-     char * str;
+do_t_blx (void)
 {
-  int reg;
-
-  skip_whitespace (str);
-
-  if ((reg = reg_required_here (&str, 0)) == FAIL)
+  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+  if (inst.operands[0].isreg)
+    /* We have a register, so this is BLX(2).  */
+    inst.instruction |= inst.operands[0].reg << 3;
+  else
     {
-      inst.error = BAD_ARGS;
-      return;
+      /* No register.  This must be BLX(1).  */
+      inst.instruction = 0xf000e800;
+#ifdef OBJ_ELF
+      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
+	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
+      else
+#endif
+	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
+      inst.reloc.pc_rel = 1;
     }
-
-  /* Note - it is not illegal to do a "bx pc".  Useless, but not illegal.  */
-  if (reg == REG_PC)
-    as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
-
-  end_of_line (str);
 }
 
 static void
-do_cdp (str)
-     char * str;
+do_t_branch (void)
 {
-  /* Co-processor data operation.
-     Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>}  */
-  skip_whitespace (str);
-
-  if (co_proc_number (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || cp_opc_expr (&str, 20,4) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  int opcode;
+  int cond;
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 12) == FAIL)
+  if (current_it_mask)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      /* Conditional branches inside IT blocks are encoded as unconditional
+         branches.  */
+      cond = COND_ALWAYS;
+      /* A branch must be the last instruction in an IT block.  */
+      constraint (current_it_mask != 0x10, BAD_BRANCH);
     }
+  else
+    cond = inst.cond;
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 16) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  if (cond != COND_ALWAYS)
+    opcode = T_MNEM_bcond;
+  else
+    opcode = inst.instruction;
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 0) == FAIL)
+  if (unified_syntax && inst.size_req == 4)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = THUMB_OP32(opcode);
+      if (cond == COND_ALWAYS)
+	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
+      else
+	{
+	  assert (cond != 0xF);
+	  inst.instruction |= cond << 22;
+	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
+	}
     }
-
-  if (skip_past_comma (&str) == SUCCESS)
+  else
     {
-      if (cp_opc_expr (&str, 5, 3) == FAIL)
+      inst.instruction = THUMB_OP16(opcode);
+      if (cond == COND_ALWAYS)
+	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
+      else
 	{
-	  if (!inst.error)
-	    inst.error = BAD_ARGS;
-	  return;
+	  inst.instruction |= cond << 8;
+	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
 	}
+      /* Allow section relaxation.  */
+      if (unified_syntax && inst.size_req != 2)
+	inst.relax = opcode;
     }
 
-  end_of_line (str);
+  inst.reloc.pc_rel = 1;
 }
 
 static void
-do_lstc (str)
-     char * str;
+do_t_bkpt (void)
 {
-  /* Co-processor register load/store.
-     Format: <LDC|STC{cond}[L] CP#,CRd,<address>  */
-
-  skip_whitespace (str);
-
-  if (co_proc_number (&str) == FAIL)
+  constraint (inst.cond != COND_ALWAYS,
+	      _("instruction is always unconditional"));
+  if (inst.operands[0].present)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (inst.operands[0].imm > 255,
+		  _("immediate value out of range"));
+      inst.instruction |= inst.operands[0].imm;
     }
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_t_branch23 (void)
+{
+  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+  inst.reloc.type   = BFD_RELOC_THUMB_PCREL_BRANCH23;
+  inst.reloc.pc_rel = 1;
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_address_required_here (&str, CP_WB_OK) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  /* If the destination of the branch is a defined symbol which does not have
+     the THUMB_FUNC attribute, then we must be calling a function which has
+     the (interfacearm) attribute.  We look for the Thumb entry point to that
+     function and change the branch to refer to that function instead.	*/
+  if (	 inst.reloc.exp.X_op == O_symbol
+      && inst.reloc.exp.X_add_symbol != NULL
+      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
+      && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
+    inst.reloc.exp.X_add_symbol =
+      find_real_start (inst.reloc.exp.X_add_symbol);
+}
 
-  end_of_line (str);
+static void
+do_t_bx (void)
+{
+  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+  inst.instruction |= inst.operands[0].reg << 3;
+  /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC.	 The reloc
+     should cause the alignment to be checked once it is known.	 This is
+     because BX PC only works if the instruction is word aligned.  */
 }
 
 static void
-do_co_reg (str)
-     char * str;
+do_t_bxj (void)
 {
-  /* Co-processor register transfer.
-     Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>}  */
+  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+  if (inst.operands[0].reg == REG_PC)
+    as_tsktsk (_("use of r15 in bxj is not really useful"));
 
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].reg << 16;
+}
 
-  if (co_proc_number (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_t_clz (void)
+{
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[1].reg;
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_opc_expr (&str, 21, 3) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_t_cps (void)
+{
+  constraint (current_it_mask, BAD_NOT_IT);
+  inst.instruction |= inst.operands[0].imm;
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL)
+static void
+do_t_cpsi (void)
+{
+  constraint (current_it_mask, BAD_NOT_IT);
+  if (unified_syntax
+      && (inst.operands[1].present || inst.size_req == 4)
+      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      unsigned int imod = (inst.instruction & 0x0030) >> 4;
+      inst.instruction = 0xf3af8000;
+      inst.instruction |= imod << 9;
+      inst.instruction |= inst.operands[0].imm << 5;
+      if (inst.operands[1].present)
+	inst.instruction |= 0x100 | inst.operands[1].imm;
     }
-
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 16) == FAIL)
+  else
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
+		  && (inst.operands[0].imm & 4),
+		  _("selected processor does not support 'A' form "
+		    "of this instruction"));
+      constraint (inst.operands[1].present || inst.size_req == 4,
+		  _("Thumb does not support the 2-argument "
+		    "form of this instruction"));
+      inst.instruction |= inst.operands[0].imm;
     }
+}
+
+/* THUMB CPY instruction (argument parse).  */
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_reg_required_here (&str, 0) == FAIL)
+static void
+do_t_cpy (void)
+{
+  if (inst.size_req == 4)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = THUMB_OP32 (T_MNEM_mov);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.instruction |= inst.operands[1].reg;
     }
-
-  if (skip_past_comma (&str) == SUCCESS)
+  else
     {
-      if (cp_opc_expr (&str, 5, 3) == FAIL)
-	{
-	  if (!inst.error)
-	    inst.error = BAD_ARGS;
-	  return;
-	}
+      inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
+      inst.instruction |= (inst.operands[0].reg & 0x7);
+      inst.instruction |= inst.operands[1].reg << 3;
     }
-
-  end_of_line (str);
 }
 
 static void
-do_fpa_ctrl (str)
-     char * str;
+do_t_czb (void)
 {
-  /* FP control registers.
-     Format: <WFS|RFS|WFC|RFC>{cond} Rn  */
-
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  constraint (current_it_mask, BAD_NOT_IT);
+  constraint (inst.operands[0].reg > 7, BAD_HIREG);
+  inst.instruction |= inst.operands[0].reg;
+  inst.reloc.pc_rel = 1;
+  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
 }
 
 static void
-do_fpa_ldst (str)
-     char * str;
+do_t_dbg (void)
 {
-  skip_whitespace (str);
-
-  if (fp_reg_required_here (&str, 12) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  inst.instruction |= inst.operands[0].imm;
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_address_required_here (&str, CP_WB_OK) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+static void
+do_t_div (void)
+{
+  if (!inst.operands[1].present)
+    inst.operands[1].reg = inst.operands[0].reg;
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+}
 
-  end_of_line (str);
+static void
+do_t_hint (void)
+{
+  if (unified_syntax && inst.size_req == 4)
+    inst.instruction = THUMB_OP32 (inst.instruction);
+  else
+    inst.instruction = THUMB_OP16 (inst.instruction);
 }
 
 static void
-do_fpa_ldmstm (str)
-     char * str;
+do_t_it (void)
 {
-  int num_regs;
+  unsigned int cond = inst.operands[0].imm;
 
-  skip_whitespace (str);
+  constraint (current_it_mask, BAD_NOT_IT);
+  current_it_mask = (inst.instruction & 0xf) | 0x10;
+  current_cc = cond;
 
-  if (fp_reg_required_here (&str, 12) == FAIL)
+  /* If the condition is a negative condition, invert the mask.  */
+  if ((cond & 0x1) == 0x0)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      unsigned int mask = inst.instruction & 0x000f;
 
-  /* Get Number of registers to transfer.  */
-  if (skip_past_comma (&str) == FAIL
-      || my_get_expression (&inst.reloc.exp, &str))
-    {
-      if (! inst.error)
-	inst.error = _("constant expression expected");
-      return;
-    }
+      if ((mask & 0x7) == 0)
+	/* no conversion needed */;
+      else if ((mask & 0x3) == 0)
+	mask ^= 0x8;
+      else if ((mask & 0x1) == 0)
+	mask ^= 0xC;
+      else
+	mask ^= 0xE;
 
-  if (inst.reloc.exp.X_op != O_constant)
-    {
-      inst.error = _("constant value required for number of registers");
-      return;
+      inst.instruction &= 0xfff0;
+      inst.instruction |= mask;
     }
 
-  num_regs = inst.reloc.exp.X_add_number;
-
-  if (num_regs < 1 || num_regs > 4)
-    {
-      inst.error = _("number of registers must be in the range [1:4]");
-      return;
-    }
+  inst.instruction |= cond << 4;
+}
 
-  switch (num_regs)
-    {
-    case 1:
-      inst.instruction |= CP_T_X;
-      break;
-    case 2:
-      inst.instruction |= CP_T_Y;
-      break;
-    case 3:
-      inst.instruction |= CP_T_Y | CP_T_X;
-      break;
-    case 4:
-      break;
-    default:
-      abort ();
-    }
+static void
+do_t_ldmstm (void)
+{
+  /* This really doesn't seem worth it.  */
+  constraint (inst.reloc.type != BFD_RELOC_UNUSED,
+	      _("expression too complex"));
+  constraint (inst.operands[1].writeback,
+	      _("Thumb load/store multiple does not support {reglist}^"));
 
-  if (inst.instruction & (CP_T_Pre | CP_T_UD)) /* ea/fd format.  */
+  if (unified_syntax)
     {
-      int reg;
-      int write_back;
-      int offset;
-
-      /* The instruction specified "ea" or "fd", so we can only accept
-	 [Rn]{!}.  The instruction does not really support stacking or
-	 unstacking, so we have to emulate these by setting appropriate
-	 bits and offsets.  */
-      if (skip_past_comma (&str) == FAIL
-	  || *str != '[')
-	{
-	  if (! inst.error)
-	    inst.error = BAD_ARGS;
-	  return;
-	}
-
-      str++;
-      skip_whitespace (str);
-
-      if ((reg = reg_required_here (&str, 16)) == FAIL)
-	return;
-
-      skip_whitespace (str);
-
-      if (*str != ']')
+      /* See if we can use a 16-bit instruction.  */
+      if (inst.instruction < 0xffff /* not ldmdb/stmdb */
+	  && inst.size_req != 4
+	  && inst.operands[0].reg <= 7
+	  && !(inst.operands[1].imm & ~0xff)
+	  && (inst.instruction == T_MNEM_stmia
+	      ? inst.operands[0].writeback
+	      : (inst.operands[0].writeback
+		 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
 	{
-	  inst.error = BAD_ARGS;
-	  return;
-	}
+	  if (inst.instruction == T_MNEM_stmia
+	      && (inst.operands[1].imm & (1 << inst.operands[0].reg))
+	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
+	    as_warn (_("value stored for r%d is UNPREDICTABLE"),
+		     inst.operands[0].reg);
 
-      str++;
-      if (*str == '!')
-	{
-	  write_back = 1;
-	  str++;
-	  if (reg == REG_PC)
-	    {
-	      inst.error =
-		_("r15 not allowed as base register with write-back");
-	      return;
-	    }
+	  inst.instruction = THUMB_OP16 (inst.instruction);
+	  inst.instruction |= inst.operands[0].reg << 8;
+	  inst.instruction |= inst.operands[1].imm;
 	}
       else
-	write_back = 0;
-
-      if (inst.instruction & CP_T_Pre)
 	{
-	  /* Pre-decrement.  */
-	  offset = 3 * num_regs;
-	  if (write_back)
-	    inst.instruction |= CP_T_WB;
-	}
-      else
-	{
-	  /* Post-increment.  */
-	  if (write_back)
+	  if (inst.operands[1].imm & (1 << 13))
+	    as_warn (_("SP should not be in register list"));
+	  if (inst.instruction == T_MNEM_stmia)
 	    {
-	      inst.instruction |= CP_T_WB;
-	      offset = 3 * num_regs;
+	      if (inst.operands[1].imm & (1 << 15))
+		as_warn (_("PC should not be in register list"));
+	      if (inst.operands[1].imm & (1 << inst.operands[0].reg))
+		as_warn (_("value stored for r%d is UNPREDICTABLE"),
+			 inst.operands[0].reg);
 	    }
 	  else
 	    {
-	      /* No write-back, so convert this into a standard pre-increment
-		 instruction -- aesthetically more pleasing.  */
-	      inst.instruction |= CP_T_Pre | CP_T_UD;
-	      offset = 0;
+	      if (inst.operands[1].imm & (1 << 14)
+		  && inst.operands[1].imm & (1 << 15))
+		as_warn (_("LR and PC should not both be in register list"));
+	      if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
+		  && inst.operands[0].writeback)
+		as_warn (_("base register should not be in register list "
+			   "when written back"));
 	    }
+	  if (inst.instruction < 0xffff)
+	    inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= inst.operands[0].reg << 16;
+	  inst.instruction |= inst.operands[1].imm;
+	  if (inst.operands[0].writeback)
+	    inst.instruction |= WRITE_BACK;
 	}
-
-      inst.instruction |= offset;
     }
-  else if (skip_past_comma (&str) == FAIL
-	   || cp_address_required_here (&str, CP_WB_OK) == FAIL)
+  else
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      constraint (inst.operands[0].reg > 7
+		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
+      if (inst.instruction == T_MNEM_stmia)
+	{
+	  if (!inst.operands[0].writeback)
+	    as_warn (_("this instruction will write back the base register"));
+	  if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
+	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
+	    as_warn (_("value stored for r%d is UNPREDICTABLE"),
+		     inst.operands[0].reg);
+	}
+      else
+	{
+	  if (!inst.operands[0].writeback
+	      && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
+	    as_warn (_("this instruction will write back the base register"));
+	  else if (inst.operands[0].writeback
+		   && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
+	    as_warn (_("this instruction will not write back the base register"));
+	}
 
-  end_of_line (str);
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.instruction |= inst.operands[1].imm;
+    }
 }
 
 static void
-do_fpa_dyadic (str)
-     char * str;
+do_t_ldrex (void)
 {
-  skip_whitespace (str);
-
-  if (fp_reg_required_here (&str, 12) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
+	      || inst.operands[1].postind || inst.operands[1].writeback
+	      || inst.operands[1].immisreg || inst.operands[1].shifted
+	      || inst.operands[1].negative,
+	      BAD_ADDR_MODE);
 
-  if (skip_past_comma (&str) == FAIL
-      || fp_reg_required_here (&str, 16) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
+}
 
-  if (skip_past_comma (&str) == FAIL
-      || fp_op2 (&str) == FAIL)
+static void
+do_t_ldrexd (void)
+{
+  if (!inst.operands[1].present)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (inst.operands[0].reg == REG_LR,
+		  _("r14 not allowed as first register "
+		    "when second register is omitted"));
+      inst.operands[1].reg = inst.operands[0].reg + 1;
     }
+  constraint (inst.operands[0].reg == inst.operands[1].reg,
+	      BAD_OVERLAP);
 
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 8;
+  inst.instruction |= inst.operands[2].reg << 16;
 }
 
 static void
-do_fpa_monadic (str)
-     char * str;
+do_t_ldst (void)
 {
-  skip_whitespace (str);
+  unsigned long opcode;
+  int Rn;
 
-  if (fp_reg_required_here (&str, 12) == FAIL)
+  opcode = inst.instruction;
+  if (unified_syntax)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      if (!inst.operands[1].isreg)
+	{
+	  if (opcode <= 0xffff)
+	    inst.instruction = THUMB_OP32 (opcode);
+	  if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+	    return;
+	}
+      if (inst.operands[1].isreg
+	  && !inst.operands[1].writeback
+	  && !inst.operands[1].shifted && !inst.operands[1].postind
+	  && !inst.operands[1].negative && inst.operands[0].reg <= 7
+	  && opcode <= 0xffff
+	  && inst.size_req != 4)
+	{
+	  /* Insn may have a 16-bit form.  */
+	  Rn = inst.operands[1].reg;
+	  if (inst.operands[1].immisreg)
+	    {
+	      inst.instruction = THUMB_OP16 (opcode);
+	      /* [Rn, Ri] */
+	      if (Rn <= 7 && inst.operands[1].imm <= 7)
+		goto op16;
+	    }
+	  else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
+		    && opcode != T_MNEM_ldrsb)
+		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
+		   || (Rn == REG_SP && opcode == T_MNEM_str))
+	    {
+	      /* [Rn, #const] */
+	      if (Rn > 7)
+		{
+		  if (Rn == REG_PC)
+		    {
+		      if (inst.reloc.pc_rel)
+			opcode = T_MNEM_ldr_pc2;
+		      else
+			opcode = T_MNEM_ldr_pc;
+		    }
+		  else
+		    {
+		      if (opcode == T_MNEM_ldr)
+			opcode = T_MNEM_ldr_sp;
+		      else
+			opcode = T_MNEM_str_sp;
+		    }
+		  inst.instruction = inst.operands[0].reg << 8;
+		}
+	      else
+		{
+		  inst.instruction = inst.operands[0].reg;
+		  inst.instruction |= inst.operands[1].reg << 3;
+		}
+	      inst.instruction |= THUMB_OP16 (opcode);
+	      if (inst.size_req == 2)
+		inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+	      else
+		inst.relax = opcode;
+	      return;
+	    }
+	}
+      /* Definitely a 32-bit variant.  */
+      inst.instruction = THUMB_OP32 (opcode);
+      inst.instruction |= inst.operands[0].reg << 12;
+      encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
       return;
     }
 
-  if (skip_past_comma (&str) == FAIL
-      || fp_op2 (&str) == FAIL)
+  constraint (inst.operands[0].reg > 7, BAD_HIREG);
+
+  if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      /* Only [Rn,Rm] is acceptable.  */
+      constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
+      constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
+		  || inst.operands[1].postind || inst.operands[1].shifted
+		  || inst.operands[1].negative,
+		  _("Thumb does not support this addressing mode"));
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      goto op16;
     }
+     
+  inst.instruction = THUMB_OP16 (inst.instruction);
+  if (!inst.operands[1].isreg)
+    if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
+      return;
 
-  end_of_line (str);
-}
+  constraint (!inst.operands[1].preind
+	      || inst.operands[1].shifted
+	      || inst.operands[1].writeback,
+	      _("Thumb does not support this addressing mode"));
+  if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
+    {
+      constraint (inst.instruction & 0x0600,
+		  _("byte or halfword not valid for base register"));
+      constraint (inst.operands[1].reg == REG_PC
+		  && !(inst.instruction & THUMB_LOAD_BIT),
+		  _("r15 based store not allowed"));
+      constraint (inst.operands[1].immisreg,
+		  _("invalid base register for register offset"));
 
-static void
-do_fpa_cmp (str)
-     char * str;
-{
-  skip_whitespace (str);
+      if (inst.operands[1].reg == REG_PC)
+	inst.instruction = T_OPCODE_LDR_PC;
+      else if (inst.instruction & THUMB_LOAD_BIT)
+	inst.instruction = T_OPCODE_LDR_SP;
+      else
+	inst.instruction = T_OPCODE_STR_SP;
 
-  if (fp_reg_required_here (&str, 16) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
       return;
     }
 
-  if (skip_past_comma (&str) == FAIL
-      || fp_op2 (&str) == FAIL)
+  constraint (inst.operands[1].reg > 7, BAD_HIREG);
+  if (!inst.operands[1].immisreg)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      /* Immediate offset.  */
+      inst.instruction |= inst.operands[0].reg;
+      inst.instruction |= inst.operands[1].reg << 3;
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
       return;
     }
 
-  end_of_line (str);
-}
-
-static void
-do_fpa_from_reg (str)
-     char * str;
-{
-  skip_whitespace (str);
-
-  if (fp_reg_required_here (&str, 16) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  /* Register offset.  */
+  constraint (inst.operands[1].imm > 7, BAD_HIREG);
+  constraint (inst.operands[1].negative,
+	      _("Thumb does not support this addressing mode"));
 
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL)
+ op16:
+  switch (inst.instruction)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+    case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
+    case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
+    case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
+    case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
+    case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
+    case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
+    case 0x5600 /* ldrsb */:
+    case 0x5e00 /* ldrsh */: break;
+    default: abort ();
     }
 
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg;
+  inst.instruction |= inst.operands[1].reg << 3;
+  inst.instruction |= inst.operands[1].imm << 6;
 }
 
 static void
-do_fpa_to_reg (str)
-     char * str;
+do_t_ldstd (void)
 {
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 12) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || fp_reg_required_here (&str, 0) == FAIL)
+  if (!inst.operands[1].present)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.operands[1].reg = inst.operands[0].reg + 1;
+      constraint (inst.operands[0].reg == REG_LR,
+		  _("r14 not allowed here"));
     }
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 8;
+  encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
+			    
+}
 
-  end_of_line (str);
+static void
+do_t_ldstt (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
 }
 
-static int
-vfp_sp_reg_required_here (str, pos)
-     char **str;
-     enum vfp_sp_reg_pos pos;
+static void
+do_t_mla (void)
 {
-  int    reg;
-  char *start = *str;
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].reg << 12;
+}
 
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_SN].htab)) != FAIL)
-    {
-      switch (pos)
-	{
-	case VFP_REG_Sd:
-	  inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
-	  break;
+static void
+do_t_mlal (void)
+{
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 8;
+  inst.instruction |= inst.operands[2].reg << 16;
+  inst.instruction |= inst.operands[3].reg;
+}
 
-	case VFP_REG_Sn:
-	  inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
-	  break;
+static void
+do_t_mov_cmp (void)
+{
+  if (unified_syntax)
+    {
+      int r0off = (inst.instruction == T_MNEM_mov
+		   || inst.instruction == T_MNEM_movs) ? 8 : 16;
+      unsigned long opcode;
+      bfd_boolean narrow;
+      bfd_boolean low_regs;
 
-	case VFP_REG_Sm:
-	  inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
-	  break;
+      low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
+      opcode = inst.instruction;
+      if (current_it_mask)
+	narrow = opcode != T_MNEM_movs;
+      else
+	narrow = opcode != T_MNEM_movs || low_regs;
+      if (inst.size_req == 4
+	  || inst.operands[1].shifted)
+	narrow = FALSE;
 
-	default:
-	  abort ();
+      if (!inst.operands[1].isreg)
+	{
+	  /* Immediate operand.  */
+	  if (current_it_mask == 0 && opcode == T_MNEM_mov)
+	    narrow = 0;
+	  if (low_regs && narrow)
+	    {
+	      inst.instruction = THUMB_OP16 (opcode);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      if (inst.size_req == 2)
+		inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+	      else
+		inst.relax = opcode;
+	    }
+	  else
+	    {
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	      inst.instruction |= inst.operands[0].reg << r0off;
+	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	    }
 	}
-      return reg;
-    }
-
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  inst.error = _(all_reg_maps[REG_TYPE_SN].expected);
+      else if (!narrow)
+	{
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= inst.operands[0].reg << r0off;
+	  encode_thumb32_shifted_operand (1);
+	}
+      else
+	switch (inst.instruction)
+	  {
+	  case T_MNEM_mov:
+	    inst.instruction = T_OPCODE_MOV_HR;
+	    inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
+	    inst.instruction |= (inst.operands[0].reg & 0x7);
+	    inst.instruction |= inst.operands[1].reg << 3;
+	    break;
 
-  /* Restore the start point.  */
-  *str = start;
-  return FAIL;
-}
+	  case T_MNEM_movs:
+	    /* We know we have low registers at this point.
+	       Generate ADD Rd, Rs, #0.  */
+	    inst.instruction = T_OPCODE_ADD_I3;
+	    inst.instruction |= inst.operands[0].reg;
+	    inst.instruction |= inst.operands[1].reg << 3;
+	    break;
 
-static int
-vfp_dp_reg_required_here (str, pos)
-     char **str;
-     enum vfp_dp_reg_pos pos;
-{
-  int   reg;
-  char *start = *str;
+	  case T_MNEM_cmp:
+	    if (low_regs)
+	      {
+		inst.instruction = T_OPCODE_CMP_LR;
+		inst.instruction |= inst.operands[0].reg;
+		inst.instruction |= inst.operands[1].reg << 3;
+	      }
+	    else
+	      {
+		inst.instruction = T_OPCODE_CMP_HR;
+		inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
+		inst.instruction |= (inst.operands[0].reg & 0x7);
+		inst.instruction |= inst.operands[1].reg << 3;
+	      }
+	    break;
+	  }
+      return;
+    }
 
-  if ((reg = arm_reg_parse (str, all_reg_maps[REG_TYPE_DN].htab)) != FAIL)
+  inst.instruction = THUMB_OP16 (inst.instruction);
+  if (inst.operands[1].isreg)
     {
-      switch (pos)
+      if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
 	{
-	case VFP_REG_Dd:
-	  inst.instruction |= reg << 12;
-	  break;
-
-	case VFP_REG_Dn:
-	  inst.instruction |= reg << 16;
-	  break;
-
-	case VFP_REG_Dm:
-	  inst.instruction |= reg << 0;
-	  break;
+	  /* A move of two lowregs is encoded as ADD Rd, Rs, #0
+	     since a MOV instruction produces unpredictable results.  */
+	  if (inst.instruction == T_OPCODE_MOV_I8)
+	    inst.instruction = T_OPCODE_ADD_I3;
+	  else
+	    inst.instruction = T_OPCODE_CMP_LR;
 
-	default:
-	  abort ();
+	  inst.instruction |= inst.operands[0].reg;
+	  inst.instruction |= inst.operands[1].reg << 3;
+	}
+      else
+	{
+	  if (inst.instruction == T_OPCODE_MOV_I8)
+	    inst.instruction = T_OPCODE_MOV_HR;
+	  else
+	    inst.instruction = T_OPCODE_CMP_HR;
+	  do_t_cpy ();
 	}
-      return reg;
     }
-
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  inst.error = _(all_reg_maps[REG_TYPE_DN].expected);
-
-  /* Restore the start point.  */
-  *str = start;
-  return FAIL;
-}
-
-static void
-do_vfp_sp_monadic (str)
-     char *str;
-{
-  skip_whitespace (str);
-
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
+  else
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (inst.operands[0].reg > 7,
+		  _("only lo regs allowed with immediate"));
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
     }
-
-  end_of_line (str);
 }
 
 static void
-do_vfp_dp_monadic (str)
-     char *str;
+do_t_mov16 (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
+  inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
+  inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
+  inst.instruction |= (inst.operands[1].imm & 0x00ff);
 }
 
 static void
-do_vfp_sp_dyadic (str)
-     char *str;
+do_t_mvn_tst (void)
 {
-  skip_whitespace (str);
+  if (unified_syntax)
+    {
+      int r0off = (inst.instruction == T_MNEM_mvn
+		   || inst.instruction == T_MNEM_mvns) ? 8 : 16;
+      bfd_boolean narrow;
 
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
-    return;
+      if (inst.size_req == 4
+	  || inst.instruction > 0xffff
+	  || inst.operands[1].shifted
+	  || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
+	narrow = FALSE;
+      else if (inst.instruction == T_MNEM_cmn)
+	narrow = TRUE;
+      else if (THUMB_SETS_FLAGS (inst.instruction))
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
 
-  if (skip_past_comma (&str) == FAIL
-      || vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      if (!inst.operands[1].isreg)
+	{
+	  /* For an immediate, we always generate a 32-bit opcode;
+	     section relaxation will shrink it later if possible.  */
+	  if (inst.instruction < 0xffff)
+	    inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	  inst.instruction |= inst.operands[0].reg << r0off;
+	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	{
+	  /* See if we can do this with a 16-bit instruction.  */
+	  if (narrow)
+	    {
+	      inst.instruction = THUMB_OP16 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].reg << 3;
+	    }
+	  else
+	    {
+	      constraint (inst.operands[1].shifted
+			  && inst.operands[1].immisreg,
+			  _("shift must be constant"));
+	      if (inst.instruction < 0xffff)
+		inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << r0off;
+	      encode_thumb32_shifted_operand (1);
+	    }
+	}
     }
+  else
+    {
+      constraint (inst.instruction > 0xffff
+		  || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
+      constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
+		  _("unshifted register required"));
+      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
+		  BAD_HIREG);
 
-  end_of_line (str);
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg;
+      inst.instruction |= inst.operands[1].reg << 3;
+    }
 }
 
 static void
-do_vfp_dp_dyadic (str)
-     char *str;
+do_t_mrs (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
+  int flags;
+  flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
+  if (flags == 0)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
+		  _("selected processor does not support "
+		    "requested special purpose register"));
     }
-
-  end_of_line (str);
+  else
+    {
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
+		  _("selected processor does not support "
+		    "requested special purpose register %x"));
+      /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
+      constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
+		  _("'CPSR' or 'SPSR' expected"));
+    }
+    
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= (flags & SPSR_BIT) >> 2;
+  inst.instruction |= inst.operands[1].imm & 0xff;
 }
 
 static void
-do_vfp_reg_from_sp (str)
-     char *str;
+do_t_msr (void)
 {
-  skip_whitespace (str);
+  int flags;
 
-  if (reg_required_here (&str, 12) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL)
+  constraint (!inst.operands[1].isreg,
+	      _("Thumb encoding does not support an immediate here"));
+  flags = inst.operands[0].imm;
+  if (flags & ~0xff)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
+		  _("selected processor does not support "
+		    "requested special purpose register"));
     }
-
-  end_of_line (str);
+  else
+    {
+      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
+		  _("selected processor does not support "
+		    "requested special purpose register"));
+      flags |= PSR_f;
+    }
+  inst.instruction |= (flags & SPSR_BIT) >> 2;
+  inst.instruction |= (flags & ~SPSR_BIT) >> 8;
+  inst.instruction |= (flags & 0xff);
+  inst.instruction |= inst.operands[1].reg << 16;
 }
 
 static void
-do_vfp_reg2_from_sp2 (str)
-     char *str;
+do_t_mul (void)
 {
-  skip_whitespace (str);
+  if (!inst.operands[2].present)
+    inst.operands[2].reg = inst.operands[0].reg;
 
-  if (reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 16) == FAIL
-      || skip_past_comma (&str) == FAIL)
+  /* There is no 32-bit MULS and no 16-bit MUL. */
+  if (unified_syntax && inst.instruction == T_MNEM_mul)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.operands[2].reg << 0;
     }
-
-  /* We require exactly two consecutive SP registers.  */
-  if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
+  else
     {
-      if (! inst.error)
-	inst.error = _("only two consecutive VFP SP registers allowed here");
-    }
+      constraint (!unified_syntax
+		  && inst.instruction == T_MNEM_muls, BAD_THUMB32);
+      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
+		  BAD_HIREG);
+
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg;
 
-  end_of_line (str);
+      if (inst.operands[0].reg == inst.operands[1].reg)
+	inst.instruction |= inst.operands[2].reg << 3;
+      else if (inst.operands[0].reg == inst.operands[2].reg)
+	inst.instruction |= inst.operands[1].reg << 3;
+      else
+	constraint (1, _("dest must overlap one source register"));
+    }
 }
 
 static void
-do_vfp_sp_from_reg (str)
-     char *str;
+do_t_mull (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sn) == FAIL)
-    return;
+  inst.instruction |= inst.operands[0].reg << 12;
+  inst.instruction |= inst.operands[1].reg << 8;
+  inst.instruction |= inst.operands[2].reg << 16;
+  inst.instruction |= inst.operands[3].reg;
 
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  if (inst.operands[0].reg == inst.operands[1].reg)
+    as_tsktsk (_("rdhi and rdlo must be different"));
 }
 
 static void
-do_vfp_sp2_from_reg2 (str)
-     char *str;
+do_t_nop (void)
 {
-  skip_whitespace (str);
-
-  /* We require exactly two consecutive SP registers.  */
-  if (vfp_sp_reg_list (&str, VFP_REG_Sm) != 2)
+  if (unified_syntax)
     {
-      if (! inst.error)
-	inst.error = _("only two consecutive VFP SP registers allowed here");
+      if (inst.size_req == 4 || inst.operands[0].imm > 15)
+	{
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= inst.operands[0].imm;
+	}
+      else
+	{
+	  inst.instruction = THUMB_OP16 (inst.instruction);
+	  inst.instruction |= inst.operands[0].imm << 4;
+	}
     }
-
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 16) == FAIL)
+  else
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      constraint (inst.operands[0].present,
+		  _("Thumb does not support NOP with hints"));
+      inst.instruction = 0x46c0;
     }
-
-  end_of_line (str);
 }
 
 static void
-do_vfp_reg_from_dp (str)
-     char *str;
+do_t_neg (void)
 {
-  skip_whitespace (str);
+  if (unified_syntax)
+    {
+      bfd_boolean narrow;
 
-  if (reg_required_here (&str, 12) == FAIL)
-    return;
+      if (THUMB_SETS_FLAGS (inst.instruction))
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
+      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
+	narrow = FALSE;
+      if (inst.size_req == 4)
+	narrow = FALSE;
 
-  if (skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      if (!narrow)
+	{
+	  inst.instruction = THUMB_OP32 (inst.instruction);
+	  inst.instruction |= inst.operands[0].reg << 8;
+	  inst.instruction |= inst.operands[1].reg << 16;
+	}
+      else
+	{
+	  inst.instruction = THUMB_OP16 (inst.instruction);
+	  inst.instruction |= inst.operands[0].reg;
+	  inst.instruction |= inst.operands[1].reg << 3;
+	}
     }
+  else
+    {
+      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
+		  BAD_HIREG);
+      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
 
-  end_of_line (str);
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg;
+      inst.instruction |= inst.operands[1].reg << 3;
+    }
 }
 
 static void
-do_vfp_reg2_from_dp (str)
-     char *str;
+do_t_pkhbt (void)
 {
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 12) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 16) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  if (inst.operands[3].present)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      unsigned int val = inst.reloc.exp.X_add_number;
+      constraint (inst.reloc.exp.X_op != O_constant,
+		  _("expression too complex"));
+      inst.instruction |= (val & 0x1c) << 10;
+      inst.instruction |= (val & 0x03) << 6;
     }
-
-  end_of_line (str);
 }
 
 static void
-do_vfp_dp_from_reg (str)
-     char *str;
+do_t_pkhtb (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dn) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  if (!inst.operands[3].present)
+    inst.instruction &= ~0x00000020;
+  do_t_pkhbt ();
 }
 
 static void
-do_vfp_dp_from_reg2 (str)
-     char *str;
+do_t_pld (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 16) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
 }
 
-static const struct vfp_reg *
-vfp_psr_parse (str)
-     char **str;
+static void
+do_t_push_pop (void)
 {
-  char *start = *str;
-  char  c;
-  char *p;
-  const struct vfp_reg *vreg;
-
-  p = start;
+  unsigned mask;
+  
+  constraint (inst.operands[0].writeback,
+	      _("push/pop do not support {reglist}^"));
+  constraint (inst.reloc.type != BFD_RELOC_UNUSED,
+	      _("expression too complex"));
 
-  /* Find the end of the current token.  */
-  do
+  mask = inst.operands[0].imm;
+  if ((mask & ~0xff) == 0)
+    inst.instruction = THUMB_OP16 (inst.instruction);
+  else if ((inst.instruction == T_MNEM_push
+	    && (mask & ~0xff) == 1 << REG_LR)
+	   || (inst.instruction == T_MNEM_pop
+	       && (mask & ~0xff) == 1 << REG_PC))
     {
-      c = *p++;
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= THUMB_PP_PC_LR;
+      mask &= 0xff;
     }
-  while (ISALPHA (c));
-
-  /* Mark it.  */
-  *--p = 0;
-
-  for (vreg = vfp_regs + 0;
-       vreg < vfp_regs + sizeof (vfp_regs) / sizeof (struct vfp_reg);
-       vreg++)
+  else if (unified_syntax)
     {
-      if (strcmp (start, vreg->name) == 0)
+      if (mask & (1 << 13))
+	inst.error =  _("SP not allowed in register list");
+      if (inst.instruction == T_MNEM_push)
 	{
-	  *p = c;
-	  *str = p;
-	  return vreg;
+	  if (mask & (1 << 15))
+	    inst.error = _("PC not allowed in register list");
 	}
+      else
+	{
+	  if (mask & (1 << 14)
+	      && mask & (1 << 15))
+	    inst.error = _("LR and PC should not both be in register list");
+	}
+      if ((mask & (mask - 1)) == 0)
+	{
+	  /* Single register push/pop implemented as str/ldr.  */
+	  if (inst.instruction == T_MNEM_push)
+	    inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
+	  else
+	    inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
+	  mask = ffs(mask) - 1;
+	  mask <<= 12;
+	}
+      else
+	inst.instruction = THUMB_OP32 (inst.instruction);
     }
-
-  *p = c;
-  return NULL;
-}
-
-static int
-vfp_psr_required_here (str)
-     char **str;
-{
-  char *start = *str;
-  const struct vfp_reg *vreg;
-
-  vreg = vfp_psr_parse (str);
-
-  if (vreg)
-    {
-      inst.instruction |= vreg->regno;
-      return SUCCESS;
-    }
-
-  inst.error = _("VFP system register expected");
-
-  *str = start;
-  return FAIL;
-}
-
-static void
-do_vfp_reg_from_ctrl (str)
-     char *str;
-{
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 12) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_psr_required_here (&str) == FAIL)
+  else
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      inst.error = _("invalid register list to push/pop instruction");
       return;
     }
 
-  end_of_line (str);
+  inst.instruction |= mask;
 }
 
 static void
-do_vfp_ctrl_from_reg (str)
-     char *str;
+do_t_rbit (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_psr_required_here (&str) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || reg_required_here (&str, 12) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
 }
 
 static void
-do_vfp_sp_ldst (str)
-     char *str;
+do_t_rev (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
+  if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
+      && inst.size_req != 4)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg;
+      inst.instruction |= inst.operands[1].reg << 3;
     }
-
-  if (skip_past_comma (&str) == FAIL
-      || cp_address_required_here (&str, CP_NO_WB) == FAIL)
+  else if (unified_syntax)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.instruction |= inst.operands[1].reg << 16;
+      inst.instruction |= inst.operands[1].reg;
     }
-
-  end_of_line (str);
+  else
+    inst.error = BAD_HIREG;
 }
 
 static void
-do_vfp_dp_ldst (str)
-     char *str;
+do_t_rsb (void)
 {
-  skip_whitespace (str);
+  int Rd, Rs;
 
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  Rd = inst.operands[0].reg;
+  Rs = (inst.operands[1].present
+	? inst.operands[1].reg    /* Rd, Rs, foo */
+	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
 
-  if (skip_past_comma (&str) == FAIL
-      || cp_address_required_here (&str, CP_NO_WB) == FAIL)
+  inst.instruction |= Rd << 8;
+  inst.instruction |= Rs << 16;
+  if (!inst.operands[2].isreg)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
     }
-
-  end_of_line (str);
+  else
+    encode_thumb32_shifted_operand (2);
 }
 
-/* Parse and encode a VFP SP register list, storing the initial
-   register in position POS and returning the range as the result.  If
-   the string is invalid return FAIL (an invalid range).  */
-static long
-vfp_sp_reg_list (str, pos)
-     char **str;
-     enum vfp_sp_reg_pos pos;
+static void
+do_t_setend (void)
 {
-  long range = 0;
-  int base_reg = 0;
-  int new_base;
-  long base_bits = 0;
-  int count = 0;
-  long tempinst;
-  unsigned long mask = 0;
-  int warned = 0;
-
-  if (**str != '{')
-    return FAIL;
-
-  (*str)++;
-  skip_whitespace (*str);
+  constraint (current_it_mask, BAD_NOT_IT);
+  if (inst.operands[0].imm)
+    inst.instruction |= 0x8;
+}
 
-  tempinst = inst.instruction;
+static void
+do_t_shift (void)
+{
+  if (!inst.operands[1].present)
+    inst.operands[1].reg = inst.operands[0].reg;
 
-  do
+  if (unified_syntax)
     {
-      inst.instruction = 0;
-
-      if ((new_base = vfp_sp_reg_required_here (str, pos)) == FAIL)
-	return FAIL;
+      bfd_boolean narrow;
+      int shift_kind;
 
-      if (count == 0 || base_reg > new_base)
+      switch (inst.instruction)
 	{
-	  base_reg = new_base;
-	  base_bits = inst.instruction;
+	case T_MNEM_asr:
+	case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
+	case T_MNEM_lsl:
+	case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
+	case T_MNEM_lsr:
+	case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
+	case T_MNEM_ror:
+	case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
+	default: abort ();
 	}
 
-      if (mask & (1 << new_base))
-	{
-	  inst.error = _("invalid register list");
-	  return FAIL;
-	}
-
-      if ((mask >> new_base) != 0 && ! warned)
-	{
-	  as_tsktsk (_("register list not in ascending order"));
-	  warned = 1;
-	}
-
-      mask |= 1 << new_base;
-      count++;
-
-      skip_whitespace (*str);
-
-      if (**str == '-') /* We have the start of a range expression */
-	{
-	  int high_range;
-
-	  (*str)++;
-
-	  if ((high_range
-	       = arm_reg_parse (str, all_reg_maps[REG_TYPE_SN].htab))
-	      == FAIL)
+      if (THUMB_SETS_FLAGS (inst.instruction))
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
+      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
+	narrow = FALSE;
+      if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
+	narrow = FALSE;
+      if (inst.operands[2].isreg
+	  && (inst.operands[1].reg != inst.operands[0].reg
+	      || inst.operands[2].reg > 7))
+	narrow = FALSE;
+      if (inst.size_req == 4)
+	narrow = FALSE;
+
+      if (!narrow)
+	{
+	  if (inst.operands[2].isreg)
 	    {
-	      inst.error = _(all_reg_maps[REG_TYPE_SN].expected);
-	      return FAIL;
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.instruction |= inst.operands[2].reg;
 	    }
-
-	  if (high_range <= new_base)
+	  else
 	    {
-	      inst.error = _("register range not in ascending order");
-	      return FAIL;
+	      inst.operands[1].shifted = 1;
+	      inst.operands[1].shift_kind = shift_kind;
+	      inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
+					     ? T_MNEM_movs : T_MNEM_mov);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      encode_thumb32_shifted_operand (1);
+	      /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup.  */
+	      inst.reloc.type = BFD_RELOC_UNUSED;
 	    }
-
-	  for (new_base++; new_base <= high_range; new_base++)
-	    {
-	      if (mask & (1 << new_base))
-		{
-		  inst.error = _("invalid register list");
-		  return FAIL;
-		}
-
-	      mask |= 1 << new_base;
-	      count++;
-	    }
-	}
-    }
-  while (skip_past_comma (str) != FAIL);
-
-  if (**str != '}')
-    {
-      inst.error = _("invalid register list");
-      return FAIL;
-    }
-
-  (*str)++;
-
-  range = count;
-
-  /* Sanity check -- should have raised a parse error above.  */
-  if (count == 0 || count > 32)
-    abort ();
-
-  /* Final test -- the registers must be consecutive.  */
-  while (count--)
-    {
-      if ((mask & (1 << base_reg++)) == 0)
-	{
-	  inst.error = _("non-contiguous register range");
-	  return FAIL;
-	}
-    }
-
-  inst.instruction = tempinst | base_bits;
-  return range;
-}
-
-static long
-vfp_dp_reg_list (str)
-     char **str;
-{
-  long range = 0;
-  int base_reg = 0;
-  int new_base;
-  int count = 0;
-  long tempinst;
-  unsigned long mask = 0;
-  int warned = 0;
-
-  if (**str != '{')
-    return FAIL;
-
-  (*str)++;
-  skip_whitespace (*str);
-
-  tempinst = inst.instruction;
-
-  do
-    {
-      inst.instruction = 0;
-
-      if ((new_base = vfp_dp_reg_required_here (str, VFP_REG_Dd)) == FAIL)
-	return FAIL;
-
-      if (count == 0 || base_reg > new_base)
-	{
-	  base_reg = new_base;
-	  range = inst.instruction;
-	}
-
-      if (mask & (1 << new_base))
-	{
-	  inst.error = _("invalid register list");
-	  return FAIL;
-	}
-
-      if ((mask >> new_base) != 0 && ! warned)
-	{
-	  as_tsktsk (_("register list not in ascending order"));
-	  warned = 1;
 	}
-
-      mask |= 1 << new_base;
-      count++;
-
-      skip_whitespace (*str);
-
-      if (**str == '-') /* We have the start of a range expression */
+      else
 	{
-	  int high_range;
-
-	  (*str)++;
-
-	  if ((high_range
-	       = arm_reg_parse (str, all_reg_maps[REG_TYPE_DN].htab))
-	      == FAIL)
+	  if (inst.operands[2].isreg)
 	    {
-	      inst.error = _(all_reg_maps[REG_TYPE_DN].expected);
-	      return FAIL;
-	    }
-
-	  if (high_range <= new_base)
-	    {
-	      inst.error = _("register range not in ascending order");
-	      return FAIL;
+	      switch (shift_kind)
+		{
+		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
+		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
+		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
+		case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
+		default: abort ();
+		}
+	  
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[2].reg << 3;
 	    }
-
-	  for (new_base++; new_base <= high_range; new_base++)
+	  else
 	    {
-	      if (mask & (1 << new_base))
+	      switch (shift_kind)
 		{
-		  inst.error = _("invalid register list");
-		  return FAIL;
+		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
+		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
+		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
+		default: abort ();
 		}
-
-	      mask |= 1 << new_base;
-	      count++;
+	      inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+	      inst.instruction |= inst.operands[0].reg;
+	      inst.instruction |= inst.operands[1].reg << 3;
 	    }
 	}
     }
-  while (skip_past_comma (str) != FAIL);
-
-  if (**str != '}')
+  else
     {
-      inst.error = _("invalid register list");
-      return FAIL;
-    }
-
-  (*str)++;
+      constraint (inst.operands[0].reg > 7
+		  || inst.operands[1].reg > 7, BAD_HIREG);
+      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
 
-  range |= 2 * count;
-
-  /* Sanity check -- should have raised a parse error above.  */
-  if (count == 0 || count > 16)
-    abort ();
+      if (inst.operands[2].isreg)  /* Rd, {Rs,} Rn */
+	{
+	  constraint (inst.operands[2].reg > 7, BAD_HIREG);
+	  constraint (inst.operands[0].reg != inst.operands[1].reg,
+		      _("source1 and dest must be same register"));
 
-  /* Final test -- the registers must be consecutive.  */
-  while (count--)
-    {
-      if ((mask & (1 << base_reg++)) == 0)
+	  switch (inst.instruction)
+	    {
+	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
+	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
+	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
+	    case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
+	    default: abort ();
+	    }
+	  
+	  inst.instruction |= inst.operands[0].reg;
+	  inst.instruction |= inst.operands[2].reg << 3;
+	}
+      else
 	{
-	  inst.error = _("non-contiguous register range");
-	  return FAIL;
+	  switch (inst.instruction)
+	    {
+	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
+	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
+	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
+	    case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
+	    default: abort ();
+	    }
+	  inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
+	  inst.instruction |= inst.operands[0].reg;
+	  inst.instruction |= inst.operands[1].reg << 3;
 	}
     }
-
-  inst.instruction = tempinst;
-  return range;
 }
 
 static void
-vfp_sp_ldstm (str, ldstm_type)
-     char *str;
-     enum vfp_ldstm_type ldstm_type;
+do_t_simd (void)
 {
-  long range;
-
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 16) == FAIL)
-    return;
-
-  skip_whitespace (str);
-
-  if (*str == '!')
-    {
-      inst.instruction |= WRITE_BACK;
-      str++;
-    }
-  else if (ldstm_type != VFP_LDSTMIA)
-    {
-      inst.error = _("this addressing mode requires base-register writeback");
-      return;
-    }
-
-  if (skip_past_comma (&str) == FAIL
-      || (range = vfp_sp_reg_list (&str, VFP_REG_Sd)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  inst.instruction |= range;
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
 }
 
 static void
-vfp_dp_ldstm (str, ldstm_type)
-     char *str;
-     enum vfp_ldstm_type ldstm_type;
+do_t_smc (void)
 {
-  long range;
-
-  skip_whitespace (str);
-
-  if (reg_required_here (&str, 16) == FAIL)
-    return;
+  unsigned int value = inst.reloc.exp.X_add_number;
+  constraint (inst.reloc.exp.X_op != O_constant,
+	      _("expression too complex"));
+  inst.reloc.type = BFD_RELOC_UNUSED;
+  inst.instruction |= (value & 0xf000) >> 12;
+  inst.instruction |= (value & 0x0ff0);
+  inst.instruction |= (value & 0x000f) << 16;
+}
 
-  skip_whitespace (str);
+static void
+do_t_ssat (void)
+{
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm - 1;
+  inst.instruction |= inst.operands[2].reg << 16;
 
-  if (*str == '!')
+  if (inst.operands[3].present)
     {
-      inst.instruction |= WRITE_BACK;
-      str++;
-    }
-  else if (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX)
-    {
-      inst.error = _("this addressing mode requires base-register writeback");
-      return;
-    }
+      constraint (inst.reloc.exp.X_op != O_constant,
+		  _("expression too complex"));
 
-  if (skip_past_comma (&str) == FAIL
-      || (range = vfp_dp_reg_list (&str)) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      if (inst.reloc.exp.X_add_number != 0)
+	{
+	  if (inst.operands[3].shift_kind == SHIFT_ASR)
+	    inst.instruction |= 0x00200000;  /* sh bit */
+	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
+	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
+	}
+      inst.reloc.type = BFD_RELOC_UNUSED;
     }
-
-  if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
-    range += 1;
-
-  inst.instruction |= range;
-  end_of_line (str);
 }
 
 static void
-do_vfp_sp_ldstmia (str)
-     char *str;
+do_t_ssat16 (void)
 {
-  vfp_sp_ldstm (str, VFP_LDSTMIA);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm - 1;
+  inst.instruction |= inst.operands[2].reg << 16;
 }
 
 static void
-do_vfp_sp_ldstmdb (str)
-     char *str;
+do_t_strex (void)
 {
-  vfp_sp_ldstm (str, VFP_LDSTMDB);
+  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
+	      || inst.operands[2].postind || inst.operands[2].writeback
+	      || inst.operands[2].immisreg || inst.operands[2].shifted
+	      || inst.operands[2].negative,
+	      BAD_ADDR_MODE);
+
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 16;
+  inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
 }
 
 static void
-do_vfp_dp_ldstmia (str)
-     char *str;
+do_t_strexd (void)
 {
-  vfp_dp_ldstm (str, VFP_LDSTMIA);
+  if (!inst.operands[2].present)
+    inst.operands[2].reg = inst.operands[1].reg + 1;
+
+  constraint (inst.operands[0].reg == inst.operands[1].reg
+	      || inst.operands[0].reg == inst.operands[2].reg
+	      || inst.operands[0].reg == inst.operands[3].reg
+	      || inst.operands[1].reg == inst.operands[2].reg,
+	      BAD_OVERLAP);
+
+  inst.instruction |= inst.operands[0].reg;
+  inst.instruction |= inst.operands[1].reg << 12;
+  inst.instruction |= inst.operands[2].reg << 8;
+  inst.instruction |= inst.operands[3].reg << 16;
 }
 
 static void
-do_vfp_dp_ldstmdb (str)
-     char *str;
+do_t_sxtah (void)
 {
-  vfp_dp_ldstm (str, VFP_LDSTMDB);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+  inst.instruction |= inst.operands[3].imm << 4;
 }
 
 static void
-do_vfp_xp_ldstmia (str)
-     char *str;
+do_t_sxth (void)
 {
-  vfp_dp_ldstm (str, VFP_LDSTMIAX);
+  if (inst.instruction <= 0xffff && inst.size_req != 4
+      && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
+      && (!inst.operands[2].present || inst.operands[2].imm == 0))
+    {
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg;
+      inst.instruction |= inst.operands[1].reg << 3;
+    }
+  else if (unified_syntax)
+    {
+      if (inst.instruction <= 0xffff)
+	inst.instruction = THUMB_OP32 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 8;
+      inst.instruction |= inst.operands[1].reg;
+      inst.instruction |= inst.operands[2].imm << 4;
+    }
+  else
+    {
+      constraint (inst.operands[2].present && inst.operands[2].imm != 0,
+		  _("Thumb encoding does not support rotation"));
+      constraint (1, BAD_HIREG);
+    }
 }
 
 static void
-do_vfp_xp_ldstmdb (str)
-     char *str;
+do_t_swi (void)
 {
-  vfp_dp_ldstm (str, VFP_LDSTMDBX);
+  inst.reloc.type = BFD_RELOC_ARM_SWI;
 }
 
 static void
-do_vfp_sp_compare_z (str)
-     char *str;
+do_t_tb (void)
 {
-  skip_whitespace (str);
+  int half;
 
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  half = (inst.instruction & 0x10) != 0;
+  constraint (current_it_mask && current_it_mask != 0x10, BAD_BRANCH);
+  constraint (inst.operands[0].immisreg,
+	      _("instruction requires register index"));
+  constraint (inst.operands[0].imm == 15,
+	      _("PC is not a valid index register"));
+  constraint (!half && inst.operands[0].shifted,
+	      _("instruction does not allow shifted index"));
+  inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
 }
 
 static void
-do_vfp_dp_compare_z (str)
-     char *str;
+do_t_usat (void)
 {
-  skip_whitespace (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm;
+  inst.instruction |= inst.operands[2].reg << 16;
 
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
+  if (inst.operands[3].present)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      constraint (inst.reloc.exp.X_op != O_constant,
+		  _("expression too complex"));
+      if (inst.reloc.exp.X_add_number != 0)
+	{
+	  if (inst.operands[3].shift_kind == SHIFT_ASR)
+	    inst.instruction |= 0x00200000;  /* sh bit */
 
-  end_of_line (str);
+	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
+	  inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
+	}
+      inst.reloc.type = BFD_RELOC_UNUSED;
+    }
 }
 
 static void
-do_vfp_dp_sp_cvt (str)
-     char *str;
+do_t_usat16 (void)
 {
-  skip_whitespace (str);
-
-  if (vfp_dp_reg_required_here (&str, VFP_REG_Dd) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_sp_reg_required_here (&str, VFP_REG_Sm) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  end_of_line (str);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].imm;
+  inst.instruction |= inst.operands[2].reg << 16;
 }
+
+/* Overall per-instruction processing.	*/
+
+/* We need to be able to fix up arbitrary expressions in some statements.
+   This is so that we can handle symbols that are an arbitrary distance from
+   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
+   which returns part of an address in a form which will be valid for
+   a data instruction.	We do this by pushing the expression into a symbol
+   in the expr_section, and creating a fix for that.  */
 
 static void
-do_vfp_sp_dp_cvt (str)
-     char *str;
+fix_new_arm (fragS *	   frag,
+	     int	   where,
+	     short int	   size,
+	     expressionS * exp,
+	     int	   pc_rel,
+	     int	   reloc)
 {
-  skip_whitespace (str);
+  fixS *	   new_fix;
 
-  if (vfp_sp_reg_required_here (&str, VFP_REG_Sd) == FAIL)
-    return;
-
-  if (skip_past_comma (&str) == FAIL
-      || vfp_dp_reg_required_here (&str, VFP_REG_Dm) == FAIL)
+  switch (exp->X_op)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+    case O_constant:
+    case O_symbol:
+    case O_add:
+    case O_subtract:
+      new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
+      break;
+
+    default:
+      new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
+			 pc_rel, reloc);
+      break;
     }
 
-  end_of_line (str);
+  /* Mark whether the fix is to a THUMB instruction, or an ARM
+     instruction.  */
+  new_fix->tc_fix_data = thumb_mode;
 }
 
-/* Thumb specific routines.  */
-
-/* Parse and validate that a register is of the right form, this saves
-   repeated checking of this information in many similar cases.
-   Unlike the 32-bit case we do not insert the register into the opcode
-   here, since the position is often unknown until the full instruction
-   has been parsed.  */
-
-static int
-thumb_reg (strp, hi_lo)
-     char ** strp;
-     int     hi_lo;
+/* Create a frg for an instruction requiring relaxation.  */
+static void
+output_relax_insn (void)
 {
-  int reg;
+  char * to;
+  symbolS *sym;
+  int offset;
 
-  if ((reg = reg_required_here (strp, -1)) == FAIL)
-    return FAIL;
+#ifdef OBJ_ELF
+  /* The size of the instruction is unknown, so tie the debug info to the
+     start of the instruction.  */
+  dwarf2_emit_insn (0);
+#endif
 
-  switch (hi_lo)
+  switch (inst.reloc.exp.X_op)
     {
-    case THUMB_REG_LO:
-      if (reg > 7)
-	{
-	  inst.error = _("lo register required");
-	  return FAIL;
-	}
+    case O_symbol:
+      sym = inst.reloc.exp.X_add_symbol;
+      offset = inst.reloc.exp.X_add_number;
       break;
-
-    case THUMB_REG_HI:
-      if (reg < 8)
-	{
-	  inst.error = _("hi register required");
-	  return FAIL;
-	}
+    case O_constant:
+      sym = NULL;
+      offset = inst.reloc.exp.X_add_number;
       break;
-
     default:
+      sym = make_expr_symbol (&inst.reloc.exp);
+      offset = 0;
       break;
-    }
-
-  return reg;
+  }
+  to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
+		 inst.relax, sym, offset, NULL/*offset, opcode*/);
+  md_number_to_chars (to, inst.instruction, THUMB_SIZE);
 }
 
-/* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
-   was SUB.  */
-
+/* Write a 32-bit thumb instruction to buf.  */
 static void
-thumb_add_sub (str, subtract)
-     char * str;
-     int    subtract;
+put_thumb32_insn (char * buf, unsigned long insn)
 {
-  int Rd, Rs, Rn = FAIL;
+  md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
+  md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
+}
 
-  skip_whitespace (str);
+static void
+output_inst (const char * str)
+{
+  char * to = NULL;
 
-  if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
-      || skip_past_comma (&str) == FAIL)
+  if (inst.error)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      as_bad ("%s -- `%s'", inst.error, str);
       return;
     }
+  if (inst.relax) {
+      output_relax_insn();
+      return;
+  }
+  if (inst.size == 0)
+    return;
 
-  if (is_immediate_prefix (*str))
-    {
-      Rs = Rd;
-      str++;
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
-    }
-  else
-    {
-      if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
-	return;
+  to = frag_more (inst.size);
 
-      if (skip_past_comma (&str) == FAIL)
-	{
-	  /* Two operand format, shuffle the registers
-	     and pretend there are 3.  */
-	  Rn = Rs;
-	  Rs = Rd;
-	}
-      else if (is_immediate_prefix (*str))
-	{
-	  str++;
-	  if (my_get_expression (&inst.reloc.exp, &str))
-	    return;
-	}
-      else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
-	return;
+  if (thumb_mode && (inst.size > THUMB_SIZE))
+    {
+      assert (inst.size == (2 * THUMB_SIZE));
+      put_thumb32_insn (to, inst.instruction);
     }
-
-  /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
-     for the latter case, EXPR contains the immediate that was found.  */
-  if (Rn != FAIL)
+  else if (inst.size > INSN_SIZE)
     {
-      /* All register format.  */
-      if (Rd > 7 || Rs > 7 || Rn > 7)
-	{
-	  if (Rs != Rd)
-	    {
-	      inst.error = _("dest and source1 must be the same register");
-	      return;
-	    }
-
-	  /* Can't do this for SUB.  */
-	  if (subtract)
-	    {
-	      inst.error = _("subtract valid only on lo regs");
-	      return;
-	    }
-
-	  inst.instruction = (T_OPCODE_ADD_HI
-			      | (Rd > 7 ? THUMB_H1 : 0)
-			      | (Rn > 7 ? THUMB_H2 : 0));
-	  inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
-	}
-      else
-	{
-	  inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
-	  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
-	}
+      assert (inst.size == (2 * INSN_SIZE));
+      md_number_to_chars (to, inst.instruction, INSN_SIZE);
+      md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
     }
   else
-    {
-      /* Immediate expression, now things start to get nasty.  */
-
-      /* First deal with HI regs, only very restricted cases allowed:
-	 Adjusting SP, and using PC or SP to get an address.  */
-      if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
-	  || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
-	{
-	  inst.error = _("invalid Hi register with immediate");
-	  return;
-	}
-
-      if (inst.reloc.exp.X_op != O_constant)
-	{
-	  /* Value isn't known yet, all we can do is store all the fragments
-	     we know about in the instruction and let the reloc hacking
-	     work it all out.  */
-	  inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
-	  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
-	}
-      else
-	{
-	  int offset = inst.reloc.exp.X_add_number;
-
-	  if (subtract)
-	    offset = - offset;
-
-	  if (offset < 0)
-	    {
-	      offset = - offset;
-	      subtract = 1;
-
-	      /* Quick check, in case offset is MIN_INT.  */
-	      if (offset < 0)
-		{
-		  inst.error = _("immediate value out of range");
-		  return;
-		}
-	    }
-	  /* Note - you cannot convert a subtract of 0 into an
-	     add of 0 because the carry flag is set differently.  */
-	  else if (offset > 0)
-	    subtract = 0;
+    md_number_to_chars (to, inst.instruction, inst.size);
 
-	  if (Rd == REG_SP)
-	    {
-	      if (offset & ~0x1fc)
-		{
-		  inst.error = _("invalid immediate value for stack adjust");
-		  return;
-		}
-	      inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
-	      inst.instruction |= offset >> 2;
-	    }
-	  else if (Rs == REG_PC || Rs == REG_SP)
-	    {
-	      if (subtract
-		  || (offset & ~0x3fc))
-		{
-		  inst.error = _("invalid immediate for address calculation");
-		  return;
-		}
-	      inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
-				  : T_OPCODE_ADD_SP);
-	      inst.instruction |= (Rd << 8) | (offset >> 2);
-	    }
-	  else if (Rs == Rd)
-	    {
-	      if (offset & ~0xff)
-		{
-		  inst.error = _("immediate value out of range");
-		  return;
-		}
-	      inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
-	      inst.instruction |= (Rd << 8) | offset;
-	    }
-	  else
-	    {
-	      if (offset & ~0x7)
-		{
-		  inst.error = _("immediate value out of range");
-		  return;
-		}
-	      inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
-	      inst.instruction |= Rd | (Rs << 3) | (offset << 6);
-	    }
-	}
-    }
+  if (inst.reloc.type != BFD_RELOC_UNUSED)
+    fix_new_arm (frag_now, to - frag_now->fr_literal,
+		 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
+		 inst.reloc.type);
 
-  end_of_line (str);
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (inst.size);
+#endif
 }
 
-static void
-thumb_shift (str, shift)
-     char * str;
-     int    shift;
-{
-  int Rd, Rs, Rn = FAIL;
+/* Tag values used in struct asm_opcode's tag field.  */
+enum opcode_tag
+{
+  OT_unconditional,	/* Instruction cannot be conditionalized.
+			   The ARM condition field is still 0xE.  */
+  OT_unconditionalF,	/* Instruction cannot be conditionalized
+			   and carries 0xF in its ARM condition field.  */
+  OT_csuffix,		/* Instruction takes a conditional suffix.  */
+  OT_cinfix3,		/* Instruction takes a conditional infix,
+			   beginning at character index 3.  (In
+			   unified mode, it becomes a suffix.)  */
+  OT_cinfix3_legacy,	/* Legacy instruction takes a conditional infix at
+			   character index 3, even in unified mode.  Used for
+			   legacy instructions where suffix and infix forms
+			   may be ambiguous.  */
+  OT_csuf_or_in3,	/* Instruction takes either a conditional
+			   suffix or an infix at character index 3.  */
+  OT_odd_infix_unc,	/* This is the unconditional variant of an
+			   instruction that takes a conditional infix
+			   at an unusual position.  In unified mode,
+			   this variant will accept a suffix.  */
+  OT_odd_infix_0	/* Values greater than or equal to OT_odd_infix_0
+			   are the conditional variants of instructions that
+			   take conditional infixes in unusual positions.
+			   The infix appears at character index
+			   (tag - OT_odd_infix_0).  These are not accepted
+			   in unified mode.  */
+};
 
-  skip_whitespace (str);
+/* Subroutine of md_assemble, responsible for looking up the primary
+   opcode from the mnemonic the user wrote.  STR points to the
+   beginning of the mnemonic.
+
+   This is not simply a hash table lookup, because of conditional
+   variants.  Most instructions have conditional variants, which are
+   expressed with a _conditional affix_ to the mnemonic.  If we were
+   to encode each conditional variant as a literal string in the opcode
+   table, it would have approximately 20,000 entries.
+
+   Most mnemonics take this affix as a suffix, and in unified syntax,
+   'most' is upgraded to 'all'.  However, in the divided syntax, some
+   instructions take the affix as an infix, notably the s-variants of
+   the arithmetic instructions.  Of those instructions, all but six
+   have the infix appear after the third character of the mnemonic.
+
+   Accordingly, the algorithm for looking up primary opcodes given
+   an identifier is:
+
+   1. Look up the identifier in the opcode table.
+      If we find a match, go to step U.
+
+   2. Look up the last two characters of the identifier in the
+      conditions table.  If we find a match, look up the first N-2
+      characters of the identifier in the opcode table.  If we
+      find a match, go to step CE.
+
+   3. Look up the fourth and fifth characters of the identifier in
+      the conditions table.  If we find a match, extract those
+      characters from the identifier, and look up the remaining
+      characters in the opcode table.  If we find a match, go
+      to step CM.
+
+   4. Fail.
+
+   U. Examine the tag field of the opcode structure, in case this is
+      one of the six instructions with its conditional infix in an
+      unusual place.  If it is, the tag tells us where to find the
+      infix; look it up in the conditions table and set inst.cond
+      accordingly.  Otherwise, this is an unconditional instruction.
+      Again set inst.cond accordingly.  Return the opcode structure.
+
+  CE. Examine the tag field to make sure this is an instruction that
+      should receive a conditional suffix.  If it is not, fail.
+      Otherwise, set inst.cond from the suffix we already looked up,
+      and return the opcode structure.
+
+  CM. Examine the tag field to make sure this is an instruction that
+      should receive a conditional infix after the third character.
+      If it is not, fail.  Otherwise, undo the edits to the current
+      line of input and proceed as for case CE.  */
+
+static const struct asm_opcode *
+opcode_lookup (char **str)
+{
+  char *end, *base;
+  char *affix;
+  const struct asm_opcode *opcode;
+  const struct asm_cond *cond;
+  char save[2];
+
+  /* Scan up to the end of the mnemonic, which must end in white space,
+     '.' (in unified mode only), or end of string.  */
+  for (base = end = *str; *end != '\0'; end++)
+    if (*end == ' ' || (unified_syntax && *end == '.'))
+      break;
 
-  if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || skip_past_comma (&str) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+  if (end == base)
+    return 0;
 
-  if (is_immediate_prefix (*str))
+  /* Handle a possible width suffix.  */
+  if (end[0] == '.')
     {
-      /* Two operand immediate format, set Rs to Rd.  */
-      Rs = Rd;
-      str ++;
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
-    }
-  else
-    {
-      if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
-	return;
+      if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
+	inst.size_req = 4;
+      else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
+	inst.size_req = 2;
+      else
+	return 0;
 
-      if (skip_past_comma (&str) == FAIL)
-	{
-	  /* Two operand format, shuffle the registers
-	     and pretend there are 3.  */
-	  Rn = Rs;
-	  Rs = Rd;
-	}
-      else if (is_immediate_prefix (*str))
-	{
-	  str++;
-	  if (my_get_expression (&inst.reloc.exp, &str))
-	    return;
-	}
-      else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
-	return;
+      *str = end + 2;
     }
+  else
+    *str = end;
 
-  /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
-     for the latter case, EXPR contains the immediate that was found.  */
-
-  if (Rn != FAIL)
+  /* Look for unaffixed or special-case affixed mnemonic.  */
+  opcode = hash_find_n (arm_ops_hsh, base, end - base);
+  if (opcode)
     {
-      if (Rs != Rd)
+      /* step U */
+      if (opcode->tag < OT_odd_infix_0)
 	{
-	  inst.error = _("source1 and dest must be same register");
-	  return;
+	  inst.cond = COND_ALWAYS;
+	  return opcode;
 	}
 
-      switch (shift)
-	{
-	case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
-	case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
-	case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
-	}
+      if (unified_syntax)
+	as_warn (_("conditional infixes are deprecated in unified syntax"));
+      affix = base + (opcode->tag - OT_odd_infix_0);
+      cond = hash_find_n (arm_cond_hsh, affix, 2);
+      assert (cond);
 
-      inst.instruction |= Rd | (Rn << 3);
+      inst.cond = cond->value;
+      return opcode;
     }
-  else
+
+  /* Cannot have a conditional suffix on a mnemonic of less than two
+     characters.  */
+  if (end - base < 3)
+    return 0;
+
+  /* Look for suffixed mnemonic.  */
+  affix = end - 2;
+  cond = hash_find_n (arm_cond_hsh, affix, 2);
+  opcode = hash_find_n (arm_ops_hsh, base, affix - base);
+  if (opcode && cond)
     {
-      switch (shift)
+      /* step CE */
+      switch (opcode->tag)
 	{
-	case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
-	case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
-	case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
-	}
+	case OT_cinfix3_legacy:
+	  /* Ignore conditional suffixes matched on infix only mnemonics.  */
+	  break;
 
-      if (inst.reloc.exp.X_op != O_constant)
-	{
-	  /* Value isn't known yet, create a dummy reloc and let reloc
-	     hacking fix it up.  */
-	  inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
-	}
-      else
-	{
-	  unsigned shift_value = inst.reloc.exp.X_add_number;
+	case OT_cinfix3:
+	case OT_odd_infix_unc:
+	  if (!unified_syntax)
+	    return 0;
+	  /* else fall through */
 
-	  if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
+	case OT_csuffix:
+	case OT_csuf_or_in3:
+	  inst.cond = cond->value;
+	  return opcode;
+
+	case OT_unconditional:
+	case OT_unconditionalF:
+	  if (thumb_mode)
 	    {
-	      inst.error = _("invalid immediate for shift");
-	      return;
+	      inst.cond = cond->value;
 	    }
+	  else
+	    {
+	      /* delayed diagnostic */
+	      inst.error = BAD_COND;
+	      inst.cond = COND_ALWAYS;
+	    }
+	  return opcode;
 
-	  /* Shifts of zero are handled by converting to LSL.  */
-	  if (shift_value == 0)
-	    inst.instruction = T_OPCODE_LSL_I;
-
-	  /* Shifts of 32 are encoded as a shift of zero.  */
-	  if (shift_value == 32)
-	    shift_value = 0;
-
-	  inst.instruction |= shift_value << 6;
+	default:
+	  return 0;
 	}
-
-      inst.instruction |= Rd | (Rs << 3);
     }
 
-  end_of_line (str);
-}
+  /* Cannot have a usual-position infix on a mnemonic of less than
+     six characters (five would be a suffix).  */
+  if (end - base < 6)
+    return 0;
 
-static void
-thumb_mov_compare (str, move)
-     char * str;
-     int    move;
-{
-  int Rd, Rs = FAIL;
+  /* Look for infixed mnemonic in the usual position.  */
+  affix = base + 3;
+  cond = hash_find_n (arm_cond_hsh, affix, 2);
+  if (!cond)
+    return 0;
 
-  skip_whitespace (str);
+  memcpy (save, affix, 2);
+  memmove (affix, affix + 2, (end - affix) - 2);
+  opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
+  memmove (affix + 2, affix, (end - affix) - 2);
+  memcpy (affix, save, 2);
 
-  if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
-      || skip_past_comma (&str) == FAIL)
+  if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
+		 || opcode->tag == OT_cinfix3_legacy))
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
+      /* step CM */
+      if (unified_syntax && opcode->tag == OT_cinfix3)
+	as_warn (_("conditional infixes are deprecated in unified syntax"));
 
-  if (move != THUMB_CPY && is_immediate_prefix (*str))
-    {
-      str++;
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
+      inst.cond = cond->value;
+      return opcode;
     }
-  else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
-    return;
 
-  if (Rs != FAIL)
-    {
-      if (move != THUMB_CPY && Rs < 8 && Rd < 8)
-	{
-	  if (move == THUMB_MOVE)
-	    /* A move of two lowregs is encoded as ADD Rd, Rs, #0
-	       since a MOV instruction produces unpredictable results.  */
-	    inst.instruction = T_OPCODE_ADD_I3;
-	  else
-	    inst.instruction = T_OPCODE_CMP_LR;
-	  inst.instruction |= Rd | (Rs << 3);
-	}
-      else
-	{
-	  if (move == THUMB_MOVE)
-	    inst.instruction = T_OPCODE_MOV_HR;
-	  else if (move != THUMB_CPY)
-	    inst.instruction = T_OPCODE_CMP_HR;
-
-	  if (Rd > 7)
-	    inst.instruction |= THUMB_H1;
+  return 0;
+}
 
-	  if (Rs > 7)
-	    inst.instruction |= THUMB_H2;
+void
+md_assemble (char *str)
+{
+  char *p = str;
+  const struct asm_opcode * opcode;
 
-	  inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
-	}
-    }
-  else
+  /* Align the previous label if needed.  */
+  if (last_label_seen != NULL)
     {
-      if (Rd > 7)
-	{
-	  inst.error = _("only lo regs allowed with immediate");
-	  return;
-	}
-
-      if (move == THUMB_MOVE)
-	inst.instruction = T_OPCODE_MOV_I8;
-      else
-	inst.instruction = T_OPCODE_CMP_I8;
-
-      inst.instruction |= Rd << 8;
-
-      if (inst.reloc.exp.X_op != O_constant)
-	inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
-      else
-	{
-	  unsigned value = inst.reloc.exp.X_add_number;
-
-	  if (value > 255)
-	    {
-	      inst.error = _("invalid immediate");
-	      return;
-	    }
-
-	  inst.instruction |= value;
-	}
+      symbol_set_frag (last_label_seen, frag_now);
+      S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
+      S_SET_SEGMENT (last_label_seen, now_seg);
     }
 
-  end_of_line (str);
-}
-
-static void
-thumb_load_store (str, load_store, size)
-     char * str;
-     int    load_store;
-     int    size;
-{
-  int Rd, Rb, Ro = FAIL;
-
-  skip_whitespace (str);
+  memset (&inst, '\0', sizeof (inst));
+  inst.reloc.type = BFD_RELOC_UNUSED;
 
-  if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || skip_past_comma (&str) == FAIL)
+  opcode = opcode_lookup (&p);
+  if (!opcode)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
+      /* It wasn't an instruction, but it might be a register alias of
+	 the form alias .req reg.  */
+      if (!create_register_alias (str, p))
+	as_bad (_("bad instruction `%s'"), str);
+
       return;
     }
 
-  if (*str == '[')
+  if (thumb_mode)
     {
-      str++;
-      if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
-	return;
+      arm_feature_set variant;
 
-      if (skip_past_comma (&str) != FAIL)
+      variant = cpu_variant;
+      /* Only allow coprocessor instructions on Thumb-2 capable devices.  */
+      if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
+	ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
+      /* Check that this instruction is supported for this CPU.  */
+      if (!opcode->tvariant
+	  || (thumb_mode == 1
+	      && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
 	{
-	  if (is_immediate_prefix (*str))
-	    {
-	      str++;
-	      if (my_get_expression (&inst.reloc.exp, &str))
-		return;
-	    }
-	  else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
-	    return;
+	  as_bad (_("selected processor does not support `%s'"), str);
+	  return;
 	}
-      else
+      if (inst.cond != COND_ALWAYS && !unified_syntax
+	  && opcode->tencode != do_t_branch)
 	{
-	  inst.reloc.exp.X_op = O_constant;
-	  inst.reloc.exp.X_add_number = 0;
+	  as_bad (_("Thumb does not support conditional execution"));
+	  return;
 	}
 
-      if (*str != ']')
+      /* Check conditional suffixes.  */
+      if (current_it_mask)
 	{
-	  inst.error = _("expected ']'");
-	  return;
+	  int cond;
+	  cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
+	  current_it_mask <<= 1;
+	  current_it_mask &= 0x1f;
+	  /* The BKPT instruction is unconditional even in an IT block.  */
+	  if (!inst.error
+	      && cond != inst.cond && opcode->tencode != do_t_bkpt)
+	    {
+	      as_bad (_("incorrect condition in IT block"));
+	      return;
+	    }
 	}
-      str++;
-    }
-  else if (*str == '=')
-    {
-      if (load_store != THUMB_LOAD)
+      else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
 	{
-	  inst.error = _("invalid pseudo operation");
+	  as_bad (_("thumb conditional instrunction not in IT block"));
 	  return;
 	}
 
-      /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op.  */
-      str++;
-
-      skip_whitespace (str);
-
-      if (my_get_expression (& inst.reloc.exp, & str))
-	return;
-
-      end_of_line (str);
-
-      if (   inst.reloc.exp.X_op != O_constant
-	  && inst.reloc.exp.X_op != O_symbol)
-	{
-	  inst.error = "Constant expression expected";
-	  return;
-	}
+      mapping_state (MAP_THUMB);
+      inst.instruction = opcode->tvalue;
 
-      if (inst.reloc.exp.X_op == O_constant
-	  && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
-	{
-	  /* This can be done with a mov instruction.  */
+      if (!parse_operands (p, opcode->operands))
+	opcode->tencode ();
 
-	  inst.instruction  = T_OPCODE_MOV_I8 | (Rd << 8);
-	  inst.instruction |= inst.reloc.exp.X_add_number;
-	  return;
-	}
+      /* Clear current_it_mask at the end of an IT block.  */
+      if (current_it_mask == 0x10)
+	current_it_mask = 0;
 
-      /* Insert into literal pool.  */
-      if (add_to_lit_pool () == FAIL)
+      if (!(inst.error || inst.relax))
 	{
-	  if (!inst.error)
-	    inst.error = "literal pool insertion failed";
-	  return;
+	  assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
+	  inst.size = (inst.instruction > 0xffff ? 4 : 2);
+	  if (inst.size_req && inst.size_req != inst.size)
+	    {
+	      as_bad (_("cannot honor width suffix -- `%s'"), str);
+	      return;
+	    }
 	}
-
-      inst.reloc.type   = BFD_RELOC_ARM_THUMB_OFFSET;
-      inst.reloc.pc_rel = 1;
-      inst.instruction  = T_OPCODE_LDR_PC | (Rd << 8);
-      /* Adjust ARM pipeline offset to Thumb.  */
-      inst.reloc.exp.X_add_number += 4;
-
-      return;
+      ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+			      *opcode->tvariant);
+      /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
+	 set those bits when Thumb-2 32-bit instuctions are seen.  ie.
+	 anything other than bl/blx.
+	 This is overly pessimistic for relaxable instructions.  */
+      if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
+	  || inst.relax)
+	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
+				arm_ext_v6t2);
     }
   else
     {
-      if (my_get_expression (&inst.reloc.exp, &str))
-	return;
-
-      inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
-      inst.reloc.pc_rel = 1;
-      inst.reloc.exp.X_add_number -= 4; /* Pipeline offset.  */
-      inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
-      end_of_line (str);
-      return;
-    }
-
-  if (Rb == REG_PC || Rb == REG_SP)
-    {
-      if (size != THUMB_WORD)
+      /* Check that this instruction is supported for this CPU.  */
+      if (!opcode->avariant ||
+	  !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
 	{
-	  inst.error = _("byte or halfword not valid for base register");
+	  as_bad (_("selected processor does not support `%s'"), str);
 	  return;
 	}
-      else if (Rb == REG_PC && load_store != THUMB_LOAD)
+      if (inst.size_req)
 	{
-	  inst.error = _("r15 based store not allowed");
+	  as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
 	  return;
 	}
-      else if (Ro != FAIL)
-	{
-	  inst.error = _("invalid base register for register offset");
-	  return;
-	}
-
-      if (Rb == REG_PC)
-	inst.instruction = T_OPCODE_LDR_PC;
-      else if (load_store == THUMB_LOAD)
-	inst.instruction = T_OPCODE_LDR_SP;
-      else
-	inst.instruction = T_OPCODE_STR_SP;
 
-      inst.instruction |= Rd << 8;
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  unsigned offset = inst.reloc.exp.X_add_number;
-
-	  if (offset & ~0x3fc)
-	    {
-	      inst.error = _("invalid offset");
-	      return;
-	    }
-
-	  inst.instruction |= offset >> 2;
-	}
-      else
-	inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
-    }
-  else if (Rb > 7)
-    {
-      inst.error = _("invalid base register in load/store");
-      return;
-    }
-  else if (Ro == FAIL)
-    {
-      /* Immediate offset.  */
-      if (size == THUMB_WORD)
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
-      else if (size == THUMB_HALFWORD)
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
-      else
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
-
-      inst.instruction |= Rd | (Rb << 3);
-
-      if (inst.reloc.exp.X_op == O_constant)
-	{
-	  unsigned offset = inst.reloc.exp.X_add_number;
-
-	  if (offset & ~(0x1f << size))
-	    {
-	      inst.error = _("invalid offset");
-	      return;
-	    }
-	  inst.instruction |= (offset >> size) << 6;
-	}
+      mapping_state (MAP_ARM);
+      inst.instruction = opcode->avalue;
+      if (opcode->tag == OT_unconditionalF)
+	inst.instruction |= 0xF << 28;
       else
-	inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
-    }
-  else
-    {
-      /* Register offset.  */
-      if (size == THUMB_WORD)
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
-      else if (size == THUMB_HALFWORD)
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
+	inst.instruction |= inst.cond << 28;
+      inst.size = INSN_SIZE;
+      if (!parse_operands (p, opcode->operands))
+	opcode->aencode ();
+      /* Arm mode bx is marked as both v4T and v5 because it's still required
+         on a hypothetical non-thumb v5 core.  */
+      if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
+	  || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
+	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
       else
-	inst.instruction = (load_store == THUMB_LOAD
-			    ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
-
-      inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
+	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
+				*opcode->avariant);
     }
-
-  end_of_line (str);
+  output_inst (str);
 }
 
-/* A register must be given at this point.
+/* Various frobbings of labels and their addresses.  */
 
-   Shift is the place to put it in inst.instruction.
-
-   Restores input start point on err.
-   Returns the reg#, or FAIL.  */
-
-static int
-mav_reg_required_here (str, shift, regtype)
-     char ** str;
-     int shift;
-     enum arm_reg_type regtype;
+void
+arm_start_line_hook (void)
 {
-  int   reg;
-  char *start = *str;
-
-  if ((reg = arm_reg_parse (str, all_reg_maps[regtype].htab)) != FAIL)
-    {
-      if (shift >= 0)
-	inst.instruction |= reg << shift;
-
-      return reg;
-    }
+  last_label_seen = NULL;
+}
 
-  /* Restore the start point.  */
-  *str = start;
+void
+arm_frob_label (symbolS * sym)
+{
+  last_label_seen = sym;
 
-  /* In the few cases where we might be able to accept something else
-     this error can be overridden.  */
-  inst.error = _(all_reg_maps[regtype].expected);
+  ARM_SET_THUMB (sym, thumb_mode);
 
-  return FAIL;
-}
+#if defined OBJ_COFF || defined OBJ_ELF
+  ARM_SET_INTERWORK (sym, support_interwork);
+#endif
 
-/* Cirrus Maverick Instructions.  */
+  /* Note - do not allow local symbols (.Lxxx) to be labeled
+     as Thumb functions.  This is because these labels, whilst
+     they exist inside Thumb code, are not the entry points for
+     possible ARM->Thumb calls.	 Also, these labels can be used
+     as part of a computed goto or switch statement.  eg gcc
+     can generate code that looks like this:
 
-/* Wrapper functions.  */
+		ldr  r2, [pc, .Laaa]
+		lsl  r3, r3, #2
+		ldr  r2, [r3, r2]
+		mov  pc, r2
 
-static void
-do_mav_binops_1a (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVF);
-}
+       .Lbbb:  .word .Lxxx
+       .Lccc:  .word .Lyyy
+       ..etc...
+       .Laaa:	.word Lbbb
 
-static void
-do_mav_binops_1b (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVD);
-}
+     The first instruction loads the address of the jump table.
+     The second instruction converts a table index into a byte offset.
+     The third instruction gets the jump address out of the table.
+     The fourth instruction performs the jump.
 
-static void
-do_mav_binops_1c (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_RN, REG_TYPE_MVDX);
-}
+     If the address stored at .Laaa is that of a symbol which has the
+     Thumb_Func bit set, then the linker will arrange for this address
+     to have the bottom bit set, which in turn would mean that the
+     address computation performed by the third instruction would end
+     up with the bottom bit set.  Since the ARM is capable of unaligned
+     word loads, the instruction would then load the incorrect address
+     out of the jump table, and chaos would ensue.  */
+  if (label_is_thumb_function_name
+      && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
+      && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    {
+      /* When the address of a Thumb function is taken the bottom
+	 bit of that address should be set.  This will allow
+	 interworking between Arm and Thumb functions to work
+	 correctly.  */
 
-static void
-do_mav_binops_1d (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVF);
-}
+      THUMB_SET_FUNC (sym, 1);
 
-static void
-do_mav_binops_1e (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVD);
-}
+      label_is_thumb_function_name = FALSE;
+    }
 
-static void
-do_mav_binops_1f (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVF);
+#ifdef OBJ_ELF
+  dwarf2_emit_label (sym);
+#endif
 }
 
-static void
-do_mav_binops_1g (str)
-     char * str;
+int
+arm_data_in_code (void)
 {
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVD);
-}
+  if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
+    {
+      *input_line_pointer = '/';
+      input_line_pointer += 5;
+      *input_line_pointer = 0;
+      return 1;
+    }
 
-static void
-do_mav_binops_1h (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVFX);
+  return 0;
 }
 
-static void
-do_mav_binops_1i (str)
-     char * str;
+char *
+arm_canonicalize_symbol_name (char * name)
 {
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVFX);
-}
+  int len;
 
-static void
-do_mav_binops_1j (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVF, REG_TYPE_MVDX);
-}
+  if (thumb_mode && (len = strlen (name)) > 5
+      && streq (name + len - 5, "/data"))
+    *(name + len - 5) = 0;
 
-static void
-do_mav_binops_1k (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVD, REG_TYPE_MVDX);
+  return name;
 }
+
+/* Table of all register names defined by default.  The user can
+   define additional names with .req.  Note that all register names
+   should appear in both upper and lowercase variants.	Some registers
+   also have mixed-case names.	*/
 
-static void
-do_mav_binops_1l (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVF);
-}
+#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
+#define REGNUM(p,n,t) REGDEF(p##n, n, t)
+#define REGSET(p,t) \
+  REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
+  REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
+  REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
+  REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
 
-static void
-do_mav_binops_1m (str)
-     char * str;
+static const struct reg_entry reg_names[] =
 {
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVD);
-}
+  /* ARM integer registers.  */
+  REGSET(r, RN), REGSET(R, RN),
 
-static void
-do_mav_binops_1n (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVFX, REG_TYPE_MVFX);
-}
+  /* ATPCS synonyms.  */
+  REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
+  REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
+  REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
 
-static void
-do_mav_binops_1o (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE1, REG_TYPE_MVDX, REG_TYPE_MVDX);
-}
+  REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
+  REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
+  REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
 
-static void
-do_mav_binops_2a (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE2, REG_TYPE_MVF, REG_TYPE_RN);
-}
+  /* Well-known aliases.  */
+  REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
+  REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
+
+  REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
+  REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
+
+  /* Coprocessor numbers.  */
+  REGSET(p, CP), REGSET(P, CP),
+
+  /* Coprocessor register numbers.  The "cr" variants are for backward
+     compatibility.  */
+  REGSET(c,  CN), REGSET(C, CN),
+  REGSET(cr, CN), REGSET(CR, CN),
+
+  /* FPA registers.  */
+  REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
+  REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
+
+  REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
+  REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
+
+  /* VFP SP registers.	*/
+  REGSET(s,VFS),
+  REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
+  REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
+  REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
+  REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
+
+  REGSET(S,VFS),
+  REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
+  REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
+  REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
+  REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
+
+  /* VFP DP Registers.	*/
+  REGSET(d,VFD), REGSET(D,VFS),
+
+  /* VFP control registers.  */
+  REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
+  REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
+
+  /* Maverick DSP coprocessor registers.  */
+  REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
+  REGSET(MVF,MVF),  REGSET(MVD,MVD),  REGSET(MVFX,MVFX),  REGSET(MVDX,MVDX),
+
+  REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
+  REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
+  REGDEF(dspsc,0,DSPSC),
+
+  REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
+  REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
+  REGDEF(DSPSC,0,DSPSC),
+
+  /* iWMMXt data registers - p0, c0-15.	 */
+  REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
+
+  /* iWMMXt control registers - p1, c0-3.  */
+  REGDEF(wcid,	0,MMXWC),  REGDEF(wCID,	 0,MMXWC),  REGDEF(WCID,  0,MMXWC),
+  REGDEF(wcon,	1,MMXWC),  REGDEF(wCon,	 1,MMXWC),  REGDEF(WCON,  1,MMXWC),
+  REGDEF(wcssf, 2,MMXWC),  REGDEF(wCSSF, 2,MMXWC),  REGDEF(WCSSF, 2,MMXWC),
+  REGDEF(wcasf, 3,MMXWC),  REGDEF(wCASF, 3,MMXWC),  REGDEF(WCASF, 3,MMXWC),
+
+  /* iWMMXt scalar (constant/offset) registers - p1, c8-11.  */
+  REGDEF(wcgr0, 8,MMXWCG),  REGDEF(wCGR0, 8,MMXWCG),  REGDEF(WCGR0, 8,MMXWCG),
+  REGDEF(wcgr1, 9,MMXWCG),  REGDEF(wCGR1, 9,MMXWCG),  REGDEF(WCGR1, 9,MMXWCG),
+  REGDEF(wcgr2,10,MMXWCG),  REGDEF(wCGR2,10,MMXWCG),  REGDEF(WCGR2,10,MMXWCG),
+  REGDEF(wcgr3,11,MMXWCG),  REGDEF(wCGR3,11,MMXWCG),  REGDEF(WCGR3,11,MMXWCG),
+
+  /* XScale accumulator registers.  */
+  REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
+};
+#undef REGDEF
+#undef REGNUM
+#undef REGSET
 
-static void
-do_mav_binops_2b (str)
-     char * str;
+/* Table of all PSR suffixes.  Bare "CPSR" and "SPSR" are handled
+   within psr_required_here.  */
+static const struct asm_psr psrs[] =
 {
-  do_mav_binops (str, MAV_MODE2, REG_TYPE_MVD, REG_TYPE_RN);
-}
+  /* Backward compatibility notation.  Note that "all" is no longer
+     truly all possible PSR bits.  */
+  {"all",  PSR_c | PSR_f},
+  {"flg",  PSR_f},
+  {"ctl",  PSR_c},
+
+  /* Individual flags.	*/
+  {"f",	   PSR_f},
+  {"c",	   PSR_c},
+  {"x",	   PSR_x},
+  {"s",	   PSR_s},
+  /* Combinations of flags.  */
+  {"fs",   PSR_f | PSR_s},
+  {"fx",   PSR_f | PSR_x},
+  {"fc",   PSR_f | PSR_c},
+  {"sf",   PSR_s | PSR_f},
+  {"sx",   PSR_s | PSR_x},
+  {"sc",   PSR_s | PSR_c},
+  {"xf",   PSR_x | PSR_f},
+  {"xs",   PSR_x | PSR_s},
+  {"xc",   PSR_x | PSR_c},
+  {"cf",   PSR_c | PSR_f},
+  {"cs",   PSR_c | PSR_s},
+  {"cx",   PSR_c | PSR_x},
+  {"fsx",  PSR_f | PSR_s | PSR_x},
+  {"fsc",  PSR_f | PSR_s | PSR_c},
+  {"fxs",  PSR_f | PSR_x | PSR_s},
+  {"fxc",  PSR_f | PSR_x | PSR_c},
+  {"fcs",  PSR_f | PSR_c | PSR_s},
+  {"fcx",  PSR_f | PSR_c | PSR_x},
+  {"sfx",  PSR_s | PSR_f | PSR_x},
+  {"sfc",  PSR_s | PSR_f | PSR_c},
+  {"sxf",  PSR_s | PSR_x | PSR_f},
+  {"sxc",  PSR_s | PSR_x | PSR_c},
+  {"scf",  PSR_s | PSR_c | PSR_f},
+  {"scx",  PSR_s | PSR_c | PSR_x},
+  {"xfs",  PSR_x | PSR_f | PSR_s},
+  {"xfc",  PSR_x | PSR_f | PSR_c},
+  {"xsf",  PSR_x | PSR_s | PSR_f},
+  {"xsc",  PSR_x | PSR_s | PSR_c},
+  {"xcf",  PSR_x | PSR_c | PSR_f},
+  {"xcs",  PSR_x | PSR_c | PSR_s},
+  {"cfs",  PSR_c | PSR_f | PSR_s},
+  {"cfx",  PSR_c | PSR_f | PSR_x},
+  {"csf",  PSR_c | PSR_s | PSR_f},
+  {"csx",  PSR_c | PSR_s | PSR_x},
+  {"cxf",  PSR_c | PSR_x | PSR_f},
+  {"cxs",  PSR_c | PSR_x | PSR_s},
+  {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
+  {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
+  {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
+  {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
+  {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
+  {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
+  {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
+  {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
+  {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
+  {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
+  {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
+  {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
+  {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
+  {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
+  {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
+  {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
+  {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
+  {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
+  {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
+  {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
+  {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
+  {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
+  {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
+  {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
+};
 
-static void
-do_mav_binops_2c (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE2, REG_TYPE_MVDX, REG_TYPE_RN);
-}
+/* Table of V7M psr names.  */
+static const struct asm_psr v7m_psrs[] =
+{
+  {"apsr",	0 },
+  {"iapsr",	1 },
+  {"eapsr",	2 },
+  {"psr",	3 },
+  {"ipsr",	5 },
+  {"epsr",	6 },
+  {"iepsr",	7 },
+  {"msp",	8 },
+  {"psp",	9 },
+  {"primask",	16},
+  {"basepri",	17},
+  {"basepri_max", 18},
+  {"faultmask",	19},
+  {"control",	20}
+};
 
-static void
-do_mav_binops_3a (str)
-     char * str;
+/* Table of all shift-in-operand names.	 */
+static const struct asm_shift_name shift_names [] =
 {
-  do_mav_binops (str, MAV_MODE3, REG_TYPE_MVAX, REG_TYPE_MVFX);
-}
+  { "asl", SHIFT_LSL },	 { "ASL", SHIFT_LSL },
+  { "lsl", SHIFT_LSL },	 { "LSL", SHIFT_LSL },
+  { "lsr", SHIFT_LSR },	 { "LSR", SHIFT_LSR },
+  { "asr", SHIFT_ASR },	 { "ASR", SHIFT_ASR },
+  { "ror", SHIFT_ROR },	 { "ROR", SHIFT_ROR },
+  { "rrx", SHIFT_RRX },	 { "RRX", SHIFT_RRX }
+};
 
-static void
-do_mav_binops_3b (str)
-     char * str;
-{
-  do_mav_binops (str, MAV_MODE3, REG_TYPE_MVFX, REG_TYPE_MVAX);
-}
+/* Table of all explicit relocation names.  */
+#ifdef OBJ_ELF
+static struct reloc_entry reloc_names[] =
+{
+  { "got",     BFD_RELOC_ARM_GOT32   },	 { "GOT",     BFD_RELOC_ARM_GOT32   },
+  { "gotoff",  BFD_RELOC_ARM_GOTOFF  },	 { "GOTOFF",  BFD_RELOC_ARM_GOTOFF  },
+  { "plt",     BFD_RELOC_ARM_PLT32   },	 { "PLT",     BFD_RELOC_ARM_PLT32   },
+  { "target1", BFD_RELOC_ARM_TARGET1 },	 { "TARGET1", BFD_RELOC_ARM_TARGET1 },
+  { "target2", BFD_RELOC_ARM_TARGET2 },	 { "TARGET2", BFD_RELOC_ARM_TARGET2 },
+  { "sbrel",   BFD_RELOC_ARM_SBREL32 },	 { "SBREL",   BFD_RELOC_ARM_SBREL32 },
+  { "tlsgd",   BFD_RELOC_ARM_TLS_GD32},  { "TLSGD",   BFD_RELOC_ARM_TLS_GD32},
+  { "tlsldm",  BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM",  BFD_RELOC_ARM_TLS_LDM32},
+  { "tlsldo",  BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO",  BFD_RELOC_ARM_TLS_LDO32},
+  { "gottpoff",BFD_RELOC_ARM_TLS_IE32},  { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
+  { "tpoff",   BFD_RELOC_ARM_TLS_LE32},  { "TPOFF",   BFD_RELOC_ARM_TLS_LE32}
+};
+#endif
 
-static void
-do_mav_binops_3c (str)
-     char * str;
+/* Table of all conditional affixes.  0xF is not defined as a condition code.  */
+static const struct asm_cond conds[] =
 {
-  do_mav_binops (str, MAV_MODE3, REG_TYPE_MVAX, REG_TYPE_MVDX);
-}
+  {"eq", 0x0},
+  {"ne", 0x1},
+  {"cs", 0x2}, {"hs", 0x2},
+  {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
+  {"mi", 0x4},
+  {"pl", 0x5},
+  {"vs", 0x6},
+  {"vc", 0x7},
+  {"hi", 0x8},
+  {"ls", 0x9},
+  {"ge", 0xa},
+  {"lt", 0xb},
+  {"gt", 0xc},
+  {"le", 0xd},
+  {"al", 0xe}
+};
 
-static void
-do_mav_binops_3d (str)
-     char * str;
+static struct asm_barrier_opt barrier_opt_names[] =
 {
-  do_mav_binops (str, MAV_MODE3, REG_TYPE_MVDX, REG_TYPE_MVAX);
-}
+  { "sy",   0xf },
+  { "un",   0x7 },
+  { "st",   0xe },
+  { "unst", 0x6 }
+};
 
-static void
-do_mav_triple_4a (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE4, REG_TYPE_MVFX, REG_TYPE_MVFX, REG_TYPE_RN);
-}
+/* Table of ARM-format instructions.	*/
+
+/* Macros for gluing together operand strings.  N.B. In all cases
+   other than OPS0, the trailing OP_stop comes from default
+   zero-initialization of the unspecified elements of the array.  */
+#define OPS0()		  { OP_stop, }
+#define OPS1(a)		  { OP_##a, }
+#define OPS2(a,b)	  { OP_##a,OP_##b, }
+#define OPS3(a,b,c)	  { OP_##a,OP_##b,OP_##c, }
+#define OPS4(a,b,c,d)	  { OP_##a,OP_##b,OP_##c,OP_##d, }
+#define OPS5(a,b,c,d,e)	  { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
+#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
+
+/* These macros abstract out the exact format of the mnemonic table and
+   save some repeated characters.  */
+
+/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix.  */
+#define TxCE(mnem, op, top, nops, ops, ae, te) \
+  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
+
+/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
+   a T_MNEM_xyz enumerator.  */
+#define TCE(mnem, aop, top, nops, ops, ae, te) \
+       TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
+#define tCE(mnem, aop, top, nops, ops, ae, te) \
+       TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
+
+/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
+   infix after the third character.  */
+#define TxC3(mnem, op, top, nops, ops, ae, te) \
+  { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
+#define TC3(mnem, aop, top, nops, ops, ae, te) \
+       TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
+#define tC3(mnem, aop, top, nops, ops, ae, te) \
+       TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
+
+/* Mnemonic with a conditional infix in an unusual place.  Each and every variant has to
+   appear in the condition table.  */
+#define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te)	\
+  { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
+    0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
+
+#define TxCM(m1, m2, op, top, nops, ops, ae, te)	\
+  TxCM_(m1,   , m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, eq, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, ne, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, cs, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, hs, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, cc, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, ul, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, lo, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, mi, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, pl, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, vs, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, vc, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, hi, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, ls, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, ge, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, lt, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, gt, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, le, m2, op, top, nops, ops, ae, te),	\
+  TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
+
+#define TCM(m1,m2, aop, top, nops, ops, ae, te)		\
+       TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
+#define tCM(m1,m2, aop, top, nops, ops, ae, te)			\
+       TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
+
+/* Mnemonic that cannot be conditionalized.  The ARM condition-code
+   field is still 0xE.  Many of the Thumb variants can be executed
+   conditionally, so this is checked separately.  */
+#define TUE(mnem, op, top, nops, ops, ae, te)				\
+  { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
+
+/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
+   condition code field.  */
+#define TUF(mnem, op, top, nops, ops, ae, te)				\
+  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
+    THUMB_VARIANT, do_##ae, do_##te }
+
+/* ARM-only variants of all the above.  */
+#define CE(mnem,  op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+
+#define C3(mnem, op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+
+/* Legacy mnemonics that always have conditional infix after the third
+   character.  */
+#define CL(mnem, op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
+    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+
+/* Coprocessor instructions.  Isomorphic between Arm and Thumb-2.  */
+#define cCE(mnem,  op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
+
+/* Legacy coprocessor instructions where conditional infix and conditional
+   suffix are ambiguous.  For consistency this includes all FPA instructions,
+   not just the potentially ambiguous ones.  */
+#define cCL(mnem, op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
+    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
+
+/* Coprocessor, takes either a suffix or a position-3 infix
+   (for an FPA corner case). */
+#define C3E(mnem, op, nops, ops, ae) \
+  { #mnem, OPS##nops ops, OT_csuf_or_in3, \
+    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
+
+#define xCM_(m1, m2, m3, op, nops, ops, ae)	\
+  { #m1 #m2 #m3, OPS##nops ops, \
+    sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
+    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
+
+#define CM(m1, m2, op, nops, ops, ae)	\
+  xCM_(m1,   , m2, op, nops, ops, ae),	\
+  xCM_(m1, eq, m2, op, nops, ops, ae),	\
+  xCM_(m1, ne, m2, op, nops, ops, ae),	\
+  xCM_(m1, cs, m2, op, nops, ops, ae),	\
+  xCM_(m1, hs, m2, op, nops, ops, ae),	\
+  xCM_(m1, cc, m2, op, nops, ops, ae),	\
+  xCM_(m1, ul, m2, op, nops, ops, ae),	\
+  xCM_(m1, lo, m2, op, nops, ops, ae),	\
+  xCM_(m1, mi, m2, op, nops, ops, ae),	\
+  xCM_(m1, pl, m2, op, nops, ops, ae),	\
+  xCM_(m1, vs, m2, op, nops, ops, ae),	\
+  xCM_(m1, vc, m2, op, nops, ops, ae),	\
+  xCM_(m1, hi, m2, op, nops, ops, ae),	\
+  xCM_(m1, ls, m2, op, nops, ops, ae),	\
+  xCM_(m1, ge, m2, op, nops, ops, ae),	\
+  xCM_(m1, lt, m2, op, nops, ops, ae),	\
+  xCM_(m1, gt, m2, op, nops, ops, ae),	\
+  xCM_(m1, le, m2, op, nops, ops, ae),	\
+  xCM_(m1, al, m2, op, nops, ops, ae)
+
+#define UE(mnem, op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
+
+#define UF(mnem, op, nops, ops, ae)	\
+  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
+
+#define do_0 0
+
+/* Thumb-only, unconditional.  */
+#define UT(mnem,  op, nops, ops, te) TUE(mnem,  0, op, nops, ops, 0, te)
 
-static void
-do_mav_triple_4b (str)
-     char * str;
+static const struct asm_opcode insns[] =
 {
-  do_mav_triple (str, MAV_MODE4, REG_TYPE_MVDX, REG_TYPE_MVDX, REG_TYPE_RN);
-}
+#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions.  */
+#define THUMB_VARIANT &arm_ext_v4t
+ tCE(and,	0000000, and,      3, (RR, oRR, SH), arit, t_arit3c),
+ tC3(ands,	0100000, ands,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tCE(eor,	0200000, eor,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tC3(eors,	0300000, eors,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tCE(sub,	0400000, sub,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tC3(subs,	0500000, subs,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tCE(add,	0800000, add,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tC3(adds,	0900000, adds,	   3, (RR, oRR, SH), arit, t_add_sub),
+ tCE(adc,	0a00000, adc,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tC3(adcs,	0b00000, adcs,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tCE(sbc,	0c00000, sbc,	   3, (RR, oRR, SH), arit, t_arit3),
+ tC3(sbcs,	0d00000, sbcs,	   3, (RR, oRR, SH), arit, t_arit3),
+ tCE(orr,	1800000, orr,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tC3(orrs,	1900000, orrs,	   3, (RR, oRR, SH), arit, t_arit3c),
+ tCE(bic,	1c00000, bic,	   3, (RR, oRR, SH), arit, t_arit3),
+ tC3(bics,	1d00000, bics,	   3, (RR, oRR, SH), arit, t_arit3),
+
+ /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
+    for setting PSR flag bits.  They are obsolete in V6 and do not
+    have Thumb equivalents. */
+ tCE(tst,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3(tsts,	1100000, tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
+  CL(tstp,	110f000,     	   2, (RR, SH),      cmp),
+ tCE(cmp,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
+ tC3(cmps,	1500000, cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
+  CL(cmpp,	150f000,     	   2, (RR, SH),      cmp),
+ tCE(cmn,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
+ tC3(cmns,	1700000, cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
+  CL(cmnp,	170f000,     	   2, (RR, SH),      cmp),
+
+ tCE(mov,	1a00000, mov,	   2, (RR, SH),      mov,  t_mov_cmp),
+ tC3(movs,	1b00000, movs,	   2, (RR, SH),      mov,  t_mov_cmp),
+ tCE(mvn,	1e00000, mvn,	   2, (RR, SH),      mov,  t_mvn_tst),
+ tC3(mvns,	1f00000, mvns,	   2, (RR, SH),      mov,  t_mvn_tst),
+
+ tCE(ldr,	4100000, ldr,	   2, (RR, ADDR),    ldst, t_ldst),
+ tC3(ldrb,	4500000, ldrb,	   2, (RR, ADDR),    ldst, t_ldst),
+ tCE(str,	4000000, str,	   2, (RR, ADDR),    ldst, t_ldst),
+ tC3(strb,	4400000, strb,	   2, (RR, ADDR),    ldst, t_ldst),
+
+ tCE(stm,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tC3(stmia,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tC3(stmea,	8800000, stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tCE(ldm,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tC3(ldmia,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tC3(ldmfd,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
+
+ TCE(swi,	f000000, df00,     1, (EXPi),        swi, t_swi),
+ TCE(svc,	f000000, df00,     1, (EXPi),        swi, t_swi),
+ tCE(b,		a000000, b,	   1, (EXPr),	     branch, t_branch),
+ TCE(bl,	b000000, f000f800, 1, (EXPr),	     bl, t_branch23),
 
-static void
-do_mav_triple_5a (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVF, REG_TYPE_MVF);
-}
+  /* Pseudo ops.  */
+ tCE(adr,	28f0000, adr,	   2, (RR, EXP),     adr,  t_adr),
+  C3(adrl,	28f0000,           2, (RR, EXP),     adrl),
+ tCE(nop,	1a00000, nop,	   1, (oI255c),	     nop,  t_nop),
+
+  /* Thumb-compatibility pseudo ops.  */
+ tCE(lsl,	1a00000, lsl,	   3, (RR, oRR, SH), shift, t_shift),
+ tC3(lsls,	1b00000, lsls,	   3, (RR, oRR, SH), shift, t_shift),
+ tCE(lsr,	1a00020, lsr,	   3, (RR, oRR, SH), shift, t_shift),
+ tC3(lsrs,	1b00020, lsrs,	   3, (RR, oRR, SH), shift, t_shift),
+ tCE(asr,	1a00040, asr,	   3, (RR, oRR, SH), shift, t_shift),
+ tC3(asrs,      1b00040, asrs,     3, (RR, oRR, SH), shift, t_shift),
+ tCE(ror,	1a00060, ror,	   3, (RR, oRR, SH), shift, t_shift),
+ tC3(rors,	1b00060, rors,	   3, (RR, oRR, SH), shift, t_shift),
+ tCE(neg,	2600000, neg,	   2, (RR, RR),      rd_rn, t_neg),
+ tC3(negs,	2700000, negs,	   2, (RR, RR),      rd_rn, t_neg),
+ tCE(push,	92d0000, push,     1, (REGLST),	     push_pop, t_push_pop),
+ tCE(pop,	8bd0000, pop,	   1, (REGLST),	     push_pop, t_push_pop),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6
+ TCE(cpy,       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
+
+ /* V1 instructions with no Thumb analogue prior to V6T2.  */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6t2
+ TCE(rsb,	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TC3(rsbs,	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+ TCE(teq,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
+ TC3(teqs,	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
+  CL(teqp,	130f000,           2, (RR, SH),      cmp),
+
+ TC3(ldrt,	4300000, f8500e00, 2, (RR, ADDR),    ldstt, t_ldstt),
+ TC3(ldrbt,	4700000, f8100e00, 2, (RR, ADDR),    ldstt, t_ldstt),
+ TC3(strt,	4200000, f8400e00, 2, (RR, ADDR),    ldstt, t_ldstt),
+ TC3(strbt,	4600000, f8000e00, 2, (RR, ADDR),    ldstt, t_ldstt),
+
+ TC3(stmdb,	9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+ TC3(stmfd,     9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+
+ TC3(ldmdb,	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+ TC3(ldmea,	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+
+ /* V1 instructions with no Thumb analogue at all.  */
+  CE(rsc,	0e00000,	   3, (RR, oRR, SH), arit),
+  C3(rscs,	0f00000,	   3, (RR, oRR, SH), arit),
+
+  C3(stmib,	9800000,	   2, (RRw, REGLST), ldmstm),
+  C3(stmfa,	9800000,	   2, (RRw, REGLST), ldmstm),
+  C3(stmda,	8000000,	   2, (RRw, REGLST), ldmstm),
+  C3(stmed,	8000000,	   2, (RRw, REGLST), ldmstm),
+  C3(ldmib,	9900000,	   2, (RRw, REGLST), ldmstm),
+  C3(ldmed,	9900000,	   2, (RRw, REGLST), ldmstm),
+  C3(ldmda,	8100000,	   2, (RRw, REGLST), ldmstm),
+  C3(ldmfa,	8100000,	   2, (RRw, REGLST), ldmstm),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v2	/* ARM 2 - multiplies.	*/
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v4t
+ tCE(mul,	0000090, mul,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
+ tC3(muls,	0100090, muls,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6t2
+ TCE(mla,	0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
+  C3(mlas,	0300090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
+
+  /* Generic coprocessor instructions.	*/
+ TCE(cdp,	e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
+ TCE(ldc,	c100000, ec100000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TC3(ldcl,	c500000, ec500000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TCE(stc,	c000000, ec000000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TC3(stcl,	c400000, ec400000, 3, (RCP, RCN, ADDR),		        lstc,   lstc),
+ TCE(mcr,	e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
+ TCE(mrc,	e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions.  */
+  CE(swp,	1000090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
+  C3(swpb,	1400090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v3	/* ARM 6 Status register instructions.	*/
+ TCE(mrs,	10f0000, f3ef8000, 2, (RR, PSR),     mrs, t_mrs),
+ TCE(msr,	120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v3m	 /* ARM 7M long multiplies.  */
+ TCE(smull,	0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
+  CM(smull,s,	0d00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ TCE(umull,	0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
+  CM(umull,s,	0900090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ TCE(smlal,	0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
+  CM(smlal,s,	0f00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+ TCE(umlal,	0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
+  CM(umlal,s,	0b00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v4	/* ARM Architecture 4.	*/
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v4t
+ tC3(ldrh,	01000b0, ldrh,     2, (RR, ADDR), ldstv4, t_ldst),
+ tC3(strh,	00000b0, strh,     2, (RR, ADDR), ldstv4, t_ldst),
+ tC3(ldrsh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
+ tC3(ldrsb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
+ tCM(ld,sh,	01000f0, ldrsh,    2, (RR, ADDR), ldstv4, t_ldst),
+ tCM(ld,sb,	01000d0, ldrsb,    2, (RR, ADDR), ldstv4, t_ldst),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v4t_5
+  /* ARM Architecture 4T.  */
+  /* Note: bx (and blx) are required on V5, even if the processor does
+     not support Thumb.	 */
+ TCE(bx,	12fff10, 4700, 1, (RR),	bx, t_bx),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v5 /*  ARM Architecture 5T.	 */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v5t
+  /* Note: blx has 2 variants; the .value coded here is for
+     BLX(2).  Only this variant has conditional execution.  */
+ TCE(blx,	12fff30, 4780, 1, (RR_EXr),			    blx,  t_blx),
+ TUE(bkpt,	1200070, be00, 1, (oIffffb),			    bkpt, t_bkpt),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6t2
+ TCE(clz,	16f0f10, fab0f080, 2, (RRnpc, RRnpc),		        rd_rm,  t_clz),
+ TUF(ldc2,	c100000, fc100000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(ldc2l,	c500000, fc500000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(stc2,	c000000, fc000000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(stc2l,	c400000, fc400000, 3, (RCP, RCN, ADDR),		        lstc,	lstc),
+ TUF(cdp2,	e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
+ TUF(mcr2,	e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
+ TUF(mrc2,	e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v5exp /*  ARM Architecture 5TExP.  */
+ TCE(smlabb,	1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+ TCE(smlatb,	10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+ TCE(smlabt,	10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+ TCE(smlatt,	10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+
+ TCE(smlawb,	1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+ TCE(smlawt,	12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
+
+ TCE(smlalbb,	1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
+ TCE(smlaltb,	14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
+ TCE(smlalbt,	14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
+ TCE(smlaltt,	14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
+
+ TCE(smulbb,	1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+ TCE(smultb,	16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+ TCE(smulbt,	16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+ TCE(smultt,	16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+
+ TCE(smulwb,	12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+ TCE(smulwt,	12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
+
+ TCE(qadd,	1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
+ TCE(qdadd,	1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
+ TCE(qsub,	1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
+ TCE(qdsub,	1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, rd_rm_rn),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v5e /*  ARM Architecture 5TE.  */
+ TUF(pld,	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
+ TC3(ldrd,	00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
+ TC3(strd,	00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
+
+ TCE(mcrr,	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
+ TCE(mrrc,	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v5j /*  ARM Architecture 5TEJ.  */
+ TCE(bxj,	12fff20, f3c08f00, 1, (RR),			  bxj, t_bxj),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v6 /*  ARM V6.  */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6
+ TUF(cpsie,     1080000, b660,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
+ TUF(cpsid,     10c0000, b670,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
+ tCE(rev,       6bf0f30, rev,      2, (RRnpc, RRnpc),             rd_rm,  t_rev),
+ tCE(rev16,     6bf0fb0, rev16,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
+ tCE(revsh,     6ff0fb0, revsh,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
+ tCE(sxth,      6bf0070, sxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
+ tCE(uxth,      6ff0070, uxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
+ tCE(sxtb,      6af0070, sxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
+ tCE(uxtb,      6ef0070, uxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
+ TUF(setend,    1010000, b650,     1, (ENDI),                     setend, t_setend),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6t2
+ TCE(ldrex,	1900f9f, e8500f00, 2, (RRnpc, ADDR),		  ldrex, t_ldrex),
+ TUF(mcrr2,	c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
+ TUF(mrrc2,	c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
+
+ TCE(ssat,	6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat,   t_ssat),
+ TCE(usat,	6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat,   t_usat),
+
+/*  ARM V6 not included in V7M (eg. integer SIMD).  */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6_notm
+ TUF(cps,	1020000, f3af8100, 1, (I31b),			  imm0, t_cps),
+ TCE(pkhbt,	6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll),   pkhbt, t_pkhbt),
+ TCE(pkhtb,	6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar),   pkhtb, t_pkhtb),
+ TCE(qadd16,	6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(qadd8,	6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(qaddsubx,	6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(qsub16,	6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(qsub8,	6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(qsubaddx,	6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(sadd16,	6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(sadd8,	6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(saddsubx,	6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shadd16,	6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shadd8,	6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shsub16,	6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shsub8,	6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(ssub16,	6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(ssub8,	6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(ssubaddx,	6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uadd16,	6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uadd8,	6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uaddsubx,	6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhadd16,	6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhadd8,	6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhsub16,	6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhsub8,	6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqadd16,	6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqadd8,	6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqsub16,	6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqsub8,	6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(usub16,	6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(usub8,	6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(usubaddx,	6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TUF(rfeia,	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
+  UF(rfeib,	9900a00,           1, (RRw),			   rfe),
+  UF(rfeda,	8100a00,           1, (RRw),			   rfe),
+ TUF(rfedb,	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
+ TUF(rfefd,	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
+  UF(rfefa,	9900a00,           1, (RRw),			   rfe),
+  UF(rfeea,	8100a00,           1, (RRw),			   rfe),
+ TUF(rfeed,	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
+ TCE(sxtah,	6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(sxtab16,	6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(sxtab,	6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(sxtb16,	68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
+ TCE(uxtah,	6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(uxtab16,	6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(uxtab,	6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
+ TCE(uxtb16,	6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
+ TCE(sel,	6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
+ TCE(smlad,	7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smladx,	7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smlald,	7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
+ TCE(smlaldx,	7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
+ TCE(smlsd,	7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smlsdx,	7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smlsld,	7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
+ TCE(smlsldx,	7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
+ TCE(smmla,	7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smmlar,	7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smmls,	75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smmlsr,	75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
+ TCE(smmul,	750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TCE(smmulr,	750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TCE(smuad,	700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TCE(smuadx,	700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TCE(smusd,	700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TCE(smusdx,	700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
+ TUF(srsia,	8cd0500, e980c000, 1, (I31w),			   srs,  srs),
+  UF(srsib,	9cd0500,           1, (I31w),			   srs),
+  UF(srsda,	84d0500,	   1, (I31w),			   srs),
+ TUF(srsdb,	94d0500, e800c000, 1, (I31w),			   srs,  srs),
+ TCE(ssat16,	6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),	   ssat16, t_ssat16),
+ TCE(strex,	1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR),	   strex,  t_strex),
+ TCE(umaal,	0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
+ TCE(usad8,	780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),	   smul,   t_simd),
+ TCE(usada8,	7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
+ TCE(usat16,	6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc),	   usat16, t_usat16),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v6k
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6k
+ tCE(yield,	320f001, yield,    0, (), noargs, t_hint),
+ tCE(wfe,	320f002, wfe,      0, (), noargs, t_hint),
+ tCE(wfi,	320f003, wfi,      0, (), noargs, t_hint),
+ tCE(sev,	320f004, sev,      0, (), noargs, t_hint),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6_notm
+ TCE(ldrexd,	1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb),        ldrexd, t_ldrexd),
+ TCE(strexd,	1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
+
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v6t2
+ TCE(ldrexb,	1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb),	              rd_rn,  rd_rn),
+ TCE(ldrexh,	1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb),	              rd_rn,  rd_rn),
+ TCE(strexb,	1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR),           strex,  rm_rd_rn),
+ TCE(strexh,	1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR),           strex,  rm_rd_rn),
+ TUF(clrex,	57ff01f, f3bf8f2f, 0, (),			      noargs, noargs),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v6z
+ TCE(smc,	1600070, f7f08000, 1, (EXPi), smc, t_smc),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v6t2
+ TCE(bfc,	7c0001f, f36f0000, 3, (RRnpc, I31, I32),	   bfc, t_bfc),
+ TCE(bfi,	7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
+ TCE(sbfx,	7a00050, f3400000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
+ TCE(ubfx,	7e00050, f3c00000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
+
+ TCE(mls,	0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
+ TCE(movw,	3000000, f2400000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
+ TCE(movt,	3400000, f2c00000, 2, (RRnpc, Iffff),		    mov16, t_mov16),
+ TCE(rbit,	3ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
+
+ TC3(ldrht,	03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
+ TC3(ldrsht,	03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
+ TC3(ldrsbt,	03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
+ TC3(strht,	02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
+
+  UT(cbnz,      b900,    2, (RR, EXP), t_czb),
+  UT(cbz,       b100,    2, (RR, EXP), t_czb),
+ /* ARM does not really have an IT instruction.  */
+ TUE(it,        0, bf08, 1, (COND),    it, t_it),
+ TUE(itt,       0, bf0c, 1, (COND),    it, t_it),
+ TUE(ite,       0, bf04, 1, (COND),    it, t_it),
+ TUE(ittt,      0, bf0e, 1, (COND),    it, t_it),
+ TUE(itet,      0, bf06, 1, (COND),    it, t_it),
+ TUE(itte,      0, bf0a, 1, (COND),    it, t_it),
+ TUE(itee,      0, bf02, 1, (COND),    it, t_it),
+ TUE(itttt,     0, bf0f, 1, (COND),    it, t_it),
+ TUE(itett,     0, bf07, 1, (COND),    it, t_it),
+ TUE(ittet,     0, bf0b, 1, (COND),    it, t_it),
+ TUE(iteet,     0, bf03, 1, (COND),    it, t_it),
+ TUE(ittte,     0, bf0d, 1, (COND),    it, t_it),
+ TUE(itete,     0, bf05, 1, (COND),    it, t_it),
+ TUE(ittee,     0, bf09, 1, (COND),    it, t_it),
+ TUE(iteee,     0, bf01, 1, (COND),    it, t_it),
+
+ /* Thumb2 only instructions.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT NULL
+
+ TCE(addw,	0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
+ TCE(subw,	0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
+ TCE(tbb,       0, e8d0f000, 1, (TB), 0, t_tb),
+ TCE(tbh,       0, e8d0f010, 1, (TB), 0, t_tb),
+
+ /* Thumb-2 hardware division instructions (R and M profiles only).  */
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_div
+ TCE(sdiv,	0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
+ TCE(udiv,	0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
+
+ /* ARM V7 instructions.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_ext_v7
+#undef THUMB_VARIANT
+#define THUMB_VARIANT &arm_ext_v7
+ TUF(pli,	450f000, f910f000, 1, (ADDR),	  pli,	    t_pld),
+ TCE(dbg,	320f0f0, f3af80f0, 1, (I15),	  dbg,	    t_dbg),
+ TUF(dmb,	57ff050, f3bf8f50, 1, (oBARRIER), barrier,  t_barrier),
+ TUF(dsb,	57ff040, f3bf8f40, 1, (oBARRIER), barrier,  t_barrier),
+ TUF(isb,	57ff060, f3bf8f60, 1, (oBARRIER), barrier,  t_barrier),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
+ cCE(wfs,	e200110, 1, (RR),	     rd),
+ cCE(rfs,	e300110, 1, (RR),	     rd),
+ cCE(wfc,	e400110, 1, (RR),	     rd),
+ cCE(rfc,	e500110, 1, (RR),	     rd),
+
+ cCL(ldfs,	c100100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(ldfd,	c108100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(ldfe,	c500100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(ldfp,	c508100, 2, (RF, ADDR),	     rd_cpaddr),
+
+ cCL(stfs,	c000100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(stfd,	c008100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(stfe,	c400100, 2, (RF, ADDR),	     rd_cpaddr),
+ cCL(stfp,	c408100, 2, (RF, ADDR),	     rd_cpaddr),
+
+ cCL(mvfs,	e008100, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfsp,	e008120, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfsm,	e008140, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfsz,	e008160, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfd,	e008180, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfdp,	e0081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfdm,	e0081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfdz,	e0081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfe,	e088100, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfep,	e088120, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfem,	e088140, 2, (RF, RF_IF),     rd_rm),
+ cCL(mvfez,	e088160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(mnfs,	e108100, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfsp,	e108120, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfsm,	e108140, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfsz,	e108160, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfd,	e108180, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfdp,	e1081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfdm,	e1081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfdz,	e1081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfe,	e188100, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfep,	e188120, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfem,	e188140, 2, (RF, RF_IF),     rd_rm),
+ cCL(mnfez,	e188160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(abss,	e208100, 2, (RF, RF_IF),     rd_rm),
+ cCL(abssp,	e208120, 2, (RF, RF_IF),     rd_rm),
+ cCL(abssm,	e208140, 2, (RF, RF_IF),     rd_rm),
+ cCL(abssz,	e208160, 2, (RF, RF_IF),     rd_rm),
+ cCL(absd,	e208180, 2, (RF, RF_IF),     rd_rm),
+ cCL(absdp,	e2081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(absdm,	e2081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(absdz,	e2081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(abse,	e288100, 2, (RF, RF_IF),     rd_rm),
+ cCL(absep,	e288120, 2, (RF, RF_IF),     rd_rm),
+ cCL(absem,	e288140, 2, (RF, RF_IF),     rd_rm),
+ cCL(absez,	e288160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(rnds,	e308100, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndsp,	e308120, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndsm,	e308140, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndsz,	e308160, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndd,	e308180, 2, (RF, RF_IF),     rd_rm),
+ cCL(rnddp,	e3081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(rnddm,	e3081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(rnddz,	e3081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(rnde,	e388100, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndep,	e388120, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndem,	e388140, 2, (RF, RF_IF),     rd_rm),
+ cCL(rndez,	e388160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(sqts,	e408100, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtsp,	e408120, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtsm,	e408140, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtsz,	e408160, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtd,	e408180, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtdp,	e4081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtdm,	e4081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtdz,	e4081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqte,	e488100, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtep,	e488120, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtem,	e488140, 2, (RF, RF_IF),     rd_rm),
+ cCL(sqtez,	e488160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(logs,	e508100, 2, (RF, RF_IF),     rd_rm),
+ cCL(logsp,	e508120, 2, (RF, RF_IF),     rd_rm),
+ cCL(logsm,	e508140, 2, (RF, RF_IF),     rd_rm),
+ cCL(logsz,	e508160, 2, (RF, RF_IF),     rd_rm),
+ cCL(logd,	e508180, 2, (RF, RF_IF),     rd_rm),
+ cCL(logdp,	e5081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(logdm,	e5081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(logdz,	e5081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(loge,	e588100, 2, (RF, RF_IF),     rd_rm),
+ cCL(logep,	e588120, 2, (RF, RF_IF),     rd_rm),
+ cCL(logem,	e588140, 2, (RF, RF_IF),     rd_rm),
+ cCL(logez,	e588160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(lgns,	e608100, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnsp,	e608120, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnsm,	e608140, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnsz,	e608160, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnd,	e608180, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgndp,	e6081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgndm,	e6081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgndz,	e6081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgne,	e688100, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnep,	e688120, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnem,	e688140, 2, (RF, RF_IF),     rd_rm),
+ cCL(lgnez,	e688160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(exps,	e708100, 2, (RF, RF_IF),     rd_rm),
+ cCL(expsp,	e708120, 2, (RF, RF_IF),     rd_rm),
+ cCL(expsm,	e708140, 2, (RF, RF_IF),     rd_rm),
+ cCL(expsz,	e708160, 2, (RF, RF_IF),     rd_rm),
+ cCL(expd,	e708180, 2, (RF, RF_IF),     rd_rm),
+ cCL(expdp,	e7081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(expdm,	e7081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(expdz,	e7081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(expe,	e788100, 2, (RF, RF_IF),     rd_rm),
+ cCL(expep,	e788120, 2, (RF, RF_IF),     rd_rm),
+ cCL(expem,	e788140, 2, (RF, RF_IF),     rd_rm),
+ cCL(expdz,	e788160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(sins,	e808100, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinsp,	e808120, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinsm,	e808140, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinsz,	e808160, 2, (RF, RF_IF),     rd_rm),
+ cCL(sind,	e808180, 2, (RF, RF_IF),     rd_rm),
+ cCL(sindp,	e8081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sindm,	e8081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sindz,	e8081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(sine,	e888100, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinep,	e888120, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinem,	e888140, 2, (RF, RF_IF),     rd_rm),
+ cCL(sinez,	e888160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(coss,	e908100, 2, (RF, RF_IF),     rd_rm),
+ cCL(cossp,	e908120, 2, (RF, RF_IF),     rd_rm),
+ cCL(cossm,	e908140, 2, (RF, RF_IF),     rd_rm),
+ cCL(cossz,	e908160, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosd,	e908180, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosdp,	e9081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosdm,	e9081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosdz,	e9081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(cose,	e988100, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosep,	e988120, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosem,	e988140, 2, (RF, RF_IF),     rd_rm),
+ cCL(cosez,	e988160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(tans,	ea08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(tansp,	ea08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(tansm,	ea08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(tansz,	ea08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(tand,	ea08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(tandp,	ea081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(tandm,	ea081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(tandz,	ea081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(tane,	ea88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(tanep,	ea88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(tanem,	ea88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(tanez,	ea88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(asns,	eb08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnsp,	eb08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnsm,	eb08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnsz,	eb08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnd,	eb08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(asndp,	eb081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(asndm,	eb081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(asndz,	eb081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(asne,	eb88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnep,	eb88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnem,	eb88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(asnez,	eb88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(acss,	ec08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(acssp,	ec08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(acssm,	ec08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(acssz,	ec08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsd,	ec08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsdp,	ec081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsdm,	ec081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsdz,	ec081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(acse,	ec88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsep,	ec88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsem,	ec88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(acsez,	ec88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(atns,	ed08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnsp,	ed08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnsm,	ed08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnsz,	ed08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnd,	ed08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(atndp,	ed081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(atndm,	ed081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(atndz,	ed081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(atne,	ed88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnep,	ed88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnem,	ed88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(atnez,	ed88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(urds,	ee08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdsp,	ee08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdsm,	ee08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdsz,	ee08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdd,	ee08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(urddp,	ee081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(urddm,	ee081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(urddz,	ee081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(urde,	ee88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdep,	ee88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdem,	ee88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(urdez,	ee88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(nrms,	ef08100, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmsp,	ef08120, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmsm,	ef08140, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmsz,	ef08160, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmd,	ef08180, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmdp,	ef081a0, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmdm,	ef081c0, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmdz,	ef081e0, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrme,	ef88100, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmep,	ef88120, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmem,	ef88140, 2, (RF, RF_IF),     rd_rm),
+ cCL(nrmez,	ef88160, 2, (RF, RF_IF),     rd_rm),
+
+ cCL(adfs,	e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfsp,	e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfsm,	e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfsz,	e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfd,	e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfdp,	e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfdm,	e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfdz,	e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfe,	e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfep,	e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfem,	e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(adfez,	e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(sufs,	e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufsp,	e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufsm,	e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufsz,	e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufd,	e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufdp,	e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufdm,	e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufdz,	e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufe,	e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufep,	e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufem,	e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(sufez,	e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(rsfs,	e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfsp,	e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfsm,	e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfsz,	e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfd,	e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfdp,	e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfdm,	e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfdz,	e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfe,	e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfep,	e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfem,	e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rsfez,	e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(mufs,	e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufsp,	e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufsm,	e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufsz,	e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufd,	e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufdp,	e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufdm,	e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufdz,	e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufe,	e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufep,	e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufem,	e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(mufez,	e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(dvfs,	e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfsp,	e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfsm,	e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfsz,	e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfd,	e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfdp,	e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfdm,	e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfdz,	e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfe,	e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfep,	e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfem,	e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(dvfez,	e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(rdfs,	e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfsp,	e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfsm,	e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfsz,	e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfd,	e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfdp,	e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfdm,	e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfdz,	e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfe,	e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfep,	e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfem,	e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rdfez,	e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(pows,	e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powsp,	e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powsm,	e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powsz,	e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powd,	e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powdp,	e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powdm,	e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powdz,	e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powe,	e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powep,	e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powem,	e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(powez,	e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(rpws,	e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwsp,	e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwsm,	e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwsz,	e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwd,	e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwdp,	e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwdm,	e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwdz,	e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwe,	e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwep,	e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwem,	e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rpwez,	e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(rmfs,	e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfsp,	e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfsm,	e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfsz,	e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfd,	e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfdp,	e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfdm,	e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfdz,	e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfe,	e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfep,	e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfem,	e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(rmfez,	e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(fmls,	e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlsp,	e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlsm,	e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlsz,	e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmld,	e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmldp,	e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmldm,	e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmldz,	e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmle,	e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlep,	e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlem,	e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fmlez,	e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(fdvs,	ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvsp,	ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvsm,	ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvsz,	ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvd,	ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvdp,	ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvdm,	ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvdz,	ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdve,	ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvep,	ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvem,	ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(fdvez,	ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(frds,	eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdsp,	eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdsm,	eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdsz,	eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdd,	eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frddp,	eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frddm,	eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frddz,	eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frde,	eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdep,	eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdem,	eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(frdez,	eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCL(pols,	ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polsp,	ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polsm,	ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polsz,	ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(pold,	ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(poldp,	ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(poldm,	ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(poldz,	ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(pole,	ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polep,	ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polem,	ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
+ cCL(polez,	ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
+
+ cCE(cmf,	e90f110, 2, (RF, RF_IF),     fpa_cmp),
+ C3E(cmfe,	ed0f110, 2, (RF, RF_IF),     fpa_cmp),
+ cCE(cnf,	eb0f110, 2, (RF, RF_IF),     fpa_cmp),
+ C3E(cnfe,	ef0f110, 2, (RF, RF_IF),     fpa_cmp),
+
+ cCL(flts,	e000110, 2, (RF, RR),	     rn_rd),
+ cCL(fltsp,	e000130, 2, (RF, RR),	     rn_rd),
+ cCL(fltsm,	e000150, 2, (RF, RR),	     rn_rd),
+ cCL(fltsz,	e000170, 2, (RF, RR),	     rn_rd),
+ cCL(fltd,	e000190, 2, (RF, RR),	     rn_rd),
+ cCL(fltdp,	e0001b0, 2, (RF, RR),	     rn_rd),
+ cCL(fltdm,	e0001d0, 2, (RF, RR),	     rn_rd),
+ cCL(fltdz,	e0001f0, 2, (RF, RR),	     rn_rd),
+ cCL(flte,	e080110, 2, (RF, RR),	     rn_rd),
+ cCL(fltep,	e080130, 2, (RF, RR),	     rn_rd),
+ cCL(fltem,	e080150, 2, (RF, RR),	     rn_rd),
+ cCL(fltez,	e080170, 2, (RF, RR),	     rn_rd),
 
-static void
-do_mav_triple_5b (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVD, REG_TYPE_MVD);
-}
+  /* The implementation of the FIX instruction is broken on some
+     assemblers, in that it accepts a precision specifier as well as a
+     rounding specifier, despite the fact that this is meaningless.
+     To be more compatible, we accept it as well, though of course it
+     does not set any bits.  */
+ cCE(fix,	e100110, 2, (RR, RF),	     rd_rm),
+ cCL(fixp,	e100130, 2, (RR, RF),	     rd_rm),
+ cCL(fixm,	e100150, 2, (RR, RF),	     rd_rm),
+ cCL(fixz,	e100170, 2, (RR, RF),	     rd_rm),
+ cCL(fixsp,	e100130, 2, (RR, RF),	     rd_rm),
+ cCL(fixsm,	e100150, 2, (RR, RF),	     rd_rm),
+ cCL(fixsz,	e100170, 2, (RR, RF),	     rd_rm),
+ cCL(fixdp,	e100130, 2, (RR, RF),	     rd_rm),
+ cCL(fixdm,	e100150, 2, (RR, RF),	     rd_rm),
+ cCL(fixdz,	e100170, 2, (RR, RF),	     rd_rm),
+ cCL(fixep,	e100130, 2, (RR, RF),	     rd_rm),
+ cCL(fixem,	e100150, 2, (RR, RF),	     rd_rm),
+ cCL(fixez,	e100170, 2, (RR, RF),	     rd_rm),
 
-static void
-do_mav_triple_5c (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVFX, REG_TYPE_MVFX);
-}
+  /* Instructions that were new with the real FPA, call them V2.  */
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_fpa_ext_v2
+ cCE(lfm,	c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCL(lfmfd,	c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCL(lfmea,	d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCE(sfm,	c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCL(sfmfd,	d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+ cCL(sfmea,	c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v1xd  /* VFP V1xD (single precision).  */
+  /* Moves and type conversions.  */
+ cCE(fcpys,	eb00a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fmrs,	e100a10, 2, (RR, RVS),	      vfp_reg_from_sp),
+ cCE(fmsr,	e000a10, 2, (RVS, RR),	      vfp_sp_from_reg),
+ cCE(fmstat,	ef1fa10, 0, (),		      noargs),
+ cCE(fsitos,	eb80ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fuitos,	eb80a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(ftosis,	ebd0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(ftosizs,	ebd0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(ftouis,	ebc0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(ftouizs,	ebc0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fmrx,	ef00a10, 2, (RR, RVC),	      rd_rn),
+ cCE(fmxr,	ee00a10, 2, (RVC, RR),	      rn_rd),
+
+  /* Memory operations.	 */
+ cCE(flds,	d100a00, 2, (RVS, ADDR),      vfp_sp_ldst),
+ cCE(fsts,	d000a00, 2, (RVS, ADDR),      vfp_sp_ldst),
+ cCE(fldmias,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
+ cCE(fldmfds,	c900a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
+ cCE(fldmdbs,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
+ cCE(fldmeas,	d300a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
+ cCE(fldmiax,	c900b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
+ cCE(fldmfdx,	c900b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
+ cCE(fldmdbx,	d300b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
+ cCE(fldmeax,	d300b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
+ cCE(fstmias,	c800a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
+ cCE(fstmeas,	c800a00, 2, (RRw, VRSLST),    vfp_sp_ldstmia),
+ cCE(fstmdbs,	d200a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
+ cCE(fstmfds,	d200a00, 2, (RRw, VRSLST),    vfp_sp_ldstmdb),
+ cCE(fstmiax,	c800b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
+ cCE(fstmeax,	c800b00, 2, (RRw, VRDLST),    vfp_xp_ldstmia),
+ cCE(fstmdbx,	d200b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
+ cCE(fstmfdx,	d200b00, 2, (RRw, VRDLST),    vfp_xp_ldstmdb),
 
-static void
-do_mav_triple_5d (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_RN, REG_TYPE_MVDX, REG_TYPE_MVDX);
-}
+  /* Monadic operations.  */
+ cCE(fabss,	eb00ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fnegs,	eb10a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fsqrts,	eb10ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+
+  /* Dyadic operations.	 */
+ cCE(fadds,	e300a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fsubs,	e300a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fmuls,	e200a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fdivs,	e800a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fmacs,	e000a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fmscs,	e100a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fnmuls,	e200a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fnmacs,	e000a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
+ cCE(fnmscs,	e100a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
 
-static void
-do_mav_triple_5e (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_MVF, REG_TYPE_MVF, REG_TYPE_MVF);
-}
+  /* Comparisons.  */
+ cCE(fcmps,	eb40a40, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fcmpzs,	eb50a40, 1, (RVS),	      vfp_sp_compare_z),
+ cCE(fcmpes,	eb40ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
+ cCE(fcmpezs,	eb50ac0, 1, (RVS),	      vfp_sp_compare_z),
 
-static void
-do_mav_triple_5f (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_MVD, REG_TYPE_MVD, REG_TYPE_MVD);
-}
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision).  */
+  /* Moves and type conversions.  */
+ cCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      rd_rm),
+ cCE(fcvtds,	eb70ac0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
+ cCE(fcvtsd,	eb70bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
+ cCE(fmdhr,	e200b10, 2, (RVD, RR),	      rn_rd),
+ cCE(fmdlr,	e000b10, 2, (RVD, RR),	      rn_rd),
+ cCE(fmrdh,	e300b10, 2, (RR, RVD),	      rd_rn),
+ cCE(fmrdl,	e100b10, 2, (RR, RVD),	      rd_rn),
+ cCE(fsitod,	eb80bc0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
+ cCE(fuitod,	eb80b40, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
+ cCE(ftosid,	ebd0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
+ cCE(ftosizd,	ebd0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
+ cCE(ftouid,	ebc0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
+ cCE(ftouizd,	ebc0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
+
+  /* Memory operations.	 */
+ cCE(fldd,	d100b00, 2, (RVD, ADDR),      vfp_dp_ldst),
+ cCE(fstd,	d000b00, 2, (RVD, ADDR),      vfp_dp_ldst),
+ cCE(fldmiad,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
+ cCE(fldmfdd,	c900b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
+ cCE(fldmdbd,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
+ cCE(fldmead,	d300b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
+ cCE(fstmiad,	c800b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
+ cCE(fstmead,	c800b00, 2, (RRw, VRDLST),    vfp_dp_ldstmia),
+ cCE(fstmdbd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
+ cCE(fstmfdd,	d200b00, 2, (RRw, VRDLST),    vfp_dp_ldstmdb),
 
-static void
-do_mav_triple_5g (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_MVFX, REG_TYPE_MVFX, REG_TYPE_MVFX);
-}
+  /* Monadic operations.  */
+ cCE(fabsd,	eb00bc0, 2, (RVD, RVD),	      rd_rm),
+ cCE(fnegd,	eb10b40, 2, (RVD, RVD),	      rd_rm),
+ cCE(fsqrtd,	eb10bc0, 2, (RVD, RVD),	      rd_rm),
+
+  /* Dyadic operations.	 */
+ cCE(faddd,	e300b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fsubd,	e300b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fmuld,	e200b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fdivd,	e800b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fmacd,	e000b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fmscd,	e100b00, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fnmuld,	e200b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fnmacd,	e000b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
+ cCE(fnmscd,	e100b40, 3, (RVD, RVD, RVD),  rd_rn_rm),
 
-static void
-do_mav_triple_5h (str)
-     char * str;
-{
-  do_mav_triple (str, MAV_MODE5, REG_TYPE_MVDX, REG_TYPE_MVDX, REG_TYPE_MVDX);
-}
+  /* Comparisons.  */
+ cCE(fcmpd,	eb40b40, 2, (RVD, RVD),	      rd_rm),
+ cCE(fcmpzd,	eb50b40, 1, (RVD),	      rd),
+ cCE(fcmped,	eb40bc0, 2, (RVD, RVD),	      rd_rm),
+ cCE(fcmpezd,	eb50bc0, 1, (RVD),	      rd),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &fpu_vfp_ext_v2
+ cCE(fmsrr,	c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
+ cCE(fmrrs,	c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
+ cCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    rm_rd_rn),
+ cCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    rd_rn_rm),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions.	 */
+ cCE(mia,	e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miaph,	e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miabb,	e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miabt,	e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miatb,	e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(miatt,	e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
+ cCE(mar,	c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
+ cCE(mra,	c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology.  */
+ cCE(tandcb,	e13f130, 1, (RR),		    iwmmxt_tandorc),
+ cCE(tandch,	e53f130, 1, (RR),		    iwmmxt_tandorc),
+ cCE(tandcw,	e93f130, 1, (RR),		    iwmmxt_tandorc),
+ cCE(tbcstb,	e400010, 2, (RIWR, RR),		    rn_rd),
+ cCE(tbcsth,	e400050, 2, (RIWR, RR),		    rn_rd),
+ cCE(tbcstw,	e400090, 2, (RIWR, RR),		    rn_rd),
+ cCE(textrcb,	e130170, 2, (RR, I7),		    iwmmxt_textrc),
+ cCE(textrch,	e530170, 2, (RR, I7),		    iwmmxt_textrc),
+ cCE(textrcw,	e930170, 2, (RR, I7),		    iwmmxt_textrc),
+ cCE(textrmub,	e100070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(textrmuh,	e500070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(textrmuw,	e900070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(textrmsb,	e100078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(textrmsh,	e500078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(textrmsw,	e900078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
+ cCE(tinsrb,	e600010, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
+ cCE(tinsrh,	e600050, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
+ cCE(tinsrw,	e600090, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
+ cCE(tmcr,	e000110, 2, (RIWC, RR),		    rn_rd),
+ cCE(tmcrr,	c400000, 3, (RIWR, RR, RR),	    rm_rd_rn),
+ cCE(tmia,	e200010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmiaph,	e280010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmiabb,	e2c0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmiabt,	e2d0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmiatb,	e2e0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmiatt,	e2f0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
+ cCE(tmovmskb,	e100030, 2, (RR, RIWR),		    rd_rn),
+ cCE(tmovmskh,	e500030, 2, (RR, RIWR),		    rd_rn),
+ cCE(tmovmskw,	e900030, 2, (RR, RIWR),		    rd_rn),
+ cCE(tmrc,	e100110, 2, (RR, RIWC),		    rd_rn),
+ cCE(tmrrc,	c500000, 3, (RR, RR, RIWR),	    rd_rn_rm),
+ cCE(torcb,	e13f150, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torch,	e53f150, 1, (RR),		    iwmmxt_tandorc),
+ cCE(torcw,	e93f150, 1, (RR),		    iwmmxt_tandorc),
+ cCE(waccb,	e0001c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wacch,	e4001c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(waccw,	e8001c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(waddbss,	e300180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddb,	e000180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddbus,	e100180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddhss,	e700180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddh,	e400180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddhus,	e500180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddwss,	eb00180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddw,	e800180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waddwus,	e900180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(waligni,	e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
+ cCE(walignr0,	e800020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(walignr1,	e900020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(walignr2,	ea00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(walignr3,	eb00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wand,	e200000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wandn,	e300000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wavg2b,	e800000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wavg2br,	e900000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wavg2h,	ec00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wavg2hr,	ed00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpeqb,	e000060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpeqh,	e400060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpeqw,	e800060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtub,	e100060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtuh,	e500060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtuw,	e900060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtsb,	e300060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtsh,	e700060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wcmpgtsw,	eb00060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wldrb,	c100000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
+ cCE(wldrh,	c500000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
+ cCE(wldrw,	c100100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
+ cCE(wldrd,	c500100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
+ cCE(wmacs,	e600100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmacsz,	e700100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmacu,	e400100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmacuz,	e500100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmadds,	ea00100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaddu,	e800100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxsb,	e200160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxsh,	e600160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxsw,	ea00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxub,	e000160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxuh,	e400160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmaxuw,	e800160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminsb,	e300160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminsh,	e700160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminsw,	eb00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminub,	e100160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminuh,	e500160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wminuw,	e900160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmov,	e000000, 2, (RIWR, RIWR),	    iwmmxt_wmov),
+ cCE(wmulsm,	e300100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmulsl,	e200100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmulum,	e100100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wmulul,	e000100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wor,	e000000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackhss,	e700080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackhus,	e500080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackwss,	eb00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackwus,	e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackdss,	ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wpackdus,	ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorh,	e700040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorhg,	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wrorw,	eb00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrorwg,	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wrord,	ef00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wrordg,	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsadb,	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsadbz,	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsadh,	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsadhz,	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wshufh,	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
+ cCE(wsllh,	e500040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllhg,	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsllw,	e900040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsllwg,	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wslld,	ed00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wslldg,	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsrah,	e400040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrahg,	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsraw,	e800040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrawg,	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsrad,	ec00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsradg,	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsrlh,	e600040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlhg,	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsrlw,	ea00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrlwg,	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wsrld,	ee00040, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsrldg,	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
+ cCE(wstrb,	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
+ cCE(wstrh,	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
+ cCE(wstrw,	c000100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
+ cCE(wstrd,	c400100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
+ cCE(wsubbss,	e3001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubb,	e0001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubbus,	e1001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubhss,	e7001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubh,	e4001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubhus,	e5001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubwss,	eb001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubw,	e8001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wsubwus,	e9001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR),	    rd_rn),
+ cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wxor,	e100000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
+ cCE(wzero,	e300000, 1, (RIWR),		    iwmmxt_wzero),
+
+#undef ARM_VARIANT
+#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions.	*/
+ cCE(cfldrs,	c100400, 2, (RMF, ADDR),	      rd_cpaddr),
+ cCE(cfldrd,	c500400, 2, (RMD, ADDR),	      rd_cpaddr),
+ cCE(cfldr32,	c100500, 2, (RMFX, ADDR),	      rd_cpaddr),
+ cCE(cfldr64,	c500500, 2, (RMDX, ADDR),	      rd_cpaddr),
+ cCE(cfstrs,	c000400, 2, (RMF, ADDR),	      rd_cpaddr),
+ cCE(cfstrd,	c400400, 2, (RMD, ADDR),	      rd_cpaddr),
+ cCE(cfstr32,	c000500, 2, (RMFX, ADDR),	      rd_cpaddr),
+ cCE(cfstr64,	c400500, 2, (RMDX, ADDR),	      rd_cpaddr),
+ cCE(cfmvsr,	e000450, 2, (RMF, RR),		      rn_rd),
+ cCE(cfmvrs,	e100450, 2, (RR, RMF),		      rd_rn),
+ cCE(cfmvdlr,	e000410, 2, (RMD, RR),		      rn_rd),
+ cCE(cfmvrdl,	e100410, 2, (RR, RMD),		      rd_rn),
+ cCE(cfmvdhr,	e000430, 2, (RMD, RR),		      rn_rd),
+ cCE(cfmvrdh,	e100430, 2, (RR, RMD),		      rd_rn),
+ cCE(cfmv64lr,	e000510, 2, (RMDX, RR),		      rn_rd),
+ cCE(cfmvr64l,	e100510, 2, (RR, RMDX),		      rd_rn),
+ cCE(cfmv64hr,	e000530, 2, (RMDX, RR),		      rn_rd),
+ cCE(cfmvr64h,	e100530, 2, (RR, RMDX),		      rd_rn),
+ cCE(cfmval32,	e200440, 2, (RMAX, RMFX),	      rd_rn),
+ cCE(cfmv32al,	e100440, 2, (RMFX, RMAX),	      rd_rn),
+ cCE(cfmvam32,	e200460, 2, (RMAX, RMFX),	      rd_rn),
+ cCE(cfmv32am,	e100460, 2, (RMFX, RMAX),	      rd_rn),
+ cCE(cfmvah32,	e200480, 2, (RMAX, RMFX),	      rd_rn),
+ cCE(cfmv32ah,	e100480, 2, (RMFX, RMAX),	      rd_rn),
+ cCE(cfmva32,	e2004a0, 2, (RMAX, RMFX),	      rd_rn),
+ cCE(cfmv32a,	e1004a0, 2, (RMFX, RMAX),	      rd_rn),
+ cCE(cfmva64,	e2004c0, 2, (RMAX, RMDX),	      rd_rn),
+ cCE(cfmv64a,	e1004c0, 2, (RMDX, RMAX),	      rd_rn),
+ cCE(cfmvsc32,	e2004e0, 2, (RMDS, RMDX),	      mav_dspsc),
+ cCE(cfmv32sc,	e1004e0, 2, (RMDX, RMDS),	      rd),
+ cCE(cfcpys,	e000400, 2, (RMF, RMF),		      rd_rn),
+ cCE(cfcpyd,	e000420, 2, (RMD, RMD),		      rd_rn),
+ cCE(cfcvtsd,	e000460, 2, (RMD, RMF),		      rd_rn),
+ cCE(cfcvtds,	e000440, 2, (RMF, RMD),		      rd_rn),
+ cCE(cfcvt32s,	e000480, 2, (RMF, RMFX),	      rd_rn),
+ cCE(cfcvt32d,	e0004a0, 2, (RMD, RMFX),	      rd_rn),
+ cCE(cfcvt64s,	e0004c0, 2, (RMF, RMDX),	      rd_rn),
+ cCE(cfcvt64d,	e0004e0, 2, (RMD, RMDX),	      rd_rn),
+ cCE(cfcvts32,	e100580, 2, (RMFX, RMF),	      rd_rn),
+ cCE(cfcvtd32,	e1005a0, 2, (RMFX, RMD),	      rd_rn),
+ cCE(cftruncs32,e1005c0, 2, (RMFX, RMF),	      rd_rn),
+ cCE(cftruncd32,e1005e0, 2, (RMFX, RMD),	      rd_rn),
+ cCE(cfrshl32,	e000550, 3, (RMFX, RMFX, RR),	      mav_triple),
+ cCE(cfrshl64,	e000570, 3, (RMDX, RMDX, RR),	      mav_triple),
+ cCE(cfsh32,	e000500, 3, (RMFX, RMFX, I63s),	      mav_shift),
+ cCE(cfsh64,	e200500, 3, (RMDX, RMDX, I63s),	      mav_shift),
+ cCE(cfcmps,	e100490, 3, (RR, RMF, RMF),	      rd_rn_rm),
+ cCE(cfcmpd,	e1004b0, 3, (RR, RMD, RMD),	      rd_rn_rm),
+ cCE(cfcmp32,	e100590, 3, (RR, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfcmp64,	e1005b0, 3, (RR, RMDX, RMDX),	      rd_rn_rm),
+ cCE(cfabss,	e300400, 2, (RMF, RMF),		      rd_rn),
+ cCE(cfabsd,	e300420, 2, (RMD, RMD),		      rd_rn),
+ cCE(cfnegs,	e300440, 2, (RMF, RMF),		      rd_rn),
+ cCE(cfnegd,	e300460, 2, (RMD, RMD),		      rd_rn),
+ cCE(cfadds,	e300480, 3, (RMF, RMF, RMF),	      rd_rn_rm),
+ cCE(cfaddd,	e3004a0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
+ cCE(cfsubs,	e3004c0, 3, (RMF, RMF, RMF),	      rd_rn_rm),
+ cCE(cfsubd,	e3004e0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
+ cCE(cfmuls,	e100400, 3, (RMF, RMF, RMF),	      rd_rn_rm),
+ cCE(cfmuld,	e100420, 3, (RMD, RMD, RMD),	      rd_rn_rm),
+ cCE(cfabs32,	e300500, 2, (RMFX, RMFX),	      rd_rn),
+ cCE(cfabs64,	e300520, 2, (RMDX, RMDX),	      rd_rn),
+ cCE(cfneg32,	e300540, 2, (RMFX, RMFX),	      rd_rn),
+ cCE(cfneg64,	e300560, 2, (RMDX, RMDX),	      rd_rn),
+ cCE(cfadd32,	e300580, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfadd64,	e3005a0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
+ cCE(cfsub32,	e3005c0, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfsub64,	e3005e0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
+ cCE(cfmul32,	e100500, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfmul64,	e100520, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
+ cCE(cfmac32,	e100540, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfmsc32,	e100560, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
+ cCE(cfmadd32,	e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ cCE(cfmsub32,	e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
+ cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+ cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
+};
+#undef ARM_VARIANT
+#undef THUMB_VARIANT
+#undef TCE
+#undef TCM
+#undef TUE
+#undef TUF
+#undef TCC
+#undef cCE
+#undef cCL
+#undef C3E
+#undef CE
+#undef CM
+#undef UE
+#undef UF
+#undef UT
+#undef OPS0
+#undef OPS1
+#undef OPS2
+#undef OPS3
+#undef OPS4
+#undef OPS5
+#undef OPS6
+#undef do_0
+
+/* MD interface: bits in the object file.  */
 
-static void
-do_mav_quad_6a (str)
-     char * str;
-{
-  do_mav_quad (str, MAV_MODE6, REG_TYPE_MVAX, REG_TYPE_MVFX, REG_TYPE_MVFX,
-	     REG_TYPE_MVFX);
-}
+/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
+   for use in the a.out file, and stores them in the array pointed to by buf.
+   This knows about the endian-ness of the target machine and does
+   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
+   2 (short) and 4 (long)  Floating numbers are put out as a series of
+   LITTLENUMS (shorts, here at least).	*/
 
-static void
-do_mav_quad_6b (str)
-     char * str;
+void
+md_number_to_chars (char * buf, valueT val, int n)
 {
-  do_mav_quad (str, MAV_MODE6, REG_TYPE_MVAX, REG_TYPE_MVAX, REG_TYPE_MVFX,
-	     REG_TYPE_MVFX);
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
 }
 
-/* cfmvsc32<cond> DSPSC,MVDX[15:0].  */
-static void
-do_mav_dspsc_1 (str)
-     char * str;
+static valueT
+md_chars_to_number (char * buf, int n)
 {
-  skip_whitespace (str);
+  valueT result = 0;
+  unsigned char * where = (unsigned char *) buf;
 
-  /* cfmvsc32.  */
-  if (mav_reg_required_here (&str, -1, REG_TYPE_DSPSC) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, 12, REG_TYPE_MVDX) == FAIL)
+  if (target_big_endian)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-
-      return;
+      while (n--)
+	{
+	  result <<= 8;
+	  result |= (*where++ & 255);
+	}
     }
-
-  end_of_line (str);
-}
-
-/* cfmv32sc<cond> MVDX[15:0],DSPSC.  */
-static void
-do_mav_dspsc_2 (str)
-     char * str;
-{
-  skip_whitespace (str);
-
-  /* cfmv32sc.  */
-  if (mav_reg_required_here (&str, 12, REG_TYPE_MVDX) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, -1, REG_TYPE_DSPSC) == FAIL)
+  else
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-
-      return;
+      while (n--)
+	{
+	  result <<= 8;
+	  result |= (where[n] & 255);
+	}
     }
 
-  end_of_line (str);
-}
-
-static void
-do_mav_shift_1 (str)
-     char * str;
-{
-  do_mav_shift (str, REG_TYPE_MVFX, REG_TYPE_MVFX);
-}
-
-static void
-do_mav_shift_2 (str)
-     char * str;
-{
-  do_mav_shift (str, REG_TYPE_MVDX, REG_TYPE_MVDX);
-}
-
-static void
-do_mav_ldst_1 (str)
-     char * str;
-{
-  do_mav_ldst (str, REG_TYPE_MVF);
+  return result;
 }
 
-static void
-do_mav_ldst_2 (str)
-     char * str;
-{
-  do_mav_ldst (str, REG_TYPE_MVD);
-}
+/* MD interface: Sections.  */
 
-static void
-do_mav_ldst_3 (str)
-     char * str;
-{
-  do_mav_ldst (str, REG_TYPE_MVFX);
-}
+/* Estimate the size of a frag before relaxing.  Assume everything fits in
+   2 bytes.  */
 
-static void
-do_mav_ldst_4 (str)
-     char * str;
+int
+md_estimate_size_before_relax (fragS * fragp,
+			       segT    segtype ATTRIBUTE_UNUSED)
 {
-  do_mav_ldst (str, REG_TYPE_MVDX);
+  fragp->fr_var = 2;
+  return 2;
 }
 
-/* Isnsn like "foo X,Y".  */
+/* Convert a machine dependent frag.  */
 
-static void
-do_mav_binops (str, mode, reg0, reg1)
-     char * str;
-     int mode;
-     enum arm_reg_type reg0;
-     enum arm_reg_type reg1;
+void
+md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
 {
-  int shift0, shift1;
-
-  shift0 = mode & 0xff;
-  shift1 = (mode >> 8) & 0xff;
-
-  skip_whitespace (str);
+  unsigned long insn;
+  unsigned long old_op;
+  char *buf;
+  expressionS exp;
+  fixS *fixp;
+  int reloc_type;
+  int pc_rel;
+  int opcode;
+
+  buf = fragp->fr_literal + fragp->fr_fix;
+
+  old_op = bfd_get_16(abfd, buf);
+  if (fragp->fr_symbol) {
+      exp.X_op = O_symbol;
+      exp.X_add_symbol = fragp->fr_symbol;
+  } else {
+      exp.X_op = O_constant;
+  }
+  exp.X_add_number = fragp->fr_offset;
+  opcode = fragp->fr_subtype;
+  switch (opcode)
+    {
+    case T_MNEM_ldr_pc:
+    case T_MNEM_ldr_pc2:
+    case T_MNEM_ldr_sp:
+    case T_MNEM_str_sp:
+    case T_MNEM_ldr:
+    case T_MNEM_ldrb:
+    case T_MNEM_ldrh:
+    case T_MNEM_str:
+    case T_MNEM_strb:
+    case T_MNEM_strh:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
+	    {
+	      insn |= (old_op & 0x700) << 4;
+	    }
+	  else
+	    {
+	      insn |= (old_op & 7) << 12;
+	      insn |= (old_op & 0x38) << 13;
+	    }
+	  insn |= 0x00000c00;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
+	}
+      pc_rel = (opcode == T_MNEM_ldr_pc2);
+      break;
+    case T_MNEM_adr:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+	  exp.X_add_number -= 4;
+	}
+      pc_rel = 1;
+      break;
+    case T_MNEM_mov:
+    case T_MNEM_movs:
+    case T_MNEM_cmp:
+    case T_MNEM_cmn:
+      if (fragp->fr_var == 4)
+	{
+	  int r0off = (opcode == T_MNEM_mov
+		       || opcode == T_MNEM_movs) ? 0 : 8;
+	  insn = THUMB_OP32 (opcode);
+	  insn = (insn & 0xe1ffffff) | 0x10000000;
+	  insn |= (old_op & 0x700) << r0off;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_IMM;
+	}
+      pc_rel = 0;
+      break;
+    case T_MNEM_b:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
+	}
+      else
+	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
+      pc_rel = 1;
+      break;
+    case T_MNEM_bcond:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  insn |= (old_op & 0xf00) << 14;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
+	}
+      else
+	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
+      pc_rel = 1;
+      break;
+    case T_MNEM_add_sp:
+    case T_MNEM_add_pc:
+    case T_MNEM_inc_sp:
+    case T_MNEM_dec_sp:
+      if (fragp->fr_var == 4)
+	{
+	  /* ??? Choose between add and addw.  */
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+      pc_rel = 0;
+      break;
 
-  if (mav_reg_required_here (&str, shift0, reg0) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift1, reg1) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
+    case T_MNEM_addi:
+    case T_MNEM_addis:
+    case T_MNEM_subi:
+    case T_MNEM_subis:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  insn |= (old_op & 0xf) << 16;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+      pc_rel = 0;
+      break;
+    default:
+      abort();
     }
-  else
-    end_of_line (str);
+  fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
+		      reloc_type);
+  fixp->fx_file = fragp->fr_file;
+  fixp->fx_line = fragp->fr_line;
+  fragp->fr_fix += fragp->fr_var;
 }
 
-/* Isnsn like "foo X,Y,Z".  */
-
-static void
-do_mav_triple (str, mode, reg0, reg1, reg2)
-     char * str;
-     int mode;
-     enum arm_reg_type reg0;
-     enum arm_reg_type reg1;
-     enum arm_reg_type reg2;
+/* Return the size of a relaxable immediate operand instruction.
+   SHIFT and SIZE specify the form of the allowable immediate.  */
+static int
+relax_immediate (fragS *fragp, int size, int shift)
 {
-  int shift0, shift1, shift2;
+  offsetT offset;
+  offsetT mask;
+  offsetT low;
 
-  shift0 = mode & 0xff;
-  shift1 = (mode >> 8) & 0xff;
-  shift2 = (mode >> 16) & 0xff;
+  /* ??? Should be able to do better than this.  */
+  if (fragp->fr_symbol)
+    return 4;
 
-  skip_whitespace (str);
-
-  if (mav_reg_required_here (&str, shift0, reg0) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift1, reg1) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift2, reg2) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-    }
-  else
-    end_of_line (str);
+  low = (1 << shift) - 1;
+  mask = (1 << (shift + size)) - (1 << shift);
+  offset = fragp->fr_offset;
+  /* Force misaligned offsets to 32-bit variant.  */
+  if (offset & low)
+    return -4;
+  if (offset & ~mask)
+    return 4;
+  return 2;
 }
 
-/* Isnsn like "foo W,X,Y,Z".
-    where W=MVAX[0:3] and X,Y,Z=MVFX[0:15].  */
-
-static void
-do_mav_quad (str, mode, reg0, reg1, reg2, reg3)
-     char * str;
-     int mode;
-     enum arm_reg_type reg0;
-     enum arm_reg_type reg1;
-     enum arm_reg_type reg2;
-     enum arm_reg_type reg3;
+/* Return the size of a relaxable adr pseudo-instruction or PC-relative
+   load.  */
+static int
+relax_adr (fragS *fragp, asection *sec)
+{
+  addressT addr;
+  offsetT val;
+
+  /* Assume worst case for symbols not known to be in the same section.  */
+  if (!S_IS_DEFINED(fragp->fr_symbol)
+      || sec != S_GET_SEGMENT (fragp->fr_symbol))
+    return 4;
+
+  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  addr = fragp->fr_address + fragp->fr_fix;
+  addr = (addr + 4) & ~3;
+  /* Fix the insn as the 4-byte version if the target address is not
+     sufficiently aligned.  This is prevents an infinite loop when two
+     instructions have contradictory range/alignment requirements.  */
+  if (val & 3)
+    return -4;
+  val -= addr;
+  if (val < 0 || val > 1020)
+    return 4;
+  return 2;
+}
+
+/* Return the size of a relaxable add/sub immediate instruction.  */
+static int
+relax_addsub (fragS *fragp, asection *sec)
 {
-  int shift0, shift1, shift2, shift3;
+  char *buf;
+  int op;
 
-  shift0= mode & 0xff;
-  shift1 = (mode >> 8) & 0xff;
-  shift2 = (mode >> 16) & 0xff;
-  shift3 = (mode >> 24) & 0xff;
-
-  skip_whitespace (str);
-
-  if (mav_reg_required_here (&str, shift0, reg0) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift1, reg1) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift2, reg2) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, shift3, reg3) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-    }
+  buf = fragp->fr_literal + fragp->fr_fix;
+  op = bfd_get_16(sec->owner, buf);
+  if ((op & 0xf) == ((op >> 4) & 0xf))
+    return relax_immediate (fragp, 8, 0);
   else
-    end_of_line (str);
+    return relax_immediate (fragp, 3, 0);
 }
 
-/* Maverick shift immediate instructions.
-   cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
-   cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0].  */
-
-static void
-do_mav_shift (str, reg0, reg1)
-     char * str;
-     enum arm_reg_type reg0;
-     enum arm_reg_type reg1;
-{
-  int error;
-  int imm, neg = 0;
-
-  skip_whitespace (str);
-
-  error = 0;
-
-  if (mav_reg_required_here (&str, 12, reg0) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || mav_reg_required_here (&str, 16, reg1) == FAIL
-      || skip_past_comma  (&str) == FAIL)
-    {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  /* Calculate the immediate operand.
-     The operand is a 7bit signed number.  */
-  skip_whitespace (str);
-
-  if (*str == '#')
-    ++str;
-
-  if (!ISDIGIT (*str) && *str != '-')
-    {
-      inst.error = _("expecting immediate, 7bit operand");
-      return;
-    }
 
-  if (*str == '-')
-    {
-      neg = 1;
-      ++str;
-    }
+/* Return the size of a relaxable branch instruction.  BITS is the
+   size of the offset field in the narrow instruction.  */
 
-  for (imm = 0; *str && ISDIGIT (*str); ++str)
-    imm = imm * 10 + *str - '0';
+static int
+relax_branch (fragS *fragp, asection *sec, int bits)
+{
+  addressT addr;
+  offsetT val;
+  offsetT limit;
 
-  if (imm > 64)
-    {
-      inst.error = _("immediate out of range");
-      return;
-    }
+  /* Assume worst case for symbols not known to be in the same section.  */
+  if (!S_IS_DEFINED(fragp->fr_symbol)
+      || sec != S_GET_SEGMENT (fragp->fr_symbol))
+    return 4;
 
-  /* Make negative imm's into 7bit signed numbers.  */
-  if (neg)
-    {
-      imm = -imm;
-      imm &= 0x0000007f;
-    }
+  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  addr = fragp->fr_address + fragp->fr_fix + 4;
+  val -= addr;
 
-  /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
-     Bits 5-7 of the insn should have bits 4-6 of the immediate.
-     Bit 4 should be 0.  */
-  imm = (imm & 0xf) | ((imm & 0x70) << 1);
-
-  inst.instruction |= imm;
-  end_of_line (str);
+  /* Offset is a signed value *2 */
+  limit = 1 << bits;
+  if (val >= limit || val < -limit)
+    return 4;
+  return 2;
 }
 
-static int
-mav_parse_offset (str, negative)
-     char ** str;
-     int *negative;
-{
-  char * p = *str;
-  int offset;
-
-  *negative = 0;
-
-  skip_whitespace (p);
 
-  if (*p == '#')
-    ++p;
+/* Relax a machine dependent frag.  This returns the amount by which
+   the current size of the frag should change.  */
 
-  if (*p == '-')
-    {
-      *negative = 1;
-      ++p;
-    }
+int
+arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
+{
+  int oldsize;
+  int newsize;
 
-  if (!ISDIGIT (*p))
+  oldsize = fragp->fr_var;
+  switch (fragp->fr_subtype)
     {
-      inst.error = _("offset expected");
-      return 0;
+    case T_MNEM_ldr_pc2:
+      newsize = relax_adr(fragp, sec);
+      break;
+    case T_MNEM_ldr_pc:
+    case T_MNEM_ldr_sp:
+    case T_MNEM_str_sp:
+      newsize = relax_immediate(fragp, 8, 2);
+      break;
+    case T_MNEM_ldr:
+    case T_MNEM_str:
+      newsize = relax_immediate(fragp, 5, 2);
+      break;
+    case T_MNEM_ldrh:
+    case T_MNEM_strh:
+      newsize = relax_immediate(fragp, 5, 1);
+      break;
+    case T_MNEM_ldrb:
+    case T_MNEM_strb:
+      newsize = relax_immediate(fragp, 5, 0);
+      break;
+    case T_MNEM_adr:
+      newsize = relax_adr(fragp, sec);
+      break;
+    case T_MNEM_mov:
+    case T_MNEM_movs:
+    case T_MNEM_cmp:
+    case T_MNEM_cmn:
+      newsize = relax_immediate(fragp, 8, 0);
+      break;
+    case T_MNEM_b:
+      newsize = relax_branch(fragp, sec, 11);
+      break;
+    case T_MNEM_bcond:
+      newsize = relax_branch(fragp, sec, 8);
+      break;
+    case T_MNEM_add_sp:
+    case T_MNEM_add_pc:
+      newsize = relax_immediate (fragp, 8, 2);
+      break;
+    case T_MNEM_inc_sp:
+    case T_MNEM_dec_sp:
+      newsize = relax_immediate (fragp, 7, 2);
+      break;
+    case T_MNEM_addi:
+    case T_MNEM_addis:
+    case T_MNEM_subi:
+    case T_MNEM_subis:
+      newsize = relax_addsub (fragp, sec);
+      break;
+    default:
+      abort();
     }
-
-  for (offset = 0; *p && ISDIGIT (*p); ++p)
-    offset = offset * 10 + *p - '0';
-
-  if (offset > 0xff)
+  if (newsize < 0)
     {
-      inst.error = _("offset out of range");
-      return 0;
+      fragp->fr_var = -newsize;
+      md_convert_frag (sec->owner, sec, fragp);
+      frag_wane(fragp);
+      return -(newsize + oldsize);
     }
-
-  *str = p;
-
-  return *negative ? -offset : offset;
+  fragp->fr_var = newsize;
+  return newsize - oldsize;
 }
 
-/* Maverick load/store instructions.
-  <insn><cond> CRd,[Rn,<offset>]{!}.
-  <insn><cond> CRd,[Rn],<offset>.  */
+/* Round up a section size to the appropriate boundary.	 */
 
-static void
-do_mav_ldst (str, reg0)
-     char * str;
-     enum arm_reg_type reg0;
+valueT
+md_section_align (segT	 segment ATTRIBUTE_UNUSED,
+		  valueT size)
 {
-  int offset, negative;
+#ifdef OBJ_ELF
+  return size;
+#else
+  /* Round all sects to multiple of 4.	*/
+  return (size + 3) & ~3;
+#endif
+}
 
-  skip_whitespace (str);
+/* This is called from HANDLE_ALIGN in write.c.	 Fill in the contents
+   of an rs_align_code fragment.  */
 
-  if (mav_reg_required_here (&str, 12, reg0) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || *str++ != '['
-      || reg_required_here (&str, 16) == FAIL)
-    goto fail_ldst;
+void
+arm_handle_align (fragS * fragP)
+{
+  static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
+  static char const thumb_noop[2] = { 0xc0, 0x46 };
+  static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
+  static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
 
-  if (skip_past_comma (&str) == SUCCESS)
-    {
-      /* You are here: "<offset>]{!}".  */
-      inst.instruction |= PRE_INDEX;
+  int bytes, fix, noop_size;
+  char * p;
+  const char * noop;
 
-      offset = mav_parse_offset (&str, &negative);
+  if (fragP->fr_type != rs_align_code)
+    return;
 
-      if (inst.error)
-	return;
+  bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
+  p = fragP->fr_literal + fragP->fr_fix;
+  fix = 0;
 
-      if (*str++ != ']')
-	{
-	  inst.error = _("missing ]");
-	  return;
-	}
+  if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
+    bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
 
-      if (*str == '!')
-	{
-	  inst.instruction |= WRITE_BACK;
-	  ++str;
-	}
+  if (fragP->tc_frag_data)
+    {
+      if (target_big_endian)
+	noop = thumb_bigend_noop;
+      else
+	noop = thumb_noop;
+      noop_size = sizeof (thumb_noop);
     }
   else
     {
-      /* You are here: "], <offset>".  */
-      if (*str++ != ']')
-	{
-	  inst.error = _("missing ]");
-	  return;
-	}
-
-      if (skip_past_comma (&str) == FAIL
-	  || (offset = mav_parse_offset (&str, &negative), inst.error))
-	goto fail_ldst;
-
-      inst.instruction |= CP_T_WB; /* Post indexed, set bit W.  */
+      if (target_big_endian)
+	noop = arm_bigend_noop;
+      else
+	noop = arm_noop;
+      noop_size = sizeof (arm_noop);
     }
 
-  if (negative)
-    offset = -offset;
-  else
-    inst.instruction |= CP_T_UD; /* Positive, so set bit U.  */
-
-  inst.instruction |= offset >> 2;
-  end_of_line (str);
-  return;
-
-fail_ldst:
-  if (!inst.error)
-     inst.error = BAD_ARGS;
-}
-
-static void
-do_t_nop (str)
-     char * str;
-{
-  /* Do nothing.  */
-  end_of_line (str);
-}
-
-/* Handle the Format 4 instructions that do not have equivalents in other
-   formats.  That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
-   BIC and MVN.  */
-
-static void
-do_t_arit (str)
-     char * str;
-{
-  int Rd, Rs, Rn;
-
-  skip_whitespace (str);
-
-  if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
+  if (bytes & (noop_size - 1))
     {
-      inst.error = BAD_ARGS;
-      return;
+      fix = bytes & (noop_size - 1);
+      memset (p, 0, fix);
+      p += fix;
+      bytes -= fix;
     }
 
-  if (skip_past_comma (&str) != FAIL)
+  while (bytes >= noop_size)
     {
-      /* Three operand format not allowed for TST, CMN, NEG and MVN.
-	 (It isn't allowed for CMP either, but that isn't handled by this
-	 function.)  */
-      if (inst.instruction == T_OPCODE_TST
-	  || inst.instruction == T_OPCODE_CMN
-	  || inst.instruction == T_OPCODE_NEG
-	  || inst.instruction == T_OPCODE_MVN)
-	{
-	  inst.error = BAD_ARGS;
-	  return;
-	}
-
-      if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
-	return;
-
-      if (Rs != Rd)
-	{
-	  inst.error = _("dest and source1 must be the same register");
-	  return;
-	}
-      Rs = Rn;
+      memcpy (p, noop, noop_size);
+      p += noop_size;
+      bytes -= noop_size;
+      fix += noop_size;
     }
 
-  if (inst.instruction == T_OPCODE_MUL
-      && Rs == Rd)
-    as_tsktsk (_("Rs and Rd must be different in MUL"));
-
-  inst.instruction |= Rd | (Rs << 3);
-  end_of_line (str);
+  fragP->fr_fix += fix;
+  fragP->fr_var = noop_size;
 }
 
-static void
-do_t_add (str)
-     char * str;
-{
-  thumb_add_sub (str, 0);
-}
+/* Called from md_do_align.  Used to create an alignment
+   frag in a code section.  */
 
-static void
-do_t_asr (str)
-     char * str;
+void
+arm_frag_align_code (int n, int max)
 {
-  thumb_shift (str, THUMB_ASR);
-}
+  char * p;
 
-static void
-do_t_branch9 (str)
-     char * str;
-{
-  if (my_get_expression (&inst.reloc.exp, &str))
-    return;
-  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
-  inst.reloc.pc_rel = 1;
-  end_of_line (str);
-}
+  /* We assume that there will never be a requirement
+     to support alignments greater than 32 bytes.  */
+  if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
+    as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
 
-static void
-do_t_branch12 (str)
-     char * str;
-{
-  if (my_get_expression (&inst.reloc.exp, &str))
-    return;
-  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
-  inst.reloc.pc_rel = 1;
-  end_of_line (str);
+  p = frag_var (rs_align_code,
+		MAX_MEM_FOR_RS_ALIGN_CODE,
+		1,
+		(relax_substateT) max,
+		(symbolS *) NULL,
+		(offsetT) n,
+		(char *) NULL);
+  *p = 0;
 }
 
-/* Find the real, Thumb encoded start of a Thumb function.  */
+/* Perform target specific initialisation of a frag.  */
 
-static symbolS *
-find_real_start (symbolP)
-     symbolS * symbolP;
+void
+arm_init_frag (fragS * fragP)
 {
-  char *       real_start;
-  const char * name = S_GET_NAME (symbolP);
-  symbolS *    new_target;
-
-  /* This definition must agree with the one in gcc/config/arm/thumb.c.  */
-#define STUB_NAME ".real_start_of"
-
-  if (name == NULL)
-    abort ();
-
-  /* Names that start with '.' are local labels, not function entry points.
-     The compiler may generate BL instructions to these labels because it
-     needs to perform a branch to a far away location.  */
-  if (name[0] == '.')
-    return symbolP;
-
-  real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
-  sprintf (real_start, "%s%s", STUB_NAME, name);
-
-  new_target = symbol_find (real_start);
-
-  if (new_target == NULL)
-    {
-      as_warn ("Failed to find real start of function: %s\n", name);
-      new_target = symbolP;
-    }
-
-  free (real_start);
-
-  return new_target;
+  /* Record whether this frag is in an ARM or a THUMB area.  */
+  fragP->tc_frag_data = thumb_mode;
 }
 
-static void
-do_t_branch23 (str)
-     char * str;
-{
-  if (my_get_expression (& inst.reloc.exp, & str))
-    return;
-
-  inst.reloc.type   = BFD_RELOC_THUMB_PCREL_BRANCH23;
-  inst.reloc.pc_rel = 1;
-  end_of_line (str);
-
-  /* If the destination of the branch is a defined symbol which does not have
-     the THUMB_FUNC attribute, then we must be calling a function which has
-     the (interfacearm) attribute.  We look for the Thumb entry point to that
-     function and change the branch to refer to that function instead.  */
-  if (   inst.reloc.exp.X_op == O_symbol
-      && inst.reloc.exp.X_add_symbol != NULL
-      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
-      && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
-    inst.reloc.exp.X_add_symbol =
-      find_real_start (inst.reloc.exp.X_add_symbol);
-}
+#ifdef OBJ_ELF
+/* When we change sections we need to issue a new mapping symbol.  */
 
-static void
-do_t_bx (str)
-     char * str;
+void
+arm_elf_change_section (void)
 {
-  int reg;
+  flagword flags;
+  segment_info_type *seginfo;
 
-  skip_whitespace (str);
+  /* Link an unlinked unwind index table section to the .text section.	*/
+  if (elf_section_type (now_seg) == SHT_ARM_EXIDX
+      && elf_linked_to_section (now_seg) == NULL)
+    elf_linked_to_section (now_seg) = text_section;
 
-  if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
+  if (!SEG_NORMAL (now_seg))
     return;
 
-  /* This sets THUMB_H2 from the top bit of reg.  */
-  inst.instruction |= reg << 3;
+  flags = bfd_get_section_flags (stdoutput, now_seg);
 
-  /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC.  The reloc
-     should cause the alignment to be checked once it is known.  This is
-     because BX PC only works if the instruction is word aligned.  */
+  /* We can ignore sections that only contain debug info.  */
+  if ((flags & SEC_ALLOC) == 0)
+    return;
 
-  end_of_line (str);
+  seginfo = seg_info (now_seg);
+  mapstate = seginfo->tc_segment_info_data.mapstate;
+  marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
 }
 
-static void
-do_t_compare (str)
-     char * str;
-{
-  thumb_mov_compare (str, THUMB_COMPARE);
-}
-
-static void
-do_t_ldmstm (str)
-     char * str;
+int
+arm_elf_section_type (const char * str, size_t len)
 {
-  int Rb;
-  long range;
-
-  skip_whitespace (str);
-
-  if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
-    return;
+  if (len == 5 && strncmp (str, "exidx", 5) == 0)
+    return SHT_ARM_EXIDX;
 
-  if (*str != '!')
-    as_warn (_("inserted missing '!': load/store multiple always writes back base register"));
-  else
-    str++;
-
-  if (skip_past_comma (&str) == FAIL
-      || (range = reg_list (&str)) == FAIL)
-    {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
-    }
-
-  if (inst.reloc.type != BFD_RELOC_NONE)
-    {
-      /* This really doesn't seem worth it.  */
-      inst.reloc.type = BFD_RELOC_NONE;
-      inst.error = _("expression too complex");
-      return;
-    }
+  return -1;
+}
+
+/* Code to deal with unwinding tables.	*/
 
-  if (range & ~0xff)
-    {
-      inst.error = _("only lo-regs valid in load/store multiple");
-      return;
-    }
+static void add_unwind_adjustsp (offsetT);
 
-  inst.instruction |= (Rb << 8) | range;
-  end_of_line (str);
-}
+/* Cenerate and deferred unwind frame offset.  */
 
 static void
-do_t_ldr (str)
-     char * str;
+flush_pending_unwind (void)
 {
-  thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
-}
+  offsetT offset;
 
-static void
-do_t_ldrb (str)
-     char * str;
-{
-  thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
+  offset = unwind.pending_offset;
+  unwind.pending_offset = 0;
+  if (offset != 0)
+    add_unwind_adjustsp (offset);
 }
 
-static void
-do_t_ldrh (str)
-     char * str;
-{
-  thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
-}
+/* Add an opcode to this list for this function.  Two-byte opcodes should
+   be passed as op[0] << 8 | op[1].  The list of opcodes is built in reverse
+   order.  */
 
 static void
-do_t_lds (str)
-     char * str;
+add_unwind_opcode (valueT op, int length)
 {
-  int Rd, Rb, Ro;
+  /* Add any deferred stack adjustment.	 */
+  if (unwind.pending_offset)
+    flush_pending_unwind ();
 
-  skip_whitespace (str);
+  unwind.sp_restored = 0;
 
-  if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || *str++ != '['
-      || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || skip_past_comma (&str) == FAIL
-      || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
-      || *str++ != ']')
+  if (unwind.opcode_count + length > unwind.opcode_alloc)
     {
-      if (! inst.error)
-	inst.error = _("syntax: ldrs[b] Rd, [Rb, Ro]");
-      return;
+      unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
+      if (unwind.opcodes)
+	unwind.opcodes = xrealloc (unwind.opcodes,
+				   unwind.opcode_alloc);
+      else
+	unwind.opcodes = xmalloc (unwind.opcode_alloc);
+    }
+  while (length > 0)
+    {
+      length--;
+      unwind.opcodes[unwind.opcode_count] = op & 0xff;
+      op >>= 8;
+      unwind.opcode_count++;
     }
-
-  inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
-  end_of_line (str);
-}
-
-static void
-do_t_lsl (str)
-     char * str;
-{
-  thumb_shift (str, THUMB_LSL);
 }
 
-static void
-do_t_lsr (str)
-     char * str;
-{
-  thumb_shift (str, THUMB_LSR);
-}
+/* Add unwind opcodes to adjust the stack pointer.  */
 
 static void
-do_t_mov (str)
-     char * str;
+add_unwind_adjustsp (offsetT offset)
 {
-  thumb_mov_compare (str, THUMB_MOVE);
-}
+  valueT op;
 
-static void
-do_t_push_pop (str)
-     char * str;
-{
-  long range;
+  if (offset > 0x200)
+    {
+      /* We need at most 5 bytes to hold a 32-bit value in a uleb128.  */
+      char bytes[5];
+      int n;
+      valueT o;
 
-  skip_whitespace (str);
+      /* Long form: 0xb2, uleb128.  */
+      /* This might not fit in a word so add the individual bytes,
+	 remembering the list is built in reverse order.  */
+      o = (valueT) ((offset - 0x204) >> 2);
+      if (o == 0)
+	add_unwind_opcode (0, 1);
 
-  if ((range = reg_list (&str)) == FAIL)
+      /* Calculate the uleb128 encoding of the offset.	*/
+      n = 0;
+      while (o)
+	{
+	  bytes[n] = o & 0x7f;
+	  o >>= 7;
+	  if (o)
+	    bytes[n] |= 0x80;
+	  n++;
+	}
+      /* Add the insn.	*/
+      for (; n; n--)
+	add_unwind_opcode (bytes[n - 1], 1);
+      add_unwind_opcode (0xb2, 1);
+    }
+  else if (offset > 0x100)
     {
-      if (! inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      /* Two short opcodes.  */
+      add_unwind_opcode (0x3f, 1);
+      op = (offset - 0x104) >> 2;
+      add_unwind_opcode (op, 1);
     }
-
-  if (inst.reloc.type != BFD_RELOC_NONE)
+  else if (offset > 0)
     {
-      /* This really doesn't seem worth it.  */
-      inst.reloc.type = BFD_RELOC_NONE;
-      inst.error = _("expression too complex");
-      return;
+      /* Short opcode.	*/
+      op = (offset - 4) >> 2;
+      add_unwind_opcode (op, 1);
     }
-
-  if (range & ~0xff)
+  else if (offset < 0)
     {
-      if ((inst.instruction == T_OPCODE_PUSH
-	   && (range & ~0xff) == 1 << REG_LR)
-	  || (inst.instruction == T_OPCODE_POP
-	      && (range & ~0xff) == 1 << REG_PC))
-	{
-	  inst.instruction |= THUMB_PP_PC_LR;
-	  range &= 0xff;
-	}
-      else
+      offset = -offset;
+      while (offset > 0x100)
 	{
-	  inst.error = _("invalid register list to push/pop instruction");
-	  return;
+	  add_unwind_opcode (0x7f, 1);
+	  offset -= 0x100;
 	}
+      op = ((offset - 4) >> 2) | 0x40;
+      add_unwind_opcode (op, 1);
     }
-
-  inst.instruction |= range;
-  end_of_line (str);
 }
 
+/* Finish the list of unwind opcodes for this function.	 */
 static void
-do_t_str (str)
-     char * str;
+finish_unwind_opcodes (void)
 {
-  thumb_load_store (str, THUMB_STORE, THUMB_WORD);
-}
+  valueT op;
 
-static void
-do_t_strb (str)
-     char * str;
-{
-  thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
-}
-
-static void
-do_t_strh (str)
-     char * str;
-{
-  thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
-}
+  if (unwind.fp_used)
+    {
+      /* Adjust sp as neccessary.  */
+      unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
+      flush_pending_unwind ();
 
-static void
-do_t_sub (str)
-     char * str;
-{
-  thumb_add_sub (str, 1);
+      /* After restoring sp from the frame pointer.  */
+      op = 0x90 | unwind.fp_reg;
+      add_unwind_opcode (op, 1);
+    }
+  else
+    flush_pending_unwind ();
 }
 
-static void
-do_t_swi (str)
-     char * str;
-{
-  skip_whitespace (str);
-
-  if (my_get_expression (&inst.reloc.exp, &str))
-    return;
 
-  inst.reloc.type = BFD_RELOC_ARM_SWI;
-  end_of_line (str);
-}
+/* Start an exception table entry.  If idx is nonzero this is an index table
+   entry.  */
 
 static void
-do_t_adr (str)
-     char * str;
+start_unwind_section (const segT text_seg, int idx)
 {
-  int reg;
-
-  /* This is a pseudo-op of the form "adr rd, label" to be converted
-     into a relative address of the form "add rd, pc, #label-.-4".  */
-  skip_whitespace (str);
+  const char * text_name;
+  const char * prefix;
+  const char * prefix_once;
+  const char * group_name;
+  size_t prefix_len;
+  size_t text_len;
+  char * sec_name;
+  size_t sec_name_len;
+  int type;
+  int flags;
+  int linkonce;
 
-  /* Store Rd in temporary location inside instruction.  */
-  if ((reg = reg_required_here (&str, 4)) == FAIL
-      || (reg > 7)  /* For Thumb reg must be r0..r7.  */
-      || skip_past_comma (&str) == FAIL
-      || my_get_expression (&inst.reloc.exp, &str))
+  if (idx)
     {
-      if (!inst.error)
-	inst.error = BAD_ARGS;
-      return;
+      prefix = ELF_STRING_ARM_unwind;
+      prefix_once = ELF_STRING_ARM_unwind_once;
+      type = SHT_ARM_EXIDX;
+    }
+  else
+    {
+      prefix = ELF_STRING_ARM_unwind_info;
+      prefix_once = ELF_STRING_ARM_unwind_info_once;
+      type = SHT_PROGBITS;
     }
 
-  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
-  inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
-  inst.reloc.pc_rel = 1;
-  inst.instruction |= REG_PC; /* Rd is already placed into the instruction.  */
-
-  end_of_line (str);
-}
+  text_name = segment_name (text_seg);
+  if (streq (text_name, ".text"))
+    text_name = "";
 
-static void
-insert_reg (r, htab)
-     const struct reg_entry *r;
-     struct hash_control *htab;
-{
-  int    len  = strlen (r->name) + 2;
-  char * buf  = (char *) xmalloc (len);
-  char * buf2 = (char *) xmalloc (len);
-  int    i    = 0;
+  if (strncmp (text_name, ".gnu.linkonce.t.",
+	       strlen (".gnu.linkonce.t.")) == 0)
+    {
+      prefix = prefix_once;
+      text_name += strlen (".gnu.linkonce.t.");
+    }
 
-#ifdef REGISTER_PREFIX
-  buf[i++] = REGISTER_PREFIX;
-#endif
+  prefix_len = strlen (prefix);
+  text_len = strlen (text_name);
+  sec_name_len = prefix_len + text_len;
+  sec_name = xmalloc (sec_name_len + 1);
+  memcpy (sec_name, prefix, prefix_len);
+  memcpy (sec_name + prefix_len, text_name, text_len);
+  sec_name[prefix_len + text_len] = '\0';
 
-  strcpy (buf + i, r->name);
+  flags = SHF_ALLOC;
+  linkonce = 0;
+  group_name = 0;
 
-  for (i = 0; buf[i]; i++)
-    buf2[i] = TOUPPER (buf[i]);
+  /* Handle COMDAT group.  */
+  if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
+    {
+      group_name = elf_group_name (text_seg);
+      if (group_name == NULL)
+	{
+	  as_bad ("Group section `%s' has no group signature",
+		  segment_name (text_seg));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      flags |= SHF_GROUP;
+      linkonce = 1;
+    }
 
-  buf2[i] = '\0';
+  obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
 
-  hash_insert (htab, buf,  (PTR) r);
-  hash_insert (htab, buf2, (PTR) r);
+  /* Set the setion link for index tables.  */
+  if (idx)
+    elf_linked_to_section (now_seg) = text_seg;
 }
 
-static void
-build_reg_hsh (map)
-     struct reg_map *map;
-{
-  const struct reg_entry *r;
 
-  if ((map->htab = hash_new ()) == NULL)
-    as_fatal (_("virtual memory exhausted"));
-
-  for (r = map->names; r->name != NULL; r++)
-    insert_reg (r, map->htab);
-}
+/* Start an unwind table entry.	 HAVE_DATA is nonzero if we have additional
+   personality routine data.  Returns zero, or the index table value for
+   and inline entry.  */
 
-static void
-insert_reg_alias (str, regnum, htab)
-     char *str;
-     int regnum;
-     struct hash_control *htab;
+static valueT
+create_unwind_entry (int have_data)
 {
-  const char *error;
-  struct reg_entry *new = xmalloc (sizeof (struct reg_entry));
-  const char *name = xmalloc (strlen (str) + 1);
-  
-  strcpy ((char *) name, str);
-  
-  new->name = name;
-  new->number = regnum;
-  new->builtin = FALSE;
-
-  error = hash_insert (htab, name, (PTR) new);
-  if (error)
-    {
-      as_bad (_("failed to create an alias for %s, reason: %s"),
-	    str, error);
-      free ((char *) name);
-      free (new);
-    }
-}
+  int size;
+  addressT where;
+  char *ptr;
+  /* The current word of data.	*/
+  valueT data;
+  /* The number of bytes left in this word.  */
+  int n;
 
-/* Look for the .req directive.  This is of the form:
+  finish_unwind_opcodes ();
 
-   	new_register_name .req existing_register_name
+  /* Remember the current text section.	 */
+  unwind.saved_seg = now_seg;
+  unwind.saved_subseg = now_subseg;
 
-   If we find one, or if it looks sufficiently like one that we want to
-   handle any error here, return non-zero.  Otherwise return zero.  */
-static int
-create_register_alias (newname, p)
-     char *newname;
-     char *p;
-{
-  char *q;
-  char c;
+  start_unwind_section (now_seg, 0);
 
-  q = p;
-  skip_whitespace (q);
-
-  c = *p;
-  *p = '\0';
-
-  if (*q && !strncmp (q, ".req ", 5))
+  if (unwind.personality_routine == NULL)
     {
-      char *copy_of_str;
-      char *r;
-
-#ifdef IGNORE_OPCODE_CASE
-      newname = original_case_string;
-#endif
-      copy_of_str = newname;
-
-      q += 4;
-      skip_whitespace (q);
-
-      for (r = q; *r != '\0'; r++)
-	if (*r == ' ')
-	  break;
-
-      if (r != q)
+      if (unwind.personality_index == -2)
 	{
-	  enum arm_reg_type new_type, old_type;
-	  int old_regno;
-	  char d = *r;
+	  if (have_data)
+	    as_bad (_("handerdata in cantunwind frame"));
+	  return 1; /* EXIDX_CANTUNWIND.  */
+	}
 
-	  *r = '\0';
-	  old_type = arm_reg_parse_any (q);
-	  *r = d;
+      /* Use a default personality routine if none is specified.  */
+      if (unwind.personality_index == -1)
+	{
+	  if (unwind.opcode_count > 3)
+	    unwind.personality_index = 1;
+	  else
+	    unwind.personality_index = 0;
+	}
 
-	  new_type = arm_reg_parse_any (newname);
+      /* Space for the personality routine entry.  */
+      if (unwind.personality_index == 0)
+	{
+	  if (unwind.opcode_count > 3)
+	    as_bad (_("too many unwind opcodes for personality routine 0"));
 
-	  if (new_type == REG_TYPE_MAX)
+	  if (!have_data)
 	    {
-	      if (old_type != REG_TYPE_MAX)
+	      /* All the data is inline in the index table.  */
+	      data = 0x80;
+	      n = 3;
+	      while (unwind.opcode_count > 0)
 		{
-		  old_regno = arm_reg_parse (&q, all_reg_maps[old_type].htab);
-		  insert_reg_alias (newname, old_regno,
-				    all_reg_maps[old_type].htab);
+		  unwind.opcode_count--;
+		  data = (data << 8) | unwind.opcodes[unwind.opcode_count];
+		  n--;
 		}
-	      else
-		as_warn (_("register '%s' does not exist\n"), q);
-	    }
-	  else if (old_type == REG_TYPE_MAX)
-	    {
-	      as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
-		       copy_of_str, q);
-	    }
-	  else
-	    {
-	      /* Do not warn about redefinitions to the same alias.  */
-	      if (new_type != old_type
-		  || (arm_reg_parse (&q, all_reg_maps[old_type].htab)
-		      != arm_reg_parse (&q, all_reg_maps[new_type].htab)))
-		as_warn (_("ignoring redefinition of register alias '%s'"),
-			 copy_of_str);
 
+	      /* Pad with "finish" opcodes.  */
+	      while (n--)
+		data = (data << 8) | 0xb0;
+
+	      return data;
 	    }
+	  size = 0;
 	}
       else
-	as_warn (_("ignoring incomplete .req pseuso op"));
-
-      *p = c;
-      return 1;
+	/* We get two opcodes "free" in the first word.	 */
+	size = unwind.opcode_count - 2;
     }
-  
-  *p = c;
-  return 0;
-}
-
-static void
-set_constant_flonums ()
-{
-  int i;
+  else
+    /* An extra byte is required for the opcode count.	*/
+    size = unwind.opcode_count + 1;
 
-  for (i = 0; i < NUM_FLOAT_VALS; i++)
-    if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
-      abort ();
-}
+  size = (size + 3) >> 2;
+  if (size > 0xff)
+    as_bad (_("too many unwind opcodes"));
 
-/* Iterate over the base tables to create the instruction patterns.  */
-static void
-build_arm_ops_hsh ()
-{
-  unsigned int i;
-  unsigned int j;
-  static struct obstack insn_obstack;
+  frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
+  unwind.table_entry = expr_build_dot ();
 
-  obstack_begin (&insn_obstack, 4000);
+  /* Allocate the table entry.	*/
+  ptr = frag_more ((size << 2) + 4);
+  where = frag_now_fix () - ((size << 2) + 4);
 
-  for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
+  switch (unwind.personality_index)
     {
-      const struct asm_opcode *insn = insns + i;
+    case -1:
+      /* ??? Should this be a PLT generating relocation?  */
+      /* Custom personality routine.  */
+      fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
+	       BFD_RELOC_ARM_PREL31);
+
+      where += 4;
+      ptr += 4;
+
+      /* Set the first byte to the number of additional words.	*/
+      data = size - 1;
+      n = 3;
+      break;
+
+    /* ABI defined personality routines.  */
+    case 0:
+      /* Three opcodes bytes are packed into the first word.  */
+      data = 0x80;
+      n = 3;
+      break;
+
+    case 1:
+    case 2:
+      /* The size and first two opcode bytes go in the first word.  */
+      data = ((0x80 + unwind.personality_index) << 8) | size;
+      n = 2;
+      break;
+
+    default:
+      /* Should never happen.  */
+      abort ();
+    }
 
-      if (insn->cond_offset != 0)
+  /* Pack the opcodes into words (MSB first), reversing the list at the same
+     time.  */
+  while (unwind.opcode_count > 0)
+    {
+      if (n == 0)
 	{
-	  /* Insn supports conditional execution.  Build the varaints
-	     and insert them in the hash table.  */
-	  for (j = 0; j < sizeof (conds) / sizeof (struct asm_cond); j++)
-	    {
-	      unsigned len = strlen (insn->template);
-	      struct asm_opcode *new;
-	      char *template;
-
-	      new = obstack_alloc (&insn_obstack, sizeof (struct asm_opcode));
-	      /* All condition codes are two characters.  */
-	      template = obstack_alloc (&insn_obstack, len + 3);
-
-	      strncpy (template, insn->template, insn->cond_offset);
-	      strcpy (template + insn->cond_offset, conds[j].template);
-	      if (len > insn->cond_offset)
-		strcpy (template + insn->cond_offset + 2,
-			insn->template + insn->cond_offset);
-	      new->template = template;
-	      new->cond_offset = 0;
-	      new->variant = insn->variant;
-	      new->parms = insn->parms;
-	      new->value = (insn->value & ~COND_MASK) | conds[j].value;
-
-	      hash_insert (arm_ops_hsh, new->template, (PTR) new);
-	    }
+	  md_number_to_chars (ptr, data, 4);
+	  ptr += 4;
+	  n = 4;
+	  data = 0;
 	}
-      /* Finally, insert the unconditional insn in the table directly;
-	 no need to build a copy.  */
-      hash_insert (arm_ops_hsh, insn->template, (PTR) insn);
+      unwind.opcode_count--;
+      n--;
+      data = (data << 8) | unwind.opcodes[unwind.opcode_count];
     }
-}
-
-#if 0 /* Suppressed - for now.  */
-#if defined OBJ_ELF || defined OBJ_COFF
 
-#ifdef OBJ_ELF
-#define arm_Note Elf_External_Note
-#else
-typedef struct
-{
-  unsigned char	namesz[4];	/* Size of entry's owner string.  */
-  unsigned char	descsz[4];	/* Size of the note descriptor.  */
-  unsigned char	type[4];	/* Interpretation of the descriptor.  */
-  char		name[1];	/* Start of the name+desc data.  */
-} arm_Note;
-#endif
+  /* Finish off the last word.	*/
+  if (n < 4)
+    {
+      /* Pad with "finish" opcodes.  */
+      while (n--)
+	data = (data << 8) | 0xb0;
 
-/* The description is kept to a fix sized in order to make updating
-   it and merging it easier.  */
-#define ARM_NOTE_DESCRIPTION_LENGTH	8
+      md_number_to_chars (ptr, data, 4);
+    }
 
-static void
-arm_add_note (name, description, type)
-     const char * name;
-     const char * description;
-     unsigned int type;
-{
-  arm_Note     note ATTRIBUTE_UNUSED;
-  char *       p;
-  unsigned int name_len;
+  if (!have_data)
+    {
+      /* Add an empty descriptor if there is no user-specified data.   */
+      ptr = frag_more (4);
+      md_number_to_chars (ptr, 0, 4);
+    }
 
-  name_len = (strlen (name) + 1 + 3) & ~3;
-  
-  p = frag_more (sizeof (note.namesz));
-  md_number_to_chars (p, (valueT) name_len, sizeof (note.namesz));
+  return 0;
+}
 
-  p = frag_more (sizeof (note.descsz));
-  md_number_to_chars (p, (valueT) ARM_NOTE_DESCRIPTION_LENGTH, sizeof (note.descsz));
+/* Convert REGNAME to a DWARF-2 register number.  */
 
-  p = frag_more (sizeof (note.type));
-  md_number_to_chars (p, (valueT) type, sizeof (note.type));
+int
+tc_arm_regname_to_dw2regnum (const char *regname)
+{
+  int reg = arm_reg_parse ((char **) &regname, REG_TYPE_RN);
 
-  p = frag_more (name_len);
-  strcpy (p, name);
+  if (reg == FAIL)
+    return -1;
 
-  p = frag_more (ARM_NOTE_DESCRIPTION_LENGTH);
-  strncpy (p, description, ARM_NOTE_DESCRIPTION_LENGTH);
-  frag_align (2, 0, 0);
+  return reg;
 }
-#endif
-#endif
+
+/* Initialize the DWARF-2 unwind information for this procedure.  */
 
 void
-md_begin ()
+tc_arm_frame_initial_instructions (void)
 {
-  unsigned mach;
-  unsigned int i;
+  cfi_add_CFA_def_cfa (REG_SP, 0);
+}
+#endif /* OBJ_ELF */
 
-  if (   (arm_ops_hsh = hash_new ()) == NULL
-      || (arm_tops_hsh = hash_new ()) == NULL
-      || (arm_cond_hsh = hash_new ()) == NULL
-      || (arm_shift_hsh = hash_new ()) == NULL
-      || (arm_psr_hsh = hash_new ()) == NULL)
-    as_fatal (_("virtual memory exhausted"));
 
-  build_arm_ops_hsh ();
-  for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
-    hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
-  for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
-    hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
-  for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
-    hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
-  for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
-    hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
+/* MD interface: Symbol and relocation handling.  */
 
-  for (i = (int) REG_TYPE_FIRST; i < (int) REG_TYPE_MAX; i++)
-    build_reg_hsh (all_reg_maps + i);
+/* Return the address within the segment that a PC-relative fixup is
+   relative to.  For ARM, PC-relative fixups applied to instructions
+   are generally relative to the location of the fixup plus 8 bytes.
+   Thumb branches are offset by 4, and Thumb loads relative to PC
+   require special handling.  */
 
-  set_constant_flonums ();
+long
+md_pcrel_from_section (fixS * fixP, segT seg)
+{
+  offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
 
-  /* Set the cpu variant based on the command-line options.  We prefer
-     -mcpu= over -march= if both are set (as for GCC); and we prefer
-     -mfpu= over any other way of setting the floating point unit.
-     Use of legacy options with new options are faulted.  */
-  if (legacy_cpu != -1)
+  /* If this is pc-relative and we are going to emit a relocation
+     then we just want to put out any pipeline compensation that the linker
+     will need.  Otherwise we want to use the calculated base.  */
+  if (fixP->fx_pcrel 
+      && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
+	  || arm_force_relocation (fixP)))
+    base = 0;
+
+  switch (fixP->fx_r_type)
     {
-      if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
-	as_bad (_("use of old and new-style options to set CPU type"));
+      /* PC relative addressing on the Thumb is slightly odd as the
+	 bottom two bits of the PC are forced to zero for the
+	 calculation.  This happens *after* application of the
+	 pipeline offset.  However, Thumb adrl already adjusts for
+	 this, so we need not do it again.  */
+    case BFD_RELOC_ARM_THUMB_ADD:
+      return base & ~3;
 
-      mcpu_cpu_opt = legacy_cpu;
-    }
-  else if (mcpu_cpu_opt == -1)
-    mcpu_cpu_opt = march_cpu_opt;
+    case BFD_RELOC_ARM_THUMB_OFFSET:
+    case BFD_RELOC_ARM_T32_OFFSET_IMM:
+    case BFD_RELOC_ARM_T32_ADD_PC12:
+    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
+      return (base + 4) & ~3;
 
-  if (legacy_fpu != -1)
-    {
-      if (mfpu_opt != -1)
-	as_bad (_("use of old and new-style options to set FPU type"));
+      /* Thumb branches are simply offset by +4.  */
+    case BFD_RELOC_THUMB_PCREL_BRANCH7:
+    case BFD_RELOC_THUMB_PCREL_BRANCH9:
+    case BFD_RELOC_THUMB_PCREL_BRANCH12:
+    case BFD_RELOC_THUMB_PCREL_BRANCH20:
+    case BFD_RELOC_THUMB_PCREL_BRANCH23:
+    case BFD_RELOC_THUMB_PCREL_BRANCH25:
+    case BFD_RELOC_THUMB_PCREL_BLX:
+      return base + 4;
 
-      mfpu_opt = legacy_fpu;
-    }
-  else if (mfpu_opt == -1)
-    {
-#if !(defined (TE_LINUX) || defined (TE_NetBSD))
-      /* Some environments specify a default FPU.  If they don't, infer it
-	 from the processor.  */
-      if (mcpu_fpu_opt != -1)
-	mfpu_opt = mcpu_fpu_opt;
-      else
-	mfpu_opt = march_fpu_opt;
+      /* ARM mode branches are offset by +8.  However, the Windows CE
+	 loader expects the relocation not to take this into account.  */
+    case BFD_RELOC_ARM_PCREL_BRANCH:
+    case BFD_RELOC_ARM_PCREL_CALL:
+    case BFD_RELOC_ARM_PCREL_JUMP:
+    case BFD_RELOC_ARM_PCREL_BLX:
+    case BFD_RELOC_ARM_PLT32:
+#ifdef TE_WINCE
+      return base;
 #else
-      mfpu_opt = FPU_DEFAULT;
+      return base + 8;
 #endif
+
+      /* ARM mode loads relative to PC are also offset by +8.  Unlike
+	 branches, the Windows CE loader *does* expect the relocation
+	 to take this into account.  */
+    case BFD_RELOC_ARM_OFFSET_IMM:
+    case BFD_RELOC_ARM_OFFSET_IMM8:
+    case BFD_RELOC_ARM_HWLITERAL:
+    case BFD_RELOC_ARM_LITERAL:
+    case BFD_RELOC_ARM_CP_OFF_IMM:
+      return base + 8;
+
+
+      /* Other PC-relative relocations are un-offset.  */
+    default:
+      return base;
     }
+}
+
+/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
+   Otherwise we have no need to default values of symbols.  */
 
-  if (mfpu_opt == -1)
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+#ifdef OBJ_ELF
+  if (name[0] == '_' && name[1] == 'G'
+      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
     {
-      if (mcpu_cpu_opt == -1)
-	mfpu_opt = FPU_DEFAULT;
-      else if (mcpu_cpu_opt & ARM_EXT_V5)
-	mfpu_opt = FPU_ARCH_VFP_V2;
-      else
-	mfpu_opt = FPU_ARCH_FPA;
+      if (!GOT_symbol)
+	{
+	  if (symbol_find (name))
+	    as_bad ("GOT already in the symbol table");
+
+	  GOT_symbol = symbol_new (name, undefined_section,
+				   (valueT) 0, & zero_address_frag);
+	}
+
+      return GOT_symbol;
     }
+#endif
 
-  if (mcpu_cpu_opt == -1)
-    mcpu_cpu_opt = CPU_DEFAULT;
+  return 0;
+}
 
-  cpu_variant = mcpu_cpu_opt | mfpu_opt;
+/* Subroutine of md_apply_fix.	 Check to see if an immediate can be
+   computed as two separate immediate values, added together.  We
+   already know that this value cannot be computed by just one ARM
+   instruction.	 */
 
-#if defined OBJ_COFF || defined OBJ_ELF
-  {
-    unsigned int flags = 0;
+static unsigned int
+validate_immediate_twopart (unsigned int   val,
+			    unsigned int * highpart)
+{
+  unsigned int a;
+  unsigned int i;
 
-    /* Set the flags in the private structure.  */
-    if (uses_apcs_26)      flags |= F_APCS26;
-    if (support_interwork) flags |= F_INTERWORK;
-    if (uses_apcs_float)   flags |= F_APCS_FLOAT;
-    if (pic_code)          flags |= F_PIC;
-    if ((cpu_variant & FPU_ANY) == FPU_NONE
-	 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only.  */
-      {
-	flags |= F_SOFT_FLOAT;
-      }
-    switch (mfloat_abi_opt)
+  for (i = 0; i < 32; i += 2)
+    if (((a = rotate_left (val, i)) & 0xff) != 0)
       {
-      case ARM_FLOAT_ABI_SOFT:
-      case ARM_FLOAT_ABI_SOFTFP:
-	flags |= F_SOFT_FLOAT;
-	break;
+	if (a & 0xff00)
+	  {
+	    if (a & ~ 0xffff)
+	      continue;
+	    * highpart = (a  >> 8) | ((i + 24) << 7);
+	  }
+	else if (a & 0xff0000)
+	  {
+	    if (a & 0xff000000)
+	      continue;
+	    * highpart = (a >> 16) | ((i + 16) << 7);
+	  }
+	else
+	  {
+	    assert (a & 0xff000000);
+	    * highpart = (a >> 24) | ((i + 8) << 7);
+	  }
 
-      case ARM_FLOAT_ABI_HARD:
-	if (flags & F_SOFT_FLOAT)
-	  as_bad (_("hard-float conflicts with specified fpu"));
-	break;
+	return (a & 0xff) | (i << 7);
       }
-    /* Using VFP conventions (even if soft-float).  */
-    if (cpu_variant & FPU_VFP_EXT_NONE) flags |= F_VFP_FLOAT;
 
-#if defined OBJ_ELF
-    if (cpu_variant & FPU_ARCH_MAVERICK)
-	flags |= EF_ARM_MAVERICK_FLOAT;
-#endif
+  return FAIL;
+}
 
-    bfd_set_private_flags (stdoutput, flags);
+static int
+validate_offset_imm (unsigned int val, int hwse)
+{
+  if ((hwse && val > 255) || val > 4095)
+    return FAIL;
+  return val;
+}
 
-    /* We have run out flags in the COFF header to encode the
-       status of ATPCS support, so instead we create a dummy,
-       empty, debug section called .arm.atpcs.  */
-    if (atpcs)
-      {
-	asection * sec;
+/* Subroutine of md_apply_fix.	 Do those data_ops which can take a
+   negative immediate constant by altering the instruction.  A bit of
+   a hack really.
+	MOV <-> MVN
+	AND <-> BIC
+	ADC <-> SBC
+	by inverting the second operand, and
+	ADD <-> SUB
+	CMP <-> CMN
+	by negating the second operand.	 */
 
-	sec = bfd_make_section (stdoutput, ".arm.atpcs");
+static int
+negate_data_op (unsigned long * instruction,
+		unsigned long	value)
+{
+  int op, new_inst;
+  unsigned long negated, inverted;
 
-	if (sec != NULL)
-	  {
-	    bfd_set_section_flags
-	      (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
-	    bfd_set_section_size (stdoutput, sec, 0);
-	    bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
-	  }
-      }
-  }
-#endif
+  negated = encode_arm_immediate (-value);
+  inverted = encode_arm_immediate (~value);
 
-  /* Record the CPU type as well.  */
-  switch (cpu_variant & ARM_CPU_MASK)
+  op = (*instruction >> DATA_OP_SHIFT) & 0xf;
+  switch (op)
     {
-    case ARM_2:
-      mach = bfd_mach_arm_2;
+      /* First negates.	 */
+    case OPCODE_SUB:		 /* ADD <-> SUB	 */
+      new_inst = OPCODE_ADD;
+      value = negated;
       break;
 
-    case ARM_3: 		/* Also ARM_250.  */
-      mach = bfd_mach_arm_2a;
+    case OPCODE_ADD:
+      new_inst = OPCODE_SUB;
+      value = negated;
       break;
 
-    case ARM_6:			/* Also ARM_7.  */
-      mach = bfd_mach_arm_3;
+    case OPCODE_CMP:		 /* CMP <-> CMN	 */
+      new_inst = OPCODE_CMN;
+      value = negated;
       break;
 
-    default:
-      mach = bfd_mach_arm_unknown;
+    case OPCODE_CMN:
+      new_inst = OPCODE_CMP;
+      value = negated;
       break;
-    }
-
-  /* Catch special cases.  */
-  if (cpu_variant & ARM_CEXT_IWMMXT)
-    mach = bfd_mach_arm_iWMMXt;
-  else if (cpu_variant & ARM_CEXT_XSCALE)
-    mach = bfd_mach_arm_XScale;
-  else if (cpu_variant & ARM_CEXT_MAVERICK)
-    mach = bfd_mach_arm_ep9312;
-  else if (cpu_variant & ARM_EXT_V5E)
-    mach = bfd_mach_arm_5TE;
-  else if (cpu_variant & ARM_EXT_V5)
-    {
-      if (cpu_variant & ARM_EXT_V4T)
-	mach = bfd_mach_arm_5T;
-      else
-	mach = bfd_mach_arm_5;
-    }
-  else if (cpu_variant & ARM_EXT_V4)
-    {
-      if (cpu_variant & ARM_EXT_V4T)
-	mach = bfd_mach_arm_4T;
-      else
-	mach = bfd_mach_arm_4;
-    }
-  else if (cpu_variant & ARM_EXT_V3M)
-    mach = bfd_mach_arm_3M;
 
-#if 0 /* Suppressed - for now.  */
-#if defined (OBJ_ELF) || defined (OBJ_COFF)
+      /* Now Inverted ops.  */
+    case OPCODE_MOV:		 /* MOV <-> MVN	 */
+      new_inst = OPCODE_MVN;
+      value = inverted;
+      break;
 
-  /* Create a .note section to fully identify this arm binary.  */
+    case OPCODE_MVN:
+      new_inst = OPCODE_MOV;
+      value = inverted;
+      break;
 
-#define NOTE_ARCH_STRING 	"arch: "
+    case OPCODE_AND:		 /* AND <-> BIC	 */
+      new_inst = OPCODE_BIC;
+      value = inverted;
+      break;
 
-#if defined OBJ_COFF && ! defined NT_VERSION
-#define NT_VERSION  1
-#define NT_ARCH     2
-#endif
-  
-  {
-    segT current_seg = now_seg;
-    subsegT current_subseg = now_subseg;
-    asection * arm_arch;
-    const char * arch_string;
+    case OPCODE_BIC:
+      new_inst = OPCODE_AND;
+      value = inverted;
+      break;
 
-    arm_arch = bfd_make_section_old_way (stdoutput, ARM_NOTE_SECTION);
+    case OPCODE_ADC:		  /* ADC <-> SBC  */
+      new_inst = OPCODE_SBC;
+      value = inverted;
+      break;
 
-#ifdef OBJ_COFF
-    bfd_set_section_flags (stdoutput, arm_arch,
-			   SEC_DATA | SEC_ALLOC | SEC_LOAD | SEC_LINK_ONCE \
-			   | SEC_HAS_CONTENTS);
-#else
-    bfd_set_section_flags (stdoutput, arm_arch,
-			   SEC_READONLY | SEC_HAS_CONTENTS);
-#endif
-    arm_arch->output_section = arm_arch;
-    subseg_set (arm_arch, 0);
+    case OPCODE_SBC:
+      new_inst = OPCODE_ADC;
+      value = inverted;
+      break;
 
-    switch (mach)
-      {
-      default:
-      case bfd_mach_arm_unknown: arch_string = "unknown"; break;
-      case bfd_mach_arm_2:       arch_string = "armv2"; break;
-      case bfd_mach_arm_2a:      arch_string = "armv2a"; break;
-      case bfd_mach_arm_3:       arch_string = "armv3"; break;
-      case bfd_mach_arm_3M:      arch_string = "armv3M"; break;
-      case bfd_mach_arm_4:       arch_string = "armv4"; break;
-      case bfd_mach_arm_4T:      arch_string = "armv4t"; break;
-      case bfd_mach_arm_5:       arch_string = "armv5"; break;
-      case bfd_mach_arm_5T:      arch_string = "armv5t"; break;
-      case bfd_mach_arm_5TE:     arch_string = "armv5te"; break;
-      case bfd_mach_arm_XScale:  arch_string = "XScale"; break;
-      case bfd_mach_arm_ep9312:  arch_string = "ep9312"; break;
-      case bfd_mach_arm_iWMMXt:  arch_string = "iWMMXt"; break;	
-      }
+      /* We cannot do anything.	 */
+    default:
+      return FAIL;
+    }
 
-    arm_add_note (NOTE_ARCH_STRING, arch_string, NT_ARCH);
+  if (value == (unsigned) FAIL)
+    return FAIL;
 
-    subseg_set (current_seg, current_subseg);
-  }
-#endif
-#endif /* Suppressed code.  */
-  
-  bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
+  *instruction &= OPCODE_MASK;
+  *instruction |= new_inst << DATA_OP_SHIFT;
+  return value;
 }
 
-/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
-   for use in the a.out file, and stores them in the array pointed to by buf.
-   This knows about the endian-ness of the target machine and does
-   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
-   2 (short) and 4 (long)  Floating numbers are put out as a series of
-   LITTLENUMS (shorts, here at least).  */
+/* Like negate_data_op, but for Thumb-2.   */
 
-void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+static unsigned int
+thumb32_negate_data_op (offsetT *instruction, offsetT value)
 {
-  if (target_big_endian)
-    number_to_chars_bigendian (buf, val, n);
-  else
-    number_to_chars_littleendian (buf, val, n);
-}
+  int op, new_inst;
+  int rd;
+  offsetT negated, inverted;
 
-static valueT
-md_chars_to_number (buf, n)
-     char * buf;
-     int    n;
-{
-  valueT result = 0;
-  unsigned char * where = (unsigned char *) buf;
+  negated = encode_thumb32_immediate (-value);
+  inverted = encode_thumb32_immediate (~value);
 
-  if (target_big_endian)
-    {
-      while (n--)
-	{
-	  result <<= 8;
-	  result |= (*where++ & 255);
-	}
-    }
-  else
+  rd = (*instruction >> 8) & 0xf;
+  op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
+  switch (op)
     {
-      while (n--)
-	{
-	  result <<= 8;
-	  result |= (where[n] & 255);
-	}
-    }
-
-  return result;
-}
-
-/* Turn a string in input_line_pointer into a floating point constant
-   of type TYPE, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.
+      /* ADD <-> SUB.  Includes CMP <-> CMN.  */
+    case T2_OPCODE_SUB:
+      new_inst = T2_OPCODE_ADD;
+      value = negated;
+      break;
 
-   Note that fp constants aren't represent in the normal way on the ARM.
-   In big endian mode, things are as expected.  However, in little endian
-   mode fp constants are big-endian word-wise, and little-endian byte-wise
-   within the words.  For example, (double) 1.1 in big endian mode is
-   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
-   the byte sequence 99 99 f1 3f 9a 99 99 99.
+    case T2_OPCODE_ADD:
+      new_inst = T2_OPCODE_SUB;
+      value = negated;
+      break;
 
-   ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
+      /* ORR <-> ORN.  Includes MOV <-> MVN.  */
+    case T2_OPCODE_ORR:
+      new_inst = T2_OPCODE_ORN;
+      value = inverted;
+      break;
 
-char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  char *t;
-  int i;
+    case T2_OPCODE_ORN:
+      new_inst = T2_OPCODE_ORR;
+      value = inverted;
+      break;
 
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
+      /* AND <-> BIC.  TST has no inverted equivalent.  */
+    case T2_OPCODE_AND:
+      new_inst = T2_OPCODE_BIC;
+      if (rd == 15)
+	value = FAIL;
+      else
+	value = inverted;
       break;
 
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
+    case T2_OPCODE_BIC:
+      new_inst = T2_OPCODE_AND;
+      value = inverted;
       break;
 
-    case 'x':
-    case 'X':
-      prec = 6;
+      /* ADC <-> SBC  */
+    case T2_OPCODE_ADC:
+      new_inst = T2_OPCODE_SBC;
+      value = inverted;
       break;
 
-    case 'p':
-    case 'P':
-      prec = 6;
+    case T2_OPCODE_SBC:
+      new_inst = T2_OPCODE_ADC;
+      value = inverted;
       break;
 
+      /* We cannot do anything.	 */
     default:
-      *sizeP = 0;
-      return _("bad call to MD_ATOF()");
+      return FAIL;
     }
 
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-  *sizeP = prec * 2;
-
-  if (target_big_endian)
-    {
-      for (i = 0; i < prec; i++)
-	{
-	  md_number_to_chars (litP, (valueT) words[i], 2);
-	  litP += 2;
-	}
-    }
-  else
-    {
-      if (cpu_variant & FPU_ARCH_VFP)
-	for (i = prec - 1; i >= 0; i--)
-	  {
-	    md_number_to_chars (litP, (valueT) words[i], 2);
-	    litP += 2;
-	  }
-      else
-	/* For a 4 byte float the order of elements in `words' is 1 0.
-	   For an 8 byte float the order is 1 0 3 2.  */
-	for (i = 0; i < prec; i += 2)
-	  {
-	    md_number_to_chars (litP, (valueT) words[i + 1], 2);
-	    md_number_to_chars (litP + 2, (valueT) words[i], 2);
-	    litP += 4;
-	  }
-    }
+  if (value == FAIL)
+    return FAIL;
 
-  return 0;
+  *instruction &= T2_OPCODE_MASK;
+  *instruction |= new_inst << T2_DATA_OP_SHIFT;
+  return value;
 }
 
-/* The knowledge of the PC's pipeline offset is built into the insns
-   themselves.  */
-
-long
-md_pcrel_from (fixP)
-     fixS * fixP;
+/* Read a 32-bit thumb instruction from buf.  */
+static unsigned long
+get_thumb32_insn (char * buf)
 {
-  if (fixP->fx_addsy
-      && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
-      && fixP->fx_subsy == NULL)
-    return 0;
-
-  if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
-    {
-      /* PC relative addressing on the Thumb is slightly odd
-	 as the bottom two bits of the PC are forced to zero
-	 for the calculation.  */
-      return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
-    }
-
-#ifdef TE_WINCE
-  /* The pattern was adjusted to accommodate CE's off-by-one fixups,
-     so we un-adjust here to compensate for the accommodation.  */
-  return fixP->fx_where + fixP->fx_frag->fr_address + 8;
-#else
-  return fixP->fx_where + fixP->fx_frag->fr_address;
-#endif
-}
+  unsigned long insn;
+  insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
+  insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
 
-/* Round up a section size to the appropriate boundary.  */
-
-valueT
-md_section_align (segment, size)
-     segT   segment ATTRIBUTE_UNUSED;
-     valueT size;
-{
-#ifdef OBJ_ELF
-  return size;
-#else
-  /* Round all sects to multiple of 4.  */
-  return (size + 3) & ~3;
-#endif
+  return insn;
 }
 
-/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
-   Otherwise we have no need to default values of symbols.  */
 
-symbolS *
-md_undefined_symbol (name)
-     char * name ATTRIBUTE_UNUSED;
+/* We usually want to set the low bit on the address of thumb function
+   symbols.  In particular .word foo - . should have the low bit set.
+   Generic code tries to fold the difference of two symbols to
+   a constant.  Prevent this and force a relocation when the first symbols
+   is a thumb function.  */
+int
+arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
 {
-#ifdef OBJ_ELF
-  if (name[0] == '_' && name[1] == 'G'
-      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
+  if (op == O_subtract
+      && l->X_op == O_symbol
+      && r->X_op == O_symbol
+      && THUMB_IS_FUNC (l->X_add_symbol))
     {
-      if (!GOT_symbol)
-	{
-	  if (symbol_find (name))
-	    as_bad ("GOT already in the symbol table");
-
-	  GOT_symbol = symbol_new (name, undefined_section,
-				   (valueT) 0, & zero_address_frag);
-	}
-
-      return GOT_symbol;
+      l->X_op = O_subtract;
+      l->X_op_symbol = r->X_add_symbol;
+      l->X_add_number -= r->X_add_number;
+      return 1;
     }
-#endif
-
+  /* Process as normal.  */
   return 0;
 }
 
-/* arm_reg_parse () := if it looks like a register, return its token and
-   advance the pointer.  */
-
-static int
-arm_reg_parse (ccp, htab)
-     register char ** ccp;
-     struct hash_control *htab;
-{
-  char * start = * ccp;
-  char   c;
-  char * p;
-  struct reg_entry * reg;
-
-#ifdef REGISTER_PREFIX
-  if (*start != REGISTER_PREFIX)
-    return FAIL;
-  p = start + 1;
-#else
-  p = start;
-#ifdef OPTIONAL_REGISTER_PREFIX
-  if (*p == OPTIONAL_REGISTER_PREFIX)
-    p++, start++;
-#endif
-#endif
-  if (!ISALPHA (*p) || !is_name_beginner (*p))
-    return FAIL;
-
-  c = *p++;
-  while (ISALPHA (c) || ISDIGIT (c) || c == '_')
-    c = *p++;
-
-  *--p = 0;
-  reg = (struct reg_entry *) hash_find (htab, start);
-  *p = c;
-
-  if (reg)
-    {
-      *ccp = p;
-      return reg->number;
-    }
-
-  return FAIL;
-}
-
-/* Search for the following register name in each of the possible reg name
-   tables.  Return the classification if found, or REG_TYPE_MAX if not
-   present.  */
-static enum arm_reg_type
-arm_reg_parse_any (cp)
-     char *cp;
-{
-  int i;
-
-  for (i = (int) REG_TYPE_FIRST; i < (int) REG_TYPE_MAX; i++)
-    if (arm_reg_parse (&cp, all_reg_maps[i].htab) != FAIL)
-      return (enum arm_reg_type) i;
-
-  return REG_TYPE_MAX;
-}
-
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *   fixP;
-     valueT * valP;
-     segT     seg;
+md_apply_fix (fixS *	fixP,
+	       valueT * valP,
+	       segT	seg)
 {
-  offsetT        value = * valP;
-  offsetT        newval;
-  unsigned int   newimm;
-  unsigned long  temp;
-  int            sign;
-  char *         buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-  arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
+  offsetT	 value = * valP;
+  offsetT	 newval;
+  unsigned int	 newimm;
+  unsigned long	 temp;
+  int		 sign;
+  char *	 buf = fixP->fx_where + fixP->fx_frag->fr_literal;
 
-  assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
+  assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
 
   /* Note whether this will delete the relocation.  */
-#if 0
-  /* Patch from REarnshaw to JDavis (disabled for the moment, since it
-     doesn't work fully.)  */
-  if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
-      && !fixP->fx_pcrel)
-#else
   if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
-#endif
     fixP->fx_done = 1;
 
-  /* If this symbol is in a different section then we need to leave it for
-     the linker to deal with.  Unfortunately, md_pcrel_from can't tell,
-     so we have to undo it's effects here.  */
-  if (fixP->fx_pcrel)
-    {
-      if (fixP->fx_addsy != NULL
-	  && S_IS_DEFINED (fixP->fx_addsy)
-	  && S_GET_SEGMENT (fixP->fx_addsy) != seg)
-	{
-	  if (target_oabi
-	      && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
-		  || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
-		  ))
-	    value = 0;
-	  else
-	    value += md_pcrel_from (fixP);
-	}
-    }
+  /* On a 64-bit host, silently truncate 'value' to 32 bits for
+     consistency with the behavior on 32-bit hosts.  Remember value
+     for emit_reloc.  */
+  value &= 0xffffffff;
+  value ^= 0x80000000;
+  value -= 0x80000000; 
 
-  /* Remember value for emit_reloc.  */
+  *valP = value;
   fixP->fx_addnumber = value;
 
+  /* Same treatment for fixP->fx_offset.  */
+  fixP->fx_offset &= 0xffffffff;
+  fixP->fx_offset ^= 0x80000000;
+  fixP->fx_offset -= 0x80000000;
+
   switch (fixP->fx_r_type)
     {
+    case BFD_RELOC_NONE:
+      /* This will need to go in the object file.  */
+      fixP->fx_done = 0;
+      break;
+
     case BFD_RELOC_ARM_IMMEDIATE:
-      newimm = validate_immediate (value);
+      /* We claim that this fixup has been processed here,
+	 even if in fact we generate an error because we do
+	 not have a reloc for it, so tc_gen_reloc will reject it.  */
+      fixP->fx_done = 1;
+
+      if (fixP->fx_addsy
+	  && ! S_IS_DEFINED (fixP->fx_addsy))
+	{
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("undefined symbol %s used as an immediate value"),
+			S_GET_NAME (fixP->fx_addsy));
+	  break;
+	}
+
+      newimm = encode_arm_immediate (value);
       temp = md_chars_to_number (buf, INSN_SIZE);
 
       /* If the instruction will fail, see if we can fix things up by
@@ -12174,7 +11584,6 @@ md_apply_fix3 (fixP, valP, seg)
 
       newimm |= (temp & 0xfffff000);
       md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
-      fixP->fx_done = 1;
       break;
 
     case BFD_RELOC_ARM_ADRL_IMMEDIATE:
@@ -12182,20 +11591,20 @@ md_apply_fix3 (fixP, valP, seg)
 	unsigned int highpart = 0;
 	unsigned int newinsn  = 0xe1a00000; /* nop.  */
 
-	newimm = validate_immediate (value);
+	newimm = encode_arm_immediate (value);
 	temp = md_chars_to_number (buf, INSN_SIZE);
 
 	/* If the instruction will fail, see if we can fix things up by
-	   changing the opcode.  */
+	   changing the opcode.	 */
 	if (newimm == (unsigned int) FAIL
 	    && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
 	  {
 	    /* No ?  OK - try using two ADD instructions to generate
-               the value.  */
+	       the value.  */
 	    newimm = validate_immediate_twopart (value, & highpart);
 
 	    /* Yes - then make sure that the second instruction is
-               also an add.  */
+	       also an add.  */
 	    if (newimm != (unsigned int) FAIL)
 	      newinsn = temp;
 	    /* Still No ?  Try using a negated value.  */
@@ -12227,6 +11636,10 @@ md_apply_fix3 (fixP, valP, seg)
       break;
 
     case BFD_RELOC_ARM_OFFSET_IMM:
+      if (!fixP->fx_done && seg->use_rela_p)
+	value = 0;
+
+    case BFD_RELOC_ARM_LITERAL:
       sign = value >= 0;
 
       if (value < 0)
@@ -12234,9 +11647,13 @@ md_apply_fix3 (fixP, valP, seg)
 
       if (validate_offset_imm (value, 0) == FAIL)
 	{
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("bad immediate value for offset (%ld)"),
-			(long) value);
+	  if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("invalid literal constant: pool needs to be closer"));
+	  else
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("bad immediate value for offset (%ld)"),
+			  (long) value);
 	  break;
 	}
 
@@ -12270,23 +11687,130 @@ md_apply_fix3 (fixP, valP, seg)
       md_number_to_chars (buf, newval, INSN_SIZE);
       break;
 
-    case BFD_RELOC_ARM_LITERAL:
-      sign = value >= 0;
+    case BFD_RELOC_ARM_T32_OFFSET_U8:
+      if (value < 0 || value > 1020 || value % 4 != 0)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("bad immediate value for offset (%ld)"), (long) value);
+      value /= 4;
 
-      if (value < 0)
-	value = - value;
+      newval = md_chars_to_number (buf+2, THUMB_SIZE);
+      newval |= value;
+      md_number_to_chars (buf+2, newval, THUMB_SIZE);
+      break;
 
-      if (validate_offset_imm (value, 0) == FAIL)
+    case BFD_RELOC_ARM_T32_OFFSET_IMM:
+      /* This is a complicated relocation used for all varieties of Thumb32
+	 load/store instruction with immediate offset:
+
+	 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
+	                                           *4, optional writeback(W)
+						   (doubleword load/store)
+
+	 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
+	 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
+	 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
+	 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
+	 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
+
+	 Uppercase letters indicate bits that are already encoded at
+	 this point.  Lowercase letters are our problem.  For the
+	 second block of instructions, the secondary opcode nybble
+	 (bits 8..11) is present, and bit 23 is zero, even if this is
+	 a PC-relative operation.  */
+      newval = md_chars_to_number (buf, THUMB_SIZE);
+      newval <<= 16;
+      newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
+
+      if ((newval & 0xf0000000) == 0xe0000000)
 	{
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("invalid literal constant: pool needs to be closer"));
-	  break;
+	  /* Doubleword load/store: 8-bit offset, scaled by 4.  */
+	  if (value >= 0)
+	    newval |= (1 << 23);
+	  else
+	    value = -value;
+	  if (value % 4 != 0)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset not a multiple of 4"));
+	      break;
+	    }
+	  value /= 4;
+	  if (value > 0xff)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset out of range"));
+	      break;
+	    }
+	  newval &= ~0xff;
+	}
+      else if ((newval & 0x000f0000) == 0x000f0000)
+	{
+	  /* PC-relative, 12-bit offset.  */
+	  if (value >= 0)
+	    newval |= (1 << 23);
+	  else
+	    value = -value;
+	  if (value > 0xfff)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset out of range"));
+	      break;
+	    }
+	  newval &= ~0xfff;
+	}
+      else if ((newval & 0x00000100) == 0x00000100)
+	{
+	  /* Writeback: 8-bit, +/- offset.  */
+	  if (value >= 0)
+	    newval |= (1 << 9);
+	  else
+	    value = -value;
+	  if (value > 0xff)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset out of range"));
+	      break;
+	    }
+	  newval &= ~0xff;
+	}
+      else if ((newval & 0x00000f00) == 0x00000e00)
+	{
+	  /* T-instruction: positive 8-bit offset.  */
+	  if (value < 0 || value > 0xff)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset out of range"));
+	      break;
+	    }
+	  newval &= ~0xff;
+	  newval |= value;
+	}
+      else
+	{
+	  /* Positive 12-bit or negative 8-bit offset.  */
+	  int limit;
+	  if (value >= 0)
+	    {
+	      newval |= (1 << 23);
+	      limit = 0xfff;
+	    }
+	  else
+	    {
+	      value = -value;
+	      limit = 0xff;
+	    }
+	  if (value > limit)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("offset out of range"));
+	      break;
+	    }
+	  newval &= ~limit;
 	}
 
-      newval = md_chars_to_number (buf, INSN_SIZE);
-      newval &= 0xff7ff000;
-      newval |= value | (sign ? INDEX_UP : 0);
-      md_number_to_chars (buf, newval, INSN_SIZE);
+      newval |= value;
+      md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
+      md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
       break;
 
     case BFD_RELOC_ARM_SHIFT_IMM:
@@ -12301,7 +11825,7 @@ md_apply_fix3 (fixP, valP, seg)
 	}
 
       if (value == 0)
-	/* Shifts of zero must be done as lsl.  */
+	/* Shifts of zero must be done as lsl.	*/
 	newval &= ~0x60;
       else if (value == 32)
 	value = 0;
@@ -12310,13 +11834,80 @@ md_apply_fix3 (fixP, valP, seg)
       md_number_to_chars (buf, newval, INSN_SIZE);
       break;
 
+    case BFD_RELOC_ARM_T32_IMMEDIATE:
+    case BFD_RELOC_ARM_T32_IMM12:
+    case BFD_RELOC_ARM_T32_ADD_PC12:
+      /* We claim that this fixup has been processed here,
+	 even if in fact we generate an error because we do
+	 not have a reloc for it, so tc_gen_reloc will reject it.  */
+      fixP->fx_done = 1;
+
+      if (fixP->fx_addsy
+	  && ! S_IS_DEFINED (fixP->fx_addsy))
+	{
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("undefined symbol %s used as an immediate value"),
+			S_GET_NAME (fixP->fx_addsy));
+	  break;
+	}
+
+      newval = md_chars_to_number (buf, THUMB_SIZE);
+      newval <<= 16;
+      newval |= md_chars_to_number (buf+2, THUMB_SIZE);
+
+      /* FUTURE: Implement analogue of negate_data_op for T32.  */
+      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
+	{
+	  newimm = encode_thumb32_immediate (value);
+	  if (newimm == (unsigned int) FAIL)
+	    newimm = thumb32_negate_data_op (&newval, value);
+	}
+      else
+	{
+	  /* 12 bit immediate for addw/subw.  */
+	  if (value < 0)
+	    {
+	      value = -value;
+	      newval ^= 0x00a00000;
+	    }
+	  if (value > 0xfff)
+	    newimm = (unsigned int) FAIL;
+	  else
+	    newimm = value;
+	}
+
+      if (newimm == (unsigned int)FAIL)
+	{
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("invalid constant (%lx) after fixup"),
+			(unsigned long) value);
+	  break;
+	}
+
+      newval |= (newimm & 0x800) << 15;
+      newval |= (newimm & 0x700) << 4;
+      newval |= (newimm & 0x0ff);
+
+      md_number_to_chars (buf,   (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
+      md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
+      break;
+
+    case BFD_RELOC_ARM_SMC:
+      if (((unsigned long) value) > 0xffff)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("invalid smc expression"));
+      newval = md_chars_to_number (buf, INSN_SIZE);
+      newval |= (value & 0xf) | ((value & 0xfff0) << 4);
+      md_number_to_chars (buf, newval, INSN_SIZE);
+      break;
+
     case BFD_RELOC_ARM_SWI:
-      if (arm_data->thumb_mode)
+      if (fixP->tc_fix_data != 0)
 	{
 	  if (((unsigned long) value) > 0xff)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid swi expression"));
-	  newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
+	  newval = md_chars_to_number (buf, THUMB_SIZE);
 	  newval |= value;
 	  md_number_to_chars (buf, newval, THUMB_SIZE);
 	}
@@ -12325,7 +11916,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  if (((unsigned long) value) > 0x00ffffff)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid swi expression"));
-	  newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
+	  newval = md_chars_to_number (buf, INSN_SIZE);
 	  newval |= value;
 	  md_number_to_chars (buf, newval, INSN_SIZE);
 	}
@@ -12339,224 +11930,257 @@ md_apply_fix3 (fixP, valP, seg)
       md_number_to_chars (buf, newval, INSN_SIZE);
       break;
 
-    case BFD_RELOC_ARM_PCREL_BRANCH:
+#ifdef OBJ_ELF
+    case BFD_RELOC_ARM_PCREL_CALL:
       newval = md_chars_to_number (buf, INSN_SIZE);
+      if ((newval & 0xf0000000) == 0xf0000000)
+	temp = 1;
+      else
+	temp = 3;
+      goto arm_branch_common;
 
-      /* Sign-extend a 24-bit number.  */
-#define SEXT24(x)	((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
-
-#ifdef OBJ_ELF
-      if (! target_oabi)
-	value = fixP->fx_offset;
+    case BFD_RELOC_ARM_PCREL_JUMP:
+    case BFD_RELOC_ARM_PLT32:
 #endif
+    case BFD_RELOC_ARM_PCREL_BRANCH:
+      temp = 3;
+      goto arm_branch_common;
 
+    case BFD_RELOC_ARM_PCREL_BLX:
+      temp = 1;
+    arm_branch_common:
       /* We are going to store value (shifted right by two) in the
-	 instruction, in a 24 bit, signed field.  Thus we need to check
-	 that none of the top 8 bits of the shifted value (top 7 bits of
-         the unshifted, unsigned value) are set, or that they are all set.  */
-      if ((value & ~ ((offsetT) 0x1ffffff)) != 0
-	  && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
+	 instruction, in a 24 bit, signed field.  Bits 26 through 32 either
+	 all clear or all set and bit 0 must be clear.  For B/BL bit 1 must
+	 also be be clear.  */
+      if (value & temp)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("misaligned branch destination"));
+      if ((value & (offsetT)0xfe000000) != (offsetT)0
+	  && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch out of range"));
+
+      if (fixP->fx_done || !seg->use_rela_p)
 	{
-#ifdef OBJ_ELF
-	  /* Normally we would be stuck at this point, since we cannot store
-	     the absolute address that is the destination of the branch in the
-	     24 bits of the branch instruction.  If however, we happen to know
-	     that the destination of the branch is in the same section as the
-	     branch instruction itself, then we can compute the relocation for
-	     ourselves and not have to bother the linker with it.
-
-	     FIXME: The tests for OBJ_ELF and ! target_oabi are only here
-	     because I have not worked out how to do this for OBJ_COFF or
-	     target_oabi.  */
-	  if (! target_oabi
-	      && fixP->fx_addsy != NULL
-	      && S_IS_DEFINED (fixP->fx_addsy)
-	      && S_GET_SEGMENT (fixP->fx_addsy) == seg)
+	  newval = md_chars_to_number (buf, INSN_SIZE);
+	  newval |= (value >> 2) & 0x00ffffff;
+	  /* Set the H bit on BLX instructions.  */
+	  if (temp == 1)
 	    {
-	      /* Get pc relative value to go into the branch.  */
-	      value = * valP;
-
-	      /* Permit a backward branch provided that enough bits
-		 are set.  Allow a forwards branch, provided that
-		 enough bits are clear.  */
-	      if (   (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
-		  || (value & ~ ((offsetT) 0x1ffffff)) == 0)
-		fixP->fx_done = 1;
+	      if (value & 2)
+		newval |= 0x01000000;
+	      else
+		newval &= ~0x01000000;
 	    }
-
-	  if (! fixP->fx_done)
-#endif
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("GAS can't handle same-section branch dest >= 0x04000000"));
+	  md_number_to_chars (buf, newval, INSN_SIZE);
 	}
+      break;
 
-      value >>= 2;
-      value += SEXT24 (newval);
-
-      if (    (value & ~ ((offsetT) 0xffffff)) != 0
-	  && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
+    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
+      /* CZB can only branch forward.  */
+      if (value & ~0x7e)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("out of range branch"));
+		      _("branch out of range"));
 
-      newval = (value & 0x00ffffff) | (newval & 0xff000000);
-      md_number_to_chars (buf, newval, INSN_SIZE);
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  newval = md_chars_to_number (buf, THUMB_SIZE);
+	  newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	}
       break;
 
-    case BFD_RELOC_ARM_PCREL_BLX:
-      {
-	offsetT hbit;
-	newval = md_chars_to_number (buf, INSN_SIZE);
+    case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.	*/
+      if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch out of range"));
 
-#ifdef OBJ_ELF
-	if (! target_oabi)
-	  value = fixP->fx_offset;
-#endif
-	hbit   = (value >> 1) & 1;
-	value  = (value >> 2) & 0x00ffffff;
-	value  = (value + (newval & 0x00ffffff)) & 0x00ffffff;
-	newval = value | (newval & 0xfe000000) | (hbit << 24);
-	md_number_to_chars (buf, newval, INSN_SIZE);
-      }
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  newval = md_chars_to_number (buf, THUMB_SIZE);
+	  newval |= (value & 0x1ff) >> 1;
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	}
       break;
 
-    case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.  */
-      newval = md_chars_to_number (buf, THUMB_SIZE);
-      {
-	addressT diff = (newval & 0xff) << 1;
-	if (diff & 0x100)
-	  diff |= ~0xff;
+    case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch.  */
+      if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch out of range"));
 
-	value += diff;
-	if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("branch out of range"));
-	newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
-      }
-      md_number_to_chars (buf, newval, THUMB_SIZE);
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  newval = md_chars_to_number (buf, THUMB_SIZE);
+	  newval |= (value & 0xfff) >> 1;
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	}
       break;
 
-    case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch.  */
-      newval = md_chars_to_number (buf, THUMB_SIZE);
-      {
-	addressT diff = (newval & 0x7ff) << 1;
-	if (diff & 0x800)
-	  diff |= ~0x7ff;
+    case BFD_RELOC_THUMB_PCREL_BRANCH20:
+      if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("conditional branch out of range"));
 
-	value += diff;
-	if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("branch out of range"));
-	newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
-      }
-      md_number_to_chars (buf, newval, THUMB_SIZE);
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  offsetT newval2;
+	  addressT S, J1, J2, lo, hi;
+
+	  S  = (value & 0x00100000) >> 20;
+	  J2 = (value & 0x00080000) >> 19;
+	  J1 = (value & 0x00040000) >> 18;
+	  hi = (value & 0x0003f000) >> 12;
+	  lo = (value & 0x00000ffe) >> 1;
+
+	  newval   = md_chars_to_number (buf, THUMB_SIZE);
+	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+	  newval  |= (S << 10) | hi;
+	  newval2 |= (J1 << 13) | (J2 << 11) | lo;
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
+	}
       break;
 
     case BFD_RELOC_THUMB_PCREL_BLX:
     case BFD_RELOC_THUMB_PCREL_BRANCH23:
-      {
-	offsetT newval2;
-	addressT diff;
-
-	newval  = md_chars_to_number (buf, THUMB_SIZE);
-	newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
-	diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
-	if (diff & 0x400000)
-	  diff |= ~0x3fffff;
-#ifdef OBJ_ELF
-	value = fixP->fx_offset;
-#endif
-	value += diff;
+      if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch out of range"));
 
-	if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("branch with link out of range"));
-
-	newval  = (newval  & 0xf800) | ((value & 0x7fffff) >> 12);
-	newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
-	if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
-	  /* For a BLX instruction, make sure that the relocation is rounded up
-	     to a word boundary.  This follows the semantics of the instruction
-	     which specifies that bit 1 of the target address will come from bit
-	     1 of the base address.  */
-	  newval2 = (newval2 + 1) & ~ 1;
-	md_number_to_chars (buf, newval, THUMB_SIZE);
-	md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
-      }
+      if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
+	/* For a BLX instruction, make sure that the relocation is rounded up
+	   to a word boundary.  This follows the semantics of the instruction
+	   which specifies that bit 1 of the target address will come from bit
+	   1 of the base address.  */
+	value = (value + 1) & ~ 1;
+
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  offsetT newval2;
+
+	  newval   = md_chars_to_number (buf, THUMB_SIZE);
+	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+	  newval  |= (value & 0x7fffff) >> 12;
+	  newval2 |= (value & 0xfff) >> 1;
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
+	}
       break;
 
-    case BFD_RELOC_8:
-      if (fixP->fx_done || fixP->fx_pcrel)
-	md_number_to_chars (buf, value, 1);
-#ifdef OBJ_ELF
-      else if (!target_oabi)
+    case BFD_RELOC_THUMB_PCREL_BRANCH25:
+      if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("branch out of range"));
+
+      if (fixP->fx_done || !seg->use_rela_p)
 	{
-	  value = fixP->fx_offset;
-	  md_number_to_chars (buf, value, 1);
+	  offsetT newval2;
+	  addressT S, I1, I2, lo, hi;
+
+	  S  = (value & 0x01000000) >> 24;
+	  I1 = (value & 0x00800000) >> 23;
+	  I2 = (value & 0x00400000) >> 22;
+	  hi = (value & 0x003ff000) >> 12;
+	  lo = (value & 0x00000ffe) >> 1;
+
+	  I1 = !(I1 ^ S);
+	  I2 = !(I2 ^ S);
+
+	  newval   = md_chars_to_number (buf, THUMB_SIZE);
+	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
+	  newval  |= (S << 10) | hi;
+	  newval2 |= (I1 << 13) | (I2 << 11) | lo;
+	  md_number_to_chars (buf, newval, THUMB_SIZE);
+	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
 	}
-#endif
+      break;
+
+    case BFD_RELOC_8:
+      if (fixP->fx_done || !seg->use_rela_p)
+	md_number_to_chars (buf, value, 1);
       break;
 
     case BFD_RELOC_16:
-      if (fixP->fx_done || fixP->fx_pcrel)
+      if (fixP->fx_done || !seg->use_rela_p)
 	md_number_to_chars (buf, value, 2);
-#ifdef OBJ_ELF
-      else if (!target_oabi)
-	{
-	  value = fixP->fx_offset;
-	  md_number_to_chars (buf, value, 2);
-	}
-#endif
       break;
 
 #ifdef OBJ_ELF
+    case BFD_RELOC_ARM_TLS_GD32:
+    case BFD_RELOC_ARM_TLS_LE32:
+    case BFD_RELOC_ARM_TLS_IE32:
+    case BFD_RELOC_ARM_TLS_LDM32:
+    case BFD_RELOC_ARM_TLS_LDO32:
+      S_SET_THREAD_LOCAL (fixP->fx_addsy);
+      /* fall through */
+
     case BFD_RELOC_ARM_GOT32:
     case BFD_RELOC_ARM_GOTOFF:
-      md_number_to_chars (buf, 0, 4);
+    case BFD_RELOC_ARM_TARGET2:
+      if (fixP->fx_done || !seg->use_rela_p)
+	md_number_to_chars (buf, 0, 4);
       break;
 #endif
 
     case BFD_RELOC_RVA:
     case BFD_RELOC_32:
-      if (fixP->fx_done || fixP->fx_pcrel)
+    case BFD_RELOC_ARM_TARGET1:
+    case BFD_RELOC_ARM_ROSEGREL32:
+    case BFD_RELOC_ARM_SBREL32:
+    case BFD_RELOC_32_PCREL:
+      if (fixP->fx_done || !seg->use_rela_p)
 	md_number_to_chars (buf, value, 4);
-#ifdef OBJ_ELF
-      else if (!target_oabi)
-	{
-	  value = fixP->fx_offset;
-	  md_number_to_chars (buf, value, 4);
-	}
-#endif
       break;
 
 #ifdef OBJ_ELF
-    case BFD_RELOC_ARM_PLT32:
-      /* It appears the instruction is fully prepared at this point.  */
+    case BFD_RELOC_ARM_PREL31:
+      if (fixP->fx_done || !seg->use_rela_p)
+	{
+	  newval = md_chars_to_number (buf, 4) & 0x80000000;
+	  if ((value ^ (value >> 1)) & 0x40000000)
+	    {
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("rel31 relocation overflow"));
+	    }
+	  newval |= value & 0x7fffffff;
+	  md_number_to_chars (buf, newval, 4);
+	}
       break;
 #endif
 
     case BFD_RELOC_ARM_CP_OFF_IMM:
-      sign = value >= 0;
+    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
       if (value < -1023 || value > 1023 || (value & 3))
 	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("illegal value for co-processor offset"));
+		      _("co-processor offset out of range"));
+    cp_off_common:
+      sign = value >= 0;
       if (value < 0)
 	value = -value;
-      newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
+      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
+	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
+	newval = md_chars_to_number (buf, INSN_SIZE);
+      else
+	newval = get_thumb32_insn (buf);
+      newval &= 0xff7fff00;
       newval |= (value >> 2) | (sign ? INDEX_UP : 0);
-      md_number_to_chars (buf, newval, INSN_SIZE);
+      if (value == 0)
+	newval &= ~WRITE_BACK;
+      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
+	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
+	md_number_to_chars (buf, newval, INSN_SIZE);
+      else
+	put_thumb32_insn (buf, newval);
       break;
 
     case BFD_RELOC_ARM_CP_OFF_IMM_S2:
-      sign = value >= 0;
+    case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
       if (value < -255 || value > 255)
-        as_bad_where (fixP->fx_file, fixP->fx_line,
-                      _("Illegal value for co-processor offset"));
-      if (value < 0)
-        value = -value;
-      newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
-      newval |= value | (sign ?  INDEX_UP : 0);
-      md_number_to_chars (buf, newval , INSN_SIZE);
-      break;
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("co-processor offset out of range"));
+      value *= 4;
+      goto cp_off_common;
 
     case BFD_RELOC_ARM_THUMB_OFFSET:
       newval = md_chars_to_number (buf, THUMB_SIZE);
@@ -12567,24 +12191,21 @@ md_apply_fix3 (fixP, valP, seg)
 	{
 	case 4: /* PC load.  */
 	  /* Thumb PC loads are somewhat odd, bit 1 of the PC is
-	     forced to zero for these loads, so we will need to round
-	     up the offset if the instruction address is not word
-	     aligned (since the final address produced must be, and
-	     we can only describe word-aligned immediate offsets).  */
-
-	  if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
+	     forced to zero for these loads; md_pcrel_from has already
+	     compensated for this.  */
+	  if (value & 3)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("invalid offset, target not word aligned (0x%08X)"),
-			  (unsigned int) (fixP->fx_frag->fr_address
-					  + fixP->fx_where + value));
+			  _("invalid offset, target not word aligned (0x%08lX)"),
+			  (((unsigned long) fixP->fx_frag->fr_address
+			    + (unsigned long) fixP->fx_where) & ~3)
+			  + (unsigned long) value);
 
-	  if ((value + 2) & ~0x3fe)
+	  if (value & ~0x3fc)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid offset, value too big (0x%08lX)"),
 			  (long) value);
 
-	  /* Round up, since pc will be rounded down.  */
-	  newval |= (value + 2) >> 2;
+	  newval |= value >> 2;
 	  break;
 
 	case 9: /* SP load/store.  */
@@ -12611,7 +12232,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  newval |= value << 6;
 	  break;
 
-	case 8: /* Halfword load/store.  */
+	case 8: /* Halfword load/store.	 */
 	  if (value & ~0x3e)
 	    as_bad_where (fixP->fx_file, fixP->fx_line,
 			  _("invalid offset, value too big (0x%08lX)"),
@@ -12630,15 +12251,15 @@ md_apply_fix3 (fixP, valP, seg)
 
     case BFD_RELOC_ARM_THUMB_ADD:
       /* This is a complicated relocation, since we use it for all of
-         the following immediate relocations:
+	 the following immediate relocations:
 
 	    3bit ADD/SUB
 	    8bit ADD/SUB
 	    9bit ADD/SUB SP word-aligned
 	   10bit ADD PC/SP word-aligned
 
-         The type of instruction being processed is encoded in the
-         instruction field:
+	 The type of instruction being processed is encoded in the
+	 instruction field:
 
 	   0x8000  SUB
 	   0x00F0  Rd
@@ -12648,7 +12269,24 @@ md_apply_fix3 (fixP, valP, seg)
       {
 	int rd = (newval >> 4) & 0xf;
 	int rs = newval & 0xf;
-	int subtract = newval & 0x8000;
+	int subtract = !!(newval & 0x8000);
+
+	/* Check for HI regs, only very restricted cases allowed:
+	   Adjusting SP, and using PC or SP to get an address.	*/
+	if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
+	    || (rs > 7 && rs != REG_SP && rs != REG_PC))
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("invalid Hi register with immediate"));
+
+	/* If value is negative, choose the opposite instruction.  */
+	if (value < 0)
+	  {
+	    value = -value;
+	    subtract = !subtract;
+	    if (value < 0)
+	      as_bad_where (fixP->fx_file, fixP->fx_line,
+			    _("immediate value out of range"));
+	  }
 
 	if (rd == REG_SP)
 	  {
@@ -12660,8 +12298,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  }
 	else if (rs == REG_PC || rs == REG_SP)
 	  {
-	    if (subtract ||
-		value & ~0x3fc)
+	    if (subtract || value & ~0x3fc)
 	      as_bad_where (fixP->fx_file, fixP->fx_line,
 			    _("invalid immediate for address calculation (value = 0x%08lX)"),
 			    (unsigned long) value);
@@ -12673,7 +12310,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  {
 	    if (value & ~0xff)
 	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("invalid 8bit immediate"));
+			    _("immediate value out of range"));
 	    newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
 	    newval |= (rd << 8) | value;
 	  }
@@ -12681,7 +12318,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  {
 	    if (value & ~0x7)
 	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("invalid 3bit immediate"));
+			    _("immediate value out of range"));
 	    newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
 	    newval |= rd | (rs << 3) | (value << 6);
 	  }
@@ -12691,29 +12328,27 @@ md_apply_fix3 (fixP, valP, seg)
 
     case BFD_RELOC_ARM_THUMB_IMM:
       newval = md_chars_to_number (buf, THUMB_SIZE);
-      switch (newval >> 11)
-	{
-	case 0x04: /* 8bit immediate MOV.  */
-	case 0x05: /* 8bit immediate CMP.  */
-	  if (value < 0 || value > 255)
-	    as_bad_where (fixP->fx_file, fixP->fx_line,
-			  _("invalid immediate: %ld is too large"),
-			  (long) value);
-	  newval |= value;
-	  break;
-
-	default:
-	  abort ();
-	}
+      if (value < 0 || value > 255)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("invalid immediate: %ld is too large"),
+		      (long) value);
+      newval |= value;
       md_number_to_chars (buf, newval, THUMB_SIZE);
       break;
 
     case BFD_RELOC_ARM_THUMB_SHIFT:
-      /* 5bit shift value (0..31).  */
-      if (value < 0 || value > 31)
+      /* 5bit shift value (0..32).  LSL cannot take 32.	 */
+      newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
+      temp = newval & 0xf800;
+      if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
 	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("illegal Thumb shift value: %ld"), (long) value);
-      newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
+		      _("invalid shift value: %ld"), (long) value);
+      /* Shifts of zero must be encoded as LSL.	 */
+      if (value == 0)
+	newval = (newval & 0x003f) | T_OPCODE_LSL_I;
+      /* Shifts of 32 are encoded as zero.  */
+      else if (value == 32)
+	value = 0;
       newval |= value << 6;
       md_number_to_chars (buf, newval, THUMB_SIZE);
       break;
@@ -12723,7 +12358,7 @@ md_apply_fix3 (fixP, valP, seg)
       fixP->fx_done = 0;
       return;
 
-    case BFD_RELOC_NONE:
+    case BFD_RELOC_UNUSED:
     default:
       as_bad_where (fixP->fx_file, fixP->fx_line,
 		    _("bad relocation fixup type (%d)"), fixP->fx_r_type);
@@ -12734,28 +12369,25 @@ md_apply_fix3 (fixP, valP, seg)
    format.  */
 
 arelent *
-tc_gen_reloc (section, fixp)
-     asection * section ATTRIBUTE_UNUSED;
-     fixS * fixp;
+tc_gen_reloc (asection *section, fixS *fixp)
 {
   arelent * reloc;
   bfd_reloc_code_real_type code;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
-  /* @@ Why fx_addnumber sometimes and fx_offset other times?  */
-#ifndef OBJ_ELF
-  if (fixp->fx_pcrel == 0)
-    reloc->addend = fixp->fx_offset;
-  else
-    reloc->addend = fixp->fx_offset = reloc->address;
-#else  /* OBJ_ELF */
+  if (fixp->fx_pcrel)
+    {
+      if (section->use_rela_p)
+	fixp->fx_offset -= md_pcrel_from_section (fixp, section);
+      else
+	fixp->fx_offset = reloc->address;
+    }
   reloc->addend = fixp->fx_offset;
-#endif
 
   switch (fixp->fx_r_type)
     {
@@ -12780,12 +12412,16 @@ tc_gen_reloc (section, fixp)
 	  break;
 	}
 
+    case BFD_RELOC_NONE:
     case BFD_RELOC_ARM_PCREL_BRANCH:
     case BFD_RELOC_ARM_PCREL_BLX:
     case BFD_RELOC_RVA:
+    case BFD_RELOC_THUMB_PCREL_BRANCH7:
     case BFD_RELOC_THUMB_PCREL_BRANCH9:
     case BFD_RELOC_THUMB_PCREL_BRANCH12:
+    case BFD_RELOC_THUMB_PCREL_BRANCH20:
     case BFD_RELOC_THUMB_PCREL_BRANCH23:
+    case BFD_RELOC_THUMB_PCREL_BRANCH25:
     case BFD_RELOC_THUMB_PCREL_BLX:
     case BFD_RELOC_VTABLE_ENTRY:
     case BFD_RELOC_VTABLE_INHERIT:
@@ -12804,6 +12440,25 @@ tc_gen_reloc (section, fixp)
     case BFD_RELOC_ARM_GOT32:
     case BFD_RELOC_ARM_GOTOFF:
     case BFD_RELOC_ARM_PLT32:
+    case BFD_RELOC_ARM_TARGET1:
+    case BFD_RELOC_ARM_ROSEGREL32:
+    case BFD_RELOC_ARM_SBREL32:
+    case BFD_RELOC_ARM_PREL31:
+    case BFD_RELOC_ARM_TARGET2:
+    case BFD_RELOC_ARM_TLS_LE32:
+    case BFD_RELOC_ARM_TLS_LDO32:
+    case BFD_RELOC_ARM_PCREL_CALL:
+    case BFD_RELOC_ARM_PCREL_JUMP:
+      code = fixp->fx_r_type;
+      break;
+
+    case BFD_RELOC_ARM_TLS_GD32:
+    case BFD_RELOC_ARM_TLS_IE32:
+    case BFD_RELOC_ARM_TLS_LDM32:
+      /* BFD will include the symbol's address in the addend.
+	 But we don't want that, so subtract it out again here.  */
+      if (!S_IS_COMMON (fixp->fx_addsy))
+	reloc->addend -= (*reloc->sym_ptr_ptr)->value;
       code = fixp->fx_r_type;
       break;
 #endif
@@ -12819,6 +12474,12 @@ tc_gen_reloc (section, fixp)
       return NULL;
 
     case BFD_RELOC_ARM_OFFSET_IMM:
+      if (section->use_rela_p)
+	{
+	  code = fixp->fx_r_type;
+	  break;
+	}
+
       if (fixp->fx_addsy != NULL
 	  && !S_IS_DEFINED (fixp->fx_addsy)
 	  && S_IS_LOCAL (fixp->fx_addsy))
@@ -12839,16 +12500,19 @@ tc_gen_reloc (section, fixp)
 
 	switch (fixp->fx_r_type)
 	  {
+	  case BFD_RELOC_NONE:		   type = "NONE";	  break;
 	  case BFD_RELOC_ARM_OFFSET_IMM8:  type = "OFFSET_IMM8";  break;
-	  case BFD_RELOC_ARM_SHIFT_IMM:    type = "SHIFT_IMM";    break;
-	  case BFD_RELOC_ARM_SWI:          type = "SWI";          break;
-	  case BFD_RELOC_ARM_MULTI:        type = "MULTI";        break;
-	  case BFD_RELOC_ARM_CP_OFF_IMM:   type = "CP_OFF_IMM";   break;
-	  case BFD_RELOC_ARM_THUMB_ADD:    type = "THUMB_ADD";    break;
+	  case BFD_RELOC_ARM_SHIFT_IMM:	   type = "SHIFT_IMM";	  break;
+	  case BFD_RELOC_ARM_SMC:	   type = "SMC";	  break;
+	  case BFD_RELOC_ARM_SWI:	   type = "SWI";	  break;
+	  case BFD_RELOC_ARM_MULTI:	   type = "MULTI";	  break;
+	  case BFD_RELOC_ARM_CP_OFF_IMM:   type = "CP_OFF_IMM";	  break;
+	  case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
+	  case BFD_RELOC_ARM_THUMB_ADD:	   type = "THUMB_ADD";	  break;
 	  case BFD_RELOC_ARM_THUMB_SHIFT:  type = "THUMB_SHIFT";  break;
-	  case BFD_RELOC_ARM_THUMB_IMM:    type = "THUMB_IMM";    break;
+	  case BFD_RELOC_ARM_THUMB_IMM:	   type = "THUMB_IMM";	  break;
 	  case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
-	  default:                         type = _("<unknown>"); break;
+	  default:			   type = _("<unknown>"); break;
 	  }
 	as_bad_where (fixp->fx_file, fixp->fx_line,
 		      _("cannot represent %s relocation in this object file format"),
@@ -12885,154 +12549,487 @@ tc_gen_reloc (section, fixp)
   return reloc;
 }
 
-int
-md_estimate_size_before_relax (fragP, segtype)
-     fragS * fragP ATTRIBUTE_UNUSED;
-     segT    segtype ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("md_estimate_size_before_relax\n"));
-  return 1;
-}
+/* This fix_new is called by cons via TC_CONS_FIX_NEW.	*/
 
-static void
-output_inst (str)
-     const char *str;
+void
+cons_fix_new_arm (fragS *	frag,
+		  int		where,
+		  int		size,
+		  expressionS * exp)
 {
-  char * to = NULL;
+  bfd_reloc_code_real_type type;
+  int pcrel = 0;
 
-  if (inst.error)
+  /* Pick a reloc.
+     FIXME: @@ Should look at CPU word size.  */
+  switch (size)
     {
-      as_bad ("%s -- `%s'", inst.error, str);
-      return;
+    case 1:
+      type = BFD_RELOC_8;
+      break;
+    case 2:
+      type = BFD_RELOC_16;
+      break;
+    case 4:
+    default:
+      type = BFD_RELOC_32;
+      break;
+    case 8:
+      type = BFD_RELOC_64;
+      break;
     }
 
-  to = frag_more (inst.size);
+  fix_new_exp (frag, where, (int) size, exp, pcrel, type);
+}
 
-  if (thumb_mode && (inst.size > THUMB_SIZE))
-    {
-      assert (inst.size == (2 * THUMB_SIZE));
-      md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
-      md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
-    }
-  else if (inst.size > INSN_SIZE)
+#if defined OBJ_COFF || defined OBJ_ELF
+void
+arm_validate_fix (fixS * fixP)
+{
+  /* If the destination of the branch is a defined symbol which does not have
+     the THUMB_FUNC attribute, then we must be calling a function which has
+     the (interfacearm) attribute.  We look for the Thumb entry point to that
+     function and change the branch to refer to that function instead.	*/
+  if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
+      && fixP->fx_addsy != NULL
+      && S_IS_DEFINED (fixP->fx_addsy)
+      && ! THUMB_IS_FUNC (fixP->fx_addsy))
     {
-      assert (inst.size == (2 * INSN_SIZE));
-      md_number_to_chars (to, inst.instruction, INSN_SIZE);
-      md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
+      fixP->fx_addsy = find_real_start (fixP->fx_addsy);
     }
-  else
-    md_number_to_chars (to, inst.instruction, inst.size);
+}
+#endif
 
-  if (inst.reloc.type != BFD_RELOC_NONE)
-    fix_new_arm (frag_now, to - frag_now->fr_literal,
-		 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
-		 inst.reloc.type);
+int
+arm_force_relocation (struct fix * fixp)
+{
+#if defined (OBJ_COFF) && defined (TE_PE)
+  if (fixp->fx_r_type == BFD_RELOC_RVA)
+    return 1;
+#endif
+
+  /* Resolve these relocations even if the symbol is extern or weak.  */
+  if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
+      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
+    return 0;
+
+  return generic_force_reloc (fixp);
+}
+
+#ifdef OBJ_COFF
+/* This is a little hack to help the gas/arm/adrl.s test.  It prevents
+   local labels from being added to the output symbol table when they
+   are used with the ADRL pseudo op.  The ADRL relocation should always
+   be resolved before the binbary is emitted, so it is safe to say that
+   it is adjustable.  */
+
+bfd_boolean
+arm_fix_adjustable (fixS * fixP)
+{
+  if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+    return 1;
+  return 0;
+}
+#endif
 
 #ifdef OBJ_ELF
-  dwarf2_emit_insn (inst.size);
+/* Relocations against Thumb function names must be left unadjusted,
+   so that the linker can use this information to correctly set the
+   bottom bit of their addresses.  The MIPS version of this function
+   also prevents relocations that are mips-16 specific, but I do not
+   know why it does this.
+
+   FIXME:
+   There is one other problem that ought to be addressed here, but
+   which currently is not:  Taking the address of a label (rather
+   than a function) and then later jumping to that address.  Such
+   addresses also ought to have their bottom bit set (assuming that
+   they reside in Thumb code), but at the moment they will not.	 */
+
+bfd_boolean
+arm_fix_adjustable (fixS * fixP)
+{
+  if (fixP->fx_addsy == NULL)
+    return 1;
+
+  if (THUMB_IS_FUNC (fixP->fx_addsy)
+      && fixP->fx_subsy == NULL)
+    return 0;
+
+  /* We need the symbol name for the VTABLE entries.  */
+  if (	 fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+    return 0;
+
+  /* Don't allow symbols to be discarded on GOT related relocs.	 */
+  if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
+      || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
+      || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
+      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
+      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
+      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
+      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
+      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
+      || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
+    return 0;
+
+  return 1;
+}
+
+const char *
+elf32_arm_target_format (void)
+{
+#ifdef TE_SYMBIAN
+  return (target_big_endian
+	  ? "elf32-bigarm-symbian"
+	  : "elf32-littlearm-symbian");
+#elif defined (TE_VXWORKS)
+  return (target_big_endian
+	  ? "elf32-bigarm-vxworks"
+	  : "elf32-littlearm-vxworks");
+#else
+  if (target_big_endian)
+    return "elf32-bigarm";
+  else
+    return "elf32-littlearm";
 #endif
 }
 
 void
-md_assemble (str)
-     char * str;
+armelf_frob_symbol (symbolS * symp,
+		    int *     puntp)
 {
-  char  c;
-  char *p;
-  char *start;
-
-  /* Align the instruction.
-     This may not be the right thing to do but ...  */
-#if 0
-  arm_align (2, 0);
+  elf_frob_symbol (symp, puntp);
+}
 #endif
 
-  /* Align the previous label if needed.  */
-  if (last_label_seen != NULL)
-    {
-      symbol_set_frag (last_label_seen, frag_now);
-      S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
-      S_SET_SEGMENT (last_label_seen, now_seg);
-    }
-
-  memset (&inst, '\0', sizeof (inst));
-  inst.reloc.type = BFD_RELOC_NONE;
+/* MD interface: Finalization.	*/
 
-  skip_whitespace (str);
+/* A good place to do this, although this was probably not intended
+   for this kind of use.  We need to dump the literal pool before
+   references are made to a null symbol pointer.  */
 
-  /* Scan up to the end of the op-code, which must end in white space or
-     end of string.  */
-  for (start = p = str; *p != '\0'; p++)
-    if (*p == ' ')
-      break;
+void
+arm_cleanup (void)
+{
+  literal_pool * pool;
 
-  if (p == str)
+  for (pool = list_of_pools; pool; pool = pool->next)
     {
-      as_bad (_("no operator -- statement `%s'\n"), str);
-      return;
+      /* Put it at the end of the relevent section.  */
+      subseg_set (pool->section, pool->sub_section);
+#ifdef OBJ_ELF
+      arm_elf_change_section ();
+#endif
+      s_ltorg (0);
     }
+}
 
-  if (thumb_mode)
-    {
-      const struct thumb_opcode * opcode;
+/* Adjust the symbol table.  This marks Thumb symbols as distinct from
+   ARM ones.  */
 
-      c = *p;
-      *p = '\0';
-      opcode = (const struct thumb_opcode *) hash_find (arm_tops_hsh, str);
-      *p = c;
+void
+arm_adjust_symtab (void)
+{
+#ifdef OBJ_COFF
+  symbolS * sym;
 
-      if (opcode)
+  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
+    {
+      if (ARM_IS_THUMB (sym))
 	{
-	  /* Check that this instruction is supported for this CPU.  */
-	  if (thumb_mode == 1 && (opcode->variant & cpu_variant) == 0)
+	  if (THUMB_IS_FUNC (sym))
 	    {
-	      as_bad (_("selected processor does not support `%s'"), str);
-	      return;
-	    }
+	      /* Mark the symbol as a Thumb function.  */
+	      if (   S_GET_STORAGE_CLASS (sym) == C_STAT
+		  || S_GET_STORAGE_CLASS (sym) == C_LABEL)  /* This can happen!	 */
+		S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
 
-	  mapping_state (MAP_THUMB);
-	  inst.instruction = opcode->value;
-	  inst.size = opcode->size;
-	  (*opcode->parms) (p);
-	  output_inst (str);
-	  return;
+	      else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
+		S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
+	      else
+		as_bad (_("%s: unexpected function type: %d"),
+			S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
+	    }
+	  else switch (S_GET_STORAGE_CLASS (sym))
+	    {
+	    case C_EXT:
+	      S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
+	      break;
+	    case C_STAT:
+	      S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
+	      break;
+	    case C_LABEL:
+	      S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
+	      break;
+	    default:
+	      /* Do nothing.  */
+	      break;
+	    }
 	}
+
+      if (ARM_IS_INTERWORK (sym))
+	coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
     }
-  else
+#endif
+#ifdef OBJ_ELF
+  symbolS * sym;
+  char	    bind;
+
+  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
     {
-      const struct asm_opcode * opcode;
+      if (ARM_IS_THUMB (sym))
+	{
+	  elf_symbol_type * elf_sym;
 
-      c = *p;
-      *p = '\0';
-      opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, str);
-      *p = c;
+	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
+	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
 
-      if (opcode)
-	{
-	  /* Check that this instruction is supported for this CPU.  */
-	  if ((opcode->variant & cpu_variant) == 0)
+	  if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
 	    {
-	      as_bad (_("selected processor does not support `%s'"), str);
-	      return;
+	      /* If it's a .thumb_func, declare it as so,
+		 otherwise tag label as .code 16.  */
+	      if (THUMB_IS_FUNC (sym))
+		elf_sym->internal_elf_sym.st_info =
+		  ELF_ST_INFO (bind, STT_ARM_TFUNC);
+	      else
+		elf_sym->internal_elf_sym.st_info =
+		  ELF_ST_INFO (bind, STT_ARM_16BIT);
 	    }
-
-          mapping_state (MAP_ARM);
-	  inst.instruction = opcode->value;
-	  inst.size = INSN_SIZE;
-	  (*opcode->parms) (p);
-	  output_inst (str);
-	  return;
 	}
     }
+#endif
+}
 
-  /* It wasn't an instruction, but it might be a register alias of the form
-     alias .req reg.  */
-  if (create_register_alias (str, p))
-    return;
+/* MD interface: Initialization.  */
+
+static void
+set_constant_flonums (void)
+{
+  int i;
+
+  for (i = 0; i < NUM_FLOAT_VALS; i++)
+    if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
+      abort ();
+}
+
+void
+md_begin (void)
+{
+  unsigned mach;
+  unsigned int i;
+
+  if (	 (arm_ops_hsh = hash_new ()) == NULL
+      || (arm_cond_hsh = hash_new ()) == NULL
+      || (arm_shift_hsh = hash_new ()) == NULL
+      || (arm_psr_hsh = hash_new ()) == NULL
+      || (arm_v7m_psr_hsh = hash_new ()) == NULL
+      || (arm_reg_hsh = hash_new ()) == NULL
+      || (arm_reloc_hsh = hash_new ()) == NULL
+      || (arm_barrier_opt_hsh = hash_new ()) == NULL)
+    as_fatal (_("virtual memory exhausted"));
+
+  for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
+    hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
+  for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
+    hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
+  for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
+    hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
+  for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
+    hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
+  for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
+    hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template, (PTR) (v7m_psrs + i));
+  for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
+    hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
+  for (i = 0;
+       i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
+       i++)
+    hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template,
+		 (PTR) (barrier_opt_names + i));
+#ifdef OBJ_ELF
+  for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
+    hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
+#endif
+
+  set_constant_flonums ();
+
+  /* Set the cpu variant based on the command-line options.  We prefer
+     -mcpu= over -march= if both are set (as for GCC); and we prefer
+     -mfpu= over any other way of setting the floating point unit.
+     Use of legacy options with new options are faulted.  */
+  if (legacy_cpu)
+    {
+      if (mcpu_cpu_opt || march_cpu_opt)
+	as_bad (_("use of old and new-style options to set CPU type"));
+
+      mcpu_cpu_opt = legacy_cpu;
+    }
+  else if (!mcpu_cpu_opt)
+    mcpu_cpu_opt = march_cpu_opt;
+
+  if (legacy_fpu)
+    {
+      if (mfpu_opt)
+	as_bad (_("use of old and new-style options to set FPU type"));
+
+      mfpu_opt = legacy_fpu;
+    }
+  else if (!mfpu_opt)
+    {
+#if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
+      /* Some environments specify a default FPU.  If they don't, infer it
+	 from the processor.  */
+      if (mcpu_fpu_opt)
+	mfpu_opt = mcpu_fpu_opt;
+      else
+	mfpu_opt = march_fpu_opt;
+#else
+      mfpu_opt = &fpu_default;
+#endif
+    }
+
+  if (!mfpu_opt)
+    {
+      if (!mcpu_cpu_opt)
+	mfpu_opt = &fpu_default;
+      else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
+	mfpu_opt = &fpu_arch_vfp_v2;
+      else
+	mfpu_opt = &fpu_arch_fpa;
+    }
+
+#ifdef CPU_DEFAULT
+  if (!mcpu_cpu_opt)
+    {
+      mcpu_cpu_opt = &cpu_default;
+      selected_cpu = cpu_default;
+    }
+#else
+  if (mcpu_cpu_opt)
+    selected_cpu = *mcpu_cpu_opt;
+  else
+    mcpu_cpu_opt = &arm_arch_any;
+#endif
+
+  ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
 
-  as_bad (_("bad instruction `%s'"), start);
+  arm_arch_used = thumb_arch_used = arm_arch_none;
+
+#if defined OBJ_COFF || defined OBJ_ELF
+  {
+    unsigned int flags = 0;
+
+#if defined OBJ_ELF
+    flags = meabi_flags;
+
+    switch (meabi_flags)
+      {
+      case EF_ARM_EABI_UNKNOWN:
+#endif
+	/* Set the flags in the private structure.  */
+	if (uses_apcs_26)      flags |= F_APCS26;
+	if (support_interwork) flags |= F_INTERWORK;
+	if (uses_apcs_float)   flags |= F_APCS_FLOAT;
+	if (pic_code)	       flags |= F_PIC;
+	if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
+	  flags |= F_SOFT_FLOAT;
+
+	switch (mfloat_abi_opt)
+	  {
+	  case ARM_FLOAT_ABI_SOFT:
+	  case ARM_FLOAT_ABI_SOFTFP:
+	    flags |= F_SOFT_FLOAT;
+	    break;
+
+	  case ARM_FLOAT_ABI_HARD:
+	    if (flags & F_SOFT_FLOAT)
+	      as_bad (_("hard-float conflicts with specified fpu"));
+	    break;
+	  }
+
+	/* Using pure-endian doubles (even if soft-float).	*/
+	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
+	  flags |= F_VFP_FLOAT;
+
+#if defined OBJ_ELF
+	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
+	    flags |= EF_ARM_MAVERICK_FLOAT;
+	break;
+
+      case EF_ARM_EABI_VER4:
+      case EF_ARM_EABI_VER5:
+	/* No additional flags to set.	*/
+	break;
+
+      default:
+	abort ();
+      }
+#endif
+    bfd_set_private_flags (stdoutput, flags);
+
+    /* We have run out flags in the COFF header to encode the
+       status of ATPCS support, so instead we create a dummy,
+       empty, debug section called .arm.atpcs.	*/
+    if (atpcs)
+      {
+	asection * sec;
+
+	sec = bfd_make_section (stdoutput, ".arm.atpcs");
+
+	if (sec != NULL)
+	  {
+	    bfd_set_section_flags
+	      (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
+	    bfd_set_section_size (stdoutput, sec, 0);
+	    bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
+	  }
+      }
+  }
+#endif
+
+  /* Record the CPU type as well.  */
+  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
+    mach = bfd_mach_arm_iWMMXt;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
+    mach = bfd_mach_arm_XScale;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
+    mach = bfd_mach_arm_ep9312;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
+    mach = bfd_mach_arm_5TE;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
+    {
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+	mach = bfd_mach_arm_5T;
+      else
+	mach = bfd_mach_arm_5;
+    }
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
+    {
+      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
+	mach = bfd_mach_arm_4T;
+      else
+	mach = bfd_mach_arm_4;
+    }
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
+    mach = bfd_mach_arm_3M;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
+    mach = bfd_mach_arm_3;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
+    mach = bfd_mach_arm_2a;
+  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
+    mach = bfd_mach_arm_2;
+  else
+    mach = bfd_mach_arm_unknown;
+
+  bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
 }
 
+/* Command line processing.  */
+
 /* md_parse_option
       Invocation line includes a switch not recognized by the base assembler.
       See if it's a processor-specific option.
@@ -13065,23 +13062,23 @@ md_assemble (str)
 
       The remaining options are only supported for back-wards compatibility.
       Cpu variants, the arm part is optional:
-              -m[arm]1                Currently not supported.
-              -m[arm]2, -m[arm]250    Arm 2 and Arm 250 processor
-              -m[arm]3                Arm 3 processor
-              -m[arm]6[xx],           Arm 6 processors
-              -m[arm]7[xx][t][[d]m]   Arm 7 processors
-              -m[arm]8[10]            Arm 8 processors
-              -m[arm]9[20][tdmi]      Arm 9 processors
-              -mstrongarm[110[0]]     StrongARM processors
-              -mxscale                XScale processors
-              -m[arm]v[2345[t[e]]]    Arm architectures
-              -mall                   All (except the ARM1)
+	      -m[arm]1		      Currently not supported.
+	      -m[arm]2, -m[arm]250    Arm 2 and Arm 250 processor
+	      -m[arm]3		      Arm 3 processor
+	      -m[arm]6[xx],	      Arm 6 processors
+	      -m[arm]7[xx][t][[d]m]   Arm 7 processors
+	      -m[arm]8[10]	      Arm 8 processors
+	      -m[arm]9[20][tdmi]      Arm 9 processors
+	      -mstrongarm[110[0]]     StrongARM processors
+	      -mxscale		      XScale processors
+	      -m[arm]v[2345[t[e]]]    Arm architectures
+	      -mall		      All (except the ARM1)
       FP variants:
-              -mfpa10, -mfpa11        FPA10 and 11 co-processor instructions
-              -mfpe-old               (No float load/store multiples)
+	      -mfpa10, -mfpa11	      FPA10 and 11 co-processor instructions
+	      -mfpe-old		      (No float load/store multiples)
 	      -mvfpxd		      VFP Single precision
 	      -mvfp		      All VFP
-              -mno-fpu                Disable all floating point instructions
+	      -mno-fpu		      Disable all floating point instructions
 
       The following CPU names are recognized:
 	      arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
@@ -13124,18 +13121,17 @@ struct arm_option_table
 {
   char *option;		/* Option name to match.  */
   char *help;		/* Help information.  */
-  int  *var;		/* Variable to change.  */
-  int   value;		/* What to change it to.  */
+  int  *var;		/* Variable to change.	*/
+  int	value;		/* What to change it to.  */
   char *deprecated;	/* If non-null, print this message.  */
 };
 
 struct arm_option_table arm_opts[] =
 {
-  {"k",      N_("generate PIC code"),      &pic_code,    1, NULL},
-  {"mthumb", N_("assemble Thumb code"),    &thumb_mode,  1, NULL},
+  {"k",	     N_("generate PIC code"),	   &pic_code,	 1, NULL},
+  {"mthumb", N_("assemble Thumb code"),	   &thumb_mode,	 1, NULL},
   {"mthumb-interwork", N_("support ARM/Thumb interworking"),
    &support_interwork, 1, NULL},
-  {"moabi",  N_("use old ABI (ELF only)"), &target_oabi, 1, NULL},
   {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
   {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
   {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
@@ -13143,218 +13139,252 @@ struct arm_option_table arm_opts[] =
   {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
   {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
   {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
-  {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 1,
+  {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
    NULL},
 
-  /* These are recognized by the assembler, but have no affect on code.  */
+  /* These are recognized by the assembler, but have no affect on code.	 */
   {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
   {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
+  {NULL, NULL, NULL, 0, NULL}
+};
+
+struct arm_legacy_option_table
+{
+  char *option;				/* Option name to match.  */
+  const arm_feature_set	**var;		/* Variable to change.	*/
+  const arm_feature_set	value;		/* What to change it to.  */
+  char *deprecated;			/* If non-null, print this message.  */
+};
 
+const struct arm_legacy_option_table arm_legacy_opts[] =
+{
   /* DON'T add any new processors to this list -- we want the whole list
      to go away...  Add them to the processors table instead.  */
-  {"marm1",	 NULL, &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
-  {"m1",	 NULL, &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
-  {"marm2",	 NULL, &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
-  {"m2",	 NULL, &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
-  {"marm250",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
-  {"m250",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
-  {"marm3",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
-  {"m3",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
-  {"marm6",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
-  {"m6",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
-  {"marm600",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
-  {"m600",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
-  {"marm610",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
-  {"m610",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
-  {"marm620",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
-  {"m620",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
-  {"marm7",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
-  {"m7",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
-  {"marm70",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
-  {"m70",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
-  {"marm700",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
-  {"m700",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
-  {"marm700i",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
-  {"m700i",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
-  {"marm710",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
-  {"m710",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
-  {"marm710c",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
-  {"m710c",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
-  {"marm720",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
-  {"m720",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
-  {"marm7d",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
-  {"m7d",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
-  {"marm7di",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
-  {"m7di",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
-  {"marm7m",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
-  {"m7m",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
-  {"marm7dm",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
-  {"m7dm",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
-  {"marm7dmi",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
-  {"m7dmi",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
-  {"marm7100",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
-  {"m7100",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
-  {"marm7500",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
-  {"m7500",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
-  {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
-  {"m7500fe",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
-  {"marm7t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
-  {"m7t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
-  {"marm7tdmi",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
-  {"m7tdmi",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
-  {"marm710t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
-  {"m710t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
-  {"marm720t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
-  {"m720t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
-  {"marm740t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
-  {"m740t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
-  {"marm8",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
-  {"m8",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
-  {"marm810",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
-  {"m810",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
-  {"marm9",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
-  {"m9",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
-  {"marm9tdmi",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
-  {"m9tdmi",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
-  {"marm920",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
-  {"m920",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
-  {"marm940",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
-  {"m940",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
-  {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=strongarm")},
-  {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
+  {"marm1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
+  {"m1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
+  {"marm2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
+  {"m2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
+  {"marm250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
+  {"m250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
+  {"marm3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
+  {"m3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
+  {"marm6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
+  {"m6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
+  {"marm600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
+  {"m600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
+  {"marm610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
+  {"m610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
+  {"marm620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
+  {"m620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
+  {"marm7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
+  {"m7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
+  {"marm70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
+  {"m70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
+  {"marm700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
+  {"m700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
+  {"marm700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
+  {"m700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
+  {"marm710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
+  {"m710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
+  {"marm710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
+  {"m710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
+  {"marm720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
+  {"m720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
+  {"marm7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
+  {"m7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
+  {"marm7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
+  {"m7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
+  {"marm7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
+  {"m7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
+  {"marm7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
+  {"m7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
+  {"marm7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
+  {"m7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
+  {"marm7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
+  {"m7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
+  {"marm7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
+  {"m7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
+  {"marm7500fe", &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
+  {"m7500fe",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
+  {"marm7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+  {"m7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+  {"marm7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+  {"m7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
+  {"marm710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
+  {"m710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
+  {"marm720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
+  {"m720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
+  {"marm740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
+  {"m740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
+  {"marm8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
+  {"m8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
+  {"marm810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
+  {"m810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
+  {"marm9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
+  {"m9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
+  {"marm9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
+  {"m9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
+  {"marm920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
+  {"m920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
+  {"marm940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
+  {"m940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
+  {"mstrongarm", &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=strongarm")},
+  {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
    N_("use -mcpu=strongarm110")},
-  {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
+  {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
    N_("use -mcpu=strongarm1100")},
-  {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
+  {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
    N_("use -mcpu=strongarm1110")},
-  {"mxscale",	 NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
-  {"miwmmxt",	 NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
-  {"mall",	 NULL, &legacy_cpu, ARM_ANY,      N_("use -mcpu=all")},
+  {"mxscale",	 &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
+  {"miwmmxt",	 &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
+  {"mall",	 &legacy_cpu, ARM_ANY,	       N_("use -mcpu=all")},
 
   /* Architecture variants -- don't add any more to this list either.  */
-  {"mv2",	 NULL, &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
-  {"marmv2",	 NULL, &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
-  {"mv2a",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
-  {"marmv2a",	 NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
-  {"mv3",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
-  {"marmv3",	 NULL, &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
-  {"mv3m",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
-  {"marmv3m",	 NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
-  {"mv4",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
-  {"marmv4",	 NULL, &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
-  {"mv4t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
-  {"marmv4t",	 NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
-  {"mv5",	 NULL, &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
-  {"marmv5",	 NULL, &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
-  {"mv5t",	 NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
-  {"marmv5t",	 NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
-  {"mv5e",	 NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
-  {"marmv5e",	 NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
-
-  /* Floating point variants -- don't add any more to this list either.  */
-  {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
-  {"mfpa10",   NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
-  {"mfpa11",   NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
-  {"mno-fpu",  NULL, &legacy_fpu, 0,
+  {"mv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
+  {"marmv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
+  {"mv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
+  {"marmv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
+  {"mv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
+  {"marmv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
+  {"mv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
+  {"marmv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
+  {"mv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
+  {"marmv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
+  {"mv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
+  {"marmv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
+  {"mv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
+  {"marmv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
+  {"mv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
+  {"marmv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
+  {"mv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
+  {"marmv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
+
+  /* Floating point variants -- don't add any more to this list either.	 */
+  {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
+  {"mfpa10",   &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
+  {"mfpa11",   &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
+  {"mno-fpu",  &legacy_fpu, ARM_ARCH_NONE,
    N_("use either -mfpu=softfpa or -mfpu=softvfp")},
 
-  {NULL, NULL, NULL, 0, NULL}
+  {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
 struct arm_cpu_option_table
 {
   char *name;
-  int   value;
+  const arm_feature_set	value;
   /* For some CPUs we assume an FPU unless the user explicitly sets
-     -mfpu=...  */
-  int   default_fpu;
+     -mfpu=...	*/
+  const arm_feature_set	default_fpu;
+  /* The canonical name of the CPU, or NULL to use NAME converted to upper
+     case.  */
+  const char *canonical_name;
 };
 
 /* This list should, at a minimum, contain all the cpu names
    recognized by GCC.  */
-static struct arm_cpu_option_table arm_cpus[] =
-{
-  {"all",		ARM_ANY,	 FPU_ARCH_FPA},
-  {"arm1",		ARM_ARCH_V1,	 FPU_ARCH_FPA},
-  {"arm2",		ARM_ARCH_V2,	 FPU_ARCH_FPA},
-  {"arm250",		ARM_ARCH_V2S,	 FPU_ARCH_FPA},
-  {"arm3",		ARM_ARCH_V2S,	 FPU_ARCH_FPA},
-  {"arm6",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm60",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm600",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm610",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm620",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7m",		ARM_ARCH_V3M,	 FPU_ARCH_FPA},
-  {"arm7d",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7dm",		ARM_ARCH_V3M,	 FPU_ARCH_FPA},
-  {"arm7di",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7dmi",		ARM_ARCH_V3M,	 FPU_ARCH_FPA},
-  {"arm70",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm700",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm700i",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm710",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm710t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm720",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm720t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm740t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm710c",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7100",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7500",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7500fe",		ARM_ARCH_V3,	 FPU_ARCH_FPA},
-  {"arm7t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm7tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm8",		ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"arm810",		ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"strongarm",		ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"strongarm1",	ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"strongarm110",	ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"strongarm1100",	ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"strongarm1110",	ARM_ARCH_V4,	 FPU_ARCH_FPA},
-  {"arm9",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm920",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm920t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm922t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm940t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
-  {"arm9tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA},
+static const struct arm_cpu_option_table arm_cpus[] =
+{
+  {"all",		ARM_ANY,	 FPU_ARCH_FPA,    NULL},
+  {"arm1",		ARM_ARCH_V1,	 FPU_ARCH_FPA,    NULL},
+  {"arm2",		ARM_ARCH_V2,	 FPU_ARCH_FPA,    NULL},
+  {"arm250",		ARM_ARCH_V2S,	 FPU_ARCH_FPA,    NULL},
+  {"arm3",		ARM_ARCH_V2S,	 FPU_ARCH_FPA,    NULL},
+  {"arm6",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm60",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm600",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm610",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm620",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7m",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
+  {"arm7d",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7dm",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
+  {"arm7di",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7dmi",		ARM_ARCH_V3M,	 FPU_ARCH_FPA,    NULL},
+  {"arm70",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm700",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm700i",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm710",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm710t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm720",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm720t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm740t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm710c",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7100",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7500",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7500fe",		ARM_ARCH_V3,	 FPU_ARCH_FPA,    NULL},
+  {"arm7t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm7tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm7tdmi-s",	ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm8",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"arm810",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"strongarm",		ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"strongarm1",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"strongarm110",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"strongarm1100",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"strongarm1110",	ARM_ARCH_V4,	 FPU_ARCH_FPA,    NULL},
+  {"arm9",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm920",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    "ARM920T"},
+  {"arm920t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm922t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm940t",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,    NULL},
+  {"arm9tdmi",		ARM_ARCH_V4T,	 FPU_ARCH_FPA,	  NULL},
   /* For V5 or later processors we default to using VFP; but the user
-     should really set the FPU type explicitly.  */
-  {"arm9e-r0",		ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
-  {"arm9e",		ARM_ARCH_V5TE,   FPU_ARCH_VFP_V2},
-  {"arm926ej",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2},
-  {"arm926ejs",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2},
-  {"arm946e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
-  {"arm946e",		ARM_ARCH_V5TE,   FPU_ARCH_VFP_V2},
-  {"arm966e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
-  {"arm966e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
-  {"arm10t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1},
-  {"arm10e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
-  {"arm1020",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
-  {"arm1020t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1},
-  {"arm1020e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
-  {"arm1026ejs",	ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2},
-  {"arm1136js",		ARM_ARCH_V6,     FPU_NONE},
-  {"arm1136jfs",	ARM_ARCH_V6,     FPU_ARCH_VFP_V2},
+     should really set the FPU type explicitly.	 */
+  {"arm9e-r0",		ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
+  {"arm9e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm926ej",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM926EJ-S"},
+  {"arm926ejs",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM926EJ-S"},
+  {"arm926ej-s",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm946e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
+  {"arm946e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM946E-S"},
+  {"arm946e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm966e-r0",	ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
+  {"arm966e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM966E-S"},
+  {"arm966e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm968e-s",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm10t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
+  {"arm10tdmi",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
+  {"arm10e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm1020",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, "ARM1020E"},
+  {"arm1020t",		ARM_ARCH_V5T,	 FPU_ARCH_VFP_V1, NULL},
+  {"arm1020e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm1022e",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm1026ejs",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
+  {"arm1026ej-s",	ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm1136js",		ARM_ARCH_V6,	 FPU_NONE,	  "ARM1136J-S"},
+  {"arm1136j-s",	ARM_ARCH_V6,	 FPU_NONE,	  NULL},
+  {"arm1136jfs",	ARM_ARCH_V6,	 FPU_ARCH_VFP_V2, "ARM1136JF-S"},
+  {"arm1136jf-s",	ARM_ARCH_V6,	 FPU_ARCH_VFP_V2, NULL},
+  {"mpcore",		ARM_ARCH_V6K,	 FPU_ARCH_VFP_V2, NULL},
+  {"mpcorenovfp",	ARM_ARCH_V6K,	 FPU_NONE,	  NULL},
+  {"arm1156t2-s",	ARM_ARCH_V6T2,	 FPU_NONE,	  NULL},
+  {"arm1156t2f-s",	ARM_ARCH_V6T2,	 FPU_ARCH_VFP_V2, NULL},
+  {"arm1176jz-s",	ARM_ARCH_V6ZK,	 FPU_NONE,	  NULL},
+  {"arm1176jzf-s",	ARM_ARCH_V6ZK,	 FPU_ARCH_VFP_V2, NULL},
+  {"cortex-a8",		ARM_ARCH_V7A,	 FPU_ARCH_VFP_V2, NULL},
+  {"cortex-r4",		ARM_ARCH_V7R,	 FPU_NONE,	  NULL},
+  {"cortex-m3",		ARM_ARCH_V7M,	 FPU_NONE,	  NULL},
   /* ??? XSCALE is really an architecture.  */
-  {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
+  {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* ??? iwmmxt is not a processor.  */
-  {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
-  {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
+  {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
+  {"i80200",		ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
   /* Maverick */
-  {"ep9312",		ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
-  {NULL, 0, 0}
+  {"ep9312",	ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
+  {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE, NULL}
 };
 
 struct arm_arch_option_table
 {
   char *name;
-  int   value;
-  int   default_fpu;
+  const arm_feature_set	value;
+  const arm_feature_set	default_fpu;
 };
 
 /* This list should, at a minimum, contain all the architecture names
    recognized by GCC.  */
-static struct arm_arch_option_table arm_archs[] =
+static const struct arm_arch_option_table arm_archs[] =
 {
   {"all",		ARM_ANY,	 FPU_ARCH_FPA},
   {"armv1",		ARM_ARCH_V1,	 FPU_ARCH_FPA},
@@ -13372,38 +13402,43 @@ static struct arm_arch_option_table arm_archs[] =
   {"armv5txm",		ARM_ARCH_V5TxM,	 FPU_ARCH_VFP},
   {"armv5te",		ARM_ARCH_V5TE,	 FPU_ARCH_VFP},
   {"armv5texp",		ARM_ARCH_V5TExP, FPU_ARCH_VFP},
-  {"armv5tej",		ARM_ARCH_V5TEJ,  FPU_ARCH_VFP},
-  {"armv6",             ARM_ARCH_V6,     FPU_ARCH_VFP},
-  {"armv6j",            ARM_ARCH_V6,     FPU_ARCH_VFP},
+  {"armv5tej",		ARM_ARCH_V5TEJ,	 FPU_ARCH_VFP},
+  {"armv6",		ARM_ARCH_V6,	 FPU_ARCH_VFP},
+  {"armv6j",		ARM_ARCH_V6,	 FPU_ARCH_VFP},
+  {"armv6k",		ARM_ARCH_V6K,	 FPU_ARCH_VFP},
+  {"armv6z",		ARM_ARCH_V6Z,	 FPU_ARCH_VFP},
+  {"armv6zk",		ARM_ARCH_V6ZK,	 FPU_ARCH_VFP},
+  {"armv6t2",		ARM_ARCH_V6T2,	 FPU_ARCH_VFP},
+  {"armv6kt2",		ARM_ARCH_V6KT2,	 FPU_ARCH_VFP},
+  {"armv6zt2",		ARM_ARCH_V6ZT2,	 FPU_ARCH_VFP},
+  {"armv6zkt2",		ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
+  {"armv7",		ARM_ARCH_V7,	 FPU_ARCH_VFP},
+  {"armv7a",		ARM_ARCH_V7A,	 FPU_ARCH_VFP},
+  {"armv7r",		ARM_ARCH_V7R,	 FPU_ARCH_VFP},
+  {"armv7m",		ARM_ARCH_V7M,	 FPU_ARCH_VFP},
   {"xscale",		ARM_ARCH_XSCALE, FPU_ARCH_VFP},
   {"iwmmxt",		ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
-  {NULL, 0, 0}
+  {NULL,		ARM_ARCH_NONE,	 ARM_ARCH_NONE}
 };
 
 /* ISA extensions in the co-processor space.  */
-struct arm_arch_extension_table
+struct arm_option_cpu_value_table
 {
   char *name;
-  int value;
+  const arm_feature_set value;
 };
 
-static struct arm_arch_extension_table arm_extensions[] =
+static const struct arm_option_cpu_value_table arm_extensions[] =
 {
-  {"maverick",		ARM_CEXT_MAVERICK},
-  {"xscale",		ARM_CEXT_XSCALE},
-  {"iwmmxt",		ARM_CEXT_IWMMXT},
-  {NULL,		0}
-};
-
-struct arm_fpu_option_table
-{
-  char *name;
-  int   value;
+  {"maverick",		ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
+  {"xscale",		ARM_FEATURE (0, ARM_CEXT_XSCALE)},
+  {"iwmmxt",		ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
+  {NULL,		ARM_ARCH_NONE}
 };
 
 /* This list should, at a minimum, contain all the fpu names
    recognized by GCC.  */
-static struct arm_fpu_option_table arm_fpus[] =
+static const struct arm_option_cpu_value_table arm_fpus[] =
 {
   {"softfpa",		FPU_NONE},
   {"fpe",		FPU_ARCH_FPE},
@@ -13423,41 +13458,57 @@ static struct arm_fpu_option_table arm_fpus[] =
   {"arm1020t",		FPU_ARCH_VFP_V1},
   {"arm1020e",		FPU_ARCH_VFP_V2},
   {"arm1136jfs",	FPU_ARCH_VFP_V2},
+  {"arm1136jf-s",	FPU_ARCH_VFP_V2},
   {"maverick",		FPU_ARCH_MAVERICK},
-  {NULL, 0}
+  {NULL,		ARM_ARCH_NONE}
 };
 
-struct arm_float_abi_option_table
+struct arm_option_value_table
 {
   char *name;
-  int value;
+  long value;
 };
 
-static struct arm_float_abi_option_table arm_float_abis[] =
+static const struct arm_option_value_table arm_float_abis[] =
 {
   {"hard",	ARM_FLOAT_ABI_HARD},
   {"softfp",	ARM_FLOAT_ABI_SOFTFP},
   {"soft",	ARM_FLOAT_ABI_SOFT},
-  {NULL, 0}
+  {NULL,	0}
 };
 
+#ifdef OBJ_ELF
+/* We only know how to output GNU and ver 4/5 (AAELF) formats.  */
+static const struct arm_option_value_table arm_eabis[] =
+{
+  {"gnu",	EF_ARM_EABI_UNKNOWN},
+  {"4",		EF_ARM_EABI_VER4},
+  {"5",		EF_ARM_EABI_VER5},
+  {NULL,	0}
+};
+#endif
+
 struct arm_long_option_table
 {
-  char *option;		/* Substring to match.  */
-  char *help;		/* Help information.  */
-  int (*func) PARAMS ((char *subopt));	/* Function to decode sub-option.  */
-  char *deprecated;	/* If non-null, print this message.  */
+  char * option;		/* Substring to match.	*/
+  char * help;			/* Help information.  */
+  int (* func) (char * subopt);	/* Function to decode sub-option.  */
+  char * deprecated;		/* If non-null, print this message.  */
 };
 
 static int
-arm_parse_extension (str, opt_p)
-     char *str;
-     int *opt_p;
+arm_parse_extension (char * str, const arm_feature_set **opt_p)
 {
+  arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
+
+  /* Copy the feature set, so that we can modify it.  */
+  *ext_set = **opt_p;
+  *opt_p = ext_set;
+
   while (str != NULL && *str != 0)
     {
-      struct arm_arch_extension_table *opt;
-      char *ext;
+      const struct arm_option_cpu_value_table * opt;
+      char * ext;
       int optlen;
 
       if (*str != '+')
@@ -13483,7 +13534,7 @@ arm_parse_extension (str, opt_p)
       for (opt = arm_extensions; opt->name != NULL; opt++)
 	if (strncmp (opt->name, str, optlen) == 0)
 	  {
-	    *opt_p |= opt->value;
+	    ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
 	    break;
 	  }
 
@@ -13500,11 +13551,10 @@ arm_parse_extension (str, opt_p)
 }
 
 static int
-arm_parse_cpu (str)
-     char *str;
+arm_parse_cpu (char * str)
 {
-  struct arm_cpu_option_table *opt;
-  char *ext = strchr (str, '+');
+  const struct arm_cpu_option_table * opt;
+  char * ext = strchr (str, '+');
   int optlen;
 
   if (ext != NULL)
@@ -13521,8 +13571,17 @@ arm_parse_cpu (str)
   for (opt = arm_cpus; opt->name != NULL; opt++)
     if (strncmp (opt->name, str, optlen) == 0)
       {
-	mcpu_cpu_opt = opt->value;
-	mcpu_fpu_opt = opt->default_fpu;
+	mcpu_cpu_opt = &opt->value;
+	mcpu_fpu_opt = &opt->default_fpu;
+	if (opt->canonical_name)
+	  strcpy(selected_cpu_name, opt->canonical_name);
+	else
+	  {
+	    int i;
+	    for (i = 0; i < optlen; i++)
+	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
+	    selected_cpu_name[i] = 0;
+	  }
 
 	if (ext != NULL)
 	  return arm_parse_extension (ext, &mcpu_cpu_opt);
@@ -13535,10 +13594,9 @@ arm_parse_cpu (str)
 }
 
 static int
-arm_parse_arch (str)
-     char *str;
+arm_parse_arch (char * str)
 {
-  struct arm_arch_option_table *opt;
+  const struct arm_arch_option_table *opt;
   char *ext = strchr (str, '+');
   int optlen;
 
@@ -13553,12 +13611,12 @@ arm_parse_arch (str)
       return 0;
     }
 
-
   for (opt = arm_archs; opt->name != NULL; opt++)
-    if (strcmp (opt->name, str) == 0)
+    if (streq (opt->name, str))
       {
-	march_cpu_opt = opt->value;
-	march_fpu_opt = opt->default_fpu;
+	march_cpu_opt = &opt->value;
+	march_fpu_opt = &opt->default_fpu;
+	strcpy(selected_cpu_name, opt->name);
 
 	if (ext != NULL)
 	  return arm_parse_extension (ext, &march_cpu_opt);
@@ -13571,15 +13629,14 @@ arm_parse_arch (str)
 }
 
 static int
-arm_parse_fpu (str)
-     char *str;
+arm_parse_fpu (char * str)
 {
-  struct arm_fpu_option_table *opt;
+  const struct arm_option_cpu_value_table * opt;
 
   for (opt = arm_fpus; opt->name != NULL; opt++)
-    if (strcmp (opt->name, str) == 0)
+    if (streq (opt->name, str))
       {
-	mfpu_opt = opt->value;
+	mfpu_opt = &opt->value;
 	return 1;
       }
 
@@ -13588,13 +13645,12 @@ arm_parse_fpu (str)
 }
 
 static int
-arm_parse_float_abi (str)
-     char * str;
+arm_parse_float_abi (char * str)
 {
-  struct arm_float_abi_option_table *opt;
+  const struct arm_option_value_table * opt;
 
   for (opt = arm_float_abis; opt->name != NULL; opt++)
-    if (strcmp (opt->name, str) == 0)
+    if (streq (opt->name, str))
       {
 	mfloat_abi_opt = opt->value;
 	return 1;
@@ -13604,6 +13660,23 @@ arm_parse_float_abi (str)
   return 0;
 }
 
+#ifdef OBJ_ELF
+static int
+arm_parse_eabi (char * str)
+{
+  const struct arm_option_value_table *opt;
+
+  for (opt = arm_eabis; opt->name != NULL; opt++)
+    if (streq (opt->name, str))
+      {
+	meabi_flags = opt->value;
+	return 1;
+      }
+  as_bad (_("unknown EABI `%s'\n"), str);
+  return 0;
+}
+#endif
+
 struct arm_long_option_table arm_long_opts[] =
 {
   {"mcpu=", N_("<cpu name>\t  assemble for CPU <cpu name>"),
@@ -13614,15 +13687,18 @@ struct arm_long_option_table arm_long_opts[] =
    arm_parse_fpu, NULL},
   {"mfloat-abi=", N_("<abi>\t  assemble for floating point ABI <abi>"),
    arm_parse_float_abi, NULL},
+#ifdef OBJ_ELF
+  {"meabi=", N_("<ver>\t  assemble for eabi version <ver>"),
+   arm_parse_eabi, NULL},
+#endif
   {NULL, NULL, 0, NULL}
 };
 
 int
-md_parse_option (c, arg)
-     int    c;
-     char * arg;
+md_parse_option (int c, char * arg)
 {
   struct arm_option_table *opt;
+  const struct arm_legacy_option_table *fopt;
   struct arm_long_option_table *lopt;
 
   switch (c)
@@ -13641,7 +13717,7 @@ md_parse_option (c, arg)
 
     case 'a':
       /* Listing option.  Just ignore these, we don't support additional
-	 ones.  */
+	 ones.	*/
       return 0;
 
     default:
@@ -13649,7 +13725,7 @@ md_parse_option (c, arg)
 	{
 	  if (c == opt->option[0]
 	      && ((arg == NULL && opt->option[1] == 0)
-		  || strcmp (arg, opt->option + 1) == 0))
+		  || streq (arg, opt->option + 1)))
 	    {
 #if WARN_DEPRECATED
 	      /* If the option is deprecated, tell the user.  */
@@ -13665,6 +13741,26 @@ md_parse_option (c, arg)
 	    }
 	}
 
+      for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
+	{
+	  if (c == fopt->option[0]
+	      && ((arg == NULL && fopt->option[1] == 0)
+		  || streq (arg, fopt->option + 1)))
+	    {
+#if WARN_DEPRECATED
+	      /* If the option is deprecated, tell the user.  */
+	      if (fopt->deprecated != NULL)
+		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
+			   arg ? arg : "", _(fopt->deprecated));
+#endif
+
+	      if (fopt->var != NULL)
+		*fopt->var = &fopt->value;
+
+	      return 1;
+	    }
+	}
+
       for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
 	{
 	  /* These options are expected to have an argument.  */
@@ -13681,11 +13777,10 @@ md_parse_option (c, arg)
 #endif
 
 	      /* Call the sup-option parser.  */
-	      return (*lopt->func)(arg + strlen (lopt->option) - 1);
+	      return lopt->func (arg + strlen (lopt->option) - 1);
 	    }
 	}
 
-      as_bad (_("unrecognized option `-%c%s'"), c, arg ? arg : "");
       return 0;
     }
 
@@ -13693,8 +13788,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (fp)
-     FILE * fp;
+md_show_usage (FILE * fp)
 {
   struct arm_option_table *opt;
   struct arm_long_option_table *lopt;
@@ -13720,581 +13814,229 @@ md_show_usage (fp)
 #endif
 }
 
-/* We need to be able to fix up arbitrary expressions in some statements.
-   This is so that we can handle symbols that are an arbitrary distance from
-   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
-   which returns part of an address in a form which will be valid for
-   a data instruction.  We do this by pushing the expression into a symbol
-   in the expr_section, and creating a fix for that.  */
-
-static void
-fix_new_arm (frag, where, size, exp, pc_rel, reloc)
-     fragS *       frag;
-     int           where;
-     short int     size;
-     expressionS * exp;
-     int           pc_rel;
-     int           reloc;
-{
-  fixS *           new_fix;
-  arm_fix_data *   arm_data;
-
-  switch (exp->X_op)
-    {
-    case O_constant:
-    case O_symbol:
-    case O_add:
-    case O_subtract:
-      new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
-      break;
-
-    default:
-      new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
-			 pc_rel, reloc);
-      break;
-    }
-
-  /* Mark whether the fix is to a THUMB instruction, or an ARM
-     instruction.  */
-  arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
-  new_fix->tc_fix_data = (PTR) arm_data;
-  arm_data->thumb_mode = thumb_mode;
-}
-
-/* This fix_new is called by cons via TC_CONS_FIX_NEW.  */
-
-void
-cons_fix_new_arm (frag, where, size, exp)
-     fragS *       frag;
-     int           where;
-     int           size;
-     expressionS * exp;
-{
-  bfd_reloc_code_real_type type;
-  int pcrel = 0;
-
-  /* Pick a reloc.
-     FIXME: @@ Should look at CPU word size.  */
-  switch (size)
-    {
-    case 1:
-      type = BFD_RELOC_8;
-      break;
-    case 2:
-      type = BFD_RELOC_16;
-      break;
-    case 4:
-    default:
-      type = BFD_RELOC_32;
-      break;
-    case 8:
-      type = BFD_RELOC_64;
-      break;
-    }
-
-  fix_new_exp (frag, where, (int) size, exp, pcrel, type);
-}
-
-/* A good place to do this, although this was probably not intended
-   for this kind of use.  We need to dump the literal pool before
-   references are made to a null symbol pointer.  */
-
-void
-arm_cleanup ()
-{
-  literal_pool * pool;
 
-  for (pool = list_of_pools; pool; pool = pool->next)
-    {
-      /* Put it at the end of the relevent section.  */
-      subseg_set (pool->section, pool->sub_section);
 #ifdef OBJ_ELF
-      arm_elf_change_section ();
-#endif
-      s_ltorg (0);
-    }
-}
-
-void
-arm_start_line_hook ()
-{
-  last_label_seen = NULL;
-}
-
-void
-arm_frob_label (sym)
-     symbolS * sym;
+typedef struct
 {
-  last_label_seen = sym;
-
-  ARM_SET_THUMB (sym, thumb_mode);
-
-#if defined OBJ_COFF || defined OBJ_ELF
-  ARM_SET_INTERWORK (sym, support_interwork);
-#endif
-
-  /* Note - do not allow local symbols (.Lxxx) to be labeled
-     as Thumb functions.  This is because these labels, whilst
-     they exist inside Thumb code, are not the entry points for
-     possible ARM->Thumb calls.  Also, these labels can be used
-     as part of a computed goto or switch statement.  eg gcc
-     can generate code that looks like this:
-
-                ldr  r2, [pc, .Laaa]
-                lsl  r3, r3, #2
-                ldr  r2, [r3, r2]
-                mov  pc, r2
-
-       .Lbbb:  .word .Lxxx
-       .Lccc:  .word .Lyyy
-       ..etc...
-       .Laaa:   .word Lbbb
-
-     The first instruction loads the address of the jump table.
-     The second instruction converts a table index into a byte offset.
-     The third instruction gets the jump address out of the table.
-     The fourth instruction performs the jump.
-
-     If the address stored at .Laaa is that of a symbol which has the
-     Thumb_Func bit set, then the linker will arrange for this address
-     to have the bottom bit set, which in turn would mean that the
-     address computation performed by the third instruction would end
-     up with the bottom bit set.  Since the ARM is capable of unaligned
-     word loads, the instruction would then load the incorrect address
-     out of the jump table, and chaos would ensue.  */
-  if (label_is_thumb_function_name
-      && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
-      && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
-    {
-      /* When the address of a Thumb function is taken the bottom
-	 bit of that address should be set.  This will allow
-	 interworking between Arm and Thumb functions to work
-	 correctly.  */
-
-      THUMB_SET_FUNC (sym, 1);
-
-      label_is_thumb_function_name = FALSE;
-    }
-}
-
-/* Adjust the symbol table.  This marks Thumb symbols as distinct from
-   ARM ones.  */
+  int val;
+  arm_feature_set flags;
+} cpu_arch_ver_table;
+
+/* Mapping from CPU features to EABI CPU arch values.  Table must be sorted
+   least features first.  */
+static const cpu_arch_ver_table cpu_arch_ver[] =
+{
+    {1, ARM_ARCH_V4},
+    {2, ARM_ARCH_V4T},
+    {3, ARM_ARCH_V5},
+    {4, ARM_ARCH_V5TE},
+    {5, ARM_ARCH_V5TEJ},
+    {6, ARM_ARCH_V6},
+    {7, ARM_ARCH_V6Z},
+    {8, ARM_ARCH_V6K},
+    {9, ARM_ARCH_V6T2},
+    {10, ARM_ARCH_V7A},
+    {10, ARM_ARCH_V7R},
+    {10, ARM_ARCH_V7M},
+    {0, ARM_ARCH_NONE}
+};
 
-void
-arm_adjust_symtab ()
+/* Set the public EABI object attributes.  */
+static void
+aeabi_set_public_attributes (void)
 {
-#ifdef OBJ_COFF
-  symbolS * sym;
-
-  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
-    {
-      if (ARM_IS_THUMB (sym))
-	{
-	  if (THUMB_IS_FUNC (sym))
-	    {
-	      /* Mark the symbol as a Thumb function.  */
-	      if (   S_GET_STORAGE_CLASS (sym) == C_STAT
-		  || S_GET_STORAGE_CLASS (sym) == C_LABEL)  /* This can happen!  */
-		S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
-
-	      else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
-		S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
-	      else
-		as_bad (_("%s: unexpected function type: %d"),
-			S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
-	    }
-	  else switch (S_GET_STORAGE_CLASS (sym))
-	    {
-	    case C_EXT:
-	      S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
-	      break;
-	    case C_STAT:
-	      S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
-	      break;
-	    case C_LABEL:
-	      S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
-	      break;
-	    default:
-	      /* Do nothing.  */
-	      break;
-	    }
-	}
-
-      if (ARM_IS_INTERWORK (sym))
-	coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
-    }
-#endif
-#ifdef OBJ_ELF
-  symbolS * sym;
-  char      bind;
+  int arch;
+  arm_feature_set flags;
+  arm_feature_set tmp;
+  const cpu_arch_ver_table *p;
 
-  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
+  /* Choose the architecture based on the capabilities of the requested cpu
+     (if any) and/or the instructions actually used.  */
+  ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
+  ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
+  ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
+  
+  tmp = flags;
+  arch = 0;
+  for (p = cpu_arch_ver; p->val; p++)
     {
-      if (ARM_IS_THUMB (sym))
+      if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
 	{
-	  elf_symbol_type * elf_sym;
-
-	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
-	  bind = ELF_ST_BIND (elf_sym);
-
-	  /* If it's a .thumb_func, declare it as so,
-	     otherwise tag label as .code 16.  */
-	  if (THUMB_IS_FUNC (sym))
-	    elf_sym->internal_elf_sym.st_info =
-	      ELF_ST_INFO (bind, STT_ARM_TFUNC);
-	  else
-	    elf_sym->internal_elf_sym.st_info =
-	      ELF_ST_INFO (bind, STT_ARM_16BIT);
+	  arch = p->val;
+	  ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
 	}
     }
-#endif
-}
 
-int
-arm_data_in_code ()
-{
-  if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
+  /* Tag_CPU_name.  */
+  if (selected_cpu_name[0])
     {
-      *input_line_pointer = '/';
-      input_line_pointer += 5;
-      *input_line_pointer = 0;
-      return 1;
-    }
-
-  return 0;
-}
-
-char *
-arm_canonicalize_symbol_name (name)
-     char * name;
-{
-  int len;
-
-  if (thumb_mode && (len = strlen (name)) > 5
-      && streq (name + len - 5, "/data"))
-    *(name + len - 5) = 0;
-
-  return name;
-}
+      char *p;
 
-#if defined OBJ_COFF || defined OBJ_ELF
+      p = selected_cpu_name;
+      if (strncmp(p, "armv", 4) == 0)
+	{
+	  int i;
+	  
+	  p += 4;
+	  for (i = 0; p[i]; i++)
+	    p[i] = TOUPPER (p[i]);
+	}
+      elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
+    }
+  /* Tag_CPU_arch.  */
+  elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
+  /* Tag_CPU_arch_profile.  */
+  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
+    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'A');
+  else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
+    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'R');
+  else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
+    elf32_arm_add_eabi_attr_int (stdoutput, 7, 'M');
+  /* Tag_ARM_ISA_use.  */
+  if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
+    elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
+  /* Tag_THUMB_ISA_use.  */
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
+    elf32_arm_add_eabi_attr_int (stdoutput, 9,
+	ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
+  /* Tag_VFP_arch.  */
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
+    elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
+  else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
+	   || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
+    elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
+  /* Tag_WMMX_arch.  */
+  if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
+      || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
+    elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
+}
+
+/* Add the .ARM.attributes section.  */
 void
-arm_validate_fix (fixP)
-     fixS * fixP;
+arm_md_end (void)
 {
-  /* If the destination of the branch is a defined symbol which does not have
-     the THUMB_FUNC attribute, then we must be calling a function which has
-     the (interfacearm) attribute.  We look for the Thumb entry point to that
-     function and change the branch to refer to that function instead.  */
-  if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
-      && fixP->fx_addsy != NULL
-      && S_IS_DEFINED (fixP->fx_addsy)
-      && ! THUMB_IS_FUNC (fixP->fx_addsy))
-    {
-      fixP->fx_addsy = find_real_start (fixP->fx_addsy);
-    }
-}
-#endif
-
-int
-arm_force_relocation (fixp)
-     struct fix * fixp;
-{
-#if defined (OBJ_COFF) && defined (TE_PE)
-  if (fixp->fx_r_type == BFD_RELOC_RVA)
-    return 1;
-#endif
-#ifdef OBJ_ELF
-  if (fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
-      || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
-      || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
-      || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
-    return 1;
-#endif
-
-  /* Resolve these relocations even if the symbol is extern or weak.  */
-  if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
-      || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
-      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
-    return 0;
-
-  return generic_force_reloc (fixp);
-}
-
-#ifdef OBJ_COFF
-/* This is a little hack to help the gas/arm/adrl.s test.  It prevents
-   local labels from being added to the output symbol table when they
-   are used with the ADRL pseudo op.  The ADRL relocation should always
-   be resolved before the binbary is emitted, so it is safe to say that
-   it is adjustable.  */
+  segT s;
+  char *p;
+  addressT addr;
+  offsetT size;
+  
+  if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
+    return;
 
-bfd_boolean
-arm_fix_adjustable (fixP)
-   fixS * fixP;
-{
-  if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
-    return 1;
-  return 0;
+  aeabi_set_public_attributes ();
+  size = elf32_arm_eabi_attr_size (stdoutput);
+  s = subseg_new (".ARM.attributes", 0);
+  bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
+  addr = frag_now_fix ();
+  p = frag_more (size);
+  elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
 }
-#endif
 
-#ifdef OBJ_ELF
-/* Relocations against Thumb function names must be left unadjusted,
-   so that the linker can use this information to correctly set the
-   bottom bit of their addresses.  The MIPS version of this function
-   also prevents relocations that are mips-16 specific, but I do not
-   know why it does this.
 
-   FIXME:
-   There is one other problem that ought to be addressed here, but
-   which currently is not:  Taking the address of a label (rather
-   than a function) and then later jumping to that address.  Such
-   addresses also ought to have their bottom bit set (assuming that
-   they reside in Thumb code), but at the moment they will not.  */
+/* Parse a .cpu directive.  */
 
-bfd_boolean
-arm_fix_adjustable (fixP)
-   fixS * fixP;
+static void
+s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
 {
-  if (fixP->fx_addsy == NULL)
-    return 1;
-
-  if (THUMB_IS_FUNC (fixP->fx_addsy)
-      && fixP->fx_subsy == NULL)
-    return 0;
-
-  /* We need the symbol name for the VTABLE entries.  */
-  if (   fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
-      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
-    return 0;
-
-  /* Don't allow symbols to be discarded on GOT related relocs.  */
-  if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
-      || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
-      || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF)
-    return 0;
-
-  return 1;
-}
+  const struct arm_cpu_option_table *opt;
+  char *name;
+  char saved_char;
 
-const char *
-elf32_arm_target_format ()
-{
-  if (target_big_endian)
-    {
-      if (target_oabi)
-	return "elf32-bigarm-oabi";
-      else
-	return "elf32-bigarm";
-    }
-  else
-    {
-      if (target_oabi)
-	return "elf32-littlearm-oabi";
-      else
-	return "elf32-littlearm";
-    }
-}
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
 
-void
-armelf_frob_symbol (symp, puntp)
-     symbolS * symp;
-     int *     puntp;
-{
-  elf_frob_symbol (symp, puntp);
+  /* Skip the first "all" entry.  */
+  for (opt = arm_cpus + 1; opt->name != NULL; opt++)
+    if (streq (opt->name, name))
+      {
+	mcpu_cpu_opt = &opt->value;
+	selected_cpu = opt->value;
+	if (opt->canonical_name)
+	  strcpy(selected_cpu_name, opt->canonical_name);
+	else
+	  {
+	    int i;
+	    for (i = 0; opt->name[i]; i++)
+	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
+	    selected_cpu_name[i] = 0;
+	  }
+	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+	*input_line_pointer = saved_char;
+	demand_empty_rest_of_line ();
+	return;
+      }
+  as_bad (_("unknown cpu `%s'"), name);
+  *input_line_pointer = saved_char;
+  ignore_rest_of_line ();
 }
 
-static bfd_reloc_code_real_type
-arm_parse_reloc ()
-{
-  char         id [16];
-  char *       ip;
-  unsigned int i;
-  static struct
-  {
-    char * str;
-    int    len;
-    bfd_reloc_code_real_type reloc;
-  }
-  reloc_map[] =
-  {
-#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
-    MAP ("(got)",    BFD_RELOC_ARM_GOT32),
-    MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
-    /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
-       branch instructions generated by GCC for PLT relocs.  */
-    MAP ("(plt)",    BFD_RELOC_ARM_PLT32),
-    { NULL, 0,         BFD_RELOC_UNUSED }
-#undef MAP
-  };
-
-  for (i = 0, ip = input_line_pointer;
-       i < sizeof (id) && (ISALNUM (*ip) || ISPUNCT (*ip));
-       i++, ip++)
-    id[i] = TOLOWER (*ip);
-
-  for (i = 0; reloc_map[i].str; i++)
-    if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
-      break;
-
-  input_line_pointer += reloc_map[i].len;
 
-  return reloc_map[i].reloc;
-}
+/* Parse a .arch directive.  */
 
 static void
-s_arm_elf_cons (nbytes)
-     int nbytes;
+s_arm_arch (int ignored ATTRIBUTE_UNUSED)
 {
-  expressionS exp;
-
-#ifdef md_flush_pending_output
-  md_flush_pending_output ();
-#endif
-
-  if (is_it_end_of_statement ())
-    {
-      demand_empty_rest_of_line ();
-      return;
-    }
-
-#ifdef md_cons_align
-  md_cons_align (nbytes);
-#endif
-
-  mapping_state (MAP_DATA);
-  do
-    {
-      bfd_reloc_code_real_type reloc;
-
-      expression (& exp);
-
-      if (exp.X_op == O_symbol
-	  && * input_line_pointer == '('
-	  && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
-	{
-	  reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
-	  int size = bfd_get_reloc_size (howto);
+  const struct arm_arch_option_table *opt;
+  char saved_char;
+  char *name;
 
-	  if (size > nbytes)
-	    as_bad ("%s relocations do not fit in %d bytes",
-		    howto->name, nbytes);
-	  else
-	    {
-	      register char *p = frag_more ((int) nbytes);
-	      int offset = nbytes - size;
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
 
-	      fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
-			   &exp, 0, reloc);
-	    }
-	}
-      else
-	emit_expr (&exp, (unsigned int) nbytes);
-    }
-  while (*input_line_pointer++ == ',');
+  /* Skip the first "all" entry.  */
+  for (opt = arm_archs + 1; opt->name != NULL; opt++)
+    if (streq (opt->name, name))
+      {
+	mcpu_cpu_opt = &opt->value;
+	selected_cpu = opt->value;
+	strcpy(selected_cpu_name, opt->name);
+	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+	*input_line_pointer = saved_char;
+	demand_empty_rest_of_line ();
+	return;
+      }
 
-  /* Put terminator back into stream.  */
-  input_line_pointer --;
-  demand_empty_rest_of_line ();
+  as_bad (_("unknown architecture `%s'\n"), name);
+  *input_line_pointer = saved_char;
+  ignore_rest_of_line ();
 }
 
-#endif /* OBJ_ELF */
-
-/* This is called from HANDLE_ALIGN in write.c.  Fill in the contents
-   of an rs_align_code fragment.  */
-
-void
-arm_handle_align (fragP)
-     fragS *fragP;
-{
-  static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
-  static char const thumb_noop[2] = { 0xc0, 0x46 };
-  static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
-  static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
-
-  int bytes, fix, noop_size;
-  char * p;
-  const char * noop;
-
-  if (fragP->fr_type != rs_align_code)
-    return;
-
-  bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
-  p = fragP->fr_literal + fragP->fr_fix;
-  fix = 0;
-
-  if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
-    bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
-
-  if (fragP->tc_frag_data)
-    {
-      if (target_big_endian)
-	noop = thumb_bigend_noop;
-      else
-	noop = thumb_noop;
-      noop_size = sizeof (thumb_noop);
-    }
-  else
-    {
-      if (target_big_endian)
-	noop = arm_bigend_noop;
-      else
-	noop = arm_noop;
-      noop_size = sizeof (arm_noop);
-    }
-
-  if (bytes & (noop_size - 1))
-    {
-      fix = bytes & (noop_size - 1);
-      memset (p, 0, fix);
-      p += fix;
-      bytes -= fix;
-    }
 
-  while (bytes >= noop_size)
-    {
-      memcpy (p, noop, noop_size);
-      p += noop_size;
-      bytes -= noop_size;
-      fix += noop_size;
-    }
-
-  fragP->fr_fix += fix;
-  fragP->fr_var = noop_size;
-}
-
-/* Called from md_do_align.  Used to create an alignment
-   frag in a code section.  */
+/* Parse a .fpu directive.  */
 
-void
-arm_frag_align_code (n, max)
-     int n;
-     int max;
+static void
+s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
 {
-  char * p;
-
-  /* We assume that there will never be a requirement
-     to support alignments greater than 32 bytes.  */
-  if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
-    as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
+  const struct arm_option_cpu_value_table *opt;
+  char saved_char;
+  char *name;
 
-  p = frag_var (rs_align_code,
-		MAX_MEM_FOR_RS_ALIGN_CODE,
-		1,
-		(relax_substateT) max,
-		(symbolS *) NULL,
-		(offsetT) n,
-		(char *) NULL);
-  *p = 0;
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
+  
+  for (opt = arm_fpus; opt->name != NULL; opt++)
+    if (streq (opt->name, name))
+      {
+	mfpu_opt = &opt->value;
+	ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
+	*input_line_pointer = saved_char;
+	demand_empty_rest_of_line ();
+	return;
+      }
 
+  as_bad (_("unknown floating point format `%s'\n"), name);
+  *input_line_pointer = saved_char;
+  ignore_rest_of_line ();
 }
+#endif /* OBJ_ELF */
 
-/* Perform target specific initialisation of a frag.  */
-
-void
-arm_init_frag (fragP)
-     fragS *fragP;
-{
-  /* Record whether this frag is in an ARM or a THUMB area.  */
-  fragP->tc_frag_data = thumb_mode;
-}
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index 4e791a083f41..f2615770c47d 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -1,6 +1,6 @@
 /* This file is tc-arm.h
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2004
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004 Free Software Foundation, Inc.
    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
 	Modified by David Taylor (dtaylor@armltd.co.uk)
 
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_ARM 1
 
@@ -32,8 +32,6 @@
 #define COFF_MAGIC 	ARMMAGIC
 #define TARGET_ARCH 	bfd_arch_arm
 
-#define AOUT_MACHTYPE 	0
-
 #define DIFF_EXPR_OK
 
 #ifdef  LITTLE_ENDIAN
@@ -81,7 +79,12 @@ struct fix;
 
 #define TC_FORCE_RELOCATION(FIX) arm_force_relocation (FIX)
 
-#define md_convert_frag(b, s, f) { as_fatal (_("arm convert_frag\n")); }
+#define md_relax_frag(segment, fragp, stretch) \
+  arm_relax_frag(segment, fragp, stretch)
+extern int arm_relax_frag (asection *, struct frag *, long);
+
+#define md_optimize_expr(l,o,r)		arm_optimize_expr (l, o, r)
+extern int arm_optimize_expr (expressionS *, operatorT, expressionS *);
 
 #define md_cleanup() arm_cleanup ()
 
@@ -92,12 +95,17 @@ struct fix;
 /* We also need to mark assembler created symbols:  */
 #define tc_frob_fake_label(S) arm_frob_label (S)
 
+#ifdef OBJ_ELF
+#define md_end arm_md_end
+extern void arm_md_end (void);
+#endif
+
 /* NOTE: The fake label creation in stabs.c:s_stab_generic() has
    deliberately not been updated to mark assembler created stabs
    symbols as Thumb.  */
 
-#define TC_FIX_TYPE PTR
-#define TC_INIT_FIX_DATA(FIX) ((FIX)->tc_fix_data = NULL)
+#define TC_FIX_TYPE int
+#define TC_INIT_FIX_DATA(FIX) ((FIX)->tc_fix_data = 0)
 
 /* We need to keep some local information on symbols.  */
 
@@ -121,14 +129,13 @@ struct fix;
 #define TC_START_LABEL(C,STR)            (c == ':' || (c == '/' && arm_data_in_code ()))
 #define tc_canonicalize_symbol_name(str) arm_canonicalize_symbol_name (str);
 #define obj_adjust_symtab() 		 arm_adjust_symtab ()
-#define tc_aout_pre_write_hook(x)	 {;}	/* not used */
 
 #define LISTING_HEADER "ARM GAS "
 
 #define OPTIONAL_REGISTER_PREFIX '%'
 
-#define LOCAL_LABEL(name) (name[0] == '.' && (name[1] == 'L'))
-#define LOCAL_LABELS_FB   1
+#define LOCAL_LABEL(name)  (name[0] == '.' && name[1] == 'L')
+#define LOCAL_LABELS_FB    1
 
 /* This expression evaluates to true if the relocation is for a local
    object for which we still want to do the relocation at runtime.
@@ -140,11 +147,16 @@ struct fix;
 #define TC_FORCE_RELOCATION_LOCAL(FIX)			\
   (!(FIX)->fx_pcrel					\
    || (FIX)->fx_plt					\
-   || (FIX)->fx_r_type == BFD_RELOC_ARM_GOT12		\
    || (FIX)->fx_r_type == BFD_RELOC_ARM_GOT32		\
    || (FIX)->fx_r_type == BFD_RELOC_32			\
    || TC_FORCE_RELOCATION (FIX))
 
+/* Force output of R_ARM_REL32 relocations against thumb function symbols.
+   This is needed to ensure the low bit is handled correctly.  */
+#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG)	\
+  (THUMB_IS_FUNC ((FIX)->fx_addsy)		\
+   || !SEG_NORMAL (SEG))
+
 #define TC_CONS_FIX_NEW cons_fix_new_arm
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE 31
@@ -167,9 +179,9 @@ struct fix;
 # define DWARF2_LINE_MIN_INSN_LENGTH 	2
 # define obj_frob_symbol(sym, punt)	armelf_frob_symbol ((sym), & (punt))
 # define md_elf_section_change_hook()	arm_elf_change_section ()
+# define md_elf_section_type(str, len)	arm_elf_section_type (str, len)
 # define GLOBAL_OFFSET_TABLE_NAME	"_GLOBAL_OFFSET_TABLE_"
-# define LOCAL_LABEL_PREFIX 		'.'
-# define TC_SEGMENT_INFO_TYPE 		enum mstate
+# define TC_SEGMENT_INFO_TYPE 		struct arm_segment_info_type
 
 enum mstate
 {
@@ -179,6 +191,25 @@ enum mstate
   MAP_THUMB
 };
 
+struct arm_segment_info_type
+{
+  enum mstate mapstate;
+  unsigned int marked_pr_dependency;
+};
+
+/* We want .cfi_* pseudo-ops for generating unwind info.  */
+#define TARGET_USE_CFIPOP              1
+
+/* The lr register is r14.  */
+#define DWARF2_DEFAULT_RETURN_COLUMN  14
+
+/* Registers are generally saved at negative offsets to the CFA.  */
+#define DWARF2_CIE_DATA_ALIGNMENT     -4
+
+/* CFI hooks.  */
+#define tc_regname_to_dw2regnum            tc_arm_regname_to_dw2regnum
+#define tc_cfi_frame_initial_instructions  tc_arm_frame_initial_instructions
+
 #else /* Not OBJ_ELF.  */
 #define GLOBAL_OFFSET_TABLE_NAME "__GLOBAL_OFFSET_TABLE_"
 #endif
@@ -187,12 +218,15 @@ enum mstate
 
 # define EXTERN_FORCE_RELOC 			1
 # define tc_fix_adjustable(FIX) 		arm_fix_adjustable (FIX)
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 # define MD_APPLY_SYM_VALUE(FIX) 		0
 # define TC_VALIDATE_FIX(FIX, SEGTYPE, LABEL)	arm_validate_fix (FIX)
 
 #endif
 
+#define MD_PCREL_FROM_SECTION(F,S) md_pcrel_from_section(F,S)
+
+extern long md_pcrel_from_section (struct fix *, segT);
 extern void arm_frag_align_code (int, int);
 extern void arm_validate_fix (struct fix *);
 extern const char * elf32_arm_target_format (void);
@@ -209,3 +243,6 @@ extern void cons_fix_new_arm (fragS *, int, int, expressionS *);
 extern void arm_init_frag (struct frag *);
 extern void arm_handle_align (struct frag *);
 extern bfd_boolean arm_fix_adjustable (struct fix *);
+extern int arm_elf_section_type (const char *, size_t);
+extern int tc_arm_regname_to_dw2regnum (const char *regname);
+extern void tc_arm_frame_initial_instructions (void);
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c
index 43b4b7167a7c..7a95033d53a3 100644
--- a/gas/config/tc-avr.c
+++ b/gas/config/tc-avr.c
@@ -1,6 +1,7 @@
 /* tc-avr.c -- Assembler code for the ATMEL AVR
 
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2006
+   Free Software Foundation, Inc.
    Contributed by Denis Chertykov <denisc@overta.ru>
 
    This file is part of GAS, the GNU Assembler.
@@ -17,21 +18,22 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
 #include "subsegs.h"
+#include "libiberty.h"
 
 struct avr_opcodes_s
 {
-  char *name;
-  char *constraints;
-  int insn_size;		/* In words.  */
-  int isa;
-  unsigned int bin_opcode;
+  char *        name;
+  char *        constraints;
+  int           insn_size;		/* In words.  */
+  int           isa;
+  unsigned int  bin_opcode;
 };
 
 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
@@ -62,7 +64,7 @@ struct mcu_type_s
 static struct mcu_type_s mcu_types[] =
 {
   {"avr1",      AVR_ISA_TINY1,    bfd_mach_avr1},
-  {"avr2",      AVR_ISA_2xxx,     bfd_mach_avr2},
+  {"avr2",      AVR_ISA_TINY2,    bfd_mach_avr2},
   {"avr3",      AVR_ISA_M103,     bfd_mach_avr3},
   {"avr4",      AVR_ISA_M8,       bfd_mach_avr4},
   {"avr5",      AVR_ISA_ALL,      bfd_mach_avr5},
@@ -85,46 +87,86 @@ static struct mcu_type_s mcu_types[] =
   {"at90s8535", AVR_ISA_2xxx,     bfd_mach_avr2},
   {"at90c8534", AVR_ISA_2xxx,     bfd_mach_avr2},
   {"at86rf401", AVR_ISA_2xxx,     bfd_mach_avr2},
+  {"attiny13",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny2313",AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny261", AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny461", AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny861", AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny24",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny44",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny84",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny25",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny45",  AVR_ISA_TINY2,    bfd_mach_avr2},
+  {"attiny85",  AVR_ISA_TINY2,    bfd_mach_avr2},
   {"atmega603", AVR_ISA_M603,     bfd_mach_avr3}, /* XXX -> m103 */
   {"atmega103", AVR_ISA_M103,     bfd_mach_avr3},
   {"at43usb320",AVR_ISA_M103,     bfd_mach_avr3},
   {"at43usb355",AVR_ISA_M603,     bfd_mach_avr3},
   {"at76c711",  AVR_ISA_M603,     bfd_mach_avr3},
+  {"atmega48",  AVR_ISA_PWMx,     bfd_mach_avr4},
   {"atmega8",   AVR_ISA_M8,       bfd_mach_avr4},
   {"atmega83",  AVR_ISA_M8,       bfd_mach_avr4}, /* XXX -> m8535 */
   {"atmega85",  AVR_ISA_M8,       bfd_mach_avr4}, /* XXX -> m8 */
+  {"atmega88",  AVR_ISA_PWMx,     bfd_mach_avr4},
   {"atmega8515",AVR_ISA_M8,       bfd_mach_avr4},
   {"atmega8535",AVR_ISA_M8,       bfd_mach_avr4},
+  {"at90pwm2",  AVR_ISA_PWMx,     bfd_mach_avr4},
+  {"at90pwm3",  AVR_ISA_PWMx,     bfd_mach_avr4},
   {"atmega16",  AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega161", AVR_ISA_M161,     bfd_mach_avr5},
   {"atmega162", AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega163", AVR_ISA_M161,     bfd_mach_avr5},
+  {"atmega164", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega165", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega168", AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega169", AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega32",  AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega323", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega324", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega325", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega329", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega3250",AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega3290",AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega406", AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega64",  AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega640", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega644", AVR_ISA_M323,     bfd_mach_avr5},
   {"atmega128", AVR_ISA_M128,     bfd_mach_avr5},
+  {"atmega1280",AVR_ISA_M128,     bfd_mach_avr5},
+  {"atmega1281",AVR_ISA_M128,     bfd_mach_avr5},
+  {"atmega645", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega649", AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega6450",AVR_ISA_M323,     bfd_mach_avr5},
+  {"atmega6490",AVR_ISA_M323,     bfd_mach_avr5},
+  {"at90can32" ,AVR_ISA_M323,     bfd_mach_avr5},
+  {"at90can64" ,AVR_ISA_M323,     bfd_mach_avr5},
+  {"at90can128",AVR_ISA_M128,     bfd_mach_avr5},
+  {"at90usb646", AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90usb647", AVR_ISA_M323,    bfd_mach_avr5},
+  {"at90usb1286",AVR_ISA_M128,    bfd_mach_avr5},
+  {"at90usb1287",AVR_ISA_M128,    bfd_mach_avr5},
   {"at94k",     AVR_ISA_94K,      bfd_mach_avr5},
   {NULL, 0, 0}
 };
 
 /* Current MCU type.  */
-static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_2xxx,bfd_mach_avr2};
-static struct mcu_type_s *avr_mcu = &default_mcu;
+static struct mcu_type_s   default_mcu = {"avr2", AVR_ISA_2xxx,bfd_mach_avr2};
+static struct mcu_type_s * avr_mcu = & default_mcu;
 
 /* AVR target-specific switches.  */
 struct avr_opt_s
 {
-  int all_opcodes;  /* -mall-opcodes: accept all known AVR opcodes  */
-  int no_skip_bug;  /* -mno-skip-bug: no warnings for skipping 2-word insns  */
-  int no_wrap;      /* -mno-wrap: reject rjmp/rcall with 8K wrap-around  */
+  int all_opcodes;  /* -mall-opcodes: accept all known AVR opcodes.  */
+  int no_skip_bug;  /* -mno-skip-bug: no warnings for skipping 2-word insns.  */
+  int no_wrap;      /* -mno-wrap: reject rjmp/rcall with 8K wrap-around.  */
 };
 
 static struct avr_opt_s avr_opt = { 0, 0, 0 };
 
 const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "dD";
-static void avr_set_arch (int dummy);
+
+static void avr_set_arch (int);
 
 /* The target specific pseudo-ops which we support.  */
 const pseudo_typeS md_pseudo_table[] =
@@ -135,27 +177,17 @@ const pseudo_typeS md_pseudo_table[] =
 
 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
 
-static void show_mcu_list PARAMS ((FILE *));
-static char *skip_space PARAMS ((char *));
-static char *extract_word PARAMS ((char *, char *, int));
-static unsigned int avr_operand PARAMS ((struct avr_opcodes_s *,
-					 int, char *, char **));
-static unsigned int avr_operands PARAMS ((struct avr_opcodes_s *, char **));
-static unsigned int avr_get_constant PARAMS ((char *, int));
-static char *parse_exp PARAMS ((char *, expressionS *));
-static bfd_reloc_code_real_type avr_ldi_expression PARAMS ((expressionS *));
-
-#define EXP_MOD_NAME(i) exp_mod[i].name
-#define EXP_MOD_RELOC(i) exp_mod[i].reloc
-#define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
-#define HAVE_PM_P(i) exp_mod[i].have_pm
+#define EXP_MOD_NAME(i)       exp_mod[i].name
+#define EXP_MOD_RELOC(i)      exp_mod[i].reloc
+#define EXP_MOD_NEG_RELOC(i)  exp_mod[i].neg_reloc
+#define HAVE_PM_P(i)          exp_mod[i].have_pm
 
 struct exp_mod_s
 {
-  char *name;
-  bfd_reloc_code_real_type reloc;
-  bfd_reloc_code_real_type neg_reloc;
-  int have_pm;
+  char *                    name;
+  bfd_reloc_code_real_type  reloc;
+  bfd_reloc_code_real_type  neg_reloc;
+  int                       have_pm;
 };
 
 static struct exp_mod_s exp_mod[] =
@@ -166,10 +198,18 @@ static struct exp_mod_s exp_mod[] =
   {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
   {"lo8",    BFD_RELOC_AVR_LO8_LDI,    BFD_RELOC_AVR_LO8_LDI_NEG,    1},
   {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
-  {"hlo8",   -BFD_RELOC_AVR_LO8_LDI,   -BFD_RELOC_AVR_LO8_LDI_NEG,   0},
-  {"hhi8",   -BFD_RELOC_AVR_HI8_LDI,   -BFD_RELOC_AVR_HI8_LDI_NEG,   0},
+  {"hlo8",   BFD_RELOC_AVR_HH8_LDI,    BFD_RELOC_AVR_HH8_LDI_NEG,    0},
+  {"hhi8",   BFD_RELOC_AVR_MS8_LDI,    BFD_RELOC_AVR_MS8_LDI_NEG,    0},
 };
 
+/* A union used to store indicies into the exp_mod[] array
+   in a hash table which expects void * data types.  */
+typedef union
+{
+  void * ptr;
+  int    index;
+} mod_index;
+
 /* Opcode hash table.  */
 static struct hash_control *avr_hash;
 
@@ -177,9 +217,12 @@ static struct hash_control *avr_hash;
 static struct hash_control *avr_mod_hash;
 
 #define OPTION_MMCU 'm'
-#define OPTION_ALL_OPCODES (OPTION_MD_BASE + 1)
-#define OPTION_NO_SKIP_BUG (OPTION_MD_BASE + 2)
-#define OPTION_NO_WRAP     (OPTION_MD_BASE + 3)
+enum options
+{
+  OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
+  OPTION_NO_SKIP_BUG,
+  OPTION_NO_WRAP
+};
 
 struct option md_longopts[] =
 {
@@ -195,8 +238,7 @@ size_t md_longopts_size = sizeof (md_longopts);
 /* Display nicely formatted list of known MCU names.  */
 
 static void
-show_mcu_list (stream)
-     FILE *stream;
+show_mcu_list (FILE *stream)
 {
   int i, x;
 
@@ -222,8 +264,7 @@ show_mcu_list (stream)
 }
 
 static inline char *
-skip_space (s)
-     char *s;
+skip_space (char *s)
 {
   while (*s == ' ' || *s == '\t')
     ++s;
@@ -256,17 +297,15 @@ extract_word (char *from, char *to, int limit)
 }
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream,
       _("AVR options:\n"
@@ -288,21 +327,17 @@ md_show_usage (stream)
 }
 
 static void
-avr_set_arch (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+avr_set_arch (int dummy ATTRIBUTE_UNUSED)
 {
-  char *str;
+  char str[20];
 
-  str = (char *) alloca (20);
   input_line_pointer = extract_word (input_line_pointer, str, 20);
   md_parse_option (OPTION_MMCU, str);
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -355,10 +390,9 @@ md_parse_option (c, arg)
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
-  return 0;
+  return NULL;
 }
 
 /* Turn a string in input_line_pointer into a floating point constant
@@ -367,10 +401,7 @@ md_undefined_symbol (name)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -407,19 +438,19 @@ md_atof (type, litP, sizeP)
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
 {
   abort ();
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   unsigned int i;
   struct avr_opcodes_s *opcode;
+
   avr_hash = hash_new ();
 
   /* Insert unique names into hash table.  This hash table then provides a
@@ -430,8 +461,13 @@ md_begin ()
 
   avr_mod_hash = hash_new ();
 
-  for (i = 0; i < sizeof (exp_mod) / sizeof (exp_mod[0]); ++i)
-    hash_insert (avr_mod_hash, EXP_MOD_NAME (i), (void *) (i + 10));
+  for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
+    {
+      mod_index m;
+
+      m.index = i + 10;
+      hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
+    }
 
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
 }
@@ -440,14 +476,13 @@ md_begin ()
    If result greater than MAX then error.  */
 
 static unsigned int
-avr_get_constant (str, max)
-     char *str;
-     int max;
+avr_get_constant (char *str, int max)
 {
   expressionS ex;
+
   str = skip_space (str);
   input_line_pointer = str;
-  expression (&ex);
+  expression (& ex);
 
   if (ex.X_op != O_constant)
     as_bad (_("constant value required"));
@@ -458,102 +493,151 @@ avr_get_constant (str, max)
   return ex.X_add_number;
 }
 
-/* Parse instruction operands.
-   Return binary opcode.  */
+/* Parse for ldd/std offset.  */
 
-static unsigned int
-avr_operands (opcode, line)
-     struct avr_opcodes_s *opcode;
-     char **line;
+static void
+avr_offset_expression (expressionS *exp)
 {
-  char *op = opcode->constraints;
-  unsigned int bin = opcode->bin_opcode;
-  char *frag = frag_more (opcode->insn_size * 2);
-  char *str = *line;
-  int where = frag - frag_now->fr_literal;
-  static unsigned int prev = 0;  /* Previous opcode.  */
+  char *str = input_line_pointer;
+  char *tmp;
+  char op[8];
 
-  /* Opcode have operands.  */
-  if (*op)
+  tmp = str;
+  str = extract_word (str, op, sizeof (op));
+
+  input_line_pointer = tmp;
+  expression (exp);
+
+  /* Warn about expressions that fail to use lo8 ().  */
+  if (exp->X_op == O_constant)
     {
-      unsigned int reg1 = 0;
-      unsigned int reg2 = 0;
-      int reg1_present = 0;
-      int reg2_present = 0;
+      int x = exp->X_add_number;
+      
+      if (x < -255 || x > 255)
+	as_warn (_("constant out of 8-bit range: %d"), x);
+    }
+}
 
-      /* Parse first operand.  */
-      if (REGISTER_P (*op))
-	reg1_present = 1;
-      reg1 = avr_operand (opcode, where, op, &str);
-      ++op;
+/* Parse ordinary expression.  */
 
-      /* Parse second operand.  */
-      if (*op)
+static char *
+parse_exp (char *s, expressionS *op)
+{
+  input_line_pointer = s;
+  expression (op);
+  if (op->X_op == O_absent)
+    as_bad (_("missing operand"));
+  return input_line_pointer;
+}
+
+/* Parse special expressions (needed for LDI command):
+   xx8 (address)
+   xx8 (-address)
+   pm_xx8 (address)
+   pm_xx8 (-address)
+   where xx is: hh, hi, lo.  */
+
+static bfd_reloc_code_real_type
+avr_ldi_expression (expressionS *exp)
+{
+  char *str = input_line_pointer;
+  char *tmp;
+  char op[8];
+  int mod;
+  tmp = str;
+
+  str = extract_word (str, op, sizeof (op));
+
+  if (op[0])
+    {
+      mod_index m;
+      
+      m.ptr = hash_find (avr_mod_hash, op);
+      mod = m.index;
+
+      if (mod)
 	{
-	  if (*op == ',')
-	    ++op;
+	  int closes = 0;
 
-	  if (*op == '=')
-	    {
-	      reg2 = reg1;
-	      reg2_present = 1;
-	    }
-	  else
+	  mod -= 10;
+	  str = skip_space (str);
+
+	  if (*str == '(')
 	    {
-	      if (REGISTER_P (*op))
-		reg2_present = 1;
+	      int neg_p = 0;
 
-	      str = skip_space (str);
-	      if (*str++ != ',')
-		as_bad (_("`,' required"));
-	      str = skip_space (str);
+	      ++str;
 
-	      reg2 = avr_operand (opcode, where, op, &str);
+	      if (strncmp ("pm(", str, 3) == 0
+		  || strncmp ("-(pm(", str, 5) == 0)
+		{
+		  if (HAVE_PM_P (mod))
+		    {
+		      ++mod;
+		      ++closes;
+		    }
+		  else
+		    as_bad (_("illegal expression"));
 
-	    }
+		  if (*str == '-')
+		    {
+		      neg_p = 1;
+		      ++closes;
+		      str += 5;
+		    }
+		  else
+		    str += 3;
+		}
 
-	  if (reg1_present && reg2_present)
-	    reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
-	  else if (reg2_present)
-	    reg2 <<= 4;
+	      if (*str == '-' && *(str + 1) == '(')
+		{
+		  neg_p ^= 1;
+		  ++closes;
+		  str += 2;
+		}
+
+	      input_line_pointer = str;
+	      expression (exp);
+
+	      do
+		{
+		  if (*input_line_pointer != ')')
+		    {
+		      as_bad (_("`)' required"));
+		      break;
+		    }
+		  input_line_pointer++;
+		}
+	      while (closes--);
+
+	      return neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
+	    }
 	}
-      if (reg1_present)
-	reg1 <<= 4;
-      bin |= reg1 | reg2;
     }
 
-  /* Detect undefined combinations (like ld r31,Z+).  */
-  if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
-    as_warn (_("undefined combination of operands"));
+  input_line_pointer = tmp;
+  expression (exp);
 
-  if (opcode->insn_size == 2)
+  /* Warn about expressions that fail to use lo8 ().  */
+  if (exp->X_op == O_constant)
     {
-      /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
-         (AVR core bug, fixed in the newer devices).  */
-
-      if (!(avr_opt.no_skip_bug || (avr_mcu->isa & AVR_ISA_MUL))
-	  && AVR_SKIP_P (prev))
-	as_warn (_("skipping two-word instruction"));
+      int x = exp->X_add_number;
 
-      bfd_putl32 ((bfd_vma) bin, frag);
+      if (x < -255 || x > 255)
+	as_warn (_("constant out of 8-bit range: %d"), x);
     }
-  else
-    bfd_putl16 ((bfd_vma) bin, frag);
 
-  prev = bin;
-  *line = str;
-  return bin;
+  return BFD_RELOC_AVR_LDI;
 }
 
 /* Parse one instruction operand.
    Return operand bitmask.  Also fixups can be generated.  */
 
 static unsigned int
-avr_operand (opcode, where, op, line)
-     struct avr_opcodes_s *opcode;
-     int where;
-     char *op;
-     char **line;
+avr_operand (struct avr_opcodes_s *opcode,
+	     int where,
+	     char *op,
+	     char **line)
 {
   expressionS op_expr;
   unsigned int op_mask = 0;
@@ -683,10 +767,11 @@ avr_operand (opcode, where, op, line)
 	str = skip_space (str);
 	if (*str++ == '+')
 	  {
-	    unsigned int x;
-	    x = avr_get_constant (str, 63);
+	    input_line_pointer = str;
+	    avr_offset_expression (& op_expr);
 	    str = input_line_pointer;
-	    op_mask |= (x & 7) | ((x & (3 << 3)) << 7) | ((x & (1 << 5)) << 8);
+	    fix_new_exp (frag_now, where, 3,
+			 &op_expr, FALSE, BFD_RELOC_AVR_6);
 	  }
       }
       break;
@@ -738,13 +823,11 @@ avr_operand (opcode, where, op, line)
       break;
 
     case 'K':
-      {
-	unsigned int x;
-
-	x = avr_get_constant (str, 63);
-	str = input_line_pointer;
-	op_mask |= (x & 0xf) | ((x & 0x30) << 2);
-      }
+      input_line_pointer = str;
+      avr_offset_expression (& op_expr);
+      str = input_line_pointer;
+      fix_new_exp (frag_now, where, 3,
+		   & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
       break;
 
     case 'S':
@@ -791,13 +874,95 @@ avr_operand (opcode, where, op, line)
   return op_mask;
 }
 
+/* Parse instruction operands.
+   Return binary opcode.  */
+
+static unsigned int
+avr_operands (struct avr_opcodes_s *opcode, char **line)
+{
+  char *op = opcode->constraints;
+  unsigned int bin = opcode->bin_opcode;
+  char *frag = frag_more (opcode->insn_size * 2);
+  char *str = *line;
+  int where = frag - frag_now->fr_literal;
+  static unsigned int prev = 0;  /* Previous opcode.  */
+
+  /* Opcode have operands.  */
+  if (*op)
+    {
+      unsigned int reg1 = 0;
+      unsigned int reg2 = 0;
+      int reg1_present = 0;
+      int reg2_present = 0;
+
+      /* Parse first operand.  */
+      if (REGISTER_P (*op))
+	reg1_present = 1;
+      reg1 = avr_operand (opcode, where, op, &str);
+      ++op;
+
+      /* Parse second operand.  */
+      if (*op)
+	{
+	  if (*op == ',')
+	    ++op;
+
+	  if (*op == '=')
+	    {
+	      reg2 = reg1;
+	      reg2_present = 1;
+	    }
+	  else
+	    {
+	      if (REGISTER_P (*op))
+		reg2_present = 1;
+
+	      str = skip_space (str);
+	      if (*str++ != ',')
+		as_bad (_("`,' required"));
+	      str = skip_space (str);
+
+	      reg2 = avr_operand (opcode, where, op, &str);
+	    }
+
+	  if (reg1_present && reg2_present)
+	    reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
+	  else if (reg2_present)
+	    reg2 <<= 4;
+	}
+      if (reg1_present)
+	reg1 <<= 4;
+      bin |= reg1 | reg2;
+    }
+
+  /* Detect undefined combinations (like ld r31,Z+).  */
+  if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
+    as_warn (_("undefined combination of operands"));
+
+  if (opcode->insn_size == 2)
+    {
+      /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
+         (AVR core bug, fixed in the newer devices).  */
+      if (!(avr_opt.no_skip_bug ||
+            (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
+	  && AVR_SKIP_P (prev))
+	as_warn (_("skipping two-word instruction"));
+
+      bfd_putl32 ((bfd_vma) bin, frag);
+    }
+  else
+    bfd_putl16 ((bfd_vma) bin, frag);
+
+  prev = bin;
+  *line = str;
+  return bin;
+}
+
 /* GAS will call this function for each section at the end of the assembly,
    to permit the CPU backend to adjust the alignment of a section.  */
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
   return ((addr + (1 << align) - 1) & (-1 << align));
@@ -810,9 +975,7 @@ md_section_align (seg, addr)
    macro would return the length of an instruction.  */
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec;
+md_pcrel_from_section (fixS *fixp, segT sec)
 {
   if (fixp->fx_addsy != (symbolS *) NULL
       && (!S_IS_DEFINED (fixp->fx_addsy)
@@ -826,10 +989,7 @@ md_pcrel_from_section (fixp, sec)
    value in the object file.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg;
+md_apply_fix (fixS *fixP, valueT * valP, segT seg)
 {
   unsigned char *where;
   unsigned long insn;
@@ -870,7 +1030,7 @@ md_apply_fix3 (fixP, valP, seg)
     {
       /* Fetch the instruction, insert the fully resolved operand
 	 value, and stuff the instruction back again.  */
-      where = fixP->fx_frag->fr_literal + fixP->fx_where;
+      where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
       insn = bfd_getl16 (where);
 
       switch (fixP->fx_r_type)
@@ -924,19 +1084,36 @@ md_apply_fix3 (fixP, valP, seg)
 	  bfd_putl16 ((bfd_vma) (value >> 1), where);
 	  break;
 
-	case BFD_RELOC_AVR_LO8_LDI:
+	case BFD_RELOC_AVR_LDI:
+	  if (value > 255)
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("operand out of range: %ld"), value);
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
 	  break;
 
-	case -BFD_RELOC_AVR_LO8_LDI:
-	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
+	case BFD_RELOC_AVR_6:
+	  if ((value > 63) || (value < 0))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("operand out of range: %ld"), value);
+	  bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) | ((value & (1 << 5)) << 8)), where);
+	  break;
+
+	case BFD_RELOC_AVR_6_ADIW:
+	  if ((value > 63) || (value < 0))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("operand out of range: %ld"), value);
+	  bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
+	  break;
+
+	case BFD_RELOC_AVR_LO8_LDI:
+	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
 	  break;
 
 	case BFD_RELOC_AVR_HI8_LDI:
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
 	  break;
 
-	case -BFD_RELOC_AVR_HI8_LDI:
+	case BFD_RELOC_AVR_MS8_LDI:
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
 	  break;
 
@@ -948,15 +1125,11 @@ md_apply_fix3 (fixP, valP, seg)
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
 	  break;
 
-	case -BFD_RELOC_AVR_LO8_LDI_NEG:
-	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
-	  break;
-
 	case BFD_RELOC_AVR_HI8_LDI_NEG:
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
 	  break;
 
-	case -BFD_RELOC_AVR_HI8_LDI_NEG:
+	case BFD_RELOC_AVR_MS8_LDI_NEG:
 	  bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
 	  break;
 
@@ -1027,26 +1200,50 @@ md_apply_fix3 (fixP, valP, seg)
     }
 }
 
-/* A `BFD_ASSEMBLER' GAS will call this to generate a reloc.  GAS
-   will pass the resulting reloc to `bfd_install_relocation'.  This
-   currently works poorly, as `bfd_install_relocation' often does the
-   wrong thing, and instances of `tc_gen_reloc' have been written to
-   work around the problems, which in turns makes it difficult to fix
-   `bfd_install_relocation'.  */
+/* GAS will call this to generate a reloc, passing the resulting reloc
+   to `bfd_install_relocation'.  This currently works poorly, as
+   `bfd_install_relocation' often does the wrong thing, and instances of
+   `tc_gen_reloc' have been written to work around the problems, which
+   in turns makes it difficult to fix `bfd_install_relocation'.  */
 
 /* If while processing a fixup, a reloc really needs to be created
    then it is done here.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
+	      fixS *fixp)
 {
   arelent *reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  if (fixp->fx_addsy && fixp->fx_subsy)
+    {
+      long value = 0;
+
+      if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
+          || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
+        {
+          as_bad_where (fixp->fx_file, fixp->fx_line,
+              "Difference of symbols in different sections is not supported");
+          return NULL;
+        }
+
+      /* We are dealing with two symbols defined in the same section. 
+         Let us fix-up them here.  */
+      value += S_GET_VALUE (fixp->fx_addsy);
+      value -= S_GET_VALUE (fixp->fx_subsy);
+
+      /* When fx_addsy and fx_subsy both are zero, md_apply_fix
+         only takes it's second operands for the fixup value.  */
+      fixp->fx_addsy = NULL;
+      fixp->fx_subsy = NULL;
+      md_apply_fix (fixp, (valueT *) &value, NULL);
+
+      return NULL;
+    }
+
+  reloc = xmalloc (sizeof (arelent));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
@@ -1069,8 +1266,7 @@ tc_gen_reloc (seg, fixp)
 }
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   struct avr_opcodes_s *opcode;
   char op[11];
@@ -1101,6 +1297,7 @@ md_assemble (str)
      but that is wrong.  Our caller assumes we don't change it.  */
   {
     char *t = input_line_pointer;
+
     avr_operands (opcode, &str);
     if (*skip_space (str))
       as_bad (_("garbage at end of line"));
@@ -1108,119 +1305,6 @@ md_assemble (str)
   }
 }
 
-/* Parse ordinary expression.  */
-
-static char *
-parse_exp (s, op)
-     char *s;
-     expressionS *op;
-{
-  input_line_pointer = s;
-  expression (op);
-  if (op->X_op == O_absent)
-    as_bad (_("missing operand"));
-  return input_line_pointer;
-}
-
-/* Parse special expressions (needed for LDI command):
-   xx8 (address)
-   xx8 (-address)
-   pm_xx8 (address)
-   pm_xx8 (-address)
-   where xx is: hh, hi, lo.  */
-
-static bfd_reloc_code_real_type
-avr_ldi_expression (exp)
-     expressionS *exp;
-{
-  char *str = input_line_pointer;
-  char *tmp;
-  char op[8];
-  int mod;
-  tmp = str;
-
-  str = extract_word (str, op, sizeof (op));
-
-  if (op[0])
-    {
-      mod = (int) hash_find (avr_mod_hash, op);
-
-      if (mod)
-	{
-	  int closes = 0;
-
-	  mod -= 10;
-	  str = skip_space (str);
-
-	  if (*str == '(')
-	    {
-	      int neg_p = 0;
-
-	      ++str;
-
-	      if (strncmp ("pm(", str, 3) == 0
-		  || strncmp ("-(pm(", str, 5) == 0)
-		{
-		  if (HAVE_PM_P (mod))
-		    {
-		      ++mod;
-		      ++closes;
-		    }
-		  else
-		    as_bad (_("illegal expression"));
-
-		  if (*str == '-')
-		    {
-		      neg_p = 1;
-		      ++closes;
-		      str += 5;
-		    }
-		  else
-		    str += 3;
-		}
-
-	      if (*str == '-' && *(str + 1) == '(')
-		{
-		  neg_p ^= 1;
-		  ++closes;
-		  str += 2;
-		}
-
-	      input_line_pointer = str;
-	      expression (exp);
-
-	      do
-		{
-		  if (*input_line_pointer != ')')
-		    {
-		      as_bad (_("`)' required"));
-		      break;
-		    }
-		  input_line_pointer++;
-		}
-	      while (closes--);
-
-	      return neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
-	    }
-	}
-    }
-
-  input_line_pointer = tmp;
-  expression (exp);
-
-  /* Warn about expressions that fail to use lo8 ().  */
-  if (exp->X_op == O_constant)
-    {
-      int x = exp->X_add_number;
-      if (x < -255 || x > 255)
-	as_warn (_("constant out of 8-bit range: %d"), x);
-    }
-  else
-    as_warn (_("expression possibly out of 8-bit range"));
-
-  return BFD_RELOC_AVR_LO8_LDI;
-}
-
 /* Flag to pass `pm' mode between `avr_parse_cons_expression' and
    `avr_cons_fix_new'.  */
 static int exp_mod_pm = 0;
@@ -1230,9 +1314,7 @@ static int exp_mod_pm = 0;
    Relocation: BFD_RELOC_AVR_16_PM.  */
 
 void
-avr_parse_cons_expression (exp, nbytes)
-     expressionS *exp;
-     int nbytes;
+avr_parse_cons_expression (expressionS *exp, int nbytes)
 {
   char *tmp;
 
@@ -1274,11 +1356,10 @@ avr_parse_cons_expression (exp, nbytes)
 }
 
 void
-avr_cons_fix_new (frag, where, nbytes, exp)
-     fragS *frag;
-     int where;
-     int nbytes;
-     expressionS *exp;
+avr_cons_fix_new (fragS *frag,
+		  int where,
+		  int nbytes,
+		  expressionS *exp)
 {
   if (exp_mod_pm == 0)
     {
diff --git a/gas/config/tc-avr.h b/gas/config/tc-avr.h
index 8a1a4eb9e308..61fc5941cd23 100644
--- a/gas/config/tc-avr.h
+++ b/gas/config/tc-avr.h
@@ -1,5 +1,5 @@
 /* This file is tc-avr.h
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
 
    Contributed by Denis Chertykov <denisc@overta.ru>
 
@@ -17,12 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#ifndef BFD_ASSEMBLER
- #error AVR support requires BFD_ASSEMBLER
-#endif
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* By convention, you should define this macro in the `.h' file.  For
    example, `tc-m68k.h' defines `TC_M68K'.  You might have to use this
@@ -57,13 +53,13 @@
 /* You may define this macro to parse an expression used in a data
    allocation pseudo-op such as `.word'.  You can use this to
    recognize relocation directives that may appear in such directives.  */
-#define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR,N)
-void avr_parse_cons_expression (expressionS *exp, int nbytes);
+#define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR, N)
+extern void avr_parse_cons_expression (expressionS *, int);
 
 /* You may define this macro to generate a fixup for a data
    allocation pseudo-op.  */
-#define TC_CONS_FIX_NEW(FRAG,WHERE,N,EXP) avr_cons_fix_new(FRAG,WHERE,N,EXP)
-void avr_cons_fix_new(fragS *frag,int where, int nbytes, expressionS *exp);
+#define TC_CONS_FIX_NEW(FRAG,WHERE,N,EXP) avr_cons_fix_new (FRAG, WHERE, N, EXP)
+extern void avr_cons_fix_new (fragS *,int, int, expressionS *);
 
 /* This should just call either `number_to_chars_bigendian' or
    `number_to_chars_littleendian', whichever is appropriate.  On
@@ -96,7 +92,7 @@ void avr_cons_fix_new(fragS *frag,int where, int nbytes, expressionS *exp);
    visible symbols can be overridden.  */
 #define EXTERN_FORCE_RELOC 0
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* If you define this macro, it should return the offset between the
@@ -104,8 +100,8 @@ void avr_cons_fix_new(fragS *frag,int where, int nbytes, expressionS *exp);
    relative adjustment should be made.  On many processors, the base
    of a PC relative instruction is the next instruction, so this
    macro would return the length of an instruction.  */
-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
 
 /* The number of bytes to put into a word in a listing.  This affects
    the way the bytes are clumped together in the listing.  For
@@ -124,3 +120,21 @@ extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
    also affected by this macro.  The default definition will set
    P2VAR to the truncated power of two of sizes up to eight bytes.  */
 #define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) (P2VAR) = 0
+
+/* We don't want gas to fixup the following program memory related relocations.
+   We will need them in case that we want to do linker relaxation.
+   We could in principle keep these fixups in gas when not relaxing.
+   However, there is no serious performance penilty when making the linker
+   make the fixup work.  */
+#define TC_VALIDATE_FIX(FIXP,SEG,SKIP)                     \
+ if (   (FIXP->fx_r_type == BFD_RELOC_AVR_7_PCREL          \
+      || FIXP->fx_r_type == BFD_RELOC_AVR_13_PCREL         \
+      || FIXP->fx_r_type == BFD_RELOC_AVR_LO8_LDI_PM       \
+      || FIXP->fx_r_type == BFD_RELOC_AVR_HI8_LDI_PM       \
+      || FIXP->fx_r_type == BFD_RELOC_AVR_HH8_LDI_PM       \
+      || FIXP->fx_r_type == BFD_RELOC_AVR_16_PM)           \
+     && (FIXP->fx_addsy))                                  \
+   {                                                       \
+     goto SKIP;                                            \
+   }
+
diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c
new file mode 100644
index 000000000000..43d48d624ea0
--- /dev/null
+++ b/gas/config/tc-bfin.c
@@ -0,0 +1,2029 @@
+/* tc-bfin.c -- Assembler for the ADI Blackfin.
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "struc-symbol.h"
+#include "obj-elf.h"
+#include "bfin-defs.h"
+#include "obstack.h"
+#include "safe-ctype.h"
+#ifdef OBJ_ELF
+#include "dwarf2dbg.h"
+#endif
+#include "libbfd.h"
+#include "elf/common.h"
+#include "elf/bfin.h"
+
+extern int yyparse (void);
+struct yy_buffer_state;
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+extern YY_BUFFER_STATE yy_scan_string (const char *yy_str);
+extern void yy_delete_buffer (YY_BUFFER_STATE b);
+static parse_state parse (char *line);
+static void bfin_s_bss PARAMS ((int));
+static int md_chars_to_number PARAMS ((char *, int));
+
+/* Global variables. */
+struct bfin_insn *insn;
+int last_insn_size;
+
+extern struct obstack mempool;
+FILE *errorf;
+
+/* Flags to set in the elf header */
+#define DEFAULT_FLAGS 0
+
+static flagword bfin_flags = DEFAULT_FLAGS;
+static const char *bfin_pic_flag = (const char *)0;
+
+/* Registers list.  */
+struct bfin_reg_entry
+{
+  const char *name;
+  int number;
+};
+
+static const struct bfin_reg_entry bfin_reg_info[] = {
+  {"R0.L", REG_RL0},
+  {"R1.L", REG_RL1},
+  {"R2.L", REG_RL2},
+  {"R3.L", REG_RL3},
+  {"R4.L", REG_RL4},
+  {"R5.L", REG_RL5},
+  {"R6.L", REG_RL6},
+  {"R7.L", REG_RL7},
+  {"R0.H", REG_RH0},
+  {"R1.H", REG_RH1},
+  {"R2.H", REG_RH2},
+  {"R3.H", REG_RH3},
+  {"R4.H", REG_RH4},
+  {"R5.H", REG_RH5},
+  {"R6.H", REG_RH6},
+  {"R7.H", REG_RH7},
+  {"R0", REG_R0},
+  {"R1", REG_R1},
+  {"R2", REG_R2},
+  {"R3", REG_R3},
+  {"R4", REG_R4},
+  {"R5", REG_R5},
+  {"R6", REG_R6},
+  {"R7", REG_R7},
+  {"P0", REG_P0},
+  {"P0.H", REG_P0},
+  {"P0.L", REG_P0},
+  {"P1", REG_P1},
+  {"P1.H", REG_P1},
+  {"P1.L", REG_P1},
+  {"P2", REG_P2},
+  {"P2.H", REG_P2},
+  {"P2.L", REG_P2},
+  {"P3", REG_P3},
+  {"P3.H", REG_P3},
+  {"P3.L", REG_P3},
+  {"P4", REG_P4},
+  {"P4.H", REG_P4},
+  {"P4.L", REG_P4},
+  {"P5", REG_P5},
+  {"P5.H", REG_P5},
+  {"P5.L", REG_P5},
+  {"SP", REG_SP},
+  {"SP.L", REG_SP},
+  {"SP.H", REG_SP},
+  {"FP", REG_FP},
+  {"FP.L", REG_FP},
+  {"FP.H", REG_FP},
+  {"A0x", REG_A0x},
+  {"A1x", REG_A1x},
+  {"A0w", REG_A0w},
+  {"A1w", REG_A1w},
+  {"A0.x", REG_A0x},
+  {"A1.x", REG_A1x},
+  {"A0.w", REG_A0w},
+  {"A1.w", REG_A1w},
+  {"A0", REG_A0},
+  {"A0.L", REG_A0},
+  {"A0.H", REG_A0},
+  {"A1", REG_A1},
+  {"A1.L", REG_A1},
+  {"A1.H", REG_A1},
+  {"I0", REG_I0},
+  {"I0.L", REG_I0},
+  {"I0.H", REG_I0},
+  {"I1", REG_I1},
+  {"I1.L", REG_I1},
+  {"I1.H", REG_I1},
+  {"I2", REG_I2},
+  {"I2.L", REG_I2},
+  {"I2.H", REG_I2},
+  {"I3", REG_I3},
+  {"I3.L", REG_I3},
+  {"I3.H", REG_I3},
+  {"M0", REG_M0},
+  {"M0.H", REG_M0},
+  {"M0.L", REG_M0},
+  {"M1", REG_M1},
+  {"M1.H", REG_M1},
+  {"M1.L", REG_M1},
+  {"M2", REG_M2},
+  {"M2.H", REG_M2},
+  {"M2.L", REG_M2},
+  {"M3", REG_M3},
+  {"M3.H", REG_M3},
+  {"M3.L", REG_M3},
+  {"B0", REG_B0},
+  {"B0.H", REG_B0},
+  {"B0.L", REG_B0},
+  {"B1", REG_B1},
+  {"B1.H", REG_B1},
+  {"B1.L", REG_B1},
+  {"B2", REG_B2},
+  {"B2.H", REG_B2},
+  {"B2.L", REG_B2},
+  {"B3", REG_B3},
+  {"B3.H", REG_B3},
+  {"B3.L", REG_B3},
+  {"L0", REG_L0},
+  {"L0.H", REG_L0},
+  {"L0.L", REG_L0},
+  {"L1", REG_L1},
+  {"L1.H", REG_L1},
+  {"L1.L", REG_L1},
+  {"L2", REG_L2},
+  {"L2.H", REG_L2},
+  {"L2.L", REG_L2},
+  {"L3", REG_L3},
+  {"L3.H", REG_L3},
+  {"L3.L", REG_L3},
+  {"AZ", S_AZ},
+  {"AN", S_AN},
+  {"AC0", S_AC0},
+  {"AC1", S_AC1},
+  {"AV0", S_AV0},
+  {"AV0S", S_AV0S},
+  {"AV1", S_AV1},
+  {"AV1S", S_AV1S},
+  {"AQ", S_AQ},
+  {"V", S_V},
+  {"VS", S_VS},
+  {"sftreset", REG_sftreset},
+  {"omode", REG_omode},
+  {"excause", REG_excause},
+  {"emucause", REG_emucause},
+  {"idle_req", REG_idle_req},
+  {"hwerrcause", REG_hwerrcause},
+  {"CC", REG_CC},
+  {"LC0", REG_LC0},
+  {"LC1", REG_LC1},
+  {"ASTAT", REG_ASTAT},
+  {"RETS", REG_RETS},
+  {"LT0", REG_LT0},
+  {"LB0", REG_LB0},
+  {"LT1", REG_LT1},
+  {"LB1", REG_LB1},
+  {"CYCLES", REG_CYCLES},
+  {"CYCLES2", REG_CYCLES2},
+  {"USP", REG_USP},
+  {"SEQSTAT", REG_SEQSTAT},
+  {"SYSCFG", REG_SYSCFG},
+  {"RETI", REG_RETI},
+  {"RETX", REG_RETX},
+  {"RETN", REG_RETN},
+  {"RETE", REG_RETE},
+  {"EMUDAT", REG_EMUDAT},
+  {0, 0}
+};
+
+/* Blackfin specific function to handle FD-PIC pointer initializations.  */
+
+static void
+bfin_pic_ptr (int nbytes)
+{
+  expressionS exp;
+  char *p;
+
+  if (nbytes != 4)
+    abort ();
+
+#ifdef md_flush_pending_output
+  md_flush_pending_output ();
+#endif
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+#ifdef md_cons_align
+  md_cons_align (nbytes);
+#endif
+
+  do
+    {
+      bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC;
+      
+      if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
+	{
+	  input_line_pointer += 9;
+	  expression (&exp);
+	  if (*input_line_pointer == ')')
+	    input_line_pointer++;
+	  else
+	    as_bad ("missing ')'");
+	}
+      else
+	error ("missing funcdesc in picptr");
+
+      p = frag_more (4);
+      memset (p, 0, 4);
+      fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
+		   reloc_type);
+    }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;			/* Put terminator back into stream. */
+  demand_empty_rest_of_line ();
+}
+
+static void
+bfin_s_bss (int ignore ATTRIBUTE_UNUSED)
+{
+  register int temp;
+
+  temp = get_absolute_expression ();
+  subseg_set (bss_section, (subsegT) temp);
+  demand_empty_rest_of_line ();
+}
+
+const pseudo_typeS md_pseudo_table[] = {
+  {"align", s_align_bytes, 0},
+  {"byte2", cons, 2},
+  {"byte4", cons, 4},
+  {"picptr", bfin_pic_ptr, 4},
+  {"code", obj_elf_section, 0},
+  {"db", cons, 1},
+  {"dd", cons, 4},
+  {"dw", cons, 2},
+  {"p", s_ignore, 0},
+  {"pdata", s_ignore, 0},
+  {"var", s_ignore, 0},
+  {"bss", bfin_s_bss, 0},
+  {0, 0, 0}
+};
+
+/* Characters that are used to denote comments and line separators. */
+const char comment_chars[] = "";
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = ";";
+
+/* Characters that can be used to separate the mantissa from the
+   exponent in floating point numbers. */
+const char EXP_CHARS[] = "eE";
+
+/* Characters that mean this number is a floating point constant.
+   As in 0f12.456 or  0d1.2345e12.  */
+const char FLT_CHARS[] = "fFdDxX";
+
+/* Define bfin-specific command-line options (there are none). */
+const char *md_shortopts = "";
+
+#define OPTION_FDPIC		(OPTION_MD_BASE)
+
+struct option md_longopts[] =
+{
+  { "mfdpic",		no_argument,		NULL, OPTION_FDPIC	   },
+  { NULL,		no_argument,		NULL, 0                 },
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    default:
+      return 0;
+
+    case OPTION_FDPIC:
+      bfin_flags |= EF_BFIN_FDPIC;
+      bfin_pic_flag = "-mfdpic";
+      break;
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+{
+  fprintf (stream, _(" BFIN specific command line options:\n"));
+}
+
+/* Perform machine-specific initializations.  */
+void
+md_begin ()
+{
+  /* Set the ELF flags if desired. */
+  if (bfin_flags)
+    bfd_set_private_flags (stdoutput, bfin_flags);
+
+  /* Set the default machine type. */
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0))
+    as_warn ("Could not set architecture and machine.");
+
+  /* Ensure that lines can begin with '(', for multiple
+     register stack pops. */
+  lex_type ['('] = LEX_BEGIN_NAME;
+  
+#ifdef OBJ_ELF
+  record_alignment (text_section, 2);
+  record_alignment (data_section, 2);
+  record_alignment (bss_section, 2);
+#endif
+
+  errorf = stderr;
+  obstack_init (&mempool);
+
+#ifdef DEBUG
+  extern int debug_codeselection;
+  debug_codeselection = 1;
+#endif 
+
+  last_insn_size = 0;
+}
+
+/* Perform the main parsing, and assembly of the input here.  Also,
+   call the required routines for alignment and fixups here.
+   This is called for every line that contains real assembly code.  */
+
+void
+md_assemble (char *line)
+{
+  char *toP = 0;
+  extern char *current_inputline;
+  int size, insn_size;
+  struct bfin_insn *tmp_insn;
+  size_t len;
+  static size_t buffer_len = 0;
+  parse_state state;
+
+  len = strlen (line);
+  if (len + 2 > buffer_len)
+    {
+      if (buffer_len > 0)
+	free (current_inputline);
+      buffer_len = len + 40;
+      current_inputline = xmalloc (buffer_len);
+    }
+  memcpy (current_inputline, line, len);
+  current_inputline[len] = ';';
+  current_inputline[len + 1] = '\0';
+
+  state = parse (current_inputline);
+  if (state == NO_INSN_GENERATED)
+    return;
+
+  for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next)
+    if (!tmp_insn->reloc || !tmp_insn->exp->symbol)
+      insn_size += 2;
+
+  if (insn_size)
+    toP = frag_more (insn_size);
+
+  last_insn_size = insn_size;
+
+#ifdef DEBUG
+  printf ("INS:");
+#endif
+  while (insn)
+    {
+      if (insn->reloc && insn->exp->symbol)
+	{
+	  char *prev_toP = toP - 2;
+	  switch (insn->reloc)
+	    {
+	    case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
+	    case BFD_RELOC_24_PCREL:
+	    case BFD_RELOC_BFIN_16_LOW:
+	    case BFD_RELOC_BFIN_16_HIGH:
+	      size = 4;
+	      break;
+	    default:
+	      size = 2;
+	    }
+
+	  /* Following if condition checks for the arithmetic relocations.
+	     If the case then it doesn't required to generate the code.
+	     It has been assumed that, their ID will be contiguous.  */
+	  if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc
+               && BFD_ARELOC_BFIN_COMP >= insn->reloc)
+              || insn->reloc == BFD_RELOC_BFIN_16_IMM)
+	    {
+	      size = 2;
+	    }
+	  if (insn->reloc == BFD_ARELOC_BFIN_CONST
+              || insn->reloc == BFD_ARELOC_BFIN_PUSH)
+	    size = 4;
+
+	  fix_new (frag_now,
+                   (prev_toP - frag_now->fr_literal),
+		   size, insn->exp->symbol, insn->exp->value,
+                   insn->pcrel, insn->reloc);
+	}
+      else
+	{
+	  md_number_to_chars (toP, insn->value, 2);
+	  toP += 2;
+	}
+
+#ifdef DEBUG
+      printf (" reloc :");
+      printf (" %02x%02x", ((unsigned char *) &insn->value)[0],
+              ((unsigned char *) &insn->value)[1]);
+      printf ("\n");
+#endif
+      insn = insn->next;
+    }
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (insn_size);
+#endif
+}
+
+/* Parse one line of instructions, and generate opcode for it.
+   To parse the line, YACC and LEX are used, because the instruction set
+   syntax doesn't confirm to the AT&T assembly syntax.
+   To call a YACC & LEX generated parser, we must provide the input via
+   a FILE stream, otherwise stdin is used by default.  Below the input
+   to the function will be put into a temporary file, then the generated
+   parser uses the temporary file for parsing.  */
+
+static parse_state
+parse (char *line)
+{
+  parse_state state;
+  YY_BUFFER_STATE buffstate;
+
+  buffstate = yy_scan_string (line);
+
+  /* our lex requires setting the start state to keyword
+     every line as the first word may be a keyword.
+     Fixes a bug where we could not have keywords as labels.  */
+  set_start_state ();
+
+  /* Call yyparse here.  */
+  state = yyparse ();
+  if (state == SEMANTIC_ERROR)
+    {
+      as_bad ("Parse failed.");
+      insn = 0;
+    }
+
+  yy_delete_buffer (buffstate);
+  return state;
+}
+
+/* We need to handle various expressions properly.
+   Such as, [SP--] = 34, concerned by md_assemble().  */
+
+void
+md_operand (expressionS * expressionP)
+{
+  if (*input_line_pointer == '[')
+    {
+      as_tsktsk ("We found a '['!");
+      input_line_pointer++;
+      expression (expressionP);
+    }
+}
+
+/* Handle undefined symbols. */
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return (symbolS *) 0;
+}
+
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+                               segT segment ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Convert from target byte order to host byte order.  */
+
+static int
+md_chars_to_number (char *val, int n)
+{
+  int retval;
+
+  for (retval = 0; n--;)
+    {
+      retval <<= 8;
+      retval |= val[n];
+    }
+  return retval;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
+{
+  char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  long value = *valueP;
+  long newval;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_BFIN_GOT:
+    case BFD_RELOC_BFIN_GOT17M4:
+    case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
+      fixP->fx_no_overflow = 1;
+      newval = md_chars_to_number (where, 2);
+      newval |= 0x0 & 0x7f;
+      md_number_to_chars (where, newval, 2);
+      break;
+
+    case BFD_RELOC_BFIN_10_PCREL:
+      if (!value)
+	break;
+      if (value < -1024 || value > 1022)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+                      "pcrel too far BFD_RELOC_BFIN_10");
+
+      /* 11 bit offset even numbered, so we remove right bit.  */
+      value = value >> 1;
+      newval = md_chars_to_number (where, 2);
+      newval |= value & 0x03ff;
+      md_number_to_chars (where, newval, 2);
+      break;
+
+    case BFD_RELOC_BFIN_12_PCREL_JUMP:
+    case BFD_RELOC_BFIN_12_PCREL_JUMP_S:
+    case BFD_RELOC_12_PCREL:
+      if (!value)
+	break;
+
+      if (value < -4096 || value > 4094)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "pcrel too far BFD_RELOC_BFIN_12");
+      /* 13 bit offset even numbered, so we remove right bit.  */
+      value = value >> 1;
+      newval = md_chars_to_number (where, 2);
+      newval |= value & 0xfff;
+      md_number_to_chars (where, newval, 2);
+      break;
+
+    case BFD_RELOC_BFIN_16_LOW:
+    case BFD_RELOC_BFIN_16_HIGH:
+      fixP->fx_done = FALSE;
+      break;
+
+    case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
+    case BFD_RELOC_BFIN_24_PCREL_CALL_X:
+    case BFD_RELOC_24_PCREL:
+      if (!value)
+	break;
+
+      if (value < -16777216 || value > 16777214)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "pcrel too far BFD_RELOC_BFIN_24");
+
+      /* 25 bit offset even numbered, so we remove right bit.  */
+      value = value >> 1;
+      value++;
+
+      md_number_to_chars (where - 2, value >> 16, 1);
+      md_number_to_chars (where, value, 1);
+      md_number_to_chars (where + 1, value >> 8, 1);
+      break;
+
+    case BFD_RELOC_BFIN_5_PCREL:	/* LSETUP (a, b) : "a" */
+      if (!value)
+	break;
+      if (value < 4 || value > 30)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "pcrel too far BFD_RELOC_BFIN_5");
+      value = value >> 1;
+      newval = md_chars_to_number (where, 1);
+      newval = (newval & 0xf0) | (value & 0xf);
+      md_number_to_chars (where, newval, 1);
+      break;
+
+    case BFD_RELOC_BFIN_11_PCREL:	/* LSETUP (a, b) : "b" */
+      if (!value)
+	break;
+      value += 2;
+      if (value < 4 || value > 2046)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "pcrel too far BFD_RELOC_BFIN_11_PCREL");
+      /* 11 bit unsigned even, so we remove right bit.  */
+      value = value >> 1;
+      newval = md_chars_to_number (where, 2);
+      newval |= value & 0x03ff;
+      md_number_to_chars (where, newval, 2);
+      break;
+
+    case BFD_RELOC_8:
+      if (value < -0x80 || value >= 0x7f)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "rel too far BFD_RELOC_8");
+      md_number_to_chars (where, value, 1);
+      break;
+
+    case BFD_RELOC_BFIN_16_IMM:
+    case BFD_RELOC_16:
+      if (value < -0x8000 || value >= 0x7fff)
+	as_bad_where (fixP->fx_file, fixP->fx_line, "rel too far BFD_RELOC_8");
+      md_number_to_chars (where, value, 2);
+      break;
+
+    case BFD_RELOC_32:
+      md_number_to_chars (where, value, 4);
+      break;
+
+    case BFD_RELOC_BFIN_PLTPC:
+      md_number_to_chars (where, value, 2);
+      break;
+
+    case BFD_RELOC_BFIN_FUNCDESC:
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_VTABLE_ENTRY:
+      fixP->fx_done = FALSE;
+      break;
+
+    default:
+      if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type))
+	{
+	  fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type);
+	  return;
+	}
+    }
+
+  if (!fixP->fx_addsy)
+    fixP->fx_done = TRUE;
+
+}
+
+/* Round up a section size to the appropriate boundary.  */
+valueT
+md_section_align (segment, size)
+     segT segment;
+     valueT size;
+{
+  int boundary = bfd_get_section_alignment (stdoutput, segment);
+  return ((size + (1 << boundary) - 1) & (-1 << boundary));
+}
+
+
+/* Turn a string in input_line_pointer into a floating point
+   constant of type type, and store the appropriate bytes in
+   *litP.  The number of LITTLENUMS emitted is stored in *sizeP.
+   An error message is returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (type, litP, sizeP)
+     char   type;
+     char * litP;
+     int *  sizeP;
+{
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  LITTLENUM_TYPE   *wordP;
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+      prec = 4;
+      break;
+
+   /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+  /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
+     the littleendianness of the processor.  */
+  for (wordP = words + prec - 1; prec--;)
+    {
+      md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+
+/* If while processing a fixup, a reloc really needs to be created
+   then it is done here.  */
+
+arelent *
+tc_gen_reloc (seg, fixp)
+     asection *seg ATTRIBUTE_UNUSED;
+     fixS *fixp;
+{
+  arelent *reloc;
+
+  reloc		      = (arelent *) xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = (asymbol **) xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address      = fixp->fx_frag->fr_address + fixp->fx_where;
+
+  reloc->addend = fixp->fx_offset;
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+
+  if (reloc->howto == (reloc_howto_type *) NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    /* xgettext:c-format.  */
+		    _("reloc %d not supported by object file format"),
+		    (int) fixp->fx_r_type);
+
+      xfree (reloc);
+
+      return NULL;
+    }
+
+  return reloc;
+}
+
+/*  The location from which a PC relative jump should be calculated,
+    given a PC relative reloc.  */
+
+long
+md_pcrel_from_section (fixP, sec)
+     fixS *fixP;
+     segT sec;
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (!S_IS_DEFINED (fixP->fx_addsy)
+      || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    {
+      /* The symbol is undefined (or is defined but not in this section).
+         Let the linker figure it out.  */
+      return 0;
+    }
+  return fixP->fx_frag->fr_address + fixP->fx_where;
+}
+
+/* Return true if the fix can be handled by GAS, false if it must
+   be passed through to the linker.  */
+
+bfd_boolean  
+bfin_fix_adjustable (fixS *fixP)
+{         
+  switch (fixP->fx_r_type)
+    {     
+  /* Adjust_reloc_syms doesn't know about the GOT.  */
+    case BFD_RELOC_BFIN_GOT:
+    case BFD_RELOC_BFIN_GOT17M4:
+    case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
+    case BFD_RELOC_BFIN_PLTPC:
+  /* We need the symbol name for the VTABLE entries.  */
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_VTABLE_ENTRY:
+      return 0;
+        
+    default:
+      return 1;
+    }     
+}
+
+
+/* Handle the LOOP_BEGIN and LOOP_END statements.
+   Parse the Loop_Begin/Loop_End and create a label.  */
+void
+bfin_start_line_hook ()
+{
+  bfd_boolean maybe_begin = FALSE;
+  bfd_boolean maybe_end = FALSE;
+
+  char *c1, *label_name;
+  symbolS *line_label;
+  char *c = input_line_pointer;
+
+  while (ISSPACE (*c))
+    c++;
+
+  /* Look for Loop_Begin or Loop_End statements.  */
+
+  if (*c != 'L' && *c != 'l')
+    return;
+
+  c++;
+  if (*c != 'O' && *c != 'o')
+    return;
+
+  c++;
+  if (*c != 'O' && *c != 'o')
+    return;
+ 
+  c++;
+  if (*c != 'P' && *c != 'p')
+    return;
+
+  c++;
+  if (*c != '_')
+    return;
+
+  c++;
+  if (*c == 'E' || *c == 'e')
+    maybe_end = TRUE;
+  else if (*c == 'B' || *c == 'b')
+    maybe_begin = TRUE;
+  else
+    return;
+
+  if (maybe_end)
+    {
+      c++;
+      if (*c != 'N' && *c != 'n')
+	return;
+
+      c++;
+      if (*c != 'D' && *c != 'd')
+        return;
+    }
+
+  if (maybe_begin)
+    {
+      c++;
+      if (*c != 'E' && *c != 'e')
+	return;
+
+      c++;
+      if (*c != 'G' && *c != 'g')
+        return;
+
+      c++;
+      if (*c != 'I' && *c != 'i')
+	return;
+
+      c++;
+      if (*c != 'N' && *c != 'n')
+        return;
+    }
+
+  c++;
+  while (ISSPACE (*c)) c++;
+  c1 = c;
+  while (ISALPHA (*c) || ISDIGIT (*c) || *c == '_') c++;
+
+  input_line_pointer = c;
+  if (maybe_end)
+    {
+      label_name = (char *) xmalloc ((c - c1) + strlen ("__END") + 1);
+      label_name[0] = 0;
+      strncat (label_name, c1, c-c1);
+      strcat (label_name, "__END");
+    }
+  else /* maybe_begin.  */
+    {
+      label_name = (char *) xmalloc ((c - c1) + strlen ("__BEGIN") + 1);
+      label_name[0] = 0;
+      strncat (label_name, c1, c-c1);
+      strcat (label_name, "__BEGIN");
+    }
+
+  line_label = colon (label_name);
+
+  /* Loop_End follows the last instruction in the loop.
+     Adjust label address.  */
+  if (maybe_end)
+    line_label->sy_value.X_add_number -= last_insn_size;
+
+}
+
+/* Special extra functions that help bfin-parse.y perform its job.  */
+
+#include <stdio.h>
+#include <assert.h>
+#include <obstack.h>
+#include <bfd.h>
+#include "bfin-defs.h"
+
+struct obstack mempool;
+
+INSTR_T
+conscode (INSTR_T head, INSTR_T tail)
+{
+  if (!head)
+    return tail;
+  head->next = tail;
+  return head;
+}
+
+INSTR_T
+conctcode (INSTR_T head, INSTR_T tail)
+{
+  INSTR_T temp = (head);
+  if (!head)
+    return tail;
+  while (temp->next)
+    temp = temp->next;
+  temp->next = tail;
+
+  return head;
+}
+
+INSTR_T
+note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel)
+{
+  /* Assert that the symbol is not an operator.  */
+  assert (symbol->type == Expr_Node_Reloc);
+
+  return note_reloc1 (code, symbol->value.s_value, reloc, pcrel);
+
+}
+
+INSTR_T
+note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel)
+{
+  code->reloc = reloc;
+  code->exp = mkexpr (0, symbol_find_or_make (symbol));
+  code->pcrel = pcrel;
+  return code;
+}
+
+INSTR_T
+note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel)
+{
+  code->reloc = reloc;
+  code->exp = mkexpr (value, symbol_find_or_make (symbol));
+  code->pcrel = pcrel;
+  return code;
+}
+
+INSTR_T
+gencode (unsigned long x)
+{
+  INSTR_T cell = (INSTR_T) obstack_alloc (&mempool, sizeof (struct bfin_insn));
+  memset (cell, 0, sizeof (struct bfin_insn));
+  cell->value = (x);
+  return cell;
+}
+
+int reloc;
+int ninsns;
+int count_insns;
+
+static void *
+allocate (int n)
+{
+  return (void *) obstack_alloc (&mempool, n);
+}
+
+Expr_Node *
+Expr_Node_Create (Expr_Node_Type type,
+	          Expr_Node_Value value,
+                  Expr_Node *Left_Child,
+                  Expr_Node *Right_Child)
+{
+
+
+  Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node));
+  node->type = type;
+  node->value = value;
+  node->Left_Child = Left_Child;
+  node->Right_Child = Right_Child;
+  return node;
+}
+
+static const char *con = ".__constant";
+static const char *op = ".__operator";
+static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head);
+INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
+
+INSTR_T
+Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
+{
+  /* Top level reloction expression generator VDSP style.
+   If the relocation is just by itself, generate one item
+   else generate this convoluted expression.  */
+
+  INSTR_T note = NULL_CODE;
+  INSTR_T note1 = NULL_CODE;
+  int pcrel = 1;  /* Is the parent reloc pcrelative?
+		  This calculation here and HOWTO should match.  */
+
+  if (parent_reloc)
+    {
+      /*  If it's 32 bit quantity then 16bit code needs to be added.  */
+      int value = 0;
+
+      if (head->type == Expr_Node_Constant)
+	{
+	  /* If note1 is not null code, we have to generate a right
+             aligned value for the constant. Otherwise the reloc is
+             a part of the basic command and the yacc file
+             generates this.  */
+	  value = head->value.i_value;
+	}
+      switch (parent_reloc)
+	{
+	  /*  Some reloctions will need to allocate extra words.  */
+	case BFD_RELOC_BFIN_16_IMM:
+	case BFD_RELOC_BFIN_16_LOW:
+	case BFD_RELOC_BFIN_16_HIGH:
+	  note1 = conscode (gencode (value), NULL_CODE);
+	  pcrel = 0;
+	  break;
+	case BFD_RELOC_BFIN_PLTPC:
+	  note1 = conscode (gencode (value), NULL_CODE);
+	  pcrel = 0;
+	  break;
+	case BFD_RELOC_16:
+	case BFD_RELOC_BFIN_GOT:
+	case BFD_RELOC_BFIN_GOT17M4:
+	case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
+	  note1 = conscode (gencode (value), NULL_CODE);
+	  pcrel = 0;
+	  break;
+	case BFD_RELOC_24_PCREL:
+	case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
+	case BFD_RELOC_BFIN_24_PCREL_CALL_X:
+	  /* These offsets are even numbered pcrel.  */
+	  note1 = conscode (gencode (value >> 1), NULL_CODE);
+	  break;
+	default:
+	  note1 = NULL_CODE;
+	}
+    }
+  if (head->type == Expr_Node_Constant)
+    note = note1;
+  else if (head->type == Expr_Node_Reloc)
+    {
+      note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel);
+      if (note1 != NULL_CODE)
+	note = conscode (note1, note);
+    }
+  else if (head->type == Expr_Node_Binop
+	   && (head->value.op_value == Expr_Op_Type_Add
+	       || head->value.op_value == Expr_Op_Type_Sub)
+	   && head->Left_Child->type == Expr_Node_Reloc
+	   && head->Right_Child->type == Expr_Node_Constant)
+    {
+      int val = head->Right_Child->value.i_value;
+      if (head->value.op_value == Expr_Op_Type_Sub)
+	val = -val;
+      note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value,
+				    parent_reloc, val, 0),
+		       NULL_CODE);
+      if (note1 != NULL_CODE)
+	note = conscode (note1, note);
+    }
+  else
+    {
+      /* Call the recursive function.  */
+      note = note_reloc1 (gencode (0), op, parent_reloc, pcrel);
+      if (note1 != NULL_CODE)
+	note = conscode (note1, note);
+      note = conctcode (Expr_Node_Gen_Reloc_R (head), note);
+    }
+  return note;
+}
+
+static INSTR_T
+Expr_Node_Gen_Reloc_R (Expr_Node * head)
+{
+
+  INSTR_T note = 0;
+  INSTR_T note1 = 0;
+
+  switch (head->type)
+    {
+    case Expr_Node_Constant:
+      note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE);
+      break;
+    case Expr_Node_Reloc:
+      note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE);
+      break;
+    case Expr_Node_Binop:
+      note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child));
+      switch (head->value.op_value)
+	{
+	case Expr_Op_Type_Add:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Sub:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Mult:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Div:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Mod:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Lshift:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_Rshift:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_BAND:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_BOR:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_BXOR:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_LAND:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_LOR:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE));
+	  break;
+	default:
+	  fprintf (stderr, "%s:%d:Unkonwn operator found for arithmetic" " relocation", __FILE__, __LINE__);
+
+
+	}
+      break;
+    case Expr_Node_Unop:
+      note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE);
+      switch (head->value.op_value)
+	{
+	case Expr_Op_Type_NEG:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE));
+	  break;
+	case Expr_Op_Type_COMP:
+	  note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE));
+	  break;
+	default:
+	  fprintf (stderr, "%s:%d:Unkonwn operator found for arithmetic" " relocation", __FILE__, __LINE__);
+	}
+      break;
+    default:
+      fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__);
+    }
+  return note;
+}
+
+
+/* Blackfin opcode generation.  */
+
+/* These functions are called by the generated parser
+   (from bfin-parse.y), the register type classification
+   happens in bfin-lex.l.  */
+
+#include "bfin-aux.h"
+#include "opcode/bfin.h"
+
+#define INIT(t)  t c_code = init_##t
+#define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
+#define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
+
+#define HI(x) ((x >> 16) & 0xffff)
+#define LO(x) ((x      ) & 0xffff)
+
+#define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
+
+#define GEN_OPCODE32()  \
+	conscode (gencode (HI (c_code.opcode)), \
+	conscode (gencode (LO (c_code.opcode)), NULL_CODE))
+
+#define GEN_OPCODE16()  \
+	conscode (gencode (c_code.opcode), NULL_CODE)
+
+
+/*  32 BIT INSTRUCTIONS.  */
+
+
+/* DSP32 instruction generation.  */
+
+INSTR_T
+bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P,
+	           int h01, int h11, int h00, int h10, int op0,
+                   REG_T dst, REG_T src0, REG_T src1, int w0)
+{
+  INIT (DSP32Mac);
+
+  ASSIGN (op0);
+  ASSIGN (op1);
+  ASSIGN (MM);
+  ASSIGN (mmod);
+  ASSIGN (w0);
+  ASSIGN (w1);
+  ASSIGN (h01);
+  ASSIGN (h11);
+  ASSIGN (h00);
+  ASSIGN (h10);
+  ASSIGN (P);
+
+  /* If we have full reg assignments, mask out LSB to encode
+  single or simultaneous even/odd register moves.  */
+  if (P)
+    {
+      dst->regno &= 0x06;
+    }
+
+  ASSIGN_R (dst);
+  ASSIGN_R (src0);
+  ASSIGN_R (src1);
+
+  return GEN_OPCODE32 ();
+}
+
+INSTR_T
+bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P,
+	            int h01, int h11, int h00, int h10, int op0,
+                    REG_T dst, REG_T src0, REG_T src1, int w0)
+{
+  INIT (DSP32Mult);
+
+  ASSIGN (op0);
+  ASSIGN (op1);
+  ASSIGN (MM);
+  ASSIGN (mmod);
+  ASSIGN (w0);
+  ASSIGN (w1);
+  ASSIGN (h01);
+  ASSIGN (h11);
+  ASSIGN (h00);
+  ASSIGN (h10);
+  ASSIGN (P);
+
+  if (P)
+    {
+      dst->regno &= 0x06;
+    }
+
+  ASSIGN_R (dst);
+  ASSIGN_R (src0);
+  ASSIGN_R (src1);
+
+  return GEN_OPCODE32 ();
+}
+
+INSTR_T
+bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,
+              REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
+{
+  INIT (DSP32Alu);
+
+  ASSIGN (HL);
+  ASSIGN (aopcde);
+  ASSIGN (aop);
+  ASSIGN (s);
+  ASSIGN (x);
+  ASSIGN_R (dst0);
+  ASSIGN_R (dst1);
+  ASSIGN_R (src0);
+  ASSIGN_R (src1);
+
+  return GEN_OPCODE32 ();
+}
+
+INSTR_T
+bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
+                REG_T src1, int sop, int HLs)
+{
+  INIT (DSP32Shift);
+
+  ASSIGN (sopcde);
+  ASSIGN (sop);
+  ASSIGN (HLs);
+
+  ASSIGN_R (dst0);
+  ASSIGN_R (src0);
+  ASSIGN_R (src1);
+
+  return GEN_OPCODE32 ();
+}
+
+INSTR_T
+bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag,
+                   REG_T src1, int sop, int HLs)
+{
+  INIT (DSP32ShiftImm);
+
+  ASSIGN (sopcde);
+  ASSIGN (sop);
+  ASSIGN (HLs);
+
+  ASSIGN_R (dst0);
+  ASSIGN (immag);
+  ASSIGN_R (src1);
+
+  return GEN_OPCODE32 ();
+}
+
+/* LOOP SETUP.  */
+
+INSTR_T
+bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop,
+               Expr_Node * peoffset, REG_T reg)
+{
+  int soffset, eoffset;
+  INIT (LoopSetup);
+
+  soffset = (EXPR_VALUE (psoffset) >> 1);
+  ASSIGN (soffset);
+  eoffset = (EXPR_VALUE (peoffset) >> 1);
+  ASSIGN (eoffset);
+  ASSIGN (rop);
+  ASSIGN_R (c);
+  ASSIGN_R (reg);
+
+  return
+      conscode (gencode (HI (c_code.opcode)),
+		conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL),
+			   conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL))));
+
+}
+
+/*  Call, Link.  */
+
+INSTR_T
+bfin_gen_calla (Expr_Node * addr, int S)
+{
+  int val;
+  int high_val;
+  int reloc = 0;
+  INIT (CALLa);
+
+  switch(S){
+   case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
+   case 1 : reloc = BFD_RELOC_24_PCREL; break;
+   case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
+   default : break;
+  }
+
+  ASSIGN (S);
+
+  val = EXPR_VALUE (addr) >> 1;
+  high_val = val >> 16;
+
+  return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
+                     Expr_Node_Gen_Reloc (addr, reloc));
+  }
+
+INSTR_T
+bfin_gen_linkage (int R, int framesize)
+{
+  INIT (Linkage);
+
+  ASSIGN (R);
+  ASSIGN (framesize);
+
+  return GEN_OPCODE32 ();
+}
+
+
+/* Load and Store.  */
+
+INSTR_T
+bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc)
+{
+  int grp, hword;
+  unsigned val = EXPR_VALUE (phword);
+  INIT (LDIMMhalf);
+
+  ASSIGN (H);
+  ASSIGN (S);
+  ASSIGN (Z);
+
+  ASSIGN_R (reg);
+  grp = (GROUP (reg));
+  ASSIGN (grp);
+  if (reloc == 2)
+    {
+      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
+    }
+  else if (reloc == 1)
+    {
+      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
+    }
+  else
+    {
+      hword = val;
+      ASSIGN (hword);
+    }
+  return GEN_OPCODE32 ();
+}
+
+INSTR_T
+bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset)
+{
+  INIT (LDSTidxI);
+
+  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
+    {
+      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
+      return 0;
+    }
+
+  ASSIGN_R (ptr);
+  ASSIGN_R (reg);
+  ASSIGN (W);
+  ASSIGN (sz);
+
+  ASSIGN (Z);
+
+  if (poffset->type != Expr_Node_Constant)
+    {
+      /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
+      /* distinguish between R0 = [P5 + symbol@GOT] and
+	 P5 = [P5 + _current_shared_library_p5_offset_]
+      */
+      if (poffset->type == Expr_Node_Reloc
+	  && !strcmp (poffset->value.s_value,
+		      "_current_shared_library_p5_offset_"))
+	{
+	  return  conscode (gencode (HI (c_code.opcode)),
+			    Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16));
+	}
+      else if (poffset->type != Expr_Node_GOT_Reloc)
+	abort ();
+
+      return conscode (gencode (HI (c_code.opcode)),
+		       Expr_Node_Gen_Reloc(poffset->Left_Child,
+					   poffset->value.i_value));
+    }
+  else
+    {
+      int value, offset;
+      switch (sz)
+	{				// load/store access size
+	case 0:			// 32 bit
+	  value = EXPR_VALUE (poffset) >> 2;
+	  break;
+	case 1:			// 16 bit
+	  value = EXPR_VALUE (poffset) >> 1;
+	  break;
+	case 2:			// 8 bit
+	  value = EXPR_VALUE (poffset);
+	  break;
+	default:
+	  abort ();
+	}
+
+      offset = (value & 0xffff);
+      ASSIGN (offset);
+      return GEN_OPCODE32 ();
+    }
+}
+
+
+INSTR_T
+bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W)
+{
+  INIT (LDST);
+
+  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
+    {
+      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
+      return 0;
+    }
+
+  ASSIGN_R (ptr);
+  ASSIGN_R (reg);
+  ASSIGN (aop);
+  ASSIGN (sz);
+  ASSIGN (Z);
+  ASSIGN (W);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op)
+{
+  int offset;
+  int value = 0;
+  INIT (LDSTii);
+
+
+  if (!IS_PREG (*ptr))
+    {
+      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
+      return 0;
+    }
+
+  switch (op)
+    {
+    case 1:
+    case 2:
+      value = EXPR_VALUE (poffset) >> 1;
+      break;
+    case 0:
+    case 3:
+      value = EXPR_VALUE (poffset) >> 2;
+      break;
+    }
+
+  ASSIGN_R (ptr);
+  ASSIGN_R (reg);
+
+  offset = value;
+  ASSIGN (offset);
+  ASSIGN (W);
+  ASSIGN (op);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W)
+{
+  /* Set bit 4 if it's a Preg.  */
+  int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0);
+  int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1;
+  INIT (LDSTiiFP);
+  ASSIGN (reg);
+  ASSIGN (offset);
+  ASSIGN (W);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx)
+{
+  INIT (LDSTpmod);
+
+  ASSIGN_R (ptr);
+  ASSIGN_R (reg);
+  ASSIGN (aop);
+  ASSIGN (W);
+  ASSIGN_R (idx);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m)
+{
+  INIT (DspLDST);
+
+  ASSIGN_R (i);
+  ASSIGN_R (reg);
+  ASSIGN (aop);
+  ASSIGN (W);
+  ASSIGN (m);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_logi2op (int opc, int src, int dst)
+{
+  INIT (LOGI2op);
+
+  ASSIGN (opc);
+  ASSIGN (src);
+  ASSIGN (dst);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_brcc (int T, int B, Expr_Node * poffset)
+{
+  int offset;
+  INIT (BRCC);
+
+  ASSIGN (T);
+  ASSIGN (B);
+  offset = ((EXPR_VALUE (poffset) >> 1));
+  ASSIGN (offset);
+  return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL));
+}
+
+INSTR_T
+bfin_gen_ujump (Expr_Node * poffset)
+{
+  int offset;
+  INIT (UJump);
+
+  offset = ((EXPR_VALUE (poffset) >> 1));
+  ASSIGN (offset);
+
+  return conscode (gencode (c_code.opcode),
+                   Expr_Node_Gen_Reloc (
+                       poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S));
+}
+
+INSTR_T
+bfin_gen_alu2op (REG_T dst, REG_T src, int opc)
+{
+  INIT (ALU2op);
+
+  ASSIGN_R (dst);
+  ASSIGN_R (src);
+  ASSIGN (opc);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_compi2opd (REG_T dst, int src, int op)
+{
+  INIT (COMPI2opD);
+
+  ASSIGN_R (dst);
+  ASSIGN (src);
+  ASSIGN (op);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_compi2opp (REG_T dst, int src, int op)
+{
+  INIT (COMPI2opP);
+
+  ASSIGN_R (dst);
+  ASSIGN (src);
+  ASSIGN (op);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_dagmodik (REG_T i, int op)
+{
+  INIT (DagMODik);
+
+  ASSIGN_R (i);
+  ASSIGN (op);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
+{
+  INIT (DagMODim);
+
+  ASSIGN_R (i);
+  ASSIGN_R (m);
+  ASSIGN (op);
+  ASSIGN (br);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ptr2op (REG_T dst, REG_T src, int opc)
+{
+  INIT (PTR2op);
+
+  ASSIGN_R (dst);
+  ASSIGN_R (src);
+  ASSIGN (opc);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
+{
+  INIT (COMP3op);
+
+  ASSIGN_R (src0);
+  ASSIGN_R (src1);
+  ASSIGN_R (dst);
+  ASSIGN (opc);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G)
+{
+  INIT (CCflag);
+
+  ASSIGN_R (x);
+  ASSIGN (y);
+  ASSIGN (opc);
+  ASSIGN (I);
+  ASSIGN (G);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_ccmv (REG_T src, REG_T dst, int T)
+{
+  int s, d;
+  INIT (CCmv);
+
+  ASSIGN_R (src);
+  ASSIGN_R (dst);
+  s = (GROUP (src));
+  ASSIGN (s);
+  d = (GROUP (dst));
+  ASSIGN (d);
+  ASSIGN (T);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_cc2stat (int cbit, int op, int D)
+{
+  INIT (CC2stat);
+
+  ASSIGN (cbit);
+  ASSIGN (op);
+  ASSIGN (D);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_regmv (REG_T src, REG_T dst)
+{
+  int gs, gd;
+  INIT (RegMv);
+
+  ASSIGN_R (src);
+  ASSIGN_R (dst);
+
+  gs = (GROUP (src));
+  ASSIGN (gs);
+  gd = (GROUP (dst));
+  ASSIGN (gd);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_cc2dreg (int op, REG_T reg)
+{
+  INIT (CC2dreg);
+
+  ASSIGN (op);
+  ASSIGN_R (reg);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_progctrl (int prgfunc, int poprnd)
+{
+  INIT (ProgCtrl);
+
+  ASSIGN (prgfunc);
+  ASSIGN (poprnd);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_cactrl (REG_T reg, int a, int op)
+{
+  INIT (CaCTRL);
+
+  ASSIGN_R (reg);
+  ASSIGN (a);
+  ASSIGN (op);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W)
+{
+  INIT (PushPopMultiple);
+
+  ASSIGN (dr);
+  ASSIGN (pr);
+  ASSIGN (d);
+  ASSIGN (p);
+  ASSIGN (W);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_pushpopreg (REG_T reg, int W)
+{
+  int grp;
+  INIT (PushPopReg);
+
+  ASSIGN_R (reg);
+  grp = (GROUP (reg));
+  ASSIGN (grp);
+  ASSIGN (W);
+
+  return GEN_OPCODE16 ();
+}
+
+/* Pseudo Debugging Support.  */
+
+INSTR_T
+bfin_gen_pseudodbg (int fn, int reg, int grp)
+{
+  INIT (PseudoDbg);
+
+  ASSIGN (fn);
+  ASSIGN (reg);
+  ASSIGN (grp);
+
+  return GEN_OPCODE16 ();
+}
+
+INSTR_T
+bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
+{
+  INIT (PseudoDbg_Assert);
+
+  ASSIGN (dbgop);
+  ASSIGN_R (regtest);
+  ASSIGN (expected);
+
+  return GEN_OPCODE32 ();
+}
+
+/* Multiple instruction generation.  */
+
+INSTR_T
+bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
+{
+  INSTR_T walk;
+
+  /* If it's a 0, convert into MNOP. */
+  if (dsp32)
+    {
+      walk = dsp32->next;
+      SET_MULTI_INSTRUCTION_BIT (dsp32);
+    }
+  else
+    {
+      dsp32 = gencode (0xc803);
+      walk = gencode (0x1800);
+      dsp32->next = walk;
+    }
+
+  if (!dsp16_grp1)
+    {
+      dsp16_grp1 = gencode (0x0000);
+    }
+
+  if (!dsp16_grp2)
+    {
+      dsp16_grp2 = gencode (0x0000);
+    }
+
+  walk->next = dsp16_grp1;
+  dsp16_grp1->next = dsp16_grp2;
+  dsp16_grp2->next = NULL_CODE;
+
+  return dsp32;
+}
+
+INSTR_T
+bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
+{
+  const char *loopsym;
+  char *lbeginsym, *lendsym;
+  Expr_Node_Value lbeginval, lendval;
+  Expr_Node *lbegin, *lend;
+
+  loopsym = expr->value.s_value;
+  lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 1);
+  lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 1);
+
+  lbeginsym[0] = 0;
+  lendsym[0] = 0;
+
+  strcat (lbeginsym, loopsym);
+  strcat (lbeginsym, "__BEGIN");
+
+  strcat (lendsym, loopsym);
+  strcat (lendsym, "__END");
+
+  lbeginval.s_value = lbeginsym;
+  lendval.s_value = lendsym;
+
+  lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
+  lend   = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
+  return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
+}
+
+bfd_boolean
+bfin_eol_in_insn (char *line)
+{
+   /* Allow a new-line to appear in the middle of a multi-issue instruction.  */
+
+   char *temp = line;
+
+  if (*line != '\n')
+    return FALSE;
+
+  /* A semi-colon followed by a newline is always the end of a line.  */
+  if (line[-1] == ';')
+    return FALSE;
+
+  if (line[-1] == '|')
+    return TRUE;
+
+  /* If the || is on the next line, there might be leading whitespace.  */
+  temp++;
+  while (*temp == ' ' || *temp == '\t') temp++;
+
+  if (*temp == '|')
+    return TRUE;
+
+  return FALSE;
+}
+
+bfd_boolean
+bfin_name_is_register (char *name)
+{
+  int i;
+
+  if (*name == '[' || *name == '(')
+    return TRUE;
+
+  if ((name[0] == 'W' || name[0] == 'w') && name[1] == '[')
+    return TRUE;
+
+  if ((name[0] == 'B' || name[0] == 'b') && name[1] == '[')
+    return TRUE;
+
+  for (i=0; bfin_reg_info[i].name != 0; i++)
+   {
+     if (!strcasecmp (bfin_reg_info[i].name, name))
+       return TRUE;
+   }
+  return FALSE;
+}
+
+void
+bfin_equals (Expr_Node *sym)
+{
+  char *c;
+
+  c = input_line_pointer;
+  while (*c != '=')
+   c--;
+
+  input_line_pointer = c;
+
+  equals ((char *) sym->value.s_value, 1);
+}
+
+bfd_boolean
+bfin_start_label (char *ptr)
+{
+  ptr--;
+  while (!ISSPACE (*ptr) && !is_end_of_line[(unsigned char) *ptr])
+    ptr--;
+
+  ptr++;
+  if (*ptr == '(' || *ptr == '[')
+    return FALSE;
+
+  return TRUE;
+} 
+
+int
+bfin_force_relocation (struct fix *fixp)
+{
+  if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
+      || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
+    return TRUE;
+
+  return generic_force_reloc (fixp);
+}
diff --git a/gas/config/tc-bfin.h b/gas/config/tc-bfin.h
new file mode 100644
index 000000000000..773030cbb720
--- /dev/null
+++ b/gas/config/tc-bfin.h
@@ -0,0 +1,78 @@
+/* tc-bfin.h - header file for tc-bfin.c
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#define TC_BFIN 1
+#define TC_ADI_BFIN 1
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_ARCH		bfd_arch_bfin
+
+/*
+ * Define the target format macro here.   The value for this should be
+ * "elf32-bfin", not "elf32-little-bfin".  Since the BFD source file 
+ * elf32-bfin.c defines TARGET_LITTLE_NAME to be "elf32-little-bfin",
+ * we must use this value, until this is corrected and BFD is rebuilt.  */
+#ifdef OBJ_ELF
+#define TARGET_FORMAT		"elf32-bfin" 
+#endif
+
+#define LISTING_HEADER "BFIN GAS "
+
+#define WORKING_DOT_WORD
+
+extern void bfin_start_line_hook PARAMS ((void));
+extern bfd_boolean bfin_start_label PARAMS ((char *));
+
+#define md_start_line_hook()    bfin_start_line_hook()
+#define md_number_to_chars	number_to_chars_littleendian
+#define md_convert_frag(b,s,f)	as_fatal ("bfin convert_frag\n");
+
+/* Allow for [, ], etc.  */
+#define LEX_BR 6
+
+#define TC_EOL_IN_INSN(PTR) (bfin_eol_in_insn(PTR) ? 1 : 0)
+extern bfd_boolean bfin_eol_in_insn PARAMS ((char *));
+
+/* The instruction is permitted to contain an = character.  */
+#define TC_EQUAL_IN_INSN(C, NAME) (bfin_name_is_register (NAME) ? 1 : 0)
+extern bfd_boolean bfin_name_is_register PARAMS ((char *));
+#define NOP_OPCODE 0x0000 
+
+#define LOCAL_LABELS_FB 1
+
+#define DOUBLESLASH_LINE_COMMENTS
+
+#define TC_START_LABEL(ch ,ptr) (ch == ':' && bfin_start_label (ptr))
+#define tc_fix_adjustable(FIX) bfin_fix_adjustable (FIX)
+extern bfd_boolean bfin_fix_adjustable PARAMS ((struct fix *));
+
+#define TC_FORCE_RELOCATION(FIX) bfin_force_relocation (FIX)
+extern int bfin_force_relocation PARAMS ((struct fix *));
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+
+/* Values passed to md_apply_fix3 don't include symbol values.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+/* end of tc-bfin.h */
diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c
index e725b8847b86..1c8e6dc64529 100644
--- a/gas/config/tc-cris.c
+++ b/gas/config/tc-cris.c
@@ -1,5 +1,5 @@
 /* tc-cris.c -- Assembler code for the CRIS CPU core.
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
 
    Contributed by Axis Communications AB, Lund, Sweden.
    Originally written for GAS 1.38.1 by Mikael Asker.
@@ -19,8 +19,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the
-   Free Software Foundation, 59 Temple Place - Suite 330, Boston,
-   MA 02111-1307, USA.  */
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -113,46 +113,53 @@ struct cris_instruction
   int imm_oprnd_size;
 };
 
-static void cris_process_instruction PARAMS ((char *,
-					      struct cris_instruction *,
-					      struct cris_prefix *));
-static int get_bwd_size_modifier PARAMS ((char **, int *));
-static int get_bw_size_modifier PARAMS ((char **, int *));
-static int get_gen_reg PARAMS ((char **, int *));
-static int get_spec_reg PARAMS ((char **,
-				 const struct cris_spec_reg **));
-static int get_autoinc_prefix_or_indir_op PARAMS ((char **,
-						   struct cris_prefix *,
-						   int *, int *, int *,
-						   expressionS *));
-static int get_3op_or_dip_prefix_op PARAMS ((char **,
-					     struct cris_prefix *));
-static int cris_get_expression PARAMS ((char **, expressionS *));
-static int get_flags PARAMS ((char **, int *));
-static void gen_bdap PARAMS ((int, expressionS *));
-static int branch_disp PARAMS ((int));
-static void gen_cond_branch_32 PARAMS ((char *, char *, fragS *,
-					symbolS *, symbolS *, long int));
-static void cris_number_to_imm PARAMS ((char *, long, int, fixS *, segT));
-static void cris_create_short_jump PARAMS ((char *, addressT, addressT,
-					    fragS *, symbolS *));
-static void s_syntax PARAMS ((int));
-static void s_cris_file PARAMS ((int));
-static void s_cris_loc PARAMS ((int));
+enum cris_archs
+{
+  arch_cris_unknown,
+  arch_crisv0, arch_crisv3, arch_crisv8, arch_crisv10,
+  arch_cris_any_v0_v10, arch_crisv32, arch_cris_common_v10_v32
+};
+
+static enum cris_archs cris_arch_from_string (char **);
+static int cris_insn_ver_valid_for_arch (enum cris_insn_version_usage,
+					 enum cris_archs);
+
+static void cris_process_instruction (char *, struct cris_instruction *,
+				      struct cris_prefix *);
+static int get_bwd_size_modifier (char **, int *);
+static int get_bw_size_modifier (char **, int *);
+static int get_gen_reg (char **, int *);
+static int get_spec_reg (char **, const struct cris_spec_reg **);
+static int get_sup_reg (char **, int *);
+static int get_autoinc_prefix_or_indir_op (char **, struct cris_prefix *,
+					   int *, int *, int *,
+					   expressionS *);
+static int get_3op_or_dip_prefix_op (char **, struct cris_prefix *);
+static int cris_get_expression (char **, expressionS *);
+static int get_flags (char **, int *);
+static void gen_bdap (int, expressionS *);
+static int branch_disp (int);
+static void gen_cond_branch_32 (char *, char *, fragS *, symbolS *, symbolS *,
+				long int);
+static void cris_number_to_imm (char *, long, int, fixS *, segT);
+static void cris_create_short_jump (char *, addressT, addressT, fragS *,
+				    symbolS *);
+static void s_syntax (int);
+static void s_cris_file (int);
+static void s_cris_loc (int);
+static void s_cris_arch (int);
 
 /* Get ":GOT", ":GOTOFF", ":PLT" etc. suffixes.  */
-static void cris_get_pic_suffix PARAMS ((char **,
-					 bfd_reloc_code_real_type *,
-					 expressionS *));
-static unsigned int cris_get_pic_reloc_size
-  PARAMS ((bfd_reloc_code_real_type));
+static void cris_get_pic_suffix (char **, bfd_reloc_code_real_type *,
+				 expressionS *);
+static unsigned int cris_get_pic_reloc_size (bfd_reloc_code_real_type);
 
 /* All the .syntax functions.  */
-static void cris_force_reg_prefix PARAMS ((void));
-static void cris_relax_reg_prefix PARAMS ((void));
-static void cris_sym_leading_underscore PARAMS ((void));
-static void cris_sym_no_leading_underscore PARAMS ((void));
-static char *cris_insn_first_word_frag PARAMS ((void));
+static void cris_force_reg_prefix (void);
+static void cris_relax_reg_prefix (void);
+static void cris_sym_leading_underscore (void);
+static void cris_sym_no_leading_underscore (void);
+static char *cris_insn_first_word_frag (void);
 
 /* Handle to the opcode hash table.  */
 static struct hash_control *op_hash = NULL;
@@ -176,12 +183,22 @@ static bfd_boolean symbols_have_leading_underscore
 /* Whether or not we allow PIC, and expand to PIC-friendly constructs.  */
 static bfd_boolean pic = FALSE;
 
+/* If we're configured for "cris", default to allow all v0..v10
+   instructions and register names.  */
+#ifndef DEFAULT_CRIS_ARCH
+#define DEFAULT_CRIS_ARCH cris_any_v0_v10
+#endif
+
+/* No whitespace in the CONCAT2 parameter list.  */
+static enum cris_archs cris_arch = XCONCAT2 (arch_,DEFAULT_CRIS_ARCH);
+
 const pseudo_typeS md_pseudo_table[] =
 {
   {"dword", cons, 4},
   {"syntax", s_syntax, 0},
   {"file", s_cris_file, 0},
   {"loc", s_cris_loc, 0},
+  {"arch", s_cris_arch, 0},
   {NULL, 0, 0}
 };
 
@@ -189,7 +206,8 @@ static int warn_for_branch_expansion = 0;
 
 /* Whether to emit error when a MULS/MULU could be located last on a
    cache-line.  */
-static int err_for_dangerous_mul_placement = 1;
+static int err_for_dangerous_mul_placement
+ = (XCONCAT2 (arch_,DEFAULT_CRIS_ARCH) != arch_crisv32);
 
 const char cris_comment_chars[] = ";";
 
@@ -214,12 +232,11 @@ const char FLT_CHARS[] = "";
       ---/ /--+-----------------+-----------------+-----------------+
 
    The "how long" bits are 00 = byte, 01 = word, 10 = dword (long).
-   This is a Un*x convention.
    Not all lengths are legit for a given value of (what state).
 
    Groups for CRIS address relaxing:
 
-   1. Bcc
+   1. Bcc (pre-V32)
       length: byte, word, 10-byte expansion
 
    2. BDAP
@@ -228,11 +245,29 @@ const char FLT_CHARS[] = "";
    3. MULS/MULU
       Not really a relaxation (no infrastructure to get delay-slots
       right), just an alignment and placement checker for the v10
-      multiply/cache-bug.  */
+      multiply/cache-bug.
 
-#define STATE_CONDITIONAL_BRANCH    (1)
+   4. Bcc (V32 and later)
+      length: byte, word, 14-byte expansion
+
+   5. Bcc (V10+V32)
+      length: byte, word, error
+
+   6. BA (V32)
+      length: byte, word, dword
+
+   7. LAPC (V32)
+      length: byte, dword
+  */
+
+#define STATE_COND_BRANCH           (1)
 #define STATE_BASE_PLUS_DISP_PREFIX (2)
 #define STATE_MUL		    (3)
+#define STATE_COND_BRANCH_V32       (4)
+#define STATE_COND_BRANCH_COMMON    (5)
+#define STATE_ABS_BRANCH_V32	    (6)
+#define STATE_LAPC		    (7)
+#define STATE_COND_BRANCH_PIC       (8)
 
 #define STATE_LENGTH_MASK	    (3)
 #define STATE_BYTE		    (0)
@@ -248,8 +283,12 @@ const char FLT_CHARS[] = "";
 
 #define BRANCH_BF ( 254)
 #define BRANCH_BB (-256)
+#define BRANCH_BF_V32 ( 252)
+#define BRANCH_BB_V32 (-258)
 #define BRANCH_WF (2 +  32767)
 #define BRANCH_WB (2 + -32768)
+#define BRANCH_WF_V32 (-2 + 32767)
+#define BRANCH_WB_V32 (-2 + -32768)
 
 #define BDAP_BF	  ( 127)
 #define BDAP_BB	  (-128)
@@ -295,39 +334,102 @@ const relax_typeS md_cris_relax_table[] =
   {0,	      0,	 4,  0},
 
   /* Unused (2, 3).  */
-  {0,	      0,	 0,  0},
+  {1,	      1,	 0,  0},
 
   /* MULS/MULU (3, 0).  Positions (3, 1..3) are unused.  */
-  {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}
+  {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0},
+
+  /* V32: Bcc o (4, 0).  */
+  {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (4, 1)},
+
+  /* V32: Bcc [PC+] (4, 1).  */
+  {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (4, 2)},
+
+  /* V32: BA .+12; NOP; BA32 target; NOP; Bcc .-6  (4, 2).  */
+  {0,	      0,	 12, 0},
+
+  /* Unused (4, 3).  */
+  {1,	      1,	 0,  0},
+
+  /* COMMON: Bcc o (5, 0).  The offsets are calculated as for v32.  Code
+     should contain two nop insns (or four if offset size is large or
+     unknown) after every label.  */
+  {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (5, 1)},
+
+  /* COMMON: Bcc [PC+] (5, 1).  */
+  {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (5, 2)},
+
+  /* COMMON: FIXME: ???.  Treat as error currently.  */
+  {0,	      0,	 12, 0},
+
+  /* Unused (5, 3).  */
+  {1,	      1,	 0,  0},
+
+  /* V32: BA o (6, 0).  */
+  {BRANCH_BF_V32, BRANCH_BB_V32, 0,  ENCODE_RELAX (6, 1)},
+
+  /* V32: BA.W (6, 1).  */
+  {BRANCH_WF_V32, BRANCH_WB_V32, 2,  ENCODE_RELAX (6, 2)},
+
+  /* V32: BA.D (6, 2).  */
+  {0,	      0,	 4, 0},
+
+  /* Unused (6, 3).  */
+  {1,	      1,	 0,  0},
+
+  /* LAPC: LAPCQ .+0..15*2,Rn  (7, 0).  */
+  {14*2,   -1*2,	 0,  ENCODE_RELAX (7, 2)},
+
+  /* Unused (7, 1).
+     While there's a shorter sequence, e.g. LAPCQ + an ADDQ or SUBQ,
+     that would affect flags, so we can't do that as it wouldn't be a
+     proper insn expansion of LAPCQ.  This row is associated with a
+     2-byte expansion, so it's unused rather than the next.  */
+  {1,	      1,	 0,  0},
+
+  /* LAPC: LAPC.D (7, 2).  */
+  {0,	      0,	 4, 0},
+
+  /* Unused (7, 3).  */
+  {1,	      1,	 0,  0},
+
+  /* PIC for pre-v32: Bcc o (8, 0).  */
+  {BRANCH_BF, BRANCH_BB, 0,  ENCODE_RELAX (STATE_COND_BRANCH_PIC, 1)},
+
+  /* Bcc [PC+] (8, 1).  */
+  {BRANCH_WF, BRANCH_WB, 2,  ENCODE_RELAX (STATE_COND_BRANCH_PIC, 2)},
+
+  /* 32-bit expansion, PIC (8, 2).  */
+  {0,	      0,	 12, 0},
+
+  /* Unused (8, 3).  */
+  {1,	      1,	 0,  0}
 };
 
-#undef BRANCH_BF
-#undef BRANCH_BB
-#undef BRANCH_WF
-#undef BRANCH_WB
 #undef BDAP_BF
 #undef BDAP_BB
 #undef BDAP_WF
 #undef BDAP_WB
 
-/* Target-specific multicharacter options, not const-declared at usage
-   in 2.9.1 and CVS of 2000-02-16.  */
+/* Target-specific multicharacter options, not const-declared.  */
 struct option md_longopts[] =
 {
 #define OPTION_NO_US (OPTION_MD_BASE + 0)
   {"no-underscore", no_argument, NULL, OPTION_NO_US},
 #define OPTION_US (OPTION_MD_BASE + 1)
   {"underscore", no_argument, NULL, OPTION_US},
-#define OPTION_PIC (OPTION_MD_BASE + 2)
+#define OPTION_PIC (OPTION_US + 1)
   {"pic", no_argument, NULL, OPTION_PIC},
-#define OPTION_MULBUG_ABORT_ON (OPTION_MD_BASE + 3)
+#define OPTION_MULBUG_ABORT_ON (OPTION_PIC + 1)
   {"mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_ON},
-#define OPTION_MULBUG_ABORT_OFF (OPTION_MD_BASE + 4)
+#define OPTION_MULBUG_ABORT_OFF (OPTION_MULBUG_ABORT_ON + 1)
   {"no-mul-bug-abort", no_argument, NULL, OPTION_MULBUG_ABORT_OFF},
+#define OPTION_ARCH (OPTION_MULBUG_ABORT_OFF + 1)
+  {"march", required_argument, NULL, OPTION_ARCH},
   {NULL, no_argument, NULL, 0}
 };
 
-/* Not const-declared at usage in 2.9.1.  */
+/* Not const-declared.  */
 size_t md_longopts_size = sizeof (md_longopts);
 const char *md_shortopts = "hHN";
 
@@ -341,15 +443,22 @@ const char *md_shortopts = "hHN";
    Note that we can't add relocs, because relaxation uses these fixed
    numbers, and md_create_short_jump is called after relaxation.  */
 
-const int md_short_jump_size = 6;
-const int md_long_jump_size = 6;
+int md_short_jump_size = 6;
+
+/* The v32 version has a delay-slot, hence two bytes longer.
+   The pre-v32 PIC version uses a prefixed insn.  */
+#define cris_any_v0_v10_long_jump_size 6
+#define cris_any_v0_v10_long_jump_size_pic 8
+#define crisv32_long_jump_size 8
+
+int md_long_jump_size = XCONCAT2 (DEFAULT_CRIS_ARCH,_long_jump_size);
 
 /* Report output format.  Small changes in output format (like elf
    variants below) can happen until all options are parsed, but after
    that, the output format must remain fixed.  */
 
 const char *
-cris_target_format ()
+cris_target_format (void)
 {
   switch (OUTPUT_FLAVOR)
     {
@@ -367,6 +476,36 @@ cris_target_format ()
     }
 }
 
+/* Return a bfd_mach_cris... value corresponding to the value of
+   cris_arch.  */
+
+unsigned int
+cris_mach (void)
+{
+  unsigned int retval = 0;
+
+  switch (cris_arch)
+    {
+    case arch_cris_common_v10_v32:
+      retval = bfd_mach_cris_v10_v32;
+      break;
+
+    case arch_crisv32:
+      retval = bfd_mach_cris_v32;
+      break;
+
+    case arch_crisv10:
+    case arch_cris_any_v0_v10:
+      retval = bfd_mach_cris_v0_v10;
+      break;
+
+    default:
+      BAD_CASE (cris_arch);
+    }
+
+  return retval;
+}
+
 /* We need a port-specific relaxation function to cope with sym2 - sym1
    relative expressions with both symbols in the same segment (but not
    necessarily in the same frag as this insn), for example:
@@ -375,10 +514,8 @@ cris_target_format ()
    The offset can be 8, 16 or 32 bits long.  */
 
 long
-cris_relax_frag (seg, fragP, stretch)
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-     long stretch ATTRIBUTE_UNUSED;
+cris_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP,
+		 long stretch ATTRIBUTE_UNUSED)
 {
   long growth;
   offsetT aim = 0;
@@ -394,7 +531,11 @@ cris_relax_frag (seg, fragP, stretch)
      because of the different reasons that they aren't relaxable.  */
   switch (fragP->fr_subtype)
     {
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
+    case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
       /* When we get to these states, the frag won't grow any more.  */
       return 0;
@@ -478,27 +619,67 @@ cris_relax_frag (seg, fragP, stretch)
    fr_var starts with a value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment_type)
-     fragS *fragP;
-     /* The segment is either N_DATA or N_TEXT.  */
-     segT segment_type;
+md_estimate_size_before_relax (fragS *fragP, segT segment_type)
 {
   int old_fr_fix;
+  symbolS *symbolP = fragP->fr_symbol;
+
+#define HANDLE_RELAXABLE(state)						\
+    case ENCODE_RELAX (state, STATE_UNDF):				\
+      if (symbolP != NULL						\
+	  && S_GET_SEGMENT (symbolP) == segment_type			\
+	  && !S_IS_WEAK (symbolP))					\
+	/* The symbol lies in the same segment - a relaxable		\
+	   case.  */							\
+	fragP->fr_subtype						\
+	  = ENCODE_RELAX (state, STATE_BYTE);				\
+      else								\
+	/* Unknown or not the same segment, so not relaxable.  */	\
+	fragP->fr_subtype						\
+	  = ENCODE_RELAX (state, STATE_DWORD);				\
+      fragP->fr_var							\
+	= md_cris_relax_table[fragP->fr_subtype].rlx_length;		\
+      break
 
   old_fr_fix = fragP->fr_fix;
 
   switch (fragP->fr_subtype)
     {
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF):
-      if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
-	/* The symbol lies in the same segment - a relaxable case.  */
-	fragP->fr_subtype
-	  = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE);
+      HANDLE_RELAXABLE (STATE_COND_BRANCH);
+      HANDLE_RELAXABLE (STATE_COND_BRANCH_V32);
+      HANDLE_RELAXABLE (STATE_COND_BRANCH_COMMON);
+      HANDLE_RELAXABLE (STATE_COND_BRANCH_PIC);
+      HANDLE_RELAXABLE (STATE_ABS_BRANCH_V32);
+
+    case ENCODE_RELAX (STATE_LAPC, STATE_UNDF):
+      if (symbolP != NULL
+	  && S_GET_SEGMENT (symbolP) == segment_type
+	  && !S_IS_WEAK (symbolP))
+	{
+	  /* The symbol lies in the same segment - a relaxable case.
+	     Check if we currently have an odd offset; we can't code
+	     that into the instruction.  Relaxing presumably only cause
+	     multiple-of-two changes, so we should only need to adjust
+	     for that here.  */
+	  bfd_vma target_address
+	    = (symbolP
+	       ? S_GET_VALUE (symbolP)
+	       : 0) + fragP->fr_offset;
+	  bfd_vma var_part_offset = fragP->fr_fix;
+	  bfd_vma address_of_var_part = fragP->fr_address + var_part_offset;
+	  long offset = target_address - (address_of_var_part - 2);
+
+	  fragP->fr_subtype
+	    = (offset & 1)
+	    ? ENCODE_RELAX (STATE_LAPC, STATE_DWORD)
+	    : ENCODE_RELAX (STATE_LAPC, STATE_BYTE);
+	}
       else
 	/* Unknown or not the same segment, so not relaxable.  */
 	fragP->fr_subtype
-	  = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD);
-      fragP->fr_var = md_cris_relax_table[fragP->fr_subtype].rlx_length;
+	  = ENCODE_RELAX (STATE_LAPC, STATE_DWORD);
+      fragP->fr_var
+	= md_cris_relax_table[fragP->fr_subtype].rlx_length;
       break;
 
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_UNDF):
@@ -512,7 +693,7 @@ md_estimate_size_before_relax (fragP, segment_type)
 	 would in general be no shorter or faster code, only more
 	 complicated.  */
 
-      if (S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
+      if (S_GET_SEGMENT (symbolP) != absolute_section)
 	{
 	  /* Go for dword if not absolute or same segment.  */
 	  fragP->fr_subtype
@@ -534,7 +715,8 @@ md_estimate_size_before_relax (fragP, segment_type)
 	{
 	  /* Absolute expression.  */
 	  long int value;
-	  value = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
+	  value = (symbolP != NULL
+		   ? S_GET_VALUE (symbolP) : 0) + fragP->fr_offset;
 
 	  if (value >= -128 && value <= 127)
 	    {
@@ -571,9 +753,23 @@ md_estimate_size_before_relax (fragP, segment_type)
 	}
       break;
 
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
+    case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
+    case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_WORD):
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_DWORD):
@@ -604,10 +800,8 @@ md_estimate_size_before_relax (fragP, segment_type)
    The caller will turn the frag into a ".space 0".  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
   /* Pointer to first byte in variable-sized part of the frag.  */
   char *var_partp;
@@ -648,24 +842,37 @@ md_convert_frag (abfd, sec, fragP)
 
   switch (fragP->fr_subtype)
     {
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_BYTE):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_BYTE):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_BYTE):
       opcodep[0] = branch_disp ((target_address - address_of_var_part));
       var_part_size = 0;
       break;
 
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_WORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_WORD):
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_WORD):
       /* We had a quick immediate branch, now turn it into a word one i.e. a
 	 PC autoincrement.  */
       opcodep[0] = BRANCH_PC_LOW;
       opcodep[1] &= 0xF0;
       opcodep[1] |= BRANCH_INCR_HIGH;
       md_number_to_chars (var_partp,
-			  (long) (target_address - (address_of_var_part + 2)),
+			  (long)
+			  (target_address
+			   - (address_of_var_part
+			      + (cris_arch == arch_crisv32
+				 || cris_arch == arch_cris_common_v10_v32
+				 ? -2 : 2))),
 			  2);
       var_part_size = 2;
       break;
 
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_DWORD):
+    case ENCODE_RELAX (STATE_COND_BRANCH, STATE_DWORD):
       gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
 			  fragP->fr_symbol, (symbolS *) NULL,
 			  fragP->fr_offset);
@@ -673,6 +880,82 @@ md_convert_frag (abfd, sec, fragP)
       var_part_size = 2 + 2 + 4 + 2;
       break;
 
+    case ENCODE_RELAX (STATE_COND_BRANCH_PIC, STATE_DWORD):
+      gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
+			  fragP->fr_symbol, (symbolS *) NULL,
+			  fragP->fr_offset);
+      /* Twelve bytes added: a branch, nop and a pic-branch-32.  */
+      var_part_size = 2 + 2 + 4 + 2 + 2;
+      break;
+
+    case ENCODE_RELAX (STATE_COND_BRANCH_V32, STATE_DWORD):
+      gen_cond_branch_32 (fragP->fr_opcode, var_partp, fragP,
+			  fragP->fr_symbol, (symbolS *) NULL,
+			  fragP->fr_offset);
+      /* Twelve bytes added: a branch, nop and another branch and nop.  */
+      var_part_size = 2 + 2 + 2 + 4 + 2;
+      break;
+
+    case ENCODE_RELAX (STATE_COND_BRANCH_COMMON, STATE_DWORD):
+      as_bad_where (fragP->fr_file, fragP->fr_line,
+		    _("Relaxation to long branches for .arch common_v10_v32\
+ not implemented"));
+      /* Pretend we have twelve bytes for sake of quelling further
+         errors.  */
+      var_part_size = 2 + 2 + 2 + 4 + 2;
+      break;
+
+    case ENCODE_RELAX (STATE_ABS_BRANCH_V32, STATE_DWORD):
+      /* We had a quick immediate branch or a word immediate ba.  Now
+	 turn it into a dword one.  */
+      opcodep[0] = BA_DWORD_OPCODE & 255;
+      opcodep[1] = (BA_DWORD_OPCODE >> 8) & 255;
+      fix_new (fragP, var_partp - fragP->fr_literal, 4, symbolP,
+	       fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
+      var_part_size = 4;
+      break;
+
+    case ENCODE_RELAX (STATE_LAPC, STATE_BYTE):
+      {
+	long offset = target_address - (address_of_var_part - 2);
+
+	/* This is mostly a sanity check; useful occurrences (if there
+	   really are any) should have been caught in
+	   md_estimate_size_before_relax.  We can (at least
+	   theoretically) stumble over invalid code with odd sizes and
+	   .p2aligns within the code, so emit an error if that happens.
+	   (The generic relaxation machinery is not fit to check this.)  */
+
+	if (offset & 1)
+	  as_bad_where (fragP->fr_file, fragP->fr_line,
+		    _("Complicated LAPC target operand is not\
+ a multiple of two.  Use LAPC.D"));
+
+	/* FIXME: This *is* a sanity check.  Remove when done with.  */
+	if (offset > 15*2 || offset < 0)
+	  as_fatal (_("Internal error found in md_convert_frag: offset %ld.\
+  Please report this."),
+		    offset);
+
+	opcodep[0] |= (offset / 2) & 0xf;
+	var_part_size = 0;
+      }
+      break;
+
+    case ENCODE_RELAX (STATE_LAPC, STATE_DWORD):
+      {
+	md_number_to_chars (opcodep,
+			    LAPC_DWORD_OPCODE + (opcodep[1] & 0xf0) * 256,
+			    2);
+	/* Remember that the reloc is against the position *after* the
+	   relocated contents, so we need to adjust to the start of
+	   the insn.  */
+	fix_new (fragP, var_partp - fragP->fr_literal, 4, fragP->fr_symbol,
+		 fragP->fr_offset + 6, 1, BFD_RELOC_32_PCREL);
+	var_part_size = 4;
+      }
+      break;
+
     case ENCODE_RELAX (STATE_BASE_PLUS_DISP_PREFIX, STATE_BYTE):
       if (symbolP == NULL)
 	as_fatal (_("internal inconsistency in %s: bdapq no symbol"),
@@ -737,34 +1020,49 @@ md_convert_frag (abfd, sec, fragP)
    Used by md_create_long_jump.
 
    This used to be md_create_short_jump, but is now called from
-   md_create_long_jump instead, when sufficient.
-   since the sizes of the jumps are the same.  It used to be brittle,
-   making possibilities for creating bad code.  */
+   md_create_long_jump instead, when sufficient, since the sizes of the
+   jumps are the same for pre-v32.  */
 
 static void
-cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol)
-     char *storep;
-     addressT from_addr;
-     addressT to_addr;
-     fragS *fragP ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+cris_create_short_jump (char *storep, addressT from_addr, addressT to_addr,
+			fragS *fragP ATTRIBUTE_UNUSED,
+			symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
   long int distance;
 
+  /* See md_create_long_jump about the comment on the "+ 2".  */
+  long int max_minimal_minus_distance;
+  long int max_minimal_plus_distance;
+  int nop_opcode;
+
+  if (cris_arch == arch_crisv32)
+    {
+      max_minimal_minus_distance = BRANCH_BB_V32 + 2;
+      max_minimal_plus_distance = BRANCH_BF_V32 + 2;
+      nop_opcode = NOP_OPCODE_V32;
+    }
+  else
+    {
+      max_minimal_minus_distance = BRANCH_BB + 2;
+      max_minimal_plus_distance = BRANCH_BF + 2;
+      nop_opcode = NOP_OPCODE;
+    }
+
   distance = to_addr - from_addr;
 
-  if (-254 <= distance && distance <= 256)
+  if (max_minimal_minus_distance <= distance
+      && distance <= max_minimal_plus_distance)
     {
       /* Create a "short" short jump: "BA distance - 2".  */
       storep[0] = branch_disp (distance - 2);
       storep[1] = BA_QUICK_HIGH;
 
       /* A nop for the delay slot.  */
-      md_number_to_chars (storep + 2, NOP_OPCODE, 2);
+      md_number_to_chars (storep + 2, nop_opcode, 2);
 
       /* The extra word should be filled with something sane too.  Make it
 	 a nop to keep disassembly sane.  */
-      md_number_to_chars (storep + 4, NOP_OPCODE, 2);
+      md_number_to_chars (storep + 4, nop_opcode, 2);
     }
   else
     {
@@ -772,10 +1070,14 @@ cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol)
       md_number_to_chars (storep, BA_PC_INCR_OPCODE, 2);
 
       /* ".WORD distance - 4".  */
-      md_number_to_chars (storep + 2, (long) (distance - 4), 2);
+      md_number_to_chars (storep + 2,
+			  (long) (distance - 4
+				  - (cris_arch == arch_crisv32
+				     ? -4 : 0)),
+			  2);
 
       /* A nop for the delay slot.  */
-      md_number_to_chars (storep + 4, NOP_OPCODE, 2);
+      md_number_to_chars (storep + 4, nop_opcode, 2);
     }
 }
 
@@ -789,33 +1091,59 @@ cris_create_short_jump (storep, from_addr, to_addr, fragP, to_symbol)
    to_symbol  Destination symbol.  */
 
 void
-md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol)
-     char *storep;
-     addressT from_addr;
-     addressT to_addr;
-     fragS *fragP;
-     symbolS *to_symbol;
+md_create_long_jump (char *storep, addressT from_addr, addressT to_addr,
+		     fragS *fragP, symbolS *to_symbol)
 {
   long int distance;
 
+  /* FIXME: What's that "+ 3"?  It comes from the magic numbers that
+     used to be here, it's just translated to the limit macros used in
+     the relax table.  But why + 3?  */
+  long int max_short_minus_distance
+    = cris_arch != arch_crisv32 ? BRANCH_WB + 3 : BRANCH_WB_V32 + 3;
+
+  long int max_short_plus_distance
+    = cris_arch != arch_crisv32 ? BRANCH_WF + 3 : BRANCH_WF_V32 + 3;
+
+  /* Bail out for compatibility mode.  (It seems it can be implemented,
+     perhaps with a 10-byte sequence: "move.d NNNN,$pc/$acr", "jump
+     $acr", "nop"; but doesn't seem worth it at the moment.)  */
+  if (cris_arch == arch_cris_common_v10_v32)
+    as_fatal (_("Out-of-range .word offset handling\
+ is not implemented for .arch common_v10_v32"));
+
   distance = to_addr - from_addr;
 
-  if (-32763 <= distance && distance <= 32772)
-    {
-      /* Then make it a "short" long jump.  */
-      cris_create_short_jump (storep, from_addr, to_addr, fragP,
-			      to_symbol);
-    }
+  if (max_short_minus_distance <= distance
+      && distance <= max_short_plus_distance)
+    /* Then make it a "short" long jump.  */
+    cris_create_short_jump (storep, from_addr, to_addr, fragP,
+			    to_symbol);
   else
     {
-      /* We have a "long" long jump: "JUMP [PC+]".
-	 Make it an "ADD [PC+],PC" if we're supposed to emit PIC code.  */
+      /* We have a "long" long jump: "JUMP [PC+]".  If CRISv32, always
+	 make it a BA.  Else make it an "MOVE [PC=PC+N],P0" if we're supposed
+	 to emit PIC code.  */
       md_number_to_chars (storep,
-			  pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE, 2);
+			  cris_arch == arch_crisv32
+			  ? BA_DWORD_OPCODE
+			  : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
+			     : JUMP_PC_INCR_OPCODE),
+			  2);
 
       /* Follow with a ".DWORD to_addr", PC-relative for PIC.  */
       fix_new (fragP, storep + 2 - fragP->fr_literal, 4, to_symbol,
-	       0, pic ? 1 : 0, pic ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
+	       cris_arch == arch_crisv32 ? 6 : 0,
+	       cris_arch == arch_crisv32 || pic ? 1 : 0,
+	       cris_arch == arch_crisv32 || pic
+	       ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
+
+      /* Follow it with a "NOP" for CRISv32.  */
+      if (cris_arch == arch_crisv32)
+	md_number_to_chars (storep + 6, NOP_OPCODE_V32, 2);
+      else if (pic)
+	/* ...and the rest of the move-opcode for pre-v32 PIC.  */
+	md_number_to_chars (storep + 6, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
     }
 }
 
@@ -823,7 +1151,7 @@ md_create_long_jump (storep, from_addr, to_addr, fragP, to_symbol)
    start of the insn for debug-format use.  */
 
 static char *
-cris_insn_first_word_frag ()
+cris_insn_first_word_frag (void)
 {
   char *insnp = frag_more (2);
 
@@ -842,7 +1170,7 @@ cris_insn_first_word_frag ()
 /* Port-specific assembler initialization.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   const char *hashret = NULL;
   int i = 0;
@@ -852,10 +1180,36 @@ md_begin ()
   if (op_hash == NULL)
     as_fatal (_("Virtual memory exhausted"));
 
+  /* Enable use of ".if ..asm.arch.cris.v32"
+     and ".if ..asm.arch.cris.common_v10_v32" and a few others.  */
+  symbol_table_insert (symbol_new ("..asm.arch.cris.v32", absolute_section,
+				   (cris_arch == arch_crisv32),
+				   &zero_address_frag));
+  symbol_table_insert (symbol_new ("..asm.arch.cris.v10", absolute_section,
+				   (cris_arch == arch_crisv10),
+				   &zero_address_frag));
+  symbol_table_insert (symbol_new ("..asm.arch.cris.common_v10_v32",
+				   absolute_section,
+				   (cris_arch == arch_cris_common_v10_v32),
+				   &zero_address_frag));
+  symbol_table_insert (symbol_new ("..asm.arch.cris.any_v0_v10",
+				   absolute_section,
+				   (cris_arch == arch_cris_any_v0_v10),
+				   &zero_address_frag));
+
   while (cris_opcodes[i].name != NULL)
     {
       const char *name = cris_opcodes[i].name;
-      hashret = hash_insert (op_hash, name, (PTR) &cris_opcodes[i]);
+
+      if (! cris_insn_ver_valid_for_arch (cris_opcodes[i].applicable_version,
+					  cris_arch))
+	{
+	  i++;
+	  continue;
+	}
+
+      /* Need to cast to get rid of "const".  FIXME: Fix hash_insert instead.  */
+      hashret = hash_insert (op_hash, name, (void *) &cris_opcodes[i]);
 
       if (hashret != NULL && *hashret != '\0')
 	as_fatal (_("Can't hash `%s': %s\n"), cris_opcodes[i].name,
@@ -876,8 +1230,7 @@ md_begin ()
 /* Assemble a source line.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   struct cris_instruction output_instruction;
   struct cris_prefix prefix;
@@ -980,7 +1333,12 @@ md_assemble (str)
 	    is_undefined = 1;
 	}
 
-      if (to_seg == now_seg || is_undefined)
+      if (to_seg == now_seg || is_undefined
+	  /* In CRISv32, there *is* a 32-bit absolute branch, so don't
+	     emit the 12-byte sequence for known symbols in other
+	     segments.  */
+	  || (cris_arch == arch_crisv32
+	      && output_instruction.opcode == BA_QUICK_OPCODE))
 	{
 	  /* Handle complex expressions.  */
 	  valueT addvalue
@@ -992,12 +1350,26 @@ md_assemble (str)
 	       ? output_instruction.expr.X_add_symbol
 	       : make_expr_symbol (&output_instruction.expr));
 
-	  /* If is_undefined, then the expression may BECOME now_seg.  */
-	  length_code = is_undefined ? STATE_UNDF : STATE_BYTE;
-
-	  /* Make room for max ten bytes of variable length.  */
-	  frag_var (rs_machine_dependent, 10, 0,
-		    ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code),
+	  /* If is_undefined, the expression may still become now_seg.
+	     That case is handled by md_estimate_size_before_relax.  */
+	  length_code = to_seg == now_seg ? STATE_BYTE : STATE_UNDF;
+
+	  /* Make room for max twelve bytes of variable length for v32 mode
+	     or PIC, ten for v10 and older.  */
+	  frag_var (rs_machine_dependent,
+		    (cris_arch == arch_crisv32
+		     || cris_arch == arch_cris_common_v10_v32
+		     || pic) ? 12 : 10, 0,
+		    ENCODE_RELAX (cris_arch == arch_crisv32
+				  ? (output_instruction.opcode
+				     == BA_QUICK_OPCODE
+				     ? STATE_ABS_BRANCH_V32
+				     : STATE_COND_BRANCH_V32)
+				  : (cris_arch == arch_cris_common_v10_v32
+				     ? STATE_COND_BRANCH_COMMON
+				     : (pic ? STATE_COND_BRANCH_PIC
+					: STATE_COND_BRANCH)),
+				  length_code),
 		    sym, addvalue, opcodep);
 	}
       else
@@ -1005,7 +1377,11 @@ md_assemble (str)
 	  /* We have: to_seg != now_seg && to_seg != undefined_section.
 	     This means it is a branch to a known symbol in another
 	     section, perhaps an absolute address.  Emit a 32-bit branch.  */
-	  char *cond_jump = frag_more (10);
+	  char *cond_jump
+	    = frag_more ((cris_arch == arch_crisv32
+			  || cris_arch == arch_cris_common_v10_v32
+			  || pic)
+			 ? 12 : 10);
 
 	  gen_cond_branch_32 (opcodep, cond_jump, frag_now,
 			      output_instruction.expr.X_add_symbol,
@@ -1057,7 +1433,29 @@ md_assemble (str)
 	  p = frag_more (output_instruction.imm_oprnd_size);
 	  fix_new_exp (frag_now, (p - frag_now->fr_literal),
 		       output_instruction.imm_oprnd_size,
-		       &output_instruction.expr, 0, reloc);
+		       &output_instruction.expr,
+		       reloc == BFD_RELOC_32_PCREL
+		       || reloc == BFD_RELOC_16_PCREL
+		       || reloc == BFD_RELOC_8_PCREL, reloc);
+	}
+      else if (output_instruction.reloc == BFD_RELOC_CRIS_LAPCQ_OFFSET
+	       && output_instruction.expr.X_md != 0)
+	{
+	  /* Handle complex expressions.  */
+	  valueT addvalue
+	    = (output_instruction.expr.X_op_symbol != NULL
+	       ? 0 : output_instruction.expr.X_add_number);
+	  symbolS *sym
+	    = (output_instruction.expr.X_op_symbol != NULL
+	       ? make_expr_symbol (&output_instruction.expr)
+	       : output_instruction.expr.X_add_symbol);
+
+	  /* This is a relaxing construct, so we need a frag_var rather
+	     than the fix_new_exp call below.  */
+	  frag_var (rs_machine_dependent,
+		    4, 0,
+		    ENCODE_RELAX (STATE_LAPC, STATE_UNDF),
+		    sym, addvalue, opcodep);
 	}
       else if (output_instruction.reloc != BFD_RELOC_NONE)
 	{
@@ -1069,7 +1467,12 @@ md_assemble (str)
 	     expressions" - where the expression contains a difference of
 	     two symbols in the same segment.  */
 	  fix_new_exp (frag_now, (opcodep - frag_now->fr_literal), 2,
-		       &output_instruction.expr, 0,
+		       &output_instruction.expr,
+		       output_instruction.reloc == BFD_RELOC_32_PCREL
+		       || output_instruction.reloc == BFD_RELOC_16_PCREL
+		       || output_instruction.reloc == BFD_RELOC_8_PCREL
+		       || (output_instruction.reloc
+			   == BFD_RELOC_CRIS_LAPCQ_OFFSET),
 		       output_instruction.reloc);
 	}
     }
@@ -1078,10 +1481,8 @@ md_assemble (str)
 /* Low level text-to-bits assembly.  */
 
 static void
-cris_process_instruction (insn_text, out_insnp, prefixp)
-     char *insn_text;
-     struct cris_instruction *out_insnp;
-     struct cris_prefix *prefixp;
+cris_process_instruction (char *insn_text, struct cris_instruction *out_insnp,
+			  struct cris_prefix *prefixp)
 {
   char *s;
   char modified_char = 0;
@@ -1097,7 +1498,7 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
      error.  */
   prefixp->kind = PREFIX_NONE;
   prefixp->reloc = BFD_RELOC_NONE;
-  out_insnp->insn_type = CRIS_INSN_NORMAL;
+  out_insnp->insn_type = CRIS_INSN_NONE;
   out_insnp->imm_oprnd_size = 0;
 
   /* Find the end of the opcode mnemonic.  We assume (true in 2.9.1)
@@ -1183,6 +1584,8 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		 Ignore it here.  */
 	      continue;
 
+	    case '[':
+	    case ']':
 	    case ',':
 	    case ' ':
 	      /* These must match exactly.  */
@@ -1190,6 +1593,21 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		continue;
 	      break;
 
+	    case 'A':
+	      /* "ACR", case-insensitive.
+		 Handle a sometimes-mandatory dollar sign as register
+		 prefix.  */
+	      if (*s == REGISTER_PREFIX_CHAR)
+		s++;
+	      else if (demand_register_prefix)
+		break;
+
+	      if ((*s++ != 'a' && s[-1] != 'A')
+		  || (*s++ != 'c' && s[-1] != 'C')
+		  || (*s++ != 'r' && s[-1] != 'R'))
+		break;
+	      continue;
+
 	    case 'B':
 	      /* This is not really an operand, but causes a "BDAP
 		 -size,SP" prefix to be output, for PUSH instructions.  */
@@ -1237,6 +1655,19 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		  continue;
 		}
 
+ 	      /* For 'd', check for an optional ".d" or ".D" at the
+                 start of the operands, followed by a space character.  */
+	    case 'd':
+	      if (modified_char == '.' && *s == '.')
+		{
+		  if ((s[1] != 'd' && s[1] == 'D')
+		      || ! ISSPACE (s[2]))
+		    break;
+		  s += 2;
+		  continue;
+		}
+	      continue;
+
 	    case 'D':
 	      /* General register in bits <15:12> and <3:0>.  */
 	      if (! get_gen_reg (&s, &regno))
@@ -1317,7 +1748,8 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 
 	    case 'm':
 	      /* A size modifier, B, W or D, to be put in bits <5:4>.  */
-	      if (! get_bwd_size_modifier (&s, &size_bits))
+	      if (modified_char != '.'
+		  || ! get_bwd_size_modifier (&s, &size_bits))
 		break;
 	      else
 		{
@@ -1335,8 +1767,25 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		  continue;
 		}
 
+	    case 'Q':
+	      /* A 8-bit quick BDAP expression, "expr,R".  */
+	      if (! cris_get_expression (&s, &out_insnp->expr))
+		break;
+
+	      if (*s != ',')
+		break;
+
+	      s++;
+
+	      if (!get_gen_reg (&s, &regno))
+		break;
+
+	      out_insnp->opcode |= regno << 12;
+	      out_insnp->reloc = BFD_RELOC_CRIS_SIGNED_8;
+	      continue;
+	      
 	    case 'O':
-	      /* A BDAP expression for any size, "expr,r".  */
+	      /* A BDAP expression for any size, "expr,R".  */
 	      if (! cris_get_expression (&s, &prefixp->expr))
 		break;
 	      else
@@ -1420,7 +1869,7 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 	    case 's':
 	      /* Source operand in bits <10>, <3:0> and optionally a
 		 prefix; i.e. an indirect operand or an side-effect
-		 prefix.  */
+		 prefix (where valid).  */
 	      if (! get_autoinc_prefix_or_indir_op (&s, prefixp, &mode,
 						    &regno,
 						    &imm_expr_found,
@@ -1452,6 +1901,71 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		  continue;
 		}
 
+	    case 'N':
+	    case 'Y':
+	      /* Like 's', but immediate operand only.  Also does not
+		 modify insn.  There are no insns where a PIC reloc
+		 specifier makes sense.  */
+	      if (cris_get_expression (&s, &out_insnp->expr))
+		{
+		  imm_expr_found = 1;
+		  continue;
+		}
+	      break;
+
+	    case 'n':
+	      /* Like 'N', but PC-relative to the start of the insn.
+		 There might be a :PLT to request a PLT entry.  */
+	      if (cris_get_expression (&s, &out_insnp->expr))
+		{
+		  imm_expr_found = 1;
+		  out_insnp->reloc = BFD_RELOC_32_PCREL;
+
+		  /* We have to adjust the expression, because that
+		     relocation is to the location *after* the
+		     relocation.  So add 2 for the insn and 4 for the
+		     relocation.  */
+		  out_insnp->expr.X_add_number += 6;
+
+		  if (pic && *s == PIC_SUFFIX_CHAR)
+		    cris_get_pic_suffix (&s, &out_insnp->reloc,
+					 &out_insnp->expr);
+
+		  continue;
+		}
+	      break;
+
+	    case 'U':
+	      /* Maybe 'u', maybe 'n'.  Only for LAPC/LAPCQ.  */
+	      if (cris_get_expression (&s, &out_insnp->expr))
+		{
+		  out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
+
+		  /* Define 1 as relaxing.  */
+		  out_insnp->expr.X_md = 1;
+		  continue;
+		}
+	      break;
+
+	    case 'u':
+	      /* Four PC-relative bits in <3:0> representing <4:1>:0 of
+		 an offset relative to the beginning of the current
+		 insn.  */
+	      if (cris_get_expression (&s, &out_insnp->expr))
+		{
+		  out_insnp->reloc = BFD_RELOC_CRIS_LAPCQ_OFFSET;
+
+		  /* Define 0 as non-relaxing.  */
+		  out_insnp->expr.X_md = 0;
+
+		  /* We have to adjust the expression, because that
+		     relocation is to the location *after* the
+		     insn.  So add 2 for the insn.  */
+		  out_insnp->expr.X_add_number += 2;
+		  continue;
+		}
+	      break;
+
 	    case 'x':
 	      /* Rs.m in bits <15:12> and <5:4>.  */
 	      if (! get_gen_reg (&s, &regno)
@@ -1506,6 +2020,15 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		  continue;
 		}
 
+	    case 'T':
+	      if (cris_arch == arch_crisv32
+		  && get_sup_reg (&s, &regno))
+		{
+		  out_insnp->opcode |= regno << 12;
+		  continue;
+		}
+	      break;
+
 	    default:
 	      BAD_CASE (*args);
 	    }
@@ -1520,9 +2043,19 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 	{
 	  /* If it's just that the args don't match, maybe the next
 	     item in the table is the same opcode but with
-	     matching operands.  */
+	     matching operands.  First skip any invalid ones.  */
+	  while (instruction[1].name != NULL
+		 && strcmp (instruction->name, instruction[1].name) == 0
+		 && ! cris_insn_ver_valid_for_arch (instruction[1]
+						    .applicable_version,
+						    cris_arch))
+	    ++instruction;
+
 	  if (instruction[1].name != NULL
-	      && ! strcmp (instruction->name, instruction[1].name))
+	      && strcmp (instruction->name, instruction[1].name) == 0
+	      && cris_insn_ver_valid_for_arch (instruction[1]
+					       .applicable_version,
+					       cris_arch))
 	    {
 	      /* Yep.  Restart and try that one instead.  */
 	      ++instruction;
@@ -1534,6 +2067,11 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 	      /* We've come to the end of instructions with this
 		 opcode, so it must be an error.  */
 	      as_bad (_("Illegal operands"));
+
+	      /* As discard_rest_of_line, but without continuing to the
+		 next line.  */
+	      while (!is_end_of_line[(unsigned char) *input_line_pointer])
+		input_line_pointer++;
 	      return;
 	    }
 	}
@@ -1558,52 +2096,91 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
 		  break;
 
 		case SIZE_SPEC_REG:
-		  switch (out_insnp->spec_reg->reg_size)
-		    {
-		    case 1:
-		      if (out_insnp->expr.X_op == O_constant
-			  && (out_insnp->expr.X_add_number < -128
-			      || out_insnp->expr.X_add_number > 255))
-			as_bad (_("Immediate value not in 8 bit range: %ld"),
-				out_insnp->expr.X_add_number);
-		      /* Fall through.  */
-		    case 2:
-		      /* FIXME:  We need an indicator in the instruction
-			 table to pass on, to indicate if we need to check
-			 overflow for a signed or unsigned number.  */
-		      if (out_insnp->expr.X_op == O_constant
-			  && (out_insnp->expr.X_add_number < -32768
-			      || out_insnp->expr.X_add_number > 65535))
-			as_bad (_("Immediate value not in 16 bit range: %ld"),
-				out_insnp->expr.X_add_number);
-		      out_insnp->imm_oprnd_size = 2;
-		      break;
-
-		    case 4:
-		      out_insnp->imm_oprnd_size = 4;
-		      break;
-
-		    default:
-		      BAD_CASE (out_insnp->spec_reg->reg_size);
-		    }
+		  if (cris_arch == arch_crisv32)
+		    /* All immediate loads of special registers are
+		       32-bit on CRISv32.  */
+		    out_insnp->imm_oprnd_size = 4;
+		  else
+		    switch (out_insnp->spec_reg->reg_size)
+		      {
+		      case 1:
+			if (out_insnp->expr.X_op == O_constant
+			    && (out_insnp->expr.X_add_number < -128
+				|| out_insnp->expr.X_add_number > 255))
+			  as_bad (_("Immediate value not in 8 bit range: %ld"),
+				  out_insnp->expr.X_add_number);
+			/* Fall through.  */
+		      case 2:
+			/* FIXME:  We need an indicator in the instruction
+			   table to pass on, to indicate if we need to check
+			   overflow for a signed or unsigned number.  */
+			if (out_insnp->expr.X_op == O_constant
+			    && (out_insnp->expr.X_add_number < -32768
+				|| out_insnp->expr.X_add_number > 65535))
+			  as_bad (_("Immediate value not in 16 bit range: %ld"),
+				  out_insnp->expr.X_add_number);
+			out_insnp->imm_oprnd_size = 2;
+			break;
+
+		      case 4:
+			out_insnp->imm_oprnd_size = 4;
+			break;
+
+		      default:
+			BAD_CASE (out_insnp->spec_reg->reg_size);
+		      }
 		  break;
 
 		case SIZE_FIELD:
+		case SIZE_FIELD_SIGNED:
+		case SIZE_FIELD_UNSIGNED:
 		  switch (size_bits)
 		    {
+		      /* FIXME: Find way to pass un/signedness to
+			 caller, and set reloc type instead, postponing
+			 this check until cris_number_to_imm.  That
+			 necessarily corrects the reloc type for the
+			 byte case, maybe requiring further changes.  */
 		    case 0:
-		      if (out_insnp->expr.X_op == O_constant
-			  && (out_insnp->expr.X_add_number < -128
-			      || out_insnp->expr.X_add_number > 255))
-			as_bad (_("Immediate value not in 8 bit range: %ld"),
-				out_insnp->expr.X_add_number);
+		      if (out_insnp->expr.X_op == O_constant)
+			{
+			  if (instruction->imm_oprnd_size == SIZE_FIELD
+			      && (out_insnp->expr.X_add_number < -128
+				  || out_insnp->expr.X_add_number > 255))
+			    as_bad (_("Immediate value not in 8 bit range: %ld"),
+				    out_insnp->expr.X_add_number);
+			  else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
+			      && (out_insnp->expr.X_add_number < -128
+				  || out_insnp->expr.X_add_number > 127))
+			    as_bad (_("Immediate value not in 8 bit signed range: %ld"),
+				    out_insnp->expr.X_add_number);
+			  else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
+				   && (out_insnp->expr.X_add_number < 0
+				       || out_insnp->expr.X_add_number > 255))
+			    as_bad (_("Immediate value not in 8 bit unsigned range: %ld"),
+				    out_insnp->expr.X_add_number);
+			}
+
 		      /* Fall through.  */
 		    case 1:
-		      if (out_insnp->expr.X_op == O_constant
-			  && (out_insnp->expr.X_add_number < -32768
-			      || out_insnp->expr.X_add_number > 65535))
-			as_bad (_("Immediate value not in 16 bit range: %ld"),
-				out_insnp->expr.X_add_number);
+		      if (out_insnp->expr.X_op == O_constant)
+			{
+			  if (instruction->imm_oprnd_size == SIZE_FIELD
+			      && (out_insnp->expr.X_add_number < -32768
+				  || out_insnp->expr.X_add_number > 65535))
+			    as_bad (_("Immediate value not in 16 bit range: %ld"),
+				    out_insnp->expr.X_add_number);
+			  else if (instruction->imm_oprnd_size == SIZE_FIELD_SIGNED
+			      && (out_insnp->expr.X_add_number < -32768
+				  || out_insnp->expr.X_add_number > 32767))
+			    as_bad (_("Immediate value not in 16 bit signed range: %ld"),
+				    out_insnp->expr.X_add_number);
+			  else if (instruction->imm_oprnd_size == SIZE_FIELD_UNSIGNED
+			      && (out_insnp->expr.X_add_number < 0
+				  || out_insnp->expr.X_add_number > 65535))
+			    as_bad (_("Immediate value not in 16 bit unsigned range: %ld"),
+				    out_insnp->expr.X_add_number);
+			}
 		      out_insnp->imm_oprnd_size = 2;
 		      break;
 
@@ -1647,9 +2224,7 @@ cris_process_instruction (insn_text, out_insnp, prefixp)
    Return 1 iff a correct size modifier is found, else 0.  */
 
 static int
-get_bwd_size_modifier (cPP, size_bitsp)
-     char **cPP;
-     int *size_bitsp;
+get_bwd_size_modifier (char **cPP, int *size_bitsp)
 {
   if (**cPP != '.')
     return 0;
@@ -1699,9 +2274,7 @@ get_bwd_size_modifier (cPP, size_bitsp)
    Return 1 iff a correct size modifier is found, else 0.  */
 
 static int
-get_bw_size_modifier (cPP, size_bitsp)
-     char **cPP;
-     int *size_bitsp;
+get_bw_size_modifier (char **cPP, int *size_bitsp)
 {
   if (**cPP != '.')
     return 0;
@@ -1746,9 +2319,7 @@ get_bw_size_modifier (cPP, size_bitsp)
 	    else 0.  */
 
 static int
-get_gen_reg (cPP, regnop)
-     char **cPP;
-     int *regnop;
+get_gen_reg (char **cPP, int *regnop)
 {
   char *oldp;
   oldp = *cPP;
@@ -1767,7 +2338,18 @@ get_gen_reg (cPP, regnop)
       (*cPP)++;
 
       if ((**cPP == 'C' || **cPP == 'c')
-	  && ! ISALNUM ((*cPP)[1]))
+	  && ! ISALNUM ((*cPP)[1])
+	  /* Here's a little twist: For v32 and the compatibility mode,
+	     we only recognize PC as a register number if there's '+]'
+	     after.  We don't consume that, but the presence can only be
+	     valid after a register in a post-increment context, which
+	     is also the only valid context for PC as a register for
+	     v32.  Not that it's used very often, but saying "MOVE.D
+	     [PC+],R5" should remain valid.  It's not supported for
+	     jump-type insns or other insns with no [Rn+] mode, though.  */
+	  && ((cris_arch != arch_crisv32
+	       && cris_arch != arch_cris_common_v10_v32)
+	      || ((*cPP)[1] == '+' && (*cPP)[2] == ']')))
 	{
 	  /* It's "PC": consume the "c" and we're done.  */
 	  (*cPP)++;
@@ -1776,6 +2358,20 @@ get_gen_reg (cPP, regnop)
 	}
       break;
 
+      /* Like with PC, we recognize ACR, but only if it's *not* followed
+	 by '+', and only for v32.  */
+    case 'A':
+    case 'a':
+      if (cris_arch != arch_crisv32
+	  || ((*cPP)[1] != 'c' && (*cPP)[1] != 'C')
+	  || ((*cPP)[2] != 'r' && (*cPP)[2] != 'R')
+	  || ISALNUM ((*cPP)[3])
+	  || (*cPP)[3] == '+')
+	break;
+      (*cPP) += 3;
+      *regnop = 15;
+      return 1;
+
     case 'R':
     case 'r':
       /* Hopefully r[0-9] or r1[0-5].  Consume 'R' or 'r'.  */
@@ -1846,9 +2442,7 @@ get_gen_reg (cPP, regnop)
    Return 1 iff a correct special register name is found.  */
 
 static int
-get_spec_reg (cPP, sregpp)
-     char **cPP;
-     const struct cris_spec_reg **sregpp;
+get_spec_reg (char **cPP, const struct cris_spec_reg **sregpp)
 {
   char *s1;
   const char *s2;
@@ -1878,7 +2472,9 @@ get_spec_reg (cPP, sregpp)
       /* For a match, we must have consumed the name in the table, and we
 	 must be outside what could be part of a name.	Assume here that a
 	 test for alphanumerics is sufficient for a name test.  */
-      if (*s2 == 0 && ! ISALNUM (*s1))
+      if (*s2 == 0 && ! ISALNUM (*s1)
+	  && cris_insn_ver_valid_for_arch (sregp->applicable_version,
+					   cris_arch))
 	{
 	  /* We have a match.  Update the pointer and be done.  */
 	  *cPP = s1;
@@ -1891,6 +2487,62 @@ get_spec_reg (cPP, sregpp)
   return 0;
 }
 
+/* Get a support register from the string pointed out by *cPP. The
+   variable *cPP is advanced to the character following the support-
+   register name if one is found, and retains its original position
+   otherwise.
+
+   cPP	    Pointer to pointer to string starting with a support-register
+	    name.
+
+   sregpp   Pointer to int containing the register number.
+
+   Return 1 iff a correct support-register name is found.  */
+
+static int
+get_sup_reg (char **cPP, int *regnop)
+{
+  char *s1;
+  const char *s2;
+  char *name_begin = *cPP;
+
+  const struct cris_support_reg *sregp;
+
+  /* Handle a sometimes-mandatory dollar sign as register prefix.  */
+  if (*name_begin == REGISTER_PREFIX_CHAR)
+    name_begin++;
+  else if (demand_register_prefix)
+    return 0;
+
+  /* Loop over all support-registers.  */
+  for (sregp = cris_support_regs; sregp->name != NULL; sregp++)
+    {
+      /* Start over from beginning of the supposed name.  */
+      s1 = name_begin;
+      s2 = sregp->name;
+
+      while (*s2 != '\0' && TOLOWER (*s1) == *s2)
+	{
+	  s1++;
+	  s2++;
+	}
+
+      /* For a match, we must have consumed the name in the table, and we
+	 must be outside what could be part of a name.	Assume here that a
+	 test for alphanumerics is sufficient for a name test.  */
+      if (*s2 == 0 && ! ISALNUM (*s1))
+	{
+	  /* We have a match.  Update the pointer and be done.  */
+	  *cPP = s1;
+	  *regnop = sregp->number;
+	  return 1;
+	}
+    }
+
+  /* If we got here, we did not find any name.  */
+  return 0;
+}
+
 /* Get an unprefixed or side-effect-prefix operand from the string pointed
    out by *cPP.  The pointer *cPP is advanced to the character following
    the indirect operand if we have success, else it contains an undefined
@@ -1917,14 +2569,9 @@ get_spec_reg (cPP, sregpp)
    Return 1 iff a correct indirect operand is found.  */
 
 static int
-get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
-				imm_foundp, imm_exprP)
-     char **cPP;
-     struct cris_prefix *prefixp;
-     int *is_autoincp;
-     int *src_regnop;
-     int *imm_foundp;
-     expressionS *imm_exprP;
+get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp,
+				int *is_autoincp, int *src_regnop,
+				int *imm_foundp, expressionS *imm_exprP)
 {
   /* Assume there was no immediate mode expression.  */
   *imm_foundp = 0;
@@ -1968,7 +2615,12 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
 
 	    case '=':
 	      /* This must be indexed with assign, or offset with assign
-		 to match.  */
+		 to match.  Not supported for crisv32 or in
+		 compatibility mode.  */
+	      if (cris_arch == arch_crisv32
+		  || cris_arch == arch_cris_common_v10_v32)
+		return 0;
+
 	      (*cPP)++;
 
 	      /* Either way, the next thing must be a register.  */
@@ -2174,9 +2826,7 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
    Returns 1 iff a correct indirect operand is found.  */
 
 static int
-get_3op_or_dip_prefix_op (cPP, prefixp)
-     char **cPP;
-     struct cris_prefix *prefixp;
+get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp)
 {
   int reg_number;
 
@@ -2297,8 +2947,14 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
 		prefixp->opcode |= size_bits << 4;
 	    }
 	  /* Seen "[rN+", but not a '[' or a register, so then
-	     it must be a constant "I".  */
-	  else if (cris_get_expression (cPP, &prefixp->expr))
+	     it must be a constant "I".
+
+	     As a quality of implementation improvement, we check for a
+	     closing ']', like in an erroneous "[rN+]".  If we don't,
+	     the expression parser will emit a confusing "bad
+	     expression" when it sees the ']', probably because it
+	     doesn't like seeing no expression.  */
+	  else if (**cPP != ']' && cris_get_expression (cPP, &prefixp->expr))
 	    {
 	      /* Expression found, so fill in the bits of offset
 		 mode and drop down to check the closing ']'.  */
@@ -2406,9 +3062,7 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
    Return 1 iff a correct expression is found.  */
 
 static int
-cris_get_expression (cPP, exprP)
-     char **cPP;
-     expressionS *exprP;
+cris_get_expression (char **cPP, expressionS *exprP)
 {
   char *saved_input_line_pointer;
   segT exp;
@@ -2419,6 +3073,17 @@ cris_get_expression (cPP, exprP)
   saved_input_line_pointer = input_line_pointer;
   input_line_pointer = *cPP;
 
+  /* Avoid a common error, confusing addressing modes.  Beware that the
+     call to expression below does not signal that error; it treats []
+     as parentheses, unless #define NEED_INDEX_OPERATOR in which case it
+     gives them other confusing semantics rather than plain outlawing
+     them, which is what we want.  */
+  if (*input_line_pointer == '[')
+    {
+      input_line_pointer = saved_input_line_pointer;
+      return 0;
+    }
+
   exp = expression (exprP);
   if (exprP->X_op == O_illegal || exprP->X_op == O_absent)
     {
@@ -2444,9 +3109,7 @@ cris_get_expression (cPP, exprP)
    Return 1 iff a correct flags expression is found.  */
 
 static int
-get_flags (cPP, flagsp)
-     char **cPP;
-     int *flagsp;
+get_flags (char **cPP, int *flagsp)
 {
   for (;;)
     {
@@ -2454,15 +3117,49 @@ get_flags (cPP, flagsp)
 	{
 	case 'd':
 	case 'D':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
+					      cris_arch))
+	    return 0;
+	  *flagsp |= 0x80;
+	  break;
+
 	case 'm':
 	case 'M':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
+					      cris_arch))
+	    return 0;
 	  *flagsp |= 0x80;
 	  break;
 
 	case 'e':
 	case 'E':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v0_3,
+					      cris_arch))
+	    return 0;
+	  *flagsp |= 0x40;
+	  break;
+
 	case 'b':
 	case 'B':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v8_10,
+					      cris_arch))
+	    return 0;
+	  *flagsp |= 0x40;
+	  break;
+
+	case 'p':
+	case 'P':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
+					      cris_arch))
+	    return 0;
+	  *flagsp |= 0x80;
+	  break;
+
+	case 'u':
+	case 'U':
+	  if (! cris_insn_ver_valid_for_arch (cris_ver_v32p,
+					      cris_arch))
+	    return 0;
 	  *flagsp |= 0x40;
 	  break;
 
@@ -2513,15 +3210,15 @@ get_flags (cPP, flagsp)
 }
 
 /* Generate code and fixes for a BDAP prefix.
+   For v32, this handles ADDOQ because thankfully the opcodes are the
+   same.
 
    base_regno	Int containing the base register number.
 
    exprP	Pointer to structure containing the offset expression.  */
 
 static void
-gen_bdap (base_regno, exprP)
-     int base_regno;
-     expressionS *exprP;
+gen_bdap (int base_regno, expressionS *exprP)
 {
   unsigned int opcode;
   char *opcodep;
@@ -2586,11 +3283,14 @@ gen_bdap (base_regno, exprP)
    offset  The displacement value in bytes.  */
 
 static int
-branch_disp (offset)
-     int offset;
+branch_disp (int offset)
 {
   int disp;
 
+  /* Adjust all short branch offsets here.  */
+  if (cris_arch == arch_crisv32 || cris_arch == arch_cris_common_v10_v32)
+    offset += 2;
+
   disp = offset & 0xFE;
 
   if (offset < 0)
@@ -2615,14 +3315,36 @@ branch_disp (offset)
    add_num.  */
 
 static void
-gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num)
-     char *opcodep;
-     char *writep;
-     fragS *fragP;
-     symbolS *add_symP;
-     symbolS *sub_symP;
-     long int add_num;
+gen_cond_branch_32 (char *opcodep, char *writep, fragS *fragP,
+		    symbolS *add_symP, symbolS *sub_symP, long int add_num)
 {
+  int nop_opcode;
+  int opc_offset;
+  int branch_offset;
+
+  if (cris_arch == arch_crisv32)
+    {
+      nop_opcode = NOP_OPCODE_V32;
+      opc_offset = 10;
+      branch_offset = -2 - 8;
+    }
+  else if (pic)
+    {
+      nop_opcode = NOP_OPCODE;
+      opc_offset = 10;
+      branch_offset = -2 - 8;
+    }
+  else
+    {
+      nop_opcode = NOP_OPCODE;
+      opc_offset = 8;
+      branch_offset = -2 - 6;
+    }
+
+  /* We should never get here for compatibility mode.  */
+  if (cris_arch == arch_cris_common_v10_v32)
+    as_fatal (_("Calling gen_cond_branch_32 for .arch common_v10_v32\n"));
+
   if (warn_for_branch_expansion)
     as_warn_where (fragP->fr_file, fragP->fr_line,
 		   _("32-bit conditional branch generated"));
@@ -2638,8 +3360,8 @@ gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num)
      it's not the optimal extended construct, but we should get this
      rarely enough that it shouldn't matter.  */
 
-  writep[8] = branch_disp (-2 - 6);
-  writep[9] = opcodep[1];
+  writep[opc_offset] = branch_disp (branch_offset);
+  writep[opc_offset + 1] = opcodep[1];
 
   /* Then, we change the branch to an unconditional branch over the
      extended part, to the new location of the Bcc:
@@ -2649,16 +3371,21 @@ gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num)
      Note that these two writes are to currently different locations,
      merged later.  */
 
-  md_number_to_chars (opcodep, BA_QUICK_OPCODE + 8, 2);
-  md_number_to_chars (writep, NOP_OPCODE, 2);
+  md_number_to_chars (opcodep, BA_QUICK_OPCODE
+		      + (cris_arch == arch_crisv32 ? 12 : (pic ? 10 : 8)),
+		      2);
+  md_number_to_chars (writep, nop_opcode, 2);
 
   /* Then the extended thing, the 32-bit jump insn.
        opcodep+4: JUMP [PC+]
      or, in the PIC case,
-       opcodep+4: ADD [PC+],PC.  */
+       opcodep+4: MOVE [PC=PC+N],P0.  */
 
   md_number_to_chars (writep + 2,
-		      pic ? ADD_PC_INCR_OPCODE : JUMP_PC_INCR_OPCODE, 2);
+		      cris_arch == arch_crisv32
+		      ? BA_DWORD_OPCODE
+		      : (pic ? MOVE_PC_INCR_OPCODE_PREFIX
+			 : JUMP_PC_INCR_OPCODE), 2);
 
   /* We have to fill in the actual value too.
        opcodep+6: .DWORD
@@ -2668,10 +3395,12 @@ gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num)
   if (add_symP == NULL && sub_symP == NULL)
     {
       /* An absolute address.  */
-      if (pic)
+      if (pic || cris_arch == arch_crisv32)
 	fix_new (fragP, writep + 4 - fragP->fr_literal, 4,
 		 section_symbol (absolute_section),
-		 add_num, 1, BFD_RELOC_32_PCREL);
+		 add_num
+		 + (cris_arch == arch_crisv32 ? 6 : 0),
+		 1, BFD_RELOC_32_PCREL);
       else
 	md_number_to_chars (writep + 4, add_num, 4);
     }
@@ -2683,16 +3412,25 @@ gen_cond_branch_32 (opcodep, writep, fragP, add_symP, sub_symP, add_num)
 
       /* Not absolute, we have to make it a frag for later evaluation.  */
       fix_new (fragP, writep + 4 - fragP->fr_literal, 4, add_symP,
-	       add_num, pic ? 1 : 0, pic ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
+	       add_num + (cris_arch == arch_crisv32 ? 6 : 0),
+	       pic || cris_arch == arch_crisv32 ? 1 : 0,
+	       pic || cris_arch == arch_crisv32
+	       ? BFD_RELOC_32_PCREL : BFD_RELOC_32);
     }
+
+  if (cris_arch == arch_crisv32)
+    /* Follow it with a "NOP" for CRISv32.  */
+    md_number_to_chars (writep + 8, NOP_OPCODE_V32, 2);
+  else if (pic)
+    /* ...and the rest of the move-opcode for pre-v32 PIC.  */
+    md_number_to_chars (writep + 8, MOVE_PC_INCR_OPCODE_SUFFIX, 2);
 }
 
 /* Get the size of an immediate-reloc in bytes.  Only valid for PIC
    relocs.  */
 
 static unsigned int
-cris_get_pic_reloc_size (reloc)
-     bfd_reloc_code_real_type reloc;
+cris_get_pic_reloc_size (bfd_reloc_code_real_type reloc)
 {
   return reloc == BFD_RELOC_CRIS_16_GOTPLT || reloc == BFD_RELOC_CRIS_16_GOT
     ? 2 : 4;
@@ -2702,10 +3440,8 @@ cris_get_pic_reloc_size (reloc)
    Adjust *EXPRP with any addend found after the PIC suffix.  */
 
 static void
-cris_get_pic_suffix (cPP, relocp, exprP)
-     char **cPP;
-     bfd_reloc_code_real_type *relocp;
-     expressionS *exprP;
+cris_get_pic_suffix (char **cPP, bfd_reloc_code_real_type *relocp,
+		     expressionS *exprP)
 {
   char *s = *cPP;
   unsigned int i;
@@ -2772,7 +3508,7 @@ cris_get_pic_suffix (cPP, relocp, exprP)
      syntax error.  */
 }
 
-/* This *could* be:
+/* This *could* have been:
 
    Turn a string in input_line_pointer into a floating point constant
    of type TYPE, and store the appropriate bytes in *LITP.  The number
@@ -2793,10 +3529,8 @@ cris_get_pic_suffix (cPP, relocp, exprP)
    find out the correct bit patterns and use them.  */
 
 char *
-md_atof (type, litp, sizep)
-     char type ATTRIBUTE_UNUSED;
-     char *litp ATTRIBUTE_UNUSED;
-     int *sizep ATTRIBUTE_UNUSED;
+md_atof (int type ATTRIBUTE_UNUSED, char *litp ATTRIBUTE_UNUSED,
+	 int *sizep ATTRIBUTE_UNUSED)
 {
   /* FIXME:  Is this function mentioned in the internals.texi manual?  If
      not, add it.  */
@@ -2819,12 +3553,7 @@ md_atof (type, litp, sizep)
    seg	      The segment containing this number.  */
 
 static void
-cris_number_to_imm (bufp, val, n, fixP, seg)
-     char *bufp;
-     long val;
-     int n;
-     fixS *fixP;
-     segT seg;
+cris_number_to_imm (char *bufp, long val, int n, fixS *fixP, segT seg)
 {
   segT sym_seg;
 
@@ -2843,15 +3572,19 @@ cris_number_to_imm (bufp, val, n, fixP, seg)
     switch (fixP->fx_r_type)
       {
 	/* These must be fully resolved when getting here.  */
-      case BFD_RELOC_32_PCREL:
       case BFD_RELOC_16_PCREL:
       case BFD_RELOC_8_PCREL:
-	as_bad_where (fixP->fx_frag->fr_file, fixP->fx_frag->fr_line,
+	as_bad_where (fixP->fx_file, fixP->fx_line,
 		      _("PC-relative relocation must be trivially resolved"));
       default:
 	;
       }
 
+  /* Only do this for old-arch binaries.  */
+  if (cris_arch != arch_cris_any_v0_v10
+      && (fixP->fx_addsy != NULL || fixP->fx_pcrel))
+    return;
+
   switch (fixP->fx_r_type)
     {
       /* Ditto here, we put the addend into the object code as
@@ -2870,8 +3603,14 @@ cris_number_to_imm (bufp, val, n, fixP, seg)
 	 being relocated for these.  */
       break;
 
-    case BFD_RELOC_32:
     case BFD_RELOC_32_PCREL:
+      /* If this one isn't fully resolved, we don't want to put anything
+	 in the object.  */
+      if (fixP->fx_addsy != NULL || fixP->fx_pcrel)
+	break;
+
+      /* Fall through.  */
+    case BFD_RELOC_32:
       /* No use having warnings here, since most hosts have a 32-bit type
 	 for "long" (which will probably change soon, now that I wrote
 	 this).  */
@@ -2883,14 +3622,24 @@ cris_number_to_imm (bufp, val, n, fixP, seg)
 
       /* FIXME: The 16 and 8-bit cases should have a way to check
 	 whether a signed or unsigned (or any signedness) number is
-	 accepted.
-	 FIXME: Does the as_bad calls find the line number by themselves,
-	 or should we change them into as_bad_where?  */
+	 accepted.  */
 
     case BFD_RELOC_16:
     case BFD_RELOC_16_PCREL:
       if (val > 0xffff || val < -32768)
-	as_bad (_("Value not in 16 bit range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 16 bit range: %ld"), val);
+      if (! fixP->fx_addsy)
+	{
+	  bufp[1] = (val >> 8) & 0xFF;
+	  bufp[0] = val & 0xFF;
+	}
+      break;
+
+    case BFD_RELOC_CRIS_SIGNED_16:
+      if (val > 32767 || val < -32768)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 16 bit signed range: %ld"), val);
       if (! fixP->fx_addsy)
 	{
 	  bufp[1] = (val >> 8) & 0xFF;
@@ -2901,35 +3650,50 @@ cris_number_to_imm (bufp, val, n, fixP, seg)
     case BFD_RELOC_8:
     case BFD_RELOC_8_PCREL:
       if (val > 255 || val < -128)
-	as_bad (_("Value not in 8 bit range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line, _("Value not in 8 bit range: %ld"), val);
       if (! fixP->fx_addsy)
 	bufp[0] = val & 0xFF;
       break;
 
+    case BFD_RELOC_CRIS_SIGNED_8:
+      if (val > 127 || val < -128)
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 8 bit signed range: %ld"), val);
+      if (! fixP->fx_addsy)
+	bufp[0] = val & 0xFF;
+      break;
+
+    case BFD_RELOC_CRIS_LAPCQ_OFFSET:
+      /* FIXME: Test-cases for out-of-range values.  Probably also need
+	 to use as_bad_where.  */
     case BFD_RELOC_CRIS_UNSIGNED_4:
       if (val > 15 || val < 0)
-	as_bad (_("Value not in 4 bit unsigned range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 4 bit unsigned range: %ld"), val);
       if (! fixP->fx_addsy)
 	bufp[0] |= val & 0x0F;
       break;
 
     case BFD_RELOC_CRIS_UNSIGNED_5:
       if (val > 31 || val < 0)
-	as_bad (_("Value not in 5 bit unsigned range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 5 bit unsigned range: %ld"), val);
       if (! fixP->fx_addsy)
 	bufp[0] |= val & 0x1F;
       break;
 
     case BFD_RELOC_CRIS_SIGNED_6:
       if (val > 31 || val < -32)
-	as_bad (_("Value not in 6 bit range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 6 bit range: %ld"), val);
       if (! fixP->fx_addsy)
 	bufp[0] |= val & 0x3F;
       break;
 
     case BFD_RELOC_CRIS_UNSIGNED_6:
       if (val > 63 || val < 0)
-	as_bad (_("Value not in 6 bit unsigned range: %ld"), val);
+	as_bad_where (fixP->fx_file, fixP->fx_line,
+		      _("Value not in 6 bit unsigned range: %ld"), val);
       if (! fixP->fx_addsy)
 	bufp[0] |= val & 0x3F;
       break;
@@ -2969,9 +3733,7 @@ cris_number_to_imm (bufp, val, n, fixP, seg)
    GAS does not understand.  */
 
 int
-md_parse_option (arg, argp)
-     int arg;
-     char *argp ATTRIBUTE_UNUSED;
+md_parse_option (int arg, char *argp ATTRIBUTE_UNUSED)
 {
   switch (arg)
     {
@@ -2983,7 +3745,7 @@ md_parse_option (arg, argp)
 
     case 'N':
       warn_for_branch_expansion = 1;
-      return 1;
+      break;
 
     case OPTION_NO_US:
       demand_register_prefix = TRUE;
@@ -2992,35 +3754,64 @@ md_parse_option (arg, argp)
 	as_bad (_("--no-underscore is invalid with a.out format"));
       else
 	symbols_have_leading_underscore = FALSE;
-      return 1;
+      break;
 
     case OPTION_US:
       demand_register_prefix = FALSE;
       symbols_have_leading_underscore = TRUE;
-      return 1;
+      break;
 
     case OPTION_PIC:
       pic = TRUE;
-      return 1;
+      if (cris_arch != arch_crisv32)
+	md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
+      else
+	md_long_jump_size = crisv32_long_jump_size;
+      break;
+
+    case OPTION_ARCH:
+      {
+	char *str = argp;
+	enum cris_archs argarch = cris_arch_from_string (&str);
+
+	if (argarch == arch_cris_unknown)
+	    as_bad (_("invalid <arch> in --march=<arch>: %s"), argp);
+	else
+	  cris_arch = argarch;
+
+	if (argarch == arch_crisv32)
+	  {
+	    err_for_dangerous_mul_placement = 0;
+	    md_long_jump_size = crisv32_long_jump_size;
+	  }
+	else
+	  {
+	    if (pic)
+	      md_long_jump_size = cris_any_v0_v10_long_jump_size_pic;
+	    else
+	      md_long_jump_size = cris_any_v0_v10_long_jump_size;
+	  }
+      }
+      break;
 
     case OPTION_MULBUG_ABORT_OFF:
       err_for_dangerous_mul_placement = 0;
-      return 1;
+      break;
 
     case OPTION_MULBUG_ABORT_ON:
       err_for_dangerous_mul_placement = 1;
-      return 1;
+      break;
 
     default:
       return 0;
     }
+
+  return 1;
 }
 
 /* Round up a section size to the appropriate boundary.  */
 valueT
-md_section_align (segment, size)
-     segT segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   /* Round all sects to multiple of 4, except the bss section, which
      we'll round to word-size.
@@ -3048,15 +3839,21 @@ md_section_align (segment, size)
 
 /* Generate a machine-dependent relocation.  */
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
 {
   arelent *relP;
   bfd_reloc_code_real_type code;
 
   switch (fixP->fx_r_type)
     {
+    case BFD_RELOC_CRIS_SIGNED_8:
+      code = BFD_RELOC_8;
+      break;
+
+    case BFD_RELOC_CRIS_SIGNED_16:
+      code = BFD_RELOC_16;
+      break;
+
     case BFD_RELOC_CRIS_16_GOT:
     case BFD_RELOC_CRIS_32_GOT:
     case BFD_RELOC_CRIS_16_GOTPLT:
@@ -3065,10 +3862,14 @@ tc_gen_reloc (section, fixP)
     case BFD_RELOC_CRIS_32_PLT_GOTREL:
     case BFD_RELOC_CRIS_32_PLT_PCREL:
     case BFD_RELOC_32:
+    case BFD_RELOC_32_PCREL:
     case BFD_RELOC_16:
     case BFD_RELOC_8:
     case BFD_RELOC_VTABLE_INHERIT:
     case BFD_RELOC_VTABLE_ENTRY:
+    case BFD_RELOC_CRIS_UNSIGNED_8:
+    case BFD_RELOC_CRIS_UNSIGNED_16:
+    case BFD_RELOC_CRIS_LAPCQ_OFFSET:
       code = fixP->fx_r_type;
       break;
     default:
@@ -3083,10 +3884,7 @@ tc_gen_reloc (section, fixP)
   *relP->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   relP->address = fixP->fx_frag->fr_address + fixP->fx_where;
 
-  if (fixP->fx_pcrel)
-    relP->addend = 0;
-  else
-    relP->addend = fixP->fx_offset;
+  relP->addend = fixP->fx_offset;
 
   /* This is the standard place for KLUDGEs to work around bugs in
      bfd_install_relocation (first such note in the documentation
@@ -3135,8 +3933,7 @@ tc_gen_reloc (section, fixP)
 /* Machine-dependent usage-output.  */
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   /* The messages are formatted to line up with the generic options.  */
   fprintf (stream, _("CRIS-specific options:\n"));
@@ -3154,16 +3951,16 @@ md_show_usage (stream)
 	   _("                          Registers will require a `$'-prefix.\n"));
   fprintf (stream, "%s",
 	   _("  --pic			Enable generation of position-independent code.\n"));
+  fprintf (stream, "%s",
+	   _("  --march=<arch>		Generate code for <arch>.  Valid choices for <arch>\n\
+				are v0_v10, v10, v32 and common_v10_v32.\n"));
 }
 
 /* Apply a fixS (fixup of an instruction or data that we didn't have
    enough info to complete immediately) to the data in a frag.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
 {
   /* This assignment truncates upper bits if valueT is 64 bits (as with
      --enable-64-bit-bfd), which is fine here, though we cast to avoid
@@ -3186,6 +3983,9 @@ md_apply_fix3 (fixP, valP, seg)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
 		      _("expression too complex"));
 
+      /* This operand-type is scaled.  */
+      if (fixP->fx_r_type == BFD_RELOC_CRIS_LAPCQ_OFFSET)
+	val /= 2;
       cris_number_to_imm (buf, val, fixP->fx_size, fixP, seg);
     }
 }
@@ -3194,8 +3994,7 @@ md_apply_fix3 (fixP, valP, seg)
    the address of the fixup plus its size.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
 
@@ -3208,7 +4007,8 @@ md_pcrel_from (fixP)
   if (OUTPUT_FLAVOR != bfd_target_elf_flavour
       || (fixP->fx_r_type != BFD_RELOC_8_PCREL
 	  && fixP->fx_r_type != BFD_RELOC_16_PCREL
-	  && fixP->fx_r_type != BFD_RELOC_32_PCREL))
+	  && fixP->fx_r_type != BFD_RELOC_32_PCREL
+	  && fixP->fx_r_type != BFD_RELOC_CRIS_LAPCQ_OFFSET))
     as_bad_where (fixP->fx_file, fixP->fx_line,
 		  _("Invalid pc-relative relocation"));
   return fixP->fx_size + addr;
@@ -3216,8 +4016,7 @@ md_pcrel_from (fixP)
 
 /* We have no need to give defaults for symbol-values.  */
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -3227,8 +4026,7 @@ md_undefined_symbol (name)
    against section symbols, and guarantees that a relocation will be
    emitted even when the value can be resolved locally.  */
 int
-md_cris_force_relocation (fixp)
-     struct fix *fixp;
+md_cris_force_relocation (struct fix *fixp)
 {
   switch (fixp->fx_r_type)
     {
@@ -3252,9 +4050,7 @@ md_cris_force_relocation (fixp)
    knows about how to handle broken words.  */
 
 void
-tc_cris_check_adjusted_broken_word (new_offset, brokwP)
-     offsetT new_offset;
-     struct broken_word *brokwP;
+tc_cris_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
 {
   if (new_offset > 32767 || new_offset < -32768)
     /* We really want a genuine error, not a warning, so make it one.  */
@@ -3265,21 +4061,24 @@ tc_cris_check_adjusted_broken_word (new_offset, brokwP)
 
 /* Make a leading REGISTER_PREFIX_CHAR mandatory for all registers.  */
 
-static void cris_force_reg_prefix ()
+static void
+cris_force_reg_prefix (void)
 {
   demand_register_prefix = TRUE;
 }
 
 /* Do not demand a leading REGISTER_PREFIX_CHAR for all registers.  */
 
-static void cris_relax_reg_prefix ()
+static void
+cris_relax_reg_prefix (void)
 {
   demand_register_prefix = FALSE;
 }
 
 /* Adjust for having a leading '_' on all user symbols.  */
 
-static void cris_sym_leading_underscore ()
+static void
+cris_sym_leading_underscore (void)
 {
   /* We can't really do anything more than assert that what the program
      thinks symbol starts with agrees with the command-line options, since
@@ -3292,7 +4091,7 @@ static void cris_sym_leading_underscore ()
 
 /* Adjust for not having any particular prefix on user symbols.  */
 
-static void cris_sym_no_leading_underscore ()
+static void cris_sym_no_leading_underscore (void)
 {
   if (symbols_have_leading_underscore)
     as_bad (_(".syntax %s requires command-line option `--no-underscore'"),
@@ -3303,13 +4102,12 @@ static void cris_sym_no_leading_underscore ()
    syntax the assembly code has.  */
 
 static void
-s_syntax (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_syntax (int ignore ATTRIBUTE_UNUSED)
 {
   static const struct syntaxes
   {
-    const char *operand;
-    void (*fn) PARAMS ((void));
+    const char *const operand;
+    void (*fn) (void);
   } syntax_table[] =
     {{SYNTAX_ENFORCE_REG_PREFIX, cris_force_reg_prefix},
      {SYNTAX_RELAX_REG_PREFIX, cris_relax_reg_prefix},
@@ -3340,8 +4138,7 @@ s_syntax (ignore)
    not emitting ELF.  */
 
 static void
-s_cris_file (dummy)
-     int dummy;
+s_cris_file (int dummy)
 {
   if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
     as_bad (_("Pseudodirective .file is only valid when generating ELF"));
@@ -3353,8 +4150,7 @@ s_cris_file (dummy)
    emitting ELF.  */
 
 static void
-s_cris_loc (dummy)
-     int dummy;
+s_cris_loc (int dummy)
 {
   if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
     as_bad (_("Pseudodirective .loc is only valid when generating ELF"));
@@ -3362,6 +4158,160 @@ s_cris_loc (dummy)
     dwarf2_directive_loc (dummy);
 }
 
+/* Translate a <arch> string (as common to --march=<arch> and .arch <arch>)
+   into an enum.  If the string *STR is recognized, *STR is updated to point
+   to the end of the string.  If the string is not recognized,
+   arch_cris_unknown is returned.  */
+
+static enum cris_archs
+cris_arch_from_string (char **str)
+{
+  static const struct cris_arch_struct
+  {
+    const char *const name;
+    enum cris_archs arch;
+  } arch_table[] =
+      /* Keep in order longest-first for choices where one is a prefix
+	 of another.  */
+    {{"v0_v10", arch_cris_any_v0_v10},
+     {"v10", arch_crisv10},
+     {"v32", arch_crisv32},
+     {"common_v10_v32", arch_cris_common_v10_v32}};
+
+  const struct cris_arch_struct *ap;
+
+  for (ap = arch_table;
+       ap < arch_table + sizeof (arch_table) / sizeof (arch_table[0]);
+       ap++)
+    {
+      int len = strlen (ap->name);
+
+      if (strncmp (*str, ap->name, len) == 0
+	  && (str[0][len] == 0 || ISSPACE (str[0][len])))
+	{
+	  *str += strlen (ap->name);
+	  return ap->arch;
+	}
+    }
+
+  return arch_cris_unknown;
+}
+
+/* Return nonzero if architecture version ARCH matches version range in
+   IVER.  */
+
+static int
+cris_insn_ver_valid_for_arch (enum cris_insn_version_usage iver,
+			      enum cris_archs arch)
+{
+  switch (arch)
+    {
+    case arch_cris_any_v0_v10:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_warning
+	 || iver == cris_ver_v0_3
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v0_10
+	 || iver == cris_ver_sim_v0_10
+	 || iver == cris_ver_v3_10
+	 || iver == cris_ver_v8
+	 || iver == cris_ver_v8p
+	 || iver == cris_ver_v8_10
+	 || iver == cris_ver_v10
+	 || iver == cris_ver_v10p);
+      
+    case arch_crisv32:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v8p
+	 || iver == cris_ver_v10p
+	 || iver == cris_ver_v32p);
+
+    case arch_cris_common_v10_v32:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v8p
+	 || iver == cris_ver_v10p);
+
+    case arch_crisv0:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v0_3
+	 || iver == cris_ver_v0_10
+	 || iver == cris_ver_sim_v0_10);
+
+    case arch_crisv3:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v0_3
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v0_10
+	 || iver == cris_ver_sim_v0_10
+	 || iver == cris_ver_v3_10);
+
+    case arch_crisv8:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v0_10
+	 || iver == cris_ver_sim_v0_10
+	 || iver == cris_ver_v3_10
+	 || iver == cris_ver_v8
+	 || iver == cris_ver_v8p
+	 || iver == cris_ver_v8_10);
+
+    case arch_crisv10:
+      return
+	(iver == cris_ver_version_all
+	 || iver == cris_ver_v3p
+	 || iver == cris_ver_v0_10
+	 || iver == cris_ver_sim_v0_10
+	 || iver == cris_ver_v3_10
+	 || iver == cris_ver_v8p
+	 || iver == cris_ver_v8_10
+	 || iver == cris_ver_v10
+	 || iver == cris_ver_v10p);
+
+    default:
+      BAD_CASE (arch);
+   }
+}
+
+/* Assert that the .arch ARCHCHOICE1 is compatible with the specified or
+   default --march=<ARCHCHOICE2> option.  */
+
+static void
+s_cris_arch (int dummy ATTRIBUTE_UNUSED)
+{
+  /* Right now we take the easy route and check for sameness.  It's not
+     obvious that allowing e.g. --march=v32 and .arch common_v0_v32
+     would be more useful than confusing, implementation-wise and
+     user-wise.  */
+
+  char *str = input_line_pointer;
+  enum cris_archs arch = cris_arch_from_string (&str);
+
+  if (arch == arch_cris_unknown)
+    {
+      as_bad (_("unknown operand to .arch"));
+
+      /* For this one, str does not reflect the end of the operand,
+	 since there was no matching arch.  Skip it manually; skip
+	 things that can be part of a word (a name).  */
+      while (is_part_of_name (*str))
+	str++;
+    }
+  else if (arch != cris_arch)
+    as_bad (_(".arch <arch> requires a matching --march=... option"));
+
+  input_line_pointer = str;
+  demand_empty_rest_of_line ();
+  return;
+}
+
 /*
  * Local variables:
  * eval: (c-set-style "gnu")
diff --git a/gas/config/tc-cris.h b/gas/config/tc-cris.h
index 9082a6262761..34e6ef8153c5 100644
--- a/gas/config/tc-cris.h
+++ b/gas/config/tc-cris.h
@@ -1,5 +1,6 @@
 /* tc-cris.h -- Header file for tc-cris.c, the CRIS GAS port.
-   Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
 
    Contributed by Axis Communications AB, Lund, Sweden.
    Originally written for GAS 1.38.1 by Mikael Asker.
@@ -19,8 +20,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the
-   Free Software Foundation, 59 Temple Place - Suite 330, Boston,
-   MA 02111-1307, USA.  */
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* See the GAS "internal" document for general documentation on this.
    It is called internals.texi (internals.info when makeinfo:d), but is
@@ -34,11 +35,14 @@
 #define TC_CRIS
 
 /* Multi-target support is always on.  */
-extern const char *cris_target_format PARAMS ((void));
+extern const char *cris_target_format (void);
 #define TARGET_FORMAT cris_target_format ()
 
 #define TARGET_ARCH bfd_arch_cris
 
+extern unsigned int cris_mach (void);
+#define TARGET_MACH (cris_mach ())
+
 #define TARGET_BYTES_BIG_ENDIAN 0
 
 extern const char *md_shortopts;
@@ -65,9 +69,6 @@ extern const char FLT_CHARS[];
 
 #define md_number_to_chars number_to_chars_littleendian
 
-extern const int md_short_jump_size;
-extern const int md_long_jump_size;
-
 /* There's no use having different functions for this; the sizes are the
    same.  Note that we can't #define md_short_jump_size here.  */
 #define md_create_short_jump md_create_long_jump
@@ -75,7 +76,7 @@ extern const int md_long_jump_size;
 extern const struct relax_type md_cris_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_cris_relax_table
 
-long cris_relax_frag PARAMS ((segT, fragS *, long));
+long cris_relax_frag (segT, fragS *, long);
 
 /* GAS only handles relaxations for pc-relative data targeting addresses
    in the same segment, so we have to handle the rest on our own.  */
@@ -86,7 +87,7 @@ long cris_relax_frag PARAMS ((segT, fragS *, long));
   : cris_relax_frag (SEG, FRAGP, STRETCH))
 
 #define TC_FORCE_RELOCATION(FIX) md_cris_force_relocation (FIX)
-extern int md_cris_force_relocation PARAMS ((struct fix *));
+extern int md_cris_force_relocation (struct fix *);
 
 #define IS_CRIS_PIC_RELOC(RTYPE)			\
   ((RTYPE) == BFD_RELOC_CRIS_16_GOT			\
@@ -113,6 +114,13 @@ extern int md_cris_force_relocation PARAMS ((struct fix *));
   && (! IS_CRIS_PIC_RELOC ((FIX)->fx_r_type)		\
       || (FIX)->fx_r_type == BFD_RELOC_CRIS_32_GOTREL))
 
+/* FIXME: This *should* be a redundant definition, as the
+   TC_FORCE_RELOCATION* definitions already told about the cases where
+   we *don't* want the symbol value calculated.  Here we seem to answer
+   the "are you sure" question.  It certainly has very little to do with
+   whether the symbol value is passed to md_apply_fix.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
 /* When we have fixups against constant expressions, we get a GAS-specific
    section symbol at no extra charge for obscure reasons in
    adjust_reloc_syms.  Since ELF outputs section symbols, it gladly
@@ -145,14 +153,13 @@ extern int md_cris_force_relocation PARAMS ((struct fix *));
    it is only for use with WORKING_DOT_WORD and warns about most stuff.
    (still in 2.9.1).  */
 struct broken_word;
-extern void tc_cris_check_adjusted_broken_word PARAMS ((offsetT,
-							struct
-							broken_word *));
+extern void tc_cris_check_adjusted_broken_word (offsetT,
+						struct broken_word *);
 #define TC_CHECK_ADJUSTED_BROKEN_DOT_WORD(new_offset, brokw) \
  tc_cris_check_adjusted_broken_word ((offsetT) (new_offset), brokw)
 
 /* We don't want any implicit alignment, so we do nothing.  */
-#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR)
+#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) do { } while (0)
 
 /* CRIS instructions, with operands and prefixes included, are a multiple
    of two bytes long.  */
diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c
new file mode 100644
index 000000000000..34448cd8dca7
--- /dev/null
+++ b/gas/config/tc-crx.c
@@ -0,0 +1,2051 @@
+/* tc-crx.c -- Assembler code for the CRX CPU core.
+   Copyright 2004 Free Software Foundation, Inc.
+
+   Contributed by Tomer Levi, NSC, Israel.
+   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "dwarf2dbg.h"
+#include "opcode/crx.h"
+#include "elf/crx.h"
+
+/* Word is considered here as a 16-bit unsigned short int.  */
+#define WORD_SHIFT  16
+
+/* Register is 4-bit size.  */
+#define REG_SIZE   4
+
+/* Maximum size of a single instruction (in words).  */
+#define INSN_MAX_SIZE   3
+
+/* Maximum bits which may be set in a `mask16' operand.  */
+#define MAX_REGS_IN_MASK16  8
+
+/* Utility macros for string comparison.  */
+#define streq(a, b)           (strcmp (a, b) == 0)
+#define strneq(a, b, c)       (strncmp (a, b, c) == 0)
+
+/* Assign a number NUM, shifted by SHIFT bytes, into a location
+   pointed by index BYTE of array 'output_opcode'.  */
+#define CRX_PRINT(BYTE, NUM, SHIFT)   output_opcode[BYTE] |= (NUM << SHIFT)
+
+/* Operand errors.  */
+typedef enum
+  {
+    OP_LEGAL = 0,	/* Legal operand.  */
+    OP_OUT_OF_RANGE,	/* Operand not within permitted range.  */
+    OP_NOT_EVEN,	/* Operand is Odd number, should be even.  */
+    OP_ILLEGAL_DISPU4,	/* Operand is not within DISPU4 range.  */
+    OP_ILLEGAL_CST4,	/* Operand is not within CST4 range.  */
+    OP_NOT_UPPER_64KB	/* Operand is not within the upper 64KB 
+			   (0xFFFF0000-0xFFFFFFFF).  */
+  }
+op_err;
+
+/* Opcode mnemonics hash table.  */
+static struct hash_control *crx_inst_hash;
+/* CRX registers hash table.  */
+static struct hash_control *reg_hash;
+/* CRX coprocessor registers hash table.  */
+static struct hash_control *copreg_hash;
+/* Current instruction we're assembling.  */
+const inst *instruction;
+
+/* Global variables.  */
+
+/* Array to hold an instruction encoding.  */
+long output_opcode[2];
+
+/* Nonzero means a relocatable symbol.  */
+int relocatable;
+
+/* A copy of the original instruction (used in error messages).  */
+char ins_parse[MAX_INST_LEN];
+
+/* The current processed argument number.  */
+int cur_arg_num;
+
+/* Generic assembler global variables which must be defined by all targets.  */
+
+/* Characters which always start a comment.  */
+const char comment_chars[] = "#";
+
+/* Characters which start a comment at the beginning of a line.  */
+const char line_comment_chars[] = "#";
+
+/* This array holds machine specific line separator characters.  */
+const char line_separator_chars[] = ";";
+
+/* Chars that can be used to separate mant from exp in floating point nums.  */
+const char EXP_CHARS[] = "eE";
+
+/* Chars that mean this number is a floating point constant as in 0f12.456  */
+const char FLT_CHARS[] = "f'";
+
+/* Target-specific multicharacter options, not const-declared at usage.  */
+const char *md_shortopts = "";
+struct option md_longopts[] =
+{
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* This table describes all the machine specific pseudo-ops
+   the assembler has to support.  The fields are:
+   *** Pseudo-op name without dot.
+   *** Function to call to execute this pseudo-op.
+   *** Integer arg to pass to the function.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* In CRX machine, align is in bytes (not a ptwo boundary).  */
+  {"align", s_align_bytes, 0},
+  {0, 0, 0}
+};
+
+/* CRX relaxation table.  */
+const relax_typeS md_relax_table[] =
+{
+  /* bCC  */
+  {0xfa, -0x100, 2, 1},			/*  8 */
+  {0xfffe, -0x10000, 4, 2},		/* 16 */
+  {0xfffffffe, -0xfffffffe, 6, 0},	/* 32 */
+
+  /* bal  */
+  {0xfffe, -0x10000, 4, 4},		/* 16 */
+  {0xfffffffe, -0xfffffffe, 6, 0},	/* 32 */
+
+  /* cmpbr/bcop  */
+  {0xfe, -0x100, 4, 6},			/*  8 */
+  {0xfffffe, -0x1000000, 6, 0}		/* 24 */
+};
+
+static void    reset_vars	        (char *);
+static reg     get_register	        (char *);
+static copreg  get_copregister	        (char *);
+static argtype get_optype	        (operand_type);
+static int     get_opbits	        (operand_type);
+static int     get_opflags	        (operand_type);
+static int     get_number_of_operands   (void);
+static void    parse_operand	        (char *, ins *);
+static int     gettrap		        (char *);
+static void    handle_LoadStor	        (char *);
+static int     get_cinv_parameters      (char *);
+static long    getconstant		(long, int);
+static op_err  check_range		(long *, int, unsigned int, int);
+static int     getreg_image	        (reg);
+static void    parse_operands	        (ins *, char *);
+static void    parse_insn	        (ins *, char *);
+static void    print_operand	        (int, int, argument *);
+static void    print_constant	        (int, int, argument *);
+static int     exponent2scale	        (int);
+static void    mask_reg		        (int, unsigned short *);
+static void    process_label_constant   (char *, ins *);
+static void    set_operand	        (char *, ins *);
+static char *  preprocess_reglist       (char *, int *);
+static int     assemble_insn	        (char *, ins *);
+static void    print_insn	        (ins *);
+static void    warn_if_needed		(ins *);
+static int     adjust_if_needed		(ins *);
+
+/* Return the bit size for a given operand.  */
+
+static int
+get_opbits (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return crx_optab[op].bit_size;
+  else
+    return 0;
+}
+
+/* Return the argument type of a given operand.  */
+
+static argtype
+get_optype (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return crx_optab[op].arg_type;
+  else
+    return nullargs;
+}
+
+/* Return the flags of a given operand.  */
+
+static int
+get_opflags (operand_type op)
+{
+  if (op < MAX_OPRD)
+    return crx_optab[op].flags;
+  else
+    return 0;
+}
+
+/* Get the core processor register 'reg_name'.  */
+
+static reg
+get_register (char *reg_name)
+{
+  const reg_entry *reg;
+
+  reg = (const reg_entry *) hash_find (reg_hash, reg_name);
+
+  if (reg != NULL)
+    return reg->value.reg_val;
+  else
+    return nullregister;
+}
+
+/* Get the coprocessor register 'copreg_name'.  */
+
+static copreg
+get_copregister (char *copreg_name)
+{
+  const reg_entry *copreg;
+
+  copreg = (const reg_entry *) hash_find (copreg_hash, copreg_name);
+
+  if (copreg != NULL)
+    return copreg->value.copreg_val;
+  else
+    return nullcopregister;
+}
+
+/* Round up a section size to the appropriate boundary.  */
+
+valueT
+md_section_align (segT seg, valueT val)
+{
+  /* Round .text section to a multiple of 2.  */
+  if (seg == text_section)
+    return (val + 1) & ~1;
+  return val;
+}
+
+/* Parse an operand that is machine-specific (remove '*').  */
+
+void
+md_operand (expressionS * exp)
+{
+  char c = *input_line_pointer;
+
+  switch (c)
+    {
+    case '*':
+      input_line_pointer++;
+      expression (exp);
+      break;
+    default:
+      break;
+    }
+}
+
+/* Reset global variables before parsing a new instruction.  */
+
+static void
+reset_vars (char *op)
+{
+  cur_arg_num = relocatable = 0;
+  memset (& output_opcode, '\0', sizeof (output_opcode));
+
+  /* Save a copy of the original OP (used in error messages).  */
+  strncpy (ins_parse, op, sizeof ins_parse - 1);
+  ins_parse [sizeof ins_parse - 1] = 0;
+}
+
+/* This macro decides whether a particular reloc is an entry in a
+   switch table.  It is used when relaxing, because the linker needs
+   to know about all such entries so that it can adjust them if
+   necessary.  */
+
+#define SWITCH_TABLE(fix)				  \
+  (   (fix)->fx_addsy != NULL				  \
+   && (fix)->fx_subsy != NULL				  \
+   && S_GET_SEGMENT ((fix)->fx_addsy) ==		  \
+      S_GET_SEGMENT ((fix)->fx_subsy)			  \
+   && S_GET_SEGMENT (fix->fx_addsy) != undefined_section  \
+   && (   (fix)->fx_r_type == BFD_RELOC_CRX_NUM8	  \
+       || (fix)->fx_r_type == BFD_RELOC_CRX_NUM16	  \
+       || (fix)->fx_r_type == BFD_RELOC_CRX_NUM32))
+
+/* See whether we need to force a relocation into the output file.
+   This is used to force out switch and PC relative relocations when
+   relaxing.  */
+
+int
+crx_force_relocation (fixS *fix)
+{
+  if (generic_force_reloc (fix) || SWITCH_TABLE (fix))
+    return 1;
+
+  return 0;
+}
+
+/* Generate a relocation entry for a fixup.  */
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
+{
+  arelent * reloc;
+
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+  reloc->addend = fixP->fx_offset;
+
+  if (fixP->fx_subsy != NULL)
+    {
+      if (SWITCH_TABLE (fixP))
+	{
+	  /* Keep the current difference in the addend.  */
+	  reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
+			   - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
+
+	  switch (fixP->fx_r_type)
+	    {
+	    case BFD_RELOC_CRX_NUM8:
+	      fixP->fx_r_type = BFD_RELOC_CRX_SWITCH8;
+	      break;
+	    case BFD_RELOC_CRX_NUM16:
+	      fixP->fx_r_type = BFD_RELOC_CRX_SWITCH16;
+	      break;
+	    case BFD_RELOC_CRX_NUM32:
+	      fixP->fx_r_type = BFD_RELOC_CRX_SWITCH32;
+	      break;
+	    default:
+	      abort ();
+	      break;
+	    }
+	}
+      else
+	{
+	  /* We only resolve difference expressions in the same section.  */
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("can't resolve `%s' {%s section} - `%s' {%s section}"),
+			fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
+			segment_name (fixP->fx_addsy
+				      ? S_GET_SEGMENT (fixP->fx_addsy)
+				      : absolute_section),
+			S_GET_NAME (fixP->fx_subsy),
+			segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
+	}
+    }
+
+  assert ((int) fixP->fx_r_type > 0);
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
+
+  if (reloc->howto == (reloc_howto_type *) NULL)
+    {
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("internal error: reloc %d (`%s') not supported by object file format"),
+		    fixP->fx_r_type,
+		    bfd_get_reloc_code_name (fixP->fx_r_type));
+      return NULL;
+    }
+  assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+  return reloc;
+}
+
+/* Prepare machine-dependent frags for relaxation.  */
+
+int
+md_estimate_size_before_relax (fragS *fragp, asection *seg)
+{
+  /* If symbol is undefined or located in a different section,
+     select the largest supported relocation.  */
+  relax_substateT subtype;
+  relax_substateT rlx_state[] = {0, 2,
+				 3, 4,
+				 5, 6};
+
+  for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
+    {
+      if (fragp->fr_subtype == rlx_state[subtype]
+	  && (!S_IS_DEFINED (fragp->fr_symbol)
+	      || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+	{
+	  fragp->fr_subtype = rlx_state[subtype + 1];
+	  break;
+	}
+    }
+
+  if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
+    abort ();
+
+  return md_relax_table[fragp->fr_subtype].rlx_length;
+}
+
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
+{
+  /* 'opcode' points to the start of the instruction, whether
+     we need to change the instruction's fixed encoding.  */
+  char *opcode = fragP->fr_literal + fragP->fr_fix;
+  bfd_reloc_code_real_type reloc;
+
+  subseg_change (sec, 0);
+
+  switch (fragP->fr_subtype)
+    {
+    case 0:
+      reloc = BFD_RELOC_CRX_REL8;
+      break;
+    case 1:
+      *opcode = 0x7e;
+      reloc = BFD_RELOC_CRX_REL16;
+      break;
+    case 2:
+      *opcode = 0x7f;
+      reloc = BFD_RELOC_CRX_REL32;
+      break;
+    case 3:
+      reloc = BFD_RELOC_CRX_REL16;
+      break;
+    case 4:
+      *++opcode = 0x31;
+      reloc = BFD_RELOC_CRX_REL32;
+      break;
+    case 5:
+      reloc = BFD_RELOC_CRX_REL8_CMP;
+      break;
+    case 6:
+      *++opcode = 0x31;
+      reloc = BFD_RELOC_CRX_REL24;
+      break;
+    default:
+      abort ();
+      break;
+    }
+
+    fix_new (fragP, fragP->fr_fix,
+	     bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
+	     fragP->fr_symbol, fragP->fr_offset, 1, reloc);
+    fragP->fr_var = 0;
+    fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+/* Process machine-dependent command line options.  Called once for
+   each option on the command line that the machine-independent part of
+   GAS does not understand.  */
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Machine-dependent usage-output.  */
+
+void
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
+{
+  return;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[4];
+  char *t;
+  int i;
+
+  switch (type)
+    {
+    case 'f':
+      prec = 2;
+      break;
+
+    case 'd':
+      prec = 4;
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  if (! target_big_endian)
+    {
+      for (i = prec - 1; i >= 0; i--)
+	{
+	  md_number_to_chars (litP, (valueT) words[i], 2);
+	  litP += 2;
+	}
+    }
+  else
+    {
+      for (i = 0; i < prec; i++)
+	{
+	  md_number_to_chars (litP, (valueT) words[i], 2);
+	  litP += 2;
+	}
+    }
+
+  return NULL;
+}
+
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+   enough info to complete immediately) to the data in a frag.
+   Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
+   relaxation of debug sections, this function is called only when
+   fixuping relocations of debug sections.  */
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+{
+  valueT val = * valP;
+  char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
+  fixP->fx_offset = 0;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_CRX_NUM8:
+      bfd_put_8 (stdoutput, (unsigned char) val, buf);
+      break;
+    case BFD_RELOC_CRX_NUM16:
+      bfd_put_16 (stdoutput, val, buf);
+      break;
+    case BFD_RELOC_CRX_NUM32:
+      bfd_put_32 (stdoutput, val, buf);
+      break;
+    default:
+      /* We shouldn't ever get here because linkrelax is nonzero.  */
+      abort ();
+      break;
+    }
+
+  fixP->fx_done = 0;
+
+  if (fixP->fx_addsy == NULL
+      && fixP->fx_pcrel == 0)
+    fixP->fx_done = 1;
+
+  if (fixP->fx_pcrel == 1
+      && fixP->fx_addsy != NULL
+      && S_GET_SEGMENT (fixP->fx_addsy) == seg)
+    fixP->fx_done = 1;
+}
+
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address + fixp->fx_where;
+}
+
+/* This function is called once, at assembler startup time.  This should
+   set up all the tables, etc that the MD part of the assembler needs.  */
+
+void
+md_begin (void)
+{
+  const char *hashret = NULL;
+  int i = 0;
+
+  /* Set up a hash table for the instructions.  */
+  if ((crx_inst_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+  
+  while (crx_instruction[i].mnemonic != NULL)
+    {
+      const char *mnemonic = crx_instruction[i].mnemonic;
+
+      hashret = hash_insert (crx_inst_hash, mnemonic,
+	(PTR) &crx_instruction[i]);
+
+      if (hashret != NULL && *hashret != '\0')
+	as_fatal (_("Can't hash `%s': %s\n"), crx_instruction[i].mnemonic,
+		  *hashret == 0 ? _("(unknown reason)") : hashret);
+
+      /* Insert unique names into hash table.  The CRX instruction set
+	 has many identical opcode names that have different opcodes based
+	 on the operands.  This hash table then provides a quick index to
+	 the first opcode with a particular name in the opcode table.  */
+      do
+	{
+	  ++i;
+	}
+      while (crx_instruction[i].mnemonic != NULL
+	     && streq (crx_instruction[i].mnemonic, mnemonic));
+    }
+
+  /* Initialize reg_hash hash table.  */
+  if ((reg_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  {
+    const reg_entry *regtab;
+
+    for (regtab = crx_regtab;
+	 regtab < (crx_regtab + NUMREGS); regtab++)
+      {
+	hashret = hash_insert (reg_hash, regtab->name, (PTR) regtab);
+	if (hashret)
+	  as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		    regtab->name,
+		    hashret);
+      }
+  }
+
+  /* Initialize copreg_hash hash table.  */
+  if ((copreg_hash = hash_new ()) == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  {
+    const reg_entry *copregtab;
+
+    for (copregtab = crx_copregtab; copregtab < (crx_copregtab + NUMCOPREGS);
+	 copregtab++)
+      {
+	hashret = hash_insert (copreg_hash, copregtab->name, (PTR) copregtab);
+	if (hashret)
+	  as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		    copregtab->name,
+		    hashret);
+      }
+  }
+  /*  Set linkrelax here to avoid fixups in most sections.  */
+  linkrelax = 1;
+}
+
+/* Process constants (immediate/absolute) 
+   and labels (jump targets/Memory locations).  */
+
+static void
+process_label_constant (char *str, ins * crx_ins)
+{
+  char *saved_input_line_pointer;
+  argument *cur_arg = &crx_ins->arg[cur_arg_num];  /* Current argument.  */
+
+  saved_input_line_pointer = input_line_pointer;
+  input_line_pointer = str;
+
+  expression (&crx_ins->exp);
+  
+  switch (crx_ins->exp.X_op)
+    {
+    case O_big:
+    case O_absent:
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      str);
+      crx_ins->exp.X_op = O_constant;
+      crx_ins->exp.X_add_number = 0;
+      crx_ins->exp.X_add_symbol = (symbolS *) 0;
+      crx_ins->exp.X_op_symbol = (symbolS *) 0;
+      /* Fall through.  */
+
+    case O_constant:
+      cur_arg->X_op = O_constant;
+      cur_arg->constant = crx_ins->exp.X_add_number;
+      break;
+
+    case O_symbol:
+    case O_subtract:
+    case O_add:
+      cur_arg->X_op = O_symbol;
+      crx_ins->rtype = BFD_RELOC_NONE;
+      relocatable = 1;
+
+      switch (cur_arg->type)
+	{
+	case arg_cr:
+          if (IS_INSN_TYPE (LD_STOR_INS_INC))
+	    crx_ins->rtype = BFD_RELOC_CRX_REGREL12;
+          else if (IS_INSN_TYPE (CSTBIT_INS)
+		   || IS_INSN_TYPE (STOR_IMM_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_REGREL28;
+          else
+	    crx_ins->rtype = BFD_RELOC_CRX_REGREL32;
+	  break;
+
+	case arg_idxr:
+	    crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
+	  break;
+	
+	case arg_c:
+          if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_REL16;
+	  else if (IS_INSN_TYPE (BRANCH_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_REL8;
+          else if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (STOR_IMM_INS)
+		   || IS_INSN_TYPE (CSTBIT_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_ABS32;
+	  else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_REL4;
+          else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
+	  break;
+	
+	case arg_ic:
+          if (IS_INSN_TYPE (ARITH_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_IMM32;
+	  else if (IS_INSN_TYPE (ARITH_BYTE_INS))
+	    crx_ins->rtype = BFD_RELOC_CRX_IMM16;
+	  break;
+	default:
+	  break;
+      }
+      break;
+
+    default:
+      cur_arg->X_op = crx_ins->exp.X_op;
+      break;
+    }
+
+  input_line_pointer = saved_input_line_pointer;
+  return;
+}
+
+/* Get the values of the scale to be encoded -
+   used for the scaled index mode of addressing.  */
+
+static int
+exponent2scale (int val)
+{
+  int exponent;
+
+  /* If 'val' is 0, the following 'for' will be an endless loop.  */
+  if (val == 0)
+    return 0;
+
+  for (exponent = 0; (val != 1); val >>= 1, exponent++)
+    ;
+
+  return exponent;
+}
+
+/* Parsing different types of operands
+   -> constants		    Immediate/Absolute/Relative numbers
+   -> Labels		    Relocatable symbols
+   -> (rbase)		    Register base
+   -> disp(rbase)	    Register relative
+   -> disp(rbase)+	    Post-increment mode
+   -> disp(rbase,ridx,scl)  Register index mode  */
+
+static void
+set_operand (char *operand, ins * crx_ins)
+{
+  char *operandS; /* Pointer to start of sub-opearand.  */
+  char *operandE; /* Pointer to end of sub-opearand.  */
+  expressionS scale;
+  int scale_val;
+  char *input_save, c;
+  argument *cur_arg = &crx_ins->arg[cur_arg_num]; /* Current argument.  */
+
+  /* Initialize pointers.  */
+  operandS = operandE = operand;
+
+  switch (cur_arg->type)
+    {
+    case arg_sc:    /* Case *+0x18.  */
+    case arg_ic:    /* Case $0x18.  */
+      operandS++;
+    case arg_c:	    /* Case 0x18.  */
+      /* Set constant.  */
+      process_label_constant (operandS, crx_ins);
+      
+      if (cur_arg->type != arg_ic)
+	cur_arg->type = arg_c;
+      break;
+
+    case arg_icr:   /* Case $0x18(r1).  */
+      operandS++;
+    case arg_cr:    /* Case 0x18(r1).   */
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+	operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, crx_ins);
+      operandS = operandE;    
+    case arg_rbase: /* Case (r1).  */
+      operandS++;
+      /* Set register base.  */
+      while (*operandE != ')')
+	operandE++;
+      *operandE = '\0';
+      if ((cur_arg->r = get_register (operandS)) == nullregister)
+	as_bad (_("Illegal register `%s' in Instruction `%s'"),
+		operandS, ins_parse);
+
+      if (cur_arg->type != arg_rbase)
+	cur_arg->type = arg_cr;
+      break;
+
+    case arg_idxr:
+      /* Set displacement constant.  */
+      while (*operandE != '(')
+	operandE++;
+      *operandE = '\0';
+      process_label_constant (operandS, crx_ins);
+      operandS = ++operandE;
+      
+      /* Set register base.  */
+      while ((*operandE != ',') && (! ISSPACE (*operandE)))
+	operandE++;
+      *operandE++ = '\0';
+      if ((cur_arg->r = get_register (operandS)) == nullregister)
+	as_bad (_("Illegal register `%s' in Instruction `%s'"),
+		operandS, ins_parse);
+
+      /* Skip leading white space.  */
+      while (ISSPACE (*operandE))
+	operandE++;
+      operandS = operandE;
+
+      /* Set register index.  */
+      while ((*operandE != ')') && (*operandE != ','))
+	operandE++;
+      c = *operandE;
+      *operandE++ = '\0';
+
+      if ((cur_arg->i_r = get_register (operandS)) == nullregister)
+	as_bad (_("Illegal register `%s' in Instruction `%s'"),
+		operandS, ins_parse);
+
+      /* Skip leading white space.  */
+      while (ISSPACE (*operandE))
+	operandE++;
+      operandS = operandE;
+
+      /* Set the scale.  */
+      if (c == ')')
+	cur_arg->scale = 0;
+      else
+        {
+	  while (*operandE != ')')
+	    operandE++;
+	  *operandE = '\0';
+
+	  /* Preprocess the scale string.  */
+	  input_save = input_line_pointer;
+	  input_line_pointer = operandS;
+	  expression (&scale);
+	  input_line_pointer = input_save;
+
+	  scale_val = scale.X_add_number;
+
+	  /* Check if the scale value is legal.  */
+          if (scale_val != 1 && scale_val != 2
+              && scale_val != 4 && scale_val != 8)
+	    as_bad (_("Illegal Scale - `%d'"), scale_val);
+
+	  cur_arg->scale = exponent2scale (scale_val);
+        }
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Parse a single operand.
+   operand - Current operand to parse.
+   crx_ins - Current assembled instruction.  */
+
+static void
+parse_operand (char *operand, ins * crx_ins)
+{
+  int ret_val;
+  argument *cur_arg = &crx_ins->arg[cur_arg_num]; /* Current argument.  */
+
+  /* Initialize the type to NULL before parsing.  */
+  cur_arg->type = nullargs;
+
+  /* Check whether this is a general processor register.  */
+  if ((ret_val = get_register (operand)) != nullregister)
+    {
+      cur_arg->type = arg_r;
+      cur_arg->r = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Check whether this is a core [special] coprocessor register.  */
+  if ((ret_val = get_copregister (operand)) != nullcopregister)
+    {
+      cur_arg->type = arg_copr;
+      if (ret_val >= cs0)
+	cur_arg->type = arg_copsr;
+      cur_arg->cr = ret_val;
+      cur_arg->X_op = O_register;
+      return;
+    }
+
+  /* Deal with special characters.  */
+  switch (operand[0])
+    {
+    case '$':
+      if (strchr (operand, '(') != NULL)
+	cur_arg->type = arg_icr;
+      else
+        cur_arg->type = arg_ic;
+      goto set_params;
+      break;
+
+    case '*':
+      cur_arg->type = arg_sc;
+      goto set_params;
+      break;
+
+    case '(':
+      cur_arg->type = arg_rbase;
+      goto set_params;
+      break;
+
+    default:
+	break;
+    }
+      
+  if (strchr (operand, '(') != NULL)
+    {
+      if (strchr (operand, ',') != NULL
+          && (strchr (operand, ',') > strchr (operand, '(')))
+	    cur_arg->type = arg_idxr;
+      else
+	cur_arg->type = arg_cr;
+    }
+  else
+    cur_arg->type = arg_c;
+  goto set_params;
+
+/* Parse an operand according to its type.  */
+set_params:
+  cur_arg->constant = 0;
+  set_operand (operand, crx_ins);
+}
+
+/* Parse the various operands. Each operand is then analyzed to fillup 
+   the fields in the crx_ins data structure.  */
+
+static void
+parse_operands (ins * crx_ins, char *operands)
+{
+  char *operandS;	       /* Operands string.  */
+  char *operandH, *operandT;   /* Single operand head/tail pointers.  */
+  int allocated = 0;	       /* Indicates a new operands string was allocated.  */
+  char *operand[MAX_OPERANDS]; /* Separating the operands.  */
+  int op_num = 0;	       /* Current operand number we are parsing.  */
+  int bracket_flag = 0;	       /* Indicates a bracket '(' was found.  */
+  int sq_bracket_flag = 0;     /* Indicates a square bracket '[' was found.  */
+
+  /* Preprocess the list of registers, if necessary.  */
+  operandS = operandH = operandT = (INST_HAS_REG_LIST) ?
+    preprocess_reglist (operands, &allocated) : operands;
+
+  while (*operandT != '\0')
+    {
+      if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
+        {
+	  *operandT++ = '\0';
+	  operand[op_num++] = strdup (operandH);
+          operandH = operandT;
+          continue;
+        }
+
+      if (*operandT == ' ')
+	as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
+
+      if (*operandT == '(')
+	bracket_flag = 1;
+      else if (*operandT == '[')
+	sq_bracket_flag = 1;
+
+      if (*operandT == ')')
+	{
+	  if (bracket_flag)
+	    bracket_flag = 0;
+	  else
+	    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+	}
+      else if (*operandT == ']')
+	{
+	  if (sq_bracket_flag)
+	    sq_bracket_flag = 0;
+	  else
+	    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+	}
+
+      if (bracket_flag == 1 && *operandT == ')')
+	bracket_flag = 0;
+      else if (sq_bracket_flag == 1 && *operandT == ']')
+	sq_bracket_flag = 0;
+
+      operandT++;
+    }
+
+  /* Adding the last operand.  */
+  operand[op_num++] = strdup (operandH);
+  crx_ins->nargs = op_num;
+
+  /* Verifying correct syntax of operands (all brackets should be closed).  */
+  if (bracket_flag || sq_bracket_flag)
+    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+
+  /* Now we parse each operand separately.  */
+  for (op_num = 0; op_num < crx_ins->nargs; op_num++)
+    {
+      cur_arg_num = op_num;
+      parse_operand (operand[op_num], crx_ins);
+      free (operand[op_num]);
+    }
+
+  if (allocated)
+    free (operandS);
+}
+
+/* Get the trap index in dispatch table, given its name.
+   This routine is used by assembling the 'excp' instruction.  */
+
+static int
+gettrap (char *s)
+{
+  const trap_entry *trap;
+
+  for (trap = crx_traps; trap < (crx_traps + NUMTRAPS); trap++)
+    if (strcasecmp (trap->name, s) == 0)
+      return trap->entry;
+
+  as_bad (_("Unknown exception: `%s'"), s);
+  return 0;
+}
+
+/* Post-Increment instructions, as well as Store-Immediate instructions, are a 
+   sub-group within load/stor instruction groups. 
+   Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to 
+   advance the instruction pointer to the start of that sub-group (that is, up 
+   to the first instruction of that type).
+   Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS.  */
+
+static void
+handle_LoadStor (char *operands)
+{
+  /* Post-Increment instructions precede Store-Immediate instructions in 
+     CRX instruction table, hence they are handled before. 
+     This synchronization should be kept.  */
+
+  /* Assuming Post-Increment insn has the following format :
+     'MNEMONIC DISP(REG)+, REG' (e.g. 'loadw 12(r5)+, r6').
+     LD_STOR_INS_INC are the only store insns containing a plus sign (+).  */
+  if (strstr (operands, ")+") != NULL)
+    {
+      while (! IS_INSN_TYPE (LD_STOR_INS_INC))
+	instruction++;
+      return;
+    }
+
+  /* Assuming Store-Immediate insn has the following format :
+     'MNEMONIC $DISP, ...' (e.g. 'storb $1, 12(r5)').
+     STOR_IMM_INS are the only store insns containing a dollar sign ($).  */
+  if (strstr (operands, "$") != NULL)
+    while (! IS_INSN_TYPE (STOR_IMM_INS))
+      instruction++;
+}
+
+/* Top level module where instruction parsing starts.
+   crx_ins - data structure holds some information.
+   operands - holds the operands part of the whole instruction.  */
+
+static void
+parse_insn (ins *insn, char *operands)
+{
+  int i;
+
+  /* Handle instructions with no operands.  */
+  for (i = 0; no_op_insn[i] != NULL; i++)
+  {
+    if (streq (no_op_insn[i], instruction->mnemonic))
+    {
+      insn->nargs = 0;
+      return;
+    }
+  }
+
+  /* Handle 'excp'/'cinv' instructions.  */
+  if (IS_INSN_MNEMONIC ("excp") || IS_INSN_MNEMONIC ("cinv"))
+    {
+      insn->nargs = 1;
+      insn->arg[0].type = arg_ic;
+      insn->arg[0].constant = IS_INSN_MNEMONIC ("excp") ?
+	gettrap (operands) : get_cinv_parameters (operands);
+      insn->arg[0].X_op = O_constant;
+      return;
+    }
+
+  /* Handle load/stor unique instructions before parsing.  */
+  if (IS_INSN_TYPE (LD_STOR_INS))
+    handle_LoadStor (operands);
+
+  if (operands != NULL)
+    parse_operands (insn, operands);
+}
+
+/* Cinv instruction requires special handling.  */
+
+static int
+get_cinv_parameters (char * operand)
+{
+  char *p = operand;
+  int d_used = 0, i_used = 0, u_used = 0, b_used = 0;
+
+  while (*++p != ']')
+    {
+      if (*p == ',' || *p == ' ')
+	continue;
+
+      if (*p == 'd')
+	d_used = 1;
+      else if (*p == 'i')
+	i_used = 1;
+      else if (*p == 'u')
+	u_used = 1;
+      else if (*p == 'b')
+	b_used = 1;
+      else
+	as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
+    }
+
+  return ((b_used ? 8 : 0)
+	+ (d_used ? 4 : 0)
+	+ (i_used ? 2 : 0)
+	+ (u_used ? 1 : 0));
+}
+
+/* Retrieve the opcode image of a given register.
+   If the register is illegal for the current instruction,
+   issue an error.  */
+
+static int
+getreg_image (reg r)
+{
+  const reg_entry *reg;
+  char *reg_name;
+  int is_procreg = 0; /* Nonzero means argument should be processor reg.  */
+
+  if (((IS_INSN_MNEMONIC ("mtpr")) && (cur_arg_num == 1))
+      || ((IS_INSN_MNEMONIC ("mfpr")) && (cur_arg_num == 0)) )
+    is_procreg = 1;
+
+  /* Check whether the register is in registers table.  */
+  if (r < MAX_REG)
+    reg = &crx_regtab[r];
+  /* Check whether the register is in coprocessor registers table.  */
+  else if (r < MAX_COPREG)
+    reg = &crx_copregtab[r-MAX_REG];
+  /* Register not found.  */
+  else
+    {
+      as_bad (_("Unknown register: `%d'"), r);
+      return 0;
+    }
+
+  reg_name = reg->name;
+
+/* Issue a error message when register is illegal.  */
+#define IMAGE_ERR \
+  as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+	    reg_name, ins_parse);			     \
+  break;
+
+  switch (reg->type)
+  {
+    case CRX_U_REGTYPE:
+      if (is_procreg || (instruction->flags & USER_REG))
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CRX_CFG_REGTYPE:
+      if (is_procreg)
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CRX_R_REGTYPE:
+      if (! is_procreg)
+	return reg->image;
+      else
+	IMAGE_ERR;
+
+    case CRX_C_REGTYPE:
+    case CRX_CS_REGTYPE:
+      return reg->image;
+      break;
+
+    default:
+      IMAGE_ERR;
+  }
+
+  return 0;
+}
+
+/* Routine used to represent integer X using NBITS bits.  */
+
+static long
+getconstant (long x, int nbits)
+{
+  /* The following expression avoids overflow if
+     'nbits' is the number of bits in 'bfd_vma'.  */
+  return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
+}
+
+/* Print a constant value to 'output_opcode':
+   ARG holds the operand's type and value.
+   SHIFT represents the location of the operand to be print into.
+   NBITS determines the size (in bits) of the constant.  */
+
+static void
+print_constant (int nbits, int shift, argument *arg)
+{
+  unsigned long mask = 0;
+
+  long constant = getconstant (arg->constant, nbits);
+
+  switch (nbits)
+  {
+    case 32:
+    case 28:
+    case 24:
+    case 22:
+      /* mask the upper part of the constant, that is, the bits
+	 going to the lowest byte of output_opcode[0].
+	 The upper part of output_opcode[1] is always filled,
+	 therefore it is always masked with 0xFFFF.  */
+      mask = (1 << (nbits - 16)) - 1;
+      /* Divide the constant between two consecutive words :
+		 0	   1	     2	       3
+	    +---------+---------+---------+---------+
+	    |	      | X X X X | X X X X |	    |
+	    +---------+---------+---------+---------+
+	      output_opcode[0]    output_opcode[1]     */
+
+      CRX_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
+      CRX_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
+      break;
+
+    case 16:
+    case 12:
+      /* Special case - in arg_cr, the SHIFT represents the location
+	 of the REGISTER, not the constant, which is itself not shifted.  */
+      if (arg->type == arg_cr)
+	{
+	  CRX_PRINT (0, constant,  0);
+	  break;
+	}
+
+      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 
+	 always filling the upper part of output_opcode[1]. If we mistakenly 
+	 write it to output_opcode[0], the constant prefix (that is, 'match')
+	 will be overriden.
+		 0	   1	     2	       3
+	    +---------+---------+---------+---------+
+	    | 'match' |         | X X X X |	    |
+	    +---------+---------+---------+---------+
+	      output_opcode[0]    output_opcode[1]     */
+
+      if ((instruction->size > 2) && (shift == WORD_SHIFT))
+	CRX_PRINT (1, constant, WORD_SHIFT);
+      else
+	CRX_PRINT (0, constant, shift);
+      break;
+
+    default:
+      CRX_PRINT (0, constant,  shift);
+      break;
+  }
+}
+
+/* Print an operand to 'output_opcode', which later on will be
+   printed to the object file:
+   ARG holds the operand's type, size and value.
+   SHIFT represents the printing location of operand.
+   NBITS determines the size (in bits) of a constant operand.  */
+
+static void
+print_operand (int nbits, int shift, argument *arg)
+{
+  switch (arg->type)
+    {
+    case arg_r:
+      CRX_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_copr:
+      if (arg->cr < c0 || arg->cr > c15)
+	as_bad (_("Illegal Co-processor register in Instruction `%s' "),
+		ins_parse);
+      CRX_PRINT (0, getreg_image (arg->cr), shift);
+      break;
+
+    case arg_copsr:
+      if (arg->cr < cs0 || arg->cr > cs15)
+	as_bad (_("Illegal Co-processor special register in Instruction `%s' "),
+		ins_parse);
+      CRX_PRINT (0, getreg_image (arg->cr), shift);
+      break;
+
+    case arg_idxr:
+      /*    16      12	      8    6         0
+	    +--------------------------------+
+	    | r_base | r_idx  | scl|  disp   |
+	    +--------------------------------+	  */
+      CRX_PRINT (0, getreg_image (arg->r), 12);
+      CRX_PRINT (0, getreg_image (arg->i_r), 8);
+      CRX_PRINT (0, arg->scale, 6);
+    case arg_ic:
+    case arg_c:
+      print_constant (nbits, shift, arg);
+      break;
+
+    case arg_rbase:
+      CRX_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    case arg_cr:
+      /* case base_cst4.  */
+      if (instruction->flags & DISPU4MAP)
+	print_constant (nbits, shift + REG_SIZE, arg);
+      else
+	/* rbase_disps<NN> and other such cases.  */
+	print_constant (nbits, shift, arg);
+      /* Add the register argument to the output_opcode.  */
+      CRX_PRINT (0, getreg_image (arg->r), shift);
+      break;
+
+    default:
+      break;
+    }
+}
+
+/* Retrieve the number of operands for the current assembled instruction.  */
+
+static int
+get_number_of_operands (void)
+{
+  int i;
+
+  for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
+    ;
+  return i;
+}
+
+/* Verify that the number NUM can be represented in BITS bits (that is, 
+   within its permitted range), based on the instruction's FLAGS.  
+   If UPDATE is nonzero, update the value of NUM if necessary.
+   Return OP_LEGAL upon success, actual error type upon failure.  */
+
+static op_err
+check_range (long *num, int bits, int unsigned flags, int update)
+{
+  long min, max;
+  int retval = OP_LEGAL;
+  int bin;
+  long upper_64kb = 0xFFFF0000;
+  long value = *num;
+
+  /* For hosts witah longs bigger than 32-bits make sure that the top 
+     bits of a 32-bit negative value read in by the parser are set,
+     so that the correct comparisons are made.  */
+  if (value & 0x80000000)
+    value |= (-1L << 31);
+
+  /* Verify operand value is even.  */
+  if (flags & OP_EVEN)
+    {
+      if (value % 2)
+	return OP_NOT_EVEN;
+    }
+
+  if (flags & OP_UPPER_64KB)
+    {
+      /* Check if value is to be mapped to upper 64 KB memory area.  */
+      if ((value & upper_64kb) == upper_64kb)
+	{
+	  value -= upper_64kb;
+	  if (update)
+	    *num = value;
+	}
+      else
+	return OP_NOT_UPPER_64KB;
+    }
+
+  if (flags & OP_SHIFT)
+    {
+      value >>= 1;
+      if (update)
+	*num = value;
+    }
+  else if (flags & OP_SHIFT_DEC)
+    {
+      value = (value >> 1) - 1;
+      if (update)
+	*num = value;
+    }
+
+  if (flags & OP_ESC)
+    {
+      /* 0x7e and 0x7f are reserved escape sequences of dispe9.  */
+      if (value == 0x7e || value == 0x7f)
+	return OP_OUT_OF_RANGE;
+    }
+
+  if (flags & OP_DISPU4)
+    {
+      int is_dispu4 = 0;
+
+      int mul = (instruction->flags & DISPUB4) ? 1 
+		: (instruction->flags & DISPUW4) ? 2
+		: (instruction->flags & DISPUD4) ? 4 : 0;
+      
+      for (bin = 0; bin < cst4_maps; bin++)
+	{
+	  if (value == (mul * bin))
+	    {
+	      is_dispu4 = 1;
+	      if (update)
+		*num = bin;
+	      break;
+	    }
+	}
+      if (!is_dispu4)
+	retval = OP_ILLEGAL_DISPU4;
+    }
+  else if (flags & OP_CST4)
+    {
+      int is_cst4 = 0;
+
+      for (bin = 0; bin < cst4_maps; bin++)
+	{
+	  if (value == cst4_map[bin])
+	    {
+	      is_cst4 = 1;
+	      if (update)
+		*num = bin;
+	      break;
+	    }
+	}
+      if (!is_cst4)
+	retval = OP_ILLEGAL_CST4;
+    }
+  else if (flags & OP_SIGNED)
+    {
+      max = (1 << (bits - 1)) - 1;
+      min = - (1 << (bits - 1));
+      if ((value > max) || (value < min))
+	retval = OP_OUT_OF_RANGE;
+    }
+  else if (flags & OP_UNSIGNED)
+    {
+      max = ((((1 << (bits - 1)) - 1) << 1) | 1);
+      min = 0;
+      if (((unsigned long) value > (unsigned long) max) 
+	    || ((unsigned long) value < (unsigned long) min))
+	retval = OP_OUT_OF_RANGE;
+    }
+  return retval;
+}
+
+/* Assemble a single instruction:
+   INSN is already parsed (that is, all operand values and types are set).
+   For instruction to be assembled, we need to find an appropriate template in 
+   the instruction table, meeting the following conditions:
+    1: Has the same number of operands.
+    2: Has the same operand types.
+    3: Each operand size is sufficient to represent the instruction's values.
+   Returns 1 upon success, 0 upon failure.  */
+
+static int
+assemble_insn (char *mnemonic, ins *insn)
+{
+  /* Type of each operand in the current template.  */
+  argtype cur_type[MAX_OPERANDS];
+  /* Size (in bits) of each operand in the current template.  */
+  unsigned int cur_size[MAX_OPERANDS];
+  /* Flags of each operand in the current template.  */
+  unsigned int cur_flags[MAX_OPERANDS];
+  /* Instruction type to match.  */
+  unsigned int ins_type;
+  /* Boolean flag to mark whether a match was found.  */
+  int match = 0;
+  int i;
+  /* Nonzero if an instruction with same number of operands was found.  */
+  int found_same_number_of_operands = 0;
+  /* Nonzero if an instruction with same argument types was found.  */
+  int found_same_argument_types = 0;
+  /* Nonzero if a constant was found within the required range.  */
+  int found_const_within_range  = 0;
+  /* Argument number of an operand with invalid type.  */
+  int invalid_optype = -1;
+  /* Argument number of an operand with invalid constant value.  */
+  int invalid_const  = -1;
+  /* Operand error (used for issuing various constant error messages).  */
+  op_err op_error, const_err = OP_LEGAL;
+
+/* Retrieve data (based on FUNC) for each operand of a given instruction.  */
+#define GET_CURRENT_DATA(FUNC, ARRAY)				  \
+  for (i = 0; i < insn->nargs; i++)				  \
+    ARRAY[i] = FUNC (instruction->operands[i].op_type)
+
+#define GET_CURRENT_TYPE    GET_CURRENT_DATA(get_optype, cur_type)
+#define GET_CURRENT_SIZE    GET_CURRENT_DATA(get_opbits, cur_size)
+#define GET_CURRENT_FLAGS   GET_CURRENT_DATA(get_opflags, cur_flags)
+
+  /* Instruction has no operands -> only copy the constant opcode.   */
+  if (insn->nargs == 0)
+    {
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+      return 1;
+    }
+
+  /* In some case, same mnemonic can appear with different instruction types.
+     For example, 'storb' is supported with 3 different types :
+     LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
+     We assume that when reaching this point, the instruction type was 
+     pre-determined. We need to make sure that the type stays the same
+     during a search for matching instruction.  */
+  ins_type = CRX_INS_TYPE(instruction->flags);
+
+  while (/* Check that match is still not found.  */
+	 match != 1
+	 /* Check we didn't get to end of table.  */
+	 && instruction->mnemonic != NULL
+	 /* Check that the actual mnemonic is still available.  */
+	 && IS_INSN_MNEMONIC (mnemonic)
+	 /* Check that the instruction type wasn't changed.  */
+	 && IS_INSN_TYPE(ins_type))
+    {
+      /* Check whether number of arguments is legal.  */
+      if (get_number_of_operands () != insn->nargs)
+	goto next_insn;
+      found_same_number_of_operands = 1;
+
+      /* Initialize arrays with data of each operand in current template.  */
+      GET_CURRENT_TYPE;
+      GET_CURRENT_SIZE;
+      GET_CURRENT_FLAGS;
+
+      /* Check for type compatibility.  */
+      for (i = 0; i < insn->nargs; i++)
+        {
+	  if (cur_type[i] != insn->arg[i].type)
+	    {
+	      if (invalid_optype == -1)
+		invalid_optype = i + 1;
+	      goto next_insn;
+	    }
+	}
+      found_same_argument_types = 1;
+
+      for (i = 0; i < insn->nargs; i++)
+	{
+	  /* Reverse the operand indices for certain opcodes:
+	     Index 0	  -->> 1
+	     Index 1	  -->> 0	
+	     Other index  -->> stays the same.  */
+	  int j = instruction->flags & REVERSE_MATCH ? 
+		  i == 0 ? 1 : 
+		  i == 1 ? 0 : i : 
+		  i;
+
+	  /* Only check range - don't update the constant's value, since the 
+	     current instruction may not be the last we try to match.  
+	     The constant's value will be updated later, right before printing 
+	     it to the object file.  */
+  	  if ((insn->arg[j].X_op == O_constant) 
+	       && (op_error = check_range (&insn->arg[j].constant, cur_size[j], 
+					   cur_flags[j], 0)))
+  	    {
+	      if (invalid_const == -1)
+	      {
+		invalid_const = j + 1;
+		const_err = op_error;
+	      }
+	      goto next_insn;
+	    }
+	  /* For symbols, we make sure the relocation size (which was already 
+	     determined) is sufficient.  */
+	  else if ((insn->arg[j].X_op == O_symbol)
+		    && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize 
+			 > cur_size[j]))
+		  goto next_insn;
+	}
+      found_const_within_range = 1;
+
+      /* If we got till here -> Full match is found.  */
+      match = 1;
+      break;
+
+/* Try again with next instruction.  */
+next_insn:
+      instruction++;
+    }
+
+  if (!match)
+    {
+      /* We haven't found a match - instruction can't be assembled.  */
+      if (!found_same_number_of_operands)
+	as_bad (_("Incorrect number of operands"));
+      else if (!found_same_argument_types)
+	as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
+      else if (!found_const_within_range)
+      {
+	switch (const_err)
+	{
+	case OP_OUT_OF_RANGE:
+	  as_bad (_("Operand out of range (arg %d)"), invalid_const);
+	  break;
+	case OP_NOT_EVEN:
+	  as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
+	  break;
+	case OP_ILLEGAL_DISPU4:
+	  as_bad (_("Invalid DISPU4 operand value (arg %d)"), invalid_const);
+	  break;
+	case OP_ILLEGAL_CST4:
+	  as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
+	  break;
+	case OP_NOT_UPPER_64KB:
+	  as_bad (_("Operand value is not within upper 64 KB (arg %d)"), 
+		    invalid_const);
+	  break;
+	default:
+	  as_bad (_("Illegal operand (arg %d)"), invalid_const);
+	  break;
+	}
+      }
+      
+      return 0;
+    }
+  else
+    /* Full match - print the encoding to output file.  */
+    {
+      /* Make further checkings (such that couldn't be made earlier).
+	 Warn the user if necessary.  */
+      warn_if_needed (insn);
+      
+      /* Check whether we need to adjust the instruction pointer.  */
+      if (adjust_if_needed (insn))
+	/* If instruction pointer was adjusted, we need to update 
+	   the size of the current template operands.  */
+	GET_CURRENT_SIZE;
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+	  int j = instruction->flags & REVERSE_MATCH ? 
+		  i == 0 ? 1 : 
+		  i == 1 ? 0 : i : 
+		  i;
+
+	  /* This time, update constant value before printing it.  */
+  	  if ((insn->arg[j].X_op == O_constant) 
+	       && (check_range (&insn->arg[j].constant, cur_size[j], 
+				cur_flags[j], 1) != OP_LEGAL))
+	      as_fatal (_("Illegal operand (arg %d)"), j+1);
+	}
+
+      /* First, copy the instruction's opcode.  */
+      output_opcode[0] = BIN (instruction->match, instruction->match_bits);
+
+      for (i = 0; i < insn->nargs; i++)
+        {
+	  cur_arg_num = i;
+          print_operand (cur_size[i], instruction->operands[i].shift, 
+			 &insn->arg[i]);
+        }
+    }
+
+  return 1;
+}
+
+/* Bunch of error checkings.
+   The checks are made after a matching instruction was found.  */
+
+void
+warn_if_needed (ins *insn)
+{
+  /* If the post-increment address mode is used and the load/store 
+     source register is the same as rbase, the result of the 
+     instruction is undefined.  */
+  if (IS_INSN_TYPE (LD_STOR_INS_INC))
+    {
+      /* Enough to verify that one of the arguments is a simple reg.  */
+      if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
+	if (insn->arg[0].r == insn->arg[1].r)
+	  as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), 
+		   insn->arg[0].r);
+    }
+
+  /* Some instruction assume the stack pointer as rptr operand.
+     Issue an error when the register to be loaded is also SP.  */
+  if (instruction->flags & NO_SP)
+    {
+      if (getreg_image (insn->arg[0].r) == getreg_image (sp))
+	as_bad (_("`%s' has undefined result"), ins_parse);
+    }
+
+  /* If the rptr register is specified as one of the registers to be loaded, 
+     the final contents of rptr are undefined. Thus, we issue an error.  */
+  if (instruction->flags & NO_RPTR)
+    {
+      if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
+	as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), 
+	 getreg_image (insn->arg[0].r));
+    }
+}
+
+/* In some cases, we need to adjust the instruction pointer although a 
+   match was already found. Here, we gather all these cases.
+   Returns 1 if instruction pointer was adjusted, otherwise 0.  */
+
+int
+adjust_if_needed (ins *insn)
+{
+  int ret_value = 0;
+
+  /* Special check for 'addub $0, r0' instruction -
+     The opcode '0000 0000 0000 0000' is not allowed.  */
+  if (IS_INSN_MNEMONIC ("addub"))
+    {
+      if ((instruction->operands[0].op_type == cst4)
+	  && instruction->operands[1].op_type == regr)
+        {
+          if (insn->arg[0].constant == 0 && insn->arg[1].r == r0)
+	    {
+	      instruction++;
+	      ret_value = 1;
+	    }
+        }
+    }
+
+  /* Optimization: Omit a zero displacement in bit operations, 
+     saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)').  */
+  if (IS_INSN_TYPE (CSTBIT_INS))
+    {
+      if ((instruction->operands[1].op_type == rbase_disps12)
+	   && (insn->arg[1].X_op == O_constant)
+	   && (insn->arg[1].constant == 0))
+            {
+              instruction--;
+	      ret_value = 1;
+            }
+    }
+
+  return ret_value;
+}
+
+/* Set the appropriate bit for register 'r' in 'mask'.
+   This indicates that this register is loaded or stored by
+   the instruction.  */
+
+static void
+mask_reg (int r, unsigned short int *mask)
+{
+  if ((reg)r > (reg)sp)
+    {
+      as_bad (_("Invalid Register in Register List"));
+      return;
+    }
+
+  *mask |= (1 << r);
+}
+
+/* Preprocess register list - create a 16-bit mask with one bit for each
+   of the 16 general purpose registers. If a bit is set, it indicates
+   that this register is loaded or stored by the instruction.  */
+
+static char *
+preprocess_reglist (char *param, int *allocated)
+{
+  char reg_name[MAX_REGNAME_LEN]; /* Current parsed register name.  */
+  char *regP;			  /* Pointer to 'reg_name' string.  */
+  int reg_counter = 0;		  /* Count number of parsed registers.  */
+  unsigned short int mask = 0;	  /* Mask for 16 general purpose registers.  */
+  char *new_param;		  /* New created operands string.  */
+  char *paramP = param;		  /* Pointer to original opearands string.  */
+  char maskstring[10];		  /* Array to print the mask as a string.  */
+  int hi_found = 0, lo_found = 0; /* Boolean flags for hi/lo registers.  */
+  reg r;
+  copreg cr;
+
+  /* If 'param' is already in form of a number, no need to preprocess.  */
+  if (strchr (paramP, '{') == NULL)
+    return param;
+
+  /* Verifying correct syntax of operand.  */
+  if (strchr (paramP, '}') == NULL)
+    as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
+
+  while (*paramP++ != '{');
+
+  new_param = (char *)xcalloc (MAX_INST_LEN, sizeof (char));
+  *allocated = 1;
+  strncpy (new_param, param, paramP - param - 1);
+
+  while (*paramP != '}')
+    {
+      regP = paramP;
+      memset (&reg_name, '\0', sizeof (reg_name));
+
+      while (ISALNUM (*paramP))
+	paramP++;
+
+      strncpy (reg_name, regP, paramP - regP);
+
+      /* Coprocessor register c<N>.  */
+      if (IS_INSN_TYPE (COP_REG_INS))
+        {
+          if (((cr = get_copregister (reg_name)) == nullcopregister)
+	      || (crx_copregtab[cr-MAX_REG].type != CRX_C_REGTYPE))
+	    as_fatal (_("Illegal register `%s' in cop-register list"), reg_name);
+	  mask_reg (getreg_image (cr - c0), &mask);
+        }
+      /* Coprocessor Special register cs<N>.  */
+      else if (IS_INSN_TYPE (COPS_REG_INS))
+        {
+          if (((cr = get_copregister (reg_name)) == nullcopregister)
+	      || (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
+	    as_fatal (_("Illegal register `%s' in cop-special-register list"), 
+		      reg_name);
+	  mask_reg (getreg_image (cr - cs0), &mask);
+        }
+      /* User register u<N>.  */
+      else if (instruction->flags & USER_REG)
+	{
+	  if (streq(reg_name, "uhi"))
+	    {
+	      hi_found = 1;
+	      goto next_inst;
+	    }
+	  else if (streq(reg_name, "ulo"))
+	    {
+	      lo_found = 1;
+	      goto next_inst;
+	    }
+          else if (((r = get_register (reg_name)) == nullregister)
+	      || (crx_regtab[r].type != CRX_U_REGTYPE))
+	    as_fatal (_("Illegal register `%s' in user register list"), reg_name);
+	  
+	  mask_reg (getreg_image (r - u0), &mask);	  
+	}
+      /* General purpose register r<N>.  */
+      else
+        {
+	  if (streq(reg_name, "hi"))
+	    {
+	      hi_found = 1;
+	      goto next_inst;
+	    }
+	  else if (streq(reg_name, "lo"))
+	    {
+	      lo_found = 1;
+	      goto next_inst;
+	    }
+          else if (((r = get_register (reg_name)) == nullregister)
+	      || (crx_regtab[r].type != CRX_R_REGTYPE))
+	    as_fatal (_("Illegal register `%s' in register list"), reg_name);
+
+	  mask_reg (getreg_image (r - r0), &mask);
+        }
+
+      if (++reg_counter > MAX_REGS_IN_MASK16)
+	as_bad (_("Maximum %d bits may be set in `mask16' operand"),
+		MAX_REGS_IN_MASK16);
+
+next_inst:
+      while (!ISALNUM (*paramP) && *paramP != '}')
+	  paramP++;
+    }
+
+  if (*++paramP != '\0')
+    as_warn (_("rest of line ignored; first ignored character is `%c'"),
+	     *paramP);
+
+  switch (hi_found + lo_found)
+    {
+    case 0:
+      /* At least one register should be specified.  */
+      if (mask == 0)
+	as_bad (_("Illegal `mask16' operand, operation is undefined - `%s'"),
+		ins_parse);
+      break;
+
+    case 1:
+      /* HI can't be specified without LO (and vise-versa).  */
+      as_bad (_("HI/LO registers should be specified together"));
+      break;
+
+    case 2:
+      /* HI/LO registers mustn't be masked with additional registers.  */
+      if (mask != 0)
+	as_bad (_("HI/LO registers should be specified without additional registers"));
+
+    default:
+      break;
+    }
+
+  sprintf (maskstring, "$0x%x", mask);
+  strcat (new_param, maskstring);
+  return new_param;
+}
+
+/* Print the instruction.
+   Handle also cases where the instruction is relaxable/relocatable.  */
+
+void
+print_insn (ins *insn)
+{
+  unsigned int i, j, insn_size;
+  char *this_frag;
+  unsigned short words[4];
+  int addr_mod;
+
+  /* Arrange the insn encodings in a WORD size array.  */
+  for (i = 0, j = 0; i < 2; i++)
+    {
+      words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
+      words[j++] = output_opcode[i] & 0xFFFF;
+    }
+
+  /* Handle relaxtion.  */
+  if ((instruction->flags & RELAXABLE) && relocatable)
+    {
+      int relax_subtype;
+
+      /* Write the maximal instruction size supported.  */
+      insn_size = INSN_MAX_SIZE;
+
+      /* bCC  */
+      if (IS_INSN_TYPE (BRANCH_INS))
+	relax_subtype = 0;
+      /* bal  */
+      else if (IS_INSN_TYPE (DCR_BRANCH_INS) || IS_INSN_MNEMONIC ("bal"))
+	relax_subtype = 3;
+      /* cmpbr/bcop  */
+      else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
+	relax_subtype = 5;
+      else
+	abort ();
+
+      this_frag = frag_var (rs_machine_dependent, insn_size * 2,
+			    4, relax_subtype,
+			    insn->exp.X_add_symbol,
+			    insn->exp.X_add_number,
+			    0);
+    }
+  else
+    {
+      insn_size = instruction->size;
+      this_frag = frag_more (insn_size * 2);
+
+      /* Handle relocation.  */
+      if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
+	{
+	  reloc_howto_type *reloc_howto;
+	  int size;
+
+	  reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
+
+	  if (!reloc_howto)
+	    abort ();
+
+	  size = bfd_get_reloc_size (reloc_howto);
+
+	  if (size < 1 || size > 4)
+	    abort ();
+
+	  fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+		       size, &insn->exp, reloc_howto->pc_relative,
+		       insn->rtype);
+	}
+    }
+
+  /* Verify a 2-byte code alignment.  */
+  addr_mod = frag_now_fix () & 1;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 2"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
+  /* Write the instruction encoding to frag.  */
+  for (i = 0; i < insn_size; i++)
+    {
+      md_number_to_chars (this_frag, (valueT) words[i], 2);
+      this_frag += 2;
+    }
+}
+
+/* This is the guts of the machine-dependent assembler.  OP points to a
+   machine dependent instruction.  This function is supposed to emit
+   the frags/bytes it assembles to.  */
+
+void
+md_assemble (char *op)
+{
+  ins crx_ins;
+  char *param;
+  char c;
+
+  /* Reset global variables for a new instruction.  */
+  reset_vars (op);
+
+  /* Strip the mnemonic.  */
+  for (param = op; *param != 0 && !ISSPACE (*param); param++)
+    ;
+  c = *param;
+  *param++ = '\0';
+
+  /* Find the instruction.  */
+  instruction = (const inst *) hash_find (crx_inst_hash, op);
+  if (instruction == NULL)
+    {
+      as_bad (_("Unknown opcode: `%s'"), op);
+      return;
+    }
+
+  /* Tie dwarf2 debug info to the address at the start of the insn.  */
+  dwarf2_emit_insn (0);
+
+  /* Parse the instruction's operands.  */
+  parse_insn (&crx_ins, param);
+
+  /* Assemble the instruction - return upon failure.  */
+  if (assemble_insn (op, &crx_ins) == 0)
+    return;
+
+  /* Print the instruction.  */
+  print_insn (&crx_ins);
+}
diff --git a/gas/config/tc-crx.h b/gas/config/tc-crx.h
new file mode 100644
index 000000000000..b1c3c6501c05
--- /dev/null
+++ b/gas/config/tc-crx.h
@@ -0,0 +1,78 @@
+/* tc-crx.h -- Header file for tc-crx.c, the CRX GAS port.
+   Copyright 2004 Free Software Foundation, Inc.
+
+   Contributed by Tomer Levi, NSC, Israel.
+   Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
+   Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
+
+#ifndef TC_CRX_H
+#define TC_CRX_H
+
+#define TC_CRX 1
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_FORMAT "elf32-crx"
+#define TARGET_ARCH   bfd_arch_crx
+
+#define WORKING_DOT_WORD
+#define LOCAL_LABEL_PREFIX '.'
+
+#define md_undefined_symbol(s)	0
+#define md_number_to_chars	number_to_chars_littleendian
+
+/* We do relaxing in the assembler as well as the linker.  */
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+/* We do not want to adjust any relocations to make implementation of
+   linker relaxations easier.  */
+#define tc_fix_adjustable(fixP)	0
+
+/* We need to force out some relocations when relaxing.  */
+#define TC_FORCE_RELOCATION(FIXP) crx_force_relocation (FIXP)
+extern int crx_force_relocation (struct fix *);
+
+/* Fixup debug sections since we will never relax them.  */
+#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
+
+/* CRX instructions, with operands included, are a multiple
+   of two bytes long.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+/* This is called by emit_expr when creating a reloc for a cons.
+   We could use the definition there, except that we want to handle 
+   the CRX reloc type specially, rather than the BFD_RELOC type.  */
+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
+      fix_new_exp (FRAG, OFF, (int) LEN, EXP, 0, \
+	LEN == 1 ? BFD_RELOC_CRX_NUM8 \
+	: LEN == 2 ? BFD_RELOC_CRX_NUM16 \
+	: LEN == 4 ? BFD_RELOC_CRX_NUM32 \
+	: BFD_RELOC_NONE);
+
+/* Give an error if a frag containing code is not aligned to a 2-byte 
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code							\
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 1) != 0)		\
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,			\
+		   _("instruction address is not a multiple of 2"));
+
+#endif /* TC_CRX_H */
diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c
index 639fdc0c9446..6c94edbb4ef3 100644
--- a/gas/config/tc-d10v.c
+++ b/gas/config/tc-d10v.c
@@ -1,5 +1,5 @@
 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -26,12 +26,12 @@
 #include "opcode/d10v.h"
 #include "elf/ppc.h"
 
-const char comment_chars[] = ";";
-const char line_comment_chars[] = "#";
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
 const char line_separator_chars[] = "";
-const char *md_shortopts = "O";
-const char EXP_CHARS[] = "eE";
-const char FLT_CHARS[] = "dD";
+const char *md_shortopts          = "O";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
 
 int Optimizing = 0;
 
@@ -42,7 +42,8 @@ int Optimizing = 0;
 #define AT_WORD_RIGHT_SHIFT 2
 
 /* Fixups.  */
-#define MAX_INSN_FIXUPS (5)
+#define MAX_INSN_FIXUPS  5
+
 struct d10v_fixup
 {
   expressionS exp;
@@ -80,40 +81,19 @@ static bfd_boolean flag_warn_suppress_instructionswap;
 static bfd_boolean flag_allow_gstabs_packing = 1;
 
 /* Local functions.  */
-static int reg_name_search PARAMS ((char *name));
-static int register_name PARAMS ((expressionS *expressionP));
-static int check_range PARAMS ((unsigned long num, int bits, int flags));
-static int postfix PARAMS ((char *p));
-static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
-static int get_operands PARAMS ((expressionS exp[]));
-static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
-static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
-static void write_long PARAMS ((unsigned long insn, Fixups *fx));
-static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
-static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
-				  struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx));
-static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
-static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
-						   offsetT value, int left, fixS *fix));
-static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
-				struct d10v_opcode *opcode2, unsigned long insn2,
-				packing_type exec_type));
-
-static void check_resource_conflict PARAMS ((struct d10v_opcode *opcode1,
-					     unsigned long insn1,
-					     struct d10v_opcode *opcode2,
-					     unsigned long insn2));
-
-static symbolS * find_symbol_matching_register PARAMS ((expressionS *));
+
+enum options
+{
+  OPTION_NOWARNSWAP = OPTION_MD_BASE,
+  OPTION_GSTABSPACKING,
+  OPTION_NOGSTABSPACKING
+};
 
 struct option md_longopts[] =
 {
-#define OPTION_NOWARNSWAP (OPTION_MD_BASE)
   {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
-#define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1)
   {"gstabspacking",  no_argument, NULL, OPTION_GSTABSPACKING},
   {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
-#define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2)
   {"nogstabspacking",   no_argument, NULL, OPTION_NOGSTABSPACKING},
   {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
   {NULL, no_argument, NULL, 0}
@@ -121,15 +101,6 @@ struct option md_longopts[] =
 
 size_t md_longopts_size = sizeof (md_longopts);
 
-static void d10v_dot_word PARAMS ((int));
-
-/* The target specific pseudo-ops which we support.  */
-const pseudo_typeS md_pseudo_table[] =
-{
-  { "word",	d10v_dot_word,	2 },
-  { NULL,       NULL,           0 }
-};
-
 /* Opcode hash table.  */
 static struct hash_control *d10v_hash;
 
@@ -138,8 +109,7 @@ static struct hash_control *d10v_hash;
    array on success, or -1 on failure.  */
 
 static int
-reg_name_search (name)
-     char *name;
+reg_name_search (char *name)
 {
   int middle, low, high;
   int cmp;
@@ -166,8 +136,7 @@ reg_name_search (name)
    to see if it is a valid register name.  */
 
 static int
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char c, *p = input_line_pointer;
@@ -197,10 +166,7 @@ register_name (expressionP)
 }
 
 static int
-check_range (num, bits, flags)
-     unsigned long num;
-     int bits;
-     int flags;
+check_range (unsigned long num, int bits, int flags)
 {
   long min, max;
   int retval = 0;
@@ -246,8 +212,7 @@ check_range (num, bits, flags)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("D10V options:\n\
 -O                      Optimize.  Will do some operations in parallel.\n\
@@ -258,9 +223,7 @@ md_show_usage (stream)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -284,8 +247,7 @@ md_parse_option (c, arg)
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -296,10 +258,7 @@ md_undefined_symbol (name)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -334,25 +293,22 @@ md_atof (type, litP, sizeP)
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
 {
   abort ();
 }
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   char *prev_name = "";
   struct d10v_opcode *opcode;
@@ -381,8 +337,7 @@ md_begin ()
    from an expression.  */
 
 static int
-postfix (p)
-     char *p;
+postfix (char *p)
 {
   while (*p != '-' && *p != '+')
     {
@@ -394,42 +349,40 @@ postfix (p)
   if (*p == '-')
     {
       *p = ' ';
-      return (-1);
+      return -1;
     }
   if (*p == '+')
     {
       *p = ' ';
-      return (1);
+      return 1;
     }
 
-  return (0);
+  return 0;
 }
 
 static bfd_reloc_code_real_type
-get_reloc (op)
-     struct d10v_operand *op;
+get_reloc (struct d10v_operand *op)
 {
   int bits = op->bits;
 
   if (bits <= 4)
-    return (0);
+    return 0;
 
   if (op->flags & OPERAND_ADDR)
     {
       if (bits == 8)
-	return (BFD_RELOC_D10V_10_PCREL_R);
+	return BFD_RELOC_D10V_10_PCREL_R;
       else
-	return (BFD_RELOC_D10V_18_PCREL);
+	return BFD_RELOC_D10V_18_PCREL;
     }
 
-  return (BFD_RELOC_16);
+  return BFD_RELOC_16;
 }
 
 /* Parse a string of operands.  Return an array of expressions.  */
 
 static int
-get_operands (exp)
-     expressionS exp[];
+get_operands (expressionS exp[])
 {
   char *p = input_line_pointer;
   int numops = 0;
@@ -561,16 +514,15 @@ get_operands (exp)
     }
 
   exp[numops].X_op = 0;
-  return (numops);
+  return numops;
 }
 
 static unsigned long
-d10v_insert_operand (insn, op_type, value, left, fix)
-     unsigned long insn;
-     int op_type;
-     offsetT value;
-     int left;
-     fixS *fix;
+d10v_insert_operand (unsigned long insn,
+		     int op_type,
+		     offsetT value,
+		     int left,
+		     fixS *fix)
 {
   int shift, bits;
 
@@ -595,10 +547,9 @@ d10v_insert_operand (insn, op_type, value, left, fix)
    array of operand expressions.  Return the instruction.  */
 
 static unsigned long
-build_insn (opcode, opers, insn)
-     struct d10v_opcode *opcode;
-     expressionS *opers;
-     unsigned long insn;
+build_insn (struct d10v_opcode *opcode,
+	    expressionS *opers,
+	    unsigned long insn)
 {
   int i, bits, shift, flags, format;
   unsigned long number;
@@ -689,9 +640,7 @@ build_insn (opcode, opers, insn)
 /* Write out a long form instruction.  */
 
 static void
-write_long (insn, fx)
-     unsigned long insn;
-     Fixups *fx;
+write_long (unsigned long insn, Fixups *fx)
 {
   int i, where;
   char *f = frag_more (4);
@@ -724,10 +673,9 @@ write_long (insn, fx)
 /* Write out a short form instruction by itself.  */
 
 static void
-write_1_short (opcode, insn, fx)
-     struct d10v_opcode *opcode;
-     unsigned long insn;
-     Fixups *fx;
+write_1_short (struct d10v_opcode *opcode,
+	       unsigned long insn,
+	       Fixups *fx)
 {
   char *f = frag_more (4);
   int i, where;
@@ -771,171 +719,151 @@ write_1_short (opcode, insn, fx)
   fx->fc = 0;
 }
 
-/* Expects two short instructions.
-   If possible, writes out both as a single packed instruction.
-   Otherwise, writes out the first one, packed with a NOP.
-   Returns number of instructions not written out.  */
+/* Determine if there are any resource conflicts among two manually
+   parallelized instructions.  Some of this was lifted from parallel_ok.  */
 
-static int
-write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
-     struct d10v_opcode *opcode1, *opcode2;
-     unsigned long insn1, insn2;
-     packing_type exec_type;
-     Fixups *fx;
+static void
+check_resource_conflict (struct d10v_opcode *op1,
+			 unsigned long insn1,
+			 struct d10v_opcode *op2,
+			 unsigned long insn2)
 {
-  unsigned long insn;
-  char *f;
-  int i, j, where;
+  int i, j, flags, mask, shift, regno;
+  unsigned long ins, mod[2];
+  struct d10v_opcode *op;
 
-  if ((exec_type != PACK_PARALLEL)
-      && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
-    as_fatal (_("Instruction must be executed in parallel"));
+  if ((op1->exec_type & SEQ)
+      || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
+    {
+      as_warn (_("packing conflict: %s must dispatch sequentially"),
+	      op1->name);
+      return;
+    }
 
-  if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
-    as_fatal (_("Long instructions may not be combined."));
+  if ((op2->exec_type & SEQ)
+      || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
+    {
+      as_warn (_("packing conflict: %s must dispatch sequentially"),
+	      op2->name);
+      return;
+    }
 
-  switch (exec_type)
+   /* See if both instructions write to the same resource.
+
+      The idea here is to create two sets of bitmasks (mod and used) which
+      indicate which registers are modified or used by each instruction.
+      The operation can only be done in parallel if neither instruction
+      modifies the same register. Accesses to control registers and memory
+      are treated as accesses to a single register. So if both instructions
+      write memory or if the first instruction writes memory and the second
+      reads, then they cannot be done in parallel. We treat reads to the PSW
+      (which includes C, F0, and F1) in isolation. So simultaneously writing
+      C and F0 in two different sub-instructions is permitted.  */
+
+  /* The bitmasks (mod and used) look like this (bit 31 = MSB).
+     r0-r15	  0-15
+     a0-a1	  16-17
+     cr (not psw) 18
+     psw(other)   19
+     mem	  20
+     psw(C flag)  21
+     psw(F0 flag) 22  */
+
+  for (j = 0; j < 2; j++)
     {
-    case PACK_UNSPEC:	/* Order not specified.  */
-      if (opcode1->exec_type & ALONE)
-	{
-	  /* Case of a short branch on a separate GAS line.  Pack with NOP.  */
-	  write_1_short (opcode1, insn1, fx->next);
-	  return 1;
-	}
-      if (Optimizing
-	  && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
+      if (j == 0)
 	{
-	  /* Parallel.  */
-	  if (opcode1->unit == IU)
-	    insn = FM00 | (insn2 << 15) | insn1;
-	  else if (opcode2->unit == MU)
-	    insn = FM00 | (insn2 << 15) | insn1;
-	  else
-	    insn = FM00 | (insn1 << 15) | insn2;
+	  op = op1;
+	  ins = insn1;
 	}
-      else if (opcode1->unit == IU)
-	/* Reverse sequential with IU opcode1 on right and done first.  */
-	insn = FM10 | (insn2 << 15) | insn1;
       else
-	/* Sequential with non-IU opcode1 on left and done first.  */
-	insn = FM01 | (insn1 << 15) | insn2;
-      break;
-
-    case PACK_PARALLEL:
-      if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
-	as_fatal
-	  (_("One of these instructions may not be executed in parallel."));
-      if (opcode1->unit == IU)
 	{
-	  if (opcode2->unit == IU)
-	    as_fatal (_("Two IU instructions may not be executed in parallel"));
-	  if (!flag_warn_suppress_instructionswap)
-	    as_warn (_("Swapping instruction order"));
-	  insn = FM00 | (insn2 << 15) | insn1;
-	}
-      else if (opcode2->unit == MU)
-	{
-	  if (opcode1->unit == MU)
-	    as_fatal (_("Two MU instructions may not be executed in parallel"));
-	  if (!flag_warn_suppress_instructionswap)
-	    as_warn (_("Swapping instruction order"));
-	  insn = FM00 | (insn2 << 15) | insn1;
+	  op = op2;
+	  ins = insn2;
 	}
-      else
-	insn = FM00 | (insn1 << 15) | insn2;
-      check_resource_conflict (opcode1, insn1, opcode2, insn2);
-      break;
+      mod[j] = 0;
+      if (op->exec_type & BRANCH_LINK)
+	mod[j] |= 1 << 13;
 
-    case PACK_LEFT_RIGHT:
-      if (opcode1->unit != IU)
-	insn = FM01 | (insn1 << 15) | insn2;
-      else if (opcode2->unit == MU || opcode2->unit == EITHER)
+      for (i = 0; op->operands[i]; i++)
 	{
-	  if (!flag_warn_suppress_instructionswap)
-	    as_warn (_("Swapping instruction order"));
-	  insn = FM10 | (insn2 << 15) | insn1;
-	}
-      else
-	as_fatal (_("IU instruction may not be in the left container"));
-      if (opcode1->exec_type & ALONE)
-	as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
-      break;
+	  flags = d10v_operands[op->operands[i]].flags;
+	  shift = d10v_operands[op->operands[i]].shift;
+	  mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
+	  if (flags & OPERAND_REG)
+	    {
+	      regno = (ins >> shift) & mask;
+	      if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
+		regno += 16;
+	      else if (flags & OPERAND_CONTROL)	/* mvtc or mvfc */
+		{
+		  if (regno == 0)
+		    regno = 19;
+		  else
+		    regno = 18;
+		}
+	      else if (flags & OPERAND_FFLAG)
+		regno = 22;
+	      else if (flags & OPERAND_CFLAG)
+		regno = 21;
 
-    case PACK_RIGHT_LEFT:
-      if (opcode2->unit != MU)
-	insn = FM10 | (insn1 << 15) | insn2;
-      else if (opcode1->unit == IU || opcode1->unit == EITHER)
-	{
-	  if (!flag_warn_suppress_instructionswap)
-	    as_warn (_("Swapping instruction order"));
-	  insn = FM01 | (insn2 << 15) | insn1;
+	      if (flags & OPERAND_DEST
+		  /* Auto inc/dec also modifies the register.  */
+		  || (op->operands[i + 1] != 0
+		      && (d10v_operands[op->operands[i + 1]].flags
+			  & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
+		{
+		  mod[j] |= 1 << regno;
+		  if (flags & OPERAND_EVEN)
+		    mod[j] |= 1 << (regno + 1);
+		}
+	    }
+	  else if (flags & OPERAND_ATMINUS)
+	    {
+	      /* SP implicitly used/modified.  */
+	      mod[j] |= 1 << 15;
+	    }
 	}
-      else
-	as_fatal (_("MU instruction may not be in the right container"));
-      if (opcode2->exec_type & ALONE)
-	as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
-      break;
 
-    default:
-      as_fatal (_("unknown execution type passed to write_2_short()"));
+      if (op->exec_type & WMEM)
+	mod[j] |= 1 << 20;
+      else if (op->exec_type & WF0)
+	mod[j] |= 1 << 22;
+      else if (op->exec_type & WCAR)
+	mod[j] |= 1 << 21;
     }
 
-  f = frag_more (4);
-  number_to_chars_bigendian (f, insn, 4);
-
-  /* Process fixup chains.  fx refers to insn2 when j == 0, and to
-     insn1 when j == 1.  Yes, it's reversed.  */
-
-  for (j = 0; j < 2; j++)
+  if ((mod[0] & mod[1]) == 0)
+    return;
+  else
     {
-      for (i = 0; i < fx->fc; i++)
-	{
-	  if (fx->fix[i].reloc)
-	    {
-	      where = f - frag_now->fr_literal;
-	      if (fx->fix[i].size == 2)
-		where += 2;
-
-	      if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
-		  /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
-		     the instruction in the L container has to be
-		     adjusted to BDF_RELOC_D10V_10_PCREL_L.  When
-		     j==0, we're processing insn2's operands, so we
-		     want to mark the operand if insn2 is *not* in the
-		     R container.  When j==1, we're processing insn1's
-		     operands, so we want to mark the operand if insn2
-		     *is* in the R container.  Note that, if two
-		     instructions are identical, we're never going to
-		     swap them, so the test is safe.  */
-		  && j == ((insn & 0x7fff) == insn2))
-		fx->fix[i].operand |= 1024;
-
-	      if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
-		fx->fix[i].operand |= 4096;
+      unsigned long x;
+      x = mod[0] & mod[1];
 
-	      fix_new_exp (frag_now,
-			   where,
-			   fx->fix[i].size,
-			   &(fx->fix[i].exp),
-			   fx->fix[i].pcrel,
-			   fx->fix[i].operand|2048);
-	    }
-	}
-      fx->fc = 0;
-      fx = fx->next;
+      for (j = 0; j <= 15; j++)
+	if (x & (1 << j))
+	  as_warn (_("resource conflict (R%d)"), j);
+      for (j = 16; j <= 17; j++)
+	if (x & (1 << j))
+	  as_warn (_("resource conflict (A%d)"), j - 16);
+      if (x & (1 << 19))
+	as_warn (_("resource conflict (PSW)"));
+      if (x & (1 << 21))
+	as_warn (_("resource conflict (C flag)"));
+      if (x & (1 << 22))
+	as_warn (_("resource conflict (F flag)"));
     }
-  return (0);
 }
 
 /* Check 2 instructions and determine if they can be safely
    executed in parallel.  Return 1 if they can be.  */
 
 static int
-parallel_ok (op1, insn1, op2, insn2, exec_type)
-     struct d10v_opcode *op1, *op2;
-     unsigned long insn1, insn2;
-     packing_type exec_type;
+parallel_ok (struct d10v_opcode *op1,
+	     unsigned long insn1,
+	     struct d10v_opcode *op2,
+	     unsigned long insn2,
+	     packing_type exec_type)
 {
   int i, j, flags, mask, shift, regno;
   unsigned long ins, mod[2], used[2];
@@ -1054,312 +982,179 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
   return 0;
 }
 
-/* Determine if there are any resource conflicts among two manually
-   parallelized instructions.  Some of this was lifted from parallel_ok.  */
+/* Expects two short instructions.
+   If possible, writes out both as a single packed instruction.
+   Otherwise, writes out the first one, packed with a NOP.
+   Returns number of instructions not written out.  */
 
-static void
-check_resource_conflict (op1, insn1, op2, insn2)
-     struct d10v_opcode *op1, *op2;
-     unsigned long insn1, insn2;
+static int
+write_2_short (struct d10v_opcode *opcode1,
+	       unsigned long insn1,
+	       struct d10v_opcode *opcode2,
+	       unsigned long insn2,
+	       packing_type exec_type,
+	       Fixups *fx)
 {
-  int i, j, flags, mask, shift, regno;
-  unsigned long ins, mod[2];
-  struct d10v_opcode *op;
-
-  if ((op1->exec_type & SEQ)
-      || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
-    {
-      as_warn (_("packing conflict: %s must dispatch sequentially"),
-	      op1->name);
-      return;
-    }
-
-  if ((op2->exec_type & SEQ)
-      || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
-    {
-      as_warn (_("packing conflict: %s must dispatch sequentially"),
-	      op2->name);
-      return;
-    }
-
-   /* See if both instructions write to the same resource.
+  unsigned long insn;
+  char *f;
+  int i, j, where;
 
-      The idea here is to create two sets of bitmasks (mod and used) which
-      indicate which registers are modified or used by each instruction.
-      The operation can only be done in parallel if neither instruction
-      modifies the same register. Accesses to control registers and memory
-      are treated as accesses to a single register. So if both instructions
-      write memory or if the first instruction writes memory and the second
-      reads, then they cannot be done in parallel. We treat reads to the PSW
-      (which includes C, F0, and F1) in isolation. So simultaneously writing
-      C and F0 in two different sub-instructions is permitted.  */
+  if ((exec_type != PACK_PARALLEL)
+      && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
+    as_fatal (_("Instruction must be executed in parallel"));
 
-  /* The bitmasks (mod and used) look like this (bit 31 = MSB).
-     r0-r15	  0-15
-     a0-a1	  16-17
-     cr (not psw) 18
-     psw(other)   19
-     mem	  20
-     psw(C flag)  21
-     psw(F0 flag) 22  */
+  if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
+    as_fatal (_("Long instructions may not be combined."));
 
-  for (j = 0; j < 2; j++)
+  switch (exec_type)
     {
-      if (j == 0)
+    case PACK_UNSPEC:	/* Order not specified.  */
+      if (opcode1->exec_type & ALONE)
 	{
-	  op = op1;
-	  ins = insn1;
+	  /* Case of a short branch on a separate GAS line.  Pack with NOP.  */
+	  write_1_short (opcode1, insn1, fx->next);
+	  return 1;
 	}
-      else
+      if (Optimizing
+	  && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
 	{
-	  op = op2;
-	  ins = insn2;
+	  /* Parallel.  */
+	  if (opcode1->unit == IU)
+	    insn = FM00 | (insn2 << 15) | insn1;
+	  else if (opcode2->unit == MU)
+	    insn = FM00 | (insn2 << 15) | insn1;
+	  else
+	    insn = FM00 | (insn1 << 15) | insn2;
 	}
-      mod[j] = 0;
-      if (op->exec_type & BRANCH_LINK)
-	mod[j] |= 1 << 13;
+      else if (opcode1->unit == IU)
+	/* Reverse sequential with IU opcode1 on right and done first.  */
+	insn = FM10 | (insn2 << 15) | insn1;
+      else
+	/* Sequential with non-IU opcode1 on left and done first.  */
+	insn = FM01 | (insn1 << 15) | insn2;
+      break;
 
-      for (i = 0; op->operands[i]; i++)
+    case PACK_PARALLEL:
+      if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
+	as_fatal
+	  (_("One of these instructions may not be executed in parallel."));
+      if (opcode1->unit == IU)
 	{
-	  flags = d10v_operands[op->operands[i]].flags;
-	  shift = d10v_operands[op->operands[i]].shift;
-	  mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
-	  if (flags & OPERAND_REG)
-	    {
-	      regno = (ins >> shift) & mask;
-	      if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
-		regno += 16;
-	      else if (flags & OPERAND_CONTROL)	/* mvtc or mvfc */
-		{
-		  if (regno == 0)
-		    regno = 19;
-		  else
-		    regno = 18;
-		}
-	      else if (flags & OPERAND_FFLAG)
-		regno = 22;
-	      else if (flags & OPERAND_CFLAG)
-		regno = 21;
-
-	      if (flags & OPERAND_DEST
-		  /* Auto inc/dec also modifies the register.  */
-		  || (op->operands[i + 1] != 0
-		      && (d10v_operands[op->operands[i + 1]].flags
-			  & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
-		{
-		  mod[j] |= 1 << regno;
-		  if (flags & OPERAND_EVEN)
-		    mod[j] |= 1 << (regno + 1);
-		}
-	    }
-	  else if (flags & OPERAND_ATMINUS)
-	    {
-	      /* SP implicitly used/modified.  */
-	      mod[j] |= 1 << 15;
-	    }
+	  if (opcode2->unit == IU)
+	    as_fatal (_("Two IU instructions may not be executed in parallel"));
+	  if (!flag_warn_suppress_instructionswap)
+	    as_warn (_("Swapping instruction order"));
+	  insn = FM00 | (insn2 << 15) | insn1;
 	}
-
-      if (op->exec_type & WMEM)
-	mod[j] |= 1 << 20;
-      else if (op->exec_type & WF0)
-	mod[j] |= 1 << 22;
-      else if (op->exec_type & WCAR)
-	mod[j] |= 1 << 21;
-    }
-
-  if ((mod[0] & mod[1]) == 0)
-    return;
-  else
-    {
-      unsigned long x;
-      x = mod[0] & mod[1];
-
-      for (j = 0; j <= 15; j++)
-	if (x & (1 << j))
-	  as_warn (_("resource conflict (R%d)"), j);
-      for (j = 16; j <= 17; j++)
-	if (x & (1 << j))
-	  as_warn (_("resource conflict (A%d)"), j - 16);
-      if (x & (1 << 19))
-	as_warn (_("resource conflict (PSW)"));
-      if (x & (1 << 21))
-	as_warn (_("resource conflict (C flag)"));
-      if (x & (1 << 22))
-	as_warn (_("resource conflict (F flag)"));
-    }
-}
-
-/* This is the main entry point for the machine-dependent assembler.
-   str points to a machine-dependent instruction.  This function is
-   supposed to emit the frags/bytes it assembles to.  For the D10V, it
-   mostly handles the special VLIW parsing and packing and leaves the
-   difficult stuff to do_assemble().  */
-
-static unsigned long prev_insn;
-static struct d10v_opcode *prev_opcode = 0;
-static subsegT prev_subseg;
-static segT prev_seg = 0;;
-
-void
-md_assemble (str)
-     char *str;
-{
-  /* etype is saved extype.  For multi-line instructions.  */
-
-  packing_type extype = PACK_UNSPEC;		/* Parallel, etc.  */
-
-  struct d10v_opcode *opcode;
-  unsigned long insn;
-  char *str2;
-
-  if (etype == PACK_UNSPEC)
-    {
-      /* Look for the special multiple instruction separators.  */
-      str2 = strstr (str, "||");
-      if (str2)
-	extype = PACK_PARALLEL;
-      else
+      else if (opcode2->unit == MU)
 	{
-	  str2 = strstr (str, "->");
-	  if (str2)
-	    extype = PACK_LEFT_RIGHT;
-	  else
-	    {
-	      str2 = strstr (str, "<-");
-	      if (str2)
-		extype = PACK_RIGHT_LEFT;
-	    }
+	  if (opcode1->unit == MU)
+	    as_fatal (_("Two MU instructions may not be executed in parallel"));
+	  if (!flag_warn_suppress_instructionswap)
+	    as_warn (_("Swapping instruction order"));
+	  insn = FM00 | (insn2 << 15) | insn1;
 	}
+      else
+	insn = FM00 | (insn1 << 15) | insn2;
+      check_resource_conflict (opcode1, insn1, opcode2, insn2);
+      break;
 
-      /* str2 points to the separator, if there is one.  */
-      if (str2)
+    case PACK_LEFT_RIGHT:
+      if (opcode1->unit != IU)
+	insn = FM01 | (insn1 << 15) | insn2;
+      else if (opcode2->unit == MU || opcode2->unit == EITHER)
 	{
-	  *str2 = 0;
-
-	  /* If two instructions are present and we already have one saved,
-	     then first write out the saved one.  */
-	  d10v_cleanup ();
-
-	  /* Assemble first instruction and save it.  */
-	  prev_insn = do_assemble (str, &prev_opcode);
-	  prev_seg = now_seg;
-	  prev_subseg = now_subseg;
-	  if (prev_insn == (unsigned long) -1)
-	    as_fatal (_("can't find opcode "));
-	  fixups = fixups->next;
-	  str = str2 + 2;
+	  if (!flag_warn_suppress_instructionswap)
+	    as_warn (_("Swapping instruction order"));
+	  insn = FM10 | (insn2 << 15) | insn1;
 	}
-    }
+      else
+	as_fatal (_("IU instruction may not be in the left container"));
+      if (opcode1->exec_type & ALONE)
+	as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
+      break;
 
-  insn = do_assemble (str, &opcode);
-  if (insn == (unsigned long) -1)
-    {
-      if (extype != PACK_UNSPEC)
+    case PACK_RIGHT_LEFT:
+      if (opcode2->unit != MU)
+	insn = FM10 | (insn1 << 15) | insn2;
+      else if (opcode1->unit == IU || opcode1->unit == EITHER)
 	{
-	  etype = extype;
-	  return;
+	  if (!flag_warn_suppress_instructionswap)
+	    as_warn (_("Swapping instruction order"));
+	  insn = FM01 | (insn2 << 15) | insn1;
 	}
-      as_fatal (_("can't find opcode "));
-    }
+      else
+	as_fatal (_("MU instruction may not be in the right container"));
+      if (opcode2->exec_type & ALONE)
+	as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
+      break;
 
-  if (etype != PACK_UNSPEC)
-    {
-      extype = etype;
-      etype = PACK_UNSPEC;
+    default:
+      as_fatal (_("unknown execution type passed to write_2_short()"));
     }
 
-  /* If this is a long instruction, write it and any previous short
-     instruction.  */
-  if (opcode->format & LONG_OPCODE)
-    {
-      if (extype != PACK_UNSPEC)
-	as_fatal (_("Unable to mix instructions as specified"));
-      d10v_cleanup ();
-      write_long (insn, fixups);
-      prev_opcode = NULL;
-      return;
-    }
+  f = frag_more (4);
+  number_to_chars_bigendian (f, insn, 4);
 
-  if (prev_opcode
-      && prev_seg
-      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
-    d10v_cleanup ();
+  /* Process fixup chains.  fx refers to insn2 when j == 0, and to
+     insn1 when j == 1.  Yes, it's reversed.  */
 
-  if (prev_opcode
-      && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
-			      fixups)))
-    {
-      /* No instructions saved.  */
-      prev_opcode = NULL;
-    }
-  else
+  for (j = 0; j < 2; j++)
     {
-      if (extype != PACK_UNSPEC)
-	as_fatal (_("Unable to mix instructions as specified"));
-      /* Save last instruction so it may be packed on next pass.  */
-      prev_opcode = opcode;
-      prev_insn = insn;
-      prev_seg = now_seg;
-      prev_subseg = now_subseg;
-      fixups = fixups->next;
-    }
-}
-
-/* Assemble a single instruction.
-   Return an opcode, or -1 (an invalid opcode) on error.  */
+      for (i = 0; i < fx->fc; i++)
+	{
+	  if (fx->fix[i].reloc)
+	    {
+	      where = f - frag_now->fr_literal;
+	      if (fx->fix[i].size == 2)
+		where += 2;
 
-static unsigned long
-do_assemble (str, opcode)
-     char *str;
-     struct d10v_opcode **opcode;
-{
-  unsigned char *op_start, *save;
-  unsigned char *op_end;
-  char name[20];
-  int nlen = 0;
-  expressionS myops[6];
-  unsigned long insn;
+	      if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
+		  /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
+		     the instruction in the L container has to be
+		     adjusted to BDF_RELOC_D10V_10_PCREL_L.  When
+		     j==0, we're processing insn2's operands, so we
+		     want to mark the operand if insn2 is *not* in the
+		     R container.  When j==1, we're processing insn1's
+		     operands, so we want to mark the operand if insn2
+		     *is* in the R container.  Note that, if two
+		     instructions are identical, we're never going to
+		     swap them, so the test is safe.  */
+		  && j == ((insn & 0x7fff) == insn2))
+		fx->fix[i].operand |= 1024;
 
-  /* Drop leading whitespace.  */
-  while (*str == ' ')
-    str++;
+	      if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
+		fx->fix[i].operand |= 4096;
 
-  /* Find the opcode end.  */
-  for (op_start = op_end = (unsigned char *) (str);
-       *op_end
-       && nlen < 20
-       && !is_end_of_line[*op_end] && *op_end != ' ';
-       op_end++)
-    {
-      name[nlen] = TOLOWER (op_start[nlen]);
-      nlen++;
+	      fix_new_exp (frag_now,
+			   where,
+			   fx->fix[i].size,
+			   &(fx->fix[i].exp),
+			   fx->fix[i].pcrel,
+			   fx->fix[i].operand|2048);
+	    }
+	}
+      fx->fc = 0;
+      fx = fx->next;
     }
-  name[nlen] = 0;
-
-  if (nlen == 0)
-    return -1;
-
-  /* Find the first opcode with the proper name.  */
-  *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
-  if (*opcode == NULL)
-    as_fatal (_("unknown opcode: %s"), name);
+  return 0;
+}
 
-  save = input_line_pointer;
-  input_line_pointer = op_end;
-  *opcode = find_opcode (*opcode, myops);
-  if (*opcode == 0)
-    return -1;
-  input_line_pointer = save;
+/* This is the main entry point for the machine-dependent assembler.
+   str points to a machine-dependent instruction.  This function is
+   supposed to emit the frags/bytes it assembles to.  For the D10V, it
+   mostly handles the special VLIW parsing and packing and leaves the
+   difficult stuff to do_assemble().  */
 
-  insn = build_insn ((*opcode), myops, 0);
-  return (insn);
-}
+static unsigned long prev_insn;
+static struct d10v_opcode *prev_opcode = 0;
+static subsegT prev_subseg;
+static segT prev_seg = 0;;
 
 /* Find the symbol which has the same name as the register in exp.  */
 
 static symbolS *
-find_symbol_matching_register (exp)
-     expressionS *exp;
+find_symbol_matching_register (expressionS *exp)
 {
   int i;
 
@@ -1383,9 +1178,7 @@ find_symbol_matching_register (exp)
    the operands to choose the correct opcode.  */
 
 static struct d10v_opcode *
-find_opcode (opcode, myops)
-     struct d10v_opcode *opcode;
-     expressionS myops[];
+find_opcode (struct d10v_opcode *opcode, expressionS myops[])
 {
   int i, match;
   struct d10v_opcode *next_opcode;
@@ -1505,10 +1298,8 @@ find_opcode (opcode, myops)
 	    opcode = next_opcode;
 	}
       else
-	{
-	  /* Not a constant, so use a long instruction.  */
-	  opcode += 2;
-	}
+	/* Not a constant, so use a long instruction.  */
+	opcode += 2;
     }
 
   match = 0;
@@ -1601,7 +1392,7 @@ find_opcode (opcode, myops)
   if (!match)
     {
       as_bad (_("bad opcode or operands"));
-      return (0);
+      return 0;
     }
 
   /* Check that all registers that are required to be even are.
@@ -1639,17 +1430,61 @@ find_opcode (opcode, myops)
   return opcode;
 }
 
+/* Assemble a single instruction.
+   Return an opcode, or -1 (an invalid opcode) on error.  */
+
+static unsigned long
+do_assemble (char *str, struct d10v_opcode **opcode)
+{
+  unsigned char *op_start, *op_end;
+  char *save;
+  char name[20];
+  int nlen = 0;
+  expressionS myops[6];
+  unsigned long insn;
+
+  /* Drop leading whitespace.  */
+  while (*str == ' ')
+    str++;
+
+  /* Find the opcode end.  */
+  for (op_start = op_end = (unsigned char *) str;
+       *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
+       op_end++)
+    {
+      name[nlen] = TOLOWER (op_start[nlen]);
+      nlen++;
+    }
+  name[nlen] = 0;
+
+  if (nlen == 0)
+    return -1;
+
+  /* Find the first opcode with the proper name.  */
+  *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
+  if (*opcode == NULL)
+    as_fatal (_("unknown opcode: %s"), name);
+
+  save = input_line_pointer;
+  input_line_pointer = (char *) op_end;
+  *opcode = find_opcode (*opcode, myops);
+  if (*opcode == 0)
+    return -1;
+  input_line_pointer = save;
+
+  insn = build_insn ((*opcode), myops, 0);
+  return insn;
+}
+
 /* If while processing a fixup, a reloc really needs to be created.
    Then it is done here.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
@@ -1670,18 +1505,15 @@ tc_gen_reloc (seg, fixp)
 }
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
 }
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec;
+md_pcrel_from_section (fixS *fixp, segT sec)
 {
   if (fixp->fx_addsy != (symbolS *) NULL
       && (!S_IS_DEFINED (fixp->fx_addsy)
@@ -1691,10 +1523,7 @@ md_pcrel_from_section (fixp, sec)
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *where;
   unsigned long insn;
@@ -1743,7 +1572,7 @@ md_apply_fix3 (fixP, valP, seg)
 	 symbol, then ignore the offset.
          XXX - Do we have to worry about branches to a symbol + offset ?  */
       if (fixP->fx_addsy != NULL
-	  && S_IS_EXTERN (fixP->fx_addsy) )
+	  && S_IS_EXTERNAL (fixP->fx_addsy) )
         {
           segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
           segment_info_type *segf = seg_info(fseg);
@@ -1806,7 +1635,7 @@ md_apply_fix3 (fixP, valP, seg)
    NOTE: invoked by various macros such as md_cleanup: see.  */
 
 int
-d10v_cleanup ()
+d10v_cleanup (void)
 {
   segT seg;
   subsegT subseg;
@@ -1838,8 +1667,7 @@ d10v_cleanup ()
    Clobbers input_line_pointer, checks end-of-line.  */
 
 static void
-d10v_dot_word (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
 {
   expressionS exp;
   char *p;
@@ -1882,8 +1710,7 @@ d10v_dot_word (dummy)
    From expr.c.  */
 
 void
-md_operand (expressionP)
-     expressionS *expressionP;
+md_operand (expressionS *expressionP)
 {
   if (*input_line_pointer == '#' && ! do_not_ignore_hash)
     {
@@ -1893,8 +1720,7 @@ md_operand (expressionP)
 }
 
 bfd_boolean
-d10v_fix_adjustable (fixP)
-     fixS *fixP;
+d10v_fix_adjustable (fixS *fixP)
 {
   /* We need the symbol name for the VTABLE entries.  */
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
@@ -1903,3 +1729,113 @@ d10v_fix_adjustable (fixP)
 
   return 1;
 }
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word",	d10v_dot_word,	2 },
+  { NULL,       NULL,           0 }
+};
+
+void
+md_assemble (char *str)
+{
+  /* etype is saved extype.  For multi-line instructions.  */
+  packing_type extype = PACK_UNSPEC;		/* Parallel, etc.  */
+  struct d10v_opcode *opcode;
+  unsigned long insn;
+  char *str2;
+
+  if (etype == PACK_UNSPEC)
+    {
+      /* Look for the special multiple instruction separators.  */
+      str2 = strstr (str, "||");
+      if (str2)
+	extype = PACK_PARALLEL;
+      else
+	{
+	  str2 = strstr (str, "->");
+	  if (str2)
+	    extype = PACK_LEFT_RIGHT;
+	  else
+	    {
+	      str2 = strstr (str, "<-");
+	      if (str2)
+		extype = PACK_RIGHT_LEFT;
+	    }
+	}
+
+      /* str2 points to the separator, if there is one.  */
+      if (str2)
+	{
+	  *str2 = 0;
+
+	  /* If two instructions are present and we already have one saved,
+	     then first write out the saved one.  */
+	  d10v_cleanup ();
+
+	  /* Assemble first instruction and save it.  */
+	  prev_insn = do_assemble (str, &prev_opcode);
+	  prev_seg = now_seg;
+	  prev_subseg = now_subseg;
+	  if (prev_insn == (unsigned long) -1)
+	    as_fatal (_("can't find opcode "));
+	  fixups = fixups->next;
+	  str = str2 + 2;
+	}
+    }
+
+  insn = do_assemble (str, &opcode);
+  if (insn == (unsigned long) -1)
+    {
+      if (extype != PACK_UNSPEC)
+	{
+	  etype = extype;
+	  return;
+	}
+      as_fatal (_("can't find opcode "));
+    }
+
+  if (etype != PACK_UNSPEC)
+    {
+      extype = etype;
+      etype = PACK_UNSPEC;
+    }
+
+  /* If this is a long instruction, write it and any previous short
+     instruction.  */
+  if (opcode->format & LONG_OPCODE)
+    {
+      if (extype != PACK_UNSPEC)
+	as_fatal (_("Unable to mix instructions as specified"));
+      d10v_cleanup ();
+      write_long (insn, fixups);
+      prev_opcode = NULL;
+      return;
+    }
+
+  if (prev_opcode
+      && prev_seg
+      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
+    d10v_cleanup ();
+
+  if (prev_opcode
+      && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
+			      fixups)))
+    {
+      /* No instructions saved.  */
+      prev_opcode = NULL;
+    }
+  else
+    {
+      if (extype != PACK_UNSPEC)
+	as_fatal (_("Unable to mix instructions as specified"));
+      /* Save last instruction so it may be packed on next pass.  */
+      prev_opcode = opcode;
+      prev_insn = insn;
+      prev_seg = now_seg;
+      prev_subseg = now_subseg;
+      fixups = fixups->next;
+    }
+}
+
diff --git a/gas/config/tc-d10v.h b/gas/config/tc-d10v.h
index debb799b95cf..f9a30b414710 100644
--- a/gas/config/tc-d10v.h
+++ b/gas/config/tc-d10v.h
@@ -1,5 +1,5 @@
 /* tc-d10v.h -- Header file for tc-d10v.c.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
    Written by Martin Hunt, Cygnus Support.
 
@@ -17,51 +17,51 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_D10V
 
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-#ifndef BFD_ASSEMBLER
- #error D10V support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH bfd_arch_d10v
 
 #define TARGET_FORMAT "elf32-d10v"
 
 /* Call md_pcrel_from_section, not md_pcrel_from.  */
-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
 struct fix;
-long md_pcrel_from_section PARAMS ((struct fix *, segT));
+long md_pcrel_from_section (struct fix *, segT);
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
 #define md_number_to_chars	     number_to_chars_bigendian
 
-int d10v_cleanup PARAMS ((void));
+int d10v_cleanup (void);
 #define md_after_pass_hook()	     d10v_cleanup ()
 #define md_cleanup()		     d10v_cleanup ()
 #define md_do_align(a,b,c,d,e)	     d10v_cleanup ()
-#define tc_frob_label(sym) do {\
-  d10v_cleanup (); \
-  symbol_set_frag (sym, frag_now);					\
-  S_SET_VALUE (sym, (valueT) frag_now_fix ());				\
-} while (0)
+#define tc_frob_label(sym)				\
+  do							\
+    {							\
+      d10v_cleanup ();					\
+      symbol_set_frag (sym, frag_now);			\
+      S_SET_VALUE (sym, (valueT) frag_now_fix ());	\
+    }							\
+  while (0)
 
 #define tc_fix_adjustable(FIX) d10v_fix_adjustable(FIX)
-bfd_boolean d10v_fix_adjustable PARAMS ((struct fix *));
+bfd_boolean d10v_fix_adjustable (struct fix *);
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
diff --git a/gas/config/tc-d30v.c b/gas/config/tc-d30v.c
index 7507c46cf3ed..848ad0341f09 100644
--- a/gas/config/tc-d30v.c
+++ b/gas/config/tc-d30v.c
@@ -1,5 +1,6 @@
 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
-   Copyright 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -24,12 +25,12 @@
 #include "subsegs.h"
 #include "opcode/d30v.h"
 
-const char comment_chars[] = ";";
-const char line_comment_chars[] = "#";
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
 const char line_separator_chars[] = "";
-const char *md_shortopts = "OnNcC";
-const char EXP_CHARS[] = "eE";
-const char FLT_CHARS[] = "dD";
+const char *md_shortopts          = "OnNcC";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
 
 #if HAVE_LIMITS_H
 #include <limits.h>
@@ -51,14 +52,15 @@ static int warn_register_name_conflicts = 1;
 /* EXEC types.  */
 typedef enum _exec_type
 {
-  EXEC_UNKNOWN,			/* no order specified */
-  EXEC_PARALLEL,		/* done in parallel (FM=00) */
-  EXEC_SEQ,			/* sequential (FM=01) */
-  EXEC_REVSEQ			/* reverse sequential (FM=10) */
+  EXEC_UNKNOWN,			/* No order specified.  */
+  EXEC_PARALLEL,		/* Done in parallel (FM=00).  */
+  EXEC_SEQ,			/* Sequential (FM=01).  */
+  EXEC_REVSEQ			/* Reverse sequential (FM=10).  */
 } exec_type_enum;
 
 /* Fixups.  */
-#define MAX_INSN_FIXUPS (5)
+#define MAX_INSN_FIXUPS  5
+
 struct d30v_fixup
 {
   expressionS exp;
@@ -109,34 +111,6 @@ static symbolS *d30v_last_label;
 #define NOP_RIGHT  ((long long) NOP)
 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
 
-/* Local functions.  */
-static int reg_name_search PARAMS ((char *name));
-static int register_name PARAMS ((expressionS *expressionP));
-static int check_range PARAMS ((unsigned long num, int bits, int flags));
-static int postfix PARAMS ((char *p));
-static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag));
-static int get_operands PARAMS ((expressionS exp[], int cmp_hack));
-static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode,
-			expressionS ops[],int fsize, int cmp_hack));
-static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers));
-static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx));
-static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn,
-				   Fixups *fx, int use_sequential));
-static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1,
-		   struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx));
-static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode,
-				      int shortp, int is_parallel));
-static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1,
-				struct d30v_insn *opcode2, unsigned long insn2,
-				exec_type_enum exec_type));
-static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes));
-static void check_size PARAMS ((long value, int bits, char *file, int line));
-static void d30v_align PARAMS ((int, char *, symbolS *));
-static void s_d30v_align PARAMS ((int));
-static void s_d30v_text PARAMS ((int));
-static void s_d30v_data PARAMS ((int));
-static void s_d30v_section PARAMS ((int));
-
 struct option md_longopts[] =
 {
   {NULL, no_argument, NULL, 0}
@@ -144,21 +118,6 @@ struct option md_longopts[] =
 
 size_t md_longopts_size = sizeof (md_longopts);
 
-/* The target specific pseudo-ops which we support.  */
-const pseudo_typeS md_pseudo_table[] =
-{
-  { "word", cons, 4 },
-  { "hword", cons, 2 },
-  { "align", s_d30v_align, 0 },
-  { "text", s_d30v_text, 0 },
-  { "data", s_d30v_data, 0 },
-  { "section", s_d30v_section, 0 },
-  { "section.s", s_d30v_section, 0 },
-  { "sect", s_d30v_section, 0 },
-  { "sect.s", s_d30v_section, 0 },
-  { NULL, NULL, 0 }
-};
-
 /* Opcode hash table.  */
 static struct hash_control *d30v_hash;
 
@@ -167,8 +126,7 @@ static struct hash_control *d30v_hash;
    array on success, or -1 on failure.  */
 
 static int
-reg_name_search (name)
-     char *name;
+reg_name_search (char *name)
 {
   int middle, low, high;
   int cmp;
@@ -205,8 +163,7 @@ reg_name_search (name)
    register name.  */
 
 static int
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char c, *p = input_line_pointer;
@@ -235,10 +192,7 @@ register_name (expressionP)
 }
 
 static int
-check_range (num, bits, flags)
-     unsigned long num;
-     int bits;
-     int flags;
+check_range (unsigned long num, int bits, int flags)
 {
   long min, max;
 
@@ -281,8 +235,7 @@ check_range (num, bits, flags)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\nD30V options:\n\
 -O                      Make adjacent short instructions parallel if possible.\n\
@@ -293,9 +246,7 @@ md_show_usage (stream)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -330,8 +281,7 @@ md_parse_option (c, arg)
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -342,10 +292,7 @@ md_undefined_symbol (name)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -380,25 +327,22 @@ md_atof (type, litP, sizeP)
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
 {
   abort ();
 }
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   struct d30v_opcode *opcode;
   d30v_hash = hash_new ();
@@ -418,8 +362,7 @@ md_begin ()
    from an expression.  */
 
 static int
-postfix (p)
-     char *p;
+postfix (char *p)
 {
   while (*p != '-' && *p != '+')
     {
@@ -444,9 +387,7 @@ postfix (p)
 }
 
 static bfd_reloc_code_real_type
-get_reloc (op, rel_flag)
-     struct d30v_operand *op;
-     int rel_flag;
+get_reloc (struct d30v_operand *op, int rel_flag)
 {
   switch (op->bits)
     {
@@ -483,9 +424,7 @@ get_reloc (op, rel_flag)
 /* Parse a string of operands and return an array of expressions.  */
 
 static int
-get_operands (exp, cmp_hack)
-     expressionS exp[];
-     int cmp_hack;
+get_operands (expressionS exp[], int cmp_hack)
 {
   char *p = input_line_pointer;
   int numops = 0;
@@ -578,9 +517,7 @@ get_operands (exp, cmp_hack)
    It does everything but write the FM bits.  */
 
 static long long
-build_insn (opcode, opers)
-     struct d30v_insn *opcode;
-     expressionS *opers;
+build_insn (struct d30v_insn *opcode, expressionS *opers)
 {
   int i, length, bits, shift, flags;
   unsigned long number, id = 0;
@@ -620,16 +557,13 @@ build_insn (opcode, opers)
 	      number = 0;
 	    }
 	  else if (number & OPERAND_FLAG)
-	    {
-	      /* NUMBER is a flag register.  */
-	      id = 3;
-	    }
+	    /* NUMBER is a flag register.  */
+	    id = 3;
+
 	  number &= 0x7F;
 	}
       else if (flags & OPERAND_SPECIAL)
-	{
-	  number = id;
-	}
+	number = id;
 
       if (opers[i].X_op != O_register && opers[i].X_op != O_constant
 	  && !(flags & OPERAND_NAME))
@@ -660,10 +594,10 @@ build_insn (opcode, opers)
       if (bits == 32)
 	{
 	  /* It's a LONG instruction.  */
-	  insn |= ((number & 0xffffffff) >> 26);	/* top 6 bits */
-	  insn <<= 32;			/* shift the first word over */
-	  insn |= ((number & 0x03FC0000) << 2);		/* next 8 bits */
-	  insn |= number & 0x0003FFFF;			/* bottom 18 bits */
+	  insn |= ((number & 0xffffffff) >> 26);	/* Top 6 bits.  */
+	  insn <<= 32;			/* Shift the first word over.  */
+	  insn |= ((number & 0x03FC0000) << 2);		/* Next 8 bits.  */
+	  insn |= number & 0x0003FFFF;			/* Bottom 18 bits.  */
 	}
       else
 	insn |= number << shift;
@@ -672,13 +606,24 @@ build_insn (opcode, opers)
   return insn;
 }
 
+static void
+d30v_number_to_chars (char *buf,	/* Return 'nbytes' of chars here.  */
+		      long long value,	/* The value of the bits.  */
+		      int n)		/* Number of bytes in the output.  */
+{
+  while (n--)
+    {
+      buf[n] = value & 0xff;
+      value >>= 8;
+    }
+}
+
 /* Write out a long form instruction.  */
 
 static void
-write_long (opcode, insn, fx)
-     struct d30v_insn *opcode ATTRIBUTE_UNUSED;
-     long long insn;
-     Fixups *fx;
+write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
+	    long long insn,
+	    Fixups *fx)
 {
   int i, where;
   char *f = frag_more (8);
@@ -691,12 +636,8 @@ write_long (opcode, insn, fx)
       if (fx->fix[i].reloc)
 	{
 	  where = f - frag_now->fr_literal;
-	  fix_new_exp (frag_now,
-		       where,
-		       fx->fix[i].size,
-		       &(fx->fix[i].exp),
-		       fx->fix[i].pcrel,
-		       fx->fix[i].reloc);
+	  fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
+		       fx->fix[i].pcrel, fx->fix[i].reloc);
 	}
     }
 
@@ -706,11 +647,10 @@ write_long (opcode, insn, fx)
 /* Write out a short form instruction by itself.  */
 
 static void
-write_1_short (opcode, insn, fx, use_sequential)
-     struct d30v_insn *opcode;
-     long long insn;
-     Fixups *fx;
-     int use_sequential;
+write_1_short (struct d30v_insn *opcode,
+	       long long insn,
+	       Fixups *fx,
+	       int use_sequential)
 {
   char *f = frag_more (8);
   int i, where;
@@ -728,7 +668,6 @@ write_1_short (opcode, insn, fx, use_sequential)
 
       /* According to 4.3.1: for FM=01, sub-instructions performed
 	 only by IU cannot be encoded in L-container.  */
-
       if (opcode->op->unit == IU)
 	/* Right then left.  */
 	insn |= FM10 | NOP_LEFT;
@@ -740,7 +679,6 @@ write_1_short (opcode, insn, fx, use_sequential)
     {
       /* According to 4.3.1: for FM=00, sub-instructions performed
 	 only by IU cannot be encoded in L-container.  */
-
       if (opcode->op->unit == IU)
 	/* Right container.  */
 	insn |= FM00 | NOP_LEFT;
@@ -768,208 +706,15 @@ write_1_short (opcode, insn, fx, use_sequential)
   fx->fc = 0;
 }
 
-/* Write out a short form instruction if possible.
-   Return number of instructions not written out.  */
-
-static int
-write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
-     struct d30v_insn *opcode1, *opcode2;
-     long long insn1, insn2;
-     exec_type_enum exec_type;
-     Fixups *fx;
-{
-  long long insn = NOP2;
-  char *f;
-  int i, j, where;
-
-  if (exec_type == EXEC_SEQ
-      && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
-      && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
-      && ((opcode1->ecc == ECC_AL) || ! Optimizing))
-    {
-      /* Unconditional, non-delayed branches kill instructions in
-	 the right bin.  Conditional branches don't always but if
-	 we are not optimizing, then we have been asked to produce
-	 an error about such constructs.  For the purposes of this
-	 test, subroutine calls are considered to be branches.  */
-      write_1_short (opcode1, insn1, fx->next, FALSE);
-      return 1;
-    }
-
-  /* Note: we do not have to worry about subroutine calls occurring
-     in the right hand container.  The return address is always
-     aligned to the next 64 bit boundary, be that 64 or 32 bit away.  */
-  switch (exec_type)
-    {
-    case EXEC_UNKNOWN:	/* Order not specified.  */
-      if (Optimizing
-	  && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
-	  && ! (   (opcode1->op->unit == EITHER_BUT_PREFER_MU
-		 || opcode1->op->unit == MU)
-		&&
-		(   opcode2->op->unit == EITHER_BUT_PREFER_MU
-		 || opcode2->op->unit == MU)))
-	{
-	  /* Parallel.  */
-	  exec_type = EXEC_PARALLEL;
-
-	  if (opcode1->op->unit == IU
-	      || opcode2->op->unit == MU
-	      || opcode2->op->unit == EITHER_BUT_PREFER_MU)
-	    insn = FM00 | (insn2 << 32) | insn1;
-	  else
-	    {
-	      insn = FM00 | (insn1 << 32) | insn2;
-	      fx = fx->next;
-	    }
-	}
-      else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
-		&& ((opcode1->op->flags_used & FLAG_DELAY) == 0))
-	       || opcode1->op->flags_used & FLAG_RP)
-	{
-	  /* We must emit (non-delayed) branch type instructions
-	     on their own with nothing in the right container.  */
-	  /* We must treat repeat instructions likewise, since the
-	     following instruction has to be separate from the repeat
-	     in order to be repeated.  */
-	  write_1_short (opcode1, insn1, fx->next, FALSE);
-	  return 1;
-	}
-      else if (prev_left_kills_right_p)
-	{
-	  /* The left instruction kils the right slot, so we
-	     must leave it empty.  */
-	  write_1_short (opcode1, insn1, fx->next, FALSE);
-	  return 1;
-	}
-      else if (opcode1->op->unit == IU)
-	{
-	  if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
-	    {
-	      /* Case 103810 is a request from Mitsubishi that opcodes
-		 with EITHER_BUT_PREFER_MU should not be executed in
-		 reverse sequential order.  */
-	      write_1_short (opcode1, insn1, fx->next, FALSE);
-	      return 1;
-	    }
-
-	  /* Reverse sequential.  */
-	  insn = FM10 | (insn2 << 32) | insn1;
-	  exec_type = EXEC_REVSEQ;
-	}
-      else
-	{
-	  /* Sequential.  */
-	  insn = FM01 | (insn1 << 32) | insn2;
-	  fx = fx->next;
-	  exec_type = EXEC_SEQ;
-	}
-      break;
-
-    case EXEC_PARALLEL:	/* Parallel.  */
-      flag_explicitly_parallel = flag_xp_state;
-      if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
-	as_bad (_("Instructions may not be executed in parallel"));
-      else if (opcode1->op->unit == IU)
-	{
-	  if (opcode2->op->unit == IU)
-	    as_bad (_("Two IU instructions may not be executed in parallel"));
-	  as_warn (_("Swapping instruction order"));
-	  insn = FM00 | (insn2 << 32) | insn1;
-	}
-      else if (opcode2->op->unit == MU)
-	{
-	  if (opcode1->op->unit == MU)
-	    as_bad (_("Two MU instructions may not be executed in parallel"));
-	  else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
-	    as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
-	  as_warn (_("Swapping instruction order"));
-	  insn = FM00 | (insn2 << 32) | insn1;
-	}
-      else
-	{
-	  if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
-	    as_warn (_("Executing %s in IU may not work in parallel execution"),
-		     opcode2->op->name);
-
-	  insn = FM00 | (insn1 << 32) | insn2;
-	  fx = fx->next;
-	}
-      flag_explicitly_parallel = 0;
-      break;
-
-    case EXEC_SEQ:	/* Sequential.  */
-      if (opcode1->op->unit == IU)
-	as_bad (_("IU instruction may not be in the left container"));
-      if (prev_left_kills_right_p)
-	as_bad (_("special left instruction `%s' kills instruction "
-		  "`%s' in right container"),
-		opcode1->op->name, opcode2->op->name);
-      insn = FM01 | (insn1 << 32) | insn2;
-      fx = fx->next;
-      break;
-
-    case EXEC_REVSEQ:	/* Reverse sequential.  */
-      if (opcode2->op->unit == MU)
-	as_bad (_("MU instruction may not be in the right container"));
-      if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
-	as_warn (_("Executing %s in reverse serial with %s may not work"),
-		 opcode1->op->name, opcode2->op->name);
-      else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
-	as_warn (_("Executing %s in IU in reverse serial may not work"),
-		 opcode2->op->name);
-      insn = FM10 | (insn1 << 32) | insn2;
-      fx = fx->next;
-      break;
-
-    default:
-      as_fatal (_("unknown execution type passed to write_2_short()"));
-    }
-
-#if 0
-  printf ("writing out %llx\n", insn);
-#endif
-  f = frag_more (8);
-  d30v_number_to_chars (f, insn, 8);
-
-  /* If the previous instruction was a 32-bit multiply but it is put into a
-     parallel container, mark the current instruction as being a 32-bit
-     multiply.  */
-  if (prev_mul32_p && exec_type == EXEC_PARALLEL)
-    cur_mul32_p = 1;
-
-  for (j = 0; j < 2; j++)
-    {
-      for (i = 0; i < fx->fc; i++)
-	{
-	  if (fx->fix[i].reloc)
-	    {
-	      where = (f - frag_now->fr_literal) + 4 * j;
-
-	      fix_new_exp (frag_now,
-			   where,
-			   fx->fix[i].size,
-			   &(fx->fix[i].exp),
-			   fx->fix[i].pcrel,
-			   fx->fix[i].reloc);
-	    }
-	}
-
-      fx->fc = 0;
-      fx = fx->next;
-    }
-
-  return 0;
-}
-
 /* Check 2 instructions and determine if they can be safely
    executed in parallel.  Return 1 if they can be.  */
 
 static int
-parallel_ok (op1, insn1, op2, insn2, exec_type)
-     struct d30v_insn *op1, *op2;
-     unsigned long insn1, insn2;
-     exec_type_enum exec_type;
+parallel_ok (struct d30v_insn *op1,
+	     unsigned long insn1,
+	     struct d30v_insn *op2,
+	     unsigned long insn2,
+	     exec_type_enum exec_type)
 {
   int i, j, shift, regno, bits, ecc;
   unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
@@ -1217,206 +962,352 @@ parallel_ok (op1, insn1, op2, insn2, exec_type)
   return 1;
 }
 
-/* This is the main entry point for the machine-dependent assembler.
-   STR points to a machine-dependent instruction.  This function is
-   supposed to emit the frags/bytes it assembles to.  For the D30V, it
-   mostly handles the special VLIW parsing and packing and leaves the
-   difficult stuff to do_assemble ().  */
-
-static long long prev_insn = -1;
-static struct d30v_insn prev_opcode;
-static subsegT prev_subseg;
-static segT prev_seg = 0;
+/* Write out a short form instruction if possible.
+   Return number of instructions not written out.  */
 
-void
-md_assemble (str)
-     char *str;
+static int
+write_2_short (struct d30v_insn *opcode1,
+	       long long insn1,
+	       struct d30v_insn *opcode2,
+	       long long insn2,
+	       exec_type_enum exec_type,
+	       Fixups *fx)
 {
-  struct d30v_insn opcode;
-  long long insn;
-  /* Execution type; parallel, etc.  */
-  exec_type_enum extype = EXEC_UNKNOWN;
-  /* Saved extype.  Used for multiline instructions.  */
-  static exec_type_enum etype = EXEC_UNKNOWN;
-  char *str2;
-
-  if ((prev_insn != -1) && prev_seg
-      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
-    d30v_cleanup (FALSE);
+  long long insn = NOP2;
+  char *f;
+  int i, j, where;
 
-  if (d30v_current_align < 3)
-    d30v_align (3, NULL, d30v_last_label);
-  else if (d30v_current_align > 3)
-    d30v_current_align = 3;
-  d30v_last_label = NULL;
+  if (exec_type == EXEC_SEQ
+      && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
+      && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
+      && ((opcode1->ecc == ECC_AL) || ! Optimizing))
+    {
+      /* Unconditional, non-delayed branches kill instructions in
+	 the right bin.  Conditional branches don't always but if
+	 we are not optimizing, then we have been asked to produce
+	 an error about such constructs.  For the purposes of this
+	 test, subroutine calls are considered to be branches.  */
+      write_1_short (opcode1, insn1, fx->next, FALSE);
+      return 1;
+    }
 
-  flag_explicitly_parallel = 0;
-  flag_xp_state = 0;
-  if (etype == EXEC_UNKNOWN)
+  /* Note: we do not have to worry about subroutine calls occurring
+     in the right hand container.  The return address is always
+     aligned to the next 64 bit boundary, be that 64 or 32 bit away.  */
+  switch (exec_type)
     {
-      /* Look for the special multiple instruction separators.  */
-      str2 = strstr (str, "||");
-      if (str2)
-	{
-	  extype = EXEC_PARALLEL;
-	  flag_xp_state = 1;
-	}
-      else
+    case EXEC_UNKNOWN:	/* Order not specified.  */
+      if (Optimizing
+	  && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
+	  && ! (   (opcode1->op->unit == EITHER_BUT_PREFER_MU
+		 || opcode1->op->unit == MU)
+		&&
+		(   opcode2->op->unit == EITHER_BUT_PREFER_MU
+		 || opcode2->op->unit == MU)))
 	{
-	  str2 = strstr (str, "->");
-	  if (str2)
-	    extype = EXEC_SEQ;
+	  /* Parallel.  */
+	  exec_type = EXEC_PARALLEL;
+
+	  if (opcode1->op->unit == IU
+	      || opcode2->op->unit == MU
+	      || opcode2->op->unit == EITHER_BUT_PREFER_MU)
+	    insn = FM00 | (insn2 << 32) | insn1;
 	  else
 	    {
-	      str2 = strstr (str, "<-");
-	      if (str2)
-		extype = EXEC_REVSEQ;
+	      insn = FM00 | (insn1 << 32) | insn2;
+	      fx = fx->next;
 	    }
 	}
+      else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
+		&& ((opcode1->op->flags_used & FLAG_DELAY) == 0))
+	       || opcode1->op->flags_used & FLAG_RP)
+	{
+	  /* We must emit (non-delayed) branch type instructions
+	     on their own with nothing in the right container.  */
+	  /* We must treat repeat instructions likewise, since the
+	     following instruction has to be separate from the repeat
+	     in order to be repeated.  */
+	  write_1_short (opcode1, insn1, fx->next, FALSE);
+	  return 1;
+	}
+      else if (prev_left_kills_right_p)
+	{
+	  /* The left instruction kils the right slot, so we
+	     must leave it empty.  */
+	  write_1_short (opcode1, insn1, fx->next, FALSE);
+	  return 1;
+	}
+      else if (opcode1->op->unit == IU)
+	{
+	  if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+	    {
+	      /* Case 103810 is a request from Mitsubishi that opcodes
+		 with EITHER_BUT_PREFER_MU should not be executed in
+		 reverse sequential order.  */
+	      write_1_short (opcode1, insn1, fx->next, FALSE);
+	      return 1;
+	    }
 
-      /* STR2 points to the separator, if one.  */
-      if (str2)
+	  /* Reverse sequential.  */
+	  insn = FM10 | (insn2 << 32) | insn1;
+	  exec_type = EXEC_REVSEQ;
+	}
+      else
 	{
-	  *str2 = 0;
+	  /* Sequential.  */
+	  insn = FM01 | (insn1 << 32) | insn2;
+	  fx = fx->next;
+	  exec_type = EXEC_SEQ;
+	}
+      break;
 
-	  /* If two instructions are present and we already have one saved,
-	     then first write it out.  */
-	  d30v_cleanup (FALSE);
+    case EXEC_PARALLEL:	/* Parallel.  */
+      flag_explicitly_parallel = flag_xp_state;
+      if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
+	as_bad (_("Instructions may not be executed in parallel"));
+      else if (opcode1->op->unit == IU)
+	{
+	  if (opcode2->op->unit == IU)
+	    as_bad (_("Two IU instructions may not be executed in parallel"));
+	  as_warn (_("Swapping instruction order"));
+	  insn = FM00 | (insn2 << 32) | insn1;
+	}
+      else if (opcode2->op->unit == MU)
+	{
+	  if (opcode1->op->unit == MU)
+	    as_bad (_("Two MU instructions may not be executed in parallel"));
+	  else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
+	    as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
+	  as_warn (_("Swapping instruction order"));
+	  insn = FM00 | (insn2 << 32) | insn1;
+	}
+      else
+	{
+	  if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+	    as_warn (_("Executing %s in IU may not work in parallel execution"),
+		     opcode2->op->name);
 
-	  /* Assemble first instruction and save it.  */
-	  prev_insn = do_assemble (str, &prev_opcode, 1, 0);
-	  if (prev_insn == -1)
-	    as_bad (_("Cannot assemble instruction"));
-	  if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
-	    as_bad (_("First opcode is long.  Unable to mix instructions as specified."));
-	  fixups = fixups->next;
-	  str = str2 + 2;
-	  prev_seg = now_seg;
-	  prev_subseg = now_subseg;
+	  insn = FM00 | (insn1 << 32) | insn2;
+	  fx = fx->next;
 	}
-    }
+      flag_explicitly_parallel = 0;
+      break;
 
-  insn = do_assemble (str, &opcode,
-		      (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
-		      extype == EXEC_PARALLEL);
-  if (insn == -1)
-    {
-      if (extype != EXEC_UNKNOWN)
-	etype = extype;
-      as_bad (_("Cannot assemble instruction"));
-      return;
-    }
+    case EXEC_SEQ:	/* Sequential.  */
+      if (opcode1->op->unit == IU)
+	as_bad (_("IU instruction may not be in the left container"));
+      if (prev_left_kills_right_p)
+	as_bad (_("special left instruction `%s' kills instruction "
+		  "`%s' in right container"),
+		opcode1->op->name, opcode2->op->name);
+      insn = FM01 | (insn1 << 32) | insn2;
+      fx = fx->next;
+      break;
 
-  if (etype != EXEC_UNKNOWN)
-    {
-      extype = etype;
-      etype = EXEC_UNKNOWN;
+    case EXEC_REVSEQ:	/* Reverse sequential.  */
+      if (opcode2->op->unit == MU)
+	as_bad (_("MU instruction may not be in the right container"));
+      if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
+	as_warn (_("Executing %s in reverse serial with %s may not work"),
+		 opcode1->op->name, opcode2->op->name);
+      else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
+	as_warn (_("Executing %s in IU in reverse serial may not work"),
+		 opcode2->op->name);
+      insn = FM10 | (insn1 << 32) | insn2;
+      fx = fx->next;
+      break;
+
+    default:
+      as_fatal (_("unknown execution type passed to write_2_short()"));
     }
 
-  /* Word multiply instructions must not be followed by either a load or a
-     16-bit multiply instruction in the next cycle.  */
-  if (   (extype != EXEC_REVSEQ)
-      && prev_mul32_p
-      && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
+  f = frag_more (8);
+  d30v_number_to_chars (f, insn, 8);
+
+  /* If the previous instruction was a 32-bit multiply but it is put into a
+     parallel container, mark the current instruction as being a 32-bit
+     multiply.  */
+  if (prev_mul32_p && exec_type == EXEC_PARALLEL)
+    cur_mul32_p = 1;
+
+  for (j = 0; j < 2; j++)
     {
-      /* However, load and multiply should able to be combined in a parallel
-	 operation, so check for that first.  */
-      if (prev_insn != -1
-	  && (opcode.op->flags_used & FLAG_MEM)
-	  && opcode.form->form < LONG
-	  && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
-	  && parallel_ok (&prev_opcode, (long) prev_insn,
-			  &opcode, (long) insn, extype)
-	  && write_2_short (&prev_opcode, (long) prev_insn,
-			    &opcode, (long) insn, extype, fixups) == 0)
+      for (i = 0; i < fx->fc; i++)
 	{
-	  /* No instructions saved.  */
-	  prev_insn = -1;
-	  return;
+	  if (fx->fix[i].reloc)
+	    {
+	      where = (f - frag_now->fr_literal) + 4 * j;
+
+	      fix_new_exp (frag_now,
+			   where,
+			   fx->fix[i].size,
+			   &(fx->fix[i].exp),
+			   fx->fix[i].pcrel,
+			   fx->fix[i].reloc);
+	    }
 	}
-      else
-	{
-	  /* Can't parallelize, flush previous instruction and emit a
-	     word of NOPS, unless the previous instruction is a NOP,
-	     in which case just flush it, as this will generate a word
-	     of NOPs for us.  */
 
-	  if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
-	    d30v_cleanup (FALSE);
-	  else
+      fx->fc = 0;
+      fx = fx->next;
+    }
+
+  return 0;
+}
+
+/* Get a pointer to an entry in the format table.
+   It must look at all formats for an opcode and use the operands
+   to choose the correct one.  Return NULL on error.  */
+
+static struct d30v_format *
+find_format (struct d30v_opcode *opcode,
+	     expressionS myops[],
+	     int fsize,
+	     int cmp_hack)
+{
+  int numops, match, index, i = 0, j, k;
+  struct d30v_format *fm;
+
+  if (opcode == NULL)
+    return NULL;
+
+  /* Get all the operands and save them as expressions.  */
+  numops = get_operands (myops, cmp_hack);
+
+  while ((index = opcode->format[i++]) != 0)
+    {
+      if (fsize == FORCE_SHORT && index >= LONG)
+	continue;
+
+      if (fsize == FORCE_LONG && index < LONG)
+	continue;
+
+      fm = (struct d30v_format *) &d30v_format_table[index];
+      k = index;
+      while (fm->form == index)
+	{
+	  match = 1;
+	  /* Now check the operands for compatibility.  */
+	  for (j = 0; match && fm->operands[j]; j++)
 	    {
-	      char *f;
+	      int flags = d30v_operand_table[fm->operands[j]].flags;
+	      int bits = d30v_operand_table[fm->operands[j]].bits;
+	      int X_op = myops[j].X_op;
+	      int num = myops[j].X_add_number;
 
-	      if (prev_insn != -1)
-		d30v_cleanup (TRUE);
-	      else
+	      if (flags & OPERAND_SPECIAL)
+		break;
+	      else if (X_op == O_illegal)
+		match = 0;
+	      else if (flags & OPERAND_REG)
 		{
-		  f = frag_more (8);
-		  d30v_number_to_chars (f, NOP2, 8);
+		  if (X_op != O_register
+		      || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
+		      || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
+		      || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
+		      || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
+		      || ((flags & OPERAND_CONTROL)
+			  && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
+		    match = 0;
+		}
+	      else if (((flags & OPERAND_MINUS)
+			&& (X_op != O_absent || num != OPERAND_MINUS))
+		       || ((flags & OPERAND_PLUS)
+			   && (X_op != O_absent || num != OPERAND_PLUS))
+		       || ((flags & OPERAND_ATMINUS)
+			   && (X_op != O_absent || num != OPERAND_ATMINUS))
+		       || ((flags & OPERAND_ATPAR)
+			   && (X_op != O_absent || num != OPERAND_ATPAR))
+		       || ((flags & OPERAND_ATSIGN)
+			   && (X_op != O_absent || num != OPERAND_ATSIGN)))
+		match = 0;
+	      else if (flags & OPERAND_NUM)
+		{
+		  /* A number can be a constant or symbol expression.  */
 
-		  if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
+		  /* If we have found a register name, but that name
+		     also matches a symbol, then re-parse the name as
+		     an expression.  */
+		  if (X_op == O_register
+		      && symbol_find ((char *) myops[j].X_op_symbol))
 		    {
-		      if (opcode.op->flags_used & FLAG_MEM)
-			as_warn (_("word of NOPs added between word multiply and load"));
-		      else
-			as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
+		      input_line_pointer = (char *) myops[j].X_op_symbol;
+		      expression (&myops[j]);
 		    }
-		}
-	    }
 
-	  extype = EXEC_UNKNOWN;
-	}
-    }
-  else if (   (extype == EXEC_REVSEQ)
-	   && cur_mul32_p
-	   && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
-    {
-      /* Can't parallelize, flush current instruction and add a
-         sequential NOP.  */
-      write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
+		  /* Turn an expression into a symbol for later resolution.  */
+		  if (X_op != O_absent && X_op != O_constant
+		      && X_op != O_symbol && X_op != O_register
+		      && X_op != O_big)
+		    {
+		      symbolS *sym = make_expr_symbol (&myops[j]);
+		      myops[j].X_op = X_op = O_symbol;
+		      myops[j].X_add_symbol = sym;
+		      myops[j].X_add_number = num = 0;
+		    }
 
-      /* Make the previous instruction the current one.  */
-      extype = EXEC_UNKNOWN;
-      insn = prev_insn;
-      now_seg = prev_seg;
-      now_subseg = prev_subseg;
-      prev_insn = -1;
-      cur_mul32_p = prev_mul32_p;
-      prev_mul32_p = 0;
-      memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
-    }
+		  if (fm->form >= LONG)
+		    {
+		      /* If we're testing for a LONG format, either fits.  */
+		      if (X_op != O_constant && X_op != O_symbol)
+			match = 0;
+		    }
+		  else if (fm->form < LONG
+			   && ((fsize == FORCE_SHORT && X_op == O_symbol)
+			       || (fm->form == SHORT_D2 && j == 0)))
+		    match = 1;
 
-  /* If this is a long instruction, write it and any previous short
-     instruction.  */
-  if (opcode.form->form >= LONG)
-    {
-      if (extype != EXEC_UNKNOWN)
-	as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
-      d30v_cleanup (FALSE);
-      write_long (&opcode, insn, fixups);
-      prev_insn = -1;
-    }
-  else if ((prev_insn != -1)
-	   && (write_2_short
-	       (&prev_opcode, (long) prev_insn, &opcode,
-		(long) insn, extype, fixups) == 0))
-    {
-      /* No instructions saved.  */
-      prev_insn = -1;
-    }
-  else
-    {
-      if (extype != EXEC_UNKNOWN)
-	as_bad (_("Unable to mix instructions as specified"));
+		  /* This is the tricky part.  Will the constant or symbol
+		     fit into the space in the current format?  */
+		  else if (X_op == O_constant)
+		    {
+		      if (check_range (num, bits, flags))
+			match = 0;
+		    }
+		  else if (X_op == O_symbol
+			   && S_IS_DEFINED (myops[j].X_add_symbol)
+			   && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
+			   && opcode->reloc_flag == RELOC_PCREL)
+		    {
+		      /* If the symbol is defined, see if the value will fit
+			 into the form we're considering.  */
+		      fragS *f;
+		      long value;
 
-      /* Save off last instruction so it may be packed on next pass.  */
-      memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
-      prev_insn = insn;
-      prev_seg = now_seg;
-      prev_subseg = now_subseg;
-      fixups = fixups->next;
-      prev_mul32_p = cur_mul32_p;
+		      /* Calculate the current address by running through the
+			 previous frags and adding our current offset.  */
+		      value = 0;
+		      for (f = frchain_now->frch_root; f; f = f->fr_next)
+			value += f->fr_fix + f->fr_offset;
+		      value = (S_GET_VALUE (myops[j].X_add_symbol) - value
+			       - (obstack_next_free (&frchain_now->frch_obstack)
+				  - frag_now->fr_literal));
+		      if (check_range (value, bits, flags))
+			match = 0;
+		    }
+		  else
+		    match = 0;
+		}
+	    }
+	  /* We're only done if the operands matched so far AND there
+	     are no more to check.  */
+	  if (match && myops[j].X_op == 0)
+	    {
+	      /* Final check - issue a warning if an odd numbered register
+		 is used as the first register in an instruction that reads
+		 or writes 2 registers.  */
+
+	      for (j = 0; fm->operands[j]; j++)
+		if (myops[j].X_op == O_register
+		    && (myops[j].X_add_number & 1)
+		    && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
+		  as_warn (_("Odd numbered register used as target of multi-register instruction"));
+
+	      return fm;
+	    }
+	  fm = (struct d30v_format *) &d30v_format_table[++k];
+	}
     }
+  return NULL;
 }
 
 /* Assemble a single instruction and return an opcode.
@@ -1425,15 +1316,14 @@ md_assemble (str)
 #define NAME_BUF_LEN	20
 
 static long long
-do_assemble (str, opcode, shortp, is_parallel)
-     char *str;
-     struct d30v_insn *opcode;
-     int shortp;
-     int is_parallel;
+do_assemble (char *str,
+	     struct d30v_insn *opcode,
+	     int shortp,
+	     int is_parallel)
 {
-  unsigned char *op_start;
-  unsigned char *save;
-  unsigned char *op_end;
+  char *op_start;
+  char *save;
+  char *op_end;
   char           name[NAME_BUF_LEN];
   int            cmp_hack;
   int            nlen = 0;
@@ -1446,11 +1336,11 @@ do_assemble (str, opcode, shortp, is_parallel)
     str++;
 
   /* Find the opcode end.  */
-  for (op_start = op_end = (unsigned char *) (str);
+  for (op_start = op_end = str;
        *op_end
        && nlen < (NAME_BUF_LEN - 1)
        && *op_end != '/'
-       && !is_end_of_line[*op_end] && *op_end != ' ';
+       && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
        op_end++)
     {
       name[nlen] = TOLOWER (op_start[nlen]);
@@ -1477,9 +1367,6 @@ do_assemble (str, opcode, shortp, is_parallel)
 	  as_bad (_("unknown condition code: %s"), tmp);
 	  return -1;
 	}
-#if 0
-      printf ("condition code=%d\n", i);
-#endif
       opcode->ecc = i;
       op_end += 3;
     }
@@ -1521,10 +1408,6 @@ do_assemble (str, opcode, shortp, is_parallel)
   else
     cmp_hack = 0;
 
-#if 0
-  printf ("cmp_hack=%d\n", cmp_hack);
-#endif
-
   /* Need to look for .s or .l.  */
   if (name[nlen - 2] == '.')
     {
@@ -1619,188 +1502,303 @@ do_assemble (str, opcode, shortp, is_parallel)
   return insn;
 }
 
-/* Get a pointer to an entry in the format table.
-   It must look at all formats for an opcode and use the operands
-   to choose the correct one.  Return NULL on error.  */
+/* Called internally to handle all alignment needs.  This takes care
+   of eliding calls to frag_align if'n the cached current alignment
+   says we've already got it, as well as taking care of the auto-aligning
+   labels wrt code.  */
 
-static struct d30v_format *
-find_format (opcode, myops, fsize, cmp_hack)
-     struct d30v_opcode *opcode;
-     expressionS myops[];
-     int fsize;
-     int cmp_hack;
+static void
+d30v_align (int n, char *pfill, symbolS *label)
 {
-  int numops, match, index, i = 0, j, k;
-  struct d30v_format *fm;
+  /* The front end is prone to changing segments out from under us
+     temporarily when -g is in effect.  */
+  int switched_seg_p = (d30v_current_align_seg != now_seg);
 
-  if (opcode == NULL)
-    return NULL;
+  /* Do not assume that if 'd30v_current_align >= n' and
+     '! switched_seg_p' that it is safe to avoid performing
+     this alignment request.  The alignment of the current frag
+     can be changed under our feet, for example by a .ascii
+     directive in the source code.  cf testsuite/gas/d30v/reloc.s  */
+  d30v_cleanup (FALSE);
 
-  /* Get all the operands and save them as expressions.  */
-  numops = get_operands (myops, cmp_hack);
+  if (pfill == NULL)
+    {
+      if (n > 2
+	  && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+	{
+	  static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
 
-  while ((index = opcode->format[i++]) != 0)
+	  /* First, make sure we're on a four-byte boundary, in case
+	     someone has been putting .byte values the text section.  */
+	  if (d30v_current_align < 2 || switched_seg_p)
+	    frag_align (2, 0, 0);
+	  frag_align_pattern (n, nop, sizeof nop, 0);
+	}
+      else
+	frag_align (n, 0, 0);
+    }
+  else
+    frag_align (n, *pfill, 0);
+
+  if (!switched_seg_p)
+    d30v_current_align = n;
+
+  if (label != NULL)
     {
-      if (fsize == FORCE_SHORT && index >= LONG)
-	continue;
+      symbolS     *sym;
+      int          label_seen = FALSE;
+      struct frag *old_frag;
+      valueT       old_value;
+      valueT       new_value;
 
-      if (fsize == FORCE_LONG && index < LONG)
-	continue;
+      assert (S_GET_SEGMENT (label) == now_seg);
 
-      fm = (struct d30v_format *) &d30v_format_table[index];
-      k = index;
-      while (fm->form == index)
+      old_frag  = symbol_get_frag (label);
+      old_value = S_GET_VALUE (label);
+      new_value = (valueT) frag_now_fix ();
+
+      /* It is possible to have more than one label at a particular
+	 address, especially if debugging is enabled, so we must
+	 take care to adjust all the labels at this address in this
+	 fragment.  To save time we search from the end of the symbol
+	 list, backwards, since the symbols we are interested in are
+	 almost certainly the ones that were most recently added.
+	 Also to save time we stop searching once we have seen at least
+	 one matching label, and we encounter a label that is no longer
+	 in the target fragment.  Note, this search is guaranteed to
+	 find at least one match when sym == label, so no special case
+	 code is necessary.  */
+      for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
 	{
-	  match = 1;
-	  /* Now check the operands for compatibility.  */
-	  for (j = 0; match && fm->operands[j]; j++)
+	  if (symbol_get_frag (sym) == old_frag
+	      && S_GET_VALUE (sym) == old_value)
 	    {
-	      int flags = d30v_operand_table[fm->operands[j]].flags;
-	      int bits = d30v_operand_table[fm->operands[j]].bits;
-	      int X_op = myops[j].X_op;
-	      int num = myops[j].X_add_number;
+	      label_seen = TRUE;
+	      symbol_set_frag (sym, frag_now);
+	      S_SET_VALUE (sym, new_value);
+	    }
+	  else if (label_seen && symbol_get_frag (sym) != old_frag)
+	    break;
+	}
+    }
 
-	      if (flags & OPERAND_SPECIAL)
-		break;
-	      else if (X_op == O_illegal)
-		match = 0;
-	      else if (flags & OPERAND_REG)
-		{
-		  if (X_op != O_register
-		      || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
-		      || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
-		      || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
-		      || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
-		      || ((flags & OPERAND_CONTROL)
-			  && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
-		    {
-		      match = 0;
-		    }
-		}
-	      else if (((flags & OPERAND_MINUS)
-			&& (X_op != O_absent || num != OPERAND_MINUS))
-		       || ((flags & OPERAND_PLUS)
-			   && (X_op != O_absent || num != OPERAND_PLUS))
-		       || ((flags & OPERAND_ATMINUS)
-			   && (X_op != O_absent || num != OPERAND_ATMINUS))
-		       || ((flags & OPERAND_ATPAR)
-			   && (X_op != O_absent || num != OPERAND_ATPAR))
-		       || ((flags & OPERAND_ATSIGN)
-			   && (X_op != O_absent || num != OPERAND_ATSIGN)))
-		{
-		  match = 0;
-		}
-	      else if (flags & OPERAND_NUM)
-		{
-		  /* A number can be a constant or symbol expression.  */
+  record_alignment (now_seg, n);
+}
 
-		  /* If we have found a register name, but that name
-		     also matches a symbol, then re-parse the name as
-		     an expression.  */
-		  if (X_op == O_register
-		      && symbol_find ((char *) myops[j].X_op_symbol))
-		    {
-		      input_line_pointer = (char *) myops[j].X_op_symbol;
-		      expression (&myops[j]);
-		    }
+/* This is the main entry point for the machine-dependent assembler.
+   STR points to a machine-dependent instruction.  This function is
+   supposed to emit the frags/bytes it assembles to.  For the D30V, it
+   mostly handles the special VLIW parsing and packing and leaves the
+   difficult stuff to do_assemble ().  */
 
-		  /* Turn an expression into a symbol for later resolution.  */
-		  if (X_op != O_absent && X_op != O_constant
-		      && X_op != O_symbol && X_op != O_register
-		      && X_op != O_big)
-		    {
-		      symbolS *sym = make_expr_symbol (&myops[j]);
-		      myops[j].X_op = X_op = O_symbol;
-		      myops[j].X_add_symbol = sym;
-		      myops[j].X_add_number = num = 0;
-		    }
+static long long prev_insn = -1;
+static struct d30v_insn prev_opcode;
+static subsegT prev_subseg;
+static segT prev_seg = 0;
 
-		  if (fm->form >= LONG)
-		    {
-		      /* If we're testing for a LONG format, either fits.  */
-		      if (X_op != O_constant && X_op != O_symbol)
-			match = 0;
-		    }
-		  else if (fm->form < LONG
-			   && ((fsize == FORCE_SHORT && X_op == O_symbol)
-			       || (fm->form == SHORT_D2 && j == 0)))
-		    match = 1;
+void
+md_assemble (char *str)
+{
+  struct d30v_insn opcode;
+  long long insn;
+  /* Execution type; parallel, etc.  */
+  exec_type_enum extype = EXEC_UNKNOWN;
+  /* Saved extype.  Used for multiline instructions.  */
+  static exec_type_enum etype = EXEC_UNKNOWN;
+  char *str2;
 
-		  /* This is the tricky part.  Will the constant or symbol
-		     fit into the space in the current format?  */
-		  else if (X_op == O_constant)
-		    {
-		      if (check_range (num, bits, flags))
-			match = 0;
-		    }
-		  else if (X_op == O_symbol
-			   && S_IS_DEFINED (myops[j].X_add_symbol)
-			   && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
-			   && opcode->reloc_flag == RELOC_PCREL)
-		    {
-		      /* If the symbol is defined, see if the value will fit
-			 into the form we're considering.  */
-		      fragS *f;
-		      long value;
+  if ((prev_insn != -1) && prev_seg
+      && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
+    d30v_cleanup (FALSE);
 
-		      /* Calculate the current address by running through the
-			 previous frags and adding our current offset.  */
-		      value = 0;
-		      for (f = frchain_now->frch_root; f; f = f->fr_next)
-			value += f->fr_fix + f->fr_offset;
-		      value = (S_GET_VALUE (myops[j].X_add_symbol) - value
-			       - (obstack_next_free (&frchain_now->frch_obstack)
-				  - frag_now->fr_literal));
-		      if (check_range (value, bits, flags))
-			match = 0;
-		    }
-		  else
-		    match = 0;
-		}
+  if (d30v_current_align < 3)
+    d30v_align (3, NULL, d30v_last_label);
+  else if (d30v_current_align > 3)
+    d30v_current_align = 3;
+  d30v_last_label = NULL;
+
+  flag_explicitly_parallel = 0;
+  flag_xp_state = 0;
+  if (etype == EXEC_UNKNOWN)
+    {
+      /* Look for the special multiple instruction separators.  */
+      str2 = strstr (str, "||");
+      if (str2)
+	{
+	  extype = EXEC_PARALLEL;
+	  flag_xp_state = 1;
+	}
+      else
+	{
+	  str2 = strstr (str, "->");
+	  if (str2)
+	    extype = EXEC_SEQ;
+	  else
+	    {
+	      str2 = strstr (str, "<-");
+	      if (str2)
+		extype = EXEC_REVSEQ;
 	    }
-#if 0
-	  printf ("through the loop: match=%d\n", match);
-#endif
-	  /* We're only done if the operands matched so far AND there
-	     are no more to check.  */
-	  if (match && myops[j].X_op == 0)
+	}
+
+      /* STR2 points to the separator, if one.  */
+      if (str2)
+	{
+	  *str2 = 0;
+
+	  /* If two instructions are present and we already have one saved,
+	     then first write it out.  */
+	  d30v_cleanup (FALSE);
+
+	  /* Assemble first instruction and save it.  */
+	  prev_insn = do_assemble (str, &prev_opcode, 1, 0);
+	  if (prev_insn == -1)
+	    as_bad (_("Cannot assemble instruction"));
+	  if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
+	    as_bad (_("First opcode is long.  Unable to mix instructions as specified."));
+	  fixups = fixups->next;
+	  str = str2 + 2;
+	  prev_seg = now_seg;
+	  prev_subseg = now_subseg;
+	}
+    }
+
+  insn = do_assemble (str, &opcode,
+		      (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
+		      extype == EXEC_PARALLEL);
+  if (insn == -1)
+    {
+      if (extype != EXEC_UNKNOWN)
+	etype = extype;
+      as_bad (_("Cannot assemble instruction"));
+      return;
+    }
+
+  if (etype != EXEC_UNKNOWN)
+    {
+      extype = etype;
+      etype = EXEC_UNKNOWN;
+    }
+
+  /* Word multiply instructions must not be followed by either a load or a
+     16-bit multiply instruction in the next cycle.  */
+  if (   (extype != EXEC_REVSEQ)
+      && prev_mul32_p
+      && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
+    {
+      /* However, load and multiply should able to be combined in a parallel
+	 operation, so check for that first.  */
+      if (prev_insn != -1
+	  && (opcode.op->flags_used & FLAG_MEM)
+	  && opcode.form->form < LONG
+	  && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
+	  && parallel_ok (&prev_opcode, (long) prev_insn,
+			  &opcode, (long) insn, extype)
+	  && write_2_short (&prev_opcode, (long) prev_insn,
+			    &opcode, (long) insn, extype, fixups) == 0)
+	{
+	  /* No instructions saved.  */
+	  prev_insn = -1;
+	  return;
+	}
+      else
+	{
+	  /* Can't parallelize, flush previous instruction and emit a
+	     word of NOPS, unless the previous instruction is a NOP,
+	     in which case just flush it, as this will generate a word
+	     of NOPs for us.  */
+
+	  if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
+	    d30v_cleanup (FALSE);
+	  else
 	    {
-	      /* Final check - issue a warning if an odd numbered register
-		 is used as the first register in an instruction that reads
-		 or writes 2 registers.  */
+	      char *f;
 
-	      for (j = 0; fm->operands[j]; j++)
-		if (myops[j].X_op == O_register
-		    && (myops[j].X_add_number & 1)
-		    && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
-		  as_warn (_("Odd numbered register used as target of multi-register instruction"));
+	      if (prev_insn != -1)
+		d30v_cleanup (TRUE);
+	      else
+		{
+		  f = frag_more (8);
+		  d30v_number_to_chars (f, NOP2, 8);
 
-	      return fm;
+		  if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
+		    {
+		      if (opcode.op->flags_used & FLAG_MEM)
+			as_warn (_("word of NOPs added between word multiply and load"));
+		      else
+			as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
+		    }
+		}
 	    }
-	  fm = (struct d30v_format *) &d30v_format_table[++k];
+
+	  extype = EXEC_UNKNOWN;
 	}
-#if 0
-      printf ("trying another format: i=%d\n", i);
-#endif
     }
-  return NULL;
+  else if (   (extype == EXEC_REVSEQ)
+	   && cur_mul32_p
+	   && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
+    {
+      /* Can't parallelize, flush current instruction and add a
+         sequential NOP.  */
+      write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
+
+      /* Make the previous instruction the current one.  */
+      extype = EXEC_UNKNOWN;
+      insn = prev_insn;
+      now_seg = prev_seg;
+      now_subseg = prev_subseg;
+      prev_insn = -1;
+      cur_mul32_p = prev_mul32_p;
+      prev_mul32_p = 0;
+      memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
+    }
+
+  /* If this is a long instruction, write it and any previous short
+     instruction.  */
+  if (opcode.form->form >= LONG)
+    {
+      if (extype != EXEC_UNKNOWN)
+	as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
+      d30v_cleanup (FALSE);
+      write_long (&opcode, insn, fixups);
+      prev_insn = -1;
+    }
+  else if ((prev_insn != -1)
+	   && (write_2_short
+	       (&prev_opcode, (long) prev_insn, &opcode,
+		(long) insn, extype, fixups) == 0))
+    {
+      /* No instructions saved.  */
+      prev_insn = -1;
+    }
+  else
+    {
+      if (extype != EXEC_UNKNOWN)
+	as_bad (_("Unable to mix instructions as specified"));
+
+      /* Save off last instruction so it may be packed on next pass.  */
+      memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
+      prev_insn = insn;
+      prev_seg = now_seg;
+      prev_subseg = now_subseg;
+      fixups = fixups->next;
+      prev_mul32_p = cur_mul32_p;
+    }
 }
 
 /* If while processing a fixup, a reloc really needs to be created,
    then it is done here.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  if (reloc->howto == NULL)
     {
       as_bad_where (fixp->fx_file, fixp->fx_line,
 		    _("reloc %d not supported by object file format"),
@@ -1813,18 +1811,15 @@ tc_gen_reloc (seg, fixp)
 }
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
 }
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec;
+md_pcrel_from_section (fixS *fixp, segT sec)
 {
   if (fixp->fx_addsy != (symbolS *) NULL
       && (!S_IS_DEFINED (fixp->fx_addsy)
@@ -1833,11 +1828,103 @@ md_pcrel_from_section (fixp, sec)
   return fixp->fx_frag->fr_address + fixp->fx_where;
 }
 
+/* Called after the assembler has finished parsing the input file or
+   after a label is defined.  Because the D30V assembler sometimes
+   saves short instructions to see if it can package them with the
+   next instruction, there may be a short instruction that still needs
+   written.  */
+
+int
+d30v_cleanup (int use_sequential)
+{
+  segT seg;
+  subsegT subseg;
+
+  if (prev_insn != -1)
+    {
+      seg = now_seg;
+      subseg = now_subseg;
+      subseg_set (prev_seg, prev_subseg);
+      write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
+		     use_sequential);
+      subseg_set (seg, subseg);
+      prev_insn = -1;
+      if (use_sequential)
+	prev_mul32_p = FALSE;
+    }
+
+  return 1;
+}
+
+/* This function is called at the start of every line.  It checks to
+   see if the first character is a '.', which indicates the start of a
+   pseudo-op.  If it is, then write out any unwritten instructions.  */
+
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+d30v_start_line (void)
+{
+  char *c = input_line_pointer;
+
+  while (ISSPACE (*c))
+    c++;
+
+  if (*c == '.')
+    d30v_cleanup (FALSE);
+}
+
+static void
+check_size (long value, int bits, char *file, int line)
+{
+  int tmp, max;
+
+  if (value < 0)
+    tmp = ~value;
+  else
+    tmp = value;
+
+  max = (1 << (bits - 1)) - 1;
+
+  if (tmp > max)
+    as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
+}
+
+/* d30v_frob_label() is called when after a label is recognized.  */
+
+void
+d30v_frob_label (symbolS *lab)
+{
+  /* Emit any pending instructions.  */
+  d30v_cleanup (FALSE);
+
+  /* Update the label's address with the current output pointer.  */
+  symbol_set_frag (lab, frag_now);
+  S_SET_VALUE (lab, (valueT) frag_now_fix ());
+
+  /* Record this label for future adjustment after we find out what
+     kind of data it references, and the required alignment therewith.  */
+  d30v_last_label = lab;
+}
+
+/* Hook into cons for capturing alignment changes.  */
+
+void
+d30v_cons_align (int size)
+{
+  int log_size;
+
+  log_size = 0;
+  while ((size >>= 1) != 0)
+    ++log_size;
+
+  if (d30v_current_align < log_size)
+    d30v_align (log_size, (char *) NULL, NULL);
+  else if (d30v_current_align > log_size)
+    d30v_current_align = log_size;
+  d30v_last_label = NULL;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *where;
   unsigned long insn, insn2;
@@ -1975,213 +2062,11 @@ md_apply_fix3 (fixP, valP, seg)
     }
 }
 
-/* Called after the assembler has finished parsing the input file or
-   after a label is defined.  Because the D30V assembler sometimes
-   saves short instructions to see if it can package them with the
-   next instruction, there may be a short instruction that still needs
-   written.  */
-
-int
-d30v_cleanup (use_sequential)
-     int use_sequential;
-{
-  segT seg;
-  subsegT subseg;
-
-  if (prev_insn != -1)
-    {
-      seg = now_seg;
-      subseg = now_subseg;
-      subseg_set (prev_seg, prev_subseg);
-      write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
-		     use_sequential);
-      subseg_set (seg, subseg);
-      prev_insn = -1;
-      if (use_sequential)
-	prev_mul32_p = FALSE;
-    }
-
-  return 1;
-}
-
-static void
-d30v_number_to_chars (buf, value, n)
-     char *buf;			/* Return 'nbytes' of chars here.  */
-     long long value;		/* The value of the bits.  */
-     int n;			/* Number of bytes in the output.  */
-{
-  while (n--)
-    {
-      buf[n] = value & 0xff;
-      value >>= 8;
-    }
-}
-
-/* This function is called at the start of every line.  It checks to
-   see if the first character is a '.', which indicates the start of a
-   pseudo-op.  If it is, then write out any unwritten instructions.  */
-
-void
-d30v_start_line ()
-{
-  char *c = input_line_pointer;
-
-  while (ISSPACE (*c))
-    c++;
-
-  if (*c == '.')
-    d30v_cleanup (FALSE);
-}
-
-static void
-check_size (value, bits, file, line)
-     long value;
-     int bits;
-     char *file;
-     int line;
-{
-  int tmp, max;
-
-  if (value < 0)
-    tmp = ~value;
-  else
-    tmp = value;
-
-  max = (1 << (bits - 1)) - 1;
-
-  if (tmp > max)
-    as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
-}
-
-/* d30v_frob_label() is called when after a label is recognized.  */
-
-void
-d30v_frob_label (lab)
-     symbolS *lab;
-{
-  /* Emit any pending instructions.  */
-  d30v_cleanup (FALSE);
-
-  /* Update the label's address with the current output pointer.  */
-  symbol_set_frag (lab, frag_now);
-  S_SET_VALUE (lab, (valueT) frag_now_fix ());
-
-  /* Record this label for future adjustment after we find out what
-     kind of data it references, and the required alignment therewith.  */
-  d30v_last_label = lab;
-}
-
-/* Hook into cons for capturing alignment changes.  */
-
-void
-d30v_cons_align (size)
-     int size;
-{
-  int log_size;
-
-  log_size = 0;
-  while ((size >>= 1) != 0)
-    ++log_size;
-
-  if (d30v_current_align < log_size)
-    d30v_align (log_size, (char *) NULL, NULL);
-  else if (d30v_current_align > log_size)
-    d30v_current_align = log_size;
-  d30v_last_label = NULL;
-}
-
-/* Called internally to handle all alignment needs.  This takes care
-   of eliding calls to frag_align if'n the cached current alignment
-   says we've already got it, as well as taking care of the auto-aligning
-   labels wrt code.  */
-
-static void
-d30v_align (n, pfill, label)
-     int n;
-     char *pfill;
-     symbolS *label;
-{
-  /* The front end is prone to changing segments out from under us
-     temporarily when -g is in effect.  */
-  int switched_seg_p = (d30v_current_align_seg != now_seg);
-
-  /* Do not assume that if 'd30v_current_align >= n' and
-     '! switched_seg_p' that it is safe to avoid performing
-     this alignment request.  The alignment of the current frag
-     can be changed under our feet, for example by a .ascii
-     directive in the source code.  cf testsuite/gas/d30v/reloc.s  */
-  d30v_cleanup (FALSE);
-
-  if (pfill == NULL)
-    {
-      if (n > 2
-	  && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
-	{
-	  static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
-
-	  /* First, make sure we're on a four-byte boundary, in case
-	     someone has been putting .byte values the text section.  */
-	  if (d30v_current_align < 2 || switched_seg_p)
-	    frag_align (2, 0, 0);
-	  frag_align_pattern (n, nop, sizeof nop, 0);
-	}
-      else
-	frag_align (n, 0, 0);
-    }
-  else
-    frag_align (n, *pfill, 0);
-
-  if (!switched_seg_p)
-    d30v_current_align = n;
-
-  if (label != NULL)
-    {
-      symbolS     *sym;
-      int          label_seen = FALSE;
-      struct frag *old_frag;
-      valueT       old_value;
-      valueT       new_value;
-
-      assert (S_GET_SEGMENT (label) == now_seg);
-
-      old_frag  = symbol_get_frag (label);
-      old_value = S_GET_VALUE (label);
-      new_value = (valueT) frag_now_fix ();
-
-      /* It is possible to have more than one label at a particular
-	 address, especially if debugging is enabled, so we must
-	 take care to adjust all the labels at this address in this
-	 fragment.  To save time we search from the end of the symbol
-	 list, backwards, since the symbols we are interested in are
-	 almost certainly the ones that were most recently added.
-	 Also to save time we stop searching once we have seen at least
-	 one matching label, and we encounter a label that is no longer
-	 in the target fragment.  Note, this search is guaranteed to
-	 find at least one match when sym == label, so no special case
-	 code is necessary.  */
-      for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
-	{
-	  if (symbol_get_frag (sym) == old_frag
-	      && S_GET_VALUE (sym) == old_value)
-	    {
-	      label_seen = TRUE;
-	      symbol_set_frag (sym, frag_now);
-	      S_SET_VALUE (sym, new_value);
-	    }
-	  else if (label_seen && symbol_get_frag (sym) != old_frag)
-	    break;
-	}
-    }
-
-  record_alignment (now_seg, n);
-}
-
 /* Handle the .align pseudo-op.  This aligns to a power of two.  We
    hook here to latch the current alignment.  */
 
 static void
-s_d30v_align (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_d30v_align (int ignore ATTRIBUTE_UNUSED)
 {
   int align;
   char fill, *pfill = NULL;
@@ -2216,8 +2101,7 @@ s_d30v_align (ignore)
    clears the saved last label and resets known alignment.  */
 
 static void
-s_d30v_text (i)
-     int i;
+s_d30v_text (int i)
 
 {
   s_text (i);
@@ -2230,8 +2114,7 @@ s_d30v_text (i)
    clears the saved last label and resets known alignment.  */
 
 static void
-s_d30v_data (i)
-     int i;
+s_d30v_data (int i)
 {
   s_data (i);
   d30v_last_label = NULL;
@@ -2243,11 +2126,26 @@ s_d30v_data (i)
    clears the saved last label and resets known alignment.  */
 
 static void
-s_d30v_section (ignore)
-     int ignore;
+s_d30v_section (int ignore)
 {
   obj_elf_section (ignore);
   d30v_last_label = NULL;
   d30v_current_align = 0;
   d30v_current_align_seg = now_seg;
 }
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word", cons, 4 },
+  { "hword", cons, 2 },
+  { "align", s_d30v_align, 0 },
+  { "text", s_d30v_text, 0 },
+  { "data", s_d30v_data, 0 },
+  { "section", s_d30v_section, 0 },
+  { "section.s", s_d30v_section, 0 },
+  { "sect", s_d30v_section, 0 },
+  { "sect.s", s_d30v_section, 0 },
+  { NULL, NULL, 0 }
+};
+
diff --git a/gas/config/tc-d30v.h b/gas/config/tc-d30v.h
index 7306817c10ae..9a5e7ccabd08 100644
--- a/gas/config/tc-d30v.h
+++ b/gas/config/tc-d30v.h
@@ -1,5 +1,6 @@
 /* tc-310v.h -- Header file for tc-d30v.c.
-   Copyright 1997, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2000, 2001, 2002, 2005
+   Free Software Foundation, Inc.
    Written by Martin Hunt, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,51 +17,48 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_D30V
 
-#ifndef BFD_ASSEMBLER
- #error D30V support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
-#define TARGET_ARCH bfd_arch_d30v
-#define TARGET_FORMAT "elf32-d30v"
-#define TARGET_BYTES_BIG_ENDIAN 1
+#define TARGET_ARCH              bfd_arch_d30v
+#define TARGET_FORMAT            "elf32-d30v"
+#define TARGET_BYTES_BIG_ENDIAN  1
 
 #define md_operand(x)
 
 /* Call md_pcrel_from_section, not md_pcrel_from.  */
 struct fix;
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
 #define md_number_to_chars           number_to_chars_bigendian
 
-int d30v_cleanup PARAMS ((int));
+int d30v_cleanup (int);
 #define md_after_pass_hook()	     d30v_cleanup (FALSE)
 #define md_cleanup()		     d30v_cleanup (FALSE)
 #define TC_START_LABEL(ch, ptr)      (ch == ':' && d30v_cleanup (FALSE))
-void d30v_start_line PARAMS ((void));
+void d30v_start_line (void);
 #define md_start_line_hook()	     d30v_start_line ()
 
-void d30v_frob_label PARAMS ((symbolS *));
-#define tc_frob_label(sym)	     d30v_frob_label(sym)
+void d30v_frob_label (symbolS *);
+#define tc_frob_label(sym)	     d30v_frob_label (sym)
 
-void d30v_cons_align PARAMS ((int));
-#define md_cons_align(nbytes)	     d30v_cons_align(nbytes)
+void d30v_cons_align (int);
+#define md_cons_align(nbytes)	     d30v_cons_align (nbytes)
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
diff --git a/gas/config/tc-dlx.c b/gas/config/tc-dlx.c
index 82b4aa249b08..ac0aabae622b 100644
--- a/gas/config/tc-dlx.c
+++ b/gas/config/tc-dlx.c
@@ -1,5 +1,5 @@
 /* tc-ldx.c -- Assemble for the DLX
-   Copyright 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Initially created by Kuang Hwa Lin, 3/20/2002.  */
 
@@ -24,9 +24,6 @@
 #include "as.h"
 #include "tc-dlx.h"
 #include "opcode/dlx.h"
-#if 0
-#include "elf/dlx.h"
-#endif
 
 /* Make it easier to clone this machine desc into another one.  */
 #define	machine_opcode      dlx_opcode
@@ -61,35 +58,6 @@ struct machine_it
 }
 the_insn;
 
-/* static void print_insn PARAMS ((struct machine_it *)); */
-char * parse_operand    PARAMS ((char *, expressionS *));
-int md_chars_to_number  PARAMS ((unsigned char *, int));
-
-static void machine_ip          PARAMS ((char *));
-static void s_proc              PARAMS ((int));
-static void insert_sreg         PARAMS ((char *, int));
-static int  hilo_modifier_ok    PARAMS ((char *));
-static int  is_ldst_registers   PARAMS ((char *));
-static int  match_sft_register  PARAMS ((char *));
-static void define_some_regs    PARAMS ((void));
-static char * dlx_parse_loadop  PARAMS ((char *));
-static char * dlx_parse_storeop PARAMS ((char *));
-static char * fix_ld_st_operand PARAMS ((unsigned long, char *));
-
-const pseudo_typeS
-
-dlx_pseudo_table[] =
-  {
-    /* Some additional ops that are used by gcc-dlx.  */
-    {"asciiz", stringer, 1},
-    {"half", cons, 2},
-    {"dword", cons, 8},
-    {"word", cons, 4},
-    {"proc", s_proc, 0},
-    {"endproc", s_proc, 1},
-    {NULL, 0, 0},
-  };
-
 /* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = ";";
@@ -116,9 +84,7 @@ const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "rRsSfFdDxXpP";
 
 static void
-insert_sreg (regname, regnum)
-     char *regname;
-     int regnum;
+insert_sreg (char *regname, int regnum)
 {
   /* Must be large enough to hold the names of the special registers.  */
   char buf[80];
@@ -138,43 +104,8 @@ insert_sreg (regname, regnum)
    See MIPS Assembly Language Programmer's Guide page 1-4   */
 
 static void
-define_some_regs ()
+define_some_regs (void)
 {
-#if 0
-  /* Hardware representation.  */
-  insert_sreg ("r0",    0);
-  insert_sreg ("r1",    1);
-  insert_sreg ("r2",    2);
-  insert_sreg ("r3",    3);
-  insert_sreg ("r4",    4);
-  insert_sreg ("r5",    5);
-  insert_sreg ("r6",    6);
-  insert_sreg ("r7",    7);
-  insert_sreg ("r8",    8);
-  insert_sreg ("r9",    9);
-  insert_sreg ("r10",   10);
-  insert_sreg ("r11",   11);
-  insert_sreg ("r12",   12);
-  insert_sreg ("r13",   13);
-  insert_sreg ("r14",   14);
-  insert_sreg ("r15",   15);
-  insert_sreg ("r16",   16);
-  insert_sreg ("r17",   17);
-  insert_sreg ("r18",   18);
-  insert_sreg ("r19",   19);
-  insert_sreg ("r20",   20);
-  insert_sreg ("r21",   21);
-  insert_sreg ("r22",   22);
-  insert_sreg ("r23",   23);
-  insert_sreg ("r24",   24);
-  insert_sreg ("r25",   25);
-  insert_sreg ("r26",   26);
-  insert_sreg ("r27",   27);
-  insert_sreg ("r28",   28);
-  insert_sreg ("r29",   29);
-  insert_sreg ("r30",   30);
-  insert_sreg ("r31",   31);
-#endif
   /* Software representation.  */
   insert_sreg ("zero",  0);
   insert_sreg ("at",    1);
@@ -214,11 +145,10 @@ define_some_regs ()
   insert_sreg ("iad",   2);
 }
 
-/* Subroutine check the string to match an register, */
+/* Subroutine check the string to match an register.  */
 
 static int
-match_sft_register (name)
-     char *name;
+match_sft_register (char *name)
 {
 #define MAX_REG_NO  35
 /* Currently we have 35 software registers defined -
@@ -249,8 +179,7 @@ match_sft_register (name)
 /* Subroutine check the string to match an register.  */
 
 static int
-is_ldst_registers (name)
-     char *name;
+is_ldst_registers (char *name)
 {
   char *ptr = name;
 
@@ -267,8 +196,7 @@ is_ldst_registers (name)
    If DEFAULT_PREFIX is NULL, use the target's "leading char".  */
 
 static void
-s_proc (end_p)
-     int end_p;
+s_proc (int end_p)
 {
   /* Record the current function so that we can issue an error message for
      misplaced .func,.endfunc, and also so that .endfunc needs no
@@ -341,7 +269,7 @@ s_proc (end_p)
    need.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   const char *retval = NULL;
   int lose = 0;
@@ -355,7 +283,7 @@ md_begin ()
     {
       const char *name = machine_opcodes[i].name;
 
-      retval = hash_insert (op_hash, name, (PTR) &machine_opcodes[i]);
+      retval = hash_insert (op_hash, name, (void *) &machine_opcodes[i]);
 
       if (retval != NULL)
 	{
@@ -371,170 +299,6 @@ md_begin ()
   define_some_regs ();
 }
 
-/* Assemble a single instruction.  Its label has already been handled
-   by the generic front end.  We just parse opcode and operands, and
-   produce the bytes of data and relocation.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  char *toP;
-  fixS *fixP;
-  bit_fixS *bitP;
-
-  know (str);
-  machine_ip (str);
-  toP = frag_more (4);
-  /* Put out the opcode.  */
-  md_number_to_chars (toP, the_insn.opcode, 4);
-
-  /* Put out the symbol-dependent stuff.  */
-  if (the_insn.reloc != NO_RELOC)
-    {
-      fixP = fix_new_exp (frag_now,
-			  (toP - frag_now->fr_literal + the_insn.reloc_offset),
-			  the_insn.size, & the_insn.exp, the_insn.pcrel,
-			  the_insn.reloc);
-
-      /* Turn off complaints that the addend is
-	 too large for things like foo+100000@ha.  */
-      switch (the_insn.reloc)
-	{
-	case RELOC_DLX_HI16:
-	case RELOC_DLX_LO16:
-	  fixP->fx_no_overflow = 1;
-	  break;
-	default:
-	  break;
-	}
-
-      switch (fixP->fx_r_type)
-	{
-	case RELOC_DLX_REL26:
-	  bitP = malloc (sizeof (bit_fixS));
-	  bitP->fx_bit_size = 26;
-	  bitP->fx_bit_offset = 25;
-	  bitP->fx_bit_base = the_insn.opcode & 0xFC000000;
-	  bitP->fx_bit_base_adj = 0;
-	  bitP->fx_bit_max = 0;
-	  bitP->fx_bit_min = 0;
-	  bitP->fx_bit_add = 0x03FFFFFF;
-	  fixP->fx_bit_fixP = bitP;
-	  break;
-	case RELOC_DLX_LO16:
-	case RELOC_DLX_REL16:
-	  bitP = malloc (sizeof (bit_fixS));
-	  bitP->fx_bit_size = 16;
-	  bitP->fx_bit_offset = 15;
-	  bitP->fx_bit_base = the_insn.opcode & 0xFFFF0000;
-	  bitP->fx_bit_base_adj = 0;
-	  bitP->fx_bit_max = 0;
-	  bitP->fx_bit_min = 0;
-	  bitP->fx_bit_add = 0x0000FFFF;
-	  fixP->fx_bit_fixP = bitP;
-	  break;
-	case RELOC_DLX_HI16:
-	  bitP = malloc (sizeof (bit_fixS));
-	  bitP->fx_bit_size = 16;
-	  bitP->fx_bit_offset = 15;
-	  bitP->fx_bit_base = the_insn.opcode & 0xFFFF0000;
-	  bitP->fx_bit_base_adj = 0;
-	  bitP->fx_bit_max = 0;
-	  bitP->fx_bit_min = 0;
-	  bitP->fx_bit_add = 0x0000FFFF;
-	  fixP->fx_bit_fixP = bitP;
-	  break;
-	default:
-	  fixP->fx_bit_fixP = (bit_fixS *)NULL;
-	  break;
-	}
-    }
-}
-
-static int
-hilo_modifier_ok (s)
-     char *s;
-{
-  char *ptr = s;
-  int   idx, count = 1;
-
-  if (*ptr != '(')
-    return 1;
-
-  for (idx = 1; ptr[idx] != '\0' && ptr[idx] != '[' && idx < 73; idx += 1)
-    {
-      if (count == 0)
-	return count;
-
-      if (ptr[idx] == '(')
-	count += 1;
-
-      if (ptr[idx] == ')')
-	count -= 1;
-    }
-
-  return (count == 0) ? 1:0;
-}
-
-char *
-parse_operand (s, operandp)
-     char *s;
-     expressionS *operandp;
-{
-  char *save = input_line_pointer;
-  char *new;
-
-  the_insn.HI = the_insn.LO = 0;
-
-  /* Search for %hi and %lo, make a mark and skip it.  */
-  if (strncmp (s, "%hi", 3) == 0)
-    {
-      s += 3;
-      the_insn.HI = 1;
-    }
-  else
-    {
-      if (strncmp (s, "%lo", 3) == 0)
-	{
-	  s += 3;
-	  the_insn.LO = 1;
-	}
-      else
-	the_insn.LO = 0;
-    }
-
-  if (the_insn.HI || the_insn.LO)
-    {
-      if (!hilo_modifier_ok (s))
-	as_bad (_("Expression Error for operand modifier %%hi/%%lo\n"));
-    }
-
-  /* Check for the % and $ register representation    */
-  if ((s[0] == '%' || s[0] == '$' || s[0] == 'r' || s[0] == 'R')
-      && ISDIGIT ((unsigned char) s[1]))
-    {
-      /* We have a numeric register expression.  No biggy.  */
-      s += 1;
-      input_line_pointer = s;
-      (void) expression (operandp);
-      if (operandp->X_op != O_constant
-	  || operandp->X_add_number > 31)
-	as_bad (_("Invalid expression after %%%%\n"));
-      operandp->X_op = O_register;
-    }
-  else
-    {
-      /* Normal operand parsing.  */
-      input_line_pointer = s;
-      (void) expression (operandp);
-    }
-
-  new = input_line_pointer;
-  input_line_pointer = save;
-  return new;
-}
-
 /* This function will check the opcode and return 1 if the opcode is one
    of the load/store instruction, and it will fix the operand string to
    the standard form so we can use the standard parse_operand routine.  */
@@ -544,8 +308,7 @@ parse_operand (s, operandp)
 static char iBuf[81];
 
 static char *
-dlx_parse_loadop (str)
-     char * str;
+dlx_parse_loadop (char * str)
 {
   char *ptr = str;
   int   idx = 0;
@@ -663,8 +426,7 @@ dlx_parse_loadop (str)
 }
 
 static char *
-dlx_parse_storeop (str)
-     char * str;
+dlx_parse_storeop (char * str)
 {
   char *ptr = str;
   int   idx = 0;
@@ -781,9 +543,7 @@ dlx_parse_storeop (str)
 }
 
 static char *
-fix_ld_st_operand (opcode, str)
-     unsigned long opcode;
-     char* str;
+fix_ld_st_operand (unsigned long opcode, char* str)
 {
   /* Check the opcode.  */
   switch ((int) opcode)
@@ -806,13 +566,92 @@ fix_ld_st_operand (opcode, str)
     }
 }
 
+static int
+hilo_modifier_ok (char *s)
+{
+  char *ptr = s;
+  int   idx, count = 1;
+
+  if (*ptr != '(')
+    return 1;
+
+  for (idx = 1; ptr[idx] != '\0' && ptr[idx] != '[' && idx < 73; idx += 1)
+    {
+      if (count == 0)
+	return count;
+
+      if (ptr[idx] == '(')
+	count += 1;
+
+      if (ptr[idx] == ')')
+	count -= 1;
+    }
+
+  return (count == 0) ? 1:0;
+}
+
+static char *
+parse_operand (char *s, expressionS *operandp)
+{
+  char *save = input_line_pointer;
+  char *new;
+
+  the_insn.HI = the_insn.LO = 0;
+
+  /* Search for %hi and %lo, make a mark and skip it.  */
+  if (strncmp (s, "%hi", 3) == 0)
+    {
+      s += 3;
+      the_insn.HI = 1;
+    }
+  else
+    {
+      if (strncmp (s, "%lo", 3) == 0)
+	{
+	  s += 3;
+	  the_insn.LO = 1;
+	}
+      else
+	the_insn.LO = 0;
+    }
+
+  if (the_insn.HI || the_insn.LO)
+    {
+      if (!hilo_modifier_ok (s))
+	as_bad (_("Expression Error for operand modifier %%hi/%%lo\n"));
+    }
+
+  /* Check for the % and $ register representation    */
+  if ((s[0] == '%' || s[0] == '$' || s[0] == 'r' || s[0] == 'R')
+      && ISDIGIT ((unsigned char) s[1]))
+    {
+      /* We have a numeric register expression.  No biggy.  */
+      s += 1;
+      input_line_pointer = s;
+      (void) expression (operandp);
+      if (operandp->X_op != O_constant
+	  || operandp->X_add_number > 31)
+	as_bad (_("Invalid expression after %%%%\n"));
+      operandp->X_op = O_register;
+    }
+  else
+    {
+      /* Normal operand parsing.  */
+      input_line_pointer = s;
+      (void) expression (operandp);
+    }
+
+  new = input_line_pointer;
+  input_line_pointer = save;
+  return new;
+}
+
 /* Instruction parsing.  Takes a string containing the opcode.
    Operands are at input_line_pointer.  Output is in the_insn.
    Warnings or errors are generated.  */
 
 static void
-machine_ip (str)
-     char *str;
+machine_ip (char *str)
 {
   char *s;
   const char *args;
@@ -1010,21 +849,18 @@ machine_ip (str)
 	  /* Type 'a' Register.  */
 	case 'a':
 	  /* A general register at bits 21-25, rs1.  */
-	  know (operand->X_op != O_register);
 	  reg_shift = 21;
 	  goto general_reg;
 
 	  /* Type 'b' Register.  */
 	case 'b':
 	  /* A general register at bits 16-20, rs2/rd.  */
-	  know (operand->X_op != O_register);
 	  reg_shift = 16;
 	  goto general_reg;
 
 	  /* Type 'c' Register.  */
 	case 'c':
 	  /* A general register at bits 11-15, rd.  */
-	  know (operand->X_op != O_register);
 	  reg_shift = 11;
 
 	general_reg:
@@ -1058,6 +894,86 @@ machine_ip (str)
     }
 }
 
+/* Assemble a single instruction.  Its label has already been handled
+   by the generic front end.  We just parse opcode and operands, and
+   produce the bytes of data and relocation.  */
+
+void
+md_assemble (char *str)
+{
+  char *toP;
+  fixS *fixP;
+  bit_fixS *bitP;
+
+  know (str);
+  machine_ip (str);
+  toP = frag_more (4);
+  /* Put out the opcode.  */
+  md_number_to_chars (toP, the_insn.opcode, 4);
+
+  /* Put out the symbol-dependent stuff.  */
+  if (the_insn.reloc != NO_RELOC)
+    {
+      fixP = fix_new_exp (frag_now,
+			  (toP - frag_now->fr_literal + the_insn.reloc_offset),
+			  the_insn.size, & the_insn.exp, the_insn.pcrel,
+			  the_insn.reloc);
+
+      /* Turn off complaints that the addend is
+	 too large for things like foo+100000@ha.  */
+      switch (the_insn.reloc)
+	{
+	case RELOC_DLX_HI16:
+	case RELOC_DLX_LO16:
+	  fixP->fx_no_overflow = 1;
+	  break;
+	default:
+	  break;
+	}
+
+      switch (fixP->fx_r_type)
+	{
+	case RELOC_DLX_REL26:
+	  bitP = malloc (sizeof (bit_fixS));
+	  bitP->fx_bit_size = 26;
+	  bitP->fx_bit_offset = 25;
+	  bitP->fx_bit_base = the_insn.opcode & 0xFC000000;
+	  bitP->fx_bit_base_adj = 0;
+	  bitP->fx_bit_max = 0;
+	  bitP->fx_bit_min = 0;
+	  bitP->fx_bit_add = 0x03FFFFFF;
+	  fixP->fx_bit_fixP = bitP;
+	  break;
+	case RELOC_DLX_LO16:
+	case RELOC_DLX_REL16:
+	  bitP = malloc (sizeof (bit_fixS));
+	  bitP->fx_bit_size = 16;
+	  bitP->fx_bit_offset = 15;
+	  bitP->fx_bit_base = the_insn.opcode & 0xFFFF0000;
+	  bitP->fx_bit_base_adj = 0;
+	  bitP->fx_bit_max = 0;
+	  bitP->fx_bit_min = 0;
+	  bitP->fx_bit_add = 0x0000FFFF;
+	  fixP->fx_bit_fixP = bitP;
+	  break;
+	case RELOC_DLX_HI16:
+	  bitP = malloc (sizeof (bit_fixS));
+	  bitP->fx_bit_size = 16;
+	  bitP->fx_bit_offset = 15;
+	  bitP->fx_bit_base = the_insn.opcode & 0xFFFF0000;
+	  bitP->fx_bit_base_adj = 0;
+	  bitP->fx_bit_max = 0;
+	  bitP->fx_bit_min = 0;
+	  bitP->fx_bit_add = 0x0000FFFF;
+	  fixP->fx_bit_fixP = bitP;
+	  break;
+	default:
+	  fixP->fx_bit_fixP = NULL;
+	  break;
+	}
+    }
+}
+
 /* This is identical to the md_atof in m68k.c.  I think this is right,
    but I'm not sure.
 
@@ -1071,10 +987,7 @@ machine_ip (str)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -1129,35 +1042,13 @@ md_atof (type, litP, sizeP)
 
 /* Write out big-endian.  */
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
 
-/* md_chars_to_number:  convert from target byte order to host byte order.  */
-
-int
-md_chars_to_number (val, n)
-     unsigned char *val;	/* Value in target byte order.  */
-     int n;			/* Number of bytes in the input.  */
-{
-  int retval;
-
-  for (retval = 0; n--;)
-    {
-      retval <<= 8;
-      retval |= val[n];
-    }
-
-  return retval;
-}
-
 bfd_boolean
-md_dlx_fix_adjustable (fixP)
-   fixS *fixP;
+md_dlx_fix_adjustable (fixS *fixP)
 {
   /* We need the symbol name for the VTABLE entries.  */
   return (fixP->fx_r_type != BFD_RELOC_VTABLE_INHERIT
@@ -1165,56 +1056,50 @@ md_dlx_fix_adjustable (fixP)
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   long val = *valP;
   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
 
-  know (fixP->fx_size == 4);
-  know (fixP->fx_r_type < NO_RELOC);
-
   switch (fixP->fx_r_type)
     {
     case RELOC_DLX_LO16:
     case RELOC_DLX_REL16:
-      if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
+      if (fixP->fx_bit_fixP != NULL)
 	{
 	  val = (val & 0x0000FFFF) | fixP->fx_bit_fixP->fx_bit_base;
 	  free (fixP->fx_bit_fixP);
-	  fixP->fx_bit_fixP = (bit_fixS *) NULL;
+	  fixP->fx_bit_fixP = NULL;
 	}
 #ifdef DEBUG
       else
-	know ((fixP->fx_bit_fixP != (bit_fixS *) NULL));
+	know ((fixP->fx_bit_fixP != NULL));
 #endif
       break;
 
     case RELOC_DLX_HI16:
-      if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
+      if (fixP->fx_bit_fixP != NULL)
 	{
 	  val = (val >> 16) | fixP->fx_bit_fixP->fx_bit_base;
 	  free (fixP->fx_bit_fixP);
-	  fixP->fx_bit_fixP = (bit_fixS *)NULL;
+	  fixP->fx_bit_fixP = NULL;
 	}
 #ifdef DEBUG
       else
-	know ((fixP->fx_bit_fixP != (bit_fixS *) NULL));
+	know ((fixP->fx_bit_fixP != NULL));
 #endif
       break;
 
     case RELOC_DLX_REL26:
-      if (fixP->fx_bit_fixP != (bit_fixS *) NULL)
+      if (fixP->fx_bit_fixP != NULL)
 	{
 	  val = (val & 0x03FFFFFF) | fixP->fx_bit_fixP->fx_bit_base;
 	  free (fixP->fx_bit_fixP);
-	  fixP->fx_bit_fixP = (bit_fixS *) NULL;
+	  fixP->fx_bit_fixP = NULL;
 	}
 #ifdef DEBUG
       else
-	know ((fixP->fx_bit_fixP != (bit_fixS *) NULL));
+	know ((fixP->fx_bit_fixP != NULL));
 #endif
       break;
 
@@ -1250,24 +1135,21 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c     ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c     ATTRIBUTE_UNUSED,
+		 char *arg ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
 {
 }
 
 /* This is called when a line is unrecognized.  */
 
 int
-dlx_unrecognized_line (c)
-     int c;
+dlx_unrecognized_line (int c)
 {
   int lab;
   char *s;
@@ -1285,10 +1167,8 @@ dlx_unrecognized_line (c)
     }
 
   if (*s != ':')
-    {
-      /* Not a label definition.  */
-      return 0;
-    }
+    /* Not a label definition.  */
+    return 0;
 
   if (dollar_label_defined (lab))
     {
@@ -1308,20 +1188,17 @@ dlx_unrecognized_line (c)
    are a lot of them.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return NULL;
 }
 
-
 /* Parse an operand that is machine-specific, the function was called
    in expr.c by operand() function, when everything failed before it
    call a quit.  */
 
 void
-md_operand (expressionP)
-     expressionS* expressionP;
+md_operand (expressionS* expressionP)
 {
   /* Check for the #number representation    */
   if (input_line_pointer[0] == '#' &&
@@ -1337,41 +1214,13 @@ md_operand (expressionP)
     }
 
   return;
-#if 0
-  else if (input_line_pointer[0] == '$'
-	   && ISDIGIT ((unsigned char) input_line_pointer[1]))
-    {
-      long lab;
-      char *name;
-      symbolS *sym;
-
-      /* This is a local label.  */
-      ++input_line_pointer;
-      lab = (long) get_absolute_expression ();
-      if (dollar_label_defined (lab))
-	{
-	  name = dollar_label_name (lab, 0);
-	  sym = symbol_find (name);
-	}
-      else
-	{
-	  name = dollar_label_name (lab, 1);
-	  sym = symbol_find_or_make (name);
-	}
-
-      expressionP->X_op = O_symbol;
-      expressionP->X_add_symbol = sym;
-      expressionP->X_add_number = 0;
-    }
-#endif
 }
 
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED,
+		  valueT size)
 {
   /* Byte alignment is fine.  */
   return size;
@@ -1382,52 +1231,26 @@ md_section_align (segment, size)
    which we have set up as the address of the fixup too.  */
 
 long
-md_pcrel_from (fixP)
-     fixS* fixP;
+md_pcrel_from (fixS* fixP)
 {
   return 4 + fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
-/* From cgen.c:  */
-
-#if 0
-static short
-tc_bfd_fix2rtype (fixP)
-     fixS* fixP;
-{
-#if 0
-  if (fixP->fx_bsr)
-    abort ();
-#endif
-
-  if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
-    return BFD_RELOC_32;
-
-  if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
-    return BFD_RELOC_26_PCREL;
-
-  abort ();
-
-  return 0;
-}
-#endif
-
 /* Translate internal representation of relocation info to BFD target
    format.
    FIXME: To what extent can we get all relevant targets to use this?
    The above FIXME is from a29k, but I think it is also needed here.    */
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
+	      fixS *fixP)
 {
   arelent * reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
 
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  if (reloc->howto == NULL)
     {
       as_bad_where (fixP->fx_file, fixP->fx_line,
 		    "internal error: can't export reloc type %d (`%s')",
@@ -1438,7 +1261,7 @@ tc_gen_reloc (section, fixP)
 
   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
 
@@ -1449,11 +1272,23 @@ tc_gen_reloc (section, fixP)
   return reloc;
 }
 
-extern void pop_insert PARAMS ((const pseudo_typeS *));
+const pseudo_typeS
+dlx_pseudo_table[] =
+{
+  /* Some additional ops that are used by gcc-dlx.  */
+  {"asciiz", stringer, 1},
+  {"half", cons, 2},
+  {"dword", cons, 8},
+  {"word", cons, 4},
+  {"proc", s_proc, 0},
+  {"endproc", s_proc, 1},
+  {NULL, NULL, 0}
+};
 
 void
-dlx_pop_insert ()
+dlx_pop_insert (void)
 {
   pop_insert (dlx_pseudo_table);
   return ;
 }
+
diff --git a/gas/config/tc-dlx.h b/gas/config/tc-dlx.h
index 9aab0d2d4f10..309f03738163 100644
--- a/gas/config/tc-dlx.h
+++ b/gas/config/tc-dlx.h
@@ -1,5 +1,5 @@
 /* tc-dlx.h -- Assemble for the DLX
-   Copyright 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,33 +15,30 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Initially created by Kuang Hwa Lin, 3/20/2002.  */
 
 #define TC_DLX
 
-#ifndef BFD_ASSEMBLER
- #error DLX support requires BFD_ASSEMBLER
-#endif
-
 #ifndef  __BFD_H_SEEN__
 #include "bfd.h"
 #endif
 
 /* The target BFD architecture.  */
-#define TARGET_ARCH bfd_arch_dlx
-#define TARGET_FORMAT "elf32-dlx"
-#define TARGET_BYTES_BIG_ENDIAN	1
+#define TARGET_ARCH              bfd_arch_dlx
+#define TARGET_FORMAT            "elf32-dlx"
+#define TARGET_BYTES_BIG_ENDIAN	 1
 
 #define WORKING_DOT_WORD
 
 #define LEX_DOLLAR 1
 
-/* #define md_operand(x) */
-extern void dlx_pop_insert              PARAMS ((void));
-extern int set_dlx_skip_hi16_flag       PARAMS ((int));
+extern void dlx_pop_insert         (void);
+extern int set_dlx_skip_hi16_flag  (int);
+extern int dlx_unrecognized_line   (int);
+extern bfd_boolean md_dlx_fix_adjustable  (struct fix *);
 
 #define md_pop_insert()		        dlx_pop_insert ()
 
@@ -51,37 +48,19 @@ extern int set_dlx_skip_hi16_flag       PARAMS ((int));
 
 #define tc_unrecognized_line(c) dlx_unrecognized_line (c)
 
-extern int dlx_unrecognized_line PARAMS ((int));
+#define tc_coff_symbol_emit_hook(a)	;	/* Not used.  */
 
-#define tc_headers_hook(a)		;	/* not used */
-#define tc_headers_hook(a)		;	/* not used */
-#define tc_crawl_symbol_chain(a)	;	/* not used */
-#define tc_coff_symbol_emit_hook(a)	;	/* not used */
-
-#define AOUT_MACHTYPE 101
-#define TC_COFF_FIX2RTYPE(fix_ptr) tc_coff_fix2rtype (fix_ptr)
-#define BFD_ARCH bfd_arch_dlx
 #define COFF_MAGIC DLXMAGIC
-/* Should the reloc be output ?
-	on the 29k, this is true only if there is a symbol attached.
-	on the h8, this is always true, since no fixup is done
-        on dlx, I have no idea!! but lets keep it here just for fun.
-*/
-#define TC_COUNT_RELOC(x) (x->fx_addsy)
-#define TC_CONS_RELOC BFD_RELOC_32_PCREL
 
 /* No shared lib support, so we don't need to ensure externally
    visible symbols can be overridden.  */
 #define EXTERN_FORCE_RELOC 0
 
 #define tc_fix_adjustable(FIX) md_dlx_fix_adjustable (FIX)
-extern bfd_boolean md_dlx_fix_adjustable PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define NEED_FX_R_TYPE
-
 /* Zero Based Segment?? sound very dangerous to me!     */
 #define ZERO_BASED_SEGMENTS
 
@@ -91,4 +70,5 @@ extern bfd_boolean md_dlx_fix_adjustable PARAMS ((struct fix *));
 #undef  LOCAL_LABELS_DOLLAR
 #define LOCAL_LABELS_DOLLAR 0
 
-#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
diff --git a/gas/config/tc-fr30.c b/gas/config/tc-fr30.c
index b47903e4486a..b0f2204c7f08 100644
--- a/gas/config/tc-fr30.c
+++ b/gas/config/tc-fr30.c
@@ -1,5 +1,5 @@
 /* tc-fr30.c -- Assembler for the Fujitsu FR30.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -66,9 +66,8 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED,
+		 char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -79,8 +78,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-  FILE * stream;
+md_show_usage (FILE * stream)
 {
   fprintf (stream, _(" FR30 specific command line options:\n"));
 }
@@ -94,7 +92,7 @@ const pseudo_typeS md_pseudo_table[] =
 
 
 void
-md_begin ()
+md_begin (void)
 {
   /* Initialize the `cgen' interface.  */
 
@@ -110,8 +108,7 @@ md_begin ()
 }
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   static int last_insn_had_delay_slot = 0;
   fr30_insn insn;
@@ -147,8 +144,7 @@ md_assemble (str)
    We just ignore it.  */
 
 void
-md_operand (expressionP)
-     expressionS * expressionP;
+md_operand (expressionS * expressionP)
 {
   if (* input_line_pointer == '#')
     {
@@ -158,19 +154,17 @@ md_operand (expressionP)
 }
 
 valueT
-md_section_align (segment, size)
-     segT   segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
+
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
 symbolS *
-md_undefined_symbol (name)
-  char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
-  return 0;
+  return NULL;
 }
 
 /* Interface to relax_segment.  */
@@ -203,50 +197,6 @@ const relax_typeS md_relax_table[] =
   {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
 };
 
-#if 0
-long
-fr30_relax_frag (segment, fragP, stretch)
-     segT    segment;
-     fragS * fragP;
-     long    stretch;
-{
-  /* Address of branch insn.  */
-  long address = fragP->fr_address + fragP->fr_fix - 2;
-  long growth = 0;
-
-  /* Keep 32 bit insns aligned on 32 bit boundaries.  */
-  if (fragP->fr_subtype == 2)
-    {
-      if ((address & 3) != 0)
-	{
-	  fragP->fr_subtype = 3;
-	  growth = 2;
-	}
-    }
-  else if (fragP->fr_subtype == 3)
-    {
-      if ((address & 3) == 0)
-	{
-	  fragP->fr_subtype = 2;
-	  growth = -2;
-	}
-    }
-  else
-    {
-      growth = relax_frag (segment, fragP, stretch);
-
-      /* Long jump on odd halfword boundary?  */
-      if (fragP->fr_subtype == 2 && (address & 3) != 0)
-	{
-	  fragP->fr_subtype = 3;
-	  growth += 2;
-	}
-    }
-
-  return growth;
-}
-#endif
-
 /* Return an initial guess of the length by which a fragment must grow to
    hold a branch to reach its destination.
    Also updates fr_type/fr_subtype as necessary.
@@ -259,9 +209,7 @@ fr30_relax_frag (segment, fragP, stretch)
    0 value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS * fragP;
-     segT    segment;
+md_estimate_size_before_relax (fragS * fragP, segT segment)
 {
   /* The only thing we have to handle here are symbols outside of the
      current segment.  They may be undefined or in a different segment in
@@ -271,34 +219,11 @@ md_estimate_size_before_relax (fragP, segment)
 
   if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
     {
-#if 0
-      int    old_fr_fix = fragP->fr_fix;
-#endif
-
       /* The symbol is undefined in this segment.
 	 Change the relaxation subtype to the max allowable and leave
 	 all further handling to md_convert_frag.  */
       fragP->fr_subtype = 2;
 
-#if 0 /* Can't use this, but leave in for illustration.  */
-      /* Change 16 bit insn to 32 bit insn.  */
-      fragP->fr_opcode[0] |= 0x80;
-
-      /* Increase known (fixed) size of fragment.  */
-      fragP->fr_fix += 2;
-
-      /* Create a relocation for it.  */
-      fix_new (fragP, old_fr_fix, 4,
-	       fragP->fr_symbol,
-	       fragP->fr_offset, 1 /* pcrel */,
-	       /* FIXME: Can't use a real BFD reloc here.
-		  gas_cgen_md_apply_fix3 can't handle it.  */
-	       BFD_RELOC_FR30_26_PCREL);
-
-      /* Mark this fragment as finished.  */
-      frag_wane (fragP);
-      return fragP->fr_fix - old_fr_fix;
-#else
       {
 	const CGEN_INSN * insn;
 	int               i;
@@ -321,7 +246,6 @@ md_estimate_size_before_relax (fragP, segment)
 	fragP->fr_cgen.insn = insn;
 	return 2;
       }
-#endif
     }
 
   /* Return the size of the variable part of the frag.  */
@@ -336,89 +260,10 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-  bfd *abfd ATTRIBUTE_UNUSED;
-  segT sec ATTRIBUTE_UNUSED;
-  fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
 {
-#if 0
-  char * opcode;
-  char * displacement;
-  int    target_address;
-  int    opcode_address;
-  int    extension;
-  int    addend;
-
-  opcode = fragP->fr_opcode;
-
-  /* Address opcode resides at in file space.  */
-  opcode_address = fragP->fr_address + fragP->fr_fix - 2;
-
-  switch (fragP->fr_subtype)
-    {
-    case 1 :
-      extension = 0;
-      displacement = & opcode[1];
-      break;
-    case 2 :
-      opcode[0] |= 0x80;
-      extension = 2;
-      displacement = & opcode[1];
-      break;
-    case 3 :
-      opcode[2] = opcode[0] | 0x80;
-      md_number_to_chars (opcode, PAR_NOP_INSN, 2);
-      opcode_address += 2;
-      extension = 4;
-      displacement = & opcode[3];
-      break;
-    default :
-      abort ();
-    }
-
-  if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
-    {
-      /* symbol must be resolved by linker */
-      if (fragP->fr_offset & 3)
-	as_warn (_("Addend to unresolved symbol not on word boundary."));
-      addend = fragP->fr_offset >> 2;
-    }
-  else
-    {
-      /* Address we want to reach in file space.  */
-      target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
-      addend = (target_address - (opcode_address & -4)) >> 2;
-    }
-
-  /* Create a relocation for symbols that must be resolved by the linker.
-     Otherwise output the completed insn.  */
-
-  if (S_GET_SEGMENT (fragP->fr_symbol) != sec)
-    {
-      assert (fragP->fr_subtype != 1);
-      assert (fragP->fr_cgen.insn != 0);
-      gas_cgen_record_fixup (fragP,
-			     /* Offset of branch insn in frag.  */
-			     fragP->fr_fix + extension - 4,
-			     fragP->fr_cgen.insn,
-			     4 /*length*/,
-			     /* FIXME: quick hack */
-#if 0
-			     CGEN_OPERAND_ENTRY (fragP->fr_cgen.opindex),
-#else
-			     CGEN_OPERAND_ENTRY (FR30_OPERAND_DISP24),
-#endif
-			     fragP->fr_cgen.opinfo,
-			     fragP->fr_symbol, fragP->fr_offset);
-    }
-
-#define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
-
-  md_number_to_chars (displacement, (valueT) addend,
-		      SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
-
-  fragP->fr_fix += extension;
-#endif
 }
 
 /* Functions concerning relocs.  */
@@ -427,18 +272,14 @@ md_convert_frag (abfd, sec, fragP)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS * fixP;
-     segT   sec;
+md_pcrel_from_section (fixS * fixP, segT sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
 	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
-    {
-      /* The symbol is undefined (or is defined but not in this section).
-	 Let the linker figure it out.  */
-      return 0;
-    }
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
 
   return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1;
 }
@@ -448,10 +289,9 @@ md_pcrel_from_section (fixP, sec)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND *operand;
-     fixS *fixP;
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND *operand,
+		      fixS *fixP)
 {
   switch (operand->type)
     {
@@ -464,7 +304,7 @@ md_cgen_lookup_reloc (insn, operand, fixP)
     case FR30_OPERAND_I8:      return BFD_RELOC_8;
     case FR30_OPERAND_I32:     return BFD_RELOC_FR30_48;
     case FR30_OPERAND_I20:     return BFD_RELOC_FR30_20;
-    default : /* avoid -Wall warning */
+    default : /* Avoid -Wall warning.  */
       break;
     }
 
@@ -474,10 +314,7 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+md_number_to_chars (char * buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
@@ -487,14 +324,11 @@ md_number_to_chars (buf, val, n)
    emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
 */
 
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
+md_atof (int type, char * litP, int * sizeP)
 {
   int              i;
   int              prec;
@@ -540,11 +374,8 @@ md_atof (type, litP, sizeP)
 }
 
 /* Worker function for fr30_is_colon_insn().  */
-static char restore_colon PARAMS ((int));
-
 static char
-restore_colon (advance_i_l_p_by)
-     int advance_i_l_p_by;
+restore_colon (int advance_i_l_p_by)
 {
   char c;
 
@@ -566,12 +397,11 @@ restore_colon (advance_i_l_p_by)
    to the real end of the instruction/symbol, and returns the character
    that really terminated the symbol.  Otherwise it returns 0.  */
 char
-fr30_is_colon_insn (start)
-     char *  start;
+fr30_is_colon_insn (char *  start)
 {
   char * i_l_p = input_line_pointer;
 
-  /* Check to see if the symbol parsed so far is 'ldi'  */
+  /* Check to see if the symbol parsed so far is 'ldi'.  */
   if (   (start[0] != 'l' && start[0] != 'L')
       || (start[1] != 'd' && start[1] != 'D')
       || (start[2] != 'i' && start[2] != 'I')
@@ -612,15 +442,15 @@ fr30_is_colon_insn (start)
       return 0;
     }
 
-  /* Check to see if the text following the colon is '8' */
+  /* Check to see if the text following the colon is '8'.  */
   if (i_l_p[1] == '8' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
     return restore_colon (2);
 
-  /* Check to see if the text following the colon is '20' */
+  /* Check to see if the text following the colon is '20'.  */
   else if (i_l_p[1] == '2' && i_l_p[2] =='0' && (i_l_p[3] == ' ' || i_l_p[3] == '\t'))
     return restore_colon (3);
 
-  /* Check to see if the text following the colon is '32' */
+  /* Check to see if the text following the colon is '32'.  */
   else if (i_l_p[1] == '3' && i_l_p[2] =='2' && (i_l_p[3] == ' ' || i_l_p[3] == '\t'))
     return restore_colon (3);
 
@@ -628,10 +458,9 @@ fr30_is_colon_insn (start)
 }
 
 bfd_boolean
-fr30_fix_adjustable (fixP)
-   fixS * fixP;
+fr30_fix_adjustable (fixS * fixP)
 {
-  /* We need the symbol name for the VTABLE entries */
+  /* We need the symbol name for the VTABLE entries.  */
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 0;
diff --git a/gas/config/tc-fr30.h b/gas/config/tc-fr30.h
index 8c1166b9051b..a3a832a5ddf3 100644
--- a/gas/config/tc-fr30.h
+++ b/gas/config/tc-fr30.h
@@ -1,5 +1,5 @@
 /* tc-fr30.h -- Header file for tc-fr30.c.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,16 +16,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_FR30
 
-#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
- #error FR30 support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "FR30 GAS "
 
 /* The target BFD architecture.  */
@@ -38,25 +33,25 @@
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs.  */
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define md_apply_fix3 gas_cgen_md_apply_fix3
+#define md_apply_fix gas_cgen_md_apply_fix
 
 #define tc_fix_adjustable(FIX) fr30_fix_adjustable (FIX)
 struct fix;
-extern bfd_boolean fr30_fix_adjustable PARAMS ((struct fix *));
+extern bfd_boolean fr30_fix_adjustable (struct fix *);
 
 #define tc_gen_reloc gas_cgen_tc_gen_reloc
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 /* For 8 vs 16 vs 32 bit branch selection.  */
 #define TC_GENERIC_RELAX_TABLE md_relax_table
@@ -72,4 +67,4 @@ extern const struct relax_type md_relax_table[];
    the local variable 'c' which is passed to this macro as 'character'.  */
 #define TC_START_LABEL(character, i_l_p)			\
   ((character) != ':' ? 0 : (character = fr30_is_colon_insn (s)) ? 0 : ((character = ':'), 1))
-extern char fr30_is_colon_insn PARAMS ((char *));
+extern char fr30_is_colon_insn (char *);
diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c
index 7c802b9fe3a1..a2f4ccef4a60 100644
--- a/gas/config/tc-frv.c
+++ b/gas/config/tc-frv.c
@@ -1,5 +1,5 @@
 /* tc-frv.c -- Assembler for the Fujitsu FRV.
-   Copyright 2002, 2003 Free Software Foundation.
+   Copyright 2002, 2003, 2004, 2005, 2006 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -169,6 +169,7 @@ static FRV_VLIW vliw;
 #endif
 
 static unsigned long frv_mach = bfd_mach_frv;
+static bfd_boolean fr400_audio;
 
 /* Flags to set in the elf header */
 static flagword frv_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
@@ -362,10 +363,24 @@ md_parse_option (c, arg)
 	    frv_mach = bfd_mach_fr550;
 	  }
 
+	else if (strcmp (p, "fr450") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR450;
+	    frv_mach = bfd_mach_fr450;
+	  }
+
+	else if (strcmp (p, "fr405") == 0)
+	  {
+	    cpu_flags = EF_FRV_CPU_FR405;
+	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = TRUE;
+	  }
+
 	else if (strcmp (p, "fr400") == 0)
 	  {
 	    cpu_flags = EF_FRV_CPU_FR400;
 	    frv_mach = bfd_mach_fr400;
+	    fr400_audio = FALSE;
 	  }
 
 	else if (strcmp (p, "fr300") == 0)
@@ -462,7 +477,7 @@ md_show_usage (stream)
   fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n"));
   fprintf (stream, _("-mfdpic      Assemble for the FDPIC ABI\n"));
   fprintf (stream, _("-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"));
-  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr300|frv|simple|tomcat}\n"));
+  fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
   fprintf (stream, _("             Record the cpu type\n"));
   fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
   fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
@@ -633,11 +648,11 @@ frv_debug_tomcat (start_chain)
       for (this_insn = this_chain->insn_list; this_insn; this_insn = this_insn->next)
 	{
 	  if (this_insn->type == VLIW_LABEL_TYPE)
-	    fprintf (stderr, "Label Value: %d\n", (int) this_insn->sym);
+	    fprintf (stderr, "Label Value: %p\n", this_insn->sym);
 	  else if (this_insn->type == VLIW_BRANCH_TYPE)
-	    fprintf (stderr, "%s to %d\n", this_insn->insn->base->name, (int) this_insn->sym);
+	    fprintf (stderr, "%s to %p\n", this_insn->insn->base->name, this_insn->sym);
 	  else if (this_insn->type == VLIW_BRANCH_HAS_NOPS)
-	    fprintf (stderr, "nop'd %s to %d\n", this_insn->insn->base->name, (int) this_insn->sym);
+	    fprintf (stderr, "nop'd %s to %p\n", this_insn->insn->base->name, this_insn->sym);
 	  else if (this_insn->type == VLIW_NOP_TYPE)
 	    fprintf (stderr, "Nop\n");
 	  else
@@ -730,7 +745,7 @@ frv_tomcat_shuffle (this_nop_type, vliw_to_split, insert_before_insn)
 	  /* Set the packing bit on the previous insn.  */
 	  if (pack_prev)
 	    {
-	      unsigned char *buffer = prev_insn->address;
+	      char *buffer = prev_insn->address;
 	      buffer[0] |= 0x80;
 	    }
 	  /* The branch is in the middle.  Split this vliw insn into first
@@ -769,7 +784,7 @@ frv_tomcat_shuffle (this_nop_type, vliw_to_split, insert_before_insn)
 	  /* Set the packing bit on the previous insn.  */
 	  if (pack_prev)
 	    {
-	      unsigned char *buffer = prev_insn->address;
+	      char *buffer = prev_insn->address;
 	      buffer[0] |= 0x80;
 	    }
 
@@ -815,7 +830,7 @@ frv_tomcat_shuffle (this_nop_type, vliw_to_split, insert_before_insn)
 	  /* Set the packing bit on the previous insn.  */
 	  if (pack_prev)
 	    {
-	      unsigned char *buffer = prev_insn->address;
+	      char *buffer = prev_insn->address;
 	      buffer[0] |= 0x80;
 	    }
 
@@ -1064,6 +1079,36 @@ fr550_check_acc_range (FRV_VLIW *vliw, frv_insn *insn)
   return 0; /* all is ok */
 }
 
+/* Return true if the target implements instruction INSN.  */
+
+static bfd_boolean
+target_implements_insn_p (const CGEN_INSN *insn)
+{
+  switch (frv_mach)
+    {
+    default:
+      /* bfd_mach_frv or generic.  */
+      return TRUE;
+
+    case bfd_mach_fr300:
+    case bfd_mach_frvsimple:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_SIMPLE);
+
+    case bfd_mach_fr400:
+      return ((fr400_audio || !CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_AUDIO))
+	      && CGEN_INSN_MACH_HAS_P (insn, MACH_FR400));
+
+    case bfd_mach_fr450:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR450);
+
+    case bfd_mach_fr500:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR500);
+
+    case bfd_mach_fr550:
+      return CGEN_INSN_MACH_HAS_P (insn, MACH_FR550);
+    }
+}
+
 void
 md_assemble (str)
      char * str;
@@ -1147,6 +1192,11 @@ md_assemble (str)
      instructions, don't do vliw checking.  */
   else if (frv_mach != bfd_mach_frv)
     {
+      if (!target_implements_insn_p (insn.insn))
+	{
+	  as_bad (_("Instruction not supported by this architecture"));
+	  return;
+	}
       packing_constraint = frv_vliw_add_insn (& vliw, insn.insn);
       if (frv_mach == bfd_mach_fr550 && ! packing_constraint)
 	packing_constraint = fr550_check_acc_range (& vliw, & insn);
@@ -1330,12 +1380,18 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 
     case FRV_OPERAND_LABEL24:
       fixP->fx_pcrel = TRUE;
+
+      if (fixP->fx_cgen.opinfo != 0)
+	return fixP->fx_cgen.opinfo;
+
       return BFD_RELOC_FRV_LABEL24;
 
     case FRV_OPERAND_UHI16:
     case FRV_OPERAND_ULO16:
     case FRV_OPERAND_SLO16:
-
+    case FRV_OPERAND_CALLANN:
+    case FRV_OPERAND_LDANN:
+    case FRV_OPERAND_LDDANN:
       /* The relocation type should be recorded in opinfo */
       if (fixP->fx_cgen.opinfo != 0)
         return fixP->fx_cgen.opinfo;
@@ -1366,9 +1422,45 @@ int
 frv_force_relocation (fix)
      fixS * fix;
 {
-  if (fix->fx_r_type == BFD_RELOC_FRV_GPREL12
-      || fix->fx_r_type == BFD_RELOC_FRV_GPRELU12)
-    return 1;
+  switch (fix->fx_r_type < BFD_RELOC_UNUSED
+	  ? (int) fix->fx_r_type
+	  : fix->fx_cgen.opinfo)
+    {
+    case BFD_RELOC_FRV_GPREL12:
+    case BFD_RELOC_FRV_GPRELU12:
+    case BFD_RELOC_FRV_GPREL32:
+    case BFD_RELOC_FRV_GPRELHI:
+    case BFD_RELOC_FRV_GPRELLO:
+    case BFD_RELOC_FRV_GOT12:
+    case BFD_RELOC_FRV_GOTHI:
+    case BFD_RELOC_FRV_GOTLO:
+    case BFD_RELOC_FRV_FUNCDESC_VALUE:
+    case BFD_RELOC_FRV_FUNCDESC_GOTOFF12:
+    case BFD_RELOC_FRV_FUNCDESC_GOTOFFHI:
+    case BFD_RELOC_FRV_FUNCDESC_GOTOFFLO:
+    case BFD_RELOC_FRV_GOTOFF12:
+    case BFD_RELOC_FRV_GOTOFFHI:
+    case BFD_RELOC_FRV_GOTOFFLO:
+    case BFD_RELOC_FRV_GETTLSOFF:
+    case BFD_RELOC_FRV_TLSDESC_VALUE:
+    case BFD_RELOC_FRV_GOTTLSDESC12:
+    case BFD_RELOC_FRV_GOTTLSDESCHI:
+    case BFD_RELOC_FRV_GOTTLSDESCLO:
+    case BFD_RELOC_FRV_TLSMOFF12:
+    case BFD_RELOC_FRV_TLSMOFFHI:
+    case BFD_RELOC_FRV_TLSMOFFLO:
+    case BFD_RELOC_FRV_GOTTLSOFF12:
+    case BFD_RELOC_FRV_GOTTLSOFFHI:
+    case BFD_RELOC_FRV_GOTTLSOFFLO:
+    case BFD_RELOC_FRV_TLSOFF:
+    case BFD_RELOC_FRV_TLSDESC_RELAX:
+    case BFD_RELOC_FRV_GETTLSOFF_RELAX:
+    case BFD_RELOC_FRV_TLSOFF_RELAX:
+      return 1;
+
+    default:
+      break;
+    }
 
   return generic_force_reloc (fix);
 }
@@ -1376,7 +1468,7 @@ frv_force_relocation (fix)
 /* Apply a fixup that could be resolved within the assembler.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS *   fixP;
      valueT * valP;
      segT     seg;
@@ -1390,9 +1482,67 @@ md_apply_fix3 (fixP, valP, seg)
       case BFD_RELOC_FRV_LO16:
 	*valP &= 0xffff;
 	break;
+
+	/* We need relocations for these, even if their symbols reduce
+	   to constants.  */
+      case BFD_RELOC_FRV_GPREL12:
+      case BFD_RELOC_FRV_GPRELU12:
+      case BFD_RELOC_FRV_GPREL32:
+      case BFD_RELOC_FRV_GPRELHI:
+      case BFD_RELOC_FRV_GPRELLO:
+      case BFD_RELOC_FRV_GOT12:
+      case BFD_RELOC_FRV_GOTHI:
+      case BFD_RELOC_FRV_GOTLO:
+      case BFD_RELOC_FRV_FUNCDESC_VALUE:
+      case BFD_RELOC_FRV_FUNCDESC_GOTOFF12:
+      case BFD_RELOC_FRV_FUNCDESC_GOTOFFHI:
+      case BFD_RELOC_FRV_FUNCDESC_GOTOFFLO:
+      case BFD_RELOC_FRV_GOTOFF12:
+      case BFD_RELOC_FRV_GOTOFFHI:
+      case BFD_RELOC_FRV_GOTOFFLO:
+      case BFD_RELOC_FRV_GETTLSOFF:
+      case BFD_RELOC_FRV_TLSDESC_VALUE:
+      case BFD_RELOC_FRV_GOTTLSDESC12:
+      case BFD_RELOC_FRV_GOTTLSDESCHI:
+      case BFD_RELOC_FRV_GOTTLSDESCLO:
+      case BFD_RELOC_FRV_TLSMOFF12:
+      case BFD_RELOC_FRV_TLSMOFFHI:
+      case BFD_RELOC_FRV_TLSMOFFLO:
+      case BFD_RELOC_FRV_GOTTLSOFF12:
+      case BFD_RELOC_FRV_GOTTLSOFFHI:
+      case BFD_RELOC_FRV_GOTTLSOFFLO:
+      case BFD_RELOC_FRV_TLSOFF:
+      case BFD_RELOC_FRV_TLSDESC_RELAX:
+      case BFD_RELOC_FRV_GETTLSOFF_RELAX:
+      case BFD_RELOC_FRV_TLSOFF_RELAX:
+	fixP->fx_addsy = expr_build_uconstant (0);
+	break;
+      }
+  else
+    switch (fixP->fx_cgen.opinfo)
+      {
+      case BFD_RELOC_FRV_GETTLSOFF:
+      case BFD_RELOC_FRV_TLSDESC_VALUE:
+      case BFD_RELOC_FRV_GOTTLSDESC12:
+      case BFD_RELOC_FRV_GOTTLSDESCHI:
+      case BFD_RELOC_FRV_GOTTLSDESCLO:
+      case BFD_RELOC_FRV_TLSMOFF12:
+      case BFD_RELOC_FRV_TLSMOFFHI:
+      case BFD_RELOC_FRV_TLSMOFFLO:
+      case BFD_RELOC_FRV_GOTTLSOFF12:
+      case BFD_RELOC_FRV_GOTTLSOFFHI:
+      case BFD_RELOC_FRV_GOTTLSOFFLO:
+      case BFD_RELOC_FRV_TLSOFF:
+      case BFD_RELOC_FRV_TLSDESC_RELAX:
+      case BFD_RELOC_FRV_GETTLSOFF_RELAX:
+      case BFD_RELOC_FRV_TLSOFF_RELAX:
+	/* Mark TLS symbols as such.  */
+	if (S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
+	break;
       }
 
-  gas_cgen_md_apply_fix3 (fixP, valP, seg);
+  gas_cgen_md_apply_fix (fixP, valP, seg);
   return;
 }
 
@@ -1553,6 +1703,16 @@ frv_pic_ptr (nbytes)
 	    as_bad ("missing ')'");
 	  reloc_type = BFD_RELOC_FRV_FUNCDESC;
 	}
+      else if (strncasecmp (input_line_pointer, "tlsmoff(", 8) == 0)
+	{
+	  input_line_pointer += 8;
+	  expression (&exp);
+	  if (*input_line_pointer == ')')
+	    input_line_pointer++;
+	  else
+	    as_bad ("missing ')'");
+	  reloc_type = BFD_RELOC_FRV_TLSMOFF;
+	}
       else
 	expression (&exp);
 
diff --git a/gas/config/tc-frv.h b/gas/config/tc-frv.h
index fb887a0d3533..ddf5c0220ffe 100644
--- a/gas/config/tc-frv.h
+++ b/gas/config/tc-frv.h
@@ -1,5 +1,5 @@
 /* tc-frv.h -- Header file for tc-frv.c.
-   Copyright 2002 Free Software Foundation, Inc.
+   Copyright 2002, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,16 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA. */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA. */
 
 #define TC_FRV
 
-#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
- #error FRV support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "FRV GAS "
 
 /* The target BFD architecture.  */
@@ -44,7 +39,7 @@ extern bfd_boolean frv_md_fdpic_enabled (void);
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 extern void frv_tomcat_workaround PARAMS ((void));
@@ -109,7 +104,7 @@ extern void frv_frob_file	PARAMS ((void));
     {									\
       valueT count = ((FRAGP)->fr_next->fr_address			\
 		      - ((FRAGP)->fr_address + (FRAGP)->fr_fix));	\
-      unsigned char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;	\
+      char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;		\
       if ((count & 3) != 0)						\
 	{								\
 	  memset (dest, 0, (count & 3));				\
diff --git a/gas/config/tc-generic.c b/gas/config/tc-generic.c
index e69de29bb2d1..8028403550bd 100644
--- a/gas/config/tc-generic.c
+++ b/gas/config/tc-generic.c
@@ -0,0 +1,22 @@
+/* This file is tc-generic.c
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* This file is tc-generic.c and is intended to be a template for
+   target cpu specific files.  */
diff --git a/gas/config/tc-generic.h b/gas/config/tc-generic.h
index f3b676ba011a..fbeba9a25c11 100644
--- a/gas/config/tc-generic.h
+++ b/gas/config/tc-generic.h
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU General Public License along
    with GAS; see the file COPYING.  If not, write to the Free Software
-   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /*
  * This file is tc-generic.h and is intended to be a template for target cpu
diff --git a/gas/config/tc-h8300.c b/gas/config/tc-h8300.c
index 467d9bcdb26c..7db600c72bb8 100644
--- a/gas/config/tc-h8300.c
+++ b/gas/config/tc-h8300.c
@@ -1,6 +1,6 @@
 /* tc-h8300.c -- Assemble code for the Renesas H8/300
    Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000,
-   2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Written By Steve Chamberlain <sac@cygnus.com>.  */
 
@@ -25,10 +25,7 @@
 #include "as.h"
 #include "subsegs.h"
 #include "bfd.h"
-
-#ifdef BFD_ASSEMBLER
 #include "dwarf2dbg.h"
-#endif
 
 #define DEFINE_TABLE
 #define h8_opcodes ops
@@ -77,10 +74,8 @@ h8300hmode (int arg ATTRIBUTE_UNUSED)
 {
   Hmode = 1;
   Smode = 0;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300h))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -88,10 +83,8 @@ h8300smode (int arg ATTRIBUTE_UNUSED)
 {
   Smode = 1;
   Hmode = 1;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300s))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -100,10 +93,8 @@ h8300hnmode (int arg ATTRIBUTE_UNUSED)
   Hmode = 1;
   Smode = 0;
   Nmode = 1;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300hn))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -112,10 +103,8 @@ h8300snmode (int arg ATTRIBUTE_UNUSED)
   Smode = 1;
   Hmode = 1;
   Nmode = 1;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sn))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -124,10 +113,8 @@ h8300sxmode (int arg ATTRIBUTE_UNUSED)
   Smode = 1;
   Hmode = 1;
   SXmode = 1;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sx))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -137,10 +124,8 @@ h8300sxnmode (int arg ATTRIBUTE_UNUSED)
   Hmode = 1;
   SXmode = 1;
   Nmode = 1;
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300sxn))
     as_warn (_("could not set architecture and machine"));
-#endif
 }
 
 static void
@@ -184,8 +169,6 @@ const pseudo_typeS md_pseudo_table[] =
   {0, 0, 0}
 };
 
-const int md_reloc_size;
-
 const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant
@@ -208,10 +191,8 @@ md_begin (void)
   char prev_buffer[100];
   int idx = 0;
 
-#ifdef BFD_ASSEMBLER
   if (!bfd_set_arch_mach (stdoutput, bfd_arch_h8300, bfd_mach_h8300))
     as_warn (_("could not set architecture and machine"));
-#endif
 
   opcode_hash_control = hash_new ();
   prev_buffer[0] = 0;
@@ -978,7 +959,8 @@ get_mova_operands (char *op_end, struct h8_op *operand)
 static void
 get_rtsl_operands (char *ptr, struct h8_op *operand)
 {
-  int mode, num, num2, len, type = 0;
+  int mode, len, type = 0;
+  unsigned int num, num2;
 
   ptr++;
   if (*ptr == '(')
@@ -1004,7 +986,7 @@ get_rtsl_operands (char *ptr, struct h8_op *operand)
       ptr += len;
       /* CONST_xxx are used as placeholders in the opcode table.  */
       num = num2 - num;
-      if (num < 0 || num > 3)
+      if (num > 3)
 	{
 	  as_bad (_("invalid register list"));
 	  return;
@@ -1193,15 +1175,6 @@ get_specific (const struct h8_instruction *instruction,
 		      x |= x_size = L_32;
 		    }
 
-#if 0 /* ??? */
-		  /* Promote an L8 to L_16 if it makes us match.  */
-		  if ((op_mode == ABS || op_mode == DISP) && x_size == L_8)
-		    {
-		      if (op_size == L_16)
-			x_size = L_16;
-		    }
-#endif
-
 		  if (((x_size == L_16 && op_size == L_16U)
 		       || (x_size == L_8 && op_size == L_8U)
 		       || (x_size == L_3 && op_size == L_3NZ))
@@ -2025,33 +1998,15 @@ md_assemble (char *str)
 
   build_bytes (instruction, operand);
 
-#ifdef BFD_ASSEMBLER
   dwarf2_emit_insn (instruction->length);
-#endif
 }
 
-#ifndef BFD_ASSEMBLER
-void
-tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_crawl_symbol_chain \n"));
-}
-#endif
-
 symbolS *
 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
-#ifndef BFD_ASSEMBLER
-void
-tc_headers_hook (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_headers_hook \n"));
-}
-#endif
-
 /* Various routines to kill one day */
 /* Equal to MAX_PRECISION in atof-ieee.c */
 #define MAX_LITTLENUMS 6
@@ -2140,12 +2095,7 @@ tc_aout_fix_to_chars (void)
 }
 
 void
-md_convert_frag (
-#ifdef BFD_ASSEMBLER
-		 bfd *headers ATTRIBUTE_UNUSED,
-#else
-		 object_headers *headers ATTRIBUTE_UNUSED,
-#endif
+md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
 		 segT seg ATTRIBUTE_UNUSED,
 		 fragS *fragP ATTRIBUTE_UNUSED)
 {
@@ -2153,25 +2103,15 @@ md_convert_frag (
   abort ();
 }
 
-#ifdef BFD_ASSEMBLER
 valueT
 md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
   return ((size + (1 << align) - 1) & (-1 << align));
 }
-#else
-valueT
-md_section_align (segT seg, valueT size)
-{
-  return ((size + (1 << section_alignment[(int) seg]) - 1)
-	  & (-1 << section_alignment[(int) seg]));
-}
-#endif
-
 
 void
-md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
   long val = *valP;
@@ -2220,66 +2160,6 @@ md_pcrel_from (fixS *fixP ATTRIBUTE_UNUSED)
   abort ();
 }
 
-#ifndef BFD_ASSEMBLER
-void
-tc_reloc_mangle (fixS *fix_ptr, struct internal_reloc *intr, bfd_vma base)
-{
-  symbolS *symbol_ptr;
-
-  symbol_ptr = fix_ptr->fx_addsy;
-
-  /* If this relocation is attached to a symbol then it's ok
-     to output it.  */
-  if (fix_ptr->fx_r_type == TC_CONS_RELOC)
-    {
-      /* cons likes to create reloc32's whatever the size of the reloc..
-       */
-      switch (fix_ptr->fx_size)
-	{
-	case 4:
-	  intr->r_type = R_RELLONG;
-	  break;
-	case 2:
-	  intr->r_type = R_RELWORD;
-	  break;
-	case 1:
-	  intr->r_type = R_RELBYTE;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  else
-    {
-      intr->r_type = fix_ptr->fx_r_type;
-    }
-
-  intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
-  intr->r_offset = fix_ptr->fx_offset;
-
-  if (symbol_ptr)
-    {
-      if (symbol_ptr->sy_number != -1)
-	intr->r_symndx = symbol_ptr->sy_number;
-      else
-	{
-	  symbolS *segsym;
-
-	  /* This case arises when a reference is made to `.'.  */
-	  segsym = seg_info (S_GET_SEGMENT (symbol_ptr))->dot;
-	  if (segsym == NULL)
-	    intr->r_symndx = -1;
-	  else
-	    {
-	      intr->r_symndx = segsym->sy_number;
-	      intr->r_offset += S_GET_VALUE (symbol_ptr);
-	    }
-	}
-    }
-  else
-    intr->r_symndx = -1;
-}
-#else /* BFD_ASSEMBLER */
 arelent *
 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
@@ -2321,4 +2201,3 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 
   return rel;
 }
-#endif
diff --git a/gas/config/tc-h8300.h b/gas/config/tc-h8300.h
index 89351cbe9329..bfc8f724c543 100644
--- a/gas/config/tc-h8300.h
+++ b/gas/config/tc-h8300.h
@@ -1,6 +1,6 @@
 /* This file is tc-h8300.h
    Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
-   1997, 1998, 2000, 2002, 2003
+   1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_H8300
 
@@ -26,10 +26,8 @@
 
 #define TARGET_ARCH bfd_arch_h8300
 
-#ifdef BFD_ASSEMBLER
 /* Fixup debug sections since we will never relax them.  */
 #define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
-#endif
 #ifdef OBJ_ELF
 #define TARGET_FORMAT "elf32-h8300"
 #define LOCAL_LABEL_PREFIX '.'
@@ -37,24 +35,15 @@
 #define FAKE_LABEL_NAME ".L0\001"
 #endif
 
-#if ANSI_PROTOTYPES
 struct fix;
 struct internal_reloc;
-#endif
 
 #define WORKING_DOT_WORD
 
-/* This macro translates between an internal fix and a coff reloc type.  */
-#define TC_COFF_FIX2RTYPE(fixP) abort ();
-
-#define BFD_ARCH bfd_arch_h8300
 #define COFF_MAGIC ( Smode && Nmode ? 0x8304 : Hmode && Nmode ? 0x8303 : Smode ? 0x8302 : Hmode ? 0x8301 : 0x8300)
-#define TC_COUNT_RELOC(x) (1)
 #define IGNORE_NONSTANDARD_ESCAPES
 
 #define tc_coff_symbol_emit_hook(a) ; /* not used */
-#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
-extern void tc_reloc_mangle (struct fix *, struct internal_reloc *, bfd_vma);
 
 /* No shared lib support, so we don't need to ensure externally
    visible symbols can be overridden.  */
@@ -86,11 +75,7 @@ extern void tc_reloc_mangle (struct fix *, struct internal_reloc *, bfd_vma);
 #define tc_fix_adjustable(FIX) 0
 #endif
 
-#define TC_CONS_RELOC          (Hmode ? R_RELLONG: R_RELWORD)
-
-#define DO_NOT_STRIP 0
 #define LISTING_HEADER "Renesas H8/300 GAS "
-#define NEED_FX_R_TYPE 1
 #ifndef OBJ_ELF
 #define RELOC_32 1234
 #endif
diff --git a/gas/config/tc-h8500.c b/gas/config/tc-h8500.c
deleted file mode 100644
index cd4d76f8831c..000000000000
--- a/gas/config/tc-h8500.c
+++ /dev/null
@@ -1,1617 +0,0 @@
-/* tc-h8500.c -- Assemble code for the Renesas H8/500
-   Copyright 1993, 1994, 1995, 1998, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* Written By Steve Chamberlain <sac@cygnus.com>.  */
-
-#include <stdio.h>
-#include "as.h"
-#include "bfd.h"
-#include "subsegs.h"
-#define DEFINE_TABLE
-#define ASSEMBLER_TABLE
-#include "opcodes/h8500-opc.h"
-#include "safe-ctype.h"
-
-const char comment_chars[] = "!";
-const char line_separator_chars[] = ";";
-const char line_comment_chars[] = "!#";
-
-/* This table describes all the machine specific pseudo-ops the assembler
-   has to support.  The fields are:
-   pseudo-op name without dot
-   function to call to execute this pseudo-op
-   Integer arg to pass to the function
-   */
-
-const pseudo_typeS md_pseudo_table[] =
-{
-  {"int", cons, 2},
-  {"data.b", cons, 1},
-  {"data.w", cons, 2},
-  {"data.l", cons, 4},
-  {"form", listing_psize, 0},
-  {"heading", listing_title, 0},
-  {"import", s_ignore, 0},
-  {"page", listing_eject, 0},
-  {"program", s_ignore, 0},
-  {0, 0, 0}
-};
-
-const int md_reloc_size;
-
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant */
-/* As in 0f12.456 */
-/* or    0d1.2345e12 */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
-
-#define C(a,b) ENCODE_RELAX(a,b)
-#define ENCODE_RELAX(what,length) (((what) << 2) + (length))
-
-#define GET_WHAT(x) ((x>>2))
-
-#define BYTE_DISP 1
-#define WORD_DISP 2
-#define UNDEF_BYTE_DISP 0
-#define UNDEF_WORD_DISP 3
-
-#define BRANCH  1
-#define SCB_F   2
-#define SCB_TST 3
-#define END 4
-
-#define BYTE_F 127
-#define BYTE_B -126
-#define WORD_F 32767
-#define WORD_B 32768
-
-relax_typeS md_relax_table[C (END, 0)] = {
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-
-  /* BRANCH */
-  { 0,      0,       0, 0 },
-  { BYTE_F, BYTE_B,  2, C (BRANCH, WORD_DISP) },
-  { WORD_F, WORD_B,  3, 0 },
-  { 0,      0,       3, 0 },
-
-  /* SCB_F */
-  { 0,      0,       0, 0 },
-  { BYTE_F, BYTE_B,  3, C (SCB_F, WORD_DISP) },
-  { WORD_F, WORD_B,  8, 0 },
-  { 0,      0,       8, 0 },
-
-  /* SCB_TST */
-  { 0,      0,       0, 0 },
-  { BYTE_F, BYTE_B,  3, C (SCB_TST, WORD_DISP) },
-  { WORD_F, WORD_B, 10, 0 },
-  { 0,      0,      10, 0 }
-
-};
-
-static struct hash_control *opcode_hash_control;	/* Opcode mnemonics */
-
-/*
-  This function is called once, at assembler startup time.  This should
-  set up all the tables, etc. that the MD part of the assembler needs
-  */
-
-void
-md_begin ()
-{
-  const h8500_opcode_info *opcode;
-  char prev_buffer[100];
-  int idx = 0;
-
-  opcode_hash_control = hash_new ();
-  prev_buffer[0] = 0;
-
-  /* Insert unique names into hash table */
-  for (opcode = h8500_table; opcode->name; opcode++)
-    {
-      if (idx != opcode->idx)
-	{
-	  hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
-	  idx++;
-	}
-    }
-}
-
-static int rn;			/* register number used by RN */
-static int rs;			/* register number used by RS */
-static int rd;			/* register number used by RD */
-static int crb;			/* byte size cr */
-static int crw;			/* word sized cr */
-static int cr;			/* unknown size cr */
-
-static expressionS displacement;/* displacement expression */
-
-static int immediate_inpage;
-static expressionS immediate;	/* immediate expression */
-
-static expressionS absolute;	/* absolute expression */
-
-typedef struct
-{
-  int type;
-  int reg;
-  expressionS exp;
-  int page;
-}
-
-h8500_operand_info;
-
-/* Try to parse a reg name.  Return the number of chars consumed.  */
-
-static int parse_reg PARAMS ((char *, int *, int *));
-
-static int
-parse_reg (src, mode, reg)
-     char *src;
-     int *mode;
-     int *reg;
-{
-  char *end;
-  int len;
-
-  /* Cribbed from get_symbol_end().  */
-  if (!is_name_beginner (*src) || *src == '\001')
-    return 0;
-  end = src + 1;
-  while (is_part_of_name (*end) || *end == '\001')
-    end++;
-  len = end - src;
-
-  if (len == 2 && src[0] == 'r')
-    {
-      if (src[1] >= '0' && src[1] <= '7')
-	{
-	  *mode = RN;
-	  *reg = (src[1] - '0');
-	  return len;
-	}
-    }
-  if (len == 2 && src[0] == 's' && src[1] == 'p')
-    {
-      *mode = RN;
-      *reg = 7;
-      return len;
-    }
-  if (len == 3 && src[0] == 'c' && src[1] == 'c' && src[2] == 'r')
-    {
-      *mode = CRB;
-      *reg = 1;
-      return len;
-    }
-  if (len == 2 && src[0] == 's' && src[1] == 'r')
-    {
-      *mode = CRW;
-      *reg = 0;
-      return len;
-    }
-  if (len == 2 && src[0] == 'b' && src[1] == 'r')
-    {
-      *mode = CRB;
-      *reg = 3;
-      return len;
-    }
-  if (len == 2 && src[0] == 'e' && src[1] == 'p')
-    {
-      *mode = CRB;
-      *reg = 4;
-      return len;
-    }
-  if (len == 2 && src[0] == 'd' && src[1] == 'p')
-    {
-      *mode = CRB;
-      *reg = 5;
-      return len;
-    }
-  if (len == 2 && src[0] == 't' && src[1] == 'p')
-    {
-      *mode = CRB;
-      *reg = 7;
-      return len;
-    }
-  if (len == 2 && src[0] == 'f' && src[1] == 'p')
-    {
-      *mode = RN;
-      *reg = 6;
-      return len;
-    }
-  return 0;
-}
-
-static char *parse_exp PARAMS ((char *, expressionS *, int *));
-
-static char *
-parse_exp (s, op, page)
-     char *s;
-     expressionS *op;
-     int *page;
-{
-  char *save;
-  char *new;
-
-  save = input_line_pointer;
-
-  *page = 0;
-  if (s[0] == '%')
-    {
-      if (s[1] == 'p' && s[2] == 'a' && s[3] == 'g' && s[4] == 'e')
-	{
-	  s += 5;
-	  *page = 'p';
-	}
-      if (s[1] == 'h' && s[2] == 'i' && s[3] == '1' && s[4] == '6')
-	{
-	  s += 5;
-	  *page = 'h';
-	}
-      else if (s[1] == 'o' && s[2] == 'f' && s[3] == 'f')
-	{
-	  s += 4;
-	  *page = 'o';
-	}
-    }
-
-  input_line_pointer = s;
-
-  expression (op);
-  if (op->X_op == O_absent)
-    as_bad (_("missing operand"));
-  new = input_line_pointer;
-  input_line_pointer = save;
-  return new;
-}
-
-typedef enum
-  {
-    exp_signed, exp_unsigned, exp_sandu
-  } sign_type;
-
-static char *skip_colonthing
-  PARAMS ((sign_type, char *, h8500_operand_info *, int, int, int, int));
-
-static char *
-skip_colonthing (sign, ptr, exp, def, size8, size16, size24)
-     sign_type sign;
-     char *ptr;
-     h8500_operand_info *exp;
-     int def;
-     int size8;
-     int size16;
-     int size24;
-{
-  ptr = parse_exp (ptr, &exp->exp, &exp->page);
-  if (*ptr == ':')
-    {
-      ptr++;
-      if (*ptr == '8')
-	{
-	  ptr++;
-	  exp->type = size8;
-	}
-      else if (ptr[0] == '1' && ptr[1] == '6')
-	{
-	  ptr += 2;
-	  exp->type = size16;
-	}
-      else if (ptr[0] == '2' && ptr[1] == '4')
-	{
-	  if (!size24)
-	    {
-	      as_bad (_(":24 not valid for this opcode"));
-	    }
-	  ptr += 2;
-	  exp->type = size24;
-	}
-      else
-	{
-	  as_bad (_("expect :8,:16 or :24"));
-	  exp->type = size16;
-	}
-    }
-  else
-    {
-      if (exp->page == 'p')
-	{
-	  exp->type = IMM8;
-	}
-      else if (exp->page == 'h')
-	{
-	  exp->type = IMM16;
-	}
-      else
-	{
-	  /* Let's work out the size from the context */
-	  int n = exp->exp.X_add_number;
-	  if (size8
-	      && exp->exp.X_op == O_constant
-	      && ((sign == exp_signed && (n >= -128 && n <= 127))
-		  || (sign == exp_unsigned && (n >= 0 && (n <= 255)))
-		  || (sign == exp_sandu && (n >= -128 && (n <= 255)))))
-	    {
-	      exp->type = size8;
-	    }
-	  else
-	    {
-	      exp->type = def;
-	    }
-	}
-    }
-  return ptr;
-}
-
-static int parse_reglist PARAMS ((char *, h8500_operand_info *));
-
-static int
-parse_reglist (src, op)
-     char *src;
-     h8500_operand_info *op;
-{
-  int mode;
-  int rn;
-  int mask = 0;
-  int rm;
-  int idx = 1;			/* skip ( */
-
-  while (src[idx] && src[idx] != ')')
-    {
-      int done = parse_reg (src + idx, &mode, &rn);
-
-      if (done)
-	{
-	  idx += done;
-	  mask |= 1 << rn;
-	}
-      else
-	{
-	  as_bad (_("syntax error in reg list"));
-	  return 0;
-	}
-      if (src[idx] == '-')
-	{
-	  idx++;
-	  done = parse_reg (src + idx, &mode, &rm);
-	  if (done)
-	    {
-	      idx += done;
-	      while (rn <= rm)
-		{
-		  mask |= 1 << rn;
-		  rn++;
-		}
-	    }
-	  else
-	    {
-	      as_bad (_("missing final register in range"));
-	    }
-	}
-      if (src[idx] == ',')
-	idx++;
-    }
-  idx++;
-  op->exp.X_add_symbol = 0;
-  op->exp.X_op_symbol = 0;
-  op->exp.X_add_number = mask;
-  op->exp.X_op = O_constant;
-  op->exp.X_unsigned = 1;
-  op->type = IMM8;
-  return idx;
-
-}
-
-/* The many forms of operand:
-
-   Rn			Register direct
-   @Rn			Register indirect
-   @(disp[:size], Rn)	Register indirect with displacement
-   @Rn+
-   @-Rn
-   @aa[:size]		absolute
-   #xx[:size]		immediate data
-
-   */
-
-static void get_operand PARAMS ((char **, h8500_operand_info *, char));
-
-static void
-get_operand (ptr, op, ispage)
-     char **ptr;
-     h8500_operand_info *op;
-     char ispage;
-{
-  char *src = *ptr;
-  int mode;
-  unsigned int num;
-  unsigned int len;
-  op->page = 0;
-  if (src[0] == '(' && src[1] == 'r')
-    {
-      /* This is a register list */
-      *ptr = src + parse_reglist (src, op);
-      return;
-    }
-
-  len = parse_reg (src, &op->type, &op->reg);
-
-  if (len)
-    {
-      *ptr = src + len;
-      return;
-    }
-
-  if (*src == '@')
-    {
-      src++;
-      if (*src == '-')
-	{
-	  src++;
-	  len = parse_reg (src, &mode, &num);
-	  if (len == 0)
-	    {
-	      /* Oops, not a reg after all, must be ordinary exp */
-	      src--;
-	      /* must be a symbol */
-	      *ptr = skip_colonthing (exp_unsigned, src,
-				      op, ABS16, ABS8, ABS16, ABS24);
-	      return;
-	    }
-
-	  op->type = RNDEC;
-	  op->reg = num;
-	  *ptr = src + len;
-	  return;
-	}
-      if (*src == '(')
-	{
-	  /* Disp */
-	  src++;
-
-	  src = skip_colonthing (exp_signed, src,
-				 op, RNIND_D16, RNIND_D8, RNIND_D16, 0);
-
-	  if (*src != ',')
-	    {
-	      as_bad (_("expected @(exp, Rn)"));
-	      return;
-	    }
-	  src++;
-	  len = parse_reg (src, &mode, &op->reg);
-	  if (len == 0 || mode != RN)
-	    {
-	      as_bad (_("expected @(exp, Rn)"));
-	      return;
-	    }
-	  src += len;
-	  if (*src != ')')
-	    {
-	      as_bad (_("expected @(exp, Rn)"));
-	      return;
-	    }
-	  *ptr = src + 1;
-	  return;
-	}
-      len = parse_reg (src, &mode, &num);
-
-      if (len)
-	{
-	  src += len;
-	  if (*src == '+')
-	    {
-	      src++;
-	      if (mode != RN)
-		{
-		  as_bad (_("@Rn+ needs word register"));
-		  return;
-		}
-	      op->type = RNINC;
-	      op->reg = num;
-	      *ptr = src;
-	      return;
-	    }
-	  if (mode != RN)
-	    {
-	      as_bad (_("@Rn needs word register"));
-	      return;
-	    }
-	  op->type = RNIND;
-	  op->reg = num;
-	  *ptr = src;
-	  return;
-	}
-      else
-	{
-	  /* must be a symbol */
-	  *ptr =
-	    skip_colonthing (exp_unsigned, src, op,
-			     ispage ? ABS24 : ABS16, ABS8, ABS16, ABS24);
-	  return;
-	}
-    }
-
-  if (*src == '#')
-    {
-      src++;
-      *ptr = skip_colonthing (exp_sandu, src, op, IMM16, IMM8, IMM16, ABS24);
-      return;
-    }
-  else
-    {
-      *ptr = skip_colonthing (exp_signed, src, op,
-			      ispage ? ABS24 : PCREL8, PCREL8, PCREL16, ABS24);
-    }
-}
-
-static char *get_operands
-  PARAMS ((h8500_opcode_info *, char *, h8500_operand_info *));
-
-static char *
-get_operands (info, args, operand)
-     h8500_opcode_info *info;
-     char *args;
-     h8500_operand_info *operand;
-{
-  char *ptr = args;
-
-  switch (info->nargs)
-    {
-    case 0:
-      operand[0].type = 0;
-      operand[1].type = 0;
-      break;
-
-    case 1:
-      ptr++;
-      get_operand (&ptr, operand + 0, info->name[0] == 'p');
-      operand[1].type = 0;
-      break;
-
-    case 2:
-      ptr++;
-      get_operand (&ptr, operand + 0, 0);
-      if (*ptr == ',')
-	ptr++;
-      get_operand (&ptr, operand + 1, 0);
-      break;
-
-    default:
-      abort ();
-    }
-
-  return ptr;
-}
-
-/* Passed a pointer to a list of opcodes which use different
-   addressing modes, return the opcode which matches the opcodes
-   provided.  */
-
-int pcrel8;			/* Set when we've seen a pcrel operand */
-
-static h8500_opcode_info *get_specific
-  PARAMS ((h8500_opcode_info *, h8500_operand_info *));
-
-static h8500_opcode_info *
-get_specific (opcode, operands)
-     h8500_opcode_info *opcode;
-     h8500_operand_info *operands;
-{
-  h8500_opcode_info *this_try = opcode;
-  int found = 0;
-  unsigned int noperands = opcode->nargs;
-  int this_index = opcode->idx;
-
-  while (this_index == opcode->idx && !found)
-    {
-      unsigned int i;
-
-      this_try = opcode++;
-
-      /* look at both operands needed by the opcodes and provided by
-       the user*/
-      for (i = 0; i < noperands; i++)
-	{
-	  h8500_operand_info *user = operands + i;
-
-	  switch (this_try->arg_type[i])
-	    {
-	    case FPIND_D8:
-	      /* Opcode needs (disp:8,fp) */
-	      if (user->type == RNIND_D8 && user->reg == 6)
-		{
-		  displacement = user->exp;
-		  continue;
-		}
-	      break;
-	    case RDIND_D16:
-	      if (user->type == RNIND_D16)
-		{
-		  displacement = user->exp;
-		  rd = user->reg;
-		  continue;
-		}
-	      break;
-	    case RDIND_D8:
-	      if (user->type == RNIND_D8)
-		{
-		  displacement = user->exp;
-		  rd = user->reg;
-		  continue;
-		}
-	      break;
-	    case RNIND_D16:
-	    case RNIND_D8:
-	      if (user->type == this_try->arg_type[i])
-		{
-		  displacement = user->exp;
-		  rn = user->reg;
-		  continue;
-		}
-	      break;
-
-	    case SPDEC:
-	      if (user->type == RNDEC && user->reg == 7)
-		{
-		  continue;
-		}
-	      break;
-	    case SPINC:
-	      if (user->type == RNINC && user->reg == 7)
-		{
-		  continue;
-		}
-	      break;
-	    case ABS16:
-	      if (user->type == ABS16)
-		{
-		  absolute = user->exp;
-		  continue;
-		}
-	      break;
-	    case ABS8:
-	      if (user->type == ABS8)
-		{
-		  absolute = user->exp;
-		  continue;
-		}
-	      break;
-	    case ABS24:
-	      if (user->type == ABS24)
-		{
-		  absolute = user->exp;
-		  continue;
-		}
-	      break;
-
-	    case CRB:
-	      if ((user->type == CRB || user->type == CR) && user->reg != 0)
-		{
-		  crb = user->reg;
-		  continue;
-		}
-	      break;
-	    case CRW:
-	      if ((user->type == CRW || user->type == CR) && user->reg == 0)
-		{
-		  crw = user->reg;
-		  continue;
-		}
-	      break;
-	    case DISP16:
-	      if (user->type == DISP16)
-		{
-		  displacement = user->exp;
-		  continue;
-		}
-	      break;
-	    case DISP8:
-	      if (user->type == DISP8)
-		{
-		  displacement = user->exp;
-		  continue;
-		}
-	      break;
-	    case FP:
-	      if (user->type == RN && user->reg == 6)
-		{
-		  continue;
-		}
-	      break;
-	    case PCREL16:
-	      if (user->type == PCREL16)
-		{
-		  displacement = user->exp;
-		  continue;
-		}
-	      break;
-	    case PCREL8:
-	      if (user->type == PCREL8)
-		{
-		  displacement = user->exp;
-		  pcrel8 = 1;
-		  continue;
-		}
-	      break;
-
-	    case IMM16:
-	      if (user->type == IMM16
-		  || user->type == IMM8)
-		{
-		  immediate_inpage = user->page;
-		  immediate = user->exp;
-		  continue;
-		}
-	      break;
-	    case RLIST:
-	    case IMM8:
-	      if (user->type == IMM8)
-		{
-		  immediate_inpage = user->page;
-		  immediate = user->exp;
-		  continue;
-		}
-	      break;
-	    case IMM4:
-	      if (user->type == IMM8)
-		{
-		  immediate_inpage = user->page;
-		  immediate = user->exp;
-		  continue;
-		}
-	      break;
-	    case QIM:
-	      if (user->type == IMM8
-		  && user->exp.X_op == O_constant
-		  &&
-		  (user->exp.X_add_number == -2
-		   || user->exp.X_add_number == -1
-		   || user->exp.X_add_number == 1
-		   || user->exp.X_add_number == 2))
-		{
-		  immediate_inpage = user->page;
-		  immediate = user->exp;
-		  continue;
-		}
-	      break;
-	    case RD:
-	      if (user->type == RN)
-		{
-		  rd = user->reg;
-		  continue;
-		}
-	      break;
-	    case RS:
-	      if (user->type == RN)
-		{
-		  rs = user->reg;
-		  continue;
-		}
-	      break;
-	    case RDIND:
-	      if (user->type == RNIND)
-		{
-		  rd = user->reg;
-		  continue;
-
-		}
-	      break;
-	    case RNINC:
-	    case RNIND:
-	    case RNDEC:
-	    case RN:
-
-	      if (user->type == this_try->arg_type[i])
-		{
-		  rn = user->reg;
-		  continue;
-		}
-	      break;
-	    case SP:
-	      if (user->type == RN && user->reg == 7)
-		{
-		  continue;
-		}
-	      break;
-	    default:
-	      printf (_("unhandled %d\n"), this_try->arg_type[i]);
-	      break;
-	    }
-
-	  /* If we get here this didn't work out */
-	  goto fail;
-	}
-      found = 1;
-    fail:;
-
-    }
-
-  if (found)
-    return this_try;
-  else
-    return 0;
-}
-
-static int check PARAMS ((expressionS *, int, int));
-
-static int
-check (operand, low, high)
-     expressionS *operand;
-     int low;
-     int high;
-{
-  if (operand->X_op != O_constant
-      || operand->X_add_number < low
-      || operand->X_add_number > high)
-    {
-      as_bad (_("operand must be absolute in range %d..%d"), low, high);
-    }
-  return operand->X_add_number;
-}
-
-static void insert PARAMS ((char *, int, expressionS *, int, int));
-
-static void
-insert (output, index, exp, reloc, pcrel)
-     char *output;
-     int index;
-     expressionS *exp;
-     int reloc;
-     int pcrel;
-{
-  fix_new_exp (frag_now,
-	       output - frag_now->fr_literal + index,
-	       4,	       	/* always say size is 4, but we know better */
-	       exp,
-	       pcrel,
-	       reloc);
-}
-
-static void build_relaxable_instruction
-  PARAMS ((h8500_opcode_info *, h8500_operand_info *));
-
-static void
-build_relaxable_instruction (opcode, operand)
-     h8500_opcode_info *opcode;
-     h8500_operand_info *operand ATTRIBUTE_UNUSED;
-{
-  /* All relaxable instructions start life as two bytes but can become
-     three bytes long if a lonely branch and up to 9 bytes if long
-     scb.  */
-  char *p;
-  int len;
-  int type;
-
-  if (opcode->bytes[0].contents == 0x01)
-    {
-      type = SCB_F;
-    }
-  else if (opcode->bytes[0].contents == 0x06
-	   || opcode->bytes[0].contents == 0x07)
-    {
-      type = SCB_TST;
-    }
-  else
-    {
-      type = BRANCH;
-    }
-
-  p = frag_var (rs_machine_dependent,
-		md_relax_table[C (type, WORD_DISP)].rlx_length,
-		len = md_relax_table[C (type, BYTE_DISP)].rlx_length,
-		C (type, UNDEF_BYTE_DISP),
-		displacement.X_add_symbol,
-		displacement.X_add_number,
-		0);
-
-  p[0] = opcode->bytes[0].contents;
-  if (type != BRANCH)
-    {
-      p[1] = opcode->bytes[1].contents | rs;
-    }
-}
-
-/* Now we know what sort of opcodes it is, let's build the bytes.  */
-
-static void build_bytes PARAMS ((h8500_opcode_info *, h8500_operand_info *));
-
-static void
-build_bytes (opcode, operand)
-     h8500_opcode_info *opcode;
-     h8500_operand_info *operand;
-{
-  int index;
-
-  if (pcrel8)
-    {
-      pcrel8 = 0;
-      build_relaxable_instruction (opcode, operand);
-    }
-  else
-    {
-      char *output = frag_more (opcode->length);
-
-      memset (output, 0, opcode->length);
-      for (index = 0; index < opcode->length; index++)
-	{
-	  output[index] = opcode->bytes[index].contents;
-
-	  switch (opcode->bytes[index].insert)
-	    {
-	    default:
-	      printf (_("failed for %d\n"), opcode->bytes[index].insert);
-	      break;
-	    case 0:
-	      break;
-	    case RN:
-	      output[index] |= rn;
-	      break;
-	    case RD:
-	    case RDIND:
-	      output[index] |= rd;
-	      break;
-	    case RS:
-	      output[index] |= rs;
-	      break;
-	    case DISP16:
-	      insert (output, index, &displacement, R_H8500_IMM16, 0);
-	      index++;
-	      break;
-	    case DISP8:
-	    case FPIND_D8:
-	      insert (output, index, &displacement, R_H8500_IMM8, 0);
-	      break;
-	    case IMM16:
-	      {
-		int p;
-
-		switch (immediate_inpage)
-		  {
-		  case 'p':
-		    p = R_H8500_HIGH16;
-		    break;
-		  case 'h':
-		    p = R_H8500_HIGH16;
-		    break;
-		  default:
-		    p = R_H8500_IMM16;
-		    break;
-		  }
-		insert (output, index, &immediate, p, 0);
-	      }
-	      index++;
-	      break;
-	    case RLIST:
-	    case IMM8:
-	      if (immediate_inpage)
-		insert (output, index, &immediate, R_H8500_HIGH8, 0);
-	      else
-		insert (output, index, &immediate, R_H8500_IMM8, 0);
-	      break;
-	    case PCREL16:
-	      insert (output, index, &displacement, R_H8500_PCREL16, 1);
-	      index++;
-	      break;
-	    case PCREL8:
-	      insert (output, index, &displacement, R_H8500_PCREL8, 1);
-	      break;
-	    case IMM4:
-	      output[index] |= check (&immediate, 0, 15);
-	      break;
-	    case CR:
-	      output[index] |= cr;
-	      if (cr == 0)
-		output[0] |= 0x8;
-	      else
-		output[0] &= ~0x8;
-	      break;
-	    case CRB:
-	      output[index] |= crb;
-	      output[0] &= ~0x8;
-	      break;
-	    case CRW:
-	      output[index] |= crw;
-	      output[0] |= 0x8;
-	      break;
-	    case ABS24:
-	      insert (output, index, &absolute, R_H8500_IMM24, 0);
-	      index += 2;
-	      break;
-	    case ABS16:
-	      insert (output, index, &absolute, R_H8500_IMM16, 0);
-	      index++;
-	      break;
-	    case ABS8:
-	      insert (output, index, &absolute, R_H8500_IMM8, 0);
-	      break;
-	    case QIM:
-	      switch (immediate.X_add_number)
-		{
-		case -2:
-		  output[index] |= 0x5;
-		  break;
-		case -1:
-		  output[index] |= 0x4;
-		  break;
-		case 1:
-		  output[index] |= 0;
-		  break;
-		case 2:
-		  output[index] |= 1;
-		  break;
-		}
-	      break;
-	    }
-	}
-    }
-}
-
-/* This is the guts of the machine-dependent assembler.  STR points to
-   a machine dependent instruction.  This function is supposed to emit
-   the frags/bytes it assembles to.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  char *op_start;
-  char *op_end;
-  h8500_operand_info operand[2];
-  h8500_opcode_info *opcode;
-  h8500_opcode_info *prev_opcode;
-  char name[11];
-
-  int nlen = 0;
-
-  /* Drop leading whitespace.  */
-  while (*str == ' ')
-    str++;
-
-  /* Find the op code end.  */
-  for (op_start = op_end = str;
-       !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
-       op_end++)
-    {
-      if (			/**op_end != '.'
-	  && *op_end != ':'
-	   	   	   	  && */ nlen < 10)
-	{
-	  name[nlen++] = *op_end;
-	}
-    }
-  name[nlen] = 0;
-
-  if (op_end == op_start)
-    as_bad (_("can't find opcode "));
-
-  opcode = (h8500_opcode_info *) hash_find (opcode_hash_control, name);
-
-  if (opcode == NULL)
-    {
-      as_bad (_("unknown opcode"));
-      return;
-    }
-
-  get_operands (opcode, op_end, operand);
-  prev_opcode = opcode;
-
-  opcode = get_specific (opcode, operand);
-
-  if (opcode == 0)
-    {
-      /* Couldn't find an opcode which matched the operands */
-      char *where = frag_more (2);
-
-      where[0] = 0x0;
-      where[1] = 0x0;
-      as_bad (_("invalid operands for opcode"));
-      return;
-    }
-
-  build_bytes (opcode, operand);
-}
-
-void
-tc_crawl_symbol_chain (headers)
-     object_headers *headers ATTRIBUTE_UNUSED;
-{
-  printf (_("call to tc_crawl_symbol_chain \n"));
-}
-
-symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-void
-tc_headers_hook (headers)
-     object_headers *headers ATTRIBUTE_UNUSED;
-{
-  printf (_("call to tc_headers_hook \n"));
-}
-
-/* Various routines to kill one day.  */
-/* Equal to MAX_PRECISION in atof-ieee.c.  */
-#define MAX_LITTLENUMS 6
-
-/* Turn a string in input_line_pointer into a floating point constant
-   of type type, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.  */
-
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to MD_ATOF()");
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  for (wordP = words; prec--;)
-    {
-      md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return 0;
-}
-
-const char *md_shortopts = "";
-struct option md_longopts[] = {
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
-{
-}
-
-static void wordify_scb PARAMS ((char *, int *, int *));
-
-static void
-wordify_scb (buffer, disp_size, inst_size)
-     char *buffer;
-     int *disp_size;
-     int *inst_size;
-{
-  int rn = buffer[1] & 0x7;
-
-  switch (buffer[0])
-    {
-    case 0x0e:			/* BSR */
-    case 0x20:
-    case 0x21:
-    case 0x22:
-    case 0x23:
-    case 0x24:
-    case 0x25:
-    case 0x26:
-    case 0x27:
-    case 0x28:
-    case 0x29:
-    case 0x2a:
-    case 0x2b:
-    case 0x2c:
-    case 0x2d:
-    case 0x2e:
-    case 0x2f:
-      buffer[0] |= 0x10;
-      buffer[1] = 0;
-      buffer[2] = 0;
-      *disp_size = 2;
-      *inst_size = 1;
-      return;
-    default:
-      abort ();
-
-    case 0x01:
-      *inst_size = 6;
-      *disp_size = 2;
-      break;
-    case 0x06:
-      *inst_size = 8;
-      *disp_size = 2;
-
-      *buffer++ = 0x26;		/* bne + 8 */
-      *buffer++ = 0x08;
-      break;
-    case 0x07:
-      *inst_size = 8;
-      *disp_size = 2;
-      *buffer++ = 0x27;		/* bne + 8 */
-      *buffer++ = 0x08;
-      break;
-
-    }
-  *buffer++ = 0xa8 | rn;	/* addq -1,rn */
-  *buffer++ = 0x0c;
-  *buffer++ = 0x04;		/* cmp #0xff:8, rn */
-  *buffer++ = 0xff;
-  *buffer++ = 0x70 | rn;
-  *buffer++ = 0x36;		/* bne ...  */
-  *buffer++ = 0;
-  *buffer++ = 0;
-}
-
-/* Called after relaxing, change the frags so they know how big they
-   are.  */
-
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-{
-  int disp_size = 0;
-  int inst_size = 0;
-  char *buffer = fragP->fr_fix + fragP->fr_literal;
-
-  switch (fragP->fr_subtype)
-    {
-    case C (BRANCH, BYTE_DISP):
-      disp_size = 1;
-      inst_size = 1;
-      break;
-
-    case C (SCB_F, BYTE_DISP):
-    case C (SCB_TST, BYTE_DISP):
-      disp_size = 1;
-      inst_size = 2;
-      break;
-
-      /* Branches to a known 16 bit displacement.  */
-
-      /* Turn on the 16bit bit.  */
-    case C (BRANCH, WORD_DISP):
-    case C (SCB_F, WORD_DISP):
-    case C (SCB_TST, WORD_DISP):
-      wordify_scb (buffer, &disp_size, &inst_size);
-      break;
-
-    case C (BRANCH, UNDEF_WORD_DISP):
-    case C (SCB_F, UNDEF_WORD_DISP):
-    case C (SCB_TST, UNDEF_WORD_DISP):
-      /* This tried to be relaxed, but didn't manage it, it now needs
-	 a fix.  */
-      wordify_scb (buffer, &disp_size, &inst_size);
-
-      /* Make a reloc */
-      fix_new (fragP,
-	       fragP->fr_fix + inst_size,
-	       4,
-	       fragP->fr_symbol,
-	       fragP->fr_offset,
-	       0,
-	       R_H8500_PCREL16);
-
-      fragP->fr_fix += disp_size + inst_size;
-      return;
-      break;
-    default:
-      abort ();
-    }
-  if (inst_size)
-    {
-      /* Get the address of the end of the instruction */
-      int next_inst = fragP->fr_fix + fragP->fr_address + disp_size + inst_size;
-      int targ_addr = (S_GET_VALUE (fragP->fr_symbol) +
-		       fragP->fr_offset);
-      int disp = targ_addr - next_inst;
-
-      md_number_to_chars (buffer + inst_size, disp, disp_size);
-      fragP->fr_fix += disp_size + inst_size;
-    }
-}
-
-valueT
-md_section_align (seg, size)
-     segT seg ;
-     valueT size;
-{
-  return ((size + (1 << section_alignment[(int) seg]) - 1)
-	  & (-1 << section_alignment[(int) seg]));
-
-}
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = * (long *) valP;
-  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-
-  if (fixP->fx_r_type == 0)
-    fixP->fx_r_type = fixP->fx_size == 4 ? R_H8500_IMM32 : R_H8500_IMM16;
-
-  switch (fixP->fx_r_type)
-    {
-    case R_H8500_IMM8:
-    case R_H8500_PCREL8:
-      *buf++ = val;
-      break;
-    case R_H8500_IMM16:
-    case R_H8500_LOW16:
-    case R_H8500_PCREL16:
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-    case R_H8500_HIGH8:
-      *buf++ = val >> 16;
-      break;
-    case R_H8500_HIGH16:
-      *buf++ = val >> 24;
-      *buf++ = val >> 16;
-      break;
-    case R_H8500_IMM24:
-      *buf++ = (val >> 16);
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-    case R_H8500_IMM32:
-      *buf++ = (val >> 24);
-      *buf++ = (val >> 16);
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-    default:
-      abort ();
-    }
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-}
-
-/* Called just before address relaxation, return the length
-   by which a fragment must grow to reach it's destination.  */
-
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS *fragP;
-     register segT segment_type;
-{
-  int what;
-
-  switch (fragP->fr_subtype)
-    {
-    default:
-      abort ();
-
-    case C (BRANCH, UNDEF_BYTE_DISP):
-    case C (SCB_F, UNDEF_BYTE_DISP):
-    case C (SCB_TST, UNDEF_BYTE_DISP):
-      what = GET_WHAT (fragP->fr_subtype);
-      /* used to be a branch to somewhere which was unknown */
-      if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
-	{
-	  /* Got a symbol and it's defined in this segment, become byte
-	     sized - maybe it will fix up.  */
-	  fragP->fr_subtype = C (what, BYTE_DISP);
-	}
-      else
-	{
-	  /* Its got a segment, but its not ours, so it will always be
-             long.  */
-	  fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
-	}
-      break;
-
-    case C (BRANCH, BYTE_DISP):
-    case C (BRANCH, WORD_DISP):
-    case C (BRANCH, UNDEF_WORD_DISP):
-    case C (SCB_F, BYTE_DISP):
-    case C (SCB_F, WORD_DISP):
-    case C (SCB_F, UNDEF_WORD_DISP):
-    case C (SCB_TST, BYTE_DISP):
-    case C (SCB_TST, WORD_DISP):
-    case C (SCB_TST, UNDEF_WORD_DISP):
-      /* When relaxing a section for the second time, we don't need to
-	 do anything besides return the current size.  */
-      break;
-    }
-
-  return md_relax_table[fragP->fr_subtype].rlx_length;
-}
-
-/* Put number into target byte order.  */
-
-void
-md_number_to_chars (ptr, use, nbytes)
-     char *ptr;
-     valueT use;
-     int nbytes;
-{
-  number_to_chars_bigendian (ptr, use, nbytes);
-}
-
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
-}
-
-void
-tc_coff_symbol_emit_hook (ignore)
-     symbolS *ignore ATTRIBUTE_UNUSED;
-{
-}
-
-short
-tc_coff_fix2rtype (fix_ptr)
-     fixS *fix_ptr;
-{
-  if (fix_ptr->fx_r_type == RELOC_32)
-    {
-      /* cons likes to create reloc32's whatever the size of the reloc..
-     */
-      switch (fix_ptr->fx_size)
-	{
-	case 2:
-	  return R_H8500_IMM16;
-	  break;
-	case 1:
-	  return R_H8500_IMM8;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  return fix_ptr->fx_r_type;
-}
-
-void
-tc_reloc_mangle (fix_ptr, intr, base)
-     fixS *fix_ptr;
-     struct internal_reloc *intr;
-     bfd_vma base;
-
-{
-  symbolS *symbol_ptr;
-
-  symbol_ptr = fix_ptr->fx_addsy;
-
-  /* If this relocation is attached to a symbol then it's ok
-     to output it */
-  if (fix_ptr->fx_r_type == RELOC_32)
-    {
-      /* cons likes to create reloc32's whatever the size of the reloc..
-       */
-      switch (fix_ptr->fx_size)
-	{
-	case 2:
-	  intr->r_type = R_IMM16;
-	  break;
-	case 1:
-	  intr->r_type = R_IMM8;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  else
-    {
-      intr->r_type = fix_ptr->fx_r_type;
-    }
-
-  intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
-  intr->r_offset = fix_ptr->fx_offset;
-
-  /* Turn the segment of the symbol into an offset.  */
-  if (symbol_ptr)
-    {
-      symbolS *dot;
-
-      dot = segment_info[S_GET_SEGMENT (symbol_ptr)].dot;
-      if (dot)
-	{
-#if 0
-	  intr->r_offset -=
-	    segment_info[S_GET_SEGMENT (symbol_ptr)].scnhdr.s_paddr;
-#endif
-	  intr->r_offset += S_GET_VALUE (symbol_ptr);
-	  intr->r_symndx = dot->sy_number;
-	}
-      else
-	{
-	  intr->r_symndx = symbol_ptr->sy_number;
-	}
-
-    }
-  else
-    {
-      intr->r_symndx = -1;
-    }
-
-}
-
-int
-start_label (ptr)
-     char *ptr;
-{
-  /* Check for :s.w */
-  if (ISALPHA (ptr[1]) && ptr[2] == '.')
-    return 0;
-  /* Check for :s */
-  if (ISALPHA (ptr[1]) && !ISALPHA (ptr[2]))
-    return 0;
-  return 1;
-}
-
-int
-tc_coff_sizemachdep (frag)
-     fragS *frag;
-{
-  return md_relax_table[frag->fr_subtype].rlx_length;
-}
diff --git a/gas/config/tc-h8500.h b/gas/config/tc-h8500.h
deleted file mode 100644
index 5902524d4f17..000000000000
--- a/gas/config/tc-h8500.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* This file is tc-h8500.h
-   Copyright 1993, 1995, 1997, 1998, 2000, 2003 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define TC_H8500
-
-#define TARGET_BYTES_BIG_ENDIAN 1
-
-#if ANSI_PROTOTYPES
-struct internal_reloc;
-#endif
-
-#define WORKING_DOT_WORD
-
-/* This macro translates between an internal fix and a coff reloc type.  */
-#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
-
-#define BFD_ARCH bfd_arch_h8500
-#define COFF_MAGIC 0x8500
-#define TC_COUNT_RELOC(x) ((x)->fx_addsy||(x)->fx_subsy)
-#define IGNORE_NONSTANDARD_ESCAPES
-
-#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
-extern void tc_reloc_mangle
-  PARAMS ((struct fix *, struct internal_reloc *, bfd_vma));
-
-#define DO_NOT_STRIP 0
-#define LISTING_HEADER "Renesas H8/500 GAS "
-#define NEED_FX_R_TYPE 1
-#define RELOC_32 1234
-
-#define TC_START_LABEL(ch, ptr)  (ch == ':' && start_label(ptr))
-int start_label PARAMS ((char *));
-
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
-int tc_coff_sizemachdep PARAMS ((struct frag *));
-
-#define md_operand(x)
-
-extern struct relax_type md_relax_table[];
-#define TC_GENERIC_RELAX_TABLE md_relax_table
diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c
index 77563a99bee5..8ae5a57e9039 100644
--- a/gas/config/tc-hppa.c
+++ b/gas/config/tc-hppa.c
@@ -1,6 +1,6 @@
 /* tc-hppa.c -- Assemble for the PA
    Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
-   2002, 2003 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* HP PA-RISC support was contributed by the Center for Software Science
    at the University of Utah.  */
@@ -363,6 +363,9 @@ struct default_subspace_dict
     /* Nonzero if this subspace contains only code.  */
     char code_only;
 
+    /* Nonzero if this is a comdat subspace.  */
+    char comdat;
+
     /* Nonzero if this is a common subspace.  */
     char common;
 
@@ -544,7 +547,7 @@ static int need_pa11_opcode PARAMS ((void));
 static int pa_parse_number PARAMS ((char **, int));
 static label_symbol_struct *pa_get_label PARAMS ((void));
 #ifdef OBJ_SOM
-static int log2 PARAMS ((int));
+static int exact_log2 PARAMS ((int));
 static void pa_compiler PARAMS ((int));
 static void pa_align PARAMS ((int));
 static void pa_space PARAMS ((int));
@@ -555,13 +558,13 @@ static sd_chain_struct *create_new_space PARAMS ((char *, int, int,
 						  asection *, int));
 static ssd_chain_struct *create_new_subspace PARAMS ((sd_chain_struct *,
 						      char *, int, int,
-						      int, int, int,
+						      int, int, int, int,
 						      int, int, int, int,
 						      int, asection *));
 static ssd_chain_struct *update_subspace PARAMS ((sd_chain_struct *,
 						  char *, int, int, int,
 						  int, int, int, int,
-						  int, int, int,
+						  int, int, int, int,
 						  asection *));
 static sd_chain_struct *is_defined_space PARAMS ((char *));
 static ssd_chain_struct *is_defined_subspace PARAMS ((char *));
@@ -571,7 +574,6 @@ static ssd_chain_struct *pa_subsegment_to_subspace PARAMS ((asection *,
 static sd_chain_struct *pa_find_space_by_number PARAMS ((int));
 static unsigned int pa_subspace_start PARAMS ((sd_chain_struct *, int));
 static sd_chain_struct *pa_parse_space_stmt PARAMS ((char *, int));
-static int pa_next_subseg PARAMS ((sd_chain_struct *));
 static void pa_spaces_begin PARAMS ((void));
 #endif
 static void pa_ip PARAMS ((char *));
@@ -769,11 +771,15 @@ static label_symbol_struct *label_symbols_rootp = NULL;
 /* Holds the last field selector.  */
 static int hppa_field_selector;
 
-/* Nonzero when strict syntax checking is enabled.  Zero otherwise.
+/* Nonzero when strict matching is enabled.  Zero otherwise.
 
-   Each opcode in the table has a flag which indicates whether or not
-   strict syntax checking should be enabled for that instruction.  */
-static int strict = 0;
+   Each opcode in the table has a flag which indicates whether or
+   not strict matching should be enabled for that instruction.
+
+   Mainly, strict causes errors to be ignored when a match failure
+   occurs.  However, it also affects the parsing of register fields
+   by pa_parse_number.  */
+static int strict;
 
 /* pa_parse_number returns values in `pa_number'.  Mostly
    pa_parse_number is used to return a register number, with floating
@@ -809,6 +815,7 @@ static int print_errors = 1;
 
    %r26 - %r23 have %arg0 - %arg3 as synonyms
    %r28 - %r29 have %ret0 - %ret1 as synonyms
+   %fr4 - %fr7 have %farg0 - %farg3 as synonyms
    %r30 has %sp as a synonym
    %r27 has %dp as a synonym
    %r2  has %rp as a synonym
@@ -852,10 +859,10 @@ static const struct pd_reg pre_defined_registers[] =
   {"%dp",    27},
   {"%eiem",  15},
   {"%eirr",  23},
-  {"%farg0",  5},
-  {"%farg1",  6},
-  {"%farg2",  7},
-  {"%farg3",  8},
+  {"%farg0",  4 + FP_REG_BASE},
+  {"%farg1",  5 + FP_REG_BASE},
+  {"%farg2",  6 + FP_REG_BASE},
+  {"%farg3",  7 + FP_REG_BASE},
   {"%fr0",    0 + FP_REG_BASE},
   {"%fr0l",   0 + FP_REG_BASE},
   {"%fr0r",   0 + FP_REG_BASE + FP_REG_RSEL},
@@ -1117,12 +1124,12 @@ static const struct selector_entry selector_table[] =
 
 static struct default_subspace_dict pa_def_subspaces[] =
 {
-  {"$CODE$", 1, 1, 1, 0, 0, 0, 24, 0x2c, 0, 8, 0, 0, SUBSEG_CODE},
-  {"$DATA$", 1, 1, 0, 0, 0, 0, 24, 0x1f, 1, 8, 1, 1, SUBSEG_DATA},
-  {"$LIT$", 1, 1, 0, 0, 0, 0, 16, 0x2c, 0, 8, 0, 0, SUBSEG_LIT},
-  {"$MILLICODE$", 1, 1, 0, 0, 0, 0, 8, 0x2c, 0, 8, 0, 0, SUBSEG_MILLI},
-  {"$BSS$", 1, 1, 0, 0, 0, 1, 80, 0x1f, 1, 8, 1, 1, SUBSEG_BSS},
-  {NULL, 0, 1, 0, 0, 0, 0, 255, 0x1f, 0, 4, 0, 0, 0}
+  {"$CODE$", 1, 1, 1, 0, 0, 0, 0, 24, 0x2c, 0, 8, 0, 0, SUBSEG_CODE},
+  {"$DATA$", 1, 1, 0, 0, 0, 0, 0, 24, 0x1f, 1, 8, 1, 1, SUBSEG_DATA},
+  {"$LIT$", 1, 1, 0, 0, 0, 0, 0, 16, 0x2c, 0, 8, 0, 0, SUBSEG_LIT},
+  {"$MILLICODE$", 1, 1, 0, 0, 0, 0, 0, 8, 0x2c, 0, 8, 0, 0, SUBSEG_MILLI},
+  {"$BSS$", 1, 1, 0, 0, 0, 0, 1, 80, 0x1f, 1, 8, 1, 1, SUBSEG_BSS},
+  {NULL, 0, 1, 0, 0, 0, 0, 0, 255, 0x1f, 0, 4, 0, 0, 0}
 };
 
 static struct default_space_dict pa_def_spaces[] =
@@ -1172,7 +1179,7 @@ static struct default_space_dict pa_def_spaces[] =
       } \
   }
 
-/* Variant of CHECK_FIELD for use in md_apply_fix3 and other places where
+/* Variant of CHECK_FIELD for use in md_apply_fix and other places where
    the current file and line number are not valid.  */
 
 #define CHECK_FIELD_WHERE(FIELD, HIGH, LOW, FILENAME, LINE) \
@@ -1284,6 +1291,10 @@ pa_define_label (symbol)
 
       label_symbols_rootp = label_chain;
     }
+
+#ifdef OBJ_ELF
+  dwarf2_emit_label (symbol);
+#endif
 }
 
 /* Removes a label definition for the current space.
@@ -1611,7 +1622,8 @@ pa_ip (str)
       break;
 
     default:
-      as_fatal (_("Unknown opcode: `%s'"), str);
+      as_bad (_("Unknown opcode: `%s'"), str);
+      return;
     }
 
   /* Look up the opcode in the has table.  */
@@ -1638,21 +1650,9 @@ pa_ip (str)
 
       the_insn.reloc = R_HPPA_NONE;
 
-      /* If this instruction is specific to a particular architecture,
-	 then set a new architecture.  */
-      /* But do not automatically promote to pa2.0.  The automatic promotion
-	 crud is for compatibility with HP's old assemblers only.  */
-      if (insn->arch < 20
+      if (insn->arch >= pa20
 	  && bfd_get_mach (stdoutput) < insn->arch)
-	{
-	  if (!bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch))
-	    as_warn (_("could not update architecture and machine"));
-	}
-      else if (bfd_get_mach (stdoutput) < insn->arch)
-	{
-	  match = FALSE;
-	  goto failed;
-	}
+	goto failed;
 
       /* Build the opcode, checking as we go to make
          sure that the operands match.  */
@@ -1847,9 +1847,9 @@ pa_ip (str)
 			else if ((strncasecmp (s, "s ", 2) == 0)
 				 || (strncasecmp (s, "s,", 2) == 0))
 			  uu = 1;
-			/* When in strict mode this is a match failure.  */
 			else if (strict)
 			  {
+			    /* This is a match failure.  */
 			    s--;
 			    break;
 			  }
@@ -1875,28 +1875,25 @@ pa_ip (str)
 		    int m = 0;
 		    if (*s == ',')
 		      {
-			int found = 0;
 			s++;
 			if (strncasecmp (s, "ma", 2) == 0)
 			  {
 			    a = 0;
 			    m = 1;
-			    found = 1;
+			    s += 2;
 			  }
 			else if (strncasecmp (s, "mb", 2) == 0)
 			  {
 			    a = 1;
 			    m = 1;
-			    found = 1;
+			    s += 2;
 			  }
-
-			/* When in strict mode, pass through for cache op.  */
-			if (!found && strict)
+			else if (strict)
+			  /* This is a match failure.  */
 			  s--;
 			else
 			  {
-			    if (!found)
-			      as_bad (_("Invalid Short Load/Store Completer."));
+			    as_bad (_("Invalid Short Load/Store Completer."));
 			    s += 2;
 			  }
 		      }
@@ -1949,7 +1946,7 @@ pa_ip (str)
 			  a = 0;
 			else if (strncasecmp (s, "e", 1) == 0)
 			  a = 1;
-			/* When in strict mode this is a match failure.  */
+			/* In strict mode, this is a match failure.  */
 			else if (strict)
 			  {
 			    s--;
@@ -3073,6 +3070,8 @@ pa_ip (str)
 
 	    /* Handle 14 bit immediate, shifted left three times.  */
 	    case '#':
+	      if (bfd_get_mach (stdoutput) != pa20)
+		break;
 	      the_insn.field_selector = pa_chk_field_selector (&s);
 	      get_expression (s);
 	      s = expr_end;
@@ -3959,6 +3958,17 @@ pa_ip (str)
 	  break;
 	}
 
+      /* If this instruction is specific to a particular architecture,
+	 then set a new architecture.  This automatic promotion crud is
+	 for compatibility with HP's old assemblers only.  */
+      if (match == TRUE
+	  && bfd_get_mach (stdoutput) < insn->arch
+	  && !bfd_set_arch_mach (stdoutput, bfd_arch_hppa, insn->arch))
+	{
+	  as_warn (_("could not update architecture and machine"));
+	  match = FALSE;
+	}
+
  failed:
       /* Check if the args matched.  */
       if (!match)
@@ -4421,12 +4431,12 @@ md_undefined_symbol (name)
 /* Apply a fixup to an instruction.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS *fixP;
      valueT *valP;
      segT seg ATTRIBUTE_UNUSED;
 {
-  unsigned char *buf;
+  char *fixpos;
   struct hppa_fix_struct *hppa_fixP;
   offsetT new_val;
   int insn, val, fmt;
@@ -4460,8 +4470,7 @@ md_apply_fix3 (fixP, valP, seg)
   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
     fixP->fx_done = 1;
 
-  /* There should have been an HPPA specific fixup associated
-     with the GAS fixup.  */
+  /* There should be a HPPA specific fixup associated with the GAS fixup.  */
   hppa_fixP = (struct hppa_fix_struct *) fixP->tc_fix_data;
   if (hppa_fixP == NULL)
     {
@@ -4471,8 +4480,16 @@ md_apply_fix3 (fixP, valP, seg)
       return;
     }
 
-  buf = (unsigned char *) (fixP->fx_frag->fr_literal + fixP->fx_where);
-  insn = bfd_get_32 (stdoutput, buf);
+  fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  if (fixP->fx_size != 4 || hppa_fixP->fx_r_format == 32)
+    {
+      /* Handle constant output. */
+      number_to_chars_bigendian (fixpos, *valP, fixP->fx_size);
+      return;
+    }
+
+  insn = bfd_get_32 (stdoutput, fixpos);
   fmt = bfd_hppa_insn2fmt (stdoutput, insn);
 
   /* If there is a symbol associated with this fixup, then it's something
@@ -4642,7 +4659,7 @@ md_apply_fix3 (fixP, valP, seg)
     }
 
   /* Insert the relocation.  */
-  bfd_put_32 (stdoutput, insn, buf);
+  bfd_put_32 (stdoutput, insn, fixpos);
 }
 
 /* Exactly what point is a PC-relative offset relative TO?
@@ -5925,8 +5942,8 @@ pa_align (bytes)
 
   /* If bytes is a power of 2, then update the current subspace's
      alignment if necessary.  */
-  if (log2 (bytes) != -1)
-    record_alignment (current_subspace->ssd_seg, log2 (bytes));
+  if (exact_log2 (bytes) != -1)
+    record_alignment (current_subspace->ssd_seg, exact_log2 (bytes));
 }
 #endif
 
@@ -5936,10 +5953,7 @@ static void
 pa_block (z)
      int z ATTRIBUTE_UNUSED;
 {
-  char *p;
-  long int temp_fill;
   unsigned int temp_size;
-  unsigned int i;
 
 #ifdef OBJ_SOM
   /* We must have a valid space and subspace.  */
@@ -5948,20 +5962,16 @@ pa_block (z)
 
   temp_size = get_absolute_expression ();
 
-  /* Always fill with zeros, that's what the HP assembler does.  */
-  temp_fill = 0;
-
-  p = frag_var (rs_fill, (int) temp_size, (int) temp_size,
-		(relax_substateT) 0, (symbolS *) 0, (offsetT) 1, NULL);
-  memset (p, 0, temp_size);
-
-  /* Convert 2 bytes at a time.  */
-
-  for (i = 0; i < temp_size; i += 2)
+  if (temp_size > 0x3FFFFFFF)
     {
-      md_number_to_chars (p + i,
-			  (valueT) temp_fill,
-			  (int) ((temp_size - i) > 2 ? 2 : (temp_size - i)));
+      as_bad (_("Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff"));
+      temp_size = 0;
+    }
+  else
+    {
+      /* Always fill with zeros, that's what the HP assembler does.  */
+      char *p = frag_var (rs_fill, 1, 1, 0, NULL, temp_size, NULL);
+      *p = 0;
     }
 
   pa_undefine_label ();
@@ -6390,7 +6400,7 @@ pa_comm (unused)
     {
       symbol_get_bfdsym (symbol)->flags |= BSF_OBJECT;
       S_SET_VALUE (symbol, size);
-      S_SET_SEGMENT (symbol, bfd_und_section_ptr);
+      S_SET_SEGMENT (symbol, bfd_com_section_ptr);
       S_SET_EXTERNAL (symbol);
 
       /* colon() has already set the frag to the current location in the
@@ -7147,7 +7157,7 @@ pa_procend (unused)
    return log2 (VALUE).  Else return -1.  */
 
 static int
-log2 (value)
+exact_log2 (value)
      int value;
 {
   int shift = 0;
@@ -7454,7 +7464,7 @@ pa_subspace (create_new)
      int create_new;
 {
   char *name, *ss_name, c;
-  char loadable, code_only, common, dup_common, zero, sort;
+  char loadable, code_only, comdat, common, dup_common, zero, sort;
   int i, access, space_index, alignment, quadrant, applicable, flags;
   sd_chain_struct *space;
   ssd_chain_struct *ssd;
@@ -7480,6 +7490,7 @@ pa_subspace (create_new)
       sort = 0;
       access = 0x7f;
       loadable = 1;
+      comdat = 0;
       common = 0;
       dup_common = 0;
       code_only = 0;
@@ -7514,6 +7525,7 @@ pa_subspace (create_new)
 	      if (strcasecmp (pa_def_subspaces[i].name, ss_name) == 0)
 		{
 		  loadable = pa_def_subspaces[i].loadable;
+		  comdat = pa_def_subspaces[i].comdat;
 		  common = pa_def_subspaces[i].common;
 		  dup_common = pa_def_subspaces[i].dup_common;
 		  code_only = pa_def_subspaces[i].code_only;
@@ -7549,7 +7561,7 @@ pa_subspace (create_new)
 		  *input_line_pointer = c;
 		  input_line_pointer++;
 		  alignment = get_absolute_expression ();
-		  if (log2 (alignment) == -1)
+		  if (exact_log2 (alignment) == -1)
 		    {
 		      as_bad (_("Alignment must be a power of 2"));
 		      alignment = 1;
@@ -7577,6 +7589,11 @@ pa_subspace (create_new)
 		  *input_line_pointer = c;
 		  loadable = 0;
 		}
+	      else if ((strncasecmp (name, "comdat", 6) == 0))
+		{
+		  *input_line_pointer = c;
+		  comdat = 1;
+		}
 	      else if ((strncasecmp (name, "common", 6) == 0))
 		{
 		  *input_line_pointer = c;
@@ -7609,8 +7626,17 @@ pa_subspace (create_new)
 	flags |= (SEC_ALLOC | SEC_LOAD);
       if (code_only)
 	flags |= SEC_CODE;
-      if (common || dup_common)
-	flags |= SEC_IS_COMMON;
+
+      /* These flags are used to implement various flavors of initialized
+	 common.  The SOM linker discards duplicate subspaces when they
+	 have the same "key" symbol name.  This support is more like
+	 GNU linkonce than BFD common.  Further, pc-relative relocations
+	 are converted to section relative relocations in BFD common
+	 sections.  This complicates the handling of relocations in
+	 common sections containing text and isn't currently supported
+	 correctly in the SOM BFD backend.  */
+      if (comdat || common || dup_common)
+	flags |= SEC_LINK_ONCE;
 
       flags |= SEC_RELOC | SEC_HAS_CONTENTS;
 
@@ -7641,7 +7667,7 @@ pa_subspace (create_new)
       bfd_set_section_flags (stdoutput, section, applicable);
 
       /* Record any alignment request for this section.  */
-      record_alignment (section, log2 (alignment));
+      record_alignment (section, exact_log2 (alignment));
 
       /* Set the starting offset for this section.  */
       bfd_set_section_vma (stdoutput, section,
@@ -7652,16 +7678,16 @@ pa_subspace (create_new)
       if (ssd)
 
 	current_subspace = update_subspace (space, ss_name, loadable,
-					    code_only, common, dup_common,
-					    sort, zero, access, space_index,
-					    alignment, quadrant,
+					    code_only, comdat, common,
+					    dup_common, sort, zero, access,
+					    space_index, alignment, quadrant,
 					    section);
       else
 	current_subspace = create_new_subspace (space, ss_name, loadable,
-						code_only, common,
+						code_only, comdat, common,
 						dup_common, zero, sort,
 						access, space_index,
-					      alignment, quadrant, section);
+						alignment, quadrant, section);
 
       demand_empty_rest_of_line ();
       current_subspace->ssd_seg = section;
@@ -7782,6 +7808,7 @@ pa_spaces_begin ()
       create_new_subspace (space, name,
 			   pa_def_subspaces[i].loadable,
 			   pa_def_subspaces[i].code_only,
+			   pa_def_subspaces[i].comdat,
 			   pa_def_subspaces[i].common,
 			   pa_def_subspaces[i].dup_common,
 			   pa_def_subspaces[i].zero,
@@ -7803,7 +7830,7 @@ create_new_space (name, spnum, loadable, defined, private,
 		  sort, seg, user_defined)
      char *name;
      int spnum;
-     int loadable;
+     int loadable ATTRIBUTE_UNUSED;
      int defined;
      int private;
      int sort;
@@ -7883,16 +7910,19 @@ create_new_space (name, spnum, loadable, defined, private,
    order as defined by the SORT entries.  */
 
 static ssd_chain_struct *
-create_new_subspace (space, name, loadable, code_only, common,
+create_new_subspace (space, name, loadable, code_only, comdat, common,
 		     dup_common, is_zero, sort, access, space_index,
 		     alignment, quadrant, seg)
      sd_chain_struct *space;
      char *name;
-     int loadable, code_only, common, dup_common, is_zero;
+     int loadable ATTRIBUTE_UNUSED;
+     int code_only ATTRIBUTE_UNUSED;
+     int comdat, common, dup_common;
+     int is_zero ATTRIBUTE_UNUSED;
      int sort;
      int access;
-     int space_index;
-     int alignment;
+     int space_index ATTRIBUTE_UNUSED;
+     int alignment ATTRIBUTE_UNUSED;
      int quadrant;
      asection *seg;
 {
@@ -7945,8 +7975,8 @@ create_new_subspace (space, name, loadable, code_only, common,
     }
 
 #ifdef obj_set_subsection_attributes
-  obj_set_subsection_attributes (seg, space->sd_seg, access,
-				 sort, quadrant);
+  obj_set_subsection_attributes (seg, space->sd_seg, access, sort,
+				 quadrant, comdat, common, dup_common);
 #endif
 
   return chain_entry;
@@ -7956,19 +7986,20 @@ create_new_subspace (space, name, loadable, code_only, common,
    various arguments.   Return the modified subspace chain entry.  */
 
 static ssd_chain_struct *
-update_subspace (space, name, loadable, code_only, common, dup_common, sort,
-		 zero, access, space_index, alignment, quadrant, section)
+update_subspace (space, name, loadable, code_only, comdat, common, dup_common,
+		 sort, zero, access, space_index, alignment, quadrant, section)
      sd_chain_struct *space;
      char *name;
-     int loadable;
-     int code_only;
+     int loadable ATTRIBUTE_UNUSED;
+     int code_only ATTRIBUTE_UNUSED;
+     int comdat;
      int common;
      int dup_common;
-     int zero;
+     int zero ATTRIBUTE_UNUSED;
      int sort;
      int access;
-     int space_index;
-     int alignment;
+     int space_index ATTRIBUTE_UNUSED;
+     int alignment ATTRIBUTE_UNUSED;
      int quadrant;
      asection *section;
 {
@@ -7977,8 +8008,8 @@ update_subspace (space, name, loadable, code_only, common, dup_common, sort,
   chain_entry = is_defined_subspace (name);
 
 #ifdef obj_set_subsection_attributes
-  obj_set_subsection_attributes (section, space->sd_seg, access,
-				 sort, quadrant);
+  obj_set_subsection_attributes (section, space->sd_seg, access, sort,
+				 quadrant, comdat, common, dup_common);
 #endif
 
   return chain_entry;
@@ -8030,9 +8061,14 @@ pa_segment_to_space (seg)
   return NULL;
 }
 
-/* Return the space chain entry for the subspace with the name NAME or
-   NULL if no such subspace exists.
+/* Return the first space chain entry for the subspace with the name
+   NAME or NULL if no such subspace exists.
 
+   When there are multiple subspaces with the same name, switching to
+   the first (i.e., default) subspace is preferable in most situations.
+   For example, it wouldn't be desirable to merge COMDAT data with non
+   COMDAT data.
+    
    Uses a linear search through all the spaces and subspaces, this may
    not be appropriate if we ever being placing each function in its
    own subspace.  */
@@ -8138,16 +8174,6 @@ pa_subspace_start (space, quadrant)
     return 0;
   return 0;
 }
-
-/* FIXME.  Needs documentation.  */
-static int
-pa_next_subseg (space)
-     sd_chain_struct *space;
-{
-
-  space->sd_last_subseg++;
-  return space->sd_last_subseg;
-}
 #endif
 
 /* Helper function for pa_stringer.  Used to find the end of
@@ -8370,28 +8396,20 @@ pa_lsym (unused)
    any fixup which creates entries in the DLT (eg they use "T" field
    selectors).
 
-   Reject reductions involving symbols with external scope; such
-   reductions make life a living hell for object file editors.
-
-   FIXME.  Also reject R_HPPA relocations which are 32bits wide in
-   the code space.  The SOM BFD backend doesn't know how to pull the
-   right bits out of an instruction.  */
+   ??? Reject reductions involving symbols with external scope; such
+   reductions make life a living hell for object file editors.  */
 
 int
 hppa_fix_adjustable (fixp)
      fixS *fixp;
 {
+#ifdef OBJ_ELF
   reloc_type code;
+#endif
   struct hppa_fix_struct *hppa_fix;
 
   hppa_fix = (struct hppa_fix_struct *) fixp->tc_fix_data;
 
-#ifdef OBJ_SOM
-  /* Reject reductions of symbols in 32bit relocs.  */
-  if (fixp->fx_r_type == R_HPPA && hppa_fix->fx_r_format == 32)
-    return 0;
-#endif
-
 #ifdef OBJ_ELF
   /* LR/RR selectors are implicitly used for a number of different relocation
      types.  We must ensure that none of these types are adjusted (see below)
diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h
index 4b43a7faf675..9b3edc1878f5 100644
--- a/gas/config/tc-hppa.h
+++ b/gas/config/tc-hppa.h
@@ -1,6 +1,6 @@
 /* tc-hppa.h -- Header file for the PA
    Copyright 1989, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003 Free Software Foundation, Inc.
+   2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* HP PA-RISC support was contributed by the Center for Software Science
    at the University of Utah.  */
@@ -106,10 +106,6 @@ extern void pa_check_eof PARAMS ((void));
 extern const char	hppa_symbol_chars[];
 #define tc_symbol_chars	hppa_symbol_chars
 
-/* The PA does not need support for either of these.  */
-#define tc_crawl_symbol_chain(headers) {;}
-#define tc_headers_hook(headers) {;}
-
 #define RELOC_EXPANSION_POSSIBLE
 #define MAX_RELOC_EXPANSION 6
 
@@ -119,15 +115,9 @@ extern const char	hppa_symbol_chars[];
   parse_cons_expression_hppa (EXP)
 #define TC_CONS_FIX_NEW cons_fix_new_hppa
 
-/* On the PA, an equal sign often appears as a condition or nullification
-   completer in an instruction.  This can be detected by checking the
-   previous character, if the character is a comma, then the equal is
-   being used as part of an instruction.  */
-#define TC_EQUAL_IN_INSN(C, PTR)	((C) == ',')
-
-/* Similarly for an exclamation point.  It is used in FP comparison
-   instructions and as an end of line marker.  When used in an instruction
-   it will always follow a comma.  */
+/* On the PA, an exclamation point can appear in an instruction.  It is
+   used in FP comparison instructions and as an end of line marker.
+   When used in an instruction it will always follow a comma.  */
 #define TC_EOL_IN_INSN(PTR)	(*(PTR) == '!' && (PTR)[-1] == ',')
 
 int hppa_fix_adjustable PARAMS((struct fix *));
@@ -140,7 +130,7 @@ int hppa_fix_adjustable PARAMS((struct fix *));
    normally appear safe to handle it completely within GAS.  */
 #define TC_FORCE_RELOCATION(FIX) hppa_force_relocation (FIX)
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #ifdef OBJ_SOM
diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c
index a1dab875ae85..d87d2d9f808c 100644
--- a/gas/config/tc-i370.c
+++ b/gas/config/tc-i370.c
@@ -1,7 +1,7 @@
 /* tc-i370.c -- Assembler for the IBM 360/370/390 instruction set.
    Loosely based on the ppc files by Linas Vepstas <linas@linas.org> 1998, 99
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005, 2006 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -18,15 +18,14 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This assembler implements a very hacked version of an elf-like thing
- * that gcc emits (when gcc is suitably hacked).  To make it behave more
- * HLASM-like, try turning on the -M or --mri flag (as there are various
- * similarities between HLASM and the MRI assemblers, such as section
- * names, lack of leading . in pseudo-ops, DC and DS, etc ...
- */
+   that gcc emits (when gcc is suitably hacked).  To make it behave more
+   HLASM-like, try turning on the -M or --mri flag (as there are various
+   similarities between HLASM and the MRI assemblers, such as section
+   names, lack of leading . in pseudo-ops, DC and DS, etc.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -40,7 +39,7 @@
 #include "elf/i370.h"
 #endif
 
-/* This is the assembler for the System/390 Architecture  */
+/* This is the assembler for the System/390 Architecture.  */
 
 /* Tell the main code what the endianness is.  */
 extern int target_big_endian;
@@ -77,8 +76,7 @@ const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "dD";
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, "\
 S/370 options: (these have not yet been tested and may not work) \n\
@@ -93,84 +91,15 @@ S/370 options: (these have not yet been tested and may not work) \n\
 #endif
 }
 
-
-static void i370_byte PARAMS ((int));
-static void i370_tc PARAMS ((int));
-static void i370_ebcdic PARAMS ((int));
-
-static void i370_dc PARAMS ((int));
-static void i370_ds PARAMS ((int));
-static void i370_rmode PARAMS ((int));
-static void i370_csect PARAMS ((int));
-static void i370_dsect PARAMS ((int));
-static void i370_ltorg PARAMS ((int));
-static void i370_using PARAMS ((int));
-static void i370_drop PARAMS ((int));
-static void i370_make_relative PARAMS ((expressionS *exp, expressionS *baseaddr));
-
-#ifdef OBJ_ELF
-static bfd_reloc_code_real_type i370_elf_suffix PARAMS ((char **, expressionS *));
-static void i370_elf_cons PARAMS ((int));
-static void i370_elf_rdata PARAMS ((int));
-static void i370_elf_lcomm PARAMS ((int));
-static void i370_elf_validate_fix PARAMS ((fixS *, segT));
-#endif
-
-
-/* The target specific pseudo-ops which we support.  */
-
-const pseudo_typeS md_pseudo_table[] =
-{
-  /* Pseudo-ops which must be overridden.  */
-  { "byte",     i370_byte,	0 },
-
-  { "dc",       i370_dc,	0 },
-  { "ds",       i370_ds,	0 },
-  { "rmode",    i370_rmode,	0 },
-  { "csect",    i370_csect,	0 },
-  { "dsect",    i370_dsect,	0 },
-
-  /* enable ebcdic strings e.g. for 3270 support */
-  { "ebcdic",   i370_ebcdic,	0 },
-
-#ifdef OBJ_ELF
-  { "long",     i370_elf_cons,	4 },
-  { "word",     i370_elf_cons,	4 },
-  { "short",    i370_elf_cons,	2 },
-  { "rdata",    i370_elf_rdata,	0 },
-  { "rodata",   i370_elf_rdata,	0 },
-  { "lcomm",    i370_elf_lcomm,	0 },
-#endif
-
-  /* This pseudo-op is used even when not generating XCOFF output.  */
-  { "tc",       i370_tc,	0 },
-
-  /* dump the literal pool */
-  { "ltorg",    i370_ltorg,	0 },
-
-  /* support the hlasm-style USING directive */
-  { "using",    i370_using,	0 },
-  { "drop",     i370_drop,	0 },
-
-  { NULL,       NULL,		0 }
-};
-
-/* ***************************************************************** */
-
 /* Whether to use user friendly register names.  */
 #define TARGET_REG_NAMES_P TRUE
 
 static bfd_boolean reg_names_p = TARGET_REG_NAMES_P;
 
-static bfd_boolean register_name PARAMS ((expressionS *));
-static void i370_set_cpu PARAMS ((void));
-static i370_insn_t i370_insert_operand
-  PARAMS ((i370_insn_t insn, const struct i370_operand *operand, offsetT val));
-static void i370_macro PARAMS ((char *str, const struct i370_macro *macro));
 
-/* Predefined register names if -mregnames */
-/* In general, there are lots of them, in an attempt to be compatible */
-/* with a number of assemblers.                      */
+/* Predefined register names if -mregnames
+   In general, there are lots of them, in an attempt to be compatible
+   with a number of assemblers.  */
 
 /* Structure to hold information about predefined registers.  */
 struct pd_reg
@@ -206,10 +135,10 @@ struct pd_reg
 
 static const struct pd_reg pre_defined_registers[] =
 {
-  { "arg", 11 },  /* Argument Pointer */
-  { "base", 3 },  /* Base Reg */
+  { "arg", 11 },   /* Argument Pointer.  */
+  { "base", 3 },   /* Base Reg.  */
 
-  { "f.0", 0 },     /* Floating point registers */
+  { "f.0", 0 },    /* Floating point registers.  */
   { "f.2", 2 },
   { "f.4", 4 },
   { "f.6", 6 },
@@ -219,11 +148,11 @@ static const struct pd_reg pre_defined_registers[] =
   { "f4", 4 },
   { "f6", 6 },
 
-  { "dsa",13 },    /* stack pointer */
-  { "lr", 14 },    /* Link Register */
-  { "pgt", 4 },    /* Page Origin Table Pointer */
+  { "dsa",13 },    /* Stack pointer.  */
+  { "lr", 14 },    /* Link Register.  */
+  { "pgt", 4 },    /* Page Origin Table Pointer.  */
 
-  { "r.0", 0 },    /* General Purpose Registers */
+  { "r.0", 0 },    /* General Purpose Registers.  */
   { "r.1", 1 },
   { "r.10", 10 },
   { "r.11", 11 },
@@ -240,16 +169,16 @@ static const struct pd_reg pre_defined_registers[] =
   { "r.8", 8 },
   { "r.9", 9 },
 
-  { "r.arg", 11 },  /* Argument Pointer */
-  { "r.base", 3 },  /* Base Reg */
-  { "r.dsa", 13 },  /* Stack Pointer */
-  { "r.pgt", 4 },   /* Page Origin Table Pointer */
-  { "r.sp", 13 },   /* Stack Pointer */
+  { "r.arg", 11 },  /* Argument Pointer.  */
+  { "r.base", 3 },  /* Base Reg.  */
+  { "r.dsa", 13 },  /* Stack Pointer.  */
+  { "r.pgt", 4 },   /* Page Origin Table Pointer.  */
+  { "r.sp", 13 },   /* Stack Pointer.  */
 
-  { "r.tca", 12 },  /* Pointer to the table of contents */
-  { "r.toc", 12 },  /* Pointer to the table of contents */
+  { "r.tca", 12 },  /* Pointer to the table of contents.  */
+  { "r.toc", 12 },  /* Pointer to the table of contents.  */
 
-  { "r0", 0 },     /* More general purpose registers */
+  { "r0", 0 },      /* More general purpose registers.  */
   { "r1", 1 },
   { "r10", 10 },
   { "r11", 11 },
@@ -266,12 +195,12 @@ static const struct pd_reg pre_defined_registers[] =
   { "r8", 8 },
   { "r9", 9 },
 
-  { "rbase", 3 },  /* Base Reg */
+  { "rbase", 3 },  /* Base Reg.  */
 
-  { "rtca", 12 },  /* Pointer to the table of contents */
-  { "rtoc", 12 },  /* Pointer to the table of contents */
+  { "rtca", 12 },  /* Pointer to the table of contents.  */
+  { "rtoc", 12 },  /* Pointer to the table of contents.  */
 
-  { "sp", 13 },   /* Stack Pointer */
+  { "sp", 13 },   /* Stack Pointer.  */
 
 };
 
@@ -280,14 +209,10 @@ static const struct pd_reg pre_defined_registers[] =
 /* Given NAME, find the register number associated with that name, return
    the integer value associated with the given name or -1 on failure.  */
 
-static int reg_name_search
-  PARAMS ((const struct pd_reg *, int, const char * name));
-
 static int
-reg_name_search (regs, regcount, name)
-     const struct pd_reg *regs;
-     int regcount;
-     const char *name;
+reg_name_search (const struct pd_reg *regs,
+		 int regcount,
+		 const char *name)
 {
   int middle, low, high;
   int cmp;
@@ -311,21 +236,18 @@ reg_name_search (regs, regcount, name)
   return -1;
 }
 
-/*
- * Summary of register_name().
- *
- * in:        Input_line_pointer points to 1st char of operand.
- *
- * out:        An expressionS.
- *      The operand may have been a register: in this case, X_op == O_register,
- *      X_add_number is set to the register number, and truth is returned.
- *        Input_line_pointer->(next non-blank) char after operand, or is in its
- *      original state.
- */
+/* Summary of register_name().
+
+   in:        Input_line_pointer points to 1st char of operand.
+
+   out:        An expressionS.
+        The operand may have been a register: in this case, X_op == O_register,
+        X_add_number is set to the register number, and truth is returned.
+          Input_line_pointer->(next non-blank) char after operand, or is in its
+        original state.  */
 
 static bfd_boolean
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -346,9 +268,7 @@ register_name (expressionP)
   /* If it's a number, treat it as a number.  If it's alpha, look to
      see if it's in the register table.  */
   if (!ISALPHA (name[0]))
-    {
-      reg_number = get_single_number ();
-    }
+    reg_number = get_single_number ();
   else
     {
       c = get_symbol_end ();
@@ -382,32 +302,31 @@ register_name (expressionP)
 static int i370_cpu = 0;
 
 /* The base register to use for opcode with optional operands.
- * We define two of these: "text" and "other".  Normally, "text"
- * would get used in the .text section for branches, while "other"
- * gets used in the .data section for address constants.
- *
- * The idea of a second base register in a different section
- * is foreign to the usual HLASM-style semantics; however, it
- * allows us to provide support for dynamically loaded libraries,
- * by allowing us to place address constants in a section other
- * than the text section. The "other" section need not be the
- * .data section, it can be any section that isn't the .text section.
- *
- * Note that HLASM defines a multiple, concurrent .using semantic
- * that we do not: in calculating offsets, it uses either the most
- * recent .using directive, or the one with the smallest displacement.
- * This allows HLASM to support a quasi-block-scope-like behaviour.
- * Handy for people writing assembly by hand ... but not supported
- * by us.
- */
+   We define two of these: "text" and "other".  Normally, "text"
+   would get used in the .text section for branches, while "other"
+   gets used in the .data section for address constants.
+
+   The idea of a second base register in a different section
+   is foreign to the usual HLASM-style semantics; however, it
+   allows us to provide support for dynamically loaded libraries,
+   by allowing us to place address constants in a section other
+   than the text section. The "other" section need not be the
+   .data section, it can be any section that isn't the .text section.
+
+   Note that HLASM defines a multiple, concurrent .using semantic
+   that we do not: in calculating offsets, it uses either the most
+   recent .using directive, or the one with the smallest displacement.
+   This allows HLASM to support a quasi-block-scope-like behaviour.
+   Handy for people writing assembly by hand ... but not supported
+   by us.  */
 static int i370_using_text_regno = -1;
 static int i370_using_other_regno = -1;
 
-/* The base address for address literals */
+/* The base address for address literals.  */
 static expressionS i370_using_text_baseaddr;
 static expressionS i370_using_other_baseaddr;
 
-/* the "other" section, used only for syntax error detection */
+/* the "other" section, used only for syntax error detection.  */
 static segT i370_other_section = undefined_section;
 
 /* Opcode hash table.  */
@@ -417,16 +336,16 @@ static struct hash_control *i370_hash;
 static struct hash_control *i370_macro_hash;
 
 #ifdef OBJ_ELF
-/* What type of shared library support to use */
+/* What type of shared library support to use.  */
 static enum { SHLIB_NONE, SHLIB_PIC, SHILB_MRELOCATABLE } shlib = SHLIB_NONE;
 #endif
 
-/* Flags to set in the elf header */
+/* Flags to set in the elf header.  */
 static flagword i370_flags = 0;
 
 #ifndef WORKING_DOT_WORD
-const int md_short_jump_size = 4;
-const int md_long_jump_size = 4;
+int md_short_jump_size = 4;
+int md_long_jump_size = 4;
 #endif
 
 #ifdef OBJ_ELF
@@ -441,9 +360,7 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -468,10 +385,10 @@ md_parse_option (c, arg)
 
     case 'm':
 
-      /* -m360 mean to assemble for the ancient 360 architecture */
+      /* -m360 mean to assemble for the ancient 360 architecture.  */
       if (strcmp (arg, "360") == 0 || strcmp (arg, "i360") == 0)
 	i370_cpu = I370_OPCODE_360;
-      /* -mxa means to assemble for the IBM 370 XA  */
+      /* -mxa means to assemble for the IBM 370 XA.  */
       else if (strcmp (arg, "xa") == 0)
 	i370_cpu = I370_OPCODE_370_XA;
       /* -many means to assemble for any architecture (370/XA).  */
@@ -485,19 +402,18 @@ md_parse_option (c, arg)
 	reg_names_p = FALSE;
 
 #ifdef OBJ_ELF
-      /* -mrelocatable/-mrelocatable-lib -- warn about initializations that require relocation */
+      /* -mrelocatable/-mrelocatable-lib -- warn about
+	 initializations that require relocation.  */
       else if (strcmp (arg, "relocatable") == 0)
         {
           shlib = SHILB_MRELOCATABLE;
           i370_flags |= EF_I370_RELOCATABLE;
         }
-
       else if (strcmp (arg, "relocatable-lib") == 0)
         {
           shlib = SHILB_MRELOCATABLE;
           i370_flags |= EF_I370_RELOCATABLE_LIB;
         }
-
 #endif
       else
         {
@@ -532,12 +448,12 @@ md_parse_option (c, arg)
    but can be made more fine grained if desred.  */
 
 static void
-i370_set_cpu ()
+i370_set_cpu (void)
 {
   const char *default_os  = TARGET_OS;
   const char *default_cpu = TARGET_CPU;
 
-  /* override with the superset for the moment.  */
+  /* Override with the superset for the moment.  */
   i370_cpu = I370_OPCODE_ESA390_SUPERSET;
   if (i370_cpu == 0)
     {
@@ -552,11 +468,11 @@ i370_set_cpu ()
     }
 }
 
-/* Figure out the BFD architecture to use.  */
-/* hack alert -- specify the different 370 architectures  */
+/* Figure out the BFD architecture to use.
+   FIXME: specify the different 370 architectures.  */
 
 enum bfd_architecture
-i370_arch ()
+i370_arch (void)
 {
    return bfd_arch_i370;
 }
@@ -566,9 +482,9 @@ i370_arch ()
    opened.  */
 
 void
-md_begin ()
+md_begin (void)
 {
-  register const struct i370_opcode *op;
+  const struct i370_opcode *op;
   const struct i370_opcode *op_end;
   const struct i370_macro *macro;
   const struct i370_macro *macro_end;
@@ -588,13 +504,14 @@ md_begin ()
    op_end = i370_opcodes + i370_num_opcodes;
    for (op = i370_opcodes; op < op_end; op++)
      {
-       know ((op->opcode & op->mask) == op->opcode);
+       know ((op->opcode.i[0] & op->mask.i[0]) == op->opcode.i[0]
+	     && (op->opcode.i[1] & op->mask.i[1]) == op->opcode.i[1]);
 
        if ((op->flags & i370_cpu) != 0)
          {
            const char *retval;
 
-           retval = hash_insert (i370_hash, op->name, (PTR) op);
+           retval = hash_insert (i370_hash, op->name, (void *) op);
            if (retval != (const char *) NULL)
              {
                as_bad ("Internal assembler error for instruction %s", op->name);
@@ -613,7 +530,7 @@ md_begin ()
         {
           const char *retval;
 
-          retval = hash_insert (i370_macro_hash, macro->name, (PTR) macro);
+          retval = hash_insert (i370_macro_hash, macro->name, (void *) macro);
           if (retval != (const char *) NULL)
             {
               as_bad ("Internal assembler error for macro %s", macro->name);
@@ -629,27 +546,24 @@ md_begin ()
 /* Insert an operand value into an instruction.  */
 
 static i370_insn_t
-i370_insert_operand (insn, operand, val)
-     i370_insn_t insn;
-     const struct i370_operand *operand;
-     offsetT val;
+i370_insert_operand (i370_insn_t insn,
+		     const struct i370_operand *operand,
+		     offsetT val)
 {
   if (operand->insert)
     {
       const char *errmsg;
 
-      /* used for 48-bit insn's */
+      /* Used for 48-bit insn's.  */
       errmsg = NULL;
       insn = (*operand->insert) (insn, (long) val, &errmsg);
       if (errmsg)
         as_bad ("%s", errmsg);
     }
   else
-    {
-      /* this is used only for 16, 32 bit insn's */
-      insn.i[0] |= (((long) val & ((1 << operand->bits) - 1))
-		    << operand->shift);
-    }
+    /* This is used only for 16, 32 bit insn's.  */
+    insn.i[0] |= (((long) val & ((1 << operand->bits) - 1))
+		  << operand->shift);
 
   return insn;
 }
@@ -664,10 +578,9 @@ i370_insert_operand (insn, operand, val)
    BFD_RELOC_UNUSED in all circumstances.  However, I'll leave
    in for now in case someone ambitious finds a good use for this stuff ...
    this routine was pretty much just copied from the powerpc code ...  */
+
 static bfd_reloc_code_real_type
-i370_elf_suffix (str_p, exp_p)
-     char **str_p;
-     expressionS *exp_p;
+i370_elf_suffix (char **str_p, expressionS *exp_p)
 {
   struct map_bfd
   {
@@ -683,15 +596,10 @@ i370_elf_suffix (str_p, exp_p)
   int len;
   struct map_bfd *ptr;
 
-#define MAP(str,reloc) { str, sizeof (str)-1, reloc }
+#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
 
   static struct map_bfd mapping[] =
   {
-#if 0
-    MAP ("l",		BFD_RELOC_LO16),
-    MAP ("h",		BFD_RELOC_HI16),
-    MAP ("ha",		BFD_RELOC_HI16_S),
-#endif
     /* warnings with -mrelocatable.  */
     MAP ("fixup",	BFD_RELOC_CTOR),
     { (char *)0, 0,	BFD_RELOC_UNUSED }
@@ -704,9 +612,7 @@ i370_elf_suffix (str_p, exp_p)
        (str2 < ident + sizeof (ident) - 1
         && (ISALNUM (ch) || ch == '@'));
        ch = *++str)
-    {
-      *str2++ = TOLOWER (ch);
-    }
+    *str2++ = TOLOWER (ch);
 
   *str2 = '\0';
   len = str2 - ident;
@@ -749,11 +655,11 @@ i370_elf_suffix (str_p, exp_p)
   return BFD_RELOC_UNUSED;
 }
 
-/* Like normal .long/.short/.word, except support @got, etc.  */
-/* clobbers input_line_pointer, checks end-of-line.  */
+/* Like normal .long/.short/.word, except support @got, etc.
+   Clobbers input_line_pointer, checks end-of-line.  */
+
 static void
-i370_elf_cons (nbytes)
-     register int nbytes;        /* 1=.byte, 2=.word, 4=.long */
+i370_elf_cons (int nbytes)   /* 1=.byte, 2=.word, 4=.long.  */
 {
   expressionS exp;
   bfd_reloc_code_real_type reloc;
@@ -767,6 +673,7 @@ i370_elf_cons (nbytes)
   do
     {
       expression (&exp);
+
       if (exp.X_op == O_symbol
           && *input_line_pointer == '@'
           && (reloc = i370_elf_suffix (&input_line_pointer, &exp)) != BFD_RELOC_UNUSED)
@@ -776,10 +683,9 @@ i370_elf_cons (nbytes)
 
           if (size > nbytes)
             as_bad ("%s relocations do not fit in %d bytes\n", reloc_howto->name, nbytes);
-
           else
             {
-              register char *p = frag_more ((int) nbytes);
+              char *p = frag_more ((int) nbytes);
               int offset = nbytes - size;
 
               fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, &exp, 0, reloc);
@@ -917,10 +823,10 @@ unsigned char ebcasc[256] =
      0x38, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF
 };
 
-/* ebcdic translation tables needed for 3270 support */
+/* EBCDIC translation tables needed for 3270 support.  */
+
 static void
-i370_ebcdic (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_ebcdic (int unused ATTRIBUTE_UNUSED)
 {
   char *p, *end;
   char delim = 0;
@@ -932,10 +838,11 @@ i370_ebcdic (unused)
   while ('\n' == *end) end --;
 
   delim = *input_line_pointer;
-  if (('\'' == delim) || ('\"' == delim)) {
-    input_line_pointer ++;
-    end = rindex (input_line_pointer, delim);
-  }
+  if (('\'' == delim) || ('\"' == delim))
+    {
+      input_line_pointer ++;
+      end = rindex (input_line_pointer, delim);
+    }
 
   if (end > input_line_pointer)
     {
@@ -952,22 +859,21 @@ i370_ebcdic (unused)
 }
 
 
-/* stub out a couple of routines */
+/* Stub out a couple of routines.  */
+
 static void
-i370_rmode (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_rmode (int unused ATTRIBUTE_UNUSED)
 {
   as_tsktsk ("rmode ignored");
 }
 
 static void
-i370_dsect (sect)
-     int sect;
+i370_dsect (int sect)
 {
   char *save_line = input_line_pointer;
   static char section[] = ".data\n";
 
-  /* Just pretend this is .section .data */
+  /* Just pretend this is .section .data.  */
   input_line_pointer = section;
   obj_elf_section (sect);
 
@@ -975,22 +881,20 @@ i370_dsect (sect)
 }
 
 static void
-i370_csect (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_csect (int unused ATTRIBUTE_UNUSED)
 {
   as_tsktsk ("csect not supported");
 }
 
 
 /* DC Define Const  is only partially supported.
- * For samplecode on what to do, look at i370_elf_cons() above.
- * This code handles pseudoops of the style
- * DC   D'3.141592653'   # in sysv4, .double 3.14159265
- * DC   F'1'             # in sysv4, .long   1
- */
+   For samplecode on what to do, look at i370_elf_cons() above.
+   This code handles pseudoops of the style
+   DC   D'3.141592653'   # in sysv4, .double 3.14159265
+   DC   F'1'             # in sysv4, .long   1.  */
+
 static void
-i370_dc (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_dc (int unused ATTRIBUTE_UNUSED)
 {
   char * p, tmp[50];
   int nbytes=0;
@@ -1003,7 +907,7 @@ i370_dc (unused)
       return;
     }
 
-  /* figure out the size */
+  /* Figure out the size.  */
   type = *input_line_pointer++;
   switch (type)
     {
@@ -1022,10 +926,11 @@ i370_dc (unused)
       return;
     }
 
-  /* get rid of pesky quotes */
+  /* Get rid of pesky quotes.  */
   if ('\'' == *input_line_pointer)
     {
       char * close;
+
       ++input_line_pointer;
       close = strchr (input_line_pointer, '\'');
       if (close)
@@ -1033,9 +938,11 @@ i370_dc (unused)
       else
 	as_bad ("missing end-quote");
     }
+
   if ('\"' == *input_line_pointer)
     {
       char * close;
+
       ++input_line_pointer;
       close = strchr (input_line_pointer, '\"');
       if (close)
@@ -1066,15 +973,15 @@ i370_dc (unused)
 }
 
 
-/* provide minimal support for DS Define Storage */
+/* Provide minimal support for DS Define Storage.  */
+
 static void
-i370_ds (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_ds (int unused ATTRIBUTE_UNUSED)
 {
-  /* DS 0H or DS 0F or DS 0D */
+  /* DS 0H or DS 0F or DS 0D.  */
   if ('0' == *input_line_pointer)
     {
-      int alignment = 0;  /* left shift 1<<align */
+      int alignment = 0;  /* Left shift 1 << align.  */
       input_line_pointer ++;
       switch (*input_line_pointer++)
 	{
@@ -1095,36 +1002,34 @@ i370_ds (unused)
       record_alignment (now_seg, alignment);
     }
   else
-    {
-      as_bad ("this DS form not yet supported");
-    }
+    as_bad ("this DS form not yet supported");
 }
 
 /* Solaris pseudo op to change to the .rodata section.  */
+
 static void
-i370_elf_rdata (sect)
-     int sect;
+i370_elf_rdata (int sect)
 {
   char *save_line = input_line_pointer;
   static char section[] = ".rodata\n";
 
-  /* Just pretend this is .section .rodata */
+  /* Just pretend this is .section .rodata.  */
   input_line_pointer = section;
   obj_elf_section (sect);
 
   input_line_pointer = save_line;
 }
 
-/* Pseudo op to make file scope bss items */
+/* Pseudo op to make file scope bss items.  */
+
 static void
-i370_elf_lcomm (unused)
-     int unused ATTRIBUTE_UNUSED;
+i370_elf_lcomm (int unused ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT size;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
   segT old_sec;
   int old_subsec;
@@ -1134,7 +1039,7 @@ i370_elf_lcomm (unused)
   name = input_line_pointer;
   c = get_symbol_end ();
 
-  /* just after name is now '\0' */
+  /* Just after name is now '\0'.  */
   p = input_line_pointer;
   *p = c;
   SKIP_WHITESPACE ();
@@ -1145,7 +1050,8 @@ i370_elf_lcomm (unused)
       return;
     }
 
-  input_line_pointer++;        	/* skip ',' */
+  /* Skip ','.  */
+  input_line_pointer++;
   if ((size = get_absolute_expression ()) < 0)
     {
       as_warn (".COMMon length (%ld.) <0! Ignored.", (long) size);
@@ -1190,12 +1096,12 @@ i370_elf_lcomm (unused)
       return;
     }
 
-  /* allocate_bss: */
+  /* Allocate_bss:  */
   old_sec = now_seg;
   old_subsec = now_subseg;
   if (align)
     {
-      /* convert to a power of 2 alignment */
+      /* Convert to a power of 2 alignment.  */
       for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2)
 	;
       if (align != 1)
@@ -1227,10 +1133,9 @@ i370_elf_lcomm (unused)
 /* Validate any relocations emitted for -mrelocatable, possibly adding
    fixups for word relocations in writable segments, so we can adjust
    them at runtime.  */
+
 static void
-i370_elf_validate_fix (fixp, seg)
-     fixS *fixp;
-     segT seg;
+i370_elf_validate_fix (fixS *fixp, segT seg)
 {
   if (fixp->fx_done || fixp->fx_pcrel)
     return;
@@ -1261,12 +1166,12 @@ i370_elf_validate_fix (fixp, seg)
         {
           if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0
               || fixp->fx_r_type != BFD_RELOC_CTOR)
-            {
-              as_bad_where (fixp->fx_file, fixp->fx_line,
-        		    "Relocation cannot be done when using -mrelocatable");
-            }
+	    as_bad_where (fixp->fx_file, fixp->fx_line,
+			  "Relocation cannot be done when using -mrelocatable");
         }
       return;
+    default:
+      break;
     }
 }
 #endif /* OBJ_ELF */
@@ -1274,20 +1179,18 @@ i370_elf_validate_fix (fixp, seg)
 
 #define LITERAL_POOL_SUPPORT
 #ifdef LITERAL_POOL_SUPPORT
-/* Provide support for literal pools within the text section.  */
-/* Loosely based on similar code from tc-arm.c  */
-/*
- * We will use four symbols to locate four parts of the literal pool.
- *    These four sections contain 64,32,16 and 8-bit constants; we use
- *    four sections so that all memory access can be appropriately aligned.
- *    That is, we want to avoid mixing these together so that we don't
- *    waste space padding out to alignments.  The four pointers
- *    longlong_poolP, word_poolP, etc. point to a symbol labeling the
- *    start of each pool part.
- *
- * lit_pool_num increments from zero to infinity and uniquely id's
- *    -- its used to generate the *_poolP symbol name.
- */
+/* Provide support for literal pools within the text section.
+   Loosely based on similar code from tc-arm.c.
+   We will use four symbols to locate four parts of the literal pool.
+   These four sections contain 64,32,16 and 8-bit constants; we use
+   four sections so that all memory access can be appropriately aligned.
+   That is, we want to avoid mixing these together so that we don't
+   waste space padding out to alignments.  The four pointers
+   longlong_poolP, word_poolP, etc. point to a symbol labeling the
+   start of each pool part.
+ 
+   lit_pool_num increments from zero to infinity and uniquely id's
+     -- its used to generate the *_poolP symbol name.  */
 
 #define MAX_LITERAL_POOL_SIZE 1024
 
@@ -1300,16 +1203,16 @@ typedef struct literalS
 } literalT;
 
 literalT literals[MAX_LITERAL_POOL_SIZE];
-int next_literal_pool_place = 0; /* Next free entry in the pool */
+int next_literal_pool_place = 0; /* Next free entry in the pool.  */
 
-static symbolS *longlong_poolP = NULL;   /* 64-bit pool entries */
-static symbolS *word_poolP = NULL;       /* 32-bit pool entries */
-static symbolS *short_poolP = NULL;      /* 16-bit pool entries */
-static symbolS *byte_poolP = NULL;       /* 8-bit  pool entries */
+static symbolS *longlong_poolP = NULL;   /* 64-bit pool entries.  */
+static symbolS *word_poolP = NULL;       /* 32-bit pool entries.  */
+static symbolS *short_poolP = NULL;      /* 16-bit pool entries.  */
+static symbolS *byte_poolP = NULL;       /* 8-bit  pool entries.  */
 
 static int lit_pool_num = 1;
 
-/* create a new, empty symbol */
+/* Create a new, empty symbol.  */
 static symbolS *
 symbol_make_empty (void)
 {
@@ -1317,14 +1220,41 @@ symbol_make_empty (void)
   			(valueT) 0, &zero_address_frag);
 }
 
-/* add an expression to the literal pool */
+/* Make the first argument an address-relative expression
+   by subtracting the second argument.  */
+
+static void
+i370_make_relative (expressionS *exx, expressionS *baseaddr)
+{
+  if (O_constant == baseaddr->X_op)
+    {
+       exx->X_op = O_symbol;
+       exx->X_add_number -= baseaddr->X_add_number;
+    }
+  else if (O_symbol == baseaddr->X_op)
+    {
+       exx->X_op = O_subtract;
+       exx->X_op_symbol = baseaddr->X_add_symbol;
+       exx->X_add_number -= baseaddr->X_add_number;
+    }
+  else if (O_uminus == baseaddr->X_op)
+    {
+       exx->X_op = O_add;
+       exx->X_op_symbol = baseaddr->X_add_symbol;
+       exx->X_add_number += baseaddr->X_add_number;
+    }
+  else
+    as_bad ("Missing or bad .using directive");
+}
+/* Add an expression to the literal pool.  */
+
 static  void
 add_to_lit_pool (expressionS *exx, char *name, int sz)
 {
   int lit_count = 0;
   int offset_in_pool = 0;
 
-  /* start a new pool, if necessary */
+  /* Start a new pool, if necessary.  */
   if (8 == sz && NULL == longlong_poolP)
     longlong_poolP = symbol_make_empty ();
   else if (4 == sz && NULL == word_poolP)
@@ -1334,12 +1264,11 @@ add_to_lit_pool (expressionS *exx, char *name, int sz)
   else if (1 == sz && NULL == byte_poolP)
     byte_poolP = symbol_make_empty ();
 
-  /* Check if this literal value is already in the pool: */
-  /* hack alert -- we should probably be checking expressions
-   * of type O_symbol as well ...  */
-  /* hack alert XXX this is probably(certainly?) broken for O_big,
-   * which includes 64-bit long-longs ...
-   */
+  /* Check if this literal value is already in the pool.
+     FIXME: We should probably be checking expressions
+            of type O_symbol as well.
+     FIXME: This is probably(certainly?) broken for O_big,
+            which includes 64-bit long-longs.  */
   while (lit_count < next_literal_pool_place)
     {
       if (exx->X_op == O_constant
@@ -1360,30 +1289,23 @@ add_to_lit_pool (expressionS *exx, char *name, int sz)
   if (lit_count == next_literal_pool_place) /* new entry */
     {
       if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
-        {
-          as_bad ("Literal Pool Overflow");
-        }
+	as_bad ("Literal Pool Overflow");
 
       literals[next_literal_pool_place].exp = *exx;
       literals[next_literal_pool_place].size = sz;
       literals[next_literal_pool_place].offset = offset_in_pool;
       if (name)
-	{
-	  literals[next_literal_pool_place].sym_name = strdup (name);
-	}
+	literals[next_literal_pool_place].sym_name = strdup (name);
       else
-	{
-	  literals[next_literal_pool_place].sym_name = NULL;
-	}
+	literals[next_literal_pool_place].sym_name = NULL;
       next_literal_pool_place++;
     }
 
   /* ???_poolP points to the beginning of the literal pool.
-   * X_add_number is the offset from the beginning of the
-   * literal pool to this expr minus the location of the most
-   * recent .using directive.  Thus, the grand total value of the
-   * expression is the distance from .using to the literal.
-   */
+     X_add_number is the offset from the beginning of the
+     literal pool to this expr minus the location of the most
+     recent .using directive.  Thus, the grand total value of the
+     expression is the distance from .using to the literal.  */
   if (8 == sz)
     exx->X_add_symbol = longlong_poolP;
   else if (4 == sz)
@@ -1396,36 +1318,28 @@ add_to_lit_pool (expressionS *exx, char *name, int sz)
   exx->X_op_symbol = NULL;
 
   /* If the user has set up a base reg in another section,
-   * use that; otherwise use the text section.  */
+     use that; otherwise use the text section.  */
   if (0 < i370_using_other_regno)
-    {
-      i370_make_relative (exx, &i370_using_other_baseaddr);
-    }
+    i370_make_relative (exx, &i370_using_other_baseaddr);
   else
-    {
-      i370_make_relative (exx, &i370_using_text_baseaddr);
-    }
+    i370_make_relative (exx, &i370_using_text_baseaddr);
 }
 
 /* The symbol setup for the literal pool is done in two steps.  First,
- * a symbol that represents the start of the literal pool is created,
- * above, in the add_to_pool() routine. This sym ???_poolP.
- * However, we don't know what fragment its in until a bit later.
- * So we defer the frag_now thing, and the symbol name, until .ltorg time
- */
+   a symbol that represents the start of the literal pool is created,
+   above, in the add_to_pool() routine. This sym ???_poolP.
+   However, we don't know what fragment its in until a bit later.
+   So we defer the frag_now thing, and the symbol name, until .ltorg time.  */
 
 /* Can't use symbol_new here, so have to create a symbol and then at
-   a later date assign it a value. Thats what these functions do */
-static void symbol_locate
-  PARAMS ((symbolS *, const char *, segT, valueT, fragS *));
+   a later date assign it a value. Thats what these functions do.  */
 
 static void
-symbol_locate (symbolP, name, segment, valu, frag)
-     symbolS *symbolP;
-     const char *name;		/* It is copied, the caller can modify */
-     segT segment;		/* Segment identifier (SEG_<something>) */
-     valueT valu;		/* Symbol value */
-     fragS *frag;		/* Associated fragment */
+symbol_locate (symbolS *symbolP,
+	       const char *name,	/* It is copied, the caller can modify.  */
+	       segT segment,		/* Segment identifier (SEG_<something>).  */
+	       valueT valu,		/* Symbol value.  */
+	       fragS *frag)		/* Associated fragment.  */
 {
   size_t name_length;
   char *preserved_copy_of_name;
@@ -1442,11 +1356,10 @@ symbol_locate (symbolP, name, segment, valu, frag)
 
   symbol_set_frag (symbolP, frag);
 
-  /*
-   * Link to end of symbol chain.
-   */
+  /* Link to end of symbol chain.  */
   {
     extern int symbol_table_frozen;
+
     if (symbol_table_frozen)
       abort ();
   }
@@ -1466,20 +1379,20 @@ symbol_locate (symbolP, name, segment, valu, frag)
 }
 
 /* i370_addr_offset() will convert operand expressions
- * that appear to be absolute into thier base-register
- * relative form.  These expressions come in two types:
- *
- * (1) of the form "* + const" * where "*" means
- * relative offset since the last using
- * i.e. "*" means ".-using_baseaddr"
- *
- * (2) labels, which are never absolute, but are always
- * relative to the last "using".  Anything with an alpha
- * character is considered to be a label (since symbols
- * can never be operands), and since we've already handled
- * register operands. For example, "BL .L33" branch low
- * to .L33 RX form insn frequently terminates for-loops,
- */
+   that appear to be absolute into thier base-register
+   relative form.  These expressions come in two types:
+
+   (1) of the form "* + const" * where "*" means
+   relative offset since the last using
+   i.e. "*" means ".-using_baseaddr"
+
+   (2) labels, which are never absolute, but are always
+   relative to the last "using".  Anything with an alpha
+   character is considered to be a label (since symbols
+   can never be operands), and since we've already handled
+   register operands. For example, "BL .L33" branch low
+   to .L33 RX form insn frequently terminates for-loops.  */
+
 static bfd_boolean
 i370_addr_offset (expressionS *exx)
 {
@@ -1487,15 +1400,13 @@ i370_addr_offset (expressionS *exx)
   int islabel = 0;
   int all_digits = 0;
 
-  /* search for a label; anything with an alpha char will do */
-  /* local labels consist of N digits followed by either b or f */
+  /* Search for a label; anything with an alpha char will do.
+     Local labels consist of N digits followed by either b or f.  */
   lab = input_line_pointer;
   while (*lab && (',' != *lab) && ('(' != *lab))
     {
       if (ISDIGIT (*lab))
-	{
-	  all_digits = 1;
-	}
+	all_digits = 1;
       else if (ISALPHA (*lab))
 	{
 	  if (!all_digits)
@@ -1516,75 +1427,65 @@ i370_addr_offset (expressionS *exx)
       ++lab;
     }
 
-  /* See if operand has a * in it */
+  /* See if operand has a * in it.  */
   dot = strchr (input_line_pointer, '*');
 
   if (!dot && !islabel)
     return FALSE;
 
-  /* replace * with . and let expr munch on it.  */
+  /* Replace * with . and let expr munch on it.  */
   if (dot)
     *dot = '.';
   expression (exx);
 
-  /* OK, now we have to subtract the "using" location  */
-  /* normally branches appear in the text section only...  */
+  /* OK, now we have to subtract the "using" location.
+     Normally branches appear in the text section only.  */
   if (0 == strncmp (now_seg->name, ".text", 5) || 0 > i370_using_other_regno)
-    {
-      i370_make_relative (exx, &i370_using_text_baseaddr);
-    }
+    i370_make_relative (exx, &i370_using_text_baseaddr);
   else
-    {
-      i370_make_relative (exx, &i370_using_other_baseaddr);
-    }
+    i370_make_relative (exx, &i370_using_other_baseaddr);
 
-  /* put the * back */
+  /* Put the * back.  */
   if (dot)
     *dot = '*';
 
   return TRUE;
 }
 
-/* handle address constants of various sorts */
+/* Handle address constants of various sorts.  */
 /* The currently supported types are
- *    =A(some_symb)
- *    =V(some_extern)
- *    =X'deadbeef'    hexadecimal
- *    =F'1234'        32-bit const int
- *    =H'1234'        16-bit const int
- */
+      =A(some_symb)
+      =V(some_extern)
+      =X'deadbeef'    hexadecimal
+      =F'1234'        32-bit const int
+      =H'1234'        16-bit const int.  */
+
 static bfd_boolean
 i370_addr_cons (expressionS *exp)
 {
   char *name;
   char *sym_name, delim;
   int name_len;
-  int hex_len=0;
-  int cons_len=0;
+  int hex_len = 0;
+  int cons_len = 0;
 
   name = input_line_pointer;
   sym_name = input_line_pointer;
-  /* Find the spelling of the operand */
+  /* Find the spelling of the operand.  */
   if (name[0] == '=' && ISALPHA (name[1]))
-    {
-      name = ++input_line_pointer;
-    }
+    name = ++input_line_pointer;
   else
-    {
-      return FALSE;
-    }
+    return FALSE;
+
   switch (name[0])
     {
-    case 'A':
-    case 'V':
-      /* A == address-of */
-      /* V == extern */
+    case 'A': /* A == address-of.  */
+    case 'V': /* V == extern.  */
       ++input_line_pointer;
       expression (exp);
 
-      /* we use a simple string name to collapse together
-       * multiple refrences to the same address literal
-       */
+      /* We use a simple string name to collapse together
+         multiple refrences to the same address literal.  */
       name_len = strcspn (sym_name, ", ");
       delim = *(sym_name + name_len);
       *(sym_name + name_len) = 0x0;
@@ -1595,29 +1496,30 @@ i370_addr_cons (expressionS *exp)
     case 'H':
     case 'F':
     case 'X':
-    case 'E':  /* single-precision float point */
-    case 'D':  /* double-precision float point */
+    case 'E':  /* Single-precision float point.  */
+    case 'D':  /* Double-precision float point.  */
 
-      /* H == 16-bit fixed-point const; expression must be const */
-      /* F == fixed-point const; expression must be const */
-      /* X == fixed-point const; expression must be const */
+      /* H == 16-bit fixed-point const; expression must be const.  */
+      /* F == fixed-point const; expression must be const.  */
+      /* X == fixed-point const; expression must be const.  */
       if ('H' == name[0]) cons_len = 2;
       else if ('F' == name[0]) cons_len = 4;
       else if ('X' == name[0]) cons_len = -1;
       else if ('E' == name[0]) cons_len = 4;
       else if ('D' == name[0]) cons_len = 8;
 
-      /* extract length, if it is present; hack alert -- assume single-digit
-       * length */
+      /* Extract length, if it is present;
+	 FIXME: assume single-digit length.  */
       if ('L' == name[1])
 	{
-	  cons_len = name[2] - '0';  /* should work for ascii and ebcdic */
+	  /* Should work for ASCII and EBCDIC.  */
+	  cons_len = name[2] - '0';
 	  input_line_pointer += 2;
 	}
 
       ++input_line_pointer;
 
-      /* get rid of pesky quotes */
+      /* Get rid of pesky quotes.  */
       if ('\'' == *input_line_pointer)
 	{
 	  char * close;
@@ -1644,12 +1546,11 @@ i370_addr_cons (expressionS *exp)
 	  char *save;
 
 	  /* The length of hex constants is specified directly with L,
-	   * or implied through the number of hex digits. For example:
-	   * =X'AB'       one byte
-	   * =X'abcd'     two bytes
-	   * =X'000000AB' four bytes
-	   * =XL4'AB'     four bytes, left-padded withn zero
-	   */
+	     or implied through the number of hex digits. For example:
+	     =X'AB'       one byte
+	     =X'abcd'     two bytes
+	     =X'000000AB' four bytes
+	     =XL4'AB'     four bytes, left-padded withn zero.  */
 	  if (('X' == name[0]) && (0 > cons_len))
 	    {
 	      save = input_line_pointer;
@@ -1662,10 +1563,9 @@ i370_addr_cons (expressionS *exp)
 	      cons_len = (hex_len+1) /2;
 	    }
 	  /* I believe this works even for =XL8'dada0000beeebaaa'
-	   * which should parse out to X_op == O_big
-	   * Note that floats and doubles get represented as
-	   * 0d3.14159265358979  or 0f 2.7
-	   */
+	     which should parse out to X_op == O_big
+	     Note that floats and doubles get represented as
+	     0d3.14159265358979  or 0f 2.7.  */
 	  tmp[0] = '0';
 	  tmp[1] = name[0];
 	  tmp[2] = 0;
@@ -1675,17 +1575,14 @@ i370_addr_cons (expressionS *exp)
 	  expression (exp);
 	  input_line_pointer = save + (input_line_pointer-tmp-2);
 
-	  /* fix up lengths for floats and doubles */
+	  /* Fix up lengths for floats and doubles.  */
 	  if (O_big == exp->X_op)
-	    {
-	      exp->X_add_number = cons_len / CHARS_PER_LITTLENUM;
-	    }
+	    exp->X_add_number = cons_len / CHARS_PER_LITTLENUM;
 	}
       else
-	{
-	  expression (exp);
-	}
-      /* O_big occurs when more than 4 bytes worth gets parsed */
+	expression (exp);
+
+      /* O_big occurs when more than 4 bytes worth gets parsed.  */
       if ((exp->X_op != O_constant) && (exp->X_op != O_big))
 	{
 	  as_bad ("expression not a constant");
@@ -1704,12 +1601,10 @@ i370_addr_cons (expressionS *exp)
 
 
 /* Dump the contents of the literal pool that we've accumulated so far.
- * This aligns the pool to the size of the largest literal in the pool.
- */
+   This aligns the pool to the size of the largest literal in the pool.  */
 
 static void
-i370_ltorg (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+i370_ltorg (int ignore ATTRIBUTE_UNUSED)
 {
   int litsize;
   int lit_count = 0;
@@ -1720,27 +1615,22 @@ i370_ltorg (ignore)
   if (strncmp (now_seg->name, ".text", 5))
     {
       if (i370_other_section == undefined_section)
-        {
-          as_bad (".ltorg without prior .using in section %s",
-		  now_seg->name);
-        }
+	as_bad (".ltorg without prior .using in section %s",
+		now_seg->name);
+
       if (i370_other_section != now_seg)
-        {
-	  as_bad (".ltorg in section %s paired to .using in section %s",
-		  now_seg->name, i370_other_section->name);
-        }
+	as_bad (".ltorg in section %s paired to .using in section %s",
+		now_seg->name, i370_other_section->name);
     }
+
   if (! longlong_poolP
       && ! word_poolP
       && ! short_poolP
       && ! byte_poolP)
-    {
-      /* Nothing to do */
-      /* as_tsktsk ("Nothing to put in the pool\n"); */
-      return;
-    }
+    /* Nothing to do.  */
+    return;
 
-  /* find largest literal .. 2 4 or 8 */
+  /* Find largest literal .. 2 4 or 8.  */
   lit_count = 0;
   while (lit_count < next_literal_pool_place)
     {
@@ -1755,14 +1645,13 @@ i370_ltorg (ignore)
   else as_bad ("bad alignment of %d bytes in literal pool", biggest_literal_size);
   if (0 == biggest_align) biggest_align = 1;
 
-  /* Align pool for short, word, double word accesses */
+  /* Align pool for short, word, double word accesses.  */
   frag_align (biggest_align, 0, 0);
   record_alignment (now_seg, biggest_align);
 
   /* Note that the gas listing will print only the first five
-   * entries in the pool .... wonder how to make it print more ...
-   */
-  /* output largest literals first, then the smaller ones.  */
+     entries in the pool .... wonder how to make it print more.  */
+  /* Output largest literals first, then the smaller ones.  */
   for (litsize=8; litsize; litsize /=2)
     {
       symbolS *current_poolP = NULL;
@@ -1793,11 +1682,10 @@ i370_ltorg (ignore)
 	    {
 #define EMIT_ADDR_CONS_SYMBOLS
 #ifdef EMIT_ADDR_CONS_SYMBOLS
-	      /* create a bogus symbol, add it to the pool ...
-	       * For the most part, I think this is a useless exercise,
-	       * except that having these symbol names in the objects
-	       * is vaguely useful for debugging ...
-	       */
+	      /* Create a bogus symbol, add it to the pool ...
+	         For the most part, I think this is a useless exercise,
+	         except that having these symbol names in the objects
+	         is vaguely useful for debugging.  */
 	      if (literals[lit_count].sym_name)
 		{
 		  symbolS * symP = symbol_make_empty ();
@@ -1824,42 +1712,39 @@ i370_ltorg (ignore)
 #endif /* LITERAL_POOL_SUPPORT */
 
 
-/* add support for the HLASM-like USING directive to indicate
- * the base register to use ...  we don't support the full
- * hlasm semantics for this ... we merely pluck a base address
- * and a register number out.  We print a warning if using is
- * called multiple times.  I suppose we should check to see
- * if the regno is valid ...
- */
+/* Add support for the HLASM-like USING directive to indicate
+   the base register to use ...  we don't support the full
+   hlasm semantics for this ... we merely pluck a base address
+   and a register number out.  We print a warning if using is
+   called multiple times.  I suppose we should check to see
+   if the regno is valid.  */
+
 static void
-i370_using (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+i370_using (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS ex, baseaddr;
   int iregno;
   char *star;
 
-  /* if "*" appears in a using, it means "."  */
-  /* replace it with "." so that expr doesn't get confused.  */
+  /* If "*" appears in a using, it means "."
+     replace it with "." so that expr doesn't get confused.  */
   star = strchr (input_line_pointer, '*');
   if (star)
     *star = '.';
 
-  /* the first arg to using will usually be ".", but it can
-   * be a more complex expression too ...  */
+  /* The first arg to using will usually be ".", but it can
+     be a more complex expression too.  */
   expression (&baseaddr);
   if (star)
     *star = '*';
   if (O_constant != baseaddr.X_op
       && O_symbol != baseaddr.X_op
       && O_uminus != baseaddr.X_op)
-  {
     as_bad (".using: base address expression illegal or too complex");
-  }
 
   if (*input_line_pointer != '\0') ++input_line_pointer;
 
-  /* the second arg to using had better be a register */
+  /* The second arg to using had better be a register.  */
   register_name (&ex);
   demand_empty_rest_of_line ();
   iregno = ex.X_add_number;
@@ -1878,8 +1763,7 @@ i370_using (ignore)
 }
 
 static void
-i370_drop (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+i370_drop (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS ex;
   int iregno;
@@ -1891,60 +1775,28 @@ i370_drop (ignore)
   if (0 == strncmp (now_seg->name, ".text", 5))
     {
       if (iregno != i370_using_text_regno)
-        {
-          as_bad ("droping register %d in section %s does not match using register %d",
-		  iregno, now_seg->name, i370_using_text_regno);
-        }
+	as_bad ("droping register %d in section %s does not match using register %d",
+		iregno, now_seg->name, i370_using_text_regno);
+
       i370_using_text_regno = -1;
       i370_using_text_baseaddr.X_op = O_absent;
     }
   else
     {
       if (iregno != i370_using_other_regno)
-        {
-          as_bad ("droping register %d in section %s does not match using register %d",
-		  iregno, now_seg->name, i370_using_other_regno);
-        }
+	as_bad ("droping register %d in section %s does not match using register %d",
+		iregno, now_seg->name, i370_using_other_regno);
+
       if (i370_other_section != now_seg)
-        {
-          as_bad ("droping register %d in section %s previously used in section %s",
-		  iregno, now_seg->name, i370_other_section->name);
-        }
+	as_bad ("droping register %d in section %s previously used in section %s",
+		iregno, now_seg->name, i370_other_section->name);
+
       i370_using_other_regno = -1;
       i370_using_other_baseaddr.X_op = O_absent;
       i370_other_section = undefined_section;
     }
 }
 
-/* Make the first argument an address-relative expression
- * by subtracting the second argument.
- */
-static void
-i370_make_relative (expressionS *exx, expressionS *baseaddr)
-{
-
-  if (O_constant == baseaddr->X_op)
-    {
-       exx->X_op = O_symbol;
-       exx->X_add_number -= baseaddr->X_add_number;
-    }
-  else if (O_symbol == baseaddr->X_op)
-    {
-       exx->X_op = O_subtract;
-       exx->X_op_symbol = baseaddr->X_add_symbol;
-       exx->X_add_number -= baseaddr->X_add_number;
-    }
-  else if (O_uminus == baseaddr->X_op)
-    {
-       exx->X_op = O_add;
-       exx->X_op_symbol = baseaddr->X_add_symbol;
-       exx->X_add_number += baseaddr->X_add_number;
-     }
-  else
-     {
-       as_bad ("Missing or bad .using directive");
-     }
-}
 
 /* We need to keep a list of fixups.  We can't simply generate them as
    we go, because that would require us to first create the frag, and
@@ -1957,13 +1809,90 @@ struct i370_fixup
   bfd_reloc_code_real_type reloc;
 };
 
-#define MAX_INSN_FIXUPS (5)
+#define MAX_INSN_FIXUPS 5
+
+/* Handle a macro.  Gather all the operands, transform them as
+   described by the macro, and call md_assemble recursively.  All the
+   operands are separated by commas; we don't accept parentheses
+   around operands here.  */
+
+static void
+i370_macro (char *str, const struct i370_macro *macro)
+{
+  char *operands[10];
+  unsigned int count;
+  char *s;
+  unsigned int len;
+  const char *format;
+  int arg;
+  char *send;
+  char *complete;
+
+  /* Gather the users operands into the operands array.  */
+  count = 0;
+  s = str;
+  while (1)
+    {
+      if (count >= sizeof operands / sizeof operands[0])
+        break;
+      operands[count++] = s;
+      s = strchr (s, ',');
+      if (s == (char *) NULL)
+        break;
+      *s++ = '\0';
+    }
+
+  if (count != macro->operands)
+    {
+      as_bad ("wrong number of operands");
+      return;
+    }
+
+  /* Work out how large the string must be (the size is unbounded
+     because it includes user input).  */
+  len = 0;
+  format = macro->format;
+  while (*format != '\0')
+    {
+      if (*format != '%')
+        {
+          ++len;
+          ++format;
+        }
+      else
+        {
+          arg = strtol (format + 1, &send, 10);
+          know (send != format && arg >= 0 && (unsigned) arg < count);
+          len += strlen (operands[arg]);
+          format = send;
+        }
+    }
+
+  /* Put the string together.  */
+  complete = s = alloca (len + 1);
+  format = macro->format;
+  while (*format != '\0')
+    {
+      if (*format != '%')
+        *s++ = *format++;
+      else
+        {
+          arg = strtol (format + 1, &send, 10);
+          strcpy (s, operands[arg]);
+          s += strlen (s);
+          format = send;
+        }
+    }
+  *s = '\0';
+
+  /* Assemble the constructed instruction.  */
+  md_assemble (complete);
+}
 
 /* This routine is called for each instruction to be assembled.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *s, *opcode_str;
   const struct i370_opcode *opcode;
@@ -2026,6 +1955,7 @@ md_assemble (str)
   for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
     {
       const struct i370_operand *operand;
+
       operand = &i370_operands[*opindex_ptr];
       if ((operand->flags & I370_OPERAND_INDEX) != 0)
 	have_optional_index = 1;
@@ -2060,7 +1990,7 @@ md_assemble (str)
       /* If there are fewer operands in the line then are called
 	 for by the instruction, we want to skip the optional
 	 operand.  */
-      nwanted = strlen (opcode->operands);
+      nwanted = strlen ((char *) opcode->operands);
       if (have_optional_index)
 	{
 	  if (opcount < nwanted)
@@ -2080,12 +2010,11 @@ md_assemble (str)
     }
 
   /* Perform some off-by-one hacks on the length field of certain instructions.
-   * Its such a shame to have to do this, but the problem is that HLASM got
-   * defined so that the lengths differ by one from the actual machine instructions.
-   * this code should probably be moved to a special inster-operand routine.
-   * Sigh. Affected instructions are Compare Logical, Move and Exclusive OR
-   * hack alert -- aren't *all* SS instructions affected ??
-   */
+     Its such a shame to have to do this, but the problem is that HLASM got
+     defined so that the lengths differ by one from the actual machine instructions.
+     this code should probably be moved to a special inster-operand routine.
+     Sigh. Affected instructions are Compare Logical, Move and Exclusive OR
+     hack alert -- aren't *all* SS instructions affected ??  */
   off_by_one = 0;
   if (0 == strcasecmp ("CLC", opcode->name)
       || 0 == strcasecmp ("ED", opcode->name)
@@ -2130,29 +2059,20 @@ md_assemble (str)
             {
               if (0 == strncmp (now_seg->name, ".text", 5)
 		  || 0 > i370_using_other_regno)
-                {
-                  basereg = i370_using_text_regno;
-                }
+		basereg = i370_using_text_regno;
               else
-                {
-                  basereg = i370_using_other_regno;
-                }
+		basereg = i370_using_other_regno;
             }
           else if (use_other)
             {
               if (0 > i370_using_other_regno)
-                {
-                  basereg = i370_using_text_regno;
-                }
+		basereg = i370_using_text_regno;
               else
-                {
-                  basereg = i370_using_other_regno;
-                }
+		basereg = i370_using_other_regno;
             }
           if (0 > basereg)
-            {
-              as_bad ("not using any base register");
-            }
+	    as_bad ("not using any base register");
+
           insn = i370_insert_operand (insn, operand, basereg);
           continue;
         }
@@ -2170,60 +2090,53 @@ md_assemble (str)
       hold = input_line_pointer;
       input_line_pointer = str;
 
-      /* register names are only allowed where there are registers ...  */
+      /* Register names are only allowed where there are registers.  */
       if ((operand->flags & I370_OPERAND_GPR) != 0)
         {
-          /* quickie hack to get past things like (,r13) */
+          /* Quickie hack to get past things like (,r13).  */
           if (skip_optional_index && (',' == *input_line_pointer))
             {
               *input_line_pointer = ' ';
               input_line_pointer ++;
             }
+
           if (! register_name (&ex))
-            {
-              as_bad ("expecting a register for operand %d",
-		      opindex_ptr - opcode->operands + 1);
-            }
+	    as_bad ("expecting a register for operand %d",
+		    (int) (opindex_ptr - opcode->operands + 1));
         }
 
       /* Check for an address constant expression.  */
       /* We will put PSW-relative addresses in the text section,
-       * and address literals in the .data (or other) section.  */
+         and address literals in the .data (or other) section.  */
       else if (i370_addr_cons (&ex))
-	use_other=1;
+	use_other = 1;
       else if (i370_addr_offset (&ex))
-	use_text=1;
+	use_text = 1;
       else expression (&ex);
 
       str = input_line_pointer;
       input_line_pointer = hold;
 
-      /* perform some off-by-one hacks on the length field of certain instructions.
-       * Its such a shame to have to do this, but the problem is that HLASM got
-       * defined so that the programmer specifies a length that is one greater
-       * than what the machine instruction wants.
-       * Sigh.
-       */
+      /* Perform some off-by-one hacks on the length field of certain instructions.
+         Its such a shame to have to do this, but the problem is that HLASM got
+         defined so that the programmer specifies a length that is one greater
+         than what the machine instruction wants.  Sigh.  */
       if (off_by_one && (0 == strcasecmp ("SS L", operand->name)))
-	{
-	  ex.X_add_number --;
-	}
+	ex.X_add_number --;
 
       if (ex.X_op == O_illegal)
         as_bad ("illegal operand");
       else if (ex.X_op == O_absent)
         as_bad ("missing operand");
       else if (ex.X_op == O_register)
-        {
-          insn = i370_insert_operand (insn, operand, ex.X_add_number);
-        }
+	insn = i370_insert_operand (insn, operand, ex.X_add_number);
       else if (ex.X_op == O_constant)
         {
 #ifdef OBJ_ELF
           /* Allow @HA, @L, @H on constants.
-           * Well actually, no we don't; there really don't make sense
-           * (at least not to me) for the i370.  However, this code is
-           * left here for any dubious future expansion reasons ...  */
+             Well actually, no we don't; there really don't make sense
+             (at least not to me) for the i370.  However, this code is
+             left here for any dubious future expansion reasons.  */
           char *orig_str = str;
 
           if ((reloc = i370_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED)
@@ -2268,14 +2181,12 @@ md_assemble (str)
           ++fc;
         }
 #endif /* OBJ_ELF */
-
       else
         {
           /* We need to generate a fixup for this expression.  */
           /* Typically, the expression will just be a symbol ...
-           * printf ("insn %s needs fixup for %s \n",
-           *        opcode->name, ex.X_add_symbol->bsym->name);
-           */
+               printf ("insn %s needs fixup for %s \n",
+                    opcode->name, ex.X_add_symbol->bsym->name);  */
 
           if (fc >= MAX_INSN_FIXUPS)
             as_fatal ("too many fixups");
@@ -2285,7 +2196,7 @@ md_assemble (str)
           ++fc;
         }
 
-      /* skip over delimiter (close paren, or comma) */
+      /* Skip over delimiter (close paren, or comma).  */
       if ((')' == *str) && (',' == *(str+1)))
 	++str;
       if (*str != '\0')
@@ -2301,21 +2212,18 @@ md_assemble (str)
   /* Write out the instruction.  */
   f = frag_more (opcode->len);
   if (4 >= opcode->len)
-    {
-      md_number_to_chars (f, insn.i[0], opcode->len);
-    }
+    md_number_to_chars (f, insn.i[0], opcode->len);
   else
     {
       md_number_to_chars (f, insn.i[0], 4);
+
       if (6 == opcode->len)
-	{
-	  md_number_to_chars ((f+4), ((insn.i[1])>>16), 2);
-	}
+	md_number_to_chars ((f + 4), ((insn.i[1])>>16), 2);
       else
 	{
-	  /* not used --- don't have any 8 byte instructions */
+	  /* Not used --- don't have any 8 byte instructions.  */
 	  as_bad ("Internal Error: bad instruction length");
-	  md_number_to_chars ((f+4), insn.i[1], opcode->len -4);
+	  md_number_to_chars ((f + 4), insn.i[1], opcode->len -4);
 	}
     }
 
@@ -2324,7 +2232,7 @@ md_assemble (str)
      BFD_RELOC_UNUSED plus the operand index.  This lets us easily
      handle fixups for any operand type, although that is admittedly
      not a very exciting feature.  We pick a BFD reloc type in
-     md_apply_fix3.  */
+     md_apply_fix.  */
   for (i = 0; i < fc; i++)
     {
       const struct i370_operand *operand;
@@ -2374,139 +2282,6 @@ md_assemble (str)
     }
 }
 
-/* Handle a macro.  Gather all the operands, transform them as
-   described by the macro, and call md_assemble recursively.  All the
-   operands are separated by commas; we don't accept parentheses
-   around operands here.  */
-
-static void
-i370_macro (str, macro)
-     char *str;
-     const struct i370_macro *macro;
-{
-  char *operands[10];
-  unsigned int count;
-  char *s;
-  unsigned int len;
-  const char *format;
-  int arg;
-  char *send;
-  char *complete;
-
-  /* Gather the users operands into the operands array.  */
-  count = 0;
-  s = str;
-  while (1)
-    {
-      if (count >= sizeof operands / sizeof operands[0])
-        break;
-      operands[count++] = s;
-      s = strchr (s, ',');
-      if (s == (char *) NULL)
-        break;
-      *s++ = '\0';
-    }
-
-  if (count != macro->operands)
-    {
-      as_bad ("wrong number of operands");
-      return;
-    }
-
-  /* Work out how large the string must be (the size is unbounded
-     because it includes user input).  */
-  len = 0;
-  format = macro->format;
-  while (*format != '\0')
-    {
-      if (*format != '%')
-        {
-          ++len;
-          ++format;
-        }
-      else
-        {
-          arg = strtol (format + 1, &send, 10);
-          know (send != format && arg >= 0 && arg < count);
-          len += strlen (operands[arg]);
-          format = send;
-        }
-    }
-
-  /* Put the string together.  */
-  complete = s = (char *) alloca (len + 1);
-  format = macro->format;
-  while (*format != '\0')
-    {
-      if (*format != '%')
-        *s++ = *format++;
-      else
-        {
-          arg = strtol (format + 1, &send, 10);
-          strcpy (s, operands[arg]);
-          s += strlen (s);
-          format = send;
-        }
-    }
-  *s = '\0';
-
-  /* Assemble the constructed instruction.  */
-  md_assemble (complete);
-}
-
-#if 0
-/* For ELF, add support for SHF_EXCLUDE and SHT_ORDERED */
-
-int
-i370_section_letter (letter, ptr_msg)
-     int letter;
-     char **ptr_msg;
-{
-  if (letter == 'e')
-    return SHF_EXCLUDE;
-
-  *ptr_msg = "Bad .section directive: want a,e,w,x,M,S in string";
-  return 0;
-}
-
-int
-i370_section_word (str, len)
-    char *str;
-    size_t len;
-{
-  if (len == 7 && strncmp (str, "exclude", 7) == 0)
-    return SHF_EXCLUDE;
-
-  return -1;
-}
-
-int
-i370_section_type (str, len)
-    char *str;
-    size_t len;
-{
-  if (len == 7 && strncmp (str, "ordered", 7) == 0)
-     return SHT_ORDERED;
-
-  return -1;
-}
-
-int
-i370_section_flags (flags, attr, type)
-     int flags;
-     int attr;
-     int type;
-{
-  if (type == SHT_ORDERED)
-    flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES;
-
-  if (attr & SHF_EXCLUDE)
-    flags |= SEC_EXCLUDE;
-
-  return flags;
-}
-#endif /* OBJ_ELF */
-
 
 /* Pseudo-op handling.  */
 
@@ -2514,8 +2289,7 @@ i370_section_flags (flags, attr, type)
    pseudo-op, but it can also take a single ASCII string.  */
 
 static void
-i370_byte (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+i370_byte (int ignore ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer != '\"')
     {
@@ -2558,8 +2332,7 @@ i370_byte (ignore)
    the first argument is simply ignored.  */
 
 static void
-i370_tc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+i370_tc (int ignore ATTRIBUTE_UNUSED)
 {
 
   /* Skip the TOC symbol name.  */
@@ -2589,10 +2362,7 @@ i370_tc (ignore)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litp, sizep)
-     int type;
-     char *litp;
-     int *sizep;
+md_atof (int type, char *litp, int *sizep)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -2639,20 +2409,15 @@ md_atof (type, litp, sizep)
    endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
-    number_to_chars_bigendian (buf, val, n);
+  number_to_chars_bigendian (buf, val, n);
 }
 
 /* Align a section (I don't know why this is machine dependent).  */
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
 
@@ -2662,9 +2427,8 @@ md_section_align (seg, addr)
 /* We don't have any form of relaxing.  */
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
+			       asection *seg ATTRIBUTE_UNUSED)
 {
   abort ();
   return 0;
@@ -2673,10 +2437,9 @@ md_estimate_size_before_relax (fragp, seg)
 /* Convert a machine dependent frag.  We never generate these.  */
 
 void
-md_convert_frag (abfd, sec, fragp)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragp ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec ATTRIBUTE_UNUSED,
+		 fragS *fragp ATTRIBUTE_UNUSED)
 {
   abort ();
 }
@@ -2684,8 +2447,7 @@ md_convert_frag (abfd, sec, fragp)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -2696,9 +2458,7 @@ md_undefined_symbol (name)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec ATTRIBUTE_UNUSED;
+md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED)
 {
   return fixp->fx_frag->fr_address + fixp->fx_where;
 }
@@ -2713,21 +2473,17 @@ md_pcrel_from_section (fixp, sec)
    fixup.
 
    See gas/cgen.c for more sample code and explanations of what's
-   going on here ...
-*/
+   going on here.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg;
+md_apply_fix (fixS *fixP, valueT * valP, segT seg)
 {
   valueT value = * valP;
 
   if (fixP->fx_addsy != NULL)
     {
 #ifdef DEBUG
-      printf ("\nmd_apply_fix3: symbol %s at 0x%x (%s:%d) val=0x%x addend=0x%x\n",
+      printf ("\nmd_apply_fix: symbol %s at 0x%x (%s:%d) val=0x%x addend=0x%x\n",
 	      S_GET_NAME (fixP->fx_addsy),
 	      fixP->fx_frag->fr_address + fixP->fx_where,
 	      fixP->fx_file, fixP->fx_line,
@@ -2752,7 +2508,7 @@ md_apply_fix3 (fixP, valP, seg)
       operand = &i370_operands[opindex];
 
 #ifdef DEBUG
-      printf ("\nmd_apply_fix3: fixup operand %s at 0x%x in %s:%d addend=0x%x\n",
+      printf ("\nmd_apply_fix: fixup operand %s at 0x%x in %s:%d addend=0x%x\n",
 	      operand->name,
 	      fixP->fx_frag->fr_address + fixP->fx_where,
 	      fixP->fx_file, fixP->fx_line,
@@ -2787,13 +2543,6 @@ md_apply_fix3 (fixP, valP, seg)
 	 Why?  Because we are not expecting the compiler to generate
 	 any operands that need relocation.  Due to the 12-bit naturew of
 	 i370 addressing, this would be unusual.  */
-#if 0
-      if ((operand->flags & I370_OPERAND_RELATIVE) != 0
-          && operand->bits == 12
-          && operand->shift == 0)
-        fixP->fx_r_type = BFD_RELOC_I370_D12;
-      else
-#endif
         {
           char *sfile;
           unsigned int sline;
@@ -2819,7 +2568,7 @@ md_apply_fix3 (fixP, valP, seg)
       i370_elf_validate_fix (fixP, seg);
 #endif
 #ifdef DEBUG
-      printf ("md_apply_fix3: reloc case %d in segment  %s %s:%d\n",
+      printf ("md_apply_fix: reloc case %d in segment  %s %s:%d\n",
 	      fixP->fx_r_type, segment_name (seg), fixP->fx_file, fixP->fx_line);
       printf ("\tcurrent fixup value is 0x%x \n", value);
 #endif
@@ -2895,15 +2644,13 @@ md_apply_fix3 (fixP, valP, seg)
 /* Generate a reloc for a fixup.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
@@ -2924,3 +2671,42 @@ tc_gen_reloc (seg, fixp)
 
   return reloc;
 }
+
+/* The target specific pseudo-ops which we support.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  /* Pseudo-ops which must be overridden.  */
+  { "byte",     i370_byte,	0 },
+
+  { "dc",       i370_dc,	0 },
+  { "ds",       i370_ds,	0 },
+  { "rmode",    i370_rmode,	0 },
+  { "csect",    i370_csect,	0 },
+  { "dsect",    i370_dsect,	0 },
+
+  /* enable ebcdic strings e.g. for 3270 support */
+  { "ebcdic",   i370_ebcdic,	0 },
+
+#ifdef OBJ_ELF
+  { "long",     i370_elf_cons,	4 },
+  { "word",     i370_elf_cons,	4 },
+  { "short",    i370_elf_cons,	2 },
+  { "rdata",    i370_elf_rdata,	0 },
+  { "rodata",   i370_elf_rdata,	0 },
+  { "lcomm",    i370_elf_lcomm,	0 },
+#endif
+
+  /* This pseudo-op is used even when not generating XCOFF output.  */
+  { "tc",       i370_tc,	0 },
+
+  /* dump the literal pool */
+  { "ltorg",    i370_ltorg,	0 },
+
+  /* support the hlasm-style USING directive */
+  { "using",    i370_using,	0 },
+  { "drop",     i370_drop,	0 },
+
+  { NULL,       NULL,		0 }
+};
+
diff --git a/gas/config/tc-i370.h b/gas/config/tc-i370.h
index 81007ac97da2..4cd5f2f16a65 100644
--- a/gas/config/tc-i370.h
+++ b/gas/config/tc-i370.h
@@ -1,5 +1,5 @@
 /* tc-i370.h -- Header file for tc-i370.c.
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2005
    Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
@@ -17,29 +17,23 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_I370
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
 
 /* Set the endianness we are using.  Default to big endian.  */
 #ifndef TARGET_BYTES_BIG_ENDIAN
 #define TARGET_BYTES_BIG_ENDIAN 1
 #endif
 
-#ifndef BFD_ASSEMBLER
- #error I370 support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH (i370_arch ())
-extern enum bfd_architecture i370_arch PARAMS ((void));
+extern enum bfd_architecture i370_arch (void);
 
-/* Whether or not the target is big endian */
+/* Whether or not the target is big endian.  */
 extern int target_big_endian;
 
 /* The target BFD format.  */
@@ -51,17 +45,18 @@ extern int target_big_endian;
 /* $ is used to refer to the current location.  */
 /* #define DOLLAR_DOT */
 
-#define DIFF_EXPR_OK		/* foo-. gets turned into PC relative relocs */
+/* foo-. gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
 /* Call md_pcrel_from_section, not md_pcrel_from.  */
-#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define md_operand(x)
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5de6a55d2f51..be384bc99a76 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1,6 +1,6 @@
 /* i386.c -- Assemble code for the Intel 80386
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004
+   2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Intel 80386 machine specific gas.
    Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
@@ -33,6 +33,7 @@
 #include "dwarf2dbg.h"
 #include "dw2gencfi.h"
 #include "opcode/i386.h"
+#include "elf/x86-64.h"
 
 #ifndef REGISTER_WARNINGS
 #define REGISTER_WARNINGS 1
@@ -76,6 +77,10 @@ static void set_code_flag PARAMS ((int));
 static void set_16bit_gcc_code_flag PARAMS ((int));
 static void set_intel_syntax PARAMS ((int));
 static void set_cpu_arch PARAMS ((int));
+#ifdef TE_PE
+static void pe_directive_secrel PARAMS ((int));
+#endif
+static void signed_cons PARAMS ((int));
 static char *output_invalid PARAMS ((int c));
 static int i386_operand PARAMS ((char *operand_string));
 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
@@ -107,6 +112,9 @@ static void output_disp PARAMS ((fragS *insn_start_frag,
 #ifndef I386COFF
 static void s_bss PARAMS ((int));
 #endif
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+static void handle_large_common (int small ATTRIBUTE_UNUSED);
+#endif
 
 static const char *default_arch = DEFAULT_ARCH;
 
@@ -179,22 +187,34 @@ typedef struct _i386_insn i386_insn;
 
 /* List of chars besides those in app.c:symbol_chars that can start an
    operand.  Used to prevent the scrubber eating vital white-space.  */
+const char extra_symbol_chars[] = "*%-(["
 #ifdef LEX_AT
-const char extra_symbol_chars[] = "*%-(@[";
-#else
-const char extra_symbol_chars[] = "*%-([";
+	"@"
+#endif
+#ifdef LEX_QM
+	"?"
 #endif
+	;
 
 #if (defined (TE_I386AIX)				\
      || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))	\
+	 && !defined (TE_GNU)				\
 	 && !defined (TE_LINUX)				\
+ 	 && !defined (TE_NETWARE)			\
 	 && !defined (TE_FreeBSD)			\
 	 && !defined (TE_NetBSD)))
 /* This array holds the chars that always start a comment.  If the
-   pre-processor is disabled, these aren't very useful.  */
-const char comment_chars[] = "#/";
+   pre-processor is disabled, these aren't very useful.  The option
+   --divide will remove '/' from this list.  */
+const char *i386_comment_chars = "#/";
+#define SVR4_COMMENT_CHARS 1
 #define PREFIX_SEPARATOR '\\'
 
+#else
+const char *i386_comment_chars = "#";
+#define PREFIX_SEPARATOR '/'
+#endif
+
 /* This array holds the chars that only start a comment at the beginning of
    a line.  If the line seems to have the form '# 123 filename'
    .line and .file directives will appear in the pre-processed output.
@@ -203,16 +223,7 @@ const char comment_chars[] = "#/";
    #NO_APP at the beginning of its output.
    Also note that comments started like this one will always work if
    '/' isn't otherwise defined.  */
-const char line_comment_chars[] = "#";
-
-#else
-/* Putting '/' here makes it impossible to use the divide operator.
-   However, we need it for compatibility with SVR4 systems.  */
-const char comment_chars[] = "#";
-#define PREFIX_SEPARATOR '/'
-
-const char line_comment_chars[] = "/#";
-#endif
+const char line_comment_chars[] = "#/";
 
 const char line_separator_chars[] = ";";
 
@@ -276,6 +287,7 @@ enum flag_code {
 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
 
 static enum flag_code flag_code;
+static unsigned int object_64bit;
 static int use_rela_relocations = 0;
 
 /* The names used to print error messages.  */
@@ -306,6 +318,7 @@ static int quiet_warnings = 0;
 
 /* CPU name.  */
 static const char *cpu_arch_name = NULL;
+static const char *cpu_sub_arch_name = NULL;
 
 /* CPU feature flags.  */
 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
@@ -315,7 +328,7 @@ static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
 static unsigned int no_cond_jump_promotion = 0;
 
 /* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
-symbolS *GOT_symbol;
+static symbolS *GOT_symbol;
 
 /* The dwarf2 return column, adjusted for 32 or 64 bit.  */
 unsigned int x86_dwarf2_return_column;
@@ -408,14 +421,28 @@ static const arch_entry cpu_arch[] = {
   {"i286",	Cpu086|Cpu186|Cpu286 },
   {"i386",	Cpu086|Cpu186|Cpu286|Cpu386 },
   {"i486",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
-  {"i586",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
-  {"i686",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
-  {"pentium",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
-  {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
-  {"pentium4",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
-  {"k6",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
-  {"athlon",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
-  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
+  {"i586",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
+  {"i686",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
+  {"pentium",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
+  {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
+  {"pentiumii",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
+  {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
+  {"pentium4",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
+  {"prescott",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
+  {"k6",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
+  {"k6_2",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
+  {"athlon",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
+  {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
+  {"opteron",	Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
+  {".mmx",	CpuMMX },
+  {".sse",	CpuMMX|CpuMMX2|CpuSSE },
+  {".sse2",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
+  {".sse3",	CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
+  {".3dnow",	CpuMMX|Cpu3dnow },
+  {".3dnowa",	CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
+  {".padlock",	CpuPadLock },
+  {".pacifica",	CpuSVME },
+  {".svme",	CpuSVME },
   {NULL, 0 }
 };
 
@@ -434,6 +461,7 @@ const pseudo_typeS md_pseudo_table[] =
   {"dfloat", float_cons, 'd'},
   {"tfloat", float_cons, 'x'},
   {"value", cons, 2},
+  {"slong", signed_cons, 4},
   {"noopt", s_ignore, 0},
   {"optim", s_ignore, 0},
   {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
@@ -442,8 +470,16 @@ const pseudo_typeS md_pseudo_table[] =
   {"code64", set_code_flag, CODE_64BIT},
   {"intel_syntax", set_intel_syntax, 1},
   {"att_syntax", set_intel_syntax, 0},
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  {"largecomm", handle_large_common, 0},
+#else
   {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
   {"loc", dwarf2_directive_loc, 0},
+  {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
+#endif
+#ifdef TE_PE
+  {"secrel32", pe_directive_secrel, 0},
+#endif
   {0, 0, 0}
 };
 
@@ -694,55 +730,66 @@ add_prefix (prefix)
      unsigned int prefix;
 {
   int ret = 1;
-  int q;
+  unsigned int q;
 
   if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
       && flag_code == CODE_64BIT)
-    q = REX_PREFIX;
+    {
+      if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
+	  || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
+	      && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
+	ret = 0;
+      q = REX_PREFIX;
+    }
   else
-    switch (prefix)
-      {
-      default:
-	abort ();
-
-      case CS_PREFIX_OPCODE:
-      case DS_PREFIX_OPCODE:
-      case ES_PREFIX_OPCODE:
-      case FS_PREFIX_OPCODE:
-      case GS_PREFIX_OPCODE:
-      case SS_PREFIX_OPCODE:
-	q = SEG_PREFIX;
-	break;
+    {
+      switch (prefix)
+	{
+	default:
+	  abort ();
+
+	case CS_PREFIX_OPCODE:
+	case DS_PREFIX_OPCODE:
+	case ES_PREFIX_OPCODE:
+	case FS_PREFIX_OPCODE:
+	case GS_PREFIX_OPCODE:
+	case SS_PREFIX_OPCODE:
+	  q = SEG_PREFIX;
+	  break;
 
-      case REPNE_PREFIX_OPCODE:
-      case REPE_PREFIX_OPCODE:
-	ret = 2;
-	/* fall thru */
-      case LOCK_PREFIX_OPCODE:
-	q = LOCKREP_PREFIX;
-	break;
+	case REPNE_PREFIX_OPCODE:
+	case REPE_PREFIX_OPCODE:
+	  ret = 2;
+	  /* fall thru */
+	case LOCK_PREFIX_OPCODE:
+	  q = LOCKREP_PREFIX;
+	  break;
 
-      case FWAIT_OPCODE:
-	q = WAIT_PREFIX;
-	break;
+	case FWAIT_OPCODE:
+	  q = WAIT_PREFIX;
+	  break;
 
-      case ADDR_PREFIX_OPCODE:
-	q = ADDR_PREFIX;
-	break;
+	case ADDR_PREFIX_OPCODE:
+	  q = ADDR_PREFIX;
+	  break;
 
-      case DATA_PREFIX_OPCODE:
-	q = DATA_PREFIX;
-	break;
-      }
+	case DATA_PREFIX_OPCODE:
+	  q = DATA_PREFIX;
+	  break;
+	}
+      if (i.prefix[q] != 0)
+	ret = 0;
+    }
 
-  if (i.prefix[q] != 0)
+  if (ret)
     {
-      as_bad (_("same type of prefix used twice"));
-      return 0;
+      if (!i.prefix[q])
+	++i.prefixes;
+      i.prefix[q] |= prefix;
     }
+  else
+    as_bad (_("same type of prefix used twice"));
 
-  i.prefixes += 1;
-  i.prefix[q] = prefix;
   return ret;
 }
 
@@ -771,7 +818,7 @@ set_16bit_gcc_code_flag (new_code_flag)
   flag_code = new_code_flag;
   cpu_arch_flags &= ~(Cpu64 | CpuNo64);
   cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
-  stackop_size = 'l';
+  stackop_size = LONG_MNEM_SUFFIX;
 }
 
 static void
@@ -804,6 +851,9 @@ set_intel_syntax (syntax_flag)
 		       && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
   else
     allow_naked_reg = (ask_naked_reg < 0);
+
+  identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
+  identifier_chars['$'] = intel_syntax ? '$' : 0;
 }
 
 static void
@@ -822,10 +872,22 @@ set_cpu_arch (dummy)
 	{
 	  if (strcmp (string, cpu_arch[i].name) == 0)
 	    {
-	      cpu_arch_name = cpu_arch[i].name;
-	      cpu_arch_flags = (cpu_arch[i].flags
-				| (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
-	      break;
+	      if (*string != '.')
+		{
+		  cpu_arch_name = cpu_arch[i].name;
+		  cpu_sub_arch_name = NULL;
+		  cpu_arch_flags = (cpu_arch[i].flags
+				    | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
+		  break;
+		}
+	      if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
+		{
+		  cpu_sub_arch_name = cpu_arch[i].name;
+		  cpu_arch_flags |= cpu_arch[i].flags;
+		}
+	      *input_line_pointer = e;
+	      demand_empty_rest_of_line ();
+	      return;
 	    }
 	}
       if (!cpu_arch[i].name)
@@ -966,7 +1028,12 @@ md_begin ()
 #ifdef LEX_AT
     identifier_chars['@'] = '@';
 #endif
+#ifdef LEX_QM
+    identifier_chars['?'] = '?';
+    operand_chars['?'] = '?';
+#endif
     digit_chars['-'] = '-';
+    mnemonic_chars['-'] = '-';
     identifier_chars['_'] = '_';
     identifier_chars['.'] = '.';
 
@@ -975,7 +1042,7 @@ md_begin ()
   }
 
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+  if (IS_ELF)
     {
       record_alignment (text_section, 2);
       record_alignment (data_section, 2);
@@ -1102,13 +1169,12 @@ ps (s)
 	   segment_name (S_GET_SEGMENT (s)));
 }
 
-struct type_name
+static struct type_name
   {
     unsigned int mask;
     char *tname;
   }
-
-static const type_names[] =
+const type_names[] =
 {
   { Reg8, "r8" },
   { Reg16, "r16" },
@@ -1158,34 +1224,80 @@ pt (t)
 
 #endif /* DEBUG386 */
 
-static bfd_reloc_code_real_type reloc
-  PARAMS ((int, int, int, bfd_reloc_code_real_type));
-
 static bfd_reloc_code_real_type
-reloc (size, pcrel, sign, other)
-     int size;
-     int pcrel;
-     int sign;
-     bfd_reloc_code_real_type other;
+reloc (unsigned int size,
+     int pcrel,
+     int sign,
+     bfd_reloc_code_real_type other)
 {
   if (other != NO_RELOC)
-    return other;
+    {
+      reloc_howto_type *reloc;
+
+      if (size == 8)
+	switch (other)
+	  {
+	    case BFD_RELOC_X86_64_GOT32:
+	      return BFD_RELOC_X86_64_GOT64;
+	      break;
+	    case BFD_RELOC_X86_64_PLTOFF64:
+	      return BFD_RELOC_X86_64_PLTOFF64;
+	      break;
+	    case BFD_RELOC_X86_64_GOTPC32:
+	      other = BFD_RELOC_X86_64_GOTPC64;
+	      break;
+	    case BFD_RELOC_X86_64_GOTPCREL:
+	      other = BFD_RELOC_X86_64_GOTPCREL64;
+	      break;
+	    case BFD_RELOC_X86_64_TPOFF32:
+	      other = BFD_RELOC_X86_64_TPOFF64;
+	      break;
+	    case BFD_RELOC_X86_64_DTPOFF32:
+	      other = BFD_RELOC_X86_64_DTPOFF64;
+	      break;
+	    default:
+	      break;
+	  }
+
+      /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
+      if (size == 4 && flag_code != CODE_64BIT)
+	sign = -1;
+
+      reloc = bfd_reloc_type_lookup (stdoutput, other);
+      if (!reloc)
+	as_bad (_("unknown relocation (%u)"), other);
+      else if (size != bfd_get_reloc_size (reloc))
+	as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
+		bfd_get_reloc_size (reloc),
+		size);
+      else if (pcrel && !reloc->pc_relative)
+	as_bad (_("non-pc-relative relocation for pc-relative field"));
+      else if ((reloc->complain_on_overflow == complain_overflow_signed
+		&& !sign)
+	       || (reloc->complain_on_overflow == complain_overflow_unsigned
+		&& sign > 0))
+	as_bad (_("relocated field and relocation type differ in signedness"));
+      else
+	return other;
+      return NO_RELOC;
+    }
 
   if (pcrel)
     {
       if (!sign)
-	as_bad (_("There are no unsigned pc-relative relocations"));
+	as_bad (_("there are no unsigned pc-relative relocations"));
       switch (size)
 	{
 	case 1: return BFD_RELOC_8_PCREL;
 	case 2: return BFD_RELOC_16_PCREL;
 	case 4: return BFD_RELOC_32_PCREL;
+	case 8: return BFD_RELOC_64_PCREL;
 	}
-      as_bad (_("can not do %d byte pc-relative relocation"), size);
+      as_bad (_("cannot do %u byte pc-relative relocation"), size);
     }
   else
     {
-      if (sign)
+      if (sign > 0)
 	switch (size)
 	  {
 	  case 4: return BFD_RELOC_X86_64_32S;
@@ -1198,8 +1310,8 @@ reloc (size, pcrel, sign, other)
 	  case 4: return BFD_RELOC_32;
 	  case 8: return BFD_RELOC_64;
 	  }
-      as_bad (_("can not do %s %d byte relocation"),
-	      sign ? "signed" : "unsigned", size);
+      as_bad (_("cannot do %s %u byte relocation"),
+	      sign > 0 ? "signed" : "unsigned", size);
     }
 
   abort ();
@@ -1216,7 +1328,7 @@ tc_i386_fix_adjustable (fixP)
      fixS *fixP ATTRIBUTE_UNUSED;
 {
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-  if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
+  if (!IS_ELF)
     return 1;
 
   /* Don't adjust pc-relative references to merge sections in 64-bit
@@ -1244,14 +1356,21 @@ tc_i386_fix_adjustable (fixP)
       || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
       || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
       || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
+      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
+      || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
       || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
       || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
       || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
       || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
       || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
+      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
       || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
       || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
+      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
+      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
+      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
+      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
       || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 0;
@@ -1265,13 +1384,54 @@ static int
 intel_float_operand (mnemonic)
      const char *mnemonic;
 {
-  if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
-    return 2;
-
-  if (mnemonic[0] == 'f')
-    return 1;
+  /* Note that the value returned is meaningful only for opcodes with (memory)
+     operands, hence the code here is free to improperly handle opcodes that
+     have no operands (for better performance and smaller code). */
+
+  if (mnemonic[0] != 'f')
+    return 0; /* non-math */
+
+  switch (mnemonic[1])
+    {
+    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
+       the fs segment override prefix not currently handled because no
+       call path can make opcodes without operands get here */
+    case 'i':
+      return 2 /* integer op */;
+    case 'l':
+      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
+	return 3; /* fldcw/fldenv */
+      break;
+    case 'n':
+      if (mnemonic[2] != 'o' /* fnop */)
+	return 3; /* non-waiting control op */
+      break;
+    case 'r':
+      if (mnemonic[2] == 's')
+	return 3; /* frstor/frstpm */
+      break;
+    case 's':
+      if (mnemonic[2] == 'a')
+	return 3; /* fsave */
+      if (mnemonic[2] == 't')
+	{
+	  switch (mnemonic[3])
+	    {
+	    case 'c': /* fstcw */
+	    case 'd': /* fstdw */
+	    case 'e': /* fstenv */
+	    case 's': /* fsts[gw] */
+	      return 3;
+	    }
+	}
+      break;
+    case 'x':
+      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
+	return 0; /* fxsave/fxrstor are not really math ops */
+      break;
+    }
 
-  return 0;
+  return 1;
 }
 
 /* This is the guts of the machine-dependent assembler.  LINE points to a
@@ -1316,13 +1476,18 @@ md_assemble (line)
      have two immediate operands.  */
   if (intel_syntax && i.operands > 1
       && (strcmp (mnemonic, "bound") != 0)
+      && (strcmp (mnemonic, "invlpga") != 0)
       && !((i.types[0] & Imm) && (i.types[1] & Imm)))
     swap_operands ();
 
   if (i.imm_operands)
     optimize_imm ();
 
-  if (i.disp_operands)
+  /* Don't optimize displacement for movabs since it only takes 64bit
+     displacement.  */
+  if (i.disp_operands
+      && (flag_code != CODE_64BIT
+	  || strcmp (mnemonic, "movabs") != 0))
     optimize_disp ();
 
   /* Next, we find a template that matches the given insn,
@@ -1343,7 +1508,20 @@ md_assemble (line)
 	 "word ptr" or "byte ptr" on the source operand, but we'll use
 	 the suffix later to choose the destination register.  */
       if ((i.tm.base_opcode & ~9) == 0x0fb6)
-	i.suffix = 0;
+	{
+	  if (i.reg_operands < 2
+	      && !i.suffix
+	      && (~i.tm.opcode_modifier
+		  & (No_bSuf
+		     | No_wSuf
+		     | No_lSuf
+		     | No_sSuf
+		     | No_xSuf
+		     | No_qSuf)))
+	    as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+
+	  i.suffix = 0;
+	}
     }
 
   if (i.tm.opcode_modifier & FWait)
@@ -1462,7 +1640,7 @@ md_assemble (line)
 	    {
 	      /* In case it is "hi" register, give up.  */
 	      if (i.op[x].regs->reg_num > 3)
-		as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
+		as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
 			i.op[x].regs->reg_name);
 
 	      /* Otherwise it is equivalent to the extended register.
@@ -1489,6 +1667,8 @@ parse_insn (line, mnemonic)
   char *l = line;
   char *token_start = l;
   char *mnem_p;
+  int supported;
+  const template *t;
 
   /* Non-zero if we found a prefix only acceptable with string insns.  */
   const char *expecting_string_instruction = NULL;
@@ -1508,8 +1688,9 @@ parse_insn (line, mnemonic)
 	}
       if (!is_space_char (*l)
 	  && *l != END_OF_INSN
-	  && *l != PREFIX_SEPARATOR
-	  && *l != ',')
+	  && (intel_syntax
+	      || (*l != PREFIX_SEPARATOR
+		  && *l != ',')))
 	{
 	  as_bad (_("invalid character %s in mnemonic"),
 		  output_invalid (*l));
@@ -1517,7 +1698,7 @@ parse_insn (line, mnemonic)
 	}
       if (token_start == l)
 	{
-	  if (*l == PREFIX_SEPARATOR)
+	  if (!intel_syntax && *l == PREFIX_SEPARATOR)
 	    as_bad (_("expecting prefix; got nothing"));
 	  else
 	    as_bad (_("expecting mnemonic; got nothing"));
@@ -1532,6 +1713,15 @@ parse_insn (line, mnemonic)
 	  && current_templates
 	  && (current_templates->start->opcode_modifier & IsPrefix))
 	{
+	  if (current_templates->start->cpu_flags
+	      & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
+	    {
+	      as_bad ((flag_code != CODE_64BIT
+		       ? _("`%s' is only supported in 64-bit mode")
+		       : _("`%s' is not supported in 64-bit mode")),
+		      current_templates->start->name);
+	      return NULL;
+	    }
 	  /* If we are in 16-bit mode, do not allow addr16 or data16.
 	     Similarly, in 32-bit mode, do not allow addr32 or data32.  */
 	  if ((current_templates->start->opcode_modifier & (Size16 | Size32))
@@ -1565,6 +1755,9 @@ parse_insn (line, mnemonic)
       switch (mnem_p[-1])
 	{
 	case WORD_MNEM_SUFFIX:
+	  if (intel_syntax && (intel_float_operand (mnemonic) & 2))
+	    i.suffix = SHORT_MNEM_SUFFIX;
+	  else
 	case BYTE_MNEM_SUFFIX:
 	case QWORD_MNEM_SUFFIX:
 	  i.suffix = mnem_p[-1];
@@ -1585,7 +1778,7 @@ parse_insn (line, mnemonic)
 	case 'd':
 	  if (intel_syntax)
 	    {
-	      if (intel_float_operand (mnemonic))
+	      if (intel_float_operand (mnemonic) == 1)
 		i.suffix = SHORT_MNEM_SUFFIX;
 	      else
 		i.suffix = LONG_MNEM_SUFFIX;
@@ -1634,11 +1827,29 @@ parse_insn (line, mnemonic)
     }
 
   /* Check if instruction is supported on specified architecture.  */
-  if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
-      & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
+  supported = 0;
+  for (t = current_templates->start; t < current_templates->end; ++t)
     {
-      as_warn (_("`%s' is not supported on `%s'"),
-	       current_templates->start->name, cpu_arch_name);
+      if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
+	    & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
+	  supported |= 1;
+      if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
+	  supported |= 2;
+    }
+  if (!(supported & 2))
+    {
+      as_bad (flag_code == CODE_64BIT
+	      ? _("`%s' is not supported in 64-bit mode")
+	      : _("`%s' is only supported in 64-bit mode"),
+	      current_templates->start->name);
+      return NULL;
+    }
+  if (!(supported & 1))
+    {
+      as_warn (_("`%s' is not supported on `%s%s'"),
+	       current_templates->start->name,
+	       cpu_arch_name,
+	       cpu_sub_arch_name ? cpu_sub_arch_name : "");
     }
   else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
     {
@@ -1646,12 +1857,24 @@ parse_insn (line, mnemonic)
     }
 
   /* Check for rep/repne without a string instruction.  */
-  if (expecting_string_instruction
-      && !(current_templates->start->opcode_modifier & IsString))
+  if (expecting_string_instruction)
     {
-      as_bad (_("expecting string instruction after `%s'"),
-	      expecting_string_instruction);
-      return NULL;
+      static templates override;
+
+      for (t = current_templates->start; t < current_templates->end; ++t)
+	if (t->opcode_modifier & IsString)
+	  break;
+      if (t >= current_templates->end)
+	{
+	  as_bad (_("expecting string instruction after `%s'"),
+	        expecting_string_instruction);
+	  return NULL;
+	}
+      for (override.start = t; t < current_templates->end; ++t)
+	if (!(t->opcode_modifier & IsString))
+	  break;
+      override.end = t;
+      current_templates = &override;
     }
 
   return l;
@@ -1901,24 +2124,36 @@ optimize_imm ()
 
 	    /* Symbols and expressions.  */
 	  default:
-	    /* Convert symbolic operand to proper sizes for matching.  */
-	    switch (guess_suffix)
-	      {
-	      case QWORD_MNEM_SUFFIX:
-		i.types[op] = Imm64 | Imm32S;
-		break;
-	      case LONG_MNEM_SUFFIX:
-		i.types[op] = Imm32 | Imm64;
-		break;
-	      case WORD_MNEM_SUFFIX:
-		i.types[op] = Imm16 | Imm32 | Imm64;
-		break;
-		break;
-	      case BYTE_MNEM_SUFFIX:
-		i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
-		break;
-		break;
-	      }
+	    /* Convert symbolic operand to proper sizes for matching, but don't
+	       prevent matching a set of insns that only supports sizes other
+	       than those matching the insn suffix.  */
+	    {
+	      unsigned int mask, allowed = 0;
+	      const template *t;
+
+	      for (t = current_templates->start; t < current_templates->end; ++t)
+	        allowed |= t->operand_types[op];
+	      switch (guess_suffix)
+		{
+		case QWORD_MNEM_SUFFIX:
+		  mask = Imm64 | Imm32S;
+		  break;
+		case LONG_MNEM_SUFFIX:
+		  mask = Imm32;
+		  break;
+		case WORD_MNEM_SUFFIX:
+		  mask = Imm16;
+		  break;
+		case BYTE_MNEM_SUFFIX:
+		  mask = Imm8;
+		  break;
+		default:
+		  mask = 0;
+		  break;
+		}
+		if (mask & allowed)
+		  i.types[op] &= mask;
+	    }
 	    break;
 	  }
       }
@@ -1931,37 +2166,61 @@ optimize_disp ()
   int op;
 
   for (op = i.operands; --op >= 0;)
-    if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
+    if (i.types[op] & Disp)
       {
-	offsetT disp = i.op[op].disps->X_add_number;
-
-	if (i.types[op] & Disp16)
+	if (i.op[op].disps->X_op == O_constant)
 	  {
-	    /* We know this operand is at most 16 bits, so
-	       convert to a signed 16 bit number before trying
-	       to see whether it will fit in an even smaller
-	       size.  */
+	    offsetT disp = i.op[op].disps->X_add_number;
 
-	    disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
-	  }
-	else if (i.types[op] & Disp32)
-	  {
-	    /* We know this operand is at most 32 bits, so convert to a
-	       signed 32 bit number before trying to see whether it will
-	       fit in an even smaller size.  */
-	    disp &= (((offsetT) 2 << 31) - 1);
-	    disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
+	    if ((i.types[op] & Disp16)
+		&& (disp & ~(offsetT) 0xffff) == 0)
+	      {
+		/* If this operand is at most 16 bits, convert
+		   to a signed 16 bit number and don't use 64bit
+		   displacement.  */
+		disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
+		i.types[op] &= ~Disp64;
+	      }
+	    if ((i.types[op] & Disp32)
+		&& (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
+	      {
+		/* If this operand is at most 32 bits, convert
+		   to a signed 32 bit number and don't use 64bit
+		   displacement.  */
+		disp &= (((offsetT) 2 << 31) - 1);
+		disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
+		i.types[op] &= ~Disp64;
+	      }
+	    if (!disp && (i.types[op] & BaseIndex))
+	      {
+		i.types[op] &= ~Disp;
+		i.op[op].disps = 0;
+		i.disp_operands--;
+	      }
+	    else if (flag_code == CODE_64BIT)
+	      {
+		if (fits_in_signed_long (disp))
+		  {
+		    i.types[op] &= ~Disp64;
+		    i.types[op] |= Disp32S;
+		  }
+		if (fits_in_unsigned_long (disp))
+		  i.types[op] |= Disp32;
+	      }
+	    if ((i.types[op] & (Disp32 | Disp32S | Disp16))
+		&& fits_in_signed_byte (disp))
+	      i.types[op] |= Disp8;
 	  }
-	if (flag_code == CODE_64BIT)
+	else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
+		 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
 	  {
-	    if (fits_in_signed_long (disp))
-	      i.types[op] |= Disp32S;
-	    if (fits_in_unsigned_long (disp))
-	      i.types[op] |= Disp32;
+	    fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
+			 i.op[op].disps, 0, i.reloc[op]);
+	    i.types[op] &= ~Disp;
 	  }
-	if ((i.types[op] & (Disp32 | Disp32S | Disp16))
-	    && fits_in_signed_byte (disp))
-	  i.types[op] |= Disp8;
+ 	else
+	  /* We only support 64bit displacement on constants.  */
+	  i.types[op] &= ~Disp64;
       }
 }
 
@@ -2004,9 +2263,7 @@ match_template ()
 			      : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
 				 ? No_xSuf : 0))))));
 
-  for (t = current_templates->start;
-       t < current_templates->end;
-       t++)
+  for (t = current_templates->start; t < current_templates->end; t++)
     {
       /* Must have right number of operands.  */
       if (i.operands != t->operands)
@@ -2015,11 +2272,20 @@ match_template ()
       /* Check the suffix, except for some instructions in intel mode.  */
       if ((t->opcode_modifier & suffix_check)
 	  && !(intel_syntax
-	       && (t->opcode_modifier & IgnoreSize))
-	  && !(intel_syntax
-	       && t->base_opcode == 0xd9
-	       && (t->extension_opcode == 5	     /* 0xd9,5 "fldcw"  */
-		   || t->extension_opcode == 7)))  /* 0xd9,7 "f{n}stcw"  */
+	       && (t->opcode_modifier & IgnoreSize)))
+	continue;
+
+      /* In general, don't allow 64-bit operands in 32-bit mode.  */
+      if (i.suffix == QWORD_MNEM_SUFFIX
+	  && flag_code != CODE_64BIT
+	  && (intel_syntax
+	      ? (!(t->opcode_modifier & IgnoreSize)
+		 && !intel_float_operand (t->name))
+	      : intel_float_operand (t->name) != 2)
+	  && (!(t->operand_types[0] & (RegMMX | RegXMM))
+	      || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
+	  && (t->base_opcode != 0x0fc7
+	      || t->extension_opcode != 1 /* cmpxchg8b */))
 	continue;
 
       /* Do not verify operands when there are none.  */
@@ -2043,10 +2309,15 @@ match_template ()
 	  overlap1 = i.types[1] & t->operand_types[1];
 	  if (!MATCH (overlap0, i.types[0], t->operand_types[0])
 	      || !MATCH (overlap1, i.types[1], t->operand_types[1])
-	      || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
-					     t->operand_types[0],
-					     overlap1, i.types[1],
-					     t->operand_types[1]))
+	      /* monitor in SSE3 is a very special case.  The first
+		 register and the second register may have differnet
+		 sizes.  */
+	      || !((t->base_opcode == 0x0f01
+		    && t->extension_opcode == 0xc8)
+		   || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
+						 t->operand_types[0],
+						 overlap1, i.types[1],
+						 t->operand_types[1])))
 	    {
 	      /* Check if other direction is valid ...  */
 	      if ((t->opcode_modifier & (D | FloatD)) == 0)
@@ -2173,7 +2444,7 @@ check_string ()
 }
 
 static int
-process_suffix ()
+process_suffix (void)
 {
   /* If matched instruction specifies an explicit instruction mnemonic
      suffix, use it.  */
@@ -2196,6 +2467,7 @@ process_suffix ()
 	     Destination register type is more significant than source
 	     register type.  */
 	  int op;
+
 	  for (op = i.operands; --op >= 0;)
 	    if ((i.types[op] & Reg)
 		&& !(i.tm.operand_types[op] & InOutPortReg))
@@ -2233,20 +2505,72 @@ process_suffix ()
       else
 	abort ();
     }
-  else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
+  else if ((i.tm.opcode_modifier & DefaultSize)
+	   && !i.suffix
+	   /* exclude fldenv/frstor/fsave/fstenv */
+	   && (i.tm.opcode_modifier & No_sSuf))
     {
       i.suffix = stackop_size;
     }
+  else if (intel_syntax
+	   && !i.suffix
+	   && ((i.tm.operand_types[0] & JumpAbsolute)
+	    || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
+	    || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
+		&& i.tm.extension_opcode <= 3)))
+    {
+      switch (flag_code)
+	{
+	case CODE_64BIT:
+	  if (!(i.tm.opcode_modifier & No_qSuf))
+	    {
+	      i.suffix = QWORD_MNEM_SUFFIX;
+	      break;
+	    }
+	case CODE_32BIT:
+	  if (!(i.tm.opcode_modifier & No_lSuf))
+	    i.suffix = LONG_MNEM_SUFFIX;
+	  break;
+	case CODE_16BIT:
+	  if (!(i.tm.opcode_modifier & No_wSuf))
+	    i.suffix = WORD_MNEM_SUFFIX;
+	  break;
+	}
+    }
 
-  /* Change the opcode based on the operand size given by i.suffix;
-     We need not change things for byte insns.  */
-
-  if (!i.suffix && (i.tm.opcode_modifier & W))
+  if (!i.suffix)
     {
-      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
-      return 0;
+      if (!intel_syntax)
+	{
+	  if (i.tm.opcode_modifier & W)
+	    {
+	      as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
+	      return 0;
+	    }
+	}
+      else
+	{
+	  unsigned int suffixes = ~i.tm.opcode_modifier
+				  & (No_bSuf
+				     | No_wSuf
+				     | No_lSuf
+				     | No_sSuf
+				     | No_xSuf
+				     | No_qSuf);
+
+	  if ((i.tm.opcode_modifier & W)
+	      || ((suffixes & (suffixes - 1))
+		  && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
+	    {
+	      as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
+	      return 0;
+	    }
+	}
     }
 
+  /* Change the opcode based on the operand size given by i.suffix;
+     We don't need to change things for byte insns.  */
+
   if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
     {
       /* It's not a byte, select word/dword operation.  */
@@ -2261,13 +2585,25 @@ process_suffix ()
       /* Now select between word & dword operations via the operand
 	 size prefix, except for instructions that will ignore this
 	 prefix anyway.  */
-      if (i.suffix != QWORD_MNEM_SUFFIX
-	  && !(i.tm.opcode_modifier & IgnoreSize)
-	  && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
-	      || (flag_code == CODE_64BIT
-		  && (i.tm.opcode_modifier & JumpByte))))
+      if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
+	{
+	  /* monitor in SSE3 is a very special case. The default size
+	     of AX is the size of mode. The address size override
+	     prefix will change the size of AX.  */
+	  if (i.op->regs[0].reg_type &
+	      (flag_code == CODE_32BIT ? Reg16 : Reg32))
+	    if (!add_prefix (ADDR_PREFIX_OPCODE))
+	      return 0;
+	}
+      else if (i.suffix != QWORD_MNEM_SUFFIX
+	       && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
+	       && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
+	       && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
+		   || (flag_code == CODE_64BIT
+		       && (i.tm.opcode_modifier & JumpByte))))
 	{
 	  unsigned int prefix = DATA_PREFIX_OPCODE;
+
 	  if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
 	    prefix = ADDR_PREFIX_OPCODE;
 
@@ -2283,19 +2619,18 @@ process_suffix ()
 
       /* Size floating point instruction.  */
       if (i.suffix == LONG_MNEM_SUFFIX)
-	{
-	  if (i.tm.opcode_modifier & FloatMF)
-	    i.tm.base_opcode ^= 4;
-	}
+	if (i.tm.opcode_modifier & FloatMF)
+	  i.tm.base_opcode ^= 4;
     }
 
   return 1;
 }
 
 static int
-check_byte_reg ()
+check_byte_reg (void)
 {
   int op;
+
   for (op = i.operands; --op >= 0;)
     {
       /* If this is an eight bit register, it's OK.  If it's the 16 or
@@ -2313,14 +2648,7 @@ check_byte_reg ()
 	      || i.tm.base_opcode == 0xfbf))
 	continue;
 
-      if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
-#if 0
-	  /* Check that the template allows eight bit regs.  This
-	     kills insns such as `orb $1,%edx', which maybe should be
-	     allowed.  */
-	  && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
-#endif
-	  )
+      if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
 	{
 	  /* Prohibit these changes in the 64bit mode, since the
 	     lowering is more complicated.  */
@@ -2490,7 +2818,7 @@ finalize_imm ()
   unsigned int overlap0, overlap1, overlap2;
 
   overlap0 = i.types[0] & i.tm.operand_types[0];
-  if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
+  if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
       && overlap0 != Imm8 && overlap0 != Imm8S
       && overlap0 != Imm16 && overlap0 != Imm32S
       && overlap0 != Imm32 && overlap0 != Imm64)
@@ -2523,7 +2851,7 @@ finalize_imm ()
   i.types[0] = overlap0;
 
   overlap1 = i.types[1] & i.tm.operand_types[1];
-  if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
+  if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
       && overlap1 != Imm8 && overlap1 != Imm8S
       && overlap1 != Imm16 && overlap1 != Imm32S
       && overlap1 != Imm32 && overlap1 != Imm64)
@@ -2641,8 +2969,10 @@ process_operands ()
       default_seg = &ds;
     }
 
-  if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
-    as_warn (_("segment override on `lea' is ineffectual"));
+  if ((i.tm.base_opcode == 0x8d /* lea */
+       || (i.tm.cpu_flags & CpuSVME))
+      && i.seg[0] && !quiet_warnings)
+    as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
 
   /* If a segment was explicitly specified, and the specified segment
      is not the default, use an opcode prefix to select it.  If we
@@ -2699,6 +3029,13 @@ build_modrm_byte ()
 	  if ((i.op[source].regs->reg_flags & RegRex) != 0)
 	    i.rex |= REX_EXTX;
 	}
+      if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
+	{
+	  if (!((i.types[0] | i.types[1]) & Control))
+	    abort ();
+	  i.rex &= ~(REX_EXTX | REX_EXTZ);
+	  add_prefix (LOCK_PREFIX_OPCODE);
+	}
     }
   else
     {			/* If it's not 2 reg operands...  */
@@ -2719,21 +3056,7 @@ build_modrm_byte ()
 	      if (i.index_reg == 0)
 		{
 		  /* Operand is just <disp>  */
-		  if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
-		      && (flag_code != CODE_64BIT))
-		    {
-		      i.rm.regmem = NO_BASE_REGISTER_16;
-		      i.types[op] &= ~Disp;
-		      i.types[op] |= Disp16;
-		    }
-		  else if (flag_code != CODE_64BIT
-			   || (i.prefix[ADDR_PREFIX] != 0))
-		    {
-		      i.rm.regmem = NO_BASE_REGISTER;
-		      i.types[op] &= ~Disp;
-		      i.types[op] |= Disp32;
-		    }
-		  else
+		  if (flag_code == CODE_64BIT)
 		    {
 		      /* 64bit mode overwrites the 32bit absolute
 			 addressing by RIP relative addressing and
@@ -2742,8 +3065,17 @@ build_modrm_byte ()
 		      i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
 		      i.sib.base = NO_BASE_REGISTER;
 		      i.sib.index = NO_INDEX_REGISTER;
-		      i.types[op] &= ~Disp;
-		      i.types[op] |= Disp32S;
+		      i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
+		    }
+		  else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
+		    {
+		      i.rm.regmem = NO_BASE_REGISTER_16;
+		      i.types[op] = Disp16;
+		    }
+		  else
+		    {
+		      i.rm.regmem = NO_BASE_REGISTER;
+		      i.types[op] = Disp32;
 		    }
 		}
 	      else /* !i.base_reg && i.index_reg  */
@@ -2765,9 +3097,11 @@ build_modrm_byte ()
 	  else if (i.base_reg->reg_type == BaseIndex)
 	    {
 	      i.rm.regmem = NO_BASE_REGISTER;
-	      i.types[op] &= ~Disp;
+	      i.types[op] &= ~ Disp;
 	      i.types[op] |= Disp32S;
 	      i.flags[op] = Operand_PCrel;
+	      if (! i.disp_operands)
+		fake_zero_displacement = 1;
 	    }
 	  else if (i.base_reg->reg_type & Reg16)
 	    {
@@ -2803,12 +3137,8 @@ build_modrm_byte ()
 	    {
 	      if (flag_code == CODE_64BIT
 		  && (i.types[op] & Disp))
-		{
-		  if (i.types[op] & Disp8)
-		    i.types[op] = Disp8 | Disp32S;
-		  else
-		    i.types[op] = Disp32S;
-		}
+		i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
+
 	      i.rm.regmem = i.base_reg->reg_num;
 	      if ((i.base_reg->reg_flags & RegRex) != 0)
 		i.rex |= REX_EXTZ;
@@ -2850,7 +3180,13 @@ build_modrm_byte ()
 		  if ((i.index_reg->reg_flags & RegRex) != 0)
 		    i.rex |= REX_EXTY;
 		}
-	      i.rm.mode = mode_from_disp_size (i.types[op]);
+
+	      if (i.disp_operands
+		  && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
+		      || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
+		i.rm.mode = 0;
+	      else
+		i.rm.mode = mode_from_disp_size (i.types[op]);
 	    }
 
 	  if (fake_zero_displacement)
@@ -3150,24 +3486,32 @@ output_insn ()
       /* Output normal instructions here.  */
       char *p;
       unsigned char *q;
+      unsigned int prefix;
 
-      /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions
-	 have 3 bytes.  We may use one more higher byte to specify a prefix
-	 the instruction requires.  */
-      if ((i.tm.cpu_flags & CpuPadLock) != 0
-	  && (i.tm.base_opcode & 0xff000000) != 0)
-        {
-	  unsigned int prefix;
-	  prefix = (i.tm.base_opcode >> 24) & 0xff;
-
-	  if (prefix != REPE_PREFIX_OPCODE
-	      || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
+      /* All opcodes on i386 have either 1 or 2 bytes.  Merom New
+	 Instructions have 3 bytes.  We may use one more higher byte
+	 to specify a prefix the instruction requires.  */
+      if ((i.tm.cpu_flags & CpuMNI) != 0)
+	{
+	  if (i.tm.base_opcode & 0xff000000)
+	    {
+	      prefix = (i.tm.base_opcode >> 24) & 0xff;
+	      goto check_prefix;
+	    }
+	}
+      else if ((i.tm.base_opcode & 0xff0000) != 0)
+	{
+	  prefix = (i.tm.base_opcode >> 16) & 0xff;
+	  if ((i.tm.cpu_flags & CpuPadLock) != 0)
+	    {
+check_prefix:
+	      if (prefix != REPE_PREFIX_OPCODE
+		  || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
+		add_prefix (prefix);
+	    }
+	  else
 	    add_prefix (prefix);
 	}
-      else
-	if ((i.tm.cpu_flags & CpuPadLock) == 0
-	    && (i.tm.base_opcode & 0xff0000) != 0)
-	  add_prefix ((i.tm.base_opcode >> 16) & 0xff);
 
       /* The prefix bytes.  */
       for (q = i.prefix;
@@ -3188,7 +3532,7 @@ output_insn ()
 	}
       else
 	{
-	  if ((i.tm.cpu_flags & CpuPadLock) != 0)
+	  if ((i.tm.cpu_flags & CpuMNI) != 0)
 	    {
 	      p = frag_more (3);
 	      *p++ = (i.tm.base_opcode >> 16) & 0xff;
@@ -3237,7 +3581,7 @@ output_insn ()
 #ifdef DEBUG386
   if (flag_debug)
     {
-      pi (line, &i);
+      pi ("" /*line*/, &i);
     }
 #endif /* DEBUG386  */
 }
@@ -3319,14 +3663,18 @@ output_disp (insn_start_frag, insn_start_off)
 
 	      p = frag_more (size);
 	      reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
-	      if (reloc_type == BFD_RELOC_32
-		  && GOT_symbol
+	      if (GOT_symbol
 		  && GOT_symbol == i.op[n].disps->X_add_symbol
-		  && (i.op[n].disps->X_op == O_symbol
-		      || (i.op[n].disps->X_op == O_add
-			  && ((symbol_get_value_expression
-			       (i.op[n].disps->X_op_symbol)->X_op)
-			      == O_subtract))))
+		  && (((reloc_type == BFD_RELOC_32
+			|| reloc_type == BFD_RELOC_X86_64_32S
+			|| (reloc_type == BFD_RELOC_64
+			    && object_64bit))
+		       && (i.op[n].disps->X_op == O_symbol
+			   || (i.op[n].disps->X_op == O_add
+			       && ((symbol_get_value_expression
+				    (i.op[n].disps->X_op_symbol)->X_op)
+				   == O_subtract))))
+		      || reloc_type == BFD_RELOC_32_PCREL))
 		{
 		  offsetT add;
 
@@ -3343,11 +3691,18 @@ output_disp (insn_start_frag, insn_start_off)
 		      add += p - frag_now->fr_literal;
 		    }
 
-		  /* We don't support dynamic linking on x86-64 yet.  */
-		  if (flag_code == CODE_64BIT)
-		    abort ();
-		  reloc_type = BFD_RELOC_386_GOTPC;
-		  i.op[n].disps->X_add_number += add;
+		  if (!object_64bit)
+		    {
+		      reloc_type = BFD_RELOC_386_GOTPC;
+		      i.op[n].imms->X_add_number += add;
+		    }
+		  else if (reloc_type == BFD_RELOC_64)
+		    reloc_type = BFD_RELOC_X86_64_GOTPC64;
+		  else
+		    /* Don't do the adjustment for x86-64, as there
+		       the pcrel addressing is relative to the _next_
+		       insn, and that is taken care of in other code.  */
+		    reloc_type = BFD_RELOC_X86_64_GOTPC32;
 		}
 	      fix_new_exp (frag_now, p - frag_now->fr_literal, size,
 			   i.op[n].disps, pcrel, reloc_type);
@@ -3398,7 +3753,8 @@ output_imm (insn_start_frag, insn_start_off)
 	      int sign = 0;
 
 	      if ((i.types[n] & (Imm32S))
-		  && i.suffix == QWORD_MNEM_SUFFIX)
+		  && (i.suffix == QWORD_MNEM_SUFFIX
+		      || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
 		sign = 1;
 	      if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
 		{
@@ -3454,7 +3810,9 @@ output_imm (insn_start_frag, insn_start_off)
 	       * since the expression is not pcrel, I felt it would be
 	       * confusing to do it this way.  */
 
-	      if (reloc_type == BFD_RELOC_32
+	      if ((reloc_type == BFD_RELOC_32
+		   || reloc_type == BFD_RELOC_X86_64_32S
+		   || reloc_type == BFD_RELOC_64)
 		  && GOT_symbol
 		  && GOT_symbol == i.op[n].imms->X_add_symbol
 		  && (i.op[n].imms->X_op == O_symbol
@@ -3478,10 +3836,12 @@ output_imm (insn_start_frag, insn_start_off)
 		      add += p - frag_now->fr_literal;
 		    }
 
-		  /* We don't support dynamic linking on x86-64 yet.  */
-		  if (flag_code == CODE_64BIT)
-		    abort ();
-		  reloc_type = BFD_RELOC_386_GOTPC;
+		  if (!object_64bit)
+		    reloc_type = BFD_RELOC_386_GOTPC;
+		  else if (size == 4)
+		    reloc_type = BFD_RELOC_X86_64_GOTPC32;
+		  else if (size == 8)
+		    reloc_type = BFD_RELOC_X86_64_GOTPC64;
 		  i.op[n].imms->X_add_number += add;
 		}
 	      fix_new_exp (frag_now, p - frag_now->fr_literal, size,
@@ -3491,9 +3851,35 @@ output_imm (insn_start_frag, insn_start_off)
     }
 }
 
-#ifndef LEX_AT
-static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
+/* x86_cons_fix_new is called via the expression parsing code when a
+   reloc is needed.  We use this hook to get the correct .got reloc.  */
+static enum bfd_reloc_code_real got_reloc = NO_RELOC;
+static int cons_sign = -1;
+
+void
+x86_cons_fix_new (fragS *frag,
+     unsigned int off,
+     unsigned int len,
+     expressionS *exp)
+{
+  enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
+
+  got_reloc = NO_RELOC;
+
+#ifdef TE_PE
+  if (exp->X_op == O_secrel)
+    {
+      exp->X_op = O_symbol;
+      r = BFD_RELOC_32_SECREL;
+    }
+#endif
 
+  fix_new_exp (frag, off, len, exp, 0, r);
+}
+
+#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
+# define lex_got(reloc, adjust, types) NULL
+#else
 /* Parse operands of the form
    <symbol>@GOTOFF+<nnn>
    and similar .plt or .got references.
@@ -3504,32 +3890,44 @@ static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
    is non-null set it to the length of the string we removed from the
    input line.  Otherwise return NULL.  */
 static char *
-lex_got (reloc, adjust)
-     enum bfd_reloc_code_real *reloc;
-     int *adjust;
+lex_got (enum bfd_reloc_code_real *reloc,
+     int *adjust,
+     unsigned int *types)
 {
-  static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
+  /* Some of the relocations depend on the size of what field is to
+     be relocated.  But in our callers i386_immediate and i386_displacement
+     we don't yet know the operand size (this will be set by insn
+     matching).  Hence we record the word32 relocation here,
+     and adjust the reloc according to the real size in reloc().  */
   static const struct {
     const char *str;
-    const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
+    const enum bfd_reloc_code_real rel[2];
+    const unsigned int types64;
   } gotrel[] = {
-    { "PLT",      { BFD_RELOC_386_PLT32,      0, BFD_RELOC_X86_64_PLT32    } },
-    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,     0, 0                         } },
-    { "GOTPCREL", { 0,                        0, BFD_RELOC_X86_64_GOTPCREL } },
-    { "TLSGD",    { BFD_RELOC_386_TLS_GD,     0, BFD_RELOC_X86_64_TLSGD    } },
-    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,    0, 0                         } },
-    { "TLSLD",    { 0,                        0, BFD_RELOC_X86_64_TLSLD    } },
-    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,  0, BFD_RELOC_X86_64_GOTTPOFF } },
-    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,  0, BFD_RELOC_X86_64_TPOFF32  } },
-    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,     0, 0                         } },
-    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
-    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,  0, 0                         } },
-    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,     0, 0                         } },
-    { "GOT",      { BFD_RELOC_386_GOT32,      0, BFD_RELOC_X86_64_GOT32    } }
+    { "PLTOFF",   { 0,                        BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
+    { "PLT",      { BFD_RELOC_386_PLT32,      BFD_RELOC_X86_64_PLT32    }, Imm32|Imm32S|Disp32 },
+    { "GOTPLT",   { 0,                        BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
+    { "GOTOFF",   { BFD_RELOC_386_GOTOFF,     BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
+    { "GOTPCREL", { 0,                        BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
+    { "TLSGD",    { BFD_RELOC_386_TLS_GD,     BFD_RELOC_X86_64_TLSGD    }, Imm32|Imm32S|Disp32 },
+    { "TLSLDM",   { BFD_RELOC_386_TLS_LDM,    0                         }, 0 },
+    { "TLSLD",    { 0,                        BFD_RELOC_X86_64_TLSLD    }, Imm32|Imm32S|Disp32 },
+    { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,  BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
+    { "TPOFF",    { BFD_RELOC_386_TLS_LE_32,  BFD_RELOC_X86_64_TPOFF32  }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
+    { "NTPOFF",   { BFD_RELOC_386_TLS_LE,     0                         }, 0 },
+    { "DTPOFF",   { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
+    { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,  0                         }, 0 },
+    { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,     0                         }, 0 },
+    { "GOT",      { BFD_RELOC_386_GOT32,      BFD_RELOC_X86_64_GOT32    }, Imm32|Imm32S|Disp32|Imm64 },
+    { "TLSDESC",  { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
+    { "TLSCALL",  { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
   };
   char *cp;
   unsigned int j;
 
+  if (!IS_ELF)
+    return NULL;
+
   for (cp = input_line_pointer; *cp != '@'; cp++)
     if (is_end_of_line[(unsigned char) *cp])
       return NULL;
@@ -3541,15 +3939,23 @@ lex_got (reloc, adjust)
       len = strlen (gotrel[j].str);
       if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
 	{
-	  if (gotrel[j].rel[(unsigned int) flag_code] != 0)
+	  if (gotrel[j].rel[object_64bit] != 0)
 	    {
 	      int first, second;
 	      char *tmpbuf, *past_reloc;
 
-	      *reloc = gotrel[j].rel[(unsigned int) flag_code];
+	      *reloc = gotrel[j].rel[object_64bit];
 	      if (adjust)
 		*adjust = len;
 
+	      if (types)
+		{
+		  if (flag_code != CODE_64BIT)
+		    *types = Imm32|Disp32;
+		  else
+		    *types = gotrel[j].types64;
+		}
+
 	      if (GOT_symbol == NULL)
 		GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
 
@@ -3577,8 +3983,8 @@ lex_got (reloc, adjust)
 	      return tmpbuf;
 	    }
 
-	  as_bad (_("@%s reloc is not supported in %s bit mode"),
-		  gotrel[j].str, mode_name[(unsigned int) flag_code]);
+	  as_bad (_("@%s reloc is not supported with %d-bit output format"),
+		  gotrel[j].str, 1 << (5 + object_64bit));
 	  return NULL;
 	}
     }
@@ -3587,28 +3993,12 @@ lex_got (reloc, adjust)
   return NULL;
 }
 
-/* x86_cons_fix_new is called via the expression parsing code when a
-   reloc is needed.  We use this hook to get the correct .got reloc.  */
-static enum bfd_reloc_code_real got_reloc = NO_RELOC;
-
-void
-x86_cons_fix_new (frag, off, len, exp)
-     fragS *frag;
-     unsigned int off;
-     unsigned int len;
-     expressionS *exp;
-{
-  enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
-  got_reloc = NO_RELOC;
-  fix_new_exp (frag, off, len, exp, 0, r);
-}
-
 void
 x86_cons (exp, size)
      expressionS *exp;
      int size;
 {
-  if (size == 4)
+  if (size == 4 || (object_64bit && size == 8))
     {
       /* Handle @GOTOFF and the like in an expression.  */
       char *save;
@@ -3616,7 +4006,7 @@ x86_cons (exp, size)
       int adjust;
 
       save = input_line_pointer;
-      gotfree_input_line = lex_got (&got_reloc, &adjust);
+      gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
       if (gotfree_input_line)
 	input_line_pointer = gotfree_input_line;
 
@@ -3638,6 +4028,36 @@ x86_cons (exp, size)
 }
 #endif
 
+static void signed_cons (int size)
+{
+  if (flag_code == CODE_64BIT)
+    cons_sign = 1;
+  cons (size);
+  cons_sign = -1;
+}
+
+#ifdef TE_PE
+static void
+pe_directive_secrel (dummy)
+     int dummy ATTRIBUTE_UNUSED;
+{
+  expressionS exp;
+
+  do
+    {
+      expression (&exp);
+      if (exp.X_op == O_symbol)
+	exp.X_op = O_secrel;
+
+      emit_expr (&exp, 4);
+    }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;
+  demand_empty_rest_of_line ();
+}
+#endif
+
 static int i386_immediate PARAMS ((char *));
 
 static int
@@ -3645,11 +4065,10 @@ i386_immediate (imm_start)
      char *imm_start;
 {
   char *save_input_line_pointer;
-#ifndef LEX_AT
   char *gotfree_input_line;
-#endif
   segT exp_seg = 0;
   expressionS *exp;
+  unsigned int types = ~0U;
 
   if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
     {
@@ -3666,11 +4085,9 @@ i386_immediate (imm_start)
   save_input_line_pointer = input_line_pointer;
   input_line_pointer = imm_start;
 
-#ifndef LEX_AT
-  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
+  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
   if (gotfree_input_line)
     input_line_pointer = gotfree_input_line;
-#endif
 
   exp_seg = expression (exp);
 
@@ -3679,10 +4096,8 @@ i386_immediate (imm_start)
     as_bad (_("junk `%s' after expression"), input_line_pointer);
 
   input_line_pointer = save_input_line_pointer;
-#ifndef LEX_AT
   if (gotfree_input_line)
     free (gotfree_input_line);
-#endif
 
   if (exp->X_op == O_absent || exp->X_op == O_big)
     {
@@ -3722,6 +4137,7 @@ i386_immediate (imm_start)
 	 determined later, depending on destination register,
 	 suffix, or the default for the section.  */
       i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
+      i.types[this_operand] &= types;
     }
 
   return 1;
@@ -3741,7 +4157,6 @@ i386_scale (scale)
 
   switch (val)
     {
-    case 0:
     case 1:
       i.log2_scale_factor = 0;
       break;
@@ -3755,10 +4170,16 @@ i386_scale (scale)
       i.log2_scale_factor = 3;
       break;
     default:
-      as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
-	      scale);
-      input_line_pointer = save;
-      return NULL;
+      {
+	char sep = *input_line_pointer;
+
+	*input_line_pointer = '\0';
+	as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
+		scale);
+	*input_line_pointer = sep;
+	input_line_pointer = save;
+	return NULL;
+      }
     }
   if (i.log2_scale_factor != 0 && i.index_reg == 0)
     {
@@ -3783,18 +4204,45 @@ i386_displacement (disp_start, disp_end)
   expressionS *exp;
   segT exp_seg = 0;
   char *save_input_line_pointer;
-#ifndef LEX_AT
   char *gotfree_input_line;
-#endif
-  int bigdisp = Disp32;
+  int bigdisp, override;
+  unsigned int types = Disp;
 
+  if ((i.types[this_operand] & JumpAbsolute)
+      || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
+    {
+      bigdisp = Disp32;
+      override = (i.prefix[ADDR_PREFIX] != 0);
+    }
+  else
+    {
+      /* For PC-relative branches, the width of the displacement
+	 is dependent upon data size, not address size.  */
+      bigdisp = 0;
+      override = (i.prefix[DATA_PREFIX] != 0);
+    }
   if (flag_code == CODE_64BIT)
     {
-      if (i.prefix[ADDR_PREFIX] == 0)
-	bigdisp = Disp64;
+      if (!bigdisp)
+	bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
+		  ? Disp16
+		  : Disp32S | Disp32;
+      else if (!override)
+	bigdisp = Disp64 | Disp32S | Disp32;
+    }
+  else
+    {
+      if (!bigdisp)
+	{
+	  if (!override)
+	    override = (i.suffix == (flag_code != CODE_16BIT
+				     ? WORD_MNEM_SUFFIX
+				     : LONG_MNEM_SUFFIX));
+	  bigdisp = Disp32;
+	}
+      if ((flag_code == CODE_16BIT) ^ override)
+	bigdisp = Disp16;
     }
-  else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
-    bigdisp = Disp16;
   i.types[this_operand] |= bigdisp;
 
   exp = &disp_expressions[i.disp_operands];
@@ -3848,11 +4296,9 @@ i386_displacement (disp_start, disp_end)
       *displacement_string_end = '0';
     }
 #endif
-#ifndef LEX_AT
-  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
+  gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
   if (gotfree_input_line)
     input_line_pointer = gotfree_input_line;
-#endif
 
   exp_seg = expression (exp);
 
@@ -3864,16 +4310,15 @@ i386_displacement (disp_start, disp_end)
 #endif
   RESTORE_END_STRING (disp_end);
   input_line_pointer = save_input_line_pointer;
-#ifndef LEX_AT
   if (gotfree_input_line)
     free (gotfree_input_line);
-#endif
 
   /* We do this to make sure that the section symbol is in
      the symbol table.  We will ultimately change the relocation
      to be relative to the beginning of the section.  */
   if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
-      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
+      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
+      || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
     {
       if (exp->X_op != O_symbol)
 	{
@@ -3891,6 +4336,8 @@ i386_displacement (disp_start, disp_end)
       exp->X_op_symbol = GOT_symbol;
       if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
 	i.reloc[this_operand] = BFD_RELOC_32_PCREL;
+      else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
+	i.reloc[this_operand] = BFD_RELOC_64;
       else
 	i.reloc[this_operand] = BFD_RELOC_32;
     }
@@ -3920,8 +4367,10 @@ i386_displacement (disp_start, disp_end)
       return 0;
     }
 #endif
-  else if (flag_code == CODE_64BIT)
-    i.types[this_operand] |= Disp32S | Disp32;
+
+  if (!(i.types[this_operand] & ~Disp))
+    i.types[this_operand] &= types;
+
   return 1;
 }
 
@@ -3941,30 +4390,41 @@ i386_index_check (operand_string)
  tryprefix:
 #endif
   ok = 1;
-  if (flag_code == CODE_64BIT)
-    {
-      if (i.prefix[ADDR_PREFIX] == 0)
-	{
-	  /* 64bit checks.  */
-	  if ((i.base_reg
-	       && ((i.base_reg->reg_type & Reg64) == 0)
-		   && (i.base_reg->reg_type != BaseIndex
-		       || i.index_reg))
-	      || (i.index_reg
-		  && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
-		      != (Reg64 | BaseIndex))))
-	    ok = 0;
-	}
+  if ((current_templates->start->cpu_flags & CpuSVME)
+      && current_templates->end[-1].operand_types[0] == AnyMem)
+    {
+      /* Memory operands of SVME insns are special in that they only allow
+	 rAX as their memory address and ignore any segment override.  */
+      unsigned RegXX;
+
+      /* SKINIT is even more restrictive: it always requires EAX.  */
+      if (strcmp (current_templates->start->name, "skinit") == 0)
+	RegXX = Reg32;
+      else if (flag_code == CODE_64BIT)
+	RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
       else
-	{
-	  /* 32bit checks.  */
-	  if ((i.base_reg
-	       && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
-	      || (i.index_reg
-		  && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
-		      != (Reg32 | BaseIndex))))
-	    ok = 0;
-	}
+	RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
+		? Reg16
+		: Reg32;
+      if (!i.base_reg
+	  || !(i.base_reg->reg_type & Acc)
+	  || !(i.base_reg->reg_type & RegXX)
+	  || i.index_reg
+	  || (i.types[0] & Disp))
+	ok = 0;
+    }
+  else if (flag_code == CODE_64BIT)
+     {
+       unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
+
+       if ((i.base_reg
+	    && ((i.base_reg->reg_type & RegXX) == 0)
+	    && (i.base_reg->reg_type != BaseIndex
+		|| i.index_reg))
+	   || (i.index_reg
+	       && ((i.index_reg->reg_type & (RegXX | BaseIndex))
+		   != (RegXX | BaseIndex))))
+	 ok = 0;
     }
   else
     {
@@ -3997,8 +4457,7 @@ i386_index_check (operand_string)
   if (!ok)
     {
 #if INFER_ADDR_PREFIX
-      if (flag_code != CODE_64BIT
-	  && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
+      if (i.prefix[ADDR_PREFIX] == 0)
 	{
 	  i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
 	  i.prefixes += 1;
@@ -4007,7 +4466,7 @@ i386_index_check (operand_string)
 	     FIXME.  There doesn't seem to be any real need for separate
 	     Disp16 and Disp32 flags.  The same goes for Imm16 and Imm32.
 	     Removing them would probably clean up the code quite a lot.  */
-	  if (i.types[this_operand] & (Disp16 | Disp32))
+	  if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
 	     i.types[this_operand] ^= (Disp16 | Disp32);
 	  fudged = 1;
 	  goto tryprefix;
@@ -4020,9 +4479,8 @@ i386_index_check (operand_string)
 	as_bad (_("`%s' is not a valid %s bit base/index expression"),
 		operand_string,
 		flag_code_names[flag_code]);
-      return 0;
     }
-  return 1;
+  return ok;
 }
 
 /* Parse OPERAND_STRING into the i386_insn structure I.  Returns non-zero
@@ -4050,8 +4508,7 @@ i386_operand (operand_string)
     }
 
   /* Check if operand is a register.  */
-  if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
-      && (r = parse_register (op_string, &end_op)) != NULL)
+  if ((r = parse_register (op_string, &end_op)) != NULL)
     {
       /* Check for a segment override by searching for ':' after a
 	 segment register.  */
@@ -4189,8 +4646,7 @@ i386_operand (operand_string)
 	    ++base_string;
 
 	  if (*base_string == ','
-	      || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
-		  && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
+	      || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
 	    {
 	      displacement_string_end = temp_string;
 
@@ -4210,8 +4666,7 @@ i386_operand (operand_string)
 		  if (is_space_char (*base_string))
 		    ++base_string;
 
-		  if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
-		      && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
+		  if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
 		    {
 		      base_string = end_op;
 		      if (is_space_char (*base_string))
@@ -4336,7 +4791,7 @@ md_estimate_size_before_relax (fragP, segment)
      shared library.  */
   if (S_GET_SEGMENT (fragP->fr_symbol) != segment
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-      || (OUTPUT_FLAVOR == bfd_target_elf_flavour
+      || (IS_ELF
 	  && (S_IS_EXTERNAL (fragP->fr_symbol)
 	      || S_IS_WEAK (fragP->fr_symbol)))
 #endif
@@ -4523,6 +4978,20 @@ md_convert_frag (abfd, sec, fragP)
 	}
     }
 
+  /* If size if less then four we are sure that the operand fits,
+     but if it's 4, then it could be that the displacement is larger
+     then -/+ 2GB.  */
+  if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
+      && object_64bit
+      && ((addressT) (displacement_from_opcode_start - extension
+                      + ((addressT) 1 << 31))
+          > (((addressT) 2 << 31) - 1)))
+    {
+      as_bad_where (fragP->fr_file, fragP->fr_line,
+		    _("jump target out of range"));
+      /* Make us emit 0.  */
+      displacement_from_opcode_start = extension;
+    }
   /* Now put displacement after opcode.  */
   md_number_to_chars ((char *) where_to_put_displacement,
 		      (valueT) (displacement_from_opcode_start - extension),
@@ -4536,9 +5005,6 @@ int md_short_jump_size = 2;
 /* Size of dword displacement jmp.  */
 int md_long_jump_size = 5;
 
-/* Size of relocation record.  */
-const int md_reloc_size = 8;
-
 void
 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
      char *ptr;
@@ -4576,7 +5042,7 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
    we are handling.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      /* The fix we're to put in.  */
      fixS *fixP;
      /* Pointer to the value of the bits.  */
@@ -4595,7 +5061,11 @@ md_apply_fix3 (fixP, valP, seg)
 	default:
 	  break;
 
+	case BFD_RELOC_64:
+	  fixP->fx_r_type = BFD_RELOC_64_PCREL;
+	  break;
 	case BFD_RELOC_32:
+	case BFD_RELOC_X86_64_32S:
 	  fixP->fx_r_type = BFD_RELOC_32_PCREL;
 	  break;
 	case BFD_RELOC_16:
@@ -4609,6 +5079,7 @@ md_apply_fix3 (fixP, valP, seg)
 
   if (fixP->fx_addsy != NULL
       && (fixP->fx_r_type == BFD_RELOC_32_PCREL
+	  || fixP->fx_r_type == BFD_RELOC_64_PCREL
 	  || fixP->fx_r_type == BFD_RELOC_16_PCREL
 	  || fixP->fx_r_type == BFD_RELOC_8_PCREL)
       && !use_rela_relocations)
@@ -4618,7 +5089,7 @@ md_apply_fix3 (fixP, valP, seg)
 	 subtract the current location (for partial_inplace, PC relative
 	 relocations); see more below.  */
 #ifndef OBJ_AOUT
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour
+      if (IS_ELF
 #ifdef TE_PE
 	  || OUTPUT_FLAVOR == bfd_target_coff_flavour
 #endif
@@ -4626,7 +5097,7 @@ md_apply_fix3 (fixP, valP, seg)
 	value += fixP->fx_where + fixP->fx_frag->fr_address;
 #endif
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
+      if (IS_ELF)
 	{
 	  segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
 
@@ -4644,9 +5115,10 @@ md_apply_fix3 (fixP, valP, seg)
 	}
 #endif
 #if defined (OBJ_COFF) && defined (TE_PE)
-      /* For some reason, the PE format does not store a section
-	 address offset for a PC relative symbol.  */
-      if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
+      /* For some reason, the PE format does not store a
+	 section address offset for a PC relative symbol.  */
+      if (S_GET_SEGMENT (fixP->fx_addsy) != seg
+	  || S_IS_WEAK (fixP->fx_addsy))
 	value += md_pcrel_from (fixP);
 #endif
     }
@@ -4654,8 +5126,7 @@ md_apply_fix3 (fixP, valP, seg)
   /* Fix a few things - the dynamic linker expects certain values here,
      and we must not disappoint it.  */
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-      && fixP->fx_addsy)
+  if (IS_ELF && fixP->fx_addsy)
     switch (fixP->fx_r_type)
       {
       case BFD_RELOC_386_PLT32:
@@ -4670,19 +5141,30 @@ md_apply_fix3 (fixP, valP, seg)
       case BFD_RELOC_386_TLS_IE_32:
       case BFD_RELOC_386_TLS_IE:
       case BFD_RELOC_386_TLS_GOTIE:
+      case BFD_RELOC_386_TLS_GOTDESC:
       case BFD_RELOC_X86_64_TLSGD:
       case BFD_RELOC_X86_64_TLSLD:
       case BFD_RELOC_X86_64_GOTTPOFF:
+      case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
 	value = 0; /* Fully resolved at runtime.  No addend.  */
 	/* Fallthrough */
       case BFD_RELOC_386_TLS_LE:
       case BFD_RELOC_386_TLS_LDO_32:
       case BFD_RELOC_386_TLS_LE_32:
       case BFD_RELOC_X86_64_DTPOFF32:
+      case BFD_RELOC_X86_64_DTPOFF64:
       case BFD_RELOC_X86_64_TPOFF32:
+      case BFD_RELOC_X86_64_TPOFF64:
 	S_SET_THREAD_LOCAL (fixP->fx_addsy);
 	break;
 
+      case BFD_RELOC_386_TLS_DESC_CALL:
+      case BFD_RELOC_X86_64_TLSDESC_CALL:
+	value = 0; /* Fully resolved at runtime.  No addend.  */
+	S_SET_THREAD_LOCAL (fixP->fx_addsy);
+	fixP->fx_done = 0;
+	return;
+
       case BFD_RELOC_386_GOT32:
       case BFD_RELOC_X86_64_GOT32:
 	value = 0; /* Fully resolved at runtime.  No addend.  */
@@ -4768,7 +5250,7 @@ md_atof (type, litP, sizeP)
   return 0;
 }
 
-char output_invalid_buf[8];
+static char output_invalid_buf[8];
 
 static char *
 output_invalid (c)
@@ -4784,9 +5266,7 @@ output_invalid (c)
 /* REG_STRING starts *before* REGISTER_PREFIX.  */
 
 static const reg_entry *
-parse_register (reg_string, end_op)
-     char *reg_string;
-     char **end_op;
+parse_real_register (char *reg_string, char **end_op)
 {
   char *s = reg_string;
   char *p;
@@ -4846,14 +5326,87 @@ parse_register (reg_string, end_op)
     }
 
   if (r != NULL
-      && (r->reg_flags & (RegRex64 | RegRex)) != 0
+      && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
+      && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
       && flag_code != CODE_64BIT)
+    return (const reg_entry *) NULL;
+
+  return r;
+}
+
+/* REG_STRING starts *before* REGISTER_PREFIX.  */
+
+static const reg_entry *
+parse_register (char *reg_string, char **end_op)
+{
+  const reg_entry *r;
+
+  if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
+    r = parse_real_register (reg_string, end_op);
+  else
+    r = NULL;
+  if (!r)
     {
-      return (const reg_entry *) NULL;
-    }
+      char *save = input_line_pointer;
+      char c;
+      symbolS *symbolP;
+
+      input_line_pointer = reg_string;
+      c = get_symbol_end ();
+      symbolP = symbol_find (reg_string);
+      if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
+	{
+	  const expressionS *e = symbol_get_value_expression (symbolP);
 
+	  know (e->X_op == O_register);
+	  know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
+	  r = i386_regtab + e->X_add_number;
+	  *end_op = input_line_pointer;
+	}
+      *input_line_pointer = c;
+      input_line_pointer = save;
+    }
   return r;
 }
+
+int
+i386_parse_name (char *name, expressionS *e, char *nextcharP)
+{
+  const reg_entry *r;
+  char *end = input_line_pointer;
+
+  *end = *nextcharP;
+  r = parse_register (name, &input_line_pointer);
+  if (r && end <= input_line_pointer)
+    {
+      *nextcharP = *input_line_pointer;
+      *input_line_pointer = 0;
+      e->X_op = O_register;
+      e->X_add_number = r - i386_regtab;
+      return 1;
+    }
+  input_line_pointer = end;
+  *end = 0;
+  return 0;
+}
+
+void
+md_operand (expressionS *e)
+{
+  if (*input_line_pointer == REGISTER_PREFIX)
+    {
+      char *end;
+      const reg_entry *r = parse_real_register (input_line_pointer, &end);
+
+      if (r)
+	{
+	  e->X_op = O_register;
+	  e->X_add_number = r - i386_regtab;
+	  input_line_pointer = end;
+	}
+    }
+}
+
 
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
 const char *md_shortopts = "kVQ:sqn";
@@ -4861,13 +5414,16 @@ const char *md_shortopts = "kVQ:sqn";
 const char *md_shortopts = "qn";
 #endif
 
-struct option md_longopts[] = {
 #define OPTION_32 (OPTION_MD_BASE + 0)
+#define OPTION_64 (OPTION_MD_BASE + 1)
+#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
+
+struct option md_longopts[] = {
   {"32", no_argument, NULL, OPTION_32},
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
-#define OPTION_64 (OPTION_MD_BASE + 1)
   {"64", no_argument, NULL, OPTION_64},
 #endif
+  {"divide", no_argument, NULL, OPTION_DIVIDE},
   {NULL, no_argument, NULL, 0}
 };
 size_t md_longopts_size = sizeof (md_longopts);
@@ -4929,6 +5485,23 @@ md_parse_option (c, arg)
       default_arch = "i386";
       break;
 
+    case OPTION_DIVIDE:
+#ifdef SVR4_COMMENT_CHARS
+      {
+	char *n, *t;
+	const char *s;
+
+	n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
+	t = n;
+	for (s = i386_comment_chars; *s != '\0'; s++)
+	  if (*s != '/')
+	    *t++ = *s;
+	*t = '\0';
+	i386_comment_chars = n;
+      }
+#endif
+      break;
+
     default:
       return 0;
     }
@@ -4943,14 +5516,21 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -Q                      ignored\n\
   -V                      print assembler version number\n\
-  -k                      ignored\n\
+  -k                      ignored\n"));
+#endif
+  fprintf (stream, _("\
   -n                      Do not optimize code alignment\n\
-  -q                      quieten some warnings\n\
+  -q                      quieten some warnings\n"));
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  fprintf (stream, _("\
   -s                      ignored\n"));
+#endif
+#ifdef SVR4_COMMENT_CHARS
+  fprintf (stream, _("\
+  --divide                do not treat `/' as a comment character\n"));
 #else
   fprintf (stream, _("\
-  -n                      Do not optimize code alignment\n\
-  -q                      quieten some warnings\n"));
+  --divide                ignored\n"));
 #endif
 }
 
@@ -4982,7 +5562,10 @@ i386_target_format ()
     case bfd_target_elf_flavour:
       {
 	if (flag_code == CODE_64BIT)
-	  use_rela_relocations = 1;
+	  {
+	    object_64bit = 1;
+	    use_rela_relocations = 1;
+	  }
 	return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
       }
 #endif
@@ -4997,8 +5580,7 @@ i386_target_format ()
 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
 void i386_elf_emit_arch_note ()
 {
-  if (OUTPUT_FLAVOR == bfd_target_elf_flavour
-      && cpu_arch_name != NULL)
+  if (IS_ELF && cpu_arch_name != NULL)
     {
       char *p;
       asection *seg = now_seg;
@@ -5101,6 +5683,10 @@ s_bss (ignore)
 {
   int temp;
 
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+  if (IS_ELF)
+    obj_elf_section_change_hook ();
+#endif
   temp = get_absolute_expression ();
   subseg_set (bss_section, (subsegT) temp);
   demand_empty_rest_of_line ();
@@ -5114,18 +5700,18 @@ i386_validate_fix (fixp)
 {
   if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
     {
-      /* GOTOFF relocation are nonsense in 64bit mode.  */
       if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
 	{
-	  if (flag_code != CODE_64BIT)
+	  if (!object_64bit)
 	    abort ();
 	  fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
 	}
       else
 	{
-	  if (flag_code == CODE_64BIT)
-	    abort ();
-	  fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
+	  if (!object_64bit)
+	    fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
+	  else
+	    fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
 	}
       fixp->fx_subsy = 0;
     }
@@ -5156,17 +5742,39 @@ tc_gen_reloc (section, fixp)
     case BFD_RELOC_386_TLS_GOTIE:
     case BFD_RELOC_386_TLS_LE_32:
     case BFD_RELOC_386_TLS_LE:
-    case BFD_RELOC_X86_64_32S:
+    case BFD_RELOC_386_TLS_GOTDESC:
+    case BFD_RELOC_386_TLS_DESC_CALL:
     case BFD_RELOC_X86_64_TLSGD:
     case BFD_RELOC_X86_64_TLSLD:
     case BFD_RELOC_X86_64_DTPOFF32:
+    case BFD_RELOC_X86_64_DTPOFF64:
     case BFD_RELOC_X86_64_GOTTPOFF:
     case BFD_RELOC_X86_64_TPOFF32:
+    case BFD_RELOC_X86_64_TPOFF64:
+    case BFD_RELOC_X86_64_GOTOFF64:
+    case BFD_RELOC_X86_64_GOTPC32:
+    case BFD_RELOC_X86_64_GOT64:
+    case BFD_RELOC_X86_64_GOTPCREL64:
+    case BFD_RELOC_X86_64_GOTPC64:
+    case BFD_RELOC_X86_64_GOTPLT64:
+    case BFD_RELOC_X86_64_PLTOFF64:
+    case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+    case BFD_RELOC_X86_64_TLSDESC_CALL:
     case BFD_RELOC_RVA:
     case BFD_RELOC_VTABLE_ENTRY:
     case BFD_RELOC_VTABLE_INHERIT:
+#ifdef TE_PE
+    case BFD_RELOC_32_SECREL:
+#endif
       code = fixp->fx_r_type;
       break;
+    case BFD_RELOC_X86_64_32S:
+      if (!fixp->fx_pcrel)
+	{
+	  /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32.  */
+	  code = fixp->fx_r_type;
+	  break;
+	}
     default:
       if (fixp->fx_pcrel)
 	{
@@ -5181,6 +5789,9 @@ tc_gen_reloc (section, fixp)
 	    case 1: code = BFD_RELOC_8_PCREL;  break;
 	    case 2: code = BFD_RELOC_16_PCREL; break;
 	    case 4: code = BFD_RELOC_32_PCREL; break;
+#ifdef BFD64
+	    case 8: code = BFD_RELOC_64_PCREL; break;
+#endif
 	    }
 	}
       else
@@ -5204,14 +5815,22 @@ tc_gen_reloc (section, fixp)
       break;
     }
 
-  if (code == BFD_RELOC_32
+  if ((code == BFD_RELOC_32
+       || code == BFD_RELOC_32_PCREL
+       || code == BFD_RELOC_X86_64_32S)
       && GOT_symbol
       && fixp->fx_addsy == GOT_symbol)
     {
-      /* We don't support GOTPC on 64bit targets.  */
-      if (flag_code == CODE_64BIT)
-	abort ();
-      code = BFD_RELOC_386_GOTPC;
+      if (!object_64bit)
+	code = BFD_RELOC_386_GOTPC;
+      else
+	code = BFD_RELOC_X86_64_GOTPC32;
+    }
+  if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
+      && GOT_symbol
+      && fixp->fx_addsy == GOT_symbol)
+    {
+      code = BFD_RELOC_X86_64_GOTPC64;
     }
 
   rel = (arelent *) xmalloc (sizeof (arelent));
@@ -5219,6 +5838,7 @@ tc_gen_reloc (section, fixp)
   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 
   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+
   if (!use_rela_relocations)
     {
       /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
@@ -5242,6 +5862,8 @@ tc_gen_reloc (section, fixp)
 	  case BFD_RELOC_X86_64_TLSGD:
 	  case BFD_RELOC_X86_64_TLSLD:
 	  case BFD_RELOC_X86_64_GOTTPOFF:
+	  case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
+	  case BFD_RELOC_X86_64_TLSDESC_CALL:
 	    rel->addend = fixp->fx_offset - fixp->fx_size;
 	    break;
 	  default:
@@ -5287,11 +5909,13 @@ tc_gen_reloc (section, fixp)
 
     alpha		[a-zA-Z]
 
+    binOp		& | AND | \| | OR | ^ | XOR
+
     byteRegister	AL | AH | BL | BH | CL | CH | DL | DH
 
     constant		digits [[ radixOverride ]]
 
-    dataType		BYTE | WORD | DWORD | QWORD | XWORD
+    dataType		BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
 
     digits		decdigit
 			| digits decdigit
@@ -5299,13 +5923,21 @@ tc_gen_reloc (section, fixp)
 
     decdigit		[0-9]
 
-    e05			e05 addOp e06
+    e04			e04 addOp e05
+			| e05
+
+    e05			e05 binOp e06
 			| e06
 
     e06			e06 mulOp e09
 			| e09
 
     e09			OFFSET e10
+			| SHORT e10
+			| + e10
+			| - e10
+			| ~ e10
+			| NOT e10
 			| e09 PTR e10
 			| e09 : e10
 			| e10
@@ -5321,8 +5953,8 @@ tc_gen_reloc (section, fixp)
 			| $
 			| register
 
- => expr		SHORT e05
-			| e05
+ => expr		expr cmpOp e04
+			| e04
 
     gpRegister		AX | EAX | BX | EBX | CX | ECX | DX | EDX
 			| BP | EBP | SP | ESP | DI | EDI | SI | ESI
@@ -5334,7 +5966,7 @@ tc_gen_reloc (section, fixp)
 			| id alpha
 			| id decdigit
 
-    mulOp		* | / | MOD
+    mulOp		* | / | % | MOD | << | SHL | >> | SHR
 
     quote		" | '
 
@@ -5344,7 +5976,7 @@ tc_gen_reloc (section, fixp)
 
     segmentRegister	CS | DS | ES | FS | GS | SS
 
-    specialRegister	CR0 | CR2 | CR3
+    specialRegister	CR0 | CR2 | CR3 | CR4
 			| DR0 | DR1 | DR2 | DR3 | DR6 | DR7
 			| TR3 | TR4 | TR5 | TR6 | TR7
 
@@ -5352,12 +5984,19 @@ tc_gen_reloc (section, fixp)
     done by calling parse_register) and eliminate immediate left recursion
     to implement a recursive-descent parser.
 
-    expr	SHORT e05
-		| e05
+    expr	e04 expr'
+
+    expr'	cmpOp e04 expr'
+		| Empty
+
+    e04		e05 e04'
+
+    e04'	addOp e05 e04'
+		| Empty
 
     e05		e06 e05'
 
-    e05'	addOp e06 e05'
+    e05'	binOp e06 e05'
 		| Empty
 
     e06		e09 e06'
@@ -5366,6 +6005,11 @@ tc_gen_reloc (section, fixp)
 		| Empty
 
     e09		OFFSET e10 e09'
+		| SHORT e10'
+		| + e10'
+		| - e10'
+		| ~ e10'
+		| NOT e10'
 		| e10 e09'
 
     e09'	PTR e10 e09'
@@ -5382,8 +6026,11 @@ tc_gen_reloc (section, fixp)
 		| BYTE
 		| WORD
 		| DWORD
+		| FWORD
 		| QWORD
-		| XWORD
+		| TBYTE
+		| OWORD
+		| XMMWORD
 		| .
 		| $
 		| register
@@ -5398,8 +6045,11 @@ struct intel_parser_s
     int got_a_float;		/* Whether the operand is a float.  */
     int op_modifier;		/* Operand modifier.  */
     int is_mem;			/* 1 if operand is memory reference.  */
+    int in_offset;			/* >=1 if parsing operand of offset.  */
+    int in_bracket;			/* >=1 if parsing operand in brackets.  */
     const reg_entry *reg;	/* Last register reference found.  */
     char *disp;			/* Displacement string being built.  */
+    char *next_operand;		/* Resume point when splitting operands.  */
   };
 
 static struct intel_parser_s intel_parser;
@@ -5421,28 +6071,30 @@ static struct intel_token cur_token, prev_token;
 #define T_REG		2
 #define T_BYTE		3
 #define T_WORD		4
-#define	T_DWORD		5
-#define T_QWORD		6
-#define T_XWORD		7
+#define T_DWORD		5
+#define T_FWORD		6
+#define T_QWORD		7
+#define T_TBYTE		8
+#define T_XMMWORD	9
 #undef  T_SHORT
-#define T_SHORT		8
-#define T_OFFSET	9
-#define T_PTR		10
-#define T_ID		11
+#define T_SHORT		10
+#define T_OFFSET	11
+#define T_PTR		12
+#define T_ID		13
+#define T_SHL		14
+#define T_SHR		15
 
 /* Prototypes for intel parser functions.  */
 static int intel_match_token	PARAMS ((int code));
 static void intel_get_token	PARAMS ((void));
 static void intel_putback_token	PARAMS ((void));
 static int intel_expr		PARAMS ((void));
+static int intel_e04		PARAMS ((void));
 static int intel_e05		PARAMS ((void));
-static int intel_e05_1		PARAMS ((void));
 static int intel_e06		PARAMS ((void));
-static int intel_e06_1		PARAMS ((void));
 static int intel_e09		PARAMS ((void));
-static int intel_e09_1		PARAMS ((void));
+static int intel_bracket_expr	PARAMS ((void));
 static int intel_e10		PARAMS ((void));
-static int intel_e10_1		PARAMS ((void));
 static int intel_e11		PARAMS ((void));
 
 static int
@@ -5453,34 +6105,42 @@ i386_intel_operand (operand_string, got_a_float)
   int ret;
   char *p;
 
-  /* Initialize token holders.  */
-  cur_token.code = prev_token.code = T_NIL;
-  cur_token.reg = prev_token.reg = NULL;
-  cur_token.str = prev_token.str = NULL;
-
-  /* Initialize parser structure.  */
-  p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
-  if (p == NULL)
-    abort ();
-  strcpy (intel_parser.op_string, operand_string);
-  intel_parser.got_a_float = got_a_float;
-  intel_parser.op_modifier = -1;
-  intel_parser.is_mem = 0;
-  intel_parser.reg = NULL;
-  intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
-  if (intel_parser.disp == NULL)
-    abort ();
-  intel_parser.disp[0] = '\0';
-
-  /* Read the first token and start the parser.  */
-  intel_get_token ();
-  ret = intel_expr ();
+  p = intel_parser.op_string = xstrdup (operand_string);
+  intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
 
-  if (ret)
+  for (;;)
     {
+      /* Initialize token holders.  */
+      cur_token.code = prev_token.code = T_NIL;
+      cur_token.reg = prev_token.reg = NULL;
+      cur_token.str = prev_token.str = NULL;
+
+      /* Initialize parser structure.  */
+      intel_parser.got_a_float = got_a_float;
+      intel_parser.op_modifier = 0;
+      intel_parser.is_mem = 0;
+      intel_parser.in_offset = 0;
+      intel_parser.in_bracket = 0;
+      intel_parser.reg = NULL;
+      intel_parser.disp[0] = '\0';
+      intel_parser.next_operand = NULL;
+
+      /* Read the first token and start the parser.  */
+      intel_get_token ();
+      ret = intel_expr ();
+
+      if (!ret)
+	break;
+
+      if (cur_token.code != T_NIL)
+	{
+	  as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
+		  current_templates->start->name, cur_token.str);
+	  ret = 0;
+	}
       /* If we found a memory reference, hand it over to i386_displacement
 	 to fill in the rest of the operand fields.  */
-      if (intel_parser.is_mem)
+      else if (intel_parser.is_mem)
 	{
 	  if ((i.mem_operands == 1
 	       && (current_templates->start->opcode_modifier & IsString) == 0)
@@ -5495,18 +6155,46 @@ i386_intel_operand (operand_string, got_a_float)
 	      char *s = intel_parser.disp;
 	      i.mem_operands++;
 
+	      if (!quiet_warnings && intel_parser.is_mem < 0)
+		/* See the comments in intel_bracket_expr.  */
+		as_warn (_("Treating `%s' as memory reference"), operand_string);
+
 	      /* Add the displacement expression.  */
 	      if (*s != '\0')
 		ret = i386_displacement (s, s + strlen (s));
 	      if (ret)
-		ret = i386_index_check (operand_string);
+		{
+		  /* Swap base and index in 16-bit memory operands like
+		     [si+bx]. Since i386_index_check is also used in AT&T
+		     mode we have to do that here.  */
+		  if (i.base_reg
+		      && i.index_reg
+		      && (i.base_reg->reg_type & Reg16)
+		      && (i.index_reg->reg_type & Reg16)
+		      && i.base_reg->reg_num >= 6
+		      && i.index_reg->reg_num < 6)
+		    {
+		      const reg_entry *base = i.index_reg;
+
+		      i.index_reg = i.base_reg;
+		      i.base_reg = base;
+		    }
+		  ret = i386_index_check (operand_string);
+		}
 	    }
 	}
 
       /* Constant and OFFSET expressions are handled by i386_immediate.  */
-      else if (intel_parser.op_modifier == OFFSET_FLAT
+      else if ((intel_parser.op_modifier & (1 << T_OFFSET))
 	       || intel_parser.reg == NULL)
 	ret = i386_immediate (intel_parser.disp);
+
+      if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
+        ret = 0;
+      if (!ret || !intel_parser.next_operand)
+	break;
+      intel_parser.op_string = intel_parser.next_operand;
+      this_operand = i.operands++;
     }
 
   free (p);
@@ -5515,50 +6203,81 @@ i386_intel_operand (operand_string, got_a_float)
   return ret;
 }
 
-/* expr	SHORT e05
-	| e05  */
+#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
+
+/* expr	e04 expr'
+
+   expr'  cmpOp e04 expr'
+	| Empty  */
 static int
 intel_expr ()
 {
-  /* expr  SHORT e05  */
-  if (cur_token.code == T_SHORT)
+  /* XXX Implement the comparison operators.  */
+  return intel_e04 ();
+}
+
+/* e04	e05 e04'
+
+   e04'	addOp e05 e04'
+	| Empty  */
+static int
+intel_e04 ()
+{
+  int nregs = -1;
+
+  for (;;)
     {
-      intel_parser.op_modifier = SHORT;
-      intel_match_token (T_SHORT);
+      if (!intel_e05())
+	return 0;
 
-      return (intel_e05 ());
-    }
+      if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+	i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
 
-  /* expr  e05  */
-  else
-    return intel_e05 ();
+      if (cur_token.code == '+')
+	nregs = -1;
+      else if (cur_token.code == '-')
+	nregs = NUM_ADDRESS_REGS;
+      else
+	return 1;
+
+      strcat (intel_parser.disp, cur_token.str);
+      intel_match_token (cur_token.code);
+    }
 }
 
 /* e05	e06 e05'
 
-   e05'	addOp e06 e05'
+   e05'	binOp e06 e05'
 	| Empty  */
 static int
 intel_e05 ()
 {
-  return (intel_e06 () && intel_e05_1 ());
-}
+  int nregs = ~NUM_ADDRESS_REGS;
 
-static int
-intel_e05_1 ()
-{
-  /* e05'  addOp e06 e05'  */
-  if (cur_token.code == '+' || cur_token.code == '-')
+  for (;;)
     {
-      strcat (intel_parser.disp, cur_token.str);
+      if (!intel_e06())
+	return 0;
+
+      if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
+	{
+	  char str[2];
+
+	  str[0] = cur_token.code;
+	  str[1] = 0;
+	  strcat (intel_parser.disp, str);
+	}
+      else
+	break;
+
       intel_match_token (cur_token.code);
 
-      return (intel_e06 () && intel_e05_1 ());
+      if (nregs < 0)
+	nregs = ~nregs;
     }
-
-  /* e05'  Empty  */
-  else
-    return 1;
+  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+    i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
+  return 1;
 }
 
 /* e06	e09 e06'
@@ -5568,27 +6287,44 @@ intel_e05_1 ()
 static int
 intel_e06 ()
 {
-  return (intel_e09 () && intel_e06_1 ());
-}
+  int nregs = ~NUM_ADDRESS_REGS;
 
-static int
-intel_e06_1 ()
-{
-  /* e06'  mulOp e09 e06'  */
-  if (cur_token.code == '*' || cur_token.code == '/')
+  for (;;)
     {
-      strcat (intel_parser.disp, cur_token.str);
-      intel_match_token (cur_token.code);
+      if (!intel_e09())
+	return 0;
 
-      return (intel_e09 () && intel_e06_1 ());
-    }
+      if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
+	{
+	  char str[2];
 
-  /* e06'  Empty  */
-  else
-    return 1;
+	  str[0] = cur_token.code;
+	  str[1] = 0;
+	  strcat (intel_parser.disp, str);
+	}
+      else if (cur_token.code == T_SHL)
+	strcat (intel_parser.disp, "<<");
+      else if (cur_token.code == T_SHR)
+	strcat (intel_parser.disp, ">>");
+      else
+	break;
+
+     intel_match_token (cur_token.code);
+
+      if (nregs < 0)
+	nregs = ~nregs;
+    }
+  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+    i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
+  return 1;
 }
 
-/* e09	OFFSET e10 e09'
+/* e09	OFFSET e09
+	| SHORT e09
+	| + e09
+	| - e09
+	| ~ e09
+	| NOT e09
 	| e10 e09'
 
    e09'	PTR e10 e09'
@@ -5597,82 +6333,287 @@ intel_e06_1 ()
 static int
 intel_e09 ()
 {
-  /* e09  OFFSET e10 e09'  */
-  if (cur_token.code == T_OFFSET)
+  int nregs = ~NUM_ADDRESS_REGS;
+  int in_offset = 0;
+
+  for (;;)
     {
-      intel_parser.is_mem = 0;
-      intel_parser.op_modifier = OFFSET_FLAT;
-      intel_match_token (T_OFFSET);
+      /* Don't consume constants here.  */
+      if (cur_token.code == '+' || cur_token.code == '-')
+	{
+	  /* Need to look one token ahead - if the next token
+	     is a constant, the current token is its sign.  */
+	  int next_code;
 
-      return (intel_e10 () && intel_e09_1 ());
-    }
+	  intel_match_token (cur_token.code);
+	  next_code = cur_token.code;
+	  intel_putback_token ();
+	  if (next_code == T_CONST)
+	    break;
+	}
 
-  /* e09  e10 e09'  */
-  else
-    return (intel_e10 () && intel_e09_1 ());
-}
+      /* e09  OFFSET e09  */
+      if (cur_token.code == T_OFFSET)
+	{
+	  if (!in_offset++)
+	    ++intel_parser.in_offset;
+	}
 
-static int
-intel_e09_1 ()
-{
-  /* e09'  PTR e10 e09' */
-  if (cur_token.code == T_PTR)
-    {
-      if (prev_token.code == T_BYTE)
-	i.suffix = BYTE_MNEM_SUFFIX;
+      /* e09  SHORT e09  */
+      else if (cur_token.code == T_SHORT)
+	intel_parser.op_modifier |= 1 << T_SHORT;
 
-      else if (prev_token.code == T_WORD)
+      /* e09  + e09  */
+      else if (cur_token.code == '+')
+	strcat (intel_parser.disp, "+");
+
+      /* e09  - e09
+	      | ~ e09
+	      | NOT e09  */
+      else if (cur_token.code == '-' || cur_token.code == '~')
 	{
-	  if (intel_parser.got_a_float == 2)	/* "fi..." */
-	    i.suffix = SHORT_MNEM_SUFFIX;
-	  else
-	    i.suffix = WORD_MNEM_SUFFIX;
+	  char str[2];
+
+	  if (nregs < 0)
+	    nregs = ~nregs;
+	  str[0] = cur_token.code;
+	  str[1] = 0;
+	  strcat (intel_parser.disp, str);
 	}
 
-      else if (prev_token.code == T_DWORD)
+      /* e09  e10 e09'  */
+      else
+	break;
+
+      intel_match_token (cur_token.code);
+    }
+
+  for (;;)
+    {
+      if (!intel_e10 ())
+	return 0;
+
+      /* e09'  PTR e10 e09' */
+      if (cur_token.code == T_PTR)
 	{
-	  if (intel_parser.got_a_float == 1)	/* "f..." */
-	    i.suffix = SHORT_MNEM_SUFFIX;
+	  char suffix;
+
+	  if (prev_token.code == T_BYTE)
+	    suffix = BYTE_MNEM_SUFFIX;
+
+	  else if (prev_token.code == T_WORD)
+	    {
+	      if (current_templates->start->name[0] == 'l'
+		  && current_templates->start->name[2] == 's'
+		  && current_templates->start->name[3] == 0)
+		suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+	      else if (intel_parser.got_a_float == 2)	/* "fi..." */
+		suffix = SHORT_MNEM_SUFFIX;
+	      else
+		suffix = WORD_MNEM_SUFFIX;
+	    }
+
+	  else if (prev_token.code == T_DWORD)
+	    {
+	      if (current_templates->start->name[0] == 'l'
+		  && current_templates->start->name[2] == 's'
+		  && current_templates->start->name[3] == 0)
+		suffix = WORD_MNEM_SUFFIX;
+	      else if (flag_code == CODE_16BIT
+		       && (current_templates->start->opcode_modifier
+			   & (Jump | JumpDword)))
+		suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	      else if (intel_parser.got_a_float == 1)	/* "f..." */
+		suffix = SHORT_MNEM_SUFFIX;
+	      else
+		suffix = LONG_MNEM_SUFFIX;
+	    }
+
+	  else if (prev_token.code == T_FWORD)
+	    {
+	      if (current_templates->start->name[0] == 'l'
+		  && current_templates->start->name[2] == 's'
+		  && current_templates->start->name[3] == 0)
+		suffix = LONG_MNEM_SUFFIX;
+	      else if (!intel_parser.got_a_float)
+		{
+		  if (flag_code == CODE_16BIT)
+		    add_prefix (DATA_PREFIX_OPCODE);
+		  suffix = LONG_DOUBLE_MNEM_SUFFIX;
+		}
+	      else
+		suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+	    }
+
+	  else if (prev_token.code == T_QWORD)
+	    {
+	      if (intel_parser.got_a_float == 1)	/* "f..." */
+		suffix = LONG_MNEM_SUFFIX;
+	      else
+		suffix = QWORD_MNEM_SUFFIX;
+	    }
+
+	  else if (prev_token.code == T_TBYTE)
+	    {
+	      if (intel_parser.got_a_float == 1)
+		suffix = LONG_DOUBLE_MNEM_SUFFIX;
+	      else
+		suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
+	    }
+
+	  else if (prev_token.code == T_XMMWORD)
+	    {
+	      /* XXX ignored for now, but accepted since gcc uses it */
+	      suffix = 0;
+	    }
+
 	  else
-	    i.suffix = LONG_MNEM_SUFFIX;
+	    {
+	      as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
+	      return 0;
+	    }
+
+	  /* Operands for jump/call using 'ptr' notation denote absolute
+	     addresses.  */
+	  if (current_templates->start->opcode_modifier & (Jump | JumpDword))
+	    i.types[this_operand] |= JumpAbsolute;
+
+	  if (current_templates->start->base_opcode == 0x8d /* lea */)
+	    ;
+	  else if (!i.suffix)
+	    i.suffix = suffix;
+	  else if (i.suffix != suffix)
+	    {
+	      as_bad (_("Conflicting operand modifiers"));
+	      return 0;
+	    }
+
 	}
 
-      else if (prev_token.code == T_QWORD)
+      /* e09'  : e10 e09'  */
+      else if (cur_token.code == ':')
 	{
-	  if (intel_parser.got_a_float == 1)	/* "f..." */
-	    i.suffix = LONG_MNEM_SUFFIX;
-	  else
-	    i.suffix = QWORD_MNEM_SUFFIX;
+	  if (prev_token.code != T_REG)
+	    {
+	      /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
+		 segment/group identifier (which we don't have), using comma
+		 as the operand separator there is even less consistent, since
+		 there all branches only have a single operand.  */
+	      if (this_operand != 0
+		  || intel_parser.in_offset
+		  || intel_parser.in_bracket
+		  || (!(current_templates->start->opcode_modifier
+			& (Jump|JumpDword|JumpInterSegment))
+		      && !(current_templates->start->operand_types[0]
+			   & JumpAbsolute)))
+		return intel_match_token (T_NIL);
+	      /* Remember the start of the 2nd operand and terminate 1st
+		 operand here.
+		 XXX This isn't right, yet (when SSSS:OOOO is right operand of
+		 another expression), but it gets at least the simplest case
+		 (a plain number or symbol on the left side) right.  */
+	      intel_parser.next_operand = intel_parser.op_string;
+	      *--intel_parser.op_string = '\0';
+	      return intel_match_token (':');
+	    }
 	}
 
-      else if (prev_token.code == T_XWORD)
-	i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
-
+      /* e09'  Empty  */
       else
+	break;
+
+      intel_match_token (cur_token.code);
+
+    }
+
+  if (in_offset)
+    {
+      --intel_parser.in_offset;
+      if (nregs < 0)
+	nregs = ~nregs;
+      if (NUM_ADDRESS_REGS > nregs)
 	{
-	  as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
+	  as_bad (_("Invalid operand to `OFFSET'"));
 	  return 0;
 	}
+      intel_parser.op_modifier |= 1 << T_OFFSET;
+    }
 
-      intel_match_token (T_PTR);
+  if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
+    i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
+  return 1;
+}
 
-      return (intel_e10 () && intel_e09_1 ());
-    }
+static int
+intel_bracket_expr ()
+{
+  int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
+  const char *start = intel_parser.op_string;
+  int len;
 
-  /* e09  : e10 e09'  */
-  else if (cur_token.code == ':')
+  if (i.op[this_operand].regs)
+    return intel_match_token (T_NIL);
+
+  intel_match_token ('[');
+
+  /* Mark as a memory operand only if it's not already known to be an
+     offset expression.  If it's an offset expression, we need to keep
+     the brace in.  */
+  if (!intel_parser.in_offset)
     {
-      /* Mark as a memory operand only if it's not already known to be an
-	 offset expression.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
-	intel_parser.is_mem = 1;
+      ++intel_parser.in_bracket;
 
-      return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
-    }
+      /* Operands for jump/call inside brackets denote absolute addresses.  */
+      if (current_templates->start->opcode_modifier & (Jump | JumpDword))
+	i.types[this_operand] |= JumpAbsolute;
 
-  /* e09'  Empty  */
+      /* Unfortunately gas always diverged from MASM in a respect that can't
+	 be easily fixed without risking to break code sequences likely to be
+	 encountered (the testsuite even check for this): MASM doesn't consider
+	 an expression inside brackets unconditionally as a memory reference.
+	 When that is e.g. a constant, an offset expression, or the sum of the
+	 two, this is still taken as a constant load. gas, however, always
+	 treated these as memory references. As a compromise, we'll try to make
+	 offset expressions inside brackets work the MASM way (since that's
+	 less likely to be found in real world code), but make constants alone
+	 continue to work the traditional gas way. In either case, issue a
+	 warning.  */
+      intel_parser.op_modifier &= ~was_offset;
+    }
   else
-    return 1;
+      strcat (intel_parser.disp, "[");
+
+  /* Add a '+' to the displacement string if necessary.  */
+  if (*intel_parser.disp != '\0'
+      && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
+    strcat (intel_parser.disp, "+");
+
+  if (intel_expr ()
+      && (len = intel_parser.op_string - start - 1,
+	  intel_match_token (']')))
+    {
+      /* Preserve brackets when the operand is an offset expression.  */
+      if (intel_parser.in_offset)
+	strcat (intel_parser.disp, "]");
+      else
+	{
+	  --intel_parser.in_bracket;
+	  if (i.base_reg || i.index_reg)
+	    intel_parser.is_mem = 1;
+	  if (!intel_parser.is_mem)
+	    {
+	      if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
+		/* Defer the warning until all of the operand was parsed.  */
+		intel_parser.is_mem = -1;
+	      else if (!quiet_warnings)
+		as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
+	    }
+	}
+      intel_parser.op_modifier |= was_offset;
+
+      return 1;
+    }
+  return 0;
 }
 
 /* e10	e11 e10'
@@ -5682,45 +6623,16 @@ intel_e09_1 ()
 static int
 intel_e10 ()
 {
-  return (intel_e11 () && intel_e10_1 ());
-}
+  if (!intel_e11 ())
+    return 0;
 
-static int
-intel_e10_1 ()
-{
-  /* e10'  [ expr ]  e10'  */
-  if (cur_token.code == '[')
+  while (cur_token.code == '[')
     {
-      intel_match_token ('[');
-
-      /* Mark as a memory operand only if it's not already known to be an
-	 offset expression.  If it's an offset expression, we need to keep
-	 the brace in.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
-	intel_parser.is_mem = 1;
-      else
-	strcat (intel_parser.disp, "[");
-
-      /* Add a '+' to the displacement string if necessary.  */
-      if (*intel_parser.disp != '\0'
-	  && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
-	strcat (intel_parser.disp, "+");
-
-      if (intel_expr () && intel_match_token (']'))
-	{
-	  /* Preserve brackets when the operand is an offset expression.  */
-	  if (intel_parser.op_modifier == OFFSET_FLAT)
-	    strcat (intel_parser.disp, "]");
-
-	  return intel_e10_1 ();
-	}
-      else
+      if (!intel_bracket_expr ())
 	return 0;
     }
 
-  /* e10'  Empty  */
-  else
-    return 1;
+  return 1;
 }
 
 /* e11	( expr )
@@ -5728,8 +6640,11 @@ intel_e10_1 ()
 	| BYTE
 	| WORD
 	| DWORD
+	| FWORD
 	| QWORD
-	| XWORD
+	| TBYTE
+	| OWORD
+	| XMMWORD
 	| $
 	| .
 	| register
@@ -5738,9 +6653,10 @@ intel_e10_1 ()
 static int
 intel_e11 ()
 {
-  /* e11  ( expr ) */
-  if (cur_token.code == '(')
+  switch (cur_token.code)
     {
+    /* e11  ( expr ) */
+    case '(':
       intel_match_token ('(');
       strcat (intel_parser.disp, "(");
 
@@ -5749,292 +6665,284 @@ intel_e11 ()
 	  strcat (intel_parser.disp, ")");
 	  return 1;
 	}
-      else
-	return 0;
-    }
-
-  /* e11  [ expr ] */
-  else if (cur_token.code == '[')
-    {
-      intel_match_token ('[');
-
-      /* Mark as a memory operand only if it's not already known to be an
-	 offset expression.  If it's an offset expression, we need to keep
-	 the brace in.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
-	intel_parser.is_mem = 1;
-      else
-	strcat (intel_parser.disp, "[");
-
-      /* Operands for jump/call inside brackets denote absolute addresses.  */
-      if (current_templates->start->opcode_modifier & Jump
-	  || current_templates->start->opcode_modifier & JumpDword
-	  || current_templates->start->opcode_modifier & JumpByte
-	  || current_templates->start->opcode_modifier & JumpInterSegment)
-	i.types[this_operand] |= JumpAbsolute;
-
-      /* Add a '+' to the displacement string if necessary.  */
-      if (*intel_parser.disp != '\0'
-	  && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
-	strcat (intel_parser.disp, "+");
-
-      if (intel_expr () && intel_match_token (']'))
-	{
-	  /* Preserve brackets when the operand is an offset expression.  */
-	  if (intel_parser.op_modifier == OFFSET_FLAT)
-	    strcat (intel_parser.disp, "]");
-
-	  return 1;
-	}
-      else
-	return 0;
-    }
+      return 0;
 
-  /* e11  BYTE
-	  | WORD
-	  | DWORD
-	  | QWORD
-	  | XWORD  */
-  else if (cur_token.code == T_BYTE
-	   || cur_token.code == T_WORD
-	   || cur_token.code == T_DWORD
-	   || cur_token.code == T_QWORD
-	   || cur_token.code == T_XWORD)
-    {
-      intel_match_token (cur_token.code);
+    /* e11  [ expr ] */
+    case '[':
+      return intel_bracket_expr ();
 
-      return 1;
-    }
-
-  /* e11  $
-	  | .  */
-  else if (cur_token.code == '$' || cur_token.code == '.')
-    {
+    /* e11  $
+	    | .  */
+    case '.':
       strcat (intel_parser.disp, cur_token.str);
       intel_match_token (cur_token.code);
 
       /* Mark as a memory operand only if it's not already known to be an
 	 offset expression.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
+      if (!intel_parser.in_offset)
 	intel_parser.is_mem = 1;
 
       return 1;
-    }
 
-  /* e11  register  */
-  else if (cur_token.code == T_REG)
-    {
-      const reg_entry *reg = intel_parser.reg = cur_token.reg;
+    /* e11  register  */
+    case T_REG:
+      {
+	const reg_entry *reg = intel_parser.reg = cur_token.reg;
 
-      intel_match_token (T_REG);
+	intel_match_token (T_REG);
 
-      /* Check for segment change.  */
-      if (cur_token.code == ':')
-	{
-	  if (reg->reg_type & (SReg2 | SReg3))
-	    {
-	      switch (reg->reg_num)
-		{
-		case 0:
-		  i.seg[i.mem_operands] = &es;
-		  break;
-		case 1:
-		  i.seg[i.mem_operands] = &cs;
-		  break;
-		case 2:
-		  i.seg[i.mem_operands] = &ss;
-		  break;
-		case 3:
-		  i.seg[i.mem_operands] = &ds;
-		  break;
-		case 4:
-		  i.seg[i.mem_operands] = &fs;
-		  break;
-		case 5:
-		  i.seg[i.mem_operands] = &gs;
-		  break;
-		}
-	    }
-	  else
-	    {
-	      as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
-	      return 0;
-	    }
-	}
+	/* Check for segment change.  */
+	if (cur_token.code == ':')
+	  {
+	    if (!(reg->reg_type & (SReg2 | SReg3)))
+	      {
+		as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
+		return 0;
+	      }
+	    else if (i.seg[i.mem_operands])
+	      as_warn (_("Extra segment override ignored"));
+	    else
+	      {
+		if (!intel_parser.in_offset)
+		  intel_parser.is_mem = 1;
+		switch (reg->reg_num)
+		  {
+		  case 0:
+		    i.seg[i.mem_operands] = &es;
+		    break;
+		  case 1:
+		    i.seg[i.mem_operands] = &cs;
+		    break;
+		  case 2:
+		    i.seg[i.mem_operands] = &ss;
+		    break;
+		  case 3:
+		    i.seg[i.mem_operands] = &ds;
+		    break;
+		  case 4:
+		    i.seg[i.mem_operands] = &fs;
+		    break;
+		  case 5:
+		    i.seg[i.mem_operands] = &gs;
+		    break;
+		  }
+	      }
+	  }
 
-      /* Not a segment register. Check for register scaling.  */
-      else if (cur_token.code == '*')
-	{
-	  if (!intel_parser.is_mem)
-	    {
-	      as_bad (_("Register scaling only allowed in memory operands."));
-	      return 0;
-	    }
+	/* Not a segment register. Check for register scaling.  */
+	else if (cur_token.code == '*')
+	  {
+	    if (!intel_parser.in_bracket)
+	      {
+		as_bad (_("Register scaling only allowed in memory operands"));
+		return 0;
+	      }
 
-	  /* What follows must be a valid scale.  */
-	  if (intel_match_token ('*')
-	      && strchr ("01248", *cur_token.str))
-	    {
-	      i.index_reg = reg;
-	      i.types[this_operand] |= BaseIndex;
+	    if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
+	      reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+	    else if (i.index_reg)
+	      reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
 
-	      /* Set the scale after setting the register (otherwise,
-		 i386_scale will complain)  */
-	      i386_scale (cur_token.str);
-	      intel_match_token (T_CONST);
-	    }
-	  else
-	    {
-	      as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
-		      cur_token.str);
-	      return 0;
-	    }
-	}
+	    /* What follows must be a valid scale.  */
+	    intel_match_token ('*');
+	    i.index_reg = reg;
+	    i.types[this_operand] |= BaseIndex;
 
-      /* No scaling. If this is a memory operand, the register is either a
-	 base register (first occurrence) or an index register (second
-	 occurrence).  */
-      else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
-	{
-	  if (i.base_reg && i.index_reg)
-	    {
-	      as_bad (_("Too many register references in memory operand.\n"));
+	    /* Set the scale after setting the register (otherwise,
+	       i386_scale will complain)  */
+	    if (cur_token.code == '+' || cur_token.code == '-')
+	      {
+		char *str, sign = cur_token.code;
+		intel_match_token (cur_token.code);
+		if (cur_token.code != T_CONST)
+		  {
+		    as_bad (_("Syntax error: Expecting a constant, got `%s'"),
+			    cur_token.str);
+		    return 0;
+		  }
+		str = (char *) xmalloc (strlen (cur_token.str) + 2);
+		strcpy (str + 1, cur_token.str);
+		*str = sign;
+		if (!i386_scale (str))
+		  return 0;
+		free (str);
+	      }
+	    else if (!i386_scale (cur_token.str))
 	      return 0;
-	    }
-
-	  if (i.base_reg == NULL)
-	    i.base_reg = reg;
-	  else
-	    i.index_reg = reg;
+	    intel_match_token (cur_token.code);
+	  }
 
-	  i.types[this_operand] |= BaseIndex;
-	}
+	/* No scaling. If this is a memory operand, the register is either a
+	   base register (first occurrence) or an index register (second
+	   occurrence).  */
+	else if (intel_parser.in_bracket)
+	  {
 
-      /* Offset modifier. Add the register to the displacement string to be
-	 parsed as an immediate expression after we're done.  */
-      else if (intel_parser.op_modifier == OFFSET_FLAT)
-	strcat (intel_parser.disp, reg->reg_name);
+	    if (!i.base_reg)
+	      i.base_reg = reg;
+	    else if (!i.index_reg)
+	      i.index_reg = reg;
+	    else
+	      {
+		as_bad (_("Too many register references in memory operand"));
+		return 0;
+	      }
 
-      /* It's neither base nor index nor offset.  */
-      else
-	{
-	  i.types[this_operand] |= reg->reg_type & ~BaseIndex;
-	  i.op[this_operand].regs = reg;
-	  i.reg_operands++;
-	}
+	    i.types[this_operand] |= BaseIndex;
+	  }
 
-      /* Since registers are not part of the displacement string (except
-	 when we're parsing offset operands), we may need to remove any
-	 preceding '+' from the displacement string.  */
-      if (*intel_parser.disp != '\0'
-	  && intel_parser.op_modifier != OFFSET_FLAT)
-	{
-	  char *s = intel_parser.disp;
-	  s += strlen (s) - 1;
-	  if (*s == '+')
-	    *s = '\0';
-	}
+	/* It's neither base nor index.  */
+	else if (!intel_parser.in_offset && !intel_parser.is_mem)
+	  {
+	    i.types[this_operand] |= reg->reg_type & ~BaseIndex;
+	    i.op[this_operand].regs = reg;
+	    i.reg_operands++;
+	  }
+	else
+	  {
+	    as_bad (_("Invalid use of register"));
+	    return 0;
+	  }
 
-      return 1;
-    }
+	/* Since registers are not part of the displacement string (except
+	   when we're parsing offset operands), we may need to remove any
+	   preceding '+' from the displacement string.  */
+	if (*intel_parser.disp != '\0'
+	    && !intel_parser.in_offset)
+	  {
+	    char *s = intel_parser.disp;
+	    s += strlen (s) - 1;
+	    if (*s == '+')
+	      *s = '\0';
+	  }
 
-  /* e11  id  */
-  else if (cur_token.code == T_ID)
-    {
-      /* Add the identifier to the displacement string.  */
-      strcat (intel_parser.disp, cur_token.str);
-      intel_match_token (T_ID);
+	return 1;
+      }
 
-      /* The identifier represents a memory reference only if it's not
-	 preceded by an offset modifier.  */
-      if (intel_parser.op_modifier != OFFSET_FLAT)
-	intel_parser.is_mem = 1;
+    /* e11  BYTE
+	    | WORD
+	    | DWORD
+	    | FWORD
+	    | QWORD
+	    | TBYTE
+	    | OWORD
+	    | XMMWORD  */
+    case T_BYTE:
+    case T_WORD:
+    case T_DWORD:
+    case T_FWORD:
+    case T_QWORD:
+    case T_TBYTE:
+    case T_XMMWORD:
+      intel_match_token (cur_token.code);
 
-      return 1;
-    }
+      if (cur_token.code == T_PTR)
+	return 1;
 
-  /* e11  constant  */
-  else if (cur_token.code == T_CONST
-	   || cur_token.code == '-'
-	   || cur_token.code == '+')
-    {
-      char *save_str;
+      /* It must have been an identifier.  */
+      intel_putback_token ();
+      cur_token.code = T_ID;
+      /* FALLTHRU */
 
-      /* Allow constants that start with `+' or `-'.  */
-      if (cur_token.code == '-' || cur_token.code == '+')
+    /* e11  id
+	    | constant  */
+    case T_ID:
+      if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
 	{
-	  strcat (intel_parser.disp, cur_token.str);
-	  intel_match_token (cur_token.code);
-	  if (cur_token.code != T_CONST)
-	    {
-	      as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
-		      cur_token.str);
-	      return 0;
-	    }
-	}
+	  symbolS *symbolP;
 
-      save_str = (char *) malloc (strlen (cur_token.str) + 1);
-      if (save_str == NULL)
-	abort ();
-      strcpy (save_str, cur_token.str);
+	  /* The identifier represents a memory reference only if it's not
+	     preceded by an offset modifier and if it's not an equate.  */
+	  symbolP = symbol_find(cur_token.str);
+	  if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
+	    intel_parser.is_mem = 1;
+	}
+	/* FALLTHRU */
 
-      /* Get the next token to check for register scaling.  */
-      intel_match_token (cur_token.code);
+    case T_CONST:
+    case '-':
+    case '+':
+      {
+	char *save_str, sign = 0;
 
-      /* Check if this constant is a scaling factor for an index register.  */
-      if (cur_token.code == '*')
-	{
-	  if (intel_match_token ('*') && cur_token.code == T_REG)
-	    {
-	      if (!intel_parser.is_mem)
-		{
-		  as_bad (_("Register scaling only allowed in memory operands."));
-		  return 0;
-		}
+	/* Allow constants that start with `+' or `-'.  */
+	if (cur_token.code == '-' || cur_token.code == '+')
+	  {
+	    sign = cur_token.code;
+	    intel_match_token (cur_token.code);
+	    if (cur_token.code != T_CONST)
+	      {
+		as_bad (_("Syntax error: Expecting a constant, got `%s'"),
+			cur_token.str);
+		return 0;
+	      }
+	  }
 
-	      /* The constant is followed by `* reg', so it must be
-		 a valid scale.  */
-	      if (strchr ("01248", *save_str))
-		{
-		  i.index_reg = cur_token.reg;
-		  i.types[this_operand] |= BaseIndex;
-
-		  /* Set the scale after setting the register (otherwise,
-		     i386_scale will complain)  */
-		  i386_scale (save_str);
-		  intel_match_token (T_REG);
-
-		  /* Since registers are not part of the displacement
-		     string, we may need to remove any preceding '+' from
-		     the displacement string.  */
-		  if (*intel_parser.disp != '\0')
-		    {
-		      char *s = intel_parser.disp;
-		      s += strlen (s) - 1;
-		      if (*s == '+')
-			*s = '\0';
-		    }
+	save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
+	strcpy (save_str + !!sign, cur_token.str);
+	if (sign)
+	  *save_str = sign;
 
-		  free (save_str);
+	/* Get the next token to check for register scaling.  */
+	intel_match_token (cur_token.code);
 
-		  return 1;
-		}
-	      else
-		return 0;
-	    }
+	/* Check if this constant is a scaling factor for an index register.  */
+	if (cur_token.code == '*')
+	  {
+	    if (intel_match_token ('*') && cur_token.code == T_REG)
+	      {
+		const reg_entry *reg = cur_token.reg;
+
+		if (!intel_parser.in_bracket)
+		  {
+		    as_bad (_("Register scaling only allowed in memory operands"));
+		    return 0;
+		  }
+
+		if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
+		  reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
+		else if (i.index_reg)
+		  reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
+
+		/* The constant is followed by `* reg', so it must be
+		   a valid scale.  */
+		i.index_reg = reg;
+		i.types[this_operand] |= BaseIndex;
+
+		/* Set the scale after setting the register (otherwise,
+		   i386_scale will complain)  */
+		if (!i386_scale (save_str))
+		  return 0;
+		intel_match_token (T_REG);
+
+		/* Since registers are not part of the displacement
+		   string, we may need to remove any preceding '+' from
+		   the displacement string.  */
+		if (*intel_parser.disp != '\0')
+		  {
+		    char *s = intel_parser.disp;
+		    s += strlen (s) - 1;
+		    if (*s == '+')
+		      *s = '\0';
+		  }
+
+		free (save_str);
+
+		return 1;
+	      }
 
-	  /* The constant was not used for register scaling. Since we have
-	     already consumed the token following `*' we now need to put it
-	     back in the stream.  */
-	  else
+	    /* The constant was not used for register scaling. Since we have
+	       already consumed the token following `*' we now need to put it
+	       back in the stream.  */
 	    intel_putback_token ();
-	}
+	  }
 
-      /* Add the constant to the displacement string.  */
-      strcat (intel_parser.disp, save_str);
-      free (save_str);
+	/* Add the constant to the displacement string.  */
+	strcat (intel_parser.disp, save_str);
+	free (save_str);
 
-      return 1;
+	return 1;
+      }
     }
 
   as_bad (_("Unrecognized token '%s'"), cur_token.str);
@@ -6054,7 +6962,7 @@ intel_match_token (code)
     }
   else
     {
-      as_bad (_("Unexpected token `%s'\n"), cur_token.str);
+      as_bad (_("Unexpected token `%s'"), cur_token.str);
       return 0;
     }
 }
@@ -6091,9 +6999,7 @@ intel_get_token ()
 
   /* The new token cannot be larger than the remainder of the operand
      string.  */
-  new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
-  if (new_token.str == NULL)
-    abort ();
+  new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
   new_token.str[0] = '\0';
 
   if (strchr ("0123456789", *intel_parser.op_string))
@@ -6115,26 +7021,15 @@ intel_get_token ()
 	new_token.code = T_ID;
     }
 
-  else if (strchr ("+-/*:[]()", *intel_parser.op_string))
+  else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
     {
-      new_token.code = *intel_parser.op_string;
-      new_token.str[0] = *intel_parser.op_string;
-      new_token.str[1] = '\0';
-    }
+      size_t len = end_op - intel_parser.op_string;
 
-  else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
-	   && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
-    {
       new_token.code = T_REG;
       new_token.reg = reg;
 
-      if (*intel_parser.op_string == REGISTER_PREFIX)
-	{
-	  new_token.str[0] = REGISTER_PREFIX;
-	  new_token.str[1] = '\0';
-	}
-
-      strcat (new_token.str, reg->reg_name);
+      memcpy (new_token.str, intel_parser.op_string, len);
+      new_token.str[len] = '\0';
     }
 
   else if (is_identifier_char (*intel_parser.op_string))
@@ -6146,8 +7041,8 @@ intel_get_token ()
 	 Otherwise, it's operator '.' followed by an expression.  */
       if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
 	{
-	  new_token.code = *q;
-	  new_token.str[0] = *q;
+	  new_token.code = '.';
+	  new_token.str[0] = '.';
 	  new_token.str[1] = '\0';
 	}
       else
@@ -6156,7 +7051,28 @@ intel_get_token ()
 	    *p++ = *q++;
 	  *p = '\0';
 
-	  if (strcasecmp (new_token.str, "BYTE") == 0)
+	  if (strcasecmp (new_token.str, "NOT") == 0)
+	    new_token.code = '~';
+
+	  else if (strcasecmp (new_token.str, "MOD") == 0)
+	    new_token.code = '%';
+
+	  else if (strcasecmp (new_token.str, "AND") == 0)
+	    new_token.code = '&';
+
+	  else if (strcasecmp (new_token.str, "OR") == 0)
+	    new_token.code = '|';
+
+	  else if (strcasecmp (new_token.str, "XOR") == 0)
+	    new_token.code = '^';
+
+	  else if (strcasecmp (new_token.str, "SHL") == 0)
+	    new_token.code = T_SHL;
+
+	  else if (strcasecmp (new_token.str, "SHR") == 0)
+	    new_token.code = T_SHR;
+
+	  else if (strcasecmp (new_token.str, "BYTE") == 0)
 	    new_token.code = T_BYTE;
 
 	  else if (strcasecmp (new_token.str, "WORD") == 0)
@@ -6165,11 +7081,20 @@ intel_get_token ()
 	  else if (strcasecmp (new_token.str, "DWORD") == 0)
 	    new_token.code = T_DWORD;
 
+	  else if (strcasecmp (new_token.str, "FWORD") == 0)
+	    new_token.code = T_FWORD;
+
 	  else if (strcasecmp (new_token.str, "QWORD") == 0)
 	    new_token.code = T_QWORD;
 
-	  else if (strcasecmp (new_token.str, "XWORD") == 0)
-	    new_token.code = T_XWORD;
+	  else if (strcasecmp (new_token.str, "TBYTE") == 0
+		   /* XXX remove (gcc still uses it) */
+		   || strcasecmp (new_token.str, "XWORD") == 0)
+	    new_token.code = T_TBYTE;
+
+	  else if (strcasecmp (new_token.str, "XMMWORD") == 0
+		   || strcasecmp (new_token.str, "OWORD") == 0)
+	    new_token.code = T_XMMWORD;
 
 	  else if (strcasecmp (new_token.str, "PTR") == 0)
 	    new_token.code = T_PTR;
@@ -6190,15 +7115,37 @@ intel_get_token ()
 
 	  /* ??? This is not mentioned in the MASM grammar.  */
 	  else if (strcasecmp (new_token.str, "FLAT") == 0)
-	    new_token.code = T_OFFSET;
+	    {
+	      new_token.code = T_OFFSET;
+	      if (*q == ':')
+		strcat (new_token.str, ":");
+	      else
+		as_bad (_("`:' expected"));
+	    }
 
 	  else
 	    new_token.code = T_ID;
 	}
     }
 
+  else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
+    {
+      new_token.code = *intel_parser.op_string;
+      new_token.str[0] = *intel_parser.op_string;
+      new_token.str[1] = '\0';
+    }
+
+  else if (strchr ("<>", *intel_parser.op_string)
+	   && *intel_parser.op_string == *(intel_parser.op_string + 1))
+    {
+      new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
+      new_token.str[0] = *intel_parser.op_string;
+      new_token.str[1] = *intel_parser.op_string;
+      new_token.str[2] = '\0';
+    }
+
   else
-    as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
+    as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
 
   intel_parser.op_string += strlen (new_token.str);
   cur_token = new_token;
@@ -6209,8 +7156,11 @@ intel_get_token ()
 static void
 intel_putback_token ()
 {
-  intel_parser.op_string -= strlen (cur_token.str);
-  free (cur_token.str);
+  if (cur_token.code != T_NIL)
+    {
+      intel_parser.op_string -= strlen (cur_token.str);
+      free (cur_token.str);
+    }
   cur_token = prev_token;
 
   /* Forget prev_token.  */
@@ -6224,21 +7174,44 @@ tc_x86_regname_to_dw2regnum (const char *regname)
 {
   unsigned int regnum;
   unsigned int regnames_count;
-  char *regnames_32[] =
+  static const char *const regnames_32[] =
     {
       "eax", "ecx", "edx", "ebx",
       "esp", "ebp", "esi", "edi",
-      "eip"
+      "eip", "eflags", NULL,
+      "st0", "st1", "st2", "st3",
+      "st4", "st5", "st6", "st7",
+      NULL, NULL,
+      "xmm0", "xmm1", "xmm2", "xmm3",
+      "xmm4", "xmm5", "xmm6", "xmm7",
+      "mm0", "mm1", "mm2", "mm3",
+      "mm4", "mm5", "mm6", "mm7",
+      "fcw", "fsw", "mxcsr",
+      "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
+      "tr", "ldtr"
     };
-  char *regnames_64[] =
+  static const char *const regnames_64[] =
     {
-      "rax", "rbx", "rcx", "rdx",
-      "rdi", "rsi", "rbp", "rsp",
-      "r8", "r9", "r10", "r11",
+      "rax", "rdx", "rcx", "rbx",
+      "rsi", "rdi", "rbp", "rsp",
+      "r8",  "r9",  "r10", "r11",
       "r12", "r13", "r14", "r15",
-      "rip"
+      "rip",
+      "xmm0",  "xmm1",  "xmm2",  "xmm3",
+      "xmm4",  "xmm5",  "xmm6",  "xmm7",
+      "xmm8",  "xmm9",  "xmm10", "xmm11",
+      "xmm12", "xmm13", "xmm14", "xmm15",
+      "st0", "st1", "st2", "st3",
+      "st4", "st5", "st6", "st7",
+      "mm0", "mm1", "mm2", "mm3",
+      "mm4", "mm5", "mm6", "mm7",
+      "rflags",
+      "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
+      "fs.base", "gs.base", NULL, NULL,
+      "tr", "ldtr",
+      "mxcsr", "fcw", "fsw"
     };
-  char **regnames;
+  const char *const *regnames;
 
   if (flag_code == CODE_64BIT)
     {
@@ -6252,7 +7225,8 @@ tc_x86_regname_to_dw2regnum (const char *regname)
     }
 
   for (regnum = 0; regnum < regnames_count; regnum++)
-    if (strcmp (regname, regnames[regnum]) == 0)
+    if (regnames[regnum] != NULL
+	&& strcmp (regname, regnames[regnum]) == 0)
       return regnum;
 
   return -1;
@@ -6270,3 +7244,95 @@ tc_x86_frame_initial_instructions (void)
   cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
   cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
 }
+
+int
+i386_elf_section_type (const char *str, size_t len)
+{
+  if (flag_code == CODE_64BIT
+      && len == sizeof ("unwind") - 1
+      && strncmp (str, "unwind", 6) == 0)
+    return SHT_X86_64_UNWIND;
+
+  return -1;
+}
+
+#ifdef TE_PE
+void
+tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
+{
+  expressionS expr;
+
+  expr.X_op = O_secrel;
+  expr.X_add_symbol = symbol;
+  expr.X_add_number = 0;
+  emit_expr (&expr, size);
+}
+#endif
+
+#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+/* For ELF on x86-64, add support for SHF_X86_64_LARGE.  */
+
+int
+x86_64_section_letter (int letter, char **ptr_msg)
+{
+  if (flag_code == CODE_64BIT)
+    {
+      if (letter == 'l')
+	return SHF_X86_64_LARGE;
+
+      *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
+     }
+  else
+   *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
+  return -1;
+}
+
+int
+x86_64_section_word (char *str, size_t len)
+{
+  if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
+    return SHF_X86_64_LARGE;
+
+  return -1;
+}
+
+static void
+handle_large_common (int small ATTRIBUTE_UNUSED)
+{
+  if (flag_code != CODE_64BIT)
+    {
+      s_comm_internal (0, elf_common_parse);
+      as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
+    }
+  else
+    {
+      static segT lbss_section;
+      asection *saved_com_section_ptr = elf_com_section_ptr;
+      asection *saved_bss_section = bss_section;
+
+      if (lbss_section == NULL)
+	{
+	  flagword applicable;
+	  segT seg = now_seg;
+	  subsegT subseg = now_subseg;
+
+	  /* The .lbss section is for local .largecomm symbols.  */
+	  lbss_section = subseg_new (".lbss", 0);
+	  applicable = bfd_applicable_section_flags (stdoutput);
+	  bfd_set_section_flags (stdoutput, lbss_section,
+				 applicable & SEC_ALLOC);
+	  seg_info (lbss_section)->bss = 1;
+
+	  subseg_set (seg, subseg);
+	}
+
+      elf_com_section_ptr = &_bfd_elf_large_com_section;
+      bss_section = lbss_section;
+
+      s_comm_internal (0, elf_common_parse);
+
+      elf_com_section_ptr = saved_com_section_ptr;
+      bss_section = saved_bss_section;
+    }
+}
+#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h
index 14b522b56495..98517041dadd 100644
--- a/gas/config/tc-i386.h
+++ b/gas/config/tc-i386.h
@@ -1,6 +1,6 @@
 /* tc-i386.h -- Header file for tc-i386.c
    Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003, 2004
+   2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,29 +17,19 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef TC_I386
 #define TC_I386 1
 
-#ifndef BFD_ASSEMBLER
-#error So, do you know what you are doing?
-#endif
-
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
 
 #define TARGET_BYTES_BIG_ENDIAN	0
 
-#ifdef TE_LYNX
-#define TARGET_FORMAT		"coff-i386-lynx"
-#endif
-
 #define TARGET_ARCH		bfd_arch_i386
 #define TARGET_MACH		(i386_mach ())
-extern unsigned long i386_mach PARAMS ((void));
+extern unsigned long i386_mach (void);
 
 #ifdef TE_FreeBSD
 #define AOUT_TARGET_FORMAT	"a.out-i386-freebsd"
@@ -65,7 +55,10 @@ extern unsigned long i386_mach PARAMS ((void));
 
 #ifdef TE_FreeBSD
 #define ELF_TARGET_FORMAT	"elf32-i386-freebsd"
+#elif defined (TE_VXWORKS)
+#define ELF_TARGET_FORMAT	"elf32-i386-vxworks"
 #endif
+
 #ifndef ELF_TARGET_FORMAT
 #define ELF_TARGET_FORMAT	"elf32-i386"
 #endif
@@ -95,6 +88,9 @@ extern void i386_elf_emit_arch_note PARAMS ((void));
 extern const char extra_symbol_chars[];
 #define tc_symbol_chars extra_symbol_chars
 
+extern const char *i386_comment_chars;
+#define tc_comment_chars i386_comment_chars
+
 #define MAX_OPERANDS 3		/* max operands per insn */
 #define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
 #define MAX_MEMORY_OPERANDS 2	/* max memory refs per insn (string ops) */
@@ -145,18 +141,6 @@ extern const char extra_symbol_chars[];
 
 #define END_OF_INSN '\0'
 
-/* Intel Syntax */
-/* Values 0-4 map onto scale factor */
-#define BYTE_PTR     0
-#define WORD_PTR     1
-#define DWORD_PTR    2
-#define QWORD_PTR    3
-#define XWORD_PTR    4
-#define SHORT        5
-#define OFFSET_FLAT  6
-#define FLAT         7
-#define NONE_FOUND   8
-
 typedef struct
 {
   /* instruction name sans width suffix ("mov" for movl insns) */
@@ -190,18 +174,26 @@ typedef struct
 #define CpuAthlon	0x200	/* AMD Athlon or better required*/
 #define CpuSledgehammer 0x400	/* Sledgehammer or better required */
 #define CpuMMX		0x800	/* MMX support required */
-#define CpuSSE	       0x1000	/* Streaming SIMD extensions required */
-#define CpuSSE2	       0x2000	/* Streaming SIMD extensions 2 required */
-#define Cpu3dnow       0x4000	/* 3dnow! support required */
-#define CpuPNI	       0x8000	/* Prescott New Instructions required */
-#define CpuPadLock    0x10000	/* VIA PadLock required */
+#define CpuMMX2	       0x1000	/* extended MMX support (with SSE or 3DNow!Ext) required */
+#define CpuSSE	       0x2000	/* Streaming SIMD extensions required */
+#define CpuSSE2	       0x4000	/* Streaming SIMD extensions 2 required */
+#define Cpu3dnow       0x8000	/* 3dnow! support required */
+#define Cpu3dnowA     0x10000	/* 3dnow!Extensions support required */
+#define CpuSSE3	      0x20000	/* Streaming SIMD extensions 3 required */
+#define CpuPNI	      CpuSSE3	/* Prescott New Instructions required */
+#define CpuPadLock    0x40000	/* VIA PadLock required */
+#define CpuSVME	      0x80000	/* AMD Secure Virtual Machine Ext-s required */
+#define CpuVMX	     0x100000	/* VMX Instructions required */
+#define CpuMNI	     0x200000	/* Merom New Instructions required */
 
   /* These flags are set by gas depending on the flag_code.  */
 #define Cpu64	     0x4000000   /* 64bit support required  */
 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
 
   /* The default value for unknown CPUs - enable all features to avoid problems.  */
-#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuSledgehammer|CpuMMX|CpuSSE|CpuSSE2|CpuPNI|Cpu3dnow|CpuK6|CpuAthlon|CpuPadLock)
+#define CpuUnknownFlags (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
+	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI|CpuVMX \
+	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuAthlon|CpuPadLock|CpuSVME|CpuMNI)
 
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of
@@ -399,14 +391,14 @@ arch_entry;
 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 #endif
 
-#ifndef LEX_AT
+#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT)
 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES)
 extern void x86_cons PARAMS ((expressionS *, int));
+#endif
 
 #define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP)
 extern void x86_cons_fix_new
   PARAMS ((fragS *, unsigned int, unsigned int, expressionS *));
-#endif
 
 #define DIFF_EXPR_OK    /* foo-. gets turned into PC relative relocs */
 
@@ -418,7 +410,7 @@ void i386_validate_fix PARAMS ((struct fix *));
 #define tc_fix_adjustable(X)  tc_i386_fix_adjustable(X)
 extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* ELF wants external syms kept, as does PE COFF.  */
@@ -446,7 +438,8 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
    || (FIX)->fx_r_type == BFD_RELOC_386_GOTPC		\
    || TC_FORCE_RELOCATION (FIX))
 
-#define md_operand(x)
+extern int i386_parse_name (char *, expressionS *, char *);
+#define md_parse_name(s, e, m, c) i386_parse_name (s, e, c)
 
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
@@ -500,4 +493,22 @@ extern int tc_x86_regname_to_dw2regnum PARAMS ((const char *regname));
 #define tc_cfi_frame_initial_instructions tc_x86_frame_initial_instructions
 extern void tc_x86_frame_initial_instructions PARAMS ((void));
 
+#define md_elf_section_type(str,len) i386_elf_section_type (str, len)
+extern int i386_elf_section_type PARAMS ((const char *, size_t len));
+
+/* Support for SHF_X86_64_LARGE */
+extern int x86_64_section_word PARAMS ((char *, size_t));
+extern int x86_64_section_letter PARAMS ((int letter, char **ptr_msg));
+#define md_elf_section_letter(LETTER, PTR_MSG)	x86_64_section_letter (LETTER, PTR_MSG)
+#define md_elf_section_word(STR, LEN)		x86_64_section_word (STR, LEN)
+
+#ifdef TE_PE
+
+#define O_secrel O_md1
+
+#define TC_DWARF2_EMIT_OFFSET  tc_pe_dwarf2_emit_offset
+void tc_pe_dwarf2_emit_offset (symbolS *, unsigned int);
+
+#endif /* TE_PE */
+
 #endif /* TC_I386 */
diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c
index c65a92dbd61d..4a87c540576b 100644
--- a/gas/config/tc-i860.c
+++ b/gas/config/tc-i860.c
@@ -19,7 +19,7 @@
 
    You should have received a copy of the GNU General Public License along
    with GAS; see the file COPYING.  If not, write to the Free Software
-   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include <string.h>
@@ -1338,7 +1338,7 @@ obtain_reloc_for_imm16 (fixS *fix, long *val)
    we will have to generate a reloc entry.  */
 
 void
-md_apply_fix3 (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *buf;
   long val = *valP;
diff --git a/gas/config/tc-i860.h b/gas/config/tc-i860.h
index 4d0229d2e90d..11c36b5acc26 100644
--- a/gas/config/tc-i860.h
+++ b/gas/config/tc-i860.h
@@ -1,5 +1,5 @@
 /* tc-i860.h -- Header file for the i860.
-   Copyright 1991, 1992, 1995, 1998, 2000, 2001, 2002
+   Copyright 1991, 1992, 1995, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    Brought back from the dead and completely reworked
@@ -19,15 +19,11 @@
 
    You should have received a copy of the GNU General Public License along
    with GAS; see the file COPYING.  If not, write to the Free Software
-   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #ifndef TC_I860
 #define TC_I860 1
 
-#ifndef BFD_ASSEMBLER
-#error i860 support requires BFD_ASSEMBLER
-#endif
-
 enum i860_fix_info
 {
   OP_NONE	 = 0x00000,
@@ -79,7 +75,7 @@ extern int target_big_endian;
 
 #define md_convert_frag(b,s,f)  as_fatal (_("i860_convert_frag\n"));
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c
index d56f28d83f72..a3206bbf2d0e 100644
--- a/gas/config/tc-i960.c
+++ b/gas/config/tc-i960.c
@@ -1,6 +1,6 @@
 /* tc-i960.c - All the i80960-specific stuff
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* See comment on md_parse_option for 80960-specific invocation options.  */
 
@@ -74,32 +74,32 @@
 
 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
 
-#define TC_S_IS_SYSPROC(s)	((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
-#define TC_S_IS_BALNAME(s)	(S_GET_OTHER(s) == N_BALNAME)
-#define TC_S_IS_CALLNAME(s)	(S_GET_OTHER(s) == N_CALLNAME)
-#define TC_S_IS_BADPROC(s)	((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
+#define TC_S_IS_SYSPROC(s)	((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
+#define TC_S_IS_BALNAME(s)	(S_GET_OTHER (s) == N_BALNAME)
+#define TC_S_IS_CALLNAME(s)	(S_GET_OTHER (s) == N_CALLNAME)
+#define TC_S_IS_BADPROC(s)	((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
 
-#define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER((s), (p)+1))
-#define TC_S_GET_SYSPROC(s)	(S_GET_OTHER(s)-1)
+#define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER ((s), (p) + 1))
+#define TC_S_GET_SYSPROC(s)	(S_GET_OTHER (s) - 1)
 
-#define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER((s), N_BALNAME))
-#define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER((s), N_CALLNAME))
+#define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER ((s), N_BALNAME))
+#define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER ((s), N_CALLNAME))
 #define TC_S_FORCE_TO_SYSPROC(s)	{;}
 
 #else /* ! OBJ_A/BOUT */
 #ifdef OBJ_COFF
 
-#define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS(s) == C_SCALL)
-#define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME(s))
-#define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME(s))
-#define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
+#define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS (s) == C_SCALL)
+#define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME (s))
+#define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME (s))
+#define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
 
 #define TC_S_SET_SYSPROC(s, p)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
 #define TC_S_GET_SYSPROC(s)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
 
-#define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME(s))
-#define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME(s))
-#define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS((s), C_SCALL))
+#define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME (s))
+#define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME (s))
+#define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS ((s), C_SCALL))
 
 #else /* ! OBJ_COFF */
 #ifdef OBJ_ELF
@@ -110,7 +110,7 @@
 #define TC_S_IS_BADPROC(s)	0
 
 #define TC_S_SET_SYSPROC(s, p)
-#define TC_S_GET_SYSPROC(s) 0
+#define TC_S_GET_SYSPROC(s)     0
 
 #define TC_S_FORCE_TO_BALNAME(s)
 #define TC_S_FORCE_TO_CALLNAME(s)
@@ -123,76 +123,16 @@
 
 extern char *input_line_pointer;
 
-#if !defined (BFD_ASSEMBLER) && !defined (BFD)
-#ifdef OBJ_COFF
-const int md_reloc_size = sizeof (struct reloc);
-#else /* OBJ_COFF */
-const int md_reloc_size = sizeof (struct relocation_info);
-#endif /* OBJ_COFF */
-#endif
-
 /* Local i80960 routines.  */
 struct memS;
 struct regop;
 
-/* Emit branch-prediction instrumentation code */
-static void brcnt_emit PARAMS ((void));
-/* Return next branch local label */
-static char *brlab_next PARAMS ((void));
-/* Generate COBR instruction */
-static void cobr_fmt PARAMS ((char *[], long, struct i960_opcode *));
-/* Generate CTRL instruction */
-static void ctrl_fmt PARAMS ((char *, long, int));
-/* Emit (internally) binary */
-static char *emit PARAMS ((long));
-/* Break arguments out of comma-separated list */
-static int get_args PARAMS ((char *, char *[]));
-/* Handle COBR or CTRL displacement */
-static void get_cdisp PARAMS ((char *, char *, long, int, int, int));
-/* Find index specification string */
-static char *get_ispec PARAMS ((char *));
-/* Translate text to register number */
-static int get_regnum PARAMS ((char *));
-/* Lexical scan of instruction source */
-static int i_scan PARAMS ((char *, char *[]));
-/* Generate MEMA or MEMB instruction */
-static void mem_fmt PARAMS ((char *[], struct i960_opcode *, int));
-/* Convert MEMA instruction to MEMB format */
-static void mema_to_memb PARAMS ((char *));
-/* Parse an expression */
-static void parse_expr PARAMS ((char *, expressionS *));
-/* Parse and replace a 'ldconst' pseudo-op */
-static int parse_ldconst PARAMS ((char *[]));
-/* Parse a memory operand */
-static void parse_memop PARAMS ((struct memS *, char *, int));
-/* Parse machine-dependent pseudo-op */
-static void parse_po PARAMS ((int));
-/* Parse a register operand */
-static void parse_regop PARAMS ((struct regop *, char *, char));
-/* Generate a REG format instruction */
-static void reg_fmt PARAMS ((char *[], struct i960_opcode *));
-/* "De-optimize" cobr into compare/branch */
-static void relax_cobr PARAMS ((fragS *));
-/* Process '.leafproc' pseudo-op */
-static void s_leafproc PARAMS ((int, char *[]));
-/* Process '.sysproc' pseudo-op */
-static void s_sysproc PARAMS ((int, char *[]));
-/* Will a 'shlo' substitute for a 'ldconst'? */
-static int shift_ok PARAMS ((int));
-/* Give syntax error */
-static void syntax PARAMS ((void));
-/* Target chip supports spec-func register? */
-static int targ_has_sfr PARAMS ((int));
-/* Target chip supports instruction set? */
-static int targ_has_iclass PARAMS ((int));
-
-/* See md_parse_option() for meanings of these options */
-static char norelax;		/* True if -norelax switch seen */
-static char instrument_branches;	/* True if -b switch seen */
+/* See md_parse_option() for meanings of these options.  */
+static char norelax;			/* True if -norelax switch seen.  */
+static char instrument_branches;	/* True if -b switch seen.  */
 
 /* Characters that always start a comment.
-   If the pre-processor is disabled, these aren't very useful.
- */
+   If the pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#";
 
 /* Characters that only start a comment at the beginning of
@@ -201,21 +141,18 @@ const char comment_chars[] = "#";
 
    Note that input_file.c hand checks for '#' at the beginning of the
    first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.
- */
+   #NO_APP at the beginning of its output.  */
 
 /* Also note that comments started like this one will always work.  */
 
-const char line_comment_chars[] = "#";
-
+const char line_comment_chars[]   = "#";
 const char line_separator_chars[] = ";";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant,
-   as in 0f12.456 or 0d1.2345e12
- */
+   as in 0f12.456 or 0d1.2345e12.  */
 const char FLT_CHARS[] = "fFdDtT";
 
 /* Table used by base assembler to relax addresses based on varying length
@@ -227,52 +164,34 @@ const char FLT_CHARS[] = "fFdDtT";
 
    For i80960, the only application is the (de-)optimization of cobr
    instructions into separate compare and branch instructions when a 13-bit
-   displacement won't hack it.
- */
+   displacement won't hack it.  */
 const relax_typeS md_relax_table[] =
 {
-  {0, 0, 0, 0},			/* State 0 => no more relaxation possible */
-  {4088, -4096, 0, 2},		/* State 1: conditional branch (cobr) */
-  {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl) */
+  {0, 0, 0, 0},				/* State 0 => no more relaxation possible.  */
+  {4088, -4096, 0, 2},			/* State 1: conditional branch (cobr).  */
+  {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl).  */
 };
 
-static void s_endian PARAMS ((int));
-
 /* These are the machine dependent pseudo-ops.
 
    This table describes all the machine specific pseudo-ops the assembler
    has to support.  The fields are:
         pseudo-op name without dot
         function to call to execute this pseudo-op
-        integer arg to pass to the function
- */
+        integer arg to pass to the function.  */
 #define S_LEAFPROC	1
 #define S_SYSPROC	2
 
-const pseudo_typeS md_pseudo_table[] =
-{
-  {"bss", s_lcomm, 1},
-  {"endian", s_endian, 0},
-  {"extended", float_cons, 't'},
-  {"leafproc", parse_po, S_LEAFPROC},
-  {"sysproc", parse_po, S_SYSPROC},
-
-  {"word", cons, 4},
-  {"quad", cons, 16},
-
-  {0, 0, 0}
-};
-
-/* Macros to extract info from an 'expressionS' structure 'e' */
+/* Macros to extract info from an 'expressionS' structure 'e'.  */
 #define adds(e)	e.X_add_symbol
 #define offs(e)	e.X_add_number
 
-/* Branch-prediction bits for CTRL/COBR format opcodes */
-#define BP_MASK		0x00000002	/* Mask for branch-prediction bit */
-#define BP_TAKEN	0x00000000	/* Value to OR in to predict branch */
-#define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch */
+/* Branch-prediction bits for CTRL/COBR format opcodes.  */
+#define BP_MASK		0x00000002	/* Mask for branch-prediction bit.  */
+#define BP_TAKEN	0x00000000	/* Value to OR in to predict branch.  */
+#define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch.  */
 
-/* Some instruction opcodes that we need explicitly */
+/* Some instruction opcodes that we need explicitly.  */
 #define BE	0x12000000
 #define BG	0x11000000
 #define BGE	0x13000000
@@ -301,12 +220,12 @@ const pseudo_typeS md_pseudo_table[] =
    used).  */
 #define MEMA_ABASE	0x2000
 
-/* Info from which a MEMA or MEMB format instruction can be generated */
+/* Info from which a MEMA or MEMB format instruction can be generated.  */
 typedef struct memS
   {
-    /* (First) 32 bits of instruction */
+    /* (First) 32 bits of instruction.  */
     long opcode;
-    /* 0-(none), 12- or, 32-bit displacement needed */
+    /* 0-(none), 12- or, 32-bit displacement needed.  */
     int disp;
     /* The expression in the source instruction from which the
        displacement should be determined.  */
@@ -314,12 +233,12 @@ typedef struct memS
   }
 memS;
 
-/* The two pieces of info we need to generate a register operand */
+/* The two pieces of info we need to generate a register operand.  */
 struct regop
   {
-    int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg */
-    int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0) */
-    int n;			/* Register number or literal value */
+    int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg.  */
+    int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0).  */
+    int n;			/* Register number or literal value.  */
   };
 
 /* Number and assembler mnemonic for all registers that can appear in
@@ -420,10 +339,10 @@ regnames[] =
 /* Number and assembler mnemonic for all registers that can appear as
    'abase' (indirect addressing) registers.  */
 static const struct
-  {
-    char *areg_name;
-    int areg_num;
-  }
+{
+  char *areg_name;
+  int areg_num;
+}
 aregs[] =
 {
   { "(pfp)", 0 },
@@ -467,24 +386,23 @@ aregs[] =
   { NULL, 0 },				/* END OF LIST */
 };
 
-/* Hash tables */
-static struct hash_control *op_hash;	/* Opcode mnemonics */
-static struct hash_control *reg_hash;	/* Register name hash table */
-static struct hash_control *areg_hash;	/* Abase register hash table */
+/* Hash tables.  */
+static struct hash_control *op_hash;	/* Opcode mnemonics.  */
+static struct hash_control *reg_hash;	/* Register name hash table.  */
+static struct hash_control *areg_hash;	/* Abase register hash table.  */
 
-/* Architecture for which we are assembling */
-#define ARCH_ANY	0	/* Default: no architecture checking done */
+/* Architecture for which we are assembling.  */
+#define ARCH_ANY	0	/* Default: no architecture checking done.  */
 #define ARCH_KA		1
 #define ARCH_KB		2
 #define ARCH_MC		3
 #define ARCH_CA		4
 #define ARCH_JX		5
 #define ARCH_HX		6
-int architecture = ARCH_ANY;	/* Architecture requested on invocation line */
+int architecture = ARCH_ANY;	/* Architecture requested on invocation line.  */
 int iclasses_seen;		/* OR of instruction classes (I_* constants)
-				 *    for which we've actually assembled
-				 *      instructions.
-				 */
+				      for which we've actually assembled
+				        instructions.  */
 
 /* BRANCH-PREDICTION INSTRUMENTATION
 
@@ -519,8 +437,7 @@ int iclasses_seen;		/* OR of instruction classes (I_* constants)
 
             Note that input source code is expected to already contain calls
             an external routine that will link the branch local table into a
-            list of such tables.
- */
+            list of such tables.  */
 
 /* Number of branches instrumented so far.  Also used to generate
    unique local labels for each instrumented branch.  */
@@ -537,19 +454,16 @@ static int br_cnt;
 #define BR_TAB_NAME	"__BRANCH_TABLE__"
 /* Name of the table of pointers to branches.  A local (i.e.,
    non-external) symbol.  */
-
-/*****************************************************************************
-   md_begin:  One-time initialization.
 
-  	Set up hash tables.
+static void ctrl_fmt (char *, long, int);
 
-  *************************************************************************** */
+
 void
-md_begin ()
+md_begin (void)
 {
-  int i;			/* Loop counter */
-  const struct i960_opcode *oP;	/* Pointer into opcode table */
-  const char *retval;		/* Value returned by hash functions */
+  int i;			/* Loop counter.  */
+  const struct i960_opcode *oP;	/* Pointer into opcode table.  */
+  const char *retval;		/* Value returned by hash functions.  */
 
   op_hash = hash_new ();
   reg_hash = hash_new ();
@@ -560,7 +474,7 @@ md_begin ()
   retval = 0;
 
   for (oP = i960_opcodes; oP->name && !retval; oP++)
-    retval = hash_insert (op_hash, oP->name, (PTR) oP);
+    retval = hash_insert (op_hash, oP->name, (void *) oP);
 
   for (i = 0; regnames[i].reg_name && !retval; i++)
     retval = hash_insert (reg_hash, regnames[i].reg_name,
@@ -574,899 +488,92 @@ md_begin ()
     as_fatal (_("Hashing returned \"%s\"."), retval);
 }
 
-/*****************************************************************************
-   md_assemble:  Assemble an instruction
-
-   Assumptions about the passed-in text:
-  	- all comments, labels removed
-  	- text is an instruction
-  	- all white space compressed to single blanks
-  	- all character constants have been replaced with decimal
-
-  *************************************************************************** */
-void
-md_assemble (textP)
-     char *textP;		/* Source text of instruction */
-{
-  /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
-     mnemonic arg[1-3]->operands, with char constants replaced by
-     decimal numbers.  */
-  char *args[4];
-
-  int n_ops;			/* Number of instruction operands */
-  /* Pointer to instruction description */
-  struct i960_opcode *oP;
-  /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
-     or ".t").  */
-  int branch_predict;
-  /* Setting of branch-prediction bit(s) to be OR'd into instruction
-     opcode of CTRL/COBR format instructions.  */
-  long bp_bits;
-
-  int n;			/* Offset of last character in opcode mnemonic */
-
-  const char *bp_error_msg = _("branch prediction invalid on this opcode");
-
-  /* Parse instruction into opcode and operands */
-  memset (args, '\0', sizeof (args));
-  n_ops = i_scan (textP, args);
-  if (n_ops == -1)
-    {
-      return;			/* Error message already issued */
-    }
-
-  /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
-  if (!strcmp (args[0], "ldconst"))
-    {
-      n_ops = parse_ldconst (args);
-      if (n_ops == -1)
-	{
-	  return;
-	}
-    }
-
-  /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
-  n = strlen (args[0]) - 1;
-  branch_predict = 0;
-  bp_bits = 0;
-  if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
-    {
-      /* We could check here to see if the target architecture
-	 supports branch prediction, but why bother?  The bit will
-	 just be ignored by processors that don't use it.  */
-      branch_predict = 1;
-      bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
-      args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
-    }
-
-  /* Look up opcode mnemonic in table and check number of operands.
-     Check that opcode is legal for the target architecture.  If all
-     looks good, assemble instruction.  */
-  oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
-  if (!oP || !targ_has_iclass (oP->iclass))
-    {
-      as_bad (_("invalid opcode, \"%s\"."), args[0]);
-
-    }
-  else if (n_ops != oP->num_ops)
-    {
-      as_bad (_("improper number of operands.  expecting %d, got %d"),
-	      oP->num_ops, n_ops);
-    }
-  else
-    {
-      switch (oP->format)
-	{
-	case FBRA:
-	case CTRL:
-	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
-	  if (oP->format == FBRA)
-	    {
-	      /* Now generate a 'bno' to same arg */
-	      ctrl_fmt (args[1], BNO | bp_bits, 1);
-	    }
-	  break;
-	case COBR:
-	case COJ:
-	  cobr_fmt (args, oP->opcode | bp_bits, oP);
-	  break;
-	case REG:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  reg_fmt (args, oP);
-	  break;
-	case MEM1:
-	  if (args[0][0] == 'c' && args[0][1] == 'a')
-	    {
-	      if (branch_predict)
-		{
-		  as_warn (bp_error_msg);
-		}
-	      mem_fmt (args, oP, 1);
-	      break;
-	    }
-	case MEM2:
-	case MEM4:
-	case MEM8:
-	case MEM12:
-	case MEM16:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  mem_fmt (args, oP, 0);
-	  break;
-	case CALLJ:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  /* Output opcode & set up "fixup" (relocation); flag
-	     relocation as 'callj' type.  */
-	  know (oP->num_ops == 1);
-	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
-	  break;
-	default:
-	  BAD_CASE (oP->format);
-	  break;
-	}
-    }
-}				/* md_assemble() */
-
-/*****************************************************************************
-   md_number_to_chars:  convert a number to target byte order
-
-  *************************************************************************** */
-void
-md_number_to_chars (buf, value, n)
-     char *buf;
-     valueT value;
-     int n;
-{
-  number_to_chars_littleendian (buf, value, n);
-}
-
-/*****************************************************************************
-   md_chars_to_number:  convert from target byte order to host byte order.
-
-  *************************************************************************** */
-static int md_chars_to_number PARAMS ((unsigned char *, int));
-
-static int
-md_chars_to_number (val, n)
-     unsigned char *val;	/* Value in target byte order */
-     int n;			/* Number of bytes in the input */
-{
-  int retval;
-
-  for (retval = 0; n--;)
-    {
-      retval <<= 8;
-      retval |= val[n];
-    }
-  return retval;
-}
-
-#define MAX_LITTLENUMS	6
-#define LNUM_SIZE	sizeof (LITTLENUM_TYPE)
-
-/*****************************************************************************
-   md_atof:	convert ascii to floating point
-
-   Turn a string at input_line_pointer into a floating point constant of type
-   'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
-   emitted is returned at 'sizeP'.  An error message is returned, or a pointer
-   to an empty message if OK.
-
-   Note we call the i386 floating point routine, rather than complicating
-   things with more files or symbolic links.
-
-  *************************************************************************** */
-char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
-{
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  int prec;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-      prec = 4;
-      break;
-
-    case 't':
-    case 'T':
-      prec = 5;
-      type = 'x';		/* That's what atof_ieee() understands */
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to md_atof()");
-    }
-
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    {
-      input_line_pointer = t;
-    }
-
-  *sizeP = prec * LNUM_SIZE;
-
-  /* Output the LITTLENUMs in REVERSE order in accord with i80960
-     word-order.  (Dunno why atof_ieee doesn't do it in the right
-     order in the first place -- probably because it's a hack of
-     atof_m68k.)  */
-
-  for (wordP = words + prec - 1; prec--;)
-    {
-      md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-
-  return 0;
-}
-
-/*****************************************************************************
-   md_number_to_imm
-
-  *************************************************************************** */
-static void md_number_to_imm PARAMS ((char *, long, int));
-
-static void
-md_number_to_imm (buf, val, n)
-     char *buf;
-     long val;
-     int n;
-{
-  md_number_to_chars (buf, val, n);
-}
-
-/*****************************************************************************
-   md_number_to_field:
-
-  	Stick a value (an address fixup) into a bit field of
-  	previously-generated instruction.
-
-  *************************************************************************** */
-static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
-
-static void
-md_number_to_field (instrP, val, bfixP)
-     char *instrP;		/* Pointer to instruction to be fixed */
-     long val;			/* Address fixup value */
-     bit_fixS *bfixP;		/* Description of bit field to be fixed up */
-{
-  int numbits;			/* Length of bit field to be fixed */
-  long instr;			/* 32-bit instruction to be fixed-up */
-  long sign;			/* 0 or -1, according to sign bit of 'val' */
-
-  /* Convert instruction back to host byte order.  */
-  instr = md_chars_to_number (instrP, 4);
-
-  /* Surprise! -- we stored the number of bits to be modified rather
-     than a pointer to a structure.  */
-  numbits = (int) bfixP;
-  if (numbits == 1)
-    {
-      /* This is a no-op, stuck here by reloc_callj() */
-      return;
-    }
-
-  know ((numbits == 13) || (numbits == 24));
-
-  /* Propagate sign bit of 'val' for the given number of bits.  Result
-     should be all 0 or all 1.  */
-  sign = val >> ((int) numbits - 1);
-  if (((val < 0) && (sign != -1))
-      || ((val > 0) && (sign != 0)))
-    {
-      as_bad (_("Fixup of %ld too large for field width of %d"),
-	      val, numbits);
-    }
-  else
-    {
-      /* Put bit field into instruction and write back in target
-         * byte order.
-       */
-      val &= ~(-1 << (int) numbits);	/* Clear unused sign bits */
-      instr |= val;
-      md_number_to_chars (instrP, instr, 4);
-    }
-}				/* md_number_to_field() */
-
-
-/*****************************************************************************
-   md_parse_option
-  	Invocation line includes a switch not recognized by the base assembler.
-  	See if it's a processor-specific option.  For the 960, these are:
-
-  	-norelax:
-  		Conditional branch instructions that require displacements
-  		greater than 13 bits (or that have external targets) should
-  		generate errors.  The default is to replace each such
-  		instruction with the corresponding compare (or chkbit) and
-  		branch instructions.  Note that the Intel "j" cobr directives
-  		are ALWAYS "de-optimized" in this way when necessary,
-  		regardless of the setting of this option.
-
-  	-b:
-  		Add code to collect information about branches taken, for
-  		later optimization of branch prediction bits by a separate
-  		tool.  COBR and CNTL format instructions have branch
-  		prediction bits (in the CX architecture);  if "BR" represents
-  		an instruction in one of these classes, the following rep-
-  		resents the code generated by the assembler:
-
-  			call	<increment routine>
-  			.word	0	# pre-counter
-  		Label:  BR
-  			call	<increment routine>
-  			.word	0	# post-counter
-
-  		A table of all such "Labels" is also generated.
-
-  	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
-  		Select the 80960 architecture.  Instructions or features not
-  		supported by the selected architecture cause fatal errors.
-  		The default is to generate code for any instruction or feature
-  		that is supported by SOME version of the 960 (even if this
-  		means mixing architectures!).
-
-  ****************************************************************************/
-
-const char *md_shortopts = "A:b";
-struct option md_longopts[] =
-{
-#define OPTION_LINKRELAX (OPTION_MD_BASE)
-  {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
-  {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
-#define OPTION_NORELAX (OPTION_MD_BASE + 1)
-  {"norelax", no_argument, NULL, OPTION_NORELAX},
-  {"no-relax", no_argument, NULL, OPTION_NORELAX},
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-struct tabentry
-  {
-    char *flag;
-    int arch;
-  };
-static const struct tabentry arch_tab[] =
-{
-  {"KA", ARCH_KA},
-  {"KB", ARCH_KB},
-  {"SA", ARCH_KA},		/* Synonym for KA */
-  {"SB", ARCH_KB},		/* Synonym for KB */
-  {"KC", ARCH_MC},		/* Synonym for MC */
-  {"MC", ARCH_MC},
-  {"CA", ARCH_CA},
-  {"JX", ARCH_JX},
-  {"HX", ARCH_HX},
-  {NULL, 0}
-};
-
-int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
-{
-  switch (c)
-    {
-    case OPTION_LINKRELAX:
-      linkrelax = 1;
-      flag_keep_locals = 1;
-      break;
-
-    case OPTION_NORELAX:
-      norelax = 1;
-      break;
-
-    case 'b':
-      instrument_branches = 1;
-      break;
-
-    case 'A':
-      {
-	const struct tabentry *tp;
-	char *p = arg;
-
-	for (tp = arch_tab; tp->flag != NULL; tp++)
-	  if (!strcmp (p, tp->flag))
-	    break;
-
-	if (tp->flag == NULL)
-	  {
-	    as_bad (_("invalid architecture %s"), p);
-	    return 0;
-	  }
-	else
-	  architecture = tp->arch;
-      }
-      break;
-
-    default:
-      return 0;
-    }
-
-  return 1;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream;
-{
-  int i;
-  fprintf (stream, _("I960 options:\n"));
-  for (i = 0; arch_tab[i].flag; i++)
-    fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
-  fprintf (stream, _("\n\
-			specify variant of 960 architecture\n\
--b			add code to collect statistics about branches taken\n\
--link-relax		preserve individual alignment directives so linker\n\
-			can do relaxing (b.out format only)\n\
--no-relax		don't alter compare-and-branch instructions for\n\
-			long displacements\n"));
-}
-
-
-/*****************************************************************************
-   md_convert_frag:
-  	Called by base assembler after address relaxation is finished:  modify
-  	variable fragments according to how much relaxation was done.
-
-  	If the fragment substate is still 1, a 13-bit displacement was enough
-  	to reach the symbol in question.  Set up an address fixup, but otherwise
-  	leave the cobr instruction alone.
-
-  	If the fragment substate is 2, a 13-bit displacement was not enough.
-  	Replace the cobr with a two instructions (a compare and a branch).
-
-  *************************************************************************** */
-#ifndef BFD_ASSEMBLER
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#else
-void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#endif
-{
-  fixS *fixP;			/* Structure describing needed address fix */
-
-  switch (fragP->fr_subtype)
-    {
-    case 1:
-      /* LEAVE SINGLE COBR INSTRUCTION */
-      fixP = fix_new (fragP,
-		      fragP->fr_opcode - fragP->fr_literal,
-		      4,
-		      fragP->fr_symbol,
-		      fragP->fr_offset,
-		      1,
-		      NO_RELOC);
-
-      fixP->fx_bit_fixP = (bit_fixS *) 13;	/* size of bit field */
-      break;
-    case 2:
-      /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
-      relax_cobr (fragP);
-      break;
-    default:
-      BAD_CASE (fragP->fr_subtype);
-      break;
-    }
-}
-
-/*****************************************************************************
-   md_estimate_size_before_relax:  How much does it look like *fragP will grow?
-
-  	Called by base assembler just before address relaxation.
-  	Return the amount by which the fragment will grow.
+/* parse_expr:		parse an expression
 
-  	Any symbol that is now undefined will not become defined; cobr's
-  	based on undefined symbols will have to be replaced with a compare
-  	instruction and a branch instruction, and the code fragment will grow
-  	by 4 bytes.
+   Use base assembler's expression parser to parse an expression.
+   It, unfortunately, runs off a global which we have to save/restore
+   in order to make it work for us.
 
-  *************************************************************************** */
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS *fragP;
-     register segT segment_type;
-{
-  /* If symbol is undefined in this segment, go to "relaxed" state
-     (compare and branch instructions instead of cobr) right now.  */
-  if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
-    {
-      relax_cobr (fragP);
-      return 4;
-    }
-
-  return md_relax_table[fragP->fr_subtype].rlx_length;
-}				/* md_estimate_size_before_relax() */
-
-#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
-
-/*****************************************************************************
-   md_ri_to_chars:
-  	This routine exists in order to overcome machine byte-order problems
-  	when dealing with bit-field entries in the relocation_info struct.
-
-  	But relocation info will be used on the host machine only (only
-  	executable code is actually downloaded to the i80960).  Therefore,
-  	we leave it in host byte order.
-
-  	The above comment is no longer true.  This routine now really
-  	does do the reordering (Ian Taylor 28 Aug 92).
+   An empty expression string is treated as an absolute 0.
 
-  *************************************************************************** */
-static void md_ri_to_chars PARAMS ((char *, struct relocation_info *));
+   Sets O_illegal regardless of expression evaluation if entire input
+   string is not consumed in the evaluation -- tolerate no dangling junk!  */
 
 static void
-md_ri_to_chars (where, ri)
-     char *where;
-     struct relocation_info *ri;
+parse_expr (char *textP,		/* Text of expression to be parsed.  */
+	    expressionS *expP)		/* Where to put the results of parsing.  */
 {
-  md_number_to_chars (where, ri->r_address,
-		      sizeof (ri->r_address));
-  where[4] = ri->r_index & 0x0ff;
-  where[5] = (ri->r_index >> 8) & 0x0ff;
-  where[6] = (ri->r_index >> 16) & 0x0ff;
-  where[7] = ((ri->r_pcrel << 0)
-	      | (ri->r_length << 1)
-	      | (ri->r_extern << 3)
-	      | (ri->r_bsr << 4)
-	      | (ri->r_disp << 5)
-	      | (ri->r_callj << 6));
-}
-
-#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
-
-
-/* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER  */
-
-/*****************************************************************************
-   brcnt_emit:	Emit code to increment inline branch counter.
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-  *************************************************************************** */
-static void
-brcnt_emit ()
-{
-  ctrl_fmt (BR_CNT_FUNC, CALL, 1);	/* Emit call to "increment" routine */
-  emit (0);			/* Emit inline counter to be incremented */
-}
-
-/*****************************************************************************
-   brlab_next:	generate the next branch local label
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-  *************************************************************************** */
-static char *
-brlab_next ()
-{
-  static char buf[20];
-
-  sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
-  return buf;
-}
-
-/*****************************************************************************
-   brtab_emit:	generate the fetch-prediction branch table.
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-
-  	The code emitted here would be functionally equivalent to the following
-  	example assembler source.
-
-  			.data
-  			.align	2
-  	   BR_TAB_NAME:
-  			.word	0		# link to next table
-  			.word	3		# length of table
-  			.word	LBRANCH0	# 1st entry in table proper
-  			.word	LBRANCH1
-  			.word	LBRANCH2
-  **************************************************************************** */
-void
-brtab_emit ()
-{
-  int i;
-  char buf[20];
-  char *p;			/* Where the binary was output to */
-  /* Pointer to description of deferred address fixup.  */
-  fixS *fixP;
-
-  if (!instrument_branches)
-    {
-      return;
-    }
-
-  subseg_set (data_section, 0);	/*      .data */
-  frag_align (2, 0, 0);		/*      .align 2 */
-  record_alignment (now_seg, 2);
-  colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
-  emit (0);			/*      .word 0 #link to next table */
-  emit (br_cnt);		/*      .word n #length of table */
-
-  for (i = 0; i < br_cnt; i++)
-    {
-      sprintf (buf, "%s%d", BR_LABEL_BASE, i);
-      p = emit (0);
-      fixP = fix_new (frag_now,
-		      p - frag_now->fr_literal,
-		      4,
-		      symbol_find (buf),
-		      0,
-		      0,
-		      NO_RELOC);
-    }
-}
-
-/*****************************************************************************
-   cobr_fmt:	generate a COBR-format instruction
-
-  *************************************************************************** */
-static void
-cobr_fmt (arg, opcode, oP)
-     /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
-     char *arg[];
-     /* Opcode, with branch-prediction bits already set if necessary.  */
-     long opcode;
-     /* Pointer to description of instruction.  */
-     struct i960_opcode *oP;
-{
-  long instr;			/* 32-bit instruction */
-  struct regop regop;		/* Description of register operand */
-  int n;			/* Number of operands */
-  int var_frag;			/* 1 if varying length code fragment should
-				 *    be emitted;  0 if an address fix
-				 *      should be emitted.
-				 */
-
-  instr = opcode;
-  n = oP->num_ops;
-
-  if (n >= 1)
-    {
-      /* First operand (if any) of a COBR is always a register
-	 operand.  Parse it.  */
-      parse_regop (&regop, arg[1], oP->operand[0]);
-      instr |= (regop.n << 19) | (regop.mode << 13);
-    }
-  if (n >= 2)
-    {
-      /* Second operand (if any) of a COBR is always a register
-	 operand.  Parse it.  */
-    parse_regop (&regop, arg[2], oP->operand[1]);
-      instr |= (regop.n << 14) | regop.special;
-    }
-
-  if (n < 3)
-    {
-      emit (instr);
-
-    }
-  else
-    {
-      if (instrument_branches)
-	{
-	  brcnt_emit ();
-	  colon (brlab_next ());
-	}
-
-      /* A third operand to a COBR is always a displacement.  Parse
-         it; if it's relaxable (a cobr "j" directive, or any cobr
-         other than bbs/bbc when the "-norelax" option is not in use)
-         set up a variable code fragment; otherwise set up an address
-         fix.  */
-      var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
-      get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
-
-      if (instrument_branches)
-	{
-	  brcnt_emit ();
-	}
-    }
-}				/* cobr_fmt() */
-
-/*****************************************************************************
-   ctrl_fmt:	generate a CTRL-format instruction
+  char *save_in;		/* Save global here.  */
+  symbolS *symP;
 
-  *************************************************************************** */
-static void
-ctrl_fmt (targP, opcode, num_ops)
-     char *targP;		/* Pointer to text of lone operand (if any) */
-     long opcode;		/* Template of instruction */
-     int num_ops;		/* Number of operands */
-{
-  int instrument;		/* TRUE iff we should add instrumentation to track
-				   * how often the branch is taken
-				 */
+  know (textP);
 
-  if (num_ops == 0)
+  if (*textP == '\0')
     {
-      emit (opcode);		/* Output opcode */
+      /* Treat empty string as absolute 0.  */
+      expP->X_add_symbol = expP->X_op_symbol = NULL;
+      expP->X_add_number = 0;
+      expP->X_op = O_constant;
     }
   else
     {
+      save_in = input_line_pointer;	/* Save global.  */
+      input_line_pointer = textP;	/* Make parser work for us.  */
 
-      instrument = instrument_branches && (opcode != CALL)
-	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
-
-      if (instrument)
-	{
-	  brcnt_emit ();
-	  colon (brlab_next ());
-	}
+      (void) expression (expP);
+      if ((size_t) (input_line_pointer - textP) != strlen (textP))
+	/* Did not consume all of the input.  */
+	expP->X_op = O_illegal;
 
-      /* The operand MUST be an ip-relative displacement. Parse it
-         * and set up address fix for the instruction we just output.
-       */
-      get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
+      symP = expP->X_add_symbol;
+      if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
+	/* Register name in an expression.  */
+	/* FIXME: this isn't much of a check any more.  */
+	expP->X_op = O_illegal;
 
-      if (instrument)
-	{
-	  brcnt_emit ();
-	}
+      input_line_pointer = save_in;	/* Restore global.  */
     }
-
 }
 
-/*****************************************************************************
-   emit:	output instruction binary
+/* emit:	output instruction binary
 
-  	Output instruction binary, in target byte order, 4 bytes at a time.
-  	Return pointer to where it was placed.
+   Output instruction binary, in target byte order, 4 bytes at a time.
+   Return pointer to where it was placed.  */
 
-  *************************************************************************** */
 static char *
-emit (instr)
-     long instr;		/* Word to be output, host byte order */
+emit (long instr)		/* Word to be output, host byte order.  */
 {
-  char *toP;			/* Where to output it */
+  char *toP;			/* Where to output it.  */
 
-  toP = frag_more (4);		/* Allocate storage */
-  md_number_to_chars (toP, instr, 4);	/* Convert to target byte order */
+  toP = frag_more (4);		/* Allocate storage.  */
+  md_number_to_chars (toP, instr, 4);	/* Convert to target byte order.  */
   return toP;
 }
 
-/*****************************************************************************
-   get_args:	break individual arguments out of comma-separated list
+/* get_cdisp:	handle displacement for a COBR or CTRL instruction.
 
-   Input assumptions:
-  	- all comments and labels have been removed
-  	- all strings of whitespace have been collapsed to a single blank.
-  	- all character constants ('x') have been replaced with decimal
+   Parse displacement for a COBR or CTRL instruction.
 
-   Output:
-  	args[0] is untouched. args[1] points to first operand, etc. All args:
-  	- are NULL-terminated
-  	- contain no whitespace
-
-   Return value:
-  	Number of operands (0,1,2, or 3) or -1 on error.
-
-  *************************************************************************** */
-static int
-get_args (p, args)
-     /* Pointer to comma-separated operands; MUCKED BY US */
-     register char *p;
-     /* Output arg: pointers to operands placed in args[1-3].  MUST
-        ACCOMMODATE 4 ENTRIES (args[0-3]).  */
-     char *args[];
-{
-  register int n;		/* Number of operands */
-  register char *to;
-
-  /* Skip lead white space */
-  while (*p == ' ')
-    {
-      p++;
-    }
-
-  if (*p == '\0')
-    {
-      return 0;
-    }
-
-  n = 1;
-  args[1] = p;
-
-  /* Squeze blanks out by moving non-blanks toward start of string.
-     * Isolate operands, whenever comma is found.
-   */
-  to = p;
-  while (*p != '\0')
-    {
-
-      if (*p == ' '
-	  && (! ISALNUM (p[1])
-	      || ! ISALNUM (p[-1])))
-	{
-	  p++;
-
-	}
-      else if (*p == ',')
-	{
-
-	  /* Start of operand */
-	  if (n == 3)
-	    {
-	      as_bad (_("too many operands"));
-	      return -1;
-	    }
-	  *to++ = '\0';		/* Terminate argument */
-	  args[++n] = to;	/* Start next argument */
-	  p++;
-
-	}
-      else
-	{
-	  *to++ = *p++;
-	}
-    }
-  *to = '\0';
-  return n;
-}
-
-/*****************************************************************************
-   get_cdisp:	handle displacement for a COBR or CTRL instruction.
-
-  	Parse displacement for a COBR or CTRL instruction.
-
-  	If successful, output the instruction opcode and set up for it,
-  	depending on the arg 'var_frag', either:
+   If successful, output the instruction opcode and set up for it,
+   depending on the arg 'var_frag', either:
   	    o an address fixup to be done when all symbol values are known, or
   	    o a varying length code fragment, with address fixup info.  This
   		will be done for cobr instructions that may have to be relaxed
   		in to compare/branch instructions (8 bytes) if the final
-  		address displacement is greater than 13 bits.
+  		address displacement is greater than 13 bits.  */
 
-  ****************************************************************************/
 static void
-get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
-     /* displacement as specified in source instruction */
-     char *dispP;
-     /* "COBR" or "CTRL" (for use in error message) */
-     char *ifmtP;
-     /* Instruction needing the displacement */
-     long instr;
-     /* # bits of displacement (13 for COBR, 24 for CTRL) */
-     int numbits;
-     /* 1 if varying length code fragment should be emitted;
-      *       0 if an address fix should be emitted.
-      */
-     int var_frag;
-     /* 1 if callj relocation should be done; else 0 */
-     int callj;
+get_cdisp (char *dispP, /* Displacement as specified in source instruction.  */
+	   char *ifmtP, /* "COBR" or "CTRL" (for use in error message).  */
+	   long instr,  /* Instruction needing the displacement.  */
+	   int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL).  */
+	   int var_frag,/* 1 if varying length code fragment should be emitted;
+			   0 if an address fix should be emitted.  */
+	   int callj)	/* 1 if callj relocation should be done; else 0.  */	   
 {
-  expressionS e;		/* Parsed expression */
-  fixS *fixP;			/* Structure describing needed address fix */
-  char *outP;			/* Where instruction binary is output to */
+  expressionS e;		/* Parsed expression.  */
+  fixS *fixP;			/* Structure describing needed address fix.  */
+  char *outP;			/* Where instruction binary is output to.  */
 
   fixP = NULL;
 
@@ -1482,7 +589,7 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	{
 	  if (var_frag)
 	    {
-	      outP = frag_more (8);	/* Allocate worst-case storage */
+	      outP = frag_more (8);	/* Allocate worst-case storage.  */
 	      md_number_to_chars (outP, instr, 4);
 	      frag_variant (rs_machine_dependent, 4, 4, 1,
 			    adds (e), offs (e), outP);
@@ -1490,8 +597,7 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	  else
 	    {
 	      /* Set up a new fix structure, so address can be updated
-	       * when all symbol values are known.
-	       */
+	         when all symbol values are known.  */
 	      outP = emit (instr);
 	      fixP = fix_new (frag_now,
 			      outP - frag_now->fr_literal,
@@ -1504,11 +610,10 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	      fixP->fx_tcbit = callj;
 
 	      /* We want to modify a bit field when the address is
-	       * known.  But we don't need all the garbage in the
-	       * bit_fix structure.  So we're going to lie and store
-	       * the number of bits affected instead of a pointer.
-	       */
-	      fixP->fx_bit_fixP = (bit_fixS *) numbits;
+	         known.  But we don't need all the garbage in the
+	         bit_fix structure.  So we're going to lie and store
+	         the number of bits affected instead of a pointer.  */
+	      fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
 	    }
 	}
       else
@@ -1521,67 +626,75 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
     }
 }
 
-/*****************************************************************************
-   get_ispec:	parse a memory operand for an index specification
+static int
+md_chars_to_number (char * val,		/* Value in target byte order.  */
+		    int n)		/* Number of bytes in the input.  */
+{
+  int retval;
 
-  	Here, an "index specification" is taken to be anything surrounded
-  	by square brackets and NOT followed by anything else.
+  for (retval = 0; n--;)
+    {
+      retval <<= 8;
+      retval |= (unsigned char) val[n];
+    }
+  return retval;
+}
 
-  	If it's found, detach it from the input string, remove the surrounding
-  	square brackets, and return a pointer to it.  Otherwise, return NULL.
+/* mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
 
-  *************************************************************************** */
-static char *
-get_ispec (textP)
-     /* Pointer to memory operand from source instruction, no white space.  */
-     char *textP;
+   There are 2 possible MEMA formats:
+  	- displacement only
+  	- displacement + abase
+
+   They are distinguished by the setting of the MEMA_ABASE bit.  */
+
+static void
+mema_to_memb (char * opcodeP)	/* Where to find the opcode, in target byte order.  */
 {
-  /* Points to start of index specification.  */
-  char *start;
-  /* Points to end of index specification.  */
-  char *end;
+  long opcode;			/* Opcode in host byte order.  */
+  long mode;			/* Mode bits for MEMB instruction.  */
 
-  /* Find opening square bracket, if any.  */
-  start = strchr (textP, '[');
+  opcode = md_chars_to_number (opcodeP, 4);
+  know (!(opcode & MEMB_BIT));
 
-  if (start != NULL)
-    {
+  mode = MEMB_BIT | D_BIT;
+  if (opcode & MEMA_ABASE)
+    mode |= A_BIT;
 
-      /* Eliminate '[', detach from rest of operand */
-      *start++ = '\0';
+  opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits.  */
+  opcode |= mode;		/* Set MEMB mode bits.  */
 
-      end = strchr (start, ']');
+  md_number_to_chars (opcodeP, opcode, 4);
+}
 
-      if (end == NULL)
-	{
-	  as_bad (_("unmatched '['"));
+/* targ_has_sfr:
 
-	}
-      else
-	{
-	  /* Eliminate ']' and make sure it was the last thing
-	     * in the string.
-	   */
-	  *end = '\0';
-	  if (*(end + 1) != '\0')
-	    {
-	      as_bad (_("garbage after index spec ignored"));
-	    }
-	}
+   Return TRUE iff the target architecture supports the specified
+   special-function register (sfr).  */
+
+static int
+targ_has_sfr (int n)		/* Number (0-31) of sfr.  */
+{
+  switch (architecture)
+    {
+    case ARCH_KA:
+    case ARCH_KB:
+    case ARCH_MC:
+    case ARCH_JX:
+      return 0;
+    case ARCH_HX:
+      return ((0 <= n) && (n <= 4));
+    case ARCH_CA:
+    default:
+      return ((0 <= n) && (n <= 2));
     }
-  return start;
 }
 
-/*****************************************************************************
-   get_regnum:
+/* Look up a (suspected) register name in the register table and return the
+   associated register number (or -1 if not found).  */
 
-  	Look up a (suspected) register name in the register table and return the
-  	associated register number (or -1 if not found).
-
-  *************************************************************************** */
 static int
-get_regnum (regname)
-     char *regname;		/* Suspected register name */
+get_regnum (char *regname)	/* Suspected register name.  */
 {
   int *rP;
 
@@ -1589,358 +702,152 @@ get_regnum (regname)
   return (rP == NULL) ? -1 : *rP;
 }
 
-/*****************************************************************************
-   i_scan:	perform lexical scan of ascii assembler instruction.
-
-   Input assumptions:
-  	- input string is an i80960 instruction (not a pseudo-op)
-  	- all comments and labels have been removed
-  	- all strings of whitespace have been collapsed to a single blank.
-
-   Output:
-  	args[0] points to opcode, other entries point to operands. All strings:
-  	- are NULL-terminated
-  	- contain no whitespace
-  	- have character constants ('x') replaced with a decimal number
+/* syntax: Issue a syntax error.  */
 
-   Return value:
-  	Number of operands (0,1,2, or 3) or -1 on error.
-
-  *************************************************************************** */
-static int
-i_scan (iP, args)
-     /* Pointer to ascii instruction;  MUCKED BY US.  */
-     register char *iP;
-     /* Output arg: pointers to opcode and operands placed here.  MUST
-	ACCOMMODATE 4 ENTRIES.  */
-     char *args[];
+static void
+syntax (void)
 {
+  as_bad (_("syntax error"));
+}
 
-  /* Isolate opcode */
-  if (*(iP) == ' ')
-    {
-      iP++;
-    }				/* Skip lead space, if any */
-  args[0] = iP;
-  for (; *iP != ' '; iP++)
-    {
-      if (*iP == '\0')
-	{
-	  /* There are no operands */
-	  if (args[0] == iP)
-	    {
-	      /* We never moved: there was no opcode either! */
-	      as_bad (_("missing opcode"));
-	      return -1;
-	    }
-	  return 0;
-	}
-    }
-  *iP++ = '\0';			/* Terminate opcode */
-  return (get_args (iP, args));
-}				/* i_scan() */
+/* parse_regop: parse a register operand.
 
-/*****************************************************************************
-   mem_fmt:	generate a MEMA- or MEMB-format instruction
+   In case of illegal operand, issue a message and return some valid
+   information so instruction processing can continue.  */
 
-  *************************************************************************** */
 static void
-mem_fmt (args, oP, callx)
-     char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
-     struct i960_opcode *oP;	/* Pointer to description of instruction */
-     int callx;			/* Is this a callx opcode */
+parse_regop (struct regop *regopP,	/* Where to put description of register operand.  */
+	     char *optext,		/* Text of operand.  */
+	     char opdesc)      		/* Descriptor byte:  what's legal for this operand.  */
 {
-  int i;			/* Loop counter */
-  struct regop regop;		/* Description of register operand */
-  char opdesc;			/* Operand descriptor byte */
-  memS instr;			/* Description of binary to be output */
-  char *outP;			/* Where the binary was output to */
-  expressionS expr;		/* Parsed expression */
-  /* ->description of deferred address fixup */
-  fixS *fixP;
-
-#ifdef OBJ_COFF
-  /* COFF support isn't in place yet for callx relaxing.  */
-  callx = 0;
-#endif
+  int n;			/* Register number.  */
+  expressionS e;		/* Parsed expression.  */
 
-  memset (&instr, '\0', sizeof (memS));
-  instr.opcode = oP->opcode;
-
-  /* Process operands.  */
-  for (i = 1; i <= oP->num_ops; i++)
+  /* See if operand is a register.  */
+  n = get_regnum (optext);
+  if (n >= 0)
     {
-      opdesc = oP->operand[i - 1];
-
-      if (MEMOP (opdesc))
+      if (IS_RG_REG (n))
 	{
-	  parse_memop (&instr, args[i], oP->format);
+	  /* Global or local register.  */
+	  if (!REG_ALIGN (opdesc, n))
+	    as_bad (_("unaligned register"));
+
+	  regopP->n = n;
+	  regopP->mode = 0;
+	  regopP->special = 0;
+	  return;
 	}
-      else
+      else if (IS_FP_REG (n) && FP_OK (opdesc))
 	{
-	  parse_regop (&regop, args[i], opdesc);
-	  instr.opcode |= regop.n << 19;
+	  /* Floating point register, and it's allowed.  */
+	  regopP->n = n - FP0;
+	  regopP->mode = 1;
+	  regopP->special = 0;
+	  return;
 	}
-    }
-
-  /* Parse the displacement; this must be done before emitting the
-     opcode, in case it is an expression using `.'.  */
-  parse_expr (instr.e, &expr);
-
-  /* Output opcode */
-  outP = emit (instr.opcode);
+      else if (IS_SF_REG (n) && SFR_OK (opdesc))
+	{
+	  /* Special-function register, and it's allowed.  */
+	  regopP->n = n - SF0;
+	  regopP->mode = 0;
+	  regopP->special = 1;
+	  if (!targ_has_sfr (regopP->n))
+	    as_bad (_("no such sfr in this architecture"));
 
-  if (instr.disp == 0)
-    {
-      return;
+	  return;
+	}
     }
-
-  /* Process the displacement */
-  switch (expr.X_op)
+  else if (LIT_OK (opdesc))
     {
-    case O_illegal:
-      as_bad (_("expression syntax error"));
-      break;
-
-    case O_constant:
-      if (instr.disp == 32)
-	{
-	  (void) emit (offs (expr));	/* Output displacement */
-	}
-      else
+      /* How about a literal?  */
+      regopP->mode = 1;
+      regopP->special = 0;
+      if (FP_OK (opdesc))
 	{
-	  /* 12-bit displacement */
-	  if (offs (expr) & ~0xfff)
+	  /* Floating point literal acceptable.  */
+	  /* Skip over 0f, 0d, or 0e prefix.  */
+	  if ((optext[0] == '0')
+	      && (optext[1] >= 'd')
+	      && (optext[1] <= 'f'))
+	    optext += 2;
+
+	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
 	    {
-	      /* Won't fit in 12 bits: convert already-output
-	       * instruction to MEMB format, output
-	       * displacement.
-	       */
-	      mema_to_memb (outP);
-	      (void) emit (offs (expr));
+	      regopP->n = 0x10;
+	      return;
 	    }
-	  else
+
+	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
 	    {
-	      /* WILL fit in 12 bits:  OR into opcode and
-	       * overwrite the binary we already put out
-	       */
-	      instr.opcode |= offs (expr);
-	      md_number_to_chars (outP, instr.opcode, 4);
+	      regopP->n = 0x16;
+	      return;
 	    }
 	}
-      break;
-
-    default:
-      if (instr.disp == 12)
+      else
 	{
-	  /* Displacement is dependent on a symbol, whose value
-	   * may change at link time.  We HAVE to reserve 32 bits.
-	   * Convert already-output opcode to MEMB format.
-	   */
-	  mema_to_memb (outP);
+	  /* Fixed point literal acceptable.  */
+	  parse_expr (optext, &e);
+	  if (e.X_op != O_constant
+	      || (offs (e) < 0) || (offs (e) > 31))
+	    {
+	      as_bad (_("illegal literal"));
+	      offs (e) = 0;
+	    }
+	  regopP->n = offs (e);
+	  return;
 	}
-
-      /* Output 0 displacement and set up address fixup for when
-       * this symbol's value becomes known.
-       */
-      outP = emit ((long) 0);
-      fixP = fix_new_exp (frag_now,
-			  outP - frag_now->fr_literal,
-			  4,
-			  &expr,
-			  0,
-			  NO_RELOC);
-      /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
-         being in the instruction stream, specifically as part of a callx
-         instruction.  */
-      fixP->fx_bsr = callx;
-      break;
-    }
-}				/* memfmt() */
-
-/*****************************************************************************
-   mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
-
-   There are 2 possible MEMA formats:
-  	- displacement only
-  	- displacement + abase
-
-   They are distinguished by the setting of the MEMA_ABASE bit.
-
-  *************************************************************************** */
-static void
-mema_to_memb (opcodeP)
-     char *opcodeP;		/* Where to find the opcode, in target byte order */
-{
-  long opcode;			/* Opcode in host byte order */
-  long mode;			/* Mode bits for MEMB instruction */
-
-  opcode = md_chars_to_number (opcodeP, 4);
-  know (!(opcode & MEMB_BIT));
-
-  mode = MEMB_BIT | D_BIT;
-  if (opcode & MEMA_ABASE)
-    {
-      mode |= A_BIT;
     }
 
-  opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits */
-  opcode |= mode;		/* Set MEMB mode bits */
-
-  md_number_to_chars (opcodeP, opcode, 4);
-}				/* mema_to_memb() */
-
-/*****************************************************************************
-   parse_expr:		parse an expression
-
-  	Use base assembler's expression parser to parse an expression.
-  	It, unfortunately, runs off a global which we have to save/restore
-  	in order to make it work for us.
-
-  	An empty expression string is treated as an absolute 0.
-
-  	Sets O_illegal regardless of expression evaluation if entire input
-  	string is not consumed in the evaluation -- tolerate no dangling junk!
-
-  *************************************************************************** */
-static void
-parse_expr (textP, expP)
-     char *textP;		/* Text of expression to be parsed */
-     expressionS *expP;		/* Where to put the results of parsing */
-{
-  char *save_in;		/* Save global here */
-  symbolS *symP;
-
-  know (textP);
-
-  if (*textP == '\0')
-    {
-      /* Treat empty string as absolute 0 */
-      expP->X_add_symbol = expP->X_op_symbol = NULL;
-      expP->X_add_number = 0;
-      expP->X_op = O_constant;
-    }
-  else
-    {
-      save_in = input_line_pointer;	/* Save global */
-      input_line_pointer = textP;	/* Make parser work for us */
-
-      (void) expression (expP);
-      if ((size_t) (input_line_pointer - textP) != strlen (textP))
-	{
-	  /* Did not consume all of the input */
-	  expP->X_op = O_illegal;
-	}
-      symP = expP->X_add_symbol;
-      if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
-	{
-	  /* Register name in an expression */
-	  /* FIXME: this isn't much of a check any more.  */
-	  expP->X_op = O_illegal;
-	}
-
-      input_line_pointer = save_in;	/* Restore global */
-    }
+  /* Nothing worked.  */
+  syntax ();
+  regopP->mode = 0;		/* Register r0 is always a good one.  */
+  regopP->n = 0;
+  regopP->special = 0;
 }
 
-/*****************************************************************************
-   parse_ldcont:
-  	Parse and replace a 'ldconst' pseudo-instruction with an appropriate
-  	i80960 instruction.
+/* get_ispec:	parse a memory operand for an index specification
+   
+   Here, an "index specification" is taken to be anything surrounded
+   by square brackets and NOT followed by anything else.
 
-  	Assumes the input consists of:
-  		arg[0]	opcode mnemonic ('ldconst')
-  		arg[1]  first operand (constant)
-  		arg[2]	name of register to be loaded
-
-  	Replaces opcode and/or operands as appropriate.
-
-  	Returns the new number of arguments, or -1 on failure.
+   If it's found, detach it from the input string, remove the surrounding
+   square brackets, and return a pointer to it.  Otherwise, return NULL.  */
 
-  *************************************************************************** */
-static int
-parse_ldconst (arg)
-     char *arg[];		/* See above */
+static char *
+get_ispec (char *textP)  /* Pointer to memory operand from source instruction, no white space.  */
+	   
 {
-  int n;			/* Constant to be loaded */
-  int shift;			/* Shift count for "shlo" instruction */
-  static char buf[5];		/* Literal for first operand */
-  static char buf2[5];		/* Literal for second operand */
-  expressionS e;		/* Parsed expression */
+  /* Points to start of index specification.  */
+  char *start;
+  /* Points to end of index specification.  */
+  char *end;
 
-  arg[3] = NULL;		/* So we can tell at the end if it got used or not */
+  /* Find opening square bracket, if any.  */
+  start = strchr (textP, '[');
 
-  parse_expr (arg[1], &e);
-  switch (e.X_op)
+  if (start != NULL)
     {
-    default:
-      /* We're dependent on one or more symbols -- use "lda" */
-      arg[0] = "lda";
-      break;
-
-    case O_constant:
-      /* Try the following mappings:
-       *      ldconst 0,<reg>  ->mov  0,<reg>
-       *        ldconst 31,<reg> ->mov  31,<reg>
-       *        ldconst 32,<reg> ->addo 1,31,<reg>
-       *        ldconst 62,<reg> ->addo 31,31,<reg>
-       *        ldconst 64,<reg> ->shlo 8,3,<reg>
-       *        ldconst -1,<reg> ->subo 1,0,<reg>
-       *        ldconst -31,<reg>->subo 31,0,<reg>
-       *
-       * anything else becomes:
-       *        lda xxx,<reg>
-       */
-      n = offs (e);
-      if ((0 <= n) && (n <= 31))
-	{
-	  arg[0] = "mov";
-
-	}
-      else if ((-31 <= n) && (n <= -1))
-	{
-	  arg[0] = "subo";
-	  arg[3] = arg[2];
-	  sprintf (buf, "%d", -n);
-	  arg[1] = buf;
-	  arg[2] = "0";
-
-	}
-      else if ((32 <= n) && (n <= 62))
-	{
-	  arg[0] = "addo";
-	  arg[3] = arg[2];
-	  arg[1] = "31";
-	  sprintf (buf, "%d", n - 31);
-	  arg[2] = buf;
+      /* Eliminate '[', detach from rest of operand.  */
+      *start++ = '\0';
 
-	}
-      else if ((shift = shift_ok (n)) != 0)
-	{
-	  arg[0] = "shlo";
-	  arg[3] = arg[2];
-	  sprintf (buf, "%d", shift);
-	  arg[1] = buf;
-	  sprintf (buf2, "%d", n >> shift);
-	  arg[2] = buf2;
+      end = strchr (start, ']');
 
-	}
+      if (end == NULL)
+	as_bad (_("unmatched '['"));
       else
 	{
-	  arg[0] = "lda";
+	  /* Eliminate ']' and make sure it was the last thing
+	     in the string.  */
+	  *end = '\0';
+	  if (*(end + 1) != '\0')
+	    as_bad (_("garbage after index spec ignored"));
 	}
-      break;
-
-    case O_illegal:
-      as_bad (_("invalid constant"));
-      return -1;
-      break;
     }
-  return (arg[3] == 0) ? 2 : 3;
+  return start;
 }
 
-/*****************************************************************************
-   parse_memop:	parse a memory operand
+/* parse_memop:	parse a memory operand
 
   	This routine is based on the observation that the 4 mode bits of the
   	MEMB format, taken individually, have fairly consistent meaning:
@@ -1967,24 +874,22 @@ parse_ldconst (arg)
 
   	The other thing to observe is that we parse from the right, peeling
   	things * off as we go:  first any index spec, then any abase, then
-  	the displacement.
+  	the displacement.  */
 
-  *************************************************************************** */
 static void
-parse_memop (memP, argP, optype)
-     memS *memP;		/* Where to put the results */
-     char *argP;		/* Text of the operand to be parsed */
-     int optype;		/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
+parse_memop (memS *memP,	/* Where to put the results.  */
+	     char *argP,	/* Text of the operand to be parsed.  */
+	     int optype)	/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16.  */
 {
-  char *indexP;			/* Pointer to index specification with "[]" removed */
-  char *p;			/* Temp char pointer */
-  char iprel_flag;		/* True if this is an IP-relative operand */
-  int regnum;			/* Register number */
+  char *indexP;			/* Pointer to index specification with "[]" removed.  */
+  char *p;			/* Temp char pointer.  */
+  char iprel_flag;		/* True if this is an IP-relative operand.  */
+  int regnum;			/* Register number.  */
   /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
      (0,1,2,3,4 respectively).  */
   int scale;
-  int mode;			/* MEMB mode bits */
-  int *intP;			/* Pointer to register number */
+  int mode;			/* MEMB mode bits.  */
+  int *intP;			/* Pointer to register number.  */
 
   /* The following table contains the default scale factors for each
      type of memory instruction.  It is accessed using (optype-MEM1)
@@ -2023,21 +928,14 @@ parse_memop (memP, argP, optype)
 	  *p++ = '\0';		/* Eliminate '*' */
 
 	  /* Now indexP->a '\0'-terminated register name,
-	     * and p->a scale factor.
-	   */
+	     and p->a scale factor.  */
 
 	  if (!strcmp (p, "16"))
-	    {
-	      scale = 16;
-	    }
+	    scale = 16;
 	  else if (strchr ("1248", *p) && (p[1] == '\0'))
-	    {
-	      scale = *p - '0';
-	    }
+	    scale = *p - '0';
 	  else
-	    {
-	      scale = -1;
-	    }
+	    scale = -1;
 	}
 
       regnum = get_regnum (indexP);	/* Get index reg. # */
@@ -2047,7 +945,7 @@ parse_memop (memP, argP, optype)
 	  return;
 	}
 
-      /* Convert scale to its binary encoding */
+      /* Convert scale to its binary encoding.  */
       switch (scale)
 	{
 	case 1:
@@ -2070,11 +968,11 @@ parse_memop (memP, argP, optype)
 	  return;
 	};
 
-      memP->opcode |= scale | regnum;	/* Set index bits in opcode */
-      mode |= I_BIT;		/* Found a valid index spec */
+      memP->opcode |= scale | regnum;	/* Set index bits in opcode.  */
+      mode |= I_BIT;			/* Found a valid index spec.  */
     }
 
-  /* Any abase (Register Indirect) specification present? */
+  /* Any abase (Register Indirect) specification present?  */
   if ((p = strrchr (argP, '(')) != NULL)
     {
       /* "(" is there -- does it start a legal abase spec?  If not, it
@@ -2082,14 +980,12 @@ parse_memop (memP, argP, optype)
       intP = (int *) hash_find (areg_hash, p);
       if (intP != NULL)
 	{
-	  /* Got an abase here */
+	  /* Got an abase here.  */
 	  regnum = *intP;
-	  *p = '\0';		/* discard register spec */
+	  *p = '\0';		/* Discard register spec.  */
 	  if (regnum == IPREL)
-	    {
-	      /* We have to specialcase ip-rel mode */
-	      iprel_flag = 1;
-	    }
+	    /* We have to specialcase ip-rel mode.  */
+	    iprel_flag = 1;
 	  else
 	    {
 	      memP->opcode |= regnum << 14;
@@ -2098,29 +994,25 @@ parse_memop (memP, argP, optype)
 	}
     }
 
-  /* Any expression present? */
+  /* Any expression present?  */
   memP->e = argP;
   if (*argP != '\0')
-    {
-      mode |= D_BIT;
-    }
+    mode |= D_BIT;
 
-  /* Special-case ip-relative addressing */
+  /* Special-case ip-relative addressing.  */
   if (iprel_flag)
     {
       if (mode & I_BIT)
-	{
-	  syntax ();
-	}
+	syntax ();
       else
 	{
-	  memP->opcode |= 5 << 10;	/* IP-relative mode */
+	  memP->opcode |= 5 << 10;	/* IP-relative mode.  */
 	  memP->disp = 32;
 	}
       return;
     }
 
-  /* Handle all other modes */
+  /* Handle all other modes.  */
   switch (mode)
     {
     case D_BIT | A_BIT:
@@ -2146,7 +1038,7 @@ parse_memop (memP, argP, optype)
       break;
 
     case A_BIT | I_BIT:
-      /* set MEMB bit in mode, and OR in mode bits */
+      /* set MEMB bit in mode, and OR in mode bits.  */
       memP->opcode |= mode | MEMB_BIT;
       break;
 
@@ -2156,7 +1048,7 @@ parse_memop (memP, argP, optype)
       /* Fall into next case.  */
     case D_BIT | A_BIT | I_BIT:
     case D_BIT | I_BIT:
-      /* set MEMB bit in mode, and OR in mode bits */
+      /* Set MEMB bit in mode, and OR in mode bits.  */
       memP->opcode |= mode | MEMB_BIT;
       memP->disp = 32;
       break;
@@ -2167,174 +1059,262 @@ parse_memop (memP, argP, optype)
     }
 }
 
-/*****************************************************************************
-   parse_po:	parse machine-dependent pseudo-op
+/* Generate a MEMA- or MEMB-format instruction.  */
 
-  	This is a top-level routine for machine-dependent pseudo-ops.  It slurps
-  	up the rest of the input line, breaks out the individual arguments,
-  	and dispatches them to the correct handler.
-  *************************************************************************** */
 static void
-parse_po (po_num)
-     int po_num;		/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC */
+mem_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
+	 struct i960_opcode *oP,/* Pointer to description of instruction.  */
+	 int callx)		/* Is this a callx opcode.  */
 {
-  /* Pointers operands, with no embedded whitespace.
-     arg[0] unused, arg[1-3]->operands */
-  char *args[4];
-  int n_ops;			/* Number of operands */
-  char *p;			/* Pointer to beginning of unparsed argument string */
-  char eol;			/* Character that indicated end of line */
+  int i;			/* Loop counter.  */
+  struct regop regop;		/* Description of register operand.  */
+  char opdesc;			/* Operand descriptor byte.  */
+  memS instr;			/* Description of binary to be output.  */
+  char *outP;			/* Where the binary was output to.  */
+  expressionS expr;		/* Parsed expression.  */
+  /* ->description of deferred address fixup.  */
+  fixS *fixP;
 
-  extern char is_end_of_line[];
+#ifdef OBJ_COFF
+  /* COFF support isn't in place yet for callx relaxing.  */
+  callx = 0;
+#endif
 
-  /* Advance input pointer to end of line.  */
-  p = input_line_pointer;
-  while (!is_end_of_line[(unsigned char) *input_line_pointer])
-    {
-      input_line_pointer++;
-    }
-  eol = *input_line_pointer;	/* Save end-of-line char */
-  *input_line_pointer = '\0';	/* Terminate argument list */
+  memset (&instr, '\0', sizeof (memS));
+  instr.opcode = oP->opcode;
 
-  /* Parse out operands */
-  n_ops = get_args (p, args);
-  if (n_ops == -1)
+  /* Process operands.  */
+  for (i = 1; i <= oP->num_ops; i++)
     {
-      return;
+      opdesc = oP->operand[i - 1];
+
+      if (MEMOP (opdesc))
+	parse_memop (&instr, args[i], oP->format);
+      else
+	{
+	  parse_regop (&regop, args[i], opdesc);
+	  instr.opcode |= regop.n << 19;
+	}
     }
 
-  /* Dispatch to correct handler */
-  switch (po_num)
+  /* Parse the displacement; this must be done before emitting the
+     opcode, in case it is an expression using `.'.  */
+  parse_expr (instr.e, &expr);
+
+  /* Output opcode.  */
+  outP = emit (instr.opcode);
+
+  if (instr.disp == 0)
+    return;
+
+  /* Process the displacement.  */
+  switch (expr.X_op)
     {
-    case S_SYSPROC:
-      s_sysproc (n_ops, args);
+    case O_illegal:
+      as_bad (_("expression syntax error"));
       break;
-    case S_LEAFPROC:
-      s_leafproc (n_ops, args);
+
+    case O_constant:
+      if (instr.disp == 32)
+	(void) emit (offs (expr));	/* Output displacement.  */
+      else
+	{
+	  /* 12-bit displacement.  */
+	  if (offs (expr) & ~0xfff)
+	    {
+	      /* Won't fit in 12 bits: convert already-output
+	         instruction to MEMB format, output
+	         displacement.  */
+	      mema_to_memb (outP);
+	      (void) emit (offs (expr));
+	    }
+	  else
+	    {
+	      /* WILL fit in 12 bits:  OR into opcode and
+	         overwrite the binary we already put out.  */
+	      instr.opcode |= offs (expr);
+	      md_number_to_chars (outP, instr.opcode, 4);
+	    }
+	}
       break;
+
     default:
-      BAD_CASE (po_num);
+      if (instr.disp == 12)
+	/* Displacement is dependent on a symbol, whose value
+	   may change at link time.  We HAVE to reserve 32 bits.
+	   Convert already-output opcode to MEMB format.  */
+	mema_to_memb (outP);
+
+      /* Output 0 displacement and set up address fixup for when
+         this symbol's value becomes known.  */
+      outP = emit ((long) 0);
+      fixP = fix_new_exp (frag_now,
+			  outP - frag_now->fr_literal,
+			  4, & expr, 0, NO_RELOC);
+      /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
+         being in the instruction stream, specifically as part of a callx
+         instruction.  */
+      fixP->fx_bsr = callx;
       break;
     }
-
-  /* Restore eol, so line numbers get updated correctly.  Base
-     assembler assumes we leave input pointer pointing at char
-     following the eol.  */
-  *input_line_pointer++ = eol;
 }
 
-/*****************************************************************************
-   parse_regop: parse a register operand.
+/* targ_has_iclass:
 
-  	In case of illegal operand, issue a message and return some valid
-  	information so instruction processing can continue.
-  *************************************************************************** */
-static void
-parse_regop (regopP, optext, opdesc)
-     struct regop *regopP;	/* Where to put description of register operand */
-     char *optext;		/* Text of operand */
-     char opdesc;		/* Descriptor byte:  what's legal for this operand */
+   Return TRUE iff the target architecture supports the indicated
+   class of instructions.  */
+
+static int
+targ_has_iclass (int ic) /* Instruction class;  one of:
+			    I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2.  */
 {
-  int n;			/* Register number */
-  expressionS e;		/* Parsed expression */
+  iclasses_seen |= ic;
 
-  /* See if operand is a register */
-  n = get_regnum (optext);
-  if (n >= 0)
+  switch (architecture)
     {
-      if (IS_RG_REG (n))
+    case ARCH_KA:
+      return ic & (I_BASE | I_KX);
+    case ARCH_KB:
+      return ic & (I_BASE | I_KX | I_FP | I_DEC);
+    case ARCH_MC:
+      return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
+    case ARCH_CA:
+      return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
+    case ARCH_JX:
+      return ic & (I_BASE | I_CX2 | I_JX);
+    case ARCH_HX:
+      return ic & (I_BASE | I_CX2 | I_JX | I_HX);
+    default:
+      if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
+	  && (iclasses_seen & (I_CX | I_CX2)))
 	{
-	  /* global or local register */
-	  if (!REG_ALIGN (opdesc, n))
-	    {
-	      as_bad (_("unaligned register"));
-	    }
-	  regopP->n = n;
-	  regopP->mode = 0;
-	  regopP->special = 0;
-	  return;
+	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
+	  iclasses_seen &= ~ic;
 	}
-      else if (IS_FP_REG (n) && FP_OK (opdesc))
+      return 1;
+    }
+}
+
+/* shift_ok:
+   Determine if a "shlo" instruction can be used to implement a "ldconst".
+   This means that some number X < 32 can be shifted left to produce the
+   constant of interest.
+
+   Return the shift count, or 0 if we can't do it.
+   Caller calculates X by shifting original constant right 'shift' places.  */
+
+static int
+shift_ok (int n)		/* The constant of interest.  */
+{
+  int shift;			/* The shift count.  */
+
+  if (n <= 0)
+    /* Can't do it for negative numbers.  */
+    return 0;
+
+  /* Shift 'n' right until a 1 is about to be lost.  */
+  for (shift = 0; (n & 1) == 0; shift++)
+    n >>= 1;
+
+  if (n >= 32)
+    return 0;
+
+  return shift;
+}
+
+/* parse_ldcont:
+   Parse and replace a 'ldconst' pseudo-instruction with an appropriate
+   i80960 instruction.
+
+   Assumes the input consists of:
+  		arg[0]	opcode mnemonic ('ldconst')
+  		arg[1]  first operand (constant)
+  		arg[2]	name of register to be loaded
+
+   Replaces opcode and/or operands as appropriate.
+
+   Returns the new number of arguments, or -1 on failure.  */
+
+static int
+parse_ldconst (char *arg[])	/* See above.  */
+{
+  int n;			/* Constant to be loaded.  */
+  int shift;			/* Shift count for "shlo" instruction.  */
+  static char buf[5];		/* Literal for first operand.  */
+  static char buf2[5];		/* Literal for second operand.  */
+  expressionS e;		/* Parsed expression.  */
+
+  arg[3] = NULL;		/* So we can tell at the end if it got used or not.  */
+
+  parse_expr (arg[1], &e);
+  switch (e.X_op)
+    {
+    default:
+      /* We're dependent on one or more symbols -- use "lda".  */
+      arg[0] = "lda";
+      break;
+
+    case O_constant:
+      /* Try the following mappings:
+              ldconst   0,<reg>  -> mov  0,<reg>
+              ldconst  31,<reg>  -> mov  31,<reg>
+              ldconst  32,<reg>  -> addo 1,31,<reg>
+              ldconst  62,<reg>  -> addo 31,31,<reg>
+              ldconst  64,<reg>  -> shlo 8,3,<reg>
+              ldconst  -1,<reg>  -> subo 1,0,<reg>
+              ldconst -31,<reg>  -> subo 31,0,<reg>
+        
+         Anything else becomes:
+                lda xxx,<reg>.  */
+      n = offs (e);
+      if ((0 <= n) && (n <= 31))
+	arg[0] = "mov";
+      else if ((-31 <= n) && (n <= -1))
 	{
-	  /* Floating point register, and it's allowed */
-	  regopP->n = n - FP0;
-	  regopP->mode = 1;
-	  regopP->special = 0;
-	  return;
+	  arg[0] = "subo";
+	  arg[3] = arg[2];
+	  sprintf (buf, "%d", -n);
+	  arg[1] = buf;
+	  arg[2] = "0";
 	}
-      else if (IS_SF_REG (n) && SFR_OK (opdesc))
+      else if ((32 <= n) && (n <= 62))
 	{
-	  /* Special-function register, and it's allowed */
-	  regopP->n = n - SF0;
-	  regopP->mode = 0;
-	  regopP->special = 1;
-	  if (!targ_has_sfr (regopP->n))
-	    {
-	      as_bad (_("no such sfr in this architecture"));
-	    }
-	  return;
+	  arg[0] = "addo";
+	  arg[3] = arg[2];
+	  arg[1] = "31";
+	  sprintf (buf, "%d", n - 31);
+	  arg[2] = buf;
 	}
-    }
-  else if (LIT_OK (opdesc))
-    {
-      /* How about a literal?  */
-      regopP->mode = 1;
-      regopP->special = 0;
-      if (FP_OK (opdesc))
-	{			/* floating point literal acceptable */
-	  /* Skip over 0f, 0d, or 0e prefix */
-	  if ((optext[0] == '0')
-	      && (optext[1] >= 'd')
-	      && (optext[1] <= 'f'))
-	    {
-	      optext += 2;
-	    }
-
-	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
-	    {
-	      regopP->n = 0x10;
-	      return;
-	    }
-	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
-	    {
-	      regopP->n = 0x16;
-	      return;
-	    }
-
+      else if ((shift = shift_ok (n)) != 0)
+	{
+	  arg[0] = "shlo";
+	  arg[3] = arg[2];
+	  sprintf (buf, "%d", shift);
+	  arg[1] = buf;
+	  sprintf (buf2, "%d", n >> shift);
+	  arg[2] = buf2;
 	}
       else
-	{			/* fixed point literal acceptable */
-	  parse_expr (optext, &e);
-	  if (e.X_op != O_constant
-	      || (offs (e) < 0) || (offs (e) > 31))
-	    {
-	      as_bad (_("illegal literal"));
-	      offs (e) = 0;
-	    }
-	  regopP->n = offs (e);
-	  return;
-	}
-    }
+	arg[0] = "lda";
+      break;
 
-  /* Nothing worked */
-  syntax ();
-  regopP->mode = 0;		/* Register r0 is always a good one */
-  regopP->n = 0;
-  regopP->special = 0;
-}				/* parse_regop() */
+    case O_illegal:
+      as_bad (_("invalid constant"));
+      return -1;
+      break;
+    }
+  return (arg[3] == 0) ? 2 : 3;
+}
 
-/*****************************************************************************
-   reg_fmt:	generate a REG-format instruction
+/* reg_fmt:	generate a REG-format instruction.  */
 
-  *************************************************************************** */
 static void
-reg_fmt (args, oP)
-     char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
-     struct i960_opcode *oP;	/* Pointer to description of instruction */
+reg_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
+	 struct i960_opcode *oP)/* Pointer to description of instruction.  */
 {
-  long instr;			/* Binary to be output */
-  struct regop regop;		/* Description of register operand */
-  int n_ops;			/* Number of operands */
+  long instr;			/* Binary to be output.  */
+  struct regop regop;		/* Description of register operand.  */
+  int n_ops;			/* Number of operands.  */
 
   instr = oP->opcode;
   n_ops = oP->num_ops;
@@ -2346,19 +1326,16 @@ reg_fmt (args, oP)
       if ((n_ops == 1) && !(instr & M3))
 	{
 	  /* 1-operand instruction in which the dst field should
-	     * be used (instead of src1).
-	   */
+	     be used (instead of src1).  */
 	  regop.n <<= 19;
 	  if (regop.special)
-	    {
-	      regop.mode = regop.special;
-	    }
+	    regop.mode = regop.special;
 	  regop.mode <<= 13;
 	  regop.special = 0;
 	}
       else
 	{
-	  /* regop.n goes in bit 0, needs no shifting */
+	  /* regop.n goes in bit 0, needs no shifting.  */
 	  regop.mode <<= 11;
 	  regop.special <<= 5;
 	}
@@ -2372,13 +1349,10 @@ reg_fmt (args, oP)
       if ((n_ops == 2) && !(instr & M3))
 	{
 	  /* 2-operand instruction in which the dst field should
-	     * be used instead of src2).
-	   */
+	     be used instead of src2).  */
 	  regop.n <<= 19;
 	  if (regop.special)
-	    {
-	      regop.mode = regop.special;
-	    }
+	    regop.mode = regop.special;
 	  regop.mode <<= 13;
 	  regop.special = 0;
 	}
@@ -2394,24 +1368,595 @@ reg_fmt (args, oP)
     {
       parse_regop (&regop, args[3], oP->operand[2]);
       if (regop.special)
-	{
-	  regop.mode = regop.special;
-	}
+	regop.mode = regop.special;
       instr |= (regop.n <<= 19) | (regop.mode <<= 13);
     }
   emit (instr);
 }
 
-/*****************************************************************************
-   relax_cobr:
-  	Replace cobr instruction in a code fragment with equivalent branch and
-  	compare instructions, so it can reach beyond a 13-bit displacement.
-  	Set up an address fix/relocation for the new branch instruction.
+/* get_args:	break individual arguments out of comma-separated list
+
+   Input assumptions:
+  	- all comments and labels have been removed
+  	- all strings of whitespace have been collapsed to a single blank.
+  	- all character constants ('x') have been replaced with decimal
+
+   Output:
+  	args[0] is untouched. args[1] points to first operand, etc. All args:
+  	- are NULL-terminated
+  	- contain no whitespace
+
+   Return value:
+   Number of operands (0,1,2, or 3) or -1 on error.  */
+
+static int
+get_args (char *p, 	/* Pointer to comma-separated operands; Mucked by us.  */
+	  char *args[]) /* Output arg: pointers to operands placed in args[1-3].
+			   Must accommodate 4 entries (args[0-3]).  */
+
+{
+  int n;		/* Number of operands.  */
+  char *to;
+
+  /* Skip lead white space.  */
+  while (*p == ' ')
+    p++;
+
+  if (*p == '\0')
+    return 0;
+
+  n = 1;
+  args[1] = p;
+
+  /* Squeze blanks out by moving non-blanks toward start of string.
+     Isolate operands, whenever comma is found.  */
+  to = p;
+  while (*p != '\0')
+    {
+      if (*p == ' '
+	  && (! ISALNUM (p[1])
+	      || ! ISALNUM (p[-1])))
+	p++;
+      else if (*p == ',')
+	{
+	  /* Start of operand.  */
+	  if (n == 3)
+	    {
+	      as_bad (_("too many operands"));
+	      return -1;
+	    }
+	  *to++ = '\0';		/* Terminate argument.  */
+	  args[++n] = to;	/* Start next argument.  */
+	  p++;
+	}
+      else
+	*to++ = *p++;
+    }
+  *to = '\0';
+  return n;
+}
+
+/* i_scan:	perform lexical scan of ascii assembler instruction.
+
+   Input assumptions:
+  	- input string is an i80960 instruction (not a pseudo-op)
+  	- all comments and labels have been removed
+  	- all strings of whitespace have been collapsed to a single blank.
+
+   Output:
+  	args[0] points to opcode, other entries point to operands. All strings:
+  	- are NULL-terminated
+  	- contain no whitespace
+  	- have character constants ('x') replaced with a decimal number
+
+   Return value:
+     Number of operands (0,1,2, or 3) or -1 on error.  */
+
+static int
+i_scan (char *iP,     /* Pointer to ascii instruction;  Mucked by us.  */
+	char *args[]) /* Output arg: pointers to opcode and operands placed here.
+			 Must accommodate 4 entries.  */
+{
+  /* Isolate opcode.  */
+  if (*(iP) == ' ')
+    iP++;
+
+  args[0] = iP;
+  for (; *iP != ' '; iP++)
+    {
+      if (*iP == '\0')
+	{
+	  /* There are no operands.  */
+	  if (args[0] == iP)
+	    {
+	      /* We never moved: there was no opcode either!  */
+	      as_bad (_("missing opcode"));
+	      return -1;
+	    }
+	  return 0;
+	}
+    }
+  *iP++ = '\0';
+  return (get_args (iP, args));
+}
+
+static void
+brcnt_emit (void)
+{
+  /* Emit call to "increment" routine.  */
+  ctrl_fmt (BR_CNT_FUNC, CALL, 1);
+  /* Emit inline counter to be incremented.  */
+  emit (0);
+}
+
+static char *
+brlab_next (void)
+{
+  static char buf[20];
+
+  sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
+  return buf;
+}
+
+static void
+ctrl_fmt (char *targP,		/* Pointer to text of lone operand (if any).  */
+	  long opcode,		/* Template of instruction.  */
+	  int num_ops)		/* Number of operands.  */
+{
+  int instrument;		/* TRUE iff we should add instrumentation to track
+				   how often the branch is taken.  */
+
+  if (num_ops == 0)
+    emit (opcode);		/* Output opcode.  */
+  else
+    {
+      instrument = instrument_branches && (opcode != CALL)
+	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
+
+      if (instrument)
+	{
+	  brcnt_emit ();
+	  colon (brlab_next ());
+	}
+
+      /* The operand MUST be an ip-relative displacement. Parse it
+         and set up address fix for the instruction we just output.  */
+      get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
+
+      if (instrument)
+	brcnt_emit ();
+    }
+}
+
+static void
+cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
+	  char *arg[],
+	  /* Opcode, with branch-prediction bits already set if necessary.  */
+	  long opcode,
+	  /* Pointer to description of instruction.  */
+	  struct i960_opcode *oP)
+{
+  long instr;			/* 32-bit instruction.  */
+  struct regop regop;		/* Description of register operand.  */
+  int n;			/* Number of operands.  */
+  int var_frag;			/* 1 if varying length code fragment should
+				     be emitted;  0 if an address fix
+				        should be emitted.  */
+
+  instr = opcode;
+  n = oP->num_ops;
+
+  if (n >= 1)
+    {
+      /* First operand (if any) of a COBR is always a register
+	 operand.  Parse it.  */
+      parse_regop (&regop, arg[1], oP->operand[0]);
+      instr |= (regop.n << 19) | (regop.mode << 13);
+    }
+
+  if (n >= 2)
+    {
+      /* Second operand (if any) of a COBR is always a register
+	 operand.  Parse it.  */
+      parse_regop (&regop, arg[2], oP->operand[1]);
+      instr |= (regop.n << 14) | regop.special;
+    }
+
+  if (n < 3)
+    emit (instr);
+  else
+    {
+      if (instrument_branches)
+	{
+	  brcnt_emit ();
+	  colon (brlab_next ());
+	}
+
+      /* A third operand to a COBR is always a displacement.  Parse
+         it; if it's relaxable (a cobr "j" directive, or any cobr
+         other than bbs/bbc when the "-norelax" option is not in use)
+         set up a variable code fragment; otherwise set up an address
+         fix.  */
+      var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
+      get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
+
+      if (instrument_branches)
+	brcnt_emit ();
+    }
+}
+
+/* Assumptions about the passed-in text:
+  	- all comments, labels removed
+  	- text is an instruction
+  	- all white space compressed to single blanks
+  	- all character constants have been replaced with decimal.  */
+
+void
+md_assemble (char *textP)
+{
+  /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
+     mnemonic arg[1-3]->operands, with char constants replaced by
+     decimal numbers.  */
+  char *args[4];
+  /* Number of instruction operands.  */
+  int n_ops;
+  /* Pointer to instruction description.  */
+  struct i960_opcode *oP;
+  /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
+     or ".t").  */
+  int branch_predict;
+  /* Setting of branch-prediction bit(s) to be OR'd into instruction
+     opcode of CTRL/COBR format instructions.  */
+  long bp_bits;
+  /* Offset of last character in opcode mnemonic.  */
+  int n;
+  const char *bp_error_msg = _("branch prediction invalid on this opcode");
+
+  /* Parse instruction into opcode and operands.  */
+  memset (args, '\0', sizeof (args));
+
+  n_ops = i_scan (textP, args);
+
+  if (n_ops == -1)
+    return;			/* Error message already issued.  */
+
+  /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction.  */
+  if (!strcmp (args[0], "ldconst"))
+    {
+      n_ops = parse_ldconst (args);
+      if (n_ops == -1)
+	return;
+    }
+
+  /* Check for branch-prediction suffix on opcode mnemonic, strip it off.  */
+  n = strlen (args[0]) - 1;
+  branch_predict = 0;
+  bp_bits = 0;
+
+  if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
+    {
+      /* We could check here to see if the target architecture
+	 supports branch prediction, but why bother?  The bit will
+	 just be ignored by processors that don't use it.  */
+      branch_predict = 1;
+      bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
+      args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
+    }
+
+  /* Look up opcode mnemonic in table and check number of operands.
+     Check that opcode is legal for the target architecture.  If all
+     looks good, assemble instruction.  */
+  oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
+  if (!oP || !targ_has_iclass (oP->iclass))
+    as_bad (_("invalid opcode, \"%s\"."), args[0]);
+  else if (n_ops != oP->num_ops)
+    as_bad (_("improper number of operands.  expecting %d, got %d"),
+	    oP->num_ops, n_ops);
+  else
+    {
+      switch (oP->format)
+	{
+	case FBRA:
+	case CTRL:
+	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
+	  if (oP->format == FBRA)
+	    /* Now generate a 'bno' to same arg */
+	    ctrl_fmt (args[1], BNO | bp_bits, 1);
+	  break;
+	case COBR:
+	case COJ:
+	  cobr_fmt (args, oP->opcode | bp_bits, oP);
+	  break;
+	case REG:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  reg_fmt (args, oP);
+	  break;
+	case MEM1:
+	  if (args[0][0] == 'c' && args[0][1] == 'a')
+	    {
+	      if (branch_predict)
+		as_warn (bp_error_msg);
+	      mem_fmt (args, oP, 1);
+	      break;
+	    }
+	case MEM2:
+	case MEM4:
+	case MEM8:
+	case MEM12:
+	case MEM16:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  mem_fmt (args, oP, 0);
+	  break;
+	case CALLJ:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  /* Output opcode & set up "fixup" (relocation); flag
+	     relocation as 'callj' type.  */
+	  know (oP->num_ops == 1);
+	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
+	  break;
+	default:
+	  BAD_CASE (oP->format);
+	  break;
+	}
+    }
+}
+
+void
+md_number_to_chars (char *buf,
+		    valueT value,
+		    int n)
+{
+  number_to_chars_littleendian (buf, value, n);
+}
+
+#define MAX_LITTLENUMS	6
+#define LNUM_SIZE	sizeof (LITTLENUM_TYPE)
+
+/* md_atof:	convert ascii to floating point
+
+   Turn a string at input_line_pointer into a floating point constant of type
+   'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
+   emitted is returned at 'sizeP'.  An error message is returned, or a pointer
+   to an empty message if OK.
+
+   Note we call the i386 floating point routine, rather than complicating
+   things with more files or symbolic links.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  int prec;
+  char *t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+      prec = 4;
+      break;
+
+    case 't':
+    case 'T':
+      prec = 5;
+      type = 'x';		/* That's what atof_ieee() understands.  */
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * LNUM_SIZE;
+
+  /* Output the LITTLENUMs in REVERSE order in accord with i80960
+     word-order.  (Dunno why atof_ieee doesn't do it in the right
+     order in the first place -- probably because it's a hack of
+     atof_m68k.)  */
+  for (wordP = words + prec - 1; prec--;)
+    {
+      md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+static void
+md_number_to_imm (char *buf, long val, int n)
+{
+  md_number_to_chars (buf, val, n);
+}
+
+static void
+md_number_to_field (char *instrP,		/* Pointer to instruction to be fixed.  */
+		    long val,			/* Address fixup value.  */
+		    bit_fixS *bfixP)		/* Description of bit field to be fixed up.  */
+{
+  int numbits;			/* Length of bit field to be fixed.  */
+  long instr;			/* 32-bit instruction to be fixed-up.  */
+  long sign;			/* 0 or -1, according to sign bit of 'val'.  */
+
+  /* Convert instruction back to host byte order.  */
+  instr = md_chars_to_number (instrP, 4);
+
+  /* Surprise! -- we stored the number of bits to be modified rather
+     than a pointer to a structure.  */
+  numbits = (int) (size_t) bfixP;
+  if (numbits == 1)
+    /* This is a no-op, stuck here by reloc_callj().  */
+    return;
+
+  know ((numbits == 13) || (numbits == 24));
+
+  /* Propagate sign bit of 'val' for the given number of bits.  Result
+     should be all 0 or all 1.  */
+  sign = val >> ((int) numbits - 1);
+  if (((val < 0) && (sign != -1))
+      || ((val > 0) && (sign != 0)))
+    as_bad (_("Fixup of %ld too large for field width of %d"),
+	    val, numbits);
+  else
+    {
+      /* Put bit field into instruction and write back in target
+         * byte order.  */
+      val &= ~(-1 << (int) numbits);	/* Clear unused sign bits.  */
+      instr |= val;
+      md_number_to_chars (instrP, instr, 4);
+    }
+}
+
+
+/* md_parse_option
+  	Invocation line includes a switch not recognized by the base assembler.
+  	See if it's a processor-specific option.  For the 960, these are:
+
+  	-norelax:
+  		Conditional branch instructions that require displacements
+  		greater than 13 bits (or that have external targets) should
+  		generate errors.  The default is to replace each such
+  		instruction with the corresponding compare (or chkbit) and
+  		branch instructions.  Note that the Intel "j" cobr directives
+  		are ALWAYS "de-optimized" in this way when necessary,
+  		regardless of the setting of this option.
+
+  	-b:
+  		Add code to collect information about branches taken, for
+  		later optimization of branch prediction bits by a separate
+  		tool.  COBR and CNTL format instructions have branch
+  		prediction bits (in the CX architecture);  if "BR" represents
+  		an instruction in one of these classes, the following rep-
+  		resents the code generated by the assembler:
+
+  			call	<increment routine>
+  			.word	0	# pre-counter
+  		Label:  BR
+  			call	<increment routine>
+  			.word	0	# post-counter
+
+  		A table of all such "Labels" is also generated.
+
+  	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
+  		Select the 80960 architecture.  Instructions or features not
+  		supported by the selected architecture cause fatal errors.
+  		The default is to generate code for any instruction or feature
+  		that is supported by SOME version of the 960 (even if this
+  		means mixing architectures!).  */
+
+const char *md_shortopts = "A:b";
+struct option md_longopts[] =
+{
+#define OPTION_LINKRELAX (OPTION_MD_BASE)
+  {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
+  {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
+#define OPTION_NORELAX (OPTION_MD_BASE + 1)
+  {"norelax", no_argument, NULL, OPTION_NORELAX},
+  {"no-relax", no_argument, NULL, OPTION_NORELAX},
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+struct tabentry
+{
+  char *flag;
+  int arch;
+};
+static const struct tabentry arch_tab[] =
+{
+  {"KA", ARCH_KA},
+  {"KB", ARCH_KB},
+  {"SA", ARCH_KA},		/* Synonym for KA.  */
+  {"SB", ARCH_KB},		/* Synonym for KB.  */
+  {"KC", ARCH_MC},		/* Synonym for MC.  */
+  {"MC", ARCH_MC},
+  {"CA", ARCH_CA},
+  {"JX", ARCH_JX},
+  {"HX", ARCH_HX},
+  {NULL, 0}
+};
+
+int
+md_parse_option (int c, char *arg)
+{
+  switch (c)
+    {
+    case OPTION_LINKRELAX:
+      linkrelax = 1;
+      flag_keep_locals = 1;
+      break;
+
+    case OPTION_NORELAX:
+      norelax = 1;
+      break;
+
+    case 'b':
+      instrument_branches = 1;
+      break;
+
+    case 'A':
+      {
+	const struct tabentry *tp;
+	char *p = arg;
+
+	for (tp = arch_tab; tp->flag != NULL; tp++)
+	  if (!strcmp (p, tp->flag))
+	    break;
+
+	if (tp->flag == NULL)
+	  {
+	    as_bad (_("invalid architecture %s"), p);
+	    return 0;
+	  }
+	else
+	  architecture = tp->arch;
+      }
+      break;
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  int i;
 
-  *************************************************************************** */
+  fprintf (stream, _("I960 options:\n"));
+  for (i = 0; arch_tab[i].flag; i++)
+    fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
+  fprintf (stream, _("\n\
+			specify variant of 960 architecture\n\
+-b			add code to collect statistics about branches taken\n\
+-link-relax		preserve individual alignment directives so linker\n\
+			can do relaxing (b.out format only)\n\
+-no-relax		don't alter compare-and-branch instructions for\n\
+			long displacements\n"));
+}
+
+/* relax_cobr:
+   Replace cobr instruction in a code fragment with equivalent branch and
+   compare instructions, so it can reach beyond a 13-bit displacement.
+   Set up an address fix/relocation for the new branch instruction.  */
 
 /* This "conditional jump" table maps cobr instructions into
    equivalent compare and branch opcodes.  */
+
 static const
 struct
 {
@@ -2440,39 +1985,37 @@ coj[] =
 };
 
 static void
-relax_cobr (fragP)
-     register fragS *fragP;	/* fragP->fr_opcode is assumed to point to
-				 * the cobr instruction, which comes at the
-				 * end of the code fragment.
-				 */
+relax_cobr (fragS *fragP)	/* fragP->fr_opcode is assumed to point to
+				   the cobr instruction, which comes at the
+				   end of the code fragment.  */
 {
   int opcode, src1, src2, m1, s2;
-  /* Bit fields from cobr instruction */
-  long bp_bits;			/* Branch prediction bits from cobr instruction */
-  long instr;			/* A single i960 instruction */
-  /* ->instruction to be replaced */
+  /* Bit fields from cobr instruction.  */
+  long bp_bits;			/* Branch prediction bits from cobr instruction.  */
+  long instr;			/* A single i960 instruction.  */
+  /* ->instruction to be replaced.  */
   char *iP;
-  fixS *fixP;			/* Relocation that can be done at assembly time */
+  fixS *fixP;			/* Relocation that can be done at assembly time.  */
 
-  /* PICK UP & PARSE COBR INSTRUCTION */
+  /* Pick up & parse cobr instruction.  */
   iP = fragP->fr_opcode;
   instr = md_chars_to_number (iP, 4);
-  opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index */
+  opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index.  */
   src1 = (instr >> 19) & 0x1f;
   m1 = (instr >> 13) & 1;
   s2 = instr & 1;
   src2 = (instr >> 14) & 0x1f;
   bp_bits = instr & BP_MASK;
 
-  /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
+  /* Generate and output compare instruction.  */
   instr = coj[opcode].compare
     | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
   md_number_to_chars (iP, instr, 4);
 
-  /* OUTPUT BRANCH INSTRUCTION */
+  /* Output branch instruction.  */
   md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
 
-  /* SET UP ADDRESS FIXUP/RELOCATION */
+  /* Set up address fixup/relocation.  */
   fixP = fix_new (fragP,
 		  iP + 4 - fragP->fr_literal,
 		  4,
@@ -2481,81 +2024,165 @@ relax_cobr (fragP)
 		  1,
 		  NO_RELOC);
 
-  fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field */
+  fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field.  */
 
   fragP->fr_fix += 4;
   frag_wane (fragP);
 }
 
-/*****************************************************************************
-   reloc_callj:	Relocate a 'callj' instruction
-
-  	This is a "non-(GNU)-standard" machine-dependent hook.  The base
-  	assembler calls it when it decides it can relocate an address at
-  	assembly time instead of emitting a relocation directive.
+/* md_convert_frag:
 
-  	Check to see if the relocation involves a 'callj' instruction to a:
-  	    sysproc:	Replace the default 'call' instruction with a 'calls'
-  	    leafproc:	Replace the default 'call' instruction with a 'bal'.
-  	    other proc:	Do nothing.
+   Called by base assembler after address relaxation is finished:  modify
+   variable fragments according to how much relaxation was done.
 
-  	See b.out.h for details on the 'n_other' field in a symbol structure.
+   If the fragment substate is still 1, a 13-bit displacement was enough
+   to reach the symbol in question.  Set up an address fixup, but otherwise
+   leave the cobr instruction alone.
 
-   IMPORTANT!:
-  	Assumes the caller has already figured out, in the case of a leafproc,
-  	to use the 'bal' entry point, and has substituted that symbol into the
-  	passed fixup structure.
+   If the fragment substate is 2, a 13-bit displacement was not enough.
+   Replace the cobr with a two instructions (a compare and a branch).  */
 
-  *************************************************************************** */
-int
-reloc_callj (fixP)
-     /* Relocation that can be done at assembly time */
-     fixS *fixP;
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
-  /* Points to the binary for the instruction being relocated.  */
-  char *where;
+  /* Structure describing needed address fix.  */
+  fixS *fixP;
 
-  if (!fixP->fx_tcbit)
+  switch (fragP->fr_subtype)
     {
-      /* This wasn't a callj instruction in the first place */
-      return 0;
+    case 1:
+      /* Leave single cobr instruction.  */
+      fixP = fix_new (fragP,
+		      fragP->fr_opcode - fragP->fr_literal,
+		      4,
+		      fragP->fr_symbol,
+		      fragP->fr_offset,
+		      1,
+		      NO_RELOC);
+
+      fixP->fx_bit_fixP = (bit_fixS *) 13;	/* Size of bit field.  */
+      break;
+    case 2:
+      /* Replace cobr with compare/branch instructions.  */
+      relax_cobr (fragP);
+      break;
+    default:
+      BAD_CASE (fragP->fr_subtype);
+      break;
     }
+}
 
-  where = fixP->fx_frag->fr_literal + fixP->fx_where;
+/* md_estimate_size_before_relax:  How much does it look like *fragP will grow?
 
-  if (TC_S_IS_SYSPROC (fixP->fx_addsy))
-    {
-      /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
-         procedure number is (other-1).  */
-      md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
+   Called by base assembler just before address relaxation.
+   Return the amount by which the fragment will grow.
 
-      /* Nothing else needs to be done for this instruction.  Make
-         sure 'md_number_to_field()' will perform a no-op.  */
-      fixP->fx_bit_fixP = (bit_fixS *) 1;
-    }
-  else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
+   Any symbol that is now undefined will not become defined; cobr's
+   based on undefined symbols will have to be replaced with a compare
+   instruction and a branch instruction, and the code fragment will grow
+   by 4 bytes.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP, segT segment_type)
+{
+  /* If symbol is undefined in this segment, go to "relaxed" state
+     (compare and branch instructions instead of cobr) right now.  */
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
     {
-      /* Should not happen: see block comment above */
-      as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
+      relax_cobr (fragP);
+      return 4;
     }
-  else if (TC_S_IS_BALNAME (fixP->fx_addsy))
+
+  return md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
+
+/* md_ri_to_chars:
+   This routine exists in order to overcome machine byte-order problems
+   when dealing with bit-field entries in the relocation_info struct.
+
+   But relocation info will be used on the host machine only (only
+   executable code is actually downloaded to the i80960).  Therefore,
+   we leave it in host byte order.  */
+
+static void
+md_ri_to_chars (char *where, struct relocation_info *ri)
+{
+  host_number_to_chars (where, ri->r_address, 4);
+  host_number_to_chars (where + 4, ri->r_index, 3);
+#if WORDS_BIGENDIAN
+  where[7] = (ri->r_pcrel << 7
+	      | ri->r_length << 5
+	      | ri->r_extern << 4
+	      | ri->r_bsr << 3
+	      | ri->r_disp << 2
+	      | ri->r_callj << 1
+	      | ri->nuthin << 0);
+#else
+  where[7] = (ri->r_pcrel << 0
+	      | ri->r_length << 1
+	      | ri->r_extern << 3
+	      | ri->r_bsr << 4
+	      | ri->r_disp << 5
+	      | ri->r_callj << 6
+	      | ri->nuthin << 7);
+#endif
+}
+
+#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
+
+
+/* brtab_emit:	generate the fetch-prediction branch table.
+
+   See the comments above the declaration of 'br_cnt' for details on
+   branch-prediction instrumentation.
+
+   The code emitted here would be functionally equivalent to the following
+   example assembler source.
+
+  			.data
+  			.align	2
+  	   BR_TAB_NAME:
+  			.word	0		# link to next table
+  			.word	3		# length of table
+  			.word	LBRANCH0	# 1st entry in table proper
+  			.word	LBRANCH1
+  			.word	LBRANCH2  */
+
+void
+brtab_emit (void)
+{
+  int i;
+  char buf[20];
+  /* Where the binary was output to.  */
+  char *p;
+  /* Pointer to description of deferred address fixup.  */
+  fixS *fixP;
+
+  if (!instrument_branches)
+    return;
+
+  subseg_set (data_section, 0);	/*      .data */
+  frag_align (2, 0, 0);		/*      .align 2 */
+  record_alignment (now_seg, 2);
+  colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
+  emit (0);			/*      .word 0 #link to next table */
+  emit (br_cnt);		/*      .word n #length of table */
+
+  for (i = 0; i < br_cnt; i++)
     {
-      /* Replace 'call' with 'bal'; both instructions have the same
-         format, so calling code should complete relocation as if
-         nothing happened here.  */
-      md_number_to_chars (where, BAL, 4);
+      sprintf (buf, "%s%d", BR_LABEL_BASE, i);
+      p = emit (0);
+      fixP = fix_new (frag_now,
+		      p - frag_now->fr_literal,
+		      4, symbol_find (buf), 0, 0, NO_RELOC);
     }
-  else if (TC_S_IS_BADPROC (fixP->fx_addsy))
-    {
-      as_bad (_("Looks like a proc, but can't tell what kind.\n"));
-    }				/* switch on proc type */
-
-  /* else Symbol is neither a sysproc nor a leafproc */
-  return 0;
 }
 
-/*****************************************************************************
-   s_leafproc:	process .leafproc pseudo-op
+/* s_leafproc:	process .leafproc pseudo-op
 
   	.leafproc takes two arguments, the second one is optional:
   		arg[1]: name of 'call' entry point to leaf procedure
@@ -2566,39 +2193,33 @@ reloc_callj (fixP)
 
   	If there are 2 distinct arguments, we must make sure that the 'bal'
   	entry point immediately follows the 'call' entry point in the linked
-  	list of symbols.
+  	list of symbols.  */
 
-  *************************************************************************** */
 static void
-s_leafproc (n_ops, args)
-     int n_ops;			/* Number of operands */
-     char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
+s_leafproc (int n_ops,		/* Number of operands.  */
+	    char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
 {
-  symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol */
-  symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol */
+  symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol.  */
+  symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol.  */
 
   if ((n_ops != 1) && (n_ops != 2))
     {
       as_bad (_("should have 1 or 2 operands"));
       return;
-    }				/* Check number of arguments */
+    }
 
   /* Find or create symbol for 'call' entry point.  */
   callP = symbol_find_or_make (args[1]);
 
   if (TC_S_IS_CALLNAME (callP))
-    {
-      as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
-    }				/* is leafproc */
+    as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
 
   /* If that was the only argument, use it as the 'bal' entry point.
-     * Otherwise, mark it as the 'call' entry point and find or create
-     * another symbol for the 'bal' entry point.
-   */
+     Otherwise, mark it as the 'call' entry point and find or create
+     another symbol for the 'bal' entry point.  */
   if ((n_ops == 1) || !strcmp (args[1], args[2]))
     {
       TC_S_FORCE_TO_BALNAME (callP);
-
     }
   else
     {
@@ -2606,32 +2227,30 @@ s_leafproc (n_ops, args)
 
       balP = symbol_find_or_make (args[2]);
       if (TC_S_IS_CALLNAME (balP))
-	{
-	  as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
-	}
+	as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
+
       TC_S_FORCE_TO_BALNAME (balP);
 
 #ifndef OBJ_ELF
       tc_set_bal_of_call (callP, balP);
 #endif
-    }				/* if only one arg, or the args are the same */
+    }
 }
 
-/*
-   s_sysproc: process .sysproc pseudo-op
+/* s_sysproc: process .sysproc pseudo-op
+
+   .sysproc takes two arguments:
+     arg[1]: name of entry point to system procedure
+     arg[2]: 'entry_num' (index) of system procedure in the range
+     [0,31] inclusive.
 
-        .sysproc takes two arguments:
-                arg[1]: name of entry point to system procedure
-                arg[2]: 'entry_num' (index) of system procedure in the range
-                        [0,31] inclusive.
+   For [ab].out, we store the 'entrynum' in the 'n_other' field of
+   the symbol.  Since that entry is normally 0, we bias 'entrynum'
+   by adding 1 to it.  It must be unbiased before it is used.  */
 
-        For [ab].out, we store the 'entrynum' in the 'n_other' field of
-        the symbol.  Since that entry is normally 0, we bias 'entrynum'
-        by adding 1 to it.  It must be unbiased before it is used.  */
 static void
-s_sysproc (n_ops, args)
-     int n_ops;			/* Number of operands */
-     char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
+s_sysproc (int n_ops,		/* Number of operands.  */
+	   char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
 {
   expressionS exp;
   symbolS *symP;
@@ -2640,7 +2259,7 @@ s_sysproc (n_ops, args)
     {
       as_bad (_("should have two operands"));
       return;
-    }				/* bad arg count */
+    }
 
   /* Parse "entry_num" argument and check it for validity.  */
   parse_expr (args[2], &exp);
@@ -2652,127 +2271,130 @@ s_sysproc (n_ops, args)
       return;
     }
 
-  /* Find/make symbol and stick entry number (biased by +1) into it */
+  /* Find/make symbol and stick entry number (biased by +1) into it.  */
   symP = symbol_find_or_make (args[1]);
 
   if (TC_S_IS_SYSPROC (symP))
-    {
-      as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
-    }				/* redefining */
+    as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
 
-  TC_S_SET_SYSPROC (symP, offs (exp));	/* encode entry number */
+  TC_S_SET_SYSPROC (symP, offs (exp));	/* Encode entry number.  */
   TC_S_FORCE_TO_SYSPROC (symP);
 }
 
-/*****************************************************************************
-   shift_ok:
-  	Determine if a "shlo" instruction can be used to implement a "ldconst".
-  	This means that some number X < 32 can be shifted left to produce the
-  	constant of interest.
+/* parse_po:	parse machine-dependent pseudo-op
 
-  	Return the shift count, or 0 if we can't do it.
-  	Caller calculates X by shifting original constant right 'shift' places.
+   This is a top-level routine for machine-dependent pseudo-ops.  It slurps
+   up the rest of the input line, breaks out the individual arguments,
+   and dispatches them to the correct handler.  */
 
-  *************************************************************************** */
-static int
-shift_ok (n)
-     int n;			/* The constant of interest */
+static void
+parse_po (int po_num)	/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC.  */
 {
-  int shift;			/* The shift count */
+  /* Pointers operands, with no embedded whitespace.
+     arg[0] unused, arg[1-3]->operands.  */
+  char *args[4];
+  int n_ops;			/* Number of operands.  */
+  char *p;			/* Pointer to beginning of unparsed argument string.  */
+  char eol;			/* Character that indicated end of line.  */
 
-  if (n <= 0)
-    {
-      /* Can't do it for negative numbers */
-      return 0;
-    }
+  extern char is_end_of_line[];
 
-  /* Shift 'n' right until a 1 is about to be lost */
-  for (shift = 0; (n & 1) == 0; shift++)
-    {
-      n >>= 1;
-    }
+  /* Advance input pointer to end of line.  */
+  p = input_line_pointer;
+  while (!is_end_of_line[(unsigned char) *input_line_pointer])
+    input_line_pointer++;
 
-  if (n >= 32)
+  eol = *input_line_pointer;	/* Save end-of-line char.  */
+  *input_line_pointer = '\0';	/* Terminate argument list.  */
+
+  /* Parse out operands.  */
+  n_ops = get_args (p, args);
+  if (n_ops == -1)
+    return;
+
+  /* Dispatch to correct handler.  */
+  switch (po_num)
     {
-      return 0;
+    case S_SYSPROC:
+      s_sysproc (n_ops, args);
+      break;
+    case S_LEAFPROC:
+      s_leafproc (n_ops, args);
+      break;
+    default:
+      BAD_CASE (po_num);
+      break;
     }
-  return shift;
+
+  /* Restore eol, so line numbers get updated correctly.  Base
+     assembler assumes we leave input pointer pointing at char
+     following the eol.  */
+  *input_line_pointer++ = eol;
 }
 
-/* syntax: issue syntax error */
+/* reloc_callj:	Relocate a 'callj' instruction
 
-static void
-syntax ()
-{
-  as_bad (_("syntax error"));
-}				/* syntax() */
+  	This is a "non-(GNU)-standard" machine-dependent hook.  The base
+  	assembler calls it when it decides it can relocate an address at
+  	assembly time instead of emitting a relocation directive.
 
-/* targ_has_sfr:
+  	Check to see if the relocation involves a 'callj' instruction to a:
+  	    sysproc:	Replace the default 'call' instruction with a 'calls'
+  	    leafproc:	Replace the default 'call' instruction with a 'bal'.
+  	    other proc:	Do nothing.
 
-   Return TRUE iff the target architecture supports the specified
-   special-function register (sfr).  */
+  	See b.out.h for details on the 'n_other' field in a symbol structure.
 
-static int
-targ_has_sfr (n)
-     int n;			/* Number (0-31) of sfr */
+   IMPORTANT!:
+  	Assumes the caller has already figured out, in the case of a leafproc,
+  	to use the 'bal' entry point, and has substituted that symbol into the
+  	passed fixup structure.  */
+
+int
+reloc_callj (fixS *fixP)  /* Relocation that can be done at assembly time.  */    
 {
-  switch (architecture)
-    {
-    case ARCH_KA:
-    case ARCH_KB:
-    case ARCH_MC:
-    case ARCH_JX:
-      return 0;
-    case ARCH_HX:
-      return ((0 <= n) && (n <= 4));
-    case ARCH_CA:
-    default:
-      return ((0 <= n) && (n <= 2));
-    }
-}
+  /* Points to the binary for the instruction being relocated.  */
+  char *where;
 
-/* targ_has_iclass:
+  if (!fixP->fx_tcbit)
+    /* This wasn't a callj instruction in the first place.  */
+    return 0;
 
-   Return TRUE iff the target architecture supports the indicated
-   class of instructions.  */
-static int
-targ_has_iclass (ic)
-     /* Instruction class;  one of:
-        I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
-      */
-     int ic;
-{
-  iclasses_seen |= ic;
-  switch (architecture)
+  where = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  if (TC_S_IS_SYSPROC (fixP->fx_addsy))
     {
-    case ARCH_KA:
-      return ic & (I_BASE | I_KX);
-    case ARCH_KB:
-      return ic & (I_BASE | I_KX | I_FP | I_DEC);
-    case ARCH_MC:
-      return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
-    case ARCH_CA:
-      return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
-    case ARCH_JX:
-      return ic & (I_BASE | I_CX2 | I_JX);
-    case ARCH_HX:
-      return ic & (I_BASE | I_CX2 | I_JX | I_HX);
-    default:
-      if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
-	  && (iclasses_seen & (I_CX | I_CX2)))
-	{
-	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
-	  iclasses_seen &= ~ic;
-	}
-      return 1;
+      /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
+         procedure number is (other-1).  */
+      md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
+
+      /* Nothing else needs to be done for this instruction.  Make
+         sure 'md_number_to_field()' will perform a no-op.  */
+      fixP->fx_bit_fixP = (bit_fixS *) 1;
+    }
+  else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
+    {
+      /* Should not happen: see block comment above.  */
+      as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
+    }
+  else if (TC_S_IS_BALNAME (fixP->fx_addsy))
+    {
+      /* Replace 'call' with 'bal'; both instructions have the same
+         format, so calling code should complete relocation as if
+         nothing happened here.  */
+      md_number_to_chars (where, BAL, 4);
     }
+  else if (TC_S_IS_BADPROC (fixP->fx_addsy))
+    as_bad (_("Looks like a proc, but can't tell what kind.\n"));
+
+  /* Otherwise Symbol is neither a sysproc nor a leafproc.  */
+  return 0;
 }
 
 /* Handle the MRI .endian pseudo-op.  */
 
 static void
-s_endian (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_endian (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char c;
@@ -2794,8 +2416,7 @@ s_endian (ignore)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -2804,35 +2425,24 @@ md_undefined_symbol (name)
    On the i960, they're relative to the address of the instruction,
    which we have set up as the address of the fixup too.  */
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP,
+	       valueT *valP,
+	       segT seg ATTRIBUTE_UNUSED)
 {
   long val = *valP;
   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
 
   if (!fixP->fx_bit_fixP)
     {
-#ifndef BFD_ASSEMBLER
-      /* For callx, we always want to write out zero, and emit a
-	 symbolic relocation.  */
-      if (fixP->fx_bsr)
-	val = 0;
-
-      fixP->fx_addnumber = val;
-#endif
-
       md_number_to_imm (place, val, fixP->fx_size);
     }
-  else if ((int) fixP->fx_bit_fixP == 13
+  else if ((int) (size_t) fixP->fx_bit_fixP == 13
 	   && fixP->fx_addsy != NULL
 	   && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
     {
@@ -2853,10 +2463,9 @@ md_apply_fix3 (fixP, valP, seg)
 
 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
 void
-tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
+tc_bout_fix_to_chars (char *where,
+		      fixS *fixP,
+		      relax_addressT segment_address_in_file)
 {
   static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
   struct relocation_info ri;
@@ -2913,180 +2522,20 @@ tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
 
 #endif /* OBJ_AOUT or OBJ_BOUT */
 
-#if defined (OBJ_COFF) && defined (BFD)
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-  if (fixP->fx_bsr)
-    abort ();
-
-  if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
-    return R_RELLONG;
-
-  if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
-    return R_IPRMED;
-
-  abort ();
-  return 0;
-}
-
-int
-tc_coff_sizemachdep (frag)
-     fragS *frag;
-{
-  if (frag->fr_next)
-    return frag->fr_next->fr_address - frag->fr_address;
-  else
-    return 0;
-}
-#endif
-
 /* Align an address by rounding it up to the specified boundary.  */
+
 valueT
-md_section_align (seg, addr)
-     segT seg;
-     valueT addr;		/* Address to be rounded up */
+md_section_align (segT seg,
+		  valueT addr)		/* Address to be rounded up.  */
 {
   int align;
-#ifdef BFD_ASSEMBLER
+
   align = bfd_get_section_alignment (stdoutput, seg);
-#else
-  align = section_alignment[(int) seg];
-#endif
   return (addr + (1 << align) - 1) & (-1 << align);
 }
 
 extern int coff_flags;
 
-#ifdef OBJ_COFF
-void
-tc_headers_hook (headers)
-     object_headers *headers;
-{
-  switch (architecture)
-    {
-    case ARCH_KA:
-      coff_flags |= F_I960KA;
-      break;
-
-    case ARCH_KB:
-      coff_flags |= F_I960KB;
-      break;
-
-    case ARCH_MC:
-      coff_flags |= F_I960MC;
-      break;
-
-    case ARCH_CA:
-      coff_flags |= F_I960CA;
-      break;
-
-    case ARCH_JX:
-      coff_flags |= F_I960JX;
-      break;
-
-    case ARCH_HX:
-      coff_flags |= F_I960HX;
-      break;
-
-    default:
-      if (iclasses_seen == I_BASE)
-	coff_flags |= F_I960CORE;
-      else if (iclasses_seen & I_CX)
-	coff_flags |= F_I960CA;
-      else if (iclasses_seen & I_HX)
-	coff_flags |= F_I960HX;
-      else if (iclasses_seen & I_JX)
-	coff_flags |= F_I960JX;
-      else if (iclasses_seen & I_CX2)
-	coff_flags |= F_I960CA;
-      else if (iclasses_seen & I_MIL)
-	coff_flags |= F_I960MC;
-      else if (iclasses_seen & (I_DEC | I_FP))
-	coff_flags |= F_I960KB;
-      else
-	coff_flags |= F_I960KA;
-      break;
-    }
-
-  if (flag_readonly_data_in_text)
-    {
-      headers->filehdr.f_magic = I960RWMAGIC;
-      headers->aouthdr.magic = OMAGIC;
-    }
-  else
-    {
-      headers->filehdr.f_magic = I960ROMAGIC;
-      headers->aouthdr.magic = NMAGIC;
-    }				/* set magic numbers */
-}
-
-#endif /* OBJ_COFF */
-
-#ifndef BFD_ASSEMBLER
-
-/* Things going on here:
-
-   For bout, We need to assure a couple of simplifying
-   assumptions about leafprocs for the linker: the leafproc
-   entry symbols will be defined in the same assembly in
-   which they're declared with the '.leafproc' directive;
-   and if a leafproc has both 'call' and 'bal' entry points
-   they are both global or both local.
-
-   For coff, the call symbol has a second aux entry that
-   contains the bal entry point.  The bal symbol becomes a
-   label.
-
-   For coff representation, the call symbol has a second aux entry that
-   contains the bal entry point.  The bal symbol becomes a label.  */
-
-void
-tc_crawl_symbol_chain (headers)
-     object_headers *headers ATTRIBUTE_UNUSED;
-{
-  symbolS *symbolP;
-
-  for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
-    {
-#ifdef OBJ_COFF
-      if (TC_S_IS_SYSPROC (symbolP))
-	{
-	  /* second aux entry already contains the sysproc number */
-	  S_SET_NUMBER_AUXILIARY (symbolP, 2);
-	  S_SET_STORAGE_CLASS (symbolP, C_SCALL);
-	  S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
-	  continue;
-	}			/* rewrite sysproc */
-#endif /* OBJ_COFF */
-
-      if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
-	{
-	  continue;
-	}			/* Not a leafproc symbol */
-
-      if (!S_IS_DEFINED (symbolP))
-	{
-	  as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
-	}			/* undefined leaf */
-
-      if (TC_S_IS_CALLNAME (symbolP))
-	{
-	  symbolS *balP = tc_get_bal_of_call (symbolP);
-	  if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
-	    {
-	      S_SET_EXTERNAL (symbolP);
-	      S_SET_EXTERNAL (balP);
-	      as_warn (_("Warning: making leafproc entries %s and %s both global\n"),
-		       S_GET_NAME (symbolP), S_GET_NAME (balP));
-	    }			/* externality mismatch */
-	}			/* if callname */
-    }				/* walk the symbol chain */
-}
-
-#endif /* ! BFD_ASSEMBLER */
-
 /* For aout or bout, the bal immediately follows the call.
 
    For coff, we cheat and store a pointer to the bal symbol in the
@@ -3101,9 +2550,8 @@ tc_crawl_symbol_chain (headers)
 #endif
 
 void
-tc_set_bal_of_call (callP, balP)
-     symbolS *callP ATTRIBUTE_UNUSED;
-     symbolS *balP ATTRIBUTE_UNUSED;
+tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
+		    symbolS *balP ATTRIBUTE_UNUSED)
 {
   know (TC_S_IS_CALLNAME (callP));
   know (TC_S_IS_BALNAME (balP));
@@ -3117,8 +2565,7 @@ tc_set_bal_of_call (callP, balP)
 #ifdef OBJ_ABOUT
 
   /* If the 'bal' entry doesn't immediately follow the 'call'
-     * symbol, unlink it from the symbol list and re-insert it.
-   */
+     symbol, unlink it from the symbol list and re-insert it.  */
   if (symbol_next (callP) != balP)
     {
       symbol_remove (balP, &symbol_rootP, &symbol_lastP);
@@ -3132,8 +2579,7 @@ tc_set_bal_of_call (callP, balP)
 }
 
 symbolS *
-tc_get_bal_of_call (callP)
-     symbolS *callP ATTRIBUTE_UNUSED;
+tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
 {
   symbolS *retval;
 
@@ -3151,46 +2597,38 @@ tc_get_bal_of_call (callP)
 
   know (TC_S_IS_BALNAME (retval));
   return retval;
-}				/* _tc_get_bal_of_call() */
+}
 
 #ifdef OBJ_COFF
 void
-tc_coff_symbol_emit_hook (symbolP)
-     symbolS *symbolP ATTRIBUTE_UNUSED;
+tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
 {
   if (TC_S_IS_CALLNAME (symbolP))
     {
       symbolS *balP = tc_get_bal_of_call (symbolP);
 
-#if 0
-      /* second aux entry contains the bal entry point */
-      S_SET_NUMBER_AUXILIARY (symbolP, 2);
-#endif
       symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
       if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
 	S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
       else
 	S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
       S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
-      /* fix up the bal symbol */
+      /* Fix up the bal symbol.  */
       S_SET_STORAGE_CLASS (balP, C_LABEL);
-    }				/* only on calls */
+    }
 }
 #endif /* OBJ_COFF */
 
 void
-i960_handle_align (fragp)
-     fragS *fragp ATTRIBUTE_UNUSED;
+i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
 {
   if (!linkrelax)
     return;
 
 #ifndef OBJ_BOUT
-
   as_bad (_("option --link-relax is only supported in b.out format"));
   linkrelax = 0;
   return;
-
 #else
 
   /* The text section "ends" with another alignment reloc, to which we
@@ -3206,15 +2644,12 @@ i960_handle_align (fragp)
 }
 
 int
-i960_validate_fix (fixP, this_segment_type)
-     fixS *fixP;
-     segT this_segment_type ATTRIBUTE_UNUSED;
+i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
 {
   if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
     {
       /* Relocation should be done via the associated 'bal'
          entry point symbol.  */
-
       if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -3228,21 +2663,11 @@ i960_validate_fix (fixP, this_segment_type)
   return 1;
 }
 
-#ifdef BFD_ASSEMBLER
-
 /* From cgen.c:  */
 
-static short tc_bfd_fix2rtype PARAMS ((fixS *));
-
 static short
-tc_bfd_fix2rtype (fixP)
-     fixS *fixP;
+tc_bfd_fix2rtype (fixS *fixP)
 {
-#if 0
-  if (fixP->fx_bsr)
-    abort ();
-#endif
-
   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
     return BFD_RELOC_32;
 
@@ -3259,19 +2684,17 @@ tc_bfd_fix2rtype (fixP)
    FIXME: To what extent can we get all relevant targets to use this?  */
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
 {
   arelent * reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
 
-  /* HACK: Is this right? */
+  /* HACK: Is this right?  */
   fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
 
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  if (reloc->howto == NULL)
     {
       as_bad_where (fixP->fx_file, fixP->fx_line,
 		    "internal error: can't export reloc type %d (`%s')",
@@ -3282,7 +2705,7 @@ tc_gen_reloc (section, fixP)
 
   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
   reloc->addend = fixP->fx_addnumber;
@@ -3292,6 +2715,16 @@ tc_gen_reloc (section, fixP)
 
 /* end from cgen.c */
 
-#endif /* BFD_ASSEMBLER */
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"bss", s_lcomm, 1},
+  {"endian", s_endian, 0},
+  {"extended", float_cons, 't'},
+  {"leafproc", parse_po, S_LEAFPROC},
+  {"sysproc", parse_po, S_SYSPROC},
 
-/* end of tc-i960.c */
+  {"word", cons, 4},
+  {"quad", cons, 16},
+
+  {0, 0, 0}
+};
diff --git a/gas/config/tc-i960.h b/gas/config/tc-i960.h
index 59269359b67d..05db36e40d5c 100644
--- a/gas/config/tc-i960.h
+++ b/gas/config/tc-i960.h
@@ -1,6 +1,6 @@
 /* tc-i960.h - Basic 80960 instruction formats.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999,
-   2000, 2002, 2003
+   2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef TC_I960
 #define TC_I960 1
@@ -52,21 +52,12 @@
  */
 
 /* tailor gas */
-#define SYMBOLS_NEED_BACKPOINTERS
 #define LOCAL_LABELS_FB 1
 #define BITFIELD_CONS_EXPRESSIONS
 
 /* tailor the coff format */
-#define BFD_ARCH				bfd_arch_i960
-#define COFF_FLAGS				F_AR32WR
 #define COFF_MAGIC				I960ROMAGIC
-#define OBJ_COFF_SECTION_HEADER_HAS_ALIGNMENT
 #define OBJ_COFF_MAX_AUXENTRIES			(2)
-#define TC_COUNT_RELOC(FIX)			(!(FIX)->fx_done)
-#define TC_COFF_FIX2RTYPE(FIX)			tc_coff_fix2rtype (FIX)
-#define TC_COFF_SIZEMACHDEP(FRAGP)		tc_coff_sizemachdep (FRAGP)
-#define TC_COFF_SET_MACHINE(HDRS)		tc_headers_hook (HDRS)
-extern int tc_coff_sizemachdep PARAMS ((struct frag *));
 
 /* MEANING OF 'n_other' in the symbol record.
  *
@@ -172,10 +163,10 @@ extern int i960_validate_fix PARAMS ((struct fix *, segT));
 #define tc_fix_adjustable(FIX)		((FIX)->fx_bsr == 0)
 
 #ifndef OBJ_ELF
-/* Values passed to md_apply_fix3 sometimes include symbol values.  */
+/* Values passed to md_apply_fix sometimes include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) tc_fix_adjustable (FIX)
 #else
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 #endif
 
@@ -188,7 +179,6 @@ extern struct symbol *tc_get_bal_of_call PARAMS ((symbolS *));
 
 extern void i960_handle_align PARAMS ((struct frag *));
 #define HANDLE_ALIGN(FRAG)	i960_handle_align (FRAG)
-#define NEED_FX_R_TYPE
 #define NO_RELOC -1
 
 #define md_operand(x)
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index f5526c980102..426b60f589aa 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -1,5 +1,6 @@
 /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture.
-   Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /*
   TODO:
@@ -50,7 +51,14 @@
 
 #include "elf/ia64.h"
 
+#ifdef HAVE_LIMITS_H
+#include <limits.h>
+#endif
+
 #define NELEMS(a)	((int) (sizeof (a)/sizeof ((a)[0])))
+
+/* Some systems define MIN in, e.g., param.h.  */
+#undef MIN
 #define MIN(a,b)	((a) < (b) ? (a) : (b))
 
 #define NUM_SLOTS	4
@@ -116,7 +124,6 @@ enum reg_symbol
     IND_DTR,
     IND_ITR,
     IND_IBR,
-    IND_MEM,
     IND_MSR,
     IND_PKR,
     IND_PMC,
@@ -151,10 +158,15 @@ struct label_fix
 {
   struct label_fix *next;
   struct symbol *sym;
+  bfd_boolean dw2_mark_labels;
 };
 
+/* This is the endianness of the current section.  */
 extern int target_big_endian;
 
+/* This is the default endianness.  */
+static int default_big_endian = TARGET_BYTES_BIG_ENDIAN;
+
 void (*ia64_number_to_chars) PARAMS ((char *, valueT, int));
 
 static void ia64_float_to_chars_bigendian
@@ -169,6 +181,10 @@ static struct hash_control *alias_name_hash;
 static struct hash_control *secalias_hash;
 static struct hash_control *secalias_name_hash;
 
+/* List of chars besides those in app.c:symbol_chars that can start an
+   operand.  Used to prevent the scrubber eating vital white-space.  */
+const char ia64_symbol_chars[] = "@?";
+
 /* Characters which always start a comment.  */
 const char comment_chars[] = "";
 
@@ -177,7 +193,7 @@ const char line_comment_chars[] = "#";
 
 /* Characters which may be used to separate multiple commands on a
    single line.  */
-const char line_separator_chars[] = ";";
+const char line_separator_chars[] = ";{}";
 
 /* Characters which are used to indicate an exponent in a floating
    point number.  */
@@ -209,13 +225,26 @@ static struct
     struct hash_control *const_hash;	/* constant hash table */
     struct hash_control *entry_hash;    /* code entry hint hash table */
 
-    symbolS *regsym[REG_NUM];
-
     /* If X_op is != O_absent, the registername for the instruction's
        qualifying predicate.  If NULL, p0 is assumed for instructions
        that are predicatable.  */
     expressionS qp;
 
+    /* Optimize for which CPU.  */
+    enum
+      {
+	itanium1,
+	itanium2
+      } tune;
+
+    /* What to do when hint.b is used.  */
+    enum
+      {
+	hint_b_error,
+	hint_b_warning,
+	hint_b_ok
+      } hint_b;
+
     unsigned int
       manual_bundling : 1,
       debug_dv: 1,
@@ -226,6 +255,13 @@ static struct
       auto_align : 1,
       keep_pending_output : 1;
 
+    /* What to do when something is wrong with unwind directives.  */
+    enum
+      {
+	unwind_check_warning,
+	unwind_check_error
+      } unwind_check;
+
     /* Each bundle consists of up to three instructions.  We keep
        track of four most recent instructions so we can correctly set
        the end_of_insn_group for the last instruction in a bundle.  */
@@ -236,7 +272,8 @@ static struct
 	unsigned int
 	  end_of_insn_group : 1,
 	  manual_bundling_on : 1,
-	  manual_bundling_off : 1;
+	  manual_bundling_off : 1,
+	  loc_directive_seen : 1;
 	signed char user_template;	/* user-selected template, if any */
 	unsigned char qp_regno;		/* qualifying predicate */
 	/* This duplicates a good fraction of "struct fix" but we
@@ -286,31 +323,29 @@ static struct
 				       the current DV-checking block.  */
     int maxpaths;                   /* size currently allocated for
 				       entry_labels */
-    /* Support for hardware errata workarounds.  */
-
-    /* Record data about the last three insn groups.  */
-    struct group
-    {
-      /* B-step workaround.
-	 For each predicate register, this is set if the corresponding insn
-	 group conditionally sets this register with one of the affected
-	 instructions.  */
-      int p_reg_set[64];
-      /* B-step workaround.
-	 For each general register, this is set if the corresponding insn
-	 a) is conditional one one of the predicate registers for which
-	    P_REG_SET is 1 in the corresponding entry of the previous group,
-	 b) sets this general register with one of the affected
-	    instructions.  */
-      int g_reg_set_conditionally[128];
-    } last_groups[3];
-    int group_idx;
 
     int pointer_size;       /* size in bytes of a pointer */
     int pointer_size_shift; /* shift size of a pointer for alignment */
+
+    symbolS *indregsym[IND_RR - IND_CPUID + 1];
   }
 md;
 
+/* These are not const, because they are modified to MMI for non-itanium1
+   targets below.  */
+/* MFI bundle of nops.  */
+static unsigned char le_nop[16] =
+{
+  0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00
+};
+/* MFI bundle of nops with stop-bit.  */
+static unsigned char le_nop_stop[16] =
+{
+  0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+  0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00
+};
+
 /* application registers:  */
 
 #define AR_K0		0
@@ -319,33 +354,52 @@ md;
 #define AR_BSP		17
 #define AR_BSPSTORE	18
 #define AR_RNAT		19
+#define AR_FCR		21
+#define AR_EFLAG	24
+#define AR_CSD		25
+#define AR_SSD		26
+#define AR_CFLG		27
+#define AR_FSR		28
+#define AR_FIR		29
+#define AR_FDR		30
+#define AR_CCV		32
 #define AR_UNAT		36
 #define AR_FPSR		40
 #define AR_ITC		44
 #define AR_PFS		64
 #define AR_LC		65
+#define AR_EC		66
 
 static const struct
   {
     const char *name;
-    int regnum;
+    unsigned int regnum;
   }
 ar[] =
   {
-    {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3},
-    {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7},
-    {"ar.rsc",		16}, {"ar.bsp",		17},
-    {"ar.bspstore",	18}, {"ar.rnat",	19},
-    {"ar.fcr",		21}, {"ar.eflag",	24},
-    {"ar.csd",		25}, {"ar.ssd",		26},
-    {"ar.cflg",		27}, {"ar.fsr",		28},
-    {"ar.fir",		29}, {"ar.fdr",		30},
-    {"ar.ccv",		32}, {"ar.unat",	36},
-    {"ar.fpsr",		40}, {"ar.itc",		44},
-    {"ar.pfs",		64}, {"ar.lc",		65},
-    {"ar.ec",		66},
+    {"ar.k0",		AR_K0},		{"ar.k1",	AR_K0 + 1},
+    {"ar.k2",		AR_K0 + 2},	{"ar.k3",	AR_K0 + 3},
+    {"ar.k4",		AR_K0 + 4},	{"ar.k5",	AR_K0 + 5},
+    {"ar.k6",		AR_K0 + 6},	{"ar.k7",	AR_K7},
+    {"ar.rsc",		AR_RSC},	{"ar.bsp",	AR_BSP},
+    {"ar.bspstore",	AR_BSPSTORE},	{"ar.rnat",	AR_RNAT},
+    {"ar.fcr",		AR_FCR},	{"ar.eflag",	AR_EFLAG},
+    {"ar.csd",		AR_CSD},	{"ar.ssd",	AR_SSD},
+    {"ar.cflg",		AR_CFLG},	{"ar.fsr",	AR_FSR},
+    {"ar.fir",		AR_FIR},	{"ar.fdr",	AR_FDR},
+    {"ar.ccv",		AR_CCV},	{"ar.unat",	AR_UNAT},
+    {"ar.fpsr",		AR_FPSR},	{"ar.itc",	AR_ITC},
+    {"ar.pfs",		AR_PFS},	{"ar.lc",	AR_LC},
+    {"ar.ec",		AR_EC},
   };
 
+/* control registers:  */
+
+#define CR_DCR           0
+#define CR_ITM           1
+#define CR_IVA           2
+#define CR_PTA           8
+#define CR_GPTA          9
 #define CR_IPSR         16
 #define CR_ISR          17
 #define CR_IIP          19
@@ -355,49 +409,52 @@ ar[] =
 #define CR_IFS          23
 #define CR_IIM          24
 #define CR_IHA          25
+#define CR_LID          64
 #define CR_IVR          65
 #define CR_TPR          66
 #define CR_EOI          67
 #define CR_IRR0         68
 #define CR_IRR3         71
+#define CR_ITV          72
+#define CR_PMV          73
+#define CR_CMCV         74
 #define CR_LRR0         80
 #define CR_LRR1         81
 
-/* control registers:  */
 static const struct
   {
     const char *name;
-    int regnum;
+    unsigned int regnum;
   }
 cr[] =
   {
-    {"cr.dcr",	 0},
-    {"cr.itm",	 1},
-    {"cr.iva",	 2},
-    {"cr.pta",	 8},
-    {"cr.gpta",	 9},
-    {"cr.ipsr",	16},
-    {"cr.isr",	17},
-    {"cr.iip",	19},
-    {"cr.ifa",	20},
-    {"cr.itir",	21},
-    {"cr.iipa",	22},
-    {"cr.ifs",	23},
-    {"cr.iim",	24},
-    {"cr.iha",	25},
-    {"cr.lid",	64},
-    {"cr.ivr",	65},
-    {"cr.tpr",	66},
-    {"cr.eoi",	67},
-    {"cr.irr0",	68},
-    {"cr.irr1",	69},
-    {"cr.irr2",	70},
-    {"cr.irr3",	71},
-    {"cr.itv",	72},
-    {"cr.pmv",	73},
-    {"cr.cmcv",	74},
-    {"cr.lrr0",	80},
-    {"cr.lrr1",	81}
+    {"cr.dcr",	CR_DCR},
+    {"cr.itm",	CR_ITM},
+    {"cr.iva",	CR_IVA},
+    {"cr.pta",	CR_PTA},
+    {"cr.gpta",	CR_GPTA},
+    {"cr.ipsr",	CR_IPSR},
+    {"cr.isr",	CR_ISR},
+    {"cr.iip",	CR_IIP},
+    {"cr.ifa",	CR_IFA},
+    {"cr.itir",	CR_ITIR},
+    {"cr.iipa",	CR_IIPA},
+    {"cr.ifs",	CR_IFS},
+    {"cr.iim",	CR_IIM},
+    {"cr.iha",	CR_IHA},
+    {"cr.lid",	CR_LID},
+    {"cr.ivr",	CR_IVR},
+    {"cr.tpr",	CR_TPR},
+    {"cr.eoi",	CR_EOI},
+    {"cr.irr0",	CR_IRR0},
+    {"cr.irr1",	CR_IRR0 + 1},
+    {"cr.irr2",	CR_IRR0 + 2},
+    {"cr.irr3",	CR_IRR3},
+    {"cr.itv",	CR_ITV},
+    {"cr.pmv",	CR_PMV},
+    {"cr.cmcv",	CR_CMCV},
+    {"cr.lrr0",	CR_LRR0},
+    {"cr.lrr1",	CR_LRR1}
   };
 
 #define PSR_MFL         4
@@ -455,7 +512,7 @@ const_bits[] =
 static const struct
   {
     const char *name;
-    int regnum;
+    unsigned int regnum;
   }
 indirect_reg[] =
   {
@@ -508,10 +565,10 @@ pseudo_func[] =
     { "segrel",	PSEUDO_FUNC_RELOC, { 0 } },
     { "tprel",	PSEUDO_FUNC_RELOC, { 0 } },
     { "ltv",	PSEUDO_FUNC_RELOC, { 0 } },
-    { "", 0, { 0 } },	/* placeholder for FUNC_LT_FPTR_RELATIVE */
-    { "", 0, { 0 } },	/* placeholder for FUNC_LT_DTP_MODULE */
-    { "", 0, { 0 } },	/* placeholder for FUNC_LT_DTP_RELATIVE */
-    { "", 0, { 0 } },	/* placeholder for FUNC_LT_TP_RELATIVE */
+    { NULL, 0, { 0 } },	/* placeholder for FUNC_LT_FPTR_RELATIVE */
+    { NULL, 0, { 0 } },	/* placeholder for FUNC_LT_DTP_MODULE */
+    { NULL, 0, { 0 } },	/* placeholder for FUNC_LT_DTP_RELATIVE */
+    { NULL, 0, { 0 } },	/* placeholder for FUNC_LT_TP_RELATIVE */
     { "iplt",	PSEUDO_FUNC_RELOC, { 0 } },
 
     /* mbtype4 constants:  */
@@ -558,7 +615,7 @@ static const bfd_vma nop[IA64_NUM_UNITS] =
     0x0008000000LL,	/* M-unit nop */
     0x4000000000LL,	/* B-unit nop */
     0x0008000000LL,	/* F-unit nop */
-    0x0008000000LL,	/* L-"unit" nop */
+    0x0000000000LL,	/* L-"unit" nop immediate */
     0x0008000000LL,	/* X-unit nop */
   };
 
@@ -571,11 +628,6 @@ static char special_section_name[][20] =
     {".init_array"}, {".fini_array"}
   };
 
-static char *special_linkonce_name[] =
-  {
-    ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
-  };
-
 /* The best template for a particular sequence of up to three
    instructions:  */
 #define N	IA64_NUM_TYPES
@@ -634,7 +686,17 @@ static struct gr {
   unsigned known:1;
   int path;
   valueT value;
-} gr_values[128] = {{ 1, 0, 0 }};
+} gr_values[128] = {
+  {
+    1,
+#ifdef INT_MAX
+    INT_MAX,
+#else
+    (((1 << (8 * sizeof(gr_values->path) - 2)) - 1) << 1) + 1,
+#endif
+    0
+  }
+};
 
 /* Remember the alignment frag.  */
 static fragS *align_frag;
@@ -655,8 +717,6 @@ typedef struct unw_rec_list {
   unwind_record r;
   unsigned long slot_number;
   fragS *slot_frag;
-  unsigned long next_slot_number;
-  fragS *next_slot_frag;
   struct unw_rec_list *next;
 } unw_rec_list;
 
@@ -671,6 +731,12 @@ typedef struct label_prologue_count
   unsigned int prologue_count;
 } label_prologue_count;
 
+typedef struct proc_pending
+{
+  symbolS *sym;
+  struct proc_pending *next;
+} proc_pending;
+
 static struct
 {
   /* Maintain a list of unwind entries for the current function.  */
@@ -682,8 +748,7 @@ static struct
   unw_rec_list *current_entry;
 
   /* These are used to create the unwind table entry for this function.  */
-  symbolS *proc_start;
-  symbolS *proc_end;
+  proc_pending proc_pending;
   symbolS *info;		/* pointer to unwind info */
   symbolS *personality_routine;
   segT saved_text_seg;
@@ -691,17 +756,28 @@ static struct
   unsigned int force_unwind_entry : 1;	/* force generation of unwind entry? */
 
   /* TRUE if processing unwind directives in a prologue region.  */
-  int prologue;
-  int prologue_mask;
+  unsigned int prologue : 1;
+  unsigned int prologue_mask : 4;
+  unsigned int prologue_gr : 7;
+  unsigned int body : 1;
+  unsigned int insn : 1;
   unsigned int prologue_count;	/* number of .prologues seen so far */
   /* Prologue counts at previous .label_state directives.  */
   struct label_prologue_count * saved_prologue_counts;
+
+  /* List of split up .save-s.  */
+  unw_p_record *pending_saves;
 } unwind;
 
+/* The input value is a negated offset from psp, and specifies an address
+   psp - offset.  The encoded value is psp + 16 - (4 * offset).  Thus we
+   must add 16 and divide by 4 to get the encoded value.  */
+
+#define ENCODED_PSP_OFFSET(OFFSET) (((OFFSET) + 16) / 4)
+
 typedef void (*vbyte_func) PARAMS ((int, char *, char *));
 
 /* Forward declarations:  */
-static int ar_is_in_integer_unit PARAMS ((int regnum));
 static void set_section PARAMS ((char *name));
 static unsigned int set_regstack PARAMS ((unsigned int, unsigned int,
 					  unsigned int, unsigned int));
@@ -712,11 +788,9 @@ static void dot_proc PARAMS ((int));
 static void dot_fframe PARAMS ((int));
 static void dot_vframe PARAMS ((int));
 static void dot_vframesp PARAMS ((int));
-static void dot_vframepsp PARAMS ((int));
 static void dot_save PARAMS ((int));
 static void dot_restore PARAMS ((int));
 static void dot_restorereg PARAMS ((int));
-static void dot_restorereg_p PARAMS ((int));
 static void dot_handlerdata  PARAMS ((int));
 static void dot_unwentry PARAMS ((int));
 static void dot_altrp PARAMS ((int));
@@ -728,8 +802,6 @@ static void dot_savegf PARAMS ((int));
 static void dot_spill PARAMS ((int));
 static void dot_spillreg PARAMS ((int));
 static void dot_spillmem PARAMS ((int));
-static void dot_spillreg_p PARAMS ((int));
-static void dot_spillmem_p PARAMS ((int));
 static void dot_label_state PARAMS ((int));
 static void dot_copy_state PARAMS ((int));
 static void dot_unwabi PARAMS ((int));
@@ -744,7 +816,7 @@ static void dot_byteorder PARAMS ((int));
 static void dot_psr PARAMS ((int));
 static void dot_alias PARAMS ((int));
 static void dot_ln PARAMS ((int));
-static char *parse_section_name PARAMS ((void));
+static void cross_section PARAMS ((int ref, void (*cons) PARAMS((int)), int ua));
 static void dot_xdata PARAMS ((int));
 static void stmt_float_cons PARAMS ((int));
 static void stmt_cons_ua PARAMS ((int));
@@ -755,19 +827,19 @@ static void dot_xfloat_cons_ua PARAMS ((int));
 static void print_prmask PARAMS ((valueT mask));
 static void dot_pred_rel PARAMS ((int));
 static void dot_reg_val PARAMS ((int));
+static void dot_serialize PARAMS ((int));
 static void dot_dv_mode PARAMS ((int));
 static void dot_entry PARAMS ((int));
 static void dot_mem_offset PARAMS ((int));
-static void add_unwind_entry PARAMS((unw_rec_list *ptr));
-static symbolS *declare_register PARAMS ((const char *name, int regnum));
-static void declare_register_set PARAMS ((const char *, int, int));
+static void add_unwind_entry PARAMS((unw_rec_list *, int));
+static symbolS *declare_register PARAMS ((const char *name, unsigned int regnum));
+static void declare_register_set PARAMS ((const char *, unsigned int, unsigned int));
 static unsigned int operand_width PARAMS ((enum ia64_opnd));
 static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc,
 							int index,
 							expressionS *e));
-static int parse_operand PARAMS ((expressionS *e));
+static int parse_operand PARAMS ((expressionS *, int));
 static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *));
-static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit));
 static void build_insn PARAMS ((struct slot *, bfd_vma *));
 static void emit_one_bundle PARAMS ((void));
 static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT));
@@ -887,15 +959,11 @@ static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long));
 static unw_rec_list *output_epilogue PARAMS ((unsigned long));
 static unw_rec_list *output_label_state PARAMS ((unsigned long));
 static unw_rec_list *output_copy_state PARAMS ((unsigned long));
-static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int));
-static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int));
-static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
+static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int,
 						    unsigned int));
-static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int,
+static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int,
 						   unsigned int));
 static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int,
-					       unsigned int));
-static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int,
 						 unsigned int, unsigned int));
 static void process_one_record PARAMS ((unw_rec_list *, vbyte_func));
 static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func));
@@ -906,51 +974,29 @@ static unsigned long slot_index PARAMS ((unsigned long, fragS *,
 					 int));
 static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *));
 static void fixup_unw_records PARAMS ((unw_rec_list *, int));
-static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
-static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *));
-static void generate_unwind_image PARAMS ((const char *));
+static int parse_predicate_and_operand PARAMS ((expressionS *, unsigned *, const char *));
+static void convert_expr_to_ab_reg PARAMS ((const expressionS *, unsigned int *, unsigned int *, const char *, int));
+static void convert_expr_to_xy_reg PARAMS ((const expressionS *, unsigned int *, unsigned int *, const char *, int));
 static unsigned int get_saved_prologue_count PARAMS ((unsigned long));
 static void save_prologue_count PARAMS ((unsigned long, unsigned int));
 static void free_saved_prologue_counts PARAMS ((void));
 
-/* Build the unwind section name by appending the (possibly stripped)
-   text section NAME to the unwind PREFIX.  The resulting string
-   pointer is assigned to RESULT.  The string is allocated on the
-   stack, so this must be a macro...  */
-#define make_unw_section_name(special, text_name, result)		   \
-  {									   \
-    const char *_prefix = special_section_name[special];		   \
-    const char *_suffix = text_name;					   \
-    size_t _prefix_len, _suffix_len;					   \
-    char *_result;							   \
-    if (strncmp (text_name, ".gnu.linkonce.t.",				   \
-		 sizeof (".gnu.linkonce.t.") - 1) == 0)			   \
-      {									   \
-	_prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \
-	_suffix += sizeof (".gnu.linkonce.t.") - 1;			   \
-      }									   \
-    _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix);	   \
-    _result = alloca (_prefix_len + _suffix_len + 1);		   	   \
-    memcpy (_result, _prefix, _prefix_len);				   \
-    memcpy (_result + _prefix_len, _suffix, _suffix_len);		   \
-    _result[_prefix_len + _suffix_len] = '\0';				   \
-    result = _result;							   \
-  }									   \
-while (0)
-
-/* Determine if application register REGNUM resides in the integer
+/* Determine if application register REGNUM resides only in the integer
    unit (as opposed to the memory unit).  */
 static int
-ar_is_in_integer_unit (reg)
-     int reg;
+ar_is_only_in_integer_unit (int reg)
 {
   reg -= REG_AR;
+  return reg >= 64 && reg <= 111;
+}
 
-  return (reg == 64	/* pfs */
-	  || reg == 65	/* lc */
-	  || reg == 66	/* ec */
-	  /* ??? ias accepts and puts these in the integer unit.  */
-	  || (reg >= 112 && reg <= 127));
+/* Determine if application register REGNUM resides only in the memory 
+   unit (as opposed to the integer unit).  */
+static int
+ar_is_only_in_memory_unit (int reg)
+{
+  reg -= REG_AR;
+  return reg >= 0 && reg <= 47;
 }
 
 /* Switch to section NAME and create section if necessary.  It's
@@ -1019,12 +1065,6 @@ ia64_elf_section_type (str, len)
   if (STREQ ("unwind"))
     return SHT_IA_64_UNWIND;
 
-  if (STREQ ("init_array"))
-    return SHT_INIT_ARRAY;
-
-  if (STREQ ("fini_array"))
-    return SHT_FINI_ARRAY;
-
   return -1;
 #undef STREQ
 }
@@ -1065,6 +1105,7 @@ ia64_flush_insns ()
   segT saved_seg;
   subsegT saved_subseg;
   unw_rec_list *ptr;
+  bfd_boolean mark;
 
   if (!md.last_text_seg)
     return;
@@ -1078,18 +1119,23 @@ ia64_flush_insns ()
     emit_one_bundle ();		/* force out queued instructions */
 
   /* In case there are labels following the last instruction, resolve
-     those now:  */
+     those now.  */
+  mark = FALSE;
   for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next)
     {
-      S_SET_VALUE (lfix->sym, frag_now_fix ());
-      symbol_set_frag (lfix->sym, frag_now);
+      symbol_set_value_now (lfix->sym);
+      mark |= lfix->dw2_mark_labels;
     }
-  CURR_SLOT.label_fixups = 0;
-  for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
+  if (mark)
     {
-      S_SET_VALUE (lfix->sym, frag_now_fix ());
-      symbol_set_frag (lfix->sym, frag_now);
+      dwarf2_where (&CURR_SLOT.debug_line);
+      CURR_SLOT.debug_line.flags |= DWARF2_FLAG_BASIC_BLOCK;
+      dwarf2_gen_line_info (frag_now_fix (), &CURR_SLOT.debug_line);
     }
+  CURR_SLOT.label_fixups = 0;
+
+  for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next)
+    symbol_set_value_now (lfix->sym);
   CURR_SLOT.tag_fixups = 0;
 
   /* In case there are unwind directives following the last instruction,
@@ -1160,7 +1206,7 @@ ia64_cons_align (nbytes)
 }
 
 /* Output COUNT bytes to a memory location.  */
-static unsigned char *vbyte_mem_ptr = NULL;
+static char *vbyte_mem_ptr = NULL;
 
 void
 output_vbyte_mem (count, ptr, comment)
@@ -1337,7 +1383,7 @@ output_P4_format (f, imask, imask_size)
      unsigned long imask_size;
 {
   imask[0] = UNW_P4;
-  (*f) (imask_size, imask, NULL);
+  (*f) (imask_size, (char *) imask, NULL);
 }
 
 static void
@@ -1723,6 +1769,55 @@ output_X4_format (f, qp, ab, reg, x, y, treg, t)
   (*f) (count, bytes, NULL);
 }
 
+/* This function checks whether there are any outstanding .save-s and
+   discards them if so.  */
+
+static void
+check_pending_save (void)
+{
+  if (unwind.pending_saves)
+    {
+      unw_rec_list *cur, *prev;
+
+      as_warn ("Previous .save incomplete");
+      for (cur = unwind.list, prev = NULL; cur; )
+	if (&cur->r.record.p == unwind.pending_saves)
+	  {
+	    if (prev)
+	      prev->next = cur->next;
+	    else
+	      unwind.list = cur->next;
+	    if (cur == unwind.tail)
+	      unwind.tail = prev;
+	    if (cur == unwind.current_entry)
+	      unwind.current_entry = cur->next;
+	    /* Don't free the first discarded record, it's being used as
+	       terminator for (currently) br_gr and gr_gr processing, and
+	       also prevents leaving a dangling pointer to it in its
+	       predecessor.  */
+	    cur->r.record.p.grmask = 0;
+	    cur->r.record.p.brmask = 0;
+	    cur->r.record.p.frmask = 0;
+	    prev = cur->r.record.p.next;
+	    cur->r.record.p.next = NULL;
+	    cur = prev;
+	    break;
+	  }
+	else
+	  {
+	    prev = cur;
+	    cur = cur->next;
+	  }
+      while (cur)
+	{
+	  prev = cur;
+	  cur = cur->r.record.p.next;
+	  free (prev);
+	}
+      unwind.pending_saves = NULL;
+    }
+}
+
 /* This function allocates a record list structure, and initializes fields.  */
 
 static unw_rec_list *
@@ -1730,11 +1825,9 @@ alloc_record (unw_record_type t)
 {
   unw_rec_list *ptr;
   ptr = xmalloc (sizeof (*ptr));
-  ptr->next = NULL;
+  memset (ptr, 0, sizeof (*ptr));
   ptr->slot_number = SLOT_NUM_NOT_SET;
   ptr->r.type = t;
-  ptr->next_slot_number = 0;
-  ptr->next_slot_frag = 0;
   return ptr;
 }
 
@@ -1796,7 +1889,7 @@ output_psp_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (psp_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -1805,7 +1898,7 @@ output_psp_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (psp_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -1821,7 +1914,7 @@ output_rp_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (rp_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -1830,7 +1923,7 @@ output_rp_br (br)
      unsigned int br;
 {
   unw_rec_list *ptr = alloc_record (rp_br);
-  ptr->r.record.p.br = br;
+  ptr->r.record.p.r.br = br;
   return ptr;
 }
 
@@ -1839,7 +1932,7 @@ output_rp_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (rp_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -1848,7 +1941,7 @@ output_rp_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (rp_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -1864,7 +1957,7 @@ output_pfs_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (pfs_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -1873,7 +1966,7 @@ output_pfs_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (pfs_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -1882,7 +1975,7 @@ output_pfs_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (pfs_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -1898,7 +1991,7 @@ output_preds_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (preds_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -1907,7 +2000,7 @@ output_preds_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (preds_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -1916,7 +2009,7 @@ output_preds_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (preds_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -1925,8 +2018,24 @@ output_fr_mem (mask)
      unsigned int mask;
 {
   unw_rec_list *ptr = alloc_record (fr_mem);
-  ptr->r.record.p.rmask = mask;
-  return ptr;
+  unw_rec_list *cur = ptr;
+
+  ptr->r.record.p.frmask = mask;
+  unwind.pending_saves = &ptr->r.record.p;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      mask &= ~(mask & (~mask + 1));
+      if (!mask)
+	return ptr;
+      cur = alloc_record (fr_mem);
+      cur->r.record.p.frmask = mask;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.frmask ^= mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
@@ -1935,9 +2044,39 @@ output_frgr_mem (gr_mask, fr_mask)
      unsigned int fr_mask;
 {
   unw_rec_list *ptr = alloc_record (frgr_mem);
-  ptr->r.record.p.grmask = gr_mask;
-  ptr->r.record.p.frmask = fr_mask;
-  return ptr;
+  unw_rec_list *cur = ptr;
+
+  unwind.pending_saves = &cur->r.record.p;
+  cur->r.record.p.frmask = fr_mask;
+  while (fr_mask)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      fr_mask &= ~(fr_mask & (~fr_mask + 1));
+      if (!gr_mask && !fr_mask)
+	return ptr;
+      cur = alloc_record (frgr_mem);
+      cur->r.record.p.frmask = fr_mask;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.frmask ^= fr_mask;
+      prev->r.record.p.next = cur;
+    }
+  cur->r.record.p.grmask = gr_mask;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      gr_mask &= ~(gr_mask & (~gr_mask + 1));
+      if (!gr_mask)
+	return ptr;
+      cur = alloc_record (frgr_mem);
+      cur->r.record.p.grmask = gr_mask;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.grmask ^= gr_mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
@@ -1946,9 +2085,27 @@ output_gr_gr (mask, reg)
      unsigned int reg;
 {
   unw_rec_list *ptr = alloc_record (gr_gr);
+  unw_rec_list *cur = ptr;
+
   ptr->r.record.p.grmask = mask;
-  ptr->r.record.p.gr = reg;
-  return ptr;
+  ptr->r.record.p.r.gr = reg;
+  unwind.pending_saves = &ptr->r.record.p;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      mask &= ~(mask & (~mask + 1));
+      if (!mask)
+	return ptr;
+      cur = alloc_record (gr_gr);
+      cur->r.record.p.grmask = mask;
+      /* Indicate this record shouldn't be output.  */
+      cur->r.record.p.r.gr = REG_NUM;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.grmask ^= mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
@@ -1956,27 +2113,77 @@ output_gr_mem (mask)
      unsigned int mask;
 {
   unw_rec_list *ptr = alloc_record (gr_mem);
-  ptr->r.record.p.rmask = mask;
-  return ptr;
+  unw_rec_list *cur = ptr;
+
+  ptr->r.record.p.grmask = mask;
+  unwind.pending_saves = &ptr->r.record.p;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      mask &= ~(mask & (~mask + 1));
+      if (!mask)
+	return ptr;
+      cur = alloc_record (gr_mem);
+      cur->r.record.p.grmask = mask;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.grmask ^= mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
 output_br_mem (unsigned int mask)
 {
   unw_rec_list *ptr = alloc_record (br_mem);
+  unw_rec_list *cur = ptr;
+
   ptr->r.record.p.brmask = mask;
-  return ptr;
+  unwind.pending_saves = &ptr->r.record.p;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      mask &= ~(mask & (~mask + 1));
+      if (!mask)
+	return ptr;
+      cur = alloc_record (br_mem);
+      cur->r.record.p.brmask = mask;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.brmask ^= mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
-output_br_gr (save_mask, reg)
-     unsigned int save_mask;
+output_br_gr (mask, reg)
+     unsigned int mask;
      unsigned int reg;
 {
   unw_rec_list *ptr = alloc_record (br_gr);
-  ptr->r.record.p.brmask = save_mask;
-  ptr->r.record.p.gr = reg;
-  return ptr;
+  unw_rec_list *cur = ptr;
+
+  ptr->r.record.p.brmask = mask;
+  ptr->r.record.p.r.gr = reg;
+  unwind.pending_saves = &ptr->r.record.p;
+  for (;;)
+    {
+      unw_rec_list *prev = cur;
+
+      /* Clear least significant set bit.  */
+      mask &= ~(mask & (~mask + 1));
+      if (!mask)
+	return ptr;
+      cur = alloc_record (br_gr);
+      cur->r.record.p.brmask = mask;
+      /* Indicate this record shouldn't be output.  */
+      cur->r.record.p.r.gr = REG_NUM;
+      /* Retain only least significant bit.  */
+      prev->r.record.p.brmask ^= mask;
+      prev->r.record.p.next = cur;
+    }
 }
 
 static unw_rec_list *
@@ -1984,7 +2191,7 @@ output_spill_base (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (spill_base);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2000,7 +2207,7 @@ output_unat_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (unat_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2009,7 +2216,7 @@ output_unat_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (unat_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2018,7 +2225,7 @@ output_unat_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (unat_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2034,7 +2241,7 @@ output_lc_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (lc_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2043,7 +2250,7 @@ output_lc_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (lc_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2052,7 +2259,7 @@ output_lc_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (lc_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2068,7 +2275,7 @@ output_fpsr_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (fpsr_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2077,7 +2284,7 @@ output_fpsr_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (fpsr_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2086,7 +2293,7 @@ output_fpsr_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (fpsr_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2109,7 +2316,7 @@ output_priunat_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (priunat_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2118,7 +2325,7 @@ output_priunat_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (priunat_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2127,7 +2334,7 @@ output_priunat_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (priunat_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2143,7 +2350,7 @@ output_bsp_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (bsp_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2152,7 +2359,7 @@ output_bsp_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (bsp_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2161,7 +2368,7 @@ output_bsp_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (bsp_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2177,7 +2384,7 @@ output_bspstore_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (bspstore_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2186,7 +2393,7 @@ output_bspstore_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (bspstore_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2195,7 +2402,7 @@ output_bspstore_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (bspstore_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2211,7 +2418,7 @@ output_rnat_gr (gr)
      unsigned int gr;
 {
   unw_rec_list *ptr = alloc_record (rnat_gr);
-  ptr->r.record.p.gr = gr;
+  ptr->r.record.p.r.gr = gr;
   return ptr;
 }
 
@@ -2220,7 +2427,7 @@ output_rnat_psprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (rnat_psprel);
-  ptr->r.record.p.pspoff = offset / 4;
+  ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset);
   return ptr;
 }
 
@@ -2229,7 +2436,7 @@ output_rnat_sprel (offset)
      unsigned int offset;
 {
   unw_rec_list *ptr = alloc_record (rnat_sprel);
-  ptr->r.record.p.spoff = offset / 4;
+  ptr->r.record.p.off.sp = offset / 4;
   return ptr;
 }
 
@@ -2269,88 +2476,47 @@ output_copy_state (unsigned long label)
 }
 
 static unw_rec_list *
-output_spill_psprel (ab, reg, offset)
-     unsigned int ab;
-     unsigned int reg;
-     unsigned int offset;
-{
-  unw_rec_list *ptr = alloc_record (spill_psprel);
-  ptr->r.record.x.ab = ab;
-  ptr->r.record.x.reg = reg;
-  ptr->r.record.x.pspoff = offset / 4;
-  return ptr;
-}
-
-static unw_rec_list *
-output_spill_sprel (ab, reg, offset)
-     unsigned int ab;
-     unsigned int reg;
-     unsigned int offset;
-{
-  unw_rec_list *ptr = alloc_record (spill_sprel);
-  ptr->r.record.x.ab = ab;
-  ptr->r.record.x.reg = reg;
-  ptr->r.record.x.spoff = offset / 4;
-  return ptr;
-}
-
-static unw_rec_list *
-output_spill_psprel_p (ab, reg, offset, predicate)
+output_spill_psprel (ab, reg, offset, predicate)
      unsigned int ab;
      unsigned int reg;
      unsigned int offset;
      unsigned int predicate;
 {
-  unw_rec_list *ptr = alloc_record (spill_psprel_p);
+  unw_rec_list *ptr = alloc_record (predicate ? spill_psprel_p : spill_psprel);
   ptr->r.record.x.ab = ab;
   ptr->r.record.x.reg = reg;
-  ptr->r.record.x.pspoff = offset / 4;
+  ptr->r.record.x.where.pspoff = ENCODED_PSP_OFFSET (offset);
   ptr->r.record.x.qp = predicate;
   return ptr;
 }
 
 static unw_rec_list *
-output_spill_sprel_p (ab, reg, offset, predicate)
+output_spill_sprel (ab, reg, offset, predicate)
      unsigned int ab;
      unsigned int reg;
      unsigned int offset;
      unsigned int predicate;
 {
-  unw_rec_list *ptr = alloc_record (spill_sprel_p);
+  unw_rec_list *ptr = alloc_record (predicate ? spill_sprel_p : spill_sprel);
   ptr->r.record.x.ab = ab;
   ptr->r.record.x.reg = reg;
-  ptr->r.record.x.spoff = offset / 4;
+  ptr->r.record.x.where.spoff = offset / 4;
   ptr->r.record.x.qp = predicate;
   return ptr;
 }
 
 static unw_rec_list *
-output_spill_reg (ab, reg, targ_reg, xy)
-     unsigned int ab;
-     unsigned int reg;
-     unsigned int targ_reg;
-     unsigned int xy;
-{
-  unw_rec_list *ptr = alloc_record (spill_reg);
-  ptr->r.record.x.ab = ab;
-  ptr->r.record.x.reg = reg;
-  ptr->r.record.x.treg = targ_reg;
-  ptr->r.record.x.xy = xy;
-  return ptr;
-}
-
-static unw_rec_list *
-output_spill_reg_p (ab, reg, targ_reg, xy, predicate)
+output_spill_reg (ab, reg, targ_reg, xy, predicate)
      unsigned int ab;
      unsigned int reg;
      unsigned int targ_reg;
      unsigned int xy;
      unsigned int predicate;
 {
-  unw_rec_list *ptr = alloc_record (spill_reg_p);
+  unw_rec_list *ptr = alloc_record (predicate ? spill_reg_p : spill_reg);
   ptr->r.record.x.ab = ab;
   ptr->r.record.x.reg = reg;
-  ptr->r.record.x.treg = targ_reg;
+  ptr->r.record.x.where.reg = targ_reg;
   ptr->r.record.x.xy = xy;
   ptr->r.record.x.qp = predicate;
   return ptr;
@@ -2364,7 +2530,7 @@ process_one_record (ptr, f)
      unw_rec_list *ptr;
      vbyte_func f;
 {
-  unsigned long fr_mask, gr_mask;
+  unsigned int fr_mask, gr_mask;
 
   switch (ptr->r.type)
     {
@@ -2430,13 +2596,13 @@ process_one_record (ptr, f)
     case bsp_gr:
     case bspstore_gr:
     case rnat_gr:
-      output_P3_format (f, ptr->r.type, ptr->r.record.p.gr);
+      output_P3_format (f, ptr->r.type, ptr->r.record.p.r.gr);
       break;
     case rp_br:
-      output_P3_format (f, rp_br, ptr->r.record.p.br);
+      output_P3_format (f, rp_br, ptr->r.record.p.r.br);
       break;
     case psp_sprel:
-      output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0);
+      output_P7_format (f, psp_sprel, ptr->r.record.p.off.sp, 0);
       break;
     case rp_when:
     case pfs_when:
@@ -2453,7 +2619,7 @@ process_one_record (ptr, f)
     case lc_psprel:
     case fpsr_psprel:
     case spill_base:
-      output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0);
+      output_P7_format (f, ptr->r.type, ptr->r.record.p.off.psp, 0);
       break;
     case rp_sprel:
     case pfs_sprel:
@@ -2465,13 +2631,29 @@ process_one_record (ptr, f)
     case bsp_sprel:
     case bspstore_sprel:
     case rnat_sprel:
-      output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff);
+      output_P8_format (f, ptr->r.type, ptr->r.record.p.off.sp);
       break;
     case gr_gr:
-      output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr);
+      if (ptr->r.record.p.r.gr < REG_NUM)
+	{
+	  const unw_rec_list *cur = ptr;
+
+	  gr_mask = cur->r.record.p.grmask;
+	  while ((cur = cur->r.record.p.next) != NULL)
+	    gr_mask |= cur->r.record.p.grmask;
+	  output_P9_format (f, gr_mask, ptr->r.record.p.r.gr);
+	}
       break;
     case br_gr:
-      output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr);
+      if (ptr->r.record.p.r.gr < REG_NUM)
+	{
+	  const unw_rec_list *cur = ptr;
+
+	  gr_mask = cur->r.record.p.brmask;
+	  while ((cur = cur->r.record.p.next) != NULL)
+	    gr_mask |= cur->r.record.p.brmask;
+	  output_P2_format (f, gr_mask, ptr->r.record.p.r.gr);
+	}
       break;
     case spill_mask:
       as_bad ("spill_mask record unimplemented.");
@@ -2487,7 +2669,7 @@ process_one_record (ptr, f)
     case bsp_psprel:
     case bspstore_psprel:
     case rnat_psprel:
-      output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff);
+      output_P8_format (f, ptr->r.type, ptr->r.record.p.off.psp);
       break;
     case unwabi:
       output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context);
@@ -2502,32 +2684,32 @@ process_one_record (ptr, f)
     case spill_psprel:
       output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
 			ptr->r.record.x.reg, ptr->r.record.x.t,
-			ptr->r.record.x.pspoff);
+			ptr->r.record.x.where.pspoff);
       break;
     case spill_sprel:
       output_X1_format (f, ptr->r.type, ptr->r.record.x.ab,
 			ptr->r.record.x.reg, ptr->r.record.x.t,
-			ptr->r.record.x.spoff);
+			ptr->r.record.x.where.spoff);
       break;
     case spill_reg:
       output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg,
 			ptr->r.record.x.xy >> 1, ptr->r.record.x.xy,
-			ptr->r.record.x.treg, ptr->r.record.x.t);
+			ptr->r.record.x.where.reg, ptr->r.record.x.t);
       break;
     case spill_psprel_p:
       output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
 			ptr->r.record.x.ab, ptr->r.record.x.reg,
-			ptr->r.record.x.t, ptr->r.record.x.pspoff);
+			ptr->r.record.x.t, ptr->r.record.x.where.pspoff);
       break;
     case spill_sprel_p:
       output_X3_format (f, ptr->r.type, ptr->r.record.x.qp,
 			ptr->r.record.x.ab, ptr->r.record.x.reg,
-			ptr->r.record.x.t, ptr->r.record.x.spoff);
+			ptr->r.record.x.t, ptr->r.record.x.where.spoff);
       break;
     case spill_reg_p:
       output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab,
 			ptr->r.record.x.reg, ptr->r.record.x.xy >> 1,
-			ptr->r.record.x.xy, ptr->r.record.x.treg,
+			ptr->r.record.x.xy, ptr->r.record.x.where.reg,
 			ptr->r.record.x.t);
       break;
     default:
@@ -2558,6 +2740,28 @@ calc_record_size (list)
   return vbyte_count;
 }
 
+/* Return the number of bits set in the input value.
+   Perhaps this has a better place...  */
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+# define popcount __builtin_popcount
+#else
+static int
+popcount (unsigned x)
+{
+  static const unsigned char popcnt[16] =
+    {
+      0, 1, 1, 2,
+      1, 2, 2, 3,
+      1, 2, 2, 3,
+      2, 3, 3, 4
+    };
+
+  if (x < NELEMS (popcnt))
+    return popcnt[x];
+  return popcnt[x % NELEMS (popcnt)] + popcount (x / NELEMS (popcnt));
+}
+#endif
+
 /* Update IMASK bitmask to reflect the fact that one or more registers
    of type TYPE are saved starting at instruction with index T.  If N
    bits are set in REGMASK, it is assumed that instructions T through
@@ -2689,6 +2893,13 @@ slot_index (slot_addr, slot_frag, first_addr, first_frag, before_relax)
       /* Move to the beginning of the next frag.  */
       first_frag = first_frag->fr_next;
       first_addr = (unsigned long) &first_frag->fr_literal;
+
+      /* This can happen if there is section switching in the middle of a
+	 function, causing the frag chain for the function to be broken.
+	 It is too difficult to recover safely from this problem, so we just
+	 exit with an error.  */
+      if (first_frag == NULL)
+	as_fatal ("Section switching in code is not supported.");
     }
 
   /* Add in the used part of the last frag.  */
@@ -2770,7 +2981,13 @@ fixup_unw_records (list, before_relax)
 	    break;
 	  }
 	case epilogue:
-	  ptr->r.record.b.t = rlen - 1 - t;
+	  if (t < rlen)
+	    ptr->r.record.b.t = rlen - 1 - t;
+	  else
+	    /* This happens when a memory-stack-less procedure uses a
+	       ".restore sp" directive at the end of a region to pop
+	       the frame state.  */
+	    ptr->r.record.b.t = 0;
 	  break;
 
 	case mem_stack_f:
@@ -2801,7 +3018,7 @@ fixup_unw_records (list, before_relax)
 	case frgr_mem:
 	  if (!region)
 	    {
-	      as_bad ("frgr_mem record before region record!\n");
+	      as_bad ("frgr_mem record before region record!");
 	      return;
 	    }
 	  region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
@@ -2812,25 +3029,25 @@ fixup_unw_records (list, before_relax)
 	case fr_mem:
 	  if (!region)
 	    {
-	      as_bad ("fr_mem record before region record!\n");
+	      as_bad ("fr_mem record before region record!");
 	      return;
 	    }
-	  region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask;
-	  set_imask (region, ptr->r.record.p.rmask, t, 1);
+	  region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask;
+	  set_imask (region, ptr->r.record.p.frmask, t, 1);
 	  break;
 	case gr_mem:
 	  if (!region)
 	    {
-	      as_bad ("gr_mem record before region record!\n");
+	      as_bad ("gr_mem record before region record!");
 	      return;
 	    }
-	  region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask;
-	  set_imask (region, ptr->r.record.p.rmask, t, 2);
+	  region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask;
+	  set_imask (region, ptr->r.record.p.grmask, t, 2);
 	  break;
 	case br_mem:
 	  if (!region)
 	    {
-	      as_bad ("br_mem record before region record!\n");
+	      as_bad ("br_mem record before region record!");
 	      return;
 	    }
 	  region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask;
@@ -2840,7 +3057,7 @@ fixup_unw_records (list, before_relax)
 	case gr_gr:
 	  if (!region)
 	    {
-	      as_bad ("gr_gr record before region record!\n");
+	      as_bad ("gr_gr record before region record!");
 	      return;
 	    }
 	  set_imask (region, ptr->r.record.p.grmask, t, 2);
@@ -2848,7 +3065,7 @@ fixup_unw_records (list, before_relax)
 	case br_gr:
 	  if (!region)
 	    {
-	      as_bad ("br_gr record before region record!\n");
+	      as_bad ("br_gr record before region record!");
 	      return;
 	    }
 	  set_imask (region, ptr->r.record.p.brmask, t, 3);
@@ -2879,8 +3096,11 @@ ia64_estimate_size_before_relax (fragS *frag,
   pad = len % md.pointer_size;
   if (pad != 0)
     len += md.pointer_size - pad;
-  /* Add 8 for the header + a pointer for the personality offset.  */
-  size = len + 8 + md.pointer_size;
+  /* Add 8 for the header.  */
+  size = len + 8;
+  /* Add a pointer for the personality offset.  */
+  if (frag->fr_offset)
+    size += md.pointer_size;
 
   /* fr_var carries the max_chars that we created the fragment with.
      We must, of course, have allocated enough memory earlier.  */
@@ -2907,8 +3127,11 @@ ia64_convert_frag (fragS *frag)
   pad = len % md.pointer_size;
   if (pad != 0)
     len += md.pointer_size - pad;
-  /* Add 8 for the header + a pointer for the personality offset.  */
-  size = len + 8 + md.pointer_size;
+  /* Add 8 for the header.  */
+  size = len + 8;
+  /* Add a pointer for the personality offset.  */
+  if (frag->fr_offset)
+    size += md.pointer_size;
 
   /* fr_var carries the max_chars that we created the fragment with.
      We must, of course, have allocated enough memory earlier.  */
@@ -2949,17 +3172,43 @@ ia64_convert_frag (fragS *frag)
 }
 
 static int
-convert_expr_to_ab_reg (e, ab, regp)
-     expressionS *e;
+parse_predicate_and_operand (e, qp, po)
+     expressionS * e;
+     unsigned * qp;
+     const char * po;
+{
+  int sep = parse_operand (e, ',');
+
+  *qp = e->X_add_number - REG_P;
+  if (e->X_op != O_register || *qp > 63)
+    {
+      as_bad ("First operand to .%s must be a predicate", po);
+      *qp = 0;
+    }
+  else if (*qp == 0)
+    as_warn ("Pointless use of p0 as first operand to .%s", po);
+  if (sep == ',')
+    sep = parse_operand (e, ',');
+  else
+    e->X_op = O_absent;
+  return sep;
+}
+
+static void
+convert_expr_to_ab_reg (e, ab, regp, po, n)
+     const expressionS *e;
      unsigned int *ab;
      unsigned int *regp;
+     const char * po;
+     int n;
 {
-  unsigned int reg;
+  unsigned int reg = e->X_add_number;
+
+  *ab = *regp = 0; /* Anything valid is good here.  */
 
   if (e->X_op != O_register)
-    return 0;
+    reg = REG_GR; /* Anything invalid is good here.  */
 
-  reg = e->X_add_number;
   if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7))
     {
       *ab = 0;
@@ -2994,31 +3243,33 @@ convert_expr_to_ab_reg (e, ab, regp)
 	case REG_AR + AR_LC:	*regp = 10; break;
 
 	default:
-	  return 0;
+	  as_bad ("Operand %d to .%s must be a preserved register", n, po);
+	  break;
 	}
     }
-  return 1;
 }
 
-static int
-convert_expr_to_xy_reg (e, xy, regp)
-     expressionS *e;
+static void
+convert_expr_to_xy_reg (e, xy, regp, po, n)
+     const expressionS *e;
      unsigned int *xy;
      unsigned int *regp;
+     const char * po;
+     int n;
 {
-  unsigned int reg;
+  unsigned int reg = e->X_add_number;
 
-  if (e->X_op != O_register)
-    return 0;
+  *xy = *regp = 0; /* Anything valid is good here.  */
 
-  reg = e->X_add_number;
+  if (e->X_op != O_register)
+    reg = REG_GR; /* Anything invalid is good here.  */
 
-  if (/* reg >= REG_GR && */ reg <= (REG_GR + 127))
+  if (reg >= (REG_GR + 1) && reg <= (REG_GR + 127))
     {
       *xy = 0;
       *regp = reg - REG_GR;
     }
-  else if (reg >= REG_FR && reg <= (REG_FR + 127))
+  else if (reg >= (REG_FR + 2) && reg <= (REG_FR + 127))
     {
       *xy = 1;
       *regp = reg - REG_FR;
@@ -3029,8 +3280,7 @@ convert_expr_to_xy_reg (e, xy, regp)
       *regp = reg - REG_BR;
     }
   else
-    return -1;
-  return 1;
+    as_bad ("Operand %d to .%s must be a writable register", n, po);
 }
 
 static void
@@ -3045,17 +3295,31 @@ static void
 dot_radix (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  int radix;
+  char *radix;
+  int ch;
 
   SKIP_WHITESPACE ();
-  radix = *input_line_pointer++;
 
-  if (radix != 'C' && !is_end_of_line[(unsigned char) radix])
-    {
-      as_bad ("Radix `%c' unsupported", *input_line_pointer);
-      ignore_rest_of_line ();
-      return;
-    }
+  if (is_it_end_of_statement ())
+    return;
+  radix = input_line_pointer;
+  ch = get_symbol_end ();
+  ia64_canonicalize_symbol_name (radix);
+  if (strcasecmp (radix, "C"))
+    as_bad ("Radix `%s' unsupported or invalid", radix);
+  *input_line_pointer = ch;
+  demand_empty_rest_of_line ();
+}
+
+/* Helper function for .loc directives.  If the assembler is not generating
+   line number info, then we need to remember which instructions have a .loc
+   directive, and only call dwarf2_gen_line_info for those instructions.  */
+
+static void
+dot_loc (int x)
+{
+  CURR_SLOT.loc_directive_seen = 1;
+  dwarf2_directive_loc (x);
 }
 
 /* .sbss, .bss etc. are macros that expand into ".section SECNAME".  */
@@ -3066,19 +3330,112 @@ dot_special_section (which)
   set_section ((char *) special_section_name[which]);
 }
 
+/* Return -1 for warning and 0 for error.  */
+
+static int
+unwind_diagnostic (const char * region, const char *directive)
+{
+  if (md.unwind_check == unwind_check_warning)
+    {
+      as_warn (".%s outside of %s", directive, region);
+      return -1;
+    }
+  else
+    {
+      as_bad (".%s outside of %s", directive, region);
+      ignore_rest_of_line ();
+      return 0;
+    }
+}
+
+/* Return 1 if a directive is in a procedure, -1 if a directive isn't in
+   a procedure but the unwind directive check is set to warning, 0 if
+   a directive isn't in a procedure and the unwind directive check is set
+   to error.  */
+
+static int
+in_procedure (const char *directive)
+{
+  if (unwind.proc_pending.sym
+      && (!unwind.saved_text_seg || strcmp (directive, "endp") == 0))
+    return 1;
+  return unwind_diagnostic ("procedure", directive);
+}
+
+/* Return 1 if a directive is in a prologue, -1 if a directive isn't in
+   a prologue but the unwind directive check is set to warning, 0 if
+   a directive isn't in a prologue and the unwind directive check is set
+   to error.  */
+
+static int
+in_prologue (const char *directive)
+{
+  int in = in_procedure (directive);
+
+  if (in > 0 && !unwind.prologue)
+    in = unwind_diagnostic ("prologue", directive);
+  check_pending_save ();
+  return in;
+}
+
+/* Return 1 if a directive is in a body, -1 if a directive isn't in
+   a body but the unwind directive check is set to warning, 0 if
+   a directive isn't in a body and the unwind directive check is set
+   to error.  */
+
+static int
+in_body (const char *directive)
+{
+  int in = in_procedure (directive);
+
+  if (in > 0 && !unwind.body)
+    in = unwind_diagnostic ("body region", directive);
+  return in;
+}
+
 static void
-add_unwind_entry (ptr)
+add_unwind_entry (ptr, sep)
      unw_rec_list *ptr;
+     int sep;
 {
-  if (unwind.tail)
-    unwind.tail->next = ptr;
-  else
-    unwind.list = ptr;
-  unwind.tail = ptr;
+  if (ptr)
+    {
+      if (unwind.tail)
+	unwind.tail->next = ptr;
+      else
+	unwind.list = ptr;
+      unwind.tail = ptr;
+
+      /* The current entry can in fact be a chain of unwind entries.  */
+      if (unwind.current_entry == NULL)
+	unwind.current_entry = ptr;
+    }
 
   /* The current entry can in fact be a chain of unwind entries.  */
   if (unwind.current_entry == NULL)
     unwind.current_entry = ptr;
+
+  if (sep == ',')
+    {
+      /* Parse a tag permitted for the current directive.  */
+      int ch;
+
+      SKIP_WHITESPACE ();
+      ch = get_symbol_end ();
+      /* FIXME: For now, just issue a warning that this isn't implemented.  */
+      {
+	static int warned;
+
+	if (!warned)
+	  {
+	    warned = 1;
+	    as_warn ("Tags on unwind pseudo-ops aren't supported, yet");
+	  }
+      }
+      *input_line_pointer = ch;
+    }
+  if (sep != NOT_A_CHAR)
+    demand_empty_rest_of_line ();
 }
 
 static void
@@ -3086,13 +3443,19 @@ dot_fframe (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
   expressionS e;
+  int sep;
+
+  if (!in_prologue ("fframe"))
+    return;
 
-  parse_operand (&e);
+  sep = parse_operand (&e, ',');
 
   if (e.X_op != O_constant)
-    as_bad ("Operand to .fframe must be a constant");
-  else
-    add_unwind_entry (output_mem_stack_f (e.X_add_number));
+    {
+      as_bad ("First operand to .fframe must be a constant");
+      e.X_add_number = 0;
+    }
+  add_unwind_entry (output_mem_stack_f (e.X_add_number), sep);
 }
 
 static void
@@ -3101,49 +3464,47 @@ dot_vframe (dummy)
 {
   expressionS e;
   unsigned reg;
+  int sep;
 
-  parse_operand (&e);
+  if (!in_prologue ("vframe"))
+    return;
+
+  sep = parse_operand (&e, ',');
   reg = e.X_add_number - REG_GR;
-  if (e.X_op == O_register && reg < 128)
+  if (e.X_op != O_register || reg > 127)
     {
-      add_unwind_entry (output_mem_stack_v ());
-      if (! (unwind.prologue_mask & 2))
-	add_unwind_entry (output_psp_gr (reg));
+      as_bad ("First operand to .vframe must be a general register");
+      reg = 0;
     }
-  else
-    as_bad ("First operand to .vframe must be a general register");
+  add_unwind_entry (output_mem_stack_v (), sep);
+  if (! (unwind.prologue_mask & 2))
+    add_unwind_entry (output_psp_gr (reg), NOT_A_CHAR);
+  else if (reg != unwind.prologue_gr
+		  + (unsigned) popcount (unwind.prologue_mask & (-2 << 1)))
+    as_warn ("Operand of .vframe contradicts .prologue");
 }
 
 static void
-dot_vframesp (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+dot_vframesp (psp)
+     int psp;
 {
   expressionS e;
+  int sep;
 
-  parse_operand (&e);
-  if (e.X_op == O_constant)
-    {
-      add_unwind_entry (output_mem_stack_v ());
-      add_unwind_entry (output_psp_sprel (e.X_add_number));
-    }
-  else
-    as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
-}
+  if (psp)
+    as_warn (".vframepsp is meaningless, assuming .vframesp was meant");
 
-static void
-dot_vframepsp (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  expressionS e;
+  if (!in_prologue ("vframesp"))
+    return;
 
-  parse_operand (&e);
-  if (e.X_op == O_constant)
+  sep = parse_operand (&e, ',');
+  if (e.X_op != O_constant)
     {
-      add_unwind_entry (output_mem_stack_v ());
-      add_unwind_entry (output_psp_sprel (e.X_add_number));
+      as_bad ("Operand to .vframesp must be a constant (sp-relative offset)");
+      e.X_add_number = 0;
     }
-  else
-    as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)");
+  add_unwind_entry (output_mem_stack_v (), sep);
+  add_unwind_entry (output_psp_sprel (e.X_add_number), NOT_A_CHAR);
 }
 
 static void
@@ -3151,100 +3512,115 @@ dot_save (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
   expressionS e1, e2;
+  unsigned reg1, reg2;
   int sep;
-  int reg1, reg2;
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    as_bad ("No second operand to .save");
-  sep = parse_operand (&e2);
+  if (!in_prologue ("save"))
+    return;
 
-  reg1 = e1.X_add_number;
-  reg2 = e2.X_add_number - REG_GR;
+  sep = parse_operand (&e1, ',');
+  if (sep == ',')
+    sep = parse_operand (&e2, ',');
+  else
+    e2.X_op = O_absent;
 
+  reg1 = e1.X_add_number;
   /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'.  */
-  if (e1.X_op == O_register)
+  if (e1.X_op != O_register)
     {
-      if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128)
-	{
-	  switch (reg1)
-	    {
-	    case REG_AR + AR_BSP:
-	      add_unwind_entry (output_bsp_when ());
-	      add_unwind_entry (output_bsp_gr (reg2));
-	      break;
-	    case REG_AR + AR_BSPSTORE:
-	      add_unwind_entry (output_bspstore_when ());
-	      add_unwind_entry (output_bspstore_gr (reg2));
-	      break;
-	    case REG_AR + AR_RNAT:
-	      add_unwind_entry (output_rnat_when ());
-	      add_unwind_entry (output_rnat_gr (reg2));
-	      break;
-	    case REG_AR + AR_UNAT:
-	      add_unwind_entry (output_unat_when ());
-	      add_unwind_entry (output_unat_gr (reg2));
-	      break;
-	    case REG_AR + AR_FPSR:
-	      add_unwind_entry (output_fpsr_when ());
-	      add_unwind_entry (output_fpsr_gr (reg2));
-	      break;
-	    case REG_AR + AR_PFS:
-	      add_unwind_entry (output_pfs_when ());
-	      if (! (unwind.prologue_mask & 4))
-		add_unwind_entry (output_pfs_gr (reg2));
-	      break;
-	    case REG_AR + AR_LC:
-	      add_unwind_entry (output_lc_when ());
-	      add_unwind_entry (output_lc_gr (reg2));
-	      break;
-	    case REG_BR:
-	      add_unwind_entry (output_rp_when ());
-	      if (! (unwind.prologue_mask & 8))
-		add_unwind_entry (output_rp_gr (reg2));
-	      break;
-	    case REG_PR:
-	      add_unwind_entry (output_preds_when ());
-	      if (! (unwind.prologue_mask & 1))
-		add_unwind_entry (output_preds_gr (reg2));
-	      break;
-	    case REG_PRIUNAT:
-	      add_unwind_entry (output_priunat_when_gr ());
-	      add_unwind_entry (output_priunat_gr (reg2));
-	      break;
-	    default:
-	      as_bad ("First operand not a valid register");
-	    }
-	}
-      else
-	as_bad (" Second operand not a valid register");
+      as_bad ("First operand to .save not a register");
+      reg1 = REG_PR; /* Anything valid is good here.  */
+    }
+  reg2 = e2.X_add_number - REG_GR;
+  if (e2.X_op != O_register || reg2 > 127)
+    {
+      as_bad ("Second operand to .save not a valid register");
+      reg2 = 0;
+    }
+  switch (reg1)
+    {
+    case REG_AR + AR_BSP:
+      add_unwind_entry (output_bsp_when (), sep);
+      add_unwind_entry (output_bsp_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_BSPSTORE:
+      add_unwind_entry (output_bspstore_when (), sep);
+      add_unwind_entry (output_bspstore_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_RNAT:
+      add_unwind_entry (output_rnat_when (), sep);
+      add_unwind_entry (output_rnat_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_UNAT:
+      add_unwind_entry (output_unat_when (), sep);
+      add_unwind_entry (output_unat_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_FPSR:
+      add_unwind_entry (output_fpsr_when (), sep);
+      add_unwind_entry (output_fpsr_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_PFS:
+      add_unwind_entry (output_pfs_when (), sep);
+      if (! (unwind.prologue_mask & 4))
+	add_unwind_entry (output_pfs_gr (reg2), NOT_A_CHAR);
+      else if (reg2 != unwind.prologue_gr
+		       + (unsigned) popcount (unwind.prologue_mask & (-4 << 1)))
+	as_warn ("Second operand of .save contradicts .prologue");
+      break;
+    case REG_AR + AR_LC:
+      add_unwind_entry (output_lc_when (), sep);
+      add_unwind_entry (output_lc_gr (reg2), NOT_A_CHAR);
+      break;
+    case REG_BR:
+      add_unwind_entry (output_rp_when (), sep);
+      if (! (unwind.prologue_mask & 8))
+	add_unwind_entry (output_rp_gr (reg2), NOT_A_CHAR);
+      else if (reg2 != unwind.prologue_gr)
+	as_warn ("Second operand of .save contradicts .prologue");
+      break;
+    case REG_PR:
+      add_unwind_entry (output_preds_when (), sep);
+      if (! (unwind.prologue_mask & 1))
+	add_unwind_entry (output_preds_gr (reg2), NOT_A_CHAR);
+      else if (reg2 != unwind.prologue_gr
+		       + (unsigned) popcount (unwind.prologue_mask & (-1 << 1)))
+	as_warn ("Second operand of .save contradicts .prologue");
+      break;
+    case REG_PRIUNAT:
+      add_unwind_entry (output_priunat_when_gr (), sep);
+      add_unwind_entry (output_priunat_gr (reg2), NOT_A_CHAR);
+      break;
+    default:
+      as_bad ("First operand to .save not a valid register");
+      add_unwind_entry (NULL, sep);
+      break;
     }
-  else
-    as_bad ("First operand not a register");
 }
 
 static void
 dot_restore (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  expressionS e1, e2;
+  expressionS e1;
   unsigned long ecount;	/* # of _additional_ regions to pop */
   int sep;
 
-  sep = parse_operand (&e1);
+  if (!in_body ("restore"))
+    return;
+
+  sep = parse_operand (&e1, ',');
   if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12)
-    {
-      as_bad ("First operand to .restore must be stack pointer (sp)");
-      return;
-    }
+    as_bad ("First operand to .restore must be stack pointer (sp)");
 
   if (sep == ',')
     {
-      parse_operand (&e2);
+      expressionS e2;
+
+      sep = parse_operand (&e2, ',');
       if (e2.X_op != O_constant || e2.X_add_number < 0)
 	{
 	  as_bad ("Second operand to .restore must be a constant >= 0");
-	  return;
+	  e2.X_add_number = 0;
 	}
       ecount = e2.X_add_number;
     }
@@ -3255,10 +3631,10 @@ dot_restore (dummy)
     {
       as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)",
 	      ecount + 1, unwind.prologue_count);
-      return;
+      ecount = 0;
     }
 
-  add_unwind_entry (output_epilogue (ecount));
+  add_unwind_entry (output_epilogue (ecount), sep);
 
   if (ecount < unwind.prologue_count)
     unwind.prologue_count -= ecount + 1;
@@ -3267,64 +3643,155 @@ dot_restore (dummy)
 }
 
 static void
-dot_restorereg (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+dot_restorereg (pred)
+     int pred;
 {
-  unsigned int ab, reg;
+  unsigned int qp, ab, reg;
   expressionS e;
+  int sep;
+  const char * const po = pred ? "restorereg.p" : "restorereg";
 
-  parse_operand (&e);
+  if (!in_procedure (po))
+    return;
 
-  if (!convert_expr_to_ab_reg (&e, &ab, &reg))
+  if (pred)
+    sep = parse_predicate_and_operand (&e, &qp, po);
+  else
     {
-      as_bad ("First operand to .restorereg must be a preserved register");
-      return;
+      sep = parse_operand (&e, ',');
+      qp = 0;
     }
-  add_unwind_entry (output_spill_reg (ab, reg, 0, 0));
+  convert_expr_to_ab_reg (&e, &ab, &reg, po, 1 + pred);
+
+  add_unwind_entry (output_spill_reg (ab, reg, 0, 0, qp), sep);
 }
 
+static char *special_linkonce_name[] =
+  {
+    ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi."
+  };
+
 static void
-dot_restorereg_p (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+start_unwind_section (const segT text_seg, int sec_index)
 {
-  unsigned int qp, ab, reg;
-  expressionS e1, e2;
-  int sep;
+  /*
+    Use a slightly ugly scheme to derive the unwind section names from
+    the text section name:
+
+    text sect.  unwind table sect.
+    name:       name:                      comments:
+    ----------  -----------------          --------------------------------
+    .text       .IA_64.unwind
+    .text.foo   .IA_64.unwind.text.foo
+    .foo        .IA_64.unwind.foo
+    .gnu.linkonce.t.foo
+		.gnu.linkonce.ia64unw.foo
+    _info       .IA_64.unwind_info         gas issues error message (ditto)
+    _infoFOO    .IA_64.unwind_infoFOO      gas issues error message (ditto)
+
+    This mapping is done so that:
+
+	(a) An object file with unwind info only in .text will use
+	    unwind section names .IA_64.unwind and .IA_64.unwind_info.
+	    This follows the letter of the ABI and also ensures backwards
+	    compatibility with older toolchains.
+
+	(b) An object file with unwind info in multiple text sections
+	    will use separate unwind sections for each text section.
+	    This allows us to properly set the "sh_info" and "sh_link"
+	    fields in SHT_IA_64_UNWIND as required by the ABI and also
+	    lets GNU ld support programs with multiple segments
+	    containing unwind info (as might be the case for certain
+	    embedded applications).
+
+	(c) An error is issued if there would be a name clash.
+  */
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
+  const char *text_name, *sec_text_name;
+  char *sec_name;
+  const char *prefix = special_section_name [sec_index];
+  const char *suffix;
+  size_t prefix_len, suffix_len, sec_name_len;
+
+  sec_text_name = segment_name (text_seg);
+  text_name = sec_text_name;
+  if (strncmp (text_name, "_info", 5) == 0)
     {
-      as_bad ("No second operand to .restorereg.p");
+      as_bad ("Illegal section name `%s' (causes unwind section name clash)",
+	      text_name);
+      ignore_rest_of_line ();
       return;
     }
+  if (strcmp (text_name, ".text") == 0)
+    text_name = "";
 
-  parse_operand (&e2);
-
-  qp = e1.X_add_number - REG_P;
-  if (e1.X_op != O_register || qp > 63)
+  /* Build the unwind section name by appending the (possibly stripped)
+     text section name to the unwind prefix.  */
+  suffix = text_name;
+  if (strncmp (text_name, ".gnu.linkonce.t.",
+	       sizeof (".gnu.linkonce.t.") - 1) == 0)
     {
-      as_bad ("First operand to .restorereg.p must be a predicate");
-      return;
+      prefix = special_linkonce_name [sec_index - SPECIAL_SECTION_UNWIND];
+      suffix += sizeof (".gnu.linkonce.t.") - 1;
     }
 
-  if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
+  prefix_len = strlen (prefix);
+  suffix_len = strlen (suffix);
+  sec_name_len = prefix_len + suffix_len;
+  sec_name = alloca (sec_name_len + 1);
+  memcpy (sec_name, prefix, prefix_len);
+  memcpy (sec_name + prefix_len, suffix, suffix_len);
+  sec_name [sec_name_len] = '\0';
+
+  /* Handle COMDAT group.  */
+  if ((text_seg->flags & SEC_LINK_ONCE) != 0
+      && (elf_section_flags (text_seg) & SHF_GROUP) != 0)
     {
-      as_bad ("Second operand to .restorereg.p must be a preserved register");
-      return;
+      char *section;
+      size_t len, group_name_len;
+      const char *group_name = elf_group_name (text_seg);
+
+      if (group_name == NULL)
+	{
+	  as_bad ("Group section `%s' has no group signature",
+		  sec_text_name);
+	  ignore_rest_of_line ();
+	  return;
+	}
+      /* We have to construct a fake section directive. */
+      group_name_len = strlen (group_name);
+      len = (sec_name_len
+	     + 16			/* ,"aG",@progbits,  */
+	     + group_name_len		/* ,group_name  */
+	     + 7);			/* ,comdat  */
+
+      section = alloca (len + 1);
+      memcpy (section, sec_name, sec_name_len);
+      memcpy (section + sec_name_len, ",\"aG\",@progbits,", 16);
+      memcpy (section + sec_name_len + 16, group_name, group_name_len);
+      memcpy (section + len - 7, ",comdat", 7);
+      section [len] = '\0';
+      set_section (section);
     }
-  add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp));
+  else
+    {
+      set_section (sec_name);
+      bfd_set_section_flags (stdoutput, now_seg,
+			     SEC_LOAD | SEC_ALLOC | SEC_READONLY);
+    }
+
+  elf_linked_to_section (now_seg) = text_seg;
 }
 
 static void
-generate_unwind_image (text_name)
-     const char *text_name;
+generate_unwind_image (const segT text_seg)
 {
   int size, pad;
   unw_rec_list *list;
 
   /* Mark the end of the unwind info, so that we can compute the size of the
      last unwind region.  */
-  add_unwind_entry (output_endp ());
+  add_unwind_entry (output_endp (), NOT_A_CHAR);
 
   /* Force out pending instructions, to make sure all unwind records have
      a valid slot_number field.  */
@@ -3342,22 +3809,20 @@ generate_unwind_image (text_name)
       pad = size % md.pointer_size;
       if (pad != 0)
 	size += md.pointer_size - pad;
-      /* Add 8 for the header + a pointer for the personality
-	 offset.  */
-      size += 8 + md.pointer_size;
+      /* Add 8 for the header.  */
+      size += 8;
+      /* Add a pointer for the personality offset.  */
+      if (unwind.personality_routine)
+	size += md.pointer_size;
     }
 
   /* If there are unwind records, switch sections, and output the info.  */
   if (size != 0)
     {
-      char *sec_name;
       expressionS exp;
       bfd_reloc_code_real_type reloc;
 
-      make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name);
-      set_section (sec_name);
-      bfd_set_section_flags (stdoutput, now_seg,
-			     SEC_LOAD | SEC_ALLOC | SEC_READONLY);
+      start_unwind_section (text_seg, SPECIAL_SECTION_UNWIND_INFO);
 
       /* Make sure the section has 4 byte alignment for ILP32 and
 	 8 byte alignment for LP64.  */
@@ -3368,7 +3833,8 @@ generate_unwind_image (text_name)
       unwind.info = expr_build_dot ();
       
       frag_var (rs_machine_dependent, size, size, 0, 0,
-		(offsetT) unwind.personality_routine, (char *) list);
+		(offsetT) (long) unwind.personality_routine,
+		(char *) list);
 
       /* Add the personality address to the image.  */
       if (unwind.personality_routine != 0)
@@ -3406,13 +3872,8 @@ static void
 dot_handlerdata (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  const char *text_name = segment_name (now_seg);
-
-  /* If text section name starts with ".text" (which it should),
-     strip this prefix off.  */
-  if (strcmp (text_name, ".text") == 0)
-    text_name = "";
-
+  if (!in_procedure ("handlerdata"))
+    return;
   unwind.force_unwind_entry = 1;
 
   /* Remember which segment we're in so we can switch back after .endp */
@@ -3422,7 +3883,7 @@ dot_handlerdata (dummy)
   /* Generate unwind info into unwind-info section and then leave that
      section as the currently active one so dataXX directives go into
      the language specific data area of the unwind info block.  */
-  generate_unwind_image (text_name);
+  generate_unwind_image (now_seg);
   demand_empty_rest_of_line ();
 }
 
@@ -3430,6 +3891,8 @@ static void
 dot_unwentry (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
+  if (!in_procedure ("unwentry"))
+    return;
   unwind.force_unwind_entry = 1;
   demand_empty_rest_of_line ();
 }
@@ -3441,12 +3904,17 @@ dot_altrp (dummy)
   expressionS e;
   unsigned reg;
 
-  parse_operand (&e);
+  if (!in_prologue ("altrp"))
+    return;
+
+  parse_operand (&e, 0);
   reg = e.X_add_number - REG_BR;
-  if (e.X_op == O_register && reg < 8)
-    add_unwind_entry (output_rp_br (reg));
-  else
-    as_bad ("First operand not a valid branch register");
+  if (e.X_op != O_register || reg > 7)
+    {
+      as_bad ("First operand to .altrp not a valid branch register");
+      reg = 0;
+    }
+  add_unwind_entry (output_rp_br (reg), 0);
 }
 
 static void
@@ -3456,371 +3924,343 @@ dot_savemem (psprel)
   expressionS e1, e2;
   int sep;
   int reg1, val;
+  const char * const po = psprel ? "savepsp" : "savesp";
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    as_bad ("No second operand to .save%ssp", psprel ? "p" : "");
-  sep = parse_operand (&e2);
+  if (!in_prologue (po))
+    return;
+
+  sep = parse_operand (&e1, ',');
+  if (sep == ',')
+    sep = parse_operand (&e2, ',');
+  else
+    e2.X_op = O_absent;
 
   reg1 = e1.X_add_number;
   val = e2.X_add_number;
 
   /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'.  */
-  if (e1.X_op == O_register)
+  if (e1.X_op != O_register)
     {
-      if (e2.X_op == O_constant)
-	{
-	  switch (reg1)
-	    {
-	    case REG_AR + AR_BSP:
-	      add_unwind_entry (output_bsp_when ());
-	      add_unwind_entry ((psprel
-				 ? output_bsp_psprel
-				 : output_bsp_sprel) (val));
-	      break;
-	    case REG_AR + AR_BSPSTORE:
-	      add_unwind_entry (output_bspstore_when ());
-	      add_unwind_entry ((psprel
-				 ? output_bspstore_psprel
-				 : output_bspstore_sprel) (val));
-	      break;
-	    case REG_AR + AR_RNAT:
-	      add_unwind_entry (output_rnat_when ());
-	      add_unwind_entry ((psprel
-				 ? output_rnat_psprel
-				 : output_rnat_sprel) (val));
-	      break;
-	    case REG_AR + AR_UNAT:
-	      add_unwind_entry (output_unat_when ());
-	      add_unwind_entry ((psprel
-				 ? output_unat_psprel
-				 : output_unat_sprel) (val));
-	      break;
-	    case REG_AR + AR_FPSR:
-	      add_unwind_entry (output_fpsr_when ());
-	      add_unwind_entry ((psprel
-				 ? output_fpsr_psprel
-				 : output_fpsr_sprel) (val));
-	      break;
-	    case REG_AR + AR_PFS:
-	      add_unwind_entry (output_pfs_when ());
-	      add_unwind_entry ((psprel
-				 ? output_pfs_psprel
-				 : output_pfs_sprel) (val));
-	      break;
-	    case REG_AR + AR_LC:
-	      add_unwind_entry (output_lc_when ());
-	      add_unwind_entry ((psprel
-				 ? output_lc_psprel
-				 : output_lc_sprel) (val));
-	      break;
-	    case REG_BR:
-	      add_unwind_entry (output_rp_when ());
-	      add_unwind_entry ((psprel
-				 ? output_rp_psprel
-				 : output_rp_sprel) (val));
-	      break;
-	    case REG_PR:
-	      add_unwind_entry (output_preds_when ());
-	      add_unwind_entry ((psprel
-				 ? output_preds_psprel
-				 : output_preds_sprel) (val));
-	      break;
-	    case REG_PRIUNAT:
-	      add_unwind_entry (output_priunat_when_mem ());
-	      add_unwind_entry ((psprel
-				 ? output_priunat_psprel
-				 : output_priunat_sprel) (val));
-	      break;
-	    default:
-	      as_bad ("First operand not a valid register");
-	    }
-	}
-      else
-	as_bad (" Second operand not a valid constant");
+      as_bad ("First operand to .%s not a register", po);
+      reg1 = REG_PR; /* Anything valid is good here.  */
     }
-  else
-    as_bad ("First operand not a register");
-}
-
-static void
-dot_saveg (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  expressionS e1, e2;
-  int sep;
-  sep = parse_operand (&e1);
-  if (sep == ',')
-    parse_operand (&e2);
-
-  if (e1.X_op != O_constant)
-    as_bad ("First operand to .save.g must be a constant.");
-  else
+  if (e2.X_op != O_constant)
     {
-      int grmask = e1.X_add_number;
-      if (sep != ',')
-	add_unwind_entry (output_gr_mem (grmask));
-      else
-	{
-	  int reg = e2.X_add_number - REG_GR;
-	  if (e2.X_op == O_register && reg >= 0 && reg < 128)
-	    add_unwind_entry (output_gr_gr (grmask, reg));
-	  else
-	    as_bad ("Second operand is an invalid register.");
-	}
+      as_bad ("Second operand to .%s not a constant", po);
+      val = 0;
+    }
+
+  switch (reg1)
+    {
+    case REG_AR + AR_BSP:
+      add_unwind_entry (output_bsp_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_bsp_psprel
+			 : output_bsp_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_BSPSTORE:
+      add_unwind_entry (output_bspstore_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_bspstore_psprel
+			 : output_bspstore_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_RNAT:
+      add_unwind_entry (output_rnat_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_rnat_psprel
+			 : output_rnat_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_UNAT:
+      add_unwind_entry (output_unat_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_unat_psprel
+			 : output_unat_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_FPSR:
+      add_unwind_entry (output_fpsr_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_fpsr_psprel
+			 : output_fpsr_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_PFS:
+      add_unwind_entry (output_pfs_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_pfs_psprel
+			 : output_pfs_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_AR + AR_LC:
+      add_unwind_entry (output_lc_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_lc_psprel
+			 : output_lc_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_BR:
+      add_unwind_entry (output_rp_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_rp_psprel
+			 : output_rp_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_PR:
+      add_unwind_entry (output_preds_when (), sep);
+      add_unwind_entry ((psprel
+			 ? output_preds_psprel
+			 : output_preds_sprel) (val), NOT_A_CHAR);
+      break;
+    case REG_PRIUNAT:
+      add_unwind_entry (output_priunat_when_mem (), sep);
+      add_unwind_entry ((psprel
+			 ? output_priunat_psprel
+			 : output_priunat_sprel) (val), NOT_A_CHAR);
+      break;
+    default:
+      as_bad ("First operand to .%s not a valid register", po);
+      add_unwind_entry (NULL, sep);
+      break;
     }
 }
 
 static void
-dot_savef (dummy)
+dot_saveg (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  expressionS e1;
+  expressionS e;
+  unsigned grmask;
   int sep;
-  sep = parse_operand (&e1);
 
-  if (e1.X_op != O_constant)
-    as_bad ("Operand to .save.f must be a constant.");
-  else
-    add_unwind_entry (output_fr_mem (e1.X_add_number));
-}
+  if (!in_prologue ("save.g"))
+    return;
 
-static void
-dot_saveb (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  expressionS e1, e2;
-  unsigned int reg;
-  unsigned char sep;
-  int brmask;
+  sep = parse_operand (&e, ',');
 
-  sep = parse_operand (&e1);
-  if (e1.X_op != O_constant)
+  grmask = e.X_add_number;
+  if (e.X_op != O_constant
+      || e.X_add_number <= 0
+      || e.X_add_number > 0xf)
     {
-      as_bad ("First operand to .save.b must be a constant.");
-      return;
+      as_bad ("First operand to .save.g must be a positive 4-bit constant");
+      grmask = 0;
     }
-  brmask = e1.X_add_number;
 
   if (sep == ',')
     {
-      sep = parse_operand (&e2);
-      reg = e2.X_add_number - REG_GR;
-      if (e2.X_op != O_register || reg > 127)
+      unsigned reg;
+      int n = popcount (grmask);
+
+      parse_operand (&e, 0);
+      reg = e.X_add_number - REG_GR;
+      if (e.X_op != O_register || reg > 127)
 	{
-	  as_bad ("Second operand to .save.b must be a general register.");
-	  return;
+	  as_bad ("Second operand to .save.g must be a general register");
+	  reg = 0;
 	}
-      add_unwind_entry (output_br_gr (brmask, e2.X_add_number));
+      else if (reg > 128U - n)
+	{
+	  as_bad ("Second operand to .save.g must be the first of %d general registers", n);
+	  reg = 0;
+	}
+      add_unwind_entry (output_gr_gr (grmask, reg), 0);
     }
   else
-    add_unwind_entry (output_br_mem (brmask));
-
-  if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    demand_empty_rest_of_line ();
+    add_unwind_entry (output_gr_mem (grmask), 0);
 }
 
 static void
-dot_savegf (dummy)
+dot_savef (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  expressionS e1, e2;
-  int sep;
-  sep = parse_operand (&e1);
-  if (sep == ',')
-    parse_operand (&e2);
+  expressionS e;
 
-  if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant)
-    as_bad ("Both operands of .save.gf must be constants.");
-  else
+  if (!in_prologue ("save.f"))
+    return;
+
+  parse_operand (&e, 0);
+
+  if (e.X_op != O_constant
+      || e.X_add_number <= 0
+      || e.X_add_number > 0xfffff)
     {
-      int grmask = e1.X_add_number;
-      int frmask = e2.X_add_number;
-      add_unwind_entry (output_frgr_mem (grmask, frmask));
+      as_bad ("Operand to .save.f must be a positive 20-bit constant");
+      e.X_add_number = 0;
     }
+  add_unwind_entry (output_fr_mem (e.X_add_number), 0);
 }
 
 static void
-dot_spill (dummy)
+dot_saveb (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
   expressionS e;
-  unsigned char sep;
-
-  sep = parse_operand (&e);
-  if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    demand_empty_rest_of_line ();
+  unsigned brmask;
+  int sep;
 
-  if (e.X_op != O_constant)
-    as_bad ("Operand to .spill must be a constant");
-  else
-    add_unwind_entry (output_spill_base (e.X_add_number));
-}
+  if (!in_prologue ("save.b"))
+    return;
 
-static void
-dot_spillreg (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  int sep, ab, xy, reg, treg;
-  expressionS e1, e2;
+  sep = parse_operand (&e, ',');
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
+  brmask = e.X_add_number;
+  if (e.X_op != O_constant
+      || e.X_add_number <= 0
+      || e.X_add_number > 0x1f)
     {
-      as_bad ("No second operand to .spillreg");
-      return;
+      as_bad ("First operand to .save.b must be a positive 5-bit constant");
+      brmask = 0;
     }
 
-  parse_operand (&e2);
-
-  if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
+  if (sep == ',')
     {
-      as_bad ("First operand to .spillreg must be a preserved register");
-      return;
-    }
+      unsigned reg;
+      int n = popcount (brmask);
 
-  if (!convert_expr_to_xy_reg (&e2, &xy, &treg))
-    {
-      as_bad ("Second operand to .spillreg must be a register");
-      return;
+      parse_operand (&e, 0);
+      reg = e.X_add_number - REG_GR;
+      if (e.X_op != O_register || reg > 127)
+	{
+	  as_bad ("Second operand to .save.b must be a general register");
+	  reg = 0;
+	}
+      else if (reg > 128U - n)
+	{
+	  as_bad ("Second operand to .save.b must be the first of %d general registers", n);
+	  reg = 0;
+	}
+      add_unwind_entry (output_br_gr (brmask, reg), 0);
     }
-
-  add_unwind_entry (output_spill_reg (ab, reg, treg, xy));
+  else
+    add_unwind_entry (output_br_mem (brmask), 0);
 }
 
 static void
-dot_spillmem (psprel)
-     int psprel;
+dot_savegf (dummy)
+     int dummy ATTRIBUTE_UNUSED;
 {
   expressionS e1, e2;
-  int sep, ab, reg;
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    {
-      as_bad ("Second operand missing");
-      return;
-    }
+  if (!in_prologue ("save.gf"))
+    return;
 
-  parse_operand (&e2);
+  if (parse_operand (&e1, ',') == ',')
+    parse_operand (&e2, 0);
+  else
+    e2.X_op = O_absent;
 
-  if (!convert_expr_to_ab_reg (&e1, &ab, &reg))
+  if (e1.X_op != O_constant
+      || e1.X_add_number < 0
+      || e1.X_add_number > 0xf)
     {
-      as_bad ("First operand to .spill%s must be a preserved register",
-	      psprel ? "psp" : "sp");
-      return;
+      as_bad ("First operand to .save.gf must be a non-negative 4-bit constant");
+      e1.X_op = O_absent;
+      e1.X_add_number = 0;
     }
-
-  if (e2.X_op != O_constant)
+  if (e2.X_op != O_constant
+      || e2.X_add_number < 0
+      || e2.X_add_number > 0xfffff)
     {
-      as_bad ("Second operand to .spill%s must be a constant",
-	      psprel ? "psp" : "sp");
-      return;
+      as_bad ("Second operand to .save.gf must be a non-negative 20-bit constant");
+      e2.X_op = O_absent;
+      e2.X_add_number = 0;
     }
+  if (e1.X_op == O_constant
+      && e2.X_op == O_constant
+      && e1.X_add_number == 0
+      && e2.X_add_number == 0)
+    as_bad ("Operands to .save.gf may not be both zero");
 
-  if (psprel)
-    add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number));
-  else
-    add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number));
+  add_unwind_entry (output_frgr_mem (e1.X_add_number, e2.X_add_number), 0);
 }
 
 static void
-dot_spillreg_p (dummy)
+dot_spill (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  int sep, ab, xy, reg, treg;
-  expressionS e1, e2, e3;
-  unsigned int qp;
+  expressionS e;
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    {
-      as_bad ("No second and third operand to .spillreg.p");
-      return;
-    }
+  if (!in_prologue ("spill"))
+    return;
+
+  parse_operand (&e, 0);
 
-  sep = parse_operand (&e2);
-  if (sep != ',')
+  if (e.X_op != O_constant)
     {
-      as_bad ("No third operand to .spillreg.p");
-      return;
+      as_bad ("Operand to .spill must be a constant");
+      e.X_add_number = 0;
     }
+  add_unwind_entry (output_spill_base (e.X_add_number), 0);
+}
 
-  parse_operand (&e3);
-
-  qp = e1.X_add_number - REG_P;
+static void
+dot_spillreg (pred)
+     int pred;
+{
+  int sep;
+  unsigned int qp, ab, xy, reg, treg;
+  expressionS e;
+  const char * const po = pred ? "spillreg.p" : "spillreg";
 
-  if (e1.X_op != O_register || qp > 63)
-    {
-      as_bad ("First operand to .spillreg.p must be a predicate");
-      return;
-    }
+  if (!in_procedure (po))
+    return;
 
-  if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
+  if (pred)
+    sep = parse_predicate_and_operand (&e, &qp, po);
+  else
     {
-      as_bad ("Second operand to .spillreg.p must be a preserved register");
-      return;
+      sep = parse_operand (&e, ',');
+      qp = 0;
     }
+  convert_expr_to_ab_reg (&e, &ab, &reg, po, 1 + pred);
 
-  if (!convert_expr_to_xy_reg (&e3, &xy, &treg))
-    {
-      as_bad ("Third operand to .spillreg.p must be a register");
-      return;
-    }
+  if (sep == ',')
+    sep = parse_operand (&e, ',');
+  else
+    e.X_op = O_absent;
+  convert_expr_to_xy_reg (&e, &xy, &treg, po, 2 + pred);
 
-  add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp));
+  add_unwind_entry (output_spill_reg (ab, reg, treg, xy, qp), sep);
 }
 
 static void
-dot_spillmem_p (psprel)
+dot_spillmem (psprel)
      int psprel;
 {
-  expressionS e1, e2, e3;
-  int sep, ab, reg;
-  unsigned int qp;
-
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    {
-      as_bad ("Second operand missing");
-      return;
-    }
+  expressionS e;
+  int pred = (psprel < 0), sep;
+  unsigned int qp, ab, reg;
+  const char * po;
 
-  parse_operand (&e2);
-  if (sep != ',')
+  if (pred)
     {
-      as_bad ("Second operand missing");
-      return;
+      psprel = ~psprel;
+      po = psprel ? "spillpsp.p" : "spillsp.p";
     }
+  else
+    po = psprel ? "spillpsp" : "spillsp";
 
-  parse_operand (&e3);
-
-  qp = e1.X_add_number - REG_P;
-  if (e1.X_op != O_register || qp > 63)
-    {
-      as_bad ("First operand to .spill%s_p must be a predicate",
-	      psprel ? "psp" : "sp");
-      return;
-    }
+  if (!in_procedure (po))
+    return;
 
-  if (!convert_expr_to_ab_reg (&e2, &ab, &reg))
+  if (pred)
+    sep = parse_predicate_and_operand (&e, &qp, po);
+  else
     {
-      as_bad ("Second operand to .spill%s_p must be a preserved register",
-	      psprel ? "psp" : "sp");
-      return;
+      sep = parse_operand (&e, ',');
+      qp = 0;
     }
+  convert_expr_to_ab_reg (&e, &ab, &reg, po, 1 + pred);
 
-  if (e3.X_op != O_constant)
+  if (sep == ',')
+    sep = parse_operand (&e, ',');
+  else
+    e.X_op = O_absent;
+  if (e.X_op != O_constant)
     {
-      as_bad ("Third operand to .spill%s_p must be a constant",
-	      psprel ? "psp" : "sp");
-      return;
+      as_bad ("Operand %d to .%s must be a constant", 2 + pred, po);
+      e.X_add_number = 0;
     }
 
   if (psprel)
-    add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp));
+    add_unwind_entry (output_spill_psprel (ab, reg, e.X_add_number, qp), sep);
   else
-    add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp));
+    add_unwind_entry (output_spill_sprel (ab, reg, e.X_add_number, qp), sep);
 }
 
 static unsigned int
@@ -3884,14 +4324,18 @@ dot_label_state (dummy)
 {
   expressionS e;
 
-  parse_operand (&e);
-  if (e.X_op != O_constant)
+  if (!in_body ("label_state"))
+    return;
+
+  parse_operand (&e, 0);
+  if (e.X_op == O_constant)
+    save_prologue_count (e.X_add_number, unwind.prologue_count);
+  else
     {
       as_bad ("Operand to .label_state must be a constant");
-      return;
+      e.X_add_number = 0;
     }
-  add_unwind_entry (output_label_state (e.X_add_number));
-  save_prologue_count (e.X_add_number, unwind.prologue_count);
+  add_unwind_entry (output_label_state (e.X_add_number), 0);
 }
 
 static void
@@ -3900,14 +4344,18 @@ dot_copy_state (dummy)
 {
   expressionS e;
 
-  parse_operand (&e);
-  if (e.X_op != O_constant)
+  if (!in_body ("copy_state"))
+    return;
+
+  parse_operand (&e, 0);
+  if (e.X_op == O_constant)
+    unwind.prologue_count = get_saved_prologue_count (e.X_add_number);
+  else
     {
       as_bad ("Operand to .copy_state must be a constant");
-      return;
+      e.X_add_number = 0;
     }
-  add_unwind_entry (output_copy_state (e.X_add_number));
-  unwind.prologue_count = get_saved_prologue_count (e.X_add_number);
+  add_unwind_entry (output_copy_state (e.X_add_number), 0);
 }
 
 static void
@@ -3917,29 +4365,28 @@ dot_unwabi (dummy)
   expressionS e1, e2;
   unsigned char sep;
 
-  sep = parse_operand (&e1);
-  if (sep != ',')
-    {
-      as_bad ("Second operand to .unwabi missing");
-      return;
-    }
-  sep = parse_operand (&e2);
-  if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-    demand_empty_rest_of_line ();
+  if (!in_prologue ("unwabi"))
+    return;
+
+  sep = parse_operand (&e1, ',');
+  if (sep == ',')
+    parse_operand (&e2, 0);
+  else
+    e2.X_op = O_absent;
 
   if (e1.X_op != O_constant)
     {
       as_bad ("First operand to .unwabi must be a constant");
-      return;
+      e1.X_add_number = 0;
     }
 
   if (e2.X_op != O_constant)
     {
       as_bad ("Second operand to .unwabi must be a constant");
-      return;
+      e2.X_add_number = 0;
     }
 
-  add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number));
+  add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number), 0);
 }
 
 static void
@@ -3947,6 +4394,8 @@ dot_personality (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
   char *name, *p, c;
+  if (!in_procedure ("personality"))
+    return;
   SKIP_WHITESPACE ();
   name = input_line_pointer;
   c = get_symbol_end ();
@@ -3964,8 +4413,22 @@ dot_proc (dummy)
 {
   char *name, *p, c;
   symbolS *sym;
+  proc_pending *pending, *last_pending;
+
+  if (unwind.proc_pending.sym)
+    {
+      (md.unwind_check == unwind_check_warning
+       ? as_warn
+       : as_bad) ("Missing .endp after previous .proc");
+      while (unwind.proc_pending.next)
+	{
+	  pending = unwind.proc_pending.next;
+	  unwind.proc_pending.next = pending->next;
+	  free (pending);
+	}
+    }
+  last_pending = NULL;
 
-  unwind.proc_start = expr_build_dot ();
   /* Parse names of main and alternate entry points and mark them as
      function symbols:  */
   while (1)
@@ -3974,22 +4437,45 @@ dot_proc (dummy)
       name = input_line_pointer;
       c = get_symbol_end ();
       p = input_line_pointer;
-      sym = symbol_find_or_make (name);
-      if (unwind.proc_start == 0)
+      if (!*name)
+	as_bad ("Empty argument of .proc");
+      else
 	{
-	  unwind.proc_start = sym;
+	  sym = symbol_find_or_make (name);
+	  if (S_IS_DEFINED (sym))
+	    as_bad ("`%s' was already defined", name);
+	  else if (!last_pending)
+	    {
+	      unwind.proc_pending.sym = sym;
+	      last_pending = &unwind.proc_pending;
+	    }
+	  else
+	    {
+	      pending = xmalloc (sizeof (*pending));
+	      pending->sym = sym;
+	      last_pending = last_pending->next = pending;
+	    }
+	  symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
 	}
-      symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION;
       *p = c;
       SKIP_WHITESPACE ();
       if (*input_line_pointer != ',')
 	break;
       ++input_line_pointer;
     }
+  if (!last_pending)
+    {
+      unwind.proc_pending.sym = expr_build_dot ();
+      last_pending = &unwind.proc_pending;
+    }
+  last_pending->next = NULL;
   demand_empty_rest_of_line ();
   ia64_do_align (16);
 
+  unwind.prologue = 0;
   unwind.prologue_count = 0;
+  unwind.body = 0;
+  unwind.insn = 0;
   unwind.list = unwind.tail = unwind.current_entry = NULL;
   unwind.personality_routine = 0;
 }
@@ -3998,52 +4484,86 @@ static void
 dot_body (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
+  if (!in_procedure ("body"))
+    return;
+  if (!unwind.prologue && !unwind.body && unwind.insn)
+    as_warn ("Initial .body should precede any instructions");
+  check_pending_save ();
+
   unwind.prologue = 0;
   unwind.prologue_mask = 0;
+  unwind.body = 1;
 
-  add_unwind_entry (output_body ());
-  demand_empty_rest_of_line ();
+  add_unwind_entry (output_body (), 0);
 }
 
 static void
 dot_prologue (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
-  unsigned char sep;
-  int mask = 0, grsave = 0;
+  unsigned mask = 0, grsave = 0;
 
-  if (!is_it_end_of_statement ())
+  if (!in_procedure ("prologue"))
+    return;
+  if (unwind.prologue)
     {
-      expressionS e1, e2;
-      sep = parse_operand (&e1);
-      if (sep != ',')
-	as_bad ("No second operand to .prologue");
-      sep = parse_operand (&e2);
-      if (!is_end_of_line[sep] && !is_it_end_of_statement ())
-	demand_empty_rest_of_line ();
+      as_bad (".prologue within prologue");
+      ignore_rest_of_line ();
+      return;
+    }
+  if (!unwind.body && unwind.insn)
+    as_warn ("Initial .prologue should precede any instructions");
 
-      if (e1.X_op == O_constant)
-	{
-	  mask = e1.X_add_number;
+  if (!is_it_end_of_statement ())
+    {
+      expressionS e;
+      int n, sep = parse_operand (&e, ',');
 
-	  if (e2.X_op == O_constant)
-	    grsave = e2.X_add_number;
-	  else if (e2.X_op == O_register
-		   && (grsave = e2.X_add_number - REG_GR) < 128)
-	    ;
-	  else
-	    as_bad ("Second operand not a constant or general register");
+      if (e.X_op != O_constant
+	  || e.X_add_number < 0
+	  || e.X_add_number > 0xf)
+	as_bad ("First operand to .prologue must be a positive 4-bit constant");
+      else if (e.X_add_number == 0)
+	as_warn ("Pointless use of zero first operand to .prologue");
+      else
+	mask = e.X_add_number;
+	n = popcount (mask);
 
-	  add_unwind_entry (output_prologue_gr (mask, grsave));
-	}
+      if (sep == ',')
+	parse_operand (&e, 0);
       else
-	as_bad ("First operand not a constant");
+	e.X_op = O_absent;
+      if (e.X_op == O_constant
+	  && e.X_add_number >= 0
+	  && e.X_add_number < 128)
+	{
+	  if (md.unwind_check == unwind_check_error)
+	    as_warn ("Using a constant as second operand to .prologue is deprecated");
+	  grsave = e.X_add_number;
+	}
+      else if (e.X_op != O_register
+	       || (grsave = e.X_add_number - REG_GR) > 127)
+	{
+	  as_bad ("Second operand to .prologue must be a general register");
+	  grsave = 0;
+	}
+      else if (grsave > 128U - n)
+	{
+	  as_bad ("Second operand to .prologue must be the first of %d general registers", n);
+	  grsave = 0;
+	}
+
     }
+
+  if (mask)
+    add_unwind_entry (output_prologue_gr (mask, grsave), 0);
   else
-    add_unwind_entry (output_prologue ());
+    add_unwind_entry (output_prologue (), 0);
 
   unwind.prologue = 1;
   unwind.prologue_mask = mask;
+  unwind.prologue_gr = grsave;
+  unwind.body = 0;
   ++unwind.prologue_count;
 }
 
@@ -4052,14 +4572,17 @@ dot_endp (dummy)
      int dummy ATTRIBUTE_UNUSED;
 {
   expressionS e;
-  unsigned char *ptr;
   int bytes_per_address;
   long where;
   segT saved_seg;
   subsegT saved_subseg;
-  const char *sec_name, *text_name;
-  char *name, *p, c;
-  symbolS *sym;
+  proc_pending *pending;
+  int unwind_check = md.unwind_check;
+
+  md.unwind_check = unwind_check_error;
+  if (!in_procedure ("endp"))
+    return;
+  md.unwind_check = unwind_check;
 
   if (unwind.saved_text_seg)
     {
@@ -4073,64 +4596,20 @@ dot_endp (dummy)
       saved_subseg = now_subseg;
     }
 
-  /*
-    Use a slightly ugly scheme to derive the unwind section names from
-    the text section name:
-
-    text sect.  unwind table sect.
-    name:       name:                      comments:
-    ----------  -----------------          --------------------------------
-    .text       .IA_64.unwind
-    .text.foo   .IA_64.unwind.text.foo
-    .foo        .IA_64.unwind.foo
-    .gnu.linkonce.t.foo
-		.gnu.linkonce.ia64unw.foo
-    _info       .IA_64.unwind_info         gas issues error message (ditto)
-    _infoFOO    .IA_64.unwind_infoFOO      gas issues error message (ditto)
-
-    This mapping is done so that:
-
-	(a) An object file with unwind info only in .text will use
-	    unwind section names .IA_64.unwind and .IA_64.unwind_info.
-	    This follows the letter of the ABI and also ensures backwards
-	    compatibility with older toolchains.
-
-	(b) An object file with unwind info in multiple text sections
-	    will use separate unwind sections for each text section.
-	    This allows us to properly set the "sh_info" and "sh_link"
-	    fields in SHT_IA_64_UNWIND as required by the ABI and also
-	    lets GNU ld support programs with multiple segments
-	    containing unwind info (as might be the case for certain
-	    embedded applications).
-
-	(c) An error is issued if there would be a name clash.
-  */
-  text_name = segment_name (saved_seg);
-  if (strncmp (text_name, "_info", 5) == 0)
-    {
-      as_bad ("Illegal section name `%s' (causes unwind section name clash)",
-	      text_name);
-      ignore_rest_of_line ();
-      return;
-    }
-  if (strcmp (text_name, ".text") == 0)
-    text_name = "";
-
   insn_group_break (1, 0, 0);
 
   /* If there wasn't a .handlerdata, we haven't generated an image yet.  */
   if (!unwind.info)
-    generate_unwind_image (text_name);
+    generate_unwind_image (saved_seg);
 
   if (unwind.info || unwind.force_unwind_entry)
     {
+      symbolS *proc_end;
+
       subseg_set (md.last_text_seg, 0);
-      unwind.proc_end = expr_build_dot ();
+      proc_end = expr_build_dot ();
 
-      make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name);
-      set_section ((char *) sec_name);
-      bfd_set_section_flags (stdoutput, now_seg,
-			     SEC_LOAD | SEC_ALLOC | SEC_READONLY);
+      start_unwind_section (saved_seg, SPECIAL_SECTION_UNWIND);
 
       /* Make sure that section has 4 byte alignment for ILP32 and
          8 byte alignment for LP64.  */
@@ -4138,7 +4617,7 @@ dot_endp (dummy)
 
       /* Need space for 3 pointers for procedure start, procedure end,
 	 and unwind info.  */
-      ptr = frag_more (3 * md.pointer_size);
+      memset (frag_more (3 * md.pointer_size), 0, 3 * md.pointer_size);
       where = frag_now_fix () - (3 * md.pointer_size);
       bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8;
 
@@ -4146,13 +4625,19 @@ dot_endp (dummy)
       e.X_op = O_pseudo_fixup;
       e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
       e.X_add_number = 0;
-      e.X_add_symbol = unwind.proc_start;
+      if (!S_IS_LOCAL (unwind.proc_pending.sym)
+	  && S_IS_DEFINED (unwind.proc_pending.sym))
+	e.X_add_symbol = symbol_temp_new (S_GET_SEGMENT (unwind.proc_pending.sym),
+					  S_GET_VALUE (unwind.proc_pending.sym),
+					  symbol_get_frag (unwind.proc_pending.sym));
+      else
+	e.X_add_symbol = unwind.proc_pending.sym;
       ia64_cons_fix_new (frag_now, where, bytes_per_address, &e);
 
       e.X_op = O_pseudo_fixup;
       e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym;
       e.X_add_number = 0;
-      e.X_add_symbol = unwind.proc_end;
+      e.X_add_symbol = proc_end;
       ia64_cons_fix_new (frag_now, where + bytes_per_address,
 			 bytes_per_address, &e);
 
@@ -4165,48 +4650,71 @@ dot_endp (dummy)
 	  ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2),
 			     bytes_per_address, &e);
 	}
-      else
-	md_number_to_chars (ptr + (bytes_per_address * 2), 0,
-			    bytes_per_address);
-
     }
   subseg_set (saved_seg, saved_subseg);
 
-  /* Parse names of main and alternate entry points and set symbol sizes.  */
+  /* Set symbol sizes.  */
+  pending = &unwind.proc_pending;
+  if (S_GET_NAME (pending->sym))
+    {
+      do
+	{
+	  symbolS *sym = pending->sym;
+
+	  if (!S_IS_DEFINED (sym))
+	    as_bad ("`%s' was not defined within procedure", S_GET_NAME (sym));
+	  else if (S_GET_SIZE (sym) == 0
+		   && symbol_get_obj (sym)->size == NULL)
+	    {
+	      fragS *frag = symbol_get_frag (sym);
+
+	      if (frag)
+		{
+		  if (frag == frag_now && SEG_NORMAL (now_seg))
+		    S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym));
+		  else
+		    {
+		      symbol_get_obj (sym)->size =
+			(expressionS *) xmalloc (sizeof (expressionS));
+		      symbol_get_obj (sym)->size->X_op = O_subtract;
+		      symbol_get_obj (sym)->size->X_add_symbol
+			= symbol_new (FAKE_LABEL_NAME, now_seg,
+				      frag_now_fix (), frag_now);
+		      symbol_get_obj (sym)->size->X_op_symbol = sym;
+		      symbol_get_obj (sym)->size->X_add_number = 0;
+		    }
+		}
+	    }
+	} while ((pending = pending->next) != NULL);
+    }
+
+  /* Parse names of main and alternate entry points.  */
   while (1)
     {
+      char *name, *p, c;
+
       SKIP_WHITESPACE ();
       name = input_line_pointer;
       c = get_symbol_end ();
       p = input_line_pointer;
-      sym = symbol_find (name);
-      if (sym && unwind.proc_start
-	  && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION)
-	  && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL)
-	{
-	  fragS *fr = symbol_get_frag (unwind.proc_start);
-	  fragS *frag = symbol_get_frag (sym);
-
-	  /* Check whether the function label is at or beyond last
-	     .proc directive.  */
-	  while (fr && fr != frag)
-	    fr = fr->fr_next;
-	  if (fr)
-	    {
-	      if (frag == frag_now && SEG_NORMAL (now_seg))
-		S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym));
-	      else
+      if (!*name)
+	(md.unwind_check == unwind_check_warning
+	 ? as_warn
+	 : as_bad) ("Empty argument of .endp");
+      else
+	{
+	  symbolS *sym = symbol_find (name);
+
+	  for (pending = &unwind.proc_pending; pending; pending = pending->next)
+	    {
+	      if (sym == pending->sym)
 		{
-		  symbol_get_obj (sym)->size =
-		    (expressionS *) xmalloc (sizeof (expressionS));
-		  symbol_get_obj (sym)->size->X_op = O_subtract;
-		  symbol_get_obj (sym)->size->X_add_symbol
-		    = symbol_new (FAKE_LABEL_NAME, now_seg,
-				  frag_now_fix (), frag_now);
-		  symbol_get_obj (sym)->size->X_op_symbol = sym;
-		  symbol_get_obj (sym)->size->X_add_number = 0;
+		  pending->sym = NULL;
+		  break;
 		}
 	    }
+	  if (!sym || !pending)
+	    as_warn ("`%s' was not specified with previous .proc", name);
 	}
       *p = c;
       SKIP_WHITESPACE ();
@@ -4215,7 +4723,21 @@ dot_endp (dummy)
       ++input_line_pointer;
     }
   demand_empty_rest_of_line ();
-  unwind.proc_start = unwind.proc_end = unwind.info = 0;
+
+  /* Deliberately only checking for the main entry point here; the
+     language spec even says all arguments to .endp are ignored.  */
+  if (unwind.proc_pending.sym
+      && S_GET_NAME (unwind.proc_pending.sym)
+      && strcmp (S_GET_NAME (unwind.proc_pending.sym), FAKE_LABEL_NAME))
+    as_warn ("`%s' should be an operand to this .endp",
+	     S_GET_NAME (unwind.proc_pending.sym));
+  while (unwind.proc_pending.next)
+    {
+      pending = unwind.proc_pending.next;
+      unwind.proc_pending.next = pending->next;
+      free (pending);
+    }
+  unwind.proc_pending.sym = unwind.info = NULL;
 }
 
 static void
@@ -4258,7 +4780,8 @@ static void
 dot_rot (type)
      int type;
 {
-  unsigned num_regs, num_alloced = 0;
+  offsetT num_regs;
+  valueT num_alloced = 0;
   struct dynreg **drpp, *dr;
   int ch, base_reg = 0;
   char *name, *start;
@@ -4276,6 +4799,7 @@ dot_rot (type)
   for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next)
     {
       hash_delete (md.dynreg_hash, dr->name);
+      /* FIXME: Free dr->name.  */
       dr->num_regs = 0;
     }
 
@@ -4284,8 +4808,8 @@ dot_rot (type)
     {
       start = input_line_pointer;
       ch = get_symbol_end ();
+      len = strlen (ia64_canonicalize_symbol_name (start));
       *input_line_pointer = ch;
-      len = (input_line_pointer - start);
 
       SKIP_WHITESPACE ();
       if (*input_line_pointer != '[')
@@ -4302,6 +4826,11 @@ dot_rot (type)
 	  as_bad ("Expected ']'");
 	  goto err;
 	}
+      if (num_regs <= 0)
+	{
+	  as_bad ("Number of elements must be positive");
+	  goto err;
+	}
       SKIP_WHITESPACE ();
 
       num_alloced += num_regs;
@@ -4334,16 +4863,16 @@ dot_rot (type)
 	  break;
 	}
 
-      name = obstack_alloc (&notes, len + 1);
-      memcpy (name, start, len);
-      name[len] = '\0';
-
       if (!*drpp)
 	{
 	  *drpp = obstack_alloc (&notes, sizeof (*dr));
 	  memset (*drpp, 0, sizeof (*dr));
 	}
 
+      name = obstack_alloc (&notes, len + 1);
+      memcpy (name, start, len);
+      name[len] = '\0';
+
       dr = *drpp;
       dr->name = name;
       dr->num_regs = num_regs;
@@ -4354,6 +4883,7 @@ dot_rot (type)
       if (hash_insert (md.dynreg_hash, name, dr))
 	{
 	  as_bad ("Attempt to redefine register set `%s'", name);
+	  obstack_free (&notes, name);
 	  goto err;
 	}
 
@@ -4378,8 +4908,7 @@ dot_byteorder (byteorder)
   if (byteorder == -1)
     {
       if (seginfo->tc_segment_info_data.endian == 0)
-	seginfo->tc_segment_info_data.endian
-	  = TARGET_BYTES_BIG_ENDIAN ? 1 : 2;
+	seginfo->tc_segment_info_data.endian = default_big_endian ? 1 : 2;
       byteorder = seginfo->tc_segment_info_data.endian == 1;
     }
   else
@@ -4442,49 +4971,75 @@ dot_ln (dummy)
   demand_empty_rest_of_line ();
 }
 
-static char *
-parse_section_name ()
+static void
+cross_section (ref, cons, ua)
+     int ref;
+     void (*cons) PARAMS((int));
+     int ua;
 {
-  char *name;
-  int len;
+  char *start, *end;
+  int saved_auto_align;
+  unsigned int section_count;
 
   SKIP_WHITESPACE ();
-  if (*input_line_pointer != '"')
+  start = input_line_pointer;
+  if (*start == '"')
     {
-      as_bad ("Missing section name");
-      ignore_rest_of_line ();
-      return 0;
+      int len;
+      char *name;
+
+      name = demand_copy_C_string (&len);
+      obstack_free(&notes, name);
+      if (!name)
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
     }
-  name = demand_copy_C_string (&len);
-  if (!name)
+  else
     {
-      ignore_rest_of_line ();
-      return 0;
+      char c = get_symbol_end ();
+
+      if (input_line_pointer == start)
+	{
+	  as_bad ("Missing section name");
+	  ignore_rest_of_line ();
+	  return;
+	}
+      *input_line_pointer = c;
     }
+  end = input_line_pointer;
   SKIP_WHITESPACE ();
   if (*input_line_pointer != ',')
     {
       as_bad ("Comma expected after section name");
       ignore_rest_of_line ();
-      return 0;
+      return;
     }
-  ++input_line_pointer;		/* skip comma */
-  return name;
+  *end = '\0';
+  end = input_line_pointer + 1;		/* skip comma */
+  input_line_pointer = start;
+  md.keep_pending_output = 1;
+  section_count = bfd_count_sections(stdoutput);
+  obj_elf_section (0);
+  if (section_count != bfd_count_sections(stdoutput))
+    as_warn ("Creating sections with .xdataN/.xrealN/.xstringZ is deprecated.");
+  input_line_pointer = end;
+  saved_auto_align = md.auto_align;
+  if (ua)
+    md.auto_align = 0;
+  (*cons) (ref);
+  if (ua)
+    md.auto_align = saved_auto_align;
+  obj_elf_previous (0);
+  md.keep_pending_output = 0;
 }
 
 static void
 dot_xdata (size)
      int size;
 {
-  char *name = parse_section_name ();
-  if (!name)
-    return;
-
-  md.keep_pending_output = 1;
-  set_section (name);
-  cons (size);
-  obj_elf_previous (0);
-  md.keep_pending_output = 0;
+  cross_section (size, cons, 0);
 }
 
 /* Why doesn't float_cons() call md_cons_align() the way cons() does?  */
@@ -4530,66 +5085,28 @@ static void
 dot_xfloat_cons (kind)
      int kind;
 {
-  char *name = parse_section_name ();
-  if (!name)
-    return;
-
-  md.keep_pending_output = 1;
-  set_section (name);
-  stmt_float_cons (kind);
-  obj_elf_previous (0);
-  md.keep_pending_output = 0;
+  cross_section (kind, stmt_float_cons, 0);
 }
 
 static void
 dot_xstringer (zero)
      int zero;
 {
-  char *name = parse_section_name ();
-  if (!name)
-    return;
-
-  md.keep_pending_output = 1;
-  set_section (name);
-  stringer (zero);
-  obj_elf_previous (0);
-  md.keep_pending_output = 0;
+  cross_section (zero, stringer, 0);
 }
 
 static void
 dot_xdata_ua (size)
      int size;
 {
-  int saved_auto_align = md.auto_align;
-  char *name = parse_section_name ();
-  if (!name)
-    return;
-
-  md.keep_pending_output = 1;
-  set_section (name);
-  md.auto_align = 0;
-  cons (size);
-  md.auto_align = saved_auto_align;
-  obj_elf_previous (0);
-  md.keep_pending_output = 0;
+  cross_section (size, cons, 1);
 }
 
 static void
 dot_xfloat_cons_ua (kind)
      int kind;
 {
-  int saved_auto_align = md.auto_align;
-  char *name = parse_section_name ();
-  if (!name)
-    return;
-
-  md.keep_pending_output = 1;
-  set_section (name);
-  md.auto_align = 0;
-  stmt_float_cons (kind);
-  md.auto_align = saved_auto_align;
-  obj_elf_previous (0);
-  md.keep_pending_output = 0;
+  cross_section (kind, float_cons, 1);
 }
 
 /* .reg.val <regname>,value */
@@ -4600,7 +5117,7 @@ dot_reg_val (dummy)
 {
   expressionS reg;
 
-  expression (&reg);
+  expression_and_evaluate (&reg);
   if (reg.X_op != O_register)
     {
       as_bad (_("Register name expected"));
@@ -4615,7 +5132,7 @@ dot_reg_val (dummy)
     {
       valueT value = get_absolute_expression ();
       int regno = reg.X_add_number;
-      if (regno < REG_GR || regno > REG_GR + 128)
+      if (regno <= REG_GR || regno > REG_GR + 127)
 	as_warn (_("Register value annotation ignored"));
       else
 	{
@@ -4627,6 +5144,23 @@ dot_reg_val (dummy)
   demand_empty_rest_of_line ();
 }
 
+/*
+  .serialize.data
+  .serialize.instruction
+ */
+static void
+dot_serialize (type)
+     int type;
+{
+  insn_group_break (0, 0, 0);
+  if (type)
+    instruction_serialization ();
+  else
+    data_serialization ();
+  insn_group_break (0, 0, 0);
+  demand_empty_rest_of_line ();
+}
+
 /* select dv checking mode
    .auto
    .explicit
@@ -4689,9 +5223,9 @@ print_prmask (mask)
 }
 
 /*
-  .pred.rel.clear [p1 [,p2 [,...]]]     (also .pred.rel "clear")
-  .pred.rel.imply p1, p2                (also .pred.rel "imply")
-  .pred.rel.mutex p1, p2 [,...]         (also .pred.rel "mutex")
+  .pred.rel.clear [p1 [,p2 [,...]]]     (also .pred.rel "clear" or @clear)
+  .pred.rel.imply p1, p2                (also .pred.rel "imply" or @imply)
+  .pred.rel.mutex p1, p2 [,...]         (also .pred.rel "mutex" or @mutex)
   .pred.safe_across_calls p1 [, p2 [,...]]
  */
 
@@ -4705,28 +5239,43 @@ dot_pred_rel (type)
 
   if (type == 0)
     {
-      if (*input_line_pointer != '"')
-	{
-	  as_bad (_("Missing predicate relation type"));
-	  ignore_rest_of_line ();
-	  return;
-	}
-      else
+      if (*input_line_pointer == '"')
 	{
 	  int len;
 	  char *form = demand_copy_C_string (&len);
+
 	  if (strcmp (form, "mutex") == 0)
 	    type = 'm';
 	  else if (strcmp (form, "clear") == 0)
 	    type = 'c';
 	  else if (strcmp (form, "imply") == 0)
 	    type = 'i';
-	  else
-	    {
-	      as_bad (_("Unrecognized predicate relation type"));
-	      ignore_rest_of_line ();
-	      return;
-	    }
+	  obstack_free (&notes, form);
+	}
+      else if (*input_line_pointer == '@')
+	{
+	  char *form = ++input_line_pointer;
+	  char c = get_symbol_end();
+
+	  if (strcmp (form, "mutex") == 0)
+	    type = 'm';
+	  else if (strcmp (form, "clear") == 0)
+	    type = 'c';
+	  else if (strcmp (form, "imply") == 0)
+	    type = 'i';
+	  *input_line_pointer = c;
+	}
+      else
+	{
+	  as_bad (_("Missing predicate relation type"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      if (type == 0)
+	{
+	  as_bad (_("Unrecognized predicate relation type"));
+	  ignore_rest_of_line ();
+	  return;
 	}
       if (*input_line_pointer == ',')
 	++input_line_pointer;
@@ -4736,59 +5285,57 @@ dot_pred_rel (type)
   SKIP_WHITESPACE ();
   while (1)
     {
-      valueT bit = 1;
+      valueT bits = 1;
       int regno;
-
-      if (TOUPPER (*input_line_pointer) != 'P'
-	  || (regno = atoi (++input_line_pointer)) < 0
-	  || regno > 63)
-	{
-	  as_bad (_("Predicate register expected"));
-	  ignore_rest_of_line ();
-	  return;
-	}
-      while (ISDIGIT (*input_line_pointer))
-	++input_line_pointer;
-      if (p1 == -1)
-	p1 = regno;
-      else if (p2 == -1)
-	p2 = regno;
-      bit <<= regno;
-      if (mask & bit)
-	as_warn (_("Duplicate predicate register ignored"));
-      mask |= bit;
-      count++;
-      /* See if it's a range.  */
-      if (*input_line_pointer == '-')
-	{
-	  valueT stop = 1;
-	  ++input_line_pointer;
-
-	  if (TOUPPER (*input_line_pointer) != 'P'
-	      || (regno = atoi (++input_line_pointer)) < 0
-	      || regno > 63)
-	    {
-	      as_bad (_("Predicate register expected"));
-	      ignore_rest_of_line ();
-	      return;
-	    }
-	  while (ISDIGIT (*input_line_pointer))
-	    ++input_line_pointer;
-	  stop <<= regno;
-	  if (bit >= stop)
+      expressionS pr, *pr1, *pr2;
+
+      expression_and_evaluate (&pr);
+      if (pr.X_op == O_register
+	  && pr.X_add_number >= REG_P
+	  && pr.X_add_number <= REG_P + 63)
+	{
+	  regno = pr.X_add_number - REG_P;
+	  bits <<= regno;
+	  count++;
+	  if (p1 == -1)
+	    p1 = regno;
+	  else if (p2 == -1)
+	    p2 = regno;
+	}
+      else if (type != 'i'
+	  && pr.X_op == O_subtract
+	  && (pr1 = symbol_get_value_expression (pr.X_add_symbol))
+	  && pr1->X_op == O_register
+	  && pr1->X_add_number >= REG_P
+	  && pr1->X_add_number <= REG_P + 63
+	  && (pr2 = symbol_get_value_expression (pr.X_op_symbol))
+	  && pr2->X_op == O_register
+	  && pr2->X_add_number >= REG_P
+	  && pr2->X_add_number <= REG_P + 63)
+	{
+	  /* It's a range.  */
+	  int stop;
+
+	  regno = pr1->X_add_number - REG_P;
+	  stop = pr2->X_add_number - REG_P;
+	  if (regno >= stop)
 	    {
 	      as_bad (_("Bad register range"));
 	      ignore_rest_of_line ();
 	      return;
 	    }
-	  while (bit < stop)
-	    {
-	      bit <<= 1;
-	      mask |= bit;
-	      count++;
-	    }
-	  SKIP_WHITESPACE ();
+	  bits = ((bits << stop) << 1) - (bits << regno);
+	  count += stop - regno + 1;
 	}
+      else
+	{
+	  as_bad (_("Predicate register expected"));
+	  ignore_rest_of_line ();
+	  return;
+	}
+      if (mask & bits)
+	as_warn (_("Duplicate predicate register ignored"));
+      mask |= bits;
       if (*input_line_pointer != ',')
 	break;
       ++input_line_pointer;
@@ -4908,6 +5455,7 @@ const pseudo_typeS md_pseudo_table[] =
   {
     { "radix", dot_radix, 0 },
     { "lcomm", s_lcomm_bytes, 1 },
+    { "loc", dot_loc, 0 },
     { "bss", dot_special_section, SPECIAL_SECTION_BSS },
     { "sbss", dot_special_section, SPECIAL_SECTION_SBSS },
     { "sdata", dot_special_section, SPECIAL_SECTION_SDATA },
@@ -4925,11 +5473,11 @@ const pseudo_typeS md_pseudo_table[] =
     { "fframe", dot_fframe, 0 },
     { "vframe", dot_vframe, 0 },
     { "vframesp", dot_vframesp, 0 },
-    { "vframepsp", dot_vframepsp, 0 },
+    { "vframepsp", dot_vframesp, 1 },
     { "save", dot_save, 0 },
     { "restore", dot_restore, 0 },
     { "restorereg", dot_restorereg, 0 },
-    { "restorereg.p", dot_restorereg_p, 0 },
+    { "restorereg.p", dot_restorereg, 1 },
     { "handlerdata", dot_handlerdata, 0 },
     { "unwentry", dot_unwentry, 0 },
     { "altrp", dot_altrp, 0 },
@@ -4943,16 +5491,13 @@ const pseudo_typeS md_pseudo_table[] =
     { "spillreg", dot_spillreg, 0 },
     { "spillsp", dot_spillmem, 0 },
     { "spillpsp", dot_spillmem, 1 },
-    { "spillreg.p", dot_spillreg_p, 0 },
-    { "spillsp.p", dot_spillmem_p, 0 },
-    { "spillpsp.p", dot_spillmem_p, 1 },
+    { "spillreg.p", dot_spillreg, 1 },
+    { "spillsp.p", dot_spillmem, ~0 },
+    { "spillpsp.p", dot_spillmem, ~1 },
     { "label_state", dot_label_state, 0 },
     { "copy_state", dot_copy_state, 0 },
     { "unwabi", dot_unwabi, 0 },
     { "personality", dot_personality, 0 },
-#if 0
-    { "estate", dot_estate, 0 },
-#endif
     { "mii", dot_template, 0x0 },
     { "mli", dot_template, 0x2 }, /* old format, for compatibility */
     { "mlx", dot_template, 0x2 },
@@ -4964,10 +5509,6 @@ const pseudo_typeS md_pseudo_table[] =
     { "bbb", dot_template, 0xb },
     { "mmb", dot_template, 0xc },
     { "mfb", dot_template, 0xe },
-#if 0
-    { "lb", dot_scope, 0 },
-    { "le", dot_scope, 1 },
-#endif
     { "align", dot_align, 0 },
     { "regstk", dot_regstk, 0 },
     { "rotr", dot_rot, DYNREG_GR },
@@ -4984,6 +5525,7 @@ const pseudo_typeS md_pseudo_table[] =
     { "xdata2", dot_xdata, 2 },
     { "xdata4", dot_xdata, 4 },
     { "xdata8", dot_xdata, 8 },
+    { "xdata16", dot_xdata, 16 },
     { "xreal4", dot_xfloat_cons, 'f' },
     { "xreal8", dot_xfloat_cons, 'd' },
     { "xreal10", dot_xfloat_cons, 'x' },
@@ -4995,6 +5537,7 @@ const pseudo_typeS md_pseudo_table[] =
     { "xdata2.ua", dot_xdata_ua, 2 },
     { "xdata4.ua", dot_xdata_ua, 4 },
     { "xdata8.ua", dot_xdata_ua, 8 },
+    { "xdata16.ua", dot_xdata_ua, 16 },
     { "xreal4.ua", dot_xfloat_cons_ua, 'f' },
     { "xreal8.ua", dot_xfloat_cons_ua, 'd' },
     { "xreal10.ua", dot_xfloat_cons_ua, 'x' },
@@ -5009,6 +5552,8 @@ const pseudo_typeS md_pseudo_table[] =
     { "pred.rel.mutex", dot_pred_rel, 'm' },
     { "pred.safe_across_calls", dot_pred_rel, 's' },
     { "reg.val", dot_reg_val, 0 },
+    { "serialize.data", dot_serialize, 0 },
+    { "serialize.instruction", dot_serialize, 1 },
     { "auto", dot_dv_mode, 'a' },
     { "explicit", dot_dv_mode, 'e' },
     { "default", dot_dv_mode, 'd' },
@@ -5063,12 +5608,12 @@ pseudo_opcode[] =
 static symbolS *
 declare_register (name, regnum)
      const char *name;
-     int regnum;
+     unsigned int regnum;
 {
   const char *err;
   symbolS *sym;
 
-  sym = symbol_new (name, reg_section, regnum, &zero_address_frag);
+  sym = symbol_create (name, reg_section, regnum, &zero_address_frag);
 
   err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym);
   if (err)
@@ -5081,11 +5626,11 @@ declare_register (name, regnum)
 static void
 declare_register_set (prefix, num_regs, base_regnum)
      const char *prefix;
-     int num_regs;
-     int base_regnum;
+     unsigned int num_regs;
+     unsigned int base_regnum;
 {
   char name[8];
-  int i;
+  unsigned int i;
 
   for (i = 0; i < num_regs; ++i)
     {
@@ -5369,6 +5914,17 @@ operand_match (idesc, index, e)
 	return OPERAND_MATCH;
       break;
 
+    case IA64_OPND_IMMU5b:
+      if (e->X_op == O_constant)
+	{
+	  val = e->X_add_number;
+	  if (val >= 32 && val <= 63)
+	    return OPERAND_MATCH;
+	  else
+	    return OPERAND_OUT_OF_RANGE;
+	}
+      break;
+
     case IA64_OPND_CCNT5:
     case IA64_OPND_CNT5:
     case IA64_OPND_CNT6:
@@ -5611,7 +6167,7 @@ operand_match (idesc, index, e)
 	case O_symbol:
 	  fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups;
 	  /* There are no external relocs for TAG13/TAG13b fields, so we
-	     create a dummy reloc.  This will not live past md_apply_fix3.  */
+	     create a dummy reloc.  This will not live past md_apply_fix.  */
 	  fix->code = BFD_RELOC_UNUSED;
 	  fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code);
 	  fix->opnd = idesc->operands[index];
@@ -5641,27 +6197,19 @@ operand_match (idesc, index, e)
 }
 
 static int
-parse_operand (e)
+parse_operand (e, more)
      expressionS *e;
+     int more;
 {
   int sep = '\0';
 
   memset (e, 0, sizeof (*e));
   e->X_op = O_absent;
   SKIP_WHITESPACE ();
-  if (*input_line_pointer != '}')
-    expression (e);
-  sep = *input_line_pointer++;
-
-  if (sep == '}')
-    {
-      if (!md.manual_bundling)
-	as_warn ("Found '}' when manual bundling is off");
-      else
-	CURR_SLOT.manual_bundling_off = 1;
-      md.manual_bundling = 0;
-      sep = '\0';
-    }
+  expression_and_evaluate (e);
+  sep = *input_line_pointer;
+  if (more && (sep == ',' || sep == more))
+    ++input_line_pointer;
   return sep;
 }
 
@@ -5686,6 +6234,8 @@ parse_operands (idesc)
 {
   int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0;
   int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0;
+  int reg1, reg2;
+  char reg_class;
   enum ia64_opnd expected_operand = IA64_OPND_NIL;
   enum operand_match_result result;
   char mnemonic[129];
@@ -5695,7 +6245,8 @@ parse_operands (idesc)
   assert (strlen (idesc->name) <= 128);
 
   strcpy (mnemonic, idesc->name);
-  if (idesc->operands[2] == IA64_OPND_SOF)
+  if (idesc->operands[2] == IA64_OPND_SOF
+      || idesc->operands[1] == IA64_OPND_SOF)
     {
       /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we
 	 can't parse the first operand until we have parsed the
@@ -5713,11 +6264,22 @@ parse_operands (idesc)
       ++num_outputs;
     }
 
-  for (; i < NELEMS (CURR_SLOT.opnd); ++i)
+  for (; ; ++i)
     {
-      sep = parse_operand (CURR_SLOT.opnd + i);
-      if (CURR_SLOT.opnd[i].X_op == O_absent)
-	break;
+      if (i < NELEMS (CURR_SLOT.opnd)) 
+	{
+	  sep = parse_operand (CURR_SLOT.opnd + i, '=');
+	  if (CURR_SLOT.opnd[i].X_op == O_absent)
+	    break;
+	}
+      else
+	{
+	  expressionS dummy;
+
+	  sep = parse_operand (&dummy, '=');
+	  if (dummy.X_op == O_absent)
+	    break;
+	}
 
       ++num_operands;
 
@@ -5738,44 +6300,59 @@ parse_operands (idesc)
       return 0;
     }
 
-  if (idesc->operands[2] == IA64_OPND_SOF)
+  if (idesc->operands[2] == IA64_OPND_SOF
+      || idesc->operands[1] == IA64_OPND_SOF)
     {
-      /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */
+      /* Map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r.
+	 Note, however, that due to that mapping operand numbers in error
+	 messages for any of the constant operands will not be correct.  */
       know (strcmp (idesc->name, "alloc") == 0);
-      if (num_operands == 5 /* first_arg not included in this count! */
-	  && CURR_SLOT.opnd[2].X_op == O_constant
-	  && CURR_SLOT.opnd[3].X_op == O_constant
-	  && CURR_SLOT.opnd[4].X_op == O_constant
-	  && CURR_SLOT.opnd[5].X_op == O_constant)
-	{
-	  sof = set_regstack (CURR_SLOT.opnd[2].X_add_number,
-			      CURR_SLOT.opnd[3].X_add_number,
-			      CURR_SLOT.opnd[4].X_add_number,
-			      CURR_SLOT.opnd[5].X_add_number);
-
-	  /* now we can parse the first arg:  */
-	  saved_input_pointer = input_line_pointer;
-	  input_line_pointer = first_arg;
-	  sep = parse_operand (CURR_SLOT.opnd + 0);
-	  if (sep != '=')
-	    --num_outputs;	/* force error */
-	  input_line_pointer = saved_input_pointer;
-
-	  CURR_SLOT.opnd[2].X_add_number = sof;
-	  CURR_SLOT.opnd[3].X_add_number
-	    = sof - CURR_SLOT.opnd[4].X_add_number;
-	  CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5];
-	}
+      /* The first operand hasn't been parsed/initialized, yet (but
+	 num_operands intentionally doesn't account for that).  */
+      i = num_operands > 4 ? 2 : 1;
+#define FORCE_CONST(n) (CURR_SLOT.opnd[n].X_op == O_constant \
+			? CURR_SLOT.opnd[n].X_add_number \
+			: 0)
+      sof = set_regstack (FORCE_CONST(i),
+			  FORCE_CONST(i + 1),
+			  FORCE_CONST(i + 2),
+			  FORCE_CONST(i + 3));
+#undef FORCE_CONST
+
+      /* now we can parse the first arg:  */
+      saved_input_pointer = input_line_pointer;
+      input_line_pointer = first_arg;
+      sep = parse_operand (CURR_SLOT.opnd + 0, '=');
+      if (sep != '=')
+	--num_outputs;	/* force error */
+      input_line_pointer = saved_input_pointer;
+
+      CURR_SLOT.opnd[i].X_add_number = sof;
+      if (CURR_SLOT.opnd[i + 1].X_op == O_constant
+	  && CURR_SLOT.opnd[i + 2].X_op == O_constant)
+	CURR_SLOT.opnd[i + 1].X_add_number
+	  = sof - CURR_SLOT.opnd[i + 2].X_add_number;
+      else
+	CURR_SLOT.opnd[i + 1].X_op = O_illegal;
+      CURR_SLOT.opnd[i + 2] = CURR_SLOT.opnd[i + 3];
     }
 
-  highest_unmatched_operand = 0;
+  highest_unmatched_operand = -4;
   curr_out_of_range_pos = -1;
   error_pos = 0;
-  expected_operand = idesc->operands[0];
   for (; idesc; idesc = get_next_opcode (idesc))
     {
       if (num_outputs != idesc->num_outputs)
 	continue;		/* mismatch in # of outputs */
+      if (highest_unmatched_operand < 0)
+	highest_unmatched_operand |= 1;
+      if (num_operands > NELEMS (idesc->operands)
+	  || (num_operands < NELEMS (idesc->operands)
+	   && idesc->operands[num_operands])
+	  || (num_operands > 0 && !idesc->operands[num_operands - 1]))
+	continue;		/* mismatch in number of arguments */
+      if (highest_unmatched_operand < 0)
+	highest_unmatched_operand |= 2;
 
       CURR_SLOT.num_fixups = 0;
 
@@ -5828,10 +6405,6 @@ parse_operands (idesc)
 	  continue;
 	}
 
-      if (num_operands < NELEMS (idesc->operands)
-	  && idesc->operands[num_operands])
-	continue;		/* mismatch in number of arguments */
-
       break;
     }
   if (!idesc)
@@ -5840,103 +6413,136 @@ parse_operands (idesc)
 	as_bad ("Operand %u of `%s' should be %s",
 		error_pos + 1, mnemonic,
 		elf64_ia64_operands[expected_operand].desc);
+      else if (highest_unmatched_operand < 0 && !(highest_unmatched_operand & 1))
+	as_bad ("Wrong number of output operands");
+      else if (highest_unmatched_operand < 0 && !(highest_unmatched_operand & 2))
+	as_bad ("Wrong number of input operands");
       else
 	as_bad ("Operand mismatch");
       return 0;
     }
-  return idesc;
-}
-
-/* Keep track of state necessary to determine whether a NOP is necessary
-   to avoid an erratum in A and B step Itanium chips, and return 1 if we
-   detect a case where additional NOPs may be necessary.  */
-static int
-errata_nop_necessary_p (slot, insn_unit)
-     struct slot *slot;
-     enum ia64_unit insn_unit;
-{
-  int i;
-  struct group *this_group = md.last_groups + md.group_idx;
-  struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3;
-  struct ia64_opcode *idesc = slot->idesc;
-
-  /* Test whether this could be the first insn in a problematic sequence.  */
-  if (insn_unit == IA64_UNIT_F)
-    {
-      for (i = 0; i < idesc->num_outputs; i++)
-	if (idesc->operands[i] == IA64_OPND_P1
-	    || idesc->operands[i] == IA64_OPND_P2)
-	  {
-	    int regno = slot->opnd[i].X_add_number - REG_P;
-	    /* Ignore invalid operands; they generate errors elsewhere.  */
-	    if (regno >= 64)
-	      return 0;
-	    this_group->p_reg_set[regno] = 1;
-	  }
-    }
 
-  /* Test whether this could be the second insn in a problematic sequence.  */
-  if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0
-      && prev_group->p_reg_set[slot->qp_regno])
+  /* Check that the instruction doesn't use
+     - r0, f0, or f1 as output operands
+     - the same predicate twice as output operands
+     - r0 as address of a base update load or store
+     - the same GR as output and address of a base update load
+     - two even- or two odd-numbered FRs as output operands of a floating
+       point parallel load.
+     At most two (conflicting) output (or output-like) operands can exist,
+     (floating point parallel loads have three outputs, but the base register,
+     if updated, cannot conflict with the actual outputs).  */
+  reg2 = reg1 = -1;
+  for (i = 0; i < num_operands; ++i)
     {
-      for (i = 0; i < idesc->num_outputs; i++)
-	if (idesc->operands[i] == IA64_OPND_R1
-	    || idesc->operands[i] == IA64_OPND_R2
-	    || idesc->operands[i] == IA64_OPND_R3)
-	  {
-	    int regno = slot->opnd[i].X_add_number - REG_GR;
-	    /* Ignore invalid operands; they generate errors elsewhere.  */
-	    if (regno >= 128)
-	      return 0;
-	    if (strncmp (idesc->name, "add", 3) != 0
-		&& strncmp (idesc->name, "sub", 3) != 0
-		&& strncmp (idesc->name, "shladd", 6) != 0
-		&& (idesc->flags & IA64_OPCODE_POSTINC) == 0)
-	      this_group->g_reg_set_conditionally[regno] = 1;
-	  }
-    }
+      int regno = 0;
 
-  /* Test whether this could be the third insn in a problematic sequence.  */
-  for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++)
-    {
-      if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc.  */
-	  idesc->operands[i] == IA64_OPND_R3
-	  /* For mov indirect.  */
-	  || idesc->operands[i] == IA64_OPND_RR_R3
-	  || idesc->operands[i] == IA64_OPND_DBR_R3
-	  || idesc->operands[i] == IA64_OPND_IBR_R3
-	  || idesc->operands[i] == IA64_OPND_PKR_R3
-	  || idesc->operands[i] == IA64_OPND_PMC_R3
-	  || idesc->operands[i] == IA64_OPND_PMD_R3
-	  || idesc->operands[i] == IA64_OPND_MSR_R3
-	  || idesc->operands[i] == IA64_OPND_CPUID_R3
-	  /* For itr.  */
-	  || idesc->operands[i] == IA64_OPND_ITR_R3
-	  || idesc->operands[i] == IA64_OPND_DTR_R3
-	  /* Normal memory addresses (load, store, xchg, cmpxchg, etc.).  */
-	  || idesc->operands[i] == IA64_OPND_MR3)
-	{
-	  int regno = slot->opnd[i].X_add_number - REG_GR;
-	  /* Ignore invalid operands; they generate errors elsewhere.  */
-	  if (regno >= 128)
-	    return 0;
-	  if (idesc->operands[i] == IA64_OPND_R3)
-	    {
-	      if (strcmp (idesc->name, "fc") != 0
-		  && strcmp (idesc->name, "tak") != 0
-		  && strcmp (idesc->name, "thash") != 0
-		  && strcmp (idesc->name, "tpa") != 0
-		  && strcmp (idesc->name, "ttag") != 0
-		  && strncmp (idesc->name, "ptr", 3) != 0
-		  && strncmp (idesc->name, "ptc", 3) != 0
-		  && strncmp (idesc->name, "probe", 5) != 0)
-		return 0;
-	    }
-	  if (prev_group->g_reg_set_conditionally[regno])
-	    return 1;
+      reg_class = 0;
+      switch (idesc->operands[i])
+	{
+	case IA64_OPND_R1:
+	case IA64_OPND_R2:
+	case IA64_OPND_R3:
+	  if (i < num_outputs)
+	    {
+	      if (CURR_SLOT.opnd[i].X_add_number == REG_GR)
+		reg_class = 'r';
+	      else if (reg1 < 0)
+		reg1 = CURR_SLOT.opnd[i].X_add_number;
+	      else if (reg2 < 0)
+		reg2 = CURR_SLOT.opnd[i].X_add_number;
+	    }
+	  break;
+	case IA64_OPND_P1:
+	case IA64_OPND_P2:
+	  if (i < num_outputs)
+	    {
+	      if (reg1 < 0)
+		reg1 = CURR_SLOT.opnd[i].X_add_number;
+	      else if (reg2 < 0)
+		reg2 = CURR_SLOT.opnd[i].X_add_number;
+	    }
+	  break;
+	case IA64_OPND_F1:
+	case IA64_OPND_F2:
+	case IA64_OPND_F3:
+	case IA64_OPND_F4:
+	  if (i < num_outputs)
+	    {
+	      if (CURR_SLOT.opnd[i].X_add_number >= REG_FR
+		  && CURR_SLOT.opnd[i].X_add_number <= REG_FR + 1)
+		{
+		  reg_class = 'f';
+		  regno = CURR_SLOT.opnd[i].X_add_number - REG_FR;
+		}
+	      else if (reg1 < 0)
+		reg1 = CURR_SLOT.opnd[i].X_add_number;
+	      else if (reg2 < 0)
+		reg2 = CURR_SLOT.opnd[i].X_add_number;
+	    }
+	  break;
+	case IA64_OPND_MR3:
+	  if (idesc->flags & IA64_OPCODE_POSTINC)
+	    {
+	      if (CURR_SLOT.opnd[i].X_add_number == REG_GR)
+		reg_class = 'm';
+	      else if (reg1 < 0)
+		reg1 = CURR_SLOT.opnd[i].X_add_number;
+	      else if (reg2 < 0)
+		reg2 = CURR_SLOT.opnd[i].X_add_number;
+	    }
+	  break;
+	default:
+	  break;
+	}
+      switch (reg_class)
+	{
+	case 0:
+	  break;
+	default:
+	  as_warn ("Invalid use of `%c%d' as output operand", reg_class, regno);
+	  break;
+	case 'm':
+	  as_warn ("Invalid use of `r%d' as base update address operand", regno);
+	  break;
 	}
     }
-  return 0;
+  if (reg1 == reg2)
+    {
+      if (reg1 >= REG_GR && reg1 <= REG_GR + 127)
+	{
+	  reg1 -= REG_GR;
+	  reg_class = 'r';
+	}
+      else if (reg1 >= REG_P && reg1 <= REG_P + 63)
+	{
+	  reg1 -= REG_P;
+	  reg_class = 'p';
+	}
+      else if (reg1 >= REG_FR && reg1 <= REG_FR + 127)
+	{
+	  reg1 -= REG_FR;
+	  reg_class = 'f';
+	}
+      else
+	reg_class = 0;
+      if (reg_class)
+	as_warn ("Invalid duplicate use of `%c%d'", reg_class, reg1);
+    }
+  else if (((reg1 >= REG_FR && reg1 <= REG_FR + 31
+	     && reg2 >= REG_FR && reg2 <= REG_FR + 31)
+	    || (reg1 >= REG_FR + 32 && reg1 <= REG_FR + 127
+	     && reg2 >= REG_FR + 32 && reg2 <= REG_FR + 127))
+	   && ! ((reg1 ^ reg2) & 1))
+    as_warn ("Invalid simultaneous use of `f%d' and `f%d'",
+	     reg1 - REG_FR, reg2 - REG_FR);
+  else if ((reg1 >= REG_FR && reg1 <= REG_FR + 31
+	    && reg2 >= REG_FR + 32 && reg2 <= REG_FR + 127)
+	   || (reg1 >= REG_FR + 32 && reg1 <= REG_FR + 127
+	    && reg2 >= REG_FR && reg2 <= REG_FR + 31))
+    as_warn ("Dangerous simultaneous use of `f%d' and `f%d'",
+	     reg1 - REG_FR, reg2 - REG_FR);
+  return idesc;
 }
 
 static void
@@ -5946,7 +6552,8 @@ build_insn (slot, insnp)
 {
   const struct ia64_operand *odesc, *o2desc;
   struct ia64_opcode *idesc = slot->idesc;
-  bfd_signed_vma insn, val;
+  bfd_vma insn;
+  bfd_signed_vma val;
   const char *err;
   int i;
 
@@ -6066,22 +6673,22 @@ build_insn (slot, insnp)
 static void
 emit_one_bundle ()
 {
-  unsigned int manual_bundling_on = 0, manual_bundling_off = 0;
-  unsigned int manual_bundling = 0;
+  int manual_bundling_off = 0, manual_bundling = 0;
   enum ia64_unit required_unit, insn_unit = 0;
   enum ia64_insn_type type[3], insn_type;
   unsigned int template, orig_template;
   bfd_vma insn[3] = { -1, -1, -1 };
   struct ia64_opcode *idesc;
   int end_of_insn_group = 0, user_template = -1;
-  int n, i, j, first, curr;
-  unw_rec_list *ptr, *last_ptr, *end_ptr;
+  int n, i, j, first, curr, last_slot;
   bfd_vma t0 = 0, t1 = 0;
   struct label_fix *lfix;
+  bfd_boolean mark_label;
   struct insn_fix *ifix;
   char mnemonic[16];
   fixS *fix;
   char *f;
+  int addr_mod;
 
   first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS;
   know (first >= 0 & first < NUM_SLOTS);
@@ -6113,14 +6720,25 @@ emit_one_bundle ()
 
   f = frag_more (16);
 
+  /* Check to see if this bundle is at an offset that is a multiple of 16-bytes
+     from the start of the frag.  */
+  addr_mod = frag_now_fix () & 15;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 16"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
+
   /* now fill in slots with as many insns as possible:  */
   curr = first;
   idesc = md.slot[curr].idesc;
   end_of_insn_group = 0;
+  last_slot = -1;
   for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i)
     {
       /* If we have unwind records, we may need to update some now.  */
-      ptr = md.slot[curr].unwind_record;
+      unw_rec_list *ptr = md.slot[curr].unwind_record;
+      unw_rec_list *end_ptr = NULL;
+
       if (ptr)
 	{
 	  /* Find the last prologue/body record in the list for the current
@@ -6130,9 +6748,11 @@ emit_one_bundle ()
 	     issued.  This matters because there may have been nops emitted
 	     meanwhile.  Any non-prologue non-body record followed by a
 	     prologue/body record must also refer to the current point.  */
-	  last_ptr = NULL;
-	  end_ptr = md.slot[(curr + 1) % NUM_SLOTS].unwind_record;
-	  for (; ptr != end_ptr; ptr = ptr->next)
+	  unw_rec_list *last_ptr;
+
+	  for (j = 1; end_ptr == NULL && j < md.num_slots_in_use; ++j)
+	    end_ptr = md.slot[(curr + j) % NUM_SLOTS].unwind_record;
+	  for (last_ptr = NULL; ptr != end_ptr; ptr = ptr->next)
 	    if (ptr->r.type == prologue || ptr->r.type == prologue_gr
 		|| ptr->r.type == body)
 	      last_ptr = ptr;
@@ -6153,13 +6773,30 @@ emit_one_bundle ()
 	    }
 	}
 
-      if (idesc->flags & IA64_OPCODE_SLOT2)
+      manual_bundling_off = md.slot[curr].manual_bundling_off;
+      if (md.slot[curr].manual_bundling_on)
 	{
-	  if (manual_bundling && i != 2)
-	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
-			  "`%s' must be last in bundle", idesc->name);
+	  if (curr == first)
+	    manual_bundling = 1;
 	  else
-	    i = 2;
+	  break; /* Need to start a new bundle.  */
+	}
+
+      /* If this instruction specifies a template, then it must be the first
+	 instruction of a bundle.  */
+      if (curr != first && md.slot[curr].user_template >= 0)
+	break;
+
+      if (idesc->flags & IA64_OPCODE_SLOT2)
+	{
+	  if (manual_bundling && !manual_bundling_off)
+	    {
+	      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			    "`%s' must be last in bundle", idesc->name);
+	      if (i < 2)
+		manual_bundling = -1; /* Suppress meaningless post-loop errors.  */
+	    }
+	  i = 2;
 	}
       if (idesc->flags & IA64_OPCODE_LAST)
 	{
@@ -6192,10 +6829,19 @@ emit_one_bundle ()
 	      required_slot = i;
 	      break;
 	    }
-	  if (manual_bundling && i != required_slot)
-	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
-			  "`%s' must be last in instruction group",
-			  idesc->name);
+	  if (manual_bundling
+	      && (i > required_slot
+		  || (required_slot == 2 && !manual_bundling_off)
+		  || (user_template >= 0
+		      /* Changing from MMI to M;MI is OK.  */
+		      && (template ^ required_template) > 1)))
+	    {
+	      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			    "`%s' must be last in instruction group",
+			    idesc->name);
+	      if (i < 2 && required_slot == 2 && !manual_bundling_off)
+		manual_bundling = -1; /* Suppress meaningless post-loop errors.  */
+	    }
 	  if (required_slot < i)
 	    /* Can't fit this instruction.  */
 	    break;
@@ -6209,29 +6855,25 @@ emit_one_bundle ()
 	         changing NOPs in front of this slot.  */
 	      for (j = i; j < 3; ++j)
 	        insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]];
+
+	      /* We just picked a template that includes the stop bit in the
+		 middle, so we don't need another one emitted later.  */
+	      md.slot[curr].end_of_insn_group = 0;
 	    }
 	  template = required_template;
 	}
       if (curr != first && md.slot[curr].label_fixups)
 	{
-	  if (manual_bundling_on)
-	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+	  if (manual_bundling)
+	    {
+	      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
 			  "Label must be first in a bundle");
+	      manual_bundling = -1; /* Suppress meaningless post-loop errors.  */
+	    }
 	  /* This insn must go into the first slot of a bundle.  */
 	  break;
 	}
 
-      manual_bundling_on = md.slot[curr].manual_bundling_on;
-      manual_bundling_off = md.slot[curr].manual_bundling_off;
-
-      if (manual_bundling_on)
-	{
-	  if (curr == first)
-	    manual_bundling = 1;
-	  else
-	    break;			/* need to start a new bundle */
-	}
-
       if (end_of_insn_group && md.num_slots_in_use >= 1)
 	{
 	  /* We need an instruction group boundary in the middle of a
@@ -6259,12 +6901,17 @@ emit_one_bundle ()
 		      reason we have to check for this is that otherwise we
 		      may end up generating "MI;;I M.." which has the deadly
 		      effect that the second M instruction is no longer the
-		      first in the bundle! --davidm 99/12/16  */
+		      first in the group! --davidm 99/12/16  */
 		   && (idesc->flags & IA64_OPCODE_FIRST) == 0)
 	    {
 	      template = 1;
 	      end_of_insn_group = 0;
 	    }
+	  else if (i == 1
+		   && user_template == 0
+		   && !(idesc->flags & IA64_OPCODE_FIRST))
+	    /* Use the next slot.  */
+	    continue;
 	  else if (curr != first)
 	    /* can't fit this insn */
 	    break;
@@ -6282,25 +6929,62 @@ emit_one_bundle ()
       /* resolve dynamic opcodes such as "break", "hint", and "nop":  */
       if (idesc->type == IA64_TYPE_DYN)
 	{
+	  enum ia64_opnd opnd1, opnd2;
+
 	  if ((strcmp (idesc->name, "nop") == 0)
-	      || (strcmp (idesc->name, "hint") == 0)
 	      || (strcmp (idesc->name, "break") == 0))
 	    insn_unit = required_unit;
-	  else if (strcmp (idesc->name, "chk.s") == 0)
+	  else if (strcmp (idesc->name, "hint") == 0)
+	    {
+	      insn_unit = required_unit;
+	      if (required_unit == IA64_UNIT_B)
+		{
+		  switch (md.hint_b)
+		    {
+		    case hint_b_ok:
+		      break;
+		    case hint_b_warning:
+		      as_warn ("hint in B unit may be treated as nop");
+		      break;
+		    case hint_b_error:
+		      /* When manual bundling is off and there is no
+			 user template, we choose a different unit so
+			 that hint won't go into the current slot. We
+			 will fill the current bundle with nops and
+			 try to put hint into the next bundle.  */
+		      if (!manual_bundling && user_template < 0)
+			insn_unit = IA64_UNIT_I;
+		      else
+			as_bad ("hint in B unit can't be used");
+		      break;
+		    }
+		}
+	    }
+	  else if (strcmp (idesc->name, "chk.s") == 0
+	      || strcmp (idesc->name, "mov") == 0)
 	    {
 	      insn_unit = IA64_UNIT_M;
-	      if (required_unit == IA64_UNIT_I)
+	      if (required_unit == IA64_UNIT_I
+		  || (required_unit == IA64_UNIT_F && template == 6))
 		insn_unit = IA64_UNIT_I;
 	    }
 	  else
 	    as_fatal ("emit_one_bundle: unexpected dynamic op");
 
-	  sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]);
+	  sprintf (mnemonic, "%s.%c", idesc->name, "?imbfxx"[insn_unit]);
+	  opnd1 = idesc->operands[0];
+	  opnd2 = idesc->operands[1];
 	  ia64_free_opcode (idesc);
-	  md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic);
-#if 0
-	  know (!idesc->next);	/* no resolved dynamic ops have collisions */
-#endif
+	  idesc = ia64_find_opcode (mnemonic);
+	  /* moves to/from ARs have collisions */
+	  if (opnd1 == IA64_OPND_AR3 || opnd2 == IA64_OPND_AR3)
+	    {
+	      while (idesc != NULL
+		     && (idesc->operands[0] != opnd1
+			 || idesc->operands[1] != opnd2))
+		idesc = get_next_opcode (idesc);
+	    }
+	  md.slot[curr].idesc = idesc;
 	}
       else
 	{
@@ -6322,37 +7006,34 @@ emit_one_bundle ()
 	}
 
       if (insn_unit != required_unit)
+	continue;		/* Try next slot.  */
+
+      /* Now is a good time to fix up the labels for this insn.  */
+      mark_label = FALSE;
+      for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
 	{
-	  if (required_unit == IA64_UNIT_L
-	      && insn_unit == IA64_UNIT_I
-	      && !(idesc->flags & IA64_OPCODE_X_IN_MLX))
-	    {
-	      /* we got ourselves an MLX template but the current
-		 instruction isn't an X-unit, or an I-unit instruction
-		 that can go into the X slot of an MLX template.  Duh.  */
-	      if (md.num_slots_in_use >= NUM_SLOTS)
-		{
-		  as_bad_where (md.slot[curr].src_file,
-				md.slot[curr].src_line,
-				"`%s' can't go in X slot of "
-				"MLX template", idesc->name);
-		  /* drop this insn so we don't livelock:  */
-		  --md.num_slots_in_use;
-		}
-	      break;
-	    }
-	  continue;		/* try next slot */
+	  S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
+	  symbol_set_frag (lfix->sym, frag_now);
+	  mark_label |= lfix->dw2_mark_labels;
+	}
+      for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
+	{
+	  S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
+	  symbol_set_frag (lfix->sym, frag_now);
 	}
 
-      {
-	bfd_vma addr;
+      if (debug_type == DEBUG_DWARF2
+	  || md.slot[curr].loc_directive_seen
+	  || mark_label)
+	{
+	  bfd_vma addr = frag_now->fr_address + frag_now_fix () - 16 + i;
 
-	addr = frag_now->fr_address + frag_now_fix () - 16 + i;
-	dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
-      }
+	  md.slot[curr].loc_directive_seen = 0;
+	  if (mark_label)
+	    md.slot[curr].debug_line.flags |= DWARF2_FLAG_BASIC_BLOCK;
 
-      if (errata_nop_necessary_p (md.slot + curr, insn_unit))
-	as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata"));
+	  dwarf2_gen_line_info (addr, &md.slot[curr].debug_line);
+	}
 
       build_insn (md.slot + curr, insn + i);
 
@@ -6362,7 +7043,6 @@ emit_one_bundle ()
 	  /* Set slot numbers for all remaining unwind records belonging to the
 	     current insn.  There can not be any prologue/body unwind records
 	     here.  */
-	  end_ptr = md.slot[(curr + 1) % NUM_SLOTS].unwind_record;
 	  for (; ptr != end_ptr; ptr = ptr->next)
 	    {
 	      ptr->slot_number = (unsigned long) f + i;
@@ -6378,19 +7058,7 @@ emit_one_bundle ()
 	  ++i;
 	}
       --md.num_slots_in_use;
-
-      /* now is a good time to fix up the labels for this insn:  */
-      for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next)
-	{
-	  S_SET_VALUE (lfix->sym, frag_now_fix () - 16);
-	  symbol_set_frag (lfix->sym, frag_now);
-	}
-      /* and fix up the tags also.  */
-      for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next)
-	{
-	  S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i);
-	  symbol_set_frag (lfix->sym, frag_now);
-	}
+      last_slot = i;
 
       for (j = 0; j < md.slot[curr].num_fixups; ++j)
 	{
@@ -6405,12 +7073,6 @@ emit_one_bundle ()
 
       end_of_insn_group = md.slot[curr].end_of_insn_group;
 
-      if (end_of_insn_group)
-	{
-	  md.group_idx = (md.group_idx + 1) % 3;
-	  memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]);
-	}
-
       /* clear slot:  */
       ia64_free_opcode (md.slot[curr].idesc);
       memset (md.slot + curr, 0, sizeof (md.slot[curr]));
@@ -6424,16 +7086,48 @@ emit_one_bundle ()
       curr = (curr + 1) % NUM_SLOTS;
       idesc = md.slot[curr].idesc;
     }
-  if (manual_bundling)
+
+  /* A user template was specified, but the first following instruction did
+     not fit.  This can happen with or without manual bundling.  */
+  if (md.num_slots_in_use > 0 && last_slot < 0)
+    {
+      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+		    "`%s' does not fit into %s template",
+		    idesc->name, ia64_templ_desc[template].name);
+      /* Drop first insn so we don't livelock.  */
+      --md.num_slots_in_use;
+      know (curr == first);
+      ia64_free_opcode (md.slot[curr].idesc);
+      memset (md.slot + curr, 0, sizeof (md.slot[curr]));
+      md.slot[curr].user_template = -1;
+    }
+  else if (manual_bundling > 0)
     {
       if (md.num_slots_in_use > 0)
-	as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
-		      "`%s' does not fit into %s template",
-		      idesc->name, ia64_templ_desc[template].name);
+	{
+	  if (last_slot >= 2)
+	    as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			  "`%s' does not fit into bundle", idesc->name);
+	  else
+	    {
+	      const char *where;
+
+	      if (template == 2)
+		where = "X slot";
+	      else if (last_slot == 0)
+		where = "slots 2 or 3";
+	      else
+		where = "slot 3";
+	      as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
+			    "`%s' can't go in %s of %s template",
+			    idesc->name, where, ia64_templ_desc[template].name);
+	    }
+	}
       else
 	as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line,
 		      "Missing '}' at end of file");
     }
+	
   know (md.num_slots_in_use < NUM_SLOTS);
 
   t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46);
@@ -6441,12 +7135,6 @@ emit_one_bundle ()
 
   number_to_chars_littleendian (f + 0, t0, 8);
   number_to_chars_littleendian (f + 8, t1, 8);
-
-  if (unwind.list)
-    {
-      unwind.list->next_slot_number = (unsigned long) f + 16;
-      unwind.list->next_slot_frag = frag_now;
-    }
 }
 
 int
@@ -6472,10 +7160,44 @@ md_parse_option (c, arg)
       else if (strcmp (arg, "le") == 0)
 	{
 	  md.flags &= ~EF_IA_64_BE;
+	  default_big_endian = 0;
 	}
       else if (strcmp (arg, "be") == 0)
 	{
 	  md.flags |= EF_IA_64_BE;
+	  default_big_endian = 1;
+	}
+      else if (strncmp (arg, "unwind-check=", 13) == 0)
+	{
+	  arg += 13;
+	  if (strcmp (arg, "warning") == 0)
+	    md.unwind_check = unwind_check_warning;
+	  else if (strcmp (arg, "error") == 0)
+	    md.unwind_check = unwind_check_error;
+	  else
+	    return 0;
+	}
+      else if (strncmp (arg, "hint.b=", 7) == 0)
+	{
+	  arg += 7;
+	  if (strcmp (arg, "ok") == 0)
+	    md.hint_b = hint_b_ok;
+	  else if (strcmp (arg, "warning") == 0)
+	    md.hint_b = hint_b_warning;
+	  else if (strcmp (arg, "error") == 0)
+	    md.hint_b = hint_b_error;
+	  else
+	    return 0;
+	}
+      else if (strncmp (arg, "tune=", 5) == 0)
+	{
+	  arg += 5;
+	  if (strcmp (arg, "itanium1") == 0)
+	    md.tune = itanium1;
+	  else if (strcmp (arg, "itanium2") == 0)
+	    md.tune = itanium2;
+	  else
+	    return 0;
 	}
       else
 	return 0;
@@ -6532,6 +7254,10 @@ md_parse_option (c, arg)
 	{
 	  md.default_explicit_mode = 0;
 	}
+      else if (strcmp (arg, "none") == 0)
+	{
+	  md.detect_dv = 0;
+	}
       else if (strcmp (arg, "debug") == 0)
 	{
 	  md.debug_dv = 1;
@@ -6541,6 +7267,11 @@ md_parse_option (c, arg)
 	  md.default_explicit_mode = 1;
 	  md.debug_dv = 1;
 	}
+      else if (strcmp (arg, "debugn") == 0)
+	{
+	  md.debug_dv = 1;
+	  md.detect_dv = 0;
+	}
       else
 	{
 	  as_bad (_("Unrecognized option '-x%s'"), arg);
@@ -6580,9 +7311,20 @@ IA-64 options:\n\
 			  EF_IA_64_NOFUNCDESC_CONS_GP)\n\
   -milp32|-milp64|-mlp64|-mp64	select data model (default -mlp64)\n\
   -mle | -mbe		  select little- or big-endian byte order (default -mle)\n\
-  -x | -xexplicit	  turn on dependency violation checking (default)\n\
-  -xauto		  automagically remove dependency violations\n\
-  -xdebug		  debug dependency violation checker\n"),
+  -mtune=[itanium1|itanium2]\n\
+			  tune for a specific CPU (default -mtune=itanium2)\n\
+  -munwind-check=[warning|error]\n\
+			  unwind directive check (default -munwind-check=warning)\n\
+  -mhint.b=[ok|warning|error]\n\
+			  hint.b check (default -mhint.b=error)\n\
+  -x | -xexplicit	  turn on dependency violation checking\n\
+  -xauto		  automagically remove dependency violations (default)\n\
+  -xnone		  turn off dependency violation checking\n\
+  -xdebug		  debug dependency violation checker\n\
+  -xdebugn		  debug dependency violation checker but turn off\n\
+			  dependency violation checking\n\
+  -xdebugx		  debug dependency violation checker and turn on\n\
+			  dependency violation checking\n"),
 	stream);
 }
 
@@ -6618,17 +7360,37 @@ match (int templ, int type, int slot)
   return result;
 }
 
-/* Add a bit of extra goodness if a nop of type F or B would fit
-   in TEMPL at SLOT.  */
+/* For Itanium 1, add a bit of extra goodness if a nop of type F or B would fit
+   in TEMPL at SLOT.  For Itanium 2, add a bit of extra goodness if a nop of
+   type M or I would fit in TEMPL at SLOT.  */
 
 static inline int
 extra_goodness (int templ, int slot)
 {
-  if (slot == 1 && match (templ, IA64_TYPE_F, slot))
-    return 2;
-  if (slot == 2 && match (templ, IA64_TYPE_B, slot))
-    return 1;
-  return 0;
+  switch (md.tune)
+    {
+    case itanium1:
+      if (slot == 1 && match (templ, IA64_TYPE_F, slot))
+	return 2;
+      else if (slot == 2 && match (templ, IA64_TYPE_B, slot))
+	return 1;
+      else
+	return 0;
+      break;
+    case itanium2:
+      if (match (templ, IA64_TYPE_M, slot)
+	  || match (templ, IA64_TYPE_I, slot))
+	/* Favor M- and I-unit NOPs.  We definitely want to avoid
+	   F-unit and B-unit may cause split-issue or less-than-optimal
+	   branch-prediction.  */
+	return 2;
+      else
+	return 0;
+      break;
+    default:
+      abort ();
+      return 0;
+    }
 }
 
 /* This function is called once, at assembler startup time.  It sets
@@ -6637,7 +7399,7 @@ extra_goodness (int templ, int slot)
 void
 md_begin ()
 {
-  int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok;
+  int i, j, k, t, goodness, best, ok;
   const char *err;
   char name[8];
 
@@ -6648,7 +7410,7 @@ md_begin ()
 
   /* Make sure function pointers get initialized.  */
   target_big_endian = -1;
-  dot_byteorder (TARGET_BYTES_BIG_ENDIAN);
+  dot_byteorder (default_big_endian);
 
   alias_hash = hash_new ();
   alias_name_hash = hash_new ();
@@ -6723,11 +7485,17 @@ md_begin ()
     symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC,
 		&zero_address_frag);
 
+ if (md.tune != itanium1)
+   {
+     /* Convert MFI NOPs bundles into MMI NOPs bundles.  */
+     le_nop[0] = 0x8;
+     le_nop_stop[0] = 0x9;
+   }
+
   /* Compute the table of best templates.  We compute goodness as a
-     base 4 value, in which each match counts for 3, each F counts
-     for 2, each B counts for 1.  This should maximize the number of
-     F and B nops in the chosen bundles, which is good because these
-     pipelines are least likely to be overcommitted.  */
+     base 4 value, in which each match counts for 3.  Match-failures
+     result in NOPs and we use extra_goodness() to pick the execution
+     units that are best suited for issuing the NOP.  */
   for (i = 0; i < IA64_NUM_TYPES; ++i)
     for (j = 0; j < IA64_NUM_TYPES; ++j)
       for (k = 0; k < IA64_NUM_TYPES; ++k)
@@ -6740,7 +7508,7 @@ md_begin ()
 		{
 		  if (match (t, j, 1))
 		    {
-		      if (match (t, k, 2))
+		      if ((t == 2 && j == IA64_TYPE_X) || match (t, k, 2))
 			goodness = 3 + 3 + 3;
 		      else
 			goodness = 3 + 3 + extra_goodness (t, 2);
@@ -6756,7 +7524,7 @@ md_begin ()
 		}
 	      else if (match (t, i, 1))
 		{
-		  if (match (t, j, 2))
+		  if ((t == 2 && i == IA64_TYPE_X) || match (t, j, 2))
 		    goodness = 3 + 3;
 		  else
 		    goodness = 3 + extra_goodness (t, 2);
@@ -6772,6 +7540,21 @@ md_begin ()
 	    }
 	}
 
+#ifdef DEBUG_TEMPLATES
+  /* For debugging changes to the best_template calculations.  We don't care
+     about combinations with invalid instructions, so start the loops at 1.  */
+  for (i = 0; i < IA64_NUM_TYPES; ++i)
+    for (j = 0; j < IA64_NUM_TYPES; ++j)
+      for (k = 0; k < IA64_NUM_TYPES; ++k)
+	{
+	  char type_letter[IA64_NUM_TYPES] = { 'n', 'a', 'i', 'm', 'b', 'f',
+					       'x', 'd' };
+	  fprintf (stderr, "%c%c%c %s\n", type_letter[i], type_letter[j],
+		   type_letter[k],
+		   ia64_templ_desc[best_template[i][j][k]].name);
+	}
+#endif
+
   for (i = 0; i < NUM_SLOTS; ++i)
     md.slot[i].user_template = -1;
 
@@ -6791,91 +7574,52 @@ md_begin ()
   md.entry_hash = hash_new ();
 
   /* general registers:  */
-
-  total = 128;
-  for (i = 0; i < total; ++i)
-    {
-      sprintf (name, "r%d", i - REG_GR);
-      md.regsym[i] = declare_register (name, i);
-    }
+  declare_register_set ("r", 128, REG_GR);
+  declare_register ("gp", REG_GR +  1);
+  declare_register ("sp", REG_GR + 12);
+  declare_register ("tp", REG_GR + 13);
+  declare_register_set ("ret", 4, REG_GR + 8);
 
   /* floating point registers:  */
-  total += 128;
-  for (; i < total; ++i)
-    {
-      sprintf (name, "f%d", i - REG_FR);
-      md.regsym[i] = declare_register (name, i);
-    }
-
-  /* application registers:  */
-  total += 128;
-  ar_base = i;
-  for (; i < total; ++i)
-    {
-      sprintf (name, "ar%d", i - REG_AR);
-      md.regsym[i] = declare_register (name, i);
-    }
+  declare_register_set ("f", 128, REG_FR);
+  declare_register_set ("farg", 8, REG_FR + 8);
+  declare_register_set ("fret", 8, REG_FR + 8);
 
-  /* control registers:  */
-  total += 128;
-  cr_base = i;
-  for (; i < total; ++i)
-    {
-      sprintf (name, "cr%d", i - REG_CR);
-      md.regsym[i] = declare_register (name, i);
-    }
+  /* branch registers:  */
+  declare_register_set ("b", 8, REG_BR);
+  declare_register ("rp", REG_BR + 0);
 
   /* predicate registers:  */
-  total += 64;
-  for (; i < total; ++i)
-    {
-      sprintf (name, "p%d", i - REG_P);
-      md.regsym[i] = declare_register (name, i);
-    }
+  declare_register_set ("p", 64, REG_P);
+  declare_register ("pr", REG_PR);
+  declare_register ("pr.rot", REG_PR_ROT);
 
-  /* branch registers:  */
-  total += 8;
-  for (; i < total; ++i)
-    {
-      sprintf (name, "b%d", i - REG_BR);
-      md.regsym[i] = declare_register (name, i);
-    }
+  /* application registers:  */
+  declare_register_set ("ar", 128, REG_AR);
+  for (i = 0; i < NELEMS (ar); ++i)
+    declare_register (ar[i].name, REG_AR + ar[i].regnum);
+
+  /* control registers:  */
+  declare_register_set ("cr", 128, REG_CR);
+  for (i = 0; i < NELEMS (cr); ++i)
+    declare_register (cr[i].name, REG_CR + cr[i].regnum);
 
-  md.regsym[REG_IP] = declare_register ("ip", REG_IP);
-  md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM);
-  md.regsym[REG_PR] = declare_register ("pr", REG_PR);
-  md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT);
-  md.regsym[REG_PSR] = declare_register ("psr", REG_PSR);
-  md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L);
-  md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM);
+  declare_register ("ip", REG_IP);
+  declare_register ("cfm", REG_CFM);
+  declare_register ("psr", REG_PSR);
+  declare_register ("psr.l", REG_PSR_L);
+  declare_register ("psr.um", REG_PSR_UM);
 
   for (i = 0; i < NELEMS (indirect_reg); ++i)
     {
-      regnum = indirect_reg[i].regnum;
-      md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum);
-    }
-
-  /* define synonyms for application registers:  */
-  for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i)
-    md.regsym[i] = declare_register (ar[i - REG_AR].name,
-				     REG_AR + ar[i - REG_AR].regnum);
-
-  /* define synonyms for control registers:  */
-  for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i)
-    md.regsym[i] = declare_register (cr[i - REG_CR].name,
-				     REG_CR + cr[i - REG_CR].regnum);
+      unsigned int regnum = indirect_reg[i].regnum;
 
-  declare_register ("gp", REG_GR +  1);
-  declare_register ("sp", REG_GR + 12);
-  declare_register ("rp", REG_BR +  0);
+      md.indregsym[regnum - IND_CPUID] = declare_register (indirect_reg[i].name, regnum);
+    }
 
   /* pseudo-registers used to specify unwind info:  */
   declare_register ("psp", REG_PSP);
 
-  declare_register_set ("ret", 4, REG_GR + 8);
-  declare_register_set ("farg", 8, REG_FR + 8);
-  declare_register_set ("fret", 8, REG_FR + 8);
-
   for (i = 0; i < NELEMS (const_bits); ++i)
     {
       err = hash_insert (md.const_hash, const_bits[i].name,
@@ -6914,10 +7658,9 @@ md_begin ()
   md.entry_labels = NULL;
 }
 
-/* Set the elf type to 64 bit ABI by default.  Cannot do this in md_begin
-   because that is called after md_parse_option which is where we do the
-   dynamic changing of md.flags based on -mlp64 or -milp32.  Also, set the
-   default endianness.  */
+/* Set the default options in md.  Cannot do this in md_begin because
+   that is called after md_parse_option which is where we set the
+   options in md based on command line options.  */
 
 void
 ia64_init (argc, argv)
@@ -6925,6 +7668,11 @@ ia64_init (argc, argv)
      char **argv ATTRIBUTE_UNUSED;
 {
   md.flags = MD_FLAGS_DEFAULT;
+  md.detect_dv = 1;
+  /* FIXME: We should change it to unwind_check_error someday.  */
+  md.unwind_check = unwind_check_warning;
+  md.hint_b = hint_b_error;
+  md.tune = itanium2;
 }
 
 /* Return a string for the target object file format.  */
@@ -6990,6 +7738,15 @@ ia64_end_of_source ()
 void
 ia64_start_line ()
 {
+  static int first;
+
+  if (!first) {
+    /* Make sure we don't reference input_line_pointer[-1] when that's
+       not valid.  */
+    first = 1;
+    return;
+  }
+
   if (md.qp.X_op == O_register)
     as_bad ("qualifying predicate not followed by instruction");
   md.qp.X_op = O_absent;
@@ -7000,42 +7757,20 @@ ia64_start_line ()
   if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';')
     {
       if (md.detect_dv && !md.explicit_mode)
-	as_warn (_("Explicit stops are ignored in auto mode"));
+	{
+	  static int warned;
+
+	  if (!warned)
+	    {
+	      warned = 1;
+	      as_warn (_("Explicit stops are ignored in auto mode"));
+	    }
+	}
       else
 	insn_group_break (1, 0, 0);
     }
-}
-
-/* This is a hook for ia64_frob_label, so that it can distinguish tags from
-   labels.  */
-static int defining_tag = 0;
-
-int
-ia64_unrecognized_line (ch)
-     int ch;
-{
-  switch (ch)
+  else if (input_line_pointer[-1] == '{')
     {
-    case '(':
-      expression (&md.qp);
-      if (*input_line_pointer++ != ')')
-	{
-	  as_bad ("Expected ')'");
-	  return 0;
-	}
-      if (md.qp.X_op != O_register)
-	{
-	  as_bad ("Qualifying predicate expected");
-	  return 0;
-	}
-      if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
-	{
-	  as_bad ("Predicate register expected");
-	  return 0;
-	}
-      return 1;
-
-    case '{':
       if (md.manual_bundling)
 	as_warn ("Found '{' when manual bundling is already turned on");
       else
@@ -7052,9 +7787,9 @@ ia64_unrecognized_line (ch)
 	  else
 	    as_warn (_("Found '{' after explicit switch to automatic mode"));
 	}
-      return 1;
-
-    case '}':
+    }
+  else if (input_line_pointer[-1] == '}')
+    {
       if (!md.manual_bundling)
 	as_warn ("Found '}' when manual bundling is off");
       else
@@ -7067,17 +7802,36 @@ ia64_unrecognized_line (ch)
 	  && !md.mode_explicitly_set
 	  && !md.default_explicit_mode)
 	dot_dv_mode ('A');
+    }
+}
 
-      /* Allow '{' to follow on the same line.  We also allow ";;", but that
-	 happens automatically because ';' is an end of line marker.  */
-      SKIP_WHITESPACE ();
-      if (input_line_pointer[0] == '{')
+/* This is a hook for ia64_frob_label, so that it can distinguish tags from
+   labels.  */
+static int defining_tag = 0;
+
+int
+ia64_unrecognized_line (ch)
+     int ch;
+{
+  switch (ch)
+    {
+    case '(':
+      expression_and_evaluate (&md.qp);
+      if (*input_line_pointer++ != ')')
 	{
-	  input_line_pointer++;
-	  return ia64_unrecognized_line ('{');
+	  as_bad ("Expected ')'");
+	  return 0;
+	}
+      if (md.qp.X_op != O_register)
+	{
+	  as_bad ("Qualifying predicate expected");
+	  return 0;
+	}
+      if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64)
+	{
+	  as_bad ("Predicate register expected");
+	  return 0;
 	}
-
-      demand_empty_rest_of_line ();
       return 1;
 
     case '[':
@@ -7162,6 +7916,7 @@ ia64_frob_label (sym)
       fix = obstack_alloc (&notes, sizeof (*fix));
       fix->sym = sym;
       fix->next = CURR_SLOT.tag_fixups;
+      fix->dw2_mark_labels = FALSE;
       CURR_SLOT.tag_fixups = fix;
 
       return;
@@ -7173,6 +7928,7 @@ ia64_frob_label (sym)
       fix = obstack_alloc (&notes, sizeof (*fix));
       fix->sym = sym;
       fix->next = CURR_SLOT.label_fixups;
+      fix->dw2_mark_labels = dwarf2_loc_mark_labels;
       CURR_SLOT.label_fixups = fix;
 
       /* Keep track of how many code entry points we've seen.  */
@@ -7227,52 +7983,148 @@ ia64_optimize_expr (l, op, r)
      operatorT op;
      expressionS *r;
 {
-  unsigned num_regs;
-
-  if (op == O_index)
+  if (op != O_index)
+    return 0;
+  resolve_expression (l);
+  if (l->X_op == O_register)
     {
-      if (l->X_op == O_register && r->X_op == O_constant)
+      unsigned num_regs = l->X_add_number >> 16;
+
+      resolve_expression (r);
+      if (num_regs)
 	{
-	  num_regs = (l->X_add_number >> 16);
-	  if ((unsigned) r->X_add_number >= num_regs)
+	  /* Left side is a .rotX-allocated register.  */
+	  if (r->X_op != O_constant)
 	    {
-	      if (!num_regs)
-		as_bad ("No current frame");
-	      else
-		as_bad ("Index out of range 0..%u", num_regs - 1);
+	      as_bad ("Rotating register index must be a non-negative constant");
+	      r->X_add_number = 0;
+	    }
+	  else if ((valueT) r->X_add_number >= num_regs)
+	    {
+	      as_bad ("Index out of range 0..%u", num_regs - 1);
 	      r->X_add_number = 0;
 	    }
 	  l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number;
 	  return 1;
 	}
-      else if (l->X_op == O_register && r->X_op == O_register)
+      else if (l->X_add_number >= IND_CPUID && l->X_add_number <= IND_RR)
 	{
-	  if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR
-	      || l->X_add_number == IND_MEM)
+	  if (r->X_op != O_register
+	      || r->X_add_number < REG_GR
+	      || r->X_add_number > REG_GR + 127)
 	    {
-	      as_bad ("Indirect register set name expected");
-	      l->X_add_number = IND_CPUID;
+	      as_bad ("Indirect register index must be a general register");
+	      r->X_add_number = REG_GR;
 	    }
 	  l->X_op = O_index;
-	  l->X_op_symbol = md.regsym[l->X_add_number];
+	  l->X_op_symbol = md.indregsym[l->X_add_number - IND_CPUID];
 	  l->X_add_number = r->X_add_number;
 	  return 1;
 	}
     }
-  return 0;
+  as_bad ("Index can only be applied to rotating or indirect registers");
+  /* Fall back to some register use of which has as little as possible
+     side effects, to minimize subsequent error messages.  */
+  l->X_op = O_register;
+  l->X_add_number = REG_GR + 3;
+  return 1;
 }
 
 int
-ia64_parse_name (name, e)
+ia64_parse_name (name, e, nextcharP)
      char *name;
      expressionS *e;
+     char *nextcharP;
 {
   struct const_desc *cdesc;
   struct dynreg *dr = 0;
-  unsigned int regnum;
+  unsigned int idx;
   struct symbol *sym;
   char *end;
 
+  if (*name == '@')
+    {
+      enum pseudo_type pseudo_type = PSEUDO_FUNC_NONE;
+
+      /* Find what relocation pseudo-function we're dealing with.  */
+      for (idx = 0; idx < NELEMS (pseudo_func); ++idx)
+	if (pseudo_func[idx].name
+	    && pseudo_func[idx].name[0] == name[1]
+	    && strcmp (pseudo_func[idx].name + 1, name + 2) == 0)
+	  {
+	    pseudo_type = pseudo_func[idx].type;
+	    break;
+	  }
+      switch (pseudo_type)
+	{
+	case PSEUDO_FUNC_RELOC:
+	  end = input_line_pointer;
+	  if (*nextcharP != '(')
+	    {
+	      as_bad ("Expected '('");
+	      break;
+	    }
+	  /* Skip '('.  */
+	  ++input_line_pointer;
+	  expression (e);
+	  if (*input_line_pointer != ')')
+	    {
+	      as_bad ("Missing ')'");
+	      goto done;
+	    }
+	  /* Skip ')'.  */
+	  ++input_line_pointer;
+	  if (e->X_op != O_symbol)
+	    {
+	      if (e->X_op != O_pseudo_fixup)
+		{
+		  as_bad ("Not a symbolic expression");
+		  goto done;
+		}
+	      if (idx != FUNC_LT_RELATIVE)
+		{
+		  as_bad ("Illegal combination of relocation functions");
+		  goto done;
+		}
+	      switch (S_GET_VALUE (e->X_op_symbol))
+		{
+		case FUNC_FPTR_RELATIVE:
+		  idx = FUNC_LT_FPTR_RELATIVE; break;
+		case FUNC_DTP_MODULE:
+		  idx = FUNC_LT_DTP_MODULE; break;
+		case FUNC_DTP_RELATIVE:
+		  idx = FUNC_LT_DTP_RELATIVE; break;
+		case FUNC_TP_RELATIVE:
+		  idx = FUNC_LT_TP_RELATIVE; break;
+		default:
+		  as_bad ("Illegal combination of relocation functions");
+		  goto done;
+		}
+	    }
+	  /* Make sure gas doesn't get rid of local symbols that are used
+	     in relocs.  */
+	  e->X_op = O_pseudo_fixup;
+	  e->X_op_symbol = pseudo_func[idx].u.sym;
+	done:
+	  *nextcharP = *input_line_pointer;
+	  break;
+
+	case PSEUDO_FUNC_CONST:
+	  e->X_op = O_constant;
+	  e->X_add_number = pseudo_func[idx].u.ival;
+	  break;
+
+	case PSEUDO_FUNC_REG:
+	  e->X_op = O_register;
+	  e->X_add_number = pseudo_func[idx].u.ival;
+	  break;
+
+	default:
+	  return 0;
+	}
+      return 1;
+    }
+
   /* first see if NAME is a known register name:  */
   sym = hash_find (md.reg_hash, name);
   if (sym)
@@ -7291,13 +8143,14 @@ ia64_parse_name (name, e)
     }
 
   /* check for inN, locN, or outN:  */
+  idx = 0;
   switch (name[0])
     {
     case 'i':
       if (name[1] == 'n' && ISDIGIT (name[2]))
 	{
 	  dr = &md.in;
-	  name += 2;
+	  idx = 2;
 	}
       break;
 
@@ -7305,7 +8158,7 @@ ia64_parse_name (name, e)
       if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3]))
 	{
 	  dr = &md.loc;
-	  name += 3;
+	  idx = 3;
 	}
       break;
 
@@ -7313,7 +8166,7 @@ ia64_parse_name (name, e)
       if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3]))
 	{
 	  dr = &md.out;
-	  name += 3;
+	  idx = 3;
 	}
       break;
 
@@ -7321,13 +8174,16 @@ ia64_parse_name (name, e)
       break;
     }
 
-  if (dr)
+  /* Ignore register numbers with leading zeroes, except zero itself.  */
+  if (dr && (name[idx] != '0' || name[idx + 1] == '\0'))
     {
+      unsigned long regnum;
+
       /* The name is inN, locN, or outN; parse the register number.  */
-      regnum = strtoul (name, &end, 10);
-      if (end > name && *end == '\0')
+      regnum = strtoul (name + idx, &end, 10);
+      if (end > name + idx && *end == '\0' && regnum < 96)
 	{
-	  if ((unsigned) regnum >= dr->num_regs)
+	  if (regnum >= dr->num_regs)
 	    {
 	      if (!dr->num_regs)
 		as_bad ("No current frame");
@@ -7342,6 +8198,9 @@ ia64_parse_name (name, e)
 	}
     }
 
+  end = alloca (strlen (name) + 1);
+  strcpy (end, name);
+  name = ia64_canonicalize_symbol_name (end);
   if ((dr = hash_find (md.dynreg_hash, name)))
     {
       /* We've got ourselves the name of a rotating register set.
@@ -7361,9 +8220,18 @@ char *
 ia64_canonicalize_symbol_name (name)
      char *name;
 {
-  size_t len = strlen (name);
-  if (len > 1 && name[len - 1] == '#')
-    name[len - 1] = '\0';
+  size_t len = strlen (name), full = len;
+
+  while (len > 0 && name[len - 1] == '#')
+    --len;
+  if (len <= 0)
+    {
+      if (full > 0)
+	as_bad ("Standalone `#' is illegal");
+    }
+  else if (len < full - 1)
+    as_warn ("Redundant `#' suffix operators");
+  name[len] = '\0';
   return name;
 }
 
@@ -7474,6 +8342,8 @@ depends_on (depind, idesc)
    IC:rse-writers.
    15+16) Represents reserved instructions, which the assembler does not
    generate.
+   17) CR[TPR] has a RAW dependency only between mov-to-CR-TPR and
+   mov-to-PSR-l or ssm instructions that set PSR.i, PSR.pp or PSR.up.
 
    Memory resources (i.e. locations in memory) are *not* marked or tracked by
    this code; there are no dependency violations based on memory access.
@@ -7509,9 +8379,15 @@ specify_resource (dep, idesc, type, specs, note, path)
   tmpl.qp_regno = CURR_SLOT.qp_regno;
   tmpl.link_to_qp_branch = 1;
   tmpl.mem_offset.hint = 0;
+  tmpl.mem_offset.offset = 0;
+  tmpl.mem_offset.base = 0;
   tmpl.specific = 1;
-  tmpl.index = 0;
+  tmpl.index = -1;
   tmpl.cmp_type = CMP_NONE;
+  tmpl.depind = 0;
+  tmpl.file = NULL;
+  tmpl.line = 0;
+  tmpl.path = 0;
 
 #define UNHANDLED \
 as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \
@@ -8556,8 +9432,9 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
       break;
 
     case IA64_RS_CRX:
-      /* Handle all CR[REG] resources */
-      if (note == 0 || note == 1)
+      /* Handle all CR[REG] resources.
+	 ??? FIXME: The rule 17 isn't really handled correctly.   */
+      if (note == 0 || note == 1 || note == 17)
 	{
 	  if (idesc->operands[!rsrc_write] == IA64_OPND_CR3)
 	    {
@@ -8753,8 +9630,7 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
 	      if (idesc->operands[0] == IA64_OPND_AR3
 		  && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE)
 		{
-		  specs[count] = tmpl;
-		  specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */
+		  specs[count++] = tmpl;
 		}
 	    }
 	  else
@@ -9208,6 +10084,7 @@ note_register_values (idesc)
   else if (idesc->operands[0] == IA64_OPND_R1
 	   && (idesc->operands[1] == IA64_OPND_IMM22
 	       || idesc->operands[1] == IA64_OPND_IMMU64)
+	   && CURR_SLOT.opnd[1].X_op == O_constant
 	   && (strcmp (idesc->name, "mov") == 0
 	       || strcmp (idesc->name, "movl") == 0))
     {
@@ -9225,6 +10102,30 @@ note_register_values (idesc)
 	    }
 	}
     }
+  /* Look for dep.z imm insns.  */
+  else if (idesc->operands[0] == IA64_OPND_R1
+	   && idesc->operands[1] == IA64_OPND_IMM8
+	   && strcmp (idesc->name, "dep.z") == 0)
+    {
+      int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR;
+      if (regno > 0 && regno < NELEMS (gr_values))
+	{
+	  valueT value = CURR_SLOT.opnd[1].X_add_number;
+
+	  if (CURR_SLOT.opnd[3].X_add_number < 64)
+	    value &= ((valueT)1 << CURR_SLOT.opnd[3].X_add_number) - 1;
+	  value <<= CURR_SLOT.opnd[2].X_add_number;
+	  gr_values[regno].known = 1;
+	  gr_values[regno].value = value;
+	  gr_values[regno].path = md.path;
+	  if (md.debug_dv)
+	    {
+	      fprintf (stderr, "  Know gr%d = ", regno);
+	      fprintf_vma (stderr, gr_values[regno].value);
+	      fputs ("\n", stderr);
+	    }
+	}
+    }
   else
     {
       clear_qp_mutex (qp_changemask);
@@ -9330,10 +10231,6 @@ resources_match (rs, idesc, note, qp_regno, path)
       else if (specs[count].index == rs->index)
 	return 1;
     }
-#if 0
-  if (md.debug_dv)
-    fprintf (stderr, "  No %s conflicts\n", rs->dependency->name);
-#endif
 
   return 0;
 }
@@ -9449,7 +10346,7 @@ print_dependency (action, depind)
       fprintf (stderr, "  %s %s '%s'",
 	       action, dv_mode[(regdeps[depind].dependency)->mode],
 	       (regdeps[depind].dependency)->name);
-      if (regdeps[depind].specific && regdeps[depind].index != 0)
+      if (regdeps[depind].specific && regdeps[depind].index >= 0)
 	fprintf (stderr, " (%d)", regdeps[depind].index);
       if (regdeps[depind].mem_offset.hint)
 	{
@@ -9513,17 +10410,16 @@ remove_marked_resource (rs)
 	insn_group_break (1, 0, 0);
       if (rs->insn_srlz < STATE_SRLZ)
 	{
-	  int oldqp = CURR_SLOT.qp_regno;
-	  struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+	  struct slot oldslot = CURR_SLOT;
 	  /* Manually jam a srlz.i insn into the stream */
-	  CURR_SLOT.qp_regno = 0;
+	  memset (&CURR_SLOT, 0, sizeof (CURR_SLOT));
+	  CURR_SLOT.user_template = -1;
 	  CURR_SLOT.idesc = ia64_find_opcode ("srlz.i");
 	  instruction_serialization ();
 	  md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
 	  if (++md.num_slots_in_use >= NUM_SLOTS)
 	    emit_one_bundle ();
-	  CURR_SLOT.qp_regno = oldqp;
-	  CURR_SLOT.idesc = oldidesc;
+	  CURR_SLOT = oldslot;
 	}
       insn_group_break (1, 0, 0);
       break;
@@ -9536,17 +10432,16 @@ remove_marked_resource (rs)
       if (rs->data_srlz < STATE_STOP)
 	insn_group_break (1, 0, 0);
       {
-	int oldqp = CURR_SLOT.qp_regno;
-	struct ia64_opcode *oldidesc = CURR_SLOT.idesc;
+	struct slot oldslot = CURR_SLOT;
 	/* Manually jam a srlz.d insn into the stream */
-	CURR_SLOT.qp_regno = 0;
+	memset (&CURR_SLOT, 0, sizeof (CURR_SLOT));
+	CURR_SLOT.user_template = -1;
 	CURR_SLOT.idesc = ia64_find_opcode ("srlz.d");
 	data_serialization ();
 	md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS;
 	if (++md.num_slots_in_use >= NUM_SLOTS)
 	  emit_one_bundle ();
-	CURR_SLOT.qp_regno = oldqp;
-	CURR_SLOT.idesc = oldidesc;
+	CURR_SLOT = oldslot;
       }
       break;
     case IA64_DVS_IMPLIED:
@@ -9651,7 +10546,7 @@ check_dependencies (idesc)
 	      if (path != 0)
 		sprintf (pathmsg, " when entry is at label '%s'",
 			 md.entry_labels[path - 1]);
-	      if (rs->specific && rs->index != 0)
+	      if (matchtype == 1 && rs->index >= 0)
 		sprintf (indexmsg, ", specific resource number is %d",
 			 rs->index);
 	      sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s",
@@ -9738,12 +10633,6 @@ mark_resources (idesc)
 
       count = specify_resource (dep, idesc, DV_REG, specs, note, md.path);
 
-#if 0
-      if (md.debug_dv && !count)
-	fprintf (stderr, "  No %s %s usage found (path %d)\n",
-		 dv_mode[dep->mode], dep->name, md.path);
-#endif
-
       while (count-- > 0)
 	{
 	  mark_resource (idesc, dep, &specs[count],
@@ -9960,9 +10849,6 @@ md_assemble (str)
 	    mnemonic = "adds";
 	  ia64_free_opcode (idesc);
 	  idesc = ia64_find_opcode (mnemonic);
-#if 0
-	  know (!idesc->next);
-#endif
 	}
       else if (strcmp (idesc->name, "mov") == 0)
 	{
@@ -9977,17 +10863,67 @@ md_assemble (str)
 	    rop = 1;
 	  else
 	    abort ();
-	  if (CURR_SLOT.opnd[rop].X_op == O_register
-	      && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
-	    mnemonic = "mov.i";
+	  if (CURR_SLOT.opnd[rop].X_op == O_register)
+	    {
+	      if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
+		mnemonic = "mov.i";
+	      else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_number))
+		mnemonic = "mov.m";
+	      else
+		rop = -1;
+	    }
 	  else
-	    mnemonic = "mov.m";
-	  ia64_free_opcode (idesc);
-	  idesc = ia64_find_opcode (mnemonic);
-	  while (idesc != NULL
-		 && (idesc->operands[0] != opnd1
-		     || idesc->operands[1] != opnd2))
-	    idesc = get_next_opcode (idesc);
+	    abort ();
+	  if (rop >= 0)
+	    {
+	      ia64_free_opcode (idesc);
+	      idesc = ia64_find_opcode (mnemonic);
+	      while (idesc != NULL
+		     && (idesc->operands[0] != opnd1
+			 || idesc->operands[1] != opnd2))
+		idesc = get_next_opcode (idesc);
+	    }
+	}
+    }
+  else if (strcmp (idesc->name, "mov.i") == 0
+	   || strcmp (idesc->name, "mov.m") == 0)
+    {
+      enum ia64_opnd opnd1, opnd2;
+      int rop;
+      
+      opnd1 = idesc->operands[0];
+      opnd2 = idesc->operands[1];
+      if (opnd1 == IA64_OPND_AR3)
+	rop = 0;
+      else if (opnd2 == IA64_OPND_AR3)
+	rop = 1;
+      else
+	abort ();
+      if (CURR_SLOT.opnd[rop].X_op == O_register)
+	{
+	  char unit = 'a';
+	  if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number))
+	    unit = 'i';
+	  else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_number))
+	    unit = 'm';
+	  if (unit != 'a' && unit != idesc->name [4])
+	    as_bad ("AR %d can only be accessed by %c-unit",
+		    (int) (CURR_SLOT.opnd[rop].X_add_number - REG_AR),
+		    TOUPPER (unit));
+	}
+    }
+  else if (strcmp (idesc->name, "hint.b") == 0)
+    {
+      switch (md.hint_b)
+	{
+	case hint_b_ok:
+	  break;
+	case hint_b_warning:
+	  as_warn ("hint.b may be treated as nop");
+	  break;
+	case hint_b_error:
+	  as_bad ("hint.b shouldn't be used");
+	  break;
 	}
     }
 
@@ -10035,12 +10971,26 @@ md_assemble (str)
   as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line);
   dwarf2_where (&CURR_SLOT.debug_line);
 
-  /* Add unwind entry, if there is one.  */
+  /* Add unwind entries, if there are any.  */
   if (unwind.current_entry)
     {
       CURR_SLOT.unwind_record = unwind.current_entry;
       unwind.current_entry = NULL;
     }
+  if (unwind.pending_saves)
+    {
+      if (unwind.pending_saves->next)
+	{
+	  /* Attach the next pending save to the next slot so that its
+	     slot number will get set correctly.  */
+	  add_unwind_entry (unwind.pending_saves->next, NOT_A_CHAR);
+	  unwind.pending_saves = &unwind.pending_saves->next->r.record.p;
+	}
+      else
+	unwind.pending_saves = NULL;
+    }
+  if (unwind.proc_pending.sym && S_IS_DEFINED (unwind.proc_pending.sym))
+    unwind.insn = 1;
 
   /* Check for dependency violations.  */
   if (md.detect_dv)
@@ -10077,110 +11027,25 @@ void
 md_operand (e)
      expressionS *e;
 {
-  enum pseudo_type pseudo_type;
-  const char *name;
-  size_t len;
-  int ch, i;
-
   switch (*input_line_pointer)
     {
-    case '@':
-      /* Find what relocation pseudo-function we're dealing with.  */
-      pseudo_type = 0;
-      ch = *++input_line_pointer;
-      for (i = 0; i < NELEMS (pseudo_func); ++i)
-	if (pseudo_func[i].name && pseudo_func[i].name[0] == ch)
-	  {
-	    len = strlen (pseudo_func[i].name);
-	    if (strncmp (pseudo_func[i].name + 1,
-			 input_line_pointer + 1, len - 1) == 0
-		&& !is_part_of_name (input_line_pointer[len]))
-	      {
-		input_line_pointer += len;
-		pseudo_type = pseudo_func[i].type;
-		break;
-	      }
-	  }
-      switch (pseudo_type)
-	{
-	case PSEUDO_FUNC_RELOC:
-	  SKIP_WHITESPACE ();
-	  if (*input_line_pointer != '(')
-	    {
-	      as_bad ("Expected '('");
-	      goto err;
-	    }
-	  /* Skip '('.  */
-	  ++input_line_pointer;
-	  expression (e);
-	  if (*input_line_pointer++ != ')')
-	    {
-	      as_bad ("Missing ')'");
-	      goto err;
-	    }
-	  if (e->X_op != O_symbol)
-	    {
-	      if (e->X_op != O_pseudo_fixup)
-		{
-		  as_bad ("Not a symbolic expression");
-		  goto err;
-		}
-	      if (i != FUNC_LT_RELATIVE)
-		{
-		  as_bad ("Illegal combination of relocation functions");
-		  goto err;
-		}
-	      switch (S_GET_VALUE (e->X_op_symbol))
-		{
-		case FUNC_FPTR_RELATIVE:
-		  i = FUNC_LT_FPTR_RELATIVE; break;
-		case FUNC_DTP_MODULE:
-		  i = FUNC_LT_DTP_MODULE; break;
-		case FUNC_DTP_RELATIVE:
-		  i = FUNC_LT_DTP_RELATIVE; break;
-		case FUNC_TP_RELATIVE:
-		  i = FUNC_LT_TP_RELATIVE; break;
-		default:
-		  as_bad ("Illegal combination of relocation functions");
-		  goto err;
-		}
-	    }
-	  /* Make sure gas doesn't get rid of local symbols that are used
-	     in relocs.  */
-	  e->X_op = O_pseudo_fixup;
-	  e->X_op_symbol = pseudo_func[i].u.sym;
-	  break;
-
-	case PSEUDO_FUNC_CONST:
-	  e->X_op = O_constant;
-	  e->X_add_number = pseudo_func[i].u.ival;
-	  break;
-
-	case PSEUDO_FUNC_REG:
-	  e->X_op = O_register;
-	  e->X_add_number = pseudo_func[i].u.ival;
-	  break;
-
-	default:
-	  name = input_line_pointer - 1;
-	  get_symbol_end ();
-	  as_bad ("Unknown pseudo function `%s'", name);
-	  goto err;
-	}
-      break;
-
     case '[':
       ++input_line_pointer;
-      expression (e);
+      expression_and_evaluate (e);
       if (*input_line_pointer != ']')
 	{
-	  as_bad ("Closing bracket misssing");
+	  as_bad ("Closing bracket missing");
 	  goto err;
 	}
       else
 	{
-	  if (e->X_op != O_register)
-	    as_bad ("Register expected as index");
+	  if (e->X_op != O_register
+	      || e->X_add_number < REG_GR
+	      || e->X_add_number > REG_GR + 127)
+	    {
+	      as_bad ("Index must be a general register");
+	      e->X_add_number = REG_GR;
+	    }
 
 	  ++input_line_pointer;
 	  e->X_op = O_index;
@@ -10205,7 +11070,7 @@ ia64_fix_adjustable (fix)
      fixS *fix;
 {
   /* Prevent all adjustments to global symbols */
-  if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
+  if (S_IS_EXTERNAL (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy))
     return 0;
 
   switch (fix->fx_r_type)
@@ -10366,7 +11231,7 @@ ia64_cons_fix_new (f, where, nbytes, exp)
   fix = fix_new_exp (f, where, nbytes, exp, 0, code);
   /* We need to store the byte order in effect in case we're going
      to fix an 8 or 16 bit relocation (for which there no real
-     relocs available).  See md_apply_fix3().  */
+     relocs available).  See md_apply_fix().  */
   fix->tc_fix_data.bigendian = target_big_endian;
 }
 
@@ -10380,6 +11245,7 @@ ia64_gen_real_reloc_type (sym, r_type)
      bfd_reloc_code_real_type r_type;
 {
   bfd_reloc_code_real_type new = 0;
+  const char *type = NULL, *suffix = "";
 
   if (sym == NULL)
     {
@@ -10396,7 +11262,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_FPTR32LSB; break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_FPTR64MSB; break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_FPTR64LSB; break;
-	default:			break;
+	default:			type = "FPTR"; break;
 	}
       break;
 
@@ -10409,7 +11275,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_GPREL32LSB; break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_GPREL64MSB; break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_GPREL64LSB; break;
-	default:			break;
+	default:			type = "GPREL"; break;
 	}
       break;
 
@@ -10418,7 +11284,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	{
 	case BFD_RELOC_IA64_IMM22:	new = BFD_RELOC_IA64_LTOFF22; break;
 	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_LTOFF64I; break;
-	default:			break;
+	default:			type = "LTOFF"; break;
 	}
       break;
 
@@ -10426,7 +11292,7 @@ ia64_gen_real_reloc_type (sym, r_type)
       switch (r_type)
 	{
 	case BFD_RELOC_IA64_IMM22:	new = BFD_RELOC_IA64_LTOFF22X; break;
-	default:			break;
+	default:			type = "LTOFF"; suffix = "X"; break;
 	}
       break;
 
@@ -10439,7 +11305,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_PCREL32LSB; break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_PCREL64MSB; break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_PCREL64LSB; break;
-	default:			break;
+	default:			type = "PCREL"; break;
 	}
       break;
 
@@ -10450,7 +11316,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_IMM64:	new = BFD_RELOC_IA64_PLTOFF64I; break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_PLTOFF64MSB;break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_PLTOFF64LSB;break;
-	default:			break;
+	default:			type = "PLTOFF"; break;
 	}
       break;
 
@@ -10461,7 +11327,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_SECREL32LSB;break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_SECREL64MSB;break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_SECREL64LSB;break;
-	default:			break;
+	default:			type = "SECREL"; break;
 	}
       break;
 
@@ -10472,7 +11338,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_SEGREL32LSB;break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_SEGREL64MSB;break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_SEGREL64LSB;break;
-	default:			break;
+	default:			type = "SEGREL"; break;
 	}
       break;
 
@@ -10483,7 +11349,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_DIR32LSB:	new = BFD_RELOC_IA64_LTV32LSB; break;
 	case BFD_RELOC_IA64_DIR64MSB:	new = BFD_RELOC_IA64_LTV64MSB; break;
 	case BFD_RELOC_IA64_DIR64LSB:	new = BFD_RELOC_IA64_LTV64LSB; break;
-	default:			break;
+	default:			type = "LTV"; break;
 	}
       break;
 
@@ -10494,22 +11360,28 @@ ia64_gen_real_reloc_type (sym, r_type)
 	  new = BFD_RELOC_IA64_LTOFF_FPTR22; break;
 	case BFD_RELOC_IA64_IMM64:
 	  new = BFD_RELOC_IA64_LTOFF_FPTR64I; break;
+	case BFD_RELOC_IA64_DIR32MSB:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR32MSB; break;
+	case BFD_RELOC_IA64_DIR32LSB:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR32LSB; break;
+	case BFD_RELOC_IA64_DIR64MSB:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:
+	  new = BFD_RELOC_IA64_LTOFF_FPTR64LSB; break;
 	default:
-	  break;
+	  type = "LTOFF_FPTR"; break;
 	}
       break;
 
     case FUNC_TP_RELATIVE:
       switch (r_type)
 	{
-	case BFD_RELOC_IA64_IMM14:
-	  new = BFD_RELOC_IA64_TPREL14; break;
-	case BFD_RELOC_IA64_IMM22:
-	  new = BFD_RELOC_IA64_TPREL22; break;
-	case BFD_RELOC_IA64_IMM64:
-	  new = BFD_RELOC_IA64_TPREL64I; break;
-	default:
-	  break;
+	case BFD_RELOC_IA64_IMM14:      new = BFD_RELOC_IA64_TPREL14; break;
+	case BFD_RELOC_IA64_IMM22:      new = BFD_RELOC_IA64_TPREL22; break;
+	case BFD_RELOC_IA64_IMM64:      new = BFD_RELOC_IA64_TPREL64I; break;
+	case BFD_RELOC_IA64_DIR64MSB:   new = BFD_RELOC_IA64_TPREL64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:   new = BFD_RELOC_IA64_TPREL64LSB; break;
+	default:                        type = "TPREL"; break;
 	}
       break;
 
@@ -10519,7 +11391,19 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_IMM22:
 	  new = BFD_RELOC_IA64_LTOFF_TPREL22; break;
 	default:
-	  break;
+	  type = "LTOFF_TPREL"; break;
+	}
+      break;
+
+    case FUNC_DTP_MODULE:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_DIR64MSB:
+	  new = BFD_RELOC_IA64_DTPMOD64MSB; break;
+	case BFD_RELOC_IA64_DIR64LSB:
+	  new = BFD_RELOC_IA64_DTPMOD64LSB; break;
+	default:
+	  type = "DTPMOD"; break;
 	}
       break;
 
@@ -10529,13 +11413,17 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_IMM22:
 	  new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break;
 	default:
-	  break;
+	  type = "LTOFF_DTPMOD"; break;
 	}
       break;
 
     case FUNC_DTP_RELATIVE:
       switch (r_type)
 	{
+	case BFD_RELOC_IA64_DIR32MSB:
+	  new = BFD_RELOC_IA64_DTPREL32MSB; break;
+	case BFD_RELOC_IA64_DIR32LSB:
+	  new = BFD_RELOC_IA64_DTPREL32LSB; break;
 	case BFD_RELOC_IA64_DIR64MSB:
 	  new = BFD_RELOC_IA64_DTPREL64MSB; break;
 	case BFD_RELOC_IA64_DIR64LSB:
@@ -10547,7 +11435,7 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_IMM64:
 	  new = BFD_RELOC_IA64_DTPREL64I; break;
 	default:
-	  break;
+	  type = "DTPREL"; break;
 	}
       break;
 
@@ -10557,22 +11445,49 @@ ia64_gen_real_reloc_type (sym, r_type)
 	case BFD_RELOC_IA64_IMM22:
 	  new = BFD_RELOC_IA64_LTOFF_DTPREL22; break;
 	default:
-	  break;
+	  type = "LTOFF_DTPREL"; break;
 	}
       break;
 
     case FUNC_IPLT_RELOC:
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_IPLTMSB:    return r_type;
+	case BFD_RELOC_IA64_IPLTLSB:    return r_type;
+	default:                        type = "IPLT"; break;
+	}
       break;
 
     default:
       abort ();
     }
 
-  /* Hmmmm.  Should this ever occur?  */
   if (new)
     return new;
   else
-    return r_type;
+    {
+      int width;
+
+      if (!type)
+	abort ();
+      switch (r_type)
+	{
+	case BFD_RELOC_IA64_DIR32MSB: width = 32; suffix = "MSB"; break;
+	case BFD_RELOC_IA64_DIR32LSB: width = 32; suffix = "LSB"; break;
+	case BFD_RELOC_IA64_DIR64MSB: width = 64; suffix = "MSB"; break;
+	case BFD_RELOC_IA64_DIR64LSB: width = 64; suffix = "LSB"; break;
+	case BFD_RELOC_UNUSED:        width = 13; break;
+	case BFD_RELOC_IA64_IMM14:    width = 14; break;
+	case BFD_RELOC_IA64_IMM22:    width = 22; break;
+	case BFD_RELOC_IA64_IMM64:    width = 64; suffix = "I"; break;
+	default:                      abort ();
+	}
+
+      /* This should be an error, but since previously there wasn't any
+	 diagnostic here, dont't make it fail because of this for now.  */
+      as_warn ("Cannot express %s%d%s relocation", type, width, suffix);
+      return r_type;
+    }
 }
 
 /* Here is where generate the appropriate reloc for pseudo relocation
@@ -10663,7 +11578,7 @@ fix_insn (fix, odesc, value)
    (if possible).  */
 
 void
-md_apply_fix3 (fix, valP, seg)
+md_apply_fix (fix, valP, seg)
      fixS *fix;
      valueT *valP;
      segT seg ATTRIBUTE_UNUSED;
@@ -10675,27 +11590,24 @@ md_apply_fix3 (fix, valP, seg)
 
   if (fix->fx_pcrel)
     {
-      switch (fix->fx_r_type)
-	{
-	case BFD_RELOC_IA64_DIR32MSB:
-	  fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
-	  break;
-
-	case BFD_RELOC_IA64_DIR32LSB:
-	  fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
-	  break;
-
-	case BFD_RELOC_IA64_DIR64MSB:
-	  fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
-	  break;
-
-	case BFD_RELOC_IA64_DIR64LSB:
-	  fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
-	  break;
-
-	default:
-	  break;
-	}
+    switch (fix->fx_r_type)
+      {
+      case BFD_RELOC_IA64_PCREL21B: break;
+      case BFD_RELOC_IA64_PCREL21BI: break;
+      case BFD_RELOC_IA64_PCREL21F: break;
+      case BFD_RELOC_IA64_PCREL21M: break;
+      case BFD_RELOC_IA64_PCREL60B: break;
+      case BFD_RELOC_IA64_PCREL22: break;
+      case BFD_RELOC_IA64_PCREL64I: break;
+      case BFD_RELOC_IA64_PCREL32MSB: break;
+      case BFD_RELOC_IA64_PCREL32LSB: break;
+      case BFD_RELOC_IA64_PCREL64MSB: break;
+      case BFD_RELOC_IA64_PCREL64LSB: break;
+      default:
+	fix->fx_r_type = ia64_gen_real_reloc_type (pseudo_func[FUNC_PC_RELATIVE].u.sym,
+					       fix->fx_r_type);
+	break;
+      }
     }
   if (fix->fx_addsy)
     {
@@ -10850,14 +11762,6 @@ void
 ia64_handle_align (fragp)
      fragS *fragp;
 {
-  /* Use mfi bundle of nops with no stop bits.  */
-  static const unsigned char le_nop[]
-    = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
-	0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
-  static const unsigned char le_nop_stop[]
-    = { 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
-	0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00};
-
   int bytes;
   char *p;
   const unsigned char *nop;
@@ -10934,6 +11838,9 @@ ia64_float_to_chars_littleendian (char *lit, LITTLENUM_TYPE *words,
 void
 ia64_elf_section_change_hook  (void)
 {
+  if (elf_section_type (now_seg) == SHT_IA_64_UNWIND
+      && elf_linked_to_section (now_seg) == NULL)
+    elf_linked_to_section (now_seg) = text_section;
   dot_byteorder (-1);
 }
 
@@ -10981,7 +11888,7 @@ dot_alias (int section)
   if (name == end_name)
     {
       as_bad (_("expected symbol name"));
-      discard_rest_of_line ();
+      ignore_rest_of_line ();
       return;
     }
 
@@ -10998,6 +11905,7 @@ dot_alias (int section)
 
   input_line_pointer++;
   *end_name = 0;
+  ia64_canonicalize_symbol_name (name);
 
   /* We call demand_copy_C_string to check if alias string is valid.
      There should be a closing `"' and no `\0' in the string.  */
diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h
index dcc2c299602d..c17494beb16b 100644
--- a/gas/config/tc-ia64.h
+++ b/gas/config/tc-ia64.h
@@ -1,5 +1,6 @@
 /* tc-ia64.h -- Header file for tc-ia64.c.
-   Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include "opcode/ia64.h"
 #include "elf/ia64.h"
@@ -74,10 +75,13 @@ extern const char *ia64_target_format PARAMS ((void));
 #define NEED_INDEX_OPERATOR		/* [ ] is index operator */
 
 #define QUOTES_IN_INSN			/* allow `string "foo;bar"' */
-#define LEX_AT		LEX_NAME	/* allow `@' inside name */
-#define LEX_QM		LEX_NAME	/* allow `?' inside name */
+#define LEX_AT		(LEX_NAME|LEX_BEGIN_NAME) /* allow `@' inside name */
+#define LEX_QM		(LEX_NAME|LEX_BEGIN_NAME) /* allow `?' inside name */
 #define LEX_HASH	LEX_END_NAME	/* allow `#' ending a name */
 
+extern const char ia64_symbol_chars[];
+#define tc_symbol_chars ia64_symbol_chars
+
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
 
 struct ia64_fix
@@ -94,7 +98,7 @@ extern void ia64_frob_label PARAMS((struct symbol *sym));
 extern int ia64_frob_symbol PARAMS((struct symbol *sym));
 #endif
 extern void ia64_flush_pending_output PARAMS((void));
-extern int ia64_parse_name (char *name, expressionS *e);
+extern int ia64_parse_name PARAMS((char *name, expressionS *e, char *nextP));
 extern int ia64_optimize_expr PARAMS((expressionS *l, operatorT op,
 				      expressionS *r));
 extern void ia64_cons_align PARAMS((int));
@@ -125,7 +129,7 @@ extern void ia64_convert_frag (fragS *);
 #define tc_frob_symbol(s,p)		p |= ia64_frob_symbol (s)
 #endif /* TE_HPUX */
 #define md_flush_pending_output()	ia64_flush_pending_output ()
-#define md_parse_name(s,e,c)		ia64_parse_name (s, e)
+#define md_parse_name(s,e,m,c)		ia64_parse_name (s, e, c)
 #define tc_canonicalize_symbol_name(s)	ia64_canonicalize_symbol_name (s)
 #define tc_canonicalize_section_name(s)	ia64_canonicalize_symbol_name (s)
 #define md_optimize_expr(l,o,r)		ia64_optimize_expr (l, o, r)
@@ -158,6 +162,14 @@ extern void ia64_convert_frag (fragS *);
 #define TC_FRAG_TYPE			int
 #define TC_FRAG_INIT(FRAGP)		do {(FRAGP)->tc_frag_data = 0;}while (0)
 
+/* Give an error if a frag containing code is not aligned to a 16 byte
+   boundary.  */
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code							\
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 15) != 0)	\
+     as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,			\
+		   _("instruction address is not a multiple of 16"));
+
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (15 + 16)
 
 #define WORKING_DOT_WORD	/* don't do broken word processing for now */
@@ -229,7 +241,7 @@ typedef struct unw_r_record
   struct
   {
     unsigned char *i;
-    unsigned long fr_mem;
+    unsigned int fr_mem;
     unsigned char gr_mem;
     unsigned char br_mem;
   } mask;
@@ -237,17 +249,22 @@ typedef struct unw_r_record
 
 typedef struct unw_p_record
 {
-  void *imask;
+  struct unw_rec_list *next;
   unsigned long t;
   unsigned long size;
-  unsigned long spoff;
-  unsigned long br;
-  unsigned long pspoff;
-  unsigned short gr;
-  unsigned short rmask;
-  unsigned short grmask;
-  unsigned long frmask;
-  unsigned short brmask;
+  union
+  {
+    unsigned long sp;
+    unsigned long psp;
+  } off;
+  union
+  {
+    unsigned short gr;
+    unsigned short br;
+  } r;
+  unsigned char grmask;
+  unsigned char brmask;
+  unsigned int frmask;
   unsigned char abi;
   unsigned char context;
 } unw_p_record;
@@ -262,10 +279,13 @@ typedef struct unw_b_record
 typedef struct unw_x_record
 {
   unsigned long t;
-  unsigned long spoff;
-  unsigned long pspoff;
+  union
+  {
+    unsigned long spoff;
+    unsigned long pspoff;
+    unsigned int reg;
+  } where;
   unsigned short reg;
-  unsigned short treg;
   unsigned short qp;
   unsigned short ab;	/* Value of the AB field..  */
   unsigned short xy;	/* Value of the XY field..  */
diff --git a/gas/config/tc-ip2k.c b/gas/config/tc-ip2k.c
index a57bc969f3b9..10e9e2f3fa20 100644
--- a/gas/config/tc-ip2k.c
+++ b/gas/config/tc-ip2k.c
@@ -1,5 +1,5 @@
 /* tc-ip2k.c -- Assembler for the Scenix IP2xxx.
-   Copyright (C) 2000, 2002, 2003 Free Software Foundation.
+   Copyright (C) 2000, 2002, 2003, 2005 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -57,8 +57,52 @@ const char line_separator_chars[] = "";
 const char EXP_CHARS[]            = "eE";
 const char FLT_CHARS[]            = "dD";
 
-static void ip2k_elf_section_text (int);
-static void ip2k_elf_section_rtn (int);
+/* Flag to detect when switching to code section where insn alignment is
+   implied.  */
+static int force_code_align = 0;
+
+/* Mach selected from command line.  */
+static int ip2k_mach = 0;
+static unsigned ip2k_mach_bitmask = 0;
+
+
+static void
+ip2k_elf_section_rtn (int i)
+{
+  obj_elf_section(i);
+
+  if (force_code_align)
+    {
+      /* The s_align_ptwo function expects that we are just after a .align
+	 directive and it will either try and read the align value or stop
+	 if end of line so we must fake it out so it thinks we are at the
+	 end of the line.  */
+      char *old_input_line_pointer = input_line_pointer;
+      input_line_pointer = "\n";
+      s_align_ptwo (1);
+      force_code_align = 0;
+      /* Restore.  */
+      input_line_pointer = old_input_line_pointer;
+    }
+}
+
+static void
+ip2k_elf_section_text (int i)
+{
+  char *old_input_line_pointer;
+  obj_elf_text(i);
+
+  /* the s_align_ptwo function expects that we are just after a .align
+     directive and it will either try and read the align value or stop if
+     end of line so we must fake it out so it thinks we are at the end of
+     the line.  */
+  old_input_line_pointer = input_line_pointer;
+  input_line_pointer = "\n";
+  s_align_ptwo (1);
+  force_code_align = 0;
+  /* Restore.  */
+  input_line_pointer = old_input_line_pointer;
+}
 
 /* The target specific pseudo-ops which we support.  */
 const pseudo_typeS md_pseudo_table[] =
@@ -70,8 +114,11 @@ const pseudo_typeS md_pseudo_table[] =
 
 
 
-#define OPTION_CPU_IP2022    (OPTION_MD_BASE)
-#define OPTION_CPU_IP2022EXT (OPTION_MD_BASE+1)
+enum options
+{
+  OPTION_CPU_IP2022 = OPTION_MD_BASE,
+  OPTION_CPU_IP2022EXT
+};
 
 struct option md_longopts[] = 
 {
@@ -83,18 +130,8 @@ size_t md_longopts_size = sizeof (md_longopts);
 
 const char * md_shortopts = "";
 
-/* Flag to detect when switching to code section where insn alignment is
-   implied.  */
-static int force_code_align = 0;
-
-/* Mach selected from command line.  */
-int ip2k_mach = 0;
-unsigned ip2k_mach_bitmask = 0;
-
 int
-md_parse_option (c, arg)
-    int c ATTRIBUTE_UNUSED;
-    char * arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -115,10 +152,8 @@ md_parse_option (c, arg)
   return 1;
 }
 
-
 void
-md_show_usage (stream)
-    FILE * stream;
+md_show_usage (FILE * stream)
 {
   fprintf (stream, _("IP2K specific command line options:\n"));
   fprintf (stream, _("  -mip2022               restrict to IP2022 insns \n"));
@@ -127,7 +162,7 @@ md_show_usage (stream)
 
 
 void
-md_begin ()
+md_begin (void)
 {
   /* Initialize the `cgen' interface.  */
   
@@ -148,8 +183,7 @@ md_begin ()
 
 
 void
-md_assemble (str)
-     char * str;
+md_assemble (char * str)
 {
   ip2k_insn insn;
   char * errmsg;
@@ -173,7 +207,7 @@ md_assemble (str)
        the PCL (pc + 2) >> 1 is odd or even.  */
     {
       enum cgen_parse_operand_result result_type;
-      long value;
+      bfd_vma value;
       const char *curpc_plus_2 = ".+2";
       const char *err;
 
@@ -194,9 +228,7 @@ md_assemble (str)
 }
 
 valueT
-md_section_align (segment, size)
-     segT   segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
 
@@ -205,16 +237,14 @@ md_section_align (segment, size)
 
 
 symbolS *
-md_undefined_symbol (name)
-    char * name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 {
     return 0;
 }
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS * fragP ATTRIBUTE_UNUSED;
-     segT    segment ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+			       segT    segment ATTRIBUTE_UNUSED)
 {
   as_fatal (_("md_estimate_size_before_relax\n"));
   return 1;
@@ -229,10 +259,9 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-    bfd   * abfd  ATTRIBUTE_UNUSED;
-    segT    sec   ATTRIBUTE_UNUSED;
-    fragS * fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd   * abfd  ATTRIBUTE_UNUSED,
+		 segT    sec   ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
 {
 }
 
@@ -240,8 +269,7 @@ md_convert_frag (abfd, sec, fragP)
 /* Functions concerning relocs.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   as_fatal (_("md_pcrel_from\n"));
 
@@ -255,10 +283,9 @@ md_pcrel_from (fixP)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *    insn     ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND * operand;
-     fixS *               fixP     ATTRIBUTE_UNUSED;
+md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP     ATTRIBUTE_UNUSED)
 {
   bfd_reloc_code_real_type result;
 
@@ -300,10 +327,7 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+md_number_to_chars (char * buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
@@ -317,10 +341,7 @@ md_number_to_chars (buf, val, n)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
+md_atof (int type, char * litP, int *  sizeP)
 {
   int              prec;
   LITTLENUM_TYPE   words [MAX_LITTLENUMS];
@@ -374,8 +395,7 @@ md_atof (type, litP, sizeP)
    the instruction it will be eventually encoded within.  */
 
 int
-ip2k_force_relocation (fix)
-     fixS * fix;
+ip2k_force_relocation (fixS * fix)
 {
   switch (fix->fx_r_type)
     {
@@ -411,16 +431,13 @@ ip2k_force_relocation (fix)
 }
 
 void
-ip2k_apply_fix3 (fixP, valueP, seg)
-     fixS *fixP;
-     valueT *valueP;
-     segT seg;
+ip2k_apply_fix (fixS *fixP, valueT *valueP, segT seg)
 {
   if (fixP->fx_r_type == BFD_RELOC_IP2K_TEXT
       && ! fixP->fx_addsy
       && ! fixP->fx_subsy)
     {
-      *valueP = ((int)(*valueP)) / 2;
+      *valueP = ((int)(* valueP)) / 2;
       fixP->fx_r_type = BFD_RELOC_16;
     }
   else if (fixP->fx_r_type == BFD_RELOC_UNUSED + IP2K_OPERAND_FR)
@@ -428,7 +445,7 @@ ip2k_apply_fix3 (fixP, valueP, seg)
       /* Must be careful when we are fixing up an FR.  We could be
 	 fixing up an offset to (SP) or (DP) in which case we don't
 	 want to step on the top 2 bits of the FR operand.  The
-	 gas_cgen_md_apply_fix3 doesn't know any better and overwrites
+	 gas_cgen_md_apply_fix doesn't know any better and overwrites
 	 the entire operand.  We counter this by adding the bits
 	 to the new value.  */
       char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
@@ -436,20 +453,19 @@ ip2k_apply_fix3 (fixP, valueP, seg)
       /* Canonical name, since used a lot.  */
       CGEN_CPU_DESC cd = gas_cgen_cpu_desc;
       CGEN_INSN_INT insn_value
-	= cgen_get_insn_value (cd, where,
+	= cgen_get_insn_value (cd, (unsigned char *) where,
 			       CGEN_INSN_BITSIZE (fixP->fx_cgen.insn));
       /* Preserve (DP) or (SP) specification.  */
       *valueP += (insn_value & 0x180);
     }
 
-  gas_cgen_md_apply_fix3 (fixP, valueP, seg);
+  gas_cgen_md_apply_fix (fixP, valueP, seg);
 }
 
 int
-ip2k_elf_section_flags (flags, attr, type)
-     int flags;
-     int attr ATTRIBUTE_UNUSED;
-     int type ATTRIBUTE_UNUSED;
+ip2k_elf_section_flags (int flags,
+			int attr ATTRIBUTE_UNUSED,
+			int type ATTRIBUTE_UNUSED)
 {
   /* This is used to detect when the section changes to an executable section.
      This function is called by the elf section processing.  When we note an
@@ -461,40 +477,3 @@ ip2k_elf_section_flags (flags, attr, type)
   return flags;
 }
 
-static void
-ip2k_elf_section_rtn (int i)
-{
-  obj_elf_section(i);
-
-  if (force_code_align)
-    {
-      /* The s_align_ptwo function expects that we are just after a .align
-	 directive and it will either try and read the align value or stop
-	 if end of line so we must fake it out so it thinks we are at the
-	 end of the line.  */
-      char *old_input_line_pointer = input_line_pointer;
-      input_line_pointer = "\n";
-      s_align_ptwo (1);
-      force_code_align = 0;
-      /* Restore.  */
-      input_line_pointer = old_input_line_pointer;
-    }
-}
-
-static void
-ip2k_elf_section_text (int i)
-{
-  char *old_input_line_pointer;
-  obj_elf_text(i);
-
-  /* the s_align_ptwo function expects that we are just after a .align
-     directive and it will either try and read the align value or stop if
-     end of line so we must fake it out so it thinks we are at the end of
-     the line.  */
-  old_input_line_pointer = input_line_pointer;
-  input_line_pointer = "\n";
-  s_align_ptwo (1);
-  force_code_align = 0;
-  /* Restore.  */
-  input_line_pointer = old_input_line_pointer;
-}
diff --git a/gas/config/tc-ip2k.h b/gas/config/tc-ip2k.h
index 3ce0f5b031d6..e26e9013bb0a 100644
--- a/gas/config/tc-ip2k.h
+++ b/gas/config/tc-ip2k.h
@@ -1,5 +1,5 @@
 /* tc-ip2k.h -- Header file for tc-ip2k.c.
-   Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 2000, 2002, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,16 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_IP2K
 
-#ifndef BFD_ASSEMBLER
-/* Leading space so will compile with cc.  */
- #error IP2K support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "IP2xxx GAS "
 
 /* The target BFD architecture.  */
@@ -47,10 +42,10 @@
 #define LITERAL_PREFIXPERCENT_BIN
 #define DOUBLESLASH_LINE_COMMENTS
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define md_apply_fix3 ip2k_apply_fix3
+#define md_apply_fix ip2k_apply_fix
 
 #define TC_HANDLES_FX_DONE
 
@@ -59,12 +54,12 @@
 #define EXTERN_FORCE_RELOC 0
 
 #define TC_FORCE_RELOCATION(FIX) ip2k_force_relocation (FIX)
-extern int ip2k_force_relocation PARAMS ((struct fix *));
+extern int ip2k_force_relocation (struct fix *);
 
 #define tc_gen_reloc gas_cgen_tc_gen_reloc
 
 #define md_elf_section_flags ip2k_elf_section_flags
-extern int ip2k_elf_section_flags PARAMS ((int, int, int));
+extern int ip2k_elf_section_flags (int, int, int);
 
 #define md_operand(x) gas_cgen_md_operand (x)
-extern void gas_cgen_md_operand PARAMS ((expressionS *));
+extern void gas_cgen_md_operand (expressionS *);
diff --git a/gas/config/tc-iq2000.c b/gas/config/tc-iq2000.c
index 9f591d39a27e..0d689c09a219 100644
--- a/gas/config/tc-iq2000.c
+++ b/gas/config/tc-iq2000.c
@@ -1,5 +1,5 @@
 /* tc-iq2000.c -- Assembler for the Sitera IQ2000.
-   Copyright (C) 2003, 2004 Free Software Foundation.
+   Copyright (C) 2003, 2004, 2005 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,13 +15,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
 #include "safe-ctype.h"
-#include "subsegs.h"     
+#include "subsegs.h"
 #include "symcat.h"
 #include "opcodes/iq2000-desc.h"
 #include "opcodes/iq2000-opc.h"
@@ -55,23 +55,23 @@ typedef struct
 iq2000_insn;
 
 const char comment_chars[]        = "#";
-const char line_comment_chars[]   = "";
-const char line_separator_chars[] = ";"; 
+const char line_comment_chars[]   = "#";
+const char line_separator_chars[] = ";";
 const char EXP_CHARS[]            = "eE";
 const char FLT_CHARS[]            = "dD";
 
-/* Default machine */
-
+/* Default machine.  */
 #define DEFAULT_MACHINE bfd_mach_iq2000
 #define DEFAULT_FLAGS	EF_IQ2000_CPU_IQ2000
 
 static unsigned long iq2000_mach = bfd_mach_iq2000;
 static int cpu_mach = (1 << MACH_IQ2000);
 
-/* Flags to set in the elf header */
+/* Flags to set in the elf header.  */
 static flagword iq2000_flags = DEFAULT_FLAGS;
 
-typedef struct proc {
+typedef struct proc
+{
   symbolS *isym;
   unsigned long reg_mask;
   unsigned long reg_offset;
@@ -86,35 +86,6 @@ static procS cur_proc;
 static procS *cur_proc_ptr;
 static int numprocs;
 
-static void s_change_sec PARAMS ((int));
-static void s_iq2000_set PARAMS ((int));
-static void s_iq2000_mask PARAMS ((int));
-static void s_iq2000_frame PARAMS ((int));
-static void s_iq2000_ent PARAMS ((int));
-static void s_iq2000_end PARAMS ((int));
-static int  get_number PARAMS ((void));
-static symbolS * get_symbol PARAMS ((void));
-static void iq2000_record_hi16 PARAMS((int, fixS *, segT));
-
-
-/* The target specific pseudo-ops which we support.  */
-const pseudo_typeS md_pseudo_table[] =
-{
-    { "align",  s_align_bytes,           0 },
-    { "word",   cons,                    4 },
-    { "rdata",  s_change_sec, 		'r'},
-    { "sdata",  s_change_sec, 		's'},
-    { "set",	s_iq2000_set,		 0 },
-    { "ent",    s_iq2000_ent, 		 0 },
-    { "end",    s_iq2000_end,              0 },
-    { "frame",  s_iq2000_frame, 		 0 },
-    { "fmask",  s_iq2000_mask, 		'F' },
-    { "mask",   s_iq2000_mask, 		'R' },
-    { "dword",	cons, 			 8 },
-    { "half",	cons, 			 2 },
-    { NULL, 	NULL,			 0 }
-};
-
 /* Relocations against symbols are done in two
    parts, with a HI relocation and a LO relocation.  Each relocation
    has only 16 bits of space to store an addend.  This means that in
@@ -129,171 +100,39 @@ const pseudo_typeS md_pseudo_table[] =
 struct iq2000_hi_fixup
 {
   struct iq2000_hi_fixup * next;  /* Next HI fixup.  */
-  fixS *                  fixp;  /* This fixup.  */
-  segT                    seg;   /* The section this fixup is in.  */
-
+  fixS *                  fixp;   /* This fixup.  */
+  segT                    seg;    /* The section this fixup is in.  */
 };
 
 /* The list of unmatched HI relocs.  */
 static struct iq2000_hi_fixup * iq2000_hi_fixup_list;
 
+/* Macro hash table, which we will add to.  */
+extern struct hash_control *macro_hash;
 
-/* assembler options */
-#define OPTION_CPU_2000		(OPTION_MD_BASE)
-#define OPTION_CPU_10	        (OPTION_MD_BASE + 1)
-
+const char *md_shortopts = "";
 struct option md_longopts[] =
-{  
-  { "m2000",       no_argument,	      NULL, OPTION_CPU_2000   },
-  { "m10",         no_argument,	      NULL, OPTION_CPU_10     },
-  { NULL,          no_argument,       NULL, 0                 },
+{
+  {NULL, no_argument, NULL, 0}
 };
-
 size_t md_longopts_size = sizeof (md_longopts);
 
-const char * md_shortopts = "";
-
-static void iq2000_add_macro         PARAMS ((const char *, const char *, const char **));
-static void iq2000_load_macros       PARAMS ((void));
-static void iq10_load_macros         PARAMS ((void));
-
-/* macro hash table, which we will add to.  */
-extern struct hash_control *macro_hash;
-
 int
-md_parse_option (c, arg)
-    int c ATTRIBUTE_UNUSED;
-    char * arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED,
+		 char * arg ATTRIBUTE_UNUSED)
 {
-  switch (c)
-    {
-    case OPTION_CPU_2000:
-      iq2000_flags = (iq2000_flags & ~EF_IQ2000_CPU_MASK) | EF_IQ2000_CPU_IQ2000;
-      iq2000_mach = bfd_mach_iq2000;
-      cpu_mach = (1 << MACH_IQ2000);
-      break;
-
-    case OPTION_CPU_10:
-      iq2000_flags = (iq2000_flags & ~EF_IQ2000_CPU_MASK) | EF_IQ2000_CPU_IQ10;
-      iq2000_mach = bfd_mach_iq10;
-      cpu_mach = (1 << MACH_IQ10);
-      /* only the first 3 pseudo ops (word, file, loc) are in IQ10 */
-      break;
-
-    default:
-      return 0;
-    }
-  return 1;
+  return 0;
 }
 
 void
-md_show_usage (stream)
-  FILE * stream;
-{
-  fprintf (stream, _("IQ2000 specific command line options:\n"));
-  fprintf (stream, _("-m2000 <default>           IQ2000 processor\n"));
-  fprintf (stream, _("-m10                       IQ10 processor\n"));
-} 
-
-
-void
-md_begin ()
+md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
 {
-  /* Initialize the `cgen' interface.  */
-  
-  /* Set the machine number and endian.  */
-  gas_cgen_cpu_desc = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
-					   CGEN_CPU_OPEN_ENDIAN,
-					   CGEN_ENDIAN_BIG,
-					   CGEN_CPU_OPEN_END);
-  iq2000_cgen_init_asm (gas_cgen_cpu_desc);
-
-  /* This is a callback from cgen to gas to parse operands.  */
-  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
-
-  /* Set the ELF flags if desired. */
-  if (iq2000_flags)
-    bfd_set_private_flags (stdoutput, iq2000_flags);
-
-  /* Set the machine type */
-  bfd_default_set_arch_mach (stdoutput, bfd_arch_iq2000, iq2000_mach);
-
-  if (iq2000_mach == bfd_mach_iq2000)
-    iq2000_load_macros ();
-  else
-    iq10_load_macros ();
 }
-
-static void
-iq2000_add_macro (name, semantics, arguments)
-     const char  *name;
-     const char  *semantics;
-     const char **arguments;
-{
-  macro_entry *macro;
-  sb macro_name;
-  const char *namestr;
-
-  macro = (macro_entry *) xmalloc (sizeof (macro_entry));
-  sb_new (&macro->sub);
-  sb_new (&macro_name);
-
-  macro->formal_count = 0;
-  macro->formals = 0;
-
-  sb_add_string (&macro->sub, semantics);
-
-  if (arguments != NULL)
-    {
-      formal_entry **p = &macro->formals;
-      
-      macro->formal_count = 0;
-      macro->formal_hash = hash_new ();
-      while (*arguments != NULL)
-	{
-	  formal_entry *formal;
-	  
-	  formal = (formal_entry *) xmalloc (sizeof (formal_entry));
-	  
-	  sb_new (&formal->name);
-	  sb_new (&formal->def);
-	  sb_new (&formal->actual);
-	  
-	  /* chlm: Added the following to allow defaulted args.  */
-	  if (strchr (*arguments,'='))
-	    {
-	      char * tt_args = strdup(*arguments);
-	      char * tt_dflt = strchr(tt_args,'=');
-
-	      *tt_dflt = 0;
-	      sb_add_string (&formal->name, tt_args);
-	      sb_add_string (&formal->def,  tt_dflt + 1);
-	    }
-	  else
-	    sb_add_string (&formal->name, *arguments);
-
-	  /* Add to macro's hash table.  */
-	  hash_jam (macro->formal_hash, sb_terminate (&formal->name), formal);
-	  
-	  formal->index = macro->formal_count;
-	  macro->formal_count++;
-	  *p = formal;
-	  p = &formal->next;
-	  *p = NULL;
-	  ++arguments;
-	}
-    }
-
-  sb_add_string (&macro_name, name);  
-  namestr = sb_terminate (&macro_name);
-  hash_jam (macro_hash, namestr, (PTR) macro);
-
-  macro_defined = 1;
-}
-
+
 /* Automatically enter conditional branch macros.  */
 
-typedef struct {
+typedef struct
+{
   const char * mnemonic;
   const char ** expansion;
   const char ** args;
@@ -301,10 +140,8 @@ typedef struct {
 
 static const char * abs_args[] = { "rd", "rs", "scratch=%1", NULL };
 static const char * abs_expn   = "\n sra \\rd,\\rs,31\n xor \\scratch,\\rd,\\rs\n sub \\rd,\\scratch,\\rd\n";
-
 static const char * la_expn    = "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
 static const char * la_args[]  = { "reg", "label", NULL };
-
 static const char * bxx_args[] = { "rs", "rt", "label", "scratch=%1", NULL };
 static const char * bge_expn   = "\n slt \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
 static const char * bgeu_expn  = "\n sltu \\scratch,\\rs,\\rt\n beq %0,\\scratch,\\label\n";
@@ -314,7 +151,6 @@ static const char * ble_expn   = "\n slt \\scratch,\\rt,\\rs\n beq %0,\\scratch,
 static const char * bleu_expn  = "\n sltu \\scratch,\\rt,\\rs\n beq %0,\\scratch,\\label\n";
 static const char * blt_expn   = "\n slt \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
 static const char * bltu_expn  = "\n sltu \\scratch,\\rs,\\rt\n bne %0,\\scratch,\\label\n";
-
 static const char * sxx_args[] = { "rd", "rs", "rt", NULL };
 static const char * sge_expn   = "\n slt \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
 static const char * sgeu_expn  = "\n sltu \\rd,\\rs,\\rt\n xori \\rd,\\rd,1\n";
@@ -324,7 +160,6 @@ static const char * sgt_expn   = "\n slt \\rd,\\rt,\\rs\n";
 static const char * sgtu_expn  = "\n sltu \\rd,\\rt,\\rs\n";
 static const char * sne_expn   = "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n";
 static const char * seq_expn   = "\n xor \\rd,\\rt,\\rs\n sltu \\rd,%0,\\rd\n xori \\rd,\\rd,1\n";
-
 static const char * ai32_args[] = { "rt", "rs", "imm", NULL };
 static const char * andi32_expn = "\n\
  .if (\\imm & 0xffff0000 == 0xffff0000)\n\
@@ -350,7 +185,6 @@ static const char * ori32_expn  = "\n\
 static const char * neg_args[] = { "rd", "rs", NULL };
 static const char * neg_expn   = "\n sub \\rd,%0,\\rs\n";
 static const char * negu_expn  = "\n subu \\rd,%0,\\rs\n";
-
 static const char * li_args[]  = { "rt", "imm", NULL };
 static const char * li_expn    = "\n\
  .if (\\imm & 0xffff0000 == 0x0)\n\
@@ -363,38 +197,106 @@ static const char * li_expn    = "\n\
  lui \\rt,%uhi(\\imm)\n\
  ori \\rt,\\rt,%lo(\\imm)\n\
  .endif\n";
-  
-static iq2000_macro_defs_s iq2000_macro_defs[] = {
-  {"abs",  (const char **)&abs_expn,  (const char **)&abs_args},
-  {"la",   (const char **)&la_expn,   (const char **)&la_args},
-  {"bge",  (const char **)&bge_expn,  (const char **)&bxx_args},
-  {"bgeu", (const char **)&bgeu_expn, (const char **)&bxx_args},
-  {"bgt",  (const char **)&bgt_expn,  (const char **)&bxx_args},
-  {"bgtu", (const char **)&bgtu_expn, (const char **)&bxx_args},
-  {"ble",  (const char **)&ble_expn,  (const char **)&bxx_args},
-  {"bleu", (const char **)&bleu_expn, (const char **)&bxx_args},
-  {"blt",  (const char **)&blt_expn,  (const char **)&bxx_args},
-  {"bltu", (const char **)&bltu_expn, (const char **)&bxx_args},
-  {"sge",  (const char **)&sge_expn,  (const char **)&sxx_args},
-  {"sgeu", (const char **)&sgeu_expn, (const char **)&sxx_args},
-  {"sle",  (const char **)&sle_expn,  (const char **)&sxx_args},
-  {"sleu", (const char **)&sleu_expn, (const char **)&sxx_args},
-  {"sgt",  (const char **)&sgt_expn,  (const char **)&sxx_args},
-  {"sgtu", (const char **)&sgtu_expn, (const char **)&sxx_args},
-  {"seq",  (const char **)&seq_expn,  (const char **)&sxx_args},
-  {"sne",  (const char **)&sne_expn,  (const char **)&sxx_args},
-  {"neg",  (const char **)&neg_expn,  (const char **)&neg_args},
-  {"negu", (const char **)&negu_expn, (const char **)&neg_args},
-  {"li",   (const char **)&li_expn,   (const char **)&li_args},
-  {"ori32", (const char **)&ori32_expn, (const char **)&ai32_args},
-  {"andi32",(const char **)&andi32_expn,(const char **)&ai32_args},
+
+static iq2000_macro_defs_s iq2000_macro_defs[] =
+{
+  {"abs",   (const char **) & abs_expn,   (const char **) & abs_args},
+  {"la",    (const char **) & la_expn,    (const char **) & la_args},
+  {"bge",   (const char **) & bge_expn,   (const char **) & bxx_args},
+  {"bgeu",  (const char **) & bgeu_expn,  (const char **) & bxx_args},
+  {"bgt",   (const char **) & bgt_expn,   (const char **) & bxx_args},
+  {"bgtu",  (const char **) & bgtu_expn,  (const char **) & bxx_args},
+  {"ble",   (const char **) & ble_expn,   (const char **) & bxx_args},
+  {"bleu",  (const char **) & bleu_expn,  (const char **) & bxx_args},
+  {"blt",   (const char **) & blt_expn,   (const char **) & bxx_args},
+  {"bltu",  (const char **) & bltu_expn,  (const char **) & bxx_args},
+  {"sge",   (const char **) & sge_expn,   (const char **) & sxx_args},
+  {"sgeu",  (const char **) & sgeu_expn,  (const char **) & sxx_args},
+  {"sle",   (const char **) & sle_expn,   (const char **) & sxx_args},
+  {"sleu",  (const char **) & sleu_expn,  (const char **) & sxx_args},
+  {"sgt",   (const char **) & sgt_expn,   (const char **) & sxx_args},
+  {"sgtu",  (const char **) & sgtu_expn,  (const char **) & sxx_args},
+  {"seq",   (const char **) & seq_expn,   (const char **) & sxx_args},
+  {"sne",   (const char **) & sne_expn,   (const char **) & sxx_args},
+  {"neg",   (const char **) & neg_expn,   (const char **) & neg_args},
+  {"negu",  (const char **) & negu_expn,  (const char **) & neg_args},
+  {"li",    (const char **) & li_expn,    (const char **) & li_args},
+  {"ori32", (const char **) & ori32_expn, (const char **) & ai32_args},
+  {"andi32",(const char **) & andi32_expn,(const char **) & ai32_args},
 };
 
 static void
-iq2000_load_macros ()
+iq2000_add_macro (const char *  name,
+		  const char *  semantics,
+		  const char ** arguments)
+{
+  macro_entry *macro;
+  sb macro_name;
+  const char *namestr;
+
+  macro = xmalloc (sizeof (macro_entry));
+  sb_new (& macro->sub);
+  sb_new (& macro_name);
+
+  macro->formal_count = 0;
+  macro->formals = 0;
+
+  sb_add_string (& macro->sub, semantics);
+
+  if (arguments != NULL)
+    {
+      formal_entry ** p = &macro->formals;
+
+      macro->formal_count = 0;
+      macro->formal_hash = hash_new ();
+
+      while (*arguments != NULL)
+	{
+	  formal_entry *formal;
+
+	  formal = xmalloc (sizeof (formal_entry));
+
+	  sb_new (& formal->name);
+	  sb_new (& formal->def);
+	  sb_new (& formal->actual);
+
+	  /* chlm: Added the following to allow defaulted args.  */
+	  if (strchr (*arguments,'='))
+	    {
+	      char * tt_args = strdup (*arguments);
+	      char * tt_dflt = strchr (tt_args,'=');
+
+	      *tt_dflt = 0;
+	      sb_add_string (& formal->name, tt_args);
+	      sb_add_string (& formal->def,  tt_dflt + 1);
+	    }
+	  else
+	    sb_add_string (& formal->name, *arguments);
+
+	  /* Add to macro's hash table.  */
+	  hash_jam (macro->formal_hash, sb_terminate (& formal->name), formal);
+
+	  formal->index = macro->formal_count;
+	  macro->formal_count++;
+	  *p = formal;
+	  p = & formal->next;
+	  *p = NULL;
+	  ++arguments;
+	}
+    }
+
+  sb_add_string (&macro_name, name);
+  namestr = sb_terminate (&macro_name);
+  hash_jam (macro_hash, namestr, macro);
+
+  macro_defined = 1;
+}
+
+static void
+iq2000_load_macros (void)
 {
   int i;
-  int mcnt = sizeof (iq2000_macro_defs) / sizeof (iq2000_macro_defs_s);
+  int mcnt = ARRAY_SIZE (iq2000_macro_defs);
 
   for (i = 0; i < mcnt; i++)
     iq2000_add_macro (iq2000_macro_defs[i].mnemonic,
@@ -402,26 +304,33 @@ iq2000_load_macros ()
 		      iq2000_macro_defs[i].args);
 }
 
-static void
-iq10_load_macros ()
+void
+md_begin (void)
 {
-  /* Allow all iq2k macros in iq10, instead of just LA. */
-  iq2000_load_macros ();
-#if 0
-  char *la_sem = "\n lui \\reg,%hi(\\label)\n ori \\reg,\\reg,%lo(\\label)\n";
+  /* Initialize the `cgen' interface.  */
 
-  char *la_arg_1 = "reg";
-  char *la_arg_2 = "label";
-  const char *la_args[3] = { la_arg_1, la_arg_2, NULL };
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
+					   CGEN_CPU_OPEN_ENDIAN,
+					   CGEN_ENDIAN_BIG,
+					   CGEN_CPU_OPEN_END);
+  iq2000_cgen_init_asm (gas_cgen_cpu_desc);
 
-  iq2000_add_macro ("la", la_sem, la_args);
-#endif
-}
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+  /* Set the ELF flags if desired.  */
+  if (iq2000_flags)
+    bfd_set_private_flags (stdoutput, iq2000_flags);
 
+  /* Set the machine type */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_iq2000, iq2000_mach);
+
+  iq2000_load_macros ();
+}
 
 void
-md_assemble (str)
-     char * str;
+md_assemble (char * str)
 {
   static long delayed_load_register = 0;
   static int last_insn_had_delay_slot = 0;
@@ -448,29 +357,21 @@ md_assemble (str)
   gas_cgen_finish_insn (insn.insn, insn.buffer,
 			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
 
-  /* We need to generate an error if there's a yielding instruction in the delay 
-     slot of a control flow modifying instruction (jump (yes), load (no))  */ 
+  /* We need to generate an error if there's a yielding instruction in the delay
+     slot of a control flow modifying instruction (jump (yes), load (no))  */
   if ((last_insn_had_delay_slot && !last_insn_has_load_delay) &&
       CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_YIELD_INSN))
       as_bad (_("the yielding instruction %s may not be in a delay slot."),
               CGEN_INSN_NAME (insn.insn));
 
   /* Warn about odd numbered base registers for paired-register
-     instructions like LDW.  On iq2000, result is always rt. */
+     instructions like LDW.  On iq2000, result is always rt.  */
   if (iq2000_mach == bfd_mach_iq2000
       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_EVEN_REG_NUM)
       && (insn.fields.f_rt % 2))
     as_bad (_("Register number (R%ld) for double word access must be even."),
 	    insn.fields.f_rt);
 
-  /* Warn about odd numbered base registers for paired-register
-     instructions like LDW.  On iq10, result is always rd. */
-  if (iq2000_mach == bfd_mach_iq10
-      && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_EVEN_REG_NUM)
-      && (insn.fields.f_rd % 2))
-    as_bad (_("Register number (R%ld) for double word access must be even."),
-	    insn.fields.f_rd);
-
   /* Warn about insns that reference the target of a previous load.  */
   /* NOTE: R0 is a special case and is not subject to load delays (except for ldw).  */
   if (delayed_load_register && (last_insn_has_load_delay || last_insn_was_ldw))
@@ -479,34 +380,34 @@ md_assemble (str)
 	  insn.fields.f_rd == delayed_load_register)
 	as_warn (_("operand references R%ld of previous load."),
 		 insn.fields.f_rd);
-      
+
       if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RS) &&
 	  insn.fields.f_rs == delayed_load_register)
 	as_warn (_("operand references R%ld of previous load."),
 		 insn.fields.f_rs);
-      
+
       if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RT) &&
 	  insn.fields.f_rt == delayed_load_register)
 	as_warn (_("operand references R%ld of previous load."),
 		 insn.fields.f_rt);
-      
+
       if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_R31) &&
 	  delayed_load_register == 31)
 	as_warn (_("instruction implicitly accesses R31 of previous load."));
     }
 
-  /* Warn about insns that reference the (target + 1) of a previous ldw */ 
-  if (last_insn_was_ldw) 
-    { 
-      if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RD) 
-           && insn.fields.f_rd == delayed_load_register + 1) 
-       || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RS) 
-           && insn.fields.f_rs == delayed_load_register + 1) 
-       || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RT) 
-           && insn.fields.f_rt == delayed_load_register + 1)) 
-        as_warn (_("operand references R%ld of previous load."), 
-                delayed_load_register + 1); 
-    } 
+  /* Warn about insns that reference the (target + 1) of a previous ldw.  */
+  if (last_insn_was_ldw)
+    {
+      if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RD)
+           && insn.fields.f_rd == delayed_load_register + 1)
+       || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RS)
+           && insn.fields.f_rs == delayed_load_register + 1)
+       || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_RT)
+           && insn.fields.f_rt == delayed_load_register + 1))
+        as_warn (_("operand references R%ld of previous load."),
+                delayed_load_register + 1);
+    }
 
   last_insn_had_delay_slot =
     CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
@@ -520,28 +421,23 @@ md_assemble (str)
 	   || ! strcmp (CGEN_INSN_MNEMONIC (insn.insn), "jal"))
 	   last_insn_unconditional_jump = 1;
 
-  /* The meaning of EVEN_REG_NUM was overloaded to also imply LDW.  Since that's 
-     not true for IQ10, let's make the above logic specific to LDW. */
+  /* The meaning of EVEN_REG_NUM was overloaded to also imply LDW.  Since
+     that's not true for IQ10, let's make the above logic specific to LDW.  */
   last_insn_was_ldw = ! strcmp ("ldw", CGEN_INSN_NAME (insn.insn));
 
-  /* The assumption here is that the target of a load is always rt.
-     That is true for iq2000 & iq10. */
+  /* The assumption here is that the target of a load is always rt.  */
   delayed_load_register = insn.fields.f_rt;
 }
 
 valueT
-md_section_align (segment, size)
-     segT   segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
-
 symbolS *
-md_undefined_symbol (name)
-    char * name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 {
     return 0;
 }
@@ -560,9 +456,8 @@ md_undefined_symbol (name)
    0 value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS * fragP;
-     segT    segment ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS * fragP,
+			       segT    segment ATTRIBUTE_UNUSED)
 {
   int    old_fr_fix = fragP->fr_fix;
 
@@ -573,7 +468,7 @@ md_estimate_size_before_relax (fragP, segment)
      alignment requirements may move the insn about.  */
 
   return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
-} 
+}
 
 /* *fragP has been relaxed to its final size, and now needs to have
    the bytes inside it modified to conform to the new size.
@@ -583,10 +478,9 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-    bfd   * abfd  ATTRIBUTE_UNUSED;
-    segT    sec   ATTRIBUTE_UNUSED;
-    fragS * fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd   * abfd  ATTRIBUTE_UNUSED,
+		 segT    sec   ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
 {
 }
 
@@ -594,9 +488,7 @@ md_convert_frag (abfd, sec, fragP)
 /* Functions concerning relocs.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS * fixP;
-     segT   sec;
+md_pcrel_from_section (fixS * fixP, segT sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
@@ -607,7 +499,7 @@ md_pcrel_from_section (fixP, sec)
       return 0;
     }
 
-  /* return the address of the delay slot */
+  /* Return the address of the delay slot.  */
   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
@@ -616,28 +508,18 @@ md_pcrel_from_section (fixP, sec)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *    insn     ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND * operand;
-     fixS *               fixP     ATTRIBUTE_UNUSED;
+md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP     ATTRIBUTE_UNUSED)
 {
   switch (operand->type)
     {
-    case IQ2000_OPERAND_OFFSET:
-      return BFD_RELOC_16_PCREL_S2;
-    case IQ2000_OPERAND_JMPTARG:
-      return BFD_RELOC_IQ2000_OFFSET_16;
-    case IQ2000_OPERAND_JMPTARGQ10:
-      if (iq2000_mach == bfd_mach_iq10)
-	return BFD_RELOC_IQ2000_OFFSET_21;
-      return BFD_RELOC_NONE;
-    case IQ2000_OPERAND_HI16:
-      return BFD_RELOC_HI16;
-    case IQ2000_OPERAND_LO16:
-      return BFD_RELOC_LO16;
-    default:
-      /* Pacify gcc -Wall.  */
-      return BFD_RELOC_NONE;
+    case IQ2000_OPERAND_OFFSET:      return BFD_RELOC_16_PCREL_S2;
+    case IQ2000_OPERAND_JMPTARG:     return BFD_RELOC_IQ2000_OFFSET_16;
+    case IQ2000_OPERAND_JMPTARGQ10:  return BFD_RELOC_NONE;
+    case IQ2000_OPERAND_HI16:        return BFD_RELOC_HI16;
+    case IQ2000_OPERAND_LO16:        return BFD_RELOC_LO16;
+    default: break;
     }
 
   return BFD_RELOC_NONE;
@@ -646,21 +528,19 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 /* Record a HI16 reloc for later matching with its LO16 cousin.  */
 
 static void
-iq2000_record_hi16 (reloc_type, fixP, seg)
-     int    reloc_type;
-     fixS * fixP;
-     segT   seg ATTRIBUTE_UNUSED;
+iq2000_record_hi16 (int    reloc_type,
+		    fixS * fixP,
+		    segT   seg ATTRIBUTE_UNUSED)
 {
   struct iq2000_hi_fixup * hi_fixup;
 
   assert (reloc_type == BFD_RELOC_HI16);
 
-  hi_fixup = ((struct iq2000_hi_fixup *)
-	      xmalloc (sizeof (struct iq2000_hi_fixup)));
+  hi_fixup = xmalloc (sizeof * hi_fixup);
   hi_fixup->fixp = fixP;
   hi_fixup->seg  = now_seg;
   hi_fixup->next = iq2000_hi_fixup_list;
-  
+
   iq2000_hi_fixup_list = hi_fixup;
 }
 
@@ -668,29 +548,22 @@ iq2000_record_hi16 (reloc_type, fixP, seg)
    We need to check for HI16 relocs and queue them up for later sorting.  */
 
 fixS *
-iq2000_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
-     fragS *              frag;
-     int                  where;
-     const CGEN_INSN *    insn;
-     int                  length;
-     const CGEN_OPERAND * operand;
-     int                  opinfo;
-     expressionS *        exp;
+iq2000_cgen_record_fixup_exp (fragS *              frag,
+			      int                  where,
+			      const CGEN_INSN *    insn,
+			      int                  length,
+			      const CGEN_OPERAND * operand,
+			      int                  opinfo,
+			      expressionS *        exp)
 {
   fixS * fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
 					   operand, opinfo, exp);
 
-  switch (operand->type)
-    {
-    case IQ2000_OPERAND_HI16 :
+  if (operand->type == IQ2000_OPERAND_HI16
       /* If low/high was used, it is recorded in `opinfo'.  */
-      if (fixP->fx_cgen.opinfo == BFD_RELOC_HI16
-	  || fixP->fx_cgen.opinfo == BFD_RELOC_LO16)
-	iq2000_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
-      break;
-    default : /* avoid -Wall warning */
-      break;
-    }
+      && (fixP->fx_cgen.opinfo == BFD_RELOC_HI16
+	  || fixP->fx_cgen.opinfo == BFD_RELOC_LO16))
+    iq2000_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
 
   return fixP;
 }
@@ -701,11 +574,11 @@ iq2000_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
 
 /* Sort any unmatched HI16 relocs so that they immediately precede
-   the corresponding LO16 reloc.  This is called before md_apply_fix3 and
+   the corresponding LO16 reloc.  This is called before md_apply_fix and
    tc_gen_reloc.  */
 
 void
-iq2000_frob_file ()
+iq2000_frob_file (void)
 {
   struct iq2000_hi_fixup * l;
 
@@ -713,10 +586,10 @@ iq2000_frob_file ()
     {
       segment_info_type * seginfo;
       int                 pass;
-      
+
       assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_HI16
 	      || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_LO16);
-      
+
       /* Check quickly whether the next fixup happens to be a matching low.  */
       if (l->fixp->fx_next != NULL
 	  && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_LO16
@@ -783,8 +656,7 @@ iq2000_frob_file ()
 /* See whether we need to force a relocation into the output file.  */
 
 int
-iq2000_force_relocation (fix)
-     fixS * fix;
+iq2000_force_relocation (fixS * fix)
 {
   if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
@@ -796,9 +668,25 @@ iq2000_force_relocation (fix)
 /* Handle the .set pseudo-op.  */
 
 static void
-s_iq2000_set (x)
-     int x ATTRIBUTE_UNUSED;
+s_iq2000_set (int x ATTRIBUTE_UNUSED)
 {
+  static const char * ignored_arguments [] =
+    {
+      "reorder",
+      "noreorder",
+      "at",
+      "noat",
+      "macro",
+      "nomacro",
+      "move",
+      "novolatile",
+      "nomove",
+      "volatile",
+      "bopt",
+      "nobopt",
+      NULL
+    };
+  const char ** ignored;
   char *name = input_line_pointer, ch;
   char *save_ILP = input_line_pointer;
 
@@ -807,43 +695,15 @@ s_iq2000_set (x)
   ch = *input_line_pointer;
   *input_line_pointer = '\0';
 
-  if (strcmp (name, "reorder") == 0)
-    {
-    }
-  else if (strcmp (name, "noreorder") == 0)
-    {
-    }
-  else if (strcmp (name, "at") == 0)
-    {
-    }
-  else if (strcmp (name, "noat") == 0)
-    {
-    }
-  else if (strcmp (name, "macro") == 0)
-    {
-    }
-  else if (strcmp (name, "nomacro") == 0)
-    {
-    }
-  else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0)
-    {
-    }
-  else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0)
-    {
-    }
-  else if (strcmp (name, "bopt") == 0)
-    {
-    }
-  else if (strcmp (name, "nobopt") == 0)
-    {
-    }
-  else
+  for (ignored = ignored_arguments; * ignored; ignored ++)
+    if (strcmp (* ignored, name) == 0)
+      break;
+  if (* ignored == NULL)
     {
       /* We'd like to be able to use .set symbol, expn */
       input_line_pointer = save_ILP;
       s_set (0);
       return;
-      /*as_warn (_("Tried to set unrecognized symbol: %s\n"), name);*/
     }
   *input_line_pointer = ch;
   demand_empty_rest_of_line ();
@@ -852,19 +712,15 @@ s_iq2000_set (x)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+md_number_to_chars (char * buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
 
 void
-md_operand (exp)
-     expressionS * exp;
+md_operand (expressionS * exp)
 {
-  /* In case of a syntax error, escape back to try next syntax combo. */
+  /* In case of a syntax error, escape back to try next syntax combo.  */
   if (exp->X_op == O_absent)
     gas_cgen_md_operand (exp);
 }
@@ -878,10 +734,7 @@ md_operand (exp)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char * litP, int * sizeP)
 {
   int              i;
   int              prec;
@@ -915,7 +768,7 @@ md_atof (type, litP, sizeP)
   if (t)
     input_line_pointer = t;
   * sizeP = prec * sizeof (LITTLENUM_TYPE);
-  
+
   for (i = 0; i < prec; i++)
     {
       md_number_to_chars (litP, (valueT) words[i],
@@ -928,8 +781,7 @@ md_atof (type, litP, sizeP)
 
 
 bfd_boolean
-iq2000_fix_adjustable (fixP)
-   fixS * fixP;
+iq2000_fix_adjustable (fixS * fixP)
 {
   bfd_reloc_code_real_type reloc_type;
 
@@ -938,6 +790,7 @@ iq2000_fix_adjustable (fixP)
       const CGEN_INSN *insn = NULL;
       int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
       const CGEN_OPERAND *operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+
       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
     }
   else
@@ -945,14 +798,14 @@ iq2000_fix_adjustable (fixP)
 
   if (fixP->fx_addsy == NULL)
     return TRUE;
-  
+
   /* Prevent all adjustments to global symbols.  */
-  if (S_IS_EXTERN (fixP->fx_addsy))
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
     return FALSE;
-  
+
   if (S_IS_WEAK (fixP->fx_addsy))
     return FALSE;
-  
+
   /* We need the symbol name for the VTABLE entries.  */
   if (   reloc_type == BFD_RELOC_VTABLE_INHERIT
       || reloc_type == BFD_RELOC_VTABLE_ENTRY)
@@ -962,10 +815,8 @@ iq2000_fix_adjustable (fixP)
 }
 
 static void
-s_change_sec (sec)
-     int sec;
+s_change_sec (int sec)
 {
-
 #ifdef OBJ_ELF
   /* The ELF backend needs to know that we are changing sections, so
      that .previous works correctly.  We could do something like check
@@ -976,8 +827,6 @@ s_change_sec (sec)
   obj_elf_section_change_hook ();
 #endif
 
-  /*   iq2000_emit_delays (false); */
-
   switch (sec)
     {
     case 't':
@@ -990,11 +839,24 @@ s_change_sec (sec)
     }
 }
 
+static symbolS *
+get_symbol (void)
+{
+  int c;
+  char *name;
+  symbolS *p;
+
+  name = input_line_pointer;
+  c = get_symbol_end ();
+  p = (symbolS *) symbol_find_or_make (name);
+  *input_line_pointer = c;
+  return p;
+}
+
 /* The .end directive.  */
 
 static void
-s_iq2000_end (x)
-     int x ATTRIBUTE_UNUSED;
+s_iq2000_end (int x ATTRIBUTE_UNUSED)
 {
   symbolS *p;
   int maybe_text;
@@ -1007,141 +869,35 @@ s_iq2000_end (x)
   else
     p = NULL;
 
-  if (1/*iq2000_mach == bfd_mach_iq2000*/)
-    {
-#ifdef BFD_ASSEMBLER
-      if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
-	maybe_text = 1;
-      else
-	maybe_text = 0;
-#else
-      if (now_seg != data_section && now_seg != bss_section)
-	maybe_text = 1;
-      else
-	maybe_text = 0;
-#endif
-      
-      if (!maybe_text)
-	as_warn (_(".end not in text section"));
-      
-      if (!cur_proc_ptr)
-	{
-	  as_warn (_(".end directive without a preceding .ent directive."));
-	  demand_empty_rest_of_line ();
-	  return;
-	}
-      
-      if (p != NULL)
-	{
-	  assert (S_GET_NAME (p));
-	  if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
-	    as_warn (_(".end symbol does not match .ent symbol."));
-	}
-      else
-	as_warn (_(".end directive missing or unknown symbol"));
-      
-    }
-
-  cur_proc_ptr = NULL;
-}
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
 
-/* The .aent and .ent directives.  */
+  if (!maybe_text)
+    as_warn (_(".end not in text section"));
 
-static void
-s_iq2000_ent (aent)
-     int aent;
-{
-  int number = 0;
-  symbolS *symbolP;
-  int maybe_text;
+  if (!cur_proc_ptr)
+    {
+      as_warn (_(".end directive without a preceding .ent directive."));
+      demand_empty_rest_of_line ();
+      return;
+    }
 
-  if (1/*iq2000_mach == bfd_mach_iq2000*/)
+  if (p != NULL)
     {
-      symbolP = get_symbol ();
-      if (*input_line_pointer == ',')
-	input_line_pointer++;
-      SKIP_WHITESPACE ();
-      if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
-	number = get_number ();
-      
-#ifdef BFD_ASSEMBLER
-      if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
-	maybe_text = 1;
-      else
-	maybe_text = 0;
-#else
-      if (now_seg != data_section && now_seg != bss_section)
-	maybe_text = 1;
-      else
-	maybe_text = 0;
-#endif
-      
-      if (!maybe_text)
-	as_warn (_(".ent or .aent not in text section."));
-      
-      if (!aent && cur_proc_ptr)
-	as_warn (_("missing `.end'"));
-      
-      if (!aent)
-	{
-	  cur_proc_ptr = &cur_proc;
-	  memset (cur_proc_ptr, '\0', sizeof (procS));
-	  
-	  cur_proc_ptr->isym = symbolP;
-	  
-	  symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
-	  
-	  numprocs++;
-	}
+      assert (S_GET_NAME (p));
+      if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
+	as_warn (_(".end symbol does not match .ent symbol."));
     }
   else
-    as_bad (_("unknown pseudo-op: `%s'"), ".ent");
+    as_warn (_(".end directive missing or unknown symbol"));
 
-  demand_empty_rest_of_line ();
-}
-
-/* The .frame directive. If the mdebug section is present (IRIX 5 native)
-   then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
-   s_iq2000_frame is used so that we can set the PDR information correctly.
-   We can't use the ecoff routines because they make reference to the ecoff
-   symbol table (in the mdebug section).  */
-
-static void
-s_iq2000_frame (ignore)
-     int ignore;
-{
-  s_ignore (ignore);
-}
-
-/* The .fmask and .mask directives. If the mdebug section is present
-   (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
-   embedded targets, s_iq2000_mask is used so that we can set the PDR
-   information correctly. We can't use the ecoff routines because they
-   make reference to the ecoff symbol table (in the mdebug section).  */
-
-static void
-s_iq2000_mask (reg_type)
-     char reg_type;
-{
-  s_ignore (reg_type);
-}
-
-static symbolS *
-get_symbol ()
-{
-  int c;
-  char *name;
-  symbolS *p;
-
-  name = input_line_pointer;
-  c = get_symbol_end ();
-  p = (symbolS *) symbol_find_or_make (name);
-  *input_line_pointer = c;
-  return p;
+  cur_proc_ptr = NULL;
 }
 
 static int
-get_number ()
+get_number (void)
 {
   int negative = 0;
   long val = 0;
@@ -1197,3 +953,86 @@ get_number ()
   return negative ? -val : val;
 }
 
+/* The .aent and .ent directives.  */
+
+static void
+s_iq2000_ent (int aent)
+{
+  int number = 0;
+  symbolS *symbolP;
+  int maybe_text;
+
+  symbolP = get_symbol ();
+  if (*input_line_pointer == ',')
+    input_line_pointer++;
+  SKIP_WHITESPACE ();
+  if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-')
+    number = get_number ();
+
+  if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
+    maybe_text = 1;
+  else
+    maybe_text = 0;
+
+  if (!maybe_text)
+    as_warn (_(".ent or .aent not in text section."));
+
+  if (!aent && cur_proc_ptr)
+    as_warn (_("missing `.end'"));
+
+  if (!aent)
+    {
+      cur_proc_ptr = &cur_proc;
+      memset (cur_proc_ptr, '\0', sizeof (procS));
+
+      cur_proc_ptr->isym = symbolP;
+
+      symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
+
+      numprocs++;
+    }
+
+  demand_empty_rest_of_line ();
+}
+
+/* The .frame directive. If the mdebug section is present (IRIX 5 native)
+   then ecoff.c (ecoff_directive_frame) is used. For embedded targets,
+   s_iq2000_frame is used so that we can set the PDR information correctly.
+   We can't use the ecoff routines because they make reference to the ecoff
+   symbol table (in the mdebug section).  */
+
+static void
+s_iq2000_frame (int ignore)
+{
+  s_ignore (ignore);
+}
+
+/* The .fmask and .mask directives. If the mdebug section is present
+   (IRIX 5 native) then ecoff.c (ecoff_directive_mask) is used. For
+   embedded targets, s_iq2000_mask is used so that we can set the PDR
+   information correctly. We can't use the ecoff routines because they
+   make reference to the ecoff symbol table (in the mdebug section).  */
+
+static void
+s_iq2000_mask (int reg_type)
+{
+  s_ignore (reg_type);
+}
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+    { "align",  s_align_bytes,           0 },
+    { "word",   cons,                    4 },
+    { "rdata",  s_change_sec, 		'r'},
+    { "sdata",  s_change_sec, 		's'},
+    { "set",	s_iq2000_set,		 0 },
+    { "ent",    s_iq2000_ent, 		 0 },
+    { "end",    s_iq2000_end,            0 },
+    { "frame",  s_iq2000_frame, 	 0 },
+    { "fmask",  s_iq2000_mask, 		'F'},
+    { "mask",   s_iq2000_mask, 		'R'},
+    { "dword",	cons, 			 8 },
+    { "half",	cons, 			 2 },
+    { NULL, 	NULL,			 0 }
+};
diff --git a/gas/config/tc-iq2000.h b/gas/config/tc-iq2000.h
index 30b6d5f62ab3..aba1da1f49b4 100644
--- a/gas/config/tc-iq2000.h
+++ b/gas/config/tc-iq2000.h
@@ -1,5 +1,5 @@
 /* tc-iq2000.h -- Header file for tc-iq2000.c.
-   Copyright (C) 2003 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,16 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA. */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA. */
 
 #define TC_IQ2000
 
-#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
- #error IQ2000 support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "IQ2000 GAS "
 
 /* The target BFD architecture.  */
@@ -34,37 +29,37 @@
 
 #define TARGET_BYTES_BIG_ENDIAN 1
 
-/* Permit temporary numeric labels. */
+/* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-/* .-foo gets turned into PC relative relocs. */
+/* .-foo gets turned into PC relative relocs.  */
 #define DIFF_EXPR_OK
 
-/* We don't need to handle .word strangely. */
+/* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
-#define md_apply_fix3 gas_cgen_md_apply_fix3
+#define md_apply_fix gas_cgen_md_apply_fix
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
 #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
 
 #define tc_frob_file() iq2000_frob_file ()
-extern void iq2000_frob_file PARAMS ((void));
 
 #define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
-extern bfd_boolean iq2000_fix_adjustable PARAMS ((struct fix *));
 
 /* After creating a fixup for an instruction operand, we need to check
-   for HI16 relocs and queue them up for later sorting. */
+   for HI16 relocs and queue them up for later sorting.  */
 #define md_cgen_record_fixup_exp  iq2000_cgen_record_fixup_exp
 
 /* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
 #define TC_FORCE_RELOCATION(fix) iq2000_force_relocation (fix)
-extern int iq2000_force_relocation PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_gen_reloc gas_cgen_tc_gen_reloc
 
+extern void         iq2000_frob_file         (void);
+extern bfd_boolean  iq2000_fix_adjustable    (struct fix *);
+extern int          iq2000_force_relocation  (struct fix *);
+extern long         md_pcrel_from_section    (struct fix *, segT);
diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c
new file mode 100644
index 000000000000..5f174d39c0d2
--- /dev/null
+++ b/gas/config/tc-m32c.c
@@ -0,0 +1,1311 @@
+/* tc-m32c.c -- Assembler for the Renesas M32C.
+   Copyright (C) 2005 Free Software Foundation.
+   Contributed by RedHat.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include <stdio.h>
+#include "as.h"
+#include "subsegs.h"     
+#include "symcat.h"
+#include "opcodes/m32c-desc.h"
+#include "opcodes/m32c-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/m32c.h"
+#include "libbfd.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+#include "bfd.h"
+
+/* Structure to hold all of the different components
+   describing an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int                   num_fixups;
+  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
+  int                   indices [MAX_OPERAND_INSTANCES];
+}
+m32c_insn;
+
+#define rl_for(insn) (CGEN_ATTR_CGEN_INSN_RL_TYPE_VALUE (&(insn.insn->base->attrs)))
+#define relaxable(insn) (CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (&(insn.insn->base->attrs)))
+
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
+const char line_separator_chars[] = "|";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+#define M32C_SHORTOPTS ""
+const char * md_shortopts = M32C_SHORTOPTS;
+
+/* assembler options */
+#define OPTION_CPU_M16C	       (OPTION_MD_BASE)
+#define OPTION_CPU_M32C        (OPTION_MD_BASE + 1)
+#define OPTION_LINKRELAX       (OPTION_MD_BASE + 2)
+
+struct option md_longopts[] =
+{
+  { "m16c",       no_argument,	      NULL, OPTION_CPU_M16C   },
+  { "m32c",       no_argument,	      NULL, OPTION_CPU_M32C   },
+  { "relax",      no_argument,	      NULL, OPTION_LINKRELAX   },
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* Default machine */
+
+#define DEFAULT_MACHINE bfd_mach_m16c
+#define DEFAULT_FLAGS	EF_M32C_CPU_M16C
+
+static unsigned long m32c_mach = bfd_mach_m16c;
+static int cpu_mach = (1 << MACH_M16C);
+static int insn_size;
+static int m32c_relax = 0;
+
+/* Flags to set in the elf header */
+static flagword m32c_flags = DEFAULT_FLAGS;
+
+static char default_isa = 1 << (7 - ISA_M16C);
+static CGEN_BITSET m32c_isa = {1, & default_isa};
+
+static void
+set_isa (enum isa_attr isa_num)
+{
+  cgen_bitset_set (& m32c_isa, isa_num);
+}
+
+static void s_bss (int);
+
+int
+md_parse_option (int c, char * arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    case OPTION_CPU_M16C:
+      m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M16C;
+      m32c_mach = bfd_mach_m16c;
+      cpu_mach = (1 << MACH_M16C);
+      set_isa (ISA_M16C);
+      break;
+
+    case OPTION_CPU_M32C:
+      m32c_flags = (m32c_flags & ~EF_M32C_CPU_MASK) | EF_M32C_CPU_M32C;
+      m32c_mach = bfd_mach_m32c;
+      cpu_mach = (1 << MACH_M32C);
+      set_isa (ISA_M32C);
+      break;
+
+    case OPTION_LINKRELAX:
+      m32c_relax = 1;
+      break;
+
+    default:
+      return 0;
+    }
+  return 1;
+}
+
+void
+md_show_usage (FILE * stream)
+{
+  fprintf (stream, _(" M32C specific command line options:\n"));
+} 
+
+static void
+s_bss (int ignore ATTRIBUTE_UNUSED)
+{
+  int temp;
+
+  temp = get_absolute_expression ();
+  subseg_set (bss_section, (subsegT) temp);
+  demand_empty_rest_of_line ();
+}
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "bss",	s_bss, 		0},
+  { "word",	cons,		4 },
+  { NULL, 	NULL, 		0 }
+};
+
+
+void
+md_begin (void)
+{
+  /* Initialize the `cgen' interface.  */
+
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
+					  CGEN_CPU_OPEN_ENDIAN,
+					  CGEN_ENDIAN_BIG,
+					  CGEN_CPU_OPEN_ISAS, & m32c_isa,
+					  CGEN_CPU_OPEN_END);
+
+  m32c_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+  /* Set the ELF flags if desired. */
+  if (m32c_flags)
+    bfd_set_private_flags (stdoutput, m32c_flags);
+
+  /* Set the machine type */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_m32c, m32c_mach);
+
+  insn_size = 0;
+}
+
+void
+m32c_md_end (void)
+{
+  int i, n_nops;
+
+  if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE)
+    {
+      /* Pad with nops for objdump.  */
+      n_nops = (32 - ((insn_size) % 32)) / 8;
+      for (i = 1; i <= n_nops; i++)
+	md_assemble ("nop");
+    }
+}
+
+void
+m32c_start_line_hook (void)
+{
+#if 0 /* not necessary....handled in the .cpu file */
+  char *s = input_line_pointer;
+  char *sg;
+
+  for (s = input_line_pointer ; s && s[0] != '\n'; s++)
+    {
+      if (s[0] == ':')
+	{
+	  /* Remove :g suffix.  Squeeze out blanks.  */
+	  if (s[1] == 'g')
+	    {
+	      for (sg = s - 1; sg && sg >= input_line_pointer; sg--)
+		{
+		  sg[2] = sg[0];
+		}
+	      sg[1] = ' ';
+	      sg[2] = ' ';
+	      input_line_pointer += 2;
+	    }
+	}
+    }
+#endif
+}
+
+/* Process [[indirect-operands]] in instruction str.  */
+
+static bfd_boolean
+m32c_indirect_operand (char *str)
+{
+  char *new_str;
+  char *s;
+  char *ns;
+  int ns_len;
+  char *ns_end;
+  enum indirect_type {none, relative, absolute} ;
+  enum indirect_type indirection [3] = { none, none, none };
+  int brace_n [3] = { 0, 0, 0 };
+  int operand;
+
+  s = str;
+  operand = 1;
+  for (s = str; *s; s++)
+    {
+      if (s[0] == ',')
+	operand = 2;
+      /* [abs] where abs is not a0 or a1  */
+      if (s[1] == '[' && ! (s[2] == 'a' && (s[3] == '0' || s[3] == '1'))
+	  && (ISBLANK (s[0]) || s[0] == ','))
+	indirection[operand] = absolute;
+      if (s[0] == ']' && s[1] == ']')
+	indirection[operand] = relative;
+      if (s[0] == '[' && s[1] == '[')
+	indirection[operand] = relative;
+    }
+   
+  if (indirection[1] == none && indirection[2] == none)
+    return FALSE;
+  
+  operand = 1;
+  ns_len = strlen (str);
+  new_str = (char*) xmalloc (ns_len);
+  ns = new_str;
+  ns_end = ns + ns_len;
+ 
+  for (s = str; *s; s++)
+    {
+      if (s[0] == ',')
+	operand = 2;
+ 
+      if (s[0] == '[' && ! brace_n[operand])
+	{
+	  brace_n[operand] += 1;
+	  /* Squeeze [[ to [ if this is an indirect operand.  */
+	  if (indirection[operand] != none)
+	    continue;
+	}
+ 
+      else if (s[0] == '[' && brace_n[operand])
+	{
+	  brace_n[operand] += 1;
+	}
+      else if (s[0] == ']' && s[1] == ']' && indirection[operand] == relative)
+	{
+	  s += 1;		/* skip one ].  */
+	  brace_n[operand] -= 2; /* allow for 2 [.  */
+	}
+      else if (s[0] == ']' && indirection[operand] == absolute)
+	{
+	  brace_n[operand] -= 1;
+	  continue;		/* skip closing ].  */
+	}
+      else if (s[0] == ']')
+	{
+	  brace_n[operand] -= 1;
+	}
+      *ns = s[0];
+      ns += 1;
+      if (ns >= ns_end)
+	return FALSE;
+      if (s[0] == 0)
+	break;
+    }
+  *ns = '\0';
+  for (operand = 1; operand <= 2; operand++)
+    if (brace_n[operand])
+      {
+	fprintf (stderr, "Unmatched [[operand-%d]] %d\n", operand, brace_n[operand]);
+      }
+       
+  if (indirection[1] != none && indirection[2] != none)
+    md_assemble ("src-dest-indirect");
+  else if (indirection[1] != none)
+    md_assemble ("src-indirect");
+  else if (indirection[2] != none)
+    md_assemble ("dest-indirect");
+
+  md_assemble (new_str);
+  free (new_str);
+  return TRUE;
+}
+
+void
+md_assemble (char * str)
+{
+  static int last_insn_had_delay_slot = 0;
+  m32c_insn insn;
+  char *    errmsg;
+  finished_insnS results;
+  int rl_type;
+
+  if (m32c_mach == bfd_mach_m32c && m32c_indirect_operand (str))
+    return;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  insn.insn = m32c_cgen_assemble_insn
+    (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+  
+  if (!insn.insn)
+    {
+      as_bad ("%s", errmsg);
+      return;
+    }
+
+  results.num_fixups = 0;
+  /* Doesn't really matter what we pass for RELAX_P here.  */
+  gas_cgen_finish_insn (insn.insn, insn.buffer,
+			CGEN_FIELDS_BITSIZE (& insn.fields), 1, &results);
+
+  last_insn_had_delay_slot
+    = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
+  insn_size = CGEN_INSN_BITSIZE(insn.insn);
+
+  rl_type = rl_for (insn);
+
+  /* We have to mark all the jumps, because we need to adjust them
+     when we delete bytes, but we only need to mark the displacements
+     if they're symbolic - if they're not, we've already picked the
+     shortest opcode by now.  The linker, however, will still have to
+     check any operands to see if they're the displacement type, since
+     we don't know (nor record) *which* operands are relaxable.  */
+  if (m32c_relax
+      && rl_type != RL_TYPE_NONE
+      && (rl_type == RL_TYPE_JUMP || results.num_fixups)
+      && !relaxable (insn))
+    {
+      int reloc = 0;
+      int addend = results.num_fixups + 16 * insn_size/8;
+
+      switch (rl_for (insn))
+	{
+	case RL_TYPE_JUMP:  reloc = BFD_RELOC_M32C_RL_JUMP;  break;
+	case RL_TYPE_1ADDR: reloc = BFD_RELOC_M32C_RL_1ADDR; break;
+	case RL_TYPE_2ADDR: reloc = BFD_RELOC_M32C_RL_2ADDR; break;
+	}
+      if (insn.insn->base->num == M32C_INSN_JMP16_S
+	  || insn.insn->base->num == M32C_INSN_JMP32_S)
+	addend = 0x10;
+
+      fix_new (results.frag,
+	       results.addr - results.frag->fr_literal,
+	       0, abs_section_sym, addend, 0,
+	       reloc);
+    }
+}
+
+/* The syntax in the manual says constants begin with '#'.
+   We just ignore it.  */
+
+void 
+md_operand (expressionS * exp)
+{
+  /* In case of a syntax error, escape back to try next syntax combo. */
+  if (exp->X_op == O_absent)
+    gas_cgen_md_operand (exp);
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+const relax_typeS md_relax_table[] =
+{
+  /* The fields are:
+     1) most positive reach of this state,
+     2) most negative reach of this state,
+     3) how many bytes this mode will have in the variable part of the frag
+     4) which index into the table to try if we can't fit into this one.  */
+
+  /* 0 */ {     0,      0, 0,  0 }, /* unused */
+  /* 1 */ {     0,      0, 0,  0 }, /* marker for "don't know yet" */
+
+  /* 2 */ {   127,   -128, 2,  3 }, /* jcnd16_5.b */
+  /* 3 */ { 32767, -32768, 5,  4 }, /* jcnd16_5.w */
+  /* 4 */ {     0,      0, 6,  0 }, /* jcnd16_5.a */
+
+  /* 5 */ {   127,   -128, 2,  6 }, /* jcnd16.b */
+  /* 6 */ { 32767, -32768, 5,  7 }, /* jcnd16.w */
+  /* 7 */ {     0,      0, 6,  0 }, /* jcnd16.a */
+
+  /* 8 */ {     8,      1, 1,  9 }, /* jmp16.s */
+  /* 9 */ {   127,   -128, 2, 10 }, /* jmp16.b */
+ /* 10 */ { 32767, -32768, 3, 11 }, /* jmp16.w */
+ /* 11 */ {     0,      0, 4,  0 }, /* jmp16.a */
+
+ /* 12 */ {   127,   -128, 2, 13 }, /* jcnd32.b */
+ /* 13 */ { 32767, -32768, 5, 14 }, /* jcnd32.w */
+ /* 14 */ {     0,      0, 6,  0 }, /* jcnd32.a */
+
+ /* 15 */ {     8,      1, 1, 16 }, /* jmp32.s */
+ /* 16 */ {   127,   -128, 2, 17 }, /* jmp32.b */
+ /* 17 */ { 32767, -32768, 3, 18 }, /* jmp32.w */
+ /* 18 */ {     0,      0, 4,  0 }, /* jmp32.a */
+
+ /* 19 */ { 32767, -32768, 3, 20 }, /* jsr16.w */
+ /* 20 */ {     0,      0, 4,  0 }, /* jsr16.a */
+ /* 21 */ { 32767, -32768, 3, 11 }, /* jsr32.w */
+ /* 22 */ {     0,      0, 4,  0 }  /* jsr32.a */
+};
+
+enum {
+  M32C_MACRO_JCND16_5_W,
+  M32C_MACRO_JCND16_5_A,
+  M32C_MACRO_JCND16_W,
+  M32C_MACRO_JCND16_A,
+  M32C_MACRO_JCND32_W,
+  M32C_MACRO_JCND32_A,
+} M32C_Macros;
+
+static struct {
+  int insn;
+  int bytes;
+  int insn_for_extern;
+  int pcrel_aim_offset;
+} subtype_mappings[] = {
+  /* 0 */ { 0, 0, 0, 0 },
+  /* 1 */ { 0, 0, 0, 0 },
+
+  /* 2 */ {  M32C_INSN_JCND16_5,    2, -M32C_MACRO_JCND16_5_A, 1 },
+  /* 3 */ { -M32C_MACRO_JCND16_5_W, 5, -M32C_MACRO_JCND16_5_A, 4 },
+  /* 4 */ { -M32C_MACRO_JCND16_5_A, 6, -M32C_MACRO_JCND16_5_A, 0 },
+
+  /* 5 */ {  M32C_INSN_JCND16,      3, -M32C_MACRO_JCND16_A,   1 },
+  /* 6 */ { -M32C_MACRO_JCND16_W,   6, -M32C_MACRO_JCND16_A,   4 },
+  /* 7 */ { -M32C_MACRO_JCND16_A,   7, -M32C_MACRO_JCND16_A,   0 },
+
+  /* 8 */ {  M32C_INSN_JMP16_S,     1, M32C_INSN_JMP16_A,     0 },
+  /* 9 */ {  M32C_INSN_JMP16_B,     2, M32C_INSN_JMP16_A,     1 },
+ /* 10 */ {  M32C_INSN_JMP16_W,     3, M32C_INSN_JMP16_A,     2 },
+ /* 11 */ {  M32C_INSN_JMP16_A,     4, M32C_INSN_JMP16_A,     0 },
+
+ /* 12 */ {  M32C_INSN_JCND32,      2, -M32C_MACRO_JCND32_A,   1 },
+ /* 13 */ { -M32C_MACRO_JCND32_W,   5, -M32C_MACRO_JCND32_A,   4 },
+ /* 14 */ { -M32C_MACRO_JCND32_A,   6, -M32C_MACRO_JCND32_A,   0 },
+
+ /* 15 */ {  M32C_INSN_JMP32_S,     1, M32C_INSN_JMP32_A,     0 },
+ /* 16 */ {  M32C_INSN_JMP32_B,     2, M32C_INSN_JMP32_A,     1 },
+ /* 17 */ {  M32C_INSN_JMP32_W,     3, M32C_INSN_JMP32_A,     2 },
+ /* 18 */ {  M32C_INSN_JMP32_A,     4, M32C_INSN_JMP32_A,     0 },
+
+ /* 19 */ {  M32C_INSN_JSR16_W,     3, M32C_INSN_JSR16_A,     2 },
+ /* 20 */ {  M32C_INSN_JSR16_A,     4, M32C_INSN_JSR16_A,     0 },
+ /* 21 */ {  M32C_INSN_JSR32_W,     3, M32C_INSN_JSR32_A,     2 },
+ /* 22 */ {  M32C_INSN_JSR32_A,     4, M32C_INSN_JSR32_A,     0 }
+};
+#define NUM_MAPPINGS (sizeof (subtype_mappings) / sizeof (subtype_mappings[0]))
+
+void
+m32c_prepare_relax_scan (fragS *fragP, offsetT *aim, relax_substateT this_state)
+{
+  symbolS *symbolP = fragP->fr_symbol;
+  if (symbolP && !S_IS_DEFINED (symbolP))
+    *aim = 0;
+  /* Adjust for m32c pcrel not being relative to the next opcode.  */
+  *aim += subtype_mappings[this_state].pcrel_aim_offset;
+}
+
+static int
+insn_to_subtype (int insn)
+{
+  unsigned int i;
+  for (i=0; i<NUM_MAPPINGS; i++)
+    if (insn == subtype_mappings[i].insn)
+      {
+	/*printf("mapping %d used\n", i);*/
+	return i;
+      }
+  abort ();
+}
+
+/* Return an initial guess of the length by which a fragment must grow to
+   hold a branch to reach its destination.
+   Also updates fr_type/fr_subtype as necessary.
+
+   Called just before doing relaxation.
+   Any symbol that is now undefined will not become defined.
+   The guess for fr_var is ACTUALLY the growth beyond fr_fix.
+   Whatever we do to grow fr_fix or fr_var contributes to our returned value.
+   Although it may not be explicit in the frag, pretend fr_var starts with a
+   0 value.  */
+
+int
+md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED)
+{
+  int where = fragP->fr_opcode - fragP->fr_literal;
+
+  if (fragP->fr_subtype == 1)
+    fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num);
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
+    {
+      int new_insn;
+
+      new_insn = subtype_mappings[fragP->fr_subtype].insn_for_extern;
+      fragP->fr_subtype = insn_to_subtype (new_insn);
+    }
+
+  if (fragP->fr_cgen.insn->base
+      && fragP->fr_cgen.insn->base->num
+         != subtype_mappings[fragP->fr_subtype].insn
+      && subtype_mappings[fragP->fr_subtype].insn > 0)
+    {
+      int new_insn= subtype_mappings[fragP->fr_subtype].insn;
+      if (new_insn >= 0)
+	{
+	  fragP->fr_cgen.insn = (fragP->fr_cgen.insn
+				 - fragP->fr_cgen.insn->base->num
+				 + new_insn);
+	}
+    }
+
+  return subtype_mappings[fragP->fr_subtype].bytes - (fragP->fr_fix - where);
+} 
+
+/* *fragP has been relaxed to its final size, and now needs to have
+   the bytes inside it modified to conform to the new size.
+
+   Called after relaxation is finished.
+   fragP->fr_type == rs_machine_dependent.
+   fragP->fr_subtype is the subtype of what the address relaxed to.  */
+
+static int
+target_address_for (fragS *frag)
+{
+  int rv = frag->fr_offset;
+  symbolS *sym = frag->fr_symbol;
+
+  if (sym)
+    rv += S_GET_VALUE (sym);
+
+  /*printf("target_address_for returns %d\n", rv);*/
+  return rv;
+}
+
+void
+md_convert_frag (bfd *   abfd ATTRIBUTE_UNUSED,
+		 segT    sec ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
+{
+  int addend;
+  int operand;
+  int new_insn;
+  int where = fragP->fr_opcode - fragP->fr_literal;
+  int rl_where = fragP->fr_opcode - fragP->fr_literal;
+  unsigned char *op = (unsigned char *)fragP->fr_opcode;
+  int op_base = 0;
+  int op_op = 0;
+  int rl_addend = 0;
+
+  addend = target_address_for (fragP) - (fragP->fr_address + where);
+  new_insn = subtype_mappings[fragP->fr_subtype].insn;
+
+  fragP->fr_fix = where + subtype_mappings[fragP->fr_subtype].bytes;
+
+  op_base = 0;
+
+  switch (subtype_mappings[fragP->fr_subtype].insn)
+    {
+    case M32C_INSN_JCND16_5:
+      op[1] = addend - 1;
+      operand = M32C_OPERAND_LAB_8_8;
+      op_op = 1;
+      rl_addend = 0x21;
+      break;
+
+    case -M32C_MACRO_JCND16_5_W:
+      op[0] ^= 0x04;
+      op[1] = 4;
+      op[2] = 0xf4;
+      op[3] = addend - 3;
+      op[4] = (addend - 3) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      where += 2;
+      new_insn = M32C_INSN_JMP16_W;
+      op_base = 2;
+      op_op = 3;
+      rl_addend = 0x51;
+      break;
+
+    case -M32C_MACRO_JCND16_5_A:
+      op[0] ^= 0x04;
+      op[1] = 5;
+      op[2] = 0xfc;
+      operand = M32C_OPERAND_LAB_8_24;
+      where += 2;
+      new_insn = M32C_INSN_JMP16_A;
+      op_base = 2;
+      op_op = 3;
+      rl_addend = 0x61;
+      break;
+
+
+    case M32C_INSN_JCND16:
+      op[2] = addend - 2;
+      operand = M32C_OPERAND_LAB_16_8;
+      op_base = 0;
+      op_op = 2;
+      rl_addend = 0x31;
+      break;
+
+    case -M32C_MACRO_JCND16_W:
+      op[1] ^= 0x04;
+      op[2] = 4;
+      op[3] = 0xf4;
+      op[4] = addend - 4;
+      op[5] = (addend - 4) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      where += 3;
+      new_insn = M32C_INSN_JMP16_W;
+      op_base = 3;
+      op_op = 4;
+      rl_addend = 0x61;
+      break;
+
+    case -M32C_MACRO_JCND16_A:
+      op[1] ^= 0x04;
+      op[2] = 5;
+      op[3] = 0xfc;
+      operand = M32C_OPERAND_LAB_8_24;
+      where += 3;
+      new_insn = M32C_INSN_JMP16_A;
+      op_base = 3;
+      op_op = 4;
+      rl_addend = 0x71;
+      break;
+
+    case M32C_INSN_JMP16_S:
+      op[0] = 0x60 | ((addend-2) & 0x07);
+      operand = M32C_OPERAND_LAB_5_3;
+      op_base = 0;
+      op_op = 0;
+      rl_addend = 0x10;
+      break;
+
+    case M32C_INSN_JMP16_B:
+      op[0] = 0xfe;
+      op[1] = addend - 1;
+      operand = M32C_OPERAND_LAB_8_8;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x21;
+      break;
+
+    case M32C_INSN_JMP16_W:
+      op[0] = 0xf4;
+      op[1] = addend - 1;
+      op[2] = (addend - 1) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x31;
+      break;
+
+    case M32C_INSN_JMP16_A:
+      op[0] = 0xfc;
+      op[1] = 0;
+      op[2] = 0;
+      op[3] = 0;
+      operand = M32C_OPERAND_LAB_8_24;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x41;
+      break;
+
+    case M32C_INSN_JCND32:
+      op[1] = addend - 1;
+      operand = M32C_OPERAND_LAB_8_8;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x21;
+      break;
+
+    case -M32C_MACRO_JCND32_W:
+      op[0] ^= 0x40;
+      op[1] = 4;
+      op[2] = 0xce;
+      op[3] = addend - 3;
+      op[4] = (addend - 3) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      where += 2;
+      new_insn = M32C_INSN_JMP32_W;
+      op_base = 2;
+      op_op = 3;
+      rl_addend = 0x51;
+      break;
+
+    case -M32C_MACRO_JCND32_A:
+      op[0] ^= 0x40;
+      op[1] = 5;
+      op[2] = 0xcc;
+      operand = M32C_OPERAND_LAB_8_24;
+      where += 2;
+      new_insn = M32C_INSN_JMP32_A;
+      op_base = 2;
+      op_op = 3;
+      rl_addend = 0x61;
+      break;
+
+
+
+    case M32C_INSN_JMP32_S:
+      addend = ((addend-2) & 0x07);
+      op[0] = 0x4a | (addend & 0x01) | ((addend << 3) & 0x30);
+      operand = M32C_OPERAND_LAB32_JMP_S;
+      op_base = 0;
+      op_op = 0;
+      rl_addend = 0x10;
+      break;
+
+    case M32C_INSN_JMP32_B:
+      op[0] = 0xbb;
+      op[1] = addend - 1;
+      operand = M32C_OPERAND_LAB_8_8;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x21;
+      break;
+
+    case M32C_INSN_JMP32_W:
+      op[0] = 0xce;
+      op[1] = addend - 1;
+      op[2] = (addend - 1) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x31;
+      break;
+
+    case M32C_INSN_JMP32_A:
+      op[0] = 0xcc;
+      op[1] = 0;
+      op[2] = 0;
+      op[3] = 0;
+      operand = M32C_OPERAND_LAB_8_24;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x41;
+      break;
+
+
+    case M32C_INSN_JSR16_W:
+      op[0] = 0xf5;
+      op[1] = addend - 1;
+      op[2] = (addend - 1) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x31;
+      break;
+
+    case M32C_INSN_JSR16_A:
+      op[0] = 0xfd;
+      op[1] = 0;
+      op[2] = 0;
+      op[3] = 0;
+      operand = M32C_OPERAND_LAB_8_24;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x41;
+      break;
+
+    case M32C_INSN_JSR32_W:
+      op[0] = 0xcf;
+      op[1] = addend - 1;
+      op[2] = (addend - 1) >> 8;
+      operand = M32C_OPERAND_LAB_8_16;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x31;
+      break;
+
+    case M32C_INSN_JSR32_A:
+      op[0] = 0xcd;
+      op[1] = 0;
+      op[2] = 0;
+      op[3] = 0;
+      operand = M32C_OPERAND_LAB_8_24;
+      op_base = 0;
+      op_op = 1;
+      rl_addend = 0x41;
+      break;
+
+
+
+    default:
+      printf("\nHey!  Need more opcode converters! missing: %d %s\n\n",
+	     fragP->fr_subtype,
+	     fragP->fr_cgen.insn->base->name);
+      abort();
+    }
+
+  if (m32c_relax)
+    {
+      if (operand != M32C_OPERAND_LAB_8_24)
+	fragP->fr_offset = (fragP->fr_address + where);
+
+      fix_new (fragP,
+	       rl_where,
+	       0, abs_section_sym, rl_addend, 0,
+	       BFD_RELOC_M32C_RL_JUMP);
+    }
+
+  if (S_GET_SEGMENT (fragP->fr_symbol) != sec
+      || operand == M32C_OPERAND_LAB_8_24
+      || (m32c_relax && (operand != M32C_OPERAND_LAB_5_3
+			 && operand != M32C_OPERAND_LAB32_JMP_S)))
+    {
+      assert (fragP->fr_cgen.insn != 0);
+      gas_cgen_record_fixup (fragP,
+			     where,
+			     fragP->fr_cgen.insn,
+			     (fragP->fr_fix - where) * 8,
+			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+							 operand),
+			     fragP->fr_cgen.opinfo,
+			     fragP->fr_symbol, fragP->fr_offset);
+    }
+}
+
+/* Functions concerning relocs.  */
+
+/* The location from which a PC relative jump should be calculated,
+   given a PC relative reloc.  */
+
+long
+md_pcrel_from_section (fixS * fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (! S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
+
+  return (fixP->fx_frag->fr_address + fixP->fx_where);
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP ATTRIBUTE_UNUSED)
+{
+  static const struct op_reloc {
+    /* A CGEN operand type that can be a relocatable expression.  */
+    CGEN_OPERAND_TYPE operand;
+
+    /* The appropriate BFD reloc type to use for that.  */
+    bfd_reloc_code_real_type reloc;
+
+    /* The offset from the start of the instruction to the field to be
+       relocated, in bytes.  */
+    int offset;
+  } op_reloc_table[] = {
+
+    /* PC-REL relocs for 8-bit fields.  */
+    { M32C_OPERAND_LAB_8_8,    BFD_RELOC_8_PCREL, 1 },
+    { M32C_OPERAND_LAB_16_8,   BFD_RELOC_8_PCREL, 2 },
+    { M32C_OPERAND_LAB_24_8,   BFD_RELOC_8_PCREL, 3 },
+    { M32C_OPERAND_LAB_32_8,   BFD_RELOC_8_PCREL, 4 },
+    { M32C_OPERAND_LAB_40_8,   BFD_RELOC_8_PCREL, 5 },
+
+    /* PC-REL relocs for 16-bit fields.  */
+    { M32C_OPERAND_LAB_8_16,   BFD_RELOC_16_PCREL, 1 },
+
+    /* Absolute relocs for 8-bit fields.  */
+    { M32C_OPERAND_IMM_8_QI,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_IMM_16_QI,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_IMM_24_QI,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_IMM_32_QI,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_IMM_40_QI,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_IMM_48_QI,  BFD_RELOC_8, 6 },
+    { M32C_OPERAND_IMM_56_QI,  BFD_RELOC_8, 7 },
+    { M32C_OPERAND_DSP_8_S8,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_DSP_16_S8,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_DSP_24_S8,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_DSP_32_S8,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_DSP_40_S8,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_DSP_48_S8,  BFD_RELOC_8, 6 },
+    { M32C_OPERAND_DSP_8_U8,   BFD_RELOC_8, 1 },
+    { M32C_OPERAND_DSP_16_U8,  BFD_RELOC_8, 2 },
+    { M32C_OPERAND_DSP_24_U8,  BFD_RELOC_8, 3 },
+    { M32C_OPERAND_DSP_32_U8,  BFD_RELOC_8, 4 },
+    { M32C_OPERAND_DSP_40_U8,  BFD_RELOC_8, 5 },
+    { M32C_OPERAND_DSP_48_U8,  BFD_RELOC_8, 6 },
+    { M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, BFD_RELOC_8, 2 },
+    { M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, BFD_RELOC_8, 2 },
+    { M32C_OPERAND_BITBASE32_24_S11_PREFIXED, BFD_RELOC_8, 3 },
+    { M32C_OPERAND_BITBASE32_24_U11_PREFIXED, BFD_RELOC_8, 3 },
+
+    /* Absolute relocs for 16-bit fields.  */
+    { M32C_OPERAND_IMM_8_HI,   BFD_RELOC_16, 1 },
+    { M32C_OPERAND_IMM_16_HI,  BFD_RELOC_16, 2 },
+    { M32C_OPERAND_IMM_24_HI,  BFD_RELOC_16, 3 },
+    { M32C_OPERAND_IMM_32_HI,  BFD_RELOC_16, 4 },
+    { M32C_OPERAND_IMM_40_HI,  BFD_RELOC_16, 5 },
+    { M32C_OPERAND_IMM_48_HI,  BFD_RELOC_16, 6 },
+    { M32C_OPERAND_IMM_56_HI,  BFD_RELOC_16, 7 },
+    { M32C_OPERAND_IMM_64_HI,  BFD_RELOC_16, 8 },
+    { M32C_OPERAND_DSP_16_S16, BFD_RELOC_16, 2 },
+    { M32C_OPERAND_DSP_24_S16, BFD_RELOC_16, 3 },
+    { M32C_OPERAND_DSP_32_S16, BFD_RELOC_16, 4 },
+    { M32C_OPERAND_DSP_40_S16, BFD_RELOC_16, 5 },
+    { M32C_OPERAND_DSP_8_U16,  BFD_RELOC_16, 1 },
+    { M32C_OPERAND_DSP_16_U16, BFD_RELOC_16, 2 },
+    { M32C_OPERAND_DSP_24_U16, BFD_RELOC_16, 3 },
+    { M32C_OPERAND_DSP_32_U16, BFD_RELOC_16, 4 },
+    { M32C_OPERAND_DSP_40_U16, BFD_RELOC_16, 5 },
+    { M32C_OPERAND_DSP_48_U16, BFD_RELOC_16, 6 },
+    { M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, BFD_RELOC_16, 2 },
+    { M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, BFD_RELOC_16, 2 },
+    { M32C_OPERAND_BITBASE32_24_S19_PREFIXED, BFD_RELOC_16, 3 },
+    { M32C_OPERAND_BITBASE32_24_U19_PREFIXED, BFD_RELOC_16, 3 },
+
+    /* Absolute relocs for 24-bit fields.  */
+    { M32C_OPERAND_LAB_8_24,   BFD_RELOC_24, 1 },
+    { M32C_OPERAND_DSP_8_S24,  BFD_RELOC_24, 1 },
+    { M32C_OPERAND_DSP_8_U24,  BFD_RELOC_24, 1 },
+    { M32C_OPERAND_DSP_16_U24, BFD_RELOC_24, 2 },
+    { M32C_OPERAND_DSP_24_U24, BFD_RELOC_24, 3 },
+    { M32C_OPERAND_DSP_32_U24, BFD_RELOC_24, 4 },
+    { M32C_OPERAND_DSP_40_U24, BFD_RELOC_24, 5 },
+    { M32C_OPERAND_DSP_48_U24, BFD_RELOC_24, 6 },
+    { M32C_OPERAND_DSP_16_U20, BFD_RELOC_24, 2 },
+    { M32C_OPERAND_DSP_24_U20, BFD_RELOC_24, 3 },
+    { M32C_OPERAND_DSP_32_U20, BFD_RELOC_24, 4 },
+    { M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, BFD_RELOC_24, 2 },
+    { M32C_OPERAND_BITBASE32_24_U27_PREFIXED, BFD_RELOC_24, 3 },
+
+    /* Absolute relocs for 32-bit fields.  */
+    { M32C_OPERAND_IMM_16_SI,  BFD_RELOC_32, 2 },
+    { M32C_OPERAND_IMM_24_SI,  BFD_RELOC_32, 3 },
+    { M32C_OPERAND_IMM_32_SI,  BFD_RELOC_32, 4 },
+    { M32C_OPERAND_IMM_40_SI,  BFD_RELOC_32, 5 },
+
+  };
+
+  int i;
+
+  for (i = ARRAY_SIZE (op_reloc_table); --i >= 0; )
+    {
+      const struct op_reloc *or = &op_reloc_table[i];
+
+      if (or->operand == operand->type)
+        {
+          fixP->fx_where += or->offset;
+          fixP->fx_size -= or->offset;
+
+	  if (fixP->fx_cgen.opinfo
+	      && fixP->fx_cgen.opinfo != BFD_RELOC_NONE)
+	    return fixP->fx_cgen.opinfo;
+
+          return or->reloc;
+        }
+    }
+
+  fprintf
+    (stderr,
+     "Error: tc-m32c.c:md_cgen_lookup_reloc Unimplemented relocation for operand %s\n",
+     operand->name);
+
+  return BFD_RELOC_NONE;
+}
+
+void
+m32c_apply_fix (struct fix *f, valueT *t, segT s)
+{
+  if (f->fx_r_type == BFD_RELOC_M32C_RL_JUMP
+      || f->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
+      || f->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
+    return;
+  gas_cgen_md_apply_fix (f, t, s);
+}
+
+arelent *
+tc_gen_reloc (asection *sec, fixS *fx)
+{
+  if (fx->fx_r_type == BFD_RELOC_M32C_RL_JUMP
+      || fx->fx_r_type == BFD_RELOC_M32C_RL_1ADDR
+      || fx->fx_r_type == BFD_RELOC_M32C_RL_2ADDR)
+    {
+      arelent * reloc;
+ 
+      reloc = xmalloc (sizeof (* reloc));
+ 
+      reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+      *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy);
+      reloc->address = fx->fx_frag->fr_address + fx->fx_where;
+      reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type);
+      reloc->addend = fx->fx_offset;
+      return reloc;
+
+    }
+  return gas_cgen_tc_gen_reloc (sec, fx);
+}
+
+/* See whether we need to force a relocation into the output file.
+   This is used to force out switch and PC relative relocations when
+   relaxing.  */
+
+int
+m32c_force_relocation (fixS * fixp)
+{
+  int reloc = fixp->fx_r_type;
+
+  if (reloc > (int)BFD_RELOC_UNUSED)
+    {
+      reloc -= (int)BFD_RELOC_UNUSED;
+      switch (reloc)
+	{
+	case M32C_OPERAND_DSP_32_S16:
+	case M32C_OPERAND_DSP_32_U16:
+	case M32C_OPERAND_IMM_32_HI:
+	case M32C_OPERAND_DSP_16_S16:
+	case M32C_OPERAND_DSP_16_U16:
+	case M32C_OPERAND_IMM_16_HI:
+	case M32C_OPERAND_DSP_24_S16:
+	case M32C_OPERAND_DSP_24_U16:
+	case M32C_OPERAND_IMM_24_HI:
+	  return 1;
+
+        /* If we're doing linker relaxing, we need to keep all the
+	   pc-relative jumps in case we need to fix them due to
+	   deleted bytes between the jump and its destination.  */
+	case M32C_OPERAND_LAB_8_8:
+	case M32C_OPERAND_LAB_8_16:
+	case M32C_OPERAND_LAB_8_24:
+	case M32C_OPERAND_LAB_16_8:
+	case M32C_OPERAND_LAB_24_8:
+	case M32C_OPERAND_LAB_32_8:
+	case M32C_OPERAND_LAB_40_8:
+	  if (m32c_relax)
+	    return 1;
+	default:
+	  break;
+	}
+    }
+  else
+    {
+      switch (fixp->fx_r_type)
+	{
+	case BFD_RELOC_16:
+	  return 1;
+
+	case BFD_RELOC_M32C_RL_JUMP:
+	case BFD_RELOC_M32C_RL_1ADDR:
+	case BFD_RELOC_M32C_RL_2ADDR:
+	case BFD_RELOC_8_PCREL:
+	case BFD_RELOC_16_PCREL:
+	  if (m32c_relax)
+	    return 1;
+	default:
+	  break;
+	}
+    }
+
+  return generic_force_reloc (fixp);
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+  number_to_chars_littleendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char * litP, int * sizeP)
+{
+  int              i;
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+   /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+
+    default:
+      * sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  for (i = 0; i < prec; i++)
+    {
+      md_number_to_chars (litP, (valueT) words[i],
+			  sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+     
+  return 0;
+}
+
+bfd_boolean
+m32c_fix_adjustable (fixS * fixP)
+{
+  int reloc;
+  if (fixP->fx_addsy == NULL)
+    return 1;
+
+  /* We need the symbol name for the VTABLE entries.  */
+  reloc = fixP->fx_r_type;
+  if (reloc > (int)BFD_RELOC_UNUSED)
+    {
+      reloc -= (int)BFD_RELOC_UNUSED;
+      switch (reloc)
+	{
+	case M32C_OPERAND_DSP_32_S16:
+	case M32C_OPERAND_DSP_32_U16:
+	case M32C_OPERAND_IMM_32_HI:
+	case M32C_OPERAND_DSP_16_S16:
+	case M32C_OPERAND_DSP_16_U16:
+	case M32C_OPERAND_IMM_16_HI:
+	case M32C_OPERAND_DSP_24_S16:
+	case M32C_OPERAND_DSP_24_U16:
+	case M32C_OPERAND_IMM_24_HI:
+	  return 0;
+	}
+    }
+  else
+    {
+      if (fixP->fx_r_type == BFD_RELOC_16)
+	return 0;
+    }
+
+  /* Do not adjust relocations involving symbols in merged sections.
+
+     A reloc patching in the value of some symbol S plus some addend A
+     can be produced in different ways:
+
+     1) It might simply be a reference to the data at S + A.  Clearly,
+        if linker merging shift that data around, the value patched in
+        by the reloc needs to be adjusted accordingly.
+
+     2) Or, it might be a reference to S, with A added in as a constant
+	bias.  For example, given code like this:
+
+	  static int S[100];
+
+	  ... S[i - 8] ...
+
+	it would be reasonable for the compiler to rearrange the array
+	reference to something like:
+
+	  ... (S-8)[i] ...
+
+	and emit assembly code that refers to S - (8 * sizeof (int)),
+	so the subtraction is done entirely at compile-time.  In this
+	case, the reloc's addend A would be -(8 * sizeof (int)), and
+	shifting around code or data at S + A should not affect the
+	reloc: the reloc isn't referring to that code or data at all.
+
+     The linker has no way of knowing which case it has in hand.  So,
+     to disambiguate, we have the linker always treat reloc addends as
+     in case 2): they're constants that should be simply added to the
+     symbol value, just like the reloc says.  And we express case 1)
+     in different way: we have the compiler place a label at the real
+     target, and reference that label with an addend of zero.  (The
+     compiler is unlikely to reference code using a label plus an
+     offset anyway, since it doesn't know the sizes of the
+     instructions.)
+
+     The simplification being done by gas/write.c:adjust_reloc_syms,
+     however, turns the explicit-label usage into the label-plus-
+     offset usage, re-introducing the ambiguity the compiler avoided.
+     So we need to disable that simplification for symbols referring
+     to merged data.
+
+     This only affects object size a little bit.  */
+  if (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE)
+    return 0;
+
+  if (m32c_relax)
+    return 0;
+
+  return 1;
+}
+
+/* Worker function for m32c_is_colon_insn().  */
+static char restore_colon PARAMS ((int));
+
+static char
+restore_colon (int advance_i_l_p_by)
+{
+  char c;
+
+  /* Restore the colon, and advance input_line_pointer to
+     the end of the new symbol.  */
+  * input_line_pointer = ':';
+  input_line_pointer += advance_i_l_p_by;
+  c = * input_line_pointer;
+  * input_line_pointer = 0;
+
+  return c;
+}
+
+/* Determines if the symbol starting at START and ending in
+   a colon that was at the location pointed to by INPUT_LINE_POINTER
+   (but which has now been replaced bu a NUL) is in fact an
+   :Z, :S, :Q, or :G suffix.
+   If it is, then it restores the colon, advances INPUT_LINE_POINTER
+   to the real end of the instruction/symbol, and returns the character
+   that really terminated the symbol.  Otherwise it returns 0.  */
+char
+m32c_is_colon_insn (char *start ATTRIBUTE_UNUSED)
+{
+  char * i_l_p = input_line_pointer;
+
+  /* Check to see if the text following the colon is 'G' */
+  if (TOLOWER (i_l_p[1]) == 'g' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
+    return restore_colon (2);
+
+  /* Check to see if the text following the colon is 'Q' */
+  if (TOLOWER (i_l_p[1]) == 'q' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
+    return restore_colon (2);
+
+  /* Check to see if the text following the colon is 'S' */
+  if (TOLOWER (i_l_p[1]) == 's' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
+    return restore_colon (2);
+
+  /* Check to see if the text following the colon is 'Z' */
+  if (TOLOWER (i_l_p[1]) == 'z' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
+    return restore_colon (2);
+
+  return 0;
+}
diff --git a/gas/config/tc-m32c.h b/gas/config/tc-m32c.h
new file mode 100644
index 000000000000..3cdd1a14e4f4
--- /dev/null
+++ b/gas/config/tc-m32c.h
@@ -0,0 +1,84 @@
+/* tc-m32c.h -- Header file for tc-m32c.c.
+   Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA. */
+
+#define TC_M32C
+
+#define LISTING_HEADER "M16C/M32C GAS "
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH bfd_arch_m32c
+
+#define TARGET_FORMAT "elf32-m32c"
+
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+#define md_end  m32c_md_end
+extern void m32c_md_end (void);
+
+#define md_start_line_hook m32c_start_line_hook
+extern void m32c_start_line_hook (void);
+
+/* call md_pcrel_from_section, not md_pcrel_from */
+long md_pcrel_from_section PARAMS ((struct fix *, segT));
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+
+/* Permit temporary numeric labels.  */
+#define LOCAL_LABELS_FB 1
+
+#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+
+/* We don't need to handle .word strangely.  */
+#define WORKING_DOT_WORD
+
+#define md_apply_fix m32c_apply_fix
+extern void m32c_apply_fix PARAMS ((struct fix *, valueT *, segT));
+
+#define tc_fix_adjustable(fixP) m32c_fix_adjustable (fixP)
+extern bfd_boolean m32c_fix_adjustable PARAMS ((struct fix *));
+
+/* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
+#define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix)
+extern int m32c_force_relocation PARAMS ((struct fix *));
+
+extern const struct relax_type md_relax_table[];
+#define TC_GENERIC_RELAX_TABLE md_relax_table
+
+extern void m32c_prepare_relax_scan PARAMS ((fragS *, offsetT *, relax_substateT state));
+#define md_prepare_relax_scan(FRAGP, ADDR, AIM, STATE, TYPE) \
+	m32c_prepare_relax_scan(FRAGP, &AIM, STATE)
+
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+
+/* We need a special version of the TC_START_LABEL macro so that we
+   allow the :Z, :S, :Q and :G suffixes to be
+   parsed as such.  Note - in a HORRIBLE HACK, we make use of the
+   knowledge that this marco is only ever evaluated in one place
+   (read_a_source_file in read.c) where we can access the local
+   variable 's' - the start of the symbol that was terminated by
+   'character'.  Also we need to be able to change the contents of
+   the local variable 'c' which is passed to this macro as 'character'.  */
+#define TC_START_LABEL(character, i_l_p)			\
+  ((character) != ':' ? 0 : (character = m32c_is_colon_insn (s)) ? 0 : ((character = ':'), 1))
+extern char m32c_is_colon_insn PARAMS ((char *));
diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c
index 919904fc15ab..51b160a98f76 100644
--- a/gas/config/tc-m32r.c
+++ b/gas/config/tc-m32r.c
@@ -1,5 +1,5 @@
 /* tc-m32r.c -- Assembler for the Renesas M32R.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -79,13 +79,6 @@ int pic_code;
    This flag does not apply to them.  */
 static int m32r_relax;
 
-#if 0
-/* Not supported yet.  */
-/* If non-NULL, pointer to cpu description file to read.
-   This allows runtime additions to the assembler.  */
-static const char *m32r_cpu_desc;
-#endif
-
 /* Non-zero if warn when a high/shigh reloc has no matching low reloc.
    Each high/shigh reloc must be paired with it's low cousin in order to
    properly calculate the addend in a relocatable link (since there is a
@@ -109,7 +102,7 @@ static int enable_special = 0;
 
 /* Non-zero if -bitinst has been specified, in which case support
    for extended M32R bit-field instruction set should be enabled.  */
-static int enable_special_m32r = 0;
+static int enable_special_m32r = 1;
 
 /* Non-zero if -float has been specified, in which case support for
    extended M32R floating point instruction set should be enabled.  */
@@ -173,7 +166,8 @@ struct m32r_hi_fixup
 
 static struct m32r_hi_fixup *m32r_hi_fixup_list;
 
-struct {
+struct
+{
   enum bfd_architecture bfd_mach;
   int mach_flags;
 } mach_table[] =
@@ -183,8 +177,6 @@ struct {
   { bfd_mach_m32r2, (1<<MACH_M32R2) }
 };
 
-static void allow_m32rx (int);
-
 static void
 allow_m32rx (int on)
 {
@@ -201,24 +193,29 @@ allow_m32rx (int on)
 
 const char *md_shortopts = M32R_SHORTOPTS;
 
+enum md_option_enums
+{
+  OPTION_M32R = OPTION_MD_BASE,
+  OPTION_M32RX,
+  OPTION_M32R2,
+  OPTION_BIG,
+  OPTION_LITTLE,
+  OPTION_PARALLEL,
+  OPTION_NO_PARALLEL,
+  OPTION_WARN_PARALLEL,
+  OPTION_NO_WARN_PARALLEL,
+  OPTION_IGNORE_PARALLEL,
+  OPTION_NO_IGNORE_PARALLEL,
+  OPTION_SPECIAL,
+  OPTION_SPECIAL_M32R,
+  OPTION_NO_SPECIAL_M32R,
+  OPTION_SPECIAL_FLOAT,
+  OPTION_WARN_UNMATCHED,
+  OPTION_NO_WARN_UNMATCHED
+};
+
 struct option md_longopts[] =
 {
-#define OPTION_M32R		  (OPTION_MD_BASE)
-#define OPTION_M32RX		  (OPTION_M32R + 1)
-#define OPTION_M32R2		  (OPTION_M32RX + 1)
-#define OPTION_BIG                (OPTION_M32R2 + 1)
-#define OPTION_LITTLE             (OPTION_BIG + 1)
-#define OPTION_PARALLEL           (OPTION_LITTLE + 1)
-#define OPTION_NO_PARALLEL        (OPTION_PARALLEL + 1)
-#define OPTION_WARN_PARALLEL	  (OPTION_NO_PARALLEL + 1)
-#define OPTION_NO_WARN_PARALLEL	  (OPTION_WARN_PARALLEL + 1)
-#define OPTION_IGNORE_PARALLEL    (OPTION_NO_WARN_PARALLEL + 1)
-#define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1)
-#define OPTION_SPECIAL		  (OPTION_NO_IGNORE_PARALLEL + 1)
-#define OPTION_SPECIAL_M32R       (OPTION_SPECIAL + 1)
-#define OPTION_SPECIAL_FLOAT      (OPTION_SPECIAL_M32R + 1)
-#define OPTION_WARN_UNMATCHED 	  (OPTION_SPECIAL_FLOAT + 1)
-#define OPTION_NO_WARN_UNMATCHED  (OPTION_WARN_UNMATCHED + 1)
   {"m32r",  no_argument, NULL, OPTION_M32R},
   {"m32rx", no_argument, NULL, OPTION_M32RX},
   {"m32r2", no_argument, NULL, OPTION_M32R2},
@@ -238,28 +235,18 @@ struct option md_longopts[] =
   {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL},
   {"hidden", no_argument, NULL, OPTION_SPECIAL},
   {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R},
+  {"no-bitinst", no_argument, NULL, OPTION_NO_SPECIAL_M32R},
   {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT},
   /* Sigh.  I guess all warnings must now have both variants.  */
   {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED},
   {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED},
   {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
   {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED},
-
-#if 0
-  /* Not supported yet.  */
-#define OPTION_RELAX		(OPTION_NO_WARN_UNMATCHED + 1)
-#define OPTION_CPU_DESC		(OPTION_RELAX + 1)
-  {"relax", no_argument, NULL, OPTION_RELAX},
-  {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC},
-#endif
   {NULL, no_argument, NULL, 0}
 };
 
 size_t md_longopts_size = sizeof (md_longopts);
 
-static void little (int);
-static int parallel (void);
-
 static void
 little (int on)
 {
@@ -281,9 +268,7 @@ parallel (void)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -353,6 +338,10 @@ md_parse_option (c, arg)
       enable_special_m32r = 1;
       break;
 
+    case OPTION_NO_SPECIAL_M32R:
+      enable_special_m32r = 0;
+      break;
+
     case OPTION_SPECIAL_FLOAT:
       enable_special_float = 1;
       break;
@@ -372,16 +361,6 @@ md_parse_option (c, arg)
         pic_code = 1;
       break;
 
-#if 0
-    /* Not supported yet.  */
-    case OPTION_RELAX:
-      m32r_relax = 1;
-      break;
-    case OPTION_CPU_DESC:
-      m32r_cpu_desc = arg;
-      break;
-#endif
-
     default:
       return 0;
     }
@@ -390,8 +369,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _(" M32R specific command line options:\n"));
 
@@ -410,6 +388,8 @@ md_show_usage (stream)
   fprintf (stream, _("\
   -no-parallel            disable -parallel\n"));
   fprintf (stream, _("\
+  -no-bitinst             disallow the M32R2's extended bit-field instructions\n"));
+  fprintf (stream, _("\
   -O                      try to optimize code.  Implies -parallel\n"));
 
   fprintf (stream, _("\
@@ -448,38 +428,74 @@ md_show_usage (stream)
 
   fprintf (stream, _("\
   -KPIC                   generate PIC\n"));
-
-#if 0
-  fprintf (stream, _("\
-  -relax                 create linker relaxable code\n"));
-  fprintf (stream, _("\
-  -cpu-desc              provide runtime cpu description file\n"));
-#endif
 }
 
-static void fill_insn PARAMS ((int));
-static void m32r_scomm PARAMS ((int));
-static void debug_sym PARAMS ((int));
-static void expand_debug_syms PARAMS ((sym_linkS *, int));
-
 /* Set by md_assemble for use by m32r_fill_insn.  */
 static subsegT prev_subseg;
 static segT prev_seg;
 
-/* The target specific pseudo-ops which we support.  */
-const pseudo_typeS md_pseudo_table[] =
+#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
+symbolS * GOT_symbol;
+
+static inline int
+m32r_PIC_related_p (symbolS *sym)
 {
-  { "word",	cons,		4 },
-  { "fillinsn", fill_insn,	0 },
-  { "scomm",	m32r_scomm,	0 },
-  { "debugsym",	debug_sym,	0 },
-  { "m32r",	allow_m32rx,	0 },
-  { "m32rx",	allow_m32rx,	1 },
-  { "m32r2",	allow_m32rx,	2 },
-  { "little",   little,         1 },
-  { "big",      little,         0 },
-  { NULL, NULL, 0 }
-};
+  expressionS *exp;
+
+  if (! sym)
+    return 0;
+
+  if (sym == GOT_symbol)
+    return 1;
+
+  exp = symbol_get_value_expression (sym);
+
+  return (exp->X_op == O_PIC_reloc
+          || exp->X_md == BFD_RELOC_M32R_26_PLTREL
+          || m32r_PIC_related_p (exp->X_add_symbol)
+          || m32r_PIC_related_p (exp->X_op_symbol));
+}
+
+static inline int
+m32r_check_fixup (expressionS *main_exp, bfd_reloc_code_real_type *r_type_p)
+{
+  expressionS *exp = main_exp;
+
+  if (exp->X_op == O_add && m32r_PIC_related_p (exp->X_op_symbol))
+    return 1;
+
+  if (exp->X_op == O_symbol && exp->X_add_symbol)
+    {
+      if (exp->X_add_symbol == GOT_symbol)
+        {
+          *r_type_p = BFD_RELOC_M32R_GOTPC24;
+          return 0;
+        }
+    }
+  else if (exp->X_op == O_add)
+    {
+      exp = symbol_get_value_expression (exp->X_add_symbol);
+      if (! exp)
+        return 0;
+    }
+
+  if (exp->X_op == O_PIC_reloc)
+    {
+      *r_type_p = exp->X_md;
+      if (exp == main_exp)
+        exp->X_op = O_symbol;
+      else
+       {
+          main_exp->X_add_symbol = exp->X_add_symbol;
+          main_exp->X_add_number += exp->X_add_number;
+       }
+    }
+  else
+    return (m32r_PIC_related_p (exp->X_add_symbol)
+            || m32r_PIC_related_p (exp->X_op_symbol));
+
+  return 0;
+}
 
 /* FIXME: Should be machine generated.  */
 #define NOP_INSN     0x7000
@@ -489,8 +505,7 @@ const pseudo_typeS md_pseudo_table[] =
    of an rs_align_code fragment.  */
 
 void
-m32r_handle_align (fragp)
-     fragS *fragp;
+m32r_handle_align (fragS *fragp)
 {
   static const unsigned char nop_pattern[] = { 0xf0, 0x00 };
   static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 };
@@ -536,8 +551,7 @@ m32r_handle_align (fragp)
    seen after an insn that is relaxable.  */
 
 static void
-fill_insn (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+fill_insn (int ignore ATTRIBUTE_UNUSED)
 {
   frag_align_code (2, 0);
   prev_insn.insn = NULL;
@@ -551,14 +565,13 @@ fill_insn (ignore)
    16 bit instruction.  */
 
 static void
-debug_sym (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+debug_sym (int ignore ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char delim;
-  register char *end_name;
-  register symbolS *symbolP;
-  register sym_linkS *link;
+  char *name;
+  char delim;
+  char *end_name;
+  symbolS *symbolP;
+  sym_linkS *link;
 
   name = input_line_pointer;
   delim = get_symbol_end ();
@@ -566,9 +579,7 @@ debug_sym (ignore)
 
   if ((symbolP = symbol_find (name)) == NULL
       && (symbolP = md_undefined_symbol (name)) == NULL)
-    {
-      symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
-    }
+    symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
 
   symbol_table_insert (symbolP);
   if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section
@@ -594,9 +605,7 @@ debug_sym (ignore)
    list of symbols and reassign the address.  */
 
 static void
-expand_debug_syms (syms, align)
-     sym_linkS *syms;
-     int align;
+expand_debug_syms (sym_linkS *syms, int align)
 {
   char *save_input_line = input_line_pointer;
   sym_linkS *next_syms;
@@ -618,7 +627,7 @@ expand_debug_syms (syms, align)
 }
 
 void
-m32r_flush_pending_output()
+m32r_flush_pending_output (void)
 {
   if (debug_sym_link)
     {
@@ -632,8 +641,7 @@ m32r_flush_pending_output()
    current line is a label.  */
 
 int
-m32r_fill_insn (done)
-     int done;
+m32r_fill_insn (int done)
 {
   if (prev_seg != NULL)
     {
@@ -659,7 +667,7 @@ m32r_fill_insn (done)
 /* The default target format to use.  */
 
 const char *
-m32r_target_format ()
+m32r_target_format (void)
 {
 #ifdef TE_LINUX
   if (target_big_endian)
@@ -675,7 +683,7 @@ m32r_target_format ()
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   flagword applicable;
   segT seg;
@@ -699,19 +707,6 @@ md_begin ()
   /* This is a callback from cgen to gas to parse operands.  */
   cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
 
-#if 0
-  /* Not supported yet.  */
-  /* If a runtime cpu description file was provided, parse it.  */
-  if (m32r_cpu_desc != NULL)
-    {
-      const char *errmsg;
-
-      errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc);
-      if (errmsg != NULL)
-	as_bad ("%s: %s", m32r_cpu_desc, errmsg);
-    }
-#endif
-
   /* Save the current subseg so we can restore it [it's the default one and
      we don't want the initial section to be .sbss].  */
   seg    = now_seg;
@@ -724,23 +719,18 @@ md_begin ()
   applicable = bfd_applicable_section_flags (stdoutput);
   bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC);
 
-#if 0
-  /* What does this do? [see perform_an_assembly_pass]  */
-  seg_info (bss_section)->bss = 1;
-#endif
-
   subseg_set (seg, subseg);
 
   /* We must construct a fake section similar to bfd_com_section
      but with the name .scommon.  */
   scom_section                = bfd_com_section;
   scom_section.name           = ".scommon";
-  scom_section.output_section = &scom_section;
-  scom_section.symbol         = &scom_symbol;
-  scom_section.symbol_ptr_ptr = &scom_section.symbol;
-  scom_symbol                 = *bfd_com_section.symbol;
+  scom_section.output_section = & scom_section;
+  scom_section.symbol         = & scom_symbol;
+  scom_section.symbol_ptr_ptr = & scom_section.symbol;
+  scom_symbol                 = * bfd_com_section.symbol;
   scom_symbol.name            = ".scommon";
-  scom_symbol.section         = &scom_section;
+  scom_symbol.section         = & scom_section;
 
   allow_m32rx (enable_m32rx);
 
@@ -757,14 +747,10 @@ md_begin ()
    of instruction 'b'.  If 'check_outputs' is true then b's outputs are
    checked, otherwise its inputs are examined.  */
 
-static int first_writes_to_seconds_operands
-  PARAMS ((m32r_insn *, m32r_insn *, const int));
-
 static int
-first_writes_to_seconds_operands (a, b, check_outputs)
-     m32r_insn *a;
-     m32r_insn *b;
-     const int check_outputs;
+first_writes_to_seconds_operands (m32r_insn *a,
+				  m32r_insn *b,
+				  const int check_outputs)
 {
   const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn);
   const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn);
@@ -837,46 +823,20 @@ first_writes_to_seconds_operands (a, b, check_outputs)
 
 /* Returns true if the insn can (potentially) alter the program counter.  */
 
-static int writes_to_pc PARAMS ((m32r_insn *));
-
 static int
-writes_to_pc (a)
-     m32r_insn *a;
+writes_to_pc (m32r_insn *a)
 {
-#if 0
-  /* Once PC operands are working....  */
-  const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
-						       a->insn);
-
-  if (a_operands == NULL)
-    return 0;
-
-  while (a_operands->type != CGEN_OPINST_END)
-    {
-      if (a_operands->operand != NULL
-	  && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc,
-				 a_operands->operand) == M32R_OPERAND_PC)
-	return 1;
-
-      a_operands++;
-    }
-#else
   if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
       || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
     return 1;
-#endif
   return 0;
 }
 
 /* Return NULL if the two 16 bit insns can be executed in parallel.
    Otherwise return a pointer to an error message explaining why not.  */
 
-static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *));
-
 static const char *
-can_make_parallel (a, b)
-     m32r_insn *a;
-     m32r_insn *b;
+can_make_parallel (m32r_insn *a, m32r_insn *b)
 {
   PIPE_ATTR a_pipe;
   PIPE_ATTR b_pipe;
@@ -910,11 +870,8 @@ can_make_parallel (a, b)
 
 /* Force the top bit of the second 16-bit insn to be set.  */
 
-static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR));
-
 static void
-make_parallel (buffer)
-     CGEN_INSN_BYTES_PTR buffer;
+make_parallel (CGEN_INSN_BYTES_PTR buffer)
 {
 #if CGEN_INT_INSN_P
   *buffer |= 0x8000;
@@ -926,11 +883,8 @@ make_parallel (buffer)
 
 /* Same as make_parallel except buffer contains the bytes in target order.  */
 
-static void target_make_parallel PARAMS ((char *));
-
 static void
-target_make_parallel (buffer)
-     char *buffer;
+target_make_parallel (char *buffer)
 {
   buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
     |= 0x80;
@@ -939,13 +893,8 @@ target_make_parallel (buffer)
 /* Assemble two instructions with an explicit parallel operation (||) or
    sequential operation (->).  */
 
-static void assemble_two_insns PARAMS ((char *, char *, int));
-
 static void
-assemble_two_insns (str, str2, parallel_p)
-     char *str;
-     char *str2;
-     int parallel_p;
+assemble_two_insns (char *str1, char *str2, int parallel_p)
 {
   char *str3;
   m32r_insn first;
@@ -969,7 +918,7 @@ assemble_two_insns (str, str2, parallel_p)
 
   /* Parse the first instruction.  */
   if (! (first.insn = m32r_cgen_assemble_insn
-	 (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
+	 (gas_cgen_cpu_desc, str1, & first.fields, first.buffer, & errmsg)))
     {
       as_bad (errmsg);
       return;
@@ -979,7 +928,7 @@ assemble_two_insns (str, str2, parallel_p)
   if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
     {
       /* xgettext:c-format  */
-      as_bad (_("not a 16 bit instruction '%s'"), str);
+      as_bad (_("not a 16 bit instruction '%s'"), str1);
       return;
     }
 #ifdef E_M32R2_ARCH
@@ -991,7 +940,7 @@ assemble_two_insns (str, str2, parallel_p)
                     & (1 << MACH_M32RX)))))
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' is for the M32R2 only"), str);
+      as_bad (_("instruction '%s' is for the M32R2 only"), str1);
       return;
     }
   else if ((! enable_special
@@ -1004,7 +953,7 @@ assemble_two_insns (str, str2, parallel_p)
 #endif
     {
       /* xgettext:c-format  */
-      as_bad (_("unknown instruction '%s'"), str);
+      as_bad (_("unknown instruction '%s'"), str1);
       return;
     }
   else if (! enable_m32rx
@@ -1013,7 +962,7 @@ assemble_two_insns (str, str2, parallel_p)
 	       == (1 << MACH_M32RX)))
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' is for the M32RX only"), str);
+      as_bad (_("instruction '%s' is for the M32RX only"), str1);
       return;
     }
 
@@ -1022,7 +971,7 @@ assemble_two_insns (str, str2, parallel_p)
       && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' cannot be executed in parallel."), str);
+      as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
       return;
     }
 
@@ -1030,10 +979,10 @@ assemble_two_insns (str, str2, parallel_p)
   *str2 = save_str2;
 
   /* Save the original string pointer.  */
-  str3 = str;
+  str3 = str1;
 
   /* Advanced past the parsed string.  */
-  str = str2 + 2;
+  str1 = str2 + 2;
 
   /* Remember the entire string in case it is needed for error
      messages.  */
@@ -1041,7 +990,7 @@ assemble_two_insns (str, str2, parallel_p)
 
   /* Convert the opcode to lower case.  */
   {
-    char *s2 = str;
+    char *s2 = str1;
 
     while (ISSPACE (*s2++))
       continue;
@@ -1083,7 +1032,7 @@ assemble_two_insns (str, str2, parallel_p)
 
   /* Parse the second instruction.  */
   if (! (second.insn = m32r_cgen_assemble_insn
-	 (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
+	 (gas_cgen_cpu_desc, str1, & second.fields, second.buffer, & errmsg)))
     {
       as_bad (errmsg);
       return;
@@ -1093,7 +1042,7 @@ assemble_two_insns (str, str2, parallel_p)
   if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
     {
       /* xgettext:c-format  */
-      as_bad (_("not a 16 bit instruction '%s'"), str);
+      as_bad (_("not a 16 bit instruction '%s'"), str1);
       return;
     }
 #ifdef E_M32R2_ARCH
@@ -1105,7 +1054,7 @@ assemble_two_insns (str, str2, parallel_p)
                     & (1 << MACH_M32RX)))))
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' is for the M32R2 only"), str);
+      as_bad (_("instruction '%s' is for the M32R2 only"), str1);
       return;
     }
   else if ((! enable_special
@@ -1118,14 +1067,14 @@ assemble_two_insns (str, str2, parallel_p)
 #endif
     {
       /* xgettext:c-format  */
-      as_bad (_("unknown instruction '%s'"), str);
+      as_bad (_("unknown instruction '%s'"), str1);
       return;
     }
   else if (! enable_m32rx
       && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' is for the M32RX only"), str);
+      as_bad (_("instruction '%s' is for the M32RX only"), str1);
       return;
     }
 
@@ -1134,7 +1083,7 @@ assemble_two_insns (str, str2, parallel_p)
       && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
     {
       /* xgettext:c-format  */
-      as_bad (_("instruction '%s' cannot be executed in parallel."), str);
+      as_bad (_("instruction '%s' cannot be executed in parallel."), str1);
       return;
     }
 
@@ -1244,8 +1193,7 @@ assemble_two_insns (str, str2, parallel_p)
 }
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   m32r_insn insn;
   char *errmsg;
@@ -1374,6 +1322,14 @@ md_assemble (str)
 	 prev_insn.insn is NULL when we're on a 32 bit boundary.  */
       on_32bit_boundary_p = prev_insn.insn == NULL;
 
+      /* Change a frag to, if each insn to swap is in a different frag.
+         It must keep only one instruction in a frag.  */
+      if (parallel() && on_32bit_boundary_p)
+        {
+          frag_wane (frag_now);
+          frag_new (0);
+        }
+
       /* Look to see if this instruction can be combined with the
 	 previous instruction to make one, parallel, 32 bit instruction.
 	 If the previous instruction (potentially) changed the flow of
@@ -1434,13 +1390,25 @@ md_assemble (str)
 	  else if (insn.frag->fr_opcode == insn.addr)
 	    insn.frag->fr_opcode = prev_insn.addr;
 
-	  /* Update the addresses in any fixups.
-	     Note that we don't have to handle the case where each insn is in
-	     a different frag as we ensure they're in the same frag above.  */
-	  for (i = 0; i < prev_insn.num_fixups; ++i)
-	    prev_insn.fixups[i]->fx_where += 2;
-	  for (i = 0; i < insn.num_fixups; ++i)
-	    insn.fixups[i]->fx_where -= 2;
+          /* Change a frag to, if each insn is in a different frag.
+	     It must keep only one instruction in a frag.  */
+          if (prev_insn.frag != insn.frag)
+            {
+              for (i = 0; i < prev_insn.num_fixups; ++i)
+                prev_insn.fixups[i]->fx_frag = insn.frag;
+              for (i = 0; i < insn.num_fixups; ++i)
+                insn.fixups[i]->fx_frag = prev_insn.frag;
+            }
+          else
+	    {
+	      /* Update the addresses in any fixups.
+		 Note that we don't have to handle the case where each insn is in
+		 a different frag as we ensure they're in the same frag above.  */
+	      for (i = 0; i < prev_insn.num_fixups; ++i)
+		prev_insn.fixups[i]->fx_where += 2;
+	      for (i = 0; i < insn.num_fixups; ++i)
+		insn.fixups[i]->fx_where -= 2;
+	    }
 	}
 
       /* Keep track of whether we've seen a pair of 16 bit insns.
@@ -1472,8 +1440,7 @@ md_assemble (str)
    We just ignore it.  */
 
 void
-md_operand (expressionP)
-     expressionS *expressionP;
+md_operand (expressionS *expressionP)
 {
   if (*input_line_pointer == '#')
     {
@@ -1483,17 +1450,15 @@ md_operand (expressionP)
 }
 
 valueT
-md_section_align (segment, size)
-     segT segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
+
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -1506,14 +1471,13 @@ md_undefined_symbol (name)
    correctly link the object file.  */
 
 static void
-m32r_scomm (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+m32r_scomm (int ignore ATTRIBUTE_UNUSED)
 {
-  register char *name;
-  register char c;
-  register char *p;
+  char *name;
+  char c;
+  char *p;
   offsetT size;
-  register symbolS *symbolP;
+  symbolS *symbolP;
   offsetT align;
   int align2;
 
@@ -1630,6 +1594,21 @@ m32r_scomm (ignore)
 
   demand_empty_rest_of_line ();
 }
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word",	cons,		4 },
+  { "fillinsn", fill_insn,	0 },
+  { "scomm",	m32r_scomm,	0 },
+  { "debugsym",	debug_sym,	0 },
+  { "m32r",	allow_m32rx,	0 },
+  { "m32rx",	allow_m32rx,	1 },
+  { "m32r2",	allow_m32rx,	2 },
+  { "little",   little,         1 },
+  { "big",      little,         0 },
+  { NULL, NULL, 0 }
+};
 
 /* Interface to relax_segment.  */
 
@@ -1662,10 +1641,7 @@ const relax_typeS md_relax_table[] =
 };
 
 long
-m32r_relax_frag (segment, fragP, stretch)
-     segT segment;
-     fragS *fragP;
-     long stretch;
+m32r_relax_frag (segT segment, fragS *fragP, long stretch)
 {
   /* Address of branch insn.  */
   long address = fragP->fr_address + fragP->fr_fix - 2;
@@ -1715,49 +1691,22 @@ m32r_relax_frag (segment, fragP, stretch)
    with a 0 value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP;
-     segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
 {
   /* The only thing we have to handle here are symbols outside of the
      current segment.  They may be undefined or in a different segment in
      which case linker scripts may place them anywhere.
      However, we can't finish the fragment here and emit the reloc as insn
      alignment requirements may move the insn about.  */
-
   if (S_GET_SEGMENT (fragP->fr_symbol) != segment
       || S_IS_EXTERNAL (fragP->fr_symbol)
       || S_IS_WEAK (fragP->fr_symbol))
     {
-#if 0
-      int old_fr_fix = fragP->fr_fix;
-#endif
-
       /* The symbol is undefined in this segment.
 	 Change the relaxation subtype to the max allowable and leave
 	 all further handling to md_convert_frag.  */
       fragP->fr_subtype = 2;
 
-#if 0
-      /* Can't use this, but leave in for illustration.  */
-      /* Change 16 bit insn to 32 bit insn.  */
-      fragP->fr_opcode[0] |= 0x80;
-
-      /* Increase known (fixed) size of fragment.  */
-      fragP->fr_fix += 2;
-
-      /* Create a relocation for it.  */
-      fix_new (fragP, old_fr_fix, 4,
-	       fragP->fr_symbol,
-	       fragP->fr_offset, 1 /* pcrel  */,
-	       /* FIXME: Can't use a real BFD reloc here.
-		  gas_cgen_md_apply_fix3 can't handle it.  */
-	       BFD_RELOC_M32R_26_PCREL);
-
-      /* Mark this fragment as finished.  */
-      frag_wane (fragP);
-      return fragP->fr_fix - old_fr_fix;
-#else
       {
 	const CGEN_INSN *insn;
 	int i;
@@ -1780,7 +1729,6 @@ md_estimate_size_before_relax (fragP, segment)
 	fragP->fr_cgen.insn = insn;
 	return 2;
       }
-#endif
     }
 
   return md_relax_table[fragP->fr_subtype].rlx_length;
@@ -1794,10 +1742,9 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec,
+		 fragS *fragP)
 {
   char *opcode;
   char *displacement;
@@ -1860,23 +1807,23 @@ md_convert_frag (abfd, sec, fragP)
       || S_IS_EXTERNAL (fragP->fr_symbol)
       || S_IS_WEAK (fragP->fr_symbol))
     {
+      fixS *fixP;
+
       assert (fragP->fr_subtype != 1);
       assert (fragP->fr_cgen.insn != 0);
-      gas_cgen_record_fixup (fragP,
-			     /* Offset of branch insn in frag.  */
-			     fragP->fr_fix + extension - 4,
-			     fragP->fr_cgen.insn,
-			     4 /* Length.  */,
-			     /* FIXME: quick hack.  */
-#if 0
-			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
-							 fragP->fr_cgen.opindex),
-#else
-			     cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
-							 M32R_OPERAND_DISP24),
-#endif
-			     fragP->fr_cgen.opinfo,
-			     fragP->fr_symbol, fragP->fr_offset);
+
+      fixP = gas_cgen_record_fixup (fragP,
+				    /* Offset of branch insn in frag.  */
+				    fragP->fr_fix + extension - 4,
+				    fragP->fr_cgen.insn,
+				    4 /* Length.  */,
+				    /* FIXME: quick hack.  */
+				    cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
+								M32R_OPERAND_DISP24),
+				    fragP->fr_cgen.opinfo,
+				    fragP->fr_symbol, fragP->fr_offset);
+      if (fragP->fr_cgen.opinfo)
+        fixP->fx_r_type = fragP->fr_cgen.opinfo;
     }
 
 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3)
@@ -1893,9 +1840,7 @@ md_convert_frag (abfd, sec, fragP)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS *fixP;
-     segT sec;
+md_pcrel_from_section (fixS *fixP, segT sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
@@ -1903,6 +1848,12 @@ md_pcrel_from_section (fixP, sec)
           || S_IS_EXTERNAL (fixP->fx_addsy)
           || S_IS_WEAK (fixP->fx_addsy)))
     {
+      if (S_GET_SEGMENT (fixP->fx_addsy) != sec
+          && S_IS_DEFINED (fixP->fx_addsy)
+          && ! S_IS_EXTERNAL (fixP->fx_addsy)
+          && ! S_IS_WEAK (fixP->fx_addsy))
+        return fixP->fx_offset;
+
       /* The symbol is undefined (or is defined but not in this section).
 	 Let the linker figure it out.  */
       return 0;
@@ -1916,10 +1867,9 @@ md_pcrel_from_section (fixP, sec)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND *operand;
-     fixS *fixP;
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND *operand,
+		      fixS *fixP)
 {
   switch (operand->type)
     {
@@ -1943,21 +1893,17 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 
 /* Record a HI16 reloc for later matching with its LO16 cousin.  */
 
-static void m32r_record_hi16 PARAMS ((int, fixS *, segT));
-
 static void
-m32r_record_hi16 (reloc_type, fixP, seg)
-     int reloc_type;
-     fixS *fixP;
-     segT seg ATTRIBUTE_UNUSED;
+m32r_record_hi16 (int reloc_type,
+		  fixS *fixP,
+		  segT seg ATTRIBUTE_UNUSED)
 {
   struct m32r_hi_fixup *hi_fixup;
 
   assert (reloc_type == BFD_RELOC_M32R_HI16_SLO
 	  || reloc_type == BFD_RELOC_M32R_HI16_ULO);
 
-  hi_fixup = ((struct m32r_hi_fixup *)
-	      xmalloc (sizeof (struct m32r_hi_fixup)));
+  hi_fixup = xmalloc (sizeof (* hi_fixup));
   hi_fixup->fixp = fixP;
   hi_fixup->seg  = now_seg;
   hi_fixup->next = m32r_hi_fixup_list;
@@ -1969,17 +1915,22 @@ m32r_record_hi16 (reloc_type, fixP, seg)
    We need to check for HI16 relocs and queue them up for later sorting.  */
 
 fixS *
-m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
-     fragS *frag;
-     int where;
-     const CGEN_INSN *insn;
-     int length;
-     const CGEN_OPERAND *operand;
-     int opinfo;
-     expressionS *exp;
+m32r_cgen_record_fixup_exp (fragS *frag,
+			    int where,
+			    const CGEN_INSN *insn,
+			    int length,
+			    const CGEN_OPERAND *operand,
+			    int opinfo,
+			    expressionS *exp)
 {
-  fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
-					  operand, opinfo, exp);
+  fixS *fixP;
+  bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED;
+
+  if (m32r_check_fixup (exp, &r_type))
+    as_bad (_("Invalid PIC expression."));
+
+  fixP = gas_cgen_record_fixup_exp (frag, where, insn, length,
+				    operand, opinfo, exp);
 
   switch (operand->type)
     {
@@ -1989,11 +1940,52 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
 	  || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
 	m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg);
       break;
+
     default:
-      /* Avoid -Wall warning */
+      /* Avoid -Wall warning.  */
       break;
     }
 
+  switch (r_type)
+    {
+    case BFD_RELOC_UNUSED:
+    default:
+      return fixP;
+
+    case BFD_RELOC_M32R_GOTPC24:
+      if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
+        r_type = BFD_RELOC_M32R_GOTPC_HI_SLO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
+        r_type = BFD_RELOC_M32R_GOTPC_HI_ULO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
+        r_type = BFD_RELOC_M32R_GOTPC_LO;
+      break;
+
+    case BFD_RELOC_M32R_GOT24:
+      if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
+        r_type = BFD_RELOC_M32R_GOT16_HI_SLO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
+        r_type = BFD_RELOC_M32R_GOT16_HI_ULO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
+        r_type = BFD_RELOC_M32R_GOT16_LO;
+      break;
+
+    case BFD_RELOC_M32R_GOTOFF:
+      if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO)
+        r_type = BFD_RELOC_M32R_GOTOFF_HI_SLO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO)
+        r_type = BFD_RELOC_M32R_GOTOFF_HI_ULO;
+      else if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_LO16)
+        r_type = BFD_RELOC_M32R_GOTOFF_LO;
+      break;
+
+    case BFD_RELOC_M32R_26_PLTREL:
+      as_bad (_("Invalid PIC expression."));
+      break;
+    }
+
+  fixP->fx_r_type = r_type;
+
   return fixP;
 }
 
@@ -2003,11 +1995,11 @@ m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo)
 
 /* Sort any unmatched HI16 relocs so that they immediately precede
-   the corresponding LO16 reloc.  This is called before md_apply_fix3 and
+   the corresponding LO16 reloc.  This is called before md_apply_fix and
    tc_gen_reloc.  */
 
 void
-m32r_frob_file ()
+m32r_frob_file (void)
 {
   struct m32r_hi_fixup *l;
 
@@ -2089,8 +2081,7 @@ m32r_frob_file ()
    relaxing.  */
 
 int
-m32r_force_relocation (fix)
-     fixS *fix;
+m32r_force_relocation (fixS *fix)
 {
   if (generic_force_reloc (fix))
     return 1;
@@ -2104,10 +2095,7 @@ m32r_force_relocation (fix)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -2124,10 +2112,7 @@ md_number_to_chars (buf, val, n)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int i;
   int prec;
@@ -2186,7 +2171,7 @@ md_atof (type, litP, sizeP)
 }
 
 void
-m32r_elf_section_change_hook ()
+m32r_elf_section_change_hook (void)
 {
   /* If we have reached the end of a section and we have just emitted a
      16 bit insn, then emit a nop to make sure that the section ends on
@@ -2200,8 +2185,7 @@ m32r_elf_section_change_hook ()
    (such as .data) instead of relative to some symbol.  */
 
 bfd_boolean
-m32r_fix_adjustable (fixP)
-   fixS *fixP;
+m32r_fix_adjustable (fixS *fixP)
 {
   bfd_reloc_code_real_type reloc_type;
 
@@ -2211,6 +2195,7 @@ m32r_fix_adjustable (fixP)
       int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
       const CGEN_OPERAND *operand =
 	cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+
       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
     }
   else
@@ -2220,7 +2205,7 @@ m32r_fix_adjustable (fixP)
     return 1;
 
   /* Prevent all adjustments to global symbols.  */
-  if (S_IS_EXTERN (fixP->fx_addsy))
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
     return 0;
   if (S_IS_WEAK (fixP->fx_addsy))
     return 0;
@@ -2233,6 +2218,16 @@ m32r_fix_adjustable (fixP)
           || reloc_type == BFD_RELOC_M32R_LO16))
     return 0;
 
+  if (reloc_type == BFD_RELOC_M32R_GOT24
+      || reloc_type == BFD_RELOC_M32R_26_PLTREL
+      || reloc_type == BFD_RELOC_M32R_GOTPC_HI_SLO
+      || reloc_type == BFD_RELOC_M32R_GOTPC_HI_ULO
+      || reloc_type == BFD_RELOC_M32R_GOTPC_LO
+      || reloc_type == BFD_RELOC_M32R_GOT16_HI_SLO
+      || reloc_type == BFD_RELOC_M32R_GOT16_HI_ULO
+      || reloc_type == BFD_RELOC_M32R_GOT16_LO)
+    return 0;
+
   /* We need the symbol name for the VTABLE entries.  */
   if (reloc_type == BFD_RELOC_VTABLE_INHERIT
       || reloc_type == BFD_RELOC_VTABLE_ENTRY)
@@ -2242,30 +2237,38 @@ m32r_fix_adjustable (fixP)
 }
 
 void
-m32r_elf_final_processing ()
+m32r_elf_final_processing (void)
 {
   if (use_parallel)
     m32r_flags |= E_M32R_HAS_PARALLEL;
   elf_elfheader (stdoutput)->e_flags |= m32r_flags;
 }
 
-#define GOT_NAME "_GLOBAL_OFFSET_TABLE_"
- 
 /* Translate internal representation of relocation info to BFD target
    format. */
+
 arelent *
-tc_gen_reloc (section, fixP)
-     asection * section;
-     fixS *     fixP;
+tc_gen_reloc (asection * section, fixS * fixP)
 {
   arelent * reloc;
   bfd_reloc_code_real_type code;
  
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (* reloc));
  
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+
+  if (fixP->fx_pcrel)
+    {
+      if (fixP->fx_r_type == BFD_RELOC_32)
+        fixP->fx_r_type = BFD_RELOC_32_PCREL;
+      else if (fixP->fx_r_type == BFD_RELOC_16)
+	{
+          fixP->fx_r_type = BFD_RELOC_16_PCREL;
+          bfd_set_error (bfd_error_bad_value);
+	}
+    }
  
   code = fixP->fx_r_type;
   if (pic_code)
@@ -2278,6 +2281,7 @@ printf("%s",bfd_get_reloc_code_name(code));
         case BFD_RELOC_M32R_26_PCREL:
             code = BFD_RELOC_M32R_26_PLTREL;
           break;
+
         case BFD_RELOC_M32R_24:
           if (fixP->fx_addsy != NULL
               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2285,6 +2289,7 @@ printf("%s",bfd_get_reloc_code_name(code));
           else
             code = BFD_RELOC_M32R_GOT24;
           break;
+
         case BFD_RELOC_M32R_HI16_ULO:
           if (fixP->fx_addsy != NULL
               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2292,6 +2297,7 @@ printf("%s",bfd_get_reloc_code_name(code));
           else
             code = BFD_RELOC_M32R_GOT16_HI_ULO;
           break;
+
         case BFD_RELOC_M32R_HI16_SLO:
           if (fixP->fx_addsy != NULL
               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2299,6 +2305,7 @@ printf("%s",bfd_get_reloc_code_name(code));
           else
             code = BFD_RELOC_M32R_GOT16_HI_SLO;
           break;
+
         case BFD_RELOC_M32R_LO16:
           if (fixP->fx_addsy != NULL
               && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0)
@@ -2306,6 +2313,7 @@ printf("%s",bfd_get_reloc_code_name(code));
           else
             code = BFD_RELOC_M32R_GOT16_LO;
           break;
+
         default:
           break;
         }
@@ -2315,10 +2323,12 @@ printf(" => %s",bfd_get_reloc_code_name(code));
     }
  
   reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
+
 #ifdef DEBUG_PIC
 printf(" => %s\n",reloc->howto->name);
 #endif
-  if (reloc->howto == (reloc_howto_type *) NULL)
+
+ if (reloc->howto == (reloc_howto_type *) NULL)
     {
       as_bad_where (fixP->fx_file, fixP->fx_line,
             _("internal error: can't export reloc type %d (`%s')"),
@@ -2326,21 +2336,128 @@ printf(" => %s\n",reloc->howto->name);
       return NULL;
     }
  
-  /* Use fx_offset for these cases */
+  /* Use fx_offset for these cases.  */
   if (   fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
-      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+      || fixP->fx_r_type == BFD_RELOC_32_PCREL)
     reloc->addend  = fixP->fx_offset;
-  else if (!pic_code
+  else if ((!pic_code
+            && code != BFD_RELOC_M32R_26_PLTREL)
            && fixP->fx_pcrel
            && fixP->fx_addsy != NULL
            && (S_GET_SEGMENT(fixP->fx_addsy) != section)
            && S_IS_DEFINED (fixP->fx_addsy)
            && ! S_IS_EXTERNAL(fixP->fx_addsy)
            && ! S_IS_WEAK(fixP->fx_addsy))
-    /* already used fx_offset in the opcode field itseld. */
-    reloc->addend  = 0;
+    /* Already used fx_offset in the opcode field itseld.  */
+    reloc->addend  = fixP->fx_offset;
   else
     reloc->addend  = fixP->fx_addnumber;
  
   return reloc;
 }
+
+inline static char *
+m32r_end_of_match (char *cont, char *what)
+{
+  int len = strlen (what);
+
+  if (strncasecmp (cont, what, strlen (what)) == 0
+      && ! is_part_of_name (cont[len]))
+    return cont + len;
+
+  return NULL;
+}
+
+int
+m32r_parse_name (char const *name,
+		 expressionS *exprP,
+		 enum expr_mode mode,
+		 char *nextcharP)
+{
+  char *next = input_line_pointer;
+  char *next_end;
+  int reloc_type;
+  operatorT op_type;
+  segT segment;
+
+  exprP->X_op_symbol = NULL;
+  exprP->X_md = BFD_RELOC_UNUSED;
+
+  if (strcmp (name, GOT_NAME) == 0)
+    {
+      if (! GOT_symbol)
+	GOT_symbol = symbol_find_or_make (name);
+
+      exprP->X_add_symbol = GOT_symbol;
+    no_suffix:
+      /* If we have an absolute symbol or a
+	 reg, then we know its value now.  */
+      segment = S_GET_SEGMENT (exprP->X_add_symbol);
+      if (mode != expr_defer && segment == absolute_section)
+	{
+	  exprP->X_op = O_constant;
+	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
+	  exprP->X_add_symbol = NULL;
+	}
+      else if (mode != expr_defer && segment == reg_section)
+	{
+	  exprP->X_op = O_register;
+	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
+	  exprP->X_add_symbol = NULL;
+	}
+      else
+	{
+	  exprP->X_op = O_symbol;
+	  exprP->X_add_number = 0;
+	}
+
+      return 1;
+    }
+
+  exprP->X_add_symbol = symbol_find_or_make (name);
+
+  if (*nextcharP != '@')
+    goto no_suffix;
+  else if ((next_end = m32r_end_of_match (next + 1, "GOTOFF")))
+    {
+      reloc_type = BFD_RELOC_M32R_GOTOFF;
+      op_type = O_PIC_reloc;
+    }
+  else if ((next_end = m32r_end_of_match (next + 1, "GOT")))
+    {
+      reloc_type = BFD_RELOC_M32R_GOT24;
+      op_type = O_PIC_reloc;
+    }
+  else if ((next_end = m32r_end_of_match (next + 1, "PLT")))
+    {
+      reloc_type = BFD_RELOC_M32R_26_PLTREL;
+      op_type = O_PIC_reloc;
+    }
+  else
+    goto no_suffix;
+
+  *input_line_pointer = *nextcharP;
+  input_line_pointer = next_end;
+  *nextcharP = *input_line_pointer;
+  *input_line_pointer = '\0';
+
+  exprP->X_op = op_type;
+  exprP->X_add_number = 0;
+  exprP->X_md = reloc_type;
+
+  return 1;
+}
+
+int
+m32r_cgen_parse_fix_exp(int opinfo, expressionS *exp)
+{
+  if (exp->X_op == O_PIC_reloc
+      && exp->X_md == BFD_RELOC_M32R_26_PLTREL)
+    {
+      exp->X_op = O_symbol;
+      opinfo = exp->X_md;
+    }
+
+  return opinfo;
+}
diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h
index 476921464180..69fe9453cc36 100644
--- a/gas/config/tc-m32r.h
+++ b/gas/config/tc-m32r.h
@@ -1,5 +1,5 @@
 /* tc-m32r.h -- Header file for tc-m32r.c.
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,16 +16,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_M32R
 
-#ifndef BFD_ASSEMBLER
-/* Leading space so will compile with cc.  */
- #error M32R support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER \
   (target_big_endian ? "M32R GAS" : "M32R GAS Little Endian")
 
@@ -35,7 +30,7 @@
 /* The endianness of the target format may change based on command
    line arguments.  */
 #define TARGET_FORMAT m32r_target_format()
-extern const char *m32r_target_format PARAMS ((void));
+extern const char *m32r_target_format (void);
 
 /* Default to big endian.  */
 #ifndef TARGET_BYTES_BIG_ENDIAN
@@ -43,13 +38,13 @@ extern const char *m32r_target_format PARAMS ((void));
 #endif
 
 /* Call md_pcrel_from_section, not md_pcrel_from.  */
-long md_pcrel_from_section PARAMS ((struct fix *, segT));
+long md_pcrel_from_section (struct fix *, segT);
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
+#define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs.  */
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
@@ -57,43 +52,37 @@ long md_pcrel_from_section PARAMS ((struct fix *, segT));
 /* For 8 vs 16 vs 32 bit branch selection.  */
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
-#if 0
-extern void m32r_prepare_relax_scan ();
-#define md_prepare_relax_scan(fragP, address, aim, this_state, this_type) \
-m32r_prepare_relax_scan (fragP, address, aim, this_state, this_type)
-#else
-extern long m32r_relax_frag PARAMS ((segT, fragS *, long));
+
+extern long m32r_relax_frag (segT, fragS *, long);
 #define md_relax_frag(segment, fragP, stretch) \
-m32r_relax_frag (segment, fragP, stretch)
-#endif
+  m32r_relax_frag (segment, fragP, stretch)
+
 /* Account for nop if 32 bit insn falls on odd halfword boundary.  */
-#define TC_CGEN_MAX_RELAX(insn, len) (6)
+#define TC_CGEN_MAX_RELAX(insn, len)	6
 
 /* Fill in rs_align_code fragments.  */
-extern void m32r_handle_align PARAMS ((fragS *));
+extern void m32r_handle_align (fragS *);
 #define HANDLE_ALIGN(f)  m32r_handle_align (f)
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2 + 4)
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define md_apply_fix3 gas_cgen_md_apply_fix3
+#define md_apply_fix gas_cgen_md_apply_fix
 
 #define tc_fix_adjustable(FIX) m32r_fix_adjustable (FIX)
-bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
+bfd_boolean m32r_fix_adjustable (struct fix *);
 
 /* After creating a fixup for an instruction operand, we need to check for
    HI16 relocs and queue them up for later sorting.  */
 #define md_cgen_record_fixup_exp m32r_cgen_record_fixup_exp
 
-/* #define tc_gen_reloc gas_cgen_tc_gen_reloc */
-
 #define TC_HANDLES_FX_DONE
 
 extern int pic_code;
 
-extern bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
+extern bfd_boolean m32r_fix_adjustable (struct fix *);
 
 /* This arranges for gas/write.c to not apply a relocation if
    obj_fix_adjustable() says it is not adjustable.  */
@@ -107,7 +96,7 @@ extern bfd_boolean m32r_fix_adjustable PARAMS ((struct fix *));
         && ! S_IS_COMMON ((FIX)->fx_addsy)))
 
 #define tc_frob_file_before_fix() m32r_frob_file ()
-extern void m32r_frob_file PARAMS ((void));
+extern void m32r_frob_file (void);
 
 /* No shared lib support, so we don't need to ensure externally
    visible symbols can be overridden.
@@ -115,19 +104,31 @@ extern void m32r_frob_file PARAMS ((void));
 
 /* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
 #define TC_FORCE_RELOCATION(fix) m32r_force_relocation (fix)
-extern int m32r_force_relocation PARAMS ((struct fix *));
+extern int m32r_force_relocation (struct fix *);
 
 /* Ensure insns at labels are aligned to 32 bit boundaries.  */
-int m32r_fill_insn PARAMS ((int));
+int m32r_fill_insn (int);
 #define md_after_pass_hook()	m32r_fill_insn (1)
 #define TC_START_LABEL(ch, ptr)	(ch == ':' && m32r_fill_insn (0))
 
 #define md_cleanup                 m32r_elf_section_change_hook
 #define md_elf_section_change_hook m32r_elf_section_change_hook
-extern void m32r_elf_section_change_hook PARAMS ((void));
+extern void m32r_elf_section_change_hook (void);
 
 #define md_flush_pending_output()       m32r_flush_pending_output ()
-extern void m32r_flush_pending_output PARAMS ((void));
+extern void m32r_flush_pending_output (void);
                                                                                   
 #define elf_tc_final_processing 	m32r_elf_final_processing
-extern void m32r_elf_final_processing PARAMS ((void));
+extern void m32r_elf_final_processing (void);
+
+#define md_parse_name(name, exprP, mode, nextcharP) \
+  m32r_parse_name ((name), (exprP), (mode), (nextcharP))
+extern int m32r_parse_name (char const *, expressionS *, enum expr_mode, char *);
+
+/* This is used to construct expressions out of @GOTOFF, @PLT and @GOT
+   symbols.  The relocation type is stored in X_md.  */
+#define O_PIC_reloc O_md1
+
+#define TC_CGEN_PARSE_FIX_EXP(opinfo, exp) \
+  m32r_cgen_parse_fix_exp(opinfo, exp)
+extern int m32r_cgen_parse_fix_exp (int, expressionS *);
diff --git a/gas/config/tc-m68851.h b/gas/config/tc-m68851.h
index 870e8810d0f2..0374861a9cbe 100644
--- a/gas/config/tc-m68851.h
+++ b/gas/config/tc-m68851.h
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*
  * pmmu.h
diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c
index 780f773fc91b..e6d4235d7699 100644
--- a/gas/config/tc-m68hc11.c
+++ b/gas/config/tc-m68hc11.c
@@ -1,5 +1,6 @@
 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12.
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
    Written by Stephane Carrez (stcarrez@nerim.fr)
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include "as.h"
 #include "safe-ctype.h"
@@ -2449,8 +2450,8 @@ md_assemble (char *str)
   struct m68hc11_opcode_def *opc;
   struct m68hc11_opcode *opcode;
 
-  unsigned char *op_start, *save;
-  unsigned char *op_end;
+  unsigned char *op_start, *op_end;
+  char *save;
   char name[20];
   int nlen = 0;
   operand operands[M6811_MAX_OPERANDS];
@@ -2464,7 +2465,7 @@ md_assemble (char *str)
 
   /* Find the opcode end and get the opcode in 'name'.  The opcode is forced
      lower case (the opcode table only has lower case op-codes).  */
-  for (op_start = op_end = (unsigned char *) (str);
+  for (op_start = op_end = (unsigned char *) str;
        *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
        op_end++)
     {
@@ -2544,7 +2545,7 @@ md_assemble (char *str)
       return;
     }
   save = input_line_pointer;
-  input_line_pointer = op_end;
+  input_line_pointer = (char *) op_end;
 
   if (opc)
     {
@@ -3227,7 +3228,7 @@ tc_m68hc11_fix_adjustable (fixS *fixP)
 }
 
 void
-md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *where;
   long value = * valP;
@@ -3281,16 +3282,10 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_M68HC11_LO8:
     case BFD_RELOC_8:
     case BFD_RELOC_M68HC11_PAGE:
-#if 0
-      bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
-#endif
       ((bfd_byte *) where)[0] = (bfd_byte) value;
       break;
 
     case BFD_RELOC_8_PCREL:
-#if 0
-      bfd_putb8 ((bfd_vma) value, (unsigned char *) where);
-#endif
       ((bfd_byte *) where)[0] = (bfd_byte) value;
 
       if (value < -128 || value > 127)
diff --git a/gas/config/tc-m68hc11.h b/gas/config/tc-m68hc11.h
index 92ba4887a843..70d7d9e7f21d 100644
--- a/gas/config/tc-m68hc11.h
+++ b/gas/config/tc-m68hc11.h
@@ -1,5 +1,6 @@
 /* tc-m68hc11.h -- Header file for tc-m68hc11.c.
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,15 +16,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_M68HC11
 #define TC_M68HC12
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
 
 /* Define TC_M68K so that we can use the MRI mode.  */
 #define TC_M68K
@@ -33,16 +32,6 @@ struct fix;
 /* Motorola assembler specs does not require '.' before pseudo-ops.  */
 #define NO_PSEUDO_DOT 1
 
-#if 0
-/* Treat the single quote as a string delimiter.
-   ??? This does not work at all.  */
-#define SINGLE_QUOTE_STRINGS 1
-#endif
-
-#ifndef BFD_ASSEMBLER
-#error M68HC11 support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH (m68hc11_arch ())
 extern enum bfd_architecture m68hc11_arch (void);
@@ -98,7 +87,7 @@ extern long m68hc11_relax_frag (segT, fragS*, long);
 
 #define DIFF_EXPR_OK		/* .-foo gets turned into PC relative relocs */
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* No shared lib support, so we don't need to ensure externally
@@ -112,9 +101,6 @@ extern int tc_m68hc11_force_relocation (struct fix *);
 extern int tc_m68hc11_fix_adjustable (struct fix *);
 
 #define md_operand(x)
-#define tc_frob_label(sym) do {\
-  S_SET_VALUE (sym, (valueT) frag_now_fix ()); \
-} while (0)
 
 #define elf_tc_final_processing	m68hc11_elf_final_processing
 extern void m68hc11_elf_final_processing (void);
diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c
index 5bef34b4efd0..6cf85d7e603a 100644
--- a/gas/config/tc-m68k.c
+++ b/gas/config/tc-m68k.c
@@ -1,6 +1,6 @@
 /* tc-m68k.c -- Assemble for the m68k family
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 #include "safe-ctype.h"
@@ -33,6 +33,10 @@
 #include "elf/m68k.h"
 #endif
 
+#ifdef M68KCOFF
+#include "obj-coff.h"
+#endif
+
 /* This string holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  The macro
    tc_comment_chars points to this.  We use this, rather than the
@@ -66,8 +70,6 @@ const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
    changed in read.c .  Ideally it shouldn't have to know about it at all,
    but nothing is ideal around here.  */
 
-const int md_reloc_size = 8;	/* Size of relocation record.  */
-
 /* Are we trying to generate PIC code?  If so, absolute references
    ought to be made into linkage table references or pc-relative
    references.  Not implemented.  For ELF there are other means
@@ -130,6 +132,9 @@ static struct label_line *labels;
 
 static struct label_line *current_label;
 
+/* Pointer to list holding the opcodes sorted by name.  */
+static struct m68k_opcode const ** m68k_sorted_opcodes;
+
 /* Its an arbitrary name:  This means I don't approve of it.
    See flames below.  */
 static struct obstack robyn;
@@ -147,42 +152,86 @@ struct m68k_incant
 #define getone(x)	((((x)->m_opcode)>>16)&0xffff)
 #define gettwo(x)	(((x)->m_opcode)&0xffff)
 
-static const enum m68k_register m68000_control_regs[] = { 0 };
-static const enum m68k_register m68010_control_regs[] = {
+static const enum m68k_register m68000_ctrl[] = { 0 };
+static const enum m68k_register m68010_ctrl[] = {
   SFC, DFC, USP, VBR,
   0
 };
-static const enum m68k_register m68020_control_regs[] = {
+static const enum m68k_register m68020_ctrl[] = {
   SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
   0
 };
-static const enum m68k_register m68040_control_regs[] = {
+static const enum m68k_register m68040_ctrl[] = {
   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
   USP, VBR, MSP, ISP, MMUSR, URP, SRP,
   0
 };
-static const enum m68k_register m68060_control_regs[] = {
+static const enum m68k_register m68060_ctrl[] = {
   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
   USP, VBR, URP, SRP, PCR,
   0
 };
-static const enum m68k_register mcf_control_regs[] = {
+static const enum m68k_register mcf_ctrl[] = {
   CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
   RAMBAR0, RAMBAR1, MBAR,
   0
 };
-static const enum m68k_register mcf528x_control_regs[] = {
-  CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
+static const enum m68k_register mcf5208_ctrl[] = {
+  CACR, ACR0, ACR1, VBR, RAMBAR1,
+  0
+};
+static const enum m68k_register mcf5213_ctrl[] = {
+  VBR, RAMBAR, FLASHBAR,
+  0
+};
+static const enum m68k_register mcf5216_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5235_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5249_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
+  0
+};
+static const enum m68k_register mcf5250_ctrl[] = {
+  VBR,
   0
 };
-static const enum m68k_register mcfv4e_control_regs[] = {
+static const enum m68k_register mcf5271_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5272_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
+  0
+};
+static const enum m68k_register mcf5275_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5282_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5329_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR,
+  0
+};
+static const enum m68k_register mcf5373_ctrl[] = {
+  VBR, CACR, ACR0, ACR1, RAMBAR,
+  0
+};
+static const enum m68k_register mcfv4e_ctrl[] = {
   CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
   ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
   PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
   PCR3U0, PCR3L0, PCR3U1, PCR3L1,
   0
 };
-#define cpu32_control_regs m68010_control_regs
+#define cpu32_ctrl m68010_ctrl
 
 static const enum m68k_register *control_regs;
 
@@ -235,14 +284,14 @@ struct m68k_it
   reloc[5];			/* Five is enough???  */
 };
 
-#define cpu_of_arch(x)		((x) & (m68000up | mcf))
+#define cpu_of_arch(x)		((x) & (m68000up | mcfisa_a))
 #define float_of_arch(x)	((x) & mfloat)
 #define mmu_of_arch(x)		((x) & mmmu)
-#define arch_coldfire_p(x)	((x) & mcf)
-#define arch_coldfire_v4e_p(x)	((x) & mcfv4e)
+#define arch_coldfire_p(x)	((x) & mcfisa_a)
+#define arch_coldfire_fpu(x)	((x) & cfloat)
 
 /* Macros for determining if cpu supports a specific addressing mode.  */
-#define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407|mcfv4e))
+#define HAVE_LONG_BRANCH(x)     ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
 
 static struct m68k_it the_ins;	/* The instruction being assembled.  */
 
@@ -252,19 +301,12 @@ static struct m68k_it the_ins;	/* The instruction being assembled.  */
 #define offs(ex)	((ex)->exp.X_add_number)
 
 /* Macros for adding things to the m68k_it struct.  */
-#define addword(w)	the_ins.opcode[the_ins.numo++]=(w)
-
-/* Static functions.  */
-static void insop PARAMS ((int, const struct m68k_incant *));
-static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
-static void add_frag PARAMS ((symbolS *, offsetT, int));
+#define addword(w)	(the_ins.opcode[the_ins.numo++] = (w))
 
 /* Like addword, but goes BEFORE general operands.  */
 
 static void
-insop (w, opcode)
-     int w;
-     const struct m68k_incant *opcode;
+insop (int w, const struct m68k_incant *opcode)
 {
   int z;
   for (z = the_ins.numo; z > opcode->m_codenum; --z)
@@ -280,17 +322,13 @@ insop (w, opcode)
 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
    Blecch.  */
 static void
-add_fix (width, exp, pc_rel, pc_fix)
-     int width;
-     struct m68k_exp *exp;
-     int pc_rel;
-     int pc_fix;
+add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
 {
-  the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
-				   ? (the_ins.numo*2-1)
-				   : (((width)=='b')
-				      ? (the_ins.numo*2+1)
-				      : (the_ins.numo*2)));
+  the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
+				   ? the_ins.numo * 2 - 1
+				   : (width == 'b'
+				      ? the_ins.numo * 2 + 1
+				      : the_ins.numo * 2));
   the_ins.reloc[the_ins.nrel].exp = exp->exp;
   the_ins.reloc[the_ins.nrel].wid = width;
   the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
@@ -311,10 +349,7 @@ add_fix (width, exp, pc_rel, pc_fix)
 
    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
 static void
-add_frag (add, off, type)
-     symbolS *add;
-     offsetT off;
-     int type;
+add_frag (symbolS *add, offsetT off, int type)
 {
   the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
   the_ins.fragb[the_ins.nfrag].fadd = add;
@@ -325,101 +360,207 @@ add_frag (add, off, type)
 #define isvar(ex) \
   (op (ex) != O_constant && op (ex) != O_big)
 
-static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
-static int get_num PARAMS ((struct m68k_exp *exp, int ok));
-static void m68k_ip PARAMS ((char *));
-static void insert_reg PARAMS ((const char *, int));
-static void select_control_regs PARAMS ((void));
-static void init_regtable PARAMS ((void));
-static int reverse_16_bits PARAMS ((int in));
-static int reverse_8_bits PARAMS ((int in));
-static void install_gen_operand PARAMS ((int mode, int val));
-static void install_operand PARAMS ((int mode, int val));
-static void s_bss PARAMS ((int));
-static void s_data1 PARAMS ((int));
-static void s_data2 PARAMS ((int));
-static void s_even PARAMS ((int));
-static void s_proc PARAMS ((int));
-static void mri_chip PARAMS ((void));
-static void s_chip PARAMS ((int));
-static void s_fopt PARAMS ((int));
-static void s_opt PARAMS ((int));
-static void s_reg PARAMS ((int));
-static void s_restore PARAMS ((int));
-static void s_save PARAMS ((int));
-static void s_mri_if PARAMS ((int));
-static void s_mri_else PARAMS ((int));
-static void s_mri_endi PARAMS ((int));
-static void s_mri_break PARAMS ((int));
-static void s_mri_next PARAMS ((int));
-static void s_mri_for PARAMS ((int));
-static void s_mri_endf PARAMS ((int));
-static void s_mri_repeat PARAMS ((int));
-static void s_mri_until PARAMS ((int));
-static void s_mri_while PARAMS ((int));
-static void s_mri_endw PARAMS ((int));
-static void md_convert_frag_1 PARAMS ((fragS *));
+static char *crack_operand (char *str, struct m68k_op *opP);
+static int get_num (struct m68k_exp *exp, int ok);
+static int reverse_16_bits (int in);
+static int reverse_8_bits (int in);
+static void install_gen_operand (int mode, int val);
+static void install_operand (int mode, int val);
+static void s_bss (int);
+static void s_data1 (int);
+static void s_data2 (int);
+static void s_even (int);
+static void s_proc (int);
+static void s_chip (int);
+static void s_fopt (int);
+static void s_opt (int);
+static void s_reg (int);
+static void s_restore (int);
+static void s_save (int);
+static void s_mri_if (int);
+static void s_mri_else (int);
+static void s_mri_endi (int);
+static void s_mri_break (int);
+static void s_mri_next (int);
+static void s_mri_for (int);
+static void s_mri_endf (int);
+static void s_mri_repeat (int);
+static void s_mri_until (int);
+static void s_mri_while (int);
+static void s_mri_endw (int);
+static void s_m68k_cpu (int);
+static void s_m68k_arch (int);
+
+struct m68k_cpu
+{
+  unsigned long arch;	/* Architecture features.  */
+  const enum m68k_register *control_regs;	/* Control regs on chip */
+  const char *name;	/* Name */
+  int alias;       	/* Alias for a cannonical name.  If 1, then
+			   succeeds canonical name, if -1 then
+			   succeeds canonical name, if <-1 ||>1 this is a
+			   deprecated name, and the next/previous name
+			   should be used. */
+};
 
+/* We hold flags for features explicitly enabled and explicitly
+   disabled.  */
 static int current_architecture;
+static int not_current_architecture;
+static const struct m68k_cpu *selected_arch;
+static const struct m68k_cpu *selected_cpu;
+static int initialized;
 
-struct m68k_cpu
-  {
-    unsigned long arch;
-    const char *name;
-    int alias;
-  };
+/* Architecture models.  */
+static const struct m68k_cpu m68k_archs[] =
+{
+  {m68000,					m68000_ctrl, "68000", 0},
+  {m68010,					m68010_ctrl, "68010", 0},
+  {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
+  {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
+  {m68040,					m68040_ctrl, "68040", 0},
+  {m68060,					m68060_ctrl, "68060", 0},
+  {cpu32|m68881,				cpu32_ctrl, "cpu32", 0},
+  {mcfisa_a|mcfhwdiv,				NULL, "isaa", 0},
+  {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,		NULL, "isaaplus", 0},
+  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,		NULL, "isab", 0},
+  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,	mcf_ctrl, "cfv4", 0},
+  {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
+  {0,0,NULL, 0}
+};
 
-static const struct m68k_cpu archs[] =
-  {
-    { m68000,  "68000", 0 },
-    { m68010,  "68010", 0 },
-    { m68020,  "68020", 0 },
-    { m68030,  "68030", 0 },
-    { m68040,  "68040", 0 },
-    { m68060,  "68060", 0 },
-    { cpu32,   "cpu32", 0 },
-    { m68881,  "68881", 0 },
-    { m68851,  "68851", 0 },
-    { mcf5200, "5200",  0 },
-    { mcf5206e,"5206e", 0 },
-    { mcf528x, "528x",  0 },
-    { mcf5307, "5307",  0 },
-    { mcf5407, "5407",  0 },
-    { mcfv4e,  "cfv4e", 0 },
-    /* Aliases (effectively, so far as gas is concerned) for the above
-       cpus.  */
-    { m68020, "68k", 1 },
-    { m68000, "68008", 1 },
-    { m68000, "68302", 1 },
-    { m68000, "68306", 1 },
-    { m68000, "68307", 1 },
-    { m68000, "68322", 1 },
-    { m68000, "68356", 1 },
-    { m68000, "68ec000", 1 },
-    { m68000, "68hc000", 1 },
-    { m68000, "68hc001", 1 },
-    { m68020, "68ec020", 1 },
-    { m68030, "68ec030", 1 },
-    { m68040, "68ec040", 1 },
-    { m68060, "68ec060", 1 },
-    { cpu32,  "68330", 1 },
-    { cpu32,  "68331", 1 },
-    { cpu32,  "68332", 1 },
-    { cpu32,  "68333", 1 },
-    { cpu32,  "68334", 1 },
-    { cpu32,  "68336", 1 },
-    { cpu32,  "68340", 1 },
-    { cpu32,  "68341", 1 },
-    { cpu32,  "68349", 1 },
-    { cpu32,  "68360", 1 },
-    { m68881, "68882", 1 },
-    { mcf5200, "5202", 1 },
-    { mcf5200, "5204", 1 },
-    { mcf5200, "5206", 1 },
-    { mcf5407, "cfv4", 1 },
+/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
+   for either.  */
+static const struct m68k_cpu m68k_extensions[] =
+{
+  {m68851,					NULL, "68851", -1},
+  {m68881,					NULL, "68881", -1},
+  {m68881,					NULL, "68882", -1},
+  
+  {cfloat|m68881,				NULL, "float", 0},
+  
+  {mcfhwdiv,					NULL, "div", 1},
+  {mcfusp,					NULL, "usp", 1},
+  {mcfmac,					NULL, "mac", 1},
+  {mcfemac,					NULL, "emac", 1},
+   
+  {0,NULL,NULL, 0}
+};
+
+/* Processor list */
+static const struct m68k_cpu m68k_cpus[] =
+{
+  {m68000,					m68000_ctrl, "68000", 0},
+  {m68000,					m68000_ctrl, "68ec000", 1},
+  {m68000,					m68000_ctrl, "68hc000", 1},
+  {m68000,					m68000_ctrl, "68hc001", 1},
+  {m68000,					m68000_ctrl, "68008", 1},
+  {m68000,					m68000_ctrl, "68302", 1},
+  {m68000,					m68000_ctrl, "68306", 1},
+  {m68000,					m68000_ctrl, "68307", 1},
+  {m68000,					m68000_ctrl, "68322", 1},
+  {m68000,					m68000_ctrl, "68356", 1},
+  {m68010,					m68010_ctrl, "68010", 0},
+  {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
+  {m68020|m68881|m68851,			m68020_ctrl, "68k", 1},
+  {m68020|m68881|m68851,			m68020_ctrl, "68ec020", 1},
+  {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
+  {m68030|m68881|m68851,			m68020_ctrl, "68ec030", 1},
+  {m68040,					m68040_ctrl, "68040", 0},
+  {m68040,					m68040_ctrl, "68ec040", 1},
+  {m68060,					m68060_ctrl, "68060", 0},
+  {m68060,					m68060_ctrl, "68ec060", 1},
+  
+  {cpu32|m68881,				cpu32_ctrl, "cpu32",  0},
+  {cpu32|m68881,				cpu32_ctrl, "68330", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68331", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68332", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68333", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68334", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68336", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68340", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68341", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68349", 1},
+  {cpu32|m68881,				cpu32_ctrl, "68360", 1},
+  
+  {mcfisa_a,					mcf_ctrl, "5200", 0},
+  {mcfisa_a,					mcf_ctrl, "5202", 1},
+  {mcfisa_a,					mcf_ctrl, "5204", 1},
+  {mcfisa_a,					mcf_ctrl, "5206", 1},
+  
+  {mcfisa_a|mcfhwdiv|mcfmac,			mcf_ctrl, "5206e", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5207", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5208", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5211", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5212", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5213", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5214", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5216", 0},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "521x", 2},
+
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5232", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5233", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5234", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5235", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "523x", 0},
+  
+  {mcfisa_a|mcfhwdiv|mcfemac,			mcf5249_ctrl, "5249", 0},
+  {mcfisa_a|mcfhwdiv|mcfemac,			mcf5250_ctrl, "5250", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5270", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5271", 0},
+  
+  {mcfisa_a|mcfhwdiv|mcfmac,			mcf5272_ctrl, "5272", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5274", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5275", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5280", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5281", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5282", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "528x", 0},
+  
+  {mcfisa_a|mcfhwdiv|mcfmac,			mcf_ctrl, "5307", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5327", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5328", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5329", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "532x", 0},
+  
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5372", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5373", -1},
+  {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "537x", 0},
+  
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,		mcf_ctrl, "5407",0},
+  
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
+  
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
+  {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
+  
+  {0,NULL,NULL, 0}
   };
 
-static const int n_archs = sizeof (archs) / sizeof (archs[0]);
+static const struct m68k_cpu *m68k_lookup_cpu
+(const char *, const struct m68k_cpu *, int, int *);
+static int m68k_set_arch (const char *, int, int);
+static int m68k_set_cpu (const char *, int, int);
+static int m68k_set_extension (const char *, int, int);
+static void m68k_init_arch (void);
 
 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
    architecture and we have a lot of relaxation modes.  */
@@ -565,6 +706,9 @@ const pseudo_typeS md_pseudo_table[] =
   {"extend", float_cons, 'x'},
   {"ldouble", float_cons, 'x'},
 
+  {"arch", s_m68k_arch, 0},
+  {"cpu", s_m68k_cpu, 0},
+
   /* The following pseudo-ops are supported for MRI compatibility.  */
   {"chip", s_chip, 0},
   {"comline", s_space, 1},
@@ -609,12 +753,7 @@ const pseudo_typeS md_pseudo_table[] =
 };
 
 /* The mote pseudo ops are put into the opcode table, since they
-   don't start with a . they look like opcodes to gas.
-   */
-
-#ifdef M68KCOFF
-extern void obj_coff_section PARAMS ((int));
-#endif
+   don't start with a . they look like opcodes to gas.  */
 
 const pseudo_typeS mote_pseudo_table[] =
 {
@@ -642,16 +781,19 @@ const pseudo_typeS mote_pseudo_table[] =
   {0, 0, 0}
 };
 
-#define issbyte(x)	((x)>=-128 && (x)<=127)
-#define isubyte(x)	((x)>=0 && (x)<=255)
-#define issword(x)	((x)>=-32768 && (x)<=32767)
-#define isuword(x)	((x)>=0 && (x)<=65535)
+/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
+   gives identical results to a 32-bit host.  */
+#define TRUNC(X)	((valueT) (X) & 0xffffffff)
+#define SEXT(X)		((TRUNC (X) ^ 0x80000000) - 0x80000000)
 
-#define isbyte(x)	((x)>= -255 && (x)<=255)
-#define isword(x)	((x)>=-65536 && (x)<=65535)
-#define islong(x)	(1)
+#define issbyte(x)	((valueT) SEXT (x) + 0x80 < 0x100)
+#define isubyte(x)	((valueT) TRUNC (x) < 0x100)
+#define issword(x)	((valueT) SEXT (x) + 0x8000 < 0x10000)
+#define isuword(x)	((valueT) TRUNC (x) < 0x10000)
 
-extern char *input_line_pointer;
+#define isbyte(x)	((valueT) SEXT (x) + 0xff < 0x1ff)
+#define isword(x)	((valueT) SEXT (x) + 0xffff < 0x1ffff)
+#define islong(x)	(1)
 
 static char notend_table[256];
 static char alt_notend_table[256];
@@ -660,66 +802,6 @@ static char alt_notend_table[256];
       || (*s == ':'						\
 	  && alt_notend_table[(unsigned char) s[1]])))
 
-#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
-
-#ifdef NO_PCREL_RELOCS
-
-int
-make_pcrel_absolute(fixP, add_number)
-    fixS *fixP;
-    long *add_number;
-{
-  register unsigned char *opcode = fixP->fx_frag->fr_opcode;
-
-  /* Rewrite the PC relative instructions to absolute address ones.
-     these are rumored to be faster, and the apollo linker refuses
-     to deal with the PC relative relocations.  */
-  if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP.  */
-    {
-      if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative branch to absolute jump"));
-      opcode[0] = 0x4e;
-      opcode[1] = 0xf9;
-    }
-  else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR.  */
-    {
-      if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
-      opcode[0] = 0x4e;
-      opcode[1] = 0xb9;
-    }
-  else
-    as_fatal (_("Unknown PC relative instruction"));
-  *add_number -= 4;
-  return 0;
-}
-
-#endif /* NO_PCREL_RELOCS */
-
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-  if (fixP->fx_tcbit && fixP->fx_size == 4)
-    return R_RELLONG_NEG;
-#ifdef NO_PCREL_RELOCS
-  know (fixP->fx_pcrel == 0);
-  return (fixP->fx_size == 1 ? R_RELBYTE
-	  : fixP->fx_size == 2 ? R_DIR16
-	  : R_DIR32);
-#else
-  return (fixP->fx_pcrel ?
-	  (fixP->fx_size == 1 ? R_PCRBYTE :
-	   fixP->fx_size == 2 ? R_PCRWORD :
-	   R_PCRLONG) :
-	  (fixP->fx_size == 1 ? R_RELBYTE :
-	   fixP->fx_size == 2 ? R_RELWORD :
-	   R_RELLONG));
-#endif
-}
-
-#endif
-
 #ifdef OBJ_ELF
 
 /* Return zero if the reference to SYMBOL from within the same segment may
@@ -739,14 +821,8 @@ tc_coff_fix2rtype (fixP)
    relative relocation if PCREL is non-zero.  PIC says whether a special
    pic relocation was requested.  */
 
-static bfd_reloc_code_real_type get_reloc_code
-  PARAMS ((int, int, enum pic_relocation));
-
 static bfd_reloc_code_real_type
-get_reloc_code (size, pcrel, pic)
-     int size;
-     int pcrel;
-     enum pic_relocation pic;
+get_reloc_code (int size, int pcrel, enum pic_relocation pic)
 {
   switch (pic)
     {
@@ -849,8 +925,7 @@ get_reloc_code (size, pcrel, pic)
    correctly, so in some cases we force the original symbol to be
    used.  */
 int
-tc_m68k_fix_adjustable (fixP)
-     fixS *fixP;
+tc_m68k_fix_adjustable (fixS *fixP)
 {
   /* Adjust_reloc_syms doesn't know about the GOT.  */
   switch (fixP->fx_r_type)
@@ -886,12 +961,8 @@ tc_m68k_fix_adjustable (fixP)
 
 #endif /* OBJ_ELF */
 
-#ifdef BFD_ASSEMBLER
-
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
   bfd_reloc_code_real_type code;
@@ -1000,8 +1071,6 @@ tc_gen_reloc (section, fixp)
   return reloc;
 }
 
-#endif /* BFD_ASSEMBLER */
-
 /* Handle of the OPCODE hash table.  NULL means any use before
    m68k_ip_begin() will crash.  */
 static struct hash_control *op_hash;
@@ -1009,8 +1078,7 @@ static struct hash_control *op_hash;
 /* Assemble an m68k instruction.  */
 
 static void
-m68k_ip (instring)
-     char *instring;
+m68k_ip (char *instring)
 {
   register char *p;
   register struct m68k_op *opP;
@@ -1022,6 +1090,7 @@ m68k_ip (instring)
   char c;
   int losing;
   int opsfound;
+  struct m68k_op operands_backup[6];
   LITTLENUM_TYPE words[6];
   LITTLENUM_TYPE *wordp;
   unsigned long ok_arch = 0;
@@ -1128,8 +1197,7 @@ m68k_ip (instring)
       for (n = opsfound; n > 0; --n)
 	the_ins.operands[n] = the_ins.operands[n - 1];
 
-      memset ((char *) (&the_ins.operands[0]), '\0',
-	      sizeof (the_ins.operands[0]));
+      memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
       the_ins.operands[0].mode = CONTROL;
       the_ins.operands[0].reg = m68k_float_copnum;
       opsfound++;
@@ -1147,7 +1215,15 @@ m68k_ip (instring)
 	++losing;
       else
 	{
-	  for (s = opcode->m_operands, opP = &the_ins.operands[0];
+	  int i;
+
+	  /* Make a copy of the operands of this insn so that
+	     we can modify them safely, should we want to.  */
+	  assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
+	  for (i = 0; i < opsfound; i++)
+	    operands_backup[i] = the_ins.operands[i];
+
+	  for (s = opcode->m_operands, opP = &operands_backup[0];
 	       *s && !losing;
 	       s += 2, opP++)
 	    {
@@ -1505,6 +1581,14 @@ m68k_ip (instring)
 		    ++losing;
 		  break;
 
+		case '4':
+		  if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
+		      && (opP->mode != DISP
+			   || opP->reg < ADDR0
+			   || opP->reg > ADDR7))
+		    ++losing;
+		  break;
+
 		case 'B':	/* FOO */
 		  if (opP->mode != ABSL
 		      || (flag_long_jumps
@@ -1552,6 +1636,12 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'e':
+		  if (opP->reg != ACC && opP->reg != ACC1
+		      && opP->reg != ACC2 && opP->reg != ACC3)
+		    losing++;
+		  break;
+
 		case 'F':
 		  if (opP->mode != FPREG)
 		    losing++;
@@ -1562,6 +1652,11 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'g':
+		  if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
+		    losing++;
+		  break;
+
 		case 'H':
 		  if (opP->reg != MASK)
 		    losing++;
@@ -1574,14 +1669,21 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'i':
+		  if (opP->mode != LSH && opP->mode != RSH)
+		    losing++;
+		  break;
+
 		case 'J':
 		  if (opP->mode != CONTROL
 		      || opP->reg < USP
-		      || opP->reg > last_movec_reg)
+		      || opP->reg > last_movec_reg
+		      || !control_regs)
 		    losing++;
 		  else
 		    {
 		      const enum m68k_register *rp;
+		      
 		      for (rp = control_regs; *rp; rp++)
 			if (*rp == opP->reg)
 			  break;
@@ -1677,8 +1779,7 @@ m68k_ip (instring)
 		  if (opP->mode != IMMED)
 		    losing++;
 		  else if (opP->disp.exp.X_op != O_constant
-			   || opP->disp.exp.X_add_number < 1
-			   || opP->disp.exp.X_add_number > 8)
+			   || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
 		    losing++;
 		  else if (! m68k_quick
 			   && (strncmp (instring, "add", 3) == 0
@@ -1724,8 +1825,7 @@ m68k_ip (instring)
 		  if (opP->mode != IMMED)
 		    losing++;
 		  else if (opP->disp.exp.X_op != O_constant
-			   || opP->disp.exp.X_add_number < 0
-			   || opP->disp.exp.X_add_number > 7)
+			   || TRUNC (opP->disp.exp.X_add_number) > 7)
 		    losing++;
 		  break;
 
@@ -1738,9 +1838,8 @@ m68k_ip (instring)
 		  if (opP->mode != IMMED)
 		    losing++;
 		  else if (opP->disp.exp.X_op != O_constant
-			   || opP->disp.exp.X_add_number < -1
-                           || opP->disp.exp.X_add_number > 7
-                           || opP->disp.exp.X_add_number == 0)
+			   || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
+			       && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
 		    losing++;
 		  break;
 
@@ -1870,8 +1969,8 @@ m68k_ip (instring)
 
 		 case 'y':
 		   if (!(opP->mode == AINDR
-			 || (opP->mode == DISP && !(opP->reg == PC ||
-						    opP->reg == ZPC))))
+			 || (opP->mode == DISP
+			     && !(opP->reg == PC || opP->reg == ZPC))))
 		     losing++;
 		   break;
 
@@ -1887,6 +1986,12 @@ m68k_ip (instring)
 	      if (losing)
 		break;
 	    }
+
+	  /* Since we have found the correct instruction, copy
+	     in the modifications that we may have made.  */
+	  if (!losing)
+	    for (i = 0; i < opsfound; i++)
+	      the_ins.operands[i] = operands_backup[i];
 	}
 
       if (!losing)
@@ -1899,56 +2004,100 @@ m68k_ip (instring)
 	  if (ok_arch
 	      && !(ok_arch & current_architecture))
 	    {
-	      char buf[200], *cp;
-
-	      strcpy (buf,
-		      _("invalid instruction for this architecture; needs "));
-	      cp = buf + strlen (buf);
+	      const struct m68k_cpu *cpu;
+	      int any = 0;
+	      size_t space = 400;
+	      char *buf = xmalloc (space + 1);
+	      size_t len;
+	      int paren = 1;
+
+	      the_ins.error = buf;
+	      /* Make sure there's a NUL at the end of the buffer -- strncpy
+		 won't write one when it runs out of buffer */
+	      buf[space] = 0;
+#define APPEND(STRING) \
+  (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
+
+	      APPEND (_("invalid instruction for this architecture; needs "));
 	      switch (ok_arch)
 		{
+		case mcfisa_a:
+		  APPEND (_("ColdFire ISA_A"));
+		  break;
+		case mcfhwdiv:
+		  APPEND (_("ColdFire hardware divide"));
+		  break;
+		case mcfisa_aa:
+		  APPEND (_("ColdFire ISA_A+"));
+		  break;
+		case mcfisa_b:
+		  APPEND (_("ColdFire ISA_B"));
+		  break;
 		case cfloat:
-		  strcpy (cp, _("ColdFire fpu (cfv4e)"));
+		  APPEND (_("ColdFire fpu"));
 		  break;
 		case mfloat:
-		  strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
+		  APPEND (_("M68K fpu"));
 		  break;
 		case mmmu:
-		  strcpy (cp, _("mmu (68030 or 68851)"));
+		  APPEND (_("M68K mmu"));
 		  break;
 		case m68020up:
-		  strcpy (cp, _("68020 or higher"));
+		  APPEND (_("68020 or higher"));
 		  break;
 		case m68000up:
-		  strcpy (cp, _("68000 or higher"));
+		  APPEND (_("68000 or higher"));
 		  break;
 		case m68010up:
-		  strcpy (cp, _("68010 or higher"));
+		  APPEND (_("68010 or higher"));
 		  break;
 		default:
+		  paren = 0;
+		}
+	      if (paren)
+		APPEND (" (");
+
+	      for (cpu = m68k_cpus; cpu->name; cpu++)
+		if (!cpu->alias && (cpu->arch & ok_arch))
 		  {
-		    int got_one = 0, idx;
-		    for (idx = 0;
-			 idx < (int) (sizeof (archs) / sizeof (archs[0]));
-			 idx++)
+		    const struct m68k_cpu *alias;
+
+		    if (any)
+		      APPEND (", ");
+		    any = 0;
+		    APPEND (cpu->name);
+		    APPEND (" [");
+		    if (cpu != m68k_cpus)
+		      for (alias = cpu - 1; alias->alias; alias--)
+			{
+			  if (any)
+			    APPEND (", ");
+			  APPEND (alias->name);
+			  any = 1;
+			}
+		    for (alias = cpu + 1; alias->alias; alias++)
 		      {
-			if ((archs[idx].arch & ok_arch)
-			    && ! archs[idx].alias)
-			  {
-			    if (got_one)
-			      {
-				strcpy (cp, " or ");
-				cp += strlen (cp);
-			      }
-			    got_one = 1;
-			    strcpy (cp, archs[idx].name);
-			    cp += strlen (cp);
-			  }
+			if (any)
+			  APPEND (", ");
+			APPEND (alias->name);
+			any = 1;
 		      }
+		    
+		    APPEND ("]");
+		    any = 1;
 		  }
+	      if (paren)
+		APPEND (")");
+#undef APPEND
+	      if (!space)
+		{
+		  /* we ran out of space, so replace the end of the list
+		     with ellipsis.  */
+		  buf -= 4;
+		  while (*buf != ' ')
+		    buf--;
+		  strcpy (buf, " ...");
 		}
-	      cp = xmalloc (strlen (buf) + 1);
-	      strcpy (cp, buf);
-	      the_ins.error = cp;
 	    }
 	  else
 	    the_ins.error = _("operands mismatch");
@@ -1968,7 +2117,7 @@ m68k_ip (instring)
   for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
     {
       /* This switch is a doozy.
-       Watch the first step; its a big one! */
+	 Watch the first step; its a big one! */
       switch (s[0])
 	{
 
@@ -1994,6 +2143,7 @@ m68k_ip (instring)
 	case 'w':
 	case 'y':
 	case 'z':
+	case '4':
 #ifndef NO_68851
 	case '|':
 #endif
@@ -2116,17 +2266,26 @@ m68k_ip (instring)
 
 	      nextword = get_num (&opP->disp, 90);
 
+	      /* Convert mode 5 addressing with a zero offset into
+		 mode 2 addressing to reduce the instruction size by a
+		 word.  */
+	      if (! isvar (&opP->disp)
+		  && (nextword == 0)
+		  && (opP->disp.size == SIZE_UNSPEC)
+		  && (opP->reg >= ADDR0)
+		  && (opP->reg <= ADDR7))
+		{
+		  tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
+		  break;
+		}
+
 	      if (opP->reg == PC
 		  && ! isvar (&opP->disp)
 		  && m68k_abspcadd)
 		{
 		  opP->disp.exp.X_op = O_symbol;
-#ifndef BFD_ASSEMBLER
-		  opP->disp.exp.X_add_symbol = &abs_symbol;
-#else
 		  opP->disp.exp.X_add_symbol =
 		    section_symbol (absolute_section);
-#endif
 		}
 
 	      /* Force into index mode.  Hope this works.  */
@@ -2171,7 +2330,7 @@ m68k_ip (instring)
 			  else
 			    {
 			      add_frag (adds (&opP->disp),
-					offs (&opP->disp),
+					SEXT (offs (&opP->disp)),
 					TAB (PCREL1632, SZ_UNDEF));
 			      break;
 			    }
@@ -2256,7 +2415,7 @@ m68k_ip (instring)
 		       && cpu_of_arch (current_architecture) < m68020)
 		      || (opP->index.scale == 8
 			  && (arch_coldfire_p (current_architecture)
-                              && !arch_coldfire_v4e_p(current_architecture))))
+                              && !arch_coldfire_fpu (current_architecture))))
 		    {
 		      opP->error =
 			_("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
@@ -2343,7 +2502,8 @@ m68k_ip (instring)
 			  frag_grow (14);
 			  nextword += baseo & 0xff;
 			  addword (nextword);
-			  add_frag (adds (&opP->disp), offs (&opP->disp),
+			  add_frag (adds (&opP->disp),
+				    SEXT (offs (&opP->disp)),
 				    TAB (PCINDEX, SZ_UNDEF));
 
 			  break;
@@ -2486,7 +2646,7 @@ m68k_ip (instring)
 		    {
 		      tmpreg = 0x3A;	/* 7.2 */
 		      add_frag (adds (&opP->disp),
-				offs (&opP->disp),
+				SEXT (offs (&opP->disp)),
 				TAB (ABSTOPCREL, SZ_UNDEF));
 		      break;
 		    }
@@ -2519,6 +2679,16 @@ m68k_ip (instring)
 	      as_bad (_("unknown/incorrect operand"));
 	      /* abort (); */
 	    }
+
+	  /* If s[0] is '4', then this is for the mac instructions
+	     that can have a trailing_ampersand set.  If so, set 0x100
+	     bit on tmpreg so install_gen_operand can check for it and
+	     set the appropriate bit (word2, bit 5).  */
+	  if (s[0] == '4')
+	    {
+	      if (opP->trailing_ampersand)
+		tmpreg |= 0x100;
+	    }
 	  install_gen_operand (s[1], tmpreg);
 	  break;
 
@@ -2659,20 +2829,24 @@ m68k_ip (instring)
 		 out which mode.  We try in this order of preference:
 		 long branch, absolute jump, byte/word branches only.  */
 	      if (HAVE_LONG_BRANCH (current_architecture))
-		add_frag (adds (&opP->disp), offs (&opP->disp),
+		add_frag (adds (&opP->disp),
+			  SEXT (offs (&opP->disp)),
 			  TAB (BRANCHBWL, SZ_UNDEF));
 	      else if (! flag_keep_pcrel)
 		{
 		  if ((the_ins.opcode[0] == 0x6000)
 		      || (the_ins.opcode[0] == 0x6100))
-		    add_frag (adds (&opP->disp), offs (&opP->disp),
+		    add_frag (adds (&opP->disp),
+			      SEXT (offs (&opP->disp)),
 			      TAB (BRABSJUNC, SZ_UNDEF));
 		  else
-		    add_frag (adds (&opP->disp), offs (&opP->disp),
+		    add_frag (adds (&opP->disp),
+			      SEXT (offs (&opP->disp)),
 			      TAB (BRABSJCOND, SZ_UNDEF));
 		}
 	      else
-		add_frag (adds (&opP->disp), offs (&opP->disp),
+		add_frag (adds (&opP->disp),
+			  SEXT (offs (&opP->disp)),
 			  TAB (BRANCHBW, SZ_UNDEF));
 	      break;
 	    case 'w':
@@ -2686,10 +2860,12 @@ m68k_ip (instring)
 			  || (! flag_keep_pcrel)))
 		    {
 		      if (HAVE_LONG_BRANCH (current_architecture))
-			add_frag (adds (&opP->disp), offs (&opP->disp),
+			add_frag (adds (&opP->disp),
+				  SEXT (offs (&opP->disp)),
 				  TAB (DBCCLBR, SZ_UNDEF));
 		      else
-			add_frag (adds (&opP->disp), offs (&opP->disp),
+			add_frag (adds (&opP->disp),
+				  SEXT (offs (&opP->disp)),
 				  TAB (DBCCABSJ, SZ_UNDEF));
 		      break;
 		    }
@@ -2711,7 +2887,8 @@ m68k_ip (instring)
 		  addword (0);
 		}
 	      else
-		add_frag (adds (&opP->disp), offs (&opP->disp),
+		add_frag (adds (&opP->disp),
+			  SEXT (offs (&opP->disp)),
 			  TAB (FBRANCH, SZ_UNDEF));
 	      break;
 	    default:
@@ -2737,6 +2914,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - DATA);
 	  break;
 
+	case 'e':  /* EMAC ACCx, reg/reg.  */
+	  install_operand (s[1], opP->reg - ACC);
+	  break;
+	  
 	case 'E':		/* Ignore it.  */
 	  break;
 
@@ -2744,6 +2925,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - FP0);
 	  break;
 
+	case 'g':  /* EMAC ACCEXTx.  */
+	  install_operand (s[1], opP->reg - ACCEXT01);
+	  break;
+
 	case 'G':		/* Ignore it.  */
 	case 'H':
 	  break;
@@ -2753,6 +2938,10 @@ m68k_ip (instring)
 	  install_operand (s[1], tmpreg);
 	  break;
 
+	case 'i':  /* MAC/EMAC scale factor.  */
+	  install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
+	  break;
+
 	case 'J':		/* JF foo.  */
 	  switch (opP->reg)
 	    {
@@ -2836,6 +3025,7 @@ m68k_ip (instring)
               tmpreg = 0xC0D;
               break;
             case MBAR0:
+            case MBAR2:
             case SECMBAR:
               tmpreg = 0xC0E;
               break;
@@ -3152,8 +3342,7 @@ m68k_ip (instring)
 }
 
 static int
-reverse_16_bits (in)
-     int in;
+reverse_16_bits (int in)
 {
   int out = 0;
   int n;
@@ -3172,8 +3361,7 @@ reverse_16_bits (in)
 }				/* reverse_16_bits() */
 
 static int
-reverse_8_bits (in)
-     int in;
+reverse_8_bits (int in)
 {
   int out = 0;
   int n;
@@ -3202,9 +3390,7 @@ reverse_8_bits (in)
 
    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
 static void
-install_operand (mode, val)
-     int mode;
-     int val;
+install_operand (int mode, int val)
 {
   switch (mode)
     {
@@ -3286,38 +3472,62 @@ install_operand (mode, val)
       the_ins.opcode[0] |= ((val & 0x7) << 9);
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'n':
+    case 'n': /* MAC/EMAC Rx on !load.  */
       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
       the_ins.opcode[0] |= ((val & 0x7) << 9);
+      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'o':
+    case 'o': /* MAC/EMAC Rx on load.  */
       the_ins.opcode[1] |= val << 12;
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'M':
+    case 'M': /* MAC/EMAC Ry on !load.  */
       the_ins.opcode[0] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
-    case 'N':
+    case 'N': /* MAC/EMAC Ry on load.  */
       the_ins.opcode[1] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
     case 'h':
       the_ins.opcode[1] |= ((val != 1) << 10);
       break;
+    case 'F':
+      the_ins.opcode[0] |= ((val & 0x3) << 9);
+      break;
+    case 'f':
+      the_ins.opcode[0] |= ((val & 0x3) << 0);
+      break;
+    case 'G':  /* EMAC accumulator in a EMAC load instruction.  */
+      the_ins.opcode[0] |= ((~val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'H':  /* EMAC accumulator in a EMAC non-load instruction.  */
+      the_ins.opcode[0] |= ((val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'I':
+      the_ins.opcode[1] |= ((val & 0x3) << 9);
+      break;
+    case ']':
+      the_ins.opcode[0] |= (val & 0x1) <<10;
+      break;
     case 'c':
     default:
       as_fatal (_("failed sanity check."));
     }
-}				/* install_operand() */
+}
 
 static void
-install_gen_operand (mode, val)
-     int mode;
-     int val;
+install_gen_operand (int mode, int val)
 {
   switch (mode)
     {
+    case '/':  /* Special for mask loads for mac/msac insns with
+		  possible mask; trailing_ampersend set in bit 8.  */
+      the_ins.opcode[0] |= (val & 0x3f);
+      the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
+      break;
     case 's':
       the_ins.opcode[0] |= val;
       break;
@@ -3338,17 +3548,13 @@ install_gen_operand (mode, val)
     default:
       as_fatal (_("failed sanity check."));
     }
-}				/* install_gen_operand() */
+}
 
-/*
- * verify that we have some number of paren pairs, do m68k_ip_op(), and
- * then deal with the bitfield hack.
- */
+/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
+   then deal with the bitfield hack.  */
 
 static char *
-crack_operand (str, opP)
-     register char *str;
-     register struct m68k_op *opP;
+crack_operand (char *str, struct m68k_op *opP)
 {
   register int parens;
   register int c;
@@ -3418,9 +3624,7 @@ crack_operand (str, opP)
    */
 
 static void
-insert_reg (regname, regnum)
-     const char *regname;
-     int regnum;
+insert_reg (const char *regname, int regnum)
 {
   char buf[100];
   int i;
@@ -3507,6 +3711,12 @@ static const struct init_entry init_table[] =
   { "cc", CCR },
 
   { "acc", ACC },
+  { "acc0", ACC },
+  { "acc1", ACC1 },
+  { "acc2", ACC2 },
+  { "acc3", ACC3 },
+  { "accext01", ACCEXT01 },
+  { "accext23", ACCEXT23 },
   { "macsr", MACSR },
   { "mask", MASK },
 
@@ -3581,6 +3791,8 @@ static const struct init_entry init_table[] =
 
   { "flashbar", FLASHBAR }, 	/* mcf528x registers.  */
   { "rambar",   RAMBAR },  	/* mcf528x registers.  */
+
+  { "mbar2",    MBAR2 },  	/* mcf5249 registers.  */
   /* End of control registers.  */
 
   { "ac", AC },
@@ -3680,23 +3892,15 @@ static const struct init_entry init_table[] =
 };
 
 static void
-init_regtable ()
+init_regtable (void)
 {
   int i;
   for (i = 0; init_table[i].name; i++)
     insert_reg (init_table[i].name, init_table[i].number);
 }
 
-static int no_68851, no_68881;
-
-#ifdef OBJ_AOUT
-/* a.out machine type.  Default to 68020.  */
-int m68k_aout_machtype = 2;
-#endif
-
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   const char *er;
   short *fromP;
@@ -3706,6 +3910,17 @@ md_assemble (str)
   int shorts_this_frag;
   fixS *fixP;
 
+  if (!selected_cpu && !selected_arch)
+    {
+      /* We've not selected an architecture yet.  Set the default
+	 now.  We do this lazily so that an initial .cpu or .arch directive
+	 can specify.  */
+      if (!m68k_set_cpu (TARGET_CPU, 1, 1))
+	as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
+    }
+  if (!initialized)
+    m68k_init_arch ();
+  
   /* In MRI mode, the instruction and operands are separated by a
      space.  Anything following the operands is a comment.  The label
      has already been removed.  */
@@ -3741,7 +3956,7 @@ md_assemble (str)
 	}
     }
 
-  memset ((char *) (&the_ins), '\0', sizeof (the_ins));
+  memset (&the_ins, '\0', sizeof (the_ins));
   m68k_ip (str);
   er = the_ins.error;
   if (!er)
@@ -3888,7 +4103,7 @@ md_assemble (str)
   shorts_this_frag = 0;
   if (n)
     {
-      toP = frag_more (n * sizeof (short));
+      toP = frag_more (n * 2);
       while (n--)
 	{
 	  md_number_to_chars (toP, (long) (*fromP), 2);
@@ -3919,13 +4134,40 @@ md_assemble (str)
     }
 }
 
+/* Comparison function used by qsort to rank the opcode entries by name.  */
+
+static int
+m68k_compare_opcode (const void * v1, const void * v2)
+{
+  struct m68k_opcode * op1, * op2;
+  int ret;
+
+  if (v1 == v2)
+    return 0;
+
+  op1 = *(struct m68k_opcode **) v1;
+  op2 = *(struct m68k_opcode **) v2;
+
+  /* Compare the two names.  If different, return the comparison.
+     If the same, return the order they are in the opcode table.  */
+  ret = strcmp (op1->name, op2->name);
+  if (ret)
+    return ret;
+  if (op1 < op2)
+    return -1;
+  return 1;
+}
+
 void
-md_begin ()
+md_begin (void)
 {
-  /*
-   * md_begin -- set up hash tables with 68000 instructions.
-   * similar to what the vax assembler does.  ---phr
-   */
+  const struct m68k_opcode *ins;
+  struct m68k_incant *hack, *slak;
+  const char *retval = 0;	/* Empty string, or error msg text.  */
+  int i;
+
+  /* Set up hash tables with 68000 instructions.
+     similar to what the vax assembler does.  */
   /* RMS claims the thing to do is take the m68k-opcode.h table, and make
      a copy of it at runtime, adding in the information we want but isn't
      there.  I think it'd be better to have an awk script hack the table
@@ -3933,11 +4175,6 @@ md_begin ()
      my lord ghod hath spoken, so we do it this way.  Excuse the ugly var
      names.  */
 
-  const struct m68k_opcode *ins;
-  struct m68k_incant *hack, *slak;
-  const char *retval = 0;	/* Empty string, or error msg text.  */
-  int i;
-
   if (flag_mri)
     {
       flag_reg_prefix_optional = 1;
@@ -3946,6 +4183,20 @@ md_begin ()
 	m68k_rel32 = 0;
     }
 
+  /* First sort the opcode table into alphabetical order to seperate
+     the order that the assembler wants to see the opcodes from the
+     order that the disassembler wants to see them.  */
+  m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
+  if (!m68k_sorted_opcodes)
+    as_fatal (_("Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"),
+	      m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
+
+  for (i = m68k_numopcodes; i--;)
+    m68k_sorted_opcodes[i] = m68k_opcodes + i;
+
+  qsort (m68k_sorted_opcodes, m68k_numopcodes,
+	 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
+
   op_hash = hash_new ();
 
   obstack_begin (&robyn, 4000);
@@ -3954,9 +4205,10 @@ md_begin ()
       hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
       do
 	{
-	  ins = &m68k_opcodes[i];
-	  /* We *could* ignore insns that don't match our arch here
-	     but just leaving them out of the hash.  */
+	  ins = m68k_sorted_opcodes[i];
+
+	  /* We *could* ignore insns that don't match our
+	     arch here by just leaving them out of the hash.  */
 	  slak->m_operands = ins->args;
 	  slak->m_opnum = strlen (slak->m_operands) / 2;
 	  slak->m_arch = ins->arch;
@@ -3964,9 +4216,9 @@ md_begin ()
 	  /* This is kludgey.  */
 	  slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
 	  if (i + 1 != m68k_numopcodes
-	      && !strcmp (ins->name, m68k_opcodes[i + 1].name))
+	      && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
 	    {
-	      slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
+	      slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
 	      i++;
 	    }
 	  else
@@ -3985,6 +4237,7 @@ md_begin ()
       const char *name = m68k_opcode_aliases[i].primary;
       const char *alias = m68k_opcode_aliases[i].alias;
       PTR val = hash_find (op_hash, name);
+
       if (!val)
 	as_fatal (_("Internal Error: Can't find %s in hash table"), name);
       retval = hash_insert (op_hash, alias, val);
@@ -4023,6 +4276,7 @@ md_begin ()
 	  const char *name = mri_aliases[i].primary;
 	  const char *alias = mri_aliases[i].alias;
 	  PTR val = hash_find (op_hash, name);
+
 	  if (!val)
 	    as_fatal (_("Internal Error: Can't find %s in hash table"), name);
 	  retval = hash_jam (op_hash, alias, val);
@@ -4036,6 +4290,7 @@ md_begin ()
       notend_table[i] = 0;
       alt_notend_table[i] = 0;
     }
+
   notend_table[','] = 1;
   notend_table['{'] = 1;
   notend_table['}'] = 1;
@@ -4052,18 +4307,15 @@ md_begin ()
 #endif
 
   /* We need to put '(' in alt_notend_table to handle
-       cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
-     */
+       cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)  */
   alt_notend_table['('] = 1;
 
   /* We need to put '@' in alt_notend_table to handle
-       cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
-     */
+       cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)  */
   alt_notend_table['@'] = 1;
 
   /* We need to put digits in alt_notend_table to handle
-       bfextu %d0{24:1},%d0
-     */
+       bfextu %d0{24:1},%d0  */
   alt_notend_table['0'] = 1;
   alt_notend_table['1'] = 1;
   alt_notend_table['2'] = 1;
@@ -4080,10 +4332,10 @@ md_begin ()
      gas expects pseudo ops to start with a dot.  */
   {
     int n = 0;
+
     while (mote_pseudo_table[n].poc_name)
       {
-	hack = (struct m68k_incant *)
-	  obstack_alloc (&robyn, sizeof (struct m68k_incant));
+	hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
 	hash_insert (op_hash,
 		     mote_pseudo_table[n].poc_name, (char *) hack);
 	hack->m_operands = 0;
@@ -4102,129 +4354,11 @@ md_begin ()
 #endif
 }
 
-static void
-select_control_regs ()
-{
-  /* Note which set of "movec" control registers is available.  */
-  switch (cpu_of_arch (current_architecture))
-    {
-    case 0:
-      as_warn (_("architecture not yet selected: defaulting to 68020"));
-      control_regs = m68020_control_regs;
-      break;
-      
-    case m68000:
-      control_regs = m68000_control_regs;
-      break;
-    case m68010:
-      control_regs = m68010_control_regs;
-      break;
-    case m68020:
-    case m68030:
-      control_regs = m68020_control_regs;
-      break;
-    case m68040:
-      control_regs = m68040_control_regs;
-      break;
-    case m68060:
-      control_regs = m68060_control_regs;
-      break;
-    case cpu32:
-      control_regs = cpu32_control_regs;
-      break;
-    case mcf5200:
-    case mcf5206e:
-    case mcf5307:
-    case mcf5407:
-      control_regs = mcf_control_regs;
-      break;
-    case mcf528x:
-      control_regs = mcf528x_control_regs;
-      break;
-    case mcfv4e:
-      control_regs = mcfv4e_control_regs;
-      break;
-    default:
-      abort ();
-    }
-}
-
-void
-m68k_init_after_args ()
-{
-  if (cpu_of_arch (current_architecture) == 0)
-    {
-      int i;
-      const char *default_cpu = TARGET_CPU;
-
-      if (*default_cpu == 'm')
-	default_cpu++;
-      for (i = 0; i < n_archs; i++)
-	if (strcasecmp (default_cpu, archs[i].name) == 0)
-	  break;
-      if (i == n_archs)
-	{
-	  as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
-	  current_architecture |= m68020;
-	}
-      else
-	current_architecture |= archs[i].arch;
-    }
-  /* Permit m68881 specification with all cpus; those that can't work
-     with a coprocessor could be doing emulation.  */
-  if (current_architecture & m68851)
-    {
-      if (current_architecture & m68040)
-	{
-	  as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
-	}
-    }
-  /* What other incompatibilities could we check for?  */
-
-  /* Toss in some default assumptions about coprocessors.  */
-  if (!no_68881
-      && (cpu_of_arch (current_architecture)
-	  /* Can CPU32 have a 68881 coprocessor??  */
-	  & (m68020 | m68030 | cpu32)))
-    {
-      current_architecture |= m68881;
-    }
-  if (!no_68851
-      && (cpu_of_arch (current_architecture) & m68020up) != 0
-      && (cpu_of_arch (current_architecture) & m68040up) == 0)
-    {
-      current_architecture |= m68851;
-    }
-  if (no_68881 && (current_architecture & m68881))
-    as_bad (_("options for 68881 and no-68881 both given"));
-  if (no_68851 && (current_architecture & m68851))
-    as_bad (_("options for 68851 and no-68851 both given"));
-
-#ifdef OBJ_AOUT
-  /* Work out the magic number.  This isn't very general.  */
-  if (current_architecture & m68000)
-    m68k_aout_machtype = 0;
-  else if (current_architecture & m68010)
-    m68k_aout_machtype = 1;
-  else if (current_architecture & m68020)
-    m68k_aout_machtype = 2;
-  else
-    m68k_aout_machtype = 2;
-#endif
-
-  /* Note which set of "movec" control registers is available.  */
-  select_control_regs ();
-
-  if (cpu_of_arch (current_architecture) < m68020
-      || arch_coldfire_p (current_architecture))
-    md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
-}
 
 /* This is called when a label is defined.  */
 
 void
-m68k_frob_label (sym)
-     symbolS *sym;
+m68k_frob_label (symbolS *sym)
 {
   struct label_line *n;
 
@@ -4235,12 +4369,16 @@ m68k_frob_label (sym)
   n->text = 0;
   labels = n;
   current_label = n;
+
+#ifdef OBJ_ELF
+  dwarf2_emit_label (sym);
+#endif
 }
 
 /* This is called when a value that is not an instruction is emitted.  */
 
 void
-m68k_flush_pending_output ()
+m68k_flush_pending_output (void)
 {
   current_label = NULL;
 }
@@ -4250,8 +4388,7 @@ m68k_flush_pending_output ()
    odd location.  */
 
 void
-m68k_frob_symbol (sym)
-     symbolS *sym;
+m68k_frob_symbol (symbolS *sym)
 {
   if (S_GET_SEGMENT (sym) == reg_section
       && (int) S_GET_VALUE (sym) < 0)
@@ -4281,8 +4418,7 @@ m68k_frob_symbol (sym)
    pseudo-op.  */
 
 void
-m68k_mri_mode_change (on)
-     int on;
+m68k_mri_mode_change (int on)
 {
   if (on)
     {
@@ -4325,10 +4461,7 @@ m68k_mri_mode_change (on)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -4379,19 +4512,13 @@ md_atof (type, litP, sizeP)
 }
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   offsetT val = *valP;
   addressT upper_limit;
@@ -4403,7 +4530,7 @@ md_apply_fix3 (fixP, valP, seg)
   buf += fixP->fx_where;
   /* End ibm compiler workaround.  */
 
-  val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000;
+  val = SEXT (val);
 
   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
     fixP->fx_done = 1;
@@ -4422,11 +4549,9 @@ md_apply_fix3 (fixP, valP, seg)
     }
 #endif
 
-#ifdef BFD_ASSEMBLER
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return;
-#endif
 
   switch (fixP->fx_size)
     {
@@ -4480,10 +4605,7 @@ md_apply_fix3 (fixP, valP, seg)
      in write.c may have clobbered fx_pcrel, so we need to examine the
      reloc type.  */
   if ((fixP->fx_pcrel
-#ifdef BFD_ASSEMBLER
-       || fixP->fx_r_type == BFD_RELOC_8_PCREL
-#endif
-       )
+       || fixP->fx_r_type == BFD_RELOC_8_PCREL)
       && fixP->fx_size == 1
       && (fixP->fx_addsy == NULL
 	  || S_IS_DEFINED (fixP->fx_addsy))
@@ -4496,8 +4618,7 @@ md_apply_fix3 (fixP, valP, seg)
    MAGIC here. ..
    */
 static void
-md_convert_frag_1 (fragP)
-     register fragS *fragP;
+md_convert_frag_1 (fragS *fragP)
 {
   long disp;
   fixS *fixP;
@@ -4549,7 +4670,7 @@ md_convert_frag_1 (fragP)
       if (fragP->fr_opcode[0] == 0x61)		/* jbsr */
 	{
 	  if (flag_keep_pcrel)
-    	    as_fatal(_("Tried to convert PC relative BSR to absolute JSR"));
+    	    as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
 	  fragP->fr_opcode[0] = 0x4E;
 	  fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand.  */
 	  fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
@@ -4559,7 +4680,7 @@ md_convert_frag_1 (fragP)
       else if (fragP->fr_opcode[0] == 0x60)	/* jbra */
 	{
 	  if (flag_keep_pcrel)
-	    as_fatal(_("Tried to convert PC relative branch to absolute jump"));
+	    as_fatal (_("Tried to convert PC relative branch to absolute jump"));
 	  fragP->fr_opcode[0] = 0x4E;
 	  fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand.  */
 	  fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
@@ -4575,7 +4696,7 @@ md_convert_frag_1 (fragP)
       break;
     case TAB (BRABSJCOND, LONG):
       if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
+    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
 
       /* Only Bcc 68000 instructions can come here
 	 Change bcc into b!cc/jmp absl long.  */
@@ -4615,7 +4736,7 @@ md_convert_frag_1 (fragP)
 	 Change dbcc into dbcc/bral.
 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
       if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert DBcc to absolute jump"));
+    	as_fatal (_("Tried to convert DBcc to absolute jump"));
 
       *buffer_address++ = 0x00;	/* Branch offset = 4.  */
       *buffer_address++ = 0x04;
@@ -4634,7 +4755,7 @@ md_convert_frag_1 (fragP)
 	 Change dbcc into dbcc/jmp.
 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
       if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
+    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
 
       *buffer_address++ = 0x00;		/* Branch offset = 4.  */
       *buffer_address++ = 0x04;
@@ -4698,7 +4819,7 @@ md_convert_frag_1 (fragP)
       break;
     case TAB (ABSTOPCREL, LONG):
       if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative conditional branch to absolute jump"));
+    	as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
       /* The thing to do here is force it to ABSOLUTE LONG, since
 	 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway.  */
       if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
@@ -4712,36 +4833,19 @@ md_convert_frag_1 (fragP)
     }
 }
 
-#ifndef BFD_ASSEMBLER
-
-void
-md_convert_frag (headers, sec, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
-{
-  md_convert_frag_1 (fragP);
-}
-
-#else
-
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
   md_convert_frag_1 (fragP);
 }
-#endif
 
 /* Force truly undefined symbols to their maximum size, and generally set up
    the frag list to be relaxed
    */
 int
-md_estimate_size_before_relax (fragP, segment)
-     register fragS *fragP;
-     segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
 {
   /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT.  */
   switch (fragP->fr_subtype)
@@ -4879,9 +4983,7 @@ md_estimate_size_before_relax (fragP, segment)
    format.  */
 #ifdef comment
 void
-md_ri_to_chars (the_bytes, ri)
-     char *the_bytes;
-     struct reloc_info_generic *ri;
+md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
 {
   /* This is easy.  */
   md_number_to_chars (the_bytes, ri->r_address, 4);
@@ -4889,57 +4991,23 @@ md_ri_to_chars (the_bytes, ri)
   the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
   the_bytes[5] = (ri->r_symbolnum >>  8) & 0x0ff;
   the_bytes[6] =  ri->r_symbolnum        & 0x0ff;
-  the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
-		  ((ri->r_extern << 4) & 0x10));
+  the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
+		  | ((ri->r_length << 5) & 0x60)
+		  | ((ri->r_extern << 4) & 0x10));
 }
 
 #endif
 
-#ifndef BFD_ASSEMBLER
-void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
-{
-  /*
-   * In: length of relocation (or of address) in chars: 1, 2 or 4.
-   * Out: GNU LD relocation length code: 0, 1, or 2.
-   */
-
-  static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
-  long r_symbolnum;
-
-  know (fixP->fx_addsy != NULL);
-
-  md_number_to_chars (where,
-       fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
-		      4);
-
-  r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
-		 ? S_GET_TYPE (fixP->fx_addsy)
-		 : fixP->fx_addsy->sy_number);
-
-  where[4] = (r_symbolnum >> 16) & 0x0ff;
-  where[5] = (r_symbolnum >> 8) & 0x0ff;
-  where[6] = r_symbolnum & 0x0ff;
-  where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
-	      (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
-}
-#endif
-
 #endif /* OBJ_AOUT or OBJ_BOUT */
 
 #ifndef WORKING_DOT_WORD
-const int md_short_jump_size = 4;
-const int md_long_jump_size = 6;
+int md_short_jump_size = 4;
+int md_long_jump_size = 6;
 
 void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
+		      fragS *frag ATTRIBUTE_UNUSED,
+		      symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
   valueT offset;
 
@@ -4950,18 +5018,15 @@ md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
 }
 
 void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag;
-     symbolS *to_symbol;
+md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
+		     fragS *frag, symbolS *to_symbol)
 {
   valueT offset;
 
-  if (!HAVE_LONG_BRANCH(current_architecture))
+  if (!HAVE_LONG_BRANCH (current_architecture))
     {
       if (flag_keep_pcrel)
-    	as_fatal(_("Tried to convert PC relative branch to absolute jump"));
+    	as_fatal (_("Tried to convert PC relative branch to absolute jump"));
       offset = to_addr - S_GET_VALUE (to_symbol);
       md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
       md_number_to_chars (ptr + 2, (valueT) offset, 4);
@@ -4994,9 +5059,7 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
    90:  No bignums.          */
 
 static int
-get_num (exp, ok)
-     struct m68k_exp *exp;
-     int ok;
+get_num (struct m68k_exp *exp, int ok)
 {
   if (exp->exp.X_op == O_absent)
     {
@@ -5016,38 +5079,38 @@ get_num (exp, ok)
       switch (ok)
 	{
 	case 10:
-	  if (offs (exp) < 1 || offs (exp) > 8)
+	  if ((valueT) TRUNC (offs (exp)) - 1 > 7)
 	    {
 	      as_warn (_("expression out of range: defaulting to 1"));
 	      offs (exp) = 1;
 	    }
 	  break;
 	case 20:
-	  if (offs (exp) < 0 || offs (exp) > 7)
+	  if ((valueT) TRUNC (offs (exp)) > 7)
 	    goto outrange;
 	  break;
 	case 30:
-	  if (offs (exp) < 0 || offs (exp) > 15)
+	  if ((valueT) TRUNC (offs (exp)) > 15)
 	    goto outrange;
 	  break;
 	case 40:
-	  if (offs (exp) < 0 || offs (exp) > 32)
+	  if ((valueT) TRUNC (offs (exp)) > 32)
 	    goto outrange;
 	  break;
 	case 50:
-	  if (offs (exp) < 0 || offs (exp) > 127)
+	  if ((valueT) TRUNC (offs (exp)) > 127)
 	    goto outrange;
 	  break;
 	case 55:
-	  if (offs (exp) < -64 || offs (exp) > 63)
+	  if ((valueT) SEXT (offs (exp)) + 64 > 127)
 	    goto outrange;
 	  break;
 	case 60:
-	  if (offs (exp) < -128 || offs (exp) > 127)
+	  if ((valueT) SEXT (offs (exp)) + 128 > 255)
 	    goto outrange;
 	  break;
 	case 70:
-	  if (offs (exp) < 0 || offs (exp) > 4095)
+	  if ((valueT) TRUNC (offs (exp)) > 4095)
 	    {
 	    outrange:
 	      as_warn (_("expression out of range: defaulting to 0"));
@@ -5055,9 +5118,8 @@ get_num (exp, ok)
 	    }
 	  break;
 	case 80:
-	  if (offs (exp) < -1
-              || offs (exp) > 7
-              || offs (exp) == 0)
+	  if ((valueT) TRUNC (offs (exp)) != 0xffffffff
+              && (valueT) TRUNC (offs (exp)) - 1 > 6)
 	    {
 	      as_warn (_("expression out of range: defaulting to 1"));
 	      offs (exp) = 1;
@@ -5093,7 +5155,7 @@ get_num (exp, ok)
 	  subs (exp) = 0;
 	  offs (exp) = (ok == 10) ? 1 : 0;
 	  as_warn (_("Can't deal with expression; defaulting to %ld"),
-		   offs (exp));
+		   (long) offs (exp));
 	}
     }
   else
@@ -5105,7 +5167,7 @@ get_num (exp, ok)
 	  subs (exp) = 0;
 	  offs (exp) = (ok == 10) ? 1 : 0;
 	  as_warn (_("Can't deal with expression; defaulting to %ld"),
-		   offs (exp));
+		   (long) offs (exp));
 	}
     }
 
@@ -5133,24 +5195,21 @@ get_num (exp, ok)
 /* These are the back-ends for the various machine dependent pseudo-ops.  */
 
 static void
-s_data1 (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_data1 (int ignore ATTRIBUTE_UNUSED)
 {
   subseg_set (data_section, 1);
   demand_empty_rest_of_line ();
 }
 
 static void
-s_data2 (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_data2 (int ignore ATTRIBUTE_UNUSED)
 {
   subseg_set (data_section, 2);
   demand_empty_rest_of_line ();
 }
 
 static void
-s_bss (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_bss (int ignore ATTRIBUTE_UNUSED)
 {
   /* We don't support putting frags in the BSS segment, we fake it
      by marking in_bss, then looking at s_skip for clues.  */
@@ -5160,8 +5219,7 @@ s_bss (ignore)
 }
 
 static void
-s_even (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_even (int ignore ATTRIBUTE_UNUSED)
 {
   register int temp;
   register long temp_fill;
@@ -5175,8 +5233,7 @@ s_even (ignore)
 }
 
 static void
-s_proc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_proc (int ignore ATTRIBUTE_UNUSED)
 {
   demand_empty_rest_of_line ();
 }
@@ -5188,8 +5245,7 @@ s_proc (ignore)
    alignment is needed.  */
 
 int
-m68k_conditional_pseudoop (pop)
-     pseudo_typeS *pop;
+m68k_conditional_pseudoop (pseudo_typeS *pop)
 {
   return (pop->poc_handler == s_mri_if
 	  || pop->poc_handler == s_mri_else);
@@ -5198,7 +5254,7 @@ m68k_conditional_pseudoop (pop)
 /* Handle an MRI style chip specification.  */
 
 static void
-mri_chip ()
+mri_chip (void)
 {
   char *s;
   char c;
@@ -5210,10 +5266,10 @@ mri_chip ()
   while (is_part_of_name (c = *input_line_pointer++))
     ;
   *--input_line_pointer = 0;
-  for (i = 0; i < n_archs; i++)
-    if (strcasecmp (s, archs[i].name) == 0)
+  for (i = 0; m68k_cpus[i].name; i++)
+    if (strcasecmp (s, m68k_cpus[i].name) == 0)
       break;
-  if (i >= n_archs)
+  if (!m68k_cpus[i].name)
     {
       as_bad (_("%s: unrecognized processor name"), s);
       *input_line_pointer = c;
@@ -5226,7 +5282,8 @@ mri_chip ()
     current_architecture = 0;
   else
     current_architecture &= m68881 | m68851;
-  current_architecture |= archs[i].arch;
+  current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
+  control_regs = m68k_cpus[i].control_regs;
 
   while (*input_line_pointer == '/')
     {
@@ -5243,16 +5300,12 @@ mri_chip ()
 	current_architecture |= m68851;
       *input_line_pointer = c;
     }
-
-  /* Update info about available control registers.  */
-  select_control_regs ();
 }
 
 /* The MRI CHIP pseudo-op.  */
 
 static void
-s_chip (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_chip (int ignore ATTRIBUTE_UNUSED)
 {
   char *stop = NULL;
   char stopc;
@@ -5268,8 +5321,7 @@ s_chip (ignore)
 /* The MRI FOPT pseudo-op.  */
 
 static void
-s_fopt (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_fopt (int ignore ATTRIBUTE_UNUSED)
 {
   SKIP_WHITESPACE ();
 
@@ -5304,7 +5356,7 @@ struct opt_action
   /* If this is not NULL, just call this function.  The first argument
      is the ARG field of this structure, the second argument is
      whether the option was negated.  */
-  void (*pfn) PARAMS ((int arg, int on));
+  void (*pfn) (int arg, int on);
 
   /* If this is not NULL, and the PFN field is NULL, set the variable
      this points to.  Set it to the ARG field if the option was not
@@ -5322,11 +5374,11 @@ struct opt_action
 
 /* The table used to handle the MRI OPT pseudo-op.  */
 
-static void skip_to_comma PARAMS ((int, int));
-static void opt_nest PARAMS ((int, int));
-static void opt_chip PARAMS ((int, int));
-static void opt_list PARAMS ((int, int));
-static void opt_list_symbols PARAMS ((int, int));
+static void skip_to_comma (int, int);
+static void opt_nest (int, int);
+static void opt_chip (int, int);
+static void opt_list (int, int);
+static void opt_list_symbols (int, int);
 
 static const struct opt_action opt_table[] =
 {
@@ -5378,8 +5430,7 @@ static const struct opt_action opt_table[] =
 /* The MRI OPT pseudo-op.  */
 
 static void
-s_opt (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_opt (int ignore ATTRIBUTE_UNUSED)
 {
   do
     {
@@ -5446,9 +5497,7 @@ s_opt (ignore)
    not support and which take arguments.  */
 
 static void
-skip_to_comma (arg, on)
-     int arg ATTRIBUTE_UNUSED;
-     int on ATTRIBUTE_UNUSED;
+skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
 {
   while (*input_line_pointer != ','
 	 && ! is_end_of_line[(unsigned char) *input_line_pointer])
@@ -5458,9 +5507,7 @@ skip_to_comma (arg, on)
 /* Handle the OPT NEST=depth option.  */
 
 static void
-opt_nest (arg, on)
-     int arg ATTRIBUTE_UNUSED;
-     int on ATTRIBUTE_UNUSED;
+opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer != '=')
     {
@@ -5475,9 +5522,7 @@ opt_nest (arg, on)
 /* Handle the OPT P=chip option.  */
 
 static void
-opt_chip (arg, on)
-     int arg ATTRIBUTE_UNUSED;
-     int on ATTRIBUTE_UNUSED;
+opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
 {
   if (*input_line_pointer != '=')
     {
@@ -5492,9 +5537,7 @@ opt_chip (arg, on)
 /* Handle the OPT S option.  */
 
 static void
-opt_list (arg, on)
-     int arg ATTRIBUTE_UNUSED;
-     int on;
+opt_list (int arg ATTRIBUTE_UNUSED, int on)
 {
   listing_list (on);
 }
@@ -5502,9 +5545,7 @@ opt_list (arg, on)
 /* Handle the OPT T option.  */
 
 static void
-opt_list_symbols (arg, on)
-     int arg ATTRIBUTE_UNUSED;
-     int on;
+opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
 {
   if (on)
     listing |= LISTING_SYMBOLS;
@@ -5515,8 +5556,7 @@ opt_list_symbols (arg, on)
 /* Handle the MRI REG pseudo-op.  */
 
 static void
-s_reg (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_reg (int ignore ATTRIBUTE_UNUSED)
 {
   char *s;
   int c;
@@ -5605,6 +5645,7 @@ struct save_opts
   int keep_locals;
   int short_refs;
   int architecture;
+  const enum m68k_register *control_regs;
   int quick;
   int rel32;
   int listing;
@@ -5619,8 +5660,7 @@ static struct save_opts *save_stack;
 /* The MRI SAVE pseudo-op.  */
 
 static void
-s_save (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_save (int ignore ATTRIBUTE_UNUSED)
 {
   struct save_opts *s;
 
@@ -5630,6 +5670,7 @@ s_save (ignore)
   s->keep_locals = flag_keep_locals;
   s->short_refs = flag_short_refs;
   s->architecture = current_architecture;
+  s->control_regs = control_regs;
   s->quick = m68k_quick;
   s->rel32 = m68k_rel32;
   s->listing = listing;
@@ -5644,8 +5685,7 @@ s_save (ignore)
 /* The MRI RESTORE pseudo-op.  */
 
 static void
-s_restore (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_restore (int ignore ATTRIBUTE_UNUSED)
 {
   struct save_opts *s;
 
@@ -5664,6 +5704,7 @@ s_restore (ignore)
   flag_keep_locals = s->keep_locals;
   flag_short_refs = s->short_refs;
   current_architecture = s->architecture;
+  control_regs = s->control_regs;
   m68k_quick = s->quick;
   m68k_rel32 = s->rel32;
   listing = s->listing;
@@ -5722,29 +5763,10 @@ static struct mri_control_info *mri_control_stack;
 
 static int mri_control_index;
 
-/* Some function prototypes.  */
-
-static void mri_assemble PARAMS ((char *));
-static char *mri_control_label PARAMS ((void));
-static struct mri_control_info *push_mri_control
-  PARAMS ((enum mri_control_type));
-static void pop_mri_control PARAMS ((void));
-static int parse_mri_condition PARAMS ((int *));
-static int parse_mri_control_operand
-  PARAMS ((int *, char **, char **, char **, char **));
-static int swap_mri_condition PARAMS ((int));
-static int reverse_mri_condition PARAMS ((int));
-static void build_mri_control_operand
-  PARAMS ((int, int, char *, char *, char *, char *, const char *,
-	   const char *, int));
-static void parse_mri_control_expression
-  PARAMS ((char *, int, const char *, const char *, int));
-
 /* Assemble an instruction for an MRI structured control directive.  */
 
 static void
-mri_assemble (str)
-     char *str;
+mri_assemble (char *str)
 {
   char *s;
 
@@ -5758,7 +5780,7 @@ mri_assemble (str)
 /* Generate a new MRI label structured control directive label name.  */
 
 static char *
-mri_control_label ()
+mri_control_label (void)
 {
   char *n;
 
@@ -5771,8 +5793,7 @@ mri_control_label ()
 /* Create a new MRI structured control directive.  */
 
 static struct mri_control_info *
-push_mri_control (type)
-     enum mri_control_type type;
+push_mri_control (enum mri_control_type type)
 {
   struct mri_control_info *n;
 
@@ -5796,7 +5817,7 @@ push_mri_control (type)
 /* Pop off the stack of MRI structured control directives.  */
 
 static void
-pop_mri_control ()
+pop_mri_control (void)
 {
   struct mri_control_info *n;
 
@@ -5812,8 +5833,7 @@ pop_mri_control ()
 /* Recognize a condition code in an MRI structured control expression.  */
 
 static int
-parse_mri_condition (pcc)
-     int *pcc;
+parse_mri_condition (int *pcc)
 {
   char c1, c2;
 
@@ -5843,12 +5863,8 @@ parse_mri_condition (pcc)
 /* Parse a single operand in an MRI structured control expression.  */
 
 static int
-parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
-     int *pcc;
-     char **leftstart;
-     char **leftstop;
-     char **rightstart;
-     char **rightstop;
+parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
+			   char **rightstart, char **rightstop)
 {
   char *s;
 
@@ -5921,8 +5937,7 @@ parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
    it generates the same result when the operands are swapped.  */
 
 static int
-swap_mri_condition (cc)
-     int cc;
+swap_mri_condition (int cc)
 {
   switch (cc)
     {
@@ -5956,8 +5971,7 @@ swap_mri_condition (cc)
 /* Reverse the sense of a condition.  */
 
 static int
-reverse_mri_condition (cc)
-     int cc;
+reverse_mri_condition (int cc)
 {
   switch (cc)
     {
@@ -5991,17 +6005,10 @@ reverse_mri_condition (cc)
    use for the branch.  */
 
 static void
-build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
-			   rightstop, truelab, falselab, extent)
-     int qual;
-     int cc;
-     char *leftstart;
-     char *leftstop;
-     char *rightstart;
-     char *rightstop;
-     const char *truelab;
-     const char *falselab;
-     int extent;
+build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
+			   char *rightstart, char *rightstop,
+			   const char *truelab, const char *falselab,
+			   int extent)
 {
   char *buf;
   char *s;
@@ -6034,20 +6041,20 @@ build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
 	{
 	  char *temp;
 
-     /* Correct conditional handling:
-        if #1 <lt> d0 then  ;means if (1 < d0)
-           ...
-        endi
+	  /* Correct conditional handling:
+	     if #1 <lt> d0 then  ;means if (1 < d0)
+		...
+	     endi
 
-        should assemble to:
+	     should assemble to:
 
-         cmp #1,d0        if we do *not* swap the operands
-         bgt true         we need the swapped condition!
-         ble false
-        true:
-         ...
-        false:
-     */
+		cmp #1,d0        if we do *not* swap the operands
+		bgt true         we need the swapped condition!
+		ble false
+	     true:
+		...
+	     false:
+	  */
 	  temp = leftstart;
 	  leftstart = rightstart;
 	  rightstart = temp;
@@ -6110,12 +6117,8 @@ build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
    expression.  EXTENT is the size to use for the branch.  */
 
 static void
-parse_mri_control_expression (stop, qual, truelab, falselab, extent)
-     char *stop;
-     int qual;
-     const char *truelab;
-     const char *falselab;
-     int extent;
+parse_mri_control_expression (char *stop, int qual, const char *truelab,
+			      const char *falselab, int extent)
 {
   int c;
   int cc;
@@ -6220,8 +6223,7 @@ parse_mri_control_expression (stop, qual, truelab, falselab, extent)
    on its operands.  */
 
 static void
-s_mri_if (qual)
-     int qual;
+s_mri_if (int qual)
 {
   char *s;
   int c;
@@ -6235,12 +6237,12 @@ s_mri_if (qual)
      This is important when assembling:
        if d0 <ne> 12(a0,d0*2) then
        if d0 <ne> #CONST*20   then.  */
-  while ( ! (    is_end_of_line[(unsigned char) *s]
-              || (     flag_mri
-                   && *s == '*'
-                   && (    s == input_line_pointer
-                        || *(s-1) == ' '
-                        || *(s-1) == '\t'))))
+  while (! (is_end_of_line[(unsigned char) *s]
+            || (flag_mri
+                && *s == '*'
+                && (s == input_line_pointer
+                    || *(s-1) == ' '
+                    || *(s-1) == '\t'))))
     ++s;
   --s;
   while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
@@ -6305,8 +6307,7 @@ s_mri_if (qual)
    it is a conditional else.  */
 
 static void
-s_mri_else (qual)
-     int qual;
+s_mri_else (int qual)
 {
   int c;
   char *buf;
@@ -6365,8 +6366,7 @@ s_mri_else (qual)
 /* Handle the MRI ENDI pseudo-op.  */
 
 static void
-s_mri_endi (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_mri_endi (int ignore ATTRIBUTE_UNUSED)
 {
   if (mri_control_stack == NULL
       || mri_control_stack->type != mri_if)
@@ -6397,8 +6397,7 @@ s_mri_endi (ignore)
 /* Handle the MRI BREAK pseudo-op.  */
 
 static void
-s_mri_break (extent)
-     int extent;
+s_mri_break (int extent)
 {
   struct mri_control_info *n;
   char *buf;
@@ -6436,8 +6435,7 @@ s_mri_break (extent)
 /* Handle the MRI NEXT pseudo-op.  */
 
 static void
-s_mri_next (extent)
-     int extent;
+s_mri_next (int extent)
 {
   struct mri_control_info *n;
   char *buf;
@@ -6475,8 +6473,7 @@ s_mri_next (extent)
 /* Handle the MRI FOR pseudo-op.  */
 
 static void
-s_mri_for (qual)
-     int qual;
+s_mri_for (int qual)
 {
   const char *varstart, *varstop;
   const char *initstart, *initstop;
@@ -6707,8 +6704,7 @@ s_mri_for (qual)
 /* Handle the MRI ENDF pseudo-op.  */
 
 static void
-s_mri_endf (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_mri_endf (int ignore ATTRIBUTE_UNUSED)
 {
   if (mri_control_stack == NULL
       || mri_control_stack->type != mri_for)
@@ -6743,8 +6739,7 @@ s_mri_endf (ignore)
 /* Handle the MRI REPEAT pseudo-op.  */
 
 static void
-s_mri_repeat (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
 {
   struct mri_control_info *n;
 
@@ -6761,8 +6756,7 @@ s_mri_repeat (ignore)
 /* Handle the MRI UNTIL pseudo-op.  */
 
 static void
-s_mri_until (qual)
-     int qual;
+s_mri_until (int qual)
 {
   char *s;
 
@@ -6800,8 +6794,7 @@ s_mri_until (qual)
 /* Handle the MRI WHILE pseudo-op.  */
 
 static void
-s_mri_while (qual)
-     int qual;
+s_mri_while (int qual)
 {
   char *s;
 
@@ -6857,8 +6850,7 @@ s_mri_while (qual)
 /* Handle the MRI ENDW pseudo-op.  */
 
 static void
-s_mri_endw (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_mri_endw (int ignore ATTRIBUTE_UNUSED)
 {
   char *buf;
 
@@ -6888,30 +6880,208 @@ s_mri_endw (ignore)
   demand_empty_rest_of_line ();
 }
 
-/*
- * md_parse_option
- *	Invocation line includes a switch not recognized by the base assembler.
- *	See if it's a processor-specific option.  These are:
- *
- *	-[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
- *	-[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
- *		Select the architecture.  Instructions or features not
- *		supported by the selected architecture cause fatal
- *		errors.  More than one may be specified.  The default is
- *		-m68020 -m68851 -m68881.  Note that -m68008 is a synonym
- *		for -m68000, and -m68882 is a synonym for -m68881.
- *	-[A]m[c]no-68851, -[A]m[c]no-68881
- *		Don't accept 688?1 instructions.  (The "c" is kind of silly,
- *		so don't use or document it, but that's the way the parsing
- *		works).
- *
- *	-pic	Indicates PIC.
- *	-k	Indicates PIC.  (Sun 3 only.)
- *      --pcrel Never turn PC-relative branches into absolute jumps.
- *
- *	--bitwise-or
- *		Permit `|' to be used in expressions.
- *
+/* Parse a .cpu directive.  */
+
+static void
+s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
+{
+  char saved_char;
+  char *name;
+
+  if (initialized)
+    {
+      as_bad (_("already assembled instructions"));
+      ignore_rest_of_line ();
+      return;
+    }
+  
+  name = input_line_pointer;
+  while (*input_line_pointer && !ISSPACE(*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
+
+  m68k_set_cpu (name, 1, 0);
+  
+  *input_line_pointer = saved_char;
+  demand_empty_rest_of_line ();
+  return;
+}
+
+/* Parse a .arch directive.  */
+
+static void
+s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
+{
+  char saved_char;
+  char *name;
+
+  if (initialized)
+    {
+      as_bad (_("already assembled instructions"));
+      ignore_rest_of_line ();
+      return;
+    }
+  
+  name = input_line_pointer;
+  while (*input_line_pointer && *input_line_pointer != ','
+	 && !ISSPACE (*input_line_pointer))
+    input_line_pointer++;
+  saved_char = *input_line_pointer;
+  *input_line_pointer = 0;
+
+  if (m68k_set_arch (name, 1, 0))
+    {
+      /* Scan extensions. */
+      do
+	{
+	  *input_line_pointer++ = saved_char;
+	  if (!*input_line_pointer || ISSPACE (*input_line_pointer))
+	    break;
+	  name = input_line_pointer;
+	  while (*input_line_pointer && *input_line_pointer != ','
+		 && !ISSPACE (*input_line_pointer))
+	    input_line_pointer++;
+	  saved_char = *input_line_pointer;
+	  *input_line_pointer = 0;
+	}
+      while (m68k_set_extension (name, 1, 0));
+    }
+  
+  *input_line_pointer = saved_char;
+  demand_empty_rest_of_line ();
+  return;
+}
+
+/* Lookup a cpu name in TABLE and return the slot found.  Return NULL
+   if none is found, the caller is responsible for emitting an error
+   message.  If ALLOW_M is non-zero, we allow an initial 'm' on the
+   cpu name, if it begins with a '6' (possibly skipping an intervening
+   'c'.  We also allow a 'c' in the same place.  if NEGATED is
+   non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
+   the option is indeed negated.  */
+
+static const struct m68k_cpu *
+m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
+		 int allow_m, int *negated)
+{
+  /* allow negated value? */
+  if (negated)
+    {
+      *negated = 0;
+
+      if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
+	{
+	  arg += 3;
+	  *negated = 1;
+	}
+    }
+  
+  /* Remove 'm' or 'mc' prefix from 68k variants.  */
+  if (allow_m)
+    {
+      if (arg[0] == 'm')
+	{
+	  if (arg[1] == '6')
+	    arg += 1;
+	  else if (arg[1] == 'c'  && arg[2] == '6')
+	    arg += 2;
+	}
+    }
+  else if (arg[0] == 'c' && arg[1] == '6')
+    arg += 1;
+
+  for (; table->name; table++)
+    if (!strcmp (arg, table->name))
+      {
+	if (table->alias < -1 || table->alias > 1)
+	  as_bad (_("`%s' is deprecated, use `%s'"),
+		  table->name, table[table->alias < 0 ? 1 : -1].name);
+	return table;
+      }
+  return 0;
+}
+
+/* Set the cpu, issuing errors if it is unrecognized, or invalid */
+
+static int
+m68k_set_cpu (char const *name, int allow_m, int silent)
+{
+  const struct m68k_cpu *cpu;
+
+  cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
+
+  if (!cpu)
+    {
+      if (!silent)
+	as_bad (_("cpu `%s' unrecognized"), name);
+      return 0;
+    }
+      
+  if (selected_cpu && selected_cpu != cpu)
+    {
+      as_bad (_("already selected `%s' processor"),
+	      selected_cpu->name);
+      return 0;
+    }
+  selected_cpu = cpu;
+  return 1;
+}
+
+/* Set the architecture, issuing errors if it is unrecognized, or invalid */
+
+static int
+m68k_set_arch (char const *name, int allow_m, int silent)
+{
+  const struct m68k_cpu *arch;
+
+  arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
+
+  if (!arch)
+    {
+      if (!silent)
+	as_bad (_("architecture `%s' unrecognized"), name);
+      return 0;
+    }
+      
+  if (selected_arch && selected_arch != arch)
+    {
+      as_bad (_("already selected `%s' architecture"),
+	      selected_arch->name);
+      return 0;
+    }
+  
+  selected_arch = arch;
+  return 1;
+}
+
+/* Set the architecture extension, issuing errors if it is
+   unrecognized, or invalid */
+
+static int
+m68k_set_extension (char const *name, int allow_m, int silent)
+{
+  int negated;
+  const struct m68k_cpu *ext;
+
+  ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
+
+  if (!ext)
+    {
+      if (!silent)
+	as_bad (_("extension `%s' unrecognized"), name);
+      return 0;
+    }
+
+  if (negated)
+    not_current_architecture |= ext->arch;
+  else
+    current_architecture |= ext->arch;
+  return 1;
+}
+
+/* md_parse_option
+   Invocation line includes a switch not recognized by the base assembler.
  */
 
 #ifdef OBJ_ELF
@@ -6943,9 +7113,7 @@ struct option md_longopts[] = {
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -6964,82 +7132,6 @@ md_parse_option (c, arg)
       flag_keep_pcrel = 1;
       break;
 
-    case 'A':
-      if (*arg == 'm')
-	arg++;
-      /* Intentional fall-through.  */
-    case 'm':
-
-      if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
-	{
-	  int i;
-	  unsigned long arch;
-	  const char *oarg = arg;
-
-	  arg += 3;
-	  if (*arg == 'm')
-	    {
-	      arg++;
-	      if (arg[0] == 'c' && arg[1] == '6')
-		arg++;
-	    }
-	  for (i = 0; i < n_archs; i++)
-	    if (!strcmp (arg, archs[i].name))
-	      break;
-	  if (i == n_archs)
-	    {
-	    unknown:
-	      as_bad (_("unrecognized option `%s'"), oarg);
-	      return 0;
-	    }
-	  arch = archs[i].arch;
-	  if (arch == m68881)
-	    no_68881 = 1;
-	  else if (arch == m68851)
-	    no_68851 = 1;
-	  else
-	    goto unknown;
-	}
-      else
-	{
-	  int i;
-
-	  if (arg[0] == 'c' && arg[1] == '6')
-	    arg++;
-
-	  for (i = 0; i < n_archs; i++)
-	    if (!strcmp (arg, archs[i].name))
-	      {
-		unsigned long arch = archs[i].arch;
-		if (cpu_of_arch (arch))
-		  /* It's a cpu spec.  */
-		  {
-		    current_architecture &= ~m68000up;
-		    current_architecture |= arch;
-		  }
-		else if (arch == m68881)
-		  {
-		    current_architecture |= m68881;
-		    no_68881 = 0;
-		  }
-		else if (arch == m68851)
-		  {
-		    current_architecture |= m68851;
-		    no_68851 = 0;
-		  }
-		else
-		  /* ??? */
-		  abort ();
-		break;
-	      }
-	  if (i == n_archs)
-	    {
-	      as_bad (_("unrecognized architecture specification `%s'"), arg);
-	      return 0;
-	    }
-	}
-      break;
-
     case OPTION_PIC:
     case 'k':
       flag_want_pic = 1;
@@ -7093,6 +7185,27 @@ md_parse_option (c, arg)
       m68k_rel32_from_cmdline = 1;
       break;
 
+    case 'A':
+#if WARN_DEPRECATED
+      as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
+		    arg, arg));
+#endif
+      /* Intentional fall-through.  */
+    case 'm':
+      if (!strncmp (arg, "arch=", 5))
+	m68k_set_arch (arg + 5, 1, 0);
+      else if (!strncmp (arg, "cpu=", 4))
+	m68k_set_cpu (arg + 4, 1, 0);
+      else if (m68k_set_extension (arg, 0, 1))
+	;
+      else if (m68k_set_arch (arg, 0, 1))
+	;
+      else if (m68k_set_cpu (arg, 0, 1))
+	;
+      else
+	return 0;
+      break;
+
     default:
       return 0;
     }
@@ -7100,9 +7213,74 @@ md_parse_option (c, arg)
   return 1;
 }
 
+/* Setup tables from the selected arch and/or cpu */
+
+static void
+m68k_init_arch (void)
+{
+  if (not_current_architecture & current_architecture)
+    {
+      as_bad (_("architecture features both enabled and disabled"));
+      not_current_architecture &= ~current_architecture;
+    }
+  if (selected_arch)
+    {
+      current_architecture |= selected_arch->arch;
+      control_regs = selected_arch->control_regs;
+    }
+  else
+    current_architecture |= selected_cpu->arch;
+  
+  current_architecture &= ~not_current_architecture;
+
+  if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
+    {
+      /* Determine which float is really meant.  */
+      if (current_architecture & (m68k_mask & ~m68881))
+	current_architecture ^= cfloat;
+      else
+	current_architecture ^= m68881;
+    }
+
+  if (selected_cpu)
+    {
+      control_regs = selected_cpu->control_regs;
+      if (current_architecture & ~selected_cpu->arch)
+	{
+	  as_bad (_("selected processor does not have all features of selected architecture"));
+	  current_architecture
+	    = selected_cpu->arch & ~not_current_architecture;
+	}
+    }
+
+  if ((current_architecture & m68k_mask)
+      && (current_architecture & ~m68k_mask))
+    {
+      as_bad (_ ("m68k and cf features both selected"));
+      if (current_architecture & m68k_mask)
+	current_architecture &= m68k_mask;
+      else
+	current_architecture &= ~m68k_mask;
+    }
+  
+  /* Permit m68881 specification with all cpus; those that can't work
+     with a coprocessor could be doing emulation.  */
+  if (current_architecture & m68851)
+    {
+      if (current_architecture & m68040)
+	as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
+    }
+  /* What other incompatibilities could we check for?  */
+
+  if (cpu_of_arch (current_architecture) < m68020
+      || arch_coldfire_p (current_architecture))
+    md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
+  
+  initialized = 1;
+}
+
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   const char *default_cpu = TARGET_CPU;
   int i;
@@ -7111,50 +7289,61 @@ md_show_usage (stream)
   /* Get the canonical name for the default target CPU.  */
   if (*default_cpu == 'm')
     default_cpu++;
-  for (i = 0; i < n_archs; i++)
+  for (i = 0; m68k_cpus[i].name; i++)
     {
-      if (strcasecmp (default_cpu, archs[i].name) == 0)
+      if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
 	{
-	  default_arch = archs[i].arch;
-	  for (i = 0; i < n_archs; i++)
-	    {
-	      if (archs[i].arch == default_arch
-		  && !archs[i].alias)
-		{
-		  default_cpu = archs[i].name;
-		  break;
-		}
-	    }
+	  default_arch = m68k_cpus[i].arch;
+	  while (m68k_cpus[i].alias > 0)
+	    i--;
+	  while (m68k_cpus[i].alias < 0)
+	    i++;
+	  default_cpu = m68k_cpus[i].name;
 	}
     }
 
   fprintf (stream, _("\
-680X0 options:\n\
--l			use 1 word for refs to undefined symbols [default 2]\n\
--m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
--m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
--m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m528x  | -m5307  |\n\
--m5407  | -mcfv4  | -mcfv4e\n\
-			specify variant of 680X0 architecture [default %s]\n\
--m68881 | -m68882 | -mno-68881 | -mno-68882\n\
-			target has/lacks floating-point coprocessor\n\
-			[default yes for 68020, 68030, and cpu32]\n"),
-          default_cpu);
+-march=<arch>		set architecture\n\
+-mcpu=<cpu>		set cpu [default %s]\n\
+"), default_cpu);
+  for (i = 0; m68k_extensions[i].name; i++)
+    fprintf (stream, _("\
+-m[no-]%-16s enable/disable%s architecture extension\n\
+"), m68k_extensions[i].name,
+	     m68k_extensions[i].alias > 0 ? " ColdFire"
+	     : m68k_extensions[i].alias < 0 ? " m68k" : "");
+  
   fprintf (stream, _("\
--m68851 | -mno-68851\n\
-			target has/lacks memory-management unit coprocessor\n\
-			[default yes for 68020 and up]\n\
+-l			use 1 word for refs to undefined symbols [default 2]\n\
 -pic, -k		generate position independent code\n\
 -S			turn jbsr into jsr\n\
 --pcrel                 never turn PC-relative branches into absolute jumps\n\
 --register-prefix-optional\n\
 			recognize register names without prefix character\n\
---bitwise-or		do not treat `|' as a comment character\n"));
-  fprintf (stream, _("\
+--bitwise-or		do not treat `|' as a comment character\n\
 --base-size-default-16	base reg without size is 16 bits\n\
 --base-size-default-32	base reg without size is 32 bits (default)\n\
 --disp-size-default-16	displacement with unknown size is 16 bits\n\
---disp-size-default-32	displacement with unknown size is 32 bits (default)\n"));
+--disp-size-default-32	displacement with unknown size is 32 bits (default)\n\
+"));
+  
+  fprintf (stream, _("Architecture variants are: "));
+  for (i = 0; m68k_archs[i].name; i++)
+    {
+      if (i)
+	fprintf (stream, " | ");
+      fprintf (stream, m68k_archs[i].name);
+    }
+  fprintf (stream, "\n");
+
+  fprintf (stream, _("Processor variants are: "));
+  for (i = 0; m68k_cpus[i].name; i++)
+    {
+      if (i)
+	fprintf (stream, " | ");
+      fprintf (stream, m68k_cpus[i].name);
+    }
+  fprintf (stream, _("\n"));
 }
 
 #ifdef TEST2
@@ -7162,7 +7351,7 @@ md_show_usage (stream)
 /* TEST2:  Test md_assemble() */
 /* Warning, this routine probably doesn't work anymore.  */
 int
-main ()
+main (void)
 {
   struct m68k_it the_ins;
   char buf[120];
@@ -7203,21 +7392,27 @@ main ()
 	      printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
 	      continue;
 	    }
-	  printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
+	  printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
+		  the_ins.operands[n].reg);
 	  if (the_ins.operands[n].b_const)
-	    printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
-	  printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
+	    printf ("Constant: '%.*s', ",
+		    1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
+		    the_ins.operands[n].b_const);
+	  printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
+		  the_ins.operands[n].isiz, the_ins.operands[n].imul);
 	  if (the_ins.operands[n].b_iadd)
-	    printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
-	  (void) putchar ('\n');
+	    printf ("Iadd: '%.*s',",
+		    1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
+		    the_ins.operands[n].b_iadd);
+	  putchar ('\n');
 	}
     }
   m68k_ip_end ();
   return 0;
 }
 
-is_label (str)
-     char *str;
+int
+is_label (char *str)
 {
   while (*str == ' ')
     str++;
@@ -7250,20 +7445,16 @@ is_label (str)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 /* Round up a section size to the appropriate boundary.  */
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
 {
 #ifdef OBJ_AOUT
-#ifdef BFD_ASSEMBLER
   /* For a.out, force the section size to be aligned.  If we don't do
      this, BFD will align it for us, but it will not write out the
      final bytes of the section.  This may be a bug in BFD, but it is
@@ -7274,7 +7465,6 @@ md_section_align (segment, size)
   align = bfd_get_section_alignment (stdoutput, segment);
   size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
 #endif
-#endif
 
   return size;
 }
@@ -7284,8 +7474,7 @@ md_section_align (segment, size)
    word.  The difference between the addresses of the offset and the
    first extension word is stored in fx_pcrel_adjust.  */
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   int adjust;
 
@@ -7297,45 +7486,78 @@ md_pcrel_from (fixP)
   return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
 }
 
-#ifndef BFD_ASSEMBLER
-#ifdef OBJ_COFF
-
-void
-tc_coff_symbol_emit_hook (ignore)
-     symbolS *ignore ATTRIBUTE_UNUSED;
-{
-}
-
-int
-tc_coff_sizemachdep (frag)
-     fragS *frag;
-{
-  switch (frag->fr_subtype & 0x3)
-    {
-    case BYTE:
-      return 1;
-    case SHORT:
-      return 2;
-    case LONG:
-      return 4;
-    default:
-      abort ();
-      return 0;
-    }
-}
-
-#endif
-#endif
 #ifdef OBJ_ELF
 void
-m68k_elf_final_processing ()
+m68k_elf_final_processing (void)
 {
+  unsigned flags = 0;
+  
+  if (arch_coldfire_fpu (current_architecture))
+    flags |= EF_M68K_CFV4E;
   /* Set file-specific flags if this is a cpu32 processor.  */
   if (cpu_of_arch (current_architecture) & cpu32)
-    elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
+    flags |= EF_M68K_CPU32;
   else if ((cpu_of_arch (current_architecture) & m68000up)
 	   && !(cpu_of_arch (current_architecture) & m68020up))
-    elf_elfheader (stdoutput)->e_flags |= EF_M68000;
+    flags |= EF_M68K_M68000;
+  
+  if (current_architecture & mcfisa_a)
+    {
+      static const unsigned isa_features[][2] =
+      {
+	{EF_M68K_ISA_A_NODIV, mcfisa_a},
+	{EF_M68K_ISA_A,	mcfisa_a|mcfhwdiv},
+	{EF_M68K_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
+	{EF_M68K_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
+	{EF_M68K_ISA_B,	mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
+	{0,0},
+      };
+      static const unsigned mac_features[][2] =
+      {
+	{EF_M68K_MAC, mcfmac},
+	{EF_M68K_EMAC, mcfemac},
+	{0,0},
+      };
+      unsigned ix;
+      unsigned pattern;
+      
+      pattern = (current_architecture
+		 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
+      for (ix = 0; isa_features[ix][1]; ix++)
+	{
+	  if (pattern == isa_features[ix][1])
+	    {
+	      flags |= isa_features[ix][0];
+	      break;
+	    }
+	}
+      if (!isa_features[ix][1])
+	{
+	cf_bad:
+	  as_warn (_("Not a defined coldfire architecture"));
+	}
+      else
+	{
+	  if (current_architecture & cfloat)
+	    flags |= EF_M68K_FLOAT | EF_M68K_CFV4E;
+
+	  pattern = current_architecture & (mcfmac|mcfemac);
+	  if (pattern)
+	    {
+	      for (ix = 0; mac_features[ix][1]; ix++)
+		{
+		  if (pattern == mac_features[ix][1])
+		    {
+		      flags |= mac_features[ix][0];
+		      break;
+		    }
+		}
+	      if (!mac_features[ix][1])
+		goto cf_bad;
+	    }
+	}
+    }
+  elf_elfheader (stdoutput)->e_flags |= flags;
 }
 #endif
 
diff --git a/gas/config/tc-m68k.h b/gas/config/tc-m68k.h
index 559d5e311ec1..fc05a9264e6a 100644
--- a/gas/config/tc-m68k.h
+++ b/gas/config/tc-m68k.h
@@ -1,6 +1,6 @@
 /* This file is tc-m68k.h
    Copyright 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003, 2004
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,14 +17,12 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_M68K 1
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
 
 #define TARGET_BYTES_BIG_ENDIAN 1
 
@@ -53,9 +51,6 @@ struct fix;
 #undef OBJ_COFF_OMIT_OPTIONAL_HEADER
 #endif
 
-#ifdef TE_LYNX
-#define TARGET_FORMAT		"coff-m68k-lynx"
-#endif
 #ifdef TE_AUX
 #define TARGET_FORMAT		"coff-m68k-aux"
 #endif
@@ -66,34 +61,11 @@ struct fix;
 #ifndef COFF_MAGIC
 #define COFF_MAGIC MC68MAGIC
 #endif
-#define BFD_ARCH bfd_arch_m68k /* for non-BFD_ASSEMBLER */
-#define TARGET_ARCH bfd_arch_m68k /* BFD_ASSEMBLER */
-#define COFF_FLAGS F_AR32W
-#define TC_COUNT_RELOC(x) ((x)->fx_addsy||(x)->fx_subsy)
-
-#define TC_COFF_FIX2RTYPE(FIX) tc_coff_fix2rtype(FIX)
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
-extern int tc_coff_sizemachdep PARAMS ((struct frag *));
-#ifdef TE_SUN3
-/* This variable contains the value to write out at the beginning of
-   the a.out file.  The 2<<16 means that this is a 68020 file instead
-   of an old-style 68000 file */
-
-#define DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE (2<<16|OMAGIC);	/* Magic byte for file header */
-#endif /* TE_SUN3 */
-
-#ifndef AOUT_MACHTYPE
-#define AOUT_MACHTYPE m68k_aout_machtype
-extern int m68k_aout_machtype;
-#endif
+#define TARGET_ARCH bfd_arch_m68k
 
 #define tc_comment_chars m68k_comment_chars
 extern const char *m68k_comment_chars;
 
-#define tc_crawl_symbol_chain(a)	{;}	/* not used */
-#define tc_headers_hook(a)		{;}	/* not used */
-#define tc_aout_pre_write_hook(x)	{;}	/* not used */
-
 #define LISTING_WORD_SIZE 2	/* A word is 2 bytes */
 #define LISTING_LHS_WIDTH 2	/* One word on the first line */
 #define LISTING_LHS_WIDTH_SECOND 2	/* One word on the second line */
@@ -106,10 +78,6 @@ extern const char *m68k_comment_chars;
 
 #if !defined (REGISTER_PREFIX_OPTIONAL)
 #if defined (M68KCOFF) || defined (OBJ_ELF)
-#ifndef BFD_ASSEMBLER
-#define LOCAL_LABEL(name) (name[0] == '.' \
-			   && (name[1] == 'L' || name[1] == '.'))
-#endif /* ! BFD_ASSEMBLER */
 #define REGISTER_PREFIX_OPTIONAL 0
 #else /* ! (COFF || ELF) */
 #define REGISTER_PREFIX_OPTIONAL 1
@@ -125,28 +93,21 @@ extern const char *m68k_comment_chars;
 #define tc_canonicalize_symbol_name(s) ((*(s) == '~' ? *(s) = '.' : '.'), s)
 /* On the Delta, dots are not required before pseudo-ops.  */
 #define NO_PSEUDO_DOT 1
-#ifndef BFD_ASSEMBLER
-#undef LOCAL_LABEL
-#define LOCAL_LABEL(name) \
-  (name[0] == '.' || (name[0] == 'L' && name[1] == '%'))
-#endif
 #endif
 
-extern void m68k_mri_mode_change PARAMS ((int));
+extern void m68k_mri_mode_change (int);
 #define MRI_MODE_CHANGE(i) m68k_mri_mode_change (i)
 
-extern int m68k_conditional_pseudoop PARAMS ((pseudo_typeS *));
+extern int m68k_conditional_pseudoop (pseudo_typeS *);
 #define tc_conditional_pseudoop(pop) m68k_conditional_pseudoop (pop)
 
-extern void m68k_frob_label PARAMS ((symbolS *));
+extern void m68k_frob_label (symbolS *);
 #define tc_frob_label(sym) m68k_frob_label (sym)
 
-extern void m68k_flush_pending_output PARAMS ((void));
+extern void m68k_flush_pending_output (void);
 #define md_flush_pending_output() m68k_flush_pending_output ()
 
-extern void m68k_frob_symbol PARAMS ((symbolS *));
-
-#ifdef BFD_ASSEMBLER
+extern void m68k_frob_symbol (symbolS *);
 
 #define tc_frob_symbol(sym,punt)				\
 do								\
@@ -167,7 +128,7 @@ while (0)
 
 #ifdef OBJ_ELF
 #define tc_fix_adjustable(X) tc_m68k_fix_adjustable(X)
-extern int tc_m68k_fix_adjustable PARAMS ((struct fix *));
+extern int tc_m68k_fix_adjustable (struct fix *);
 
 /* Target *-*-elf implies an embedded target.  No shared libs.
    *-*-uclinux also requires special casing to prevent GAS from
@@ -175,38 +136,20 @@ extern int tc_m68k_fix_adjustable PARAMS ((struct fix *));
 #define EXTERN_FORCE_RELOC \
   ((strcmp (TARGET_OS, "elf") != 0) && (strcmp (TARGET_OS, "uclinux") != 0))
 
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define elf_tc_final_processing m68k_elf_final_processing
-extern void m68k_elf_final_processing PARAMS ((void));
+extern void m68k_elf_final_processing (void);
 #endif
 
-#else /* ! BFD_ASSEMBLER */
-
-#define tc_frob_coff_symbol(sym) m68k_frob_symbol (sym)
-
-#define NO_RELOC          0
-#define RELAX_RELOC_ABS8  0
-#define RELAX_RELOC_ABS16 0
-#define RELAX_RELOC_ABS32 0
-#define RELAX_RELOC_PC8   0
-#define RELAX_RELOC_PC16  0
-#define RELAX_RELOC_PC32  0
-
-#endif /* ! BFD_ASSEMBLER */
-
 #define DIFF_EXPR_OK
 
-extern void m68k_init_after_args PARAMS ((void));
-#define tc_init_after_args m68k_init_after_args
-
-extern int m68k_parse_long_option PARAMS ((char *));
+extern int m68k_parse_long_option (char *);
 #define md_parse_long_option m68k_parse_long_option
 
 #define md_operand(x)
 
-#define TARGET_WORD_SIZE 32
 #define TARGET_ARCH bfd_arch_m68k
 
 extern struct relax_type md_relax_table[];
diff --git a/gas/config/tc-m88k.c b/gas/config/tc-m88k.c
deleted file mode 100644
index ec4acc88c3e9..000000000000
--- a/gas/config/tc-m88k.c
+++ /dev/null
@@ -1,1207 +0,0 @@
-/* m88k.c -- Assembler for the Motorola 88000
-   Contributed by Devon Bowen of Buffalo University
-   and Torbjorn Granlund of the Swedish Institute of Computer Science.
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999,
-   2000, 2001, 2002
-   Free Software Foundation, Inc.
-
-This file is part of GAS, the GNU Assembler.
-
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GAS is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
-
-#include "as.h"
-#include "safe-ctype.h"
-#include "subsegs.h"
-#include "m88k-opcode.h"
-
-struct field_val_assoc
-{
-  char *name;
-  unsigned val;
-};
-
-struct field_val_assoc cr_regs[] =
-{
-  {"PID", 0},
-  {"PSR", 1},
-  {"EPSR", 2},
-  {"SSBR", 3},
-  {"SXIP", 4},
-  {"SNIP", 5},
-  {"SFIP", 6},
-  {"VBR", 7},
-  {"DMT0", 8},
-  {"DMD0", 9},
-  {"DMA0", 10},
-  {"DMT1", 11},
-  {"DMD1", 12},
-  {"DMA1", 13},
-  {"DMT2", 14},
-  {"DMD2", 15},
-  {"DMA2", 16},
-  {"SR0", 17},
-  {"SR1", 18},
-  {"SR2", 19},
-  {"SR3", 20},
-
-  {NULL, 0},
-};
-
-struct field_val_assoc fcr_regs[] =
-{
-  {"FPECR", 0},
-  {"FPHS1", 1},
-  {"FPLS1", 2},
-  {"FPHS2", 3},
-  {"FPLS2", 4},
-  {"FPPT", 5},
-  {"FPRH", 6},
-  {"FPRL", 7},
-  {"FPIT", 8},
-
-  {"FPSR", 62},
-  {"FPCR", 63},
-
-  {NULL, 0},
-};
-
-struct field_val_assoc cmpslot[] =
-{
-/* Integer	Floating point */
-  {"nc", 0},
-  {"cp", 1},
-  {"eq", 2},
-  {"ne", 3},
-  {"gt", 4},
-  {"le", 5},
-  {"lt", 6},
-  {"ge", 7},
-  {"hi", 8},	{"ou", 8},
-  {"ls", 9},	{"ib", 9},
-  {"lo", 10},	{"in", 10},
-  {"hs", 11},	{"ob", 11},
-  {"be", 12},	{"ue", 12},
-  {"nb", 13},	{"lg", 13},
-  {"he", 14},	{"ug", 14},
-  {"nh", 15},	{"ule", 15},
-		{"ul", 16},
-		{"uge", 17},
-
-  {NULL, 0},
-};
-
-struct field_val_assoc cndmsk[] =
-{
-  {"gt0", 1},
-  {"eq0", 2},
-  {"ge0", 3},
-  {"lt0", 12},
-  {"ne0", 13},
-  {"le0", 14},
-
-  {NULL, 0},
-};
-
-struct m88k_insn
-{
-  unsigned long opcode;
-  expressionS exp;
-  enum reloc_type reloc;
-};
-
-static char *get_bf PARAMS ((char *param, unsigned *valp));
-static char *get_cmp PARAMS ((char *param, unsigned *valp));
-static char *get_cnd PARAMS ((char *param, unsigned *valp));
-static char *get_bf2 PARAMS ((char *param, int bc));
-static char *get_bf_offset_expression PARAMS ((char *param, unsigned *offsetp));
-static char *get_cr PARAMS ((char *param, unsigned *regnop));
-static char *get_fcr PARAMS ((char *param, unsigned *regnop));
-static char *get_imm16 PARAMS ((char *param, struct m88k_insn *insn));
-static char *get_o6 PARAMS ((char *param, unsigned *valp));
-static char *match_name PARAMS ((char *, struct field_val_assoc *, unsigned *));
-static char *get_reg PARAMS ((char *param, unsigned *regnop, unsigned int reg_prefix));
-static char *get_vec9 PARAMS ((char *param, unsigned *valp));
-static char *getval PARAMS ((char *param, unsigned int *valp));
-
-static char *get_pcr PARAMS ((char *param, struct m88k_insn *insn,
-		      enum reloc_type reloc));
-
-static int calcop PARAMS ((struct m88k_opcode *format,
-			   char *param, struct m88k_insn *insn));
-
-extern char *myname;
-static struct hash_control *op_hash = NULL;
-
-/* These bits should be turned off in the first address of every segment */
-int md_seg_align = 7;
-
-/* These chars start a comment anywhere in a source file (except inside
-   another comment.  */
-const char comment_chars[] = ";";
-
-/* These chars only start a comment at the beginning of a line.  */
-const char line_comment_chars[] = "#";
-
-const char line_separator_chars[] = "";
-
-/* Chars that can be used to separate mant from exp in floating point nums */
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant */
-/* as in 0f123.456 */
-/* or    0H1.234E-12 (see exp chars above) */
-const char FLT_CHARS[] = "dDfF";
-
-const pseudo_typeS md_pseudo_table[] =
-{
-  {"align", s_align_bytes, 4},
-  {"def", s_set, 0},
-  {"dfloat", float_cons, 'd'},
-  {"ffloat", float_cons, 'f'},
-  {"half", cons, 2},
-  {"bss", s_lcomm, 1},
-  {"string", stringer, 0},
-  {"word", cons, 4},
-  /* Force set to be treated as an instruction.  */
-  {"set", NULL, 0},
-  {".set", s_set, 0},
-  {NULL, NULL, 0}
-};
-
-void
-md_begin ()
-{
-  const char *retval = NULL;
-  unsigned int i = 0;
-
-  /* Initialize hash table.  */
-  op_hash = hash_new ();
-
-  while (*m88k_opcodes[i].name)
-    {
-      char *name = m88k_opcodes[i].name;
-
-      /* Hash each mnemonic and record its position.  */
-      retval = hash_insert (op_hash, name, &m88k_opcodes[i]);
-
-      if (retval != NULL)
-	as_fatal (_("Can't hash instruction '%s':%s"),
-		  m88k_opcodes[i].name, retval);
-
-      /* Skip to next unique mnemonic or end of list.  */
-      for (i++; !strcmp (m88k_opcodes[i].name, name); i++)
-	;
-    }
-}
-
-const char *md_shortopts = "";
-struct option md_longopts[] = {
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
-{
-}
-
-void
-md_assemble (op)
-     char *op;
-{
-  char *param, *thisfrag;
-  char c;
-  struct m88k_opcode *format;
-  struct m88k_insn insn;
-
-  assert (op);
-
-  /* Skip over instruction to find parameters.  */
-  for (param = op; *param != 0 && !ISSPACE (*param); param++)
-    ;
-  c = *param;
-  *param++ = '\0';
-
-  /* Try to find the instruction in the hash table.  */
-  if ((format = (struct m88k_opcode *) hash_find (op_hash, op)) == NULL)
-    {
-      as_bad (_("Invalid mnemonic '%s'"), op);
-      return;
-    }
-
-  /* Try parsing this instruction into insn.  */
-  insn.exp.X_add_symbol = 0;
-  insn.exp.X_op_symbol = 0;
-  insn.exp.X_add_number = 0;
-  insn.exp.X_op = O_illegal;
-  insn.reloc = NO_RELOC;
-
-  while (!calcop (format, param, &insn))
-    {
-      /* If it doesn't parse try the next instruction.  */
-      if (!strcmp (format[0].name, format[1].name))
-	format++;
-      else
-	{
-	  as_fatal (_("Parameter syntax error"));
-	  return;
-	}
-    }
-
-  /* Grow the current frag and plop in the opcode.  */
-  thisfrag = frag_more (4);
-  md_number_to_chars (thisfrag, insn.opcode, 4);
-
-  /* If this instruction requires labels mark it for later.  */
-  switch (insn.reloc)
-    {
-    case NO_RELOC:
-      break;
-
-    case RELOC_LO16:
-    case RELOC_HI16:
-      fix_new_exp (frag_now,
-		   thisfrag - frag_now->fr_literal + 2,
-		   2,
-		   &insn.exp,
-		   0,
-		   insn.reloc);
-      break;
-
-    case RELOC_IW16:
-      fix_new_exp (frag_now,
-		   thisfrag - frag_now->fr_literal,
-		   4,
-		   &insn.exp,
-		   0,
-		   insn.reloc);
-      break;
-
-    case RELOC_PC16:
-      fix_new_exp (frag_now,
-		   thisfrag - frag_now->fr_literal + 2,
-		   2,
-		   &insn.exp,
-		   1,
-		   insn.reloc);
-      break;
-
-    case RELOC_PC26:
-      fix_new_exp (frag_now,
-		   thisfrag - frag_now->fr_literal,
-		   4,
-		   &insn.exp,
-		   1,
-		   insn.reloc);
-      break;
-
-    default:
-      as_fatal (_("Unknown relocation type"));
-      break;
-    }
-}
-
-static int
-calcop (format, param, insn)
-     struct m88k_opcode *format;
-     char *param;
-     struct m88k_insn *insn;
-{
-  char *fmt = format->op_spec;
-  int f;
-  unsigned val;
-  unsigned opcode;
-  unsigned int reg_prefix = 'r';
-
-  insn->opcode = format->opcode;
-  opcode = 0;
-
-  for (;;)
-    {
-      if (param == 0)
-	return 0;
-      f = *fmt++;
-      switch (f)
-	{
-	case 0:
-	  insn->opcode |= opcode;
-	  return (*param == 0 || *param == '\n');
-
-	default:
-	  if (f != *param++)
-	    return 0;
-	  break;
-
-	case 'd':
-	  param = get_reg (param, &val, reg_prefix);
-	  reg_prefix = 'r';
-	  opcode |= val << 21;
-	  break;
-
-	case 'o':
-	  param = get_o6 (param, &val);
-	  opcode |= ((val >> 2) << 7);
-	  break;
-
-	case 'x':
-	  reg_prefix = 'x';
-	  break;
-
-	case '1':
-	  param = get_reg (param, &val, reg_prefix);
-	  reg_prefix = 'r';
-	  opcode |= val << 16;
-	  break;
-
-	case '2':
-	  param = get_reg (param, &val, reg_prefix);
-	  reg_prefix = 'r';
-	  opcode |= val;
-	  break;
-
-	case '3':
-	  param = get_reg (param, &val, 'r');
-	  opcode |= (val << 16) | val;
-	  break;
-
-	case 'I':
-	  param = get_imm16 (param, insn);
-	  break;
-
-	case 'b':
-	  param = get_bf (param, &val);
-	  opcode |= val;
-	  break;
-
-	case 'p':
-	  param = get_pcr (param, insn, RELOC_PC16);
-	  break;
-
-	case 'P':
-	  param = get_pcr (param, insn, RELOC_PC26);
-	  break;
-
-	case 'B':
-	  param = get_cmp (param, &val);
-	  opcode |= val;
-	  break;
-
-	case 'M':
-	  param = get_cnd (param, &val);
-	  opcode |= val;
-	  break;
-
-	case 'c':
-	  param = get_cr (param, &val);
-	  opcode |= val << 5;
-	  break;
-
-	case 'f':
-	  param = get_fcr (param, &val);
-	  opcode |= val << 5;
-	  break;
-
-	case 'V':
-	  param = get_vec9 (param, &val);
-	  opcode |= val;
-	  break;
-
-	case '?':
-	  /* Having this here repeats the warning somtimes.
-	   But can't we stand that?  */
-	  as_warn (_("Use of obsolete instruction"));
-	  break;
-	}
-    }
-}
-
-static char *
-match_name (param, assoc_tab, valp)
-     char *param;
-     struct field_val_assoc *assoc_tab;
-     unsigned *valp;
-{
-  int i;
-  char *name;
-  int name_len;
-
-  for (i = 0;; i++)
-    {
-      name = assoc_tab[i].name;
-      if (name == NULL)
-	return NULL;
-      name_len = strlen (name);
-      if (!strncmp (param, name, name_len))
-	{
-	  *valp = assoc_tab[i].val;
-	  return param + name_len;
-	}
-    }
-}
-
-static char *
-get_reg (param, regnop, reg_prefix)
-     char *param;
-     unsigned *regnop;
-     unsigned int reg_prefix;
-{
-  unsigned c;
-  unsigned regno;
-
-  c = *param++;
-  if (c == reg_prefix)
-    {
-      regno = *param++ - '0';
-      if (regno < 10)
-	{
-	  if (regno == 0)
-	    {
-	      *regnop = 0;
-	      return param;
-	    }
-	  c = *param - '0';
-	  if (c < 10)
-	    {
-	      regno = regno * 10 + c;
-	      if (c < 32)
-		{
-		  *regnop = regno;
-		  return param + 1;
-		}
-	    }
-	  else
-	    {
-	      *regnop = regno;
-	      return param;
-	    }
-	}
-      return NULL;
-    }
-  else if (c == 's' && param[0] == 'p')
-    {
-      *regnop = 31;
-      return param + 1;
-    }
-
-  return 0;
-}
-
-static char *
-get_imm16 (param, insn)
-     char *param;
-     struct m88k_insn *insn;
-{
-  enum reloc_type reloc = NO_RELOC;
-  unsigned int val;
-  char *save_ptr;
-
-  if (!strncmp (param, "hi16", 4) && !ISALNUM (param[4]))
-    {
-      reloc = RELOC_HI16;
-      param += 4;
-    }
-  else if (!strncmp (param, "lo16", 4) && !ISALNUM (param[4]))
-    {
-      reloc = RELOC_LO16;
-      param += 4;
-    }
-  else if (!strncmp (param, "iw16", 4) && !ISALNUM (param[4]))
-    {
-      reloc = RELOC_IW16;
-      param += 4;
-    }
-
-  save_ptr = input_line_pointer;
-  input_line_pointer = param;
-  expression (&insn->exp);
-  param = input_line_pointer;
-  input_line_pointer = save_ptr;
-
-  val = insn->exp.X_add_number;
-
-  if (insn->exp.X_op == O_constant)
-    {
-      /* Insert the value now, and reset reloc to NO_RELOC.  */
-      if (reloc == NO_RELOC)
-	{
-	  /* Warn about too big expressions if not surrounded by xx16.  */
-	  if (val > 0xffff)
-	    as_warn (_("Expression truncated to 16 bits"));
-	}
-
-      if (reloc == RELOC_HI16)
-	val >>= 16;
-
-      insn->opcode |= val & 0xffff;
-      reloc = NO_RELOC;
-    }
-  else if (reloc == NO_RELOC)
-    /* We accept a symbol even without lo16, hi16, etc, and assume
-       lo16 was intended.  */
-    reloc = RELOC_LO16;
-
-  insn->reloc = reloc;
-
-  return param;
-}
-
-static char *
-get_pcr (param, insn, reloc)
-     char *param;
-     struct m88k_insn *insn;
-     enum reloc_type reloc;
-{
-  char *saveptr, *saveparam;
-
-  saveptr = input_line_pointer;
-  input_line_pointer = param;
-
-  expression (&insn->exp);
-
-  saveparam = input_line_pointer;
-  input_line_pointer = saveptr;
-
-  /* Botch: We should relocate now if O_constant.  */
-  insn->reloc = reloc;
-
-  return saveparam;
-}
-
-static char *
-get_cmp (param, valp)
-     char *param;
-     unsigned *valp;
-{
-  unsigned int val;
-  char *save_ptr;
-
-  save_ptr = param;
-
-  param = match_name (param, cmpslot, valp);
-  val = *valp;
-
-  if (param == NULL)
-    {
-      param = save_ptr;
-
-      save_ptr = input_line_pointer;
-      input_line_pointer = param;
-      val = get_absolute_expression ();
-      param = input_line_pointer;
-      input_line_pointer = save_ptr;
-
-      if (val >= 32)
-	{
-	  as_warn (_("Expression truncated to 5 bits"));
-	  val %= 32;
-	}
-    }
-
-  *valp = val << 21;
-  return param;
-}
-
-static char *
-get_cnd (param, valp)
-     char *param;
-     unsigned *valp;
-{
-  unsigned int val;
-
-  if (ISDIGIT (*param))
-    {
-      param = getval (param, &val);
-
-      if (val >= 32)
-	{
-	  as_warn (_("Expression truncated to 5 bits"));
-	  val %= 32;
-	}
-    }
-  else
-    {
-      param[0] = TOLOWER (param[0]);
-      param[1] = TOLOWER (param[1]);
-
-      param = match_name (param, cndmsk, valp);
-
-      if (param == NULL)
-	return NULL;
-
-      val = *valp;
-    }
-
-  *valp = val << 21;
-  return param;
-}
-
-static char *
-get_bf2 (param, bc)
-     char *param;
-     int bc;
-{
-  int depth = 0;
-  int c;
-
-  for (;;)
-    {
-      c = *param;
-      if (c == 0)
-	return param;
-      else if (c == '(')
-	depth++;
-      else if (c == ')')
-	depth--;
-      else if (c == bc && depth <= 0)
-	return param;
-      param++;
-    }
-}
-
-static char *
-get_bf_offset_expression (param, offsetp)
-     char *param;
-     unsigned *offsetp;
-{
-  unsigned offset;
-
-  if (ISALPHA (param[0]))
-    {
-      param[0] = TOLOWER (param[0]);
-      param[1] = TOLOWER (param[1]);
-
-      param = match_name (param, cmpslot, offsetp);
-
-      return param;
-    }
-  else
-    {
-      input_line_pointer = param;
-      offset = get_absolute_expression ();
-      param = input_line_pointer;
-    }
-
-  *offsetp = offset;
-  return param;
-}
-
-static char *
-get_bf (param, valp)
-     char *param;
-     unsigned *valp;
-{
-  unsigned offset = 0;
-  unsigned width = 0;
-  char *xp;
-  char *save_ptr;
-
-  xp = get_bf2 (param, '<');
-
-  save_ptr = input_line_pointer;
-  input_line_pointer = param;
-  if (*xp == 0)
-    {
-      /* We did not find '<'.  We have an offset (width implicitly 32).  */
-      param = get_bf_offset_expression (param, &offset);
-      input_line_pointer = save_ptr;
-      if (param == NULL)
-	return NULL;
-    }
-  else
-    {
-      *xp++ = 0;		/* Overwrite the '<' */
-      param = get_bf2 (xp, '>');
-      if (*param == 0)
-	return NULL;
-      *param++ = 0;		/* Overwrite the '>' */
-
-      width = get_absolute_expression ();
-      xp = get_bf_offset_expression (xp, &offset);
-      input_line_pointer = save_ptr;
-
-      if (xp + 1 != param)
-	return NULL;
-    }
-
-  *valp = ((width % 32) << 5) | (offset % 32);
-
-  return param;
-}
-
-static char *
-get_cr (param, regnop)
-     char *param;
-     unsigned *regnop;
-{
-  unsigned regno;
-  unsigned c;
-
-  if (!strncmp (param, "cr", 2))
-    {
-      param += 2;
-
-      regno = *param++ - '0';
-      if (regno < 10)
-	{
-	  if (regno == 0)
-	    {
-	      *regnop = 0;
-	      return param;
-	    }
-	  c = *param - '0';
-	  if (c < 10)
-	    {
-	      regno = regno * 10 + c;
-	      if (c < 64)
-		{
-		  *regnop = regno;
-		  return param + 1;
-		}
-	    }
-	  else
-	    {
-	      *regnop = regno;
-	      return param;
-	    }
-	}
-      return NULL;
-    }
-
-  param = match_name (param, cr_regs, regnop);
-
-  return param;
-}
-
-static char *
-get_fcr (param, regnop)
-     char *param;
-     unsigned *regnop;
-{
-  unsigned regno;
-  unsigned c;
-
-  if (!strncmp (param, "fcr", 3))
-    {
-      param += 3;
-
-      regno = *param++ - '0';
-      if (regno < 10)
-	{
-	  if (regno == 0)
-	    {
-	      *regnop = 0;
-	      return param;
-	    }
-	  c = *param - '0';
-	  if (c < 10)
-	    {
-	      regno = regno * 10 + c;
-	      if (c < 64)
-		{
-		  *regnop = regno;
-		  return param + 1;
-		}
-	    }
-	  else
-	    {
-	      *regnop = regno;
-	      return param;
-	    }
-	}
-      return NULL;
-    }
-
-  param = match_name (param, fcr_regs, regnop);
-
-  return param;
-}
-
-static char *
-get_vec9 (param, valp)
-     char *param;
-     unsigned *valp;
-{
-  unsigned val;
-  char *save_ptr;
-
-  save_ptr = input_line_pointer;
-  input_line_pointer = param;
-  val = get_absolute_expression ();
-  param = input_line_pointer;
-  input_line_pointer = save_ptr;
-
-  if (val >= 1 << 9)
-    as_warn (_("Expression truncated to 9 bits"));
-
-  *valp = val % (1 << 9);
-
-  return param;
-}
-
-static char *
-get_o6 (param, valp)
-     char *param;
-     unsigned *valp;
-{
-  unsigned val;
-  char *save_ptr;
-
-  save_ptr = input_line_pointer;
-  input_line_pointer = param;
-  val = get_absolute_expression ();
-  param = input_line_pointer;
-  input_line_pointer = save_ptr;
-
-  if (val & 0x3)
-    as_warn (_("Removed lower 2 bits of expression"));
-
-  *valp = val;
-
-  return (param);
-}
-
-#define hexval(z) \
-  (ISDIGIT (z) ? (z) - '0' :						\
-   ISLOWER (z) ? (z) - 'a' + 10 : 					\
-   ISUPPER (z) ? (z) - 'A' + 10 : (unsigned) -1)
-
-static char *
-getval (param, valp)
-     char *param;
-     unsigned int *valp;
-{
-  unsigned int val = 0;
-  unsigned int c;
-
-  c = *param++;
-  if (c == '0')
-    {
-      c = *param++;
-      if (c == 'x' || c == 'X')
-	{
-	  c = *param++;
-	  c = hexval (c);
-	  while (c < 16)
-	    {
-	      val = val * 16 + c;
-	      c = *param++;
-	      c = hexval (c);
-	    }
-	}
-      else
-	{
-	  c -= '0';
-	  while (c < 8)
-	    {
-	      val = val * 8 + c;
-	      c = *param++ - '0';
-	    }
-	}
-    }
-  else
-    {
-      c -= '0';
-      while (c < 10)
-	{
-	  val = val * 10 + c;
-	  c = *param++ - '0';
-	}
-    }
-
-  *valp = val;
-  return param - 1;
-}
-
-void
-md_number_to_chars (buf, val, nbytes)
-     char *buf;
-     valueT val;
-     int nbytes;
-{
-  number_to_chars_bigendian (buf, val, nbytes);
-}
-
-#define MAX_LITTLENUMS 6
-
-/* Turn a string in input_line_pointer into a floating point constant of type
-   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
-   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.
- */
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to MD_ATOF()");
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  for (wordP = words; prec--;)
-    {
-      md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return 0;
-}
-
-int md_short_jump_size = 4;
-
-void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr ATTRIBUTE_UNUSED;
-     addressT to_addr ATTRIBUTE_UNUSED;
-     fragS *frag;
-     symbolS *to_symbol;
-{
-  ptr[0] = (char) 0xc0;
-  ptr[1] = 0x00;
-  ptr[2] = 0x00;
-  ptr[3] = 0x00;
-  fix_new (frag,
-	   ptr - frag->fr_literal,
-	   4,
-	   to_symbol,
-	   (offsetT) 0,
-	   0,
-	   RELOC_PC26);		/* Botch: Shouldn't this be RELOC_PC16? */
-}
-
-int md_long_jump_size = 4;
-
-void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr ATTRIBUTE_UNUSED;
-     addressT to_addr ATTRIBUTE_UNUSED;
-     fragS *frag;
-     symbolS *to_symbol;
-{
-  ptr[0] = (char) 0xc0;
-  ptr[1] = 0x00;
-  ptr[2] = 0x00;
-  ptr[3] = 0x00;
-  fix_new (frag,
-	   ptr - frag->fr_literal,
-	   4,
-	   to_symbol,
-	   (offsetT) 0,
-	   0,
-	   RELOC_PC26);
-}
-
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     fragS *fragP ATTRIBUTE_UNUSED;
-     segT segment_type ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("Relaxation should never occur"));
-  return (-1);
-}
-
-#ifdef M88KCOFF
-
-/* These functions are needed if we are linking with obj-coffbfd.c.
-   That file may be replaced by a more BFD oriented version at some
-   point.  If that happens, these functions should be reexamined.
-
-   Ian Lance Taylor, Cygnus Support, 13 July 1993.  */
-
-/* Given a fixS structure (created by a call to fix_new, above),
-   return the BFD relocation type to use for it.  */
-
-short
-tc_coff_fix2rtype (fixp)
-     fixS *fixp;
-{
-  switch (fixp->fx_r_type)
-    {
-    case RELOC_LO16:
-      return R_LVRT16;
-    case RELOC_HI16:
-      return R_HVRT16;
-    case RELOC_PC16:
-      return R_PCR16L;
-    case RELOC_PC26:
-      return R_PCR26L;
-    case RELOC_32:
-      return R_VRT32;
-    case RELOC_IW16:
-      return R_VRT16;
-    default:
-      abort ();
-    }
-}
-
-/* Apply a fixS to the object file.  Since COFF does not use addends
-   in relocs, the addend is actually stored directly in the object
-   file itself.  */
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = * (long *) valP;
-  char *buf;
-
-  buf = fixP->fx_frag->fr_literal + fixP->fx_where;
-  fixP->fx_offset = 0;
-
-  switch (fixP->fx_r_type)
-    {
-    case RELOC_IW16:
-      fixP->fx_offset = val >> 16;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_LO16:
-      fixP->fx_offset = val >> 16;
-      buf[0] = val >> 8;
-      buf[1] = val;
-      break;
-
-    case RELOC_HI16:
-      fixP->fx_offset = val >> 16;
-      buf[0] = val >> 8;
-      buf[1] = val;
-      break;
-
-    case RELOC_PC16:
-      buf[0] = val >> 10;
-      buf[1] = val >> 2;
-      break;
-
-    case RELOC_PC26:
-      buf[0] |= (val >> 26) & 0x03;
-      buf[1] = val >> 18;
-      buf[2] = val >> 10;
-      buf[3] = val >> 2;
-      break;
-
-    case RELOC_32:
-      buf[0] = val >> 24;
-      buf[1] = val >> 16;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    default:
-      abort ();
-    }
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-}
-
-/* Where a PC relative offset is calculated from.  On the m88k they
-   are calculated from just after the instruction.  */
-
-long
-md_pcrel_from (fixp)
-     fixS *fixp;
-{
-  switch (fixp->fx_r_type)
-    {
-    case RELOC_PC16:
-      return fixp->fx_frag->fr_address + fixp->fx_where - 2;
-    case RELOC_PC26:
-      return fixp->fx_frag->fr_address + fixp->fx_where;
-    default:
-      abort ();
-    }
-  /*NOTREACHED*/
-}
-
-/* Fill in rs_align_code fragments.  */
-
-void
-m88k_handle_align (fragp)
-     fragS *fragp;
-{
-  static const unsigned char nop_pattern[] = { 0xf4, 0x00, 0x58, 0x00 };
-
-  int bytes;
-  char *p;
-
-  if (fragp->fr_type != rs_align_code)
-    return;
-
-  bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
-  p = fragp->fr_literal + fragp->fr_fix;
-
-  if (bytes & 3)
-    {
-      int fix = bytes & 3;
-      memset (p, 0, fix);
-      p += fix;
-      bytes -= fix;
-      fragp->fr_fix += fix;
-    }
-
-  memcpy (p, nop_pattern, 4);
-  fragp->fr_var = 4;
-}
-
-#endif /* M88KCOFF */
diff --git a/gas/config/tc-m88k.h b/gas/config/tc-m88k.h
deleted file mode 100644
index 5b0a83515293..000000000000
--- a/gas/config/tc-m88k.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* m88k.h -- Assembler for the Motorola 88000
-   Contributed by Devon Bowen of Buffalo University
-   and Torbjorn Granlund of the Swedish Institute of Computer Science.
-   Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000,
-   2002 Free Software Foundation, Inc.
-
-This file is part of GAS, the GNU Assembler.
-
-GAS is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GAS is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
-
-#define TC_M88K
-
-#define TARGET_BYTES_BIG_ENDIAN 1
-
-#ifdef M88KCOFF
-#define COFF_MAGIC MC88OMAGIC
-#define BFD_ARCH bfd_arch_m88k
-#define COFF_FLAGS F_AR32W
-#endif
-
-#define NEED_FX_R_TYPE
-#define TC_KEEP_FX_OFFSET
-#define TC_CONS_RELOC RELOC_32
-
-/* different type of relocation available in the m88k */
-
-enum reloc_type
-{
-  RELOC_LO16,			/* lo16(sym) */
-  RELOC_HI16,			/* hi16(sym) */
-  RELOC_PC16,			/* bb0, bb1, bcnd */
-  RELOC_PC26,			/* br, bsr */
-  RELOC_32,			/* jump tables, etc */
-  RELOC_IW16,			/* global access through linker regs 28 */
-  NO_RELOC
-};
-
-struct reloc_info_m88k
-{
-  unsigned long int r_address;
-  unsigned int r_symbolnum:24;
-  unsigned int r_extern:1;
-  unsigned int r_pad:3;
-  enum reloc_type r_type:4;
-  long int r_addend;
-};
-
-#define relocation_info reloc_info_m88k
-
-/* The m88k uses '@' to start local labels.  */
-#define LEX_AT (LEX_BEGIN_NAME | LEX_NAME)
-
-#ifndef BFD_ASSEMBLER
-#define LOCAL_LABEL(name) \
-  ((name[0] =='@' && (name [1] == 'L' || name [1] == '.')) \
-   || (name[0] == 'L' && name[1] == '0' && name[2] == '\001'))
-#endif
-
-/* The m88k uses pseudo-ops with no leading period.  */
-#define NO_PSEUDO_DOT 1
-
-/* Don't warn on word overflow; it happens on %hi relocs.  */
-#undef WARN_SIGNED_OVERFLOW_WORD
-
-#define md_convert_frag(b,s,f)		{as_fatal (_("m88k convert_frag\n"));}
-
-/* We don't need to do anything special for undefined symbols.  */
-#define md_undefined_symbol(s) 0
-
-/* We have no special operand handling.  */
-#define md_operand(e)
-
-#ifdef M88KCOFF
-
-/* Whether a reloc should be output.  */
-#define TC_COUNT_RELOC(fixp) ((fixp)->fx_addsy != NULL)
-
-/* Get the BFD reloc type to use for a gas fixS structure.  */
-#define TC_COFF_FIX2RTYPE(fixp) tc_coff_fix2rtype (fixp)
-
-/* No special hook needed for symbols.  */
-#define tc_coff_symbol_emit_hook(s)
-
-/* Align sections to a four byte boundary.  */
-#ifndef max
-#define max(a,b)	(((a) > (b)) ? (a) : (b))
-#endif
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)	max (section_alignment[(int) (SEG)], 4)
-
-/* Fill in rs_align_code fragments.  */
-extern void m88k_handle_align PARAMS ((fragS *));
-#define HANDLE_ALIGN(frag)  m88k_handle_align (frag)
-
-#define MAX_MEM_FOR_RS_ALIGN_CODE  (3 + 4)
-
-#endif /* M88KCOFF */
diff --git a/gas/config/tc-maxq.c b/gas/config/tc-maxq.c
new file mode 100644
index 000000000000..c1a11afc05fd
--- /dev/null
+++ b/gas/config/tc-maxq.c
@@ -0,0 +1,3119 @@
+/* tc-maxq.c -- assembler code for a MAXQ chip.
+
+   Copyright 2004, 2005 Free Software Foundation, Inc.
+
+   Contributed by HCL Technologies Pvt. Ltd.
+
+   Author: Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com)
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify it under the
+   terms of the GNU General Public License as published by the Free Software
+   Foundation; either version 2, or (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+   details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "dwarf2dbg.h"
+#include "tc-maxq.h"
+#include "opcode/maxq.h"
+#include "ctype.h"
+
+#ifndef MAXQ10S
+#define MAXQ10S 1
+#endif
+
+#ifndef _STRING_H
+#include "string.h"
+#endif
+
+#ifndef DEFAULT_ARCH
+#define DEFAULT_ARCH "MAXQ20"
+#endif
+
+#ifndef MAX_OPERANDS
+#define MAX_OPERANDS 2
+#endif
+
+#ifndef MAX_MNEM_SIZE
+#define MAX_MNEM_SIZE 8
+#endif
+
+#ifndef END_OF_INSN
+#define END_OF_INSN '\0'
+#endif
+
+#ifndef IMMEDIATE_PREFIX
+#define IMMEDIATE_PREFIX '#'
+#endif
+
+#ifndef MAX_REG_NAME_SIZE
+#define MAX_REG_NAME_SIZE 4
+#endif
+
+#ifndef MAX_MEM_NAME_SIZE
+#define MAX_MEM_NAME_SIZE 9
+#endif
+
+/* opcode for PFX[0].  */
+#define PFX0 0x0b
+
+/* Set default to MAXQ20.  */
+unsigned int max_version = bfd_mach_maxq20;
+
+const char *default_arch = DEFAULT_ARCH;
+
+/* Type of the operand: Register,Immediate,Memory access,flag or bit.  */
+
+union _maxq20_op
+{
+  const reg_entry *  reg;
+  char               imms; /* This is to store the immediate value operand.  */
+  expressionS *      disps;
+  symbolS *          data;
+  const mem_access * mem;
+  int                flag;
+  const reg_bit *    r_bit;
+};
+
+typedef union _maxq20_op maxq20_opcode;
+
+/* For handling optional L/S in Maxq20.  */
+
+/* Exposed For Linker - maps indirectly to the liker relocations.  */
+#define LONG_PREFIX  		MAXQ_LONGJUMP	/* BFD_RELOC_16 */
+#define SHORT_PREFIX 		MAXQ_SHORTJUMP	/* BFD_RELOC_16_PCREL_S2 */
+#define ABSOLUTE_ADDR_FOR_DATA 	MAXQ_INTERSEGMENT
+
+#define NO_PREFIX    		0
+#define EXPLICT_LONG_PREFIX     14
+
+/* The main instruction structure containing fields to describe instrn */
+typedef struct _maxq20_insn
+{
+  /* The opcode information for the MAXQ20 */
+  MAXQ20_OPCODE_INFO op;
+
+  /* The number of operands */
+  unsigned int operands;
+
+  /* Number of different types of operands - Comments can be removed if reqd. 
+   */
+  unsigned int reg_operands, mem_operands, disp_operands, data_operands;
+  unsigned int imm_operands, imm_bit_operands, bit_operands, flag_operands;
+
+  /* Types of the individual operands */
+  UNKNOWN_OP types[MAX_OPERANDS];
+
+  /* Relocation type for operand : to be investigated into */
+  int reloc[MAX_OPERANDS];
+
+  /* Complete information of the Operands */
+  maxq20_opcode maxq20_op[MAX_OPERANDS];
+
+  /* Choice of prefix register whenever needed */
+  int prefix;
+
+  /* Optional Prefix for Instructions like LJUMP, SJUMP etc */
+  unsigned char Instr_Prefix;
+
+  /* 16 bit Instruction word */
+  unsigned char instr[2];
+}
+maxq20_insn;
+
+/* Definitions of all possible characters that can start an operand.  */
+const char *extra_symbol_chars = "@(#";
+
+/* Special Character that would start a comment.  */
+const char comment_chars[] = ";";
+
+/* Starts a comment when it appears at the start of a line.  */
+const char line_comment_chars[] = ";#";
+
+const char line_separator_chars[] = "";	/* originally may b by sudeep "\n".  */
+
+/*  The following are used for option processing.  */
+
+/* This is added to the mach independent string passed to getopt.  */
+const char *md_shortopts = "q";
+
+/* Characters for exponent and floating point.  */
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "";
+
+/* This is for the machine dependent option handling.  */
+#define OPTION_EB               (OPTION_MD_BASE + 0)
+#define OPTION_EL               (OPTION_MD_BASE + 1)
+#define MAXQ_10                 (OPTION_MD_BASE + 2)
+#define MAXQ_20			(OPTION_MD_BASE + 3)
+
+struct option md_longopts[] =
+{
+  {"MAXQ10", no_argument, NULL, MAXQ_10},
+  {"MAXQ20", no_argument, NULL, MAXQ_20},
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+/* md_undefined_symbol We have no need for this function.  */
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+  return NULL;
+}
+
+static void
+maxq_target (int target)
+{
+  max_version = target;
+  bfd_set_arch_mach (stdoutput, bfd_arch_maxq, max_version);
+}
+
+int
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
+{
+  /* Any options support will be added onto this switch case.  */
+  switch (c)
+    {
+    case MAXQ_10:
+      max_version = bfd_mach_maxq10;
+      break;
+    case MAXQ_20:
+      max_version = bfd_mach_maxq20;
+      break;
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+/* When a usage message is printed, this function is called and
+   it prints a description of the machine specific options.  */
+
+void
+md_show_usage (FILE * stream)
+{
+  /* Over here we will fill the description of the machine specific options.  */
+
+  fprintf (stream, _(" MAXQ-specific assembler options:\n"));
+
+  fprintf (stream, _("\
+	-MAXQ20		       generate obj for MAXQ20(default)\n\
+	-MAXQ10		       generate obj for MAXQ10\n\
+	"));
+}
+
+unsigned long
+maxq20_mach (void)
+{
+  if (!(strcmp (default_arch, "MAXQ20")))
+    return 0;
+
+  as_fatal (_("Unknown architecture"));
+  return 1;
+}
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *rel;
+  bfd_reloc_code_real_type code;
+
+  switch (fixp->fx_r_type)
+    {
+    case MAXQ_INTERSEGMENT:
+    case MAXQ_LONGJUMP:
+    case BFD_RELOC_16_PCREL_S2:
+      code = fixp->fx_r_type;
+      break;
+
+    case 0:
+    default:
+      switch (fixp->fx_size)
+	{
+	default:
+	  as_bad_where (fixp->fx_file, fixp->fx_line,
+			_("can not do %d byte relocation"), fixp->fx_size);
+	  code = BFD_RELOC_32;
+	  break;
+
+	case 1:
+	  code = BFD_RELOC_8;
+	  break;
+	case 2:
+	  code = BFD_RELOC_16;
+	  break;
+	case 4:
+	  code = BFD_RELOC_32;
+	  break;
+	}
+    }
+
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+
+  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  rel->addend  = fixp->fx_addnumber;
+  rel->howto   = bfd_reloc_type_lookup (stdoutput, code);
+
+  if (rel->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("cannot represent relocation type %s"),
+		    bfd_get_reloc_code_name (code));
+
+      /* Set howto to a garbage value so that we can keep going.  */
+      rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
+      assert (rel->howto != NULL);
+    }
+
+  return rel;
+}
+
+/* md_estimate_size_before_relax()
+
+   Called just before relax() for rs_machine_dependent frags.  The MAXQ
+   assembler uses these frags to handle 16 bit absolute jumps which require a 
+   prefix instruction to be inserted. Any symbol that is now undefined will
+   not become defined. Return the correct fr_subtype in the frag. Return the
+   initial "guess for variable size of frag"(This will be eiter 2 or 0) to
+   caller. The guess is actually the growth beyond the fixed part.  Whatever
+   we do to grow the fixed or variable part contributes to our returned
+   value.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP, segT segment)
+{
+  /* Check whether the symbol has been resolved or not.
+     Otherwise we will have to generate a fixup.  */
+  if ((S_GET_SEGMENT (fragP->fr_symbol) != segment)
+      || fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+    {
+      RELOC_ENUM reloc_type;
+      unsigned char *opcode;
+      int old_fr_fix;
+
+      /* Now this symbol has not been defined in this file.
+	 Hence we will have to create a fixup.  */
+      int size = 2;
+
+      /* This is for the prefix instruction.  */
+
+      if (fragP->fr_subtype == EXPLICT_LONG_PREFIX)
+	fragP->fr_subtype = LONG_PREFIX;
+
+      if (S_GET_SEGMENT (fragP->fr_symbol) != segment
+	  && ((!(fragP->fr_subtype) == EXPLICT_LONG_PREFIX)))
+	fragP->fr_subtype = ABSOLUTE_ADDR_FOR_DATA;
+
+      reloc_type =
+	(fragP->fr_subtype ? fragP->fr_subtype : ABSOLUTE_ADDR_FOR_DATA);
+
+      fragP->fr_subtype = reloc_type;
+
+      if (reloc_type == SHORT_PREFIX)
+	size = 0;
+      old_fr_fix = fragP->fr_fix;
+      opcode = (unsigned char *) fragP->fr_opcode;
+
+      fragP->fr_fix += (size);
+
+      fix_new (fragP, old_fr_fix - 2, size + 2,
+	       fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+      frag_wane (fragP);
+      return fragP->fr_fix - old_fr_fix;
+    }
+
+  if (fragP->fr_subtype == SHORT_PREFIX)
+    {
+      fragP->fr_subtype = SHORT_PREFIX;
+      return 0;
+    }
+
+  if (fragP->fr_subtype == NO_PREFIX || fragP->fr_subtype == LONG_PREFIX)
+    {
+      unsigned long instr;
+      unsigned long call_addr;
+      long diff;
+      fragS *f;
+      diff = diff ^ diff;;
+      call_addr = call_addr ^ call_addr;
+      instr = 0;
+      f = NULL;
+
+      /* segment_info_type *seginfo = seg_info (segment);  */
+      instr = fragP->fr_address + fragP->fr_fix - 2;
+
+      /* This is the offset if it is a PC relative jump.  */
+      call_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
+
+      /* PC stores the value of the next instruction.  */
+      diff = (call_addr - instr) - 1;
+
+      if (diff >= (-128 * 2) && diff <= (2 * 127))
+	{
+	  /* Now as offset is an 8 bit value, we will pass
+	     that to the jump instruction directly.  */
+	  fragP->fr_subtype = NO_PREFIX;
+	  return 0;
+	}
+
+      fragP->fr_subtype = LONG_PREFIX;
+      return 2;
+    }
+
+  as_fatal (_("Illegal Reloc type in md_estimate_size_before_relax for line : %d"),
+	    frag_now->fr_line);
+  return 0;
+}
+
+/* Equal to MAX_PRECISION in atof-ieee.c */
+#define MAX_LITTLENUMS 6
+
+/* Turn a string in input_line_pointer into a floating point constant of type 
+   TYPE, and store the appropriate bytes in *LITP.  The number of LITTLENUMS
+   emitted is stored in *SIZEP.  An error message is returned, or NULL on OK.  */
+
+char *
+md_atof (int type, char * litP, int * sizeP)
+{
+  int prec;
+  LITTLENUM_TYPE words[4];
+  char *t;
+  int i;
+
+  switch (type)
+    {
+    case 'f':
+      prec = 2;
+      break;
+
+    case 'd':
+      prec = 2;
+      /* The size of Double has been changed to 2 words ie 32 bits.  */
+      /* prec = 4; */
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("bad call to md_atof");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * 2;
+
+  for (i = prec - 1; i >= 0; i--)
+    {
+      md_number_to_chars (litP, (valueT) words[i], 2);
+      litP += 2;
+    }
+
+  return NULL;
+}
+
+void
+maxq20_cons_fix_new (fragS * frag, unsigned int off, unsigned int len,
+		     expressionS * exp)
+{
+  int r = 0;
+
+  switch (len)
+    {
+    case 2:
+      r = MAXQ_WORDDATA;	/* Word+n */
+      break;
+    case 4:
+      r = MAXQ_LONGDATA;	/* Long+n */
+      break;
+    }
+
+  fix_new_exp (frag, off, len, exp, 0, r);
+  return;
+}
+
+/* GAS will call this for every rs_machine_dependent fragment. The
+   instruction is compleated using the data from the relaxation pass. It may
+   also create any necessary relocations.  */
+void
+md_convert_frag (bfd *   headers ATTRIBUTE_UNUSED,
+		 segT    seg ATTRIBUTE_UNUSED,
+		 fragS * fragP)
+{
+  char *opcode;
+  offsetT target_address;
+  offsetT opcode_address;
+  offsetT displacement_from_opcode_start;
+  int address;
+
+  opcode = fragP->fr_opcode;
+  address = 0;
+  target_address = opcode_address = displacement_from_opcode_start = 0;
+
+  target_address =
+    (S_GET_VALUE (fragP->fr_symbol) / MAXQ_OCTETS_PER_BYTE) +
+    (fragP->fr_offset / MAXQ_OCTETS_PER_BYTE);
+
+  opcode_address =
+    (fragP->fr_address / MAXQ_OCTETS_PER_BYTE) +
+    ((fragP->fr_fix - 2) / MAXQ_OCTETS_PER_BYTE);
+
+  /* PC points to the next Instruction.  */
+  displacement_from_opcode_start = ((target_address - opcode_address)  - 1);
+
+  if ((displacement_from_opcode_start >= -128
+       && displacement_from_opcode_start <= 127)
+      && (fragP->fr_subtype == SHORT_PREFIX
+	  || fragP->fr_subtype == NO_PREFIX))
+    {
+      /* Its a displacement.  */
+      *opcode = (char) displacement_from_opcode_start;
+    }
+  else
+    {
+      /* Its an absolute 16 bit jump. Now we have to
+	 load the prefix operator with the upper 8 bits.  */
+      if (fragP->fr_subtype == SHORT_PREFIX)
+	{
+	  as_bad (_("Cant make long jump/call into short jump/call : %d"),
+		  fragP->fr_line);
+	  return;
+	}
+
+      /* Check whether the symbol has been resolved or not.
+	 Otherwise we will have to generate a fixup.  */
+
+      if (fragP->fr_subtype != SHORT_PREFIX)
+	{
+	  RELOC_ENUM reloc_type;
+	  int old_fr_fix;
+	  int size = 2;
+
+	  /* Now this is a basolute jump/call.
+	     Hence we will have to create a fixup.  */
+	  if (fragP->fr_subtype == NO_PREFIX)
+	    fragP->fr_subtype = LONG_PREFIX;
+
+	  reloc_type =
+	    (fragP->fr_subtype ? fragP->fr_subtype : LONG_PREFIX);
+
+	  if (reloc_type == 1)
+	    size = 0;
+	  old_fr_fix = fragP->fr_fix;
+
+	  fragP->fr_fix += (size);
+
+	  fix_new (fragP, old_fr_fix - 2, size + 2,
+		   fragP->fr_symbol, fragP->fr_offset, 0, reloc_type);
+	  frag_wane (fragP);
+	}
+    }
+}
+
+long
+md_pcrel_from (fixS *fixP)
+{
+  return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+/* Writes the val to the buf, where n is the nuumber of bytes to write.  */
+
+void
+maxq_number_to_chars (char *buf, valueT val, int n)
+{
+  if (target_big_endian)
+    number_to_chars_bigendian (buf, val, n);
+  else
+    number_to_chars_littleendian (buf, val, n);
+}
+
+/* GAS will call this for each fixup. It's main objective is to store the
+   correct value in the object file. 'fixup_segment' performs the generic
+   overflow check on the 'valueT *val' argument after md_apply_fix returns.
+   If the overflow check is relevant for the target machine, then
+   'md_apply_fix' should modify 'valueT *val', typically to the value stored 
+   in the object file (not to be done in MAXQ).  */
+
+void
+md_apply_fix (fixS *fixP, valueT *valT, segT seg ATTRIBUTE_UNUSED)
+{
+  char *p = fixP->fx_frag->fr_literal + fixP->fx_where;
+  char *frag_to_fix_at =
+    fixP->fx_frag->fr_literal + fixP->fx_frag->fr_fix - 2;
+
+  if (fixP)
+    {
+      if (fixP->fx_frag && valT)
+	{
+	  /* If the relaxation substate is not defined we make it equal
+	     to the kind of relocation the fixup is generated for.  */
+	  if (!fixP->fx_frag->fr_subtype)
+	    fixP->fx_frag->fr_subtype = fixP->fx_r_type;
+
+	  /* For any instruction in which either we have specified an
+	     absolute address or it is a long jump we need to add a PFX0
+	     instruction to it. In this case as the instruction has already
+	     being written at 'fx_where' in the frag we copy it at the end of 
+	     the frag(which is where the relocation was generated) as when
+	     the relocation is generated the frag is grown by 2 type, this is 
+	     where we copy the contents of fx_where and add a pfx0 at
+	     fx_where.  */
+	  if ((fixP->fx_frag->fr_subtype == ABSOLUTE_ADDR_FOR_DATA)
+	      || (fixP->fx_frag->fr_subtype == LONG_PREFIX))
+	    {
+	      *(frag_to_fix_at + 1) = *(p + 1);
+	      maxq_number_to_chars (p + 1, PFX0, 1);
+	    }
+
+	  /* Remember value for tc_gen_reloc.  */
+	  fixP->fx_addnumber = *valT;
+	}
+
+      /* Some fixups generated by GAS which gets resovled before this this
+         func. is called need to be wriiten to the frag as here we are going
+         to go away with the relocations fx_done=1.  */
+      if (fixP->fx_addsy == NULL)
+	{
+	  maxq_number_to_chars (p, *valT, fixP->fx_size);
+	  fixP->fx_addnumber = *valT;
+	  fixP->fx_done = 1;
+	}
+    }
+}
+
+/* Tables for lexical analysis.  */
+static char mnemonic_chars[256];
+static char register_chars[256];
+static char operand_chars[256];
+static char identifier_chars[256];
+static char digit_chars[256];
+
+/* Lexical Macros.  */
+#define is_mnemonic_char(x)   (mnemonic_chars[(unsigned char)(x)])
+#define is_register_char(x)   (register_chars[(unsigned char)(x)])
+#define is_operand_char(x)    (operand_chars[(unsigned char)(x)])
+#define is_space_char(x)      (x==' ')
+#define is_identifier_char(x) (identifier_chars[(unsigned char)(x)])
+#define is_digit_char(x)      (identifier_chars[(unsigned char)(x)])
+
+/* Special characters for operands.  */
+static char operand_special_chars[] = "[]@.-+";
+
+/* md_assemble() will always leave the instruction passed to it unaltered.
+   To do this we store the instruction in a special stack.  */
+static char save_stack[32];
+static char *save_stack_p;
+
+#define END_STRING_AND_SAVE(s)	\
+  do				\
+    {				\
+      *save_stack_p++ = *(s);	\
+      *s = '\0';		\
+    }				\
+  while (0)
+
+#define RESTORE_END_STRING(s)	\
+  do				\
+    {				\
+      *(s) = *(--save_stack_p);	\
+    }				\
+  while (0)
+
+/* The instruction we are assembling.  */
+static maxq20_insn i;
+
+/* The current template.  */
+static MAXQ20_OPCODES *current_templates;
+
+/* The displacement operand if any.  */
+static expressionS disp_expressions;
+
+/* Current Operand we are working on (0:1st operand,1:2nd operand).  */
+static int this_operand;
+
+/* The prefix instruction if used.  */
+static char PFX_INSN[2];
+static char INSERT_BUFFER[2];
+
+/* For interface with expression() ????? */
+extern char *input_line_pointer;
+
+/* The HASH Tables:  */
+
+/* Operand Hash Table.  */
+static struct hash_control *op_hash;
+
+/* Register Hash Table.  */
+static struct hash_control *reg_hash;
+
+/* Memory reference Hash Table.  */
+static struct hash_control *mem_hash;
+
+/* Bit hash table.  */
+static struct hash_control *bit_hash;
+
+/* Memory Access syntax table.  */
+static struct hash_control *mem_syntax_hash;
+
+/* This is a mapping from pseudo-op names to functions.  */
+
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"int", cons, 2},		/* size of 'int' has been changed to 1 word
+				   (i.e) 16 bits.  */
+  {"maxq10", maxq_target, bfd_mach_maxq10},
+  {"maxq20", maxq_target, bfd_mach_maxq20},
+  {NULL, 0, 0},
+};
+
+#define SET_PFX_ARG(x) (PFX_INSN[1] = x)
+
+
+/* This function sets the PFX value coresponding to the specs. Source
+   Destination Index Selection ---------------------------------- Write To|
+   SourceRegRange | Dest Addr Range
+   ------------------------------------------------------ PFX[0] | 0h-Fh |
+   0h-7h PFX[1] | 10h-1Fh | 0h-7h PFX[2] | 0h-Fh | 8h-Fh PFX[3] | 10h-1Fh |
+   8h-Fh PFX[4] | 0h-Fh | 10h-17h PFX[5] | 10h-1Fh | 10h-17h PFX[6] | 0h-Fh | 
+   18h-1Fh PFX[7] | 0h-Fh | 18h-1Fh */
+
+static void
+set_prefix (void)
+{
+  short int src_index = 0, dst_index = 0;
+
+  if (i.operands == 0)
+    return;
+  if (i.operands == 1)		/* Only SRC is Present */
+    {
+      if (i.types[0] == REG)
+	{
+	  if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+	    {
+	      dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	      src_index = 0x00;
+	    }
+	  else
+	    {
+	      src_index = i.maxq20_op[0].reg[0].Mod_index;
+	      dst_index = 0x00;
+	    }
+	}
+    }
+
+  if (i.operands == 2)
+    {
+      if (i.types[0] == REG && i.types[1] == REG)
+	{
+	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+	}
+      else if (i.types[0] != REG && i.types[1] == REG)	/* DST is Absent */
+	{
+	  src_index = i.maxq20_op[1].reg[0].Mod_index;
+	  dst_index = 0x00;
+	}
+      else if (i.types[0] == REG && i.types[1] != REG)	/* Id SRC is Absent */
+	{
+	  dst_index = i.maxq20_op[0].reg[0].Mod_index;
+	  src_index = 0x00;
+	}
+      else if (i.types[0] == BIT && i.maxq20_op[0].r_bit)
+	{
+	  dst_index = i.maxq20_op[0].r_bit->reg->Mod_index;
+	  src_index = 0x00;
+	}
+
+      else if (i.types[1] == BIT && i.maxq20_op[1].r_bit)
+	{
+	  dst_index = 0x00;
+	  src_index = i.maxq20_op[1].r_bit->reg->Mod_index;
+	}
+    }
+
+  if (src_index >= 0x00 && src_index <= 0xF)
+    {
+      if (dst_index >= 0x00 && dst_index <= 0x07)
+	/* Set PFX[0] */
+	i.prefix = 0;
+
+      else if (dst_index >= 0x08 && dst_index <= 0x0F)
+	/* Set PFX[2] */
+	i.prefix = 2;
+
+      else if (dst_index >= 0x10 && dst_index <= 0x17)
+	/* Set PFX[4] */
+	i.prefix = 4;
+
+      else if (dst_index >= 0x18 && dst_index <= 0x1F)
+	/* Set PFX[6] */
+	i.prefix = 6;
+    }
+  else if (src_index >= 0x10 && src_index <= 0x1F)
+    {
+      if (dst_index >= 0x00 && dst_index <= 0x07)
+	/* Set PFX[1] */
+	i.prefix = 1;
+
+      else if (dst_index >= 0x08 && dst_index <= 0x0F)
+	/* Set PFX[3] */
+	i.prefix = 3;
+
+      else if (dst_index >= 0x10 && dst_index <= 0x17)
+	/* Set PFX[5] */
+	i.prefix = 5;
+
+      else if (dst_index >= 0x18 && dst_index <= 0x1F)
+	/* Set PFX[7] */
+	i.prefix = 7;
+    }
+}
+
+static unsigned char
+is_a_LSinstr (const char *ln_pointer)
+{
+  int i = 0;
+
+  for (i = 0; LSInstr[i] != NULL; i++)
+    if (!strcmp (LSInstr[i], ln_pointer))
+      return 1;
+
+  return 0;
+}
+
+static void
+LS_processing (const char *line)
+{
+  if (is_a_LSinstr (line))
+    {
+      if ((line[0] == 'L') || (line[0] == 'l'))
+	{
+	  i.prefix = 0;
+	  INSERT_BUFFER[0] = PFX0;
+	  i.Instr_Prefix = LONG_PREFIX;
+	}
+      else if ((line[0] == 'S') || (line[0] == 's'))
+	i.Instr_Prefix = SHORT_PREFIX;
+      else
+	i.Instr_Prefix = NO_PREFIX;
+    }
+  else
+    i.Instr_Prefix = LONG_PREFIX;
+}
+
+/* Separate mnemonics and the operands.  */
+
+static char *
+parse_insn (char *line, char *mnemonic)
+{
+  char *l = line;
+  char *token_start = l;
+  char *mnem_p;
+  char temp[MAX_MNEM_SIZE];
+  int ii = 0;
+
+  memset (temp, END_OF_INSN, MAX_MNEM_SIZE);
+  mnem_p = mnemonic;
+
+  while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
+    {
+      ii++;
+      mnem_p++;
+      if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
+	{
+	  as_bad (_("no such instruction: `%s'"), token_start);
+	  return NULL;
+	}
+      l++;
+    }
+
+  if (!is_space_char (*l) && *l != END_OF_INSN)
+    {
+      as_bad (_("invalid character %s in mnemonic"), l);
+      return NULL;
+    }
+
+  while (ii)
+    {
+      temp[ii - 1] = toupper ((char) mnemonic[ii - 1]);
+      ii--;
+    }
+
+  LS_processing (temp);
+
+  if (i.Instr_Prefix != 0 && is_a_LSinstr (temp))
+    /* Skip the optional L-S.  */
+    memcpy (temp, temp + 1, MAX_MNEM_SIZE);
+
+  /* Look up instruction (or prefix) via hash table.  */
+  current_templates = (MAXQ20_OPCODES *) hash_find (op_hash, temp);
+
+  if (current_templates != NULL)
+    return l;
+
+  as_bad (_("no such instruction: `%s'"), token_start);
+  return NULL;
+}
+
+/* Function to calculate x to the power of y.
+   Just to avoid including the math libraries.  */
+
+static int
+pwr (int x, int y)
+{
+  int k, ans = 1;
+
+  for (k = 0; k < y; k++)
+    ans *= x;
+
+  return ans;
+}
+
+static reg_entry *
+parse_reg_by_index (char *imm_start)
+{
+  int k = 0, mid = 0, rid = 0, val = 0, j = 0;
+  char temp[4] = { 0 };
+  reg_entry *reg = NULL;
+
+  do
+    {
+      if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k])
+	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (imm_start[k] - 'a');
+
+      else if (imm_start[k] == 'h')
+	break;
+
+      else if (imm_start[k] == END_OF_INSN)
+	{
+	  imm_start[k] = 'd';
+	  break;
+	}
+
+      else
+	return NULL;		/* not a hex digit */
+
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = 0; j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    case 'd':
+      for (j = 0; j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    return NULL;	/* not a number */
+
+	  val += temp[j] * pwr (10, k - j - 1);
+	  break;
+	}
+    }
+
+  /* Get the module and register id's.  */
+  mid = val & 0x0f;
+  rid = (val >> 4) & 0x0f;
+
+  if (mid < 6)
+    {
+      /* Search the pheripheral reg table.  */
+      for (j = 0; j < num_of_reg; j++)
+	{
+	  if (new_reg_table[j].opcode == val)
+	    {
+	      reg = (reg_entry *) & new_reg_table[j];
+	      break;
+	    }
+	}
+    }
+
+  else
+    {
+      /* Search the system register table.  */
+      j = 0;
+
+      while (system_reg_table[j].reg_name != NULL)
+	{
+	  if (system_reg_table[j].opcode == val)
+	    {
+	      reg = (reg_entry *) & system_reg_table[j];
+	      break;
+	    }
+	  j++;
+	}
+    }
+
+  if (reg == NULL)
+    {
+      as_bad (_("Invalid register value %s"), imm_start);
+      return reg;
+    }
+
+#if CHANGE_PFX
+  if (this_operand == 0 && reg != NULL)
+    {
+      if (reg->Mod_index > 7)
+	i.prefix = 2;
+      else
+	i.prefix = 0;
+    }
+#endif
+  return (reg_entry *) reg;
+}
+
+/* REG_STRING starts *before* REGISTER_PREFIX.  */
+
+static reg_entry *
+parse_register (char *reg_string, char **end_op)
+{
+  char *s = reg_string;
+  char *p = NULL;
+  char reg_name_given[MAX_REG_NAME_SIZE + 1];
+  reg_entry *r = NULL;
+
+  r = NULL;
+  p = NULL;
+
+  /* Skip possible REGISTER_PREFIX and possible whitespace.  */
+  if (is_space_char (*s))
+    ++s;
+
+  p = reg_name_given;
+  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+    {
+      if (p >= reg_name_given + MAX_REG_NAME_SIZE)
+	return (reg_entry *) NULL;
+      s++;
+    }
+
+  *end_op = s;
+
+  r = (reg_entry *) hash_find (reg_hash, reg_name_given);
+
+#if CHANGE_PFX
+  if (this_operand == 0 && r != NULL)
+    {
+      if (r->Mod_index > 7)
+	i.prefix = 2;
+      else
+	i.prefix = 0;
+    }
+#endif
+  return r;
+}
+
+static reg_bit *
+parse_register_bit (char *reg_string, char **end_op)
+{
+  const char *s = reg_string;
+  short k = 0;
+  char diff = 0;
+  reg_bit *rb = NULL;
+  reg_entry *r = NULL;
+  bit_name *b = NULL;
+  char temp_bitname[MAX_REG_NAME_SIZE + 2];
+  char temp[MAX_REG_NAME_SIZE + 1];
+
+  memset (&temp, '\0', (MAX_REG_NAME_SIZE + 1));
+  memset (&temp_bitname, '\0', (MAX_REG_NAME_SIZE + 2));
+
+  diff = 0;
+  r = NULL;
+  rb = NULL;
+  rb = xmalloc (sizeof (reg_bit));
+  rb->reg = xmalloc (sizeof (reg_entry));
+  k = 0;
+
+  /* For supporting bit names.  */
+  b = (bit_name *) hash_find (bit_hash, reg_string);
+
+  if (b != NULL)
+    {
+      *end_op = reg_string + strlen (reg_string);
+      strcpy (temp_bitname, b->reg_bit);
+      s = temp_bitname;
+    }
+
+  if (strchr (s, '.'))
+    {
+      while (*s != '.')
+	{
+	  if (*s == '\0')
+	    return NULL;
+	  temp[k] = *s++;
+
+	  k++;
+	}
+      temp[k] = '\0';
+    }
+
+  if ((r = parse_register (temp, end_op)) == NULL)
+    return NULL;
+
+  rb->reg = r;
+
+  /* Skip the "."  */
+  s++;
+
+  if (isdigit ((char) *s))
+    rb->bit = atoi (s);
+  else if (isalpha ((char) *s))
+    {
+      rb->bit = (char) *s - 'a';
+      rb->bit += 10;
+      if (rb->bit > 15)
+	{
+	  as_bad (_("Invalid bit number : '%c'"), (char) *s);
+	  return NULL;
+	}
+    }
+
+  if (b != NULL)
+    diff = strlen (temp_bitname) - strlen (temp) - 1;
+  else
+    diff = strlen (reg_string) - strlen (temp) - 1;
+
+  if (*(s + diff) != '\0')
+    {
+      as_bad (_("Illegal character after operand '%s'"), reg_string);
+      return NULL;
+    }
+
+  return rb;
+}
+
+static void
+pfx_for_imm_val (int arg)
+{
+  if (i.prefix == -1)
+    return;
+
+  if (i.prefix == 0 && arg == 0 && PFX_INSN[1] == 0 && !(i.data_operands))
+    return;
+
+  if (!(i.prefix < 0) && !(i.prefix > 7))
+    PFX_INSN[0] = (i.prefix << 4) | PFX0;
+
+  if (!PFX_INSN[1])
+    PFX_INSN[1] = arg;
+
+}
+
+static int
+maxq20_immediate (char *imm_start)
+{
+  int val = 0, val_pfx = 0;
+  char sign_val = 0;
+  int k = 0, j;
+  int temp[4] = { 0 };
+
+  imm_start++;
+
+  if (imm_start[1] == '\0' && (imm_start[0] == '0' || imm_start[0] == '1')
+      && (this_operand == 1 && ((i.types[0] == BIT || i.types[0] == FLAG))))
+    {
+      val = imm_start[0] - '0';
+      i.imm_bit_operands++;
+      i.types[this_operand] = IMMBIT;
+      i.maxq20_op[this_operand].imms = (char) val;
+#if CHANGE_PFX
+      if (i.prefix == 2)
+	pfx_for_imm_val (0);
+#endif
+      return 1;
+    }
+
+  /* Check For Sign Charcater.  */
+  sign_val = 0;
+
+  do
+    {
+      if (imm_start[k] == '-' && k == 0)
+	sign_val = -1;
+
+      else if (imm_start[k] == '+' && k == 0)
+	sign_val = 1;
+
+      else if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k])
+	       && (imm_start[k] = tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (imm_start[k] - 'a');
+
+      else if (imm_start[k] == 'h')
+	break;
+
+      else if (imm_start[k] == '\0')
+	{
+	  imm_start[k] = 'd';
+	  break;
+	}
+      else
+	{
+	  as_bad (_("Invalid Character in immediate Value : %c"),
+		  imm_start[k]);
+	  return 0;
+	}
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    case 'd':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    {
+	      as_bad (_("Invalid Character in immediate value : %c"),
+		      imm_start[j]);
+	      return 0;
+	    }
+	  val += temp[j] * pwr (10, k - j - 1);
+	}
+    }
+
+  if (!sign_val)
+    sign_val = 1;
+
+  /* Now over here the value val stores the 8 bit/16 bit value. We will put a 
+     check if we are moving a 16 bit immediate value into an 8 bit register. 
+     In that case we will generate a warning and move only the lower 8 bits */
+  if (val > 65535)
+    {
+      as_bad (_("Immediate value greater than 16 bits"));
+      return 0;
+    }
+
+  val = val * sign_val;
+
+  /* If it is a stack pointer and the value is greater than the maximum
+     permissible size */
+  if (this_operand == 1)
+    {
+      if ((val * sign_val) > MAX_STACK && i.types[0] == REG
+	  && !strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+	{
+	  as_warn (_
+		   ("Attempt to move a value in the stack pointer greater than the size of the stack"));
+	  val = val & MAX_STACK;
+	}
+
+      /* Check the range for 8 bit registers.  */
+      else if (((val * sign_val) > 0xFF) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	{
+	  as_warn (_
+		   ("Attempt to move 16 bit value into an 8 bit register.Truncating..\n"));
+	  val = val & 0xfe;
+	}
+
+      else if (((sign_val == -1) || (val > 0xFF)) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      else if ((val <= 0xff) && (i.types[0] == REG)
+	       && (i.maxq20_op[0].reg->rtype == Reg_8W))
+	i.maxq20_op[this_operand].imms = (char) val;
+
+
+      /* Check for 16 bit registers.  */
+      else if (((sign_val == -1) || val > 0xFE) && i.types[0] == REG
+	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+	{
+	  /* Add PFX for any negative value -> 16bit register.  */
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      else if (val < 0xFF && i.types[0] == REG
+	       && i.maxq20_op[0].reg->rtype == Reg_16W)
+	{
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      /* All the immediate memory access - no PFX.  */
+      else if (i.types[0] == MEM)
+	{
+	  if ((sign_val == -1) || val > 0xFE)
+	    {
+	      val_pfx = val >> 8;
+	      val = ((val) & 0x00ff);
+	      SET_PFX_ARG (val_pfx);
+	      i.maxq20_op[this_operand].imms = (char) val;
+	    }
+	  else
+	    i.maxq20_op[this_operand].imms = (char) val;
+	}
+
+      /* Special handling for immediate jumps like jump nz, #03h etc.  */
+      else if (val < 0xFF && i.types[0] == FLAG)
+	i.maxq20_op[this_operand].imms = (char) val;
+
+      else if ((((sign_val == -1) || val > 0xFE)) && i.types[0] == FLAG)
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+      else
+	{
+	  as_bad (_("Invalid immediate move operation"));
+	  return 0;
+	}
+    }
+  else
+    {
+      /* All the instruction with operation on ACC: like ADD src, etc.  */
+      if ((sign_val == -1) || val > 0xFE)
+	{
+	  val_pfx = val >> 8;
+	  val = ((val) & 0x00ff);
+	  SET_PFX_ARG (val_pfx);
+	  i.maxq20_op[this_operand].imms = (char) val;
+	}
+      else
+	i.maxq20_op[this_operand].imms = (char) val;
+    }
+
+  i.imm_operands++;
+  return 1;
+}
+
+static int
+extract_int_val (const char *imm_start)
+{
+  int k, j, val;
+  char sign_val;
+  int temp[4];
+
+  k = 0;
+  j = 0;
+  val = 0;
+  sign_val = 0;
+  do
+    {
+      if (imm_start[k] == '-' && k == 0)
+	sign_val = -1;
+
+      else if (imm_start[k] == '+' && k == 0)
+	sign_val = 1;
+
+      else if (isdigit (imm_start[k]))
+	temp[k] = imm_start[k] - '0';
+
+      else if (isalpha (imm_start[k]) && (tolower (imm_start[k])) < 'g')
+	temp[k] = 10 + (int) (tolower (imm_start[k]) - 'a');
+
+      else if (tolower (imm_start[k]) == 'h')
+	break;
+
+      else if ((imm_start[k] == '\0') || (imm_start[k] == ']'))
+	/* imm_start[k]='d'; */
+	break;
+
+      else
+	{
+	  as_bad (_("Invalid Character in immediate Value : %c"),
+		  imm_start[k]);
+	  return 0;
+	}
+      k++;
+    }
+  while (imm_start[k] != '\n');
+
+  switch (imm_start[k])
+    {
+    case 'h':
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	val += temp[j] * pwr (16, k - j - 1);
+      break;
+
+    default:
+      for (j = (sign_val ? 1 : 0); j < k; j++)
+	{
+	  if (temp[j] > 9)
+	    {
+	      as_bad (_("Invalid Character in immediate value : %c"),
+		      imm_start[j]);
+	      return 0;
+	    }
+	  val += temp[j] * pwr (10, k - j - 1);
+	}
+    }
+
+  if (!sign_val)
+    sign_val = 1;
+
+  return val * sign_val;
+}
+
+static char
+check_for_parse (const char *line)
+{
+  int val;
+
+  if (*(line + 1) == '[')
+    {
+      do
+	{
+	  line++;
+	  if ((*line == '-') || (*line == '+'))
+	    break;
+	}
+      while (!is_space_char (*line));
+
+      if ((*line == '-') || (*line == '+'))
+	val = extract_int_val (line);
+      else
+	val = extract_int_val (line + 1);
+
+      INSERT_BUFFER[0] = 0x3E;
+      INSERT_BUFFER[1] = val;
+
+      return 1;
+    }
+
+  return 0;
+}
+
+static mem_access *
+maxq20_mem_access (char *mem_string, char **end_op)
+{
+  char *s = mem_string;
+  char *p;
+  char mem_name_given[MAX_MEM_NAME_SIZE + 1];
+  mem_access *m;
+
+  m = NULL;
+
+  /* Skip possible whitespace.  */
+  if (is_space_char (*s))
+    ++s;
+
+  p = mem_name_given;
+  while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
+    {
+      if (p >= mem_name_given + MAX_MEM_NAME_SIZE)
+	return (mem_access *) NULL;
+      s++;
+    }
+
+  *end_op = s;
+
+  m = (mem_access *) hash_find (mem_hash, mem_name_given);
+
+  return m;
+}
+
+/* This function checks whether the operand is a variable in the data segment 
+   and if so, it returns its symbol entry from the symbol table.  */
+
+static symbolS *
+maxq20_data (char *op_string)
+{
+  symbolS *symbolP;
+  symbolP = symbol_find (op_string);
+
+  if (symbolP != NULL
+      && S_GET_SEGMENT (symbolP) != now_seg
+      && S_GET_SEGMENT (symbolP) != bfd_und_section_ptr)
+    {
+      /* In case we do not want to always include the prefix instruction and
+         let the loader handle the job or in case of a 8 bit addressing mode, 
+         we will just check for val_pfx to be equal to zero and then load the 
+         prefix instruction. Otherwise no prefix instruction needs to be
+         loaded.  */
+      /* The prefix register will have to be loaded automatically as we have 
+	 a 16 bit addressing field.  */
+      pfx_for_imm_val (0);
+      return symbolP;
+    }
+
+  return NULL;
+}
+
+static int
+maxq20_displacement (char *disp_start, char *disp_end)
+{
+  expressionS *exp;
+  segT exp_seg = 0;
+  char *save_input_line_pointer;
+#ifndef LEX_AT
+  char *gotfree_input_line;
+#endif
+
+  gotfree_input_line = NULL;
+  exp = &disp_expressions;
+  i.maxq20_op[this_operand].disps = exp;
+  i.disp_operands++;
+  save_input_line_pointer = input_line_pointer;
+  input_line_pointer = disp_start;
+
+  END_STRING_AND_SAVE (disp_end);
+
+#ifndef LEX_AT
+  /* gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); if
+     (gotfree_input_line) input_line_pointer = gotfree_input_line; */
+#endif
+  exp_seg = expression (exp);
+
+  SKIP_WHITESPACE ();
+  if (*input_line_pointer)
+    as_bad (_("junk `%s' after expression"), input_line_pointer);
+#if GCC_ASM_O_HACK
+  RESTORE_END_STRING (disp_end + 1);
+#endif
+  RESTORE_END_STRING (disp_end);
+  input_line_pointer = save_input_line_pointer;
+#ifndef LEX_AT
+  if (gotfree_input_line)
+    free (gotfree_input_line);
+#endif
+  if (exp->X_op == O_absent || exp->X_op == O_big)
+    {
+      /* Missing or bad expr becomes absolute 0.  */
+      as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
+	      disp_start);
+      exp->X_op = O_constant;
+      exp->X_add_number = 0;
+      exp->X_add_symbol = (symbolS *) 0;
+      exp->X_op_symbol = (symbolS *) 0;
+    }
+#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
+
+  if (exp->X_op != O_constant
+      && OUTPUT_FLAVOR == bfd_target_aout_flavour
+      && exp_seg != absolute_section
+      && exp_seg != text_section
+      && exp_seg != data_section
+      && exp_seg != bss_section && exp_seg != undefined_section
+      && !bfd_is_com_section (exp_seg))
+    {
+      as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
+      return 0;
+    }
+#endif
+  i.maxq20_op[this_operand].disps = exp;
+  return 1;
+}
+
+/* Parse OPERAND_STRING into the maxq20_insn structure I.
+   Returns non-zero on error.  */
+
+static int
+maxq20_operand (char *operand_string)
+{
+  reg_entry *r = NULL;
+  reg_bit *rb = NULL;
+  mem_access *m = NULL;
+  char *end_op = NULL;
+  symbolS *sym = NULL;
+  char *base_string = NULL;
+  int ii = 0;
+  /* Start and end of displacement string expression (if found).  */
+  char *displacement_string_start = NULL;
+  char *displacement_string_end = NULL;
+  /* This maintains the  case sentivness.  */
+  char case_str_op_string[MAX_OPERAND_SIZE + 1];
+  char str_op_string[MAX_OPERAND_SIZE + 1];
+  char *org_case_op_string = case_str_op_string;
+  char *op_string = str_op_string;
+
+  
+  memset (op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+  memset (org_case_op_string, END_OF_INSN, (MAX_OPERAND_SIZE + 1));
+
+  memcpy (op_string, operand_string, strlen (operand_string) + 1);
+  memcpy (org_case_op_string, operand_string, strlen (operand_string) + 1);
+
+  ii = strlen (operand_string) + 1;
+
+  if (ii > MAX_OPERAND_SIZE)
+    {
+      as_bad (_("Size of Operand '%s' greater than %d"), op_string,
+	      MAX_OPERAND_SIZE);
+      return 0;
+    }
+
+  while (ii)
+    {
+      op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+      ii--;
+    }
+
+  if (is_space_char (*op_string))
+    ++op_string;
+
+  if (isxdigit (operand_string[0]))
+    {
+      /* Now the operands can start with an Integer.  */
+      r = parse_reg_by_index (op_string);
+      if (r != NULL)
+	{
+	  if (is_space_char (*op_string))
+	    ++op_string;
+	  i.types[this_operand] = REG;	/* Set the type.  */
+	  i.maxq20_op[this_operand].reg = r;	/* Set the Register value.  */
+	  i.reg_operands++;
+	  return 1;
+	}
+
+      /* Get the origanal string.  */
+      memcpy (op_string, operand_string, strlen (operand_string) + 1);
+      ii = strlen (operand_string) + 1;
+
+      while (ii)
+	{
+	  op_string[ii - 1] = toupper ((char) op_string[ii - 1]);
+	  ii--;
+	}
+    }
+
+  /* Check for flags.  */
+  if (!strcmp (op_string, "Z"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_Z;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NZ"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_NZ;	/* Set the Register value.  */
+      i.flag_operands++;
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NC"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_NC;	/* Set the Register value.  */
+      i.flag_operands++;
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "E"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;		/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_E;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "S"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_S;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "C"))
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+      i.maxq20_op[this_operand].flag = FLAG_C;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  else if (!strcmp (op_string, "NE"))
+    {
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = FLAG;	/* Set the type.  */
+
+      i.maxq20_op[this_operand].flag = FLAG_NE;	/* Set the Register value.  */
+
+      i.flag_operands++;
+
+      return 1;
+    }
+
+  /* CHECK FOR REGISTER BIT */
+  else if ((rb = parse_register_bit (op_string, &end_op)) != NULL)
+    {
+      op_string = end_op;
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = BIT;
+
+      i.maxq20_op[this_operand].r_bit = rb;
+
+      i.bit_operands++;
+
+      return 1;
+    }
+
+  else if (*op_string == IMMEDIATE_PREFIX)	/* FOR IMMEDITE.  */
+    {
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = IMM;
+
+      if (!maxq20_immediate (op_string))
+	{
+	  as_bad (_("illegal immediate operand '%s'"), op_string);
+	  return 0;
+	}
+      return 1;
+    }
+
+  else if (*op_string == ABSOLUTE_PREFIX || !strcmp (op_string, "NUL"))
+    {
+     if (is_space_char (*op_string))
+	++op_string;
+
+      /* For new requiremnt of copiler of for, @(BP,cons).  */
+      if (check_for_parse (op_string))
+	{
+	  memset (op_string, '\0', strlen (op_string) + 1);
+	  memcpy (op_string, "@BP[OFFS]\0", 11);
+	}
+
+      i.types[this_operand] = MEM;
+
+      if ((m = maxq20_mem_access (op_string, &end_op)) == NULL)
+	{
+	  as_bad (_("Invalid operand for memory access '%s'"), op_string);
+	  return 0;
+	}
+      i.maxq20_op[this_operand].mem = m;
+
+      i.mem_operands++;
+
+      return 1;
+    }
+
+  else if ((r = parse_register (op_string, &end_op)) != NULL)	/* Check for register.  */
+    {
+      op_string = end_op;
+
+      if (is_space_char (*op_string))
+	++op_string;
+
+      i.types[this_operand] = REG;	/* Set the type.  */
+      i.maxq20_op[this_operand].reg = r;	/* Set the Register value.  */
+      i.reg_operands++;
+      return 1;
+    }
+
+  if (this_operand == 1)
+    {
+      /* Changed for orginal case of data refrence on 30 Nov 2003.  */
+      /* The operand can either be a data reference or a symbol reference.  */
+      if ((sym = maxq20_data (org_case_op_string)) != NULL)	/* Check for data memory.  */
+	{
+	  while (is_space_char (*op_string))
+	    ++op_string;
+
+	  /* Set the type of the operand.  */
+	  i.types[this_operand] = DATA;
+
+	  /* Set the value of the data.  */
+	  i.maxq20_op[this_operand].data = sym;
+	  i.data_operands++;
+
+	  return 1;
+	}
+
+      else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+	{
+	  /* This is a memory reference of some sort. char *base_string;
+	     Start and end of displacement string expression (if found). char 
+	     *displacement_string_start; char *displacement_string_end.  */
+	  base_string = org_case_op_string + strlen (org_case_op_string);
+
+	  --base_string;
+	  if (is_space_char (*base_string))
+	    --base_string;
+
+	  /* If we only have a displacement, set-up for it to be parsed
+	     later.  */
+	  displacement_string_start = org_case_op_string;
+	  displacement_string_end = base_string + 1;
+	  if (displacement_string_start != displacement_string_end)
+	    {
+	      if (!maxq20_displacement (displacement_string_start,
+					displacement_string_end))
+		{
+		  as_bad (_("illegal displacement operand "));
+		  return 0;
+		}
+	      /* A displacement operand found.  */
+	      i.types[this_operand] = DISP;	/* Set the type.  */
+	      return 1;
+	    }
+	}
+    }
+  
+  /* Check for displacement.  */
+  else if (is_digit_char (*op_string) || is_identifier_char (*op_string))
+    {
+      /* This is a memory reference of some sort. char *base_string;
+         Start and end of displacement string expression (if found). char
+         *displacement_string_start; char *displacement_string_end;  */
+      base_string = org_case_op_string + strlen (org_case_op_string);
+
+      --base_string;
+      if (is_space_char (*base_string))
+	--base_string;
+
+      /* If we only have a displacement, set-up for it to be parsed later.  */
+      displacement_string_start = org_case_op_string;
+      displacement_string_end = base_string + 1;
+      if (displacement_string_start != displacement_string_end)
+	{
+	  if (!maxq20_displacement (displacement_string_start,
+				    displacement_string_end))
+	    return 0;
+	  /* A displacement operand found.  */
+	  i.types[this_operand] = DISP;	/* Set the type.  */
+	}
+    }
+  return 1;
+}
+
+/* Parse_operand takes as input instruction and operands and Parse operands
+   and makes entry in the template.  */
+
+static char *
+parse_operands (char *l, const char *mnemonic)
+{
+  char *token_start;
+
+  /* 1 if operand is pending after ','.  */
+  short int expecting_operand = 0;
+
+  /* Non-zero if operand parens not balanced.  */
+  short int paren_not_balanced;
+
+  int operand_ok;
+
+  /* For Overcoming Warning of unused variable.  */
+  if (mnemonic)
+    operand_ok = 0;
+
+  while (*l != END_OF_INSN)
+    {
+      /* Skip optional white space before operand.  */
+      if (is_space_char (*l))
+	++l;
+
+      if (!is_operand_char (*l) && *l != END_OF_INSN)
+	{
+	  as_bad (_("invalid character %c before operand %d"),
+		  (char) (*l), i.operands + 1);
+	  return NULL;
+	}
+      token_start = l;
+
+      paren_not_balanced = 0;
+      while (paren_not_balanced || *l != ',')
+	{
+	  if (*l == END_OF_INSN)
+	    {
+	      if (paren_not_balanced)
+		{
+		  as_bad (_("unbalanced brackets in operand %d."),
+			  i.operands + 1);
+		  return NULL;
+		}
+
+	      break;
+	    }
+	  else if (!is_operand_char (*l) && !is_space_char (*l))
+	    {
+	      as_bad (_("invalid character %c in operand %d"),
+		      (char) (*l), i.operands + 1);
+	      return NULL;
+	    }
+	  if (*l == '[')
+	    ++paren_not_balanced;
+	  if (*l == ']')
+	    --paren_not_balanced;
+	  l++;
+	}
+
+      if (l != token_start)
+	{
+	  /* Yes, we've read in another operand.  */
+	  this_operand = i.operands++;
+	  if (i.operands > MAX_OPERANDS)
+	    {
+	      as_bad (_("spurious operands; (%d operands/instruction max)"),
+		      MAX_OPERANDS);
+	      return NULL;
+	    }
+
+	  /* Now parse operand adding info to 'i' as we go along.  */
+	  END_STRING_AND_SAVE (l);
+
+	  operand_ok = maxq20_operand (token_start);
+
+	  RESTORE_END_STRING (l);
+
+	  if (!operand_ok)
+	    return NULL;
+	}
+      else
+	{
+	  if (expecting_operand)
+	    {
+	    expecting_operand_after_comma:
+	      as_bad (_("expecting operand after ','; got nothing"));
+	      return NULL;
+	    }
+	}
+
+      if (*l == ',')
+	{
+	  if (*(++l) == END_OF_INSN)
+	    /* Just skip it, if it's \n complain.  */
+	    goto expecting_operand_after_comma;
+
+	  expecting_operand = 1;
+	}
+    }
+
+  return l;
+}
+
+static int
+match_operands (int type, MAX_ARG_TYPE flag_type, MAX_ARG_TYPE arg_type,
+		int op_num)
+{
+  switch (type)
+    {
+    case REG:
+      if ((arg_type & A_REG) == A_REG)
+	return 1;
+      break;
+    case IMM:
+      if ((arg_type & A_IMM) == A_IMM)
+	return 1;
+      break;
+    case IMMBIT:
+      if ((arg_type & A_BIT_0) == A_BIT_0 && (i.maxq20_op[op_num].imms == 0))
+	return 1;
+      else if ((arg_type & A_BIT_1) == A_BIT_1
+	       && (i.maxq20_op[op_num].imms == 1))
+	return 1;
+      break;
+    case MEM:
+      if ((arg_type & A_MEM) == A_MEM)
+	return 1;
+      break;
+
+    case FLAG:
+      if ((arg_type & flag_type) == flag_type)
+	return 1;
+
+      break;
+
+    case BIT:
+      if ((arg_type & ACC_BIT) == ACC_BIT && !strcmp (i.maxq20_op[op_num].r_bit->reg->reg_name, "ACC"))
+	return 1;
+      else if ((arg_type & SRC_BIT) == SRC_BIT && (op_num == 1))
+	return 1;
+      else if ((op_num == 0) && (arg_type & DST_BIT) == DST_BIT)
+	return 1;
+      break;
+    case DISP:
+      if ((arg_type & A_DISP) == A_DISP)
+	return 1;
+    case DATA:
+      if ((arg_type & A_DATA) == A_DATA)
+	return 1;
+    case BIT_BUCKET:
+      if ((arg_type & A_BIT_BUCKET) == A_BIT_BUCKET)
+	return 1;
+    }
+  return 0;
+}
+
+static int
+match_template (void)
+{
+  /* Points to template once we've found it.  */
+  const MAXQ20_OPCODE_INFO *t;
+  char inv_oper;
+  inv_oper = 0;
+
+  for (t = current_templates->start; t < current_templates->end; t++)
+    {
+      /* Must have right number of operands.  */
+      if (i.operands != t->op_number)
+	continue;
+      else if (!t->op_number)
+	break;
+
+      switch (i.operands)
+	{
+	case 2:
+	  if (!match_operands (i.types[1], i.maxq20_op[1].flag, t->arg[1], 1))
+	    {
+	      inv_oper = 1;
+	      continue;
+	    }
+	case 1:
+	  if (!match_operands (i.types[0], i.maxq20_op[0].flag, t->arg[0], 0))
+	    {
+	      inv_oper = 2;
+	      continue;
+	    }
+	}
+      break;
+    }
+
+  if (t == current_templates->end)
+    {
+      /* We found no match.  */
+      as_bad (_("operand %d is invalid for `%s'"),
+	      inv_oper, current_templates->start->name);
+      return 0;
+    }
+
+  /* Copy the template we have found.  */
+  i.op = *t;
+  return 1;
+}
+
+/* This function filters out the various combinations of operands which are
+   not allowed for a particular instruction.  */
+
+static int
+match_filters (void)
+{
+  /* Now we have at our disposal the instruction i. We will be using the
+     following fields i.op.name : This is the mnemonic name. i.types[2] :
+     These are the types of the operands (REG/IMM/DISP/MEM/BIT/FLAG/IMMBIT)
+     i.maxq20_op[2] : This contains the specific info of the operands.  */
+
+  /* Our first filter : NO ALU OPERATIONS CAN HAVE THE ACTIVE ACCUMULATOR AS
+     SOURCE.  */
+  if (!strcmp (i.op.name, "AND") || !strcmp (i.op.name, "OR")
+      || !strcmp (i.op.name, "XOR") || !strcmp (i.op.name, "ADD")
+      || !strcmp (i.op.name, "ADDC") || !strcmp (i.op.name, "SUB")
+      || !strcmp (i.op.name, "SUBB"))
+    {
+      if (i.types[0] == REG)
+	{
+	  if (i.maxq20_op[0].reg->Mod_name == 0xa)
+	    {
+	      as_bad (_
+		      ("The Accumulator cannot be used as a source in ALU instructions\n"));
+	      return 0;
+	    }
+	}
+    }
+
+  if (!strcmp (i.op.name, "MOVE") && (i.types[0] == MEM || i.types[1] == MEM)
+      && i.operands == 2)
+    {
+      mem_access_syntax *mem_op = NULL;
+
+      if (i.types[0] == MEM)
+	{
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[0].mem->name);
+	  if ((mem_op->type == SRC) && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as destination in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	  else if ((mem_op->invalid_op != NULL) && (i.types[1] == MEM)
+		   && mem_op)
+	    {
+	      int k = 0;
+
+	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+		{
+		  if (mem_op->invalid_op[k] != NULL)
+		    if (!strcmp
+			(mem_op->invalid_op[k], i.maxq20_op[1].mem->name))
+		      {
+			as_bad (_
+				("Invalid Instruction '%s' operand cant be used with %s"),
+				mem_op->name, i.maxq20_op[1].mem->name);
+			return 0;
+		      }
+		}
+	    }
+	}
+
+      if (i.types[1] == MEM)
+	{
+	  mem_op = NULL;
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[1].mem->name);
+	  if (mem_op->type == DST && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as source in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	  else if (mem_op->invalid_op != NULL && i.types[0] == MEM && mem_op)
+	    {
+	      int k = 0;
+
+	      for (k = 0; k < 5 || !mem_op->invalid_op[k]; k++)
+		{
+		  if (mem_op->invalid_op[k] != NULL)
+		    if (!strcmp
+			(mem_op->invalid_op[k], i.maxq20_op[0].mem->name))
+		      {
+			as_bad (_
+				("Invalid Instruction '%s' operand cant be used with %s"),
+				mem_op->name, i.maxq20_op[0].mem->name);
+			return 0;
+		      }
+		}
+	    }
+	  else if (i.types[0] == REG
+		   && !strcmp (i.maxq20_op[0].reg->reg_name, "OFFS")
+		   && mem_op)
+	    {
+	      if (!strcmp (mem_op->name, "@BP[OFFS--]")
+		  || !strcmp (mem_op->name, "@BP[OFFS++]"))
+		{
+		  as_bad (_
+			  ("Invalid Instruction '%s' operand cant be used with %s"),
+			  mem_op->name, i.maxq20_op[0].mem->name);
+		  return 0;
+		}
+	    }
+	}
+    }
+
+  /* Added for SRC and DST in one operand instructioni i.e OR @--DP[1] added
+     on 10-March-2004.  */
+  if ((i.types[0] == MEM) && (i.operands == 1)
+      && !(!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI")))
+    {
+      mem_access_syntax *mem_op = NULL;
+
+      if (i.types[0] == MEM)
+	{
+	  mem_op =
+	    (mem_access_syntax *) hash_find (mem_syntax_hash,
+					     i.maxq20_op[0].mem->name);
+	  if (mem_op->type == DST && mem_op)
+	    {
+	      as_bad (_("'%s' operand cant be used as source in %s"),
+		      mem_op->name, i.op.name);
+	      return 0;
+	    }
+	}
+    }
+
+  if (i.operands == 2 && i.types[0] == IMM)
+    {
+      as_bad (_("'%s' instruction cant have first operand as Immediate vale"),
+	      i.op.name);
+      return 0;
+    }
+
+  /* Our second filter : SP or @SP-- cannot be used with PUSH or POP */
+  if (!strcmp (i.op.name, "PUSH") || !strcmp (i.op.name, "POP")
+      || !strcmp (i.op.name, "POPI"))
+    {
+      if (i.types[0] == REG)
+	{
+	  if (!strcmp (i.maxq20_op[0].reg->reg_name, "SP"))
+	    {
+	      as_bad (_("SP cannot be used with %s\n"), i.op.name);
+	      return 0;
+	    }
+	}
+      else if (i.types[0] == MEM
+	       && !strcmp (i.maxq20_op[0].mem->name, "@SP--"))
+	{
+	  as_bad (_("@SP-- cannot be used with PUSH\n"));
+	  return 0;
+	}
+    }
+
+  /* This filter checks that two memory references using DP's cannot be used
+     together in an instruction */
+  if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 2)
+    {
+      if (strlen (i.maxq20_op[0].mem->name) != 6 ||
+	  strcmp (i.maxq20_op[0].mem->name, i.maxq20_op[1].mem->name))
+	{
+	  if (!strncmp (i.maxq20_op[0].mem->name, "@DP", 3)
+	      && !strncmp (i.maxq20_op[1].mem->name, "@DP", 3))
+	    {
+	      as_bad (_
+		      ("Operands either contradictory or use the data bus in read/write state together"));
+	      return 0;
+	    }
+
+	  if (!strncmp (i.maxq20_op[0].mem->name, "@SP", 3)
+	      && !strncmp (i.maxq20_op[1].mem->name, "@SP", 3))
+	    {
+	      as_bad (_
+		      ("Operands either contradictory or use the data bus in read/write state together"));
+	      return 0;
+	    }
+	}
+      if ((i.maxq20_op[1].mem != NULL)
+	  && !strncmp (i.maxq20_op[1].mem->name, "NUL", 3))
+	{
+	  as_bad (_("MOVE Cant Use NUL as SRC"));
+	  return 0;
+	}
+    }
+
+  /* This filter checks that contradictory movement between DP register and
+     Memory access using DP followed by increment or decrement.  */
+
+  if (!strcmp (i.op.name, "MOVE") && i.mem_operands == 1
+      && i.reg_operands == 1)
+    {
+      int memnum, regnum;
+
+      memnum = (i.types[0] == MEM) ? 0 : 1;
+      regnum = (memnum == 0) ? 1 : 0;
+      if (!strncmp (i.maxq20_op[regnum].reg->reg_name, "DP", 2) &&
+	  !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+		    i.maxq20_op[regnum].reg->reg_name, 5)
+	  && strcmp ((i.maxq20_op[memnum].mem->name) + 1,
+		     i.maxq20_op[regnum].reg->reg_name))
+	{
+	  as_bad (_
+		  ("Contradictory movement between DP register and memory access using DP"));
+	  return 0;
+	}
+      else if (!strcmp (i.maxq20_op[regnum].reg->reg_name, "SP") &&
+	       !strncmp ((i.maxq20_op[memnum].mem->name) + 1,
+			 i.maxq20_op[regnum].reg->reg_name, 2))
+	{
+	  as_bad (_
+		  ("SP and @SP-- cannot be used together in a move instruction"));
+	  return 0;
+	}
+    }
+
+  /* This filter restricts the instructions containing source and destination 
+     bits to only CTRL module of the serial registers. Peripheral registers
+     yet to be defined.  */
+
+  if (i.bit_operands == 1 && i.operands == 2)
+    {
+      int bitnum = (i.types[0] == BIT) ? 0 : 1;
+
+      if (strcmp (i.maxq20_op[bitnum].r_bit->reg->reg_name, "ACC"))
+	{
+	  if (i.maxq20_op[bitnum].r_bit->reg->Mod_name >= 0x7 &&
+	      i.maxq20_op[bitnum].r_bit->reg->Mod_name != CTRL)
+	    {
+	      as_bad (_
+		      ("Only Module 8 system registers allowed in this operation"));
+	      return 0;
+	    }
+	}
+    }
+
+  /* This filter is for checking the register bits.  */
+  if (i.bit_operands == 1 || i.operands == 2)
+    {
+      int bitnum = 0, size = 0;
+
+      bitnum = (i.types[0] == BIT) ? 0 : 1;
+      if (i.bit_operands == 1)
+	{
+	  switch (i.maxq20_op[bitnum].r_bit->reg->rtype)
+	    {
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    case Reg_8R:
+	      size = 7;
+	      if (bitnum == 0)
+		{
+		  as_fatal (_("Read only Register used as destination"));
+		  return 0;
+		}
+	      break;
+
+	    case Reg_16R:
+	      size = 15;
+	      if (bitnum == 0)
+		{
+		  as_fatal (_("Read only Register used as destination"));
+		  return 0;
+		}
+	      break;
+	    }
+
+	  if (size < (i.maxq20_op[bitnum].r_bit)->bit)
+	    {
+	      as_bad (_("Bit No '%d'exceeds register size in this operation"),
+		      (i.maxq20_op[bitnum].r_bit)->bit);
+	      return 0;
+	    }
+	}
+
+      if (i.bit_operands == 2)
+	{
+	  switch ((i.maxq20_op[0].r_bit)->reg->rtype)
+	    {
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    case Reg_8R:
+	    case Reg_16R:
+	      as_fatal (_("Read only Register used as destination"));
+	      return 0;
+	    }
+
+	  if (size < (i.maxq20_op[0].r_bit)->bit)
+	    {
+	      as_bad (_
+		      ("Bit No '%d' exceeds register size in this operation"),
+		      (i.maxq20_op[0].r_bit)->bit);
+	      return 0;
+	    }
+
+	  size = 0;
+	  switch ((i.maxq20_op[1].r_bit)->reg->rtype)
+	    {
+	    case Reg_8R:
+	    case Reg_8W:
+	      size = 7;		/* 8 bit register, both read and write.  */
+	      break;
+	    case Reg_16R:
+	    case Reg_16W:
+	      size = 15;
+	      break;
+	    }
+
+	  if (size < (i.maxq20_op[1].r_bit)->bit)
+	    {
+	      as_bad (_
+		      ("Bit No '%d' exceeds register size in this operation"),
+		      (i.maxq20_op[1].r_bit)->bit);
+	      return 0;
+	    }
+	}
+    }
+
+  /* No branch operations should occur into the data memory. Hence any memory 
+     references have to be filtered out when used with instructions like
+     jump, djnz[] and call.  */
+
+  if (!strcmp (i.op.name, "JUMP") || !strcmp (i.op.name, "CALL")
+      || !strncmp (i.op.name, "DJNZ", 4))
+    {
+      if (i.mem_operands)
+	as_warn (_
+		 ("Memory References cannot be used with branching operations\n"));
+    }
+
+  if (!strcmp (i.op.name, "DJNZ"))
+    {
+      if (!
+	  (strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+	   || strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))
+	{
+	  as_bad (_("DJNZ uses only LC[n] register \n"));
+	  return 0;
+	}
+    }
+
+  /* No destination register used should be read only!  */
+  if ((i.operands == 2 && i.types[0] == REG) || !strcmp (i.op.name, "POP")
+      || !strcmp (i.op.name, "POPI"))
+    {				/* The destination is a register */
+      int regnum = 0;
+
+      if (!strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+	{
+	  regnum = 0;
+
+	  if (i.types[regnum] == MEM)
+	    {
+	      mem_access_syntax *mem_op = NULL;
+
+	      mem_op =
+		(mem_access_syntax *) hash_find (mem_syntax_hash,
+						 i.maxq20_op[regnum].mem->
+						 name);
+	      if (mem_op->type == SRC && mem_op)
+		{
+		  as_bad (_
+			  ("'%s' operand cant be used as destination  in %s"),
+			  mem_op->name, i.op.name);
+		  return 0;
+		}
+	    }
+	}
+
+      if (i.maxq20_op[regnum].reg->rtype == Reg_8R
+	  || i.maxq20_op[regnum].reg->rtype == Reg_16R)
+	{
+	  as_bad (_("Read only register used for writing purposes '%s'"),
+		  i.maxq20_op[regnum].reg->reg_name);
+	  return 0;
+	}
+    }
+
+  /* While moving the address of a data in the data section, the destination
+     should be either data pointers only.  */
+  if ((i.data_operands) && (i.operands == 2))
+    {
+      if ((i.types[0] != REG) && (i.types[0] != MEM))
+	{
+	  as_bad (_("Invalid destination for this kind of source."));
+	  return 0;
+	}
+
+	if (i.types[0] == REG && i.maxq20_op[0].reg->rtype == Reg_8W)
+	  {
+	    as_bad (_
+		    ("Invalid register as destination for this kind of source.Only data pointers can be used."));
+	    return 0;
+	  }
+    }
+  return 1;
+}
+
+static int
+decode_insn (void)
+{
+  /* Check for the format Bit if defined.  */
+  if (i.op.format == 0 || i.op.format == 1)
+    i.instr[0] = i.op.format << 7;
+  else
+    {
+      /* Format bit not defined. We will have to be find it out ourselves.  */
+      if (i.imm_operands == 1 || i.data_operands == 1 || i.disp_operands == 1)
+	i.op.format = 0;
+      else
+	i.op.format = 1;
+      i.instr[0] = i.op.format << 7;
+    }
+
+  /* Now for the destination register.  */
+
+  /* If destination register is already defined . The conditions are the
+     following: (1) The second entry in the destination array should be 0 (2) 
+     If there are two operands then the first entry should not be a register,
+     memory or a register bit (3) If there are less than two operands and the
+     it is not a pop operation (4) The second argument is the carry
+     flag(applicable to move Acc.<b>,C.  */
+  if (i.op.dst[1] == 0
+      &&
+      ((i.types[0] != REG && i.types[0] != MEM && i.types[0] != BIT
+	&& i.operands == 2) || (i.operands < 2 && strcmp (i.op.name, "POP")
+				&& strcmp (i.op.name, "POPI"))
+       || (i.op.arg[1] == FLAG_C)))
+    {
+      i.op.dst[0] &= 0x7f;
+      i.instr[0] |= i.op.dst[0];
+    }
+  else if (i.op.dst[1] == 0 && !strcmp (i.op.name, "DJNZ")
+	   &&
+	   (((i.types[0] == REG)
+	     && (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]")
+		 || !strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]")))))
+    {
+      i.op.dst[0] &= 0x7f;
+      if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[0]"))
+	i.instr[0] |= 0x4D;
+
+      if (!strcmp (i.maxq20_op[0].reg->reg_name, "LC[1]"))
+	i.instr[0] |= 0x5D;
+    }
+  else
+    {
+      unsigned char temp;
+
+      /* Target register will have to be specified.  */
+      if (i.types[0] == REG
+	  && (i.op.dst[0] == REG || i.op.dst[0] == (REG | MEM)))
+	{
+	  temp = (i.maxq20_op[0].reg)->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[0] == MEM && (i.op.dst[0] == (REG | MEM)))
+	{
+	  temp = (i.maxq20_op[0].mem)->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[0] == BIT && (i.op.dst[0] == REG))
+	{
+	  temp = (i.maxq20_op[0].r_bit)->reg->opcode;
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else if (i.types[1] == BIT && (i.op.dst[0] == BIT))
+	{
+	  temp = (i.maxq20_op[1].r_bit)->bit;
+	  temp = temp << 4;
+	  temp |= i.op.dst[1];
+	  temp &= 0x7f;
+	  i.instr[0] |= temp;
+	}
+      else
+	{
+	  as_bad (_("Invalid Instruction"));
+	  return 0;
+	}
+    }
+
+  /* Now for the source register.  */
+
+  /* If Source register is already known. The following conditions are
+     checked: (1) There are no operands (2) If there is only one operand and
+     it is a flag (3) If the operation is MOVE C,#0/#1 (4) If it is a POP
+     operation.  */
+
+  if (i.operands == 0 || (i.operands == 1 && i.types[0] == FLAG)
+      || (i.types[0] == FLAG && i.types[1] == IMMBIT)
+      || !strcmp (i.op.name, "POP") || !strcmp (i.op.name, "POPI"))
+    i.instr[1] = i.op.src[0];
+
+  else if (i.imm_operands == 1 && ((i.op.src[0] & IMM) == IMM))
+    i.instr[1] = i.maxq20_op[this_operand].imms;
+  
+  else if (i.types[this_operand] == REG && ((i.op.src[0] & REG) == REG))
+    i.instr[1] = (char) ((i.maxq20_op[this_operand].reg)->opcode);
+
+  else if (i.types[this_operand] == BIT && ((i.op.src[0] & REG) == REG))
+    i.instr[1] = (char) (i.maxq20_op[this_operand].r_bit->reg->opcode);
+
+  else if (i.types[this_operand] == MEM && ((i.op.src[0] & MEM) == MEM))
+    i.instr[1] = (char) ((i.maxq20_op[this_operand].mem)->opcode);
+
+  else if (i.types[this_operand] == DATA && ((i.op.src[0] & DATA) == DATA))
+    /* This will copy only the lower order bytes into the instruction. The
+       higher order bytes have already been copied into the prefix register.  */
+    i.instr[1] = 0;
+
+  /* Decoding the source in the case when the second array entry is not 0.
+     This means that the source register has been divided into two nibbles.  */
+
+  else if (i.op.src[1] != 0)
+    {
+      /* If the first operand is a accumulator bit then
+	 the first 4 bits will be filled with the bit number.  */
+      if (i.types[0] == BIT && ((i.op.src[0] & BIT) == BIT))
+	{
+	  unsigned char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  i.instr[1] = temp;
+	}
+      /* In case of MOVE dst.<b>,#1 The first nibble in the source register
+         has to start with a zero. This is called a ZEROBIT */
+      else if (i.types[0] == BIT && ((i.op.src[0] & ZEROBIT) == ZEROBIT))
+	{
+	  char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  temp &= 0x7f;
+	  i.instr[1] = temp;
+	}
+      /* Similarly for a ONEBIT */
+      else if (i.types[0] == BIT && ((i.op.src[0] & ONEBIT) == ONEBIT))
+	{
+	  char temp = (i.maxq20_op[0].r_bit)->bit;
+
+	  temp = temp << 4;
+	  temp |= i.op.src[1];
+	  temp |= 0x80;
+	  i.instr[1] = temp;
+	}
+      /* In case the second operand is a register bit (MOVE C,Acc.<b> or MOVE 
+         C,src.<b> */
+      else if (i.types[1] == BIT)
+	{
+	  if (i.op.src[1] == 0 && i.op.src[1] == REG)
+	    i.instr[1] = (i.maxq20_op[1].r_bit)->reg->opcode;
+
+	  else if (i.op.src[0] == BIT && i.op.src)
+	    {
+	      char temp = (i.maxq20_op[1].r_bit)->bit;
+
+	      temp = temp << 4;
+	      temp |= i.op.src[1];
+	      i.instr[1] = temp;
+	    }
+	}
+      else
+	{
+	  as_bad (_("Invalid Instruction"));
+	  return 0;
+	}
+    }
+  return 1;
+}
+
+/* This is a function for outputting displacement operands.  */
+
+static void
+output_disp (fragS *insn_start_frag, offsetT insn_start_off)
+{
+  char *p;
+  relax_substateT subtype;
+  symbolS *sym;
+  offsetT off;
+  int diff;
+
+  diff = 0;
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  switch (i.Instr_Prefix)
+    {
+    case LONG_PREFIX:
+      subtype = EXPLICT_LONG_PREFIX;
+      break;
+    case SHORT_PREFIX:
+      subtype = SHORT_PREFIX;
+      break;
+    default:
+      subtype = NO_PREFIX;
+      break;
+    }
+
+  /* Its a symbol. Here we end the frag and start the relaxation. Now in our
+     case there is no need for relaxation. But we do need support for a
+     prefix operator. Hence we will check whethere is room for 4 bytes ( 2
+     for prefix + 2 for the current instruction ) Hence if at a particular
+     time we find out whether the prefix operator is reqd , we shift the
+     current instruction two places ahead and insert the prefix instruction.  */
+  frag_grow (2 + 2);
+  p = frag_more (2);
+
+  sym = i.maxq20_op[this_operand].disps->X_add_symbol;
+  off = i.maxq20_op[this_operand].disps->X_add_number;
+
+  if (i.maxq20_op[this_operand].disps->X_add_symbol != NULL && sym && frag_now
+      && (subtype != EXPLICT_LONG_PREFIX))
+    {
+      /* If in the same frag.  */
+      if (frag_now == symbol_get_frag (sym))
+	{
+	  diff =
+	    ((((expressionS *) symbol_get_value_expression (sym))->
+	      X_add_number) - insn_start_off);
+
+	  /* PC points to the next instruction.  */
+	  diff = (diff / MAXQ_OCTETS_PER_BYTE) - 1;
+
+	  if (diff >= -128 && diff <= 127)
+	    {
+	      i.instr[1] = (char) diff;
+
+	      /* This will be overwritten later when the symbol is resolved.  */
+	      *p = i.instr[1];
+	      *(p + 1) = i.instr[0];
+
+	      /* No Need to create a FIXUP.  */
+	      return;
+	    }
+	}
+    }
+
+  /* This will be overwritten later when the symbol is resolved.  */
+  *p = i.instr[1];
+  *(p + 1) = i.instr[0];
+
+  if (i.maxq20_op[this_operand].disps->X_op != O_constant
+      && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+    {
+      /* Handle complex expressions.  */
+      sym = make_expr_symbol (i.maxq20_op[this_operand].disps);
+      off = 0;
+    }
+
+  /* Vineet : This has been added for md_estimate_size_before_relax to
+     estimate the correct size.  */
+  if (subtype != SHORT_PREFIX)
+    i.reloc[this_operand] = LONG_PREFIX;
+
+  frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,  p);
+}
+
+/* This is a function for outputting displacement operands.  */
+
+static void
+output_data (fragS *insn_start_frag, offsetT insn_start_off)
+{
+  char *p;
+  relax_substateT subtype;
+  symbolS *sym;
+  offsetT off;
+  int diff;
+
+  diff = 0;
+  off = 0;
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  subtype = EXPLICT_LONG_PREFIX;
+
+  frag_grow (2 + 2);
+  p = frag_more (2);
+
+  sym = i.maxq20_op[this_operand].data;
+  off = 0;
+
+  /* This will be overwritten later when the symbol is resolved.  */
+  *p = i.instr[1];
+  *(p + 1) = i.instr[0];
+
+  if (i.maxq20_op[this_operand].disps->X_op != O_constant
+      && i.maxq20_op[this_operand].disps->X_op != O_symbol)
+    /* Handle complex expressions.  */
+    /* Because data is already in terms of symbol so no
+       need to convert it from expression to symbol.  */
+    off = 0;
+
+  frag_var (rs_machine_dependent, 2, i.reloc[this_operand], subtype, sym, off,  p);
+}
+
+static void
+output_insn (void)
+{
+  fragS *insn_start_frag;
+  offsetT insn_start_off;
+  char *p;
+
+  /* Tie dwarf2 debug info to the address at the start of the insn. We can't
+     do this after the insn has been output as the current frag may have been 
+     closed off.  eg. by frag_var.  */
+  dwarf2_emit_insn (0);
+
+  /* To ALign the text section on word.  */
+
+  frag_align (1, 0, 1);
+
+  /* We initialise the frags for this particular instruction.  */
+  insn_start_frag = frag_now;
+  insn_start_off = frag_now_fix ();
+
+  /* If there are displacement operators(unresolved) present, then handle
+     them separately.  */
+  if (i.disp_operands)
+    {
+      output_disp (insn_start_frag, insn_start_off);
+      return;
+    }
+
+  if (i.data_operands)
+    {
+      output_data (insn_start_frag, insn_start_off);
+      return;
+    }
+
+  /* Check whether the INSERT_BUFFER has to be written.  */
+  if (strcmp (INSERT_BUFFER, ""))
+    {
+      p = frag_more (2);
+
+      *p++ = INSERT_BUFFER[1];
+      *p = INSERT_BUFFER[0];
+    }
+
+  /* Check whether the prefix instruction has to be written.  */
+  if (strcmp (PFX_INSN, ""))
+    {
+      p = frag_more (2);
+
+      *p++ = PFX_INSN[1];
+      *p = PFX_INSN[0];
+    }
+
+  p = frag_more (2);
+  /* For Little endian.  */
+  *p++ = i.instr[1];
+  *p = i.instr[0];
+}
+
+static void
+make_new_reg_table (void)
+{
+  unsigned long size_pm = sizeof (peripheral_reg_table);
+  num_of_reg = ARRAY_SIZE (peripheral_reg_table);
+
+  new_reg_table = xmalloc (size_pm);
+  if (new_reg_table == NULL)
+    as_bad (_("Cannot allocate memory"));
+
+  memcpy (new_reg_table, peripheral_reg_table, size_pm);
+}
+
+/* pmmain performs the initilizations for the pheripheral modules. */
+
+static void
+pmmain (void)
+{
+  make_new_reg_table ();
+  return;
+}
+
+void
+md_begin (void)
+{
+  const char *hash_err = NULL;
+  int c = 0;
+  char *p;
+  const MAXQ20_OPCODE_INFO *optab;
+  MAXQ20_OPCODES *core_optab;	/* For opcodes of the same name. This will
+				   be inserted into the hash table.  */
+  struct reg *reg_tab;
+  struct mem_access_syntax const *memsyntab;
+  struct mem_access *memtab;
+  struct bit_name *bittab;
+
+  /* Initilize pherioipheral modules.  */
+  pmmain ();
+
+  /* Initialise the opcode hash table.  */
+  op_hash = hash_new ();
+
+  optab = op_table;		/* Initialise it to the first entry of the
+				   maxq20 operand table.  */
+
+  /* Setup for loop.  */
+  core_optab = xmalloc (sizeof (MAXQ20_OPCODES));
+  core_optab->start = optab;
+
+  while (1)
+    {
+      ++optab;
+      if (optab->name == NULL || strcmp (optab->name, (optab - 1)->name) != 0)
+	{
+	  /* different name --> ship out current template list; add to hash
+	     table; & begin anew.  */
+
+	  core_optab->end = optab;
+#ifdef MAXQ10S
+	  if (max_version == bfd_mach_maxq10)
+	    {
+	      if (((optab - 1)->arch == MAXQ10) || ((optab - 1)->arch == MAX))
+		{
+		  hash_err = hash_insert (op_hash,
+					  (optab - 1)->name,
+					  (PTR) core_optab);
+		}
+	    }
+	  else if (max_version == bfd_mach_maxq20)
+	    {
+	      if (((optab - 1)->arch == MAXQ20) || ((optab - 1)->arch == MAX))
+		{
+#endif
+		  hash_err = hash_insert (op_hash,
+					  (optab - 1)->name,
+					  (PTR) core_optab);
+#if MAXQ10S
+		}
+	    }
+	  else
+	    as_fatal (_("Internal Error: Illegal Architecure specified"));
+#endif
+	  if (hash_err)
+	    as_fatal (_("Internal Error:  Can't hash %s: %s"),
+		      (optab - 1)->name, hash_err);
+
+	  if (optab->name == NULL)
+	    break;
+	  core_optab = xmalloc (sizeof (MAXQ20_OPCODES));
+	  core_optab->start = optab;
+	}
+    }
+
+  /* Initialise a new register table.  */
+  reg_hash = hash_new ();
+
+  for (reg_tab = system_reg_table;
+       reg_tab < (system_reg_table + ARRAY_SIZE (system_reg_table));
+       reg_tab++)
+    {
+#if MAXQ10S
+      switch (max_version)
+	{
+	case bfd_mach_maxq10:
+	  if ((reg_tab->arch == MAXQ10) || (reg_tab->arch == MAX))
+	    hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+	  break;
+
+	case bfd_mach_maxq20:
+	  if ((reg_tab->arch == MAXQ20) || (reg_tab->arch == MAX))
+	    {
+#endif
+	      hash_err =
+		hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+#if MAXQ10S
+	    }
+	  break;
+	default:
+	  as_fatal (_("Invalid architecture type"));
+	}
+#endif
+
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  reg_tab->reg_name, hash_err);
+    }
+
+  /* Pheripheral Registers Entry.  */
+  for (reg_tab = new_reg_table;
+       reg_tab < (new_reg_table + num_of_reg - 1); reg_tab++)
+    {
+      hash_err = hash_insert (reg_hash, reg_tab->reg_name, (PTR) reg_tab);
+
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  reg_tab->reg_name, hash_err);
+    }
+
+  /* Initialise a new memory operand table.  */
+  mem_hash = hash_new ();
+
+  for (memtab = mem_table;
+       memtab < mem_table + ARRAY_SIZE (mem_table);
+       memtab++)
+    {
+      hash_err = hash_insert (mem_hash, memtab->name, (PTR) memtab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  memtab->name, hash_err);
+    }
+
+  bit_hash = hash_new ();
+
+  for (bittab = bit_table;
+       bittab < bit_table + ARRAY_SIZE (bit_table);
+       bittab++)
+    {
+      hash_err = hash_insert (bit_hash, bittab->name, (PTR) bittab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  bittab->name, hash_err);
+    }
+
+  mem_syntax_hash = hash_new ();
+
+  for (memsyntab = mem_access_syntax_table;
+       memsyntab < mem_access_syntax_table + ARRAY_SIZE (mem_access_syntax_table);
+       memsyntab++)
+    {
+      hash_err =
+	hash_insert (mem_syntax_hash, memsyntab->name, (PTR) memsyntab);
+      if (hash_err)
+	as_fatal (_("Internal Error : Can't Hash %s : %s"),
+		  memsyntab->name, hash_err);
+    }
+
+  /* Initialise the lexical tables,mnemonic chars,operand chars.  */
+  for (c = 0; c < 256; c++)
+    {
+      if (ISDIGIT (c))
+	{
+	  digit_chars[c] = c;
+	  mnemonic_chars[c] = c;
+	  operand_chars[c] = c;
+	  register_chars[c] = c;
+	}
+      else if (ISLOWER (c))
+	{
+	  mnemonic_chars[c] = c;
+	  operand_chars[c] = c;
+	  register_chars[c] = c;
+	}
+      else if (ISUPPER (c))
+	{
+	  mnemonic_chars[c] = TOLOWER (c);
+	  register_chars[c] = c;
+	  operand_chars[c] = c;
+	}
+
+      if (ISALPHA (c) || ISDIGIT (c))
+	{
+	  identifier_chars[c] = c;
+	}
+      else if (c > 128)
+	{
+	  identifier_chars[c] = c;
+	  operand_chars[c] = c;
+	}
+    }
+
+  /* All the special characters.  */
+  register_chars['@'] = '@';
+  register_chars['+'] = '+';
+  register_chars['-'] = '-';
+  digit_chars['-'] = '-';
+  identifier_chars['_'] = '_';
+  identifier_chars['.'] = '.';
+  register_chars['['] = '[';
+  register_chars[']'] = ']';
+  operand_chars['_'] = '_';
+  operand_chars['#'] = '#';
+  mnemonic_chars['['] = '[';
+  mnemonic_chars[']'] = ']';
+
+  for (p = operand_special_chars; *p != '\0'; p++)
+    operand_chars[(unsigned char) *p] = (unsigned char) *p;
+
+  /* Set the maxq arch type.  */
+  maxq_target (max_version);
+}
+
+/* md_assemble - Parse Instr - Seprate menmonics and operands - lookup the
+   menmunonic in the operand table - Parse operands and populate the
+   structure/template - Match the operand with opcode and its validity -
+   Output Instr.  */
+
+void
+md_assemble (char *line)
+{
+  int j;
+
+  char mnemonic[MAX_MNEM_SIZE];
+  char temp4prev[256];
+  static char prev_insn[256];
+
+  /* Initialize globals.  */
+  memset (&i, '\0', sizeof (i));
+  for (j = 0; j < MAX_OPERANDS; j++)
+    i.reloc[j] = NO_RELOC;
+
+  i.prefix = -1;
+  PFX_INSN[0] = 0;
+  PFX_INSN[1] = 0;
+  INSERT_BUFFER[0] = 0;
+  INSERT_BUFFER[1] = 0;
+
+  memcpy (temp4prev, line, strlen (line) + 1);
+
+  save_stack_p = save_stack;
+
+  line = (char *) parse_insn (line, mnemonic);
+  if (line == NULL)
+    return;
+
+  line = (char *) parse_operands (line, mnemonic);
+  if (line == NULL)
+    return;
+
+  /* Next, we find a template that matches the given insn, making sure the
+     overlap of the given operands types is consistent with the template
+     operand types.  */
+  if (!match_template ())
+    return;
+
+  /* In the MAXQ20, there are certain register combinations, and other
+     restrictions which are not allowed. We will try to resolve these right
+     now.  */
+  if (!match_filters ())
+    return;
+
+  /* Check for the approprate PFX register.  */
+  set_prefix ();
+  pfx_for_imm_val (0);
+
+  if (!decode_insn ())		/* decode insn. */
+    need_pass_2 = 1;
+
+  /* Check for Exlipct PFX instruction.  */
+  if (PFX_INSN[0] && (strstr (prev_insn, "PFX") || strstr (prev_insn, "pfx")))
+    as_warn (_("Ineffective insntruction %s \n"), prev_insn);
+
+  memcpy (prev_insn, temp4prev, strlen (temp4prev) + 1);
+
+  /* We are ready to output the insn.  */
+  output_insn ();
+}
diff --git a/gas/config/tc-maxq.h b/gas/config/tc-maxq.h
new file mode 100644
index 000000000000..12b7a9497acc
--- /dev/null
+++ b/gas/config/tc-maxq.h
@@ -0,0 +1,148 @@
+/* tc-maxq.h -- Header file for the asssembler(MAXQ)
+
+   Copyright 2004, 2005  Free Software Foundation, Inc.
+
+   Contributed by HCL Technologies Pvt. Ltd.
+
+   Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com)
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify it under the
+   terms of the GNU General Public License as published by the Free Software
+   Foundation; either version 2, or (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful, but WITHOUT ANY
+   WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+   FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+   details.
+
+   You should have received a copy of the GNU General Public License along
+   with GAS; see the file COPYING.  If not, write to the Free Software
+   Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+#ifndef  _TC_MAXQ_H_
+#define  _TC_MAXQ_H_
+
+#ifndef NO_RELOC
+#define NO_RELOC 0
+#endif
+
+/* `md_short_jump_size' `md_long_jump_size' `md_create_short_jump'
+   `md_create_long_jump' If `WORKING_DOT_WORD' is defined, GAS will not do
+   broken word processing (*note Broken words::.).  Otherwise, you should set
+   `md_short_jump_size' to the size of a short jump (a jump that is just long
+   enough to jump around a long jmp) and `md_long_jump_size' to the size of a
+   long jump (a jump that can go anywhere in the function), You should define
+   `md_create_short_jump' to create a short jump around a long jump, and
+   define `md_create_long_jump' to create a long jump.  */
+#define WORKING_DOT_WORD
+typedef enum _RELOC_ENUM
+{
+  MAXQ_WORDDATA = 5,		/* Word+n.  */
+  MAXQ_LONGDATA = 2,		/* Long+n.  */
+  MAXQ_INTERSEGMENT = 4,	/* Text to any other segment.  */
+  MAXQ_SHORTJUMP = BFD_RELOC_16_PCREL_S2,	/* PC Relative.  */
+  MAXQ_LONGJUMP = 6,		/* Absolute Jump.  */
+  EXTERNAL_RELOC = 8,
+  INTERSEGMENT_RELOC
+}
+RELOC_ENUM;
+
+#ifndef MAX_STACK
+#define MAX_STACK 0xf
+#endif
+
+#ifndef TC_MAXQ20
+#define TC_MAXQ20 1
+#endif
+
+#ifndef MAX_OPERAND_SIZE
+#define MAX_OPERAND_SIZE 255
+#endif
+
+#ifndef MAXQ_INSTRUCTION_SIZE
+#define MAXQ_INSTRUCTION_SIZE 2	/* 16 - BITS */
+#endif
+
+#if MAXQ_INSTRUCTION_SIZE
+#define MAXQ_OCTETS_PER_BYTE 	MAXQ_INSTRUCTION_SIZE
+#else
+#define MAXQ_OCTETS_PER_BYTE 	OCTETS_PER_BYTE
+#endif
+
+/* if this macro is defined gas will use this instead of comment_chars.  */
+#define tc_comments_chars maxq20_comment_chars
+
+#define tc_coff_symbol_emit_hook(a)     ;	/* not used */
+
+#define md_section_align(SEGMENT, SIZE)     (SIZE)
+
+/* Locally defined symbol shoudnot be adjusted to section symbol.  */
+#define tc_fix_adjustable(FIX) 0
+
+/* This specifies that the target has been defined as little endian -
+   default.  */
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define MAX_MEM_NAME_SIZE 12
+#define MAX_REG_NAME_SIZE  7
+#define MAX_MNEM_SIZE      8
+
+#define END_OF_INSN '\0'
+
+/* This macro is the BFD archetectureto pass to 'bfd_set_arch_mach'.  */
+#define TARGET_ARCH		bfd_arch_maxq
+
+/* This macro is the BFD machine number to pass to 'bfd_set_arch_mach'.
+   If not defines GAS will use 0.  */
+#define TARGET_MACH     	maxq20_mach ()
+extern unsigned long maxq20_mach (void);
+
+#ifndef LEX_AT
+/* We define this macro to generate a fixup for a data allocation pseudo-op.  */
+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) maxq20_cons_fix_new (FRAG,OFF,LEN,EXP)
+extern void maxq20_cons_fix_new (fragS *, unsigned int, unsigned int, expressionS *);
+#endif
+
+/* Define md_number_to_chars as the appropriate standard big endian or This
+   should just call either `number_to_chars_bigendian' or
+   `number_to_chars_littleendian', whichever is appropriate.  On targets like 
+   the MIPS which support options to change the endianness, which function to 
+   call is a runtime decision.  On other targets, `md_number_to_chars' can be 
+   a simple macro.  */
+#define md_number_to_chars maxq_number_to_chars
+extern void maxq_number_to_chars (char *, valueT, int);
+
+/* If this macro is defined, it is a pointer to a NULL terminated list of
+   chracters which may appear in an operand. GAS already assumes that all
+   alphanumeric chracters, and '$', '.', and '_' may appear in an
+   operand("symbol_char"in app.c). This macro may be defined to treat
+   additional chracters as appearing in an operand. This affects the way in
+   which GAS removes whitespaces before passing the string to md_assemble.  */
+#define tc_symbol_chars_extra_symbol_chars
+
+/* Define away the call to md_operand in the expression parsing code. This is 
+   called whenever the expression parser can't parse the input and gives the
+   assembler backend a chance to deal with it instead.  */
+#define md_operand(x)
+
+#define MAX_OPERANDS           2	/* Max operands per instruction.  */
+#define MAX_IMMEDIATE_OPERANDS 1	/* Max immediate operands per instruction.  */
+#define MAX_MEMORY_OPERANDS    1	/* Max memory operands per instruction.  */
+
+/* Define the prefix we are using while trying to use an immediate value in
+   an instruction. e.g move A[0], #03h.  */
+#define IMMEDIATE_PREFIX '#'
+
+#define ABSOLUTE_PREFIX '@'
+
+/* This here defines the opcode of the nop operation on the MAXQ. We did
+   declare it here when we tried to fill the align bites with nop's but GAS
+   only expects nop's to be single byte instruction.  */
+#define NOP_OPCODE (char)0xDA3A
+
+#define SIZE_OF_PM sizeof(pmodule)	/* Size of the structure.  */
+
+#endif /* TC_MAXQ_H */
diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c
index c10b75d226c7..a795a5550362 100644
--- a/gas/config/tc-mcore.c
+++ b/gas/config/tc-mcore.c
@@ -1,5 +1,6 @@
 /* tc-mcore.c -- Assemble code for M*Core
-   Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -36,31 +37,6 @@
 #endif
 
 /* Forward declarations for dumb compilers.  */
-static void   mcore_s_literals PARAMS ((int));
-static void   mcore_pool_count PARAMS ((void (*) (int), int));
-static void   mcore_cons PARAMS ((int));
-static void   mcore_float_cons PARAMS ((int));
-static void   mcore_stringer PARAMS ((int));
-static void   mcore_fill   PARAMS ((int));
-static int    log2 PARAMS ((unsigned int));
-static char * parse_reg    PARAMS ((char *, unsigned *));
-static char * parse_creg   PARAMS ((char *, unsigned *));
-static char * parse_exp    PARAMS ((char *, expressionS *));
-static char * parse_rt     PARAMS ((char *, char **, int, expressionS *));
-static char * parse_imm    PARAMS ((char *, unsigned *, unsigned, unsigned));
-static char * parse_mem    PARAMS ((char *, unsigned *, unsigned *, unsigned));
-static char * parse_psrmod PARAMS ((char *, unsigned *));
-static void   make_name PARAMS ((char *, char *, int));
-static int    enter_literal PARAMS ((expressionS *, int));
-static void   dump_literals PARAMS ((int));
-static void   check_literals PARAMS ((int, int));
-static void   mcore_s_text    PARAMS ((int));
-static void   mcore_s_data    PARAMS ((int));
-static void   mcore_s_section PARAMS ((int));
-static void   mcore_s_bss     PARAMS ((int));
-#ifdef OBJ_ELF
-static void   mcore_s_comm    PARAMS ((int));
-#endif
 
 /* Several places in this file insert raw instructions into the
    object. They should use MCORE_INST_XXX macros to get the opcodes
@@ -73,8 +49,6 @@ const char comment_chars[] = "#/";
 const char line_separator_chars[] = ";";
 const char line_comment_chars[] = "#/";
 
-const int md_reloc_size = 8;
-
 static int do_jsri2bsr = 0;	/* Change here from 1 by Cruess 19 August 97.  */
 static int sifilter_mode = 0;
 
@@ -88,7 +62,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
 #define C(what,length) (((what) << 2) + (length))
 #define GET_WHAT(x)    ((x >> 2))
 
-/* These are the two types of relaxable instruction */
+/* These are the two types of relaxable instruction.  */
 #define COND_JUMP  1
 #define UNCD_JUMP  2
 
@@ -98,9 +72,9 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
 #define UNDEF_WORD_DISP 3
 
 #define C12_LEN	        2
-#define C32_LEN	       10	/* allow for align */
+#define C32_LEN	       10	/* Allow for align.  */
 #define U12_LEN	        2
-#define U32_LEN	        8	/* allow for align */
+#define U32_LEN	        8	/* Allow for align.  */
 
 typedef enum
 {
@@ -112,7 +86,8 @@ cpu_type;
 cpu_type cpu = M340;
 
 /* Initialize the relax table.  */
-const relax_typeS md_relax_table[] = {
+const relax_typeS md_relax_table[] =
+{
   {    0,     0, 0,	  0 },
   {    0,     0, 0,	  0 },
   {    0,     0, 0,	  0 },
@@ -162,68 +137,76 @@ static unsigned long poolspan;
 #define SPANPANIC	(1016)		/* 1024 - 1 entry - 2 byte rounding.  */
 #define SPANCLOSE	(900)
 #define SPANEXIT	(600)
-static symbolS * poolsym;		/* label for current pool.  */
+static symbolS * poolsym;		/* Label for current pool.  */
 static char poolname[8];
 static struct hash_control * opcode_hash_control;	/* Opcode mnemonics.  */
 
-/* This table describes all the machine specific pseudo-ops the assembler
-   has to support.  The fields are:
-     Pseudo-op name without dot
-     Function to call to execute this pseudo-op
-     Integer arg to pass to the function.   */
-const pseudo_typeS md_pseudo_table[] =
+#define POOL_END_LABEL   ".LE"
+#define POOL_START_LABEL ".LS"
+
+static void
+make_name (char * s, char * p, int n)
 {
-  { "export",   s_globl,          0 },
-  { "import",   s_ignore,         0 },
-  { "literals", mcore_s_literals, 0 },
-  { "page",     listing_eject,    0 },
+  static const char hex[] = "0123456789ABCDEF";
 
-  /* The following are to intercept the placement of data into the text
-     section (eg addresses for a switch table), so that the space they
-     occupy can be taken into account when deciding whether or not to
-     dump the current literal pool.
-     XXX - currently we do not cope with the .space and .dcb.d directives.  */
-  { "ascii",    mcore_stringer,       0 },
-  { "asciz",    mcore_stringer,       1 },
-  { "byte",     mcore_cons,           1 },
-  { "dc",       mcore_cons,           2 },
-  { "dc.b",     mcore_cons,           1 },
-  { "dc.d",     mcore_float_cons,    'd'},
-  { "dc.l",     mcore_cons,           4 },
-  { "dc.s",     mcore_float_cons,    'f'},
-  { "dc.w",     mcore_cons,           2 },
-  { "dc.x",     mcore_float_cons,    'x'},
-  { "double",   mcore_float_cons,    'd'},
-  { "float",    mcore_float_cons,    'f'},
-  { "hword",    mcore_cons,           2 },
-  { "int",      mcore_cons,           4 },
-  { "long",     mcore_cons,           4 },
-  { "octa",     mcore_cons,          16 },
-  { "quad",     mcore_cons,           8 },
-  { "short",    mcore_cons,           2 },
-  { "single",   mcore_float_cons,    'f'},
-  { "string",   mcore_stringer,       1 },
-  { "word",     mcore_cons,           2 },
-  { "fill",     mcore_fill,           0 },
+  s[0] = p[0];
+  s[1] = p[1];
+  s[2] = p[2];
+  s[3] = hex[(n >> 12) & 0xF];
+  s[4] = hex[(n >>  8) & 0xF];
+  s[5] = hex[(n >>  4) & 0xF];
+  s[6] = hex[(n)       & 0xF];
+  s[7] = 0;
+}
 
-  /* Allow for the effect of section changes.  */
-  { "text",      mcore_s_text,    0 },
-  { "data",      mcore_s_data,    0 },
-  { "bss",       mcore_s_bss,     1 },
-#ifdef OBJ_ELF
-  { "comm",      mcore_s_comm,    0 },
-#endif
-  { "section",   mcore_s_section, 0 },
-  { "section.s", mcore_s_section, 0 },
-  { "sect",      mcore_s_section, 0 },
-  { "sect.s",    mcore_s_section, 0 },
+static void
+dump_literals (int isforce)
+{
+  unsigned int i;
+  struct literal * p;
+  symbolS * brarsym = NULL;
 
-  { 0,          0,                0 }
-};
+  if (poolsize == 0)
+    return;
+
+  /* Must we branch around the literal table?  */
+  if (isforce)
+    {
+      char * output;
+      char brarname[8];
+
+      make_name (brarname, POOL_END_LABEL, poolnumber);
+
+      brarsym = symbol_make (brarname);
+
+      symbol_table_insert (brarsym);
+
+      output = frag_var (rs_machine_dependent,
+			 md_relax_table[C (UNCD_JUMP, DISP32)].rlx_length,
+			 md_relax_table[C (UNCD_JUMP, DISP12)].rlx_length,
+			 C (UNCD_JUMP, 0), brarsym, 0, 0);
+      output[0] = INST_BYTE0 (MCORE_INST_BR);	/* br .+xxx */
+      output[1] = INST_BYTE1 (MCORE_INST_BR);
+    }
+
+  /* Make sure that the section is sufficiently aligned and that
+     the literal table is aligned within it.  */
+  record_alignment (now_seg, 2);
+  frag_align (2, 0, 0);
+
+  colon (S_GET_NAME (poolsym));
+
+  for (i = 0, p = litpool; i < poolsize; i++, p++)
+    emit_expr (& p->e, 4);
+
+  if (brarsym != NULL)
+    colon (S_GET_NAME (brarsym));
+
+   poolsize = 0;
+}
 
 static void
-mcore_s_literals (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+mcore_s_literals (int ignore ATTRIBUTE_UNUSED)
 {
   dump_literals (0);
   demand_empty_rest_of_line ();
@@ -232,9 +215,7 @@ mcore_s_literals (ignore)
 /* Perform FUNC (ARG), and track number of bytes added to frag.  */
 
 static void
-mcore_pool_count (func, arg)
-     void (*func) PARAMS ((int));
-     int arg;
+mcore_pool_count (void (*func) (int), int arg)
 {
   const fragS *curr_frag = frag_now;
   offsetT added = -frag_now_fix_octets ();
@@ -252,8 +233,42 @@ mcore_pool_count (func, arg)
 }
 
 static void
-mcore_cons (nbytes)
-     int nbytes;
+check_literals (int kind, int offset)
+{
+  poolspan += offset;
+
+  /* SPANCLOSE and SPANEXIT are smaller numbers than SPANPANIC.
+     SPANPANIC means that we must dump now.
+     kind == 0 is any old instruction.
+     kind  > 0 means we just had a control transfer instruction.
+     kind == 1 means within a function
+     kind == 2 means we just left a function
+
+     The dump_literals (1) call inserts a branch around the table, so
+     we first look to see if its a situation where we won't have to
+     insert a branch (e.g., the previous instruction was an unconditional
+     branch).
+
+     SPANPANIC is the point where we must dump a single-entry pool.
+     it accounts for alignments and an inserted branch.
+     the 'poolsize*2' accounts for the scenario where we do:
+       lrw r1,lit1; lrw r2,lit2; lrw r3,lit3
+     Note that the 'lit2' reference is 2 bytes further along
+     but the literal it references will be 4 bytes further along,
+     so we must consider the poolsize into this equation.
+     This is slightly over-cautious, but guarantees that we won't
+     panic because a relocation is too distant.  */
+
+  if (poolspan > SPANCLOSE && kind > 0)
+    dump_literals (0);
+  else if (poolspan > SPANEXIT && kind > 1)
+    dump_literals (0);
+  else if (poolspan >= (SPANPANIC - poolsize * 2))
+    dump_literals (1);
+}
+
+static void
+mcore_cons (int nbytes)
 {
   if (now_seg == text_section)
     mcore_pool_count (cons, nbytes);
@@ -268,8 +283,7 @@ mcore_cons (nbytes)
 }
 
 static void
-mcore_float_cons (float_type)
-     int float_type;
+mcore_float_cons (int float_type)
 {
   if (now_seg == text_section)
     mcore_pool_count (float_cons, float_type);
@@ -284,8 +298,7 @@ mcore_float_cons (float_type)
 }
 
 static void
-mcore_stringer (append_zero)
-     int append_zero;
+mcore_stringer (int append_zero)
 {
   if (now_seg == text_section)
     mcore_pool_count (stringer, append_zero);
@@ -301,8 +314,7 @@ mcore_stringer (append_zero)
 }
 
 static void
-mcore_fill (unused)
-     int unused;
+mcore_fill (int unused)
 {
   if (now_seg == text_section)
     mcore_pool_count (s_fill, unused);
@@ -314,9 +326,9 @@ mcore_fill (unused)
 
 /* Handle the section changing pseudo-ops.  These call through to the
    normal implementations, but they dump the literal pool first.  */
+
 static void
-mcore_s_text (ignore)
-     int ignore;
+mcore_s_text (int ignore)
 {
   dump_literals (0);
 
@@ -328,8 +340,7 @@ mcore_s_text (ignore)
 }
 
 static void
-mcore_s_data (ignore)
-     int ignore;
+mcore_s_data (int ignore)
 {
   dump_literals (0);
 
@@ -341,8 +352,7 @@ mcore_s_data (ignore)
 }
 
 static void
-mcore_s_section (ignore)
-     int ignore;
+mcore_s_section (int ignore)
 {
   /* Scan forwards to find the name of the section.  If the section
      being switched to is ".line" then this is a DWARF1 debug section
@@ -370,8 +380,7 @@ mcore_s_section (ignore)
 }
 
 static void
-mcore_s_bss (needs_align)
-     int needs_align;
+mcore_s_bss (int needs_align)
 {
   dump_literals (0);
 
@@ -380,8 +389,7 @@ mcore_s_bss (needs_align)
 
 #ifdef OBJ_ELF
 static void
-mcore_s_comm (needs_align)
-     int needs_align;
+mcore_s_comm (int needs_align)
 {
   dump_literals (0);
 
@@ -389,17 +397,73 @@ mcore_s_comm (needs_align)
 }
 #endif
 
+/* This table describes all the machine specific pseudo-ops the assembler
+   has to support.  The fields are:
+     Pseudo-op name without dot
+     Function to call to execute this pseudo-op
+     Integer arg to pass to the function.   */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "export",   s_globl,          0 },
+  { "import",   s_ignore,         0 },
+  { "literals", mcore_s_literals, 0 },
+  { "page",     listing_eject,    0 },
+
+  /* The following are to intercept the placement of data into the text
+     section (eg addresses for a switch table), so that the space they
+     occupy can be taken into account when deciding whether or not to
+     dump the current literal pool.
+     XXX - currently we do not cope with the .space and .dcb.d directives.  */
+  { "ascii",    mcore_stringer,       0 },
+  { "asciz",    mcore_stringer,       1 },
+  { "byte",     mcore_cons,           1 },
+  { "dc",       mcore_cons,           2 },
+  { "dc.b",     mcore_cons,           1 },
+  { "dc.d",     mcore_float_cons,    'd'},
+  { "dc.l",     mcore_cons,           4 },
+  { "dc.s",     mcore_float_cons,    'f'},
+  { "dc.w",     mcore_cons,           2 },
+  { "dc.x",     mcore_float_cons,    'x'},
+  { "double",   mcore_float_cons,    'd'},
+  { "float",    mcore_float_cons,    'f'},
+  { "hword",    mcore_cons,           2 },
+  { "int",      mcore_cons,           4 },
+  { "long",     mcore_cons,           4 },
+  { "octa",     mcore_cons,          16 },
+  { "quad",     mcore_cons,           8 },
+  { "short",    mcore_cons,           2 },
+  { "single",   mcore_float_cons,    'f'},
+  { "string",   mcore_stringer,       1 },
+  { "word",     mcore_cons,           2 },
+  { "fill",     mcore_fill,           0 },
+
+  /* Allow for the effect of section changes.  */
+  { "text",      mcore_s_text,    0 },
+  { "data",      mcore_s_data,    0 },
+  { "bss",       mcore_s_bss,     1 },
+#ifdef OBJ_ELF
+  { "comm",      mcore_s_comm,    0 },
+#endif
+  { "section",   mcore_s_section, 0 },
+  { "section.s", mcore_s_section, 0 },
+  { "sect",      mcore_s_section, 0 },
+  { "sect.s",    mcore_s_section, 0 },
+
+  { 0,          0,                0 }
+};
+
 /* This function is called once, at assembler startup time.  This should
    set up all the tables, etc that the MD part of the assembler needs.  */
+
 void
-md_begin ()
+md_begin (void)
 {
   const mcore_opcode_info * opcode;
   char * prev_name = "";
 
   opcode_hash_control = hash_new ();
 
-  /* Insert unique names into hash table */
+  /* Insert unique names into hash table.  */
   for (opcode = mcore_table; opcode->name; opcode ++)
     {
       if (! streq (prev_name, opcode->name))
@@ -411,25 +475,25 @@ md_begin ()
 }
 
 /* Get a log2(val).  */
+
 static int
-log2 (val)
-    unsigned int val;
+mylog2 (unsigned int val)
 {
-    int log = -1;
-    while (val != 0)
+  int log = -1;
+
+  while (val != 0)
       {
 	log ++;
 	val >>= 1;
       }
 
-    return log;
+  return log;
 }
 
 /* Try to parse a reg name.  */
+
 static char *
-parse_reg (s, reg)
-     char * s;
-     unsigned * reg;
+parse_reg (char * s, unsigned * reg)
 {
   /* Strip leading whitespace.  */
   while (ISSPACE (* s))
@@ -485,9 +549,7 @@ cregs[] =
 };
 
 static char *
-parse_creg (s, reg)
-     char * s;
-     unsigned * reg;
+parse_creg (char * s, unsigned * reg)
 {
   int i;
 
@@ -547,9 +609,7 @@ parse_creg (s, reg)
 }
 
 static char *
-parse_psrmod (s, reg)
-  char *     s;
-  unsigned * reg;
+parse_psrmod (char * s, unsigned * reg)
 {
   int  i;
   char buf[10];
@@ -587,9 +647,7 @@ parse_psrmod (s, reg)
 }
 
 static char *
-parse_exp (s, e)
-     char * s;
-     expressionS * e;
+parse_exp (char * s, expressionS * e)
 {
   char * save;
   char * new;
@@ -612,129 +670,20 @@ parse_exp (s, e)
   return new;
 }
 
-static void
-make_name (s, p, n)
-     char * s;
-     char * p;
-     int n;
-{
-  static const char hex[] = "0123456789ABCDEF";
-
-  s[0] = p[0];
-  s[1] = p[1];
-  s[2] = p[2];
-  s[3] = hex[(n >> 12) & 0xF];
-  s[4] = hex[(n >>  8) & 0xF];
-  s[5] = hex[(n >>  4) & 0xF];
-  s[6] = hex[(n)       & 0xF];
-  s[7] = 0;
-}
-
-#define POOL_END_LABEL   ".LE"
-#define POOL_START_LABEL ".LS"
-
-static void
-dump_literals (isforce)
-     int isforce;
-{
-  unsigned int i;
-  struct literal * p;
-  symbolS * brarsym = NULL;
-
-  if (poolsize == 0)
-    return;
-
-  /* Must we branch around the literal table? */
-  if (isforce)
-    {
-      char * output;
-      char brarname[8];
-
-      make_name (brarname, POOL_END_LABEL, poolnumber);
-
-      brarsym = symbol_make (brarname);
-
-      symbol_table_insert (brarsym);
-
-      output = frag_var (rs_machine_dependent,
-			 md_relax_table[C (UNCD_JUMP, DISP32)].rlx_length,
-			 md_relax_table[C (UNCD_JUMP, DISP12)].rlx_length,
-			 C (UNCD_JUMP, 0), brarsym, 0, 0);
-      output[0] = INST_BYTE0 (MCORE_INST_BR);	/* br .+xxx */
-      output[1] = INST_BYTE1 (MCORE_INST_BR);
-    }
-
-  /* Make sure that the section is sufficiently aligned and that
-     the literal table is aligned within it.  */
-  record_alignment (now_seg, 2);
-  frag_align (2, 0, 0);
-
-  colon (S_GET_NAME (poolsym));
-
-  for (i = 0, p = litpool; i < poolsize; i++, p++)
-    emit_expr (& p->e, 4);
-
-  if (brarsym != NULL)
-    colon (S_GET_NAME (brarsym));
-
-   poolsize = 0;
-}
-
-static void
-check_literals (kind, offset)
-     int kind;
-     int offset;
-{
-  poolspan += offset;
-
-  /* SPANCLOSE and SPANEXIT are smaller numbers than SPANPANIC.
-     SPANPANIC means that we must dump now.
-     kind == 0 is any old instruction.
-     kind  > 0 means we just had a control transfer instruction.
-     kind == 1 means within a function
-     kind == 2 means we just left a function
-
-     The dump_literals (1) call inserts a branch around the table, so
-     we first look to see if its a situation where we won't have to
-     insert a branch (e.g., the previous instruction was an unconditional
-     branch).
-
-     SPANPANIC is the point where we must dump a single-entry pool.
-     it accounts for alignments and an inserted branch.
-     the 'poolsize*2' accounts for the scenario where we do:
-       lrw r1,lit1; lrw r2,lit2; lrw r3,lit3
-     Note that the 'lit2' reference is 2 bytes further along
-     but the literal it references will be 4 bytes further along,
-     so we must consider the poolsize into this equation.
-     This is slightly over-cautious, but guarantees that we won't
-     panic because a relocation is too distant.  */
-
-  if (poolspan > SPANCLOSE && kind > 0)
-    dump_literals (0);
-  else if (poolspan > SPANEXIT && kind > 1)
-    dump_literals (0);
-  else if (poolspan >= (SPANPANIC - poolsize * 2))
-    dump_literals (1);
-}
-
 static int
-enter_literal (e, ispcrel)
-     expressionS * e;
-     int ispcrel;
+enter_literal (expressionS * e, int ispcrel)
 {
   unsigned int i;
   struct literal * p;
 
   if (poolsize >= MAX_POOL_SIZE - 2)
-    {
-      /* The literal pool is as full as we can handle. We have
-	 to be 2 entries shy of the 1024/4=256 entries because we
-	 have to allow for the branch (2 bytes) and the alignment
-	 (2 bytes before the first insn referencing the pool and
-	 2 bytes before the pool itself) == 6 bytes, rounds up
-	 to 2 entries.  */
-      dump_literals (1);
-    }
+    /* The literal pool is as full as we can handle. We have
+       to be 2 entries shy of the 1024/4=256 entries because we
+       have to allow for the branch (2 bytes) and the alignment
+       (2 bytes before the first insn referencing the pool and
+       2 bytes before the pool itself) == 6 bytes, rounds up
+       to 2 entries.  */
+    dump_literals (1);
 
   if (poolsize == 0)
     {
@@ -773,12 +722,12 @@ enter_literal (e, ispcrel)
 /* Parse a literal specification. -- either new or old syntax.
    old syntax: the user supplies the label and places the literal.
    new syntax: we put it into the literal pool.  */
+
 static char *
-parse_rt (s, outputp, ispcrel, ep)
-     char * s;
-     char ** outputp;
-     int ispcrel;
-     expressionS * ep;
+parse_rt (char * s,
+	  char ** outputp,
+	  int ispcrel,
+	  expressionS * ep)
 {
   expressionS e;
   int n;
@@ -820,11 +769,10 @@ parse_rt (s, outputp, ispcrel, ep)
 }
 
 static char *
-parse_imm (s, val, min, max)
-     char * s;
-     unsigned * val;
-     unsigned min;
-     unsigned max;
+parse_imm (char * s,
+	   unsigned * val,
+	   unsigned min,
+	   unsigned max)
 {
   char * new;
   expressionS e;
@@ -845,11 +793,10 @@ parse_imm (s, val, min, max)
 }
 
 static char *
-parse_mem (s, reg, off, siz)
-     char * s;
-     unsigned * reg;
-     unsigned * off;
-     unsigned siz;
+parse_mem (char * s,
+	   unsigned * reg,
+	   unsigned * off,
+	   unsigned siz)
 {
   * off = 0;
 
@@ -903,8 +850,7 @@ parse_mem (s, reg, off, siz)
    the frags/bytes it assembles to.  */
 
 void
-md_assemble (str)
-     char * str;
+md_assemble (char * str)
 {
   char * op_start;
   char * op_end;
@@ -992,15 +938,15 @@ md_assemble (str)
 
       if (sifilter_mode)
 	{
-	  /* Replace with:  bsr .+2 ; addi r15,6; jmp rx ; jmp rx */
-	  inst = MCORE_INST_BSR;	/* with 0 displacement */
+	  /* Replace with:  bsr .+2 ; addi r15,6; jmp rx ; jmp rx.  */
+	  inst = MCORE_INST_BSR;	/* With 0 displacement.  */
 	  output[0] = INST_BYTE0 (inst);
 	  output[1] = INST_BYTE1 (inst);
 
 	  output = frag_more (2);
 	  inst = MCORE_INST_ADDI;
-	  inst |= 15;			/* addi r15,6 */
-	  inst |= (6 - 1) << 4;		/* over the jmp's */
+	  inst |= 15;			/* addi r15,6  */
+	  inst |= (6 - 1) << 4;		/* Over the jmp's.  */
 	  output[0] = INST_BYTE0 (inst);
 	  output[1] = INST_BYTE1 (inst);
 
@@ -1009,7 +955,8 @@ md_assemble (str)
 	  output[0] = INST_BYTE0 (inst);
 	  output[1] = INST_BYTE1 (inst);
 
-	  output = frag_more (2);		/* 2nd emitted in fallthru */
+	  /* 2nd emitted in fallthrough.  */
+	  output = frag_more (2);
 	}
       break;
 
@@ -1056,14 +1003,15 @@ md_assemble (str)
       output = frag_more (2);
       break;
 
-    case X1:	/* Handle both syntax-> xtrb- r1,rx OR xtrb- rx */
+    case X1:
+      /* Handle both syntax-> xtrb- r1,rx OR xtrb- rx.  */
       op_end = parse_reg (op_end + 1, & reg);
 
       /* Skip whitespace.  */
       while (ISSPACE (* op_end))
 	++ op_end;
 
-      if (* op_end == ',')	/* xtrb- r1,rx */
+      if (* op_end == ',')	/* xtrb- r1,rx.  */
 	{
 	  if (reg != 1)
 	    as_bad (_("destination register must be r1"));
@@ -1075,7 +1023,7 @@ md_assemble (str)
       output = frag_more (2);
       break;
 
-    case O1R1:  /* div- rx,r1 */
+    case O1R1:  /* div- rx,r1.  */
       op_end = parse_reg (op_end + 1, & reg);
       inst |= reg;
 
@@ -1133,7 +1081,8 @@ md_assemble (str)
       output = frag_more (2);
       break;
 
-    case OB2:		/* like OB, but arg is 2^n instead of n */
+    case OB2:
+      /* Like OB, but arg is 2^n instead of n.  */
       op_end = parse_reg (op_end + 1, & reg);
       inst |= reg;
 
@@ -1146,7 +1095,7 @@ md_assemble (str)
 	  op_end = parse_imm (op_end + 1, & reg, 1, 1 << 31);
 	  /* Further restrict the immediate to a power of two.  */
 	  if ((reg & (reg - 1)) == 0)
-	    reg = log2 (reg);
+	    reg = mylog2 (reg);
 	  else
 	    {
 	      reg = 0;
@@ -1173,7 +1122,7 @@ md_assemble (str)
       if (* op_end == ',')
 	{
 	  op_end = parse_imm (op_end + 1, & reg, 0, 31);
-	  /* immediate values of 0 -> 6 translate to movi */
+	  /* Immediate values of 0 -> 6 translate to movi.  */
 	  if (reg <= 6)
 	    {
 	      inst = (inst & 0xF) | MCORE_INST_BGENI_ALT;
@@ -1189,7 +1138,7 @@ md_assemble (str)
       output = frag_more (2);
       break;
 
-    case OBR2:	/* like OBR, but arg is 2^n instead of n */
+    case OBR2:	/* Like OBR, but arg is 2^n instead of n.  */
       op_end = parse_reg (op_end + 1, & reg);
       inst |= reg;
 
@@ -1203,7 +1152,7 @@ md_assemble (str)
 
 	  /* Further restrict the immediate to a power of two.  */
 	  if ((reg & (reg - 1)) == 0)
-	    reg = log2 (reg);
+	    reg = mylog2 (reg);
 	  else
 	    {
 	      reg = 0;
@@ -1542,7 +1491,8 @@ md_assemble (str)
 	}
       break;
 
-    case RSI:				/* SI, but imm becomes 32-imm */
+    case RSI:
+      /* SI, but imm becomes 32-imm.  */
       op_end = parse_reg (op_end + 1, & reg);
       inst |= reg;
 
@@ -1656,31 +1606,28 @@ md_assemble (str)
 }
 
 symbolS *
-md_undefined_symbol (name)
-       char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_mcore_end ()
+md_mcore_end (void)
 {
   dump_literals (0);
   subseg_set (text_section, 0);
 }
 
 /* Various routines to kill one day.  */
-/* Equal to MAX_PRECISION in atof-ieee.c */
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
 #define MAX_LITTLENUMS 6
 
 /* Turn a string in input_line_pointer into a floating point constant of type
    type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
-   emitted is stored in *sizeP.  An error message is returned, or NULL on OK.*/
+   emitted is stored in *sizeP.  An error message is returned, or NULL on OK.  */
+
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char * litP;
-     int * sizeP;
+md_atof (int type,  char * litP, int * sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -1747,13 +1694,16 @@ md_atof (type, litP, sizeP)
 
 const char * md_shortopts = "";
 
-#define OPTION_JSRI2BSR_ON	(OPTION_MD_BASE + 0)
-#define OPTION_JSRI2BSR_OFF	(OPTION_MD_BASE + 1)
-#define OPTION_SIFILTER_ON	(OPTION_MD_BASE + 2)
-#define OPTION_SIFILTER_OFF	(OPTION_MD_BASE + 3)
-#define OPTION_CPU		(OPTION_MD_BASE + 4)
-#define OPTION_EB		(OPTION_MD_BASE + 5)
-#define OPTION_EL		(OPTION_MD_BASE + 6)
+enum options
+{
+  OPTION_JSRI2BSR_ON = OPTION_MD_BASE,
+  OPTION_JSRI2BSR_OFF,
+  OPTION_SIFILTER_ON,
+  OPTION_SIFILTER_OFF,
+  OPTION_CPU,
+  OPTION_EB,
+  OPTION_EL,
+};
 
 struct option md_longopts[] =
 {
@@ -1770,9 +1720,7 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char * arg;
+md_parse_option (int c, char * arg)
 {
   switch (c)
     {
@@ -1801,8 +1749,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE * stream;
+md_show_usage (FILE * stream)
 {
   fprintf (stream, _("\
 MCORE specific options:\n\
@@ -1816,38 +1763,36 @@ MCORE specific options:\n\
 int md_short_jump_size;
 
 void
-md_create_short_jump (ptr, from_Nddr, to_Nddr, frag, to_symbol)
-     char * ptr ATTRIBUTE_UNUSED;
-     addressT from_Nddr ATTRIBUTE_UNUSED;
-     addressT to_Nddr ATTRIBUTE_UNUSED;
-     fragS * frag ATTRIBUTE_UNUSED;
-     symbolS * to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char * ptr ATTRIBUTE_UNUSED,
+		      addressT from_Nddr ATTRIBUTE_UNUSED,
+		      addressT to_Nddr ATTRIBUTE_UNUSED,
+		      fragS * frag ATTRIBUTE_UNUSED,
+		      symbolS * to_symbol ATTRIBUTE_UNUSED)
 {
   as_fatal (_("failed sanity check: short_jump"));
 }
 
 void
-md_create_long_jump (ptr, from_Nddr, to_Nddr, frag, to_symbol)
-     char * ptr ATTRIBUTE_UNUSED;
-     addressT from_Nddr ATTRIBUTE_UNUSED;
-     addressT to_Nddr ATTRIBUTE_UNUSED;
-     fragS * frag ATTRIBUTE_UNUSED;
-     symbolS * to_symbol ATTRIBUTE_UNUSED;
+md_create_long_jump (char * ptr ATTRIBUTE_UNUSED,
+		     addressT from_Nddr ATTRIBUTE_UNUSED,
+		     addressT to_Nddr ATTRIBUTE_UNUSED,
+		     fragS * frag ATTRIBUTE_UNUSED,
+		     symbolS * to_symbol ATTRIBUTE_UNUSED)
 {
   as_fatal (_("failed sanity check: long_jump"));
 }
 
 /* Called after relaxing, change the frags so they know how big they are.  */
+
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd * abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     register fragS * fragP;
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS * fragP)
 {
-  unsigned char * buffer;
+  char *buffer;
   int targ_addr = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
 
-  buffer = (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
+  buffer = fragP->fr_fix + fragP->fr_literal;
 
   switch (fragP->fr_subtype)
     {
@@ -1889,47 +1834,46 @@ md_convert_frag (abfd, sec, fragP)
     case C (COND_JUMP, UNDEF_WORD_DISP):
       {
 	/* A conditional branch wont fit into 12 bits so:
-	 *	b!cond	1f
-	 *	jmpi	0f
-	 *	.align 2
-	 * 0:	.long disp
-	 * 1:
-	 *
-	 * if the b!cond is 4 byte aligned, the literal which would
-	 * go at x+4 will also be aligned.
-	 */
+	  	b!cond	1f
+	  	jmpi	0f
+	  	.align 2
+	   0:	.long disp
+	   1:
+	  
+	   If the b!cond is 4 byte aligned, the literal which would
+	   go at x+4 will also be aligned.  */
 	int first_inst = fragP->fr_fix + fragP->fr_address;
 	int needpad = (first_inst & 3);
 
 	if (! target_big_endian)
 	  buffer[1] ^= 0x08;
 	else
-	  buffer[0] ^= 0x08;	/* Toggle T/F bit */
+	  buffer[0] ^= 0x08;	/* Toggle T/F bit.  */
 
-	buffer[2] = INST_BYTE0 (MCORE_INST_JMPI);	/* Build jmpi */
+	buffer[2] = INST_BYTE0 (MCORE_INST_JMPI);	/* Build jmpi.  */
 	buffer[3] = INST_BYTE1 (MCORE_INST_JMPI);
 
 	if (needpad)
 	  {
 	    if (! target_big_endian)
 	      {
-		buffer[0] = 4;	/* branch over jmpi, pad, and ptr */
-		buffer[2] = 1;	/* jmpi offset of 1 gets the pointer */
+		buffer[0] = 4;	/* Branch over jmpi, pad, and ptr.  */
+		buffer[2] = 1;	/* Jmpi offset of 1 gets the pointer.  */
 	      }
 	    else
 	      {
-		buffer[1] = 4;	/* branch over jmpi, pad, and ptr */
-		buffer[3] = 1;	/* jmpi offset of 1 gets the pointer */
+		buffer[1] = 4;	/* Branch over jmpi, pad, and ptr.  */
+		buffer[3] = 1;	/* Jmpi offset of 1 gets the pointer.  */
 	      }
 
-	    buffer[4] = 0;	/* alignment/pad */
+	    buffer[4] = 0;	/* Alignment/pad.  */
 	    buffer[5] = 0;
-	    buffer[6] = 0;	/* space for 32 bit address */
+	    buffer[6] = 0;	/* Space for 32 bit address.  */
 	    buffer[7] = 0;
 	    buffer[8] = 0;
 	    buffer[9] = 0;
 
-	    /* Make reloc for the long disp */
+	    /* Make reloc for the long disp.  */
 	    fix_new (fragP, fragP->fr_fix + 6, 4,
 		     fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_32);
 
@@ -1943,16 +1887,16 @@ md_convert_frag (abfd, sec, fragP)
 	       for this fragment.  */
 	    if (! target_big_endian)
 	      {
-		buffer[0] = 3;	/* branch over jmpi, and ptr */
-		buffer[2] = 0;	/* jmpi offset of 0 gets the pointer */
+		buffer[0] = 3;	/* Branch over jmpi, and ptr.  */
+		buffer[2] = 0;	/* Jmpi offset of 0 gets the pointer.  */
 	      }
 	    else
 	      {
-		buffer[1] = 3;	/* branch over jmpi, and ptr */
-		buffer[3] = 0;	/* jmpi offset of 0 gets the pointer */
+		buffer[1] = 3;	/* Branch over jmpi, and ptr.  */
+		buffer[3] = 0;	/* Jmpi offset of 0 gets the pointer.  */
 	      }
 
-	    buffer[4] = 0;	/* space for 32 bit address */
+	    buffer[4] = 0;	/* Space for 32 bit address.  */
 	    buffer[5] = 0;
 	    buffer[6] = 0;
 	    buffer[7] = 0;
@@ -1968,9 +1912,9 @@ md_convert_frag (abfd, sec, fragP)
 	       full length of the fragment, not just what we actually
 	       filled in.  */
 	    if (! target_big_endian)
-	      buffer[0] = 4;	/* jmpi, ptr, and the 'tail pad' */
+	      buffer[0] = 4;	/* Jmpi, ptr, and the 'tail pad'.  */
 	    else
-	      buffer[1] = 4;	/* jmpi, ptr, and the 'tail pad' */
+	      buffer[1] = 4;	/* Jmpi, ptr, and the 'tail pad'.  */
 	  }
       }
       break;
@@ -1984,22 +1928,22 @@ md_convert_frag (abfd, sec, fragP)
 	  	.align 2
 	     0:	.long disp
 	   we need a pad if "first_inst" is 4 byte aligned.
-	   [because the natural literal place is x + 2]  */
+	   [because the natural literal place is x + 2].  */
 	int first_inst = fragP->fr_fix + fragP->fr_address;
 	int needpad = !(first_inst & 3);
 
-	buffer[0] = INST_BYTE0 (MCORE_INST_JMPI);	/* Build jmpi */
+	buffer[0] = INST_BYTE0 (MCORE_INST_JMPI);	/* Build jmpi.  */
 	buffer[1] = INST_BYTE1 (MCORE_INST_JMPI);
 
 	if (needpad)
 	  {
 	    if (! target_big_endian)
-	      buffer[0] = 1;	/* jmpi offset of 1 since padded */
+	      buffer[0] = 1;	/* Jmpi offset of 1 since padded.  */
 	    else
-	      buffer[1] = 1;	/* jmpi offset of 1 since padded */
-	    buffer[2] = 0;	/* alignment */
+	      buffer[1] = 1;	/* Jmpi offset of 1 since padded.  */
+	    buffer[2] = 0;	/* Alignment.  */
 	    buffer[3] = 0;
-	    buffer[4] = 0;	/* space for 32 bit address */
+	    buffer[4] = 0;	/* Space for 32 bit address.  */
 	    buffer[5] = 0;
 	    buffer[6] = 0;
 	    buffer[7] = 0;
@@ -2013,10 +1957,10 @@ md_convert_frag (abfd, sec, fragP)
 	else
 	  {
 	    if (! target_big_endian)
-	      buffer[0] = 0;	/* jmpi offset of 0 if no pad */
+	      buffer[0] = 0;	/* Jmpi offset of 0 if no pad.  */
 	    else
-	      buffer[1] = 0;	/* jmpi offset of 0 if no pad */
-	    buffer[2] = 0;	/* space for 32 bit address */
+	      buffer[1] = 0;	/* Jmpi offset of 0 if no pad.  */
+	    buffer[2] = 0;	/* Space for 32 bit address.  */
 	    buffer[3] = 0;
 	    buffer[4] = 0;
 	    buffer[5] = 0;
@@ -2038,10 +1982,9 @@ md_convert_frag (abfd, sec, fragP)
    Also sets up addends for 'rela' type relocations.  */
 
 void
-md_apply_fix3 (fixP, valP, segment)
-     fixS *   fixP;
-     valueT * valP;
-     segT     segment ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *   fixP,
+	       valueT * valP,
+	       segT     segment ATTRIBUTE_UNUSED)
 {
   char *       buf  = fixP->fx_where + fixP->fx_frag->fr_literal;
   char *       file = fixP->fx_file ? fixP->fx_file : _("unknown");
@@ -2067,7 +2010,8 @@ md_apply_fix3 (fixP, valP, segment)
 
   switch (fixP->fx_r_type)
     {
-    case BFD_RELOC_MCORE_PCREL_IMM11BY2:     /* second byte of 2 byte opcode */
+      /* Second byte of 2 byte opcode.  */
+    case BFD_RELOC_MCORE_PCREL_IMM11BY2:
       if ((val & 1) != 0)
 	as_bad_where (file, fixP->fx_line,
 		      _("odd distance branch (0x%lx bytes)"), (long) val);
@@ -2088,7 +2032,8 @@ md_apply_fix3 (fixP, valP, segment)
 	}
       break;
 
-    case BFD_RELOC_MCORE_PCREL_IMM8BY4:	/* lower 8 bits of 2 byte opcode */
+      /* Lower 8 bits of 2 byte opcode.  */
+    case BFD_RELOC_MCORE_PCREL_IMM8BY4:
       val += 3;
       val /= 4;
       if (val & ~0xff)
@@ -2101,7 +2046,8 @@ md_apply_fix3 (fixP, valP, segment)
 	buf[1] |= (val & 0xff);
       break;
 
-    case BFD_RELOC_MCORE_PCREL_IMM4BY2:	/* loopt instruction */
+      /* Loopt instruction.  */
+    case BFD_RELOC_MCORE_PCREL_IMM4BY2:
       if ((val < -32) || (val > -2))
 	as_bad_where (file, fixP->fx_line,
 		      _("pcrel for loopt too far (0x%lx)"), (long) val);
@@ -2161,8 +2107,7 @@ md_apply_fix3 (fixP, valP, segment)
 }
 
 void
-md_operand (expressionP)
-     expressionS * expressionP;
+md_operand (expressionS * expressionP)
 {
   /* Ignore leading hash symbol, if poresent.  */
   if (* input_line_pointer == '#')
@@ -2177,9 +2122,7 @@ int md_long_jump_size;
 /* Called just before address relaxation, return the length
    by which a fragment must grow to reach it's destination.  */
 int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS * fragP;
-     register segT segment_type;
+md_estimate_size_before_relax (fragS * fragP, segT segment_type)
 {
   switch (fragP->fr_subtype)
     {
@@ -2189,38 +2132,26 @@ md_estimate_size_before_relax (fragP, segment_type)
     case C (UNCD_JUMP, UNDEF_DISP):
       /* Used to be a branch to somewhere which was unknown.  */
       if (!fragP->fr_symbol)
-	{
-	  fragP->fr_subtype = C (UNCD_JUMP, DISP12);
-	}
+	fragP->fr_subtype = C (UNCD_JUMP, DISP12);
       else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
-	{
-	  fragP->fr_subtype = C (UNCD_JUMP, DISP12);
-	}
+	fragP->fr_subtype = C (UNCD_JUMP, DISP12);
       else
-	{
-	  fragP->fr_subtype = C (UNCD_JUMP, UNDEF_WORD_DISP);
-	}
+	fragP->fr_subtype = C (UNCD_JUMP, UNDEF_WORD_DISP);
       break;
 
     case C (COND_JUMP, UNDEF_DISP):
       /* Used to be a branch to somewhere which was unknown.  */
       if (fragP->fr_symbol
 	  && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
-	{
-	  /* Got a symbol and it's defined in this segment, become byte
-	     sized - maybe it will fix up */
-	  fragP->fr_subtype = C (COND_JUMP, DISP12);
-	}
+	/* Got a symbol and it's defined in this segment, become byte
+	   sized - maybe it will fix up */
+	fragP->fr_subtype = C (COND_JUMP, DISP12);
       else if (fragP->fr_symbol)
-	{
-	  /* Its got a segment, but its not ours, so it will always be long.  */
-	  fragP->fr_subtype = C (COND_JUMP, UNDEF_WORD_DISP);
-	}
+	/* Its got a segment, but its not ours, so it will always be long.  */
+	fragP->fr_subtype = C (COND_JUMP, UNDEF_WORD_DISP);
       else
-	{
-	  /* We know the abs value.  */
-	  fragP->fr_subtype = C (COND_JUMP, DISP12);
-	}
+	/* We know the abs value.  */
+	fragP->fr_subtype = C (COND_JUMP, DISP12);
       break;
 
     case C (UNCD_JUMP, DISP12):
@@ -2238,47 +2169,45 @@ md_estimate_size_before_relax (fragP, segment_type)
 }
 
 /* Put number into target byte order.  */
+
 void
-md_number_to_chars (ptr, use, nbytes)
-     char * ptr;
-     valueT use;
-     int nbytes;
+md_number_to_chars (char * ptr, valueT use, int nbytes)
 {
   if (! target_big_endian)
     switch (nbytes)
       {
-      case 4: ptr[3] = (use >> 24) & 0xff; /* fall through */
-      case 3: ptr[2] = (use >> 16) & 0xff; /* fall through */
-      case 2: ptr[1] = (use >>  8) & 0xff; /* fall through */
+      case 4: ptr[3] = (use >> 24) & 0xff; /* Fall through.  */
+      case 3: ptr[2] = (use >> 16) & 0xff; /* Fall through.  */
+      case 2: ptr[1] = (use >>  8) & 0xff; /* Fall through.  */
       case 1: ptr[0] = (use >>  0) & 0xff;    break;
       default: abort ();
       }
   else
     switch (nbytes)
       {
-      case 4: *ptr++ = (use >> 24) & 0xff; /* fall through */
-      case 3: *ptr++ = (use >> 16) & 0xff; /* fall through */
-      case 2: *ptr++ = (use >>  8) & 0xff; /* fall through */
+      case 4: *ptr++ = (use >> 24) & 0xff; /* Fall through.  */
+      case 3: *ptr++ = (use >> 16) & 0xff; /* Fall through.  */
+      case 2: *ptr++ = (use >>  8) & 0xff; /* Fall through.  */
       case 1: *ptr++ = (use >>  0) & 0xff;    break;
       default: abort ();
       }
 }
 
 /* Round up a section size to the appropriate boundary.  */
+
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED,
+		  valueT size)
 {
-  return size;			/* Byte alignment is fine */
+  /* Byte alignment is fine.  */
+  return size;
 }
 
 /* The location from which a PC relative jump should be calculated,
    given a PC relative reloc.  */
+
 long
-md_pcrel_from_section (fixp, sec)
-     fixS * fixp;
-     segT sec ATTRIBUTE_UNUSED;
+md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
 {
 #ifdef OBJ_ELF
   /* If the symbol is undefined or defined in another section
@@ -2302,9 +2231,7 @@ md_pcrel_from_section (fixp, sec)
 #define MAP(SZ,PCREL,TYPE)	case F (SZ, PCREL): code = (TYPE); break
 
 arelent *
-tc_gen_reloc (section, fixp)
-     asection * section ATTRIBUTE_UNUSED;
-     fixS * fixp;
+tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
 {
   arelent * rel;
   bfd_reloc_code_real_type code;
@@ -2340,8 +2267,8 @@ tc_gen_reloc (section, fixp)
       break;
   }
 
-  rel = (arelent *) xmalloc (sizeof (arelent));
-  rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
   /* Always pass the addend along!  */
@@ -2368,8 +2295,7 @@ tc_gen_reloc (section, fixp)
    This is used to force out switch and PC relative relocations when
    relaxing.  */
 int
-mcore_force_relocation (fix)
-     fixS * fix;
+mcore_force_relocation (fixS * fix)
 {
   if (fix->fx_r_type == BFD_RELOC_RVA)
     return 1;
@@ -2379,9 +2305,9 @@ mcore_force_relocation (fix)
 
 /* Return true if the fix can be handled by GAS, false if it must
    be passed through to the linker.  */
+
 bfd_boolean
-mcore_fix_adjustable (fixP)
-   fixS * fixP;
+mcore_fix_adjustable (fixS * fixP)
 {
   /* We need the symbol name for the VTABLE entries.  */
   if (   fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
diff --git a/gas/config/tc-mcore.h b/gas/config/tc-mcore.h
index b685a4ef49b7..16346384c58f 100644
--- a/gas/config/tc-mcore.h
+++ b/gas/config/tc-mcore.h
@@ -1,6 +1,6 @@
 /* This file is tc-mcore.h
 
-   Copyright 1999, 2000, 2001, 2002, 2003
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,43 +17,27 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the
-   Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef	TC_MCORE
 #define TC_MCORE 1
 
-#ifndef BFD_ASSEMBLER
- #error MCORE support requires BFD_ASSEMBLER
-#endif
-
 #define TARGET_ARCH	bfd_arch_mcore
 /* Used to initialise target_big_endian.  */
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-/* Don't write out relocs for pcrel stuff.  */
-#define TC_COUNT_RELOC(x) (((x)->fx_addsy || (x)->fx_subsy) && \
-			   (x)->fx_r_type < BFD_RELOC_MCORE_PCREL_IMM8BY4)
-
 #define IGNORE_NONSTANDARD_ESCAPES
 
-#define TC_RELOC_MANGLE(a,b,c) tc_reloc_mangle (a, b, c)
-
 /* Some pseudo-op semantic extensions.  */
 #define	PSEUDO_LCOMM_OPTIONAL_ALIGN
 
 #define LISTING_HEADER        	"M.CORE GAS Version 2.9.4"
 #define LISTING_LHS_CONT_LINES	4
 
-#define NEED_FX_R_TYPE	1
-#define COFF_FLAGS 	1
-
 /* We want local label support.  */
 #define LOCAL_LABELS_FB 1
 
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
-int tc_coff_sizemachdep PARAMS ((struct frag *));
-
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
 #define md_end	md_mcore_end
@@ -89,12 +73,10 @@ struct mcore_tc_sy
 
 /* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
 #define TC_FORCE_RELOCATION(fix) mcore_force_relocation (fix)
-extern int mcore_force_relocation PARAMS ((struct fix *));
 
 #define tc_fix_adjustable(FIX) mcore_fix_adjustable (FIX)
-extern bfd_boolean mcore_fix_adjustable PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #endif /* OBJ_ELF */
@@ -105,8 +87,10 @@ extern bfd_boolean mcore_fix_adjustable PARAMS ((struct fix *));
 
 #include "write.h"        /* For definition of fixS */
 
-extern void      md_mcore_end        PARAMS ((void));
-extern long      md_pcrel_from_section         PARAMS ((fixS *, segT));
-extern arelent * tc_gen_reloc                  PARAMS ((asection *, fixS *));
+extern void        md_mcore_end           (void);
+extern long        md_pcrel_from_section  (fixS *, segT);
+extern arelent *   tc_gen_reloc           (asection *, fixS *);
+extern int         mcore_force_relocation (fixS *);
+extern bfd_boolean mcore_fix_adjustable   (fixS *);
 
 #endif /* TC_MCORE */
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index a448265d47d1..c885205dad47 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1,6 +1,6 @@
 /* tc-mips.c -- assemble code for a MIPS chip.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004 Free Software Foundation, Inc.
+   2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
    Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
@@ -20,8 +20,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 #include "config.h"
@@ -33,6 +33,7 @@
 #include "opcode/mips.h"
 #include "itbl-ops.h"
 #include "dwarf2dbg.h"
+#include "dw2gencfi.h"
 
 #ifdef DEBUG
 #define DBG(x) printf x
@@ -111,9 +112,7 @@ static char *mips_regmask_frag;
 extern int target_big_endian;
 
 /* The name of the readonly data section.  */
-#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
-			    ? ".data" \
-			    : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
+#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
 			    ? ".rdata" \
 			    : OUTPUT_FLAVOR == bfd_target_coff_flavour \
 			    ? ".rdata" \
@@ -121,6 +120,43 @@ extern int target_big_endian;
 			    ? ".rodata" \
 			    : (abort (), ""))
 
+/* Information about an instruction, including its format, operands
+   and fixups.  */
+struct mips_cl_insn
+{
+  /* The opcode's entry in mips_opcodes or mips16_opcodes.  */
+  const struct mips_opcode *insn_mo;
+
+  /* True if this is a mips16 instruction and if we want the extended
+     form of INSN_MO.  */
+  bfd_boolean use_extend;
+
+  /* The 16-bit extension instruction to use when USE_EXTEND is true.  */
+  unsigned short extend;
+
+  /* The 16-bit or 32-bit bitstring of the instruction itself.  This is
+     a copy of INSN_MO->match with the operands filled in.  */
+  unsigned long insn_opcode;
+
+  /* The frag that contains the instruction.  */
+  struct frag *frag;
+
+  /* The offset into FRAG of the first instruction byte.  */
+  long where;
+
+  /* The relocs associated with the instruction, if any.  */
+  fixS *fixp[3];
+
+  /* True if this entry cannot be moved from its current position.  */
+  unsigned int fixed_p : 1;
+
+  /* True if this instruction occured in a .set noreorder block.  */
+  unsigned int noreorder_p : 1;
+
+  /* True for mips16 instructions that jump to an absolute address.  */
+  unsigned int mips16_absolute_jump_p : 1;
+};
+
 /* The ABI to use.  */
 enum mips_abi_level
 {
@@ -138,6 +174,10 @@ static enum mips_abi_level mips_abi = NO_ABI;
 /* Whether or not we have code that can call pic code.  */
 int mips_abicalls = FALSE;
 
+/* Whether or not we have code which can be put into a shared
+   library.  */
+static bfd_boolean mips_in_shared = TRUE;
+
 /* This is the set of options which may be modified by the .set
    pseudo-op.  We use a struct so that .set push and .set pop are more
    reliable.  */
@@ -153,6 +193,8 @@ struct mips_set_options
      command line options, and based on the default architecture.  */
   int ase_mips3d;
   int ase_mdmx;
+  int ase_dsp;
+  int ase_mt;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
      Changed by `.set mips16' and `.set nomips16', and the -mips16 and
@@ -187,6 +229,8 @@ struct mips_set_options
   /* MIPS architecture (CPU) type.  Changed by .set arch=FOO, the -march
      command line option, and the default CPU.  */
   int arch;
+  /* True if ".set sym32" is in effect.  */
+  bfd_boolean sym32;
 };
 
 /* True if -mgp32 was passed.  */
@@ -201,7 +245,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
+  ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -225,6 +269,14 @@ static int file_ase_mips3d;
    command line (e.g., by -march).  */
 static int file_ase_mdmx;
 
+/* True if -mdsp was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_dsp;
+
+/* True if -mmt was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_mt;
+
 /* The argument of the -march= flag.  The architecture we are assembling.  */
 static int file_mips_arch = CPU_UNKNOWN;
 static const char *mips_arch_string;
@@ -281,15 +333,19 @@ static int mips_32bitmode = 0;
 
 #define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
 
-/* We can only have 64bit addresses if the object file format
-   supports it.  */
-#define HAVE_32BIT_ADDRESSES                           \
-   (HAVE_32BIT_GPRS                                    \
-    || ((bfd_arch_bits_per_address (stdoutput) == 32   \
-         || ! HAVE_64BIT_OBJECTS)                      \
-        && mips_pic != EMBEDDED_PIC))
+/* True if relocations are stored in-place.  */
+#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
 
-#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
+/* The ABI-derived address size.  */
+#define HAVE_64BIT_ADDRESSES \
+  (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
+#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
+
+/* The size of symbolic constants (i.e., expressions of the form
+   "SYMBOL" or "SYMBOL + OFFSET").  */
+#define HAVE_32BIT_SYMBOLS \
+  (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
+#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
 
 /* Addresses are loaded in different ways, depending on the address size
    in use.  The n32 ABI Documentation also mandates the use of additions
@@ -319,6 +375,14 @@ static int mips_32bitmode = 0;
 #define CPU_HAS_MDMX(cpu)	(FALSE                 \
 				 )
 
+/* Return true if the given CPU supports the DSP ASE.  */
+#define CPU_HAS_DSP(cpu)	(FALSE                 \
+				 )
+
+/* Return true if the given CPU supports the MT ASE.  */
+#define CPU_HAS_MT(cpu)		(FALSE                 \
+				 )
+
 /* True if CPU has a dror instruction.  */
 #define CPU_HAS_DROR(CPU)	((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
 
@@ -346,7 +410,6 @@ static int mips_32bitmode = 0;
    || mips_opts.arch == CPU_R10000                    \
    || mips_opts.arch == CPU_R12000                    \
    || mips_opts.arch == CPU_RM7000                    \
-   || mips_opts.arch == CPU_SB1                       \
    || mips_opts.arch == CPU_VR5500                    \
    )
 
@@ -357,8 +420,6 @@ static int mips_32bitmode = 0;
    level I.  */
 #define gpr_interlocks \
   (mips_opts.isa != ISA_MIPS1  \
-   || mips_opts.arch == CPU_VR5400  \
-   || mips_opts.arch == CPU_VR5500  \
    || mips_opts.arch == CPU_R3900)
 
 /* Whether the processor uses hardware interlocks to avoid delays
@@ -374,9 +435,6 @@ static int mips_32bitmode = 0;
     && mips_opts.isa != ISA_MIPS2                     \
     && mips_opts.isa != ISA_MIPS3)                    \
    || mips_opts.arch == CPU_R4300                     \
-   || mips_opts.arch == CPU_VR5400                    \
-   || mips_opts.arch == CPU_VR5500                    \
-   || mips_opts.arch == CPU_SB1                       \
    )
 
 /* Whether the processor uses hardware interlocks to protect reads
@@ -518,44 +576,27 @@ static int mips_optimize = 2;
    equivalent to seeing no -g option at all.  */
 static int mips_debug = 0;
 
-/* The previous instruction.  */
-static struct mips_cl_insn prev_insn;
-
-/* The instruction before prev_insn.  */
-static struct mips_cl_insn prev_prev_insn;
-
-/* If we don't want information for prev_insn or prev_prev_insn, we
-   point the insn_mo field at this dummy integer.  */
-static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
-
-/* Non-zero if prev_insn is valid.  */
-static int prev_insn_valid;
-
-/* The frag for the previous instruction.  */
-static struct frag *prev_insn_frag;
-
-/* The offset into prev_insn_frag for the previous instruction.  */
-static long prev_insn_where;
+/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata.  */
+#define MAX_VR4130_NOPS 4
 
-/* The reloc type for the previous instruction, if any.  */
-static bfd_reloc_code_real_type prev_insn_reloc_type[3];
+/* The maximum number of NOPs needed to fill delay slots.  */
+#define MAX_DELAY_NOPS 2
 
-/* The reloc for the previous instruction, if any.  */
-static fixS *prev_insn_fixp[3];
+/* The maximum number of NOPs needed for any purpose.  */
+#define MAX_NOPS 4
 
-/* Non-zero if the previous instruction was in a delay slot.  */
-static int prev_insn_is_delay_slot;
+/* A list of previous instructions, with index 0 being the most recent.
+   We need to look back MAX_NOPS instructions when filling delay slots
+   or working around processor errata.  We need to look back one
+   instruction further if we're thinking about using history[0] to
+   fill a branch delay slot.  */
+static struct mips_cl_insn history[1 + MAX_NOPS];
 
-/* Non-zero if the previous instruction was in a .set noreorder.  */
-static int prev_insn_unreordered;
+/* Nop instructions used by emit_nop.  */
+static struct mips_cl_insn nop_insn, mips16_nop_insn;
 
-/* Non-zero if the previous instruction uses an extend opcode (if
-   mips16).  */
-static int prev_insn_extended;
-
-/* Non-zero if the previous previous instruction was in a .set
-   noreorder.  */
-static int prev_prev_insn_unreordered;
+/* The appropriate nop for the current mode.  */
+#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
 
 /* If this is set, it points to a frag holding nop instructions which
    were inserted before the start of a noreorder section.  If those
@@ -622,8 +663,29 @@ static const unsigned int mips16_to_32_reg_map[] =
   16, 17, 2, 3, 4, 5, 6, 7
 };
 
+/* Classifies the kind of instructions we're interested in when
+   implementing -mfix-vr4120.  */
+enum fix_vr4120_class {
+  FIX_VR4120_MACC,
+  FIX_VR4120_DMACC,
+  FIX_VR4120_MULT,
+  FIX_VR4120_DMULT,
+  FIX_VR4120_DIV,
+  FIX_VR4120_MTHILO,
+  NUM_FIX_VR4120_CLASSES
+};
+
+/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
+   there must be at least one other instruction between an instruction
+   of type X and an instruction of type Y.  */
+static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
+
+/* True if -mfix-vr4120 is in force.  */
 static int mips_fix_vr4120;
 
+/* ...likewise -mfix-vr4130.  */
+static int mips_fix_vr4130;
+
 /* We don't relax branches by default, since this causes us to expand
    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
    fail to compute the offset before expanding the macro to the most
@@ -817,6 +879,41 @@ static int mips_relax_branch;
   (((x) &~ (offsetT) 0x7fff) == 0					\
    || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
 
+/* Is the given value a zero-extended 32-bit value?  Or a negated one?  */
+#define IS_ZEXT_32BIT_NUM(x)						\
+  (((x) &~ (offsetT) 0xffffffff) == 0					\
+   || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
+
+/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
+   VALUE << SHIFT.  VALUE is evaluated exactly once.  */
+#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
+  (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
+	      | (((VALUE) & (MASK)) << (SHIFT)))
+
+/* Extract bits MASK << SHIFT from STRUCT and shift them right
+   SHIFT places.  */
+#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
+  (((STRUCT) >> (SHIFT)) & (MASK))
+
+/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
+   INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
+
+   include/opcode/mips.h specifies operand fields using the macros
+   OP_MASK_<FIELD> and OP_SH_<FIELD>.  The MIPS16 equivalents start
+   with "MIPS16OP" instead of "OP".  */
+#define INSERT_OPERAND(FIELD, INSN, VALUE) \
+  INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
+#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
+  INSERT_BITS ((INSN).insn_opcode, VALUE, \
+		MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
+
+/* Extract the operand given by FIELD from mips_cl_insn INSN.  */
+#define EXTRACT_OPERAND(FIELD, INSN) \
+  EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
+#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
+  EXTRACT_BITS ((INSN).insn_opcode, \
+		MIPS16OP_MASK_##FIELD, \
+		MIPS16OP_SH_##FIELD)
 
 /* Global variables used when generating relaxable macros.  See the
    comment above RELAX_ENCODE for more details about how relaxation
@@ -863,7 +960,7 @@ enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
 
 static void append_insn
   (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
-static void mips_no_prev_insn (int);
+static void mips_no_prev_insn (void);
 static void mips16_macro_build
   (expressionS *, const char *, const char *, va_list);
 static void load_register (int, expressionS *, int);
@@ -1089,13 +1186,17 @@ mips_target_format (void)
 {
   switch (OUTPUT_FLAVOR)
     {
-    case bfd_target_aout_flavour:
-      return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
     case bfd_target_ecoff_flavour:
       return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
     case bfd_target_coff_flavour:
       return "pe-mips";
     case bfd_target_elf_flavour:
+#ifdef TE_VXWORKS
+      if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
+	return (target_big_endian
+		? "elf32-bigmips-vxworks"
+		: "elf32-littlemips-vxworks");
+#endif
 #ifdef TE_TMIPS
       /* This is traditional mips.  */
       return (target_big_endian
@@ -1124,6 +1225,174 @@ mips_target_format (void)
     }
 }
 
+/* Return the length of instruction INSN.  */
+
+static inline unsigned int
+insn_length (const struct mips_cl_insn *insn)
+{
+  if (!mips_opts.mips16)
+    return 4;
+  return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
+}
+
+/* Initialise INSN from opcode entry MO.  Leave its position unspecified.  */
+
+static void
+create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
+{
+  size_t i;
+
+  insn->insn_mo = mo;
+  insn->use_extend = FALSE;
+  insn->extend = 0;
+  insn->insn_opcode = mo->match;
+  insn->frag = NULL;
+  insn->where = 0;
+  for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
+    insn->fixp[i] = NULL;
+  insn->fixed_p = (mips_opts.noreorder > 0);
+  insn->noreorder_p = (mips_opts.noreorder > 0);
+  insn->mips16_absolute_jump_p = 0;
+}
+
+/* Install INSN at the location specified by its "frag" and "where" fields.  */
+
+static void
+install_insn (const struct mips_cl_insn *insn)
+{
+  char *f = insn->frag->fr_literal + insn->where;
+  if (!mips_opts.mips16)
+    md_number_to_chars (f, insn->insn_opcode, 4);
+  else if (insn->mips16_absolute_jump_p)
+    {
+      md_number_to_chars (f, insn->insn_opcode >> 16, 2);
+      md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
+    }
+  else
+    {
+      if (insn->use_extend)
+	{
+	  md_number_to_chars (f, 0xf000 | insn->extend, 2);
+	  f += 2;
+	}
+      md_number_to_chars (f, insn->insn_opcode, 2);
+    }
+}
+
+/* Move INSN to offset WHERE in FRAG.  Adjust the fixups accordingly
+   and install the opcode in the new location.  */
+
+static void
+move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
+{
+  size_t i;
+
+  insn->frag = frag;
+  insn->where = where;
+  for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
+    if (insn->fixp[i] != NULL)
+      {
+	insn->fixp[i]->fx_frag = frag;
+	insn->fixp[i]->fx_where = where;
+      }
+  install_insn (insn);
+}
+
+/* Add INSN to the end of the output.  */
+
+static void
+add_fixed_insn (struct mips_cl_insn *insn)
+{
+  char *f = frag_more (insn_length (insn));
+  move_insn (insn, frag_now, f - frag_now->fr_literal);
+}
+
+/* Start a variant frag and move INSN to the start of the variant part,
+   marking it as fixed.  The other arguments are as for frag_var.  */
+
+static void
+add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
+		  relax_substateT subtype, symbolS *symbol, offsetT offset)
+{
+  frag_grow (max_chars);
+  move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
+  insn->fixed_p = 1;
+  frag_var (rs_machine_dependent, max_chars, var,
+	    subtype, symbol, offset, NULL);
+}
+
+/* Insert N copies of INSN into the history buffer, starting at
+   position FIRST.  Neither FIRST nor N need to be clipped.  */
+
+static void
+insert_into_history (unsigned int first, unsigned int n,
+		     const struct mips_cl_insn *insn)
+{
+  if (mips_relax.sequence != 2)
+    {
+      unsigned int i;
+
+      for (i = ARRAY_SIZE (history); i-- > first;)
+	if (i >= first + n)
+	  history[i] = history[i - n];
+	else
+	  history[i] = *insn;
+    }
+}
+
+/* Emit a nop instruction, recording it in the history buffer.  */
+
+static void
+emit_nop (void)
+{
+  add_fixed_insn (NOP_INSN);
+  insert_into_history (0, 1, NOP_INSN);
+}
+
+/* Initialize vr4120_conflicts.  There is a bit of duplication here:
+   the idea is to make it obvious at a glance that each errata is
+   included.  */
+
+static void
+init_vr4120_conflicts (void)
+{
+#define CONFLICT(FIRST, SECOND) \
+    vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
+
+  /* Errata 21 - [D]DIV[U] after [D]MACC */
+  CONFLICT (MACC, DIV);
+  CONFLICT (DMACC, DIV);
+
+  /* Errata 23 - Continuous DMULT[U]/DMACC instructions.  */
+  CONFLICT (DMULT, DMULT);
+  CONFLICT (DMULT, DMACC);
+  CONFLICT (DMACC, DMULT);
+  CONFLICT (DMACC, DMACC);
+
+  /* Errata 24 - MT{LO,HI} after [D]MACC */
+  CONFLICT (MACC, MTHILO);
+  CONFLICT (DMACC, MTHILO);
+
+  /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
+     instruction is executed immediately after a MACC or DMACC
+     instruction, the result of [either instruction] is incorrect."  */
+  CONFLICT (MACC, MULT);
+  CONFLICT (MACC, DMULT);
+  CONFLICT (DMACC, MULT);
+  CONFLICT (DMACC, DMULT);
+
+  /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
+     executed immediately after a DMULT, DMULTU, DIV, DIVU,
+     DDIV or DDIVU instruction, the result of the MACC or
+     DMACC instruction is incorrect.".  */
+  CONFLICT (DMULT, MACC);
+  CONFLICT (DMULT, DMACC);
+  CONFLICT (DIV, MACC);
+  CONFLICT (DIV, DMACC);
+
+#undef CONFLICT
+}
+
 /* This function is called once, at assembler startup time.  It should
    set up all the tables, etc. that the MD part of the assembler will need.  */
 
@@ -1134,6 +1403,13 @@ md_begin (void)
   int i = 0;
   int broken = 0;
 
+  if (mips_pic != NO_PIC)
+    {
+      if (g_switch_seen && g_switch_value != 0)
+	as_bad (_("-G may not be used in position-independent code"));
+      g_switch_value = 0;
+    }
+
   if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
     as_warn (_("Could not set architecture and machine"));
 
@@ -1157,6 +1433,11 @@ md_begin (void)
 	    {
 	      if (!validate_mips_insn (&mips_opcodes[i]))
 		broken = 1;
+	      if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
+		{
+		  create_insn (&nop_insn, mips_opcodes + i);
+		  nop_insn.fixed_p = 1;
+		}
 	    }
 	  ++i;
 	}
@@ -1184,6 +1465,11 @@ md_begin (void)
 		       mips16_opcodes[i].name, mips16_opcodes[i].args);
 	      broken = 1;
 	    }
+	  if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
+	    {
+	      create_insn (&mips16_nop_insn, mips16_opcodes + i);
+	      mips16_nop_insn.fixed_p = 1;
+	    }
 	  ++i;
 	}
       while (i < bfd_mips16_num_opcodes
@@ -1236,7 +1522,7 @@ md_begin (void)
 				       &zero_address_frag));
     }
 
-  mips_no_prev_insn (FALSE);
+  mips_no_prev_insn ();
 
   mips_gprmask = 0;
   mips_cprmask[0] = 0;
@@ -1247,15 +1533,15 @@ md_begin (void)
   /* set the default alignment for the text section (2**2) */
   record_alignment (text_section, 2);
 
-  if (USE_GLOBAL_POINTER_OPT)
-    bfd_set_gp_size (stdoutput, g_switch_value);
+  bfd_set_gp_size (stdoutput, g_switch_value);
 
   if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
     {
-      /* On a native system, sections must be aligned to 16 byte
-	 boundaries.  When configured for an embedded ELF target, we
-	 don't bother.  */
-      if (strcmp (TARGET_OS, "elf") != 0)
+      /* On a native system other than VxWorks, sections must be aligned
+	 to 16 byte boundaries.  When configured for an embedded ELF
+	 target, we don't bother.  */
+      if (strcmp (TARGET_OS, "elf") != 0
+	  && strcmp (TARGET_OS, "vxworks") != 0)
 	{
 	  (void) bfd_set_section_alignment (stdoutput, text_section, 4);
 	  (void) bfd_set_section_alignment (stdoutput, data_section, 4);
@@ -1343,6 +1629,9 @@ md_begin (void)
 
   if (! ECOFF_DEBUGGING)
     md_obj_begin ();
+
+  if (mips_fix_vr4120)
+    init_vr4120_conflicts ();
 }
 
 void
@@ -1405,14 +1694,18 @@ md_assemble (char *str)
 }
 
 /* Return true if the given relocation might need a matching %lo().
-   Note that R_MIPS_GOT16 relocations only need a matching %lo() when
-   applied to local symbols.  */
+   This is only "might" because SVR4 R_MIPS_GOT16 relocations only
+   need a matching %lo() when applied to local symbols.  */
 
 static inline bfd_boolean
 reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
 {
-  return (reloc == BFD_RELOC_HI16_S
-	  || reloc == BFD_RELOC_MIPS_GOT16);
+  return (HAVE_IN_PLACE_ADDENDS
+	  && (reloc == BFD_RELOC_HI16_S
+	      || reloc == BFD_RELOC_MIPS16_HI16_S
+	      /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
+		 all GOT16 relocations evaluate to "G".  */
+	      || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC)));
 }
 
 /* Return true if the given fixup is followed by a matching R_MIPS_LO16
@@ -1422,7 +1715,8 @@ static inline bfd_boolean
 fixup_has_matching_lo_p (fixS *fixp)
 {
   return (fixp->fx_next != NULL
-	  && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+	  && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
+	     || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
 	  && fixp->fx_addsy == fixp->fx_next->fx_addsy
 	  && fixp->fx_offset == fixp->fx_next->fx_offset);
 }
@@ -1431,7 +1725,7 @@ fixup_has_matching_lo_p (fixS *fixp)
    of register.  */
 
 static int
-insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
+insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
 	       enum mips_regclass class)
 {
   if (class == MIPS16_REG)
@@ -1456,38 +1750,33 @@ insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
 	 because there is no instruction that sets both $f0 and $f1
 	 and requires a delay.  */
       if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
-	  && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
+	  && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
 	      == (reg &~ (unsigned) 1)))
 	return 1;
       if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
-	  && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
+	  && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
 	      == (reg &~ (unsigned) 1)))
 	return 1;
     }
   else if (! mips_opts.mips16)
     {
       if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
-	  && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
+	  && EXTRACT_OPERAND (RS, *ip) == reg)
 	return 1;
       if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
-	  && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
+	  && EXTRACT_OPERAND (RT, *ip) == reg)
 	return 1;
     }
   else
     {
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
-	  && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
-				    & MIPS16OP_MASK_RX)]
-	      == reg))
+	  && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
 	return 1;
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
-	  && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
-				    & MIPS16OP_MASK_RY)]
-	      == reg))
+	  && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
 	return 1;
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
-	  && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
-				    & MIPS16OP_MASK_MOVE32Z)]
+	  && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
 	      == reg))
 	return 1;
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
@@ -1497,8 +1786,7 @@ insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
 	return 1;
       if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
-	  && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
-	      & MIPS16OP_MASK_REGR32) == reg)
+	  && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
 	return 1;
     }
 
@@ -1513,7 +1801,7 @@ reg_needs_delay (unsigned int reg)
 {
   unsigned long prev_pinfo;
 
-  prev_pinfo = prev_insn.insn_mo->pinfo;
+  prev_pinfo = history[0].insn_mo->pinfo;
   if (! mips_opts.noreorder
       && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
 	   && ! gpr_interlocks)
@@ -1524,13 +1812,33 @@ reg_needs_delay (unsigned int reg)
 	 delay the use of general register rt for one instruction.  */
       /* Itbl support may require additional care here.  */
       know (prev_pinfo & INSN_WRITE_GPR_T);
-      if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
+      if (reg == EXTRACT_OPERAND (RT, history[0]))
 	return 1;
     }
 
   return 0;
 }
 
+/* Move all labels in insn_labels to the current insertion point.  */
+
+static void
+mips_move_labels (void)
+{
+  struct insn_label_list *l;
+  valueT val;
+
+  for (l = insn_labels; l != NULL; l = l->next)
+    {
+      assert (S_GET_SEGMENT (l->label) == now_seg);
+      symbol_set_frag (l->label, frag_now);
+      val = (valueT) frag_now_fix ();
+      /* mips16 text labels are stored as odd.  */
+      if (mips_opts.mips16)
+	++val;
+      S_SET_VALUE (l->label, val);
+    }
+}
+
 /* Mark instruction labels in mips16 mode.  This permits the linker to
    handle them specially, such as generating jalx instructions when
    needed.  We also make them odd for the duration of the assembly, in
@@ -1606,323 +1914,308 @@ relax_end (void)
   mips_relax.sequence = 0;
 }
 
-/* Output an instruction.  IP is the instruction information.
-   ADDRESS_EXPR is an operand of the instruction to be used with
-   RELOC_TYPE.  */
+/* Classify an instruction according to the FIX_VR4120_* enumeration.
+   Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
+   by VR4120 errata.  */
+
+static unsigned int
+classify_vr4120_insn (const char *name)
+{
+  if (strncmp (name, "macc", 4) == 0)
+    return FIX_VR4120_MACC;
+  if (strncmp (name, "dmacc", 5) == 0)
+    return FIX_VR4120_DMACC;
+  if (strncmp (name, "mult", 4) == 0)
+    return FIX_VR4120_MULT;
+  if (strncmp (name, "dmult", 5) == 0)
+    return FIX_VR4120_DMULT;
+  if (strstr (name, "div"))
+    return FIX_VR4120_DIV;
+  if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
+    return FIX_VR4120_MTHILO;
+  return NUM_FIX_VR4120_CLASSES;
+}
 
-static void
-append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
-	     bfd_reloc_code_real_type *reloc_type)
+/* Return the number of instructions that must separate INSN1 and INSN2,
+   where INSN1 is the earlier instruction.  Return the worst-case value
+   for any INSN2 if INSN2 is null.  */
+
+static unsigned int
+insns_between (const struct mips_cl_insn *insn1,
+	       const struct mips_cl_insn *insn2)
 {
-  register unsigned long prev_pinfo, pinfo;
-  char *f;
-  fixS *fixp[3];
-  int nops = 0;
-  relax_stateT prev_insn_frag_type = 0;
-  bfd_boolean relaxed_branch = FALSE;
-  bfd_boolean force_new_frag = FALSE;
+  unsigned long pinfo1, pinfo2;
 
-  /* Mark instruction labels in mips16 mode.  */
-  mips16_mark_labels ();
+  /* This function needs to know which pinfo flags are set for INSN2
+     and which registers INSN2 uses.  The former is stored in PINFO2 and
+     the latter is tested via INSN2_USES_REG.  If INSN2 is null, PINFO2
+     will have every flag set and INSN2_USES_REG will always return true.  */
+  pinfo1 = insn1->insn_mo->pinfo;
+  pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
 
-  prev_pinfo = prev_insn.insn_mo->pinfo;
-  pinfo = ip->insn_mo->pinfo;
+#define INSN2_USES_REG(REG, CLASS) \
+   (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
 
-  if (mips_relax.sequence != 2
-      && (!mips_opts.noreorder || prev_nop_frag != NULL))
+  /* For most targets, write-after-read dependencies on the HI and LO
+     registers must be separated by at least two instructions.  */
+  if (!hilo_interlocks)
     {
-      int prev_prev_nop;
+      if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
+	return 2;
+      if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
+	return 2;
+    }
 
-      /* If the previous insn required any delay slots, see if we need
-	 to insert a NOP or two.  There are eight kinds of possible
-	 hazards, of which an instruction can have at most one type.
-	 (1) a load from memory delay
-	 (2) a load from a coprocessor delay
-	 (3) an unconditional branch delay
-	 (4) a conditional branch delay
-	 (5) a move to coprocessor register delay
-	 (6) a load coprocessor register from memory delay
-	 (7) a coprocessor condition code delay
-	 (8) a HI/LO special register delay
+  /* If we're working around r7000 errata, there must be two instructions
+     between an mfhi or mflo and any instruction that uses the result.  */
+  if (mips_7000_hilo_fix
+      && MF_HILO_INSN (pinfo1)
+      && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
+    return 2;
 
-	 There are a lot of optimizations we could do that we don't.
-	 In particular, we do not, in general, reorder instructions.
-	 If you use gcc with optimization, it will reorder
-	 instructions and generally do much more optimization then we
-	 do here; repeating all that work in the assembler would only
-	 benefit hand written assembly code, and does not seem worth
-	 it.  */
+  /* If working around VR4120 errata, check for combinations that need
+     a single intervening instruction.  */
+  if (mips_fix_vr4120)
+    {
+      unsigned int class1, class2;
 
-      /* This is how a NOP is emitted.  */
-#define emit_nop()					\
-  (mips_opts.mips16					\
-   ? md_number_to_chars (frag_more (2), 0x6500, 2)	\
-   : md_number_to_chars (frag_more (4), 0, 4))
-
-      /* The previous insn might require a delay slot, depending upon
-	 the contents of the current insn.  */
-      if (! mips_opts.mips16
-	  && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
-	       && ! gpr_interlocks)
-	      || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
-		  && ! cop_interlocks)))
-	{
-	  /* A load from a coprocessor or from memory.  All load
-	     delays delay the use of general register rt for one
-	     instruction.  */
-	  /* Itbl support may require additional care here.  */
-	  know (prev_pinfo & INSN_WRITE_GPR_T);
-	  if (mips_optimize == 0
-	      || insn_uses_reg (ip,
-				((prev_insn.insn_opcode >> OP_SH_RT)
-				 & OP_MASK_RT),
-				MIPS_GR_REG))
-	    ++nops;
-	}
-      else if (! mips_opts.mips16
-	       && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
-		    && ! cop_interlocks)
-		   || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
-		       && ! cop_mem_interlocks)))
-	{
-	  /* A generic coprocessor delay.  The previous instruction
-	     modified a coprocessor general or control register.  If
-	     it modified a control register, we need to avoid any
-	     coprocessor instruction (this is probably not always
-	     required, but it sometimes is).  If it modified a general
-	     register, we avoid using that register.
-
-	     This case is not handled very well.  There is no special
-	     knowledge of CP0 handling, and the coprocessors other
-	     than the floating point unit are not distinguished at
-	     all.  */
-          /* Itbl support may require additional care here. FIXME!
-             Need to modify this to include knowledge about
-             user specified delays!  */
-	  if (prev_pinfo & INSN_WRITE_FPR_T)
+      class1 = classify_vr4120_insn (insn1->insn_mo->name);
+      if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
+	{
+	  if (insn2 == NULL)
+	    return 1;
+	  class2 = classify_vr4120_insn (insn2->insn_mo->name);
+	  if (vr4120_conflicts[class1] & (1 << class2))
+	    return 1;
+	}
+    }
+
+  if (!mips_opts.mips16)
+    {
+      /* Check for GPR or coprocessor load delays.  All such delays
+	 are on the RT register.  */
+      /* Itbl support may require additional care here.  */
+      if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
+	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
+	{
+	  know (pinfo1 & INSN_WRITE_GPR_T);
+	  if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
+	    return 1;
+	}
+
+      /* Check for generic coprocessor hazards.
+
+	 This case is not handled very well.  There is no special
+	 knowledge of CP0 handling, and the coprocessors other than
+	 the floating point unit are not distinguished at all.  */
+      /* Itbl support may require additional care here. FIXME!
+	 Need to modify this to include knowledge about
+	 user specified delays!  */
+      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
+	       || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
+	{
+	  /* Handle cases where INSN1 writes to a known general coprocessor
+	     register.  There must be a one instruction delay before INSN2
+	     if INSN2 reads that register, otherwise no delay is needed.  */
+	  if (pinfo1 & INSN_WRITE_FPR_T)
 	    {
-	      if (mips_optimize == 0
-		  || insn_uses_reg (ip,
-				    ((prev_insn.insn_opcode >> OP_SH_FT)
-				     & OP_MASK_FT),
-				    MIPS_FP_REG))
-		++nops;
+	      if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
+		return 1;
 	    }
-	  else if (prev_pinfo & INSN_WRITE_FPR_S)
+	  else if (pinfo1 & INSN_WRITE_FPR_S)
 	    {
-	      if (mips_optimize == 0
-		  || insn_uses_reg (ip,
-				    ((prev_insn.insn_opcode >> OP_SH_FS)
-				     & OP_MASK_FS),
-				    MIPS_FP_REG))
-		++nops;
+	      if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
+		return 1;
 	    }
 	  else
 	    {
-	      /* We don't know exactly what the previous instruction
-		 does.  If the current instruction uses a coprocessor
-		 register, we must insert a NOP.  If previous
-		 instruction may set the condition codes, and the
-		 current instruction uses them, we must insert two
-		 NOPS.  */
-              /* Itbl support may require additional care here.  */
-	      if (mips_optimize == 0
-		  || ((prev_pinfo & INSN_WRITE_COND_CODE)
-		      && (pinfo & INSN_READ_COND_CODE)))
-		nops += 2;
-	      else if (pinfo & INSN_COP)
-		++nops;
+	      /* Read-after-write dependencies on the control registers
+		 require a two-instruction gap.  */
+	      if ((pinfo1 & INSN_WRITE_COND_CODE)
+		  && (pinfo2 & INSN_READ_COND_CODE))
+		return 2;
+
+	      /* We don't know exactly what INSN1 does.  If INSN2 is
+		 also a coprocessor instruction, assume there must be
+		 a one instruction gap.  */
+	      if (pinfo2 & INSN_COP)
+		return 1;
 	    }
 	}
-      else if (! mips_opts.mips16
-	       && (prev_pinfo & INSN_WRITE_COND_CODE)
-               && ! cop_interlocks)
-	{
-	  /* The previous instruction sets the coprocessor condition
-	     codes, but does not require a general coprocessor delay
-	     (this means it is a floating point comparison
-	     instruction).  If this instruction uses the condition
-	     codes, we need to insert a single NOP.  */
-	  /* Itbl support may require additional care here.  */
-	  if (mips_optimize == 0
-	      || (pinfo & INSN_READ_COND_CODE))
-	    ++nops;
-	}
-
-      /* If we're fixing up mfhi/mflo for the r7000 and the
-	 previous insn was an mfhi/mflo and the current insn
-	 reads the register that the mfhi/mflo wrote to, then
-	 insert two nops.  */
-
-      else if (mips_7000_hilo_fix
-	       && MF_HILO_INSN (prev_pinfo)
-	       && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
-				      & OP_MASK_RD),
-				 MIPS_GR_REG))
-	{
-	  nops += 2;
-	}
-
-      /* If we're fixing up mfhi/mflo for the r7000 and the
-	 2nd previous insn was an mfhi/mflo and the current insn
-	 reads the register that the mfhi/mflo wrote to, then
-	 insert one nop.  */
-
-      else if (mips_7000_hilo_fix
-	       && MF_HILO_INSN (prev_prev_insn.insn_opcode)
-	       && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
-                                       & OP_MASK_RD),
-                                    MIPS_GR_REG))
-
-	{
-	  ++nops;
-	}
-
-      else if (prev_pinfo & INSN_READ_LO)
-	{
-	  /* The previous instruction reads the LO register; if the
-	     current instruction writes to the LO register, we must
-	     insert two NOPS.  Some newer processors have interlocks.
-	     Also the tx39's multiply instructions can be executed
-             immediately after a read from HI/LO (without the delay),
-             though the tx39's divide insns still do require the
-	     delay.  */
-	  if (! (hilo_interlocks
-		 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
-	      && (mips_optimize == 0
-		  || (pinfo & INSN_WRITE_LO)))
-	    nops += 2;
-	  /* Most mips16 branch insns don't have a delay slot.
-	     If a read from LO is immediately followed by a branch
-	     to a write to LO we have a read followed by a write
-	     less than 2 insns away.  We assume the target of
-	     a branch might be a write to LO, and insert a nop
-	     between a read and an immediately following branch.  */
-	  else if (mips_opts.mips16
-		   && (mips_optimize == 0
-		       || (pinfo & MIPS16_INSN_BRANCH)))
-	    ++nops;
-	}
-      else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
-	{
-	  /* The previous instruction reads the HI register; if the
-	     current instruction writes to the HI register, we must
-	     insert a NOP.  Some newer processors have interlocks.
-	     Also the note tx39's multiply above.  */
-	  if (! (hilo_interlocks
-		 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
-	      && (mips_optimize == 0
-		  || (pinfo & INSN_WRITE_HI)))
-	    nops += 2;
-	  /* Most mips16 branch insns don't have a delay slot.
-	     If a read from HI is immediately followed by a branch
-	     to a write to HI we have a read followed by a write
-	     less than 2 insns away.  We assume the target of
-	     a branch might be a write to HI, and insert a nop
-	     between a read and an immediately following branch.  */
-	  else if (mips_opts.mips16
-		   && (mips_optimize == 0
-		       || (pinfo & MIPS16_INSN_BRANCH)))
-	    ++nops;
-	}
-
-      /* If the previous instruction was in a noreorder section, then
-         we don't want to insert the nop after all.  */
+
+      /* Check for read-after-write dependencies on the coprocessor
+	 control registers in cases where INSN1 does not need a general
+	 coprocessor delay.  This means that INSN1 is a floating point
+	 comparison instruction.  */
       /* Itbl support may require additional care here.  */
-      if (prev_insn_unreordered)
-	nops = 0;
-
-      /* There are two cases which require two intervening
-	 instructions: 1) setting the condition codes using a move to
-	 coprocessor instruction which requires a general coprocessor
-	 delay and then reading the condition codes 2) reading the HI
-	 or LO register and then writing to it (except on processors
-	 which have interlocks).  If we are not already emitting a NOP
-	 instruction, we must check for these cases compared to the
-	 instruction previous to the previous instruction.  */
-      if ((! mips_opts.mips16
-	   && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
-	   && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
-	   && (pinfo & INSN_READ_COND_CODE)
-	   && ! cop_interlocks)
-	  || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
-	      && (pinfo & INSN_WRITE_LO)
-	      && ! (hilo_interlocks
-		    || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
-	  || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
-	      && (pinfo & INSN_WRITE_HI)
-	      && ! (hilo_interlocks
-		    || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
-	prev_prev_nop = 1;
-      else
-	prev_prev_nop = 0;
+      else if (!cop_interlocks
+	       && (pinfo1 & INSN_WRITE_COND_CODE)
+	       && (pinfo2 & INSN_READ_COND_CODE))
+	return 1;
+    }
 
-      if (prev_prev_insn_unreordered)
-	prev_prev_nop = 0;
+#undef INSN2_USES_REG
 
-      if (prev_prev_nop && nops == 0)
-	++nops;
+  return 0;
+}
 
-      if (mips_fix_vr4120 && prev_insn.insn_mo->name)
-	{
-	  /* We're out of bits in pinfo, so we must resort to string
-	     ops here.  Shortcuts are selected based on opcodes being
-	     limited to the VR4120 instruction set.  */
-	  int min_nops = 0;
-	  const char *pn = prev_insn.insn_mo->name;
-	  const char *tn = ip->insn_mo->name;
-	  if (strncmp(pn, "macc", 4) == 0
-	      || strncmp(pn, "dmacc", 5) == 0)
-	    {
-	      /* Errata 21 - [D]DIV[U] after [D]MACC */
-	      if (strstr (tn, "div"))
-		{
-		  min_nops = 1;
-		}
+/* Return the number of nops that would be needed to work around the
+   VR4130 mflo/mfhi errata if instruction INSN immediately followed
+   the MAX_VR4130_NOPS instructions described by HISTORY.  */
 
-	      /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
-	      if (pn[0] == 'd' /* dmacc */
-		  && (strncmp(tn, "dmult", 5) == 0
-		      || strncmp(tn, "dmacc", 5) == 0))
-		{
-		  min_nops = 1;
-		}
+static int
+nops_for_vr4130 (const struct mips_cl_insn *history,
+		 const struct mips_cl_insn *insn)
+{
+  int i, j, reg;
 
-	      /* Errata 24 - MT{LO,HI} after [D]MACC */
-	      if (strcmp (tn, "mtlo") == 0
-		  || strcmp (tn, "mthi") == 0)
-		{
-		  min_nops = 1;
-		}
+  /* Check if the instruction writes to HI or LO.  MTHI and MTLO
+     are not affected by the errata.  */
+  if (insn != 0
+      && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
+	  || strcmp (insn->insn_mo->name, "mtlo") == 0
+	  || strcmp (insn->insn_mo->name, "mthi") == 0))
+    return 0;
 
-	    }
-	  else if (strncmp(pn, "dmult", 5) == 0
-		   && (strncmp(tn, "dmult", 5) == 0
-		       || strncmp(tn, "dmacc", 5) == 0))
-	    {
-	      /* Here is the rest of errata 23.  */
-	      min_nops = 1;
-	    }
-	  if (nops < min_nops)
-	    nops = min_nops;
-	}
+  /* Search for the first MFLO or MFHI.  */
+  for (i = 0; i < MAX_VR4130_NOPS; i++)
+    if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
+      {
+	/* Extract the destination register.  */
+	if (mips_opts.mips16)
+	  reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
+	else
+	  reg = EXTRACT_OPERAND (RD, history[i]);
+
+	/* No nops are needed if INSN reads that register.  */
+	if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
+	  return 0;
+
+	/* ...or if any of the intervening instructions do.  */
+	for (j = 0; j < i; j++)
+	  if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
+	    return 0;
+
+	return MAX_VR4130_NOPS - i;
+      }
+  return 0;
+}
+
+/* Return the number of nops that would be needed if instruction INSN
+   immediately followed the MAX_NOPS instructions given by HISTORY,
+   where HISTORY[0] is the most recent instruction.  If INSN is null,
+   return the worse-case number of nops for any instruction.  */
+
+static int
+nops_for_insn (const struct mips_cl_insn *history,
+	       const struct mips_cl_insn *insn)
+{
+  int i, nops, tmp_nops;
+
+  nops = 0;
+  for (i = 0; i < MAX_DELAY_NOPS; i++)
+    if (!history[i].noreorder_p)
+      {
+	tmp_nops = insns_between (history + i, insn) - i;
+	if (tmp_nops > nops)
+	  nops = tmp_nops;
+      }
+
+  if (mips_fix_vr4130)
+    {
+      tmp_nops = nops_for_vr4130 (history, insn);
+      if (tmp_nops > nops)
+	nops = tmp_nops;
+    }
+
+  return nops;
+}
+
+/* The variable arguments provide NUM_INSNS extra instructions that
+   might be added to HISTORY.  Return the largest number of nops that
+   would be needed after the extended sequence.  */
+
+static int
+nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
+{
+  va_list args;
+  struct mips_cl_insn buffer[MAX_NOPS];
+  struct mips_cl_insn *cursor;
+  int nops;
+
+  va_start (args, history);
+  cursor = buffer + num_insns;
+  memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
+  while (cursor > buffer)
+    *--cursor = *va_arg (args, const struct mips_cl_insn *);
+
+  nops = nops_for_insn (buffer, NULL);
+  va_end (args);
+  return nops;
+}
+
+/* Like nops_for_insn, but if INSN is a branch, take into account the
+   worst-case delay for the branch target.  */
 
-      /* If we are being given a nop instruction, don't bother with
-	 one of the nops we would otherwise output.  This will only
-	 happen when a nop instruction is used with mips_optimize set
-	 to 0.  */
-      if (nops > 0
-	  && ! mips_opts.noreorder
-	  && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
-	--nops;
+static int
+nops_for_insn_or_target (const struct mips_cl_insn *history,
+			 const struct mips_cl_insn *insn)
+{
+  int nops, tmp_nops;
 
-      /* Now emit the right number of NOP instructions.  */
-      if (nops > 0 && ! mips_opts.noreorder)
+  nops = nops_for_insn (history, insn);
+  if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
+			      | INSN_COND_BRANCH_DELAY
+			      | INSN_COND_BRANCH_LIKELY))
+    {
+      tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
+      if (tmp_nops > nops)
+	nops = tmp_nops;
+    }
+  else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
+    {
+      tmp_nops = nops_for_sequence (1, history, insn);
+      if (tmp_nops > nops)
+	nops = tmp_nops;
+    }
+  return nops;
+}
+
+/* Output an instruction.  IP is the instruction information.
+   ADDRESS_EXPR is an operand of the instruction to be used with
+   RELOC_TYPE.  */
+
+static void
+append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
+	     bfd_reloc_code_real_type *reloc_type)
+{
+  register unsigned long prev_pinfo, pinfo;
+  relax_stateT prev_insn_frag_type = 0;
+  bfd_boolean relaxed_branch = FALSE;
+
+  /* Mark instruction labels in mips16 mode.  */
+  mips16_mark_labels ();
+
+  prev_pinfo = history[0].insn_mo->pinfo;
+  pinfo = ip->insn_mo->pinfo;
+
+  if (mips_relax.sequence != 2 && !mips_opts.noreorder)
+    {
+      /* There are a lot of optimizations we could do that we don't.
+	 In particular, we do not, in general, reorder instructions.
+	 If you use gcc with optimization, it will reorder
+	 instructions and generally do much more optimization then we
+	 do here; repeating all that work in the assembler would only
+	 benefit hand written assembly code, and does not seem worth
+	 it.  */
+      int nops = (mips_optimize == 0
+		  ? nops_for_insn (history, NULL)
+		  : nops_for_insn_or_target (history, ip));
+      if (nops > 0)
 	{
 	  fragS *old_frag;
 	  unsigned long old_frag_offset;
 	  int i;
-	  struct insn_label_list *l;
 
 	  old_frag = frag_now;
 	  old_frag_offset = frag_now_fix ();
@@ -1944,66 +2237,54 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      frag_grow (40);
 	    }
 
-	  for (l = insn_labels; l != NULL; l = l->next)
-	    {
-	      valueT val;
-
-	      assert (S_GET_SEGMENT (l->label) == now_seg);
-	      symbol_set_frag (l->label, frag_now);
-	      val = (valueT) frag_now_fix ();
-	      /* mips16 text labels are stored as odd.  */
-	      if (mips_opts.mips16)
-		++val;
-	      S_SET_VALUE (l->label, val);
-	    }
+	  mips_move_labels ();
 
 #ifndef NO_ECOFF_DEBUGGING
 	  if (ECOFF_DEBUGGING)
 	    ecoff_fix_loc (old_frag, old_frag_offset);
 #endif
 	}
-      else if (prev_nop_frag != NULL)
-	{
-	  /* We have a frag holding nops we may be able to remove.  If
-             we don't need any nops, we can decrease the size of
-             prev_nop_frag by the size of one instruction.  If we do
-             need some nops, we count them in prev_nops_required.  */
-	  if (prev_nop_frag_since == 0)
-	    {
-	      if (nops == 0)
-		{
-		  prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
-		  --prev_nop_frag_holds;
-		}
-	      else
-		prev_nop_frag_required += nops;
-	    }
-	  else
-	    {
-	      if (prev_prev_nop == 0)
-		{
-		  prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
-		  --prev_nop_frag_holds;
-		}
-	      else
-		++prev_nop_frag_required;
-	    }
-
-	  if (prev_nop_frag_holds <= prev_nop_frag_required)
-	    prev_nop_frag = NULL;
+    }
+  else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
+    {
+      /* Work out how many nops in prev_nop_frag are needed by IP.  */
+      int nops = nops_for_insn_or_target (history, ip);
+      assert (nops <= prev_nop_frag_holds);
 
-	  ++prev_nop_frag_since;
+      /* Enforce NOPS as a minimum.  */
+      if (nops > prev_nop_frag_required)
+	prev_nop_frag_required = nops;
 
-	  /* Sanity check: by the time we reach the second instruction
-             after prev_nop_frag, we should have used up all the nops
-             one way or another.  */
-	  assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
+      if (prev_nop_frag_holds == prev_nop_frag_required)
+	{
+	  /* Settle for the current number of nops.  Update the history
+	     accordingly (for the benefit of any future .set reorder code).  */
+	  prev_nop_frag = NULL;
+	  insert_into_history (prev_nop_frag_since,
+			       prev_nop_frag_holds, NOP_INSN);
+	}
+      else
+	{
+	  /* Allow this instruction to replace one of the nops that was
+	     tentatively added to prev_nop_frag.  */
+	  prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
+	  prev_nop_frag_holds--;
+	  prev_nop_frag_since++;
 	}
     }
 
+#ifdef OBJ_ELF
+  /* The value passed to dwarf2_emit_insn is the distance between
+     the beginning of the current instruction and the address that
+     should be recorded in the debug tables.  For MIPS16 debug info
+     we want to use ISA-encoded addresses, so we pass -1 for an
+     address higher by one than the current.  */
+  dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
+#endif
+
   /* Record the frag type before frag_var.  */
-  if (prev_insn_frag)
-    prev_insn_frag_type = prev_insn_frag->fr_type;
+  if (history[0].frag)
+    prev_insn_frag_type = history[0].frag->fr_type;
 
   if (address_expr
       && *reloc_type == BFD_RELOC_16_PCREL_S2
@@ -2018,42 +2299,41 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
       && !mips_opts.mips16)
     {
       relaxed_branch = TRUE;
-      f = frag_var (rs_machine_dependent,
-		    relaxed_branch_length
-		    (NULL, NULL,
-		     (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
-		     : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
-		    RELAX_BRANCH_ENCODE
-		    (pinfo & INSN_UNCOND_BRANCH_DELAY,
-		     pinfo & INSN_COND_BRANCH_LIKELY,
-		     pinfo & INSN_WRITE_GPR_31,
-		     0),
-		    address_expr->X_add_symbol,
-		    address_expr->X_add_number,
-		    0);
+      add_relaxed_insn (ip, (relaxed_branch_length
+			     (NULL, NULL,
+			      (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
+			      : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
+			      : 0)), 4,
+			RELAX_BRANCH_ENCODE
+			(pinfo & INSN_UNCOND_BRANCH_DELAY,
+			 pinfo & INSN_COND_BRANCH_LIKELY,
+			 pinfo & INSN_WRITE_GPR_31,
+			 0),
+			address_expr->X_add_symbol,
+			address_expr->X_add_number);
       *reloc_type = BFD_RELOC_UNUSED;
     }
   else if (*reloc_type > BFD_RELOC_UNUSED)
     {
       /* We need to set up a variant frag.  */
       assert (mips_opts.mips16 && address_expr != NULL);
-      f = frag_var (rs_machine_dependent, 4, 0,
-		    RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
-					 mips16_small, mips16_ext,
-					 (prev_pinfo
-					  & INSN_UNCOND_BRANCH_DELAY),
-					 (*prev_insn_reloc_type
-					  == BFD_RELOC_MIPS16_JMP)),
-		    make_expr_symbol (address_expr), 0, NULL);
+      add_relaxed_insn (ip, 4, 0,
+			RELAX_MIPS16_ENCODE
+			(*reloc_type - BFD_RELOC_UNUSED,
+			 mips16_small, mips16_ext,
+			 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
+			 history[0].mips16_absolute_jump_p),
+			make_expr_symbol (address_expr), 0);
     }
   else if (mips_opts.mips16
 	   && ! ip->use_extend
 	   && *reloc_type != BFD_RELOC_MIPS16_JMP)
     {
-      /* Make sure there is enough room to swap this instruction with
-         a following jump instruction.  */
-      frag_grow (6);
-      f = frag_more (2);
+      if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
+	/* Make sure there is enough room to swap this instruction with
+	   a following jump instruction.  */
+	frag_grow (6);
+      add_fixed_insn (ip);
     }
   else
     {
@@ -2077,15 +2357,19 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
       if (mips_relax.sequence != 1)
 	mips_macro_warning.sizes[1] += 4;
 
-      f = frag_more (4);
+      if (mips_opts.mips16)
+	{
+	  ip->fixed_p = 1;
+	  ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
+	}
+      add_fixed_insn (ip);
     }
 
-  fixp[0] = fixp[1] = fixp[2] = NULL;
-  if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
+  if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
     {
       if (address_expr->X_op == O_constant)
 	{
-	  valueT tmp;
+	  unsigned int tmp;
 
 	  switch (*reloc_type)
 	    {
@@ -2094,26 +2378,25 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      break;
 
 	    case BFD_RELOC_MIPS_HIGHEST:
-	      tmp = (address_expr->X_add_number
-		     + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
-	      tmp >>= 16;
-	      ip->insn_opcode |= (tmp >> 16) & 0xffff;
+	      tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
+	      ip->insn_opcode |= tmp & 0xffff;
 	      break;
 
 	    case BFD_RELOC_MIPS_HIGHER:
-	      tmp = (address_expr->X_add_number + 0x80008000) >> 16;
-	      ip->insn_opcode |= (tmp >> 16) & 0xffff;
+	      tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
+	      ip->insn_opcode |= tmp & 0xffff;
 	      break;
 
 	    case BFD_RELOC_HI16_S:
-	      ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
-				  >> 16) & 0xffff;
+	      tmp = (address_expr->X_add_number + 0x8000) >> 16;
+	      ip->insn_opcode |= tmp & 0xffff;
 	      break;
 
 	    case BFD_RELOC_HI16:
 	      ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
 	      break;
 
+	    case BFD_RELOC_UNUSED:
 	    case BFD_RELOC_LO16:
 	    case BFD_RELOC_MIPS_GOT_DISP:
 	      ip->insn_opcode |= address_expr->X_add_number & 0xffff;
@@ -2123,9 +2406,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      if ((address_expr->X_add_number & 3) != 0)
 		as_bad (_("jump to misaligned address (0x%lx)"),
 			(unsigned long) address_expr->X_add_number);
-	      if (address_expr->X_add_number & ~0xfffffff)
-		as_bad (_("jump address range overflow (0x%lx)"),
-			(unsigned long) address_expr->X_add_number);
 	      ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
 	      break;
 
@@ -2133,9 +2413,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      if ((address_expr->X_add_number & 3) != 0)
 		as_bad (_("jump to misaligned address (0x%lx)"),
 			(unsigned long) address_expr->X_add_number);
-	      if (address_expr->X_add_number & ~0xfffffff)
-		as_bad (_("jump address range overflow (0x%lx)"),
-			(unsigned long) address_expr->X_add_number);
 	      ip->insn_opcode |=
 		(((address_expr->X_add_number & 0x7c0000) << 3)
 		 | ((address_expr->X_add_number & 0xf800000) >> 7)
@@ -2143,13 +2420,22 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      break;
 
 	    case BFD_RELOC_16_PCREL_S2:
-	      goto need_reloc;
+	      if ((address_expr->X_add_number & 3) != 0)
+		as_bad (_("branch to misaligned address (0x%lx)"),
+			(unsigned long) address_expr->X_add_number);
+	      if (mips_relax_branch)
+		goto need_reloc;
+	      if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
+		as_bad (_("branch address range overflow (0x%lx)"),
+			(unsigned long) address_expr->X_add_number);
+	      ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
+	      break;
 
 	    default:
 	      internalError ();
 	    }
 	}
-      else
+      else if (*reloc_type < BFD_RELOC_UNUSED)
 	need_reloc:
 	{
 	  reloc_howto_type *howto;
@@ -2162,11 +2448,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      break;
 
 	  howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
-	  fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
-				 bfd_get_reloc_size(howto),
-				 address_expr,
-				 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
-				 reloc_type[0]);
+	  ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
+				     bfd_get_reloc_size (howto),
+				     address_expr,
+				     reloc_type[0] == BFD_RELOC_16_PCREL_S2,
+				     reloc_type[0]);
 
 	  /* These relocations can have an addend that won't fit in
 	     4 octets for 64bit assembly.  */
@@ -2187,13 +2473,16 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		  || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
 		  || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
 		  || reloc_type[0] == BFD_RELOC_MIPS_REL16
-		  || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
-	    fixp[0]->fx_no_overflow = 1;
+		  || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
+		  || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
+		  || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
+		  || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
+	    ip->fixp[0]->fx_no_overflow = 1;
 
 	  if (mips_relax.sequence)
 	    {
 	      if (mips_relax.first_fixup == 0)
-		mips_relax.first_fixup = fixp[0];
+		mips_relax.first_fixup = ip->fixp[0];
 	    }
 	  else if (reloc_needs_lo_p (*reloc_type))
 	    {
@@ -2209,7 +2498,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		  hi_fixup->next = mips_hi_fixup_list;
 		  mips_hi_fixup_list = hi_fixup;
 		}
-	      hi_fixup->fixp = fixp[0];
+	      hi_fixup->fixp = ip->fixp[0];
 	      hi_fixup->seg = now_seg;
 	    }
 
@@ -2221,64 +2510,37 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	  for (i = 1; i < 3; i++)
 	    if (reloc_type[i] != BFD_RELOC_UNUSED)
 	      {
-		address_expr->X_op = O_absent;
-		address_expr->X_add_symbol = 0;
-		address_expr->X_add_number = 0;
-
-		fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
-				       fixp[0]->fx_size, address_expr,
+		ip->fixp[i] = fix_new (ip->frag, ip->where,
+				       ip->fixp[0]->fx_size, NULL, 0,
 				       FALSE, reloc_type[i]);
-	      }
-	}
-    }
 
-  if (! mips_opts.mips16)
-    {
-      md_number_to_chars (f, ip->insn_opcode, 4);
-#ifdef OBJ_ELF
-      dwarf2_emit_insn (4);
-#endif
-    }
-  else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
-    {
-      md_number_to_chars (f, ip->insn_opcode >> 16, 2);
-      md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
-#ifdef OBJ_ELF
-      dwarf2_emit_insn (4);
-#endif
-    }
-  else
-    {
-      if (ip->use_extend)
-	{
-	  md_number_to_chars (f, 0xf000 | ip->extend, 2);
-	  f += 2;
+		/* Use fx_tcbit to mark compound relocs.  */
+		ip->fixp[0]->fx_tcbit = 1;
+		ip->fixp[i]->fx_tcbit = 1;
+	      }
 	}
-      md_number_to_chars (f, ip->insn_opcode, 2);
-#ifdef OBJ_ELF
-      dwarf2_emit_insn (ip->use_extend ? 4 : 2);
-#endif
     }
+  install_insn (ip);
 
   /* Update the register mask information.  */
   if (! mips_opts.mips16)
     {
       if (pinfo & INSN_WRITE_GPR_D)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
+	mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
       if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
+	mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
       if (pinfo & INSN_READ_GPR_S)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
+	mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
       if (pinfo & INSN_WRITE_GPR_31)
 	mips_gprmask |= 1 << RA;
       if (pinfo & INSN_WRITE_FPR_D)
-	mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
+	mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
       if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
-	mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
+	mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
       if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
-	mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
+	mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
       if ((pinfo & INSN_READ_FPR_R) != 0)
-	mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
+	mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
       if (pinfo & INSN_COP)
 	{
 	  /* We don't keep enough information to sort these cases out.
@@ -2292,14 +2554,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
   else
     {
       if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
-	mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
-			      & MIPS16OP_MASK_RX);
+	mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
       if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
-	mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
-			      & MIPS16OP_MASK_RY);
+	mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
       if (pinfo & MIPS16_INSN_WRITE_Z)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
-			      & MIPS16OP_MASK_RZ);
+	mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
       if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
 	mips_gprmask |= 1 << TREG;
       if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
@@ -2309,11 +2568,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
       if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
 	mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
       if (pinfo & MIPS16_INSN_READ_Z)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
-			      & MIPS16OP_MASK_MOVE32Z);
+	mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
       if (pinfo & MIPS16_INSN_READ_GPR_X)
-	mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
-			      & MIPS16OP_MASK_REGR32);
+	mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
     }
 
   if (mips_relax.sequence != 2 && !mips_opts.noreorder)
@@ -2330,15 +2587,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      /* If we have seen .set volatile or .set nomove, don't
 		 optimize.  */
 	      || mips_opts.nomove != 0
-	      /* If we had to emit any NOP instructions, then we
-		 already know we can not swap.  */
-	      || nops != 0
-	      /* If we don't even know the previous insn, we can not
-		 swap.  */
-	      || ! prev_insn_valid
-	      /* If the previous insn is already in a branch delay
-		 slot, then we can not swap.  */
-	      || prev_insn_is_delay_slot
+	      /* We can't swap if the previous instruction's position
+		 is fixed.  */
+	      || history[0].fixed_p
 	      /* If the previous previous insn was in a .set
 		 noreorder, we can't swap.  Actually, the MIPS
 		 assembler will swap in this situation.  However, gcc
@@ -2350,12 +2601,8 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		   bne	$4,$0,foo
 		 in which we can not swap the bne and INSN.  If gcc is
 		 not configured -with-gnu-as, it does not output the
-		 .set pseudo-ops.  We don't have to check
-		 prev_insn_unreordered, because prev_insn_valid will
-		 be 0 in that case.  We don't want to use
-		 prev_prev_insn_valid, because we do want to be able
-		 to swap at the start of a function.  */
-	      || prev_prev_insn_unreordered
+		 .set pseudo-ops.  */
+	      || history[1].noreorder_p
 	      /* If the branch is itself the target of a branch, we
 		 can not swap.  We cheat on this; all we check for is
 		 whether there is a label on this instruction.  If
@@ -2368,44 +2615,12 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		 frags for different purposes.  */
 	      || (! mips_opts.mips16
 		  && prev_insn_frag_type == rs_machine_dependent)
-	      /* If the branch reads the condition codes, we don't
-		 even try to swap, because in the sequence
-		   ctc1 $X,$31
-		   INSN
-		   INSN
-		   bc1t LABEL
-		 we can not swap, and I don't feel like handling that
-		 case.  */
-	      || (! mips_opts.mips16
-		  && (pinfo & INSN_READ_COND_CODE)
-		  && ! cop_interlocks)
-	      /* We can not swap with an instruction that requires a
-		 delay slot, because the target of the branch might
-		 interfere with that instruction.  */
-	      || (! mips_opts.mips16
-		  && (prev_pinfo
-              /* Itbl support may require additional care here.  */
-		      & (INSN_LOAD_COPROC_DELAY
-			 | INSN_COPROC_MOVE_DELAY
-			 | INSN_WRITE_COND_CODE))
-		  && ! cop_interlocks)
-	      || (! (hilo_interlocks
-		     || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
-		  && (prev_pinfo
-		      & (INSN_READ_LO
-			 | INSN_READ_HI)))
-	      || (! mips_opts.mips16
-		  && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
-		  && ! gpr_interlocks)
-	      || (! mips_opts.mips16
-                  /* Itbl support may require additional care here.  */
-		  && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
-		  && ! cop_mem_interlocks)
-	      /* We can not swap with a branch instruction.  */
-	      || (prev_pinfo
-		  & (INSN_UNCOND_BRANCH_DELAY
-		     | INSN_COND_BRANCH_DELAY
-		     | INSN_COND_BRANCH_LIKELY))
+	      /* Check for conflicts between the branch and the instructions
+		 before the candidate delay slot.  */
+	      || nops_for_insn (history + 1, ip) > 0
+	      /* Check for conflicts between the swapped sequence and the
+		 target of the branch.  */
+	      || nops_for_sequence (2, history + 1, ip, history) > 0
 	      /* We do not swap with a trap instruction, since it
 		 complicates trap handlers to have the trap
 		 instruction be in a delay slot.  */
@@ -2414,43 +2629,33 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 		 instruction sets, we can not swap.  */
 	      || (! mips_opts.mips16
 		  && (prev_pinfo & INSN_WRITE_GPR_T)
-		  && insn_uses_reg (ip,
-				    ((prev_insn.insn_opcode >> OP_SH_RT)
-				     & OP_MASK_RT),
+		  && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
 				    MIPS_GR_REG))
 	      || (! mips_opts.mips16
 		  && (prev_pinfo & INSN_WRITE_GPR_D)
-		  && insn_uses_reg (ip,
-				    ((prev_insn.insn_opcode >> OP_SH_RD)
-				     & OP_MASK_RD),
+		  && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
 				    MIPS_GR_REG))
 	      || (mips_opts.mips16
 		  && (((prev_pinfo & MIPS16_INSN_WRITE_X)
-		       && insn_uses_reg (ip,
-					 ((prev_insn.insn_opcode
-					   >> MIPS16OP_SH_RX)
-					  & MIPS16OP_MASK_RX),
-					 MIPS16_REG))
+		       && (insn_uses_reg
+			   (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
+			    MIPS16_REG)))
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
-			  && insn_uses_reg (ip,
-					    ((prev_insn.insn_opcode
-					      >> MIPS16OP_SH_RY)
-					     & MIPS16OP_MASK_RY),
-					    MIPS16_REG))
+			  && (insn_uses_reg
+			      (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
+			       MIPS16_REG)))
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
-			  && insn_uses_reg (ip,
-					    ((prev_insn.insn_opcode
-					      >> MIPS16OP_SH_RZ)
-					     & MIPS16OP_MASK_RZ),
-					    MIPS16_REG))
+			  && (insn_uses_reg
+			      (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
+			       MIPS16_REG)))
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_T)
 			  && insn_uses_reg (ip, TREG, MIPS_GR_REG))
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_31)
 			  && insn_uses_reg (ip, RA, MIPS_GR_REG))
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
 			  && insn_uses_reg (ip,
-					    MIPS16OP_EXTRACT_REG32R (prev_insn.
-								     insn_opcode),
+					    MIPS16OP_EXTRACT_REG32R
+					      (history[0].insn_opcode),
 					    MIPS_GR_REG))))
 	      /* If the branch writes a register that the previous
 		 instruction sets, we can not swap (we know that
@@ -2458,61 +2663,37 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	      || (! mips_opts.mips16
 		  && (prev_pinfo & INSN_WRITE_GPR_T)
 		  && (((pinfo & INSN_WRITE_GPR_D)
-		       && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
-			   == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
+		       && (EXTRACT_OPERAND (RT, history[0])
+			   == EXTRACT_OPERAND (RD, *ip)))
 		      || ((pinfo & INSN_WRITE_GPR_31)
-			  && (((prev_insn.insn_opcode >> OP_SH_RT)
-			       & OP_MASK_RT)
-			      == RA))))
+			  && EXTRACT_OPERAND (RT, history[0]) == RA)))
 	      || (! mips_opts.mips16
 		  && (prev_pinfo & INSN_WRITE_GPR_D)
 		  && (((pinfo & INSN_WRITE_GPR_D)
-		       && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
-			   == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
+		       && (EXTRACT_OPERAND (RD, history[0])
+			   == EXTRACT_OPERAND (RD, *ip)))
 		      || ((pinfo & INSN_WRITE_GPR_31)
-			  && (((prev_insn.insn_opcode >> OP_SH_RD)
-			       & OP_MASK_RD)
-			      == RA))))
+			  && EXTRACT_OPERAND (RD, history[0]) == RA)))
 	      || (mips_opts.mips16
 		  && (pinfo & MIPS16_INSN_WRITE_31)
 		  && ((prev_pinfo & MIPS16_INSN_WRITE_31)
 		      || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
-			  && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
+			  && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
 			      == RA))))
 	      /* If the branch writes a register that the previous
 		 instruction reads, we can not swap (we know that
 		 branches only write to RD or to $31).  */
 	      || (! mips_opts.mips16
 		  && (pinfo & INSN_WRITE_GPR_D)
-		  && insn_uses_reg (&prev_insn,
-				    ((ip->insn_opcode >> OP_SH_RD)
-				     & OP_MASK_RD),
+		  && insn_uses_reg (&history[0],
+				    EXTRACT_OPERAND (RD, *ip),
 				    MIPS_GR_REG))
 	      || (! mips_opts.mips16
 		  && (pinfo & INSN_WRITE_GPR_31)
-		  && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
+		  && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
 	      || (mips_opts.mips16
 		  && (pinfo & MIPS16_INSN_WRITE_31)
-		  && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
-	      /* If we are generating embedded PIC code, the branch
-		 might be expanded into a sequence which uses $at, so
-		 we can't swap with an instruction which reads it.  */
-	      || (mips_pic == EMBEDDED_PIC
-		  && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
-	      /* If the previous previous instruction has a load
-		 delay, and sets a register that the branch reads, we
-		 can not swap.  */
-	      || (! mips_opts.mips16
-              /* Itbl support may require additional care here.  */
-		  && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
-		       && ! cop_interlocks)
-		      || ((prev_prev_insn.insn_mo->pinfo
-			   & INSN_LOAD_MEMORY_DELAY)
-			  && ! gpr_interlocks))
-		  && insn_uses_reg (ip,
-				    ((prev_prev_insn.insn_opcode >> OP_SH_RT)
-				     & OP_MASK_RT),
-				    MIPS_GR_REG))
+		  && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
 	      /* If one instruction sets a condition code and the
                  other one uses a condition code, we can not swap.  */
 	      || ((pinfo & INSN_READ_COND_CODE)
@@ -2523,173 +2704,75 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
                  swap.  */
 	      || (mips_opts.mips16
 		  && (prev_pinfo & MIPS16_INSN_READ_PC))
-	      /* If the previous instruction was extended, we can not
-                 swap.  */
-	      || (mips_opts.mips16 && prev_insn_extended)
 	      /* If the previous instruction had a fixup in mips16
                  mode, we can not swap.  This normally means that the
                  previous instruction was a 4 byte branch anyhow.  */
-	      || (mips_opts.mips16 && prev_insn_fixp[0])
+	      || (mips_opts.mips16 && history[0].fixp[0])
 	      /* If the previous instruction is a sync, sync.l, or
 		 sync.p, we can not swap.  */
 	      || (prev_pinfo & INSN_SYNC))
 	    {
-	      /* We could do even better for unconditional branches to
-		 portions of this object file; we could pick up the
-		 instruction at the destination, put it in the delay
-		 slot, and bump the destination address.  */
-	      emit_nop ();
-	      /* Update the previous insn information.  */
-	      prev_prev_insn = *ip;
-	      prev_insn.insn_mo = &dummy_opcode;
+	      if (mips_opts.mips16
+		  && (pinfo & INSN_UNCOND_BRANCH_DELAY)
+		  && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
+		  && (mips_opts.isa == ISA_MIPS32
+		      || mips_opts.isa == ISA_MIPS32R2
+		      || mips_opts.isa == ISA_MIPS64
+		      || mips_opts.isa == ISA_MIPS64R2))
+		{
+		  /* Convert MIPS16 jr/jalr into a "compact" jump.  */
+		  ip->insn_opcode |= 0x0080;
+		  install_insn (ip);
+		  insert_into_history (0, 1, ip);
+		} 
+	      else
+		{
+		  /* We could do even better for unconditional branches to
+		     portions of this object file; we could pick up the
+		     instruction at the destination, put it in the delay
+		     slot, and bump the destination address.  */
+		  insert_into_history (0, 1, ip);
+		  emit_nop ();
+		}
+		
+	      if (mips_relax.sequence)
+		mips_relax.sizes[mips_relax.sequence - 1] += 4;
 	    }
 	  else
 	    {
 	      /* It looks like we can actually do the swap.  */
-	      if (! mips_opts.mips16)
+	      struct mips_cl_insn delay = history[0];
+	      if (mips_opts.mips16)
 		{
-		  char *prev_f;
-		  char temp[4];
-
-		  prev_f = prev_insn_frag->fr_literal + prev_insn_where;
-		  if (!relaxed_branch)
-		    {
-		      /* If this is not a relaxed branch, then just
-			 swap the instructions.  */
-		      memcpy (temp, prev_f, 4);
-		      memcpy (prev_f, f, 4);
-		      memcpy (f, temp, 4);
-		    }
-		  else
-		    {
-		      /* If this is a relaxed branch, then we move the
-			 instruction to be placed in the delay slot to
-			 the current frag, shrinking the fixed part of
-			 the originating frag.  If the branch occupies
-			 the tail of the latter, we move it backwards,
-			 into the space freed by the moved instruction.  */
-		      f = frag_more (4);
-		      memcpy (f, prev_f, 4);
-		      prev_insn_frag->fr_fix -= 4;
-		      if (prev_insn_frag->fr_type == rs_machine_dependent)
-			memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
-		    }
-
-		  if (prev_insn_fixp[0])
-		    {
-		      prev_insn_fixp[0]->fx_frag = frag_now;
-		      prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
-		    }
-		  if (prev_insn_fixp[1])
-		    {
-		      prev_insn_fixp[1]->fx_frag = frag_now;
-		      prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
-		    }
-		  if (prev_insn_fixp[2])
-		    {
-		      prev_insn_fixp[2]->fx_frag = frag_now;
-		      prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
-		    }
-		  if (prev_insn_fixp[0] && HAVE_NEWABI
-		      && prev_insn_frag != frag_now
-		      && (prev_insn_fixp[0]->fx_r_type
-			  == BFD_RELOC_MIPS_GOT_DISP
-			  || (prev_insn_fixp[0]->fx_r_type
-			      == BFD_RELOC_MIPS_CALL16)))
-		    {
-		      /* To avoid confusion in tc_gen_reloc, we must
-			 ensure that this does not become a variant
-			 frag.  */
-		      force_new_frag = TRUE;
-		    }
-
-		  if (!relaxed_branch)
-		    {
-		      if (fixp[0])
-			{
-			  fixp[0]->fx_frag = prev_insn_frag;
-			  fixp[0]->fx_where = prev_insn_where;
-			}
-		      if (fixp[1])
-			{
-			  fixp[1]->fx_frag = prev_insn_frag;
-			  fixp[1]->fx_where = prev_insn_where;
-			}
-		      if (fixp[2])
-			{
-			  fixp[2]->fx_frag = prev_insn_frag;
-			  fixp[2]->fx_where = prev_insn_where;
-			}
-		    }
-		  else if (prev_insn_frag->fr_type == rs_machine_dependent)
-		    {
-		      if (fixp[0])
-			fixp[0]->fx_where -= 4;
-		      if (fixp[1])
-			fixp[1]->fx_where -= 4;
-		      if (fixp[2])
-			fixp[2]->fx_where -= 4;
-		    }
+		  know (delay.frag == ip->frag);
+                  move_insn (ip, delay.frag, delay.where);
+		  move_insn (&delay, ip->frag, ip->where + insn_length (ip));
+		}
+	      else if (relaxed_branch)
+		{
+		  /* Add the delay slot instruction to the end of the
+		     current frag and shrink the fixed part of the
+		     original frag.  If the branch occupies the tail of
+		     the latter, move it backwards to cover the gap.  */
+		  delay.frag->fr_fix -= 4;
+		  if (delay.frag == ip->frag)
+		    move_insn (ip, ip->frag, ip->where - 4);
+		  add_fixed_insn (&delay);
 		}
 	      else
 		{
-		  char *prev_f;
-		  char temp[2];
-
-		  assert (prev_insn_fixp[0] == NULL);
-		  assert (prev_insn_fixp[1] == NULL);
-		  assert (prev_insn_fixp[2] == NULL);
-		  prev_f = prev_insn_frag->fr_literal + prev_insn_where;
-		  memcpy (temp, prev_f, 2);
-		  memcpy (prev_f, f, 2);
-		  if (*reloc_type != BFD_RELOC_MIPS16_JMP)
-		    {
-		      assert (*reloc_type == BFD_RELOC_UNUSED);
-		      memcpy (f, temp, 2);
-		    }
-		  else
-		    {
-		      memcpy (f, f + 2, 2);
-		      memcpy (f + 2, temp, 2);
-		    }
-		  if (fixp[0])
-		    {
-		      fixp[0]->fx_frag = prev_insn_frag;
-		      fixp[0]->fx_where = prev_insn_where;
-		    }
-		  if (fixp[1])
-		    {
-		      fixp[1]->fx_frag = prev_insn_frag;
-		      fixp[1]->fx_where = prev_insn_where;
-		    }
-		  if (fixp[2])
-		    {
-		      fixp[2]->fx_frag = prev_insn_frag;
-		      fixp[2]->fx_where = prev_insn_where;
-		    }
+		  move_insn (&delay, ip->frag, ip->where);
+		  move_insn (ip, history[0].frag, history[0].where);
 		}
-
-	      /* Update the previous insn information; leave prev_insn
-		 unchanged.  */
-	      prev_prev_insn = *ip;
+	      history[0] = *ip;
+	      delay.fixed_p = 1;
+	      insert_into_history (0, 1, &delay);
 	    }
-	  prev_insn_is_delay_slot = 1;
 
 	  /* If that was an unconditional branch, forget the previous
 	     insn information.  */
 	  if (pinfo & INSN_UNCOND_BRANCH_DELAY)
-	    {
-	      prev_prev_insn.insn_mo = &dummy_opcode;
-	      prev_insn.insn_mo = &dummy_opcode;
-	    }
-
-	  prev_insn_fixp[0] = NULL;
-	  prev_insn_fixp[1] = NULL;
-	  prev_insn_fixp[2] = NULL;
-	  prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
-	  prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
-	  prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
-	  prev_insn_extended = 0;
+	    mips_no_prev_insn ();
 	}
       else if (pinfo & INSN_COND_BRANCH_LIKELY)
 	{
@@ -2697,170 +2780,70 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
 	     is look at the target, copy the instruction found there
 	     into the delay slot, and increment the branch to jump to
 	     the next instruction.  */
+	  insert_into_history (0, 1, ip);
 	  emit_nop ();
-	  /* Update the previous insn information.  */
-	  prev_prev_insn = *ip;
-	  prev_insn.insn_mo = &dummy_opcode;
-	  prev_insn_fixp[0] = NULL;
-	  prev_insn_fixp[1] = NULL;
-	  prev_insn_fixp[2] = NULL;
-	  prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
-	  prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
-	  prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
-	  prev_insn_extended = 0;
-	  prev_insn_is_delay_slot = 1;
 	}
       else
-	{
-	  /* Update the previous insn information.  */
-	  if (nops > 0)
-	    prev_prev_insn.insn_mo = &dummy_opcode;
-	  else
-	    prev_prev_insn = prev_insn;
-	  prev_insn = *ip;
-
-	  /* Any time we see a branch, we always fill the delay slot
-	     immediately; since this insn is not a branch, we know it
-	     is not in a delay slot.  */
-	  prev_insn_is_delay_slot = 0;
-
-	  prev_insn_fixp[0] = fixp[0];
-	  prev_insn_fixp[1] = fixp[1];
-	  prev_insn_fixp[2] = fixp[2];
-	  prev_insn_reloc_type[0] = reloc_type[0];
-	  prev_insn_reloc_type[1] = reloc_type[1];
-	  prev_insn_reloc_type[2] = reloc_type[2];
-	  if (mips_opts.mips16)
-	    prev_insn_extended = (ip->use_extend
-				  || *reloc_type > BFD_RELOC_UNUSED);
-	}
-
-      prev_prev_insn_unreordered = prev_insn_unreordered;
-      prev_insn_unreordered = 0;
-      prev_insn_frag = frag_now;
-      prev_insn_where = f - frag_now->fr_literal;
-      prev_insn_valid = 1;
-    }
-  else if (mips_relax.sequence != 2)
-    {
-      /* We need to record a bit of information even when we are not
-         reordering, in order to determine the base address for mips16
-         PC relative relocs.  */
-      prev_prev_insn = prev_insn;
-      prev_insn = *ip;
-      prev_insn_reloc_type[0] = reloc_type[0];
-      prev_insn_reloc_type[1] = reloc_type[1];
-      prev_insn_reloc_type[2] = reloc_type[2];
-      prev_prev_insn_unreordered = prev_insn_unreordered;
-      prev_insn_unreordered = 1;
+	insert_into_history (0, 1, ip);
     }
+  else
+    insert_into_history (0, 1, ip);
 
   /* We just output an insn, so the next one doesn't have a label.  */
   mips_clear_insn_labels ();
 }
 
-/* This function forgets that there was any previous instruction or
-   label.  If PRESERVE is non-zero, it remembers enough information to
-   know whether nops are needed before a noreorder section.  */
+/* Forget that there was any previous instruction or label.  */
 
 static void
-mips_no_prev_insn (int preserve)
+mips_no_prev_insn (void)
 {
-  if (! preserve)
-    {
-      prev_insn.insn_mo = &dummy_opcode;
-      prev_prev_insn.insn_mo = &dummy_opcode;
-      prev_nop_frag = NULL;
-      prev_nop_frag_holds = 0;
-      prev_nop_frag_required = 0;
-      prev_nop_frag_since = 0;
-    }
-  prev_insn_valid = 0;
-  prev_insn_is_delay_slot = 0;
-  prev_insn_unreordered = 0;
-  prev_insn_extended = 0;
-  prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
-  prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
-  prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
-  prev_prev_insn_unreordered = 0;
+  prev_nop_frag = NULL;
+  insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
   mips_clear_insn_labels ();
 }
 
-/* This function must be called whenever we turn on noreorder or emit
-   something other than instructions.  It inserts any NOPS which might
-   be needed by the previous instruction, and clears the information
-   kept for the previous instructions.  The INSNS parameter is true if
-   instructions are to follow.  */
+/* This function must be called before we emit something other than
+   instructions.  It is like mips_no_prev_insn except that it inserts
+   any NOPS that might be needed by previous instructions.  */
 
-static void
-mips_emit_delays (bfd_boolean insns)
+void
+mips_emit_delays (void)
 {
   if (! mips_opts.noreorder)
     {
-      int nops;
-
-      nops = 0;
-      if ((! mips_opts.mips16
-	   && ((prev_insn.insn_mo->pinfo
-		& (INSN_LOAD_COPROC_DELAY
-		   | INSN_COPROC_MOVE_DELAY
-		   | INSN_WRITE_COND_CODE))
-	       && ! cop_interlocks))
-	  || (! hilo_interlocks
-	      && (prev_insn.insn_mo->pinfo
-		  & (INSN_READ_LO
-		     | INSN_READ_HI)))
-	  || (! mips_opts.mips16
-	      && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
-	      && ! gpr_interlocks)
-	  || (! mips_opts.mips16
-	      && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
-	      && ! cop_mem_interlocks))
-	{
-	  /* Itbl support may require additional care here.  */
-	  ++nops;
-	  if ((! mips_opts.mips16
-	       && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
-		   && ! cop_interlocks))
-	      || (! hilo_interlocks
-		  && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
-		      || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
-	    ++nops;
-
-	  if (prev_insn_unreordered)
-	    nops = 0;
-	}
-      else if ((! mips_opts.mips16
-		&& ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
-		    && ! cop_interlocks))
-	       || (! hilo_interlocks
-		   && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
-		       || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
+      int nops = nops_for_insn (history, NULL);
+      if (nops > 0)
 	{
-	  /* Itbl support may require additional care here.  */
-	  if (! prev_prev_insn_unreordered)
-	    ++nops;
+	  while (nops-- > 0)
+	    add_fixed_insn (NOP_INSN);
+	  mips_move_labels ();
 	}
+    }
+  mips_no_prev_insn ();
+}
 
-      if (mips_fix_vr4120 && prev_insn.insn_mo->name)
-	{
-	  int min_nops = 0;
-	  const char *pn = prev_insn.insn_mo->name;
-	  if (strncmp(pn, "macc", 4) == 0
-	      || strncmp(pn, "dmacc", 5) == 0
-	      || strncmp(pn, "dmult", 5) == 0)
-	    {
-	      min_nops = 1;
-	    }
-	  if (nops < min_nops)
-	    nops = min_nops;
-	}
+/* Start a (possibly nested) noreorder block.  */
+
+static void
+start_noreorder (void)
+{
+  if (mips_opts.noreorder == 0)
+    {
+      unsigned int i;
+      int nops;
+
+      /* None of the instructions before the .set noreorder can be moved.  */
+      for (i = 0; i < ARRAY_SIZE (history); i++)
+	history[i].fixed_p = 1;
 
+      /* Insert any nops that might be needed between the .set noreorder
+	 block and the previous instructions.  We will later remove any
+	 nops that turn out not to be needed.  */
+      nops = nops_for_insn (history, NULL);
       if (nops > 0)
 	{
-	  struct insn_label_list *l;
-
-	  if (insns)
+	  if (mips_optimize != 0)
 	    {
 	      /* Record the frag which holds the nop instructions, so
                  that we can remove them if we don't need them.  */
@@ -2872,36 +2855,37 @@ mips_emit_delays (bfd_boolean insns)
 	    }
 
 	  for (; nops > 0; --nops)
-	    emit_nop ();
-
-	  if (insns)
-	    {
-	      /* Move on to a new frag, so that it is safe to simply
-                 decrease the size of prev_nop_frag.  */
-	      frag_wane (frag_now);
-	      frag_new (0);
-	    }
-
-	  for (l = insn_labels; l != NULL; l = l->next)
-	    {
-	      valueT val;
+	    add_fixed_insn (NOP_INSN);
 
-	      assert (S_GET_SEGMENT (l->label) == now_seg);
-	      symbol_set_frag (l->label, frag_now);
-	      val = (valueT) frag_now_fix ();
-	      /* mips16 text labels are stored as odd.  */
-	      if (mips_opts.mips16)
-		++val;
-	      S_SET_VALUE (l->label, val);
-	    }
+	  /* Move on to a new frag, so that it is safe to simply
+	     decrease the size of prev_nop_frag.  */
+	  frag_wane (frag_now);
+	  frag_new (0);
+	  mips_move_labels ();
 	}
+      mips16_mark_labels ();
+      mips_clear_insn_labels ();
     }
+  mips_opts.noreorder++;
+  mips_any_noreorder = 1;
+}
 
-  /* Mark instruction labels in mips16 mode.  */
-  if (insns)
-    mips16_mark_labels ();
+/* End a nested noreorder block.  */
 
-  mips_no_prev_insn (insns);
+static void
+end_noreorder (void)
+{
+  mips_opts.noreorder--;
+  if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
+    {
+      /* Commit to inserting prev_nop_frag_required nops and go back to
+	 handling nop insertion the .set reorder way.  */
+      prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
+				* (mips_opts.mips16 ? 2 : 4));
+      insert_into_history (prev_nop_frag_since,
+			   prev_nop_frag_required, NOP_INSN);
+      prev_nop_frag = NULL;
+    }
 }
 
 /* Set up global variables for the start of a new macro.  */
@@ -2911,7 +2895,7 @@ macro_start (void)
 {
   memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
   mips_macro_warning.delay_slot_p = (mips_opts.noreorder
-				     && (prev_insn.insn_mo->pinfo
+				     && (history[0].insn_mo->pinfo
 					 & (INSN_UNCOND_BRANCH_DELAY
 					    | INSN_COND_BRANCH_DELAY
 					    | INSN_COND_BRANCH_LIKELY)) != 0);
@@ -2969,6 +2953,24 @@ macro_end (void)
     }
 }
 
+/* Read a macro's relocation codes from *ARGS and store them in *R.
+   The first argument in *ARGS will be either the code for a single
+   relocation or -1 followed by the three codes that make up a
+   composite relocation.  */
+
+static void
+macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
+{
+  int i, next;
+
+  next = va_arg (*args, int);
+  if (next >= 0)
+    r[0] = (bfd_reloc_code_real_type) next;
+  else
+    for (i = 0; i < 3; i++)
+      r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
+}
+
 /* Build an instruction created by a macro expansion.  This is passed
    a pointer to the count of instructions created so far, an
    expression, the name of the instruction to build, an operand format
@@ -2977,6 +2979,7 @@ macro_end (void)
 static void
 macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 {
+  const struct mips_opcode *mo;
   struct mips_cl_insn insn;
   bfd_reloc_code_real_type r[3];
   va_list args;
@@ -2993,30 +2996,26 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
   r[0] = BFD_RELOC_UNUSED;
   r[1] = BFD_RELOC_UNUSED;
   r[2] = BFD_RELOC_UNUSED;
-  insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
-  assert (insn.insn_mo);
-  assert (strcmp (name, insn.insn_mo->name) == 0);
-
-  /* Search until we get a match for NAME.  */
-  while (1)
-    {
-      /* It is assumed here that macros will never generate
-         MDMX or MIPS-3D instructions.  */
-      if (strcmp (fmt, insn.insn_mo->args) == 0
-	  && insn.insn_mo->pinfo != INSN_MACRO
-  	  && OPCODE_IS_MEMBER (insn.insn_mo,
-  			       (mips_opts.isa
-	      		        | (file_ase_mips16 ? INSN_MIPS16 : 0)),
+  mo = (struct mips_opcode *) hash_find (op_hash, name);
+  assert (mo);
+  assert (strcmp (name, mo->name) == 0);
+
+  /* Search until we get a match for NAME.  It is assumed here that
+     macros will never generate MDMX or MIPS-3D instructions.  */
+  while (strcmp (fmt, mo->args) != 0
+	 || mo->pinfo == INSN_MACRO
+	 || !OPCODE_IS_MEMBER (mo,
+			       (mips_opts.isa
+				| (file_ase_mips16 ? INSN_MIPS16 : 0)),
 			       mips_opts.arch)
-	  && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
-	break;
-
-      ++insn.insn_mo;
-      assert (insn.insn_mo->name);
-      assert (strcmp (name, insn.insn_mo->name) == 0);
+	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
+    {
+      ++mo;
+      assert (mo->name);
+      assert (strcmp (name, mo->name) == 0);
     }
 
-  insn.insn_opcode = insn.insn_mo->match;
+  create_insn (&insn, mo);
   for (;;)
     {
       switch (*fmt++)
@@ -3034,8 +3033,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	    {
 	    case 'A':
 	    case 'E':
-	      insn.insn_opcode |= (va_arg (args, int)
-				   & OP_MASK_SHAMT) << OP_SH_SHAMT;
+	      INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
 	      continue;
 
 	    case 'B':
@@ -3044,8 +3042,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 		 in MSB form.  (When handling the instruction in the
 		 non-macro case, these arguments are sizes from which
 		 MSB values must be calculated.)  */
-	      insn.insn_opcode |= (va_arg (args, int)
-				   & OP_MASK_INSMSB) << OP_SH_INSMSB;
+	      INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
 	      continue;
 
 	    case 'C':
@@ -3055,8 +3052,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 		 in MSBD form.  (When handling the instruction in the
 		 non-macro case, these arguments are sizes from which
 		 MSBD values must be calculated.)  */
-	      insn.insn_opcode |= (va_arg (args, int)
-				   & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
+	      INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
 	      continue;
 
 	    default:
@@ -3067,72 +3063,72 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	case 't':
 	case 'w':
 	case 'E':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
+	  INSERT_OPERAND (RT, insn, va_arg (args, int));
 	  continue;
 
 	case 'c':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
+	  INSERT_OPERAND (CODE, insn, va_arg (args, int));
 	  continue;
 
 	case 'T':
 	case 'W':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
+	  INSERT_OPERAND (FT, insn, va_arg (args, int));
 	  continue;
 
 	case 'd':
 	case 'G':
 	case 'K':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
+	  INSERT_OPERAND (RD, insn, va_arg (args, int));
 	  continue;
 
 	case 'U':
 	  {
 	    int tmp = va_arg (args, int);
 
-	    insn.insn_opcode |= tmp << OP_SH_RT;
-	    insn.insn_opcode |= tmp << OP_SH_RD;
+	    INSERT_OPERAND (RT, insn, tmp);
+	    INSERT_OPERAND (RD, insn, tmp);
 	    continue;
 	  }
 
 	case 'V':
 	case 'S':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
+	  INSERT_OPERAND (FS, insn, va_arg (args, int));
 	  continue;
 
 	case 'z':
 	  continue;
 
 	case '<':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
+	  INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
 	  continue;
 
 	case 'D':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
+	  INSERT_OPERAND (FD, insn, va_arg (args, int));
 	  continue;
 
 	case 'B':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
+	  INSERT_OPERAND (CODE20, insn, va_arg (args, int));
 	  continue;
 
 	case 'J':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
+	  INSERT_OPERAND (CODE19, insn, va_arg (args, int));
 	  continue;
 
 	case 'q':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
+	  INSERT_OPERAND (CODE2, insn, va_arg (args, int));
 	  continue;
 
 	case 'b':
 	case 's':
 	case 'r':
 	case 'v':
-	  insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
+	  INSERT_OPERAND (RS, insn, va_arg (args, int));
 	  continue;
 
 	case 'i':
 	case 'j':
 	case 'o':
-	  *r = (bfd_reloc_code_real_type) va_arg (args, int);
+	  macro_read_relocs (&args, r);
 	  assert (*r == BFD_RELOC_GPREL16
 		  || *r == BFD_RELOC_MIPS_LITERAL
 		  || *r == BFD_RELOC_MIPS_HIGHER
@@ -3144,13 +3140,11 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 		  || *r == BFD_RELOC_MIPS_GOT_PAGE
 		  || *r == BFD_RELOC_MIPS_GOT_OFST
 		  || *r == BFD_RELOC_MIPS_GOT_LO16
-		  || *r == BFD_RELOC_MIPS_CALL_LO16
-		  || (ep->X_op == O_subtract
-		      && *r == BFD_RELOC_PCREL_LO16));
+		  || *r == BFD_RELOC_MIPS_CALL_LO16);
 	  continue;
 
 	case 'u':
-	  *r = (bfd_reloc_code_real_type) va_arg (args, int);
+	  macro_read_relocs (&args, r);
 	  assert (ep != NULL
 		  && (ep->X_op == O_constant
 		      || (ep->X_op == O_symbol
@@ -3159,22 +3153,27 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 			      || *r == BFD_RELOC_HI16
 			      || *r == BFD_RELOC_GPREL16
 			      || *r == BFD_RELOC_MIPS_GOT_HI16
-			      || *r == BFD_RELOC_MIPS_CALL_HI16))
-		      || (ep->X_op == O_subtract
-			  && *r == BFD_RELOC_PCREL_HI16_S)));
+			      || *r == BFD_RELOC_MIPS_CALL_HI16))));
 	  continue;
 
 	case 'p':
 	  assert (ep != NULL);
+
 	  /*
 	   * This allows macro() to pass an immediate expression for
 	   * creating short branches without creating a symbol.
-	   * Note that the expression still might come from the assembly
-	   * input, in which case the value is not checked for range nor
-	   * is a relocation entry generated (yuck).
+	   *
+	   * We don't allow branch relaxation for these branches, as
+	   * they should only appear in ".set nomacro" anyway.
 	   */
 	  if (ep->X_op == O_constant)
 	    {
+	      if ((ep->X_add_number & 3) != 0)
+		as_bad (_("branch to misaligned address (0x%lx)"),
+			(unsigned long) ep->X_add_number);
+	      if ((ep->X_add_number + 0x20000) & ~0x3ffff)
+		as_bad (_("branch address range overflow (0x%lx)"),
+			(unsigned long) ep->X_add_number);
 	      insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
 	      ep = NULL;
 	    }
@@ -3206,25 +3205,23 @@ static void
 mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 		    va_list args)
 {
+  struct mips_opcode *mo;
   struct mips_cl_insn insn;
   bfd_reloc_code_real_type r[3]
     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
 
-  insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
-  assert (insn.insn_mo);
-  assert (strcmp (name, insn.insn_mo->name) == 0);
+  mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
+  assert (mo);
+  assert (strcmp (name, mo->name) == 0);
 
-  while (strcmp (fmt, insn.insn_mo->args) != 0
-	 || insn.insn_mo->pinfo == INSN_MACRO)
+  while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
     {
-      ++insn.insn_mo;
-      assert (insn.insn_mo->name);
-      assert (strcmp (name, insn.insn_mo->name) == 0);
+      ++mo;
+      assert (mo->name);
+      assert (strcmp (name, mo->name) == 0);
     }
 
-  insn.insn_opcode = insn.insn_mo->match;
-  insn.use_extend = FALSE;
-
+  create_insn (&insn, mo);
   for (;;)
     {
       int c;
@@ -3242,20 +3239,20 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 
 	case 'y':
 	case 'w':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
+	  MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
 	  continue;
 
 	case 'x':
 	case 'v':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
+	  MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
 	  continue;
 
 	case 'z':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
+	  MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
 	  continue;
 
 	case 'Z':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
+	  MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
 	  continue;
 
 	case '0':
@@ -3265,7 +3262,7 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 	  continue;
 
 	case 'X':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
+	  MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
 	  continue;
 
 	case 'Y':
@@ -3311,7 +3308,7 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 	  continue;
 
 	case '6':
-	  insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
+	  MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
 	  continue;
 	}
 
@@ -3324,6 +3321,33 @@ mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
 }
 
 /*
+ * Sign-extend 32-bit mode constants that have bit 31 set and all
+ * higher bits unset.
+ */
+static void
+normalize_constant_expr (expressionS *ex)
+{
+  if (ex->X_op == O_constant
+      && IS_ZEXT_32BIT_NUM (ex->X_add_number))
+    ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
+			- 0x80000000);
+}
+
+/*
+ * Sign-extend 32-bit mode address offsets that have bit 31 set and
+ * all higher bits unset.
+ */
+static void
+normalize_address_expr (expressionS *ex)
+{
+  if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
+	|| (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
+      && IS_ZEXT_32BIT_NUM (ex->X_add_number))
+    ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
+			- 0x80000000);
+}
+
+/*
  * Generate a "jalr" instruction with a relocation hint to the called
  * function.  This occurs in NewABI PIC code.
  */
@@ -3350,6 +3374,7 @@ static void
 macro_build_lui (expressionS *ep, int regnum)
 {
   expressionS high_expr;
+  const struct mips_opcode *mo;
   struct mips_cl_insn insn;
   bfd_reloc_code_real_type r[3]
     = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
@@ -3370,19 +3395,24 @@ macro_build_lui (expressionS *ep, int regnum)
   else
     {
       assert (ep->X_op == O_symbol);
-      /* _gp_disp is a special case, used from s_cpload.  */
+      /* _gp_disp is a special case, used from s_cpload.
+	 __gnu_local_gp is used if mips_no_shared.  */
       assert (mips_pic == NO_PIC
 	      || (! HAVE_NEWABI
-		  && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
+		  && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
+	      || (! mips_in_shared
+		  && strcmp (S_GET_NAME (ep->X_add_symbol),
+                             "__gnu_local_gp") == 0));
       *r = BFD_RELOC_HI16_S;
     }
 
-  insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
-  assert (insn.insn_mo);
-  assert (strcmp (name, insn.insn_mo->name) == 0);
-  assert (strcmp (fmt, insn.insn_mo->args) == 0);
+  mo = hash_find (op_hash, name);
+  assert (strcmp (name, mo->name) == 0);
+  assert (strcmp (fmt, mo->args) == 0);
+  create_insn (&insn, mo);
 
-  insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
+  insn.insn_opcode = insn.insn_mo->match;
+  INSERT_OPERAND (RT, insn, regnum);
   if (*r == BFD_RELOC_UNUSED)
     {
       insn.insn_opcode |= high_expr.X_add_number;
@@ -3402,15 +3432,8 @@ macro_build_ldst_constoffset (expressionS *ep, const char *op,
   assert (ep->X_op == O_constant);
 
   /* Sign-extending 32-bit constants makes their handling easier.  */
-  if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
-		  == ~((bfd_vma) 0x7fffffff)))
-    {
-      if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
-	as_bad (_("constant too large"));
-
-      ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
-			  - 0x80000000);
-    }
+  if (!dbl)
+    normalize_constant_expr (ep);
 
   /* Right now, this routine can only handle signed 32-bit constants.  */
   if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
@@ -3433,7 +3456,7 @@ macro_build_ldst_constoffset (expressionS *ep, const char *op,
       macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
 
       if (mips_opts.noat)
-	as_warn (_("Macro used $at after \".set noat\""));
+	as_bad (_("Macro used $at after \".set noat\""));
     }
 }
 
@@ -3456,14 +3479,6 @@ set_at (int reg, int unsignedp)
     }
 }
 
-static void
-normalize_constant_expr (expressionS *ex)
-{
-  if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
-    ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
-			- 0x80000000);
-}
-
 /* Warn if an expression is not a constant.  */
 
 static void
@@ -3472,9 +3487,11 @@ check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
   if (ex->X_op == O_big)
     as_bad (_("unsupported large constant"));
   else if (ex->X_op != O_constant)
-    as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
+    as_bad (_("Instruction %s requires absolute expression"),
+	    ip->insn_mo->name);
 
-  normalize_constant_expr (ex);
+  if (HAVE_32BIT_GPRS)
+    normalize_constant_expr (ex);
 }
 
 /* Count the leading zeroes by performing a binary chop. This is a
@@ -3568,15 +3585,8 @@ load_register (int reg, expressionS *ep, int dbl)
       assert (ep->X_op == O_constant);
 
       /* Sign-extending 32-bit constants makes their handling easier.  */
-      if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
-		      == ~((bfd_vma) 0x7fffffff)))
-	{
-	  if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
-	    as_bad (_("constant too large"));
-
-	  ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
-			      - 0x80000000);
-	}
+      if (!dbl)
+	normalize_constant_expr (ep);
 
       if (IS_SEXT_16BIT_NUM (ep->X_add_number))
 	{
@@ -3605,10 +3615,12 @@ load_register (int reg, expressionS *ep, int dbl)
 
   /* The value is larger than 32 bits.  */
 
-  if (HAVE_32BIT_GPRS)
+  if (!dbl || HAVE_32BIT_GPRS)
     {
-      as_bad (_("Number (0x%lx) larger than 32 bits"),
-	      (unsigned long) ep->X_add_number);
+      char value[32];
+
+      sprintf_vma (value, ep->X_add_number);
+      as_bad (_("Number (0x%s) larger than 32 bits"), value);
       macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
       return;
     }
@@ -3790,6 +3802,13 @@ load_register (int reg, expressionS *ep, int dbl)
     macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
 }
 
+static inline void
+load_delay_nop (void)
+{
+  if (!gpr_interlocks)
+    macro_build (NULL, "nop", "");
+}
+
 /* Load an address into a register.  */
 
 static void
@@ -3833,14 +3852,21 @@ load_address (int reg, expressionS *ep, int *used_at)
 	   daddiu	$reg,<sym>		(BFD_RELOC_HI16_S)
 	   dsll		$reg,16
 	   daddiu	$reg,<sym>		(BFD_RELOC_LO16)
-       */
-      if (HAVE_64BIT_ADDRESSES)
+
+	 For GP relative symbols in 64bit address space we can use
+	 the same sequence as in 32bit address space.  */
+      if (HAVE_64BIT_SYMBOLS)
 	{
-	  /* ??? We don't provide a GP-relative alternative for these macros.
-	     It used not to be possible with the original relaxation code,
-	     but it could be done now.  */
+	  if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
+	      && !nopic_need_relax (ep->X_add_symbol, 1))
+	    {
+	      relax_start (ep->X_add_symbol);
+	      macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
+			   mips_gp_register, BFD_RELOC_GPREL16);
+	      relax_switch ();
+	    }
 
-	  if (*used_at == 0 && ! mips_opts.noat)
+	  if (*used_at == 0 && !mips_opts.noat)
 	    {
 	      macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
 	      macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
@@ -3861,11 +3887,14 @@ load_address (int reg, expressionS *ep, int *used_at)
 	      macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
 	      macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
 	    }
+
+	  if (mips_relax.sequence)
+	    relax_end ();
 	}
       else
 	{
 	  if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
-	      && ! nopic_need_relax (ep->X_add_symbol, 1))
+	      && !nopic_need_relax (ep->X_add_symbol, 1))
 	    {
 	      relax_start (ep->X_add_symbol);
 	      macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
@@ -3879,7 +3908,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    relax_end ();
 	}
     }
-  else if (mips_pic == SVR4_PIC && ! mips_big_got)
+  else if (!mips_big_got)
     {
       expressionS ex;
 
@@ -3923,7 +3952,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	  ep->X_add_number = 0;
 	  macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  relax_start (ep->X_add_symbol);
 	  relax_switch ();
 	  macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
@@ -3940,7 +3969,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    }
 	}
     }
-  else if (mips_pic == SVR4_PIC)
+  else if (mips_big_got)
     {
       expressionS ex;
 
@@ -4008,7 +4037,7 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    }
 	  macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
 		       BFD_RELOC_LO16);
 	  relax_end ();
@@ -4023,16 +4052,11 @@ load_address (int reg, expressionS *ep, int *used_at)
 	    }
 	}
     }
-  else if (mips_pic == EMBEDDED_PIC)
-    {
-      /* We always do
-	   addiu	$reg,$gp,<sym>		(BFD_RELOC_GPREL16)
-       */
-      macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
-		   reg, mips_gp_register, BFD_RELOC_GPREL16);
-    }
   else
     abort ();
+
+  if (mips_opts.noat && *used_at == 1)
+    as_bad (_("Macro used $at after \".set noat\""));
 }
 
 /* Move the contents of register SOURCE into register DEST.  */
@@ -4181,9 +4205,7 @@ macro (struct mips_cl_insn *ip)
 	 sub v0,$zero,$a0
 	 */
 
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
 
       expr1.X_add_number = 8;
       macro_build (&expr1, "bgez", "s,p", sreg);
@@ -4193,8 +4215,8 @@ macro (struct mips_cl_insn *ip)
 	move_register (dreg, sreg);
       macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
 
-      --mips_opts.noreorder;
-      return;
+      end_noreorder ();
+      break;
 
     case M_ADD_I:
       s = "addi";
@@ -4219,8 +4241,9 @@ macro (struct mips_cl_insn *ip)
 	  && imm_expr.X_add_number < 0x8000)
 	{
 	  macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, dbl);
       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
       break;
@@ -4253,9 +4276,10 @@ macro (struct mips_cl_insn *ip)
 			   treg, sreg, BFD_RELOC_LO16);
 	      macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
 	    }
-	  return;
+	  break;
 	}
 
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
       break;
@@ -4277,8 +4301,9 @@ macro (struct mips_cl_insn *ip)
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
 	{
 	  macro_build (&offset_expr, s, "s,t,p", sreg, 0);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (&offset_expr, s, "s,t,p", sreg, AT);
       break;
@@ -4289,13 +4314,14 @@ macro (struct mips_cl_insn *ip)
       if (treg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4322,7 +4348,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "nop", "", 0);
 	  else
 	    macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op != O_constant)
 	as_bad (_("Unsupported large constant"));
@@ -4335,12 +4361,12 @@ macro (struct mips_cl_insn *ip)
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
 	{
 	  macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
-	  return;
+	  break;
 	}
       maxnum = 0x7fffffff;
       if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
@@ -4359,8 +4385,9 @@ macro (struct mips_cl_insn *ip)
 	  /* result is always true */
 	  as_warn (_("Branch %s is always true"), ip->insn_mo->name);
 	  macro_build (&offset_expr, "b", "p");
-	  return;
+	  break;
 	}
+      used_at = 1;
       set_at (sreg, 0);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4374,8 +4401,9 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "beql" : "beq",
 		       "s,t,p", 0, treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4402,8 +4430,9 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "bnel" : "bne",
 		       "s,t,p", sreg, 0);
-	  return;
+	  break;
 	}
+      used_at = 1;
       set_at (sreg, 1);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4414,13 +4443,14 @@ macro (struct mips_cl_insn *ip)
       if (treg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4432,10 +4462,11 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "bnel" : "bne",
 		       "s,t,p", sreg, 0);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	goto do_false;
+      used_at = 1;
       macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4446,13 +4477,14 @@ macro (struct mips_cl_insn *ip)
       if (treg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4483,13 +4515,14 @@ macro (struct mips_cl_insn *ip)
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
 	{
 	  macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       set_at (sreg, 0);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4501,10 +4534,11 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "beql" : "beq",
 		       "s,t,p", sreg, 0);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	goto do_true;
+      used_at = 1;
       macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
       macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
       break;
@@ -4531,8 +4565,9 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "beql" : "beq",
 		       "s,t,p", sreg, 0);
-	  return;
+	  break;
 	}
+      used_at = 1;
       set_at (sreg, 1);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4543,13 +4578,14 @@ macro (struct mips_cl_insn *ip)
       if (treg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
 	  macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4563,8 +4599,9 @@ macro (struct mips_cl_insn *ip)
 	{
 	  macro_build (&offset_expr, likely ? "bnel" : "bne",
 		       "s,t,p", 0, treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
       macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
       break;
@@ -4615,7 +4652,7 @@ macro (struct mips_cl_insn *ip)
 	  }
 	macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
       }
-      return;
+      break;
 
     case M_DINS:
       {
@@ -4664,7 +4701,7 @@ macro (struct mips_cl_insn *ip)
 	macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
 		     pos + size - 1);
       }
-      return;
+      break;
 
     case M_DDIV_3:
       dbl = 1;
@@ -4683,12 +4720,10 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
 	  else
 	    macro_build (NULL, "break", "c", 7);
-	  return;
+	  break;
 	}
 
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
       if (mips_trap)
 	{
 	  macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
@@ -4702,6 +4737,7 @@ macro (struct mips_cl_insn *ip)
 	  macro_build (NULL, "break", "c", 7);
 	}
       expr1.X_add_number = -1;
+      used_at = 1;
       load_register (AT, &expr1, dbl);
       expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
       macro_build (&expr1, "bne", "s,t,p", treg, AT);
@@ -4721,7 +4757,7 @@ macro (struct mips_cl_insn *ip)
 	  macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
 	  /* We want to close the noreorder block as soon as possible, so
 	     that later insns are available for delay slot filling.  */
-	  --mips_opts.noreorder;
+	  end_noreorder ();
 	}
       else
 	{
@@ -4731,7 +4767,7 @@ macro (struct mips_cl_insn *ip)
 
 	  /* We want to close the noreorder block as soon as possible, so
 	     that later insns are available for delay slot filling.  */
-	  --mips_opts.noreorder;
+	  end_noreorder ();
 
 	  macro_build (NULL, "break", "c", 6);
 	}
@@ -4781,7 +4817,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
 	  else
 	    macro_build (NULL, "break", "c", 7);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
 	{
@@ -4789,7 +4825,7 @@ macro (struct mips_cl_insn *ip)
 	    move_register (dreg, sreg);
 	  else
 	    move_register (dreg, 0);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant
 	  && imm_expr.X_add_number == -1
@@ -4801,9 +4837,10 @@ macro (struct mips_cl_insn *ip)
 	    }
 	  else
 	    move_register (dreg, 0);
-	  return;
+	  break;
 	}
 
+      used_at = 1;
       load_register (AT, &imm_expr, dbl);
       macro_build (NULL, s, "z,s,t", sreg, AT);
       macro_build (NULL, s2, "d", dreg);
@@ -4825,16 +4862,14 @@ macro (struct mips_cl_insn *ip)
       s = "ddivu";
       s2 = "mfhi";
     do_divu3:
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
       if (mips_trap)
 	{
 	  macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
 	  macro_build (NULL, s, "z,s,t", sreg, treg);
 	  /* We want to close the noreorder block as soon as possible, so
 	     that later insns are available for delay slot filling.  */
-	  --mips_opts.noreorder;
+	  end_noreorder ();
 	}
       else
 	{
@@ -4844,11 +4879,11 @@ macro (struct mips_cl_insn *ip)
 
 	  /* We want to close the noreorder block as soon as possible, so
 	     that later insns are available for delay slot filling.  */
-	  --mips_opts.noreorder;
+	  end_noreorder ();
 	  macro_build (NULL, "break", "c", 7);
 	}
       macro_build (NULL, s2, "d", dreg);
-      return;
+      break;
 
     case M_DLCA_AB:
       dbl = 1;
@@ -4872,13 +4907,12 @@ macro (struct mips_cl_insn *ip)
 	  && offset_expr.X_add_number >= -0x8000
 	  && offset_expr.X_add_number < 0x8000)
 	{
-	  macro_build (&offset_expr,
-		       (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
+	  macro_build (&offset_expr, ADDRESS_ADDI_INSN,
 		       "t,r,j", treg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
 
-      if (treg == breg)
+      if (!mips_opts.noat && (treg == breg))
 	{
 	  tempreg = AT;
 	  used_at = 1;
@@ -4886,51 +4920,6 @@ macro (struct mips_cl_insn *ip)
       else
 	{
 	  tempreg = treg;
-	  used_at = 0;
-	}
-
-      /* When generating embedded PIC code, we permit expressions of
-	 the form
-	   la	$treg,foo-bar
-	   la	$treg,foo-bar($breg)
-	 where bar is an address in the current section.  These are used
-	 when getting the addresses of functions.  We don't permit
-	 X_add_number to be non-zero, because if the symbol is
-	 external the relaxing code needs to know that any addend is
-	 purely the offset to X_op_symbol.  */
-      if (mips_pic == EMBEDDED_PIC
-	  && offset_expr.X_op == O_subtract
-	  && (symbol_constant_p (offset_expr.X_op_symbol)
-	      ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
-	      : (symbol_equated_p (offset_expr.X_op_symbol)
-		 && (S_GET_SEGMENT
-		     (symbol_get_value_expression (offset_expr.X_op_symbol)
-		      ->X_add_symbol)
-		     == now_seg)))
-	  && (offset_expr.X_add_number == 0
-	      || OUTPUT_FLAVOR == bfd_target_elf_flavour))
-	{
-	  if (breg == 0)
-	    {
-	      tempreg = treg;
-	      used_at = 0;
-	      macro_build (&offset_expr, "lui", "t,u",
-			   tempreg, BFD_RELOC_PCREL_HI16_S);
-	    }
-	  else
-	    {
-	      macro_build (&offset_expr, "lui", "t,u",
-			   tempreg, BFD_RELOC_PCREL_HI16_S);
-	      macro_build (NULL,
-			   (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
-			   "d,v,t", tempreg, tempreg, breg);
-	    }
-	  macro_build (&offset_expr,
-		       (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
-		       "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
-	  if (! used_at)
-	    return;
-	  break;
 	}
 
       if (offset_expr.X_op != O_symbol
@@ -4941,10 +4930,7 @@ macro (struct mips_cl_insn *ip)
 	}
 
       if (offset_expr.X_op == O_constant)
-	load_register (tempreg, &offset_expr,
-		       ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
-			? (dbl || HAVE_64BIT_ADDRESSES)
-			: HAVE_64BIT_ADDRESSES));
+	load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
       else if (mips_pic == NO_PIC)
 	{
 	  /* If this is a reference to a GP relative symbol, we want
@@ -4955,30 +4941,37 @@ macro (struct mips_cl_insn *ip)
 	     If we have a constant, we need two instructions anyhow,
 	     so we may as well always use the latter form.
 
-	    With 64bit address space and a usable $at we want
-	      lui	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHEST)
-	      lui	$at,<sym>		(BFD_RELOC_HI16_S)
-	      daddiu	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHER)
-	      daddiu	$at,<sym>		(BFD_RELOC_LO16)
-	      dsll32	$tempreg,0
-	      daddu	$tempreg,$tempreg,$at
-
-	    If $at is already in use, we use a path which is suboptimal
-	    on superscalar processors.
-	      lui	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHEST)
-	      daddiu	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHER)
-	      dsll	$tempreg,16
-	      daddiu	$tempreg,<sym>		(BFD_RELOC_HI16_S)
-	      dsll	$tempreg,16
-	      daddiu	$tempreg,<sym>		(BFD_RELOC_LO16)
-	  */
-	  if (HAVE_64BIT_ADDRESSES)
+	     With 64bit address space and a usable $at we want
+	       lui	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHEST)
+	       lui	$at,<sym>		(BFD_RELOC_HI16_S)
+	       daddiu	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHER)
+	       daddiu	$at,<sym>		(BFD_RELOC_LO16)
+	       dsll32	$tempreg,0
+	       daddu	$tempreg,$tempreg,$at
+
+	     If $at is already in use, we use a path which is suboptimal
+	     on superscalar processors.
+	       lui	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHEST)
+	       daddiu	$tempreg,<sym>		(BFD_RELOC_MIPS_HIGHER)
+	       dsll	$tempreg,16
+	       daddiu	$tempreg,<sym>		(BFD_RELOC_HI16_S)
+	       dsll	$tempreg,16
+	       daddiu	$tempreg,<sym>		(BFD_RELOC_LO16)
+
+	     For GP relative symbols in 64bit address space we can use
+	     the same sequence as in 32bit address space.  */
+	  if (HAVE_64BIT_SYMBOLS)
 	    {
-	      /* ??? We don't provide a GP-relative alternative for
-		 these macros.  It used not to be possible with the
-		 original relaxation code, but it could be done now.  */
+	      if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
+		  && !nopic_need_relax (offset_expr.X_add_symbol, 1))
+		{
+		  relax_start (offset_expr.X_add_symbol);
+		  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+			       tempreg, mips_gp_register, BFD_RELOC_GPREL16);
+		  relax_switch ();
+		}
 
-	      if (used_at == 0 && ! mips_opts.noat)
+	      if (used_at == 0 && !mips_opts.noat)
 		{
 		  macro_build (&offset_expr, "lui", "t,u",
 			       tempreg, BFD_RELOC_MIPS_HIGHEST);
@@ -5005,17 +4998,22 @@ macro (struct mips_cl_insn *ip)
 		  macro_build (&offset_expr, "daddiu", "t,r,j",
 			       tempreg, tempreg, BFD_RELOC_LO16);
 		}
+
+	      if (mips_relax.sequence)
+		relax_end ();
 	    }
 	  else
 	    {
 	      if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
-		  && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
+		  && !nopic_need_relax (offset_expr.X_add_symbol, 1))
 		{
 		  relax_start (offset_expr.X_add_symbol);
 		  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			       tempreg, mips_gp_register, BFD_RELOC_GPREL16);
 		  relax_switch ();
 		}
+	      if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
+		as_bad (_("offset too large"));
 	      macro_build_lui (&offset_expr, tempreg);
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
@@ -5023,7 +5021,7 @@ macro (struct mips_cl_insn *ip)
 		relax_end ();
 	    }
 	}
-      else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
+      else if (!mips_big_got && !HAVE_NEWABI)
 	{
 	  int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
 
@@ -5059,7 +5057,9 @@ macro (struct mips_cl_insn *ip)
 
 	  if (offset_expr.X_add_number == 0)
 	    {
-	      if (breg == 0 && (call || tempreg == PIC_CALL_REG))
+	      if (mips_pic == SVR4_PIC
+		  && breg == 0
+		  && (call || tempreg == PIC_CALL_REG))
 		lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
 
 	      relax_start (offset_expr.X_add_symbol);
@@ -5070,12 +5070,12 @@ macro (struct mips_cl_insn *ip)
 		  /* We're going to put in an addu instruction using
 		     tempreg, so we may as well insert the nop right
 		     now.  */
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		}
 	      relax_switch ();
 	      macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			   tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	      relax_end ();
@@ -5087,7 +5087,7 @@ macro (struct mips_cl_insn *ip)
 		   && offset_expr.X_add_number < 0x8000)
 	    {
 	      load_got_offset (tempreg, &offset_expr);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      add_got_offset (tempreg, &offset_expr);
 	    }
 	  else
@@ -5106,7 +5106,7 @@ macro (struct mips_cl_insn *ip)
 		 not using a base register.  */
 	      if (breg == treg)
 		{
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  breg = 0;
@@ -5116,7 +5116,7 @@ macro (struct mips_cl_insn *ip)
 	      used_at = 1;
 	    }
 	}
-      else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
+      else if (!mips_big_got && HAVE_NEWABI)
 	{
 	  int add_breg_early = 0;
 
@@ -5219,7 +5219,7 @@ macro (struct mips_cl_insn *ip)
 			   BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
 	    }
 	}
-      else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
+      else if (mips_big_got && !HAVE_NEWABI)
 	{
 	  int gpdelay;
 	  int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
@@ -5289,13 +5289,13 @@ macro (struct mips_cl_insn *ip)
 		  /* We're going to put in an addu instruction using
 		     tempreg, so we may as well insert the nop right
 		     now.  */
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		}
 	    }
 	  else if (expr1.X_add_number >= -0x8000
 		   && expr1.X_add_number < 0x8000)
 	    {
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	    }
@@ -5315,7 +5315,7 @@ macro (struct mips_cl_insn *ip)
 	      else
 		{
 		  assert (tempreg == AT);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  dreg = treg;
@@ -5342,7 +5342,7 @@ macro (struct mips_cl_insn *ip)
 	  if (expr1.X_add_number >= -0x8000
 	      && expr1.X_add_number < 0x8000)
 	    {
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   tempreg, tempreg, BFD_RELOC_LO16);
 	      /* FIXME: If add_number is 0, and there was no base
@@ -5358,7 +5358,7 @@ macro (struct mips_cl_insn *ip)
 		  /* We must add in the base register now, as in the
 		     external symbol case.  */
 		  assert (tempreg == AT);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			       treg, AT, breg);
 		  tempreg = treg;
@@ -5372,10 +5372,11 @@ macro (struct mips_cl_insn *ip)
 			   AT, AT, BFD_RELOC_LO16);
 	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
 			   tempreg, tempreg, AT);
+	      used_at = 1;
 	    }
 	  relax_end ();
 	}
-      else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
+      else if (mips_big_got && HAVE_NEWABI)
 	{
 	  int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
 	  int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
@@ -5482,32 +5483,11 @@ macro (struct mips_cl_insn *ip)
 	    }
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* We use
-	       addiu	$tempreg,$gp,<sym>	(BFD_RELOC_GPREL16)
-	     */
-	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
-		       mips_gp_register, BFD_RELOC_GPREL16);
-	}
       else
 	abort ();
 
       if (breg != 0)
-	{
-	  char *s;
-
-	  if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
-	    s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
-	  else
-	    s = ADDRESS_ADD_INSN;
-
-	  macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
-	}
-
-      if (! used_at)
-	return;
-
+	macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
       break;
 
     case M_J_A:
@@ -5518,7 +5498,7 @@ macro (struct mips_cl_insn *ip)
 	macro_build (&offset_expr, "j", "a");
       else
 	macro_build (&offset_expr, "b", "p");
-      return;
+      break;
 
       /* The jal instructions must be handled as macros because when
 	 generating PIC code they expand to multi-instruction
@@ -5527,16 +5507,15 @@ macro (struct mips_cl_insn *ip)
       dreg = RA;
       /* Fall through.  */
     case M_JAL_2:
-      if (mips_pic == NO_PIC
-	  || mips_pic == EMBEDDED_PIC)
+      if (mips_pic == NO_PIC)
 	macro_build (NULL, "jalr", "d,s", dreg, sreg);
-      else if (mips_pic == SVR4_PIC)
+      else
 	{
 	  if (sreg != PIC_CALL_REG)
 	    as_warn (_("MIPS PIC call to register other than $25"));
 
 	  macro_build (NULL, "jalr", "d,s", dreg, sreg);
-	  if (! HAVE_NEWABI)
+	  if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
 	    {
 	      if (mips_cprestore_offset < 0)
 		as_warn (_("No .cprestore pseudo-op used in PIC code"));
@@ -5562,10 +5541,8 @@ macro (struct mips_cl_insn *ip)
 		}
 	    }
 	}
-      else
-	abort ();
 
-      return;
+      break;
 
     case M_JAL_A:
       if (mips_pic == NO_PIC)
@@ -5644,7 +5621,7 @@ macro (struct mips_cl_insn *ip)
 		  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			       PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
 			       mips_gp_register);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  relax_switch ();
 		}
 	      else
@@ -5659,7 +5636,7 @@ macro (struct mips_cl_insn *ip)
 		  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			       PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
 			       PIC_CALL_REG);
-		  macro_build (NULL, "nop", "");
+		  load_delay_nop ();
 		  relax_switch ();
 		  if (gpdelay)
 		    macro_build (NULL, "nop", "");
@@ -5667,7 +5644,7 @@ macro (struct mips_cl_insn *ip)
 	      macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 			   PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
 			   mips_gp_register);
-	      macro_build (NULL, "nop", "");
+	      load_delay_nop ();
 	      macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
 			   PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
 	      relax_end ();
@@ -5699,17 +5676,12 @@ macro (struct mips_cl_insn *ip)
 		}
 	    }
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  macro_build (&offset_expr, "bal", "p");
-	  /* The linker may expand the call to a longer sequence which
-	     uses $at, so we must break rather than return.  */
-	  break;
-	}
+      else if (mips_pic == VXWORKS_PIC)
+	as_bad (_("Non-PIC jump used in PIC library"));
       else
 	abort ();
 
-      return;
+      break;
 
     case M_LB_AB:
       s = "lb";
@@ -5758,7 +5730,7 @@ macro (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
       s = "ldc1";
       /* Itbl support may require additional care here.  */
@@ -5799,7 +5771,6 @@ macro (struct mips_cl_insn *ip)
       else
 	{
 	  tempreg = treg;
-	  used_at = 0;
 	}
       goto ld_st;
     case M_SB_AB:
@@ -5847,7 +5818,7 @@ macro (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
       s = "sdc1";
       coproc = 1;
@@ -5885,62 +5856,6 @@ macro (struct mips_cl_insn *ip)
       else
 	fmt = "t,o(b)";
 
-      /* Sign-extending 32-bit constants makes their handling easier.
-         The HAVE_64BIT_GPRS... part is due to the linux kernel hack
-         described below.  */
-      if ((! HAVE_64BIT_ADDRESSES
-	   && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
-          && (offset_expr.X_op == O_constant)
-	  && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
-		== ~((bfd_vma) 0x7fffffff)))
-	{
-	  if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
-	    as_bad (_("constant too large"));
-
-	  offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
-				       ^ 0x80000000) - 0x80000000);
-	}
-
-      /* For embedded PIC, we allow loads where the offset is calculated
-         by subtracting a symbol in the current segment from an unknown
-         symbol, relative to a base register, e.g.:
-		<op>	$treg, <sym>-<localsym>($breg)
-	 This is used by the compiler for switch statements.  */
-      if (mips_pic == EMBEDDED_PIC
-          && offset_expr.X_op == O_subtract
-          && (symbol_constant_p (offset_expr.X_op_symbol)
-              ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
-              : (symbol_equated_p (offset_expr.X_op_symbol)
-                 && (S_GET_SEGMENT
-                     (symbol_get_value_expression (offset_expr.X_op_symbol)
-                      ->X_add_symbol)
-                     == now_seg)))
-          && breg != 0
-          && (offset_expr.X_add_number == 0
-              || OUTPUT_FLAVOR == bfd_target_elf_flavour))
-        {
-          /* For this case, we output the instructions:
-                lui     $tempreg,<sym>          (BFD_RELOC_PCREL_HI16_S)
-                addiu   $tempreg,$tempreg,$breg
-                <op>    $treg,<sym>($tempreg)   (BFD_RELOC_PCREL_LO16)
-             If the relocation would fit entirely in 16 bits, it would be
-             nice to emit:
-                <op>    $treg,<sym>($breg)      (BFD_RELOC_PCREL_LO16)
-             instead, but that seems quite difficult.  */
-          macro_build (&offset_expr, "lui", "t,u", tempreg,
-		       BFD_RELOC_PCREL_HI16_S);
-          macro_build (NULL,
-		       ((bfd_arch_bits_per_address (stdoutput) == 32
-			 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
-			? "addu" : "daddu"),
-		       "d,v,t", tempreg, tempreg, breg);
-          macro_build (&offset_expr, s, fmt, treg,
-		       BFD_RELOC_PCREL_LO16, tempreg);
-          if (! used_at)
-            return;
-          break;
-        }
-
       if (offset_expr.X_op != O_constant
 	  && offset_expr.X_op != O_symbol)
 	{
@@ -5948,10 +5863,29 @@ macro (struct mips_cl_insn *ip)
 	  offset_expr.X_op = O_constant;
 	}
 
+      if (HAVE_32BIT_ADDRESSES
+	  && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
+	{
+	  char value [32];
+
+	  sprintf_vma (value, offset_expr.X_add_number);
+	  as_bad (_("Number (0x%s) larger than 32 bits"), value);
+	}
+
       /* A constant expression in PIC code can be handled just as it
 	 is in non PIC code.  */
-      if (mips_pic == NO_PIC
-	  || offset_expr.X_op == O_constant)
+      if (offset_expr.X_op == O_constant)
+	{
+	  expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
+				& ~(bfd_vma) 0xffff);
+	  normalize_address_expr (&expr1);
+	  load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
+	  if (breg != 0)
+	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+			 tempreg, tempreg, breg);
+	  macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
+	}
+      else if (mips_pic == NO_PIC)
 	{
 	  /* If this is a reference to a GP relative symbol, and there
 	     is no base register, we want
@@ -6006,43 +5940,30 @@ macro (struct mips_cl_insn *ip)
 	       daddu	$tempreg,$tempreg,$breg
 	       <op>	$treg,<sym>($tempreg)	(BFD_RELOC_LO16)
 
-	     If we have 64-bit addresses, as an optimization, for
-	     addresses which are 32-bit constants (e.g. kseg0/kseg1
-	     addresses) we fall back to the 32-bit address generation
-	     mechanism since it is more efficient.  Note that due to
-	     the signed offset used by memory operations, the 32-bit
-	     range is shifted down by 32768 here.  This code should
-	     probably attempt to generate 64-bit constants more
-	     efficiently in general.
-
-	     As an extension for architectures with 64-bit registers,
-	     we don't truncate 64-bit addresses given as literal
-	     constants down to 32 bits, to support existing practice
-	     in the mips64 Linux (the kernel), that compiles source
-	     files with -mabi=64, assembling them as o32 or n32 (with
-	     -Wa,-32 or -Wa,-n32).  This is not beautiful, but since
-	     the whole kernel is loaded into a memory region that is
-	     addressable with sign-extended 32-bit addresses, it is
-	     wasteful to compute the upper 32 bits of every
-	     non-literal address, that takes more space and time.
-	     Some day this should probably be implemented as an
-	     assembler option, such that the kernel doesn't have to
-	     use such ugly hacks, even though it will still have to
-	     end up converting the binary to ELF32 for a number of
-	     platforms whose boot loaders don't support ELF64
-	     binaries.  */
-	  if ((HAVE_64BIT_ADDRESSES
-	       && ! (offset_expr.X_op == O_constant
-		     && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
-	      || (HAVE_64BIT_GPRS
-		  && offset_expr.X_op == O_constant
-		  && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
+	     For GP relative symbols in 64bit address space we can use
+	     the same sequence as in 32bit address space.  */
+	  if (HAVE_64BIT_SYMBOLS)
 	    {
-	      /* ??? We don't provide a GP-relative alternative for
-		 these macros.  It used not to be possible with the
-		 original relaxation code, but it could be done now.  */
+	      if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
+		  && !nopic_need_relax (offset_expr.X_add_symbol, 1))
+		{
+		  relax_start (offset_expr.X_add_symbol);
+		  if (breg == 0)
+		    {
+		      macro_build (&offset_expr, s, fmt, treg,
+				   BFD_RELOC_GPREL16, mips_gp_register);
+		    }
+		  else
+		    {
+		      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+				   tempreg, breg, mips_gp_register);
+		      macro_build (&offset_expr, s, fmt, treg,
+				   BFD_RELOC_GPREL16, tempreg);
+		    }
+		  relax_switch ();
+		}
 
-	      if (used_at == 0 && ! mips_opts.noat)
+	      if (used_at == 0 && !mips_opts.noat)
 		{
 		  macro_build (&offset_expr, "lui", "t,u", tempreg,
 			       BFD_RELOC_MIPS_HIGHEST);
@@ -6075,23 +5996,20 @@ macro (struct mips_cl_insn *ip)
 			       BFD_RELOC_LO16, tempreg);
 		}
 
-	      return;
+	      if (mips_relax.sequence)
+		relax_end ();
+	      break;
 	    }
 
-	  if (offset_expr.X_op == O_constant
-	      && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
-	    as_bad (_("load/store address overflow (max 32 bits)"));
-
 	  if (breg == 0)
 	    {
 	      if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
-		  && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
+		  && !nopic_need_relax (offset_expr.X_add_symbol, 1))
 		{
 		  relax_start (offset_expr.X_add_symbol);
 		  macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
 			       mips_gp_register);
 		  relax_switch ();
-		  used_at = 0;
 		}
 	      macro_build_lui (&offset_expr, tempreg);
 	      macro_build (&offset_expr, s, fmt, treg,
@@ -6102,7 +6020,7 @@ macro (struct mips_cl_insn *ip)
 	  else
 	    {
 	      if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
-		  && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
+		  && !nopic_need_relax (offset_expr.X_add_symbol, 1))
 		{
 		  relax_start (offset_expr.X_add_symbol);
 		  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
@@ -6120,7 +6038,7 @@ macro (struct mips_cl_insn *ip)
 		relax_end ();
 	    }
 	}
-      else if (mips_pic == SVR4_PIC && ! mips_big_got)
+      else if (!mips_big_got)
 	{
 	  int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
 
@@ -6154,10 +6072,6 @@ macro (struct mips_cl_insn *ip)
 			     tempreg, tempreg, breg);
 	      macro_build (&offset_expr, s, fmt, treg,
 			   BFD_RELOC_MIPS_GOT_OFST, tempreg);
-
-	      if (! used_at)
-		return;
-
 	      break;
 	    }
 	  expr1.X_add_number = offset_expr.X_add_number;
@@ -6167,7 +6081,7 @@ macro (struct mips_cl_insn *ip)
 	    as_bad (_("PIC code offset overflow (max 16 signed bits)"));
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
 		       lw_reloc_type, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  relax_start (offset_expr.X_add_symbol);
 	  relax_switch ();
 	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
@@ -6178,7 +6092,7 @@ macro (struct mips_cl_insn *ip)
 			 tempreg, tempreg, breg);
 	  macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
 	}
-      else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
+      else if (mips_big_got && !HAVE_NEWABI)
 	{
 	  int gpdelay;
 
@@ -6217,7 +6131,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "nop", "");
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
 		       tempreg, BFD_RELOC_LO16);
 	  relax_end ();
@@ -6227,7 +6141,7 @@ macro (struct mips_cl_insn *ip)
 			 tempreg, tempreg, breg);
 	  macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
 	}
-      else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
+      else if (mips_big_got && HAVE_NEWABI)
 	{
 	  /* If this is a reference to an external symbol, we want
 	       lui	$tempreg,<sym>		(BFD_RELOC_MIPS_GOT_HI16)
@@ -6266,49 +6180,24 @@ macro (struct mips_cl_insn *ip)
 		       BFD_RELOC_MIPS_GOT_OFST, tempreg);
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* If there is no base register, we want
-	       <op>	$treg,<sym>($gp)	(BFD_RELOC_GPREL16)
-	     If there is a base register, we want
-	       addu	$tempreg,$breg,$gp
-	       <op>	$treg,<sym>($tempreg)	(BFD_RELOC_GPREL16)
-	     */
-	  assert (offset_expr.X_op == O_symbol);
-	  if (breg == 0)
-	    {
-	      macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
-			   mips_gp_register);
-	      used_at = 0;
-	    }
-	  else
-	    {
-	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
-			   tempreg, breg, mips_gp_register);
-	      macro_build (&offset_expr, s, fmt, treg,
-			   BFD_RELOC_GPREL16, tempreg);
-	    }
-	}
       else
 	abort ();
 
-      if (! used_at)
-	return;
-
       break;
 
     case M_LI:
     case M_LI_S:
       load_register (treg, &imm_expr, 0);
-      return;
+      break;
 
     case M_DLI:
       load_register (treg, &imm_expr, 1);
-      return;
+      break;
 
     case M_LI_SS:
       if (imm_expr.X_op == O_constant)
 	{
+	  used_at = 1;
 	  load_register (AT, &imm_expr, 0);
 	  macro_build (NULL, "mtc1", "t,G", AT, treg);
 	  break;
@@ -6322,7 +6211,7 @@ macro (struct mips_cl_insn *ip)
 		  && offset_expr.X_add_number == 0);
 	  macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
 		       BFD_RELOC_MIPS_LITERAL, mips_gp_register);
-	  return;
+	  break;
 	}
 
     case M_LI_D:
@@ -6362,7 +6251,7 @@ macro (struct mips_cl_insn *ip)
 		    }
 		}
 	    }
-	  return;
+	  break;
 	}
 
       /* We know that sym is in the .rdata section.  First we get the
@@ -6370,29 +6259,24 @@ macro (struct mips_cl_insn *ip)
       if (mips_pic == NO_PIC)
 	{
 	  macro_build_lui (&offset_expr, AT);
+	  used_at = 1;
 	}
-      else if (mips_pic == SVR4_PIC)
+      else
 	{
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
+	  used_at = 1;
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* For embedded PIC we pick up the entire address off $gp in
-	     a single instruction.  */
-	  macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
-		       mips_gp_register, BFD_RELOC_GPREL16);
-	  offset_expr.X_op = O_constant;
-	  offset_expr.X_add_number = 0;
-	}
-      else
-	abort ();
 
       /* Now we load the register(s).  */
       if (HAVE_64BIT_GPRS)
-	macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
+	{
+	  used_at = 1;
+	  macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
+	}
       else
 	{
+	  used_at = 1;
 	  macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
 	  if (treg != RA)
 	    {
@@ -6413,6 +6297,7 @@ macro (struct mips_cl_insn *ip)
          OFFSET_EXPR.  */
       if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
 	{
+	  used_at = 1;
 	  load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
 	  if (HAVE_64BIT_FPRS)
 	    {
@@ -6443,7 +6328,7 @@ macro (struct mips_cl_insn *ip)
 	    {
 	      macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
 			   BFD_RELOC_MIPS_LITERAL, mips_gp_register);
-	      return;
+	      break;
 	    }
 	  breg = mips_gp_register;
 	  r = BFD_RELOC_MIPS_LITERAL;
@@ -6452,7 +6337,8 @@ macro (struct mips_cl_insn *ip)
       else
 	{
 	  assert (strcmp (s, RDATA_SECTION_NAME) == 0);
-	  if (mips_pic == SVR4_PIC)
+	  used_at = 1;
+	  if (mips_pic != NO_PIC)
 	    macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
 			 BFD_RELOC_MIPS_GOT16, mips_gp_register);
 	  else
@@ -6476,7 +6362,7 @@ macro (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
       /* Even on a big endian machine $fn comes before $fn+1.  We have
 	 to adjust when loading from memory.  */
@@ -6490,9 +6376,6 @@ macro (struct mips_cl_insn *ip)
       offset_expr.X_add_number += 4;
       macro_build (&offset_expr, "lwc1", "T,o(b)",
 		   target_big_endian ? treg : treg + 1, r, breg);
-
-      if (breg != AT)
-	return;
       break;
 
     case M_L_DAB:
@@ -6510,7 +6393,7 @@ macro (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
       /* Itbl support may require additional care here.  */
       coproc = 1;
@@ -6528,7 +6411,7 @@ macro (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
 
       if (mips_opts.isa != ISA_MIPS1)
@@ -6565,11 +6448,6 @@ macro (struct mips_cl_insn *ip)
       fmt = "t,o(b)";
 
     ldd_std:
-      /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
-	 loads for the case of doing a pair of loads to simulate an 'ld'.
-	 This is not currently done by the compiler, and assembly coders
-	 writing embedded-pic code can cope.  */
-
       if (offset_expr.X_op != O_symbol
 	  && offset_expr.X_op != O_constant)
 	{
@@ -6577,6 +6455,15 @@ macro (struct mips_cl_insn *ip)
 	  offset_expr.X_op = O_constant;
 	}
 
+      if (HAVE_32BIT_ADDRESSES
+	  && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
+	{
+	  char value [32];
+
+	  sprintf_vma (value, offset_expr.X_add_number);
+	  as_bad (_("Number (0x%s) larger than 32 bits"), value);
+	}
+
       /* Even on a big endian machine $fn comes before $fn+1.  We have
 	 to adjust when loading from memory.  We set coproc if we must
 	 load $fn+1 first.  */
@@ -6601,16 +6488,14 @@ macro (struct mips_cl_insn *ip)
 	     If there is a base register, we add it to $at after the
 	     lui instruction.  If there is a constant, we always use
 	     the last case.  */
-	  if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
-	      || nopic_need_relax (offset_expr.X_add_symbol, 1))
-	    used_at = 1;
-	  else
+	  if (offset_expr.X_op == O_symbol
+	      && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
+	      && !nopic_need_relax (offset_expr.X_add_symbol, 1))
 	    {
 	      relax_start (offset_expr.X_add_symbol);
 	      if (breg == 0)
 		{
 		  tempreg = mips_gp_register;
-		  used_at = 0;
 		}
 	      else
 		{
@@ -6657,6 +6542,7 @@ macro (struct mips_cl_insn *ip)
 		  offset_expr.X_op = O_constant;
 		}
 	    }
+	  used_at = 1;
 	  macro_build_lui (&offset_expr, AT);
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
@@ -6671,7 +6557,7 @@ macro (struct mips_cl_insn *ip)
 	  if (mips_relax.sequence)
 	    relax_end ();
 	}
-      else if (mips_pic == SVR4_PIC && ! mips_big_got)
+      else if (!mips_big_got)
 	{
 	  /* If this is a reference to an external symbol, we want
 	       lw	$at,<sym>($gp)		(BFD_RELOC_MIPS_GOT16)
@@ -6692,7 +6578,7 @@ macro (struct mips_cl_insn *ip)
 	      || expr1.X_add_number >= 0x8000 - 4)
 	    as_bad (_("PIC code offset overflow (max 16 signed bits)"));
 	  load_got_offset (AT, &offset_expr);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 
@@ -6718,7 +6604,7 @@ macro (struct mips_cl_insn *ip)
 
 	  mips_optimize = hold_mips_optimize;
 	}
-      else if (mips_pic == SVR4_PIC)
+      else if (mips_big_got)
 	{
 	  int gpdelay;
 
@@ -6751,7 +6637,7 @@ macro (struct mips_cl_insn *ip)
 		       AT, AT, mips_gp_register);
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
 		       AT, BFD_RELOC_MIPS_GOT_LO16, AT);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 	  /* Itbl support may require additional care here.  */
@@ -6775,7 +6661,7 @@ macro (struct mips_cl_insn *ip)
 	    macro_build (NULL, "nop", "");
 	  macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
 		       BFD_RELOC_MIPS_GOT16, mips_gp_register);
-	  macro_build (NULL, "nop", "");
+	  load_delay_nop ();
 	  if (breg != 0)
 	    macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
 	  /* Itbl support may require additional care here.  */
@@ -6793,43 +6679,9 @@ macro (struct mips_cl_insn *ip)
 	  mips_optimize = hold_mips_optimize;
 	  relax_end ();
 	}
-      else if (mips_pic == EMBEDDED_PIC)
-	{
-	  /* If there is no base register, we use
-	       <op>	$treg,<sym>($gp)	(BFD_RELOC_GPREL16)
-	       <op>	$treg+1,<sym>+4($gp)	(BFD_RELOC_GPREL16)
-	     If we have a base register, we use
-	       addu	$at,$breg,$gp
-	       <op>	$treg,<sym>($at)	(BFD_RELOC_GPREL16)
-	       <op>	$treg+1,<sym>+4($at)	(BFD_RELOC_GPREL16)
-	     */
-	  if (breg == 0)
-	    {
-	      tempreg = mips_gp_register;
-	      used_at = 0;
-	    }
-	  else
-	    {
-	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
-			   AT, breg, mips_gp_register);
-	      tempreg = AT;
-	      used_at = 1;
-	    }
-
-	  /* Itbl support may require additional care here.  */
-	  macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
-		       BFD_RELOC_GPREL16, tempreg);
-	  offset_expr.X_add_number += 4;
-	  /* Itbl support may require additional care here.  */
-	  macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
-		       BFD_RELOC_GPREL16, tempreg);
-	}
       else
 	abort ();
 
-      if (! used_at)
-	return;
-
       break;
 
     case M_LD_OB:
@@ -6842,7 +6694,7 @@ macro (struct mips_cl_insn *ip)
       macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
       offset_expr.X_add_number += 4;
       macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
-      return;
+      break;
 
    /* New code added to support COPZ instructions.
       This code builds table entries out of the macros in mip_opcodes.
@@ -6876,11 +6728,11 @@ macro (struct mips_cl_insn *ip)
       /* For now we just do C (same as Cz).  The parameter will be
          stored in insn_opcode by mips_ip.  */
       macro_build (NULL, s, "C", ip->insn_opcode);
-      return;
+      break;
 
     case M_MOVE:
       move_register (dreg, sreg);
-      return;
+      break;
 
 #ifdef LOSING_COMPILER
     default:
@@ -6899,13 +6751,13 @@ macro (struct mips_cl_insn *ip)
 	  s2 = "cop3";
 	  coproc = ITBL_DECODE_PNUM (immed_expr);;
 	  macro_build (&immed_expr, s, "C");
-	  return;
+	  break;
 	}
       macro2 (ip);
-      return;
+      break;
     }
-  if (mips_opts.noat)
-    as_warn (_("Macro used $at after \".set noat\""));
+  if (mips_opts.noat && used_at)
+    as_bad (_("Macro used $at after \".set noat\""));
 }
 
 static void
@@ -6947,7 +6799,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_MUL:
       macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
       macro_build (NULL, "mflo", "d", dreg);
-      return;
+      break;
 
     case M_DMUL_I:
       dbl = 1;
@@ -6955,6 +6807,7 @@ macro2 (struct mips_cl_insn *ip)
       /* The MIPS assembler some times generates shifts and adds.  I'm
 	 not trying to be that fancy. GCC should do this for us
 	 anyway.  */
+      used_at = 1;
       load_register (AT, &imm_expr, dbl);
       macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
       macro_build (NULL, "mflo", "d", dreg);
@@ -6970,9 +6823,8 @@ macro2 (struct mips_cl_insn *ip)
       dbl = 1;
     case M_MULO:
     do_mulo:
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
+      used_at = 1;
       if (imm)
 	load_register (AT, &imm_expr, dbl);
       macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
@@ -6988,7 +6840,7 @@ macro2 (struct mips_cl_insn *ip)
 	  macro_build (NULL, "nop", "", 0);
 	  macro_build (NULL, "break", "c", 6);
 	}
-      --mips_opts.noreorder;
+      end_noreorder ();
       macro_build (NULL, "mflo", "d", dreg);
       break;
 
@@ -7002,9 +6854,8 @@ macro2 (struct mips_cl_insn *ip)
       dbl = 1;
     case M_MULOU:
     do_mulou:
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
+      used_at = 1;
       if (imm)
 	load_register (AT, &imm_expr, dbl);
       macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
@@ -7020,7 +6871,7 @@ macro2 (struct mips_cl_insn *ip)
 	  macro_build (NULL, "nop", "", 0);
 	  macro_build (NULL, "break", "c", 6);
 	}
-      --mips_opts.noreorder;
+      end_noreorder ();
       break;
 
     case M_DROL:
@@ -7034,14 +6885,12 @@ macro2 (struct mips_cl_insn *ip)
 	  else
 	    {
 	      tempreg = dreg;
-	      used_at = 0;
 	    }
 	  macro_build (NULL, "dnegu", "d,w", tempreg, treg);
 	  macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
-	  if (used_at)
-	    break;
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
       macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
       macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
@@ -7059,14 +6908,12 @@ macro2 (struct mips_cl_insn *ip)
 	  else
 	    {
 	      tempreg = dreg;
-	      used_at = 0;
 	    }
 	  macro_build (NULL, "negu", "d,w", tempreg, treg);
 	  macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
-	  if (used_at)
-	    break;
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
       macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
       macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
@@ -7088,16 +6935,17 @@ macro2 (struct mips_cl_insn *ip)
 	      macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
 	    else
 	      macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
-	    return;
+	    break;
 	  }
 	if (rot == 0)
 	  {
 	    macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
-	    return;
+	    break;
 	  }
 	l = (rot < 0x20) ? "dsll" : "dsll32";
 	r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
 	rot &= 0x1f;
+	used_at = 1;
 	macro_build (NULL, l, "d,w,<", AT, sreg, rot);
 	macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
 	macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
@@ -7114,13 +6962,14 @@ macro2 (struct mips_cl_insn *ip)
 	if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
 	  {
 	    macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
-	    return;
+	    break;
 	  }
 	if (rot == 0)
 	  {
 	    macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
-	    return;
+	    break;
 	  }
+	used_at = 1;
 	macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
 	macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
 	macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
@@ -7131,8 +6980,9 @@ macro2 (struct mips_cl_insn *ip)
       if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
 	{
 	  macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
       macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
       macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
@@ -7143,8 +6993,9 @@ macro2 (struct mips_cl_insn *ip)
       if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
 	{
 	  macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
-	  return;
+	  break;
 	}
+      used_at = 1;
       macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
       macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
       macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
@@ -7165,16 +7016,17 @@ macro2 (struct mips_cl_insn *ip)
 	      macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
 	    else
 	      macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
-	    return;
+	    break;
 	  }
 	if (rot == 0)
 	  {
 	    macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
-	    return;
+	    break;
 	  }
 	r = (rot < 0x20) ? "dsrl" : "dsrl32";
 	l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
 	rot &= 0x1f;
+	used_at = 1;
 	macro_build (NULL, r, "d,w,<", AT, sreg, rot);
 	macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
 	macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
@@ -7191,13 +7043,14 @@ macro2 (struct mips_cl_insn *ip)
 	if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
 	  {
 	    macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
-	    return;
+	    break;
 	  }
 	if (rot == 0)
 	  {
 	    macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
-	    return;
+	    break;
 	  }
+	used_at = 1;
 	macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
 	macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
 	macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
@@ -7208,7 +7061,7 @@ macro2 (struct mips_cl_insn *ip)
       if (mips_opts.arch == CPU_R4650)
 	{
 	  as_bad (_("opcode not supported on this processor"));
-	  return;
+	  break;
 	}
       assert (mips_opts.isa == ISA_MIPS1);
       /* Even on a big endian machine $fn comes before $fn+1.  We have
@@ -7218,7 +7071,7 @@ macro2 (struct mips_cl_insn *ip)
       offset_expr.X_add_number += 4;
       macro_build (&offset_expr, "swc1", "T,o(b)",
 		   target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
-      return;
+      break;
 
     case M_SEQ:
       if (sreg == 0)
@@ -7230,27 +7083,26 @@ macro2 (struct mips_cl_insn *ip)
 	  macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
 	  macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
 	}
-      return;
+      break;
 
     case M_SEQ_I:
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
 	{
 	  macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
 	  as_warn (_("Instruction %s: result is always false"),
 		   ip->insn_mo->name);
 	  move_register (dreg, 0);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant
 	  && imm_expr.X_add_number >= 0
 	  && imm_expr.X_add_number < 0x10000)
 	{
 	  macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
-	  used_at = 0;
 	}
       else if (imm_expr.X_op == O_constant
 	       && imm_expr.X_add_number > -0x8000
@@ -7259,7 +7111,6 @@ macro2 (struct mips_cl_insn *ip)
 	  imm_expr.X_add_number = -imm_expr.X_add_number;
 	  macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
 		       "t,r,j", dreg, sreg, BFD_RELOC_LO16);
-	  used_at = 0;
 	}
       else
 	{
@@ -7268,9 +7119,7 @@ macro2 (struct mips_cl_insn *ip)
 	  used_at = 1;
 	}
       macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
-      if (used_at)
-	break;
-      return;
+      break;
 
     case M_SGE:		/* sreg >= treg <==> not (sreg < treg) */
       s = "slt";
@@ -7280,7 +7129,7 @@ macro2 (struct mips_cl_insn *ip)
     sge:
       macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
-      return;
+      break;
 
     case M_SGE_I:		/* sreg >= I <==> not (sreg < I) */
     case M_SGEU_I:
@@ -7290,7 +7139,6 @@ macro2 (struct mips_cl_insn *ip)
 	{
 	  macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
 		       dreg, sreg, BFD_RELOC_LO16);
-	  used_at = 0;
 	}
       else
 	{
@@ -7300,9 +7148,7 @@ macro2 (struct mips_cl_insn *ip)
 	  used_at = 1;
 	}
       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
-      if (used_at)
-	break;
-      return;
+      break;
 
     case M_SGT:		/* sreg > treg  <==>  treg < sreg */
       s = "slt";
@@ -7311,7 +7157,7 @@ macro2 (struct mips_cl_insn *ip)
       s = "sltu";
     sgt:
       macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
-      return;
+      break;
 
     case M_SGT_I:		/* sreg > I  <==>  I < sreg */
       s = "slt";
@@ -7319,6 +7165,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_SGTU_I:
       s = "sltu";
     sgti:
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
       break;
@@ -7331,7 +7178,7 @@ macro2 (struct mips_cl_insn *ip)
     sle:
       macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
-      return;
+      break;
 
     case M_SLE_I:	/* sreg <= I <==> I >= sreg <==> not (I < sreg) */
       s = "slt";
@@ -7339,6 +7186,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_SLEU_I:
       s = "sltu";
     slei:
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
       macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
@@ -7350,8 +7198,9 @@ macro2 (struct mips_cl_insn *ip)
 	  && imm_expr.X_add_number < 0x8000)
 	{
 	  macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
       break;
@@ -7363,8 +7212,9 @@ macro2 (struct mips_cl_insn *ip)
 	{
 	  macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
 		       BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
       break;
@@ -7379,13 +7229,13 @@ macro2 (struct mips_cl_insn *ip)
 	  macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
 	  macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
 	}
-      return;
+      break;
 
     case M_SNE_I:
       if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
 	{
 	  macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
-	  return;
+	  break;
 	}
       if (sreg == 0)
 	{
@@ -7393,14 +7243,13 @@ macro2 (struct mips_cl_insn *ip)
 		   ip->insn_mo->name);
 	  macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
 		       dreg, 0, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
       if (imm_expr.X_op == O_constant
 	  && imm_expr.X_add_number >= 0
 	  && imm_expr.X_add_number < 0x10000)
 	{
 	  macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
-	  used_at = 0;
 	}
       else if (imm_expr.X_op == O_constant
 	       && imm_expr.X_add_number > -0x8000
@@ -7409,7 +7258,6 @@ macro2 (struct mips_cl_insn *ip)
 	  imm_expr.X_add_number = -imm_expr.X_add_number;
 	  macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
 		       "t,r,j", dreg, sreg, BFD_RELOC_LO16);
-	  used_at = 0;
 	}
       else
 	{
@@ -7418,9 +7266,7 @@ macro2 (struct mips_cl_insn *ip)
 	  used_at = 1;
 	}
       macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
-      if (used_at)
-	break;
-      return;
+      break;
 
     case M_DSUB_I:
       dbl = 1;
@@ -7432,8 +7278,9 @@ macro2 (struct mips_cl_insn *ip)
 	  imm_expr.X_add_number = -imm_expr.X_add_number;
 	  macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
 		       dreg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, dbl);
       macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
       break;
@@ -7448,8 +7295,9 @@ macro2 (struct mips_cl_insn *ip)
 	  imm_expr.X_add_number = -imm_expr.X_add_number;
 	  macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
 		       dreg, sreg, BFD_RELOC_LO16);
-	  return;
+	  break;
 	}
+      used_at = 1;
       load_register (AT, &imm_expr, dbl);
       macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
       break;
@@ -7472,6 +7320,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_TNE_I:
       s = "tne";
     trap:
+      used_at = 1;
       load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
       macro_build (NULL, s, "s,t", sreg, AT);
       break;
@@ -7479,6 +7328,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_TRUNCWS:
     case M_TRUNCWD:
       assert (mips_opts.isa == ISA_MIPS1);
+      used_at = 1;
       sreg = (ip->insn_opcode >> 11) & 0x1f;	/* floating reg */
       dreg = (ip->insn_opcode >> 06) & 0x1f;	/* floating reg */
 
@@ -7486,9 +7336,7 @@ macro2 (struct mips_cl_insn *ip)
        * Is the double cfc1 instruction a bug in the mips assembler;
        * or is there a reason for it?
        */
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
       macro_build (NULL, "cfc1", "t,G", treg, RA);
       macro_build (NULL, "cfc1", "t,G", treg, RA);
       macro_build (NULL, "nop", "");
@@ -7502,7 +7350,7 @@ macro2 (struct mips_cl_insn *ip)
 		   dreg, sreg);
       macro_build (NULL, "ctc1", "t,G", treg, RA);
       macro_build (NULL, "nop", "");
-      --mips_opts.noreorder;
+      end_noreorder ();
       break;
 
     case M_ULH:
@@ -7511,6 +7359,7 @@ macro2 (struct mips_cl_insn *ip)
     case M_ULHU:
       s = "lbu";
     ulh:
+      used_at = 1;
       if (offset_expr.X_add_number >= 0x7fff)
 	as_bad (_("operand overflow"));
       if (! target_big_endian)
@@ -7540,7 +7389,10 @@ macro2 (struct mips_cl_insn *ip)
       if (treg != breg)
 	tempreg = treg;
       else
-	tempreg = AT;
+	{
+	  used_at = 1;
+	  tempreg = AT;
+	}
       if (! target_big_endian)
 	offset_expr.X_add_number += off;
       macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
@@ -7552,10 +7404,9 @@ macro2 (struct mips_cl_insn *ip)
 
       /* If necessary, move the result in tempreg the final destination.  */
       if (treg == tempreg)
-        return;
+        break;
       /* Protect second load's delay slot.  */
-      if (!gpr_interlocks)
-	macro_build (NULL, "nop", "");
+      load_delay_nop ();
       move_register (treg, tempreg);
       break;
 
@@ -7605,6 +7456,7 @@ macro2 (struct mips_cl_insn *ip)
       break;
 
     case M_USH:
+      used_at = 1;
       if (offset_expr.X_add_number >= 0x7fff)
 	as_bad (_("operand overflow"));
       if (target_big_endian)
@@ -7638,7 +7490,7 @@ macro2 (struct mips_cl_insn *ip)
       else
 	offset_expr.X_add_number += off;
       macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
-      return;
+      break;
 
     case M_USD_A:
       s = "sdl";
@@ -7695,8 +7547,8 @@ macro2 (struct mips_cl_insn *ip)
       as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
       break;
     }
-  if (mips_opts.noat)
-    as_warn (_("Macro used $at after \".set noat\""));
+  if (mips_opts.noat && used_at)
+    as_bad (_("Macro used $at after \".set noat\""));
 }
 
 /* Implement macros in mips16 mode.  */
@@ -7712,9 +7564,9 @@ mips16_macro (struct mips_cl_insn *ip)
 
   mask = ip->insn_mo->mask;
 
-  xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
-  yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
-  zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
+  xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
+  yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
+  zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
 
   expr1.X_op = O_constant;
   expr1.X_op_symbol = NULL;
@@ -7738,9 +7590,7 @@ mips16_macro (struct mips_cl_insn *ip)
     case M_REM_3:
       s = "mfhi";
     do_div3:
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
       macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
       expr1.X_add_number = 2;
       macro_build (&expr1, "bnez", "x,p", yreg);
@@ -7750,7 +7600,7 @@ mips16_macro (struct mips_cl_insn *ip)
          since that causes an overflow.  We should do that as well,
          but I don't see how to do the comparisons without a temporary
          register.  */
-      --mips_opts.noreorder;
+      end_noreorder ();
       macro_build (NULL, s, "x", zreg);
       break;
 
@@ -7770,14 +7620,12 @@ mips16_macro (struct mips_cl_insn *ip)
       s = "ddivu";
       s2 = "mfhi";
     do_divu3:
-      mips_emit_delays (TRUE);
-      ++mips_opts.noreorder;
-      mips_any_noreorder = 1;
+      start_noreorder ();
       macro_build (NULL, s, "0,x,y", xreg, yreg);
       expr1.X_add_number = 2;
       macro_build (&expr1, "bnez", "x,p", yreg);
       macro_build (NULL, "break", "6", 7);
-      --mips_opts.noreorder;
+      end_noreorder ();
       macro_build (NULL, s2, "x", zreg);
       break;
 
@@ -7786,7 +7634,7 @@ mips16_macro (struct mips_cl_insn *ip)
     case M_MUL:
       macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
       macro_build (NULL, "mflo", "x", zreg);
-      return;
+      break;
 
     case M_DSUBU_I:
       dbl = 1;
@@ -7970,6 +7818,9 @@ validate_mips_insn (const struct mips_opcode *opc)
 	  case 'G': USE_BITS (OP_MASK_EXTMSBD,	OP_SH_EXTMSBD);	break;
 	  case 'H': USE_BITS (OP_MASK_EXTMSBD,	OP_SH_EXTMSBD);	break;
 	  case 'I': break;
+	  case 't': USE_BITS (OP_MASK_RT,	OP_SH_RT);	break;
+	  case 'T': USE_BITS (OP_MASK_RT,	OP_SH_RT);
+		    USE_BITS (OP_MASK_SEL,	OP_SH_SEL);	break;
 	  default:
 	    as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
 		    c, opc->name, opc->args);
@@ -8031,6 +7882,22 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+      case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
+      case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;
+      case '5': USE_BITS (OP_MASK_IMM8, 	OP_SH_IMM8);	break;
+      case '6': USE_BITS (OP_MASK_RS,		OP_SH_RS);	break;
+      case '7': USE_BITS (OP_MASK_DSPACC,	OP_SH_DSPACC);	break;
+      case '8': USE_BITS (OP_MASK_WRDSP,	OP_SH_WRDSP);	break;
+      case '9': USE_BITS (OP_MASK_DSPACC_S,	OP_SH_DSPACC_S);break;
+      case '0': USE_BITS (OP_MASK_DSPSFT,	OP_SH_DSPSFT);	break;
+      case '\'': USE_BITS (OP_MASK_RDDSP,	OP_SH_RDDSP);	break;
+      case ':': USE_BITS (OP_MASK_DSPSFT_7,	OP_SH_DSPSFT_7);break;
+      case '@': USE_BITS (OP_MASK_IMM10,	OP_SH_IMM10);	break;
+      case '!': USE_BITS (OP_MASK_MT_U,		OP_SH_MT_U);	break;
+      case '$': USE_BITS (OP_MASK_MT_H,		OP_SH_MT_H);	break;
+      case '*': USE_BITS (OP_MASK_MTACC_T,	OP_SH_MTACC_T);	break;
+      case '&': USE_BITS (OP_MASK_MTACC_D,	OP_SH_MTACC_D);	break;
+      case 'g': USE_BITS (OP_MASK_RD,		OP_SH_RD);	break;
       default:
 	as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
 		c, opc->name, opc->args);
@@ -8065,6 +7932,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
   unsigned int limlo, limhi;
   char *s_reset;
   char save_c = 0;
+  offsetT min_range, max_range;
 
   insn_error = NULL;
 
@@ -8127,6 +7995,8 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 			    (mips_opts.isa
 			     | (file_ase_mips16 ? INSN_MIPS16 : 0)
 	      		     | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
+	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
+	      		     | (mips_opts.ase_mt ? INSN_MT : 0)
 			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
 			    mips_opts.arch))
 	ok = TRUE;
@@ -8164,8 +8034,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	    }
 	}
 
-      ip->insn_mo = insn;
-      ip->insn_opcode = insn->match;
+      create_insn (ip, insn);
       insn_error = NULL;
       for (args = insn->args;; ++args)
 	{
@@ -8180,6 +8049,229 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		return;
 	      break;
 
+	    case '3': /* dsp 3-bit unsigned immediate in bit 21 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_SA3)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_SA3;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '4': /* dsp 4-bit unsigned immediate in bit 21 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_SA4)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_SA4;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '5': /* dsp 8-bit unsigned immediate in bit 16 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_IMM8)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_IMM8;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '6': /* dsp 5-bit unsigned immediate in bit 21 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_RS)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_RS;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '7': /* four dsp accumulators in bits 11,12 */ 
+	      if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+		  s[3] >= '0' && s[3] <= '3')
+		{
+		  regno = s[3] - '0';
+		  s += 4;
+		  ip->insn_opcode |= regno << OP_SH_DSPACC;
+		  continue;
+		}
+	      else
+		as_bad (_("Invalid dsp acc register"));
+	      break;
+
+	    case '8': /* dsp 6-bit unsigned immediate in bit 11 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_WRDSP,
+			   (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_WRDSP;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '9': /* four dsp accumulators in bits 21,22 */
+	      if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+		  s[3] >= '0' && s[3] <= '3')
+		{
+		  regno = s[3] - '0';
+		  s += 4;
+		  ip->insn_opcode |= regno << OP_SH_DSPACC_S;
+		  continue;
+		}
+	      else
+		as_bad (_("Invalid dsp acc register"));
+	      break;
+
+	    case '0': /* dsp 6-bit signed immediate in bit 20 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      min_range = -((OP_MASK_DSPSFT + 1) >> 1);
+	      max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
+	      if (imm_expr.X_add_number < min_range ||
+		  imm_expr.X_add_number > max_range)
+		{
+		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
+			   (long) min_range, (long) max_range,
+			   (long) imm_expr.X_add_number);
+		}
+	      imm_expr.X_add_number &= OP_MASK_DSPSFT;
+	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
+				  << OP_SH_DSPSFT);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
+		{
+		  as_warn (_("DSP immediate not in range 0..%d (%lu)"),
+			   OP_MASK_RDDSP,
+			   (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_RDDSP;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case ':': /* dsp 7-bit signed immediate in bit 19 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
+	      max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
+	      if (imm_expr.X_add_number < min_range ||
+		  imm_expr.X_add_number > max_range)
+		{
+		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
+			   (long) min_range, (long) max_range,
+			   (long) imm_expr.X_add_number);
+		}
+	      imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
+	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
+				  << OP_SH_DSPSFT_7);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '@': /* dsp 10-bit signed immediate in bit 16 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      min_range = -((OP_MASK_IMM10 + 1) >> 1);
+	      max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
+	      if (imm_expr.X_add_number < min_range ||
+		  imm_expr.X_add_number > max_range)
+		{
+		  as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
+			   (long) min_range, (long) max_range,
+			   (long) imm_expr.X_add_number);
+		}
+	      imm_expr.X_add_number &= OP_MASK_IMM10;
+	      ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
+				  << OP_SH_IMM10);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+            case '!': /* mt 1-bit unsigned immediate in bit 5 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_MT_U)
+		{
+		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
+			   OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_MT_U;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+            case '$': /* mt 1-bit unsigned immediate in bit 4 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if (imm_expr.X_add_number & ~OP_MASK_MT_H)
+		{
+		  as_warn (_("MT immediate not in range 0..%d (%lu)"),
+			   OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
+		  imm_expr.X_add_number &= OP_MASK_MT_H;
+		}
+	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
+	    case '*': /* four dsp accumulators in bits 18,19 */ 
+	      if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+		  s[3] >= '0' && s[3] <= '3')
+		{
+		  regno = s[3] - '0';
+		  s += 4;
+		  ip->insn_opcode |= regno << OP_SH_MTACC_T;
+		  continue;
+		}
+	      else
+		as_bad (_("Invalid dsp/smartmips acc register"));
+	      break;
+
+	    case '&': /* four dsp accumulators in bits 13,14 */ 
+	      if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
+		  s[3] >= '0' && s[3] <= '3')
+		{
+		  regno = s[3] - '0';
+		  s += 4;
+		  ip->insn_opcode |= regno << OP_SH_MTACC_D;
+		  continue;
+		}
+	      else
+		as_bad (_("Invalid dsp/smartmips acc register"));
+	      break;
+
 	    case ',':
 	      if (*s++ == *args)
 		continue;
@@ -8188,19 +8280,19 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		{
 		case 'r':
 		case 'v':
-		  ip->insn_opcode |= lastregno << OP_SH_RS;
+		  INSERT_OPERAND (RS, *ip, lastregno);
 		  continue;
 
 		case 'w':
-		  ip->insn_opcode |= lastregno << OP_SH_RT;
+		  INSERT_OPERAND (RT, *ip, lastregno);
 		  continue;
 
 		case 'W':
-		  ip->insn_opcode |= lastregno << OP_SH_FT;
+		  INSERT_OPERAND (FT, *ip, lastregno);
 		  continue;
 
 		case 'V':
-		  ip->insn_opcode |= lastregno << OP_SH_FS;
+		  INSERT_OPERAND (FS, *ip, lastregno);
 		  continue;
 		}
 	      break;
@@ -8245,8 +8337,7 @@ do_lsb:
 		      imm_expr.X_add_number = limlo;
 		    }
 		  lastpos = imm_expr.X_add_number;
-		  ip->insn_opcode |= (imm_expr.X_add_number
-				      & OP_MASK_SHAMT) << OP_SH_SHAMT;
+		  INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
 		  imm_expr.X_op = O_absent;
 		  s = expr_end;
 		  continue;
@@ -8277,8 +8368,8 @@ do_msb:
 			      (unsigned long) lastpos);
 		      imm_expr.X_add_number = limlo - lastpos;
 		    }
-		  ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
-				      & OP_MASK_INSMSB) << OP_SH_INSMSB;
+		  INSERT_OPERAND (INSMSB, *ip,
+				 lastpos + imm_expr.X_add_number - 1);
 		  imm_expr.X_op = O_absent;
 		  s = expr_end;
 		  continue;
@@ -8313,8 +8404,7 @@ do_msbd:
 			      (unsigned long) lastpos);
 		      imm_expr.X_add_number = limlo - lastpos;
 		    }
-		  ip->insn_opcode |= ((imm_expr.X_add_number - 1)
-				      & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
+		  INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
 		  imm_expr.X_op = O_absent;
 		  s = expr_end;
 		  continue;
@@ -8329,10 +8419,39 @@ do_msbd:
 		  if (imm2_expr.X_op != O_big
 		      && imm2_expr.X_op != O_constant)
 		  insn_error = _("absolute expression required");
-		  normalize_constant_expr (&imm2_expr);
+		  if (HAVE_32BIT_GPRS)
+		    normalize_constant_expr (&imm2_expr);
 		  s = expr_end;
 		  continue;
 
+		case 'T': /* Coprocessor register */
+		  /* +T is for disassembly only; never match.  */
+		  break;
+
+		case 't': /* Coprocessor register number */
+		  if (s[0] == '$' && ISDIGIT (s[1]))
+		    {
+		      ++s;
+		      regno = 0;
+		      do
+		        {
+			  regno *= 10;
+			  regno += *s - '0';
+			  ++s;
+			}
+		      while (ISDIGIT (*s));
+		      if (regno > 31)
+			as_bad (_("Invalid register number (%d)"), regno);
+		      else
+			{
+			  ip->insn_opcode |= regno << OP_SH_RT;
+			  continue;
+			}
+		    }
+		  else
+		    as_bad (_("Invalid coprocessor 0 register number"));
+		  break;
+
 		default:
 		  as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
 		    *args, insn->name, insn->args);
@@ -8351,12 +8470,9 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 31)
-		{
-		  as_warn (_("Improper shift amount (%lu)"),
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_SHAMT;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
+		as_warn (_("Improper shift amount (%lu)"),
+			 (unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8367,7 +8483,7 @@ do_msbd:
 	      if ((unsigned long) imm_expr.X_add_number < 32
 		  || (unsigned long) imm_expr.X_add_number > 63)
 		break;
-	      ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
+	      INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8377,16 +8493,13 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 31)
-		{
-		  as_warn (_("Invalid value for `%s' (%lu)"),
-			   ip->insn_mo->name,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= 0x1f;
-		}
+		as_warn (_("Invalid value for `%s' (%lu)"),
+			 ip->insn_mo->name,
+			 (unsigned long) imm_expr.X_add_number);
 	      if (*args == 'k')
-		ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
+		INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
 	      else
-		ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
+		INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8395,12 +8508,9 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		{
-		  as_warn (_("Illegal break code (%lu)"),
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_CODE;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
+		as_warn (_("Illegal break code (%lu)"),
+			 (unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8409,12 +8519,9 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 1023)
-		{
-		  as_warn (_("Illegal lower break code (%lu)"),
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_CODE2;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
+		as_warn (_("Illegal lower break code (%lu)"),
+			 (unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8425,7 +8532,7 @@ do_msbd:
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
 		as_warn (_("Illegal 20-bit code (%lu)"),
 			 (unsigned long) imm_expr.X_add_number);
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
+	      INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8450,7 +8557,7 @@ do_msbd:
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
 		as_warn (_("Illegal 19-bit code (%lu)"),
 			 (unsigned long) imm_expr.X_add_number);
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
+	      INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8459,12 +8566,9 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
-		{
-		  as_warn (_("Invalid performance register (%lu)"),
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_PERFREG;
-		}
-	      ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
+		as_warn (_("Invalid performance register (%lu)"),
+			 (unsigned long) imm_expr.X_add_number);
+	      INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8482,10 +8586,10 @@ do_msbd:
 	    case 'x':		/* ignore register name */
 	    case 'z':		/* must be zero register */
 	    case 'U':           /* destination register (clo/clz).  */
+	    case 'g':		/* coprocessor destination register */
 	      s_reset = s;
 	      if (s[0] == '$')
 		{
-
 		  if (ISDIGIT (s[1]))
 		    {
 		      ++s;
@@ -8601,21 +8705,22 @@ do_msbd:
 		    case 's':
 		    case 'v':
 		    case 'b':
-		      ip->insn_opcode |= regno << OP_SH_RS;
+		      INSERT_OPERAND (RS, *ip, regno);
 		      break;
 		    case 'd':
 		    case 'G':
 		    case 'K':
-		      ip->insn_opcode |= regno << OP_SH_RD;
+		    case 'g':
+		      INSERT_OPERAND (RD, *ip, regno);
 		      break;
 		    case 'U':
-		      ip->insn_opcode |= regno << OP_SH_RD;
-		      ip->insn_opcode |= regno << OP_SH_RT;
+		      INSERT_OPERAND (RD, *ip, regno);
+		      INSERT_OPERAND (RT, *ip, regno);
 		      break;
 		    case 'w':
 		    case 't':
 		    case 'E':
-		      ip->insn_opcode |= regno << OP_SH_RT;
+		      INSERT_OPERAND (RT, *ip, regno);
 		      break;
 		    case 'x':
 		      /* This case exists because on the r3000 trunc
@@ -8646,10 +8751,10 @@ do_msbd:
 		{
 		case 'r':
 		case 'v':
-		  ip->insn_opcode |= lastregno << OP_SH_RS;
+		  INSERT_OPERAND (RS, *ip, lastregno);
 		  continue;
 		case 'w':
-		  ip->insn_opcode |= lastregno << OP_SH_RT;
+		  INSERT_OPERAND (RT, *ip, lastregno);
 		  continue;
 		}
 	      break;
@@ -8658,12 +8763,9 @@ do_msbd:
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
-		{
-		  as_warn ("Improper align amount (%ld), using low bits",
-			   (long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= OP_MASK_ALN;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
+		as_warn ("Improper align amount (%ld), using low bits",
+			 (long) imm_expr.X_add_number);
+	      INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -8675,17 +8777,13 @@ do_msbd:
 		  my_getExpression (&imm_expr, s);
 		  check_absolute_expr (ip, &imm_expr);
 		  if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
-		    {
-		      as_warn (_("Invalid MDMX Immediate (%ld)"),
-			       (long) imm_expr.X_add_number);
-		      imm_expr.X_add_number &= OP_MASK_FT;
-		    }
-		  imm_expr.X_add_number &= OP_MASK_FT;
+		    as_warn (_("Invalid MDMX Immediate (%ld)"),
+			     (long) imm_expr.X_add_number);
+		  INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
 		  if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
 		    ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
 		  else
 		    ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
-		  ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
 		  imm_expr.X_op = O_absent;
 		  s = expr_end;
 		  continue;
@@ -8728,7 +8826,13 @@ do_msbd:
 			    || strcmp (str, "lwc1") == 0
 			    || strcmp (str, "swc1") == 0
 			    || strcmp (str, "l.s") == 0
-			    || strcmp (str, "s.s") == 0))
+			    || strcmp (str, "s.s") == 0
+			    || strcmp (str, "mftc1") == 0
+			    || strcmp (str, "mfthc1") == 0
+			    || strcmp (str, "cftc1") == 0
+			    || strcmp (str, "mttc1") == 0
+			    || strcmp (str, "mtthc1") == 0
+			    || strcmp (str, "cttc1") == 0))
 		    as_warn (_("Float register should be even, was %d"),
 			     regno);
 
@@ -8748,12 +8852,12 @@ do_msbd:
 		    {
 		    case 'D':
 		    case 'X':
-		      ip->insn_opcode |= regno << OP_SH_FD;
+		      INSERT_OPERAND (FD, *ip, regno);
 		      break;
 		    case 'V':
 		    case 'S':
 		    case 'Y':
-		      ip->insn_opcode |= regno << OP_SH_FS;
+		      INSERT_OPERAND (FS, *ip, regno);
 		      break;
 		    case 'Q':
 		      /* This is like 'Z', but also needs to fix the MDMX
@@ -8774,6 +8878,7 @@ do_msbd:
 			  ip->insn_opcode |= (imm_expr.X_add_number
 					      << (OP_SH_VSEL +
 						  (is_qh ? 2 : 1)));
+			  imm_expr.X_op = O_absent;
 			  if (*s != ']')
 			    as_warn(_("Expecting ']' found '%s'"), s);
 			  else
@@ -8792,10 +8897,10 @@ do_msbd:
 		    case 'W':
 		    case 'T':
 		    case 'Z':
-		      ip->insn_opcode |= regno << OP_SH_FT;
+		      INSERT_OPERAND (FT, *ip, regno);
 		      break;
 		    case 'R':
-		      ip->insn_opcode |= regno << OP_SH_FR;
+		      INSERT_OPERAND (FR, *ip, regno);
 		      break;
 		    }
 		  lastregno = regno;
@@ -8805,10 +8910,10 @@ do_msbd:
 	      switch (*args++)
 		{
 		case 'V':
-		  ip->insn_opcode |= lastregno << OP_SH_FS;
+		  INSERT_OPERAND (FS, *ip, lastregno);
 		  continue;
 		case 'W':
-		  ip->insn_opcode |= lastregno << OP_SH_FT;
+		  INSERT_OPERAND (FT, *ip, lastregno);
 		  continue;
 		}
 	      break;
@@ -8818,12 +8923,14 @@ do_msbd:
 	      if (imm_expr.X_op != O_big
 		  && imm_expr.X_op != O_constant)
 		insn_error = _("absolute expression required");
-	      normalize_constant_expr (&imm_expr);
+	      if (HAVE_32BIT_GPRS)
+		normalize_constant_expr (&imm_expr);
 	      s = expr_end;
 	      continue;
 
 	    case 'A':
 	      my_getExpression (&offset_expr, s);
+	      normalize_address_expr (&offset_expr);
 	      *imm_reloc = BFD_RELOC_32;
 	      s = expr_end;
 	      continue;
@@ -8863,13 +8970,6 @@ do_msbd:
 		    The .lit4 and .lit8 sections are only used if
 		    permitted by the -G argument.
 
-		    When generating embedded PIC code, we use the
-		    .lit8 section but not the .lit4 section (we can do
-		    .lit4 inline easily; we need to put .lit8
-		    somewhere in the data segment, and using .lit8
-		    permits the linker to eventually combine identical
-		    .lit8 entries).
-
 		    The code below needs to know whether the target register
 		    is 32 or 64 bits wide.  It relies on the fact 'f' and
 		    'F' are used with GPR-based instructions and 'l' and
@@ -8895,9 +8995,7 @@ do_msbd:
 
 		if (*args == 'f'
 		    || (*args == 'l'
-			&& (! USE_GLOBAL_POINTER_OPT
-			    || mips_pic == EMBEDDED_PIC
-			    || g_switch_value < 4
+			&& (g_switch_value < 4
 			    || (temp[0] == 0 && temp[1] == 0)
 			    || (temp[2] == 0 && temp[3] == 0))))
 		  {
@@ -8984,19 +9082,14 @@ do_msbd:
 		      default: /* unused default case avoids warnings.  */
 		      case 'L':
 			newname = RDATA_SECTION_NAME;
-			if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
-			    || mips_pic == EMBEDDED_PIC)
+			if (g_switch_value >= 8)
 			  newname = ".lit8";
 			break;
 		      case 'F':
-			if (mips_pic == EMBEDDED_PIC)
-			  newname = ".lit8";
-			else
-			  newname = RDATA_SECTION_NAME;
+			newname = RDATA_SECTION_NAME;
 			break;
 		      case 'l':
-			assert (!USE_GLOBAL_POINTER_OPT
-				|| g_switch_value >= 4);
+			assert (g_switch_value >= 4);
 			newname = ".lit4";
 			break;
 		      }
@@ -9152,9 +9245,9 @@ do_msbd:
 		as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
 			str, regno);
 	      if (*args == 'N')
-		ip->insn_opcode |= regno << OP_SH_BCC;
+		INSERT_OPERAND (BCC, *ip, regno);
 	      else
-		ip->insn_opcode |= regno << OP_SH_CCC;
+		INSERT_OPERAND (CCC, *ip, regno);
 	      continue;
 
 	    case 'H':
@@ -9192,7 +9285,7 @@ do_msbd:
 		  imm_expr.X_add_number = 0;
 		}
 
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
+	      INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -9209,7 +9302,7 @@ do_msbd:
 		  imm_expr.X_add_number = 0;
 		}
 
-	      ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
+	      INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -9236,6 +9329,8 @@ do_msbd:
     }
 }
 
+#define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
+
 /* This routine assembles an instruction into its binary format when
    assembling for the mips16.  As a side effect, it sets one of the
    global variables imm_reloc or offset_reloc to the type of
@@ -9253,6 +9348,7 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
   unsigned int regno;
   unsigned int lastregno = 0;
   char *s_reset;
+  size_t i;
 
   insn_error = NULL;
 
@@ -9305,9 +9401,7 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
     {
       assert (strcmp (insn->name, str) == 0);
 
-      ip->insn_mo = insn;
-      ip->insn_opcode = insn->match;
-      ip->use_extend = FALSE;
+      create_insn (ip, insn);
       imm_expr.X_op = O_absent;
       imm_reloc[0] = BFD_RELOC_UNUSED;
       imm_reloc[1] = BFD_RELOC_UNUSED;
@@ -9339,8 +9433,34 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		      && *imm_reloc > BFD_RELOC_UNUSED
 		      && insn->pinfo != INSN_MACRO)
 		    {
+		      valueT tmp;
+
+		      switch (*offset_reloc)
+			{
+			  case BFD_RELOC_MIPS16_HI16_S:
+			    tmp = (imm_expr.X_add_number + 0x8000) >> 16;
+			    break;
+
+			  case BFD_RELOC_MIPS16_HI16:
+			    tmp = imm_expr.X_add_number >> 16;
+			    break;
+
+			  case BFD_RELOC_MIPS16_LO16:
+			    tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
+				  - 0x8000;
+			    break;
+
+			  case BFD_RELOC_UNUSED:
+			    tmp = imm_expr.X_add_number;
+			    break;
+
+			  default:
+			    internalError ();
+			}
+		      *offset_reloc = BFD_RELOC_UNUSED;
+
 		      mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
-				    imm_expr.X_add_number, TRUE, mips16_small,
+				    tmp, TRUE, mips16_small,
 				    mips16_ext, &ip->insn_opcode,
 				    &ip->use_extend, &ip->extend);
 		      imm_expr.X_op = O_absent;
@@ -9358,10 +9478,10 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	      switch (*++args)
 		{
 		case 'v':
-		  ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
+		  MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
 		  continue;
 		case 'w':
-		  ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
+		  MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
 		  continue;
 		}
 	      break;
@@ -9377,9 +9497,9 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	      if (s[0] != '$')
 		{
 		  if (c == 'v')
-		    ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
+		    MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
 		  else
-		    ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
+		    MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
 		  ++args;
 		  continue;
 		}
@@ -9514,27 +9634,27 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		{
 		case 'x':
 		case 'v':
-		  ip->insn_opcode |= regno << MIPS16OP_SH_RX;
+		  MIPS16_INSERT_OPERAND (RX, *ip, regno);
 		  break;
 		case 'y':
 		case 'w':
-		  ip->insn_opcode |= regno << MIPS16OP_SH_RY;
+		  MIPS16_INSERT_OPERAND (RY, *ip, regno);
 		  break;
 		case 'z':
-		  ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
+		  MIPS16_INSERT_OPERAND (RZ, *ip, regno);
 		  break;
 		case 'Z':
-		  ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
+		  MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
 		case '0':
 		case 'S':
 		case 'R':
 		  break;
 		case 'X':
-		  ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
+		  MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
 		  break;
 		case 'Y':
 		  regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
-		  ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
+		  MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
 		  break;
 		default:
 		  internalError ();
@@ -9551,47 +9671,43 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 		}
 	      break;
 
-	    case '<':
-	    case '>':
-	    case '[':
-	    case ']':
-	    case '4':
 	    case '5':
 	    case 'H':
 	    case 'W':
 	    case 'D':
 	    case 'j':
-	    case '8':
 	    case 'V':
 	    case 'C':
 	    case 'U':
 	    case 'k':
 	    case 'K':
-	      if (s[0] == '%'
-		  && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
+	      i = my_getSmallExpression (&imm_expr, imm_reloc, s);
+	      if (i > 0)
 		{
-		  /* This is %gprel(SYMBOL).  We need to read SYMBOL,
-                     and generate the appropriate reloc.  If the text
-                     inside %gprel is not a symbol name with an
-                     optional offset, then we generate a normal reloc
-                     and will probably fail later.  */
-		  my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
-		  if (imm_expr.X_op == O_symbol)
+		  if (imm_expr.X_op != O_constant)
 		    {
 		      mips16_ext = TRUE;
-		      *imm_reloc = BFD_RELOC_MIPS16_GPREL;
-		      s = expr_end;
 		      ip->use_extend = TRUE;
 		      ip->extend = 0;
-		      continue;
 		    }
+		  else
+		    {
+		      /* We need to relax this instruction.  */
+		      *offset_reloc = *imm_reloc;
+		      *imm_reloc = (int) BFD_RELOC_UNUSED + c;
+		    }
+		  s = expr_end;
+		  continue;
 		}
-	      else
-		{
-		  /* Just pick up a normal expression.  */
-		  my_getExpression (&imm_expr, s);
-		}
-
+	      *imm_reloc = BFD_RELOC_UNUSED;
+	      /* Fall through.  */
+	    case '<':
+	    case '>':
+	    case '[':
+	    case ']':
+	    case '4':
+	    case '8':
+	      my_getExpression (&imm_expr, s);
 	      if (imm_expr.X_op == O_register)
 		{
 		  /* What we thought was an expression turned out to
@@ -9640,13 +9756,10 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
 	      if ((unsigned long) imm_expr.X_add_number > 63)
-		{
-		  as_warn (_("Invalid value for `%s' (%lu)"),
-			   ip->insn_mo->name,
-			   (unsigned long) imm_expr.X_add_number);
-		  imm_expr.X_add_number &= 0x3f;
-		}
-	      ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
+		as_warn (_("Invalid value for `%s' (%lu)"),
+			 ip->insn_mo->name,
+			 (unsigned long) imm_expr.X_add_number);
+	      MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
 	      imm_expr.X_op = O_absent;
 	      s = expr_end;
 	      continue;
@@ -9751,6 +9864,184 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
 	      }
 	    continue;
 
+	    case 'm':		/* Register list for save insn.  */
+	    case 'M':		/* Register list for restore insn.  */
+	      {
+		int opcode = 0;
+		int framesz = 0, seen_framesz = 0;
+		int args = 0, statics = 0, sregs = 0;
+
+		while (*s != '\0')
+		  {
+		    unsigned int reg1, reg2;
+
+		    SKIP_SPACE_TABS (s);
+		    while (*s == ',')
+		      ++s;
+		    SKIP_SPACE_TABS (s);
+
+		    my_getExpression (&imm_expr, s);
+		    if (imm_expr.X_op == O_constant)
+		      {
+			/* Handle the frame size.  */
+			if (seen_framesz)
+			  {
+			    as_bad (_("more than one frame size in list"));
+			    break;
+			  }
+			seen_framesz = 1;
+			framesz = imm_expr.X_add_number;
+			imm_expr.X_op = O_absent;
+			s = expr_end;
+			continue;
+		      }
+
+		    if (*s != '$')
+		      {
+			as_bad (_("can't parse register list"));
+			break;
+		      }
+		    ++s;
+
+		    reg1 = 0;
+		    while (ISDIGIT (*s))
+		      {
+			reg1 *= 10;
+			reg1 += *s - '0';
+			++s;
+		      }
+		    SKIP_SPACE_TABS (s);
+		    if (*s != '-')
+		      reg2 = reg1;
+		    else
+		      {
+			++s;
+			if (*s != '$')
+			  {
+			    as_bad (_("can't parse register list"));
+			    break;
+			  }
+			++s;
+			reg2 = 0;
+			while (ISDIGIT (*s))
+			  {
+			    reg2 *= 10;
+			    reg2 += *s - '0';
+			    ++s;
+			  }
+		      }
+
+		    while (reg1 <= reg2)
+		      {
+			if (reg1 >= 4 && reg1 <= 7)
+			  {
+			    if (c == 'm' && !seen_framesz)
+				/* args $a0-$a3 */
+				args |= 1 << (reg1 - 4);
+			    else
+				/* statics $a0-$a3 */
+				statics |= 1 << (reg1 - 4);
+			  }
+			else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
+			  {
+			    /* $s0-$s8 */
+			    sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
+			  }
+			else if (reg1 == 31)
+			  {
+			    /* Add $ra to insn.  */
+			    opcode |= 0x40;
+			  }
+			else
+			  {
+			    as_bad (_("unexpected register in list"));
+			    break;
+			  }
+			if (++reg1 == 24)
+			  reg1 = 30;
+		      }
+		  }
+
+		/* Encode args/statics combination.  */
+		if (args & statics)
+		  as_bad (_("arg/static registers overlap"));
+		else if (args == 0xf)
+		  /* All $a0-$a3 are args.  */
+		  opcode |= MIPS16_ALL_ARGS << 16;
+		else if (statics == 0xf)
+		  /* All $a0-$a3 are statics.  */
+		  opcode |= MIPS16_ALL_STATICS << 16;
+		else 
+		  {
+		    int narg = 0, nstat = 0;
+
+		    /* Count arg registers.  */
+		    while (args & 0x1)
+		      {
+			args >>= 1;
+			narg++;
+		      }
+		    if (args != 0)
+		      as_bad (_("invalid arg register list"));
+
+		    /* Count static registers.  */
+		    while (statics & 0x8)
+		      {
+			statics = (statics << 1) & 0xf;
+			nstat++;
+		      }
+		    if (statics != 0) 
+		      as_bad (_("invalid static register list"));
+
+		    /* Encode args/statics.  */
+		    opcode |= ((narg << 2) | nstat) << 16;
+		  }
+
+		/* Encode $s0/$s1.  */
+		if (sregs & (1 << 0))		/* $s0 */
+		  opcode |= 0x20;
+		if (sregs & (1 << 1))		/* $s1 */
+		  opcode |= 0x10;
+		sregs >>= 2;
+
+		if (sregs != 0)
+		  {
+		    /* Count regs $s2-$s8.  */
+		    int nsreg = 0;
+		    while (sregs & 1)
+		      {
+			sregs >>= 1;
+			nsreg++;
+		      }
+		    if (sregs != 0)
+		      as_bad (_("invalid static register list"));
+		    /* Encode $s2-$s8. */
+		    opcode |= nsreg << 24;
+		  }
+
+		/* Encode frame size.  */
+		if (!seen_framesz)
+		  as_bad (_("missing frame size"));
+		else if ((framesz & 7) != 0 || framesz < 0
+			 || framesz > 0xff * 8)
+		  as_bad (_("invalid frame size"));
+		else if (framesz != 128 || (opcode >> 16) != 0)
+		  {
+		    framesz /= 8;
+		    opcode |= (((framesz & 0xf0) << 16)
+			     | (framesz & 0x0f));
+		  }
+
+		/* Finally build the instruction.  */
+		if ((opcode >> 16) != 0 || framesz == 0)
+		  {
+		    ip->use_extend = TRUE;
+		    ip->extend = opcode >> 16;
+		  }
+		ip->insn_opcode |= opcode & 0x7f;
+	      }
+	    continue;
+
 	    case 'e':		/* extend code */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
@@ -9953,11 +10244,13 @@ mips16_immed (char *file, unsigned int line, int type, offsetT val,
     }
 }
 
-static const struct percent_op_match
+struct percent_op_match
 {
   const char *str;
   bfd_reloc_code_real_type reloc;
-} percent_op[] =
+};
+
+static const struct percent_op_match mips_percent_op[] =
 {
   {"%lo", BFD_RELOC_LO16},
 #ifdef OBJ_ELF
@@ -9975,10 +10268,24 @@ static const struct percent_op_match
   {"%highest", BFD_RELOC_MIPS_HIGHEST},
   {"%higher", BFD_RELOC_MIPS_HIGHER},
   {"%neg", BFD_RELOC_MIPS_SUB},
+  {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
+  {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
+  {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
+  {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
+  {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
+  {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
+  {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
 #endif
   {"%hi", BFD_RELOC_HI16_S}
 };
 
+static const struct percent_op_match mips16_percent_op[] =
+{
+  {"%lo", BFD_RELOC_MIPS16_LO16},
+  {"%gprel", BFD_RELOC_MIPS16_GPREL},
+  {"%hi", BFD_RELOC_MIPS16_HI16_S}
+};
+
 
 /* Return true if *STR points to a relocation operator.  When returning true,
    move *STR over the operator and store its relocation code in *RELOC.
@@ -9987,11 +10294,28 @@ static const struct percent_op_match
 static bfd_boolean
 parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
 {
-  size_t i;
+  const struct percent_op_match *percent_op;
+  size_t limit, i;
 
-  for (i = 0; i < ARRAY_SIZE (percent_op); i++)
+  if (mips_opts.mips16)
+    {
+      percent_op = mips16_percent_op;
+      limit = ARRAY_SIZE (mips16_percent_op);
+    }
+  else
+    {
+      percent_op = mips_percent_op;
+      limit = ARRAY_SIZE (mips_percent_op);
+    }
+
+  for (i = 0; i < limit; i++)
     if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
       {
+	int len = strlen (percent_op[i].str);
+
+	if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
+	  continue;
+
 	*str += strlen (percent_op[i].str);
 	*reloc = percent_op[i].reloc;
 
@@ -10001,7 +10325,7 @@ parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
 	  {
 	    as_bad ("relocation %s isn't supported by the current ABI",
 		    percent_op[i].str);
-	    *reloc = BFD_RELOC_LO16;
+	    *reloc = BFD_RELOC_UNUSED;
 	  }
 	return TRUE;
       }
@@ -10013,8 +10337,7 @@ parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
    expression in *EP and the relocations in the array starting
    at RELOC.  Return the number of relocation operators used.
 
-   On exit, EXPR_END points to the first character after the expression.
-   If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16.  */
+   On exit, EXPR_END points to the first character after the expression.  */
 
 static size_t
 my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
@@ -10060,9 +10383,7 @@ my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
 
   expr_end = str;
 
-  if (reloc_index == 0)
-    reloc[0] = BFD_RELOC_LO16;
-  else
+  if (reloc_index != 0)
     {
       prev_reloc_op_frag = frag_now;
       for (i = 0; i < reloc_index; i++)
@@ -10228,9 +10549,17 @@ struct option md_longopts[] =
   {"mdmx", no_argument, NULL, OPTION_MDMX},
 #define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
   {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
+#define OPTION_DSP (OPTION_ASE_BASE + 6)
+  {"mdsp", no_argument, NULL, OPTION_DSP},
+#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
+  {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
+#define OPTION_MT (OPTION_ASE_BASE + 8)
+  {"mmt", no_argument, NULL, OPTION_MT},
+#define OPTION_NO_MT (OPTION_ASE_BASE + 9)
+  {"mno-mt", no_argument, NULL, OPTION_NO_MT},
 
   /* Old-style architecture options.  Don't add more of these.  */
-#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
+#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
   {"m4650", no_argument, NULL, OPTION_M4650},
 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
@@ -10259,41 +10588,51 @@ struct option md_longopts[] =
 #define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
   {"mfix-vr4120",    no_argument, NULL, OPTION_FIX_VR4120},
   {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
+#define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
+#define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
+  {"mfix-vr4130",    no_argument, NULL, OPTION_FIX_VR4130},
+  {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
 
   /* Miscellaneous options.  */
-#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
-#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
-  {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
-#define OPTION_TRAP (OPTION_MISC_BASE + 1)
+#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
+#define OPTION_TRAP (OPTION_MISC_BASE + 0)
   {"trap", no_argument, NULL, OPTION_TRAP},
   {"no-break", no_argument, NULL, OPTION_TRAP},
-#define OPTION_BREAK (OPTION_MISC_BASE + 2)
+#define OPTION_BREAK (OPTION_MISC_BASE + 1)
   {"break", no_argument, NULL, OPTION_BREAK},
   {"no-trap", no_argument, NULL, OPTION_BREAK},
-#define OPTION_EB (OPTION_MISC_BASE + 3)
+#define OPTION_EB (OPTION_MISC_BASE + 2)
   {"EB", no_argument, NULL, OPTION_EB},
-#define OPTION_EL (OPTION_MISC_BASE + 4)
+#define OPTION_EL (OPTION_MISC_BASE + 3)
   {"EL", no_argument, NULL, OPTION_EL},
-#define OPTION_FP32 (OPTION_MISC_BASE + 5)
+#define OPTION_FP32 (OPTION_MISC_BASE + 4)
   {"mfp32", no_argument, NULL, OPTION_FP32},
-#define OPTION_GP32 (OPTION_MISC_BASE + 6)
+#define OPTION_GP32 (OPTION_MISC_BASE + 5)
   {"mgp32", no_argument, NULL, OPTION_GP32},
-#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
+#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
   {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
-#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
+#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
   {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
-#define OPTION_FP64 (OPTION_MISC_BASE + 9)
+#define OPTION_FP64 (OPTION_MISC_BASE + 8)
   {"mfp64", no_argument, NULL, OPTION_FP64},
-#define OPTION_GP64 (OPTION_MISC_BASE + 10)
+#define OPTION_GP64 (OPTION_MISC_BASE + 9)
   {"mgp64", no_argument, NULL, OPTION_GP64},
-#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
-#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
+#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
+#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
   {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
   {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
+#define OPTION_MSHARED (OPTION_MISC_BASE + 12)
+#define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
+  {"mshared", no_argument, NULL, OPTION_MSHARED},
+  {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
+#define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
+#define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
+  {"msym32", no_argument, NULL, OPTION_MSYM32},
+  {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
 
   /* ELF-specific options.  */
 #ifdef OBJ_ELF
-#define OPTION_ELF_BASE    (OPTION_MISC_BASE + 13)
+#define OPTION_ELF_BASE    (OPTION_MISC_BASE + 16)
 #define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
   {"KPIC",        no_argument, NULL, OPTION_CALL_SHARED},
   {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
@@ -10317,6 +10656,8 @@ struct option md_longopts[] =
   {"mpdr", no_argument, NULL, OPTION_PDR},
 #define OPTION_NO_PDR	   (OPTION_ELF_BASE + 10)
   {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
+#define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
+  {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
 #endif /* OBJ_ELF */
 
   {NULL, no_argument, NULL, 0}
@@ -10472,14 +10813,30 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mdmx = 0;
       break;
 
+    case OPTION_DSP:
+      mips_opts.ase_dsp = 1;
+      break;
+
+    case OPTION_NO_DSP:
+      mips_opts.ase_dsp = 0;
+      break;
+
+    case OPTION_MT:
+      mips_opts.ase_mt = 1;
+      break;
+
+    case OPTION_NO_MT:
+      mips_opts.ase_mt = 0;
+      break;
+
     case OPTION_MIPS16:
       mips_opts.mips16 = 1;
-      mips_no_prev_insn (FALSE);
+      mips_no_prev_insn ();
       break;
 
     case OPTION_NO_MIPS16:
       mips_opts.mips16 = 0;
-      mips_no_prev_insn (FALSE);
+      mips_no_prev_insn ();
       break;
 
     case OPTION_MIPS3D:
@@ -10490,16 +10847,6 @@ md_parse_option (int c, char *arg)
       mips_opts.ase_mips3d = 0;
       break;
 
-    case OPTION_MEMBEDDED_PIC:
-      mips_pic = EMBEDDED_PIC;
-      if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
-	{
-	  as_bad (_("-G may not be used with embedded PIC code"));
-	  return 0;
-	}
-      g_switch_value = 0x7fffffff;
-      break;
-
     case OPTION_FIX_VR4120:
       mips_fix_vr4120 = 1;
       break;
@@ -10508,6 +10855,14 @@ md_parse_option (int c, char *arg)
       mips_fix_vr4120 = 0;
       break;
 
+    case OPTION_FIX_VR4130:
+      mips_fix_vr4130 = 1;
+      break;
+
+    case OPTION_NO_FIX_VR4130:
+      mips_fix_vr4130 = 0;
+      break;
+
     case OPTION_RELAX_BRANCH:
       mips_relax_branch = 1;
       break;
@@ -10516,6 +10871,22 @@ md_parse_option (int c, char *arg)
       mips_relax_branch = 0;
       break;
 
+    case OPTION_MSHARED:
+      mips_in_shared = TRUE;
+      break;
+
+    case OPTION_MNO_SHARED:
+      mips_in_shared = FALSE;
+      break;
+
+    case OPTION_MSYM32:
+      mips_opts.sym32 = TRUE;
+      break;
+
+    case OPTION_MNO_SYM32:
+      mips_opts.sym32 = FALSE;
+      break;
+
 #ifdef OBJ_ELF
       /* When generating ELF code, we permit -KPIC and -call_shared to
 	 select SVR4_PIC, and -non_shared to select no PIC.  This is
@@ -10528,12 +10899,6 @@ md_parse_option (int c, char *arg)
 	}
       mips_pic = SVR4_PIC;
       mips_abicalls = TRUE;
-      if (g_switch_seen && g_switch_value != 0)
-	{
-	  as_bad (_("-G may not be used with SVR4 PIC code"));
-	  return 0;
-	}
-      g_switch_value = 0;
       break;
 
     case OPTION_NON_SHARED:
@@ -10546,8 +10911,8 @@ md_parse_option (int c, char *arg)
       mips_abicalls = FALSE;
       break;
 
-      /* The -xgot option tells the assembler to use 32 offsets when
-         accessing the got in SVR4_PIC mode.  It is for Irix
+      /* The -xgot option tells the assembler to use 32 bit offsets
+         when accessing the got in SVR4_PIC mode.  It is for Irix
          compatibility.  */
     case OPTION_XGOT:
       mips_big_got = 1;
@@ -10555,18 +10920,7 @@ md_parse_option (int c, char *arg)
 #endif /* OBJ_ELF */
 
     case 'G':
-      if (! USE_GLOBAL_POINTER_OPT)
-	{
-	  as_bad (_("-G is not supported for this configuration"));
-	  return 0;
-	}
-      else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
-	{
-	  as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
-	  return 0;
-	}
-      else
-	g_switch_value = atoi (arg);
+      g_switch_value = atoi (arg);
       g_switch_seen = 1;
       break;
 
@@ -10673,6 +11027,10 @@ md_parse_option (int c, char *arg)
     case OPTION_NO_PDR:
       mips_flag_pdr = FALSE;
       break;
+
+    case OPTION_MVXWORKS_PIC:
+      mips_pic = VXWORKS_PIC;
+      break;
 #endif /* OBJ_ELF */
 
     default:
@@ -10714,10 +11072,9 @@ mips_after_parse_args (void)
   const struct mips_cpu_info *tune_info = 0;
 
   /* GP relative stuff not working for PE */
-  if (strncmp (TARGET_OS, "pe", 2) == 0
-      && g_switch_value != 0)
+  if (strncmp (TARGET_OS, "pe", 2) == 0)
     {
-      if (g_switch_seen)
+      if (g_switch_seen && g_switch_value != 0)
 	as_bad (_("-G not supported in this configuration."));
       g_switch_value = 0;
     }
@@ -10819,11 +11176,17 @@ mips_after_parse_args (void)
     mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
   if (mips_opts.ase_mdmx == -1)
     mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
+  if (mips_opts.ase_dsp == -1)
+    mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
+  if (mips_opts.ase_mt == -1)
+    mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
 
   file_mips_isa = mips_opts.isa;
   file_ase_mips16 = mips_opts.mips16;
   file_ase_mips3d = mips_opts.ase_mips3d;
   file_ase_mdmx = mips_opts.ase_mdmx;
+  file_ase_dsp = mips_opts.ase_dsp;
+  file_ase_mt = mips_opts.ase_mt;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
 
@@ -10879,10 +11242,53 @@ mips_frob_file_before_adjust (void)
 #endif
 }
 
-/* Sort any unmatched HI16_S relocs so that they immediately precede
-   the corresponding LO reloc.  This is called before md_apply_fix3 and
-   tc_gen_reloc.  Unmatched HI16_S relocs can only be generated by
-   explicit use of the %hi modifier.  */
+/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
+   the corresponding LO16 reloc.  This is called before md_apply_fix and
+   tc_gen_reloc.  Unmatched relocs can only be generated by use of explicit
+   relocation operators.
+
+   For our purposes, a %lo() expression matches a %got() or %hi()
+   expression if:
+
+      (a) it refers to the same symbol; and
+      (b) the offset applied in the %lo() expression is no lower than
+	  the offset applied in the %got() or %hi().
+
+   (b) allows us to cope with code like:
+
+	lui	$4,%hi(foo)
+	lh	$4,%lo(foo+2)($4)
+
+   ...which is legal on RELA targets, and has a well-defined behaviour
+   if the user knows that adding 2 to "foo" will not induce a carry to
+   the high 16 bits.
+
+   When several %lo()s match a particular %got() or %hi(), we use the
+   following rules to distinguish them:
+
+     (1) %lo()s with smaller offsets are a better match than %lo()s with
+         higher offsets.
+
+     (2) %lo()s with no matching %got() or %hi() are better than those
+         that already have a matching %got() or %hi().
+
+     (3) later %lo()s are better than earlier %lo()s.
+
+   These rules are applied in order.
+
+   (1) means, among other things, that %lo()s with identical offsets are
+   chosen if they exist.
+
+   (2) means that we won't associate several high-part relocations with
+   the same low-part relocation unless there's no alternative.  Having
+   several high parts for the same low part is a GNU extension; this rule
+   allows careful users to avoid it.
+
+   (3) is purely cosmetic.  mips_hi_fixup_list is is in reverse order,
+   with the last high-part relocation being at the front of the list.
+   It therefore makes sense to choose the last matching low-part
+   relocation, all other things being equal.  It's also easier
+   to code that way.  */
 
 void
 mips_frob_file (void)
@@ -10892,7 +11298,8 @@ mips_frob_file (void)
   for (l = mips_hi_fixup_list; l != NULL; l = l->next)
     {
       segment_info_type *seginfo;
-      int pass;
+      bfd_boolean matched_lo_p;
+      fixS **hi_pos, **lo_pos, **pos;
 
       assert (reloc_needs_lo_p (l->fixp->fx_r_type));
 
@@ -10906,81 +11313,57 @@ mips_frob_file (void)
       if (fixup_has_matching_lo_p (l->fixp))
 	continue;
 
-      /* Look through the fixups for this segment for a matching %lo.
-         When we find one, move the %hi just in front of it.  We do
-         this in two passes.  In the first pass, we try to find a
-         unique %lo.  In the second pass, we permit multiple %hi
-         relocs for a single %lo (this is a GNU extension).  */
       seginfo = seg_info (l->seg);
-      for (pass = 0; pass < 2; pass++)
-	{
-	  fixS *f, *prev;
 
-	  prev = NULL;
-	  for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
+      /* Set HI_POS to the position of this relocation in the chain.
+	 Set LO_POS to the position of the chosen low-part relocation.
+	 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
+	 relocation that matches an immediately-preceding high-part
+	 relocation.  */
+      hi_pos = NULL;
+      lo_pos = NULL;
+      matched_lo_p = FALSE;
+      for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
+	{
+	  if (*pos == l->fixp)
+	    hi_pos = pos;
+
+	  if (((*pos)->fx_r_type == BFD_RELOC_LO16
+	       || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16)
+	      && (*pos)->fx_addsy == l->fixp->fx_addsy
+	      && (*pos)->fx_offset >= l->fixp->fx_offset
+	      && (lo_pos == NULL
+		  || (*pos)->fx_offset < (*lo_pos)->fx_offset
+		  || (!matched_lo_p
+		      && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
+	    lo_pos = pos;
+
+	  matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
+			  && fixup_has_matching_lo_p (*pos));
+	}
+
+      /* If we found a match, remove the high-part relocation from its
+	 current position and insert it before the low-part relocation.
+	 Make the offsets match so that fixup_has_matching_lo_p()
+	 will return true.
+
+	 We don't warn about unmatched high-part relocations since some
+	 versions of gcc have been known to emit dead "lui ...%hi(...)"
+	 instructions.  */
+      if (lo_pos != NULL)
+	{
+	  l->fixp->fx_offset = (*lo_pos)->fx_offset;
+	  if (l->fixp->fx_next != *lo_pos)
 	    {
-	      /* Check whether this is a %lo fixup which matches l->fixp.  */
-	      if (f->fx_r_type == BFD_RELOC_LO16
-		  && f->fx_addsy == l->fixp->fx_addsy
-		  && f->fx_offset == l->fixp->fx_offset
-		  && (pass == 1
-		      || prev == NULL
-		      || !reloc_needs_lo_p (prev->fx_r_type)
-		      || !fixup_has_matching_lo_p (prev)))
-		{
-		  fixS **pf;
-
-		  /* Move l->fixp before f.  */
-		  for (pf = &seginfo->fix_root;
-		       *pf != l->fixp;
-		       pf = &(*pf)->fx_next)
-		    assert (*pf != NULL);
-
-		  *pf = l->fixp->fx_next;
-
-		  l->fixp->fx_next = f;
-		  if (prev == NULL)
-		    seginfo->fix_root = l->fixp;
-		  else
-		    prev->fx_next = l->fixp;
-
-		  break;
-		}
-
-	      prev = f;
+	      *hi_pos = l->fixp->fx_next;
+	      l->fixp->fx_next = *lo_pos;
+	      *lo_pos = l->fixp;
 	    }
-
-	  if (f != NULL)
-	    break;
-
-#if 0 /* GCC code motion plus incomplete dead code elimination
-	 can leave a %hi without a %lo.  */
-	  if (pass == 1)
-	    as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
-			   _("Unmatched %%hi reloc"));
-#endif
 	}
     }
 }
 
-/* When generating embedded PIC code we need to use a special
-   relocation to represent the difference of two symbols in the .text
-   section (switch tables use a difference of this sort).  See
-   include/coff/mips.h for details.  This macro checks whether this
-   fixup requires the special reloc.  */
-#define SWITCH_TABLE(fixp) \
-  ((fixp)->fx_r_type == BFD_RELOC_32 \
-   && OUTPUT_FLAVOR != bfd_target_elf_flavour \
-   && (fixp)->fx_addsy != NULL \
-   && (fixp)->fx_subsy != NULL \
-   && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
-   && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
-
-/* When generating embedded PIC code we must keep all PC relative
-   relocations, in case the linker has to relax a call.  We also need
-   to keep relocations for switch table entries.
-
-   We may have combined relocations without symbols in the N32/N64 ABI.
+/* We may have combined relocations without symbols in the N32/N64 ABI.
    We have to prevent gas from dropping them.  */
 
 int
@@ -10996,99 +11379,16 @@ mips_force_relocation (fixS *fixp)
 	  || fixp->fx_r_type == BFD_RELOC_LO16))
     return 1;
 
-  return (mips_pic == EMBEDDED_PIC
-	  && (fixp->fx_pcrel
-	      || SWITCH_TABLE (fixp)
-	      || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
-	      || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
-}
-
-/* This hook is called before a fix is simplified.  We don't really
-   decide whether to skip a fix here.  Rather, we turn global symbols
-   used as branch targets into local symbols, such that they undergo
-   simplification.  We can only do this if the symbol is defined and
-   it is in the same section as the branch.  If this doesn't hold, we
-   emit a better error message than just saying the relocation is not
-   valid for the selected object format.
-
-   FIXP is the fix-up we're going to try to simplify, SEG is the
-   segment in which the fix up occurs.  The return value should be
-   non-zero to indicate the fix-up is valid for further
-   simplifications.  */
-
-int
-mips_validate_fix (struct fix *fixP, asection *seg)
-{
-  /* There's a lot of discussion on whether it should be possible to
-     use R_MIPS_PC16 to represent branch relocations.  The outcome
-     seems to be that it can, but gas/bfd are very broken in creating
-     RELA relocations for this, so for now we only accept branches to
-     symbols in the same section.  Anything else is of dubious value,
-     since there's no guarantee that at link time the symbol would be
-     in range.  Even for branches to local symbols this is arguably
-     wrong, since it we assume the symbol is not going to be
-     overridden, which should be possible per ELF library semantics,
-     but then, there isn't a dynamic relocation that could be used to
-     this effect, and the target would likely be out of range as well.
-
-     Unfortunately, it seems that there is too much code out there
-     that relies on branches to symbols that are global to be resolved
-     as if they were local, like the IRIX tools do, so we do it as
-     well, but with a warning so that people are reminded to fix their
-     code.  If we ever get back to using R_MIPS_PC16 for branch
-     targets, this entire block should go away (and probably the
-     whole function).  */
-
-  if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
-      && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
-	    || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	   && mips_pic != EMBEDDED_PIC)
-	  || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
-      && fixP->fx_addsy)
-    {
-      if (! S_IS_DEFINED (fixP->fx_addsy))
-	{
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("Cannot branch to undefined symbol."));
-	  /* Avoid any further errors about this fixup.  */
-	  fixP->fx_done = 1;
-	}
-      else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
-	{
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("Cannot branch to symbol in another section."));
-	  fixP->fx_done = 1;
-	}
-      else if (S_IS_EXTERNAL (fixP->fx_addsy))
-	{
-	  symbolS *sym = fixP->fx_addsy;
-
-	  if (mips_pic == SVR4_PIC)
-	    as_warn_where (fixP->fx_file, fixP->fx_line,
-			   _("Pretending global symbol used as branch target is local."));
-
-	  fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
-					  S_GET_SEGMENT (sym),
-					  S_GET_VALUE (sym),
-					  symbol_get_frag (sym));
-	  copy_symbol_attributes (fixP->fx_addsy, sym);
-	  S_CLEAR_EXTERNAL (fixP->fx_addsy);
-	  assert (symbol_resolved_p (sym));
-	  symbol_mark_resolved (fixP->fx_addsy);
-	}
-    }
-
-  return 1;
+  return 0;
 }
 
 /* Apply a fixup to the object file.  */
 
 void
-md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   bfd_byte *buf;
   long insn;
-  static int previous_fx_r_type = 0;
   reloc_howto_type *howto;
 
   /* We ignore generic BFD relocations we don't know about.  */
@@ -11106,20 +11406,33 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
   buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
 
-  /* We are not done if this is a composite relocation to set up gp.  */
-  if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
-      && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
-	   || (fixP->fx_r_type == BFD_RELOC_64
-	       && (previous_fx_r_type == BFD_RELOC_GPREL32
-		   || previous_fx_r_type == BFD_RELOC_GPREL16))
-	   || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
-	       && (fixP->fx_r_type == BFD_RELOC_HI16_S
-		   || fixP->fx_r_type == BFD_RELOC_LO16))))
+  assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
+
+  /* Don't treat parts of a composite relocation as done.  There are two
+     reasons for this:
+
+     (1) The second and third parts will be against 0 (RSS_UNDEF) but
+	 should nevertheless be emitted if the first part is.
+
+     (2) In normal usage, composite relocations are never assembly-time
+	 constants.  The easiest way of dealing with the pathological
+	 exceptions is to generate a relocation against STN_UNDEF and
+	 leave everything up to the linker.  */
+  if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
     fixP->fx_done = 1;
-  previous_fx_r_type = fixP->fx_r_type;
 
   switch (fixP->fx_r_type)
     {
+    case BFD_RELOC_MIPS_TLS_GD:
+    case BFD_RELOC_MIPS_TLS_LDM:
+    case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
+    case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
+    case BFD_RELOC_MIPS_TLS_GOTTPREL:
+    case BFD_RELOC_MIPS_TLS_TPREL_HI16:
+    case BFD_RELOC_MIPS_TLS_TPREL_LO16:
+      S_SET_THREAD_LOCAL (fixP->fx_addsy);
+      /* fall through */
+
     case BFD_RELOC_MIPS_JMP:
     case BFD_RELOC_MIPS_SHIFT5:
     case BFD_RELOC_MIPS_SHIFT6:
@@ -11148,9 +11461,8 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_MIPS_CALL_HI16:
     case BFD_RELOC_MIPS_CALL_LO16:
     case BFD_RELOC_MIPS16_GPREL:
-      if (fixP->fx_pcrel)
-	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("Invalid PC relative reloc"));
+    case BFD_RELOC_MIPS16_HI16:
+    case BFD_RELOC_MIPS16_HI16_S:
       /* Nothing needed to do. The value comes from the reloc entry */
       break;
 
@@ -11161,47 +11473,13 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       *valP = 0;
       break;
 
-    case BFD_RELOC_PCREL_HI16_S:
-      /* The addend for this is tricky if it is internal, so we just
-	 do everything here rather than in bfd_install_relocation.  */
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
-	break;
-      if (fixP->fx_addsy
-	  && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
-	{
-	  /* For an external symbol adjust by the address to make it
-	     pcrel_offset.  We use the address of the RELLO reloc
-	     which follows this one.  */
-	  *valP += (fixP->fx_next->fx_frag->fr_address
-		    + fixP->fx_next->fx_where);
-	}
-      *valP = ((*valP + 0x8000) >> 16) & 0xffff;
-      if (target_big_endian)
-	buf += 2;
-      md_number_to_chars (buf, *valP, 2);
-      break;
-
-    case BFD_RELOC_PCREL_LO16:
-      /* The addend for this is tricky if it is internal, so we just
-	 do everything here rather than in bfd_install_relocation.  */
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
-	break;
-      if (fixP->fx_addsy
-	  && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
-	*valP += fixP->fx_frag->fr_address + fixP->fx_where;
-      if (target_big_endian)
-	buf += 2;
-      md_number_to_chars (buf, *valP, 2);
-      break;
-
     case BFD_RELOC_64:
       /* This is handled like BFD_RELOC_32, but we output a sign
          extended value if we are only 32 bits.  */
-      if (fixP->fx_done
-	  || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
+      if (fixP->fx_done)
 	{
 	  if (8 <= sizeof (valueT))
-	    md_number_to_chars (buf, *valP, 8);
+	    md_number_to_chars ((char *) buf, *valP, 8);
 	  else
 	    {
 	      valueT hiv;
@@ -11210,9 +11488,9 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 		hiv = 0xffffffff;
 	      else
 		hiv = 0;
-	      md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
+	      md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
 				  *valP, 4);
-	      md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
+	      md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
 				  hiv, 4);
 	    }
 	}
@@ -11222,23 +11500,22 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
     case BFD_RELOC_32:
       /* If we are deleting this reloc entry, we must fill in the
 	 value now.  This can happen if we have a .word which is not
-	 resolved when it appears but is later defined.  We also need
-	 to fill in the value if this is an embedded PIC switch table
-	 entry.  */
-      if (fixP->fx_done
-	  || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
-	md_number_to_chars (buf, *valP, 4);
+	 resolved when it appears but is later defined.   */
+      if (fixP->fx_done)
+	md_number_to_chars ((char *) buf, *valP, 4);
       break;
 
     case BFD_RELOC_16:
       /* If we are deleting this reloc entry, we must fill in the
          value now.  */
-      assert (fixP->fx_size == 2);
       if (fixP->fx_done)
-	md_number_to_chars (buf, *valP, 2);
+	md_number_to_chars ((char *) buf, *valP, 2);
       break;
 
     case BFD_RELOC_LO16:
+    case BFD_RELOC_MIPS16_LO16:
+      /* FIXME: Now that embedded-PIC is gone, some of this code/comment
+	 may be safe to remove, but if so it's not obvious.  */
       /* When handling an embedded PIC switch statement, we can wind
 	 up deleting a LO16 reloc.  See the 'o' case in mips_ip.  */
       if (fixP->fx_done)
@@ -11248,14 +11525,14 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 			  _("relocation overflow"));
 	  if (target_big_endian)
 	    buf += 2;
-	  md_number_to_chars (buf, *valP, 2);
+	  md_number_to_chars ((char *) buf, *valP, 2);
 	}
       break;
 
     case BFD_RELOC_16_PCREL_S2:
       if ((*valP & 0x3) != 0)
 	as_bad_where (fixP->fx_file, fixP->fx_line,
-		      _("Branch to odd address (%lx)"), (long) *valP);
+		      _("Branch to misaligned address (%lx)"), (long) *valP);
 
       /*
        * We need to save the bits in the instruction since fixup_segment()
@@ -11274,13 +11551,13 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       if (*valP + 0x20000 <= 0x3ffff)
 	{
 	  insn |= (*valP >> 2) & 0xffff;
-	  md_number_to_chars (buf, insn, 4);
+	  md_number_to_chars ((char *) buf, insn, 4);
 	}
       else if (mips_pic == NO_PIC
 	       && fixP->fx_done
 	       && fixP->fx_frag->fr_address >= text_section->vma
 	       && (fixP->fx_frag->fr_address
-		   < text_section->vma + text_section->_raw_size)
+		   < text_section->vma + bfd_get_section_size (text_section))
 	       && ((insn & 0xffff0000) == 0x10000000	 /* beq $0,$0 */
 		   || (insn & 0xffff0000) == 0x04010000	 /* bgez $0 */
 		   || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
@@ -11296,7 +11573,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  fixP->fx_done = 0;
 	  fixP->fx_addsy = section_symbol (text_section);
 	  *valP += md_pcrel_from (fixP);
-	  md_number_to_chars (buf, insn, 4);
+	  md_number_to_chars ((char *) buf, insn, 4);
 	}
       else
 	{
@@ -11328,93 +11605,6 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
   fixP->fx_addnumber = *valP;
 }
 
-#if 0
-void
-printInsn (unsigned long oc)
-{
-  const struct mips_opcode *p;
-  int treg, sreg, dreg, shamt;
-  short imm;
-  const char *args;
-  int i;
-
-  for (i = 0; i < NUMOPCODES; ++i)
-    {
-      p = &mips_opcodes[i];
-      if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
-	{
-	  printf ("%08lx %s\t", oc, p->name);
-	  treg = (oc >> 16) & 0x1f;
-	  sreg = (oc >> 21) & 0x1f;
-	  dreg = (oc >> 11) & 0x1f;
-	  shamt = (oc >> 6) & 0x1f;
-	  imm = oc;
-	  for (args = p->args;; ++args)
-	    {
-	      switch (*args)
-		{
-		case '\0':
-		  printf ("\n");
-		  break;
-
-		case ',':
-		case '(':
-		case ')':
-		  printf ("%c", *args);
-		  continue;
-
-		case 'r':
-		  assert (treg == sreg);
-		  printf ("$%d,$%d", treg, sreg);
-		  continue;
-
-		case 'd':
-		case 'G':
-		  printf ("$%d", dreg);
-		  continue;
-
-		case 't':
-		case 'E':
-		  printf ("$%d", treg);
-		  continue;
-
-		case 'k':
-		  printf ("0x%x", treg);
-		  continue;
-
-		case 'b':
-		case 's':
-		  printf ("$%d", sreg);
-		  continue;
-
-		case 'a':
-		  printf ("0x%08lx", oc & 0x1ffffff);
-		  continue;
-
-		case 'i':
-		case 'j':
-		case 'o':
-		case 'u':
-		  printf ("%d", imm);
-		  continue;
-
-		case '<':
-		case '>':
-		  printf ("$%d", shamt);
-		  continue;
-
-		default:
-		  internalError ();
-		}
-	      break;
-	    }
-	  return;
-	}
-    }
-  printf (_("%08lx  UNDEFINED\n"), oc);
-}
-#endif
-
 static symbolS *
 get_symbol (void)
 {
@@ -11435,7 +11625,7 @@ get_symbol (void)
 static void
 mips_align (int to, int fill, symbolS *label)
 {
-  mips_emit_delays (FALSE);
+  mips_emit_delays ();
   frag_align (to, fill, 0);
   record_alignment (now_seg, to);
   if (label != NULL)
@@ -11497,25 +11687,11 @@ s_align (int x ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
-void
-mips_flush_pending_output (void)
-{
-  mips_emit_delays (FALSE);
-  mips_clear_insn_labels ();
-}
-
 static void
 s_change_sec (int sec)
 {
   segT seg;
 
-  /* When generating embedded PIC code, we only use the .text, .lit8,
-     .sdata and .sbss sections.  We change the .data and .rdata
-     pseudo-ops to use .sdata.  */
-  if (mips_pic == EMBEDDED_PIC
-      && (sec == 'd' || sec == 'r'))
-    sec = 's';
-
 #ifdef OBJ_ELF
   /* The ELF backend needs to know that we are changing sections, so
      that .previous works correctly.  We could do something like check
@@ -11526,7 +11702,7 @@ s_change_sec (int sec)
   obj_elf_section_change_hook ();
 #endif
 
-  mips_emit_delays (FALSE);
+  mips_emit_delays ();
   switch (sec)
     {
     case 't':
@@ -11541,52 +11717,30 @@ s_change_sec (int sec)
       break;
 
     case 'r':
-      if (USE_GLOBAL_POINTER_OPT)
-	{
-	  seg = subseg_new (RDATA_SECTION_NAME,
-			    (subsegT) get_absolute_expression ());
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    {
-	      bfd_set_section_flags (stdoutput, seg,
-				     (SEC_ALLOC
-				      | SEC_LOAD
-				      | SEC_READONLY
-				      | SEC_RELOC
-				      | SEC_DATA));
-	      if (strcmp (TARGET_OS, "elf") != 0)
-		record_alignment (seg, 4);
-	    }
-	  demand_empty_rest_of_line ();
-	}
-      else
+      seg = subseg_new (RDATA_SECTION_NAME,
+			(subsegT) get_absolute_expression ());
+      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 	{
-	  as_bad (_("No read only data section in this object file format"));
-	  demand_empty_rest_of_line ();
-	  return;
+	  bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
+						  | SEC_READONLY | SEC_RELOC
+						  | SEC_DATA));
+	  if (strcmp (TARGET_OS, "elf") != 0)
+	    record_alignment (seg, 4);
 	}
+      demand_empty_rest_of_line ();
       break;
 
     case 's':
-      if (USE_GLOBAL_POINTER_OPT)
-	{
-	  seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
-	  if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	    {
-	      bfd_set_section_flags (stdoutput, seg,
-				     SEC_ALLOC | SEC_LOAD | SEC_RELOC
-				     | SEC_DATA);
-	      if (strcmp (TARGET_OS, "elf") != 0)
-		record_alignment (seg, 4);
-	    }
-	  demand_empty_rest_of_line ();
-	  break;
-	}
-      else
+      seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
+      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 	{
-	  as_bad (_("Global pointers not supported; recompile -G 0"));
-	  demand_empty_rest_of_line ();
-	  return;
+	  bfd_set_section_flags (stdoutput, seg,
+				 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
+	  if (strcmp (TARGET_OS, "elf") != 0)
+	    record_alignment (seg, 4);
 	}
+      demand_empty_rest_of_line ();
+      break;
     }
 
   auto_align = 1;
@@ -11679,7 +11833,7 @@ s_cons (int log_size)
   symbolS *label;
 
   label = insn_labels != NULL ? insn_labels->label : NULL;
-  mips_emit_delays (FALSE);
+  mips_emit_delays ();
   if (log_size > 0 && auto_align)
     mips_align (log_size, 0, label);
   mips_clear_insn_labels ();
@@ -11693,7 +11847,7 @@ s_float_cons (int type)
 
   label = insn_labels != NULL ? insn_labels->label : NULL;
 
-  mips_emit_delays (FALSE);
+  mips_emit_delays ();
 
   if (auto_align)
     {
@@ -11722,35 +11876,50 @@ s_mips_globl (int x ATTRIBUTE_UNUSED)
   symbolS *symbolP;
   flagword flag;
 
-  name = input_line_pointer;
-  c = get_symbol_end ();
-  symbolP = symbol_find_or_make (name);
-  *input_line_pointer = c;
-  SKIP_WHITESPACE ();
-
-  /* On Irix 5, every global symbol that is not explicitly labelled as
-     being a function is apparently labelled as being an object.  */
-  flag = BSF_OBJECT;
-
-  if (! is_end_of_line[(unsigned char) *input_line_pointer])
+  do
     {
-      char *secname;
-      asection *sec;
-
-      secname = input_line_pointer;
+      name = input_line_pointer;
       c = get_symbol_end ();
-      sec = bfd_get_section_by_name (stdoutput, secname);
-      if (sec == NULL)
-	as_bad (_("%s: no such section"), secname);
+      symbolP = symbol_find_or_make (name);
+      S_SET_EXTERNAL (symbolP);
+
       *input_line_pointer = c;
+      SKIP_WHITESPACE ();
 
-      if (sec != NULL && (sec->flags & SEC_CODE) != 0)
-	flag = BSF_FUNCTION;
-    }
+      /* On Irix 5, every global symbol that is not explicitly labelled as
+         being a function is apparently labelled as being an object.  */
+      flag = BSF_OBJECT;
 
-  symbol_get_bfdsym (symbolP)->flags |= flag;
+      if (!is_end_of_line[(unsigned char) *input_line_pointer]
+	  && (*input_line_pointer != ','))
+	{
+	  char *secname;
+	  asection *sec;
+
+	  secname = input_line_pointer;
+	  c = get_symbol_end ();
+	  sec = bfd_get_section_by_name (stdoutput, secname);
+	  if (sec == NULL)
+	    as_bad (_("%s: no such section"), secname);
+	  *input_line_pointer = c;
+
+	  if (sec != NULL && (sec->flags & SEC_CODE) != 0)
+	    flag = BSF_FUNCTION;
+	}
+
+      symbol_get_bfdsym (symbolP)->flags |= flag;
+
+      c = *input_line_pointer;
+      if (c == ',')
+	{
+	  input_line_pointer++;
+	  SKIP_WHITESPACE ();
+	  if (is_end_of_line[(unsigned char) *input_line_pointer])
+	    c = '\n';
+	}
+    }
+  while (c == ',');
 
-  S_SET_EXTERNAL (symbolP);
   demand_empty_rest_of_line ();
 }
 
@@ -11782,7 +11951,7 @@ s_option (int x ATTRIBUTE_UNUSED)
       else
 	as_bad (_(".option pic%d not supported"), i);
 
-      if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
+      if (mips_pic == SVR4_PIC)
 	{
 	  if (g_switch_seen && g_switch_value != 0)
 	    as_warn (_("-G may not be used with SVR4 PIC code"));
@@ -11821,22 +11990,13 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 
   if (strcmp (name, "reorder") == 0)
     {
-      if (mips_opts.noreorder && prev_nop_frag != NULL)
-	{
-	  /* If we still have pending nops, we can discard them.  The
-	     usual nop handling will insert any that are still
-	     needed.  */
-	  prev_nop_frag->fr_fix -= (prev_nop_frag_holds
-				    * (mips_opts.mips16 ? 2 : 4));
-	  prev_nop_frag = NULL;
-	}
-      mips_opts.noreorder = 0;
+      if (mips_opts.noreorder)
+	end_noreorder ();
     }
   else if (strcmp (name, "noreorder") == 0)
     {
-      mips_emit_delays (TRUE);
-      mips_opts.noreorder = 1;
-      mips_any_noreorder = 1;
+      if (!mips_opts.noreorder)
+	start_noreorder ();
     }
   else if (strcmp (name, "at") == 0)
     {
@@ -11886,40 +12046,25 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
     mips_opts.ase_mdmx = 1;
   else if (strcmp (name, "nomdmx") == 0)
     mips_opts.ase_mdmx = 0;
+  else if (strcmp (name, "dsp") == 0)
+    mips_opts.ase_dsp = 1;
+  else if (strcmp (name, "nodsp") == 0)
+    mips_opts.ase_dsp = 0;
+  else if (strcmp (name, "mt") == 0)
+    mips_opts.ase_mt = 1;
+  else if (strcmp (name, "nomt") == 0)
+    mips_opts.ase_mt = 0;
   else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
     {
       int reset = 0;
 
       /* Permit the user to change the ISA and architecture on the fly.
 	 Needless to say, misuse can cause serious problems.  */
-      if (strcmp (name, "mips0") == 0)
+      if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
 	{
 	  reset = 1;
 	  mips_opts.isa = file_mips_isa;
-	}
-      else if (strcmp (name, "mips1") == 0)
-	mips_opts.isa = ISA_MIPS1;
-      else if (strcmp (name, "mips2") == 0)
-	mips_opts.isa = ISA_MIPS2;
-      else if (strcmp (name, "mips3") == 0)
-	mips_opts.isa = ISA_MIPS3;
-      else if (strcmp (name, "mips4") == 0)
-	mips_opts.isa = ISA_MIPS4;
-      else if (strcmp (name, "mips5") == 0)
-	mips_opts.isa = ISA_MIPS5;
-      else if (strcmp (name, "mips32") == 0)
-	mips_opts.isa = ISA_MIPS32;
-      else if (strcmp (name, "mips32r2") == 0)
-	mips_opts.isa = ISA_MIPS32R2;
-      else if (strcmp (name, "mips64") == 0)
-	mips_opts.isa = ISA_MIPS64;
-      else if (strcmp (name, "mips64r2") == 0)
-	mips_opts.isa = ISA_MIPS64R2;
-      else if (strcmp (name, "arch=default") == 0)
-	{
-	  reset = 1;
 	  mips_opts.arch = file_mips_arch;
-	  mips_opts.isa = file_mips_isa;
 	}
       else if (strncmp (name, "arch=", 5) == 0)
 	{
@@ -11934,8 +12079,21 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	      mips_opts.isa = p->isa;
 	    }
 	}
+      else if (strncmp (name, "mips", 4) == 0)
+	{
+	  const struct mips_cpu_info *p;
+
+	  p = mips_parse_cpu("internal use", name);
+	  if (!p)
+	    as_bad (_("unknown ISA level %s"), name + 4);
+	  else
+	    {
+	      mips_opts.arch = p->cpu;
+	      mips_opts.isa = p->isa;
+	    }
+	}
       else
-	as_bad (_("unknown ISA level %s"), name + 4);
+	as_bad (_("unknown ISA or architecture %s"), name);
 
       switch (mips_opts.isa)
 	{
@@ -11991,22 +12149,19 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	  /* If we're changing the reorder mode we need to handle
              delay slots correctly.  */
 	  if (s->options.noreorder && ! mips_opts.noreorder)
-	    mips_emit_delays (TRUE);
+	    start_noreorder ();
 	  else if (! s->options.noreorder && mips_opts.noreorder)
-	    {
-	      if (prev_nop_frag != NULL)
-		{
-		  prev_nop_frag->fr_fix -= (prev_nop_frag_holds
-					    * (mips_opts.mips16 ? 2 : 4));
-		  prev_nop_frag = NULL;
-		}
-	    }
+	    end_noreorder ();
 
 	  mips_opts = s->options;
 	  mips_opts_stack = s->next;
 	  free (s);
 	}
     }
+  else if (strcmp (name, "sym32") == 0)
+    mips_opts.sym32 = TRUE;
+  else if (strcmp (name, "nosym32") == 0)
+    mips_opts.sym32 = FALSE;
   else
     {
       as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
@@ -12023,12 +12178,11 @@ s_abicalls (int ignore ATTRIBUTE_UNUSED)
 {
   mips_pic = SVR4_PIC;
   mips_abicalls = TRUE;
-  if (USE_GLOBAL_POINTER_OPT)
-    {
-      if (g_switch_seen && g_switch_value != 0)
-	as_warn (_("-G may not be used with SVR4 PIC code"));
-      g_switch_value = 0;
-    }
+
+  if (g_switch_seen && g_switch_value != 0)
+    as_warn (_("-G may not be used with SVR4 PIC code"));
+  g_switch_value = 0;
+
   bfd_set_gp_size (stdoutput, 0);
   demand_empty_rest_of_line ();
 }
@@ -12041,12 +12195,22 @@ s_abicalls (int ignore ATTRIBUTE_UNUSED)
 	lui	$gp,%hi(_gp_disp)
 	addiu	$gp,$gp,%lo(_gp_disp)
 	addu	$gp,$gp,.cpload argument
-   The .cpload argument is normally $25 == $t9.  */
+   The .cpload argument is normally $25 == $t9.
+
+   The -mno-shared option changes this to:
+	lui	$gp,%hi(__gnu_local_gp)
+	addiu	$gp,$gp,%lo(__gnu_local_gp)
+   and the argument is ignored.  This saves an instruction, but the
+   resulting code is not position independent; it uses an absolute
+   address for __gnu_local_gp.  Thus code assembled with -mno-shared
+   can go into an ordinary executable, but not into a shared library.  */
 
 static void
 s_cpload (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS ex;
+  int reg;
+  int in_shared;
 
   /* If we are not generating SVR4 PIC code, or if this is NewABI code,
      .cpload is ignored.  */
@@ -12060,8 +12224,15 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
   if (mips_opts.noreorder == 0)
     as_warn (_(".cpload not in noreorder section"));
 
+  reg = tc_get_register (0);
+
+  /* If we need to produce a 64-bit address, we are better off using
+     the default instruction sequence.  */
+  in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
+
   ex.X_op = O_symbol;
-  ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
+  ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
+                                         "__gnu_local_gp");
   ex.X_op_symbol = NULL;
   ex.X_add_number = 0;
 
@@ -12072,8 +12243,9 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
   macro_build_lui (&ex, mips_gp_register);
   macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
 	       mips_gp_register, BFD_RELOC_LO16);
-  macro_build (NULL, "addu", "d,v,t", mips_gp_register,
-	       mips_gp_register, tc_get_register (0));
+  if (in_shared)
+    macro_build (NULL, "addu", "d,v,t", mips_gp_register,
+		 mips_gp_register, reg);
   macro_end ();
 
   demand_empty_rest_of_line ();
@@ -12093,14 +12265,19 @@ s_cpload (int ignore ATTRIBUTE_UNUSED)
      lui	$gp, %hi(%neg(%gp_rel(label)))
      addiu	$gp, $gp, %lo(%neg(%gp_rel(label)))
      daddu	$gp, $gp, $reg1
-   $reg1 is normally $25 == $t9.  */
+   $reg1 is normally $25 == $t9.
+
+   The -mno-shared option replaces the last three instructions with
+	lui	$gp,%hi(_gp)
+	addiu	$gp,$gp,%lo(_gp)
+   */
+
 static void
 s_cpsetup (int ignore ATTRIBUTE_UNUSED)
 {
   expressionS ex_off;
   expressionS ex_sym;
   int reg1;
-  char *f;
 
   /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
      We also need NewABI support.  */
@@ -12156,26 +12333,36 @@ s_cpsetup (int ignore ATTRIBUTE_UNUSED)
     macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
 		 mips_gp_register, 0);
 
-  /* Ensure there's room for the next two instructions, so that `f'
-     doesn't end up with an address in the wrong frag.  */
-  frag_grow (8);
-  f = frag_more (0);
-  macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
-  fix_new (frag_now, f - frag_now->fr_literal,
-	   8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
-  fix_new (frag_now, f - frag_now->fr_literal,
-	   4, NULL, 0, 0, BFD_RELOC_HI16_S);
-
-  f = frag_more (0);
-  macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
-	       mips_gp_register, BFD_RELOC_GPREL16);
-  fix_new (frag_now, f - frag_now->fr_literal,
-	   8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
-  fix_new (frag_now, f - frag_now->fr_literal,
-	   4, NULL, 0, 0, BFD_RELOC_LO16);
-
-  macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
-	       mips_gp_register, reg1);
+  if (mips_in_shared || HAVE_64BIT_SYMBOLS)
+    {
+      macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
+		   -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
+		   BFD_RELOC_HI16_S);
+
+      macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
+		   mips_gp_register, -1, BFD_RELOC_GPREL16,
+		   BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
+
+      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
+		   mips_gp_register, reg1);
+    }
+  else
+    {
+      expressionS ex;
+
+      ex.X_op = O_symbol;
+      ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
+      ex.X_op_symbol = NULL;
+      ex.X_add_number = 0;
+
+      /* In ELF, this symbol is implicitly an STT_OBJECT symbol.  */
+      symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
+
+      macro_build_lui (&ex, mips_gp_register);
+      macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
+		   mips_gp_register, BFD_RELOC_LO16);
+    }
+
   macro_end ();
 
   demand_empty_rest_of_line ();
@@ -12304,7 +12491,7 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
     }
 
   label = insn_labels != NULL ? insn_labels->label : NULL;
-  mips_emit_delays (TRUE);
+  mips_emit_delays ();
   if (auto_align)
     mips_align (2, 0, label);
   mips_clear_insn_labels ();
@@ -12340,7 +12527,7 @@ s_gpdword (int ignore ATTRIBUTE_UNUSED)
     }
 
   label = insn_labels != NULL ? insn_labels->label : NULL;
-  mips_emit_delays (TRUE);
+  mips_emit_delays ();
   if (auto_align)
     mips_align (3, 0, label);
   mips_clear_insn_labels ();
@@ -12356,14 +12543,11 @@ s_gpdword (int ignore ATTRIBUTE_UNUSED)
   p = frag_more (8);
   md_number_to_chars (p, 0, 8);
   fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
-	       BFD_RELOC_GPREL32);
+	       BFD_RELOC_GPREL32)->fx_tcbit = 1;
 
   /* GPREL32 composed with 64 gives a 64-bit GP offset.  */
-  ex.X_op = O_absent;
-  ex.X_add_symbol = 0;
-  ex.X_add_number = 0;
-  fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
-	       BFD_RELOC_64);
+  fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
+	   FALSE, BFD_RELOC_64)->fx_tcbit = 1;
 
   demand_empty_rest_of_line ();
 }
@@ -12585,7 +12769,7 @@ nopic_need_relax (symbolS *sym, int before_relaxing)
   if (sym == 0)
     return 0;
 
-  if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
+  if (g_switch_value > 0)
     {
       const char *symname;
       int change;
@@ -12692,9 +12876,7 @@ pic_need_relax (symbolS *sym, asection *segtype)
 #ifdef OBJ_ELF
 	  /* A global or weak symbol is treated as external.  */
 	  && (OUTPUT_FLAVOR != bfd_target_elf_flavour
-	      || (! S_IS_WEAK (sym)
-		  && (! S_IS_EXTERNAL (sym)
-		      || mips_pic == EMBEDDED_PIC)))
+	      || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
 #endif
 	  );
 }
@@ -12989,6 +13171,9 @@ md_estimate_size_before_relax (fragS *fragp, asection *segtype)
     change = nopic_need_relax (fragp->fr_symbol, 0);
   else if (mips_pic == SVR4_PIC)
     change = pic_need_relax (fragp->fr_symbol, segtype);
+  else if (mips_pic == VXWORKS_PIC)
+    /* For vxworks, GOT16 relocations never have a corresponding LO16.  */
+    change = 0;
   else
     abort ();
 
@@ -13002,15 +13187,13 @@ md_estimate_size_before_relax (fragS *fragp, asection *segtype)
 }
 
 /* This is called to see whether a reloc against a defined symbol
-   should be converted into a reloc against a section.  Don't adjust
-   MIPS16 jump relocations, so we don't have to worry about the format
-   of the offset in the .o file.  Don't adjust relocations against
-   mips16 symbols, so that the linker can find them if it needs to set
-   up a stub.  */
+   should be converted into a reloc against a section.  */
 
 int
 mips_fix_adjustable (fixS *fixp)
 {
+  /* Don't adjust MIPS16 jump relocations, so we don't have to worry
+     about the format of the offset in the .o file. */
   if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
     return 0;
 
@@ -13021,7 +13204,30 @@ mips_fix_adjustable (fixS *fixp)
   if (fixp->fx_addsy == NULL)
     return 1;
 
+  /* If symbol SYM is in a mergeable section, relocations of the form
+     SYM + 0 can usually be made section-relative.  The mergeable data
+     is then identified by the section offset rather than by the symbol.
+
+     However, if we're generating REL LO16 relocations, the offset is split
+     between the LO16 and parterning high part relocation.  The linker will
+     need to recalculate the complete offset in order to correctly identify
+     the merge data.
+
+     The linker has traditionally not looked for the parterning high part
+     relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
+     placed anywhere.  Rather than break backwards compatibility by changing
+     this, it seems better not to force the issue, and instead keep the
+     original symbol.  This will work with either linker behavior.  */
+  if ((fixp->fx_r_type == BFD_RELOC_LO16
+       || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16
+       || reloc_needs_lo_p (fixp->fx_r_type))
+      && HAVE_IN_PLACE_ADDENDS
+      && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
+    return 0;
+
 #ifdef OBJ_ELF
+  /* Don't adjust relocations against mips16 symbols, so that the linker
+     can find them if it needs to set up a stub.  */
   if (OUTPUT_FLAVOR == bfd_target_elf_flavour
       && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
       && fixp->fx_subsy == NULL)
@@ -13047,56 +13253,20 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
-  if (mips_pic == EMBEDDED_PIC
-      && SWITCH_TABLE (fixp))
-    {
-      /* For a switch table entry we use a special reloc.  The addend
-	 is actually the difference between the reloc address and the
-	 subtrahend.  */
-      reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
-      if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
-	as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
-      fixp->fx_r_type = BFD_RELOC_GPREL32;
-    }
-  else if (fixp->fx_pcrel)
+  if (fixp->fx_pcrel)
     {
-      bfd_vma pcrel_address;
+      assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
 
-      /* Set PCREL_ADDRESS to this relocation's "PC".  The PC for high
-	 high-part relocs is the address of the low-part reloc.  */
-      if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
-	{
-	  assert (fixp->fx_next != NULL
-		  && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
-	  pcrel_address = (fixp->fx_next->fx_where
-			   + fixp->fx_next->fx_frag->fr_address);
-	}
-      else
-	pcrel_address = reloc->address;
-
-      if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
-	{
-	  /* At this point, fx_addnumber is "symbol offset - pcrel_address".
-	     Relocations want only the symbol offset.  */
-	  reloc->addend = fixp->fx_addnumber + pcrel_address;
-	}
-      else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
-	       || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
-	{
-	  /* We use a special addend for an internal RELLO or RELHI reloc.  */
-	  if (symbol_section_p (fixp->fx_addsy))
-	    reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
-	  else
-	    reloc->addend = fixp->fx_addnumber + pcrel_address;
-	}
-      else
+      /* At this point, fx_addnumber is "symbol offset - pcrel address".
+	 Relocations want only the symbol offset.  */
+      reloc->addend = fixp->fx_addnumber + reloc->address;
+      if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
 	{
-	  if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
-	    /* A gruesome hack which is a result of the gruesome gas reloc
-	       handling.  */
-	    reloc->addend = pcrel_address;
-	  else
-	    reloc->addend = -pcrel_address;
+	  /* A gruesome hack which is a result of the gruesome gas
+	     reloc handling.  What's worse, for COFF (as opposed to
+	     ECOFF), we might need yet another copy of reloc->address.
+	     See bfd_install_relocation.  */
+	  reloc->addend += reloc->address;
 	}
     }
   else
@@ -13110,53 +13280,9 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
       reloc->addend = 0;
     }
 
-  /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
-     fixup_segment converted a non-PC relative reloc into a PC
-     relative reloc.  In such a case, we need to convert the reloc
-     code.  */
   code = fixp->fx_r_type;
-  if (fixp->fx_pcrel)
-    {
-      switch (code)
-	{
-	case BFD_RELOC_8:
-	  code = BFD_RELOC_8_PCREL;
-	  break;
-	case BFD_RELOC_16:
-	  code = BFD_RELOC_16_PCREL;
-	  break;
-	case BFD_RELOC_32:
-	  code = BFD_RELOC_32_PCREL;
-	  break;
-	case BFD_RELOC_64:
-	  code = BFD_RELOC_64_PCREL;
-	  break;
-	case BFD_RELOC_8_PCREL:
-	case BFD_RELOC_16_PCREL:
-	case BFD_RELOC_32_PCREL:
-	case BFD_RELOC_64_PCREL:
-	case BFD_RELOC_16_PCREL_S2:
-	case BFD_RELOC_PCREL_HI16_S:
-	case BFD_RELOC_PCREL_LO16:
-	  break;
-	default:
-	  as_bad_where (fixp->fx_file, fixp->fx_line,
-			_("Cannot make %s relocation PC relative"),
-			bfd_get_reloc_code_name (code));
-	}
-    }
-
-  /* To support a PC relative reloc when generating embedded PIC code
-     for ECOFF, we use a Cygnus extension.  We check for that here to
-     make sure that we don't let such a reloc escape normally.  */
-  if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
-       || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-      && code == BFD_RELOC_16_PCREL_S2
-      && mips_pic != EMBEDDED_PIC)
-    reloc->howto = NULL;
-  else
-    reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
 
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
   if (reloc->howto == NULL)
     {
       as_bad_where (fixp->fx_file, fixp->fx_line,
@@ -13233,12 +13359,11 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  exp.X_add_number = fragp->fr_offset;
 
 	  fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
-			      4, &exp, 1,
-			      BFD_RELOC_16_PCREL_S2);
+			      4, &exp, 1, BFD_RELOC_16_PCREL_S2);
 	  fixp->fx_file = fragp->fr_file;
 	  fixp->fx_line = fragp->fr_line;
 
-	  md_number_to_chars (buf, insn, 4);
+	  md_number_to_chars ((char *) buf, insn, 4);
 	  buf += 4;
 	}
       else
@@ -13310,11 +13435,11 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	  i--;
 	  insn |= i;
 	  /* Branch over the jump.  */
-	  md_number_to_chars (buf, insn, 4);
+	  md_number_to_chars ((char *) buf, insn, 4);
 	  buf += 4;
 
 	  /* Nop */
-	  md_number_to_chars (buf, 0, 4);
+	  md_number_to_chars ((char *) buf, 0, 4);
 	  buf += 4;
 
 	  if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
@@ -13333,10 +13458,10 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 		 delay slot.  */
 
 	      insn |= i;
-	      md_number_to_chars (buf, insn, 4);
+	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 
-	      md_number_to_chars (buf, 0, 4);
+	      md_number_to_chars ((char *) buf, 0, 4);
 	      buf += 4;
 	    }
 
@@ -13355,7 +13480,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
-	      md_number_to_chars (buf, insn, 4);
+	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 	    }
 	  else
@@ -13377,13 +13502,13 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
-	      md_number_to_chars (buf, insn, 4);
+	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 
 	      if (mips_opts.isa == ISA_MIPS1)
 		{
 		  /* nop */
-		  md_number_to_chars (buf, 0, 4);
+		  md_number_to_chars ((char *) buf, 0, 4);
 		  buf += 4;
 		}
 
@@ -13395,7 +13520,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      fixp->fx_file = fragp->fr_file;
 	      fixp->fx_line = fragp->fr_line;
 
-	      md_number_to_chars (buf, insn, 4);
+	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 
 	      /* j(al)r $at.  */
@@ -13404,7 +13529,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 	      else
 		insn = 0x00200008;
 
-	      md_number_to_chars (buf, insn, 4);
+	      md_number_to_chars ((char *) buf, insn, 4);
 	      buf += 4;
 	    }
 	}
@@ -13497,12 +13622,12 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
 
       if (use_extend)
 	{
-	  md_number_to_chars (buf, 0xf000 | extend, 2);
+	  md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
 	  fragp->fr_fix += 2;
 	  buf += 2;
 	}
 
-      md_number_to_chars (buf, insn, 2);
+      md_number_to_chars ((char *) buf, insn, 2);
       fragp->fr_fix += 2;
       buf += 2;
     }
@@ -13615,6 +13740,10 @@ mips_define_label (symbolS *sym)
   l->label = sym;
   l->next = insn_labels;
   insn_labels = l;
+
+#ifdef OBJ_ELF
+  dwarf2_emit_label (sym);
+#endif
 }
 
 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
@@ -13670,6 +13799,10 @@ mips_elf_final_processing (void)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
 
   /* Set MIPS ELF flags for ASEs.  */
+  /* We may need to define a new flag for DSP ASE, and set this flag when
+     file_ase_dsp is true.  */
+  /* We may need to define a new flag for MT ASE, and set this flag when
+     file_ase_mt is true.  */
   if (file_ase_mips16)
     elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
 #if 0 /* XXX FIXME */
@@ -13703,7 +13836,8 @@ mips_elf_final_processing (void)
 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */
 
 typedef struct proc {
-  symbolS *isym;
+  symbolS *func_sym;
+  symbolS *func_end_sym;
   unsigned long reg_mask;
   unsigned long reg_offset;
   unsigned long fpreg_mask;
@@ -13840,7 +13974,7 @@ s_mips_file (int x ATTRIBUTE_UNUSED)
       if (filename != NULL && ! first_file_directive)
 	{
 	  (void) new_logical_line (filename, -1);
-	  s_app_file_string (filename);
+	  s_app_file_string (filename, 0);
 	}
       first_file_directive = 1;
     }
@@ -13887,7 +14021,7 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
   if (p != NULL)
     {
       assert (S_GET_NAME (p));
-      if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
+      if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
 	as_warn (_(".end symbol does not match .ent symbol."));
 
       if (debug_type == DEBUG_STABS)
@@ -13898,6 +14032,21 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
     as_warn (_(".end directive missing or unknown symbol"));
 
 #ifdef OBJ_ELF
+  /* Create an expression to calculate the size of the function.  */
+  if (p && cur_proc_ptr)
+    {
+      OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
+      expressionS *exp = xmalloc (sizeof (expressionS));
+
+      obj->size = exp;
+      exp->X_op = O_subtract;
+      exp->X_add_symbol = symbol_temp_new_now ();
+      exp->X_op_symbol = p;
+      exp->X_add_number = 0;
+
+      cur_proc_ptr->func_end_sym = exp->X_add_symbol;
+    }
+
   /* Generate a .pdr section.  */
   if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
       && mips_flag_pdr)
@@ -13970,7 +14119,7 @@ s_mips_ent (int aent)
       cur_proc_ptr = &cur_proc;
       memset (cur_proc_ptr, '\0', sizeof (procS));
 
-      cur_proc_ptr->isym = symbolP;
+      cur_proc_ptr->func_sym = symbolP;
 
       symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
 
@@ -14076,29 +14225,6 @@ s_mips_mask (int reg_type)
     s_ignore (reg_type);
 }
 
-/* The .loc directive.  */
-
-#if 0
-static void
-s_loc (int x)
-{
-  symbolS *symbolP;
-  int lineno;
-  int addroff;
-
-  assert (now_seg == text_section);
-
-  lineno = get_number ();
-  addroff = frag_now_fix ();
-
-  symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
-  S_SET_TYPE (symbolP, N_SLINE);
-  S_SET_OTHER (symbolP, 0);
-  S_SET_DESC (symbolP, lineno);
-  symbolP->sy_segment = now_seg;
-}
-#endif
-
 /* A table describing all the processors gas knows about.  Names are
    matched in the order listed.
 
@@ -14152,15 +14278,23 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "rm5261",         0,      ISA_MIPS4,      CPU_R5000 },
   { "rm5721",         0,      ISA_MIPS4,      CPU_R5000 },
   { "rm7000",         0,      ISA_MIPS4,      CPU_RM7000 },
-  { "rm9000",         0,      ISA_MIPS4,      CPU_RM7000 },
+  { "rm9000",         0,      ISA_MIPS4,      CPU_RM9000 },
 
   /* MIPS 32 */
   { "4kc",            0,      ISA_MIPS32,     CPU_MIPS32 },
   { "4km",            0,      ISA_MIPS32,     CPU_MIPS32 },
   { "4kp",            0,      ISA_MIPS32,     CPU_MIPS32 },
 
+  /* MIPS32 Release 2 */
+  { "m4k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24k",            0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kc",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kf",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+  { "24kx",           0,      ISA_MIPS32R2,   CPU_MIPS32R2 },
+
   /* MIPS 64 */
   { "5kc",            0,      ISA_MIPS64,     CPU_MIPS64 },
+  { "5kf",            0,      ISA_MIPS64,     CPU_MIPS64 },
   { "20kc",           0,      ISA_MIPS64,     CPU_MIPS64 },
 
   /* Broadcom SB-1 CPU core */
@@ -14332,7 +14466,6 @@ md_show_usage (FILE *stream)
 
   fprintf (stream, _("\
 MIPS options:\n\
--membedded-pic		generate embedded position independent code\n\
 -EB			generate big endian output\n\
 -EL			generate little endian output\n\
 -g, -g2			do not remove unneeded NOPs or swap branches\n\
@@ -14374,9 +14507,18 @@ MIPS options:\n\
 -mips16			generate mips16 instructions\n\
 -no-mips16		do not generate mips16 instructions\n"));
   fprintf (stream, _("\
+-mdsp			generate DSP instructions\n\
+-mno-dsp		do not generate DSP instructions\n"));
+  fprintf (stream, _("\
+-mmt			generate MT instructions\n\
+-mno-mt			do not generate MT instructions\n"));
+  fprintf (stream, _("\
 -mfix-vr4120		work around certain VR4120 errata\n\
+-mfix-vr4130		work around VR4130 mflo/mfhi errata\n\
 -mgp32			use 32-bit GPRs, regardless of the chosen ISA\n\
 -mfp32			use 32-bit FPRs, regardless of the chosen ISA\n\
+-mno-shared		optimize output for executables\n\
+-msym32			assume all symbols have 32-bit values\n\
 -O0			remove unneeded NOPs, do not swap branches\n\
 -O			remove unneeded NOPs and swap branches\n\
 --[no-]construct-floats [dis]allow floating point values to be constructed\n\
@@ -14388,6 +14530,8 @@ MIPS options:\n\
 -non_shared		do not generate position independent code\n\
 -xgot			assume a 32 bit GOT\n\
 -mpdr, -mno-pdr		enable/disable creation of .pdr sections\n\
+-mshared, -mno-shared   disable/enable .cpload optimization for\n\
+                        non-shared code\n\
 -mabi=ABI		create ABI conformant object file for:\n"));
 
   first = 1;
@@ -14430,3 +14574,11 @@ mips_dwarf2_addr_size (void)
   else
     return 4;
 }
+
+/* Standard calling conventions leave the CFA at SP on entry.  */
+void
+mips_cfi_frame_initial_instructions (void)
+{
+  cfi_add_CFA_def_cfa_register (SP);
+}
+
diff --git a/gas/config/tc-mips.h b/gas/config/tc-mips.h
index 46a765369a16..5665d3decdd7 100644
--- a/gas/config/tc-mips.h
+++ b/gas/config/tc-mips.h
@@ -1,5 +1,5 @@
 /* tc-mips.h -- header file for tc-mips.c.
-   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003
+   Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
    Contributed by the OSF and Ralph Campbell.
    Written by Keith Knowles and Ralph Campbell, working independently.
@@ -19,8 +19,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef TC_MIPS
 #define TC_MIPS
@@ -58,10 +58,6 @@ extern void mips_handle_align (struct frag *);
 
 #define MAX_MEM_FOR_RS_ALIGN_CODE  (1 + 2)
 
-/* We permit PC relative difference expressions when generating
-   embedded PIC code.  */
-#define DIFF_EXPR_OK
-
 /* Tell assembler that we have an itbl_mips.h header file to include.  */
 #define HAVE_ITBL_CPU
 
@@ -80,24 +76,12 @@ enum mips_pic_level
   /* Generate PIC code as in the SVR4 MIPS ABI.  */
   SVR4_PIC,
 
-  /* Generate PIC code without using a global offset table: the data
-     segment has a maximum size of 64K, all data references are off
-     the $gp register, and all text references are PC relative.  This
-     is used on some embedded systems.  */
-  EMBEDDED_PIC
+  /* VxWorks's PIC model.  */
+  VXWORKS_PIC
 };
 
 extern enum mips_pic_level mips_pic;
 
-struct mips_cl_insn
-{
-  unsigned long insn_opcode;
-  const struct mips_opcode *insn_mo;
-  /* The next two fields are used when generating mips16 code.  */
-  bfd_boolean use_extend;
-  unsigned short extend;
-};
-
 extern int tc_get_register (int frame);
 
 #define md_after_parse_args() mips_after_parse_args()
@@ -126,32 +110,21 @@ extern void mips_frob_file_after_relocs (void);
 #define tc_fix_adjustable(fixp) mips_fix_adjustable (fixp)
 extern int mips_fix_adjustable (struct fix *);
 
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-/* Global syms must not be resolved, to support ELF shared libraries.
-   When generating embedded code, we don't have shared libs.  */
+/* Global syms must not be resolved, to support ELF shared libraries.  */
 #define EXTERN_FORCE_RELOC			\
-  (OUTPUT_FLAVOR == bfd_target_elf_flavour	\
-   && mips_pic != EMBEDDED_PIC)
+  (OUTPUT_FLAVOR == bfd_target_elf_flavour)
 
-/* When generating embedded PIC code we must keep PC relative
-   relocations.  */
+/* When generating NEWABI code, we may need to have to keep combined
+   relocations which don't have symbols.  */
 #define TC_FORCE_RELOCATION(FIX) mips_force_relocation (FIX)
 extern int mips_force_relocation (struct fix *);
 
 #define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \
   (! SEG_NORMAL (SEG) || mips_force_relocation (FIX))
 
-/* We use this to turn branches to global symbols into branches to
-   local symbols, so that they can be simplified.  */
-#define TC_VALIDATE_FIX(fixp, this_segment, skip_label) \
-  do \
-    if (! mips_validate_fix ((fixp), (this_segment))) \
-      goto skip_label; \
-  while (0)
-extern int mips_validate_fix (struct fix *, asection *);
-
 /* Register mask variables.  These are set by the MIPS assembly code
    and used by ECOFF and possibly other object file formats.  */
 extern unsigned long mips_gprmask;
@@ -167,15 +140,11 @@ extern void mips_elf_final_processing (void);
 extern void md_mips_end (void);
 #define md_end()	md_mips_end()
 
-#define USE_GLOBAL_POINTER_OPT	(OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
-				 || OUTPUT_FLAVOR == bfd_target_coff_flavour \
-				 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
-
 extern void mips_pop_insert (void);
 #define md_pop_insert()		mips_pop_insert()
 
-extern void mips_flush_pending_output (void);
-#define md_flush_pending_output mips_flush_pending_output
+extern void mips_emit_delays (void);
+#define md_flush_pending_output mips_emit_delays
 
 extern void mips_enable_auto_align (void);
 #define md_elf_section_change_hook()	mips_enable_auto_align()
@@ -183,6 +152,15 @@ extern void mips_enable_auto_align (void);
 extern enum dwarf2_format mips_dwarf2_format (void);
 #define DWARF2_FORMAT() mips_dwarf2_format ()
 
+extern int mips_dwarf2_addr_size (void);
 #define DWARF2_ADDR_SIZE(bfd) mips_dwarf2_addr_size ()
 
+#define TARGET_USE_CFIPOP 1
+
+#define tc_cfi_frame_initial_instructions mips_cfi_frame_initial_instructions
+extern void mips_cfi_frame_initial_instructions (void);
+
+#define DWARF2_DEFAULT_RETURN_COLUMN 31
+#define DWARF2_CIE_DATA_ALIGNMENT -4
+
 #endif /* TC_MIPS */
diff --git a/gas/config/tc-mmix.c b/gas/config/tc-mmix.c
index dddc20a622bc..c1a8d536b18c 100644
--- a/gas/config/tc-mmix.c
+++ b/gas/config/tc-mmix.c
@@ -1,5 +1,5 @@
 /* tc-mmix.c -- Assembler for Don Knuth's MMIX.
-   Copyright (C) 2001, 2002, 2003 Free Software Foundation.
+   Copyright (C) 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* Knuth's assembler mmixal does not provide a relocatable format; mmo is
    to be considered a final link-format.  In the final link, we make mmo,
@@ -47,27 +47,25 @@ enum mmix_fixup_action
    mmix_fixup_register_or_adjust_for_byte
  };
 
-static int get_spec_regno PARAMS ((char *));
-static int get_operands PARAMS ((int, char *, expressionS[]));
-static int get_putget_operands
-  PARAMS ((struct mmix_opcode *, char *, expressionS[]));
-static void s_prefix PARAMS ((int));
-static void s_greg PARAMS ((int));
-static void s_loc PARAMS ((int));
-static void s_bspec PARAMS ((int));
-static void s_espec PARAMS ((int));
-static void mmix_s_local PARAMS ((int));
-static void mmix_greg_internal PARAMS ((char *));
-static void mmix_set_geta_branch_offset PARAMS ((char *, offsetT value));
-static void mmix_set_jmp_offset PARAMS ((char *, offsetT));
-static void mmix_fill_nops PARAMS ((char *, int));
-static int cmp_greg_symbol_fixes PARAMS ((const PTR, const PTR));
-static int cmp_greg_val_greg_symbol_fixes
-  PARAMS ((const PTR p1, const PTR p2));
-static void mmix_handle_rest_of_empty_line PARAMS ((void));
-static void mmix_discard_rest_of_line PARAMS ((void));
-static void mmix_byte PARAMS ((void));
-static void mmix_cons PARAMS ((int));
+static int get_spec_regno (char *);
+static int get_operands (int, char *, expressionS *);
+static int get_putget_operands (struct mmix_opcode *, char *, expressionS *);
+static void s_prefix (int);
+static void s_greg (int);
+static void s_loc (int);
+static void s_bspec (int);
+static void s_espec (int);
+static void mmix_s_local (int);
+static void mmix_greg_internal (char *);
+static void mmix_set_geta_branch_offset (char *, offsetT);
+static void mmix_set_jmp_offset (char *, offsetT);
+static void mmix_fill_nops (char *, int);
+static int cmp_greg_symbol_fixes (const void *, const void *);
+static int cmp_greg_val_greg_symbol_fixes (const void *, const void *);
+static void mmix_handle_rest_of_empty_line (void);
+static void mmix_discard_rest_of_line (void);
+static void mmix_byte (void);
+static void mmix_cons (int);
 
 /* Continue the tradition of symbols.c; use control characters to enforce
    magic.  These are used when replacing e.g. 8F and 8B so we can handle
@@ -301,22 +299,9 @@ struct obstack mmix_sym_obstack;
 #define PUSHJ_4B GETA_3B
 
 /* We'll very rarely have sections longer than LONG_MAX, but we'll make a
-   feeble attempt at getting 64-bit C99 or gcc-specific values (assuming
-   long long is 64 bits on the host).  */
-#ifdef LLONG_MIN
-#define PUSHJSTUB_MIN LLONG_MIN
-#elsif defined (LONG_LONG_MIN)
-#define PUSHJSTUB_MIN LONG_LONG_MIN
-#else
-#define PUSHJSTUB_MIN LONG_MIN
-#endif
-#ifdef LLONG_MAX
-#define PUSHJSTUB_MAX LLONG_MAX
-#elsif defined (LONG_LONG_MAX)
-#define PUSHJSTUB_MAX LONG_LONG_MAX
-#else
-#define PUSHJSTUB_MAX LONG_MAX
-#endif
+   feeble attempt at getting 64-bit values.  */
+#define PUSHJSTUB_MAX ((offsetT) (((addressT) -1) >> 1))
+#define PUSHJSTUB_MIN (-PUSHJSTUB_MAX - 1)
 
 #define JMP_0F (65536 * 256 * 4 - 8)
 #define JMP_0B (-65536 * 256 * 4 - 4)
@@ -412,9 +397,7 @@ const char mmix_flt_chars[] = "rf";
 /* Fill in the offset-related part of GETA or Bcc.  */
 
 static void
-mmix_set_geta_branch_offset (opcodep, value)
-     char *opcodep;
-     offsetT value;
+mmix_set_geta_branch_offset (char *opcodep, offsetT value)
 {
   if (value < 0)
     {
@@ -429,9 +412,7 @@ mmix_set_geta_branch_offset (opcodep, value)
 /* Fill in the offset-related part of JMP.  */
 
 static void
-mmix_set_jmp_offset (opcodep, value)
-     char *opcodep;
-     offsetT value;
+mmix_set_jmp_offset (char *opcodep, offsetT value)
 {
   if (value < 0)
     {
@@ -446,9 +427,7 @@ mmix_set_jmp_offset (opcodep, value)
 /* Fill in NOP:s for the expanded part of GETA/JMP/Bcc/PUSHJ.  */
 
 static void
-mmix_fill_nops (opcodep, n)
-     char *opcodep;
-     int n;
+mmix_fill_nops (char *opcodep, int n)
 {
   int i;
 
@@ -459,9 +438,7 @@ mmix_fill_nops (opcodep, n)
 /* See macro md_parse_name in tc-mmix.h.  */
 
 int
-mmix_current_location (fn, exp)
-     void (*fn) PARAMS ((expressionS *));
-     expressionS *exp;
+mmix_current_location (void (*fn) (expressionS *), expressionS *exp)
 {
   (*fn) (exp);
 
@@ -472,10 +449,7 @@ mmix_current_location (fn, exp)
    General idea and code stolen from the tic80 port.  */
 
 static int
-get_operands (max_operands, s, exp)
-     int max_operands;
-     char *s;
-     expressionS exp[];
+get_operands (int max_operands, char *s, expressionS *exp)
 {
   char *p = s;
   int numexp = 0;
@@ -541,8 +515,7 @@ get_operands (max_operands, s, exp)
    one.  NAME is a null-terminated string.  */
 
 static int
-get_spec_regno (name)
-     char *name;
+get_spec_regno (char *name)
 {
   int i;
 
@@ -564,10 +537,8 @@ get_spec_regno (name)
 /* For GET and PUT, parse the register names "manually", so we don't use
    user labels.  */
 static int
-get_putget_operands (insn, operands, exp)
-     struct mmix_opcode *insn;
-     char *operands;
-     expressionS exp[];
+get_putget_operands (struct mmix_opcode *insn, char *operands,
+		     expressionS *exp)
 {
   expressionS *expp_reg;
   expressionS *expp_sreg;
@@ -661,9 +632,7 @@ get_putget_operands (insn, operands, exp)
 /* Handle MMIX-specific option.  */
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -720,8 +689,7 @@ md_parse_option (c, arg)
 /* Display MMIX-specific help text.  */
 
 void
-md_show_usage (stream)
-     FILE * stream;
+md_show_usage (FILE * stream)
 {
   fprintf (stream, _(" MMIX-specific command line options:\n"));
   fprintf (stream, _("\
@@ -754,7 +722,7 @@ md_show_usage (stream)
 /* Step to end of line, but don't step over the end of the line.  */
 
 static void
-mmix_discard_rest_of_line ()
+mmix_discard_rest_of_line (void)
 {
   while (*input_line_pointer
 	 && (! is_end_of_line[(unsigned char) *input_line_pointer]
@@ -767,7 +735,7 @@ mmix_discard_rest_of_line ()
    delimiter).  */
 
 static void
-mmix_handle_rest_of_empty_line ()
+mmix_handle_rest_of_empty_line (void)
 {
   if (mmix_gnu_syntax)
     demand_empty_rest_of_line ();
@@ -781,7 +749,7 @@ mmix_handle_rest_of_empty_line ()
 /* Initialize GAS MMIX specifics.  */
 
 void
-mmix_md_begin ()
+mmix_md_begin (void)
 {
   int i;
   const struct mmix_opcode *opcode;
@@ -840,8 +808,7 @@ mmix_md_begin ()
 /* Assemble one insn in STR.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *operands = str;
   char modified_char = 0;
@@ -1922,8 +1889,7 @@ md_assemble (str)
    tc_unrecognized_line too, through this function.  */
 
 int
-mmix_assemble_return_nonzero (str)
-     char *str;
+mmix_assemble_return_nonzero (char *str)
 {
   int last_error_count = had_errors ();
   char *s2 = str;
@@ -1952,8 +1918,7 @@ mmix_assemble_return_nonzero (str)
 /* The PREFIX pseudo.  */
 
 static void
-s_prefix (unused)
-     int unused ATTRIBUTE_UNUSED;
+s_prefix (int unused ATTRIBUTE_UNUSED)
 {
   char *p;
   int c;
@@ -1995,8 +1960,7 @@ s_prefix (unused)
    that.  (It might be worth a rewrite for other reasons, though).  */
 
 char *
-mmix_prefix_name (shortname)
-     char *shortname;
+mmix_prefix_name (char *shortname)
 {
   if (*shortname == ':')
     return shortname + 1;
@@ -2020,8 +1984,7 @@ mmix_prefix_name (shortname)
    be persistent, perhaps allocated on an obstack.  */
 
 static void
-mmix_greg_internal (label)
-     char *label;
+mmix_greg_internal (char *label)
 {
   expressionS *expP = &mmix_raw_gregs[n_of_raw_gregs].exp;
 
@@ -2057,8 +2020,7 @@ mmix_greg_internal (label)
 /* The ".greg label,expr" worker.  */
 
 static void
-s_greg (unused)
-     int unused ATTRIBUTE_UNUSED;
+s_greg (int unused ATTRIBUTE_UNUSED)
 {
   char *p;
   char c;
@@ -2087,8 +2049,7 @@ s_greg (unused)
 /* The "BSPEC expr" worker.  */
 
 static void
-s_bspec (unused)
-     int unused ATTRIBUTE_UNUSED;
+s_bspec (int unused ATTRIBUTE_UNUSED)
 {
   asection *expsec;
   asection *sec;
@@ -2153,8 +2114,7 @@ s_bspec (unused)
 /* The "ESPEC" worker.  */
 
 static void
-s_espec (unused)
-     int unused ATTRIBUTE_UNUSED;
+s_espec (int unused ATTRIBUTE_UNUSED)
 {
   /* First, check that we *do* have a BSPEC in progress.  */
   if (! doing_bspec)
@@ -2177,8 +2137,7 @@ s_espec (unused)
    Implementing this by means of contents in a section lost.  */
 
 static void
-mmix_s_local (unused)
-     int unused ATTRIBUTE_UNUSED;
+mmix_s_local (int unused ATTRIBUTE_UNUSED)
 {
   expressionS exp;
 
@@ -2208,9 +2167,7 @@ mmix_s_local (unused)
    function may be called multiple times.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP;
-     segT    segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
 {
   int length;
 
@@ -2281,10 +2238,7 @@ md_estimate_size_before_relax (fragP, segment)
    OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -2327,10 +2281,8 @@ md_atof (type, litP, sizeP)
 /* Convert variable-sized frags into one or more fixups.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
   /* Pointer to first byte in variable-sized part of the frag.  */
   char *var_partp;
@@ -2413,7 +2365,7 @@ md_convert_frag (abfd, sec, fragP)
       if (fragP->tc_frag_data == NULL)
 	{
 	  /* We must initialize data that's supposed to be "fixed up" to
-	     avoid emitting garbage, because md_apply_fix3 won't do
+	     avoid emitting garbage, because md_apply_fix won't do
 	     anything for undefined symbols.  */
 	  md_number_to_chars (var_partp, 0, 8);
 	  tmpfixP
@@ -2461,10 +2413,7 @@ md_convert_frag (abfd, sec, fragP)
    Note that this function isn't called when linkrelax != 0.  */
 
 void
-md_apply_fix3 (fixP, valP, segment)
-     fixS *   fixP;
-     valueT * valP;
-     segT     segment;
+md_apply_fix (fixS *fixP, valueT *valP, segT segment)
 {
   char *buf  = fixP->fx_where + fixP->fx_frag->fr_literal;
   /* Note: use offsetT because it is signed, valueT is unsigned.  */
@@ -2638,9 +2587,7 @@ md_apply_fix3 (fixP, valP, segment)
    definitions.  */
 
 static int
-cmp_greg_val_greg_symbol_fixes (p1, p2)
-     const PTR p1;
-     const PTR p2;
+cmp_greg_val_greg_symbol_fixes (const void *p1, const void *p2)
 {
   offsetT val1 = *(offsetT *) p1;
   offsetT val2 = ((struct mmix_symbol_greg_fixes *) p2)->offs;
@@ -2657,9 +2604,7 @@ cmp_greg_val_greg_symbol_fixes (p1, p2)
 /* Generate a machine-dependent relocation.  */
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
 {
   bfd_signed_vma val
     = fixP->fx_offset
@@ -2707,7 +2652,7 @@ tc_gen_reloc (section, fixP)
 
       if (addsy == NULL || bfd_is_abs_section (addsec))
 	{
-	  /* Resolve this reloc now, as md_apply_fix3 would have done (not
+	  /* Resolve this reloc now, as md_apply_fix would have done (not
 	     called if -linkrelax).  There is no point in keeping a reloc
 	     to an absolute symbol.  No reloc that is subject to
 	     relaxation must be to an absolute symbol; difference
@@ -2907,9 +2852,9 @@ tc_gen_reloc (section, fixP)
 	}
       /* FALLTHROUGH.  */
 
-      /* The others are supposed to be handled by md_apply_fix3.
+      /* The others are supposed to be handled by md_apply_fix.
 	 FIXME: ... which isn't called when -linkrelax.  Move over
-	 md_apply_fix3 code here for everything reasonable.  */
+	 md_apply_fix code here for everything reasonable.  */
     badop:
     default:
       as_bad_where
@@ -2953,10 +2898,10 @@ tc_gen_reloc (section, fixP)
    ugly labels_without_colons etc.  */
 
 void
-mmix_handle_mmixal ()
+mmix_handle_mmixal (void)
 {
-  char *s0 = input_line_pointer;
-  char *s;
+  char *insn;
+  char *s = input_line_pointer;
   char *label = NULL;
   char c;
 
@@ -2966,44 +2911,20 @@ mmix_handle_mmixal ()
   if (mmix_gnu_syntax)
     return;
 
-  /* If the first character is a '.', then it's a pseudodirective, not a
-     label.  Make GAS not handle label-without-colon on this line.  We
-     also don't do mmixal-specific stuff on this line.  */
-  if (input_line_pointer[0] == '.')
-    {
-      label_without_colon_this_line = 0;
-      return;
-    }
-
-  /* Don't handle empty lines here.  */
-  while (1)
-    {
-      if (*s0 == 0 || is_end_of_line[(unsigned int) *s0])
-	return;
-
-      if (! ISSPACE (*s0))
-	break;
-
-      s0++;
-    }
-
   /* If we're on a line with a label, check if it's a mmixal fb-label.
      Save an indicator and skip the label; it must be set only after all
      fb-labels of expressions are evaluated.  */
-  if (ISDIGIT (input_line_pointer[0])
-      && input_line_pointer[1] == 'H'
-      && ISSPACE (input_line_pointer[2]))
+  if (ISDIGIT (s[0]) && s[1] == 'H' && ISSPACE (s[2]))
     {
-      char *s;
-      current_fb_label = input_line_pointer[0] - '0';
+      current_fb_label = s[0] - '0';
 
       /* We have to skip the label, but also preserve the newlineness of
 	 the previous character, since the caller checks that.  It's a
 	 mess we blame on the caller.  */
-      input_line_pointer[1] = input_line_pointer[-1];
-      input_line_pointer += 2;
+      s[1] = s[-1];
+      s += 2;
+      input_line_pointer = s;
 
-      s = input_line_pointer;
       while (*s && ISSPACE (*s) && ! is_end_of_line[(unsigned int) *s])
 	s++;
 
@@ -3027,32 +2948,61 @@ mmix_handle_mmixal ()
 			_("[0-9]H labels do not mix with dot-pseudos"));
 	  current_fb_label = -1;
 	}
+
+      /* Back off to the last space before the opcode so we don't handle
+	 the opcode as a label.  */
+      s--;
     }
   else
+    current_fb_label = -1;
+
+  if (*s == '.')
     {
-      current_fb_label = -1;
-      if (is_name_beginner (input_line_pointer[0]))
-	label = input_line_pointer;
+      /* If the first character is a '.', then it's a pseudodirective, not a
+	 label.  Make GAS not handle label-without-colon on this line.  We
+	 also don't do mmixal-specific stuff on this line.  */
+      label_without_colon_this_line = 0;
+      return;
     }
 
-  s0 = input_line_pointer;
-  /* Skip over label.  */
-  while (*s0 && is_part_of_name (*s0))
-    s0++;
-
-  /* Remove trailing ":" off labels, as they'd otherwise be considered
-     part of the name.  But don't do it for local labels.  */
-  if (s0 != input_line_pointer && s0[-1] == ':'
-      && (s0 - 2 != input_line_pointer
-	  || ! ISDIGIT (s0[-2])))
-    s0[-1] = ' ';
-  else if (label != NULL)
+  if (*s == 0 || is_end_of_line[(unsigned int) *s])
+    /* We avoid handling empty lines here.  */
+    return;
+      
+  if (is_name_beginner (*s))
+    label = s;
+
+  /* If there is a label, skip over it.  */
+  while (*s && is_part_of_name (*s))
+    s++;
+
+  /* Find the start of the instruction or pseudo following the label,
+     if there is one.  */
+  for (insn = s;
+       *insn && ISSPACE (*insn) && ! is_end_of_line[(unsigned int) *insn];
+       insn++)
+    /* Empty */
+    ;
+
+  /* Remove a trailing ":" off labels, as they'd otherwise be considered
+     part of the name.  But don't do this for local labels.  */
+  if (s != input_line_pointer && s[-1] == ':'
+      && (s - 2 != input_line_pointer
+	  || ! ISDIGIT (s[-2])))
+    s[-1] = ' ';
+  else if (label != NULL
+	   /* For a lone label on a line, we don't attach it to the next
+	      instruction or MMIXAL-pseudo (getting its alignment).  Thus
+	      is acts like a "normal" :-ended label.  Ditto if it's
+	      followed by a non-MMIXAL pseudo.  */
+	   && !is_end_of_line[(unsigned int) *insn]
+	   && *insn != '.')
     {
       /* For labels that don't end in ":", we save it so we can later give
 	 it the same alignment and address as the associated instruction.  */
 
       /* Make room for the label including the ending nul.  */
-      int len_0 = s0 - label + 1;
+      int len_0 = s - label + 1;
 
       /* Save this label on the MMIX symbol obstack.  Saving it on an
 	 obstack is needless for "IS"-pseudos, but it's harmless and we
@@ -3062,14 +3012,10 @@ mmix_handle_mmixal ()
       pending_label[len_0 - 1] = 0;
     }
 
-  while (*s0 && ISSPACE (*s0) && ! is_end_of_line[(unsigned int) *s0])
-    s0++;
-
-  if (pending_label != NULL && is_end_of_line[(unsigned int) *s0])
-    /* Whoops, this was actually a lone label on a line.  Like :-ended
-       labels, we don't attach such labels to the next instruction or
-       pseudo.  */
-    pending_label = NULL;
+  /* If we have a non-MMIXAL pseudo, we have not business with the rest of
+     the line.  */
+  if (*insn == '.')
+    return;
 
   /* Find local labels of operands.  Look for "[0-9][FB]" where the
      characters before and after are not part of words.  Break if a single
@@ -3081,7 +3027,6 @@ mmix_handle_mmixal ()
 
   /* First make sure we don't have any of the magic characters on the line
      appearing as input.  */
-  s = s0;
   while (*s)
     {
       c = *s++;
@@ -3092,7 +3037,7 @@ mmix_handle_mmixal ()
     }
 
   /* Scan again, this time looking for ';' after operands.  */
-  s = s0;
+  s = insn;
 
   /* Skip the insn.  */
   while (*s
@@ -3132,7 +3077,9 @@ mmix_handle_mmixal ()
 	{
 	  if ((s[1] != 'B' && s[1] != 'F')
 	      || is_part_of_name (s[-1])
-	      || is_part_of_name (s[2]))
+	      || is_part_of_name (s[2])
+	      /* Don't treat e.g. #1F as a local-label reference.  */
+	      || (s != input_line_pointer && s[-1] == '#'))
 	    s++;
 	  else
 	    {
@@ -3158,7 +3105,7 @@ mmix_handle_mmixal ()
 
   /* Make IS into an EQU by replacing it with "= ".  Only match upper-case
      though; let lower-case be a syntax error.  */
-  s = s0;
+  s = insn;
   if (s[0] == 'I' && s[1] == 'S' && ISSPACE (s[2]))
     {
       *s = '=';
@@ -3264,8 +3211,7 @@ mmix_handle_mmixal ()
    We fill in the label as an expression.  */
 
 void
-mmix_fb_label (expP)
-     expressionS *expP;
+mmix_fb_label (expressionS *expP)
 {
   symbolS *sym;
   char *fb_internal_name;
@@ -3314,8 +3260,7 @@ mmix_fb_label (expP)
    relaxing.  */
 
 int
-mmix_force_relocation (fixP)
-     fixS *fixP;
+mmix_force_relocation (fixS *fixP)
 {
   if (fixP->fx_r_type == BFD_RELOC_MMIX_LOCAL
       || fixP->fx_r_type == BFD_RELOC_MMIX_BASE_PLUS_OFFSET)
@@ -3324,10 +3269,10 @@ mmix_force_relocation (fixP)
   if (linkrelax)
     return 1;
 
-  /* All our pcrel relocations are must-keep.  Note that md_apply_fix3 is
+  /* All our pcrel relocations are must-keep.  Note that md_apply_fix is
      called *after* this, and will handle getting rid of the presumed
      reloc; a relocation isn't *forced* other than to be handled by
-     md_apply_fix3 (or tc_gen_reloc if linkrelax).  */
+     md_apply_fix (or tc_gen_reloc if linkrelax).  */
   if (fixP->fx_pcrel)
     return 1;
 
@@ -3338,9 +3283,7 @@ mmix_force_relocation (fixP)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS * fixP;
-     segT   sec;
+md_pcrel_from_section (fixS *fixP, segT sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
@@ -3358,7 +3301,7 @@ md_pcrel_from_section (fixP, sec)
    register section.  */
 
 void
-mmix_adjust_symtab ()
+mmix_adjust_symtab (void)
 {
   symbolS *sym;
   symbolS *regsec = section_symbol (reg_section);
@@ -3368,7 +3311,7 @@ mmix_adjust_symtab ()
       {
 	if (sym == regsec)
 	  {
-	    if (S_IS_EXTERN (sym) || symbol_used_in_reloc_p (sym))
+	    if (S_IS_EXTERNAL (sym) || symbol_used_in_reloc_p (sym))
 	      abort ();
 	    symbol_remove (sym, &symbol_rootP, &symbol_lastP);
 	  }
@@ -3388,7 +3331,7 @@ mmix_adjust_symtab ()
    thought at the time I first wrote this.  */
 
 int
-mmix_label_without_colon_this_line ()
+mmix_label_without_colon_this_line (void)
 {
   int retval = label_without_colon_this_line;
 
@@ -3404,10 +3347,7 @@ mmix_label_without_colon_this_line ()
    join with.  */
 
 long
-mmix_md_relax_frag (seg, fragP, stretch)
-     segT seg;
-     fragS *fragP;
-     long stretch;
+mmix_md_relax_frag (segT seg, fragS *fragP, long stretch)
 {
   switch (fragP->fr_subtype)
     {
@@ -3533,7 +3473,7 @@ mmix_md_relax_frag (seg, fragP, stretch)
 /* Various things we punt until all input is seen.  */
 
 void
-mmix_md_end ()
+mmix_md_end (void)
 {
   fragS *fragP;
   symbolS *mainsym;
@@ -3708,9 +3648,7 @@ mmix_md_end ()
 /* qsort function for mmix_symbol_gregs.  */
 
 static int
-cmp_greg_symbol_fixes (parg, qarg)
-     const PTR parg;
-     const PTR qarg;
+cmp_greg_symbol_fixes (const void *parg, const void *qarg)
 {
   const struct mmix_symbol_greg_fixes *p
     = (const struct mmix_symbol_greg_fixes *) parg;
@@ -3727,7 +3665,7 @@ cmp_greg_symbol_fixes (parg, qarg)
    as an ELF section.  */
 
 void
-mmix_frob_file ()
+mmix_frob_file (void)
 {
   int i;
   struct mmix_symbol_gregs *all_greg_symbols[MAX_GREGS];
@@ -3811,18 +3749,11 @@ mmix_frob_file ()
 
   if (real_reg_section != NULL)
     {
-      asection **secpp;
-
       /* FIXME: Pass error state gracefully.  */
       if (bfd_get_section_flags (stdoutput, real_reg_section) & SEC_HAS_CONTENTS)
 	as_fatal (_("register section has contents\n"));
 
-      /* Really remove the section.  */
-      for (secpp = &stdoutput->sections;
-	   *secpp != real_reg_section;
-	   secpp = &(*secpp)->next)
-	;
-      bfd_section_list_remove (stdoutput, secpp);
+      bfd_section_list_remove (stdoutput, real_reg_section);
       --stdoutput->section_count;
     }
 
@@ -3835,9 +3766,7 @@ mmix_frob_file ()
    If the name isn't a built-in name and parsed into *EXPP, return zero.  */
 
 int
-mmix_parse_predefined_name (name, expP)
-     char *name;
-     expressionS *expP;
+mmix_parse_predefined_name (char *name, expressionS *expP)
 {
   char *canon_name;
   char *handler_charp;
@@ -3946,7 +3875,7 @@ mmix_parse_predefined_name (name, expP)
    section.  */
 
 void
-mmix_md_elf_section_change_hook ()
+mmix_md_elf_section_change_hook (void)
 {
   if (doing_bspec)
     as_bad (_("section change from within a BSPEC/ESPEC pair is not supported"));
@@ -3959,8 +3888,7 @@ mmix_md_elf_section_change_hook ()
    section too.   */
 
 static void
-s_loc (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_loc (int ignore ATTRIBUTE_UNUSED)
 {
   segT section;
   expressionS exp;
@@ -4089,7 +4017,7 @@ s_loc (ignore)
    by comma.  */
 
 static void
-mmix_byte ()
+mmix_byte (void)
 {
   unsigned int c;
   char *start;
@@ -4179,8 +4107,7 @@ mmix_byte ()
    lenient than mmix_byte but FIXME: they should eventually merge.  */
 
 static void
-mmix_cons (nbytes)
-     int nbytes;
+mmix_cons (int nbytes)
 {
   expressionS exp;
   char *start;
@@ -4309,11 +4236,8 @@ mmix_cons (nbytes)
    Arguably this is a GCC bug.  */
 
 void
-mmix_md_do_align (n, fill, len, max)
-     int n;
-     char *fill ATTRIBUTE_UNUSED;
-     int len ATTRIBUTE_UNUSED;
-     int max ATTRIBUTE_UNUSED;
+mmix_md_do_align (int n, char *fill ATTRIBUTE_UNUSED,
+		  int len ATTRIBUTE_UNUSED, int max ATTRIBUTE_UNUSED)
 {
   last_alignment = n;
   want_unaligned = n == 0;
diff --git a/gas/config/tc-mmix.h b/gas/config/tc-mmix.h
index c6d222f1fdd3..61bc881d1268 100644
--- a/gas/config/tc-mmix.h
+++ b/gas/config/tc-mmix.h
@@ -1,5 +1,5 @@
 /* tc-mmix.h -- Header file for tc-mmix.c.
-   Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright (C) 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
    Written by Hans-Peter Nilsson (hp@bitrange.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_MMIX
 
@@ -41,25 +41,25 @@ extern const char mmix_flt_chars[];
 /* "@" is a synonym for ".".  */
 #define LEX_AT (LEX_BEGIN_NAME)
 
-extern int mmix_label_without_colon_this_line PARAMS ((void));
+extern int mmix_label_without_colon_this_line (void);
 #define LABELS_WITHOUT_COLONS mmix_label_without_colon_this_line ()
 
 extern int mmix_next_semicolon_is_eoln;
 #define TC_EOL_IN_INSN(p) (*(p) == ';' && ! mmix_next_semicolon_is_eoln)
 
 /* This is one direction we can get mmixal compatibility.  */
-extern void mmix_handle_mmixal PARAMS ((void));
+extern void mmix_handle_mmixal (void);
 #define md_start_line_hook mmix_handle_mmixal
 
-extern void mmix_md_begin PARAMS ((void));
+extern void mmix_md_begin (void);
 #define md_begin mmix_md_begin
 
-extern void mmix_md_end PARAMS ((void));
+extern void mmix_md_end (void);
 #define md_end mmix_md_end
 
 extern int mmix_current_location \
-  PARAMS ((void (*fn) (expressionS *), expressionS *));
-extern int mmix_parse_predefined_name PARAMS ((char *, expressionS *));
+  (void (*fn) (expressionS *), expressionS *);
+extern int mmix_parse_predefined_name (char *, expressionS *);
 
 extern char *mmix_current_prefix;
 
@@ -70,7 +70,7 @@ extern char *mmix_current_prefix;
    The [DVWIOUZX]_Handler symbols are provided when-used.  */
 
 extern int mmix_gnu_syntax;
-#define md_parse_name(name, exp, cpos)				\
+#define md_parse_name(name, exp, mode, cpos)			\
  (! mmix_gnu_syntax						\
   && (name[0] == '@'						\
       ? (! is_part_of_name (name[1])				\
@@ -78,7 +78,7 @@ extern int mmix_gnu_syntax;
       : ((name[0] == ':' || ISUPPER (name[0]))			\
 	 && mmix_parse_predefined_name (name, exp))))
 
-extern char *mmix_prefix_name PARAMS ((char *));
+extern char *mmix_prefix_name (char *);
 
 /* We implement when *creating* a symbol, we also need to strip a ':' or
    prepend a prefix.  */
@@ -87,7 +87,7 @@ extern char *mmix_prefix_name PARAMS ((char *));
 
 #define md_undefined_symbol(x) NULL
 
-extern void mmix_fb_label PARAMS ((expressionS *));
+extern void mmix_fb_label (expressionS *);
 
 /* Since integer_constant is local to expr.c, we have to make this a
    macro.  FIXME: Do it cleaner.  */
@@ -110,7 +110,7 @@ extern void mmix_fb_label PARAMS ((expressionS *));
 /* Gas dislikes the 2ADD, 8ADD etc. insns, so we have to assemble them in
    the error-recovery loop.  Hopefully there are no significant
    differences.  Also, space on a line isn't gracefully handled.  */
-extern int mmix_assemble_return_nonzero PARAMS ((char *));
+extern int mmix_assemble_return_nonzero (char *);
 #define tc_unrecognized_line(c)						\
  ((c) == ' '								\
   || (((c) == '1' || (c) == '2' || (c) == '4' || (c) == '8')		\
@@ -124,7 +124,7 @@ extern const struct relax_type mmix_relax_table[];
 #define TC_GENERIC_RELAX_TABLE mmix_relax_table
 
 /* We use the relax table for everything except the GREG frags and PUSHJ.  */
-extern long mmix_md_relax_frag PARAMS ((segT, fragS *, long));
+extern long mmix_md_relax_frag (segT, fragS *, long);
 #define md_relax_frag mmix_md_relax_frag
 
 #define tc_fix_adjustable(FIX)					\
@@ -136,7 +136,7 @@ extern long mmix_md_relax_frag PARAMS ((segT, fragS *, long));
 
 /* Adjust symbols which are registers.  */
 #define tc_adjust_symtab() mmix_adjust_symtab ()
-extern void mmix_adjust_symtab PARAMS ((void));
+extern void mmix_adjust_symtab (void);
 
 /* Here's where we make all symbols global, when so requested.
    We must avoid doing that for expression symbols or section symbols,
@@ -170,11 +170,11 @@ extern int mmix_globalize_symbols;
 
 /* When relaxing, we need to emit various relocs we otherwise wouldn't.  */
 #define TC_FORCE_RELOCATION(fix) mmix_force_relocation (fix)
-extern int mmix_force_relocation PARAMS ((struct fix *));
+extern int mmix_force_relocation (struct fix *);
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define md_section_align(seg, size) (size)
 
@@ -192,7 +192,7 @@ extern fragS *mmix_opcode_frag;
    all symbols have been evaluated and all frags mapped, and when the
    fixups are done and relocs are output.  Similarly for each unknown
    symbol.  */
-extern void mmix_frob_file PARAMS ((void));
+extern void mmix_frob_file (void);
 #define tc_frob_file_before_fix mmix_frob_file
 
 /* Used by mmix_frob_file.  Hangs on section symbols and unknown symbols.  */
@@ -210,10 +210,10 @@ struct mmix_segment_info_type
  };
 #define TC_SEGMENT_INFO_TYPE struct mmix_segment_info_type
 
-extern void mmix_md_elf_section_change_hook PARAMS ((void));
+extern void mmix_md_elf_section_change_hook (void);
 #define md_elf_section_change_hook mmix_md_elf_section_change_hook
 
-extern void mmix_md_do_align PARAMS ((int, char *, int, int));
+extern void mmix_md_do_align (int, char *, int, int);
 #define md_do_align(n, fill, len, max, label) \
  mmix_md_do_align (n, fill, len, max)
 
diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c
index 642069493b4a..909652ef6e0e 100644
--- a/gas/config/tc-mn10200.c
+++ b/gas/config/tc-mn10200.c
@@ -1,6 +1,6 @@
 /* tc-mn10200.c -- Assembler code for the Matsushita 10200
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
+   2005, 2006  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -53,7 +53,8 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-const relax_typeS md_relax_table[] = {
+const relax_typeS md_relax_table[] =
+ {
   /* bCC relaxing  */
   {0x81, -0x7e, 2, 1},
   {0x8004, -0x7ffb, 5, 2},
@@ -72,34 +73,27 @@ const relax_typeS md_relax_table[] = {
 
 };
 
-/* Local functions.  */
-static void mn10200_insert_operand PARAMS ((unsigned long *, unsigned long *,
-					    const struct mn10200_operand *,
-					    offsetT, char *, unsigned,
-					    unsigned));
-static unsigned long check_operand PARAMS ((unsigned long,
-					    const struct mn10200_operand *,
-					    offsetT));
-static int reg_name_search PARAMS ((const struct reg_name *, int, const char *));
-static bfd_boolean data_register_name PARAMS ((expressionS *expressionP));
-static bfd_boolean address_register_name PARAMS ((expressionS *expressionP));
-static bfd_boolean other_register_name PARAMS ((expressionS *expressionP));
 
 /* Fixups.  */
-#define MAX_INSN_FIXUPS (5)
+#define MAX_INSN_FIXUPS 5
+
 struct mn10200_fixup
 {
   expressionS exp;
   int opindex;
   bfd_reloc_code_real_type reloc;
 };
+
 struct mn10200_fixup fixups[MAX_INSN_FIXUPS];
 static int fc;
 
 const char *md_shortopts = "";
-struct option md_longopts[] = {
+
+struct option md_longopts[] =
+{
   {NULL, no_argument, NULL, 0}
 };
+
 size_t md_longopts_size = sizeof (md_longopts);
 
 /* The target specific pseudo-ops which we support.  */
@@ -145,10 +139,9 @@ static const struct reg_name other_registers[] =
    number from the array on success, or -1 on failure.  */
 
 static int
-reg_name_search (regs, regcount, name)
-     const struct reg_name *regs;
-     int regcount;
-     const char *name;
+reg_name_search (const struct reg_name *regs,
+		 int regcount,
+		 const char *name)
 {
   int middle, low, high;
   int cmp;
@@ -172,19 +165,17 @@ reg_name_search (regs, regcount, name)
 }
 
 /* Summary of register_name().
- *
- * in: Input_line_pointer points to 1st char of operand.
- *
- * out: An expressionS.
- *	The operand may have been a register: in this case, X_op == O_register,
- *	X_add_number is set to the register number, and truth is returned.
- *	Input_line_pointer->(next non-blank) char after operand, or is in
- *	its original state.
- */
+
+   in: Input_line_pointer points to 1st char of operand.
+
+   out: An expressionS.
+  	The operand may have been a register: in this case, X_op == O_register,
+  	X_add_number is set to the register number, and truth is returned.
+  	Input_line_pointer->(next non-blank) char after operand, or is in
+  	its original state.  */
 
 static bfd_boolean
-data_register_name (expressionP)
-     expressionS *expressionP;
+data_register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -219,19 +210,17 @@ data_register_name (expressionP)
 }
 
 /* Summary of register_name().
- *
- * in: Input_line_pointer points to 1st char of operand.
- *
- * out: An expressionS.
- *	The operand may have been a register: in this case, X_op == O_register,
- *	X_add_number is set to the register number, and truth is returned.
- *	Input_line_pointer->(next non-blank) char after operand, or is in
- *	its original state.
- */
+
+   in: Input_line_pointer points to 1st char of operand.
+
+   out: An expressionS.
+  	The operand may have been a register: in this case, X_op == O_register,
+  	X_add_number is set to the register number, and truth is returned.
+  	Input_line_pointer->(next non-blank) char after operand, or is in
+  	its original state.  */
 
 static bfd_boolean
-address_register_name (expressionP)
-     expressionS *expressionP;
+address_register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -266,19 +255,17 @@ address_register_name (expressionP)
 }
 
 /* Summary of register_name().
- *
- * in: Input_line_pointer points to 1st char of operand.
- *
- * out: An expressionS.
- *	The operand may have been a register: in this case, X_op == O_register,
- *	X_add_number is set to the register number, and truth is returned.
- *	Input_line_pointer->(next non-blank) char after operand, or is in
- *	its original state.
- */
+
+   in: Input_line_pointer points to 1st char of operand.
+
+   out: An expressionS.
+  	The operand may have been a register: in this case, X_op == O_register,
+  	X_add_number is set to the register number, and truth is returned.
+  	Input_line_pointer->(next non-blank) char after operand, or is in
+  	its original state.  */
 
 static bfd_boolean
-other_register_name (expressionP)
-     expressionS *expressionP;
+other_register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -313,33 +300,27 @@ other_register_name (expressionP)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("MN10200 options:\n\
 none yet\n"));
 }
 
 int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED,
+		 char *arg ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 char *
-md_atof (type, litp, sizep)
-     int type;
-     char *litp;
-     int *sizep;
+md_atof (int type, char *litp, int *sizep)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -377,10 +358,9 @@ md_atof (type, litp, sizep)
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec,
+		 fragS *fragP)
 {
   static unsigned long label_count = 0;
   char buf[40];
@@ -728,16 +708,14 @@ md_convert_frag (abfd, sec, fragP)
 }
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   char *prev_name = "";
   register const struct mn10200_opcode *op;
@@ -760,15 +738,175 @@ md_begin ()
       op++;
     }
 
-  /* This is both a simplification (we don't have to write md_apply_fix3)
+  /* This is both a simplification (we don't have to write md_apply_fix)
      and support for future optimizations (branch shortening and similar
      stuff in the linker.  */
   linkrelax = 1;
 }
 
+static unsigned long
+check_operand (unsigned long insn ATTRIBUTE_UNUSED,
+	       const struct mn10200_operand *operand,
+	       offsetT val)
+{
+  /* No need to check 24bit or 32bit operands for a bit.  */
+  if (operand->bits < 24
+      && (operand->flags & MN10200_OPERAND_NOCHECK) == 0)
+    {
+      long min, max;
+      offsetT test;
+
+      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
+	{
+	  max = (1 << (operand->bits - 1)) - 1;
+	  min = - (1 << (operand->bits - 1));
+	}
+      else
+	{
+	  max = (1 << operand->bits) - 1;
+	  min = 0;
+	}
+
+      test = val;
+
+      if (test < (offsetT) min || test > (offsetT) max)
+	return 0;
+      else
+	return 1;
+    }
+  return 1;
+}
+/* If while processing a fixup, a reloc really needs to be created
+   Then it is done here.  */
+
+arelent *
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *reloc;
+  reloc = xmalloc (sizeof (arelent));
+
+  if (fixp->fx_subsy != NULL)
+    {
+      if (S_GET_SEGMENT (fixp->fx_addsy) == S_GET_SEGMENT (fixp->fx_subsy)
+	  && S_IS_DEFINED (fixp->fx_subsy))
+	{
+	  fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
+	  fixp->fx_subsy = NULL;
+	}
+      else
+	/* FIXME: We should try more ways to resolve difference expressions
+	   here.  At least this is better than silently ignoring the
+	   subtrahend.  */
+	as_bad_where (fixp->fx_file, fixp->fx_line,
+		      _("can't resolve `%s' {%s section} - `%s' {%s section}"),
+		      fixp->fx_addsy ? S_GET_NAME (fixp->fx_addsy) : "0",
+		      segment_name (fixp->fx_addsy
+				    ? S_GET_SEGMENT (fixp->fx_addsy)
+				    : absolute_section),
+		      S_GET_NAME (fixp->fx_subsy),
+		      segment_name (S_GET_SEGMENT (fixp->fx_addsy)));
+    }
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+  if (reloc->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("reloc %d not supported by object file format"),
+		    (int) fixp->fx_r_type);
+      return NULL;
+    }
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->addend = fixp->fx_offset;
+  return reloc;
+}
+
+int
+md_estimate_size_before_relax (fragS *fragp, asection *seg)
+{
+  if (fragp->fr_subtype == 6
+      && (!S_IS_DEFINED (fragp->fr_symbol)
+	  || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+    fragp->fr_subtype = 7;
+  else if (fragp->fr_subtype == 8
+	   && (!S_IS_DEFINED (fragp->fr_symbol)
+	       || seg != S_GET_SEGMENT (fragp->fr_symbol)))
+    fragp->fr_subtype = 10;
+
+  if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
+    abort ();
+
+  return md_relax_table[fragp->fr_subtype].rlx_length;
+}
+
+long
+md_pcrel_from (fixS *fixp)
+{
+  return fixp->fx_frag->fr_address;
+}
+
 void
-md_assemble (str)
-     char *str;
+md_apply_fix (fixS * fixP, valueT * valP ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED)
+{
+  /* We shouldn't ever get here because linkrelax is nonzero.  */
+  abort ();
+  fixP->fx_done = 1;
+}
+
+/* Insert an operand value into an instruction.  */
+
+static void
+mn10200_insert_operand (unsigned long *insnp,
+			unsigned long *extensionp,
+			const struct mn10200_operand *operand,
+			offsetT val,
+			char *file,
+			unsigned int line,
+			unsigned int shift)
+{
+  /* No need to check 24 or 32bit operands for a bit.  */
+  if (operand->bits < 24
+      && (operand->flags & MN10200_OPERAND_NOCHECK) == 0)
+    {
+      long min, max;
+      offsetT test;
+
+      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
+	{
+	  max = (1 << (operand->bits - 1)) - 1;
+	  min = - (1 << (operand->bits - 1));
+	}
+      else
+	{
+	  max = (1 << operand->bits) - 1;
+	  min = 0;
+	}
+
+      test = val;
+
+      if (test < (offsetT) min || test > (offsetT) max)
+	as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
+    }
+
+  if ((operand->flags & MN10200_OPERAND_EXTENDED) == 0)
+    {
+      *insnp |= (((long) val & ((1 << operand->bits) - 1))
+		 << (operand->shift + shift));
+
+      if ((operand->flags & MN10200_OPERAND_REPEATED) != 0)
+	*insnp |= (((long) val & ((1 << operand->bits) - 1))
+		   << (operand->shift + shift + 2));
+    }
+  else
+    {
+      *extensionp |= (val >> 16) & 0xff;
+      *insnp |= val & 0xffff;
+    }
+}
+
+void
+md_assemble (char *str)
 {
   char *s;
   struct mn10200_opcode *opcode;
@@ -957,7 +1095,7 @@ md_assemble (str)
 		extra_shift = 0;
 
 	      mn10200_insert_operand (&insn, &extension, operand,
-				      ex.X_add_number, (char *) NULL,
+				      ex.X_add_number, NULL,
 				      0, extra_shift);
 
 	      break;
@@ -976,7 +1114,7 @@ md_assemble (str)
 		}
 
 	      mn10200_insert_operand (&insn, &extension, operand,
-				      ex.X_add_number, (char *) NULL,
+				      ex.X_add_number, NULL,
 				      0, 0);
 	      break;
 
@@ -1051,9 +1189,20 @@ keep_going:
     abort ();
 
   /* Write out the instruction.  */
-
   if (relaxable && fc > 0)
     {
+      /* On a 64-bit host the size of an 'int' is not the same
+	 as the size of a pointer, so we need a union to convert
+	 the opindex field of the fr_cgen structure into a char *
+	 so that it can be stored in the frag.  We do not have
+	 to worry about loosing accuracy as we are not going to
+	 be even close to the 32bit limit of the int.  */
+      union
+      {
+	int opindex;
+	char * ptr;
+      }
+      opindex_converter;
       int type;
 
       /* bCC  */
@@ -1081,10 +1230,11 @@ keep_going:
       else
 	type = 3;
 
+      opindex_converter.opindex = fixups[0].opindex;
       f = frag_var (rs_machine_dependent, 8, 8 - size, type,
 		    fixups[0].exp.X_add_symbol,
 		    fixups[0].exp.X_add_number,
-		    (char *)fixups[0].opindex);
+		    opindex_converter.ptr);
       number_to_chars_bigendian (f, insn, size);
       if (8 - size > 4)
 	{
@@ -1094,7 +1244,6 @@ keep_going:
       else
 	number_to_chars_bigendian (f + size, 0, 8 - size);
     }
-
   else
     {
       f = frag_more (size);
@@ -1118,9 +1267,7 @@ keep_going:
 	  number_to_chars_littleendian (f + 4, extension & 0xff, 1);
 	}
       else
-	{
-	  number_to_chars_bigendian (f, insn, size > 4 ? 4 : size);
-	}
+	number_to_chars_bigendian (f, insn, size > 4 ? 4 : size);
 
       /* Create any fixups.  */
       for (i = 0; i < fc; i++)
@@ -1222,185 +1369,3 @@ keep_going:
     }
 }
 
-/* If while processing a fixup, a reloc really needs to be created
-   Then it is done here.  */
-
-arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
-{
-  arelent *reloc;
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-
-  if (fixp->fx_subsy != NULL)
-    {
-      /* FIXME: We should resolve difference expressions if possible
-	 here.  At least this is better than silently ignoring the
-	 subtrahend.  */
-      as_bad_where (fixp->fx_file, fixp->fx_line,
-		    _("can't resolve `%s' {%s section} - `%s' {%s section}"),
-		    fixp->fx_addsy ? S_GET_NAME (fixp->fx_addsy) : "0",
-		    segment_name (fixp->fx_addsy
-				  ? S_GET_SEGMENT (fixp->fx_addsy)
-				  : absolute_section),
-		    S_GET_NAME (fixp->fx_subsy),
-		    segment_name (S_GET_SEGMENT (fixp->fx_addsy)));
-    }
-
-  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
-  if (reloc->howto == (reloc_howto_type *) NULL)
-    {
-      as_bad_where (fixp->fx_file, fixp->fx_line,
-		    _("reloc %d not supported by object file format"),
-		    (int) fixp->fx_r_type);
-      return NULL;
-    }
-  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
-  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
-  reloc->addend = fixp->fx_offset;
-  return reloc;
-}
-
-int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp;
-     asection *seg;
-{
-  if (fragp->fr_subtype == 6
-      && (!S_IS_DEFINED (fragp->fr_symbol)
-	  || seg != S_GET_SEGMENT (fragp->fr_symbol)))
-    fragp->fr_subtype = 7;
-  else if (fragp->fr_subtype == 8
-	   && (!S_IS_DEFINED (fragp->fr_symbol)
-	       || seg != S_GET_SEGMENT (fragp->fr_symbol)))
-    fragp->fr_subtype = 10;
-
-  if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
-    abort ();
-
-  return md_relax_table[fragp->fr_subtype].rlx_length;
-}
-
-long
-md_pcrel_from (fixp)
-     fixS *fixp;
-{
-  return fixp->fx_frag->fr_address;
-#if 0
-  if (fixp->fx_addsy != (symbolS *) NULL && !S_IS_DEFINED (fixp->fx_addsy))
-    {
-      /* The symbol is undefined.  Let the linker figure it out.  */
-      return 0;
-    }
-  return fixp->fx_frag->fr_address + fixp->fx_where;
-#endif
-}
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS * fixP;
-     valueT * valP ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  /* We shouldn't ever get here because linkrelax is nonzero.  */
-  abort ();
-  fixP->fx_done = 1;
-}
-
-/* Insert an operand value into an instruction.  */
-
-static void
-mn10200_insert_operand (insnp, extensionp, operand, val, file, line, shift)
-     unsigned long *insnp;
-     unsigned long *extensionp;
-     const struct mn10200_operand *operand;
-     offsetT val;
-     char *file;
-     unsigned int line;
-     unsigned int shift;
-{
-  /* No need to check 24 or 32bit operands for a bit.  */
-  if (operand->bits < 24
-      && (operand->flags & MN10200_OPERAND_NOCHECK) == 0)
-    {
-      long min, max;
-      offsetT test;
-
-      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
-	{
-	  max = (1 << (operand->bits - 1)) - 1;
-	  min = - (1 << (operand->bits - 1));
-	}
-      else
-	{
-	  max = (1 << operand->bits) - 1;
-	  min = 0;
-	}
-
-      test = val;
-
-      if (test < (offsetT) min || test > (offsetT) max)
-        {
-          const char *err =
-            _("operand out of range (%s not between %ld and %ld)");
-          char buf[100];
-
-          sprint_value (buf, test);
-          if (file == (char *) NULL)
-            as_warn (err, buf, min, max);
-          else
-            as_warn_where (file, line, err, buf, min, max);
-        }
-    }
-
-  if ((operand->flags & MN10200_OPERAND_EXTENDED) == 0)
-    {
-      *insnp |= (((long) val & ((1 << operand->bits) - 1))
-		 << (operand->shift + shift));
-
-      if ((operand->flags & MN10200_OPERAND_REPEATED) != 0)
-	*insnp |= (((long) val & ((1 << operand->bits) - 1))
-		   << (operand->shift + shift + 2));
-    }
-  else
-    {
-      *extensionp |= (val >> 16) & 0xff;
-      *insnp |= val & 0xffff;
-    }
-}
-
-static unsigned long
-check_operand (insn, operand, val)
-     unsigned long insn ATTRIBUTE_UNUSED;
-     const struct mn10200_operand *operand;
-     offsetT val;
-{
-  /* No need to check 24bit or 32bit operands for a bit.  */
-  if (operand->bits < 24
-      && (operand->flags & MN10200_OPERAND_NOCHECK) == 0)
-    {
-      long min, max;
-      offsetT test;
-
-      if ((operand->flags & MN10200_OPERAND_SIGNED) != 0)
-	{
-	  max = (1 << (operand->bits - 1)) - 1;
-	  min = - (1 << (operand->bits - 1));
-	}
-      else
-	{
-	  max = (1 << operand->bits) - 1;
-	  min = 0;
-	}
-
-      test = val;
-
-      if (test < (offsetT) min || test > (offsetT) max)
-	return 0;
-      else
-	return 1;
-    }
-  return 1;
-}
diff --git a/gas/config/tc-mn10200.h b/gas/config/tc-mn10200.h
index ca181160a279..b4722df22b3d 100644
--- a/gas/config/tc-mn10200.h
+++ b/gas/config/tc-mn10200.h
@@ -1,5 +1,5 @@
 /* tc-mn10200.h -- Header file for tc-mn10200.c.
-   Copyright 1996, 1997, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 2000, 2001, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,17 +15,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_MN10200
 
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-#ifndef BFD_ASSEMBLER
- #error MN10200 support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH bfd_arch_mn10200
 
diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c
index 832464617d2b..102c2eacef84 100644
--- a/gas/config/tc-mn10300.c
+++ b/gas/config/tc-mn10300.c
@@ -1,6 +1,6 @@
 /* tc-mn10300.c -- Assembler code for the Matsushita 10300
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -54,15 +54,20 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-const relax_typeS md_relax_table[] = {
+const relax_typeS md_relax_table[] =
+{
+  /* The plus values for the bCC and fBCC instructions in the table below
+     are because the branch instruction is translated into a jump
+     instruction that is now +2 or +3 bytes further on in memory, and the
+     correct size of jump instruction must be selected.  */
   /* bCC relaxing  */
   {0x7f, -0x80, 2, 1},
-  {0x7fff, -0x8000, 5, 2},
+  {0x7fff + 2, -0x8000 + 2, 5, 2},
   {0x7fffffff, -0x80000000, 7, 0},
 
-  /* bCC relaxing (uncommon cases)  */
+  /* bCC relaxing (uncommon cases for 3byte length instructions)  */
   {0x7f, -0x80, 3, 4},
-  {0x7fff, -0x8000, 6, 5},
+  {0x7fff + 3, -0x8000 + 3, 6, 5},
   {0x7fffffff, -0x80000000, 8, 0},
 
   /* call relaxing  */
@@ -80,7 +85,7 @@ const relax_typeS md_relax_table[] = {
 
   /* fbCC relaxing  */
   {0x7f, -0x80, 3, 14},
-  {0x7fff, -0x8000, 6, 15},
+  {0x7fff + 3, -0x8000 + 3, 6, 15},
   {0x7fffffff, -0x80000000, 8, 0},
 
 };
@@ -2000,6 +2005,18 @@ keep_going:
 
   if (relaxable && fc > 0)
     {
+      /* On a 64-bit host the size of an 'int' is not the same
+	 as the size of a pointer, so we need a union to convert
+	 the opindex field of the fr_cgen structure into a char *
+	 so that it can be stored in the frag.  We do not have
+	 to worry about loosing accuracy as we are not going to
+	 be even close to the 32bit limit of the int.  */
+      union
+      {
+	int opindex;
+	char * ptr;
+      }
+      opindex_converter;
       int type;
 
       /* We want to anchor the line info to the previous frag (if
@@ -2039,10 +2056,11 @@ keep_going:
       else
 	type = 3;
 
+      opindex_converter.opindex = fixups[0].opindex;
       f = frag_var (rs_machine_dependent, 8, 8 - size, type,
 		    fixups[0].exp.X_add_symbol,
 		    fixups[0].exp.X_add_number,
-		    (char *)fixups[0].opindex);
+		    opindex_converter.ptr);
 
       /* This is pretty hokey.  We basically just care about the
 	 opcode, so we have to write out the first word big endian.
@@ -2447,7 +2465,7 @@ md_pcrel_from (fixp)
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS * fixP;
      valueT * valP;
      segT seg;
@@ -2463,11 +2481,10 @@ md_apply_fix3 (fixP, valP, seg)
     abort ();
 
   /* The value we are passed in *valuep includes the symbol values.
-     Since we are using BFD_ASSEMBLER, if we are doing this relocation
-     the code in write.c is going to call bfd_install_relocation, which
-     is also going to use the symbol value.  That means that if the
-     reloc is fully resolved we want to use *valuep since
-     bfd_install_relocation is not being used.
+     If we are doing this relocation the code in write.c is going to
+     call bfd_install_relocation, which is also going to use the symbol
+     value.  That means that if the reloc is fully resolved we want to
+     use *valuep since bfd_install_relocation is not being used.
 
      However, if the reloc is not fully resolved we do not want to use
      *valuep, and must use fx_offset instead.  However, if the reloc
@@ -2542,6 +2559,15 @@ mn10300_fix_adjustable (fixp)
   if (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE)
     return 0;
 
+  /* Likewise, do not adjust symbols that won't be merged, or debug
+     symbols, because they too break relaxation.  We do want to adjust
+     other mergable symbols, like .rodata, because code relaxations
+     need section-relative symbols to properly relax them.  */
+  if (! (S_GET_SEGMENT(fixp->fx_addsy)->flags & SEC_MERGE))
+    return 0;
+  if (strncmp (S_GET_SEGMENT (fixp->fx_addsy)->name, ".debug", 6) == 0)
+    return 0;
+
   return 1;
 }
 
@@ -2584,17 +2610,7 @@ mn10300_insert_operand (insnp, extensionp, operand, val, file, line, shift)
       test = val;
 
       if (test < (offsetT) min || test > (offsetT) max)
-	{
-	  const char *err =
-	    _("operand out of range (%s not between %ld and %ld)");
-	  char buf[100];
-
-	  sprint_value (buf, test);
-	  if (file == (char *) NULL)
-	    as_warn (err, buf, min, max);
-	  else
-	    as_warn_where (file, line, err, buf, min, max);
-	}
+	as_warn_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
     }
 
   if ((operand->flags & MN10300_OPERAND_SPLIT) != 0)
@@ -2740,9 +2756,10 @@ mn10300_end_of_match (cont, what)
 }  
 
 int
-mn10300_parse_name (name, exprP, nextcharP)
+mn10300_parse_name (name, exprP, mode, nextcharP)
      char const *name;
      expressionS *exprP;
+     enum expr_mode mode;
      char *nextcharP;
 {
   char *next = input_line_pointer;
@@ -2762,13 +2779,13 @@ mn10300_parse_name (name, exprP, nextcharP)
       /* If we have an absolute symbol or a reg,
 	 then we know its value now.  */
       segment = S_GET_SEGMENT (exprP->X_add_symbol);
-      if (segment == absolute_section)
+      if (mode != expr_defer && segment == absolute_section)
 	{
 	  exprP->X_op = O_constant;
 	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
 	  exprP->X_add_symbol = NULL;
 	}
-      else if (segment == reg_section)
+      else if (mode != expr_defer && segment == reg_section)
 	{
 	  exprP->X_op = O_register;
 	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
diff --git a/gas/config/tc-mn10300.h b/gas/config/tc-mn10300.h
index 1b88cf2d908d..dff663d29adf 100644
--- a/gas/config/tc-mn10300.h
+++ b/gas/config/tc-mn10300.h
@@ -1,5 +1,5 @@
 /* tc-mn10300.h -- Header file for tc-mn10300.c.
-   Copyright 1996, 1997, 2000, 2001, 2002, 2003
+   Copyright 1996, 1997, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,17 +16,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_MN10300
 
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-#ifndef BFD_ASSEMBLER
- #error MN10300 support requires BFD_ASSEMBLER
-#endif
-
 #define DIFF_EXPR_OK
 #define GLOBAL_OFFSET_TABLE_NAME "_GLOBAL_OFFSET_TABLE_"
 
@@ -40,9 +36,10 @@
 	   && S_IS_DEFINED ((FIX)->fx_addsy)			\
 	   && ! S_IS_COMMON ((FIX)->fx_addsy))))
 
-#define md_parse_name(name, exprP, nextcharP) \
-    mn10300_parse_name ((name), (exprP), (nextcharP))
-int mn10300_parse_name PARAMS ((char const *, expressionS *, char *));
+#define md_parse_name(name, exprP, mode, nextcharP) \
+    mn10300_parse_name ((name), (exprP), (mode), (nextcharP))
+int mn10300_parse_name PARAMS ((char const *, expressionS *,
+				enum expr_mode, char *));
 
 #define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
      mn10300_cons_fix_new ((FRAG), (OFF), (LEN), (EXP))
@@ -102,8 +99,8 @@ void mn10300_cons_fix_new PARAMS ((fragS *, int, int, expressionS *));
 #define md_number_to_chars number_to_chars_littleendian
 
 /* Don't bother to adjust relocs.  */
-#define tc_fix_adjustable(FIX) 0
-/* #define tc_fix_adjustable(FIX) mn10300_fix_adjustable (FIX) */
+/* #define tc_fix_adjustable(FIX) 0 */
+#define tc_fix_adjustable(FIX) mn10300_fix_adjustable (FIX)
 extern bfd_boolean mn10300_fix_adjustable PARAMS ((struct fix *));
 
 /* We do relaxing in the assembler as well as the linker.  */
diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c
index 082a9164599a..6978b85a3e1a 100644
--- a/gas/config/tc-msp430.c
+++ b/gas/config/tc-msp430.c
@@ -1,6 +1,6 @@
 /* tc-msp430.c -- Assembler code for the Texas Instruments MSP430
 
-  Copyright (C) 2002, 2003 Free Software Foundation, Inc.
+  Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   Contributed by Dmitry Diky <diwil@mail.ru>
 
   This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to
-  the Free Software Foundation, 59 Temple Place - Suite 330,
-  Boston, MA 02111-1307, USA.  */
+  the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+  Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include <string.h>
@@ -30,6 +30,141 @@
 #include "subsegs.h"
 #include "opcode/msp430.h"
 #include "safe-ctype.h"
+#include "dwarf2dbg.h"
+
+/*
+   We will disable polymorphs by default because it is dangerous.
+   The potencial problem here is the following: assume we got the
+   following code:
+
+	jump .l1
+	nop
+	jump  subroutine	; external symbol
+      .l1:
+	nop
+	ret
+   
+   In case of assembly time relaxation we'll get:
+	0: jmp .l1 <.text +0x08> (reloc deleted)
+	2: nop
+	4: br subroutine
+    .l1:
+	8: nop
+	10: ret
+
+   If the 'subroutine' wiys thin +-1024 bytes range then linker
+   will produce
+	0: jmp .text +0x08
+	2: nop
+	4: jmp subroutine
+	.l1:
+	6: nop
+	8: ret	; 'jmp .text +0x08' will land here. WRONG!!!
+
+
+   The workaround is the following:
+   1. Declare global var enable_polymorphs which set to 1 via option -mP.
+   2. Declare global var enable_relax	which set to 1 via option -mQ.
+
+   If polymorphs are enabled, and relax isn't, treat all jumps as long jumps,
+   do not delete any relocs and leave them for linker.
+   
+   If relax is enabled, relax at assembly time and kill relocs as necessary.
+ */
+
+int msp430_enable_relax;
+int msp430_enable_polys;
+
+/* GCC uses the some condition codes which we'll
+   implement as new polymorph instructions.
+  
+   COND	EXPL	   SHORT JUMP	LONG JUMP
+   ===============================================
+   eq	==	   jeq 		jne +4; br lab
+   ne	!=	   jne 		jeq +4; br lab
+
+   ltn honours no-overflow flag
+   ltn	<	   jn 		jn +2;  jmp +4; br lab
+
+   lt	<	   jl 		jge +4;	br lab 
+   ltu	<	   jlo 		lhs +4; br lab
+   le	<= see below
+   leu	<= see below
+
+   gt	>  see below
+   gtu	>  see below
+   ge	>=	   jge 		jl +4; br lab
+   geu	>=	   jhs 		jlo +4; br lab
+   ===============================================
+
+   Therefore, new opcodes are (BranchEQ -> beq; and so on...)
+   beq,bne,blt,bltn,bltu,bge,bgeu
+   'u' means unsigned compares 
+  
+   Also, we add 'jump' instruction:
+   jump	UNCOND	-> jmp		br lab
+
+   They will have fmt == 4, and insn_opnumb == number of instruction.  */
+
+struct rcodes_s 
+{
+  char * name;
+  int    index;	/* Corresponding insn_opnumb.  */
+  int    sop;	/* Opcode if jump length is short.  */
+  long   lpos;	/* Label position.  */
+  long   lop0;	/* Opcode 1 _word_ (16 bits).  */
+  long   lop1;	/* Opcode second word.  */
+  long   lop2;	/* Opcode third word.  */
+};
+
+#define MSP430_RLC(n,i,sop,o1) \
+  {#n, i, sop, 2, (o1 + 2), 0x4010, 0}
+
+static struct rcodes_s msp430_rcodes[] = 
+{
+  MSP430_RLC (beq,  0, 0x2400, 0x2000),
+  MSP430_RLC (bne,  1, 0x2000, 0x2400),
+  MSP430_RLC (blt,  2, 0x3800, 0x3400),
+  MSP430_RLC (bltu, 3, 0x2800, 0x2c00),
+  MSP430_RLC (bge,  4, 0x3400, 0x3800),
+  MSP430_RLC (bgeu, 5, 0x2c00, 0x2800),
+  {"bltn",          6, 0x3000, 3, 0x3000 + 1, 0x3c00 + 2,0x4010},
+  {"jump",          7, 0x3c00, 1, 0x4010, 0, 0},
+  {0,0,0,0,0,0,0}
+};
+#undef MSP430_RLC
+
+
+/* More difficult than above and they have format 5.
+   
+   COND	EXPL	SHORT			LONG
+   =================================================================
+   gt	>	jeq +2; jge label	jeq +6; jl  +4; br label
+   gtu	>	jeq +2; jhs label	jeq +6; jlo +4; br label
+   leu	<=	jeq label; jlo label	jeq +2; jhs +4; br label
+   le	<=	jeq label; jl  label	jeq +2; jge +4; br label
+   =================================================================  */
+
+struct hcodes_s 
+{
+  char * name;	
+  int    index;		/* Corresponding insn_opnumb.  */
+  int    tlab;		/* Number of labels in short mode.  */
+  int    op0;		/* Opcode for first word of short jump.  */
+  int    op1;		/* Opcode for second word of short jump.  */
+  int    lop0;		/* Opcodes for long jump mode.  */
+  int    lop1;
+  int    lop2;
+};
+
+static struct hcodes_s msp430_hcodes[] = 
+{
+  {"bgt",  0, 1, 0x2401, 0x3400, 0x2403, 0x3802, 0x4010 },
+  {"bgtu", 1, 1, 0x2401, 0x2c00, 0x2403, 0x2802, 0x4010 },
+  {"bleu", 2, 2, 0x2400, 0x2800, 0x2401, 0x2c02, 0x4010 },
+  {"ble",  3, 2, 0x2400, 0x3800, 0x2401, 0x3402, 0x4010 },
+  {0,0,0,0,0,0,0,0}
+};
 
 const char comment_chars[] = ";";
 const char line_comment_chars[] = "#";
@@ -42,30 +177,67 @@ extern LITTLENUM_TYPE generic_bignum[];
 
 static struct hash_control *msp430_hash;
 
-static unsigned int msp430_operands
-  PARAMS ((struct msp430_opcode_s *, char *));
-static int msp430_srcoperand
-  PARAMS ((struct msp430_operand_s *, char *, int, int *));
-static int msp430_dstoperand
-  PARAMS ((struct msp430_operand_s *, char *, int));
-static char *parse_exp
-  PARAMS ((char *, expressionS *));
-static inline char *skip_space
-  PARAMS ((char *));
-static int check_reg
-  PARAMS ((char *));
-static void msp430_set_arch
-  PARAMS ((int));
-static void show_mcu_list
-  PARAMS ((FILE *));
-static void del_spaces
-  PARAMS ((char *));
+/* Relaxations.  */
+#define STATE_UNCOND_BRANCH	1	/* jump */
+#define STATE_NOOV_BRANCH	3	/* bltn */
+#define STATE_SIMPLE_BRANCH	2	/* bne, beq, etc... */
+#define STATE_EMUL_BRANCH	4
+
+#define CNRL	2
+#define CUBL	4
+#define CNOL	8
+#define CSBL	6
+#define CEBL	4
+
+/* Length.  */
+#define STATE_BITS10	1	/* wild guess. short jump */
+#define STATE_WORD	2	/* 2 bytes pc rel. addr. more */
+#define STATE_UNDEF	3	/* cannot handle this yet. convert to word mode */
+
+#define ENCODE_RELAX(what,length) (((what) << 2) + (length))
+#define RELAX_STATE(s)            ((s) & 3)
+#define RELAX_LEN(s)	          ((s) >> 2)
+#define RELAX_NEXT(a,b)	          ENCODE_RELAX (a, b + 1)
+
+relax_typeS md_relax_table[] =
+{
+  /* Unused.  */
+  {1, 1, 0, 0},
+  {1, 1, 0, 0},
+  {1, 1, 0, 0},
+  {1, 1, 0, 0},
+
+  /* Unconditional jump.  */
+  {1, 1, 8, 5},
+  {1024, -1024, CNRL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_BITS10)},	/* state 10 bits displ */
+  {0, 0, CUBL, RELAX_NEXT (STATE_UNCOND_BRANCH, STATE_WORD)},		/* state word */
+  {1, 1, CUBL, 0},							/* state undef */
+
+  /* Simple branches.  */
+  {0, 0, 8, 9},
+  {1024, -1024, CNRL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_BITS10)},	/* state 10 bits displ */
+  {0, 0, CSBL, RELAX_NEXT (STATE_SIMPLE_BRANCH, STATE_WORD)},		/* state word */
+  {1, 1, CSBL, 0},
+
+  /* blt no overflow branch.  */
+  {1, 1, 8, 13},
+  {1024, -1024, CNRL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_BITS10)},	/* state 10 bits displ */
+  {0, 0, CNOL, RELAX_NEXT (STATE_NOOV_BRANCH, STATE_WORD)},		/* state word */
+  {1, 1, CNOL, 0},
+
+  /* Emulated branches.  */
+  {1, 1, 8, 17},
+  {1020, -1020, CEBL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_BITS10)},	/* state 10 bits displ */
+  {0, 0, CNOL, RELAX_NEXT (STATE_EMUL_BRANCH, STATE_WORD)},		/* state word */
+  {1, 1, CNOL, 0}
+};
+
 
 #define MAX_OP_LEN	256
 
 struct mcu_type_s
 {
-  char *name;
+  char * name;
   int isa;
   int mach;
 };
@@ -77,6 +249,7 @@ struct mcu_type_s
 #define MSP430_ISA_14   14
 #define MSP430_ISA_15   15
 #define MSP430_ISA_16   16
+#define MSP430_ISA_21   21
 #define MSP430_ISA_31   31
 #define MSP430_ISA_32   32
 #define MSP430_ISA_33   33
@@ -90,62 +263,77 @@ struct mcu_type_s
 
 static struct mcu_type_s mcu_types[] =
 {
-  {"msp1",       MSP430_ISA_11, bfd_mach_msp11},
-  {"msp2",       MSP430_ISA_14, bfd_mach_msp14},
-  {"msp430x110", MSP430_ISA_11, bfd_mach_msp11},
-  {"msp430x112", MSP430_ISA_11, bfd_mach_msp11},
-  {"msp430x1101",MSP430_ISA_110, bfd_mach_msp110},
-  {"msp430x1111",MSP430_ISA_110, bfd_mach_msp110},
-  {"msp430x1121",MSP430_ISA_110, bfd_mach_msp110},
-  {"msp430x1122",MSP430_ISA_11, bfd_mach_msp110},
-  {"msp430x1132",MSP430_ISA_11, bfd_mach_msp110},
-
-  {"msp430x122", MSP430_ISA_12, bfd_mach_msp12},
-  {"msp430x123", MSP430_ISA_12, bfd_mach_msp12},
-  {"msp430x1222",MSP430_ISA_12, bfd_mach_msp12},
-  {"msp430x1232",MSP430_ISA_12, bfd_mach_msp12},
-
-  {"msp430x133", MSP430_ISA_13, bfd_mach_msp13},
-  {"msp430x135", MSP430_ISA_13, bfd_mach_msp13},
-  {"msp430x1331",MSP430_ISA_13, bfd_mach_msp13},
-  {"msp430x1351",MSP430_ISA_13, bfd_mach_msp13},
-  {"msp430x147", MSP430_ISA_14, bfd_mach_msp14},
-  {"msp430x148", MSP430_ISA_14, bfd_mach_msp14},
-  {"msp430x149", MSP430_ISA_14, bfd_mach_msp14},
-
-  {"msp430x155", MSP430_ISA_15, bfd_mach_msp15},
-  {"msp430x156", MSP430_ISA_15, bfd_mach_msp15},
-  {"msp430x157", MSP430_ISA_15, bfd_mach_msp15},
-  {"msp430x167", MSP430_ISA_16, bfd_mach_msp16},
-  {"msp430x168", MSP430_ISA_16, bfd_mach_msp16},
-  {"msp430x169", MSP430_ISA_16, bfd_mach_msp16},
-
-  {"msp430x311", MSP430_ISA_31, bfd_mach_msp31},
-  {"msp430x312", MSP430_ISA_31, bfd_mach_msp31},
-  {"msp430x313", MSP430_ISA_31, bfd_mach_msp31},
-  {"msp430x314", MSP430_ISA_31, bfd_mach_msp31},
-  {"msp430x315", MSP430_ISA_31, bfd_mach_msp31},
-  {"msp430x323", MSP430_ISA_32, bfd_mach_msp32},
-  {"msp430x325", MSP430_ISA_32, bfd_mach_msp32},
-  {"msp430x336", MSP430_ISA_33, bfd_mach_msp33},
-  {"msp430x337", MSP430_ISA_33, bfd_mach_msp33},
-
-  {"msp430x412", MSP430_ISA_41, bfd_mach_msp41},
-  {"msp430x413", MSP430_ISA_41, bfd_mach_msp41},
+  {"msp1",        MSP430_ISA_11, bfd_mach_msp11},
+  {"msp2",        MSP430_ISA_14, bfd_mach_msp14},
+  {"msp430x110",  MSP430_ISA_11, bfd_mach_msp11},
+  {"msp430x112",  MSP430_ISA_11, bfd_mach_msp11},
+  {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110},
+  {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110},
+  {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110},
+  {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110},
+  {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110},
+
+  {"msp430x122",  MSP430_ISA_12, bfd_mach_msp12},
+  {"msp430x123",  MSP430_ISA_12, bfd_mach_msp12},
+  {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12},
+  {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12},
+
+  {"msp430x133",  MSP430_ISA_13, bfd_mach_msp13},
+  {"msp430x135",  MSP430_ISA_13, bfd_mach_msp13},
+  {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13},
+  {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13},
+  {"msp430x147",  MSP430_ISA_14, bfd_mach_msp14},
+  {"msp430x148",  MSP430_ISA_14, bfd_mach_msp14},
+  {"msp430x149",  MSP430_ISA_14, bfd_mach_msp14},
+
+  {"msp430x155",  MSP430_ISA_15, bfd_mach_msp15},
+  {"msp430x156",  MSP430_ISA_15, bfd_mach_msp15},
+  {"msp430x157",  MSP430_ISA_15, bfd_mach_msp15},
+  {"msp430x167",  MSP430_ISA_16, bfd_mach_msp16},
+  {"msp430x168",  MSP430_ISA_16, bfd_mach_msp16},
+  {"msp430x169",  MSP430_ISA_16, bfd_mach_msp16},
+  {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16},
+  {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16},
+  {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16},
+
+  {"msp430x2101", MSP430_ISA_21, bfd_mach_msp21},
+  {"msp430x2111", MSP430_ISA_21, bfd_mach_msp21},
+  {"msp430x2121", MSP430_ISA_21, bfd_mach_msp21},
+  {"msp430x2131", MSP430_ISA_21, bfd_mach_msp21},
+  
+  {"msp430x311",  MSP430_ISA_31, bfd_mach_msp31},
+  {"msp430x312",  MSP430_ISA_31, bfd_mach_msp31},
+  {"msp430x313",  MSP430_ISA_31, bfd_mach_msp31},
+  {"msp430x314",  MSP430_ISA_31, bfd_mach_msp31},
+  {"msp430x315",  MSP430_ISA_31, bfd_mach_msp31},
+  {"msp430x323",  MSP430_ISA_32, bfd_mach_msp32},
+  {"msp430x325",  MSP430_ISA_32, bfd_mach_msp32},
+  {"msp430x336",  MSP430_ISA_33, bfd_mach_msp33},
+  {"msp430x337",  MSP430_ISA_33, bfd_mach_msp33},
+
+  {"msp430x412",  MSP430_ISA_41, bfd_mach_msp41},
+  {"msp430x413",  MSP430_ISA_41, bfd_mach_msp41},
+  {"msp430x415",  MSP430_ISA_41, bfd_mach_msp41},
+  {"msp430x417",  MSP430_ISA_41, bfd_mach_msp41},
 
   {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42},
   {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42},
   {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42},
+
   {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42},
   {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42},
   {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42},
 
-  {"msp430x435", MSP430_ISA_43, bfd_mach_msp43},
-  {"msp430x436", MSP430_ISA_43, bfd_mach_msp43},
-  {"msp430x437", MSP430_ISA_43, bfd_mach_msp43},
-  {"msp430x447", MSP430_ISA_44, bfd_mach_msp44},
-  {"msp430x448", MSP430_ISA_44, bfd_mach_msp44},
-  {"msp430x449", MSP430_ISA_44, bfd_mach_msp44},
+  {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43},
+  {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43},
+  {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43},
+
+  {"msp430x435",  MSP430_ISA_43, bfd_mach_msp43},
+  {"msp430x436",  MSP430_ISA_43, bfd_mach_msp43},
+  {"msp430x437",  MSP430_ISA_43, bfd_mach_msp43},
+  {"msp430x447",  MSP430_ISA_44, bfd_mach_msp44},
+  {"msp430x448",  MSP430_ISA_44, bfd_mach_msp44},
+  {"msp430x449",  MSP430_ISA_44, bfd_mach_msp44},
 
   {NULL, 0, 0}
 };
@@ -154,71 +342,346 @@ static struct mcu_type_s mcu_types[] =
 static struct mcu_type_s default_mcu =
     { "msp430x11", MSP430_ISA_11, bfd_mach_msp11 };
 
-static struct mcu_type_s *msp430_mcu = &default_mcu;
+static struct mcu_type_s * msp430_mcu = & default_mcu;
+
+/* Profiling capability:
+   It is a performance hit to use gcc's profiling approach for this tiny target.
+   Even more -- jtag hardware facility does not perform any profiling functions.
+   However we've got gdb's built-in simulator where we can do anything.
+   Therefore my suggestion is:
+
+   We define new section ".profiler" which holds all profiling information.
+   We define new pseudo operation .profiler which will instruct assembler to
+   add new profile entry to the object file. Profile should take place at the
+   present address.
+
+   Pseudo-op format:
+
+      .profiler flags,function_to_profile [, cycle_corrector, extra]
+
+   where 'flags' is a combination of the following chars:
+	    s - function Start
+	    x - function eXit
+	    i - function is in Init section
+	    f - function is in Fini section
+	    l - Library call
+	    c - libC standard call
+	    d - stack value Demand (saved at run-time in simulator)
+	    I - Interrupt service routine
+	    P - Prologue start
+	    p - Prologue end
+	    E - Epilogue start
+	    e - Epilogue end
+	    j - long Jump/ sjlj unwind
+	    a - an Arbitrary code fragment
+	    t - exTra parameter saved (constant value like frame size)
+	  '""' optional: "sil" == sil
+
+      function_to_profile - function's address
+      cycle_corrector     - a value which should be added to the cycle
+			      counter, zero if omitted
+      extra - some extra parameter, zero if omitted.
+
+      For example:
+      ------------------------------
+	.global fxx
+	.type fxx,@function
+      fxx:
+      .LFrameOffset_fxx=0x08
+      .profiler "scdP", fxx	; function entry.
+				; we also demand stack value to be displayed
+	push r11
+	push r10
+	push r9
+	push r8
+      .profiler "cdp",fxx,0, .LFrameOffset_fxx	; check stack value at this point
+						; (this is a prologue end)
+						; note, that spare var filled with the farme size
+	mov r15,r8
+	....
+      .profiler cdE,fxx		; check stack
+	pop r8
+	pop r9
+	pop r10
+	pop r11
+      .profiler xcde,fxx,3	; exit adds 3 to the cycle counter
+      ret			; cause 'ret' insn takes 3 cycles
+      -------------------------------
+
+      This profiling approach does not produce any overhead and
+      absolutely harmless.
+      So, even profiled code can be uploaded to the MCU.  */
+#define MSP430_PROFILER_FLAG_ENTRY	1	/* s */
+#define MSP430_PROFILER_FLAG_EXIT	2	/* x */
+#define MSP430_PROFILER_FLAG_INITSECT	4	/* i */
+#define MSP430_PROFILER_FLAG_FINISECT	8	/* f */
+#define MSP430_PROFILER_FLAG_LIBCALL	0x10	/* l */
+#define MSP430_PROFILER_FLAG_STDCALL	0x20	/* c */
+#define MSP430_PROFILER_FLAG_STACKDMD	0x40	/* d */
+#define MSP430_PROFILER_FLAG_ISR	0x80	/* I */
+#define MSP430_PROFILER_FLAG_PROLSTART	0x100	/* P */
+#define MSP430_PROFILER_FLAG_PROLEND	0x200	/* p */
+#define MSP430_PROFILER_FLAG_EPISTART	0x400	/* E */
+#define MSP430_PROFILER_FLAG_EPIEND	0x800	/* e */
+#define MSP430_PROFILER_FLAG_JUMP	0x1000	/* j */
+#define MSP430_PROFILER_FLAG_FRAGMENT	0x2000	/* a */
+#define MSP430_PROFILER_FLAG_EXTRA	0x4000	/* t */
+#define MSP430_PROFILER_FLAG_notyet	0x8000	/* ? */
 
-const pseudo_typeS md_pseudo_table[] =
+static int
+pow2value (int y)
 {
-  {"arch", msp430_set_arch, 0},
-  {NULL, NULL, 0}
-};
+  int n = 0;
+  unsigned int x;
 
-#define OPTION_MMCU 'm'
+  x = y;
 
-const char *md_shortopts = "m:";
+  if (!x)
+    return 1;
 
-struct option md_longopts[] =
+  for (; x; x = x >> 1)
+    if (x & 1)
+      n++;
+
+  return n == 1;
+}
+
+/* Parse ordinary expression.  */
+
+static char *
+parse_exp (char * s, expressionS * op)
 {
-  {"mmcu", required_argument, NULL, OPTION_MMCU},
-  {NULL, no_argument, NULL, 0}
-};
+  input_line_pointer = s;
+  expression (op);
+  if (op->X_op == O_absent)
+    as_bad (_("missing operand"));
+  return input_line_pointer;
+}
 
-size_t md_longopts_size = sizeof (md_longopts);
+
+/* Delete spaces from s: X ( r 1  2)  => X(r12).  */
 
 static void
-show_mcu_list (stream)
-     FILE *stream;
+del_spaces (char * s)
 {
-  int i;
+  while (*s)
+    {
+      if (ISSPACE (*s))
+	{
+	  char *m = s + 1;
 
-  fprintf (stream, _("Known MCU names:\n"));
+	  while (ISSPACE (*m) && *m)
+	    m++;
+	  memmove (s, m, strlen (m) + 1);
+	}
+      else
+	s++;
+    }
+}
 
-  for (i = 0; mcu_types[i].name; i++)
-    fprintf (stream, _("\t %s\n"), mcu_types[i].name);
+static inline char *
+skip_space (char * s)
+{
+  while (ISSPACE (*s))
+    ++s;
+  return s;
+}
 
-  fprintf (stream, "\n");
+/* Extract one word from FROM and copy it to TO. Delimeters are ",;\n"  */
+
+static char *
+extract_operand (char * from, char * to, int limit)
+{
+  int size = 0;
+
+  /* Drop leading whitespace.  */
+  from = skip_space (from);
+
+  while (size < limit && *from)
+    {
+      *(to + size) = *from;
+      if (*from == ',' || *from == ';' || *from == '\n')
+	break;
+      from++;
+      size++;
+    }
+
+  *(to + size) = 0;
+  del_spaces (to);
+
+  from++;
+
+  return from;
 }
 
-void
-md_show_usage (stream)
-     FILE *stream;
+static void
+msp430_profiler (int dummy ATTRIBUTE_UNUSED)
 {
-  fprintf (stream,
-	   _("MSP430 options:\n"
-	     "  -mmcu=[msp430-name] select microcontroller type\n"
-	     "                  msp430x110  msp430x112\n"
-	     "                  msp430x1101 msp430x1111\n"
-	     "                  msp430x1121 msp430x1122 msp430x1132\n"
-	     "                  msp430x122  msp430x123\n"
-	     "                  msp430x1222 msp430x1232\n"
-	     "                  msp430x133  msp430x135\n"
-	     "                  msp430x1331 msp430x1351\n"
-	     "                  msp430x147  msp430x148  msp430x149\n"
-	     "                  msp430x155  msp430x156  msp430x157\n"
-	     "                  msp430x167  msp430x168  msp430x169\n"
-	     "                  msp430x311  msp430x312  msp430x313  msp430x314  msp430x315\n"
-	     "                  msp430x323  msp430x325\n"
-	     "                  msp430x336  msp430x337\n"
-	     "                  msp430x412  msp430x413\n"
-	     "                  msp430xE423 msp430xE425 msp430E427\n"
-	     "                  msp430xW423 msp430xW425 msp430W427\n"
-	     "                  msp430x435  msp430x436  msp430x437\n"
-	     "                  msp430x447  msp430x448  msp430x449\n"));
+  char   buffer[1024];
+  char   f[32];
+  char * str = buffer;
+  char * flags = f;
+  int    p_flags = 0;
+  char * halt;
+  int    ops = 0;
+  int    left;
+  char * s;
+  segT   seg;
+  int    subseg;
+  char * end = 0;
+  expressionS exp;
+  expressionS exp1;
+
+  s = input_line_pointer;
+  end = input_line_pointer;
+
+  while (*end && *end != '\n')
+    end++;
+
+  while (*s && *s != '\n')
+    {
+      if (*s == ',')
+	ops++;
+      s++;
+    }
 
-  show_mcu_list (stream);
+  left = 3 - ops;
+
+  if (ops < 1)
+    {
+      as_bad (_(".profiler pseudo requires at least two operands."));
+      input_line_pointer = end;
+      return;
+    }
+
+  input_line_pointer = extract_operand (input_line_pointer, flags, 32);
+
+  while (*flags)
+    {
+      switch (*flags)
+	{
+	case '"':
+	  break;
+	case 'a':
+	  p_flags |= MSP430_PROFILER_FLAG_FRAGMENT;
+	  break;
+	case 'j':
+	  p_flags |= MSP430_PROFILER_FLAG_JUMP;
+	  break;
+	case 'P':
+	  p_flags |= MSP430_PROFILER_FLAG_PROLSTART;
+	  break;
+	case 'p':
+	  p_flags |= MSP430_PROFILER_FLAG_PROLEND;
+	  break;
+	case 'E':
+	  p_flags |= MSP430_PROFILER_FLAG_EPISTART;
+	  break;
+	case 'e':
+	  p_flags |= MSP430_PROFILER_FLAG_EPIEND;
+	  break;
+	case 's':
+	  p_flags |= MSP430_PROFILER_FLAG_ENTRY;
+	  break;
+	case 'x':
+	  p_flags |= MSP430_PROFILER_FLAG_EXIT;
+	  break;
+	case 'i':
+	  p_flags |= MSP430_PROFILER_FLAG_INITSECT;
+	  break;
+	case 'f':
+	  p_flags |= MSP430_PROFILER_FLAG_FINISECT;
+	  break;
+	case 'l':
+	  p_flags |= MSP430_PROFILER_FLAG_LIBCALL;
+	  break;
+	case 'c':
+	  p_flags |= MSP430_PROFILER_FLAG_STDCALL;
+	  break;
+	case 'd':
+	  p_flags |= MSP430_PROFILER_FLAG_STACKDMD;
+	  break;
+	case 'I':
+	  p_flags |= MSP430_PROFILER_FLAG_ISR;
+	  break;
+	case 't':
+	  p_flags |= MSP430_PROFILER_FLAG_EXTRA;
+	  break;
+	default:
+	  as_warn (_("unknown profiling flag - ignored."));
+	  break;
+	}
+      flags++;
+    }
+
+  if (p_flags
+      && (   ! pow2value (p_flags & (  MSP430_PROFILER_FLAG_ENTRY
+				     | MSP430_PROFILER_FLAG_EXIT))
+	  || ! pow2value (p_flags & (  MSP430_PROFILER_FLAG_PROLSTART
+				     | MSP430_PROFILER_FLAG_PROLEND
+				     | MSP430_PROFILER_FLAG_EPISTART
+				     | MSP430_PROFILER_FLAG_EPIEND))
+	  || ! pow2value (p_flags & (  MSP430_PROFILER_FLAG_INITSECT
+				     | MSP430_PROFILER_FLAG_FINISECT))))
+    {
+      as_bad (_("ambigious flags combination - '.profiler' directive ignored."));
+      input_line_pointer = end;
+      return;
+    }
+
+  /* Generate temp symbol which denotes current location.  */
+  if (now_seg == absolute_section)	/* Paranoja ?  */
+    {
+      exp1.X_op = O_constant;
+      exp1.X_add_number = abs_section_offset;
+      as_warn (_("profiling in absolute section? Hm..."));
+    }
+  else
+    {
+      exp1.X_op = O_symbol;
+      exp1.X_add_symbol = symbol_temp_new_now ();
+      exp1.X_add_number = 0;
+    }
+
+  /* Generate a symbol which holds flags value.  */
+  exp.X_op = O_constant;
+  exp.X_add_number = p_flags;
+
+  /* Save current section.  */
+  seg = now_seg;
+  subseg = now_subseg;
+
+  /* Now go to .profiler section.  */
+  obj_elf_change_section (".profiler", SHT_PROGBITS, 0, 0, 0, 0, 0);
+
+  /* Save flags.  */
+  emit_expr (& exp, 2);
+
+  /* Save label value.  */
+  emit_expr (& exp1, 2);
+
+  while (ops--)
+    {
+      /* Now get profiling info.  */
+      halt = extract_operand (input_line_pointer, str, 1024);
+      /* Process like ".word xxx" directive.  */
+      parse_exp (str, & exp);
+      emit_expr (& exp, 2);
+      input_line_pointer = halt;
+    }
+
+  /* Fill the rest with zeros.  */
+  exp.X_op = O_constant;
+  exp.X_add_number = 0;
+  while (left--)
+    emit_expr (& exp, 2);
+
+  /* Return to current section.  */
+  subseg_set (seg, subseg);
 }
 
 static char *
-extract_word (char *from, char *to, int limit)
+extract_word (char * from, char * to, int limit)
 {
   char *op_start;
   char *op_end;
@@ -240,9 +703,12 @@ extract_word (char *from, char *to, int limit)
   return op_end;
 }
 
+#define OPTION_MMCU 'm'
+#define OPTION_RELAX 'Q'
+#define OPTION_POLYMORPHS 'P'
+
 static void
-msp430_set_arch (dummy)
-     int dummy ATTRIBUTE_UNUSED;
+msp430_set_arch (int dummy ATTRIBUTE_UNUSED)
 {
   char *str = (char *) alloca (32);	/* 32 for good measure.  */
 
@@ -252,10 +718,21 @@ msp430_set_arch (dummy)
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);
 }
 
+static void
+show_mcu_list (FILE * stream)
+{
+  int i;
+
+  fprintf (stream, _("Known MCU names:\n"));
+
+  for (i = 0; mcu_types[i].name; i++)
+    fprintf (stream, _("\t %s\n"), mcu_types[i].name);
+
+  fprintf (stream, "\n");
+}
+
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char * arg)
 {
   int i;
 
@@ -278,77 +755,83 @@ md_parse_option (c, arg)
 	as_fatal (_("redefinition of mcu type %s' to %s'"),
 		  msp430_mcu->name, mcu_types[i].name);
       return 1;
+      break;
+      
+    case OPTION_RELAX:
+      msp430_enable_relax = 1; 
+      return 1;
+      break;
+      
+    case OPTION_POLYMORPHS:
+      msp430_enable_polys = 1;
+      return 1;
+      break;
     }
 
   return 0;
 }
 
-symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
 
-static inline char *
-skip_space (s)
-     char *s;
+const pseudo_typeS md_pseudo_table[] =
 {
-  while (ISSPACE (*s))
-    ++s;
-  return s;
-}
+  {"arch", msp430_set_arch, 0},
+  {"profiler", msp430_profiler, 0},
+  {NULL, NULL, 0}
+};
 
-/* Delete spaces from s: X ( r 1  2)  => X(r12).  */
+const char *md_shortopts = "m:";
 
-static void
-del_spaces (s)
-     char *s;
+struct option md_longopts[] =
 {
-  while (*s)
-    {
-      if (ISSPACE (*s))
-	{
-	  char *m = s + 1;
-
-	  while (ISSPACE (*m) && *m)
-	    m++;
-	  memmove (s, m, strlen (m) + 1);
-	}
-      else
-	s++;
-    }
-}
+  {"mmcu", required_argument, NULL, OPTION_MMCU},
+  {"mP", no_argument, NULL, OPTION_POLYMORPHS},
+  {"mQ", no_argument, NULL, OPTION_RELAX},
+  {NULL, no_argument, NULL, 0}
+};
 
-/* Extract one word from FROM and copy it to TO. Delimeters are ",;\n"  */
+size_t md_longopts_size = sizeof (md_longopts);
 
-static char *
-extract_operand (char *from, char *to, int limit)
+void
+md_show_usage (FILE * stream)
 {
-  int size = 0;
-
-  /* Drop leading whitespace.  */
-  from = skip_space (from);
-
-  while (size < limit && *from)
-    {
-      *(to + size) = *from;
-      if (*from == ',' || *from == ';' || *from == '\n')
-	break;
-      from++;
-      size++;
-    }
-
-  *(to + size) = 0;
-  del_spaces (to);
+  fprintf (stream,
+	   _("MSP430 options:\n"
+	     "  -mmcu=[msp430-name] select microcontroller type\n"
+	     "                  msp430x110  msp430x112\n"
+	     "                  msp430x1101 msp430x1111\n"
+	     "                  msp430x1121 msp430x1122 msp430x1132\n"
+	     "                  msp430x122  msp430x123\n"
+	     "                  msp430x1222 msp430x1232\n"
+	     "                  msp430x133  msp430x135\n"
+	     "                  msp430x1331 msp430x1351\n"
+	     "                  msp430x147  msp430x148  msp430x149\n"
+	     "                  msp430x155  msp430x156  msp430x157\n"
+	     "                  msp430x167  msp430x168  msp430x169\n"
+	     "                  msp430x1610 msp430x1611 msp430x1612\n"
+	     "                  msp430x311  msp430x312  msp430x313  msp430x314  msp430x315\n"
+	     "                  msp430x323  msp430x325\n"
+	     "                  msp430x336  msp430x337\n"
+	     "                  msp430x412  msp430x413  msp430x415  msp430x417\n"
+	     "                  msp430xE423 msp430xE425 msp430E427\n"
+	     "                  msp430xW423 msp430xW425 msp430W427\n"
+	     "                  msp430xG437 msp430xG438 msp430G439\n"
+	     "                  msp430x435  msp430x436  msp430x437\n"
+	     "                  msp430x447  msp430x448  msp430x449\n"));
+  fprintf (stream,
+	   _("  -mQ - enable relaxation at assembly time. DANGEROUS!\n"
+	     "  -mP - enable polymorph instructions\n"));
 
-  from++;
+  show_mcu_list (stream);
+}
 
-  return from;
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+  return 0;
 }
 
 static char *
-extract_cmd (char *from, char *to, int limit)
+extract_cmd (char * from, char * to, int limit)
 {
   int size = 0;
 
@@ -370,10 +853,7 @@ extract_cmd (char *from, char *to, int limit)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char * litP, int * sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -410,18 +890,9 @@ md_atof (type, litP, sizeP)
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
-{
-  abort ();
-}
-
-void
-md_begin ()
+md_begin (void)
 {
-  struct msp430_opcode_s *opcode;
+  struct msp430_opcode_s * opcode;
   msp430_hash = hash_new ();
 
   for (opcode = msp430_opcodes; opcode->name; opcode++)
@@ -430,424 +901,8 @@ md_begin ()
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, msp430_mcu->mach);
 }
 
-void
-md_assemble (str)
-     char *str;
-{
-  struct msp430_opcode_s *opcode;
-  char cmd[32];
-  unsigned int i = 0;
-
-  str = skip_space (str);	/* Skip leading spaces.  */
-  str = extract_cmd (str, cmd, sizeof (cmd));
-
-  while (cmd[i] && i < sizeof (cmd))
-    {
-      char a = TOLOWER (cmd[i]);
-      cmd[i] = a;
-      i++;
-    }
-
-  if (!cmd[0])
-    {
-      as_bad (_("can't find opcode "));
-      return;
-    }
-
-  opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);
-
-  if (opcode == NULL)
-    {
-      as_bad (_("unknown opcode `%s'"), cmd);
-      return;
-    }
-
-  {
-    char *__t = input_line_pointer;
-    msp430_operands (opcode, str);
-    input_line_pointer = __t;
-  }
-}
-
-/* Parse instruction operands.
-   Return binary opcode.  */
-
-static unsigned int
-msp430_operands (opcode, line)
-     struct msp430_opcode_s *opcode;
-     char *line;
-{
-  int bin = opcode->bin_opcode;	/* opcode mask.  */
-  int __is;
-  char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
-  char *frag;
-  int where;
-  struct msp430_operand_s op1, op2;
-  int res = 0;
-  static short ZEROS = 0;
-  int byte_op, imm_op;
-
-  /* opcode is the one from opcodes table
-     line contains something like
-     [.w] @r2+, 5(R1)
-     or
-     .b @r2+, 5(R1).  */
-
-  /* Check if byte or word operation.  */
-  if (*line == '.' && TOLOWER (*(line + 1)) == 'b')
-    {
-      bin |= BYTE_OPERATION;
-      byte_op = 1;
-    }
-  else
-    byte_op = 0;
-
-  /* skip .[bwBW].  */
-  while (! ISSPACE (*line) && *line)
-    line++;
-
-  if (opcode->insn_opnumb && (!*line || *line == '\n'))
-    {
-      as_bad (_("instruction %s requires %d operand(s)"),
-	      opcode->name, opcode->insn_opnumb);
-      return 0;
-    }
-
-  memset (l1, 0, sizeof (l1));
-  memset (l2, 0, sizeof (l2));
-  memset (&op1, 0, sizeof (op1));
-  memset (&op2, 0, sizeof (op2));
-
-  imm_op = 0;
-
-  switch (opcode->fmt)
-    {
-    case 0:			/* Emulated.  */
-      switch (opcode->insn_opnumb)
-	{
-	case 0:
-	  /* Set/clear bits instructions.  */
-	  __is = 2;
-	  frag = frag_more (__is);
-	  bfd_putl16 ((bfd_vma) bin, frag);
-	  break;
-	case 1:
-	  /* Something which works with destination operand.  */
-	  line = extract_operand (line, l1, sizeof (l1));
-	  res = msp430_dstoperand (&op1, l1, opcode->bin_opcode);
-	  if (res)
-	    break;
-
-	  bin |= (op1.reg | (op1.am << 7));
-	  __is = 1 + op1.ol;
-	  frag = frag_more (2 * __is);
-	  where = frag - frag_now->fr_literal;
-	  bfd_putl16 ((bfd_vma) bin, frag);
-
-	  if (op1.mode == OP_EXP)
-	    {
-	      where += 2;
-	      bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
-
-	      if (op1.reg)
-		fix_new_exp (frag_now, where, 2,
-			     &(op1.exp), FALSE, CHECK_RELOC_MSP430);
-	      else
-		fix_new_exp (frag_now, where, 2,
-			     &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	    }
-	  break;
-
-	case 2:
-	  {
-	    /* Shift instruction.  */
-	    line = extract_operand (line, l1, sizeof (l1));
-	    strncpy (l2, l1, sizeof (l2));
-	    l2[sizeof (l2) - 1] = '\0';
-	    res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
-	    res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
-
-	    if (res)
-	      break;	/* An error occurred.  All warnings were done before.  */
-
-	    bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
-
-	    __is = 1 + op1.ol + op2.ol;	/* insn size in words.  */
-	    frag = frag_more (2 * __is);
-	    where = frag - frag_now->fr_literal;
-	    bfd_putl16 ((bfd_vma) bin, frag);
-
-	    if (op1.mode == OP_EXP)
-	      {
-		where += 2;	/* Advance 'where' as we do not know _where_.  */
-		bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
-
-		if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
-		  fix_new_exp (frag_now, where, 2,
-			       &(op1.exp), FALSE, CHECK_RELOC_MSP430);
-		else
-		  fix_new_exp (frag_now, where, 2,
-			       &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	      }
-
-	    if (op2.mode == OP_EXP)
-	      {
-		imm_op = 0;
-		bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));
-
-		if (op2.reg)	/* Not PC relative.  */
-		  fix_new_exp (frag_now, where + 2, 2,
-			       &(op2.exp), FALSE, CHECK_RELOC_MSP430);
-		else
-		  fix_new_exp (frag_now, where + 2, 2,
-			       &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	      }
-	    break;
-	  }
-	case 3:
-	  /* Branch instruction => mov dst, r0.  */
-	  line = extract_operand (line, l1, sizeof (l1));
-
-	  res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
-	  if (res)
-	    break;
-
-	  byte_op = 0;
-	  imm_op = 0;
-
-	  bin |= ((op1.reg << 8) | (op1.am << 4));
-	  __is = 1 + op1.ol;
-	  frag = frag_more (2 * __is);
-	  where = frag - frag_now->fr_literal;
-	  bfd_putl16 ((bfd_vma) bin, frag);
-
-	  if (op1.mode == OP_EXP)
-	    {
-	      where += 2;
-	      bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
-
-	      if (op1.reg || (op1.reg == 0 && op1.am == 3))
-		fix_new_exp (frag_now, where, 2,
-			     &(op1.exp), FALSE, CHECK_RELOC_MSP430);
-	      else
-		fix_new_exp (frag_now, where, 2,
-			     &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	    }
-	  break;
-	}
-      break;
-
-    case 1:			/* Format 1, double operand.  */
-      line = extract_operand (line, l1, sizeof (l1));
-      line = extract_operand (line, l2, sizeof (l2));
-      res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
-      res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
-
-      if (res)
-	break;			/* Error occurred.  All warnings were done before.  */
-
-      bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
-
-      __is = 1 + op1.ol + op2.ol;	/* insn size in words.  */
-      frag = frag_more (2 * __is);
-      where = frag - frag_now->fr_literal;
-      bfd_putl16 ((bfd_vma) bin, frag);
-
-      if (op1.mode == OP_EXP)
-	{
-	  where += 2;		/* Advance where as we do not know _where_.  */
-	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
-
-	  if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
-	    fix_new_exp (frag_now, where, 2,
-			 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
-	  else
-	    fix_new_exp (frag_now, where, 2,
-			 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	}
-
-      if (op2.mode == OP_EXP)
-	{
-	  imm_op = 0;
-	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));
-
-	  if (op2.reg)		/* Not PC relative.  */
-	    fix_new_exp (frag_now, where + 2, 2,
-			 &(op2.exp), FALSE, CHECK_RELOC_MSP430);
-	  else
-	    fix_new_exp (frag_now, where + 2, 2,
-			 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	}
-      break;
-
-    case 2:			/* Single-operand mostly instr.  */
-      if (opcode->insn_opnumb == 0)
-	{
-	  /* reti instruction.  */
-	  frag = frag_more (2);
-	  bfd_putl16 ((bfd_vma) bin, frag);
-	  break;
-	}
-
-      line = extract_operand (line, l1, sizeof (l1));
-      res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
-      if (res)
-	break;		/* Error in operand.  */
-
-      bin |= op1.reg | (op1.am << 4);
-      __is = 1 + op1.ol;
-      frag = frag_more (2 * __is);
-      where = frag - frag_now->fr_literal;
-      bfd_putl16 ((bfd_vma) bin, frag);
-
-      if (op1.mode == OP_EXP)
-	{
-	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
-
-	  if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
-	    fix_new_exp (frag_now, where + 2, 2,
-			 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
-	  else
-	    fix_new_exp (frag_now, where + 2, 2,
-			 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
-	}
-      break;
-
-    case 3:			/* Conditional jumps instructions.  */
-      line = extract_operand (line, l1, sizeof (l1));
-      /* l1 is a label.  */
-      if (l1[0])
-	{
-	  char *m = l1;
-	  expressionS exp;
-
-	  if (*m == '$')
-	    m++;
-
-	  parse_exp (m, &exp);
-	  frag = frag_more (2);	/* Instr size is 1 word.  */
-
-	  /* In order to handle something like:
-
-	     and #0x8000, r5
-	     tst r5
-	     jz   4     ;       skip next 4 bytes
-	     inv r5
-	     inc r5
-	     nop        ;       will jump here if r5 positive or zero
-
-	     jCOND      -n      ;assumes jump n bytes backward:
-
-	     mov r5,r6
-	     jmp -2
-
-	     is equal to:
-	     lab:
-	     mov r5,r6
-	     jmp lab
-
-	     jCOND      $n      ; jump from PC in either direction.  */
-
-	  if (exp.X_op == O_constant)
-	    {
-	      int x = exp.X_add_number;
-
-	      if (x & 1)
-		{
-		  as_warn (_("Even number required. Rounded to %d"), x + 1);
-		  x++;
-		}
-
-	      if ((*l1 == '$' && x > 0) || x < 0)
-		x -= 2;
-
-	      x >>= 1;
-
-	      if (x > 512 || x < -511)
-		{
-		  as_bad (_("Wrong displacement  %d"), x << 1);
-		  break;
-		}
-
-	      bin |= x & 0x3ff;
-	      bfd_putl16 ((bfd_vma) bin, frag);
-	    }
-	  else if (exp.X_op == O_symbol && *l1 != '$')
-	    {
-	      where = frag - frag_now->fr_literal;
-	      fix_new_exp (frag_now, where, 2,
-			   &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
-
-	      bfd_putl16 ((bfd_vma) bin, frag);
-	    }
-	  else if (*l1 == '$')
-	    {
-	      as_bad (_("instruction requires label sans '$'"));
-	      break;
-	    }
-	  else
-	    {
-	      as_bad (_
-		      ("instruction requires label or value in range -511:512"));
-	      break;
-	    }
-	}
-      else
-	{
-	  as_bad (_("instruction requires label"));
-	  break;
-	}
-      break;
-
-    default:
-      as_bad (_("Ilegal instruction or not implmented opcode."));
-    }
-
-  input_line_pointer = line;
-  return 0;
-}
-
 static int
-msp430_dstoperand (op, l, bin)
-     struct msp430_operand_s *op;
-     char *l;
-     int bin;
-{
-  int dummy;
-  int ret = msp430_srcoperand (op, l, bin, &dummy);
-  if (ret)
-    return ret;
-
-  if (op->am == 2)
-    {
-      char *__tl = "0";
-
-      op->mode = OP_EXP;
-      op->am = 1;
-      op->ol = 1;
-      parse_exp (__tl, &(op->exp));
-      if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
-	{
-	  as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
-		  op->reg, op->reg);
-	  return 1;
-	}
-      return 0;
-    }
-
-  if (op->am > 1)
-    {
-      as_bad (_
-	      ("this addressing mode is not applicable for destination operand"));
-      return 1;
-    }
-  return 0;
-}
-
-
-static int
-check_reg (t)
-     char *t;
+check_reg (char * t)
 {
   /* If this is a reg numb, str 't' must be a number from 0 - 15.  */
 
@@ -869,11 +924,8 @@ check_reg (t)
 
 
 static int
-msp430_srcoperand (op, l, bin, imm_op)
-     struct msp430_operand_s *op;
-     char *l;
-     int bin;
-     int *imm_op;
+msp430_srcoperand (struct msp430_operand_s * op,
+		   char * l, int bin, int * imm_op)
 {
   char *__tl = l;
 
@@ -929,6 +981,7 @@ msp430_srcoperand (op, l, bin, imm_op)
       op->ol = 1;		/* Immediate  will follow an instruction.  */
       __tl = h + 1 + rval;
       op->mode = OP_EXP;
+
       parse_exp (__tl, &(op->exp));
       if (op->exp.X_op == O_constant)
 	{
@@ -955,7 +1008,7 @@ msp430_srcoperand (op, l, bin, imm_op)
 
 	  if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)
 	    {
-	      as_bad (_("value %ld out of range. Use #lo() or #hi()"), x);
+	      as_bad (_("value %d out of range. Use #lo() or #hi()"), x);
 	      return 1;
 	    }
 
@@ -1091,10 +1144,13 @@ msp430_srcoperand (op, l, bin, imm_op)
 	      op->mode = OP_REG;
 	    }
 	}
+      /* Redudant (yet) check.  */
+      else if (op->exp.X_op == O_register)
+	as_bad
+	  (_("Registers cannot be used within immediate expression [%s]"), l);
       else
-	{
-	  as_bad (_("unknown operand %s"), l);
-	}
+	as_bad (_("unknown operand %s"), l);
+
       return 0;
     }
 
@@ -1112,6 +1168,7 @@ msp430_srcoperand (op, l, bin, imm_op)
       if (op->exp.X_op == O_constant)
 	{
 	  int x = op->exp.X_add_number;
+
 	  if (x > 65535 || x < -32768)
 	    {
 	      as_bad (_("value out of range: %d"), x);
@@ -1119,11 +1176,15 @@ msp430_srcoperand (op, l, bin, imm_op)
 	    }
 	}
       else if (op->exp.X_op == O_symbol)
-	{
-	}
+	;
       else
 	{
-	  as_bad (_("unknown expression in operand %s"), l);
+	  /* Redudant (yet) check.  */
+	  if (op->exp.X_op == O_register)
+	    as_bad
+	      (_("Registers cannot be used within absolute expression [%s]"), l);
+	  else
+	    as_bad (_("unknown expression in operand %s"), l);
 	  return 1;
 	}
       return 0;
@@ -1258,11 +1319,15 @@ msp430_srcoperand (op, l, bin, imm_op)
 	    }
 	}
       else if (op->exp.X_op == O_symbol)
-	{
-	}
+	;
       else
 	{
-	  as_bad (_("unknown expression in operand %s"), l);
+	  /* Redudant (yet) check.  */
+	  if (op->exp.X_op == O_register)
+	    as_bad
+	      (_("Registers cannot be used as a prefix of indexed expression [%s]"), l);
+	  else
+	    as_bad (_("unknown expression in operand %s"), l);
 	  return 1;
 	}
 
@@ -1298,21 +1363,6 @@ msp430_srcoperand (op, l, bin, imm_op)
   /* Symbolic mode 'mov a, b' == 'mov x(pc), y(pc)'.  */
   do
     {
-      char *t = l;
-
-      __tl = l;
-
-      while (*t)
-	{
-	  /* alpha/number    underline     dot for labels.  */
-	  if (! ISALNUM (*t) && *t != '_' && *t != '.')
-	    {
-	      as_bad (_("unknown operand %s"), l);
-	      return 1;
-	    }
-	  t++;
-	}
-
       op->mode = OP_EXP;
       op->reg = 0;		/* PC relative... be careful.  */
       op->am = 1;
@@ -1329,13 +1379,511 @@ msp430_srcoperand (op, l, bin, imm_op)
 }
 
 
+static int
+msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin)
+{
+  int dummy;
+  int ret = msp430_srcoperand (op, l, bin, & dummy);
+
+  if (ret)
+    return ret;
+
+  if (op->am == 2)
+    {
+      char *__tl = "0";
+
+      op->mode = OP_EXP;
+      op->am = 1;
+      op->ol = 1;
+      parse_exp (__tl, &(op->exp));
+
+      if (op->exp.X_op != O_constant || op->exp.X_add_number != 0)
+	{
+	  as_bad (_("Internal bug. Try to use 0(r%d) instead of @r%d"),
+		  op->reg, op->reg);
+	  return 1;
+	}
+      return 0;
+    }
+
+  if (op->am > 1)
+    {
+      as_bad (_
+	      ("this addressing mode is not applicable for destination operand"));
+      return 1;
+    }
+  return 0;
+}
+
+
+/* Parse instruction operands.
+   Return binary opcode.  */
+
+static unsigned int
+msp430_operands (struct msp430_opcode_s * opcode, char * line)
+{
+  int bin = opcode->bin_opcode;	/* Opcode mask.  */
+  int __is = 0;
+  char l1[MAX_OP_LEN], l2[MAX_OP_LEN];
+  char *frag;
+  int where;
+  struct msp430_operand_s op1, op2;
+  int res = 0;
+  static short ZEROS = 0;
+  int byte_op, imm_op;
+
+  /* Opcode is the one from opcodes table
+     line contains something like
+     [.w] @r2+, 5(R1)
+     or
+     .b @r2+, 5(R1).  */
+
+  /* Check if byte or word operation.  */
+  if (*line == '.' && TOLOWER (*(line + 1)) == 'b')
+    {
+      bin |= BYTE_OPERATION;
+      byte_op = 1;
+    }
+  else
+    byte_op = 0;
+
+  /* skip .[bwBW].  */
+  while (! ISSPACE (*line) && *line)
+    line++;
+
+  if (opcode->insn_opnumb && (!*line || *line == '\n'))
+    {
+      as_bad (_("instruction %s requires %d operand(s)"),
+	      opcode->name, opcode->insn_opnumb);
+      return 0;
+    }
+
+  memset (l1, 0, sizeof (l1));
+  memset (l2, 0, sizeof (l2));
+  memset (&op1, 0, sizeof (op1));
+  memset (&op2, 0, sizeof (op2));
+
+  imm_op = 0;
+
+  switch (opcode->fmt)
+    {
+    case 0:			/* Emulated.  */
+      switch (opcode->insn_opnumb)
+	{
+	case 0:
+	  /* Set/clear bits instructions.  */
+	  __is = 2;
+	  frag = frag_more (__is);
+	  bfd_putl16 ((bfd_vma) bin, frag);
+	  dwarf2_emit_insn (__is);
+	  break;
+	case 1:
+	  /* Something which works with destination operand.  */
+	  line = extract_operand (line, l1, sizeof (l1));
+	  res = msp430_dstoperand (&op1, l1, opcode->bin_opcode);
+	  if (res)
+	    break;
+
+	  bin |= (op1.reg | (op1.am << 7));
+	  __is = 1 + op1.ol;
+	  frag = frag_more (2 * __is);
+	  where = frag - frag_now->fr_literal;
+	  bfd_putl16 ((bfd_vma) bin, frag);
+	  dwarf2_emit_insn (2 * __is);
+
+	  if (op1.mode == OP_EXP)
+	    {
+	      where += 2;
+	      bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+
+	      if (op1.reg)
+		fix_new_exp (frag_now, where, 2,
+			     &(op1.exp), FALSE, CHECK_RELOC_MSP430);
+	      else
+		fix_new_exp (frag_now, where, 2,
+			     &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	    }
+	  break;
+
+	case 2:
+	  {
+	    /* Shift instruction.  */
+	    line = extract_operand (line, l1, sizeof (l1));
+	    strncpy (l2, l1, sizeof (l2));
+	    l2[sizeof (l2) - 1] = '\0';
+	    res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
+	    res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
+
+	    if (res)
+	      break;	/* An error occurred.  All warnings were done before.  */
+
+	    bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
+
+	    __is = 1 + op1.ol + op2.ol;	/* insn size in words.  */
+	    frag = frag_more (2 * __is);
+	    where = frag - frag_now->fr_literal;
+	    bfd_putl16 ((bfd_vma) bin, frag);
+	    dwarf2_emit_insn (2 * __is);
+	    
+	    if (op1.mode == OP_EXP)
+	      {
+		where += 2;	/* Advance 'where' as we do not know _where_.  */
+		bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+
+		if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
+		  fix_new_exp (frag_now, where, 2,
+			       &(op1.exp), FALSE, CHECK_RELOC_MSP430);
+		else
+		  fix_new_exp (frag_now, where, 2,
+			       &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	      }
+
+	    if (op2.mode == OP_EXP)
+	      {
+		imm_op = 0;
+		bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));
+
+		if (op2.reg)	/* Not PC relative.  */
+		  fix_new_exp (frag_now, where + 2, 2,
+			       &(op2.exp), FALSE, CHECK_RELOC_MSP430);
+		else
+		  fix_new_exp (frag_now, where + 2, 2,
+			       &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	      }
+	    break;
+	  }
+	case 3:
+	  /* Branch instruction => mov dst, r0.  */
+	  line = extract_operand (line, l1, sizeof (l1));
+
+	  res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
+	  if (res)
+	    break;
+
+	  byte_op = 0;
+	  imm_op = 0;
+
+	  bin |= ((op1.reg << 8) | (op1.am << 4));
+	  __is = 1 + op1.ol;
+	  frag = frag_more (2 * __is);
+	  where = frag - frag_now->fr_literal;
+	  bfd_putl16 ((bfd_vma) bin, frag);
+	  dwarf2_emit_insn (2 * __is);
+
+	  if (op1.mode == OP_EXP)
+	    {
+	      where += 2;
+	      bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+
+	      if (op1.reg || (op1.reg == 0 && op1.am == 3))
+		fix_new_exp (frag_now, where, 2,
+			     &(op1.exp), FALSE, CHECK_RELOC_MSP430);
+	      else
+		fix_new_exp (frag_now, where, 2,
+			     &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	    }
+	  break;
+	}
+      break;
+
+    case 1:			/* Format 1, double operand.  */
+      line = extract_operand (line, l1, sizeof (l1));
+      line = extract_operand (line, l2, sizeof (l2));
+      res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
+      res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
+
+      if (res)
+	break;			/* Error occurred.  All warnings were done before.  */
+
+      bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
+
+      __is = 1 + op1.ol + op2.ol;	/* insn size in words.  */
+      frag = frag_more (2 * __is);
+      where = frag - frag_now->fr_literal;
+      bfd_putl16 ((bfd_vma) bin, frag);
+      dwarf2_emit_insn (2 * __is);
+
+      if (op1.mode == OP_EXP)
+	{
+	  where += 2;		/* Advance where as we do not know _where_.  */
+	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+
+	  if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
+	    fix_new_exp (frag_now, where, 2,
+			 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
+	  else
+	    fix_new_exp (frag_now, where, 2,
+			 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	}
+
+      if (op2.mode == OP_EXP)
+	{
+	  imm_op = 0;
+	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0));
+
+	  if (op2.reg)		/* Not PC relative.  */
+	    fix_new_exp (frag_now, where + 2, 2,
+			 &(op2.exp), FALSE, CHECK_RELOC_MSP430);
+	  else
+	    fix_new_exp (frag_now, where + 2, 2,
+			 &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	}
+      break;
+
+    case 2:			/* Single-operand mostly instr.  */
+      if (opcode->insn_opnumb == 0)
+	{
+	  /* reti instruction.  */
+	  frag = frag_more (2);
+	  bfd_putl16 ((bfd_vma) bin, frag);
+	  dwarf2_emit_insn (2);
+	  break;
+	}
+
+      line = extract_operand (line, l1, sizeof (l1));
+      res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);
+      if (res)
+	break;		/* Error in operand.  */
+
+      bin |= op1.reg | (op1.am << 4);
+      __is = 1 + op1.ol;
+      frag = frag_more (2 * __is);
+      where = frag - frag_now->fr_literal;
+      bfd_putl16 ((bfd_vma) bin, frag);
+      dwarf2_emit_insn (2 * __is);
+
+      if (op1.mode == OP_EXP)
+	{
+	  bfd_putl16 ((bfd_vma) ZEROS, frag + 2);
+
+	  if (op1.reg || (op1.reg == 0 && op1.am == 3))	/* Not PC relative.  */
+	    fix_new_exp (frag_now, where + 2, 2,
+			 &(op1.exp), FALSE, CHECK_RELOC_MSP430);
+	  else
+	    fix_new_exp (frag_now, where + 2, 2,
+			 &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL);
+	}
+      break;
+
+    case 3:			/* Conditional jumps instructions.  */
+      line = extract_operand (line, l1, sizeof (l1));
+      /* l1 is a label.  */
+      if (l1[0])
+	{
+	  char *m = l1;
+	  expressionS exp;
+
+	  if (*m == '$')
+	    m++;
+
+	  parse_exp (m, &exp);
+	  frag = frag_more (2);	/* Instr size is 1 word.  */
+
+	  /* In order to handle something like:
+
+	     and #0x8000, r5
+	     tst r5
+	     jz   4     ;       skip next 4 bytes
+	     inv r5
+	     inc r5
+	     nop        ;       will jump here if r5 positive or zero
+
+	     jCOND      -n      ;assumes jump n bytes backward:
+
+	     mov r5,r6
+	     jmp -2
+
+	     is equal to:
+	     lab:
+	     mov r5,r6
+	     jmp lab
+
+	     jCOND      $n      ; jump from PC in either direction.  */
+
+	  if (exp.X_op == O_constant)
+	    {
+	      int x = exp.X_add_number;
+
+	      if (x & 1)
+		{
+		  as_warn (_("Even number required. Rounded to %d"), x + 1);
+		  x++;
+		}
+
+	      if ((*l1 == '$' && x > 0) || x < 0)
+		x -= 2;
+
+	      x >>= 1;
+
+	      if (x > 512 || x < -511)
+		{
+		  as_bad (_("Wrong displacement  %d"), x << 1);
+		  break;
+		}
+
+	      bin |= x & 0x3ff;
+	      bfd_putl16 ((bfd_vma) bin, frag);
+	    }
+	  else if (exp.X_op == O_symbol && *l1 != '$')
+	    {
+	      where = frag - frag_now->fr_literal;
+	      fix_new_exp (frag_now, where, 2,
+			   &exp, TRUE, BFD_RELOC_MSP430_10_PCREL);
+
+	      bfd_putl16 ((bfd_vma) bin, frag);
+	    }
+	  else if (*l1 == '$')
+	    {
+	      as_bad (_("instruction requires label sans '$'"));
+	    }
+	  else
+	    {
+	      as_bad (_
+		      ("instruction requires label or value in range -511:512"));
+	    }
+	  dwarf2_emit_insn (2 * __is);
+	  break;
+	}
+      else
+	{
+	  as_bad (_("instruction requires label"));
+	  break;
+	}
+      break;
+
+    case 4:	/* Extended jumps.  */
+      if (!msp430_enable_polys)
+	{
+	  as_bad(_("polymorphs are not enabled. Use -mP option to enable."));
+	  break;
+	}
+	
+      line = extract_operand (line, l1, sizeof (l1));
+      if (l1[0])
+	{
+	  char *m = l1;
+	  expressionS exp;
+
+	  /* Ignore absolute addressing. make it PC relative anyway.  */
+	  if (*m == '#' || *m == '$')
+	    m++;
+
+	  parse_exp (m, & exp);
+	  if (exp.X_op == O_symbol)
+	    {
+	      /* Relaxation required.  */
+	      struct rcodes_s rc = msp430_rcodes[opcode->insn_opnumb];
+
+	      /* The parameter to dwarf2_emit_insn is actually the offset to the start
+		 of the insn from the fix piece of instruction that was emitted.
+		 Since next fragments may have variable size we tie debug info
+	         to the beginning of the instruction. */
+	      frag = frag_more (8);
+	      dwarf2_emit_insn (0);
+	      bfd_putl16 ((bfd_vma) rc.sop, frag);
+	      frag = frag_variant (rs_machine_dependent, 8, 2,
+				   ENCODE_RELAX (rc.lpos, STATE_BITS10), /* Wild guess.  */
+				   exp.X_add_symbol,
+				   0,	/* Offset is zero if jump dist less than 1K.  */
+				   (char *) frag);
+	      break;
+	    }
+	}
+
+      as_bad (_("instruction requires label"));
+      break;
+
+    case 5:	/* Emulated extended branches.  */
+      if (!msp430_enable_polys)
+	{
+	  as_bad(_("polymorphs are not enabled. Use -mP option to enable."));
+	  break;
+	}
+      line = extract_operand (line, l1, sizeof (l1));
+      if (l1[0])
+	{
+	  char * m = l1;
+	  expressionS exp;
+
+	  /* Ignore absolute addressing. make it PC relative anyway.  */
+	  if (*m == '#' || *m == '$')
+	    m++;
+
+	  parse_exp (m, & exp);
+	  if (exp.X_op == O_symbol)
+	    {
+	      /* Relaxation required.  */
+	      struct hcodes_s hc = msp430_hcodes[opcode->insn_opnumb];
+
+	      frag = frag_more (8);
+	      dwarf2_emit_insn (0);
+	      bfd_putl16 ((bfd_vma) hc.op0, frag);
+	      bfd_putl16 ((bfd_vma) hc.op1, frag+2);
+
+	      frag = frag_variant (rs_machine_dependent, 8, 2,
+				   ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10), /* Wild guess.  */
+				   exp.X_add_symbol,
+				   0,	/* Offset is zero if jump dist less than 1K.  */
+				   (char *) frag);
+	      break;
+	    }
+	}
+
+      as_bad (_("instruction requires label"));
+      break;
+
+    default:
+      as_bad (_("Ilegal instruction or not implmented opcode."));
+    }
+
+  input_line_pointer = line;
+  return 0;
+}
+
+void
+md_assemble (char * str)
+{
+  struct msp430_opcode_s * opcode;
+  char cmd[32];
+  unsigned int i = 0;
+
+  str = skip_space (str);	/* Skip leading spaces.  */
+  str = extract_cmd (str, cmd, sizeof (cmd));
+
+  while (cmd[i] && i < sizeof (cmd))
+    {
+      char a = TOLOWER (cmd[i]);
+      cmd[i] = a;
+      i++;
+    }
+
+  if (!cmd[0])
+    {
+      as_bad (_("can't find opcode "));
+      return;
+    }
+
+  opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);
+
+  if (opcode == NULL)
+    {
+      as_bad (_("unknown opcode `%s'"), cmd);
+      return;
+    }
+
+  {
+    char *__t = input_line_pointer;
+
+    msp430_operands (opcode, str);
+    input_line_pointer = __t;
+  }
+}
+
 /* GAS will call this function for each section at the end of the assembly,
    to permit the CPU backend to adjust the alignment of a section.  */
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection * seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
 
@@ -1349,9 +1897,7 @@ md_section_align (seg, addr)
    macro would return the length of an instruction.  */
 
 long
-md_pcrel_from_section (fixp, sec)
-     fixS *fixp;
-     segT sec;
+md_pcrel_from_section (fixS * fixp, segT sec)
 {
   if (fixp->fx_addsy != (symbolS *) NULL
       && (!S_IS_DEFINED (fixp->fx_addsy)
@@ -1361,16 +1907,28 @@ md_pcrel_from_section (fixp, sec)
   return fixp->fx_frag->fr_address + fixp->fx_where;
 }
 
+/* Replaces standard TC_FORCE_RELOCATION_LOCAL.
+   Now it handles the situation when relocations
+   have to be passed to linker. */
+int
+msp430_force_relocation_local(fixS *fixp)
+{
+  if (msp430_enable_polys
+        && !msp430_enable_relax)
+    return 1;
+  else
+    return (!fixp->fx_pcrel
+	    || fixp->fx_plt
+	    || generic_force_reloc(fixp));
+}
+
+
 /* GAS will call this for each fixup.  It should store the correct
    value in the object file.  */
-
 void
-md_apply_fix3 (fixp, valuep, seg)
-     fixS *fixp;
-     valueT *valuep;
-     segT seg;
+md_apply_fix (fixS * fixp, valueT * valuep, segT seg)
 {
-  unsigned char *where;
+  unsigned char * where;
   unsigned long insn;
   long value;
 
@@ -1385,7 +1943,19 @@ md_apply_fix3 (fixp, valuep, seg)
 
       if (fixp->fx_addsy && (s == seg || s == absolute_section))
 	{
-	  value = S_GET_VALUE (fixp->fx_addsy) + *valuep;
+	  /* FIXME: We can appear here only in case if we perform a pc
+	     relative jump to the label which is i) global, ii) locally
+	     defined or this is a jump to an absolute symbol.
+	     If this is an absolute symbol -- everything is OK.
+	     If this is a global label, we've got a symbol value defined
+	     twice:
+               1. S_GET_VALUE (fixp->fx_addsy) will contain a symbol offset
+	          from this section start
+               2. *valuep will contain the real offset from jump insn to the
+	          label
+	     So, the result of S_GET_VALUE (fixp->fx_addsy) + (* valuep);
+	     will be incorrect. Therefore remove s_get_value.  */
+	  value = /* S_GET_VALUE (fixp->fx_addsy) + */ * valuep;
 	  fixp->fx_done = 1;
 	}
       else
@@ -1411,13 +1981,18 @@ md_apply_fix3 (fixp, valuep, seg)
 	}
     }
 
-  switch (fixp->fx_r_type)
+  fixp->fx_no_overflow = 1;
+
+  /* if polymorphs are enabled and relax disabled. 
+     do not kill any relocs and pass them to linker. */
+  if (msp430_enable_polys 
+      && !msp430_enable_relax)
     {
-    default:
-      fixp->fx_no_overflow = 1;
-      break;
-    case BFD_RELOC_MSP430_10_PCREL:
-      break;
+      if (!fixp->fx_addsy || (fixp->fx_addsy 
+	  && S_GET_SEGMENT (fixp->fx_addsy) == absolute_section))
+	fixp->fx_done = 1;	/* it is ok to kill 'abs' reloc */
+      else
+      	fixp->fx_done = 0;
     }
 
   if (fixp->fx_done)
@@ -1425,7 +2000,7 @@ md_apply_fix3 (fixp, valuep, seg)
       /* Fetch the instruction, insert the fully resolved operand
 	 value, and stuff the instruction back again.  */
 
-      where = fixp->fx_frag->fr_literal + fixp->fx_where;
+      where = (unsigned char *) fixp->fx_frag->fr_literal + fixp->fx_where;
 
       insn = bfd_getl16 (where);
 
@@ -1448,6 +2023,7 @@ md_apply_fix3 (fixp, valuep, seg)
 	  bfd_putl16 ((bfd_vma) (value | insn), where);
 	  break;
 
+	case BFD_RELOC_MSP430_RL_PCREL:
 	case BFD_RELOC_MSP430_16_PCREL:
 	  if (value & 1)
 	    as_bad_where (fixp->fx_file, fixp->fx_line,
@@ -1495,26 +2071,23 @@ md_apply_fix3 (fixp, valuep, seg)
     }
 }
 
-/* A `BFD_ASSEMBLER' GAS will call this to generate a reloc.  GAS
-   will pass the resulting reloc to `bfd_install_relocation'.  This
-   currently works poorly, as `bfd_install_relocation' often does the
-   wrong thing, and instances of `tc_gen_reloc' have been written to
-   work around the problems, which in turns makes it difficult to fix
-   `bfd_install_relocation'.  */
+/* GAS will call this to generate a reloc, passing the resulting reloc
+   to `bfd_install_relocation'.  This currently works poorly, as
+   `bfd_install_relocation' often does the wrong thing, and instances of
+   `tc_gen_reloc' have been written to work around the problems, which
+   in turns makes it difficult to fix `bfd_install_relocation'.  */
 
 /* If while processing a fixup, a reloc really needs to be created
    then it is done here.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
 {
-  arelent *reloc;
+  arelent * reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
 
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
@@ -1536,26 +2109,230 @@ tc_gen_reloc (seg, fixp)
   return reloc;
 }
 
-/* Parse ordinary expression.  */
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+			       asection * segment_type ATTRIBUTE_UNUSED)
+{
+  if (fragP->fr_symbol && S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
+    {
+      /* This is a jump -> pcrel mode. Nothing to do much here.
+         Return value == 2.  */
+      fragP->fr_subtype =
+	  ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_BITS10);
+    }
+  else if (fragP->fr_symbol)
+    {
+      /* Its got a segment, but its not ours.   Even if fr_symbol is in
+	 an absolute segment, we dont know a displacement until we link
+	 object files. So it will always be long. This also applies to
+	 labels in a subsegment of current. Liker may relax it to short
+	 jump later. Return value == 8.  */
+      fragP->fr_subtype =
+	  ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_WORD);
+    }
+  else
+    {
+      /* We know the abs value. may be it is a jump to fixed address.
+         Impossible in our case, cause all constants already handeled. */
+      fragP->fr_subtype =
+	  ENCODE_RELAX (RELAX_LEN (fragP->fr_subtype), STATE_UNDEF);
+    }
 
-static char *
-parse_exp (s, op)
-     char *s;
-     expressionS *op;
+  return md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+void
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+		 asection * sec ATTRIBUTE_UNUSED,
+		 fragS * fragP)
 {
-  input_line_pointer = s;
-  expression (op);
-  if (op->X_op == O_absent)
-    as_bad (_("missing operand"));
-  return input_line_pointer;
+  char * where = 0;
+  int rela = -1;
+  int i;
+  struct rcodes_s * cc = NULL;
+  struct hcodes_s * hc = NULL;
+
+  switch (fragP->fr_subtype)
+    {
+    case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_BITS10):
+    case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_BITS10):
+    case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_BITS10):
+      /* We do not have to convert anything here.
+         Just apply a fix.  */
+      rela = BFD_RELOC_MSP430_10_PCREL;
+      break;
+
+    case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_UNCOND_BRANCH, STATE_UNDEF):
+      /* Convert uncond branch jmp lab -> br lab.  */
+      cc = & msp430_rcodes[7];
+      where = fragP->fr_literal + fragP->fr_fix;
+      bfd_putl16 (cc->lop0, where);
+      rela = BFD_RELOC_MSP430_RL_PCREL;
+      fragP->fr_fix += 2;
+      break;
+
+    case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_SIMPLE_BRANCH, STATE_UNDEF):
+      {
+	/* Other simple branches.  */
+	int insn = bfd_getl16 (fragP->fr_opcode);
+
+	insn &= 0xffff;
+	/* Find actual instruction.  */
+	for (i = 0; i < 7 && !cc; i++)
+	  if (msp430_rcodes[i].sop == insn)
+	    cc = & msp430_rcodes[i];
+	if (!cc || !cc->name)
+	  as_fatal (_("internal inconsistency problem in %s: insn %04lx"),
+		    __FUNCTION__, (long) insn);
+	where = fragP->fr_literal + fragP->fr_fix;
+	bfd_putl16 (cc->lop0, where);
+	bfd_putl16 (cc->lop1, where + 2);
+	rela = BFD_RELOC_MSP430_RL_PCREL;
+	fragP->fr_fix += 4;
+      }
+      break;
+
+    case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_NOOV_BRANCH, STATE_UNDEF):
+      cc = & msp430_rcodes[6];
+      where = fragP->fr_literal + fragP->fr_fix;
+      bfd_putl16 (cc->lop0, where);
+      bfd_putl16 (cc->lop1, where + 2);
+      bfd_putl16 (cc->lop2, where + 4);
+      rela = BFD_RELOC_MSP430_RL_PCREL;
+      fragP->fr_fix += 6;
+      break;
+
+    case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_BITS10):
+      {
+	int insn = bfd_getl16 (fragP->fr_opcode + 2);
+
+	insn &= 0xffff;
+	for (i = 0; i < 4 && !hc; i++)
+	  if (msp430_hcodes[i].op1 == insn)
+	    hc = &msp430_hcodes[i];
+	if (!hc || !hc->name)
+	  as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
+	      __FUNCTION__, (long) insn);
+	rela = BFD_RELOC_MSP430_10_PCREL;
+	/* Apply a fix for a first label if necessary.
+	   another fix will be applied to the next word of insn anyway.  */
+	if (hc->tlab == 2)
+	  fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+	      fragP->fr_offset, TRUE, rela);
+	fragP->fr_fix += 2;
+      }
+
+      break;
+
+    case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_WORD):
+    case ENCODE_RELAX (STATE_EMUL_BRANCH, STATE_UNDEF):
+      {
+	int insn = bfd_getl16 (fragP->fr_opcode + 2);
+
+	insn &= 0xffff;
+	for (i = 0; i < 4 && !hc; i++)
+	  if (msp430_hcodes[i].op1 == insn)
+	    hc = & msp430_hcodes[i];
+	if (!hc || !hc->name)
+	  as_fatal (_("internal inconsistency problem in %s: ext. insn %04lx"),
+	      __FUNCTION__, (long) insn);
+	rela = BFD_RELOC_MSP430_RL_PCREL;
+	where = fragP->fr_literal + fragP->fr_fix;
+	bfd_putl16 (hc->lop0, where);
+	bfd_putl16 (hc->lop1, where + 2);
+	bfd_putl16 (hc->lop2, where + 4);
+	fragP->fr_fix += 6;
+      }
+      break;
+
+    default:
+      as_fatal (_("internal inconsistency problem in %s:  %lx"),
+		__FUNCTION__, (long) fragP->fr_subtype);
+      break;
+    }
+
+  /* Now apply fix.  */
+  fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
+	   fragP->fr_offset, TRUE, rela);
+  /* Just fixed 2 bytes.  */
+  fragP->fr_fix += 2;
 }
 
+/* Relax fragment. Mostly stolen from hc11 and mcore
+   which arches I think I know.  */
 
-int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp ATTRIBUTE_UNUSED;
-     asection *seg ATTRIBUTE_UNUSED;
+long
+msp430_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS * fragP,
+		   long stretch ATTRIBUTE_UNUSED)
 {
-  abort ();
-  return 0;
+  long growth;
+  offsetT aim = 0;
+  symbolS *symbolP;
+  const relax_typeS *this_type;
+  const relax_typeS *start_type;
+  relax_substateT next_state;
+  relax_substateT this_state;
+  const relax_typeS *table = md_relax_table;
+
+  /* Nothing to be done if the frag has already max size.  */
+  if (RELAX_STATE (fragP->fr_subtype) == STATE_UNDEF
+      || RELAX_STATE (fragP->fr_subtype) == STATE_WORD)
+    return 0;
+
+  if (RELAX_STATE (fragP->fr_subtype) == STATE_BITS10)
+    {
+      symbolP = fragP->fr_symbol;
+      if (symbol_resolved_p (symbolP))
+	as_fatal (_("internal inconsistency problem in %s: resolved symbol"),
+		  __FUNCTION__);
+      /* We know the offset. calculate a distance.  */
+      aim = S_GET_VALUE (symbolP) - fragP->fr_address - fragP->fr_fix;
+    }
+
+  if (!msp430_enable_relax)
+    {
+      /* Relaxation is not enabled. So, make all jump as long ones
+         by setting 'aim' to quite high value. */
+      aim = 0x7fff;
+    }
+  
+  this_state = fragP->fr_subtype;
+  start_type = this_type = table + this_state;
+
+  if (aim < 0)
+    {
+      /* Look backwards.  */
+      for (next_state = this_type->rlx_more; next_state;)
+	if (aim >= this_type->rlx_backward || !this_type->rlx_backward)
+	  next_state = 0;
+	else
+	  {
+	    /* Grow to next state.  */
+	    this_state = next_state;
+	    this_type = table + this_state;
+	    next_state = this_type->rlx_more;
+	  }
+    }
+  else
+    {
+      /* Look forwards.  */
+      for (next_state = this_type->rlx_more; next_state;)
+	if (aim <= this_type->rlx_forward || !this_type->rlx_forward)
+	  next_state = 0;
+	else
+	  {
+	    /* Grow to next state.  */
+	    this_state = next_state;
+	    this_type = table + this_state;
+	    next_state = this_type->rlx_more;
+	  }
+    }
+
+  growth = this_type->rlx_length - start_type->rlx_length;
+  if (growth != 0)
+    fragP->fr_subtype = this_state;
+  return growth;
 }
diff --git a/gas/config/tc-msp430.h b/gas/config/tc-msp430.h
index e540124bc82c..9fef126e5515 100644
--- a/gas/config/tc-msp430.h
+++ b/gas/config/tc-msp430.h
@@ -1,5 +1,5 @@
 /* This file is tc-msp430.h
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2004, 2005 Free Software Foundation, Inc.
 
    Contributed by Dmitry Diky <diwil@mail.ru>
 
@@ -17,12 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#ifndef BFD_ASSEMBLER
- #error MSP430 support requires BFD_ASSEMBLER
-#endif
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_MSP430
 /*   By convention, you should define this macro in the `.h' file.  For
@@ -93,7 +89,7 @@
      of a PC relative instruction is the next instruction, so this
      macro would return the length of an instruction.  */
 
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define LISTING_WORD_SIZE 2
 /*   The number of bytes to put into a word in a listing.  This affects
@@ -112,3 +108,15 @@ extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
      should do nothing.  Some targets define a `.bss' directive that is
      also affected by this macro.  The default definition will set
      P2VAR to the truncated power of two of sizes up to eight bytes.  */
+
+#define md_relax_frag(SEG, FRAGP, STRETCH)             \
+   msp430_relax_frag (SEG, FRAGP, STRETCH)
+extern long msp430_relax_frag (segT, fragS *, long);
+
+#define TC_FORCE_RELOCATION_LOCAL(FIX)	\
+   msp430_force_relocation_local(FIX)
+extern int msp430_force_relocation_local(struct fix *);
+
+
+extern int msp430_enable_relax;
+extern int msp430_enable_polys;
diff --git a/gas/config/tc-mt.c b/gas/config/tc-mt.c
new file mode 100644
index 000000000000..f9a610e049c1
--- /dev/null
+++ b/gas/config/tc-mt.c
@@ -0,0 +1,538 @@
+/* tc-mt.c -- Assembler for the Morpho Technologies mt .
+   Copyright (C) 2005 Free Software Foundation.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include <stdio.h>
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"     
+#include "symcat.h"
+#include "opcodes/mt-desc.h"
+#include "opcodes/mt-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/mt.h"
+#include "libbfd.h"
+
+/* Structure to hold all of the different components
+   describing an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int                   num_fixups;
+  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
+  int                   indices [MAX_OPERAND_INSTANCES];
+}
+mt_insn;
+
+
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
+const char line_separator_chars[] = ""; 
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+    { "word",   cons,                   4 }, 
+    { NULL, 	NULL,			0 }
+};
+
+
+
+static int no_scheduling_restrictions = 0;
+
+struct option md_longopts[] = 
+{
+#define OPTION_NO_SCHED_REST	(OPTION_MD_BASE)
+  { "nosched",	   no_argument, NULL, OPTION_NO_SCHED_REST },
+#define OPTION_MARCH		(OPTION_MD_BASE + 1)
+  { "march", required_argument, NULL, OPTION_MARCH},
+  { NULL,	   no_argument, NULL, 0 },
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+
+/* Mach selected from command line.  */
+static int mt_mach = bfd_mach_ms1;
+static unsigned mt_mach_bitmask = 1 << MACH_MS1;
+
+/* Flags to set in the elf header */
+static flagword mt_flags = EF_MT_CPU_MRISC;
+
+/* The architecture to use.  */
+enum mt_architectures
+  {
+    ms1_64_001,
+    ms1_16_002,
+    ms1_16_003,
+    ms2
+  };
+
+/* MT architecture we are using for this output file.  */
+static enum mt_architectures mt_arch = ms1_16_002;
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
+{
+  switch (c)
+    {
+    case OPTION_MARCH:
+      if (strcmp (arg, "ms1-64-001") == 0)
+ 	{
+ 	  mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
+ 	  mt_mach = bfd_mach_ms1;
+ 	  mt_mach_bitmask = 1 << MACH_MS1;
+ 	  mt_arch = ms1_64_001;
+ 	}
+      else if (strcmp (arg, "ms1-16-002") == 0)
+ 	{
+ 	  mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
+ 	  mt_mach = bfd_mach_ms1;
+ 	  mt_mach_bitmask = 1 << MACH_MS1;
+ 	  mt_arch = ms1_16_002;
+ 	}
+      else if (strcmp (arg, "ms1-16-003") == 0)
+ 	{
+ 	  mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC2;
+ 	  mt_mach = bfd_mach_mrisc2;
+ 	  mt_mach_bitmask = 1 << MACH_MS1_003;
+ 	  mt_arch = ms1_16_003;
+ 	}
+      else if (strcmp (arg, "ms2") == 0)
+ 	{
+ 	  mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MS2;
+ 	  mt_mach = bfd_mach_mrisc2;
+ 	  mt_mach_bitmask = 1 << MACH_MS2;
+ 	  mt_arch = ms2;
+ 	}
+    case OPTION_NO_SCHED_REST:
+      no_scheduling_restrictions = 1;
+      break;
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+
+void
+md_show_usage (FILE * stream)
+{
+  fprintf (stream, _("MT specific command line options:\n"));
+  fprintf (stream, _("  -march=ms1-64-001         allow ms1-64-001 instructions\n"));
+  fprintf (stream, _("  -march=ms1-16-002         allow ms1-16-002 instructions (default)\n"));
+  fprintf (stream, _("  -march=ms1-16-003         allow ms1-16-003 instructions\n"));
+  fprintf (stream, _("  -march=ms2                allow ms2 instructions \n"));
+  fprintf (stream, _("  -nosched                  disable scheduling restrictions\n"));
+}
+
+
+void
+md_begin (void)
+{
+  /* Initialize the `cgen' interface.  */
+  
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask,
+					CGEN_CPU_OPEN_ENDIAN,
+					CGEN_ENDIAN_BIG,
+					CGEN_CPU_OPEN_END);
+  mt_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+  /* Set the ELF flags if desired. */
+  if (mt_flags)
+    bfd_set_private_flags (stdoutput, mt_flags);
+
+  /* Set the machine type.  */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
+}
+
+void
+md_assemble (char * str)
+{
+  static long delayed_load_register = 0;
+  static long prev_delayed_load_register = 0;
+  static int last_insn_had_delay_slot = 0;
+  static int last_insn_in_noncond_delay_slot = 0;
+  static int last_insn_has_load_delay = 0;
+  static int last_insn_was_memory_access = 0;
+  static int last_insn_was_io_insn = 0;
+  static int last_insn_was_arithmetic_or_logic = 0;
+  static int last_insn_was_branch_insn = 0;
+  static int last_insn_was_conditional_branch_insn = 0;
+
+  mt_insn insn;
+  char * errmsg;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  insn.insn = mt_cgen_assemble_insn
+      (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+  if (!insn.insn)
+    {
+      as_bad ("%s", errmsg);
+      return;
+    }
+
+  /* Doesn't really matter what we pass for RELAX_P here.  */
+  gas_cgen_finish_insn (insn.insn, insn.buffer,
+			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+
+
+  /* Handle Scheduling Restrictions.  */
+  if (!no_scheduling_restrictions)
+    {
+      /* Detect consecutive Memory Accesses.  */
+      if (last_insn_was_memory_access
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS)
+	  && mt_mach == ms1_64_001)
+	as_warn (_("instruction %s may not follow another memory access instruction."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect consecutive I/O Instructions.  */
+      else if (last_insn_was_io_insn
+	       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN))
+	as_warn (_("instruction %s may not follow another I/O instruction."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect consecutive branch instructions.  */
+      else if (last_insn_was_branch_insn
+	       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN))
+	as_warn (_("%s may not occupy the delay slot of another branch insn."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect data dependencies on delayed loads: memory and input insns.  */
+      if (last_insn_has_load_delay && delayed_load_register)
+	{
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	      && insn.fields.f_sr1 == delayed_load_register)
+	    as_warn (_("operand references R%ld of previous load."),
+		     insn.fields.f_sr1);
+
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+	      && insn.fields.f_sr2 == delayed_load_register)
+	    as_warn (_("operand references R%ld of previous load."),
+		     insn.fields.f_sr2);
+	}
+
+      /* Detect JAL/RETI hazard */
+      if (mt_mach == ms2
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
+	{
+	  if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	       && insn.fields.f_sr1 == delayed_load_register)
+	      || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		  && insn.fields.f_sr2 == delayed_load_register))
+	    as_warn (_("operand references R%ld of previous instrutcion."),
+		     delayed_load_register);
+	  else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+		    && insn.fields.f_sr1 == prev_delayed_load_register)
+		   || (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+		       && insn.fields.f_sr2 == prev_delayed_load_register))
+	    as_warn (_("operand references R%ld of instructcion before previous."),
+		     prev_delayed_load_register);
+	}
+      
+      /* Detect data dependency between conditional branch instruction
+         and an immediately preceding arithmetic or logical instruction.  */
+      if (last_insn_was_arithmetic_or_logic
+	  && !last_insn_in_noncond_delay_slot
+	  && (delayed_load_register != 0)
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
+	  && mt_arch == ms1_64_001)
+	{
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	      && insn.fields.f_sr1 == delayed_load_register)
+	    as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
+		     insn.fields.f_sr1);
+
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+	      && insn.fields.f_sr2 == delayed_load_register)
+	    as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
+		     insn.fields.f_sr2);
+	}
+    }
+
+  /* Keep track of details of this insn for processing next insn.  */
+  last_insn_in_noncond_delay_slot = last_insn_was_branch_insn
+    && !last_insn_was_conditional_branch_insn;
+
+  last_insn_had_delay_slot =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
+
+  last_insn_has_load_delay =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY);
+
+  last_insn_was_memory_access =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS);
+
+  last_insn_was_io_insn =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN);
+
+  last_insn_was_arithmetic_or_logic =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_AL_INSN);
+
+  last_insn_was_branch_insn =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN);
+  
+  last_insn_was_conditional_branch_insn =
+  CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
+    && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
+  
+  prev_delayed_load_register = delayed_load_register;
+  
+  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
+     delayed_load_register = insn.fields.f_dr; 
+  else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
+     delayed_load_register = insn.fields.f_drrr; 
+  else  /* Insns has no destination register.  */
+     delayed_load_register = 0; 
+
+  /* Generate dwarf2 line numbers.  */
+  dwarf2_emit_insn (4); 
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+    return NULL;
+}
+
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+			       segT    segment ATTRIBUTE_UNUSED)
+{
+  as_fatal (_("md_estimate_size_before_relax\n"));
+  return 1;
+} 
+
+/* *fragP has been relaxed to its final size, and now needs to have
+   the bytes inside it modified to conform to the new size.
+
+   Called after relaxation is finished.
+   fragP->fr_type == rs_machine_dependent.
+   fragP->fr_subtype is the subtype of what the address relaxed to.  */
+
+void
+md_convert_frag (bfd   * abfd  ATTRIBUTE_UNUSED,
+		 segT    sec   ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
+{
+}
+
+
+/* Functions concerning relocs.  */
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (!S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
+
+  /* Return the address of the opcode - cgen adjusts for opcode size
+     itself, to be consistent with the disassembler, which must do
+     so.  */
+  return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP     ATTRIBUTE_UNUSED)
+{
+  bfd_reloc_code_real_type result;
+
+  result = BFD_RELOC_NONE;
+
+  switch (operand->type)
+    {
+    case MT_OPERAND_IMM16O:
+      result = BFD_RELOC_16_PCREL;
+      fixP->fx_pcrel = 1;
+      /* fixP->fx_no_overflow = 1; */
+      break;
+    case MT_OPERAND_IMM16:
+    case MT_OPERAND_IMM16Z:
+      /* These may have been processed at parse time.  */
+      if (fixP->fx_cgen.opinfo != 0)
+        result = fixP->fx_cgen.opinfo;
+      fixP->fx_no_overflow = 1;
+      break;
+    case MT_OPERAND_LOOPSIZE:
+      result = BFD_RELOC_MT_PCINSN8;
+      fixP->fx_pcrel = 1;
+      /* Adjust for the delay slot, which is not part of the loop  */
+      fixP->fx_offset -= 8;
+      break;
+    default:
+      result = BFD_RELOC_NONE;
+      break;
+    }
+
+  return result;
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+  number_to_chars_bigendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (type, litP, sizeP)
+     char   type;
+     char * litP;
+     int *  sizeP;
+{
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  LITTLENUM_TYPE * wordP;
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+   /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+
+    default:
+      * sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  /* This loops outputs the LITTLENUMs in REVERSE order;
+     in accord with the mt endianness.  */
+  for (wordP = words; prec--;)
+    {
+      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+     
+  return 0;
+}
+
+/* See whether we need to force a relocation into the output file.  */
+
+int
+mt_force_relocation (fixS * fixp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+void
+mt_apply_fix (fixS *fixP, valueT *valueP, segT seg)
+{
+  if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32))
+    fixP->fx_r_type = BFD_RELOC_32_PCREL;
+
+  gas_cgen_md_apply_fix (fixP, valueP, seg);
+}
+
+bfd_boolean
+mt_fix_adjustable (fixS * fixP)
+{
+  bfd_reloc_code_real_type reloc_type;
+
+  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+    {
+      const CGEN_INSN *insn = NULL;
+      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+      const CGEN_OPERAND *operand;
+
+      operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+    }
+  else
+    reloc_type = fixP->fx_r_type;
+
+  if (fixP->fx_addsy == NULL)
+    return TRUE;
+  
+  /* Prevent all adjustments to global symbols.  */
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
+    return FALSE;
+  
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return FALSE;
+  
+  return 1;
+}
diff --git a/gas/config/tc-mt.h b/gas/config/tc-mt.h
new file mode 100644
index 000000000000..3f64988a678e
--- /dev/null
+++ b/gas/config/tc-mt.h
@@ -0,0 +1,70 @@
+/* tc-mt.h -- Header file for tc-mt.c.
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA. */
+
+#define TC_MT
+
+#define LISTING_HEADER "MT GAS "
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH bfd_arch_mt
+
+#define TARGET_FORMAT "elf32-mt"
+
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+/* Permit temporary numeric labels.  */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely.  */
+#define WORKING_DOT_WORD
+
+/* All mt instructions are multiples of 32 bits.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 4
+
+#define LITERAL_PREFIXDOLLAR_HEX
+#define LITERAL_PREFIXPERCENT_BIN
+
+#define md_apply_fix mt_apply_fix
+extern void mt_apply_fix (struct fix *, valueT *, segT); 
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
+extern bfd_boolean mt_fix_adjustable (struct fix *);
+
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+#define md_operand(x) gas_cgen_md_operand (x)
+extern void gas_cgen_md_operand (expressionS *);
+
+#define TC_FORCE_RELOCATION(fixp) mt_force_relocation (fixp)
+extern int mt_force_relocation (struct fix *);
+
+#define tc_fix_adjustable(fixP) mt_fix_adjustable (fixP)
+extern bfd_boolean mt_fix_adjustable (struct fix *);
+
diff --git a/gas/config/tc-ns32k.c b/gas/config/tc-ns32k.c
index 4284e55c2a53..1a8c3cb3eea8 100644
--- a/gas/config/tc-ns32k.c
+++ b/gas/config/tc-ns32k.c
@@ -1,6 +1,6 @@
 /* ns32k.c  -- Assemble on the National Semiconductor 32k series
    Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002
+   2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*#define SHOW_NUM 1*//* Uncomment for debugging.  */
 
@@ -38,17 +38,17 @@
                                    encountered.  */
 
 #define IIF(ptr,a1,c1,e1,g1,i1,k1,m1,o1,q1,s1,u1)	\
-    iif.iifP[ptr].type= a1;				\
-    iif.iifP[ptr].size= c1;				\
-    iif.iifP[ptr].object= e1;				\
-    iif.iifP[ptr].object_adjust= g1;			\
-    iif.iifP[ptr].pcrel= i1;				\
-    iif.iifP[ptr].pcrel_adjust= k1;			\
-    iif.iifP[ptr].im_disp= m1;				\
-    iif.iifP[ptr].relax_substate= o1;			\
-    iif.iifP[ptr].bit_fixP= q1;				\
-    iif.iifP[ptr].addr_mode= s1;			\
-    iif.iifP[ptr].bsr= u1;
+    iif.iifP[ptr].type = a1;				\
+    iif.iifP[ptr].size = c1;				\
+    iif.iifP[ptr].object = e1;				\
+    iif.iifP[ptr].object_adjust = g1;			\
+    iif.iifP[ptr].pcrel = i1;				\
+    iif.iifP[ptr].pcrel_adjust = k1;			\
+    iif.iifP[ptr].im_disp = m1;				\
+    iif.iifP[ptr].relax_substate = o1;			\
+    iif.iifP[ptr].bit_fixP = q1;			\
+    iif.iifP[ptr].addr_mode = s1;			\
+    iif.iifP[ptr].bsr = u1;
 
 #ifdef SEQUENT_COMPATABILITY
 #define LINE_COMMENT_CHARS "|"
@@ -70,21 +70,21 @@ static int default_disp_size = 4; /* Displacement size for external refs.  */
 #endif
 
 struct addr_mode
-  {
-    signed char mode;		/* Addressing mode of operand (0-31).  */
-    signed char scaled_mode;	/* Mode combined with scaled mode.  */
-    char scaled_reg;		/* Register used in scaled+1 (1-8).  */
-    char float_flag;		/* Set if R0..R7 was F0..F7 ie a
+{
+  signed char mode;		/* Addressing mode of operand (0-31).  */
+  signed char scaled_mode;	/* Mode combined with scaled mode.  */
+  char scaled_reg;		/* Register used in scaled+1 (1-8).  */
+  char float_flag;		/* Set if R0..R7 was F0..F7 ie a
 				   floating-point-register.  */
-    char am_size;		/* Estimated max size of general addr-mode
+  char am_size;			/* Estimated max size of general addr-mode
 				   parts.  */
-    char im_disp;		/* If im_disp==1 we have a displacement.  */
-    char pcrel;			/* 1 if pcrel, this is really redundant info.  */
-    char disp_suffix[2];	/* Length of displacement(s), 0=undefined.  */
-    char *disp[2];		/* Pointer(s) at displacement(s)
+  char im_disp;			/* If im_disp==1 we have a displacement.  */
+  char pcrel;			/* 1 if pcrel, this is really redundant info.  */
+  char disp_suffix[2];		/* Length of displacement(s), 0=undefined.  */
+  char *disp[2];		/* Pointer(s) at displacement(s)
 				   or immediates(s)     (ascii).  */
-    char index_byte;		/* Index byte.  */
-  };
+  char index_byte;		/* Index byte.  */
+};
 typedef struct addr_mode addr_modeS;
 
 char *freeptr, *freeptr_static;	/* Points at some number of free bytes.  */
@@ -112,27 +112,27 @@ struct ns32k_option
 };
 
 typedef struct
-  {
-    int type;			/* How to interpret object.  */
-    int size;			/* Estimated max size of object.  */
-    unsigned long object;	/* Binary data.  */
-    int object_adjust;		/* Number added to object.  */
-    int pcrel;			/* True if object is pcrel.  */
-    int pcrel_adjust;		/* Length in bytes from the instruction
+{
+  int type;			/* How to interpret object.  */
+  int size;			/* Estimated max size of object.  */
+  unsigned long object;		/* Binary data.  */
+  int object_adjust;		/* Number added to object.  */
+  int pcrel;			/* True if object is pcrel.  */
+  int pcrel_adjust;		/* Length in bytes from the instruction
 				   start to the	displacement.  */
-    int im_disp;		/* True if the object is a displacement.  */
-    relax_substateT relax_substate;	/* Initial relaxsubstate.  */
-    bit_fixS *bit_fixP;		/* Pointer at bit_fix struct.  */
-    int addr_mode;		/* What addrmode do we associate with this
+  int im_disp;			/* True if the object is a displacement.  */
+  relax_substateT relax_substate;/*Initial relaxsubstate.  */
+  bit_fixS *bit_fixP;		/* Pointer at bit_fix struct.  */
+  int addr_mode;		/* What addrmode do we associate with this
 				   iif-entry.  */
-    char bsr;			/* Sequent hack.  */
-  } iif_entryT;			/* Internal Instruction Format.  */
+  char bsr;			/* Sequent hack.  */
+} iif_entryT;			/* Internal Instruction Format.  */
 
 struct int_ins_form
-  {
-    int instr_size;		/* Max size of instruction in bytes.  */
-    iif_entryT iifP[IIF_ENTRIES + 1];
-  };
+{
+  int instr_size;		/* Max size of instruction in bytes.  */
+  iif_entryT iifP[IIF_ENTRIES + 1];
+};
 
 struct int_ins_form iif;
 expressionS exprP;
@@ -367,11 +367,6 @@ char disp_test[] =
 char disp_size[] =
 {4, 1, 2, 0, 4};
 
-static void evaluate_expr PARAMS ((expressionS * resultP, char *));
-static void md_number_to_disp PARAMS ((char *, long, int));
-static void md_number_to_imm PARAMS ((char *, long, int));
-static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
-
 /* Parse a general operand into an addressingmode struct
 
    In:  pointer at operand in ascii form
@@ -380,13 +375,10 @@ static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
 
    Out: data in addr_mode struct.  */
 
-static int addr_mode PARAMS ((char *, addr_modeS *, int));
-
 static int
-addr_mode (operand, addr_modeP, recursive_level)
-     char *operand;
-     addr_modeS *addr_modeP;
-     int recursive_level;
+addr_mode (char *operand,
+	   addr_modeS *addr_modeP,
+	   int recursive_level)
 {
   char *str;
   int i;
@@ -657,17 +649,25 @@ addr_mode (operand, addr_modeP, recursive_level)
   return -1;
 }
 
+static void
+evaluate_expr (expressionS *resultP, char *ptr)
+{
+  char *tmp_line;
+
+  tmp_line = input_line_pointer;
+  input_line_pointer = ptr;
+  expression (resultP);
+  input_line_pointer = tmp_line;
+}
+
 /* ptr points at string addr_modeP points at struct with result This
    routine calls addr_mode to determine the general addr.mode of the
    operand. When this is ready it parses the displacements for size
    specifying suffixes and determines size of immediate mode via
    ns32k-opcode.  Also builds index bytes if needed.  */
 
-static int get_addr_mode PARAMS ((char *, addr_modeS *));
 static int
-get_addr_mode (ptr, addr_modeP)
-     char *ptr;
-     addr_modeS *addr_modeP;
+get_addr_mode (char *ptr, addr_modeS *addr_modeP)
 {
   int tmp;
 
@@ -801,12 +801,10 @@ get_addr_mode (ptr, addr_modeP)
 
 /* Read an optionlist.  */
 
-static void optlist PARAMS ((char *, struct ns32k_option *, unsigned long *));
 static void
-optlist (str, optionP, default_map)
-     char *str;			/* The string to extract options from.  */
-     struct ns32k_option *optionP;	/* How to search the string.  */
-     unsigned long *default_map;	/* Default pattern and output.  */
+optlist (char *str,			/* The string to extract options from.  */
+	 struct ns32k_option *optionP,	/* How to search the string.  */
+	 unsigned long *default_map)	/* Default pattern and output.  */
 {
   int i, j, k, strlen1, strlen2;
   char *patternP, *strP;
@@ -845,13 +843,10 @@ optlist (str, optionP, default_map)
    the instructions lmr, smr, lpr, spr return true if str is found in
    list.  */
 
-static int list_search PARAMS ((char *, struct ns32k_option *, unsigned long *));
-
 static int
-list_search (str, optionP, default_map)
-     char *str;				/* The string to match.  */
-     struct ns32k_option *optionP;	/* List to search.  */
-     unsigned long *default_map;	/* Default pattern and output.  */
+list_search (char *str,				/* The string to match.  */
+	     struct ns32k_option *optionP,	/* List to search.  */
+	     unsigned long *default_map)	/* Default pattern and output.  */
 {
   int i;
 
@@ -870,37 +865,49 @@ list_search (str, optionP, default_map)
   as_bad (_("No such entry in list. (cpu/mmu register)"));
   return 0;
 }
+
+/* Create a bit_fixS in obstack 'notes'.
+   This struct is used to profile the normal fix. If the bit_fixP is a
+   valid pointer (not NULL) the bit_fix data will be used to format
+   the fix.  */
 
-static void
-evaluate_expr (resultP, ptr)
-     expressionS *resultP;
-     char *ptr;
+static bit_fixS *
+bit_fix_new (int size,		/* Length of bitfield.  */
+	     int offset,	/* Bit offset to bitfield.  */
+	     long min,		/* Signextended min for bitfield.  */
+	     long max,		/* Signextended max for bitfield.  */
+	     long add,		/* Add mask, used for huffman prefix.  */
+	     long base_type,	/* 0 or 1, if 1 it's exploded to opcode ptr.  */
+	     long base_adj)
 {
-  char *tmp_line;
+  bit_fixS *bit_fixP;
 
-  tmp_line = input_line_pointer;
-  input_line_pointer = ptr;
-  expression (resultP);
-  input_line_pointer = tmp_line;
+  bit_fixP = (bit_fixS *) obstack_alloc (&notes, sizeof (bit_fixS));
+
+  bit_fixP->fx_bit_size = size;
+  bit_fixP->fx_bit_offset = offset;
+  bit_fixP->fx_bit_base = base_type;
+  bit_fixP->fx_bit_base_adj = base_adj;
+  bit_fixP->fx_bit_max = max;
+  bit_fixP->fx_bit_min = min;
+  bit_fixP->fx_bit_add = add;
+
+  return bit_fixP;
 }
-
+
 /* Convert operands to iif-format and adds bitfields to the opcode.
    Operands are parsed in such an order that the opcode is updated from
    its most significant bit, that is when the operand need to alter the
    opcode.
    Be careful not to put to objects in the same iif-slot.  */
 
-static void encode_operand
-  PARAMS ((int, char **, const char *, const char *, char, char));
-
 static void
-encode_operand (argc, argv, operandsP, suffixP, im_size, opcode_bit_ptr)
-     int argc;
-     char **argv;
-     const char *operandsP;
-     const char *suffixP;
-     char im_size ATTRIBUTE_UNUSED;
-     char opcode_bit_ptr;
+encode_operand (int argc,
+		char **argv,
+		const char *operandsP,
+		const char *suffixP,
+		char im_size ATTRIBUTE_UNUSED,
+		char opcode_bit_ptr)
 {
   int i, j;
   char d;
@@ -1079,12 +1086,8 @@ encode_operand (argc, argv, operandsP, suffixP, im_size, opcode_bit_ptr)
    Return-value = recursive_level.  */
 /* Build iif of one assembly text line.  */
 
-static int parse PARAMS ((const char *, int));
-
 static int
-parse (line, recursive_level)
-     const char *line;
-     int recursive_level;
+parse (const char *line, int recursive_level)
 {
   const char *lineptr;
   char c, suffix_separator;
@@ -1109,9 +1112,7 @@ parse (line, recursive_level)
       *(char *) lineptr = c;
     }
   else
-    {
-      lineptr = line;
-    }
+    lineptr = line;
 
   argc = 0;
 
@@ -1208,9 +1209,7 @@ parse (line, recursive_level)
 		  lineptr += 1;
 		}
 	      else
-		{
-		  as_fatal (_("Too many operands passed to instruction"));
-		}
+		as_fatal (_("Too many operands passed to instruction"));
 	    }
 	}
     }
@@ -1225,9 +1224,7 @@ parse (line, recursive_level)
 	    as_fatal (_("Wrong numbers of operands in default, check ns32k-opcodes.h"));
 	}
       else
-	{
-	  as_fatal (_("Wrong number of operands"));
-	}
+	as_fatal (_("Wrong number of operands"));
     }
 
   for (i = 0; i < IIF_ENTRIES; i++)
@@ -1240,17 +1237,359 @@ parse (line, recursive_level)
 
   /* This call encodes operands to iif format.  */
   if (argc)
-    {
-      encode_operand (argc,
-		      argv,
-		      &desc->operands[0],
-		      &suffix[0],
-		      desc->im_size,
-		      desc->opcode_size);
-    }
+    encode_operand (argc, argv, &desc->operands[0],
+		    &suffix[0], desc->im_size, desc->opcode_size);
+
   return recursive_level;
 }
 
+/* This functionality should really be in the bfd library.  */
+
+static bfd_reloc_code_real_type
+reloc (int size, int pcrel, int type)
+{
+  int length, index;
+  bfd_reloc_code_real_type relocs[] =
+  {
+    BFD_RELOC_NS32K_IMM_8,
+    BFD_RELOC_NS32K_IMM_16,
+    BFD_RELOC_NS32K_IMM_32,
+    BFD_RELOC_NS32K_IMM_8_PCREL,
+    BFD_RELOC_NS32K_IMM_16_PCREL,
+    BFD_RELOC_NS32K_IMM_32_PCREL,
+
+    /* ns32k displacements.  */
+    BFD_RELOC_NS32K_DISP_8,
+    BFD_RELOC_NS32K_DISP_16,
+    BFD_RELOC_NS32K_DISP_32,
+    BFD_RELOC_NS32K_DISP_8_PCREL,
+    BFD_RELOC_NS32K_DISP_16_PCREL,
+    BFD_RELOC_NS32K_DISP_32_PCREL,
+
+    /* Normal 2's complement.  */
+    BFD_RELOC_8,
+    BFD_RELOC_16,
+    BFD_RELOC_32,
+    BFD_RELOC_8_PCREL,
+    BFD_RELOC_16_PCREL,
+    BFD_RELOC_32_PCREL
+  };
+
+  switch (size)
+    {
+    case 1:
+      length = 0;
+      break;
+    case 2:
+      length = 1;
+      break;
+    case 4:
+      length = 2;
+      break;
+    default:
+      length = -1;
+      break;
+    }
+
+  index = length + 3 * pcrel + 6 * type;
+
+  if (index >= 0 && (unsigned int) index < sizeof (relocs) / sizeof (relocs[0]))
+    return relocs[index];
+
+  if (pcrel)
+    as_bad (_("Can not do %d byte pc-relative relocation for storage type %d"),
+	    size, type);
+  else
+    as_bad (_("Can not do %d byte relocation for storage type %d"),
+	    size, type);
+
+  return BFD_RELOC_NONE;
+
+}
+
+static void
+fix_new_ns32k (fragS *frag,		/* Which frag? */
+	       int where,		/* Where in that frag? */
+	       int size,		/* 1, 2  or 4 usually.  */
+	       symbolS *add_symbol,	/* X_add_symbol.  */
+	       long offset,		/* X_add_number.  */
+	       int pcrel,		/* True if PC-relative relocation.  */
+	       char im_disp,		/* True if the value to write is a
+					   displacement.  */
+	       bit_fixS *bit_fixP,	/* Pointer at struct of bit_fix's, ignored if
+					   NULL.  */
+	       char bsr,		/* Sequent-linker-hack: 1 when relocobject is
+					   a bsr.  */
+	       fragS *opcode_frag,
+	       unsigned int opcode_offset)
+{
+  fixS *fixP = fix_new (frag, where, size, add_symbol,
+			offset, pcrel,
+			bit_fixP ? NO_RELOC : reloc (size, pcrel, im_disp)
+			);
+
+  fix_opcode_frag (fixP) = opcode_frag;
+  fix_opcode_offset (fixP) = opcode_offset;
+  fix_im_disp (fixP) = im_disp;
+  fix_bsr (fixP) = bsr;
+  fix_bit_fixP (fixP) = bit_fixP;
+  /* We have a MD overflow check for displacements.  */
+  fixP->fx_no_overflow = (im_disp != 0);
+}
+
+static void
+fix_new_ns32k_exp (fragS *frag,		/* Which frag? */
+		   int where,		/* Where in that frag? */
+		   int size,		/* 1, 2  or 4 usually.  */
+		   expressionS *exp,	/* Expression.  */
+		   int pcrel,		/* True if PC-relative relocation.  */
+		   char im_disp,	/* True if the value to write is a
+					   displacement.  */
+		   bit_fixS *bit_fixP,	/* Pointer at struct of bit_fix's, ignored if
+					   NULL.  */
+		   char bsr,		/* Sequent-linker-hack: 1 when relocobject is
+					   a bsr.  */
+		   fragS *opcode_frag,
+		   unsigned int opcode_offset)
+{
+  fixS *fixP = fix_new_exp (frag, where, size, exp, pcrel,
+			    bit_fixP ? NO_RELOC : reloc (size, pcrel, im_disp)
+			    );
+
+  fix_opcode_frag (fixP) = opcode_frag;
+  fix_opcode_offset (fixP) = opcode_offset;
+  fix_im_disp (fixP) = im_disp;
+  fix_bsr (fixP) = bsr;
+  fix_bit_fixP (fixP) = bit_fixP;
+  /* We have a MD overflow check for displacements.  */
+  fixP->fx_no_overflow = (im_disp != 0);
+}
+
+/* Convert number to chars in correct order.  */
+
+void
+md_number_to_chars (char *buf, valueT value, int nbytes)
+{
+  number_to_chars_littleendian (buf, value, nbytes);
+}
+
+/* This is a variant of md_numbers_to_chars. The reason for its'
+   existence is the fact that ns32k uses Huffman coded
+   displacements. This implies that the bit order is reversed in
+   displacements and that they are prefixed with a size-tag.
+
+   binary: msb -> lsb
+   0xxxxxxx				byte
+   10xxxxxx xxxxxxxx			word
+   11xxxxxx xxxxxxxx xxxxxxxx xxxxxxxx	double word
+
+   This must be taken care of and we do it here!  */
+
+static void
+md_number_to_disp (char *buf, long val, int n)
+{
+  switch (n)
+    {
+    case 1:
+      if (val < -64 || val > 63)
+	as_bad (_("value of %ld out of byte displacement range."), val);
+      val &= 0x7f;
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    case 2:
+      if (val < -8192 || val > 8191)
+	as_bad (_("value of %ld out of word displacement range."), val);
+      val &= 0x3fff;
+      val |= 0x8000;
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 8 & 0xff);
+#endif
+      *buf++ = (val >> 8);
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    case 4:
+      if (val < -0x20000000 || val >= 0x20000000)
+	as_bad (_("value of %ld out of double word displacement range."), val);
+      val |= 0xc0000000;
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 24 & 0xff);
+#endif
+      *buf++ = (val >> 24);
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 16 & 0xff);
+#endif
+      *buf++ = (val >> 16);
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 8 & 0xff);
+#endif
+      *buf++ = (val >> 8);
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    default:
+      as_fatal (_("Internal logic error.  line %d, file \"%s\""),
+		__LINE__, __FILE__);
+    }
+}
+
+static void
+md_number_to_imm (char *buf, long val, int n)
+{
+  switch (n)
+    {
+    case 1:
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    case 2:
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 8 & 0xff);
+#endif
+      *buf++ = (val >> 8);
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    case 4:
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 24 & 0xff);
+#endif
+      *buf++ = (val >> 24);
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 16 & 0xff);
+#endif
+      *buf++ = (val >> 16);
+#ifdef SHOW_NUM
+      printf ("%x ", val >> 8 & 0xff);
+#endif
+      *buf++ = (val >> 8);
+#ifdef SHOW_NUM
+      printf ("%x ", val & 0xff);
+#endif
+      *buf++ = val;
+      break;
+
+    default:
+      as_fatal (_("Internal logic error. line %d, file \"%s\""),
+		__LINE__, __FILE__);
+    }
+}
+
+/* Fast bitfiddling support.  */
+/* Mask used to zero bitfield before oring in the true field.  */
+
+static unsigned long l_mask[] =
+{
+  0xffffffff, 0xfffffffe, 0xfffffffc, 0xfffffff8,
+  0xfffffff0, 0xffffffe0, 0xffffffc0, 0xffffff80,
+  0xffffff00, 0xfffffe00, 0xfffffc00, 0xfffff800,
+  0xfffff000, 0xffffe000, 0xffffc000, 0xffff8000,
+  0xffff0000, 0xfffe0000, 0xfffc0000, 0xfff80000,
+  0xfff00000, 0xffe00000, 0xffc00000, 0xff800000,
+  0xff000000, 0xfe000000, 0xfc000000, 0xf8000000,
+  0xf0000000, 0xe0000000, 0xc0000000, 0x80000000,
+};
+static unsigned long r_mask[] =
+{
+  0x00000000, 0x00000001, 0x00000003, 0x00000007,
+  0x0000000f, 0x0000001f, 0x0000003f, 0x0000007f,
+  0x000000ff, 0x000001ff, 0x000003ff, 0x000007ff,
+  0x00000fff, 0x00001fff, 0x00003fff, 0x00007fff,
+  0x0000ffff, 0x0001ffff, 0x0003ffff, 0x0007ffff,
+  0x000fffff, 0x001fffff, 0x003fffff, 0x007fffff,
+  0x00ffffff, 0x01ffffff, 0x03ffffff, 0x07ffffff,
+  0x0fffffff, 0x1fffffff, 0x3fffffff, 0x7fffffff,
+};
+#define MASK_BITS 31
+/* Insert bitfield described by field_ptr and val at buf
+   This routine is written for modification of the first 4 bytes pointed
+   to by buf, to yield speed.
+   The ifdef stuff is for selection between a ns32k-dependent routine
+   and a general version. (My advice: use the general version!).  */
+
+static void
+md_number_to_field (char *buf, long val, bit_fixS *field_ptr)
+{
+  unsigned long object;
+  unsigned long mask;
+  /* Define ENDIAN on a ns32k machine.  */
+#ifdef ENDIAN
+  unsigned long *mem_ptr;
+#else
+  char *mem_ptr;
+#endif
+
+  if (field_ptr->fx_bit_min <= val && val <= field_ptr->fx_bit_max)
+    {
+#ifdef ENDIAN
+      if (field_ptr->fx_bit_base)
+	/* Override buf.  */
+	mem_ptr = (unsigned long *) field_ptr->fx_bit_base;
+      else
+	mem_ptr = (unsigned long *) buf;
+
+      mem_ptr = ((unsigned long *)
+		 ((char *) mem_ptr + field_ptr->fx_bit_base_adj));
+#else
+      if (field_ptr->fx_bit_base)
+	mem_ptr = (char *) field_ptr->fx_bit_base;
+      else
+	mem_ptr = buf;
+
+      mem_ptr += field_ptr->fx_bit_base_adj;
+#endif
+#ifdef ENDIAN
+      /* We have a nice ns32k machine with lowbyte at low-physical mem.  */
+      object = *mem_ptr;	/* get some bytes */
+#else /* OVE Goof! the machine is a m68k or dito.  */
+      /* That takes more byte fiddling.  */
+      object = 0;
+      object |= mem_ptr[3] & 0xff;
+      object <<= 8;
+      object |= mem_ptr[2] & 0xff;
+      object <<= 8;
+      object |= mem_ptr[1] & 0xff;
+      object <<= 8;
+      object |= mem_ptr[0] & 0xff;
+#endif
+      mask = 0;
+      mask |= (r_mask[field_ptr->fx_bit_offset]);
+      mask |= (l_mask[field_ptr->fx_bit_offset + field_ptr->fx_bit_size]);
+      object &= mask;
+      val += field_ptr->fx_bit_add;
+      object |= ((val << field_ptr->fx_bit_offset) & (mask ^ 0xffffffff));
+#ifdef ENDIAN
+      *mem_ptr = object;
+#else
+      mem_ptr[0] = (char) object;
+      object >>= 8;
+      mem_ptr[1] = (char) object;
+      object >>= 8;
+      mem_ptr[2] = (char) object;
+      object >>= 8;
+      mem_ptr[3] = (char) object;
+#endif
+    }
+  else
+    as_bad (_("Bit field out of range"));
+}
+
 /* Convert iif to fragments.  From this point we start to dribble with
    functions in other files than this one.(Except hash.c) So, if it's
    possible to make an iif for an other CPU, you don't need to know
@@ -1275,9 +1614,8 @@ parse (line, recursive_level)
    objects not part of an instruction, the pointer to the opcode frag
    is always zero.  */
 
-static void convert_iif PARAMS ((void));
 static void
-convert_iif ()
+convert_iif (void)
 {
   int i;
   bit_fixS *j;
@@ -1324,22 +1662,19 @@ convert_iif ()
 		{
 		case 1:	/* The object is pure binary.  */
 		  if (j)
-		    {
-		      md_number_to_field(memP, exprP.X_add_number, j);
-		    }
+		    md_number_to_field (memP, exprP.X_add_number, j);
+
 		  else if (iif.iifP[i].pcrel)
-		    {
-		      fix_new_ns32k (frag_now,
-				     (long) (memP - frag_now->fr_literal),
-				     size,
-				     0,
-				     iif.iifP[i].object,
-				     iif.iifP[i].pcrel,
-				     iif.iifP[i].im_disp,
-				     0,
-				     iif.iifP[i].bsr,	/* Sequent hack.  */
-				     inst_frag, inst_offset);
-		    }
+		    fix_new_ns32k (frag_now,
+				   (long) (memP - frag_now->fr_literal),
+				   size,
+				   0,
+				   iif.iifP[i].object,
+				   iif.iifP[i].pcrel,
+				   iif.iifP[i].im_disp,
+				   0,
+				   iif.iifP[i].bsr,	/* Sequent hack.  */
+				   inst_frag, inst_offset);
 		  else
 		    {
 		      /* Good, just put them bytes out.  */
@@ -1433,9 +1768,7 @@ convert_iif ()
 					 inst_frag, inst_offset);
 		    }
 		  else if (j)
-		    {
-		      md_number_to_field(memP, exprP.X_add_number, j);
-		    }
+		    md_number_to_field (memP, exprP.X_add_number, j);
 		  else
 		    {
 		      /* Good, just put them bytes out.  */
@@ -1488,10 +1821,8 @@ convert_iif ()
 		  {
 		    /* Frag it.  */
 		    if (exprP.X_op_symbol)
-		      {
-			/* We cant relax this case.  */
-			as_fatal (_("Can't relax difference"));
-		      }
+		      /* We cant relax this case.  */
+		      as_fatal (_("Can't relax difference"));
 		    else
 		      {
 			/* Size is not important.  This gets fixed by
@@ -1519,23 +1850,17 @@ convert_iif ()
 		  {
 		    /* This duplicates code in md_number_to_disp.  */
 		    if (-64 <= exprP.X_add_number && exprP.X_add_number <= 63)
-		      {
-			size = 1;
-		      }
+		      size = 1;
 		    else
 		      {
 			if (-8192 <= exprP.X_add_number
 			    && exprP.X_add_number <= 8191)
-			  {
-			    size = 2;
-			  }
+			  size = 2;
 			else
 			  {
 			    if (-0x20000000 <= exprP.X_add_number
 				&& exprP.X_add_number<=0x1fffffff)
-			      {
-				size = 4;
-			      }
+			      size = 4;
 			    else
 			      {
 				as_bad (_("Displacement to large for :d"));
@@ -1557,74 +1882,8 @@ convert_iif ()
     }
 }
 
-#ifdef BFD_ASSEMBLER
-/* This functionality should really be in the bfd library.  */
-static bfd_reloc_code_real_type
-reloc (int size, int pcrel, int type)
-{
-  int length, index;
-  bfd_reloc_code_real_type relocs[] =
-  {
-    BFD_RELOC_NS32K_IMM_8,
-    BFD_RELOC_NS32K_IMM_16,
-    BFD_RELOC_NS32K_IMM_32,
-    BFD_RELOC_NS32K_IMM_8_PCREL,
-    BFD_RELOC_NS32K_IMM_16_PCREL,
-    BFD_RELOC_NS32K_IMM_32_PCREL,
-
-    /* ns32k displacements.  */
-    BFD_RELOC_NS32K_DISP_8,
-    BFD_RELOC_NS32K_DISP_16,
-    BFD_RELOC_NS32K_DISP_32,
-    BFD_RELOC_NS32K_DISP_8_PCREL,
-    BFD_RELOC_NS32K_DISP_16_PCREL,
-    BFD_RELOC_NS32K_DISP_32_PCREL,
-
-    /* Normal 2's complement.  */
-    BFD_RELOC_8,
-    BFD_RELOC_16,
-    BFD_RELOC_32,
-    BFD_RELOC_8_PCREL,
-    BFD_RELOC_16_PCREL,
-    BFD_RELOC_32_PCREL
-  };
-
-  switch (size)
-    {
-    case 1:
-      length = 0;
-      break;
-    case 2:
-      length = 1;
-      break;
-    case 4:
-      length = 2;
-      break;
-    default:
-      length = -1;
-      break;
-    }
-
-  index = length + 3 * pcrel + 6 * type;
-
-  if (index >= 0 && (unsigned int) index < sizeof (relocs) / sizeof (relocs[0]))
-    return relocs[index];
-
-  if (pcrel)
-    as_bad (_("Can not do %d byte pc-relative relocation for storage type %d"),
-	    size, type);
-  else
-    as_bad (_("Can not do %d byte relocation for storage type %d"),
-	    size, type);
-
-  return BFD_RELOC_NONE;
-
-}
-#endif
-
 void
-md_assemble (line)
-     char *line;
+md_assemble (char *line)
 {
   freeptr = freeptr_static;
   parse (line, 0);		/* Explode line to more fix form in iif.  */
@@ -1635,7 +1894,7 @@ md_assemble (line)
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   /* Build a hashtable of the instructions.  */
   const struct ns32k_opcode *ptr;
@@ -1665,10 +1924,7 @@ md_begin ()
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -1704,242 +1960,8 @@ md_atof (type, litP, sizeP)
   return 0;
 }
 
-/* Convert number to chars in correct order.  */
-
-void
-md_number_to_chars (buf, value, nbytes)
-     char *buf;
-     valueT value;
-     int nbytes;
-{
-  number_to_chars_littleendian (buf, value, nbytes);
-}
-
-/* This is a variant of md_numbers_to_chars. The reason for its'
-   existence is the fact that ns32k uses Huffman coded
-   displacements. This implies that the bit order is reversed in
-   displacements and that they are prefixed with a size-tag.
-
-   binary: msb -> lsb
-   0xxxxxxx				byte
-   10xxxxxx xxxxxxxx			word
-   11xxxxxx xxxxxxxx xxxxxxxx xxxxxxxx	double word
-
-   This must be taken care of and we do it here!  */
-
-static void
-md_number_to_disp (buf, val, n)
-     char *buf;
-     long val;
-     char n;
-{
-  switch (n)
-    {
-    case 1:
-      if (val < -64 || val > 63)
-	as_bad (_("value of %ld out of byte displacement range."), val);
-      val &= 0x7f;
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    case 2:
-      if (val < -8192 || val > 8191)
-	as_bad (_("value of %ld out of word displacement range."), val);
-      val &= 0x3fff;
-      val |= 0x8000;
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 8 & 0xff);
-#endif
-      *buf++ = (val >> 8);
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    case 4:
-      if (val < -0x20000000 || val >= 0x20000000)
-	as_bad (_("value of %ld out of double word displacement range."), val);
-      val |= 0xc0000000;
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 24 & 0xff);
-#endif
-      *buf++ = (val >> 24);
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 16 & 0xff);
-#endif
-      *buf++ = (val >> 16);
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 8 & 0xff);
-#endif
-      *buf++ = (val >> 8);
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    default:
-      as_fatal (_("Internal logic error.  line %d, file \"%s\""),
-		__LINE__, __FILE__);
-    }
-}
-
-static void
-md_number_to_imm (buf, val, n)
-     char *buf;
-     long val;
-     char n;
-{
-  switch (n)
-    {
-    case 1:
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    case 2:
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 8 & 0xff);
-#endif
-      *buf++ = (val >> 8);
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    case 4:
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 24 & 0xff);
-#endif
-      *buf++ = (val >> 24);
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 16 & 0xff);
-#endif
-      *buf++ = (val >> 16);
-#ifdef SHOW_NUM
-      printf ("%x ", val >> 8 & 0xff);
-#endif
-      *buf++ = (val >> 8);
-#ifdef SHOW_NUM
-      printf ("%x ", val & 0xff);
-#endif
-      *buf++ = val;
-      break;
-    default:
-      as_fatal (_("Internal logic error. line %d, file \"%s\""),
-		__LINE__, __FILE__);
-    }
-}
-
-/* Fast bitfiddling support.  */
-/* Mask used to zero bitfield before oring in the true field.  */
-
-static unsigned long l_mask[] =
-{
-  0xffffffff, 0xfffffffe, 0xfffffffc, 0xfffffff8,
-  0xfffffff0, 0xffffffe0, 0xffffffc0, 0xffffff80,
-  0xffffff00, 0xfffffe00, 0xfffffc00, 0xfffff800,
-  0xfffff000, 0xffffe000, 0xffffc000, 0xffff8000,
-  0xffff0000, 0xfffe0000, 0xfffc0000, 0xfff80000,
-  0xfff00000, 0xffe00000, 0xffc00000, 0xff800000,
-  0xff000000, 0xfe000000, 0xfc000000, 0xf8000000,
-  0xf0000000, 0xe0000000, 0xc0000000, 0x80000000,
-};
-static unsigned long r_mask[] =
-{
-  0x00000000, 0x00000001, 0x00000003, 0x00000007,
-  0x0000000f, 0x0000001f, 0x0000003f, 0x0000007f,
-  0x000000ff, 0x000001ff, 0x000003ff, 0x000007ff,
-  0x00000fff, 0x00001fff, 0x00003fff, 0x00007fff,
-  0x0000ffff, 0x0001ffff, 0x0003ffff, 0x0007ffff,
-  0x000fffff, 0x001fffff, 0x003fffff, 0x007fffff,
-  0x00ffffff, 0x01ffffff, 0x03ffffff, 0x07ffffff,
-  0x0fffffff, 0x1fffffff, 0x3fffffff, 0x7fffffff,
-};
-#define MASK_BITS 31
-/* Insert bitfield described by field_ptr and val at buf
-   This routine is written for modification of the first 4 bytes pointed
-   to by buf, to yield speed.
-   The ifdef stuff is for selection between a ns32k-dependent routine
-   and a general version. (My advice: use the general version!).  */
-
-static void
-md_number_to_field (buf, val, field_ptr)
-     char *buf;
-     long val;
-     bit_fixS *field_ptr;
-{
-  unsigned long object;
-  unsigned long mask;
-  /* Define ENDIAN on a ns32k machine.  */
-#ifdef ENDIAN
-  unsigned long *mem_ptr;
-#else
-  char *mem_ptr;
-#endif
-
-  if (field_ptr->fx_bit_min <= val && val <= field_ptr->fx_bit_max)
-    {
-#ifdef ENDIAN
-      if (field_ptr->fx_bit_base)
-	/* Override buf.  */
-	mem_ptr = (unsigned long *) field_ptr->fx_bit_base;
-      else
-	mem_ptr = (unsigned long *) buf;
-
-      mem_ptr = ((unsigned long *)
-		 ((char *) mem_ptr + field_ptr->fx_bit_base_adj));
-#else
-      if (field_ptr->fx_bit_base)
-	mem_ptr = (char *) field_ptr->fx_bit_base;
-      else
-	mem_ptr = buf;
-
-      mem_ptr += field_ptr->fx_bit_base_adj;
-#endif
-#ifdef ENDIAN
-      /* We have a nice ns32k machine with lowbyte at low-physical mem.  */
-      object = *mem_ptr;	/* get some bytes */
-#else /* OVE Goof! the machine is a m68k or dito.  */
-      /* That takes more byte fiddling.  */
-      object = 0;
-      object |= mem_ptr[3] & 0xff;
-      object <<= 8;
-      object |= mem_ptr[2] & 0xff;
-      object <<= 8;
-      object |= mem_ptr[1] & 0xff;
-      object <<= 8;
-      object |= mem_ptr[0] & 0xff;
-#endif
-      mask = 0;
-      mask |= (r_mask[field_ptr->fx_bit_offset]);
-      mask |= (l_mask[field_ptr->fx_bit_offset + field_ptr->fx_bit_size]);
-      object &= mask;
-      val += field_ptr->fx_bit_add;
-      object |= ((val << field_ptr->fx_bit_offset) & (mask ^ 0xffffffff));
-#ifdef ENDIAN
-      *mem_ptr = object;
-#else
-      mem_ptr[0] = (char) object;
-      object >>= 8;
-      mem_ptr[1] = (char) object;
-      object >>= 8;
-      mem_ptr[2] = (char) object;
-      object >>= 8;
-      mem_ptr[3] = (char) object;
-#endif
-    }
-  else
-    {
-      as_bad (_("Bit field out of range"));
-    }
-}
-
 int
-md_pcrel_adjust (fragP)
-     fragS *fragP;
+md_pcrel_adjust (fragS *fragP)
 {
   fragS *opcode_frag;
   addressT opcode_address;
@@ -1955,10 +1977,8 @@ md_pcrel_adjust (fragP)
   return fragP->fr_address + fragP->fr_fix - opcode_address;
 }
 
-static int md_fix_pcrel_adjust PARAMS ((fixS *fixP));
 static int
-md_fix_pcrel_adjust (fixP)
-     fixS *fixP;
+md_fix_pcrel_adjust (fixS *fixP)
 {
   fragS *opcode_frag;
   addressT opcode_address;
@@ -1982,19 +2002,14 @@ md_fix_pcrel_adjust (fixP)
    They all get called from here.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT * valP, segT seg ATTRIBUTE_UNUSED)
 {
   long val = * (long *) valP;
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
 
   if (fix_bit_fixP (fixP))
-    {
-      /* Bitfields to fix, sigh.  */
-      md_number_to_field (buf, val, fix_bit_fixP (fixP));
-    }
+    /* Bitfields to fix, sigh.  */
+    md_number_to_field (buf, val, fix_bit_fixP (fixP));
   else switch (fix_im_disp (fixP))
     {
     case 0:
@@ -2022,19 +2037,10 @@ md_apply_fix3 (fixP, valP, seg)
 
 /* Convert a relaxed displacement to ditto in final output.  */
 
-#ifndef BFD_ASSEMBLER
 void
-md_convert_frag (headers, sec, fragP)
-     object_headers *headers;
-     segT sec;
-     fragS *fragP;
-#else
-void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#endif
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
   long disp;
   long ext = 0;
@@ -2076,9 +2082,7 @@ md_convert_frag (abfd, sec, fragP)
    actually know it.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP;
-     segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
 {
   if (fragP->fr_subtype == IND (BRANCH, UNDEF))
     {
@@ -2098,9 +2102,6 @@ md_estimate_size_before_relax (fragP, segment)
 			 frag_opcode_frag (fragP),
 			 frag_opcode_offset (fragP));
 	  fragP->fr_fix += 4;
-#if 0
-	  fragP->fr_opcode[1] = 0xff;
-#endif
 	  frag_wane (fragP);
 	  return 4;
 	}
@@ -2119,14 +2120,13 @@ md_estimate_size_before_relax (fragP, segment)
 
 int md_short_jump_size = 3;
 int md_long_jump_size = 5;
-const int md_reloc_size = 8;	/* Size of relocation record.  */
 
 void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char *ptr,
+		      addressT from_addr,
+		      addressT to_addr,
+		      fragS *frag ATTRIBUTE_UNUSED,
+		      symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
   valueT offset;
 
@@ -2136,11 +2136,11 @@ md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
 }
 
 void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+md_create_long_jump (char *ptr,
+		     addressT from_addr,
+		     addressT to_addr,
+		     fragS *frag ATTRIBUTE_UNUSED,
+		     symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
   valueT offset;
 
@@ -2161,9 +2161,7 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -2207,8 +2205,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 NS32K options:\n\
@@ -2216,114 +2213,13 @@ NS32K options:\n\
 --disp-size-default=<1|2|4>\n"));
 }
 
-/* Create a bit_fixS in obstack 'notes'.
-   This struct is used to profile the normal fix. If the bit_fixP is a
-   valid pointer (not NULL) the bit_fix data will be used to format
-   the fix.  */
-
-bit_fixS *
-bit_fix_new (size, offset, min, max, add, base_type, base_adj)
-     char size;			/* Length of bitfield.  */
-     char offset;		/* Bit offset to bitfield.  */
-     long min;			/* Signextended min for bitfield.  */
-     long max;			/* Signextended max for bitfield.  */
-     long add;			/* Add mask, used for huffman prefix.  */
-     long base_type;		/* 0 or 1, if 1 it's exploded to opcode ptr.  */
-     long base_adj;
-{
-  bit_fixS *bit_fixP;
-
-  bit_fixP = (bit_fixS *) obstack_alloc (&notes, sizeof (bit_fixS));
-
-  bit_fixP->fx_bit_size = size;
-  bit_fixP->fx_bit_offset = offset;
-  bit_fixP->fx_bit_base = base_type;
-  bit_fixP->fx_bit_base_adj = base_adj;
-  bit_fixP->fx_bit_max = max;
-  bit_fixP->fx_bit_min = min;
-  bit_fixP->fx_bit_add = add;
-
-  return bit_fixP;
-}
-
-void
-fix_new_ns32k (frag, where, size, add_symbol, offset, pcrel,
-	       im_disp, bit_fixP, bsr, opcode_frag, opcode_offset)
-     fragS *frag;		/* Which frag? */
-     int where;			/* Where in that frag? */
-     int size;			/* 1, 2  or 4 usually.  */
-     symbolS *add_symbol;	/* X_add_symbol.  */
-     long offset;		/* X_add_number.  */
-     int pcrel;			/* True if PC-relative relocation.  */
-     char im_disp;		/* True if the value to write is a
-				   displacement.  */
-     bit_fixS *bit_fixP;	/* Pointer at struct of bit_fix's, ignored if
-				   NULL.  */
-     char bsr;			/* Sequent-linker-hack: 1 when relocobject is
-				   a bsr.  */
-     fragS *opcode_frag;
-     unsigned int opcode_offset;
-{
-  fixS *fixP = fix_new (frag, where, size, add_symbol,
-			offset, pcrel,
-#ifdef BFD_ASSEMBLER
-			bit_fixP ? NO_RELOC : reloc (size, pcrel, im_disp)
-#else
-			NO_RELOC
-#endif
-			);
-
-  fix_opcode_frag (fixP) = opcode_frag;
-  fix_opcode_offset (fixP) = opcode_offset;
-  fix_im_disp (fixP) = im_disp;
-  fix_bsr (fixP) = bsr;
-  fix_bit_fixP (fixP) = bit_fixP;
-  /* We have a MD overflow check for displacements.  */
-  fixP->fx_no_overflow = (im_disp != 0);
-}
-
-void
-fix_new_ns32k_exp (frag, where, size, exp, pcrel,
-		   im_disp, bit_fixP, bsr, opcode_frag, opcode_offset)
-     fragS *frag;		/* Which frag? */
-     int where;			/* Where in that frag? */
-     int size;			/* 1, 2  or 4 usually.  */
-     expressionS *exp;		/* Expression.  */
-     int pcrel;			/* True if PC-relative relocation.  */
-     char im_disp;		/* True if the value to write is a
-				   displacement.  */
-     bit_fixS *bit_fixP;	/* Pointer at struct of bit_fix's, ignored if
-				   NULL.  */
-     char bsr;			/* Sequent-linker-hack: 1 when relocobject is
-				   a bsr.  */
-     fragS *opcode_frag;
-     unsigned int opcode_offset;
-{
-  fixS *fixP = fix_new_exp (frag, where, size, exp, pcrel,
-#ifdef BFD_ASSEMBLER
-			    bit_fixP ? NO_RELOC : reloc (size, pcrel, im_disp)
-#else
-			    NO_RELOC
-#endif
-			    );
-
-  fix_opcode_frag (fixP) = opcode_frag;
-  fix_opcode_offset (fixP) = opcode_offset;
-  fix_im_disp (fixP) = im_disp;
-  fix_bsr (fixP) = bsr;
-  fix_bit_fixP (fixP) = bit_fixP;
-  /* We have a MD overflow check for displacements.  */
-  fixP->fx_no_overflow = (im_disp != 0);
-}
-
 /* This is TC_CONS_FIX_NEW, called by emit_expr in read.c.  */
 
 void
-cons_fix_new_ns32k (frag, where, size, exp)
-     fragS *frag;		/* Which frag? */
-     int where;			/* Where in that frag? */
-     int size;			/* 1, 2  or 4 usually.  */
-     expressionS *exp;		/* Expression.  */
+cons_fix_new_ns32k (fragS *frag,	/* Which frag? */
+		    int where,		/* Where in that frag? */
+		    int size,		/* 1, 2  or 4 usually.  */
+		    expressionS *exp)	/* Expression.  */
 {
   fix_new_ns32k_exp (frag, where, size, exp,
 		     0, 2, 0, 0, 0, 0);
@@ -2332,8 +2228,7 @@ cons_fix_new_ns32k (frag, where, size, exp)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -2341,9 +2236,7 @@ md_undefined_symbol (name)
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
 {
   return size;			/* Byte alignment is fine.  */
 }
@@ -2352,8 +2245,7 @@ md_section_align (segment, size)
    ns32k, they're relative to the start of the instruction.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   long res;
 
@@ -2365,20 +2257,16 @@ md_pcrel_from (fixP)
       return res;
 }
 
-#ifdef BFD_ASSEMBLER
-
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *rel;
   bfd_reloc_code_real_type code;
 
   code = reloc (fixp->fx_size, fixp->fx_pcrel, fix_im_disp (fixp));
 
-  rel = (arelent *) xmalloc (sizeof (arelent));
-  rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
   if (fixp->fx_pcrel)
@@ -2400,40 +2288,3 @@ tc_gen_reloc (section, fixp)
 
   return rel;
 }
-#else /* BFD_ASSEMBLER */
-
-#ifdef OBJ_AOUT
-void
-cons_fix_new_ns32k (where, fixP, segment_address_in_file)
-     char *where;
-     struct fix *fixP;
-     relax_addressT segment_address_in_file;
-{
-  /* In:  Length of relocation (or of address) in chars: 1, 2 or 4.
-     Out: GNU LD relocation length code: 0, 1, or 2.  */
-
-  static unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
-  long r_symbolnum;
-
-  know (fixP->fx_addsy != NULL);
-
-  md_number_to_chars (where,
-       fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
-		      4);
-
-  r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
-		 ? S_GET_TYPE (fixP->fx_addsy)
-		 : fixP->fx_addsy->sy_number);
-
-  md_number_to_chars (where + 4,
-		      ((long) (r_symbolnum)
-		       | (long) (fixP->fx_pcrel << 24)
-		       | (long) (nbytes_r_length[fixP->fx_size] << 25)
-		       | (long) ((!S_IS_DEFINED (fixP->fx_addsy)) << 27)
-		       | (long) (fix_bsr (fixP) << 28)
-		       | (long) (fix_im_disp (fixP) << 29)),
-		      4);
-}
-
-#endif /* OBJ_AOUT */
-#endif /* BFD_ASSEMBLER */
diff --git a/gas/config/tc-ns32k.h b/gas/config/tc-ns32k.h
index e547bf59a9aa..150496636556 100644
--- a/gas/config/tc-ns32k.h
+++ b/gas/config/tc-ns32k.h
@@ -1,5 +1,5 @@
 /* tc-ns32k.h -- Opcode table for National Semi 32k processor
-   Copyright 1987, 1992, 1993, 1994, 1995, 1997, 2000, 2002
+   Copyright 1987, 1992, 1993, 1994, 1995, 1997, 2000, 2002, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,36 +16,28 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_NS32K
 
 #define TARGET_BYTES_BIG_ENDIAN	0
 
 #define TC_PCREL_ADJUST(F) md_pcrel_adjust(F)
-extern int md_pcrel_adjust PARAMS((fragS *fragP));
+extern int md_pcrel_adjust (fragS *);
 
-#ifdef BFD_ASSEMBLER
 #define NO_RELOC BFD_RELOC_NONE
 
 #define TARGET_ARCH		bfd_arch_ns32k
 
-#ifndef TARGET_FORMAT		/* Maybe defined in te-*.h */
+#ifndef TARGET_FORMAT		/* Maybe defined in te-*.h.  */
 #define TARGET_FORMAT		"a.out-pc532-mach"
 #endif
-#else
-#define NO_RELOC 0
-#endif
 
 #define LOCAL_LABELS_FB 1
 
 #include "bit_fix.h"
 
-#define tc_aout_pre_write_hook(x)	{;}	/* not used */
-#define tc_crawl_symbol_chain(a)	{;}	/* not used */
-#define tc_headers_hook(a)		{;}	/* not used */
-
 #ifdef SEQUENT_COMPATABILITY
 #define DEF_MODEC 20
 #define DEF_MODEL 21
@@ -63,15 +55,7 @@ extern int md_pcrel_adjust PARAMS((fragS *fragP));
 #define ARG_LEN 50
 
 #define TC_CONS_FIX_NEW cons_fix_new_ns32k
-extern void fix_new_ns32k_exp PARAMS ((fragS *, int, int, expressionS *,
-				       int, int, bit_fixS *, int, fragS *,
-				       unsigned int));
-
-extern void fix_new_ns32k PARAMS ((fragS *, int, int, symbolS *, long,
-				   int, int, bit_fixS *, int, fragS *,
-				   unsigned int));
-
-extern void cons_fix_new_ns32k PARAMS ((fragS *, int, int, expressionS *));
+extern void cons_fix_new_ns32k (fragS *, int, int, expressionS *);
 
 /* The NS32x32 has a non 0 nop instruction which should be used in aligns.  */
 #define NOP_OPCODE 0xa2
diff --git a/gas/config/tc-openrisc.c b/gas/config/tc-openrisc.c
index 9b97958248fd..50597a7f9dc9 100644
--- a/gas/config/tc-openrisc.c
+++ b/gas/config/tc-openrisc.c
@@ -1,5 +1,5 @@
 /* tc-openrisc.c -- Assembler for the OpenRISC family.
-   Copyright 2001, 2002, 2003 Free Software Foundation.
+   Copyright 2001, 2002, 2003, 2005 Free Software Foundation.
    Contributed by Johan Rydberg, jrydberg@opencores.org
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -70,24 +70,18 @@ size_t md_longopts_size = sizeof (md_longopts);
 unsigned long openrisc_machine = 0; /* default */
 
 int
-md_parse_option (c, arg)
-     int    c ATTRIBUTE_UNUSED;
-     char * arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_show_usage (stream)
-  FILE * stream ATTRIBUTE_UNUSED;
+md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
 {
 }
 
-static void ignore_pseudo PARAMS ((int));
-
 static void
-ignore_pseudo (val)
-     int val ATTRIBUTE_UNUSED;
+ignore_pseudo (int val ATTRIBUTE_UNUSED)
 {
   discard_rest_of_line ();
 }
@@ -106,7 +100,7 @@ const pseudo_typeS md_pseudo_table[] =
 
 
 void
-md_begin ()
+md_begin (void)
 {
   /* Initialize the `cgen' interface.  */
 
@@ -122,8 +116,7 @@ md_begin ()
 }
 
 void
-md_assemble (str)
-     char * str;
+md_assemble (char * str)
 {
   static int last_insn_had_delay_slot = 0;
   openrisc_insn insn;
@@ -145,14 +138,6 @@ md_assemble (str)
   gas_cgen_finish_insn (insn.insn, insn.buffer,
 			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
 
-#if 0 /* Currently disabled  */
-  /* Warn about invalid insns in delay slots.  */
-  if (last_insn_had_delay_slot
-      && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_NOT_IN_DELAY_SLOT))
-    as_warn (_("Instruction %s not allowed in a delay slot."),
-	     CGEN_INSN_NAME (insn.insn));
-#endif
-
   last_insn_had_delay_slot
     = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
 }
@@ -162,8 +147,7 @@ md_assemble (str)
    We just ignore it.  */
 
 void
-md_operand (expressionP)
-     expressionS * expressionP;
+md_operand (expressionS * expressionP)
 {
   if (* input_line_pointer == '#')
     {
@@ -173,17 +157,14 @@ md_operand (expressionP)
 }
 
 valueT
-md_section_align (segment, size)
-     segT   segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char * name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -219,49 +200,6 @@ const relax_typeS md_relax_table[] =
   {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
 };
 
-long
-openrisc_relax_frag (segment, fragP, stretch)
-     segT    segment;
-     fragS * fragP;
-     long    stretch;
-{
-  /* Address of branch insn.  */
-  long address = fragP->fr_address + fragP->fr_fix - 2;
-  long growth = 0;
-
-  /* Keep 32 bit insns aligned on 32 bit boundaries.  */
-  if (fragP->fr_subtype == 2)
-    {
-      if ((address & 3) != 0)
-	{
-	  fragP->fr_subtype = 3;
-	  growth = 2;
-	}
-    }
-  else if (fragP->fr_subtype == 3)
-    {
-      if ((address & 3) == 0)
-	{
-	  fragP->fr_subtype = 2;
-	  growth = -2;
-	}
-    }
-  else
-    {
-      growth = relax_frag (segment, fragP, stretch);
-
-      /* Long jump on odd halfword boundary?  */
-      if (fragP->fr_subtype == 2 && (address & 3) != 0)
-	{
-	  fragP->fr_subtype = 3;
-	  growth += 2;
-	}
-    }
-
-  return growth;
-}
-
-
 /* Return an initial guess of the length by which a fragment must grow to
    hold a branch to reach its destination.
    Also updates fr_type/fr_subtype as necessary.
@@ -274,9 +212,7 @@ openrisc_relax_frag (segment, fragP, stretch)
    0 value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS * fragP;
-     segT    segment;
+md_estimate_size_before_relax (fragS * fragP, segT segment)
 {
   /* The only thing we have to handle here are symbols outside of the
      current segment.  They may be undefined or in a different segment in
@@ -326,10 +262,9 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-  bfd *   abfd ATTRIBUTE_UNUSED;
-  segT    sec  ATTRIBUTE_UNUSED;
-  fragS * fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *   abfd ATTRIBUTE_UNUSED,
+		 segT    sec  ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
 {
   /* FIXME */
 }
@@ -341,18 +276,14 @@ md_convert_frag (abfd, sec, fragP)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS * fixP;
-     segT   sec;
+md_pcrel_from_section (fixS * fixP, segT sec)
 {
   if (fixP->fx_addsy != (symbolS *) NULL
       && (! S_IS_DEFINED (fixP->fx_addsy)
 	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
-    {
-      /* The symbol is undefined (or is defined but not in this section).
-	 Let the linker figure it out.  */
-      return 0;
-    }
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
 
   return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1;
 }
@@ -363,10 +294,9 @@ md_pcrel_from_section (fixP, sec)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *    insn ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND * operand;
-     fixS *               fixP;
+md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP)
 {
   bfd_reloc_code_real_type type;
 
@@ -402,10 +332,7 @@ md_cgen_lookup_reloc (insn, operand, fixP)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+md_number_to_chars (char * buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
@@ -419,10 +346,7 @@ md_number_to_chars (buf, val, n)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
+md_atof (int type, char * litP, int *  sizeP)
 {
   int              i;
   int              prec;
@@ -468,16 +392,12 @@ md_atof (type, litP, sizeP)
 }
 
 bfd_boolean
-openrisc_fix_adjustable (fixP)
-   fixS * fixP;
+openrisc_fix_adjustable (fixS * fixP)
 {
-  /* We need the symbol name for the VTABLE entries */
+  /* We need the symbol name for the VTABLE entries.  */
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 0;
 
   return 1;
 }
-
-
-
diff --git a/gas/config/tc-openrisc.h b/gas/config/tc-openrisc.h
index b822800efdef..0c14da269f4f 100644
--- a/gas/config/tc-openrisc.h
+++ b/gas/config/tc-openrisc.h
@@ -1,5 +1,5 @@
 /* tc-openrisc.h -- Header file for tc-openrisc.c.
-   Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,16 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_OPENRISC
 
-#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
-#  error OPENRISC support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "OpenRISC GAS "
 
 /* The target BFD architecture.  */
@@ -47,18 +42,18 @@ extern const char openrisc_comment_chars [];
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define md_apply_fix3 gas_cgen_md_apply_fix3
+#define md_apply_fix gas_cgen_md_apply_fix
 
-extern bfd_boolean openrisc_fix_adjustable PARAMS ((struct fix *));
+extern bfd_boolean openrisc_fix_adjustable (struct fix *);
 #define tc_fix_adjustable(FIX) openrisc_fix_adjustable (FIX)
 
 #define tc_gen_reloc gas_cgen_tc_gen_reloc
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
 
 /* For 8 vs 16 vs 32 bit branch selection.  */
diff --git a/gas/config/tc-or32.c b/gas/config/tc-or32.c
index 4fd91f0c7a21..3099e9f58626 100644
--- a/gas/config/tc-or32.c
+++ b/gas/config/tc-or32.c
@@ -1,5 +1,5 @@
 /* Assembly backend for the OpenRISC 1000.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003, 2005 Free Software Foundation, Inc.
    Contributed by Damjan Lampret <lampret@opencores.org>.
    Modified bu Johan Rydberg, <johan.rydberg@netinsight.se>.
    Based upon a29k port.
@@ -18,18 +18,15 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* tc-a29k.c used as a template.  */
 
 #include "safe-ctype.h"
 #include "as.h"
 #include "opcode/or32.h"
-
-#ifdef BFD_ASSEMBLER
 #include "elf/or32.h"
-#endif
 
 #define DEBUG 0
 
@@ -47,45 +44,33 @@
 static struct hash_control *op_hash = NULL;
 
 struct machine_it
-  {
-    char *          error;
-    unsigned long   opcode;
-    struct nlist *  nlistp;
-    expressionS     exp;
-    int             pcrel;
-    int             reloc_offset;   /* Offset of reloc within insn.  */
-    int             reloc;
-  }
+{
+  char *          error;
+  unsigned long   opcode;
+  struct nlist *  nlistp;
+  expressionS     exp;
+  int             pcrel;
+  int             reloc_offset;   /* Offset of reloc within insn.  */
+  int             reloc;
+}
 the_insn;
 
-static void machine_ip PARAMS ((char *));
-
 const pseudo_typeS md_pseudo_table[] =
-  {
-    {"align",   s_align_bytes,  4 },
-    {"space",   s_space,        0 },
-    {"cputype", s_ignore,       0 },
-    {"reg",     s_lsym,         0 },  /* Register equate, same as equ.  */
-    {"sect",    s_ignore,       0 },  /* Creation of coff sections.  */
-    {"proc",    s_ignore,       0 },  /* Start of a function.  */
-    {"endproc", s_ignore,       0 },  /* Function end.  */
-    {"word",    cons,           4 },
-    {NULL,      0,              0 },
-  };
+{
+  {"align",   s_align_bytes,  4 },
+  {"space",   s_space,        0 },
+  {"cputype", s_ignore,       0 },
+  {"reg",     s_lsym,         0 },  /* Register equate, same as equ.  */
+  {"sect",    s_ignore,       0 },  /* Creation of coff sections.  */
+  {"proc",    s_ignore,       0 },  /* Start of a function.  */
+  {"endproc", s_ignore,       0 },  /* Function end.  */
+  {"word",    cons,           4 },
+  {NULL,      0,              0 },
+};
 
 int md_short_jump_size  = 4;
 int md_long_jump_size   = 4;
 
-#if defined(BFD_HEADERS)
-#ifdef RELSZ
-const int md_reloc_size = RELSZ;  /* Coff headers.  */
-#else
-const int md_reloc_size = 12;   /* Something else headers.  */
-#endif
-#else
-const int md_reloc_size = 12;   /* Not bfdized.  */
-#endif
-
 /* This array holds the chars that always start a comment.
    If the pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#";
@@ -114,20 +99,17 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
 /* "l.jalr r9" precalculated opcode.  */
 static unsigned long jalr_r9_opcode;
 
+static void machine_ip (char *);
 
-static int check_invalid_opcode PARAMS ((unsigned long));
-static void encode PARAMS ((const struct machine_opcode *, unsigned long *, signed long, char));
-static char *parse_operand PARAMS ((char *, expressionS *, int));
 
 /* Set bits in machine opcode according to insn->encoding
    description and passed operand.  */
 
 static void
-encode (insn, opcode, param_val, param_ch)
-     const struct machine_opcode *insn;
-     unsigned long *opcode;
-     signed long param_val;
-     char param_ch;
+encode (const struct machine_opcode *insn,
+	unsigned long *opcode,
+	signed long param_val,
+	char param_ch)
 {
   int opc_pos = 0;
   int param_pos = 0;
@@ -195,7 +177,7 @@ encode (insn, opcode, param_val, param_ch)
    need.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   const char *retval = NULL;
   int lose = 0;
@@ -215,7 +197,7 @@ md_begin ()
           continue;
         }
 
-      retval = hash_insert (op_hash, name, (PTR) &machine_opcodes[i]);
+      retval = hash_insert (op_hash, name, (void *) &machine_opcodes[i]);
       if (retval != NULL)
         {
           fprintf (stderr, "internal error: can't hash `%s': %s\n",
@@ -233,8 +215,7 @@ md_begin ()
 /* Returns non zero if instruction is to be used.  */
 
 static int
-check_invalid_opcode (opcode)
-     unsigned long opcode;
+check_invalid_opcode (unsigned long opcode)
 {
   return opcode == jalr_r9_opcode;
 }
@@ -244,8 +225,7 @@ check_invalid_opcode (opcode)
    produce the bytes of data and relocation.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *toP;
 
@@ -261,11 +241,7 @@ md_assemble (str)
   md_number_to_chars (toP, the_insn.opcode, 4);
 
   /* Put out the symbol-dependent stuff.  */
-#ifdef BFD_ASSEMBLER
   if (the_insn.reloc != BFD_RELOC_NONE)
-#else
-  if (the_insn.reloc != NO_RELOC)
-#endif
     {
       fix_new_exp (frag_now,
                    (toP - frag_now->fr_literal + the_insn.reloc_offset),
@@ -281,12 +257,8 @@ static int waiting_for_shift = 0;
 
 static int mask_or_shift = 0;
 
-#ifdef BFD_ASSEMBLER
 static char *
-parse_operand (s, operandp, opt)
-     char *s;
-     expressionS *operandp;
-     int opt;
+parse_operand (char *s, expressionS *operandp, int opt)
 {
   char *save = input_line_pointer;
   char *new;
@@ -348,90 +320,13 @@ parse_operand (s, operandp, opt)
 
   return new;
 }
-#else
-
-static char *
-parse_operand (s, operandp, opt)
-     char *s;
-     expressionS *operandp;
-     int opt;
-{
-  char *save = input_line_pointer;
-  char *new;
-
-#if DEBUG
-  printf ("  PROCESS NEW OPERAND(%s) == %c (%d)\n", s, opt ? opt : '!', opt);
-#endif
-
-  input_line_pointer = s;
-
-  if (strncasecmp (s, "HI(", 3) == 0)
-    {
-      waiting_for_shift = 1;
-      mask_or_shift = RELOC_CONSTH;
-
-      input_line_pointer += 3;
-    }
-  else if (strncasecmp (s, "LO(", 3) == 0)
-    {
-      mask_or_shift = RELOC_CONST;
-
-      input_line_pointer += 3;
-    }
-  else
-    mask_or_shift = 0;
-
-
-  expression (operandp);
-
-  if (operandp->X_op == O_absent)
-    {
-      if (! opt)
-        as_bad (_("missing operand"));
-      else
-        {
-          operandp->X_add_number = 0;
-          operandp->X_op = O_constant;
-        }
-    }
-
-  new = input_line_pointer;
-  input_line_pointer = save;
-
-  if ((operandp->X_op == O_symbol) && (*s != '_'))
-    {
-#if DEBUG
-      printf ("symbol: '%s'\n", save);
-#endif
-
-      for (save = s; s < new; s++)
-        if ((*s == REGISTER_PREFIX) && (*(s + 1) == 'r')) /* Register prefix.  */
-          s++;
-
-        if ((*s == 'r') && ISDIGIT (*(s + 1)))
-          {
-            operandp->X_add_number = strtol (s + 1, NULL, 10);
-            operandp->X_op = O_register;
-          }
-      s = save;
-    }
-
-#if DEBUG
-  printf ("  %s=parse_operand(%s): operandp->X_op = %u\n", new, s, operandp->X_op);
-#endif
-
-  return new;
-}
-#endif
 
 /* Instruction parsing.  Takes a string containing the opcode.
    Operands are at input_line_pointer.  Output is in the_insn.
    Warnings or errors are generated.  */
 
-#ifdef BFD_ASSEMBLER
 static void
-machine_ip (str)
-     char *str;
+machine_ip (char *str)
 {
   char *s;
   const char *args;
@@ -485,10 +380,8 @@ machine_ip (str)
      If an operand matches, we modify the_insn or opcode appropriately,
      and do a "continue".  If an operand fails to match, we "break".  */
   if (insn->args[0] != '\0')
-    {
-      /* Prime the pump.  */
-      s = parse_operand (s, operand, insn->args[0] == 'I');
-    }
+    /* Prime the pump.  */
+    s = parse_operand (s, operand, insn->args[0] == 'I');
 
   for (args = insn->args;; ++args)
     {
@@ -579,13 +472,7 @@ machine_ip (str)
             }
 
           if (*s == '(')
-            {
-              operand->X_op = O_constant;
-#if 0
-              operand->X_add_number = 0; /* ??? if enabled load/store offsets
-					    are zero.  */
-#endif
-            }
+	    operand->X_op = O_constant;
           else if (*s == ')')
             s += 1;
 #if DEBUG
@@ -642,221 +529,6 @@ machine_ip (str)
     }
 }
 
-#else
-
-static void
-machine_ip (str)
-     char *str;
-{
-  char *s;
-  const char *args;
-  const struct machine_opcode *insn;
-  char *argsStart;
-  unsigned long opcode;
-  expressionS the_operand;
-  expressionS *operand = &the_operand;
-  unsigned int regno;
-  int reloc = NO_RELOC;
-
-#if DEBUG
-  printf ("machine_ip(%s)\n", str);
-#endif
-
-  s = str;
-  for (; ISALNUM (*s) || *s == '.'; ++s)
-    if (ISUPPER (*s))
-      *s = TOLOWER (*s);
-
-  switch (*s)
-    {
-    case '\0':
-      break;
-
-    case ' ':     /* FIXME-SOMEDAY more whitespace.  */
-      *s++ = '\0';
-      break;
-
-    default:
-      as_bad (_("unknown opcode1: `%s'"), str);
-      return;
-    }
-
-  if ((insn = (struct machine_opcode *) hash_find (op_hash, str)) == NULL)
-    {
-      as_bad (_("unknown opcode2 `%s'."), str);
-      return;
-    }
-
-  argsStart = s;
-  opcode = 0;
-  memset (&the_insn, '\0', sizeof (the_insn));
-  the_insn.reloc = NO_RELOC;
-
-  reloc = NO_RELOC;
-
-  /* Build the opcode, checking as we go to make sure that the
-     operands match.
-
-     If an operand matches, we modify the_insn or opcode appropriately,
-     and do a "continue".  If an operand fails to match, we "break".  */
-  if (insn->args[0] != '\0')
-    /* Prime the pump.  */
-    s = parse_operand (s, operand,
-		       insn->args[0] == 'I'
-		       || strcmp (insn->name, "l.nop") == 0);
-
-  for (args = insn->args;; ++args)
-    {
-#if DEBUG
-      printf ("  args = %s\n", args);
-#endif
-      switch (*args)
-        {
-        case '\0':    /* End of args.  */
-          /* We have have 0 args, do the bazoooka!  */
-          if (args == insn->args)
-	    encode (insn, &opcode, 0, 0);
-
-          if (*s == '\0')
-            {
-              /* We are truly done.  */
-              the_insn.opcode = opcode;
-              if (check_invalid_opcode (opcode))
-                as_bad (_("instruction not allowed: %s"), str);
-              return;
-            }
-          as_bad (_("too many operands: %s"), s);
-          break;
-
-        case ',':   /* Must match a comma.  */
-          if (*s++ == ',')
-            {
-              reloc = NO_RELOC;
-
-              /* Parse next operand.  */
-              s = parse_operand (s, operand, args[1] == 'I');
-#if DEBUG
-	      printf ("    ',' case: operand->X_add_number = %d, *args = %s, *s = %s\n",
-		      operand->X_add_number, args, s);
-#endif
-              continue;
-            }
-          break;
-
-        case '(':   /* Must match a (.  */
-          s = parse_operand (s, operand, args[1] == 'I');
-          continue;
-
-        case ')':   /* Must match a ).  */
-          continue;
-
-        case 'r':   /* A general register.  */
-          args++;
-
-          if (operand->X_op != O_register)
-            break;    /* Only registers.  */
-
-          know (operand->X_add_symbol == 0);
-          know (operand->X_op_symbol == 0);
-          regno = operand->X_add_number;
-          encode (insn, &opcode, regno, *args);
-#if DEBUG
-          printf ("    r: operand->X_op = %d\n", operand->X_op);
-#endif
-          continue;
-
-        default:
-          /* if (! ISALPHA (*args))
-               break;  */   /* Only immediate values.  */
-
-          if (mask_or_shift)
-	    {
-#if DEBUG
-	      printf ("mask_or_shift = %d\n", mask_or_shift);
-#endif
-	      reloc = mask_or_shift;
-	    }
-          mask_or_shift = 0;
-
-          if (strncasecmp (args, "LO(", 3) == 0)
-            {
-#if DEBUG
-              printf ("reloc_const\n");
-#endif
-              reloc = RELOC_CONST;
-            }
-          else if (strncasecmp (args, "HI(", 3) == 0)
-            {
-#if DEBUG
-              printf ("reloc_consth\n");
-#endif
-              reloc = RELOC_CONSTH;
-            }
-
-          if (*s == '(')
-            {
-              operand->X_op = O_constant;
-#if 0
-              operand->X_add_number = 0; /* ??? if enabled load/store offsets
-					    are zero.  */
-#endif
-            }
-          else if (*s == ')')
-            s += 1;
-#if DEBUG
-          printf ("    default case: operand->X_add_number = %d, *args = %s, *s = %s\n",
-		  operand->X_add_number, args, s);
-#endif
-          if (operand->X_op == O_constant)
-            {
-	      if (reloc == NO_RELOC)
-		{
-		  unsigned long v, mask;
-
-		  mask = 0x3ffffff;
-		  v = abs (operand->X_add_number) & ~ mask;
-		  if (v)
-		    as_bad (_("call/jmp target out of range (1)"));
-		}
-
-              if (reloc == RELOC_CONSTH)
-		operand->X_add_number = ((operand->X_add_number>>16) & 0xffff);
-
-              the_insn.pcrel = 0;
-              encode (insn, &opcode, operand->X_add_number, *args);
-	      /* the_insn.reloc = NO_RELOC; */
-              continue;
-            }
-
-          if (reloc == NO_RELOC)
-            the_insn.reloc = RELOC_JUMPTARG;
-          else
-            the_insn.reloc = reloc;
-#if DEBUG
-          printf ("    reloc sym=%d\n", the_insn.reloc);
-          printf ("    NO_RELOC=%d\n", NO_RELOC);
-#endif
-          the_insn.exp = *operand;
-
-          /*  the_insn.reloc_offset = 1;  */
-          the_insn.pcrel = 1; /* Assume PC-relative jump.  */
-
-          /* FIXME-SOON, Do we figure out whether abs later, after
-             know sym val?  */
-          if (reloc == RELOC_CONST || reloc == RELOC_CONSTH)
-            the_insn.pcrel = 0;
-
-          encode (insn, &opcode, operand->X_add_number, *args);
-          continue;
-        }
-
-      /* Types or values of args don't match.  */
-      as_bad (_("invalid operands"));
-      return;
-    }
-}
-#endif
-
 /* This is identical to the md_atof in m68k.c.  I think this is right,
    but I'm not sure.
 
@@ -869,10 +541,7 @@ machine_ip (str)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
+md_atof (int type, char * litP, int *  sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
@@ -928,20 +597,13 @@ md_atof (type, litP, sizeP)
 /* Write out big-endian.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   number_to_chars_bigendian (buf, val, n);
 }
 
-#ifdef BFD_ASSEMBLER
 void
-md_apply_fix3 (fixP, val, seg)
-     fixS *   fixP;
-     valueT * val;
-     segT     seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS * fixP, valueT * val, segT seg ATTRIBUTE_UNUSED)
 {
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
   long t_val;
@@ -1002,20 +664,7 @@ md_apply_fix3 (fixP, val, seg)
 
     case BFD_RELOC_32_GOT_PCREL:  /* 0000XXXX pattern in a word.  */
       if (!fixP->fx_done)
-        {
-          /* The linker tries to support both AMD and old GNU style
-             R_IREL relocs.  That means that if the addend is exactly
-             the negative of the address within the section, the
-             linker will not handle it correctly.  */
-#if 0
-          if (fixP->fx_pcrel
-              && t_val != 0
-              && t_val == - (fixP->fx_frag->fr_address + fixP->fx_where))
-            as_bad_where
-              (fixP->fx_file, fixP->fx_line,
-               _("the linker will not handle this relocation correctly (1)"));
-#endif
-        }
+        ;
       else if (fixP->fx_pcrel)
         {
           long v = t_val >> 28;
@@ -1048,218 +697,37 @@ md_apply_fix3 (fixP, val, seg)
   if (fixP->fx_addsy == (symbolS *) NULL)
     fixP->fx_done = 1;
 }
-#else
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = *valP;
-  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-
-#if DEBUG
-  printf ("md_apply_fix val:%x\n", val);
-#endif
-
-  fixP->fx_addnumber = val; /* Remember value for emit_reloc.  */
-
-  know (fixP->fx_size == 4);
-  know (fixP->fx_r_type < NO_RELOC);
-
-  /* This is a hack.  There should be a better way to handle this.  */
-  if (fixP->fx_r_type == RELOC_WDISP30 && fixP->fx_addsy)
-    val += fixP->fx_where + fixP->fx_frag->fr_address;
-
-  switch (fixP->fx_r_type)
-    {
-    case RELOC_32:
-      buf[0] = val >> 24;
-      buf[1] = val >> 16;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_8:
-      buf[0] = val;
-      break;
-
-    case RELOC_WDISP30:
-      val = (val >> 2) + 1;
-      buf[0] |= (val >> 24) & 0x3f;
-      buf[1] = (val >> 16);
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_HI22:
-      buf[1] |= (val >> 26) & 0x3f;
-      buf[2] = val >> 18;
-      buf[3] = val >> 10;
-      break;
-
-    case RELOC_LO10:
-      buf[2] |= (val >> 8) & 0x03;
-      buf[3] = val;
-      break;
-
-    case RELOC_BASE13:
-      buf[2] |= (val >> 8) & 0x1f;
-      buf[3] = val;
-      break;
-
-    case RELOC_WDISP22:
-      val = (val >> 2) + 1;
-      /* FALLTHROUGH */
-    case RELOC_BASE22:
-      buf[1] |= (val >> 16) & 0x3f;
-      buf[2] = val >> 8;
-      buf[3] = val;
-      break;
-
-    case RELOC_JUMPTARG:  /* 0000XXXX pattern in a word.  */
-      if (!fixP->fx_done)
-        {
-          /* The linker tries to support both AMD and old GNU style
-             R_IREL relocs.  That means that if the addend is exactly
-             the negative of the address within the section, the
-             linker will not handle it correctly.  */
-#if 0
-          if (fixP->fx_pcrel
-              && val != 0
-              && val == - (fixP->fx_frag->fr_address + fixP->fx_where))
-            as_bad_where
-              (fixP->fx_file, fixP->fx_line,
-               _("the linker will not handle this relocation correctly (1)"));
-#endif
-        }
-      else if (fixP->fx_pcrel)
-        {
-          long v = val >> 28;
-#if 1
-          if (v != 0 && v != -1)
-            as_bad_where (fixP->fx_file, fixP->fx_line,
-                          _("call/jmp target out of range (2)"));
-#endif
-        }
-      else
-        /* This case was supposed to be handled in machine_ip.  */
-        abort ();
-
-      buf[0] |= (val >> 26) & 0x03; /* Holds bits 0FFFFFFC of address.  */
-      buf[1] = val >> 18;
-      buf[2] = val >> 10;
-      buf[3] = val >> 2;
-      break;
-
-    case RELOC_CONST:     /* 0000XXXX pattern in a word.  */
-#if DEBUG
-      printf ("reloc_const: val=%x\n", val);
-#endif
-      buf[2] = val >> 8;  /* Holds bits 0000XXXX.  */
-      buf[3] = val;
-      break;
-
-    case RELOC_CONSTH:    /* 0000XXXX pattern in a word.  */
-#if DEBUG
-      printf ("reloc_consth: val=%x\n", val);
-#endif
-      buf[2] = val >> 24; /* Holds bits XXXX0000.  */
-      buf[3] = val >> 16;
-      break;
-
-    case BFD_RELOC_VTABLE_INHERIT:
-    case BFD_RELOC_VTABLE_ENTRY:
-      fixP->fx_done = 0;
-      break;
-
-    case NO_RELOC:
-    default:
-      as_bad (_("bad relocation type: 0x%02x"), fixP->fx_r_type);
-      break;
-    }
-
-  if (fixP->fx_addsy == (symbolS *) NULL)
-    fixP->fx_done = 1;
-}
-#endif
-
-#ifdef OBJ_COFF
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-#if DEBUG
-  printf ("tc_coff_fix2rtype\n");
-#endif
-
-  switch (fixP->fx_r_type)
-    {
-    case RELOC_32:
-      return (R_WORD);
-    case RELOC_8:
-      return (R_BYTE);
-    case RELOC_CONST:
-      return (R_ILOHALF);
-    case RELOC_CONSTH:
-      return (R_IHIHALF);
-    case RELOC_JUMPTARG:
-      return (R_IREL);
-    default:
-      printf ("need %d\n", fixP->fx_r_type);
-      abort ();
-    }
-
-  return 0;
-}
-
-#endif /* OBJ_COFF */
 
 /* Should never be called for or32.  */
 
 void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *    ptr       ATTRIBUTE_UNUSED;
-     addressT  from_addr ATTRIBUTE_UNUSED;
-     addressT  to_addr   ATTRIBUTE_UNUSED;
-     fragS *   frag      ATTRIBUTE_UNUSED;
-     symbolS * to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char *    ptr       ATTRIBUTE_UNUSED,
+		      addressT  from_addr ATTRIBUTE_UNUSED,
+		      addressT  to_addr   ATTRIBUTE_UNUSED,
+		      fragS *   frag      ATTRIBUTE_UNUSED,
+		      symbolS * to_symbol ATTRIBUTE_UNUSED)
 {
   as_fatal ("or32_create_short_jmp\n");
 }
 
 /* Should never be called for or32.  */
 
-#ifndef BFD_ASSEMBLER
 void
-md_convert_frag (headers, seg, fragP)
-     object_headers * headers ATTRIBUTE_UNUSED;
-     segT             seg     ATTRIBUTE_UNUSED;
-     register fragS * fragP   ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *   headers ATTRIBUTE_UNUSED,
+		 segT    seg     ATTRIBUTE_UNUSED,
+		 fragS * fragP   ATTRIBUTE_UNUSED)
 {
   as_fatal ("or32_convert_frag\n");
 }
 
-#else
-void
-md_convert_frag (headers, seg, fragP)
-     bfd *   headers ATTRIBUTE_UNUSED;
-     segT    seg     ATTRIBUTE_UNUSED;
-     fragS * fragP   ATTRIBUTE_UNUSED;
-{
-  as_fatal ("or32_convert_frag\n");
-}
-#endif
-
 /* Should never be called for or32.  */
 
 void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *    ptr       ATTRIBUTE_UNUSED;
-     addressT  from_addr ATTRIBUTE_UNUSED;
-     addressT  to_addr   ATTRIBUTE_UNUSED;
-     fragS *   frag      ATTRIBUTE_UNUSED;
-     symbolS * to_symbol ATTRIBUTE_UNUSED;
+md_create_long_jump (char *    ptr       ATTRIBUTE_UNUSED,
+		     addressT  from_addr ATTRIBUTE_UNUSED,
+		     addressT  to_addr   ATTRIBUTE_UNUSED,
+		     fragS *   frag      ATTRIBUTE_UNUSED,
+		     symbolS * to_symbol ATTRIBUTE_UNUSED)
 {
   as_fatal ("or32_create_long_jump\n");
 }
@@ -1267,9 +735,8 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
 /* Should never be called for or32.  */
 
 int
-md_estimate_size_before_relax (fragP, segtype)
-     fragS * fragP   ATTRIBUTE_UNUSED;
-     segT    segtype ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS * fragP   ATTRIBUTE_UNUSED,
+			       segT    segtype ATTRIBUTE_UNUSED)
 {
   as_fatal ("or32_estimate_size_before_relax\n");
   return 0;
@@ -1285,10 +752,9 @@ md_estimate_size_before_relax (fragP, segtype)
 
 #ifdef OBJ_AOUT
 void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
+tc_aout_fix_to_chars (char *where,
+		      fixS *fixP,
+		      relax_addressT segment_address_in_file)
 {
   long r_symbolnum;
 
@@ -1322,22 +788,19 @@ tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
 const char *md_shortopts = "";
 
 struct option md_longopts[] =
-  {
-    { NULL, no_argument, NULL, 0 }
-  };
+{
+  { NULL, no_argument, NULL, 0 }
+};
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int    c   ATTRIBUTE_UNUSED;
-     char * arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_show_usage (stream)
-     FILE * stream ATTRIBUTE_UNUSED;
+md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
 {
 }
 
@@ -1345,8 +808,7 @@ md_show_usage (stream)
    definitions of or32 style local labels.  */
 
 int
-or32_unrecognized_line (c)
-     int c;
+or32_unrecognized_line (int c)
 {
   int lab;
   char *s;
@@ -1381,75 +843,20 @@ or32_unrecognized_line (c)
   return 1;
 }
 
-#ifndef BFD_ASSEMBLER
-/* Record a fixup for a cons expression.  */
-/*
-  void
-or32_cons_fix_new (frag, where, nbytes, exp)
-     fragS *frag;
-     int where;
-     int nbytes;
-     expressionS *exp;
-{
-  fix_new_exp (frag, where, nbytes, exp, 0,
-		   nbytes == 5 ? RELOC_32
-                   : nbytes == 2 ? RELOC_16
-		   : RELOC_8);
-}
-void
-tc_aout_pre_write_hook ()
-{
-#if DEBUG
-  printf ("In tc_aout_pre_write_hook()\n");
-#endif
-}
-*/
-#endif
-
 /* Default the values of symbols known that should be "predefined".  We
    don't bother to predefine them unless you actually use one, since there
    are a lot of them.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
-#ifndef BFD_ASSEMBLER
-  long regnum;
-  char testbuf[5 + /*SLOP*/ 5];
-
-#if DEBUG
-  printf ("md_undefined_symbol(%s)\n", name);
-#endif
-
-  /* Register name.  */
-  if (name[0] == 'r' || name[0] == 'R' || name[0] == 'a' || name[0] == 'b')
-    {
-      /* Parse the number, make sure it has no extra zeroes or
-         trailing chars.  */
-      regnum = atol (& name[1]);
-
-      if (regnum > 31)
-        as_fatal (_("register out of range"));
-
-      sprintf (testbuf, "%ld", regnum);
-
-      if (strcmp (testbuf, &name[1]) != 0)
-        return NULL;  /* gr007 or lr7foo or whatever.  */
-
-      /* We have a wiener!  Define and return a new symbol for it.  */
-      return (symbol_new (name, SEG_REGISTER, (valueT) regnum,
-                          &zero_address_frag));
-    }
-#endif
   return NULL;
 }
 
 /* Parse an operand that is machine-specific.  */
 
 void
-md_operand (expressionP)
-     expressionS *expressionP;
+md_operand (expressionS *expressionP)
 {
 #if DEBUG
   printf ("  md_operand(input_line_pointer = %s)\n", input_line_pointer);
@@ -1577,9 +984,7 @@ md_operand (expressionP)
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size ATTRIBUTE_UNUSED;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size ATTRIBUTE_UNUSED)
 {
   return size;      /* Byte alignment is fine.  */
 }
@@ -1589,24 +994,20 @@ md_section_align (segment, size)
    which we have set up as the address of the fixup too.  */
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
 /* Generate a reloc for a fixup.  */
 
-#ifdef BFD_ASSEMBLER
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
   /*  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where + fixp->fx_addnumber;*/
@@ -1626,5 +1027,3 @@ tc_gen_reloc (seg, fixp)
   reloc->addend = fixp->fx_addnumber;
   return reloc;
 }
-#endif
-
diff --git a/gas/config/tc-or32.h b/gas/config/tc-or32.h
index 1a31a02b00b0..b17482d863f8 100644
--- a/gas/config/tc-or32.h
+++ b/gas/config/tc-or32.h
@@ -1,5 +1,5 @@
 /* tc-or32.h -- Assemble for the OpenRISC 1000.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003. 2005 Free Software Foundation, Inc.
    Contributed by Damjan Lampret <lampret@opencores.org>.
    Based upon a29k port.
 
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_OR32
 
@@ -38,16 +38,10 @@
 
 #define tc_unrecognized_line(c) or32_unrecognized_line (c)
 
-extern int or32_unrecognized_line PARAMS ((int));
+extern int or32_unrecognized_line (int);
 
-#define tc_headers_hook(a)    ; /* not used */
-#define tc_headers_hook(a)    ; /* not used */
-#define tc_crawl_symbol_chain(a)  ; /* not used */
-#define tc_coff_symbol_emit_hook(a) ; /* not used */
+#define tc_coff_symbol_emit_hook(a) ; /* Not used.  */
 
-#define AOUT_MACHTYPE               80
-#define TC_COFF_FIX2RTYPE(fix_ptr)  tc_coff_fix2rtype (fix_ptr)
-#define BFD_ARCH                    bfd_arch_or32
 #define COFF_MAGIC                  SIPFBOMAGIC
 
 /* No shared lib support, so we don't need to ensure externally
@@ -55,17 +49,8 @@ extern int or32_unrecognized_line PARAMS ((int));
 #define EXTERN_FORCE_RELOC 0
 
 #ifdef OBJ_ELF
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 #endif
 
-/* Should the reloc be output ?
-   on the 29k, this is true only if there is a symbol attached.
-   on the h8, this is always true, since no fixup is done.  */
-#define TC_COUNT_RELOC(x)           (x->fx_addsy)
-#define TC_CONS_RELOC               RELOC_32
-
-#define COFF_FLAGS                  F_AR32W
-#define NEED_FX_R_TYPE
-
 #define ZERO_BASED_SEGMENTS
diff --git a/gas/config/tc-pdp11.c b/gas/config/tc-pdp11.c
index 92023d130a80..cf103df92959 100644
--- a/gas/config/tc-pdp11.c
+++ b/gas/config/tc-pdp11.c
@@ -1,5 +1,5 @@
 /* tc-pdp11.c - pdp11-specific -
-   Copyright 2001, 2002 Free Software Foundation, Inc.
+   Copyright 2001, 2002, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,39 +15,24 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-/*
-  Apparently unused functions:
-    md_convert_frag
-    md_estimate_size_before_relax
-    md_create_short_jump
-    md_create_long_jump
-*/
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include "as.h"
 #include "safe-ctype.h"
 #include "opcode/pdp11.h"
 
-static int set_option PARAMS ((char *arg));
-static int set_cpu_model PARAMS ((char *arg));
-static int set_machine_model PARAMS ((char *arg));
-
-extern int flonum_gen2vax PARAMS ((char format_letter, FLONUM_TYPE * f,
-                                   LITTLENUM_TYPE * words));
+extern int flonum_gen2vax (int, FLONUM_TYPE * f, LITTLENUM_TYPE *);
 
-#define TRUE 1
+#define TRUE  1
 #define FALSE 0
 
-/*
- * A representation for PDP-11 machine code.
- */
+/* A representation for PDP-11 machine code.  */
 struct pdp11_code
 {
   char *error;
   int code;
-  int additional;	/* is there an additional word? */
-  int word;		/* additional word, if any */
+  int additional;	/* Is there an additional word?  */
+  int word;		/* Additional word, if any.  */
   struct
   {
     bfd_reloc_code_real_type type;
@@ -56,17 +41,13 @@ struct pdp11_code
   } reloc;
 };
 
-/*
- * Instruction set extensions.
- *
- * If you change this from an array to something else, please update
- * the "PDP-11 instruction set extensions" comment in pdp11.h.
- */
+/* Instruction set extensions.
+
+   If you change this from an array to something else, please update
+   the "PDP-11 instruction set extensions" comment in pdp11.h.  */
 int pdp11_extension[PDP11_EXT_NUM];
 
-/*
- * Assembly options.
- */
+/* Assembly options.  */
 
 #define ASM_OPT_PIC 1
 #define ASM_OPT_NUM 2
@@ -74,7 +55,7 @@ int pdp11_extension[PDP11_EXT_NUM];
 int asm_option[ASM_OPT_NUM];
 
 /* These chars start a comment anywhere in a source file (except inside
-   another comment */
+   another comment.  */
 const char comment_chars[] = "#/";
 
 /* These chars only start a comment at the beginning of a line.  */
@@ -82,12 +63,12 @@ const char line_comment_chars[] = "#/";
 
 const char line_separator_chars[] = ";";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
-/* Chars that mean this number is a floating point constant */
-/* as in 0f123.456 */
-/* or    0H1.234E-12 (see exp chars above) */
+/* Chars that mean this number is a floating point constant.  */
+/* as in 0f123.456.  */
+/* or    0H1.234E-12 (see exp chars above).  */
 const char FLT_CHARS[] = "dDfF";
 
 void pseudo_even (int);
@@ -100,8 +81,94 @@ const pseudo_typeS md_pseudo_table[] =
   { 0, 0, 0 },
 };
 
+static struct hash_control *insn_hash = NULL;
+
+static int
+set_option (char *arg)
+{
+  int yes = 1;
+
+  if (strcmp (arg, "all-extensions") == 0
+      || strcmp (arg, "all") == 0)
+    {
+      memset (pdp11_extension, ~0, sizeof pdp11_extension);
+      pdp11_extension[PDP11_NONE] = 0;
+      return 1;
+    }
+  else if (strcmp (arg, "no-extensions") == 0)
+    {
+      memset (pdp11_extension, 0, sizeof pdp11_extension);
+      pdp11_extension[PDP11_BASIC] = 1;
+      return 1;
+    }
+
+  if (strncmp (arg, "no-", 3) == 0)
+    {
+      yes = 0;
+      arg += 3;
+    }
+
+  /* Commersial instructions.  */
+  if (strcmp (arg, "cis") == 0)
+    pdp11_extension[PDP11_CIS] = yes;
+  /* Call supervisor mode.  */
+  else if (strcmp (arg, "csm") == 0)
+    pdp11_extension[PDP11_CSM] = yes;
+  /* Extended instruction set.  */
+  else if (strcmp (arg, "eis") == 0)
+    pdp11_extension[PDP11_EIS] = pdp11_extension[PDP11_LEIS] = yes;
+  /* KEV11 floating-point.  */
+  else if (strcmp (arg, "fis") == 0
+	   || strcmp (arg, "kev11") == 0
+	   || strcmp (arg, "kev-11") == 0)
+    pdp11_extension[PDP11_FIS] = yes;
+  /* FP-11 floating-point.  */
+  else if (strcmp (arg, "fpp") == 0
+	   || strcmp (arg, "fpu") == 0
+	   || strcmp (arg, "fp11") == 0
+	   || strcmp (arg, "fp-11") == 0
+	   || strcmp (arg, "fpj11") == 0
+	   || strcmp (arg, "fp-j11") == 0
+	   || strcmp (arg, "fpj-11") == 0)
+    pdp11_extension[PDP11_FPP] = yes;
+  /* Limited extended insns.  */
+  else if (strcmp (arg, "limited-eis") == 0)
+    {
+      pdp11_extension[PDP11_LEIS] = yes;
+      if (!pdp11_extension[PDP11_LEIS])
+	pdp11_extension[PDP11_EIS] = 0;
+    }
+  /* Move from processor type.  */
+  else if (strcmp (arg, "mfpt") == 0)
+    pdp11_extension[PDP11_MFPT] = yes;
+  /* Multiprocessor insns:  */
+  else if (strncmp (arg, "mproc", 5) == 0
+	   /* TSTSET, WRTLCK */
+	   || strncmp (arg, "multiproc", 9) == 0)
+    pdp11_extension[PDP11_MPROC] = yes;
+  /* Move from/to proc status.  */
+  else if (strcmp (arg, "mxps") == 0)
+    pdp11_extension[PDP11_MXPS] = yes;
+  /* Position-independent code.  */
+  else if (strcmp (arg, "pic") == 0)
+    asm_option[ASM_OPT_PIC] = yes;
+  /* Set priority level.  */
+  else if (strcmp (arg, "spl") == 0)
+    pdp11_extension[PDP11_SPL] = yes;
+  /* Microcode instructions:  */
+  else if (strcmp (arg, "ucode") == 0
+	   /* LDUB, MED, XFC */
+	   || strcmp (arg, "microcode") == 0)
+    pdp11_extension[PDP11_UCODE] = yes;
+  else
+    return 0;
+
+  return 1;
+}
+
+
 static void
-init_defaults ()
+init_defaults (void)
 {
   static int first = 1;
 
@@ -113,10 +180,8 @@ init_defaults ()
     }
 }
 
-static struct hash_control *insn_hash = NULL;
-
 void
-md_begin ()
+md_begin (void)
 {
   int i;
 
@@ -127,21 +192,17 @@ md_begin ()
     as_fatal ("Virtual memory exhausted");
 
   for (i = 0; i < pdp11_num_opcodes; i++)
-    hash_insert (insn_hash, pdp11_opcodes[i].name, (PTR)(pdp11_opcodes + i));
+    hash_insert (insn_hash, pdp11_opcodes[i].name, (void *) (pdp11_opcodes + i));
   for (i = 0; i < pdp11_num_aliases; i++)
-    hash_insert (insn_hash, pdp11_aliases[i].name, (PTR)(pdp11_aliases + i));
+    hash_insert (insn_hash, pdp11_aliases[i].name, (void *) (pdp11_aliases + i));
 }
 
 void
-md_number_to_chars (con, value, nbytes)
-     char con[];
-     valueT value;
-     int nbytes;
+md_number_to_chars (char con[], valueT value, int nbytes)
 {
   /* On a PDP-11, 0x1234 is stored as "\x12\x34", and
-   * 0x12345678 is stored as "\x56\x78\x12\x34". It's
-   * anyones guess what 0x123456 would be stored like.
-   */
+     0x12345678 is stored as "\x56\x78\x12\x34". It's
+     anyones guess what 0x123456 would be stored like.  */
 
   switch (nbytes)
     {
@@ -151,13 +212,13 @@ md_number_to_chars (con, value, nbytes)
       con[0] =  value       & 0xff;
       break;
     case 2:
-      con[0] =  value       & 0xff;
+      con[0] =  value        & 0xff;
       con[1] = (value >>  8) & 0xff;
       break;
     case 4:
       con[0] = (value >> 16) & 0xff;
       con[1] = (value >> 24) & 0xff;
-      con[2] =  value       & 0xff;
+      con[2] =  value        & 0xff;
       con[3] = (value >>  8) & 0xff;
       break;
     default:
@@ -169,10 +230,9 @@ md_number_to_chars (con, value, nbytes)
    that they reference.  Knows about order of bytes in address.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP,
+	       valueT * valP,
+	       segT seg ATTRIBUTE_UNUSED)
 {
   valueT code;
   valueT mask;
@@ -183,7 +243,7 @@ md_apply_fix3 (fixP, valP, seg)
 
   buf = fixP->fx_where + fixP->fx_frag->fr_literal;
   size = fixP->fx_size;
-  code = md_chars_to_number (buf, size);
+  code = md_chars_to_number ((unsigned char *) buf, size);
 
   switch (fixP->fx_r_type)
     {
@@ -199,6 +259,7 @@ md_apply_fix3 (fixP, valP, seg)
     case BFD_RELOC_PDP11_DISP_6_PCREL:
       mask = 0x003f;
       shift = 1;
+      val = -val;
       break;
     default:
       BAD_CASE (fixP->fx_r_type);
@@ -222,10 +283,8 @@ md_chars_to_number (con, nbytes)
      int nbytes;		/* Number of bytes in the input.  */
 {
   /* On a PDP-11, 0x1234 is stored as "\x12\x34", and
-   * 0x12345678 is stored as "\x56\x78\x12\x34". It's
-   * anyones guess what 0x123456 would be stored like.
-   */
-
+     0x12345678 is stored as "\x56\x78\x12\x34". It's
+     anyones guess what 0x123456 would be stored like.  */
   switch (nbytes)
     {
     case 0:
@@ -236,8 +295,8 @@ md_chars_to_number (con, nbytes)
       return (con[1] << BITS_PER_CHAR) | con[0];
     case 4:
       return
-	(((con[1] << BITS_PER_CHAR) | con[0]) << (2 * BITS_PER_CHAR)) |
-	 ((con[3] << BITS_PER_CHAR) | con[2]);
+	(((con[1] << BITS_PER_CHAR) | con[0]) << (2 * BITS_PER_CHAR))
+	|((con[3] << BITS_PER_CHAR) | con[2]);
     default:
       BAD_CASE (nbytes);
       return 0;
@@ -279,14 +338,14 @@ parse_reg (char *str, struct pdp11_code *operand)
 	  return str - 1;
 	}
     }
-  else if (strncmp (str, "sp", 2) == 0 ||
-	   strncmp (str, "SP", 2) == 0)
+  else if (strncmp (str, "sp", 2) == 0
+	   || strncmp (str, "SP", 2) == 0)
     {
       operand->code = 6;
       str += 2;
     }
-  else if (strncmp (str, "pc", 2) == 0 ||
-	   strncmp (str, "PC", 2) == 0)
+  else if (strncmp (str, "pc", 2) == 0
+	   || strncmp (str, "PC", 2) == 0)
     {
       operand->code = 7;
       str += 2;
@@ -304,10 +363,10 @@ static char *
 parse_ac5 (char *str, struct pdp11_code *operand)
 {
   str = skip_whitespace (str);
-  if (strncmp (str, "fr", 2) == 0 ||
-      strncmp (str, "FR", 2) == 0 ||
-      strncmp (str, "ac", 2) == 0 ||
-      strncmp (str, "AC", 2) == 0)
+  if (strncmp (str, "fr", 2) == 0
+      || strncmp (str, "FR", 2) == 0
+      || strncmp (str, "ac", 2) == 0
+      || strncmp (str, "AC", 2) == 0)
     {
       str += 2;
       switch (*str)
@@ -365,30 +424,6 @@ parse_expression (char *str, struct pdp11_code *operand)
 
   operand->reloc.pc_rel = 0;
 
-#if 0
-  /* FIXME: what follows is broken badly.  You can't deal with differences
-     in radix conventions this way, because of symbolic constants, constant
-     expressions made up of pieces of differing radix, etc.  The only
-     choices are to change ../expr.c to know about pdp11 conventions, or
-     to accept the fact that gas will use consistent conventions that differ
-     from those of traditional pdp11 assemblers.  For now, I've
-     chosen the latter.   paul koning, 12/23/2001
-  */
-  if (operand->reloc.exp.X_op == O_constant)
-    {
-      if (*str == '.')
-	str++;
-      else
-	{
-	  /* FIXME: buffer overflow! */
-	  char buf[100];
-	  char *end;
-
-	  sprintf (buf, "%ld", operand->reloc.exp.X_add_number);
-	  operand->reloc.exp.X_add_number = strtol (buf, &end, 8);
-	}
-    }
-#endif
   return str;
 }
 
@@ -423,7 +458,8 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
 	}
       break;
 
-    case '#':				/* immediate */
+      /* Immediate.  */
+    case '#':
     case '$':
       str = parse_expression (str + 1, operand);
       if (operand->error)
@@ -446,7 +482,7 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
               operand->error = "Error in expression";
               break;
             }
-          /* it's a floating literal...  */
+          /* It's a floating literal...  */
           know (operand->reloc.exp.X_add_number < 0);
           flonum_gen2vax ('f', &generic_floating_point_number, literal_float);
           operand->word = literal_float[0];
@@ -460,7 +496,8 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
       operand->code = 027;
       break;
 
-    default:				/* label, d(rn), -(rn) */
+      /* label, d(rn), -(rn)  */
+    default:
       {
 	char *old = str;
 
@@ -486,7 +523,7 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
 
 	str = skip_whitespace (str);
 
-	if (*str != '(')		/* label */
+	if (*str != '(')
 	  {
 	    if (operand->reloc.exp.X_op != O_symbol)
 	      {
@@ -501,7 +538,8 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
 	    break;
 	  }
 
-	str++;				/* d(rn) */
+	/* d(rn) */
+	str++;
 	str = parse_reg (str, operand);
 	if (operand->error)
 	  return str;
@@ -530,9 +568,8 @@ parse_op_no_deferred (char *str, struct pdp11_code *operand)
 		operand->word = operand->reloc.exp.X_add_number;
 	      }
 	    else
-	      {
-		operand->word = operand->reloc.exp.X_add_number;
-	      }
+	      operand->word = operand->reloc.exp.X_add_number;
+
 	    break;
 	  default:
 	    BAD_CASE (operand->reloc.exp.X_op);
@@ -614,8 +651,7 @@ parse_separator (char *str, int *error)
 }
 
 void
-md_assemble (instruction_string)
-     char *instruction_string;
+md_assemble (char *instruction_string)
 {
   const struct pdp11_opcode *op;
   struct pdp11_code insn, op1, op2;
@@ -640,31 +676,7 @@ md_assemble (instruction_string)
   *p = c;
   if (op == 0)
     {
-#if 0
-      op1.error = NULL;
-      op1.additional = FALSE;
-      op1.reloc.type = BFD_RELOC_NONE;
-      op1.code = 0;
-      op1.word = 0;
-      str = parse_expression (str, &op1);
-      if (op1.error)
-	{
-	  as_bad (op1.error);
-	  return;
-	}
-
-      {
-	char *to = frag_more (2);
-
-	md_number_to_chars (to, op1.code, 2);
-	if (insn.reloc.type != BFD_RELOC_NONE)
-	  fix_new_exp (frag_now, to - frag_now->fr_literal, 2,
-		       &insn.reloc.exp, insn.reloc.pc_rel, insn.reloc.type);
-      }
-#else
       as_bad (_("Unknown instruction '%s'"), str);
-#endif
-
       return;
     }
 
@@ -1004,117 +1016,42 @@ md_assemble (instruction_string)
 }
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP ATTRIBUTE_UNUSED;
-     segT segment ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+			       segT segment ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_convert_frag (headers, seg, fragP)
-     bfd *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
+		 segT seg ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
 {
 }
 
-const int md_short_jump_size = 2;
-const int md_long_jump_size = 4;
+int md_short_jump_size = 2;
+int md_long_jump_size = 4;
 
 void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr ATTRIBUTE_UNUSED;
-     addressT from_addr ATTRIBUTE_UNUSED;
-     addressT to_addr ATTRIBUTE_UNUSED;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char *ptr ATTRIBUTE_UNUSED,
+		      addressT from_addr ATTRIBUTE_UNUSED,
+		      addressT to_addr ATTRIBUTE_UNUSED,
+		      fragS *frag ATTRIBUTE_UNUSED,
+		      symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
 }
 
 void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr ATTRIBUTE_UNUSED;
-     addressT from_addr ATTRIBUTE_UNUSED;
-     addressT to_addr ATTRIBUTE_UNUSED;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
-{
-}
-
-static int
-set_option (arg)
-     char *arg;
+md_create_long_jump (char *ptr ATTRIBUTE_UNUSED,
+		     addressT from_addr ATTRIBUTE_UNUSED,
+		     addressT to_addr ATTRIBUTE_UNUSED,
+		     fragS *frag ATTRIBUTE_UNUSED,
+		     symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
-  int yes = 1;
-
-  if (strcmp (arg, "all-extensions") == 0 ||
-      strcmp (arg, "all") == 0)
-    {
-      memset (pdp11_extension, ~0, sizeof pdp11_extension);
-      pdp11_extension[PDP11_NONE] = 0;
-      return 1;
-    }
-  else if (strcmp (arg, "no-extensions") == 0)
-    {
-      memset (pdp11_extension, 0, sizeof pdp11_extension);
-      pdp11_extension[PDP11_BASIC] = 1;
-      return 1;
-    }
-
-  if (strncmp (arg, "no-", 3) == 0)
-    {
-      yes = 0;
-      arg += 3;
-    }
-
-  if (strcmp (arg, "cis") == 0)			/* commersial instructions */
-    pdp11_extension[PDP11_CIS] = yes;
-  else if (strcmp (arg, "csm") == 0)		/* call supervisor mode */
-    pdp11_extension[PDP11_CSM] = yes;
-  else if (strcmp (arg, "eis") == 0)		/* extended instruction set */
-    pdp11_extension[PDP11_EIS] = pdp11_extension[PDP11_LEIS] = yes;
-  else if (strcmp (arg, "fis") == 0 ||		/* KEV11 floating-point */
-	   strcmp (arg, "kev11") == 0 ||
-	   strcmp (arg, "kev-11") == 0)
-    pdp11_extension[PDP11_FIS] = yes;
-  else if (strcmp (arg, "fpp") == 0 ||		/* FP-11 floating-point */
-	   strcmp (arg, "fpu") == 0 ||
-	   strcmp (arg, "fp11") == 0 ||
-	   strcmp (arg, "fp-11") == 0 ||
-	   strcmp (arg, "fpj11") == 0 ||
-	   strcmp (arg, "fp-j11") == 0 ||
-	   strcmp (arg, "fpj-11") == 0)
-    pdp11_extension[PDP11_FPP] = yes;
-  else if (strcmp (arg, "limited-eis") == 0)	/* limited extended insns */
-    {
-      pdp11_extension[PDP11_LEIS] = yes;
-      if (!pdp11_extension[PDP11_LEIS])
-	pdp11_extension[PDP11_EIS] = 0;
-    }
-  else if (strcmp (arg, "mfpt") == 0)		/* move from processor type */
-    pdp11_extension[PDP11_MFPT] = yes;
-  else if (strncmp (arg, "mproc", 5) == 0 ||	/* multiprocessor insns: */
-	   strncmp (arg, "multiproc", 9) == 0 )	/* TSTSET, WRTLCK */
-    pdp11_extension[PDP11_MPROC] = yes;
-  else if (strcmp (arg, "mxps") == 0)		/* move from/to proc status */
-    pdp11_extension[PDP11_MXPS] = yes;
-  else if (strcmp (arg, "pic") == 0)		/* position-independent code */
-    asm_option[ASM_OPT_PIC] = yes;
-  else if (strcmp (arg, "spl") == 0)		/* set priority level */
-    pdp11_extension[PDP11_SPL] = yes;
-  else if (strcmp (arg, "ucode") == 0 ||	/* microcode instructions: */
-	   strcmp (arg, "microcode") == 0)	/* LDUB, MED, XFC */
-    pdp11_extension[PDP11_UCODE] = yes;
-  else
-    return 0;
-
-  return 1;
 }
 
 static int
-set_cpu_model (arg)
-     char *arg;
+set_cpu_model (char *arg)
 {
   char buf[4];
   char *model = buf;
@@ -1129,8 +1066,7 @@ set_cpu_model (arg)
 
   if (model[-1] == 'd')
     {
-      if (arg[0] == 'f' ||
-	  arg[0] == 'j')
+      if (arg[0] == 'f' || arg[0] == 'j')
 	model[-1] = *arg++;
     }
   else if (model[-1] == 'x')
@@ -1152,7 +1088,7 @@ set_cpu_model (arg)
 	return 0;
     }
 
-  /* allow up to two revision letters */
+  /* Allow up to two revision letters.  */
   if (arg[0] != 0)
     *model++ = *arg++;
   if (arg[0] != 0)
@@ -1162,70 +1098,80 @@ set_cpu_model (arg)
 
   set_option ("no-extensions");
 
-  if (strncmp (buf, "a", 1) == 0)		/* KA11 (11/15/20) */
-    return 1; /* no extensions */
+  /* KA11 (11/15/20).  */
+  if (strncmp (buf, "a", 1) == 0)
+    return 1; /* No extensions.  */
 
-  else if (strncmp (buf, "b", 1) == 0)		/* KB11 (11/45/50/55/70) */
-    return set_option ("eis") &&
-           set_option ("spl");
+  /* KB11 (11/45/50/55/70).  */
+  else if (strncmp (buf, "b", 1) == 0)
+    return set_option ("eis") && set_option ("spl");
 
-  else if (strncmp (buf, "da", 2) == 0)		/* KD11-A (11/35/40) */
+  /* KD11-A (11/35/40).  */
+  else if (strncmp (buf, "da", 2) == 0)
     return set_option ("limited-eis");
 
-  else if (strncmp (buf, "db", 2) == 0 ||	/* KD11-B (11/05/10) */
-	   strncmp (buf, "dd", 2) == 0)		/* KD11-D (11/04) */
+  /* KD11-B (11/05/10).  */
+  else if (strncmp (buf, "db", 2) == 0
+	   /* KD11-D (11/04).  */
+	   || strncmp (buf, "dd", 2) == 0)
     return 1; /* no extensions */
 
-  else if (strncmp (buf, "de", 2) == 0)		/* KD11-E (11/34) */
-    return set_option ("eis") &&
-           set_option ("mxps");
-
-  else if (strncmp (buf, "df", 2) == 0 ||	/* KD11-F (11/03) */
-	   strncmp (buf, "dh", 2) == 0 ||	/* KD11-H (11/03) */
-	   strncmp (buf, "dq", 2) == 0)		/* KD11-Q (11/03) */
-    return set_option ("limited-eis") &&
-           set_option ("mxps");
-
-  else if (strncmp (buf, "dk", 2) == 0)		/* KD11-K (11/60) */
-    return set_option ("eis") &&
-           set_option ("mxps") &&
-           set_option ("ucode");
-
-  else if (strncmp (buf, "dz", 2) == 0)		/* KD11-Z (11/44) */
-    return set_option ("csm") &&
-           set_option ("eis") &&
-           set_option ("mfpt") &&
-           set_option ("mxps") &&
-           set_option ("spl");
-
-  else if (strncmp (buf, "f", 1) == 0)		/* F11 (11/23/24) */
-    return set_option ("eis") &&
-           set_option ("mfpt") &&
-           set_option ("mxps");
-
-  else if (strncmp (buf, "j", 1) == 0)		/* J11 (11/53/73/83/84/93/94)*/
-    return set_option ("csm") &&
-           set_option ("eis") &&
-           set_option ("mfpt") &&
-           set_option ("multiproc") &&
-           set_option ("mxps") &&
-           set_option ("spl");
-
-  else if (strncmp (buf, "t", 1) == 0)		/* T11 (11/21) */
-    return set_option ("limited-eis") &&
-           set_option ("mxps");
+  /* KD11-E (11/34).  */
+  else if (strncmp (buf, "de", 2) == 0)
+    return set_option ("eis") && set_option ("mxps");
+
+  /* KD11-F (11/03).  */
+  else if (strncmp (buf, "df", 2) == 0
+	   /* KD11-H (11/03).  */
+	   || strncmp (buf, "dh", 2) == 0
+	   /* KD11-Q (11/03).  */
+	   || strncmp (buf, "dq", 2) == 0)
+    return set_option ("limited-eis") && set_option ("mxps");
+
+  /* KD11-K (11/60).  */
+  else if (strncmp (buf, "dk", 2) == 0)
+    return set_option ("eis")
+      && set_option ("mxps")
+      && set_option ("ucode");
+
+  /* KD11-Z (11/44).  */
+  else if (strncmp (buf, "dz", 2) == 0)
+    return set_option ("csm")
+      && set_option ("eis")
+      && set_option ("mfpt")
+      && set_option ("mxps")
+      && set_option ("spl");
+
+  /* F11 (11/23/24).  */
+  else if (strncmp (buf, "f", 1) == 0)
+    return set_option ("eis")
+      && set_option ("mfpt")
+      && set_option ("mxps");
+
+  /* J11 (11/53/73/83/84/93/94).  */
+  else if (strncmp (buf, "j", 1) == 0)
+    return set_option ("csm")
+      && set_option ("eis")
+      && set_option ("mfpt")
+      && set_option ("multiproc")
+      && set_option ("mxps")
+      && set_option ("spl");
+
+  /* T11 (11/21).  */
+  else if (strncmp (buf, "t", 1) == 0)
+    return set_option ("limited-eis")
+      && set_option ("mxps");
 
   else
     return 0;
 }
 
 static int
-set_machine_model (arg)
-     char *arg;
+set_machine_model (char *arg)
 {
-  if (strncmp (arg, "pdp-11/", 7) != 0 &&
-      strncmp (arg, "pdp11/", 6) != 0 &&
-      strncmp (arg, "11/", 3) != 0)
+  if (strncmp (arg, "pdp-11/", 7) != 0
+      && strncmp (arg, "pdp11/", 6) != 0
+      && strncmp (arg, "11/", 3) != 0)
     return 0;
 
   if (strncmp (arg, "pdp", 3) == 0)
@@ -1235,56 +1181,56 @@ set_machine_model (arg)
   if (strncmp (arg, "11/", 3) == 0)
     arg += 3;
 
-  if (strcmp (arg, "03") == 0)			/* 11/03 */
-    return set_cpu_model ("kd11f");		/* KD11-F */
+  if (strcmp (arg, "03") == 0)
+    return set_cpu_model ("kd11f");
+
+  else if (strcmp (arg, "04") == 0)
+    return set_cpu_model ("kd11d");
 
-  else if (strcmp (arg, "04") == 0)		/* 11/04 */
-    return set_cpu_model ("kd11d");		/* KD11-D */
+  else if (strcmp (arg, "05") == 0
+	   || strcmp (arg, "10") == 0)
+    return set_cpu_model ("kd11b");
 
-  else if (strcmp (arg, "05") == 0 ||		/* 11/05 or 11/10 */
-	   strcmp (arg, "10") == 0)
-    return set_cpu_model ("kd11b");		/* KD11-B */
+  else if (strcmp (arg, "15") == 0
+	   || strcmp (arg, "20") == 0)
+    return set_cpu_model ("ka11");
 
-  else if (strcmp (arg, "15") == 0 ||		/* 11/15 or 11/20 */
-	   strcmp (arg, "20") == 0)
-    return set_cpu_model ("ka11");		/* KA11 */
+  else if (strcmp (arg, "21") == 0)
+    return set_cpu_model ("t11");
 
-  else if (strcmp (arg, "21") == 0)		/* 11/21 */
-    return set_cpu_model ("t11");		/* T11 */
+  else if (strcmp (arg, "23") == 0
+	   || strcmp (arg, "24") == 0)
+    return set_cpu_model ("f11");
 
-  else if (strcmp (arg, "23") == 0 ||		/* 11/23 or 11/24 */
-	   strcmp (arg, "24") == 0)
-    return set_cpu_model ("f11");		/* F11 */
+  else if (strcmp (arg, "34") == 0
+	   || strcmp (arg, "34a") == 0)
+    return set_cpu_model ("kd11e");
 
-  else if (strcmp (arg, "34") == 0 ||		/* 11/34 or 11/34a */
-           strcmp (arg, "34a") == 0)
-    return set_cpu_model ("kd11e");		/* KD11-E */
+  else if (strcmp (arg, "35") == 0
+	   || strcmp (arg, "40") == 0)
+    return set_cpu_model ("kd11da");
 
-  else if (strcmp (arg, "35") == 0 ||		/* 11/35 or 11/40 */
-	   strcmp (arg, "40") == 0)
-    return set_cpu_model ("kd11da");		/* KD11-A */
+  else if (strcmp (arg, "44") == 0)
+    return set_cpu_model ("kd11dz");
 
-  else if (strcmp (arg, "44") == 0)		/* 11/44 */
-    return set_cpu_model ("kd11dz");		/* KD11-Z */
+  else if (strcmp (arg, "45") == 0
+	   || strcmp (arg, "50") == 0
+	   || strcmp (arg, "55") == 0
+	   || strcmp (arg, "70") == 0)
+    return set_cpu_model ("kb11");
 
-  else if (strcmp (arg, "45") == 0 ||		/* 11/45/50/55/70 */
-	   strcmp (arg, "50") == 0 ||
-	   strcmp (arg, "55") == 0 ||
-	   strcmp (arg, "70") == 0)
-    return set_cpu_model ("kb11");		/* KB11 */
+  else if (strcmp (arg, "60") == 0)
+    return set_cpu_model ("kd11k");
 
-  else if (strcmp (arg, "60") == 0)		/* 11/60 */
-    return set_cpu_model ("kd11k");		/* KD11-K */ /* FPP? */
+  else if (strcmp (arg, "53") == 0
+	   || strcmp (arg, "73") == 0
+	   || strcmp (arg, "83") == 0
+	   || strcmp (arg, "84") == 0
+	   || strcmp (arg, "93") == 0
+	   || strcmp (arg, "94") == 0)
+    return set_cpu_model ("j11")
+      && set_option ("fpp");
 
-  else if (strcmp (arg, "53") == 0 ||		/* 11/53/73/83/84/93/94 */
-	   strcmp (arg, "73") == 0 ||
-	   strcmp (arg, "83") == 0 ||
-	   strcmp (arg, "84") == 0 ||
-	   strcmp (arg, "93") == 0 ||
-	   strcmp (arg, "94") == 0)
-    return set_cpu_model ("j11") &&		/* J11 */
-           set_option ("fpp");			/* All J11 machines come */
-						/* with FPP installed.  */
   else
     return 0;
 }
@@ -1304,16 +1250,11 @@ struct option md_longopts[] =
 
 size_t md_longopts_size = sizeof (md_longopts);
 
-/*
- * md_parse_option
- *	Invocation line includes a switch not recognized by the base assembler.
- *	See if it's a processor-specific option.
- */
+/* Invocation line includes a switch not recognized by the base assembler.
+   See if it's a processor-specific option.  */
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   init_defaults ();
 
@@ -1347,254 +1288,11 @@ md_parse_option (c, arg)
       break;
     }
 
-  as_bad ("unrecognized option `-%c%s'", c, arg ? arg : "");
-
   return 0;
 }
 
-/*
-One possible way of parsing options.
-
-enum
-{
-  OPTION_CSM,
-  OPTION_CIS,
-  ...
-};
-
-struct
-{
-  const char *pattern;
-  int opt;
-  const char *description;
-} options;
-
-static struct options extension_opts[] =
-{
-  { "Ncsm", OPTION_CSM,
-			"allow (disallow) CSM instruction" },
-  { "Ncis", OPTION_CIS,
-			"allow (disallow) commersial instruction set" },
-  { "Neis", OPTION_EIS,
-			"allow (disallow) extended instruction set" },
-  ...
-  { "all-extensions", OPTION_ALL_EXTENSIONS,
-			"allow all instruction set extensions\n\
-			(this is the default)" },
-  { "no-extensions", OPTION_NO_EXTENSIONS,
-			"disallow all instruction set extensions" },
-  { "pic", OPTION_PIC,
-			"position-independent code" },
-};
-
-static struct options cpu_opts[] =
-{
-  { "Ka_11_*", OPTION_KA11, "KA11 CPU. ..." },
-  { "Kb_11_*", OPTION_KB11, "KB11 CPU. ..." },
-  { "Kd_11_a*", OPTION_KD11A, "KD11-A CPU. ..." },
-  { "Kd_11_b*", OPTION_KD11B, "KD11-B CPU. ..." },
-  { "Kd_11_d*", OPTION_KD11D, "KD11-D CPU. ..." },
-  { "Kd_11_e*", OPTION_KD11E, "KD11-E CPU. ..." },
-  { "Kd_11_f*", OPTION_KD11F, "KD11-F CPU. ..." },
-  { "Kd_11_h*", OPTION_KD11H, "KD11-H CPU. ..." },
-  { "Kd_11_q*", OPTION_KD11Q, "KD11-Q CPU. ..." },
-  { "Kd_11_z*", OPTION_KD11Z, "KD11-Z CPU. ..." },
-  { "Df_11_*", OPTION_F11, "F11 CPU. ..." },
-  { "Dj_11_*", OPTION_J11, "J11 CPU. ..." },
-  { "Dt_11_*", OPTION_T11, "T11 CPU. ..." },
-};
-
-static struct options model_opts[] =
-{
-  { "P03", OPTION_PDP11_03, "same as ..." },
-  { "P04", OPTION_PDP11_04, "same as ..." },
-  { "P05", OPTION_PDP11_05, "same as ..." },
-  { "P10", OPTION_PDP11_10, "same as ..." },
-  { "P15", OPTION_PDP11_15, "same as ..." },
-  { "P20", OPTION_PDP11_20, "same as ..." },
-  { "P21", OPTION_PDP11_21, "same as ..." },
-  { "P24", OPTION_PDP11_24, "same as ..." },
-  { "P34", OPTION_PDP11_34, "same as ..." },
-  { "P34a", OPTION_PDP11_34A, "same as ..." },
-  { "P40", OPTION_PDP11_40, "same as ..." },
-  { "P44", OPTION_PDP11_44, "same as ..." },
-  { "P45", OPTION_PDP11_45, "same as ..." },
-  { "P50", OPTION_PDP11_50, "same as ..." },
-  { "P53", OPTION_PDP11_53, "same as ..." },
-  { "P55", OPTION_PDP11_55, "same as ..." },
-  { "P60", OPTION_PDP11_60, "same as ..." },
-  { "P70", OPTION_PDP11_70, "same as ..." },
-  { "P73", OPTION_PDP11_73, "same as ..." },
-  { "P83", OPTION_PDP11_83, "same as ..." },
-  { "P84", OPTION_PDP11_84, "same as ..." },
-  { "P93", OPTION_PDP11_93, "same as ..." },
-  { "P94", OPTION_PDP11_94, "same as ..." },
-};
-
-struct
-{
-  const char *title;
-  struct options *opts;
-  int num;
-} all_opts[] =
-{
-  { "PDP-11 instruction set extentions",
-    extension_opts,
-    sizeof extension_opts / sizeof extension_opts[0] },
-  { "PDP-11 CPU model options",
-    cpu_opts,
-    sizeof cpu_opts / sizeof cpu_opts[0] },
-  { "PDP-11 machine model options",
-    model_opts,
-    sizeof model_opts / sizeof model_opts[0] },
-};
-
-int
-parse_match (char *arg, char *pattern)
-{
-  int yes = 1;
-
-  while (*pattern)
-    {
-      switch (*pattern++)
-	{
-	case 'N':
-	  if (strncmp (arg, "no-") == 0)
-	    {
-	      yes = 0;
-	      arg += 3;
-	    }
-	  break;
-
-	case 'K':
-	  if (arg[0] == 'k')
-	    arg++;
-	  break;
-
-	case 'D':
-	  if (strncmp (arg, "kd", 2) == 0)
-	    arg +=2;
-	  break;
-
-	case 'P':
-	  if (strncmp (arg, "pdp-11/", 7) == 0)
-	    arg += 7;
-	  else if (strncmp (arg, "pdp11/", 6) == 0)
-	    arg += 6;
-	  else if (strncmp (arg, "11/", 3) == 0)
-	    arg += 3;
-	  break;
-
-	case '_':
-	  if (arg[0] == "-")
-	    {
-	      if (*++arg == 0)
-		return 0;
-	    }
-	  break;
-
-	case '*':
-	  return 1;
-
-	default:
-	  if (*arg++ != pattern[-1])
-	    return 0;
-	}
-    }
-
-  return arg[0] == 0;
-}
-
-int
-fprint_opt (stream, pattern)
-     FILE *stream;
-     const char *pattern;
-{
-  int n;
-
-  while (*pattern)
-    {
-      switch (*pattern++)
-	{
-	case 'N':
-	  n += fprintf (stream, "(no-)");
-	  break;
-
-	case 'K':
-	  n += fprintf (stream, "k");
-	  break;
-
-	case 'P':
-	  n += fprintf (stream "11/");
-	  break;
-
-	case 'D':
-	case '_':
-	case '*':
-	  break;
-
-	default:
-	  fputc (pattern[-1], stream);
-	  n++;
-	}
-    }
-
-  return n;
-}
-
-int
-parse_option (char *arg)
-{
-  int i, j;
-
-  for (i = 0; i < sizeof all_opts / sizeof all_opts[0]; i++)
-    {
-      for (j = 0; j < all_opts[i].num; j++)
-	{
-	  if (parse_match (arg, all_opts[i].opts[j].pattern))
-	    {
-	      set_option (all_opts[i].opts[j].opt);
-	      return 1;
-	    }
-	}
-    }
-
-  return 0;
-}
-
-static void
-fprint_space (stream, n)
-     FILE *stream;
-     int n;
-{
-  while (n--)
-    fputc (' ', stream);
-}
-
 void
-md_show_usage (stream)
-     FILE *stream;
-{
-  int i, j, n;
-
-  for (i = 0; i < sizeof all_opts / sizeof all_opts[0]; i++)
-    {
-      fprintf (stream "\n%s:\n\n", all_opts[i].title);
-
-      for (j = 0; j < all_opts[i].num; j++)
-	{
-	  fprintf (stream, "-m");
-	  n = fprintf_opt (stream, all_opts[i].opts[j].pattern);
-	  fprint_space (stream, 22 - n);
-	  fprintf (stream, "%s\n", all_opts[i].opts[j].description);
-	}
-    }
-}
-*/
-
-void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, "\
 \n\
@@ -1668,44 +1366,41 @@ PDP-11 machine model options:\n\
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED,
+		  valueT size)
 {
   return (size + 1) & ~1;
 }
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_frag->fr_address + fixP->fx_where + fixP->fx_size;
 }
 
 /* Translate internal representation of relocation info to BFD target
    format.  */
+
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
+	      fixS *fixp)
 {
   arelent *reloc;
   bfd_reloc_code_real_type code;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (* reloc));
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
-  /* This is taken account for in md_apply_fix3().  */
+  /* This is taken account for in md_apply_fix().  */
   reloc->addend = -symbol_get_bfdsym (fixp->fx_addsy)->section->vma;
 
   switch (fixp->fx_r_type)
@@ -1740,8 +1435,7 @@ tc_gen_reloc (section, fixp)
 }
 
 void
-pseudo_bss (c)
-     int c ATTRIBUTE_UNUSED;
+pseudo_bss (int c ATTRIBUTE_UNUSED)
 {
   int temp;
 
@@ -1751,12 +1445,9 @@ pseudo_bss (c)
 }
 
 void
-pseudo_even (c)
-     int c ATTRIBUTE_UNUSED;
+pseudo_even (int c ATTRIBUTE_UNUSED)
 {
   int alignment = 1; /* 2^1 */
   frag_align (alignment, 0, 1);
   record_alignment (now_seg, alignment);
 }
-
-/* end of tc-pdp11.c */
diff --git a/gas/config/tc-pdp11.h b/gas/config/tc-pdp11.h
index d831ec395278..53200dd788ed 100644
--- a/gas/config/tc-pdp11.h
+++ b/gas/config/tc-pdp11.h
@@ -1,5 +1,5 @@
 /* tc-pdp11.h -- Header file for tc-pdp11.c.
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 2001, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_PDP11 1
 
@@ -28,6 +28,6 @@
 
 #define md_operand(x)
 
-long md_chars_to_number PARAMS ((unsigned char *, int));
+long md_chars_to_number (unsigned char *, int);
 
 /* end of tc-pdp11.h */
diff --git a/gas/config/tc-pj.c b/gas/config/tc-pj.c
index a0666e17dee8..dff23145bad8 100644
--- a/gas/config/tc-pj.c
+++ b/gas/config/tc-pj.c
@@ -1,6 +1,7 @@
 /*-
    tc-pj.c -- Assemble code for Pico Java
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* Contributed by Steve Chamberlain of Transmeta <sac@pobox.com>.  */
 
@@ -27,43 +28,27 @@
 
 extern const pj_opc_info_t pj_opc_info[512];
 
-const char comment_chars[] = "!/";
+const char comment_chars[]        = "!/";
 const char line_separator_chars[] = ";";
-const char line_comment_chars[] = "/!#";
+const char line_comment_chars[]   = "/!#";
 
 static int pending_reloc;
 static struct hash_control *opcode_hash_control;
 
-static void little
-  PARAMS ((int));
-static void big
-  PARAMS ((int));
-static char *parse_exp_save_ilp
-  PARAMS ((char *, expressionS *));
-static int c_to_r
-  PARAMS ((char));
-static void ipush_code
-  PARAMS ((pj_opc_info_t *, char *));
-static void fake_opcode
-  PARAMS ((const char *, void (*) (struct pj_opc_info_t *, char *)));
-static void alias
-  PARAMS ((const char *, const char *));
-
 static void
-little (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+little (int ignore ATTRIBUTE_UNUSED)
 {
   target_big_endian = 0;
 }
 
 static void
-big (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+big (int ignore ATTRIBUTE_UNUSED)
 {
   target_big_endian = 1;
 }
 
-const pseudo_typeS md_pseudo_table[] = {
+const pseudo_typeS md_pseudo_table[] =
+{
   {"ml",    little, 0},
   {"mb",    big,    0},
   {0, 0, 0}
@@ -73,8 +58,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
 const char EXP_CHARS[] = "eE";
 
 void
-md_operand (op)
-     expressionS *op;
+md_operand (expressionS *op)
 {
   if (strncmp (input_line_pointer, "%hi16", 5) == 0)
     {
@@ -84,6 +68,7 @@ md_operand (op)
       input_line_pointer += 5;
       expression (op);
     }
+
   if (strncmp (input_line_pointer, "%lo16", 5) == 0)
     {
       if (pending_reloc)
@@ -97,11 +82,10 @@ md_operand (op)
 /* Parse an expression and then restore the input line pointer.  */
 
 static char *
-parse_exp_save_ilp (s, op)
-     char *s;
-     expressionS *op;
+parse_exp_save_ilp (char *s, expressionS *op)
 {
   char *save = input_line_pointer;
+
   input_line_pointer = s;
   expression (op);
   s = input_line_pointer;
@@ -114,11 +98,7 @@ parse_exp_save_ilp (s, op)
    we want to handle magic pending reloc expressions specially.  */
 
 void
-pj_cons_fix_new_pj (frag, where, nbytes, exp)
-     fragS *frag;
-     int where;
-     int nbytes;
-     expressionS *exp;
+pj_cons_fix_new_pj (fragS *frag, int where, int nbytes, expressionS *exp)
 {
   static int rv[5][2] =
   { { 0, 0 },
@@ -138,8 +118,7 @@ pj_cons_fix_new_pj (frag, where, nbytes, exp)
    code which BFD can handle.  */
 
 static int
-c_to_r (x)
-     char x;
+c_to_r (int x)
 {
   switch (x)
     {
@@ -166,9 +145,7 @@ c_to_r (x)
    turns ipush <foo> into sipush lo16<foo>, sethi hi16<foo>.  */
 
 static void
-ipush_code (opcode, str)
-     pj_opc_info_t *opcode ATTRIBUTE_UNUSED;
-     char *str;
+ipush_code (pj_opc_info_t *opcode ATTRIBUTE_UNUSED, char *str)
 {
   char *b = frag_more (6);
   expressionS arg;
@@ -192,11 +169,10 @@ ipush_code (opcode, str)
    not opcodes.  The fakeness is indicated with an opcode of -1.  */
 
 static void
-fake_opcode (name, func)
-     const char *name;
-     void (*func) PARAMS ((struct pj_opc_info_t *, char *));
+fake_opcode (const char *name,
+	     void (*func) (struct pj_opc_info_t *, char *))
 {
-  pj_opc_info_t *fake = (pj_opc_info_t *) xmalloc (sizeof (pj_opc_info_t));
+  pj_opc_info_t * fake = xmalloc (sizeof (pj_opc_info_t));
 
   fake->opcode = -1;
   fake->opcode_next = -1;
@@ -208,9 +184,7 @@ fake_opcode (name, func)
    can have another name.  */
 
 static void
-alias (new, old)
-     const char *new;
-     const char *old;
+alias (const char *new, const char *old)
 {
   hash_insert (opcode_hash_control, new,
 	       (char *) hash_find (opcode_hash_control, old));
@@ -221,7 +195,7 @@ alias (new, old)
    some aliases for compatibility with other assemblers.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   const pj_opc_info_t *opcode;
   opcode_hash_control = hash_new ();
@@ -250,15 +224,11 @@ md_begin ()
    the frags/bytes it assembles to.  */
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
-  unsigned char *op_start;
-  unsigned char *op_end;
+  char *op_start;
+  char *op_end;
 
-#if 0
-  pj_operan_info operand[3];
-#endif
   pj_opc_info_t *opcode;
   char *output;
   int idx = 0;
@@ -271,8 +241,9 @@ md_assemble (str)
     str++;
 
   /* Find the op code end.  */
-  for (op_start = op_end = (unsigned char *) (str);
-       *op_end && !is_end_of_line[*op_end] && *op_end != ' ';
+  op_start = str;
+  for (op_end = str;
+       *op_end && !is_end_of_line[*op_end & 0xff] && *op_end != ' ';
        op_end++)
     nlen++;
 
@@ -349,10 +320,7 @@ md_assemble (str)
    returned, or NULL on OK.  */
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -402,8 +370,8 @@ md_atof (type, litP, sizeP)
 
 const char *md_shortopts = "";
 
-struct option md_longopts[] = {
-
+struct option md_longopts[] =
+{
 #define OPTION_LITTLE (OPTION_MD_BASE)
 #define OPTION_BIG    (OPTION_LITTLE + 1)
 
@@ -414,9 +382,7 @@ struct option md_longopts[] = {
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 {
   switch (c)
     {
@@ -433,8 +399,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 PJ options:\n\
@@ -445,10 +410,7 @@ PJ options:\n\
 /* Apply a fixup to the object file.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT * valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
   long val = *valP;
@@ -544,10 +506,7 @@ md_apply_fix3 (fixP, valP, seg)
    executable section into big endian order.  */
 
 void
-md_number_to_chars (ptr, use, nbytes)
-     char *ptr;
-     valueT use;
-     int nbytes;
+md_number_to_chars (char *ptr, valueT use, int nbytes)
 {
   if (target_big_endian || now_seg->flags & SEC_CODE)
     number_to_chars_bigendian (ptr, use, nbytes);
@@ -559,15 +518,13 @@ md_number_to_chars (ptr, use, nbytes)
    format.  */
 
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *rel;
   bfd_reloc_code_real_type r_type;
 
-  rel = (arelent *) xmalloc (sizeof (arelent));
-  rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
diff --git a/gas/config/tc-pj.h b/gas/config/tc-pj.h
index 7d0a07d43de2..8ca8f5f886f8 100644
--- a/gas/config/tc-pj.h
+++ b/gas/config/tc-pj.h
@@ -1,5 +1,5 @@
 /* This file is tc-pj.h
-   Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    Contributed by Steve Chamberlain of Transmeta, sac@pobox.com
 
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* Contributed by Steve Chamberlain, of Transmeta. sac@pobox.com.  */
 
@@ -31,8 +31,8 @@
    ? "Pico Java GAS Big Endian"           				\
    : "Pico Java GAS Little Endian")
 
-void pj_cons_fix_new_pj PARAMS ((struct frag *, int, int, expressionS *));
-arelent *tc_gen_reloc PARAMS((asection *, struct fix *));
+void pj_cons_fix_new_pj (struct frag *, int, int, expressionS *);
+arelent *tc_gen_reloc (asection *, struct fix *);
 
 #define md_section_align(SEGMENT, SIZE)     (SIZE)
 #define md_convert_frag(B, S, F)            (as_fatal (_("convert_frag\n")), 0)
@@ -52,9 +52,9 @@ arelent *tc_gen_reloc PARAMS((asection *, struct fix *));
    visible symbols can be overridden.  */
 #define EXTERN_FORCE_RELOC 0
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_fix_adjustable(FIX) 					\
-          (! ((FIX)->fx_r_type == BFD_RELOC_VTABLE_INHERIT         	\
+          (! ((FIX)->fx_r_type == BFD_RELOC_VTABLE_INHERIT     	\
 	   || (FIX)->fx_r_type == BFD_RELOC_VTABLE_ENTRY))
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 66366a57d23c..d5bdb9e643ea 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -1,6 +1,6 @@
 /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000)
    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004 Free Software Foundation, Inc.
+   2004, 2005 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -184,8 +184,10 @@ const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "dD";
 
 /* '+' and '-' can be used as postfix predicate predictors for conditional
-   branches.  So they need to be accepted as symbol characters.  */
-const char ppc_symbol_chars[] = "+-";
+   branches.  So they need to be accepted as symbol characters.
+   Also, anything that can start an operand needs to be mentioned here,
+   to stop the input scrubber eating whitespace.  */
+const char ppc_symbol_chars[] = "+-%[";
 
 /* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
 int ppc_cie_data_alignment;
@@ -858,6 +860,9 @@ parse_cpu (const char *arg)
 	   || strcmp (arg, "7455") == 0)
     ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
 	       | PPC_OPCODE_ALTIVEC | PPC_OPCODE_32);
+  else if (strcmp (arg, "e300") == 0)
+    ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32
+	       | PPC_OPCODE_E300);
   else if (strcmp (arg, "altivec") == 0)
     {
       if (ppc_cpu == 0)
@@ -906,6 +911,12 @@ parse_cpu (const char *arg)
       ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
 		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4);
     }
+  else if (strcmp (arg, "power5") == 0)
+    {
+      ppc_cpu = (PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC
+		 | PPC_OPCODE_64 | PPC_OPCODE_POWER4
+		 | PPC_OPCODE_POWER5);
+    }
   /* -mcom means assemble for the common intersection between Power
      and PowerPC.  At present, we just allow the union, rather
      than the intersection.  */
@@ -1100,10 +1111,12 @@ PowerPC options:\n\
 -mbooke64		generate code for 64-bit PowerPC BookE\n\
 -mbooke, mbooke32	generate code for 32-bit PowerPC BookE\n\
 -mpower4		generate code for Power4 architecture\n\
+-mpower5		generate code for Power5 architecture\n\
 -mcom			generate code Power/PowerPC common instructions\n\
 -many			generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
 -maltivec		generate code for AltiVec\n\
+-me300			generate code for PowerPC e300 family\n\
 -me500, -me500x2	generate code for Motorola e500 core complex\n\
 -mspe			generate code for Motorola SPE instructions\n\
 -mregnames		Allow symbolic names for registers\n\
@@ -1144,19 +1157,15 @@ ppc_set_cpu ()
       else if (strcmp (default_cpu, "rs6000") == 0)
 	ppc_cpu |= PPC_OPCODE_POWER | PPC_OPCODE_32;
       else if (strncmp (default_cpu, "powerpc", 7) == 0)
-	{
-	  if (default_cpu[7] == '6' && default_cpu[8] == '4')
-	    ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_64;
-	  else
-	    ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
-	}
+	ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_CLASSIC | PPC_OPCODE_32;
       else
 	as_fatal (_("Unknown default cpu = %s, os = %s"),
 		  default_cpu, default_os);
     }
 }
 
-/* Figure out the BFD architecture to use.  */
+/* Figure out the BFD architecture to use.  This function and ppc_mach
+   are called well before md_begin, when the output file is opened.  */
 
 enum bfd_architecture
 ppc_arch ()
@@ -1208,9 +1217,13 @@ ppc_target_format ()
 #endif
 #endif
 #ifdef OBJ_ELF
+# ifdef TE_VXWORKS
+  return "elf32-powerpc-vxworks";
+# else
   return (target_big_endian
 	  ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc")
 	  : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle"));
+# endif
 #endif
 }
 
@@ -1254,7 +1267,10 @@ ppc_setup_opcodes (void)
 	      || (ppc_cpu & PPC_OPCODE_BOOKE) == 0)
 	  && ((op->flags & (PPC_OPCODE_POWER4 | PPC_OPCODE_NOPOWER4)) == 0
 	      || ((op->flags & PPC_OPCODE_POWER4)
-		  == (ppc_cpu & PPC_OPCODE_POWER4))))
+		  == (ppc_cpu & PPC_OPCODE_POWER4)))
+	  && ((op->flags & PPC_OPCODE_POWER5) == 0
+	      || ((op->flags & PPC_OPCODE_POWER5)
+		  == (ppc_cpu & PPC_OPCODE_POWER5))))
 	{
 	  const char *retval;
 
@@ -1457,14 +1473,7 @@ ppc_insert_operand (insn, operand, val, file, line)
 	test = val;
 
       if (test < (offsetT) min || test > (offsetT) max)
-	{
-	  const char *err =
-	    _("operand out of range (%s not between %ld and %ld)");
-	  char buf[100];
-
-	  sprint_value (buf, test);
-	  as_bad_where (file, line, err, buf, min, max);
-	}
+	as_bad_value_out_of_range (_("operand"), test, (offsetT) min, (offsetT) max, file, line);
     }
 
   if (operand->insert)
@@ -1898,6 +1907,7 @@ void
 ppc_frob_file_before_adjust ()
 {
   symbolS *symp;
+  asection *toc;
 
   if (!ppc_obj64)
     return;
@@ -1921,15 +1931,19 @@ ppc_frob_file_before_adjust ()
       dotname = xmalloc (len + 1);
       dotname[0] = '.';
       memcpy (dotname + 1, name, len);
-      dotsym = symbol_find (dotname);
+      dotsym = symbol_find_noref (dotname, 1);
       free (dotname);
       if (dotsym != NULL && (symbol_used_p (dotsym)
 			     || symbol_used_in_reloc_p (dotsym)))
-	{
-	  symbol_mark_used (symp);
-	}
+	symbol_mark_used (symp);
+
     }
 
+  toc = bfd_get_section_by_name (stdoutput, ".toc");
+  if (toc != NULL
+      && bfd_section_size (stdoutput, toc) > 0x10000)
+    as_warn (_("TOC section size exceeds 64k"));
+
   /* Don't emit .TOC. symbol.  */
   symp = symbol_find (".TOC.");
   if (symp != NULL)
@@ -2098,6 +2112,7 @@ md_assemble (str)
   struct ppc_fixup fixups[MAX_INSN_FIXUPS];
   int fc;
   char *f;
+  int addr_mod;
   int i;
 #ifdef OBJ_ELF
   bfd_reloc_code_real_type reloc;
@@ -2625,6 +2640,11 @@ md_assemble (str)
 
   /* Write out the instruction.  */
   f = frag_more (4);
+  addr_mod = frag_now_fix () & 3;
+  if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+    as_bad (_("instruction address is not a multiple of 4"));
+  frag_now->insn_addr = addr_mod;
+  frag_now->has_code = 1;
   md_number_to_chars (f, insn, 4);
 
 #ifdef OBJ_ELF
@@ -2636,7 +2656,7 @@ md_assemble (str)
      BFD_RELOC_UNUSED plus the operand index.  This lets us easily
      handle fixups for any operand type, although that is admittedly
      not a very exciting feature.  We pick a BFD reloc type in
-     md_apply_fix3.  */
+     md_apply_fix.  */
   for (i = 0; i < fc; i++)
     {
       const struct powerpc_operand *operand;
@@ -4396,6 +4416,7 @@ ppc_pe_comm (lcomm)
     {
       S_SET_VALUE (symbolP, (valueT) temp);
       S_SET_EXTERNAL (symbolP);
+      S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
     }
 
   demand_empty_rest_of_line ();
@@ -4820,6 +4841,10 @@ ppc_frob_label (sym)
 		     &symbol_rootP, &symbol_lastP);
       symbol_get_tc (ppc_current_csect)->within = sym;
     }
+
+#ifdef OBJ_ELF
+  dwarf2_emit_label (sym);
+#endif
 }
 
 /* This variable is set by ppc_frob_symbol if any absolute symbols are
@@ -4844,7 +4869,7 @@ ppc_frob_symbol (sym)
      table.  */
   if (! symbol_used_in_reloc_p (sym)
       && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0
-	  || (! S_IS_EXTERNAL (sym)
+	  || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
 	      && ! symbol_get_tc (sym)->output
 	      && S_GET_STORAGE_CLASS (sym) != C_FILE)))
     return 1;
@@ -4910,7 +4935,7 @@ ppc_frob_symbol (sym)
 	}
     }
 
-  if (! S_IS_EXTERNAL (sym)
+  if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym))
       && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0
       && S_GET_STORAGE_CLASS (sym) != C_FILE
       && S_GET_STORAGE_CLASS (sym) != C_FCN
@@ -5455,6 +5480,7 @@ ppc_force_relocation (fix)
     case BFD_RELOC_PPC_B16_BRNTAKEN:
     case BFD_RELOC_PPC_BA16_BRTAKEN:
     case BFD_RELOC_PPC_BA16_BRNTAKEN:
+    case BFD_RELOC_24_PLT_PCREL:
     case BFD_RELOC_PPC64_TOC:
       return 1;
     default:
@@ -5480,12 +5506,7 @@ ppc_fix_adjustable (fix)
 	  && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
 	  && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY
 	  && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS
-	       && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA)
-	  && (fix->fx_pcrel
-	      || (fix->fx_subsy != NULL
-		  && (S_GET_SEGMENT (fix->fx_subsy)
-		      == S_GET_SEGMENT (fix->fx_addsy)))
-	      || S_IS_LOCAL (fix->fx_addsy)));
+	       && fix->fx_r_type <= BFD_RELOC_PPC64_DTPREL16_HIGHESTA));
 }
 #endif
 
@@ -5499,7 +5520,7 @@ ppc_fix_adjustable (fix)
    fixup.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS *fixP;
      valueT * valP;
      segT seg ATTRIBUTE_UNUSED;
@@ -5517,11 +5538,11 @@ md_apply_fix3 (fixP, valP, seg)
     fixP->fx_done = 1;
 #else
   /* FIXME FIXME FIXME: The value we are passed in *valP includes
-     the symbol values.  Since we are using BFD_ASSEMBLER, if we are
-     doing this relocation the code in write.c is going to call
-     bfd_install_relocation, which is also going to use the symbol
-     value.  That means that if the reloc is fully resolved we want to
-     use *valP since bfd_install_relocation is not being used.
+     the symbol values.  If we are doing this relocation the code in
+     write.c is going to call bfd_install_relocation, which is also
+     going to use the symbol value.  That means that if the reloc is
+     fully resolved we want to use *valP since bfd_install_relocation is
+     not being used.
      However, if the reloc is not fully resolved we do not want to use
      *valP, and must use fx_offset instead.  However, if the reloc
      is PC relative, we do want to use *valP since it includes the
@@ -5707,8 +5728,6 @@ md_apply_fix3 (fixP, valP, seg)
 			      value, 8);
 	  break;
 
-	case BFD_RELOC_LO16:
-	case BFD_RELOC_16:
 	case BFD_RELOC_GPREL16:
 	case BFD_RELOC_16_GOT_PCREL:
 	case BFD_RELOC_16_GOTOFF:
@@ -5754,19 +5773,45 @@ md_apply_fix3 (fixP, valP, seg)
 			      value, 2);
 	  break;
 
+	case BFD_RELOC_16:
+	  if (fixP->fx_pcrel)
+	    fixP->fx_r_type = BFD_RELOC_16_PCREL;
+	  /* fall through */
+
+	case BFD_RELOC_16_PCREL:
+	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+			      value, 2);
+	  break;
+
+	case BFD_RELOC_LO16:
+	  if (fixP->fx_pcrel)
+	    fixP->fx_r_type = BFD_RELOC_LO16_PCREL;
+	  /* fall through */
+
+	case BFD_RELOC_LO16_PCREL:
+	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
+			      value, 2);
+	  break;
+
 	  /* This case happens when you write, for example,
 	     lis %r3,(L1-L2)@ha
 	     where L1 and L2 are defined later.  */
 	case BFD_RELOC_HI16:
 	  if (fixP->fx_pcrel)
-	    abort ();
+	    fixP->fx_r_type = BFD_RELOC_HI16_PCREL;
+	  /* fall through */
+
+	case BFD_RELOC_HI16_PCREL:
 	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
 			      PPC_HI (value), 2);
 	  break;
 
 	case BFD_RELOC_HI16_S:
 	  if (fixP->fx_pcrel)
-	    abort ();
+	    fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL;
+	  /* fall through */
+
+	case BFD_RELOC_HI16_S_PCREL:
 	  md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where,
 			      PPC_HA (value), 2);
 	  break;
@@ -5814,7 +5859,7 @@ md_apply_fix3 (fixP, valP, seg)
 	  if (fixP->fx_pcrel)
 	    abort ();
 	  {
-	    unsigned char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
+	    char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
 	    unsigned long val, mask;
 
 	    if (target_big_endian)
@@ -5841,6 +5886,8 @@ md_apply_fix3 (fixP, valP, seg)
 	  break;
 
 	case BFD_RELOC_PPC_TLS:
+	  break;
+
 	case BFD_RELOC_PPC_DTPMOD:
 	case BFD_RELOC_PPC_TPREL16:
 	case BFD_RELOC_PPC_TPREL16_LO:
@@ -5880,6 +5927,7 @@ md_apply_fix3 (fixP, valP, seg)
 	case BFD_RELOC_PPC64_DTPREL16_HIGHERA:
 	case BFD_RELOC_PPC64_DTPREL16_HIGHEST:
 	case BFD_RELOC_PPC64_DTPREL16_HIGHESTA:
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
 	  break;
 #endif
 	  /* Because SDA21 modifies the register field, the size is set to 4
@@ -5972,6 +6020,13 @@ md_apply_fix3 (fixP, valP, seg)
 
 #ifdef OBJ_ELF
   fixP->fx_addnumber = value;
+
+  /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately
+     from the section contents.  If we are going to be emitting a reloc
+     then the section contents are immaterial, so don't warn if they
+     happen to overflow.  Leave such warnings to ld.  */
+  if (!fixP->fx_done)
+    fixP->fx_no_overflow = 1;
 #else
   if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16)
     fixP->fx_addnumber = 0;
@@ -6033,7 +6088,7 @@ tc_ppc_regname_to_dw2regnum (const char *regname)
     {
       { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 },
       { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 },
-      { "cc", 68 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
+      { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 },
       { "spe_acc", 111 }, { "spefscr", 112 }
     };
 
diff --git a/gas/config/tc-ppc.h b/gas/config/tc-ppc.h
index 0844f84cefab..f7c2da619cbc 100644
--- a/gas/config/tc-ppc.h
+++ b/gas/config/tc-ppc.h
@@ -1,6 +1,6 @@
 /* tc-ppc.h -- Header file for tc-ppc.c.
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005 Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,24 +17,18 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_PPC
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
 
 /* Set the endianness we are using.  Default to big endian.  */
 #ifndef TARGET_BYTES_BIG_ENDIAN
 #define TARGET_BYTES_BIG_ENDIAN 1
 #endif
 
-#ifndef BFD_ASSEMBLER
- #error PowerPC support requires BFD_ASSEMBLER
-#endif
-
 /* If OBJ_COFF is defined, and TE_PE is not defined, we are assembling
    XCOFF for AIX or PowerMac.  If TE_PE is defined, we are assembling
    COFF for Windows NT.  */
@@ -90,7 +84,7 @@ extern char *ppc_target_format PARAMS ((void));
 		      - ((FRAGP)->fr_address + (FRAGP)->fr_fix));	\
       if (count != 0 && (count & 3) == 0)				\
 	{								\
-	  unsigned char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;	\
+	  char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;		\
 									\
 	  (FRAGP)->fr_var = 4;						\
 	  if (target_big_endian)					\
@@ -110,6 +104,11 @@ extern char *ppc_target_format PARAMS ((void));
 	}								\
     }
 
+#define md_frag_check(FRAGP) \
+  if ((FRAGP)->has_code							\
+      && (((FRAGP)->fr_address + (FRAGP)->insn_addr) & 3) != 0)		\
+    as_bad_where ((FRAGP)->fr_file, (FRAGP)->fr_line,			\
+		  _("instruction address is not a multiple of 4"));
 
 #ifdef TE_PE
 
@@ -229,7 +228,7 @@ extern const char *ppc_comment_chars;
 #define tc_fix_adjustable(FIX) ppc_fix_adjustable (FIX)
 extern int ppc_fix_adjustable PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_frob_file_before_adjust ppc_frob_file_before_adjust
@@ -246,7 +245,7 @@ extern int ppc_force_relocation PARAMS ((struct fix *));
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section(FIX, SEC)
 extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
 
-#define md_parse_name(name, exp, c) ppc_parse_name (name, exp)
+#define md_parse_name(name, exp, mode, c) ppc_parse_name (name, exp)
 extern int ppc_parse_name PARAMS ((const char *, struct expressionS *));
 
 #define md_operand(x)
diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c
index 4fafbec35fe4..56b5b2594f8f 100644
--- a/gas/config/tc-s390.c
+++ b/gas/config/tc-s390.c
@@ -1,5 +1,6 @@
 /* tc-s390.c -- Assemble for the S390
-   Copyright 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -312,8 +313,8 @@ static flagword s390_flags = 0;
 symbolS *GOT_symbol;		/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
 
 #ifndef WORKING_DOT_WORD
-const int md_short_jump_size = 4;
-const int md_long_jump_size = 4;
+int md_short_jump_size = 4;
+int md_long_jump_size = 4;
 #endif
 
 const char *md_shortopts = "A:m:kVQ:";
@@ -409,6 +410,8 @@ md_parse_option (c, arg)
 	    current_cpu = S390_OPCODE_Z900;
 	  else if (strcmp (arg + 5, "z990") == 0)
 	    current_cpu = S390_OPCODE_Z990;
+	  else if (strcmp (arg + 5, "z9-109") == 0)
+	    current_cpu = S390_OPCODE_Z9_109;
 	  else
 	    {
 	      as_bad (_("invalid switch -m%s"), arg);
@@ -601,21 +604,15 @@ s390_insert_operand (insn, operand, val, file, line)
       /* Check for underflow / overflow.  */
       if (uval < min || uval > max)
 	{
-	  const char *err =
-	    "operand out of range (%s not between %ld and %ld)";
-	  char buf[100];
-
 	  if (operand->flags & S390_OPERAND_LENGTH)
 	    {
 	      uval++;
 	      min++;
 	      max++;
 	    }
-	  sprint_value (buf, uval);
-	  if (file == (char *) NULL)
-	    as_bad (err, buf, (int) min, (int) max);
-	  else
-	    as_bad_where (file, line, err, buf, (int) min, (int) max);
+
+	  as_bad_value_out_of_range (_("operand"), uval, (offsetT) min, (offsetT) max, file, line);
+
 	  return;
 	}
     }
@@ -1358,8 +1355,19 @@ md_gather_operands (str, insn, opcode)
 	      /* If there is a next operand it must be separated by a comma.  */
 	      if (opindex_ptr[1] != '\0')
 		{
-		  if (*str++ != ',')
-		    as_bad (_("syntax error; expected ,"));
+		  if (*str != ',')
+		    {
+		      while (opindex_ptr[1] != '\0')
+			{
+			  operand = s390_operands + *(++opindex_ptr);
+			  if (operand->flags & S390_OPERAND_OPTIONAL)
+			    continue;
+			  as_bad (_("syntax error; expected ,"));
+			  break;
+			}
+		    }
+		  else
+		    str++;
 		}
 	    }
 	  else
@@ -1391,8 +1399,19 @@ md_gather_operands (str, insn, opcode)
 	  /* If there is a next operand it must be separated by a comma.  */
 	  if (opindex_ptr[1] != '\0')
 	    {
-	      if (*str++ != ',')
-		as_bad (_("syntax error; expected ,"));
+	      if (*str != ',')
+		{
+		  while (opindex_ptr[1] != '\0')
+		    {
+		      operand = s390_operands + *(++opindex_ptr);
+		      if (operand->flags & S390_OPERAND_OPTIONAL)
+			continue;
+		      as_bad (_("syntax error; expected ,"));
+		      break;
+		    }
+		}
+	      else
+		str++;
 	    }
 	}
       else
@@ -1410,8 +1429,19 @@ md_gather_operands (str, insn, opcode)
 	  /* If there is a next operand it must be separated by a comma.  */
 	  if (opindex_ptr[1] != '\0')
 	    {
-	      if (*str++ != ',')
-		as_bad (_("syntax error; expected ,"));
+	      if (*str != ',')
+		{
+		  while (opindex_ptr[1] != '\0')
+		    {
+		      operand = s390_operands + *(++opindex_ptr);
+		      if (operand->flags & S390_OPERAND_OPTIONAL)
+			continue;
+		      as_bad (_("syntax error; expected ,"));
+		      break;
+		    }
+		}
+	      else
+		str++;
 	    }
 	}
     }
@@ -1454,7 +1484,7 @@ md_gather_operands (str, insn, opcode)
      BFD_RELOC_UNUSED plus the operand index.  This lets us easily
      handle fixups for any operand type, although that is admittedly
      not a very exciting feature.  We pick a BFD reloc type in
-     md_apply_fix3.  */
+     md_apply_fix.  */
   for (i = 0; i < fc; i++)
     {
 
@@ -1602,15 +1632,12 @@ s390_insn (ignore)
   if (exp.X_op == O_constant)
     {
       if (   (   opformat->oplen == 6
-	      && exp.X_add_number >= 0
 	      && (addressT) exp.X_add_number < (1ULL << 48))
 	  || (   opformat->oplen == 4
-	      && exp.X_add_number >= 0
 	      && (addressT) exp.X_add_number < (1ULL << 32))
 	  || (   opformat->oplen == 2
-	      && exp.X_add_number >= 0
 	      && (addressT) exp.X_add_number < (1ULL << 16)))
-	md_number_to_chars (insn, exp.X_add_number, opformat->oplen);
+	md_number_to_chars ((char *) insn, exp.X_add_number, opformat->oplen);
       else
 	as_bad (_("Invalid .insn format\n"));
     }
@@ -1620,9 +1647,9 @@ s390_insn (ignore)
 	  && opformat->oplen == 6
 	  && generic_bignum[3] == 0)
 	{
-	  md_number_to_chars (insn, generic_bignum[2], 2);
-	  md_number_to_chars (&insn[2], generic_bignum[1], 2);
-	  md_number_to_chars (&insn[4], generic_bignum[0], 2);
+	  md_number_to_chars ((char *) insn, generic_bignum[2], 2);
+	  md_number_to_chars ((char *) &insn[2], generic_bignum[1], 2);
+	  md_number_to_chars ((char *) &insn[4], generic_bignum[0], 2);
 	}
       else
 	as_bad (_("Invalid .insn format\n"));
@@ -1965,7 +1992,7 @@ tc_s390_force_relocation (fixp)
    fixup.  */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS *fixP;
      valueT *valP;
      segT seg ATTRIBUTE_UNUSED;
@@ -2000,8 +2027,8 @@ md_apply_fix3 (fixP, valP, seg)
       if (fixP->fx_done)
 	{
 	  /* Insert the fully resolved operand value.  */
-	  s390_insert_operand (where, operand, (offsetT) value,
-			       fixP->fx_file, fixP->fx_line);
+	  s390_insert_operand ((unsigned char *) where, operand,
+			       (offsetT) value, fixP->fx_file, fixP->fx_line);
 	  return;
 	}
 
@@ -2223,10 +2250,12 @@ md_apply_fix3 (fixP, valP, seg)
 	case BFD_RELOC_390_TLS_DTPMOD:
 	case BFD_RELOC_390_TLS_DTPOFF:
 	case BFD_RELOC_390_TLS_TPOFF:
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
 	  /* Fully resolved at link time.  */
 	  break;
 	case BFD_RELOC_390_TLS_IEENT:
 	  /* Fully resolved at link time.  */
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
 	  value += 2;
 	  break;
 
diff --git a/gas/config/tc-s390.h b/gas/config/tc-s390.h
index fe55e15c89de..dbecfef3a553 100644
--- a/gas/config/tc-s390.h
+++ b/gas/config/tc-s390.h
@@ -1,5 +1,6 @@
 /* tc-s390.h -- Header file for tc-s390.c.
-   Copyright 2000, 2001, 2002, 2004 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
    Written by Martin Schwidefsky (schwidefsky@de.ibm.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -16,18 +17,12 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_S390
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
-
-#ifndef BFD_ASSEMBLER
- #error S390 support requires BFD_ASSEMBLER
-#endif
 
 #define TC_FORCE_RELOCATION(FIX) tc_s390_force_relocation(FIX)
 extern int tc_s390_force_relocation PARAMS ((struct fix *));
@@ -39,7 +34,7 @@ extern int tc_s390_force_relocation PARAMS ((struct fix *));
 #define tc_fix_adjustable(X)  tc_s390_fix_adjustable(X)
 extern int tc_s390_fix_adjustable PARAMS ((struct fix *));
 
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* The target BFD architecture.  */
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index 424aeb7b57b3..acf62aef21d6 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -1,6 +1,6 @@
 /* tc-sh.c -- Assemble code for the Renesas / SuperH SH
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003, 2004  Free Software Foundation, Inc.
+   2003, 2004, 2005  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* Written By Steve Chamberlain <sac@cygnus.com>  */
 
@@ -124,8 +124,6 @@ const pseudo_typeS md_pseudo_table[] =
   {0, 0, 0}
 };
 
-/*int md_reloc_size; */
-
 int sh_relax;		/* set if -relax seen */
 
 /* Whether -small was seen.  */
@@ -136,13 +134,17 @@ int sh_small;
 
 static int dont_adjust_reloc_32;
 
-/* preset architecture set, if given; zero otherwise.  */
+/* Flag to indicate that '$' is allowed as a register prefix.  */
+
+static int allow_dollar_register_prefix;
+
+/* Preset architecture set, if given; zero otherwise.  */
 
-static int preset_target_arch;
+static unsigned int preset_target_arch;
 
 /* The bit mask of architectures that could
    accommodate the insns seen so far.  */
-static int valid_arch;
+static unsigned int valid_arch;
 
 const char EXP_CHARS[] = "eE";
 
@@ -836,10 +838,10 @@ md_begin (void)
 {
   const sh_opcode_info *opcode;
   char *prev_name = "";
-  int target_arch;
+  unsigned int target_arch;
 
   target_arch
-    = preset_target_arch ? preset_target_arch : arch_sh1_up & ~arch_sh_dsp_up;
+    = preset_target_arch ? preset_target_arch : arch_sh_up & ~arch_sh_has_dsp;
   valid_arch = target_arch;
 
 #ifdef HAVE_SH64
@@ -853,7 +855,7 @@ md_begin (void)
     {
       if (strcmp (prev_name, opcode->name) != 0)
 	{
-	  if (! (opcode->arch & target_arch))
+	  if (!SH_MERGE_ARCH_SET_VALID (opcode->arch, target_arch))
 	    continue;
 	  prev_name = opcode->name;
 	  hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
@@ -871,8 +873,8 @@ static int reg_b;
 
 /* Try to parse a reg name.  Return the number of chars consumed.  */
 
-static int
-parse_reg (char *src, int *mode, int *reg)
+static unsigned int
+parse_reg_without_prefix (char *src, int *mode, int *reg)
 {
   char l0 = TOLOWER (src[0]);
   char l1 = l0 ? TOLOWER (src[1]) : 0;
@@ -1098,6 +1100,12 @@ parse_reg (char *src, int *mode, int *reg)
       return 3;
     }
 
+  if (l0 == 't' && l1 == 'b' && TOLOWER (src[2]) == 'r'
+      && ! IDENT_CHAR ((unsigned char) src[3]))
+    {
+      *mode = A_TBR;
+      return 3;
+    }
   if (l0 == 'm' && l1 == 'a' && TOLOWER (src[2]) == 'c'
       && ! IDENT_CHAR ((unsigned char) src[4]))
     {
@@ -1221,6 +1229,36 @@ parse_reg (char *src, int *mode, int *reg)
   return 0;
 }
 
+/* Like parse_reg_without_prefix, but this version supports
+   $-prefixed register names if enabled by the user.  */
+
+static unsigned int
+parse_reg (char *src, int *mode, int *reg)
+{
+  unsigned int prefix;
+  unsigned int consumed;
+
+  if (src[0] == '$')
+    {
+      if (allow_dollar_register_prefix)
+	{
+	  src ++;
+	  prefix = 1;
+	}
+      else
+	return 0;
+    }
+  else
+    prefix = 0;
+  
+  consumed = parse_reg_without_prefix (src, mode, reg);
+
+  if (consumed == 0)
+    return 0;
+
+  return consumed + prefix;
+}
+
 static char *
 parse_exp (char *s, sh_operand_info *op)
 {
@@ -1268,7 +1306,15 @@ parse_at (char *src, sh_operand_info *op)
   int len;
   int mode;
   src++;
-  if (src[0] == '-')
+  if (src[0] == '@')
+    {
+      src = parse_at (src, op);
+      if (op->type == A_DISP_TBR)
+	op->type = A_DISP2_TBR;
+      else
+	as_bad (_("illegal double indirection"));
+    }
+  else if (src[0] == '-')
     {
       /* Must be predecrement.  */
       src++;
@@ -1341,6 +1387,10 @@ parse_at (char *src, sh_operand_info *op)
 		{
 		  op->type = A_DISP_GBR;
 		}
+	      else if (mode == A_TBR)
+		{
+		  op->type = A_DISP_TBR;
+		}
 	      else if (mode == A_PC)
 		{
 		  /* We want @(expr, pc) to uniformly address . + expr,
@@ -1542,6 +1592,36 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 	  sh_operand_info *user = operands + n;
 	  sh_arg_type arg = this_try->arg[n];
 
+	  if (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh2a_nofpu_up)
+	      && (   arg == A_DISP_REG_M
+		  || arg == A_DISP_REG_N))
+	    {
+	      /* Check a few key IMM* fields for overflow.  */
+	      int opf;
+	      long val = user->immediate.X_add_number;
+
+	      for (opf = 0; opf < 4; opf ++)
+		switch (this_try->nibbles[opf])
+		  {
+		  case IMM0_4:
+		  case IMM1_4:
+		    if (val < 0 || val > 15)
+		      goto fail;
+		    break;
+		  case IMM0_4BY2:
+		  case IMM1_4BY2:
+		    if (val < 0 || val > 15 * 2)
+		      goto fail;
+		    break;
+		  case IMM0_4BY4:
+		  case IMM1_4BY4:
+		    if (val < 0 || val > 15 * 4)
+		      goto fail;
+		    break;
+		  default:
+		    break;
+		  }
+	    }
 	  switch (arg)
 	    {
 	    case A_DISP_PC:
@@ -1552,6 +1632,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 	    case A_BDISP12:
 	    case A_BDISP8:
 	    case A_DISP_GBR:
+	    case A_DISP2_TBR:
 	    case A_MACH:
 	    case A_PR:
 	    case A_MACL:
@@ -1596,6 +1677,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 	      reg_n = user->reg;
 	      break;
 	    case A_GBR:
+	    case A_TBR:
 	    case A_SR:
 	    case A_VBR:
 	    case A_DSR:
@@ -1616,6 +1698,22 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 	      reg_b = user->reg;
 	      break;
 
+	    case A_INC_R15:
+	      if (user->type != A_INC_N)
+		goto fail;
+	      if (user->reg != 15)
+		goto fail;
+	      reg_n = user->reg;
+	      break;
+
+	    case A_DEC_R15:
+	      if (user->type != A_DEC_N)
+		goto fail;
+	      if (user->reg != 15)
+		goto fail;
+	      reg_n = user->reg;
+	      break;
+
 	    case A_REG_M:
 	    case A_INC_M:
 	    case A_DEC_M:
@@ -1636,7 +1734,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1644,7 +1742,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1652,7 +1750,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AS_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1660,7 +1758,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1668,7 +1766,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1676,7 +1774,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AX_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1684,7 +1782,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1693,7 +1791,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1702,7 +1800,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AXY_PMOD_N:
 	      if (user->type != AX_PMOD_N)
 		goto fail;
@@ -1711,7 +1809,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_INC_N:
 	      if (user->type != A_INC_N)
 		goto fail;
@@ -1719,7 +1817,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1727,7 +1825,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AY_PMOD_N:
 	      if (user->type != AY_PMOD_N)
 		goto fail;
@@ -1744,7 +1842,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AYX_IND_N:
 	      if (user->type != A_IND_N)
 		goto fail;
@@ -1753,7 +1851,7 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 		goto fail;
 	      reg_n = user->reg;
 	      break;
-	      
+
 	    case AYX_PMOD_N:
 	      if (user->type != AY_PMOD_N)
 		goto fail;
@@ -2018,9 +2116,9 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
 	      goto fail;
 	    }
 	}
-      if ( !(valid_arch & this_try->arch))
+      if ( !SH_MERGE_ARCH_SET_VALID (valid_arch, this_try->arch))
 	goto fail;
-      valid_arch &= this_try->arch;
+      valid_arch = SH_MERGE_ARCH_SET (valid_arch, this_try->arch);
       return this_try;
     fail:
       ;
@@ -2041,6 +2139,16 @@ insert (char *where, int how, int pcrel, sh_operand_info *op)
 }
 
 static void
+insert4 (char * where, int how, int pcrel, sh_operand_info * op)
+{
+  fix_new_exp (frag_now,
+	       where - frag_now->fr_literal,
+	       4,
+	       & op->immediate,
+	       pcrel,
+	       how);
+}
+static void
 build_relax (sh_opcode_info *opcode, sh_operand_info *op)
 {
   int high_byte = target_big_endian ? 0 : 1;
@@ -2126,16 +2234,31 @@ static unsigned int
 build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
 {
   int index;
-  char nbuf[4];
-  char *output = frag_more (2);
+  char nbuf[8];
+  char *output;
   unsigned int size = 2;
   int low_byte = target_big_endian ? 1 : 0;
+  int max_index = 4;
+
   nbuf[0] = 0;
   nbuf[1] = 0;
   nbuf[2] = 0;
   nbuf[3] = 0;
+  nbuf[4] = 0;
+  nbuf[5] = 0;
+  nbuf[6] = 0;
+  nbuf[7] = 0;
+
+  if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
+    {
+      output = frag_more (4);
+      size = 4;
+      max_index = 8;
+    }
+  else
+    output = frag_more (2);
 
-  for (index = 0; index < 4; index++)
+  for (index = 0; index < max_index; index++)
     {
       sh_nibble_type i = opcode->nibbles[index];
       if (i < 16)
@@ -2167,6 +2290,48 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
 	    case REG_N_B01:
 	      nbuf[index] = reg_n | 0x01;
 	      break;
+	    case IMM0_3s:
+	      nbuf[index] |= 0x08;
+	    case IMM0_3c:
+	      insert (output + low_byte, BFD_RELOC_SH_IMM3, 0, operand);
+	      break;
+	    case IMM0_3Us:
+	      nbuf[index] |= 0x80;
+	    case IMM0_3Uc:
+	      insert (output + low_byte, BFD_RELOC_SH_IMM3U, 0, operand);
+	      break;
+	    case DISP0_12:
+	      insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand);
+	      break;
+	    case DISP0_12BY2:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand);
+	      break;
+	    case DISP0_12BY4:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand);
+	      break;
+	    case DISP0_12BY8:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand);
+	      break;
+	    case DISP1_12:
+	      insert (output + 2, BFD_RELOC_SH_DISP12, 0, operand+1);
+	      break;
+	    case DISP1_12BY2:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY2, 0, operand+1);
+	      break;
+	    case DISP1_12BY4:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY4, 0, operand+1);
+	      break;
+	    case DISP1_12BY8:
+	      insert (output + 2, BFD_RELOC_SH_DISP12BY8, 0, operand+1);
+	      break;
+	    case IMM0_20_4:
+	      break;
+	    case IMM0_20:
+	      insert4 (output, BFD_RELOC_SH_DISP20, 0, operand);
+	      break;
+	    case IMM0_20BY8:
+	      insert4 (output, BFD_RELOC_SH_DISP20BY8, 0, operand);
+	      break;
 	    case IMM0_4BY4:
 	      insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand);
 	      break;
@@ -2231,6 +2396,19 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
       output[0] = (nbuf[0] << 4) | (nbuf[1]);
       output[1] = (nbuf[2] << 4) | (nbuf[3]);
     }
+  if (SH_MERGE_ARCH_SET (opcode->arch, arch_op32))
+    {
+      if (!target_big_endian)
+	{
+	  output[3] = (nbuf[4] << 4) | (nbuf[5]);
+	  output[2] = (nbuf[6] << 4) | (nbuf[7]);
+	}
+      else
+	{
+	  output[2] = (nbuf[4] << 4) | (nbuf[5]);
+	  output[3] = (nbuf[6] << 4) | (nbuf[7]);
+	}
+    }
   return size;
 }
 
@@ -2254,7 +2432,7 @@ find_cooked_opcode (char **str_p)
      The pre-processor will eliminate whitespace in front of
      any '@' after the first argument; we may be called from
      assemble_ppi, so the opcode might be terminated by an '@'.  */
-  for (op_start = op_end = (unsigned char *) (str);
+  for (op_start = op_end = (unsigned char *) str;
        *op_end
        && nlen < 20
        && !is_end_of_line[*op_end] && *op_end != ' ' && *op_end != '@';
@@ -2273,7 +2451,7 @@ find_cooked_opcode (char **str_p)
     }
 
   name[nlen] = 0;
-  *str_p = op_end;
+  *str_p = (char *) op_end;
 
   if (nlen == 0)
     as_bad (_("can't find opcode "));
@@ -2486,9 +2664,9 @@ assemble_ppi (char *op_end, sh_opcode_info *opcode)
 		field_b -= 0x8100;
 	      /* pclr Dz pmuls Se,Sf,Dg */
 	      else if ((field_b & 0xff00) == 0x8d00
-		       && (valid_arch & arch_sh4al_dsp_up))
+		       && (SH_MERGE_ARCH_SET_VALID (valid_arch, arch_sh4al_dsp_up)))
 		{
-		  valid_arch &= arch_sh4al_dsp_up;
+		  valid_arch = SH_MERGE_ARCH_SET (valid_arch, arch_sh4al_dsp_up);
 		  field_b -= 0x8cf0;
 		}
 	      else
@@ -2588,10 +2766,11 @@ assemble_ppi (char *op_end, sh_opcode_info *opcode)
 void
 md_assemble (char *str)
 {
-  unsigned char *op_end;
+  char *op_end;
   sh_operand_info operand[3];
   sh_opcode_info *opcode;
   unsigned int size = 0;
+  char *initial_str = str;
 
 #ifdef HAVE_SH64
   if (sh64_isa_mode == sh64_isa_shmedia)
@@ -2618,7 +2797,46 @@ md_assemble (char *str)
 
   if (opcode == NULL)
     {
-      as_bad (_("unknown opcode"));
+      /* The opcode is not in the hash table.
+	 This means we definately have an assembly failure,
+	 but the instruction may be valid in another CPU variant.
+	 In this case emit something better than 'unknown opcode'.
+	 Search the full table in sh-opc.h to check. */
+
+      char *name = initial_str;
+      int name_length = 0;
+      const sh_opcode_info *op;
+      int found = 0;
+
+      /* identify opcode in string */
+      while (ISSPACE (*name))
+	{
+	  name++;
+	}
+      while (!ISSPACE (name[name_length]))
+	{
+	  name_length++;
+	}
+
+      /* search for opcode in full list */
+      for (op = sh_table; op->name; op++)
+	{
+	  if (strncasecmp (op->name, name, name_length) == 0
+	      && op->name[name_length] == '\0')
+	    {
+	      found = 1;
+	      break;
+	    }
+	}
+
+      if ( found )
+	{
+	  as_bad (_("opcode not valid for this cpu variant"));
+	}
+      else
+	{
+	  as_bad (_("unknown opcode"));
+	}
       return;
     }
 
@@ -2643,8 +2861,8 @@ md_assemble (char *str)
 	{
 	  /* Since we skip get_specific here, we have to check & update
 	     valid_arch now.  */
-	  if (valid_arch & opcode->arch)
-	    valid_arch &= opcode->arch;
+	  if (SH_MERGE_ARCH_SET_VALID (valid_arch, opcode->arch))
+	    valid_arch = SH_MERGE_ARCH_SET (valid_arch, opcode->arch);
 	  else
 	    as_bad (_("Delayed branches not available on SH1"));
 	  parse_exp (op_end + 1, &operand[0]);
@@ -2685,16 +2903,14 @@ md_assemble (char *str)
 	}
     }
 
-#ifdef BFD_ASSEMBLER
   dwarf2_emit_insn (size);
-#endif
 }
 
 /* This routine is called each time a label definition is seen.  It
    emits a BFD_RELOC_SH_LABEL reloc if necessary.  */
 
 void
-sh_frob_label (void)
+sh_frob_label (symbolS *sym)
 {
   static fragS *last_label_frag;
   static int last_label_offset;
@@ -2713,6 +2929,8 @@ sh_frob_label (void)
 	  last_label_offset = offset;
 	}
     }
+
+  dwarf2_emit_label (sym);
 }
 
 /* This routine is called when the assembler is about to output some
@@ -2736,24 +2954,6 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
   return 0;
 }
 
-#ifdef OBJ_COFF
-#ifndef BFD_ASSEMBLER
-
-void
-tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_crawl_symbol_chain \n"));
-}
-
-void
-tc_headers_hook (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_headers_hook \n"));
-}
-
-#endif
-#endif
-
 /* Various routines to kill one day.  */
 /* Equal to MAX_PRECISION in atof-ieee.c.  */
 #define MAX_LITTLENUMS 6
@@ -2839,31 +3039,39 @@ s_uses (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+enum options
+{
+  OPTION_RELAX = OPTION_MD_BASE,
+  OPTION_BIG,
+  OPTION_LITTLE,
+  OPTION_SMALL,
+  OPTION_DSP,
+  OPTION_ISA,
+  OPTION_RENESAS,
+  OPTION_ALLOW_REG_PREFIX,
+#ifdef HAVE_SH64
+  OPTION_ABI,
+  OPTION_NO_MIX,
+  OPTION_SHCOMPACT_CONST_CRANGE,
+  OPTION_NO_EXPAND,
+  OPTION_PT32,
+#endif
+  OPTION_DUMMY  /* Not used.  This is just here to make it easy to add and subtract options from this enum.  */
+};
+
 const char *md_shortopts = "";
 struct option md_longopts[] =
 {
-#define OPTION_RELAX  (OPTION_MD_BASE)
-#define OPTION_BIG (OPTION_MD_BASE + 1)
-#define OPTION_LITTLE (OPTION_BIG + 1)
-#define OPTION_SMALL (OPTION_LITTLE + 1)
-#define OPTION_DSP (OPTION_SMALL + 1)
-#define OPTION_ISA                    (OPTION_DSP + 1)
-#define OPTION_RENESAS (OPTION_ISA + 1)
-
   {"relax", no_argument, NULL, OPTION_RELAX},
   {"big", no_argument, NULL, OPTION_BIG},
   {"little", no_argument, NULL, OPTION_LITTLE},
   {"small", no_argument, NULL, OPTION_SMALL},
   {"dsp", no_argument, NULL, OPTION_DSP},
-  {"isa",                    required_argument, NULL, OPTION_ISA},
+  {"isa", required_argument, NULL, OPTION_ISA},
   {"renesas", no_argument, NULL, OPTION_RENESAS},
+  {"allow-reg-prefix", no_argument, NULL, OPTION_ALLOW_REG_PREFIX},
 
 #ifdef HAVE_SH64
-#define OPTION_ABI                    (OPTION_RENESAS + 1)
-#define OPTION_NO_MIX                 (OPTION_ABI + 1)
-#define OPTION_SHCOMPACT_CONST_CRANGE (OPTION_NO_MIX + 1)
-#define OPTION_NO_EXPAND              (OPTION_SHCOMPACT_CONST_CRANGE + 1)
-#define OPTION_PT32                   (OPTION_NO_EXPAND + 1)
   {"abi",                    required_argument, NULL, OPTION_ABI},
   {"no-mix",                 no_argument, NULL, OPTION_NO_MIX},
   {"shcompact-const-crange", no_argument, NULL, OPTION_SHCOMPACT_CONST_CRANGE},
@@ -2897,24 +3105,24 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
       break;
 
     case OPTION_DSP:
-      preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
+      preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
       break;
 
     case OPTION_RENESAS:
       dont_adjust_reloc_32 = 1;
       break;
 
+    case OPTION_ALLOW_REG_PREFIX:
+      allow_dollar_register_prefix = 1;
+      break;
+
     case OPTION_ISA:
-      if (strcasecmp (arg, "sh4") == 0)
-	preset_target_arch = arch_sh4;
-      else if (strcasecmp (arg, "sh4a") == 0)
-	preset_target_arch = arch_sh4a;
-      else if (strcasecmp (arg, "dsp") == 0)
-	preset_target_arch = arch_sh1_up & ~arch_sh2e_up;
+      if (strcasecmp (arg, "dsp") == 0)
+	preset_target_arch = arch_sh_up & ~(arch_sh_sp_fpu|arch_sh_dp_fpu);
       else if (strcasecmp (arg, "fp") == 0)
-	preset_target_arch = arch_sh2e_up;
+	preset_target_arch = arch_sh_up & ~arch_sh_has_dsp;
       else if (strcasecmp (arg, "any") == 0)
-	preset_target_arch = arch_sh1_up;
+	preset_target_arch = arch_sh_up;
 #ifdef HAVE_SH64
       else if (strcasecmp (arg, "shmedia") == 0)
 	{
@@ -2932,7 +3140,35 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
 	}
 #endif /* HAVE_SH64 */
       else
-	as_bad ("Invalid argument to --isa option: %s", arg);
+	{
+	  extern const bfd_arch_info_type bfd_sh_arch;
+	  bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
+
+	  preset_target_arch = 0;
+	  for (; bfd_arch; bfd_arch=bfd_arch->next)
+	    {
+	      int len = strlen(bfd_arch->printable_name);
+	      
+	      if (bfd_arch->mach == bfd_mach_sh5)
+		continue;
+	      
+	      if (strncasecmp (bfd_arch->printable_name, arg, len) != 0)
+		continue;
+
+	      if (arg[len] == '\0')
+		preset_target_arch =
+		  sh_get_arch_from_bfd_mach (bfd_arch->mach);
+	      else if (strcasecmp(&arg[len], "-up") == 0)
+		preset_target_arch =
+		  sh_get_arch_up_from_bfd_mach (bfd_arch->mach);
+	      else
+		continue;
+	      break;
+	    }
+	  
+	  if (!preset_target_arch)
+	    as_bad ("Invalid argument to --isa option: %s", arg);
+	}
       break;
 
 #ifdef HAVE_SH64
@@ -2984,40 +3220,45 @@ md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 SH options:\n\
--little			generate little endian code\n\
--big			generate big endian code\n\
--relax			alter jump instructions for long displacements\n\
--renesas		disable optimization with section symbol for\n\
+--little		generate little endian code\n\
+--big			generate big endian code\n\
+--relax			alter jump instructions for long displacements\n\
+--renesas		disable optimization with section symbol for\n\
 			compatibility with Renesas assembler.\n\
--small			align sections to 4 byte boundaries, not 16\n\
--dsp			enable sh-dsp insns, and disable floating-point ISAs.\n"));
+--small			align sections to 4 byte boundaries, not 16\n\
+--dsp			enable sh-dsp insns, and disable floating-point ISAs.\n\
+--allow-reg-prefix	allow '$' as a register name prefix.\n\
+--isa=[any		use most appropriate isa\n\
+    | dsp               same as '-dsp'\n\
+    | fp"));
+  {
+    extern const bfd_arch_info_type bfd_sh_arch;
+    bfd_arch_info_type const *bfd_arch = &bfd_sh_arch;
+
+    for (; bfd_arch; bfd_arch=bfd_arch->next)
+      if (bfd_arch->mach != bfd_mach_sh5)
+	{
+	  fprintf (stream, "\n    | %s", bfd_arch->printable_name);
+	  fprintf (stream, "\n    | %s-up", bfd_arch->printable_name);
+	}
+  }
+  fprintf (stream, "]\n");
 #ifdef HAVE_SH64
   fprintf (stream, _("\
--isa=[sh4\n\
-    | sh4a\n\
-    | dsp		same as '-dsp'\n\
-    | fp\n\
-    | shmedia		set as the default instruction set for SH64\n\
+--isa=[shmedia		set as the default instruction set for SH64\n\
     | SHmedia\n\
     | shcompact\n\
-    | SHcompact\n"));
+    | SHcompact]\n"));
   fprintf (stream, _("\
--abi=[32|64]		set size of expanded SHmedia operands and object\n\
+--abi=[32|64]		set size of expanded SHmedia operands and object\n\
 			file type\n\
--shcompact-const-crange	emit code-range descriptors for constants in\n\
+--shcompact-const-crange  emit code-range descriptors for constants in\n\
 			SHcompact code sections\n\
--no-mix			disallow SHmedia code in the same section as\n\
+--no-mix		disallow SHmedia code in the same section as\n\
 			constants and SHcompact code\n\
--no-expand		do not expand MOVI, PT, PTA or PTB instructions\n\
--expand-pt32		with -abi=64, expand PT, PTA and PTB instructions\n\
+--no-expand		do not expand MOVI, PT, PTA or PTB instructions\n\
+--expand-pt32		with -abi=64, expand PT, PTA and PTB instructions\n\
 			to 32 bits only\n"));
-#else
-  fprintf (stream, _("\
--isa=[sh4\n\
-    | sh4a\n\
-    | dsp		same as '-dsp'\n\
-    | fp\n\
-    | any]\n"));
 #endif /* HAVE_SH64 */
 }
 
@@ -3033,8 +3274,7 @@ struct sh_count_relocs
 };
 
 /* Count the number of fixups in a section which refer to a particular
-   symbol.  When using BFD_ASSEMBLER, this is called via
-   bfd_map_over_sections.  */
+   symbol.  This is called via bfd_map_over_sections.  */
 
 static void
 sh_count_relocs (bfd *abfd ATTRIBUTE_UNUSED, segT sec, void *data)
@@ -3059,8 +3299,8 @@ sh_count_relocs (bfd *abfd ATTRIBUTE_UNUSED, segT sec, void *data)
     }
 }
 
-/* Handle the count relocs for a particular section.  When using
-   BFD_ASSEMBLER, this is called via bfd_map_over_sections.  */
+/* Handle the count relocs for a particular section.
+   This is called via bfd_map_over_sections.  */
 
 static void
 sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
@@ -3090,9 +3330,6 @@ sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
 	  || fix->fx_subsy != NULL
 	  || fix->fx_addnumber != 0
 	  || S_GET_SEGMENT (sym) != sec
-#if ! defined (BFD_ASSEMBLER) && defined (OBJ_COFF)
-	  || S_GET_STORAGE_CLASS (sym) == C_EXT
-#endif
 	  || S_IS_EXTERNAL (sym))
 	{
 	  as_warn_where (fix->fx_file, fix->fx_line,
@@ -3132,9 +3369,6 @@ sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
 	  || fscan->fx_subsy != NULL
 	  || fscan->fx_addnumber != 0
 	  || S_GET_SEGMENT (sym) != sec
-#if ! defined (BFD_ASSEMBLER) && defined (OBJ_COFF)
-	  || S_GET_STORAGE_CLASS (sym) == C_EXT
-#endif
 	  || S_IS_EXTERNAL (sym))
 	{
 	  as_warn_where (fix->fx_file, fix->fx_line,
@@ -3146,16 +3380,7 @@ sh_frob_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec,
 	 counting the number of times we find a reference to sym.  */
       info.sym = sym;
       info.count = 0;
-#ifdef BFD_ASSEMBLER
       bfd_map_over_sections (stdoutput, sh_count_relocs, &info);
-#else
-      {
-	int iscan;
-
-	for (iscan = SEG_E0; iscan < SEG_UNKNOWN; iscan++)
-	  sh_count_relocs ((bfd *) NULL, iscan, &info);
-      }
-#endif
 
       if (info.count < 1)
 	abort ();
@@ -3190,28 +3415,14 @@ sh_frob_file (void)
   if (! sh_relax)
     return;
 
-#ifdef BFD_ASSEMBLER
   bfd_map_over_sections (stdoutput, sh_frob_section, NULL);
-#else
-  {
-    int iseg;
-
-    for (iseg = SEG_E0; iseg < SEG_UNKNOWN; iseg++)
-      sh_frob_section ((bfd *) NULL, iseg, NULL);
-  }
-#endif
 }
 
 /* Called after relaxing.  Set the correct sizes of the fragments, and
-   create relocs so that md_apply_fix3 will fill in the correct values.  */
+   create relocs so that md_apply_fix will fill in the correct values.  */
 
 void
-#ifdef BFD_ASSEMBLER
 md_convert_frag (bfd *headers ATTRIBUTE_UNUSED, segT seg, fragS *fragP)
-#else
-md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED, segT seg,
-		 fragS *fragP)
-#endif
 {
   int donerelax = 0;
 
@@ -3284,12 +3495,7 @@ md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED, segT seg,
 
 	/* Build a relocation to six / four bytes farther on.  */
 	subseg_change (seg, 0);
-	fix_new (fragP, fragP->fr_fix, 2,
-#ifdef BFD_ASSEMBLER
-		 section_symbol (seg),
-#else
-		 seg_info (seg)->dot,
-#endif
+	fix_new (fragP, fragP->fr_fix, 2, section_symbol (seg),
 		 fragP->fr_address + fragP->fr_fix + (delay ? 4 : 6),
 		 1, BFD_RELOC_SH_PCDISP8BY2);
 
@@ -3356,17 +3562,12 @@ md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED, segT seg,
 valueT
 md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
 {
-#ifdef BFD_ASSEMBLER
 #ifdef OBJ_ELF
   return size;
 #else /* ! OBJ_ELF */
   return ((size + (1 << bfd_get_section_alignment (stdoutput, seg)) - 1)
 	  & (-1 << bfd_get_section_alignment (stdoutput, seg)));
 #endif /* ! OBJ_ELF */
-#else /* ! BFD_ASSEMBLER */
-  return ((size + (1 << section_alignment[(int) seg]) - 1)
-	  & (-1 << section_alignment[(int) seg]));
-#endif /* ! BFD_ASSEMBLER */
 }
 
 /* This static variable is set by s_uacons to tell sh_cons_align that
@@ -3563,33 +3764,16 @@ sh_elf_final_processing (void)
   if (sh64_isa_mode != sh64_isa_unspecified)
     val = EF_SH5;
   else
+#elif defined TARGET_SYMBIAN
+    if (1)
+      {
+	extern int sh_symbian_find_elf_flags (unsigned int);
+
+	val = sh_symbian_find_elf_flags (valid_arch);
+      }
+    else
 #endif /* HAVE_SH64 */
-  if (valid_arch & arch_sh1)
-    val = EF_SH1;
-  else if (valid_arch & arch_sh2)
-    val = EF_SH2;
-  else if (valid_arch & arch_sh2e)
-    val = EF_SH2E;
-  else if (valid_arch & arch_sh_dsp)
-    val = EF_SH_DSP;
-  else if (valid_arch & arch_sh3)
-    val = EF_SH3;
-  else if (valid_arch & arch_sh3_dsp)
-    val = EF_SH3_DSP;
-  else if (valid_arch & arch_sh3e)
-    val = EF_SH3E;
-  else if (valid_arch & arch_sh4_nofpu)
-    val = EF_SH4_NOFPU;
-  else if (valid_arch & arch_sh4)
-    val = EF_SH4;
-  else if (valid_arch & arch_sh4a_nofpu)
-    val = EF_SH4A_NOFPU;
-  else if (valid_arch & arch_sh4a)
-    val = EF_SH4A;
-  else if (valid_arch & arch_sh4al_dsp)
-    val = EF_SH4AL_DSP;
-  else
-    abort ();
+    val = sh_find_elf_flags (valid_arch);
 
   elf_elfheader (stdoutput)->e_flags &= ~EF_SH_MACH_MASK;
   elf_elfheader (stdoutput)->e_flags |= val;
@@ -3599,7 +3783,7 @@ sh_elf_final_processing (void)
 /* Apply a fixup to the object file.  */
 
 void
-md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
   int lowbyte = target_big_endian ? 1 : 0;
@@ -3608,7 +3792,6 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
   long max, min;
   int shift;
 
-#ifdef BFD_ASSEMBLER
   /* A difference between two symbols, the second of which is in the
      current section, is transformed in a PC-relative relocation to
      the other symbol.  We have to adjust the relocation type here.  */
@@ -3654,29 +3837,65 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       && fixP->fx_addsy != NULL
       && S_IS_WEAK (fixP->fx_addsy))
     val -= S_GET_VALUE  (fixP->fx_addsy);
-#endif
 
-#ifdef BFD_ASSEMBLER
   if (SWITCH_TABLE (fixP))
     val -= S_GET_VALUE  (fixP->fx_subsy);
-#else
-  if (fixP->fx_r_type == 0)
-    {
-      if (fixP->fx_size == 2)
-	fixP->fx_r_type = BFD_RELOC_16;
-      else if (fixP->fx_size == 4)
-	fixP->fx_r_type = BFD_RELOC_32;
-      else if (fixP->fx_size == 1)
-	fixP->fx_r_type = BFD_RELOC_8;
-      else
-	abort ();
-    }
-#endif
 
   max = min = 0;
   shift = 0;
   switch (fixP->fx_r_type)
     {
+    case BFD_RELOC_SH_IMM3:
+      max = 0x7;
+      * buf = (* buf & 0xf8) | (val & 0x7);
+      break;
+    case BFD_RELOC_SH_IMM3U:
+      max = 0x7;
+      * buf = (* buf & 0x8f) | ((val & 0x7) << 4);
+      break;
+    case BFD_RELOC_SH_DISP12:
+      max = 0xfff;
+      buf[lowbyte] = val & 0xff;
+      buf[highbyte] |= (val >> 8) & 0x0f;
+      break;
+    case BFD_RELOC_SH_DISP12BY2:
+      max = 0xfff;
+      shift = 1;
+      buf[lowbyte] = (val >> 1) & 0xff;
+      buf[highbyte] |= (val >> 9) & 0x0f;
+      break;
+    case BFD_RELOC_SH_DISP12BY4:
+      max = 0xfff;
+      shift = 2;
+      buf[lowbyte] = (val >> 2) & 0xff;
+      buf[highbyte] |= (val >> 10) & 0x0f;
+      break;
+    case BFD_RELOC_SH_DISP12BY8:
+      max = 0xfff;
+      shift = 3;
+      buf[lowbyte] = (val >> 3) & 0xff;
+      buf[highbyte] |= (val >> 11) & 0x0f;
+      break;
+    case BFD_RELOC_SH_DISP20:
+      if (! target_big_endian)
+	abort();
+      max = 0x7ffff;
+      min = -0x80000;
+      buf[1] = (buf[1] & 0x0f) | ((val >> 12) & 0xf0);
+      buf[2] = (val >> 8) & 0xff;
+      buf[3] = val & 0xff;
+      break;
+    case BFD_RELOC_SH_DISP20BY8:
+      if (!target_big_endian)
+	abort();
+      max = 0x7ffff;
+      min = -0x80000;
+      shift = 8;
+      buf[1] = (buf[1] & 0x0f) | ((val >> 20) & 0xf0);
+      buf[2] = (val >> 16) & 0xff;
+      buf[3] = (val >> 8) & 0xff;
+      break;
+
     case BFD_RELOC_SH_IMM4:
       max = 0xf;
       *buf = (*buf & 0xf0) | (val & 0xf);
@@ -3769,7 +3988,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       break;
 
     case BFD_RELOC_SH_USES:
-      /* Pass the value into sh_coff_reloc_mangle.  */
+      /* Pass the value into sh_reloc().  */
       fixP->fx_addnumber = val;
       break;
 
@@ -3844,7 +4063,7 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 
     default:
 #ifdef HAVE_SH64
-      shmedia_md_apply_fix3 (fixP, valP);
+      shmedia_md_apply_fix (fixP, valP);
       return;
 #else
       abort ();
@@ -3961,8 +4180,7 @@ md_number_to_chars (char *ptr, valueT use, int nbytes)
     number_to_chars_bigendian (ptr, use, nbytes);
 }
 
-/* This version is used in obj-coff.c when not using BFD_ASSEMBLER.
-   eg for the sh-hms target.  */
+/* This version is used in obj-coff.c eg. for the sh-hms target.  */
 
 long
 md_pcrel_from (fixS *fixP)
@@ -3988,167 +4206,6 @@ md_pcrel_from_section (fixS *fixP, segT sec)
   return md_pcrel_from (fixP);
 }
 
-#ifdef OBJ_COFF
-
-int
-tc_coff_sizemachdep (fragS *frag)
-{
-  return md_relax_table[frag->fr_subtype].rlx_length;
-}
-
-#endif /* OBJ_COFF */
-
-#ifndef BFD_ASSEMBLER
-#ifdef OBJ_COFF
-
-/* Map BFD relocs to SH COFF relocs.  */
-
-struct reloc_map
-{
-  bfd_reloc_code_real_type bfd_reloc;
-  int sh_reloc;
-};
-
-static const struct reloc_map coff_reloc_map[] =
-{
-  { BFD_RELOC_32, R_SH_IMM32 },
-  { BFD_RELOC_16, R_SH_IMM16 },
-  { BFD_RELOC_8, R_SH_IMM8 },
-  { BFD_RELOC_SH_PCDISP8BY2, R_SH_PCDISP8BY2 },
-  { BFD_RELOC_SH_PCDISP12BY2, R_SH_PCDISP },
-  { BFD_RELOC_SH_IMM4, R_SH_IMM4 },
-  { BFD_RELOC_SH_IMM4BY2, R_SH_IMM4BY2 },
-  { BFD_RELOC_SH_IMM4BY4, R_SH_IMM4BY4 },
-  { BFD_RELOC_SH_IMM8, R_SH_IMM8 },
-  { BFD_RELOC_SH_IMM8BY2, R_SH_IMM8BY2 },
-  { BFD_RELOC_SH_IMM8BY4, R_SH_IMM8BY4 },
-  { BFD_RELOC_SH_PCRELIMM8BY2, R_SH_PCRELIMM8BY2 },
-  { BFD_RELOC_SH_PCRELIMM8BY4, R_SH_PCRELIMM8BY4 },
-  { BFD_RELOC_8_PCREL, R_SH_SWITCH8 },
-  { BFD_RELOC_SH_SWITCH16, R_SH_SWITCH16 },
-  { BFD_RELOC_SH_SWITCH32, R_SH_SWITCH32 },
-  { BFD_RELOC_SH_USES, R_SH_USES },
-  { BFD_RELOC_SH_COUNT, R_SH_COUNT },
-  { BFD_RELOC_SH_ALIGN, R_SH_ALIGN },
-  { BFD_RELOC_SH_CODE, R_SH_CODE },
-  { BFD_RELOC_SH_DATA, R_SH_DATA },
-  { BFD_RELOC_SH_LABEL, R_SH_LABEL },
-  { BFD_RELOC_UNUSED, 0 }
-};
-
-/* Adjust a reloc for the SH.  This is similar to the generic code,
-   but does some minor tweaking.  */
-
-void
-sh_coff_reloc_mangle (segment_info_type *seg, fixS *fix,
-		      struct internal_reloc *intr, unsigned int paddr)
-{
-  symbolS *symbol_ptr = fix->fx_addsy;
-  symbolS *dot;
-
-  intr->r_vaddr = paddr + fix->fx_frag->fr_address + fix->fx_where;
-
-  if (! SWITCH_TABLE (fix))
-    {
-      const struct reloc_map *rm;
-
-      for (rm = coff_reloc_map; rm->bfd_reloc != BFD_RELOC_UNUSED; rm++)
-	if (rm->bfd_reloc == (bfd_reloc_code_real_type) fix->fx_r_type)
-	  break;
-      if (rm->bfd_reloc == BFD_RELOC_UNUSED)
-	as_bad_where (fix->fx_file, fix->fx_line,
-		      _("Can not represent %s relocation in this object file format"),
-		      bfd_get_reloc_code_name (fix->fx_r_type));
-      intr->r_type = rm->sh_reloc;
-      intr->r_offset = 0;
-    }
-  else
-    {
-      know (sh_relax);
-
-      if (fix->fx_r_type == BFD_RELOC_16)
-	intr->r_type = R_SH_SWITCH16;
-      else if (fix->fx_r_type == BFD_RELOC_8)
-	intr->r_type = R_SH_SWITCH8;
-      else if (fix->fx_r_type == BFD_RELOC_32)
-	intr->r_type = R_SH_SWITCH32;
-      else
-	abort ();
-
-      /* For a switch reloc, we set r_offset to the difference between
-         the reloc address and the subtrahend.  When the linker is
-         doing relaxing, it can use the determine the starting and
-         ending points of the switch difference expression.  */
-      intr->r_offset = intr->r_vaddr - S_GET_VALUE (fix->fx_subsy);
-    }
-
-  /* PC relative relocs are always against the current section.  */
-  if (symbol_ptr == NULL)
-    {
-      switch (fix->fx_r_type)
-	{
-	case BFD_RELOC_SH_PCRELIMM8BY2:
-	case BFD_RELOC_SH_PCRELIMM8BY4:
-	case BFD_RELOC_SH_PCDISP8BY2:
-	case BFD_RELOC_SH_PCDISP12BY2:
-	case BFD_RELOC_SH_USES:
-	  symbol_ptr = seg->dot;
-	  break;
-	default:
-	  break;
-	}
-    }
-
-  if (fix->fx_r_type == BFD_RELOC_SH_USES)
-    {
-      /* We can't store the offset in the object file, since this
-	 reloc does not take up any space, so we store it in r_offset.
-	 The fx_addnumber field was set in md_apply_fix3.  */
-      intr->r_offset = fix->fx_addnumber;
-    }
-  else if (fix->fx_r_type == BFD_RELOC_SH_COUNT)
-    {
-      /* We can't store the count in the object file, since this reloc
-         does not take up any space, so we store it in r_offset.  The
-         fx_offset field was set when the fixup was created in
-         sh_coff_frob_file.  */
-      intr->r_offset = fix->fx_offset;
-      /* This reloc is always absolute.  */
-      symbol_ptr = NULL;
-    }
-  else if (fix->fx_r_type == BFD_RELOC_SH_ALIGN)
-    {
-      /* Store the alignment in the r_offset field.  */
-      intr->r_offset = fix->fx_offset;
-      /* This reloc is always absolute.  */
-      symbol_ptr = NULL;
-    }
-  else if (fix->fx_r_type == BFD_RELOC_SH_CODE
-	   || fix->fx_r_type == BFD_RELOC_SH_DATA
-	   || fix->fx_r_type == BFD_RELOC_SH_LABEL)
-    {
-      /* These relocs are always absolute.  */
-      symbol_ptr = NULL;
-    }
-
-  /* Turn the segment of the symbol into an offset.  */
-  if (symbol_ptr != NULL)
-    {
-      dot = segment_info[S_GET_SEGMENT (symbol_ptr)].dot;
-      if (dot != NULL)
-	intr->r_symndx = dot->sy_number;
-      else
-	intr->r_symndx = symbol_ptr->sy_number;
-    }
-  else
-    intr->r_symndx = -1;
-}
-
-#endif /* OBJ_COFF */
-#endif /* ! BFD_ASSEMBLER */
-
-#ifdef BFD_ASSEMBLER
-
 /* Create a reloc.  */
 
 arelent *
@@ -4238,7 +4295,10 @@ sh_end_of_match (char *cont, char *what)
 }
 
 int
-sh_parse_name (char const *name, expressionS *exprP, char *nextcharP)
+sh_parse_name (char const *name,
+	       expressionS *exprP,
+	       enum expr_mode mode,
+	       char *nextcharP)
 {
   char *next = input_line_pointer;
   char *next_end;
@@ -4255,15 +4315,15 @@ sh_parse_name (char const *name, expressionS *exprP, char *nextcharP)
       exprP->X_add_symbol = GOT_symbol;
     no_suffix:
       /* If we have an absolute symbol or a reg, then we know its
-	     value now.  */
+	 value now.  */
       segment = S_GET_SEGMENT (exprP->X_add_symbol);
-      if (segment == absolute_section)
+      if (mode != expr_defer && segment == absolute_section)
 	{
 	  exprP->X_op = O_constant;
 	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
 	  exprP->X_add_symbol = NULL;
 	}
-      else if (segment == reg_section)
+      else if (mode != expr_defer && segment == reg_section)
 	{
 	  exprP->X_op = O_register;
 	  exprP->X_add_number = S_GET_VALUE (exprP->X_add_symbol);
@@ -4314,7 +4374,6 @@ sh_parse_name (char const *name, expressionS *exprP, char *nextcharP)
 
   return 1;
 }
-#endif
 
 void
 sh_cfi_frame_initial_instructions (void)
@@ -4364,4 +4423,4 @@ sh_regname_to_dw2regnum (const char *regname)
     }
   return regnum;
 }
-#endif /* BFD_ASSEMBLER */
+#endif /* OBJ_ELF */
diff --git a/gas/config/tc-sh.h b/gas/config/tc-sh.h
index 9931847b01c4..a812036fcd51 100644
--- a/gas/config/tc-sh.h
+++ b/gas/config/tc-sh.h
@@ -1,6 +1,6 @@
 /* This file is tc-sh.h
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-   2003 Free Software Foundation, Inc.
+   2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,14 +16,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_SH
 
 #define TARGET_ARCH bfd_arch_sh
 
-#if ANSI_PROTOTYPES
 /* The type fixS is defined (to struct fix) in write.h, but write.h uses
    definitions from this file.  To avoid problems with including write.h
    after the "right" definitions, don't; just forward-declare struct fix
@@ -31,7 +30,6 @@
 struct fix;
 struct segment_info_struct;
 struct internal_reloc;
-#endif
 
 /* Whether -relax was used.  */
 extern int sh_relax;
@@ -62,16 +60,6 @@ extern int sh_force_relocation (struct fix *);
    to know about all such entries so that it can adjust them if
    necessary.  */
 
-#ifdef BFD_ASSEMBLER
-#define SWITCH_TABLE_CONS(FIX) (0)
-#else
-#define SWITCH_TABLE_CONS(FIX)				\
-  ((FIX)->fx_r_type == 0				\
-   && ((FIX)->fx_size == 2				\
-       || (FIX)->fx_size == 1				\
-       || (FIX)->fx_size == 4))
-#endif
-
 #define SWITCH_TABLE(FIX)				\
   ((FIX)->fx_addsy != NULL				\
    && (FIX)->fx_subsy != NULL				\
@@ -79,8 +67,7 @@ extern int sh_force_relocation (struct fix *);
    && S_GET_SEGMENT ((FIX)->fx_subsy) == text_section	\
    && ((FIX)->fx_r_type == BFD_RELOC_32			\
        || (FIX)->fx_r_type == BFD_RELOC_16		\
-       || (FIX)->fx_r_type == BFD_RELOC_8		\
-       || SWITCH_TABLE_CONS (FIX)))
+       || (FIX)->fx_r_type == BFD_RELOC_8))
 
 #define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEC)		\
   (! SEG_NORMAL (SEC)					\
@@ -116,57 +103,28 @@ struct sh_segment_info_type
 
 /* We call a routine to emit a reloc for a label, so that the linker
    can align loads and stores without crossing a label.  */
-extern void sh_frob_label (void);
-#define tc_frob_label(sym) sh_frob_label ()
+extern void sh_frob_label (symbolS *);
+#define tc_frob_label(sym) sh_frob_label (sym)
 
 /* We call a routine to flush pending output in order to output a DATA
    reloc when required.  */
 extern void sh_flush_pending_output (void);
 #define md_flush_pending_output() sh_flush_pending_output ()
 
-#ifdef BFD_ASSEMBLER
 #define tc_frob_file_before_adjust sh_frob_file
-#else
-#define tc_frob_file sh_frob_file
-#endif
 extern void sh_frob_file (void);
 
 
 #ifdef OBJ_COFF
 /* COFF specific definitions.  */
 
-#define DO_NOT_STRIP 0
-
-/* This macro translates between an internal fix and a coff reloc type.  */
-#define TC_COFF_FIX2RTYPE(fix) ((fix)->fx_r_type)
-
-#define BFD_ARCH TARGET_ARCH
-
 #define COFF_MAGIC (!target_big_endian ? SH_ARCH_MAGIC_LITTLE : SH_ARCH_MAGIC_BIG)
 
-/* We need to write out relocs which have not been completed.  */
-#define TC_COUNT_RELOC(fix) ((fix)->fx_addsy != NULL)
-
-#define TC_RELOC_MANGLE(seg, fix, int, paddr) \
-  sh_coff_reloc_mangle ((seg), (fix), (int), (paddr))
-extern void sh_coff_reloc_mangle
-  (struct segment_info_struct *, struct fix *,
-   struct internal_reloc *, unsigned int);
-
 #define tc_coff_symbol_emit_hook(a) ; /* not used */
 
-#define NEED_FX_R_TYPE 1
-
 #define TC_KEEP_FX_OFFSET 1
 
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
-extern int tc_coff_sizemachdep (fragS *);
-
-#ifdef BFD_ASSEMBLER
 #define SEG_NAME(SEG) segment_name (SEG)
-#else
-#define SEG_NAME(SEG) obj_segment_name (SEG)
-#endif
 
 /* We align most sections to a 16 byte boundary.  */
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN)			\
@@ -189,6 +147,8 @@ extern int target_big_endian;
 #define TARGET_FORMAT (!target_big_endian ? "elf32-sh-linux" : "elf32-shbig-linux")
 #elif defined(TE_NetBSD)
 #define TARGET_FORMAT (!target_big_endian ? "elf32-shl-nbsd" : "elf32-sh-nbsd")
+#elif defined TARGET_SYMBIAN
+#define TARGET_FORMAT (!target_big_endian ? "elf32-shl-symbian" : "elf32-sh-symbian")
 #else
 #define TARGET_FORMAT (!target_big_endian ? "elf32-shl" : "elf32-sh")
 #endif
@@ -212,7 +172,7 @@ extern void sh_elf_final_processing (void);
 #define tc_fix_adjustable(FIX) sh_fix_adjustable(FIX)
 extern bfd_boolean sh_fix_adjustable (struct fix *);
 
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* This expression evaluates to true if the relocation is for a local object
@@ -246,9 +206,10 @@ extern bfd_boolean sh_fix_adjustable (struct fix *);
   ((FIX)->fx_r_type == BFD_RELOC_32_PLT_PCREL		\
    || (sh_relax && SWITCH_TABLE (FIX)))
 
-#define md_parse_name(name, exprP, nextcharP) \
-  sh_parse_name ((name), (exprP), (nextcharP))
-int sh_parse_name (char const *name, expressionS *exprP, char *nextchar);
+#define md_parse_name(name, exprP, mode, nextcharP) \
+  sh_parse_name ((name), (exprP), (mode), (nextcharP))
+int sh_parse_name (char const *name, expressionS *exprP,
+		   enum expr_mode mode, char *nextchar);
 
 #define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \
   sh_cons_fix_new ((FRAG), (OFF), (LEN), (EXP))
diff --git a/gas/config/tc-sh64.c b/gas/config/tc-sh64.c
index 7a6f830e405d..74330612e43a 100644
--- a/gas/config/tc-sh64.c
+++ b/gas/config/tc-sh64.c
@@ -1,5 +1,5 @@
 /* tc-sh64.c -- Assemble code for the SuperH SH SHcompact and SHmedia.
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 /* This file defines SHmedia ISA-specific functions and includes tc-sh.c.
    The SHcompact ISA is in all useful aspects the "old" sh4 as implemented
@@ -39,7 +39,7 @@
    symbol" or local symbol.  */
 #define DATALABEL_SUFFIX " DL"
 
-/* See shmedia_md_apply_fix3 and shmedia_md_pcrel_from_section for usage.  */
+/* See shmedia_md_apply_fix and shmedia_md_pcrel_from_section for usage.  */
 #define SHMEDIA_MD_PCREL_FROM_FIX(FIXP) \
  ((FIXP)->fx_size + (FIXP)->fx_where + (FIXP)->fx_frag->fr_address - 4)
 
@@ -136,7 +136,7 @@ static const unsigned char shmedia_little_nop_pattern[4] =
 static void shmedia_md_begin (void);
 static int shmedia_parse_reg (char *, int *, int *, shmedia_arg_type);
 static void shmedia_md_assemble (char *);
-static void shmedia_md_apply_fix3 (fixS *, valueT *);
+static void shmedia_md_apply_fix (fixS *, valueT *);
 static int shmedia_md_estimate_size_before_relax (fragS *, segT);
 static int shmedia_init_reloc (arelent *, fixS *);
 static char *shmedia_get_operands (shmedia_opcode_info *, char *,
@@ -284,7 +284,7 @@ shmedia_frob_file_before_adjust (void)
 
       if (mainsym != NULL
 	  && S_GET_OTHER (mainsym) != STO_SH5_ISA32
-	  && (S_IS_EXTERN (mainsym) || S_IS_WEAK (mainsym)))
+	  && (S_IS_EXTERNAL (mainsym) || S_IS_WEAK (mainsym)))
 	{
 	  symp->sy_value.X_op = O_symbol;
 	  symp->sy_value.X_add_symbol = mainsym;
@@ -577,10 +577,10 @@ shmedia_init_reloc (arelent *rel, fixS *fixP)
   return 0;
 }
 
-/* Hook called from md_apply_fix3 in tc-sh.c.  */
+/* Hook called from md_apply_fix in tc-sh.c.  */
 
 static void
-shmedia_md_apply_fix3 (fixS *fixP, valueT *valp)
+shmedia_md_apply_fix (fixS *fixP, valueT *valp)
 {
   offsetT val = *valp;
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
@@ -602,7 +602,7 @@ shmedia_md_apply_fix3 (fixS *fixP, valueT *valp)
 	  /* Because write.c calls MD_PCREL_FROM_SECTION twice, we need to
 	     undo one of the adjustments, if the relocation is not
 	     actually for a symbol within the same segment (which we
-	     cannot check, because we're not called from md_apply_fix3, so
+	     cannot check, because we're not called from md_apply_fix, so
 	     we have to keep the reloc).  FIXME: This is a bug in
 	     write.c:fixup_segment affecting most targets that change
 	     ordinary relocs to pcrel relocs in md_apply_fix.  */
@@ -691,7 +691,7 @@ shmedia_md_apply_fix3 (fixS *fixP, valueT *valp)
   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
     {
       /* Emit error for an out-of-range value.  */
-      shmedia_check_limits (valp, fixP->fx_r_type, fixP);
+      shmedia_check_limits ((offsetT *) valp, fixP->fx_r_type, fixP);
 
       switch (fixP->fx_r_type)
 	{
@@ -739,6 +739,11 @@ shmedia_md_apply_fix3 (fixS *fixP, valueT *valp)
 			      insn | ((val & (0x3ff << 2)) << (10 - 2)), 4);
 	  break;
 
+	case BFD_RELOC_SH_IMMS10BY8:
+	  md_number_to_chars (buf,
+			      insn | ((val & (0x3ff << 3)) << (10 - 3)), 4);
+	  break;
+
 	case BFD_RELOC_SH_SHMEDIA_CODE:
 	  /* We just ignore and remove this one for the moment.  FIXME:
 	     Use it when implementing relaxing.  */
@@ -818,7 +823,7 @@ shmedia_md_convert_frag (bfd *output_bfd ATTRIBUTE_UNUSED,
        || sh_relax
        || symbolP == NULL
        || ! S_IS_DEFINED (symbolP)
-       || S_IS_EXTERN (symbolP)
+       || S_IS_EXTERNAL (symbolP)
        || S_IS_WEAK (symbolP)
        || (S_GET_SEGMENT (fragP->fr_symbol) != absolute_section
 	   && S_GET_SEGMENT (fragP->fr_symbol) != seg));
@@ -2672,7 +2677,10 @@ shmedia_build_Mytes (shmedia_opcode_info *opcode,
 
 	    /* Don't allow complex expressions here.  */
 	    if (opjp->immediate.X_op_symbol != NULL)
-	      return 0;
+	      {
+		as_bad(_("invalid operand: expression in PT target"));
+		return 0;
+	      }
 
 	    if (opjp->reloctype == BFD_RELOC_32_PLT_PCREL)
 	      init = max = min = SH64PCRELPLT;
@@ -2709,7 +2717,10 @@ shmedia_build_Mytes (shmedia_opcode_info *opcode,
 
 	    /* Don't allow complex expressions here.  */
 	    if (opjp->immediate.X_op_symbol != NULL)
-	      return 0;
+	      {
+		as_bad(_("invalid operand: expression in PT target"));
+		return 0;
+	      }
 
 	    if (opjp->reloctype == BFD_RELOC_32_PLT_PCREL)
 	      init = max = min = SH64PCRELPLT;
@@ -2725,7 +2736,7 @@ shmedia_build_Mytes (shmedia_opcode_info *opcode,
 			insn_loc);
 	    else
 	      /* This reloc-type is just temporary, so we can distinguish
-		 PTA from PT.  It is changed in shmedia_md_apply_fix3 to
+		 PTA from PT.  It is changed in shmedia_md_apply_fix to
 		 BFD_RELOC_SH_PT_16.  */
 	      insn |= shmedia_immediate_op (insn_loc, opjp, 1,
 					    opjp->reloctype == BFD_RELOC_NONE
@@ -2917,14 +2928,14 @@ sh64_target_format (void)
 {
 #ifdef TE_NetBSD
   /* For NetBSD, if the ISA is unspecified, always use SHmedia.  */
-  if (sh64_isa_mode == sh64_isa_unspecified)
+  if (preset_target_arch == 0 && sh64_isa_mode == sh64_isa_unspecified)
     sh64_isa_mode = sh64_isa_shmedia;
 
   /* If the ABI is unspecified, select a default: based on how
      we were configured: sh64 == sh64_abi_64, else sh64_abi_32.  */
   if (sh64_abi == sh64_abi_unspecified)
     {
-      if (sh64_isa_mode == sh64_isa_shcompact)
+      if (preset_target_arch != 0 || sh64_isa_mode == sh64_isa_shcompact)
 	sh64_abi = sh64_abi_32;
       else if (strncmp (TARGET_CPU, "sh64", 4) == 0)
         sh64_abi = sh64_abi_64;
@@ -2934,7 +2945,7 @@ sh64_target_format (void)
 #endif
 
 #ifdef TE_LINUX
-  if (sh64_isa_mode == sh64_isa_unspecified)
+  if (preset_target_arch == 0 && sh64_isa_mode == sh64_isa_unspecified)
     sh64_isa_mode = sh64_isa_shmedia;
 
   if (sh64_abi == sh64_abi_unspecified)
@@ -3233,8 +3244,9 @@ sh64_frob_label (symbolS *symp)
    symbol hook.  */
 
 int
-sh64_consume_datalabel (const char *name, expressionS *exp, char *cp,
-			segT (*operandf) (expressionS *))
+sh64_consume_datalabel (const char *name, expressionS *exp,
+			enum expr_mode mode, char *cp,
+			segT (*operandf) (expressionS *, enum expr_mode))
 {
   static int parsing_datalabel = 0;
 
@@ -3247,7 +3259,7 @@ sh64_consume_datalabel (const char *name, expressionS *exp, char *cp,
 
       *input_line_pointer = *cp;
       parsing_datalabel = 1;
-      (*operandf) (exp);
+      (*operandf) (exp, expr_normal);
       parsing_datalabel = save_parsing_datalabel;
 
       if (exp->X_op == O_symbol || exp->X_op == O_PIC_reloc)
@@ -3320,7 +3332,7 @@ sh64_consume_datalabel (const char *name, expressionS *exp, char *cp,
       return 1;
     }
 
-  return sh_parse_name (name, exp, cp);
+  return sh_parse_name (name, exp, mode, cp);
 }
 
 /* This function is called just before symbols are being output.  It
@@ -3502,3 +3514,18 @@ sh64_vtable_inherit (int ignore ATTRIBUTE_UNUSED)
   input_line_pointer = eol;
 }
 
+int
+sh64_fake_label (const char *name)
+{
+  size_t len;
+
+  if (strcmp (name, FAKE_LABEL_NAME) == 0)
+    return 1;
+
+  len = strlen (name);
+  if (len >= (sizeof (DATALABEL_SUFFIX) - 1))
+    return strcmp (&name [len - sizeof (DATALABEL_SUFFIX) + 1],
+		   DATALABEL_SUFFIX) == 0;
+
+  return 0;
+}
diff --git a/gas/config/tc-sh64.h b/gas/config/tc-sh64.h
index b82fa3920d76..21f5d59f4c56 100644
--- a/gas/config/tc-sh64.h
+++ b/gas/config/tc-sh64.h
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_SH64
 #include "config/tc-sh.h"
@@ -124,10 +124,11 @@ extern int sh64_target_mach (void);
    expression, since we have handled it ourselves.  FIXME: What we really
    need is a new GAS infrastructure feature: md_qualifier.  */
 #undef md_parse_name
-#define md_parse_name(NAME, EXP, CP) \
- sh64_consume_datalabel (NAME, EXP, CP, operand)
-extern int sh64_consume_datalabel (const char *, expressionS *, char *,
-				   segT (*) (expressionS *));
+#define md_parse_name(NAME, EXP, MODE, CP) \
+ sh64_consume_datalabel (NAME, EXP, MODE, CP, operand)
+extern int sh64_consume_datalabel (const char *, expressionS *,
+				   enum expr_mode, char *,
+				   segT (*) (expressionS *, enum expr_mode));
 
 /* Saying "$" is the same as saying ".".  */
 #define DOLLAR_DOT
@@ -144,7 +145,7 @@ extern void sh64_frob_label (symbolS *);
 
 #undef  tc_frob_label
 #define tc_frob_label(sym) \
-  do { sh_frob_label (); sh64_frob_label (sym); } while (0)
+  do { sh_frob_label (sym); sh64_frob_label (sym); } while (0)
 
 #define tc_symbol_new_hook(s) sh64_frob_label (s)
 
@@ -221,3 +222,6 @@ void shmedia_md_end (void);
    we have to say we only have minimum byte-size insns.  */
 #undef  DWARF2_LINE_MIN_INSN_LENGTH
 #define DWARF2_LINE_MIN_INSN_LENGTH 1
+
+#define TC_FAKE_LABEL(NAME) sh64_fake_label(NAME)
+extern int sh64_fake_label (const char *);
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index ba6b4ed5689a..10a1411b5260 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -1,6 +1,6 @@
 /* tc-sparc.c -- Assemble for the SPARC
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003, 2004
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public
    License along with GAS; see the file COPYING.  If not, write
-   to the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -133,7 +133,7 @@ int sparc_cie_data_alignment;
 /* Handle of the OPCODE hash table.  */
 static struct hash_control *op_hash;
 
-static int log2 PARAMS ((int));
+static int mylog2 PARAMS ((int));
 static void s_data1 PARAMS ((void));
 static void s_seg PARAMS ((int));
 static void s_proc PARAMS ((int));
@@ -174,9 +174,6 @@ const pseudo_typeS md_pseudo_table[] =
   {NULL, 0, 0},
 };
 
-/* Size of relocation record.  */
-const int md_reloc_size = 12;
-
 /* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "!";	/* JF removed '|' from
@@ -207,7 +204,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
    changed in read.c.  Ideally it shouldn't have to know about it at all,
    but nothing is ideal around here.  */
 
-#define isoctal(c)  ((unsigned) ((c) - '0') < '8')
+#define isoctal(c)  ((unsigned) ((c) - '0') < 8)
 
 struct sparc_it
   {
@@ -337,6 +334,10 @@ sparc_target_format ()
 #endif
 #endif
 
+#ifdef TE_VXWORKS
+  return "elf32-sparc-vxworks";
+#endif
+
 #ifdef OBJ_ELF
   return sparc_arch_size == 64 ? "elf64-sparc" : "elf32-sparc";
 #endif
@@ -727,7 +728,7 @@ struct
   {NULL, NULL, NULL},
 };
 
-/* sparc64 privileged registers.  */
+/* sparc64 privileged and hyperprivileged registers.  */
 
 struct priv_reg_entry
 {
@@ -753,10 +754,22 @@ struct priv_reg_entry priv_reg_table[] =
   {"otherwin", 13},
   {"wstate", 14},
   {"fq", 15},
+  {"gl", 16},
   {"ver", 31},
   {"", -1},			/* End marker.  */
 };
 
+struct priv_reg_entry hpriv_reg_table[] =
+{
+  {"hpstate", 0},
+  {"htstate", 1},
+  {"hintp", 3},
+  {"htba", 5},
+  {"hver", 6},
+  {"hstick_cmpr", 31},
+  {"", -1},			/* End marker.  */
+};
+
 /* v9a specific asrs.  */
 
 struct priv_reg_entry v9a_asr_table[] =
@@ -1304,11 +1317,12 @@ md_assemble (str)
 
   know (str);
   special_case = sparc_ip (str, &insn);
+  if (insn == NULL)
+    return;
 
   /* We warn about attempts to put a floating point branch in a delay slot,
      unless the delay slot has been annulled.  */
-  if (insn != NULL
-      && last_insn != NULL
+  if (last_insn != NULL
       && (insn->flags & F_FBR) != 0
       && (last_insn->flags & F_DELAYED) != 0
       /* ??? This test isn't completely accurate.  We assume anything with
@@ -1321,7 +1335,6 @@ md_assemble (str)
      point instruction and a floating point branch.  We insert one
      automatically, with a warning.  */
   if (max_architecture < SPARC_OPCODE_ARCH_V9
-      && insn != NULL
       && last_insn != NULL
       && (insn->flags & F_FBR) != 0
       && (last_insn->flags & F_FLOAT) != 0)
@@ -1417,7 +1430,9 @@ sparc_ip (str, pinsn)
       break;
 
     default:
-      as_fatal (_("Unknown opcode: `%s'"), str);
+      as_bad (_("Unknown opcode: `%s'"), str);
+      *pinsn = NULL;
+      return special_case;
     }
   insn = (struct sparc_opcode *) hash_find (op_hash, str);
   *pinsn = insn;
@@ -1573,6 +1588,42 @@ sparc_ip (str, pinsn)
 		  goto error;
 		}
 
+	    case '$':
+	    case '%':
+	      /* Parse a sparc64 hyperprivileged register.  */
+	      if (*s == '%')
+		{
+		  struct priv_reg_entry *p = hpriv_reg_table;
+		  unsigned int len = 9999999; /* Init to make gcc happy.  */
+
+		  s += 1;
+		  while (p->name[0] > s[0])
+		    p++;
+		  while (p->name[0] == s[0])
+		    {
+		      len = strlen (p->name);
+		      if (strncmp (p->name, s, len) == 0)
+			break;
+		      p++;
+		    }
+		  if (p->name[0] != s[0])
+		    {
+		      error_message = _(": unrecognizable hyperprivileged register");
+		      goto error;
+		    }
+		  if (*args == '$')
+		    opcode |= (p->regnum << 14);
+		  else
+		    opcode |= (p->regnum << 25);
+		  s += len;
+		  continue;
+		}
+	      else
+		{
+		  error_message = _(": unrecognizable hyperprivileged register");
+		  goto error;
+		}
+
 	    case '_':
 	    case '/':
 	      /* Parse a v9a/v9b ancillary state register.  */
@@ -2231,7 +2282,7 @@ sparc_ip (str, pinsn)
 	      {
 		char *s1;
 		char *op_arg = NULL;
-		expressionS op_exp;
+		static expressionS op_exp;
 		bfd_reloc_code_real_type old_reloc = the_insn.reloc;
 
 		/* Check for %hi, etc.  */
@@ -2484,12 +2535,12 @@ sparc_ip (str, pinsn)
 		      goto error;
 		    }
 
-		  /* Constants that won't fit are checked in md_apply_fix3
+		  /* Constants that won't fit are checked in md_apply_fix
 		     and bfd_install_relocation.
 		     ??? It would be preferable to install the constants
 		     into the insn here and save having to create a fixS
 		     for each one.  There already exists code to handle
-		     all the various cases (e.g. in md_apply_fix3 and
+		     all the various cases (e.g. in md_apply_fix and
 		     bfd_install_relocation) so duplicating all that code
 		     here isn't right.  */
 		}
@@ -2877,7 +2928,7 @@ output_insn (insn, the_insn)
 				 the_insn->pcrel,
 				 the_insn->reloc);
       /* Turn off overflow checking in fixup_segment.  We'll do our
-	 own overflow checking in md_apply_fix3.  This is necessary because
+	 own overflow checking in md_apply_fix.  This is necessary because
 	 the insn size is 4 and fixup_segment will signal an overflow for
 	 large 8 byte quantities.  */
       fixP->fx_no_overflow = 1;
@@ -2996,7 +3047,7 @@ md_number_to_chars (buf, val, n)
    hold.  */
 
 void
-md_apply_fix3 (fixP, valP, segment)
+md_apply_fix (fixP, valP, segment)
      fixS *fixP;
      valueT *valP;
      segT segment ATTRIBUTE_UNUSED;
@@ -3012,7 +3063,41 @@ md_apply_fix3 (fixP, valP, segment)
 #ifdef OBJ_ELF
   /* SPARC ELF relocations don't use an addend in the data field.  */
   if (fixP->fx_addsy != NULL)
-    return;
+    {
+      switch (fixP->fx_r_type)
+	{
+	case BFD_RELOC_SPARC_TLS_GD_HI22:
+	case BFD_RELOC_SPARC_TLS_GD_LO10:
+	case BFD_RELOC_SPARC_TLS_GD_ADD:
+	case BFD_RELOC_SPARC_TLS_GD_CALL:
+	case BFD_RELOC_SPARC_TLS_LDM_HI22:
+	case BFD_RELOC_SPARC_TLS_LDM_LO10:
+	case BFD_RELOC_SPARC_TLS_LDM_ADD:
+	case BFD_RELOC_SPARC_TLS_LDM_CALL:
+	case BFD_RELOC_SPARC_TLS_LDO_HIX22:
+	case BFD_RELOC_SPARC_TLS_LDO_LOX10:
+	case BFD_RELOC_SPARC_TLS_LDO_ADD:
+	case BFD_RELOC_SPARC_TLS_IE_HI22:
+	case BFD_RELOC_SPARC_TLS_IE_LO10:
+	case BFD_RELOC_SPARC_TLS_IE_LD:
+	case BFD_RELOC_SPARC_TLS_IE_LDX:
+	case BFD_RELOC_SPARC_TLS_IE_ADD:
+	case BFD_RELOC_SPARC_TLS_LE_HIX22:
+	case BFD_RELOC_SPARC_TLS_LE_LOX10:
+	case BFD_RELOC_SPARC_TLS_DTPMOD32:
+	case BFD_RELOC_SPARC_TLS_DTPMOD64:
+	case BFD_RELOC_SPARC_TLS_DTPOFF32:
+	case BFD_RELOC_SPARC_TLS_DTPOFF64:
+	case BFD_RELOC_SPARC_TLS_TPOFF32:
+	case BFD_RELOC_SPARC_TLS_TPOFF64:
+	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
+
+	default:
+	  break;
+	}
+
+      return;
+    }
 #endif
 
   /* This is a hack.  There should be a better way to
@@ -3447,6 +3532,10 @@ tc_gen_reloc (section, fixp)
 #else
 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_"
 #endif
+#ifdef TE_VXWORKS
+#define GOTT_BASE "__GOTT_BASE__"
+#define GOTT_INDEX "__GOTT_INDEX__"
+#endif
 
   /* This code must be parallel to the OBJ_ELF tc_fix_adjustable.  */
 
@@ -3459,18 +3548,30 @@ tc_gen_reloc (section, fixp)
 	    code = BFD_RELOC_SPARC_WPLT30;
 	  break;
 	case BFD_RELOC_HI22:
-	  if (fixp->fx_addsy != NULL
-	      && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
-	    code = BFD_RELOC_SPARC_PC22;
-	  else
-	    code = BFD_RELOC_SPARC_GOT22;
+	  code = BFD_RELOC_SPARC_GOT22;
+	  if (fixp->fx_addsy != NULL)
+	    {
+	      if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
+		code = BFD_RELOC_SPARC_PC22;
+#ifdef TE_VXWORKS
+	      if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
+		  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
+		code = BFD_RELOC_HI22; /* Unchanged.  */
+#endif
+	    }
 	  break;
 	case BFD_RELOC_LO10:
-	  if (fixp->fx_addsy != NULL
-	      && strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
-	    code = BFD_RELOC_SPARC_PC10;
-	  else
-	    code = BFD_RELOC_SPARC_GOT10;
+	  code = BFD_RELOC_SPARC_GOT10;
+	  if (fixp->fx_addsy != NULL)
+	    {
+	      if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0)
+		code = BFD_RELOC_SPARC_PC10;
+#ifdef TE_VXWORKS
+	      if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0
+		  || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0)
+		code = BFD_RELOC_LO10; /* Unchanged.  */
+#endif
+	    }
 	  break;
 	case BFD_RELOC_SPARC13:
 	  code = BFD_RELOC_SPARC_GOT13;
@@ -3603,7 +3704,7 @@ md_pcrel_from (fixP)
    of two.  */
 
 static int
-log2 (value)
+mylog2 (value)
      int value;
 {
   int shift;
@@ -3705,7 +3806,7 @@ s_reserve (ignore)
 
       if (align != 0)
 	{
-	  temp = log2 (align);
+	  temp = mylog2 (align);
 	  if (temp < 0)
 	    {
 	      as_bad (_("alignment not a power of 2"));
@@ -3843,7 +3944,7 @@ s_common (ignore)
       if (temp > max_alignment)
 	{
 	  temp = max_alignment;
-	  as_warn (_("alignment too large; assuming %d"), temp);
+	  as_warn (_("alignment too large; assuming %ld"), (long) temp);
 	}
 #endif
 
@@ -3868,7 +3969,7 @@ s_common (ignore)
 	  if (temp == 0)
 	    align = 0;
 	  else
-	    align = log2 (temp);
+	    align = mylog2 (temp);
 
 	  if (align < 0)
 	    {
@@ -3925,9 +4026,7 @@ s_common (ignore)
       goto allocate_common;
     }
 
-#ifdef BFD_ASSEMBLER
   symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
-#endif
 
   demand_empty_rest_of_line ();
   return;
@@ -4191,7 +4290,7 @@ sparc_cons_align (nbytes)
   if (sparc_no_align_cons)
     return;
 
-  nalign = log2 (nbytes);
+  nalign = mylog2 (nbytes);
   if (nalign == 0)
     return;
 
diff --git a/gas/config/tc-sparc.h b/gas/config/tc-sparc.h
index e99222bab589..14da16ad627a 100644
--- a/gas/config/tc-sparc.h
+++ b/gas/config/tc-sparc.h
@@ -1,6 +1,6 @@
 /* tc-sparc.h - Macros and type defines for the sparc.
    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,15 +16,13 @@
 
    You should have received a copy of the GNU General Public
    License along with GAS; see the file COPYING.  If not, write
-   to the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   to the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #ifndef TC_SPARC
 #define TC_SPARC 1
 
-#ifdef ANSI_PROTOTYPES
 struct frag;
-#endif
 
 /* This is used to set the default value for `target_big_endian'.  */
 #define TARGET_BYTES_BIG_ENDIAN 1
@@ -39,13 +37,6 @@ extern const char *sparc_target_format PARAMS ((void));
 #define RELOC_EXPANSION_POSSIBLE
 #define MAX_RELOC_EXPANSION 2
 
-#if 0
-#ifdef TE_SPARCAOUT
-/* Bi-endian support may eventually be unconditional, but until things are
-   working well it's only provided for targets that need it.  */
-#define SPARC_BIENDIAN
-#endif
-#endif
 /* Make it unconditional and check if -EL is valid after option parsing */
 #define SPARC_BIENDIAN
 
@@ -116,7 +107,7 @@ extern void sparc_handle_align PARAMS ((struct frag *));
 		       == S_GET_SEGMENT ((FIX)->fx_addsy)))		\
 	       || S_IS_LOCAL ((FIX)->fx_addsy)))))
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 /* Finish up the entire symtab.  */
diff --git a/gas/config/tc-tahoe.c b/gas/config/tc-tahoe.c
deleted file mode 100644
index 4bc75ea2c727..000000000000
--- a/gas/config/tc-tahoe.c
+++ /dev/null
@@ -1,2013 +0,0 @@
-/* This file is tc-tahoe.c
-
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1995, 2000, 2001, 2002
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-#include "as.h"
-#include "safe-ctype.h"
-#include "obstack.h"
-
-/* This bit glommed from tahoe-inst.h.  */
-
-typedef unsigned char byte;
-typedef byte tahoe_opcodeT;
-
-/* This is part of tahoe-ins-parse.c & friends.
-   We want to parse a tahoe instruction text into a tree defined here.  */
-
-#define TIT_MAX_OPERANDS (4)	/* maximum number of operands in one
-				   single tahoe instruction */
-
-struct top			/* tahoe instruction operand */
-  {
-    int top_ndx;		/* -1, or index register. eg 7=[R7] */
-    int top_reg;		/* -1, or register number. eg 7 = R7 or (R7) */
-    byte top_mode;		/* Addressing mode byte. This byte, defines
-				   which of the 11 modes opcode is.  */
-
-    char top_access;		/* Access type wanted for this operand
-				   'b'branch ' 'no-instruction 'amrvw' */
-    char top_width;		/* Operand width expected, one of "bwlq?-:!" */
-
-    char * top_error;		/* Say if operand is inappropriate         */
-
-    segT seg_of_operand;	/* segment as returned by expression()*/
-
-    expressionS exp_of_operand;	/* The expression as parsed by expression()*/
-
-    byte top_dispsize;		/* Number of bytes in the displacement if we
-				   can figure it out */
-  };
-
-/* The addressing modes for an operand. These numbers are the actual values
-   for certain modes, so be careful if you screw with them.  */
-#define TAHOE_DIRECT_REG (0x50)
-#define TAHOE_REG_DEFERRED (0x60)
-
-#define TAHOE_REG_DISP (0xE0)
-#define TAHOE_REG_DISP_DEFERRED (0xF0)
-
-#define TAHOE_IMMEDIATE (0x8F)
-#define TAHOE_IMMEDIATE_BYTE (0x88)
-#define TAHOE_IMMEDIATE_WORD (0x89)
-#define TAHOE_IMMEDIATE_LONGWORD (0x8F)
-#define TAHOE_ABSOLUTE_ADDR (0x9F)
-
-#define TAHOE_DISPLACED_RELATIVE (0xEF)
-#define TAHOE_DISP_REL_DEFERRED (0xFF)
-
-#define TAHOE_AUTO_DEC (0x7E)
-#define TAHOE_AUTO_INC (0x8E)
-#define TAHOE_AUTO_INC_DEFERRED (0x9E)
-/* INDEXED_REG is decided by the existence or lack of a [reg].  */
-
-/* These are encoded into top_width when top_access=='b'
-   and it's a psuedo op.  */
-#define TAHOE_WIDTH_ALWAYS_JUMP      '-'
-#define TAHOE_WIDTH_CONDITIONAL_JUMP '?'
-#define TAHOE_WIDTH_BIG_REV_JUMP     '!'
-#define TAHOE_WIDTH_BIG_NON_REV_JUMP ':'
-
-/* The hex code for certain tahoe commands and modes.
-   This is just for readability.  */
-#define TAHOE_JMP (0x71)
-#define TAHOE_PC_REL_LONG (0xEF)
-#define TAHOE_BRB (0x11)
-#define TAHOE_BRW (0x13)
-/* These, when 'ored' with, or added to, a register number,
-   set up the number for the displacement mode.  */
-#define TAHOE_PC_OR_BYTE (0xA0)
-#define TAHOE_PC_OR_WORD (0xC0)
-#define TAHOE_PC_OR_LONG (0xE0)
-
-struct tit			/* Get it out of the sewer, it stands for
-				   tahoe instruction tree (Geeze!).  */
-{
-  tahoe_opcodeT tit_opcode;	/* The opcode.  */
-  byte tit_operands;		/* How many operands are here.  */
-  struct top tit_operand[TIT_MAX_OPERANDS];	/* Operands */
-  char *tit_error;		/* "" or fatal error text */
-};
-
-/* end: tahoe-inst.h */
-
-/* tahoe.c - tahoe-specific -
-   Not part of gas yet.
-   */
-
-#include "opcode/tahoe.h"
-
-/* This is the number to put at the beginning of the a.out file */
-long omagic = OMAGIC;
-
-/* These chars start a comment anywhere in a source file (except inside
-   another comment or a quoted string.  */
-const char comment_chars[] = "#;";
-
-/* These chars only start a comment at the beginning of a line.  */
-const char line_comment_chars[] = "#";
-
-/* Chars that can be used to separate mant from exp in floating point nums */
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant
-   as in 0f123.456
-   or    0d1.234E-12 (see exp chars above)
-   Note: The Tahoe port doesn't support floating point constants. This is
-         consistent with 'as' If it's needed, I can always add it later.  */
-const char FLT_CHARS[] = "df";
-
-/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
-   changed in read.c .  Ideally it shouldn't have to know about it at all,
-   but nothing is ideal around here.
-   (The tahoe has plenty of room, so the change currently isn't needed.)
-   */
-
-static struct tit t;		/* A tahoe instruction after decoding.  */
-
-void float_cons ();
-/* A table of pseudo ops (sans .), the function called, and an integer op
-   that the function is called with.  */
-
-const pseudo_typeS md_pseudo_table[] =
-{
-  {"dfloat", float_cons, 'd'},
-  {"ffloat", float_cons, 'f'},
-  {0}
-};
-
-/*
- * For Tahoe, relative addresses of "just the right length" are pretty easy.
- * The branch displacement is always the last operand, even in
- * synthetic instructions.
- * For Tahoe, we encode the relax_substateTs (in e.g. fr_substate) as:
- *
- *		    4       3       2       1       0	     bit number
- *	---/ /--+-------+-------+-------+-------+-------+
- *		|     what state ?	|  how long ?	|
- *	---/ /--+-------+-------+-------+-------+-------+
- *
- * The "how long" bits are 00=byte, 01=word, 10=long.
- * This is a Un*x convention.
- * Not all lengths are legit for a given value of (what state).
- * The four states are listed below.
- * The "how long" refers merely to the displacement length.
- * The address usually has some constant bytes in it as well.
- *
-
-States for Tahoe address relaxing.
-1.	TAHOE_WIDTH_ALWAYS_JUMP (-)
-	Format: "b-"
-	Tahoe opcodes are:	(Hex)
-		jr		11
-		jbr		11
-	Simple branch.
-	Always, 1 byte opcode, then displacement/absolute.
-	If word or longword, change opcode to brw or jmp.
-
-2.	TAHOE_WIDTH_CONDITIONAL_JUMP (?)
-	J<cond> where <cond> is a simple flag test.
-	Format: "b?"
-	Tahoe opcodes are:	(Hex)
-		jneq/jnequ	21
-		jeql/jeqlu	31
-		jgtr		41
-		jleq		51
-		jgeq		81
-		jlss		91
-		jgtru		a1
-		jlequ		b1
-		jvc		c1
-		jvs		d1
-		jlssu/jcs	e1
-		jgequ/jcc	f1
-	Always, you complement 4th bit to reverse the condition.
-	Always, 1-byte opcode, then 1-byte displacement.
-
-3.	TAHOE_WIDTH_BIG_REV_JUMP (!)
-	Jbc/Jbs where cond tests a memory bit.
-	Format: "rlvlb!"
-	Tahoe opcodes are:	(Hex)
-		jbs		0e
-		jbc		1e
-	Always, you complement 4th bit to reverse the condition.
-	Always, 1-byte opcde, longword, longword-address, 1-word-displacement
-
-4.	TAHOE_WIDTH_BIG_NON_REV_JUMP (:)
-	JaoblXX/Jbssi
-	Format: "rlmlb:"
-	Tahoe opcodes are:	(Hex)
-		aojlss		2f
-		jaoblss		2f
-		aojleq		3f
-		jaobleq		3f
-		jbssi		5f
-	Always, we cannot reverse the sense of the branch; we have a word
-	displacement.
-
-We need to modify the opcode is for class 1, 2 and 3 instructions.
-After relax() we may complement the 4th bit of 2 or 3 to reverse sense of
-branch.
-
-We sometimes store context in the operand literal. This way we can figure out
-after relax() what the original addressing mode was. (Was is pc_rel, or
-pc_rel_disp? That sort of thing.) */
-
-/* These displacements are relative to the START address of the
-   displacement which is at the start of the displacement, not the end of
-   the instruction. The hardware pc_rel is at the end of the instructions.
-   That's why all the displacements have the length of the displacement added
-   to them. (WF + length(word))
-
-   The first letter is Byte, Word.
-   2nd letter is Forward, Backward.  */
-#define BF (1+ 127)
-#define BB (1+-128)
-#define WF (2+ 32767)
-#define WB (2+-32768)
-/* Dont need LF, LB because they always reach. [They are coded as 0.] */
-
-#define C(a,b) ENCODE_RELAX(a,b)
-/* This macro has no side-effects.  */
-#define ENCODE_RELAX(what,length) (((what) << 2) + (length))
-#define RELAX_STATE(s) ((s) >> 2)
-#define RELAX_LENGTH(s) ((s) & 3)
-
-#define STATE_ALWAYS_BRANCH             (1)
-#define STATE_CONDITIONAL_BRANCH        (2)
-#define STATE_BIG_REV_BRANCH            (3)
-#define STATE_BIG_NON_REV_BRANCH        (4)
-#define STATE_PC_RELATIVE		(5)
-
-#define STATE_BYTE                      (0)
-#define STATE_WORD                      (1)
-#define STATE_LONG                      (2)
-#define STATE_UNDF                      (3)	/* Symbol undefined in pass1 */
-
-/* This is the table used by gas to figure out relaxing modes. The fields are
-   forward_branch reach, backward_branch reach, number of bytes it would take,
-   where the next biggest branch is.  */
-const relax_typeS md_relax_table[] =
-{
-  {
-    1, 1, 0, 0
-  },				/* error sentinel   0,0	*/
-  {
-    1, 1, 0, 0
-  },				/* unused	    0,1	*/
-  {
-    1, 1, 0, 0
-  },				/* unused	    0,2	*/
-  {
-    1, 1, 0, 0
-  },				/* unused	    0,3	*/
-/* Unconditional branch cases "jrb"
-     The relax part is the actual displacement */
-  {
-    BF, BB, 1, C (1, 1)
-  },				/* brb B`foo	    1,0 */
-  {
-    WF, WB, 2, C (1, 2)
-  },				/* brw W`foo	    1,1 */
-  {
-    0, 0, 5, 0
-  },				/* Jmp L`foo	    1,2 */
-  {
-    1, 1, 0, 0
-  },				/* unused	    1,3 */
-/* Reversible Conditional Branch. If the branch won't reach, reverse
-     it, and jump over a brw or a jmp that will reach. The relax part is the
-     actual address.  */
-  {
-    BF, BB, 1, C (2, 1)
-  },				/* b<cond> B`foo    2,0 */
-  {
-    WF + 2, WB + 2, 4, C (2, 2)
-  },				/* brev over, brw W`foo, over: 2,1 */
-  {
-    0, 0, 7, 0
-  },				/* brev over, jmp L`foo, over: 2,2 */
-  {
-    1, 1, 0, 0
-  },				/* unused	    2,3 */
-/* Another type of reversible branch. But this only has a word
-     displacement.  */
-  {
-    1, 1, 0, 0
-  },				/* unused	    3,0 */
-  {
-    WF, WB, 2, C (3, 2)
-  },				/* jbX W`foo	    3,1 */
-  {
-    0, 0, 8, 0
-  },				/* jrevX over, jmp L`foo, over:  3,2 */
-  {
-    1, 1, 0, 0
-  },				/* unused	    3,3 */
-/* These are the non reversible branches, all of which have a word
-     displacement. If I can't reach, branch over a byte branch, to a
-     jump that will reach. The jumped branch jumps over the reaching
-     branch, to continue with the flow of the program. It's like playing
-     leap frog.  */
-  {
-    1, 1, 0, 0
-  },				/* unused	    4,0 */
-  {
-    WF, WB, 2, C (4, 2)
-  },				/* aobl_ W`foo	    4,1 */
-  {
-    0, 0, 10, 0
-  },				/*aobl_ W`hop,br over,hop: jmp L^foo,over 4,2*/
-  {
-    1, 1, 0, 0
-  },				/* unused	    4,3 */
-/* Normal displacement mode, no jumping or anything like that.
-     The relax points to one byte before the address, thats why all
-     the numbers are up by one.  */
-  {
-    BF + 1, BB + 1, 2, C (5, 1)
-  },				/* B^"foo"	    5,0 */
-  {
-    WF + 1, WB + 1, 3, C (5, 2)
-  },				/* W^"foo"	    5,1 */
-  {
-    0, 0, 5, 0
-  },				/* L^"foo"	    5,2 */
-  {
-    1, 1, 0, 0
-  },				/* unused	    5,3 */
-};
-
-#undef C
-#undef BF
-#undef BB
-#undef WF
-#undef WB
-/* End relax stuff */
-
-/* Handle of the OPCODE hash table.  NULL means any use before
-   md_begin() will crash.  */
-static struct hash_control *op_hash;
-
-/* Init function. Build the hash table.  */
-void
-md_begin ()
-{
-  struct tot *tP;
-  char *errorval = 0;
-  int synthetic_too = 1;	/* If 0, just use real opcodes.  */
-
-  op_hash = hash_new ();
-
-  for (tP = totstrs; *tP->name && !errorval; tP++)
-    errorval = hash_insert (op_hash, tP->name, &tP->detail);
-
-  if (synthetic_too)
-    for (tP = synthetic_totstrs; *tP->name && !errorval; tP++)
-      errorval = hash_insert (op_hash, tP->name, &tP->detail);
-
-  if (errorval)
-    as_fatal (errorval);
-}
-
-const char *md_shortopts = "ad:STt:V";
-struct option md_longopts[] = {
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
-{
-  switch (c)
-    {
-    case 'a':
-      as_warn (_("The -a option doesn't exist. (Despite what the man page says!"));
-      break;
-
-    case 'd':
-      as_warn (_("Displacement length %s ignored!"), arg);
-      break;
-
-    case 'S':
-      as_warn (_("SYMBOL TABLE not implemented"));
-      break;
-
-    case 'T':
-      as_warn (_("TOKEN TRACE not implemented"));
-      break;
-
-    case 't':
-      as_warn (_("I don't need or use temp. file \"%s\"."), arg);
-      break;
-
-    case 'V':
-      as_warn (_("I don't use an interpass file! -V ignored"));
-      break;
-
-    default:
-      return 0;
-    }
-
-  return 1;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream;
-{
-  fprintf (stream, _("\
-Tahoe options:\n\
--a			ignored\n\
--d LENGTH		ignored\n\
--J			ignored\n\
--S			ignored\n\
--t FILE			ignored\n\
--T			ignored\n\
--V			ignored\n"));
-}
-
-/* The functions in this section take numbers in the machine format, and
-   munges them into Tahoe byte order.
-   They exist primarily for cross assembly purpose.  */
-void				/* Knows about order of bytes in address.  */
-md_number_to_chars (con, value, nbytes)
-     char con[];		/* Return 'nbytes' of chars here.  */
-     valueT value;		/* The value of the bits.  */
-     int nbytes;		/* Number of bytes in the output.  */
-{
-  number_to_chars_bigendian (con, value, nbytes);
-}
-
-#ifdef comment
-void				/* Knows about order of bytes in address.  */
-md_number_to_imm (con, value, nbytes)
-     char con[];		/* Return 'nbytes' of chars here.  */
-     long int value;		/* The value of the bits.  */
-     int nbytes;		/* Number of bytes in the output.  */
-{
-  md_number_to_chars (con, value, nbytes);
-}
-
-#endif /* comment */
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP ATTRIBUTE_UNUSED;
-     valueT * valP ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED:
-{
-  /* Should never be called.  */
-  know (0);
-}
-
-void				/* Knows about order of bytes in address.  */
-md_number_to_disp (con, value, nbytes)
-     char con[];		/* Return 'nbytes' of chars here.  */
-     long int value;		/* The value of the bits.  */
-     int nbytes;		/* Number of bytes in the output.  */
-{
-  md_number_to_chars (con, value, nbytes);
-}
-
-void				/* Knows about order of bytes in address.  */
-md_number_to_field (con, value, nbytes)
-     char con[];		/* Return 'nbytes' of chars here.  */
-     long int value;		/* The value of the bits.  */
-     int nbytes;		/* Number of bytes in the output.  */
-{
-  md_number_to_chars (con, value, nbytes);
-}
-
-/* Put the bits in an order that a tahoe will understand, despite the ordering
-   of the native machine.
-   On Tahoe: first 4 bytes are normal unsigned big endian long,
-   next three bytes are symbolnum, in kind of 3 byte big endian (least sig. byte last).
-   The last byte is broken up with bit 7 as pcrel,
-   	bits 6 & 5 as length,
-	bit 4 as extern and the last nibble as 'undefined'.  */
-
-#if comment
-void
-md_ri_to_chars (ri_p, ri)
-     struct relocation_info *ri_p, ri;
-{
-  byte the_bytes[sizeof (struct relocation_info)];
-  /* The reason I can't just encode these directly into ri_p is that
-     ri_p may point to ri.  */
-
-  /* This is easy */
-  md_number_to_chars (the_bytes, ri.r_address, sizeof (ri.r_address));
-
-  /* now the fun stuff */
-  the_bytes[4] = (ri.r_symbolnum >> 16) & 0x0ff;
-  the_bytes[5] = (ri.r_symbolnum >> 8) & 0x0ff;
-  the_bytes[6] = ri.r_symbolnum & 0x0ff;
-  the_bytes[7] = (((ri.r_extern << 4) & 0x10) | ((ri.r_length << 5) & 0x60) |
-		  ((ri.r_pcrel << 7) & 0x80)) & 0xf0;
-
-  bcopy (the_bytes, (char *) ri_p, sizeof (struct relocation_info));
-}
-
-#endif /* comment */
-
-/* Put the bits in an order that a tahoe will understand, despite the ordering
-   of the native machine.
-   On Tahoe: first 4 bytes are normal unsigned big endian long,
-   next three bytes are symbolnum, in kind of 3 byte big endian (least sig. byte last).
-   The last byte is broken up with bit 7 as pcrel,
-   	bits 6 & 5 as length,
-	bit 4 as extern and the last nibble as 'undefined'.  */
-
-void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
-{
-  long r_symbolnum;
-
-  know (fixP->fx_addsy != NULL);
-
-  md_number_to_chars (where,
-       fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
-		      4);
-
-  r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
-		 ? S_GET_TYPE (fixP->fx_addsy)
-		 : fixP->fx_addsy->sy_number);
-
-  where[4] = (r_symbolnum >> 16) & 0x0ff;
-  where[5] = (r_symbolnum >> 8) & 0x0ff;
-  where[6] = r_symbolnum & 0x0ff;
-  where[7] = (((is_pcrel (fixP) << 7) & 0x80)
-	      | ((((fixP->fx_type == FX_8 || fixP->fx_type == FX_PCREL8
-		    ? 0
-		    : (fixP->fx_type == FX_16 || fixP->fx_type == FX_PCREL16
-		       ? 1
-		    : (fixP->fx_type == FX_32 || fixP->fx_type == FX_PCREL32
-		       ? 2
-		       : 42)))) << 5) & 0x60)
-	      | ((!S_IS_DEFINED (fixP->fx_addsy) << 4) & 0x10));
-}
-
-/* Relocate byte stuff */
-
-/* This is for broken word.  */
-const int md_short_jump_size = 3;
-
-void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag;
-     symbolS *to_symbol;
-{
-  valueT offset;
-
-  offset = to_addr - (from_addr + 1);
-  *ptr++ = TAHOE_BRW;
-  md_number_to_chars (ptr, offset, 2);
-}
-
-const int md_long_jump_size = 6;
-const int md_reloc_size = 8;	/* Size of relocation record */
-
-void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr, to_addr;
-     fragS *frag;
-     symbolS *to_symbol;
-{
-  valueT offset;
-
-  offset = to_addr - (from_addr + 4);
-  *ptr++ = TAHOE_JMP;
-  *ptr++ = TAHOE_PC_REL_LONG;
-  md_number_to_chars (ptr, offset, 4);
-}
-
-/* md_estimate_size_before_relax(), called just before relax().
-   Any symbol that is now undefined will not become defined.
-   Return the correct fr_subtype in the frag and the growth beyond
-   fr_fix.  */
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS *fragP;
-     segT segment_type;		/* N_DATA or N_TEXT.  */
-{
-  if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF)
-    {
-      if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
-	{
-	  /* Non-relaxable cases.  */
-	  char *p;
-	  int old_fr_fix;
-
-	  old_fr_fix = fragP->fr_fix;
-	  p = fragP->fr_literal + old_fr_fix;
-	  switch (RELAX_STATE (fragP->fr_subtype))
-	    {
-	    case STATE_PC_RELATIVE:
-	      *p |= TAHOE_PC_OR_LONG;
-	      /* We now know how big it will be, one long word.  */
-	      fragP->fr_fix += 1 + 4;
-	      fix_new (fragP, old_fr_fix + 1, fragP->fr_symbol,
-		       fragP->fr_offset, FX_PCREL32, NULL);
-	      break;
-
-	    case STATE_CONDITIONAL_BRANCH:
-	      *fragP->fr_opcode ^= 0x10;	/* Reverse sense of branch.  */
-	      *p++ = 6;
-	      *p++ = TAHOE_JMP;
-	      *p++ = TAHOE_PC_REL_LONG;
-	      fragP->fr_fix += 1 + 1 + 1 + 4;
-	      fix_new (fragP, old_fr_fix + 3, fragP->fr_symbol,
-		       fragP->fr_offset, FX_PCREL32, NULL);
-	      break;
-
-	    case STATE_BIG_REV_BRANCH:
-	      *fragP->fr_opcode ^= 0x10;	/* Reverse sense of branch.  */
-	      *p++ = 0;
-	      *p++ = 6;
-	      *p++ = TAHOE_JMP;
-	      *p++ = TAHOE_PC_REL_LONG;
-	      fragP->fr_fix += 2 + 2 + 4;
-	      fix_new (fragP, old_fr_fix + 4, fragP->fr_symbol,
-		       fragP->fr_offset, FX_PCREL32, NULL);
-	      break;
-
-	    case STATE_BIG_NON_REV_BRANCH:
-	      *p++ = 2;
-	      *p++ = 0;
-	      *p++ = TAHOE_BRB;
-	      *p++ = 6;
-	      *p++ = TAHOE_JMP;
-	      *p++ = TAHOE_PC_REL_LONG;
-	      fragP->fr_fix += 2 + 2 + 2 + 4;
-	      fix_new (fragP, old_fr_fix + 6, fragP->fr_symbol,
-		       fragP->fr_offset, FX_PCREL32, NULL);
-	      break;
-
-	    case STATE_ALWAYS_BRANCH:
-	      *fragP->fr_opcode = TAHOE_JMP;
-	      *p++ = TAHOE_PC_REL_LONG;
-	      fragP->fr_fix += 1 + 4;
-	      fix_new (fragP, old_fr_fix + 1, fragP->fr_symbol,
-		       fragP->fr_offset, FX_PCREL32, NULL);
-	      break;
-
-	    default:
-	      abort ();
-	    }
-	  frag_wane (fragP);
-
-	  /* Return the growth in the fixed part of the frag.  */
-	  return fragP->fr_fix - old_fr_fix;
-	}
-
-      /* Relaxable cases.  Set up the initial guess for the variable
-	 part of the frag.  */
-      switch (RELAX_STATE (fragP->fr_subtype))
-	{
-	case STATE_PC_RELATIVE:
-	  fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE);
-	  break;
-	case STATE_CONDITIONAL_BRANCH:
-	  fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE);
-	  break;
-	case STATE_BIG_REV_BRANCH:
-	  fragP->fr_subtype = ENCODE_RELAX (STATE_BIG_REV_BRANCH, STATE_WORD);
-	  break;
-	case STATE_BIG_NON_REV_BRANCH:
-	  fragP->fr_subtype = ENCODE_RELAX (STATE_BIG_NON_REV_BRANCH, STATE_WORD);
-	  break;
-	case STATE_ALWAYS_BRANCH:
-	  fragP->fr_subtype = ENCODE_RELAX (STATE_ALWAYS_BRANCH, STATE_BYTE);
-	  break;
-	}
-    }
-
-  if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
-    abort ();
-
-  /* Return the size of the variable part of the frag.  */
-  return md_relax_table[fragP->fr_subtype].rlx_length;
-}
-
-/*
- *			md_convert_frag();
- *
- * Called after relax() is finished.
- * In:	Address of frag.
- *	fr_type == rs_machine_dependent.
- *	fr_subtype is what the address relaxed to.
- *
- * Out:	Any fixSs and constants are set up.
- *	Caller will turn frag into a ".space 0".
- */
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers;
-     segT seg;
-     register fragS *fragP;
-{
-  register char *addressP;	/* -> _var to change.  */
-  register char *opcodeP;	/* -> opcode char(s) to change.  */
-  register short int extension = 0;	/* Size of relaxed address.
-				   Added to fr_fix: incl. ALL var chars.  */
-  register symbolS *symbolP;
-  register long int where;
-  register long int address_of_var;
-  /* Where, in file space, is _var of *fragP? */
-  register long int target_address;
-  /* Where, in file space, does addr point? */
-
-  know (fragP->fr_type == rs_machine_dependent);
-  where = fragP->fr_fix;
-  addressP = fragP->fr_literal + where;
-  opcodeP = fragP->fr_opcode;
-  symbolP = fragP->fr_symbol;
-  know (symbolP);
-  target_address = S_GET_VALUE (symbolP) + fragP->fr_offset;
-  address_of_var = fragP->fr_address + where;
-  switch (fragP->fr_subtype)
-    {
-    case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
-      /* *addressP holds the registers number, plus 0x10, if it's deferred
-       mode. To set up the right mode, just OR the size of this displacement */
-      /* Byte displacement.  */
-      *addressP++ |= TAHOE_PC_OR_BYTE;
-      *addressP = target_address - (address_of_var + 2);
-      extension = 2;
-      break;
-
-    case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD):
-      /* Word displacement.  */
-      *addressP++ |= TAHOE_PC_OR_WORD;
-      md_number_to_chars (addressP, target_address - (address_of_var + 3), 2);
-      extension = 3;
-      break;
-
-    case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_LONG):
-      /* Long word displacement.  */
-      *addressP++ |= TAHOE_PC_OR_LONG;
-      md_number_to_chars (addressP, target_address - (address_of_var + 5), 4);
-      extension = 5;
-      break;
-
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE):
-      *addressP = target_address - (address_of_var + 1);
-      extension = 1;
-      break;
-
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD):
-      *opcodeP ^= 0x10;		/* Reverse sense of test.  */
-      *addressP++ = 3;		/* Jump over word branch */
-      *addressP++ = TAHOE_BRW;
-      md_number_to_chars (addressP, target_address - (address_of_var + 4), 2);
-      extension = 4;
-      break;
-
-    case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_LONG):
-      *opcodeP ^= 0x10;		/* Reverse sense of test.  */
-      *addressP++ = 6;
-      *addressP++ = TAHOE_JMP;
-      *addressP++ = TAHOE_PC_REL_LONG;
-      md_number_to_chars (addressP, target_address, 4);
-      extension = 7;
-      break;
-
-    case ENCODE_RELAX (STATE_ALWAYS_BRANCH, STATE_BYTE):
-      *addressP = target_address - (address_of_var + 1);
-      extension = 1;
-      break;
-
-    case ENCODE_RELAX (STATE_ALWAYS_BRANCH, STATE_WORD):
-      *opcodeP = TAHOE_BRW;
-      md_number_to_chars (addressP, target_address - (address_of_var + 2), 2);
-      extension = 2;
-      break;
-
-    case ENCODE_RELAX (STATE_ALWAYS_BRANCH, STATE_LONG):
-      *opcodeP = TAHOE_JMP;
-      *addressP++ = TAHOE_PC_REL_LONG;
-      md_number_to_chars (addressP, target_address - (address_of_var + 5), 4);
-      extension = 5;
-      break;
-
-    case ENCODE_RELAX (STATE_BIG_REV_BRANCH, STATE_WORD):
-      md_number_to_chars (addressP, target_address - (address_of_var + 2), 2);
-      extension = 2;
-      break;
-
-    case ENCODE_RELAX (STATE_BIG_REV_BRANCH, STATE_LONG):
-      *opcodeP ^= 0x10;
-      *addressP++ = 0;
-      *addressP++ = 6;
-      *addressP++ = TAHOE_JMP;
-      *addressP++ = TAHOE_PC_REL_LONG;
-      md_number_to_chars (addressP, target_address, 4);
-      extension = 8;
-      break;
-
-    case ENCODE_RELAX (STATE_BIG_NON_REV_BRANCH, STATE_WORD):
-      md_number_to_chars (addressP, target_address - (address_of_var + 2), 2);
-      extension = 2;
-      break;
-
-    case ENCODE_RELAX (STATE_BIG_NON_REV_BRANCH, STATE_LONG):
-      *addressP++ = 0;
-      *addressP++ = 2;
-      *addressP++ = TAHOE_BRB;
-      *addressP++ = 6;
-      *addressP++ = TAHOE_JMP;
-      *addressP++ = TAHOE_PC_REL_LONG;
-      md_number_to_chars (addressP, target_address, 4);
-      extension = 10;
-      break;
-
-    default:
-      BAD_CASE (fragP->fr_subtype);
-      break;
-    }
-  fragP->fr_fix += extension;
-}				/* md_convert_frag */
-
-
-/* This is the stuff for md_assemble.  */
-#define FP_REG 13
-#define SP_REG 14
-#define PC_REG 15
-#define BIGGESTREG PC_REG
-
-/*
- * Parse the string pointed to by START
- * If it represents a valid register, point START to the character after
- * the last valid register char, and return the register number (0-15).
- * If invalid, leave START alone, return -1.
- * The format has to be exact. I don't do things like eat leading zeros
- * or the like.
- * Note: This doesn't check for the next character in the string making
- * this invalid. Ex: R123 would return 12, it's the callers job to check
- * what start is point to apon return.
- *
- * Valid registers are R1-R15, %1-%15, FP (13), SP (14), PC (15)
- * Case doesn't matter.
- */
-int
-tahoe_reg_parse (start)
-     char **start;		/* A pointer to the string to parse.  */
-{
-  register char *regpoint = *start;
-  register int regnum = -1;
-
-  switch (*regpoint++)
-    {
-    case '%':			/* Registers can start with a %,
-				   R or r, and then a number.  */
-    case 'R':
-    case 'r':
-      if (ISDIGIT (*regpoint))
-	{
-	  /* Got the first digit.  */
-	  regnum = *regpoint++ - '0';
-	  if ((regnum == 1) && ISDIGIT (*regpoint))
-	    {
-	      /* Its a two digit number.  */
-	      regnum = 10 + (*regpoint++ - '0');
-	      if (regnum > BIGGESTREG)
-		{		/* Number too big? */
-		  regnum = -1;
-		}
-	    }
-	}
-      break;
-    case 'F':			/* Is it the FP */
-    case 'f':
-      switch (*regpoint++)
-	{
-	case 'p':
-	case 'P':
-	  regnum = FP_REG;
-	}
-      break;
-    case 's':			/* How about the SP */
-    case 'S':
-      switch (*regpoint++)
-	{
-	case 'p':
-	case 'P':
-	  regnum = SP_REG;
-	}
-      break;
-    case 'p':			/* OR the PC even */
-    case 'P':
-      switch (*regpoint++)
-	{
-	case 'c':
-	case 'C':
-	  regnum = PC_REG;
-	}
-      break;
-    }
-
-  if (regnum != -1)
-    {				/* No error, so move string pointer */
-      *start = regpoint;
-    }
-  return regnum;		/* Return results */
-}				/* tahoe_reg_parse */
-
-/*
- * This chops up an operand and figures out its modes and stuff.
- * It's a little touchy about extra characters.
- * Optex to start with one extra character so it can be overwritten for
- * the backward part of the parsing.
- * You can't put a bunch of extra characters in side to
- * make the command look cute. ie: * foo ( r1 ) [  r0 ]
- * If you like doing a lot of typing, try COBOL!
- * Actually, this parser is a little weak all around. It's designed to be
- * used with compliers, so I emphasize correct decoding of valid code quickly
- * rather that catching every possible error.
- * Note: This uses the expression function, so save input_line_pointer before
- * calling.
- *
- * Sperry defines the semantics of address modes (and values)
- * by a two-letter code, explained here.
- *
- *   letter 1:   access type
- *
- *     a         address calculation - no data access, registers forbidden
- *     b         branch displacement
- *     m         read - let go of bus - write back "modify"
- *     r         read
- *     w         write
- *     v         bit field address: like 'a' but registers are OK
- *
- *   letter 2:   data type (i.e. width, alignment)
- *
- *     b         byte
- *     w         word
- *     l         longword
- *     q         quadword (Even regs < 14 allowed) (if 12, you get a warning)
- *     -	 unconditional synthetic jbr operand
- *     ?	 simple synthetic reversible branch operand
- *     !	 complex synthetic reversible branch operand
- *     :	 complex synthetic non-reversible branch operand
- *
- * The '-?!:' letter 2's are not for external consumption. They are used
- * by GAS for psuedo ops relaxing code.
- *
- * After parsing topP has:
- *
- *   top_ndx:        -1, or the index register. eg 7=[R7]
- *   top_reg:        -1, or register number. eg 7 = R7 or (R7)
- *   top_mode:       The addressing mode byte. This byte, defines which of
- *                   the 11 modes opcode is.
- *   top_access:     Access type wanted for this operand 'b'branch ' '
- *                   no-instruction 'amrvw'
- *   top_width:      Operand width expected, one of "bwlq?-:!"
- *   exp_of_operand: The expression as parsed by expression()
- *   top_dispsize:   Number of bytes in the displacement if we can figure it
- *                   out and it's relevant.
- *
- * Need syntax checks built.
- */
-
-void
-tip_op (optex, topP)
-     char *optex;		/* The users text input, with one leading character */
-     struct top *topP;		/* The tahoe instruction with some fields already set:
-			 in: access, width
-			 out: ndx, reg, mode, error, dispsize */
-
-{
-  int mode = 0;			/* This operand's mode.  */
-  char segfault = *optex;	/* To keep the back parsing from freaking.  */
-  char *point = optex + 1;	/* Parsing from front to back.  */
-  char *end;			/* Parsing from back to front.  */
-  int reg = -1;			/* major register, -1 means absent */
-  int imreg = -1;		/* Major register in immediate mode */
-  int ndx = -1;			/* index register number, -1 means absent */
-  char dec_inc = ' ';		/* Is the SP auto-incremented '+' or
-				   auto-decremented '-' or neither ' '.  */
-  int immediate = 0;		/* 1 if '$' immediate mode */
-  int call_width = 0;		/* If the caller casts the displacement */
-  int abs_width = 0;		/* The width of the absolute displacement */
-  int com_width = 0;		/* Displacement width required by branch */
-  int deferred = 0;		/* 1 if '*' deferral is used */
-  byte disp_size = 0;		/* How big is this operand. 0 == don't know */
-  char *op_bad = "";		/* Bad operand error */
-
-  char *tp, *temp, c;		/* Temporary holders */
-
-  char access = topP->top_access;	/* Save on a deref.  */
-  char width = topP->top_width;
-
-  int really_none = 0;		/* Empty expressions evaluate to 0
-				   but I need to know if it's there or not */
-  expressionS *expP;		/* -> expression values for this operand */
-
-  /* Does this command restrict the displacement size.  */
-  if (access == 'b')
-    com_width = (width == 'b' ? 1 :
-		 (width == 'w' ? 2 :
-		  (width == 'l' ? 4 : 0)));
-
-  *optex = '\0';		/* This is kind of a back stop for all
-				   the searches to fail on if needed.*/
-  if (*point == '*')
-    {				/* A dereference? */
-      deferred = 1;
-      point++;
-    }
-
-  /* Force words into a certain mode */
-  /* Bitch, Bitch, Bitch! */
-  /*
-   * Using the ^ operator is ambiguous. If I have an absolute label
-   * called 'w' set to, say 2, and I have the expression 'w^1', do I get
-   * 1, forced to be in word displacement mode, or do I get the value of
-   * 'w' or'ed with 1 (3 in this case).
-   * The default is 'w' as an offset, so that's what I use.
-   * Stick with `, it does the same, and isn't ambig.
-   */
-
-  if (*point != '\0' && ((point[1] == '^') || (point[1] == '`')))
-    switch (*point)
-      {
-      case 'b':
-      case 'B':
-      case 'w':
-      case 'W':
-      case 'l':
-      case 'L':
-	if (com_width)
-	  as_warn (_("Casting a branch displacement is bad form, and is ignored."));
-	else
-	  {
-	    c = TOLOWER (*point);
-	    call_width = ((c == 'b') ? 1 :
-			  ((c == 'w') ? 2 : 4));
-	  }
-	point += 2;
-	break;
-      }
-
-  /* Setting immediate mode */
-  if (*point == '$')
-    {
-      immediate = 1;
-      point++;
-    }
-
-  /*
-   * I've pulled off all the easy stuff off the front, move to the end and
-   * yank.
-   */
-
-  for (end = point; *end != '\0'; end++)	/* Move to the end.  */
-    ;
-
-  if (end != point)		/* Null string? */
-    end--;
-
-  if (end > point && *end == ' ' && end[-1] != '\'')
-    end--;			/* Hop white space */
-
-  /* Is this an index reg.  */
-  if ((*end == ']') && (end[-1] != '\''))
-    {
-      temp = end;
-
-      /* Find opening brace.  */
-      for (--end; (*end != '[' && end != point); end--)
-	;
-
-      /* If I found the opening brace, get the index register number.  */
-      if (*end == '[')
-	{
-	  tp = end + 1;		/* tp should point to the start of a reg.  */
-	  ndx = tahoe_reg_parse (&tp);
-	  if (tp != temp)
-	    {			/* Reg. parse error.  */
-	      ndx = -1;
-	    }
-	  else
-	    {
-	      end--;		/* Found it, move past brace.  */
-	    }
-	  if (ndx == -1)
-	    {
-	      op_bad = _("Couldn't parse the [index] in this operand.");
-	      end = point;	/* Force all the rest of the tests to fail.  */
-	    }
-	}
-      else
-	{
-	  op_bad = _("Couldn't find the opening '[' for the index of this operand.");
-	  end = point;		/* Force all the rest of the tests to fail.  */
-	}
-    }
-
-  /* Post increment? */
-  if (*end == '+')
-    {
-      dec_inc = '+';
-      /* was:    *end--; */
-      end--;
-    }
-
-  /* register in parens? */
-  if ((*end == ')') && (end[-1] != '\''))
-    {
-      temp = end;
-
-      /* Find opening paren.  */
-      for (--end; (*end != '(' && end != point); end--)
-	;
-
-      /* If I found the opening paren, get the register number.  */
-      if (*end == '(')
-	{
-	  tp = end + 1;
-	  reg = tahoe_reg_parse (&tp);
-	  if (tp != temp)
-	    {
-	      /* Not a register, but could be part of the expression.  */
-	      reg = -1;
-	      end = temp;	/* Rest the pointer back */
-	    }
-	  else
-	    {
-	      end--;		/* Found the reg. move before opening paren.  */
-	    }
-	}
-      else
-	{
-	  op_bad = _("Couldn't find the opening '(' for the deref of this operand.");
-	  end = point;		/* Force all the rest of the tests to fail.  */
-	}
-    }
-
-  /* Pre decrement? */
-  if (*end == '-')
-    {
-      if (dec_inc != ' ')
-	{
-	  op_bad = _("Operand can't be both pre-inc and post-dec.");
-	  end = point;
-	}
-      else
-	{
-	  dec_inc = '-';
-	  /* was:      *end--; */
-	  end--;
-	}
-    }
-
-  /*
-   * Everything between point and end is the 'expression', unless it's
-   * a register name.
-   */
-
-  c = end[1];
-  end[1] = '\0';
-
-  tp = point;
-  imreg = tahoe_reg_parse (&point);	/* Get the immediate register
-				      if it is there.*/
-  if (*point != '\0')
-    {
-      /* If there is junk after point, then the it's not immediate reg.  */
-      point = tp;
-      imreg = -1;
-    }
-
-  if (imreg != -1 && reg != -1)
-    op_bad = _("I parsed 2 registers in this operand.");
-
-  /*
-   * Evaluate whats left of the expression to see if it's valid.
-   * Note again: This assumes that the calling expression has saved
-   * input_line_pointer. (Nag, nag, nag!)
-   */
-
-  if (*op_bad == '\0')
-    {
-      /* Statement has no syntax goofs yet: let's sniff the expression.  */
-      input_line_pointer = point;
-      expP = &(topP->exp_of_operand);
-      topP->seg_of_operand = expression (expP);
-      switch (expP->X_op)
-	{
-	case O_absent:
-	  /* No expression. For BSD4.2 compatibility, missing expression is
-	     absolute 0 */
-	  expP->X_op = O_constant;
-	  expP->X_add_number = 0;
-	  really_none = 1;
-	case O_constant:
-	  /* for SEG_ABSOLUTE, we shouldn't need to set X_op_symbol,
-	     X_add_symbol to any particular value.  */
-	  /* But, we will program defensively. Since this situation occurs
-	     rarely so it costs us little to do so.  */
-	  expP->X_add_symbol = NULL;
-	  expP->X_op_symbol = NULL;
-	  /* How many bytes are needed to express this abs value? */
-	  abs_width =
-	    ((((expP->X_add_number & 0xFFFFFF80) == 0) ||
-	      ((expP->X_add_number & 0xFFFFFF80) == 0xFFFFFF80)) ? 1 :
-	     (((expP->X_add_number & 0xFFFF8000) == 0) ||
-	      ((expP->X_add_number & 0xFFFF8000) == 0xFFFF8000)) ? 2 : 4);
-
-	case O_symbol:
-	  break;
-
-	default:
-	  /*
-	   * Major bug. We can't handle the case of an operator
-	   * expression in a synthetic opcode variable-length
-	   * instruction.  We don't have a frag type that is smart
-	   * enough to relax an operator, and so we just force all
-	   * operators to behave like SEG_PASS1s.  Clearly, if there is
-	   * a demand we can invent a new or modified frag type and
-	   * then coding up a frag for this case will be easy.
-	   */
-	  need_pass_2 = 1;
-	  op_bad = _("Can't relocate expression error.");
-	  break;
-
-	case O_big:
-	  /* This is an error. Tahoe doesn't allow any expressions
-	     bigger that a 32 bit long word. Any bigger has to be referenced
-	     by address.  */
-	  op_bad = _("Expression is too large for a 32 bits.");
-	  break;
-	}
-      if (*input_line_pointer != '\0')
-	{
-	  op_bad = _("Junk at end of expression.");
-	}
-    }
-
-  end[1] = c;
-
-  /* I'm done, so restore optex */
-  *optex = segfault;
-
-  /*
-   * At this point in the game, we (in theory) have all the components of
-   * the operand at least parsed. Now it's time to check for syntax/semantic
-   * errors, and build the mode.
-   * This is what I have:
-   *   deferred = 1 if '*'
-   *   call_width = 0,1,2,4
-   *   abs_width = 0,1,2,4
-   *   com_width = 0,1,2,4
-   *   immediate = 1 if '$'
-   *   ndx = -1 or reg num
-   *   dec_inc = '-' or '+' or ' '
-   *   reg = -1 or reg num
-   *   imreg = -1 or reg num
-   *   topP->exp_of_operand
-   *   really_none
-   */
-  /* Is there a displacement size? */
-  disp_size = (call_width ? call_width :
-	       (com_width ? com_width :
-		abs_width ? abs_width : 0));
-
-  if (*op_bad == '\0')
-    {
-      if (imreg != -1)
-	{
-	  /* Rn */
-	  mode = TAHOE_DIRECT_REG;
-	  if (deferred || immediate || (dec_inc != ' ') ||
-	      (reg != -1) || !really_none)
-	    op_bad = _("Syntax error in direct register mode.");
-	  else if (ndx != -1)
-	    op_bad = _("You can't index a register in direct register mode.");
-	  else if (imreg == SP_REG && access == 'r')
-	    op_bad =
-	      _("SP can't be the source operand with direct register addressing.");
-	  else if (access == 'a')
-	    op_bad = _("Can't take the address of a register.");
-	  else if (access == 'b')
-	    op_bad = _("Direct Register can't be used in a branch.");
-	  else if (width == 'q' && ((imreg % 2) || (imreg > 13)))
-	    op_bad = _("For quad access, the register must be even and < 14.");
-	  else if (call_width)
-	    op_bad = _("You can't cast a direct register.");
-
-	  if (*op_bad == '\0')
-	    {
-	      /* No errors, check for warnings */
-	      if (width == 'q' && imreg == 12)
-		as_warn (_("Using reg 14 for quadwords can tromp the FP register."));
-
-	      reg = imreg;
-	    }
-
-	  /* We know: imm = -1 */
-	}
-      else if (dec_inc == '-')
-	{
-	  /* -(SP) */
-	  mode = TAHOE_AUTO_DEC;
-	  if (deferred || immediate || !really_none)
-	    op_bad = _("Syntax error in auto-dec mode.");
-	  else if (ndx != -1)
-	    op_bad = _("You can't have an index auto dec mode.");
-	  else if (access == 'r')
-	    op_bad = _("Auto dec mode cant be used for reading.");
-	  else if (reg != SP_REG)
-	    op_bad = _("Auto dec only works of the SP register.");
-	  else if (access == 'b')
-	    op_bad = _("Auto dec can't be used in a branch.");
-	  else if (width == 'q')
-	    op_bad = _("Auto dec won't work with quadwords.");
-
-	  /* We know: imm = -1, dec_inc != '-' */
-	}
-      else if (dec_inc == '+')
-	{
-	  if (immediate || !really_none)
-	    op_bad = _("Syntax error in one of the auto-inc modes.");
-	  else if (deferred)
-	    {
-	      /* *(SP)+ */
-	      mode = TAHOE_AUTO_INC_DEFERRED;
-	      if (reg != SP_REG)
-		op_bad = _("Auto inc deferred only works of the SP register.");
-	      else if (ndx != -1)
-		op_bad = _("You can't have an index auto inc deferred mode.");
-	      else if (access == 'b')
-		op_bad = _("Auto inc can't be used in a branch.");
-	    }
-	  else
-	    {
-	      /* (SP)+ */
-	      mode = TAHOE_AUTO_INC;
-	      if (access == 'm' || access == 'w')
-		op_bad = _("You can't write to an auto inc register.");
-	      else if (reg != SP_REG)
-		op_bad = _("Auto inc only works of the SP register.");
-	      else if (access == 'b')
-		op_bad = _("Auto inc can't be used in a branch.");
-	      else if (width == 'q')
-		op_bad = _("Auto inc won't work with quadwords.");
-	      else if (ndx != -1)
-		op_bad = _("You can't have an index in auto inc mode.");
-	    }
-
-	  /* We know: imm = -1, dec_inc == ' ' */
-	}
-      else if (reg != -1)
-	{
-	  if ((ndx != -1) && (reg == SP_REG))
-	    op_bad = _("You can't index the sp register.");
-	  if (deferred)
-	    {
-	      /* *<disp>(Rn) */
-	      mode = TAHOE_REG_DISP_DEFERRED;
-	      if (immediate)
-		op_bad = _("Syntax error in register displaced mode.");
-	    }
-	  else if (really_none)
-	    {
-	      /* (Rn) */
-	      mode = TAHOE_REG_DEFERRED;
-	      /* if reg = SP then cant be indexed */
-	    }
-	  else
-	    {
-	      /* <disp>(Rn) */
-	      mode = TAHOE_REG_DISP;
-	    }
-
-	  /* We know: imm = -1, dec_inc == ' ', Reg = -1 */
-	}
-      else
-	{
-	  if (really_none)
-	    op_bad = _("An offest is needed for this operand.");
-	  if (deferred && immediate)
-	    {
-	      /* *$<ADDR> */
-	      mode = TAHOE_ABSOLUTE_ADDR;
-	      disp_size = 4;
-	    }
-	  else if (immediate)
-	    {
-	      /* $<disp> */
-	      mode = TAHOE_IMMEDIATE;
-	      if (ndx != -1)
-		op_bad = _("You can't index a register in immediate mode.");
-	      if (access == 'a')
-		op_bad = _("Immediate access can't be used as an address.");
-	      /* ponder the wisdom of a cast because it doesn't do any good.  */
-	    }
-	  else if (deferred)
-	    {
-	      /* *<disp> */
-	      mode = TAHOE_DISP_REL_DEFERRED;
-	    }
-	  else
-	    {
-	      /* <disp> */
-	      mode = TAHOE_DISPLACED_RELATIVE;
-	    }
-	}
-    }
-
-  /*
-   * At this point, all the errors we can do have be checked for.
-   * We can build the 'top'.  */
-
-  topP->top_ndx = ndx;
-  topP->top_reg = reg;
-  topP->top_mode = mode;
-  topP->top_error = op_bad;
-  topP->top_dispsize = disp_size;
-}				/* tip_op */
-
-/*
- *                  t i p ( )
- *
- * This converts a string into a tahoe instruction.
- * The string must be a bare single instruction in tahoe (with BSD4 frobs)
- * format.
- * It provides at most one fatal error message (which stops the scan)
- * some warning messages as it finds them.
- * The tahoe instruction is returned in exploded form.
- *
- * The exploded instruction is returned to a struct tit of your choice.
- * #include "tahoe-inst.h" to know what a struct tit is.
- *
- */
-
-static void
-tip (titP, instring)
-     struct tit *titP;		/* We build an exploded instruction here.  */
-     char *instring;		/* Text of a vax instruction: we modify.  */
-{
-  register struct tot_wot *twP = NULL;	/* How to bit-encode this opcode.  */
-  register char *p;		/* 1/skip whitespace.2/scan vot_how */
-  register char *q;		/*  */
-  register unsigned char count;	/* counts number of operands seen */
-  register struct top *operandp;/* scan operands in struct tit */
-  register char *alloperr = "";	/* error over all operands */
-  register char c;		/* Remember char, (we clobber it
-				   with '\0' temporarily).  */
-  char *save_input_line_pointer;
-
-  if (*instring == ' ')
-    ++instring;			/* Skip leading whitespace.  */
-  for (p = instring; *p && *p != ' '; p++)
-    ;				/* MUST end in end-of-string or
-				   exactly 1 space.  */
-  /* Scanned up to end of operation-code.  */
-  /* Operation-code is ended with whitespace.  */
-  if (p == instring)
-    {
-      titP->tit_error = _("No operator");
-      count = 0;
-      titP->tit_opcode = 0;
-    }
-  else
-    {
-      c = *p;
-      *p = '\0';
-      /*
-     * Here with instring pointing to what better be an op-name, and p
-     * pointing to character just past that.
-     * We trust instring points to an op-name, with no whitespace.
-     */
-      twP = (struct tot_wot *) hash_find (op_hash, instring);
-      *p = c;			/* Restore char after op-code.  */
-      if (twP == 0)
-	{
-	  titP->tit_error = _("Unknown operator");
-	  count = 0;
-	  titP->tit_opcode = 0;
-	}
-      else
-	{
-	  /*
-       * We found a match! So let's pick up as many operands as the
-       * instruction wants, and even gripe if there are too many.
-       * We expect comma to separate each operand.
-       * We let instring track the text, while p tracks a part of the
-       * struct tot.
-       */
-
-	  count = 0;		/* no operands seen yet */
-	  instring = p + (*p != '\0');	/* point past the operation code */
-	  /* tip_op() screws with the input_line_pointer, so save it before
-	 I jump in */
-	  save_input_line_pointer = input_line_pointer;
-	  for (p = twP->args, operandp = titP->tit_operand;
-	       !*alloperr && *p;
-	       operandp++, p += 2)
-	    {
-	      /*
-	 * Here to parse one operand. Leave instring pointing just
-	 * past any one ',' that marks the end of this operand.
-	 */
-	      if (!p[1])
-		as_fatal (_("Compiler bug: ODD number of bytes in arg structure %s."),
-			  twP->args);
-	      else if (*instring)
-		{
-		  for (q = instring; (*q != ',' && *q != '\0'); q++)
-		    {
-		      if (*q == '\'' && q[1] != '\0')	/* Jump quoted characters */
-			q++;
-		    }
-		  c = *q;
-		  /*
-	   * Q points to ',' or '\0' that ends argument. C is that
-	   * character.
-	   */
-		  *q = '\0';
-		  operandp->top_access = p[0];
-		  operandp->top_width = p[1];
-		  tip_op (instring - 1, operandp);
-		  *q = c;	/* Restore input text.  */
-		  if (*(operandp->top_error))
-		    {
-		      alloperr = operandp->top_error;
-		    }
-		  instring = q + (c ? 1 : 0);	/* next operand (if any) */
-		  count++;	/*  won another argument, may have an operr */
-		}
-	      else
-		alloperr = _("Not enough operands");
-	    }
-	  /* Restore the pointer.  */
-	  input_line_pointer = save_input_line_pointer;
-
-	  if (!*alloperr)
-	    {
-	      if (*instring == ' ')
-		instring++;	/* Skip whitespace.  */
-	      if (*instring)
-		alloperr = _("Too many operands");
-	    }
-	  titP->tit_error = alloperr;
-	}
-    }
-
-  titP->tit_opcode = twP->code;	/* The op-code.  */
-  titP->tit_operands = count;
-}				/* tip */
-
-/* md_assemble() emit frags for 1 instruction */
-void
-md_assemble (instruction_string)
-     char *instruction_string;	/* A string: assemble 1 instruction.  */
-{
-  char *p;
-  register struct top *operandP;/* An operand. Scans all operands.  */
-  /*  char c_save;	fixme: remove this line *//* What used to live after an expression.  */
-  /*  struct frag *fragP;	fixme: remove this line *//* Fragment of code we just made.  */
-  /*  register struct top *end_operandP; fixme: remove this line *//* -> slot just after last operand
-					Limit of the for (each operand).  */
-  register expressionS *expP;	/* -> expression values for this operand */
-
-  /* These refer to an instruction operand expression.  */
-  segT to_seg;			/* Target segment of the address.	 */
-
-  register valueT this_add_number;
-  register symbolS *this_add_symbol;	/* +ve (minuend) symbol.  */
-
-  /*  tahoe_opcodeT opcode_as_number; fixme: remove this line *//* The opcode as a number.  */
-  char *opcodeP;		/* Where it is in a frag.  */
-  /*  char *opmodeP;	fixme: remove this line *//* Where opcode type is, in a frag.  */
-
-  int dispsize;			/* From top_dispsize: tahoe_operand_width
-				   (in bytes) */
-  int is_undefined;		/* 1 if operand expression's
-				   segment not known yet.  */
-  int pc_rel;			/* Is this operand pc relative? */
-
-  /* Decode the operand.  */
-  tip (&t, instruction_string);
-
-  /*
-   * Check to see if this operand decode properly.
-   * Notice that we haven't made any frags yet.
-   * If it goofed, then this instruction will wedge in any pass,
-   * and we can safely flush it, without causing interpass symbol phase
-   * errors. That is, without changing label values in different passes.
-   */
-  if (*t.tit_error)
-    {
-      as_warn (_("Ignoring statement due to \"%s\""), t.tit_error);
-    }
-  else
-    {
-      /* We saw no errors in any operands - try to make frag(s) */
-      /* Emit op-code.  */
-      /* Remember where it is, in case we want to modify the op-code later.  */
-      opcodeP = frag_more (1);
-      *opcodeP = t.tit_opcode;
-      /* Now do each operand.  */
-      for (operandP = t.tit_operand;
-	   operandP < t.tit_operand + t.tit_operands;
-	   operandP++)
-	{			/* for each operand */
-	  expP = &(operandP->exp_of_operand);
-	  if (operandP->top_ndx >= 0)
-	    {
-	      /* Indexed addressing byte
-	   Legality of indexed mode already checked: it is OK */
-	      FRAG_APPEND_1_CHAR (0x40 + operandP->top_ndx);
-	    }			/* if(top_ndx>=0) */
-
-	  /* Here to make main operand frag(s).  */
-	  this_add_number = expP->X_add_number;
-	  this_add_symbol = expP->X_add_symbol;
-	  to_seg = operandP->seg_of_operand;
-	  know (to_seg == SEG_UNKNOWN || \
-		to_seg == SEG_ABSOLUTE || \
-		to_seg == SEG_DATA || \
-		to_seg == SEG_TEXT || \
-		to_seg == SEG_BSS);
-	  is_undefined = (to_seg == SEG_UNKNOWN);
-	  /* Do we know how big this operand is? */
-	  dispsize = operandP->top_dispsize;
-	  pc_rel = 0;
-	  /* Deal with the branch possibilities. (Note, this doesn't include
-	 jumps.)*/
-	  if (operandP->top_access == 'b')
-	    {
-	      /* Branches must be expressions. A psuedo branch can also jump to
-	   an absolute address.  */
-	      if (to_seg == now_seg || is_undefined)
-		{
-		  /* If is_undefined, then it might BECOME now_seg by relax time.  */
-		  if (dispsize)
-		    {
-		      /* I know how big the branch is supposed to be (it's a normal
-	       branch), so I set up the frag, and let GAS do the rest.  */
-		      p = frag_more (dispsize);
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-			       size_to_fx (dispsize, 1),
-			       NULL);
-		    }
-		  else
-		    {
-		      /* (to_seg==now_seg || to_seg == SEG_UNKNOWN) && dispsize==0 */
-		      /* If we don't know how big it is, then its a synthetic branch,
-	       so we set up a simple relax state.  */
-		      switch (operandP->top_width)
-			{
-			case TAHOE_WIDTH_CONDITIONAL_JUMP:
-			  /* Simple (conditional) jump. I may have to reverse the
-		 condition of opcodeP, and then jump to my destination.
-		 I set 1 byte aside for the branch off set, and could need 6
-		 more bytes for the pc_rel jump */
-			  frag_var (rs_machine_dependent, 7, 1,
-				    ENCODE_RELAX (STATE_CONDITIONAL_BRANCH,
-				    is_undefined ? STATE_UNDF : STATE_BYTE),
-				 this_add_symbol, this_add_number, opcodeP);
-			  break;
-			case TAHOE_WIDTH_ALWAYS_JUMP:
-			  /* Simple (unconditional) jump. I may have to convert this to
-		 a word branch, or an absolute jump.  */
-			  frag_var (rs_machine_dependent, 5, 1,
-				    ENCODE_RELAX (STATE_ALWAYS_BRANCH,
-				    is_undefined ? STATE_UNDF : STATE_BYTE),
-				 this_add_symbol, this_add_number, opcodeP);
-			  break;
-			  /* The smallest size for the next 2 cases is word.  */
-			case TAHOE_WIDTH_BIG_REV_JUMP:
-			  frag_var (rs_machine_dependent, 8, 2,
-				    ENCODE_RELAX (STATE_BIG_REV_BRANCH,
-				    is_undefined ? STATE_UNDF : STATE_WORD),
-				    this_add_symbol, this_add_number,
-				    opcodeP);
-			  break;
-			case TAHOE_WIDTH_BIG_NON_REV_JUMP:
-			  frag_var (rs_machine_dependent, 10, 2,
-				    ENCODE_RELAX (STATE_BIG_NON_REV_BRANCH,
-				    is_undefined ? STATE_UNDF : STATE_WORD),
-				    this_add_symbol, this_add_number,
-				    opcodeP);
-			  break;
-			default:
-			  as_fatal (_("Compliler bug: Got a case (%d) I wasn't expecting."),
-				    operandP->top_width);
-			}
-		    }
-		}
-	      else
-		{
-		  /* to_seg != now_seg && to_seg != seg_unknown (still in branch)
-	     In other words, I'm jumping out of my segment so extend the
-	     branches to jumps, and let GAS fix them.  */
-
-		  /* These are "branches" what will always be branches around a jump
-	     to the correct address in real life.
-	     If to_seg is SEG_ABSOLUTE, just encode the branch in,
-	     else let GAS fix the address.  */
-
-		  switch (operandP->top_width)
-		    {
-		      /* The theory:
-	       For SEG_ABSOLUTE, then mode is ABSOLUTE_ADDR, jump
-	       to that address (not pc_rel).
-	       For other segs, address is a long word PC rel jump.  */
-		    case TAHOE_WIDTH_CONDITIONAL_JUMP:
-		      /* b<cond> */
-		      /* To reverse the condition in a TAHOE branch,
-	       complement bit 4 */
-		      *opcodeP ^= 0x10;
-		      p = frag_more (7);
-		      *p++ = 6;
-		      *p++ = TAHOE_JMP;
-		      *p++ = (operandP->top_mode ==
-			      TAHOE_ABSOLUTE_ADDR ? TAHOE_ABSOLUTE_ADDR :
-			      TAHOE_PC_REL_LONG);
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-		       (to_seg != SEG_ABSOLUTE) ? FX_PCREL32 : FX_32, NULL);
-		      /*
-	     * Now (eg)	BLEQ	1f
-	     *		JMP	foo
-	     *	1:
-	     */
-		      break;
-		    case TAHOE_WIDTH_ALWAYS_JUMP:
-		      /* br, just turn it into a jump */
-		      *opcodeP = TAHOE_JMP;
-		      p = frag_more (5);
-		      *p++ = (operandP->top_mode ==
-			      TAHOE_ABSOLUTE_ADDR ? TAHOE_ABSOLUTE_ADDR :
-			      TAHOE_PC_REL_LONG);
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-		       (to_seg != SEG_ABSOLUTE) ? FX_PCREL32 : FX_32, NULL);
-		      /* Now (eg) JMP foo */
-		      break;
-		    case TAHOE_WIDTH_BIG_REV_JUMP:
-		      p = frag_more (8);
-		      *opcodeP ^= 0x10;
-		      *p++ = 0;
-		      *p++ = 6;
-		      *p++ = TAHOE_JMP;
-		      *p++ = (operandP->top_mode ==
-			      TAHOE_ABSOLUTE_ADDR ? TAHOE_ABSOLUTE_ADDR :
-			      TAHOE_PC_REL_LONG);
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-		       (to_seg != SEG_ABSOLUTE) ? FX_PCREL32 : FX_32, NULL);
-		      /*
-	     * Now (eg)	ACBx	1f
-	     *		JMP     foo
-	     *	1:
-	     */
-		      break;
-		    case TAHOE_WIDTH_BIG_NON_REV_JUMP:
-		      p = frag_more (10);
-		      *p++ = 0;
-		      *p++ = 2;
-		      *p++ = TAHOE_BRB;
-		      *p++ = 6;
-		      *p++ = TAHOE_JMP;
-		      *p++ = (operandP->top_mode ==
-			      TAHOE_ABSOLUTE_ADDR ? TAHOE_ABSOLUTE_ADDR :
-			      TAHOE_PC_REL_LONG);
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-		       (to_seg != SEG_ABSOLUTE) ? FX_PCREL32 : FX_32, NULL);
-		      /*
-	     * Now (eg)	xOBxxx	1f
-	     *		BRB	2f
-	     *	1:	JMP	@#foo
-	     *	2:
-	     */
-		      break;
-		    case 'b':
-		    case 'w':
-		      as_warn (_("Real branch displacements must be expressions."));
-		      break;
-		    default:
-		      as_fatal (_("Complier error: I got an unknown synthetic branch :%c"),
-				operandP->top_width);
-		      break;
-		    }
-		}
-	    }
-	  else
-	    {
-	      /* It ain't a branch operand.  */
-	      switch (operandP->top_mode)
-		{
-		  /* Auto-foo access, only works for one reg (SP)
-	     so the only thing needed is the mode.  */
-		case TAHOE_AUTO_DEC:
-		case TAHOE_AUTO_INC:
-		case TAHOE_AUTO_INC_DEFERRED:
-		  FRAG_APPEND_1_CHAR (operandP->top_mode);
-		  break;
-
-		  /* Numbered Register only access. Only thing needed is the
-	     mode + Register number */
-		case TAHOE_DIRECT_REG:
-		case TAHOE_REG_DEFERRED:
-		  FRAG_APPEND_1_CHAR (operandP->top_mode + operandP->top_reg);
-		  break;
-
-		  /* An absolute address. It's size is always 5 bytes.
-	     (mode_type + 4 byte address).  */
-		case TAHOE_ABSOLUTE_ADDR:
-		  know ((this_add_symbol == NULL));
-		  p = frag_more (5);
-		  *p = TAHOE_ABSOLUTE_ADDR;
-		  md_number_to_chars (p + 1, this_add_number, 4);
-		  break;
-
-		  /* Immediate data. If the size isn't known, then it's an address
-	     + and offset, which is 4 bytes big.  */
-		case TAHOE_IMMEDIATE:
-		  if (this_add_symbol != NULL)
-		    {
-		      p = frag_more (5);
-		      *p++ = TAHOE_IMMEDIATE_LONGWORD;
-		      fix_new (frag_now, p - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-			       FX_32, NULL);
-		    }
-		  else
-		    {
-		      /* It's an integer, and I know it's size.  */
-		      if ((unsigned) this_add_number < 0x40)
-			{
-			  /* Will it fit in a literal? */
-			  FRAG_APPEND_1_CHAR ((byte) this_add_number);
-			}
-		      else
-			{
-			  p = frag_more (dispsize + 1);
-			  switch (dispsize)
-			    {
-			    case 1:
-			      *p++ = TAHOE_IMMEDIATE_BYTE;
-			      *p = (byte) this_add_number;
-			      break;
-			    case 2:
-			      *p++ = TAHOE_IMMEDIATE_WORD;
-			      md_number_to_chars (p, this_add_number, 2);
-			      break;
-			    case 4:
-			      *p++ = TAHOE_IMMEDIATE_LONGWORD;
-			      md_number_to_chars (p, this_add_number, 4);
-			      break;
-			    }
-			}
-		    }
-		  break;
-
-		  /* Distance from the PC. If the size isn't known, we have to relax
-	     into it. The difference between this and disp(sp) is that
-	     this offset is pc_rel, and disp(sp) isn't.
-	     Note the drop through code.  */
-
-		case TAHOE_DISPLACED_RELATIVE:
-		case TAHOE_DISP_REL_DEFERRED:
-		  operandP->top_reg = PC_REG;
-		  pc_rel = 1;
-
-		  /* Register, plus a displacement mode. Save the register number,
-	     and weather its deffered or not, and relax the size if it isn't
-	     known.  */
-		case TAHOE_REG_DISP:
-		case TAHOE_REG_DISP_DEFERRED:
-		  if (operandP->top_mode == TAHOE_DISP_REL_DEFERRED ||
-		      operandP->top_mode == TAHOE_REG_DISP_DEFERRED)
-		    operandP->top_reg += 0x10;	/* deffered mode is always 0x10 higher
-					  than it's non-deffered sibling.  */
-
-		  /* Is this a value out of this segment?
-	     The first part of this conditional is a cludge to make gas
-	     produce the same output as 'as' when there is a lable, in
-	     the current segment, displacing a register. It's strange,
-	     and no one in their right mind would do it, but it's easy
-	     to cludge.  */
-		  if ((dispsize == 0 && !pc_rel) ||
-		      (to_seg != now_seg && !is_undefined && to_seg != SEG_ABSOLUTE))
-		    dispsize = 4;
-
-		  if (dispsize == 0)
-		    {
-		      /*
-	     * We have a SEG_UNKNOWN symbol, or the size isn't cast.
-	     * It might turn out to be in the same segment as
-	     * the instruction, permitting relaxation.
-	     */
-		      p = frag_var (rs_machine_dependent, 5, 2,
-				    ENCODE_RELAX (STATE_PC_RELATIVE,
-				    is_undefined ? STATE_UNDF : STATE_BYTE),
-				    this_add_symbol, this_add_number, 0);
-		      *p = operandP->top_reg;
-		    }
-		  else
-		    {
-		      /* Either this is an abs, or a cast.  */
-		      p = frag_more (dispsize + 1);
-		      switch (dispsize)
-			{
-			case 1:
-			  *p = TAHOE_PC_OR_BYTE + operandP->top_reg;
-			  break;
-			case 2:
-			  *p = TAHOE_PC_OR_WORD + operandP->top_reg;
-			  break;
-			case 4:
-			  *p = TAHOE_PC_OR_LONG + operandP->top_reg;
-			  break;
-			};
-		      fix_new (frag_now, p + 1 - frag_now->fr_literal,
-			       this_add_symbol, this_add_number,
-			       size_to_fx (dispsize, pc_rel), NULL);
-		    }
-		  break;
-		default:
-		  as_fatal (_("Barf, bad mode %x\n"), operandP->top_mode);
-		}
-	    }
-	}			/* for(operandP) */
-    }				/* if(!need_pass_2 && !goofed) */
-}				/* tahoe_assemble() */
-
-/* We have no need to default values of symbols.  */
-
-symbolS *
-md_undefined_symbol (name)
-     char *name;
-{
-  return 0;
-}				/* md_undefined_symbol() */
-
-/* Round up a section size to the appropriate boundary.  */
-valueT
-md_section_align (segment, size)
-     segT segment;
-     valueT size;
-{
-  return ((size + 7) & ~7);	/* Round all sects to multiple of 8 */
-}				/* md_section_align() */
-
-/* Exactly what point is a PC-relative offset relative TO?
-   On the sparc, they're relative to the address of the offset, plus
-   its size.  This gets us to the following instruction.
-   (??? Is this right?  FIXME-SOON) */
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  return (((fixP->fx_type == FX_8
-	    || fixP->fx_type == FX_PCREL8)
-	   ? 1
-	   : ((fixP->fx_type == FX_16
-	       || fixP->fx_type == FX_PCREL16)
-	      ? 2
-	      : ((fixP->fx_type == FX_32
-		  || fixP->fx_type == FX_PCREL32)
-		 ? 4
-		 : 0))) + fixP->fx_where + fixP->fx_frag->fr_address);
-}				/* md_pcrel_from() */
-
-int
-tc_is_pcrel (fixP)
-     fixS *fixP;
-{
-  /* should never be called */
-  know (0);
-  return (0);
-}				/* tc_is_pcrel() */
diff --git a/gas/config/tc-tahoe.h b/gas/config/tc-tahoe.h
deleted file mode 100644
index 74dd32e90598..000000000000
--- a/gas/config/tc-tahoe.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* This file is tc-tahoe.h
-
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1995, 2000
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define TC_TAHOE 1
-
-#define TARGET_BYTES_BIG_ENDIAN 1
-
-#define NO_LISTING
-
-#define tc_headers_hook(a)		{;}	/* don't need it.  */
-#define tc_crawl_symbol_chain(a)	{;}	/* don't need it.  */
-#define tc_aout_pre_write_hook(a)	{;}
-
-#define md_operand(x)
-
-extern const struct relax_type md_relax_table[];
-#define TC_GENERIC_RELAX_TABLE md_relax_table
-
-/*
- * Local Variables:
- * comment-column: 0
- * fill-column: 131
- * End:
- */
diff --git a/gas/config/tc-tic30.c b/gas/config/tc-tic30.c
index 50431345f2c8..b4acccc59bf5 100644
--- a/gas/config/tc-tic30.c
+++ b/gas/config/tc-tic30.c
@@ -1,5 +1,6 @@
 /* tc-c30.c -- Assembly code for the Texas Instruments TMS320C30
-   Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1998, 1999, 2000, 2001, 2002, 2003
+   Free Software Foundation, Inc.
    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Texas Instruments TMS320C30 machine specific gas.
    Written by Steven Haworth (steve@pm.cse.rmit.edu.au).
@@ -27,42 +28,38 @@
 #include "as.h"
 #include "safe-ctype.h"
 #include "opcode/tic30.h"
-#ifdef ANSI_PROTOTYPES
 #include <stdarg.h>
-#else
-#include <varargs.h>
-#endif
 
 /* Put here all non-digit non-letter characters that may occur in an
    operand.  */
 static char operand_special_chars[] = "%$-+(,)*._~/<>&^!:[@]";
-static char *ordinal_names[] = {
+static char *ordinal_names[] =
+{
   "first", "second", "third", "fourth", "fifth"
 };
 
-const int md_reloc_size = 0;
-
-const char comment_chars[] = ";";
-const char line_comment_chars[] = "*";
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "*";
 const char line_separator_chars[] = "";
 
 const char *md_shortopts = "";
-struct option md_longopts[] = {
+struct option md_longopts[] =
+{
   {NULL, no_argument, NULL, 0}
 };
 
 size_t md_longopts_size = sizeof (md_longopts);
 
-/* Chars that mean this number is a floating point constant.  */
-/* As in 0f12.456 */
-/* or    0d1.2345e12 */
+/* Chars that mean this number is a floating point constant.
+   As in 0f12.456
+   or    0d1.2345e12.  */
 const char FLT_CHARS[] = "fFdDxX";
 
 /* Chars that can be used to separate mant from exp in floating point
    nums.  */
 const char EXP_CHARS[] = "eE";
 
-/* tables for lexical analysis */
+/* Tables for lexical analysis.  */
 static char opcode_chars[256];
 static char register_chars[256];
 static char operand_chars[256];
@@ -70,22 +67,21 @@ static char space_chars[256];
 static char identifier_chars[256];
 static char digit_chars[256];
 
-/* lexical macros */
-#define is_opcode_char(x) (opcode_chars[(unsigned char) x])
-#define is_operand_char(x) (operand_chars[(unsigned char) x])
-#define is_register_char(x) (register_chars[(unsigned char) x])
-#define is_space_char(x) (space_chars[(unsigned char) x])
-#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
-#define is_digit_char(x) (digit_chars[(unsigned char) x])
+/* Lexical macros.  */
+#define is_opcode_char(x)     (opcode_chars     [(unsigned char) x])
+#define is_operand_char(x)    (operand_chars    [(unsigned char) x])
+#define is_register_char(x)   (register_chars   [(unsigned char) x])
+#define is_space_char(x)      (space_chars      [(unsigned char) x])
+#define is_identifier_char(x) (identifier_chars [(unsigned char) x])
+#define is_digit_char(x)      (digit_chars      [(unsigned char) x])
 
-const pseudo_typeS md_pseudo_table[] = {
+const pseudo_typeS md_pseudo_table[] =
+{
   {0, 0, 0}
 };
 
-int debug PARAMS ((const char *string, ...));
-
-int
-debug VPARAMS ((const char *string, ...))
+static int ATTRIBUTE_PRINTF_1
+debug (const char *string, ...)
 {
   if (flag_debug)
     {
@@ -104,64 +100,85 @@ debug VPARAMS ((const char *string, ...))
     return 0;
 }
 
-/* hash table for opcode lookup */
+/* Hash table for opcode lookup.  */
 static struct hash_control *op_hash;
-/* hash table for parallel opcode lookup */
+/* Hash table for parallel opcode lookup.  */
 static struct hash_control *parop_hash;
-/* hash table for register lookup */
+/* Hash table for register lookup.  */
 static struct hash_control *reg_hash;
-/* hash table for indirect addressing lookup */
+/* Hash table for indirect addressing lookup.  */
 static struct hash_control *ind_hash;
 
 void
-md_begin ()
+md_begin (void)
 {
   const char *hash_err;
+
   debug ("In md_begin()\n");
   op_hash = hash_new ();
+
   {
     const template *current_optab = tic30_optab;
+
     for (; current_optab < tic30_optab_end; current_optab++)
       {
-	hash_err = hash_insert (op_hash, current_optab->name, (char *) current_optab);
+	hash_err = hash_insert (op_hash, current_optab->name,
+				(char *) current_optab);
 	if (hash_err)
-	  as_fatal ("Internal Error: Can't Hash %s: %s", current_optab->name, hash_err);
+	  as_fatal ("Internal Error: Can't Hash %s: %s",
+		    current_optab->name, hash_err);
       }
   }
+
   parop_hash = hash_new ();
+
   {
     const partemplate *current_parop = tic30_paroptab;
+
     for (; current_parop < tic30_paroptab_end; current_parop++)
       {
-	hash_err = hash_insert (parop_hash, current_parop->name, (char *) current_parop);
+	hash_err = hash_insert (parop_hash, current_parop->name,
+				(char *) current_parop);
 	if (hash_err)
-	  as_fatal ("Internal Error: Can't Hash %s: %s", current_parop->name, hash_err);
+	  as_fatal ("Internal Error: Can't Hash %s: %s",
+		    current_parop->name, hash_err);
       }
   }
+
   reg_hash = hash_new ();
+
   {
     const reg *current_reg = tic30_regtab;
+
     for (; current_reg < tic30_regtab_end; current_reg++)
       {
-	hash_err = hash_insert (reg_hash, current_reg->name, (char *) current_reg);
+	hash_err = hash_insert (reg_hash, current_reg->name,
+				(char *) current_reg);
 	if (hash_err)
-	  as_fatal ("Internal Error: Can't Hash %s: %s", current_reg->name, hash_err);
+	  as_fatal ("Internal Error: Can't Hash %s: %s",
+		    current_reg->name, hash_err);
       }
   }
+
   ind_hash = hash_new ();
+
   {
     const ind_addr_type *current_ind = tic30_indaddr_tab;
+
     for (; current_ind < tic30_indaddrtab_end; current_ind++)
       {
-	hash_err = hash_insert (ind_hash, current_ind->syntax, (char *) current_ind);
+	hash_err = hash_insert (ind_hash, current_ind->syntax,
+				(char *) current_ind);
 	if (hash_err)
-	  as_fatal ("Internal Error: Can't Hash %s: %s", current_ind->syntax, hash_err);
+	  as_fatal ("Internal Error: Can't Hash %s: %s",
+		    current_ind->syntax, hash_err);
       }
   }
-  /* fill in lexical tables:  opcode_chars, operand_chars, space_chars */
+
+  /* Fill in lexical tables:  opcode_chars, operand_chars, space_chars.  */
   {
-    register int c;
-    register char *p;
+    int c;
+    char *p;
 
     for (c = 0; c < 256; c++)
       {
@@ -176,17 +193,20 @@ md_begin ()
 	    register_chars[c] = opcode_chars[c];
 	  }
 	else if (c == ')' || c == '(')
-	  {
-	    register_chars[c] = c;
-	  }
+	  register_chars[c] = c;
+
 	if (ISUPPER (c) || ISLOWER (c) || ISDIGIT (c))
 	  operand_chars[c] = c;
+
 	if (ISDIGIT (c) || c == '-')
 	  digit_chars[c] = c;
+
 	if (ISALPHA (c) || c == '_' || c == '.' || ISDIGIT (c))
 	  identifier_chars[c] = c;
+
 	if (c == ' ' || c == '\t')
 	  space_chars[c] = c;
+
 	if (c == '_')
 	  opcode_chars[c] = c;
       }
@@ -195,34 +215,39 @@ md_begin ()
   }
 }
 
-/* Address Mode OR values */
+/* Address Mode OR values.  */
 #define AM_Register  0x00000000
 #define AM_Direct    0x00200000
 #define AM_Indirect  0x00400000
 #define AM_Immediate 0x00600000
 #define AM_NotReq    0xFFFFFFFF
 
-/* PC Relative OR values */
+/* PC Relative OR values.  */
 #define PC_Register 0x00000000
 #define PC_Relative 0x02000000
 
-typedef struct {
+typedef struct
+{
   unsigned op_type;
-  struct {
+  struct
+  {
     int resolved;
     unsigned address;
     char *label;
     expressionS direct_expr;
   } direct;
-  struct {
+  struct
+  {
     unsigned mod;
     int ARnum;
     unsigned char disp;
   } indirect;
-  struct {
+  struct
+  {
     unsigned opcode;
   } reg;
-  struct {
+  struct
+  {
     int resolved;
     int decimal_found;
     float f_number;
@@ -233,564 +258,403 @@ typedef struct {
   } immediate;
 } operand;
 
-int tic30_parallel_insn PARAMS ((char *));
-operand *tic30_operand PARAMS ((char *));
-char *tic30_find_parallel_insn PARAMS ((char *, char *));
-
 template *opcode;
 
-struct tic30_insn {
-  template *tm;			/* Template of current instruction */
-  unsigned opcode;		/* Final opcode */
-  unsigned int operands;	/* Number of given operands */
-  /* Type of operand given in instruction */
+struct tic30_insn
+{
+  template *tm;			/* Template of current instruction.  */
+  unsigned opcode;		/* Final opcode.  */
+  unsigned int operands;	/* Number of given operands.  */
+  /* Type of operand given in instruction.  */
   operand *operand_type[MAX_OPERANDS];
-  unsigned addressing_mode;	/* Final addressing mode of instruction */
+  unsigned addressing_mode;	/* Final addressing mode of instruction.  */
 };
 
 struct tic30_insn insn;
 static int found_parallel_insn;
 
-void
-md_assemble (line)
-     char *line;
-{
-  template *opcode;
-  char *current_posn;
-  char *token_start;
-  char save_char;
-  unsigned int count;
+static char output_invalid_buf[8];
 
-  debug ("In md_assemble() with argument %s\n", line);
-  memset (&insn, '\0', sizeof (insn));
-  if (found_parallel_insn)
-    {
-      debug ("Line is second part of parallel instruction\n\n");
-      found_parallel_insn = 0;
-      return;
-    }
-  if ((current_posn = tic30_find_parallel_insn (line, input_line_pointer + 1)) == NULL)
-    current_posn = line;
+static char *
+output_invalid (char c)
+{
+  if (ISPRINT (c))
+    sprintf (output_invalid_buf, "'%c'", c);
   else
-    found_parallel_insn = 1;
-  while (is_space_char (*current_posn))
-    current_posn++;
-  token_start = current_posn;
-  if (!is_opcode_char (*current_posn))
-    {
-      as_bad ("Invalid character %s in opcode", output_invalid (*current_posn));
-      return;
-    }
-  /* Check if instruction is a parallel instruction by seeing if the first
-     character is a q.  */
-  if (*token_start == 'q')
+    sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
+  return output_invalid_buf;
+}
+
+/* next_line points to the next line after the current instruction
+   (current_line).  Search for the parallel bars, and if found, merge two
+   lines into internal syntax for a parallel instruction:
+     q_[INSN1]_[INSN2] [OPERANDS1] | [OPERANDS2]
+   By this stage, all comments are scrubbed, and only the bare lines are
+   given.  */
+
+#define NONE           0
+#define START_OPCODE   1
+#define END_OPCODE     2
+#define START_OPERANDS 3
+#define END_OPERANDS   4
+
+static char *
+tic30_find_parallel_insn (char *current_line, char *next_line)
+{
+  int found_parallel = 0;
+  char first_opcode[256];
+  char second_opcode[256];
+  char first_operands[256];
+  char second_operands[256];
+  char *parallel_insn;
+
+  debug ("In tic30_find_parallel_insn()\n");
+  while (!is_end_of_line[(unsigned char) *next_line])
     {
-      if (tic30_parallel_insn (token_start))
+      if (*next_line == PARALLEL_SEPARATOR
+	  && *(next_line + 1) == PARALLEL_SEPARATOR)
 	{
-	  if (found_parallel_insn)
-	    free (token_start);
-	  return;
+	  found_parallel = 1;
+	  next_line++;
+	  break;
 	}
+      next_line++;
     }
-  while (is_opcode_char (*current_posn))
-    current_posn++;
-  {				/* Find instruction */
-    save_char = *current_posn;
-    *current_posn = '\0';
-    opcode = (template *) hash_find (op_hash, token_start);
-    if (opcode)
-      {
-	debug ("Found instruction %s\n", opcode->name);
-	insn.tm = opcode;
-      }
-    else
+  if (!found_parallel)
+    return NULL;
+  debug ("Found a parallel instruction\n");
+
+  {
+    int i;
+    char *opcode, *operands, *line;
+
+    for (i = 0; i < 2; i++)
       {
-	debug ("Didn't find insn\n");
-	as_bad ("Unknown TMS320C30 instruction: %s", token_start);
-	return;
-      }
-    *current_posn = save_char;
-  }
-  if (*current_posn != END_OF_INSN)
-    {				/* Find operands */
-      int paren_not_balanced;
-      int expecting_operand = 0;
-      int this_operand;
-      do
+	if (i == 0)
+	  {
+	    opcode = &first_opcode[0];
+	    operands = &first_operands[0];
+	    line = current_line;
+	  }
+	else
+	  {
+	    opcode = &second_opcode[0];
+	    operands = &second_operands[0];
+	    line = next_line;
+	  }
+
 	{
-	  /* skip optional white space before operand */
-	  while (!is_operand_char (*current_posn) && *current_posn != END_OF_INSN)
-	    {
-	      if (!is_space_char (*current_posn))
-		{
-		  as_bad ("Invalid character %s before %s operand",
-			  output_invalid (*current_posn),
-			  ordinal_names[insn.operands]);
-		  return;
-		}
-	      current_posn++;
-	    }
-	  token_start = current_posn;	/* after white space */
-	  paren_not_balanced = 0;
-	  while (paren_not_balanced || *current_posn != ',')
+	  int search_status = NONE;
+	  int char_ptr = 0;
+	  char c;
+
+	  while (!is_end_of_line[(unsigned char) (c = *line)])
 	    {
-	      if (*current_posn == END_OF_INSN)
-		{
-		  if (paren_not_balanced)
-		    {
-		      as_bad ("Unbalanced parenthesis in %s operand.",
-			      ordinal_names[insn.operands]);
-		      return;
-		    }
-		  else
-		    break;	/* we are done */
-		}
-	      else if (!is_operand_char (*current_posn) && !is_space_char (*current_posn))
-		{
-		  as_bad ("Invalid character %s in %s operand",
-			  output_invalid (*current_posn),
-			  ordinal_names[insn.operands]);
-		  return;
-		}
-	      if (*current_posn == '(')
-		++paren_not_balanced;
-	      if (*current_posn == ')')
-		--paren_not_balanced;
-	      current_posn++;
-	    }
-	  if (current_posn != token_start)
-	    {			/* yes, we've read in another operand */
-	      this_operand = insn.operands++;
-	      if (insn.operands > MAX_OPERANDS)
+	      if (is_opcode_char (c) && search_status == NONE)
 		{
-		  as_bad ("Spurious operands; (%d operands/instruction max)",
-			  MAX_OPERANDS);
-		  return;
+		  opcode[char_ptr++] = TOLOWER (c);
+		  search_status = START_OPCODE;
 		}
-	      /* now parse operand adding info to 'insn' as we go along */
-	      save_char = *current_posn;
-	      *current_posn = '\0';
-	      insn.operand_type[this_operand] = tic30_operand (token_start);
-	      *current_posn = save_char;
-	      if (insn.operand_type[this_operand] == NULL)
-		return;
-	    }
-	  else
-	    {
-	      if (expecting_operand)
+	      else if (is_opcode_char (c) && search_status == START_OPCODE)
+		opcode[char_ptr++] = TOLOWER (c);
+	      else if (!is_opcode_char (c) && search_status == START_OPCODE)
 		{
-		  as_bad ("Expecting operand after ','; got nothing");
-		  return;
+		  opcode[char_ptr] = '\0';
+		  char_ptr = 0;
+		  search_status = END_OPCODE;
 		}
-	      if (*current_posn == ',')
+	      else if (is_operand_char (c) && search_status == START_OPERANDS)
+		operands[char_ptr++] = c;
+
+	      if (is_operand_char (c) && search_status == END_OPCODE)
 		{
-		  as_bad ("Expecting operand before ','; got nothing");
-		  return;
-		}
-	    }
-	  /* now *current_posn must be either ',' or END_OF_INSN */
-	  if (*current_posn == ',')
-	    {
-	      if (*++current_posn == END_OF_INSN)
-		{		/* just skip it, if it's \n complain */
-		  as_bad ("Expecting operand after ','; got nothing");
-		  return;
+		  operands[char_ptr++] = c;
+		  search_status = START_OPERANDS;
 		}
-	      expecting_operand = 1;
+
+	      line++;
 	    }
+	  if (search_status != START_OPERANDS)
+	    return NULL;
+	  operands[char_ptr] = '\0';
 	}
-      while (*current_posn != END_OF_INSN);	/* until we get end of insn */
-    }
-  debug ("Number of operands found: %d\n", insn.operands);
-  /* Check that number of operands is correct */
-  if (insn.operands != insn.tm->operands)
+      }
+  }
+  parallel_insn = malloc (strlen (first_opcode) + strlen (first_operands)
+			  + strlen (second_opcode) + strlen (second_operands) + 8);
+  sprintf (parallel_insn, "q_%s_%s %s | %s",
+	   first_opcode, second_opcode,
+	   first_operands, second_operands);
+  debug ("parallel insn = %s\n", parallel_insn);
+  return parallel_insn;
+}
+
+#undef NONE
+#undef START_OPCODE
+#undef END_OPCODE
+#undef START_OPERANDS
+#undef END_OPERANDS
+
+static operand *
+tic30_operand (char *token)
+{
+  unsigned int count;
+  char ind_buffer[strlen (token)];
+  operand *current_op;
+
+  debug ("In tic30_operand with %s\n", token);
+  current_op = malloc (sizeof (* current_op));
+  memset (current_op, '\0', sizeof (operand));
+
+  if (*token == DIRECT_REFERENCE)
     {
-      unsigned int i;
-      unsigned int numops = insn.tm->operands;
-      /* If operands are not the same, then see if any of the operands are not
-         required.  Then recheck with number of given operands.  If they are still not
-         the same, then give an error, otherwise carry on.  */
-      for (i = 0; i < insn.tm->operands; i++)
-	if (insn.tm->operand_types[i] & NotReq)
-	  numops--;
-      if (insn.operands != numops)
+      char *token_posn = token + 1;
+      int direct_label = 0;
+
+      debug ("Found direct reference\n");
+      while (*token_posn)
 	{
-	  as_bad ("Incorrect number of operands given");
-	  return;
+	  if (!is_digit_char (*token_posn))
+	    direct_label = 1;
+	  token_posn++;
 	}
-    }
-  insn.addressing_mode = AM_NotReq;
-  for (count = 0; count < insn.operands; count++)
-    {
-      if (insn.operand_type[count]->op_type & insn.tm->operand_types[count])
+
+      if (direct_label)
 	{
-	  debug ("Operand %d matches\n", count + 1);
-	  /* If instruction has two operands and has an AddressMode modifier then set
-	     addressing mode type for instruction */
-	  if (insn.tm->opcode_modifier == AddressMode)
+	  char *save_input_line_pointer;
+	  segT retval;
+
+	  debug ("Direct reference is a label\n");
+	  current_op->direct.label = token + 1;
+	  save_input_line_pointer = input_line_pointer;
+	  input_line_pointer = token + 1;
+	  debug ("Current input_line_pointer: %s\n", input_line_pointer);
+	  retval = expression (&current_op->direct.direct_expr);
+
+	  debug ("Expression type: %d\n",
+		 current_op->direct.direct_expr.X_op);
+	  debug ("Expression addnum: %ld\n",
+		 (long) current_op->direct.direct_expr.X_add_number);
+	  debug ("Segment: %p\n", retval);
+
+	  input_line_pointer = save_input_line_pointer;
+
+	  if (current_op->direct.direct_expr.X_op == O_constant)
 	    {
-	      int addr_insn = 0;
-	      /* Store instruction uses the second operand for the address mode.  */
-	      if ((insn.tm->operand_types[1] & (Indirect | Direct)) == (Indirect | Direct))
-		addr_insn = 1;
-	      if (insn.operand_type[addr_insn]->op_type & (AllReg))
-		insn.addressing_mode = AM_Register;
-	      else if (insn.operand_type[addr_insn]->op_type & Direct)
-		insn.addressing_mode = AM_Direct;
-	      else if (insn.operand_type[addr_insn]->op_type & Indirect)
-		insn.addressing_mode = AM_Indirect;
-	      else
-		insn.addressing_mode = AM_Immediate;
+	      current_op->direct.address =
+		current_op->direct.direct_expr.X_add_number;
+	      current_op->direct.resolved = 1;
 	    }
 	}
       else
 	{
-	  as_bad ("The %s operand doesn't match", ordinal_names[count]);
-	  return;
+	  debug ("Direct reference is a number\n");
+	  current_op->direct.address = atoi (token + 1);
+	  current_op->direct.resolved = 1;
 	}
+      current_op->op_type = Direct;
     }
-  /* Now set the addressing mode for 3 operand instructions.  */
-  if ((insn.tm->operand_types[0] & op3T1) && (insn.tm->operand_types[1] & op3T2))
+  else if (*token == INDIRECT_REFERENCE)
     {
-      /* Set the addressing mode to the values used for 2 operand instructions in the
-         G addressing field of the opcode.  */
-      char *p;
-      switch (insn.operand_type[0]->op_type)
-	{
-	case Rn:
-	case ARn:
-	case DPReg:
-	case OtherReg:
-	  if (insn.operand_type[1]->op_type & (AllReg))
-	    insn.addressing_mode = AM_Register;
-	  else if (insn.operand_type[1]->op_type & Indirect)
-	    insn.addressing_mode = AM_Direct;
-	  else
-	    {
-	      /* Shouldn't make it to this stage */
-	      as_bad ("Incompatible first and second operands in instruction");
-	      return;
-	    }
-	  break;
-	case Indirect:
-	  if (insn.operand_type[1]->op_type & (AllReg))
-	    insn.addressing_mode = AM_Indirect;
-	  else if (insn.operand_type[1]->op_type & Indirect)
-	    insn.addressing_mode = AM_Immediate;
-	  else
-	    {
-	      /* Shouldn't make it to this stage */
-	      as_bad ("Incompatible first and second operands in instruction");
-	      return;
-	    }
-	  break;
-	}
-      /* Now make up the opcode for the 3 operand instructions.  As in parallel
-         instructions, there will be no unresolved values, so they can be fully formed
-         and added to the frag table.  */
-      insn.opcode = insn.tm->base_opcode;
-      if (insn.operand_type[0]->op_type & Indirect)
-	{
-	  insn.opcode |= (insn.operand_type[0]->indirect.ARnum);
-	  insn.opcode |= (insn.operand_type[0]->indirect.mod << 3);
-	}
-      else
-	insn.opcode |= (insn.operand_type[0]->reg.opcode);
-      if (insn.operand_type[1]->op_type & Indirect)
-	{
-	  insn.opcode |= (insn.operand_type[1]->indirect.ARnum << 8);
-	  insn.opcode |= (insn.operand_type[1]->indirect.mod << 11);
-	}
-      else
-	insn.opcode |= (insn.operand_type[1]->reg.opcode << 8);
-      if (insn.operands == 3)
-	insn.opcode |= (insn.operand_type[2]->reg.opcode << 16);
-      insn.opcode |= insn.addressing_mode;
-      p = frag_more (INSN_SIZE);
-      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-    }
-  else
-    {				/* Not a three operand instruction */
-      char *p;
-      int am_insn = -1;
-      insn.opcode = insn.tm->base_opcode;
-      /* Create frag for instruction - all instructions are 4 bytes long.  */
-      p = frag_more (INSN_SIZE);
-      if ((insn.operands > 0) && (insn.tm->opcode_modifier == AddressMode))
+      /* Indirect reference operand.  */
+      int found_ar = 0;
+      int found_disp = 0;
+      int ar_number = -1;
+      int disp_number = 0;
+      int buffer_posn = 1;
+      ind_addr_type *ind_addr_op;
+
+      debug ("Found indirect reference\n");
+      ind_buffer[0] = *token;
+
+      for (count = 1; count < strlen (token); count++)
 	{
-	  insn.opcode |= insn.addressing_mode;
-	  if (insn.addressing_mode == AM_Indirect)
-	    {
-	      /* Determine which operand gives the addressing mode */
-	      if (insn.operand_type[0]->op_type & Indirect)
-		am_insn = 0;
-	      if ((insn.operands > 1) && (insn.operand_type[1]->op_type & Indirect))
-		am_insn = 1;
-	      insn.opcode |= (insn.operand_type[am_insn]->indirect.disp);
-	      insn.opcode |= (insn.operand_type[am_insn]->indirect.ARnum << 8);
-	      insn.opcode |= (insn.operand_type[am_insn]->indirect.mod << 11);
-	      if (insn.operands > 1)
-		insn.opcode |= (insn.operand_type[!am_insn]->reg.opcode << 16);
-	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-	    }
-	  else if (insn.addressing_mode == AM_Register)
-	    {
-	      insn.opcode |= (insn.operand_type[0]->reg.opcode);
-	      if (insn.operands > 1)
-		insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
-	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-	    }
-	  else if (insn.addressing_mode == AM_Direct)
+	  /* Strip operand.  */
+	  ind_buffer[buffer_posn] = TOLOWER (*(token + count));
+
+	  if ((*(token + count - 1) == 'a' || *(token + count - 1) == 'A')
+	      && (*(token + count) == 'r' || *(token + count) == 'R'))
 	    {
-	      if (insn.operand_type[0]->op_type & Direct)
-		am_insn = 0;
-	      if ((insn.operands > 1) && (insn.operand_type[1]->op_type & Direct))
-		am_insn = 1;
-	      if (insn.operands > 1)
-		insn.opcode |= (insn.operand_type[!am_insn]->reg.opcode << 16);
-	      if (insn.operand_type[am_insn]->direct.resolved == 1)
+	      /* AR reference is found, so get its number and remove
+		 it from the buffer so it can pass through hash_find().  */
+	      if (found_ar)
 		{
-		  /* Resolved values can be placed straight into instruction word, and output */
-		  insn.opcode |= (insn.operand_type[am_insn]->direct.address & 0x0000FFFF);
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  as_bad ("More than one AR register found in indirect reference");
+		  return NULL;
 		}
-	      else
-		{		/* Unresolved direct addressing mode instruction */
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		  fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal), 2, &insn.operand_type[am_insn]->direct.direct_expr, 0, 0);
+	      if (*(token + count + 1) < '0' || *(token + count + 1) > '7')
+		{
+		  as_bad ("Illegal AR register in indirect reference");
+		  return NULL;
 		}
+	      ar_number = *(token + count + 1) - '0';
+	      found_ar = 1;
+	      count++;
 	    }
-	  else if (insn.addressing_mode == AM_Immediate)
+
+	  if (*(token + count) == '(')
 	    {
-	      if (insn.operand_type[0]->immediate.resolved == 1)
+	      /* Parenthesis found, so check if a displacement value is
+		 inside.  If so, get the value and remove it from the
+		 buffer.  */
+	      if (is_digit_char (*(token + count + 1)))
 		{
-		  char *keeploc;
-		  int size;
-		  if (insn.operands > 1)
-		    insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
-		  switch (insn.tm->imm_arg_type)
+		  char disp[10];
+		  int disp_posn = 0;
+
+		  if (found_disp)
 		    {
-		    case Imm_Float:
-		      debug ("Floating point first operand\n");
-		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		      keeploc = input_line_pointer;
-		      input_line_pointer = insn.operand_type[0]->immediate.label;
-		      if (md_atof ('f', p + 2, &size) != 0)
-			{
-			  as_bad ("invalid short form floating point immediate operand");
-			  return;
-			}
-		      input_line_pointer = keeploc;
-		      break;
-		    case Imm_UInt:
-		      debug ("Unsigned int first operand\n");
-		      if (insn.operand_type[0]->immediate.decimal_found)
-			as_warn ("rounding down first operand float to unsigned int");
-		      if (insn.operand_type[0]->immediate.u_number > 0xFFFF)
-			as_warn ("only lower 16-bits of first operand are used");
-		      insn.opcode |= (insn.operand_type[0]->immediate.u_number & 0x0000FFFFL);
-		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		      break;
-		    case Imm_SInt:
-		      debug ("Int first operand\n");
-		      if (insn.operand_type[0]->immediate.decimal_found)
-			as_warn ("rounding down first operand float to signed int");
-		      if (insn.operand_type[0]->immediate.s_number < -32768 ||
-			  insn.operand_type[0]->immediate.s_number > 32767)
+		      as_bad ("More than one displacement found in indirect reference");
+		      return NULL;
+		    }
+		  count++;
+		  while (*(token + count) != ')')
+		    {
+		      if (!is_digit_char (*(token + count)))
 			{
-			  as_bad ("first operand is too large for 16-bit signed int");
-			  return;
+			  as_bad ("Invalid displacement in indirect reference");
+			  return NULL;
 			}
-		      insn.opcode |= (insn.operand_type[0]->immediate.s_number & 0x0000FFFFL);
-		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		      break;
+		      disp[disp_posn++] = *(token + (count++));
 		    }
-		}
-	      else
-		{		/* Unresolved immediate label */
-		  if (insn.operands > 1)
-		    insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		  fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal), 2, &insn.operand_type[0]->immediate.imm_expr, 0, 0);
+		  disp[disp_posn] = '\0';
+		  disp_number = atoi (disp);
+		  count--;
+		  found_disp = 1;
 		}
 	    }
+	  buffer_posn++;
 	}
-      else if (insn.tm->opcode_modifier == PCRel)
+
+      ind_buffer[buffer_posn] = '\0';
+      if (!found_ar)
+	{
+	  as_bad ("AR register not found in indirect reference");
+	  return NULL;
+	}
+
+      ind_addr_op = (ind_addr_type *) hash_find (ind_hash, ind_buffer);
+      if (ind_addr_op)
 	{
-	  /* Conditional Branch and Call instructions */
-	  if ((insn.tm->operand_types[0] & (AllReg | Disp)) == (AllReg | Disp))
+	  debug ("Found indirect reference: %s\n", ind_addr_op->syntax);
+	  if (ind_addr_op->displacement == IMPLIED_DISP)
 	    {
-	      if (insn.operand_type[0]->op_type & (AllReg))
-		{
-		  insn.opcode |= (insn.operand_type[0]->reg.opcode);
-		  insn.opcode |= PC_Register;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		}
-	      else
-		{
-		  insn.opcode |= PC_Relative;
-		  if (insn.operand_type[0]->immediate.resolved == 1)
-		    {
-		      insn.opcode |= (insn.operand_type[0]->immediate.s_number & 0x0000FFFF);
-		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		    }
-		  else
-		    {
-		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		      fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal), 2, &insn.operand_type[0]->immediate.imm_expr, 1, 0);
-		    }
-		}
+	      found_disp = 1;
+	      disp_number = 1;
 	    }
-	  else if ((insn.tm->operand_types[0] & ARn) == ARn)
+	  else if ((ind_addr_op->displacement == DISP_REQUIRED) && !found_disp)
 	    {
-	      /* Decrement and Branch instructions */
-	      insn.opcode |= ((insn.operand_type[0]->reg.opcode - 0x08) << 22);
-	      if (insn.operand_type[1]->op_type & (AllReg))
-		{
-		  insn.opcode |= (insn.operand_type[1]->reg.opcode);
-		  insn.opcode |= PC_Register;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		}
-	      else if (insn.operand_type[1]->immediate.resolved == 1)
-		{
-		  if (insn.operand_type[0]->immediate.decimal_found)
-		    {
-		      as_bad ("first operand is floating point");
-		      return;
-		    }
-		  if (insn.operand_type[0]->immediate.s_number < -32768 ||
-		      insn.operand_type[0]->immediate.s_number > 32767)
-		    {
-		      as_bad ("first operand is too large for 16-bit signed int");
-		      return;
-		    }
-		  insn.opcode |= (insn.operand_type[1]->immediate.s_number);
-		  insn.opcode |= PC_Relative;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		}
-	      else
-		{
-		  insn.opcode |= PC_Relative;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		  fix_new_exp (frag_now, p + 2 - frag_now->fr_literal, 2, &insn.operand_type[1]->immediate.imm_expr, 1, 0);
-		}
+	      /* Maybe an implied displacement of 1 again.  */
+	      as_bad ("required displacement wasn't given in indirect reference");
+	      return 0;
 	    }
 	}
-      else if (insn.tm->operand_types[0] == IVector)
+      else
 	{
-	  /* Trap instructions */
-	  if (insn.operand_type[0]->op_type & IVector)
-	    insn.opcode |= (insn.operand_type[0]->immediate.u_number);
-	  else
-	    {			/* Shouldn't get here */
-	      as_bad ("interrupt vector for trap instruction out of range");
-	      return;
-	    }
-	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	  as_bad ("illegal indirect reference");
+	  return NULL;
 	}
-      else if (insn.tm->opcode_modifier == StackOp || insn.tm->opcode_modifier == Rotate)
+
+      if (found_disp && (disp_number < 0 || disp_number > 255))
 	{
-	  /* Push, Pop and Rotate instructions */
-	  insn.opcode |= (insn.operand_type[0]->reg.opcode << 16);
-	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	  as_bad ("displacement must be an unsigned 8-bit number");
+	  return NULL;
 	}
-      else if ((insn.tm->operand_types[0] & (Abs24 | Direct)) == (Abs24 | Direct))
+
+      current_op->indirect.mod = ind_addr_op->modfield;
+      current_op->indirect.disp = disp_number;
+      current_op->indirect.ARnum = ar_number;
+      current_op->op_type = Indirect;
+    }
+  else
+    {
+      reg *regop = (reg *) hash_find (reg_hash, token);
+
+      if (regop)
 	{
-	  /* LDP Instruction needs to be tested for before the next section */
-	  if (insn.operand_type[0]->op_type & Direct)
-	    {
-	      if (insn.operand_type[0]->direct.resolved == 1)
-		{
-		  /* Direct addressing uses lower 8 bits of direct address */
-		  insn.opcode |= (insn.operand_type[0]->direct.address & 0x00FF0000) >> 16;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		}
-	      else
-		{
-		  fixS *fix;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		  fix = fix_new_exp (frag_now, p + 3 - (frag_now->fr_literal), 1, &insn.operand_type[0]->direct.direct_expr, 0, 0);
-		  /* Ensure that the assembler doesn't complain about fitting a 24-bit
-		     address into 8 bits.  */
-		  fix->fx_no_overflow = 1;
-		}
-	    }
+	  debug ("Found register operand: %s\n", regop->name);
+	  if (regop->regtype == REG_ARn)
+	    current_op->op_type = ARn;
+	  else if (regop->regtype == REG_Rn)
+	    current_op->op_type = Rn;
+	  else if (regop->regtype == REG_DP)
+	    current_op->op_type = DPReg;
 	  else
-	    {
-	      if (insn.operand_type[0]->immediate.resolved == 1)
-		{
-		  /* Immediate addressing uses upper 8 bits of address */
-		  if (insn.operand_type[0]->immediate.u_number > 0x00FFFFFF)
-		    {
-		      as_bad ("LDP instruction needs a 24-bit operand");
-		      return;
-		    }
-		  insn.opcode |= ((insn.operand_type[0]->immediate.u_number & 0x00FF0000) >> 16);
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		}
-	      else
-		{
-		  fixS *fix;
-		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-		  fix = fix_new_exp (frag_now, p + 3 - (frag_now->fr_literal), 1, &insn.operand_type[0]->immediate.imm_expr, 0, 0);
-		  fix->fx_no_overflow = 1;
-		}
-	    }
+	    current_op->op_type = OtherReg;
+	  current_op->reg.opcode = regop->opcode;
 	}
-      else if (insn.tm->operand_types[0] & (Imm24))
+      else
 	{
-	  /* Unconditional Branch and Call instructions */
-	  if (insn.operand_type[0]->immediate.resolved == 1)
+	  if (!is_digit_char (*token)
+	      || *(token + 1) == 'x'
+	      || strchr (token, 'h'))
 	    {
-	      if (insn.operand_type[0]->immediate.u_number > 0x00FFFFFF)
-		as_warn ("first operand is too large for a 24-bit displacement");
-	      insn.opcode |= (insn.operand_type[0]->immediate.u_number & 0x00FFFFFF);
-	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	      char *save_input_line_pointer;
+	      segT retval;
+
+	      debug ("Probably a label: %s\n", token);
+	      current_op->immediate.label = malloc (strlen (token) + 1);
+	      strcpy (current_op->immediate.label, token);
+	      current_op->immediate.label[strlen (token)] = '\0';
+	      save_input_line_pointer = input_line_pointer;
+	      input_line_pointer = token;
+
+	      debug ("Current input_line_pointer: %s\n", input_line_pointer);
+	      retval = expression (&current_op->immediate.imm_expr);
+	      debug ("Expression type: %d\n",
+		     current_op->immediate.imm_expr.X_op);
+	      debug ("Expression addnum: %ld\n",
+		     (long) current_op->immediate.imm_expr.X_add_number);
+	      debug ("Segment: %p\n", retval);
+	      input_line_pointer = save_input_line_pointer;
+
+	      if (current_op->immediate.imm_expr.X_op == O_constant)
+		{
+		  current_op->immediate.s_number
+		    = current_op->immediate.imm_expr.X_add_number;
+		  current_op->immediate.u_number
+		    = (unsigned int) current_op->immediate.imm_expr.X_add_number;
+		  current_op->immediate.resolved = 1;
+		}
 	    }
 	  else
 	    {
-	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-	      fix_new_exp (frag_now, p + 1 - (frag_now->fr_literal), 3, &insn.operand_type[0]->immediate.imm_expr, 0, 0);
+	      unsigned count;
+
+	      debug ("Found a number or displacement\n");
+	      for (count = 0; count < strlen (token); count++)
+		if (*(token + count) == '.')
+		  current_op->immediate.decimal_found = 1;
+	      current_op->immediate.label = malloc (strlen (token) + 1);
+	      strcpy (current_op->immediate.label, token);
+	      current_op->immediate.label[strlen (token)] = '\0';
+	      current_op->immediate.f_number = (float) atof (token);
+	      current_op->immediate.s_number = (int) atoi (token);
+	      current_op->immediate.u_number = (unsigned int) atoi (token);
+	      current_op->immediate.resolved = 1;
 	    }
-	}
-      else if (insn.tm->operand_types[0] & NotReq)
-	{
-	  /* Check for NOP instruction without arguments.  */
-	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
-	}
-      else if (insn.tm->operands == 0)
-	{
-	  /* Check for instructions without operands.  */
-	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	  current_op->op_type = Disp | Abs24 | Imm16 | Imm24;
+	  if (current_op->immediate.u_number <= 31)
+	    current_op->op_type |= IVector;
 	}
     }
-  debug ("Addressing mode: %08X\n", insn.addressing_mode);
-  {
-    unsigned int i;
-    for (i = 0; i < insn.operands; i++)
-      {
-	if (insn.operand_type[i]->immediate.label)
-	  free (insn.operand_type[i]->immediate.label);
-	free (insn.operand_type[i]);
-      }
-  }
-  debug ("Final opcode: %08X\n", insn.opcode);
-  debug ("\n");
+  return current_op;
 }
 
-struct tic30_par_insn {
-  partemplate *tm;		/* Template of current parallel instruction */
-  unsigned operands[2];		/* Number of given operands for each insn */
-  /* Type of operand given in instruction */
+struct tic30_par_insn
+{
+  partemplate *tm;		/* Template of current parallel instruction.  */
+  unsigned operands[2];		/* Number of given operands for each insn.  */
+  /* Type of operand given in instruction.  */
   operand *operand_type[2][MAX_OPERANDS];
   int swap_operands;		/* Whether to swap operands around.  */
-  unsigned p_field;		/* Value of p field in multiply add/sub instructions */
-  unsigned opcode;		/* Final opcode */
+  unsigned p_field;		/* Value of p field in multiply add/sub instructions.  */
+  unsigned opcode;		/* Final opcode.  */
 };
 
 struct tic30_par_insn p_insn;
 
-int
+static int
 tic30_parallel_insn (char *token)
 {
   static partemplate *p_opcode;
@@ -800,9 +664,11 @@ tic30_parallel_insn (char *token)
 
   debug ("In tic30_parallel_insn with %s\n", token);
   memset (&p_insn, '\0', sizeof (p_insn));
+
   while (is_opcode_char (*current_posn))
     current_posn++;
-  {				/* Find instruction */
+  {
+    /* Find instruction.  */
     save_char = *current_posn;
     *current_posn = '\0';
     p_opcode = (partemplate *) hash_find (parop_hash, token);
@@ -813,10 +679,8 @@ tic30_parallel_insn (char *token)
       }
     else
       {
-	char first_opcode[6] =
-	{0};
-	char second_opcode[6] =
-	{0};
+	char first_opcode[6] = {0};
+	char second_opcode[6] = {0};
 	unsigned int i;
 	int current_opcode = -1;
 	int char_ptr = 0;
@@ -824,17 +688,20 @@ tic30_parallel_insn (char *token)
 	for (i = 0; i < strlen (token); i++)
 	  {
 	    char ch = *(token + i);
+
 	    if (ch == '_' && current_opcode == -1)
 	      {
 		current_opcode = 0;
 		continue;
 	      }
+
 	    if (ch == '_' && current_opcode == 0)
 	      {
 		current_opcode = 1;
 		char_ptr = 0;
 		continue;
 	      }
+
 	    switch (current_opcode)
 	      {
 	      case 0:
@@ -845,10 +712,12 @@ tic30_parallel_insn (char *token)
 		break;
 	      }
 	  }
+
 	debug ("first_opcode = %s\n", first_opcode);
 	debug ("second_opcode = %s\n", second_opcode);
 	sprintf (token, "q_%s_%s", second_opcode, first_opcode);
 	p_opcode = (partemplate *) hash_find (parop_hash, token);
+
 	if (p_opcode)
 	  {
 	    debug ("Found instruction %s\n", p_opcode->name);
@@ -860,16 +729,21 @@ tic30_parallel_insn (char *token)
       }
     *current_posn = save_char;
   }
-  {				/* Find operands */
+
+  {
+    /* Find operands.  */
     int paren_not_balanced;
     int expecting_operand = 0;
     int found_separator = 0;
+
     do
       {
-	/* skip optional white space before operand */
-	while (!is_operand_char (*current_posn) && *current_posn != END_OF_INSN)
+	/* Skip optional white space before operand.  */
+	while (!is_operand_char (*current_posn)
+	       && *current_posn != END_OF_INSN)
 	  {
-	    if (!is_space_char (*current_posn) && *current_posn != PARALLEL_SEPARATOR)
+	    if (!is_space_char (*current_posn)
+		&& *current_posn != PARALLEL_SEPARATOR)
 	      {
 		as_bad ("Invalid character %s before %s operand",
 			output_invalid (*current_posn),
@@ -880,8 +754,10 @@ tic30_parallel_insn (char *token)
 	      found_separator = 1;
 	    current_posn++;
 	  }
-	token_start = current_posn;	/* after white space */
+
+	token_start = current_posn;
 	paren_not_balanced = 0;
+
 	while (paren_not_balanced || *current_posn != ',')
 	  {
 	    if (*current_posn == END_OF_INSN)
@@ -893,7 +769,7 @@ tic30_parallel_insn (char *token)
 		    return 1;
 		  }
 		else
-		  break;	/* we are done */
+		  break;
 	      }
 	    else if (*current_posn == PARALLEL_SEPARATOR)
 	      {
@@ -901,21 +777,25 @@ tic30_parallel_insn (char *token)
 		  current_posn--;
 		break;
 	      }
-	    else if (!is_operand_char (*current_posn) && !is_space_char (*current_posn))
+	    else if (!is_operand_char (*current_posn)
+		     && !is_space_char (*current_posn))
 	      {
 		as_bad ("Invalid character %s in %s operand",
 			output_invalid (*current_posn),
 			ordinal_names[insn.operands]);
 		return 1;
 	      }
+
 	    if (*current_posn == '(')
 	      ++paren_not_balanced;
 	    if (*current_posn == ')')
 	      --paren_not_balanced;
 	    current_posn++;
 	  }
+
 	if (current_posn != token_start)
-	  {			/* yes, we've read in another operand */
+	  {
+	    /* Yes, we've read in another operand.  */
 	    p_insn.operands[found_separator]++;
 	    if (p_insn.operands[found_separator] > MAX_OPERANDS)
 	      {
@@ -923,7 +803,8 @@ tic30_parallel_insn (char *token)
 			MAX_OPERANDS);
 		return 1;
 	      }
-	    /* now parse operand adding info to 'insn' as we go along */
+
+	    /* Now parse operand adding info to 'insn' as we go along.  */
 	    save_char = *current_posn;
 	    *current_posn = '\0';
 	    p_insn.operand_type[found_separator][p_insn.operands[found_separator] - 1] =
@@ -945,19 +826,22 @@ tic30_parallel_insn (char *token)
 		return 1;
 	      }
 	  }
-	/* now *current_posn must be either ',' or END_OF_INSN */
+
+	/* Now *current_posn must be either ',' or END_OF_INSN.  */
 	if (*current_posn == ',')
 	  {
 	    if (*++current_posn == END_OF_INSN)
-	      {			/* just skip it, if it's \n complain */
+	      {
+		/* Just skip it, if it's \n complain.  */
 		as_bad ("Expecting operand after ','; got nothing");
 		return 1;
 	      }
 	    expecting_operand = 1;
 	  }
       }
-    while (*current_posn != END_OF_INSN);	/* until we get end of insn */
+    while (*current_posn != END_OF_INSN);
   }
+
   if (p_insn.swap_operands)
     {
       int temp_num, i;
@@ -973,22 +857,28 @@ tic30_parallel_insn (char *token)
 	  p_insn.operand_type[1][i] = temp_op;
 	}
     }
+
   if (p_insn.operands[0] != p_insn.tm->operands_1)
     {
       as_bad ("incorrect number of operands given in the first instruction");
       return 1;
     }
+
   if (p_insn.operands[1] != p_insn.tm->operands_2)
     {
       as_bad ("incorrect number of operands given in the second instruction");
       return 1;
     }
+
   debug ("Number of operands in first insn: %d\n", p_insn.operands[0]);
   debug ("Number of operands in second insn: %d\n", p_insn.operands[1]);
-  {				/* Now check if operands are correct */
+
+  {
+    /* Now check if operands are correct.  */
     int count;
     int num_rn = 0;
     int num_ind = 0;
+
     for (count = 0; count < 2; count++)
       {
 	unsigned int i;
@@ -997,64 +887,76 @@ tic30_parallel_insn (char *token)
 	    if ((p_insn.operand_type[count][i]->op_type &
 		 p_insn.tm->operand_types[count][i]) == 0)
 	      {
-		as_bad ("%s instruction, operand %d doesn't match", ordinal_names[count], i + 1);
+		as_bad ("%s instruction, operand %d doesn't match",
+			ordinal_names[count], i + 1);
 		return 1;
 	      }
-	    /* Get number of R register and indirect reference contained within the first
-	       two operands of each instruction.  This is required for the multiply
-	       parallel instructions which require two R registers and two indirect
-	       references, but not in any particular place.  */
+
+	    /* Get number of R register and indirect reference contained
+	       within the first two operands of each instruction.  This is
+	       required for the multiply parallel instructions which require
+	       two R registers and two indirect references, but not in any
+	       particular place.  */
 	    if ((p_insn.operand_type[count][i]->op_type & Rn) && i < 2)
 	      num_rn++;
-	    else if ((p_insn.operand_type[count][i]->op_type & Indirect) && i < 2)
+	    else if ((p_insn.operand_type[count][i]->op_type & Indirect)
+		     && i < 2)
 	      num_ind++;
 	  }
       }
-    if ((p_insn.tm->operand_types[0][0] & (Indirect | Rn)) == (Indirect | Rn))
+
+    if ((p_insn.tm->operand_types[0][0] & (Indirect | Rn))
+	== (Indirect | Rn))
       {
-	/* Check for the multiply instructions */
+	/* Check for the multiply instructions.  */
 	if (num_rn != 2)
 	  {
 	    as_bad ("incorrect format for multiply parallel instruction");
 	    return 1;
 	  }
+
 	if (num_ind != 2)
-	  {			/* Shouldn't get here */
+	  {
+	    /* Shouldn't get here.  */
 	    as_bad ("incorrect format for multiply parallel instruction");
 	    return 1;
 	  }
-	if ((p_insn.operand_type[0][2]->reg.opcode != 0x00) &&
-	    (p_insn.operand_type[0][2]->reg.opcode != 0x01))
+
+	if ((p_insn.operand_type[0][2]->reg.opcode != 0x00)
+	    && (p_insn.operand_type[0][2]->reg.opcode != 0x01))
 	  {
 	    as_bad ("destination for multiply can only be R0 or R1");
 	    return 1;
 	  }
-	if ((p_insn.operand_type[1][2]->reg.opcode != 0x02) &&
-	    (p_insn.operand_type[1][2]->reg.opcode != 0x03))
+
+	if ((p_insn.operand_type[1][2]->reg.opcode != 0x02)
+	    && (p_insn.operand_type[1][2]->reg.opcode != 0x03))
 	  {
 	    as_bad ("destination for add/subtract can only be R2 or R3");
 	    return 1;
 	  }
-	/* Now determine the P field for the instruction */
+
+	/* Now determine the P field for the instruction.  */
 	if (p_insn.operand_type[0][0]->op_type & Indirect)
 	  {
 	    if (p_insn.operand_type[0][1]->op_type & Indirect)
-	      p_insn.p_field = 0x00000000;	/* Ind * Ind, Rn  +/- Rn  */
+	      p_insn.p_field = 0x00000000;	/* Ind * Ind, Rn  +/- Rn.  */
 	    else if (p_insn.operand_type[1][0]->op_type & Indirect)
-	      p_insn.p_field = 0x01000000;	/* Ind * Rn,  Ind +/- Rn  */
+	      p_insn.p_field = 0x01000000;	/* Ind * Rn,  Ind +/- Rn.  */
 	    else
-	      p_insn.p_field = 0x03000000;	/* Ind * Rn,  Rn  +/- Ind */
+	      p_insn.p_field = 0x03000000;	/* Ind * Rn,  Rn  +/- Ind.  */
 	  }
 	else
 	  {
 	    if (p_insn.operand_type[0][1]->op_type & Rn)
-	      p_insn.p_field = 0x02000000;	/* Rn  * Rn,  Ind +/- Ind */
+	      p_insn.p_field = 0x02000000;	/* Rn  * Rn,  Ind +/- Ind.  */
 	    else if (p_insn.operand_type[1][0]->op_type & Indirect)
 	      {
 		operand *temp;
-		p_insn.p_field = 0x01000000;	/* Rn  * Ind, Ind +/- Rn  */
-		/* Need to swap the two multiply operands around so that everything is in
-		   its place for the opcode makeup ie so Ind * Rn, Ind +/- Rn */
+		p_insn.p_field = 0x01000000;	/* Rn  * Ind, Ind +/- Rn.  */
+		/* Need to swap the two multiply operands around so that
+		   everything is in its place for the opcode makeup.
+		   ie so Ind * Rn, Ind +/- Rn.  */
 		temp = p_insn.operand_type[0][0];
 		p_insn.operand_type[0][0] = p_insn.operand_type[0][1];
 		p_insn.operand_type[0][1] = temp;
@@ -1062,7 +964,7 @@ tic30_parallel_insn (char *token)
 	    else
 	      {
 		operand *temp;
-		p_insn.p_field = 0x03000000;	/* Rn  * Ind, Rn  +/- Ind */
+		p_insn.p_field = 0x03000000;	/* Rn  * Ind, Rn  +/- Ind.  */
 		temp = p_insn.operand_type[0][0];
 		p_insn.operand_type[0][0] = p_insn.operand_type[0][1];
 		p_insn.operand_type[0][1] = temp;
@@ -1070,476 +972,161 @@ tic30_parallel_insn (char *token)
 	  }
       }
   }
+
   debug ("P field: %08X\n", p_insn.p_field);
-  /* Finalise opcode.  This is easier for parallel instructions as they have to be
-     fully resolved, there are no memory addresses allowed, except through indirect
-     addressing, so there are no labels to resolve.  */
-  {
-    p_insn.opcode = p_insn.tm->base_opcode;
-    switch (p_insn.tm->oporder)
-      {
-      case OO_4op1:
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
-	p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 22);
-	break;
-      case OO_4op2:
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum << 8);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 11);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 19);
-	p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 22);
-	if (p_insn.operand_type[1][1]->reg.opcode == p_insn.operand_type[0][1]->reg.opcode)
-	  as_warn ("loading the same register in parallel operation");
-	break;
-      case OO_4op3:
-	p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
-	p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
-	p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 22);
-	break;
-      case OO_5op1:
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
-	p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
-	p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
-	p_insn.opcode |= (p_insn.operand_type[0][2]->reg.opcode << 22);
-	break;
-      case OO_5op2:
-	p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
-	p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
-	p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
-	p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
-	p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 19);
-	p_insn.opcode |= (p_insn.operand_type[0][2]->reg.opcode << 22);
-	break;
-      case OO_PField:
-	p_insn.opcode |= p_insn.p_field;
-	if (p_insn.operand_type[0][2]->reg.opcode == 0x01)
-	  p_insn.opcode |= 0x00800000;
-	if (p_insn.operand_type[1][2]->reg.opcode == 0x03)
-	  p_insn.opcode |= 0x00400000;
-	switch (p_insn.p_field)
-	  {
-	  case 0x00000000:
-	    p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
-	    p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 16);
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 19);
-	    break;
-	  case 0x01000000:
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum);
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 3);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 16);
-	    p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
-	    break;
-	  case 0x02000000:
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum);
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 3);
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum << 8);
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 11);
-	    p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 16);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 19);
-	    break;
-	  case 0x03000000:
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum);
-	    p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 3);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
-	    p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
-	    p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
-	    p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
-	    break;
-	  }
-	break;
-      }
-  }				/* Opcode is finalised at this point for all parallel instructions.  */
-  {				/* Output opcode */
-    char *p;
-    p = frag_more (INSN_SIZE);
-    md_number_to_chars (p, (valueT) p_insn.opcode, INSN_SIZE);
-  }
-  {
-    unsigned int i, j;
-    for (i = 0; i < 2; i++)
-      for (j = 0; j < p_insn.operands[i]; j++)
-	free (p_insn.operand_type[i][j]);
-  }
-  debug ("Final opcode: %08X\n", p_insn.opcode);
-  debug ("\n");
-  return 1;
-}
 
-operand *
-tic30_operand (token)
-     char *token;
-{
-  unsigned int count;
-  char ind_buffer[strlen (token)];
-  operand *current_op;
+  /* Finalise opcode.  This is easier for parallel instructions as they have
+     to be fully resolved, there are no memory addresses allowed, except
+     through indirect addressing, so there are no labels to resolve.  */
+  p_insn.opcode = p_insn.tm->base_opcode;
 
-  debug ("In tic30_operand with %s\n", token);
-  current_op = (operand *) malloc (sizeof (operand));
-  memset (current_op, '\0', sizeof (operand));
-  if (*token == DIRECT_REFERENCE)
+  switch (p_insn.tm->oporder)
     {
-      char *token_posn = token + 1;
-      int direct_label = 0;
-      debug ("Found direct reference\n");
-      while (*token_posn)
-	{
-	  if (!is_digit_char (*token_posn))
-	    direct_label = 1;
-	  token_posn++;
-	}
-      if (direct_label)
-	{
-	  char *save_input_line_pointer;
-	  segT retval;
-	  debug ("Direct reference is a label\n");
-	  current_op->direct.label = token + 1;
-	  save_input_line_pointer = input_line_pointer;
-	  input_line_pointer = token + 1;
-	  debug ("Current input_line_pointer: %s\n", input_line_pointer);
-	  retval = expression (&current_op->direct.direct_expr);
-	  debug ("Expression type: %d\n", current_op->direct.direct_expr.X_op);
-	  debug ("Expression addnum: %d\n", current_op->direct.direct_expr.X_add_number);
-	  debug ("Segment: %d\n", retval);
-	  input_line_pointer = save_input_line_pointer;
-	  if (current_op->direct.direct_expr.X_op == O_constant)
-	    {
-	      current_op->direct.address = current_op->direct.direct_expr.X_add_number;
-	      current_op->direct.resolved = 1;
-	    }
-	}
-      else
-	{
-	  debug ("Direct reference is a number\n");
-	  current_op->direct.address = atoi (token + 1);
-	  current_op->direct.resolved = 1;
-	}
-      current_op->op_type = Direct;
-    }
-  else if (*token == INDIRECT_REFERENCE)
-    {				/* Indirect reference operand */
-      int found_ar = 0;
-      int found_disp = 0;
-      int ar_number = -1;
-      int disp_number = 0;
-      int buffer_posn = 1;
-      ind_addr_type *ind_addr_op;
-      debug ("Found indirect reference\n");
-      ind_buffer[0] = *token;
-      for (count = 1; count < strlen (token); count++)
-	{			/* Strip operand */
-	  ind_buffer[buffer_posn] = TOLOWER (*(token + count));
-	  if ((*(token + count - 1) == 'a' || *(token + count - 1) == 'A') &&
-	      (*(token + count) == 'r' || *(token + count) == 'R'))
-	    {
-	      /* AR reference is found, so get its number and remove it from the buffer
-	         so it can pass through hash_find() */
-	      if (found_ar)
-		{
-		  as_bad ("More than one AR register found in indirect reference");
-		  return NULL;
-		}
-	      if (*(token + count + 1) < '0' || *(token + count + 1) > '7')
-		{
-		  as_bad ("Illegal AR register in indirect reference");
-		  return NULL;
-		}
-	      ar_number = *(token + count + 1) - '0';
-	      found_ar = 1;
-	      count++;
-	    }
-	  if (*(token + count) == '(')
-	    {
-	      /* Parenthesis found, so check if a displacement value is inside.  If so, get
-	         the value and remove it from the buffer.  */
-	      if (is_digit_char (*(token + count + 1)))
-		{
-		  char disp[10];
-		  int disp_posn = 0;
+    case OO_4op1:
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
+      p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 22);
+      break;
 
-		  if (found_disp)
-		    {
-		      as_bad ("More than one displacement found in indirect reference");
-		      return NULL;
-		    }
-		  count++;
-		  while (*(token + count) != ')')
-		    {
-		      if (!is_digit_char (*(token + count)))
-			{
-			  as_bad ("Invalid displacement in indirect reference");
-			  return NULL;
-			}
-		      disp[disp_posn++] = *(token + (count++));
-		    }
-		  disp[disp_posn] = '\0';
-		  disp_number = atoi (disp);
-		  count--;
-		  found_disp = 1;
-		}
-	    }
-	  buffer_posn++;
-	}
-      ind_buffer[buffer_posn] = '\0';
-      if (!found_ar)
-	{
-	  as_bad ("AR register not found in indirect reference");
-	  return NULL;
-	}
-      ind_addr_op = (ind_addr_type *) hash_find (ind_hash, ind_buffer);
-      if (ind_addr_op)
-	{
-	  debug ("Found indirect reference: %s\n", ind_addr_op->syntax);
-	  if (ind_addr_op->displacement == IMPLIED_DISP)
-	    {
-	      found_disp = 1;
-	      disp_number = 1;
-	    }
-	  else if ((ind_addr_op->displacement == DISP_REQUIRED) && !found_disp)
-	    {
-	      /* Maybe an implied displacement of 1 again */
-	      as_bad ("required displacement wasn't given in indirect reference");
-	      return 0;
-	    }
-	}
-      else
-	{
-	  as_bad ("illegal indirect reference");
-	  return NULL;
-	}
-      if (found_disp && (disp_number < 0 || disp_number > 255))
-	{
-	  as_bad ("displacement must be an unsigned 8-bit number");
-	  return NULL;
-	}
-      current_op->indirect.mod = ind_addr_op->modfield;
-      current_op->indirect.disp = disp_number;
-      current_op->indirect.ARnum = ar_number;
-      current_op->op_type = Indirect;
-    }
-  else
-    {
-      reg *regop = (reg *) hash_find (reg_hash, token);
-      if (regop)
-	{
-	  debug ("Found register operand: %s\n", regop->name);
-	  if (regop->regtype == REG_ARn)
-	    current_op->op_type = ARn;
-	  else if (regop->regtype == REG_Rn)
-	    current_op->op_type = Rn;
-	  else if (regop->regtype == REG_DP)
-	    current_op->op_type = DPReg;
-	  else
-	    current_op->op_type = OtherReg;
-	  current_op->reg.opcode = regop->opcode;
-	}
-      else
-	{
-	  if (!is_digit_char (*token) || *(token + 1) == 'x' || strchr (token, 'h'))
-	    {
-	      char *save_input_line_pointer;
-	      segT retval;
-	      debug ("Probably a label: %s\n", token);
-	      current_op->immediate.label = (char *) malloc (strlen (token) + 1);
-	      strcpy (current_op->immediate.label, token);
-	      current_op->immediate.label[strlen (token)] = '\0';
-	      save_input_line_pointer = input_line_pointer;
-	      input_line_pointer = token;
-	      debug ("Current input_line_pointer: %s\n", input_line_pointer);
-	      retval = expression (&current_op->immediate.imm_expr);
-	      debug ("Expression type: %d\n", current_op->immediate.imm_expr.X_op);
-	      debug ("Expression addnum: %d\n", current_op->immediate.imm_expr.X_add_number);
-	      debug ("Segment: %d\n", retval);
-	      input_line_pointer = save_input_line_pointer;
-	      if (current_op->immediate.imm_expr.X_op == O_constant)
-		{
-		  current_op->immediate.s_number = current_op->immediate.imm_expr.X_add_number;
-		  current_op->immediate.u_number = (unsigned int) current_op->immediate.imm_expr.X_add_number;
-		  current_op->immediate.resolved = 1;
-		}
-	    }
-	  else
-	    {
-	      unsigned count;
-	      debug ("Found a number or displacement\n");
-	      for (count = 0; count < strlen (token); count++)
-		if (*(token + count) == '.')
-		  current_op->immediate.decimal_found = 1;
-	      current_op->immediate.label = (char *) malloc (strlen (token) + 1);
-	      strcpy (current_op->immediate.label, token);
-	      current_op->immediate.label[strlen (token)] = '\0';
-	      current_op->immediate.f_number = (float) atof (token);
-	      current_op->immediate.s_number = (int) atoi (token);
-	      current_op->immediate.u_number = (unsigned int) atoi (token);
-	      current_op->immediate.resolved = 1;
-	    }
-	  current_op->op_type = Disp | Abs24 | Imm16 | Imm24;
-	  if (current_op->immediate.u_number <= 31)
-	    current_op->op_type |= IVector;
-	}
-    }
-  return current_op;
-}
+    case OO_4op2:
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum << 8);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 11);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 19);
+      p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 22);
+      if (p_insn.operand_type[1][1]->reg.opcode == p_insn.operand_type[0][1]->reg.opcode)
+	as_warn ("loading the same register in parallel operation");
+      break;
 
-/* next_line points to the next line after the current instruction (current_line).
-   Search for the parallel bars, and if found, merge two lines into internal syntax
-   for a parallel instruction:
-   q_[INSN1]_[INSN2] [OPERANDS1] | [OPERANDS2]
-   By this stage, all comments are scrubbed, and only the bare lines are given.
- */
+    case OO_4op3:
+      p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
+      p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
+      p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 22);
+      break;
 
-#define NONE           0
-#define START_OPCODE   1
-#define END_OPCODE     2
-#define START_OPERANDS 3
-#define END_OPERANDS   4
+    case OO_5op1:
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum);
+      p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 3);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
+      p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
+      p_insn.opcode |= (p_insn.operand_type[0][2]->reg.opcode << 22);
+      break;
 
-char *
-tic30_find_parallel_insn (current_line, next_line)
-     char *current_line;
-     char *next_line;
-{
-  int found_parallel = 0;
-  char first_opcode[256];
-  char second_opcode[256];
-  char first_operands[256];
-  char second_operands[256];
-  char *parallel_insn;
+    case OO_5op2:
+      p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
+      p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum << 8);
+      p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 11);
+      p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
+      p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 19);
+      p_insn.opcode |= (p_insn.operand_type[0][2]->reg.opcode << 22);
+      break;
 
-  debug ("In tic30_find_parallel_insn()\n");
-  while (!is_end_of_line[(unsigned char) *next_line])
-    {
-      if (*next_line == PARALLEL_SEPARATOR && *(next_line + 1) == PARALLEL_SEPARATOR)
+    case OO_PField:
+      p_insn.opcode |= p_insn.p_field;
+      if (p_insn.operand_type[0][2]->reg.opcode == 0x01)
+	p_insn.opcode |= 0x00800000;
+      if (p_insn.operand_type[1][2]->reg.opcode == 0x03)
+	p_insn.opcode |= 0x00400000;
+
+      switch (p_insn.p_field)
 	{
-	  found_parallel = 1;
-	  next_line++;
+	case 0x00000000:
+	  p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.ARnum);
+	  p_insn.opcode |= (p_insn.operand_type[0][1]->indirect.mod << 3);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 16);
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 19);
+	  break;
+	case 0x01000000:
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum);
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 3);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->reg.opcode << 16);
+	  p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
+	  break;
+	case 0x02000000:
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum);
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 3);
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.ARnum << 8);
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->indirect.mod << 11);
+	  p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 16);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->reg.opcode << 19);
+	  break;
+	case 0x03000000:
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.ARnum);
+	  p_insn.opcode |= (p_insn.operand_type[1][1]->indirect.mod << 3);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.ARnum << 8);
+	  p_insn.opcode |= (p_insn.operand_type[0][0]->indirect.mod << 11);
+	  p_insn.opcode |= (p_insn.operand_type[1][0]->reg.opcode << 16);
+	  p_insn.opcode |= (p_insn.operand_type[0][1]->reg.opcode << 19);
 	  break;
 	}
-      next_line++;
+      break;
     }
-  if (!found_parallel)
-    return NULL;
-  debug ("Found a parallel instruction\n");
+
   {
-    int i;
-    char *opcode, *operands, *line;
+    char *p;
 
-    for (i = 0; i < 2; i++)
-      {
-	if (i == 0)
-	  {
-	    opcode = &first_opcode[0];
-	    operands = &first_operands[0];
-	    line = current_line;
-	  }
-	else
-	  {
-	    opcode = &second_opcode[0];
-	    operands = &second_operands[0];
-	    line = next_line;
-	  }
-	{
-	  int search_status = NONE;
-	  int char_ptr = 0;
-	  char c;
+    p = frag_more (INSN_SIZE);
+    md_number_to_chars (p, (valueT) p_insn.opcode, INSN_SIZE);
+  }
 
-	  while (!is_end_of_line[(unsigned char) (c = *line)])
-	    {
-	      if (is_opcode_char (c) && search_status == NONE)
-		{
-		  opcode[char_ptr++] = TOLOWER (c);
-		  search_status = START_OPCODE;
-		}
-	      else if (is_opcode_char (c) && search_status == START_OPCODE)
-		{
-		  opcode[char_ptr++] = TOLOWER (c);
-		}
-	      else if (!is_opcode_char (c) && search_status == START_OPCODE)
-		{
-		  opcode[char_ptr] = '\0';
-		  char_ptr = 0;
-		  search_status = END_OPCODE;
-		}
-	      else if (is_operand_char (c) && search_status == START_OPERANDS)
-		{
-		  operands[char_ptr++] = c;
-		}
-	      if (is_operand_char (c) && search_status == END_OPCODE)
-		{
-		  operands[char_ptr++] = c;
-		  search_status = START_OPERANDS;
-		}
-	      line++;
-	    }
-	  if (search_status != START_OPERANDS)
-	    return NULL;
-	  operands[char_ptr] = '\0';
-	}
-      }
+  {
+    unsigned int i, j;
+
+    for (i = 0; i < 2; i++)
+      for (j = 0; j < p_insn.operands[i]; j++)
+	free (p_insn.operand_type[i][j]);
   }
-  parallel_insn = (char *) malloc (strlen (first_opcode) + strlen (first_operands) +
-		     strlen (second_opcode) + strlen (second_operands) + 8);
-  sprintf (parallel_insn, "q_%s_%s %s | %s", first_opcode, second_opcode, first_operands, second_operands);
-  debug ("parallel insn = %s\n", parallel_insn);
-  return parallel_insn;
-}
 
-#undef NONE
-#undef START_OPCODE
-#undef END_OPCODE
-#undef START_OPERANDS
-#undef END_OPERANDS
+  debug ("Final opcode: %08X\n", p_insn.opcode);
+  debug ("\n");
+
+  return 1;
+}
 
 /* In order to get gas to ignore any | chars at the start of a line,
    this function returns true if a | is found in a line.  */
 
 int
-tic30_unrecognized_line (c)
-     int c;
+tic30_unrecognized_line (int c)
 {
   debug ("In tc_unrecognized_line\n");
   return (c == PARALLEL_SEPARATOR);
 }
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP ATTRIBUTE_UNUSED;
-     segT segment ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+			       segT segment ATTRIBUTE_UNUSED)
 {
   debug ("In md_estimate_size_before_relax()\n");
   return 0;
 }
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     register fragS *fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 register fragS *fragP ATTRIBUTE_UNUSED)
 {
   debug ("In md_convert_frag()\n");
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP,
+	       valueT *valP,
+	       segT seg ATTRIBUTE_UNUSED)
 {
   valueT value = *valP;
 
@@ -1547,7 +1134,7 @@ md_apply_fix3 (fixP, valP, seg)
   debug ("Values in fixP\n");
   debug ("fx_size = %d\n", fixP->fx_size);
   debug ("fx_pcrel = %d\n", fixP->fx_pcrel);
-  debug ("fx_where = %d\n", fixP->fx_where);
+  debug ("fx_where = %ld\n", fixP->fx_where);
   debug ("fx_offset = %d\n", (int) fixP->fx_offset);
   {
     char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
@@ -1566,53 +1153,49 @@ md_apply_fix3 (fixP, valP, seg)
 }
 
 int
-md_parse_option (c, arg)
-     int c ATTRIBUTE_UNUSED;
-     char *arg ATTRIBUTE_UNUSED;
+md_parse_option (int c ATTRIBUTE_UNUSED,
+		 char *arg ATTRIBUTE_UNUSED)
 {
   debug ("In md_parse_option()\n");
   return 0;
 }
 
 void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
+md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
 {
   debug ("In md_show_usage()\n");
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   debug ("In md_undefined_symbol()\n");
   return (symbolS *) 0;
 }
 
 valueT
-md_section_align (segment, size)
-     segT segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
-  debug ("In md_section_align() segment = %d and size = %d\n", segment, size);
+  debug ("In md_section_align() segment = %p and size = %lu\n",
+	 segment, (unsigned long) size);
   size = (size + 3) / 4;
   size *= 4;
-  debug ("New size value = %d\n", size);
+  debug ("New size value = %lu\n", (unsigned long) size);
   return size;
 }
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   int offset;
 
   debug ("In md_pcrel_from()\n");
-  debug ("fx_where = %d\n", fixP->fx_where);
+  debug ("fx_where = %ld\n", fixP->fx_where);
   debug ("fx_size = %d\n", fixP->fx_size);
-  /* Find the opcode that represents the current instruction in the fr_literal
-     storage area, and check bit 21.  Bit 21 contains whether the current instruction
-     is a delayed one or not, and then set the offset value appropriately.  */
+  /* Find the opcode that represents the current instruction in the
+     fr_literal storage area, and check bit 21.  Bit 21 contains whether the
+     current instruction is a delayed one or not, and then set the offset
+     value appropriately.  */
   if (fixP->fx_frag->fr_literal[fixP->fx_where - fixP->fx_size + 1] & 0x20)
     offset = 3;
   else
@@ -1622,22 +1205,21 @@ md_pcrel_from (fixP)
      displacement = Label - (PC + offset)
      This function returns PC + offset where:
      fx_where - fx_size = PC
-     INSN_SIZE * offset = offset number of instructions
-   */
+     INSN_SIZE * offset = offset number of instructions.  */
   return fixP->fx_where - fixP->fx_size + (INSN_SIZE * offset);
 }
 
 char *
-md_atof (what_statement_type, literalP, sizeP)
-     int what_statement_type;
-     char *literalP;
-     int *sizeP;
+md_atof (int what_statement_type,
+	 char *literalP,
+	 int *sizeP)
 {
   int prec;
   char *token;
   char keepval;
   unsigned long value;
   float float_value;
+
   debug ("In md_atof()\n");
   debug ("precision = %c\n", what_statement_type);
   debug ("literal = %s\n", literalP);
@@ -1649,12 +1231,14 @@ md_atof (what_statement_type, literalP, sizeP)
       debug ("%c", *input_line_pointer);
       input_line_pointer++;
     }
+
   keepval = *input_line_pointer;
   *input_line_pointer = '\0';
   debug ("\n");
   float_value = (float) atof (token);
   *input_line_pointer = keepval;
   debug ("float_value = %f\n", float_value);
+
   switch (what_statement_type)
     {
     case 'f':
@@ -1675,14 +1259,21 @@ md_atof (what_statement_type, literalP, sizeP)
       *sizeP = 0;
       return "Bad call to MD_ATOF()";
     }
+
   if (float_value == 0.0)
-    {
-      value = (prec == 2) ? 0x00008000L : 0x80000000L;
-    }
+    value = (prec == 2) ? 0x00008000L : 0x80000000L;
   else
     {
       unsigned long exp, sign, mant, tmsfloat;
-      tmsfloat = *((long *) &float_value);
+      union
+      {
+	float f;
+	long  l;
+      }
+      converter;
+
+      converter.f = float_value;
+      tmsfloat = converter.l;
       sign = tmsfloat & 0x80000000;
       mant = tmsfloat & 0x007FFFFF;
       exp = tmsfloat & 0x7F800000;
@@ -1718,9 +1309,7 @@ md_atof (what_statement_type, literalP, sizeP)
 	  long exp, mant;
 
 	  if (tmsfloat == 0x80000000)
-	    {
-	      value = 0x8000;
-	    }
+	    value = 0x8000;
 	  else
 	    {
 	      value = 0;
@@ -1763,23 +1352,17 @@ md_atof (what_statement_type, literalP, sizeP)
 }
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   debug ("In md_number_to_chars()\n");
   number_to_chars_bigendian (buf, val, n);
-  /*  number_to_chars_littleendian(buf,val,n); */
 }
 
 #define F(SZ,PCREL)		(((SZ) << 1) + (PCREL))
 #define MAP(SZ,PCREL,TYPE)	case F(SZ,PCREL): code = (TYPE); break
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
 {
   arelent *rel;
   bfd_reloc_code_real_type code = 0;
@@ -1788,6 +1371,7 @@ tc_gen_reloc (section, fixP)
   debug ("fixP.size = %d\n", fixP->fx_size);
   debug ("fixP.pcrel = %d\n", fixP->fx_pcrel);
   debug ("addsy.name = %s\n", S_GET_NAME (fixP->fx_addsy));
+
   switch (F (fixP->fx_size, fixP->fx_pcrel))
     {
       MAP (1, 0, BFD_RELOC_TIC30_LDP);
@@ -1802,9 +1386,9 @@ tc_gen_reloc (section, fixP)
 #undef MAP
 #undef F
 
-  rel = (arelent *) xmalloc (sizeof (arelent));
+  rel = xmalloc (sizeof (* rel));
   assert (rel != 0);
-  rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *rel->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   rel->address = fixP->fx_frag->fr_address + fixP->fx_where;
   rel->addend = 0;
@@ -1812,30 +1396,610 @@ tc_gen_reloc (section, fixP)
   if (!rel->howto)
     {
       const char *name;
+
       name = S_GET_NAME (fixP->fx_addsy);
       if (name == NULL)
 	name = "<unknown>";
-      as_fatal ("Cannot generate relocation type for symbol %s, code %s", name, bfd_get_reloc_code_name (code));
+      as_fatal ("Cannot generate relocation type for symbol %s, code %s",
+		name, bfd_get_reloc_code_name (code));
     }
   return rel;
 }
 
 void
-md_operand (expressionP)
-     expressionS *expressionP ATTRIBUTE_UNUSED;
+md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
 {
   debug ("In md_operand()\n");
 }
 
-char output_invalid_buf[8];
-
-char *
-output_invalid (c)
-     char c;
+void
+md_assemble (char *line)
 {
-  if (ISPRINT (c))
-    sprintf (output_invalid_buf, "'%c'", c);
+  template *opcode;
+  char *current_posn;
+  char *token_start;
+  char save_char;
+  unsigned int count;
+
+  debug ("In md_assemble() with argument %s\n", line);
+  memset (&insn, '\0', sizeof (insn));
+  if (found_parallel_insn)
+    {
+      debug ("Line is second part of parallel instruction\n\n");
+      found_parallel_insn = 0;
+      return;
+    }
+  if ((current_posn =
+       tic30_find_parallel_insn (line, input_line_pointer + 1)) == NULL)
+    current_posn = line;
   else
-    sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
-  return output_invalid_buf;
+    found_parallel_insn = 1;
+
+  while (is_space_char (*current_posn))
+    current_posn++;
+
+  token_start = current_posn;
+
+  if (!is_opcode_char (*current_posn))
+    {
+      as_bad ("Invalid character %s in opcode",
+	      output_invalid (*current_posn));
+      return;
+    }
+  /* Check if instruction is a parallel instruction
+     by seeing if the first character is a q.  */
+  if (*token_start == 'q')
+    {
+      if (tic30_parallel_insn (token_start))
+	{
+	  if (found_parallel_insn)
+	    free (token_start);
+	  return;
+	}
+    }
+  while (is_opcode_char (*current_posn))
+    current_posn++;
+  {
+    /* Find instruction.  */
+    save_char = *current_posn;
+    *current_posn = '\0';
+    opcode = (template *) hash_find (op_hash, token_start);
+    if (opcode)
+      {
+	debug ("Found instruction %s\n", opcode->name);
+	insn.tm = opcode;
+      }
+    else
+      {
+	debug ("Didn't find insn\n");
+	as_bad ("Unknown TMS320C30 instruction: %s", token_start);
+	return;
+      }
+    *current_posn = save_char;
+  }
+
+  if (*current_posn != END_OF_INSN)
+    {
+      /* Find operands.  */
+      int paren_not_balanced;
+      int expecting_operand = 0;
+      int this_operand;
+      do
+	{
+	  /* Skip optional white space before operand.  */
+	  while (!is_operand_char (*current_posn)
+		 && *current_posn != END_OF_INSN)
+	    {
+	      if (!is_space_char (*current_posn))
+		{
+		  as_bad ("Invalid character %s before %s operand",
+			  output_invalid (*current_posn),
+			  ordinal_names[insn.operands]);
+		  return;
+		}
+	      current_posn++;
+	    }
+	  token_start = current_posn;
+	  paren_not_balanced = 0;
+	  while (paren_not_balanced || *current_posn != ',')
+	    {
+	      if (*current_posn == END_OF_INSN)
+		{
+		  if (paren_not_balanced)
+		    {
+		      as_bad ("Unbalanced parenthesis in %s operand.",
+			      ordinal_names[insn.operands]);
+		      return;
+		    }
+		  else
+		    break;
+		}
+	      else if (!is_operand_char (*current_posn)
+		       && !is_space_char (*current_posn))
+		{
+		  as_bad ("Invalid character %s in %s operand",
+			  output_invalid (*current_posn),
+			  ordinal_names[insn.operands]);
+		  return;
+		}
+	      if (*current_posn == '(')
+		++paren_not_balanced;
+	      if (*current_posn == ')')
+		--paren_not_balanced;
+	      current_posn++;
+	    }
+	  if (current_posn != token_start)
+	    {
+	      /* Yes, we've read in another operand.  */
+	      this_operand = insn.operands++;
+	      if (insn.operands > MAX_OPERANDS)
+		{
+		  as_bad ("Spurious operands; (%d operands/instruction max)",
+			  MAX_OPERANDS);
+		  return;
+		}
+
+	      /* Now parse operand adding info to 'insn' as we go along.  */
+	      save_char = *current_posn;
+	      *current_posn = '\0';
+	      insn.operand_type[this_operand] = tic30_operand (token_start);
+	      *current_posn = save_char;
+	      if (insn.operand_type[this_operand] == NULL)
+		return;
+	    }
+	  else
+	    {
+	      if (expecting_operand)
+		{
+		  as_bad ("Expecting operand after ','; got nothing");
+		  return;
+		}
+	      if (*current_posn == ',')
+		{
+		  as_bad ("Expecting operand before ','; got nothing");
+		  return;
+		}
+	    }
+
+	  /* Now *current_posn must be either ',' or END_OF_INSN.  */
+	  if (*current_posn == ',')
+	    {
+	      if (*++current_posn == END_OF_INSN)
+		{
+		  /* Just skip it, if it's \n complain.  */
+		  as_bad ("Expecting operand after ','; got nothing");
+		  return;
+		}
+	      expecting_operand = 1;
+	    }
+	}
+      while (*current_posn != END_OF_INSN);
+    }
+
+  debug ("Number of operands found: %d\n", insn.operands);
+
+  /* Check that number of operands is correct.  */
+  if (insn.operands != insn.tm->operands)
+    {
+      unsigned int i;
+      unsigned int numops = insn.tm->operands;
+
+      /* If operands are not the same, then see if any of the operands are
+	 not required.  Then recheck with number of given operands.  If they
+	 are still not the same, then give an error, otherwise carry on.  */
+      for (i = 0; i < insn.tm->operands; i++)
+	if (insn.tm->operand_types[i] & NotReq)
+	  numops--;
+      if (insn.operands != numops)
+	{
+	  as_bad ("Incorrect number of operands given");
+	  return;
+	}
+    }
+  insn.addressing_mode = AM_NotReq;
+  for (count = 0; count < insn.operands; count++)
+    {
+      if (insn.operand_type[count]->op_type & insn.tm->operand_types[count])
+	{
+	  debug ("Operand %d matches\n", count + 1);
+	  /* If instruction has two operands and has an AddressMode
+	     modifier then set addressing mode type for instruction.  */
+	  if (insn.tm->opcode_modifier == AddressMode)
+	    {
+	      int addr_insn = 0;
+	      /* Store instruction uses the second
+		 operand for the address mode.  */
+	      if ((insn.tm->operand_types[1] & (Indirect | Direct))
+		  == (Indirect | Direct))
+		addr_insn = 1;
+
+	      if (insn.operand_type[addr_insn]->op_type & (AllReg))
+		insn.addressing_mode = AM_Register;
+	      else if (insn.operand_type[addr_insn]->op_type & Direct)
+		insn.addressing_mode = AM_Direct;
+	      else if (insn.operand_type[addr_insn]->op_type & Indirect)
+		insn.addressing_mode = AM_Indirect;
+	      else
+		insn.addressing_mode = AM_Immediate;
+	    }
+	}
+      else
+	{
+	  as_bad ("The %s operand doesn't match", ordinal_names[count]);
+	  return;
+	}
+    }
+
+  /* Now set the addressing mode for 3 operand instructions.  */
+  if ((insn.tm->operand_types[0] & op3T1)
+      && (insn.tm->operand_types[1] & op3T2))
+    {
+      /* Set the addressing mode to the values used for 2 operand
+	 instructions in the  G addressing field of the opcode.  */
+      char *p;
+      switch (insn.operand_type[0]->op_type)
+	{
+	case Rn:
+	case ARn:
+	case DPReg:
+	case OtherReg:
+	  if (insn.operand_type[1]->op_type & (AllReg))
+	    insn.addressing_mode = AM_Register;
+	  else if (insn.operand_type[1]->op_type & Indirect)
+	    insn.addressing_mode = AM_Direct;
+	  else
+	    {
+	      /* Shouldn't make it to this stage.  */
+	      as_bad ("Incompatible first and second operands in instruction");
+	      return;
+	    }
+	  break;
+	case Indirect:
+	  if (insn.operand_type[1]->op_type & (AllReg))
+	    insn.addressing_mode = AM_Indirect;
+	  else if (insn.operand_type[1]->op_type & Indirect)
+	    insn.addressing_mode = AM_Immediate;
+	  else
+	    {
+	      /* Shouldn't make it to this stage.  */
+	      as_bad ("Incompatible first and second operands in instruction");
+	      return;
+	    }
+	  break;
+	}
+      /* Now make up the opcode for the 3 operand instructions.  As in
+	 parallel instructions, there will be no unresolved values, so they
+	 can be fully formed and added to the frag table.  */
+      insn.opcode = insn.tm->base_opcode;
+      if (insn.operand_type[0]->op_type & Indirect)
+	{
+	  insn.opcode |= (insn.operand_type[0]->indirect.ARnum);
+	  insn.opcode |= (insn.operand_type[0]->indirect.mod << 3);
+	}
+      else
+	insn.opcode |= (insn.operand_type[0]->reg.opcode);
+
+      if (insn.operand_type[1]->op_type & Indirect)
+	{
+	  insn.opcode |= (insn.operand_type[1]->indirect.ARnum << 8);
+	  insn.opcode |= (insn.operand_type[1]->indirect.mod << 11);
+	}
+      else
+	insn.opcode |= (insn.operand_type[1]->reg.opcode << 8);
+
+      if (insn.operands == 3)
+	insn.opcode |= (insn.operand_type[2]->reg.opcode << 16);
+
+      insn.opcode |= insn.addressing_mode;
+      p = frag_more (INSN_SIZE);
+      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+    }
+  else
+    {
+      /* Not a three operand instruction.  */
+      char *p;
+      int am_insn = -1;
+      insn.opcode = insn.tm->base_opcode;
+      /* Create frag for instruction - all instructions are 4 bytes long.  */
+      p = frag_more (INSN_SIZE);
+      if ((insn.operands > 0) && (insn.tm->opcode_modifier == AddressMode))
+	{
+	  insn.opcode |= insn.addressing_mode;
+	  if (insn.addressing_mode == AM_Indirect)
+	    {
+	      /* Determine which operand gives the addressing mode.  */
+	      if (insn.operand_type[0]->op_type & Indirect)
+		am_insn = 0;
+	      if ((insn.operands > 1)
+		  && (insn.operand_type[1]->op_type & Indirect))
+		am_insn = 1;
+	      insn.opcode |= (insn.operand_type[am_insn]->indirect.disp);
+	      insn.opcode |= (insn.operand_type[am_insn]->indirect.ARnum << 8);
+	      insn.opcode |= (insn.operand_type[am_insn]->indirect.mod << 11);
+	      if (insn.operands > 1)
+		insn.opcode |= (insn.operand_type[!am_insn]->reg.opcode << 16);
+	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	    }
+	  else if (insn.addressing_mode == AM_Register)
+	    {
+	      insn.opcode |= (insn.operand_type[0]->reg.opcode);
+	      if (insn.operands > 1)
+		insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
+	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	    }
+	  else if (insn.addressing_mode == AM_Direct)
+	    {
+	      if (insn.operand_type[0]->op_type & Direct)
+		am_insn = 0;
+	      if ((insn.operands > 1)
+		  && (insn.operand_type[1]->op_type & Direct))
+		am_insn = 1;
+	      if (insn.operands > 1)
+		insn.opcode |=
+		  (insn.operand_type[! am_insn]->reg.opcode << 16);
+	      if (insn.operand_type[am_insn]->direct.resolved == 1)
+		{
+		  /* Resolved values can be placed straight
+		     into instruction word, and output.  */
+		  insn.opcode |=
+		    (insn.operand_type[am_insn]->direct.address & 0x0000FFFF);
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else
+		{
+		  /* Unresolved direct addressing mode instruction.  */
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal), 2,
+			       & insn.operand_type[am_insn]->direct.direct_expr,
+			       0, 0);
+		}
+	    }
+	  else if (insn.addressing_mode == AM_Immediate)
+	    {
+	      if (insn.operand_type[0]->immediate.resolved == 1)
+		{
+		  char *keeploc;
+		  int size;
+
+		  if (insn.operands > 1)
+		    insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
+
+		  switch (insn.tm->imm_arg_type)
+		    {
+		    case Imm_Float:
+		      debug ("Floating point first operand\n");
+		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+
+		      keeploc = input_line_pointer;
+		      input_line_pointer =
+			insn.operand_type[0]->immediate.label;
+
+		      if (md_atof ('f', p + 2, & size) != 0)
+			{
+			  as_bad ("invalid short form floating point immediate operand");
+			  return;
+			}
+
+		      input_line_pointer = keeploc;
+		      break;
+
+		    case Imm_UInt:
+		      debug ("Unsigned int first operand\n");
+		      if (insn.operand_type[0]->immediate.decimal_found)
+			as_warn ("rounding down first operand float to unsigned int");
+		      if (insn.operand_type[0]->immediate.u_number > 0xFFFF)
+			as_warn ("only lower 16-bits of first operand are used");
+		      insn.opcode |=
+			(insn.operand_type[0]->immediate.u_number & 0x0000FFFFL);
+		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		      break;
+
+		    case Imm_SInt:
+		      debug ("Int first operand\n");
+
+		      if (insn.operand_type[0]->immediate.decimal_found)
+			as_warn ("rounding down first operand float to signed int");
+
+		      if (insn.operand_type[0]->immediate.s_number < -32768 ||
+			  insn.operand_type[0]->immediate.s_number > 32767)
+			{
+			  as_bad ("first operand is too large for 16-bit signed int");
+			  return;
+			}
+		      insn.opcode |=
+			(insn.operand_type[0]->immediate.s_number & 0x0000FFFFL);
+		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		      break;
+		    }
+		}
+	      else
+		{
+		  /* Unresolved immediate label.  */
+		  if (insn.operands > 1)
+		    insn.opcode |= (insn.operand_type[1]->reg.opcode << 16);
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal), 2,
+			       & insn.operand_type[0]->immediate.imm_expr,
+			       0, 0);
+		}
+	    }
+	}
+      else if (insn.tm->opcode_modifier == PCRel)
+	{
+	  /* Conditional Branch and Call instructions.  */
+	  if ((insn.tm->operand_types[0] & (AllReg | Disp))
+	      == (AllReg | Disp))
+	    {
+	      if (insn.operand_type[0]->op_type & (AllReg))
+		{
+		  insn.opcode |= (insn.operand_type[0]->reg.opcode);
+		  insn.opcode |= PC_Register;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else
+		{
+		  insn.opcode |= PC_Relative;
+		  if (insn.operand_type[0]->immediate.resolved == 1)
+		    {
+		      insn.opcode |=
+			(insn.operand_type[0]->immediate.s_number & 0x0000FFFF);
+		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		    }
+		  else
+		    {
+		      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		      fix_new_exp (frag_now, p + 2 - (frag_now->fr_literal),
+				   2, & insn.operand_type[0]->immediate.imm_expr,
+				   1, 0);
+		    }
+		}
+	    }
+	  else if ((insn.tm->operand_types[0] & ARn) == ARn)
+	    {
+	      /* Decrement and Branch instructions.  */
+	      insn.opcode |= ((insn.operand_type[0]->reg.opcode - 0x08) << 22);
+	      if (insn.operand_type[1]->op_type & (AllReg))
+		{
+		  insn.opcode |= (insn.operand_type[1]->reg.opcode);
+		  insn.opcode |= PC_Register;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else if (insn.operand_type[1]->immediate.resolved == 1)
+		{
+		  if (insn.operand_type[0]->immediate.decimal_found)
+		    {
+		      as_bad ("first operand is floating point");
+		      return;
+		    }
+		  if (insn.operand_type[0]->immediate.s_number < -32768 ||
+		      insn.operand_type[0]->immediate.s_number > 32767)
+		    {
+		      as_bad ("first operand is too large for 16-bit signed int");
+		      return;
+		    }
+		  insn.opcode |= (insn.operand_type[1]->immediate.s_number);
+		  insn.opcode |= PC_Relative;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else
+		{
+		  insn.opcode |= PC_Relative;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  fix_new_exp (frag_now, p + 2 - frag_now->fr_literal, 2,
+			       & insn.operand_type[1]->immediate.imm_expr,
+			       1, 0);
+		}
+	    }
+	}
+      else if (insn.tm->operand_types[0] == IVector)
+	{
+	  /* Trap instructions.  */
+	  if (insn.operand_type[0]->op_type & IVector)
+	    insn.opcode |= (insn.operand_type[0]->immediate.u_number);
+	  else
+	    {
+	      /* Shouldn't get here.  */
+	      as_bad ("interrupt vector for trap instruction out of range");
+	      return;
+	    }
+	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	}
+      else if (insn.tm->opcode_modifier == StackOp
+	       || insn.tm->opcode_modifier == Rotate)
+	{
+	  /* Push, Pop and Rotate instructions.  */
+	  insn.opcode |= (insn.operand_type[0]->reg.opcode << 16);
+	  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	}
+      else if ((insn.tm->operand_types[0] & (Abs24 | Direct))
+	       == (Abs24 | Direct))
+	{
+	  /* LDP Instruction needs to be tested
+	     for before the next section.  */
+	  if (insn.operand_type[0]->op_type & Direct)
+	    {
+	      if (insn.operand_type[0]->direct.resolved == 1)
+		{
+		  /* Direct addressing uses lower 8 bits of direct address.  */
+		  insn.opcode |=
+		    (insn.operand_type[0]->direct.address & 0x00FF0000) >> 16;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else
+		{
+		  fixS *fix;
+
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  fix = fix_new_exp (frag_now, p + 3 - (frag_now->fr_literal),
+				     1, &insn.operand_type[0]->direct.direct_expr, 0, 0);
+		  /* Ensure that the assembler doesn't complain
+		     about fitting a 24-bit address into 8 bits.  */
+		  fix->fx_no_overflow = 1;
+		}
+	    }
+	  else
+	    {
+	      if (insn.operand_type[0]->immediate.resolved == 1)
+		{
+		  /* Immediate addressing uses upper 8 bits of address.  */
+		  if (insn.operand_type[0]->immediate.u_number > 0x00FFFFFF)
+		    {
+		      as_bad ("LDP instruction needs a 24-bit operand");
+		      return;
+		    }
+		  insn.opcode |=
+		    ((insn.operand_type[0]->immediate.u_number & 0x00FF0000) >> 16);
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		}
+	      else
+		{
+		  fixS *fix;
+		  md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+		  fix = fix_new_exp (frag_now, p + 3 - (frag_now->fr_literal),
+				     1, &insn.operand_type[0]->immediate.imm_expr,
+				     0, 0);
+		  fix->fx_no_overflow = 1;
+		}
+	    }
+	}
+      else if (insn.tm->operand_types[0] & (Imm24))
+	{
+	  /* Unconditional Branch and Call instructions.  */
+	  if (insn.operand_type[0]->immediate.resolved == 1)
+	    {
+	      if (insn.operand_type[0]->immediate.u_number > 0x00FFFFFF)
+		as_warn ("first operand is too large for a 24-bit displacement");
+	      insn.opcode |=
+		(insn.operand_type[0]->immediate.u_number & 0x00FFFFFF);
+	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	    }
+	  else
+	    {
+	      md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+	      fix_new_exp (frag_now, p + 1 - (frag_now->fr_literal), 3,
+			   & insn.operand_type[0]->immediate.imm_expr, 0, 0);
+	    }
+	}
+      else if (insn.tm->operand_types[0] & NotReq)
+	/* Check for NOP instruction without arguments.  */
+	md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+
+      else if (insn.tm->operands == 0)
+	/* Check for instructions without operands.  */
+	md_number_to_chars (p, (valueT) insn.opcode, INSN_SIZE);
+    }
+  debug ("Addressing mode: %08X\n", insn.addressing_mode);
+  {
+    unsigned int i;
+
+    for (i = 0; i < insn.operands; i++)
+      {
+	if (insn.operand_type[i]->immediate.label)
+	  free (insn.operand_type[i]->immediate.label);
+	free (insn.operand_type[i]);
+      }
+  }
+  debug ("Final opcode: %08X\n", insn.opcode);
+  debug ("\n");
 }
+
diff --git a/gas/config/tc-tic30.h b/gas/config/tc-tic30.h
index 522892183f3d..10017071c2df 100644
--- a/gas/config/tc-tic30.h
+++ b/gas/config/tc-tic30.h
@@ -1,5 +1,5 @@
 /* tc-tic30.h -- Header file for tc-tic30.c
-   Copyright 1998, 2000 Free Software Foundation, Inc.
+   Copyright 1998, 2000, 2002, 2005 Free Software Foundation, Inc.
    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef _TC_TIC30_H_
 #define _TC_TIC30_H_
@@ -30,28 +30,22 @@
 
 #define TARGET_ARCH		bfd_arch_tic30
 #define TARGET_BYTES_BIG_ENDIAN	1
-
 #define WORKING_DOT_WORD
-
-char *output_invalid PARAMS ((int c));
-
-#define END_OF_INSN '\0'
-#define MAX_OPERANDS 6
-#define DIRECT_REFERENCE '@'
-#define INDIRECT_REFERENCE '*'
-#define PARALLEL_SEPARATOR '|'
-#define INSN_SIZE 4
+#define END_OF_INSN 		'\0'
+#define MAX_OPERANDS 		6
+#define DIRECT_REFERENCE 	'@'
+#define INDIRECT_REFERENCE 	'*'
+#define PARALLEL_SEPARATOR 	'|'
+#define INSN_SIZE 		4
 
 /* Define this to 1 if you want the debug output to be on stdout,
    otherwise stderr will be used.  If stderr is used, there will be a
    better synchronisation with the as_bad outputs, but you can't
    capture the output.  */
-#define USE_STDOUT 0
+#define USE_STDOUT 		0
 
 #define tc_unrecognized_line tic30_unrecognized_line
 
-extern int tic30_unrecognized_line PARAMS ((int));
-
-#define tc_aout_pre_write_hook {}
+extern int tic30_unrecognized_line (int);
 
 #endif
diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c
index f0308da662de..8707180c1328 100644
--- a/gas/config/tc-tic4x.c
+++ b/gas/config/tc-tic4x.c
@@ -1,5 +1,5 @@
 /* tc-tic4x.c -- Assemble for the Texas Instruments TMS320C[34]x.
-   Copyright (C) 1997,1998, 2002, 2003 Free Software Foundation.
+   Copyright (C) 1997,1998, 2002, 2003, 2005 Free Software Foundation.
 
    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
 
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, 
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, 
+   Boston, MA 02110-1301, USA.  */
 /*
   TODOs:
   ------
@@ -157,7 +157,7 @@ static void tic4x_insert_sym
 static char *tic4x_expression
   PARAMS ((char *, expressionS *));
 static char *tic4x_expression_abs
-  PARAMS ((char *, int *));
+  PARAMS ((char *, offsetT *));
 static void tic4x_emit_char
   PARAMS ((char, int));
 static void tic4x_seg_alloc
@@ -257,7 +257,6 @@ const pseudo_typeS
 
 int md_short_jump_size = 4;
 int md_long_jump_size = 4;
-const int md_reloc_size = RELSZ;	/* Coff headers.  */
 
 /* This array holds the chars that always start a comment.  If the
    pre-processor is disabled, these aren't very useful.  */
@@ -323,7 +322,7 @@ tic4x_gen_to_words (flonum, words, precision)
   unsigned int rbit;            /* Round bit. */
   int shift;			/* Shift count.  */
 
-  /* NOTE: Svein Seldal <Svein.Seldal@solidas.com>
+  /* NOTE: Svein Seldal <Svein@dev.seldal.com>
      The code in this function is altered slightly to support floats
      with 31-bits mantissas, thus the documentation below may be a
      little bit inaccurate.
@@ -708,7 +707,7 @@ tic4x_insert_reg (regname, regnum)
   symbol_table_insert (symbol_new (regname, reg_section, (valueT) regnum,
 				   &zero_address_frag));
   for (i = 0; regname[i]; i++)
-    buf[i] = islower (regname[i]) ? TOUPPER (regname[i]) : regname[i];
+    buf[i] = ISLOWER (regname[i]) ? TOUPPER (regname[i]) : regname[i];
   buf[i] = '\0';
 
   symbol_table_insert (symbol_new (buf, reg_section, (valueT) regnum,
@@ -747,7 +746,7 @@ tic4x_expression (str, exp)
 static char *
 tic4x_expression_abs (str, value)
      char *str;
-     int *value;
+     offsetT *value;
 {
   char *s;
   char *t;
@@ -843,7 +842,7 @@ tic4x_bss (x)
   char c;
   char *name;
   char *p;
-  int size;
+  offsetT size;
   segT current_seg;
   subsegT current_subseg;
   symbolS *symbolP;
@@ -864,7 +863,7 @@ tic4x_bss (x)
     tic4x_expression_abs (++input_line_pointer, &size);
   if (size < 0)
     {
-      as_bad (".bss size %d < 0!", size);
+      as_bad (".bss size %ld < 0!", (long) size);
       return;
     }
   subseg_set (bss_section, 0);
@@ -1024,7 +1023,7 @@ tic4x_eval (x)
      int x ATTRIBUTE_UNUSED;
 {
   char c;
-  int value;
+  offsetT value;
   char *name;
 
   SKIP_WHITESPACE ();
@@ -1060,7 +1059,7 @@ tic4x_sect (x)
   char *subsection_name;
   char *name;
   segT seg;
-  int num;
+  offsetT num;
 
   SKIP_WHITESPACE ();
   if (*input_line_pointer == '"')
@@ -1145,6 +1144,7 @@ tic4x_set (x)
 	  ignore_rest_of_line ();
 	  return;
 	}
+      ++input_line_pointer;
       symbolP = symbol_find_or_make (name);
     }
   else
@@ -1163,7 +1163,7 @@ tic4x_usect (x)
   char *name;
   char *section_name;
   segT seg;
-  int size, alignment_flag;
+  offsetT size, alignment_flag;
   segT current_seg;
   subsegT current_subseg;
 
@@ -1226,15 +1226,15 @@ static void
 tic4x_version (x)
      int x ATTRIBUTE_UNUSED;
 {
-  unsigned int temp;
+  offsetT temp;
 
   input_line_pointer =
     tic4x_expression_abs (input_line_pointer, &temp);
   if (!IS_CPU_TIC3X (temp) && !IS_CPU_TIC4X (temp))
-    as_bad ("This assembler does not support processor generation %d",
-	    temp);
+    as_bad ("This assembler does not support processor generation %ld",
+	    (long) temp);
 
-  if (tic4x_cpu && temp != tic4x_cpu)
+  if (tic4x_cpu && temp != (offsetT) tic4x_cpu)
     as_warn ("Changing processor generation on fly not supported...");
   tic4x_cpu = temp;
   demand_empty_rest_of_line ();
@@ -2675,7 +2675,7 @@ md_atof (type, litP, sizeP)
   int ieee;
   LITTLENUM_TYPE words[MAX_LITTLENUMS];
   LITTLENUM_TYPE *wordP;
-  unsigned char *t;
+  char *t;
 
   switch (type)
     {
@@ -2718,7 +2718,7 @@ md_atof (type, litP, sizeP)
   if (t)
     input_line_pointer = t;
   *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  t = litP;
+
   /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
      little endian byte order.  */
   /* SES: However it is required to put the words (32-bits) out in the
@@ -2742,7 +2742,7 @@ md_atof (type, litP, sizeP)
 }
 
 void 
-md_apply_fix3 (fixP, value, seg)
+md_apply_fix (fixP, value, seg)
      fixS *fixP;
      valueT *value;
      segT seg ATTRIBUTE_UNUSED;
@@ -3072,9 +3072,10 @@ long
 md_pcrel_from (fixP)
      fixS *fixP;
 {
-  unsigned char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+  unsigned char *buf;
   unsigned int op;
 
+  buf = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
   op = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
 
   return ((fixP->fx_where + fixP->fx_frag->fr_address) >> 2) +
@@ -3090,7 +3091,7 @@ tic4x_do_align (alignment, fill, len, max)
      int len ATTRIBUTE_UNUSED;
      int max ATTRIBUTE_UNUSED;
 {
-  unsigned long nop = NOP_OPCODE;
+  unsigned long nop = TIC_NOP_OPCODE;
 
   /* Because we are talking lwords, not bytes, adjust alignment to do words */
   alignment += 2;
diff --git a/gas/config/tc-tic4x.h b/gas/config/tc-tic4x.h
index 0d6c72c42584..fdc6eea628df 100644
--- a/gas/config/tc-tic4x.h
+++ b/gas/config/tc-tic4x.h
@@ -1,5 +1,5 @@
 /* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X.
-   Copyright (C) 1997, 2002, 2003 Free Software Foundation.
+   Copyright (C) 1997, 2002, 2003, 2005 Free Software Foundation.
    
    Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
 
@@ -17,15 +17,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #define TC_TIC4X
 #define TIC4X
 
-#ifndef BFD_ASSEMBLER
-#error TMS320C4x requires BFD_ASSEMBLER
-#endif
-
 #define TARGET_ARCH bfd_arch_tic4x
 
 #define WORKING_DOT_WORD
@@ -57,15 +53,8 @@
 #define OCTETS_PER_BYTE_POWER 	2
 
 #define TARGET_ARCH		bfd_arch_tic4x
-#define BFD_ARCH                TARGET_ARCH
-
-#define TC_COUNT_RELOC(x) 	(x->fx_addsy)
-#define TC_CONS_RELOC 		RELOC_32
-#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype (fixP)
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
-#define NEED_FX_R_TYPE
 
-#define NOP_OPCODE              0x0c800000
+#define TIC_NOP_OPCODE		0x0c800000
 
 #define reloc_type 		int
 
diff --git a/gas/config/tc-tic54x.c b/gas/config/tc-tic54x.c
index 87dd6daf11b2..f84afcd838e7 100644
--- a/gas/config/tc-tic54x.c
+++ b/gas/config/tc-tic54x.c
@@ -1,5 +1,6 @@
 /* tc-tic54x.c -- Assembly code for the Texas Instruments TMS320C54X
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
    Contributed by Timothy Wall (twall@cygnus.com)
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Texas Instruments TMS320C54X machine specific gas.
    Written by Timothy Wall (twall@alum.mit.edu).
@@ -153,9 +154,6 @@ struct option md_longopts[] =
   { "mfar-mode",       no_argument,	    NULL, OPTION_ADDRESS_MODE },
   { "mf",	       no_argument,	    NULL, OPTION_ADDRESS_MODE },
   { "mcpu",	       required_argument,   NULL, OPTION_CPU_VERSION },
-#if 0
-  { "mcoff-version",   required_argument,   NULL, OPTION_COFF_VERSION },
-#endif
   { "merrors-to-file", required_argument,   NULL, OPTION_STDERR_TO_FILE },
   { "me",	       required_argument,   NULL, OPTION_STDERR_TO_FILE },
   { NULL,              no_argument,         NULL, 0},
@@ -349,9 +347,6 @@ md_show_usage (stream)
   fprintf (stream, _("C54x-specific command line  options:\n"));
   fprintf (stream, _("-mfar-mode | -mf          Use extended addressing\n"));
   fprintf (stream, _("-mcpu=<CPU version>       Specify the CPU version\n"));
-#if 0
-  fprintf (stream, _("-mcoff-version={0|1|2}    Select COFF version\n"));
-#endif
   fprintf (stream, _("-merrors-to-file <filename>\n"));
   fprintf (stream, _("-me <filename>            Redirect errors to a file\n"));
 }
@@ -667,7 +662,7 @@ tic54x_bss (x)
     }
 
   if (block)
-    bss_section->flags |= SEC_BLOCK;
+    bss_section->flags |= SEC_TIC54X_BLOCK;
 
   subseg_set (current_seg, current_subseg);	/* Restore current seg.  */
   demand_empty_rest_of_line ();
@@ -1580,7 +1575,7 @@ tic54x_usect (x)
   *p = 0;
 
   if (blocking_flag)
-    flags |= SEC_BLOCK;
+    flags |= SEC_TIC54X_BLOCK;
 
   if (!bfd_set_section_flags (stdoutput, seg, flags))
     as_warn ("Error setting flags for \"%s\": %s", name,
@@ -2020,7 +2015,7 @@ tic54x_clink (ignored)
 	}
     }
 
-  seg->flags |= SEC_CLINK;
+  seg->flags |= SEC_TIC54X_CLINK;
 
   demand_empty_rest_of_line ();
 }
@@ -2331,7 +2326,7 @@ tic54x_sblock (ignore)
 	  ignore_rest_of_line ();
 	  return;
 	}
-      seg->flags |= SEC_BLOCK;
+      seg->flags |= SEC_TIC54X_BLOCK;
 
       c = *input_line_pointer;
       if (!is_end_of_line[(int) c])
@@ -2583,9 +2578,6 @@ const pseudo_typeS md_pseudo_table[] =
   { "emsg"     , tic54x_message           ,        'e' },
   { "mmsg"     , tic54x_message           ,        'm' },
   { "wmsg"     , tic54x_message           ,        'w' },
-#if 0
-  { "end"      , s_end                    ,          0 },
-#endif
   { "far_mode" , tic54x_address_mode      ,   far_mode },
   { "fclist"   , tic54x_fclist            ,          1 },
   { "fcnolist" , tic54x_fclist            ,          0 },
@@ -2611,10 +2603,6 @@ const pseudo_typeS md_pseudo_table[] =
                                                              address.  */
   { "length"   , s_ignore                 ,          0 },
   { "width"    , s_ignore                 ,          0 },
-#if 0
-  { "list"     , listing_list             ,          1 },
-  { "nolist"   , listing_list             ,          0 },
-#endif
   { "long"     , tic54x_cons              ,        'l' },
   { "ulong"    , tic54x_cons              ,        'L' },
   { "xlong"    , tic54x_cons              ,        'x' },
@@ -2628,9 +2616,6 @@ const pseudo_typeS md_pseudo_table[] =
   { "newblock" , tic54x_clear_local_labels,          0 },
   { "option"   , s_ignore                 ,          0 },
   { "p2align"  , tic54x_p2align           ,          0 },
-#if 0
-  { "page"     , listing_eject            ,          0 },
-#endif
   { "sblock"   , tic54x_sblock            ,          0 },
   { "sect"     , tic54x_sect              ,        '*' },
   { "set"      , tic54x_set               ,          0 },
@@ -2646,9 +2631,6 @@ const pseudo_typeS md_pseudo_table[] =
   { "endstruct", tic54x_endstruct         ,          0 },
   { "tab"      , s_ignore                 ,          0 },
   { "text"     , tic54x_sect              ,        't' },
-#if 0
-  { "title"    , listing_title            ,          0 },
-#endif
   { "union"    , tic54x_struct            ,          1 },
   { "endunion" , tic54x_endstruct         ,          1 },
   { "usect"    , tic54x_usect             ,          0 },
@@ -2657,21 +2639,6 @@ const pseudo_typeS md_pseudo_table[] =
   {0           , 0                        ,          0 }
 };
 
-#if 0
-/* For debugging, strings for each operand type.  */
-static const char *optypes[] =
-{
-  "none", "Xmem", "Ymem", "pmad", "dmad", "Smem", "Lmem", "MMR", "PA",
-  "Sind", "xpmad", "xpmad+", "MMRX", "MMRY",
-  "SRC1", "SRC", "RND", "DST",
-  "ARX",
-  "SHIFT", "SHFT",
-  "B", "A", "lk", "TS", "k8", "16", "BITC", "CC", "CC2", "CC3", "123", "031",
-  "k5", "k8u", "ASM", "T", "DP", "ARP", "k3", "lku", "N", "SBIT", "12",
-  "k9", "TRN",
-};
-#endif
-
 int
 md_parse_option (c, arg)
      int c;
@@ -2733,29 +2700,10 @@ tic54x_macro_start ()
 }
 
 void
-tic54x_macro_info (info)
-     void *info;
+tic54x_macro_info (macro)
+     const macro_entry *macro;
 {
-  struct formal_struct
-  {
-    struct formal_struct *next;	/* Next formal in list  */
-    sb name;			/* Name of the formal  */
-    sb def;			/* The default value  */
-    sb actual;			/* The actual argument (changed on
-                                   each expansion) */
-    int index;			/* The index of the formal
-                                   0 .. formal_count - 1 */
-  } *entry;
-  struct macro_struct
-  {
-    sb sub;			/* Substitution text.  */
-    int formal_count;		/* Number of formal args.  */
-    struct formal_struct *formals;	/* Pointer to list of
-                                           formal_structs.  */
-    struct hash_control *formal_hash; /* Hash table of formals.  */
-  } *macro;
-
-  macro = (struct macro_struct *) info;
+  const formal_entry *entry;
 
   /* Put the formal args into the substitution symbol table.  */
   for (entry = macro->formals; entry; entry = entry->next)
@@ -5037,7 +4985,7 @@ subsym_substitute (line, forced)
 		      if (beg < 1)
 			{
 			  as_bad (_("Invalid subscript (use 1 to %d)"),
-				  strlen (value));
+				  (int) strlen (value));
 			  break;
 			}
 		      if (*input_line_pointer == ',')
@@ -5047,7 +4995,7 @@ subsym_substitute (line, forced)
 			  if (beg + len > strlen (value))
 			    {
 			      as_bad (_("Invalid length (use 0 to %d"),
-				      strlen (value) - beg);
+				      (int) strlen (value) - beg);
 			      break;
 			    }
 			}
@@ -5080,24 +5028,6 @@ subsym_substitute (line, forced)
 		      break;
 		    }
 		  ++tail;
-#if 0
-		  /* Try to replace required whitespace
-		     eliminated by the preprocessor; technically, a forced
-		     substitution could come anywhere, even mid-symbol,
-		     e.g. if x is "0", 'sym:x:end' should result in 'sym0end',
-		     but 'sym:x: end' should result in 'sym0 end'.
-		     FIXME -- this should really be fixed in the preprocessor,
-		     but would require several new states;
-		     KEEP_WHITE_AROUND_COLON does part of the job, but isn't
-		     complete.  */
-		  if ((is_part_of_name (tail[1])
-		       && tail[1] != '.'
-		       && tail[1] != '$')
-		      || tail[1] == '\0' || tail[1] == ',' || tail[1] == '"')
-		    ++tail;
-		  else
-		    *tail = ' ';
-#endif
 		}
 	      else
 		/* Restore the character after the symbol end.  */
@@ -5379,7 +5309,7 @@ tic54x_adjust_symtab ()
       char *filename;
       unsigned lineno;
       as_where (&filename, &lineno);
-      c_dot_file_symbol (filename);
+      c_dot_file_symbol (filename, 0);
     }
 }
 
@@ -5402,11 +5332,6 @@ void
 tic54x_define_label (sym)
      symbolS *sym;
 {
-#if 0
-  static int local_label_count = 0;
-  const char *name = S_GET_NAME (sym);
-#endif
-
   /* Just in case we need this later; note that this is not necessarily the
      same thing as line_label...
      When aligning or assigning labels to fields, sometimes the label is
@@ -5456,17 +5381,6 @@ tic54x_parse_name (name, exp)
      char *name ATTRIBUTE_UNUSED;
      expressionS *exp ATTRIBUTE_UNUSED;
 {
-#if 0
-  symbol *sym = (symbol *) hash_find (mmreg_hash, name);
-
-  /* If it's a MMREG, replace it with its constant value.  */
-  if (sym)
-    {
-      exp->X_op = O_constant;
-      exp->X_add_number = sym->value;
-      return 1;
-    }
-#endif
   return 0;
 }
 
@@ -5567,7 +5481,7 @@ tic54x_cons_fix_new (frag, where, octets, exp)
    If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry.   */
 
 void
-md_apply_fix3 (fixP, valP, seg)
+md_apply_fix (fixP, valP, seg)
      fixS *fixP;
      valueT * valP;
      segT seg ATTRIBUTE_UNUSED;
@@ -5635,17 +5549,6 @@ md_pcrel_from (fixP)
   return 0;
 }
 
-#if defined OBJ_COFF
-
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-  return (fixP->fx_r_type);
-}
-
-#endif /* OBJ_COFF */
-
 /* Mostly little-endian, but longwords (4 octets) get MS word stored
    first.  */
 
diff --git a/gas/config/tc-tic54x.h b/gas/config/tc-tic54x.h
index 07b1f67e98c0..7476500e79be 100644
--- a/gas/config/tc-tic54x.h
+++ b/gas/config/tc-tic54x.h
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef _TC_TIC54X_H_
 #define _TC_TIC54X_H_
@@ -29,7 +29,6 @@
 #define OCTETS_PER_BYTE_POWER 1
 
 #define TARGET_ARCH		bfd_arch_tic54x
-#define BFD_ARCH                TARGET_ARCH
 
 #define WORKING_DOT_WORD        1
 
@@ -48,10 +47,6 @@
 /* affects preprocessor */
 #define KEEP_WHITE_AROUND_COLON 1
 
-/* We need the extra field in the fixup struct to put the relocation in.  */
-
-#define NEED_FX_R_TYPE
-
 struct bit_info
 {
   segT seg;
@@ -88,7 +83,7 @@ extern void tic54x_number_to_chars (char *, valueT, int);
 extern void tic54x_adjust_symtab (void);
 #define tc_unrecognized_line(ch) tic54x_unrecognized_line(ch)
 extern int tic54x_unrecognized_line (int ch);
-#define md_parse_name(s,e,c) tic54x_parse_name(s,e)
+#define md_parse_name(s,e,m,c) tic54x_parse_name(s,e)
 extern int tic54x_parse_name (char *name, expressionS *e);
 #define md_undefined_symbol(s) tic54x_undefined_symbol(s)
 extern symbolS *tic54x_undefined_symbol (char *name);
@@ -97,7 +92,8 @@ extern void tic54x_macro_start (void);
 #define md_macro_end() tic54x_macro_end()
 extern void tic54x_macro_end (void);
 #define md_macro_info(args) tic54x_macro_info(args)
-extern void tic54x_macro_info PARAMS((void *macro));
+struct macro_struct;
+extern void tic54x_macro_info PARAMS((const struct macro_struct *));
 #define tc_frob_label(sym) tic54x_define_label (sym)
 extern void tic54x_define_label PARAMS((symbolS *));
 
diff --git a/gas/config/tc-tic80.c b/gas/config/tc-tic80.c
deleted file mode 100644
index 0ec638228b58..000000000000
--- a/gas/config/tc-tic80.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-/* tc-tic80.c -- Assemble for the TI TMS320C80 (MV)
-   Copyright 1996, 1997, 2000, 2001, 2002 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#include "as.h"
-#include "safe-ctype.h"
-#include "opcode/tic80.h"
-
-#define internal_error(what) \
-  as_fatal (_("internal error:%s:%d: %s\n"), __FILE__, __LINE__, what)
-
-#define internal_error_a(what,arg) \
-  as_fatal (_("internal error:%s:%d: %s %ld\n"), __FILE__, __LINE__, what, arg)
-
-/* Generic assembler global variables which must be defined by all
-   targets.  */
-
-/* Characters which always start a comment.  */
-const char comment_chars[] = ";";
-
-/* Characters which start a comment at the beginning of a line.  */
-const char line_comment_chars[] = ";*#";
-
-/* Characters which may be used to separate multiple commands on a single
-   line. The semicolon is such a character by default and should not be
-   explicitly listed.  */
-const char line_separator_chars[] = "";
-
-/* Characters which are used to indicate an exponent in a floating
-   point number.  */
-const char EXP_CHARS[] = "eE";
-
-/* Characters which mean that a number is a floating point constant,
-   as in 0f1.0.  */
-const char FLT_CHARS[] = "fF";
-
-/* This table describes all the machine specific pseudo-ops the assembler
-   has to support.  The fields are:
-
-   pseudo-op name without dot
-   function to call to execute this pseudo-op
-   integer arg to pass to the function  */
-
-const pseudo_typeS md_pseudo_table[] = {
-  { "align",	s_align_bytes,		4 },	/* Do byte alignment, default is a 4 byte boundary  */
-  { "word",	cons,			4 },	/* FIXME: Should this be machine independent?  */
-  { "bss",	s_lcomm_bytes,		1 },
-  { "sect",	obj_coff_section,	0},	/* For compatibility with TI tools  */
-  { "section",	obj_coff_section,	0},	/* Standard COFF .section pseudo-op  */
-  { NULL,	NULL,			0 }
-};
-
-/* Opcode hash table.  */
-static struct hash_control *tic80_hash;
-
-static struct tic80_opcode * find_opcode PARAMS ((struct tic80_opcode *, expressionS []));
-static void build_insn PARAMS ((struct tic80_opcode *, expressionS *));
-static int get_operands PARAMS ((expressionS exp[]));
-static int const_overflow PARAMS ((unsigned long num, int bits, int flags));
-
-/* Replace short PC relative instructions with long form when
-   necessary.  Currently this is off by default or when given the
-   -no-relax option.  Turning it on by using the -relax option forces
-   all PC relative instructions to use the long form, which is why it
-   is currently not the default.  */
-static int tic80_relax = 0;
-
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     fragS *fragP ATTRIBUTE_UNUSED;
-     segT segment_type ATTRIBUTE_UNUSED;
-{
-  internal_error (_("Relaxation is a luxury we can't afford"));
-  return (-1);
-}
-
-/* We have no need to default values of symbols.  */
-
-symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-/* Turn a string in input_line_pointer into a floating point constant
-   of type TYPE, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.  */
-
-#define MAX_LITTLENUMS 4
-
-char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("bad call to md_atof ()");
-    }
-
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    {
-      input_line_pointer = t;
-    }
-
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-
-  for (wordP = words; prec--;)
-    {
-      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return (NULL);
-}
-
-/* Check to see if the constant value in NUM will fit in a field of
-   width BITS if it has flags FLAGS.  */
-
-static int
-const_overflow (num, bits, flags)
-     unsigned long num;
-     int bits;
-     int flags;
-{
-  long min, max;
-  int retval = 0;
-
-  /* Only need to check fields less than 32 bits wide.  */
-  if (bits >= 32)
-    return retval;
-
-  if (flags & TIC80_OPERAND_SIGNED)
-    {
-      max = (1 << (bits - 1)) - 1;
-      min = - (1 << (bits - 1));
-      retval = (long) num > max || (long) num < min;
-    }
-  else
-    {
-      max = (1 << bits) - 1;
-      retval = num > (unsigned long) max;
-    }
-  return retval;
-}
-
-/* get_operands () parses a string of operands and fills in a passed
-   array of expressions in EXP.
-
-   Note that we use O_absent expressions to record additional information
-   about the previous non-O_absent expression, such as ":m" or ":s"
-   modifiers or register numbers enclosed in parens like "(r10)".
-
-   Returns the number of expressions that were placed in EXP.  */
-
-static int
-get_operands (exp)
-     expressionS exp[];
-{
-  char *p = input_line_pointer;
-  int numexp = 0;
-  int parens = 0;
-
-  while (*p)
-    {
-      /* Skip leading whitespace.  */
-      while (*p == ' ' || *p == '\t' || *p == ',')
-	p++;
-
-      /* Check to see if we have any operands left to parse.  */
-      if (*p == 0 || *p == '\n' || *p == '\r')
-	break;
-
-      /* Notice scaling or direct memory operand modifiers and save them in
-	 an O_absent expression after the expression that they modify.  */
-
-      if (*p == ':')
-	{
-	  p++;
-	  exp[numexp].X_op = O_absent;
-	  if (*p == 'm')
-	    {
-	      p++;
-	      /* This is a ":m" modifier.  */
-	      exp[numexp].X_add_number = TIC80_OPERAND_M_SI | TIC80_OPERAND_M_LI;
-	    }
-	  else if (*p == 's')
-	    {
-	      p++;
-	      /* This is a ":s" modifier.  */
-	      exp[numexp].X_add_number = TIC80_OPERAND_SCALED;
-	    }
-	  else
-	    {
-	      as_bad (_("':' not followed by 'm' or 's'"));
-	    }
-	  numexp++;
-	  continue;
-	}
-
-      /* Handle leading '(' on operands that use them, by recording that we
-	 have entered a paren nesting level and then continuing.  We complain
-	 about multiple nesting.  */
-
-      if (*p == '(')
-	{
-	  if (++parens != 1)
-	    as_bad (_("paren nesting"));
-
-	  p++;
-	  continue;
-	}
-
-      /* Handle trailing ')' on operands that use them, by reducing the
-	 nesting level and then continuing.  We complain if there were too
-	 many closures.  */
-
-      if (*p == ')')
-	{
-	  /* Record that we have left a paren group and continue.  */
-	  if (--parens < 0)
-	    as_bad (_("mismatched parenthesis"));
-
-	  p++;
-	  continue;
-	}
-
-      /* Begin operand parsing at the current scan point.  */
-
-      input_line_pointer = p;
-      expression (&exp[numexp]);
-
-      if (exp[numexp].X_op == O_illegal)
-	{
-	  as_bad (_("illegal operand"));
-	}
-      else if (exp[numexp].X_op == O_absent)
-	{
-	  as_bad (_("missing operand"));
-	}
-
-      numexp++;
-      p = input_line_pointer;
-    }
-
-  if (parens)
-    {
-      exp[numexp].X_op = O_absent;
-      exp[numexp++].X_add_number = TIC80_OPERAND_PARENS;
-    }
-
-  /* Mark the end of the valid operands with an illegal expression.  */
-  exp[numexp].X_op = O_illegal;
-
-  return (numexp);
-}
-
-/* find_opcode() gets a pointer to the entry in the opcode table that
-   matches the instruction being assembled, or returns NULL if no such match
-   is found.
-
-   First it parses all the operands and save them as expressions.  Note that
-   we use O_absent expressions to record additional information about the
-   previous non-O_absent expression, such as ":m" or ":s" modifiers or
-   register numbers enclosed in parens like "(r10)".
-
-   It then looks at all opcodes with the same name and uses the operands to
-   choose the correct opcode.  */
-
-static struct tic80_opcode *
-find_opcode (opcode, myops)
-     struct tic80_opcode *opcode;
-     expressionS myops[];
-{
-  int numexp;				/* Number of expressions from parsing operands */
-  int expi;				/* Index of current expression to match */
-  int opi;				/* Index of current operand to match */
-  int match = 0;			/* Set to 1 when an operand match is found */
-  struct tic80_opcode *opc = opcode;	/* Pointer to current opcode table entry */
-  const struct tic80_opcode *end;	/* Pointer to end of opcode table */
-
-  /* First parse all the operands so we only have to do it once.  There may
-     be more expressions generated than there are operands.  */
-
-  numexp = get_operands (myops);
-
-  /* For each opcode with the same name, try to match it against the parsed
-     operands.  */
-
-  end = tic80_opcodes + tic80_num_opcodes;
-  while (!match && (opc < end) && (strcmp (opc->name, opcode->name) == 0))
-    {
-      /* Start off assuming a match.  If we find a mismatch, then this is
-	 reset and the operand/expr matching loop terminates with match
-	 equal to zero, which allows us to try the next opcode.  */
-
-      match = 1;
-
-      /* For each expression, try to match it against the current operand
-	 for the current opcode.  Upon any mismatch, we abandon further
-	 matching for the current opcode table entry.  */
-
-      for (expi = 0, opi = -1; (expi < numexp) && match; expi++)
-	{
-	  int bits, flags, X_op, num;
-
-	  X_op = myops[expi].X_op;
-	  num = myops[expi].X_add_number;
-
-	  /* The O_absent expressions apply to the same operand as the most
-	     recent non O_absent expression.  So only increment the operand
-	     index when the current expression is not one of these special
-	     expressions.  */
-
-	  if (X_op != O_absent)
-	    {
-	      opi++;
-	    }
-
-	  flags = tic80_operands[opc->operands[opi]].flags;
-	  bits  = tic80_operands[opc->operands[opi]].bits;
-
-	  switch (X_op)
-	    {
-	    case O_register:
-	      /* Also check that registers that are supposed to be
-		 even actually are even.  */
-	      if (((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) ||
-		  ((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) ||
-		  ((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR)) ||
-		  ((flags & TIC80_OPERAND_EVEN) && (num & 1)) ||
-		  const_overflow (num & ~TIC80_OPERAND_MASK, bits, flags))
-		{
-		  match = 0;
-		}
-	      break;
-	    case O_constant:
-	      if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32))
-		{
-		  /* Endmask values of 0 and 32 give identical
-                     results.  */
-		  num = 0;
-		}
-	      if ((flags & (TIC80_OPERAND_FPA | TIC80_OPERAND_GPR)) ||
-		  const_overflow (num, bits, flags))
-		{
-		  match = 0;
-		}
-	      break;
-	    case O_symbol:
-	      if ((bits < 32) && (flags & TIC80_OPERAND_PCREL)
-		  && !tic80_relax)
-		{
-		  /* The default is to prefer the short form of PC
-		     relative relocations.  This is the only form that
-		     the TI assembler supports.  If the -relax option
-		     is given, we never use the short forms.
-		     FIXME: Should be able to choose "best-fit".  */
-		}
-	      else if ((bits == 32)
-#if 0
-		       && (flags & TIC80_OPERAND_BASEREL)
-#endif
-		       )
-		{
-		  /* The default is to prefer the long form of base
-		     relative relocations.  This is the only form that
-		     the TI assembler supports.  If the -no-relax
-		     option is given, we always use the long form of
-		     PC relative relocations.
-		     FIXME: Should be able to choose "best-fit".  */
-		}
-	      else
-		{
-		  /* Symbols that don't match one of the above cases are
-		     rejected as an operand.  */
-		  match = 0;
-		}
-	      break;
-	    case O_absent:
-	      /* If this is an O_absent expression, then it may be an
-		 expression that supplies additional information about
-		 the operand, such as ":m" or ":s" modifiers. Check to
-		 see that the operand matches this requirement.  */
-	      if (!((num & flags & TIC80_OPERAND_M_SI)
-		    || (num & flags & TIC80_OPERAND_M_LI)
-		    || (num & flags & TIC80_OPERAND_SCALED)))
-		{
-		  match = 0;
-		}
-	      break;
-	    case O_big:
-	      if ((num > 0) || !(flags & TIC80_OPERAND_FLOAT))
-		{
-		  match = 0;
-		}
-	      break;
-	    case O_illegal:
-	    case O_symbol_rva:
-	    case O_uminus:
-	    case O_bit_not:
-	    case O_logical_not:
-	    case O_multiply:
-	    case O_divide:
-	    case O_modulus:
-	    case O_left_shift:
-	    case O_right_shift:
-	    case O_bit_inclusive_or:
-	    case O_bit_or_not:
-	    case O_bit_exclusive_or:
-	    case O_bit_and:
-	    case O_add:
-	    case O_subtract:
-	    case O_eq:
-	    case O_ne:
-	    case O_lt:
-	    case O_le:
-	    case O_ge:
-	    case O_gt:
-	    case O_logical_and:
-	    case O_logical_or:
-	    case O_max:
-	    default:
-	      internal_error_a (_("unhandled expression type"), (long) X_op);
-	    }
-	}
-      if (!match)
-	opc++;
-    }
-
-  return (match ? opc : NULL);
-
-#if 0
-  /* Now search the opcode table table for one with operands that
-     matches what we've got.  */
-
-  while (!match)
-    {
-      match = 1;
-      for (i = 0; opcode->operands[i]; i++)
-	{
-	  int flags = tic80_operands[opcode->operands[i]].flags;
-	  int X_op = myops[i].X_op;
-	  int num = myops[i].X_add_number;
-
-	  if (X_op == 0)
-	    {
-	      match = 0;
-	      break;
-	    }
-
-	  if (flags
-	      & (TIC80_OPERAND_GPR | TIC80_OPERAND_FPA | TIC80_OPERAND_CR))
-	    {
-	      if ((X_op != O_register) ||
-		  ((flags & TIC80_OPERAND_GPR) != (num & TIC80_OPERAND_GPR)) ||
-		  ((flags & TIC80_OPERAND_FPA) != (num & TIC80_OPERAND_FPA)) ||
-		  ((flags & TIC80_OPERAND_CR) != (num & TIC80_OPERAND_CR)))
-		{
-		  match = 0;
-		  break;
-		}
-	    }
-
-	  if (((flags & TIC80_OPERAND_MINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_MINUS))) ||
-	      ((flags & TIC80_OPERAND_PLUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_PLUS))) ||
-	      ((flags & TIC80_OPERAND_ATMINUS) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATMINUS))) ||
-	      ((flags & TIC80_OPERAND_ATPAR) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATPAR))) ||
-	      ((flags & TIC80_OPERAND_ATSIGN) && ((X_op != O_absent) || (num != TIC80_OPERAND_ATSIGN))))
-	    {
-	      match = 0;
-	      break;
-	    }
-	}
-      /* We're only done if the operands matched so far AND there
-	 are no more to check.  */
-      if (match && myops[i].X_op == 0)
-	break;
-      else
-	match = 0;
-
-      next_opcode = opcode + 1;
-      if (next_opcode->opcode == 0)
-	break;
-      if (strcmp (next_opcode->name, opcode->name))
-	break;
-      opcode = next_opcode;
-    }
-
-  if (!match)
-    {
-      as_bad (_("bad opcode or operands"));
-      return (0);
-    }
-
-  /* Check that all registers that are required to be even are.
-     Also, if any operands were marked as registers, but were really
-     symbols, fix that here.  */
-  for (i = 0; opcode->operands[i]; i++)
-    {
-      if ((tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_EVEN)
-	  && (myops[i].X_add_number & 1))
-	as_fatal (_("Register number must be EVEN"));
-      if (myops[i].X_op == O_register)
-	{
-	  if (!(tic80_operands[opcode->operands[i]].flags & TIC80_OPERAND_REG))
-	    {
-	      myops[i].X_op = O_symbol;
-	      myops[i].X_add_symbol =
-		symbol_find_or_make ((char *) myops[i].X_op_symbol);
-	      myops[i].X_add_number = 0;
-	      myops[i].X_op_symbol = NULL;
-	    }
-	}
-    }
-#endif
-}
-
-/* build_insn takes a pointer to the opcode entry in the opcode table
-   and the array of operand expressions and writes out the instruction.
-
-   Note that the opcode word and extended word may be written to different
-   frags, with the opcode at the end of one frag and the extension at the
-   beginning of the next.  */
-
-static void
-build_insn (opcode, opers)
-     struct tic80_opcode *opcode;
-     expressionS *opers;
-{
-  int expi;				/* Index of current expression to match */
-  int opi;				/* Index of current operand to match */
-  unsigned long insn[2];		/* Instruction and long immediate (if any) */
-  char *f;				/* Pointer to frag location for insn[0] */
-  fragS *ffrag;				/* Frag containing location f */
-  char *fx = NULL;			/* Pointer to frag location for insn[1] */
-  fragS *fxfrag;			/* Frag containing location fx */
-
-  /* Start with the raw opcode bits from the opcode table.  */
-  insn[0] = opcode->opcode;
-
-  /* We are going to insert at least one 32 bit opcode so get the
-     frag now.  */
-
-  f = frag_more (4);
-  ffrag = frag_now;
-
-  /* For each operand expression, insert the appropriate bits into the
-     instruction.  */
-  for (expi = 0, opi = -1; opers[expi].X_op != O_illegal; expi++)
-    {
-      int bits, shift, flags, X_op, num;
-
-      X_op = opers[expi].X_op;
-      num = opers[expi].X_add_number;
-
-      /* The O_absent expressions apply to the same operand as the most
-	 recent non O_absent expression.  So only increment the operand
-	 index when the current expression is not one of these special
-	 expressions.  */
-
-      if (X_op != O_absent)
-	{
-	  opi++;
-	}
-
-      flags = tic80_operands[opcode->operands[opi]].flags;
-      bits  = tic80_operands[opcode->operands[opi]].bits;
-      shift = tic80_operands[opcode->operands[opi]].shift;
-
-      switch (X_op)
-	{
-	case O_register:
-	  num &= ~TIC80_OPERAND_MASK;
-	  insn[0] = insn[0] | (num << shift);
-	  break;
-	case O_constant:
-	  if ((flags & TIC80_OPERAND_ENDMASK) && (num == 32))
-	    {
-	      /* Endmask values of 0 and 32 give identical results.  */
-	      num = 0;
-	    }
-	  else if ((flags & TIC80_OPERAND_BITNUM))
-	    {
-	      /* BITNUM values are stored in one's complement form.  */
-	      num = (~num & 0x1F);
-	    }
-	  /* Mask off upper bits, just it case it is signed and is
-	     negative.  */
-	  if (bits < 32)
-	    {
-	      num &= (1 << bits) - 1;
-	      insn[0] = insn[0] | (num << shift);
-	    }
-	  else
-	    {
-	      fx = frag_more (4);
-	      fxfrag = frag_now;
-	      insn[1] = num;
-	    }
-	  break;
-	case O_symbol:
-	  if (bits == 32)
-	    {
-	      fx = frag_more (4);
-	      fxfrag = frag_now;
-	      insn[1] = 0;
-	      if (flags & TIC80_OPERAND_PCREL)
-		{
-		  fix_new_exp (fxfrag,
-			       fx - (fxfrag->fr_literal),
-			       4,
-			       &opers[expi],
-			       1,
-			       R_MPPCR);
-		}
-	      else
-		{
-		  fix_new_exp (fxfrag,
-			       fx - (fxfrag->fr_literal),
-			       4,
-			       &opers[expi],
-			       0,
-			       R_RELLONGX);
-		}
-	    }
-	  else if (flags & TIC80_OPERAND_PCREL)
-	    {
-	      fix_new_exp (ffrag,
-			   f - (ffrag->fr_literal),
-			   4,			/* FIXME! how is this used?  */
-			   &opers[expi],
-			   1,
-			   R_MPPCR15W);
-	    }
-	  else
-	    {
-	      internal_error (_("symbol reloc that is not PC relative or 32 bits"));
-	    }
-	  break;
-	case O_absent:
-	  /* Each O_absent expression can indicate exactly one
-             possible modifier.  */
-	  if ((num & TIC80_OPERAND_M_SI)
-	      && (flags & TIC80_OPERAND_M_SI))
-	    {
-	      insn[0] = insn[0] | (1 << 17);
-	    }
-	  else if ((num & TIC80_OPERAND_M_LI)
-		   && (flags & TIC80_OPERAND_M_LI))
-	    {
-	      insn[0] = insn[0] | (1 << 15);
-	    }
-	  else if ((num & TIC80_OPERAND_SCALED)
-		   && (flags & TIC80_OPERAND_SCALED))
-	    {
-	      insn[0] = insn[0] | (1 << 11);
-	    }
-	  else if ((num & TIC80_OPERAND_PARENS)
-		   && (flags & TIC80_OPERAND_PARENS))
-	    {
-	      /* No code to generate, just accept and discard this
-                 expression.  */
-	    }
-	  else
-	    {
-	      internal_error_a (_("unhandled operand modifier"),
-				(long) opers[expi].X_add_number);
-	    }
-	  break;
-	case O_big:
-	  fx = frag_more (4);
-	  fxfrag = frag_now;
-	  {
-	    int precision = 2;
-	    long exponent_bits = 8L;
-	    LITTLENUM_TYPE words[2];
-	    /* Value is still in generic_floating_point_number.  */
-	    gen_to_words (words, precision, exponent_bits);
-	    insn[1] = (words[0] << 16) | words[1];
-	  }
-	  break;
-	case O_illegal:
-	case O_symbol_rva:
-	case O_uminus:
-	case O_bit_not:
-	case O_logical_not:
-	case O_multiply:
-	case O_divide:
-	case O_modulus:
-	case O_left_shift:
-	case O_right_shift:
-	case O_bit_inclusive_or:
-	case O_bit_or_not:
-	case O_bit_exclusive_or:
-	case O_bit_and:
-	case O_add:
-	case O_subtract:
-	case O_eq:
-	case O_ne:
-	case O_lt:
-	case O_le:
-	case O_ge:
-	case O_gt:
-	case O_logical_and:
-	case O_logical_or:
-	case O_max:
-	default:
-	  internal_error_a (_("unhandled expression"), (long) X_op);
-	  break;
-	}
-    }
-
-  /* Write out the instruction, either 4 or 8 bytes.  */
-
-  md_number_to_chars (f, insn[0], 4);
-  if (fx != NULL)
-    {
-      md_number_to_chars (fx, insn[1], 4);
-    }
-}
-
-/* This is the main entry point for the machine-dependent assembler.  Gas
-   calls this function for each input line which does not contain a
-   pseudoop.
-
-  STR points to a NULL terminated machine dependent instruction.  This
-  function is supposed to emit the frags/bytes it assembles to.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  char *scan;
-  unsigned char *input_line_save;
-  struct tic80_opcode *opcode;
-  expressionS myops[16];
-
-  /* Ensure there is something there to assemble.  */
-  assert (str);
-
-  /* Drop any leading whitespace.  */
-  while (ISSPACE (*str))
-    str++;
-
-  /* Isolate the mnemonic from the rest of the string by finding the first
-     whitespace character and zapping it to a null byte.  */
-  for (scan = str; *scan != '\000' && !ISSPACE (*scan); scan++)
-    ;
-
-  if (*scan != '\000')
-    *scan++ = '\000';
-
-  /* Try to find this mnemonic in the hash table.  */
-  if ((opcode = (struct tic80_opcode *) hash_find (tic80_hash, str)) == NULL)
-    {
-      as_bad (_("Invalid mnemonic: '%s'"), str);
-      return;
-    }
-
-  str = scan;
-  while (ISSPACE (*scan))
-    scan++;
-
-  input_line_save = input_line_pointer;
-  input_line_pointer = str;
-
-  opcode = find_opcode (opcode, myops);
-  if (opcode == NULL)
-    as_bad (_("Invalid operands: '%s'"), input_line_save);
-
-  input_line_pointer = input_line_save;
-  build_insn (opcode, myops);
-}
-
-/* This function is called once at the start of assembly, after the command
-   line arguments have been parsed and all the machine independent
-   initializations have been completed.
-
-   It should set up all the tables, etc., that the machine dependent part of
-   the assembler will need.  */
-
-void
-md_begin ()
-{
-  char *prev_name = "";
-  register const struct tic80_opcode *op;
-  register const struct tic80_opcode *op_end;
-  const struct predefined_symbol *pdsp;
-  extern int coff_flags;			/* Defined in obj-coff.c  */
-
-  /* Set F_AR32WR in coff_flags, which will end up in the file header
-     f_flags field.  */
-
-  coff_flags |= F_AR32WR;	/* TIc80 is 32 bit little endian.  */
-
-  /* Insert unique names into hash table.  The TIc80 instruction set
-     has many identical opcode names that have different opcodes based
-     on the operands.  This hash table then provides a quick index to
-     the first opcode with a particular name in the opcode table.  */
-
-  tic80_hash = hash_new ();
-  op_end = tic80_opcodes + tic80_num_opcodes;
-  for (op = tic80_opcodes; op < op_end; op++)
-    {
-      if (strcmp (prev_name, op->name) != 0)
-	{
-	  prev_name = (char *) op->name;
-	  hash_insert (tic80_hash, op->name, (char *) op);
-	}
-    }
-
-  /* Insert the predefined symbols into the symbol table.  We use
-     symbol_create rather than symbol_new so that these symbols don't
-     end up in the object files' symbol table.  Note that the values
-     of the predefined symbols include some upper bits that
-     distinguish the type of the symbol (register, bitnum, condition
-     code, etc) and these bits must be masked away before actually
-     inserting the values into the instruction stream.  For registers
-     we put these bits in the symbol table since we use them later and
-     there is no question that they aren't part of the register
-     number.  For constants we can't do that since the constant can be
-     any value, so they are masked off before putting them into the
-     symbol table.  */
-
-  pdsp = NULL;
-  while ((pdsp = tic80_next_predefined_symbol (pdsp)) != NULL)
-    {
-      segT segment;
-      valueT valu;
-      int symtype;
-
-      symtype = PDS_VALUE (pdsp) & TIC80_OPERAND_MASK;
-      switch (symtype)
-	{
-	case TIC80_OPERAND_GPR:
-	case TIC80_OPERAND_FPA:
-	case TIC80_OPERAND_CR:
-	  segment = reg_section;
-	  valu = PDS_VALUE (pdsp);
-	  break;
-	case TIC80_OPERAND_CC:
-	case TIC80_OPERAND_BITNUM:
-	  segment = absolute_section;
-	  valu = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK;
-	  break;
-	default:
-	  internal_error_a (_("unhandled predefined symbol bits"),
-			    (long) symtype);
-	  break;
-	}
-      symbol_table_insert (symbol_create (PDS_NAME (pdsp), segment, valu,
-					  &zero_address_frag));
-    }
-}
-
-/* The assembler adds md_shortopts to the string passed to getopt.  */
-
-const char *md_shortopts = "";
-
-/* The assembler adds md_longopts to the machine independent long options
-   that are passed to getopt.  */
-
-struct option md_longopts[] = {
-
-#define OPTION_RELAX	(OPTION_MD_BASE)
-  {"relax", no_argument, NULL, OPTION_RELAX},
-
-#define OPTION_NO_RELAX	(OPTION_RELAX + 1)
-  {"no-relax", no_argument, NULL, OPTION_NO_RELAX},
-
-  {NULL, no_argument, NULL, 0}
-};
-
-size_t md_longopts_size = sizeof (md_longopts);
-
-/* The md_parse_option function will be called whenever getopt returns an
-   unrecognized code, presumably indicating a special code value which
-   appears in md_longopts for machine specific command line options.  */
-
-int
-md_parse_option (c, arg)
-     int c;
-     char *arg ATTRIBUTE_UNUSED;
-{
-  switch (c)
-    {
-    case OPTION_RELAX:
-      tic80_relax = 1;
-      break;
-    case OPTION_NO_RELAX:
-      tic80_relax = 0;
-      break;
-    default:
-      return (0);
-    }
-  return (1);
-}
-
-/* The md_show_usage function will be called whenever a usage message is
-   printed.  It should print a description of the machine specific options
-   found in md_longopts.  */
-
-void
-md_show_usage (stream)
-     FILE *stream;
-{
-  fprintf (stream, "\
-TIc80 options:\n\
--relax			alter PC relative branch instructions to use long form when needed\n\
--no-relax		always use short PC relative branch instructions, error on overflow\n");
-}
-
-/* Attempt to simplify or even eliminate a fixup.  The return value is
-   ignored; perhaps it was once meaningful, but now it is historical.
-   To indicate that a fixup has been eliminated, set fixP->fx_done.  */
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = * (long *) valP;
-  char *dest = fixP->fx_frag->fr_literal + fixP->fx_where;
-  int overflow;
-
-  switch (fixP->fx_r_type)
-    {
-    case R_RELLONGX:
-      md_number_to_chars (dest, (valueT) val, 4);
-      break;
-    case R_MPPCR:
-      val >>= 2;
-      val += 1;	  /* Target address computed from inst start */
-      md_number_to_chars (dest, (valueT) val, 4);
-      break;
-    case R_MPPCR15W:
-      overflow = (val < -65536L) || (val > 65532L);
-      if (overflow)
-	{
-	  as_bad_where (fixP->fx_file, fixP->fx_line,
-			_("PC offset 0x%lx outside range 0x%lx-0x%lx"),
-			val, -65536L, 65532L);
-	}
-      else
-	{
-	  val >>= 2;
-	  *dest++ = val & 0xFF;
-	  val >>= 8;
-	  *dest = (*dest & 0x80) | (val & 0x7F);
-	}
-      break;
-    case R_ABS:
-      md_number_to_chars (dest, (valueT) val, fixP->fx_size);
-      break;
-    default:
-      internal_error_a (_("unhandled relocation type in fixup"),
-			(long) fixP->fx_r_type);
-      break;
-    }
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-}
-
-/* Functions concerning relocs.  */
-
-/* The location from which a PC relative jump should be calculated,
-   given a PC relative reloc.
-
-   For the TIc80, this is the address of the 32 bit opcode containing
-   the PC relative field.  */
-
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  return (fixP->fx_frag->fr_address + fixP->fx_where);
-}
-
-/* Called after relax() is finished.
- * In:	Address of frag.
- *	fr_type == rs_machine_dependent.
- *	fr_subtype is what the address relaxed to.
- *
- * Out:	Any fixSs and constants are set up.
- *	Caller will turn frag into a ".space 0".
- */
-
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP ATTRIBUTE_UNUSED;
-{
-  internal_error (_("md_convert_frag() not implemented yet"));
-  abort ();
-}
-
-void
-tc_coff_symbol_emit_hook (ignore)
-     symbolS *ignore ATTRIBUTE_UNUSED;
-{
-}
-
-#if defined OBJ_COFF
-
-short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
-{
-  return (fixP->fx_r_type);
-}
-
-#endif /* OBJ_COFF */
diff --git a/gas/config/tc-tic80.h b/gas/config/tc-tic80.h
deleted file mode 100644
index 749cf4276311..000000000000
--- a/gas/config/tc-tic80.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* This file is tc-tic80.h
-   Copyright 1996, 1997, 2000 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define TC_TIC80
-
-#define TARGET_BYTES_BIG_ENDIAN 0
-
-#define TARGET_ARCH	bfd_arch_tic80
-#define TARGET_FORMAT	"coff-tic80"
-#define BFD_ARCH	TARGET_ARCH
-
-/* We need the extra field in the fixup struct to put the relocation in.  */
-
-#define NEED_FX_R_TYPE
-
-/* Define md_number_to_chars as the appropriate standard big endian or
-   little endian function.  Should we someday support endianness as a
-   runtime decision, this will need to change.  */
-
-#define md_number_to_chars number_to_chars_littleendian
-
-/* Define away the call to md_operand in the expression parsing code.
-   This is called whenever the expression parser can't parse the input
-   and gives the assembler backend a chance to deal with it instead.  */
-
-#define md_operand(x)
-
-#ifdef OBJ_COFF
-
-/* COFF specific definitions.  */
-
-#define COFF_MAGIC	TIC80_ARCH_MAGIC
-
-/* Whether a reloc should be output.  */
-
-#define TC_COUNT_RELOC(fixp) ((fixp) -> fx_addsy != NULL)
-
-/* This macro translates between an internal fix and a coff reloc type. */
-
-#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
-
-extern short tc_coff_fix2rtype PARAMS ((struct fix *));
-
-#endif	/* OBJ_COFF */
diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index d53a97313d75..798495616014 100644
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -1,6 +1,6 @@
 /* tc-v850.c -- Assembler code for the NEC V850
-   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
+   2006  Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -43,7 +43,8 @@ static int machine = -1;
 static int processor_mask = -1;
 
 /* Structure to hold information about predefined registers.  */
-struct reg_name {
+struct reg_name
+{
   const char *name;
   int value;
 };
@@ -69,7 +70,8 @@ const char EXP_CHARS[] = "eE";
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
 
-const relax_typeS md_relax_table[] = {
+const relax_typeS md_relax_table[] =
+{
   /* Conditional branches.  */
   {0xff,     -0x100,    2, 1},
   {0x1fffff, -0x200000, 6, 0},
@@ -81,8 +83,10 @@ const relax_typeS md_relax_table[] = {
 static int  v850_relax = 0;
 
 /* Fixups.  */
-#define MAX_INSN_FIXUPS (5)
-struct v850_fixup {
+#define MAX_INSN_FIXUPS   5
+
+struct v850_fixup
+{
   expressionS exp;
   int opindex;
   bfd_reloc_code_real_type reloc;
@@ -152,20 +156,15 @@ struct v850_seg_entry v850_seg_table[] =
 #define CALL_TABLE_TEXT_SECTION	12
 #define BSS_SECTION		13
 
-static void do_v850_seg PARAMS ((int, subsegT));
-
 static void
-do_v850_seg (i, sub)
-     int i;
-     subsegT sub;
+do_v850_seg (int i, subsegT sub)
 {
   struct v850_seg_entry *seg = v850_seg_table + i;
 
   obj_elf_section_change_hook ();
+
   if (seg->s != NULL)
-    {
-      subseg_set (seg->s, sub);
-    }
+    subseg_set (seg->s, sub);
   else
     {
       seg->s = subseg_new (seg->name, sub);
@@ -175,11 +174,8 @@ do_v850_seg (i, sub)
     }
 }
 
-static void v850_seg PARAMS ((int i));
-
 static void
-v850_seg (i)
-     int i;
+v850_seg (int i)
 {
   subsegT sub = get_absolute_expression ();
 
@@ -187,11 +183,8 @@ v850_seg (i)
   demand_empty_rest_of_line ();
 }
 
-static void v850_offset PARAMS ((int));
-
 static void
-v850_offset (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+v850_offset (int ignore ATTRIBUTE_UNUSED)
 {
   char *pfrag;
   int temp = get_absolute_expression ();
@@ -205,11 +198,8 @@ v850_offset (ignore)
 
 /* Copied from obj_elf_common() in gas/config/obj-elf.c.  */
 
-static void v850_comm PARAMS ((int));
-
 static void
-v850_comm (area)
-     int area;
+v850_comm (int area)
 {
   char *name;
   char c;
@@ -261,11 +251,9 @@ v850_comm (area)
   if (S_GET_VALUE (symbolP) != 0)
     {
       if (S_GET_VALUE (symbolP) != size)
-	{
-	  /* xgettext:c-format  */
-	  as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
-		   S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
-	}
+	/* xgettext:c-format  */
+	as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."),
+		 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size);
     }
 
   know (symbol_get_frag (symbolP) == &zero_address_frag);
@@ -441,8 +429,10 @@ v850_comm (area)
 	  input_line_pointer--;
 	  goto bad_common_segment;
 	}
+
       while (*input_line_pointer++ != '"')
 	;
+
       goto allocate_common;
     }
 
@@ -466,11 +456,8 @@ v850_comm (area)
   }
 }
 
-static void set_machine PARAMS ((int));
-
 static void
-set_machine (number)
-     int number;
+set_machine (int number)
 {
   machine = number;
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine);
@@ -483,11 +470,8 @@ set_machine (number)
     }
 }
 
-static void v850_longcode PARAMS ((int));
-
 static void
-v850_longcode (type)
-     int type;
+v850_longcode (int type)
 {
   expressionS ex;
 
@@ -552,10 +536,10 @@ static struct hash_control *v850_hash;
 /* This table is sorted.  Suitable for searching by a binary search.  */
 static const struct reg_name pre_defined_registers[] =
 {
-  { "ep",  30 },		/* ep - element ptr */
-  { "gp",   4 },		/* gp - global ptr  */
-  { "hp",   2 },		/* hp - handler stack ptr  */
-  { "lp",  31 },		/* lp - link ptr  */
+  { "ep",  30 },		/* ep - element ptr.  */
+  { "gp",   4 },		/* gp - global ptr.  */
+  { "hp",   2 },		/* hp - handler stack ptr.  */
+  { "lp",  31 },		/* lp - link ptr.  */
   { "r0",   0 },
   { "r1",   1 },
   { "r10", 10 },
@@ -588,8 +572,8 @@ static const struct reg_name pre_defined_registers[] =
   { "r7",   7 },
   { "r8",   8 },
   { "r9",   9 },
-  { "sp",   3 },		/* sp - stack ptr  */
-  { "tp",   5 },		/* tp - text ptr  */
+  { "sp",   3 },		/* sp - stack ptr.  */
+  { "tp",   5 },		/* tp - text ptr.  */
   { "zero", 0 },
 };
 
@@ -663,15 +647,11 @@ static const struct reg_name cc_names[] =
    valid regiter name.  Return the register number from the array on
    success, or -1 on failure.  */
 
-static int reg_name_search
-  PARAMS ((const struct reg_name *, int, const char *, bfd_boolean));
-
 static int
-reg_name_search (regs, regcount, name, accept_numbers)
-     const struct reg_name *regs;
-     int regcount;
-     const char *name;
-     bfd_boolean accept_numbers;
+reg_name_search (const struct reg_name *regs,
+		 int regcount,
+		 const char *name,
+		 bfd_boolean accept_numbers)
 {
   int middle, low, high;
   int cmp;
@@ -683,10 +663,8 @@ reg_name_search (regs, regcount, name, accept_numbers)
       /* If the symbol is an alias for another name then use that.
 	 If the symbol is an alias for a number, then return the number.  */
       if (symbol_equated_p (symbolP))
-	{
-	  name
-	    = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
-	}
+	name
+	  = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol);
       else if (accept_numbers)
 	{
 	  int reg = S_GET_VALUE (symbolP);
@@ -726,11 +704,8 @@ reg_name_search (regs, regcount, name, accept_numbers)
   	Input_line_pointer->(next non-blank) char after operand, or is in
   	its original state.  */
 
-static bfd_boolean register_name PARAMS ((expressionS *));
-
 static bfd_boolean
-register_name (expressionP)
-     expressionS *expressionP;
+register_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -783,14 +758,10 @@ register_name (expressionP)
   	Input_line_pointer->(next non-blank) char after operand, or is in
   	its original state.  */
 
-static bfd_boolean system_register_name
-  PARAMS ((expressionS *, bfd_boolean, bfd_boolean));
-
 static bfd_boolean
-system_register_name (expressionP, accept_numbers, accept_list_names)
-     expressionS *expressionP;
-     bfd_boolean accept_numbers;
-     bfd_boolean accept_list_names;
+system_register_name (expressionS *expressionP,
+		      bfd_boolean accept_numbers,
+		      bfd_boolean accept_list_names)
 {
   int reg_number;
   char *name;
@@ -821,9 +792,7 @@ system_register_name (expressionP, accept_numbers, accept_list_names)
 	  if (reg_number < 0
 	      || (reg_number > 5 && reg_number < 16)
 	      || reg_number > 27)
-	    {
-	      reg_number = -1;
-	    }
+	    reg_number = -1;
 	}
       else if (accept_list_names)
 	{
@@ -867,11 +836,8 @@ system_register_name (expressionP, accept_numbers, accept_list_names)
   	Input_line_pointer->(next non-blank) char after operand, or is in
   	its original state.  */
 
-static bfd_boolean cc_name PARAMS ((expressionS *));
-
 static bfd_boolean
-cc_name (expressionP)
-     expressionS *expressionP;
+cc_name (expressionS *expressionP)
 {
   int reg_number;
   char *name;
@@ -908,10 +874,8 @@ cc_name (expressionP)
     }
 }
 
-static void skip_white_space PARAMS ((void));
-
 static void
-skip_white_space ()
+skip_white_space (void)
 {
   while (*input_line_pointer == ' '
 	 || *input_line_pointer == '\t')
@@ -943,23 +907,22 @@ skip_white_space ()
    and so on upwards.  System registers are considered to be very
    high numbers.  */
 
-static char *parse_register_list
-  PARAMS ((unsigned long *, const struct v850_operand *));
-
 static char *
-parse_register_list (insn, operand)
-     unsigned long *insn;
-     const struct v850_operand *operand;
+parse_register_list (unsigned long *insn,
+		     const struct v850_operand *operand)
 {
-  static int type1_regs[32] = {
+  static int type1_regs[32] =
+  {
     30,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
      0,  0,  0,  0,  0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
   };
-  static int type2_regs[32] = {
+  static int type2_regs[32] =
+  {
     19, 18, 17, 16,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
      0,  0,  0,  0, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24
   };
-  static int type3_regs[32] = {
+  static int type3_regs[32] =
+  {
      3,  2,  1,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
      0,  0,  0,  0, 14, 15, 13, 12,  7,  6,  5,  4, 11, 10,  9,  8
   };
@@ -1143,15 +1106,15 @@ parse_register_list (insn, operand)
 
 const char *md_shortopts = "m:";
 
-struct option md_longopts[] = {
+struct option md_longopts[] =
+{
   {NULL, no_argument, NULL, 0}
 };
 
 size_t md_longopts_size = sizeof (md_longopts);
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _(" V850 options:\n"));
   fprintf (stream, _("  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"));
@@ -1164,26 +1127,17 @@ md_show_usage (stream)
 }
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   if (c != 'm')
-    {
-      if (c != 'a')
-	/* xgettext:c-format  */
-	fprintf (stderr, _("unknown command line option: -%c%s\n"), c, arg);
-      return 0;
-    }
+    return 0;
 
   if (strcmp (arg, "warn-signed-overflow") == 0)
-    {
-      warn_signed_overflows = TRUE;
-    }
+    warn_signed_overflows = TRUE;
+
   else if (strcmp (arg, "warn-unsigned-overflow") == 0)
-    {
-      warn_unsigned_overflows = TRUE;
-    }
+    warn_unsigned_overflows = TRUE;
+
   else if (strcmp (arg, "v850") == 0)
     {
       machine = 0;
@@ -1211,27 +1165,19 @@ md_parse_option (c, arg)
   else if (strcmp (arg, "relax") == 0)
     v850_relax = 1;
   else
-    {
-      /* xgettext:c-format  */
-      fprintf (stderr, _("unknown command line option: -%c%s\n"), c, arg);
-      return 0;
-    }
+    return 0;
 
   return 1;
 }
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 char *
-md_atof (type, litp, sizep)
-     int type;
-     char *litp;
-     int *sizep;
+md_atof (int type, char *litp, int *sizep)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -1271,18 +1217,33 @@ md_atof (type, litp, sizep)
 /* Very gross.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec;
-     fragS *fragP;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 asection *sec,
+		 fragS *fragP)
 {
+  /* This code performs some nasty type punning between the
+     fr_opcode field of the frag structure (a char *) and the
+     fx_r_type field of the fix structure (a bfd_reloc_code_real_type)
+     On a 64bit host this causes problems because these two fields
+     are not the same size, but since we know that we are only
+     ever storing small integers in the fields, it is safe to use
+     a union to convert between them.  */
+  union u
+  {
+    bfd_reloc_code_real_type fx_r_type;
+    char * fr_opcode;
+  }
+  opcode_converter;
   subseg_change (sec, 0);
 
+  opcode_converter.fr_opcode = fragP->fr_opcode;
+      
   /* In range conditional or unconditional branch.  */
   if (fragP->fr_subtype == 0 || fragP->fr_subtype == 2)
     {
       fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
-	       fragP->fr_offset, 1, BFD_RELOC_UNUSED + (int)fragP->fr_opcode);
+	       fragP->fr_offset, 1,
+	       BFD_RELOC_UNUSED + opcode_converter.fx_r_type);
       fragP->fr_fix += 2;
     }
   /* Out of range conditional branch.  Emit a branch around a jump.  */
@@ -1302,10 +1263,10 @@ md_convert_frag (abfd, sec, fragP)
 
       /* Now create the unconditional branch + fixup to the final
 	 target.  */
-      md_number_to_chars (buffer + 2, 0x00000780, 4);
+      md_number_to_chars ((char *) buffer + 2, 0x00000780, 4);
       fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol,
-	       fragP->fr_offset, 1, BFD_RELOC_UNUSED +
-	       (int) fragP->fr_opcode + 1);
+	       fragP->fr_offset, 1,
+	       BFD_RELOC_UNUSED + opcode_converter.fx_r_type + 1);
       fragP->fr_fix += 6;
     }
   /* Out of range unconditional branch.  Emit a jump.  */
@@ -1313,8 +1274,8 @@ md_convert_frag (abfd, sec, fragP)
     {
       md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4);
       fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
-	       fragP->fr_offset, 1, BFD_RELOC_UNUSED +
-	       (int) fragP->fr_opcode + 1);
+	       fragP->fr_offset, 1,
+	       BFD_RELOC_UNUSED + opcode_converter.fx_r_type + 1);
       fragP->fr_fix += 4;
     }
   else
@@ -1322,16 +1283,14 @@ md_convert_frag (abfd, sec, fragP)
 }
 
 valueT
-md_section_align (seg, addr)
-     asection *seg;
-     valueT addr;
+md_section_align (asection *seg, valueT addr)
 {
   int align = bfd_get_section_alignment (stdoutput, seg);
   return ((addr + (1 << align) - 1) & (-1 << align));
 }
 
 void
-md_begin ()
+md_begin (void)
 {
   char *prev_name = "";
   const struct v850_opcode *op;
@@ -1386,12 +1345,27 @@ md_begin ()
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, machine);
 }
 
-static bfd_reloc_code_real_type handle_ctoff
-  PARAMS ((const struct v850_operand *));
+static bfd_reloc_code_real_type
+handle_lo16 (const struct v850_operand *operand)
+{
+  if (operand != NULL)
+    {
+      if (operand->bits == -1)
+	return BFD_RELOC_V850_LO16_SPLIT_OFFSET;
+
+      if (!(operand->bits == 16 && operand->shift == 16)
+	  && !(operand->bits == 15 && operand->shift == 17))
+	{
+	  as_bad (_("lo() relocation used on an instruction which does "
+		    "not support it"));
+	  return BFD_RELOC_64;  /* Used to indicate an error condition.  */
+	}
+    }
+  return BFD_RELOC_LO16;
+}
 
 static bfd_reloc_code_real_type
-handle_ctoff (operand)
-     const struct v850_operand *operand;
+handle_ctoff (const struct v850_operand *operand)
 {
   if (operand == NULL)
     return BFD_RELOC_V850_CALLT_16_16_OFFSET;
@@ -1406,12 +1380,8 @@ handle_ctoff (operand)
   return BFD_RELOC_V850_CALLT_6_7_OFFSET;
 }
 
-static bfd_reloc_code_real_type handle_sdaoff
-  PARAMS ((const struct v850_operand *));
-
 static bfd_reloc_code_real_type
-handle_sdaoff (operand)
-     const struct v850_operand *operand;
+handle_sdaoff (const struct v850_operand *operand)
 {
   if (operand == NULL)
     return BFD_RELOC_V850_SDA_16_16_OFFSET;
@@ -1432,12 +1402,8 @@ handle_sdaoff (operand)
   return BFD_RELOC_V850_SDA_16_16_OFFSET;
 }
 
-static bfd_reloc_code_real_type handle_zdaoff
-  PARAMS ((const struct v850_operand *));
-
 static bfd_reloc_code_real_type
-handle_zdaoff (operand)
-     const struct v850_operand *operand;
+handle_zdaoff (const struct v850_operand *operand)
 {
   if (operand == NULL)
     return BFD_RELOC_V850_ZDA_16_16_OFFSET;
@@ -1459,31 +1425,27 @@ handle_zdaoff (operand)
   return BFD_RELOC_V850_ZDA_16_16_OFFSET;
 }
 
-static bfd_reloc_code_real_type handle_tdaoff
-  PARAMS ((const struct v850_operand *));
-
 static bfd_reloc_code_real_type
-handle_tdaoff (operand)
-     const struct v850_operand *operand;
+handle_tdaoff (const struct v850_operand *operand)
 {
   if (operand == NULL)
     /* Data item, not an instruction.  */
     return BFD_RELOC_V850_TDA_7_7_OFFSET;
 
   if (operand->bits == 6 && operand->shift == 1)
-    /* sld.w/sst.w, operand: D8_6  */
+    /* sld.w/sst.w, operand: D8_6.  */
     return BFD_RELOC_V850_TDA_6_8_OFFSET;
 
   if (operand->bits == 4 && operand->insert != NULL)
-    /* sld.hu, operand: D5-4  */
+    /* sld.hu, operand: D5-4.  */
     return BFD_RELOC_V850_TDA_4_5_OFFSET;
 
   if (operand->bits == 4 && operand->insert == NULL)
-    /* sld.bu, operand: D4   */
+    /* sld.bu, operand: D4.   */
     return BFD_RELOC_V850_TDA_4_4_OFFSET;
 
   if (operand->bits == 16 && operand->shift == 16)
-    /* set1 & chums, operands: D16  */
+    /* set1 & chums, operands: D16.  */
     return BFD_RELOC_V850_TDA_16_16_OFFSET;
 
   if (operand->bits != 7)
@@ -1494,20 +1456,16 @@ handle_tdaoff (operand)
     }
 
   return  operand->insert != NULL
-    ? BFD_RELOC_V850_TDA_7_8_OFFSET     /* sld.h/sst.h, operand: D8_7  */
-    : BFD_RELOC_V850_TDA_7_7_OFFSET;    /* sld.b/sst.b, operand: D7    */
+    ? BFD_RELOC_V850_TDA_7_8_OFFSET     /* sld.h/sst.h, operand: D8_7.  */
+    : BFD_RELOC_V850_TDA_7_7_OFFSET;    /* sld.b/sst.b, operand: D7.    */
 }
 
 /* Warning: The code in this function relies upon the definitions
    in the v850_operands[] array (defined in opcodes/v850-opc.c)
    matching the hard coded values contained herein.  */
 
-static bfd_reloc_code_real_type v850_reloc_prefix
-  PARAMS ((const struct v850_operand *));
-
 static bfd_reloc_code_real_type
-v850_reloc_prefix (operand)
-     const struct v850_operand *operand;
+v850_reloc_prefix (const struct v850_operand *operand)
 {
   bfd_boolean paren_skipped = FALSE;
 
@@ -1527,7 +1485,7 @@ v850_reloc_prefix (operand)
 
   CHECK_ ("hi0",    BFD_RELOC_HI16	   );
   CHECK_ ("hi",	    BFD_RELOC_HI16_S	   );
-  CHECK_ ("lo",	    BFD_RELOC_LO16	   );
+  CHECK_ ("lo",	    handle_lo16 (operand)  );
   CHECK_ ("sdaoff", handle_sdaoff (operand));
   CHECK_ ("zdaoff", handle_zdaoff (operand));
   CHECK_ ("tdaoff", handle_tdaoff (operand));
@@ -1543,18 +1501,13 @@ v850_reloc_prefix (operand)
 
 /* Insert an operand value into an instruction.  */
 
-static unsigned long v850_insert_operand
-  PARAMS ((unsigned long, const struct v850_operand *, offsetT, char *,
-	   unsigned int, char *));
-
 static unsigned long
-v850_insert_operand (insn, operand, val, file, line, str)
-     unsigned long insn;
-     const struct v850_operand *operand;
-     offsetT val;
-     char *file;
-     unsigned int line;
-     char *str;
+v850_insert_operand (unsigned long insn,
+		     const struct v850_operand *operand,
+		     offsetT val,
+		     char *file,
+		     unsigned int line,
+		     char *str)
 {
   if (operand->insert)
     {
@@ -1618,10 +1571,7 @@ v850_insert_operand (insn, operand, val, file, line, str)
 
 	  if (val < (offsetT) min || val > (offsetT) max)
 	    {
-	      /* xgettext:c-format  */
-	      const char *err =
-		_("operand out of range (%s not between %ld and %ld)");
-	      char buf[100];
+	      char buf [128];
 
 	      /* Restore min and mix to expected values for decimal ranges.  */
 	      if ((operand->flags & V850_OPERAND_SIGNED)
@@ -1633,18 +1583,12 @@ v850_insert_operand (insn, operand, val, file, line, str)
 		min = 0;
 
 	      if (str)
-		{
-		  sprintf (buf, "%s: ", str);
-
-		  sprint_value (buf + strlen (buf), val);
-		}
+		sprintf (buf, "%s: ", str);
 	      else
-		sprint_value (buf, val);
+		buf[0] = 0;
+	      strcat (buf, _("operand"));
 
-	      if (file == (char *) NULL)
-		as_warn (err, buf, min, max);
-	      else
-		as_warn_where (file, line, err, buf, min, max);
+	      as_bad_value_out_of_range (buf, val, (offsetT) min, (offsetT) max, file, line);
 	    }
 	}
 
@@ -1657,8 +1601,7 @@ v850_insert_operand (insn, operand, val, file, line, str)
 static char copy_of_instruction[128];
 
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   char *s;
   char *start_of_operands;
@@ -1732,9 +1675,7 @@ md_assemble (str)
 	  bfd_reloc_code_real_type reloc;
 
 	  if (next_opindex == 0)
-	    {
-	      operand = &v850_operands[*opindex_ptr];
-	    }
+	    operand = &v850_operands[*opindex_ptr];
 	  else
 	    {
 	      operand = &v850_operands[next_opindex];
@@ -1775,6 +1716,7 @@ md_assemble (str)
 		      /* Fall through.  */
 
 		    case BFD_RELOC_LO16:
+		    case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
 		      {
 			/* Truncate, then sign extend the value.  */
 			ex.X_add_number = SEXT16 (ex.X_add_number);
@@ -1856,9 +1798,7 @@ md_assemble (str)
 	      if ((operand->flags & V850_OPERAND_REG) != 0)
 		{
 		  if (!register_name (&ex))
-		    {
-		      errmsg = _("invalid register name");
-		    }
+		    errmsg = _("invalid register name");
 		  else if ((operand->flags & V850_NOT_R0)
 			   && ex.X_add_number == 0)
 		    {
@@ -1873,9 +1813,7 @@ md_assemble (str)
 	      else if ((operand->flags & V850_OPERAND_SRG) != 0)
 		{
 		  if (!system_register_name (&ex, TRUE, FALSE))
-		    {
-		      errmsg = _("invalid system register name");
-		    }
+		    errmsg = _("invalid system register name");
 		}
 	      else if ((operand->flags & V850_OPERAND_EP) != 0)
 		{
@@ -1903,9 +1841,7 @@ md_assemble (str)
 	      else if ((operand->flags & V850_OPERAND_CC) != 0)
 		{
 		  if (!cc_name (&ex))
-		    {
-		      errmsg = _("invalid condition code name");
-		    }
+		    errmsg = _("invalid condition code name");
 		}
 	      else if (operand->flags & V850E_PUSH_POP)
 		{
@@ -1997,14 +1933,12 @@ md_assemble (str)
 		}
 	      else if (system_register_name (&ex, FALSE, FALSE)
 		       && (operand->flags & V850_OPERAND_SRG) == 0)
-		{
-		  errmsg = _("syntax error: system register not expected");
-		}
+		errmsg = _("syntax error: system register not expected");
+
 	      else if (cc_name (&ex)
 		       && (operand->flags & V850_OPERAND_CC) == 0)
-		{
-		  errmsg = _("syntax error: condition code not expected");
-		}
+		errmsg = _("syntax error: condition code not expected");
+
 	      else
 		{
 		  expression (&ex);
@@ -2025,13 +1959,6 @@ md_assemble (str)
 	      if (errmsg)
 		goto error;
 
-#if 0
-	      fprintf (stderr,
-		       " insn: %x, operand %d, op: %d, add_number: %d\n",
-		       insn, opindex_ptr - opcode->operands,
-		       ex.X_op, ex.X_add_number);
-#endif
-
 	      switch (ex.X_op)
 		{
 		case O_illegal:
@@ -2048,14 +1975,12 @@ md_assemble (str)
 		      goto error;
 		    }
 		  insn = v850_insert_operand (insn, operand, ex.X_add_number,
-					      (char *) NULL, 0,
-					      copy_of_instruction);
+					      NULL, 0, copy_of_instruction);
 		  break;
 
 		case O_constant:
 		  insn = v850_insert_operand (insn, operand, ex.X_add_number,
-					      (char *) NULL, 0,
-					      copy_of_instruction);
+					      NULL, 0, copy_of_instruction);
 		  break;
 
 		default:
@@ -2127,6 +2052,20 @@ md_assemble (str)
 
   if (relaxable && fc > 0)
     {
+      /* On a 64-bit host the size of an 'int' is not the same
+	 as the size of a pointer, so we need a union to convert
+	 the opindex field of the fr_cgen structure into a char *
+	 so that it can be stored in the frag.  We do not have
+	 to worry about loosing accuracy as we are not going to
+	 be even close to the 32bit limit of the int.  */
+      union
+      {
+	int opindex;
+	char * ptr;
+      }
+      opindex_converter;
+
+      opindex_converter.opindex = fixups[0].opindex;
       insn_size = 2;
       fc = 0;
 
@@ -2135,7 +2074,7 @@ md_assemble (str)
 	  f = frag_var (rs_machine_dependent, 4, 2, 2,
 			fixups[0].exp.X_add_symbol,
 			fixups[0].exp.X_add_number,
-			(char *) fixups[0].opindex);
+			opindex_converter.ptr);
 	  md_number_to_chars (f, insn, insn_size);
 	  md_number_to_chars (f + 2, 0, 2);
 	}
@@ -2144,7 +2083,7 @@ md_assemble (str)
 	  f = frag_var (rs_machine_dependent, 6, 4, 0,
 			fixups[0].exp.X_add_symbol,
 			fixups[0].exp.X_add_number,
-			(char *) fixups[0].opindex);
+			opindex_converter.ptr);
 	  md_number_to_chars (f, insn, insn_size);
 	  md_number_to_chars (f + 2, 0, 4);
 	}
@@ -2178,7 +2117,7 @@ md_assemble (str)
      BFD_RELOC_UNUSED plus the operand index.  This lets us easily
      handle fixups for any operand type, although that is admittedly
      not a very exciting feature.  We pick a BFD reloc type in
-     md_apply_fix3.  */
+     md_apply_fix.  */
   for (i = 0; i < fc; i++)
     {
       const struct v850_operand *operand;
@@ -2216,9 +2155,12 @@ md_assemble (str)
 			      reloc_howto->pc_relative,
 			      reloc);
 
+	  fixP->tc_fix_data = (void *) operand;
+
 	  switch (reloc)
 	    {
 	    case BFD_RELOC_LO16:
+	    case BFD_RELOC_V850_LO16_SPLIT_OFFSET:
 	    case BFD_RELOC_HI16:
 	    case BFD_RELOC_HI16_S:
 	      fixP->fx_no_overflow = 1;
@@ -2245,14 +2187,12 @@ md_assemble (str)
    then it is done here.  */
 
 arelent *
-tc_gen_reloc (seg, fixp)
-     asection *seg ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
-  reloc		      = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr  = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc		      = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address      = fixp->fx_frag->fr_address + fixp->fx_where;
 
@@ -2273,7 +2213,7 @@ tc_gen_reloc (seg, fixp)
 
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
 
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  if (reloc->howto == NULL)
     {
       as_bad_where (fixp->fx_file, fixp->fx_line,
 		    /* xgettext:c-format  */
@@ -2289,8 +2229,7 @@ tc_gen_reloc (seg, fixp)
 }
 
 void
-v850_handle_align (frag)
-     fragS * frag;
+v850_handle_align (fragS * frag)
 {
   if (v850_relax
       && frag->fr_type == rs_align
@@ -2307,9 +2246,7 @@ v850_handle_align (frag)
 /* Return current size of variable part of frag.  */
 
 int
-md_estimate_size_before_relax (fragp, seg)
-     fragS *fragp;
-     asection *seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED)
 {
   if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0]))
     abort ();
@@ -2318,9 +2255,7 @@ md_estimate_size_before_relax (fragp, seg)
 }
 
 long
-v850_pcrel_from_section (fixp, section)
-     fixS *fixp;
-     segT section;
+v850_pcrel_from_section (fixS *fixp, segT section)
 {
   /* If the symbol is undefined, or in a section other than our own,
      or it is weak (in which case it may well be in another section,
@@ -2335,10 +2270,7 @@ v850_pcrel_from_section (fixp, section)
 }
 
 void
-md_apply_fix3 (fixP, valueP, seg)
-     fixS *fixP;
-     valueT *valueP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
 {
   valueT value = * valueP;
   char *where;
@@ -2367,11 +2299,9 @@ md_apply_fix3 (fixP, valueP, seg)
 	  if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)
 	    value -= S_GET_VALUE (fixP->fx_subsy);
 	  else
-	    {
-	      /* We don't actually support subtracting a symbol.  */
-	      as_bad_where (fixP->fx_file, fixP->fx_line,
-			    _("expression too complex"));
-	    }
+	    /* We don't actually support subtracting a symbol.  */
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("expression too complex"));
 	}
       fixP->fx_addnumber = value;
     }
@@ -2410,10 +2340,6 @@ md_apply_fix3 (fixP, valueP, seg)
 	fixP->fx_r_type = BFD_RELOC_V850_9_PCREL;
       else
 	{
-#if 0
-	  fprintf (stderr, "bits: %d, insn: %x\n", operand->bits, insn);
-#endif
-
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
 			_("unresolved expression that must be resolved"));
 	  fixP->fx_done = 1;
@@ -2425,12 +2351,44 @@ md_apply_fix3 (fixP, valueP, seg)
       /* We still have to insert the value into memory!  */
       where = fixP->fx_frag->fr_literal + fixP->fx_where;
 
-      if (fixP->fx_size == 1)
-	*where = value & 0xff;
-      else if (fixP->fx_size == 2)
-	bfd_putl16 (value & 0xffff, (unsigned char *) where);
-      else if (fixP->fx_size == 4)
-	bfd_putl32 (value, (unsigned char *) where);
+      if (fixP->tc_fix_data != NULL
+	  && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL)
+	{
+	  const char * message = NULL;
+	  struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data;
+	  unsigned long insn;
+
+	  /* The variable "where" currently points at the exact point inside
+	     the insn where we need to insert the value.  But we need to
+	     extract the entire insn so we probably need to move "where"
+	     back a few bytes.  */
+	  if (fixP->fx_size == 2)
+	    where -= 2;
+	  else if (fixP->fx_size == 1)
+	    where -= 3;
+
+	  insn = bfd_getl32 ((unsigned char *) where);
+
+	  /* Use the operand's insertion procedure, if present, in order to
+	     make sure that the value is correctly stored in the insn.  */
+	  insn = operand->insert (insn, (offsetT) value, & message);
+	  /* Ignore message even if it is set.  */
+
+	  bfd_putl32 ((bfd_vma) insn, (unsigned char *) where);
+	}
+      else
+	{
+	  if (fixP->fx_r_type == BFD_RELOC_V850_LO16_SPLIT_OFFSET)
+	    bfd_putl32 (((value << 16) & 0xfffe0000)
+			| ((value << 5) & 0x20)
+			| (bfd_getl32 (where) & ~0xfffe0020), where);
+	  else if (fixP->fx_size == 1)
+	    *where = value & 0xff;
+	  else if (fixP->fx_size == 2)
+	    bfd_putl16 (value & 0xffff, (unsigned char *) where);
+	  else if (fixP->fx_size == 4)
+	    bfd_putl32 (value, (unsigned char *) where);
+	}
     }
 }
 
@@ -2438,8 +2396,7 @@ md_apply_fix3 (fixP, valueP, seg)
    on the v850.  */
 
 void
-parse_cons_expression_v850 (exp)
-     expressionS *exp;
+parse_cons_expression_v850 (expressionS *exp)
 {
   /* See if there's a reloc prefix like hi() we have to handle.  */
   hold_cons_reloc = v850_reloc_prefix (NULL);
@@ -2453,11 +2410,10 @@ parse_cons_expression_v850 (exp)
    appropriate one based on the size of the expression.  */
 
 void
-cons_fix_new_v850 (frag, where, size, exp)
-     fragS *frag;
-     int where;
-     int size;
-     expressionS *exp;
+cons_fix_new_v850 (fragS *frag,
+		   int where,
+		   int size,
+		   expressionS *exp)
 {
   if (hold_cons_reloc == BFD_RELOC_UNUSED)
     {
@@ -2478,8 +2434,7 @@ cons_fix_new_v850 (frag, where, size, exp)
 }
 
 bfd_boolean
-v850_fix_adjustable (fixP)
-     fixS *fixP;
+v850_fix_adjustable (fixS *fixP)
 {
   if (fixP->fx_addsy == NULL)
     return 1;
@@ -2497,8 +2452,7 @@ v850_fix_adjustable (fixP)
 }
 
 int
-v850_force_relocation (fixP)
-     struct fix *fixP;
+v850_force_relocation (struct fix *fixP)
 {
   if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL
       || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP)
diff --git a/gas/config/tc-v850.h b/gas/config/tc-v850.h
index 26b1bf1e6608..f9ec80456781 100644
--- a/gas/config/tc-v850.h
+++ b/gas/config/tc-v850.h
@@ -1,5 +1,5 @@
 /* tc-v850.h -- Header file for tc-v850.c.
-   Copyright 1996, 1997, 1998, 2000, 2001, 2002
+   Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_V850
 
@@ -25,10 +25,6 @@
 
 #define TARGET_BYTES_BIG_ENDIAN 0
 
-#ifndef BFD_ASSEMBLER
- #error V850 support requires BFD_ASSEMBLER
-#endif
-
 /* The target BFD architecture.  */
 #define TARGET_ARCH 		bfd_arch_v850
 
@@ -38,13 +34,13 @@
 #define md_operand(x)
 
 #define tc_fix_adjustable(FIX) v850_fix_adjustable (FIX)
-extern bfd_boolean v850_fix_adjustable PARAMS ((struct fix *));
+extern bfd_boolean v850_fix_adjustable (struct fix *);
 
 #define TC_FORCE_RELOCATION(FIX) v850_force_relocation(FIX)
-extern int v850_force_relocation PARAMS ((struct fix *));
+extern int v850_force_relocation (struct fix *);
 
 #ifdef OBJ_ELF
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 #endif
 
@@ -61,10 +57,10 @@ extern int v850_force_relocation PARAMS ((struct fix *));
 /* We need to handle lo(), hi(), etc etc in .hword, .word, etc
    directives, so we have to parse "cons" expressions ourselves.  */
 #define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) parse_cons_expression_v850 (EXP)
-extern void parse_cons_expression_v850 PARAMS ((expressionS *));
+extern void parse_cons_expression_v850 (expressionS *);
 
 #define TC_CONS_FIX_NEW cons_fix_new_v850
-extern void cons_fix_new_v850 PARAMS ((fragS *, int, int, expressionS *));
+extern void cons_fix_new_v850 (fragS *, int, int, expressionS *);
 
 #define TC_GENERIC_RELAX_TABLE md_relax_table
 extern const struct relax_type md_relax_table[];
@@ -72,9 +68,14 @@ extern const struct relax_type md_relax_table[];
 /* When relaxing, we need to generate
    relocations for alignment directives.  */
 #define HANDLE_ALIGN(frag) v850_handle_align (frag)
-extern void v850_handle_align PARAMS ((fragS *));
+extern void v850_handle_align (fragS *);
 
 #define MD_PCREL_FROM_SECTION(FIX, SEC) v850_pcrel_from_section (FIX, SEC)
-extern long v850_pcrel_from_section PARAMS ((struct fix *, asection *));
+extern long v850_pcrel_from_section (struct fix *, asection *);
 
 #define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+/* We need to record the operand involved when a pseudo-reloc is
+   processed so that the resulting value can be inserted correctly.  */
+#define TC_FIX_TYPE             void *
+#define TC_INIT_FIX_DATA(fixP)  (fixP)->tc_fix_data = NULL
diff --git a/gas/config/tc-vax.c b/gas/config/tc-vax.c
index 1e1c1282aa0c..b0ac3f745f36 100644
--- a/gas/config/tc-vax.c
+++ b/gas/config/tc-vax.c
@@ -1,5 +1,6 @@
 /* tc-vax.c - vax-specific -
-   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1998, 2000, 2001, 2002, 2003
+   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1998, 2000, 2001, 2002,
+   2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,14 +17,15 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
 #include "vax-inst.h"
 #include "obstack.h"		/* For FRAG_APPEND_1_CHAR macro in "frags.h" */
 #include "subsegs.h"
+#include "safe-ctype.h"
 
 #ifdef OBJ_ELF
 #include "elf/vax.h"
@@ -39,19 +41,19 @@ const char line_comment_chars[] = "#";
 
 const char line_separator_chars[] = ";";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
-/* Chars that mean this number is a floating point constant */
-/* as in 0f123.456 */
-/* or    0H1.234E-12 (see exp chars above) */
+/* Chars that mean this number is a floating point constant
+   as in 0f123.456
+   or    0H1.234E-12 (see exp chars above).  */
 const char FLT_CHARS[] = "dDfFgGhH";
 
 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
    changed in read.c .  Ideally it shouldn't have to know about it at all,
    but nothing is ideal around here.  */
 
-/* Hold details of an operand expression */
+/* Hold details of an operand expression.  */
 static expressionS exp_of_operand[VIT_MAX_OPERANDS];
 static segT seg_of_operand[VIT_MAX_OPERANDS];
 
@@ -66,8 +68,8 @@ FLONUM_TYPE float_operand[VIT_MAX_OPERANDS];
 #ifdef OBJ_ELF
 #define GLOBAL_OFFSET_TABLE_NAME	"_GLOBAL_OFFSET_TABLE_"
 #define PROCEDURE_LINKAGE_TABLE_NAME	"_PROCEDURE_LINKAGE_TABLE_"
-symbolS *GOT_symbol;		/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
-symbolS *PLT_symbol;		/* Pre-defined "_PROCEDURE_LINKAGE_TABLE_" */
+symbolS *GOT_symbol;		/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
+symbolS *PLT_symbol;		/* Pre-defined "_PROCEDURE_LINKAGE_TABLE_".  */
 #endif
 
 int flag_hash_long_names;	/* -+ */
@@ -78,23 +80,21 @@ int flag_no_hash_mixed_case;	/* -h NUM */
 int flag_want_pic;		/* -k */
 #endif
 
-/*
- * For VAX, relative addresses of "just the right length" are easy.
- * The branch displacement is always the last operand, even in
- * synthetic instructions.
- * For VAX, we encode the relax_substateTs (in e.g. fr_substate) as:
- *
- *		    4       3       2       1       0	     bit number
- *	---/ /--+-------+-------+-------+-------+-------+
- *		|     what state ?	|  how long ?	|
- *	---/ /--+-------+-------+-------+-------+-------+
- *
- * The "how long" bits are 00=byte, 01=word, 10=long.
- * This is a Un*x convention.
- * Not all lengths are legit for a given value of (what state).
- * The "how long" refers merely to the displacement length.
- * The address usually has some constant bytes in it as well.
- *
+/* For VAX, relative addresses of "just the right length" are easy.
+   The branch displacement is always the last operand, even in
+   synthetic instructions.
+   For VAX, we encode the relax_substateTs (in e.g. fr_substate) as:
+
+  		    4       3       2       1       0	     bit number
+  	---/ /--+-------+-------+-------+-------+-------+
+  		|     what state ?	|  how long ?	|
+  	---/ /--+-------+-------+-------+-------+-------+
+
+   The "how long" bits are 00=byte, 01=word, 10=long.
+   This is a Un*x convention.
+   Not all lengths are legit for a given value of (what state).
+   The "how long" refers merely to the displacement length.
+   The address usually has some constant bytes in it as well.
 
  groups for VAX address relaxing.
 
@@ -181,8 +181,7 @@ int flag_want_pic;		/* -k */
  We can change an opcode's lowest order bit without breaking anything else.
 
  We sometimes store context in the operand literal. This way we can figure out
- after relax() what the original addressing mode was.
- */
+ after relax() what the original addressing mode was.  */
 
 /* These displacements are relative to the start address of the
    displacement.  The first letter is Byte, Word.  2nd letter is
@@ -191,7 +190,7 @@ int flag_want_pic;		/* -k */
 #define BB (1+-128)
 #define WF (2+ 32767)
 #define WB (2+-32768)
-/* Dont need LF, LB because they always reach. [They are coded as 0.] */
+/* Dont need LF, LB because they always reach. [They are coded as 0.]  */
 
 #define C(a,b) ENCODE_RELAX(a,b)
 /* This macro has no side-effects.  */
@@ -238,7 +237,8 @@ const relax_typeS md_relax_table[] =
 #undef WF
 #undef WB
 
-void float_cons PARAMS ((int));
+void float_cons (int);
+int flonum_gen2vax (char, FLONUM_TYPE *, LITTLENUM_TYPE *);
 
 const pseudo_typeS md_pseudo_table[] =
 {
@@ -246,6 +246,10 @@ const pseudo_typeS md_pseudo_table[] =
   {"ffloat", float_cons, 'f'},
   {"gfloat", float_cons, 'g'},
   {"hfloat", float_cons, 'h'},
+  {"d_floating", float_cons, 'd'},
+  {"f_floating", float_cons, 'f'},
+  {"g_floating", float_cons, 'g'},
+  {"h_floating", float_cons, 'h'},
   {NULL, NULL, 0},
 };
 
@@ -258,47 +262,12 @@ const pseudo_typeS md_pseudo_table[] =
 #define STATE_BYTE			(0)
 #define STATE_WORD			(1)
 #define STATE_LONG			(2)
-#define STATE_UNDF			(3)	/* Symbol undefined in pass1 */
+#define STATE_UNDF			(3)	/* Symbol undefined in pass1.  */
 
 #define min(a, b)	((a) < (b) ? (a) : (b))
-
-int flonum_gen2vax PARAMS ((char format_letter, FLONUM_TYPE * f,
-			    LITTLENUM_TYPE * words));
-static const char *vip_begin PARAMS ((int, const char *, const char *,
-				      const char *));
-static void vip_op_1 PARAMS ((int, const char *));
-static void vip_op_defaults PARAMS ((const char *, const char *, const char *));
-static void vip_op PARAMS ((char *, struct vop *));
-static void vip PARAMS ((struct vit *, char *));
-
-static int vax_reg_parse PARAMS ((char, char, char, char));
-
-void
-md_begin ()
-{
-  const char *errtxt;
-  FLONUM_TYPE *fP;
-  int i;
-
-  if ((errtxt = vip_begin (1, "$", "*", "`")) != 0)
-    {
-      as_fatal (_("VIP_BEGIN error:%s"), errtxt);
-    }
-
-  for (i = 0, fP = float_operand;
-       fP < float_operand + VIT_MAX_OPERANDS;
-       i++, fP++)
-    {
-      fP->low = &big_operand_bits[i][0];
-      fP->high = &big_operand_bits[i][SIZE_OF_LARGE_NUMBER - 1];
-    }
-}
 
 void
-md_number_to_chars (con, value, nbytes)
-     char con[];
-     valueT value;
-     int nbytes;
+md_number_to_chars (char con[], valueT value, int nbytes)
 {
   number_to_chars_littleendian (con, value, nbytes);
 }
@@ -307,18 +276,14 @@ md_number_to_chars (con, value, nbytes)
    that they reference.  */
 
 void				/* Knows about order of bytes in address.  */
-md_apply_fix3 (fixP, valueP, seg)
-     fixS *fixP;
-     valueT *valueP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
 {
   valueT value = * valueP;
-#ifdef BFD_ASSEMBLER
+
   if (((fixP->fx_addsy == NULL && fixP->fx_subsy == NULL)
        && fixP->fx_r_type != BFD_RELOC_32_PLT_PCREL
        && fixP->fx_r_type != BFD_RELOC_32_GOT_PCREL)
       || fixP->fx_r_type == NO_RELOC)
-#endif
     number_to_chars_littleendian (fixP->fx_where + fixP->fx_frag->fr_literal,
 				  value, fixP->fx_size);
 
@@ -326,12 +291,15 @@ md_apply_fix3 (fixP, valueP, seg)
     fixP->fx_done = 1;
 }
 
-long
-md_chars_to_number (con, nbytes)
-     unsigned char con[];	/* Low order byte 1st.  */
-     int nbytes;		/* Number of bytes in the input.  */
+/* Convert a number from VAX byte order (little endian)
+   into host byte order.
+   con		is the buffer to convert,
+   nbytes	is the length of the given buffer.  */
+static long
+md_chars_to_number (unsigned char con[], int nbytes)
 {
   long retval;
+
   for (retval = 0, con += nbytes - 1; nbytes--; con--)
     {
       retval <<= BITS_PER_CHAR;
@@ -339,893 +307,60 @@ md_chars_to_number (con, nbytes)
     }
   return retval;
 }
-
-/* vax:md_assemble() emit frags for 1 instruction */
 
-void
-md_assemble (instruction_string)
-     char *instruction_string;	/* A string: assemble 1 instruction.  */
+/* Copy a bignum from in to out.
+   If the output is shorter than the input, copy lower-order
+   littlenums.  Return 0 or the number of significant littlenums
+   dropped.  Assumes littlenum arrays are densely packed: no unused
+   chars between the littlenums. Uses memcpy() to move littlenums, and
+   wants to know length (in chars) of the input bignum.  */
+
+static int
+bignum_copy (LITTLENUM_TYPE *in,
+	     int in_length,	/* in sizeof(littlenum)s */
+	     LITTLENUM_TYPE *out,
+	     int out_length	/* in sizeof(littlenum)s */)
 {
-  /* Non-zero if operand expression's segment is not known yet.  */
-  int is_undefined;
-  /* Non-zero if operand expression's segment is absolute.  */
-  int is_absolute;
+  int significant_littlenums_dropped;
 
-  int length_code;
-  char *p;
-  /* An operand. Scans all operands.  */
-  struct vop *operandP;
-  char *save_input_line_pointer;
-			/* What used to live after an expression.  */
-  char c_save;
-  /* 1: instruction_string bad for all passes.  */
-  int goofed;
-  /* Points to slot just after last operand.  */
-  struct vop *end_operandP;
-  /* Points to expression values for this operand.  */
-  expressionS *expP;
-  segT *segP;
-
-  /* These refer to an instruction operand expression.  */
-  /* Target segment of the address.	 */
-  segT to_seg;
-  valueT this_add_number;
-  /* Positive (minuend) symbol.  */
-  symbolS *this_add_symbol;
-  /* As a number.  */
-  long opcode_as_number;
-  /* Least significant byte 1st.  */
-  char *opcode_as_chars;
-  /* As an array of characters.  */
-  /* Least significant byte 1st */
-  char *opcode_low_byteP;
-  /* length (bytes) meant by vop_short.  */
-  int length;
-  /* 0, or 1 if '@' is in addressing mode.  */
-  int at;
-  /* From vop_nbytes: vax_operand_width (in bytes) */
-  int nbytes;
-  FLONUM_TYPE *floatP;
-  LITTLENUM_TYPE literal_float[8];
-  /* Big enough for any floating point literal.  */
-
-  vip (&v, instruction_string);
-
-  /*
-   * Now we try to find as many as_warn()s as we can. If we do any as_warn()s
-   * then goofed=1. Notice that we don't make any frags yet.
-   * Should goofed be 1, then this instruction will wedge in any pass,
-   * and we can safely flush it, without causing interpass symbol phase
-   * errors. That is, without changing label values in different passes.
-   */
-  if ((goofed = (*v.vit_error)) != 0)
+  if (out_length < in_length)
     {
-      as_fatal (_("Ignoring statement due to \"%s\""), v.vit_error);
-    }
-  /*
-   * We need to use expression() and friends, which require us to diddle
-   * input_line_pointer. So we save it and restore it later.
-   */
-  save_input_line_pointer = input_line_pointer;
-  for (operandP = v.vit_operand,
-       expP = exp_of_operand,
-       segP = seg_of_operand,
-       floatP = float_operand,
-       end_operandP = v.vit_operand + v.vit_operands;
-
-       operandP < end_operandP;
+      LITTLENUM_TYPE *p;	/* -> most significant (non-zero) input
+				      littlenum.  */
 
-       operandP++, expP++, segP++, floatP++)
-    {				/* for each operand */
-      if (operandP->vop_error)
-	{
-	  as_fatal (_("Aborting because statement has \"%s\""), operandP->vop_error);
-	  goofed = 1;
-	}
-      else
+      memcpy ((void *) out, (void *) in,
+	      (unsigned int) out_length << LITTLENUM_SHIFT);
+      for (p = in + in_length - 1; p >= in; --p)
 	{
-	  /* Statement has no syntax goofs: let's sniff the expression.  */
-	  int can_be_short = 0;	/* 1 if a bignum can be reduced to a short literal.  */
-
-	  input_line_pointer = operandP->vop_expr_begin;
-	  c_save = operandP->vop_expr_end[1];
-	  operandP->vop_expr_end[1] = '\0';
-	  /* If to_seg == SEG_PASS1, expression() will have set need_pass_2 = 1.  */
-	  *segP = expression (expP);
-	  switch (expP->X_op)
-	    {
-	    case O_absent:
-	      /* for BSD4.2 compatibility, missing expression is absolute 0 */
-	      expP->X_op = O_constant;
-	      expP->X_add_number = 0;
-	      /* For SEG_ABSOLUTE, we shouldn't need to set X_op_symbol,
-		 X_add_symbol to any particular value.  But, we will program
-		 defensively. Since this situation occurs rarely so it costs
-		 us little to do, and stops Dean worrying about the origin of
-		 random bits in expressionS's.  */
-	      expP->X_add_symbol = NULL;
-	      expP->X_op_symbol = NULL;
-	      break;
-
-	    case O_symbol:
-	    case O_constant:
-	      break;
-
-	    default:
-	      /*
-	       * Major bug. We can't handle the case of a
-	       * SEG_OP expression in a VIT_OPCODE_SYNTHETIC
-	       * variable-length instruction.
-	       * We don't have a frag type that is smart enough to
-	       * relax a SEG_OP, and so we just force all
-	       * SEG_OPs to behave like SEG_PASS1s.
-	       * Clearly, if there is a demand we can invent a new or
-	       * modified frag type and then coding up a frag for this
-	       * case will be easy. SEG_OP was invented for the
-	       * .words after a CASE opcode, and was never intended for
-	       * instruction operands.
-	       */
-	      need_pass_2 = 1;
-	      as_fatal (_("Can't relocate expression"));
-	      break;
-
-	    case O_big:
-	      /* Preserve the bits.  */
-	      if (expP->X_add_number > 0)
-		{
-		  bignum_copy (generic_bignum, expP->X_add_number,
-			       floatP->low, SIZE_OF_LARGE_NUMBER);
-		}
-	      else
-		{
-		  know (expP->X_add_number < 0);
-		  flonum_copy (&generic_floating_point_number,
-			       floatP);
-		  if (strchr ("s i", operandP->vop_short))
-		    {
-		      /* Could possibly become S^# */
-		      flonum_gen2vax (-expP->X_add_number, floatP, literal_float);
-		      switch (-expP->X_add_number)
-			{
-			case 'f':
-			  can_be_short =
-			    (literal_float[0] & 0xFC0F) == 0x4000
-			    && literal_float[1] == 0;
-			  break;
-
-			case 'd':
-			  can_be_short =
-			    (literal_float[0] & 0xFC0F) == 0x4000
-			    && literal_float[1] == 0
-			    && literal_float[2] == 0
-			    && literal_float[3] == 0;
-			  break;
-
-			case 'g':
-			  can_be_short =
-			    (literal_float[0] & 0xFF81) == 0x4000
-			    && literal_float[1] == 0
-			    && literal_float[2] == 0
-			    && literal_float[3] == 0;
-			  break;
-
-			case 'h':
-			  can_be_short = ((literal_float[0] & 0xFFF8) == 0x4000
-					  && (literal_float[1] & 0xE000) == 0
-					  && literal_float[2] == 0
-					  && literal_float[3] == 0
-					  && literal_float[4] == 0
-					  && literal_float[5] == 0
-					  && literal_float[6] == 0
-					  && literal_float[7] == 0);
-			  break;
-
-			default:
-			  BAD_CASE (-expP->X_add_number);
-			  break;
-			}	/* switch (float type) */
-		    }		/* if (could want to become S^#...) */
-		}		/* bignum or flonum ? */
-
-	      if (operandP->vop_short == 's'
-		  || operandP->vop_short == 'i'
-		  || (operandP->vop_short == ' '
-		      && operandP->vop_reg == 0xF
-		      && (operandP->vop_mode & 0xE) == 0x8))
-		{
-		  /* Saw a '#'.  */
-		  if (operandP->vop_short == ' ')
-		    {
-		      /* We must chose S^ or I^.  */
-		      if (expP->X_add_number > 0)
-			{
-			  /* Bignum: Short literal impossible.  */
-			  operandP->vop_short = 'i';
-			  operandP->vop_mode = 8;
-			  operandP->vop_reg = 0xF;	/* VAX PC.  */
-			}
-		      else
-			{
-			  /* Flonum: Try to do it.  */
-			  if (can_be_short)
-			    {
-			      operandP->vop_short = 's';
-			      operandP->vop_mode = 0;
-			      operandP->vop_ndx = -1;
-			      operandP->vop_reg = -1;
-			      expP->X_op = O_constant;
-			    }
-			  else
-			    {
-			      operandP->vop_short = 'i';
-			      operandP->vop_mode = 8;
-			      operandP->vop_reg = 0xF;	/* VAX PC */
-			    }
-			}	/* bignum or flonum ? */
-		    }		/*  if #, but no S^ or I^ seen.  */
-		  /* No more ' ' case: either 's' or 'i'.  */
-		  if (operandP->vop_short == 's')
-		    {
-		      /* Wants to be a short literal.  */
-		      if (expP->X_add_number > 0)
-			{
-			  as_warn (_("Bignum not permitted in short literal. Immediate mode assumed."));
-			  operandP->vop_short = 'i';
-			  operandP->vop_mode = 8;
-			  operandP->vop_reg = 0xF;	/* VAX PC.  */
-			}
-		      else
-			{
-			  if (!can_be_short)
-			    {
-			      as_warn (_("Can't do flonum short literal: immediate mode used."));
-			      operandP->vop_short = 'i';
-			      operandP->vop_mode = 8;
-			      operandP->vop_reg = 0xF;	/* VAX PC.  */
-			    }
-			  else
-			    {	/* Encode short literal now.  */
-			      int temp = 0;
-
-			      switch (-expP->X_add_number)
-				{
-				case 'f':
-				case 'd':
-				  temp = literal_float[0] >> 4;
-				  break;
-
-				case 'g':
-				  temp = literal_float[0] >> 1;
-				  break;
-
-				case 'h':
-				  temp = ((literal_float[0] << 3) & 070)
-				    | ((literal_float[1] >> 13) & 07);
-				  break;
-
-				default:
-				  BAD_CASE (-expP->X_add_number);
-				  break;
-				}
-
-			      floatP->low[0] = temp & 077;
-			      floatP->low[1] = 0;
-			    }	/* if can be short literal float */
-			}	/* flonum or bignum ? */
-		    }
-		  else
-		    {		/* I^# seen: set it up if float.  */
-		      if (expP->X_add_number < 0)
-			{
-			  memcpy (floatP->low, literal_float, sizeof (literal_float));
-			}
-		    }		/* if S^# seen.  */
-		}
-	      else
-		{
-		  as_warn (_("A bignum/flonum may not be a displacement: 0x%lx used"),
-			   (expP->X_add_number = 0x80000000L));
-		  /* Chosen so luser gets the most offset bits to patch later.  */
-		}
-	      expP->X_add_number = floatP->low[0]
-		| ((LITTLENUM_MASK & (floatP->low[1])) << LITTLENUM_NUMBER_OF_BITS);
-	      /*
-	       * For the O_big case we have:
-	       * If vop_short == 's' then a short floating literal is in the
-	       *	lowest 6 bits of floatP -> low [0], which is
-	       *	big_operand_bits [---] [0].
-	       * If vop_short == 'i' then the appropriate number of elements
-	       *	of big_operand_bits [---] [...] are set up with the correct
-	       *	bits.
-	       * Also, just in case width is byte word or long, we copy the lowest
-	       * 32 bits of the number to X_add_number.
-	       */
-	      break;
-	    }
-	  if (input_line_pointer != operandP->vop_expr_end + 1)
-	    {
-	      as_fatal ("Junk at end of expression \"%s\"", input_line_pointer);
-	      goofed = 1;
-	    }
-	  operandP->vop_expr_end[1] = c_save;
+	  if (*p)
+	    break;
 	}
-    }				/* for(each operand) */
-
-  input_line_pointer = save_input_line_pointer;
+      significant_littlenums_dropped = p - in - in_length + 1;
 
-  if (need_pass_2 || goofed)
-    {
-      return;
+      if (significant_littlenums_dropped < 0)
+	significant_littlenums_dropped = 0;
     }
-
-  /* Emit op-code.  */
-  /* Remember where it is, in case we want to modify the op-code later.  */
-  opcode_low_byteP = frag_more (v.vit_opcode_nbytes);
-  memcpy (opcode_low_byteP, v.vit_opcode, v.vit_opcode_nbytes);
-  opcode_as_number = md_chars_to_number (opcode_as_chars = v.vit_opcode, 4);
-  for (operandP = v.vit_operand,
-       expP = exp_of_operand,
-       segP = seg_of_operand,
-       floatP = float_operand,
-       end_operandP = v.vit_operand + v.vit_operands;
-
-       operandP < end_operandP;
-
-       operandP++,
-       floatP++,
-       segP++,
-       expP++)
+  else
     {
-      if (operandP->vop_ndx >= 0)
-	{
-	  /* indexed addressing byte */
-	  /* Legality of indexed mode already checked: it is OK */
-	  FRAG_APPEND_1_CHAR (0x40 + operandP->vop_ndx);
-	}			/* if(vop_ndx>=0) */
+      memcpy ((char *) out, (char *) in,
+	      (unsigned int) in_length << LITTLENUM_SHIFT);
 
-      /* Here to make main operand frag(s).  */
-      this_add_number = expP->X_add_number;
-      this_add_symbol = expP->X_add_symbol;
-      to_seg = *segP;
-#ifdef BFD_ASSEMBLER
-      is_undefined = (to_seg == undefined_section);
-      is_absolute = (to_seg == absolute_section);
-#else
-      is_undefined = (to_seg == SEG_UNKNOWN);
-      is_absolute = (to_seg == SEG_ABSOLUTE);
-#endif
-      at = operandP->vop_mode & 1;
-      length = (operandP->vop_short == 'b'
-		? 1 : (operandP->vop_short == 'w'
-		       ? 2 : (operandP->vop_short == 'l'
-			      ? 4 : 0)));
-      nbytes = operandP->vop_nbytes;
-      if (operandP->vop_access == 'b')
-	{
-	  if (to_seg == now_seg || is_undefined)
-	    {
-	      /* If is_undefined, then it might BECOME now_seg.  */
-	      if (nbytes)
-		{
-		  p = frag_more (nbytes);
-		  fix_new (frag_now, p - frag_now->fr_literal, nbytes,
-			   this_add_symbol, this_add_number, 1, NO_RELOC);
-		}
-	      else
-		{		/* to_seg==now_seg || to_seg == SEG_UNKNOWN */
-		  /* nbytes==0 */
-		  length_code = is_undefined ? STATE_UNDF : STATE_BYTE;
-		  if (opcode_as_number & VIT_OPCODE_SPECIAL)
-		    {
-		      if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
-			{
-			  /* br or jsb */
-			  frag_var (rs_machine_dependent, 5, 1,
-			    ENCODE_RELAX (STATE_ALWAYS_BRANCH, length_code),
-				    this_add_symbol, this_add_number,
-				    opcode_low_byteP);
-			}
-		      else
-			{
-			  if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
-			    {
-			      length_code = STATE_WORD;
-			      /* JF: There is no state_byte for this one! */
-			      frag_var (rs_machine_dependent, 10, 2,
-					ENCODE_RELAX (STATE_COMPLEX_BRANCH, length_code),
-					this_add_symbol, this_add_number,
-					opcode_low_byteP);
-			    }
-			  else
-			    {
-			      know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
-			      frag_var (rs_machine_dependent, 9, 1,
-			      ENCODE_RELAX (STATE_COMPLEX_HOP, length_code),
-					this_add_symbol, this_add_number,
-					opcode_low_byteP);
-			    }
-			}
-		    }
-		  else
-		    {
-		      know (operandP->vop_width == VAX_WIDTH_CONDITIONAL_JUMP);
-		      frag_var (rs_machine_dependent, 7, 1,
-		       ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code),
-				this_add_symbol, this_add_number,
-				opcode_low_byteP);
-		    }
-		}
-	    }
-	  else
-	    {
-	      /* to_seg != now_seg && to_seg != SEG_UNKNOWN */
-	      /*
-	       * --- SEG FLOAT MAY APPEAR HERE ----
-	       */
-	      if (is_absolute)
-		{
-		  if (nbytes)
-		    {
-		      know (!(opcode_as_number & VIT_OPCODE_SYNTHETIC));
-		      p = frag_more (nbytes);
-		      /* Conventional relocation.  */
-		      fix_new (frag_now, p - frag_now->fr_literal, nbytes,
-#ifdef BFD_ASSEMBLER
-			       section_symbol (absolute_section),
-#else
-			       &abs_symbol,
-#endif
-			       this_add_number, 1, NO_RELOC);
-		    }
-		  else
-		    {
-		      know (opcode_as_number & VIT_OPCODE_SYNTHETIC);
-		      if (opcode_as_number & VIT_OPCODE_SPECIAL)
-			{
-			  if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
-			    {
-			      /* br or jsb */
-			      *opcode_low_byteP = opcode_as_chars[0] + VAX_WIDEN_LONG;
-			      know (opcode_as_chars[1] == 0);
-			      p = frag_more (5);
-			      p[0] = VAX_ABSOLUTE_MODE;	/* @#...  */
-			      md_number_to_chars (p + 1, this_add_number, 4);
-			      /* Now (eg) JMP @#foo or JSB @#foo.  */
-			    }
-			  else
-			    {
-			      if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
-				{
-				  p = frag_more (10);
-				  p[0] = 2;
-				  p[1] = 0;
-				  p[2] = VAX_BRB;
-				  p[3] = 6;
-				  p[4] = VAX_JMP;
-				  p[5] = VAX_ABSOLUTE_MODE;	/* @#...  */
-				  md_number_to_chars (p + 6, this_add_number, 4);
-				  /*
-				   * Now (eg)	ACBx	1f
-				   *		BRB	2f
-				   *	1:	JMP	@#foo
-				   *	2:
-				   */
-				}
-			      else
-				{
-				  know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
-				  p = frag_more (9);
-				  p[0] = 2;
-				  p[1] = VAX_BRB;
-				  p[2] = 6;
-				  p[3] = VAX_JMP;
-                                  p[4] = VAX_ABSOLUTE_MODE;     /* @#...  */
-				  md_number_to_chars (p + 5, this_add_number, 4);
-				  /*
-				   * Now (eg)	xOBxxx	1f
-				   *		BRB	2f
-				   *	1:	JMP	@#foo
-				   *	2:
-				   */
-				}
-			    }
-			}
-		      else
-			{
-			  /* b<cond> */
-			  *opcode_low_byteP ^= 1;
-			  /* To reverse the condition in a VAX branch,
-			     complement the lowest order bit.  */
-			  p = frag_more (7);
-			  p[0] = 6;
-			  p[1] = VAX_JMP;
-			  p[2] = VAX_ABSOLUTE_MODE;	/* @#...  */
-			  md_number_to_chars (p + 3, this_add_number, 4);
-			  /*
-			   * Now (eg)	BLEQ	1f
-			   *		JMP	@#foo
-			   *	1:
-			   */
-			}
-		    }
-		}
-	      else
-		{
-		  /* to_seg != now_seg && !is_undefinfed && !is_absolute */
-		  if (nbytes > 0)
-		    {
-		      /* Pc-relative. Conventional relocation.  */
-		      know (!(opcode_as_number & VIT_OPCODE_SYNTHETIC));
-		      p = frag_more (nbytes);
-		      fix_new (frag_now, p - frag_now->fr_literal, nbytes,
-#ifdef BFD_ASSEMBLER
-			       section_symbol (absolute_section),
-#else
-			       &abs_symbol,
-#endif
-			       this_add_number, 1, NO_RELOC);
-		    }
-		  else
-		    {
-		      know (opcode_as_number & VIT_OPCODE_SYNTHETIC);
-		      if (opcode_as_number & VIT_OPCODE_SPECIAL)
-			{
-			  if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
-			    {
-			      /* br or jsb */
-			      know (opcode_as_chars[1] == 0);
-			      *opcode_low_byteP = opcode_as_chars[0] + VAX_WIDEN_LONG;
-			      p = frag_more (5);
-			      p[0] = VAX_PC_RELATIVE_MODE;
-			      fix_new (frag_now,
-				       p + 1 - frag_now->fr_literal, 4,
-				       this_add_symbol,
-				       this_add_number, 1, NO_RELOC);
-			      /* Now eg JMP foo or JSB foo.  */
-			    }
-			  else
-			    {
-			      if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
-				{
-				  p = frag_more (10);
-				  p[0] = 0;
-				  p[1] = 2;
-				  p[2] = VAX_BRB;
-				  p[3] = 6;
-				  p[4] = VAX_JMP;
-				  p[5] = VAX_PC_RELATIVE_MODE;
-				  fix_new (frag_now,
-					   p + 6 - frag_now->fr_literal, 4,
-					   this_add_symbol,
-					   this_add_number, 1, NO_RELOC);
-				  /*
-				   * Now (eg)	ACBx	1f
-				   *		BRB	2f
-				   *	1:	JMP	foo
-				   *	2:
-				   */
-				}
-			      else
-				{
-				  know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
-				  p = frag_more (10);
-				  p[0] = 2;
-				  p[1] = VAX_BRB;
-				  p[2] = 6;
-				  p[3] = VAX_JMP;
-				  p[4] = VAX_PC_RELATIVE_MODE;
-				  fix_new (frag_now,
-					   p + 5 - frag_now->fr_literal,
-					   4, this_add_symbol,
-					   this_add_number, 1, NO_RELOC);
-				  /*
-				   * Now (eg)	xOBxxx	1f
-				   *		BRB	2f
-				   *	1:	JMP	foo
-				   *	2:
-				   */
-				}
-			    }
-			}
-		      else
-			{
-			  know (operandP->vop_width == VAX_WIDTH_CONDITIONAL_JUMP);
-			  *opcode_low_byteP ^= 1;	/* Reverse branch condition.  */
-			  p = frag_more (7);
-			  p[0] = 6;
-			  p[1] = VAX_JMP;
-			  p[2] = VAX_PC_RELATIVE_MODE;
-			  fix_new (frag_now, p + 3 - frag_now->fr_literal,
-				   4, this_add_symbol,
-				   this_add_number, 1, NO_RELOC);
-			}
-		    }
-		}
-	    }
-	}
-      else
-	{
-	  know (operandP->vop_access != 'b');	/* So it is ordinary operand.  */
-	  know (operandP->vop_access != ' ');	/* ' ' target-independent: elsewhere.  */
-	  know (operandP->vop_access == 'a'
-		|| operandP->vop_access == 'm'
-		|| operandP->vop_access == 'r'
-		|| operandP->vop_access == 'v'
-		|| operandP->vop_access == 'w');
-	  if (operandP->vop_short == 's')
-	    {
-	      if (is_absolute)
-		{
-		  if (this_add_number >= 64)
-		    {
-		      as_warn (_("Short literal overflow(%ld.), immediate mode assumed."),
-			       (long) this_add_number);
-		      operandP->vop_short = 'i';
-		      operandP->vop_mode = 8;
-		      operandP->vop_reg = 0xF;
-		    }
-		}
-	      else
-		{
-		  as_warn (_("Forced short literal to immediate mode. now_seg=%s to_seg=%s"),
-			   segment_name (now_seg), segment_name (to_seg));
-		  operandP->vop_short = 'i';
-		  operandP->vop_mode = 8;
-		  operandP->vop_reg = 0xF;
-		}
-	    }
-	  if (operandP->vop_reg >= 0 && (operandP->vop_mode < 8
-		  || (operandP->vop_reg != 0xF && operandP->vop_mode < 10)))
-	    {
-	      /* One byte operand.  */
-	      know (operandP->vop_mode > 3);
-	      FRAG_APPEND_1_CHAR (operandP->vop_mode << 4 | operandP->vop_reg);
-	      /* All 1-bytes except S^# happen here.  */
-	    }
-	  else
-	    {
-	      /* {@}{q^}foo{(Rn)} or S^#foo */
-	      if (operandP->vop_reg == -1 && operandP->vop_short != 's')
-		{
-		  /* "{@}{q^}foo" */
-		  if (to_seg == now_seg)
-		    {
-		      if (length == 0)
-			{
-			  know (operandP->vop_short == ' ');
-			  length_code = STATE_BYTE;
-#ifdef OBJ_ELF
-			  if (S_IS_EXTERNAL (this_add_symbol)
-			      || S_IS_WEAK (this_add_symbol))
-			    length_code = STATE_UNDF;
-#endif
-			  p = frag_var (rs_machine_dependent, 10, 2,
-			       ENCODE_RELAX (STATE_PC_RELATIVE, length_code),
-					this_add_symbol, this_add_number,
-					opcode_low_byteP);
-			  know (operandP->vop_mode == 10 + at);
-			  *p = at << 4;
-			  /* At is the only context we need to carry
-			     to other side of relax() process.  Must
-			     be in the correct bit position of VAX
-			     operand spec. byte.  */
-			}
-		      else
-			{
-			  know (length);
-			  know (operandP->vop_short != ' ');
-			  p = frag_more (length + 1);
-			  p[0] = 0xF | ((at + "?\12\14?\16"[length]) << 4);
-			  fix_new (frag_now, p + 1 - frag_now->fr_literal,
-				   length, this_add_symbol,
-				   this_add_number, 1, NO_RELOC);
-			}
-		    }
-		  else
-		    {		/* to_seg != now_seg */
-		      if (this_add_symbol == NULL)
-			{
-			  know (is_absolute);
-			  /* Do @#foo: simpler relocation than foo-.(pc) anyway.  */
-			  p = frag_more (5);
-			  p[0] = VAX_ABSOLUTE_MODE;	/* @#...  */
-			  md_number_to_chars (p + 1, this_add_number, 4);
-			  if (length && length != 4)
-			    {
-			      as_warn (_("Length specification ignored. Address mode 9F used"));
-			    }
-			}
-		      else
-			{
-			  /* {@}{q^}other_seg */
-			  know ((length == 0 && operandP->vop_short == ' ')
-			     || (length > 0 && operandP->vop_short != ' '));
-			  if (is_undefined
-#ifdef OBJ_ELF
-			      || S_IS_WEAK(this_add_symbol)
-			      || S_IS_EXTERNAL(this_add_symbol)
-#endif
-			      )
-			    {
-			      switch (length)
-				{
-				default: length_code = STATE_UNDF; break;
-				case 1: length_code = STATE_BYTE; break;
-				case 2: length_code = STATE_WORD; break;
-				case 4: length_code = STATE_LONG; break;
-				}
-			      /*
-			       * We have a SEG_UNKNOWN symbol. It might
-			       * turn out to be in the same segment as
-			       * the instruction, permitting relaxation.
-			       */
-			      p = frag_var (rs_machine_dependent, 5, 2,
-			       ENCODE_RELAX (STATE_PC_RELATIVE, length_code),
-					    this_add_symbol, this_add_number,
-					    opcode_low_byteP);
-			      p[0] = at << 4;
-			    }
-			  else
-			    {
-			      if (length == 0)
-				{
-				  know (operandP->vop_short == ' ');
-				  length = 4;	/* Longest possible.  */
-				}
-			      p = frag_more (length + 1);
-			      p[0] = 0xF | ((at + "?\12\14?\16"[length]) << 4);
-			      md_number_to_chars (p + 1, this_add_number, length);
-			      fix_new (frag_now,
-				       p + 1 - frag_now->fr_literal,
-				       length, this_add_symbol,
-				       this_add_number, 1, NO_RELOC);
-			    }
-			}
-		    }
-		}
-	      else
-		{
-		  /* {@}{q^}foo(Rn) or S^# or I^# or # */
-		  if (operandP->vop_mode < 0xA)
-		    {
-		      /* # or S^# or I^# */
-		      if (operandP->vop_access == 'v'
-			  || operandP->vop_access == 'a')
-			{
-			  if (operandP->vop_access == 'v')
-			    as_warn (_("Invalid operand:  immediate value used as base address."));
-			  else
-			    as_warn (_("Invalid operand:  immediate value used as address."));
-			  /* gcc 2.6.3 is known to generate these in at least
-			     one case.  */
-			}
-		      if (length == 0
-			  && is_absolute && (expP->X_op != O_big)
-			  && operandP->vop_mode == 8	/* No '@'.  */
-			  && this_add_number < 64)
-			{
-			  operandP->vop_short = 's';
-			}
-		      if (operandP->vop_short == 's')
-			{
-			  FRAG_APPEND_1_CHAR (this_add_number);
-			}
-		      else
-			{
-			  /* I^#...  */
-			  know (nbytes);
-			  p = frag_more (nbytes + 1);
-			  know (operandP->vop_reg == 0xF);
-#ifdef OBJ_ELF
-			  if (flag_want_pic && operandP->vop_mode == 8
-				&& this_add_symbol != NULL)
-			    {
-			      as_warn (_("Symbol used as immediate operand in PIC mode."));
-			    }
-#endif
-			  p[0] = (operandP->vop_mode << 4) | 0xF;
-			  if ((is_absolute) && (expP->X_op != O_big))
-			    {
-			      /*
-			       * If nbytes > 4, then we are scrod. We
-			       * don't know if the high order bytes
-			       * are to be 0xFF or 0x00.  BSD4.2 & RMS
-			       * say use 0x00. OK --- but this
-			       * assembler needs ANOTHER rewrite to
-			       * cope properly with this bug.  */
-			      md_number_to_chars (p + 1, this_add_number, min (4, nbytes));
-			      if (nbytes > 4)
-				{
-				  memset (p + 5, '\0', nbytes - 4);
-				}
-			    }
-			  else
-			    {
-			      if (expP->X_op == O_big)
-				{
-				  /*
-				   * Problem here is to get the bytes
-				   * in the right order.  We stored
-				   * our constant as LITTLENUMs, not
-				   * bytes.  */
-				  LITTLENUM_TYPE *lP;
+      if (out_length > in_length)
+	memset ((char *) (out + in_length), '\0',
+		(unsigned int) (out_length - in_length) << LITTLENUM_SHIFT);
 
-				  lP = floatP->low;
-				  if (nbytes & 1)
-				    {
-				      know (nbytes == 1);
-				      p[1] = *lP;
-				    }
-				  else
-				    {
-				      for (p++; nbytes; nbytes -= 2, p += 2, lP++)
-					{
-					  md_number_to_chars (p, *lP, 2);
-					}
-				    }
-				}
-			      else
-				{
-				  fix_new (frag_now, p + 1 - frag_now->fr_literal,
-					   nbytes, this_add_symbol,
-					   this_add_number, 0, NO_RELOC);
-				}
-			    }
-			}
-		    }
-		  else
-		    {		/* {@}{q^}foo(Rn) */
-		      know ((length == 0 && operandP->vop_short == ' ')
-			    || (length > 0 && operandP->vop_short != ' '));
-		      if (length == 0)
-			{
-			  if (is_absolute)
-			    {
-			      long test;
-
-			      test = this_add_number;
-
-			      if (test < 0)
-				test = ~test;
+      significant_littlenums_dropped = 0;
+    }
 
-			      length = test & 0xffff8000 ? 4
-				: test & 0xffffff80 ? 2
-				: 1;
-			    }
-			  else
-			    {
-			      length = 4;
-			    }
-			}
-		      p = frag_more (1 + length);
-		      know (operandP->vop_reg >= 0);
-		      p[0] = operandP->vop_reg
-			| ((at | "?\12\14?\16"[length]) << 4);
-		      if (is_absolute)
-			{
-			  md_number_to_chars (p + 1, this_add_number, length);
-			}
-		      else
-			{
-			  fix_new (frag_now, p + 1 - frag_now->fr_literal,
-				   length, this_add_symbol,
-				   this_add_number, 0, NO_RELOC);
-			}
-		    }
-		}
-	    }			/* if(single-byte-operand) */
-	}
-    }				/* for(operandP) */
-}				/* vax_assemble() */
+  return significant_littlenums_dropped;
+}
 
 /* md_estimate_size_before_relax(), called just before relax().
    Any symbol that is now undefined will not become defined.
    Return the correct fr_subtype in the frag and the growth beyond
    fr_fix.  */
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS *fragP;
-     segT segment;
+md_estimate_size_before_relax (fragS *fragP, segT segment)
 {
   if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF)
     {
@@ -1368,30 +503,17 @@ md_estimate_size_before_relax (fragP, segment)
   return md_relax_table[fragP->fr_subtype].rlx_length;
 }
 
-/*
- *			md_convert_frag();
- *
- * Called after relax() is finished.
- * In:	Address of frag.
- *	fr_type == rs_machine_dependent.
- *	fr_subtype is what the address relaxed to.
- *
- * Out:	Any fixSs and constants are set up.
- *	Caller will turn frag into a ".space 0".
- */
-#ifdef BFD_ASSEMBLER
-void
-md_convert_frag (headers, seg, fragP)
-     bfd *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#else
+/* Called after relax() is finished.
+   In:	Address of frag.
+  	fr_type == rs_machine_dependent.
+  	fr_subtype is what the address relaxed to.
+
+   Out:	Any fixSs and constants are set up.
+  	Caller will turn frag into a ".space 0".  */
 void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#endif
+md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
+		 segT seg ATTRIBUTE_UNUSED,
+		 fragS *fragP)
 {
   char *addressP;		/* -> _var to change.  */
   char *opcodeP;		/* -> opcode char(s) to change.  */
@@ -1409,7 +531,6 @@ md_convert_frag (headers, seg, fragP)
 
   switch (fragP->fr_subtype)
     {
-
     case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE):
       know (*addressP == 0 || *addressP == 0x10);	/* '@' bit.  */
       addressP[0] |= 0xAF;	/* Byte displacement. */
@@ -1530,7 +651,7 @@ md_convert_frag (headers, seg, fragP)
       break;
     }
   fragP->fr_fix += extension;
-}				/* md_convert_frag() */
+}
 
 /* Translate internal format of relocation info into target format.
 
@@ -1540,133 +661,87 @@ md_convert_frag (headers, seg, fragP)
    bit 0 as pcrel.  */
 #ifdef comment
 void
-md_ri_to_chars (the_bytes, ri)
-     char *the_bytes;
-     struct reloc_info_generic ri;
+md_ri_to_chars (char *the_bytes, struct reloc_info_generic ri)
 {
-  /* this is easy */
+  /* This is easy.  */
   md_number_to_chars (the_bytes, ri.r_address, sizeof (ri.r_address));
-  /* now the fun stuff */
+  /* Now the fun stuff.  */
   the_bytes[6] = (ri.r_symbolnum >> 16) & 0x0ff;
   the_bytes[5] = (ri.r_symbolnum >> 8) & 0x0ff;
   the_bytes[4] = ri.r_symbolnum & 0x0ff;
-  the_bytes[7] = (((ri.r_extern << 3) & 0x08) | ((ri.r_length << 1) & 0x06) |
-		  ((ri.r_pcrel << 0) & 0x01)) & 0x0F;
+  the_bytes[7] = (((ri.r_extern << 3) & 0x08) | ((ri.r_length << 1) & 0x06)
+		  | ((ri.r_pcrel << 0) & 0x01)) & 0x0F;
 }
 
 #endif /* comment */
 
-#ifdef OBJ_AOUT
-#ifndef BFD_ASSEMBLER
-void
-tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
-{
-  /*
-   * In: length of relocation (or of address) in chars: 1, 2 or 4.
-   * Out: GNU LD relocation length code: 0, 1, or 2.
-   */
-
-  static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
-  long r_symbolnum;
-
-  know (fixP->fx_addsy != NULL);
-
-  md_number_to_chars (where,
-       fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
-		      4);
-
-  r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
-		 ? S_GET_TYPE (fixP->fx_addsy)
-		 : fixP->fx_addsy->sy_number);
-
-  where[6] = (r_symbolnum >> 16) & 0x0ff;
-  where[5] = (r_symbolnum >> 8) & 0x0ff;
-  where[4] = r_symbolnum & 0x0ff;
-  where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
-	      | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
-	      | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
-}
-#endif /* !BFD_ASSEMBLER */
-#endif /* OBJ_AOUT */
-
-/*
- *       BUGS, GRIPES,  APOLOGIA, etc.
- *
- * The opcode table 'votstrs' needs to be sorted on opcode frequency.
- * That is, AFTER we hash it with hash_...(), we want most-used opcodes
- * to come out of the hash table faster.
- *
- * I am sorry to inflict yet another VAX assembler on the world, but
- * RMS says we must do everything from scratch, to prevent pin-heads
- * restricting this software.
- */
-
-/*
- * This is a vaguely modular set of routines in C to parse VAX
- * assembly code using DEC mnemonics. It is NOT un*x specific.
- *
- * The idea here is that the assembler has taken care of all:
- *   labels
- *   macros
- *   listing
- *   pseudo-ops
- *   line continuation
- *   comments
- *   condensing any whitespace down to exactly one space
- * and all we have to do is parse 1 line into a vax instruction
- * partially formed. We will accept a line, and deliver:
- *   an error message (hopefully empty)
- *   a skeleton VAX instruction (tree structure)
- *   textual pointers to all the operand expressions
- *   a warning message that notes a silly operand (hopefully empty)
- */
-
-/*
- *		E D I T   H I S T O R Y
- *
- * 17may86 Dean Elsner. Bug if line ends immediately after opcode.
- * 30apr86 Dean Elsner. New vip_op() uses arg block so change call.
- *  6jan86 Dean Elsner. Crock vip_begin() to call vip_op_defaults().
- *  2jan86 Dean Elsner. Invent synthetic opcodes.
- *	Widen vax_opcodeT to 32 bits. Use a bit for VIT_OPCODE_SYNTHETIC,
- *	which means this is not a real opcode, it is like a macro; it will
- *	be relax()ed into 1 or more instructions.
- *	Use another bit for VIT_OPCODE_SPECIAL if the op-code is not optimised
- *	like a regular branch instruction. Option added to vip_begin():
- *	exclude	synthetic opcodes. Invent synthetic_votstrs[].
- * 31dec85 Dean Elsner. Invent vit_opcode_nbytes.
- *	Also make vit_opcode into a char[]. We now have n-byte vax opcodes,
- *	so caller's don't have to know the difference between a 1-byte & a
- *	2-byte op-code. Still need vax_opcodeT concept, so we know how
- *	big an object must be to hold an op.code.
- * 30dec85 Dean Elsner. Widen typedef vax_opcodeT in "vax-inst.h"
- *	because vax opcodes may be 16 bits. Our crufty C compiler was
- *	happily initialising 8-bit vot_codes with 16-bit numbers!
- *	(Wouldn't the 'phone company like to compress data so easily!)
- * 29dec85 Dean Elsner. New static table vax_operand_width_size[].
- *	Invented so we know hw many bytes a "I^#42" needs in its immediate
- *	operand. Revised struct vop in "vax-inst.h": explicitly include
- *	byte length of each operand, and it's letter-code datum type.
- * 17nov85 Dean Elsner. Name Change.
- *	Due to ar(1) truncating names, we learned the hard way that
- *	"vax-inst-parse.c" -> "vax-inst-parse." dropping the "o" off
- *	the archived object name. SO... we shortened the name of this
- *	source file, and changed the makefile.
- */
-
-/* handle of the OPCODE hash table */
+/*       BUGS, GRIPES,  APOLOGIA, etc.
+
+   The opcode table 'votstrs' needs to be sorted on opcode frequency.
+   That is, AFTER we hash it with hash_...(), we want most-used opcodes
+   to come out of the hash table faster.
+
+   I am sorry to inflict yet another VAX assembler on the world, but
+   RMS says we must do everything from scratch, to prevent pin-heads
+   restricting this software.
+
+   This is a vaguely modular set of routines in C to parse VAX
+   assembly code using DEC mnemonics. It is NOT un*x specific.
+
+   The idea here is that the assembler has taken care of all:
+     labels
+     macros
+     listing
+     pseudo-ops
+     line continuation
+     comments
+     condensing any whitespace down to exactly one space
+   and all we have to do is parse 1 line into a vax instruction
+   partially formed. We will accept a line, and deliver:
+     an error message (hopefully empty)
+     a skeleton VAX instruction (tree structure)
+     textual pointers to all the operand expressions
+     a warning message that notes a silly operand (hopefully empty)
+
+  		E D I T   H I S T O R Y
+
+   17may86 Dean Elsner. Bug if line ends immediately after opcode.
+   30apr86 Dean Elsner. New vip_op() uses arg block so change call.
+    6jan86 Dean Elsner. Crock vip_begin() to call vip_op_defaults().
+    2jan86 Dean Elsner. Invent synthetic opcodes.
+  	Widen vax_opcodeT to 32 bits. Use a bit for VIT_OPCODE_SYNTHETIC,
+  	which means this is not a real opcode, it is like a macro; it will
+  	be relax()ed into 1 or more instructions.
+  	Use another bit for VIT_OPCODE_SPECIAL if the op-code is not optimised
+  	like a regular branch instruction. Option added to vip_begin():
+  	exclude	synthetic opcodes. Invent synthetic_votstrs[].
+   31dec85 Dean Elsner. Invent vit_opcode_nbytes.
+  	Also make vit_opcode into a char[]. We now have n-byte vax opcodes,
+  	so caller's don't have to know the difference between a 1-byte & a
+  	2-byte op-code. Still need vax_opcodeT concept, so we know how
+  	big an object must be to hold an op.code.
+   30dec85 Dean Elsner. Widen typedef vax_opcodeT in "vax-inst.h"
+  	because vax opcodes may be 16 bits. Our crufty C compiler was
+  	happily initialising 8-bit vot_codes with 16-bit numbers!
+  	(Wouldn't the 'phone company like to compress data so easily!)
+   29dec85 Dean Elsner. New static table vax_operand_width_size[].
+  	Invented so we know hw many bytes a "I^#42" needs in its immediate
+  	operand. Revised struct vop in "vax-inst.h": explicitly include
+  	byte length of each operand, and it's letter-code datum type.
+   17nov85 Dean Elsner. Name Change.
+  	Due to ar(1) truncating names, we learned the hard way that
+  	"vax-inst-parse.c" -> "vax-inst-parse." dropping the "o" off
+  	the archived object name. SO... we shortened the name of this
+  	source file, and changed the makefile.  */
+
+/* Handle of the OPCODE hash table.  */
 static struct hash_control *op_hash;
 
-/*
- * In:	1 character, from "bdfghloqpw" being the data-type of an operand
- *	of a vax instruction.
- *
- * Out:	the length of an operand of that type, in bytes.
- *	Special branch operands types "-?!" have length 0.
- */
+/* In:	1 character, from "bdfghloqpw" being the data-type of an operand
+  	of a vax instruction.
+
+   Out:	the length of an operand of that type, in bytes.
+  	Special branch operands types "-?!" have length 0.  */
 
 static const short int vax_operand_width_size[256] =
 {
@@ -1688,61 +763,54 @@ static const short int vax_operand_width_size[256] =
   0, 0, 0, 0, 0, 0, 0, 0,  0, 0, 0, 0, 0, 0, 0, 0,
 };
 
-/*
- * This perversion encodes all the vax opcodes as a bunch of strings.
- * RMS says we should build our hash-table at run-time. Hmm.
- * Please would someone arrange these in decreasing frequency of opcode?
- * Because of the way hash_...() works, the most frequently used opcode
- * should be textually first and so on.
- *
- * Input for this table was 'vax.opcodes', awk(1)ed by 'vax.opcodes.c.awk' .
- * So change 'vax.opcodes', then re-generate this table.
- */
+/* This perversion encodes all the vax opcodes as a bunch of strings.
+   RMS says we should build our hash-table at run-time. Hmm.
+   Please would someone arrange these in decreasing frequency of opcode?
+   Because of the way hash_...() works, the most frequently used opcode
+   should be textually first and so on.
+
+   Input for this table was 'vax.opcodes', awk(1)ed by 'vax.opcodes.c.awk' .
+   So change 'vax.opcodes', then re-generate this table.  */
 
 #include "opcode/vax.h"
 
-/*
- * This is a table of optional op-codes. All of them represent
- * 'synthetic' instructions that seem popular.
- *
- * Here we make some pseudo op-codes. Every code has a bit set to say
- * it is synthetic. This lets you catch them if you want to
- * ban these opcodes. They are mnemonics for "elastic" instructions
- * that are supposed to assemble into the fewest bytes needed to do a
- * branch, or to do a conditional branch, or whatever.
- *
- * The opcode is in the usual place [low-order n*8 bits]. This means
- * that if you mask off the bucky bits, the usual rules apply about
- * how long the opcode is.
- *
- * All VAX branch displacements come at the end of the instruction.
- * For simple branches (1-byte opcode + 1-byte displacement) the last
- * operand is coded 'b?' where the "data type" '?' is a clue that we
- * may reverse the sense of the branch (complement lowest order bit)
- * and branch around a jump. This is by far the most common case.
- * That is why the VIT_OPCODE_SYNTHETIC bit is set: it says this is
- * a 0-byte op-code followed by 2 or more bytes of operand address.
- *
- * If the op-code has VIT_OPCODE_SPECIAL set, then we have a more unusual
- * case.
- *
- * For JBSB & JBR the treatment is the similar, except (1) we have a 'bw'
- * option before (2) we can directly JSB/JMP because there is no condition.
- * These operands have 'b-' as their access/data type.
- *
- * That leaves a bunch of random opcodes: JACBx, JxOBxxx. In these
- * cases, we do the same idea. JACBxxx are all marked with a 'b!'
- * JAOBxxx & JSOBxxx are marked with a 'b:'.
- *
- */
+/* This is a table of optional op-codes. All of them represent
+   'synthetic' instructions that seem popular.
+
+   Here we make some pseudo op-codes. Every code has a bit set to say
+   it is synthetic. This lets you catch them if you want to
+   ban these opcodes. They are mnemonics for "elastic" instructions
+   that are supposed to assemble into the fewest bytes needed to do a
+   branch, or to do a conditional branch, or whatever.
+  
+   The opcode is in the usual place [low-order n*8 bits]. This means
+   that if you mask off the bucky bits, the usual rules apply about
+   how long the opcode is.
+  
+   All VAX branch displacements come at the end of the instruction.
+   For simple branches (1-byte opcode + 1-byte displacement) the last
+   operand is coded 'b?' where the "data type" '?' is a clue that we
+   may reverse the sense of the branch (complement lowest order bit)
+   and branch around a jump. This is by far the most common case.
+   That is why the VIT_OPCODE_SYNTHETIC bit is set: it says this is
+   a 0-byte op-code followed by 2 or more bytes of operand address.
+  
+   If the op-code has VIT_OPCODE_SPECIAL set, then we have a more unusual
+   case.
+  
+   For JBSB & JBR the treatment is the similar, except (1) we have a 'bw'
+   option before (2) we can directly JSB/JMP because there is no condition.
+   These operands have 'b-' as their access/data type.
+  
+   That leaves a bunch of random opcodes: JACBx, JxOBxxx. In these
+   cases, we do the same idea. JACBxxx are all marked with a 'b!'
+   JAOBxxx & JSOBxxx are marked with a 'b:'.  */
 #if (VIT_OPCODE_SYNTHETIC != 0x80000000)
-You have just broken the encoding below, which assumes the sign bit
-  means 'I am an imaginary instruction'.
+#error "You have just broken the encoding below, which assumes the sign bit means 'I am an imaginary instruction'."
 #endif
 
 #if (VIT_OPCODE_SPECIAL != 0x40000000)
-  You have just broken the encoding below, which assumes the 0x40 M bit means
-  'I am not to be "optimised" the way normal branches are'.
+#error "You have just broken the encoding below, which assumes the 0x40 M bit means 'I am not to be "optimised" the way normal branches are'."
 #endif
 
 static const struct vot
@@ -1795,25 +863,95 @@ static const struct vot
 /* CASEx has no branch addresses in our conception of it.  */
 /* You should use ".word ..." statements after the "case ...".  */
 
-  {"",	{"", 0}}			/* empty is end sentinel */
-
-};				/* synthetic_votstrs */
+  {"",		{"", 0}}	/* Empty is end sentinel.  */
+};
 
-/*
- *                  v i p _ b e g i n ( )
- *
- * Call me once before you decode any lines.
- * I decode votstrs into a hash table at op_hash (which I create).
- * I return an error text or null.
- * If you want, I will include the 'synthetic' jXXX instructions in the
- * instruction table.
- * You must nominate metacharacters for eg DEC's "#", "@", "^".
- */
+/* Because this module is useful for both VMS and UN*X style assemblers
+   and because of the variety of UN*X assemblers we must recognise
+   the different conventions for assembler operand notation. For example
+   VMS says "#42" for immediate mode, while most UN*X say "$42".
+   We permit arbitrary sets of (single) characters to represent the
+   3 concepts that DEC writes '#', '@', '^'.  */
+
+/* Character tests.  */
+#define VIP_IMMEDIATE 01	/* Character is like DEC # */
+#define VIP_INDIRECT  02	/* Char is like DEC @ */
+#define VIP_DISPLEN   04	/* Char is like DEC ^ */
+
+#define IMMEDIATEP(c)	(vip_metacharacters [(c) & 0xff] & VIP_IMMEDIATE)
+#define INDIRECTP(c)	(vip_metacharacters [(c) & 0xff] & VIP_INDIRECT)
+#define DISPLENP(c)	(vip_metacharacters [(c) & 0xff] & VIP_DISPLEN)
+
+/* We assume 8 bits per byte. Use vip_op_defaults() to set these up BEFORE we
+   are ever called.  */
+
+#if defined(CONST_TABLE)
+#define _ 0,
+#define I VIP_IMMEDIATE,
+#define S VIP_INDIRECT,
+#define D VIP_DISPLEN,
+static const char
+vip_metacharacters[256] =
+{
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/* ^@ ^A ^B ^C ^D ^E ^F ^G ^H ^I ^J ^K ^L ^M ^N ^O*/
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/* ^P ^Q ^R ^S ^T ^U ^V ^W ^X ^Y ^Z ^[ ^\ ^] ^^ ^_ */
+  _ _ _ _ I _ _ _ _ _ S _ _ _ _ _	/* sp !  "  #  $  %  & '  (  )  *  +  ,  -  .  / */
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*0  1  2  3  4  5  6  7  8  9  :  ;  <  =  >  ?*/
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*@  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O*/
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _*/
+  D _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*`  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o*/
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~  ^?*/
+
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
+};
+#undef _
+#undef I
+#undef S
+#undef D
+
+#else
+
+static char vip_metacharacters[256];
+
+static void
+vip_op_1 (int bit, const char *syms)
+{
+  unsigned char t;
+
+  while ((t = *syms++) != 0)
+    vip_metacharacters[t] |= bit;
+}
+
+/* Can be called any time.  More arguments may appear in future.  */
+static void
+vip_op_defaults (const char *immediate, const char *indirect, const char *displen)
+{
+  vip_op_1 (VIP_IMMEDIATE, immediate);
+  vip_op_1 (VIP_INDIRECT, indirect);
+  vip_op_1 (VIP_DISPLEN, displen);
+}
+
+#endif
+
+/* Call me once before you decode any lines.
+   I decode votstrs into a hash table at op_hash (which I create).
+   I return an error text or null.
+   If you want, I will include the 'synthetic' jXXX instructions in the
+   instruction table.
+   You must nominate metacharacters for eg DEC's "#", "@", "^".  */
 
 static const char *
-vip_begin (synthetic_too, immediate, indirect, displen)
-     int synthetic_too;		/* 1 means include jXXX op-codes.  */
-     const char *immediate, *indirect, *displen;
+vip_begin (int synthetic_too,		/* 1 means include jXXX op-codes.  */
+	   const char *immediate,
+	   const char *indirect,
+	   const char *displen)
 {
   const struct vot *vP;		/* scan votstrs */
   const char *retval = 0;	/* error text */
@@ -1834,303 +972,65 @@ vip_begin (synthetic_too, immediate, indirect, displen)
   return retval;
 }
 
-/*
- *                  v i p ( )
- *
- * This converts a string into a vax instruction.
- * The string must be a bare single instruction in dec-vax (with BSD4 frobs)
- * format.
- * It provides some error messages: at most one fatal error message (which
- * stops the scan) and at most one warning message for each operand.
- * The vax instruction is returned in exploded form, since we have no
- * knowledge of how you parse (or evaluate) your expressions.
- * We do however strip off and decode addressing modes and operation
- * mnemonic.
- *
- * The exploded instruction is returned to a struct vit of your choice.
- * #include "vax-inst.h" to know what a struct vit is.
- *
- * This function's value is a string. If it is not "" then an internal
- * logic error was found: read this code to assign meaning to the string.
- * No argument string should generate such an error string:
- * it means a bug in our code, not in the user's text.
- *
- * You MUST have called vip_begin() once before using this function.
- */
-
-static void
-vip (vitP, instring)
-     struct vit *vitP;		/* We build an exploded instruction here.  */
-     char *instring;		/* Text of a vax instruction: we modify.  */
-{
-  /* How to bit-encode this opcode.  */
-  struct vot_wot *vwP;
-  /* 1/skip whitespace.2/scan vot_how */
-  char *p;
-  char *q;
-  /* counts number of operands seen */
-  unsigned char count;
-  /* scan operands in struct vit */
-  struct vop *operandp;
-  /* error over all operands */
-  const char *alloperr;
-  /* Remember char, (we clobber it with '\0' temporarily).  */
-  char c;
-  /* Op-code of this instruction.  */
-  vax_opcodeT oc;
-
-  if (*instring == ' ')
-    ++instring;			/* Skip leading whitespace.  */
-  for (p = instring; *p && *p != ' '; p++);;	/* MUST end in end-of-string or exactly 1 space.  */
-  /* Scanned up to end of operation-code.  */
-  /* Operation-code is ended with whitespace.  */
-  if (p - instring == 0)
-    {
-      vitP->vit_error = _("No operator");
-      count = 0;
-      memset (vitP->vit_opcode, '\0', sizeof (vitP->vit_opcode));
-    }
-  else
-    {
-      c = *p;
-      *p = '\0';
-      /*
-       * Here with instring pointing to what better be an op-name, and p
-       * pointing to character just past that.
-       * We trust instring points to an op-name, with no whitespace.
-       */
-      vwP = (struct vot_wot *) hash_find (op_hash, instring);
-      *p = c;			/* Restore char after op-code.  */
-      if (vwP == 0)
-	{
-	  vitP->vit_error = _("Unknown operator");
-	  count = 0;
-	  memset (vitP->vit_opcode, '\0', sizeof (vitP->vit_opcode));
-	}
-      else
-	{
-	  /*
-	   * We found a match! So let's pick up as many operands as the
-	   * instruction wants, and even gripe if there are too many.
-	   * We expect comma to separate each operand.
-	   * We let instring track the text, while p tracks a part of the
-	   * struct vot.
-	   */
-	  const char *howp;
-	  /*
-	   * The lines below know about 2-byte opcodes starting FD,FE or FF.
-	   * They also understand synthetic opcodes. Note:
-	   * we return 32 bits of opcode, including bucky bits, BUT
-	   * an opcode length is either 8 or 16 bits for vit_opcode_nbytes.
-	   */
-	  oc = vwP->vot_code;	/* The op-code.  */
-	  vitP->vit_opcode_nbytes = (oc & 0xFF) >= 0xFD ? 2 : 1;
-	  md_number_to_chars (vitP->vit_opcode, oc, 4);
-	  count = 0;		/* no operands seen yet */
-	  instring = p;		/* point just past operation code */
-	  alloperr = "";
-	  for (howp = vwP->vot_how, operandp = vitP->vit_operand;
-	       !(alloperr && *alloperr) && *howp;
-	       operandp++, howp += 2)
-	    {
-	      /*
-	       * Here to parse one operand. Leave instring pointing just
-	       * past any one ',' that marks the end of this operand.
-	       */
-	      if (!howp[1])
-		as_fatal (_("odd number of bytes in operand description"));
-	      else if (*instring)
-		{
-		  for (q = instring; (c = *q) && c != ','; q++)
-		    ;
-		  /*
-		   * Q points to ',' or '\0' that ends argument. C is that
-		   * character.
-		   */
-		  *q = 0;
-		  operandp->vop_width = howp[1];
-		  operandp->vop_nbytes = vax_operand_width_size[(unsigned) howp[1]];
-		  operandp->vop_access = howp[0];
-		  vip_op (instring, operandp);
-		  *q = c;	/* Restore input text.  */
-		  if (operandp->vop_error)
-		    alloperr = _("Bad operand");
-		  instring = q + (c ? 1 : 0);	/* next operand (if any) */
-		  count++;	/*  won another argument, may have an operr */
-		}
-	      else
-		alloperr = _("Not enough operands");
-	    }
-	  if (!*alloperr)
-	    {
-	      if (*instring == ' ')
-		instring++;	/* Skip whitespace.  */
-	      if (*instring)
-		alloperr = _("Too many operands");
-	    }
-	  vitP->vit_error = alloperr;
-	}
-    }
-  vitP->vit_operands = count;
-}
-
-#ifdef test
-
-/*
- * Test program for above.
- */
-
-struct vit myvit;		/* build an exploded vax instruction here */
-char answer[100];		/* human types a line of vax assembler here */
-char *mybug;			/* "" or an internal logic diagnostic */
-int mycount;			/* number of operands */
-struct vop *myvop;		/* scan operands from myvit */
-int mysynth;			/* 1 means want synthetic opcodes.  */
-char my_immediate[200];
-char my_indirect[200];
-char my_displen[200];
-
-main ()
-{
-  char *p;
-
-  printf ("0 means no synthetic instructions.   ");
-  printf ("Value for vip_begin?  ");
-  gets (answer);
-  sscanf (answer, "%d", &mysynth);
-  printf ("Synthetic opcodes %s be included.\n", mysynth ? "will" : "will not");
-  printf ("enter immediate symbols eg enter #   ");
-  gets (my_immediate);
-  printf ("enter indirect symbols  eg enter @   ");
-  gets (my_indirect);
-  printf ("enter displen symbols   eg enter ^   ");
-  gets (my_displen);
-  if (p = vip_begin (mysynth, my_immediate, my_indirect, my_displen))
-    {
-      error ("vip_begin=%s", p);
-    }
-  printf ("An empty input line will quit you from the vax instruction parser\n");
-  for (;;)
-    {
-      printf ("vax instruction: ");
-      fflush (stdout);
-      gets (answer);
-      if (!*answer)
-	{
-	  break;		/* out of for each input text loop */
-	}
-      vip (&myvit, answer);
-      if (*myvit.vit_error)
-	{
-	  printf ("ERR:\"%s\"\n", myvit.vit_error);
-	}
-      printf ("opcode=");
-      for (mycount = myvit.vit_opcode_nbytes, p = myvit.vit_opcode;
-	   mycount;
-	   mycount--, p++
-	)
-	{
-	  printf ("%02x ", *p & 0xFF);
-	}
-      printf ("   operand count=%d.\n", mycount = myvit.vit_operands);
-      for (myvop = myvit.vit_operand; mycount; mycount--, myvop++)
-	{
-	  printf ("mode=%xx reg=%xx ndx=%xx len='%c'=%c%c%d. expr=\"",
-		  myvop->vop_mode, myvop->vop_reg, myvop->vop_ndx,
-		  myvop->vop_short, myvop->vop_access, myvop->vop_width,
-		  myvop->vop_nbytes);
-	  for (p = myvop->vop_expr_begin; p <= myvop->vop_expr_end; p++)
-	    {
-	      putchar (*p);
-	    }
-	  printf ("\"\n");
-	  if (myvop->vop_error)
-	    {
-	      printf ("  err:\"%s\"\n", myvop->vop_error);
-	    }
-	  if (myvop->vop_warn)
-	    {
-	      printf ("  wrn:\"%s\"\n", myvop->vop_warn);
-	    }
-	}
-    }
-  vip_end ();
-  exit (EXIT_SUCCESS);
-}
-
-#endif /* #ifdef test */
-
-/* end of vax_ins_parse.c */
-
-/* vax_reg_parse.c - convert a VAX register name to a number */
-
-/* Copyright (C) 1987 Free Software Foundation, Inc. A part of GNU.  */
-
-/*
- *          v a x _ r e g _ p a r s e ( )
- *
- * Take 3 char.s, the last of which may be `\0` (non-existent)
- * and return the VAX register number that they represent.
- *
- * Return -1 if they don't form a register name. Good names return
- * a number from 0:15 inclusive.
- *
- * Case is not important in a name.
- *
- * Register names understood are:
- *
- *	R0
- *	R1
- *	R2
- *	R3
- *	R4
- *	R5
- *	R6
- * 	R7
- *	R8
- *	R9
- *	R10
- *	R11
- *	R12	AP
- *	R13	FP
- *	R14	SP
- *	R15	PC
- *
- */
-
-#include "safe-ctype.h"
-#define AP (12)
-#define FP (13)
-#define SP (14)
-#define PC (15)
-
-int				/* return -1 or 0:15 */
-vax_reg_parse (c1, c2, c3, c4)	/* 3 chars of register name */
-     char c1, c2, c3, c4;	/* c3 == 0 if 2-character reg name */
+/* Take 3 char.s, the last of which may be `\0` (non-existent)
+   and return the VAX register number that they represent.
+  
+   Return -1 if they don't form a register name. Good names return
+   a number from 0:15 inclusive.
+  
+   Case is not important in a name.
+  
+   Register names understood are:
+  
+  	R0
+  	R1
+  	R2
+  	R3
+  	R4
+  	R5
+  	R6
+   	R7
+  	R8
+  	R9
+  	R10
+  	R11
+  	R12	AP
+  	R13	FP
+  	R14	SP
+  	R15	PC  */
+
+#define AP 12
+#define FP 13
+#define SP 14
+#define PC 15
+
+/* Returns the register number of something like '%r15' or 'ap', supplied
+   in four single chars. Returns -1 if the register isn't recognized,
+   0..15 otherwise.  */
+static int
+vax_reg_parse (char c1, char c2, char c3, char c4)
 {
-  int retval;		/* return -1:15 */
-
-  retval = -1;
+  int retval = -1;
 
 #ifdef OBJ_ELF
-  if (c1 != '%')	/* register prefixes are mandatory for ELF */
+  if (c1 != '%')	/* Register prefixes are mandatory for ELF.  */
     return retval;
   c1 = c2;
   c2 = c3;
   c3 = c4;
 #endif
 #ifdef OBJ_VMS
-  if (c4 != 0)		/* register prefixes are not allowed under VMS */
+  if (c4 != 0)		/* Register prefixes are not allowed under VMS.  */
     return retval;
 #endif
 #ifdef OBJ_AOUT
-  if (c1 == '%')	/* register prefixes are optional under a.out */
+  if (c1 == '%')	/* Register prefixes are optional under a.out.  */
     {
       c1 = c2;
       c2 = c3;
       c3 = c4;
     }
-  else if (c3 && c4)	/* can't be 4 characters long.  */
+  else if (c3 && c4)	/* Can't be 4 characters long.  */
     return retval;
 #endif
 
@@ -2146,9 +1046,9 @@ vax_reg_parse (c1, c2, c3, c4)	/* 3 chars of register name */
 	  /* clamp the register value to 1 hex digit */
 	}
       else if (c3)
-	retval = -1;		/* c3 must be '\0' or a digit */
+	retval = -1;		/* c3 must be '\0' or a digit.  */
     }
-  else if (c3)			/* There are no three letter regs */
+  else if (c3)			/* There are no three letter regs.  */
     retval = -1;
   else if (c2 == 'p')
     {
@@ -2171,290 +1071,206 @@ vax_reg_parse (c1, c2, c3, c4)	/* 3 chars of register name */
     retval = PC;
   else
     retval = -1;
-  return (retval);
+  return retval;
 }
 
-/*
- *               v i p _ o p ( )
- *
- * Parse a vax operand in DEC assembler notation.
- * For speed, expect a string of whitespace to be reduced to a single ' '.
- * This is the case for GNU AS, and is easy for other DEC-compatible
- * assemblers.
- *
- * Knowledge about DEC VAX assembler operand notation lives here.
- * This doesn't even know what a register name is, except it believes
- * all register names are 2 or 3 characters, and lets vax_reg_parse() say
- * what number each name represents.
- * It does, however, know that PC, SP etc are special registers so it can
- * detect addressing modes that are silly for those registers.
- *
- * Where possible, it delivers 1 fatal or 1 warning message if the operand
- * is suspect. Exactly what we test for is still evolving.
- */
-
-/*
- *		   	B u g s
- *
- *	Arg block.
- *
- * There were a number of 'mismatched argument type' bugs to vip_op.
- * The most general solution is to typedef each (of many) arguments.
- * We used instead a typedef'd argument block. This is less modular
- * than using separate return pointers for each result, but runs faster
- * on most engines, and seems to keep programmers happy. It will have
- * to be done properly if we ever want to use vip_op as a general-purpose
- * module (it was designed to be).
- *
- *	G^
- *
- * Doesn't support DEC "G^" format operands. These always take 5 bytes
- * to express, and code as modes 8F or 9F. Reason: "G^" deprives you of
- * optimising to (say) a "B^" if you are lucky in the way you link.
- * When someone builds a linker smart enough to convert "G^" to "B^", "W^"
- * whenever possible, then we should implement it.
- * If there is some other use for "G^", feel free to code it in!
- *
- *
- *	speed
- *
- * If I nested if()s more, I could avoid testing (*err) which would save
- * time, space and page faults. I didn't nest all those if()s for clarity
- * and because I think the mode testing can be re-arranged 1st to test the
- * commoner constructs 1st. Does anybody have statistics on this?
- *
- *
- *
- *	error messages
- *
- * In future, we should be able to 'compose' error messages in a scratch area
- * and give the user MUCH more informative error messages. Although this takes
- * a little more code at run-time, it will make this module much more self-
- * documenting. As an example of what sucks now: most error messages have
- * hardwired into them the DEC VAX metacharacters "#^@" which are nothing like
- * the Un*x characters "$`*", that most users will expect from this AS.
- */
-
-/*
- * The input is a string, ending with '\0'.
- *
- * We also require a 'hint' of what kind of operand is expected: so
- * we can remind caller not to write into literals for instance.
- *
- * The output is a skeletal instruction.
- *
- * The algorithm has two parts.
- * 1. extract the syntactic features (parse off all the @^#-()+[] mode crud);
- * 2. express the @^#-()+[] as some parameters suited to further analysis.
- *
- * 2nd step is where we detect the googles of possible invalid combinations
- * a human (or compiler) might write. Note that if we do a half-way
- * decent assembler, we don't know how long to make (eg) displacement
- * fields when we first meet them (because they may not have defined values).
- * So we must wait until we know how many bits are needed for each address,
- * then we can know both length and opcodes of instructions.
- * For reason(s) above, we will pass to our caller a 'broken' instruction
- * of these major components, from which our caller can generate instructions:
- *  -  displacement length      I^ S^ L^ B^ W^ unspecified
- *  -  mode                     (many)
- *  -  register                 R0-R15 or absent
- *  -  index register           R0-R15 or absent
- *  -  expression text          what we don't parse
- *  -  error text(s)            why we couldn't understand the operand
- */
-
-/*
- * To decode output of this, test errtxt. If errtxt[0] == '\0', then
- * we had no errors that prevented parsing. Also, if we ever report
- * an internal bug, errtxt[0] is set non-zero. So one test tells you
- * if the other outputs are to be taken seriously.
- */
-
-/*
- * Because this module is useful for both VMS and UN*X style assemblers
- * and because of the variety of UN*X assemblers we must recognise
- * the different conventions for assembler operand notation. For example
- * VMS says "#42" for immediate mode, while most UN*X say "$42".
- * We permit arbitrary sets of (single) characters to represent the
- * 3 concepts that DEC writes '#', '@', '^'.
- */
-
-/* character tests */
-#define VIP_IMMEDIATE 01	/* Character is like DEC # */
-#define VIP_INDIRECT  02	/* Char is like DEC @ */
-#define VIP_DISPLEN   04	/* Char is like DEC ^ */
-
-#define IMMEDIATEP(c)	(vip_metacharacters [(c)&0xff]&VIP_IMMEDIATE)
-#define INDIRECTP(c)	(vip_metacharacters [(c)&0xff]&VIP_INDIRECT)
-#define DISPLENP(c)	(vip_metacharacters [(c)&0xff]&VIP_DISPLEN)
-
-/* We assume 8 bits per byte. Use vip_op_defaults() to set these up BEFORE we
- * are ever called.
- */
+/* Parse a vax operand in DEC assembler notation.
+   For speed, expect a string of whitespace to be reduced to a single ' '.
+   This is the case for GNU AS, and is easy for other DEC-compatible
+   assemblers.
+  
+   Knowledge about DEC VAX assembler operand notation lives here.
+   This doesn't even know what a register name is, except it believes
+   all register names are 2 or 3 characters, and lets vax_reg_parse() say
+   what number each name represents.
+   It does, however, know that PC, SP etc are special registers so it can
+   detect addressing modes that are silly for those registers.
+  
+   Where possible, it delivers 1 fatal or 1 warning message if the operand
+   is suspect. Exactly what we test for is still evolving.
+
+   ---
+  	Arg block.
+  
+   There were a number of 'mismatched argument type' bugs to vip_op.
+   The most general solution is to typedef each (of many) arguments.
+   We used instead a typedef'd argument block. This is less modular
+   than using separate return pointers for each result, but runs faster
+   on most engines, and seems to keep programmers happy. It will have
+   to be done properly if we ever want to use vip_op as a general-purpose
+   module (it was designed to be).
+  
+ 	G^
+
+   Doesn't support DEC "G^" format operands. These always take 5 bytes
+   to express, and code as modes 8F or 9F. Reason: "G^" deprives you of
+   optimising to (say) a "B^" if you are lucky in the way you link.
+   When someone builds a linker smart enough to convert "G^" to "B^", "W^"
+   whenever possible, then we should implement it.
+   If there is some other use for "G^", feel free to code it in!
+
+  	speed
+  
+   If I nested if()s more, I could avoid testing (*err) which would save
+   time, space and page faults. I didn't nest all those if()s for clarity
+   and because I think the mode testing can be re-arranged 1st to test the
+   commoner constructs 1st. Does anybody have statistics on this?  
+  
+  	error messages
+  
+   In future, we should be able to 'compose' error messages in a scratch area
+   and give the user MUCH more informative error messages. Although this takes
+   a little more code at run-time, it will make this module much more self-
+   documenting. As an example of what sucks now: most error messages have
+   hardwired into them the DEC VAX metacharacters "#^@" which are nothing like
+   the Un*x characters "$`*", that most users will expect from this AS.
+
+   ----
+   
+   The input is a string, ending with '\0'.
+  
+   We also require a 'hint' of what kind of operand is expected: so
+   we can remind caller not to write into literals for instance.
+  
+   The output is a skeletal instruction.
+  
+   The algorithm has two parts.
+   1. extract the syntactic features (parse off all the @^#-()+[] mode crud);
+   2. express the @^#-()+[] as some parameters suited to further analysis.
+  
+   2nd step is where we detect the googles of possible invalid combinations
+   a human (or compiler) might write. Note that if we do a half-way
+   decent assembler, we don't know how long to make (eg) displacement
+   fields when we first meet them (because they may not have defined values).
+   So we must wait until we know how many bits are needed for each address,
+   then we can know both length and opcodes of instructions.
+   For reason(s) above, we will pass to our caller a 'broken' instruction
+   of these major components, from which our caller can generate instructions:
+    -  displacement length      I^ S^ L^ B^ W^ unspecified
+    -  mode                     (many)
+    -  register                 R0-R15 or absent
+    -  index register           R0-R15 or absent
+    -  expression text          what we don't parse
+    -  error text(s)            why we couldn't understand the operand
+
+   ----
+    
+   To decode output of this, test errtxt. If errtxt[0] == '\0', then
+   we had no errors that prevented parsing. Also, if we ever report
+   an internal bug, errtxt[0] is set non-zero. So one test tells you
+   if the other outputs are to be taken seriously.
+
+   ----
+   
+   Dec defines the semantics of address modes (and values)
+   by a two-letter code, explained here.
+  
+     letter 1:   access type
+  
+       a         address calculation - no data access, registers forbidden
+       b         branch displacement
+       m         read - let go of bus - write back    "modify"
+       r         read
+       v         bit field address: like 'a' but registers are OK
+       w         write
+       space	 no operator (eg ".long foo") [our convention]
+  
+     letter 2:   data type (i.e. width, alignment)
+  
+       b         byte
+       d         double precision floating point (D format)
+       f         single precision floating point (F format)
+       g         G format floating
+       h         H format floating
+       l         longword
+       o         octaword
+       q         quadword
+       w         word
+       ?	 simple synthetic branch operand
+       -	 unconditional synthetic JSB/JSR operand
+       !	 complex synthetic branch operand
+  
+   The '-?!' letter 2's are not for external consumption. They are used
+   for various assemblers. Generally, all unknown widths are assumed 0.
+   We don't limit your choice of width character.
+  
+   DEC operands are hard work to parse. For example, '@' as the first
+   character means indirect (deferred) mode but elsewhere it is a shift
+   operator.
+   The long-winded explanation of how this is supposed to work is
+   cancelled. Read a DEC vax manual.
+   We try hard not to parse anything that MIGHT be part of the expression
+   buried in that syntax. For example if we see @...(Rn) we don't check
+   for '-' before the '(' because mode @-(Rn) does not exist.
+  
+   After parsing we have:
+  
+   at                     1 if leading '@' (or Un*x '*')
+   len                    takes one value from " bilsw". eg B^ -> 'b'.
+   hash                   1 if leading '#' (or Un*x '$')
+   expr_begin, expr_end   the expression we did not parse
+                          even though we don't interpret it, we make use
+                          of its presence or absence.
+   sign                   -1: -(Rn)    0: absent    +1: (Rn)+
+   paren                  1 if () are around register
+   reg                    major register number 0:15    -1 means absent
+   ndx                    index register number 0:15    -1 means absent
+  
+   Again, I dare not explain it: just trace ALL the code!
+
+   Summary of vip_op outputs.
 
-#if defined(CONST_TABLE)
-#define _ 0,
-#define I VIP_IMMEDIATE,
-#define S VIP_INDIRECT,
-#define D VIP_DISPLEN,
-static const char
-vip_metacharacters[256] =
-{
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/* ^@ ^A ^B ^C ^D ^E ^F ^G ^H ^I ^J ^K ^L ^M ^N ^O*/
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/* ^P ^Q ^R ^S ^T ^U ^V ^W ^X ^Y ^Z ^[ ^\ ^] ^^ ^_ */
-  _ _ _ _ I _ _ _ _ _ S _ _ _ _ _	/* sp !  "  #  $  %  & '  (  )  *  +  ,  -  .  / */
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*0  1  2  3  4  5  6  7  8  9  :  ;  <  =  >  ?*/
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*@  A  B  C  D  E  F  G  H  I  J  K  L  M  N  O*/
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*P  Q  R  S  T  U  V  W  X  Y  Z  [  \  ]  ^  _*/
-  D _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*`  a  b  c  d  e  f  g  h  i  j  k  l  m  n  o*/
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _	/*p  q  r  s  t  u  v  w  x  y  z  {  |  }  ~  ^?*/
-
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-  _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-};
-#undef _
-#undef I
-#undef S
-#undef D
-#else
-static char vip_metacharacters[256];
-
-static void
-vip_op_1 (bit, syms)
-     int bit;
-     const char *syms;
-{
-  unsigned char t;
-
-  while ((t = *syms++) != 0)
-    vip_metacharacters[t] |= bit;
-}
-
-/* Can be called any time.  More arguments may appear in future.  */
-static void
-vip_op_defaults (immediate, indirect, displen)
-     const char *immediate;
-     const char *indirect;
-     const char *displen;
-{
-  vip_op_1 (VIP_IMMEDIATE, immediate);
-  vip_op_1 (VIP_INDIRECT, indirect);
-  vip_op_1 (VIP_DISPLEN, displen);
-}
+  mode	reg	len	ndx
+  (Rn) => @Rn
+  {@}Rn			5+@	n	' '	optional
+  branch operand		0	-1	' '	-1
+  S^#foo			0	-1	's'	-1
+  -(Rn)			7	n	' '	optional
+  {@}(Rn)+		8+@	n	' '	optional
+  {@}#foo, no S^		8+@	PC	" i"	optional
+  {@}{q^}{(Rn)}		10+@+q	option	" bwl"	optional  */
 
-#endif
-
+/* Dissect user-input 'optext' (which is something like "@B^foo@bar(AP)[FP]:")
+   using the vop in vopP. vopP's vop_access and vop_width. We fill _ndx, _reg,
+   _mode, _short, _warn, _error, _expr_begin, _expr_end and _nbytes.  */
 
-/*
- * Dec defines the semantics of address modes (and values)
- * by a two-letter code, explained here.
- *
- *   letter 1:   access type
- *
- *     a         address calculation - no data access, registers forbidden
- *     b         branch displacement
- *     m         read - let go of bus - write back    "modify"
- *     r         read
- *     v         bit field address: like 'a' but registers are OK
- *     w         write
- *     space	 no operator (eg ".long foo") [our convention]
- *
- *   letter 2:   data type (i.e. width, alignment)
- *
- *     b         byte
- *     d         double precision floating point (D format)
- *     f         single precision floating point (F format)
- *     g         G format floating
- *     h         H format floating
- *     l         longword
- *     o         octaword
- *     q         quadword
- *     w         word
- *     ?	 simple synthetic branch operand
- *     -	 unconditional synthetic JSB/JSR operand
- *     !	 complex synthetic branch operand
- *
- * The '-?!' letter 2's are not for external consumption. They are used
- * for various assemblers. Generally, all unknown widths are assumed 0.
- * We don't limit your choice of width character.
- *
- * DEC operands are hard work to parse. For example, '@' as the first
- * character means indirect (deferred) mode but elsewhere it is a shift
- * operator.
- * The long-winded explanation of how this is supposed to work is
- * cancelled. Read a DEC vax manual.
- * We try hard not to parse anything that MIGHT be part of the expression
- * buried in that syntax. For example if we see @...(Rn) we don't check
- * for '-' before the '(' because mode @-(Rn) does not exist.
- *
- * After parsing we have:
- *
- * at                     1 if leading '@' (or Un*x '*')
- * len                    takes one value from " bilsw". eg B^ -> 'b'.
- * hash                   1 if leading '#' (or Un*x '$')
- * expr_begin, expr_end   the expression we did not parse
- *                        even though we don't interpret it, we make use
- *                        of its presence or absence.
- * sign                   -1: -(Rn)    0: absent    +1: (Rn)+
- * paren                  1 if () are around register
- * reg                    major register number 0:15    -1 means absent
- * ndx                    index register number 0:15    -1 means absent
- *
- * Again, I dare not explain it: just trace ALL the code!
- */
-
 static void
-vip_op (optext, vopP)
-     /* user's input string e.g.: "@B^foo@bar(AP)[FP]:" */
-     char *optext;
-     /* Input fields: vop_access, vop_width.
-	Output fields: _ndx, _reg, _mode, _short, _warn,
-	_error _expr_begin, _expr_end, _nbytes.
-	vop_nbytes : number of bytes in a datum.  */
-     struct vop *vopP;
+vip_op (char *optext, struct vop *vopP)
 {
-  /* track operand text forward */
+  /* Track operand text forward.  */
   char *p;
-  /* track operand text backward */
+  /* Track operand text backward.  */
   char *q;
-  /* 1 if leading '@' ('*') seen */
+  /* 1 if leading '@' ('*') seen.  */
   int at;
   /* one of " bilsw" */
   char len;
-  /* 1 if leading '#' ('$') seen */
+  /* 1 if leading '#' ('$') seen.  */
   int hash;
-  /* -1, 0 or +1 */
+  /* -1, 0 or +1.  */
   int sign = 0;
-  /* 1 if () surround register */
+  /* 1 if () surround register.  */
   int paren = 0;
-  /* register number, -1:absent */
+  /* Register number, -1:absent.  */
   int reg = 0;
-  /* index register number -1:absent */
+  /* Index register number -1:absent.  */
   int ndx = 0;
-  /* report illegal operand, ""==OK */
-  /* " " is a FAKE error: means we won */
+  /* Report illegal operand, ""==OK.  */
+  /* " " is a FAKE error: means we won.  */
   /* ANY err that begins with ' ' is a fake.  */
-  /* " " is converted to "" before return */
+  /* " " is converted to "" before return.  */
   const char *err;
-  /* warn about weird modes pf address */
+  /* Warn about weird modes pf address.  */
   const char *wrn;
-  /* preserve q in case we backup */
+  /* Preserve q in case we backup.  */
   char *oldq = NULL;
-  /* build up 4-bit operand mode here */
-  /* note: index mode is in ndx, this is */
-  /* the major mode of operand address */
+  /* Build up 4-bit operand mode here.  */
+  /* Note: index mode is in ndx, this is.  */
+  /* The major mode of operand address.  */
   int mode = 0;
-  /*
-   * Notice how we move wrong-arg-type bugs INSIDE this module: if we
-   * get the types wrong below, we lose at compile time rather than at
-   * lint or run time.
-   */
+  /* Notice how we move wrong-arg-type bugs INSIDE this module: if we
+     get the types wrong below, we lose at compile time rather than at
+     lint or run time.  */
   char access_mode;		/* vop_access.  */
   char width;			/* vop_width.  */
 
@@ -2476,66 +1292,59 @@ vip_op (optext, vopP)
 	p++;			/* skip over whitespace */
     }
 
-  /*
-   * This code is subtle. It tries to detect all legal (letter)'^'
-   * but it doesn't waste time explicitly testing for premature '\0' because
-   * this case is rejected as a mismatch against either (letter) or '^'.
-   */
+  /* This code is subtle. It tries to detect all legal (letter)'^'
+     but it doesn't waste time explicitly testing for premature '\0' because
+     this case is rejected as a mismatch against either (letter) or '^'.  */
   {
     char c;
 
     c = *p;
     c = TOLOWER (c);
     if (DISPLENP (p[1]) && strchr ("bilws", len = c))
-      p += 2;			/* skip (letter) '^' */
-    else			/* no (letter) '^' seen */
-      len = ' ';		/* len is determined */
+      p += 2;			/* Skip (letter) '^'.  */
+    else			/* No (letter) '^' seen.  */
+      len = ' ';		/* Len is determined.  */
   }
 
   if (*p == ' ')		/* Expect all whitespace reduced to ' '.  */
-    p++;			/* skip over whitespace */
+    p++;
 
   if ((hash = IMMEDIATEP (*p)) != 0)	/* 1 if *p=='#' ('$' for Un*x) */
-    p++;			/* hash is determined */
+    p++;			/* Hash is determined.  */
 
-  /*
-   * p points to what may be the beginning of an expression.
-   * We have peeled off the front all that is peelable.
-   * We know at, len, hash.
-   *
-   * Lets point q at the end of the text and parse that (backwards).
-   */
+  /* p points to what may be the beginning of an expression.
+     We have peeled off the front all that is peelable.
+     We know at, len, hash.
+    
+     Lets point q at the end of the text and parse that (backwards).  */
 
   for (q = p; *q; q++)
     ;
-  q--;				/* now q points at last char of text */
-
+  q--;				/* Now q points at last char of text.  */
+
   if (*q == ' ' && q >= p)	/* Expect all whitespace reduced to ' '.  */
     q--;
-  /* reverse over whitespace, but don't */
-  /* run back over *p */
-
-  /*
-   * As a matter of policy here, we look for [Rn], although both Rn and S^#
-   * forbid [Rn]. This is because it is easy, and because only a sick
-   * cyborg would have [...] trailing an expression in a VAX-like assembler.
-   * A meticulous parser would first check for Rn followed by '(' or '['
-   * and not parse a trailing ']' if it found another. We just ban expressions
-   * ending in ']'.
-   */
+
+  /* Reverse over whitespace, but don't.  */
+  /* Run back over *p.  */
+
+  /* As a matter of policy here, we look for [Rn], although both Rn and S^#
+     forbid [Rn]. This is because it is easy, and because only a sick
+     cyborg would have [...] trailing an expression in a VAX-like assembler.
+     A meticulous parser would first check for Rn followed by '(' or '['
+     and not parse a trailing ']' if it found another. We just ban expressions
+     ending in ']'.  */
   if (*q == ']')
     {
       while (q >= p && *q != '[')
 	q--;
-      /* either q<p or we got matching '[' */
+      /* Either q<p or we got matching '['.  */
       if (q < p)
 	err = _("no '[' to match ']'");
       else
 	{
-	  /*
-	   * Confusers like "[]" will eventually lose with a bad register
-	   * name error. So again we don't need to check for early '\0'.
-	   */
+	  /* Confusers like "[]" will eventually lose with a bad register
+	   * name error. So again we don't need to check for early '\0'.  */
 	  if (q[3] == ']')
 	    ndx = vax_reg_parse (q[1], q[2], 0, 0);
 	  else if (q[4] == ']')
@@ -2544,34 +1353,33 @@ vip_op (optext, vopP)
 	    ndx = vax_reg_parse (q[1], q[2], q[3], q[4]);
 	  else
 	    ndx = -1;
-	  /*
-	   * Since we saw a ']' we will demand a register name in the [].
-	   * If luser hasn't given us one: be rude.
-	   */
+	  /* Since we saw a ']' we will demand a register name in the [].
+	   * If luser hasn't given us one: be rude.  */
 	  if (ndx < 0)
 	    err = _("bad register in []");
 	  else if (ndx == PC)
 	    err = _("[PC] index banned");
 	  else
-	    q--;		/* point q just before "[...]" */
+	    /* Point q just before "[...]".  */
+	    q--;
 	}
     }
   else
-    ndx = -1;			/* no ']', so no iNDeX register */
+    /* No ']', so no iNDeX register.  */
+    ndx = -1;
+
+  /* If err = "..." then we lost: run away.
+     Otherwise ndx == -1 if there was no "[...]".
+     Otherwise, ndx is index register number, and q points before "[...]".  */
 
-  /*
-   * If err = "..." then we lost: run away.
-   * Otherwise ndx == -1 if there was no "[...]".
-   * Otherwise, ndx is index register number, and q points before "[...]".
-   */
-
   if (*q == ' ' && q >= p)	/* Expect all whitespace reduced to ' '.  */
     q--;
-  /* reverse over whitespace, but don't */
-  /* run back over *p */
+  /* Reverse over whitespace, but don't.  */
+  /* Run back over *p.  */
   if (!err || !*err)
     {
-      sign = 0;			/* no ()+ or -() seen yet */
+      /* no ()+ or -() seen yet */
+      sign = 0;
 
       if (q > p + 3 && *q == '+' && q[-1] == ')')
 	{
@@ -2589,10 +1397,8 @@ vip_op (optext, vopP)
 	    err = _("no '(' to match ')'");
 	  else
 	    {
-	      /*
-	       * Confusers like "()" will eventually lose with a bad register
-	       * name error. So again we don't need to check for early '\0'.
-	       */
+	      /* Confusers like "()" will eventually lose with a bad register
+	         name error. So again we don't need to check for early '\0'.  */
 	      if (q[3] == ')')
 		reg = vax_reg_parse (q[1], q[2], 0, 0);
 	      else if (q[4] == ')')
@@ -2601,15 +1407,13 @@ vip_op (optext, vopP)
 		reg = vax_reg_parse (q[1], q[2], q[3], q[4]);
 	      else
 		reg = -1;
-	      /*
-	       * Since we saw a ')' we will demand a register name in the ')'.
-	       * This is nasty: why can't our hypothetical assembler permit
-	       * parenthesised expressions? BECAUSE I AM LAZY! That is why.
-	       * Abuse luser if we didn't spy a register name.
-	       */
+	      /* Since we saw a ')' we will demand a register name in the ')'.
+	         This is nasty: why can't our hypothetical assembler permit
+	         parenthesised expressions? BECAUSE I AM LAZY! That is why.
+	         Abuse luser if we didn't spy a register name.  */
 	      if (reg < 0)
 		{
-		  /* JF allow parenthesized expressions.  I hope this works */
+		  /* JF allow parenthesized expressions.  I hope this works.  */
 		  paren = 0;
 		  while (*q != ')')
 		    q++;
@@ -2617,32 +1421,24 @@ vip_op (optext, vopP)
 		}
 	      else
 		q--;		/* point just before '(' of "(...)" */
-	      /*
-	       * If err == "..." then we lost. Run away.
-	       * Otherwise if reg >= 0 then we saw (Rn).
-	       */
+	      /* If err == "..." then we lost. Run away.
+	         Otherwise if reg >= 0 then we saw (Rn).  */
 	    }
-	  /*
-	   * If err == "..." then we lost.
-	   * Otherwise paren==1 and reg = register in "()".
-	   */
+	  /* If err == "..." then we lost.
+	     Otherwise paren==1 and reg = register in "()".  */
 	}
       else
 	paren = 0;
-      /*
-       * If err == "..." then we lost.
-       * Otherwise, q points just before "(Rn)", if any.
-       * If there was a "(...)" then paren==1, and reg is the register.
-       */
-
-      /*
-       * We should only seek '-' of "-(...)" if:
-       *   we saw "(...)"                    paren == 1
-       *   we have no errors so far          ! *err
-       *   we did not see '+' of "(...)+"    sign < 1
-       * We don't check len. We want a specific error message later if
-       * user tries "x^...-(Rn)". This is a feature not a bug.
-       */
+      /* If err == "..." then we lost.
+         Otherwise, q points just before "(Rn)", if any.
+         If there was a "(...)" then paren==1, and reg is the register.  */
+
+      /* We should only seek '-' of "-(...)" if:
+           we saw "(...)"                    paren == 1
+           we have no errors so far          ! *err
+           we did not see '+' of "(...)+"    sign < 1
+         We don't check len. We want a specific error message later if
+         user tries "x^...-(Rn)". This is a feature not a bug.  */
       if (!err || !*err)
 	{
 	  if (paren && sign < 1)/* !sign is adequate test */
@@ -2653,31 +1449,27 @@ vip_op (optext, vopP)
 		  q--;
 		}
 	    }
-	  /*
-	   * We have back-tracked over most
-	   * of the crud at the end of an operand.
-	   * Unless err, we know: sign, paren. If paren, we know reg.
-	   * The last case is of an expression "Rn".
-	   * This is worth hunting for if !err, !paren.
-	   * We wouldn't be here if err.
-	   * We remember to save q, in case we didn't want "Rn" anyway.
-	   */
+	  /* We have back-tracked over most
+	     of the crud at the end of an operand.
+	     Unless err, we know: sign, paren. If paren, we know reg.
+	     The last case is of an expression "Rn".
+	     This is worth hunting for if !err, !paren.
+	     We wouldn't be here if err.
+	     We remember to save q, in case we didn't want "Rn" anyway.  */
 	  if (!paren)
 	    {
 	      if (*q == ' ' && q >= p)	/* Expect all whitespace reduced to ' '.  */
 		q--;
-	      /* reverse over whitespace, but don't */
-	      /* run back over *p */
-	      /* room for Rn or Rnn (include prefix) exactly? */
+	      /* Reverse over whitespace, but don't.  */
+	      /* Run back over *p.  */
+	      /* Room for Rn or Rnn (include prefix) exactly?  */
 	      if (q > p && q < p + 4)
 		reg = vax_reg_parse (p[0], p[1],
 		  q < p + 2 ? 0 : p[2],
 		  q < p + 3 ? 0 : p[3]);
 	      else
-		reg = -1;	/* always comes here if no register at all */
-	      /*
-	       * Here with a definitive reg value.
-	       */
+		reg = -1;	/* Always comes here if no register at all.  */
+	      /* Here with a definitive reg value.  */
 	      if (reg >= 0)
 		{
 		  oldq = q;
@@ -2686,43 +1478,35 @@ vip_op (optext, vopP)
 	    }
 	}
     }
-  /*
-   * have reg. -1:absent; else 0:15
-   */
-
-  /*
-   * We have:  err, at, len, hash, ndx, sign, paren, reg.
-   * Also, any remaining expression is from *p through *q inclusive.
-   * Should there be no expression, q==p-1. So expression length = q-p+1.
-   * This completes the first part: parsing the operand text.
-   */
+  /* have reg. -1:absent; else 0:15.  */
+
+  /* We have:  err, at, len, hash, ndx, sign, paren, reg.
+     Also, any remaining expression is from *p through *q inclusive.
+     Should there be no expression, q==p-1. So expression length = q-p+1.
+     This completes the first part: parsing the operand text.  */
 
-  /*
-   * We now want to boil the data down, checking consistency on the way.
-   * We want:  len, mode, reg, ndx, err, p, q, wrn, bug.
-   * We will deliver a 4-bit reg, and a 4-bit mode.
-   */
-
-  /*
-   * Case of branch operand. Different. No L^B^W^I^S^ allowed for instance.
-   *
-   * in:  at	?
-   *      len	?
-   *      hash	?
-   *      p:q	?
-   *      sign  ?
-   *      paren	?
-   *      reg   ?
-   *      ndx   ?
-   *
-   * out: mode  0
-   *      reg   -1
-   *      len	' '
-   *      p:q	whatever was input
-   *      ndx	-1
-   *      err	" "		 or error message, and other outputs trashed
-   */
-  /* branch operands have restricted forms */
+  /* We now want to boil the data down, checking consistency on the way.
+     We want:  len, mode, reg, ndx, err, p, q, wrn, bug.
+     We will deliver a 4-bit reg, and a 4-bit mode.  */
+
+  /* Case of branch operand. Different. No L^B^W^I^S^ allowed for instance.
+    
+     in:  at	?
+          len	?
+          hash	?
+          p:q	?
+          sign  ?
+          paren	?
+          reg   ?
+          ndx   ?
+    
+     out: mode  0
+          reg   -1
+          len	' '
+          p:q	whatever was input
+          ndx	-1
+          err	" "		 or error message, and other outputs trashed.  */
+  /* Branch operands have restricted forms.  */
   if ((!err || !*err) && access_mode == 'b')
     {
       if (at || hash || sign || paren || ndx >= 0 || reg >= 0 || len != ' ')
@@ -2730,28 +1514,26 @@ vip_op (optext, vopP)
       else
 	err = " ";
     }
-
+
   /* Since nobody seems to use it: comment this 'feature'(?) out for now.  */
 #ifdef NEVER
-  /*
-   * Case of stand-alone operand. e.g. ".long foo"
-   *
-   * in:  at	?
-   *      len	?
-   *      hash	?
-   *      p:q	?
-   *      sign  ?
-   *      paren	?
-   *      reg   ?
-   *      ndx   ?
-   *
-   * out: mode  0
-   *      reg   -1
-   *      len	' '
-   *      p:q	whatever was input
-   *      ndx	-1
-   *      err	" "		 or error message, and other outputs trashed
-   */
+  /* Case of stand-alone operand. e.g. ".long foo"
+    
+     in:  at	?
+          len	?
+          hash	?
+          p:q	?
+          sign  ?
+          paren	?
+          reg   ?
+          ndx   ?
+    
+     out: mode  0
+          reg   -1
+          len	' '
+          p:q	whatever was input
+          ndx	-1
+          err	" "		 or error message, and other outputs trashed.  */
   if ((!err || !*err) && access_mode == ' ')
     {
       if (at)
@@ -2779,26 +1561,24 @@ vip_op (optext, vopP)
 	  mode = 0;
 	}
     }
-#endif /*#Ifdef NEVER*/
-
-  /*
-   * Case of S^#.
-   *
-   * in:  at       0
-   *      len      's'               definition
-   *      hash     1              demand
-   *      p:q                        demand not empty
-   *      sign     0                 by paren==0
-   *      paren    0             by "()" scan logic because "S^" seen
-   *      reg      -1                or nn by mistake
-   *      ndx      -1
-   *
-   * out: mode     0
-   *      reg      -1
-   *      len      's'
-   *      exp
-   *      ndx      -1
-   */
+#endif
+
+  /* Case of S^#.
+    
+     in:  at       0
+          len      's'               definition
+          hash     1              demand
+          p:q                        demand not empty
+          sign     0                 by paren==0
+          paren    0             by "()" scan logic because "S^" seen
+          reg      -1                or nn by mistake
+          ndx      -1
+    
+     out: mode     0
+          reg      -1
+          len      's'
+          exp
+          ndx      -1  */
   if ((!err || !*err) && len == 's')
     {
       if (!hash || paren || at || ndx >= 0)
@@ -2807,17 +1587,13 @@ vip_op (optext, vopP)
 	{
 	  if (reg >= 0)
 	    {
-	      /*
-	       * SHIT! we saw S^#Rnn ! put the Rnn back in
-	       * expression. KLUDGE! Use oldq so we don't
-	       * need to know exact length of reg name.
-	       */
+	      /* Darn! we saw S^#Rnn ! put the Rnn back in
+	         expression. KLUDGE! Use oldq so we don't
+	         need to know exact length of reg name.  */
 	      q = oldq;
 	      reg = 0;
 	    }
-	  /*
-	   * We have all the expression we will ever get.
-	   */
+	  /* We have all the expression we will ever get.  */
 	  if (p > q)
 	    err = _("S^# needs expression");
 	  else if (access_mode == 'r')
@@ -2829,25 +1605,23 @@ vip_op (optext, vopP)
 	    err = _("S^# may only read-access");
 	}
     }
-
-  /*
-   * Case of -(Rn), which is weird case.
-   *
-   * in:  at       0
-   *      len      '
-   *      hash     0
-   *      p:q      q<p
-   *      sign     -1                by definition
-   *      paren    1              by definition
-   *      reg      present           by definition
-   *      ndx      optional
-   *
-   * out: mode     7
-   *      reg      present
-   *      len      ' '
-   *      exp      ""                enforce empty expression
-   *      ndx      optional          warn if same as reg
-   */
+  
+  /* Case of -(Rn), which is weird case.
+    
+     in:  at       0
+          len      '
+          hash     0
+          p:q      q<p
+          sign     -1                by definition
+          paren    1              by definition
+          reg      present           by definition
+          ndx      optional
+    
+     out: mode     7
+          reg      present
+          len      ' '
+          exp      ""                enforce empty expression
+          ndx      optional          warn if same as reg.  */
   if ((!err || !*err) && sign < 0)
     {
       if (len != ' ' || hash || at || p <= q)
@@ -2862,36 +1636,32 @@ vip_op (optext, vopP)
 	    wrn = _("[]index same as -()register: unpredictable");
 	}
     }
-
-  /*
-   * We convert "(Rn)" to "@Rn" for our convenience.
-   * (I hope this is convenient: has someone got a better way to parse this?)
-   * A side-effect of this is that "@Rn" is a valid operand.
-   */
+
+  /* We convert "(Rn)" to "@Rn" for our convenience.
+     (I hope this is convenient: has someone got a better way to parse this?)
+     A side-effect of this is that "@Rn" is a valid operand.  */
   if (paren && !sign && !hash && !at && len == ' ' && p > q)
     {
       at = 1;
       paren = 0;
     }
 
-  /*
-   * Case of (Rn)+, which is slightly different.
-   *
-   * in:  at
-   *      len      ' '
-   *      hash     0
-   *      p:q      q<p
-   *      sign     +1                by definition
-   *      paren    1              by definition
-   *      reg      present           by definition
-   *      ndx      optional
-   *
-   * out: mode     8+@
-   *      reg      present
-   *      len      ' '
-   *      exp      ""                enforce empty expression
-   *      ndx      optional          warn if same as reg
-   */
+  /* Case of (Rn)+, which is slightly different.
+    
+     in:  at
+          len      ' '
+          hash     0
+          p:q      q<p
+          sign     +1                by definition
+          paren    1              by definition
+          reg      present           by definition
+          ndx      optional
+    
+     out: mode     8+@
+          reg      present
+          len      ' '
+          exp      ""                enforce empty expression
+          ndx      optional          warn if same as reg.  */
   if ((!err || !*err) && sign > 0)
     {
       if (len != ' ' || hash || p <= q)
@@ -2906,25 +1676,23 @@ vip_op (optext, vopP)
 	    wrn = _("[]index same as ()+register: unpredictable");
 	}
     }
-
-  /*
-   * Case of #, without S^.
-   *
-   * in:  at
-   *      len      ' ' or 'i'
-   *      hash     1              by definition
-   *      p:q
-   *      sign     0
-   *      paren    0
-   *      reg      absent
-   *      ndx      optional
-   *
-   * out: mode     8+@
-   *      reg      PC
-   *      len      ' ' or 'i'
-   *      exp
-   *      ndx      optional
-   */
+
+  /* Case of #, without S^.
+    
+     in:  at
+          len      ' ' or 'i'
+          hash     1              by definition
+          p:q
+          sign     0
+          paren    0
+          reg      absent
+          ndx      optional
+    
+     out: mode     8+@
+          reg      PC
+          len      ' ' or 'i'
+          exp
+          ndx      optional.  */
   if ((!err || !*err) && hash)
     {
       if (len != 'i' && len != ' ')
@@ -2935,17 +1703,15 @@ vip_op (optext, vopP)
 	{
 	  if (reg >= 0)
 	    {
-	      /*
-	       * SHIT! we saw #Rnn! Put the Rnn back into the expression.
-	       * By using oldq, we don't need to know how long Rnn was.
-	       * KLUDGE!
-	       */
+	      /* Darn! we saw #Rnn! Put the Rnn back into the expression.
+	         By using oldq, we don't need to know how long Rnn was.
+	         KLUDGE!  */
 	      q = oldq;
-	      reg = -1;		/* no register any more */
+	      reg = -1;		/* No register any more.  */
 	    }
-	  err = " ";		/* win */
+	  err = " ";		/* Win.  */
 
-	  /* JF a bugfix, I think! */
+	  /* JF a bugfix, I think!  */
 	  if (at && access_mode == 'a')
 	    vopP->vop_nbytes = 4;
 
@@ -2955,30 +1721,26 @@ vip_op (optext, vopP)
 	    wrn = _("writing or modifying # is unpredictable");
 	}
     }
-  /*
-   * If !*err, then        sign == 0
-   *                       hash == 0
-   */
-
-  /*
-   * Case of Rn. We separate this one because it has a few special
-   * errors the remaining modes lack.
-   *
-   * in:  at       optional
-   *      len      ' '
-   *      hash     0             by program logic
-   *      p:q      empty
-   *      sign     0                 by program logic
-   *      paren    0             by definition
-   *      reg      present           by definition
-   *      ndx      optional
-   *
-   * out: mode     5+@
-   *      reg      present
-   *      len      ' '               enforce no length
-   *      exp      ""                enforce empty expression
-   *      ndx      optional          warn if same as reg
-   */
+  /* If !*err, then       sign == 0
+                          hash == 0 */
+
+  /* Case of Rn. We separate this one because it has a few special
+     errors the remaining modes lack.
+    
+     in:  at       optional
+          len      ' '
+          hash     0             by program logic
+          p:q      empty
+          sign     0                 by program logic
+          paren    0             by definition
+          reg      present           by definition
+          ndx      optional
+    
+     out: mode     5+@
+          reg      present
+          len      ' '               enforce no length
+          exp      ""                enforce empty expression
+          ndx      optional          warn if same as reg.  */
   if ((!err || !*err) && !paren && reg >= 0)
     {
       if (len != ' ')
@@ -2994,43 +1756,37 @@ vip_op (optext, vopP)
 	err = _("a register has no address");
       else
 	{
-	  /*
-	   * Idea here is to detect from length of datum
-	   * and from register number if we will touch PC.
-	   * Warn if we do.
-	   * vop_nbytes is number of bytes in operand.
-	   * Compute highest byte affected, compare to PC0.
-	   */
+	  /* Idea here is to detect from length of datum
+	     and from register number if we will touch PC.
+	     Warn if we do.
+	     vop_nbytes is number of bytes in operand.
+	     Compute highest byte affected, compare to PC0.  */
 	  if ((vopP->vop_nbytes + reg * 4) > 60)
 	    wrn = _("PC part of operand unpredictable");
 	  err = " ";		/* win */
 	  mode = 5;		/* Rn */
 	}
     }
-  /*
-   * If !*err,        sign  == 0
-   *                  hash  == 0
-   *                  paren == 1  OR reg==-1
-   */
-
-  /*
-   * Rest of cases fit into one bunch.
-   *
-   * in:  at       optional
-   *      len      ' ' or 'b' or 'w' or 'l'
-   *      hash     0             by program logic
-   *      p:q      expected          (empty is not an error)
-   *      sign     0                 by program logic
-   *      paren    optional
-   *      reg      optional
-   *      ndx      optional
-   *
-   * out: mode     10 + @ + len
-   *      reg      optional
-   *      len      ' ' or 'b' or 'w' or 'l'
-   *      exp                        maybe empty
-   *      ndx      optional          warn if same as reg
-   */
+  /* If !*err,        sign  == 0
+                      hash  == 0
+                      paren == 1  OR reg==-1  */
+
+  /* Rest of cases fit into one bunch.
+    
+     in:  at       optional
+          len      ' ' or 'b' or 'w' or 'l'
+          hash     0             by program logic
+          p:q      expected          (empty is not an error)
+          sign     0                 by program logic
+          paren    optional
+          reg      optional
+          ndx      optional
+    
+     out: mode     10 + @ + len
+          reg      optional
+          len      ' ' or 'b' or 'w' or 'l'
+          exp                        maybe empty
+          ndx      optional          warn if same as reg.  */
   if (!err || !*err)
     {
       err = " ";		/* win (always) */
@@ -3041,22 +1797,20 @@ vip_op (optext, vopP)
 	  mode += 2;
 	case 'w':
 	  mode += 2;
-	case ' ':		/* assumed B^ until our caller changes it */
+	case ' ':	/* Assumed B^ until our caller changes it.  */
 	case 'b':
 	  break;
 	}
     }
 
-  /*
-   * here with completely specified     mode
-   *					len
-   *					reg
-   *					expression   p,q
-   *					ndx
-   */
+  /* here with completely specified     mode
+    					len
+    					reg
+    					expression   p,q
+    					ndx.  */
 
   if (*err == ' ')
-    err = 0;			/* " " is no longer an error */
+    err = 0;			/* " " is no longer an error.  */
 
   vopP->vop_mode = mode;
   vopP->vop_reg = reg;
@@ -3067,34 +1821,223 @@ vip_op (optext, vopP)
   vopP->vop_error = err;
   vopP->vop_warn = wrn;
 }
+
+/* This converts a string into a vax instruction.
+   The string must be a bare single instruction in dec-vax (with BSD4 frobs)
+   format.
+   It provides some error messages: at most one fatal error message (which
+   stops the scan) and at most one warning message for each operand.
+   The vax instruction is returned in exploded form, since we have no
+   knowledge of how you parse (or evaluate) your expressions.
+   We do however strip off and decode addressing modes and operation
+   mnemonic.
+  
+   The exploded instruction is returned to a struct vit of your choice.
+   #include "vax-inst.h" to know what a struct vit is.
+  
+   This function's value is a string. If it is not "" then an internal
+   logic error was found: read this code to assign meaning to the string.
+   No argument string should generate such an error string:
+   it means a bug in our code, not in the user's text.
+  
+   You MUST have called vip_begin() once before using this function.  */
+
+static void
+vip (struct vit *vitP,		/* We build an exploded instruction here.  */
+     char *instring)		/* Text of a vax instruction: we modify.  */
+{
+  /* How to bit-encode this opcode.  */
+  struct vot_wot *vwP;
+  /* 1/skip whitespace.2/scan vot_how */
+  char *p;
+  char *q;
+  /* counts number of operands seen */
+  unsigned char count;
+  /* scan operands in struct vit */
+  struct vop *operandp;
+  /* error over all operands */
+  const char *alloperr;
+  /* Remember char, (we clobber it with '\0' temporarily).  */
+  char c;
+  /* Op-code of this instruction.  */
+  vax_opcodeT oc;
+
+  if (*instring == ' ')
+    ++instring;
+  
+  /* MUST end in end-of-string or exactly 1 space.  */
+  for (p = instring; *p && *p != ' '; p++)
+    ;
+
+  /* Scanned up to end of operation-code.  */
+  /* Operation-code is ended with whitespace.  */
+  if (p - instring == 0)
+    {
+      vitP->vit_error = _("No operator");
+      count = 0;
+      memset (vitP->vit_opcode, '\0', sizeof (vitP->vit_opcode));
+    }
+  else
+    {
+      c = *p;
+      *p = '\0';
+      /* Here with instring pointing to what better be an op-name, and p
+         pointing to character just past that.
+         We trust instring points to an op-name, with no whitespace.  */
+      vwP = (struct vot_wot *) hash_find (op_hash, instring);
+      /* Restore char after op-code.  */
+      *p = c;
+      if (vwP == 0)
+	{
+	  vitP->vit_error = _("Unknown operator");
+	  count = 0;
+	  memset (vitP->vit_opcode, '\0', sizeof (vitP->vit_opcode));
+	}
+      else
+	{
+	  /* We found a match! So let's pick up as many operands as the
+	     instruction wants, and even gripe if there are too many.
+	     We expect comma to separate each operand.
+	     We let instring track the text, while p tracks a part of the
+	     struct vot.  */
+	  const char *howp;
+	  /* The lines below know about 2-byte opcodes starting FD,FE or FF.
+	     They also understand synthetic opcodes. Note:
+	     we return 32 bits of opcode, including bucky bits, BUT
+	     an opcode length is either 8 or 16 bits for vit_opcode_nbytes.  */
+	  oc = vwP->vot_code;	/* The op-code.  */
+	  vitP->vit_opcode_nbytes = (oc & 0xFF) >= 0xFD ? 2 : 1;
+	  md_number_to_chars (vitP->vit_opcode, oc, 4);
+	  count = 0;		/* No operands seen yet.  */
+	  instring = p;		/* Point just past operation code.  */
+	  alloperr = "";
+	  for (howp = vwP->vot_how, operandp = vitP->vit_operand;
+	       !(alloperr && *alloperr) && *howp;
+	       operandp++, howp += 2)
+	    {
+	      /* Here to parse one operand. Leave instring pointing just
+	         past any one ',' that marks the end of this operand.  */
+	      if (!howp[1])
+		as_fatal (_("odd number of bytes in operand description"));
+	      else if (*instring)
+		{
+		  for (q = instring; (c = *q) && c != ','; q++)
+		    ;
+		  /* Q points to ',' or '\0' that ends argument. C is that
+		     character.  */
+		  *q = 0;
+		  operandp->vop_width = howp[1];
+		  operandp->vop_nbytes = vax_operand_width_size[(unsigned) howp[1]];
+		  operandp->vop_access = howp[0];
+		  vip_op (instring, operandp);
+		  *q = c;	/* Restore input text.  */
+		  if (operandp->vop_error)
+		    alloperr = _("Bad operand");
+		  instring = q + (c ? 1 : 0);	/* Next operand (if any).  */
+		  count++;	/*  Won another argument, may have an operr.  */
+		}
+	      else
+		alloperr = _("Not enough operands");
+	    }
+	  if (!*alloperr)
+	    {
+	      if (*instring == ' ')
+		instring++;
+	      if (*instring)
+		alloperr = _("Too many operands");
+	    }
+	  vitP->vit_error = alloperr;
+	}
+    }
+  vitP->vit_operands = count;
+}
 
-/*
+#ifdef test
 
-  Summary of vip_op outputs.
+/* Test program for above.  */
 
-  mode	reg	len	ndx
-  (Rn) => @Rn
-  {@}Rn			5+@	n	' '	optional
-  branch operand		0	-1	' '	-1
-  S^#foo			0	-1	's'	-1
-  -(Rn)			7	n	' '	optional
-  {@}(Rn)+		8+@	n	' '	optional
-  {@}#foo, no S^		8+@	PC	" i"	optional
-  {@}{q^}{(Rn)}		10+@+q	option	" bwl"	optional
+struct vit myvit;		/* Build an exploded vax instruction here.  */
+char answer[100];		/* Human types a line of vax assembler here.  */
+char *mybug;			/* "" or an internal logic diagnostic.  */
+int mycount;			/* Number of operands.  */
+struct vop *myvop;		/* Scan operands from myvit.  */
+int mysynth;			/* 1 means want synthetic opcodes.  */
+char my_immediate[200];
+char my_indirect[200];
+char my_displen[200];
+
+int
+main (void)
+{
+  char *p;
+
+  printf ("0 means no synthetic instructions.   ");
+  printf ("Value for vip_begin?  ");
+  gets (answer);
+  sscanf (answer, "%d", &mysynth);
+  printf ("Synthetic opcodes %s be included.\n", mysynth ? "will" : "will not");
+  printf ("enter immediate symbols eg enter #   ");
+  gets (my_immediate);
+  printf ("enter indirect symbols  eg enter @   ");
+  gets (my_indirect);
+  printf ("enter displen symbols   eg enter ^   ");
+  gets (my_displen);
+
+  if (p = vip_begin (mysynth, my_immediate, my_indirect, my_displen))
+    error ("vip_begin=%s", p);
+
+  printf ("An empty input line will quit you from the vax instruction parser\n");
+  for (;;)
+    {
+      printf ("vax instruction: ");
+      fflush (stdout);
+      gets (answer);
+      if (!*answer)
+	break;		/* Out of for each input text loop.  */
+
+      vip (& myvit, answer);
+      if (*myvit.vit_error)
+	printf ("ERR:\"%s\"\n", myvit.vit_error);
+
+      printf ("opcode=");
+      for (mycount = myvit.vit_opcode_nbytes, p = myvit.vit_opcode;
+	   mycount;
+	   mycount--, p++)
+	printf ("%02x ", *p & 0xFF);
+
+      printf ("   operand count=%d.\n", mycount = myvit.vit_operands);
+      for (myvop = myvit.vit_operand; mycount; mycount--, myvop++)
+	{
+	  printf ("mode=%xx reg=%xx ndx=%xx len='%c'=%c%c%d. expr=\"",
+		  myvop->vop_mode, myvop->vop_reg, myvop->vop_ndx,
+		  myvop->vop_short, myvop->vop_access, myvop->vop_width,
+		  myvop->vop_nbytes);
+	  for (p = myvop->vop_expr_begin; p <= myvop->vop_expr_end; p++)
+	    putchar (*p);
+
+	  printf ("\"\n");
+	  if (myvop->vop_error)
+	    printf ("  err:\"%s\"\n", myvop->vop_error);
 
-  */
+	  if (myvop->vop_warn)
+	    printf ("  wrn:\"%s\"\n", myvop->vop_warn);
+	}
+    }
+  vip_end ();
+  exit (EXIT_SUCCESS);
+}
+
+#endif
 
 #ifdef TEST			/* #Define to use this testbed.  */
 
-/*
- * Follows a test program for this function.
- * We declare arrays non-local in case some of our tiny-minded machines
- * default to small stacks. Also, helps with some debuggers.
- */
+/* Follows a test program for this function.
+   We declare arrays non-local in case some of our tiny-minded machines
+   default to small stacks. Also, helps with some debuggers.  */
 
 #include <stdio.h>
 
-char answer[100];		/* human types into here */
+char answer[100];		/* Human types into here.  */
 char *p;			/*  */
 char *myerr;
 char *mywrn;
@@ -3112,7 +2055,8 @@ char my_immediate[200];
 char my_indirect[200];
 char my_displen[200];
 
-main ()
+int
+main (void)
 {
   printf ("enter immediate symbols eg enter #   ");
   gets (my_immediate);
@@ -3121,6 +2065,7 @@ main ()
   printf ("enter displen symbols   eg enter ^   ");
   gets (my_displen);
   vip_op_defaults (my_immediate, my_indirect, my_displen);
+
   for (;;)
     {
       printf ("access,width (eg 'ab' or 'wh') [empty line to quit] :  ");
@@ -3198,9 +2143,8 @@ main ()
     }
 }
 
-mumble (text, value)
-     char *text;
-     int value;
+void
+mumble (char *text, int value)
 {
   printf ("%s:", text);
   if (value >= 0)
@@ -3210,21 +2154,17 @@ mumble (text, value)
   printf ("  ");
 }
 
-#endif /* ifdef TEST */
-
-/* end: vip_op.c */
+#endif
 
-const int md_short_jump_size = 3;
-const int md_long_jump_size = 6;
-const int md_reloc_size = 8;	/* Size of relocation record */
+int md_short_jump_size = 3;
+int md_long_jump_size = 6;
 
 void
-md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr;
-     addressT to_addr ATTRIBUTE_UNUSED;
-     fragS *frag ATTRIBUTE_UNUSED;
-     symbolS *to_symbol ATTRIBUTE_UNUSED;
+md_create_short_jump (char *ptr,
+		      addressT from_addr,
+		      addressT to_addr ATTRIBUTE_UNUSED,
+		      fragS *frag ATTRIBUTE_UNUSED,
+		      symbolS *to_symbol ATTRIBUTE_UNUSED)
 {
   valueT offset;
 
@@ -3233,22 +2173,21 @@ md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
      We need to account for the one byte instruction and also its
      two byte operand.  */
   offset = to_addr - (from_addr + 1 + 2);
-  *ptr++ = VAX_BRW;		/* branch with word (16 bit) offset */
+  *ptr++ = VAX_BRW;		/* Branch with word (16 bit) offset.  */
   md_number_to_chars (ptr, offset, 2);
 }
 
 void
-md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
-     char *ptr;
-     addressT from_addr ATTRIBUTE_UNUSED;
-     addressT to_addr;
-     fragS *frag;
-     symbolS *to_symbol;
+md_create_long_jump (char *ptr,
+		     addressT from_addr ATTRIBUTE_UNUSED,
+		     addressT to_addr,
+		     fragS *frag,
+		     symbolS *to_symbol)
 {
   valueT offset;
 
   offset = to_addr - S_GET_VALUE (to_symbol);
-  *ptr++ = VAX_JMP;		/* arbitrary jump */
+  *ptr++ = VAX_JMP;		/* Arbitrary jump.  */
   *ptr++ = VAX_ABSOLUTE_MODE;
   md_number_to_chars (ptr, offset, 4);
   fix_new (frag, ptr - frag->fr_literal, 4, to_symbol, (long) 0, 0, NO_RELOC);
@@ -3261,19 +2200,18 @@ const char *md_shortopts = "d:STt:VkKQ:";
 #else
 const char *md_shortopts = "d:STt:V";
 #endif
-struct option md_longopts[] = {
+struct option md_longopts[] =
+{
 #ifdef OBJ_ELF
 #define OPTION_PIC (OPTION_MD_BASE)
-  {"pic", no_argument, NULL, OPTION_PIC},
+  { "pic", no_argument, NULL, OPTION_PIC },
 #endif
-  {NULL, no_argument, NULL, 0}
+  { NULL, no_argument, NULL, 0 }
 };
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
@@ -3302,15 +2240,15 @@ md_parse_option (c, arg)
       flag_hash_long_names = 1;
       break;
 
-    case '1':			/* For backward compatibility */
+    case '1':			/* For backward compatibility.  */
       flag_one = 1;
       break;
 
-    case 'H':			/* Show new symbol after hash truncation */
+    case 'H':			/* Show new symbol after hash truncation.  */
       flag_show_after_trunc = 1;
       break;
 
-    case 'h':			/* No hashing of mixed-case names */
+    case 'h':			/* No hashing of mixed-case names.  */
       {
 	extern char vms_name_mapping;
 	vms_name_mapping = atoi (arg);
@@ -3321,8 +2259,9 @@ md_parse_option (c, arg)
     case 'v':
       {
 	extern char *compiler_version_string;
+
 	if (!arg || !*arg || access (arg, 0) == 0)
-	  return 0;		/* have caller show the assembler version */
+	  return 0;		/* Have caller show the assembler version.  */
 	compiler_version_string = arg;
       }
       break;
@@ -3332,7 +2271,7 @@ md_parse_option (c, arg)
     case OPTION_PIC:
     case 'k':
       flag_want_pic = 1;
-      break;			/* -pic, Position Independent Code */
+      break;			/* -pic, Position Independent Code.  */
 
      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment
 	section should be emitted or not.  FIXME: Not implemented.  */
@@ -3348,8 +2287,7 @@ md_parse_option (c, arg)
 }
 
 void
-md_show_usage (stream)
-     FILE *stream;
+md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 VAX options:\n\
@@ -3374,56 +2312,36 @@ VMS options:\n\
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
-  return 0;
+  return NULL;
 }
 
 /* Round up a section size to the appropriate boundary.  */
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
 {
-  return size;			/* Byte alignment is fine */
+  /* Byte alignment is fine */
+  return size;
 }
 
 /* Exactly what point is a PC-relative offset relative TO?
    On the vax, they're relative to the address of the offset, plus
    its size. */
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
-#ifdef OBJ_AOUT
-#ifndef BFD_ASSEMBLER
-void
-tc_headers_hook(headers)
-     object_headers *headers;
-{
-#ifdef TE_NetBSD
-  N_SET_INFO(headers->header, OMAGIC, M_VAX4K_NETBSD, 0);
-  headers->header.a_info = htonl(headers->header.a_info);
-#endif
-}
-#endif /* !BFD_ASSEMBLER */
-#endif /* OBJ_AOUT */
-
-#ifdef BFD_ASSEMBLER
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
   bfd_reloc_code_real_type code;
 
   if (fixp->fx_tcbit)
-    abort();
+    abort ();
 
   if (fixp->fx_r_type != BFD_RELOC_NONE)
     {
@@ -3471,8 +2389,8 @@ tc_gen_reloc (section, fixp)
 #undef F
 #undef MAP
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 #ifndef OBJ_ELF
@@ -3489,6 +2407,863 @@ tc_gen_reloc (section, fixp)
 
   return reloc;
 }
-#endif	/* BFD_ASSEMBLER */
 
-/* end of tc-vax.c */
+/* vax:md_assemble() emit frags for 1 instruction given in textual form.  */
+void
+md_assemble (char *instruction_string)
+{
+  /* Non-zero if operand expression's segment is not known yet.  */
+  int is_undefined;
+  /* Non-zero if operand expression's segment is absolute.  */
+  int is_absolute;
+  int length_code;
+  char *p;
+  /* An operand. Scans all operands.  */
+  struct vop *operandP;
+  char *save_input_line_pointer;
+			/* What used to live after an expression.  */
+  char c_save;
+  /* 1: instruction_string bad for all passes.  */
+  int goofed;
+  /* Points to slot just after last operand.  */
+  struct vop *end_operandP;
+  /* Points to expression values for this operand.  */
+  expressionS *expP;
+  segT *segP;
+
+  /* These refer to an instruction operand expression.  */
+  /* Target segment of the address.	 */
+  segT to_seg;
+  valueT this_add_number;
+  /* Positive (minuend) symbol.  */
+  symbolS *this_add_symbol;
+  /* As a number.  */
+  long opcode_as_number;
+  /* Least significant byte 1st.  */
+  char *opcode_as_chars;
+  /* As an array of characters.  */
+  /* Least significant byte 1st */
+  char *opcode_low_byteP;
+  /* length (bytes) meant by vop_short.  */
+  int length;
+  /* 0, or 1 if '@' is in addressing mode.  */
+  int at;
+  /* From vop_nbytes: vax_operand_width (in bytes) */
+  int nbytes;
+  FLONUM_TYPE *floatP;
+  LITTLENUM_TYPE literal_float[8];
+  /* Big enough for any floating point literal.  */
+
+  vip (&v, instruction_string);
+
+  /* Now we try to find as many as_warn()s as we can. If we do any as_warn()s
+     then goofed=1. Notice that we don't make any frags yet.
+     Should goofed be 1, then this instruction will wedge in any pass,
+     and we can safely flush it, without causing interpass symbol phase
+     errors. That is, without changing label values in different passes.  */
+  if ((goofed = (*v.vit_error)) != 0)
+    {
+      as_fatal (_("Ignoring statement due to \"%s\""), v.vit_error);
+    }
+  /* We need to use expression() and friends, which require us to diddle
+     input_line_pointer. So we save it and restore it later.  */
+  save_input_line_pointer = input_line_pointer;
+  for (operandP = v.vit_operand,
+       expP = exp_of_operand,
+       segP = seg_of_operand,
+       floatP = float_operand,
+       end_operandP = v.vit_operand + v.vit_operands;
+
+       operandP < end_operandP;
+
+       operandP++, expP++, segP++, floatP++)
+    {
+      if (operandP->vop_error)
+	{
+	  as_fatal (_("Aborting because statement has \"%s\""), operandP->vop_error);
+	  goofed = 1;
+	}
+      else
+	{
+	  /* Statement has no syntax goofs: let's sniff the expression.  */
+	  int can_be_short = 0;	/* 1 if a bignum can be reduced to a short literal.  */
+
+	  input_line_pointer = operandP->vop_expr_begin;
+	  c_save = operandP->vop_expr_end[1];
+	  operandP->vop_expr_end[1] = '\0';
+	  /* If to_seg == SEG_PASS1, expression() will have set need_pass_2 = 1.  */
+	  *segP = expression (expP);
+	  switch (expP->X_op)
+	    {
+	    case O_absent:
+	      /* for BSD4.2 compatibility, missing expression is absolute 0 */
+	      expP->X_op = O_constant;
+	      expP->X_add_number = 0;
+	      /* For SEG_ABSOLUTE, we shouldn't need to set X_op_symbol,
+		 X_add_symbol to any particular value.  But, we will program
+		 defensively. Since this situation occurs rarely so it costs
+		 us little to do, and stops Dean worrying about the origin of
+		 random bits in expressionS's.  */
+	      expP->X_add_symbol = NULL;
+	      expP->X_op_symbol = NULL;
+	      break;
+
+	    case O_symbol:
+	    case O_constant:
+	      break;
+
+	    default:
+	      /* Major bug. We can't handle the case of a
+	         SEG_OP expression in a VIT_OPCODE_SYNTHETIC
+	         variable-length instruction.
+	         We don't have a frag type that is smart enough to
+	         relax a SEG_OP, and so we just force all
+	         SEG_OPs to behave like SEG_PASS1s.
+	         Clearly, if there is a demand we can invent a new or
+	         modified frag type and then coding up a frag for this
+	         case will be easy. SEG_OP was invented for the
+	         .words after a CASE opcode, and was never intended for
+	         instruction operands.  */
+	      need_pass_2 = 1;
+	      as_fatal (_("Can't relocate expression"));
+	      break;
+
+	    case O_big:
+	      /* Preserve the bits.  */
+	      if (expP->X_add_number > 0)
+		{
+		  bignum_copy (generic_bignum, expP->X_add_number,
+			       floatP->low, SIZE_OF_LARGE_NUMBER);
+		}
+	      else
+		{
+		  know (expP->X_add_number < 0);
+		  flonum_copy (&generic_floating_point_number,
+			       floatP);
+		  if (strchr ("s i", operandP->vop_short))
+		    {
+		      /* Could possibly become S^# */
+		      flonum_gen2vax (-expP->X_add_number, floatP, literal_float);
+		      switch (-expP->X_add_number)
+			{
+			case 'f':
+			  can_be_short =
+			    (literal_float[0] & 0xFC0F) == 0x4000
+			    && literal_float[1] == 0;
+			  break;
+
+			case 'd':
+			  can_be_short =
+			    (literal_float[0] & 0xFC0F) == 0x4000
+			    && literal_float[1] == 0
+			    && literal_float[2] == 0
+			    && literal_float[3] == 0;
+			  break;
+
+			case 'g':
+			  can_be_short =
+			    (literal_float[0] & 0xFF81) == 0x4000
+			    && literal_float[1] == 0
+			    && literal_float[2] == 0
+			    && literal_float[3] == 0;
+			  break;
+
+			case 'h':
+			  can_be_short = ((literal_float[0] & 0xFFF8) == 0x4000
+					  && (literal_float[1] & 0xE000) == 0
+					  && literal_float[2] == 0
+					  && literal_float[3] == 0
+					  && literal_float[4] == 0
+					  && literal_float[5] == 0
+					  && literal_float[6] == 0
+					  && literal_float[7] == 0);
+			  break;
+
+			default:
+			  BAD_CASE (-expP->X_add_number);
+			  break;
+			}
+		    }
+		}
+
+	      if (operandP->vop_short == 's'
+		  || operandP->vop_short == 'i'
+		  || (operandP->vop_short == ' '
+		      && operandP->vop_reg == 0xF
+		      && (operandP->vop_mode & 0xE) == 0x8))
+		{
+		  /* Saw a '#'.  */
+		  if (operandP->vop_short == ' ')
+		    {
+		      /* We must chose S^ or I^.  */
+		      if (expP->X_add_number > 0)
+			{
+			  /* Bignum: Short literal impossible.  */
+			  operandP->vop_short = 'i';
+			  operandP->vop_mode = 8;
+			  operandP->vop_reg = 0xF;	/* VAX PC.  */
+			}
+		      else
+			{
+			  /* Flonum: Try to do it.  */
+			  if (can_be_short)
+			    {
+			      operandP->vop_short = 's';
+			      operandP->vop_mode = 0;
+			      operandP->vop_ndx = -1;
+			      operandP->vop_reg = -1;
+			      expP->X_op = O_constant;
+			    }
+			  else
+			    {
+			      operandP->vop_short = 'i';
+			      operandP->vop_mode = 8;
+			      operandP->vop_reg = 0xF;	/* VAX PC */
+			    }
+			}	/* bignum or flonum ? */
+		    }		/*  if #, but no S^ or I^ seen.  */
+		  /* No more ' ' case: either 's' or 'i'.  */
+		  if (operandP->vop_short == 's')
+		    {
+		      /* Wants to be a short literal.  */
+		      if (expP->X_add_number > 0)
+			{
+			  as_warn (_("Bignum not permitted in short literal. Immediate mode assumed."));
+			  operandP->vop_short = 'i';
+			  operandP->vop_mode = 8;
+			  operandP->vop_reg = 0xF;	/* VAX PC.  */
+			}
+		      else
+			{
+			  if (!can_be_short)
+			    {
+			      as_warn (_("Can't do flonum short literal: immediate mode used."));
+			      operandP->vop_short = 'i';
+			      operandP->vop_mode = 8;
+			      operandP->vop_reg = 0xF;	/* VAX PC.  */
+			    }
+			  else
+			    {
+			      /* Encode short literal now.  */
+			      int temp = 0;
+
+			      switch (-expP->X_add_number)
+				{
+				case 'f':
+				case 'd':
+				  temp = literal_float[0] >> 4;
+				  break;
+
+				case 'g':
+				  temp = literal_float[0] >> 1;
+				  break;
+
+				case 'h':
+				  temp = ((literal_float[0] << 3) & 070)
+				    | ((literal_float[1] >> 13) & 07);
+				  break;
+
+				default:
+				  BAD_CASE (-expP->X_add_number);
+				  break;
+				}
+
+			      floatP->low[0] = temp & 077;
+			      floatP->low[1] = 0;
+			    }
+			}
+		    }
+		  else
+		    {
+		      /* I^# seen: set it up if float.  */
+		      if (expP->X_add_number < 0)
+			{
+			  memcpy (floatP->low, literal_float, sizeof (literal_float));
+			}
+		    }		/* if S^# seen.  */
+		}
+	      else
+		{
+		  as_warn (_("A bignum/flonum may not be a displacement: 0x%lx used"),
+			   (expP->X_add_number = 0x80000000L));
+		  /* Chosen so luser gets the most offset bits to patch later.  */
+		}
+	      expP->X_add_number = floatP->low[0]
+		| ((LITTLENUM_MASK & (floatP->low[1])) << LITTLENUM_NUMBER_OF_BITS);
+
+	      /* For the O_big case we have:
+	         If vop_short == 's' then a short floating literal is in the
+	        	lowest 6 bits of floatP -> low [0], which is
+	        	big_operand_bits [---] [0].
+	         If vop_short == 'i' then the appropriate number of elements
+	        	of big_operand_bits [---] [...] are set up with the correct
+	        	bits.
+	         Also, just in case width is byte word or long, we copy the lowest
+	         32 bits of the number to X_add_number.  */
+	      break;
+	    }
+	  if (input_line_pointer != operandP->vop_expr_end + 1)
+	    {
+	      as_fatal ("Junk at end of expression \"%s\"", input_line_pointer);
+	      goofed = 1;
+	    }
+	  operandP->vop_expr_end[1] = c_save;
+	}
+    }
+
+  input_line_pointer = save_input_line_pointer;
+
+  if (need_pass_2 || goofed)
+    return;
+
+  /* Emit op-code.  */
+  /* Remember where it is, in case we want to modify the op-code later.  */
+  opcode_low_byteP = frag_more (v.vit_opcode_nbytes);
+  memcpy (opcode_low_byteP, v.vit_opcode, v.vit_opcode_nbytes);
+  opcode_as_chars = v.vit_opcode;
+  opcode_as_number = md_chars_to_number ((unsigned char *) opcode_as_chars, 4);
+  for (operandP = v.vit_operand,
+       expP = exp_of_operand,
+       segP = seg_of_operand,
+       floatP = float_operand,
+       end_operandP = v.vit_operand + v.vit_operands;
+
+       operandP < end_operandP;
+
+       operandP++,
+       floatP++,
+       segP++,
+       expP++)
+    {
+      if (operandP->vop_ndx >= 0)
+	{
+	  /* Indexed addressing byte.  */
+	  /* Legality of indexed mode already checked: it is OK.  */
+	  FRAG_APPEND_1_CHAR (0x40 + operandP->vop_ndx);
+	}			/* if(vop_ndx>=0) */
+
+      /* Here to make main operand frag(s).  */
+      this_add_number = expP->X_add_number;
+      this_add_symbol = expP->X_add_symbol;
+      to_seg = *segP;
+      is_undefined = (to_seg == undefined_section);
+      is_absolute = (to_seg == absolute_section);
+      at = operandP->vop_mode & 1;
+      length = (operandP->vop_short == 'b'
+		? 1 : (operandP->vop_short == 'w'
+		       ? 2 : (operandP->vop_short == 'l'
+			      ? 4 : 0)));
+      nbytes = operandP->vop_nbytes;
+      if (operandP->vop_access == 'b')
+	{
+	  if (to_seg == now_seg || is_undefined)
+	    {
+	      /* If is_undefined, then it might BECOME now_seg.  */
+	      if (nbytes)
+		{
+		  p = frag_more (nbytes);
+		  fix_new (frag_now, p - frag_now->fr_literal, nbytes,
+			   this_add_symbol, this_add_number, 1, NO_RELOC);
+		}
+	      else
+		{
+		  /* to_seg==now_seg || to_seg == SEG_UNKNOWN */
+		  /* nbytes==0 */
+		  length_code = is_undefined ? STATE_UNDF : STATE_BYTE;
+		  if (opcode_as_number & VIT_OPCODE_SPECIAL)
+		    {
+		      if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
+			{
+			  /* br or jsb */
+			  frag_var (rs_machine_dependent, 5, 1,
+			    ENCODE_RELAX (STATE_ALWAYS_BRANCH, length_code),
+				    this_add_symbol, this_add_number,
+				    opcode_low_byteP);
+			}
+		      else
+			{
+			  if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
+			    {
+			      length_code = STATE_WORD;
+			      /* JF: There is no state_byte for this one! */
+			      frag_var (rs_machine_dependent, 10, 2,
+					ENCODE_RELAX (STATE_COMPLEX_BRANCH, length_code),
+					this_add_symbol, this_add_number,
+					opcode_low_byteP);
+			    }
+			  else
+			    {
+			      know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
+			      frag_var (rs_machine_dependent, 9, 1,
+			      ENCODE_RELAX (STATE_COMPLEX_HOP, length_code),
+					this_add_symbol, this_add_number,
+					opcode_low_byteP);
+			    }
+			}
+		    }
+		  else
+		    {
+		      know (operandP->vop_width == VAX_WIDTH_CONDITIONAL_JUMP);
+		      frag_var (rs_machine_dependent, 7, 1,
+		       ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, length_code),
+				this_add_symbol, this_add_number,
+				opcode_low_byteP);
+		    }
+		}
+	    }
+	  else
+	    {
+	      /* to_seg != now_seg && to_seg != SEG_UNKNOWN */
+	      /* --- SEG FLOAT MAY APPEAR HERE ---  */
+	      if (is_absolute)
+		{
+		  if (nbytes)
+		    {
+		      know (!(opcode_as_number & VIT_OPCODE_SYNTHETIC));
+		      p = frag_more (nbytes);
+		      /* Conventional relocation.  */
+		      fix_new (frag_now, p - frag_now->fr_literal, nbytes,
+			       section_symbol (absolute_section),
+			       this_add_number, 1, NO_RELOC);
+		    }
+		  else
+		    {
+		      know (opcode_as_number & VIT_OPCODE_SYNTHETIC);
+		      if (opcode_as_number & VIT_OPCODE_SPECIAL)
+			{
+			  if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
+			    {
+			      /* br or jsb */
+			      *opcode_low_byteP = opcode_as_chars[0] + VAX_WIDEN_LONG;
+			      know (opcode_as_chars[1] == 0);
+			      p = frag_more (5);
+			      p[0] = VAX_ABSOLUTE_MODE;	/* @#...  */
+			      md_number_to_chars (p + 1, this_add_number, 4);
+			      /* Now (eg) JMP @#foo or JSB @#foo.  */
+			    }
+			  else
+			    {
+			      if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
+				{
+				  p = frag_more (10);
+				  p[0] = 2;
+				  p[1] = 0;
+				  p[2] = VAX_BRB;
+				  p[3] = 6;
+				  p[4] = VAX_JMP;
+				  p[5] = VAX_ABSOLUTE_MODE;	/* @#...  */
+				  md_number_to_chars (p + 6, this_add_number, 4);
+				  /* Now (eg)	ACBx	1f
+				    		BRB	2f
+				    	1:	JMP	@#foo
+				    	2:  */
+				}
+			      else
+				{
+				  know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
+				  p = frag_more (9);
+				  p[0] = 2;
+				  p[1] = VAX_BRB;
+				  p[2] = 6;
+				  p[3] = VAX_JMP;
+                                  p[4] = VAX_ABSOLUTE_MODE;     /* @#...  */
+				  md_number_to_chars (p + 5, this_add_number, 4);
+				  /* Now (eg)	xOBxxx	1f
+				   		BRB	2f
+				   	1:	JMP	@#foo
+				   	2:  */
+				}
+			    }
+			}
+		      else
+			{
+			  /* b<cond> */
+			  *opcode_low_byteP ^= 1;
+			  /* To reverse the condition in a VAX branch,
+			     complement the lowest order bit.  */
+			  p = frag_more (7);
+			  p[0] = 6;
+			  p[1] = VAX_JMP;
+			  p[2] = VAX_ABSOLUTE_MODE;	/* @#...  */
+			  md_number_to_chars (p + 3, this_add_number, 4);
+			  /* Now (eg)	BLEQ	1f
+			   		JMP	@#foo
+			   	1:  */
+			}
+		    }
+		}
+	      else
+		{
+		  /* to_seg != now_seg && !is_undefinfed && !is_absolute */
+		  if (nbytes > 0)
+		    {
+		      /* Pc-relative. Conventional relocation.  */
+		      know (!(opcode_as_number & VIT_OPCODE_SYNTHETIC));
+		      p = frag_more (nbytes);
+		      fix_new (frag_now, p - frag_now->fr_literal, nbytes,
+			       section_symbol (absolute_section),
+			       this_add_number, 1, NO_RELOC);
+		    }
+		  else
+		    {
+		      know (opcode_as_number & VIT_OPCODE_SYNTHETIC);
+		      if (opcode_as_number & VIT_OPCODE_SPECIAL)
+			{
+			  if (operandP->vop_width == VAX_WIDTH_UNCONDITIONAL_JUMP)
+			    {
+			      /* br or jsb */
+			      know (opcode_as_chars[1] == 0);
+			      *opcode_low_byteP = opcode_as_chars[0] + VAX_WIDEN_LONG;
+			      p = frag_more (5);
+			      p[0] = VAX_PC_RELATIVE_MODE;
+			      fix_new (frag_now,
+				       p + 1 - frag_now->fr_literal, 4,
+				       this_add_symbol,
+				       this_add_number, 1, NO_RELOC);
+			      /* Now eg JMP foo or JSB foo.  */
+			    }
+			  else
+			    {
+			      if (operandP->vop_width == VAX_WIDTH_WORD_JUMP)
+				{
+				  p = frag_more (10);
+				  p[0] = 0;
+				  p[1] = 2;
+				  p[2] = VAX_BRB;
+				  p[3] = 6;
+				  p[4] = VAX_JMP;
+				  p[5] = VAX_PC_RELATIVE_MODE;
+				  fix_new (frag_now,
+					   p + 6 - frag_now->fr_literal, 4,
+					   this_add_symbol,
+					   this_add_number, 1, NO_RELOC);
+				  /* Now (eg)	ACBx	1f
+				   		BRB	2f
+				   	1:	JMP	foo
+				   	2:  */
+				}
+			      else
+				{
+				  know (operandP->vop_width == VAX_WIDTH_BYTE_JUMP);
+				  p = frag_more (10);
+				  p[0] = 2;
+				  p[1] = VAX_BRB;
+				  p[2] = 6;
+				  p[3] = VAX_JMP;
+				  p[4] = VAX_PC_RELATIVE_MODE;
+				  fix_new (frag_now,
+					   p + 5 - frag_now->fr_literal,
+					   4, this_add_symbol,
+					   this_add_number, 1, NO_RELOC);
+				  /* Now (eg)	xOBxxx	1f
+				   		BRB	2f
+				   	1:	JMP	foo
+				   	2:  */
+				}
+			    }
+			}
+		      else
+			{
+			  know (operandP->vop_width == VAX_WIDTH_CONDITIONAL_JUMP);
+			  *opcode_low_byteP ^= 1;	/* Reverse branch condition.  */
+			  p = frag_more (7);
+			  p[0] = 6;
+			  p[1] = VAX_JMP;
+			  p[2] = VAX_PC_RELATIVE_MODE;
+			  fix_new (frag_now, p + 3 - frag_now->fr_literal,
+				   4, this_add_symbol,
+				   this_add_number, 1, NO_RELOC);
+			}
+		    }
+		}
+	    }
+	}
+      else
+	{
+	  /* So it is ordinary operand.  */
+	  know (operandP->vop_access != 'b');
+	  /* ' ' target-independent: elsewhere.  */
+	  know (operandP->vop_access != ' ');
+	  know (operandP->vop_access == 'a'
+		|| operandP->vop_access == 'm'
+		|| operandP->vop_access == 'r'
+		|| operandP->vop_access == 'v'
+		|| operandP->vop_access == 'w');
+	  if (operandP->vop_short == 's')
+	    {
+	      if (is_absolute)
+		{
+		  if (this_add_number >= 64)
+		    {
+		      as_warn (_("Short literal overflow(%ld.), immediate mode assumed."),
+			       (long) this_add_number);
+		      operandP->vop_short = 'i';
+		      operandP->vop_mode = 8;
+		      operandP->vop_reg = 0xF;
+		    }
+		}
+	      else
+		{
+		  as_warn (_("Forced short literal to immediate mode. now_seg=%s to_seg=%s"),
+			   segment_name (now_seg), segment_name (to_seg));
+		  operandP->vop_short = 'i';
+		  operandP->vop_mode = 8;
+		  operandP->vop_reg = 0xF;
+		}
+	    }
+	  if (operandP->vop_reg >= 0 && (operandP->vop_mode < 8
+		  || (operandP->vop_reg != 0xF && operandP->vop_mode < 10)))
+	    {
+	      /* One byte operand.  */
+	      know (operandP->vop_mode > 3);
+	      FRAG_APPEND_1_CHAR (operandP->vop_mode << 4 | operandP->vop_reg);
+	      /* All 1-bytes except S^# happen here.  */
+	    }
+	  else
+	    {
+	      /* {@}{q^}foo{(Rn)} or S^#foo */
+	      if (operandP->vop_reg == -1 && operandP->vop_short != 's')
+		{
+		  /* "{@}{q^}foo" */
+		  if (to_seg == now_seg)
+		    {
+		      if (length == 0)
+			{
+			  know (operandP->vop_short == ' ');
+			  length_code = STATE_BYTE;
+#ifdef OBJ_ELF
+			  if (S_IS_EXTERNAL (this_add_symbol)
+			      || S_IS_WEAK (this_add_symbol))
+			    length_code = STATE_UNDF;
+#endif
+			  p = frag_var (rs_machine_dependent, 10, 2,
+			       ENCODE_RELAX (STATE_PC_RELATIVE, length_code),
+					this_add_symbol, this_add_number,
+					opcode_low_byteP);
+			  know (operandP->vop_mode == 10 + at);
+			  *p = at << 4;
+			  /* At is the only context we need to carry
+			     to other side of relax() process.  Must
+			     be in the correct bit position of VAX
+			     operand spec. byte.  */
+			}
+		      else
+			{
+			  know (length);
+			  know (operandP->vop_short != ' ');
+			  p = frag_more (length + 1);
+			  p[0] = 0xF | ((at + "?\12\14?\16"[length]) << 4);
+			  fix_new (frag_now, p + 1 - frag_now->fr_literal,
+				   length, this_add_symbol,
+				   this_add_number, 1, NO_RELOC);
+			}
+		    }
+		  else
+		    {
+		      /* to_seg != now_seg */
+		      if (this_add_symbol == NULL)
+			{
+			  know (is_absolute);
+			  /* Do @#foo: simpler relocation than foo-.(pc) anyway.  */
+			  p = frag_more (5);
+			  p[0] = VAX_ABSOLUTE_MODE;	/* @#...  */
+			  md_number_to_chars (p + 1, this_add_number, 4);
+			  if (length && length != 4)
+			    as_warn (_("Length specification ignored. Address mode 9F used"));
+			}
+		      else
+			{
+			  /* {@}{q^}other_seg */
+			  know ((length == 0 && operandP->vop_short == ' ')
+			     || (length > 0 && operandP->vop_short != ' '));
+			  if (is_undefined
+#ifdef OBJ_ELF
+			      || S_IS_WEAK(this_add_symbol)
+			      || S_IS_EXTERNAL(this_add_symbol)
+#endif
+			      )
+			    {
+			      switch (length)
+				{
+				default: length_code = STATE_UNDF; break;
+				case 1: length_code = STATE_BYTE; break;
+				case 2: length_code = STATE_WORD; break;
+				case 4: length_code = STATE_LONG; break;
+				}
+			      /* We have a SEG_UNKNOWN symbol. It might
+			         turn out to be in the same segment as
+			         the instruction, permitting relaxation.  */
+			      p = frag_var (rs_machine_dependent, 5, 2,
+			       ENCODE_RELAX (STATE_PC_RELATIVE, length_code),
+					    this_add_symbol, this_add_number,
+					    opcode_low_byteP);
+			      p[0] = at << 4;
+			    }
+			  else
+			    {
+			      if (length == 0)
+				{
+				  know (operandP->vop_short == ' ');
+				  length = 4;	/* Longest possible.  */
+				}
+			      p = frag_more (length + 1);
+			      p[0] = 0xF | ((at + "?\12\14?\16"[length]) << 4);
+			      md_number_to_chars (p + 1, this_add_number, length);
+			      fix_new (frag_now,
+				       p + 1 - frag_now->fr_literal,
+				       length, this_add_symbol,
+				       this_add_number, 1, NO_RELOC);
+			    }
+			}
+		    }
+		}
+	      else
+		{
+		  /* {@}{q^}foo(Rn) or S^# or I^# or # */
+		  if (operandP->vop_mode < 0xA)
+		    {
+		      /* # or S^# or I^# */
+		      if (operandP->vop_access == 'v'
+			  || operandP->vop_access == 'a')
+			{
+			  if (operandP->vop_access == 'v')
+			    as_warn (_("Invalid operand:  immediate value used as base address."));
+			  else
+			    as_warn (_("Invalid operand:  immediate value used as address."));
+			  /* gcc 2.6.3 is known to generate these in at least
+			     one case.  */
+			}
+		      if (length == 0
+			  && is_absolute && (expP->X_op != O_big)
+			  && operandP->vop_mode == 8	/* No '@'.  */
+			  && this_add_number < 64)
+			{
+			  operandP->vop_short = 's';
+			}
+		      if (operandP->vop_short == 's')
+			{
+			  FRAG_APPEND_1_CHAR (this_add_number);
+			}
+		      else
+			{
+			  /* I^#...  */
+			  know (nbytes);
+			  p = frag_more (nbytes + 1);
+			  know (operandP->vop_reg == 0xF);
+#ifdef OBJ_ELF
+			  if (flag_want_pic && operandP->vop_mode == 8
+				&& this_add_symbol != NULL)
+			    {
+			      as_warn (_("Symbol used as immediate operand in PIC mode."));
+			    }
+#endif
+			  p[0] = (operandP->vop_mode << 4) | 0xF;
+			  if ((is_absolute) && (expP->X_op != O_big))
+			    {
+			      /* If nbytes > 4, then we are scrod. We
+			         don't know if the high order bytes
+			         are to be 0xFF or 0x00.  BSD4.2 & RMS
+			         say use 0x00. OK --- but this
+			         assembler needs ANOTHER rewrite to
+			         cope properly with this bug.  */
+			      md_number_to_chars (p + 1, this_add_number,
+						  min (sizeof (valueT),
+						       (size_t) nbytes));
+			      if ((size_t) nbytes > sizeof (valueT))
+				memset (p + 5, '\0', nbytes - sizeof (valueT));
+			    }
+			  else
+			    {
+			      if (expP->X_op == O_big)
+				{
+				  /* Problem here is to get the bytes
+				     in the right order.  We stored
+				     our constant as LITTLENUMs, not
+				     bytes.  */
+				  LITTLENUM_TYPE *lP;
+
+				  lP = floatP->low;
+				  if (nbytes & 1)
+				    {
+				      know (nbytes == 1);
+				      p[1] = *lP;
+				    }
+				  else
+				    {
+				      for (p++; nbytes; nbytes -= 2, p += 2, lP++)
+					md_number_to_chars (p, *lP, 2);
+				    }
+				}
+			      else
+				{
+				  fix_new (frag_now, p + 1 - frag_now->fr_literal,
+					   nbytes, this_add_symbol,
+					   this_add_number, 0, NO_RELOC);
+				}
+			    }
+			}
+		    }
+		  else
+		    {
+		      /* {@}{q^}foo(Rn) */
+		      know ((length == 0 && operandP->vop_short == ' ')
+			    || (length > 0 && operandP->vop_short != ' '));
+		      if (length == 0)
+			{
+			  if (is_absolute)
+			    {
+			      long test;
+
+			      test = this_add_number;
+
+			      if (test < 0)
+				test = ~test;
+
+			      length = test & 0xffff8000 ? 4
+				: test & 0xffffff80 ? 2
+				: 1;
+			    }
+			  else
+			    {
+			      length = 4;
+			    }
+			}
+		      p = frag_more (1 + length);
+		      know (operandP->vop_reg >= 0);
+		      p[0] = operandP->vop_reg
+			| ((at | "?\12\14?\16"[length]) << 4);
+		      if (is_absolute)
+			{
+			  md_number_to_chars (p + 1, this_add_number, length);
+			}
+		      else
+			{
+			  fix_new (frag_now, p + 1 - frag_now->fr_literal,
+				   length, this_add_symbol,
+				   this_add_number, 0, NO_RELOC);
+			}
+		    }
+		}
+	    }
+	}
+    }
+}
+
+void
+md_begin (void)
+{
+  const char *errtxt;
+  FLONUM_TYPE *fP;
+  int i;
+
+  if ((errtxt = vip_begin (1, "$", "*", "`")) != 0)
+    as_fatal (_("VIP_BEGIN error:%s"), errtxt);
+
+  for (i = 0, fP = float_operand;
+       fP < float_operand + VIT_MAX_OPERANDS;
+       i++, fP++)
+    {
+      fP->low = &big_operand_bits[i][0];
+      fP->high = &big_operand_bits[i][SIZE_OF_LARGE_NUMBER - 1];
+    }
+}
diff --git a/gas/config/tc-vax.h b/gas/config/tc-vax.h
index a1beb1c82e1a..715d54a812f6 100644
--- a/gas/config/tc-vax.h
+++ b/gas/config/tc-vax.h
@@ -1,5 +1,5 @@
 /* tc-vax.h -- Header file for tc-vax.c.
-   Copyright 1987, 1991, 1992, 1993, 1995, 1996, 1997, 2000, 2002
+   Copyright 1987, 1991, 1992, 1993, 1995, 1996, 1997, 2000, 2002, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_VAX 1
 
@@ -40,27 +40,17 @@
 #define TARGET_FORMAT "elf32-vax"
 #endif
 
-#define BFD_ARCH	bfd_arch_vax	/* for non-BFD_ASSEMBLER */
-#define TARGET_ARCH	bfd_arch_vax	/* BFD_ASSEMBLER */
+#define TARGET_ARCH	bfd_arch_vax
 
-#ifdef BFD_ASSEMBLER
 #define NO_RELOC	BFD_RELOC_NONE
-#else
-#define NO_RELOC	0
-#endif
 #define NOP_OPCODE	0x01
 
-#define tc_aout_pre_write_hook(x)	{;}	/* not used */
-#define tc_crawl_symbol_chain(a)	{;}	/* not used */
 #define md_operand(x)
 
-long md_chars_to_number PARAMS ((unsigned char *, int));
-
 extern const struct relax_type md_relax_table[];
 #define TC_GENERIC_RELAX_TABLE md_relax_table
 
-#ifdef BFD_ASSEMBLER
-/* Values passed to md_apply_fix3 don't include symbol values.  */
+/* Values passed to md_apply_fix don't include symbol values.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
 #define tc_fix_adjustable(FIX)					\
@@ -73,7 +63,6 @@ extern const struct relax_type md_relax_table[];
 		 && (S_GET_SEGMENT ((FIX)->fx_subsy)		\
 		     == S_GET_SEGMENT ((FIX)->fx_addsy)))	\
 	     || S_IS_LOCAL ((FIX)->fx_addsy)))
-#endif
 
 /*
  * Local Variables:
diff --git a/gas/config/tc-w65.c b/gas/config/tc-w65.c
deleted file mode 100644
index 82f39f865c9f..000000000000
--- a/gas/config/tc-w65.c
+++ /dev/null
@@ -1,1137 +0,0 @@
-/* tc-w65.c -- Assemble code for the W65816
-   Copyright 1995, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* Written By Steve Chamberlain <sac@cygnus.com>.  */
-
-#include <stdio.h>
-#include "as.h"
-#include "bfd.h"
-#include "subsegs.h"
-#define DEFINE_TABLE
-#include "../opcodes/w65-opc.h"
-
-const char comment_chars[] = "!";
-const char line_separator_chars[] = ";";
-const char line_comment_chars[] = "!#";
-
-/* This table describes all the machine specific pseudo-ops the assembler
-   has to support.  The fields are:
-
-   pseudo-op name without dot
-   function to call to execute this pseudo-op
-   Integer arg to pass to the function  */
-
-#define OP_BCC	0x90
-#define OP_BCS	0xB0
-#define OP_BEQ	0xF0
-#define OP_BMI	0x30
-#define OP_BNE	0xD0
-#define OP_BPL	0x10
-#define OP_BRA	0x80
-#define OP_BRL	0x82
-#define OP_BVC	0x50
-#define OP_BVS	0x70
-
-static void s_longa PARAMS ((int));
-static char *parse_exp PARAMS ((char *));
-static char *get_operands PARAMS ((const struct opinfo *, char *));
-static const struct opinfo *get_specific PARAMS ((const struct opinfo *));
-static void build_Mytes PARAMS ((const struct opinfo *));
-
-
-const pseudo_typeS md_pseudo_table[] = {
-  {"int", cons, 2},
-  {"word", cons, 2},
-  {"longa", s_longa, 0},
-  {"longi", s_longa, 1},
-  {0, 0, 0}
-};
-
-#if 0
-int md_reloc_size;
-#endif
-
-const char EXP_CHARS[] = "eE";
-
-/* Chars that mean this number is a floating point constant.  */
-/* As in 0f12.456 */
-/* or    0d1.2345e12 */
-const char FLT_CHARS[] = "rRsSfFdDxXpP";
-
-/* Opcode mnemonics */
-static struct hash_control *opcode_hash_control;
-
-int M;				/* M flag */
-int X;				/* X flag */
-
-#define C(a,b) ENCODE_RELAX(a,b)
-#define ENCODE_RELAX(what,length) (((what) << 2) + (length))
-
-#define GET_WHAT(x) ((x>>2))
-
-#define BYTE_DISP 1
-#define WORD_DISP 2
-#define UNDEF_BYTE_DISP 0
-#define UNDEF_WORD_DISP 3
-
-#define COND_BRANCH 	1
-#define UNCOND_BRANCH   2
-#define END 	3
-
-#define BYTE_F 127		/* How far we can branch forwards */
-#define BYTE_B -126		/* How far we can branch backwards */
-#define WORD_F 32767
-#define WORD_B 32768
-
-relax_typeS md_relax_table[C (END, 0)] = {
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-  { 0, 0, 0, 0 },
-
-  /* COND_BRANCH */
-  { 0,       0,       0,  0 },				/* UNDEF_BYTE_DISP */
-  { BYTE_F,  BYTE_B,  2,  C (COND_BRANCH, WORD_DISP) },	/* BYTE_DISP */
-  { WORD_F,  WORD_B,  5,  0 },				/* WORD_DISP */
-  { 0,       0,       5,  0 },				/* UNDEF_WORD_DISP */
-
-  /* UNCOND_BRANCH */
-  { 0,       0,       0,  0 },				  /* UNDEF_BYTE_DISP */
-  { BYTE_F,  BYTE_B,  2,  C (UNCOND_BRANCH, WORD_DISP) }, /* BYTE_DISP */
-  { WORD_F,  WORD_B,  3,  0 },				  /* WORD_DISP */
-  { 0,       0,       3,  0 }				  /* UNDEF_WORD_DISP */
-
-};
-
-/* This function is called once, at assembler startup time.  This
-   should set up all the tables, etc that the MD part of the assembler
-   needs.  */
-
-static void
-s_longa (xmode)
-     int xmode;
-{
-  int *p = xmode ? &X : &M;
-  while (*input_line_pointer == ' ')
-    input_line_pointer++;
-  if (strncmp (input_line_pointer, "on", 2) == 0)
-    {
-      input_line_pointer += 2;
-      *p = 0;
-    }
-  else if (strncmp (input_line_pointer, "off", 3) == 0)
-    {
-      *p = 1;
-      input_line_pointer += 3;
-    }
-  else
-    as_bad (_("need on or off."));
-  demand_empty_rest_of_line ();
-}
-
-void
-md_begin ()
-{
-  const struct opinfo *opcode;
-  char *prev_name = "";
-
-  opcode_hash_control = hash_new ();
-
-  /* Insert unique names into hash table.  */
-  for (opcode = optable; opcode->name; opcode++)
-    {
-      if (strcmp (prev_name, opcode->name))
-	{
-	  prev_name = opcode->name;
-	  hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
-	}
-    }
-
-  flag_signed_overflow_ok = 1;
-}
-
-static expressionS immediate;	/* absolute expression */
-static expressionS immediate1;	/* absolute expression */
-int expr_size;
-int expr_shift;
-int tc_cons_reloc;
-
-void
-w65_expression (dest)
-     expressionS *dest;
-{
-  expr_size = 0;
-  expr_shift = 0;
-  tc_cons_reloc = 0;
-  while (*input_line_pointer == ' ')
-    input_line_pointer++;
-
-  if (*input_line_pointer == '<')
-    {
-      expr_size = 1;
-      input_line_pointer++;
-    }
-  else if (*input_line_pointer == '>')
-    {
-      expr_shift = 1;
-      input_line_pointer++;
-    }
-  else if (*input_line_pointer == '^')
-    {
-      expr_shift = 2;
-      input_line_pointer++;
-    }
-
-  expr (0, dest);
-}
-
-int amode;
-
-static char *
-parse_exp (s)
-     char *s;
-{
-  char *save;
-  char *new;
-
-  save = input_line_pointer;
-  input_line_pointer = s;
-  w65_expression (&immediate);
-  if (immediate.X_op == O_absent)
-    as_bad (_("missing operand"));
-  new = input_line_pointer;
-  input_line_pointer = save;
-  return new;
-}
-
-static char *
-get_operands (info, ptr)
-     const struct opinfo *info;
-     char *ptr;
-{
-  register int override_len = 0;
-  register int bytes = 0;
-
-  while (*ptr == ' ')
-    ptr++;
-
-  if (ptr[0] == '#')
-    {
-      ptr++;
-      switch (info->amode)
-	{
-	case ADDR_IMMTOI:
-	  bytes = X ? 1 : 2;
-	  amode = ADDR_IMMTOI;
-	  break;
-	case ADDR_IMMTOA:
-	  bytes = M ? 1 : 2;
-	  amode = ADDR_IMMTOA;
-	  break;
-	case ADDR_IMMCOP:
-	  bytes = 1;
-	  amode = ADDR_IMMCOP;
-	  break;
-	case ADDR_DIR:
-	  bytes = 2;
-	  amode = ADDR_ABS;
-	  break;
-	default:
-	  abort ();
-	  break;
-	}
-      ptr = parse_exp (ptr);
-    }
-  else if (ptr[0] == '!')
-    {
-      ptr = parse_exp (ptr + 1);
-      if (ptr[0] == ',')
-	{
-	  if (ptr[1] == 'y')
-	    {
-	      amode = ADDR_ABS_IDX_Y;
-	      bytes = 2;
-	      ptr += 2;
-	    }
-	  else if (ptr[1] == 'x')
-	    {
-	      amode = ADDR_ABS_IDX_X;
-	      bytes = 2;
-	      ptr += 2;
-	    }
-	  else
-	    {
-	      as_bad (_("syntax error after <exp"));
-	    }
-	}
-      else
-	{
-	  amode = ADDR_ABS;
-	  bytes = 2;
-	}
-    }
-  else if (ptr[0] == '>')
-    {
-      ptr = parse_exp (ptr + 1);
-      if (ptr[0] == ',' && ptr[1] == 'x')
-	{
-	  amode = ADDR_ABS_LONG_IDX_X;
-	  bytes = 3;
-	  ptr += 2;
-	}
-      else
-	{
-	  amode = ADDR_ABS_LONG;
-	  bytes = 3;
-	}
-    }
-  else if (ptr[0] == '<')
-    {
-      ptr = parse_exp (ptr + 1);
-      if (ptr[0] == ',')
-	{
-	  if (ptr[1] == 'y')
-	    {
-	      amode = ADDR_DIR_IDX_Y;
-	      ptr += 2;
-	      bytes = 2;
-	    }
-	  else if (ptr[1] == 'x')
-	    {
-	      amode = ADDR_DIR_IDX_X;
-	      ptr += 2;
-	      bytes = 2;
-	    }
-	  else
-	    {
-	      as_bad (_("syntax error after <exp"));
-	    }
-	}
-      else
-	{
-	  amode = ADDR_DIR;
-	  bytes = 1;
-	}
-    }
-  else if (ptr[0] == 'a')
-    {
-      amode = ADDR_ACC;
-    }
-  else if (ptr[0] == '(')
-    {
-      /* Look for (exp),y
-	 (<exp),y
-	 (exp,x)
-	 (<exp,x)
-	 (exp)
-	 (!exp)
-	 (exp)
-	 (<exp)
-	 (exp,x)
-	 (!exp,x)
-	 (exp,s)
-	 (exp,s),y */
-
-      ptr++;
-      if (ptr[0] == '<')
-	{
-	  override_len = 1;
-	  ptr++;
-	}
-      else if (ptr[0] == '!')
-	{
-	  override_len = 2;
-	  ptr++;
-	}
-      else if (ptr[0] == '>')
-	{
-	  override_len = 3;
-	  ptr++;
-	}
-      else
-	{
-	  override_len = 0;
-	}
-      ptr = parse_exp (ptr);
-
-      if (ptr[0] == ',')
-	{
-	  ptr++;
-	  if (ptr[0] == 'x' && ptr[1] == ')')
-	    {
-	      ptr += 2;
-
-	      if (override_len == 1)
-		{
-		  amode = ADDR_DIR_IDX_IND_X;
-		  bytes = 2;
-		}
-	      else
-		{
-		  amode = ADDR_ABS_IND_IDX;
-		  bytes = 2;
-		}
-	    }
-	  else if (ptr[0] == 's' && ptr[1] == ')'
-		   && ptr[2] == ',' && ptr[3] == 'y')
-	    {
-	      amode = ADDR_STACK_REL_INDX_IDX;
-	      bytes = 1;
-	      ptr += 4;
-	    }
-	}
-      else if (ptr[0] == ')')
-	{
-	  if (ptr[1] == ',' && ptr[2] == 'y')
-	    {
-	      amode = ADDR_DIR_IND_IDX_Y;
-	      ptr += 3;
-	      bytes = 2;
-	    }
-	  else
-	    {
-	      if (override_len == 1)
-		{
-		  amode = ADDR_DIR_IND;
-		  bytes = 1;
-		}
-	      else
-		{
-		  amode = ADDR_ABS_IND;
-		  bytes = 2;
-		}
-	      ptr++;
-
-	    }
-	}
-    }
-  else if (ptr[0] == '[')
-    {
-      ptr = parse_exp (ptr + 1);
-      if (ptr[0] == ']')
-	{
-	  ptr++;
-	  if (ptr[0] == ',' && ptr[1] == 'y')
-	    {
-	      bytes = 1;
-	      amode = ADDR_DIR_IND_IDX_Y_LONG;
-	      ptr += 2;
-	    }
-	  else
-	    {
-	      if (info->code == O_jmp)
-		{
-		  bytes = 2;
-		  amode = ADDR_ABS_IND_LONG;
-		}
-	      else
-		{
-		  bytes = 1;
-		  amode = ADDR_DIR_IND_LONG;
-		}
-	    }
-	}
-    }
-  else
-    {
-      ptr = parse_exp (ptr);
-      if (ptr[0] == ',')
-	{
-	  if (ptr[1] == 'y')
-	    {
-	      if (override_len == 1)
-		{
-		  bytes = 1;
-		  amode = ADDR_DIR_IDX_Y;
-		}
-	      else
-		{
-		  amode = ADDR_ABS_IDX_Y;
-		  bytes = 2;
-		}
-	      ptr += 2;
-	    }
-	  else if (ptr[1] == 'x')
-	    {
-	      if (override_len == 1)
-		{
-		  amode = ADDR_DIR_IDX_X;
-		  bytes = 1;
-		}
-	      else
-		{
-		  amode = ADDR_ABS_IDX_X;
-		  bytes = 2;
-		}
-	      ptr += 2;
-	    }
-	  else if (ptr[1] == 's')
-	    {
-	      bytes = 1;
-	      amode = ADDR_STACK_REL;
-	      ptr += 2;
-	    }
-	  else
-	    {
-	      bytes = 1;
-	      immediate1 = immediate;
-	      ptr = parse_exp (ptr + 1);
-	      amode = ADDR_BLOCK_MOVE;
-	    }
-	}
-      else
-	{
-	  switch (info->amode)
-	    {
-	    case ADDR_PC_REL:
-	      amode = ADDR_PC_REL;
-	      bytes = 1;
-	      break;
-	    case ADDR_PC_REL_LONG:
-	      amode = ADDR_PC_REL_LONG;
-	      bytes = 2;
-	      break;
-	    default:
-	      if (override_len == 1)
-		{
-		  amode = ADDR_DIR;
-		  bytes = 1;
-		}
-	      else if (override_len == 3)
-		{
-		  bytes = 3;
-		  amode = ADDR_ABS_LONG;
-		}
-	      else
-		{
-		  amode = ADDR_ABS;
-		  bytes = 2;
-		}
-	    }
-	}
-    }
-
-  switch (bytes)
-    {
-    case 1:
-      switch (expr_shift)
-	{
-	case 0:
-	  if (amode == ADDR_DIR)
-	    tc_cons_reloc = R_W65_DP;
-	  else
-	    tc_cons_reloc = R_W65_ABS8;
-	  break;
-	case 1:
-	  tc_cons_reloc = R_W65_ABS8S8;
-	  break;
-	case 2:
-	  tc_cons_reloc = R_W65_ABS8S16;
-	  break;
-	}
-      break;
-    case 2:
-      switch (expr_shift)
-	{
-	case 0:
-	  tc_cons_reloc = R_W65_ABS16;
-	  break;
-	case 1:
-	  tc_cons_reloc = R_W65_ABS16S8;
-	  break;
-	case 2:
-	  tc_cons_reloc = R_W65_ABS16S16;
-	  break;
-	}
-    }
-  return ptr;
-}
-
-/* Passed a pointer to a list of opcodes which use different
-   addressing modes, return the opcode which matches the opcodes
-   provided.  */
-
-static const struct opinfo *
-get_specific (opcode)
-     const struct opinfo *opcode;
-{
-  int ocode = opcode->code;
-
-  for (; opcode->code == ocode; opcode++)
-    {
-      if (opcode->amode == amode)
-	return opcode;
-    }
-  return 0;
-}
-
-/* Now we know what sort of opcodes it is, let's build the bytes.  */
-
-static void
-build_Mytes (opcode)
-     const struct opinfo *opcode;
-{
-  int size;
-  int type;
-  int pcrel;
-  char *output;
-
-  if (opcode->amode == ADDR_IMPLIED)
-    {
-      output = frag_more (1);
-    }
-  else if (opcode->amode == ADDR_PC_REL)
-    {
-      int type;
-
-      /* This is a relaxable insn, so we do some special handling.  */
-      type = opcode->val == OP_BRA ? UNCOND_BRANCH : COND_BRANCH;
-      output = frag_var (rs_machine_dependent,
-			 md_relax_table[C (type, WORD_DISP)].rlx_length,
-			 md_relax_table[C (type, BYTE_DISP)].rlx_length,
-			 C (type, UNDEF_BYTE_DISP),
-			 immediate.X_add_symbol,
-			 immediate.X_add_number,
-			 0);
-    }
-  else
-    {
-      switch (opcode->amode)
-	{
-	  GETINFO (size, type, pcrel);
-	default:
-	  abort ();
-	}
-
-      /* If something special was done in the expression modify the
-	 reloc type.  */
-      if (tc_cons_reloc)
-	type = tc_cons_reloc;
-
-      /* 1 byte for the opcode + the bytes for the addrmode.  */
-      output = frag_more (size + 1);
-
-      if (opcode->amode == ADDR_BLOCK_MOVE)
-	{
-	  /* Two relocs for this one.  */
-	  fix_new_exp (frag_now,
-		       output + 1 - frag_now->fr_literal,
-		       1,
-		       &immediate,
-		       0,
-		       R_W65_ABS8S16);
-
-	  fix_new_exp (frag_now,
-		       output + 2 - frag_now->fr_literal,
-		       1,
-		       &immediate1,
-		       0,
-		       R_W65_ABS8S16);
-	}
-      else if (type >= 0
-	       && opcode->amode != ADDR_IMPLIED
-	       && opcode->amode != ADDR_ACC
-	       && opcode->amode != ADDR_STACK)
-	{
-	  fix_new_exp (frag_now,
-		       output + 1 - frag_now->fr_literal,
-		       size,
-		       &immediate,
-		       pcrel,
-		       type);
-	}
-    }
-  output[0] = opcode->val;
-}
-
-/* This is the guts of the machine-dependent assembler.  STR points to
-   a machine dependent instruction.  This function is supposed to emit
-   the frags/bytes it assembles to.  */
-
-void
-md_assemble (str)
-     char *str;
-{
-  const struct opinfo *opcode;
-  char name[20];
-
-  /* Drop leading whitespace */
-  while (*str == ' ')
-    str++;
-
-  /* all opcodes are three letters */
-  name[0] = str[0];
-  name[1] = str[1];
-  name[2] = str[2];
-  name[3] = 0;
-
-  tc_cons_reloc = 0;
-  str += 3;
-  opcode = (struct opinfo *) hash_find (opcode_hash_control, name);
-
-  if (opcode == NULL)
-    {
-      as_bad (_("unknown opcode"));
-      return;
-    }
-
-  if (opcode->amode != ADDR_IMPLIED
-      && opcode->amode != ADDR_STACK)
-    {
-      get_operands (opcode, str);
-      opcode = get_specific (opcode);
-    }
-
-  if (opcode == 0)
-    {
-      /* Couldn't find an opcode which matched the operands.  */
-
-      char *where = frag_more (1);
-
-      where[0] = 0x0;
-      where[1] = 0x0;
-      as_bad (_("invalid operands for opcode"));
-      return;
-    }
-
-  build_Mytes (opcode);
-}
-
-symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-/* Various routines to kill one day.  */
-/* Equal to MAX_PRECISION in atof-ieee.c.  */
-#define MAX_LITTLENUMS 6
-
-/* Turn a string in input_line_pointer into a floating point constant
-   of type TYPE, and store the appropriate bytes in *LITP.  The number
-   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
-   returned, or NULL on OK.  */
-
-char *
-md_atof (type, litP, sizeP)
-     char type;
-     char *litP;
-     int *sizeP;
-{
-  int prec;
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-    case 's':
-    case 'S':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-    case 'r':
-    case 'R':
-      prec = 4;
-      break;
-
-    case 'x':
-    case 'X':
-      prec = 6;
-      break;
-
-    case 'p':
-    case 'P':
-      prec = 6;
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to MD_NTOF()");
-    }
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    input_line_pointer = t;
-
-  *sizeP = prec * sizeof (LITTLENUM_TYPE);
-  for (wordP = words + prec - 1; prec--;)
-    {
-      md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-  return 0;
-}
-
-int
-md_parse_option (c, a)
-     int c ATTRIBUTE_UNUSED;
-     char *a ATTRIBUTE_UNUSED;
-{
-  return 0;
-}
-
-/* Called after relaxing, change the frags so they know how big they
-   are.  */
-
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-{
-  int disp_size = 0;
-  int inst_size = 0;
-  unsigned char *buffer =
-    (unsigned char *) (fragP->fr_fix + fragP->fr_literal);
-
-  switch (fragP->fr_subtype)
-    {
-    case C (COND_BRANCH, BYTE_DISP):
-    case C (UNCOND_BRANCH, BYTE_DISP):
-      disp_size = 1;
-      inst_size = 1;
-      break;
-
-      /* Conditional branches to a known 16 bit displacement.  */
-    case C (COND_BRANCH, WORD_DISP):
-      switch (buffer[0])
-	{
-	case OP_BCC:
-	case OP_BCS:
-	case OP_BEQ:
-	case OP_BMI:
-	case OP_BNE:
-	case OP_BPL:
-	case OP_BVS:
-	case OP_BVC:
-	  /* Invert the sense of the test */
-	  buffer[0] ^= 0x20;
-	  buffer[1] = 3;	/* Jump over following brl */
-	  buffer[2] = OP_BRL;
-	  buffer[3] = 0;
-	  buffer[4] = 0;
-	  disp_size = 2;
-	  inst_size = 3;
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-    case C (UNCOND_BRANCH, WORD_DISP):
-      /* Unconditional branches to a known 16 bit displacement.  */
-
-      switch (buffer[0])
-	{
-	case OP_BRA:
-	  buffer[0] = OP_BRL;
-	  disp_size = 2;
-	  inst_size = 1;
-	  break;
-	default:
-	  abort ();
-	}
-      break;
-      /* Got to create a branch over a reloc here.  */
-    case C (COND_BRANCH, UNDEF_WORD_DISP):
-      buffer[0] ^= 0x20;	/* invert test */
-      buffer[1] = 3;
-      buffer[2] = OP_BRL;
-      buffer[3] = 0;
-      buffer[4] = 0;
-      fix_new (fragP,
-	       fragP->fr_fix + 3,
-	       4,
-	       fragP->fr_symbol,
-	       fragP->fr_offset,
-	       0,
-	       R_W65_PCR16);
-
-      fragP->fr_fix += disp_size + inst_size;
-      fragP->fr_var = 0;
-      break;
-    case C (UNCOND_BRANCH, UNDEF_WORD_DISP):
-      buffer[0] = OP_BRL;
-      buffer[1] = 0;
-      buffer[2] = 0;
-      fix_new (fragP,
-	       fragP->fr_fix + 1,
-	       4,
-	       fragP->fr_symbol,
-	       fragP->fr_offset,
-	       0,
-	       R_W65_PCR16);
-
-      fragP->fr_fix += disp_size + inst_size;
-      fragP->fr_var = 0;
-      break;
-    default:
-      abort ();
-    }
-  if (inst_size)
-    {
-      /* Get the address of the end of the instruction.  */
-      int next_inst = (fragP->fr_fix + fragP->fr_address
-		       + disp_size + inst_size);
-      int targ_addr = (S_GET_VALUE (fragP->fr_symbol) +
-		       fragP->fr_offset);
-      int disp = targ_addr - next_inst;
-
-      md_number_to_chars (buffer + inst_size, disp, disp_size);
-      fragP->fr_fix += disp_size + inst_size;
-      fragP->fr_var = 0;
-    }
-}
-
-valueT
-md_section_align (seg, size)
-     segT seg;
-     valueT size;
-{
-  return ((size + (1 << section_alignment[(int) seg]) - 1)
-	  & (-1 << section_alignment[(int) seg]));
-}
-
-void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT * valP;
-     segT seg ATTRIBUTE_UNUSED;
-{
-  long val = * (long *) valP;
-  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
-  int addr = fixP->fx_frag->fr_address + fixP->fx_where;
-
-  if (fixP->fx_r_type == 0)
-    {
-      if (fixP->fx_size == 1)
-	fixP->fx_r_type = R_W65_ABS8;
-      else
-	fixP->fx_r_type = R_W65_ABS16;
-    }
-
-  switch (fixP->fx_r_type)
-    {
-    case R_W65_ABS8S16:
-      val >>= 8;
-    case R_W65_ABS8S8:
-      val >>= 8;
-    case R_W65_ABS8:
-      *buf++ = val;
-      break;
-    case R_W65_ABS16S16:
-      val >>= 8;
-    case R_W65_ABS16S8:
-      val >>= 8;
-    case R_W65_ABS16:
-      *buf++ = val >> 0;
-      *buf++ = val >> 8;
-      break;
-    case R_W65_ABS24:
-      *buf++ = val >> 0;
-      *buf++ = val >> 8;
-      *buf++ = val >> 16;
-      break;
-    case R_W65_PCR8:
-      *buf++ = val - addr - 1;
-      break;
-    case R_W65_PCR16:
-      val = val - addr - 1;
-      *buf++ = val;
-      *buf++ = val >> 8;
-      break;
-    case R_W65_DP:
-      *buf++ = val;
-      break;
-
-    default:
-      abort ();
-    }
-
-  if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
-    fixP->fx_done = 1;
-}
-
-/* Put number into target byte order.  */
-
-void
-md_number_to_chars (ptr, use, nbytes)
-     char *ptr;
-     valueT use;
-     int nbytes;
-{
-  number_to_chars_littleendian (ptr, use, nbytes);
-}
-
-long
-md_pcrel_from (fixP)
-     fixS *fixP;
-{
-  int gap = fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address - 1;
-  return gap;
-}
-
-void
-tc_coff_symbol_emit_hook (x)
-     symbolS *x ATTRIBUTE_UNUSED;
-{
-}
-
-short
-tc_coff_fix2rtype (fix_ptr)
-     fixS *fix_ptr;
-{
-  return fix_ptr->fx_r_type;
-}
-
-void
-tc_reloc_mangle (fix_ptr, intr, base)
-     fixS *fix_ptr;
-     struct internal_reloc *intr;
-     bfd_vma base;
-
-{
-  symbolS *symbol_ptr;
-
-  symbol_ptr = fix_ptr->fx_addsy;
-
-  /* If this relocation is attached to a symbol then it's ok
-     to output it */
-  if (fix_ptr->fx_r_type == RELOC_32)
-    {
-      /* cons likes to create reloc32's whatever the size of the reloc..
-       */
-      switch (fix_ptr->fx_size)
-	{
-	case 2:
-	  intr->r_type = R_IMM16;
-	  break;
-	case 1:
-	  intr->r_type = R_IMM8;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  else
-    {
-      if (fix_ptr->fx_size == 4)
-	intr->r_type = R_W65_ABS24;
-      else
-	intr->r_type = fix_ptr->fx_r_type;
-    }
-
-  intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
-  intr->r_offset = fix_ptr->fx_offset;
-
-  /* Turn the segment of the symbol into an offset.  */
-  if (symbol_ptr)
-    {
-      symbolS *dot;
-
-      dot = segment_info[S_GET_SEGMENT (symbol_ptr)].dot;
-      if (dot)
-	{
-	  intr->r_offset += S_GET_VALUE (symbol_ptr);
-	  intr->r_symndx = dot->sy_number;
-	}
-      else
-	{
-	  intr->r_symndx = symbol_ptr->sy_number;
-	}
-    }
-  else
-    {
-      intr->r_symndx = -1;
-    }
-}
-
-int
-tc_coff_sizemachdep (frag)
-     fragS *frag;
-{
-  return md_relax_table[frag->fr_subtype].rlx_length;
-}
-
-/* Called just before address relaxation, return the length by which a
-   fragment must grow to reach it's destination.  */
-
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS *fragP;
-     register segT segment_type;
-{
-  int what;
-
-  switch (fragP->fr_subtype)
-    {
-    default:
-      abort ();
-
-    case C (COND_BRANCH, UNDEF_BYTE_DISP):
-    case C (UNCOND_BRANCH, UNDEF_BYTE_DISP):
-      what = GET_WHAT (fragP->fr_subtype);
-      /* Used to be a branch to somewhere which was unknown.  */
-      if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type)
-	{
-	  /* Got a symbol and it's defined in this segment, become byte
-	     sized - maybe it will fix up.  */
-	  fragP->fr_subtype = C (what, BYTE_DISP);
-	}
-      else
-	{
-	  /* Its got a segment, but its not ours, so it will always be
-             long.  */
-	  fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
-	}
-      break;
-
-    case C (COND_BRANCH, BYTE_DISP):
-    case C (COND_BRANCH, WORD_DISP):
-    case C (COND_BRANCH, UNDEF_WORD_DISP):
-    case C (UNCOND_BRANCH, BYTE_DISP):
-    case C (UNCOND_BRANCH, WORD_DISP):
-    case C (UNCOND_BRANCH, UNDEF_WORD_DISP):
-      /* When relaxing a section for the second time, we don't need to
-	 do anything besides return the current size.  */
-      break;
-    }
-
-  fragP->fr_var = md_relax_table[fragP->fr_subtype].rlx_length;
-  return fragP->fr_var;
-}
-
-const char *md_shortopts = "";
-struct option md_longopts[] = {
-#define OPTION_RELAX (OPTION_MD_BASE)
-  {NULL, no_argument, NULL, 0}
-};
-
-void
-md_show_usage (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
-{
-}
-
-size_t md_longopts_size = sizeof (md_longopts);
diff --git a/gas/config/tc-w65.h b/gas/config/tc-w65.h
deleted file mode 100644
index 2858b4f82e82..000000000000
--- a/gas/config/tc-w65.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* This file is tc-w65.h
-   Copyright 1995, 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define TC_W65
-
-#define TARGET_BYTES_BIG_ENDIAN 0
-
-#if ANSI_PROTOTYPES
-struct internal_reloc;
-struct fix;
-#endif
-
-#define WORKING_DOT_WORD
-
-/* This macro translates between an internal fix and a coff reloc type.  */
-#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype (fixP)
-
-#define BFD_ARCH bfd_arch_w65
-#define COFF_MAGIC 0x6500
-
-#define IGNORE_NONSTANDARD_ESCAPES
-
-#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle (a,b,c)
-extern void tc_reloc_mangle
-  PARAMS ((struct fix *, struct internal_reloc *, bfd_vma));
-
-#define DO_NOT_STRIP 0
-#define LISTING_HEADER "W65816 GAS "
-#define NEED_FX_R_TYPE 1
-#define RELOC_32 1234
-
-#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep (frag)
-int tc_coff_sizemachdep PARAMS ((fragS *));
-
-#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) w65_expression (EXP)
-void w65_expression PARAMS ((expressionS *));
-
-#define TC_COUNT_RELOC(x) (1)
-#define TC_CONS_RELOC tc_cons_reloc
-#define DONT_OVERFLOW
-int tc_cons_reloc;
-
-#define md_operand(x)
-
-extern struct relax_type md_relax_table[];
-#define TC_GENERIC_RELAX_TABLE md_relax_table
diff --git a/gas/config/tc-xc16x.c b/gas/config/tc-xc16x.c
new file mode 100644
index 000000000000..7a369b42ec29
--- /dev/null
+++ b/gas/config/tc-xc16x.c
@@ -0,0 +1,395 @@
+/* tc-xc16x.c -- Assembler for the Infineon XC16X.
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by KPIT Cummins Infosystems 
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+    along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+
+#include <stdio.h>
+#include "as.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "symcat.h"
+#include "opcodes/xc16x-desc.h"
+#include "opcodes/xc16x-opc.h"
+#include "cgen.h"
+#include "bfd.h"
+#include "dwarf2dbg.h"
+
+
+#ifdef OBJ_ELF
+#include "elf/xc16x.h"
+#endif
+
+/* Structure to hold all of the different components describing
+   an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int  			num_fixups;
+  fixS *		fixups [GAS_CGEN_MAX_FIXUPS];
+  int  			indices [MAX_OPERAND_INSTANCES];
+}
+xc16x_insn;
+
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
+const char line_separator_chars[] = "";
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+#define XC16X_SHORTOPTS ""
+const char * md_shortopts = XC16X_SHORTOPTS;
+
+struct option md_longopts[] =
+{
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+static void
+xc16xlmode (int arg ATTRIBUTE_UNUSED)
+{
+ if (stdoutput != NULL)
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xl))
+    as_warn (_("could not set architecture and machine"));
+}
+
+static void
+xc16xsmode (int arg ATTRIBUTE_UNUSED)
+{
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16xs))
+    as_warn (_("could not set architecture and machine"));
+}
+
+static void
+xc16xmode (int arg ATTRIBUTE_UNUSED)
+{
+  if (!bfd_set_arch_mach (stdoutput, bfd_arch_xc16x, bfd_mach_xc16x))
+    as_warn (_("could not set architecture and machine"));
+}
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "word",	cons,		2 },
+  {"xc16xl",  xc16xlmode,  0},
+  {"xc16xs", xc16xsmode, 0},
+  {"xc16x",  xc16xmode,  0},
+  { NULL, 	NULL, 		0 }
+};
+
+void
+md_begin (void)
+{
+  /* Initialize the `cgen' interface.  */
+
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
+					   CGEN_CPU_OPEN_ENDIAN,
+					   CGEN_ENDIAN_LITTLE,
+					   CGEN_CPU_OPEN_END);
+  xc16x_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+}
+
+void
+md_assemble (char *str)
+{
+  xc16x_insn insn;
+  char *errmsg;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  insn.insn = xc16x_cgen_assemble_insn
+    (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+  if (!insn.insn)
+    {
+      as_bad (errmsg);
+      return;
+    }
+
+  /* Doesn't really matter what we pass for RELAX_P here.  */
+  gas_cgen_finish_insn (insn.insn, insn.buffer,
+			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+}
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND *operand,
+		      fixS *fixP)
+{
+  switch (operand->type)
+    {
+    case XC16X_OPERAND_REL:
+      fixP->fx_where += 1;
+      fixP->fx_pcrel = 1;
+      return BFD_RELOC_8_PCREL;
+
+    case XC16X_OPERAND_CADDR:
+      fixP->fx_where += 2;
+      return BFD_RELOC_16;
+
+    case XC16X_OPERAND_UIMM7:
+      fixP->fx_where += 1;
+      fixP->fx_pcrel = 1;
+      return BFD_RELOC_8_PCREL;
+
+    case XC16X_OPERAND_UIMM16:
+    case XC16X_OPERAND_MEMORY:
+      fixP->fx_where += 2;
+      return BFD_RELOC_16;
+
+    case XC16X_OPERAND_UPOF16:
+      fixP->fx_where += 2;
+      return BFD_RELOC_XC16X_POF;
+
+    case XC16X_OPERAND_UPAG16:
+      fixP->fx_where += 2;
+      return BFD_RELOC_XC16X_PAG;
+
+    case XC16X_OPERAND_USEG8:
+      fixP->fx_where += 1;
+      return BFD_RELOC_XC16X_SEG;
+
+    case XC16X_OPERAND_USEG16:
+    case  XC16X_OPERAND_USOF16:
+      fixP->fx_where += 2;
+      return BFD_RELOC_XC16X_SOF;
+
+    default : /* avoid -Wall warning */
+      break;
+    }
+
+  fixP->fx_where += 2;
+  return BFD_RELOC_XC16X_SOF;
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+  number_to_chars_littleendian (buf, val, n);
+}
+
+void
+md_show_usage (FILE * stream)
+{
+  fprintf (stream, _(" XC16X specific command line options:\n"));
+}
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED,
+		 char *arg ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+/* Turn a string in input_line_pointer into a floating point constant
+   of type TYPE, and store the appropriate bytes in *LITP.  The number
+   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
+   returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  int i;
+  int prec;
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  char *t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+      /* FIXME: Some targets allow other format chars for bigger sizes
+         here.  */
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  *sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+   for (i = prec - 1; i >= 0; i--)
+     {
+       md_number_to_chars (litP, (valueT) words[i],
+			   sizeof (LITTLENUM_TYPE));
+       litP += sizeof (LITTLENUM_TYPE);
+     }
+
+  return NULL;
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return NULL;
+}
+
+int
+md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
+			       segT segment_type ATTRIBUTE_UNUSED)
+{
+  printf (_("call tomd_estimate_size_before_relax \n"));
+  abort ();
+}
+
+
+long
+md_pcrel_from (fixS *fixP)
+{
+  long temp_val;
+  temp_val=fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
+
+  return temp_val;
+}
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (! S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec
+          || S_IS_EXTERNAL (fixP->fx_addsy)
+          || S_IS_WEAK (fixP->fx_addsy)))
+    {
+      return 0;
+    }
+
+  return md_pcrel_from (fixP);
+}
+
+arelent *
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
+{
+  arelent *rel;
+  bfd_reloc_code_real_type r_type;
+
+  if (fixp->fx_addsy && fixp->fx_subsy)
+    {
+      if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
+	  || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
+	{
+	  as_bad_where (fixp->fx_file, fixp->fx_line,
+			"Difference of symbols in different sections is not supported");
+	  return NULL;
+	}
+    }
+
+  rel = xmalloc (sizeof (arelent));
+  rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  rel->addend = fixp->fx_offset;
+
+  r_type = fixp->fx_r_type;
+
+#define DEBUG 0
+#if DEBUG
+  fprintf (stderr, "%s\n", bfd_get_reloc_code_name (r_type));
+  fflush(stderr);
+#endif
+
+  rel->howto = bfd_reloc_type_lookup (stdoutput, r_type);
+   if (rel->howto == NULL)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("Cannot represent relocation type %s"),
+		    bfd_get_reloc_code_name (r_type));
+      return NULL;
+    }
+
+  return rel;
+}
+
+void
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
+{
+  if(!strstr (seg->name,".debug"))
+    {
+      if (*valP < 128)
+	*valP /= 2;
+      if (*valP>268435455)
+	{
+	  *valP = *valP * (-1);
+	  *valP /= 2;
+	  *valP = 256 - (*valP);
+	}
+    }
+  
+  gas_cgen_md_apply_fix (fixP, valP, seg);
+  return;
+}
+
+void
+md_convert_frag (bfd *headers ATTRIBUTE_UNUSED,
+		 segT seg ATTRIBUTE_UNUSED,
+		 fragS *fragP ATTRIBUTE_UNUSED)
+{
+  printf (_("call to md_convert_frag \n"));
+  abort ();
+}
+
+
diff --git a/gas/config/tc-xc16x.h b/gas/config/tc-xc16x.h
new file mode 100644
index 000000000000..aa510d8e1a59
--- /dev/null
+++ b/gas/config/tc-xc16x.h
@@ -0,0 +1,67 @@
+/* This file is tc-xc16x.h
+   Copyright 2006 Free Software Foundation, Inc.
+   Contributed by KPIT Cummins Infosystems 
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#define TC_XC16X
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_ARCH bfd_arch_xc16x
+
+#ifdef BFD_ASSEMBLER
+/* Fixup debug sections since we will never relax them.  */
+#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_ALLOC)
+#endif
+
+#ifdef OBJ_ELF
+#define TARGET_FORMAT       "elf32-xc16x"
+#define LOCAL_LABEL_PREFIX  '.'
+#define LOCAL_LABEL(NAME)   (NAME[0] == '.' && NAME[1] == 'L')
+#define FAKE_LABEL_NAME     ".L0\001"
+#endif
+
+#if ANSI_PROTOTYPES
+struct fix;
+struct internal_reloc;
+#endif
+
+#define WORKING_DOT_WORD
+
+#define BFD_ARCH bfd_arch_xc16x
+#define TC_COUNT_RELOC(x)  1
+#define IGNORE_NONSTANDARD_ESCAPES
+
+#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
+extern void tc_reloc_mangle (struct fix *, struct internal_reloc *, bfd_vma);
+
+/* No shared lib support, so we don't need to ensure externally
+   visible symbols can be overridden.  */
+#define EXTERN_FORCE_RELOC 0
+
+/* Minimum instruction is of 16 bits.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 2
+
+#define DO_NOT_STRIP 0
+#define LISTING_HEADER "Infineon XC16X GAS "
+#define NEED_FX_R_TYPE 1
+#define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define md_operand(x)
diff --git a/gas/config/tc-xstormy16.c b/gas/config/tc-xstormy16.c
index 83ae94d382aa..29e019942457 100644
--- a/gas/config/tc-xstormy16.c
+++ b/gas/config/tc-xstormy16.c
@@ -1,5 +1,5 @@
 /* tc-xstormy16.c -- Assembler for the Sanyo XSTORMY16.
-   Copyright 2000, 2001, 2002, 2003 Free Software Foundation.
+   Copyright 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #include <stdio.h>
 #include "as.h"
@@ -66,16 +66,14 @@ struct option md_longopts[] =
 size_t md_longopts_size = sizeof (md_longopts);
 
 int
-md_parse_option (c, arg)
-     int    c ATTRIBUTE_UNUSED;
-     char * arg ATTRIBUTE_UNUSED;
+md_parse_option (int    c ATTRIBUTE_UNUSED,
+		 char * arg ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 void
-md_show_usage (stream)
-  FILE * stream;
+md_show_usage (FILE * stream)
 {
   fprintf (stream, _(" XSTORMY16 specific command line options:\n"));
 }
@@ -89,7 +87,7 @@ const pseudo_typeS md_pseudo_table[] =
 
 
 void
-md_begin ()
+md_begin (void)
 {
   /* Initialize the `cgen' interface.  */
 
@@ -107,8 +105,7 @@ md_begin ()
 static bfd_boolean skipping_fptr = FALSE;
 
 void
-md_assemble (str)
-     char * str;
+md_assemble (char * str)
 {
   xstormy16_insn insn;
   char *    errmsg;
@@ -135,8 +132,7 @@ md_assemble (str)
 }
 
 void
-md_operand (e)
-     expressionS * e;
+md_operand (expressionS * e)
 {
   if (*input_line_pointer != '@')
     return;
@@ -195,24 +191,41 @@ md_operand (e)
    Create BFD_RELOC_XSTORMY16_FPTR16 relocations.  */
 
 void
-xstormy16_cons_fix_new (f, where, nbytes, exp)
-     fragS *f;
-     int where;
-     int nbytes;
-     expressionS *exp;
+xstormy16_cons_fix_new (fragS *f,
+			int where,
+			int nbytes,
+			expressionS *exp)
 {
   bfd_reloc_code_real_type code;
   fixS *fix;
 
   if (exp->X_op == O_fptr_symbol)
     {
-      if (nbytes != 2)
+      switch (nbytes)
 	{
+ 	case 4:
+ 	  /* This can happen when gcc is generating debug output.
+ 	     For example it can create a stab with the address of
+ 	     a function:
+ 	     
+ 	     	.stabs	"foo:F(0,21)",36,0,0,@fptr(foo)
+ 
+ 	     Since this does not involve switching code pages, we
+ 	     just allow the reloc to be generated without any
+ 	     @fptr behaviour.  */
+ 	  exp->X_op = O_symbol;
+ 	  code = BFD_RELOC_32;
+ 	  break;
+
+ 	case 2:
+ 	  exp->X_op = O_symbol;
+ 	  code = BFD_RELOC_XSTORMY16_FPTR16;
+ 	  break;
+
+ 	default:
 	  as_bad ("unsupported fptr fixup size %d", nbytes);
 	  return;
 	}
-      exp->X_op = O_symbol;
-      code = BFD_RELOC_XSTORMY16_FPTR16;
     }
   else if (nbytes == 1)
     code = BFD_RELOC_8;
@@ -233,14 +246,13 @@ xstormy16_cons_fix_new (f, where, nbytes, exp)
    Create BFD_RELOC_XSTORMY16_FPTR16 relocations.  */
 
 fixS *
-xstormy16_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp)
-     fragS *              frag;
-     int                  where;
-     const CGEN_INSN *    insn;
-     int                  length;
-     const CGEN_OPERAND * operand;
-     int                  opinfo;
-     expressionS *        exp;
+xstormy16_cgen_record_fixup_exp (fragS *              frag,
+				 int                  where,
+				 const CGEN_INSN *    insn,
+				 int                  length,
+				 const CGEN_OPERAND * operand,
+				 int                  opinfo,
+				 expressionS *        exp)
 {
   fixS *fixP;
   operatorT op = exp->X_op;
@@ -266,17 +278,15 @@ xstormy16_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp
 }
 
 valueT
-md_section_align (segment, size)
-     segT   segment;
-     valueT size;
+md_section_align (segT segment, valueT size)
 {
   int align = bfd_get_section_alignment (stdoutput, segment);
+
   return ((size + (1 << align) - 1) & (-1 << align));
 }
 
 symbolS *
-md_undefined_symbol (name)
-  char * name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -293,9 +303,8 @@ md_undefined_symbol (name)
    0 value.  */
 
 int
-md_estimate_size_before_relax (fragP, segment)
-     fragS * fragP ATTRIBUTE_UNUSED;
-     segT    segment ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+			       segT    segment ATTRIBUTE_UNUSED)
 {
   /* No assembler relaxation is defined (or necessary) for this port.  */
   abort ();
@@ -309,10 +318,9 @@ md_estimate_size_before_relax (fragP, segment)
    fragP->fr_subtype is the subtype of what the address relaxed to.  */
 
 void
-md_convert_frag (abfd, sec, fragP)
-  bfd *   abfd ATTRIBUTE_UNUSED;
-  segT    sec ATTRIBUTE_UNUSED;
-  fragS * fragP ATTRIBUTE_UNUSED;
+md_convert_frag (bfd *   abfd ATTRIBUTE_UNUSED,
+		 segT    sec ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
 {
   /* No assembler relaxation is defined (or necessary) for this port.  */
   abort ();
@@ -324,14 +332,12 @@ md_convert_frag (abfd, sec, fragP)
    given a PC relative reloc.  */
 
 long
-md_pcrel_from_section (fixP, sec)
-     fixS * fixP;
-     segT   sec;
+md_pcrel_from_section (fixS * fixP, segT sec)
 {
-  if (fixP->fx_addsy != (symbolS *) NULL
-      && (! S_IS_DEFINED (fixP->fx_addsy)
-	  || S_GET_SEGMENT (fixP->fx_addsy) != sec)
-          || xstormy16_force_relocation (fixP))
+  if ((fixP->fx_addsy != (symbolS *) NULL
+       && (! S_IS_DEFINED (fixP->fx_addsy)
+	   || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+      || xstormy16_force_relocation (fixP))
     /* The symbol is undefined,
        or it is defined but not in this section,
        or the relocation will be relative to this symbol not the section symbol.	 
@@ -346,10 +352,9 @@ md_pcrel_from_section (fixP, sec)
    *FIXP may be modified if desired.  */
 
 bfd_reloc_code_real_type
-md_cgen_lookup_reloc (insn, operand, fixP)
-     const CGEN_INSN *    insn ATTRIBUTE_UNUSED;
-     const CGEN_OPERAND * operand;
-     fixS *               fixP;
+md_cgen_lookup_reloc (const CGEN_INSN *    insn ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP)
 {
   switch (operand->type)
     {
@@ -403,8 +408,7 @@ md_cgen_lookup_reloc (insn, operand, fixP)
    relaxing.  */
 
 int
-xstormy16_force_relocation (fix)
-     fixS * fix;
+xstormy16_force_relocation (fixS * fix)
 {
   if (fix->fx_r_type == BFD_RELOC_XSTORMY16_FPTR16)
     return 1;
@@ -416,28 +420,26 @@ xstormy16_force_relocation (fix)
    a relocation against section+offset.  */
 
 bfd_boolean
-xstormy16_fix_adjustable (fixP)
-   fixS * fixP;
+xstormy16_fix_adjustable (fixS * fixP)
 {
   /* We need the symbol name for the VTABLE entries.  */
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
-    return 0;
+    return FALSE;
 
   if (fixP->fx_r_type == BFD_RELOC_XSTORMY16_FPTR16)
-    return 0;
+    return FALSE;
 
-  return 1;
+  return TRUE;
 }
 
-/* This is a copy of gas_cgen_md_apply_fix3, with some enhancements to
+/* This is a copy of gas_cgen_md_apply_fix, with some enhancements to
    do various things that would not be valid for all ports.  */
 
 void
-xstormy16_md_apply_fix3 (fixP, valueP, seg)
-     fixS *   fixP;
-     valueT * valueP;
-     segT     seg ATTRIBUTE_UNUSED;
+xstormy16_md_apply_fix (fixS *   fixP,
+			 valueT * valueP,
+			 segT     seg ATTRIBUTE_UNUSED)
 {
   char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
   valueT value = *valueP;
@@ -454,8 +456,7 @@ xstormy16_md_apply_fix3 (fixP, valueP, seg)
      it must deal with turning a BFD_RELOC_{8,16,32,64} into a
      BFD_RELOC_*_PCREL for the case of
 
-	.word something-.
-  */
+	.word something-.  */
   if (fixP->fx_pcrel)
     switch (fixP->fx_r_type)
       {
@@ -501,17 +502,19 @@ xstormy16_md_apply_fix3 (fixP, valueP, seg)
 #if CGEN_INT_INSN_P
 	  {
 	    CGEN_INSN_INT insn_value =
-	      cgen_get_insn_value (cd, where, CGEN_INSN_BITSIZE (insn));
+	      cgen_get_insn_value (cd, (unsigned char *) where,
+				   CGEN_INSN_BITSIZE (insn));
 
 	    /* ??? 0 is passed for `pc'.  */
 	    errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields,
 						   &insn_value, (bfd_vma) 0);
-	    cgen_put_insn_value (cd, where, CGEN_INSN_BITSIZE (insn),
-				 insn_value);
+	    cgen_put_insn_value (cd, (unsigned char *) where,
+				 CGEN_INSN_BITSIZE (insn), insn_value);
 	  }
 #else
 	  /* ??? 0 is passed for `pc'.  */
-	  errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields, where,
+	  errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields,
+						 (unsigned char *) where,
 						 (bfd_vma) 0);
 #endif
 	  if (errmsg)
@@ -528,9 +531,7 @@ xstormy16_md_apply_fix3 (fixP, valueP, seg)
 
       reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
       if (reloc_type != BFD_RELOC_NONE)
-	{
-	  fixP->fx_r_type = reloc_type;
-	}
+	fixP->fx_r_type = reloc_type;
       else
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -590,10 +591,7 @@ xstormy16_md_apply_fix3 (fixP, valueP, seg)
 /* Write a value out to the object file, using the appropriate endianness.  */
 
 void
-md_number_to_chars (buf, val, n)
-     char * buf;
-     valueT val;
-     int    n;
+md_number_to_chars (char * buf, valueT val, int n)
 {
   number_to_chars_littleendian (buf, val, n);
 }
@@ -607,10 +605,7 @@ md_number_to_chars (buf, val, n)
 #define MAX_LITTLENUMS 6
 
 char *
-md_atof (type, litP, sizeP)
-     char   type;
-     char * litP;
-     int *  sizeP;
+md_atof (int type, char * litP, int * sizeP)
 {
   int              prec;
   LITTLENUM_TYPE   words [MAX_LITTLENUMS];
diff --git a/gas/config/tc-xstormy16.h b/gas/config/tc-xstormy16.h
index cd0ebb96dc65..542587452a4c 100644
--- a/gas/config/tc-xstormy16.h
+++ b/gas/config/tc-xstormy16.h
@@ -1,5 +1,5 @@
 /* tc-xstormy16.h -- Header file for tc-xstormy16.c.
-   Copyright 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 2000, 2001, 2002, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,16 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
 #define TC_XSTORMY16
 
-#ifndef BFD_ASSEMBLER
-/* leading space so will compile with cc */
- #error XSTORMY16 support requires BFD_ASSEMBLER
-#endif
-
 #define LISTING_HEADER "XSTORMY16 GAS "
 
 /* The target BFD architecture.  */
@@ -37,21 +32,21 @@
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
 
-#define DIFF_EXPR_OK		/* foo-. gets turned into PC relative relocs */
+#define DIFF_EXPR_OK		/* foo-. gets turned into PC relative relocs.  */
 
 /* We don't need to handle .word strangely.  */
 #define WORKING_DOT_WORD
 
-/* Values passed to md_apply_fix3 don't include the symbol value.  */
+/* Values passed to md_apply_fix don't include the symbol value.  */
 #define MD_APPLY_SYM_VALUE(FIX) 0
 
-#define md_apply_fix3 xstormy16_md_apply_fix3
+#define md_apply_fix xstormy16_md_apply_fix
 
 #define tc_fix_adjustable(FIX) xstormy16_fix_adjustable (FIX)
-extern bfd_boolean xstormy16_fix_adjustable PARAMS ((struct fix *));
+extern bfd_boolean xstormy16_fix_adjustable (struct fix *);
 
 #define TC_FORCE_RELOCATION(fix) xstormy16_force_relocation (fix)
-extern int xstormy16_force_relocation PARAMS ((struct fix *));
+extern int xstormy16_force_relocation (struct fix *);
 
 #define TC_HANDLES_FX_DONE
 
@@ -59,10 +54,10 @@ extern int xstormy16_force_relocation PARAMS ((struct fix *));
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from_section (FIX, SEC)
-extern long md_pcrel_from_section PARAMS ((struct fix *, segT));
+extern long md_pcrel_from_section (struct fix *, segT);
 
 #define TC_CONS_FIX_NEW xstormy16_cons_fix_new
-extern void xstormy16_cons_fix_new PARAMS ((fragS *f, int, int, expressionS *));
+extern void xstormy16_cons_fix_new (fragS *f, int, int, expressionS *);
 
 #define md_cgen_record_fixup_exp  xstormy16_cgen_record_fixup_exp
 
diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c
index 6f9198a23cee..d7f059e6f5ea 100644
--- a/gas/config/tc-xtensa.c
+++ b/gas/config/tc-xtensa.c
@@ -1,5 +1,5 @@
 /* tc-xtensa.c -- Assemble Xtensa instructions.
-   Copyright 2003 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,10 +15,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 
-   MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #include <string.h>
+#include <limits.h>
 #include "as.h"
 #include "sb.h"
 #include "safe-ctype.h"
@@ -40,13 +41,6 @@
 
 /* Notes:
 
-   There are 3 forms for instructions,
-   1) the MEMORY format -- this is the encoding 2 or 3 byte instruction
-   2) the TInsn -- handles instructions/labels and literals;
-      all operands are assumed to be expressions
-   3) the IStack -- a stack of TInsn.  this allows us to 
-      reason about the generated expansion instructions
-  
    Naming conventions (used somewhat inconsistently):
       The xtensa_ functions are exported
       The xg_ functions are internal
@@ -71,17 +65,25 @@ const char EXP_CHARS[] = "eE";
 const char FLT_CHARS[] = "rRsSfFdDxXpP";
 
 
-/* Flag to indicate whether the hardware supports the density option.
-   If not, enabling density instructions (via directives or --density flag)
-   is illegal.  */
+/* Flags to indicate whether the hardware supports the density and
+   absolute literals options.  */
 
-#if STATIC_LIBISA
 bfd_boolean density_supported = XCHAL_HAVE_DENSITY;
-#else
-bfd_boolean density_supported = TRUE;
-#endif
+bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS;
+
+/* Maximum width we would pad an unreachable frag to get alignment.  */
+#define UNREACHABLE_MAX_WIDTH  8
+
+static vliw_insn cur_vinsn;
 
-#define XTENSA_FETCH_WIDTH 4
+unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH;
+
+static enum debug_info_type xt_saved_debug_type = DEBUG_NONE;
+
+/* Some functions are only valid in the front end.  This variable
+   allows us to assert that we haven't crossed over into the
+   back end.  */
+static bfd_boolean past_xtensa_end = FALSE;
 
 /* Flags for properties of the last instruction in a segment.  */
 #define FLAG_IS_A0_WRITER	0x1
@@ -94,21 +96,24 @@ bfd_boolean density_supported = TRUE;
    their own special .fini.literal and .init.literal sections.  */
 
 #define LITERAL_SECTION_NAME		xtensa_section_rename (".literal")
+#define LIT4_SECTION_NAME		xtensa_section_rename (".lit4")
 #define FINI_SECTION_NAME		xtensa_section_rename (".fini")
 #define INIT_SECTION_NAME		xtensa_section_rename (".init")
 #define FINI_LITERAL_SECTION_NAME	xtensa_section_rename (".fini.literal")
 #define INIT_LITERAL_SECTION_NAME	xtensa_section_rename (".init.literal")
 
 
-/* This type is used for the directive_stack to keep track of the 
+/* This type is used for the directive_stack to keep track of the
    state of the literal collection pools.  */
 
 typedef struct lit_state_struct
 {
   const char *lit_seg_name;
+  const char *lit4_seg_name;
   const char *init_lit_seg_name;
   const char *fini_lit_seg_name;
   segT lit_seg;
+  segT lit4_seg;
   segT init_lit_seg;
   segT fini_lit_seg;
 } lit_state;
@@ -153,9 +158,145 @@ static sym_list *saved_insn_labels = NULL;
 static sym_list *literal_syms;
 
 
+/* Flags to determine whether to prefer const16 or l32r
+   if both options are available.  */
+int prefer_const16 = 0;
+int prefer_l32r = 0;
+
 /* Global flag to indicate when we are emitting literals.  */
 int generating_literals = 0;
 
+/* The following PROPERTY table definitions are copied from
+   <elf/xtensa.h> and must be kept in sync with the code there.  */
+
+/* Flags in the property tables to specify whether blocks of memory
+   are literals, instructions, data, or unreachable.  For
+   instructions, blocks that begin loop targets and branch targets are
+   designated.  Blocks that do not allow density, instruction
+   reordering or transformation are also specified.  Finally, for
+   branch targets, branch target alignment priority is included.
+   Alignment of the next block is specified in the current block
+   and the size of the current block does not include any fill required
+   to align to the next block.  */
+
+#define XTENSA_PROP_LITERAL		0x00000001
+#define XTENSA_PROP_INSN		0x00000002
+#define XTENSA_PROP_DATA		0x00000004
+#define XTENSA_PROP_UNREACHABLE		0x00000008
+/* Instruction only properties at beginning of code.  */
+#define XTENSA_PROP_INSN_LOOP_TARGET	0x00000010
+#define XTENSA_PROP_INSN_BRANCH_TARGET	0x00000020
+/* Instruction only properties about code.  */
+#define XTENSA_PROP_INSN_NO_DENSITY	0x00000040
+#define XTENSA_PROP_INSN_NO_REORDER	0x00000080
+#define XTENSA_PROP_INSN_NO_TRANSFORM	0x00000100
+
+/*  Branch target alignment information.  This transmits information
+    to the linker optimization about the priority of aligning a
+    particular block for branch target alignment: None, low priority,
+    high priority, or required.  These only need to be checked in
+    instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET.
+    Common usage is
+
+    switch (GET_XTENSA_PROP_BT_ALIGN (flags))
+    case XTENSA_PROP_BT_ALIGN_NONE:
+    case XTENSA_PROP_BT_ALIGN_LOW:
+    case XTENSA_PROP_BT_ALIGN_HIGH:
+    case XTENSA_PROP_BT_ALIGN_REQUIRE:
+*/
+#define XTENSA_PROP_BT_ALIGN_MASK       0x00000600
+
+/* No branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_NONE       0x0
+/* Low priority branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_LOW        0x1
+/* High priority branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_HIGH       0x2
+/* Required branch target alignment.  */
+#define XTENSA_PROP_BT_ALIGN_REQUIRE    0x3
+
+#define GET_XTENSA_PROP_BT_ALIGN(flag) \
+  (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9)
+#define SET_XTENSA_PROP_BT_ALIGN(flag, align) \
+  (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \
+    (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK))
+
+
+/* Alignment is specified in the block BEFORE the one that needs
+   alignment.  Up to 5 bits.  Use GET_XTENSA_PROP_ALIGNMENT(flags) to
+   get the required alignment specified as a power of 2.  Use
+   SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required
+   alignment.  Be careful of side effects since the SET will evaluate
+   flags twice.  Also, note that the SIZE of a block in the property
+   table does not include the alignment size, so the alignment fill
+   must be calculated to determine if two blocks are contiguous.
+   TEXT_ALIGN is not currently implemented but is a placeholder for a
+   possible future implementation.  */
+
+#define XTENSA_PROP_ALIGN		0x00000800
+
+#define XTENSA_PROP_ALIGNMENT_MASK      0x0001f000
+
+#define GET_XTENSA_PROP_ALIGNMENT(flag) \
+  (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12)
+#define SET_XTENSA_PROP_ALIGNMENT(flag, align) \
+  (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \
+    (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK))
+
+#define XTENSA_PROP_INSN_ABSLIT 0x00020000
+
+
+/* Structure for saving instruction and alignment per-fragment data
+   that will be written to the object file.  This structure is
+   equivalent to the actual data that will be written out to the file
+   but is easier to use.   We provide a conversion to file flags
+   in frag_flags_to_number.  */
+
+typedef struct frag_flags_struct frag_flags;
+
+struct frag_flags_struct
+{
+  /* is_literal should only be used after xtensa_move_literals.
+     If you need to check if you are generating a literal fragment,
+     then use the generating_literals global.  */
+
+  unsigned is_literal : 1;
+  unsigned is_insn : 1;
+  unsigned is_data : 1;
+  unsigned is_unreachable : 1;
+
+  struct
+  {
+    unsigned is_loop_target : 1;
+    unsigned is_branch_target : 1; /* Branch targets have a priority.  */
+    unsigned bt_align_priority : 2;
+
+    unsigned is_no_density : 1;
+    /* no_longcalls flag does not need to be placed in the object file.  */
+    /* is_specific_opcode implies no_transform.  */
+    unsigned is_no_transform : 1;
+
+    unsigned is_no_reorder : 1;
+
+    /* Uses absolute literal addressing for l32r.  */
+    unsigned is_abslit : 1;
+  } insn;
+  unsigned is_align : 1;
+  unsigned alignment : 5;
+};
+
+
+/* Structure for saving information about a block of property data
+   for frags that have the same flags.  */
+struct xtensa_block_info_struct
+{
+  segT sec;
+  bfd_vma offset;
+  size_t size;
+  frag_flags flags;
+  struct xtensa_block_info_struct *next;
+};
+
 
 /* Structure for saving the current state before emitting literals.  */
 typedef struct emit_state_struct
@@ -167,6 +308,53 @@ typedef struct emit_state_struct
 } emit_state;
 
 
+/* Opcode placement information */
+
+typedef unsigned long long bitfield;
+#define bit_is_set(bit, bf)	((bf) & (0x01ll << (bit)))
+#define set_bit(bit, bf)	((bf) |= (0x01ll << (bit)))
+#define clear_bit(bit, bf)	((bf) &= ~(0x01ll << (bit)))
+
+#define MAX_FORMATS 32
+
+typedef struct op_placement_info_struct
+{
+  int num_formats;
+  /* A number describing how restrictive the issue is for this
+     opcode.  For example, an opcode that fits lots of different
+     formats has a high freedom, as does an opcode that fits
+     only one format but many slots in that format.  The most
+     restrictive is the opcode that fits only one slot in one
+     format.  */
+  int issuef;
+  xtensa_format narrowest;
+  char narrowest_size;
+  char narrowest_slot;
+
+  /* formats is a bitfield with the Nth bit set
+     if the opcode fits in the Nth xtensa_format.  */
+  bitfield formats;
+
+  /* slots[N]'s Mth bit is set if the op fits in the
+     Mth slot of the Nth xtensa_format.  */
+  bitfield slots[MAX_FORMATS];
+
+  /* A count of the number of slots in a given format
+     an op can fit (i.e., the bitcount of the slot field above).  */
+  char slots_in_format[MAX_FORMATS];
+
+} op_placement_info, *op_placement_info_table;
+
+op_placement_info_table op_placement_table;
+
+
+/* Extra expression types.  */
+
+#define O_pltrel	O_md1	/* like O_symbol but use a PLT reloc */
+#define O_hi16		O_md2	/* use high 16 bits of symbolic value */
+#define O_lo16		O_md3	/* use low 16 bits of symbolic value */
+
+
 /* Directives.  */
 
 typedef enum
@@ -174,11 +362,13 @@ typedef enum
   directive_none = 0,
   directive_literal,
   directive_density,
-  directive_generics,
-  directive_relax,
+  directive_transform,
   directive_freeregs,
   directive_longcalls,
-  directive_literal_prefix
+  directive_literal_prefix,
+  directive_schedule,
+  directive_absolute_literals,
+  directive_last_directive
 } directiveE;
 
 typedef struct
@@ -189,539 +379,143 @@ typedef struct
 
 const directive_infoS directive_info[] =
 {
-  {"none",	FALSE},
-  {"literal",	FALSE},
-  {"density",	TRUE},
-  {"generics",	TRUE},
-  {"relax",	TRUE},
-  {"freeregs",	FALSE},
-  {"longcalls",	TRUE},
-  {"literal_prefix", FALSE}
+  { "none",		FALSE },
+  { "literal",		FALSE },
+  { "density",		TRUE },
+  { "transform",	TRUE },
+  { "freeregs",		FALSE },
+  { "longcalls",	TRUE },
+  { "literal_prefix",	FALSE },
+  { "schedule",		TRUE },
+  { "absolute-literals", TRUE }
 };
 
 bfd_boolean directive_state[] =
 {
   FALSE,			/* none */
   FALSE,			/* literal */
-#if STATIC_LIBISA && !XCHAL_HAVE_DENSITY
+#if !XCHAL_HAVE_DENSITY
   FALSE,			/* density */
 #else
   TRUE,				/* density */
 #endif
-  TRUE,				/* generics */
-  TRUE,				/* relax */
+  TRUE,				/* transform */
   FALSE,			/* freeregs */
   FALSE,			/* longcalls */
-  FALSE				/* literal_prefix */
-};
-
-
-enum xtensa_relax_statesE
-{
-  RELAX_ALIGN_NEXT_OPCODE,
-  /* Use the first opcode of the next fragment to determine the
-     alignment requirements.  This is ONLY used for LOOPS
-     currently.  */
-
-  RELAX_DESIRE_ALIGN_IF_TARGET,
-  /* These are placed in front of labels.  They will all be converted
-     to RELAX_DESIRE_ALIGN / RELAX_LOOP_END or rs_fill of 0 before
-     relaxation begins.  */
-
-  RELAX_ADD_NOP_IF_A0_B_RETW,
-  /* These are placed in front of conditional branches.  It will be
-     turned into a NOP (using a1) if the branch is immediately
-     followed by a RETW or RETW.N.  Otherwise it will be turned into
-     an rs_fill of 0 before relaxation begins.  */
-
-  RELAX_ADD_NOP_IF_PRE_LOOP_END,
-  /* These are placed after JX instructions.  It will be turned into a
-     NOP if there is one instruction before a loop end label.
-     Otherwise it will be turned into an rs_fill of 0 before
-     relaxation begins.  This is used to avoid a hardware TIE
-     interlock issue prior to T1040.  */
-
-  RELAX_ADD_NOP_IF_SHORT_LOOP,
-  /* These are placed after LOOP instructions.  It will be turned into
-     a NOP when: (1) there are less than 3 instructions in the loop;
-     we place 2 of these in a row to add up to 2 NOPS in short loops;
-     or (2) The instructions in the loop do not include a branch or
-     jump.  Otherwise it will be turned into an rs_fill of 0 before
-     relaxation begins.  This is used to avoid hardware bug
-     PR3830.  */
-
-  RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
-  /* These are placed after LOOP instructions.  It will be turned into
-     a NOP if there are less than 12 bytes to the end of some other
-     loop's end.  Otherwise it will be turned into an rs_fill of 0
-     before relaxation begins.  This is used to avoid hardware bug
-     PR3830.  */
-
-  RELAX_DESIRE_ALIGN,
-  /* The next fragment like its first instruction to NOT cross a
-     4-byte boundary.  */
-
-  RELAX_LOOP_END,
-  /* This will be turned into a NOP or NOP.N if the previous
-     instruction is expanded to negate a loop.  */
-
-  RELAX_LOOP_END_ADD_NOP,
-  /* When the code density option is available, this will generate a
-     NOP.N marked RELAX_NARROW.  Otherwise, it will create an rs_fill
-     fragment with a NOP in it.  */
-
-  RELAX_LITERAL,
-  /* Another fragment could generate an expansion here but has not yet.  */
-
-  RELAX_LITERAL_NR,
-  /* Expansion has been generated by an instruction that generates a
-     literal.  However, the stretch has NOT been reported yet in this
-     fragment.  */
-
-  RELAX_LITERAL_FINAL,
-  /* Expansion has been generated by an instruction that generates a
-     literal.  */
-
-  RELAX_LITERAL_POOL_BEGIN,
-  RELAX_LITERAL_POOL_END,
-  /* Technically these are not relaxations at all, but mark a location
-     to store literals later.  Note that fr_var stores the frchain for
-     BEGIN frags and fr_var stores now_seg for END frags.  */
-
-  RELAX_NARROW,
-  /* The last instruction in this fragment (at->fr_opcode) can be
-     freely replaced with a single wider instruction if a future
-     alignment desires or needs it.  */
-
-  RELAX_IMMED,
-  /* The last instruction in this fragment (at->fr_opcode) contains
-     the value defined by fr_symbol (fr_offset = 0).  If the value
-     does not fit, use the specified expansion.  This is similar to
-     "NARROW", except that these may not be expanded in order to align
-     code.  */
-  
-  RELAX_IMMED_STEP1,
-  /* The last instruction in this fragment (at->fr_opcode) contains a
-     literal.  It has already been expanded at least 1 step.  */
-
-  RELAX_IMMED_STEP2
-  /* The last instruction in this fragment (at->fr_opcode) contains a
-     literal.  It has already been expanded at least 2 steps.  */
+  FALSE,			/* literal_prefix */
+  TRUE,				/* schedule */
+#if XSHAL_USE_ABSOLUTE_LITERALS
+  TRUE				/* absolute_literals */
+#else
+  FALSE				/* absolute_literals */
+#endif
 };
 
-/* This is used as a stopper to bound the number of steps that
-   can be taken.  */
-#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP2 - RELAX_IMMED)
-
-
-typedef bfd_boolean (*frag_predicate) (const fragS *);
-
 
 /* Directive functions.  */
 
-static bfd_boolean use_generics
-  PARAMS ((void));
-static bfd_boolean use_longcalls
-  PARAMS ((void));
-static bfd_boolean code_density_available
-  PARAMS ((void));
-static bfd_boolean can_relax
-  PARAMS ((void));
-static void directive_push
-  PARAMS ((directiveE, bfd_boolean, const void *));
-static void directive_pop
-  PARAMS ((directiveE *, bfd_boolean *, const char **,
-	   unsigned int *, const void **));
-static void directive_balance
-  PARAMS ((void));
-static bfd_boolean inside_directive
-  PARAMS ((directiveE));
-static void get_directive
-  PARAMS ((directiveE *, bfd_boolean *));
-static void xtensa_begin_directive
-  PARAMS ((int));
-static void xtensa_end_directive
-  PARAMS ((int));
-static void xtensa_literal_prefix
-  PARAMS ((char const *, int));
-static void xtensa_literal_position
-  PARAMS ((int));
-static void xtensa_literal_pseudo
-  PARAMS ((int));
-
-/* Parsing and Idiom Translation Functions.  */
-
-static const char *expression_end
-  PARAMS ((const char *));
-static unsigned tc_get_register
-  PARAMS ((const char *));
-static void expression_maybe_register
-  PARAMS ((xtensa_operand, expressionS *));
-static int tokenize_arguments
-  PARAMS ((char **, char *));
-static bfd_boolean parse_arguments
-  PARAMS ((TInsn *, int, char **));
-static int xg_translate_idioms
-  PARAMS ((char **, int *, char **));
-static int xg_translate_sysreg_op
-  PARAMS ((char **, int *, char **));
-static void xg_reverse_shift_count
-  PARAMS ((char **));
-static int xg_arg_is_constant
-  PARAMS ((char *, offsetT *));
-static void xg_replace_opname
-  PARAMS ((char **, char *));
-static int xg_check_num_args
-  PARAMS ((int *, int, char *, char **));
+static void xtensa_begin_directive (int);
+static void xtensa_end_directive (int);
+static void xtensa_literal_prefix (char const *, int);
+static void xtensa_literal_position (int);
+static void xtensa_literal_pseudo (int);
+static void xtensa_frequency_pseudo (int);
+static void xtensa_elf_cons (int);
 
-/* Functions for dealing with the Xtensa ISA.  */
+/* Parsing and Idiom Translation.  */
 
-static bfd_boolean operand_is_immed
-  PARAMS ((xtensa_operand));
-static bfd_boolean operand_is_pcrel_label
-  PARAMS ((xtensa_operand));
-static int get_relaxable_immed
-  PARAMS ((xtensa_opcode));
-static xtensa_opcode get_opcode_from_buf
-  PARAMS ((const char *));
-static bfd_boolean is_direct_call_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_call_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_entry_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_loop_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_the_loop_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_jx_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_windowed_return_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_conditional_branch_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_boolean is_branch_or_jump_opcode
-  PARAMS ((xtensa_opcode));
-static bfd_reloc_code_real_type opnum_to_reloc
-  PARAMS ((int));
-static int reloc_to_opnum
-  PARAMS ((bfd_reloc_code_real_type));
-static void xtensa_insnbuf_set_operand
-  PARAMS ((xtensa_insnbuf, xtensa_opcode, xtensa_operand, int32,
-	   const char *, unsigned int));
-static uint32 xtensa_insnbuf_get_operand
-  PARAMS ((xtensa_insnbuf, xtensa_opcode, int));
-static void xtensa_insnbuf_set_immediate_field
-  PARAMS ((xtensa_opcode, xtensa_insnbuf, int32, const char *,
-	   unsigned int));
-static bfd_boolean is_negatable_branch
-  PARAMS ((TInsn *));
+static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *);
 
 /* Various Other Internal Functions.  */
 
-static bfd_boolean is_unique_insn_expansion
-  PARAMS ((TransitionRule *));
-static int xg_get_insn_size
-  PARAMS ((TInsn *));
-static int xg_get_build_instr_size
-  PARAMS ((BuildInstr *));
-static bfd_boolean xg_is_narrow_insn
-  PARAMS ((TInsn *));
-static bfd_boolean xg_is_single_relaxable_insn
-  PARAMS ((TInsn *));
-static int xg_get_max_narrow_insn_size
-  PARAMS ((xtensa_opcode));
-static int xg_get_max_insn_widen_size
-  PARAMS ((xtensa_opcode));
-static int xg_get_max_insn_widen_literal_size
-  PARAMS ((xtensa_opcode));
-static bfd_boolean xg_is_relaxable_insn
-  PARAMS ((TInsn *, int));
-static symbolS *get_special_literal_symbol
-  PARAMS ((void));
-static symbolS *get_special_label_symbol
-  PARAMS ((void));
-static bfd_boolean xg_build_to_insn
-  PARAMS ((TInsn *, TInsn *, BuildInstr *));
-static bfd_boolean xg_build_to_stack
-  PARAMS ((IStack *, TInsn *, BuildInstr *));
-static bfd_boolean xg_expand_to_stack
-  PARAMS ((IStack *, TInsn *, int));
-static bfd_boolean xg_expand_narrow
-  PARAMS ((TInsn *, TInsn *));
-static bfd_boolean xg_immeds_fit
-  PARAMS ((const TInsn *));
-static bfd_boolean xg_symbolic_immeds_fit
-  PARAMS ((const TInsn *, segT, fragS *, offsetT, long));
-static bfd_boolean xg_check_operand
-  PARAMS ((int32, xtensa_operand));
-static int is_dnrange
-  PARAMS ((fragS *, symbolS *, long));
-static int xg_assembly_relax
-  PARAMS ((IStack *, TInsn *, segT, fragS *, offsetT, int, long));
-static void xg_force_frag_space
-  PARAMS ((int));
-static void xg_finish_frag
-  PARAMS ((char *, enum xtensa_relax_statesE, int, bfd_boolean));
-static bfd_boolean is_branch_jmp_to_next
-  PARAMS ((TInsn *, fragS *));
-static void xg_add_branch_and_loop_targets
-  PARAMS ((TInsn *));
-static bfd_boolean xg_instruction_matches_rule
-  PARAMS ((TInsn *, TransitionRule *));
-static TransitionRule *xg_instruction_match
-  PARAMS ((TInsn *));
-static bfd_boolean xg_build_token_insn
-  PARAMS ((BuildInstr *, TInsn *, TInsn *));
-static bfd_boolean xg_simplify_insn
-  PARAMS ((TInsn *, TInsn *));
-static bfd_boolean xg_expand_assembly_insn
-  PARAMS ((IStack *, TInsn *));
-static symbolS *xg_assemble_literal
-  PARAMS ((TInsn *));
-static void xg_assemble_literal_space
-  PARAMS ((int));
-static symbolS *xtensa_create_literal_symbol
-  PARAMS ((segT, fragS *));
-static void xtensa_add_literal_sym
-  PARAMS ((symbolS *));
-static void xtensa_add_insn_label
-  PARAMS ((symbolS *));
-static void xtensa_clear_insn_labels
-  PARAMS ((void));
-static bfd_boolean get_is_linkonce_section
-  PARAMS ((bfd *, segT));
-static bfd_boolean xg_emit_insn
-  PARAMS ((TInsn *, bfd_boolean));
-static bfd_boolean xg_emit_insn_to_buf
-  PARAMS ((TInsn *, char *, fragS *, offsetT, bfd_boolean));
-static bfd_boolean xg_add_opcode_fix
-  PARAMS ((xtensa_opcode, int, expressionS *, fragS *, offsetT));
-static void xg_resolve_literals
-  PARAMS ((TInsn *, symbolS *));
-static void xg_resolve_labels
-  PARAMS ((TInsn *, symbolS *));
-static void xg_assemble_tokens
-  PARAMS ((TInsn *));
-static bfd_boolean is_register_writer
-  PARAMS ((const TInsn *, const char *, int));
-static bfd_boolean is_bad_loopend_opcode
-  PARAMS ((const TInsn *));
-static bfd_boolean is_unaligned_label
-  PARAMS ((symbolS *));
-static fragS *next_non_empty_frag
-  PARAMS ((const fragS *));
-static xtensa_opcode next_frag_opcode
-  PARAMS ((const fragS *));
-static void update_next_frag_nop_state
-  PARAMS ((fragS *));
-static bfd_boolean next_frag_is_branch_target
-  PARAMS ((const fragS *));
-static bfd_boolean next_frag_is_loop_target
-  PARAMS ((const fragS *));
-static addressT next_frag_pre_opcode_bytes
-  PARAMS ((const fragS *));
-static bfd_boolean is_next_frag_target
-  PARAMS ((const fragS *, const fragS *));
-static void xtensa_mark_literal_pool_location
-  PARAMS ((void));
-static void xtensa_move_labels
-  PARAMS ((fragS *, valueT, bfd_boolean));
-static void assemble_nop
-  PARAMS ((size_t, char *));
-static addressT get_expanded_loop_offset
-  PARAMS ((xtensa_opcode));
-static fragS *get_literal_pool_location
-  PARAMS ((segT));
-static void set_literal_pool_location
-  PARAMS ((segT, fragS *));
-
-/* Helpers for xtensa_end().  */
-
-static void xtensa_cleanup_align_frags
-  PARAMS ((void));
-static void xtensa_fix_target_frags
-  PARAMS ((void));
-static bfd_boolean frag_can_negate_branch
-  PARAMS ((fragS *));
-static void xtensa_fix_a0_b_retw_frags
-  PARAMS ((void));
-static bfd_boolean next_instrs_are_b_retw
-  PARAMS ((fragS *));
-static void xtensa_fix_b_j_loop_end_frags
-  PARAMS ((void));
-static bfd_boolean next_instr_is_loop_end
-  PARAMS ((fragS *));
-static void xtensa_fix_close_loop_end_frags
-  PARAMS ((void));
-static size_t min_bytes_to_other_loop_end
-  PARAMS ((fragS *, fragS *, offsetT, size_t));
-static size_t unrelaxed_frag_min_size
-  PARAMS ((fragS *));
-static void xtensa_fix_short_loop_frags
-  PARAMS ((void));
-static size_t count_insns_to_loop_end
-  PARAMS ((fragS *, bfd_boolean, size_t));
-static size_t unrelaxed_frag_min_insn_count
-  PARAMS ((fragS *));
-static bfd_boolean branch_before_loop_end
-  PARAMS ((fragS *));
-static bfd_boolean unrelaxed_frag_has_b_j
-  PARAMS ((fragS *));
-static void xtensa_sanity_check
-  PARAMS ((void));
-static bfd_boolean is_empty_loop
-  PARAMS ((const TInsn *, fragS *));
-static bfd_boolean is_local_forward_loop
-  PARAMS ((const TInsn *, fragS *));
+extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean);
+static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *);
+static void xtensa_mark_literal_pool_location (void);
+static addressT get_expanded_loop_offset (xtensa_opcode);
+static fragS *get_literal_pool_location (segT);
+static void set_literal_pool_location (segT, fragS *);
+static void xtensa_set_frag_assembly_state (fragS *);
+static void finish_vinsn (vliw_insn *);
+static bfd_boolean emit_single_op (TInsn *);
+static int total_frag_text_expansion (fragS *);
 
 /* Alignment Functions.  */
 
-static size_t get_text_align_power
-  PARAMS ((int));
-static addressT get_text_align_max_fill_size
-  PARAMS ((int, bfd_boolean, bfd_boolean));
-static addressT get_text_align_fill_size
-  PARAMS ((addressT, int, int, bfd_boolean, bfd_boolean));
-static size_t get_text_align_nop_count
-  PARAMS ((size_t, bfd_boolean));
-static size_t get_text_align_nth_nop_size
-  PARAMS ((size_t, size_t, bfd_boolean));
-static addressT get_noop_aligned_address
-  PARAMS ((fragS *, addressT));
-static addressT get_widen_aligned_address
-  PARAMS ((fragS *, addressT));
+static int get_text_align_power (unsigned);
+static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean);
+static int branch_align_power (segT);
 
 /* Helpers for xtensa_relax_frag().  */
 
-static long relax_frag_text_align
-  PARAMS ((fragS *, long));
-static long relax_frag_add_nop
-  PARAMS ((fragS *));
-static long relax_frag_narrow
-  PARAMS ((fragS *, long));
-static bfd_boolean future_alignment_required
-  PARAMS ((fragS *, long));
-static long relax_frag_immed
-  PARAMS ((segT, fragS *, long, int, int *));
-
-/* Helpers for md_convert_frag().  */
+static long relax_frag_add_nop (fragS *);
 
-static void convert_frag_align_next_opcode
-  PARAMS ((fragS *));
-static void convert_frag_narrow
-  PARAMS ((fragS *));
-static void convert_frag_immed
-  PARAMS ((segT, fragS *, int));
-static fixS *fix_new_exp_in_seg
-  PARAMS ((segT, subsegT, fragS *, int, int, expressionS *, int,
-	   bfd_reloc_code_real_type));
-static void convert_frag_immed_finish_loop
-  PARAMS ((segT, fragS *, TInsn *));
-static offsetT get_expression_value
-  PARAMS ((segT, expressionS *));
-
-/* Flags for the Last Instruction in Each Subsegment.  */
+/* Accessors for additional per-subsegment information.  */
 
-static unsigned get_last_insn_flags
-  PARAMS ((segT, subsegT));
-static void set_last_insn_flags
-  PARAMS ((segT, subsegT, unsigned, bfd_boolean));
+static unsigned get_last_insn_flags (segT, subsegT);
+static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean);
+static float get_subseg_total_freq (segT, subsegT);
+static float get_subseg_target_freq (segT, subsegT);
+static void set_subseg_freq (segT, subsegT, float, float);
 
 /* Segment list functions.  */
 
-static void xtensa_remove_section
-  PARAMS ((segT));
-static void xtensa_insert_section
-  PARAMS ((segT, segT));
-static void xtensa_move_seg_list_to_beginning
-  PARAMS ((seg_list *));
-static void xtensa_move_literals
-  PARAMS ((void));
-static void mark_literal_frags
-  PARAMS ((seg_list *));
-static void xtensa_reorder_seg_list
-  PARAMS ((seg_list *, segT));
-static void xtensa_reorder_segments
-  PARAMS ((void));
-static segT get_last_sec
-  PARAMS ((void));
-static void xtensa_switch_to_literal_fragment
-  PARAMS ((emit_state *));
-static void xtensa_switch_section_emit_state
-  PARAMS ((emit_state *, segT, subsegT));
-static void xtensa_restore_emit_state
-  PARAMS ((emit_state *));
+static void xtensa_move_literals (void);
+static void xtensa_reorder_segments (void);
+static void xtensa_switch_to_literal_fragment (emit_state *);
+static void xtensa_switch_to_non_abs_literal_fragment (emit_state *);
+static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT);
+static void xtensa_restore_emit_state (emit_state *);
 static void cache_literal_section
-  PARAMS ((seg_list *, const char *, segT *));
-static segT retrieve_literal_seg
-  PARAMS ((seg_list *, const char *));
-static segT seg_present
-  PARAMS ((const char *));
-static void add_seg_list
-  PARAMS ((seg_list *, segT));
+  (seg_list *, const char *, segT *, bfd_boolean);
 
-/* Property Table (e.g., ".xt.insn" and ".xt.lit") Functions.  */
+/* Import from elf32-xtensa.c in BFD library.  */
 
-static void xtensa_create_property_segments
-  PARAMS ((frag_predicate, const char *, xt_section_type));
-static segment_info_type *retrieve_segment_info
-  PARAMS ((segT));
-static segT retrieve_xtensa_section
-  PARAMS ((char *));
-static bfd_boolean section_has_property
-  PARAMS ((segT sec, frag_predicate));
-static void add_xt_block_frags
-  PARAMS ((segT, segT, xtensa_block_info **, frag_predicate));
-static bfd_boolean get_frag_is_literal
-  PARAMS ((const fragS *));
-static bfd_boolean get_frag_is_insn
-  PARAMS ((const fragS *));
+extern char *xtensa_get_property_section_name (asection *, const char *);
 
-/* Import from elf32-xtensa.c in BFD library.  */
-extern char *xtensa_get_property_section_name
-  PARAMS ((asection *, const char *));
+/* op_placement_info functions.  */
+
+static void init_op_placement_info_table (void);
+extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int);
+static int xg_get_single_size (xtensa_opcode);
+static xtensa_format xg_get_single_format (xtensa_opcode);
+static int xg_get_single_slot (xtensa_opcode);
 
 /* TInsn and IStack functions.  */
-static bfd_boolean tinsn_has_symbolic_operands
-  PARAMS ((const TInsn *));
-static bfd_boolean tinsn_has_invalid_symbolic_operands
-  PARAMS ((const TInsn *));
-static bfd_boolean tinsn_has_complex_operands
-  PARAMS ((const TInsn *));
-static bfd_boolean tinsn_to_insnbuf
-  PARAMS ((TInsn *, xtensa_insnbuf));
-static bfd_boolean tinsn_check_arguments
-  PARAMS ((const TInsn *));
-static void tinsn_from_chars
-  PARAMS ((TInsn *, char *));
-static void tinsn_immed_from_frag
-  PARAMS ((TInsn *, fragS *));
-static int get_num_stack_text_bytes
-  PARAMS ((IStack *));
-static int get_num_stack_literal_bytes
-  PARAMS ((IStack *));
+
+static bfd_boolean tinsn_has_symbolic_operands (const TInsn *);
+static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *);
+static bfd_boolean tinsn_has_complex_operands (const TInsn *);
+static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf);
+static bfd_boolean tinsn_check_arguments (const TInsn *);
+static void tinsn_from_chars (TInsn *, char *, int);
+static void tinsn_immed_from_frag (TInsn *, fragS *, int);
+static int get_num_stack_text_bytes (IStack *);
+static int get_num_stack_literal_bytes (IStack *);
+
+/* vliw_insn functions.  */
+
+static void xg_init_vinsn (vliw_insn *);
+static void xg_clear_vinsn (vliw_insn *);
+static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *);
+static void xg_free_vinsn (vliw_insn *);
+static bfd_boolean vinsn_to_insnbuf
+  (vliw_insn *, char *, fragS *, bfd_boolean);
+static void vinsn_from_chars (vliw_insn *, char *);
 
 /* Expression Utilities.  */
-bfd_boolean expr_is_const
-  PARAMS ((const expressionS *));
-offsetT get_expr_const
-  PARAMS ((const expressionS *));
-void set_expr_const
-  PARAMS ((expressionS *, offsetT));
-void set_expr_symbol_offset
-  PARAMS ((expressionS *, symbolS *, offsetT));
-bfd_boolean expr_is_equal
-  PARAMS ((expressionS *, expressionS *));
-static void copy_expr
-  PARAMS ((expressionS *, const expressionS *));
-
-#ifdef XTENSA_SECTION_RENAME
-static void build_section_rename
-  PARAMS ((const char *));
-static void add_section_rename
-  PARAMS ((char *, char *));
-#endif
+
+bfd_boolean expr_is_const (const expressionS *);
+offsetT get_expr_const (const expressionS *);
+void set_expr_const (expressionS *, offsetT);
+bfd_boolean expr_is_register (const expressionS *);
+offsetT get_expr_register (const expressionS *);
+void set_expr_symbol_offset (expressionS *, symbolS *, offsetT);
+bfd_boolean expr_is_equal (expressionS *, expressionS *);
+static void copy_expr (expressionS *, const expressionS *);
+
+/* Section renaming.  */
+
+static void build_section_rename (const char *);
 
 
 /* ISA imported from bfd.  */
@@ -739,20 +533,24 @@ static xtensa_opcode xtensa_callx0_opcode;
 static xtensa_opcode xtensa_callx4_opcode;
 static xtensa_opcode xtensa_callx8_opcode;
 static xtensa_opcode xtensa_callx12_opcode;
+static xtensa_opcode xtensa_const16_opcode;
 static xtensa_opcode xtensa_entry_opcode;
+static xtensa_opcode xtensa_movi_opcode;
+static xtensa_opcode xtensa_movi_n_opcode;
 static xtensa_opcode xtensa_isync_opcode;
-static xtensa_opcode xtensa_j_opcode;
 static xtensa_opcode xtensa_jx_opcode;
+static xtensa_opcode xtensa_l32r_opcode;
 static xtensa_opcode xtensa_loop_opcode;
 static xtensa_opcode xtensa_loopnez_opcode;
 static xtensa_opcode xtensa_loopgtz_opcode;
+static xtensa_opcode xtensa_nop_opcode;
 static xtensa_opcode xtensa_nop_n_opcode;
 static xtensa_opcode xtensa_or_opcode;
 static xtensa_opcode xtensa_ret_opcode;
 static xtensa_opcode xtensa_ret_n_opcode;
 static xtensa_opcode xtensa_retw_opcode;
 static xtensa_opcode xtensa_retw_n_opcode;
-static xtensa_opcode xtensa_rsr_opcode;
+static xtensa_opcode xtensa_rsr_lcount_opcode;
 static xtensa_opcode xtensa_waiti_opcode;
 
 
@@ -760,34 +558,43 @@ static xtensa_opcode xtensa_waiti_opcode;
 
 bfd_boolean use_literal_section = TRUE;
 static bfd_boolean align_targets = TRUE;
-static bfd_boolean align_only_targets = FALSE;
-static bfd_boolean software_a0_b_retw_interlock = TRUE;
+static bfd_boolean warn_unaligned_branch_targets = FALSE;
 static bfd_boolean has_a0_b_retw = FALSE;
-static bfd_boolean workaround_a0_b_retw = TRUE;
+static bfd_boolean workaround_a0_b_retw = FALSE;
+static bfd_boolean workaround_b_j_loop_end = FALSE;
+static bfd_boolean workaround_short_loop = FALSE;
+static bfd_boolean maybe_has_short_loop = FALSE;
+static bfd_boolean workaround_close_loop_end = FALSE;
+static bfd_boolean maybe_has_close_loop_end = FALSE;
+static bfd_boolean enforce_three_byte_loop_align = FALSE;
 
-static bfd_boolean software_avoid_b_j_loop_end = TRUE;
-static bfd_boolean workaround_b_j_loop_end = TRUE;
-static bfd_boolean maybe_has_b_j_loop_end = FALSE;
+/* When workaround_short_loops is TRUE, all loops with early exits must
+   have at least 3 instructions.  workaround_all_short_loops is a modifier
+   to the workaround_short_loop flag.  In addition to the
+   workaround_short_loop actions, all straightline loopgtz and loopnez
+   must have at least 3 instructions.  */
 
-static bfd_boolean software_avoid_short_loop = TRUE;
-static bfd_boolean workaround_short_loop = TRUE;
-static bfd_boolean maybe_has_short_loop = FALSE;
+static bfd_boolean workaround_all_short_loops = FALSE;
 
-static bfd_boolean software_avoid_close_loop_end = TRUE;
-static bfd_boolean workaround_close_loop_end = TRUE;
-static bfd_boolean maybe_has_close_loop_end = FALSE;
 
-/* When avoid_short_loops is true, all loops with early exits must
-   have at least 3 instructions.  avoid_all_short_loops is a modifier
-   to the avoid_short_loop flag.  In addition to the avoid_short_loop
-   actions, all straightline loopgtz and loopnez must have at least 3
-   instructions.  */
+static void
+xtensa_setup_hw_workarounds (int earliest, int latest)
+{
+  if (earliest > latest)
+    as_fatal (_("illegal range of target hardware versions"));
 
-static bfd_boolean software_avoid_all_short_loops = TRUE;
-static bfd_boolean workaround_all_short_loops = TRUE;
+  /* Enable all workarounds for pre-T1050.0 hardware.  */
+  if (earliest < 105000 || latest < 105000)
+    {
+      workaround_a0_b_retw |= TRUE;
+      workaround_b_j_loop_end |= TRUE;
+      workaround_short_loop |= TRUE;
+      workaround_close_loop_end |= TRUE;
+      workaround_all_short_loops |= TRUE;
+      enforce_three_byte_loop_align = TRUE;
+    }
+}
 
-/* This is on a per-instruction basis.  */
-static bfd_boolean specific_opcode = FALSE;
 
 enum
 {
@@ -797,17 +604,25 @@ enum
   option_relax,
   option_no_relax,
 
+  option_link_relax,
+  option_no_link_relax,
+
   option_generics,
   option_no_generics,
 
+  option_transform,
+  option_no_transform,
+
   option_text_section_literals,
   option_no_text_section_literals,
 
+  option_absolute_literals,
+  option_no_absolute_literals,
+
   option_align_targets,
   option_no_align_targets,
 
-  option_align_only_targets,
-  option_no_align_only_targets,
+  option_warn_unaligned_targets,
 
   option_longcalls,
   option_no_longcalls,
@@ -829,119 +644,115 @@ enum
 
   option_no_workarounds,
 
-#ifdef XTENSA_SECTION_RENAME
-  option_literal_section_name,
-  option_text_section_name,
-  option_data_section_name,
-  option_bss_section_name,
   option_rename_section_name,
-#endif
 
-  option_eb,
-  option_el
+  option_prefer_l32r,
+  option_prefer_const16,
+
+  option_target_hardware
 };
 
 const char *md_shortopts = "";
 
 struct option md_longopts[] =
 {
-  {"density", no_argument, NULL, option_density},
-  {"no-density", no_argument, NULL, option_no_density},
-  /* At least as early as alameda, --[no-]relax didn't work as
-     documented, so as of albany, --[no-]relax is equivalent to
-     --[no-]generics.  Both of these will be deprecated in
-     BearValley.  */
-  {"relax", no_argument, NULL, option_generics},
-  {"no-relax", no_argument, NULL, option_no_generics},
-  {"generics", no_argument, NULL, option_generics},
-  {"no-generics", no_argument, NULL, option_no_generics},
-  {"text-section-literals", no_argument, NULL, option_text_section_literals},
-  {"no-text-section-literals", no_argument, NULL,
-   option_no_text_section_literals},
+  { "density", no_argument, NULL, option_density },
+  { "no-density", no_argument, NULL, option_no_density },
+
+  /* Both "relax" and "generics" are deprecated and treated as equivalent
+     to the "transform" option.  */
+  { "relax", no_argument, NULL, option_relax },
+  { "no-relax", no_argument, NULL, option_no_relax },
+  { "generics", no_argument, NULL, option_generics },
+  { "no-generics", no_argument, NULL, option_no_generics },
+
+  { "transform", no_argument, NULL, option_transform },
+  { "no-transform", no_argument, NULL, option_no_transform },
+  { "text-section-literals", no_argument, NULL, option_text_section_literals },
+  { "no-text-section-literals", no_argument, NULL,
+    option_no_text_section_literals },
+  { "absolute-literals", no_argument, NULL, option_absolute_literals },
+  { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals },
   /* This option was changed from -align-target to -target-align
      because it conflicted with the "-al" option.  */
-  {"target-align", no_argument, NULL, option_align_targets},
-  {"no-target-align", no_argument, NULL,
-   option_no_align_targets},
-#if 0
-  /* This option  should do a better job aligning targets because
-     it will only attempt to align targets that are the target of a 
-     branch.  */
-   { "target-align-only", no_argument, NULL, option_align_only_targets },
-   { "no-target-align-only", no_argument, NULL, option_no_align_only_targets },
-#endif /* 0 */
-  {"longcalls", no_argument, NULL, option_longcalls},
-  {"no-longcalls", no_argument, NULL, option_no_longcalls},
-
-  {"no-workaround-a0-b-retw", no_argument, NULL,
-   option_no_workaround_a0_b_retw},
-  {"workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw},
-  
-  {"no-workaround-b-j-loop-end", no_argument, NULL,
-   option_no_workaround_b_j_loop_end},
-  {"workaround-b-j-loop-end", no_argument, NULL,
-   option_workaround_b_j_loop_end},
-  
-  {"no-workaround-short-loops", no_argument, NULL,
-   option_no_workaround_short_loop},
-  {"workaround-short-loops", no_argument, NULL, option_workaround_short_loop},
-
-  {"no-workaround-all-short-loops", no_argument, NULL,
-   option_no_workaround_all_short_loops},
-  {"workaround-all-short-loop", no_argument, NULL,
-   option_workaround_all_short_loops},
-
-  {"no-workaround-close-loop-end", no_argument, NULL,
-   option_no_workaround_close_loop_end},
-  {"workaround-close-loop-end", no_argument, NULL,
-   option_workaround_close_loop_end},
-
-  {"no-workarounds", no_argument, NULL, option_no_workarounds},
-
-#ifdef XTENSA_SECTION_RENAME
-  {"literal-section-name", required_argument, NULL,
-   option_literal_section_name},
-  {"text-section-name", required_argument, NULL,
-   option_text_section_name},
-  {"data-section-name", required_argument, NULL,
-   option_data_section_name},
-  {"rename-section", required_argument, NULL,
-   option_rename_section_name},
-  {"bss-section-name", required_argument, NULL,
-   option_bss_section_name},
-#endif /* XTENSA_SECTION_RENAME */
-
-  {NULL, no_argument, NULL, 0}
+  { "target-align", no_argument, NULL, option_align_targets },
+  { "no-target-align", no_argument, NULL, option_no_align_targets },
+  { "warn-unaligned-targets", no_argument, NULL,
+    option_warn_unaligned_targets },
+  { "longcalls", no_argument, NULL, option_longcalls },
+  { "no-longcalls", no_argument, NULL, option_no_longcalls },
+
+  { "no-workaround-a0-b-retw", no_argument, NULL,
+    option_no_workaround_a0_b_retw },
+  { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw },
+
+  { "no-workaround-b-j-loop-end", no_argument, NULL,
+    option_no_workaround_b_j_loop_end },
+  { "workaround-b-j-loop-end", no_argument, NULL,
+    option_workaround_b_j_loop_end },
+
+  { "no-workaround-short-loops", no_argument, NULL,
+    option_no_workaround_short_loop },
+  { "workaround-short-loops", no_argument, NULL,
+    option_workaround_short_loop },
+
+  { "no-workaround-all-short-loops", no_argument, NULL,
+    option_no_workaround_all_short_loops },
+  { "workaround-all-short-loop", no_argument, NULL,
+    option_workaround_all_short_loops },
+
+  { "prefer-l32r", no_argument, NULL, option_prefer_l32r },
+  { "prefer-const16", no_argument, NULL, option_prefer_const16 },
+
+  { "no-workarounds", no_argument, NULL, option_no_workarounds },
+
+  { "no-workaround-close-loop-end", no_argument, NULL,
+    option_no_workaround_close_loop_end },
+  { "workaround-close-loop-end", no_argument, NULL,
+    option_workaround_close_loop_end },
+
+  { "rename-section", required_argument, NULL, option_rename_section_name },
+
+  { "link-relax", no_argument, NULL, option_link_relax },
+  { "no-link-relax", no_argument, NULL, option_no_link_relax },
+
+  { "target-hardware", required_argument, NULL, option_target_hardware },
+
+  { NULL, no_argument, NULL, 0 }
 };
 
 size_t md_longopts_size = sizeof md_longopts;
 
 
 int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
+md_parse_option (int c, char *arg)
 {
   switch (c)
     {
     case option_density:
-      if (!density_supported)
-	{
-	  as_bad (_("'--density' option not supported in this Xtensa "
-		  "configuration"));
-	  return 0;
-	}
-      directive_state[directive_density] = TRUE;
+      as_warn (_("--density option is ignored"));
       return 1;
     case option_no_density:
-      directive_state[directive_density] = FALSE;
+      as_warn (_("--no-density option is ignored"));
       return 1;
-    case option_generics:
-      directive_state[directive_generics] = TRUE;
+    case option_link_relax:
+      linkrelax = 1;
       return 1;
-    case option_no_generics:
-      directive_state[directive_generics] = FALSE;
+    case option_no_link_relax:
+      linkrelax = 0;
       return 1;
+    case option_generics:
+      as_warn (_("--generics is deprecated; use --transform instead"));
+      return md_parse_option (option_transform, arg);
+    case option_no_generics:
+      as_warn (_("--no-generics is deprecated; use --no-transform instead"));
+      return md_parse_option (option_no_transform, arg);
+    case option_relax:
+      as_warn (_("--relax is deprecated; use --transform instead"));
+      return md_parse_option (option_transform, arg);
+    case option_no_relax:
+      as_warn (_("--no-relax is deprecated; use --no-transform instead"));
+      return md_parse_option (option_no_transform, arg);
     case option_longcalls:
       directive_state[directive_longcalls] = TRUE;
       return 1;
@@ -954,63 +765,60 @@ md_parse_option (c, arg)
     case option_no_text_section_literals:
       use_literal_section = TRUE;
       return 1;
+    case option_absolute_literals:
+      if (!absolute_literals_supported)
+	{
+	  as_fatal (_("--absolute-literals option not supported in this Xtensa configuration"));
+	  return 0;
+	}
+      directive_state[directive_absolute_literals] = TRUE;
+      return 1;
+    case option_no_absolute_literals:
+      directive_state[directive_absolute_literals] = FALSE;
+      return 1;
+
     case option_workaround_a0_b_retw:
       workaround_a0_b_retw = TRUE;
-      software_a0_b_retw_interlock = TRUE;
       return 1;
     case option_no_workaround_a0_b_retw:
       workaround_a0_b_retw = FALSE;
-      software_a0_b_retw_interlock = FALSE;
       return 1;
     case option_workaround_b_j_loop_end:
       workaround_b_j_loop_end = TRUE;
-      software_avoid_b_j_loop_end = TRUE;
       return 1;
     case option_no_workaround_b_j_loop_end:
       workaround_b_j_loop_end = FALSE;
-      software_avoid_b_j_loop_end = FALSE;
       return 1;
 
     case option_workaround_short_loop:
       workaround_short_loop = TRUE;
-      software_avoid_short_loop = TRUE;
       return 1;
     case option_no_workaround_short_loop:
       workaround_short_loop = FALSE;
-      software_avoid_short_loop = FALSE;
       return 1;
 
     case option_workaround_all_short_loops:
       workaround_all_short_loops = TRUE;
-      software_avoid_all_short_loops = TRUE;
       return 1;
     case option_no_workaround_all_short_loops:
       workaround_all_short_loops = FALSE;
-      software_avoid_all_short_loops = FALSE;
       return 1;
 
     case option_workaround_close_loop_end:
       workaround_close_loop_end = TRUE;
-      software_avoid_close_loop_end = TRUE;
       return 1;
     case option_no_workaround_close_loop_end:
       workaround_close_loop_end = FALSE;
-      software_avoid_close_loop_end = FALSE;
       return 1;
 
     case option_no_workarounds:
       workaround_a0_b_retw = FALSE;
-      software_a0_b_retw_interlock = FALSE;
       workaround_b_j_loop_end = FALSE;
-      software_avoid_b_j_loop_end = FALSE;
       workaround_short_loop = FALSE;
-      software_avoid_short_loop = FALSE;
       workaround_all_short_loops = FALSE;
-      software_avoid_all_short_loops = FALSE;
       workaround_close_loop_end = FALSE;
-      software_avoid_close_loop_end = FALSE;
       return 1;
-      
+
     case option_align_targets:
       align_targets = TRUE;
       return 1;
@@ -1018,48 +826,69 @@ md_parse_option (c, arg)
       align_targets = FALSE;
       return 1;
 
-    case option_align_only_targets:
-      align_only_targets = TRUE;
-      return 1;
-    case option_no_align_only_targets:
-      align_only_targets = FALSE;
+    case option_warn_unaligned_targets:
+      warn_unaligned_branch_targets = TRUE;
       return 1;
 
-#ifdef XTENSA_SECTION_RENAME
-    case option_literal_section_name:
-      add_section_rename (".literal", arg);
-      as_warn (_("'--literal-section-name' is deprecated; "
-		 "use '--rename-section .literal=NEWNAME'"));
+    case option_rename_section_name:
+      build_section_rename (arg);
       return 1;
 
-    case option_text_section_name:
-      add_section_rename (".text", arg);
-      as_warn (_("'--text-section-name' is deprecated; "
-		 "use '--rename-section .text=NEWNAME'"));
+    case 'Q':
+      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
+         should be emitted or not.  FIXME: Not implemented.  */
       return 1;
 
-    case option_data_section_name:
-      add_section_rename (".data", arg);
-      as_warn (_("'--data-section-name' is deprecated; "
-		 "use '--rename-section .data=NEWNAME'"));
+    case option_prefer_l32r:
+      if (prefer_const16)
+	as_fatal (_("prefer-l32r conflicts with prefer-const16"));
+      prefer_l32r = 1;
       return 1;
 
-    case option_bss_section_name:
-      add_section_rename (".bss", arg);
-      as_warn (_("'--bss-section-name' is deprecated; "
-		 "use '--rename-section .bss=NEWNAME'"));
+    case option_prefer_const16:
+      if (prefer_l32r)
+	as_fatal (_("prefer-const16 conflicts with prefer-l32r"));
+      prefer_const16 = 1;
       return 1;
 
-    case option_rename_section_name:
-      build_section_rename (arg);
+    case option_target_hardware:
+      {
+	int earliest, latest = 0;
+	if (*arg == 0 || *arg == '-')
+	  as_fatal (_("invalid target hardware version"));
+
+	earliest = strtol (arg, &arg, 0);
+
+	if (*arg == 0)
+	  latest = earliest;
+	else if (*arg == '-')
+	  {
+	    if (*++arg == 0)
+	      as_fatal (_("invalid target hardware version"));
+	    latest = strtol (arg, &arg, 0);
+	  }
+	if (*arg != 0)
+	  as_fatal (_("invalid target hardware version"));
+
+	xtensa_setup_hw_workarounds (earliest, latest);
+	return 1;
+      }
+
+    case option_transform:
+      /* This option has no affect other than to use the defaults,
+	 which are already set.  */
       return 1;
-#endif /* XTENSA_SECTION_RENAME */
 
-    case 'Q':
-      /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
-         should be emitted or not.  FIXME: Not implemented.  */
+    case option_no_transform:
+      /* This option turns off all transformations of any kind.
+	 However, because we want to preserve the state of other
+	 directives, we only change its own field.  Thus, before
+	 you perform any transformation, always check if transform
+	 is available.  If you use the functions we provide for this
+	 purpose, you will be ok.  */
+      directive_state[directive_transform] = FALSE;
       return 1;
-      
+
     default:
       return 0;
     }
@@ -1067,28 +896,92 @@ md_parse_option (c, arg)
 
 
 void
-md_show_usage (stream)
-     FILE *stream;
-{
-  fputs ("\nXtensa options:\n"
-	 "--[no-]density          [Do not] emit density instructions\n"
-	 "--[no-]relax            [Do not] perform branch relaxation\n"
-	 "--[no-]generics         [Do not] transform instructions\n"
-	 "--[no-]longcalls        [Do not] emit 32-bit call sequences\n"
-	 "--[no-]target-align     [Do not] try to align branch targets\n"
-	 "--[no-]text-section-literals\n"
-	 "                        [Do not] put literals in the text section\n"
-	 "--no-workarounds        Do not use any Xtensa workarounds\n"
-#ifdef XTENSA_SECTION_RENAME
-	 "--rename-section old=new(:old1=new1)*\n"
-	 "                        Rename section 'old' to 'new'\n"
-	 "\nThe following Xtensa options are deprecated\n"
-	 "--literal-section-name  Name of literal section (default .literal)\n"
-	 "--text-section-name     Name of text section (default .text)\n"
-	 "--data-section-name     Name of data section (default .data)\n"
-	 "--bss-section-name      Name of bss section (default .bss)\n"
-#endif
-	 , stream);
+md_show_usage (FILE *stream)
+{
+  fputs ("\n\
+Xtensa options:\n\
+  --[no-]text-section-literals\n\
+                          [Do not] put literals in the text section\n\
+  --[no-]absolute-literals\n\
+                          [Do not] default to use non-PC-relative literals\n\
+  --[no-]target-align     [Do not] try to align branch targets\n\
+  --[no-]longcalls        [Do not] emit 32-bit call sequences\n\
+  --[no-]transform        [Do not] transform instructions\n\
+  --rename-section old=new Rename section 'old' to 'new'\n", stream);
+}
+
+
+/* Functions related to the list of current label symbols.  */
+
+static void
+xtensa_add_insn_label (symbolS *sym)
+{
+  sym_list *l;
+
+  if (!free_insn_labels)
+    l = (sym_list *) xmalloc (sizeof (sym_list));
+  else
+    {
+      l = free_insn_labels;
+      free_insn_labels = l->next;
+    }
+
+  l->sym = sym;
+  l->next = insn_labels;
+  insn_labels = l;
+}
+
+
+static void
+xtensa_clear_insn_labels (void)
+{
+  sym_list **pl;
+
+  for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
+    ;
+  *pl = insn_labels;
+  insn_labels = NULL;
+}
+
+
+/* The "loops_ok" argument is provided to allow ignoring labels that
+   define loop ends.  This fixes a bug where the NOPs to align a
+   loop opcode were included in a previous zero-cost loop:
+
+   loop a0, loopend
+     <loop1 body>
+   loopend:
+
+   loop a2, loopend2
+     <loop2 body>
+
+   would become:
+
+   loop a0, loopend
+     <loop1 body>
+     nop.n <===== bad!
+   loopend:
+
+   loop a2, loopend2
+     <loop2 body>
+
+   This argument is used to prevent moving the NOP to before the
+   loop-end label, which is what you want in this special case.  */
+
+static void
+xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok)
+{
+  sym_list *lit;
+
+  for (lit = insn_labels; lit; lit = lit->next)
+    {
+      symbolS *lit_sym = lit->sym;
+      if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target)
+	{
+	  S_SET_VALUE (lit_sym, new_offset);
+	  symbol_set_frag (lit_sym, new_frag);
+	}
+    }
 }
 
 
@@ -1109,50 +1002,43 @@ state_stackS *directive_state_stack;
 
 const pseudo_typeS md_pseudo_table[] =
 {
-  {"align", s_align_bytes, 0},	/* Defaulting is invalid (0) */
-  {"literal_position", xtensa_literal_position, 0},
-  {"frame", s_ignore, 0},	/* formerly used for STABS debugging */
-  {"word", cons, 4},
-  {"begin", xtensa_begin_directive, 0},
-  {"end", xtensa_end_directive, 0},
-  {"literal", xtensa_literal_pseudo, 0},
-  {NULL, 0, 0},
+  { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0).  */
+  { "literal_position", xtensa_literal_position, 0 },
+  { "frame", s_ignore, 0 },	/* Formerly used for STABS debugging.  */
+  { "long", xtensa_elf_cons, 4 },
+  { "word", xtensa_elf_cons, 4 },
+  { "short", xtensa_elf_cons, 2 },
+  { "begin", xtensa_begin_directive, 0 },
+  { "end", xtensa_end_directive, 0 },
+  { "literal", xtensa_literal_pseudo, 0 },
+  { "frequency", xtensa_frequency_pseudo, 0 },
+  { NULL, 0, 0 },
 };
 
 
-bfd_boolean
-use_generics ()
-{
-  return directive_state[directive_generics];
-}
-
-
-bfd_boolean
-use_longcalls ()
-{
-  return directive_state[directive_longcalls];
-}
-
-
-bfd_boolean
-code_density_available ()
+static bfd_boolean
+use_transform (void)
 {
-  return directive_state[directive_density];
+  /* After md_end, you should be checking frag by frag, rather
+     than state directives.  */
+  assert (!past_xtensa_end);
+  return directive_state[directive_transform];
 }
 
 
-bfd_boolean
-can_relax ()
+static bfd_boolean
+do_align_targets (void)
 {
-  return use_generics ();
+  /* Do not use this function after md_end; just look at align_targets
+     instead.  There is no target-align directive, so alignment is either
+     enabled for all frags or not done at all.  */
+  assert (!past_xtensa_end);
+  return align_targets && use_transform ();
 }
 
 
 static void
-directive_push (directive, negated, datum)
-     directiveE directive;
-     bfd_boolean negated;
-     const void *datum;
+directive_push (directiveE directive, bfd_boolean negated, const void *datum)
 {
   char *file;
   unsigned int line;
@@ -1172,13 +1058,13 @@ directive_push (directive, negated, datum)
   directive_state[directive] = !negated;
 }
 
+
 static void
-directive_pop (directive, negated, file, line, datum)
-     directiveE *directive;
-     bfd_boolean *negated;
-     const char **file;
-     unsigned int *line;
-     const void **datum;
+directive_pop (directiveE *directive,
+	       bfd_boolean *negated,
+	       const char **file,
+	       unsigned int *line,
+	       const void **datum)
 {
   state_stackS *top = directive_state_stack;
 
@@ -1201,7 +1087,7 @@ directive_pop (directive, negated, file, line, datum)
 
 
 static void
-directive_balance ()
+directive_balance (void)
 {
   while (directive_state_stack)
     {
@@ -1219,8 +1105,7 @@ directive_balance ()
 
 
 static bfd_boolean
-inside_directive (dir)
-     directiveE dir;
+inside_directive (directiveE dir)
 {
   state_stackS *top = directive_state_stack;
 
@@ -1232,12 +1117,11 @@ inside_directive (dir)
 
 
 static void
-get_directive (directive, negated)
-     directiveE *directive;
-     bfd_boolean *negated;
+get_directive (directiveE *directive, bfd_boolean *negated)
 {
   int len;
   unsigned i;
+  char *directive_string;
 
   if (strncmp (input_line_pointer, "no-", 3) != 0)
     *negated = FALSE;
@@ -1248,16 +1132,33 @@ get_directive (directive, negated)
     }
 
   len = strspn (input_line_pointer,
-		"abcdefghijklmnopqrstuvwxyz_/0123456789.");
+		"abcdefghijklmnopqrstuvwxyz_-/0123456789.");
+
+  /* This code is a hack to make .begin [no-][generics|relax] exactly
+     equivalent to .begin [no-]transform.  We should remove it when
+     we stop accepting those options.  */
+
+  if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0)
+    {
+      as_warn (_("[no-]generics is deprecated; use [no-]transform instead"));
+      directive_string = "transform";
+    }
+  else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0)
+    {
+      as_warn (_("[no-]relax is deprecated; use [no-]transform instead"));
+      directive_string = "transform";
+    }
+  else
+    directive_string = input_line_pointer;
 
   for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i)
     {
-      if (strncmp (input_line_pointer, directive_info[i].name, len) == 0)
+      if (strncmp (directive_string, directive_info[i].name, len) == 0)
 	{
 	  input_line_pointer += len;
 	  *directive = (directiveE) i;
 	  if (*negated && !directive_info[i].can_be_negated)
-	    as_bad (_("directive %s can't be negated"),
+	    as_bad (_("directive %s cannot be negated"),
 		    directive_info[i].name);
 	  return;
 	}
@@ -1269,8 +1170,7 @@ get_directive (directive, negated)
 
 
 static void
-xtensa_begin_directive (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED)
 {
   directiveE directive;
   bfd_boolean negated;
@@ -1278,8 +1178,6 @@ xtensa_begin_directive (ignore)
   int len;
   lit_state *ls;
 
-  md_flush_pending_output ();
-
   get_directive (&directive, &negated);
   if (directive == (directiveE) XTENSA_UNDEFINED)
     {
@@ -1287,6 +1185,9 @@ xtensa_begin_directive (ignore)
       return;
     }
 
+  if (cur_vinsn.inside_bundle)
+    as_bad (_("directives are not valid inside bundles"));
+
   switch (directive)
     {
     case directive_literal:
@@ -1297,15 +1198,19 @@ xtensa_begin_directive (ignore)
 	  saved_insn_labels = insn_labels;
 	  insn_labels = NULL;
 	}
+      as_warn (_(".begin literal is deprecated; use .literal instead"));
       state = (emit_state *) xmalloc (sizeof (emit_state));
       xtensa_switch_to_literal_fragment (state);
       directive_push (directive_literal, negated, state);
       break;
 
     case directive_literal_prefix:
+      /* Have to flush pending output because a movi relaxed to an l32r
+	 might produce a literal.  */
+      md_flush_pending_output ();
       /* Check to see if the current fragment is a literal
 	 fragment.  If it is, then this operation is not allowed.  */
-      if (frag_now->tc_frag_data.is_literal)
+      if (generating_literals)
 	{
 	  as_bad (_("cannot set literal_prefix inside literal fragment"));
 	  return;
@@ -1341,15 +1246,32 @@ xtensa_begin_directive (ignore)
       directive_push (directive_freeregs, negated, 0);
       break;
 
+    case directive_schedule:
+      md_flush_pending_output ();
+      frag_var (rs_fill, 0, 0, frag_now->fr_subtype,
+		frag_now->fr_symbol, frag_now->fr_offset, NULL);
+      directive_push (directive_schedule, negated, 0);
+      xtensa_set_frag_assembly_state (frag_now);
+      break;
+
     case directive_density:
-      if (!density_supported && !negated)
+      as_warn (_(".begin [no-]density is ignored"));
+      break;
+
+    case directive_absolute_literals:
+      md_flush_pending_output ();
+      if (!absolute_literals_supported && !negated)
 	{
-	  as_warn (_("Xtensa density option not supported; ignored"));
+	  as_warn (_("Xtensa absolute literals option not supported; ignored"));
 	  break;
 	}
-      /* fall through */
+      xtensa_set_frag_assembly_state (frag_now);
+      directive_push (directive, negated, 0);
+      break;
 
     default:
+      md_flush_pending_output ();
+      xtensa_set_frag_assembly_state (frag_now);
       directive_push (directive, negated, 0);
       break;
     }
@@ -1359,34 +1281,50 @@ xtensa_begin_directive (ignore)
 
 
 static void
-xtensa_end_directive (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+xtensa_end_directive (int ignore ATTRIBUTE_UNUSED)
 {
   directiveE begin_directive, end_directive;
   bfd_boolean begin_negated, end_negated;
   const char *file;
   unsigned int line;
   emit_state *state;
+  emit_state **state_ptr;
   lit_state *s;
 
-  md_flush_pending_output ();
+  if (cur_vinsn.inside_bundle)
+    as_bad (_("directives are not valid inside bundles"));
 
   get_directive (&end_directive, &end_negated);
-  if (end_directive == (directiveE) XTENSA_UNDEFINED)
+
+  md_flush_pending_output ();
+
+  switch (end_directive)
     {
+    case (directiveE) XTENSA_UNDEFINED:
       discard_rest_of_line ();
       return;
-    }
 
-  if (end_directive == directive_density && !density_supported && !end_negated)
-    {
-      as_warn (_("Xtensa density option not supported; ignored"));
+    case directive_density:
+      as_warn (_(".end [no-]density is ignored"));
       demand_empty_rest_of_line ();
-      return;
+      break;
+
+    case directive_absolute_literals:
+      if (!absolute_literals_supported && !end_negated)
+	{
+	  as_warn (_("Xtensa absolute literals option not supported; ignored"));
+	  demand_empty_rest_of_line ();
+	  return;
+	}
+      break;
+
+    default:
+      break;
     }
 
+  state_ptr = &state; /* use state_ptr to avoid type-punning warning */
   directive_pop (&begin_directive, &begin_negated, &file, &line,
-		 (const void **) &state);
+		 (const void **) state_ptr);
 
   if (begin_directive != directive_none)
     {
@@ -1403,6 +1341,7 @@ xtensa_end_directive (ignore)
 	    case directive_literal:
 	      frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL);
 	      xtensa_restore_emit_state (state);
+	      xtensa_set_frag_assembly_state (frag_now);
 	      free (state);
 	      if (!inside_directive (directive_literal))
 		{
@@ -1412,22 +1351,23 @@ xtensa_end_directive (ignore)
 		}
 	      break;
 
-	    case directive_freeregs:
-	      break;
-
 	    case directive_literal_prefix:
 	      /* Restore the default collection sections from saved state.  */
 	      s = (lit_state *) state;
 	      assert (s);
 
-	      if (use_literal_section)
-		default_lit_sections = *s;
+	      default_lit_sections = *s;
 
 	      /* free the state storage */
 	      free (s);
 	      break;
 
+	    case directive_schedule:
+	    case directive_freeregs:
+	      break;
+
 	    default:
+	      xtensa_set_frag_assembly_state (frag_now);
 	      break;
 	    }
 	}
@@ -1440,29 +1380,27 @@ xtensa_end_directive (ignore)
 /* Place an aligned literal fragment at the current location.  */
 
 static void
-xtensa_literal_position (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+xtensa_literal_position (int ignore ATTRIBUTE_UNUSED)
 {
+  md_flush_pending_output ();
+
   if (inside_directive (directive_literal))
     as_warn (_(".literal_position inside literal directive; ignoring"));
-  else if (!use_literal_section)
-    xtensa_mark_literal_pool_location ();
+  xtensa_mark_literal_pool_location ();
 
   demand_empty_rest_of_line ();
   xtensa_clear_insn_labels ();
 }
 
 
-/* Support .literal label, value@plt + offset.  */
+/* Support .literal label, expr, ...  */
 
 static void
-xtensa_literal_pseudo (ignored)
-     int ignored ATTRIBUTE_UNUSED;
+xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED)
 {
   emit_state state;
   char *p, *base_name;
   char c;
-  expressionS expP;
   segT dest_seg;
 
   if (inside_directive (directive_literal))
@@ -1472,6 +1410,8 @@ xtensa_literal_pseudo (ignored)
       return;
     }
 
+  md_flush_pending_output ();
+
   /* Previous labels go with whatever follows this directive, not with
      the literal, so save them now.  */
   saved_insn_labels = insn_labels;
@@ -1484,14 +1424,14 @@ xtensa_literal_pseudo (ignored)
 
   xtensa_switch_to_literal_fragment (&state);
 
-  /* ...but if we aren't using text-section-literals, then we 
+  /* ...but if we aren't using text-section-literals, then we
      need to put them in the section we just switched to.  */
-  if (use_literal_section)
+  if (use_literal_section || directive_state[directive_absolute_literals])
     dest_seg = now_seg;
 
-  /* All literals are aligned to four-byte boundaries
-     which is handled by switch to literal fragment.  */
-  /* frag_align (2, 0, 0);  */
+  /* All literals are aligned to four-byte boundaries.  */
+  frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
 
   c = get_symbol_end ();
   /* Just after name is now '\0'.  */
@@ -1511,20 +1451,10 @@ xtensa_literal_pseudo (ignored)
 
   colon (base_name);
 
-  do 
-    {
-      input_line_pointer++;		/* skip ',' or ':' */
-      
-      expr (0, &expP);
-
-      /* We only support 4-byte literals with .literal.  */
-      emit_expr (&expP, 4);
-    }
-  while (*input_line_pointer == ',');
-
   *p = c;
+  input_line_pointer++;		/* skip ',' or ':' */
 
-  demand_empty_rest_of_line ();
+  xtensa_elf_cons (4);
 
   xtensa_restore_emit_state (&state);
 
@@ -1535,21 +1465,11 @@ xtensa_literal_pseudo (ignored)
 
 
 static void
-xtensa_literal_prefix (start, len)
-     char const *start;
-     int len;
+xtensa_literal_prefix (char const *start, int len)
 {
-  segT s_now;			/* Storage for the current seg and subseg.  */
-  subsegT ss_now;
-  char *name;			/* Pointer to the name itself.  */
-  char *newname;
-
-  if (!use_literal_section)
-    return;
-
-  /* Store away the current section and subsection.  */
-  s_now = now_seg;
-  ss_now = now_subseg;
+  char *name, *linkonce_suffix;
+  char *newname, *newname4;
+  size_t linkonce_len;
 
   /* Get a null-terminated copy of the name.  */
   name = xmalloc (len + 1);
@@ -1560,40 +1480,227 @@ xtensa_literal_prefix (start, len)
 
   /* Allocate the sections (interesting note: the memory pointing to
      the name is actually used for the name by the new section). */
+
   newname = xmalloc (len + strlen (".literal") + 1);
-  strcpy (newname, name);
-  strcpy (newname + len, ".literal");
+  newname4 = xmalloc (len + strlen (".lit4") + 1);
+
+  linkonce_len = sizeof (".gnu.linkonce.") - 1;
+  if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0
+      && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0)
+    {
+      strcpy (newname, ".gnu.linkonce.literal");
+      strcpy (newname4, ".gnu.linkonce.lit4");
 
-  /* Note that retrieve_literal_seg does not create a segment if 
+      strcat (newname, linkonce_suffix);
+      strcat (newname4, linkonce_suffix);
+    }
+  else
+    {
+      int suffix_pos = len;
+
+      /* If the section name ends with ".text", then replace that suffix
+	 instead of appending an additional suffix.  */
+      if (len >= 5 && strcmp (name + len - 5, ".text") == 0)
+	suffix_pos -= 5;
+
+      strcpy (newname, name);
+      strcpy (newname4, name);
+
+      strcpy (newname + suffix_pos, ".literal");
+      strcpy (newname4 + suffix_pos, ".lit4");
+    }
+
+  /* Note that cache_literal_section does not create a segment if
      it already exists.  */
-  default_lit_sections.lit_seg = NULL;	/* retrieved on demand */
+  default_lit_sections.lit_seg = NULL;
+  default_lit_sections.lit4_seg = NULL;
 
   /* Canonicalizing section names allows renaming literal
      sections to occur correctly.  */
-  default_lit_sections.lit_seg_name =
-    tc_canonicalize_symbol_name (newname);
+  default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname);
+  default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4);
 
   free (name);
+}
+
+
+/* Support ".frequency branch_target_frequency fall_through_frequency".  */
+
+static void
+xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED)
+{
+  float fall_through_f, target_f;
+
+  fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer);
+  if (fall_through_f < 0)
+    {
+      as_bad (_("fall through frequency must be greater than 0"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  target_f = (float) strtod (input_line_pointer, &input_line_pointer);
+  if (target_f < 0)
+    {
+      as_bad (_("branch target frequency must be greater than 0"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f);
+
+  demand_empty_rest_of_line ();
+}
 
-  /* Restore the current section and subsection and set the 
-     generation into the old segment.  */
-  subseg_set (s_now, ss_now);
+
+/* Like normal .long/.short/.word, except support @plt, etc.
+   Clobbers input_line_pointer, checks end-of-line.  */
+
+static void
+xtensa_elf_cons (int nbytes)
+{
+  expressionS exp;
+  bfd_reloc_code_real_type reloc;
+
+  md_flush_pending_output ();
+
+  if (cur_vinsn.inside_bundle)
+    as_bad (_("directives are not valid inside bundles"));
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+
+  do
+    {
+      expression (&exp);
+      if (exp.X_op == O_symbol
+	  && *input_line_pointer == '@'
+	  && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp))
+	      != BFD_RELOC_NONE))
+	{
+	  reloc_howto_type *reloc_howto =
+	    bfd_reloc_type_lookup (stdoutput, reloc);
+
+	  if (reloc == BFD_RELOC_UNUSED || !reloc_howto)
+	    as_bad (_("unsupported relocation"));
+	  else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP
+		    && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
+		   || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
+		       && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT))
+	    as_bad (_("opcode-specific %s relocation used outside "
+		      "an instruction"), reloc_howto->name);
+	  else if (nbytes != (int) bfd_get_reloc_size (reloc_howto))
+	    as_bad (_("%s relocations do not fit in %d bytes"),
+		    reloc_howto->name, nbytes);
+	  else
+	    {
+	      char *p = frag_more ((int) nbytes);
+	      xtensa_set_frag_assembly_state (frag_now);
+	      fix_new_exp (frag_now, p - frag_now->fr_literal,
+			   nbytes, &exp, 0, reloc);
+	    }
+	}
+      else
+	emit_expr (&exp, (unsigned int) nbytes);
+    }
+  while (*input_line_pointer++ == ',');
+
+  input_line_pointer--;		/* Put terminator back into stream.  */
+  demand_empty_rest_of_line ();
 }
 
 
 /* Parsing and Idiom Translation.  */
 
+/* Parse @plt, etc. and return the desired relocation.  */
+static bfd_reloc_code_real_type
+xtensa_elf_suffix (char **str_p, expressionS *exp_p)
+{
+  struct map_bfd
+  {
+    char *string;
+    int length;
+    bfd_reloc_code_real_type reloc;
+  };
+
+  char ident[20];
+  char *str = *str_p;
+  char *str2;
+  int ch;
+  int len;
+  struct map_bfd *ptr;
+
+#define MAP(str,reloc) { str, sizeof (str) - 1, reloc }
+
+  static struct map_bfd mapping[] =
+  {
+    MAP ("l",		BFD_RELOC_LO16),
+    MAP ("h",		BFD_RELOC_HI16),
+    MAP ("plt",		BFD_RELOC_XTENSA_PLT),
+    { (char *) 0, 0,	BFD_RELOC_UNUSED }
+  };
+
+  if (*str++ != '@')
+    return BFD_RELOC_NONE;
+
+  for (ch = *str, str2 = ident;
+       (str2 < ident + sizeof (ident) - 1
+	&& (ISALNUM (ch) || ch == '@'));
+       ch = *++str)
+    {
+      *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch);
+    }
+
+  *str2 = '\0';
+  len = str2 - ident;
+
+  ch = ident[0];
+  for (ptr = &mapping[0]; ptr->length > 0; ptr++)
+    if (ch == ptr->string[0]
+	&& len == ptr->length
+	&& memcmp (ident, ptr->string, ptr->length) == 0)
+      {
+	/* Now check for "identifier@suffix+constant".  */
+	if (*str == '-' || *str == '+')
+	  {
+	    char *orig_line = input_line_pointer;
+	    expressionS new_exp;
+
+	    input_line_pointer = str;
+	    expression (&new_exp);
+	    if (new_exp.X_op == O_constant)
+	      {
+		exp_p->X_add_number += new_exp.X_add_number;
+		str = input_line_pointer;
+	      }
+
+	    if (&input_line_pointer != str_p)
+	      input_line_pointer = orig_line;
+	  }
+
+	*str_p = str;
+	return ptr->reloc;
+      }
+
+  return BFD_RELOC_UNUSED;
+}
+
+
 static const char *
-expression_end (name)
-     const char *name;
+expression_end (const char *name)
 {
   while (1)
     {
       switch (*name)
 	{
+	case '}':
 	case ';':
 	case '\0':
 	case ',':
+	case ':':
 	  return name;
 	case ' ':
 	case '\t':
@@ -1609,8 +1716,7 @@ expression_end (name)
 #define ERROR_REG_NUM ((unsigned) -1)
 
 static unsigned
-tc_get_register (prefix)
-     const char *prefix;
+tc_get_register (const char *prefix)
 {
   unsigned reg;
   const char *next_expr;
@@ -1664,45 +1770,64 @@ tc_get_register (prefix)
 }
 
 
-#define PLT_SUFFIX "@PLT"
-#define plt_suffix "@plt"
-
 static void
-expression_maybe_register (opnd, tok)
-     xtensa_operand opnd;
-     expressionS *tok;
+expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok)
 {
-  char *kind = xtensa_operand_kind (opnd);
+  xtensa_isa isa = xtensa_default_isa;
 
-  if ((strlen (kind) == 1)
-      && (*kind == 'l' || *kind == 'L' || *kind == 'i' || *kind == 'r'))
+  /* Check if this is an immediate operand.  */
+  if (xtensa_operand_is_register (isa, opc, opnd) == 0)
     {
+      bfd_reloc_code_real_type reloc;
       segT t = expression (tok);
-      if (t == absolute_section && operand_is_pcrel_label (opnd))
+      if (t == absolute_section
+	  && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
 	{
 	  assert (tok->X_op == O_constant);
 	  tok->X_op = O_symbol;
 	  tok->X_add_symbol = &abs_symbol;
 	}
-      if (tok->X_op == O_symbol 
-	  && (!strncmp (input_line_pointer, PLT_SUFFIX,
-			strlen (PLT_SUFFIX) - 1)
-	      || !strncmp (input_line_pointer, plt_suffix,
-			   strlen (plt_suffix) - 1)))
+
+      if ((tok->X_op == O_constant || tok->X_op == O_symbol)
+	  && (reloc = xtensa_elf_suffix (&input_line_pointer, tok))
+	  && (reloc != BFD_RELOC_NONE))
 	{
-	  symbol_get_tc (tok->X_add_symbol)->plt = 1;
-	  input_line_pointer += strlen (plt_suffix);
+	  switch (reloc)
+	    {
+	      default:
+	      case BFD_RELOC_UNUSED:
+		as_bad (_("unsupported relocation"));
+	        break;
+
+	      case BFD_RELOC_XTENSA_PLT:
+		tok->X_op = O_pltrel;
+		break;
+
+	      case BFD_RELOC_LO16:
+		if (tok->X_op == O_constant)
+		  tok->X_add_number &= 0xffff;
+		else
+		  tok->X_op = O_lo16;
+		break;
+
+	      case BFD_RELOC_HI16:
+		if (tok->X_op == O_constant)
+		  tok->X_add_number = ((unsigned) tok->X_add_number) >> 16;
+		else
+		  tok->X_op = O_hi16;
+		break;
+	    }
 	}
     }
   else
     {
-      unsigned reg = tc_get_register (kind);
+      xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
+      unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf));
 
       if (reg != ERROR_REG_NUM)	/* Already errored */
 	{
 	  uint32 buf = reg;
-	  if ((xtensa_operand_encode (opnd, &buf) != xtensa_encode_result_ok)
-	      || (reg != xtensa_operand_decode (opnd, buf)))
+	  if (xtensa_operand_encode (isa, opc, opnd, &buf))
 	    as_bad (_("register number out of range"));
 	}
 
@@ -1716,18 +1841,17 @@ expression_maybe_register (opnd, tok)
 /* Split up the arguments for an opcode or pseudo-op.  */
 
 static int
-tokenize_arguments (args, str)
-     char **args;
-     char *str;
+tokenize_arguments (char **args, char *str)
 {
   char *old_input_line_pointer;
   bfd_boolean saw_comma = FALSE;
   bfd_boolean saw_arg = FALSE;
+  bfd_boolean saw_colon = FALSE;
   int num_args = 0;
   char *arg_end, *arg;
   int arg_len;
-  
-  /* Save and restore input_line_pointer around this function.  */ 
+
+  /* Save and restore input_line_pointer around this function.  */
   old_input_line_pointer = input_line_pointer;
   input_line_pointer = str;
 
@@ -1737,110 +1861,239 @@ tokenize_arguments (args, str)
       switch (*input_line_pointer)
 	{
 	case '\0':
+	case '}':
 	  goto fini;
 
+	case ':':
+	  input_line_pointer++;
+	  if (saw_comma || saw_colon || !saw_arg)
+	    goto err;
+	  saw_colon = TRUE;
+	  break;
+
 	case ',':
 	  input_line_pointer++;
-	  if (saw_comma || !saw_arg)
+	  if (saw_comma || saw_colon || !saw_arg)
 	    goto err;
 	  saw_comma = TRUE;
 	  break;
 
 	default:
-	  if (!saw_comma && saw_arg)
+	  if (!saw_comma && !saw_colon && saw_arg)
 	    goto err;
 
 	  arg_end = input_line_pointer + 1;
 	  while (!expression_end (arg_end))
 	    arg_end += 1;
- 
+
 	  arg_len = arg_end - input_line_pointer;
-	  arg = (char *) xmalloc (arg_len + 1);
+	  arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1);
 	  args[num_args] = arg;
 
+	  if (saw_colon)
+	    *arg++ = ':';
 	  strncpy (arg, input_line_pointer, arg_len);
 	  arg[arg_len] = '\0';
- 
+
 	  input_line_pointer = arg_end;
 	  num_args += 1;
-	  saw_comma = FALSE; 
-	  saw_arg = TRUE; 
+	  saw_comma = FALSE;
+	  saw_colon = FALSE;
+	  saw_arg = TRUE;
 	  break;
 	}
     }
 
 fini:
-  if (saw_comma)
+  if (saw_comma || saw_colon)
     goto err;
   input_line_pointer = old_input_line_pointer;
   return num_args;
 
 err:
+  if (saw_comma)
+    as_bad (_("extra comma"));
+  else if (saw_colon)
+    as_bad (_("extra colon"));
+  else if (!saw_arg)
+    as_bad (_("missing argument"));
+  else
+    as_bad (_("missing comma or colon"));
   input_line_pointer = old_input_line_pointer;
   return -1;
 }
 
 
-/* Parse the arguments to an opcode.  Return true on error.  */
+/* Parse the arguments to an opcode.  Return TRUE on error.  */
 
 static bfd_boolean
-parse_arguments (insn, num_args, arg_strings)
-     TInsn *insn;
-     int num_args;
-     char **arg_strings;
+parse_arguments (TInsn *insn, int num_args, char **arg_strings)
 {
-  expressionS *tok = insn->tok;
+  expressionS *tok, *last_tok;
   xtensa_opcode opcode = insn->opcode;
   bfd_boolean had_error = TRUE;
-  xtensa_isa isa = xtensa_default_isa; 
-  int n;
+  xtensa_isa isa = xtensa_default_isa;
+  int n, num_regs = 0;
   int opcode_operand_count;
-  int actual_operand_count = 0;
-  xtensa_operand opnd = NULL; 
+  int opnd_cnt, last_opnd_cnt;
+  unsigned int next_reg = 0;
   char *old_input_line_pointer;
 
   if (insn->insn_type == ITYPE_LITERAL)
     opcode_operand_count = 1;
   else
-    opcode_operand_count = xtensa_num_operands (isa, opcode);
+    opcode_operand_count = xtensa_opcode_num_operands (isa, opcode);
 
+  tok = insn->tok;
   memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS);
 
   /* Save and restore input_line_pointer around this function.  */
-  old_input_line_pointer = input_line_pointer; 
+  old_input_line_pointer = input_line_pointer;
+
+  last_tok = 0;
+  last_opnd_cnt = -1;
+  opnd_cnt = 0;
+
+  /* Skip invisible operands.  */
+  while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0)
+    {
+      opnd_cnt += 1;
+      tok++;
+    }
 
   for (n = 0; n < num_args; n++)
-    { 
+    {
       input_line_pointer = arg_strings[n];
+      if (*input_line_pointer == ':')
+	{
+	  xtensa_regfile opnd_rf;
+	  input_line_pointer++;
+	  if (num_regs == 0)
+	    goto err;
+	  assert (opnd_cnt > 0);
+	  num_regs--;
+	  opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt);
+	  if (next_reg
+	      != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)))
+	    as_warn (_("incorrect register number, ignoring"));
+	  next_reg++;
+	}
+      else
+	{
+	  if (opnd_cnt >= opcode_operand_count)
+	    {
+	      as_warn (_("too many arguments"));
+	      goto err;
+	    }
+	  assert (opnd_cnt < MAX_INSN_ARGS);
 
-      if (actual_operand_count >= opcode_operand_count)
-	{ 
-	  as_warn (_("too many arguments")); 
-	  goto err;
-	} 
-      assert (actual_operand_count < MAX_INSN_ARGS);
+	  expression_maybe_register (opcode, opnd_cnt, tok);
+	  next_reg = tok->X_add_number + 1;
 
-      opnd = xtensa_get_operand (isa, opcode, actual_operand_count); 
-      expression_maybe_register (opnd, tok);
+	  if (tok->X_op == O_illegal || tok->X_op == O_absent)
+	    goto err;
+	  if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1)
+	    {
+	      num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1;
+	      /* minus 1 because we are seeing one right now */
+	    }
+	  else
+	    num_regs = 0;
+
+	  last_tok = tok;
+	  last_opnd_cnt = opnd_cnt;
+
+	  do
+	    {
+	      opnd_cnt += 1;
+	      tok++;
+	    }
+	  while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0);
+	}
+    }
 
-      if (tok->X_op == O_illegal || tok->X_op == O_absent) 
-	goto err; 
-      actual_operand_count++;
-      tok++; 
-    } 
+  if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1))
+    goto err;
 
   insn->ntok = tok - insn->tok;
-  had_error = FALSE; 
+  had_error = FALSE;
 
  err:
-  input_line_pointer = old_input_line_pointer; 
+  input_line_pointer = old_input_line_pointer;
   return had_error;
 }
 
 
+static int
+get_invisible_operands (TInsn *insn)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  static xtensa_insnbuf slotbuf = NULL;
+  xtensa_format fmt;
+  xtensa_opcode opc = insn->opcode;
+  int slot, opnd, fmt_found;
+  unsigned val;
+
+  if (!slotbuf)
+    slotbuf = xtensa_insnbuf_alloc (isa);
+
+  /* Find format/slot where this can be encoded.  */
+  fmt_found = 0;
+  slot = 0;
+  for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
+    {
+      for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
+	{
+	  if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0)
+	    {
+	      fmt_found = 1;
+	      break;
+	    }
+	}
+      if (fmt_found) break;
+    }
+
+  if (!fmt_found)
+    {
+      as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc));
+      return -1;
+    }
+
+  /* First encode all the visible operands
+     (to deal with shared field operands).  */
+  for (opnd = 0; opnd < insn->ntok; opnd++)
+    {
+      if (xtensa_operand_is_visible (isa, opc, opnd) == 1
+	  && (insn->tok[opnd].X_op == O_register
+	      || insn->tok[opnd].X_op == O_constant))
+	{
+	  val = insn->tok[opnd].X_add_number;
+	  xtensa_operand_encode (isa, opc, opnd, &val);
+	  xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val);
+	}
+    }
+
+  /* Then pull out the values for the invisible ones.  */
+  for (opnd = 0; opnd < insn->ntok; opnd++)
+    {
+      if (xtensa_operand_is_visible (isa, opc, opnd) == 0)
+	{
+	  xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val);
+	  xtensa_operand_decode (isa, opc, opnd, &val);
+	  insn->tok[opnd].X_add_number = val;
+	  if (xtensa_operand_is_register (isa, opc, opnd) == 1)
+	    insn->tok[opnd].X_op = O_register;
+	  else
+	    insn->tok[opnd].X_op = O_constant;
+	}
+    }
+
+  return 0;
+}
+
+
 static void
-xg_reverse_shift_count (cnt_argp)
-     char **cnt_argp;
+xg_reverse_shift_count (char **cnt_argp)
 {
   char *cnt_arg, *new_arg;
   cnt_arg = *cnt_argp;
@@ -1858,9 +2111,7 @@ xg_reverse_shift_count (cnt_argp)
    in *valp.  */
 
 static int
-xg_arg_is_constant (arg, valp)
-     char *arg;
-     offsetT *valp;
+xg_arg_is_constant (char *arg, offsetT *valp)
 {
   expressionS exp;
   char *save_ptr = input_line_pointer;
@@ -1880,9 +2131,7 @@ xg_arg_is_constant (arg, valp)
 
 
 static void
-xg_replace_opname (popname, newop)
-     char **popname;
-     char *newop;
+xg_replace_opname (char **popname, char *newop)
 {
   free (*popname);
   *popname = (char *) xmalloc (strlen (newop) + 1);
@@ -1891,15 +2140,14 @@ xg_replace_opname (popname, newop)
 
 
 static int
-xg_check_num_args (pnum_args, expected_num, opname, arg_strings)
-     int *pnum_args;
-     int expected_num; 
-     char *opname;
-     char **arg_strings;
+xg_check_num_args (int *pnum_args,
+		   int expected_num,
+		   char *opname,
+		   char **arg_strings)
 {
   int num_args = *pnum_args;
 
-  if (num_args < expected_num) 
+  if (num_args < expected_num)
     {
       as_bad (_("not enough operands (%d) for '%s'; expected %d"),
 	      num_args, opname, expected_num);
@@ -1923,56 +2171,160 @@ xg_check_num_args (pnum_args, expected_num, opname, arg_strings)
 }
 
 
+/* If the register is not specified as part of the opcode,
+   then get it from the operand and move it to the opcode.  */
+
 static int
-xg_translate_sysreg_op (popname, pnum_args, arg_strings)
-     char **popname;
-     int *pnum_args;
-     char **arg_strings;
+xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings)
 {
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_sysreg sr;
   char *opname, *new_opname;
-  offsetT val;
-  bfd_boolean has_underbar = FALSE;
+  const char *sr_name;
+  int is_user, is_write;
 
   opname = *popname;
   if (*opname == '_')
+    opname += 1;
+  is_user = (opname[1] == 'u');
+  is_write = (opname[0] == 'w');
+
+  /* Opname == [rw]ur or [rwx]sr... */
+
+  if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
+    return -1;
+
+  /* Check if the argument is a symbolic register name.  */
+  sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]);
+  /* Handle WSR to "INTSET" as a special case.  */
+  if (sr == XTENSA_UNDEFINED && is_write && !is_user
+      && !strcasecmp (arg_strings[1], "intset"))
+    sr = xtensa_sysreg_lookup_name (isa, "interrupt");
+  if (sr == XTENSA_UNDEFINED
+      || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user)
+    {
+      /* Maybe it's a register number.... */
+      offsetT val;
+      if (!xg_arg_is_constant (arg_strings[1], &val))
+	{
+	  as_bad (_("invalid register '%s' for '%s' instruction"),
+		  arg_strings[1], opname);
+	  return -1;
+	}
+      sr = xtensa_sysreg_lookup (isa, val, is_user);
+      if (sr == XTENSA_UNDEFINED)
+	{
+	  as_bad (_("invalid register number (%ld) for '%s' instruction"),
+		  (long) val, opname);
+	  return -1;
+	}
+    }
+
+  /* Remove the last argument, which is now part of the opcode.  */
+  free (arg_strings[1]);
+  arg_strings[1] = 0;
+  *pnum_args = 1;
+
+  /* Translate the opcode.  */
+  sr_name = xtensa_sysreg_name (isa, sr);
+  /* Another special case for "WSR.INTSET"....  */
+  if (is_write && !is_user && !strcasecmp ("interrupt", sr_name))
+    sr_name = "intset";
+  new_opname = (char *) xmalloc (strlen (sr_name) + 6);
+  sprintf (new_opname, "%s.%s", *popname, sr_name);
+  free (*popname);
+  *popname = new_opname;
+
+  return 0;
+}
+
+
+static int
+xtensa_translate_old_userreg_ops (char **popname)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_sysreg sr;
+  char *opname, *new_opname;
+  const char *sr_name;
+  bfd_boolean has_underbar = FALSE;
+
+  opname = *popname;
+  if (opname[0] == '_')
     {
       has_underbar = TRUE;
       opname += 1;
     }
 
-  /* Opname == [rw]ur... */
-
-  if (opname[3] == '\0')
+  sr = xtensa_sysreg_lookup_name (isa, opname + 1);
+  if (sr != XTENSA_UNDEFINED)
+    {
+      /* The new default name ("nnn") is different from the old default
+	 name ("URnnn").  The old default is handled below, and we don't
+	 want to recognize [RW]nnn, so do nothing if the name is the (new)
+	 default.  */
+      static char namebuf[10];
+      sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr));
+      if (strcmp (namebuf, opname + 1) == 0)
+	return 0;
+    }
+  else
     {
-      /* If the register is not specified as part of the opcode,
-	 then get it from the operand and move it to the opcode.  */
+      offsetT val;
+      char *end;
 
-      if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
-	return -1;
+      /* Only continue if the reg name is "URnnn".  */
+      if (opname[1] != 'u' || opname[2] != 'r')
+	return 0;
+      val = strtoul (opname + 3, &end, 10);
+      if (*end != '\0')
+	return 0;
 
-      if (!xg_arg_is_constant (arg_strings[1], &val))
+      sr = xtensa_sysreg_lookup (isa, val, 1);
+      if (sr == XTENSA_UNDEFINED)
 	{
-	  as_bad (_("register number for `%s' is not a constant"), opname);
-	  return -1;
-	}
-      if ((unsigned) val > 255)
-	{
-	  as_bad (_("register number (%ld) for `%s' is out of range"),
-		  val, opname);
+	  as_bad (_("invalid register number (%ld) for '%s'"),
+		  (long) val, opname);
 	  return -1;
 	}
+    }
 
-      /* Remove the last argument, which is now part of the opcode.  */
-      free (arg_strings[1]);
-      arg_strings[1] = 0;
-      *pnum_args = 1;
+  /* Translate the opcode.  */
+  sr_name = xtensa_sysreg_name (isa, sr);
+  new_opname = (char *) xmalloc (strlen (sr_name) + 6);
+  sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""),
+	   opname[0], sr_name);
+  free (*popname);
+  *popname = new_opname;
+
+  return 0;
+}
 
-      /* Translate the opcode.  */
-      new_opname = (char *) xmalloc (8);
-      sprintf (new_opname, "%s%cur%u", (has_underbar ? "_" : ""),
-	       opname[0], (unsigned) val);
-      free (*popname);
-      *popname = new_opname;
+
+static int
+xtensa_translate_zero_immed (char *old_op,
+			     char *new_op,
+			     char **popname,
+			     int *pnum_args,
+			     char **arg_strings)
+{
+  char *opname;
+  offsetT val;
+
+  opname = *popname;
+  assert (opname[0] != '_');
+
+  if (strcmp (opname, old_op) != 0)
+    return 0;
+
+  if (xg_check_num_args (pnum_args, 3, opname, arg_strings))
+    return -1;
+  if (xg_arg_is_constant (arg_strings[1], &val) && val == 0)
+    {
+      xg_replace_opname (popname, new_op);
+      free (arg_strings[1]);
+      arg_strings[1] = arg_strings[2];
+      arg_strings[2] = 0;
+      *pnum_args = 2;
     }
 
   return 0;
@@ -1983,14 +2335,14 @@ xg_translate_sysreg_op (popname, pnum_args, arg_strings)
    Returns non-zero if an error was found.  */
 
 static int
-xg_translate_idioms (popname, pnum_args, arg_strings)
-     char **popname;
-     int *pnum_args;
-     char **arg_strings;
+xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings)
 {
   char *opname = *popname;
   bfd_boolean has_underbar = FALSE;
 
+  if (cur_vinsn.inside_bundle)
+    return 0;
+
   if (*opname == '_')
     {
       has_underbar = TRUE;
@@ -1999,7 +2351,7 @@ xg_translate_idioms (popname, pnum_args, arg_strings)
 
   if (strcmp (opname, "mov") == 0)
     {
-      if (!has_underbar && code_density_available ())
+      if (use_transform () && !has_underbar && density_supported)
 	xg_replace_opname (popname, "mov.n");
       else
 	{
@@ -2033,9 +2385,10 @@ xg_translate_idioms (popname, pnum_args, arg_strings)
       return 0;
     }
 
-  if (strcmp (opname, "nop") == 0)
+  if (xtensa_nop_opcode == XTENSA_UNDEFINED
+      && strcmp (opname, "nop") == 0)
     {
-      if (!has_underbar && code_density_available ())
+      if (use_transform () && !has_underbar && density_supported)
 	xg_replace_opname (popname, "nop.n");
       else
 	{
@@ -2053,80 +2406,39 @@ xg_translate_idioms (popname, pnum_args, arg_strings)
       return 0;
     }
 
-  if ((opname[0] == 'r' || opname[0] == 'w')
-      && opname[1] == 'u'
-      && opname[2] == 'r')
+  /* Recognize [RW]UR and [RWX]SR.  */
+  if ((((opname[0] == 'r' || opname[0] == 'w')
+	&& (opname[1] == 'u' || opname[1] == 's'))
+       || (opname[0] == 'x' && opname[1] == 's'))
+      && opname[2] == 'r'
+      && opname[3] == '\0')
     return xg_translate_sysreg_op (popname, pnum_args, arg_strings);
 
+  /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and
+     [RW]<name> if <name> is the non-default name of a user register.  */
+  if ((opname[0] == 'r' || opname[0] == 'w')
+      && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED)
+    return xtensa_translate_old_userreg_ops (popname);
 
-  /* WIDENING DENSITY OPCODES
-
-     questionable relaxations (widening) from old "tai" idioms:
-
-       ADD.N --> ADD
-       BEQZ.N --> BEQZ
-       RET.N --> RET
-       RETW.N --> RETW
-       MOVI.N --> MOVI
-       MOV.N --> MOV
-       NOP.N --> NOP
-
-     Note: this incomplete list was imported to match the "tai"
-     behavior; other density opcodes are not handled.
-
-     The xtensa-relax code may know how to do these but it doesn't do
-     anything when these density opcodes appear inside a no-density
-     region.  Somehow GAS should either print an error when that happens
-     or do the widening.  The old "tai" behavior was to do the widening.
-     For now, I'll make it widen but print a warning.
-
-     FIXME: GAS needs to detect density opcodes inside no-density
-     regions and treat them as errors.  This code should be removed
-     when that is done.  */
-
-  if (use_generics ()
-      && !has_underbar
-      && density_supported
-      && !code_density_available ())
+  /* Relax branches that don't allow comparisons against an immediate value
+     of zero to the corresponding branches with implicit zero immediates.  */
+  if (!has_underbar && use_transform ())
     {
-      if (strcmp (opname, "add.n") == 0)
-	xg_replace_opname (popname, "add");
-
-      else if (strcmp (opname, "beqz.n") == 0)
-	xg_replace_opname (popname, "beqz");
-
-      else if (strcmp (opname, "ret.n") == 0)
-	xg_replace_opname (popname, "ret");
-
-      else if (strcmp (opname, "retw.n") == 0)
-	xg_replace_opname (popname, "retw");
+      if (xtensa_translate_zero_immed ("bnei", "bnez", popname,
+				       pnum_args, arg_strings))
+	return -1;
 
-      else if (strcmp (opname, "movi.n") == 0)
-	xg_replace_opname (popname, "movi");
+      if (xtensa_translate_zero_immed ("beqi", "beqz", popname,
+				       pnum_args, arg_strings))
+	return -1;
 
-      else if (strcmp (opname, "mov.n") == 0)
-	{
-	  if (xg_check_num_args (pnum_args, 2, opname, arg_strings))
-	    return -1;
-	  xg_replace_opname (popname, "or");
-	  arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1);
-	  strcpy (arg_strings[2], arg_strings[1]);
-	  *pnum_args = 3;
-	}
+      if (xtensa_translate_zero_immed ("bgei", "bgez", popname,
+				       pnum_args, arg_strings))
+	return -1;
 
-      else if (strcmp (opname, "nop.n") == 0)
-	{
-	  if (xg_check_num_args (pnum_args, 0, opname, arg_strings))
-	    return -1;
-	  xg_replace_opname (popname, "or");
-	  arg_strings[0] = (char *) xmalloc (3);
-	  arg_strings[1] = (char *) xmalloc (3);
-	  arg_strings[2] = (char *) xmalloc (3);
-	  strcpy (arg_strings[0], "a1");
-	  strcpy (arg_strings[1], "a1");
-	  strcpy (arg_strings[2], "a1");
-	  *pnum_args = 3;
-	}
+      if (xtensa_translate_zero_immed ("blti", "bltz", popname,
+				       pnum_args, arg_strings))
+	return -1;
     }
 
   return 0;
@@ -2135,531 +2447,565 @@ xg_translate_idioms (popname, pnum_args, arg_strings)
 
 /* Functions for dealing with the Xtensa ISA.  */
 
-/* Return true if the given operand is an immed or target instruction,
-   i.e., has a reloc associated with it.  Currently, this is only true
-   if the operand kind is "i, "l" or "L".  */
-
-static bfd_boolean
-operand_is_immed (opnd)
-     xtensa_operand opnd;
-{
-  const char *opkind = xtensa_operand_kind (opnd);
-  if (opkind[0] == '\0' || opkind[1] != '\0')
-    return FALSE;
-  switch (opkind[0])
-    {
-    case 'i':
-    case 'l':
-    case 'L':
-      return TRUE;
-    }
-  return FALSE;
-}
-
-
-/* Return true if the given operand is a pc-relative label.  This is
-   true for "l", "L", and "r" operand kinds.  */
-
-bfd_boolean
-operand_is_pcrel_label (opnd)
-     xtensa_operand opnd;
-{
-  const char *opkind = xtensa_operand_kind (opnd);
-  if (opkind[0] == '\0' || opkind[1] != '\0')
-    return FALSE;
-  switch (opkind[0])
-    {
-    case 'r':
-    case 'l':
-    case 'L':
-      return TRUE;
-    }
-  return FALSE;
-}
-
-
 /* Currently the assembler only allows us to use a single target per
    fragment.  Because of this, only one operand for a given
-   instruction may be symbolic.  If there is an operand of kind "lrL",
+   instruction may be symbolic.  If there is a PC-relative operand,
    the last one is chosen.  Otherwise, the result is the number of the
-   last operand of type "i", and if there are none of those, we fail
-   and return -1.  */
+   last immediate operand, and if there are none of those, we fail and
+   return -1.  */
 
-int
-get_relaxable_immed (opcode)
-     xtensa_opcode opcode;
+static int
+get_relaxable_immed (xtensa_opcode opcode)
 {
   int last_immed = -1;
   int noperands, opi;
-  xtensa_operand operand;
 
   if (opcode == XTENSA_UNDEFINED)
     return -1;
 
-  noperands = xtensa_num_operands (xtensa_default_isa, opcode);
+  noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode);
   for (opi = noperands - 1; opi >= 0; opi--)
     {
-      operand = xtensa_get_operand (xtensa_default_isa, opcode, opi);
-      if (operand_is_pcrel_label (operand))
+      if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0)
+	continue;
+      if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1)
 	return opi;
-      if (last_immed == -1 && operand_is_immed (operand))
+      if (last_immed == -1
+	  && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0)
 	last_immed = opi;
     }
   return last_immed;
 }
 
 
-xtensa_opcode
-get_opcode_from_buf (buf)
-     const char *buf;
+static xtensa_opcode
+get_opcode_from_buf (const char *buf, int slot)
 {
   static xtensa_insnbuf insnbuf = NULL;
-  xtensa_opcode opcode;
+  static xtensa_insnbuf slotbuf = NULL;
   xtensa_isa isa = xtensa_default_isa;
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (isa);
-
-  xtensa_insnbuf_from_chars (isa, insnbuf, buf);
-  opcode = xtensa_decode_insn (isa, insnbuf);
-  return opcode;
-}
-
-
-static bfd_boolean
-is_direct_call_opcode (opcode)
-     xtensa_opcode opcode;
-{
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
-
-  return (opcode == xtensa_call0_opcode
-	  || opcode == xtensa_call4_opcode
-	  || opcode == xtensa_call8_opcode
-	  || opcode == xtensa_call12_opcode);
-}
-
-
-static bfd_boolean
-is_call_opcode (opcode)
-     xtensa_opcode opcode;
-{
-  if (is_direct_call_opcode (opcode))
-    return TRUE;
-
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
-
-  return (opcode == xtensa_callx0_opcode
-	  || opcode == xtensa_callx4_opcode
-	  || opcode == xtensa_callx8_opcode
-	  || opcode == xtensa_callx12_opcode);
-}
+  xtensa_format fmt;
 
+  if (!insnbuf)
+    {
+      insnbuf = xtensa_insnbuf_alloc (isa);
+      slotbuf = xtensa_insnbuf_alloc (isa);
+    }
 
-/* Return true if the opcode is an entry opcode.  This is used because
-   "entry" adds an implicit ".align 4" and also the entry instruction
-   has an extra check for an operand value.  */
+  xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+  if (fmt == XTENSA_UNDEFINED)
+    return XTENSA_UNDEFINED;
 
-static bfd_boolean
-is_entry_opcode (opcode)
-     xtensa_opcode opcode;
-{
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
+  if (slot >= xtensa_format_num_slots (isa, fmt))
+    return XTENSA_UNDEFINED;
 
-  return (opcode == xtensa_entry_opcode);
+  xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
+  return xtensa_opcode_decode (isa, fmt, slot, slotbuf);
 }
 
 
-/* Return true if it is one of the loop opcodes.  Loops are special
-   because they need automatic alignment and they have a relaxation so
-   complex that we hard-coded it.  */
+#ifdef TENSILICA_DEBUG
 
-static bfd_boolean
-is_loop_opcode (opcode)
-     xtensa_opcode opcode;
-{
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
+/* For debugging, print out the mapping of opcode numbers to opcodes.  */
 
-  return (opcode == xtensa_loop_opcode
-	  || opcode == xtensa_loopnez_opcode
-	  || opcode == xtensa_loopgtz_opcode);
-}
-
-
-static bfd_boolean
-is_the_loop_opcode (opcode)
-     xtensa_opcode opcode;
+static void
+xtensa_print_insn_table (void)
 {
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
+  int num_opcodes, num_operands;
+  xtensa_opcode opcode;
+  xtensa_isa isa = xtensa_default_isa;
 
-  return (opcode == xtensa_loop_opcode);
+  num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
+  for (opcode = 0; opcode < num_opcodes; opcode++)
+    {
+      int opn;
+      fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode));
+      num_operands = xtensa_opcode_num_operands (isa, opcode);
+      for (opn = 0; opn < num_operands; opn++)
+	{
+	  if (xtensa_operand_is_visible (isa, opcode, opn) == 0)
+	    continue;
+	  if (xtensa_operand_is_register (isa, opcode, opn) == 1)
+	    {
+	      xtensa_regfile opnd_rf =
+		xtensa_operand_regfile (isa, opcode, opn);
+	      fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf));
+	    }
+	  else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1)
+	    fputs ("[lLr] ", stderr);
+	  else
+	    fputs ("i ", stderr);
+	}
+      fprintf (stderr, "\n");
+    }
 }
 
 
-static bfd_boolean
-is_jx_opcode (opcode)
-     xtensa_opcode opcode;
+static void
+print_vliw_insn (xtensa_insnbuf vbuf)
 {
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
-
-  return (opcode == xtensa_jx_opcode);
-}
-
-
-/* Return true if the opcode is a retw or retw.n.
-   Needed to add nops to avoid a hardware interlock issue.  */
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_format f = xtensa_format_decode (isa, vbuf);
+  xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa);
+  int op;
 
-static bfd_boolean
-is_windowed_return_opcode (opcode)
-     xtensa_opcode opcode;
-{
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
+  fprintf (stderr, "format = %d\n", f);
 
-  return (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode);
+  for (op = 0; op < xtensa_format_num_slots (isa, f); op++)
+    {
+      xtensa_opcode opcode;
+      const char *opname;
+      int operands;
+
+      xtensa_format_get_slot (isa, f, op, vbuf, sbuf);
+      opcode = xtensa_opcode_decode (isa, f, op, sbuf);
+      opname = xtensa_opcode_name (isa, opcode);
+
+      fprintf (stderr, "op in slot %i is %s;\n", op, opname);
+      fprintf (stderr, "   operands = ");
+      for (operands = 0;
+	   operands < xtensa_opcode_num_operands (isa, opcode);
+	   operands++)
+	{
+	  unsigned int val;
+	  if (xtensa_operand_is_visible (isa, opcode, operands) == 0)
+	    continue;
+	  xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val);
+	  xtensa_operand_decode (isa, opcode, operands, &val);
+	  fprintf (stderr, "%d ", val);
+	}
+      fprintf (stderr, "\n");
+    }
+  xtensa_insnbuf_free (isa, sbuf);
 }
 
+#endif /* TENSILICA_DEBUG */
 
-/* Return true if the opcode type is "l" and the opcode is NOT a jump.  */
 
 static bfd_boolean
-is_conditional_branch_opcode (opcode)
-     xtensa_opcode opcode;
+is_direct_call_opcode (xtensa_opcode opcode)
 {
   xtensa_isa isa = xtensa_default_isa;
-  int num_ops, i;
+  int n, num_operands;
 
-  if (opcode == xtensa_j_opcode && opcode != XTENSA_UNDEFINED)
+  if (xtensa_opcode_is_call (isa, opcode) == 0)
     return FALSE;
 
-  num_ops = xtensa_num_operands (isa, opcode);
-  for (i = 0; i < num_ops; i++)
+  num_operands = xtensa_opcode_num_operands (isa, opcode);
+  for (n = 0; n < num_operands; n++)
     {
-      xtensa_operand operand = xtensa_get_operand (isa, opcode, i);
-      if (strcmp (xtensa_operand_kind (operand), "l") == 0)
+      if (xtensa_operand_is_register (isa, opcode, n) == 0
+	  && xtensa_operand_is_PCrelative (isa, opcode, n) == 1)
 	return TRUE;
     }
   return FALSE;
 }
 
 
-/* Return true if the given opcode is a conditional branch
-   instruction, i.e., currently this is true if the instruction 
-   is a jx or has an operand with 'l' type and is not a loop.  */
+/* Convert from BFD relocation type code to slot and operand number.
+   Returns non-zero on failure.  */
 
-bfd_boolean
-is_branch_or_jump_opcode (opcode)
-     xtensa_opcode opcode;
+static int
+decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt)
 {
-  int opn, op_count;
-
-  if (opcode == XTENSA_UNDEFINED)
-    return FALSE;
-
-  if (is_loop_opcode (opcode))
-    return FALSE;
-
-  if (is_jx_opcode (opcode))
-    return TRUE;
-
-  op_count = xtensa_num_operands (xtensa_default_isa, opcode);
-  for (opn = 0; opn < op_count; opn++)
+  if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP
+      && reloc <= BFD_RELOC_XTENSA_SLOT14_OP)
     {
-      xtensa_operand opnd =
-	xtensa_get_operand (xtensa_default_isa, opcode, opn);
-      const char *opkind = xtensa_operand_kind (opnd);
-      if (opkind && opkind[0] == 'l' && opkind[1] == '\0')
-	return TRUE;
+      *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP;
+      *is_alt = FALSE;
     }
-  return FALSE;
+  else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT
+      && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)
+    {
+      *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT;
+      *is_alt = TRUE;
+    }
+  else
+    return -1;
+
+  return 0;
 }
 
 
-/* Convert from operand numbers to BFD relocation type code.
-   Return BFD_RELOC_NONE on failure.  */
+/* Convert from slot number to BFD relocation type code for the
+   standard PC-relative relocations.  Return BFD_RELOC_NONE on
+   failure.  */
 
-bfd_reloc_code_real_type
-opnum_to_reloc (opnum)
-     int opnum;
+static bfd_reloc_code_real_type
+encode_reloc (int slot)
 {
-  switch (opnum)
-    {
-    case 0:
-      return BFD_RELOC_XTENSA_OP0;
-    case 1:
-      return BFD_RELOC_XTENSA_OP1;
-    case 2:
-      return BFD_RELOC_XTENSA_OP2;
-    default:
-      break;
-    }
-  return BFD_RELOC_NONE;
+  if (slot < 0 || slot > 14)
+    return BFD_RELOC_NONE;
+
+  return BFD_RELOC_XTENSA_SLOT0_OP + slot;
 }
 
 
-/* Convert from BFD relocation type code to operand number.
-   Return -1 on failure.  */
+/* Convert from slot numbers to BFD relocation type code for the
+   "alternate" relocations.  Return BFD_RELOC_NONE on failure.  */
 
-int
-reloc_to_opnum (reloc)
-     bfd_reloc_code_real_type reloc;
+static bfd_reloc_code_real_type
+encode_alt_reloc (int slot)
 {
-  switch (reloc)
-    {
-    case BFD_RELOC_XTENSA_OP0:
-      return 0;
-    case BFD_RELOC_XTENSA_OP1:
-      return 1;
-    case BFD_RELOC_XTENSA_OP2:
-      return 2;
-    default:
-      break;
-    }
-  return -1;
+  if (slot < 0 || slot > 14)
+    return BFD_RELOC_NONE;
+
+  return BFD_RELOC_XTENSA_SLOT0_ALT + slot;
 }
 
 
 static void
-xtensa_insnbuf_set_operand (insnbuf, opcode, operand, value, file, line)
-     xtensa_insnbuf insnbuf;
-     xtensa_opcode opcode;
-     xtensa_operand operand;
-     int32 value;
-     const char *file;
-     unsigned int line;
-{
-  xtensa_encode_result encode_result;
+xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf,
+			    xtensa_format fmt,
+			    int slot,
+			    xtensa_opcode opcode,
+			    int operand,
+			    uint32 value,
+			    const char *file,
+			    unsigned int line)
+{
   uint32 valbuf = value;
 
-  encode_result = xtensa_operand_encode (operand, &valbuf);
-
-  switch (encode_result)
+  if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
     {
-    case xtensa_encode_result_ok:
-      break;
-    case xtensa_encode_result_align:
-      as_bad_where ((char *) file, line,
-		    _("operand %d not properly aligned for '%s'"),
-		    value, xtensa_opcode_name (xtensa_default_isa, opcode));
-      break;
-    case xtensa_encode_result_not_in_table:
-      as_bad_where ((char *) file, line,
-		    _("operand %d not in immediate table for '%s'"),
-		    value, xtensa_opcode_name (xtensa_default_isa, opcode));
-      break;
-    case xtensa_encode_result_too_high:
-      as_bad_where ((char *) file, line,
-		    _("operand %d too large for '%s'"), value,
-		    xtensa_opcode_name (xtensa_default_isa, opcode));
-      break;
-    case xtensa_encode_result_too_low:
-      as_bad_where ((char *) file, line,
-		    _("operand %d too small for '%s'"), value,
-		    xtensa_opcode_name (xtensa_default_isa, opcode));
-      break;
-    case xtensa_encode_result_not_ok:
-      as_bad_where ((char *) file, line,
-		    _("operand %d is invalid for '%s'"), value,
-		    xtensa_opcode_name (xtensa_default_isa, opcode));
-      break;
-    default:
-      abort ();
+      if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand)
+	  == 1)
+	as_bad_where ((char *) file, line,
+		      _("operand %d of '%s' has out of range value '%u'"), 
+		      operand + 1,
+		      xtensa_opcode_name (xtensa_default_isa, opcode),
+		      value);
+      else
+	as_bad_where ((char *) file, line,
+		      _("operand %d of '%s' has invalid value '%u'"),
+		      operand + 1,
+		      xtensa_opcode_name (xtensa_default_isa, opcode),
+		      value);
+      return;
     }
 
-  xtensa_operand_set_field (operand, insnbuf, valbuf);
+  xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot,
+			    slotbuf, valbuf);
 }
 
 
 static uint32
-xtensa_insnbuf_get_operand (insnbuf, opcode, opnum)
-     xtensa_insnbuf insnbuf;
-     xtensa_opcode opcode;
-     int opnum;
+xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf,
+			    xtensa_format fmt,
+			    int slot,
+			    xtensa_opcode opcode,
+			    int opnum)
 {
-  xtensa_operand op = xtensa_get_operand (xtensa_default_isa, opcode, opnum);
-  return xtensa_operand_decode (op, xtensa_operand_get_field (op, insnbuf));
+  uint32 val = 0;
+  (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum,
+				   fmt, slot, slotbuf, &val);
+  (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val);
+  return val;
 }
 
+
+/* Checks for rules from xtensa-relax tables.  */
 
-static void
-xtensa_insnbuf_set_immediate_field (opcode, insnbuf, value, file, line)
-     xtensa_opcode opcode;
-     xtensa_insnbuf insnbuf;
-     int32 value;
-     const char *file;
-     unsigned int line;
+/* The routine xg_instruction_matches_option_term must return TRUE
+   when a given option term is true.  The meaning of all of the option
+   terms is given interpretation by this function.  This is needed when
+   an option depends on the state of a directive, but there are no such
+   options in use right now.  */
+
+static bfd_boolean
+xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED,
+				    const ReqOrOption *option)
 {
-  xtensa_isa isa = xtensa_default_isa;
-  int last_opnd = xtensa_num_operands (isa, opcode) - 1;
-  xtensa_operand operand = xtensa_get_operand (isa, opcode, last_opnd);
-  xtensa_insnbuf_set_operand (insnbuf, opcode, operand, value, file, line);
+  if (strcmp (option->option_name, "realnop") == 0
+      || strncmp (option->option_name, "IsaUse", 6) == 0)
+    {
+      /* These conditions were evaluated statically when building the
+	 relaxation table.  There's no need to reevaluate them now.  */
+      return TRUE;
+    }
+  else
+    {
+      as_fatal (_("internal error: unknown option name '%s'"),
+		option->option_name);
+    }
 }
 
 
 static bfd_boolean
-is_negatable_branch (insn)
-     TInsn *insn;
+xg_instruction_matches_or_options (TInsn *insn,
+				   const ReqOrOptionList *or_option)
 {
-  xtensa_isa isa = xtensa_default_isa;
-  int i;
-  int num_ops = xtensa_num_operands (isa, insn->opcode);
-
-  for (i = 0; i < num_ops; i++)
+  const ReqOrOption *option;
+  /* Must match each of the AND terms.  */
+  for (option = or_option; option != NULL; option = option->next)
     {
-      xtensa_operand opnd = xtensa_get_operand (isa, insn->opcode, i);
-      char *kind = xtensa_operand_kind (opnd);
-      if (strlen (kind) == 1 && *kind == 'l')
+      if (xg_instruction_matches_option_term (insn, option))
 	return TRUE;
     }
   return FALSE;
 }
 
-
-/* Various Other Internal Functions.  */
 
 static bfd_boolean
-is_unique_insn_expansion (r)
-     TransitionRule *r;
+xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options)
 {
-  if (!r->to_instr || r->to_instr->next != NULL)
-    return FALSE;
-  if (r->to_instr->typ != INSTR_INSTR)
-    return FALSE;
+  const ReqOption *req_options;
+  /* Must match each of the AND terms.  */
+  for (req_options = options;
+       req_options != NULL;
+       req_options = req_options->next)
+    {
+      /* Must match one of the OR clauses.  */
+      if (!xg_instruction_matches_or_options (insn,
+					      req_options->or_option_terms))
+	return FALSE;
+    }
   return TRUE;
 }
 
 
-static int
-xg_get_insn_size (insn)
-     TInsn *insn;
+/* Return the transition rule that matches or NULL if none matches.  */
+
+static bfd_boolean
+xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule)
 {
-  assert (insn->insn_type == ITYPE_INSN);
-  return xtensa_insn_length (xtensa_default_isa, insn->opcode);
+  PreconditionList *condition_l;
+
+  if (rule->opcode != insn->opcode)
+    return FALSE;
+
+  for (condition_l = rule->conditions;
+       condition_l != NULL;
+       condition_l = condition_l->next)
+    {
+      expressionS *exp1;
+      expressionS *exp2;
+      Precondition *cond = condition_l->precond;
+
+      switch (cond->typ)
+	{
+	case OP_CONSTANT:
+	  /* The expression must be the constant.  */
+	  assert (cond->op_num < insn->ntok);
+	  exp1 = &insn->tok[cond->op_num];
+	  if (expr_is_const (exp1))
+	    {
+	      switch (cond->cmp)
+		{
+		case OP_EQUAL:
+		  if (get_expr_const (exp1) != cond->op_data)
+		    return FALSE;
+		  break;
+		case OP_NOTEQUAL:
+		  if (get_expr_const (exp1) == cond->op_data)
+		    return FALSE;
+		  break;
+		default:
+		  return FALSE;
+		}
+	    }
+	  else if (expr_is_register (exp1))
+	    {
+	      switch (cond->cmp)
+		{
+		case OP_EQUAL:
+		  if (get_expr_register (exp1) != cond->op_data)
+		    return FALSE;
+		  break;
+		case OP_NOTEQUAL:
+		  if (get_expr_register (exp1) == cond->op_data)
+		    return FALSE;
+		  break;
+		default:
+		  return FALSE;
+		}
+	    }
+	  else
+	    return FALSE;
+	  break;
+
+	case OP_OPERAND:
+	  assert (cond->op_num < insn->ntok);
+	  assert (cond->op_data < insn->ntok);
+	  exp1 = &insn->tok[cond->op_num];
+	  exp2 = &insn->tok[cond->op_data];
+
+	  switch (cond->cmp)
+	    {
+	    case OP_EQUAL:
+	      if (!expr_is_equal (exp1, exp2))
+		return FALSE;
+	      break;
+	    case OP_NOTEQUAL:
+	      if (expr_is_equal (exp1, exp2))
+		return FALSE;
+	      break;
+	    }
+	  break;
+
+	case OP_LITERAL:
+	case OP_LABEL:
+	default:
+	  return FALSE;
+	}
+    }
+  if (!xg_instruction_matches_options (insn, rule->options))
+    return FALSE;
+
+  return TRUE;
 }
 
 
 static int
-xg_get_build_instr_size (insn)
-     BuildInstr *insn;
+transition_rule_cmp (const TransitionRule *a, const TransitionRule *b)
 {
-  assert (insn->typ == INSTR_INSTR);
-  return xtensa_insn_length (xtensa_default_isa, insn->opcode);
-}
+  bfd_boolean a_greater = FALSE;
+  bfd_boolean b_greater = FALSE;
 
+  ReqOptionList *l_a = a->options;
+  ReqOptionList *l_b = b->options;
 
-bfd_boolean
-xg_is_narrow_insn (insn)
-     TInsn *insn;
-{
-  TransitionTable *table = xg_build_widen_table ();
-  TransitionList *l;
-  int num_match = 0;
-  assert (insn->insn_type == ITYPE_INSN);
-  assert (insn->opcode < table->num_opcodes);
+  /* We only care if they both are the same except for
+     a const16 vs. an l32r.  */
 
-  for (l = table->table[insn->opcode]; l != NULL; l = l->next)
+  while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL)))
     {
-      TransitionRule *rule = l->rule;
-
-      if (xg_instruction_matches_rule (insn, rule)
-	  && is_unique_insn_expansion (rule))
+      ReqOrOptionList *l_or_a = l_a->or_option_terms;
+      ReqOrOptionList *l_or_b = l_b->or_option_terms;
+      while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL)))
 	{
-	  /* It only generates one instruction... */
-	  assert (insn->insn_type == ITYPE_INSN);
-	  /* ...and it is a larger instruction.  */
-	  if (xg_get_insn_size (insn)
-	      < xg_get_build_instr_size (rule->to_instr))
+	  if (l_or_a->is_true != l_or_b->is_true)
+	    return 0;
+	  if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0)
 	    {
-	      num_match++;
-	      if (num_match > 1)
-		return FALSE;
+	      /* This is the case we care about.  */
+	      if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0
+		  && strcmp (l_or_b->option_name, "IsaUseL32R") == 0)
+		{
+		  if (prefer_const16)
+		    a_greater = TRUE;
+		  else
+		    b_greater = TRUE;
+		}
+	      else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0
+		       && strcmp (l_or_b->option_name, "IsaUseConst16") == 0)
+		{
+		  if (prefer_const16)
+		    b_greater = TRUE;
+		  else
+		    a_greater = TRUE;
+		}
+	      else
+		return 0;
 	    }
+	  l_or_a = l_or_a->next;
+	  l_or_b = l_or_b->next;
 	}
+      if (l_or_a || l_or_b)
+	return 0;
+
+      l_a = l_a->next;
+      l_b = l_b->next;
     }
-  return (num_match == 1);
+  if (l_a || l_b)
+    return 0;
+
+  /* Incomparable if the substitution was used differently in two cases.  */
+  if (a_greater && b_greater)
+    return 0;
+
+  if (b_greater)
+    return 1;
+  if (a_greater)
+    return -1;
+
+  return 0;
 }
 
 
-bfd_boolean
-xg_is_single_relaxable_insn (insn)
-     TInsn *insn;
+static TransitionRule *
+xg_instruction_match (TInsn *insn)
 {
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp);
   TransitionList *l;
-  int num_match = 0;
-  assert (insn->insn_type == ITYPE_INSN);
   assert (insn->opcode < table->num_opcodes);
 
+  /* Walk through all of the possible transitions.  */
   for (l = table->table[insn->opcode]; l != NULL; l = l->next)
     {
       TransitionRule *rule = l->rule;
-
-      if (xg_instruction_matches_rule (insn, rule)
-	  && is_unique_insn_expansion (rule))
-	{
-	  assert (insn->insn_type == ITYPE_INSN);
-	  /* ... and it is a larger instruction.  */
-	  if (xg_get_insn_size (insn)
-	      <= xg_get_build_instr_size (rule->to_instr))
-	    {
-	      num_match++;
-	      if (num_match > 1)
-		return FALSE;
-	    }
-	}
+      if (xg_instruction_matches_rule (insn, rule))
+	return rule;
     }
-  return (num_match == 1);
+  return NULL;
 }
 
+
+/* Various Other Internal Functions.  */
+
+static bfd_boolean
+is_unique_insn_expansion (TransitionRule *r)
+{
+  if (!r->to_instr || r->to_instr->next != NULL)
+    return FALSE;
+  if (r->to_instr->typ != INSTR_INSTR)
+    return FALSE;
+  return TRUE;
+}
 
-/* Return the largest size instruction that this instruction can
-   expand to.  Currently, in all cases, this is 3 bytes.  Of course we
-   could just calculate this once and generate a table.  */
 
-int
-xg_get_max_narrow_insn_size (opcode)
-     xtensa_opcode opcode;
+/* Check if there is exactly one relaxation for INSN that converts it to
+   another instruction of equal or larger size.  If so, and if TARG is
+   non-null, go ahead and generate the relaxed instruction into TARG.  If
+   NARROW_ONLY is true, then only consider relaxations that widen a narrow
+   instruction, i.e., ignore relaxations that convert to an instruction of
+   equal size.  In some contexts where this function is used, only
+   a single widening is allowed and the NARROW_ONLY argument is used to
+   exclude cases like ADDI being "widened" to an ADDMI, which may
+   later be relaxed to an ADDMI/ADDI pair.  */
+
+bfd_boolean
+xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only)
 {
-  /* Go ahead and compute it, but it better be 3.  */
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
   TransitionList *l;
-  int old_size = xtensa_insn_length (xtensa_default_isa, opcode);
-  assert (opcode < table->num_opcodes);
+  TransitionRule *match = 0;
 
-  /* Actually we can do better. Check to see of Only one applies.  */
-  for (l = table->table[opcode]; l != NULL; l = l->next)
+  assert (insn->insn_type == ITYPE_INSN);
+  assert (insn->opcode < table->num_opcodes);
+
+  for (l = table->table[insn->opcode]; l != NULL; l = l->next)
     {
       TransitionRule *rule = l->rule;
 
-      /* If it only generates one instruction.  */
-      if (is_unique_insn_expansion (rule))
+      if (xg_instruction_matches_rule (insn, rule)
+	  && is_unique_insn_expansion (rule)
+	  && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0)
+	      <= xg_get_single_size (rule->to_instr->opcode)))
 	{
-	  int new_size = xtensa_insn_length (xtensa_default_isa,
-					     rule->to_instr->opcode);
-	  if (new_size > old_size)
-	    {
-	      assert (new_size == 3);
-	      return 3;
-	    }
+	  if (match)
+	    return FALSE;
+	  match = rule;
 	}
     }
-  return old_size;
+  if (!match)
+    return FALSE;
+
+  if (targ)
+    xg_build_to_insn (targ, insn, match->to_instr);
+  return TRUE;
 }
 
 
 /* Return the maximum number of bytes this opcode can expand to.  */
 
-int
-xg_get_max_insn_widen_size (opcode)
-     xtensa_opcode opcode;
+static int
+xg_get_max_insn_widen_size (xtensa_opcode opcode)
 {
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
   TransitionList *l;
-  int max_size = xtensa_insn_length (xtensa_default_isa, opcode);
+  int max_size = xg_get_single_size (opcode);
 
   assert (opcode < table->num_opcodes);
 
@@ -2683,9 +3029,7 @@ xg_get_max_insn_widen_size (opcode)
 	    switch (build_list->typ)
 	      {
 	      case INSTR_INSTR:
-		this_size += xtensa_insn_length (xtensa_default_isa,
-						 build_list->opcode);
-
+		this_size += xg_get_single_size (build_list->opcode);
 		break;
 	      case INSTR_LITERAL_DEF:
 	      case INSTR_LABEL_DEF:
@@ -2702,11 +3046,10 @@ xg_get_max_insn_widen_size (opcode)
 
 /* Return the maximum number of literal bytes this opcode can generate.  */
 
-int
-xg_get_max_insn_widen_literal_size (opcode)
-     xtensa_opcode opcode;
+static int
+xg_get_max_insn_widen_literal_size (xtensa_opcode opcode)
 {
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
   TransitionList *l;
   int max_size = 0;
 
@@ -2732,7 +3075,7 @@ xg_get_max_insn_widen_literal_size (opcode)
 	    switch (build_list->typ)
 	      {
 	      case INSTR_LITERAL_DEF:
-		/* hard coded 4-byte literal.  */
+		/* Hard-coded 4-byte literal.  */
 		this_size += 4;
 		break;
 	      case INSTR_INSTR:
@@ -2748,13 +3091,11 @@ xg_get_max_insn_widen_literal_size (opcode)
 }
 
 
-bfd_boolean
-xg_is_relaxable_insn (insn, lateral_steps)
-     TInsn *insn;
-     int lateral_steps;
+static bfd_boolean
+xg_is_relaxable_insn (TInsn *insn, int lateral_steps)
 {
   int steps_taken = 0;
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
   TransitionList *l;
 
   assert (insn->insn_type == ITYPE_INSN);
@@ -2776,7 +3117,7 @@ xg_is_relaxable_insn (insn, lateral_steps)
 
 
 static symbolS *
-get_special_literal_symbol ()
+get_special_literal_symbol (void)
 {
   static symbolS *sym = NULL;
 
@@ -2787,7 +3128,7 @@ get_special_literal_symbol ()
 
 
 static symbolS *
-get_special_label_symbol ()
+get_special_label_symbol (void)
 {
   static symbolS *sym = NULL;
 
@@ -2797,18 +3138,182 @@ get_special_label_symbol ()
 }
 
 
-/* Return true on success.  */
+static bfd_boolean
+xg_valid_literal_expression (const expressionS *exp)
+{
+  switch (exp->X_op)
+    {
+    case O_constant:
+    case O_symbol:
+    case O_big:
+    case O_uminus:
+    case O_subtract:
+    case O_pltrel:
+      return TRUE;
+    default:
+      return FALSE;
+    }
+}
 
-bfd_boolean
-xg_build_to_insn (targ, insn, bi)
-     TInsn *targ;
-     TInsn *insn;
-     BuildInstr *bi;
+
+/* This will check to see if the value can be converted into the
+   operand type.  It will return TRUE if it does not fit.  */
+
+static bfd_boolean
+xg_check_operand (int32 value, xtensa_opcode opcode, int operand)
+{
+  uint32 valbuf = value;
+  if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf))
+    return TRUE;
+  return FALSE;
+}
+
+
+/* Assumes: All immeds are constants.  Check that all constants fit
+   into their immeds; return FALSE if not.  */
+
+static bfd_boolean
+xg_immeds_fit (const TInsn *insn)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  int i;
+
+  int n = insn->ntok;
+  assert (insn->insn_type == ITYPE_INSN);
+  for (i = 0; i < n; ++i)
+    {
+      const expressionS *expr = &insn->tok[i];
+      if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
+	continue;
+
+      switch (expr->X_op)
+	{
+	case O_register:
+	case O_constant:
+	  if (xg_check_operand (expr->X_add_number, insn->opcode, i))
+	    return FALSE;
+	  break;
+
+	default:
+	  /* The symbol should have a fixup associated with it.  */
+	  assert (FALSE);
+	  break;
+	}
+    }
+  return TRUE;
+}
+
+
+/* This should only be called after we have an initial
+   estimate of the addresses.  */
+
+static bfd_boolean
+xg_symbolic_immeds_fit (const TInsn *insn,
+			segT pc_seg,
+			fragS *pc_frag,
+			offsetT pc_offset,
+			long stretch)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  symbolS *symbolP;
+  fragS *sym_frag;
+  offsetT target, pc;
+  uint32 new_offset;
+  int i;
+  int n = insn->ntok;
+
+  assert (insn->insn_type == ITYPE_INSN);
+
+  for (i = 0; i < n; ++i)
+    {
+      const expressionS *expr = &insn->tok[i];
+      if (xtensa_operand_is_register (isa, insn->opcode, i) == 1)
+	continue;
+
+      switch (expr->X_op)
+	{
+	case O_register:
+	case O_constant:
+	  if (xg_check_operand (expr->X_add_number, insn->opcode, i))
+	    return FALSE;
+	  break;
+
+	case O_lo16:
+	case O_hi16:
+	  /* Check for the worst case.  */
+	  if (xg_check_operand (0xffff, insn->opcode, i))
+	    return FALSE;
+	  break;
+
+	case O_symbol:
+	  /* We only allow symbols for PC-relative references.
+	     If pc_frag == 0, then we don't have frag locations yet.  */
+	  if (pc_frag == 0
+	      || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0)
+	    return FALSE;
+
+	  /* If it is a weak symbol, then assume it won't reach.  */
+	  if (S_IS_WEAK (expr->X_add_symbol))
+	    return FALSE;
+
+	  if (is_direct_call_opcode (insn->opcode)
+	      && ! pc_frag->tc_frag_data.use_longcalls)
+	    {
+	      /* If callee is undefined or in a different segment, be
+		 optimistic and assume it will be in range.  */
+	      if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
+		return TRUE;
+	    }
+
+	  /* Only references within a segment can be known to fit in the
+	     operands at assembly time.  */
+	  if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
+	    return FALSE;
+
+	  symbolP = expr->X_add_symbol;
+	  sym_frag = symbol_get_frag (symbolP);
+	  target = S_GET_VALUE (symbolP) + expr->X_add_number;
+	  pc = pc_frag->fr_address + pc_offset;
+
+	  /* If frag has yet to be reached on this pass, assume it
+	     will move by STRETCH just as we did.  If this is not so,
+	     it will be because some frag between grows, and that will
+	     force another pass.  Beware zero-length frags.  There
+	     should be a faster way to do this.  */
+
+	  if (stretch != 0
+	      && sym_frag->relax_marker != pc_frag->relax_marker
+	      && S_GET_SEGMENT (symbolP) == pc_seg)
+	    {
+	      target += stretch;
+	    }
+
+	  new_offset = target;
+	  xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc);
+	  if (xg_check_operand (new_offset, insn->opcode, i))
+	    return FALSE;
+	  break;
+
+	default:
+	  /* The symbol should have a fixup associated with it.  */
+	  return FALSE;
+	}
+    }
+
+  return TRUE;
+}
+
+
+/* Return TRUE on success.  */
+
+static bfd_boolean
+xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi)
 {
   BuildOp *op;
   symbolS *sym;
 
   memset (targ, 0, sizeof (TInsn));
+  targ->linenum = insn->linenum;
   switch (bi->typ)
     {
     case INSTR_INSTR:
@@ -2844,6 +3349,38 @@ xg_build_to_insn (targ, insn, bi)
 	      sym = get_special_label_symbol ();
 	      set_expr_symbol_offset (&targ->tok[op_num], sym, 0);
 	      break;
+	    case OP_OPERAND_HI16U:
+	    case OP_OPERAND_LOW16U:
+	      assert (op_data < insn->ntok);
+	      if (expr_is_const (&insn->tok[op_data]))
+		{
+		  long val;
+		  copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
+		  val = xg_apply_userdef_op_fn (op->typ,
+						targ->tok[op_num].
+						X_add_number);
+		  targ->tok[op_num].X_add_number = val;
+		}
+	      else
+		{
+		  /* For const16 we can create relocations for these.  */
+		  if (targ->opcode == XTENSA_UNDEFINED
+		      || (targ->opcode != xtensa_const16_opcode))
+		    return FALSE;
+		  assert (op_data < insn->ntok);
+		  /* Need to build a O_lo16 or O_hi16.  */
+		  copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
+		  if (targ->tok[op_num].X_op == O_symbol)
+		    {
+		      if (op->typ == OP_OPERAND_HI16U)
+			targ->tok[op_num].X_op = O_hi16;
+		      else if (op->typ == OP_OPERAND_LOW16U)
+			targ->tok[op_num].X_op = O_lo16;
+		      else
+			return FALSE;
+		    }
+		}
+	      break;
 	    default:
 	      /* currently handles:
 		 OP_OPERAND_LOW8
@@ -2889,6 +3426,9 @@ xg_build_to_insn (targ, insn, bi)
 	    {
 	    case OP_OPERAND:
 	      assert (op_data < insn->ntok);
+	      /* We can only pass resolvable literals through.  */
+	      if (!xg_valid_literal_expression (&insn->tok[op_data]))
+		return FALSE;
 	      copy_expr (&targ->tok[op_num], &insn->tok[op_data]);
 	      break;
 	    case OP_LITERAL:
@@ -2906,7 +3446,7 @@ xg_build_to_insn (targ, insn, bi)
       targ->opcode = XTENSA_UNDEFINED;
       targ->insn_type = ITYPE_LABEL;
       targ->is_specific_opcode = FALSE;
-      /* Literal with no ops. is a label?  */
+      /* Literal with no ops is a label?  */
       assert (op == NULL);
       break;
 
@@ -2918,13 +3458,10 @@ xg_build_to_insn (targ, insn, bi)
 }
 
 
-/* Return true on success.  */
+/* Return TRUE on success.  */
 
-bfd_boolean
-xg_build_to_stack (istack, insn, bi)
-     IStack *istack;
-     TInsn *insn;
-     BuildInstr *bi;
+static bfd_boolean
+xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi)
 {
   for (; bi != NULL; bi = bi->next)
     {
@@ -2937,17 +3474,14 @@ xg_build_to_stack (istack, insn, bi)
 }
 
 
-/* Return true on valid expansion.  */
+/* Return TRUE on valid expansion.  */
 
-bfd_boolean
-xg_expand_to_stack (istack, insn, lateral_steps)
-     IStack *istack;
-     TInsn *insn;
-     int lateral_steps;
+static bfd_boolean
+xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps)
 {
   int stack_size = istack->ninsn;
   int steps_taken = 0;
-  TransitionTable *table = xg_build_widen_table ();
+  TransitionTable *table = xg_build_widen_table (&transition_rule_cmp);
   TransitionList *l;
 
   assert (insn->insn_type == ITYPE_INSN);
@@ -2988,237 +3522,18 @@ xg_expand_to_stack (istack, insn, lateral_steps)
   return FALSE;
 }
 
-
-bfd_boolean
-xg_expand_narrow (targ, insn)
-     TInsn *targ;
-     TInsn *insn;
-{
-  TransitionTable *table = xg_build_widen_table ();
-  TransitionList *l;
-
-  assert (insn->insn_type == ITYPE_INSN);
-  assert (insn->opcode < table->num_opcodes);
-
-  for (l = table->table[insn->opcode]; l != NULL; l = l->next)
-    {
-      TransitionRule *rule = l->rule;
-      if (xg_instruction_matches_rule (insn, rule)
-	  && is_unique_insn_expansion (rule))
-	{
-	  /* Is it a larger instruction?  */
-	  if (xg_get_insn_size (insn)
-	      <= xg_get_build_instr_size (rule->to_instr))
-	    {
-	      xg_build_to_insn (targ, insn, rule->to_instr);
-	      return FALSE;
-	    }
-	}
-    }
-  return TRUE;
-}
-
-
-/* Assumes: All immeds are constants.  Check that all constants fit
-   into their immeds; return false if not.  */
-
-static bfd_boolean
-xg_immeds_fit (insn)
-     const TInsn *insn;
-{
-  int i;
-
-  int n = insn->ntok;
-  assert (insn->insn_type == ITYPE_INSN);
-  for (i = 0; i < n; ++i)
-    {
-      const expressionS *expr = &insn->tok[i];
-      xtensa_operand opnd = xtensa_get_operand (xtensa_default_isa,
-						insn->opcode, i);
-      if (!operand_is_immed (opnd))
-	continue;
-
-      switch (expr->X_op)
-	{
-	case O_register:
-	case O_constant:
-	  {
-	    if (xg_check_operand (expr->X_add_number, opnd))
-	      return FALSE;
-	  }
-	  break;
-	default:
-	  /* The symbol should have a fixup associated with it.  */
-	  assert (FALSE);
-	  break;
-	}
-    }
-  return TRUE;
-}
-
-
-/* This should only be called after we have an initial
-   estimate of the addresses.  */
-
-static bfd_boolean
-xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch)
-     const TInsn *insn;
-     segT pc_seg;
-     fragS *pc_frag;
-     offsetT pc_offset;
-     long stretch;
-{
-  symbolS *symbolP;
-  offsetT target, pc, new_offset;
-  int i;
-  int n = insn->ntok;
-
-  assert (insn->insn_type == ITYPE_INSN);
-
-  for (i = 0; i < n; ++i)
-    {
-      const expressionS *expr = &insn->tok[i];
-      xtensa_operand opnd = xtensa_get_operand (xtensa_default_isa,
-						insn->opcode, i);
-      if (!operand_is_immed (opnd))
-	continue;
-
-      switch (expr->X_op)
-	{
-	case O_register:
-	case O_constant:
-	  if (xg_check_operand (expr->X_add_number, opnd))
-	    return FALSE;
-	  break;
-
-	case O_symbol:
-	  /* We only allow symbols for pc-relative stuff.
-	     If pc_frag == 0, then we don't have frag locations yet.  */
-	  if (pc_frag == 0)
-	    return FALSE;
-
-	  /* If it is PC-relative and the symbol is in the same segment as
-	     the PC.... */
-	  if (!xtensa_operand_isPCRelative (opnd)
-	      || S_GET_SEGMENT (expr->X_add_symbol) != pc_seg)
-	    return FALSE;
-
-	  symbolP = expr->X_add_symbol;
-	  target = S_GET_VALUE (symbolP) + expr->X_add_number;
-	  pc = pc_frag->fr_address + pc_offset;
-
-	  /* If frag has yet to be reached on this pass, assume it
-	     will move by STRETCH just as we did.  If this is not so,
-	     it will be because some frag between grows, and that will
-	     force another pass.  Beware zero-length frags.  There
-	     should be a faster way to do this.  */
-
-	  if (stretch && is_dnrange (pc_frag, symbolP, stretch))
-	    target += stretch;
-
-	  new_offset = xtensa_operand_do_reloc (opnd, target, pc);
-	  if (xg_check_operand (new_offset, opnd))
-	    return FALSE;
-	  break;
-
-	default:
-	  /* The symbol should have a fixup associated with it.  */
-	  return FALSE;
-	}
-    }
-
-  return TRUE;
-}
-
-
-/* This will check to see if the value can be converted into the
-   operand type.  It will return true if it does not fit.  */
-
-static bfd_boolean
-xg_check_operand (value, operand)
-     int32 value;
-     xtensa_operand operand;
-{
-  uint32 valbuf = value;
-  return (xtensa_operand_encode (operand, &valbuf) != xtensa_encode_result_ok);
-}
-
-
-/* Check if a symbol is pointing to somewhere after
-   the start frag, given that the segment has stretched 
-   by stretch during relaxation.
-
-   This is more complicated than it might appear at first blush
-   because of the stretching that goes on. Here is how the check
-   works:
-
-   If the symbol and the frag are in the same segment, then
-   the symbol could be down range. Note that this function 
-   assumes that start_frag is in now_seg.
-
-   If the symbol is pointing to a frag with an address greater than 
-   than the start_frag's address, then it _could_ be down range. 
-
-   The problem comes because target_frag may or may not have had
-   stretch bytes added to its address already, depending on if it is 
-   before or after start frag. (And if we knew that, then we wouldn't
-   need this function.) start_frag has definitely already had stretch
-   bytes added to its address.
-   
-   If target_frag's address hasn't been adjusted yet, then to 
-   determine if it comes after start_frag, we need to subtract
-   stretch from start_frag's address.
-
-   If target_frag's address has been adjusted, then it might have
-   been adjusted such that it comes after start_frag's address minus
-   stretch bytes.
-
-   So, in that case, we scan for it down stream to within 
-   stretch bytes. We could search to the end of the fr_chain, but
-   that ends up taking too much time (over a minute on some gnu 
-   tests).  */
-
-int
-is_dnrange (start_frag, sym, stretch)
-     fragS *start_frag;
-     symbolS *sym;
-     long stretch;
-{
-  if (S_GET_SEGMENT (sym) == now_seg)
-    {
-      fragS *cur_frag = symbol_get_frag (sym);
-
-      if (cur_frag->fr_address >= start_frag->fr_address - stretch)
-	{
-	  int distance = stretch;
-
-	  while (cur_frag && distance >= 0) 
-	    {
-	      distance -= cur_frag->fr_fix;
-	      if (cur_frag == start_frag)
-		return 0;
-	      cur_frag = cur_frag->fr_next;
-	    }
-	  return 1;
-	}
-    }
-  return 0;
-}
-
 
 /* Relax the assembly instruction at least "min_steps".
    Return the number of steps taken.  */
 
-int
-xg_assembly_relax (istack, insn, pc_seg, pc_frag, pc_offset, min_steps,
-		   stretch)
-     IStack *istack;
-     TInsn *insn;
-     segT pc_seg;
-     fragS *pc_frag;		/* If pc_frag == 0, then no pc-relative.  */
-     offsetT pc_offset;		/* Offset in fragment.  */
-     int min_steps;		/* Minimum number of conversion steps.  */
-     long stretch;		/* Number of bytes stretched so far.  */
+static int
+xg_assembly_relax (IStack *istack,
+		   TInsn *insn,
+		   segT pc_seg,
+		   fragS *pc_frag,	/* if pc_frag == 0, not pc-relative */
+		   offsetT pc_offset,	/* offset in fragment */
+		   int min_steps,	/* minimum conversion steps */
+		   long stretch)	/* number of bytes stretched so far */
 {
   int steps_taken = 0;
 
@@ -3240,26 +3555,22 @@ xg_assembly_relax (istack, insn, pc_seg, pc_frag, pc_offset, min_steps,
       istack_push (istack, insn);
       return steps_taken;
     }
-  tinsn_copy (&current_insn, insn);
+  current_insn = *insn;
 
-  /* Walk through all of the single instruction expansions. */
-  while (xg_is_single_relaxable_insn (&current_insn))
+  /* Walk through all of the single instruction expansions.  */
+  while (xg_is_single_relaxable_insn (&current_insn, &single_target, FALSE))
     {
-      int error_val = xg_expand_narrow (&single_target, &current_insn);
-
-      assert (!error_val);
-
+      steps_taken++;
       if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset,
 				  stretch))
 	{
-	  steps_taken++;
 	  if (steps_taken >= min_steps)
 	    {
 	      istack_push (istack, &single_target);
 	      return steps_taken;
 	    }
 	}
-      tinsn_copy (&current_insn, &single_target);
+      current_insn = single_target;
     }
 
   /* Now check for a multi-instruction expansion.  */
@@ -3291,8 +3602,7 @@ xg_assembly_relax (istack, insn, pc_seg, pc_frag, pc_offset, min_steps,
 
 
 static void
-xg_force_frag_space (size)
-     int size;
+xg_force_frag_space (int size)
 {
   /* This may have the side effect of creating a new fragment for the
      space to go into.  I just do not like the name of the "frag"
@@ -3301,12 +3611,12 @@ xg_force_frag_space (size)
 }
 
 
-void
-xg_finish_frag (last_insn, state, max_growth, is_insn)
-     char *last_insn;
-     enum xtensa_relax_statesE state;
-     int max_growth;
-     bfd_boolean is_insn;
+static void
+xg_finish_frag (char *last_insn,
+		enum xtensa_relax_statesE frag_state,
+		enum xtensa_relax_statesE slot0_state,
+		int max_growth,
+		bfd_boolean is_insn)
 {
   /* Finish off this fragment so that it has at LEAST the desired
      max_growth.  If it doesn't fit in this fragment, close this one
@@ -3314,6 +3624,7 @@ xg_finish_frag (last_insn, state, max_growth, is_insn)
      beginning of the growth area.  */
 
   fragS *old_frag;
+
   xg_force_frag_space (max_growth);
 
   old_frag = frag_now;
@@ -3323,33 +3634,59 @@ xg_finish_frag (last_insn, state, max_growth, is_insn)
     frag_now->tc_frag_data.is_insn = TRUE;
 
   frag_var (rs_machine_dependent, max_growth, max_growth,
-	    state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
+	    frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn);
+
+  old_frag->tc_frag_data.slot_subtypes[0] = slot0_state;
+  xtensa_set_frag_assembly_state (frag_now);
 
   /* Just to make sure that we did not split it up.  */
   assert (old_frag->fr_next == frag_now);
 }
 
 
+/* Return TRUE if the target frag is one of the next non-empty frags.  */
+
 static bfd_boolean
-is_branch_jmp_to_next (insn, fragP)
-     TInsn *insn;
-     fragS *fragP;
+is_next_frag_target (const fragS *fragP, const fragS *target)
+{
+  if (fragP == NULL)
+    return FALSE;
+
+  for (; fragP; fragP = fragP->fr_next)
+    {
+      if (fragP == target)
+	return TRUE;
+      if (fragP->fr_fix != 0)
+	return FALSE;
+      if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
+	return FALSE;
+      if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
+	  && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
+	return FALSE;
+      if (fragP->fr_type == rs_space)
+	return FALSE;
+    }
+  return FALSE;
+}
+
+
+static bfd_boolean
+is_branch_jmp_to_next (TInsn *insn, fragS *fragP)
 {
   xtensa_isa isa = xtensa_default_isa;
   int i;
-  int num_ops = xtensa_num_operands (isa, insn->opcode);
+  int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
   int target_op = -1;
   symbolS *sym;
   fragS *target_frag;
 
-  if (is_loop_opcode (insn->opcode))
+  if (xtensa_opcode_is_branch (isa, insn->opcode) == 0
+      && xtensa_opcode_is_jump (isa, insn->opcode) == 0)
     return FALSE;
 
   for (i = 0; i < num_ops; i++)
     {
-      xtensa_operand opnd = xtensa_get_operand (isa, insn->opcode, i);
-      char *kind = xtensa_operand_kind (opnd);
-      if (strlen (kind) == 1 && *kind == 'l')
+      if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1)
 	{
 	  target_op = i;
 	  break;
@@ -3375,7 +3712,7 @@ is_branch_jmp_to_next (insn, fragP)
   if (target_frag == NULL)
     return FALSE;
 
-  if (is_next_frag_target (fragP->fr_next, target_frag) 
+  if (is_next_frag_target (fragP->fr_next, target_frag)
       && S_GET_VALUE (sym) == target_frag->fr_address)
     return TRUE;
 
@@ -3384,36 +3721,28 @@ is_branch_jmp_to_next (insn, fragP)
 
 
 static void
-xg_add_branch_and_loop_targets (insn)
-     TInsn *insn;
+xg_add_branch_and_loop_targets (TInsn *insn)
 {
   xtensa_isa isa = xtensa_default_isa;
-  int num_ops = xtensa_num_operands (isa, insn->opcode);
+  int num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
 
-  if (is_loop_opcode (insn->opcode))
+  if (xtensa_opcode_is_loop (isa, insn->opcode) == 1)
     {
       int i = 1;
-      xtensa_operand opnd = xtensa_get_operand (isa, insn->opcode, i);
-      char *kind = xtensa_operand_kind (opnd);
-      if (strlen (kind) == 1 && *kind == 'l')
-	if (insn->tok[i].X_op == O_symbol)
-	  symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
+      if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
+	  && insn->tok[i].X_op == O_symbol)
+	symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE;
       return;
     }
 
-  /* Currently, we do not add branch targets.  This is an optimization
-     for later that tries to align only branch targets, not just any
-     label in a text section.  */
-
-  if (align_only_targets)
+  if (xtensa_opcode_is_branch (isa, insn->opcode) == 1
+      || xtensa_opcode_is_loop (isa, insn->opcode) == 1)
     {
       int i;
 
       for (i = 0; i < insn->ntok && i < num_ops; i++)
 	{
-	  xtensa_operand opnd = xtensa_get_operand (isa, insn->opcode, i);
-	  char *kind = xtensa_operand_kind (opnd);
-	  if (strlen (kind) == 1 && *kind == 'l'
+	  if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1
 	      && insn->tok[i].X_op == O_symbol)
 	    {
 	      symbolS *sym = insn->tok[i].X_add_symbol;
@@ -3426,102 +3755,10 @@ xg_add_branch_and_loop_targets (insn)
 }
 
 
-/* Return the transition rule that matches or NULL if none matches.  */
-
-bfd_boolean
-xg_instruction_matches_rule (insn, rule)
-     TInsn *insn;
-     TransitionRule *rule;
-{
-  PreconditionList *condition_l;
-
-  if (rule->opcode != insn->opcode)
-    return FALSE;
-
-  for (condition_l = rule->conditions;
-       condition_l != NULL;
-       condition_l = condition_l->next)
-    {
-      expressionS *exp1;
-      expressionS *exp2;
-      Precondition *cond = condition_l->precond;
+/* Return FALSE if no error.  */
 
-      switch (cond->typ)
-	{
-	case OP_CONSTANT:
-	  /* The expression must be the constant.  */
-	  assert (cond->op_num < insn->ntok);
-	  exp1 = &insn->tok[cond->op_num];
-	  if (!expr_is_const (exp1))
-	    return FALSE;
-	  switch (cond->cmp)
-	    {
-	    case OP_EQUAL:
-	      if (get_expr_const (exp1) != cond->op_data)
-		return FALSE;
-	      break;
-	    case OP_NOTEQUAL:
-	      if (get_expr_const (exp1) == cond->op_data)
-		return FALSE;
-	      break;
-	    }
-	  break;
-
-	case OP_OPERAND:
-	  assert (cond->op_num < insn->ntok);
-	  assert (cond->op_data < insn->ntok);
-	  exp1 = &insn->tok[cond->op_num];
-	  exp2 = &insn->tok[cond->op_data];
-
-	  switch (cond->cmp)
-	    {
-	    case OP_EQUAL:
-	      if (!expr_is_equal (exp1, exp2))
-		return FALSE;
-	      break;
-	    case OP_NOTEQUAL:
-	      if (expr_is_equal (exp1, exp2))
-		return FALSE;
-	      break;
-	    }
-	  break;
-
-	case OP_LITERAL:
-	case OP_LABEL:
-	default:
-	  return FALSE;
-	}
-    }
-  return TRUE;
-}
-
-
-TransitionRule *
-xg_instruction_match (insn)
-     TInsn *insn;
-{
-  TransitionTable *table = xg_build_simplify_table ();
-  TransitionList *l;
-  assert (insn->opcode < table->num_opcodes);
-
-  /* Walk through all of the possible transitions.  */
-  for (l = table->table[insn->opcode]; l != NULL; l = l->next)
-    {
-      TransitionRule *rule = l->rule;
-      if (xg_instruction_matches_rule (insn, rule))
-	return rule;
-    }
-  return NULL;
-}
-
-
-/* Return false if no error.  */
-
-bfd_boolean
-xg_build_token_insn (instr_spec, old_insn, new_insn)
-     BuildInstr *instr_spec;
-     TInsn *old_insn;
-     TInsn *new_insn;
+static bfd_boolean
+xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn)
 {
   int num_ops = 0;
   BuildOp *b_op;
@@ -3532,11 +3769,13 @@ xg_build_token_insn (instr_spec, old_insn, new_insn)
       new_insn->insn_type = ITYPE_INSN;
       new_insn->opcode = instr_spec->opcode;
       new_insn->is_specific_opcode = FALSE;
+      new_insn->linenum = old_insn->linenum;
       break;
     case INSTR_LITERAL_DEF:
       new_insn->insn_type = ITYPE_LITERAL;
       new_insn->opcode = XTENSA_UNDEFINED;
       new_insn->is_specific_opcode = FALSE;
+      new_insn->linenum = old_insn->linenum;
       break;
     case INSTR_LABEL_DEF:
       as_bad (_("INSTR_LABEL_DEF not supported yet"));
@@ -3582,15 +3821,18 @@ xg_build_token_insn (instr_spec, old_insn, new_insn)
 }
 
 
-/* Return true if it was simplified.  */
+/* Return TRUE if it was simplified.  */
 
-bfd_boolean
-xg_simplify_insn (old_insn, new_insn)
-     TInsn *old_insn;
-     TInsn *new_insn;
+static bfd_boolean
+xg_simplify_insn (TInsn *old_insn, TInsn *new_insn)
 {
-  TransitionRule *rule = xg_instruction_match (old_insn);
+  TransitionRule *rule;
   BuildInstr *insn_spec;
+
+  if (old_insn->is_specific_opcode || !density_supported)
+    return FALSE;
+
+  rule = xg_instruction_match (old_insn);
   if (rule == NULL)
     return FALSE;
 
@@ -3609,28 +3851,25 @@ xg_simplify_insn (old_insn, new_insn)
 
 /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i ->
    l32i.n. (2) Check the number of operands.  (3) Place the instruction
-   tokens into the stack or if we can relax it at assembly time, place
-   multiple instructions/literals onto the stack.  Return false if no
-   error.  */
+   tokens into the stack or relax it and place multiple
+   instructions/literals onto the stack.  Return FALSE if no error.  */
 
 static bfd_boolean
-xg_expand_assembly_insn (istack, orig_insn)
-     IStack *istack;
-     TInsn *orig_insn;
+xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn)
 {
   int noperands;
   TInsn new_insn;
+  bfd_boolean do_expand;
+
   memset (&new_insn, 0, sizeof (TInsn));
 
-  /* On return, we will be using the "use_tokens" with "use_ntok".
-     This will reduce things like addi to addi.n.  */
-  if (code_density_available () && !orig_insn->is_specific_opcode)
-    {
-      if (xg_simplify_insn (orig_insn, &new_insn))
-	orig_insn = &new_insn;
-    }
+  /* Narrow it if we can.  xg_simplify_insn now does all the
+     appropriate checking (e.g., for the density option).  */
+  if (xg_simplify_insn (orig_insn, &new_insn))
+    orig_insn = &new_insn;
 
-  noperands = xtensa_num_operands (xtensa_default_isa, orig_insn->opcode);
+  noperands = xtensa_opcode_num_operands (xtensa_default_isa,
+					  orig_insn->opcode);
   if (orig_insn->ntok < noperands)
     {
       as_bad (_("found %d operands for '%s':  Expected %d"),
@@ -3645,70 +3884,111 @@ xg_expand_assembly_insn (istack, orig_insn)
 	     xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode),
 	     noperands);
 
-  /* If there are not enough operands, we will assert above. If there
+  /* If there are not enough operands, we will assert above.  If there
      are too many, just cut out the extras here.  */
-
   orig_insn->ntok = noperands;
 
-  /* Cases: 
-
-     Instructions with all constant immeds:
-     Assemble them and relax the instruction if possible.
-     Give error if not possible; no fixup needed.
-
-     Instructions with symbolic immeds:
-     Assemble them with a Fix up (that may cause instruction expansion).
-     Also close out the fragment if the fixup may cause instruction expansion. 
-     
-     There are some other special cases where we need alignment.
-     1) before certain instructions with required alignment (OPCODE_ALIGN)
-     2) before labels that have jumps (LABEL_ALIGN)
-     3) after call instructions (RETURN_ALIGN)
-        Multiple of these may be possible on the same fragment. 
-	If so, make sure to satisfy the required alignment. 
-	Then try to get the desired alignment.  */
-
   if (tinsn_has_invalid_symbolic_operands (orig_insn))
     return TRUE;
 
-  if (orig_insn->is_specific_opcode || !can_relax ())
-    {
-      istack_push (istack, orig_insn);
-      return FALSE;
-    }
+  /* If the instruction will definitely need to be relaxed, it is better
+     to expand it now for better scheduling.  Decide whether to expand
+     now....  */
+  do_expand = (!orig_insn->is_specific_opcode && use_transform ());
+
+  /* Calls should be expanded to longcalls only in the backend relaxation
+     so that the assembly scheduler will keep the L32R/CALLX instructions
+     adjacent.  */
+  if (is_direct_call_opcode (orig_insn->opcode))
+    do_expand = FALSE;
 
   if (tinsn_has_symbolic_operands (orig_insn))
     {
-      if (tinsn_has_complex_operands (orig_insn))
-	xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
-      else
-	istack_push (istack, orig_insn);
+      /* The values of symbolic operands are not known yet, so only expand
+	 now if an operand is "complex" (e.g., difference of symbols) and
+	 will have to be stored as a literal regardless of the value.  */
+      if (!tinsn_has_complex_operands (orig_insn))
+	do_expand = FALSE;
     }
+  else if (xg_immeds_fit (orig_insn))
+    do_expand = FALSE;
+
+  if (do_expand)
+    xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
   else
+    istack_push (istack, orig_insn);
+
+  return FALSE;
+}
+
+
+/* Return TRUE if the section flags are marked linkonce
+   or the name is .gnu.linkonce*.  */
+
+static bfd_boolean
+get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec)
+{
+  flagword flags, link_once_flags;
+
+  flags = bfd_get_section_flags (abfd, sec);
+  link_once_flags = (flags & SEC_LINK_ONCE);
+
+  /* Flags might not be set yet.  */
+  if (!link_once_flags)
     {
-      if (xg_immeds_fit (orig_insn))
-	istack_push (istack, orig_insn);
-      else
-	xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0);
+      static size_t len = sizeof ".gnu.linkonce.t.";
+
+      if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
+	link_once_flags = SEC_LINK_ONCE;
     }
+  return (link_once_flags != 0);
+}
 
-#if 0
-  for (i = 0; i < istack->ninsn; i++)
+
+static void
+xtensa_add_literal_sym (symbolS *sym)
+{
+  sym_list *l;
+
+  l = (sym_list *) xmalloc (sizeof (sym_list));
+  l->sym = sym;
+  l->next = literal_syms;
+  literal_syms = l;
+}
+
+
+static symbolS *
+xtensa_create_literal_symbol (segT sec, fragS *frag)
+{
+  static int lit_num = 0;
+  static char name[256];
+  symbolS *symbolP;
+
+  sprintf (name, ".L_lit_sym%d", lit_num);
+
+  /* Create a local symbol.  If it is in a linkonce section, we have to
+     be careful to make sure that if it is used in a relocation that the
+     symbol will be in the output file.  */
+  if (get_is_linkonce_section (stdoutput, sec))
     {
-      if (xg_simplify_insn (&new_insn, &istack->insn[i]))
-	istack->insn[i] = new_insn;
+      symbolP = symbol_new (name, sec, 0, frag);
+      S_CLEAR_EXTERNAL (symbolP);
+      /* symbolP->local = 1; */
     }
-#endif
+  else
+    symbolP = symbol_new (name, sec, 0, frag);
 
-  return FALSE;
+  xtensa_add_literal_sym (symbolP);
+
+  lit_num++;
+  return symbolP;
 }
 
 
 /* Currently all literals that are generated here are 32-bit L32R targets.  */
 
-symbolS *
-xg_assemble_literal (insn)
-     /* const */ TInsn *insn;
+static symbolS *
+xg_assemble_literal (/* const */ TInsn *insn)
 {
   emit_state state;
   symbolS *lit_sym = NULL;
@@ -3718,25 +3998,53 @@ xg_assemble_literal (insn)
   offsetT litsize = 4;
   offsetT litalign = 2;		/* 2^2 = 4 */
   expressionS saved_loc;
+  expressionS * emit_val;
+
   set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
 
   assert (insn->insn_type == ITYPE_LITERAL);
-  assert (insn->ntok = 1);	/* must be only one token here */
+  assert (insn->ntok == 1);	/* must be only one token here */
 
   xtensa_switch_to_literal_fragment (&state);
 
+  emit_val = &insn->tok[0];
+  if (emit_val->X_op == O_big)
+    {
+      int size = emit_val->X_add_number * CHARS_PER_LITTLENUM;
+      if (size > litsize)
+	{
+	  /* This happens when someone writes a "movi a2, big_number".  */
+	  as_bad_where (frag_now->fr_file, frag_now->fr_line,
+			_("invalid immediate"));
+	  xtensa_restore_emit_state (&state);
+	  return NULL;
+	}
+    }
+
   /* Force a 4-byte align here.  Note that this opens a new frag, so all
      literals done with this function have a frag to themselves.  That's
      important for the way text section literals work.  */
   frag_align (litalign, 0, 0);
+  record_alignment (now_seg, litalign);
 
-  emit_expr (&insn->tok[0], litsize);
+  if (emit_val->X_op == O_pltrel)
+    {
+      char *p = frag_more (litsize);
+      xtensa_set_frag_assembly_state (frag_now);
+      if (emit_val->X_add_symbol)
+	emit_val->X_op = O_symbol;
+      else
+	emit_val->X_op = O_constant;
+      fix_new_exp (frag_now, p - frag_now->fr_literal,
+		   litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT);
+    }
+  else
+    emit_expr (emit_val, litsize);
 
   assert (frag_now->tc_frag_data.literal_frag == NULL);
   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
   lit_sym = frag_now->fr_symbol;
-  frag_now->tc_frag_data.is_literal = TRUE;
 
   /* Go back.  */
   xtensa_restore_emit_state (&state);
@@ -3745,324 +4053,162 @@ xg_assemble_literal (insn)
 
 
 static void
-xg_assemble_literal_space (size)
-     /* const */ int size;
+xg_assemble_literal_space (/* const */ int size, int slot)
 {
   emit_state state;
-  /* We might have to do something about this alignment.  It only  
+  /* We might have to do something about this alignment.  It only
      takes effect if something is placed here.  */
   offsetT litalign = 2;		/* 2^2 = 4 */
   fragS *lit_saved_frag;
 
-  expressionS saved_loc;
-
   assert (size % 4 == 0);
-  set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ());
 
   xtensa_switch_to_literal_fragment (&state);
 
   /* Force a 4-byte align here.  */
   frag_align (litalign, 0, 0);
+  record_alignment (now_seg, litalign);
 
   xg_force_frag_space (size);
 
   lit_saved_frag = frag_now;
   frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg);
-  frag_now->tc_frag_data.is_literal = TRUE;
   frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now);
-  xg_finish_frag (0, RELAX_LITERAL, size, FALSE);
+  xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE);
 
   /* Go back.  */
   xtensa_restore_emit_state (&state);
-  frag_now->tc_frag_data.literal_frag = lit_saved_frag;
+  frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag;
 }
 
 
-symbolS *
-xtensa_create_literal_symbol (sec, frag)
-     segT sec;
-     fragS *frag;
+/* Put in a fixup record based on the opcode.
+   Return TRUE on success.  */
+
+static bfd_boolean
+xg_add_opcode_fix (TInsn *tinsn,
+		   int opnum,
+		   xtensa_format fmt,
+		   int slot,
+		   expressionS *expr,
+		   fragS *fragP,
+		   offsetT offset)
 {
-  static int lit_num = 0;
-  static char name[256];
-  symbolS *symbolP;
+  xtensa_opcode opcode = tinsn->opcode;
+  bfd_reloc_code_real_type reloc;
+  reloc_howto_type *howto;
+  int fmt_length;
+  fixS *the_fix;
 
-  sprintf (name, ".L_lit_sym%d", lit_num);
+  reloc = BFD_RELOC_NONE;
 
-  /* Create a local symbol.  If it is in a linkonce section, we have to
-     be careful to make sure that if it is used in a relocation that the
-     symbol will be in the output file.  */
-  if (get_is_linkonce_section (stdoutput, sec))
+  /* First try the special cases for "alternate" relocs.  */
+  if (opcode == xtensa_l32r_opcode)
     {
-      symbolP = symbol_new (name, sec, 0, frag);
-      S_CLEAR_EXTERNAL (symbolP);
-      /* symbolP->local = 1; */
+      if (fragP->tc_frag_data.use_absolute_literals)
+	reloc = encode_alt_reloc (slot);
     }
-  else
-    symbolP = symbol_new (name, sec, 0, frag);
-
-  xtensa_add_literal_sym (symbolP);
-
-  frag->tc_frag_data.is_literal = TRUE;
-  lit_num++;
-  return symbolP;
-}
-
-
-static void
-xtensa_add_literal_sym (sym)
-     symbolS *sym;
-{
-  sym_list *l;
-
-  l = (sym_list *) xmalloc (sizeof (sym_list));
-  l->sym = sym;
-  l->next = literal_syms;
-  literal_syms = l;
-}
-
-
-static void
-xtensa_add_insn_label (sym)
-     symbolS *sym;
-{
-  sym_list *l;
-
-  if (!free_insn_labels)
-    l = (sym_list *) xmalloc (sizeof (sym_list));
-  else
+  else if (opcode == xtensa_const16_opcode)
     {
-      l = free_insn_labels;
-      free_insn_labels = l->next;
+      if (expr->X_op == O_lo16)
+	{
+	  reloc = encode_reloc (slot);
+	  expr->X_op = O_symbol;
+	}
+      else if (expr->X_op == O_hi16)
+	{
+	  reloc = encode_alt_reloc (slot);
+	  expr->X_op = O_symbol;
+	}
     }
 
-  l->sym = sym;
-  l->next = insn_labels;
-  insn_labels = l;
-}
-
-
-static void
-xtensa_clear_insn_labels (void)
-{
-  sym_list **pl;
-
-  for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
-    ;
-  *pl = insn_labels;
-  insn_labels = NULL;
-}
-
-
-/* Return true if the section flags are marked linkonce
-   or the name is .gnu.linkonce*.  */
-
-bfd_boolean
-get_is_linkonce_section (abfd, sec)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec;
-{
-  flagword flags, link_once_flags;
-
-  flags = bfd_get_section_flags (abfd, sec);
-  link_once_flags = (flags & SEC_LINK_ONCE);
-
-  /* Flags might not be set yet.  */
-  if (!link_once_flags)
+  if (opnum != get_relaxable_immed (opcode))
     {
-      static size_t len = sizeof ".gnu.linkonce.t.";
-
-      if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0)
-	link_once_flags = SEC_LINK_ONCE;
+      as_bad (_("invalid relocation for operand %i of '%s'"),
+	      opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
+      return FALSE;
     }
-  return (link_once_flags != 0);
-}
-
-
-/* Emit an instruction to the current fragment.  If record_fix is true,
-   then this instruction will not change and we can go ahead and record
-   the fixup.  If record_fix is false, then the instruction may change
-   and we are going to close out this fragment.  Go ahead and set the
-   fr_symbol and fr_offset instead of adding a fixup.  */
-
-static bfd_boolean
-xg_emit_insn (t_insn, record_fix)
-     TInsn *t_insn;
-     bfd_boolean record_fix;
-{
-  bfd_boolean ok = TRUE;
-  xtensa_isa isa = xtensa_default_isa;
-  xtensa_opcode opcode = t_insn->opcode;
-  bfd_boolean has_fixup = FALSE;
-  int noperands;
-  int i, byte_count;
-  fragS *oldfrag;
-  size_t old_size;
-  char *f;
-  static xtensa_insnbuf insnbuf = NULL;
-  
-  /* Use a static pointer to the insn buffer so we don't have to call 
-     malloc each time through.  */
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-
-  has_fixup = tinsn_to_insnbuf (t_insn, insnbuf);
-
-  noperands = xtensa_num_operands (isa, opcode);
-  assert (noperands == t_insn->ntok);
 
-  byte_count = xtensa_insn_length (isa, opcode);
-  oldfrag = frag_now;
-  /* This should NEVER cause us to jump into a new frag;
-     we've already reserved space.  */
-  old_size = frag_now_fix ();
-  f = frag_more (byte_count);
-  assert (oldfrag == frag_now);
-
-  /* This needs to generate a record that lists the parts that are
-     instructions.  */
-  if (!frag_now->tc_frag_data.is_insn)
+  /* Handle erroneous "@h" and "@l" expressions here before they propagate
+     into the symbol table where the generic portions of the assembler
+     won't know what to do with them.  */
+  if (expr->X_op == O_lo16 || expr->X_op == O_hi16)
     {
-      /* If we are at the beginning of a fragment, switch this
-	 fragment to an instruction fragment.  */
-      if (now_seg != absolute_section && old_size != 0)
-	as_warn (_("instruction fragment may contain data"));
-      frag_now->tc_frag_data.is_insn = TRUE;
+      as_bad (_("invalid expression for operand %i of '%s'"),
+	      opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode));
+      return FALSE;
     }
 
-  xtensa_insnbuf_to_chars (isa, insnbuf, f);
-
-  dwarf2_emit_insn (byte_count);
-
-  /* Now spit out the opcode fixup.... */
-  if (!has_fixup)
-    return !ok;
+  /* Next try the generic relocs.  */
+  if (reloc == BFD_RELOC_NONE)
+    reloc = encode_reloc (slot);
+  if (reloc == BFD_RELOC_NONE)
+    {
+      as_bad (_("invalid relocation in instruction slot %i"), slot);
+      return FALSE;
+    }
 
-  for (i = 0; i < noperands; ++i)
+  howto = bfd_reloc_type_lookup (stdoutput, reloc);
+  if (!howto)
     {
-      expressionS *expr = &t_insn->tok[i];
-      switch (expr->X_op)
-	{
-	case O_symbol:
-	  if (get_relaxable_immed (opcode) == i)
-	    {
-	      if (record_fix)
-		{
-		  if (!xg_add_opcode_fix (opcode, i, expr, frag_now,
-					  f - frag_now->fr_literal))
-		    ok = FALSE;
-		}
-	      else
-		{
-		  /* Write it to the fr_offset, fr_symbol.  */
-		  frag_now->fr_symbol = expr->X_add_symbol;
-		  frag_now->fr_offset = expr->X_add_number;
-		}
-	    }
-	  else
-	    {
-	      as_bad (_("invalid operand %d on '%s'"),
-		      i, xtensa_opcode_name (isa, opcode));
-	      ok = FALSE;
-	    }
-	  break;
+      as_bad (_("undefined symbol for opcode \"%s\""),
+	      xtensa_opcode_name (xtensa_default_isa, opcode));
+      return FALSE;
+    }
 
-	case O_constant:
-	case O_register:
-	  break;
+  fmt_length = xtensa_format_length (xtensa_default_isa, fmt);
+  the_fix = fix_new_exp (fragP, offset, fmt_length, expr,
+			 howto->pc_relative, reloc);
+  the_fix->fx_no_overflow = 1;
 
-	default:
-	  as_bad (_("invalid expression for operand %d on '%s'"),
-		  i, xtensa_opcode_name (isa, opcode));
-	  ok = FALSE;
-	  break;
-	}
-    }
+  if (expr->X_add_symbol
+      && (S_IS_EXTERNAL (expr->X_add_symbol)
+	  || S_IS_WEAK (expr->X_add_symbol)))
+    the_fix->fx_plt = TRUE;
 
-  return !ok;
+  the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol;
+  the_fix->tc_fix_data.X_add_number = expr->X_add_number;
+  the_fix->tc_fix_data.slot = slot;
+
+  return TRUE;
 }
 
 
 static bfd_boolean
-xg_emit_insn_to_buf (t_insn, buf, fragP, offset, build_fix)
-     TInsn *t_insn;
-     char *buf;
-     fragS *fragP;
-     offsetT offset;
-     bfd_boolean build_fix;
+xg_emit_insn_to_buf (TInsn *tinsn,
+		     char *buf,
+		     fragS *fragP,
+		     offsetT offset,
+		     bfd_boolean build_fix)
 {
   static xtensa_insnbuf insnbuf = NULL;
   bfd_boolean has_symbolic_immed = FALSE;
   bfd_boolean ok = TRUE;
+
   if (!insnbuf)
     insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
 
-  has_symbolic_immed = tinsn_to_insnbuf (t_insn, insnbuf);
+  has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf);
   if (has_symbolic_immed && build_fix)
     {
       /* Add a fixup.  */
-      int opnum = get_relaxable_immed (t_insn->opcode);
-      expressionS *exp = &t_insn->tok[opnum];
+      xtensa_format fmt = xg_get_single_format (tinsn->opcode);
+      int slot = xg_get_single_slot (tinsn->opcode);
+      int opnum = get_relaxable_immed (tinsn->opcode);
+      expressionS *exp = &tinsn->tok[opnum];
 
-      if (!xg_add_opcode_fix (t_insn->opcode, 
-			      opnum, exp, fragP, offset))
+      if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset))
 	ok = FALSE;
     }
   fragP->tc_frag_data.is_insn = TRUE;
-  xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf);
+  xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
+			   (unsigned char *) buf, 0);
   return ok;
 }
 
 
-/* Put in a fixup record based on the opcode.
-   Return true on success.  */
-
-bfd_boolean
-xg_add_opcode_fix (opcode, opnum, expr, fragP, offset)
-     xtensa_opcode opcode;
-     int opnum;
-     expressionS *expr;
-     fragS *fragP;
-     offsetT offset;
-{ 
-  bfd_reloc_code_real_type reloc; 
-  reloc_howto_type *howto; 
-  int insn_length;
-  fixS *the_fix;
-
-  reloc = opnum_to_reloc (opnum);
-  if (reloc == BFD_RELOC_NONE)
-    {
-      as_bad (_("invalid relocation operand %i on '%s'"),
-	      opnum, xtensa_opcode_name (xtensa_default_isa, opcode));
-      return FALSE;
-    }
-
-  howto = bfd_reloc_type_lookup (stdoutput, reloc);
-
-  if (!howto)
-    {
-      as_bad (_("undefined symbol for opcode \"%s\"."),
-	      xtensa_opcode_name (xtensa_default_isa, opcode));
-      return FALSE;
-    }
-
-  insn_length = xtensa_insn_length (xtensa_default_isa, opcode);
-  the_fix = fix_new_exp (fragP, offset, insn_length, expr,
-			 howto->pc_relative, reloc);
-
-  if (expr->X_add_symbol && 
-      (S_IS_EXTERNAL (expr->X_add_symbol) || S_IS_WEAK (expr->X_add_symbol)))
-    the_fix->fx_plt = TRUE;
-  
-  return TRUE;
-}
-
-
-void
-xg_resolve_literals (insn, lit_sym)
-     TInsn *insn;
-     symbolS *lit_sym;
+static void
+xg_resolve_literals (TInsn *insn, symbolS *lit_sym)
 {
   symbolS *sym = get_special_literal_symbol ();
   int i;
@@ -4076,14 +4222,11 @@ xg_resolve_literals (insn, lit_sym)
 }
 
 
-void
-xg_resolve_labels (insn, label_sym)
-     TInsn *insn;
-     symbolS *label_sym;
+static void
+xg_resolve_labels (TInsn *insn, symbolS *label_sym)
 {
   symbolS *sym = get_special_label_symbol ();
   int i;
-  /* assert(!insn->is_literal); */
   for (i = 0; i < insn->ntok; i++)
     if (insn->tok[i].X_add_symbol == sym)
       insn->tok[i].X_add_symbol = label_sym;
@@ -4091,179 +4234,28 @@ xg_resolve_labels (insn, label_sym)
 }
 
 
-static void
-xg_assemble_tokens (insn)
-     /*const */ TInsn *insn;
-{
-  /* By the time we get here, there's not too much left to do. 
-     1) Check our assumptions. 
-     2) Check if the current instruction is "narrow". 
-        If so, then finish the frag, create another one.
-        We could also go back to change some previous
-        "narrow" frags into no-change ones if we have more than
-        MAX_NARROW_ALIGNMENT of them without alignment restrictions
-        between them.
-
-     Cases:
-        1) It has constant operands and doesn't fit.
-           Go ahead and assemble it so it will fail.
-        2) It has constant operands that fit.
-           If narrow and !is_specific_opcode,
-              assemble it and put in a relocation
-           else
-              assemble it.
-        3) It has a symbolic immediate operand
-           a) Find the worst-case relaxation required
-           b) Find the worst-case literal pool space required.
-              Insert appropriate alignment & space in the literal.
-              Assemble it.
-              Add the relocation.  */
-
-  assert (insn->insn_type == ITYPE_INSN);
-
-  if (!tinsn_has_symbolic_operands (insn))
-    {
-      if (xg_is_narrow_insn (insn) && !insn->is_specific_opcode)
-	{
-	  /* assemble it but add max required space */
-	  int max_size = xg_get_max_narrow_insn_size (insn->opcode);
-	  int min_size = xg_get_insn_size (insn);
-	  char *last_insn;
-	  assert (max_size == 3);
-	  /* make sure we have enough space to widen it */
-	  xg_force_frag_space (max_size);
-	  /* Output the instruction.  It may cause an error if some 
-	     operands do not fit.  */
-	  last_insn = frag_more (0);
-	  if (xg_emit_insn (insn, TRUE))
-	    as_warn (_("instruction with constant operands does not fit"));
-	  xg_finish_frag (last_insn, RELAX_NARROW, max_size - min_size, TRUE);
-	}
-      else
-	{
-	  /* Assemble it.  No relocation needed.  */
-	  int max_size = xg_get_insn_size (insn);
-	  xg_force_frag_space (max_size);
-	  if (xg_emit_insn (insn, FALSE))
-	    as_warn (_("instruction with constant operands does not "
-		       "fit without widening"));
-	  /* frag_more (max_size); */
-
-	  /* Special case for jx.  If the jx is the next to last
-	     instruction in a loop, we will add a NOP after it.  This
-	     avoids a hardware issue that could occur if the jx jumped
-	     to the next instruction.  */
-	  if (software_avoid_b_j_loop_end
-	      && is_jx_opcode (insn->opcode))
-	    {
-	      maybe_has_b_j_loop_end = TRUE;
-	      /* add 2 of these */
-	      frag_now->tc_frag_data.is_insn = TRUE;
-	      frag_var (rs_machine_dependent, 4, 4,
-			RELAX_ADD_NOP_IF_PRE_LOOP_END,
-			frag_now->fr_symbol, frag_now->fr_offset, NULL);
-	    }
-	}
-    }
-  else
-    {
-      /* Need to assemble it with space for the relocation.  */
-      if (!insn->is_specific_opcode)
-	{
-	  /* Assemble it but add max required space.  */
-	  char *last_insn;
-	  int min_size = xg_get_insn_size (insn);
-	  int max_size = xg_get_max_insn_widen_size (insn->opcode);
-	  int max_literal_size =
-	    xg_get_max_insn_widen_literal_size (insn->opcode);
-
-#if 0
-	  symbolS *immed_sym = xg_get_insn_immed_symbol (insn);
-	  set_frag_segment (frag_now, now_seg);
-#endif /* 0 */
-
-	  /* Make sure we have enough space to widen the instruction. 
-	     This may open a new fragment.  */
-	  xg_force_frag_space (max_size);
-	  if (max_literal_size != 0)
-	    xg_assemble_literal_space (max_literal_size);
-
-	  /* Output the instruction.  It may cause an error if some 
-	     operands do not fit.  Emit the incomplete instruction.  */
-	  last_insn = frag_more (0);
-	  xg_emit_insn (insn, FALSE);
-
-	  xg_finish_frag (last_insn, RELAX_IMMED, max_size - min_size, TRUE);
-
-	  /* Special cases for loops:
-	     close_loop_end should be inserted AFTER short_loop.
-	     Make sure that CLOSE loops are processed BEFORE short_loops
-	     when converting them.  */
-
-	  /* "short_loop": add a NOP if the loop is < 4 bytes.  */
-	  if (software_avoid_short_loop
-	      && is_loop_opcode (insn->opcode))
-	    {
-	      maybe_has_short_loop = TRUE;
-	      frag_now->tc_frag_data.is_insn = TRUE;
-	      frag_var (rs_machine_dependent, 4, 4,
-			RELAX_ADD_NOP_IF_SHORT_LOOP,
-			frag_now->fr_symbol, frag_now->fr_offset, NULL);
-	      frag_now->tc_frag_data.is_insn = TRUE;
-	      frag_var (rs_machine_dependent, 4, 4,
-			RELAX_ADD_NOP_IF_SHORT_LOOP,
-			frag_now->fr_symbol, frag_now->fr_offset, NULL);
-	    }
-
-	  /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
-	     loop at least 12 bytes away from another loop's loop
-	     end.  */
-	  if (software_avoid_close_loop_end
-	      && is_loop_opcode (insn->opcode))
-	    {
-	      maybe_has_close_loop_end = TRUE;
-	      frag_now->tc_frag_data.is_insn = TRUE;
-	      frag_var (rs_machine_dependent, 12, 12,
-			RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
-			frag_now->fr_symbol, frag_now->fr_offset, NULL);
-	    }
-	}
-      else
-	{
-	  /* Assemble it in place.  No expansion will be required, 
-	     but we'll still need a relocation record.  */
-	  int max_size = xg_get_insn_size (insn);
-	  xg_force_frag_space (max_size);
-	  if (xg_emit_insn (insn, TRUE))
-	    as_warn (_("instruction's constant operands do not fit"));
-	}
-    }
-}
-
-
-/* Return true if the instruction can write to the specified
+/* Return TRUE if the instruction can write to the specified
    integer register.  */
 
 static bfd_boolean
-is_register_writer (insn, regset, regnum)
-     const TInsn *insn;
-     const char *regset;
-     int regnum;
+is_register_writer (const TInsn *insn, const char *regset, int regnum)
 {
   int i;
   int num_ops;
   xtensa_isa isa = xtensa_default_isa;
 
-  num_ops = xtensa_num_operands (isa, insn->opcode);
+  num_ops = xtensa_opcode_num_operands (isa, insn->opcode);
 
   for (i = 0; i < num_ops; i++)
     {
-      xtensa_operand operand = xtensa_get_operand (isa, insn->opcode, i);
-      char inout = xtensa_operand_inout (operand);
-
-      if (inout == '>' || inout == '=')
+      char inout;
+      inout = xtensa_operand_inout (isa, insn->opcode, i);
+      if ((inout == 'o' || inout == 'm')
+	  && xtensa_operand_is_register (isa, insn->opcode, i) == 1)
 	{
-	  if (strcmp (xtensa_operand_kind (operand), regset) == 0)
+	  xtensa_regfile opnd_rf =
+	    xtensa_operand_regfile (isa, insn->opcode, i);
+	  if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset))
 	    {
 	      if ((insn->tok[i].X_op == O_register)
 		  && (insn->tok[i].X_add_number == regnum))
@@ -4276,8 +4268,7 @@ is_register_writer (insn, regset, regnum)
 
 
 static bfd_boolean
-is_bad_loopend_opcode (tinsn)
-     const TInsn * tinsn;
+is_bad_loopend_opcode (const TInsn *tinsn)
 {
   xtensa_opcode opcode = tinsn->opcode;
 
@@ -4297,14 +4288,8 @@ is_bad_loopend_opcode (tinsn)
       || opcode == xtensa_ret_n_opcode
       || opcode == xtensa_retw_opcode
       || opcode == xtensa_retw_n_opcode
-      || opcode == xtensa_waiti_opcode)
-    return TRUE;
-  
-  /* An RSR of LCOUNT is illegal as the last opcode in a loop.  */
-  if (opcode == xtensa_rsr_opcode
-      && tinsn->ntok >= 2
-      && tinsn->tok[1].X_op == O_constant
-      && tinsn->tok[1].X_add_number == 2)
+      || opcode == xtensa_waiti_opcode
+      || opcode == xtensa_rsr_lcount_opcode)
     return TRUE;
 
   return FALSE;
@@ -4316,9 +4301,8 @@ is_bad_loopend_opcode (tinsn)
    Also, the assembler generates stabs labels that need
    not be aligned:  FAKE_LABEL_NAME . {"F", "L", "endfunc"}.  */
 
-bfd_boolean
-is_unaligned_label (sym) 
-     symbolS *sym; 
+static bfd_boolean
+is_unaligned_label (symbolS *sym)
 {
   const char *name = S_GET_NAME (sym);
   static size_t fake_size = 0;
@@ -4332,7 +4316,7 @@ is_unaligned_label (sym)
   if (fake_size == 0)
     fake_size = strlen (FAKE_LABEL_NAME);
 
-  if (name 
+  if (name
       && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0
       && (name[fake_size] == 'F'
 	  || name[fake_size] == 'L'
@@ -4344,13 +4328,12 @@ is_unaligned_label (sym)
 }
 
 
-fragS *
-next_non_empty_frag (fragP)
-     const fragS *fragP;
+static fragS *
+next_non_empty_frag (const fragS *fragP)
 {
   fragS *next_fragP = fragP->fr_next;
 
-  /* Sometimes an empty will end up here due storage allocation issues. 
+  /* Sometimes an empty will end up here due storage allocation issues.
      So we have to skip until we find something legit.  */
   while (next_fragP && next_fragP->fr_fix == 0)
     next_fragP = next_fragP->fr_next;
@@ -4362,50 +4345,106 @@ next_non_empty_frag (fragP)
 }
 
 
-xtensa_opcode
-next_frag_opcode (fragP)
-     const fragS * fragP;
+static bfd_boolean
+next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode)
 {
+  xtensa_opcode out_opcode;
   const fragS *next_fragP = next_non_empty_frag (fragP);
+
+  if (next_fragP == NULL)
+    return FALSE;
+
+  out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0);
+  if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1)
+    {
+      *opcode = out_opcode;
+      return TRUE;
+    }
+  return FALSE;
+}
+
+
+static int
+frag_format_size (const fragS *fragP)
+{
   static xtensa_insnbuf insnbuf = NULL;
   xtensa_isa isa = xtensa_default_isa;
+  xtensa_format fmt;
+  int fmt_size;
 
   if (!insnbuf)
     insnbuf = xtensa_insnbuf_alloc (isa);
 
-  if (next_fragP == NULL)
+  if (fragP == NULL)
+    return XTENSA_UNDEFINED;
+
+  xtensa_insnbuf_from_chars (isa, insnbuf,
+			     (unsigned char *) fragP->fr_literal, 0);
+
+  fmt = xtensa_format_decode (isa, insnbuf);
+  if (fmt == XTENSA_UNDEFINED)
     return XTENSA_UNDEFINED;
+  fmt_size = xtensa_format_length (isa, fmt);
+
+  /* If the next format won't be changing due to relaxation, just
+     return the length of the first format.  */
+  if (fragP->fr_opcode != fragP->fr_literal)
+    return fmt_size;
+
+  /* If during relaxation we have to pull an instruction out of a
+     multi-slot instruction, we will return the more conservative
+     number.  This works because alignment on bigger instructions
+     is more restrictive than alignment on smaller instructions.
+     This is more conservative than we would like, but it happens
+     infrequently.  */
+
+  if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1)
+    return fmt_size;
+
+  /* If we aren't doing one of our own relaxations or it isn't
+     slot-based, then the insn size won't change.  */
+  if (fragP->fr_type != rs_machine_dependent)
+    return fmt_size;
+  if (fragP->fr_subtype != RELAX_SLOTS)
+    return fmt_size;
+
+  /* If an instruction is about to grow, return the longer size.  */
+  if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1
+      || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2)
+    return 3;
+
+  if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+    return 2 + fragP->tc_frag_data.text_expansion[0];
+
+  return fmt_size;
+}
+
 
-  xtensa_insnbuf_from_chars (isa, insnbuf, next_fragP->fr_literal);
-  return xtensa_decode_insn (isa, insnbuf);
+static int
+next_frag_format_size (const fragS *fragP)
+{
+  const fragS *next_fragP = next_non_empty_frag (fragP);
+  return frag_format_size (next_fragP);
 }
 
 
-/* Return true if the target frag is one of the next non-empty frags.  */
+/* In early Xtensa Processors, for reasons that are unclear, the ISA
+   required two-byte instructions to be treated as three-byte instructions
+   for loop instruction alignment.  This restriction was removed beginning
+   with Xtensa LX.  Now the only requirement on loop instruction alignment
+   is that the first instruction of the loop must appear at an address that
+   does not cross a fetch boundary.  */
 
-bfd_boolean
-is_next_frag_target (fragP, target)
-     const fragS *fragP;
-     const fragS *target;
+static int
+get_loop_align_size (int insn_size)
 {
-  if (fragP == NULL)
-    return FALSE;
+  if (insn_size == XTENSA_UNDEFINED)
+    return xtensa_fetch_width;
 
-  for (; fragP; fragP = fragP->fr_next)
-    {
-      if (fragP == target)
-	return TRUE;
-      if (fragP->fr_fix != 0)
-	return FALSE;
-      if (fragP->fr_type == rs_fill && fragP->fr_offset != 0)
-	return FALSE;
-      if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
-	  && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0))
-	return FALSE;
-      if (fragP->fr_type == rs_space)
-	return FALSE;
-    }
-  return FALSE;
+  if (enforce_three_byte_loop_align && insn_size == 2)
+    return 3;
+
+  return insn_size;
 }
 
 
@@ -4413,10 +4452,34 @@ is_next_frag_target (fragP, target)
    switch its state so it will instantiate a NOP.  */
 
 static void
-update_next_frag_nop_state (fragP)
-     fragS *fragP;
+update_next_frag_state (fragS *fragP)
 {
   fragS *next_fragP = fragP->fr_next;
+  fragS *new_target = NULL;
+
+  if (align_targets)
+    {
+      /* We are guaranteed there will be one of these...   */
+      while (!(next_fragP->fr_type == rs_machine_dependent
+	       && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
+		   || next_fragP->fr_subtype == RELAX_UNREACHABLE)))
+	next_fragP = next_fragP->fr_next;
+
+      assert (next_fragP->fr_type == rs_machine_dependent
+	      && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE
+		  || next_fragP->fr_subtype == RELAX_UNREACHABLE));
+
+      /* ...and one of these.  */
+      new_target = next_fragP->fr_next;
+      while (!(new_target->fr_type == rs_machine_dependent
+	       && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
+		   || new_target->fr_subtype == RELAX_DESIRE_ALIGN)))
+	new_target = new_target->fr_next;
+
+      assert (new_target->fr_type == rs_machine_dependent
+	      && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN
+		  || new_target->fr_subtype == RELAX_DESIRE_ALIGN));
+    }
 
   while (next_fragP && next_fragP->fr_fix == 0)
     {
@@ -4426,16 +4489,16 @@ update_next_frag_nop_state (fragP)
 	  next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP;
 	  return;
 	}
+
       next_fragP = next_fragP->fr_next;
     }
 }
 
 
 static bfd_boolean
-next_frag_is_branch_target (fragP)
-     const fragS *fragP;
+next_frag_is_branch_target (const fragS *fragP)
 {
-  /* Sometimes an empty will end up here due storage allocation issues,
+  /* Sometimes an empty will end up here due to storage allocation issues,
      so we have to skip until we find something legit.  */
   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
     {
@@ -4449,10 +4512,9 @@ next_frag_is_branch_target (fragP)
 
 
 static bfd_boolean
-next_frag_is_loop_target (fragP)
-     const fragS *fragP;
+next_frag_is_loop_target (const fragS *fragP)
 {
-  /* Sometimes an empty will end up here due storage allocation issues. 
+  /* Sometimes an empty will end up here due storage allocation issues.
      So we have to skip until we find something legit. */
   for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next)
     {
@@ -4466,17 +4528,16 @@ next_frag_is_loop_target (fragP)
 
 
 static addressT
-next_frag_pre_opcode_bytes (fragp)
-     const fragS *fragp;
+next_frag_pre_opcode_bytes (const fragS *fragp)
 {
   const fragS *next_fragp = fragp->fr_next;
+  xtensa_opcode next_opcode;
 
-  xtensa_opcode next_opcode = next_frag_opcode (fragp);
-  if (!is_loop_opcode (next_opcode))
+  if (!next_frag_opcode_is_loop (fragp, &next_opcode))
     return 0;
 
-  /* Sometimes an empty will end up here due storage allocation issues.
-     So we have to skip until we find something legit.  */
+  /* Sometimes an empty will end up here due to storage allocation issues,
+     so we have to skip until we find something legit.  */
   while (next_fragp->fr_fix == 0)
     next_fragp = next_fragp->fr_next;
 
@@ -4485,8 +4546,9 @@ next_frag_pre_opcode_bytes (fragp)
 
   /* There is some implicit knowledge encoded in here.
      The LOOP instructions that are NOT RELAX_IMMED have
-     been relaxed.  */
-  if (next_fragp->fr_subtype > RELAX_IMMED)
+     been relaxed.  Note that we can assume that the LOOP
+     instruction is in slot 0 because loops aren't bundleable.  */
+  if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED)
       return get_expanded_loop_offset (next_opcode);
 
   return 0;
@@ -4498,77 +4560,75 @@ next_frag_pre_opcode_bytes (fragp)
    placed nearest to their use.  */
 
 static void
-xtensa_mark_literal_pool_location ()
+xtensa_mark_literal_pool_location (void)
 {
   /* Any labels pointing to the current location need
      to be adjusted to after the literal pool.  */
   emit_state s;
   fragS *pool_location;
 
+  if (use_literal_section && !directive_state[directive_absolute_literals])
+    return;
+
   frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
 
-  /* We stash info in the fr_var of these frags
-     so we can later move the literal's fixes into this 
-     frchain's fix list.  We can use fr_var because fr_var's
-     interpretation depends solely on the fr_type and subtype.  */
+  /* We stash info in these frags so we can later move the literal's
+     fixes into this frchain's fix list.  */
   pool_location = frag_now;
-  frag_variant (rs_machine_dependent, 0, (int) frchain_now, 
+  frag_now->tc_frag_data.lit_frchain = frchain_now;
+  frag_variant (rs_machine_dependent, 0, 0,
 		RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL);
-  frag_variant (rs_machine_dependent, 0, (int) now_seg, 
+  xtensa_set_frag_assembly_state (frag_now);
+  frag_now->tc_frag_data.lit_seg = now_seg;
+  frag_variant (rs_machine_dependent, 0, 0,
 		RELAX_LITERAL_POOL_END, NULL, 0, NULL);
+  xtensa_set_frag_assembly_state (frag_now);
 
   /* Now put a frag into the literal pool that points to this location.  */
   set_literal_pool_location (now_seg, pool_location);
-  xtensa_switch_to_literal_fragment (&s);
+  xtensa_switch_to_non_abs_literal_fragment (&s);
+  frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
 
   /* Close whatever frag is there.  */
   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
+  xtensa_set_frag_assembly_state (frag_now);
   frag_now->tc_frag_data.literal_frag = pool_location;
   frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
   xtensa_restore_emit_state (&s);
+  xtensa_set_frag_assembly_state (frag_now);
 }
 
 
-/* The "loops_ok" argument is provided to allow ignoring labels that 
-   define loop ends.  This fixes a bug where the NOPs to align a 
-   loop opcode were included in a previous zero-cost loop:
-
-   loop a0, loopend
-     <loop1 body>
-   loopend:
-
-   loop a2, loopend2
-     <loop2 body>
-
-   would become:
-
-   loop a0, loopend
-     <loop1 body>
-     nop.n <===== bad!
-   loopend:
-
-   loop a2, loopend2
-     <loop2 body>
-
-   This argument is used to prevent moving the NOP to before the
-   loop-end label, which is what you want in this special case.  */
+/* Build a nop of the correct size into tinsn.  */
 
 static void
-xtensa_move_labels (new_frag, new_offset, loops_ok)
-     fragS *new_frag;
-     valueT new_offset;
-     bfd_boolean loops_ok;
+build_nop (TInsn *tinsn, int size)
 {
-  sym_list *lit;
-
-  for (lit = insn_labels; lit; lit = lit->next)
+  tinsn_init (tinsn);
+  switch (size)
     {
-      symbolS *lit_sym = lit->sym;
-      if (loops_ok || symbol_get_tc (lit_sym)->is_loop_target == 0)
+    case 2:
+      tinsn->opcode = xtensa_nop_n_opcode;
+      tinsn->ntok = 0;
+      if (tinsn->opcode == XTENSA_UNDEFINED)
+	as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
+      break;
+
+    case 3:
+      if (xtensa_nop_opcode == XTENSA_UNDEFINED)
 	{
-	  S_SET_VALUE (lit_sym, new_offset);
-	  symbol_set_frag (lit_sym, new_frag);
+	  tinsn->opcode = xtensa_or_opcode;
+	  set_expr_const (&tinsn->tok[0], 1);
+	  set_expr_const (&tinsn->tok[1], 1);
+	  set_expr_const (&tinsn->tok[2], 1);
+	  tinsn->ntok = 3;
 	}
+      else
+	tinsn->opcode = xtensa_nop_opcode;
+
+      assert (tinsn->opcode != XTENSA_UNDEFINED);
     }
 }
 
@@ -4576,44 +4636,20 @@ xtensa_move_labels (new_frag, new_offset, loops_ok)
 /* Assemble a NOP of the requested size in the buffer.  User must have
    allocated "buf" with at least "size" bytes.  */
 
-void
-assemble_nop (size, buf)
-     size_t size;
-     char *buf;
+static void
+assemble_nop (int size, char *buf)
 {
   static xtensa_insnbuf insnbuf = NULL;
-  TInsn t_insn;
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
+  TInsn tinsn;
 
-  tinsn_init (&t_insn);
-  switch (size)
-    {
-    case 2:
-      t_insn.opcode = xtensa_nop_n_opcode;
-      t_insn.ntok = 0;
-      if (t_insn.opcode == XTENSA_UNDEFINED)
-	as_fatal (_("opcode 'NOP.N' unavailable in this configuration"));
-      tinsn_to_insnbuf (&t_insn, insnbuf);
-      xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf);
-      break;
+  build_nop (&tinsn, size);
 
-    case 3:
-      t_insn.opcode = xtensa_or_opcode;
-      assert (t_insn.opcode != XTENSA_UNDEFINED);
-      if (t_insn.opcode == XTENSA_UNDEFINED)
-	as_fatal (_("opcode 'OR' unavailable in this configuration"));
-      set_expr_const (&t_insn.tok[0], 1);
-      set_expr_const (&t_insn.tok[1], 1);
-      set_expr_const (&t_insn.tok[2], 1);
-      t_insn.ntok = 3;
-      tinsn_to_insnbuf (&t_insn, insnbuf);
-      xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, buf);
-      break;
+  if (!insnbuf)
+    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
 
-    default:
-      as_fatal (_("invalid %d-byte NOP requested"), size);
-    }
+  tinsn_to_insnbuf (&tinsn, insnbuf);
+  xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf,
+			   (unsigned char *) buf, 0);
 }
 
 
@@ -4625,14 +4661,12 @@ assemble_nop (size, buf)
    opcode.  */
 
 static addressT
-get_expanded_loop_offset (opcode)
-     xtensa_opcode opcode;
+get_expanded_loop_offset (xtensa_opcode opcode)
 {
   /* This is the OFFSET of the loop instruction in the expanded loop.
      This MUST correspond directly to the specification of the loop
      expansion.  It will be validated on fragment conversion.  */
-  if (opcode == XTENSA_UNDEFINED)
-    as_fatal (_("get_expanded_loop_offset: undefined opcode"));
+  assert (opcode != XTENSA_UNDEFINED);
   if (opcode == xtensa_loop_opcode)
     return 0;
   if (opcode == xtensa_loopnez_opcode)
@@ -4644,45 +4678,252 @@ get_expanded_loop_offset (opcode)
 }
 
 
-fragS *
-get_literal_pool_location (seg)
-     segT seg;
+static fragS *
+get_literal_pool_location (segT seg)
 {
   return seg_info (seg)->tc_segment_info_data.literal_pool_loc;
 }
 
 
 static void
-set_literal_pool_location (seg, literal_pool_loc)
-     segT seg;
-     fragS *literal_pool_loc;
+set_literal_pool_location (segT seg, fragS *literal_pool_loc)
 {
   seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc;
 }
 
+
+/* Set frag assembly state should be called when a new frag is
+   opened and after a frag has been closed.  */
+
+static void
+xtensa_set_frag_assembly_state (fragS *fragP)
+{
+  if (!density_supported)
+    fragP->tc_frag_data.is_no_density = TRUE;
+
+  /* This function is called from subsegs_finish, which is called
+     after xtensa_end, so we can't use "use_transform" or
+     "use_schedule" here.  */
+  if (!directive_state[directive_transform])
+    fragP->tc_frag_data.is_no_transform = TRUE;
+  if (directive_state[directive_longcalls])
+    fragP->tc_frag_data.use_longcalls = TRUE;
+  fragP->tc_frag_data.use_absolute_literals =
+    directive_state[directive_absolute_literals];
+  fragP->tc_frag_data.is_assembly_state_set = TRUE;
+}
+
+
+static bfd_boolean
+relaxable_section (asection *sec)
+{
+  return (sec->flags & SEC_DEBUGGING) == 0;
+}
+
+
+static void
+xtensa_find_unmarked_state_frags (void)
+{
+  segT *seclist;
+
+  /* Walk over each fragment of all of the current segments.  For each
+     unmarked fragment, mark it with the same info as the previous
+     fragment.  */
+  for (seclist = &stdoutput->sections;
+       seclist && *seclist;
+       seclist = &(*seclist)->next)
+    {
+      segT sec = *seclist;
+      segment_info_type *seginfo;
+      fragS *fragP;
+      flagword flags;
+      flags = bfd_get_section_flags (stdoutput, sec);
+      if (flags & SEC_DEBUGGING)
+	continue;
+      if (!(flags & SEC_ALLOC))
+	continue;
+
+      seginfo = seg_info (sec);
+      if (seginfo && seginfo->frchainP)
+	{
+	  fragS *last_fragP = 0;
+	  for (fragP = seginfo->frchainP->frch_root; fragP;
+	       fragP = fragP->fr_next)
+	    {
+	      if (fragP->fr_fix != 0
+		  && !fragP->tc_frag_data.is_assembly_state_set)
+		{
+		  if (last_fragP == 0)
+		    {
+		      as_warn_where (fragP->fr_file, fragP->fr_line,
+				     _("assembly state not set for first frag in section %s"),
+				     sec->name);
+		    }
+		  else
+		    {
+		      fragP->tc_frag_data.is_assembly_state_set = TRUE;
+		      fragP->tc_frag_data.is_no_density =
+			last_fragP->tc_frag_data.is_no_density;
+		      fragP->tc_frag_data.is_no_transform =
+			last_fragP->tc_frag_data.is_no_transform;
+		      fragP->tc_frag_data.use_longcalls =
+			last_fragP->tc_frag_data.use_longcalls;
+		      fragP->tc_frag_data.use_absolute_literals =
+			last_fragP->tc_frag_data.use_absolute_literals;
+		    }
+		}
+	      if (fragP->tc_frag_data.is_assembly_state_set)
+		last_fragP = fragP;
+	    }
+	}
+    }
+}
+
+
+static void
+xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED,
+				      asection *sec,
+				      void *unused ATTRIBUTE_UNUSED)
+{
+  flagword flags = bfd_get_section_flags (abfd, sec);
+  segment_info_type *seginfo = seg_info (sec);
+  fragS *frag = seginfo->frchainP->frch_root;
+
+  if (flags & SEC_CODE)
+    {
+      xtensa_isa isa = xtensa_default_isa;
+      xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
+      while (frag != NULL)
+	{
+	  if (frag->tc_frag_data.is_branch_target)
+	    {
+	      int op_size;
+	      addressT branch_align, frag_addr;
+	      xtensa_format fmt;
+
+	      xtensa_insnbuf_from_chars
+		(isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
+	      fmt = xtensa_format_decode (isa, insnbuf);
+	      op_size = xtensa_format_length (isa, fmt);
+	      branch_align = 1 << branch_align_power (sec);
+	      frag_addr = frag->fr_address % branch_align;
+	      if (frag_addr + op_size > branch_align)
+		as_warn_where (frag->fr_file, frag->fr_line,
+			       _("unaligned branch target: %d bytes at 0x%lx"),
+			       op_size, (long) frag->fr_address);
+	    }
+	  frag = frag->fr_next;
+	}
+      xtensa_insnbuf_free (isa, insnbuf);
+    }
+}
+
+
+static void
+xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED,
+			     asection *sec,
+			     void *unused ATTRIBUTE_UNUSED)
+{
+  flagword flags = bfd_get_section_flags (abfd, sec);
+  segment_info_type *seginfo = seg_info (sec);
+  fragS *frag = seginfo->frchainP->frch_root;
+  xtensa_isa isa = xtensa_default_isa;
+
+  if (flags & SEC_CODE)
+    {
+      xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa);
+      while (frag != NULL)
+	{
+	  if (frag->tc_frag_data.is_first_loop_insn)
+	    {
+	      int op_size;
+	      addressT frag_addr;
+	      xtensa_format fmt;
+
+	      xtensa_insnbuf_from_chars
+		(isa, insnbuf, (unsigned char *) frag->fr_literal, 0);
+	      fmt = xtensa_format_decode (isa, insnbuf);
+	      op_size = xtensa_format_length (isa, fmt);
+	      frag_addr = frag->fr_address % xtensa_fetch_width;
+
+	      if (frag_addr + op_size > xtensa_fetch_width)
+		as_warn_where (frag->fr_file, frag->fr_line,
+			       _("unaligned loop: %d bytes at 0x%lx"),
+			       op_size, (long) frag->fr_address);
+	    }
+	  frag = frag->fr_next;
+	}
+      xtensa_insnbuf_free (isa, insnbuf);
+    }
+}
+
+
+static int
+xg_apply_fix_value (fixS *fixP, valueT val)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  static xtensa_insnbuf insnbuf = NULL;
+  static xtensa_insnbuf slotbuf = NULL;
+  xtensa_format fmt;
+  int slot;
+  bfd_boolean alt_reloc;
+  xtensa_opcode opcode;
+  char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc);
+  if (alt_reloc)
+    as_fatal (_("unexpected fix"));
+
+  if (!insnbuf)
+    {
+      insnbuf = xtensa_insnbuf_alloc (isa);
+      slotbuf = xtensa_insnbuf_alloc (isa);
+    }
+
+  xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+  if (fmt == XTENSA_UNDEFINED)
+    as_fatal (_("undecodable fix"));
+  xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
+  opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
+  if (opcode == XTENSA_UNDEFINED)
+    as_fatal (_("undecodable fix"));
+
+  /* CONST16 immediates are not PC-relative, despite the fact that we
+     reuse the normal PC-relative operand relocations for the low part
+     of a CONST16 operand.  */
+  if (opcode == xtensa_const16_opcode)
+    return 0;
+
+  xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode,
+			      get_relaxable_immed (opcode), val,
+			      fixP->fx_file, fixP->fx_line);
+
+  xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf);
+  xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0);
+
+  return 1;
+}
+
 
 /* External Functions and Other GAS Hooks.  */
 
 const char *
-xtensa_target_format ()
+xtensa_target_format (void)
 {
   return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le");
 }
 
 
 void
-xtensa_file_arch_init (abfd)
-     bfd *abfd;
+xtensa_file_arch_init (bfd *abfd)
 {
   bfd_set_private_flags (abfd, 0x100 | 0x200);
 }
 
 
 void
-md_number_to_chars (buf, val, n)
-     char *buf;
-     valueT val;
-     int n;
+md_number_to_chars (char *buf, valueT val, int n)
 {
   if (target_big_endian)
     number_to_chars_bigendian (buf, val, n);
@@ -4696,27 +4937,28 @@ md_number_to_chars (buf, val, n)
    need.  */
 
 void
-md_begin ()
+md_begin (void)
 {
   segT current_section = now_seg;
   int current_subsec = now_subseg;
   xtensa_isa isa;
 
-#if STATIC_LIBISA
-  isa = xtensa_isa_init ();
-#else
-  /* ISA was already initialized by xtensa_init().  */
+  xtensa_default_isa = xtensa_isa_init (0, 0);
   isa = xtensa_default_isa;
-#endif
 
-  /* Set  up the .literal, .fini.literal and .init.literal sections.  */
+  linkrelax = 1;
+
+  /* Set up the .literal, .fini.literal and .init.literal sections.  */
   memset (&default_lit_sections, 0, sizeof (default_lit_sections));
   default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME;
   default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME;
   default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME;
+  default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME;
 
   subseg_set (current_section, current_subsec);
 
+  xg_init_vinsn (&cur_vinsn);
+
   xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi");
   xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi");
   xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0");
@@ -4727,75 +4969,175 @@ md_begin ()
   xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4");
   xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8");
   xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12");
+  xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16");
   xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry");
+  xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi");
+  xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n");
   xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync");
-  xtensa_j_opcode = xtensa_opcode_lookup (isa, "j");
   xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx");
+  xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r");
   xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop");
   xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez");
   xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz");
+  xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop");
   xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n");
   xtensa_or_opcode = xtensa_opcode_lookup (isa, "or");
   xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret");
   xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n");
   xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw");
   xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n");
-  xtensa_rsr_opcode = xtensa_opcode_lookup (isa, "rsr");
+  xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount");
   xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti");
+
+  init_op_placement_info_table ();
+
+  /* Set up the assembly state.  */
+  if (!frag_now->tc_frag_data.is_assembly_state_set)
+    xtensa_set_frag_assembly_state (frag_now);
+}
+
+
+/* TC_INIT_FIX_DATA hook */
+
+void
+xtensa_init_fix_data (fixS *x)
+{
+  x->tc_fix_data.slot = 0;
+  x->tc_fix_data.X_add_symbol = NULL;
+  x->tc_fix_data.X_add_number = 0;
 }
 
 
 /* tc_frob_label hook */
 
 void
-xtensa_frob_label (sym)
-     symbolS *sym;
+xtensa_frob_label (symbolS *sym)
 {
+  float freq;
+
+  if (cur_vinsn.inside_bundle)
+    {
+      as_bad (_("labels are not valid inside bundles"));
+      return;
+    }
+
+  freq = get_subseg_target_freq (now_seg, now_subseg);
+
+  /* Since the label was already attached to a frag associated with the
+     previous basic block, it now needs to be reset to the current frag.  */
+  symbol_set_frag (sym, frag_now);
+  S_SET_VALUE (sym, (valueT) frag_now_fix ());
+
   if (generating_literals)
     xtensa_add_literal_sym (sym);
   else
     xtensa_add_insn_label (sym);
 
-  if (symbol_get_tc (sym)->is_loop_target
-      && (get_last_insn_flags (now_seg, now_subseg)
+  if (symbol_get_tc (sym)->is_loop_target)
+    {
+      if ((get_last_insn_flags (now_seg, now_subseg)
 	  & FLAG_IS_BAD_LOOPEND) != 0)
-    as_bad (_("invalid last instruction for a zero-overhead loop"));
+	as_bad (_("invalid last instruction for a zero-overhead loop"));
+
+      xtensa_set_frag_assembly_state (frag_now);
+      frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END,
+		frag_now->fr_symbol, frag_now->fr_offset, NULL);
+
+      xtensa_set_frag_assembly_state (frag_now);
+      xtensa_move_labels (frag_now, 0, TRUE);
+    }
 
   /* No target aligning in the absolute section.  */
   if (now_seg != absolute_section
-      && align_targets
+      && do_align_targets ()
       && !is_unaligned_label (sym)
-      && !frag_now->tc_frag_data.is_literal)
+      && !generating_literals)
     {
-      /* frag_now->tc_frag_data.is_insn = TRUE; */
-      frag_var (rs_machine_dependent, 4, 4,
+      xtensa_set_frag_assembly_state (frag_now);
+
+      frag_var (rs_machine_dependent,
+		0, (int) freq,
 		RELAX_DESIRE_ALIGN_IF_TARGET,
 		frag_now->fr_symbol, frag_now->fr_offset, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
       xtensa_move_labels (frag_now, 0, TRUE);
+    }
+
+  /* We need to mark the following properties even if we aren't aligning.  */
+
+  /* If the label is already known to be a branch target, i.e., a
+     forward branch, mark the frag accordingly.  Backward branches
+     are handled by xg_add_branch_and_loop_targets.  */
+  if (symbol_get_tc (sym)->is_branch_target)
+    symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
+
+  /* Loops only go forward, so they can be identified here.  */
+  if (symbol_get_tc (sym)->is_loop_target)
+    symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
+
+  dwarf2_emit_label (sym);
+}
 
-      /* If the label is already known to be a branch target, i.e., a
-	 forward branch, mark the frag accordingly.  Backward branches
-	 are handled by xg_add_branch_and_loop_targets.  */
-      if (symbol_get_tc (sym)->is_branch_target)
-	symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE;
 
-      /* Loops only go forward, so they can be identified here.  */
-      if (symbol_get_tc (sym)->is_loop_target)
-	symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE;
+/* tc_unrecognized_line hook */
+
+int
+xtensa_unrecognized_line (int ch)
+{
+  switch (ch)
+    {
+    case '{' :
+      if (cur_vinsn.inside_bundle == 0)
+	{
+	  /* PR8110: Cannot emit line number info inside a FLIX bundle
+	     when using --gstabs.  Temporarily disable debug info.  */
+	  generate_lineno_debug ();
+	  if (debug_type == DEBUG_STABS)
+	    {
+	      xt_saved_debug_type = debug_type;
+	      debug_type = DEBUG_NONE;
+	    }
+
+	  cur_vinsn.inside_bundle = 1;
+	}
+      else
+	{
+	  as_bad (_("extra opening brace"));
+	  return 0;
+	}
+      break;
+
+    case '}' :
+      if (cur_vinsn.inside_bundle)
+	finish_vinsn (&cur_vinsn);
+      else
+	{
+	  as_bad (_("extra closing brace"));
+	  return 0;
+	}
+      break;
+    default:
+      as_bad (_("syntax error"));
+      return 0;
     }
+  return 1;
 }
 
 
 /* md_flush_pending_output hook */
 
 void
-xtensa_flush_pending_output ()
+xtensa_flush_pending_output (void)
 {
+  if (cur_vinsn.inside_bundle)
+    as_bad (_("missing closing brace"));
+
   /* If there is a non-zero instruction fragment, close it.  */
   if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn)
     {
       frag_wane (frag_now);
       frag_new (0);
+      xtensa_set_frag_assembly_state (frag_now);
     }
   frag_now->tc_frag_data.is_insn = FALSE;
 
@@ -4803,33 +5145,36 @@ xtensa_flush_pending_output ()
 }
 
 
+/* We had an error while parsing an instruction.  The string might look
+   like this: "insn arg1, arg2 }".  If so, we need to see the closing
+   brace and reset some fields.  Otherwise, the vinsn never gets closed
+   and the num_slots field will grow past the end of the array of slots,
+   and bad things happen.  */
+
+static void
+error_reset_cur_vinsn (void)
+{
+  if (cur_vinsn.inside_bundle)
+    {
+      if (*input_line_pointer == '}'
+	  || *(input_line_pointer - 1) == '}'
+	  || *(input_line_pointer - 2) == '}')
+	xg_clear_vinsn (&cur_vinsn);
+    }
+}
+
+
 void
-md_assemble (str)
-     char *str;
+md_assemble (char *str)
 {
   xtensa_isa isa = xtensa_default_isa;
-  char *opname;
+  char *opname, *file_name;
   unsigned opnamelen;
   bfd_boolean has_underbar = FALSE;
-  char *arg_strings[MAX_INSN_ARGS]; 
+  char *arg_strings[MAX_INSN_ARGS];
   int num_args;
-  IStack istack;		/* Put instructions into here.  */
   TInsn orig_insn;		/* Original instruction from the input.  */
-  int i;
-  symbolS *lit_sym = NULL;
-
-  if (frag_now->tc_frag_data.is_literal)
-    {
-      static bfd_boolean reported = 0;
-      if (reported < 4)
-	as_bad (_("cannot assemble '%s' into a literal fragment"), str);
-      if (reported == 3)
-	as_bad (_("..."));
-      reported++;
-      return;
-    }
 
-  istack_init (&istack);
   tinsn_init (&orig_insn);
 
   /* Split off the opcode.  */
@@ -4857,52 +5202,38 @@ md_assemble (str)
 
   orig_insn.insn_type = ITYPE_INSN;
   orig_insn.ntok = 0;
-  orig_insn.is_specific_opcode = (has_underbar || !use_generics ());
-  specific_opcode = orig_insn.is_specific_opcode;
+  orig_insn.is_specific_opcode = (has_underbar || !use_transform ());
 
   orig_insn.opcode = xtensa_opcode_lookup (isa, opname);
   if (orig_insn.opcode == XTENSA_UNDEFINED)
     {
-      as_bad (_("unknown opcode %s"), opname);
-      return;
-    }
-
-  if (frag_now_fix () != 0 && !frag_now->tc_frag_data.is_insn)
-    {
-      frag_wane (frag_now);
-      frag_new (0);
-    }
-
-  if (software_a0_b_retw_interlock)
-    {
-      if ((get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
-	  && is_conditional_branch_opcode (orig_insn.opcode))
+      xtensa_format fmt = xtensa_format_lookup (isa, opname);
+      if (fmt == XTENSA_UNDEFINED)
 	{
-	  has_a0_b_retw = TRUE;
-
-	  /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
-	     After the first assembly pass we will check all of them and
-	     add a nop if needed.  */
-	  frag_now->tc_frag_data.is_insn = TRUE;
-	  frag_var (rs_machine_dependent, 4, 4,
-		    RELAX_ADD_NOP_IF_A0_B_RETW,
-		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
-	  frag_now->tc_frag_data.is_insn = TRUE;
-	  frag_var (rs_machine_dependent, 4, 4,
-		    RELAX_ADD_NOP_IF_A0_B_RETW,
-		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	  as_bad (_("unknown opcode or format name '%s'"), opname);
+	  error_reset_cur_vinsn ();
+	  return;
+	}
+      if (!cur_vinsn.inside_bundle)
+	{
+	  as_bad (_("format names only valid inside bundles"));
+	  error_reset_cur_vinsn ();
+	  return;
 	}
+      if (cur_vinsn.format != XTENSA_UNDEFINED)
+	as_warn (_("multiple formats specified for one bundle; using '%s'"),
+		 opname);
+      cur_vinsn.format = fmt;
+      free (has_underbar ? opname - 1 : opname);
+      error_reset_cur_vinsn ();
+      return;
     }
 
-  /* Special case: The call instructions should be marked "specific opcode"
-     to keep them from expanding.  */
-  if (!use_longcalls () && is_direct_call_opcode (orig_insn.opcode))
-    orig_insn.is_specific_opcode = TRUE;
-
   /* Parse the arguments.  */
   if (parse_arguments (&orig_insn, num_args, arg_strings))
     {
       as_bad (_("syntax error"));
+      error_reset_cur_vinsn ();
       return;
     }
 
@@ -4912,176 +5243,102 @@ md_assemble (str)
   while (num_args-- > 0)
     free (arg_strings[num_args]);
 
-  /* Check for the right number and type of arguments.  */
-  if (tinsn_check_arguments (&orig_insn))
-    return;
-
-  /* See if the instruction implies an aligned section.  */
-  if (is_entry_opcode (orig_insn.opcode) || is_loop_opcode (orig_insn.opcode))
-    record_alignment (now_seg, 2);
-
-  xg_add_branch_and_loop_targets (&orig_insn);
-
-  /* Special cases for instructions that force an alignment... */
-  if (!orig_insn.is_specific_opcode && is_loop_opcode (orig_insn.opcode))
+  /* Get expressions for invisible operands.  */
+  if (get_invisible_operands (&orig_insn))
     {
-      size_t max_fill;
-
-      frag_now->tc_frag_data.is_insn = TRUE;
-      frag_now->tc_frag_data.is_no_density = !code_density_available ();
-      max_fill = get_text_align_max_fill_size
-	(get_text_align_power (XTENSA_FETCH_WIDTH),
-	 TRUE, frag_now->tc_frag_data.is_no_density);
-      frag_var (rs_machine_dependent, max_fill, max_fill,
-		RELAX_ALIGN_NEXT_OPCODE, frag_now->fr_symbol,
-		frag_now->fr_offset, NULL);
-
-      xtensa_move_labels (frag_now, 0, FALSE);
+      error_reset_cur_vinsn ();
+      return;
     }
 
-  /* Special-case for "entry" instruction.  */
-  if (is_entry_opcode (orig_insn.opcode))
+  /* Check for the right number and type of arguments.  */
+  if (tinsn_check_arguments (&orig_insn))
     {
-      /* Check that the second opcode (#1) is >= 16.  */
-      if (orig_insn.ntok >= 2)
-	{
-	  expressionS *exp = &orig_insn.tok[1];
-	  switch (exp->X_op)
-	    {
-	    case O_constant:
-	      if (exp->X_add_number < 16)
-		as_warn (_("entry instruction with stack decrement < 16"));
-	      break;
-
-	    default:
-	      as_warn (_("entry instruction with non-constant decrement"));
-	    }
-	}
-
-      if (!orig_insn.is_specific_opcode)
-	{
-	  xtensa_mark_literal_pool_location ();
-
-	  /* Automatically align ENTRY instructions.  */
-	  xtensa_move_labels (frag_now, 0, TRUE);
-	  frag_align (2, 0, 0);
-	}
+      error_reset_cur_vinsn ();
+      return;
     }
 
-  /* Any extra alignment frags have been inserted now, and we're about to
-     emit a new instruction so clear the list of labels.  */
-  xtensa_clear_insn_labels ();
+  /* A FLIX bundle may be spread across multiple input lines.  We want to
+     report the first such line in the debug information.  Record the line
+     number for each TInsn (assume the file name doesn't change), so the
+     first line can be found later.  */
+  as_where (&file_name, &orig_insn.linenum);
 
-  if (software_a0_b_retw_interlock)
-    set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
-			 is_register_writer (&orig_insn, "a", 0));
+  xg_add_branch_and_loop_targets (&orig_insn);
 
-  set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
-		       is_bad_loopend_opcode (&orig_insn));
+  /* Check that immediate value for ENTRY is >= 16.  */
+  if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3)
+    {
+      expressionS *exp = &orig_insn.tok[2];
+      if (exp->X_op == O_constant && exp->X_add_number < 16)
+	as_warn (_("entry instruction with stack decrement < 16"));
+    }
 
   /* Finish it off:
-     assemble_tokens (opcode, tok, ntok); 
-     expand the tokens from the orig_insn into the 
-     stack of instructions that will not expand 
+     assemble_tokens (opcode, tok, ntok);
+     expand the tokens from the orig_insn into the
+     stack of instructions that will not expand
      unless required at relaxation time.  */
-  if (xg_expand_assembly_insn (&istack, &orig_insn))
-    return;
 
-  for (i = 0; i < istack.ninsn; i++)
+  if (!cur_vinsn.inside_bundle)
+    emit_single_op (&orig_insn);
+  else /* We are inside a bundle.  */
     {
-      TInsn *insn = &istack.insn[i];
-      if (insn->insn_type == ITYPE_LITERAL)
-	{
-	  assert (lit_sym == NULL);
-	  lit_sym = xg_assemble_literal (insn);
-	}
-      else
-	{
-	  if (lit_sym)
-	    xg_resolve_literals (insn, lit_sym);
-	  xg_assemble_tokens (insn);
-	}
+      cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn;
+      cur_vinsn.num_slots++;
+      if (*input_line_pointer == '}'
+	  || *(input_line_pointer - 1) == '}'
+	  || *(input_line_pointer - 2) == '}')
+	finish_vinsn (&cur_vinsn);
     }
 
-  /* Now, if the original opcode was a call... */
-  if (align_targets && is_call_opcode (orig_insn.opcode))
-    {
-      frag_now->tc_frag_data.is_insn = TRUE;
-      frag_var (rs_machine_dependent, 4, 4,
-		RELAX_DESIRE_ALIGN,
-		frag_now->fr_symbol,
-		frag_now->fr_offset,
-		NULL);
-    }
+  /* We've just emitted a new instruction so clear the list of labels.  */
+  xtensa_clear_insn_labels ();
 }
 
 
-/* TC_CONS_FIX_NEW hook: Check for "@PLT" suffix on symbol references.
-   If found, use an XTENSA_PLT reloc for 4-byte values.  Otherwise, this
-   is the same as the standard code in read.c.  */
+/* HANDLE_ALIGN hook */
 
-void 
-xtensa_cons_fix_new (frag, where, size, exp)
-     fragS *frag;
-     int where; 
-     int size;
-     expressionS *exp;
-{
-  bfd_reloc_code_real_type r;
-  bfd_boolean plt = FALSE;
+/* For a .align directive, we mark the previous block with the alignment
+   information.  This will be placed in the object file in the
+   property section corresponding to this section.  */
 
-  if (*input_line_pointer == '@') 
+void
+xtensa_handle_align (fragS *fragP)
+{
+  if (linkrelax
+      && ! fragP->tc_frag_data.is_literal
+      && (fragP->fr_type == rs_align
+	  || fragP->fr_type == rs_align_code)
+      && fragP->fr_address + fragP->fr_fix > 0
+      && fragP->fr_offset > 0
+      && now_seg != bss_section)
     {
-      if (!strncmp (input_line_pointer, PLT_SUFFIX, strlen (PLT_SUFFIX) - 1)
-	  && !strncmp (input_line_pointer, plt_suffix,
-		       strlen (plt_suffix) - 1))
-	{
-	  as_bad (_("undefined @ suffix '%s', expected '%s'"), 
-		  input_line_pointer, plt_suffix);
-	  ignore_rest_of_line ();
-	  return;
-	}
-
-      input_line_pointer += strlen (plt_suffix);
-      plt = TRUE;
+      fragP->tc_frag_data.is_align = TRUE;
+      fragP->tc_frag_data.alignment = fragP->fr_offset;
     }
 
-  switch (size)
+  if (fragP->fr_type == rs_align_test)
     {
-    case 1:
-      r = BFD_RELOC_8;
-      break;
-    case 2:
-      r = BFD_RELOC_16;
-      break;
-    case 4:
-      r = plt ? BFD_RELOC_XTENSA_PLT : BFD_RELOC_32;
-      break;
-    case 8:
-      r = BFD_RELOC_64;
-      break;
-    default:
-      as_bad (_("unsupported BFD relocation size %u"), size);
-      r = BFD_RELOC_32;
-      break;
+      int count;
+      count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
+      if (count != 0)
+	as_bad_where (fragP->fr_file, fragP->fr_line,
+		      _("unaligned entry instruction"));
     }
-  fix_new_exp (frag, where, size, exp, 0, r);
 }
-  
+
 
 /* TC_FRAG_INIT hook */
 
 void
-xtensa_frag_init (frag)
-     fragS *frag;
+xtensa_frag_init (fragS *frag)
 {
-  frag->tc_frag_data.is_no_density = !code_density_available ();
+  xtensa_set_frag_assembly_state (frag);
 }
 
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return NULL;
 }
@@ -5090,95 +5347,180 @@ md_undefined_symbol (name)
 /* Round up a section size to the appropriate boundary.  */
 
 valueT
-md_section_align (segment, size)
-     segT segment ATTRIBUTE_UNUSED;
-     valueT size;
+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
 {
   return size;			/* Byte alignment is fine.  */
 }
 
 
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   char *insn_p;
   static xtensa_insnbuf insnbuf = NULL;
+  static xtensa_insnbuf slotbuf = NULL;
   int opnum;
-  xtensa_operand operand;
+  uint32 opnd_value;
   xtensa_opcode opcode;
+  xtensa_format fmt;
+  int slot;
   xtensa_isa isa = xtensa_default_isa;
   valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
-
-  if (fixP->fx_done)
-    return addr;
+  bfd_boolean alt_reloc;
 
   if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND)
-    return addr;
+    return 0;
 
   if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (isa);
+    {
+      insnbuf = xtensa_insnbuf_alloc (isa);
+      slotbuf = xtensa_insnbuf_alloc (isa);
+    }
 
   insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where];
-  xtensa_insnbuf_from_chars (isa, insnbuf, insn_p);
-  opcode = xtensa_decode_insn (isa, insnbuf);
+  xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+
+  if (fmt == XTENSA_UNDEFINED)
+    as_fatal (_("bad instruction format"));
 
-  opnum = reloc_to_opnum (fixP->fx_r_type);
+  if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0)
+    as_fatal (_("invalid relocation"));
 
-  if (opnum < 0)
-    as_fatal (_("invalid operand relocation for '%s' instruction"),
-	      xtensa_opcode_name (isa, opcode));
-  if (opnum >= xtensa_num_operands (isa, opcode))
-    as_fatal (_("invalid relocation for operand %d in '%s' instruction"),
-	      opnum, xtensa_opcode_name (isa, opcode));
-  operand = xtensa_get_operand (isa, opcode, opnum);
-  if (!operand)
+  xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
+  opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
+
+  /* Check for "alternate" relocations (operand not specified).  None
+     of the current uses for these are really PC-relative.  */
+  if (alt_reloc || opcode == xtensa_const16_opcode)
     {
-      as_warn_where (fixP->fx_file,
-		     fixP->fx_line,
-		     _("invalid relocation type %d for %s instruction"),
-		     fixP->fx_r_type, xtensa_opcode_name (isa, opcode));
-      return addr;
+      if (opcode != xtensa_l32r_opcode
+	  && opcode != xtensa_const16_opcode)
+	as_fatal (_("invalid relocation for '%s' instruction"),
+		  xtensa_opcode_name (isa, opcode));
+      return 0;
     }
 
-  if (!operand_is_pcrel_label (operand))
+  opnum = get_relaxable_immed (opcode);
+  opnd_value = 0;
+  if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1
+      || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr))
     {
       as_bad_where (fixP->fx_file,
 		    fixP->fx_line,
 		    _("invalid relocation for operand %d of '%s'"),
 		    opnum, xtensa_opcode_name (isa, opcode));
-      return addr;
+      return 0;
     }
-  if (!xtensa_operand_isPCRelative (operand))
+  return 0 - opnd_value;
+}
+
+
+/* TC_FORCE_RELOCATION hook */
+
+int
+xtensa_force_relocation (fixS *fix)
+{
+  switch (fix->fx_r_type)
     {
-      as_warn_where (fixP->fx_file,
-		     fixP->fx_line,
-		     _("non-PCREL relocation operand %d for '%s': %s"),
-		     opnum, xtensa_opcode_name (isa, opcode),
-		     bfd_get_reloc_code_name (fixP->fx_r_type));
-      return addr;
+    case BFD_RELOC_XTENSA_ASM_EXPAND:
+    case BFD_RELOC_XTENSA_SLOT0_ALT:
+    case BFD_RELOC_XTENSA_SLOT1_ALT:
+    case BFD_RELOC_XTENSA_SLOT2_ALT:
+    case BFD_RELOC_XTENSA_SLOT3_ALT:
+    case BFD_RELOC_XTENSA_SLOT4_ALT:
+    case BFD_RELOC_XTENSA_SLOT5_ALT:
+    case BFD_RELOC_XTENSA_SLOT6_ALT:
+    case BFD_RELOC_XTENSA_SLOT7_ALT:
+    case BFD_RELOC_XTENSA_SLOT8_ALT:
+    case BFD_RELOC_XTENSA_SLOT9_ALT:
+    case BFD_RELOC_XTENSA_SLOT10_ALT:
+    case BFD_RELOC_XTENSA_SLOT11_ALT:
+    case BFD_RELOC_XTENSA_SLOT12_ALT:
+    case BFD_RELOC_XTENSA_SLOT13_ALT:
+    case BFD_RELOC_XTENSA_SLOT14_ALT:
+      return 1;
+    default:
+      break;
     }
 
-  return 0 - xtensa_operand_do_reloc (operand, 0, addr);
+  if (linkrelax && fix->fx_addsy
+      && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
+    return 1;
+
+  return generic_force_reloc (fix);
 }
 
 
-/* tc_symbol_new_hook */
+/* TC_VALIDATE_FIX_SUB hook */
+
+int
+xtensa_validate_fix_sub (fixS *fix)
+{
+  segT add_symbol_segment, sub_symbol_segment;
+
+  /* The difference of two symbols should be resolved by the assembler when
+     linkrelax is not set.  If the linker may relax the section containing
+     the symbols, then an Xtensa DIFF relocation must be generated so that
+     the linker knows to adjust the difference value.  */
+  if (!linkrelax || fix->fx_addsy == NULL)
+    return 0;
+
+  /* Make sure both symbols are in the same segment, and that segment is
+     "normal" and relaxable.  If the segment is not "normal", then the
+     fix is not valid.  If the segment is not "relaxable", then the fix
+     should have been handled earlier.  */
+  add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
+  if (! SEG_NORMAL (add_symbol_segment) ||
+      ! relaxable_section (add_symbol_segment))
+    return 0;
+  sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
+  return (sub_symbol_segment == add_symbol_segment);
+}
+
+
+/* NO_PSEUDO_DOT hook */
+
+/* This function has nothing to do with pseudo dots, but this is the
+   nearest macro to where the check needs to take place.  FIXME: This
+   seems wrong.  */
+
+bfd_boolean
+xtensa_check_inside_bundle (void)
+{
+  if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.')
+    as_bad (_("directives are not valid inside bundles"));
+
+  /* This function must always return FALSE because it is called via a
+     macro that has nothing to do with bundling.  */
+  return FALSE;
+}
+
+
+/* md_elf_section_change_hook */
 
 void
-xtensa_symbol_new_hook (symbolP)
-     symbolS *symbolP;
+xtensa_elf_section_change_hook (void)
 {
-  symbol_get_tc (symbolP)->plt = 0;
+  /* Set up the assembly state.  */
+  if (!frag_now->tc_frag_data.is_assembly_state_set)
+    xtensa_set_frag_assembly_state (frag_now);
 }
 
 
 /* tc_fix_adjustable hook */
 
 bfd_boolean
-xtensa_fix_adjustable (fixP)
-     fixS *fixP;
-{
+xtensa_fix_adjustable (fixS *fixP)
+{
+  /* An offset is not allowed in combination with the difference of two
+     symbols, but that cannot be easily detected after a local symbol
+     has been adjusted to a (section+offset) form.  Return 0 so that such
+     an fix will not be adjusted.  */
+  if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset
+      && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy)))
+    return 0;
+
   /* We need the symbol name for the VTABLE entries.  */
   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
@@ -5189,79 +5531,143 @@ xtensa_fix_adjustable (fixP)
 
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix (fixS *fixP, valueT *valP, segT seg)
 {
-  if (fixP->fx_pcrel == 0 && fixP->fx_addsy == 0)
-    {
-      /* This happens when the relocation is within the current section. 
-         It seems this implies a PCREL operation.  We'll catch it and error 
-         if not.  */
+  char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
+  valueT val = 0;
 
-      char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
-      static xtensa_insnbuf insnbuf = NULL;
-      xtensa_opcode opcode;
-      xtensa_isa isa;
+  /* Subtracted symbols are only allowed for a few relocation types, and
+     unless linkrelax is enabled, they should not make it to this point.  */
+  if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32
+					|| fixP->fx_r_type == BFD_RELOC_16
+					|| fixP->fx_r_type == BFD_RELOC_8)))
+    as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
 
-      switch (fixP->fx_r_type)
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_32:
+    case BFD_RELOC_16:
+    case BFD_RELOC_8:
+      if (fixP->fx_subsy)
 	{
-	case BFD_RELOC_XTENSA_ASM_EXPAND:
-	  fixP->fx_done = 1;
-	  break;
-
-	case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
-	  as_bad (_("unhandled local relocation fix %s"),
-		  bfd_get_reloc_code_name (fixP->fx_r_type));
-	  break;
+	  switch (fixP->fx_r_type)
+	    {
+	    case BFD_RELOC_8:
+	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8;
+	      break;
+	    case BFD_RELOC_16:
+	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16;
+	      break;
+	    case BFD_RELOC_32:
+	      fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32;
+	      break;
+	    default:
+	      break;
+	    }
 
-	case BFD_RELOC_32:
-	case BFD_RELOC_16:
-	case BFD_RELOC_8:
-	  /* The only one we support that isn't an instruction field.  */
-	  md_number_to_chars (fixpos, *valP, fixP->fx_size);
+	  /* An offset is only allowed when it results from adjusting a
+	     local symbol into a section-relative offset.  If the offset
+	     came from the original expression, tc_fix_adjustable will have
+	     prevented the fix from being converted to a section-relative
+	     form so that we can flag the error here.  */
+	  if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy))
+	    as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("cannot represent subtraction with an offset"));
+
+	  val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
+		 - S_GET_VALUE (fixP->fx_subsy));
+
+	  /* The difference value gets written out, and the DIFF reloc
+	     identifies the address of the subtracted symbol (i.e., the one
+	     with the lowest address).  */
+	  *valP = val;
+	  fixP->fx_offset -= val;
+	  fixP->fx_subsy = NULL;
+	}
+      else if (! fixP->fx_addsy)
+	{
+	  val = *valP;
 	  fixP->fx_done = 1;
-	  break;
-
-	case BFD_RELOC_XTENSA_OP0:
-	case BFD_RELOC_XTENSA_OP1:
-	case BFD_RELOC_XTENSA_OP2:
-	  isa = xtensa_default_isa;
-	  if (!insnbuf)
-	    insnbuf = xtensa_insnbuf_alloc (isa);
+	}
+      /* fall through */
 
-	  xtensa_insnbuf_from_chars (isa, insnbuf, fixpos);
-	  opcode = xtensa_decode_insn (isa, insnbuf);
-	  if (opcode == XTENSA_UNDEFINED)
-	    as_fatal (_("undecodable FIX"));
+    case BFD_RELOC_XTENSA_PLT:
+      md_number_to_chars (fixpos, val, fixP->fx_size);
+      fixP->fx_no_overflow = 0; /* Use the standard overflow check.  */
+      break;
 
-	  xtensa_insnbuf_set_immediate_field (opcode, insnbuf, *valP,
-					      fixP->fx_file, fixP->fx_line);
+    case BFD_RELOC_XTENSA_SLOT0_OP:
+    case BFD_RELOC_XTENSA_SLOT1_OP:
+    case BFD_RELOC_XTENSA_SLOT2_OP:
+    case BFD_RELOC_XTENSA_SLOT3_OP:
+    case BFD_RELOC_XTENSA_SLOT4_OP:
+    case BFD_RELOC_XTENSA_SLOT5_OP:
+    case BFD_RELOC_XTENSA_SLOT6_OP:
+    case BFD_RELOC_XTENSA_SLOT7_OP:
+    case BFD_RELOC_XTENSA_SLOT8_OP:
+    case BFD_RELOC_XTENSA_SLOT9_OP:
+    case BFD_RELOC_XTENSA_SLOT10_OP:
+    case BFD_RELOC_XTENSA_SLOT11_OP:
+    case BFD_RELOC_XTENSA_SLOT12_OP:
+    case BFD_RELOC_XTENSA_SLOT13_OP:
+    case BFD_RELOC_XTENSA_SLOT14_OP:
+      if (linkrelax)
+	{
+	  /* Write the tentative value of a PC-relative relocation to a
+	     local symbol into the instruction.  The value will be ignored
+	     by the linker, and it makes the object file disassembly
+	     readable when all branch targets are encoded in relocations.  */
+
+	  assert (fixP->fx_addsy);
+	  if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt
+	      && !S_FORCE_RELOC (fixP->fx_addsy, 1))
+	    {
+	      val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset
+		     - md_pcrel_from (fixP));
+	      (void) xg_apply_fix_value (fixP, val);
+	    }
+	}
+      else if (! fixP->fx_addsy)
+	{
+	  val = *valP;
+	  if (xg_apply_fix_value (fixP, val))
+	    fixP->fx_done = 1;
+	}
+      break;
 
-	  fixP->fx_frag->tc_frag_data.is_insn = TRUE;
-	  xtensa_insnbuf_to_chars (isa, insnbuf, fixpos);
-	  fixP->fx_done = 1;
-	  break;
+    case BFD_RELOC_XTENSA_ASM_EXPAND:
+    case BFD_RELOC_XTENSA_SLOT0_ALT:
+    case BFD_RELOC_XTENSA_SLOT1_ALT:
+    case BFD_RELOC_XTENSA_SLOT2_ALT:
+    case BFD_RELOC_XTENSA_SLOT3_ALT:
+    case BFD_RELOC_XTENSA_SLOT4_ALT:
+    case BFD_RELOC_XTENSA_SLOT5_ALT:
+    case BFD_RELOC_XTENSA_SLOT6_ALT:
+    case BFD_RELOC_XTENSA_SLOT7_ALT:
+    case BFD_RELOC_XTENSA_SLOT8_ALT:
+    case BFD_RELOC_XTENSA_SLOT9_ALT:
+    case BFD_RELOC_XTENSA_SLOT10_ALT:
+    case BFD_RELOC_XTENSA_SLOT11_ALT:
+    case BFD_RELOC_XTENSA_SLOT12_ALT:
+    case BFD_RELOC_XTENSA_SLOT13_ALT:
+    case BFD_RELOC_XTENSA_SLOT14_ALT:
+      /* These all need to be resolved at link-time.  Do nothing now.  */
+      break;
 
-	case BFD_RELOC_VTABLE_INHERIT:
-	case BFD_RELOC_VTABLE_ENTRY:
-	  fixP->fx_done = 0;
-	  break;
+    case BFD_RELOC_VTABLE_INHERIT:
+    case BFD_RELOC_VTABLE_ENTRY:
+      fixP->fx_done = 0;
+      break;
 
-	default:
-	  as_bad (_("unhandled local relocation fix %s"),
-		  bfd_get_reloc_code_name (fixP->fx_r_type));
-	}
+    default:
+      as_bad (_("unhandled local relocation fix %s"),
+	      bfd_get_reloc_code_name (fixP->fx_r_type));
     }
 }
 
 
 char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
+md_atof (int type, char *litP, int *sizeP)
 {
   int prec;
   LITTLENUM_TYPE words[4];
@@ -5304,11 +5710,9 @@ md_atof (type, litP, sizeP)
 
 
 int
-md_estimate_size_before_relax (fragP, seg)
-     fragS *fragP;
-     segT seg ATTRIBUTE_UNUSED;
+md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED)
 {
-  return fragP->tc_frag_data.text_expansion;
+  return total_frag_text_expansion (fragP);
 }
 
 
@@ -5316,9 +5720,7 @@ md_estimate_size_before_relax (fragP, seg)
    format.  */
 
 arelent *
-tc_gen_reloc (section, fixp)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixp;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
 {
   arelent *reloc;
 
@@ -5331,82 +5733,1231 @@ tc_gen_reloc (section, fixp)
      They'd better have been fully resolved by this point.  */
   assert ((int) fixp->fx_r_type > 0);
 
+  reloc->addend = fixp->fx_offset;
+
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
   if (reloc->howto == NULL)
     {
       as_bad_where (fixp->fx_file, fixp->fx_line,
 		    _("cannot represent `%s' relocation in object file"),
 		    bfd_get_reloc_code_name (fixp->fx_r_type));
+      free (reloc->sym_ptr_ptr);
+      free (reloc);
       return NULL;
     }
 
   if (!fixp->fx_pcrel != !reloc->howto->pc_relative)
+    as_fatal (_("internal error? cannot generate `%s' relocation"),
+	      bfd_get_reloc_code_name (fixp->fx_r_type));
+
+  return reloc;
+}
+
+
+/* Checks for resource conflicts between instructions.  */
+
+/* The func unit stuff could be implemented as bit-vectors rather
+   than the iterative approach here.  If it ends up being too
+   slow, we will switch it.  */
+
+resource_table *
+new_resource_table (void *data,
+		    int cycles,
+		    int nu,
+		    unit_num_copies_func uncf,
+		    opcode_num_units_func onuf,
+		    opcode_funcUnit_use_unit_func ouuf,
+		    opcode_funcUnit_use_stage_func ousf)
+{
+  int i;
+  resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table));
+  rt->data = data;
+  rt->cycles = cycles;
+  rt->allocated_cycles = cycles;
+  rt->num_units = nu;
+  rt->unit_num_copies = uncf;
+  rt->opcode_num_units = onuf;
+  rt->opcode_unit_use = ouuf;
+  rt->opcode_unit_stage = ousf;
+
+  rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *));
+  for (i = 0; i < cycles; i++)
+    rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char));
+
+  return rt;
+}
+
+
+void
+clear_resource_table (resource_table *rt)
+{
+  int i, j;
+  for (i = 0; i < rt->allocated_cycles; i++)
+    for (j = 0; j < rt->num_units; j++)
+      rt->units[i][j] = 0;
+}
+
+
+/* We never shrink it, just fake it into thinking so.  */
+
+void
+resize_resource_table (resource_table *rt, int cycles)
+{
+  int i, old_cycles;
+
+  rt->cycles = cycles;
+  if (cycles <= rt->allocated_cycles)
+    return;
+
+  old_cycles = rt->allocated_cycles;
+  rt->allocated_cycles = cycles;
+
+  rt->units = xrealloc (rt->units,
+			rt->allocated_cycles * sizeof (unsigned char *));
+  for (i = 0; i < old_cycles; i++)
+    rt->units[i] = xrealloc (rt->units[i],
+			     rt->num_units * sizeof (unsigned char));
+  for (i = old_cycles; i < cycles; i++)
+    rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char));
+}
+
+
+bfd_boolean
+resources_available (resource_table *rt, xtensa_opcode opcode, int cycle)
+{
+  int i;
+  int uses = (rt->opcode_num_units) (rt->data, opcode);
+
+  for (i = 0; i < uses; i++)
     {
-      as_fatal (_("internal error? cannot generate `%s' relocation"),
-		bfd_get_reloc_code_name (fixp->fx_r_type));
+      xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
+      int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
+      int copies_in_use = rt->units[stage + cycle][unit];
+      int copies = (rt->unit_num_copies) (rt->data, unit);
+      if (copies_in_use >= copies)
+	return FALSE;
     }
-  assert (!fixp->fx_pcrel == !reloc->howto->pc_relative);
+  return TRUE;
+}
 
-  reloc->addend = fixp->fx_offset;
 
-  switch (fixp->fx_r_type)
+void
+reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
+{
+  int i;
+  int uses = (rt->opcode_num_units) (rt->data, opcode);
+
+  for (i = 0; i < uses; i++)
     {
-    case BFD_RELOC_XTENSA_OP0:
-    case BFD_RELOC_XTENSA_OP1:
-    case BFD_RELOC_XTENSA_OP2:
-    case BFD_RELOC_XTENSA_ASM_EXPAND:
-    case BFD_RELOC_32: 
-    case BFD_RELOC_XTENSA_PLT: 
-    case BFD_RELOC_VTABLE_INHERIT:
-    case BFD_RELOC_VTABLE_ENTRY:
-      break;
+      xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
+      int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
+      /* Note that this allows resources to be oversubscribed.  That's
+	 essential to the way the optional scheduler works.
+	 resources_available reports when a resource is over-subscribed,
+	 so it's easy to tell.  */
+      rt->units[stage + cycle][unit]++;
+    }
+}
 
-    case BFD_RELOC_XTENSA_ASM_SIMPLIFY:
-      as_warn (_("emitting simplification relocation"));
-      break;
 
-    default:
-      as_warn (_("emitting unknown relocation"));
+void
+release_resources (resource_table *rt, xtensa_opcode opcode, int cycle)
+{
+  int i;
+  int uses = (rt->opcode_num_units) (rt->data, opcode);
+
+  for (i = 0; i < uses; i++)
+    {
+      xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i);
+      int stage = (rt->opcode_unit_stage) (rt->data, opcode, i);
+      assert (rt->units[stage + cycle][unit] > 0);
+      rt->units[stage + cycle][unit]--;
     }
+}
 
-  return reloc;
+
+/* Wrapper functions make parameterized resource reservation
+   more convenient.  */
+
+int
+opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx)
+{
+  xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
+  return use->unit;
+}
+
+
+int
+opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx)
+{
+  xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx);
+  return use->stage;
+}
+
+
+/* Note that this function does not check issue constraints, but
+   solely whether the hardware is available to execute the given
+   instructions together.  It also doesn't check if the tinsns
+   write the same state, or access the same tieports.  That is
+   checked by check_t1_t2_reads_and_writes.  */
+
+static bfd_boolean
+resources_conflict (vliw_insn *vinsn)
+{
+  int i;
+  static resource_table *rt = NULL;
+
+  /* This is the most common case by far.  Optimize it.  */
+  if (vinsn->num_slots == 1)
+    return FALSE;
+
+  if (rt == NULL)
+    {
+      xtensa_isa isa = xtensa_default_isa;
+      rt = new_resource_table
+	(isa, xtensa_isa_num_pipe_stages (isa),
+	 xtensa_isa_num_funcUnits (isa),
+	 (unit_num_copies_func) xtensa_funcUnit_num_copies,
+	 (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses,
+	 opcode_funcUnit_use_unit,
+	 opcode_funcUnit_use_stage);
+    }
+
+  clear_resource_table (rt);
+
+  for (i = 0; i < vinsn->num_slots; i++)
+    {
+      if (!resources_available (rt, vinsn->slots[i].opcode, 0))
+	return TRUE;
+      reserve_resources (rt, vinsn->slots[i].opcode, 0);
+    }
+
+  return FALSE;
 }
 
 
+/* finish_vinsn, emit_single_op and helper functions.  */
+
+static bfd_boolean find_vinsn_conflicts (vliw_insn *);
+static xtensa_format xg_find_narrowest_format (vliw_insn *);
+static void xg_assemble_vliw_tokens (vliw_insn *);
+
+
+/* We have reached the end of a bundle; emit into the frag.  */
+
+static void
+finish_vinsn (vliw_insn *vinsn)
+{
+  IStack slotstack;
+  int i;
+  char *file_name;
+  unsigned line;
+
+  if (find_vinsn_conflicts (vinsn))
+    {
+      xg_clear_vinsn (vinsn);
+      return;
+    }
+
+  /* First, find a format that works.  */
+  if (vinsn->format == XTENSA_UNDEFINED)
+    vinsn->format = xg_find_narrowest_format (vinsn);
+
+  if (vinsn->format == XTENSA_UNDEFINED)
+    {
+      as_where (&file_name, &line);
+      as_bad_where (file_name, line,
+		    _("couldn't find a valid instruction format"));
+      fprintf (stderr, _("    ops were: "));
+      for (i = 0; i < vinsn->num_slots; i++)
+	fprintf (stderr, _(" %s;"),
+		 xtensa_opcode_name (xtensa_default_isa,
+				     vinsn->slots[i].opcode));
+      fprintf (stderr, _("\n"));
+      xg_clear_vinsn (vinsn);
+      return;
+    }
+
+  if (vinsn->num_slots
+      != xtensa_format_num_slots (xtensa_default_isa, vinsn->format))
+    {
+      as_bad (_("format '%s' allows %d slots, but there are %d opcodes"),
+	      xtensa_format_name (xtensa_default_isa, vinsn->format),
+	      xtensa_format_num_slots (xtensa_default_isa, vinsn->format),
+	      vinsn->num_slots);
+      xg_clear_vinsn (vinsn);
+      return;
+    }
+
+  if (resources_conflict (vinsn))
+    {
+      as_where (&file_name, &line);
+      as_bad_where (file_name, line, _("illegal resource usage in bundle"));
+      fprintf (stderr, "    ops were: ");
+      for (i = 0; i < vinsn->num_slots; i++)
+	fprintf (stderr, " %s;",
+		 xtensa_opcode_name (xtensa_default_isa,
+				     vinsn->slots[i].opcode));
+      fprintf (stderr, "\n");
+      xg_clear_vinsn (vinsn);
+      return;
+    }
+
+  for (i = 0; i < vinsn->num_slots; i++)
+    {
+      if (vinsn->slots[i].opcode != XTENSA_UNDEFINED)
+	{
+	  symbolS *lit_sym = NULL;
+	  int j;
+	  bfd_boolean e = FALSE;
+	  bfd_boolean saved_density = density_supported;
+
+	  /* We don't want to narrow ops inside multi-slot bundles.  */
+	  if (vinsn->num_slots > 1)
+	    density_supported = FALSE;
+
+	  istack_init (&slotstack);
+	  if (vinsn->slots[i].opcode == xtensa_nop_opcode)
+	    {
+	      vinsn->slots[i].opcode =
+		xtensa_format_slot_nop_opcode (xtensa_default_isa,
+					       vinsn->format, i);
+	      vinsn->slots[i].ntok = 0;
+	    }
+
+	  if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i]))
+	    {
+	      e = TRUE;
+	      continue;
+	    }
+
+	  density_supported = saved_density;
+
+	  if (e)
+	    {
+	      xg_clear_vinsn (vinsn);
+	      return;
+	    }
+
+	  for (j = 0; j < slotstack.ninsn; j++)
+	    {
+	      TInsn *insn = &slotstack.insn[j];
+	      if (insn->insn_type == ITYPE_LITERAL)
+		{
+		  assert (lit_sym == NULL);
+		  lit_sym = xg_assemble_literal (insn);
+		}
+	      else
+		{
+		  assert (insn->insn_type == ITYPE_INSN);
+		  if (lit_sym)
+		    xg_resolve_literals (insn, lit_sym);
+		  if (j != slotstack.ninsn - 1)
+		    emit_single_op (insn);
+		}
+	    }
+
+	  if (vinsn->num_slots > 1)
+	    {
+	      if (opcode_fits_format_slot
+		  (slotstack.insn[slotstack.ninsn - 1].opcode,
+		   vinsn->format, i))
+		{
+		  vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1];
+		}
+	      else
+		{
+		  emit_single_op (&slotstack.insn[slotstack.ninsn - 1]);
+		  if (vinsn->format == XTENSA_UNDEFINED)
+		    vinsn->slots[i].opcode = xtensa_nop_opcode;
+		  else
+		    vinsn->slots[i].opcode
+		      = xtensa_format_slot_nop_opcode (xtensa_default_isa,
+						       vinsn->format, i);
+
+		  vinsn->slots[i].ntok = 0;
+		}
+	    }
+	  else
+	    {
+	      vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1];
+	      vinsn->format = XTENSA_UNDEFINED;
+	    }
+	}
+    }
+
+  /* Now check resource conflicts on the modified bundle.  */
+  if (resources_conflict (vinsn))
+    {
+      as_where (&file_name, &line);
+      as_bad_where (file_name, line, _("illegal resource usage in bundle"));
+      fprintf (stderr, "    ops were: ");
+      for (i = 0; i < vinsn->num_slots; i++)
+	fprintf (stderr, " %s;",
+		 xtensa_opcode_name (xtensa_default_isa,
+				     vinsn->slots[i].opcode));
+      fprintf (stderr, "\n");
+      xg_clear_vinsn (vinsn);
+      return;
+    }
+
+  /* First, find a format that works.  */
+  if (vinsn->format == XTENSA_UNDEFINED)
+      vinsn->format = xg_find_narrowest_format (vinsn);
+
+  xg_assemble_vliw_tokens (vinsn);
+
+  xg_clear_vinsn (vinsn);
+}
+
+
+/* Given an vliw instruction, what conflicts are there in register
+   usage and in writes to states and queues?
+
+   This function does two things:
+   1. Reports an error when a vinsn contains illegal combinations
+      of writes to registers states or queues.
+   2. Marks individual tinsns as not relaxable if the combination
+      contains antidependencies.
+
+   Job 2 handles things like swap semantics in instructions that need
+   to be relaxed.  For example,
+
+	addi a0, a1, 100000
+
+   normally would be relaxed to
+
+	l32r a0, some_label
+	add a0, a1, a0
+
+   _but_, if the above instruction is bundled with an a0 reader, e.g.,
+
+	{ addi a0, a1, 10000 ; add a2, a0, a4 ; }
+
+   then we can't relax it into
+
+	l32r a0, some_label
+	{ add a0, a1, a0 ; add a2, a0, a4 ; }
+
+   because the value of a0 is trashed before the second add can read it.  */
+
+static char check_t1_t2_reads_and_writes (TInsn *, TInsn *);
+
+static bfd_boolean
+find_vinsn_conflicts (vliw_insn *vinsn)
+{
+  int i, j;
+  int branches = 0;
+  xtensa_isa isa = xtensa_default_isa;
+
+  assert (!past_xtensa_end);
+
+  for (i = 0 ; i < vinsn->num_slots; i++)
+    {
+      TInsn *op1 = &vinsn->slots[i];
+      if (op1->is_specific_opcode)
+	op1->keep_wide = TRUE;
+      else
+	op1->keep_wide = FALSE;
+    }
+
+  for (i = 0 ; i < vinsn->num_slots; i++)
+    {
+      TInsn *op1 = &vinsn->slots[i];
+
+      if (xtensa_opcode_is_branch (isa, op1->opcode) == 1)
+	branches++;
+
+      for (j = 0; j < vinsn->num_slots; j++)
+	{
+	  if (i != j)
+	    {
+	      TInsn *op2 = &vinsn->slots[j];
+	      char conflict_type = check_t1_t2_reads_and_writes (op1, op2);
+	      switch (conflict_type)
+		{
+		case 'c':
+		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"),
+			  xtensa_opcode_name (isa, op1->opcode), i,
+			  xtensa_opcode_name (isa, op2->opcode), j);
+		  return TRUE;
+		case 'd':
+		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"),
+			  xtensa_opcode_name (isa, op1->opcode), i,
+			  xtensa_opcode_name (isa, op2->opcode), j);
+		  return TRUE;
+		case 'e':
+		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"),
+			  xtensa_opcode_name (isa, op1->opcode), i,
+			  xtensa_opcode_name (isa, op2->opcode), j);
+		  return TRUE;
+		case 'f':
+		  as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"),
+			  xtensa_opcode_name (isa, op1->opcode), i,
+			  xtensa_opcode_name (isa, op2->opcode), j);
+		  return TRUE;
+		default:
+		  /* Everything is OK.  */
+		  break;
+		}
+	      op2->is_specific_opcode = (op2->is_specific_opcode
+					 || conflict_type == 'a');
+	    }
+	}
+    }
+
+  if (branches > 1)
+    {
+      as_bad (_("multiple branches or jumps in the same bundle"));
+      return TRUE;
+    }
+
+  return FALSE;
+}
+
+
+/* Check how the state used by t1 and t2 relate.
+   Cases found are:
+
+   case A: t1 reads a register t2 writes (an antidependency within a bundle)
+   case B: no relationship between what is read and written (both could
+           read the same reg though)
+   case C: t1 writes a register t2 writes (a register conflict within a
+           bundle)
+   case D: t1 writes a state that t2 also writes
+   case E: t1 writes a tie queue that t2 also writes
+   case F: two volatile queue accesses
+*/
+
+static char
+check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_regfile t1_regfile, t2_regfile;
+  int t1_reg, t2_reg;
+  int t1_base_reg, t1_last_reg;
+  int t2_base_reg, t2_last_reg;
+  char t1_inout, t2_inout;
+  int i, j;
+  char conflict = 'b';
+  int t1_states;
+  int t2_states;
+  int t1_interfaces;
+  int t2_interfaces;
+  bfd_boolean t1_volatile = FALSE;
+  bfd_boolean t2_volatile = FALSE;
+
+  /* Check registers.  */
+  for (j = 0; j < t2->ntok; j++)
+    {
+      if (xtensa_operand_is_register (isa, t2->opcode, j) != 1)
+	continue;
+
+      t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j);
+      t2_base_reg = t2->tok[j].X_add_number;
+      t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j);
+
+      for (i = 0; i < t1->ntok; i++)
+	{
+	  if (xtensa_operand_is_register (isa, t1->opcode, i) != 1)
+	    continue;
+
+	  t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i);
+
+	  if (t1_regfile != t2_regfile)
+	    continue;
+
+	  t1_inout = xtensa_operand_inout (isa, t1->opcode, i);
+	  t2_inout = xtensa_operand_inout (isa, t2->opcode, j);
+
+	  if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0
+	      || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0)
+	    {
+	      if (t1_inout == 'm' || t1_inout == 'o'
+		  || t2_inout == 'm' || t2_inout == 'o')
+		{
+		  conflict = 'a';
+		  continue;
+		}
+	    }
+
+	  t1_base_reg = t1->tok[i].X_add_number;
+	  t1_last_reg = (t1_base_reg
+			 + xtensa_operand_num_regs (isa, t1->opcode, i));
+
+	  for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++)
+	    {
+	      for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++)
+		{
+		  if (t1_reg != t2_reg)
+		    continue;
+
+		  if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
+		    {
+		      conflict = 'a';
+		      continue;
+		    }
+
+		  if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
+		    {
+		      conflict = 'a';
+		      continue;
+		    }
+
+		  if (t1_inout != 'i' && t2_inout != 'i')
+		    return 'c';
+		}
+	    }
+	}
+    }
+
+  /* Check states.  */
+  t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode);
+  t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode);
+  for (j = 0; j < t2_states; j++)
+    {
+      xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j);
+      t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j);
+      for (i = 0; i < t1_states; i++)
+	{
+	  xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i);
+	  t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i);
+	  if (t1_so != t2_so)
+	    continue;
+
+	  if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o'))
+	    {
+	      conflict = 'a';
+	      continue;
+	    }
+
+	  if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o'))
+	    {
+	      conflict = 'a';
+	      continue;
+	    }
+
+	  if (t1_inout != 'i' && t2_inout != 'i')
+	    return 'd';
+	}
+    }
+
+  /* Check tieports.  */
+  t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode);
+  t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode);
+  for (j = 0; j < t2_interfaces; j++)
+    {
+      xtensa_interface t2_int
+	= xtensa_interfaceOperand_interface (isa, t2->opcode, j);
+      int t2_class = xtensa_interface_class_id (isa, t2_int);
+
+      t2_inout = xtensa_interface_inout (isa, t2_int);
+      if (xtensa_interface_has_side_effect (isa, t2_int) == 1)
+	t2_volatile = TRUE;
+
+      for (i = 0; i < t1_interfaces; i++)
+	{
+	  xtensa_interface t1_int
+	    = xtensa_interfaceOperand_interface (isa, t1->opcode, j);
+	  int t1_class = xtensa_interface_class_id (isa, t1_int);
+
+	  t1_inout = xtensa_interface_inout (isa, t1_int);
+	  if (xtensa_interface_has_side_effect (isa, t1_int) == 1)
+	    t1_volatile = TRUE;
+
+	  if (t1_volatile && t2_volatile && (t1_class == t2_class))
+	    return 'f';
+
+	  if (t1_int != t2_int)
+	    continue;
+
+	  if (t2_inout == 'i' && t1_inout == 'o')
+	    {
+	      conflict = 'a';
+	      continue;
+	    }
+
+	  if (t1_inout == 'i' && t2_inout == 'o')
+	    {
+	      conflict = 'a';
+	      continue;
+	    }
+
+	  if (t1_inout != 'i' && t2_inout != 'i')
+	    return 'e';
+	}
+    }
+
+  return conflict;
+}
+
+
+static xtensa_format
+xg_find_narrowest_format (vliw_insn *vinsn)
+{
+  /* Right now we assume that the ops within the vinsn are properly
+     ordered for the slots that the programmer wanted them in.  In
+     other words, we don't rearrange the ops in hopes of finding a
+     better format.  The scheduler handles that.  */
+
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_format format;
+  vliw_insn v_copy = *vinsn;
+  xtensa_opcode nop_opcode = xtensa_nop_opcode;
+
+  if (vinsn->num_slots == 1)
+    return xg_get_single_format (vinsn->slots[0].opcode);
+
+  for (format = 0; format < xtensa_isa_num_formats (isa); format++)
+    {
+      v_copy = *vinsn;
+      if (xtensa_format_num_slots (isa, format) == v_copy.num_slots)
+	{
+	  int slot;
+	  int fit = 0;
+	  for (slot = 0; slot < v_copy.num_slots; slot++)
+	    {
+	      if (v_copy.slots[slot].opcode == nop_opcode)
+		{
+		  v_copy.slots[slot].opcode =
+		    xtensa_format_slot_nop_opcode (isa, format, slot);
+		  v_copy.slots[slot].ntok = 0;
+		}
+
+	      if (opcode_fits_format_slot (v_copy.slots[slot].opcode,
+					   format, slot))
+		fit++;
+	      else if (v_copy.num_slots > 1)
+		{
+		  TInsn widened;
+		  /* Try the widened version.  */
+		  if (!v_copy.slots[slot].keep_wide
+		      && !v_copy.slots[slot].is_specific_opcode
+		      && xg_is_single_relaxable_insn (&v_copy.slots[slot],
+						      &widened, TRUE)
+		      && opcode_fits_format_slot (widened.opcode,
+						  format, slot))
+		    {
+		      v_copy.slots[slot] = widened;
+		      fit++;
+		    }
+		}
+	    }
+	  if (fit == v_copy.num_slots)
+	    {
+	      *vinsn = v_copy;
+	      xtensa_format_encode (isa, format, vinsn->insnbuf);
+	      vinsn->format = format;
+	      break;
+	    }
+	}
+    }
+
+  if (format == xtensa_isa_num_formats (isa))
+    return XTENSA_UNDEFINED;
+
+  return format;
+}
+
+
+/* Return the additional space needed in a frag
+   for possible relaxations of any ops in a VLIW insn.
+   Also fill out the relaxations that might be required of
+   each tinsn in the vinsn.  */
+
+static int
+relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag)
+{
+  bfd_boolean finish_frag = FALSE;
+  int extra_space = 0;
+  int slot;
+
+  for (slot = 0; slot < vinsn->num_slots; slot++)
+    {
+      TInsn *tinsn = &vinsn->slots[slot];
+      if (!tinsn_has_symbolic_operands (tinsn))
+	{
+	  /* A narrow instruction could be widened later to help
+	     alignment issues.  */
+	  if (xg_is_single_relaxable_insn (tinsn, 0, TRUE)
+	      && !tinsn->is_specific_opcode
+	      && vinsn->num_slots == 1)
+	    {
+	      /* Difference in bytes between narrow and wide insns...  */
+	      extra_space += 1;
+	      tinsn->subtype = RELAX_NARROW;
+	    }
+	}
+      else
+	{
+	  if (workaround_b_j_loop_end
+	      && tinsn->opcode == xtensa_jx_opcode
+	      && use_transform ())
+	    {
+	      /* Add 2 of these.  */
+	      extra_space += 3; /* for the nop size */
+	      tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END;
+	    }
+
+	  /* Need to assemble it with space for the relocation.  */
+	  if (xg_is_relaxable_insn (tinsn, 0)
+	      && !tinsn->is_specific_opcode)
+	    {
+	      int max_size = xg_get_max_insn_widen_size (tinsn->opcode);
+	      int max_literal_size =
+		xg_get_max_insn_widen_literal_size (tinsn->opcode);
+
+	      tinsn->literal_space = max_literal_size;
+
+	      tinsn->subtype = RELAX_IMMED;
+	      extra_space += max_size;
+	    }
+	  else
+	    {
+	      /* A fix record will be added for this instruction prior
+		 to relaxation, so make it end the frag.  */
+	      finish_frag = TRUE;
+	    }
+	}
+    }
+  *pfinish_frag = finish_frag;
+  return extra_space;
+}
+
+
+static void
+bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  int slot, chosen_slot;
+
+  vinsn->format = xg_get_single_format (tinsn->opcode);
+  assert (vinsn->format != XTENSA_UNDEFINED);
+  vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format);
+
+  chosen_slot = xg_get_single_slot (tinsn->opcode);
+  for (slot = 0; slot < vinsn->num_slots; slot++)
+    {
+      if (slot == chosen_slot)
+	vinsn->slots[slot] = *tinsn;
+      else
+	{
+	  vinsn->slots[slot].opcode =
+	    xtensa_format_slot_nop_opcode (isa, vinsn->format, slot);
+	  vinsn->slots[slot].ntok = 0;
+	  vinsn->slots[slot].insn_type = ITYPE_INSN;
+	}
+    }
+}
+
+
+static bfd_boolean
+emit_single_op (TInsn *orig_insn)
+{
+  int i;
+  IStack istack;		/* put instructions into here */
+  symbolS *lit_sym = NULL;
+  symbolS *label_sym = NULL;
+
+  istack_init (&istack);
+
+  /* Special-case for "movi aX, foo" which is guaranteed to need relaxing.
+     Because the scheduling and bundling characteristics of movi and
+     l32r or const16 are so different, we can do much better if we relax
+     it prior to scheduling and bundling, rather than after.  */
+  if ((orig_insn->opcode == xtensa_movi_opcode
+       || orig_insn->opcode == xtensa_movi_n_opcode)
+      && !cur_vinsn.inside_bundle
+      && (orig_insn->tok[1].X_op == O_symbol
+	  || orig_insn->tok[1].X_op == O_pltrel)
+      && !orig_insn->is_specific_opcode && use_transform ())
+    xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0);
+  else
+    if (xg_expand_assembly_insn (&istack, orig_insn))
+      return TRUE;
+
+  for (i = 0; i < istack.ninsn; i++)
+    {
+      TInsn *insn = &istack.insn[i];
+      switch (insn->insn_type)
+	{
+	case ITYPE_LITERAL:
+	  assert (lit_sym == NULL);
+	  lit_sym = xg_assemble_literal (insn);
+	  break;
+	case ITYPE_LABEL:
+	  {
+	    static int relaxed_sym_idx = 0;
+	    char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12);
+	    sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++);
+	    colon (label);
+	    assert (label_sym == NULL);
+	    label_sym = symbol_find_or_make (label);
+	    assert (label_sym);
+	    free (label);
+	  }
+	  break;
+	case ITYPE_INSN:
+	  {
+	    vliw_insn v;
+	    if (lit_sym)
+	      xg_resolve_literals (insn, lit_sym);
+	    if (label_sym)
+	      xg_resolve_labels (insn, label_sym);
+	    xg_init_vinsn (&v);
+	    bundle_tinsn (insn, &v);
+	    finish_vinsn (&v);
+	    xg_free_vinsn (&v);
+	  }
+	  break;
+	default:
+	  assert (0);
+	  break;
+	}
+    }
+  return FALSE;
+}
+
+
+static int
+total_frag_text_expansion (fragS *fragP)
+{
+  int slot;
+  int total_expansion = 0;
+
+  for (slot = 0; slot < MAX_SLOTS; slot++)
+    total_expansion += fragP->tc_frag_data.text_expansion[slot];
+
+  return total_expansion;
+}
+
+
+/* Emit a vliw instruction to the current fragment.  */
+
+static void
+xg_assemble_vliw_tokens (vliw_insn *vinsn)
+{
+  bfd_boolean finish_frag;
+  bfd_boolean is_jump = FALSE;
+  bfd_boolean is_branch = FALSE;
+  xtensa_isa isa = xtensa_default_isa;
+  int i;
+  int insn_size;
+  int extra_space;
+  char *f = NULL;
+  int slot;
+  unsigned current_line, best_linenum;
+  char *current_file;
+
+  best_linenum = UINT_MAX;
+
+  if (generating_literals)
+    {
+      static int reported = 0;
+      if (reported < 4)
+	as_bad_where (frag_now->fr_file, frag_now->fr_line,
+		      _("cannot assemble into a literal fragment"));
+      if (reported == 3)
+	as_bad (_("..."));
+      reported++;
+      return;
+    }
+
+  if (frag_now_fix () != 0
+      && (! frag_now->tc_frag_data.is_insn
+ 	  || (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+ 	  || !use_transform () != frag_now->tc_frag_data.is_no_transform
+ 	  || (directive_state[directive_longcalls]
+	      != frag_now->tc_frag_data.use_longcalls)
+ 	  || (directive_state[directive_absolute_literals]
+	      != frag_now->tc_frag_data.use_absolute_literals)))
+    {
+      frag_wane (frag_now);
+      frag_new (0);
+      xtensa_set_frag_assembly_state (frag_now);
+    }
+
+  if (workaround_a0_b_retw
+      && vinsn->num_slots == 1
+      && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0
+      && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1
+      && use_transform ())
+    {
+      has_a0_b_retw = TRUE;
+
+      /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW.
+	 After the first assembly pass we will check all of them and
+	 add a nop if needed.  */
+      frag_now->tc_frag_data.is_insn = TRUE;
+      frag_var (rs_machine_dependent, 4, 4,
+		RELAX_ADD_NOP_IF_A0_B_RETW,
+		frag_now->fr_symbol,
+		frag_now->fr_offset,
+		NULL);
+      xtensa_set_frag_assembly_state (frag_now);
+      frag_now->tc_frag_data.is_insn = TRUE;
+      frag_var (rs_machine_dependent, 4, 4,
+		RELAX_ADD_NOP_IF_A0_B_RETW,
+		frag_now->fr_symbol,
+		frag_now->fr_offset,
+		NULL);
+      xtensa_set_frag_assembly_state (frag_now);
+    }
+
+  for (i = 0; i < vinsn->num_slots; i++)
+    {
+      /* See if the instruction implies an aligned section.  */
+      if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1)
+	record_alignment (now_seg, 2);
+
+      /* Also determine the best line number for debug info.  */
+      best_linenum = vinsn->slots[i].linenum < best_linenum
+	? vinsn->slots[i].linenum : best_linenum;
+    }
+
+  /* Special cases for instructions that force an alignment... */
+  /* None of these opcodes are bundle-able.  */
+  if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1)
+    {
+      int max_fill;
+
+      /* Remember the symbol that marks the end of the loop in the frag
+	 that marks the start of the loop.  This way we can easily find
+	 the end of the loop at the beginning, without adding special code
+	 to mark the loop instructions themselves.  */
+      symbolS *target_sym = NULL;
+      if (vinsn->slots[0].tok[1].X_op == O_symbol)
+	target_sym = vinsn->slots[0].tok[1].X_add_symbol;
+
+      xtensa_set_frag_assembly_state (frag_now);
+      frag_now->tc_frag_data.is_insn = TRUE;
+
+      max_fill = get_text_align_max_fill_size
+	(get_text_align_power (xtensa_fetch_width),
+	 TRUE, frag_now->tc_frag_data.is_no_density);
+
+      if (use_transform ())
+	frag_var (rs_machine_dependent, max_fill, max_fill,
+		  RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
+      else
+	frag_var (rs_machine_dependent, 0, 0,
+		  RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
+
+      xtensa_move_labels (frag_now, 0, FALSE);
+    }
+
+  if (vinsn->slots[0].opcode == xtensa_entry_opcode
+      && !vinsn->slots[0].is_specific_opcode)
+    {
+      xtensa_mark_literal_pool_location ();
+      xtensa_move_labels (frag_now, 0, TRUE);
+      frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL);
+    }
+
+  if (vinsn->num_slots == 1)
+    {
+      if (workaround_a0_b_retw && use_transform ())
+	set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER,
+			     is_register_writer (&vinsn->slots[0], "a", 0));
+
+      set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND,
+			   is_bad_loopend_opcode (&vinsn->slots[0]));
+    }
+  else
+    set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE);
+
+  insn_size = xtensa_format_length (isa, vinsn->format);
+
+  extra_space = relaxation_requirements (vinsn, &finish_frag);
+
+  /* vinsn_to_insnbuf will produce the error.  */
+  if (vinsn->format != XTENSA_UNDEFINED)
+    {
+      f = frag_more (insn_size + extra_space);
+      xtensa_set_frag_assembly_state (frag_now);
+      frag_now->tc_frag_data.is_insn = TRUE;
+    }
+
+  vinsn_to_insnbuf (vinsn, f, frag_now, FALSE);
+  if (vinsn->format == XTENSA_UNDEFINED)
+    return;
+
+  xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0);
+
+  /* Temporarily set the logical line number to the one we want to appear
+     in the debug information.  */
+  as_where (&current_file, &current_line);
+  new_logical_line (current_file, best_linenum);
+  dwarf2_emit_insn (insn_size + extra_space);
+  new_logical_line (current_file, current_line);
+
+  for (slot = 0; slot < vinsn->num_slots; slot++)
+    {
+      TInsn *tinsn = &vinsn->slots[slot];
+      frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype;
+      frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol;
+      frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset;
+      frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag;
+      if (tinsn->literal_space != 0)
+	xg_assemble_literal_space (tinsn->literal_space, slot);
+
+      if (tinsn->subtype == RELAX_NARROW)
+	assert (vinsn->num_slots == 1);
+      if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1)
+	is_jump = TRUE;
+      if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1)
+	is_branch = TRUE;
+
+      if (tinsn->subtype || tinsn->symbol || tinsn->offset
+	  || tinsn->literal_frag || is_jump || is_branch)
+	finish_frag = TRUE;
+    }
+
+  if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+    frag_now->tc_frag_data.is_specific_opcode = TRUE;
+
+  if (finish_frag)
+    {
+      frag_variant (rs_machine_dependent,
+		    extra_space, extra_space, RELAX_SLOTS,
+		    frag_now->fr_symbol, frag_now->fr_offset, f);
+      xtensa_set_frag_assembly_state (frag_now);
+    }
+
+  /* Special cases for loops:
+     close_loop_end should be inserted AFTER short_loop.
+     Make sure that CLOSE loops are processed BEFORE short_loops
+     when converting them.  */
+
+  /* "short_loop": Add a NOP if the loop is < 4 bytes.  */
+  if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode)
+      && !vinsn->slots[0].is_specific_opcode)
+    {
+      if (workaround_short_loop && use_transform ())
+	{
+	  maybe_has_short_loop = TRUE;
+	  frag_now->tc_frag_data.is_insn = TRUE;
+	  frag_var (rs_machine_dependent, 4, 4,
+		    RELAX_ADD_NOP_IF_SHORT_LOOP,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	  frag_now->tc_frag_data.is_insn = TRUE;
+	  frag_var (rs_machine_dependent, 4, 4,
+		    RELAX_ADD_NOP_IF_SHORT_LOOP,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	}
+
+      /* "close_loop_end": Add up to 12 bytes of NOPs to keep a
+	 loop at least 12 bytes away from another loop's end.  */
+      if (workaround_close_loop_end && use_transform ())
+	{
+	  maybe_has_close_loop_end = TRUE;
+	  frag_now->tc_frag_data.is_insn = TRUE;
+	  frag_var (rs_machine_dependent, 12, 12,
+		    RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	}
+    }
+
+  if (use_transform ())
+    {
+      if (is_jump)
+	{
+	  assert (finish_frag);
+	  frag_var (rs_machine_dependent,
+		    UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
+		    RELAX_UNREACHABLE,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	  xtensa_set_frag_assembly_state (frag_now);
+	}
+      else if (is_branch && do_align_targets ())
+	{
+	  assert (finish_frag);
+	  frag_var (rs_machine_dependent,
+		    UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH,
+		    RELAX_MAYBE_UNREACHABLE,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	  xtensa_set_frag_assembly_state (frag_now);
+	  frag_var (rs_machine_dependent,
+		    0, 0,
+		    RELAX_MAYBE_DESIRE_ALIGN,
+		    frag_now->fr_symbol, frag_now->fr_offset, NULL);
+	  xtensa_set_frag_assembly_state (frag_now);
+	}
+    }
+
+  /* Now, if the original opcode was a call...  */
+  if (do_align_targets ()
+      && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1)
+    {
+      float freq = get_subseg_total_freq (now_seg, now_subseg);
+      frag_now->tc_frag_data.is_insn = TRUE;
+      frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN,
+		frag_now->fr_symbol, frag_now->fr_offset, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
+    }
+
+  if (vinsn_has_specific_opcodes (vinsn) && use_transform ())
+    {
+      frag_wane (frag_now);
+      frag_new (0);
+      xtensa_set_frag_assembly_state (frag_now);
+    }
+}
+
+
+/* xtensa_end and helper functions.  */
+
+static void xtensa_cleanup_align_frags (void);
+static void xtensa_fix_target_frags (void);
+static void xtensa_mark_narrow_branches (void);
+static void xtensa_mark_zcl_first_insns (void);
+static void xtensa_fix_a0_b_retw_frags (void);
+static void xtensa_fix_b_j_loop_end_frags (void);
+static void xtensa_fix_close_loop_end_frags (void);
+static void xtensa_fix_short_loop_frags (void);
+static void xtensa_sanity_check (void);
+
 void
-xtensa_end ()
+xtensa_end (void)
 {
   directive_balance ();
+  xtensa_flush_pending_output ();
+
+  past_xtensa_end = TRUE;
+
   xtensa_move_literals ();
 
   xtensa_reorder_segments ();
   xtensa_cleanup_align_frags ();
   xtensa_fix_target_frags ();
-  if (software_a0_b_retw_interlock && has_a0_b_retw)
+  if (workaround_a0_b_retw && has_a0_b_retw)
     xtensa_fix_a0_b_retw_frags ();
-  if (software_avoid_b_j_loop_end && maybe_has_b_j_loop_end)
+  if (workaround_b_j_loop_end)
     xtensa_fix_b_j_loop_end_frags ();
 
   /* "close_loop_end" should be processed BEFORE "short_loop".  */
-  if (software_avoid_close_loop_end && maybe_has_close_loop_end)
+  if (workaround_close_loop_end && maybe_has_close_loop_end)
     xtensa_fix_close_loop_end_frags ();
 
-  if (software_avoid_short_loop && maybe_has_short_loop)
+  if (workaround_short_loop && maybe_has_short_loop)
     xtensa_fix_short_loop_frags ();
+  if (align_targets)
+    xtensa_mark_narrow_branches ();
+  xtensa_mark_zcl_first_insns ();
 
   xtensa_sanity_check ();
 }
 
 
 static void
-xtensa_cleanup_align_frags ()
+xtensa_cleanup_align_frags (void)
 {
   frchainS *frchP;
 
   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
     {
       fragS *fragP;
-
       /* Walk over all of the fragments in a subsection.  */
       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
 	{
@@ -5417,16 +6968,28 @@ xtensa_cleanup_align_frags ()
 		       || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)))
 	      && fragP->fr_fix == 0)
 	    {
-	      fragS * next = fragP->fr_next;
+	      fragS *next = fragP->fr_next;
 
 	      while (next
-		     && next->fr_type == rs_machine_dependent 
-		     && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) 
+		     && next->fr_fix == 0
+		     && next->fr_type == rs_machine_dependent
+		     && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
 		{
 		  frag_wane (next);
 		  next = next->fr_next;
 		}
 	    }
+	  /* If we don't widen branch targets, then they
+	     will be easier to align.  */
+	  if (fragP->tc_frag_data.is_branch_target
+	      && fragP->fr_opcode == fragP->fr_literal
+	      && fragP->fr_type == rs_machine_dependent
+	      && fragP->fr_subtype == RELAX_SLOTS
+	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+	    frag_wane (fragP);
+	  if (fragP->fr_type == rs_machine_dependent
+	      && fragP->fr_subtype == RELAX_UNREACHABLE)
+	    fragP->tc_frag_data.is_unreachable = TRUE;
 	}
     }
 }
@@ -5435,12 +6998,10 @@ xtensa_cleanup_align_frags ()
 /* Re-process all of the fragments looking to convert all of the
    RELAX_DESIRE_ALIGN_IF_TARGET fragments.  If there is a branch
    target in the next fragment, convert this to RELAX_DESIRE_ALIGN.
-   If the next fragment starts with a loop target, AND the previous
-   fragment can be expanded to negate the branch, convert this to a
-   RELAX_LOOP_END.  Otherwise, convert to a .fill 0.  */
+   Otherwise, convert to a .fill 0.  */
 
 static void
-xtensa_fix_target_frags ()
+xtensa_fix_target_frags (void)
 {
   frchainS *frchP;
 
@@ -5448,7 +7009,6 @@ xtensa_fix_target_frags ()
      so we walk over subsections instead of sections.  */
   for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
     {
-      bfd_boolean prev_frag_can_negate_branch = FALSE;
       fragS *fragP;
 
       /* Walk over all of the fragments in a subsection.  */
@@ -5457,57 +7017,162 @@ xtensa_fix_target_frags ()
 	  if (fragP->fr_type == rs_machine_dependent
 	      && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET)
 	    {
-	      if (next_frag_is_loop_target (fragP))
-		{
-		  if (prev_frag_can_negate_branch)
-		    fragP->fr_subtype = RELAX_LOOP_END;
-		  else
-		    {
-		      if (!align_only_targets ||
-			  next_frag_is_branch_target (fragP))
-			fragP->fr_subtype = RELAX_DESIRE_ALIGN;
-		      else
-			frag_wane (fragP);
-		    }
-		}
-	      else if (!align_only_targets
-		       || next_frag_is_branch_target (fragP))
+	      if (next_frag_is_branch_target (fragP))
 		fragP->fr_subtype = RELAX_DESIRE_ALIGN;
 	      else
 		frag_wane (fragP);
 	    }
-	  if (fragP->fr_fix != 0)
-	    prev_frag_can_negate_branch = FALSE;
-	  if (frag_can_negate_branch (fragP))
-	    prev_frag_can_negate_branch = TRUE;
 	}
     }
 }
 
 
+static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *);
+
+static void
+xtensa_mark_narrow_branches (void)
+{
+  frchainS *frchP;
+
+  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
+    {
+      fragS *fragP;
+      /* Walk over all of the fragments in a subsection.  */
+      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	{
+	  if (fragP->fr_type == rs_machine_dependent
+	      && fragP->fr_subtype == RELAX_SLOTS
+	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED)
+	    {
+	      vliw_insn vinsn;
+
+	      vinsn_from_chars (&vinsn, fragP->fr_opcode);
+	      tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0);
+
+	      if (vinsn.num_slots == 1
+		  && xtensa_opcode_is_branch (xtensa_default_isa,
+					      vinsn.slots[0].opcode)
+		  && xg_get_single_size (vinsn.slots[0].opcode) == 2
+		  && is_narrow_branch_guaranteed_in_range (fragP,
+							   &vinsn.slots[0]))
+		{
+		  fragP->fr_subtype = RELAX_SLOTS;
+		  fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW;
+		  fragP->tc_frag_data.is_aligning_branch = 1;
+		}
+	    }
+	}
+    }
+}
+
+
+/* A branch is typically widened only when its target is out of
+   range.  However, we would like to widen them to align a subsequent
+   branch target when possible.
+
+   Because the branch relaxation code is so convoluted, the optimal solution
+   (combining the two cases) is difficult to get right in all circumstances.
+   We therefore go with an "almost as good" solution, where we only
+   use for alignment narrow branches that definitely will not expand to a
+   jump and a branch.  These functions find and mark these cases.  */
+
+/* The range in bytes of BNEZ.N and BEQZ.N.  The target operand is encoded
+   as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63.
+   We start counting beginning with the frag after the 2-byte branch, so the
+   maximum offset is (4 - 2) + 63 = 65.  */
+#define MAX_IMMED6 65
+
+static offsetT unrelaxed_frag_max_size (fragS *);
+
 static bfd_boolean
-frag_can_negate_branch (fragP)
-     fragS *fragP;
+is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn)
 {
-  if (fragP->fr_type == rs_machine_dependent
-      && fragP->fr_subtype == RELAX_IMMED)
+  const expressionS *expr = &tinsn->tok[1];
+  symbolS *symbolP = expr->X_add_symbol;
+  offsetT max_distance = expr->X_add_number;
+  fragS *target_frag;
+
+  if (expr->X_op != O_symbol)
+    return FALSE;
+
+  target_frag = symbol_get_frag (symbolP);
+
+  max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address);
+  if (is_branch_jmp_to_next (tinsn, fragP))
+    return FALSE;
+
+  /* The branch doesn't branch over it's own frag,
+     but over the subsequent ones.  */
+  fragP = fragP->fr_next;
+  while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6)
     {
-      TInsn t_insn;
-      tinsn_from_chars (&t_insn, fragP->fr_opcode);
-      if (is_negatable_branch (&t_insn))
-	return TRUE;
+      max_distance += unrelaxed_frag_max_size (fragP);
+      fragP = fragP->fr_next;
     }
+  if (max_distance <= MAX_IMMED6 && fragP == target_frag)
+    return TRUE;
   return FALSE;
 }
 
 
+static void
+xtensa_mark_zcl_first_insns (void)
+{
+  frchainS *frchP;
+
+  for (frchP = frchain_root; frchP; frchP = frchP->frch_next)
+    {
+      fragS *fragP;
+      /* Walk over all of the fragments in a subsection.  */
+      for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
+	{
+	  if (fragP->fr_type == rs_machine_dependent
+	      && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE
+		  || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))
+	    {
+	      /* Find the loop frag.  */
+	      fragS *targ_frag = next_non_empty_frag (fragP);
+	      /* Find the first insn frag.  */
+	      targ_frag = next_non_empty_frag (targ_frag);
+
+	      /* Of course, sometimes (mostly for toy test cases) a
+		 zero-cost loop instruction is the last in a section.  */
+	      if (targ_frag)
+		{
+		  targ_frag->tc_frag_data.is_first_loop_insn = TRUE;
+		  /* Do not widen a frag that is the first instruction of a
+		     zero-cost loop.  It makes that loop harder to align.  */
+		  if (targ_frag->fr_type == rs_machine_dependent
+		      && targ_frag->fr_subtype == RELAX_SLOTS
+		      && (targ_frag->tc_frag_data.slot_subtypes[0]
+			  == RELAX_NARROW))
+		    {
+		      if (targ_frag->tc_frag_data.is_aligning_branch)
+			targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
+		      else
+			{
+			  frag_wane (targ_frag);
+			  targ_frag->tc_frag_data.slot_subtypes[0] = 0;
+			}
+		    }
+		}
+	      if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)
+		frag_wane (fragP);
+	    }
+	}
+    }
+}
+
+
 /* Re-process all of the fragments looking to convert all of the
    RELAX_ADD_NOP_IF_A0_B_RETW.  If the next instruction is a
    conditional branch or a retw/retw.n, convert this frag to one that
    will generate a NOP.  In any case close it off with a .fill 0.  */
 
+static bfd_boolean next_instrs_are_b_retw (fragS *);
+
 static void
-xtensa_fix_a0_b_retw_frags ()
+xtensa_fix_a0_b_retw_frags (void)
 {
   frchainS *frchP;
 
@@ -5524,53 +7189,87 @@ xtensa_fix_a0_b_retw_frags ()
 	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW)
 	    {
 	      if (next_instrs_are_b_retw (fragP))
-		relax_frag_add_nop (fragP);
-	      else
-		frag_wane (fragP);
+		{
+		  if (fragP->tc_frag_data.is_no_transform)
+		    as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata"));
+		  else
+		    relax_frag_add_nop (fragP);
+		}
+	      frag_wane (fragP);
 	    }
 	}
     }
 }
 
 
-bfd_boolean
-next_instrs_are_b_retw (fragP)
-     fragS * fragP;
+static bfd_boolean
+next_instrs_are_b_retw (fragS *fragP)
 {
   xtensa_opcode opcode;
+  xtensa_format fmt;
   const fragS *next_fragP = next_non_empty_frag (fragP);
   static xtensa_insnbuf insnbuf = NULL;
+  static xtensa_insnbuf slotbuf = NULL;
   xtensa_isa isa = xtensa_default_isa;
   int offset = 0;
+  int slot;
+  bfd_boolean branch_seen = FALSE;
 
   if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (isa);
+    {
+      insnbuf = xtensa_insnbuf_alloc (isa);
+      slotbuf = xtensa_insnbuf_alloc (isa);
+    }
 
   if (next_fragP == NULL)
     return FALSE;
 
   /* Check for the conditional branch.  */
-  xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset]);
-  opcode = xtensa_decode_insn (isa, insnbuf);
+  xtensa_insnbuf_from_chars
+    (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+  if (fmt == XTENSA_UNDEFINED)
+    return FALSE;
+
+  for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
+    {
+      xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf);
+      opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
+
+      branch_seen = (branch_seen
+		     || xtensa_opcode_is_branch (isa, opcode) == 1);
+    }
 
-  if (!is_conditional_branch_opcode (opcode))
+  if (!branch_seen)
     return FALSE;
 
-  offset += xtensa_insn_length (isa, opcode);
+  offset += xtensa_format_length (isa, fmt);
   if (offset == next_fragP->fr_fix)
     {
       next_fragP = next_non_empty_frag (next_fragP);
       offset = 0;
     }
+
   if (next_fragP == NULL)
     return FALSE;
 
   /* Check for the retw/retw.n.  */
-  xtensa_insnbuf_from_chars (isa, insnbuf, &next_fragP->fr_literal[offset]);
-  opcode = xtensa_decode_insn (isa, insnbuf);
+  xtensa_insnbuf_from_chars
+    (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+
+  /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we
+     have no problems.  */
+  if (fmt == XTENSA_UNDEFINED
+      || xtensa_format_num_slots (isa, fmt) != 1)
+    return FALSE;
+
+  xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf);
+  opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf);
 
-  if (is_windowed_return_opcode (opcode))
+  if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode)
     return TRUE;
+
   return FALSE;
 }
 
@@ -5580,8 +7279,10 @@ next_instrs_are_b_retw (fragP)
    loop end label, convert this frag to one that will generate a NOP.
    In any case close it off with a .fill 0.  */
 
+static bfd_boolean next_instr_is_loop_end (fragS *);
+
 static void
-xtensa_fix_b_j_loop_end_frags ()
+xtensa_fix_b_j_loop_end_frags (void)
 {
   frchainS *frchP;
 
@@ -5598,18 +7299,21 @@ xtensa_fix_b_j_loop_end_frags ()
 	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END)
 	    {
 	      if (next_instr_is_loop_end (fragP))
-		relax_frag_add_nop (fragP);
-	      else
-		frag_wane (fragP);
+		{
+		  if (fragP->tc_frag_data.is_no_transform)
+		    as_bad (_("branching or jumping to a loop end may trigger hardware errata"));
+		  else
+		    relax_frag_add_nop (fragP);
+		}
+	      frag_wane (fragP);
 	    }
 	}
     }
 }
 
 
-bfd_boolean
-next_instr_is_loop_end (fragP)
-     fragS * fragP;
+static bfd_boolean
+next_instr_is_loop_end (fragS *fragP)
 {
   const fragS *next_fragP;
 
@@ -5638,8 +7342,11 @@ next_instr_is_loop_end (fragP)
    make it at least 12 bytes away.  In any case close it off with a
    .fill 0.  */
 
+static offsetT min_bytes_to_other_loop_end
+  (fragS *, fragS *, offsetT);
+
 static void
-xtensa_fix_close_loop_end_frags ()
+xtensa_fix_close_loop_end_frags (void)
 {
   frchainS *frchP;
 
@@ -5650,80 +7357,69 @@ xtensa_fix_close_loop_end_frags ()
       fragS *fragP;
 
       fragS *current_target = NULL;
-      offsetT current_offset = 0;
 
       /* Walk over all of the fragments in a subsection.  */
       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
 	{
 	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_IMMED)
-	    {
-	      /* Read it.  If the instruction is a loop, get the target.  */
-	      xtensa_opcode opcode = get_opcode_from_buf (fragP->fr_opcode);
-	      if (is_loop_opcode (opcode))
-		{
-		  TInsn t_insn;
-
-		  tinsn_from_chars (&t_insn, fragP->fr_opcode);
-		  tinsn_immed_from_frag (&t_insn, fragP);
-
-		  /* Get the current fragment target.  */
-		  if (fragP->fr_symbol)
-		    {
-		      current_target = symbol_get_frag (fragP->fr_symbol);
-		      current_offset = fragP->fr_offset;
-		    }
-		}
-	    }
+	      && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
+		  || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
+	      current_target = symbol_get_frag (fragP->fr_symbol);
 
 	  if (current_target
 	      && fragP->fr_type == rs_machine_dependent
 	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END)
 	    {
-	      size_t min_bytes;
-	      size_t bytes_added = 0;
+	      offsetT min_bytes;
+	      int bytes_added = 0;
 
 #define REQUIRED_LOOP_DIVIDING_BYTES 12
 	      /* Max out at 12.  */
 	      min_bytes = min_bytes_to_other_loop_end
-		(fragP->fr_next, current_target, current_offset,
-		 REQUIRED_LOOP_DIVIDING_BYTES);
+		(fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES);
 
 	      if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES)
 		{
-		  while (min_bytes + bytes_added
-			 < REQUIRED_LOOP_DIVIDING_BYTES)
+		  if (fragP->tc_frag_data.is_no_transform)
+		    as_bad (_("loop end too close to another loop end may trigger hardware errata"));
+		  else
 		    {
-		      int length = 3;
-
-		      if (fragP->fr_var < length)
-			as_warn (_("fr_var %lu < length %d; ignoring"),
-				 fragP->fr_var, length);
-		      else
+		      while (min_bytes + bytes_added
+			     < REQUIRED_LOOP_DIVIDING_BYTES)
 			{
-			  assemble_nop (length,
-					fragP->fr_literal + fragP->fr_fix);
-			  fragP->fr_fix += length;
-			  fragP->fr_var -= length;
+			  int length = 3;
+
+			  if (fragP->fr_var < length)
+			    as_fatal (_("fr_var %lu < length %d"),
+				      (long) fragP->fr_var, length);
+			  else
+			    {
+			      assemble_nop (length,
+					    fragP->fr_literal + fragP->fr_fix);
+			      fragP->fr_fix += length;
+			      fragP->fr_var -= length;
+			    }
+			  bytes_added += length;
 			}
-		      bytes_added += length;
 		    }
 		}
 	      frag_wane (fragP);
 	    }
+	  assert (fragP->fr_type != rs_machine_dependent
+		  || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END);
 	}
     }
 }
 
 
-size_t
-min_bytes_to_other_loop_end (fragP, current_target, current_offset, max_size)
-     fragS *fragP;
-     fragS *current_target;
-     offsetT current_offset;
-     size_t max_size;
+static offsetT unrelaxed_frag_min_size (fragS *);
+
+static offsetT
+min_bytes_to_other_loop_end (fragS *fragP,
+			     fragS *current_target,
+			     offsetT max_size)
 {
-  size_t offset = 0;
+  offsetT offset = 0;
   fragS *current_fragP;
 
   for (current_fragP = fragP;
@@ -5732,24 +7428,23 @@ min_bytes_to_other_loop_end (fragP, current_target, current_offset, max_size)
     {
       if (current_fragP->tc_frag_data.is_loop_target
 	  && current_fragP != current_target)
-	return offset + current_offset;
+	return offset;
 
       offset += unrelaxed_frag_min_size (current_fragP);
 
-      if (offset + current_offset >= max_size)
+      if (offset >= max_size)
 	return max_size;
     }
   return max_size;
 }
 
 
-size_t
-unrelaxed_frag_min_size (fragP)
-     fragS * fragP;
+static offsetT
+unrelaxed_frag_min_size (fragS *fragP)
 {
-  size_t size = fragP->fr_fix;
+  offsetT size = fragP->fr_fix;
 
-  /* add fill size */
+  /* Add fill size.  */
   if (fragP->fr_type == rs_fill)
     size += fragP->fr_offset;
 
@@ -5757,6 +7452,43 @@ unrelaxed_frag_min_size (fragP)
 }
 
 
+static offsetT
+unrelaxed_frag_max_size (fragS *fragP)
+{
+  offsetT size = fragP->fr_fix;
+  switch (fragP->fr_type)
+    {
+    case 0:
+      /* Empty frags created by the obstack allocation scheme
+	 end up with type 0.  */
+      break;
+    case rs_fill:
+    case rs_org:
+    case rs_space:
+      size += fragP->fr_offset;
+      break;
+    case rs_align:
+    case rs_align_code:
+    case rs_align_test:
+    case rs_leb128:
+    case rs_cfa:
+    case rs_dwarf2dbg:
+      /* No further adjustments needed.  */
+      break;
+    case rs_machine_dependent:
+      if (fragP->fr_subtype != RELAX_DESIRE_ALIGN)
+	size += fragP->fr_var;
+      break;
+    default:
+      /* We had darn well better know how big it is.  */
+      assert (0);
+      break;
+    }
+
+  return size;
+}
+
+
 /* Re-process all of the fragments looking to convert all
    of the RELAX_ADD_NOP_IF_SHORT_LOOP.  If:
 
@@ -5766,15 +7498,18 @@ unrelaxed_frag_min_size (fragP)
      2) loop has a jump or branch in it
 
    or B)
-     1) software_avoid_all_short_loops is true
+     1) workaround_all_short_loops is TRUE
      2) The generating loop was a  'loopgtz' or 'loopnez'
      3) the instruction size count to the loop end label is too short
         (<= 2 instructions)
    then convert this frag (and maybe the next one) to generate a NOP.
    In any case close it off with a .fill 0.  */
 
+static int count_insns_to_loop_end (fragS *, bfd_boolean, int);
+static bfd_boolean branch_before_loop_end (fragS *);
+
 static void
-xtensa_fix_short_loop_frags ()
+xtensa_fix_short_loop_frags (void)
 {
   frchainS *frchP;
 
@@ -5784,62 +7519,54 @@ xtensa_fix_short_loop_frags ()
     {
       fragS *fragP;
       fragS *current_target = NULL;
-      offsetT current_offset = 0;
       xtensa_opcode current_opcode = XTENSA_UNDEFINED;
 
       /* Walk over all of the fragments in a subsection.  */
       for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next)
 	{
-	  /* check on the current loop */
 	  if (fragP->fr_type == rs_machine_dependent
-	      && fragP->fr_subtype == RELAX_IMMED)
+	      && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
+		  || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)))
 	    {
-	      /* Read it.  If the instruction is a loop, get the target.  */
-	      xtensa_opcode opcode = get_opcode_from_buf (fragP->fr_opcode);
-	      if (is_loop_opcode (opcode))
-		{
-		  TInsn t_insn;
-
-		  tinsn_from_chars (&t_insn, fragP->fr_opcode);
-		  tinsn_immed_from_frag (&t_insn, fragP);
-
-		  /* Get the current fragment target.  */
-		  if (fragP->fr_symbol)
-		    {
-		      current_target = symbol_get_frag (fragP->fr_symbol);
-		      current_offset = fragP->fr_offset;
-		      current_opcode = opcode;
-		    }
-		}
+	      TInsn t_insn;
+	      fragS *loop_frag = next_non_empty_frag (fragP);
+	      tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0);
+	      current_target = symbol_get_frag (fragP->fr_symbol);
+	      current_opcode = t_insn.opcode;
+	      assert (xtensa_opcode_is_loop (xtensa_default_isa,
+					     current_opcode));
 	    }
 
 	  if (fragP->fr_type == rs_machine_dependent
 	      && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP)
 	    {
-	      size_t insn_count =
-		count_insns_to_loop_end (fragP->fr_next, TRUE, 3);
-	      if (insn_count < 3
+	      if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3
 		  && (branch_before_loop_end (fragP->fr_next)
-		      || (software_avoid_all_short_loops
+		      || (workaround_all_short_loops
 			  && current_opcode != XTENSA_UNDEFINED
-			  && !is_the_loop_opcode (current_opcode))))
-		relax_frag_add_nop (fragP);
-	      else
-		frag_wane (fragP);
+			  && current_opcode != xtensa_loop_opcode)))
+		{
+		  if (fragP->tc_frag_data.is_no_transform)
+		    as_bad (_("loop containing less than three instructions may trigger hardware errata"));
+		  else
+		    relax_frag_add_nop (fragP);
+		}
+	      frag_wane (fragP);
 	    }
 	}
     }
 }
 
 
-size_t
-count_insns_to_loop_end (base_fragP, count_relax_add, max_count)
-     fragS *base_fragP;
-     bfd_boolean count_relax_add;
-     size_t max_count;
+static int unrelaxed_frag_min_insn_count (fragS *);
+
+static int
+count_insns_to_loop_end (fragS *base_fragP,
+			 bfd_boolean count_relax_add,
+			 int max_count)
 {
   fragS *fragP = NULL;
-  size_t insn_count = 0;
+  int insn_count = 0;
 
   fragP = base_fragP;
 
@@ -5867,26 +7594,35 @@ count_insns_to_loop_end (base_fragP, count_relax_add, max_count)
 }
 
 
-size_t
-unrelaxed_frag_min_insn_count (fragP)
-     fragS *fragP;
+static int
+unrelaxed_frag_min_insn_count (fragS *fragP)
 {
-  size_t insn_count = 0;
+  xtensa_isa isa = xtensa_default_isa;
+  static xtensa_insnbuf insnbuf = NULL;
+  int insn_count = 0;
   int offset = 0;
 
   if (!fragP->tc_frag_data.is_insn)
     return insn_count;
 
+  if (!insnbuf)
+    insnbuf = xtensa_insnbuf_alloc (isa);
+
   /* Decode the fixed instructions.  */
   while (offset < fragP->fr_fix)
     {
-      xtensa_opcode opcode = get_opcode_from_buf (fragP->fr_literal + offset);
-      if (opcode == XTENSA_UNDEFINED)
+      xtensa_format fmt;
+
+      xtensa_insnbuf_from_chars
+	(isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
+      fmt = xtensa_format_decode (isa, insnbuf);
+
+      if (fmt == XTENSA_UNDEFINED)
 	{
 	  as_fatal (_("undecodable instruction in instruction frag"));
 	  return insn_count;
 	}
-      offset += xtensa_insn_length (xtensa_default_isa, opcode);
+      offset += xtensa_format_length (isa, fmt);
       insn_count++;
     }
 
@@ -5894,9 +7630,10 @@ unrelaxed_frag_min_insn_count (fragP)
 }
 
 
-bfd_boolean
-branch_before_loop_end (base_fragP)
-     fragS *base_fragP;
+static bfd_boolean unrelaxed_frag_has_b_j (fragS *);
+
+static bfd_boolean
+branch_before_loop_end (fragS *base_fragP)
 {
   fragS *fragP;
 
@@ -5911,28 +7648,40 @@ branch_before_loop_end (base_fragP)
 }
 
 
-bfd_boolean
-unrelaxed_frag_has_b_j (fragP)
-     fragS *fragP;
+static bfd_boolean
+unrelaxed_frag_has_b_j (fragS *fragP)
 {
-  size_t insn_count = 0;
+  static xtensa_insnbuf insnbuf = NULL;
+  xtensa_isa isa = xtensa_default_isa;
   int offset = 0;
 
   if (!fragP->tc_frag_data.is_insn)
     return FALSE;
 
+  if (!insnbuf)
+    insnbuf = xtensa_insnbuf_alloc (isa);
+
   /* Decode the fixed instructions.  */
   while (offset < fragP->fr_fix)
     {
-      xtensa_opcode opcode = get_opcode_from_buf (fragP->fr_literal + offset);
-      if (opcode == XTENSA_UNDEFINED)
+      xtensa_format fmt;
+      int slot;
+
+      xtensa_insnbuf_from_chars
+	(isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0);
+      fmt = xtensa_format_decode (isa, insnbuf);
+      if (fmt == XTENSA_UNDEFINED)
+	return FALSE;
+
+      for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
 	{
-	  as_fatal (_("undecodable instruction in instruction frag"));
-	  return insn_count;
+	  xtensa_opcode opcode =
+	    get_opcode_from_buf (fragP->fr_literal + offset, slot);
+	  if (xtensa_opcode_is_branch (isa, opcode) == 1
+	      || xtensa_opcode_is_jump (isa, opcode) == 1)
+	    return TRUE;
 	}
-      if (is_branch_or_jump_opcode (opcode))
-	return TRUE;
-      offset += xtensa_insn_length (xtensa_default_isa, opcode);
+      offset += xtensa_format_length (isa, fmt);
     }
   return FALSE;
 }
@@ -5940,11 +7689,14 @@ unrelaxed_frag_has_b_j (fragP)
 
 /* Checks to be made after initial assembly but before relaxation.  */
 
+static bfd_boolean is_empty_loop (const TInsn *, fragS *);
+static bfd_boolean is_local_forward_loop (const TInsn *, fragS *);
+
 static void
-xtensa_sanity_check ()
+xtensa_sanity_check (void)
 {
   char *file_name;
-  int line;
+  unsigned line;
 
   frchainS *frchP;
 
@@ -5967,10 +7719,11 @@ xtensa_sanity_check ()
 		{
 		  if (!insnbuf)
 		    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-		  tinsn_from_chars (&t_insn, fragP->fr_opcode);
-		  tinsn_immed_from_frag (&t_insn, fragP);
+		  tinsn_from_chars (&t_insn, fragP->fr_opcode, 0);
+		  tinsn_immed_from_frag (&t_insn, fragP, 0);
 
-		  if (is_loop_opcode (t_insn.opcode))
+		  if (xtensa_opcode_is_loop (xtensa_default_isa,
+					     t_insn.opcode) == 1)
 		    {
 		      if (is_empty_loop (&t_insn, fragP))
 			{
@@ -5994,12 +7747,10 @@ xtensa_sanity_check ()
 
 #define LOOP_IMMED_OPN 1
 
-/* Return true if the loop target is the next non-zero fragment.  */
+/* Return TRUE if the loop target is the next non-zero fragment.  */
 
-bfd_boolean
-is_empty_loop (insn, fragP)
-     const TInsn *insn;
-     fragS *fragP;
+static bfd_boolean
+is_empty_loop (const TInsn *insn, fragS *fragP)
 {
   const expressionS *expr;
   symbolS *symbolP;
@@ -6008,7 +7759,7 @@ is_empty_loop (insn, fragP)
   if (insn->insn_type != ITYPE_INSN)
     return FALSE;
 
-  if (!is_loop_opcode (insn->opcode))
+  if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1)
     return FALSE;
 
   if (insn->ntok <= LOOP_IMMED_OPN)
@@ -6031,6 +7782,7 @@ is_empty_loop (insn, fragP)
 
   /* Walk through the zero-size fragments from this one.  If we find
      the target fragment, then this is a zero-size loop.  */
+
   for (next_fragP = fragP->fr_next;
        next_fragP != NULL;
        next_fragP = next_fragP->fr_next)
@@ -6044,10 +7796,8 @@ is_empty_loop (insn, fragP)
 }
 
 
-bfd_boolean
-is_local_forward_loop (insn, fragP)
-     const TInsn *insn;
-     fragS *fragP;
+static bfd_boolean
+is_local_forward_loop (const TInsn *insn, fragS *fragP)
 {
   const expressionS *expr;
   symbolS *symbolP;
@@ -6056,7 +7806,7 @@ is_local_forward_loop (insn, fragP)
   if (insn->insn_type != ITYPE_INSN)
     return FALSE;
 
-  if (!is_loop_opcode (insn->opcode))
+  if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) == 0)
     return FALSE;
 
   if (insn->ntok <= LOOP_IMMED_OPN)
@@ -6076,11 +7826,14 @@ is_local_forward_loop (insn, fragP)
 
   /* Walk through fragments until we find the target.
      If we do not find the target, then this is an invalid loop.  */
+
   for (next_fragP = fragP->fr_next;
        next_fragP != NULL;
        next_fragP = next_fragP->fr_next)
-    if (next_fragP == symbol_get_frag (symbolP))
-      return TRUE;
+    {
+      if (next_fragP == symbol_get_frag (symbolP))
+	return TRUE;
+    }
 
   return FALSE;
 }
@@ -6088,26 +7841,20 @@ is_local_forward_loop (insn, fragP)
 
 /* Alignment Functions.  */
 
-size_t
-get_text_align_power (target_size)
-     int target_size;
+static int
+get_text_align_power (unsigned target_size)
 {
-  size_t i = 0;
-  for (i = 0; i < sizeof (size_t); i++)
-    {
-      if (target_size <= (1 << i))
-	return i;
-    }
-  as_fatal (_("get_text_align_power: argument too large"));
-  return 0;
+  if (target_size <= 4)
+    return 2;
+  assert (target_size == 8);
+  return 3;
 }
 
 
-addressT
-get_text_align_max_fill_size (align_pow, use_nops, use_no_density)
-     int align_pow;
-     bfd_boolean use_nops;
-     bfd_boolean use_no_density;
+static int
+get_text_align_max_fill_size (int align_pow,
+			      bfd_boolean use_nops,
+			      bfd_boolean use_no_density)
 {
   if (!use_nops)
     return (1 << align_pow);
@@ -6118,105 +7865,86 @@ get_text_align_max_fill_size (align_pow, use_nops, use_no_density)
 }
 
 
-/* get_text_align_fill_size ()
-  
-   Desired alignments:
-      give the address
-      target_size = size of next instruction
-      align_pow = get_text_align_power (target_size).
-      use_nops = 0
-      use_no_density = 0;
-   Loop alignments:
-      address = current address + loop instruction size;
-      target_size = 3 (for 2 or 3 byte target)
-                  = 8 (for 8 byte target)
-      align_pow = get_text_align_power (target_size);
-      use_nops = 1
-      use_no_density = set appropriately
-   Text alignments:
-      address = current address + loop instruction size;
-      target_size = 0
-      align_pow = get_text_align_power (target_size);
-      use_nops = 0
-      use_no_density = 0.  */
-
-addressT
-get_text_align_fill_size (address, align_pow, target_size,
-			  use_nops, use_no_density)
-     addressT address;
-     int align_pow;
-     int target_size;
-     bfd_boolean use_nops;
-     bfd_boolean use_no_density;
-{
-  /* Input arguments:
-
-     align_pow: log2 (required alignment).
-
-     target_size: alignment must allow the new_address and
-     new_address+target_size-1.
-
-     use_nops: if true, then we can only use 2 or 3 byte nops.
-
-     use_no_density: if use_nops and use_no_density, we can only use
-     3-byte nops.
-
-     Usually, for non-zero target_size, the align_pow is the power of 2
-     that is greater than or equal to the target_size.  This handles the
-     2-byte, 3-byte and 8-byte instructions.  */
-
-  size_t alignment = (1 << align_pow);
+/* Calculate the minimum bytes of fill needed at "address" to align a
+   target instruction of size "target_size" so that it does not cross a
+   power-of-two boundary specified by "align_pow".  If "use_nops" is FALSE,
+   the fill can be an arbitrary number of bytes.  Otherwise, the space must
+   be filled by NOP instructions.  */
+
+static int
+get_text_align_fill_size (addressT address,
+			  int align_pow,
+			  int target_size,
+			  bfd_boolean use_nops,
+			  bfd_boolean use_no_density)
+{
+  addressT alignment, fill, fill_limit, fill_step;
+  bfd_boolean skip_one = FALSE;
+
+  alignment = (1 << align_pow);
+  assert (target_size > 0 && alignment >= (addressT) target_size);
+
   if (!use_nops)
     {
-      /* This is the easy case.  */
-      size_t mod;
-      mod = address % alignment;
-      if (mod != 0)
-	mod = alignment - mod;
-      assert ((address + mod) % alignment == 0);
-      return mod;
+      fill_limit = alignment;
+      fill_step = 1;
     }
-
-  /* This is the slightly harder case.  */
-  assert ((int) alignment >= target_size);
-  assert (target_size > 0);
-  if (!use_no_density)
+  else if (!use_no_density)
     {
-      size_t i;
-      for (i = 0; i < alignment * 2; i++)
-	{
-	  if (i == 1)
-	    continue;
-	  if ((address + i) >> align_pow ==
-	      (address + i + target_size - 1) >> align_pow)
-	    return i;
-	}
+      /* Combine 2- and 3-byte NOPs to fill anything larger than one.  */
+      fill_limit = alignment * 2;
+      fill_step = 1;
+      skip_one = TRUE;
     }
   else
     {
-      size_t i;
+      /* Fill with 3-byte NOPs -- can only fill multiples of 3.  */
+      fill_limit = alignment * 3;
+      fill_step = 3;
+    }
 
-      /* Can only fill multiples of 3.  */
-      for (i = 0; i <= alignment * 3; i += 3)
-	{
-	  if ((address + i) >> align_pow ==
-	      (address + i + target_size - 1) >> align_pow)
-	    return i;
-	}
+  /* Try all fill sizes until finding one that works.  */
+  for (fill = 0; fill < fill_limit; fill += fill_step)
+    {
+      if (skip_one && fill == 1)
+	continue;
+      if ((address + fill) >> align_pow
+	  == (address + fill + target_size - 1) >> align_pow)
+	return fill;
     }
   assert (0);
   return 0;
 }
 
 
+static int
+branch_align_power (segT sec)
+{
+  /* If the Xtensa processor has a fetch width of 8 bytes, and the section
+     is aligned to at least an 8-byte boundary, then a branch target need
+     only fit within an 8-byte aligned block of memory to avoid a stall.
+     Otherwise, try to fit branch targets within 4-byte aligned blocks
+     (which may be insufficient, e.g., if the section has no alignment, but
+     it's good enough).  */
+  if (xtensa_fetch_width == 8)
+    {
+      if (get_recorded_alignment (sec) >= 3)
+	return 3;
+    }
+  else
+    assert (xtensa_fetch_width == 4);
+
+  return 2;
+}
+
+
 /* This will assert if it is not possible.  */
 
-size_t
-get_text_align_nop_count (fill_size, use_no_density)
-     size_t fill_size;
-     bfd_boolean use_no_density;
+static int
+get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density)
 {
-  size_t count = 0;
+  int count = 0;
+
   if (use_no_density)
     {
       assert (fill_size % 3 == 0);
@@ -6227,7 +7955,7 @@ get_text_align_nop_count (fill_size, use_no_density)
 
   while (fill_size > 1)
     {
-      size_t insn_size = 3;
+      int insn_size = 3;
       if (fill_size == 2 || fill_size == 4)
 	insn_size = 2;
       fill_size -= insn_size;
@@ -6238,22 +7966,21 @@ get_text_align_nop_count (fill_size, use_no_density)
 }
 
 
-size_t
-get_text_align_nth_nop_size (fill_size, n, use_no_density)
-     size_t fill_size;
-     size_t n;
-     bfd_boolean use_no_density;
+static int
+get_text_align_nth_nop_size (offsetT fill_size,
+			     int n,
+			     bfd_boolean use_no_density)
 {
-  size_t count = 0;
-
-  assert (get_text_align_nop_count (fill_size, use_no_density) > n);
+  int count = 0;
 
   if (use_no_density)
     return 3;
 
+  assert (fill_size != 1);	/* Bad argument.  */
+
   while (fill_size > 1)
     {
-      size_t insn_size = 3;
+      int insn_size = 3;
       if (fill_size == 2 || fill_size == 4)
 	insn_size = 2;
       fill_size -= insn_size;
@@ -6270,234 +7997,173 @@ get_text_align_nth_nop_size (fill_size, n, use_no_density)
    for it to begin at if we are using NOPs to align it.  */
 
 static addressT
-get_noop_aligned_address (fragP, address)
-     fragS *fragP;
-     addressT address;
+get_noop_aligned_address (fragS *fragP, addressT address)
 {
-  static xtensa_insnbuf insnbuf = NULL;
-  size_t fill_size = 0;
-
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-
-  switch (fragP->fr_type)
-    {
-    case rs_machine_dependent:
-      if (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
-	{
-	  /* The rule is: get next fragment's FIRST instruction.  Find
-	     the smallest number of bytes that need to be added to
-	     ensure that the next fragment's FIRST instruction will fit
-	     in a single word.
-
-	     E.G.,   2 bytes : 0, 1, 2 mod 4 
-		     3 bytes: 0, 1 mod 4 
+  /* The rule is: get next fragment's FIRST instruction.  Find
+     the smallest number of bytes that need to be added to
+     ensure that the next fragment's FIRST instruction will fit
+     in a single word.
 
-	     If the FIRST instruction MIGHT be relaxed, 
-	     assume that it will become a 3 byte instruction.  */
+     E.G.,   2 bytes : 0, 1, 2 mod 4
+	     3 bytes: 0, 1 mod 4
 
-	  int target_insn_size;
-	  xtensa_opcode opcode = next_frag_opcode (fragP);
-	  addressT pre_opcode_bytes;
+     If the FIRST instruction MIGHT be relaxed,
+     assume that it will become a 3-byte instruction.
 
-	  if (opcode == XTENSA_UNDEFINED)
-	    {
-	      as_bad_where (fragP->fr_file, fragP->fr_line,
-			    _("invalid opcode for RELAX_ALIGN_NEXT_OPCODE"));
-	      as_fatal (_("cannot continue"));
-	    }
+     Note again here that LOOP instructions are not bundleable,
+     and this relaxation only applies to LOOP opcodes.  */
 
-	  target_insn_size = xtensa_insn_length (xtensa_default_isa, opcode);
+  int fill_size = 0;
+  int first_insn_size;
+  int loop_insn_size;
+  addressT pre_opcode_bytes;
+  int align_power;
+  fragS *first_insn;
+  xtensa_opcode opcode;
+  bfd_boolean is_loop;
 
-	  pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
+  assert (fragP->fr_type == rs_machine_dependent);
+  assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE);
 
-	  if (is_loop_opcode (opcode))
-	    {
-	      /* next_fragP should be the loop.  */
-	      const fragS *next_fragP = next_non_empty_frag (fragP);
-	      xtensa_opcode next_opcode = next_frag_opcode (next_fragP);
-	      size_t alignment;
+  /* Find the loop frag.  */
+  first_insn = next_non_empty_frag (fragP);
+  /* Now find the first insn frag.  */
+  first_insn = next_non_empty_frag (first_insn);
 
-	      pre_opcode_bytes += target_insn_size;
+  is_loop = next_frag_opcode_is_loop (fragP, &opcode);
+  assert (is_loop);
+  loop_insn_size = xg_get_single_size (opcode);
 
-	      /* For loops, the alignment depends on the size of the
-		 instruction following the loop, not the loop instruction.  */
-	      if (next_opcode == XTENSA_UNDEFINED)
-		target_insn_size = 3;
-	      else
-		{
-		  target_insn_size =
-		    xtensa_insn_length (xtensa_default_isa, next_opcode);
+  pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP);
+  pre_opcode_bytes += loop_insn_size;
 
-		  if (target_insn_size == 2)
-		    target_insn_size = 3;	/* ISA specifies this.  */
-		}
+  /* For loops, the alignment depends on the size of the
+     instruction following the loop, not the LOOP instruction.  */
 
-	      /* If it was 8, then we'll need a larger alignment
-	         for the section.  */
-	      alignment = get_text_align_power (target_insn_size);
+  if (first_insn == NULL)
+    first_insn_size = xtensa_fetch_width;
+  else
+    first_insn_size = get_loop_align_size (frag_format_size (first_insn));
 
-	      /* Is Now_seg valid */
-	      record_alignment (now_seg, alignment);
-	    }
-	  else
-	    as_fatal (_("expected loop opcode in relax align next target"));
+  /* If it was 8, then we'll need a larger alignment for the section.  */
+  align_power = get_text_align_power (first_insn_size);
+  record_alignment (now_seg, align_power);
 
-	  fill_size = get_text_align_fill_size
-	    (address + pre_opcode_bytes,
-	     get_text_align_power (target_insn_size),
-	     target_insn_size, TRUE, fragP->tc_frag_data.is_no_density);
-	}
-      break;
-#if 0
-    case rs_align:
-    case rs_align_code:
-      fill_size = get_text_align_fill_size
-	(address, fragP->fr_offset, 1, TRUE,
-	 fragP->tc_frag_data.is_no_density);
-      break;
-#endif
-    default:
-      as_fatal (_("expected align_code or RELAX_ALIGN_NEXT_OPCODE"));
-    }
+  fill_size = get_text_align_fill_size
+    (address + pre_opcode_bytes, align_power, first_insn_size, TRUE,
+     fragP->tc_frag_data.is_no_density);
 
   return address + fill_size;
 }
 
 
-/* 3 mechanisms for relaxing an alignment: 
-   
-   Align to a power of 2. 
-   Align so the next fragment's instruction does not cross a word boundary. 
-   Align the current instruction so that if the next instruction 
-       were 3 bytes, it would not cross a word boundary. 
-   
+/* 3 mechanisms for relaxing an alignment:
+
+   Align to a power of 2.
+   Align so the next fragment's instruction does not cross a word boundary.
+   Align the current instruction so that if the next instruction
+       were 3 bytes, it would not cross a word boundary.
+
    We can align with:
 
-   zeros    - This is easy; always insert zeros. 
-   nops     - 3 and 2 byte instructions 
-              2 - 2 byte nop 
-              3 - 3 byte nop 
-              4 - 2, 2-byte nops 
-              >=5 : 3 byte instruction + fn(n-3) 
+   zeros    - This is easy; always insert zeros.
+   nops     - 3-byte and 2-byte instructions
+              2 - 2-byte nop
+              3 - 3-byte nop
+              4 - 2 2-byte nops
+              >=5 : 3-byte instruction + fn (n-3)
    widening - widen previous instructions.  */
 
-static addressT
-get_widen_aligned_address (fragP, address)
-     fragS *fragP;
-     addressT address;
+static offsetT
+get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff)
 {
-  addressT align_pow, new_address, loop_insn_offset;
-  fragS *next_frag;
-  int insn_size;
-  xtensa_opcode opcode, next_opcode;
-  static xtensa_insnbuf insnbuf = NULL;
-
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-
-  if (fragP->fr_type == rs_align || fragP->fr_type == rs_align_code)
-    {
-      align_pow = fragP->fr_offset;
-      new_address = ((address + ((1 << align_pow) - 1))
-		     << align_pow) >> align_pow;
-      return new_address;
-    }
+  addressT target_address, loop_insn_offset;
+  int target_size;
+  xtensa_opcode loop_opcode;
+  bfd_boolean is_loop;
+  int align_power;
+  offsetT opt_diff;
+  offsetT branch_align;
 
-  if (fragP->fr_type == rs_machine_dependent)
+  assert (fragP->fr_type == rs_machine_dependent);
+  switch (fragP->fr_subtype)
     {
-      switch (fragP->fr_subtype)
-	{
-	case RELAX_DESIRE_ALIGN:
-
-	  /* The rule is: get the next fragment's FIRST instruction. 
-	     Find the smallest number of bytes needed to be added 
-	     in order to ensure that the next fragment is FIRST 
-	     instruction will fit in a single word. 
-	     i.e.    2 bytes : 0, 1, 2.  mod 4 
-	             3 bytes: 0, 1 mod 4 
-	     If the FIRST instruction MIGHT be relaxed, 
-	     assume that it will become a 3-byte instruction.  */
-
-	  insn_size = 3;
-	  /* Check to see if it might be 2 bytes.  */
-	  next_opcode = next_frag_opcode (fragP);
-	  if (next_opcode != XTENSA_UNDEFINED
-	      && xtensa_insn_length (xtensa_default_isa, next_opcode) == 2)
-	    insn_size = 2;
-
-	  assert (insn_size <= 4);
-	  for (new_address = address; new_address < address + 4; new_address++)
-	    {
-	      if (new_address >> 2 == (new_address + insn_size - 1) >> 2)
-		return new_address;
-	    }
-	  as_bad (_("internal error aligning"));
-	  return address;
-
-	case RELAX_ALIGN_NEXT_OPCODE:
-	  /* The rule is: get next fragment's FIRST instruction. 
-	     Find the smallest number of bytes needed to be added 
-	     in order to ensure that the next fragment's FIRST 
-	     instruction will fit in a single word. 
-	     i.e.    2 bytes : 0, 1, 2.  mod 4 
-	             3 bytes: 0, 1 mod 4 
-	     If the FIRST instruction MIGHT be relaxed, 
-	     assume that it will become a 3 byte instruction.  */
-
-	  opcode = next_frag_opcode (fragP);
-	  if (opcode == XTENSA_UNDEFINED)
-	    {
-	      as_bad_where (fragP->fr_file, fragP->fr_line,
-			    _("invalid opcode for RELAX_ALIGN_NEXT_OPCODE"));
-	      as_fatal (_("cannot continue"));
-	    }
-	  insn_size = xtensa_insn_length (xtensa_default_isa, opcode);
-	  assert (insn_size <= 4);
-	  assert (is_loop_opcode (opcode));
-
-	  loop_insn_offset = 0;
-	  next_frag = next_non_empty_frag (fragP);
-
-	  /* If the loop has been expanded then the loop
-	     instruction could be at an offset from this fragment.  */
-	  if (next_frag->fr_subtype != RELAX_IMMED)
-	    loop_insn_offset = get_expanded_loop_offset (opcode);
+    case RELAX_DESIRE_ALIGN:
+      target_size = next_frag_format_size (fragP);
+      if (target_size == XTENSA_UNDEFINED)
+	target_size = 3;
+      align_power = branch_align_power (now_seg);
+      branch_align = 1 << align_power;
+      /* Don't count on the section alignment being as large as the target.  */
+      if (target_size > branch_align)
+	target_size = branch_align;
+      opt_diff = get_text_align_fill_size (address, align_power,
+					   target_size, FALSE, FALSE);
+
+      *max_diff = (opt_diff + branch_align
+		   - (target_size + ((address + opt_diff) % branch_align)));
+      assert (*max_diff >= opt_diff);
+      return opt_diff;
 
-	  for (new_address = address; new_address < address + 4; new_address++)
-	    {
-	      if ((new_address + loop_insn_offset + insn_size) >> 2 ==
-		  (new_address + loop_insn_offset + insn_size + 2) >> 2)
-		return new_address;
-	    }
-	  as_bad (_("internal error aligning"));
-	  return address;
+    case RELAX_ALIGN_NEXT_OPCODE:
+      target_size = get_loop_align_size (next_frag_format_size (fragP));
+      loop_insn_offset = 0;
+      is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode);
+      assert (is_loop);
+
+      /* If the loop has been expanded then the LOOP instruction
+	 could be at an offset from this fragment.  */
+      if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0]
+	  != RELAX_IMMED)
+	loop_insn_offset = get_expanded_loop_offset (loop_opcode);
+
+      /* In an ideal world, which is what we are shooting for here,
+	 we wouldn't need to use any NOPs immediately prior to the
+	 LOOP instruction.  If this approach fails, relax_frag_loop_align
+	 will call get_noop_aligned_address.  */
+      target_address =
+	address + loop_insn_offset + xg_get_single_size (loop_opcode);
+      align_power = get_text_align_power (target_size),
+      opt_diff = get_text_align_fill_size (target_address, align_power,
+					   target_size, FALSE, FALSE);
+
+      *max_diff = xtensa_fetch_width
+	- ((target_address + opt_diff) % xtensa_fetch_width)
+	- target_size + opt_diff;
+      assert (*max_diff >= opt_diff);
+      return opt_diff;
 
-	default:
-	  as_bad (_("internal error aligning"));
-	  return address;
-	}
+    default:
+      break;
     }
-  as_bad (_("internal error aligning"));
-  return address;
+  assert (0);
+  return 0;
 }
 
 
 /* md_relax_frag Hook and Helper Functions.  */
 
+static long relax_frag_loop_align (fragS *, long);
+static long relax_frag_for_align (fragS *, long);
+static long relax_frag_immed
+  (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean);
+
+
 /* Return the number of bytes added to this fragment, given that the
    input has been stretched already by "stretch".  */
 
 long
-xtensa_relax_frag (fragP, stretch, stretched_p)
-     fragS *fragP;
-     long stretch;
-     int *stretched_p;
+xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p)
 {
+  xtensa_isa isa = xtensa_default_isa;
   int unreported = fragP->tc_frag_data.unreported_expansion;
   long new_stretch = 0;
   char *file_name;
-  int line, lit_size;
+  unsigned line;
+  int lit_size;
+  static xtensa_insnbuf vbuf = NULL;
+  int slot, num_slots;
+  xtensa_format fmt;
 
   as_where (&file_name, &line);
   new_logical_line (fragP->fr_file, fragP->fr_line);
@@ -6508,7 +8174,8 @@ xtensa_relax_frag (fragP, stretch, stretched_p)
     {
     case RELAX_ALIGN_NEXT_OPCODE:
       /* Always convert.  */
-      new_stretch = relax_frag_text_align (fragP, stretch);
+      if (fragP->tc_frag_data.relax_seen)
+	new_stretch = relax_frag_loop_align (fragP, stretch);
       break;
 
     case RELAX_LOOP_END:
@@ -6518,11 +8185,11 @@ xtensa_relax_frag (fragP, stretch, stretched_p)
     case RELAX_LOOP_END_ADD_NOP:
       /* Add a NOP and switch to .fill 0.  */
       new_stretch = relax_frag_add_nop (fragP);
+      frag_wane (fragP);
       break;
 
     case RELAX_DESIRE_ALIGN:
-      /* We REALLY want to change the relaxation order here.  This
-         should do NOTHING.  The narrowing before it will either align
+      /* Do nothing. The narrowing before this frag will either align
          it or not.  */
       break;
 
@@ -6540,54 +8207,85 @@ xtensa_relax_frag (fragP, stretch, stretched_p)
       new_stretch = 4;
       break;
 
-    case RELAX_NARROW:
-      new_stretch = relax_frag_narrow (fragP, stretch);
-      break;
+    case RELAX_SLOTS:
+      if (vbuf == NULL)
+	vbuf = xtensa_insnbuf_alloc (isa);
 
-    case RELAX_IMMED:
-    case RELAX_IMMED_STEP1:
-    case RELAX_IMMED_STEP2:
-      /* Place the immediate.  */
-      new_stretch = relax_frag_immed (now_seg, fragP, stretch,
-				      fragP->fr_subtype - RELAX_IMMED,
-				      stretched_p);
+      xtensa_insnbuf_from_chars
+	(isa, vbuf, (unsigned char *) fragP->fr_opcode, 0);
+      fmt = xtensa_format_decode (isa, vbuf);
+      num_slots = xtensa_format_num_slots (isa, fmt);
+
+      for (slot = 0; slot < num_slots; slot++)
+	{
+	  switch (fragP->tc_frag_data.slot_subtypes[slot])
+	    {
+	    case RELAX_NARROW:
+	      if (fragP->tc_frag_data.relax_seen)
+		new_stretch += relax_frag_for_align (fragP, stretch);
+	      break;
+
+	    case RELAX_IMMED:
+	    case RELAX_IMMED_STEP1:
+	    case RELAX_IMMED_STEP2:
+	      /* Place the immediate.  */
+	      new_stretch += relax_frag_immed
+		(now_seg, fragP, stretch,
+		 fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
+		 fmt, slot, stretched_p, FALSE);
+	      break;
+
+	    default:
+	      /* This is OK; see the note in xg_assemble_vliw_tokens.  */
+	      break;
+	    }
+	}
       break;
 
     case RELAX_LITERAL_POOL_BEGIN:
     case RELAX_LITERAL_POOL_END:
+    case RELAX_MAYBE_UNREACHABLE:
+    case RELAX_MAYBE_DESIRE_ALIGN:
       /* No relaxation required.  */
       break;
 
+    case RELAX_FILL_NOP:
+    case RELAX_UNREACHABLE:
+      if (fragP->tc_frag_data.relax_seen)
+	new_stretch += relax_frag_for_align (fragP, stretch);
+      break;
+
     default:
       as_bad (_("bad relaxation state"));
     }
 
+  /* Tell gas we need another relaxation pass.  */
+  if (! fragP->tc_frag_data.relax_seen)
+    {
+      fragP->tc_frag_data.relax_seen = TRUE;
+      *stretched_p = 1;
+    }
+
   new_logical_line (file_name, line);
   return new_stretch;
 }
 
 
 static long
-relax_frag_text_align (fragP, stretch)
-     fragS *fragP;
-     long stretch;
+relax_frag_loop_align (fragS *fragP, long stretch)
 {
   addressT old_address, old_next_address, old_size;
   addressT new_address, new_next_address, new_size;
   addressT growth;
 
-  /* Overview of the relaxation procedure for alignment
-     inside an executable section:
-    
-     The old size is stored in the tc_frag_data.text_expansion field.
-    
-     Calculate the new address, fix up the text_expansion and
-     return the growth.  */
+  /* All the frags with relax_frag_for_alignment prior to this one in the
+     section have been done, hopefully eliminating the need for a NOP here.
+     But, this will put it in if necessary.  */
 
   /* Calculate the old address of this fragment and the next fragment.  */
   old_address = fragP->fr_address - stretch;
   old_next_address = (fragP->fr_address - stretch + fragP->fr_fix +
-		      fragP->tc_frag_data.text_expansion);
+		      fragP->tc_frag_data.text_expansion[0]);
   old_size = old_next_address - old_address;
 
   /* Calculate the new address of this fragment and the next fragment.  */
@@ -6599,198 +8297,510 @@ relax_frag_text_align (fragP, stretch)
   growth = new_size - old_size;
 
   /* Fix up the text_expansion field and return the new growth.  */
-  fragP->tc_frag_data.text_expansion += growth;
+  fragP->tc_frag_data.text_expansion[0] += growth;
   return growth;
 }
 
 
-/* Add a NOP (i.e., "or a1, a1, a1").  Use the 3-byte one because we
-   don't know about the availability of density yet.  TODO: When the
-   flags are stored per fragment, use NOP.N when possible.  */
+/* Add a NOP instruction.  */
 
 static long
-relax_frag_add_nop (fragP)
-     fragS *fragP;
+relax_frag_add_nop (fragS *fragP)
 {
-  static xtensa_insnbuf insnbuf = NULL;
-  TInsn t_insn;
   char *nop_buf = fragP->fr_literal + fragP->fr_fix;
-  int length;
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-
-  tinsn_init (&t_insn);
-  t_insn.opcode = xtensa_or_opcode;
-  assert (t_insn.opcode != XTENSA_UNDEFINED);
-
-  t_insn.ntok = 3;
-  set_expr_const (&t_insn.tok[0], 1);
-  set_expr_const (&t_insn.tok[1], 1);
-  set_expr_const (&t_insn.tok[2], 1);
-
-  tinsn_to_insnbuf (&t_insn, insnbuf);
+  int length = fragP->tc_frag_data.is_no_density ? 3 : 2;
+  assemble_nop (length, nop_buf);
   fragP->tc_frag_data.is_insn = TRUE;
-  xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, nop_buf);
 
-  length = xtensa_insn_length (xtensa_default_isa, t_insn.opcode);
   if (fragP->fr_var < length)
     {
-      as_warn (_("fr_var (%ld) < length (%d); ignoring"),
-	       fragP->fr_var, length);
-      frag_wane (fragP);
+      as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length);
       return 0;
     }
 
   fragP->fr_fix += length;
   fragP->fr_var -= length;
-  frag_wane (fragP);
   return length;
 }
 
 
+static long future_alignment_required (fragS *, long);
+
 static long
-relax_frag_narrow (fragP, stretch)
-     fragS *fragP;
-     long stretch;
+relax_frag_for_align (fragS *fragP, long stretch)
 {
-  /* Overview of the relaxation procedure for alignment inside an
-     executable section: Find the number of widenings required and the
-     number of nop bytes required. Store the number of bytes ALREADY
-     widened. If there are enough instructions to widen (must go back
-     ONLY through NARROW fragments), mark each of the fragments as TO BE
-     widened, recalculate the fragment addresses.  */
+  /* Overview of the relaxation procedure for alignment:
+     We can widen with NOPs or by widening instructions or by filling
+     bytes after jump instructions.  Find the opportune places and widen
+     them if necessary.  */
+
+  long stretch_me;
+  long diff;
 
-  assert (fragP->fr_type == rs_machine_dependent
-	  && fragP->fr_subtype == RELAX_NARROW);
+  assert (fragP->fr_subtype == RELAX_FILL_NOP
+	  || fragP->fr_subtype == RELAX_UNREACHABLE
+	  || (fragP->fr_subtype == RELAX_SLOTS
+	      && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW));
 
-  if (!future_alignment_required (fragP, 0))
+  stretch_me = future_alignment_required (fragP, stretch);
+  diff = stretch_me - fragP->tc_frag_data.text_expansion[0];
+  if (diff == 0)
+    return 0;
+
+  if (diff < 0)
     {
-      /* If already expanded but no longer needed because of a prior
-         stretch, it is SAFE to unexpand because the next fragment will
-         NEVER start at an address > the previous time through the
-         relaxation.  */
-      if (fragP->tc_frag_data.text_expansion)
+      /* We expanded on a previous pass.  Can we shrink now?  */
+      long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me;
+      if (shrink <= stretch && stretch > 0)
 	{
-	  if (stretch > 0)
-	    {
-	      fragP->tc_frag_data.text_expansion = 0;
-	      return -1;
-	    }
-	  /* Otherwise we have to live with this bad choice.  */
-	  return 0;
+	  fragP->tc_frag_data.text_expansion[0] = stretch_me;
+	  return -shrink;
 	}
       return 0;
     }
 
-  if (fragP->tc_frag_data.text_expansion == 0)
-    {
-      fragP->tc_frag_data.text_expansion = 1;
-      return 1;
-    }
+  /* Below here, diff > 0.  */
+  fragP->tc_frag_data.text_expansion[0] = stretch_me;
 
-  return 0;
+  return diff;
 }
 
 
-static bfd_boolean
-future_alignment_required (fragP, stretch)
-     fragS *fragP;
-     long stretch;
+/* Return the address of the next frag that should be aligned.
+
+   By "address" we mean the address it _would_ be at if there
+   is no action taken to align it between here and the target frag.
+   In other words, if no narrows and no fill nops are used between
+   here and the frag to align, _even_if_ some of the frags we use
+   to align targets have already expanded on a previous relaxation
+   pass.
+
+   Also, count each frag that may be used to help align the target.
+
+   Return 0 if there are no frags left in the chain that need to be
+   aligned.  */
+
+static addressT
+find_address_of_next_align_frag (fragS **fragPP,
+				 int *wide_nops,
+				 int *narrow_nops,
+				 int *widens,
+				 bfd_boolean *paddable)
 {
-  long address = fragP->fr_address + stretch;
-  int num_widens = 0;
-  addressT aligned_address;
-  offsetT desired_diff;
+  fragS *fragP = *fragPP;
+  addressT address = fragP->fr_address;
+
+  /* Do not reset the counts to 0.  */
 
   while (fragP)
     {
       /* Limit this to a small search.  */
-      if (num_widens > 8)
-	return FALSE;
+      if (*widens >= (int) xtensa_fetch_width)
+	{
+	  *fragPP = fragP;
+	  return 0;
+	}
       address += fragP->fr_fix;
 
-      switch (fragP->fr_type)
+      if (fragP->fr_type == rs_fill)
+	address += fragP->fr_offset * fragP->fr_var;
+      else if (fragP->fr_type == rs_machine_dependent)
 	{
-	case rs_fill:
-	  address += fragP->fr_offset * fragP->fr_var;
-	  break;
-
-	case rs_machine_dependent:
 	  switch (fragP->fr_subtype)
 	    {
-	    case RELAX_NARROW:
-	      /* address += fragP->fr_fix; */
-	      num_widens++;
+	    case RELAX_UNREACHABLE:
+	      *paddable = TRUE;
+	      break;
+
+	    case RELAX_FILL_NOP:
+	      (*wide_nops)++;
+	      if (!fragP->tc_frag_data.is_no_density)
+		(*narrow_nops)++;
+	      break;
+
+	    case RELAX_SLOTS:
+	      if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+		{
+		  (*widens)++;
+		  break;
+		}
+	      address += total_frag_text_expansion (fragP);;
 	      break;
 
 	    case RELAX_IMMED:
-	      address += (/* fragP->fr_fix + */
-			  fragP->tc_frag_data.text_expansion);
+	      address += fragP->tc_frag_data.text_expansion[0];
 	      break;
 
 	    case RELAX_ALIGN_NEXT_OPCODE:
 	    case RELAX_DESIRE_ALIGN:
-	      /* address += fragP->fr_fix; */
-	      aligned_address = get_widen_aligned_address (fragP, address);
-	      desired_diff = aligned_address - address;
-	      assert (desired_diff >= 0);
-	      /* If there are enough wideners in between do it.  */
-	      /* return (num_widens == desired_diff); */
-	      if (num_widens == desired_diff)
-		return TRUE;
-	      if (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE)
-		return FALSE;
+	      *fragPP = fragP;
+	      return address;
+
+	    case RELAX_MAYBE_UNREACHABLE:
+	    case RELAX_MAYBE_DESIRE_ALIGN:
+	      /* Do nothing.  */
 	      break;
 
 	    default:
-	      return FALSE;
+	      /* Just punt if we don't know the type.  */
+	      *fragPP = fragP;
+	      return 0;
 	    }
-	  break;
-
-	default:
-	  return FALSE;
+	}
+      else
+	{
+	  /* Just punt if we don't know the type.  */
+	  *fragPP = fragP;
+	  return 0;
 	}
       fragP = fragP->fr_next;
     }
 
-  return FALSE;
+  *fragPP = fragP;
+  return 0;
 }
 
 
+static long bytes_to_stretch (fragS *, int, int, int, int);
+
 static long
-relax_frag_immed (segP, fragP, stretch, min_steps, stretched_p)
-     segT segP;
-     fragS *fragP;
-     long stretch;
-     int min_steps;
-     int *stretched_p;
+future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED)
 {
-  static xtensa_insnbuf insnbuf = NULL;
-  TInsn t_insn;
+  fragS *this_frag = fragP;
+  long address;
+  int num_widens = 0;
+  int wide_nops = 0;
+  int narrow_nops = 0;
+  bfd_boolean paddable = FALSE;
+  offsetT local_opt_diff;
+  offsetT opt_diff;
+  offsetT max_diff;
+  int stretch_amount = 0;
+  int local_stretch_amount;
+  int global_stretch_amount;
+
+  address = find_address_of_next_align_frag
+    (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable);
+
+  if (!address)
+    {
+      if (this_frag->tc_frag_data.is_aligning_branch)
+	this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED;
+      else
+	frag_wane (this_frag);
+    }
+  else
+    {
+      local_opt_diff = get_aligned_diff (fragP, address, &max_diff);
+      opt_diff = local_opt_diff;
+      assert (opt_diff >= 0);
+      assert (max_diff >= opt_diff);
+      if (max_diff == 0)
+	return 0;
+
+      if (fragP)
+	fragP = fragP->fr_next;
+
+      while (fragP && opt_diff < max_diff && address)
+	{
+	  /* We only use these to determine if we can exit early
+	     because there will be plenty of ways to align future
+	     align frags.  */
+	  int glob_widens = 0;
+	  int dnn = 0;
+	  int dw = 0;
+	  bfd_boolean glob_pad = 0;
+	  address = find_address_of_next_align_frag
+	    (&fragP, &glob_widens, &dnn, &dw, &glob_pad);
+	  /* If there is a padable portion, then skip.  */
+	  if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg)))
+	    address = 0;
+
+	  if (address)
+	    {
+	      offsetT next_m_diff;
+	      offsetT next_o_diff;
+
+	      /* Downrange frags haven't had stretch added to them yet.  */
+	      address += stretch;
+
+	      /* The address also includes any text expansion from this
+		 frag in a previous pass, but we don't want that.  */
+	      address -= this_frag->tc_frag_data.text_expansion[0];
+
+	      /* Assume we are going to move at least opt_diff.  In
+		 reality, we might not be able to, but assuming that
+		 we will helps catch cases where moving opt_diff pushes
+		 the next target from aligned to unaligned.  */
+	      address += opt_diff;
+
+	      next_o_diff = get_aligned_diff (fragP, address, &next_m_diff);
+
+	      /* Now cleanup for the adjustments to address.  */
+	      next_o_diff += opt_diff;
+	      next_m_diff += opt_diff;
+	      if (next_o_diff <= max_diff && next_o_diff > opt_diff)
+		opt_diff = next_o_diff;
+	      if (next_m_diff < max_diff)
+		max_diff = next_m_diff;
+	      fragP = fragP->fr_next;
+	    }
+	}
+
+      /* If there are enough wideners in between, do it.  */
+      if (paddable)
+	{
+	  if (this_frag->fr_subtype == RELAX_UNREACHABLE)
+	    {
+	      assert (opt_diff <= UNREACHABLE_MAX_WIDTH);
+	      return opt_diff;
+	    }
+	  return 0;
+	}
+      local_stretch_amount
+	= bytes_to_stretch (this_frag, wide_nops, narrow_nops,
+			    num_widens, local_opt_diff);
+      global_stretch_amount
+	= bytes_to_stretch (this_frag, wide_nops, narrow_nops,
+			    num_widens, opt_diff);
+      /* If the condition below is true, then the frag couldn't
+	 stretch the correct amount for the global case, so we just
+	 optimize locally.  We'll rely on the subsequent frags to get
+	 the correct alignment in the global case.  */
+      if (global_stretch_amount < local_stretch_amount)
+	stretch_amount = local_stretch_amount;
+      else
+	stretch_amount = global_stretch_amount;
+
+      if (this_frag->fr_subtype == RELAX_SLOTS
+	  && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)
+	assert (stretch_amount <= 1);
+      else if (this_frag->fr_subtype == RELAX_FILL_NOP)
+	{
+	  if (this_frag->tc_frag_data.is_no_density)
+	    assert (stretch_amount == 3 || stretch_amount == 0);
+	  else
+	    assert (stretch_amount <= 3);
+	}
+    }
+  return stretch_amount;
+}
+
+
+/* The idea: widen everything you can to get a target or loop aligned,
+   then start using NOPs.
+
+   When we must have a NOP, here is a table of how we decide
+   (so you don't have to fight through the control flow below):
+
+   wide_nops   = the number of wide NOPs available for aligning
+   narrow_nops = the number of narrow NOPs available for aligning
+		 (a subset of wide_nops)
+   widens      = the number of narrow instructions that should be widened
+
+   Desired   wide   narrow
+   Diff      nop    nop      widens
+   1           0      0         1
+   2           0      1         0
+   3a          1      0         0
+    b          0      1         1 (case 3a makes this case unnecessary)
+   4a          1      0         1
+    b          0      2         0
+    c          0      1         2 (case 4a makes this case unnecessary)
+   5a          1      0         2
+    b          1      1         0
+    c          0      2         1 (case 5b makes this case unnecessary)
+   6a          2      0         0
+    b          1      0         3
+    c          0      1         4 (case 6b makes this case unneccesary)
+    d          1      1         1 (case 6a makes this case unnecessary)
+    e          0      2         2 (case 6a makes this case unnecessary)
+    f          0      3         0 (case 6a makes this case unnecessary)
+   7a          1      0         4
+    b          2      0         1
+    c          1      1         2 (case 7b makes this case unnecessary)
+    d          0      1         5 (case 7a makes this case unnecessary)
+    e          0      2         3 (case 7b makes this case unnecessary)
+    f          0      3         1 (case 7b makes this case unnecessary)
+    g          1      2         1 (case 7b makes this case unnecessary)
+*/
+
+static long
+bytes_to_stretch (fragS *this_frag,
+		  int wide_nops,
+		  int narrow_nops,
+		  int num_widens,
+		  int desired_diff)
+{
+  int bytes_short = desired_diff - num_widens;
+
+  assert (desired_diff >= 0 && desired_diff < 8);
+  if (desired_diff == 0)
+    return 0;
+
+  assert (wide_nops > 0 || num_widens > 0);
+
+  /* Always prefer widening to NOP-filling.  */
+  if (bytes_short < 0)
+    {
+      /* There are enough RELAX_NARROW frags after this one
+	 to align the target without widening this frag in any way.  */
+      return 0;
+    }
+
+  if (bytes_short == 0)
+    {
+      /* Widen every narrow between here and the align target
+	 and the align target will be properly aligned.  */
+      if (this_frag->fr_subtype == RELAX_FILL_NOP)
+	return 0;
+      else
+	return 1;
+    }
+
+  /* From here we will need at least one NOP to get an alignment.
+     However, we may not be able to align at all, in which case,
+     don't widen.  */
+  if (this_frag->fr_subtype == RELAX_FILL_NOP)
+    {
+      switch (desired_diff)
+	{
+	case 1:
+	  return 0;
+	case 2:
+	  if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1)
+	    return 2; /* case 2 */
+	  return 0;
+	case 3:
+	  if (wide_nops > 1)
+	    return 0;
+	  else
+	    return 3; /* case 3a */
+	case 4:
+	  if (num_widens >= 1 && wide_nops == 1)
+	    return 3; /* case 4a */
+	  if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2)
+	    return 2; /* case 4b */
+	  return 0;
+	case 5:
+	  if (num_widens >= 2 && wide_nops == 1)
+	    return 3; /* case 5a */
+	  /* We will need two nops.  Are there enough nops
+	     between here and the align target?  */
+	  if (wide_nops < 2 || narrow_nops == 0)
+	    return 0;
+	  /* Are there other nops closer that can serve instead?  */
+	  if (wide_nops > 2 && narrow_nops > 1)
+	    return 0;
+	  /* Take the density one first, because there might not be
+	     another density one available.  */
+	  if (!this_frag->tc_frag_data.is_no_density)
+	    return 2; /* case 5b narrow */
+	  else
+	    return 3; /* case 5b wide */
+	  return 0;
+	case 6:
+	  if (wide_nops == 2)
+	    return 3; /* case 6a */
+	  else if (num_widens >= 3 && wide_nops == 1)
+	    return 3; /* case 6b */
+	  return 0;
+	case 7:
+	  if (wide_nops == 1 && num_widens >= 4)
+	    return 3; /* case 7a */
+	  else if (wide_nops == 2 && num_widens >= 1)
+	    return 3; /* case 7b */
+	  return 0;
+	default:
+	  assert (0);
+	}
+    }
+  else
+    {
+      /* We will need a NOP no matter what, but should we widen
+	 this instruction to help?
+
+	 This is a RELAX_NARROW frag.  */
+      switch (desired_diff)
+	{
+	case 1:
+	  assert (0);
+	  return 0;
+	case 2:
+	case 3:
+	  return 0;
+	case 4:
+	  if (wide_nops >= 1 && num_widens == 1)
+	    return 1; /* case 4a */
+	  return 0;
+	case 5:
+	  if (wide_nops >= 1 && num_widens == 2)
+	    return 1; /* case 5a */
+	  return 0;
+	case 6:
+	  if (wide_nops >= 2)
+	    return 0; /* case 6a */
+	  else if (wide_nops >= 1 && num_widens == 3)
+	    return 1; /* case 6b */
+	  return 0;
+	case 7:
+	  if (wide_nops >= 1 && num_widens == 4)
+	    return 1; /* case 7a */
+	  else if (wide_nops >= 2 && num_widens == 1)
+	    return 1; /* case 7b */
+	  return 0;
+	default:
+	  assert (0);
+	  return 0;
+	}
+    }
+  assert (0);
+  return 0;
+}
+
+
+static long
+relax_frag_immed (segT segP,
+		  fragS *fragP,
+		  long stretch,
+		  int min_steps,
+		  xtensa_format fmt,
+		  int slot,
+		  int *stretched_p,
+		  bfd_boolean estimate_only)
+{
+  TInsn tinsn;
   int old_size;
   bfd_boolean negatable_branch = FALSE;
   bfd_boolean branch_jmp_to_next = FALSE;
+  bfd_boolean wide_insn = FALSE;
+  xtensa_isa isa = xtensa_default_isa;
   IStack istack;
   offsetT frag_offset;
   int num_steps;
   fragS *lit_fragP;
   int num_text_bytes, num_literal_bytes;
-  int literal_diff, text_diff;
+  int literal_diff, total_text_diff, this_text_diff, first;
 
   assert (fragP->fr_opcode != NULL);
 
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
+  xg_clear_vinsn (&cur_vinsn);
+  vinsn_from_chars (&cur_vinsn, fragP->fr_opcode);
+  if (cur_vinsn.num_slots > 1)
+    wide_insn = TRUE;
 
-  tinsn_from_chars (&t_insn, fragP->fr_opcode);
-  tinsn_immed_from_frag (&t_insn, fragP);
+  tinsn = cur_vinsn.slots[slot];
+  tinsn_immed_from_frag (&tinsn, fragP, slot);
 
-  negatable_branch = is_negatable_branch (&t_insn);
+  if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode))
+    return 0;
 
-  old_size = xtensa_insn_length (xtensa_default_isa, t_insn.opcode);
+  if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
+    branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP);
 
-  if (software_avoid_b_j_loop_end)
-    branch_jmp_to_next = is_branch_jmp_to_next (&t_insn, fragP);
+  negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1);
+
+  old_size = xtensa_format_length (isa, fmt);
 
   /* Special case: replace a branch to the next instruction with a NOP.
      This is required to work around a hardware bug in T1040.0 and also
@@ -6807,7 +8817,7 @@ relax_frag_immed (segP, fragP, stretch, min_steps, stretched_p)
 
   frag_offset = fragP->fr_opcode - fragP->fr_literal;
   istack_init (&istack);
-  num_steps = xg_assembly_relax (&istack, &t_insn, segP, fragP, frag_offset,
+  num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset,
 				 min_steps, stretch);
   if (num_steps < min_steps)
     {
@@ -6821,26 +8831,40 @@ relax_frag_immed (segP, fragP, stretch, min_steps, stretched_p)
       return 0;
     }
 
-  fragP->fr_subtype = (int) RELAX_IMMED + num_steps;
+  fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps;
 
   /* Figure out the number of bytes needed.  */
   lit_fragP = 0;
-  num_text_bytes = get_num_stack_text_bytes (&istack) - old_size;
   num_literal_bytes = get_num_stack_literal_bytes (&istack);
-  literal_diff = num_literal_bytes - fragP->tc_frag_data.literal_expansion;
-  text_diff = num_text_bytes - fragP->tc_frag_data.text_expansion;
+  literal_diff =
+    num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot];
+  first = 0;
+  while (istack.insn[first].opcode == XTENSA_UNDEFINED)
+    first++;
+  num_text_bytes = get_num_stack_text_bytes (&istack);
+  if (wide_insn)
+    {
+      num_text_bytes += old_size;
+      if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot))
+	num_text_bytes -= xg_get_single_size (istack.insn[first].opcode);
+    }
+  total_text_diff = num_text_bytes - old_size;
+  this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot];
 
   /* It MUST get larger.  If not, we could get an infinite loop.  */
-  know (num_text_bytes >= 0);
-  know (literal_diff >= 0 && text_diff >= 0);
+  assert (num_text_bytes >= 0);
+  assert (literal_diff >= 0);
+  assert (total_text_diff >= 0);
 
-  fragP->tc_frag_data.text_expansion = num_text_bytes;
-  fragP->tc_frag_data.literal_expansion = num_literal_bytes;
+  fragP->tc_frag_data.text_expansion[slot] = total_text_diff;
+  fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes;
+  assert (fragP->tc_frag_data.text_expansion[slot] >= 0);
+  assert (fragP->tc_frag_data.literal_expansion[slot] >= 0);
 
   /* Find the associated expandable literal for this.  */
   if (literal_diff != 0)
     {
-      lit_fragP = fragP->tc_frag_data.literal_frag;
+      lit_fragP = fragP->tc_frag_data.literal_frags[slot];
       if (lit_fragP)
 	{
 	  assert (literal_diff == 4);
@@ -6858,29 +8882,30 @@ relax_frag_immed (segP, fragP, stretch, min_steps, stretched_p)
 	}
     }
 
-  /* This implicitly uses the assumption that a branch is negated
-     when the size of the output increases by at least 2 bytes.  */
+  if (negatable_branch && istack.ninsn > 1)
+    update_next_frag_state (fragP);
 
-  if (negatable_branch && num_text_bytes >= 2)
-    {
-      /* If next frag is a loop end, then switch it to add a NOP.  */
-      update_next_frag_nop_state (fragP);
-    }
-
-  return text_diff;
+  return this_text_diff;
 }
 
 
 /* md_convert_frag Hook and Helper Functions.  */
 
+static void convert_frag_align_next_opcode (fragS *);
+static void convert_frag_narrow (segT, fragS *, xtensa_format, int);
+static void convert_frag_fill_nop (fragS *);
+static void convert_frag_immed (segT, fragS *, int, xtensa_format, int);
+
 void
-md_convert_frag (abfd, sec, fragp)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec;
-     fragS *fragp;
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp)
 {
+  static xtensa_insnbuf vbuf = NULL;
+  xtensa_isa isa = xtensa_default_isa;
+  int slot;
+  int num_slots;
+  xtensa_format fmt;
   char *file_name;
-  int line;
+  unsigned line;
 
   as_where (&file_name, &line);
   new_logical_line (fragp->fr_file, fragp->fr_line);
@@ -6900,16 +8925,55 @@ md_convert_frag (abfd, sec, fragp)
     case RELAX_LITERAL_FINAL:
       break;
 
-    case RELAX_NARROW:
-      /* No conversion.  */
-      convert_frag_narrow (fragp);
+    case RELAX_SLOTS:
+      if (vbuf == NULL)
+	vbuf = xtensa_insnbuf_alloc (isa);
+
+      xtensa_insnbuf_from_chars
+	(isa, vbuf, (unsigned char *) fragp->fr_opcode, 0);
+      fmt = xtensa_format_decode (isa, vbuf);
+      num_slots = xtensa_format_num_slots (isa, fmt);
+
+      for (slot = 0; slot < num_slots; slot++)
+	{
+	  switch (fragp->tc_frag_data.slot_subtypes[slot])
+	    {
+	    case RELAX_NARROW:
+	      convert_frag_narrow (sec, fragp, fmt, slot);
+	      break;
+
+	    case RELAX_IMMED:
+	    case RELAX_IMMED_STEP1:
+	    case RELAX_IMMED_STEP2:
+	      /* Place the immediate.  */
+	      convert_frag_immed
+		(sec, fragp,
+		 fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED,
+		 fmt, slot);
+	      break;
+
+	    default:
+	      /* This is OK because some slots could have
+		 relaxations and others have none.  */
+	      break;
+	    }
+	}
+      break;
+
+    case RELAX_UNREACHABLE:
+      memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var);
+      fragp->fr_fix += fragp->tc_frag_data.text_expansion[0];
+      fragp->fr_var -= fragp->tc_frag_data.text_expansion[0];
+      frag_wane (fragp);
       break;
 
-    case RELAX_IMMED:
-    case RELAX_IMMED_STEP1:
-    case RELAX_IMMED_STEP2:
-      /* Place the immediate.  */
-      convert_frag_immed (sec, fragp, fragp->fr_subtype - RELAX_IMMED);
+    case RELAX_MAYBE_UNREACHABLE:
+    case RELAX_MAYBE_DESIRE_ALIGN:
+      frag_wane (fragp);
+      break;
+
+    case RELAX_FILL_NOP:
+      convert_frag_fill_nop (fragp);
       break;
 
     case RELAX_LITERAL_NR:
@@ -6947,16 +9011,14 @@ md_convert_frag (abfd, sec, fragp)
 }
 
 
-void
-convert_frag_align_next_opcode (fragp)
-     fragS *fragp;
+static void
+convert_frag_align_next_opcode (fragS *fragp)
 {
   char *nop_buf;		/* Location for Writing.  */
-  size_t i;
-
   bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density;
   addressT aligned_address;
-  size_t fill_size, nop_count;
+  offsetT fill_size;
+  int nop, nop_count;
 
   aligned_address = get_noop_aligned_address (fragp, fragp->fr_address +
 					      fragp->fr_fix);
@@ -6964,10 +9026,10 @@ convert_frag_align_next_opcode (fragp)
   nop_count = get_text_align_nop_count (fill_size, use_no_density);
   nop_buf = fragp->fr_literal + fragp->fr_fix;
 
-  for (i = 0; i < nop_count; i++)
+  for (nop = 0; nop < nop_count; nop++)
     {
-      size_t nop_size;
-      nop_size = get_text_align_nth_nop_size (fill_size, i, use_no_density);
+      int nop_size;
+      nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density);
 
       assemble_nop (nop_size, nop_buf);
       nop_buf += nop_size;
@@ -6979,15 +9041,25 @@ convert_frag_align_next_opcode (fragp)
 
 
 static void
-convert_frag_narrow (fragP)
-     fragS *fragP;
+convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot)
 {
-  static xtensa_insnbuf insnbuf = NULL;
-  TInsn t_insn, single_target;
-  int size, old_size, diff, error_val;
+  TInsn tinsn, single_target;
+  int size, old_size, diff;
   offsetT frag_offset;
 
-  if (fragP->tc_frag_data.text_expansion == 0)
+  assert (slot == 0);
+  tinsn_from_chars (&tinsn, fragP->fr_opcode, 0);
+
+  if (fragP->tc_frag_data.is_aligning_branch == 1)
+    {
+      assert (fragP->tc_frag_data.text_expansion[0] == 1
+	      || fragP->tc_frag_data.text_expansion[0] == 0);
+      convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0],
+			  fmt, slot);
+      return;
+    }
+
+  if (fragP->tc_frag_data.text_expansion[0] == 0)
     {
       /* No conversion.  */
       fragP->fr_var = 0;
@@ -6996,26 +9068,26 @@ convert_frag_narrow (fragP)
 
   assert (fragP->fr_opcode != NULL);
 
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
-
-  tinsn_from_chars (&t_insn, fragP->fr_opcode);
-  tinsn_immed_from_frag (&t_insn, fragP);
+  /* Frags in this relaxation state should only contain
+     single instruction bundles.  */
+  tinsn_immed_from_frag (&tinsn, fragP, 0);
 
   /* Just convert it to a wide form....  */
   size = 0;
-  old_size = xtensa_insn_length (xtensa_default_isa, t_insn.opcode);
+  old_size = xg_get_single_size (tinsn.opcode);
 
   tinsn_init (&single_target);
   frag_offset = fragP->fr_opcode - fragP->fr_literal;
 
-  error_val = xg_expand_narrow (&single_target, &t_insn);
-  if (error_val)
-    as_bad (_("unable to widen instruction"));
+  if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE))
+    {
+      as_bad (_("unable to widen instruction"));
+      return;
+    }
 
-  size = xtensa_insn_length (xtensa_default_isa, single_target.opcode);
-  xg_emit_insn_to_buf (&single_target, fragP->fr_opcode,
-		       fragP, frag_offset, TRUE);
+  size = xg_get_single_size (single_target.opcode);
+  xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP,
+		       frag_offset, TRUE);
 
   diff = size - old_size;
   assert (diff >= 0);
@@ -7029,81 +9101,132 @@ convert_frag_narrow (fragP)
 
 
 static void
-convert_frag_immed (segP, fragP, min_steps)
-     segT segP;
-     fragS *fragP;
-     int min_steps;
+convert_frag_fill_nop (fragS *fragP)
+{
+  char *loc = &fragP->fr_literal[fragP->fr_fix];
+  int size = fragP->tc_frag_data.text_expansion[0];
+  assert ((unsigned) size == (fragP->fr_next->fr_address
+			      - fragP->fr_address - fragP->fr_fix));
+  if (size == 0)
+    {
+      /* No conversion.  */
+      fragP->fr_var = 0;
+      return;
+    }
+  assemble_nop (size, loc);
+  fragP->tc_frag_data.is_insn = TRUE;
+  fragP->fr_var -= size;
+  fragP->fr_fix += size;
+  frag_wane (fragP);
+}
+
+
+static fixS *fix_new_exp_in_seg
+  (segT, subsegT, fragS *, int, int, expressionS *, int,
+   bfd_reloc_code_real_type);
+static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *);
+
+static void
+convert_frag_immed (segT segP,
+		    fragS *fragP,
+		    int min_steps,
+		    xtensa_format fmt,
+		    int slot)
 {
   char *immed_instr = fragP->fr_opcode;
-  static xtensa_insnbuf insnbuf = NULL;
-  TInsn orig_t_insn;
+  TInsn orig_tinsn;
   bfd_boolean expanded = FALSE;
-  char *fr_opcode = fragP->fr_opcode;
   bfd_boolean branch_jmp_to_next = FALSE;
-  int size;
+  char *fr_opcode = fragP->fr_opcode;
+  xtensa_isa isa = xtensa_default_isa;
+  bfd_boolean wide_insn = FALSE;
+  int bytes;
+  bfd_boolean is_loop;
 
-  assert (fragP->fr_opcode != NULL);
+  assert (fr_opcode != NULL);
 
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa);
+  xg_clear_vinsn (&cur_vinsn);
 
-  tinsn_from_chars (&orig_t_insn, fragP->fr_opcode);
-  tinsn_immed_from_frag (&orig_t_insn, fragP);
+  vinsn_from_chars (&cur_vinsn, fr_opcode);
+  if (cur_vinsn.num_slots > 1)
+    wide_insn = TRUE;
 
-  /* Here is the fun stuff:  Get the immediate field from this
-     instruction.  If it fits, we're done.  If not, find the next
-     instruction sequence that fits.  */
+  orig_tinsn = cur_vinsn.slots[slot];
+  tinsn_immed_from_frag (&orig_tinsn, fragP, slot);
 
-  if (software_avoid_b_j_loop_end)
-    branch_jmp_to_next = is_branch_jmp_to_next (&orig_t_insn, fragP);
+  is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1;
+
+  if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform)
+    branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP);
 
   if (branch_jmp_to_next && !next_frag_is_loop_target (fragP))
     {
       /* Conversion just inserts a NOP and marks the fix as completed.  */
-      size = xtensa_insn_length (xtensa_default_isa, orig_t_insn.opcode);
-      assemble_nop (size, fragP->fr_opcode);
+      bytes = xtensa_format_length (isa, fmt);
+      if (bytes >= 4)
+	{
+	  cur_vinsn.slots[slot].opcode =
+	    xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot);
+	  cur_vinsn.slots[slot].ntok = 0;
+	}
+      else
+	{
+	  bytes += fragP->tc_frag_data.text_expansion[0];
+	  assert (bytes == 2 || bytes == 3);
+	  build_nop (&cur_vinsn.slots[0], bytes);
+	  fragP->fr_fix += fragP->tc_frag_data.text_expansion[0];
+	}
+      vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE);
+      xtensa_insnbuf_to_chars
+	(isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0);
       fragP->fr_var = 0;
     }
   else
     {
+      /* Here is the fun stuff:  Get the immediate field from this
+	 instruction.  If it fits, we're done.  If not, find the next
+	 instruction sequence that fits.  */
+
       IStack istack;
       int i;
       symbolS *lit_sym = NULL;
       int total_size = 0;
+      int target_offset = 0;
       int old_size;
       int diff;
       symbolS *gen_label = NULL;
       offsetT frag_offset;
+      bfd_boolean first = TRUE;
+      bfd_boolean last_is_jump;
 
-      /* It does not fit.  Find something that does and 
+      /* It does not fit.  Find something that does and
          convert immediately.  */
-      frag_offset = fragP->fr_opcode - fragP->fr_literal;
+      frag_offset = fr_opcode - fragP->fr_literal;
       istack_init (&istack);
-      xg_assembly_relax (&istack, &orig_t_insn,
+      xg_assembly_relax (&istack, &orig_tinsn,
 			 segP, fragP, frag_offset, min_steps, 0);
 
-      old_size = xtensa_insn_length (xtensa_default_isa, orig_t_insn.opcode);
+      old_size = xtensa_format_length (isa, fmt);
 
       /* Assemble this right inline.  */
 
       /* First, create the mapping from a label name to the REAL label.  */
-      total_size = 0;
+      target_offset = 0;
       for (i = 0; i < istack.ninsn; i++)
 	{
-	  TInsn *t_insn = &istack.insn[i];
-	  int size = 0;
+	  TInsn *tinsn = &istack.insn[i];
 	  fragS *lit_frag;
 
-	  switch (t_insn->insn_type)
+	  switch (tinsn->insn_type)
 	    {
 	    case ITYPE_LITERAL:
 	      if (lit_sym != NULL)
 		as_bad (_("multiple literals in expansion"));
 	      /* First find the appropriate space in the literal pool.  */
-	      lit_frag = fragP->tc_frag_data.literal_frag;
+	      lit_frag = fragP->tc_frag_data.literal_frags[slot];
 	      if (lit_frag == NULL)
 		as_bad (_("no registered fragment for literal"));
-	      if (t_insn->ntok != 1)
+	      if (tinsn->ntok != 1)
 		as_bad (_("number of literal tokens != 1"));
 
 	      /* Set the literal symbol and add a fixup.  */
@@ -7111,53 +9234,112 @@ convert_frag_immed (segP, fragP, min_steps)
 	      break;
 
 	    case ITYPE_LABEL:
+	      if (align_targets && !is_loop)
+		{
+		  fragS *unreach = fragP->fr_next;
+		  while (!(unreach->fr_type == rs_machine_dependent
+			   && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
+			       || unreach->fr_subtype == RELAX_UNREACHABLE)))
+		    {
+		      unreach = unreach->fr_next;
+		    }
+
+		  assert (unreach->fr_type == rs_machine_dependent
+			  && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE
+			      || unreach->fr_subtype == RELAX_UNREACHABLE));
+
+		  target_offset += unreach->tc_frag_data.text_expansion[0];
+		}
 	      assert (gen_label == NULL);
 	      gen_label = symbol_new (FAKE_LABEL_NAME, now_seg,
-				      fragP->fr_opcode - fragP->fr_literal +
-				      total_size, fragP);
+				      fr_opcode - fragP->fr_literal
+				      + target_offset, fragP);
 	      break;
 
 	    case ITYPE_INSN:
-	      size = xtensa_insn_length (xtensa_default_isa, t_insn->opcode);
-	      total_size += size;
+	      if (first && wide_insn)
+		{
+		  target_offset += xtensa_format_length (isa, fmt);
+		  first = FALSE;
+		  if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
+		    target_offset += xg_get_single_size (tinsn->opcode);
+		}
+	      else
+		target_offset += xg_get_single_size (tinsn->opcode);
 	      break;
 	    }
 	}
 
       total_size = 0;
+      first = TRUE;
+      last_is_jump = FALSE;
       for (i = 0; i < istack.ninsn; i++)
 	{
-	  TInsn *t_insn = &istack.insn[i];
+	  TInsn *tinsn = &istack.insn[i];
 	  fragS *lit_frag;
 	  int size;
 	  segT target_seg;
+	  bfd_reloc_code_real_type reloc_type;
 
-	  switch (t_insn->insn_type)
+	  switch (tinsn->insn_type)
 	    {
 	    case ITYPE_LITERAL:
-	      lit_frag = fragP->tc_frag_data.literal_frag;
-	      /* already checked */
+	      lit_frag = fragP->tc_frag_data.literal_frags[slot];
+	      /* Already checked.  */
 	      assert (lit_frag != NULL);
 	      assert (lit_sym != NULL);
-	      assert (t_insn->ntok == 1);
-	      /* add a fixup */
+	      assert (tinsn->ntok == 1);
+	      /* Add a fixup.  */
 	      target_seg = S_GET_SEGMENT (lit_sym);
 	      assert (target_seg);
+	      if (tinsn->tok[0].X_op == O_pltrel)
+		reloc_type = BFD_RELOC_XTENSA_PLT;
+	      else
+		reloc_type = BFD_RELOC_32;
 	      fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4,
-				  &t_insn->tok[0], FALSE, BFD_RELOC_32);
+				  &tinsn->tok[0], FALSE, reloc_type);
 	      break;
 
 	    case ITYPE_LABEL:
 	      break;
 
 	    case ITYPE_INSN:
-	      xg_resolve_labels (t_insn, gen_label);
-	      xg_resolve_literals (t_insn, lit_sym);
-	      size = xtensa_insn_length (xtensa_default_isa, t_insn->opcode);
-	      total_size += size;
-	      xg_emit_insn_to_buf (t_insn, immed_instr, fragP,
-				   immed_instr - fragP->fr_literal, TRUE);
+	      xg_resolve_labels (tinsn, gen_label);
+	      xg_resolve_literals (tinsn, lit_sym);
+	      if (wide_insn && first)
+		{
+		  first = FALSE;
+		  if (opcode_fits_format_slot (tinsn->opcode, fmt, slot))
+		    {
+		      cur_vinsn.slots[slot] = *tinsn;
+		    }
+		  else
+		    {
+		      cur_vinsn.slots[slot].opcode =
+			xtensa_format_slot_nop_opcode (isa, fmt, slot);
+		      cur_vinsn.slots[slot].ntok = 0;
+		    }
+		  vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE);
+		  xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf,
+					   (unsigned char *) immed_instr, 0);
+		  fragP->tc_frag_data.is_insn = TRUE;
+		  size = xtensa_format_length (isa, fmt);
+		  if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot))
+		    {
+		      xg_emit_insn_to_buf
+			(tinsn, immed_instr + size, fragP,
+			 immed_instr - fragP->fr_literal + size, TRUE);
+		      size += xg_get_single_size (tinsn->opcode);
+		    }
+		}
+	      else
+		{
+		  size = xg_get_single_size (tinsn->opcode);
+		  xg_emit_insn_to_buf (tinsn, immed_instr, fragP,
+				       immed_instr - fragP->fr_literal, TRUE);
+		}
 	      immed_instr += size;
+	      total_size += size;
 	      break;
 	    }
 	}
@@ -7171,20 +9353,17 @@ convert_frag_immed (segP, fragP, min_steps)
       fragP->fr_fix += diff;
     }
 
-  /* Clean it up.  */
-  fragP->fr_var = 0;
-
   /* Check for undefined immediates in LOOP instructions.  */
-  if (is_loop_opcode (orig_t_insn.opcode))
+  if (is_loop)
     {
       symbolS *sym;
-      sym = orig_t_insn.tok[1].X_add_symbol;
+      sym = orig_tinsn.tok[1].X_add_symbol;
       if (sym != NULL && !S_IS_DEFINED (sym))
 	{
 	  as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
 	  return;
 	}
-      sym = orig_t_insn.tok[1].X_op_symbol;
+      sym = orig_tinsn.tok[1].X_op_symbol;
       if (sym != NULL && !S_IS_DEFINED (sym))
 	{
 	  as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym));
@@ -7192,16 +9371,15 @@ convert_frag_immed (segP, fragP, min_steps)
 	}
     }
 
-  if (expanded && is_loop_opcode (orig_t_insn.opcode))
-    convert_frag_immed_finish_loop (segP, fragP, &orig_t_insn);
+  if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1)
+    convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn);
 
-  if (expanded && is_direct_call_opcode (orig_t_insn.opcode))
+  if (expanded && is_direct_call_opcode (orig_tinsn.opcode))
     {
       /* Add an expansion note on the expanded instruction.  */
       fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4,
-			  &orig_t_insn.tok[0], TRUE,
+			  &orig_tinsn.tok[0], TRUE,
 			  BFD_RELOC_XTENSA_ASM_EXPAND);
-
     }
 }
 
@@ -7210,57 +9388,47 @@ convert_frag_immed (segP, fragP, min_steps)
    switch to that segment to do this.  */
 
 static fixS *
-fix_new_exp_in_seg (new_seg, new_subseg,
-		    frag, where, size, exp, pcrel, r_type)
-     segT new_seg;
-     subsegT new_subseg;
-     fragS *frag;
-     int where;
-     int size;
-     expressionS *exp;
-     int pcrel;
-     bfd_reloc_code_real_type r_type;
+fix_new_exp_in_seg (segT new_seg,
+		    subsegT new_subseg,
+		    fragS *frag,
+		    int where,
+		    int size,
+		    expressionS *exp,
+		    int pcrel,
+		    bfd_reloc_code_real_type r_type)
 {
   fixS *new_fix;
   segT seg = now_seg;
   subsegT subseg = now_subseg;
+
   assert (new_seg != 0);
   subseg_set (new_seg, new_subseg);
 
-  if (r_type == BFD_RELOC_32
-      && exp->X_add_symbol
-      && symbol_get_tc (exp->X_add_symbol)->plt == 1)
-    {
-      r_type = BFD_RELOC_XTENSA_PLT;
-    }
-
   new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type);
   subseg_set (seg, subseg);
   return new_fix;
 }
 
 
-/* Relax a loop instruction so that it can span loop >256 bytes.  */
-/* 
-                  loop    as, .L1 
-          .L0: 
-                  rsr     as, LEND 
-                  wsr     as, LBEG 
-                  addi    as, as, lo8(label-.L1) 
-                  addmi   as, as, mid8(label-.L1) 
-                  wsr     as, LEND 
-                  isync 
-                  rsr     as, LCOUNT 
-                  addi    as, as, 1 
-          .L1: 
-                  <<body>> 
-          label:                                     */
+/* Relax a loop instruction so that it can span loop >256 bytes.
+
+                  loop    as, .L1
+          .L0:
+                  rsr     as, LEND
+                  wsr     as, LBEG
+                  addi    as, as, lo8 (label-.L1)
+                  addmi   as, as, mid8 (label-.L1)
+                  wsr     as, LEND
+                  isync
+                  rsr     as, LCOUNT
+                  addi    as, as, 1
+          .L1:
+                  <<body>>
+          label:
+*/
 
 static void
-convert_frag_immed_finish_loop (segP, fragP, t_insn)
-     segT segP;
-     fragS *fragP;
-     TInsn *t_insn;
+convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn)
 {
   TInsn loop_insn;
   TInsn addi_insn;
@@ -7272,26 +9440,41 @@ convert_frag_immed_finish_loop (segP, fragP, t_insn)
   addressT loop_offset;
   addressT addi_offset = 9;
   addressT addmi_offset = 12;
+  fragS *next_fragP;
+  int target_count;
 
   if (!insnbuf)
     insnbuf = xtensa_insnbuf_alloc (isa);
 
   /* Get the loop offset.  */
-  loop_offset = get_expanded_loop_offset (t_insn->opcode);
-  /* Validate that there really is a LOOP at the loop_offset.  */
-  tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset);
+  loop_offset = get_expanded_loop_offset (tinsn->opcode);
 
-  if (!is_loop_opcode (loop_insn.opcode))
-    {
-      as_bad_where (fragP->fr_file, fragP->fr_line,
-		    _("loop relaxation specification does not correspond"));
-      assert (0);
-    }
+  /* Validate that there really is a LOOP at the loop_offset.  Because
+     loops are not bundleable, we can assume that the instruction will be
+     in slot 0.  */
+  tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0);
+  tinsn_immed_from_frag (&loop_insn, fragP, 0);
+
+  assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1);
   addi_offset += loop_offset;
   addmi_offset += loop_offset;
 
-  assert (t_insn->ntok == 2);
-  target = get_expression_value (segP, &t_insn->tok[1]);
+  assert (tinsn->ntok == 2);
+  if (tinsn->tok[1].X_op == O_constant)
+    target = tinsn->tok[1].X_add_number;
+  else if (tinsn->tok[1].X_op == O_symbol)
+    {
+      /* Find the fragment.  */
+      symbolS *sym = tinsn->tok[1].X_add_symbol;
+      assert (S_GET_SEGMENT (sym) == segP
+	      || S_GET_SEGMENT (sym) == absolute_section);
+      target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number);
+    }
+  else
+    {
+      as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op);
+      target = 0;
+    }
 
   know (symbolP);
   know (symbolP->sy_frag);
@@ -7307,49 +9490,45 @@ convert_frag_immed_finish_loop (segP, fragP, t_insn)
       loop_length_hi += 256;
     }
 
-  /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most 
+  /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most
      32512.  If the loop is larger than that, then we just fail.  */
   if (loop_length_hi > 32512)
     as_bad_where (fragP->fr_file, fragP->fr_line,
 		  _("loop too long for LOOP instruction"));
 
-  tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset);
+  tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0);
   assert (addi_insn.opcode == xtensa_addi_opcode);
 
-  tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset);
+  tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0);
   assert (addmi_insn.opcode == xtensa_addmi_opcode);
 
   set_expr_const (&addi_insn.tok[2], loop_length_lo);
   tinsn_to_insnbuf (&addi_insn, insnbuf);
-  
+
   fragP->tc_frag_data.is_insn = TRUE;
-  xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addi_offset);
+  xtensa_insnbuf_to_chars
+    (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0);
 
   set_expr_const (&addmi_insn.tok[2], loop_length_hi);
   tinsn_to_insnbuf (&addmi_insn, insnbuf);
-  xtensa_insnbuf_to_chars (isa, insnbuf, fragP->fr_opcode + addmi_offset);
-}
+  xtensa_insnbuf_to_chars
+    (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0);
 
+  /* Walk through all of the frags from here to the loop end
+     and mark them as no_transform to keep them from being modified
+     by the linker.  If we ever have a relocation for the
+     addi/addmi of the difference of two symbols we can remove this.  */
 
-static offsetT
-get_expression_value (segP, exp)
-     segT segP;
-     expressionS *exp;
-{
-  if (exp->X_op == O_constant)
-    return exp->X_add_number;
-  if (exp->X_op == O_symbol)
+  target_count = 0;
+  for (next_fragP = fragP; next_fragP != NULL;
+       next_fragP = next_fragP->fr_next)
     {
-      /* Find the fragment.  */
-      symbolS *sym = exp->X_add_symbol;
-
-      assert (S_GET_SEGMENT (sym) == segP
-	      || S_GET_SEGMENT (sym) == absolute_section);
-
-      return (S_GET_VALUE (sym) + exp->X_add_number);
+      next_fragP->tc_frag_data.is_no_transform = TRUE;
+      if (next_fragP->tc_frag_data.is_loop_target)
+	target_count++;
+      if (target_count == 2)
+	break;
     }
-  as_bad (_("invalid expression evaluation type %d"), exp->X_op);
-  return 0;
 }
 
 
@@ -7366,99 +9545,107 @@ typedef struct subseg_map_struct
 
   /* the data */
   unsigned flags;
+  float total_freq;	/* fall-through + branch target frequency */
+  float target_freq;	/* branch target frequency alone */
 
   struct subseg_map_struct *next;
 } subseg_map;
 
-static subseg_map *sseg_map = NULL;
 
+static subseg_map *sseg_map = NULL;
 
-static unsigned
-get_last_insn_flags (seg, subseg)
-     segT seg;
-     subsegT subseg;
+static subseg_map *
+get_subseg_info (segT seg, subsegT subseg)
 {
   subseg_map *subseg_e;
 
-  for (subseg_e = sseg_map; subseg_e != NULL; subseg_e = subseg_e->next)
-    if (seg == subseg_e->seg && subseg == subseg_e->subseg)
-      return subseg_e->flags;
-
-  return 0;
+  for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
+    {
+      if (seg == subseg_e->seg && subseg == subseg_e->subseg)
+	break;
+    }
+  return subseg_e;
 }
 
 
-static void
-set_last_insn_flags (seg, subseg, fl, val)
-     segT seg;
-     subsegT subseg;
-     unsigned fl;
-     bfd_boolean val;
+static subseg_map *
+add_subseg_info (segT seg, subsegT subseg)
 {
-  subseg_map *subseg_e;
+  subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
+  memset (subseg_e, 0, sizeof (subseg_map));
+  subseg_e->seg = seg;
+  subseg_e->subseg = subseg;
+  subseg_e->flags = 0;
+  /* Start off considering every branch target very important.  */
+  subseg_e->target_freq = 1.0;
+  subseg_e->total_freq = 1.0;
+  subseg_e->next = sseg_map;
+  sseg_map = subseg_e;
+  return subseg_e;
+}
 
-  for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next)
-    if (seg == subseg_e->seg && subseg == subseg_e->subseg)
-      break;
 
-  if (!subseg_e)
-    {
-      subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map));
-      memset (subseg_e, 0, sizeof (subseg_map));
-      subseg_e->seg = seg;
-      subseg_e->subseg = subseg;
-      subseg_e->flags = 0;
-      subseg_e->next = sseg_map;
-      sseg_map = subseg_e;
-    }
+static unsigned
+get_last_insn_flags (segT seg, subsegT subseg)
+{
+  subseg_map *subseg_e = get_subseg_info (seg, subseg);
+  if (subseg_e)
+    return subseg_e->flags;
+  return 0;
+}
 
+
+static void
+set_last_insn_flags (segT seg,
+		     subsegT subseg,
+		     unsigned fl,
+		     bfd_boolean val)
+{
+  subseg_map *subseg_e = get_subseg_info (seg, subseg);
+  if (! subseg_e)
+    subseg_e = add_subseg_info (seg, subseg);
   if (val)
     subseg_e->flags |= fl;
   else
     subseg_e->flags &= ~fl;
 }
 
-
-/* Segment Lists and emit_state Stuff.  */
-
-/* Remove the segment from the global sections list.  */
 
-static void
-xtensa_remove_section (sec)
-     segT sec;
+static float
+get_subseg_total_freq (segT seg, subsegT subseg)
 {
-  /* Handle brain-dead bfd_section_list_remove macro, which
-     expect the address of the prior section's "next" field, not
-     just the address of the section to remove.  */
+  subseg_map *subseg_e = get_subseg_info (seg, subseg);
+  if (subseg_e)
+    return subseg_e->total_freq;
+  return 1.0;
+}
 
-  segT *ps_next_ptr = &stdoutput->sections;
-  while (*ps_next_ptr != sec && *ps_next_ptr != NULL) 
-    ps_next_ptr = &(*ps_next_ptr)->next;
-  
-  assert (*ps_next_ptr != NULL);
 
-  bfd_section_list_remove (stdoutput, ps_next_ptr);
+static float
+get_subseg_target_freq (segT seg, subsegT subseg)
+{
+  subseg_map *subseg_e = get_subseg_info (seg, subseg);
+  if (subseg_e)
+    return subseg_e->target_freq;
+  return 1.0;
 }
 
 
 static void
-xtensa_insert_section (after_sec, sec)
-     segT after_sec;
-     segT sec;
+set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f)
 {
-  segT *after_sec_next;
-  if (after_sec == NULL)
-    after_sec_next = &stdoutput->sections;
-  else
-    after_sec_next = &after_sec->next;
-
-  bfd_section_list_insert (stdoutput, after_sec_next, sec);
+  subseg_map *subseg_e = get_subseg_info (seg, subseg);
+  if (! subseg_e)
+    subseg_e = add_subseg_info (seg, subseg);
+  subseg_e->total_freq = total_f;
+  subseg_e->target_freq = target_f;
 }
 
+
+/* Segment Lists and emit_state Stuff.  */
 
 static void
-xtensa_move_seg_list_to_beginning (head)
-     seg_list *head;
+xtensa_move_seg_list_to_beginning (seg_list *head)
 {
   head = head->next;
   while (head)
@@ -7467,16 +9654,20 @@ xtensa_move_seg_list_to_beginning (head)
 
       /* Move the literal section to the front of the section list.  */
       assert (literal_section);
-      xtensa_remove_section (literal_section);
-      xtensa_insert_section (NULL, literal_section);
-
+      if (literal_section != stdoutput->sections)
+	{
+	  bfd_section_list_remove (stdoutput, literal_section);
+	  bfd_section_list_prepend (stdoutput, literal_section);
+	}
       head = head->next;
     }
 }
 
 
-void
-xtensa_move_literals ()
+static void mark_literal_frags (seg_list *);
+
+static void
+xtensa_move_literals (void)
 {
   seg_list *segment;
   frchainS *frchain_from, *frchain_to;
@@ -7519,31 +9710,31 @@ xtensa_move_literals ()
 	 prevents us from making a segment with an frchain without any
 	 frags in it.  */
       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
       last_frag = frag_now;
       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
 
-      while (search_frag != frag_now) 
+      while (search_frag != frag_now)
 	{
 	  next_frag = search_frag->fr_next;
 
-	  /* First, move the frag out of the literal section and 
+	  /* First, move the frag out of the literal section and
 	     to the appropriate place.  */
 	  if (search_frag->tc_frag_data.literal_frag)
 	    {
 	      literal_pool = search_frag->tc_frag_data.literal_frag;
 	      assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN);
-	      /* Note that we set this fr_var to be a fix 
-		 chain when we created the literal pool location
-		 as RELAX_LITERAL_POOL_BEGIN.  */
-	      frchain_to = (frchainS *) literal_pool->fr_var;
+	      frchain_to = literal_pool->tc_frag_data.lit_frchain;
+	      assert (frchain_to);
 	    }
 	  insert_after = literal_pool;
-	  
+
 	  while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END)
 	    insert_after = insert_after->fr_next;
 
-	  dest_seg = (segT) insert_after->fr_next->fr_var;
-	  
+	  dest_seg = insert_after->fr_next->tc_frag_data.lit_seg;
+
 	  *frag_splice = next_frag;
 	  search_frag->fr_next = insert_after->fr_next;
 	  insert_after->fr_next = search_frag;
@@ -7588,7 +9779,8 @@ xtensa_move_literals ()
     {
       symbolS *lit_sym = lit->sym;
       segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg;
-      S_SET_SEGMENT (lit_sym, dest_seg);
+      if (dest_seg)
+	S_SET_SEGMENT (lit_sym, dest_seg);
     }
 }
 
@@ -7598,8 +9790,7 @@ xtensa_move_literals ()
    and frag_variant to get called in all situations.  */
 
 static void
-mark_literal_frags (segment)
-     seg_list *segment;
+mark_literal_frags (seg_list *segment)
 {
   frchainS *frchain_from;
   fragS *search_frag;
@@ -7608,7 +9799,7 @@ mark_literal_frags (segment)
     {
       frchain_from = seg_info (segment->seg)->frchainP;
       search_frag = frchain_from->frch_root;
-      while (search_frag) 
+      while (search_frag)
 	{
 	  search_frag->tc_frag_data.is_literal = TRUE;
 	  search_frag = search_frag->fr_next;
@@ -7619,9 +9810,7 @@ mark_literal_frags (segment)
 
 
 static void
-xtensa_reorder_seg_list (head, after)
-     seg_list *head;
-     segT after;
+xtensa_reorder_seg_list (seg_list *head, segT after)
 {
   /* Move all of the sections in the section list to come
      after "after" in the gnu segment list.  */
@@ -7635,8 +9824,8 @@ xtensa_reorder_seg_list (head, after)
       assert (literal_section);
       if (literal_section != after)
 	{
-	  xtensa_remove_section (literal_section);
-	  xtensa_insert_section (after, literal_section);
+	  bfd_section_list_remove (stdoutput, literal_section);
+	  bfd_section_list_insert_after (stdoutput, after, literal_section);
 	}
 
       head = head->next;
@@ -7646,20 +9835,22 @@ xtensa_reorder_seg_list (head, after)
 
 /* Push all the literal segments to the end of the gnu list.  */
 
-void
-xtensa_reorder_segments ()
+static void
+xtensa_reorder_segments (void)
 {
   segT sec;
-  segT last_sec;
+  segT last_sec = 0;
   int old_count = 0;
   int new_count = 0;
 
   for (sec = stdoutput->sections; sec != NULL; sec = sec->next)
-    old_count++;
+    {
+      last_sec = sec;
+      old_count++;
+    }
 
   /* Now that we have the last section, push all the literal
      sections to the end.  */
-  last_sec = get_last_sec ();
   xtensa_reorder_seg_list (literal_head, last_sec);
   xtensa_reorder_seg_list (init_literal_head, last_sec);
   xtensa_reorder_seg_list (fini_literal_head, last_sec);
@@ -7671,24 +9862,31 @@ xtensa_reorder_segments ()
 }
 
 
-segT
-get_last_sec ()
+/* Change the emit state (seg, subseg, and frag related stuff) to the
+   correct location.  Return a emit_state which can be passed to
+   xtensa_restore_emit_state to return to current fragment.  */
+
+static void
+xtensa_switch_to_literal_fragment (emit_state *result)
 {
-  segT last_sec = stdoutput->sections;
-  while (last_sec->next != NULL)
-    last_sec = last_sec->next;
+  if (directive_state[directive_absolute_literals])
+    {
+      cache_literal_section (0, default_lit_sections.lit4_seg_name,
+			     &default_lit_sections.lit4_seg, FALSE);
+      xtensa_switch_section_emit_state (result,
+					default_lit_sections.lit4_seg, 0);
+    }
+  else
+    xtensa_switch_to_non_abs_literal_fragment (result);
 
-  return last_sec;
+  /* Do a 4-byte align here.  */
+  frag_align (2, 0, 0);
+  record_alignment (now_seg, 2);
 }
 
 
-/* Change the emit state (seg, subseg, and frag related stuff) to the
-   correct location.  Return a emit_state which can be passed to
-   xtensa_restore_emit_state to return to current fragment.  */
-
-void
-xtensa_switch_to_literal_fragment (result)
-     emit_state *result;
+static void
+xtensa_switch_to_non_abs_literal_fragment (emit_state *result)
 {
   /* When we mark a literal pool location, we want to put a frag in
      the literal pool that points to it.  But to do that, we want to
@@ -7698,20 +9896,18 @@ xtensa_switch_to_literal_fragment (result)
 
   static bfd_boolean recursive = FALSE;
   fragS *pool_location = get_literal_pool_location (now_seg);
-  bfd_boolean is_init = 
+  bfd_boolean is_init =
     (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME));
 
-  bfd_boolean is_fini = 
+  bfd_boolean is_fini =
     (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME));
-  
 
-  if (pool_location == NULL 
-      && !use_literal_section 
+  if (pool_location == NULL
+      && !use_literal_section
       && !recursive
       && !is_init && ! is_fini)
     {
-      as_warn (_("inlining literal pool; "
-		 "specify location with .literal_position."));
+      as_bad (_("literal pool location required for text-section-literals; specify with .literal_position"));
       recursive = TRUE;
       xtensa_mark_literal_pool_location ();
       recursive = FALSE;
@@ -7725,7 +9921,7 @@ xtensa_switch_to_literal_fragment (result)
     {
       cache_literal_section (init_literal_head,
 			     default_lit_sections.init_lit_seg_name,
-			     &default_lit_sections.init_lit_seg);
+			     &default_lit_sections.init_lit_seg, TRUE);
       xtensa_switch_section_emit_state (result,
 					default_lit_sections.init_lit_seg, 0);
     }
@@ -7733,31 +9929,30 @@ xtensa_switch_to_literal_fragment (result)
     {
       cache_literal_section (fini_literal_head,
 			     default_lit_sections.fini_lit_seg_name,
-			     &default_lit_sections.fini_lit_seg);
+			     &default_lit_sections.fini_lit_seg, TRUE);
       xtensa_switch_section_emit_state (result,
 					default_lit_sections.fini_lit_seg, 0);
     }
-  else 
+  else
     {
       cache_literal_section (literal_head,
 			     default_lit_sections.lit_seg_name,
-			     &default_lit_sections.lit_seg);
+			     &default_lit_sections.lit_seg, TRUE);
       xtensa_switch_section_emit_state (result,
 					default_lit_sections.lit_seg, 0);
     }
 
-  if (!use_literal_section &&
-      !is_init && !is_fini &&
-      get_literal_pool_location (now_seg) != pool_location)
+  if (!use_literal_section
+      && !is_init && !is_fini
+      && get_literal_pool_location (now_seg) != pool_location)
     {
       /* Close whatever frag is there.  */
       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
       frag_now->tc_frag_data.literal_frag = pool_location;
       frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL);
+      xtensa_set_frag_assembly_state (frag_now);
     }
-
-  /* Do a 4 byte align here.  */
-  frag_align (2, 0, 0);
 }
 
 
@@ -7765,29 +9960,27 @@ xtensa_switch_to_literal_fragment (result)
    This is a helper function for xtensa_switch_to_literal_fragment.
    This is similar to a .section new_now_seg subseg. */
 
-void
-xtensa_switch_section_emit_state (state, new_now_seg, new_now_subseg)
-     emit_state *state;
-     segT new_now_seg;
-     subsegT new_now_subseg;
+static void
+xtensa_switch_section_emit_state (emit_state *state,
+				  segT new_now_seg,
+				  subsegT new_now_subseg)
 {
   state->name = now_seg->name;
   state->now_seg = now_seg;
   state->now_subseg = now_subseg;
   state->generating_literals = generating_literals;
   generating_literals++;
-  subseg_new (segment_name (new_now_seg), new_now_subseg);
+  subseg_set (new_now_seg, new_now_subseg);
 }
 
 
 /* Use to restore the emitting into the normal place.  */
 
-void
-xtensa_restore_emit_state (state)
-     emit_state *state;
+static void
+xtensa_restore_emit_state (emit_state *state)
 {
   generating_literals = state->generating_literals;
-  subseg_new (state->name, state->now_subseg);
+  subseg_set (state->now_seg, state->now_subseg);
 }
 
 
@@ -7795,152 +9988,147 @@ xtensa_restore_emit_state (state)
    present, return it; otherwise, create a new one.  */
 
 static void
-cache_literal_section (head, name, seg)
-     seg_list *head;
-     const char *name;
-     segT *seg;
+cache_literal_section (seg_list *head,
+		       const char *name,
+		       segT *pseg,
+		       bfd_boolean is_code)
 {
   segT current_section = now_seg;
   int current_subsec = now_subseg;
+  segT seg;
 
-  if (*seg != 0)
+  if (*pseg != 0)
     return;
-  *seg = retrieve_literal_seg (head, name);
-  subseg_set (current_section, current_subsec);
-}
 
-
-/* Get a segment of a given name.  If the segment is already
-   present, return it; otherwise, create a new one.  */
-
-static segT
-retrieve_literal_seg (head, name)
-     seg_list *head;
-     const char *name;
-{
-  segT ret = 0;
-
-  assert (head);
-
-  ret = seg_present (name);
-  if (!ret)
+  /* Check if the named section exists.  */
+  for (seg = stdoutput->sections; seg; seg = seg->next)
     {
-      ret = subseg_new (name, (subsegT) 0);
-      add_seg_list (head, ret);
-      bfd_set_section_flags (stdoutput, ret, SEC_HAS_CONTENTS |
-			     SEC_READONLY | SEC_ALLOC | SEC_LOAD | SEC_CODE);
-      bfd_set_section_alignment (stdoutput, ret, 2);
+      if (!strcmp (segment_name (seg), name))
+	break;
     }
 
-  return ret;
-}
-
-
-/* Return a segment of a given name if it is present.  */
-
-static segT
-seg_present (name)
-     const char *name;
-{
-  segT seg;
-  seg = stdoutput->sections;
-
-  while (seg)
+  if (!seg)
     {
-      if (!strcmp (segment_name (seg), name))
-	return seg;
-      seg = seg->next;
+      /* Create a new literal section.  */
+      seg = subseg_new (name, (subsegT) 0);
+      if (head)
+	{
+	  /* Add the newly created literal segment to the specified list.  */
+	  seg_list *n = (seg_list *) xmalloc (sizeof (seg_list));
+	  n->seg = seg;
+	  n->next = head->next;
+	  head->next = n;
+	}
+      bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS |
+			     SEC_READONLY | SEC_ALLOC | SEC_LOAD
+			     | (is_code ? SEC_CODE : SEC_DATA));
+      bfd_set_section_alignment (stdoutput, seg, 2);
     }
 
-  return 0;
-}
-
-
-/* Add a segment to a segment list.  */
-
-static void
-add_seg_list (head, seg)
-     seg_list *head;
-     segT seg;
-{
-  seg_list *n;
-  n = (seg_list *) xmalloc (sizeof (seg_list));
-  assert (n);
-
-  n->seg = seg;
-  n->next = head->next;
-  head->next = n;
+  *pseg = seg;
+  subseg_set (current_section, current_subsec);
 }
 
 
-/* Set up Property Tables after Relaxation.  */
+/* Property Tables Stuff.  */
 
 #define XTENSA_INSN_SEC_NAME ".xt.insn"
 #define XTENSA_LIT_SEC_NAME ".xt.lit"
+#define XTENSA_PROP_SEC_NAME ".xt.prop"
+
+typedef bfd_boolean (*frag_predicate) (const fragS *);
+typedef void (*frag_flags_fn) (const fragS *, frag_flags *);
+
+static bfd_boolean get_frag_is_literal (const fragS *);
+static void xtensa_create_property_segments
+  (frag_predicate, frag_predicate, const char *, xt_section_type);
+static void xtensa_create_xproperty_segments
+  (frag_flags_fn, const char *, xt_section_type);
+static segment_info_type *retrieve_segment_info (segT);
+static segT retrieve_xtensa_section (char *);
+static bfd_boolean section_has_property (segT, frag_predicate);
+static bfd_boolean section_has_xproperty (segT, frag_flags_fn);
+static void add_xt_block_frags
+  (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate);
+static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *);
+static void xtensa_frag_flags_init (frag_flags *);
+static void get_frag_property_flags (const fragS *, frag_flags *);
+static bfd_vma frag_flags_to_number (const frag_flags *);
+static void add_xt_prop_frags
+  (segT, segT, xtensa_block_info **, frag_flags_fn);
+
+/* Set up property tables after relaxation.  */
 
 void
-xtensa_post_relax_hook ()
+xtensa_post_relax_hook (void)
 {
   xtensa_move_seg_list_to_beginning (literal_head);
   xtensa_move_seg_list_to_beginning (init_literal_head);
   xtensa_move_seg_list_to_beginning (fini_literal_head);
 
-  xtensa_create_property_segments (get_frag_is_insn,
-				   XTENSA_INSN_SEC_NAME,
-				   xt_insn_sec);
+  xtensa_find_unmarked_state_frags ();
+
   xtensa_create_property_segments (get_frag_is_literal,
+				   NULL,
 				   XTENSA_LIT_SEC_NAME,
 				   xt_literal_sec);
+  xtensa_create_xproperty_segments (get_frag_property_flags,
+				    XTENSA_PROP_SEC_NAME,
+				    xt_prop_sec);
+
+  if (warn_unaligned_branch_targets)
+    bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0);
+  bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0);
 }
 
 
-static bfd_boolean
-get_frag_is_literal (fragP)
-     const fragS *fragP;
-{
-  assert (fragP != NULL);
-  return (fragP->tc_frag_data.is_literal);
-}
- 
+/* This function is only meaningful after xtensa_move_literals.  */
 
 static bfd_boolean
-get_frag_is_insn (fragP)
-     const fragS *fragP;
+get_frag_is_literal (const fragS *fragP)
 {
   assert (fragP != NULL);
-  return (fragP->tc_frag_data.is_insn);
+  return fragP->tc_frag_data.is_literal;
 }
 
 
 static void
-xtensa_create_property_segments (property_function, section_name_base, 
-				 sec_type)
-     frag_predicate property_function;
-     const char * section_name_base;
-     xt_section_type sec_type;
+xtensa_create_property_segments (frag_predicate property_function,
+				 frag_predicate end_property_function,
+				 const char *section_name_base,
+				 xt_section_type sec_type)
 {
   segT *seclist;
 
   /* Walk over all of the current segments.
      Walk over each fragment
-      For each fragment that has instructions
-      Build an instruction record (append where possible).  */
+     For each non-empty fragment,
+     Build a property record (append where possible).  */
 
   for (seclist = &stdoutput->sections;
        seclist && *seclist;
        seclist = &(*seclist)->next)
     {
       segT sec = *seclist;
+      flagword flags;
+
+      flags = bfd_get_section_flags (stdoutput, sec);
+      if (flags & SEC_DEBUGGING)
+	continue;
+      if (!(flags & SEC_ALLOC))
+	continue;
+
       if (section_has_property (sec, property_function))
 	{
 	  char *property_section_name =
 	    xtensa_get_property_section_name (sec, section_name_base);
 	  segT insn_sec = retrieve_xtensa_section (property_section_name);
 	  segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
-	  xtensa_block_info **xt_blocks = 
+	  xtensa_block_info **xt_blocks =
 	    &xt_seg_info->tc_segment_info_data.blocks[sec_type];
 	  /* Walk over all of the frchains here and add new sections.  */
-	  add_xt_block_frags (sec, insn_sec, xt_blocks, property_function);
+	  add_xt_block_frags (sec, insn_sec, xt_blocks, property_function,
+			      end_property_function);
 	}
     }
 
@@ -7953,6 +10141,7 @@ xtensa_create_property_segments (property_function, section_name_base,
       segment_info_type *seginfo;
       xtensa_block_info *block;
       segT sec = *seclist;
+
       seginfo = seg_info (sec);
       block = seginfo->tc_segment_info_data.blocks[sec_type];
 
@@ -7960,8 +10149,8 @@ xtensa_create_property_segments (property_function, section_name_base,
 	{
 	  xtensa_block_info *cur_block;
 	  /* This is a section with some data.  */
-	  size_t num_recs = 0;
-	  size_t rec_size;
+	  int num_recs = 0;
+	  bfd_size_type rec_size;
 
 	  for (cur_block = block; cur_block; cur_block = cur_block->next)
 	    num_recs++;
@@ -7978,10 +10167,10 @@ xtensa_create_property_segments (property_function, section_name_base,
 	    {
 	      /* Allocate a fragment and leak it.  */
 	      fragS *fragP;
-	      size_t frag_size;
+	      bfd_size_type frag_size;
 	      fixS *fixes;
 	      frchainS *frchainP;
-	      size_t i;
+	      int i;
 	      char *frag_data;
 
 	      frag_size = sizeof (fragS) + rec_size;
@@ -7993,7 +10182,7 @@ xtensa_create_property_segments (property_function, section_name_base,
 	      fragP->fr_fix = rec_size;
 	      fragP->fr_var = 0;
 	      fragP->fr_type = rs_fill;
-	      /* the rest are zeros */
+	      /* The rest are zeros.  */
 
 	      frchainP = seginfo->frchainP;
 	      frchainP->frch_root = fragP;
@@ -8037,9 +10226,144 @@ xtensa_create_property_segments (property_function, section_name_base,
 }
 
 
-segment_info_type *
-retrieve_segment_info (seg)
-     segT seg;
+static void
+xtensa_create_xproperty_segments (frag_flags_fn flag_fn,
+				  const char *section_name_base,
+				  xt_section_type sec_type)
+{
+  segT *seclist;
+
+  /* Walk over all of the current segments.
+     Walk over each fragment.
+     For each fragment that has instructions,
+     build an instruction record (append where possible).  */
+
+  for (seclist = &stdoutput->sections;
+       seclist && *seclist;
+       seclist = &(*seclist)->next)
+    {
+      segT sec = *seclist;
+      flagword flags;
+
+      flags = bfd_get_section_flags (stdoutput, sec);
+      if ((flags & SEC_DEBUGGING)
+	  || !(flags & SEC_ALLOC)
+	  || (flags & SEC_MERGE))
+	continue;
+
+      if (section_has_xproperty (sec, flag_fn))
+	{
+	  char *property_section_name =
+	    xtensa_get_property_section_name (sec, section_name_base);
+	  segT insn_sec = retrieve_xtensa_section (property_section_name);
+	  segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec);
+	  xtensa_block_info **xt_blocks =
+	    &xt_seg_info->tc_segment_info_data.blocks[sec_type];
+	  /* Walk over all of the frchains here and add new sections.  */
+	  add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn);
+	}
+    }
+
+  /* Now we fill them out....  */
+
+  for (seclist = &stdoutput->sections;
+       seclist && *seclist;
+       seclist = &(*seclist)->next)
+    {
+      segment_info_type *seginfo;
+      xtensa_block_info *block;
+      segT sec = *seclist;
+
+      seginfo = seg_info (sec);
+      block = seginfo->tc_segment_info_data.blocks[sec_type];
+
+      if (block)
+	{
+	  xtensa_block_info *cur_block;
+	  /* This is a section with some data.  */
+	  int num_recs = 0;
+	  bfd_size_type rec_size;
+
+	  for (cur_block = block; cur_block; cur_block = cur_block->next)
+	    num_recs++;
+
+	  rec_size = num_recs * (8 + 4);
+	  bfd_set_section_size (stdoutput, sec, rec_size);
+
+	  /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */
+
+	  /* In order to make this work with the assembler, we have to build
+	     some frags then build the "fixups" for it.  It would be easier to
+	     just set the contents then set the arlents.  */
+
+	  if (num_recs)
+	    {
+	      /* Allocate a fragment and (unfortunately) leak it.  */
+	      fragS *fragP;
+	      bfd_size_type frag_size;
+	      fixS *fixes;
+	      frchainS *frchainP;
+	      int i;
+	      char *frag_data;
+
+	      frag_size = sizeof (fragS) + rec_size;
+	      fragP = (fragS *) xmalloc (frag_size);
+
+	      memset (fragP, 0, frag_size);
+	      fragP->fr_address = 0;
+	      fragP->fr_next = NULL;
+	      fragP->fr_fix = rec_size;
+	      fragP->fr_var = 0;
+	      fragP->fr_type = rs_fill;
+	      /* The rest are zeros.  */
+
+	      frchainP = seginfo->frchainP;
+	      frchainP->frch_root = fragP;
+	      frchainP->frch_last = fragP;
+
+	      fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs);
+	      memset (fixes, 0, sizeof (fixS) * num_recs);
+
+	      seginfo->fix_root = fixes;
+	      seginfo->fix_tail = &fixes[num_recs - 1];
+	      cur_block = block;
+	      frag_data = &fragP->fr_literal[0];
+	      for (i = 0; i < num_recs; i++)
+		{
+		  fixS *fix = &fixes[i];
+		  assert (cur_block);
+
+		  /* Write the fixup.  */
+		  if (i != num_recs - 1)
+		    fix->fx_next = &fixes[i + 1];
+		  else
+		    fix->fx_next = NULL;
+		  fix->fx_size = 4;
+		  fix->fx_done = 0;
+		  fix->fx_frag = fragP;
+		  fix->fx_where = i * (8 + 4);
+		  fix->fx_addsy = section_symbol (cur_block->sec);
+		  fix->fx_offset = cur_block->offset;
+		  fix->fx_r_type = BFD_RELOC_32;
+		  fix->fx_file = "Internal Assembly";
+		  fix->fx_line = 0;
+
+		  /* Write the length.  */
+		  md_number_to_chars (&frag_data[4 + (8+4) * i],
+				      cur_block->size, 4);
+		  md_number_to_chars (&frag_data[8 + (8+4) * i],
+				      frag_flags_to_number (&cur_block->flags),
+				      4);
+		  cur_block = cur_block->next;
+		}
+	    }
+	}
+    }
+}
+
+
+static segment_info_type *
+retrieve_segment_info (segT seg)
 {
   segment_info_type *seginfo;
   seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
@@ -8048,24 +10372,13 @@ retrieve_segment_info (seg)
       frchainS *frchainP;
 
       seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-      memset ((PTR) seginfo, 0, sizeof (*seginfo));
+      memset ((void *) seginfo, 0, sizeof (*seginfo));
       seginfo->fix_root = NULL;
       seginfo->fix_tail = NULL;
       seginfo->bfd_section = seg;
       seginfo->sym = 0;
       /* We will not be dealing with these, only our special ones.  */
-#if 0
-      if (seg == bfd_abs_section_ptr)
-	abs_seg_info = seginfo;
-      else if (seg == bfd_und_section_ptr)
-	und_seg_info = seginfo;
-      else
-#endif
-	bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
-#if 0
-      seg_fix_rootP = &segment_info[seg].fix_root;
-      seg_fix_tailP = &segment_info[seg].fix_tail;
-#endif
+      bfd_set_section_userdata (stdoutput, seg, (void *) seginfo);
 
       frchainP = (frchainS *) xmalloc (sizeof (frchainS));
       frchainP->frch_root = NULL;
@@ -8087,9 +10400,8 @@ retrieve_segment_info (seg)
 }
 
 
-segT
-retrieve_xtensa_section (sec_name)
-     char *sec_name;
+static segT
+retrieve_xtensa_section (char *sec_name)
 {
   bfd *abfd = stdoutput;
   flagword flags, out_flags, link_once_flags;
@@ -8111,10 +10423,8 @@ retrieve_xtensa_section (sec_name)
 }
 
 
-bfd_boolean
-section_has_property (sec, property_function)
-     segT sec;
-     frag_predicate property_function;
+static bfd_boolean
+section_has_property (segT sec, frag_predicate property_function)
 {
   segment_info_type *seginfo = seg_info (sec);
   fragS *fragP;
@@ -8132,14 +10442,34 @@ section_has_property (sec, property_function)
 }
 
 
+static bfd_boolean
+section_has_xproperty (segT sec, frag_flags_fn property_function)
+{
+  segment_info_type *seginfo = seg_info (sec);
+  fragS *fragP;
+
+  if (seginfo && seginfo->frchainP)
+    {
+      for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next)
+	{
+	  frag_flags prop_flags;
+	  property_function (fragP, &prop_flags);
+	  if (!xtensa_frag_flags_is_empty (&prop_flags))
+	    return TRUE;
+	}
+    }
+  return FALSE;
+}
+
+
 /* Two types of block sections exist right now: literal and insns.  */
 
-void
-add_xt_block_frags (sec, xt_block_sec, xt_block, property_function)
-     segT sec;
-     segT xt_block_sec;
-     xtensa_block_info **xt_block;
-     frag_predicate property_function;
+static void
+add_xt_block_frags (segT sec,
+		    segT xt_block_sec,
+		    xtensa_block_info **xt_block,
+		    frag_predicate property_function,
+		    frag_predicate end_property_function)
 {
   segment_info_type *seg_info;
   segment_info_type *xt_seg_info;
@@ -8182,19 +10512,369 @@ add_xt_block_frags (sec, xt_block_sec, xt_block, property_function)
 		  new_block->offset = fragP->fr_address;
 		  new_block->size = fragP->fr_fix;
 		  new_block->next = NULL;
+		  xtensa_frag_flags_init (&new_block->flags);
 		  *xt_block = new_block;
 		}
+	      if (end_property_function
+		  && end_property_function (fragP))
+		{
+		  xt_block = &((*xt_block)->next);
+		}
+	    }
+	}
+    }
+}
+
+
+/* Break the encapsulation of add_xt_prop_frags here.  */
+
+static bfd_boolean
+xtensa_frag_flags_is_empty (const frag_flags *prop_flags)
+{
+  if (prop_flags->is_literal
+      || prop_flags->is_insn
+      || prop_flags->is_data
+      || prop_flags->is_unreachable)
+    return FALSE;
+  return TRUE;
+}
+
+
+static void
+xtensa_frag_flags_init (frag_flags *prop_flags)
+{
+  memset (prop_flags, 0, sizeof (frag_flags));
+}
+
+
+static void
+get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags)
+{
+  xtensa_frag_flags_init (prop_flags);
+  if (fragP->tc_frag_data.is_literal)
+    prop_flags->is_literal = TRUE;
+  if (fragP->tc_frag_data.is_unreachable)
+    prop_flags->is_unreachable = TRUE;
+  else if (fragP->tc_frag_data.is_insn)
+    {
+      prop_flags->is_insn = TRUE;
+      if (fragP->tc_frag_data.is_loop_target)
+	prop_flags->insn.is_loop_target = TRUE;
+      if (fragP->tc_frag_data.is_branch_target)
+	prop_flags->insn.is_branch_target = TRUE;
+      if (fragP->tc_frag_data.is_specific_opcode
+	  || fragP->tc_frag_data.is_no_transform)
+	prop_flags->insn.is_no_transform = TRUE;
+      if (fragP->tc_frag_data.is_no_density)
+	prop_flags->insn.is_no_density = TRUE;
+      if (fragP->tc_frag_data.use_absolute_literals)
+	prop_flags->insn.is_abslit = TRUE;
+    }
+  if (fragP->tc_frag_data.is_align)
+    {
+      prop_flags->is_align = TRUE;
+      prop_flags->alignment = fragP->tc_frag_data.alignment;
+      if (xtensa_frag_flags_is_empty (prop_flags))
+	prop_flags->is_data = TRUE;
+    }
+}
+
+
+static bfd_vma
+frag_flags_to_number (const frag_flags *prop_flags)
+{
+  bfd_vma num = 0;
+  if (prop_flags->is_literal)
+    num |= XTENSA_PROP_LITERAL;
+  if (prop_flags->is_insn)
+    num |= XTENSA_PROP_INSN;
+  if (prop_flags->is_data)
+    num |= XTENSA_PROP_DATA;
+  if (prop_flags->is_unreachable)
+    num |= XTENSA_PROP_UNREACHABLE;
+  if (prop_flags->insn.is_loop_target)
+    num |= XTENSA_PROP_INSN_LOOP_TARGET;
+  if (prop_flags->insn.is_branch_target)
+    {
+      num |= XTENSA_PROP_INSN_BRANCH_TARGET;
+      num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority);
+    }
+
+  if (prop_flags->insn.is_no_density)
+    num |= XTENSA_PROP_INSN_NO_DENSITY;
+  if (prop_flags->insn.is_no_transform)
+    num |= XTENSA_PROP_INSN_NO_TRANSFORM;
+  if (prop_flags->insn.is_no_reorder)
+    num |= XTENSA_PROP_INSN_NO_REORDER;
+  if (prop_flags->insn.is_abslit)
+    num |= XTENSA_PROP_INSN_ABSLIT;
+
+  if (prop_flags->is_align)
+    {
+      num |= XTENSA_PROP_ALIGN;
+      num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment);
+    }
+
+  return num;
+}
+
+
+static bfd_boolean
+xtensa_frag_flags_combinable (const frag_flags *prop_flags_1,
+			      const frag_flags *prop_flags_2)
+{
+  /* Cannot combine with an end marker.  */
+
+  if (prop_flags_1->is_literal != prop_flags_2->is_literal)
+    return FALSE;
+  if (prop_flags_1->is_insn != prop_flags_2->is_insn)
+    return FALSE;
+  if (prop_flags_1->is_data != prop_flags_2->is_data)
+    return FALSE;
+
+  if (prop_flags_1->is_insn)
+    {
+      /* Properties of the beginning of the frag.  */
+      if (prop_flags_2->insn.is_loop_target)
+	return FALSE;
+      if (prop_flags_2->insn.is_branch_target)
+	return FALSE;
+      if (prop_flags_1->insn.is_no_density !=
+	  prop_flags_2->insn.is_no_density)
+	return FALSE;
+      if (prop_flags_1->insn.is_no_transform !=
+	  prop_flags_2->insn.is_no_transform)
+	return FALSE;
+      if (prop_flags_1->insn.is_no_reorder !=
+	  prop_flags_2->insn.is_no_reorder)
+	return FALSE;
+      if (prop_flags_1->insn.is_abslit !=
+	  prop_flags_2->insn.is_abslit)
+	return FALSE;
+    }
+
+  if (prop_flags_1->is_align)
+    return FALSE;
+
+  return TRUE;
+}
+
+
+static bfd_vma
+xt_block_aligned_size (const xtensa_block_info *xt_block)
+{
+  bfd_vma end_addr;
+  unsigned align_bits;
+
+  if (!xt_block->flags.is_align)
+    return xt_block->size;
+
+  end_addr = xt_block->offset + xt_block->size;
+  align_bits = xt_block->flags.alignment;
+  end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits;
+  return end_addr - xt_block->offset;
+}
+
+
+static bfd_boolean
+xtensa_xt_block_combine (xtensa_block_info *xt_block,
+			 const xtensa_block_info *xt_block_2)
+{
+  if (xt_block->sec != xt_block_2->sec)
+    return FALSE;
+  if (xt_block->offset + xt_block_aligned_size (xt_block)
+      != xt_block_2->offset)
+    return FALSE;
+
+  if (xt_block_2->size == 0
+      && (!xt_block_2->flags.is_unreachable
+	  || xt_block->flags.is_unreachable))
+    {
+      if (xt_block_2->flags.is_align
+	  && xt_block->flags.is_align)
+	{
+	  /* Nothing needed.  */
+	  if (xt_block->flags.alignment >= xt_block_2->flags.alignment)
+	    return TRUE;
+	}
+      else
+	{
+	  if (xt_block_2->flags.is_align)
+	    {
+	      /* Push alignment to previous entry.  */
+	      xt_block->flags.is_align = xt_block_2->flags.is_align;
+	      xt_block->flags.alignment = xt_block_2->flags.alignment;
+	    }
+	  return TRUE;
+	}
+    }
+  if (!xtensa_frag_flags_combinable (&xt_block->flags,
+				     &xt_block_2->flags))
+    return FALSE;
+
+  xt_block->size += xt_block_2->size;
+
+  if (xt_block_2->flags.is_align)
+    {
+      xt_block->flags.is_align = TRUE;
+      xt_block->flags.alignment = xt_block_2->flags.alignment;
+    }
+
+  return TRUE;
+}
+
+
+static void
+add_xt_prop_frags (segT sec,
+		   segT xt_block_sec,
+		   xtensa_block_info **xt_block,
+		   frag_flags_fn property_function)
+{
+  segment_info_type *seg_info;
+  segment_info_type *xt_seg_info;
+  bfd_vma seg_offset;
+  fragS *fragP;
+
+  xt_seg_info = retrieve_segment_info (xt_block_sec);
+  seg_info = retrieve_segment_info (sec);
+  /* Build it if needed.  */
+  while (*xt_block != NULL)
+    {
+      xt_block = &(*xt_block)->next;
+    }
+  /* We are either at NULL at the beginning or at the end.  */
+
+  /* Walk through the frags.  */
+  seg_offset = 0;
+
+  if (seg_info->frchainP)
+    {
+      for (fragP = seg_info->frchainP->frch_root; fragP;
+	   fragP = fragP->fr_next)
+	{
+	  xtensa_block_info tmp_block;
+	  tmp_block.sec = sec;
+	  tmp_block.offset = fragP->fr_address;
+	  tmp_block.size = fragP->fr_fix;
+	  tmp_block.next = NULL;
+	  property_function (fragP, &tmp_block.flags);
+
+	  if (!xtensa_frag_flags_is_empty (&tmp_block.flags))
+	    /* && fragP->fr_fix != 0) */
+	    {
+	      if ((*xt_block) == NULL
+		  || !xtensa_xt_block_combine (*xt_block, &tmp_block))
+		{
+		  xtensa_block_info *new_block;
+		  if ((*xt_block) != NULL)
+		    xt_block = &(*xt_block)->next;
+		  new_block = (xtensa_block_info *)
+		    xmalloc (sizeof (xtensa_block_info));
+		  *new_block = tmp_block;
+		  *xt_block = new_block;
+		}
+	    }
+	}
+    }
+}
+
+
+/* op_placement_info_table */
+
+/* op_placement_info makes it easier to determine which
+   ops can go in which slots.  */
+
+static void
+init_op_placement_info_table (void)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa);
+  xtensa_opcode opcode;
+  xtensa_format fmt;
+  int slot;
+  int num_opcodes = xtensa_isa_num_opcodes (isa);
+
+  op_placement_table = (op_placement_info_table)
+    xmalloc (sizeof (op_placement_info) * num_opcodes);
+  assert (xtensa_isa_num_formats (isa) < MAX_FORMATS);
+
+  for (opcode = 0; opcode < num_opcodes; opcode++)
+    {
+      op_placement_info *opi = &op_placement_table[opcode];
+      /* FIXME: Make tinsn allocation dynamic.  */
+      if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS)
+	as_fatal (_("too many operands in instruction"));
+      opi->narrowest = XTENSA_UNDEFINED;
+      opi->narrowest_size = 0x7F;
+      opi->narrowest_slot = 0;
+      opi->formats = 0;
+      opi->num_formats = 0;
+      opi->issuef = 0;
+      for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++)
+	{
+	  opi->slots[fmt] = 0;
+	  for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++)
+	    {
+	      if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0)
+		{
+		  int fmt_length = xtensa_format_length (isa, fmt);
+		  opi->issuef++;
+		  set_bit (fmt, opi->formats);
+		  set_bit (slot, opi->slots[fmt]);
+		  if (fmt_length < opi->narrowest_size
+		      || (fmt_length == opi->narrowest_size
+			  && (xtensa_format_num_slots (isa, fmt)
+			      < xtensa_format_num_slots (isa,
+							 opi->narrowest))))
+		    {
+		      opi->narrowest = fmt;
+		      opi->narrowest_size = fmt_length;
+		      opi->narrowest_slot = slot;
+		    }
+		}
 	    }
+	  if (opi->formats)
+	    opi->num_formats++;
 	}
     }
+  xtensa_insnbuf_free (isa, ibuf);
+}
+
+
+bfd_boolean
+opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot)
+{
+  return bit_is_set (slot, op_placement_table[opcode].slots[fmt]);
+}
+
+
+/* If the opcode is available in a single slot format, return its size.  */
+
+static int
+xg_get_single_size (xtensa_opcode opcode)
+{
+  return op_placement_table[opcode].narrowest_size;
+}
+
+
+static xtensa_format
+xg_get_single_format (xtensa_opcode opcode)
+{
+  return op_placement_table[opcode].narrowest;
+}
+
+
+static int
+xg_get_single_slot (xtensa_opcode opcode)
+{
+  return op_placement_table[opcode].narrowest_slot;
 }
 
 
 /* Instruction Stack Functions (from "xtensa-istack.h").  */
 
 void
-istack_init (stack)
-     IStack *stack;
+istack_init (IStack *stack)
 {
   memset (stack, 0, sizeof (IStack));
   stack->ninsn = 0;
@@ -8202,27 +10882,24 @@ istack_init (stack)
 
 
 bfd_boolean
-istack_empty (stack)
-     IStack *stack;
+istack_empty (IStack *stack)
 {
   return (stack->ninsn == 0);
 }
 
 
 bfd_boolean
-istack_full (stack)
-     IStack *stack;
+istack_full (IStack *stack)
 {
   return (stack->ninsn == MAX_ISTACK);
 }
 
 
 /* Return a pointer to the top IStack entry.
-   It is an error to call this if istack_empty () is true. */
+   It is an error to call this if istack_empty () is TRUE. */
 
 TInsn *
-istack_top (stack)
-     IStack *stack;
+istack_top (IStack *stack)
 {
   int rec = stack->ninsn - 1;
   assert (!istack_empty (stack));
@@ -8231,26 +10908,23 @@ istack_top (stack)
 
 
 /* Add a new TInsn to an IStack.
-   It is an error to call this if istack_full () is true.  */
+   It is an error to call this if istack_full () is TRUE.  */
 
 void
-istack_push (stack, insn)
-     IStack *stack;
-     TInsn *insn;
+istack_push (IStack *stack, TInsn *insn)
 {
   int rec = stack->ninsn;
   assert (!istack_full (stack));
-  tinsn_copy (&stack->insn[rec], insn);
+  stack->insn[rec] = *insn;
   stack->ninsn++;
 }
 
 
 /* Clear space for the next TInsn on the IStack and return a pointer
-   to it.  It is an error to call this if istack_full () is true.  */
+   to it.  It is an error to call this if istack_full () is TRUE.  */
 
 TInsn *
-istack_push_space (stack)
-     IStack *stack;
+istack_push_space (IStack *stack)
 {
   int rec = stack->ninsn;
   TInsn *insn;
@@ -8263,11 +10937,10 @@ istack_push_space (stack)
 
 
 /* Remove the last pushed instruction.  It is an error to call this if
-   istack_empty () returns true.  */
+   istack_empty () returns TRUE.  */
 
 void
-istack_pop (stack)
-     IStack *stack;
+istack_pop (IStack *stack)
 {
   int rec = stack->ninsn - 1;
   assert (!istack_empty (stack));
@@ -8279,41 +10952,27 @@ istack_pop (stack)
 /* TInsn functions.  */
 
 void
-tinsn_init (dst)
-     TInsn *dst;
+tinsn_init (TInsn *dst)
 {
   memset (dst, 0, sizeof (TInsn));
 }
 
 
-void
-tinsn_copy (dst, src)
-     TInsn *dst;
-     const TInsn *src;
-{
-  tinsn_init (dst);
-  memcpy (dst, src, sizeof (TInsn));
-}
-
-
 /* Get the ``num''th token of the TInsn.
    It is illegal to call this if num > insn->ntoks.  */
 
 expressionS *
-tinsn_get_tok (insn, num)
-     TInsn *insn;
-     int num;
+tinsn_get_tok (TInsn *insn, int num)
 {
   assert (num < insn->ntok);
   return &insn->tok[num];
 }
 
 
-/* Return true if ANY of the operands in the insn are symbolic.  */
+/* Return TRUE if ANY of the operands in the insn are symbolic.  */
 
 static bfd_boolean
-tinsn_has_symbolic_operands (insn)
-     const TInsn *insn;
+tinsn_has_symbolic_operands (const TInsn *insn)
 {
   int i;
   int n = insn->ntok;
@@ -8336,9 +10995,9 @@ tinsn_has_symbolic_operands (insn)
 
 
 bfd_boolean
-tinsn_has_invalid_symbolic_operands (insn)
-     const TInsn *insn;
+tinsn_has_invalid_symbolic_operands (const TInsn *insn)
 {
+  xtensa_isa isa = xtensa_default_isa;
   int i;
   int n = insn->ntok;
 
@@ -8351,12 +11010,24 @@ tinsn_has_invalid_symbolic_operands (insn)
 	case O_register:
 	case O_constant:
 	  break;
+	case O_big:
+	case O_illegal:
+	case O_absent:
+	  /* Errors for these types are caught later.  */
+	  break;
+	case O_hi16:
+	case O_lo16:
 	default:
-	  if (i == get_relaxable_immed (insn->opcode))
-	    break;
-	  as_bad (_("invalid symbolic operand %d on '%s'"),
-		  i, xtensa_opcode_name (xtensa_default_isa, insn->opcode));
-	  return TRUE;
+	  /* Symbolic immediates are only allowed on the last immediate
+	     operand.  At this time, CONST16 is the only opcode where we
+	     support non-PC-relative relocations.  */
+	  if (i != get_relaxable_immed (insn->opcode)
+	      || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1
+		  && insn->opcode != xtensa_const16_opcode))
+	    {
+	      as_bad (_("invalid symbolic operand"));
+	      return TRUE;
+	    }
 	}
     }
   return FALSE;
@@ -8370,8 +11041,7 @@ tinsn_has_invalid_symbolic_operands (insn)
    boil down to SYMBOL + OFFSET.  */
 
 static bfd_boolean
-tinsn_has_complex_operands (insn)
-     const TInsn *insn;
+tinsn_has_complex_operands (const TInsn *insn)
 {
   int i;
   int n = insn->ntok;
@@ -8383,6 +11053,8 @@ tinsn_has_complex_operands (insn)
 	case O_register:
 	case O_constant:
 	case O_symbol:
+	case O_lo16:
+	case O_hi16:
 	  break;
 	default:
 	  return TRUE;
@@ -8392,73 +11064,122 @@ tinsn_has_complex_operands (insn)
 }
 
 
-/* Convert the constant operands in the t_insn to insnbuf.
-   Return true if there is a symbol in the immediate field.
-
-   Before this is called, 
-   1) the number of operands are correct
-   2) the t_insn is a ITYPE_INSN
-   3) ONLY the relaxable_ is built
-   4) All operands are O_constant, O_symbol.  All constants fit
-   The return value tells whether there are any remaining O_symbols.  */
+/* Encode a TInsn opcode and its constant operands into slotbuf.
+   Return TRUE if there is a symbol in the immediate field.  This
+   function assumes that:
+   1) The number of operands are correct.
+   2) The insn_type is ITYPE_INSN.
+   3) The opcode can be encoded in the specified format and slot.
+   4) Operands are either O_constant or O_symbol, and all constants fit.  */
 
 static bfd_boolean
-tinsn_to_insnbuf (t_insn, insnbuf)
-     TInsn *t_insn;
-     xtensa_insnbuf insnbuf;
+tinsn_to_slotbuf (xtensa_format fmt,
+		  int slot,
+		  TInsn *tinsn,
+		  xtensa_insnbuf slotbuf)
 {
   xtensa_isa isa = xtensa_default_isa;
-  xtensa_opcode opcode = t_insn->opcode;
+  xtensa_opcode opcode = tinsn->opcode;
   bfd_boolean has_fixup = FALSE;
-  int noperands = xtensa_num_operands (isa, opcode);
+  int noperands = xtensa_opcode_num_operands (isa, opcode);
   int i;
-  uint32 opnd_value;
-  char *file_name;
-  int line;
 
-  assert (t_insn->insn_type == ITYPE_INSN);
-  if (noperands != t_insn->ntok)
+  assert (tinsn->insn_type == ITYPE_INSN);
+  if (noperands != tinsn->ntok)
     as_fatal (_("operand number mismatch"));
 
-  xtensa_encode_insn (isa, opcode, insnbuf);
+  if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode))
+    {
+      as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""),
+	      xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt));
+      return FALSE;
+    }
 
-  for (i = 0; i < noperands; ++i)
+  for (i = 0; i < noperands; i++)
     {
-      expressionS *expr = &t_insn->tok[i];
-      xtensa_operand operand = xtensa_get_operand (isa, opcode, i);
+      expressionS *expr = &tinsn->tok[i];
+      int rc;
+      unsigned line;
+      char *file_name;
+      uint32 opnd_value;
+
       switch (expr->X_op)
 	{
 	case O_register:
-	  /* The register number has already been checked in  
+	  if (xtensa_operand_is_visible (isa, opcode, i) == 0)
+	    break;
+	  /* The register number has already been checked in
 	     expression_maybe_register, so we don't need to check here.  */
 	  opnd_value = expr->X_add_number;
-	  (void) xtensa_operand_encode (operand, &opnd_value);
-	  xtensa_operand_set_field (operand, insnbuf, opnd_value);
+	  (void) xtensa_operand_encode (isa, opcode, i, &opnd_value);
+	  rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf,
+					 opnd_value);
+	  if (rc != 0)
+	    as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa));
 	  break;
 
 	case O_constant:
+	  if (xtensa_operand_is_visible (isa, opcode, i) == 0)
+	    break;
 	  as_where (&file_name, &line);
-	  /* It is a constant and we called this function,
+	  /* It is a constant and we called this function
 	     then we have to try to fit it.  */
-	  xtensa_insnbuf_set_operand (insnbuf, opcode, operand,
+	  xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i,
 				      expr->X_add_number, file_name, line);
 	  break;
 
-	case O_symbol:
 	default:
 	  has_fixup = TRUE;
 	  break;
 	}
     }
+
   return has_fixup;
 }
 
 
-/* Check the instruction arguments.  Return true on failure.  */
+/* Encode a single TInsn into an insnbuf.  If the opcode can only be encoded
+   into a multi-slot instruction, fill the other slots with NOPs.
+   Return TRUE if there is a symbol in the immediate field.  See also the
+   assumptions listed for tinsn_to_slotbuf.  */
 
-bfd_boolean
-tinsn_check_arguments (insn)
-     const TInsn *insn;
+static bfd_boolean
+tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf)
+{
+  static xtensa_insnbuf slotbuf = 0;
+  static vliw_insn vinsn;
+  xtensa_isa isa = xtensa_default_isa;
+  bfd_boolean has_fixup = FALSE;
+  int i;
+
+  if (!slotbuf)
+    {
+      slotbuf = xtensa_insnbuf_alloc (isa);
+      xg_init_vinsn (&vinsn);
+    }
+
+  xg_clear_vinsn (&vinsn);
+
+  bundle_tinsn (tinsn, &vinsn);
+
+  xtensa_format_encode (isa, vinsn.format, insnbuf);
+
+  for (i = 0; i < vinsn.num_slots; i++)
+    {
+      /* Only one slot may have a fix-up because the rest contains NOPs.  */
+      has_fixup |=
+	tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]);
+      xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]);
+    }
+
+  return has_fixup;
+}
+
+
+/* Check the instruction arguments.  Return TRUE on failure.  */
+
+static bfd_boolean
+tinsn_check_arguments (const TInsn *insn)
 {
   xtensa_isa isa = xtensa_default_isa;
   xtensa_opcode opcode = insn->opcode;
@@ -8469,13 +11190,13 @@ tinsn_check_arguments (insn)
       return TRUE;
     }
 
-  if (xtensa_num_operands (isa, opcode) > insn->ntok)
+  if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok)
     {
       as_bad (_("too few operands"));
       return TRUE;
     }
 
-  if (xtensa_num_operands (isa, opcode) < insn->ntok)
+  if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok)
     {
       as_bad (_("too many operands"));
       return TRUE;
@@ -8487,31 +11208,38 @@ tinsn_check_arguments (insn)
 /* Load an instruction from its encoded form.  */
 
 static void
-tinsn_from_chars (t_insn, f)
-     TInsn *t_insn;
-     char *f;
+tinsn_from_chars (TInsn *tinsn, char *f, int slot)
 {
-  static xtensa_insnbuf insnbuf = NULL;
-  int i;
-  xtensa_opcode opcode;
-  xtensa_isa isa = xtensa_default_isa;
+  vliw_insn vinsn;
 
-  if (!insnbuf)
-    insnbuf = xtensa_insnbuf_alloc (isa);
+  xg_init_vinsn (&vinsn);
+  vinsn_from_chars (&vinsn, f);
 
-  xtensa_insnbuf_from_chars (isa, insnbuf, f);
-  opcode = xtensa_decode_insn (isa, insnbuf);
+  *tinsn = vinsn.slots[slot];
+  xg_free_vinsn (&vinsn);
+}
+
+
+static void
+tinsn_from_insnbuf (TInsn *tinsn,
+		    xtensa_insnbuf slotbuf,
+		    xtensa_format fmt,
+		    int slot)
+{
+  int i;
+  xtensa_isa isa = xtensa_default_isa;
 
   /* Find the immed.  */
-  tinsn_init (t_insn);
-  t_insn->insn_type = ITYPE_INSN;
-  t_insn->is_specific_opcode = FALSE;	/* Must not be specific.  */
-  t_insn->opcode = opcode;
-  t_insn->ntok = xtensa_num_operands (isa, opcode);
-  for (i = 0; i < t_insn->ntok; i++)
+  tinsn_init (tinsn);
+  tinsn->insn_type = ITYPE_INSN;
+  tinsn->is_specific_opcode = FALSE;	/* must not be specific */
+  tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf);
+  tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode);
+  for (i = 0; i < tinsn->ntok; i++)
     {
-      set_expr_const (&t_insn->tok[i],
-		      xtensa_insnbuf_get_operand (insnbuf, opcode, i));
+      set_expr_const (&tinsn->tok[i],
+		      xtensa_insnbuf_get_operand (slotbuf, fmt, slot,
+						  tinsn->opcode, i));
     }
 }
 
@@ -8519,75 +11247,249 @@ tinsn_from_chars (t_insn, f)
 /* Read the value of the relaxable immed from the fr_symbol and fr_offset.  */
 
 static void
-tinsn_immed_from_frag (t_insn, fragP)
-     TInsn *t_insn;
-     fragS *fragP;
+tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot)
 {
-  xtensa_opcode opcode = t_insn->opcode;
+  xtensa_opcode opcode = tinsn->opcode;
   int opnum;
 
-  if (fragP->fr_symbol)
+  if (fragP->tc_frag_data.slot_symbols[slot])
     {
       opnum = get_relaxable_immed (opcode);
-      set_expr_symbol_offset (&t_insn->tok[opnum],
-			      fragP->fr_symbol, fragP->fr_offset);
+      assert (opnum >= 0);
+      set_expr_symbol_offset (&tinsn->tok[opnum],
+			      fragP->tc_frag_data.slot_symbols[slot],
+			      fragP->tc_frag_data.slot_offsets[slot]);
     }
 }
 
 
 static int
-get_num_stack_text_bytes (istack)
-     IStack *istack;
+get_num_stack_text_bytes (IStack *istack)
 {
   int i;
   int text_bytes = 0;
 
   for (i = 0; i < istack->ninsn; i++)
     {
-      TInsn *t_insn = &istack->insn[i];
-      if (t_insn->insn_type == ITYPE_INSN)
-	text_bytes += xg_get_insn_size (t_insn);
+      TInsn *tinsn = &istack->insn[i];
+      if (tinsn->insn_type == ITYPE_INSN)
+	text_bytes += xg_get_single_size (tinsn->opcode);
     }
   return text_bytes;
 }
 
 
 static int
-get_num_stack_literal_bytes (istack)
-     IStack *istack;
+get_num_stack_literal_bytes (IStack *istack)
 {
   int i;
   int lit_bytes = 0;
 
   for (i = 0; i < istack->ninsn; i++)
     {
-      TInsn *t_insn = &istack->insn[i];
-
-      if (t_insn->insn_type == ITYPE_LITERAL && t_insn->ntok == 1)
+      TInsn *tinsn = &istack->insn[i];
+      if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1)
 	lit_bytes += 4;
     }
   return lit_bytes;
 }
 
 
+/* vliw_insn functions.  */
+
+static void
+xg_init_vinsn (vliw_insn *v)
+{
+  int i;
+  xtensa_isa isa = xtensa_default_isa;
+
+  xg_clear_vinsn (v);
+
+  v->insnbuf = xtensa_insnbuf_alloc (isa);
+  if (v->insnbuf == NULL)
+    as_fatal (_("out of memory"));
+
+  for (i = 0; i < MAX_SLOTS; i++)
+    {
+      v->slotbuf[i] = xtensa_insnbuf_alloc (isa);
+      if (v->slotbuf[i] == NULL)
+	as_fatal (_("out of memory"));
+    }
+}
+
+
+static void
+xg_clear_vinsn (vliw_insn *v)
+{
+  int i;
+
+  memset (v, 0, offsetof (vliw_insn, insnbuf));
+
+  v->format = XTENSA_UNDEFINED;
+  v->num_slots = 0;
+  v->inside_bundle = FALSE;
+
+  if (xt_saved_debug_type != DEBUG_NONE)
+    debug_type = xt_saved_debug_type;
+
+  for (i = 0; i < MAX_SLOTS; i++)
+    v->slots[i].opcode = XTENSA_UNDEFINED;
+}
+
+
+static bfd_boolean
+vinsn_has_specific_opcodes (vliw_insn *v)
+{
+  int i;
+
+  for (i = 0; i < v->num_slots; i++)
+    {
+      if (v->slots[i].is_specific_opcode)
+	return TRUE;
+    }
+  return FALSE;
+}
+
+
+static void
+xg_free_vinsn (vliw_insn *v)
+{
+  int i;
+  xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf);
+  for (i = 0; i < MAX_SLOTS; i++)
+    xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]);
+}
+
+
+/* Encode a vliw_insn into an insnbuf.  Return TRUE if there are any symbolic
+   operands.  See also the assumptions listed for tinsn_to_slotbuf.  */
+
+static bfd_boolean
+vinsn_to_insnbuf (vliw_insn *vinsn,
+		  char *frag_offset,
+		  fragS *fragP,
+		  bfd_boolean record_fixup)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_format fmt = vinsn->format;
+  xtensa_insnbuf insnbuf = vinsn->insnbuf;
+  int slot;
+  bfd_boolean has_fixup = FALSE;
+
+  xtensa_format_encode (isa, fmt, insnbuf);
+
+  for (slot = 0; slot < vinsn->num_slots; slot++)
+    {
+      TInsn *tinsn = &vinsn->slots[slot];
+      bfd_boolean tinsn_has_fixup =
+	tinsn_to_slotbuf (vinsn->format, slot, tinsn,
+			  vinsn->slotbuf[slot]);
+
+      xtensa_format_set_slot (isa, fmt, slot,
+			      insnbuf, vinsn->slotbuf[slot]);
+      if (tinsn_has_fixup)
+	{
+	  int i;
+	  xtensa_opcode opcode = tinsn->opcode;
+	  int noperands = xtensa_opcode_num_operands (isa, opcode);
+	  has_fixup = TRUE;
+
+	  for (i = 0; i < noperands; i++)
+	    {
+	      expressionS* expr = &tinsn->tok[i];
+	      switch (expr->X_op)
+		{
+		case O_symbol:
+		case O_lo16:
+		case O_hi16:
+		  if (get_relaxable_immed (opcode) == i)
+		    {
+		      /* Add a fix record for the instruction, except if this
+			 function is being called prior to relaxation, i.e.,
+			 if record_fixup is false, and the instruction might
+			 be relaxed later.  */
+		      if (record_fixup
+			  || tinsn->is_specific_opcode
+			  || !xg_is_relaxable_insn (tinsn, 0))
+			{
+			  xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP,
+					     frag_offset - fragP->fr_literal);
+			}
+		      else
+			{
+			  if (expr->X_op != O_symbol)
+			    as_bad (_("invalid operand"));
+			  tinsn->symbol = expr->X_add_symbol;
+			  tinsn->offset = expr->X_add_number;
+			}
+		    }
+		  else
+		    as_bad (_("symbolic operand not allowed"));
+		  break;
+
+		case O_constant:
+		case O_register:
+		  break;
+
+		default:
+		  as_bad (_("expression too complex"));
+		  break;
+		}
+	    }
+	}
+    }
+
+  return has_fixup;
+}
+
+
+static void
+vinsn_from_chars (vliw_insn *vinsn, char *f)
+{
+  static xtensa_insnbuf insnbuf = NULL;
+  static xtensa_insnbuf slotbuf = NULL;
+  int i;
+  xtensa_format fmt;
+  xtensa_isa isa = xtensa_default_isa;
+
+  if (!insnbuf)
+    {
+      insnbuf = xtensa_insnbuf_alloc (isa);
+      slotbuf = xtensa_insnbuf_alloc (isa);
+    }
+
+  xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0);
+  fmt = xtensa_format_decode (isa, insnbuf);
+  if (fmt == XTENSA_UNDEFINED)
+    as_fatal (_("cannot decode instruction format"));
+  vinsn->format = fmt;
+  vinsn->num_slots = xtensa_format_num_slots (isa, fmt);
+
+  for (i = 0; i < vinsn->num_slots; i++)
+    {
+      TInsn *tinsn = &vinsn->slots[i];
+      xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf);
+      tinsn_from_insnbuf (tinsn, slotbuf, fmt, i);
+    }
+}
+
+
 /* Expression utilities.  */
 
-/* Return true if the expression is an integer constant.  */
+/* Return TRUE if the expression is an integer constant.  */
 
 bfd_boolean
-expr_is_const (s)
-     const expressionS *s;
+expr_is_const (const expressionS *s)
 {
   return (s->X_op == O_constant);
 }
 
 
 /* Get the expression constant.
-   Calling this is illegal if expr_is_const () returns true.  */
+   Calling this is illegal if expr_is_const () returns TRUE.  */
 
 offsetT
-get_expr_const (s)
-     const expressionS *s;
+get_expr_const (const expressionS *s)
 {
   assert (expr_is_const (s));
   return s->X_add_number;
@@ -8597,9 +11499,7 @@ get_expr_const (s)
 /* Set the expression to a constant value.  */
 
 void
-set_expr_const (s, val)
-     expressionS *s;
-     offsetT val;
+set_expr_const (expressionS *s, offsetT val)
 {
   s->X_op = O_constant;
   s->X_add_number = val;
@@ -8608,13 +11508,28 @@ set_expr_const (s, val)
 }
 
 
+bfd_boolean
+expr_is_register (const expressionS *s)
+{
+  return (s->X_op == O_register);
+}
+
+
+/* Get the expression constant.
+   Calling this is illegal if expr_is_const () returns TRUE.  */
+
+offsetT
+get_expr_register (const expressionS *s)
+{
+  assert (expr_is_register (s));
+  return s->X_add_number;
+}
+
+
 /* Set the expression to a symbol + constant offset.  */
 
 void
-set_expr_symbol_offset (s, sym, offset)
-     expressionS *s;
-     symbolS *sym;
-     offsetT offset;
+set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset)
 {
   s->X_op = O_symbol;
   s->X_add_symbol = sym;
@@ -8623,10 +11538,10 @@ set_expr_symbol_offset (s, sym, offset)
 }
 
 
+/* Return TRUE if the two expressions are equal.  */
+
 bfd_boolean
-expr_is_equal (s1, s2)
-     expressionS *s1;
-     expressionS *s2;
+expr_is_equal (expressionS *s1, expressionS *s2)
 {
   if (s1->X_op != s2->X_op)
     return FALSE;
@@ -8641,17 +11556,13 @@ expr_is_equal (s1, s2)
 
 
 static void
-copy_expr (dst, src)
-     expressionS *dst;
-     const expressionS *src;
+copy_expr (expressionS *dst, const expressionS *src)
 {
   memcpy (dst, src, sizeof (expressionS));
 }
 
 
-/* Support for Tensilica's "--rename-section" option.  */
-
-#ifdef XTENSA_SECTION_RENAME
+/* Support for the "--rename-section" option.  */
 
 struct rename_section_struct
 {
@@ -8663,18 +11574,22 @@ struct rename_section_struct
 static struct rename_section_struct *section_rename;
 
 
-/* Parse the string oldname=new_name:oldname2=new_name2 
-   and call add_section_rename.  */
+/* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add
+   entries to the section_rename list.  Note: Specifying multiple
+   renamings separated by colons is not documented and is retained only
+   for backward compatibility.  */
 
-void
-build_section_rename (arg)
-     const char *arg;
+static void
+build_section_rename (const char *arg)
 {
+  struct rename_section_struct *r;
   char *this_arg = NULL;
   char *next_arg = NULL;
 
-  for (this_arg = strdup (arg); this_arg != NULL; this_arg = next_arg)
+  for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg)
     {
+      char *old_name, *new_name;
+
       if (this_arg)
 	{
 	  next_arg = strchr (this_arg, ':');
@@ -8684,67 +11599,55 @@ build_section_rename (arg)
 	      next_arg++;
 	    }
 	}
-      {
-	char *old_name = this_arg;
-	char *new_name = strchr (this_arg, '=');
 
-	if (*old_name == '\0')
-	  {
-	    as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
-	    continue;
-	  }
-	if (!new_name || new_name[1] == '\0')
-	  {
-	    as_warn (_("ignoring invalid '-rename-section' "
-		       "specification: '%s'"), old_name);
-	    continue;
-	  }
-	*new_name = '\0';
-	new_name++;
-	add_section_rename (old_name, new_name);
-      }
-    }
-}
+      old_name = this_arg;
+      new_name = strchr (this_arg, '=');
 
+      if (*old_name == '\0')
+	{
+	  as_warn (_("ignoring extra '-rename-section' delimiter ':'"));
+	  continue;
+	}
+      if (!new_name || new_name[1] == '\0')
+	{
+	  as_warn (_("ignoring invalid '-rename-section' specification: '%s'"),
+		   old_name);
+	  continue;
+	}
+      *new_name = '\0';
+      new_name++;
 
-static void
-add_section_rename (old_name, new_name)
-     char *old_name;
-     char *new_name;
-{
-  struct rename_section_struct *r = section_rename;
+      /* Check for invalid section renaming.  */
+      for (r = section_rename; r != NULL; r = r->next)
+	{
+	  if (strcmp (r->old_name, old_name) == 0)
+	    as_bad (_("section %s renamed multiple times"), old_name);
+	  if (strcmp (r->new_name, new_name) == 0)
+	    as_bad (_("multiple sections remapped to output section %s"),
+		    new_name);
+	}
 
-  /* Check for invalid section renaming.  */
-  for (r = section_rename; r != NULL; r = r->next)
-    {
-      if (strcmp (r->old_name, old_name) == 0)
-	as_bad (_("section %s renamed multiple times"), old_name);
-      if (strcmp (r->new_name, new_name) == 0)
-	as_bad (_("multiple sections remapped to output section %s"),
-		new_name);
+      /* Now add it.  */
+      r = (struct rename_section_struct *)
+	xmalloc (sizeof (struct rename_section_struct));
+      r->old_name = xstrdup (old_name);
+      r->new_name = xstrdup (new_name);
+      r->next = section_rename;
+      section_rename = r;
     }
-
-  /* Now add it.  */
-  r = (struct rename_section_struct *)
-    xmalloc (sizeof (struct rename_section_struct));
-  r->old_name = strdup (old_name);
-  r->new_name = strdup (new_name);
-  r->next = section_rename;
-  section_rename = r;
 }
 
 
-const char *
-xtensa_section_rename (name)
-     const char *name;
+char *
+xtensa_section_rename (char *name)
 {
   struct rename_section_struct *r = section_rename;
 
   for (r = section_rename; r != NULL; r = r->next)
-    if (strcmp (r->old_name, name) == 0)
-      return r->new_name;
+    {
+      if (strcmp (r->old_name, name) == 0)
+	return r->new_name;
+    }
 
   return name;
 }
-
-#endif /* XTENSA_SECTION_RENAME */
diff --git a/gas/config/tc-xtensa.h b/gas/config/tc-xtensa.h
index cf4a3507b138..71f1ebbd3b38 100644
--- a/gas/config/tc-xtensa.h
+++ b/gas/config/tc-xtensa.h
@@ -1,5 +1,5 @@
 /* tc-xtensa.h -- Header file for tc-xtensa.c.
-   Copyright (C) 2003 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,79 +15,270 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef TC_XTENSA
 #define TC_XTENSA 1
 
-#ifdef ANSI_PROTOTYPES
 struct fix;
-#endif
-
-#ifndef BFD_ASSEMBLER
-#error Xtensa support requires BFD_ASSEMBLER
-#endif
 
 #ifndef OBJ_ELF
 #error Xtensa support requires ELF object format
 #endif
 
+#include "xtensa-isa.h"
 #include "xtensa-config.h"
 
 #define TARGET_BYTES_BIG_ENDIAN XCHAL_HAVE_BE
 
 
+/* Maximum number of opcode slots in a VLIW instruction.  */
+#define MAX_SLOTS 15
+
+
+/* For all xtensa relax states except RELAX_DESIRE_ALIGN and
+   RELAX_DESIRE_ALIGN_IF_TARGET, the amount a frag might grow is stored
+   in the fr_var field.  For the two exceptions, fr_var is a float value
+   that records the frequency with which the following instruction is
+   executed as a branch target.  The aligner uses this information to
+   tell which targets are most important to be aligned.  */
+
+enum xtensa_relax_statesE
+{
+  RELAX_ALIGN_NEXT_OPCODE,
+  /* Use the first opcode of the next fragment to determine the
+     alignment requirements.  This is ONLY used for LOOPs currently.  */
+
+  RELAX_CHECK_ALIGN_NEXT_OPCODE,
+  /* The next non-empty frag contains a loop instruction.  Check to see
+     if it is correctly aligned, but do not align it.  */
+
+  RELAX_DESIRE_ALIGN_IF_TARGET,
+  /* These are placed in front of labels and converted to either
+     RELAX_DESIRE_ALIGN / RELAX_LOOP_END or rs_fill of 0 before
+     relaxation begins.  */
+
+  RELAX_ADD_NOP_IF_A0_B_RETW,
+  /* These are placed in front of conditional branches.  Before
+     relaxation begins, they are turned into either NOPs for branches
+     immediately followed by RETW or RETW.N or rs_fills of 0.  This is
+     used to avoid a hardware bug in some early versions of the
+     processor.  */
+
+  RELAX_ADD_NOP_IF_PRE_LOOP_END,
+  /* These are placed after JX instructions.  Before relaxation begins,
+     they are turned into either NOPs, if the JX is one instruction
+     before a loop end label, or rs_fills of 0.  This is used to avoid a
+     hardware interlock issue prior to Xtensa version T1040.  */
+
+  RELAX_ADD_NOP_IF_SHORT_LOOP,
+  /* These are placed after LOOP instructions and turned into NOPs when:
+     (1) there are less than 3 instructions in the loop; we place 2 of
+     these in a row to add up to 2 NOPS in short loops; or (2) the
+     instructions in the loop do not include a branch or jump.
+     Otherwise they are turned into rs_fills of 0 before relaxation
+     begins.  This is used to avoid hardware bug PR3830.  */
+
+  RELAX_ADD_NOP_IF_CLOSE_LOOP_END,
+  /* These are placed after LOOP instructions and turned into NOPs if
+     there are less than 12 bytes to the end of some other loop's end.
+     Otherwise they are turned into rs_fills of 0 before relaxation
+     begins.  This is used to avoid hardware bug PR3830.  */
+
+  RELAX_DESIRE_ALIGN,
+  /* The next fragment would like its first instruction to NOT cross an
+     instruction fetch boundary.  */
+
+  RELAX_MAYBE_DESIRE_ALIGN,
+  /* The next fragment might like its first instruction to NOT cross an
+     instruction fetch boundary.  These are placed after a branch that
+     might be relaxed.  If the branch is relaxed, then this frag will be
+     a branch target and this frag will be changed to RELAX_DESIRE_ALIGN
+     frag.  */
+
+  RELAX_LOOP_END,
+  /* This will be turned into a NOP or NOP.N if the previous instruction
+     is expanded to negate a loop.  */
+
+  RELAX_LOOP_END_ADD_NOP,
+  /* When the code density option is available, this will generate a
+     NOP.N marked RELAX_NARROW.  Otherwise, it will create an rs_fill
+     fragment with a NOP in it.  */
+
+  RELAX_LITERAL,
+  /* Another fragment could generate an expansion here but has not yet.  */
+
+  RELAX_LITERAL_NR,
+  /* Expansion has been generated by an instruction that generates a
+     literal.  However, the stretch has NOT been reported yet in this
+     fragment.  */
+
+  RELAX_LITERAL_FINAL,
+  /* Expansion has been generated by an instruction that generates a
+     literal.  */
+
+  RELAX_LITERAL_POOL_BEGIN,
+  RELAX_LITERAL_POOL_END,
+  /* Technically these are not relaxations at all but mark a location
+     to store literals later.  Note that fr_var stores the frchain for
+     BEGIN frags and fr_var stores now_seg for END frags.  */
+
+  RELAX_NARROW,
+  /* The last instruction in this fragment (at->fr_opcode) can be
+     freely replaced with a single wider instruction if a future
+     alignment desires or needs it.  */
+
+  RELAX_IMMED,
+  /* The last instruction in this fragment (at->fr_opcode) contains
+     the value defined by fr_symbol (fr_offset = 0).  If the value
+     does not fit, use the specified expansion.  This is similar to
+     "NARROW", except that these may not be expanded in order to align
+     code.  */
+
+  RELAX_IMMED_STEP1,
+  /* The last instruction in this fragment (at->fr_opcode) contains a
+     literal.  It has already been expanded at least 1 step.  */
+
+  RELAX_IMMED_STEP2,
+  /* The last instruction in this fragment (at->fr_opcode) contains a
+     literal.  It has already been expanded at least 2 steps.  */
+
+  RELAX_SLOTS,
+  /* There are instructions within the last VLIW instruction that need
+     relaxation.  Find the relaxation based on the slot info in
+     xtensa_frag_type.  Relaxations that deal with particular opcodes
+     are slot-based (e.g., converting a MOVI to an L32R).  Relaxations
+     that deal with entire instructions, such as alignment, are not
+     slot-based.  */
+
+  RELAX_FILL_NOP,
+  /* This marks the location of a pipeline stall.  We can fill these guys
+     in for alignment of any size.  */
+
+  RELAX_UNREACHABLE,
+  /* This marks the location as unreachable.  The assembler may widen or
+     narrow this area to meet alignment requirements of nearby
+     instructions.  */
+
+  RELAX_MAYBE_UNREACHABLE,
+  /* This marks the location as possibly unreachable.  These are placed
+     after a branch that may be relaxed into a branch and jump. If the
+     branch is relaxed, then this frag will be converted to a
+     RELAX_UNREACHABLE frag.  */
+
+  RELAX_NONE
+};
+
+/* This is used as a stopper to bound the number of steps that
+   can be taken.  */
+#define RELAX_IMMED_MAXSTEPS (RELAX_IMMED_STEP2 - RELAX_IMMED)
+
 struct xtensa_frag_type
 {
-  unsigned is_literal:1;
-  unsigned is_text:1;
-  unsigned is_loop_target:1;
-  unsigned is_branch_target:1;
-  unsigned is_insn:1;
+  /* Info about the current state of assembly, e.g., transform,
+     absolute_literals, etc.  These need to be passed to the backend and
+     then to the object file.
+
+     When is_assembly_state_set is false, the frag inherits some of the
+     state settings from the previous frag in this segment.  Because it
+     is not possible to intercept all fragment closures (frag_more and
+     frag_append_1_char can close a frag), we use a pass after initial
+     assembly to fill in the assembly states.  */
+
+  unsigned int is_assembly_state_set : 1;
+  unsigned int is_no_density : 1;
+  unsigned int is_no_transform : 1;
+  unsigned int use_longcalls : 1;
+  unsigned int use_absolute_literals : 1;
+
+  /* Inhibits relaxation of machine-dependent alignment frags the
+     first time through a relaxation....  */
+  unsigned int relax_seen : 1;
+
+  /* Information that is needed in the object file and set when known.  */
+  unsigned int is_literal : 1;
+  unsigned int is_loop_target : 1;
+  unsigned int is_branch_target : 1;
+  unsigned int is_insn : 1;
+  unsigned int is_unreachable : 1;
 
-  /* Info about the current state of assembly, i.e., density, relax,
-     generics, freeregs, longcalls.  These need to be passed to the
-     backend and then to the linking file.  */
+  unsigned int is_specific_opcode : 1; /* also implies no_transform */
 
-  unsigned is_no_density:1;
-  unsigned is_relax:1;
-  unsigned is_generics:1;
-  unsigned is_longcalls:1;
+  unsigned int is_align : 1;
+  unsigned int is_text_align : 1;
+  unsigned int alignment : 5;
+
+  /* A frag with this bit set is the first in a loop that actually
+     contains an instruction.  */
+  unsigned int is_first_loop_insn : 1;
+
+  /* A frag with this bit set is a branch that we are using to
+     align branch targets as if it were a normal narrow instruction.  */
+  unsigned int is_aligning_branch : 1;
 
   /* For text fragments that can generate literals at relax time, this
      variable points to the frag where the literal will be stored.  For
      literal frags, this variable points to the nearest literal pool
      location frag.  This literal frag will be moved to after this
      location.  */
-
   fragS *literal_frag;
 
   /* The destination segment for literal frags.  (Note that this is only
-     valid after xtensa_move_literals.  */
-
+     valid after xtensa_move_literals.)  This field is also used for
+     LITERAL_POOL_END frags.  */
   segT lit_seg;
 
+  /* Frag chain for LITERAL_POOL_BEGIN frags.  */
+  struct frchain *lit_frchain;
+
   /* For the relaxation scheme, some literal fragments can have their
      expansions modified by an instruction that relaxes.  */
-
-  unsigned text_expansion;
-  unsigned literal_expansion;
-  unsigned unreported_expansion;
+  int text_expansion[MAX_SLOTS];
+  int literal_expansion[MAX_SLOTS];
+  int unreported_expansion;
+
+  /* For text fragments that can generate literals at relax time:  */
+  fragS *literal_frags[MAX_SLOTS];
+  enum xtensa_relax_statesE slot_subtypes[MAX_SLOTS];
+  symbolS *slot_symbols[MAX_SLOTS];
+  offsetT slot_offsets[MAX_SLOTS];
+
+  /* The global aligner needs to walk backward through the list of
+     frags.  This field is only valid after xtensa_end.  */
+  fragS *fr_prev;
 };
 
-typedef struct xtensa_block_info_struct
+
+/* For VLIW support, we need to know what slot a fixup applies to.  */
+typedef struct xtensa_fix_data_struct
 {
-  segT sec;
-  bfd_vma offset;
-  size_t size;
-  struct xtensa_block_info_struct *next;
-} xtensa_block_info;
+  int slot;
+  symbolS *X_add_symbol;
+  offsetT X_add_number;
+} xtensa_fix_data;
+
 
+/* Structure to record xtensa-specific symbol information.  */
+typedef struct xtensa_symfield_type
+{
+  unsigned int is_loop_target : 1;
+  unsigned int is_branch_target : 1;
+} xtensa_symfield_type;
+
+
+/* Structure for saving information about a block of property data
+   for frags that have the same flags.   The forward reference is
+   in this header file.  The actual definition is in tc-xtensa.c.  */
+struct xtensa_block_info_struct;
+typedef struct xtensa_block_info_struct xtensa_block_info;
+
+
+/* Property section types.  */
 typedef enum
 {
-  xt_insn_sec,
   xt_literal_sec,
+  xt_prop_sec,
   max_xt_sec
 } xt_section_type;
 
@@ -97,67 +288,55 @@ typedef struct xtensa_segment_info_struct
   xtensa_block_info *blocks[max_xt_sec];
 } xtensa_segment_info;
 
-typedef struct xtensa_symfield_type_struct
-{
-  unsigned int plt : 1;
-  unsigned int is_loop_target : 1;
-  unsigned int is_branch_target : 1;
-} xtensa_symfield_type;
-
 
-/* Section renaming is only supported in Tensilica's version of GAS.  */
-#define XTENSA_SECTION_RENAME 1
-#ifdef  XTENSA_SECTION_RENAME
-extern const char *xtensa_section_rename
-  PARAMS ((const char *));
-#else
-/* Tensilica's section renaming feature is not included here.  */
-#define xtensa_section_rename(name)	(name)
-#endif /* XTENSA_SECTION_RENAME */
-
-
-extern const char *xtensa_target_format
-  PARAMS ((void));
-extern void xtensa_frag_init
-  PARAMS ((fragS *));
-extern void xtensa_cons_fix_new
-  PARAMS ((fragS *, int, int, expressionS *));
-extern void xtensa_frob_label
-  PARAMS ((struct symbol *));
-extern void xtensa_end
-  PARAMS ((void));
-extern void xtensa_post_relax_hook
-  PARAMS ((void));
-extern void xtensa_file_arch_init
-  PARAMS ((bfd *));
-extern void xtensa_flush_pending_output
-  PARAMS ((void));
-extern bfd_boolean xtensa_fix_adjustable
-  PARAMS ((struct fix *));
-extern void xtensa_symbol_new_hook
-  PARAMS ((symbolS *));
-extern long xtensa_relax_frag
-  PARAMS ((fragS *, long, int *));
+extern const char *xtensa_target_format (void);
+extern void xtensa_init_fix_data (struct fix *);
+extern void xtensa_frag_init (fragS *);
+extern int xtensa_force_relocation (struct fix *);
+extern int xtensa_validate_fix_sub (struct fix *);
+extern void xtensa_frob_label (struct symbol *);
+extern void xtensa_end (void);
+extern void xtensa_post_relax_hook (void);
+extern void xtensa_file_arch_init (bfd *);
+extern void xtensa_flush_pending_output (void);
+extern bfd_boolean xtensa_fix_adjustable (struct fix *);
+extern void xtensa_symbol_new_hook (symbolS *);
+extern long xtensa_relax_frag (fragS *, long, int *);
+extern void xtensa_elf_section_change_hook (void);
+extern int xtensa_unrecognized_line (int);
+extern bfd_boolean xtensa_check_inside_bundle (void);
+extern void xtensa_handle_align (fragS *);
+extern char *xtensa_section_rename (char *);
 
 #define TARGET_FORMAT			xtensa_target_format ()
 #define TARGET_ARCH			bfd_arch_xtensa
 #define TC_SEGMENT_INFO_TYPE		xtensa_segment_info
-#define TC_SYMFIELD_TYPE		xtensa_symfield_type
+#define TC_SYMFIELD_TYPE                struct xtensa_symfield_type
+#define TC_FIX_TYPE			xtensa_fix_data
+#define TC_INIT_FIX_DATA(x)		xtensa_init_fix_data (x)
 #define TC_FRAG_TYPE			struct xtensa_frag_type
 #define TC_FRAG_INIT(frag)		xtensa_frag_init (frag)
-#define TC_CONS_FIX_NEW			xtensa_cons_fix_new
+#define TC_FORCE_RELOCATION(fix)	xtensa_force_relocation (fix)
+#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \
+  (! SEG_NORMAL (seg) || xtensa_force_relocation (fix))
+#define	TC_VALIDATE_FIX_SUB(fix)	xtensa_validate_fix_sub (fix)
+#define NO_PSEUDO_DOT			xtensa_check_inside_bundle ()
 #define tc_canonicalize_symbol_name(s)	xtensa_section_rename (s)
+#define tc_canonicalize_section_name(s)	xtensa_section_rename (s)
 #define tc_init_after_args()		xtensa_file_arch_init (stdoutput)
 #define tc_fix_adjustable(fix)		xtensa_fix_adjustable (fix)
 #define tc_frob_label(sym)		xtensa_frob_label (sym)
-#define tc_symbol_new_hook(s)		xtensa_symbol_new_hook (s)
-#define md_elf_section_rename(name)	xtensa_section_rename (name)
+#define tc_unrecognized_line(ch)	xtensa_unrecognized_line (ch)
+#define md_do_align(a,b,c,d,e)		xtensa_flush_pending_output ()
+#define md_elf_section_change_hook	xtensa_elf_section_change_hook
 #define md_end				xtensa_end
 #define md_flush_pending_output()	xtensa_flush_pending_output ()
 #define md_operand(x)
 #define TEXT_SECTION_NAME		xtensa_section_rename (".text")
 #define DATA_SECTION_NAME		xtensa_section_rename (".data")
 #define BSS_SECTION_NAME		xtensa_section_rename (".bss")
+#define HANDLE_ALIGN(fragP)		xtensa_handle_align (fragP)
+#define MAX_MEM_FOR_RS_ALIGN_CODE	1
 
 
 /* The renumber_section function must be mapped over all the sections
@@ -188,7 +367,65 @@ extern long xtensa_relax_frag
 #define DOUBLESLASH_LINE_COMMENTS
 #define TC_HANDLES_FX_DONE
 #define TC_FINALIZE_SYMS_BEFORE_SIZE_SEG 0
-
+#define TC_LINKRELAX_FIXUP(SEG) 0
 #define MD_APPLY_SYM_VALUE(FIX) 0
+#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
+
+
+/* Resource reservation info functions.  */
+
+/* Returns the number of copies of a particular unit.  */
+typedef int (*unit_num_copies_func) (void *, xtensa_funcUnit);
+
+/* Returns the number of units the opcode uses.  */
+typedef int (*opcode_num_units_func) (void *, xtensa_opcode);
+
+/* Given an opcode and an index into the opcode's funcUnit list,
+   returns the unit used for the index.  */
+typedef int (*opcode_funcUnit_use_unit_func) (void *, xtensa_opcode, int);
+
+/* Given an opcode and an index into the opcode's funcUnit list,
+   returns the cycle during which the unit is used.  */
+typedef int (*opcode_funcUnit_use_stage_func) (void *, xtensa_opcode, int);
+
+/* The above typedefs parameterize the resource_table so that the
+   optional scheduler doesn't need its own resource reservation system.
+
+   For simple resource checking, which is all that happens normally,
+   the functions will be as follows (with some wrapping to make the
+   interface more convenient):
+
+   unit_num_copies_func = xtensa_funcUnit_num_copies
+   opcode_num_units_func = xtensa_opcode_num_funcUnit_uses
+   opcode_funcUnit_use_unit_func = xtensa_opcode_funcUnit_use->unit
+   opcode_funcUnit_use_stage_func = xtensa_opcode_funcUnit_use->stage
+
+   Of course the optional scheduler has its own reservation table
+   and functions.  */
+
+int opcode_funcUnit_use_unit (void *, xtensa_opcode, int);
+int opcode_funcUnit_use_stage (void *, xtensa_opcode, int);
+
+typedef struct
+{
+  void *data;
+  int cycles;
+  int allocated_cycles;
+  int num_units;
+  unit_num_copies_func unit_num_copies;
+  opcode_num_units_func opcode_num_units;
+  opcode_funcUnit_use_unit_func opcode_unit_use;
+  opcode_funcUnit_use_stage_func opcode_unit_stage;
+  unsigned char **units;
+} resource_table;
+
+resource_table *new_resource_table
+  (void *, int, int, unit_num_copies_func, opcode_num_units_func,
+   opcode_funcUnit_use_unit_func, opcode_funcUnit_use_stage_func);
+void resize_resource_table (resource_table *, int);
+void clear_resource_table (resource_table *);
+bfd_boolean resources_available (resource_table *, xtensa_opcode, int);
+void reserve_resources (resource_table *, xtensa_opcode, int);
+void release_resources (resource_table *, xtensa_opcode, int);
 
 #endif /* TC_XTENSA */
diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
new file mode 100644
index 000000000000..413e336a2c89
--- /dev/null
+++ b/gas/config/tc-z80.c
@@ -0,0 +1,2035 @@
+/* tc-z80.c -- Assemble code for the Zilog Z80 and ASCII R800
+   Copyright 2005 Free Software Foundation, Inc.
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "as.h"
+#include "listing.h"
+#include "bfd.h"
+#include "safe-ctype.h"
+#include "subsegs.h"
+#include "symbols.h"
+#include "libiberty.h"
+
+/* Exported constants.  */
+const char comment_chars[] = ";\0";
+const char line_comment_chars[] = "#;\0";
+const char line_separator_chars[] = "\0";
+const char EXP_CHARS[] = "eE\0";
+const char FLT_CHARS[] = "RrFf\0";
+
+/* For machine specific options.  */
+const char * md_shortopts = ""; /* None yet.  */
+
+enum options
+{
+  OPTION_MACH_Z80 = OPTION_MD_BASE,
+  OPTION_MACH_R800,
+  OPTION_MACH_IUD,
+  OPTION_MACH_WUD,
+  OPTION_MACH_FUD,
+  OPTION_MACH_IUP,
+  OPTION_MACH_WUP,
+  OPTION_MACH_FUP
+};
+
+#define INS_Z80    1
+#define INS_UNDOC  2
+#define INS_UNPORT 4
+#define INS_R800   8
+
+struct option md_longopts[] =
+{
+  { "z80",       no_argument, NULL, OPTION_MACH_Z80},
+  { "r800",      no_argument, NULL, OPTION_MACH_R800},
+  { "ignore-undocumented-instructions", no_argument, NULL, OPTION_MACH_IUD },
+  { "Wnud",  no_argument, NULL, OPTION_MACH_IUD },
+  { "warn-undocumented-instructions",  no_argument, NULL, OPTION_MACH_WUD },
+  { "Wud",  no_argument, NULL, OPTION_MACH_WUD },
+  { "forbid-undocumented-instructions", no_argument, NULL, OPTION_MACH_FUD },
+  { "Fud",  no_argument, NULL, OPTION_MACH_FUD },
+  { "ignore-unportable-instructions", no_argument, NULL, OPTION_MACH_IUP },
+  { "Wnup",  no_argument, NULL, OPTION_MACH_IUP },
+  { "warn-unportable-instructions",  no_argument, NULL, OPTION_MACH_WUP },
+  { "Wup",  no_argument, NULL, OPTION_MACH_WUP },
+  { "forbid-unportable-instructions", no_argument, NULL, OPTION_MACH_FUP },
+  { "Fup",  no_argument, NULL, OPTION_MACH_FUP },
+
+  { NULL, no_argument, NULL, 0 }
+} ;
+
+size_t md_longopts_size = sizeof (md_longopts);
+
+extern int coff_flags;
+/* Instruction classes that silently assembled.  */
+static int ins_ok = INS_Z80 | INS_UNDOC;
+/* Instruction classes that generate errors.  */
+static int ins_err = INS_R800;
+/* Instruction classes actually used, determines machine type.  */
+static int ins_used = INS_Z80;
+
+int
+md_parse_option (int c, char* arg ATTRIBUTE_UNUSED)
+{
+  switch (c)
+    {
+    default:
+      return 0;
+    case OPTION_MACH_Z80:
+      ins_ok &= ~INS_R800;
+      ins_err |= INS_R800;
+      break;
+    case OPTION_MACH_R800:
+      ins_ok = INS_Z80 | INS_UNDOC | INS_R800;
+      ins_err = INS_UNPORT;
+      break;
+    case OPTION_MACH_IUD:
+      ins_ok |= INS_UNDOC;
+      ins_err &= ~INS_UNDOC;
+      break;
+    case OPTION_MACH_IUP:
+      ins_ok |= INS_UNDOC | INS_UNPORT;
+      ins_err &= ~(INS_UNDOC | INS_UNPORT);
+      break;
+    case OPTION_MACH_WUD:
+      if ((ins_ok & INS_R800) == 0)
+	{
+	  ins_ok &= ~(INS_UNDOC|INS_UNPORT);
+	  ins_err &= ~INS_UNDOC;
+	}
+      break;
+    case OPTION_MACH_WUP:
+      ins_ok &= ~INS_UNPORT;
+      ins_err &= ~(INS_UNDOC|INS_UNPORT);
+      break;
+    case OPTION_MACH_FUD:
+      if ((ins_ok & INS_R800) == 0)
+	{
+	  ins_ok &= (INS_UNDOC | INS_UNPORT);
+	  ins_err |= INS_UNDOC | INS_UNPORT;
+	}
+      break;
+    case OPTION_MACH_FUP:
+      ins_ok &= ~INS_UNPORT;
+      ins_err |= INS_UNPORT;
+      break;
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (FILE * f)
+{
+  fprintf (f, "\n\
+CPU model/instruction set options:\n\
+\n\
+  -z80\t\t  assemble for Z80\n\
+  -ignore-undocumented-instructions\n\
+  -Wnud\n\
+\tsilently assemble undocumented Z80-instructions that work on R800\n\
+  -ignore-unportable-instructions\n\
+  -Wnup\n\
+\tsilently assemble all undocumented Z80-instructions\n\
+  -warn-undocumented-instructions\n\
+  -Wud\n\
+\tissue warnings for undocumented Z80-instructions that work on R800\n\
+  -warn-unportable-instructions\n\
+  -Wup\n\
+\tissue warnings for other undocumented Z80-instructions\n\
+  -forbid-undocumented-instructions\n\
+  -Fud\n\
+\ttreat all undocumented z80-instructions as errors\n\
+  -forbid-unportable-instructions\n\
+  -Fup\n\
+\ttreat undocumented z80-instructions that do not work on R800 as errors\n\
+  -r800\t  assemble for R800\n\n\
+Default: -z80 -ignore-undocument-instructions -warn-unportable-instructions.\n");
+}
+
+static symbolS * zero;
+
+void
+md_begin (void)
+{
+  expressionS nul;
+  char * p;
+
+  p = input_line_pointer;
+  input_line_pointer = "0";
+  nul.X_md=0;
+  expression (& nul);
+  input_line_pointer = p;
+  zero = make_expr_symbol (& nul);
+  /* We do not use relaxation (yet).  */
+  linkrelax = 0;
+}
+
+void
+z80_md_end (void)
+{
+  int mach_type;
+
+  if (ins_used & (INS_UNPORT | INS_R800))
+    ins_used |= INS_UNDOC;
+
+  switch (ins_used)
+    {
+    case INS_Z80:
+      mach_type = bfd_mach_z80strict;
+      break;
+    case INS_Z80|INS_UNDOC:
+      mach_type = bfd_mach_z80;
+      break;
+    case INS_Z80|INS_UNDOC|INS_UNPORT:
+      mach_type = bfd_mach_z80full;
+      break;
+    case INS_Z80|INS_UNDOC|INS_R800:
+      mach_type = bfd_mach_r800;
+      break;
+    default:
+      mach_type = 0;
+    }
+
+  bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_type);
+}
+
+static const char *
+skip_space (const char *s)
+{
+  while (*s == ' ' || *s == '\t')
+    ++s;
+  return s;
+}
+
+/* A non-zero return-value causes a continue in the
+   function read_a_source_file () in ../read.c.  */
+int
+z80_start_line_hook (void)
+{
+  char *p, quote;
+  char buf[4];
+
+  /* Convert one character constants.  */
+  for (p = input_line_pointer; *p && *p != '\n'; ++p)
+    {
+      switch (*p)
+	{
+	case '\'':
+	  if (p[1] != 0 && p[1] != '\'' && p[2] == '\'')
+	    {
+	      snprintf (buf, 4, "%3d", (unsigned char)p[1]);
+	      *p++ = buf[0];
+	      *p++ = buf[1];
+	      *p++ = buf[2];
+	      break;
+	    }
+	case '"':
+	  for (quote = *p++; quote != *p && '\n' != *p; ++p)
+	    /* No escapes.  */ ;
+	  if (quote != *p)
+	    {
+	      as_bad (_("-- unterminated string"));
+	      ignore_rest_of_line ();
+	      return 1;
+	    }
+	  break;
+	}
+    }
+  /* Check for <label>[:] [.](EQU|DEFL) <value>.  */
+  if (is_name_beginner (*input_line_pointer))
+    {
+      char c, *rest, *line_start;
+      int len;
+      symbolS * symbolP;
+
+      line_start = input_line_pointer;
+      LISTING_NEWLINE ();
+      if (ignore_input ())
+	return 0;
+
+      c = get_symbol_end ();
+      rest = input_line_pointer + 1;
+
+      if (*rest == ':')
+	++rest;
+      if (*rest == ' ' || *rest == '\t')
+	++rest;
+      if (*rest == '.')
+	++rest;
+      if (strncasecmp (rest, "EQU", 3) == 0)
+	len = 3;
+      else if (strncasecmp (rest, "DEFL", 4) == 0)
+	len = 4;
+      else
+	len = 0;
+      if (len && (rest[len] == ' ' || rest[len] == '\t'))
+	{
+	  /* Handle assignment here.  */
+	  input_line_pointer = rest + len;
+	  if (line_start[-1] == '\n')
+	    bump_line_counters ();
+	  /* Most Z80 assemblers require the first definition of a
+             label to use "EQU" and redefinitions to have "DEFL".  */
+	  if (len == 3 && (symbolP = symbol_find (line_start)) != NULL) 
+	    {
+	      if (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
+		as_bad (_("symbol `%s' is already defined"), line_start);
+	    }
+	  equals (line_start, 1);
+	  return 1;
+	}
+      else
+	{
+	  /* Restore line and pointer.  */
+	  *input_line_pointer = c;
+	  input_line_pointer = line_start;
+	}
+    }
+  return 0;
+}
+
+symbolS *
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
+{
+  return NULL;
+}
+
+char *
+md_atof (int type ATTRIBUTE_UNUSED, char *litP ATTRIBUTE_UNUSED,
+	 int *sizeP ATTRIBUTE_UNUSED)
+{
+  return _("floating point numbers are not implemented");
+}
+
+valueT
+md_section_align (segT seg ATTRIBUTE_UNUSED, valueT size)
+{
+  return size;
+}
+
+long
+md_pcrel_from (fixS * fixp)
+{
+  return fixp->fx_where +
+    fixp->fx_frag->fr_address + 1;
+}
+
+typedef const char * (asfunc)(char, char, const char*);
+
+typedef struct _table_t
+{
+  char* name;
+  char prefix;
+  char opcode;
+  asfunc * fp;
+} table_t;
+
+/* Compares the key for structs that start with a char * to the key.  */
+static int
+key_cmp (const void * a, const void * b)
+{
+  const char *str_a, *str_b;
+
+  str_a = *((const char**)a);
+  str_b = *((const char**)b);
+  return strcmp (str_a, str_b);
+}
+
+#define BUFLEN 8 /* Large enough for any keyword.  */
+
+char buf[BUFLEN];
+const char *key = buf;
+
+#define R_STACKABLE (0x80)
+#define R_ARITH     (0x40)
+#define R_IX        (0x20)
+#define R_IY        (0x10)
+#define R_INDEX     (R_IX | R_IY)
+
+#define REG_A (7)
+#define REG_B (0)
+#define REG_C (1)
+#define REG_D (2)
+#define REG_E (3)
+#define REG_H (4)
+#define REG_L (5)
+#define REG_F (6 | 8)
+#define REG_I (9)
+#define REG_R (10)
+
+#define REG_AF (3 | R_STACKABLE)
+#define REG_BC (0 | R_STACKABLE | R_ARITH)
+#define REG_DE (1 | R_STACKABLE | R_ARITH)
+#define REG_HL (2 | R_STACKABLE | R_ARITH)
+#define REG_SP (3 | R_ARITH)
+
+static const struct reg_entry
+{
+  char* name;
+  int number;
+} regtable[] =
+{
+  {"a",  REG_A },
+  {"af", REG_AF },
+  {"b",  REG_B },
+  {"bc", REG_BC },
+  {"c",  REG_C },
+  {"d",  REG_D },
+  {"de", REG_DE },
+  {"e",  REG_E },
+  {"f",  REG_F },
+  {"h",  REG_H },
+  {"hl", REG_HL },
+  {"i",  REG_I },
+  {"ix", REG_HL | R_IX },
+  {"ixh",REG_H | R_IX },
+  {"ixl",REG_L | R_IX },
+  {"iy", REG_HL | R_IY },
+  {"iyh",REG_H | R_IY },
+  {"iyl",REG_L | R_IY },
+  {"l",  REG_L },
+  {"r",  REG_R },
+  {"sp", REG_SP },
+} ;
+
+/* Prevent an error on a line from also generating
+   a "junk at end of line" error message.  */
+static char err_flag;
+
+static void
+error (const char * message)
+{
+  as_bad (message);
+  err_flag = 1;
+}
+
+static void
+ill_op (void)
+{
+  error (_("illegal operand"));
+}
+
+static void
+wrong_mach (int ins_type)
+{
+  const char *p;
+
+  switch (ins_type)
+    {
+    case INS_UNDOC:
+      p = "undocumented instruction";
+      break;
+    case INS_UNPORT:
+      p = "instruction does not work on R800";
+      break;
+    case INS_R800:
+      p = "instruction only works R800";
+      break;
+    default:
+      p = 0; /* Not reachable.  */
+    }
+
+  if (ins_type & ins_err)
+    error (_(p));
+  else
+    as_warn (_(p));
+}
+
+static void
+check_mach (int ins_type)
+{
+  if ((ins_type & ins_ok) == 0)
+    wrong_mach (ins_type);
+  ins_used |= ins_type;
+}
+
+/* Check whether an expression is indirect.  */
+static int
+is_indir (const char *s)
+{
+  char quote;
+  const char *p;
+  int indir, depth;
+
+  /* Indirection is indicated with parentheses.  */
+  indir = (*s == '(');
+
+  for (p = s, depth = 0; *p && *p != ','; ++p)
+    {
+      switch (*p)
+	{
+	case '"':
+	case '\'':
+	  for (quote = *p++; quote != *p && *p != '\n'; ++p)
+	    if (*p == '\\' && p[1])
+	      ++p;
+	  break;
+	case '(':
+	  ++ depth;
+	  break;
+	case ')':
+	  -- depth;
+	  if (depth == 0)
+	    {
+	      p = skip_space (p + 1);
+	      if (*p && *p != ',')
+		indir = 0;
+	      --p;
+	    }
+	  if (depth < 0)
+	    error (_("mismatched parentheses"));
+	  break;
+	}
+    }
+
+  if (depth != 0)
+    error (_("mismatched parentheses"));
+
+  return indir;
+}
+
+/* Parse general expression.  */
+static const char *
+parse_exp2 (const char *s, expressionS *op, segT *pseg)
+{
+  const char *p;
+  int indir;
+  int i;
+  const struct reg_entry * regp;
+  expressionS offset;
+
+  p = skip_space (s);
+  op->X_md = indir = is_indir (p);
+  if (indir)
+    p = skip_space (p + 1);
+
+  for (i = 0; i < BUFLEN; ++i)
+    {
+      if (!ISALPHA (p[i])) /* Register names consist of letters only.  */
+	break;
+      buf[i] = TOLOWER (p[i]);
+    }
+
+  if ((i < BUFLEN) && ((p[i] == 0) || (strchr (")+-, \t", p[i]))))
+    {
+      buf[i] = 0;
+      regp = bsearch (& key, regtable, ARRAY_SIZE (regtable),
+		      sizeof (regtable[0]), key_cmp);
+      if (regp)
+	{
+	  *pseg = reg_section;
+	  op->X_add_symbol = op->X_op_symbol = 0;
+	  op->X_add_number = regp->number;
+	  op->X_op = O_register;
+	  p += strlen (regp->name);
+	  p = skip_space (p);
+	  if (indir)
+	    {
+	      if (*p == ')')
+		++p;
+	      if ((regp->number & R_INDEX) && (regp->number & R_ARITH))
+		{
+		  op->X_op = O_md1;
+
+		  if  ((*p == '+') || (*p == '-'))
+		    {
+		      input_line_pointer = (char*) p;
+		      expression (& offset);
+		      p = skip_space (input_line_pointer);
+		      if (*p != ')')
+			error (_("bad offset expression syntax"));
+		      else
+			++ p;
+		      op->X_add_symbol = make_expr_symbol (& offset);
+		      return p;
+		    }
+
+		  /* We treat (i[xy]) as (i[xy]+0), which is how it will
+		     end up anyway, unless we're processing jp (i[xy]).  */
+		  op->X_add_symbol = zero;
+		}
+	    }
+	  p = skip_space (p);
+
+	  if ((*p == 0) || (*p == ','))
+	    return p;
+	}
+    }
+  /* Not an argument involving a register; use the generic parser.  */
+  input_line_pointer = (char*) s ;
+  *pseg = expression (op);
+  if (op->X_op == O_absent)
+    error (_("missing operand"));
+  if (op->X_op == O_illegal)
+    error (_("bad expression syntax"));
+  return input_line_pointer;
+}
+
+static const char *
+parse_exp (const char *s, expressionS *op)
+{
+  segT dummy;
+  return parse_exp2 (s, op, & dummy);
+}
+
+/* Condition codes, including some synonyms provided by HiTech zas.  */
+static const struct reg_entry cc_tab[] =
+{
+  { "age", 6 << 3 },
+  { "alt", 7 << 3 },
+  { "c",   3 << 3 },
+  { "di",  4 << 3 },
+  { "ei",  5 << 3 },
+  { "lge", 2 << 3 },
+  { "llt", 3 << 3 },
+  { "m",   7 << 3 },
+  { "nc",  2 << 3 },
+  { "nz",  0 << 3 },
+  { "p",   6 << 3 },
+  { "pe",  5 << 3 },
+  { "po",  4 << 3 },
+  { "z",   1 << 3 },
+} ;
+
+/* Parse condition code.  */
+static const char *
+parse_cc (const char *s, char * op)
+{
+  const char *p;
+  int i;
+  struct reg_entry * cc_p;
+
+  for (i = 0; i < BUFLEN; ++i)
+    {
+      if (!ISALPHA (s[i])) /* Condition codes consist of letters only.  */
+	break;
+      buf[i] = TOLOWER (s[i]);
+    }
+
+  if ((i < BUFLEN)
+      && ((s[i] == 0) || (s[i] == ',')))
+    {
+      buf[i] = 0;
+      cc_p = bsearch (&key, cc_tab, ARRAY_SIZE (cc_tab),
+		      sizeof (cc_tab[0]), key_cmp);
+    }
+  else
+    cc_p = NULL;
+
+  if (cc_p)
+    {
+      *op = cc_p->number;
+      p = s + i;
+    }
+  else
+    p = NULL;
+
+  return p;
+}
+
+static const char *
+emit_insn (char prefix, char opcode, const char * args)
+{
+  char *p;
+
+  if (prefix)
+    {
+      p = frag_more (2);
+      *p++ = prefix;
+    }
+  else
+    p = frag_more (1);
+  *p = opcode;
+  return args;
+}
+
+void z80_cons_fix_new (fragS *frag_p, int offset, int nbytes, expressionS *exp)
+{
+  bfd_reloc_code_real_type r[4] =
+    {
+      BFD_RELOC_8,
+      BFD_RELOC_16,
+      BFD_RELOC_24,
+      BFD_RELOC_32
+    };
+
+  if (nbytes < 1 || nbytes > 4) 
+    {
+      as_bad (_("unsupported BFD relocation size %u"), nbytes);
+    }
+  else
+    {
+      fix_new_exp (frag_p, offset, nbytes, exp, 0, r[nbytes-1]);
+    }
+}
+
+static void
+emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
+{
+  char *p;
+  int lo, hi;
+  fixS * fixp;
+
+  p = frag_more (1);
+  *p = val->X_add_number;
+  if ((r_type == BFD_RELOC_8_PCREL) && (val->X_op == O_constant))
+    {
+      as_bad(_("cannot make a relative jump to an absolute location"));
+    }
+  else if (val->X_op == O_constant)
+    {
+      lo = -128;
+      hi = (BFD_RELOC_8 == r_type) ? 255 : 127;
+
+      if ((val->X_add_number < lo) || (val->X_add_number > hi))
+	{
+	  if (r_type == BFD_RELOC_Z80_DISP8)
+	    as_bad (_("offset too large"));
+	  else
+	    as_warn (_("overflow"));
+	}
+    }
+  else
+    {
+      fixp = fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val,
+			  (r_type == BFD_RELOC_8_PCREL) ? TRUE : FALSE, r_type);
+      /* FIXME : Process constant offsets immediately.  */
+    }
+}
+
+static void
+emit_word (expressionS * val)
+{
+  char *p;
+
+  p = frag_more (2);
+  if (   (val->X_op == O_register)
+      || (val->X_op == O_md1))
+    ill_op ();
+  else
+    {
+      *p = val->X_add_number;
+      p[1] = (val->X_add_number>>8);
+      if (val->X_op != O_constant)
+	fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
+		     val, FALSE, BFD_RELOC_16);
+    }
+}
+
+static void
+emit_mx (char prefix, char opcode, int shift, expressionS * arg)
+     /* The operand m may be r, (hl), (ix+d), (iy+d),
+	if 0 == prefix m may also be ixl, ixh, iyl, iyh.  */
+{
+  char *q;
+  int rnum;
+
+  rnum = arg->X_add_number;
+  switch (arg->X_op)
+    {
+    case O_register:
+      if (arg->X_md)
+	{
+	  if (rnum != REG_HL)
+	    {
+	      ill_op ();
+	      break;
+	    }
+	  else
+	    rnum = 6;
+	}
+      else
+	{
+	  if ((prefix == 0) && (rnum & R_INDEX))
+	    {
+	      prefix = (rnum & R_IX) ? 0xDD : 0xFD;
+	      check_mach (INS_UNDOC);
+	      rnum &= ~R_INDEX;
+	    }
+	  if (rnum > 7)
+	    {
+	      ill_op ();
+	      break;
+	    }
+	}
+      q = frag_more (prefix ? 2 : 1);
+      if (prefix)
+	* q ++ = prefix;
+      * q ++ = opcode + (rnum << shift);
+      break;
+    case O_md1:
+      q = frag_more (2);
+      *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
+      *q = (prefix) ? prefix : (opcode + (6 << shift));
+      emit_byte (symbol_get_value_expression (arg->X_add_symbol),
+		 BFD_RELOC_Z80_DISP8);
+      if (prefix)
+	{
+	  q = frag_more (1);
+	  *q = opcode+(6<<shift);
+	}
+      break;
+    default:
+      abort ();
+    }
+}
+
+/* The operand m may be r, (hl), (ix+d), (iy+d),
+   if 0 = prefix m may also be ixl, ixh, iyl, iyh.  */
+static const char *
+emit_m (char prefix, char opcode, const char *args)
+{
+  expressionS arg_m;
+  const char *p;
+
+  p = parse_exp (args, &arg_m);
+  switch (arg_m.X_op)
+    {
+    case O_md1:
+    case O_register:
+      emit_mx (prefix, opcode, 0, &arg_m);
+      break;
+    default:
+      ill_op ();
+    }
+  return p;
+}
+
+/* The operand m may be as above or one of the undocumented
+   combinations (ix+d),r and (iy+d),r (if unportable instructions
+   are allowed).  */
+static const char *
+emit_mr (char prefix, char opcode, const char *args)
+{
+  expressionS arg_m, arg_r;
+  const char *p;
+
+  p = parse_exp (args, & arg_m);
+
+  switch (arg_m.X_op)
+    {
+    case O_md1:
+      if (*p == ',')
+	{
+	  p = parse_exp (p + 1, & arg_r);
+
+	  if ((arg_r.X_md == 0)
+	      && (arg_r.X_op == O_register)
+	      && (arg_r.X_add_number < 8))
+	    opcode += arg_r.X_add_number-6; /* Emit_mx () will add 6.  */
+	  else
+	    {
+	      ill_op ();
+	      break;
+	    }
+	  check_mach (INS_UNPORT);
+	}
+    case O_register:
+      emit_mx (prefix, opcode, 0, & arg_m);
+      break;
+    default:
+      ill_op ();
+    }
+  return p;
+}
+
+static void
+emit_sx (char prefix, char opcode, expressionS * arg_p)
+{
+  char *q;
+
+  switch (arg_p->X_op)
+    {
+    case O_register:
+    case O_md1:
+      emit_mx (prefix, opcode, 0, arg_p);
+      break;
+    default:
+      if (arg_p->X_md)
+	ill_op ();
+      else
+	{
+	  q = frag_more (prefix ? 2 : 1);
+	  if (prefix)
+	    *q++ = prefix;
+	  *q = opcode ^ 0x46;
+	  emit_byte (arg_p, BFD_RELOC_8);
+	}
+    }
+}
+
+/* The operand s may be r, (hl), (ix+d), (iy+d), n.  */
+static const char *
+emit_s (char prefix, char opcode, const char *args)
+{
+  expressionS arg_s;
+  const char *p;
+
+  p = parse_exp (args, & arg_s);
+  emit_sx (prefix, opcode, & arg_s);
+  return p;
+}
+
+static const char *
+emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  expressionS addr;
+  const char *p;  char *q;
+
+  p = parse_exp (args, &addr);
+  if (addr.X_md)
+    ill_op ();
+  else
+    {
+      q = frag_more (1);
+      *q = opcode;
+      emit_word (& addr);
+    }
+  return p;
+}
+
+/* Operand may be rr, r, (hl), (ix+d), (iy+d).  */
+static const char *
+emit_incdec (char prefix, char opcode, const char * args)
+{
+  expressionS operand;
+  int rnum;
+  const char *p;  char *q;
+
+  p = parse_exp (args, &operand);
+  rnum = operand.X_add_number;
+  if ((! operand.X_md)
+      && (operand.X_op == O_register)
+      && (R_ARITH&rnum))
+    {
+      q = frag_more ((rnum & R_INDEX) ? 2 : 1);
+      if (rnum & R_INDEX)
+	*q++ = (rnum & R_IX) ? 0xDD : 0xFD;
+      *q = prefix + ((rnum & 3) << 4);
+    }
+  else
+    {
+      if ((operand.X_op == O_md1) || (operand.X_op == O_register))
+	emit_mx (0, opcode, 3, & operand);
+      else
+	ill_op ();
+    }
+  return p;
+}
+
+static const char *
+emit_jr (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  expressionS addr;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, &addr);
+  if (addr.X_md)
+    ill_op ();
+  else
+    {
+      q = frag_more (1);
+      *q = opcode;
+      emit_byte (&addr, BFD_RELOC_8_PCREL);
+    }
+  return p;
+}
+
+static const char *
+emit_jp (char prefix, char opcode, const char * args)
+{
+  expressionS addr;
+  const char *p;
+  char *q;
+  int rnum;
+
+  p = parse_exp (args, & addr);
+  if (addr.X_md)
+    {
+      rnum = addr.X_add_number;
+      if ((addr.X_op == O_register && (rnum & ~R_INDEX) == REG_HL)
+	 /* An operand (i[xy]) would have been rewritten to (i[xy]+0)
+            in parse_exp ().  */
+	  || (addr.X_op == O_md1 && addr.X_add_symbol == zero))
+	{
+	  q = frag_more ((rnum & R_INDEX) ? 2 : 1);
+	  if (rnum & R_INDEX)
+	    *q++ = (rnum & R_IX) ? 0xDD : 0xFD;
+	  *q = prefix;
+	}
+      else
+	ill_op ();
+    }
+  else
+    {
+      q = frag_more (1);
+      *q = opcode;
+      emit_word (& addr);
+    }
+  return p;
+}
+
+static const char *
+emit_im (char prefix, char opcode, const char * args)
+{
+  expressionS mode;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, & mode);
+  if (mode.X_md || (mode.X_op != O_constant))
+    ill_op ();
+  else
+    switch (mode.X_add_number)
+      {
+      case 1:
+      case 2:
+	++mode.X_add_number;
+	/* Fall through.  */
+      case 0:
+	q = frag_more (2);
+	*q++ = prefix;
+	*q = opcode + 8*mode.X_add_number;
+	break;
+      default:
+	ill_op ();
+      }
+  return p;
+}
+
+static const char *
+emit_pop (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  expressionS regp;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, & regp);
+  if ((!regp.X_md)
+      && (regp.X_op == O_register)
+      && (regp.X_add_number & R_STACKABLE))
+    {
+      int rnum;
+
+      rnum = regp.X_add_number;
+      if (rnum&R_INDEX)
+	{
+	  q = frag_more (2);
+	  *q++ = (rnum&R_IX)?0xDD:0xFD;
+	}
+      else
+	q = frag_more (1);
+      *q = opcode + ((rnum & 3) << 4);
+    }
+  else
+    ill_op ();
+
+  return p;
+}
+
+static const char *
+emit_retcc (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  char cc, *q;
+  const char *p;
+
+  p = parse_cc (args, &cc);
+  q = frag_more (1);
+  if (p)
+    *q = opcode + cc;
+  else
+    *q = prefix;
+  return p ? p : args;
+}
+
+static const char *
+emit_adc (char prefix, char opcode, const char * args)
+{
+  expressionS term;
+  int rnum;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, &term);
+  if (*p++ != ',')
+    {
+      error (_("bad intruction syntax"));
+      return p;
+    }
+
+  if ((term.X_md) || (term.X_op != O_register))
+    ill_op ();
+  else
+    switch (term.X_add_number)
+      {
+      case REG_A:
+	p = emit_s (0, prefix, p);
+	break;
+      case REG_HL:
+	p = parse_exp (p, &term);
+	if ((!term.X_md) && (term.X_op == O_register))
+	  {
+	    rnum = term.X_add_number;
+	    if (R_ARITH == (rnum & (R_ARITH | R_INDEX)))
+	      {
+		q = frag_more (2);
+		*q++ = 0xED;
+		*q = opcode + ((rnum & 3) << 4);
+		break;
+	      }
+	  }
+	/* Fall through.  */
+      default:
+	ill_op ();
+      }
+  return p;
+}
+
+static const char *
+emit_add (char prefix, char opcode, const char * args)
+{
+  expressionS term;
+  int lhs, rhs;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, &term);
+  if (*p++ != ',')
+    {
+      error (_("bad intruction syntax"));
+      return p;
+    }
+
+  if ((term.X_md) || (term.X_op != O_register))
+    ill_op ();
+  else
+    switch (term.X_add_number & ~R_INDEX)
+      {
+      case REG_A:
+	p = emit_s (0, prefix, p);
+	break;
+      case REG_HL:
+	lhs = term.X_add_number;
+	p = parse_exp (p, &term);
+	if ((!term.X_md) && (term.X_op == O_register))
+	  {
+	    rhs = term.X_add_number;
+	    if ((rhs & R_ARITH)
+		&& ((rhs == lhs) || ((rhs & ~R_INDEX) != REG_HL)))
+	      {
+		q = frag_more ((lhs & R_INDEX) ? 2 : 1);
+		if (lhs & R_INDEX)
+		  *q++ = (lhs & R_IX) ? 0xDD : 0xFD;
+		*q = opcode + ((rhs & 3) << 4);
+		break;
+	      }
+	  }
+	/* Fall through.  */
+      default:
+	ill_op ();
+      }
+  return p;
+}
+
+static const char *
+emit_bit (char prefix, char opcode, const char * args)
+{
+  expressionS b;
+  int bn;
+  const char *p;
+
+  p = parse_exp (args, &b);
+  if (*p++ != ',')
+    error (_("bad intruction syntax"));
+
+  bn = b.X_add_number;
+  if ((!b.X_md)
+      && (b.X_op == O_constant)
+      && (0 <= bn)
+      && (bn < 8))
+    {
+      if (opcode == 0x40)
+	/* Bit : no optional third operand.  */
+	p = emit_m (prefix, opcode + (bn << 3), p);
+      else
+	/* Set, res : resulting byte can be copied to register.  */
+	p = emit_mr (prefix, opcode + (bn << 3), p);
+    }
+  else
+    ill_op ();
+  return p;
+}
+
+static const char *
+emit_jpcc (char prefix, char opcode, const char * args)
+{
+  char cc;
+  const char *p;
+
+  p = parse_cc (args, & cc);
+  if (p && *p++ == ',')
+    p = emit_call (0, opcode + cc, p);
+  else
+    p = (prefix == (char)0xC3)
+      ? emit_jp (0xE9, prefix, args)
+      : emit_call (0, prefix, args);
+  return p;
+}
+
+static const char *
+emit_jrcc (char prefix, char opcode, const char * args)
+{
+  char cc;
+  const char *p;
+
+  p = parse_cc (args, &cc);
+  if (p && *p++ == ',')
+    {
+      if (cc > (3 << 3))
+	error (_("condition code invalid for jr"));
+      else
+	p = emit_jr (0, opcode + cc, p);
+    }
+  else
+    p = emit_jr (0, prefix, args);
+
+  return p;
+}
+
+static const char *
+emit_ex (char prefix_in ATTRIBUTE_UNUSED,
+	 char opcode_in ATTRIBUTE_UNUSED, const char * args)
+{
+  expressionS op;
+  const char * p;
+  char prefix, opcode;
+
+  p = parse_exp (args, &op);
+  p = skip_space (p);
+  if (*p++ != ',')
+    {
+      error (_("bad instruction syntax"));
+      return p;
+    }
+
+  prefix = opcode = 0;
+  if (op.X_op == O_register)
+    switch (op.X_add_number | (op.X_md ? 0x8000 : 0))
+      {
+      case REG_AF:
+	if (TOLOWER (*p++) == 'a' && TOLOWER (*p++) == 'f')
+	  {
+	    /* The scrubber changes '\'' to '`' in this context.  */
+	    if (*p == '`')
+	      ++p;
+	    opcode = 0x08;
+	  }
+	break;
+      case REG_DE:
+	if (TOLOWER (*p++) == 'h' && TOLOWER (*p++) == 'l')
+	  opcode = 0xEB;
+	break;
+      case REG_SP|0x8000:
+	p = parse_exp (p, & op);
+	if (op.X_op == O_register
+	    && op.X_md == 0
+	    && (op.X_add_number & ~R_INDEX) == REG_HL)
+	  {
+	    opcode = 0xE3;
+	    if (R_INDEX & op.X_add_number)
+	      prefix = (R_IX & op.X_add_number) ? 0xDD : 0xFD;
+	  }
+	break;
+      }
+  if (opcode)
+    emit_insn (prefix, opcode, p);
+  else
+    ill_op ();
+
+  return p;
+}
+
+static const char *
+emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
+	const char * args)
+{
+  expressionS reg, port;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, &reg);
+  if (*p++ != ',')
+    {
+      error (_("bad intruction syntax"));
+      return p;
+    }
+
+  p = parse_exp (p, &port);
+  if (reg.X_md == 0
+      && reg.X_op == O_register
+      && (reg.X_add_number <= 7 || reg.X_add_number == REG_F)
+      && (port.X_md))
+    {
+      if (port.X_op != O_md1 && port.X_op != O_register)
+	{
+	  if (REG_A == reg.X_add_number)
+	    {
+	      q = frag_more (1);
+	      *q = 0xDB;
+	      emit_byte (&port, BFD_RELOC_8);
+	    }
+	  else
+	    ill_op ();
+	}
+      else
+	{
+	  if (port.X_add_number == REG_C)
+	    {
+	      if (reg.X_add_number == REG_F)
+		check_mach (INS_UNDOC);
+	      else
+		{
+		  q = frag_more (2);
+		  *q++ = 0xED;
+		  *q = 0x40|((reg.X_add_number&7)<<3);
+		}
+	    }
+	  else
+	    ill_op ();
+	}
+    }
+  else
+    ill_op ();
+  return p;
+}
+
+static const char *
+emit_out (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
+	 const char * args)
+{
+  expressionS reg, port;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, & port);
+  if (*p++ != ',')
+    {
+      error (_("bad intruction syntax"));
+      return p;
+    }
+  p = parse_exp (p, &reg);
+  if (!port.X_md)
+    { ill_op (); return p; }
+  /* Allow "out (c), 0" as unportable instruction.  */
+  if (reg.X_op == O_constant && reg.X_add_number == 0)
+    {
+      check_mach (INS_UNPORT);
+      reg.X_op = O_register;
+      reg.X_add_number = 6;
+    }
+  if (reg.X_md
+      || reg.X_op != O_register
+      || reg.X_add_number > 7)
+    ill_op ();
+  else
+    if (port.X_op != O_register && port.X_op != O_md1)
+      {
+	if (REG_A == reg.X_add_number)
+	  {
+	    q = frag_more (1);
+	    *q = 0xD3;
+	    emit_byte (&port, BFD_RELOC_8);
+	  }
+	else
+	  ill_op ();
+      }
+    else
+      {
+	if (REG_C == port.X_add_number)
+	  {
+	    q = frag_more (2);
+	    *q++ = 0xED;
+	    *q = 0x41 | (reg.X_add_number << 3);
+	  }
+	else
+	  ill_op ();
+      }
+  return p;
+}
+
+static const char *
+emit_rst (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  expressionS addr;
+  const char *p;
+  char *q;
+
+  p = parse_exp (args, &addr);
+  if (addr.X_op != O_constant)
+    {
+      error ("rst needs constant address");
+      return p;
+    }
+
+  if (addr.X_add_number & ~(7 << 3))
+    ill_op ();
+  else
+    {
+      q = frag_more (1);
+      *q = opcode + (addr.X_add_number & (7 << 3));
+    }
+  return p;
+}
+
+static void
+emit_ldxhl (char prefix, char opcode, expressionS *src, expressionS *d)
+{
+  char *q;
+
+  if (src->X_md)
+    ill_op ();
+  else
+    {
+      if (src->X_op == O_register)
+	{
+	  if (src->X_add_number>7)
+	    ill_op ();
+	  if (prefix)
+	    {
+	      q = frag_more (2);
+	      *q++ = prefix;
+	    }
+	  else
+	q = frag_more (1);
+	  *q = opcode + src->X_add_number;
+	  if (d)
+	    emit_byte (d, BFD_RELOC_Z80_DISP8);
+	}
+      else
+	{
+	  if (prefix)
+	    {
+	      q = frag_more (2);
+	      *q++ = prefix;
+	    }
+	  else
+	    q = frag_more (1);
+	  *q = opcode^0x46;
+	  if (d)
+	    emit_byte (d, BFD_RELOC_Z80_DISP8);
+	  emit_byte (src, BFD_RELOC_8);
+	}
+    }
+}
+
+static void
+emit_ldreg (int dest, expressionS * src)
+{
+  char *q;
+  int rnum;
+
+  switch (dest)
+    {
+      /* 8 Bit ld group:  */
+    case REG_I:
+    case REG_R:
+      if (src->X_md == 0 && src->X_op == O_register && src->X_add_number == REG_A)
+	{
+	  q = frag_more (2);
+	  *q++ = 0xED;
+	  *q = (dest == REG_I) ? 0x47 : 0x4F;
+	}
+      else
+	ill_op ();
+      break;
+
+    case REG_A:
+      if ((src->X_md) && src->X_op != O_register && src->X_op != O_md1)
+	{
+	  q = frag_more (1);
+	  *q = 0x3A;
+	  emit_word (src);
+	  break;
+	}
+
+      if ((src->X_md)
+	  && src->X_op == O_register
+	  && (src->X_add_number == REG_BC || src->X_add_number == REG_DE))
+	{
+	  q = frag_more (1);
+	  *q = 0x0A + ((dest & 1) << 4);
+	  break;
+	}
+
+      if ((!src->X_md)
+	  && src->X_op == O_register
+	  && (src->X_add_number == REG_R || src->X_add_number == REG_I))
+	{
+	  q = frag_more (2);
+	  *q++ = 0xED;
+	  *q = (src->X_add_number == REG_I) ? 0x57 : 0x5F;
+	  break;
+	}
+      /* Fall through.  */
+    case REG_B:
+    case REG_C:
+    case REG_D:
+    case REG_E:
+      emit_sx (0, 0x40 + (dest << 3), src);
+      break;
+
+    case REG_H:
+    case REG_L:
+      if ((src->X_md == 0)
+	  && (src->X_op == O_register)
+	  && (src->X_add_number & R_INDEX))
+	ill_op ();
+      else
+	emit_sx (0, 0x40 + (dest << 3), src);
+      break;
+
+    case R_IX | REG_H:
+    case R_IX | REG_L:
+    case R_IY | REG_H:
+    case R_IY | REG_L:
+      if (src->X_md)
+	{
+	  ill_op ();
+	  break;
+	}
+      check_mach (INS_UNDOC);
+      if (src-> X_op == O_register)
+	{
+	  rnum = src->X_add_number;
+	  if ((rnum & ~R_INDEX) < 8
+	      && ((rnum & R_INDEX) == (dest & R_INDEX)
+		   || (   (rnum & ~R_INDEX) != REG_H
+		       && (rnum & ~R_INDEX) != REG_L)))
+	    {
+	      q = frag_more (2);
+	      *q++ = (dest & R_IX) ? 0xDD : 0xFD;
+	      *q = 0x40 + ((dest & 0x07) << 3) + (rnum & 7);
+	    }
+	  else
+	    ill_op ();
+	}
+      else
+	{
+	  q = frag_more (2);
+	  *q++ = (dest & R_IX) ? 0xDD : 0xFD;
+	  *q = 0x06 + ((dest & 0x07) << 3);
+	  emit_byte (src, BFD_RELOC_8);
+	}
+      break;
+
+      /* 16 Bit ld group:  */
+    case REG_SP:
+      if (src->X_md == 0
+	  && src->X_op == O_register
+	  && REG_HL == (src->X_add_number &~ R_INDEX))
+	{
+	  q = frag_more ((src->X_add_number & R_INDEX) ? 2 : 1);
+	  if (src->X_add_number & R_INDEX)
+	    *q++ = (src->X_add_number & R_IX) ? 0xDD : 0xFD;
+	  *q = 0xF9;
+	  break;
+	}
+      /* Fall through.  */
+    case REG_BC:
+    case REG_DE:
+      if (src->X_op == O_register || src->X_op == O_md1)
+	ill_op ();
+      q = frag_more (src->X_md ? 2 : 1);
+      if (src->X_md)
+	{
+	  *q++ = 0xED;
+	  *q = 0x4B + ((dest & 3) << 4);
+	}
+      else
+	*q = 0x01 + ((dest & 3) << 4);
+      emit_word (src);
+      break;
+
+    case REG_HL:
+    case REG_HL | R_IX:
+    case REG_HL | R_IY:
+      if (src->X_op == O_register || src->X_op == O_md1)
+	ill_op ();
+      q = frag_more ((dest & R_INDEX) ? 2 : 1);
+      if (dest & R_INDEX)
+	* q ++ = (dest & R_IX) ? 0xDD : 0xFD;
+      *q = (src->X_md) ? 0x2A : 0x21;
+      emit_word (src);
+      break;
+
+    case REG_AF:
+    case REG_F:
+      ill_op ();
+      break;
+
+    default:
+      abort ();
+    }
+}
+
+static const char *
+emit_ld (char prefix_in ATTRIBUTE_UNUSED, char opcode_in ATTRIBUTE_UNUSED,
+	const char * args)
+{
+  expressionS dst, src;
+  const char *p;
+  char *q;
+  char prefix, opcode;
+
+  p = parse_exp (args, &dst);
+  if (*p++ != ',')
+    error (_("bad intruction syntax"));
+  p = parse_exp (p, &src);
+
+  switch (dst.X_op)
+    {
+    case O_md1:
+      emit_ldxhl ((dst.X_add_number & R_IX) ? 0xDD : 0xFD, 0x70,
+		  &src, symbol_get_value_expression (dst.X_add_symbol));
+      break;
+
+    case O_register:
+      if (dst.X_md)
+	{
+	  switch (dst.X_add_number)
+	    {
+	    case REG_BC:
+	    case REG_DE:
+	      if (src.X_md == 0 && src.X_op == O_register && src.X_add_number == REG_A)
+		{
+		  q = frag_more (1);
+		  *q = 0x02 + ( (dst.X_add_number & 1) << 4);
+		}
+	      else
+		ill_op ();
+	      break;
+	    case REG_HL:
+	      emit_ldxhl (0, 0x70, &src, NULL);
+	      break;
+	    default:
+	      ill_op ();
+	    }
+	}
+      else
+	emit_ldreg (dst.X_add_number, &src);
+      break;
+
+    default:
+      if (src.X_md != 0 || src.X_op != O_register)
+	ill_op ();
+      prefix = opcode = 0;
+      switch (src.X_add_number)
+	{
+	case REG_A:
+	  opcode = 0x32; break;
+	case REG_BC: case REG_DE: case REG_SP:
+	  prefix = 0xED; opcode = 0x43 + ((src.X_add_number&3)<<4); break;
+	case REG_HL:
+	  opcode = 0x22; break;
+	case REG_HL|R_IX:
+	  prefix = 0xDD; opcode = 0x22; break;
+	case REG_HL|R_IY:
+	  prefix = 0xFD; opcode = 0x22; break;
+	}
+      if (opcode)
+	{
+	  q = frag_more (prefix?2:1);
+	  if (prefix)
+	    *q++ = prefix;
+	  *q = opcode;
+	  emit_word (&dst);
+	}
+      else
+	ill_op ();
+    }
+  return p;
+}
+
+static void
+emit_data (int size ATTRIBUTE_UNUSED)
+{
+  const char *p, *q;
+  char *u, quote;
+  int cnt;
+  expressionS exp;
+
+  if (is_it_end_of_statement ())
+    {
+      demand_empty_rest_of_line ();
+      return;
+    }
+  p = skip_space (input_line_pointer);
+
+  do
+    {
+      if (*p == '\"' || *p == '\'')
+	{
+	    for (quote = *p, q = ++p, cnt = 0; *p && quote != *p; ++p, ++cnt)
+	      ;
+	    u = frag_more (cnt);
+	    memcpy (u, q, cnt);
+	    if (!*p)
+	      as_warn (_("unterminated string"));
+	    else
+	      p = skip_space (p+1);
+	}
+      else
+	{
+	  p = parse_exp (p, &exp);
+	  if (exp.X_op == O_md1 || exp.X_op == O_register)
+	    {
+	      ill_op ();
+	      break;
+	    }
+	  if (exp.X_md)
+	    as_warn (_("parentheses ignored"));
+	  emit_byte (&exp, BFD_RELOC_8);
+	  p = skip_space (p);
+	}
+    }
+  while (*p++ == ',') ;
+  input_line_pointer = (char *)(p-1);
+}
+
+static const char *
+emit_mulub (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  const char *p;
+
+  p = skip_space (args);
+  if (TOLOWER (*p++) != 'a' || *p++ != ',')
+    ill_op ();
+  else
+    {
+      char *q, reg;
+
+      reg = TOLOWER (*p++);
+      switch (reg)
+	{
+	case 'b':
+	case 'c':
+	case 'd':
+	case 'e':
+	  check_mach (INS_R800);
+	  if (!*skip_space (p))
+	    {
+	      q = frag_more (2);
+	      *q++ = prefix;
+	      *q = opcode + ((reg - 'b') << 3);
+	      break;
+	    }
+	default:
+	  ill_op ();
+	}
+    }
+  return p;
+}
+
+static const char *
+emit_muluw (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+  const char *p;
+
+  p = skip_space (args);
+  if (TOLOWER (*p++) != 'h' || TOLOWER (*p++) != 'l' || *p++ != ',')
+    ill_op ();
+  else
+    {
+      expressionS reg;
+      char *q;
+
+      p = parse_exp (p, & reg);
+
+      if ((!reg.X_md) && reg.X_op == O_register)
+	switch (reg.X_add_number)
+	  {
+	  case REG_BC:
+	  case REG_SP:
+	    check_mach (INS_R800);
+	    q = frag_more (2);
+	    *q++ = prefix;
+	    *q = opcode + ((reg.X_add_number & 3) << 4);
+	    break;
+	  default:
+	    ill_op ();
+	  }
+    }
+  return p;
+}
+
+/* Port specific pseudo ops.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+  { "db" , emit_data, 1},
+  { "d24", cons, 3},
+  { "d32", cons, 4},
+  { "def24", cons, 3},
+  { "def32", cons, 4},
+  { "defb", emit_data, 1},  
+  { "defs", s_space, 1}, /* Synonym for ds on some assemblers.  */
+  { "defw", cons, 2},
+  { "ds",   s_space, 1}, /* Fill with bytes rather than words.  */
+  { "dw", cons, 2},
+  { "psect", obj_coff_section, 0}, /* TODO: Translate attributes.  */
+  { "set", 0, 0}, 		/* Real instruction on z80.  */
+  { NULL, 0, 0 }
+} ;
+
+static table_t instab[] =
+{
+  { "adc",  0x88, 0x4A, emit_adc },
+  { "add",  0x80, 0x09, emit_add },
+  { "and",  0x00, 0xA0, emit_s },
+  { "bit",  0xCB, 0x40, emit_bit },
+  { "call", 0xCD, 0xC4, emit_jpcc },
+  { "ccf",  0x00, 0x3F, emit_insn },
+  { "cp",   0x00, 0xB8, emit_s },
+  { "cpd",  0xED, 0xA9, emit_insn },
+  { "cpdr", 0xED, 0xB9, emit_insn },
+  { "cpi",  0xED, 0xA1, emit_insn },
+  { "cpir", 0xED, 0xB1, emit_insn },
+  { "cpl",  0x00, 0x2F, emit_insn },
+  { "daa",  0x00, 0x27, emit_insn },
+  { "dec",  0x0B, 0x05, emit_incdec },
+  { "di",   0x00, 0xF3, emit_insn },
+  { "djnz", 0x00, 0x10, emit_jr },
+  { "ei",   0x00, 0xFB, emit_insn },
+  { "ex",   0x00, 0x00, emit_ex},
+  { "exx",  0x00, 0xD9, emit_insn },
+  { "halt", 0x00, 0x76, emit_insn },
+  { "im",   0xED, 0x46, emit_im },
+  { "in",   0x00, 0x00, emit_in },
+  { "inc",  0x03, 0x04, emit_incdec },
+  { "ind",  0xED, 0xAA, emit_insn },
+  { "indr", 0xED, 0xBA, emit_insn },
+  { "ini",  0xED, 0xA2, emit_insn },
+  { "inir", 0xED, 0xB2, emit_insn },
+  { "jp",   0xC3, 0xC2, emit_jpcc },
+  { "jr",   0x18, 0x20, emit_jrcc },
+  { "ld",   0x00, 0x00, emit_ld },
+  { "ldd",  0xED, 0xA8, emit_insn },
+  { "lddr", 0xED, 0xB8, emit_insn },
+  { "ldi",  0xED, 0xA0, emit_insn },
+  { "ldir", 0xED, 0xB0, emit_insn },
+  { "mulub", 0xED, 0xC5, emit_mulub }, /* R800 only.  */
+  { "muluw", 0xED, 0xC3, emit_muluw }, /* R800 only.  */
+  { "neg",  0xed, 0x44, emit_insn },
+  { "nop",  0x00, 0x00, emit_insn },
+  { "or",   0x00, 0xB0, emit_s },
+  { "otdr", 0xED, 0xBB, emit_insn },
+  { "otir", 0xED, 0xB3, emit_insn },
+  { "out",  0x00, 0x00, emit_out },
+  { "outd", 0xED, 0xAB, emit_insn },
+  { "outi", 0xED, 0xA3, emit_insn },
+  { "pop",  0x00, 0xC1, emit_pop },
+  { "push", 0x00, 0xC5, emit_pop },
+  { "res",  0xCB, 0x80, emit_bit },
+  { "ret",  0xC9, 0xC0, emit_retcc },
+  { "reti", 0xED, 0x4D, emit_insn },
+  { "retn", 0xED, 0x45, emit_insn },
+  { "rl",   0xCB, 0x10, emit_mr },
+  { "rla",  0x00, 0x17, emit_insn },
+  { "rlc",  0xCB, 0x00, emit_mr },
+  { "rlca", 0x00, 0x07, emit_insn },
+  { "rld",  0xED, 0x6F, emit_insn },
+  { "rr",   0xCB, 0x18, emit_mr },
+  { "rra",  0x00, 0x1F, emit_insn },
+  { "rrc",  0xCB, 0x08, emit_mr },
+  { "rrca", 0x00, 0x0F, emit_insn },
+  { "rrd",  0xED, 0x67, emit_insn },
+  { "rst",  0x00, 0xC7, emit_rst},
+  { "sbc",  0x98, 0x42, emit_adc },
+  { "scf",  0x00, 0x37, emit_insn },
+  { "set",  0xCB, 0xC0, emit_bit },
+  { "sla",  0xCB, 0x20, emit_mr },
+  { "sli",  0xCB, 0x30, emit_mr },
+  { "sll",  0xCB, 0x30, emit_mr },
+  { "sra",  0xCB, 0x28, emit_mr },
+  { "srl",  0xCB, 0x38, emit_mr },
+  { "sub",  0x00, 0x90, emit_s },
+  { "xor",  0x00, 0xA8, emit_s },
+} ;
+
+void
+md_assemble (char* str)
+{
+  const char *p;
+  char * old_ptr;
+  int i;
+  table_t *insp;
+
+  err_flag = 0;
+  old_ptr = input_line_pointer;
+  p = skip_space (str);
+  for (i = 0; (i < BUFLEN) && (ISALPHA (*p));)
+    buf[i++] = TOLOWER (*p++);
+
+  if (i == BUFLEN)
+    {
+      buf[BUFLEN-3] = buf[BUFLEN-2] = '.'; /* Mark opcode as abbreviated.  */
+      buf[BUFLEN-1] = 0;
+      as_bad (_("Unknown instruction '%s'"), buf);
+    }
+  else if ((*p) && (!ISSPACE (*p)))
+    as_bad (_("syntax error"));
+  else 
+    {
+      buf[i] = 0;
+      p = skip_space (p);
+      key = buf;
+      
+      insp = bsearch (&key, instab, ARRAY_SIZE (instab),
+		    sizeof (instab[0]), key_cmp);
+      if (!insp)
+	as_bad (_("Unknown instruction '%s'"), buf);
+      else
+	{
+	  p = insp->fp (insp->prefix, insp->opcode, p);
+	  p = skip_space (p);
+	if ((!err_flag) && *p)
+	  as_bad (_("junk at end of line, first unrecognized character is `%c'"),
+		  *p);
+	}
+    }
+  input_line_pointer = old_ptr;
+}
+
+void
+md_apply_fix (fixS * fixP, valueT* valP, segT seg ATTRIBUTE_UNUSED)
+{
+  long val = * (long *) valP;
+  char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
+
+  switch (fixP->fx_r_type)
+    {
+    case BFD_RELOC_8_PCREL:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+	  fixP->fx_no_overflow = (-128 <= val && val < 128);
+	  if (!fixP->fx_no_overflow)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("relative jump out of range"));
+	  *buf++ = val;
+          fixP->fx_done = 1;
+        }
+      break;
+
+    case BFD_RELOC_Z80_DISP8:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+	  fixP->fx_no_overflow = (-128 <= val && val < 128);
+	  if (!fixP->fx_no_overflow)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+			  _("index offset  out of range"));
+	  *buf++ = val;
+          fixP->fx_done = 1;
+        }
+      break;
+
+    case BFD_RELOC_8:
+      if (val > 255 || val < -128)
+	as_warn_where (fixP->fx_file, fixP->fx_line, _("overflow"));
+      *buf++ = val;
+      fixP->fx_no_overflow = 1; 
+      if (fixP->fx_addsy == NULL)
+	fixP->fx_done = 1;
+      break;
+
+    case BFD_RELOC_16:
+      *buf++ = val;
+      *buf++ = (val >> 8);
+      fixP->fx_no_overflow = 1; 
+      if (fixP->fx_addsy == NULL)
+	fixP->fx_done = 1;
+      break;
+
+    case BFD_RELOC_24: /* Def24 may produce this.  */
+      *buf++ = val;
+      *buf++ = (val >> 8);
+      *buf++ = (val >> 16);
+      fixP->fx_no_overflow = 1; 
+      if (fixP->fx_addsy == NULL)
+	fixP->fx_done = 1;
+      break;
+
+    case BFD_RELOC_32: /* Def32 and .long may produce this.  */
+      *buf++ = val;
+      *buf++ = (val >> 8);
+      *buf++ = (val >> 16);
+      *buf++ = (val >> 24);
+      if (fixP->fx_addsy == NULL)
+	fixP->fx_done = 1;
+      break;
+
+    default:
+      printf (_("md_apply_fix: unknown r_type 0x%x\n"), fixP->fx_r_type);
+      abort ();
+    }
+}
+
+/* GAS will call this to generate a reloc.  GAS will pass the
+   resulting reloc to `bfd_install_relocation'.  This currently works
+   poorly, as `bfd_install_relocation' often does the wrong thing, and
+   instances of `tc_gen_reloc' have been written to work around the
+   problems, which in turns makes it difficult to fix
+   `bfd_install_relocation'.  */
+
+/* If while processing a fixup, a reloc really
+   needs to be created then it is done here.  */
+
+arelent *
+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp)
+{
+  arelent *reloc;
+
+  if (! bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type))
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+		    _("reloc %d not supported by object file format"),
+		    (int) fixp->fx_r_type);
+      return NULL;
+    }
+
+  reloc               = xmalloc (sizeof (arelent));
+  reloc->sym_ptr_ptr  = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address      = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->howto        = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+  reloc->addend       = fixp->fx_offset;
+
+  return reloc;
+}
+
diff --git a/gas/config/tc-z80.h b/gas/config/tc-z80.h
new file mode 100644
index 000000000000..0021fb3943a7
--- /dev/null
+++ b/gas/config/tc-z80.h
@@ -0,0 +1,105 @@
+/* this is tc-z80.h
+   Copyright 2005 Free Software Foundation, Inc.
+
+   Contributed by Arnold Metselaar <arnold_m@operamail.com>
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of .the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef TC_Z80
+#define TC_Z80
+
+#define TARGET_ARCH   bfd_arch_z80
+#define BFD_ARCH      TARGET_ARCH
+#define COFF_MAGIC    0x5A80
+#define TARGET_MACH   0
+#define TARGET_BYTES_BIG_ENDIAN  0
+
+/* If you define this macro, GAS will warn about the
+   use of nonstandard escape sequences in a string.  */
+#define ONLY_STANDARD_ESCAPES
+
+/* GAS will call this function for any expression that can not be
+   recognized.  When the function is called, `input_line_pointer'
+   will point to the start of the expression.  */
+#define md_operand(x)
+
+/* This should just call either `number_to_chars_bigendian' or
+   `number_to_chars_littleendian', whichever is appropriate.  On
+   targets like the MIPS which support options to change the
+   endianness, which function to call is a runtime decision.  On
+   other targets, `md_number_to_chars' can be a simple macro.  */
+#define md_number_to_chars number_to_chars_littleendian
+
+#define TC_COUNT_RELOC(x) 1
+
+#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype (fixP)
+#define md_convert_frag(b,s,f)   as_fatal ("convert_frag called\n")
+#define md_estimate_size_before_relax(f,s) \
+  (as_fatal (_("estimate_size_before_relax called")), 1)
+
+/* Define some functions to be called by generic code.  */
+#define md_end               z80_md_end
+#define md_start_line_hook() { if (z80_start_line_hook ()) continue; }
+#define TC_CONS_FIX_NEW z80_cons_fix_new
+
+extern void z80_md_end (void);
+extern int z80_start_line_hook (void);
+extern void z80_cons_fix_new (fragS *, int, int, expressionS *);
+
+#define WORKING_DOT_WORD
+
+/* If you define this macro, it means that `tc_gen_reloc' may return
+   multiple relocation entries for a single fixup.  In this case, the
+   return value of `tc_gen_reloc' is a pointer to a null terminated
+   array.  */
+#undef RELOC_EXPANSION_POSSIBLE
+
+/* No shared lib support, so we don't need to ensure
+   externally visible symbols can be overridden.  */
+#define EXTERN_FORCE_RELOC 0
+
+/* Values passed to md_apply_fix3 don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define LISTING_WORD_SIZE 2
+
+/* A single '=' is accepted as a comparison operator.  */
+#define O_SINGLE_EQ O_eq
+
+/* A '$' is used to refer to the current location or as a hex. prefix.  */
+#define DOLLAR_DOT
+#define DOLLAR_AMBIGU                1
+#define LOCAL_LABELS_FB              1
+#define LITERAL_PREFIXPERCENT_BIN
+#define NUMBERS_WITH_SUFFIX          1
+#define NO_PSEUDO_DOT                1
+/* We allow single quotes to delimit character constants as
+   well, but it is cleaner to handle that in tc-z80.c.  */
+#define SINGLE_QUOTE_STRINGS
+#define NO_STRING_ESCAPES
+
+/* An `.lcomm' directive with no explicit alignment parameter will
+   use this macro to set P2VAR to the alignment that a request for
+   SIZE bytes will have.  The alignment is expressed as a power of
+   two.  If no alignment should take place, the macro definition
+   should do nothing.  Some targets define a `.bss' directive that is
+   also affected by this macro.  The default definition will set
+   P2VAR to the truncated power of two of sizes up to eight bytes.  */
+#define TC_IMPLICIT_LCOMM_ALIGNMENT(SIZE, P2VAR) (P2VAR) = 0
+
+#endif
diff --git a/gas/config/tc-z8k.c b/gas/config/tc-z8k.c
index f2aa9ad6115a..355ac12c2bbb 100644
--- a/gas/config/tc-z8k.c
+++ b/gas/config/tc-z8k.c
@@ -1,6 +1,6 @@
 /* tc-z8k.c -- Assemble code for the Zilog Z800n
-   Copyright 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, 2002, 2003,
+   2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,17 +16,17 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Written By Steve Chamberlain <sac@cygnus.com>.  */
 
-#define DEFINE_TABLE
 #include <stdio.h>
 
 #include "as.h"
 #include "bfd.h"
 #include "safe-ctype.h"
+#define DEFINE_TABLE
 #include "opcodes/z8k-opc.h"
 
 const char comment_chars[] = "!";
@@ -36,7 +36,6 @@ const char line_separator_chars[] = ";";
 extern int machine;
 extern int coff_flags;
 int segmented_mode;
-const int md_reloc_size;
 
 /* This is non-zero if target was set from the command line.  */
 static int z8k_target_from_cmdline;
@@ -47,14 +46,12 @@ s_segm (int segm)
   if (segm)
     {
       segmented_mode = 1;
-      machine = bfd_mach_z8001;
-      coff_flags = F_Z8001;
+      bfd_set_arch_mach (stdoutput, TARGET_ARCH, bfd_mach_z8001);
     }
   else
     {
       segmented_mode = 0;
-      machine = bfd_mach_z8002;
-      coff_flags = F_Z8002;
+      bfd_set_arch_mach (stdoutput, TARGET_ARCH, bfd_mach_z8002);
     }
 }
 
@@ -203,7 +200,7 @@ static int the_flags;
 static int the_interrupt;
 
 static char *
-whatreg (int *reg, char *src)
+whatreg (unsigned int *reg, char *src)
 {
   if (ISDIGIT (src[1]))
     {
@@ -631,13 +628,14 @@ get_operand (char **ptr, struct z8k_op *mode, unsigned int dst ATTRIBUTE_UNUSED)
     }
   else
     {
-      int regn;
+      unsigned int regn;
 
       end = parse_reg (src, &mode->mode, &regn);
 
       if (end)
 	{
-	  int nw, nr;
+	  int nw;
+	  unsigned int nr;
 
 	  src = end;
 	  if (*src == '(')
@@ -655,9 +653,6 @@ get_operand (char **ptr, struct z8k_op *mode, unsigned int dst ATTRIBUTE_UNUSED)
 		    src++;
 
 		  regaddr (mode->mode, "ra(rb) ra");
-#if 0
-		  regword (mode->mode, "ra(rb) rb");
-#endif
 		  mode->mode = CLASS_BX;
 		  mode->reg = regn;
 		  mode->x_reg = nr;
@@ -943,26 +938,24 @@ static void
 newfix (int ptr, int type, int size, expressionS *operand)
 {
   int is_pcrel = 0;
+  fixS *fixP;
 
-  /* size is in nibbles.  */
-
+  /* Size is in nibbles.  */
   if (operand->X_add_symbol
       || operand->X_op_symbol
       || operand->X_add_number)
     {
       switch(type)
         {
-        case R_JR:
-        case R_DISP7:
-        case R_CALLR:
+        case BFD_RELOC_8_PCREL:
+        case BFD_RELOC_Z8K_CALLR:
+        case BFD_RELOC_Z8K_DISP7:
           is_pcrel = 1;
         }
-      fix_new_exp (frag_now,
-		   ptr,
-		   size / 2,
-		   operand,
-		   is_pcrel,
-		   type);
+      fixP = fix_new_exp (frag_now, ptr, size / 2,
+                          operand, is_pcrel, type);
+      if (is_pcrel)
+	fixP->fx_no_overflow = 1;
     }
 }
 
@@ -995,8 +988,6 @@ apply_fix (char *ptr, int type, expressionS *operand, int size)
 
 /* Now we know what sort of opcodes it is.  Let's build the bytes.  */
 
-#define INSERT(x,y) *x++ = y>>24; *x++ = y>> 16; *x++=y>>8; *x++ =y;
-
 static void
 build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSED)
 {
@@ -1008,6 +999,9 @@ build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSE
   frag_wane (frag_now);
   frag_new (0);
 
+  if (frag_room () < 8)
+    frag_grow (8);  /* Make room for maximum instruction size.  */
+
   memset (buffer, 0, sizeof (buffer));
   class_ptr = this_try->byte_info;
 
@@ -1024,31 +1018,31 @@ build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSE
 	  if (segmented_mode)
 	    {
 	      /* da_operand->X_add_number |= 0x80000000;  --  Now set at relocation time.  */
-	      output_ptr = apply_fix (output_ptr, R_IMM32, da_operand, 8);
+	      output_ptr = apply_fix (output_ptr, BFD_RELOC_32, da_operand, 8);
 	    }
 	  else
 	    {
-	      output_ptr = apply_fix (output_ptr, R_IMM16, da_operand, 4);
+	      output_ptr = apply_fix (output_ptr, BFD_RELOC_16, da_operand, 4);
 	    }
 	  da_operand = 0;
 	  break;
 	case CLASS_DISP8:
 	  /* pc rel 8 bit  */
-	  output_ptr = apply_fix (output_ptr, R_JR, da_operand, 2);
+	  output_ptr = apply_fix (output_ptr, BFD_RELOC_8_PCREL, da_operand, 2);
 	  da_operand = 0;
 	  break;
 
 	case CLASS_0DISP7:
 	  /* pc rel 7 bit  */
 	  *output_ptr = 0;
-	  output_ptr = apply_fix (output_ptr, R_DISP7, da_operand, 2);
+	  output_ptr = apply_fix (output_ptr, BFD_RELOC_Z8K_DISP7, da_operand, 2);
 	  da_operand = 0;
 	  break;
 
 	case CLASS_1DISP7:
 	  /* pc rel 7 bit  */
 	  *output_ptr = 0x80;
-	  output_ptr = apply_fix (output_ptr, R_DISP7, da_operand, 2);
+	  output_ptr = apply_fix (output_ptr, BFD_RELOC_Z8K_DISP7, da_operand, 2);
 	  output_ptr[-2] = 0x8;
 	  da_operand = 0;
 	  break;
@@ -1108,13 +1102,13 @@ build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSE
           switch (c & ARG_MASK)
             {
             case ARG_DISP12:
-              output_ptr = apply_fix (output_ptr, R_CALLR, da_operand, 4);
+              output_ptr = apply_fix (output_ptr, BFD_RELOC_Z8K_CALLR, da_operand, 4);
               break;
             case ARG_DISP16:
-	      output_ptr = apply_fix (output_ptr, R_REL16, da_operand, 4);
+	      output_ptr = apply_fix (output_ptr, BFD_RELOC_16_PCREL, da_operand, 4);
 	      break;
 	    default:
-	      output_ptr = apply_fix (output_ptr, R_IMM16, da_operand, 4);
+	      output_ptr = apply_fix (output_ptr, BFD_RELOC_16, da_operand, 4);
 	    }
 	  da_operand = 0;
 	  break;
@@ -1125,11 +1119,9 @@ build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSE
 	      {
 	      case ARG_NIM4:
                 if (imm_operand->X_add_number > 15)
-                  {
-                    as_bad (_("immediate value out of range"));
-                  }
+		  as_bad (_("immediate value out of range"));
 		imm_operand->X_add_number = -imm_operand->X_add_number;
-		output_ptr = apply_fix (output_ptr, R_IMM4L, imm_operand, 1);
+		output_ptr = apply_fix (output_ptr, BFD_RELOC_Z8K_IMM4L, imm_operand, 1);
 		break;
               /*case ARG_IMMNMINUS1: not used.  */
 	      case ARG_IMM4M1:
@@ -1137,22 +1129,20 @@ build_bytes (opcode_entry_type *this_try, struct z8k_op *operand ATTRIBUTE_UNUSE
                 /* Drop through.  */
 	      case ARG_IMM4:
                 if (imm_operand->X_add_number > 15)
-                  {
-                    as_bad (_("immediate value out of range"));
-                  }
-		output_ptr = apply_fix (output_ptr, R_IMM4L, imm_operand, 1);
+		  as_bad (_("immediate value out of range"));
+		output_ptr = apply_fix (output_ptr, BFD_RELOC_Z8K_IMM4L, imm_operand, 1);
 		break;
 	      case ARG_NIM8:
 		imm_operand->X_add_number = -imm_operand->X_add_number;
                 /* Drop through.  */
 	      case ARG_IMM8:
-		output_ptr = apply_fix (output_ptr, R_IMM8, imm_operand, 2);
+		output_ptr = apply_fix (output_ptr, BFD_RELOC_8, imm_operand, 2);
 		break;
 	      case ARG_IMM16:
-		output_ptr = apply_fix (output_ptr, R_IMM16, imm_operand, 4);
+		output_ptr = apply_fix (output_ptr, BFD_RELOC_16, imm_operand, 4);
 		break;
 	      case ARG_IMM32:
-		output_ptr = apply_fix (output_ptr, R_IMM32, imm_operand, 8);
+		output_ptr = apply_fix (output_ptr, BFD_RELOC_32, imm_operand, 8);
 		break;
 	      default:
 		abort ();
@@ -1186,7 +1176,7 @@ md_assemble (char *str)
   char c;
   char *op_start;
   char *op_end;
-  struct z8k_op operand[3];
+  struct z8k_op operand[4];
   opcode_entry_type *opcode;
 
   /* Drop leading whitespace.  */
@@ -1243,11 +1233,12 @@ md_assemble (char *str)
 
       new_input_line_pointer = get_operands (opcode, op_end, operand);
       if (new_input_line_pointer)
-        input_line_pointer = new_input_line_pointer;
-
-      opcode = get_specific (opcode, operand);
+        {
+          input_line_pointer = new_input_line_pointer;
+          opcode = get_specific (opcode, operand);
+        }
 
-      if (opcode == 0)
+      if (new_input_line_pointer == NULL || opcode == NULL)
 	{
 	  /* Couldn't find an opcode which matched the operands.  */
 	  char *where = frag_more (2);
@@ -1263,12 +1254,6 @@ md_assemble (char *str)
     }
 }
 
-void
-tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_crawl_symbol_chain \n"));
-}
-
 /* We have no need to default values of symbols.  */
 
 symbolS *
@@ -1277,12 +1262,6 @@ md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
   return 0;
 }
 
-void
-tc_headers_hook (object_headers *headers ATTRIBUTE_UNUSED)
-{
-  printf (_("call to tc_headers_hook \n"));
-}
-
 /* Various routines to kill one day.  */
 /* Equal to MAX_PRECISION in atof-ieee.c.  */
 #define MAX_LITTLENUMS 6
@@ -1394,56 +1373,108 @@ md_show_usage (FILE *stream)
 }
 
 void
-md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
-                 segT seg ATTRIBUTE_UNUSED,
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+                 segT sec ATTRIBUTE_UNUSED,
                  fragS *fragP ATTRIBUTE_UNUSED)
 {
   printf (_("call to md_convert_frag\n"));
   abort ();
 }
 
+/* Generate a machine dependent reloc from a fixup.  */
+
+arelent*
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
+	      fixS *fixp      ATTRIBUTE_UNUSED)
+{
+  arelent *reloc;
+
+  reloc = xmalloc (sizeof (*reloc));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
+  reloc->addend = fixp->fx_offset;
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+
+  if (! reloc->howto)
+    {
+      as_bad_where (fixp->fx_file, fixp->fx_line,
+                    "Cannot represent %s relocation in object file",
+                    bfd_get_reloc_code_name (fixp->fx_r_type));
+      abort ();
+    }
+  return reloc;
+}
+
 valueT
 md_section_align (segT seg, valueT size)
 {
-  return ((size + (1 << section_alignment[(int) seg]) - 1)
-	  & (-1 << section_alignment[(int) seg]));
+  int align = bfd_get_section_alignment (stdoutput, seg);
+  valueT mask = ((valueT) 1 << align) - 1;
+
+  return (size + mask) & ~mask;
 }
 
 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
    has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
    we will have to generate a reloc entry.  */
 void
-md_apply_fix3 (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
+md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
 {
   long val = * (long *) valP;
   char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
 
   switch (fixP->fx_r_type)
     {
-    case R_IMM4L:
-      buf[0] = (buf[0] & 0xf0) | (val & 0xf);
+    case BFD_RELOC_Z8K_IMM4L:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+	buf[0] = (buf[0] & 0xf0) | (val & 0xf);
       break;
 
-    case R_JR:
+    case BFD_RELOC_8:
       if (fixP->fx_addsy)
         {
           fixP->fx_no_overflow = 1;
           fixP->fx_done = 0;
         }
       else
+	*buf++ = val;
+      break;
+
+    case BFD_RELOC_16:
+      if (fixP->fx_addsy)
         {
-      if (val & 1)
-        as_bad (_("cannot branch to odd address"));
-      val /= 2;
-      if (val > 127 || val < -128)
-            as_warn (_("relative jump out of range"));
-      *buf++ = val;
-      fixP->fx_no_overflow = 1;
-          fixP->fx_done = 1;
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+          *buf++ = (val >> 8);
+          *buf++ = val;
         }
       break;
 
-    case R_DISP7:
+    case BFD_RELOC_32:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+          *buf++ = (val >> 24);
+          *buf++ = (val >> 16);
+          *buf++ = (val >> 8);
+          *buf++ = val;
+        }
+      break;
+
+    case BFD_RELOC_8_PCREL:
       if (fixP->fx_addsy)
         {
           fixP->fx_no_overflow = 1;
@@ -1452,17 +1483,38 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
       else
         {
           if (val & 1)
-            as_bad (_("cannot branch to odd address"));
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("cannot branch to odd address"));
           val /= 2;
-          if (val > 0 || val < -127)
-            as_bad (_("relative jump out of range"));
-          *buf = (*buf & 0x80) | (-val & 0x7f);
+          if (val > 127 || val < -128)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("relative jump out of range"));
+          *buf++ = val;
           fixP->fx_no_overflow = 1;
           fixP->fx_done = 1;
         }
       break;
 
-    case R_CALLR:
+    case BFD_RELOC_16_PCREL:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+          val = val - fixP->fx_frag->fr_address + fixP->fx_where - fixP->fx_size;
+          if (val > 32767 || val < -32768)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("relative address out of range"));
+          *buf++ = (val >> 8);
+          *buf++ = val;
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 1;
+        }
+      break;
+
+    case BFD_RELOC_Z8K_CALLR:
       if (fixP->fx_addsy)
         {
           fixP->fx_no_overflow = 1;
@@ -1471,9 +1523,11 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
       else
         {
           if (val & 1)
-            as_bad (_("cannot branch to odd address"));
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("cannot branch to odd address"));
           if (val > 4096 || val < -4095)
-            as_bad (_("relative call out of range"));
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("relative call out of range"));
           val = -val / 2;
           *buf = (*buf & 0xf0) | ((val >> 8) & 0xf);
           buf++;
@@ -1483,46 +1537,29 @@ md_apply_fix3 (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED)
         }
       break;
 
-    case R_IMM8:
-      *buf++ = val;
-      break;
-
-    case R_IMM16:
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-
-    case R_IMM32:
-      *buf++ = (val >> 24);
-      *buf++ = (val >> 16);
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-
-    case R_REL16:
-      val = val - fixP->fx_frag->fr_address + fixP->fx_where - fixP->fx_size;
-      if (val > 32767 || val < -32768)
-        as_bad (_("relative address out of range"));
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      fixP->fx_no_overflow = 1;
-      break;
-
-#if 0
-    case R_DA | R_SEG:
-      *buf++ = (val >> 16);
-      *buf++ = 0x00;
-      *buf++ = (val >> 8);
-      *buf++ = val;
-      break;
-#endif
-
-    case 0:
-      md_number_to_chars (buf, val, fixP->fx_size);
+    case BFD_RELOC_Z8K_DISP7:
+      if (fixP->fx_addsy)
+        {
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 0;
+        }
+      else
+        {
+          if (val & 1)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("cannot branch to odd address"));
+          val /= 2;
+          if (val > 0 || val < -127)
+            as_bad_where (fixP->fx_file, fixP->fx_line,
+                          _("relative jump out of range"));
+          *buf = (*buf & 0x80) | (-val & 0x7f);
+          fixP->fx_no_overflow = 1;
+          fixP->fx_done = 1;
+        }
       break;
 
     default:
-      printf(_("md_apply_fix3: unknown r_type 0x%x\n"), fixP->fx_r_type);
+      printf(_("md_apply_fix: unknown r_type 0x%x\n"), fixP->fx_r_type);
       abort ();
     }
 
@@ -1558,60 +1595,3 @@ void
 tc_coff_symbol_emit_hook (symbolS *s ATTRIBUTE_UNUSED)
 {
 }
-
-void
-tc_reloc_mangle (fixS *fix_ptr, struct internal_reloc *intr, bfd_vma base)
-{
-  symbolS *symbol_ptr;
-
-  if (fix_ptr->fx_addsy
-      && fix_ptr->fx_subsy)
-    {
-      symbolS *add = fix_ptr->fx_addsy;
-      symbolS *sub = fix_ptr->fx_subsy;
-
-      if (S_GET_SEGMENT (add) != S_GET_SEGMENT (sub))
-	as_bad (_("Can't subtract symbols in different sections %s %s"),
-		S_GET_NAME (add), S_GET_NAME (sub));
-      else
-	{
-	  int diff = S_GET_VALUE (add) - S_GET_VALUE (sub);
-
-	  fix_ptr->fx_addsy = 0;
-	  fix_ptr->fx_subsy = 0;
-	  fix_ptr->fx_offset += diff;
-	}
-    }
-  symbol_ptr = fix_ptr->fx_addsy;
-
-  /* If this relocation is attached to a symbol then it's ok
-     to output it.  */
-  if (fix_ptr->fx_r_type == 0)
-    {
-      /* cons likes to create reloc32's whatever the size of the reloc.  */
-      switch (fix_ptr->fx_size)
-	{
-	case 2:
-	  intr->r_type = R_IMM16;
-	  break;
-	case 1:
-	  intr->r_type = R_IMM8;
-	  break;
-	case 4:
-	  intr->r_type = R_IMM32;
-	  break;
-	default:
-	  abort ();
-	}
-    }
-  else
-    intr->r_type = fix_ptr->fx_r_type;
-
-  intr->r_vaddr = fix_ptr->fx_frag->fr_address + fix_ptr->fx_where + base;
-  intr->r_offset = fix_ptr->fx_offset;
-
-  if (symbol_ptr)
-    intr->r_symndx = symbol_ptr->sy_number;
-  else
-    intr->r_symndx = -1;
-}
diff --git a/gas/config/tc-z8k.h b/gas/config/tc-z8k.h
index 56ffd7489692..3765a15ae086 100644
--- a/gas/config/tc-z8k.h
+++ b/gas/config/tc-z8k.h
@@ -1,6 +1,6 @@
 /* This file is tc-z8k.h
    Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1995, 1997, 1998,
-   2000
+   2000, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,36 +17,25 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TC_Z8K
 #define TARGET_BYTES_BIG_ENDIAN 1
+#define TARGET_ARCH    bfd_arch_z8k
+#define TARGET_FORMAT  "coff-z8k"
 
 struct internal_reloc;
 
 #define WORKING_DOT_WORD
 
-#ifndef BFD_ASSEMBLER
-#define LOCAL_LABEL(x) 0
-#endif
-
-/* This macro translates between an internal fix and a coff reloc type.  */
-#define TC_COFF_FIX2RTYPE(fixP) abort ();
-
-#define BFD_ARCH bfd_arch_z8k
 #define COFF_MAGIC 0x8000
-#define TC_COUNT_RELOC(x) (1)
 #define IGNORE_NONSTANDARD_ESCAPES
 #undef WARN_SIGNED_OVERFLOW_WORD
 
-#define TC_RELOC_MANGLE(s,a,b,c) tc_reloc_mangle(a,b,c)
-extern void tc_reloc_mangle
-  PARAMS ((struct fix *, struct internal_reloc *, bfd_vma));
+#define tc_fix_adjustable(X)  0
 
-#define DO_NOT_STRIP 0
 #define LISTING_HEADER "Zilog Z8000 GAS "
-#define NEED_FX_R_TYPE 1
 #define RELOC_32 1234
 
 #define md_operand(x)
diff --git a/gas/config/te-386bsd.h b/gas/config/te-386bsd.h
index da2d692f72f4..ad7769c50b41 100644
--- a/gas/config/te-386bsd.h
+++ b/gas/config/te-386bsd.h
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TE_386BSD	1
 
diff --git a/gas/config/te-armeabi.h b/gas/config/te-armeabi.h
new file mode 100644
index 000000000000..74535931982b
--- /dev/null
+++ b/gas/config/te-armeabi.h
@@ -0,0 +1,8 @@
+/* The EABI requires the use of VFP.  */
+#define FPU_DEFAULT FPU_ARCH_VFP_V2
+#define EABI_DEFAULT EF_ARM_EABI_VER4
+
+#define LOCAL_LABELS_DOLLAR 1
+#define LOCAL_LABELS_FB 1
+
+#include "obj-format.h"
diff --git a/gas/config/te-armlinuxeabi.h b/gas/config/te-armlinuxeabi.h
new file mode 100644
index 000000000000..b3f5f1e78c5d
--- /dev/null
+++ b/gas/config/te-armlinuxeabi.h
@@ -0,0 +1,5 @@
+#include "te-linux.h"
+
+/* The EABI requires the use of VFP.  */
+#define FPU_DEFAULT FPU_ARCH_VFP_V2
+#define EABI_DEFAULT EF_ARM_EABI_VER4
diff --git a/gas/config/te-aux.h b/gas/config/te-aux.h
deleted file mode 100644
index 38445d9920ce..000000000000
--- a/gas/config/te-aux.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#define TE_AUX
-
-/* From obj-coff.h:
-   This internal_lineno crap is to stop namespace pollution from the
-   bfd internal coff headerfile.  */
-#define internal_lineno bfd_internal_lineno
-#include "coff/aux-coff.h"	/* override bits in coff/internal.h */
-#undef internal_lineno
-
-#define COFF_NOLOAD_PROBLEM
-#define KEEP_RELOC_INFO
-
-#include "obj-format.h"
-
-#ifndef LOCAL_LABELS_FB
-#define LOCAL_LABELS_FB 1
-#endif
diff --git a/gas/config/te-delt88.h b/gas/config/te-delt88.h
deleted file mode 100644
index 150518332ac7..000000000000
--- a/gas/config/te-delt88.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* This file is te-delta88.h.  */
-
-#define TE_DELTA88 1
-
-#define COFF_NOLOAD_PROBLEM	1
-
-/* Added these, because if we don't know what we're targeting we may
-   need an assembler version of libgcc, and that will use local
-   labels.  */
-#define LOCAL_LABELS_DOLLAR	1
-#define LOCAL_LABELS_FB		1
-
-#include "obj-format.h"
diff --git a/gas/config/te-delta.h b/gas/config/te-delta.h
deleted file mode 100644
index f88b71e560de..000000000000
--- a/gas/config/te-delta.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#define TE_DELTA
-
-#include "obj-format.h"
-
-#define COFF_NOLOAD_PROBLEM	1
-#define COFF_COMMON_ADDEND	1
-
-/* Added these, because if we don't know what we're targeting we may
-   need an assembler version of libgcc, and that will use local
-   labels.  */
-#define LOCAL_LABELS_DOLLAR	1
-#define LOCAL_LABELS_FB		1
-
-/* end of te-delta.h */
diff --git a/gas/config/te-dpx2.h b/gas/config/te-dpx2.h
deleted file mode 100644
index 5daeb9f036e4..000000000000
--- a/gas/config/te-dpx2.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Machine specific defines for the dpx2 machine.  */
-
-/* The magic number is not the usual MC68MAGIC.  */
-#define COFF_MAGIC       MC68KBCSMAGIC
-
-#define REGISTER_PREFIX_OPTIONAL 1
-
-#define TARGET_FORMAT "coff-m68k-un"
-
-#include "obj-format.h"
-
-/* end of te-dpx2.h */
diff --git a/gas/config/te-freebsd.h b/gas/config/te-freebsd.h
index 6992561bd592..eb16f3c46389 100644
--- a/gas/config/te-freebsd.h
+++ b/gas/config/te-freebsd.h
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Target environment for FreeBSD.  It is the same as the generic
    target, except that it arranges via the TE_FreeBSD define to
diff --git a/gas/config/te-gnu.h b/gas/config/te-gnu.h
new file mode 100644
index 000000000000..1d1d44278617
--- /dev/null
+++ b/gas/config/te-gnu.h
@@ -0,0 +1,4 @@
+#define TE_GNU
+#define LOCAL_LABELS_FB 1
+
+#include "obj-format.h"
diff --git a/gas/config/te-hp300.h b/gas/config/te-hp300.h
deleted file mode 100644
index 1680d279fdb7..000000000000
--- a/gas/config/te-hp300.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/* te-hp300.h -- hpux 9000/300 target environment declarations.
-   Copyright 1987, 1990, 1991, 1992, 1993, 1995, 2000
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#define LOCAL_LABELS_DOLLAR 1
-#define LOCAL_LABELS_FB 1
-
-#include "obj-format.h"
-
-/* end of te-hp300.h */
diff --git a/gas/config/te-hppa.h b/gas/config/te-hppa.h
index 703b2e06e3fc..5215e2881531 100644
--- a/gas/config/te-hppa.h
+++ b/gas/config/te-hppa.h
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* HP PA-RISC and OSF/1 support was contributed by the Center for
 	Software Science at the University of Utah.  */
diff --git a/gas/config/te-ic960.h b/gas/config/te-ic960.h
deleted file mode 100644
index b1275abb5206..000000000000
--- a/gas/config/te-ic960.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* This file is te-ic960.h
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1994, 1995, 1997, 2000
-   Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* This file is te-ic960.h and is intended to define ic960 environment
-   specific differences.  */
-
-#define OBJ_COFF_OMIT_OPTIONAL_HEADER
-
-#ifndef BFD_ASSEMBLER
-#define LOCAL_LABEL(name) ((name[0] =='L') \
-			   || (name[0] =='.' \
-			       && (name[1]=='C' \
-				   || name[1]=='I' \
-				   || name[1]=='.')))
-#endif
-
-#include "obj-format.h"
-
-/* end of te-ic960.h */
diff --git a/gas/config/te-irix.h b/gas/config/te-irix.h
index 49fa26179aad..882f54b8d321 100644
--- a/gas/config/te-irix.h
+++ b/gas/config/te-irix.h
@@ -1,5 +1,5 @@
 /* IRIX targets
-   Copyright 2002 Free Software Foundation, Inc.
+   Copyright 2002, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This file is te-irix.h and is intended to provide support for
    IRIX targets.  Created by Alexandre Oliva <aoliva@redhat.com>.  */
diff --git a/gas/config/te-nbsd.h b/gas/config/te-nbsd.h
index cb8dc092eb5e..e428fab68fcd 100644
--- a/gas/config/te-nbsd.h
+++ b/gas/config/te-nbsd.h
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TE_NetBSD	1
 #define LOCAL_LABELS_FB 1
diff --git a/gas/config/te-netware.h b/gas/config/te-netware.h
new file mode 100644
index 000000000000..175675dfa110
--- /dev/null
+++ b/gas/config/te-netware.h
@@ -0,0 +1,28 @@
+/* te-netware.h -- NetWare target environment declarations.
+   Copyright 2004 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#define TE_NETWARE
+#define LOCAL_LABELS_FB 1
+
+#define LEX_AT  (LEX_NAME | LEX_BEGIN_NAME)  /* Can have @'s inside labels.  */
+#define LEX_PCT (LEX_NAME | LEX_BEGIN_NAME)  /* Can have %'s inside labels.  */
+#define LEX_QM  (LEX_NAME | LEX_BEGIN_NAME)  /* Can have ?'s inside labels.  */
+
+#include "obj-format.h"
diff --git a/gas/config/te-ppcnw.h b/gas/config/te-ppcnw.h
deleted file mode 100644
index 133759156ae8..000000000000
--- a/gas/config/te-ppcnw.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* te-ppcnw.h -- Power PC running Netware environment declarations.
-   Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
-
-   This file is part of GAS, the GNU Assembler.
-
-   GAS is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   GAS is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-/* Added these, because if we don't know what we're targeting we may
-   need an assembler version of libgcc, and that will use local
-   labels.  */
-#define LOCAL_LABELS_DOLLAR 1
-#define LOCAL_LABELS_FB 1
-
-/* these define interfaces */
-#include "obj-format.h"
-
-/* gcc uses escape sequences for ppc/netware.  */
-
-#undef NO_STRING_ESCAPES
diff --git a/gas/config/te-sparcaout.h b/gas/config/te-sparcaout.h
index edd376617261..791811610349 100644
--- a/gas/config/te-sparcaout.h
+++ b/gas/config/te-sparcaout.h
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #define TE_SPARCAOUT	1
 #include "obj-format.h"
diff --git a/gas/config/te-sun3.h b/gas/config/te-sun3.h
index 233201afa58f..184ba323e198 100644
--- a/gas/config/te-sun3.h
+++ b/gas/config/te-sun3.h
@@ -1,5 +1,6 @@
 /* te-sun3.h -- Sun-3 target environment declarations.
-   Copyright 1987, 1990, 1991, 1992, 2000 Free Software Foundation, Inc.
+   Copyright 1987, 1990, 1991, 1992, 2000, 2003
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This header file contains the #defines specific
    to SUN computer SUN 3 series computers.  (The only kind
diff --git a/gas/config/te-symbian.h b/gas/config/te-symbian.h
new file mode 100644
index 000000000000..e6090494aacc
--- /dev/null
+++ b/gas/config/te-symbian.h
@@ -0,0 +1,3 @@
+#define TE_SYMBIAN 1
+
+#include "te-armeabi.h"
diff --git a/gas/config/te-sysv32.h b/gas/config/te-sysv32.h
deleted file mode 100644
index c60728a975d6..000000000000
--- a/gas/config/te-sysv32.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Remove leading underscore from the gcc generated symbol names.  */
-#define STRIP_UNDERSCORE
-
-#include "obj-format.h"
-
-/* end of te-sysv32.h */
diff --git a/gas/config/te-tmips.h b/gas/config/te-tmips.h
index 2fc6fd91005a..87d432884f58 100644
--- a/gas/config/te-tmips.h
+++ b/gas/config/te-tmips.h
@@ -1,5 +1,5 @@
 /* Traditional MIPS targets
-   Copyright 2000 Free Software Foundation, Inc.
+   Copyright 2000, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This file is te-tmips.h and is intended to provide support for
    traditional mips targets like mips-dde-sysv4.2MP (Supermax ) ,
diff --git a/gas/config/te-vxworks.h b/gas/config/te-vxworks.h
new file mode 100644
index 000000000000..56492a90139f
--- /dev/null
+++ b/gas/config/te-vxworks.h
@@ -0,0 +1,31 @@
+/* te-vxworks.h -- VxWorks target environment declarations.
+   Copyright 2005
+   Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#define TE_VXWORKS	1
+#define LOCAL_LABELS_DOLLAR 1
+#define LOCAL_LABELS_FB 1
+
+/* these define interfaces */
+#ifdef OBJ_HEADER
+#include OBJ_HEADER
+#else
+#include "obj-format.h"
+#endif
diff --git a/gas/config/vax-inst.h b/gas/config/vax-inst.h
index 269752688d44..eca309121baa 100644
--- a/gas/config/vax-inst.h
+++ b/gas/config/vax-inst.h
@@ -1,5 +1,5 @@
 /* vax-inst.h - GNU - Part of vax.c
-   Copyright 1987, 1992, 1995, 2000 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1995, 2000, 2002 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,7 +15,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /*
  * This is part of vax-ins-parse.c & friends.
diff --git a/gas/config/vms-a-conf.h b/gas/config/vms-a-conf.h
deleted file mode 100644
index 688fc6890ca5..000000000000
--- a/gas/config/vms-a-conf.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* vms-alpha-conf.h.  Generated manually from conf.in,
-   and used by config-gas-alpha.com when constructing config.h.  */
-
-/* Define if using alloca.c.  */
-#ifdef __GNUC__
-#undef C_ALLOCA
-#else
-#define C_ALLOCA
-#endif
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#ifdef __GNUC__
-#undef inline
-#else
-#define inline
-#endif
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
-	STACK_DIRECTION > 0 => grows toward higher addresses
-	STACK_DIRECTION < 0 => grows toward lower addresses
-	STACK_DIRECTION = 0 => direction of growth unknown
- */
-#define STACK_DIRECTION (-1)
-
-/* Should gas use high-level BFD interfaces?  */
-#define BFD_ASSEMBLER
-
-/* Some assert/preprocessor combinations are incapable of handling
-   certain kinds of constructs in the argument of assert.  For example,
-   quoted strings (if requoting isn't done right) or newlines.  */
-#ifdef __GNUC__
-#undef BROKEN_ASSERT
-#else
-#define BROKEN_ASSERT
-#endif
-
-/* If we aren't doing cross-assembling, some operations can be optimized,
-   since byte orders and value sizes don't need to be adjusted.  */
-#undef CROSS_COMPILE
-
-/* Some gas code wants to know these parameters.  */
-#define TARGET_ALIAS	"alpha-vms"
-#define TARGET_CPU	"alpha"
-#define TARGET_CANONICAL	"alpha-dec-vms"
-#define TARGET_OS	"openVMS/Alpha"
-#define TARGET_VENDOR	"dec"
-
-/* Sometimes the system header files don't declare malloc and realloc.  */
-#undef NEED_DECLARATION_MALLOC
-
-/* Sometimes the system header files don't declare free.  */
-#undef NEED_DECLARATION_FREE
-
-/* Sometimes errno.h doesn't declare errno itself.  */
-#undef NEED_DECLARATION_ERRNO
-
-#undef MANY_SEGMENTS
-
-/* Needed only for sparc configuration */
-#undef sparcv9
-
-/* Define if you have the remove function.  */
-#define HAVE_REMOVE
-
-/* Define if you have the unlink function.  */
-#undef HAVE_UNLINK
-
-/* Define if you have the <errno.h> header file.  */
-#define HAVE_ERRNO_H
-
-/* Define if you have the <memory.h> header file.  */
-#undef HAVE_MEMORY_H
-
-/* Define if you have the <stdarg.h> header file.  */
-#define HAVE_STDARG_H
-
-/* Define if you have the <stdlib.h> header file.  */
-#define HAVE_STDLIB_H
-
-/* Define if you have the <string.h> header file.  */
-#define HAVE_STRING_H
-
-/* Define if you have the <strings.h> header file.  */
-#undef HAVE_STRINGS_H
-
-/* Define if you have the <sys/types.h> header file.  */
-#ifdef __GNUC__
-#define HAVE_SYS_TYPES_H
-#else
-#undef HAVE_SYS_TYPES_H
-#endif
-
-/* Define if you have the <unistd.h> header file.  */
-#define HAVE_UNISTD_H	/* config-gas.com will make one if necessary */
-
-/* Define if you have the <varargs.h> header file.  */
-#undef HAVE_VARARGS_H
-
-/* VMS-specific:  we need to set up EXIT_xxx here because the default
-   values in as.h are inappropriate for VMS, but we also want to prevent
-   as.h's inclusion of <stdlib.h> from triggering redefinition warnings.
-   <stdlib.h> guards itself against multiple inclusion, so including it
-   here turns as.h's later #include into a no-op.  (We can't simply use
-   #ifndef HAVE_STDLIB_H here, because the <stdlib.h> in several older
-   gcc-vms distributions neglects to define these two required macros.)  */
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#endif
-#if __DECC
-#undef EXIT_SUCCESS
-#undef EXIT_FAILURE
-#define EXIT_SUCCESS 1			/* SS$_NORMAL, STS$K_SUCCESS */
-#define EXIT_FAILURE 0x10000002		/* (STS$K_ERROR | STS$M_INHIB_MSG) */
-#endif
-
-#include <unixlib.h>
-#if __DECC
-extern int strcasecmp ();
-extern int strncasecmp ();
-#endif
diff --git a/gas/config/vms-conf.h b/gas/config/vms-conf.h
deleted file mode 100644
index 1c17074f57ac..000000000000
--- a/gas/config/vms-conf.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/* vms-conf.h.  Generated manually from conf.in,
-   and used by config-gas.com when constructing config.h.  */
-
-/* Define if using alloca.c.  */
-#ifdef __GNUC__
-#undef C_ALLOCA
-#else
-#define C_ALLOCA
-#endif
-
-/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
-   This function is required for alloca.c support on those systems.  */
-#undef CRAY_STACKSEG_END
-
-/* Define if you have alloca, as a function or macro.  */
-#undef HAVE_ALLOCA
-
-/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
-#undef HAVE_ALLOCA_H
-
-/* Define as __inline if that's what the C compiler calls it.  */
-#ifdef __GNUC__
-#undef inline
-#else
-#define inline
-#endif
-
-/* If using the C implementation of alloca, define if you know the
-   direction of stack growth for your system; otherwise it will be
-   automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown
- */
-#define STACK_DIRECTION (-1)
-
-/* Define if lex declares yytext as a char * by default, not a char[].  */
-#undef YYTEXT_POINTER
-
-/* Name of package.  */
-#undef PACKAGE
-
-/* Version of package.  */
-/* Define in by config-gas.com */
-/* #undef VERSION */
-
-/* Should gas use high-level BFD interfaces?  */
-#undef BFD_ASSEMBLER
-
-/* Some assert/preprocessor combinations are incapable of handling
-   certain kinds of constructs in the argument of assert.  For example,
-   quoted strings (if requoting isn't done right) or newlines.  */
-#ifdef __GNUC__
-#undef BROKEN_ASSERT
-#else
-#define BROKEN_ASSERT
-#endif
-
-/* If we aren't doing cross-assembling, some operations can be optimized,
-   since byte orders and value sizes don't need to be adjusted.  */
-#undef CROSS_COMPILE
-
-/* Some gas code wants to know these parameters.  */
-#define TARGET_ALIAS	"vms"
-#define TARGET_CPU	"vax"
-#define TARGET_CANONICAL	"vax-dec-vms"
-#define TARGET_OS	"vms"
-#define TARGET_VENDOR	"dec"
-
-/* Sometimes the system header files don't declare strstr.  */
-#undef NEED_DECLARATION_STRSTR
-
-/* Sometimes the system header files don't declare malloc and realloc.  */
-#undef NEED_DECLARATION_MALLOC
-
-/* Sometimes the system header files don't declare free.  */
-#undef NEED_DECLARATION_FREE
-
-/* Sometimes the system header files don't declare sbrk.  */
-#undef NEED_DECLARATION_SBRK
-
-/* Sometimes errno.h doesn't declare errno itself.  */
-#undef NEED_DECLARATION_ERRNO
-
-#undef MANY_SEGMENTS
-
-/* The configure script defines this for some targets based on the
-   target name used.  It is not always defined.  */
-#undef TARGET_BYTES_BIG_ENDIAN
-
-/* Needed only for some configurations that can produce multiple output
-   formats.  */
-#undef DEFAULT_EMULATION
-#undef EMULATIONS
-#undef USE_EMULATIONS
-#undef OBJ_MAYBE_AOUT
-#undef OBJ_MAYBE_BOUT
-#undef OBJ_MAYBE_COFF
-#undef OBJ_MAYBE_ECOFF
-#undef OBJ_MAYBE_ELF
-#undef OBJ_MAYBE_GENERIC
-#undef OBJ_MAYBE_HP300
-#undef OBJ_MAYBE_IEEE
-#undef OBJ_MAYBE_SOM
-#undef OBJ_MAYBE_VMS
-
-/* Used for some of the COFF configurations, when the COFF code needs
-   to select something based on the CPU type before it knows it...  */
-#undef I386COFF
-#undef M68KCOFF
-#undef M88KCOFF
-
-/* Using cgen code?  */
-#undef USING_CGEN
-
-/* Needed only for sparc configuration.  */
-#undef DEFAULT_ARCH
-
-/* Needed only for PowerPC Solaris.  */
-#undef TARGET_SOLARIS_COMMENT
-
-/* Needed only for SCO 5.  */
-#undef SCO_ELF
-
-/* Define if you have the remove function.  */
-#define HAVE_REMOVE
-
-/* Define if you have the sbrk function.  */
-/* sbrk() is available, but we don't want gas to use it.  */
-#undef HAVE_SBRK
-
-/* Define if you have the unlink function.  */
-#undef HAVE_UNLINK
-
-/* Define if you have the <errno.h> header file.  */
-#define HAVE_ERRNO_H
-
-/* Define if you have the <memory.h> header file.  */
-#undef HAVE_MEMORY_H
-
-/* Define if you have the <stdarg.h> header file.  */
-#define HAVE_STDARG_H
-
-/* Define if you have the <stdlib.h> header file.  */
-#define HAVE_STDLIB_H
-
-/* Define if you have the <string.h> header file.  */
-#define HAVE_STRING_H
-
-/* Define if you have the <strings.h> header file.  */
-#undef HAVE_STRINGS_H
-
-/* Define if you have the <sys/types.h> header file.  */
-#ifdef __GNUC__
-#define HAVE_SYS_TYPES_H
-#else
-#undef HAVE_SYS_TYPES_H
-#endif
-
-/* Define if you have the <unistd.h> header file.  */
-#define HAVE_UNISTD_H	/* config-gas.com will make one if necessary */
-
-/* Define if you have the <varargs.h> header file.  */
-#undef HAVE_VARARGS_H
-
-/* VMS-specific:  we need to set up EXIT_xxx here because the default
-   values in as.h are inappropriate for VMS, but we also want to prevent
-   as.h's inclusion of <stdlib.h> from triggering redefinition warnings.
-   <stdlib.h> guards itself against multiple inclusion, so including it
-   here turns as.h's later #include into a no-op.  (We can't simply use
-   #ifndef HAVE_STDLIB_H here, because the <stdlib.h> in several older
-   gcc-vms distributions neglects to define these two required macros.)  */
-#ifdef HAVE_STDLIB_H
-#include <stdlib.h>
-#undef EXIT_SUCCESS
-#undef EXIT_FAILURE
-#endif
-#define EXIT_SUCCESS 1			/* SS$_NORMAL, STS$K_SUCCESS */
-#define EXIT_FAILURE 0x10000002		/* (STS$K_ERROR | STS$M_INHIB_MSG) */
diff --git a/gas/config/xtensa-istack.h b/gas/config/xtensa-istack.h
index a1cca2ea702b..7d2471abd465 100644
--- a/gas/config/xtensa-istack.h
+++ b/gas/config/xtensa-istack.h
@@ -1,5 +1,5 @@
 /* Declarations for stacks of tokenized Xtensa instructions.
-   Copyright (C) 2003 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef XTENSA_ISTACK_H
 #define XTENSA_ISTACK_H
@@ -24,7 +24,7 @@
 #include "xtensa-isa.h"
 
 #define MAX_ISTACK 12
-#define MAX_INSN_ARGS 6
+#define MAX_INSN_ARGS 10
 
 enum itype_enum
 {
@@ -40,11 +40,23 @@ enum itype_enum
 typedef struct tinsn_struct
 {
   enum itype_enum insn_type;
-  
-  bfd_boolean is_specific_opcode; 
+
   xtensa_opcode opcode;	/* Literals have an invalid opcode.  */
+  bfd_boolean is_specific_opcode;
+  bfd_boolean keep_wide;
   int ntok;
   expressionS tok[MAX_INSN_ARGS];
+  unsigned linenum;
+
+  struct fixP *fixup;
+
+  /* Filled out by relaxation_requirements:  */
+  enum xtensa_relax_statesE subtype;
+  int literal_space;
+  /* Filled out by vinsn_to_insnbuf:  */
+  symbolS *symbol;
+  offsetT offset;
+  fragS *literal_frag;
 } TInsn;
 
 
@@ -57,17 +69,29 @@ typedef struct tinsn_stack
 } IStack;
 
 
-void         istack_init        PARAMS ((IStack *));
-bfd_boolean  istack_empty       PARAMS ((IStack *));
-bfd_boolean  istack_full        PARAMS ((IStack *));
-TInsn *      istack_top         PARAMS ((IStack *));
-void         istack_push        PARAMS ((IStack *, TInsn *));
-TInsn *      istack_push_space  PARAMS ((IStack *)); 
-void         istack_pop         PARAMS ((IStack *));
+void istack_init (IStack *);
+bfd_boolean istack_empty (IStack *);
+bfd_boolean istack_full (IStack *);
+TInsn *istack_top (IStack *);
+void istack_push (IStack *, TInsn *);
+TInsn *istack_push_space (IStack *);
+void istack_pop (IStack *);
 
 /* TInsn utilities.  */
-void         tinsn_init         PARAMS ((TInsn *));
-void         tinsn_copy         PARAMS ((TInsn *, const TInsn *));
-expressionS *tinsn_get_tok      PARAMS ((TInsn *, int));
+void tinsn_init (TInsn *);
+expressionS *tinsn_get_tok (TInsn *, int);
+
+
+/* vliw_insn: bundles of TInsns.  */
+
+typedef struct vliw_insn
+{
+  xtensa_format format;
+  int num_slots;
+  unsigned int inside_bundle;
+  TInsn slots[MAX_SLOTS];
+  xtensa_insnbuf insnbuf;
+  xtensa_insnbuf slotbuf[MAX_SLOTS];
+} vliw_insn;
 
 #endif /* !XTENSA_ISTACK_H */
diff --git a/gas/config/xtensa-relax.c b/gas/config/xtensa-relax.c
index 49a93b20e053..a0848820eb36 100644
--- a/gas/config/xtensa-relax.c
+++ b/gas/config/xtensa-relax.c
@@ -1,5 +1,5 @@
 /* Table of relaxations for Xtensa assembly.
-   Copyright 2003 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,38 +15,53 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 
-   MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 /* This file contains the code for generating runtime data structures
    for relaxation pattern matching from statically specified strings.
    Each action contains an instruction pattern to match and
    preconditions for the match as well as an expansion if the pattern
    matches.  The preconditions can specify that two operands are the
-   same or an operand is a specific constant.  The expansion uses the
-   bound variables from the pattern to specify that specific operands
-   from the pattern should be used in the result.  
+   same or an operand is a specific constant or register.  The expansion
+   uses the bound variables from the pattern to specify that specific
+   operands from the pattern should be used in the result.
+
+   The code determines whether the condition applies to a constant or
+   a register depending on the type of the operand.  You may get
+   unexpected results if you don't match the rule against the operand
+   type correctly.
 
    The patterns match a language like:
 
-   INSN_PATTERN ::= INSN_TEMPL ( '|' PRECOND )*
+   INSN_PATTERN ::= INSN_TEMPL ( '|' PRECOND )* ( '?' OPTIONPRED )*
    INSN_TEMPL   ::= OPCODE ' ' [ OPERAND (',' OPERAND)* ]
    OPCODE       ::=  id
    OPERAND      ::= CONSTANT | VARIABLE | SPECIALFN '(' VARIABLE ')'
    SPECIALFN    ::= 'HI24S' | 'F32MINUS' | 'LOW8'
+                    | 'HI16' | 'LOW16'
    VARIABLE     ::= '%' id
    PRECOND      ::= OPERAND CMPOP OPERAND
    CMPOP        ::= '==' | '!='
+   OPTIONPRED   ::= OPTIONNAME ('+' OPTIONNAME)
+   OPTIONNAME   ::= '"' id '"'
 
-   The replacement language 
+   The replacement language
    INSN_REPL      ::= INSN_LABEL_LIT ( ';' INSN_LABEL_LIT )*
-   INSN_LABEL_LIT ::= INSN_TEMPL 
-                      | 'LABEL' num 
+   INSN_LABEL_LIT ::= INSN_TEMPL
+                      | 'LABEL' num
                       | 'LITERAL' num ' ' VARIABLE
 
    The operands in a PRECOND must be constants or variables bound by
    the INSN_PATTERN.
 
+   The configuration options define a predicate on the availability of
+   options which must be TRUE for this rule to be valid.  Examples are
+   requiring "density" for replacements with density instructions,
+   requiring "const16" for replacements that require const16
+   instructions, etc.  The names are interpreted by the assembler to a
+   truth value for a particular frag.
+
    The operands in the INSN_REPL must be constants, variables bound in
    the associated INSN_PATTERN, special variables that are bound in
    the INSN_REPL by LABEL or LITERAL definitions, or special value
@@ -60,7 +75,7 @@
    {"beqz %as,%label", "bnez %as,%LABEL0;j %label;LABEL0"}
    would convert a branch to a negated branch to the following instruction
    with a jump to the original label.
-   
+
    An Xtensa-specific example that generates a literal:
    {"movi %at,%imm", "LITERAL0 %imm; l32r %at,%LITERAL0"}
    will convert a movi instruction to an l32r of a literal
@@ -84,11 +99,15 @@
 #include "xtensa-isa.h"
 #include "xtensa-relax.h"
 #include <stddef.h>
+#include "xtensa-config.h"
+
+#ifndef XCHAL_HAVE_WIDE_BRANCHES
+#define XCHAL_HAVE_WIDE_BRANCHES 0
+#endif
 
 /* Imported from bfd.  */
 extern xtensa_isa xtensa_default_isa;
 
-
 /* The opname_list is a small list of names that we use for opcode and
    operand variable names to simplify ownership of these commonly used
    strings.  Strings entered in the table can be compared by pointer
@@ -115,7 +134,7 @@ typedef struct opname_map_struct opname_map;
 struct opname_map_e_struct
 {
   const char *operand_name;	/* If null, then use constant_value.  */
-  size_t operand_num;
+  int operand_num;
   unsigned constant_value;
   opname_map_e *next;
 };
@@ -173,6 +192,7 @@ struct insn_pattern_struct
 {
   insn_templ t;
   precond_list preconds;
+  ReqOptionList *options;
 };
 
 
@@ -202,7 +222,7 @@ typedef struct split_rec_struct split_rec;
 struct split_rec_struct
 {
   char **vec;
-  size_t count;
+  int count;
 };
 
 /* The "string_pattern_pair" is a set of pairs containing instruction
@@ -231,94 +251,147 @@ struct string_pattern_pair_struct
 
 static string_pattern_pair widen_spec_list[] =
 {
-  {"add.n %ar,%as,%at", "add %ar,%as,%at"},
-  {"addi.n %ar,%as,%imm", "addi %ar,%as,%imm"},
-  {"beqz.n %as,%label", "beqz %as,%label"},
-  {"bnez.n %as,%label", "bnez %as,%label"},
-  {"l32i.n %at,%as,%imm", "l32i %at,%as,%imm"},
-  {"mov.n %at,%as", "or %at,%as,%as"},
-  {"movi.n %as,%imm", "movi %as,%imm"},
-  {"nop.n", "or 1,1,1"},
-  {"ret.n", "ret"},
-  {"retw.n", "retw"},
-  {"s32i.n %at,%as,%imm", "s32i %at,%as,%imm"},
+  {"add.n %ar,%as,%at ? IsaUseDensityInstruction", "add %ar,%as,%at"},
+  {"addi.n %ar,%as,%imm ? IsaUseDensityInstruction", "addi %ar,%as,%imm"},
+  {"beqz.n %as,%label ? IsaUseDensityInstruction", "beqz %as,%label"},
+  {"bnez.n %as,%label ? IsaUseDensityInstruction", "bnez %as,%label"},
+  {"l32i.n %at,%as,%imm ? IsaUseDensityInstruction", "l32i %at,%as,%imm"},
+  {"mov.n %at,%as ? IsaUseDensityInstruction", "or %at,%as,%as"},
+  {"movi.n %as,%imm ? IsaUseDensityInstruction", "movi %as,%imm"},
+  {"nop.n ? IsaUseDensityInstruction ? realnop", "nop"},
+  {"nop.n ? IsaUseDensityInstruction ? no-realnop", "or 1,1,1"},
+  {"ret.n %as ? IsaUseDensityInstruction", "ret %as"},
+  {"retw.n %as ? IsaUseDensityInstruction", "retw %as"},
+  {"s32i.n %at,%as,%imm ? IsaUseDensityInstruction", "s32i %at,%as,%imm"},
   {"srli %at,%as,%imm", "extui %at,%as,%imm,F32MINUS(%imm)"},
   {"slli %ar,%as,0", "or %ar,%as,%as"},
-  /* Widening with literals */
-  {"movi %at,%imm", "LITERAL0 %imm; l32r %at,%LITERAL0"},
+
+  /* Widening with literals or const16.  */
+  {"movi %at,%imm ? IsaUseL32R ",
+   "LITERAL0 %imm; l32r %at,%LITERAL0"},
+  {"movi %at,%imm ? IsaUseConst16",
+   "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm)"},
+
   {"addi %ar,%as,%imm", "addmi %ar,%as,%imm"},
   /* LOW8 is the low 8 bits of the Immed
      MID8S is the middle 8 bits of the Immed */
   {"addmi %ar,%as,%imm", "addmi %ar,%as,HI24S(%imm); addi %ar,%ar,LOW8(%imm)"},
-  {"addmi %ar,%as,%imm | %ar!=%as",
+
+  /* In the end convert to either an l32r or const16.  */
+  {"addmi %ar,%as,%imm | %ar!=%as ? IsaUseL32R",
    "LITERAL0 %imm; l32r %ar,%LITERAL0; add %ar,%as,%ar"},
+  {"addmi %ar,%as,%imm | %ar!=%as ? IsaUseConst16",
+   "const16 %ar,HI16U(%imm); const16 %ar,LOW16U(%imm); add %ar,%as,%ar"},
 
   /* Widening the load instructions with too-large immediates */
-  {"l8ui %at,%as,%imm | %at!=%as",
+  {"l8ui %at,%as,%imm | %at!=%as ? IsaUseL32R",
    "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l8ui %at,%at,0"},
-  {"l16si %at,%as,%imm | %at!=%as",
+  {"l16si %at,%as,%imm | %at!=%as ? IsaUseL32R",
    "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l16si %at,%at,0"},
-  {"l16ui %at,%as,%imm | %at!=%as",
+  {"l16ui %at,%as,%imm | %at!=%as ? IsaUseL32R",
    "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l16ui %at,%at,0"},
-#if 0 /* Xtensa Synchronization Option not yet available */
-  {"l32ai %at,%as,%imm",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32ai %at,%at,0"},
-#endif
-#if 0 /* Xtensa Speculation Option not yet available */
-  {"l32is %at,%as,%imm",
-   "LITERAL0 %imm; l32r %at,%LITERAL0; add.n %at,%at,%as; l32is %at,%at,0"},
-#endif
-  {"l32i %at,%as,%imm | %at!=%as",
+  {"l32i %at,%as,%imm | %at!=%as ? IsaUseL32R",
    "LITERAL0 %imm; l32r %at,%LITERAL0; add %at,%at,%as; l32i %at,%at,0"},
 
-  /* This is only PART of the loop instruction.  In addition, hard
-     coded into it's use is a modification of the final operand in the
-     instruction in bytes 9 and 12.  */
-  {"loop %as,%label",
+  /* Widening load instructions with const16s.  */
+  {"l8ui %at,%as,%imm | %at!=%as ? IsaUseConst16",
+   "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l8ui %at,%at,0"},
+  {"l16si %at,%as,%imm | %at!=%as ? IsaUseConst16",
+   "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l16si %at,%at,0"},
+  {"l16ui %at,%as,%imm | %at!=%as ? IsaUseConst16",
+   "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l16ui %at,%at,0"},
+  {"l32i %at,%as,%imm | %at!=%as ? IsaUseConst16",
+   "const16 %at,HI16U(%imm); const16 %at,LOW16U(%imm); add %at,%at,%as; l32i %at,%at,0"},
+
+  /* This is only PART of the loop instruction.  In addition,
+     hardcoded into its use is a modification of the final operand in
+     the instruction in bytes 9 and 12.  */
+  {"loop %as,%label | %as!=1 ? IsaUseLoops",
    "loop %as,%LABEL0;"
-   "rsr     %as, 1;"		/* LEND */
-   "wsr     %as, 0;"		/* LBEG */
+   "rsr.lend    %as;"		/* LEND */
+   "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
    "addmi   %as, %as, 0;"	/* mid8(%label-%LABEL1) */
-   "wsr     %as, 1;"
+   "wsr.lend    %as;"
    "isync;"
-   "rsr     %as, 2;"		/* LCOUNT */
+   "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
    "LABEL0"},
-  {"loopgtz %as,%label",
-   "beqz     %as,%label;"
-   "bltz     %as,%label;"
+  {"loopgtz %as,%label | %as!=1 ? IsaUseLoops",
+   "beqz    %as,%label;"
+   "bltz    %as,%label;"
    "loopgtz %as,%LABEL0;"
-   "rsr     %as, 1;"		/* LEND */
-   "wsr     %as, 0;"		/* LBEG */
+   "rsr.lend    %as;"		/* LEND */
+   "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
    "addmi   %as, %as, 0;"	/* mid8(%label-%LABEL1) */
-   "wsr     %as, 1;"
+   "wsr.lend    %as;"
    "isync;"
-   "rsr     %as, 2;"		/* LCOUNT */
+   "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
    "LABEL0"},
-  {"loopnez %as,%label",
+  {"loopnez %as,%label | %as!=1 ? IsaUseLoops",
    "beqz     %as,%label;"
    "loopnez %as,%LABEL0;"
-   "rsr     %as, 1;"		/* LEND */
-   "wsr     %as, 0;"		/* LBEG */
+   "rsr.lend    %as;"		/* LEND */
+   "wsr.lbeg    %as;"		/* LBEG */
    "addi    %as, %as, 0;"	/* lo8(%label-%LABEL1) */
    "addmi   %as, %as, 0;"	/* mid8(%label-%LABEL1) */
-   "wsr     %as, 1;"
+   "wsr.lend    %as;"
    "isync;"
-   "rsr     %as, 2;"		/* LCOUNT */
+   "rsr.lcount    %as;"		/* LCOUNT */
    "addi    %as, %as, 1;"	/* density -> addi.n %as, %as, 1 */
    "LABEL0"},
 
-#if 0 /* no mechanism here to determine if Density Option is available */
-  {"beqz %as,%label", "bnez.n %as,%LABEL0;j %label;LABEL0"},
-  {"bnez %as,%label", "beqz.n %as,%LABEL0;j %label;LABEL0"},
-#else
+  /* Relaxing to wide branches.  Order is important here.  With wide
+     branches, there is more than one correct relaxation for an
+     out-of-range branch.  Put the wide branch relaxations first in the
+     table since they are more efficient than the branch-around
+     relaxations.  */
+  
+  {"beqz %as,%label ? IsaUseWideBranches", "WIDE.beqz %as,%label"},
+  {"bnez %as,%label ? IsaUseWideBranches", "WIDE.bnez %as,%label"},
+  {"bgez %as,%label ? IsaUseWideBranches", "WIDE.bgez %as,%label"},
+  {"bltz %as,%label ? IsaUseWideBranches", "WIDE.bltz %as,%label"},
+  {"beqi %as,%imm,%label ? IsaUseWideBranches", "WIDE.beqi %as,%imm,%label"},
+  {"bnei %as,%imm,%label ? IsaUseWideBranches", "WIDE.bnei %as,%imm,%label"},
+  {"bgei %as,%imm,%label ? IsaUseWideBranches", "WIDE.bgei %as,%imm,%label"},
+  {"blti %as,%imm,%label ? IsaUseWideBranches", "WIDE.blti %as,%imm,%label"},
+  {"bgeui %as,%imm,%label ? IsaUseWideBranches", "WIDE.bgeui %as,%imm,%label"},
+  {"bltui %as,%imm,%label ? IsaUseWideBranches", "WIDE.bltui %as,%imm,%label"},
+  {"bbci %as,%imm,%label ? IsaUseWideBranches", "WIDE.bbci %as,%imm,%label"},
+  {"bbsi %as,%imm,%label ? IsaUseWideBranches", "WIDE.bbsi %as,%imm,%label"},
+  {"beq %as,%at,%label ? IsaUseWideBranches", "WIDE.beq %as,%at,%label"},
+  {"bne %as,%at,%label ? IsaUseWideBranches", "WIDE.bne %as,%at,%label"},
+  {"bge %as,%at,%label ? IsaUseWideBranches", "WIDE.bge %as,%at,%label"},
+  {"blt %as,%at,%label ? IsaUseWideBranches", "WIDE.blt %as,%at,%label"},
+  {"bgeu %as,%at,%label ? IsaUseWideBranches", "WIDE.bgeu %as,%at,%label"},
+  {"bltu %as,%at,%label ? IsaUseWideBranches", "WIDE.bltu %as,%at,%label"},
+  {"bany %as,%at,%label ? IsaUseWideBranches", "WIDE.bany %as,%at,%label"},
+  {"bnone %as,%at,%label ? IsaUseWideBranches", "WIDE.bnone %as,%at,%label"},
+  {"ball %as,%at,%label ? IsaUseWideBranches", "WIDE.ball %as,%at,%label"},
+  {"bnall %as,%at,%label ? IsaUseWideBranches", "WIDE.bnall %as,%at,%label"},
+  {"bbc %as,%at,%label ? IsaUseWideBranches", "WIDE.bbc %as,%at,%label"},
+  {"bbs %as,%at,%label ? IsaUseWideBranches", "WIDE.bbs %as,%at,%label"},
+  
+  /* Widening branch comparisons eq/ne to zero.  Prefer relaxing to narrow
+     branches if the density option is available.  */
+  {"beqz %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%LABEL0;j %label;LABEL0"},
+  {"bnez %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%LABEL0;j %label;LABEL0"},
   {"beqz %as,%label", "bnez %as,%LABEL0;j %label;LABEL0"},
   {"bnez %as,%label", "beqz %as,%LABEL0;j %label;LABEL0"},
-#endif
 
+  /* Widening expect-taken branches.  */
+  {"beqzt %as,%label ? IsaUsePredictedBranches", "bnez %as,%LABEL0;j %label;LABEL0"},
+  {"bnezt %as,%label ? IsaUsePredictedBranches", "beqz %as,%LABEL0;j %label;LABEL0"},
+  {"beqt %as,%at,%label ? IsaUsePredictedBranches", "bne %as,%at,%LABEL0;j %label;LABEL0"},
+  {"bnet %as,%at,%label ? IsaUsePredictedBranches", "beq %as,%at,%LABEL0;j %label;LABEL0"},
+
+  /* Widening branches from the Xtensa boolean option.  */
+  {"bt %bs,%label ? IsaUseBooleans", "bf %bs,%LABEL0;j %label;LABEL0"},
+  {"bf %bs,%label ? IsaUseBooleans", "bt %bs,%LABEL0;j %label;LABEL0"},
+
+  /* Other branch-around-jump widenings.  */
   {"bgez %as,%label", "bltz %as,%LABEL0;j %label;LABEL0"},
   {"bltz %as,%label", "bgez %as,%LABEL0;j %label;LABEL0"},
   {"beqi %as,%imm,%label", "bnei %as,%imm,%LABEL0;j %label;LABEL0"},
@@ -336,19 +409,31 @@ static string_pattern_pair widen_spec_list[] =
   {"bgeu %as,%at,%label", "bltu %as,%at,%LABEL0;j %label;LABEL0"},
   {"bltu %as,%at,%label", "bgeu %as,%at,%LABEL0;j %label;LABEL0"},
   {"bany %as,%at,%label", "bnone %as,%at,%LABEL0;j %label;LABEL0"},
-#if 1 /* provide relaxations for Boolean Option */
-  {"bt %bs,%label", "bf %bs,%LABEL0;j %label;LABEL0"},
-  {"bf %bs,%label", "bt %bs,%LABEL0;j %label;LABEL0"},
-#endif
   {"bnone %as,%at,%label", "bany %as,%at,%LABEL0;j %label;LABEL0"},
   {"ball %as,%at,%label", "bnall %as,%at,%LABEL0;j %label;LABEL0"},
   {"bnall %as,%at,%label", "ball %as,%at,%LABEL0;j %label;LABEL0"},
   {"bbc %as,%at,%label", "bbs %as,%at,%LABEL0;j %label;LABEL0"},
   {"bbs %as,%at,%label", "bbc %as,%at,%LABEL0;j %label;LABEL0"},
-  {"call0 %label", "LITERAL0 %label; l32r a0,%LITERAL0; callx0 a0"},
-  {"call4 %label", "LITERAL0 %label; l32r a4,%LITERAL0; callx4 a4"},
-  {"call8 %label", "LITERAL0 %label; l32r a8,%LITERAL0; callx8 a8"},
-  {"call12 %label", "LITERAL0 %label; l32r a12,%LITERAL0; callx12 a12"}
+
+  /* Expanding calls with literals.  */
+  {"call0 %label,%ar0 ? IsaUseL32R",
+   "LITERAL0 %label; l32r a0,%LITERAL0; callx0 a0,%ar0"},
+  {"call4 %label,%ar4 ? IsaUseL32R",
+   "LITERAL0 %label; l32r a4,%LITERAL0; callx4 a4,%ar4"},
+  {"call8 %label,%ar8 ? IsaUseL32R",
+   "LITERAL0 %label; l32r a8,%LITERAL0; callx8 a8,%ar8"},
+  {"call12 %label,%ar12 ? IsaUseL32R",
+   "LITERAL0 %label; l32r a12,%LITERAL0; callx12 a12,%ar12"},
+
+  /* Expanding calls with const16.  */
+  {"call0 %label,%ar0 ? IsaUseConst16",
+   "const16 a0,HI16U(%label); const16 a0,LOW16U(%label); callx0 a0,%ar0"},
+  {"call4 %label,%ar4 ? IsaUseConst16",
+   "const16 a4,HI16U(%label); const16 a4,LOW16U(%label); callx4 a4,%ar4"},
+  {"call8 %label,%ar8 ? IsaUseConst16",
+   "const16 a8,HI16U(%label); const16 a8,LOW16U(%label); callx8 a8,%ar8"},
+  {"call12 %label,%ar12 ? IsaUseConst16",
+   "const16 a12,HI16U(%label); const16 a12,LOW16U(%label); callx12 a12,%ar12"}
 };
 
 #define WIDEN_COUNT (sizeof (widen_spec_list) / sizeof (string_pattern_pair))
@@ -366,154 +451,43 @@ static string_pattern_pair widen_spec_list[] =
 
 string_pattern_pair simplify_spec_list[] =
 {
-  {"add %ar,%as,%at", "add.n %ar,%as,%at"},
-  {"addi.n %ar,%as,0", "mov.n %ar,%as"},
-  {"addi %ar,%as,0", "mov.n %ar,%as"},
-  {"addi %ar,%as,%imm", "addi.n %ar,%as,%imm"},
-  {"addmi %ar,%as,%imm", "addi.n %ar,%as,%imm"},
-  {"beqz %as,%label", "beqz.n %as,%label"},
-  {"bnez %as,%label", "bnez.n %as,%label"},
-  {"l32i %at,%as,%imm", "l32i.n %at,%as,%imm"},
-  {"movi %as,%imm", "movi.n %as,%imm"},
-  {"or %ar,%as,%at | %as==%at", "mov.n %ar,%as"},
-  {"ret", "ret.n"},
-  {"retw", "retw.n"},
-  {"s32i %at,%as,%imm", "s32i.n %at,%as,%imm"},
-  {"slli %ar,%as,0", "mov.n %ar,%as"}
+  {"add %ar,%as,%at ? IsaUseDensityInstruction", "add.n %ar,%as,%at"},
+  {"addi.n %ar,%as,0 ? IsaUseDensityInstruction", "mov.n %ar,%as"},
+  {"addi %ar,%as,0 ? IsaUseDensityInstruction", "mov.n %ar,%as"},
+  {"addi %ar,%as,%imm ? IsaUseDensityInstruction", "addi.n %ar,%as,%imm"},
+  {"addmi %ar,%as,%imm ? IsaUseDensityInstruction", "addi.n %ar,%as,%imm"},
+  {"beqz %as,%label ? IsaUseDensityInstruction", "beqz.n %as,%label"},
+  {"bnez %as,%label ? IsaUseDensityInstruction", "bnez.n %as,%label"},
+  {"l32i %at,%as,%imm ? IsaUseDensityInstruction", "l32i.n %at,%as,%imm"},
+  {"movi %as,%imm ? IsaUseDensityInstruction", "movi.n %as,%imm"},
+  {"nop ? realnop ? IsaUseDensityInstruction", "nop.n"},
+  {"or %ar,%as,%at | %ar==%as | %as==%at ? IsaUseDensityInstruction", "nop.n"},
+  {"or %ar,%as,%at | %ar!=%as | %as==%at ? IsaUseDensityInstruction", "mov.n %ar,%as"},
+  {"ret %as ? IsaUseDensityInstruction", "ret.n %as"},
+  {"retw %as ? IsaUseDensityInstruction", "retw.n %as"},
+  {"s32i %at,%as,%imm ? IsaUseDensityInstruction", "s32i.n %at,%as,%imm"},
+  {"slli %ar,%as,0 ? IsaUseDensityInstruction", "mov.n %ar,%as"}
 };
 
 #define SIMPLIFY_COUNT \
   (sizeof (simplify_spec_list) / sizeof (string_pattern_pair))
 
 
-/* Transition generation helpers.  */
-
-static void append_transition 
-  PARAMS ((TransitionTable *, xtensa_opcode, TransitionRule *));
-static void append_condition 
-  PARAMS ((TransitionRule *, Precondition *));
-static void append_value_condition 
-  PARAMS ((TransitionRule *, CmpOp, unsigned, unsigned));
-static void append_constant_value_condition 
-  PARAMS ((TransitionRule *, CmpOp, unsigned, unsigned));
-static void append_build_insn
-  PARAMS ((TransitionRule *, BuildInstr *));
-static void append_op
-  PARAMS ((BuildInstr *, BuildOp *));
-static void append_literal_op 
-  PARAMS ((BuildInstr *, unsigned, unsigned));
-static void append_label_op 
-  PARAMS ((BuildInstr *, unsigned, unsigned));
-static void append_constant_op 
-  PARAMS ((BuildInstr *, unsigned, unsigned));
-static void append_field_op 
-  PARAMS ((BuildInstr *, unsigned, unsigned));
-static void append_user_fn_field_op 
-  PARAMS ((BuildInstr *, unsigned, OpType, unsigned));
-static long operand_function_HI24S
-  PARAMS ((long));
-static long operand_function_F32MINUS
-  PARAMS ((long));
-static long operand_function_LOW8
-  PARAMS ((long));
-
 /* Externally visible functions.  */
 
-extern bfd_boolean xg_has_userdef_op_fn
-  PARAMS ((OpType));
-extern long xg_apply_userdef_op_fn
-  PARAMS ((OpType, long));
-
-/* Parsing helpers.  */
-
-static const char *enter_opname_n
-  PARAMS ((const char *, size_t));
-static const char *enter_opname
-  PARAMS ((const char *));
-
-/* Construction and destruction.  */
-
-static void init_opname_map
-  PARAMS ((opname_map *));
-static void clear_opname_map
-  PARAMS ((opname_map *));
-static void init_precond_list
-  PARAMS ((precond_list *));
-static void clear_precond_list
-  PARAMS ((precond_list *));
-static void init_insn_templ
-  PARAMS ((insn_templ *));
-static void clear_insn_templ
-  PARAMS ((insn_templ *));
-static void init_insn_pattern
-  PARAMS ((insn_pattern *));
-static void clear_insn_pattern
-  PARAMS ((insn_pattern *));
-static void init_insn_repl
-  PARAMS ((insn_repl *));
-static void clear_insn_repl
-  PARAMS ((insn_repl *));
-static void init_split_rec
-  PARAMS ((split_rec *));
-static void clear_split_rec
-  PARAMS ((split_rec *));
-
-/* Operand and insn_templ helpers.  */
-
-static bfd_boolean same_operand_name
-  PARAMS ((const opname_map_e *, const opname_map_e *));
-static opname_map_e *get_opmatch
-  PARAMS ((opname_map *, const char *));
-static bfd_boolean op_is_constant
-  PARAMS ((const opname_map_e *));
-static unsigned op_get_constant
-  PARAMS ((const opname_map_e *));
-static size_t insn_templ_operand_count
-  PARAMS ((const insn_templ *));
-
-/* parsing helpers.  */
-
-static const char *skip_white
-  PARAMS ((const char *));
-static void trim_whitespace
-  PARAMS ((char *));
-static void split_string 
-  PARAMS ((split_rec *, const char *, char,  bfd_boolean));
-
-/* Language parsing.  */
-
-static bfd_boolean parse_insn_pattern 
-  PARAMS ((const char *, insn_pattern *));
-static bfd_boolean parse_insn_repl 
-  PARAMS ((const char *, insn_repl *));
-static bfd_boolean parse_insn_templ 
-  PARAMS ((const char *, insn_templ *));
-static bfd_boolean parse_special_fn 
-  PARAMS ((const char *, const char **, const char **));
-static bfd_boolean parse_precond
-  PARAMS ((const char *, precond_e *));
-static bfd_boolean parse_constant
-  PARAMS ((const char *, unsigned *));
-static bfd_boolean parse_id_constant 
-  PARAMS ((const char *, const char *, unsigned *));
-
-/* Transition table building code.  */
-
-static TransitionRule *build_transition 
-  PARAMS ((insn_pattern *, insn_repl *, const char *, const char *));
-static TransitionTable *build_transition_table 
-  PARAMS ((const string_pattern_pair *, size_t));
+extern bfd_boolean xg_has_userdef_op_fn (OpType);
+extern long xg_apply_userdef_op_fn (OpType, long);
 
-
-void
-append_transition (tt, opcode, t)
-     TransitionTable *tt;
-     xtensa_opcode opcode;
-     TransitionRule *t;
+
+static void
+append_transition (TransitionTable *tt,
+		   xtensa_opcode opcode,
+		   TransitionRule *t,
+		   transition_cmp_fn cmp)
 {
   TransitionList *tl = (TransitionList *) xmalloc (sizeof (TransitionList));
   TransitionList *prev;
-  TransitionList *nxt;
+  TransitionList **t_p;
   assert (tt != NULL);
   assert (opcode < tt->num_opcodes);
 
@@ -525,20 +499,23 @@ append_transition (tt, opcode, t)
       tt->table[opcode] = tl;
       return;
     }
-  nxt = prev->next;
-  while (nxt != NULL)
+
+  for (t_p = &tt->table[opcode]; (*t_p) != NULL; t_p = &(*t_p)->next)
     {
-      prev = nxt;
-      nxt = nxt->next;
+      if (cmp && cmp (t, (*t_p)->rule) < 0)
+	{
+	  /* Insert it here.  */
+	  tl->next = *t_p;
+	  *t_p = tl;
+	  return;
+	}
     }
-  prev->next = tl;
+  (*t_p) = tl;
 }
 
 
-void
-append_condition (tr, cond)
-     TransitionRule *tr;
-     Precondition *cond;
+static void
+append_condition (TransitionRule *tr, Precondition *cond)
 {
   PreconditionList *pl =
     (PreconditionList *) xmalloc (sizeof (PreconditionList));
@@ -562,12 +539,11 @@ append_condition (tr, cond)
 }
 
 
-void
-append_value_condition (tr, cmp, op1, op2)
-     TransitionRule *tr;
-     CmpOp cmp;
-     unsigned op1;
-     unsigned op2;
+static void
+append_value_condition (TransitionRule *tr,
+			CmpOp cmp,
+			unsigned op1,
+			unsigned op2)
 {
   Precondition *cond = (Precondition *) xmalloc (sizeof (Precondition));
 
@@ -579,12 +555,11 @@ append_value_condition (tr, cmp, op1, op2)
 }
 
 
-void
-append_constant_value_condition (tr, cmp, op1, cnst)
-     TransitionRule *tr;
-     CmpOp cmp;
-     unsigned op1;
-     unsigned cnst;
+static void
+append_constant_value_condition (TransitionRule *tr,
+				 CmpOp cmp,
+				 unsigned op1,
+				 unsigned cnst)
 {
   Precondition *cond = (Precondition *) xmalloc (sizeof (Precondition));
 
@@ -596,10 +571,8 @@ append_constant_value_condition (tr, cmp, op1, cnst)
 }
 
 
-void
-append_build_insn (tr, bi)
-     TransitionRule *tr;
-     BuildInstr *bi;
+static void
+append_build_insn (TransitionRule *tr, BuildInstr *bi)
 {
   BuildInstr *prev = tr->to_instr;
   BuildInstr *nxt;
@@ -620,10 +593,8 @@ append_build_insn (tr, bi)
 }
 
 
-void
-append_op (bi, b_op)
-     BuildInstr *bi;
-     BuildOp *b_op;
+static void
+append_op (BuildInstr *bi, BuildOp *b_op)
 {
   BuildOp *prev = bi->ops;
   BuildOp *nxt;
@@ -643,11 +614,8 @@ append_op (bi, b_op)
 }
 
 
-void
-append_literal_op (bi, op1, litnum)
-     BuildInstr *bi;
-     unsigned op1;
-     unsigned litnum;
+static void
+append_literal_op (BuildInstr *bi, unsigned op1, unsigned litnum)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
@@ -659,11 +627,8 @@ append_literal_op (bi, op1, litnum)
 }
 
 
-void
-append_label_op (bi, op1, labnum)
-     BuildInstr *bi;
-     unsigned op1;
-     unsigned labnum;
+static void
+append_label_op (BuildInstr *bi, unsigned op1, unsigned labnum)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
@@ -675,11 +640,8 @@ append_label_op (bi, op1, labnum)
 }
 
 
-void
-append_constant_op (bi, op1, cnst)
-     BuildInstr *bi;
-     unsigned op1;
-     unsigned cnst;
+static void
+append_constant_op (BuildInstr *bi, unsigned op1, unsigned cnst)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
@@ -691,11 +653,8 @@ append_constant_op (bi, op1, cnst)
 }
 
 
-void
-append_field_op (bi, op1, src_op)
-     BuildInstr *bi;
-     unsigned op1;
-     unsigned src_op;
+static void
+append_field_op (BuildInstr *bi, unsigned op1, unsigned src_op)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
@@ -709,12 +668,11 @@ append_field_op (bi, op1, src_op)
 
 /* These could be generated but are not currently.  */
 
-void
-append_user_fn_field_op (bi, op1, typ, src_op)
-     BuildInstr *bi;
-     unsigned op1;
-     OpType typ;
-     unsigned src_op;
+static void
+append_user_fn_field_op (BuildInstr *bi,
+			 unsigned op1,
+			 OpType typ,
+			 unsigned src_op)
 {
   BuildOp *b_op = (BuildOp *) xmalloc (sizeof (BuildOp));
 
@@ -729,9 +687,8 @@ append_user_fn_field_op (bi, op1, typ, src_op)
 /* These operand functions are the semantics of user-defined
    operand functions.  */
 
-long
-operand_function_HI24S (a)
-     long a;
+static long
+operand_function_HI24S (long a)
 {
   if (a & 0x80)
     return (a & (~0xff)) + 0x100;
@@ -740,17 +697,15 @@ operand_function_HI24S (a)
 }
 
 
-long
-operand_function_F32MINUS (a)
-     long a;
+static long
+operand_function_F32MINUS (long a)
 {
   return (32 - a);
 }
 
 
-long
-operand_function_LOW8 (a)
-     long a;
+static long
+operand_function_LOW8 (long a)
 {
   if (a & 0x80)
     return (a & 0xff) | ~0xff;
@@ -759,15 +714,31 @@ operand_function_LOW8 (a)
 }
 
 
+static long
+operand_function_LOW16U (long a)
+{
+  return (a & 0xffff);
+}
+
+
+static long
+operand_function_HI16U (long a)
+{
+  unsigned long b = a & 0xffff0000;
+  return (long) (b >> 16);
+}
+
+
 bfd_boolean
-xg_has_userdef_op_fn (op)
-     OpType op;
+xg_has_userdef_op_fn (OpType op)
 {
   switch (op)
     {
     case OP_OPERAND_F32MINUS:
     case OP_OPERAND_LOW8:
     case OP_OPERAND_HI24S:
+    case OP_OPERAND_LOW16U:
+    case OP_OPERAND_HI16U:
       return TRUE;
     default:
       break;
@@ -777,9 +748,7 @@ xg_has_userdef_op_fn (op)
 
 
 long
-xg_apply_userdef_op_fn (op, a)
-     OpType op;
-     long a;
+xg_apply_userdef_op_fn (OpType op, long a)
 {
   switch (op)
     {
@@ -789,6 +758,10 @@ xg_apply_userdef_op_fn (op, a)
       return operand_function_LOW8 (a);
     case OP_OPERAND_HI24S:
       return operand_function_HI24S (a);
+    case OP_OPERAND_LOW16U:
+      return operand_function_LOW16U (a);
+    case OP_OPERAND_HI16U:
+      return operand_function_HI16U (a);
     default:
       break;
     }
@@ -798,16 +771,15 @@ xg_apply_userdef_op_fn (op, a)
 
 /* Generate a transition table.  */
 
-const char *
-enter_opname_n (name, len)
-     const char *name;
-     size_t len;
+static const char *
+enter_opname_n (const char *name, int len)
 {
   opname_e *op;
 
   for (op = local_opnames; op != NULL; op = op->next)
     {
-      if (strlen (op->opname) == len && strncmp (op->opname, name, len) == 0)
+      if (strlen (op->opname) == (unsigned) len
+	  && strncmp (op->opname, name, len) == 0)
 	return op->opname;
     }
   op = (opname_e *) xmalloc (sizeof (opname_e));
@@ -819,8 +791,7 @@ enter_opname_n (name, len)
 
 
 static const char *
-enter_opname (name)
-     const char *name;
+enter_opname (const char *name)
 {
   opname_e *op;
 
@@ -830,23 +801,21 @@ enter_opname (name)
 	return op->opname;
     }
   op = (opname_e *) xmalloc (sizeof (opname_e));
-  op->opname = strdup (name);
+  op->opname = xstrdup (name);
   return op->opname;
 }
 
 
-void
-init_opname_map (m)
-     opname_map *m;
+static void
+init_opname_map (opname_map *m)
 {
   m->head = NULL;
   m->tail = &m->head;
 }
 
 
-void
-clear_opname_map (m)
-     opname_map *m;
+static void
+clear_opname_map (opname_map *m)
 {
   opname_map_e *e;
 
@@ -861,9 +830,7 @@ clear_opname_map (m)
 
 
 static bfd_boolean
-same_operand_name (m1, m2)
-     const opname_map_e *m1;
-     const opname_map_e *m2;
+same_operand_name (const opname_map_e *m1, const opname_map_e *m2)
 {
   if (m1->operand_name == NULL || m1->operand_name == NULL)
     return FALSE;
@@ -871,10 +838,8 @@ same_operand_name (m1, m2)
 }
 
 
-opname_map_e *
-get_opmatch (map, operand_name)
-     opname_map *map;
-     const char *operand_name;
+static opname_map_e *
+get_opmatch (opname_map *map, const char *operand_name)
 {
   opname_map_e *m;
 
@@ -887,35 +852,31 @@ get_opmatch (map, operand_name)
 }
 
 
-bfd_boolean
-op_is_constant (m1)
-     const opname_map_e *m1;
+static bfd_boolean
+op_is_constant (const opname_map_e *m1)
 {
   return (m1->operand_name == NULL);
 }
 
 
 static unsigned
-op_get_constant (m1)
-     const opname_map_e *m1;
+op_get_constant (const opname_map_e *m1)
 {
   assert (m1->operand_name == NULL);
   return m1->constant_value;
 }
 
 
-void
-init_precond_list (l)
-     precond_list *l;
+static void
+init_precond_list (precond_list *l)
 {
   l->head = NULL;
   l->tail = &l->head;
 }
 
 
-void
-clear_precond_list (l)
-     precond_list *l;
+static void
+clear_precond_list (precond_list *l)
 {
   precond_e *e;
 
@@ -929,53 +890,48 @@ clear_precond_list (l)
 }
 
 
-void
-init_insn_templ (t)
-     insn_templ *t;
+static void
+init_insn_templ (insn_templ *t)
 {
   t->opcode_name = NULL;
   init_opname_map (&t->operand_map);
 }
 
 
-void
-clear_insn_templ (t)
-     insn_templ *t;
+static void
+clear_insn_templ (insn_templ *t)
 {
   clear_opname_map (&t->operand_map);
 }
 
 
-void
-init_insn_pattern (p)
-     insn_pattern *p;
+static void
+init_insn_pattern (insn_pattern *p)
 {
   init_insn_templ (&p->t);
   init_precond_list (&p->preconds);
+  p->options = NULL;
 }
 
 
-void
-clear_insn_pattern (p)
-     insn_pattern *p;
+static void
+clear_insn_pattern (insn_pattern *p)
 {
   clear_insn_templ (&p->t);
   clear_precond_list (&p->preconds);
 }
 
 
-void
-init_insn_repl (r)
-     insn_repl *r;
+static void
+init_insn_repl (insn_repl *r)
 {
   r->head = NULL;
   r->tail = &r->head;
 }
 
 
-void
-clear_insn_repl (r)
-     insn_repl *r;
+static void
+clear_insn_repl (insn_repl *r)
 {
   insn_repl_e *e;
 
@@ -989,14 +945,13 @@ clear_insn_repl (r)
 }
 
 
-static size_t
-insn_templ_operand_count (t)
-     const insn_templ *t;
+static int
+insn_templ_operand_count (const insn_templ *t)
 {
-  size_t i = 0;
+  int i = 0;
   const opname_map_e *op;
 
-  for (op = t->operand_map.head; op != NULL; op = op->next, ++i)
+  for (op = t->operand_map.head; op != NULL; op = op->next, i++)
     ;
   return i;
 }
@@ -1004,10 +959,8 @@ insn_templ_operand_count (t)
 
 /* Convert a string to a number.  E.G.: parse_constant("10", &num) */
 
-bfd_boolean
-parse_constant (in, val_p)
-     const char *in;
-     unsigned *val_p;
+static bfd_boolean
+parse_constant (const char *in, unsigned *val_p)
 {
   unsigned val = 0;
   const char *p;
@@ -1033,11 +986,8 @@ parse_constant (in, val_p)
    parse_id_constant("foo1", "foo", &num).
    This may also be used to just match a number.  */
 
-bfd_boolean
-parse_id_constant (in, name, val_p)
-     const char *in;
-     const char *name;
-     unsigned *val_p;
+static bfd_boolean
+parse_id_constant (const char *in, const char *name, unsigned *val_p)
 {
   unsigned namelen = 0;
   const char *p;
@@ -1057,10 +1007,9 @@ parse_id_constant (in, name, val_p)
 
 
 static bfd_boolean
-parse_special_fn (name, fn_name_p, arg_name_p)
-     const char *name;
-     const char **fn_name_p;
-     const char **arg_name_p;
+parse_special_fn (const char *name,
+		  const char **fn_name_p,
+		  const char **arg_name_p)
 {
   char *p_start;
   const char *p_end;
@@ -1083,9 +1032,8 @@ parse_special_fn (name, fn_name_p, arg_name_p)
 }
 
 
-const char *
-skip_white (p)
-     const char *p;
+static const char *
+skip_white (const char *p)
 {
   if (p == NULL)
     return p;
@@ -1095,9 +1043,8 @@ skip_white (p)
 }
 
 
-void
-trim_whitespace (in)
-     char *in;
+static void
+trim_whitespace (char *in)
 {
   char *last_white = NULL;
   char *p = in;
@@ -1124,15 +1071,14 @@ trim_whitespace (in)
 /* Split a string into component strings where "c" is the
    delimiter.  Place the result in the split_rec.  */
 
-void
-split_string (rec, in, c, elide_whitespace)
-     split_rec *rec;
-     const char *in;
-     char c;
-     bfd_boolean elide_whitespace;
+static void
+split_string (split_rec *rec,
+	      const char *in,
+	      char c,
+	      bfd_boolean elide_whitespace)
 {
-  size_t cnt = 0;
-  size_t i;
+  int cnt = 0;
+  int i;
   const char *p = in;
 
   while (p != NULL && *p != '\0')
@@ -1156,7 +1102,7 @@ split_string (rec, in, c, elide_whitespace)
   for (i = 0; i < cnt; i++)
     {
       const char *q;
-      size_t len;
+      int len;
 
       q = p;
       if (elide_whitespace)
@@ -1164,7 +1110,7 @@ split_string (rec, in, c, elide_whitespace)
 
       p = strchr (q, c);
       if (p == NULL)
-	rec->vec[i] = strdup (q);
+	rec->vec[i] = xstrdup (q);
       else
 	{
 	  len = p - q;
@@ -1180,13 +1126,12 @@ split_string (rec, in, c, elide_whitespace)
 }
 
 
-void
-clear_split_rec (rec)
-     split_rec *rec;
+static void
+clear_split_rec (split_rec *rec)
 {
-  size_t i;
+  int i;
 
-  for (i = 0; i < rec->count; ++i)
+  for (i = 0; i < rec->count; i++)
     free (rec->vec[i]);
 
   if (rec->count > 0)
@@ -1194,9 +1139,11 @@ clear_split_rec (rec)
 }
 
 
-void
-init_split_rec (rec)
-     split_rec *rec;
+/* Initialize a split record.  The split record must be initialized
+   before split_string is called.  */
+
+static void
+init_split_rec (split_rec *rec)
 {
   rec->vec = NULL;
   rec->count = 0;
@@ -1205,16 +1152,15 @@ init_split_rec (rec)
 
 /* Parse an instruction template like "insn op1, op2, op3".  */
 
-bfd_boolean
-parse_insn_templ (s, t)
-     const char *s;
-     insn_templ *t;
+static bfd_boolean
+parse_insn_templ (const char *s, insn_templ *t)
 {
   const char *p = s;
-  /* First find the first whitespace.  */
-  size_t insn_name_len;
+  int insn_name_len;
   split_rec oprec;
-  size_t i;
+  int i;
+
+  /* First find the first whitespace.  */
 
   init_split_rec (&oprec);
 
@@ -1266,10 +1212,8 @@ parse_insn_templ (s, t)
 }
 
 
-bfd_boolean
-parse_precond (s, precond)
-     const char *s;
-     precond_e *precond;
+static bfd_boolean
+parse_precond (const char *s, precond_e *precond)
 {
   /* All preconditions are currently of the form:
      a == b or a != b or a == k (where k is a constant).
@@ -1277,7 +1221,7 @@ parse_precond (s, precond)
      to identify when density is available.  */
 
   const char *p = s;
-  size_t len;
+  int len;
   precond->opname1 = NULL;
   precond->opval1 = 0;
   precond->cmpop = OP_EQUAL;
@@ -1322,34 +1266,162 @@ parse_precond (s, precond)
 }
 
 
+static void
+clear_req_or_option_list (ReqOrOption **r_p)
+{
+  if (*r_p == NULL)
+    return;
+
+  free ((*r_p)->option_name);
+  clear_req_or_option_list (&(*r_p)->next);
+  *r_p = NULL;
+}
+
+
+static void
+clear_req_option_list (ReqOption **r_p)
+{
+  if (*r_p == NULL)
+    return;
+
+  clear_req_or_option_list (&(*r_p)->or_option_terms);
+  clear_req_option_list (&(*r_p)->next);
+  *r_p = NULL;
+}
+
+
+static ReqOrOption *
+clone_req_or_option_list (ReqOrOption *req_or_option)
+{
+  ReqOrOption *new_req_or_option;
+
+  if (req_or_option == NULL)
+    return NULL;
+
+  new_req_or_option = (ReqOrOption *) xmalloc (sizeof (ReqOrOption));
+  new_req_or_option->option_name = xstrdup (req_or_option->option_name);
+  new_req_or_option->is_true = req_or_option->is_true;
+  new_req_or_option->next = NULL;
+  new_req_or_option->next = clone_req_or_option_list (req_or_option->next);
+  return new_req_or_option;
+}
+
+
+static ReqOption *
+clone_req_option_list (ReqOption *req_option)
+{
+  ReqOption *new_req_option;
+
+  if (req_option == NULL)
+    return NULL;
+
+  new_req_option = (ReqOption *) xmalloc (sizeof (ReqOption));
+  new_req_option->or_option_terms = NULL;
+  new_req_option->next = NULL;
+  new_req_option->or_option_terms =
+    clone_req_or_option_list (req_option->or_option_terms);
+  new_req_option->next = clone_req_option_list (req_option->next);
+  return new_req_option;
+}
+
+
+static bfd_boolean
+parse_option_cond (const char *s, ReqOption *option)
+{
+  int i;
+  split_rec option_term_rec;
+
+  /* All option or conditions are of the form:
+     optionA + no-optionB + ...
+     "Ands" are divided by "?".  */
+
+  init_split_rec (&option_term_rec);
+  split_string (&option_term_rec, s, '+', TRUE);
+
+  if (option_term_rec.count == 0)
+    {
+      clear_split_rec (&option_term_rec);
+      return FALSE;
+    }
+
+  for (i = 0; i < option_term_rec.count; i++)
+    {
+      char *option_name = option_term_rec.vec[i];
+      bfd_boolean is_true = TRUE;
+      ReqOrOption *req;
+      ReqOrOption **r_p;
+
+      if (strncmp (option_name, "no-", 3) == 0)
+	{
+	  option_name = xstrdup (&option_name[3]);
+	  is_true = FALSE;
+	}
+      else
+	option_name = xstrdup (option_name);
+
+      req = (ReqOrOption *) xmalloc (sizeof (ReqOrOption));
+      req->option_name = option_name;
+      req->is_true = is_true;
+      req->next = NULL;
+
+      /* Append to list.  */
+      for (r_p = &option->or_option_terms; (*r_p) != NULL;
+	   r_p = &(*r_p)->next)
+	;
+      (*r_p) = req;
+    }
+  return TRUE;
+}
+
+
 /* Parse a string like:
    "insn op1, op2, op3, op4 | op1 != op2 | op2 == op3 | op4 == 1".
    I.E., instruction "insn" with 4 operands where operand 1 and 2 are not
-   the same and operand 2 and 3 are the same and operand 4 is 1.  */
+   the same and operand 2 and 3 are the same and operand 4 is 1.
 
-bfd_boolean
-parse_insn_pattern (in, insn)
-     const char *in;
-     insn_pattern *insn;
-{
+   or:
+
+   "insn op1 | op1 == 1 / density + boolean / no-useroption".
+   i.e. instruction "insn" with 1 operands where operand 1 is 1
+   when "density" or "boolean" options are available and
+   "useroption" is not available.
 
+   Because the current implementation of this parsing scheme uses
+   split_string, it requires that '|' and '?' are only used as
+   delimiters for predicates and required options.  */
+
+static bfd_boolean
+parse_insn_pattern (const char *in, insn_pattern *insn)
+{
   split_rec rec;
-  size_t i;
+  split_rec optionrec;
+  int i;
 
-  init_split_rec (&rec);
   init_insn_pattern (insn);
 
-  split_string (&rec, in, '|', TRUE);
+  init_split_rec (&optionrec);
+  split_string (&optionrec, in, '?', TRUE);
+  if (optionrec.count == 0)
+    {
+      clear_split_rec (&optionrec);
+      return FALSE;
+    }
+
+  init_split_rec (&rec);
+
+  split_string (&rec, optionrec.vec[0], '|', TRUE);
 
   if (rec.count == 0)
     {
       clear_split_rec (&rec);
+      clear_split_rec (&optionrec);
       return FALSE;
     }
 
   if (!parse_insn_templ (rec.vec[0], &insn->t))
     {
       clear_split_rec (&rec);
+      clear_split_rec (&optionrec);
       return FALSE;
     }
 
@@ -1360,6 +1432,7 @@ parse_insn_pattern (in, insn)
       if (!parse_precond (rec.vec[i], cond))
 	{
 	  clear_split_rec (&rec);
+	  clear_split_rec (&optionrec);
 	  clear_insn_pattern (insn);
 	  return FALSE;
 	}
@@ -1369,19 +1442,42 @@ parse_insn_pattern (in, insn)
       insn->preconds.tail = &cond->next;
     }
 
+  for (i = 1; i < optionrec.count; i++)
+    {
+      /* Handle the option conditions.  */
+      ReqOption **r_p;
+      ReqOption *req_option = (ReqOption *) xmalloc (sizeof (ReqOption));
+      req_option->or_option_terms = NULL;
+      req_option->next = NULL;
+
+      if (!parse_option_cond (optionrec.vec[i], req_option))
+	{
+	  clear_split_rec (&rec);
+	  clear_split_rec (&optionrec);
+	  clear_insn_pattern (insn);
+	  clear_req_option_list (&req_option);
+	  return FALSE;
+	}
+
+      /* Append the condition.  */
+      for (r_p = &insn->options; (*r_p) != NULL; r_p = &(*r_p)->next)
+	;
+
+      (*r_p) = req_option;
+    }
+
   clear_split_rec (&rec);
+  clear_split_rec (&optionrec);
   return TRUE;
 }
 
 
-bfd_boolean
-parse_insn_repl (in, r_p)
-     const char *in;
-     insn_repl *r_p;
+static bfd_boolean
+parse_insn_repl (const char *in, insn_repl *r_p)
 {
   /* This is a list of instruction templates separated by ';'.  */
   split_rec rec;
-  size_t i;
+  int i;
 
   split_string (&rec, in, ';', TRUE);
 
@@ -1404,12 +1500,90 @@ parse_insn_repl (in, r_p)
 }
 
 
-TransitionRule *
-build_transition (initial_insn, replace_insns, from_string, to_string)
-     insn_pattern *initial_insn;
-     insn_repl *replace_insns;
-     const char *from_string;
-     const char *to_string;
+static bfd_boolean
+transition_applies (insn_pattern *initial_insn,
+		    const char *from_string ATTRIBUTE_UNUSED,
+		    const char *to_string ATTRIBUTE_UNUSED)
+{
+  ReqOption *req_option;
+
+  for (req_option = initial_insn->options;
+       req_option != NULL;
+       req_option = req_option->next)
+    {
+      ReqOrOption *req_or_option = req_option->or_option_terms;
+
+      if (req_or_option == NULL
+	  || req_or_option->next != NULL)
+	continue;
+
+      if (strncmp (req_or_option->option_name, "IsaUse", 6) == 0)
+	{
+	  bfd_boolean option_available = FALSE;
+	  char *option_name = req_or_option->option_name + 6;
+	  if (!strcmp (option_name, "DensityInstruction"))
+	    option_available = (XCHAL_HAVE_DENSITY == 1);
+	  else if (!strcmp (option_name, "L32R"))
+	    option_available = (XCHAL_HAVE_L32R == 1);
+	  else if (!strcmp (option_name, "Const16"))
+	    option_available = (XCHAL_HAVE_CONST16 == 1);
+	  else if (!strcmp (option_name, "Loops"))
+	    option_available = (XCHAL_HAVE_LOOPS == 1);
+	  else if (!strcmp (option_name, "WideBranches"))
+	    option_available = (XCHAL_HAVE_WIDE_BRANCHES == 1);
+	  else if (!strcmp (option_name, "PredictedBranches"))
+	    option_available = (XCHAL_HAVE_PREDICTED_BRANCHES == 1);
+	  else if (!strcmp (option_name, "Booleans"))
+	    option_available = (XCHAL_HAVE_BOOLEANS == 1);
+	  else
+	    as_warn (_("invalid configuration option '%s' in transition rule '%s'"),
+		     req_or_option->option_name, from_string);
+	  if ((option_available ^ req_or_option->is_true) != 0)
+	    return FALSE;
+	}
+      else if (strcmp (req_or_option->option_name, "realnop") == 0)
+	{
+	  bfd_boolean nop_available =
+	    (xtensa_opcode_lookup (xtensa_default_isa, "nop")
+	     != XTENSA_UNDEFINED);
+	  if ((nop_available ^ req_or_option->is_true) != 0)
+	    return FALSE;
+	}
+    }
+  return TRUE;
+}
+
+
+static bfd_boolean
+wide_branch_opcode (const char *opcode_name,
+		    char *suffix,
+		    xtensa_opcode *popcode)
+{
+  xtensa_isa isa = xtensa_default_isa;
+  xtensa_opcode opcode;
+  static char wbr_name_buf[20];
+
+  if (strncmp (opcode_name, "WIDE.", 5) != 0)
+    return FALSE;
+
+  strcpy (wbr_name_buf, opcode_name + 5);
+  strcat (wbr_name_buf, suffix);
+  opcode = xtensa_opcode_lookup (isa, wbr_name_buf);
+  if (opcode != XTENSA_UNDEFINED)
+    {
+      *popcode = opcode;
+      return TRUE;
+    }
+
+  return FALSE;
+}
+
+
+static TransitionRule *
+build_transition (insn_pattern *initial_insn,
+		  insn_repl *replace_insns,
+		  const char *from_string,
+		  const char *to_string)
 {
   TransitionRule *tr = NULL;
   xtensa_opcode opcode;
@@ -1429,26 +1603,16 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
   if (opcode == XTENSA_UNDEFINED)
     {
       /* It is OK to not be able to translate some of these opcodes.  */
-#if 0
-      as_warn (_("Invalid opcode '%s' in transition rule '%s'\n"),
-	       initial_insn->t.opcode_name, to_string);
-#endif
       return NULL;
     }
 
 
-  if (xtensa_num_operands (isa, opcode)
-      != (int) insn_templ_operand_count (&initial_insn->t))
+  if (xtensa_opcode_num_operands (isa, opcode)
+      != insn_templ_operand_count (&initial_insn->t))
     {
       /* This is also OK because there are opcodes that
 	 have different numbers of operands on different
 	 architecture variations.  */
-#if 0
-      as_fatal (_("opcode %s mismatched operand count %d != expected %d"),
-		xtensa_opcode_name (isa, opcode),
-		xtensa_num_operands (isa, opcode),
-		insn_templ_operand_count (&initial_insn->t));
-#endif
       return NULL;
     }
 
@@ -1531,12 +1695,14 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
 				op1->operand_num, op2->operand_num);
       else if (op2 == NULL)
 	append_constant_value_condition (tr, precond->cmpop,
-					 op1->operand_num, precond->opval1);
+					 op1->operand_num, precond->opval2);
       else
 	append_constant_value_condition (tr, precond->cmpop,
-					 op2->operand_num, precond->opval2);
+					 op2->operand_num, precond->opval1);
     }
 
+  tr->options = clone_req_option_list (initial_insn->options);
+
   /* Generate the replacement instructions.  Some of these
      "instructions" are actually labels and literals.  The literals
      must be defined in order 0..n and a literal must be defined
@@ -1549,7 +1715,7 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
     {
       BuildInstr *bi;
       const char *opcode_name;
-      size_t operand_count;
+      int operand_count;
       opname_map_e *op;
       unsigned idnum = 0;
       const char *fn_name;
@@ -1590,14 +1756,25 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
       else
 	{
 	  bi->typ = INSTR_INSTR;
-	  bi->opcode = xtensa_opcode_lookup (isa, r->t.opcode_name);
+	  if (wide_branch_opcode (opcode_name, ".w18", &bi->opcode)
+	      || wide_branch_opcode (opcode_name, ".w15", &bi->opcode))
+	    opcode_name = xtensa_opcode_name (isa, bi->opcode);
+	  else
+	    bi->opcode = xtensa_opcode_lookup (isa, opcode_name);
+
 	  if (bi->opcode == XTENSA_UNDEFINED)
-	    return NULL;
+	    {
+	      as_warn (_("invalid opcode '%s' in transition rule '%s'"),
+		       opcode_name, to_string);
+	      return NULL;
+	    }
+
 	  /* Check for the right number of ops.  */
-	  if (xtensa_num_operands (isa, bi->opcode) 
+	  if (xtensa_opcode_num_operands (isa, bi->opcode)
 	      != (int) operand_count)
 	    as_fatal (_("opcode '%s': replacement does not have %d ops"),
-		      opcode_name, xtensa_num_operands (isa, bi->opcode));
+		      opcode_name,
+		      xtensa_opcode_num_operands (isa, bi->opcode));
 	}
 
       for (op = r->t.operand_map.head; op != NULL; op = op->next)
@@ -1650,8 +1827,12 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
 		typ = OP_OPERAND_HI24S;
 	      else if (strcmp (fn_name, "F32MINUS") == 0)
 		typ = OP_OPERAND_F32MINUS;
+	      else if (strcmp (fn_name, "LOW16U") == 0)
+		typ = OP_OPERAND_LOW16U;
+	      else if (strcmp (fn_name, "HI16U") == 0)
+		typ = OP_OPERAND_HI16U;
 	      else
-		as_fatal (_("unknown user defined function %s"), fn_name);
+		as_fatal (_("unknown user-defined function %s"), fn_name);
 
 	      orig_op = get_opmatch (&initial_insn->t.operand_map,
 				     operand_arg_name);
@@ -1685,15 +1866,14 @@ build_transition (initial_insn, replace_insns, from_string, to_string)
 }
 
 
-TransitionTable *
-build_transition_table (transitions, transition_count)
-     const string_pattern_pair *transitions;
-     size_t transition_count;
+static TransitionTable *
+build_transition_table (const string_pattern_pair *transitions,
+			int transition_count,
+			transition_cmp_fn cmp)
 {
   TransitionTable *table = NULL;
-  int num_opcodes = xtensa_num_opcodes (xtensa_default_isa);
-  int i;
-  size_t tnum;
+  int num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa);
+  int i, tnum;
 
   if (table != NULL)
     return table;
@@ -1733,10 +1913,20 @@ build_transition_table (transitions, transition_count)
 	  continue;
 	}
 
-      tr = build_transition (&initial_insn, &replace_insns,
-			     from_string, to_string);
-      if (tr)
-	append_transition (table, tr->opcode, tr);
+      if (transition_applies (&initial_insn, from_string, to_string))
+	{
+	  tr = build_transition (&initial_insn, &replace_insns,
+				 from_string, to_string);
+	  if (tr)
+	    append_transition (table, tr->opcode, tr, cmp);
+	  else
+	    {
+#if TENSILICA_DEBUG
+	      as_warn (_("could not build transition for %s => %s"),
+		       from_string, to_string);
+#endif
+	    }
+	}
 
       clear_insn_repl (&replace_insns);
       clear_insn_pattern (&initial_insn);
@@ -1746,20 +1936,20 @@ build_transition_table (transitions, transition_count)
 
 
 extern TransitionTable *
-xg_build_widen_table ()
+xg_build_widen_table (transition_cmp_fn cmp)
 {
   static TransitionTable *table = NULL;
   if (table == NULL)
-    table = build_transition_table (widen_spec_list, WIDEN_COUNT);
+    table = build_transition_table (widen_spec_list, WIDEN_COUNT, cmp);
   return table;
 }
 
 
 extern TransitionTable *
-xg_build_simplify_table ()
+xg_build_simplify_table (transition_cmp_fn cmp)
 {
   static TransitionTable *table = NULL;
   if (table == NULL)
-    table = build_transition_table (simplify_spec_list, SIMPLIFY_COUNT);
+    table = build_transition_table (simplify_spec_list, SIMPLIFY_COUNT, cmp);
   return table;
 }
diff --git a/gas/config/xtensa-relax.h b/gas/config/xtensa-relax.h
index 99bf77bfd8e9..6ae11e379cef 100644
--- a/gas/config/xtensa-relax.h
+++ b/gas/config/xtensa-relax.h
@@ -1,5 +1,5 @@
 /* Table of relaxations for Xtensa assembly.
-   Copyright 2003 Free Software Foundation, Inc.
+   Copyright 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 
-   MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+   MA 02110-1301, USA.  */
 
 #ifndef XTENSA_RELAX_H
 #define XTENSA_RELAX_H
@@ -33,6 +33,11 @@ typedef struct transition_rule TransitionRule;
 typedef struct precondition_list PreconditionList;
 typedef struct precondition Precondition;
 
+typedef struct req_or_option_list ReqOrOptionList;
+typedef struct req_or_option_list ReqOrOption;
+typedef struct req_option_list ReqOptionList;
+typedef struct req_option_list ReqOption;
+
 struct transition_table
 {
   int num_opcodes;
@@ -52,6 +57,38 @@ struct precondition_list
 };
 
 
+/* The required options for a rule are represented with a two-level
+   structure, with leaf expressions combined by logical ORs at the
+   lower level, and the results then combined by logical ANDs at the
+   top level.  The AND terms are linked in a list, and each one can
+   contain a reference to a list of OR terms.  The leaf expressions,
+   i.e., the OR options, can be negated by setting the is_true field
+   to FALSE.  There are two classes of leaf expressions: (1) those
+   that are properties of the Xtensa configuration and can be
+   evaluated once when building the tables, and (2) those that depend
+   of the state of directives or other settings that may vary during
+   the assembly.  The following expressions may be used in group (1):
+
+   IsaUse*:	Xtensa configuration settings.
+   realnop:	TRUE if the instruction set includes a NOP instruction.
+
+   There are currently no expressions in group (2), but they are still
+   supported since there is a good chance they'll be needed again for
+   something.  */
+
+struct req_option_list
+{
+  ReqOrOptionList *or_option_terms;
+  ReqOptionList *next;
+};
+
+struct req_or_option_list
+{
+  char *option_name;
+  bfd_boolean is_true;
+  ReqOrOptionList *next;
+};
+
 /* Operand types and constraints on operands:  */
 
 typedef enum op_type OpType;
@@ -62,9 +99,11 @@ enum op_type
   OP_CONSTANT,
   OP_OPERAND,
   OP_OPERAND_LOW8,		/* Sign-extended low 8 bits of immed.  */
-  OP_OPERAND_HI24S,		/* high 24 bits of immed,
+  OP_OPERAND_HI24S,		/* High 24 bits of immed,
 				   plus 0x100 if low 8 bits are signed.  */
   OP_OPERAND_F32MINUS,		/* 32 - immed.  */
+  OP_OPERAND_LOW16U,		/* Low 16 bits of immed.  */
+  OP_OPERAND_HI16U,		/* High 16 bits of immed.  */
   OP_LITERAL,
   OP_LABEL
 };
@@ -85,6 +124,7 @@ struct precondition
   int op_data;
 };
 
+
 typedef struct build_op BuildOp;
 
 struct build_op
@@ -117,7 +157,7 @@ struct build_instr
   InstrType typ;
   unsigned id;			/* LITERAL_DEF or LABEL_DEF: an ordinal to
 				   identify which one.  */
-  xtensa_opcode opcode;		/* unused for LITERAL_DEF or LABEL_DEF.  */
+  xtensa_opcode opcode;		/* Unused for LITERAL_DEF or LABEL_DEF.  */
   BuildOp *ops;
   BuildInstr *next;
 };
@@ -126,17 +166,17 @@ struct transition_rule
 {
   xtensa_opcode opcode;
   PreconditionList *conditions;
+  ReqOptionList *options;
   BuildInstr *to_instr;
 };
 
-extern TransitionTable *xg_build_simplify_table
-  PARAMS ((void));
-extern TransitionTable *xg_build_widen_table
-  PARAMS ((void));
+typedef int (*transition_cmp_fn) (const TransitionRule *,
+				  const TransitionRule *);
+
+extern TransitionTable *xg_build_simplify_table (transition_cmp_fn);
+extern TransitionTable *xg_build_widen_table (transition_cmp_fn);
 
-extern bfd_boolean xg_has_userdef_op_fn
-  PARAMS ((OpType));
-extern long xg_apply_userdef_op_fn
-  PARAMS ((OpType, long));
+extern bfd_boolean xg_has_userdef_op_fn (OpType);
+extern long xg_apply_userdef_op_fn (OpType, long);
 
 #endif /* !XTENSA_RELAX_H */
diff --git a/gas/configure b/gas/configure
index e66abca67bc9..dca6497031ce 100755
--- a/gas/configure
+++ b/gas/configure
@@ -309,7 +309,7 @@ ac_includes_default="\
 # include <unistd.h>
 #endif"
 
-ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO AMTAR install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LN_S RANLIB ac_ct_RANLIB LIBTOOL WARN_CFLAGS GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof BFDLIB OPCODES_LIB BFDVER_H ALL_OBJ_DEPS YACC LEX LEXLIB LEX_OUTPUT_ROOT CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBM LIBOBJS LTLIBOBJS'
+ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE LN_S RANLIB ac_ct_RANLIB LIBTOOL WARN_CFLAGS NO_WERROR GDBINIT cgen_cpu_prefix extra_objects target_cpu_type obj_format te_file install_tooldir atof BFDLIB OPCODES_LIB BFDVER_H ALL_OBJ_DEPS YACC LEX LEXLIB LEX_OUTPUT_ROOT CPP EGREP ALLOCA USE_NLS MSGFMT GMSGFMT XGETTEXT USE_INCLUDED_LIBINTL CATALOGS CATOBJEXT DATADIRNAME GMOFILES INSTOBJEXT INTLDEPS INTLLIBS INTLOBJS POFILES POSUB INCLUDE_LOCALE_H GT_NO GT_YES MKINSTALLDIRS l MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBM datarootdir docdir htmldir LIBOBJS LTLIBOBJS'
 ac_subst_files=''
 
 # Initialize some variables set by options.
@@ -856,10 +856,10 @@ Optional Features:
   --enable-static=PKGS  build static libraries default=yes
   --enable-fast-install=PKGS  optimize for fast installation default=yes
   --disable-libtool-lock  avoid locking (might break parallel builds)
-  --enable-bfd-assembler  use BFD back end for writing object files
-    targets            alternative target configurations besides the primary
+   --enable-targets       alternative target configurations besides the primary
   --enable-commonbfdlib   build shared BFD/opcodes/libiberty library
-  --enable-build-warnings Enable build-time compiler warnings if gcc is used
+  --enable-werror    treat compile warnings as errors
+  --enable-build-warnings Enable build-time compiler warnings
   --disable-nls           do not use Native Language Support
   --enable-maintainer-mode  enable make rules and dependencies not useful
 			  (and sometimes confusing) to the casual installer
@@ -971,7 +971,7 @@ esac
     else
       echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
     fi
-    cd "$ac_popdir"
+    cd $ac_popdir
   done
 fi
 
@@ -1994,7 +1994,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2052,7 +2053,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2168,7 +2170,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2222,7 +2225,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2267,7 +2271,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2311,7 +2316,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2389,7 +2395,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2443,7 +2450,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2477,7 +2485,7 @@ fi
 
 
 BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ 	]*\([^ 	]*\)[ 	]*).*/\1/p' < ${srcdir}/../bfd/configure.in`
-am__api_version="1.8"
+am__api_version="1.9"
 # Find a good install program.  We prefer a C program (faster),
 # so one script is as good as another.  But avoid the broken or
 # incompatible versions:
@@ -2629,13 +2637,21 @@ echo "$as_me: WARNING: \`missing' script is too old or missing" >&2;}
 fi
 
 if mkdir -p --version . >/dev/null 2>&1 && test ! -d ./--version; then
-  # Keeping the `.' argument allows $(mkdir_p) to be used without
-  # argument.  Indeed, we sometimes output rules like
+  # We used to keeping the `.' as first argument, in order to
+  # allow $(mkdir_p) to be used without argument.  As in
   #   $(mkdir_p) $(somedir)
-  # where $(somedir) is conditionally defined.
-  # (`test -n '$(somedir)' && $(mkdir_p) $(somedir)' is a more
-  # expensive solution, as it forces Make to start a sub-shell.)
-  mkdir_p='mkdir -p -- .'
+  # where $(somedir) is conditionally defined.  However this is wrong
+  # for two reasons:
+  #  1. if the package is installed by a user who cannot write `.'
+  #     make install will fail,
+  #  2. the above comment should most certainly read
+  #     $(mkdir_p) $(DESTDIR)$(somedir)
+  #     so it does not work when $(somedir) is undefined and
+  #     $(DESTDIR) is not.
+  #  To support the latter case, we have to write
+  #     test -z "$(somedir)" || $(mkdir_p) $(DESTDIR)$(somedir),
+  #  so the `.' trick is pointless.
+  mkdir_p='mkdir -p --'
 else
   # On NextStep and OpenStep, the `mkdir' command does not
   # recognize any option.  It will interpret all options as
@@ -2844,9 +2860,6 @@ AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"}
 
 MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"}
 
-
-AMTAR=${AMTAR-"${am_missing_run}tar"}
-
 install_sh=${install_sh-"$am_aux_dir/install-sh"}
 
 # Installed binaries are usually stripped using `strip' when the user
@@ -2939,6 +2952,13 @@ INSTALL_STRIP_PROGRAM="\${SHELL} \$(install_sh) -c -s"
 
 # We need awk for the "check" target.  The system "awk" is bad on
 # some platforms.
+# Always define AMTAR for backward compatibility.
+
+AMTAR=${AMTAR-"${am_missing_run}tar"}
+
+am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'
+
+
 
 
 depcc="$CC"   am_compiler_list=
@@ -3320,6 +3340,7 @@ cygwin* | mingw* |pw32*)
   ;;
 
 darwin* | rhapsody*)
+  # this will be overwritten by pass_all, but leave it in just in case
   lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library'
   lt_cv_file_magic_cmd='/usr/bin/file -L'
   case "$host_os" in
@@ -3330,9 +3351,10 @@ darwin* | rhapsody*)
     lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib'
     ;;
   esac
+  lt_cv_deplibs_check_method=pass_all
   ;;
 
-freebsd* )
+freebsd* | kfreebsd*-gnu)
   if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
     case $host_cpu in
     i*86 )
@@ -3390,17 +3412,10 @@ irix5* | irix6*)
 
 # This must be Linux ELF.
 linux-gnu*)
-  case $host_cpu in
-  alpha* | mips* | hppa* | i*86 | powerpc* | sparc* | ia64* )
-    lt_cv_deplibs_check_method=pass_all ;;
-  *)
-    # glibc up to 2.1.1 does not perform some relocations on ARM
-    lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;;
-  esac
-  lt_cv_file_magic_test_file=`echo /lib/libc.so* /lib/libc-*.so`
+  lt_cv_deplibs_check_method=pass_all
   ;;
 
-netbsd*)
+netbsd* | knetbsd*-gnu)
   if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then
     lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$'
   else
@@ -3458,6 +3473,67 @@ deplibs_check_method=$lt_cv_deplibs_check_method
 
 # Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers!
 
+# find the maximum length of command line arguments
+echo "$as_me:$LINENO: checking the maximum length of command line arguments" >&5
+echo $ECHO_N "checking the maximum length of command line arguments... $ECHO_C" >&6
+if test "${lt_cv_sys_max_cmd_len+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+    i=0
+  teststring="ABCD"
+
+  case $build_os in
+  msdosdjgpp*)
+    # On DJGPP, this test can blow up pretty badly due to problems in libc
+    # (any single argument exceeding 2000 bytes causes a buffer overrun
+    # during glob expansion).  Even if it were fixed, the result of this
+    # check would be larger than it should be.
+    lt_cv_sys_max_cmd_len=12288;    # 12K is about right
+    ;;
+
+  cygwin* | mingw*)
+    # On Win9x/ME, this test blows up -- it succeeds, but takes
+    # about 5 minutes as the teststring grows exponentially.
+    # Worse, since 9x/ME are not pre-emptively multitasking,
+    # you end up with a "frozen" computer, even though with patience
+    # the test eventually succeeds (with a max line length of 256k).
+    # Instead, let's just punt: use the minimum linelength reported by
+    # all of the supported platforms: 8192 (on NT/2K/XP).
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  amigaos*)
+    # On AmigaOS with pdksh, this test takes hours, literally.
+    # So we just punt and use a minimum line length of 8192.
+    lt_cv_sys_max_cmd_len=8192;
+    ;;
+
+  netbsd* | freebsd* | openbsd* | darwin* | dragonfly*)
+    # This has been around since 386BSD, at least.  Likely further.
+    if test -x /sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax`
+    elif test -x /usr/sbin/sysctl; then
+      lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax`
+    else
+      lt_cv_sys_max_cmd_len=65536 # usable default for *BSD
+    fi
+    # And add a safety zone
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4`
+    lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3`
+    ;;
+  esac
+
+fi
+
+if test -n "$lt_cv_sys_max_cmd_len" ; then
+  echo "$as_me:$LINENO: result: $lt_cv_sys_max_cmd_len" >&5
+echo "${ECHO_T}$lt_cv_sys_max_cmd_len" >&6
+else
+  echo "$as_me:$LINENO: result: none" >&5
+echo "${ECHO_T}none" >&6
+fi
+
+
 # Only perform the check for file, if the check method requires it
 case $deplibs_check_method in
 file_magic*)
@@ -3791,7 +3867,7 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
 case $host in
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 3794 "configure"' > conftest.$ac_ext
+  echo '#line 3870 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
@@ -3846,6 +3922,52 @@ ia64-*-hpux*)
   rm -rf conftest*
   ;;
 
+x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*|s390*-*linux*|sparc*-*linux*)
+  # Find out which ABI we are using.
+  echo 'int i;' > conftest.$ac_ext
+  if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; then
+    case "`/usr/bin/file conftest.o`" in
+    *32-bit*)
+      case $host in
+        x86_64-*linux*)
+          LD="${LD-ld} -m elf_i386"
+          ;;
+        ppc64-*linux*|powerpc64-*linux*)
+          LD="${LD-ld} -m elf32ppclinux"
+          ;;
+        s390x-*linux*)
+          LD="${LD-ld} -m elf_s390"
+          ;;
+        sparc64-*linux*)
+          LD="${LD-ld} -m elf32_sparc"
+          ;;
+      esac
+      ;;
+    *64-bit*)
+      case $host in
+        x86_64-*linux*)
+          LD="${LD-ld} -m elf_x86_64"
+          ;;
+        ppc*-*linux*|powerpc*-*linux*)
+          LD="${LD-ld} -m elf64ppc"
+          ;;
+        s390*-*linux*)
+          LD="${LD-ld} -m elf64_s390"
+          ;;
+        sparc*-*linux*)
+          LD="${LD-ld} -m elf64_sparc"
+          ;;
+      esac
+      ;;
+    esac
+  fi
+  rm -rf conftest*
+  ;;
+
 *-*-sco3.2v5*)
   # On SCO OpenServer 5, we need -belf to get full-featured binaries.
   SAVE_CFLAGS="$CFLAGS"
@@ -3887,7 +4009,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4031,18 +4154,7 @@ exec 5>>./config.log
 
 
 
-user_bfd_gas=
-# Check whether --enable-bfd-assembler or --disable-bfd-assembler was given.
-if test "${enable_bfd_assembler+set}" = set; then
-  enableval="$enable_bfd_assembler"
-  case "${enableval}" in
-  yes) need_bfd=yes user_bfd_gas=yes ;;
-  no)  user_bfd_gas=no ;;
-  *)   { { echo "$as_me:$LINENO: error: bad value ${enableval} given for bfd-assembler option" >&5
-echo "$as_me: error: bad value ${enableval} given for bfd-assembler option" >&2;}
-   { (exit 1); exit 1; }; } ;;
-esac
-fi; # Check whether --enable-targets or --disable-targets was given.
+# Check whether --enable-targets or --disable-targets was given.
 if test "${enable_targets+set}" = set; then
   enableval="$enable_targets"
   case "${enableval}" in
@@ -4066,28 +4178,60 @@ esac
 fi;
 using_cgen=no
 
-build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
+
+GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
+
+# Check whether --enable-werror or --disable-werror was given.
+if test "${enable_werror+set}" = set; then
+  enableval="$enable_werror"
+  case "${enableval}" in
+     yes | y) ERROR_ON_WARNING="yes" ;;
+     no | n)  ERROR_ON_WARNING="no" ;;
+     *) { { echo "$as_me:$LINENO: error: bad value ${enableval} for --enable-werror" >&5
+echo "$as_me: error: bad value ${enableval} for --enable-werror" >&2;}
+   { (exit 1); exit 1; }; } ;;
+   esac
+fi;
+
+# Enable -Werror by default when using gcc
+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then
+    ERROR_ON_WARNING=yes
+fi
+
+NO_WERROR=
+if test "${ERROR_ON_WARNING}" = yes ; then
+    GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Werror"
+    NO_WERROR="-Wno-error"
+fi
+
+if test "${GCC}" = yes ; then
+  WARN_CFLAGS="${GCC_WARN_CFLAGS}"
+fi
+
 # Check whether --enable-build-warnings or --disable-build-warnings was given.
 if test "${enable_build_warnings+set}" = set; then
   enableval="$enable_build_warnings"
   case "${enableval}" in
-  yes)	;;
-  no)	build_warnings="-w";;
+  yes)	WARN_CFLAGS="${GCC_WARN_CFLAGS}";;
+  no)	if test "${GCC}" = yes ; then
+	  WARN_CFLAGS="-w"
+	fi;;
   ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${build_warnings} ${t}";;
+        WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}";;
   *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${t} ${build_warnings}";;
-  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+        WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}";;
+  *)    WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;;
 esac
-if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
-  echo "Setting warning flags = $build_warnings" 6>&1
-fi
-fi; WARN_CFLAGS=""
-if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then
-    WARN_CFLAGS="${build_warnings}"
+fi;
+
+if test x"$silent" != x"yes" && test x"$WARN_CFLAGS" != x""; then
+  echo "Setting warning flags = $WARN_CFLAGS" 6>&1
 fi
 
 
+
+
+
 # Generate a header file
           ac_config_headers="$ac_config_headers config.h:config.in"
 
@@ -4108,6 +4252,238 @@ case "${host}" in
 esac
 
 
+#We need this for the host.  BOUT header is in host order.
+echo "$as_me:$LINENO: checking whether byte ordering is bigendian" >&5
+echo $ECHO_N "checking whether byte ordering is bigendian... $ECHO_C" >&6
+if test "${ac_cv_c_bigendian+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  # See if sys/param.h defines the BYTE_ORDER macro.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  # It does; now see whether it defined to BIG_ENDIAN or not.
+cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <sys/types.h>
+#include <sys/param.h>
+
+int
+main ()
+{
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_c_bigendian=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+ac_cv_c_bigendian=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+# It does not; compile a test program.
+if test "$cross_compiling" = yes; then
+  # try to guess the endianness by grepping values into an object file
+  ac_cv_c_bigendian=unknown
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+short ascii_mm[] = { 0x4249, 0x4765, 0x6E44, 0x6961, 0x6E53, 0x7953, 0 };
+short ascii_ii[] = { 0x694C, 0x5454, 0x656C, 0x6E45, 0x6944, 0x6E61, 0 };
+void _ascii () { char *s = (char *) ascii_mm; s = (char *) ascii_ii; }
+short ebcdic_ii[] = { 0x89D3, 0xE3E3, 0x8593, 0x95C5, 0x89C4, 0x9581, 0 };
+short ebcdic_mm[] = { 0xC2C9, 0xC785, 0x95C4, 0x8981, 0x95E2, 0xA8E2, 0 };
+void _ebcdic () { char *s = (char *) ebcdic_mm; s = (char *) ebcdic_ii; }
+int
+main ()
+{
+ _ascii (); _ebcdic ();
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  if grep BIGenDianSyS conftest.$ac_objext >/dev/null ; then
+  ac_cv_c_bigendian=yes
+fi
+if grep LiTTleEnDian conftest.$ac_objext >/dev/null ; then
+  if test "$ac_cv_c_bigendian" = unknown; then
+    ac_cv_c_bigendian=no
+  else
+    # finding both strings is unlikely to happen, but who knows?
+    ac_cv_c_bigendian=unknown
+  fi
+fi
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+int
+main ()
+{
+  /* Are we little or big endian?  From Harbison&Steele.  */
+  union
+  {
+    long l;
+    char c[sizeof (long)];
+  } u;
+  u.l = 1;
+  exit (u.c[sizeof (long) - 1] == 1);
+}
+_ACEOF
+rm -f conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } && { ac_try='./conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  ac_cv_c_bigendian=no
+else
+  echo "$as_me: program exited with status $ac_status" >&5
+echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+( exit $ac_status )
+ac_cv_c_bigendian=yes
+fi
+rm -f core *.core gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext
+fi
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $ac_cv_c_bigendian" >&5
+echo "${ECHO_T}$ac_cv_c_bigendian" >&6
+case $ac_cv_c_bigendian in
+  yes)
+
+cat >>confdefs.h <<\_ACEOF
+#define WORDS_BIGENDIAN 1
+_ACEOF
+ ;;
+  no)
+     ;;
+  *)
+    { { echo "$as_me:$LINENO: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&5
+echo "$as_me: error: unknown endianness
+presetting ac_cv_c_bigendian=no (or yes) will help" >&2;}
+   { (exit 1); exit 1; }; } ;;
+esac
+
+
 te_file=generic
 
 # Makefile target for installing gas in $(tooldir)/bin.
@@ -4148,55 +4524,17 @@ emulations=""
 
 for this_target in $target $canon_targets ; do
 
-    eval `echo $this_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/cpu=\1 vendor=\2 os=\3/'`
-
-    # check for architecture variants
-    arch=
-    endian=
-    case ${cpu} in
-      am33_2.0)		cpu_type=mn10300 endian=little ;;
-      alpha*)		cpu_type=alpha ;;
-      arm*b|xscale*b|strongarm*b) cpu_type=arm endian=big ;;
-      arm*|xscale*|strongarm*)    cpu_type=arm endian=little ;;
-      c4x*)		cpu_type=tic4x ;;
-      hppa*)		cpu_type=hppa ;;
-      i[3-7]86)		cpu_type=i386 arch=i386;;
-      x86_64)		cpu_type=i386 arch=x86_64;;
-      ia64)		cpu_type=ia64 ;;
-      ip2k)             cpu_type=ip2k endian=big ;;
-      iq2000)           cpu_type=iq2000 endian=big ;;
-      m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
-      m680[012346]0)	cpu_type=m68k ;;
-      m68008)		cpu_type=m68k ;;
-      m683??)		cpu_type=m68k ;;
-      m5200)		cpu_type=m68k ;;
-      m8*)		cpu_type=m88k ;;
-      mips*el)		cpu_type=mips endian=little ;;
-      mips*)		cpu_type=mips endian=big ;;
-      or32*)		cpu_type=or32 endian=big ;;
-      pjl*)		cpu_type=pj endian=little ;;
-      pj*)		cpu_type=pj endian=big ;;
-      powerpc*le*)	cpu_type=ppc endian=little ;;
-      powerpc*)		cpu_type=ppc endian=big ;;
-      rs6000*)		cpu_type=ppc ;;
-      s390x*)		cpu_type=s390 arch=s390x ;;
-      s390*)		cpu_type=s390 arch=s390 ;;
-      sh5*)		cpu_type=sh64 endian=big ;;
-      sh5le*)		cpu_type=sh64 endian=little ;;
-      sh64*)            cpu_type=sh64 endian=big ;;
-      sh64le*)		cpu_type=sh64 endian=little ;;
-      sh*le)		cpu_type=sh endian=little ;;
-      sh*)		cpu_type=sh endian=big ;;
-      sparclite*)	cpu_type=sparc arch=sparclite ;;
-      sparclet*)	cpu_type=sparc arch=sparclet ;;
-      sparc64*)		cpu_type=sparc arch=v9-64 ;;
-      sparc86x*)	cpu_type=sparc arch=sparc86x  ;;
-      sparc*)		cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
-      v850*)		cpu_type=v850 ;;
-      xtensa*)		cpu_type=xtensa arch=xtensa ;;
-      m32r)             cpu_type=m32r target_cpu=m32r endian=big ;;
-      m32rle)           cpu_type=m32r target_cpu=m32r endian=little ;;
-      *)		cpu_type=${cpu} ;;
+    targ=${this_target}
+    . ${srcdir}/configure.tgt
+
+    case ${target_cpu} in
+      crisv32)
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_CRIS_ARCH $arch
+_ACEOF
+
+	;;
     esac
 
     if test ${this_target} = $target ; then
@@ -4205,371 +4543,78 @@ for this_target in $target $canon_targets ; do
       continue
     fi
 
-    generic_target=${cpu_type}-$vendor-$os
-    dev=no
-    bfd_gas=no
-    em=generic
-
-    # assign object format
+    generic_target=${cpu_type}-${target_vendor}-${target_os}
     case ${generic_target} in
-      a29k-*-coff)			fmt=coff ;;
-      a29k-amd-udi)			fmt=coff ;;
-      a29k-amd-ebmon)			fmt=coff ;;
-      a29k-nyu-sym1)			fmt=coff ;;
-      a29k-*-rtems*)			fmt=coff ;;
-      a29k-*-vxworks*)			fmt=coff ;;
-
-      alpha*-*-*vms*)			fmt=evax ;;
-      alpha*-*-netware*)		fmt=ecoff ;;
-      alpha*-*-osf*)			fmt=ecoff ;;
-      alpha*-*-linuxecoff*)		fmt=ecoff ;;
-      alpha*-*-linux-gnu*)		fmt=elf em=linux ;;
-      alpha*-*-netbsd*)			fmt=elf em=nbsd ;;
-      alpha*-*-openbsd*)		fmt=elf em=obsd ;;
-
-      # cpu_type for am33_2.0 is set to mn10300
-      mn10300-*-linux*)			fmt=elf bfd_gas=yes em=linux ;;
-
-      arc-*-elf*)			fmt=elf ;;
-
-      arm-*-aout)			fmt=aout ;;
-      arm-*-coff | thumb-*-coff)	fmt=coff ;;
-      arm-*-rtems* | thumb-*-rtems*)	fmt=elf ;;
-      arm-*-elf | thumb-*-elf)		fmt=elf ;;
-      arm-*-kaos*)			fmt=elf ;;
-      arm*-*-conix*)			fmt=elf ;;
-      arm-*-linux*aout*)		fmt=aout em=linux ;;
-      arm*-*-linux-gnu*)		fmt=elf  em=linux ;;
-      arm*-*-uclinux*)			fmt=elf  em=linux ;;
-      arm-*-netbsdelf*)                 fmt=elf  em=nbsd ;;
-      arm-*-*n*bsd*)			fmt=aout em=nbsd ;;
-      arm-**-nto*)			fmt=elf ;;
-      arm-*-oabi | thumb-*-oabi)	fmt=elf ;;
-      arm-epoc-pe | thumb-epoc-pe)	fmt=coff em=epoc-pe ;;
-      arm-wince-pe | arm-*-wince)       fmt=coff em=wince-pe ;;
-      arm-*-pe | thumb-*-pe)		fmt=coff em=pe ;;
-      arm-*-riscix*)			fmt=aout em=riscix ;;
-
-      avr-*-*)				fmt=elf ;;
-
-      cris-*-linux-gnu*)		fmt=multi bfd_gas=yes em=linux ;;
-      cris-*-*)				fmt=multi bfd_gas=yes ;;
-
-      d10v-*-*)				fmt=elf ;;
-      d30v-*-*)				fmt=elf ;;
-      dlx-*-*)				fmt=elf ;;
-
-      fr30-*-*)				fmt=elf ;;
-      frv-*-*linux*)			fmt=elf em=linux;;
-      frv-*-*)				fmt=elf ;;
-
-      hppa-*-linux*)	case ${cpu} in
-			    hppa*64*)	fmt=elf em=hppalinux64;;
-			    hppa*)	fmt=elf em=linux;;
-			esac ;;
-      hppa-*-*elf*)			fmt=elf em=hppa ;;
-      hppa-*-lites*)			fmt=elf em=hppa ;;
-      hppa-*-netbsd*)			fmt=elf em=nbsd ;;
-      hppa-*-openbsd*)			fmt=elf em=hppa ;;
-      hppa-*-osf*)			fmt=som em=hppa ;;
-      hppa-*-rtems*)			fmt=elf em=hppa ;;
-      hppa-*-hpux11*)	case ${cpu} in
-			    hppa*64*)	fmt=elf em=hppa64 ;;
-			    hppa*)	fmt=som em=hppa ;;
-			esac ;;
-      hppa-*-hpux*)			fmt=som em=hppa ;;
-      hppa-*-mpeix*)			fmt=som em=hppa ;;
-      hppa-*-bsd*)			fmt=som em=hppa ;;
-      hppa-*-hiux*)			fmt=som em=hppa ;;
-
-      h8300-*-rtems*)			fmt=coff ;;
-      h8300-*-coff)			fmt=coff ;;
-      h8300-*-elf)			fmt=elf ;;
-      h8500-*-rtems*)			fmt=coff ;;
-      h8500-*-coff)			fmt=coff ;;
-
-      i370-*-elf* | i370-*-linux*)	fmt=elf ;;
-      i386-ibm-aix*)			fmt=coff em=i386aix ;;
-      i386-sequent-bsd*)		fmt=aout em=dynix ;;
-      i386-*-beospe*)			fmt=coff em=pe ;;
-      i386-*-beos*)			fmt=elf ;;
-      i386-*-coff)			fmt=coff ;;
-      i386-*-elf)			fmt=elf ;;
-      i386-*-kaos*)			fmt=elf ;;
-      i386-*-bsd*)			fmt=aout em=386bsd ;;
-      i386-*-netbsd0.8)			fmt=aout em=386bsd ;;
-      i386-*-netbsdpe*)			fmt=coff em=pe ;;
-      i386-*-netbsd*-gnu* | \
-      i386-*-knetbsd*-gnu | \
-      i386-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      i386-*-*n*bsd*)	case ${cpu} in
-			    x86_64)	fmt=elf em=nbsd ;;
-			    *)		fmt=aout em=nbsd ;;
-			esac ;;
-      i386-*-linux*aout*)		fmt=aout em=linux ;;
-      i386-*-linux*oldld)		fmt=aout em=linux ;;
-      i386-*-linux*coff*)		fmt=coff em=linux ;;
-      i386-*-linux-gnu*)		fmt=elf em=linux ;;
-      x86_64-*-linux-gnu*)		fmt=elf em=linux ;;
-      i386-*-lynxos*)			fmt=coff em=lynx ;;
-      i386-*-sysv[45]*)			fmt=elf ;;
-      i386-*-solaris*)			fmt=elf ;;
-      i386-*-freebsdaout*)		fmt=aout em=386bsd ;;
-      i386-*-freebsd[12].*)		fmt=aout em=386bsd ;;
-      i386-*-freebsd[12])		fmt=aout em=386bsd ;;
-      i386-*-freebsd* | i386-*-kfreebsd*-gnu)
-					fmt=elf em=freebsd ;;
-      i386-*-sysv*)			fmt=coff ;;
-      i386-*-sco3.2v5*coff)		fmt=coff ;;
-      i386-*-isc*)			fmt=coff ;;
-      i386-*-sco3.2v5*)			fmt=elf
-	  if test ${this_target} = $target; then
+      i386-*-sco3.2v5*)
+	if test ${this_target} = $target; then
 
 cat >>confdefs.h <<\_ACEOF
 #define SCO_ELF 1
 _ACEOF
 
-	  fi ;;
-      i386-*-sco3.2*)			fmt=coff ;;
-      i386-*-vsta)			fmt=aout ;;
+	fi
+	;;
+
       i386-*-msdosdjgpp* \
       | i386-*-go32* \
-      | i386-go32-rtems*)		fmt=coff em=go32
+      | i386-go32-rtems*)
 
 cat >>confdefs.h <<\_ACEOF
 #define STRICTCOFF 1
 _ACEOF
- ;;
-      i386-*-rtemself*)			fmt=elf ;;
-      i386-*-rtemscoff*)		fmt=coff ;;
-      i386-*-rtems*)			fmt=elf ;;
-      i386-*-gnu*)			fmt=elf ;;
-      i386-*-mach*)			fmt=aout em=mach ;;
-      i386-*-msdos*)			fmt=aout ;;
-      i386-*-moss*)			fmt=elf ;;
-      i386-*-pe)			fmt=coff em=pe ;;
-      i386-*-cygwin*)			fmt=coff em=pe ;;
-      i386-*-interix*)			fmt=coff em=interix ;;
-      i386-*-mingw32*)			fmt=coff em=pe ;;
-      i386-*-nto-qnx*)			fmt=elf ;;
-      i386-*-*nt*)			fmt=coff em=pe ;;
-      i386-*-chaos)			fmt=elf ;;
-
-      i860-*-*)				fmt=elf endian=little
-		{ echo "$as_me:$LINENO: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&5
-echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;} ;;
-      i960-*-bout)			fmt=bout ;;
-      i960-*-coff)			fmt=coff em=ic960 ;;
-      i960-*-rtems*)			fmt=coff em=ic960 ;;
-      i960-*-nindy*)			fmt=bout ;;
-      i960-*-vxworks5.0)		fmt=bout ;;
-      i960-*-vxworks5.*)		fmt=coff em=ic960 ;;
-      i960-*-vxworks*)			fmt=bout ;;
-      i960-*-elf*)			fmt=elf ;;
-
-      ia64-*-elf*)			fmt=elf ;;
-      ia64-*-aix*)			fmt=elf em=ia64aix ;;
-      ia64-*-linux-gnu*)		fmt=elf em=linux ;;
-      ia64-*-hpux*)			fmt=elf em=hpux ;;
-      ia64-*-netbsd*)			fmt=elf em=nbsd ;;
-
-      ip2k-*-*)				fmt=elf ;;
-
-      iq2000-*-elf)         		fmt=elf bfd_gas=yes ;;
-
-      m32r-*-elf*)			fmt=elf ;;
-      m32r-*-linux*)			fmt=elf em=linux;;
-
-      m68hc11-*-* | m6811-*-*)		fmt=elf ;;
-      m68hc12-*-* | m6812-*-*)		fmt=elf ;;
-
-      m68k-*-vxworks*)			fmt=aout em=sun3 ;;
-      m68k-ericsson-ose)		fmt=aout em=sun3 ;;
-      m68k-*-sunos*)			fmt=aout em=sun3 ;;
-      m68k-motorola-sysv*)		fmt=coff em=delta ;;
-      m68k-bull-sysv3*)			fmt=coff em=dpx2 ;;
-      m68k-apollo-*)			fmt=coff em=apollo ;;
-      m68k-*-elf*)			fmt=elf ;;
-      m68k-*-sysv4*)			fmt=elf em=svr4 ;;
-      m68k-*-sysv*)			fmt=coff ;;
-      m68k-*-coff | m68k-*-rtemscoff*)	fmt=coff ;;
-      m68k-*-rtems*)			fmt=elf ;;
-      m68k-*-hpux*)			fmt=hp300 em=hp300 ;;
-      m68k-*-linux*aout*)		fmt=aout em=linux ;;
-      m68k-*-linux-gnu*)		fmt=elf em=linux ;;
-      m68k-*-uclinux*)			fmt=elf ;;
-      m68k-*-gnu*)			fmt=elf ;;
-      m68k-*-lynxos*)			fmt=coff em=lynx ;;
-      m68k-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      m68k-*-netbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
-      m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
-      m68k-apple-aux*)			fmt=coff em=aux ;;
-      m68k-*-psos*)			fmt=elf em=psos;;
-
-      m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
-      m88k-*-coff*)			fmt=coff ;;
-
-      mcore-*-elf)			fmt=elf ;;
-      mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
-
-      # don't change em like *-*-bsd does
-      mips-dec-openbsd*)		fmt=elf endian=little ;;
-      mips-sony-bsd*)			fmt=ecoff ;;
+
+	;;
+
+      i860-*-*)
+	{ echo "$as_me:$LINENO: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&5
+echo "$as_me: WARNING: GAS support for ${generic_target} is preliminary and a work in progress" >&2;}
+	;;
+
+      mips-sony-bsd*)
+	;;
       mips-*-bsd*)
-	    { { echo "$as_me:$LINENO: error: Unknown vendor for mips-bsd configuration." >&5
+	{ { echo "$as_me:$LINENO: error: Unknown vendor for mips-bsd configuration." >&5
 echo "$as_me: error: Unknown vendor for mips-bsd configuration." >&2;}
-   { (exit 1); exit 1; }; } ;;
-      mips-*-ultrix*)			fmt=ecoff endian=little ;;
-      mips-*-osf*)			fmt=ecoff endian=little ;;
-      mips-*-ecoff*)			fmt=ecoff ;;
-      mips-*-pe*)			fmt=coff endian=little em=pe ;;
-      mips-*-irix6*)			fmt=elf em=irix ;;
-      mips-*-irix5*)			fmt=elf em=irix ;;
-      mips-*-irix*)			fmt=ecoff em=irix ;;
-      mips-*-lnews*)			fmt=ecoff em=lnews ;;
-      mips-*-riscos*)			fmt=ecoff ;;
-      mips*-*-linux*)			fmt=elf em=tmips ;;
-      mips-*-sysv4*MP* | mips-*-gnu*)	fmt=elf em=tmips ;;
-      mips-*-sysv*)			fmt=ecoff ;;
-      mips-*-elf* | mips-*-rtems*)	fmt=elf ;;
-      mips-*-netbsd*)			fmt=elf ;;
-      mips-*-openbsd*)			fmt=elf ;;
-
-      mmix-*-*)				fmt=elf ;;
-      mn10200-*-*)			fmt=elf ;;
-      mn10300-*-*)			fmt=elf ;;
-      msp430-*-*)			fmt=elf ;;
-      openrisc-*-*)			fmt=elf ;;
-      or32-*-rtems*)			fmt=elf ;;
-      or32-*-coff)			fmt=coff ;;
-      or32-*-elf)			fmt=elf ;;
-      pj*)				fmt=elf ;;
-
-      ppc-*-pe | ppc-*-cygwin*)		fmt=coff em=pe ;;
-      ppc-*-winnt*)			fmt=coff em=pe ;;
-      ppc-*-aix5.[01])			fmt=coff em=aix5 ;;
-      ppc-*-aix5.*)			fmt=coff em=aix5
+   { (exit 1); exit 1; }; }
+	;;
+
+      ppc-*-aix5.*)
 
 cat >>confdefs.h <<\_ACEOF
 #define AIX_WEAK_SUPPORT 1
 _ACEOF
 
-      ;;
-      ppc-*-aix*)			fmt=coff ;;
-      ppc-*-beos*)			fmt=coff ;;
-      ppc-*-*n*bsd* | ppc-*-elf*)	fmt=elf ;;
-      ppc-*-eabi* | ppc-*-sysv4*)	fmt=elf ;;
-      ppc-*-linux-gnu*)			fmt=elf em=linux
-	    case "$endian" in
-		big)  ;;
-		*)    { { echo "$as_me:$LINENO: error: GNU/Linux must be configured big endian" >&5
+	;;
+      ppc-*-linux-*)
+	case "$endian" in
+	  big)  ;;
+	  *)    { { echo "$as_me:$LINENO: error: GNU/Linux must be configured big endian" >&5
 echo "$as_me: error: GNU/Linux must be configured big endian" >&2;}
    { (exit 1); exit 1; }; } ;;
-	    esac ;;
-      ppc-*-solaris*)			fmt=elf
-	    if test ${this_target} = $target; then
+	esac
+	;;
+      ppc-*-solaris*)
+	if test ${this_target} = $target; then
 
 cat >>confdefs.h <<\_ACEOF
 #define TARGET_SOLARIS_COMMENT 1
 _ACEOF
 
-	    fi
-	    if test x${endian} = xbig; then
-		{ { echo "$as_me:$LINENO: error: Solaris must be configured little endian" >&5
+	fi
+	if test x${endian} = xbig; then
+	  { { echo "$as_me:$LINENO: error: Solaris must be configured little endian" >&5
 echo "$as_me: error: Solaris must be configured little endian" >&2;}
    { (exit 1); exit 1; }; }
-	    fi ;;
-      ppc-*-rtems*)			fmt=elf ;;
-      ppc-*-macos* | ppc-*-mpw*)	fmt=coff em=macos ;;
-      ppc-*-netware*)			fmt=elf em=ppcnw ;;
-      ppc-**-nto*)			fmt=elf ;;
-      ppc-*-kaos*)			fmt=elf ;;
-
-      s390x-*-linux-gnu*)		fmt=elf em=linux ;;
-      s390-*-linux-gnu*)		fmt=elf em=linux ;;
-
-      sh*-*-linux*)			fmt=elf em=linux
-	    case ${cpu} in
-		sh*eb)	endian=big ;;
-		*)	endian=little ;;
-	    esac ;;
-      sh5*-*-netbsd*)			fmt=elf em=nbsd ;;
-      sh64*-*-netbsd*)			fmt=elf em=nbsd ;;
-      sh*-*-netbsdelf*)			fmt=elf em=nbsd ;;
-      sh-*-elf*)			fmt=elf ;;
-      sh-*-coff*)			fmt=coff ;;
-      sh-*-nto*)			fmt=elf ;;
-      sh-*-pe*)				fmt=coff em=pe bfd_gas=yes endian=little ;;
-      sh-*-rtemscoff*)			fmt=coff ;;
-      sh-*-rtems*)			fmt=elf ;;
-      sh-*-kaos*)			fmt=elf ;;
-      shle*-*-kaos*)			fmt=elf ;;
-      sh64-*-elf*)			fmt=elf ;;
-
-      ns32k-pc532-mach*)		fmt=aout em=pc532mach ;;
-      ns32k-pc532-ux*)			fmt=aout em=pc532mach ;;
-      ns32k-pc532-lites*)		fmt=aout em=nbsd532 ;;
-      ns32k-*-*n*bsd*)			fmt=aout em=nbsd532 ;;
-
-      sparc-*-rtemsaout*)		fmt=aout ;;
-      sparc-*-rtemself*)		fmt=elf ;;
-      sparc-*-rtems*)			fmt=elf ;;
-      sparc-*-sunos4*)			fmt=aout em=sun3 ;;
-      sparc-*-aout | sparc*-*-vxworks*)	fmt=aout em=sparcaout ;;
-      sparc-*-coff)			fmt=coff ;;
-      sparc-*-linux*aout*)		fmt=aout em=linux ;;
-      sparc-*-linux-gnu*)		fmt=elf em=linux ;;
-      sparc-*-lynxos*)			fmt=coff em=lynx ;;
-      sparc-fujitsu-none)		fmt=aout ;;
-      sparc-*-elf)			fmt=elf ;;
-      sparc-*-sysv4*)			fmt=elf ;;
-      sparc-*-solaris*)			fmt=elf ;;
-      sparc-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      sparc-*-*n*bsd*)	case ${cpu} in
-			    sparc64)	fmt=elf em=nbsd ;;
-			    *)		fmt=aout em=nbsd ;;
-			esac ;;
-      strongarm-*-coff)			fmt=coff ;;
-      strongarm-*-elf)			fmt=elf ;;
-      strongarm-*-kaos*)		fmt=elf ;;
-      xscale-*-coff)			fmt=coff ;;
-      xscale-*-elf)			fmt=elf ;;
-
-      tic30-*-*aout*)			fmt=aout bfd_gas=yes ;;
-      tic30-*-*coff*)			fmt=coff bfd_gas=yes ;;
-      tic4x-*-* | c4x-*-*)              fmt=coff bfd_gas=yes ;;
-      tic54x-*-* | c54x*-*-*)		fmt=coff bfd_gas=yes need_libm=yes;;
-      tic80-*-*)			fmt=coff ;;
-
-      v850-*-*)				fmt=elf ;;
-      v850e-*-*)			fmt=elf ;;
-      v850ea-*-*)			fmt=elf ;;
-
-      vax-*-netbsdelf*)			fmt=elf em=nbsd ;;
-      vax-*-netbsd*)			fmt=aout em=nbsd ;;
-      vax-*-bsd* | vax-*-ultrix*)	fmt=aout ;;
-      vax-*-linux-gnu*)			fmt=elf em=linux bfd_gas=yes ;;
-      vax-*-vms)			fmt=vms ;;
-
-      w65-*-*)				fmt=coff ;;
-
-      xstormy16-*-*)			fmt=elf ;;
-
-      xtensa-*-*)			fmt=elf ;;
-
-      z8k-*-coff | z8k-*-sim)		fmt=coff ;;
-
-      *-*-aout | *-*-scout)		fmt=aout ;;
-      *-*-freebsd* | *-*-kfreebsd*-gnu)	fmt=elf em=freebsd ;;
-      *-*-nindy*)			fmt=bout ;;
-      *-*-bsd*)				fmt=aout em=sun3 ;;
-      *-*-generic)			fmt=generic ;;
-      *-*-xray | *-*-hms)		fmt=coff ;;
-      *-*-sim)				fmt=coff ;;
-      *-*-elf | *-*-sysv4* | *-*-solaris*) fmt=elf dev=yes ;;
-      *-*-aros*)			fmt=elf em=linux bfd_gas=yes ;;
-      *-*-vxworks | *-*-windiss)	fmt=elf ;;
-      *-*-netware)			fmt=elf ;;
+	fi
+	;;
+
+      sh*-*-symbianelf*)
+
+cat >>confdefs.h <<\_ACEOF
+#define TARGET_SYMBIAN 1
+_ACEOF
+
+	;;
     esac
 
     if test ${this_target} = $target ; then
@@ -4588,13 +4633,6 @@ _ACEOF
       fi
     fi
 
-    case ${cpu_type}-${fmt} in
-	alpha*-* | arm-* | i386-* | ia64*-* | mips-* | ns32k-* \
-		| pdp11-* | ppc-* | sparc-* | strongarm-* | xscale-* \
-		| *-elf | *-ecoff | *-som)
-	    bfd_gas=yes ;;
-    esac
-
 # Other random stuff.
 
     case ${cpu_type} in
@@ -4663,6 +4701,9 @@ echo "$as_me: error: $target_cpu isn't a supported MIPS CPU name" >&2;}
 	  mips*-linux*)
 	    mips_default_abi=O32_ABI
 	    ;;
+	  mips64*-openbsd*)
+	    mips_default_abi=N64_ABI
+	    ;;
 	  *)
 	    mips_default_abi=NO_ABI
 	    ;;
@@ -4703,19 +4744,31 @@ _ACEOF
 	*opcodes*) shared_opcodes=true ;;
 	*) shared_opcodes=false ;;
 	esac
-	if test "${shared_opcodes}" = "true"; then
-	  # A shared libopcodes must be linked against libbfd.
-	  need_bfd=yes
-	fi
 	;;
     esac
 
     # Any other special object files needed ?
     case ${cpu_type} in
+
+      bfin)
+        echo ${extra_objects} | grep -s "bfin-parse.o"
+        if test $? -ne 0 ; then
+          extra_objects="$extra_objects bfin-parse.o"
+        fi
+
+        echo ${extra_objects} | grep -s "bfin-lex.o"
+        if test $? -ne 0 ; then
+          extra_objects="$extra_objects bfin-lex.o"
+        fi
+        ;;
+
       fr30 | ip2k | iq2000 | m32r | openrisc)
 	using_cgen=yes
 	;;
 
+      m32c)
+	using_cgen=yes
+	;;
       frv)
 	using_cgen=yes
 	;;
@@ -4743,6 +4796,10 @@ _ACEOF
 	fi
 	;;
 
+      mt)
+        using_cgen=yes
+	;;
+
       i386 | s390 | sparc)
 	if test $this_target = $target ; then
 
@@ -4757,6 +4814,10 @@ _ACEOF
 	using_cgen=yes
 	;;
 
+      xc16x)
+	using_cgen=yes
+	;;
+
       xtensa)
 	echo ${extra_objects} | grep -s "xtensa-relax.o"
 	if test $? -ne 0 ; then
@@ -4778,17 +4839,8 @@ _ACEOF
 # See if we really can support this configuration with the emulation code.
 
     if test $this_target = $target ; then
-      primary_bfd_gas=$bfd_gas
       obj_format=$fmt
       te_file=$em
-
-      if test $bfd_gas = no ; then
-	# Can't support other configurations this way.
-	break
-      fi
-    elif test $bfd_gas = no ; then
-      # Can't support this configuration.
-      break
     fi
 
 # From target name and format, produce a list of supported emulations.
@@ -4889,28 +4941,6 @@ echo "$as_me: error: GAS does not have support for object file format ${obj_form
    { (exit 1); exit 1; }; }
 fi
 
-case ${user_bfd_gas}-${primary_bfd_gas} in
-  yes-yes | no-no)
-    # We didn't override user's choice.
-    ;;
-  no-yes)
-    { echo "$as_me:$LINENO: WARNING: Use of BFD is required for ${target}; overriding config options." >&5
-echo "$as_me: WARNING: Use of BFD is required for ${target}; overriding config options." >&2;}
-    ;;
-  no-preferred)
-    primary_bfd_gas=no
-    ;;
-  *-preferred)
-    primary_bfd_gas=yes
-    ;;
-  yes-*)
-    primary_bfd_gas=yes
-    ;;
-  -*)
-    # User specified nothing.
-    ;;
-esac
-
 # Some COFF configurations want these random other flags set.
 case ${obj_format} in
   coff)
@@ -4935,8 +4965,8 @@ _ACEOF
 esac
 
 # Getting this done right is going to be a bitch.  Each configuration specified
-# with --enable-targets=... should be checked for environment, format, cpu, and
-# bfd_gas setting.
+# with --enable-targets=... should be checked for environment, format, cpu
+# setting.
 #
 # For each configuration, the necessary object file support code must be linked
 # in.  This might be only one, it might be up to four.  The necessary emulation
@@ -5039,11 +5069,6 @@ cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_GENERIC 1
 _ACEOF
  ;;
-      hp300)
-cat >>confdefs.h <<\_ACEOF
-#define OBJ_MAYBE_HP300 1
-_ACEOF
-   ;;
       ieee)
 cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_IEEE 1
@@ -5054,11 +5079,6 @@ cat >>confdefs.h <<\_ACEOF
 #define OBJ_MAYBE_SOM 1
 _ACEOF
      ;;
-      vms)
-cat >>confdefs.h <<\_ACEOF
-#define OBJ_MAYBE_VMS 1
-_ACEOF
-     ;;
     esac
     extra_objects="$extra_objects obj-$fmt.o"
   done
@@ -5091,16 +5111,6 @@ cat >>confdefs.h <<_ACEOF
 _ACEOF
 
 
-case ${primary_bfd_gas}-${target_cpu_type}-${obj_format} in
-  yes-*-coff)	need_bfd=yes ;;
-  no-*-coff)	need_bfd=yes
-
-cat >>confdefs.h <<\_ACEOF
-#define MANY_SEGMENTS 1
-_ACEOF
- ;;
-esac
-
 reject_dev_configs=yes
 
 case ${reject_dev_configs}-${dev} in
@@ -5117,15 +5127,6 @@ esac
 
 
 
-case "${primary_bfd_gas}" in
-  yes)
-cat >>confdefs.h <<\_ACEOF
-#define BFD_ASSEMBLER 1
-_ACEOF
-
-	need_bfd=yes ;;
-esac
-
 # do we need the opcodes library?
 case "${need_opcodes}" in
 yes)
@@ -5133,13 +5134,9 @@ yes)
   ;;
 esac
 
-case "${need_bfd}" in
-yes)
-  BFDLIB=../bfd/libbfd.la
-  BFDVER_H=../bfd/bfdver.h
-  ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-  ;;
-esac
+BFDLIB=../bfd/libbfd.la
+BFDVER_H=../bfd/bfdver.h
+ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
 
 
 
@@ -5540,7 +5537,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5598,7 +5596,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5714,7 +5713,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5768,7 +5768,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5813,7 +5814,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5857,7 +5859,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6019,7 +6022,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6085,7 +6089,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6174,7 +6179,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6213,7 +6219,7 @@ if test "$LEX" = :; then
   LEX=${am_missing_run}flex
 fi
 
-ALL_LINGUAS="fr tr es"
+ALL_LINGUAS="fr tr es rw"
 if test -n "$ac_tool_prefix"; then
   # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args.
 set dummy ${ac_tool_prefix}ranlib; ac_word=$2
@@ -6577,7 +6583,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6784,7 +6791,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6844,7 +6852,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6923,7 +6932,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6988,7 +6998,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7053,7 +7064,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7117,7 +7129,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7198,7 +7211,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7339,7 +7353,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7477,7 +7492,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7661,7 +7677,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7912,7 +7929,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8106,7 +8124,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8209,7 +8228,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8280,7 +8300,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8328,11 +8349,6 @@ echo "${ECHO_T}$USE_NLS" >&6
     USE_INCLUDED_LIBINTL=no
 
         if test "$USE_NLS" = "yes"; then
-
-cat >>confdefs.h <<\_ACEOF
-#define ENABLE_NLS 1
-_ACEOF
-
       echo "$as_me:$LINENO: checking whether included gettext is requested" >&5
 echo $ECHO_N "checking whether included gettext is requested... $ECHO_C" >&6
 
@@ -8350,7 +8366,7 @@ echo "${ECHO_T}$nls_cv_force_use_gnu_gettext" >&6
       if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
                         		nls_cv_header_intl=
 	nls_cv_header_libgt=
-	CATOBJEXT=NONE
+	CATOBJEXT=
 
 	if test "${ac_cv_header_libintl_h+set}" = set; then
   echo "$as_me:$LINENO: checking for libintl.h" >&5
@@ -8382,7 +8398,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8518,7 +8535,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8582,7 +8600,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8637,7 +8656,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8777,7 +8797,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8910,7 +8931,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8942,8 +8964,10 @@ fi
 
 
 
-        if test "$CATOBJEXT" = "NONE"; then
-	  	  	  nls_cv_use_gnu_gettext=yes
+        if test x"$CATOBJEXT" = x && test -d $srcdir/../intl; then
+	  # Neither gettext nor catgets in included in the C library.
+	  # Fall back on GNU gettext library (assuming it is present).
+	  nls_cv_use_gnu_gettext=yes
         fi
       fi
 
@@ -9114,6 +9138,13 @@ echo "${ECHO_T}found xgettext programs is not GNU xgettext; ignore it" >&6
 
 
 
+    if test "x$CATOBJEXT" != "x"; then
+
+cat >>confdefs.h <<\_ACEOF
+#define ENABLE_NLS 1
+_ACEOF
+
+    fi
 
 
    if test "x$CATOBJEXT" != "x"; then
@@ -9178,7 +9209,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9399,7 +9431,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9563,7 +9596,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9644,7 +9678,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9785,7 +9820,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9917,7 +9953,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10030,7 +10067,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10133,7 +10171,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10171,8 +10210,9 @@ case "${need_libm}" in
 yes)
   LIBM=
 case $host in
-*-*-beos* | *-*-cygwin* | *-*-pw32*)
+*-*-beos* | *-*-cygwin* | *-*-pw32* | *-*-darwin*)
   # These system don't have libm
+  # on darwin the libm is a symbolic link to libSystem.dylib
   ;;
 *-ncr-sysv4.3*)
   echo "$as_me:$LINENO: checking for _mwvalidcheckl in -lmw" >&5
@@ -10213,7 +10253,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10274,7 +10315,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10337,7 +10379,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10414,7 +10457,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10467,9 +10511,146 @@ gas_test_headers="
 #endif
 "
 
-echo "$as_me:$LINENO: checking whether declaration is required for strstr" >&5
-echo $ECHO_N "checking whether declaration is required for strstr... $ECHO_C" >&6
-if test "${gas_cv_decl_needed_strstr+set}" = set; then
+# Does errno.h declare errno, or do we have to add a separate declaration
+# for it?
+
+echo "$as_me:$LINENO: checking whether declaration is required for errno" >&5
+echo $ECHO_N "checking whether declaration is required for errno... $ECHO_C" >&6
+if test "${gas_cv_decl_needed_errno+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+
+#ifdef HAVE_ERRNO_H
+#include <errno.h>
+#endif
+
+int
+main ()
+{
+
+typedef int f;
+f x;
+x = (f) errno;
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  gas_cv_decl_needed_errno=no
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+gas_cv_decl_needed_errno=yes
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $gas_cv_decl_needed_errno" >&5
+echo "${ECHO_T}$gas_cv_decl_needed_errno" >&6
+if test $gas_cv_decl_needed_errno = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define NEED_DECLARATION_ERRNO 1
+_ACEOF
+
+fi
+
+
+echo "$as_me:$LINENO: checking for a known getopt prototype in unistd.h" >&5
+echo $ECHO_N "checking for a known getopt prototype in unistd.h... $ECHO_C" >&6
+if test "${gas_cv_decl_getopt_unistd_h+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+#include <unistd.h>
+int
+main ()
+{
+extern int getopt (int, char *const*, const char *);
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest.$ac_objext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  gas_cv_decl_getopt_unistd_h=yes
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+gas_cv_decl_getopt_unistd_h=no
+fi
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+
+echo "$as_me:$LINENO: result: $gas_cv_decl_getopt_unistd_h" >&5
+echo "${ECHO_T}$gas_cv_decl_getopt_unistd_h" >&6
+if test $gas_cv_decl_getopt_unistd_h = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define HAVE_DECL_GETOPT 1
+_ACEOF
+
+fi
+
+
+echo "$as_me:$LINENO: checking whether declaration is required for environ" >&5
+echo $ECHO_N "checking whether declaration is required for environ... $ECHO_C" >&6
+if test "${gas_cv_decl_needed_environ+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   cat >conftest.$ac_ext <<_ACEOF
@@ -10483,9 +10664,9 @@ int
 main ()
 {
 
-typedef char *(*f)();
+typedef char **f;
 f x;
-x = (f) strstr;
+x = (f) environ;
 
   ;
   return 0;
@@ -10500,7 +10681,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10512,30 +10694,30 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  gas_cv_decl_needed_strstr=no
+  gas_cv_decl_needed_environ=no
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-gas_cv_decl_needed_strstr=yes
+gas_cv_decl_needed_environ=yes
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 fi
-echo "$as_me:$LINENO: result: $gas_cv_decl_needed_strstr" >&5
-echo "${ECHO_T}$gas_cv_decl_needed_strstr" >&6
-if test $gas_cv_decl_needed_strstr = yes; then
+echo "$as_me:$LINENO: result: $gas_cv_decl_needed_environ" >&5
+echo "${ECHO_T}$gas_cv_decl_needed_environ" >&6
+if test $gas_cv_decl_needed_environ = yes; then
 
 cat >>confdefs.h <<\_ACEOF
-#define NEED_DECLARATION_STRSTR 1
+#define NEED_DECLARATION_ENVIRON 1
 _ACEOF
 
 fi
 
 
-echo "$as_me:$LINENO: checking whether declaration is required for malloc" >&5
-echo $ECHO_N "checking whether declaration is required for malloc... $ECHO_C" >&6
-if test "${gas_cv_decl_needed_malloc+set}" = set; then
+echo "$as_me:$LINENO: checking whether declaration is required for ffs" >&5
+echo $ECHO_N "checking whether declaration is required for ffs... $ECHO_C" >&6
+if test "${gas_cv_decl_needed_ffs+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   cat >conftest.$ac_ext <<_ACEOF
@@ -10549,9 +10731,9 @@ int
 main ()
 {
 
-typedef char *(*f)();
+typedef int (*f)(int);
 f x;
-x = (f) malloc;
+x = (f) ffs;
 
   ;
   return 0;
@@ -10566,7 +10748,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10578,22 +10761,22 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  gas_cv_decl_needed_malloc=no
+  gas_cv_decl_needed_ffs=no
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-gas_cv_decl_needed_malloc=yes
+gas_cv_decl_needed_ffs=yes
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 fi
-echo "$as_me:$LINENO: result: $gas_cv_decl_needed_malloc" >&5
-echo "${ECHO_T}$gas_cv_decl_needed_malloc" >&6
-if test $gas_cv_decl_needed_malloc = yes; then
+echo "$as_me:$LINENO: result: $gas_cv_decl_needed_ffs" >&5
+echo "${ECHO_T}$gas_cv_decl_needed_ffs" >&6
+if test $gas_cv_decl_needed_ffs = yes; then
 
 cat >>confdefs.h <<\_ACEOF
-#define NEED_DECLARATION_MALLOC 1
+#define NEED_DECLARATION_FFS 1
 _ACEOF
 
 fi
@@ -10632,7 +10815,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10665,6 +10849,73 @@ _ACEOF
 fi
 
 
+echo "$as_me:$LINENO: checking whether declaration is required for malloc" >&5
+echo $ECHO_N "checking whether declaration is required for malloc... $ECHO_C" >&6
+if test "${gas_cv_decl_needed_malloc+set}" = set; then
+  echo $ECHO_N "(cached) $ECHO_C" >&6
+else
+  cat >conftest.$ac_ext <<_ACEOF
+/* confdefs.h.  */
+_ACEOF
+cat confdefs.h >>conftest.$ac_ext
+cat >>conftest.$ac_ext <<_ACEOF
+/* end confdefs.h.  */
+$gas_test_headers
+int
+main ()
+{
+
+typedef char *(*f)();
+f x;
+x = (f) malloc;
+
+  ;
+  return 0;
+}
+_ACEOF
+rm -f conftest.$ac_objext conftest$ac_exeext
+if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
+  (eval $ac_link) 2>conftest.er1
+  ac_status=$?
+  grep -v '^ *+' conftest.er1 >conftest.err
+  rm -f conftest.er1
+  cat conftest.err >&5
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); } &&
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; } &&
+	 { ac_try='test -s conftest$ac_exeext'
+  { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
+  (eval $ac_try) 2>&5
+  ac_status=$?
+  echo "$as_me:$LINENO: \$? = $ac_status" >&5
+  (exit $ac_status); }; }; then
+  gas_cv_decl_needed_malloc=no
+else
+  echo "$as_me: failed program was:" >&5
+sed 's/^/| /' conftest.$ac_ext >&5
+
+gas_cv_decl_needed_malloc=yes
+fi
+rm -f conftest.err conftest.$ac_objext \
+      conftest$ac_exeext conftest.$ac_ext
+fi
+echo "$as_me:$LINENO: result: $gas_cv_decl_needed_malloc" >&5
+echo "${ECHO_T}$gas_cv_decl_needed_malloc" >&6
+if test $gas_cv_decl_needed_malloc = yes; then
+
+cat >>confdefs.h <<\_ACEOF
+#define NEED_DECLARATION_MALLOC 1
+_ACEOF
+
+fi
+
+
 echo "$as_me:$LINENO: checking whether declaration is required for sbrk" >&5
 echo $ECHO_N "checking whether declaration is required for sbrk... $ECHO_C" >&6
 if test "${gas_cv_decl_needed_sbrk+set}" = set; then
@@ -10698,7 +10949,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10731,9 +10983,9 @@ _ACEOF
 fi
 
 
-echo "$as_me:$LINENO: checking whether declaration is required for environ" >&5
-echo $ECHO_N "checking whether declaration is required for environ... $ECHO_C" >&6
-if test "${gas_cv_decl_needed_environ+set}" = set; then
+echo "$as_me:$LINENO: checking whether declaration is required for strstr" >&5
+echo $ECHO_N "checking whether declaration is required for strstr... $ECHO_C" >&6
+if test "${gas_cv_decl_needed_strstr+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   cat >conftest.$ac_ext <<_ACEOF
@@ -10747,9 +10999,9 @@ int
 main ()
 {
 
-typedef char **f;
+typedef char *(*f)();
 f x;
-x = (f) environ;
+x = (f) strstr;
 
   ;
   return 0;
@@ -10764,7 +11016,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10776,33 +11029,30 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  gas_cv_decl_needed_environ=no
+  gas_cv_decl_needed_strstr=no
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-gas_cv_decl_needed_environ=yes
+gas_cv_decl_needed_strstr=yes
 fi
 rm -f conftest.err conftest.$ac_objext \
       conftest$ac_exeext conftest.$ac_ext
 fi
-echo "$as_me:$LINENO: result: $gas_cv_decl_needed_environ" >&5
-echo "${ECHO_T}$gas_cv_decl_needed_environ" >&6
-if test $gas_cv_decl_needed_environ = yes; then
+echo "$as_me:$LINENO: result: $gas_cv_decl_needed_strstr" >&5
+echo "${ECHO_T}$gas_cv_decl_needed_strstr" >&6
+if test $gas_cv_decl_needed_strstr = yes; then
 
 cat >>confdefs.h <<\_ACEOF
-#define NEED_DECLARATION_ENVIRON 1
+#define NEED_DECLARATION_STRSTR 1
 _ACEOF
 
 fi
 
 
-# Does errno.h declare errno, or do we have to add a separate declaration
-# for it?
-
-echo "$as_me:$LINENO: checking whether declaration is required for errno" >&5
-echo $ECHO_N "checking whether declaration is required for errno... $ECHO_C" >&6
-if test "${gas_cv_decl_needed_errno+set}" = set; then
+echo "$as_me:$LINENO: checking whether vsnprintf is declared" >&5
+echo $ECHO_N "checking whether vsnprintf is declared... $ECHO_C" >&6
+if test "${ac_cv_have_decl_vsnprintf+set}" = set; then
   echo $ECHO_N "(cached) $ECHO_C" >&6
 else
   cat >conftest.$ac_ext <<_ACEOF
@@ -10811,67 +11061,74 @@ _ACEOF
 cat confdefs.h >>conftest.$ac_ext
 cat >>conftest.$ac_ext <<_ACEOF
 /* end confdefs.h.  */
-
-#ifdef HAVE_ERRNO_H
-#include <errno.h>
-#endif
-
+$ac_includes_default
 int
 main ()
 {
-
-typedef int f;
-f x;
-x = (f) errno;
+#ifndef vsnprintf
+  char *p = (char *) vsnprintf;
+#endif
 
   ;
   return 0;
 }
 _ACEOF
-rm -f conftest.$ac_objext conftest$ac_exeext
-if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
-  (eval $ac_link) 2>conftest.er1
+rm -f conftest.$ac_objext
+if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
+  (eval $ac_compile) 2>conftest.er1
   ac_status=$?
   grep -v '^ *+' conftest.er1 >conftest.err
   rm -f conftest.er1
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; } &&
-	 { ac_try='test -s conftest$ac_exeext'
+	 { ac_try='test -s conftest.$ac_objext'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); }; }; then
-  gas_cv_decl_needed_errno=no
+  ac_cv_have_decl_vsnprintf=yes
 else
   echo "$as_me: failed program was:" >&5
 sed 's/^/| /' conftest.$ac_ext >&5
 
-gas_cv_decl_needed_errno=yes
+ac_cv_have_decl_vsnprintf=no
 fi
-rm -f conftest.err conftest.$ac_objext \
-      conftest$ac_exeext conftest.$ac_ext
+rm -f conftest.err conftest.$ac_objext conftest.$ac_ext
 fi
-echo "$as_me:$LINENO: result: $gas_cv_decl_needed_errno" >&5
-echo "${ECHO_T}$gas_cv_decl_needed_errno" >&6
-if test $gas_cv_decl_needed_errno = yes; then
+echo "$as_me:$LINENO: result: $ac_cv_have_decl_vsnprintf" >&5
+echo "${ECHO_T}$ac_cv_have_decl_vsnprintf" >&6
+if test $ac_cv_have_decl_vsnprintf = yes; then
 
-cat >>confdefs.h <<\_ACEOF
-#define NEED_DECLARATION_ERRNO 1
+cat >>confdefs.h <<_ACEOF
+#define HAVE_DECL_VSNPRINTF 1
+_ACEOF
+
+
+else
+  cat >>confdefs.h <<_ACEOF
+#define HAVE_DECL_VSNPRINTF 0
 _ACEOF
 
+
 fi
 
 
 
 
+
+
+
+
+
                               ac_config_files="$ac_config_files Makefile doc/Makefile po/Makefile.in:po/Make-in"
 
           ac_config_commands="$ac_config_commands default"
@@ -11560,7 +11817,6 @@ s,@AUTOCONF@,$AUTOCONF,;t t
 s,@AUTOMAKE@,$AUTOMAKE,;t t
 s,@AUTOHEADER@,$AUTOHEADER,;t t
 s,@MAKEINFO@,$MAKEINFO,;t t
-s,@AMTAR@,$AMTAR,;t t
 s,@install_sh@,$install_sh,;t t
 s,@STRIP@,$STRIP,;t t
 s,@ac_ct_STRIP@,$ac_ct_STRIP,;t t
@@ -11569,6 +11825,9 @@ s,@mkdir_p@,$mkdir_p,;t t
 s,@AWK@,$AWK,;t t
 s,@SET_MAKE@,$SET_MAKE,;t t
 s,@am__leading_dot@,$am__leading_dot,;t t
+s,@AMTAR@,$AMTAR,;t t
+s,@am__tar@,$am__tar,;t t
+s,@am__untar@,$am__untar,;t t
 s,@DEPDIR@,$DEPDIR,;t t
 s,@am__include@,$am__include,;t t
 s,@am__quote@,$am__quote,;t t
@@ -11583,6 +11842,7 @@ s,@RANLIB@,$RANLIB,;t t
 s,@ac_ct_RANLIB@,$ac_ct_RANLIB,;t t
 s,@LIBTOOL@,$LIBTOOL,;t t
 s,@WARN_CFLAGS@,$WARN_CFLAGS,;t t
+s,@NO_WERROR@,$NO_WERROR,;t t
 s,@GDBINIT@,$GDBINIT,;t t
 s,@cgen_cpu_prefix@,$cgen_cpu_prefix,;t t
 s,@extra_objects@,$extra_objects,;t t
@@ -11626,6 +11886,9 @@ s,@MAINTAINER_MODE_TRUE@,$MAINTAINER_MODE_TRUE,;t t
 s,@MAINTAINER_MODE_FALSE@,$MAINTAINER_MODE_FALSE,;t t
 s,@MAINT@,$MAINT,;t t
 s,@LIBM@,$LIBM,;t t
+s,@datarootdir@,$datarootdir,;t t
+s,@docdir@,$docdir,;t t
+s,@htmldir@,$htmldir,;t t
 s,@LIBOBJS@,$LIBOBJS,;t t
 s,@LTLIBOBJS@,$LTLIBOBJS,;t t
 CEOF
@@ -11794,6 +12057,11 @@ esac
   *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
   esac
 
+  if test x"$ac_file" != x-; then
+    { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+    rm -f "$ac_file"
+  fi
   # Let's still pretend it is `configure' which instantiates (i.e., don't
   # use $as_me), people would be surprised to read:
   #    /* config.h.  Generated by config.status.  */
@@ -11832,12 +12100,6 @@ echo "$as_me: error: cannot find input file: $f" >&2;}
 	 fi;;
       esac
     done` || { (exit 1); exit 1; }
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF
   sed "$ac_vpsub
@@ -12251,27 +12513,21 @@ echo X"$mf" |
   else
     continue
   fi
-  grep '^DEP_FILES *= *[^ #]' < "$mf" > /dev/null || continue
-  # Extract the definition of DEP_FILES from the Makefile without
-  # running `make'.
+  # Extract the definition of DEPDIR, am__include, and am__quote
+  # from the Makefile without running `make'.
   DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"`
   test -z "$DEPDIR" && continue
+  am__include=`sed -n 's/^am__include = //p' < "$mf"`
+  test -z "am__include" && continue
+  am__quote=`sed -n 's/^am__quote = //p' < "$mf"`
   # When using ansi2knr, U may be empty or an underscore; expand it
   U=`sed -n 's/^U = //p' < "$mf"`
-  test -d "$dirpart/$DEPDIR" || mkdir "$dirpart/$DEPDIR"
-  # We invoke sed twice because it is the simplest approach to
-  # changing $(DEPDIR) to its actual value in the expansion.
-  for file in `sed -n '
-    /^DEP_FILES = .*\\\\$/ {
-      s/^DEP_FILES = //
-      :loop
-	s/\\\\$//
-	p
-	n
-	/\\\\$/ b loop
-      p
-    }
-    /^DEP_FILES = / s/^DEP_FILES = //p' < "$mf" | \
+  # Find all dependency output files, they are included files with
+  # $(DEPDIR) in their names.  We invoke sed twice because it is the
+  # simplest approach to changing $(DEPDIR) to its actual value in the
+  # expansion.
+  for file in `sed -n "
+    s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \
        sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do
     # Make sure the directory exists.
     test -f "$dirpart/$file" && continue
diff --git a/gas/configure.in b/gas/configure.in
index f7d0acbcae71..fe69a51c9259 100644
--- a/gas/configure.in
+++ b/gas/configure.in
@@ -22,16 +22,8 @@ AM_INIT_AUTOMAKE(gas, ${BFD_VERSION})
 
 AM_PROG_LIBTOOL
 
-user_bfd_gas=
-AC_ARG_ENABLE(bfd-assembler,
-[  --enable-bfd-assembler  use BFD back end for writing object files],
-[case "${enableval}" in
-  yes) need_bfd=yes user_bfd_gas=yes ;;
-  no)  user_bfd_gas=no ;;
-  *)   AC_MSG_ERROR(bad value ${enableval} given for bfd-assembler option) ;;
-esac])dnl
 AC_ARG_ENABLE(targets,
-[    targets            alternative target configurations besides the primary],
+[   --enable-targets       alternative target configurations besides the primary],
 [case "${enableval}" in
   yes | "") AC_ERROR(enable-targets option must specify target names or 'all')
 	    ;;
@@ -48,26 +40,7 @@ esac])dnl
 
 using_cgen=no
 
-build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
-AC_ARG_ENABLE(build-warnings,
-[  --enable-build-warnings Enable build-time compiler warnings if gcc is used],
-[case "${enableval}" in
-  yes)	;;
-  no)	build_warnings="-w";;
-  ,*)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${build_warnings} ${t}";;
-  *,)   t=`echo "${enableval}" | sed -e "s/,/ /g"`
-        build_warnings="${t} ${build_warnings}";;
-  *)    build_warnings=`echo "${enableval}" | sed -e "s/,/ /g"`;;
-esac
-if test x"$silent" != x"yes" && test x"$build_warnings" != x""; then
-  echo "Setting warning flags = $build_warnings" 6>&1
-fi])dnl
-WARN_CFLAGS=""
-if test "x${build_warnings}" != x -a "x$GCC" = xyes ; then
-    WARN_CFLAGS="${build_warnings}"
-fi
-AC_SUBST(WARN_CFLAGS)
+AM_BINUTILS_WARNINGS
 
 # Generate a header file
 AM_CONFIG_HEADER(config.h:config.in)
@@ -86,6 +59,9 @@ case "${host}" in
 esac
 AC_SUBST(GDBINIT)
 
+#We need this for the host.  BOUT header is in host order.
+AC_C_BIGENDIAN
+
 te_file=generic
 
 # Makefile target for installing gas in $(tooldir)/bin.
@@ -114,59 +90,14 @@ emulations=""
 
 for this_target in $target $canon_targets ; do
 
-changequote(,)dnl
-    eval `echo $this_target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/cpu=\1 vendor=\2 os=\3/'`
-changequote([,])dnl
+    targ=${this_target}
+    . ${srcdir}/configure.tgt
 
-    # check for architecture variants
-    arch=
-    endian=
-    case ${cpu} in
-      am33_2.0)		cpu_type=mn10300 endian=little ;;
-      alpha*)		cpu_type=alpha ;;
-      arm*b|xscale*b|strongarm*b) cpu_type=arm endian=big ;;
-      arm*|xscale*|strongarm*)    cpu_type=arm endian=little ;;
-      c4x*)		cpu_type=tic4x ;;
-      hppa*)		cpu_type=hppa ;;
-changequote(,)dnl
-      i[3-7]86)		cpu_type=i386 arch=i386;;
-      x86_64)		cpu_type=i386 arch=x86_64;;
-      ia64)		cpu_type=ia64 ;;
-      ip2k)             cpu_type=ip2k endian=big ;; 
-      iq2000)           cpu_type=iq2000 endian=big ;; 
-      m6811|m6812|m68hc12) cpu_type=m68hc11 ;;
-      m680[012346]0)	cpu_type=m68k ;;
-changequote([,])dnl
-      m68008)		cpu_type=m68k ;;
-      m683??)		cpu_type=m68k ;;
-      m5200)		cpu_type=m68k ;;
-      m8*)		cpu_type=m88k ;;
-      mips*el)		cpu_type=mips endian=little ;;
-      mips*)		cpu_type=mips endian=big ;;
-      or32*)		cpu_type=or32 endian=big ;;
-      pjl*)		cpu_type=pj endian=little ;;
-      pj*)		cpu_type=pj endian=big ;;
-      powerpc*le*)	cpu_type=ppc endian=little ;;
-      powerpc*)		cpu_type=ppc endian=big ;;
-      rs6000*)		cpu_type=ppc ;;
-      s390x*)		cpu_type=s390 arch=s390x ;;
-      s390*)		cpu_type=s390 arch=s390 ;;
-      sh5*)		cpu_type=sh64 endian=big ;;
-      sh5le*)		cpu_type=sh64 endian=little ;;
-      sh64*)            cpu_type=sh64 endian=big ;;
-      sh64le*)		cpu_type=sh64 endian=little ;;
-      sh*le)		cpu_type=sh endian=little ;;
-      sh*)		cpu_type=sh endian=big ;;
-      sparclite*)	cpu_type=sparc arch=sparclite ;;
-      sparclet*)	cpu_type=sparc arch=sparclet ;;
-      sparc64*)		cpu_type=sparc arch=v9-64 ;;
-      sparc86x*)	cpu_type=sparc arch=sparc86x  ;;
-      sparc*)		cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
-      v850*)		cpu_type=v850 ;;
-      xtensa*)		cpu_type=xtensa arch=xtensa ;;
-      m32r)             cpu_type=m32r target_cpu=m32r endian=big ;;
-      m32rle)           cpu_type=m32r target_cpu=m32r endian=little ;;
-      *)		cpu_type=${cpu} ;;
+    case ${target_cpu} in
+      crisv32)
+	AC_DEFINE_UNQUOTED(DEFAULT_CRIS_ARCH, $arch,
+			   [Default CRIS architecture.])
+	;;
     esac
 
     if test ${this_target} = $target ; then
@@ -175,354 +106,53 @@ changequote([,])dnl
       continue
     fi
 
-    generic_target=${cpu_type}-$vendor-$os
-    dev=no
-    bfd_gas=no
-    em=generic
-
-    # assign object format
+    generic_target=${cpu_type}-${target_vendor}-${target_os}
     case ${generic_target} in
-      a29k-*-coff)			fmt=coff ;;
-      a29k-amd-udi)			fmt=coff ;;
-      a29k-amd-ebmon)			fmt=coff ;;
-      a29k-nyu-sym1)			fmt=coff ;;
-      a29k-*-rtems*)			fmt=coff ;;
-      a29k-*-vxworks*)			fmt=coff ;;
-
-      alpha*-*-*vms*)			fmt=evax ;;
-      alpha*-*-netware*)		fmt=ecoff ;;
-      alpha*-*-osf*)			fmt=ecoff ;;
-      alpha*-*-linuxecoff*)		fmt=ecoff ;;
-      alpha*-*-linux-gnu*)		fmt=elf em=linux ;;
-      alpha*-*-netbsd*)			fmt=elf em=nbsd ;;
-      alpha*-*-openbsd*)		fmt=elf em=obsd ;;
-
-      # cpu_type for am33_2.0 is set to mn10300
-      mn10300-*-linux*)			fmt=elf bfd_gas=yes em=linux ;;
-
-      arc-*-elf*)			fmt=elf ;;
-
-      arm-*-aout)			fmt=aout ;;
-      arm-*-coff | thumb-*-coff)	fmt=coff ;;
-      arm-*-rtems* | thumb-*-rtems*)	fmt=elf ;;
-      arm-*-elf | thumb-*-elf)		fmt=elf ;;
-      arm-*-kaos*)			fmt=elf ;;
-      arm*-*-conix*)			fmt=elf ;;
-      arm-*-linux*aout*)		fmt=aout em=linux ;;
-      arm*-*-linux-gnu*)		fmt=elf  em=linux ;;
-      arm*-*-uclinux*)			fmt=elf  em=linux ;;
-      arm-*-netbsdelf*)                 fmt=elf  em=nbsd ;;
-      arm-*-*n*bsd*)			fmt=aout em=nbsd ;;
-      arm-**-nto*)			fmt=elf ;;
-      arm-*-oabi | thumb-*-oabi)	fmt=elf ;;
-      arm-epoc-pe | thumb-epoc-pe)	fmt=coff em=epoc-pe ;;
-      arm-wince-pe | arm-*-wince)       fmt=coff em=wince-pe ;;
-      arm-*-pe | thumb-*-pe)		fmt=coff em=pe ;;
-      arm-*-riscix*)			fmt=aout em=riscix ;;
-
-      avr-*-*)				fmt=elf ;;
-
-      cris-*-linux-gnu*)		fmt=multi bfd_gas=yes em=linux ;;
-      cris-*-*)				fmt=multi bfd_gas=yes ;;
-
-      d10v-*-*)				fmt=elf ;;
-      d30v-*-*)				fmt=elf ;;
-      dlx-*-*)				fmt=elf ;;
-
-      fr30-*-*)				fmt=elf ;;
-      frv-*-*linux*)			fmt=elf em=linux;;
-      frv-*-*)				fmt=elf ;;
-
-      hppa-*-linux*)	case ${cpu} in
-			    hppa*64*)	fmt=elf em=hppalinux64;;
-			    hppa*)	fmt=elf em=linux;;
-			esac ;;
-      hppa-*-*elf*)			fmt=elf em=hppa ;;
-      hppa-*-lites*)			fmt=elf em=hppa ;;
-      hppa-*-netbsd*)			fmt=elf em=nbsd ;;
-      hppa-*-openbsd*)			fmt=elf em=hppa ;;
-      hppa-*-osf*)			fmt=som em=hppa ;;
-      hppa-*-rtems*)			fmt=elf em=hppa ;;
-      hppa-*-hpux11*)	case ${cpu} in
-			    hppa*64*)	fmt=elf em=hppa64 ;;
-			    hppa*)	fmt=som em=hppa ;;
-			esac ;;
-      hppa-*-hpux*)			fmt=som em=hppa ;;
-      hppa-*-mpeix*)			fmt=som em=hppa ;;
-      hppa-*-bsd*)			fmt=som em=hppa ;;
-      hppa-*-hiux*)			fmt=som em=hppa ;;
-
-      h8300-*-rtems*)			fmt=coff ;;
-      h8300-*-coff)			fmt=coff ;;
-      h8300-*-elf)			fmt=elf ;;
-      h8500-*-rtems*)			fmt=coff ;;
-      h8500-*-coff)			fmt=coff ;;
-
-      i370-*-elf* | i370-*-linux*)	fmt=elf ;;
-      i386-ibm-aix*)			fmt=coff em=i386aix ;;
-      i386-sequent-bsd*)		fmt=aout em=dynix ;;
-      i386-*-beospe*)			fmt=coff em=pe ;;
-      i386-*-beos*)			fmt=elf ;;
-      i386-*-coff)			fmt=coff ;;
-      i386-*-elf)			fmt=elf ;;
-      i386-*-kaos*)			fmt=elf ;;
-      i386-*-bsd*)			fmt=aout em=386bsd ;;
-      i386-*-netbsd0.8)			fmt=aout em=386bsd ;;
-      i386-*-netbsdpe*)			fmt=coff em=pe ;;
-      i386-*-netbsd*-gnu* | \
-      i386-*-knetbsd*-gnu | \
-      i386-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      i386-*-*n*bsd*)	case ${cpu} in
-			    x86_64)	fmt=elf em=nbsd ;;
-			    *)		fmt=aout em=nbsd ;;
-			esac ;;
-      i386-*-linux*aout*)		fmt=aout em=linux ;;
-      i386-*-linux*oldld)		fmt=aout em=linux ;;
-      i386-*-linux*coff*)		fmt=coff em=linux ;;
-      i386-*-linux-gnu*)		fmt=elf em=linux ;;
-      x86_64-*-linux-gnu*)		fmt=elf em=linux ;;
-      i386-*-lynxos*)			fmt=coff em=lynx ;;
-changequote(,)dnl
-      i386-*-sysv[45]*)			fmt=elf ;;
-      i386-*-solaris*)			fmt=elf ;;
-      i386-*-freebsdaout*)		fmt=aout em=386bsd ;;
-      i386-*-freebsd[12].*)		fmt=aout em=386bsd ;;
-      i386-*-freebsd[12])		fmt=aout em=386bsd ;;
-changequote([,])dnl
-      i386-*-freebsd* | i386-*-kfreebsd*-gnu)
-					fmt=elf em=freebsd ;;
-      i386-*-sysv*)			fmt=coff ;;
-      i386-*-sco3.2v5*coff)		fmt=coff ;;
-      i386-*-isc*)			fmt=coff ;;
-      i386-*-sco3.2v5*)			fmt=elf
-	  if test ${this_target} = $target; then
-	    AC_DEFINE(SCO_ELF, 1, [Define if defaulting to ELF on SCO 5.])
-	  fi ;;
-      i386-*-sco3.2*)			fmt=coff ;;
-      i386-*-vsta)			fmt=aout ;;
+      i386-*-sco3.2v5*)
+	if test ${this_target} = $target; then
+	  AC_DEFINE(SCO_ELF, 1, [Define if defaulting to ELF on SCO 5.])
+	fi
+	;;
+
       i386-*-msdosdjgpp* \
       | i386-*-go32* \
-      | i386-go32-rtems*)		fmt=coff em=go32
-	    AC_DEFINE(STRICTCOFF, 1, [Using strict COFF?]) ;;
-      i386-*-rtemself*)			fmt=elf ;;
-      i386-*-rtemscoff*)		fmt=coff ;;
-      i386-*-rtems*)			fmt=elf ;;
-      i386-*-gnu*)			fmt=elf ;;
-      i386-*-mach*)			fmt=aout em=mach ;;
-      i386-*-msdos*)			fmt=aout ;;
-      i386-*-moss*)			fmt=elf ;;
-      i386-*-pe)			fmt=coff em=pe ;;
-      i386-*-cygwin*)			fmt=coff em=pe ;;
-      i386-*-interix*)			fmt=coff em=interix ;;
-      i386-*-mingw32*)			fmt=coff em=pe ;;
-      i386-*-nto-qnx*)			fmt=elf ;;
-      i386-*-*nt*)			fmt=coff em=pe ;;
-      i386-*-chaos)			fmt=elf ;;
-
-      i860-*-*)				fmt=elf endian=little
-		AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress) ;;
-      i960-*-bout)			fmt=bout ;;
-      i960-*-coff)			fmt=coff em=ic960 ;;
-      i960-*-rtems*)			fmt=coff em=ic960 ;;
-      i960-*-nindy*)			fmt=bout ;;
-      i960-*-vxworks5.0)		fmt=bout ;;
-      i960-*-vxworks5.*)		fmt=coff em=ic960 ;;
-      i960-*-vxworks*)			fmt=bout ;;
-      i960-*-elf*)			fmt=elf ;;
-
-      ia64-*-elf*)			fmt=elf ;;
-      ia64-*-aix*)			fmt=elf em=ia64aix ;;
-      ia64-*-linux-gnu*)		fmt=elf em=linux ;;
-      ia64-*-hpux*)			fmt=elf em=hpux ;;
-      ia64-*-netbsd*)			fmt=elf em=nbsd ;;
-
-      ip2k-*-*)				fmt=elf ;;
-
-      iq2000-*-elf)         		fmt=elf bfd_gas=yes ;;
-
-      m32r-*-elf*)			fmt=elf ;;
-      m32r-*-linux*)			fmt=elf em=linux;;
-
-      m68hc11-*-* | m6811-*-*)		fmt=elf ;;
-      m68hc12-*-* | m6812-*-*)		fmt=elf ;;
-
-      m68k-*-vxworks*)			fmt=aout em=sun3 ;;
-      m68k-ericsson-ose)		fmt=aout em=sun3 ;;
-      m68k-*-sunos*)			fmt=aout em=sun3 ;;
-      m68k-motorola-sysv*)		fmt=coff em=delta ;;
-      m68k-bull-sysv3*)			fmt=coff em=dpx2 ;;
-      m68k-apollo-*)			fmt=coff em=apollo ;;
-      m68k-*-elf*)			fmt=elf ;;
-      m68k-*-sysv4*)			fmt=elf em=svr4 ;;
-      m68k-*-sysv*)			fmt=coff ;;
-      m68k-*-coff | m68k-*-rtemscoff*)	fmt=coff ;;
-      m68k-*-rtems*)			fmt=elf ;;
-      m68k-*-hpux*)			fmt=hp300 em=hp300 ;;
-      m68k-*-linux*aout*)		fmt=aout em=linux ;;
-      m68k-*-linux-gnu*)		fmt=elf em=linux ;;
-      m68k-*-uclinux*)			fmt=elf ;;
-      m68k-*-gnu*)			fmt=elf ;;
-      m68k-*-lynxos*)			fmt=coff em=lynx ;;
-      m68k-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      m68k-*-netbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
-      m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
-      m68k-apple-aux*)			fmt=coff em=aux ;;
-      m68k-*-psos*)			fmt=elf em=psos;;
-
-      m88k-motorola-sysv3*)		fmt=coff em=delt88 ;;
-      m88k-*-coff*)			fmt=coff ;;
-
-      mcore-*-elf)			fmt=elf ;;
-      mcore-*-pe)			fmt=coff em=pe bfd_gas=yes ;;
-
-      # don't change em like *-*-bsd does
-      mips-dec-openbsd*)		fmt=elf endian=little ;;
-      mips-sony-bsd*)			fmt=ecoff ;;
+      | i386-go32-rtems*)
+	AC_DEFINE(STRICTCOFF, 1, [Using strict COFF?])
+	;;
+
+      i860-*-*)
+	AC_MSG_WARN(GAS support for ${generic_target} is preliminary and a work in progress)
+	;;
+
+      mips-sony-bsd*)
+	;;
       mips-*-bsd*)
-	    AC_MSG_ERROR(Unknown vendor for mips-bsd configuration.) ;;
-      mips-*-ultrix*)			fmt=ecoff endian=little ;;
-      mips-*-osf*)			fmt=ecoff endian=little ;;
-      mips-*-ecoff*)			fmt=ecoff ;;
-      mips-*-pe*)			fmt=coff endian=little em=pe ;;
-      mips-*-irix6*)			fmt=elf em=irix ;;
-      mips-*-irix5*)			fmt=elf em=irix ;;
-      mips-*-irix*)			fmt=ecoff em=irix ;;
-      mips-*-lnews*)			fmt=ecoff em=lnews ;;
-      mips-*-riscos*)			fmt=ecoff ;;
-      mips*-*-linux*)			fmt=elf em=tmips ;;
-      mips-*-sysv4*MP* | mips-*-gnu*)	fmt=elf em=tmips ;;
-      mips-*-sysv*)			fmt=ecoff ;;
-      mips-*-elf* | mips-*-rtems*)	fmt=elf ;;
-      mips-*-netbsd*)			fmt=elf ;;
-      mips-*-openbsd*)			fmt=elf ;;
-
-      mmix-*-*)				fmt=elf ;;
-      mn10200-*-*)			fmt=elf ;;
-      mn10300-*-*)			fmt=elf ;;
-      msp430-*-*)			fmt=elf ;;
-      openrisc-*-*)			fmt=elf ;;
-      or32-*-rtems*)			fmt=elf ;;
-      or32-*-coff)			fmt=coff ;;
-      or32-*-elf)			fmt=elf ;;
-      pj*)				fmt=elf ;;
-
-      ppc-*-pe | ppc-*-cygwin*)		fmt=coff em=pe ;;
-      ppc-*-winnt*)			fmt=coff em=pe ;;
-changequote(,)dnl
-      ppc-*-aix5.[01])			fmt=coff em=aix5 ;;
-changequote([,])dnl
-      ppc-*-aix5.*)			fmt=coff em=aix5
-      	AC_DEFINE(AIX_WEAK_SUPPORT, 1,
+	AC_MSG_ERROR(Unknown vendor for mips-bsd configuration.)
+	;;
+
+      ppc-*-aix5.*)
+	AC_DEFINE(AIX_WEAK_SUPPORT, 1,
 		  [Define if using AIX 5.2 value for C_WEAKEXT.])
-      ;;
-      ppc-*-aix*)			fmt=coff ;;
-      ppc-*-beos*)			fmt=coff ;;
-      ppc-*-*n*bsd* | ppc-*-elf*)	fmt=elf ;;
-      ppc-*-eabi* | ppc-*-sysv4*)	fmt=elf ;;
-      ppc-*-linux-gnu*)			fmt=elf em=linux
-	    case "$endian" in
-		big)  ;;
-		*)    AC_MSG_ERROR(GNU/Linux must be configured big endian) ;;
-	    esac ;;
-      ppc-*-solaris*)			fmt=elf
-	    if test ${this_target} = $target; then
-		AC_DEFINE(TARGET_SOLARIS_COMMENT, 1,
-			  [Define if default target is PowerPC Solaris.])
-	    fi
-	    if test x${endian} = xbig; then
-		AC_MSG_ERROR(Solaris must be configured little endian)
-	    fi ;;
-      ppc-*-rtems*)			fmt=elf ;;
-      ppc-*-macos* | ppc-*-mpw*)	fmt=coff em=macos ;;
-      ppc-*-netware*)			fmt=elf em=ppcnw ;;
-      ppc-**-nto*)			fmt=elf ;;
-      ppc-*-kaos*)			fmt=elf ;;
-
-      s390x-*-linux-gnu*)		fmt=elf em=linux ;;
-      s390-*-linux-gnu*)		fmt=elf em=linux ;;
-
-      sh*-*-linux*)			fmt=elf em=linux
-	    case ${cpu} in
-		sh*eb)	endian=big ;;
-		*)	endian=little ;;
-	    esac ;;
-      sh5*-*-netbsd*)			fmt=elf em=nbsd ;;
-      sh64*-*-netbsd*)			fmt=elf em=nbsd ;;
-      sh*-*-netbsdelf*)			fmt=elf em=nbsd ;;
-      sh-*-elf*)			fmt=elf ;;
-      sh-*-coff*)			fmt=coff ;;
-      sh-*-nto*)			fmt=elf ;;
-      sh-*-pe*)				fmt=coff em=pe bfd_gas=yes endian=little ;;
-      sh-*-rtemscoff*)			fmt=coff ;;
-      sh-*-rtems*)			fmt=elf ;;
-      sh-*-kaos*)			fmt=elf ;;
-      shle*-*-kaos*)			fmt=elf ;;
-      sh64-*-elf*)			fmt=elf ;;
-
-      ns32k-pc532-mach*)		fmt=aout em=pc532mach ;;
-      ns32k-pc532-ux*)			fmt=aout em=pc532mach ;;
-      ns32k-pc532-lites*)		fmt=aout em=nbsd532 ;;
-      ns32k-*-*n*bsd*)			fmt=aout em=nbsd532 ;;
-
-      sparc-*-rtemsaout*)		fmt=aout ;;
-      sparc-*-rtemself*)		fmt=elf ;;
-      sparc-*-rtems*)			fmt=elf ;;
-      sparc-*-sunos4*)			fmt=aout em=sun3 ;;
-      sparc-*-aout | sparc*-*-vxworks*)	fmt=aout em=sparcaout ;;
-      sparc-*-coff)			fmt=coff ;;
-      sparc-*-linux*aout*)		fmt=aout em=linux ;;
-      sparc-*-linux-gnu*)		fmt=elf em=linux ;;
-      sparc-*-lynxos*)			fmt=coff em=lynx ;;
-      sparc-fujitsu-none)		fmt=aout ;;
-      sparc-*-elf)			fmt=elf ;;
-      sparc-*-sysv4*)			fmt=elf ;;
-      sparc-*-solaris*)			fmt=elf ;;
-      sparc-*-netbsdelf*)		fmt=elf em=nbsd ;;
-      sparc-*-*n*bsd*)	case ${cpu} in
-			    sparc64)	fmt=elf em=nbsd ;;
-			    *)		fmt=aout em=nbsd ;;
-			esac ;;
-      strongarm-*-coff)			fmt=coff ;;
-      strongarm-*-elf)			fmt=elf ;;
-      strongarm-*-kaos*)		fmt=elf ;;
-      xscale-*-coff)			fmt=coff ;;
-      xscale-*-elf)			fmt=elf ;;
-
-      tic30-*-*aout*)			fmt=aout bfd_gas=yes ;;
-      tic30-*-*coff*)			fmt=coff bfd_gas=yes ;;
-      tic4x-*-* | c4x-*-*)              fmt=coff bfd_gas=yes ;;
-      tic54x-*-* | c54x*-*-*)		fmt=coff bfd_gas=yes need_libm=yes;;
-      tic80-*-*)			fmt=coff ;;
-
-      v850-*-*)				fmt=elf ;;
-      v850e-*-*)			fmt=elf ;;
-      v850ea-*-*)			fmt=elf ;;
-
-      vax-*-netbsdelf*)			fmt=elf em=nbsd ;;
-      vax-*-netbsd*)			fmt=aout em=nbsd ;;
-      vax-*-bsd* | vax-*-ultrix*)	fmt=aout ;;
-      vax-*-linux-gnu*)			fmt=elf em=linux bfd_gas=yes ;;
-      vax-*-vms)			fmt=vms ;;
-
-      w65-*-*)				fmt=coff ;;
-
-      xstormy16-*-*)			fmt=elf ;;
-
-      xtensa-*-*)			fmt=elf ;;
-
-      z8k-*-coff | z8k-*-sim)		fmt=coff ;;
-
-      *-*-aout | *-*-scout)		fmt=aout ;;
-      *-*-freebsd* | *-*-kfreebsd*-gnu)	fmt=elf em=freebsd ;;
-      *-*-nindy*)			fmt=bout ;;
-      *-*-bsd*)				fmt=aout em=sun3 ;;
-      *-*-generic)			fmt=generic ;;
-      *-*-xray | *-*-hms)		fmt=coff ;;
-      *-*-sim)				fmt=coff ;;
-      *-*-elf | *-*-sysv4* | *-*-solaris*) fmt=elf dev=yes ;;
-      *-*-aros*)			fmt=elf em=linux bfd_gas=yes ;;
-      *-*-vxworks | *-*-windiss)	fmt=elf ;;
-      *-*-netware)			fmt=elf ;;
+	;;
+      ppc-*-linux-*)
+	case "$endian" in
+	  big)  ;;
+	  *)    AC_MSG_ERROR(GNU/Linux must be configured big endian) ;;
+	esac
+	;;
+      ppc-*-solaris*)
+	if test ${this_target} = $target; then
+	  AC_DEFINE(TARGET_SOLARIS_COMMENT, 1,
+		    [Define if default target is PowerPC Solaris.])
+	fi
+	if test x${endian} = xbig; then
+	  AC_MSG_ERROR(Solaris must be configured little endian)
+	fi
+	;;
+
+      sh*-*-symbianelf*)
+	AC_DEFINE(TARGET_SYMBIAN, 1, [Define if target is Symbian OS.])
+	;;
     esac
 
     if test ${this_target} = $target ; then
@@ -538,13 +168,6 @@ changequote([,])dnl
       fi
     fi
 
-    case ${cpu_type}-${fmt} in
-	alpha*-* | arm-* | i386-* | ia64*-* | mips-* | ns32k-* \
-		| pdp11-* | ppc-* | sparc-* | strongarm-* | xscale-* \
-		| *-elf | *-ecoff | *-som)
-	    bfd_gas=yes ;;
-    esac
-
 # Other random stuff.
 
     case ${cpu_type} in
@@ -615,6 +238,9 @@ changequote([,])dnl
 	  mips*-linux*)
 	    mips_default_abi=O32_ABI
 	    ;;
+	  mips64*-openbsd*)
+	    mips_default_abi=N64_ABI
+	    ;;
 	  *)
 	    mips_default_abi=NO_ABI
 	    ;;
@@ -643,19 +269,31 @@ changequote([,])dnl
 	*opcodes*) shared_opcodes=true ;;
 	*) shared_opcodes=false ;;
 	esac
-	if test "${shared_opcodes}" = "true"; then
-	  # A shared libopcodes must be linked against libbfd.
-	  need_bfd=yes
-	fi
 	;;
     esac
 
     # Any other special object files needed ?
     case ${cpu_type} in
+
+      bfin)
+        echo ${extra_objects} | grep -s "bfin-parse.o"
+        if test $? -ne 0 ; then
+          extra_objects="$extra_objects bfin-parse.o"
+        fi
+
+        echo ${extra_objects} | grep -s "bfin-lex.o"
+        if test $? -ne 0 ; then
+          extra_objects="$extra_objects bfin-lex.o"
+        fi
+        ;;
+
       fr30 | ip2k | iq2000 | m32r | openrisc)
 	using_cgen=yes
 	;;
 
+      m32c)
+	using_cgen=yes
+	;;
       frv)
 	using_cgen=yes
 	;;
@@ -683,6 +321,10 @@ changequote([,])dnl
 	fi
 	;;
 
+      mt)
+        using_cgen=yes
+	;;
+
       i386 | s390 | sparc)
 	if test $this_target = $target ; then
 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
@@ -693,6 +335,10 @@ changequote([,])dnl
 	using_cgen=yes
 	;;
 
+      xc16x)
+	using_cgen=yes
+	;;
+
       xtensa)
 	echo ${extra_objects} | grep -s "xtensa-relax.o"
 	if test $? -ne 0 ; then
@@ -714,17 +360,8 @@ changequote([,])dnl
 # See if we really can support this configuration with the emulation code.
 
     if test $this_target = $target ; then
-      primary_bfd_gas=$bfd_gas
       obj_format=$fmt
       te_file=$em
-
-      if test $bfd_gas = no ; then
-	# Can't support other configurations this way.
-	break
-      fi
-    elif test $bfd_gas = no ; then
-      # Can't support this configuration.
-      break
     fi
 
 # From target name and format, produce a list of supported emulations.
@@ -818,27 +455,6 @@ if test ! -r ${srcdir}/config/obj-${obj_format}.c; then
   AC_MSG_ERROR(GAS does not have support for object file format ${obj_format})
 fi
 
-case ${user_bfd_gas}-${primary_bfd_gas} in
-  yes-yes | no-no)
-    # We didn't override user's choice.
-    ;;
-  no-yes)
-    AC_MSG_WARN(Use of BFD is required for ${target}; overriding config options.)
-    ;;
-  no-preferred)
-    primary_bfd_gas=no
-    ;;
-  *-preferred)
-    primary_bfd_gas=yes
-    ;;
-  yes-*)
-    primary_bfd_gas=yes
-    ;;
-  -*)
-    # User specified nothing.
-    ;;
-esac
-
 # Some COFF configurations want these random other flags set.
 case ${obj_format} in
   coff)
@@ -851,8 +467,8 @@ case ${obj_format} in
 esac
 
 # Getting this done right is going to be a bitch.  Each configuration specified
-# with --enable-targets=... should be checked for environment, format, cpu, and
-# bfd_gas setting.
+# with --enable-targets=... should be checked for environment, format, cpu
+# setting.
 #
 # For each configuration, the necessary object file support code must be linked
 # in.  This might be only one, it might be up to four.  The necessary emulation
@@ -895,10 +511,8 @@ if test `set . $formats ; shift ; echo $#` -gt 1 ; then
       ecoff)	AC_DEFINE(OBJ_MAYBE_ECOFF, 1,   [ECOFF support?])   ;;
       elf)	AC_DEFINE(OBJ_MAYBE_ELF, 1,     [ELF support?])     ;;
       generic)	AC_DEFINE(OBJ_MAYBE_GENERIC, 1, [generic support?]) ;;
-      hp300)	AC_DEFINE(OBJ_MAYBE_HP300, 1,   [HP300 support?])   ;;
       ieee)	AC_DEFINE(OBJ_MAYBE_IEEE, 1,    [IEEE support?])    ;;
       som)	AC_DEFINE(OBJ_MAYBE_SOM, 1,     [SOM support?])     ;;
-      vms)	AC_DEFINE(OBJ_MAYBE_VMS, 1,     [VMS support?])     ;;
     esac
     extra_objects="$extra_objects obj-$fmt.o"
   done
@@ -920,12 +534,6 @@ AC_DEFINE_UNQUOTED(EMULATIONS, $EMULATIONS, [Supported emulations.])
 AC_DEFINE_UNQUOTED(DEFAULT_EMULATION, "$DEFAULT_EMULATION",
 		   [Default emulation.])
 
-case ${primary_bfd_gas}-${target_cpu_type}-${obj_format} in
-  yes-*-coff)	need_bfd=yes ;;
-  no-*-coff)	need_bfd=yes
-		AC_DEFINE(MANY_SEGMENTS, 1, [old COFF support?]) ;;
-esac
-
 reject_dev_configs=yes
 
 case ${reject_dev_configs}-${dev} in
@@ -941,11 +549,6 @@ AC_SUBST(install_tooldir)
 AC_SUBST(atof)
 dnl AC_SUBST(emulation)
 
-case "${primary_bfd_gas}" in
-  yes)	AC_DEFINE(BFD_ASSEMBLER, 1, [Use BFD interface?])
-	need_bfd=yes ;;
-esac
-
 # do we need the opcodes library?
 case "${need_opcodes}" in
 yes)
@@ -953,13 +556,9 @@ yes)
   ;;
 esac
 
-case "${need_bfd}" in
-yes)
-  BFDLIB=../bfd/libbfd.la
-  BFDVER_H=../bfd/bfdver.h
-  ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
-  ;;
-esac
+BFDLIB=../bfd/libbfd.la
+BFDVER_H=../bfd/bfdver.h
+ALL_OBJ_DEPS="$ALL_OBJ_DEPS"' ../bfd/bfd.h $(INCDIR)/symcat.h'
 
 AC_SUBST(BFDLIB)
 AC_SUBST(OPCODES_LIB)
@@ -978,7 +577,7 @@ AC_PROG_CC
 AC_PROG_YACC
 AM_PROG_LEX
 
-ALL_LINGUAS="fr tr es"
+ALL_LINGUAS="fr tr es rw"
 CY_GNU_GETTEXT
 
 AM_MAINTAINER_MODE
@@ -1042,11 +641,6 @@ gas_test_headers="
 #include <unistd.h>
 #endif
 "
-GAS_CHECK_DECL_NEEDED(strstr, f, char *(*f)(), $gas_test_headers)
-GAS_CHECK_DECL_NEEDED(malloc, f, char *(*f)(), $gas_test_headers)
-GAS_CHECK_DECL_NEEDED(free, f, void (*f)(), $gas_test_headers)
-GAS_CHECK_DECL_NEEDED(sbrk, f, char *(*f)(), $gas_test_headers)
-GAS_CHECK_DECL_NEEDED(environ, f, char **f, $gas_test_headers)
 
 # Does errno.h declare errno, or do we have to add a separate declaration
 # for it?
@@ -1056,6 +650,30 @@ GAS_CHECK_DECL_NEEDED(errno, f, int f, [
 #endif
 ])
 
+AC_MSG_CHECKING(for a known getopt prototype in unistd.h)
+AC_CACHE_VAL(gas_cv_decl_getopt_unistd_h,
+[AC_TRY_COMPILE([#include <unistd.h>], [extern int getopt (int, char *const*, const char *);],
+gas_cv_decl_getopt_unistd_h=yes, gas_cv_decl_getopt_unistd_h=no)])
+AC_MSG_RESULT($gas_cv_decl_getopt_unistd_h)
+if test $gas_cv_decl_getopt_unistd_h = yes; then
+  AC_DEFINE([HAVE_DECL_GETOPT], 1,
+	    [Is the prototype for getopt in <unistd.h> in the expected format?])
+fi
+
+GAS_CHECK_DECL_NEEDED(environ, f, char **f, $gas_test_headers)
+GAS_CHECK_DECL_NEEDED(ffs, f, int (*f)(int), $gas_test_headers)
+GAS_CHECK_DECL_NEEDED(free, f, void (*f)(), $gas_test_headers)
+GAS_CHECK_DECL_NEEDED(malloc, f, char *(*f)(), $gas_test_headers)
+GAS_CHECK_DECL_NEEDED(sbrk, f, char *(*f)(), $gas_test_headers)
+GAS_CHECK_DECL_NEEDED(strstr, f, char *(*f)(), $gas_test_headers)
+
+AC_CHECK_DECLS([vsnprintf])
+
+dnl Required for html and install-html targets.
+AC_SUBST(datarootdir)
+AC_SUBST(docdir)
+AC_SUBST(htmldir)
+
 dnl This must come last.
 
 dnl We used to make symlinks to files in the source directory, but now
diff --git a/gas/configure.tgt b/gas/configure.tgt
new file mode 100644
index 000000000000..696daaa128fb
--- /dev/null
+++ b/gas/configure.tgt
@@ -0,0 +1,409 @@
+# gas target specific configuration file.  This is a -*- sh -*- file.
+
+# This is invoked by configure.  Putting it in a separate shell file
+# lets us skip running autoconf when modifying target specific
+# information.
+
+# Input shell variables:
+#   targ	a configuration target name, such as i686-pc-linux-gnu.
+
+# Output shell variables:
+#   cpu_type	canonical gas cpu type; identifies the config/tc-* files
+#   fmt		output format; identifies the config/obj-* files
+#   em		emulation; identifies the config/te-* files
+
+# Optional output shell variables; these are not always set:
+#   arch	the default architecture; sets DEFAULT_ARCH on some systems 
+#   endian	"big" or "little"; used on bi-endian systems
+
+cpu_type=
+fmt=
+em=generic
+bfd_gas=no
+arch=
+endian=
+
+eval `echo $targ | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/cpu=\1 vendor=\2 os=\3/'`
+
+# Check for architecture variants.  Set cpu_type and, optionally,
+# endian and arch.
+# Note: This table is alpha-sorted, please try to keep it that way.
+case ${cpu} in
+  alpha*)		cpu_type=alpha ;;
+  am33_2.0)		cpu_type=mn10300 endian=little ;;
+  arm*be|arm*b)		cpu_type=arm endian=big ;;
+  arm*)			cpu_type=arm endian=little ;;
+  bfin*)		cpu_type=bfin endian=little ;;
+  c4x*)			cpu_type=tic4x ;;
+  crisv32)		cpu_type=cris arch=crisv32 ;;
+  crx*)			cpu_type=crx endian=little ;;
+  hppa*)		cpu_type=hppa ;;
+  i[3-7]86)		cpu_type=i386 arch=i386;;
+  ia64)			cpu_type=ia64 ;;
+  ip2k)			cpu_type=ip2k endian=big ;; 
+  iq2000)		cpu_type=iq2000 endian=big ;; 
+  m32c)			cpu_type=m32c endian=big ;;
+  m32r)			cpu_type=m32r endian=big ;;
+  m32rle)		cpu_type=m32r endian=little ;;
+  m5200)		cpu_type=m68k ;;
+  m68008)		cpu_type=m68k ;;
+  m680[012346]0)	cpu_type=m68k ;;
+  m6811|m6812|m68hc12)	cpu_type=m68hc11 ;;
+  m683??)		cpu_type=m68k ;;
+  maxq)			cpu_type=maxq ;;
+  mips*el)		cpu_type=mips endian=little ;;
+  mips*)		cpu_type=mips endian=big ;;
+  mt)                   cpu_type=mt endian=big ;;
+  or32*)		cpu_type=or32 endian=big ;;
+  pjl*)			cpu_type=pj endian=little ;;
+  pj*)			cpu_type=pj endian=big ;;
+  powerpc*le*)		cpu_type=ppc endian=little ;;
+  powerpc*)		cpu_type=ppc endian=big ;;
+  rs6000*)		cpu_type=ppc ;;
+  s390x*)		cpu_type=s390 arch=s390x ;;
+  s390*)		cpu_type=s390 arch=s390 ;;
+  sh5le*)		cpu_type=sh64 endian=little ;;
+  sh5*)			cpu_type=sh64 endian=big ;;
+  sh64le*)		cpu_type=sh64 endian=little ;;
+  sh64*)            	cpu_type=sh64 endian=big ;;
+  sh*le)		cpu_type=sh endian=little ;;
+  sh*)			cpu_type=sh endian=big ;;
+  sparc64*)		cpu_type=sparc arch=v9-64 ;;
+  sparc86x*)		cpu_type=sparc arch=sparc86x  ;;
+  sparclet*)		cpu_type=sparc arch=sparclet ;;
+  sparclite*)		cpu_type=sparc arch=sparclite ;;
+  sparc*)		cpu_type=sparc arch=sparclite ;; # ??? See tc-sparc.c.
+  strongarm*be)		cpu_type=arm endian=big ;;
+  strongarm*b)		cpu_type=arm endian=big ;;
+  strongarm*)		cpu_type=arm endian=little ;;
+  v850*)		cpu_type=v850 ;;
+  x86_64)		cpu_type=i386 arch=x86_64;;
+  xscale*be|xscale*b)	cpu_type=arm endian=big ;;
+  xscale*)		cpu_type=arm endian=little ;;
+  xtensa*)		cpu_type=xtensa arch=xtensa ;;
+  *)			cpu_type=${cpu} ;;
+esac
+
+
+# Assign object format.  Set fmt, em, and bfd_gas.
+generic_target=${cpu_type}-$vendor-$os
+# Note: This table is alpha-sorted, please try to keep it that way.
+case ${generic_target} in
+  alpha-*-*vms*)			fmt=evax ;;
+  alpha-*-osf*)				fmt=ecoff ;;
+  alpha-*-linuxecoff*)			fmt=ecoff ;;
+  alpha-*-linux-*)			fmt=elf em=linux ;;
+  alpha-*-netbsd*)			fmt=elf em=nbsd ;;
+  alpha-*-openbsd*)			fmt=elf em=obsd ;;
+
+  arc-*-elf*)				fmt=elf ;;
+
+  arm-*-aout)				fmt=aout ;;
+  arm-*-coff | thumb-*-coff)		fmt=coff ;;
+  arm-*-rtems* | thumb-*-rtems*)	fmt=elf ;;
+  arm-*-elf | thumb-*-elf)		fmt=elf ;;
+  arm-*-eabi*)				fmt=elf em=armeabi ;;
+  arm-*-symbianelf*)			fmt=elf em=symbian ;;
+  arm-*-kaos*)				fmt=elf ;;
+  arm-*-conix*)				fmt=elf ;;
+  arm-*-linux*aout*)			fmt=aout em=linux ;;
+  arm-*-linux-*eabi*)			fmt=elf  em=armlinuxeabi ;;
+  arm-*-linux-*)			fmt=elf  em=linux ;;
+  arm-*-uclinux*)			fmt=elf  em=linux ;;
+  arm-*-netbsdelf*)                 	fmt=elf  em=nbsd ;;
+  arm-*-*n*bsd*)			fmt=aout em=nbsd ;;
+  arm-*-nto*)				fmt=elf ;;
+  arm-epoc-pe | thumb-epoc-pe)		fmt=coff em=epoc-pe ;;
+  arm-wince-pe | arm-*-wince)		fmt=coff em=wince-pe ;;
+  arm-*-pe | thumb-*-pe)		fmt=coff em=pe ;;
+  arm-*-riscix*)			fmt=aout em=riscix ;;
+
+  avr-*-*)				fmt=elf bfd_gas=yes ;;
+  bfin-*-*)				fmt=elf bfd_gas=yes ;;
+  bfin-*elf)				fmt=elf ;;
+
+  cris-*-linux-* | crisv32-*-linux-*)
+					fmt=multi em=linux ;;
+  cris-*-* | crisv32-*-*)		fmt=multi ;;
+
+  crx-*-elf*)	    			fmt=elf ;;
+
+  d10v-*-*)				fmt=elf ;;
+  d30v-*-*)				fmt=elf ;;
+  dlx-*-*)				fmt=elf ;;
+
+  fr30-*-*)				fmt=elf ;;
+  frv-*-*linux*)			fmt=elf em=linux;;
+  frv-*-*)				fmt=elf ;;
+
+  hppa-*-linux*)
+    case ${cpu} in
+      hppa*64*)				fmt=elf em=hppalinux64 ;;
+      hppa*)				fmt=elf em=linux ;;
+    esac ;;
+  hppa-*-*elf*)				fmt=elf em=hppa ;;
+  hppa-*-lites*)			fmt=elf em=hppa ;;
+  hppa-*-netbsd*)			fmt=elf em=nbsd ;;
+  hppa-*-openbsd*)			fmt=elf em=hppa ;;
+  hppa-*-osf*)				fmt=som em=hppa ;;
+  hppa-*-hpux11*)
+    case ${cpu} in
+      hppa*64*)				fmt=elf em=hppa64 ;;
+      hppa*)				fmt=som em=hppa ;;
+    esac ;;
+  hppa-*-hpux*)				fmt=som em=hppa ;;
+  hppa-*-mpeix*)			fmt=som em=hppa ;;
+  hppa-*-bsd*)				fmt=som em=hppa ;;
+  hppa-*-hiux*)				fmt=som em=hppa ;;
+
+  h8300-*-elf | h8300-*-rtems*)		fmt=elf ;;
+
+  i370-*-elf* | i370-*-linux*)		fmt=elf ;;
+
+  i386-ibm-aix*)			fmt=coff em=i386aix ;;
+  i386-sequent-bsd*)			fmt=aout em=dynix ;;
+  i386-*-beospe*)			fmt=coff em=pe ;;
+  i386-*-beos*)				fmt=elf ;;
+  i386-*-coff)				fmt=coff ;;
+  i386-*-elf)				fmt=elf ;;
+  i386-*-kaos*)				fmt=elf ;;
+  i386-*-bsd*)				fmt=aout em=386bsd ;;
+  i386-*-netbsd0.8)			fmt=aout em=386bsd ;;
+  i386-*-netbsdpe*)			fmt=coff em=pe ;;
+  i386-*-netbsd*-gnu* | \
+  i386-*-knetbsd*-gnu | \
+  i386-*-netbsdelf*)			fmt=elf em=nbsd ;;
+  i386-*-netbsd*)
+    case ${cpu} in
+      x86_64)				fmt=elf em=nbsd ;;
+      *)				fmt=aout em=nbsd ;;
+    esac ;;
+  i386-*-openbsd[0-2].* | \
+  i386-*-openbsd3.[0-2])		fmt=aout em=nbsd ;;
+  i386-*-openbsd*)			fmt=elf em=nbsd ;;
+  i386-*-linux*aout*)			fmt=aout em=linux ;;
+  i386-*-linux*oldld)			fmt=aout em=linux ;;
+  i386-*-linux*coff*)			fmt=coff em=linux ;;
+  i386-*-linux-*)			fmt=elf em=linux ;;
+  i386-*-lynxos*)			fmt=elf em=lynx ;;
+  i386-*-sysv[45]*)			fmt=elf ;;
+  i386-*-solaris*)			fmt=elf ;;
+  i386-*-freebsdaout*)			fmt=aout em=386bsd ;;
+  i386-*-freebsd[12].*)			fmt=aout em=386bsd ;;
+  i386-*-freebsd[12])			fmt=aout em=386bsd ;;
+  i386-*-freebsd* | i386-*-kfreebsd*-gnu)
+				    	fmt=elf em=freebsd ;;
+  i386-*-sysv*)				fmt=coff ;;
+  i386-*-sco3.2v5*coff)			fmt=coff ;;
+  i386-*-isc*)				fmt=coff ;;
+  i386-*-sco3.2v5*)			fmt=elf ;;
+  i386-*-sco3.2*)			fmt=coff ;;
+  i386-*-vsta)				fmt=aout ;;
+  i386-*-msdosdjgpp* \
+  | i386-*-go32*)			fmt=coff em=go32 ;;
+  i386-*-rtems*)			fmt=elf ;;
+  i386-*-gnu*)				fmt=elf em=gnu ;;
+  i386-*-mach*)				fmt=aout em=mach ;;
+  i386-*-msdos*)			fmt=aout ;;
+  i386-*-moss*)				fmt=elf ;;
+  i386-*-pe)				fmt=coff em=pe ;;
+  i386-*-cygwin*)			fmt=coff em=pe ;;
+  i386-*-interix*)			fmt=coff em=interix ;;
+  i386-*-mingw32*)			fmt=coff em=pe ;;
+  i386-*-nto-qnx*)			fmt=elf ;;
+  i386-*-*nt*)				fmt=coff em=pe ;;
+  i386-*-chaos)				fmt=elf ;;
+  i386-*-rdos*)				fmt=elf ;;
+
+  i860-*-*)				fmt=elf endian=little ;;
+
+  i960-*-elf*)				fmt=elf ;;
+
+  ia64-*-elf*)				fmt=elf ;;
+  ia64-*-aix*)				fmt=elf em=ia64aix ;;
+  ia64-*-linux-*)			fmt=elf em=linux ;;
+  ia64-*-hpux*)				fmt=elf em=hpux ;;
+  ia64-*-netbsd*)			fmt=elf em=nbsd ;;
+
+  ip2k-*-*)				fmt=elf ;;
+
+  iq2000-*-elf)         		fmt=elf ;;
+
+  m32c-*-elf)         			fmt=elf ;;
+
+  m32r-*-elf*)				fmt=elf ;;
+  m32r-*-linux*)			fmt=elf em=linux;;
+
+  m68hc11-*-* | m6811-*-*)		fmt=elf ;;
+  m68hc12-*-* | m6812-*-*)		fmt=elf ;;
+
+  m68k-*-elf*)				fmt=elf ;;
+  m68k-*-sysv4*)			fmt=elf em=svr4 ;;
+  m68k-*-rtems*)			fmt=elf ;;
+  m68k-*-linux-*)			fmt=elf em=linux ;;
+  m68k-*-uclinux*)			fmt=elf ;;
+  m68k-*-gnu*)				fmt=elf ;;
+  m68k-*-netbsdelf*)			fmt=elf em=nbsd ;;
+  m68k-*-netbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
+  m68k-*-openbsd*)			fmt=aout em=nbsd bfd_gas=yes ;;
+  m68k-*-psos*)				fmt=elf em=psos;;
+
+  maxq-*-coff)      			fmt=coff bfd_gas=yes ;;
+
+  mcore-*-elf)				fmt=elf ;;
+  mcore-*-pe)				fmt=coff em=pe bfd_gas=yes ;;
+
+  # don't change em like *-*-bsd does
+  mips-sony-bsd*)			fmt=ecoff ;;
+  mips-*-ultrix*)			fmt=ecoff endian=little ;;
+  mips-*-osf*)				fmt=ecoff endian=little ;;
+  mips-*-ecoff*)			fmt=ecoff ;;
+  mips-*-pe*)				fmt=coff endian=little em=pe ;;
+  mips-*-irix6*)			fmt=elf em=irix ;;
+  mips-*-irix5*)			fmt=elf em=irix ;;
+  mips-*-irix*)				fmt=ecoff em=irix ;;
+  mips-*-lnews*)			fmt=ecoff em=lnews ;;
+  mips-*-riscos*)			fmt=ecoff ;;
+  mips*-*-linux*)			fmt=elf em=tmips ;;
+  mips-*-sysv4*MP* | mips-*-gnu*)	fmt=elf em=tmips ;;
+  mips-*-sysv*)				fmt=ecoff ;;
+  mips-*-elf* | mips-*-rtems*)		fmt=elf ;;
+  mips-*-netbsd*)			fmt=elf em=tmips ;;
+  mips-*-openbsd*)			fmt=elf em=tmips ;;
+
+  mmix-*-*)				fmt=elf ;;
+
+  mn10200-*-*)				fmt=elf ;;
+
+  # cpu_type for am33_2.0 is set to mn10300
+  mn10300-*-linux*)			fmt=elf em=linux ;;
+  mn10300-*-*)				fmt=elf ;;
+
+  mt-*-elf)				fmt=elf bfd_gas=yes ;;
+
+  msp430-*-*)				fmt=elf ;;
+
+  ns32k-pc532-mach*)			fmt=aout em=pc532mach ;;
+  ns32k-pc532-ux*)			fmt=aout em=pc532mach ;;
+  ns32k-pc532-lites*)			fmt=aout em=nbsd532 ;;
+  ns32k-*-*n*bsd*)			fmt=aout em=nbsd532 ;;
+
+  openrisc-*-*)				fmt=elf ;;
+
+  or32-*-rtems*)			fmt=elf ;;
+  or32-*-elf)				fmt=elf ;;
+
+  pj*)					fmt=elf ;;
+
+  ppc-*-pe | ppc-*-cygwin*)		fmt=coff em=pe ;;
+  ppc-*-winnt*)				fmt=coff em=pe ;;
+  ppc-*-aix5.[01])			fmt=coff em=aix5 ;;
+  ppc-*-aix5.*)				fmt=coff em=aix5 ;;
+  ppc-*-aix*)				fmt=coff ;;
+  ppc-*-beos*)				fmt=coff ;;
+  ppc-*-*n*bsd* | ppc-*-elf*)		fmt=elf ;;
+  ppc-*-eabi* | ppc-*-sysv4*)		fmt=elf ;;
+  ppc-*-linux-*)			fmt=elf em=linux ;;
+  ppc-*-solaris*)			fmt=elf ;;
+  ppc-*-rtems*)				fmt=elf ;;
+  ppc-*-macos*)				fmt=coff em=macos ;;
+  ppc-*-nto*)				fmt=elf ;;
+  ppc-*-kaos*)				fmt=elf ;;
+  ppc-*-lynxos*)			fmt=elf em=lynx ;;
+
+  s390-*-linux-*)			fmt=elf em=linux ;;
+  s390-*-tpf*)				fmt=elf ;;
+
+  sh*-*-linux*)				fmt=elf em=linux
+    case ${cpu} in
+      sh*eb)	endian=big ;;
+      *)	endian=little ;;
+    esac ;;
+  sh5*-*-netbsd*)			fmt=elf em=nbsd ;;
+  sh64*-*-netbsd*)			fmt=elf em=nbsd ;;
+  sh*-*-netbsdelf*)			fmt=elf em=nbsd ;;
+  sh*-*-symbianelf*)			fmt=elf endian=little ;;
+  sh-*-elf*)				fmt=elf ;;
+  sh-*-coff*)				fmt=coff ;;
+  sh-*-nto*)				fmt=elf ;;
+  sh-*-pe*)				fmt=coff em=pe bfd_gas=yes endian=little ;;
+  sh-*-rtemscoff*)			fmt=coff ;;
+  sh-*-rtems*)				fmt=elf ;;
+  sh-*-kaos*)				fmt=elf ;;
+  shle*-*-kaos*)			fmt=elf ;;
+  sh64-*-elf*)				fmt=elf ;;
+
+  sparc-*-rtems*)			fmt=elf ;;
+  sparc-*-sunos4*)			fmt=aout em=sun3 ;;
+  sparc-*-aout)				fmt=aout em=sparcaout ;;
+  sparc-*-coff)				fmt=coff ;;
+  sparc-*-linux*aout*)			fmt=aout em=linux ;;
+  sparc-*-linux-*)			fmt=elf em=linux ;;
+  sparc-fujitsu-none)			fmt=aout ;;
+  sparc-*-elf)				fmt=elf ;;
+  sparc-*-sysv4*)			fmt=elf ;;
+  sparc-*-solaris*)			fmt=elf ;;
+  sparc-*-netbsdelf*)			fmt=elf em=nbsd ;;
+  sparc-*-netbsd*)
+    case ${cpu} in
+      sparc64)				fmt=elf em=nbsd ;;
+      *)				fmt=aout em=nbsd ;;
+    esac ;;
+  sparc-*-openbsd[0-2].* | \
+  sparc-*-openbsd3.[0-1])
+    case ${cpu} in
+      sparc64)				fmt=elf em=nbsd ;;
+      *)				fmt=aout em=nbsd ;;
+    esac ;;
+  sparc-*-openbsd*)			fmt=elf em=nbsd ;;
+
+  tic30-*-*aout*)			fmt=aout bfd_gas=yes ;;
+  tic30-*-*coff*)			fmt=coff bfd_gas=yes ;;
+  tic4x-*-* | c4x-*-*)			fmt=coff bfd_gas=yes ;;
+  tic54x-*-* | c54x*-*-*)		fmt=coff bfd_gas=yes need_libm=yes;;
+
+  v850-*-*)				fmt=elf ;;
+  v850e-*-*)				fmt=elf ;;
+  v850ea-*-*)				fmt=elf ;;
+
+  vax-*-netbsdelf*)			fmt=elf em=nbsd ;;
+  vax-*-linux-*)			fmt=elf em=linux ;;
+
+  xscale-*-coff)			fmt=coff ;;
+  xscale-*-elf)				fmt=elf ;;
+
+  xstormy16-*-*)			fmt=elf ;;
+
+  xtensa-*-*)				fmt=elf ;;
+
+  z80-*-coff)				fmt=coff ;;
+
+  z8k-*-coff | z8k-*-sim)		fmt=coff ;;
+
+  *-*-aout | *-*-scout)			fmt=aout ;;
+  *-*-freebsd* | *-*-kfreebsd*-gnu)	fmt=elf em=freebsd ;;
+  *-*-bsd*)				fmt=aout em=sun3 ;;
+  *-*-generic)				fmt=generic ;;
+  *-*-xray | *-*-hms)			fmt=coff ;;
+  *-*-sim)				fmt=coff ;;
+  *-*-elf | *-*-sysv4* | *-*-solaris*)	fmt=elf ;;
+  *-*-aros*)				fmt=elf em=linux ;;
+  *-*-vxworks* | *-*-windiss)		fmt=elf em=vxworks ;;
+  *-*-netware)				fmt=elf em=netware ;;
+esac
+
+case ${cpu_type} in
+  alpha | arm | i386 | ia64 | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k)
+    bfd_gas=yes
+    ;;
+esac
+case ${fmt} in
+  elf | ecoff | multi | som)
+    bfd_gas=yes
+    ;;
+esac
+
+if test $bfd_gas != yes; then
+  echo This target is no longer supported in gas
+  exit 1
+fi
diff --git a/gas/debug.c b/gas/debug.c
index 7d1038736d95..fe2ed8c6536f 100644
--- a/gas/debug.c
+++ b/gas/debug.c
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* Routines for debug use only.  */
 
diff --git a/gas/dep-in.sed b/gas/dep-in.sed
index 2e2717ccc675..f23c2018fe97 100644
--- a/gas/dep-in.sed
+++ b/gas/dep-in.sed
@@ -3,6 +3,7 @@
 /\\$/b loop
 
 s! \.\./! !g
+s! \./! !g
 s!@INCDIR@!$(INCDIR)!g
 s!@TOPDIR@/include!$(INCDIR)!g
 s!@BFDDIR@!$(BFDDIR)!g
diff --git a/gas/depend.c b/gas/depend.c
index 127c819180d7..4a264aa7038c 100644
--- a/gas/depend.c
+++ b/gas/depend.c
@@ -1,5 +1,5 @@
 /* depend.c - Handle dependency tracking.
-   Copyright 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am
index 7f0f805fbc58..d48a9ccb2412 100644
--- a/gas/doc/Makefile.am
+++ b/gas/doc/Makefile.am
@@ -8,7 +8,7 @@ CONFIG=all
 # Options to extract the man page from as.texinfo
 MANCONF = -Dman
 
-TEXI2POD = perl $(top_srcdir)/../etc/texi2pod.pl
+TEXI2POD = perl $(BASEDIR)/etc/texi2pod.pl $(AM_MAKEINFOFLAGS)
 
 POD2MAN = pod2man --center="GNU Development Tools" \
 	--release="binutils-$(VERSION)" --section=1
@@ -17,33 +17,35 @@ man_MANS = as.1
 
 info_TEXINFOS = as.texinfo 
 
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+
 asconfig.texi: $(CONFIG).texi
 	rm -f asconfig.texi
-	ln -s $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
-	  || ln $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
-	  || cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
+	cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
+	chmod u+w ./asconfig.texi
 
 CPU_DOCS = \
-	c-a29k.texi \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-bfin.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
-	c-h8500.texi \
 	c-hppa.texi \
 	c-i370.texi \
 	c-i386.texi \
 	c-i860.texi \
 	c-i960.texi \
 	c-ip2k.texi \
+	c-m32c.texi \
 	c-m32r.texi \
 	c-m68hc11.texi \
 	c-m68k.texi \
-	c-m88k.texi \
 	c-mips.texi \
 	c-mmix.texi \
+	c-mt.texi \
 	c-msp430.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
@@ -56,26 +58,46 @@ CPU_DOCS = \
 	c-vax.texi \
 	c-v850.texi \
 	c-xtensa.texi \
+	c-z80.texi \
 	c-z8k.texi
 
-gasver.texi: Makefile
+gasver.texi: $(srcdir)/../../bfd/configure
 	rm -f $@
-	echo '@set VERSION $(VERSION)' > $@
+	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
+	  echo "@set VERSION $$VERSION" > $@
 
-as.info: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-as.dvi: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
 
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
 
+html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
+
+install-html: install-html-am
+
+install-html-am: $(HTMLS)
+	@$(NORMAL_INSTALL)
+	test -z "$(htmldir)" || $(mkdir_p) "$(DESTDIR)$(htmldir)"
+	@list='$(HTMLS)'; for p in $$list; do \
+	  if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \
+	  f=$(html__strip_dir) \
+	  if test -d "$$d$$p"; then \
+	    echo " $(mkdir_p) '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(mkdir_p) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \
+	    echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \
+	  else \
+	    echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \
+	  fi; \
+	done
+
 # This one isn't ready for prime time yet.  Not even a little bit.
 
 noinst_TEXINFOS = internals.texi
 
-DISTCLEANFILES = asconfig.texi
-
-MAINTAINERCLEANFILES = gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi gasver.texi
 
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
@@ -85,7 +107,7 @@ CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
 # Maintenance
 
 # We need it for the taz target in ../../Makefile.in.
-info: $(MANS)
+info-local: $(MANS)
 
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in
index 0c6a1b0ab986..cd9dad2baaf8 100644
--- a/gas/doc/Makefile.in
+++ b/gas/doc/Makefile.in
@@ -1,8 +1,8 @@
-# Makefile.in generated by automake 1.8.4 from Makefile.am.
+# Makefile.in generated by automake 1.9.6 from Makefile.am.
 # @configure_input@
 
 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-# 2003, 2004  Free Software Foundation, Inc.
+# 2003, 2004, 2005  Free Software Foundation, Inc.
 # This Makefile.in is free software; the Free Software Foundation
 # gives unlimited permission to copy and/or distribute it,
 # with or without modifications, as long as this notice is preserved.
@@ -40,8 +40,8 @@ subdir = doc
 DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am
 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
 am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
-	$(top_srcdir)/../libtool.m4 $(top_srcdir)/../gettext.m4 \
-	$(top_srcdir)/configure.in
+	$(top_srcdir)/../bfd/warning.m4 $(top_srcdir)/../libtool.m4 \
+	$(top_srcdir)/../gettext.m4 $(top_srcdir)/configure.in
 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
 	$(ACLOCAL_M4)
 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
@@ -50,7 +50,6 @@ CONFIG_CLEAN_FILES =
 depcomp =
 am__depfiles_maybe =
 SOURCES =
-DIST_SOURCES =
 INFO_DEPS = $(srcdir)/as.info
 TEXINFO_TEX = $(top_srcdir)/../texinfo/texinfo.tex
 am__TEXINFO_TEX_DIR = $(top_srcdir)/../texinfo
@@ -59,11 +58,6 @@ PDFS = as.pdf
 PSS = as.ps
 HTMLS = as.html
 TEXINFOS = as.texinfo
-TEXI2DVI = `if test -f $(top_srcdir)/../texinfo/util/texi2dvi; then \
-             echo $(top_srcdir)/../texinfo/util/texi2dvi; \
-           else \
-             echo texi2dvi; \
-           fi`
 TEXI2PDF = $(TEXI2DVI) --pdf --batch
 MAKEINFOHTML = $(MAKEINFO) --html
 AM_MAKEINFOHTMLFLAGS = $(AM_MAKEINFOFLAGS)
@@ -130,6 +124,7 @@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@
 MAKEINFO = @MAKEINFO@
 MKINSTALLDIRS = @MKINSTALLDIRS@
 MSGFMT = @MSGFMT@
+NO_WERROR = @NO_WERROR@
 OBJEXT = @OBJEXT@
 OPCODES_LIB = @OPCODES_LIB@
 PACKAGE = @PACKAGE@
@@ -159,6 +154,8 @@ am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
 am__include = @am__include@
 am__leading_dot = @am__leading_dot@
 am__quote = @am__quote@
+am__tar = @am__tar@
+am__untar = @am__untar@
 atof = @atof@
 bindir = @bindir@
 build = @build@
@@ -168,6 +165,8 @@ build_os = @build_os@
 build_vendor = @build_vendor@
 cgen_cpu_prefix = @cgen_cpu_prefix@
 datadir = @datadir@
+datarootdir = @datarootdir@
+docdir = @docdir@
 exec_prefix = @exec_prefix@
 extra_objects = @extra_objects@
 host = @host@
@@ -175,6 +174,7 @@ host_alias = @host_alias@
 host_cpu = @host_cpu@
 host_os = @host_os@
 host_vendor = @host_vendor@
+htmldir = @htmldir@
 includedir = @includedir@
 infodir = @infodir@
 install_sh = @install_sh@
@@ -206,33 +206,35 @@ CONFIG = all
 
 # Options to extract the man page from as.texinfo
 MANCONF = -Dman
-TEXI2POD = perl $(top_srcdir)/../etc/texi2pod.pl
+TEXI2POD = perl $(BASEDIR)/etc/texi2pod.pl $(AM_MAKEINFOFLAGS)
 POD2MAN = pod2man --center="GNU Development Tools" \
 	--release="binutils-$(VERSION)" --section=1
 
 man_MANS = as.1
 info_TEXINFOS = as.texinfo 
+AM_MAKEINFOFLAGS = -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
+TEXI2DVI = texi2dvi -I "$(srcdir)" -I "$(top_srcdir)/../libiberty"
 CPU_DOCS = \
-	c-a29k.texi \
 	c-alpha.texi \
 	c-arc.texi \
 	c-arm.texi \
+	c-bfin.texi \
 	c-d10v.texi \
 	c-cris.texi \
 	c-h8300.texi \
-	c-h8500.texi \
 	c-hppa.texi \
 	c-i370.texi \
 	c-i386.texi \
 	c-i860.texi \
 	c-i960.texi \
 	c-ip2k.texi \
+	c-m32c.texi \
 	c-m32r.texi \
 	c-m68hc11.texi \
 	c-m68k.texi \
-	c-m88k.texi \
 	c-mips.texi \
 	c-mmix.texi \
+	c-mt.texi \
 	c-msp430.texi \
 	c-ns32k.texi \
 	c-pdp11.texi \
@@ -245,13 +247,14 @@ CPU_DOCS = \
 	c-vax.texi \
 	c-v850.texi \
 	c-xtensa.texi \
+	c-z80.texi \
 	c-z8k.texi
 
+html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
 
 # This one isn't ready for prime time yet.  Not even a little bit.
 noinst_TEXINFOS = internals.texi
-DISTCLEANFILES = asconfig.texi
-MAINTAINERCLEANFILES = gasver.texi
+MAINTAINERCLEANFILES = asconfig.texi gasver.texi
 BASEDIR = $(srcdir)/../..
 BFDDIR = $(BASEDIR)/bfd
 CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in
@@ -299,16 +302,14 @@ distclean-libtool:
 	-rm -f libtool
 
 .texinfo.info:
-	restore=: && \
-	backupdir="$(am__leading_dot)am$$$$" && \
+	restore=: && backupdir="$(am__leading_dot)am$$$$" && \
 	am__cwd=`pwd` && cd $(srcdir) && \
 	rm -rf $$backupdir && mkdir $$backupdir && \
-	for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \
-	  if test -f $$f; then \
-	    mv $$f $$backupdir; \
-	    restore=mv; \
-	  fi; \
-	done; \
+	if ($(MAKEINFO) --version) >/dev/null 2>&1; then \
+	  for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \
+	    if test -f $$f; then mv $$f $$backupdir; restore=mv; else :; fi; \
+	  done; \
+	else :; fi && \
 	cd "$$am__cwd"; \
 	if $(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
 	 -o $@ $<; \
@@ -320,8 +321,7 @@ distclean-libtool:
 	  cd $(srcdir) && \
 	  $$restore $$backupdir/* `echo "./$@" | sed 's|[^/]*$$||'`; \
 	fi; \
-	rm -rf $$backupdir; \
-	exit $$rc
+	rm -rf $$backupdir; exit $$rc
 
 .texinfo.dvi:
 	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
@@ -334,18 +334,28 @@ distclean-libtool:
 	$(TEXI2PDF) $<
 
 .texinfo.html:
-	$(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
-	 -o $@ $<
-	if test ! -d $@ && test -d $(@:.html=); then \
-	  mv $(@:.html=) $@; else :; fi
+	rm -rf $(@:.html=.htp)
+	if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \
+	 -o $(@:.html=.htp) $<; \
+	then \
+	  rm -rf $@; \
+	  if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \
+	    mv $(@:.html=) $@; else mv $(@:.html=.htp) $@; fi; \
+	else \
+	  if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \
+	    rm -rf $(@:.html=); else rm -Rf $(@:.html=.htp) $@; fi; \
+	  exit 1; \
+	fi
 $(srcdir)/as.info: as.texinfo 
+as.dvi: as.texinfo 
 as.pdf: as.texinfo 
 as.html: as.texinfo 
 .dvi.ps:
+	TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \
 	$(DVIPS) -o $@ $<
 
 uninstall-info-am:
-	$(PRE_UNINSTALL)
+	@$(PRE_UNINSTALL)
 	@if (install-info --version && \
 	     install-info --version 2>&1 | sed 1q | grep -i -v debian) >/dev/null 2>&1; then \
 	  list='$(INFO_DEPS)'; \
@@ -361,7 +371,7 @@ uninstall-info-am:
 	  relfile=`echo "$$file" | sed 's|^.*/||'`; \
 	  relfile_i=`echo "$$relfile" | sed 's|\.info$$||;s|$$|.i|'`; \
 	  (if cd "$(DESTDIR)$(infodir)"; then \
-	     echo " rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9])"; \
+	     echo " cd '$(DESTDIR)$(infodir)' && rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9]"; \
 	     rm -f $$relfile $$relfile-[0-9] $$relfile-[0-9][0-9] $$relfile_i[0-9] $$relfile_i[0-9][0-9]; \
 	   else :; fi); \
 	done
@@ -470,8 +480,7 @@ mostlyclean-generic:
 clean-generic:
 
 distclean-generic:
-	-rm -f $(CONFIG_CLEAN_FILES)
-	-test -z "$(DISTCLEANFILES)" || rm -f $(DISTCLEANFILES)
+	-test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
 
 maintainer-clean-generic:
 	@echo "This command is intended for maintainers to use"
@@ -493,7 +502,9 @@ html: html-am
 
 html-am: $(HTMLS)
 
-info-am: $(INFO_DEPS)
+info: info-am
+
+info-am: $(INFO_DEPS) info-local
 
 install-data-am: install-data-local install-man
 
@@ -559,11 +570,11 @@ uninstall-man: uninstall-man1
 
 .PHONY: all all-am check check-am clean clean-generic clean-info \
 	clean-libtool dist-info distclean distclean-generic \
-	distclean-libtool dvi dvi-am html html-am info info-am install \
-	install-am install-data install-data-am install-data-local \
-	install-exec install-exec-am install-info install-info-am \
-	install-man install-man1 install-strip installcheck \
-	installcheck-am installdirs maintainer-clean \
+	distclean-libtool dvi dvi-am html html-am info info-am \
+	info-local install install-am install-data install-data-am \
+	install-data-local install-exec install-exec-am install-info \
+	install-info-am install-man install-man1 install-strip \
+	installcheck installcheck-am installdirs maintainer-clean \
 	maintainer-clean-aminfo maintainer-clean-generic mostlyclean \
 	mostlyclean-aminfo mostlyclean-generic mostlyclean-libtool pdf \
 	pdf-am ps ps-am uninstall uninstall-am uninstall-info-am \
@@ -572,25 +583,43 @@ uninstall-man: uninstall-man1
 
 asconfig.texi: $(CONFIG).texi
 	rm -f asconfig.texi
-	ln -s $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
-	  || ln $(srcdir)/$(CONFIG).texi ./asconfig.texi >/dev/null 2>&1 \
-	  || cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
+	cp $(srcdir)/$(CONFIG).texi ./asconfig.texi
+	chmod u+w ./asconfig.texi
 
-gasver.texi: Makefile
+gasver.texi: $(srcdir)/../../bfd/configure
 	rm -f $@
-	echo '@set VERSION $(VERSION)' > $@
+	eval `grep '^ *VERSION=' $(srcdir)/../../bfd/configure`; \
+	  echo "@set VERSION $$VERSION" > $@
 
-as.info: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
-as.dvi: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
+$(srcdir)/as.info as.dvi as.html: $(srcdir)/as.texinfo asconfig.texi gasver.texi $(CPU_DOCS)
 
 # We want install to imply install-info as per GNU standards, despite the
 # cygnus option.
 install-data-local: install-info
 
+install-html: install-html-am
+
+install-html-am: $(HTMLS)
+	@$(NORMAL_INSTALL)
+	test -z "$(htmldir)" || $(mkdir_p) "$(DESTDIR)$(htmldir)"
+	@list='$(HTMLS)'; for p in $$list; do \
+	  if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \
+	  f=$(html__strip_dir) \
+	  if test -d "$$d$$p"; then \
+	    echo " $(mkdir_p) '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(mkdir_p) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \
+	    echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \
+	  else \
+	    echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \
+	    $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \
+	  fi; \
+	done
+
 # Maintenance
 
 # We need it for the taz target in ../../Makefile.in.
-info: $(MANS)
+info-local: $(MANS)
 
 # Build the man page from the texinfo file
 # The sed command removes the no-adjust Nroff command so that
diff --git a/gas/doc/all.texi b/gas/doc/all.texi
index 4e302cea1f6c..5192f5471c97 100644
--- a/gas/doc/all.texi
+++ b/gas/doc/all.texi
@@ -1,4 +1,5 @@
-@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002
+@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
+@c 2003, 2005
 @c Free Software Foundation, Inc.
 @c This file is part of the documentation for the GAS manual
 
@@ -19,35 +20,36 @@
 @c Object formats of interest
 @c ==========================
 @set AOUT
-@set BOUT
 @set COFF
 @set ELF
 @set SOM
 
 @c CPUs of interest
 @c ================
-@set A29K
 @set ALPHA
 @set ARC
 @set ARM
+@set BFIN
 @set CRIS
 @set D10V
 @set D30V
 @set H8/300
-@set H8/500
 @set HPPA
 @set I370
 @set I80386
 @set I860
 @set I960
+@set IA64
 @set IP2K
+@set M32C
 @set M32R
+@set xc16x
 @set M68HC11
 @set M680X0
-@set M880X0
 @set MCORE
 @set MIPS
 @set MMIX
+@set MS1
 @set MSP430
 @set PDP11
 @set PJ
@@ -57,8 +59,8 @@
 @set TIC54X
 @set V850
 @set VAX
-@set VXWORKS
 @set XTENSA
+@set Z80
 @set Z8000
 
 @c Does this version of the assembler use the difference-table kluge?
diff --git a/gas/doc/as.1 b/gas/doc/as.1
index e16cbe920aa2..89e3b4c2c7c8 100644
--- a/gas/doc/as.1
+++ b/gas/doc/as.1
@@ -1,4 +1,4 @@
-.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14
+.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32
 .\"
 .\" Standard preamble:
 .\" ========================================================================
@@ -25,11 +25,11 @@
 ..
 .\" Set up some character translations and predefined strings.  \*(-- will
 .\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
-.\" double quote, and \*(R" will give a right double quote.  | will give a
-.\" real vertical bar.  \*(C+ will give a nicer C++.  Capital omega is used to
-.\" do unbreakable dashes and therefore won't be available.  \*(C` and \*(C'
-.\" expand to `' in nroff, nothing in troff, for use with C<>.
-.tr \(*W-|\(bv\*(Tr
+.\" double quote, and \*(R" will give a right double quote.  \*(C+ will
+.\" give a nicer C++.  Capital omega is used to do unbreakable dashes and
+.\" therefore won't be available.  \*(C` and \*(C' expand to `' in nroff,
+.\" nothing in troff, for use with C<>.
+.tr \(*W-
 .ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
 .ie n \{\
 .    ds -- \(*W-
@@ -128,19 +128,21 @@
 .\" ========================================================================
 .\"
 .IX Title "AS 1"
-.TH AS 1 "2004-05-17" "binutils-2.15" "GNU Development Tools"
+.TH AS 1 "2006-06-23" "binutils-2.17" "GNU Development Tools"
 .SH "NAME"
 AS \- the portable GNU assembler.
 .SH "SYNOPSIS"
 .IX Header "SYNOPSIS"
-as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR]
- [\fB\-f\fR] [\fB\-\-gstabs\fR] [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf2\fR] [\fB\-\-help\fR]
- [\fB\-I\fR \fIdir\fR] [\fB\-J\fR] [\fB\-K\fR] [\fB\-L\fR]
- [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR]
- [\fB\-\-keep\-locals\fR] [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-statistics\fR] [\fB\-v\fR]
- [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] 
- [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB\-\-target\-help\fR] [\fItarget-options\fR] 
+as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
+ [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
+ [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
+ [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
+ [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
+ [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR
+ \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]
+ [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]
+ [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
+ [\fB\-\-target\-help\fR] [\fItarget-options\fR]
  [\fB\-\-\fR|\fIfiles\fR ...]
 .PP
 \&\fITarget Alpha options:\fR
@@ -158,16 +160,18 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f
    [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
    [\fB\-mfpu\fR=\fIfloating-point-format\fR]
    [\fB\-mfloat\-abi\fR=\fIabi\fR]
+   [\fB\-meabi\fR=\fIver\fR]
    [\fB\-mthumb\fR]
    [\fB\-EB\fR|\fB\-EL\fR]
    [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
     \fB\-mapcs\-reentrant\fR]
-   [\fB\-mthumb\-interwork\fR] [\fB\-moabi\fR] [\fB\-k\fR]
+   [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
 .PP
 \&\fITarget \s-1CRIS\s0 options:\fR
    [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
    [\fB\-\-pic\fR] [\fB\-N\fR]
    [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
+   [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
 .PP
 \&\fITarget D10V options:\fR
    [\fB\-O\fR]
@@ -183,9 +187,21 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f
     \fB\-AKC\fR|\fB\-AMC\fR]
    [\fB\-b\fR] [\fB\-no\-relax\fR]
 .PP
+\&\fITarget \s-1IA\-64\s0 options:\fR
+   [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
+   [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
+   [\fB\-mle\fR|\fBmbe\fR]
+   [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
+   [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
+   [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
+   [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
+.PP
 \&\fITarget \s-1IP2K\s0 options:\fR
    [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
 .PP
+\&\fITarget M32C options:\fR
+   [\fB\-m32c\fR|\fB\-m16c\fR]
+.PP
 \&\fITarget M32R options:\fR
    [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
    \fB\-\-W[n]p\fR]
@@ -208,7 +224,7 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f
 \&\fITarget \s-1MIPS\s0 options:\fR
    [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
    [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
-   [\fB\-non_shared\fR] [\fB\-xgot\fR] [\fB\-\-membedded\-pic\fR]
+   [\fB\-non_shared\fR] [\fB\-xgot\fR]
    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
    [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
    [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
@@ -219,6 +235,8 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f
    [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
    [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
    [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
+   [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
+   [\fB\-mmt\fR] [\fB\-mno\-mt\fR]
    [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
    [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
 .PP
@@ -256,10 +274,20 @@ as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-D\fR] [\fB\-\-defsym\fR \fIsym\f
  [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] 
  [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
 .PP
+\&\fITarget Z80 options:\fR
+  [\fB\-z80\fR] [\fB\-r800\fR]
+  [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]
+  [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]
+  [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]
+  [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]
+  [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]
+  [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]
+.PP
 \&\fITarget Xtensa options:\fR
- [\fB\-\-[no\-]density\fR] [\fB\-\-[no\-]relax\fR] [\fB\-\-[no\-]generics\fR]
- [\fB\-\-[no\-]text\-section\-literals\fR]
+ [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]
  [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
+ [\fB\-\-[no\-]transform\fR]
+ [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
 .SH "DESCRIPTION"
 .IX Header "DESCRIPTION"
 \&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
@@ -311,7 +339,7 @@ The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
 by commas.  For example:
 .PP
 .Vb 1
-\&        gcc -c -g -O -Wa,-alh,-L file.c
+\&        gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
 .Ve
 .PP
 This passes two options to the assembler: \fB\-alh\fR (emit a listing to
@@ -325,6 +353,19 @@ precisely what options it passes to each compilation pass, including the
 assembler.)
 .SH "OPTIONS"
 .IX Header "OPTIONS"
+.IP "\fB@\fR\fIfile\fR" 4
+.IX Item "@file"
+Read command-line options from \fIfile\fR.  The options read are
+inserted in place of the original @\fIfile\fR option.  If \fIfile\fR
+does not exist, or cannot be read, then the option will be treated
+literally, and not removed.  
+.Sp
+Options in \fIfile\fR are separated by whitespace.  A whitespace
+character may be included in an option by surrounding the entire
+option in either single or double quotes.  Any character (including a
+backslash) may be included by prefixing the character to be included
+with a backslash.  The \fIfile\fR may itself contain additional
+@\fIfile\fR options; any such options will be processed recursively.
 .IP "\fB\-a[cdhlmns]\fR" 4
 .IX Item "-a[cdhlmns]"
 Turn on listings, in any of a variety of ways:
@@ -360,6 +401,9 @@ You may combine these options; for example, use \fB\-aln\fR for assembly
 listing without forms processing.  The \fB=file\fR option, if used, must be
 the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
 .RE
+.IP "\fB\-\-alternate\fR" 4
+.IX Item "--alternate"
+Begin in alternate macro mode, see \fBAltmacro,,\f(CB\*(C`.altmacro\*(C'\fB\fR.
 .IP "\fB\-D\fR" 4
 .IX Item "-D"
 Ignored.  This option is accepted for script compatibility with calls to
@@ -371,8 +415,17 @@ Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
 indicates a hexadecimal value, and a leading \fB0\fR indicates an octal value.
 .IP "\fB\-f\fR" 4
 .IX Item "-f"
-``fast''\-\-\-skip whitespace and comment preprocessing (assume source is
+\&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
 compiler output).
+.IP "\fB\-g\fR" 4
+.IX Item "-g"
+.PD 0
+.IP "\fB\-\-gen\-debug\fR" 4
+.IX Item "--gen-debug"
+.PD
+Generate debugging information for each assembler source line using whichever
+debug format is preferred by the target.  This currently means either \s-1STABS\s0,
+\&\s-1ECOFF\s0 or \s-1DWARF2\s0.
 .IP "\fB\-\-gstabs\fR" 4
 .IX Item "--gstabs"
 Generate stabs debugging information for each assembler line.  This
@@ -384,8 +437,8 @@ extensions that probably only gdb can handle, and that could make other
 debuggers crash or refuse to read your program.  This
 may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is
 the location of the current working directory at assembling time.
-.IP "\fB\-\-gdwarf2\fR" 4
-.IX Item "--gdwarf2"
+.IP "\fB\-\-gdwarf\-2\fR" 4
+.IX Item "--gdwarf-2"
 Generate \s-1DWARF2\s0 debugging information for each assembler line.  This
 may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this
 option is only supported by some targets, not all of them.
@@ -435,6 +488,17 @@ Name the object-file output from \fBas\fR \fIobjfile\fR.
 .IP "\fB\-R\fR" 4
 .IX Item "-R"
 Fold the data section into the text section.
+.Sp
+Set the default size of \s-1GAS\s0's hash tables to a prime number close to
+\&\fInumber\fR.  Increasing this value can reduce the length of time it takes the
+assembler to perform its tasks, at the expense of increasing the assembler's
+memory requirements.  Similarly reducing this value can reduce the memory
+requirements at the expense of speed.
+.IP "\fB\-\-reduce\-memory\-overheads\fR" 4
+.IX Item "--reduce-memory-overheads"
+This option reduces \s-1GAS\s0's memory requirements, at the expense of making the
+assembly processes slower.  Currently this switch is a synonym for
+\&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.
 .IP "\fB\-\-statistics\fR" 4
 .IX Item "--statistics"
 Print the maximum space (in bytes) and total time (in seconds) used by
@@ -504,8 +568,8 @@ Select which floating point \s-1ABI\s0 is in use.
 .IP "\fB\-mthumb\fR" 4
 .IX Item "-mthumb"
 Enable Thumb only instruction decoding.
-.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant | \-moabi\fR" 4
-.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi"
+.IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
+.IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
 Select which procedure calling convention is in use.
 .IP "\fB\-EB | \-EL\fR" 4
 .IX Item "-EB | -EL"
@@ -562,6 +626,15 @@ Restores the default behaviour, which restricts the permitted instructions to
 just the basic \s-1IP2022\s0 ones.
 .PP
 The following options are available when as is configured for the
+Renesas M32C and M16C processors.
+.IP "\fB\-m32c\fR" 4
+.IX Item "-m32c"
+Assemble M32C instructions.
+.IP "\fB\-m16c\fR" 4
+.IX Item "-m16c"
+Assemble M16C instructions (the default).
+.PP
+The following options are available when as is configured for the
 Renesas M32R (formerly Mitsubishi M32R) series.
 .IP "\fB\-\-m32rx\fR" 4
 .IX Item "--m32rx"
@@ -604,7 +677,7 @@ The target machine does (or does not) have a memory-management
 unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
 .PP
 For details about the \s-1PDP\-11\s0 machine dependent features options,
-see \f(CW@ref\fR{PDP\-11\-Options}.
+see \fBPDP\-11\-Options\fR.
 .IP "\fB\-mpic | \-mno\-pic\fR" 4
 .IX Item "-mpic | -mno-pic"
 Generate position-independent (or position\-dependent) code.  The
@@ -635,10 +708,10 @@ The following options are available when as is configured for
 a picoJava processor.
 .IP "\fB\-mb\fR" 4
 .IX Item "-mb"
-Generate ``big endian'' format output.
+Generate \*(L"big endian\*(R" format output.
 .IP "\fB\-ml\fR" 4
 .IX Item "-ml"
-Generate ``little endian'' format output.
+Generate \*(L"little endian\*(R" format output.
 .PP
 The following options are available when as is configured for the
 Motorola 68HC11 or 68HC12 series.
@@ -728,10 +801,10 @@ implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targ
 use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
 .IP "\fB\-EB\fR" 4
 .IX Item "-EB"
-Generate ``big endian'' format output.
+Generate \*(L"big endian\*(R" format output.
 .IP "\fB\-EL\fR" 4
 .IX Item "-EL"
-Generate ``little endian'' format output.
+Generate \*(L"little endian\*(R" format output.
 .IP "\fB\-mips1\fR" 4
 .IX Item "-mips1"
 .PD 0
@@ -828,6 +901,24 @@ This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
 Generate code for the \s-1MDMX\s0 Application Specific Extension.
 This tells the assembler to accept \s-1MDMX\s0 instructions.
 \&\fB\-no\-mdmx\fR turns off this option.
+.IP "\fB\-mdsp\fR" 4
+.IX Item "-mdsp"
+.PD 0
+.IP "\fB\-mno\-dsp\fR" 4
+.IX Item "-mno-dsp"
+.PD
+Generate code for the \s-1DSP\s0 Application Specific Extension.
+This tells the assembler to accept \s-1DSP\s0 instructions.
+\&\fB\-mno\-dsp\fR turns off this option.
+.IP "\fB\-mmt\fR" 4
+.IX Item "-mmt"
+.PD 0
+.IP "\fB\-mno\-mt\fR" 4
+.IX Item "-mno-mt"
+.PD
+Generate code for the \s-1MT\s0 Application Specific Extension.
+This tells the assembler to accept \s-1MT\s0 instructions.
+\&\fB\-mno\-mt\fR turns off this option.
 .IP "\fB\-\-construct\-floats\fR" 4
 .IX Item "--construct-floats"
 .PD 0
@@ -923,29 +1014,20 @@ See the info pages for documentation of the MMIX-specific options.
 .PP
 The following options are available when as is configured for
 an Xtensa processor.
-.IP "\fB\-\-density | \-\-no\-density\fR" 4
-.IX Item "--density | --no-density"
-Enable or disable use of instructions from the Xtensa code density
-option.  This is enabled by default when the Xtensa processor supports
-the code density option.
-.IP "\fB\-\-relax | \-\-no\-relax\fR" 4
-.IX Item "--relax | --no-relax"
-Enable or disable instruction relaxation.  This is enabled by default.
-Note: In the current implementation, these options also control whether
-assembler optimizations are performed, making these options equivalent
-to \fB\-\-generics\fR and \fB\-\-no\-generics\fR.
-.IP "\fB\-\-generics | \-\-no\-generics\fR" 4
-.IX Item "--generics | --no-generics"
-Enable or disable all assembler transformations of Xtensa instructions.
-The default is \fB\-\-generics\fR;
-\&\fB\-\-no\-generics\fR should be used only in the rare cases when the
-instructions must be exactly as specified in the assembly source.
 .IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
 .IX Item "--text-section-literals | --no-text-section-literals"
 With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
 in the text section.  The default is
 \&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
-separate section in the output file.
+separate section in the output file.  These options only affect literals
+referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for
+absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
+.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
+.IX Item "--absolute-literals | --no-absolute-literals"
+Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
+or PC-relative addressing.  The default is to assume absolute addressing
+if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing
+option.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.
 .IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
 .IX Item "--target-align | --no-target-align"
 Enable or disable automatic alignment to reduce branch penalties at the
@@ -955,6 +1037,63 @@ expense of some code density.  The default is \fB\-\-target\-align\fR.
 Enable or disable transformation of call instructions to allow calls
 across a greater range of addresses.  The default is
 \&\fB\-\-no\-longcalls\fR.
+.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
+.IX Item "--transform | --no-transform"
+Enable or disable all assembler transformations of Xtensa instructions.
+The default is \fB\-\-transform\fR;
+\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
+instructions must be exactly as specified in the assembly source.
+.PP
+The following options are available when as is configured for
+a Z80 family processor.
+.IP "\fB\-z80\fR" 4
+.IX Item "-z80"
+Assemble for Z80 processor.
+.IP "\fB\-r800\fR" 4
+.IX Item "-r800"
+Assemble for R800 processor.
+.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
+.IX Item "-ignore-undocumented-instructions"
+.PD 0
+.IP "\fB\-Wnud\fR" 4
+.IX Item "-Wnud"
+.PD
+Assemble undocumented Z80 instructions that also work on R800 without warning.
+.IP "\fB\-ignore\-unportable\-instructions\fR" 4
+.IX Item "-ignore-unportable-instructions"
+.PD 0
+.IP "\fB\-Wnup\fR" 4
+.IX Item "-Wnup"
+.PD
+Assemble all undocumented Z80 instructions without warning.
+.IP "\fB\-warn\-undocumented\-instructions\fR" 4
+.IX Item "-warn-undocumented-instructions"
+.PD 0
+.IP "\fB\-Wud\fR" 4
+.IX Item "-Wud"
+.PD
+Issue a warning for undocumented Z80 instructions that also work on R800.
+.IP "\fB\-warn\-unportable\-instructions\fR" 4
+.IX Item "-warn-unportable-instructions"
+.PD 0
+.IP "\fB\-Wup\fR" 4
+.IX Item "-Wup"
+.PD
+Issue a warning for undocumented Z80 instructions that do notwork on R800.  
+.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
+.IX Item "-forbid-undocumented-instructions"
+.PD 0
+.IP "\fB\-Fud\fR" 4
+.IX Item "-Fud"
+.PD
+Treat all undocumented instructions as errors.
+.IP "\fB\-forbid\-unportable\-instructions\fR" 4
+.IX Item "-forbid-unportable-instructions"
+.PD 0
+.IP "\fB\-Fup\fR" 4
+.IX Item "-Fup"
+.PD
+Treat undocumented Z80 intructions that do notwork on R800 as errors.
 .SH "SEE ALSO"
 .IX Header "SEE ALSO"
 \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
@@ -967,4 +1106,4 @@ under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
 or any later version published by the Free Software Foundation;
 with no Invariant Sections, with no Front-Cover Texts, and with no
 Back-Cover Texts.  A copy of the license is included in the
-section entitled ``\s-1GNU\s0 Free Documentation License''.
+section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".
diff --git a/gas/doc/as.info b/gas/doc/as.info
new file mode 100644
index 000000000000..adf3ed4558bd
--- /dev/null
+++ b/gas/doc/as.info
@@ -0,0 +1,18352 @@
+This is ../.././gas/doc/as.info, produced by makeinfo version 4.8 from
+../.././gas/doc/as.texinfo.
+
+START-INFO-DIR-ENTRY
+* As: (as).                     The GNU assembler.
+* Gas: (as).                    The GNU assembler.
+END-INFO-DIR-ENTRY
+
+   This file documents the GNU Assembler "as".
+
+   Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002
+Free Software Foundation, Inc.
+
+   Permission is granted to copy, distribute and/or modify this document
+under the terms of the GNU Free Documentation License, Version 1.1 or
+any later version published by the Free Software Foundation; with no
+Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
+Texts.  A copy of the license is included in the section entitled "GNU
+Free Documentation License".
+
+
+File: as.info,  Node: Top,  Next: Overview,  Up: (dir)
+
+Using as
+********
+
+This file is a user guide to the GNU assembler `as' version 2.17.
+
+   This document is distributed under the terms of the GNU Free
+Documentation License.  A copy of the license is included in the
+section entitled "GNU Free Documentation License".
+
+* Menu:
+
+* Overview::                    Overview
+* Invoking::                    Command-Line Options
+* Syntax::                      Syntax
+* Sections::                    Sections and Relocation
+* Symbols::                     Symbols
+* Expressions::                 Expressions
+* Pseudo Ops::                  Assembler Directives
+* Machine Dependencies::        Machine Dependent Features
+* Reporting Bugs::              Reporting Bugs
+* Acknowledgements::            Who Did What
+* GNU Free Documentation License::  GNU Free Documentation License
+* Index::                       Index
+
+
+File: as.info,  Node: Overview,  Next: Invoking,  Prev: Top,  Up: Top
+
+1 Overview
+**********
+
+Here is a brief summary of how to invoke `as'.  For details, *note
+Command-Line Options: Invoking.
+
+     as [-a[cdhlns][=FILE]] [-alternate] [-D]
+      [-defsym SYM=VAL] [-f] [-g] [-gstabs]
+      [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J]
+      [-K] [-L] [-listing-lhs-width=NUM]
+      [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM]
+      [-listing-cont-lines=NUM] [-keep-locals] [-o
+      OBJFILE] [-R] [-reduce-memory-overheads] [-statistics]
+      [-v] [-version] [-version] [-W] [-warn]
+      [-fatal-warnings] [-w] [-x] [-Z] [@FILE]
+      [-target-help] [TARGET-OPTIONS]
+      [-|FILES ...]
+
+     _Target Alpha options:_
+        [-mCPU]
+        [-mdebug | -no-mdebug]
+        [-relax] [-g] [-GSIZE]
+        [-F] [-32addr]
+
+     _Target ARC options:_
+        [-marc[5|6|7|8]]
+        [-EB|-EL]
+
+     _Target ARM options:_
+        [-mcpu=PROCESSOR[+EXTENSION...]]
+        [-march=ARCHITECTURE[+EXTENSION...]]
+        [-mfpu=FLOATING-POINT-FORMAT]
+        [-mfloat-abi=ABI]
+        [-meabi=VER]
+        [-mthumb]
+        [-EB|-EL]
+        [-mapcs-32|-mapcs-26|-mapcs-float|
+         -mapcs-reentrant]
+        [-mthumb-interwork] [-k]
+
+     _Target CRIS options:_
+        [-underscore | -no-underscore]
+        [-pic] [-N]
+        [-emulation=criself | -emulation=crisaout]
+        [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32]
+
+     _Target D10V options:_
+        [-O]
+
+     _Target D30V options:_
+        [-O|-n|-N]
+
+     _Target i386 options:_
+        [-32|-64] [-n]
+
+     _Target i960 options:_
+        [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
+         -AKC|-AMC]
+        [-b] [-no-relax]
+
+     _Target IA-64 options:_
+        [-mconstant-gp|-mauto-pic]
+        [-milp32|-milp64|-mlp64|-mp64]
+        [-mle|mbe]
+        [-mtune=itanium1|-mtune=itanium2]
+        [-munwind-check=warning|-munwind-check=error]
+        [-mhint.b=ok|-mhint.b=warning|-mhint.b=error]
+        [-x|-xexplicit] [-xauto] [-xdebug]
+
+     _Target IP2K options:_
+        [-mip2022|-mip2022ext]
+
+     _Target M32C options:_
+        [-m32c|-m16c]
+
+     _Target M32R options:_
+        [-m32rx|-[no-]warn-explicit-parallel-conflicts|
+        -W[n]p]
+
+     _Target M680X0 options:_
+        [-l] [-m68000|-m68010|-m68020|...]
+
+     _Target M68HC11 options:_
+        [-m68hc11|-m68hc12|-m68hcs12]
+        [-mshort|-mlong]
+        [-mshort-double|-mlong-double]
+        [-force-long-branchs] [-short-branchs]
+        [-strict-direct-mode] [-print-insn-syntax]
+        [-print-opcodes] [-generate-example]
+
+     _Target MCORE options:_
+        [-jsri2bsr] [-sifilter] [-relax]
+        [-mcpu=[210|340]]
+
+     _Target MIPS options:_
+        [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]]
+        [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared]
+        [-non_shared] [-xgot]
+        [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]
+        [-march=CPU] [-mtune=CPU] [-mips1] [-mips2]
+        [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]
+        [-mips64] [-mips64r2]
+        [-construct-floats] [-no-construct-floats]
+        [-trap] [-no-break] [-break] [-no-trap]
+        [-mfix7000] [-mno-fix7000]
+        [-mips16] [-no-mips16]
+        [-mips3d] [-no-mips3d]
+        [-mdmx] [-no-mdmx]
+        [-mdsp] [-mno-dsp]
+        [-mmt] [-mno-mt]
+        [-mdebug] [-no-mdebug]
+        [-mpdr] [-mno-pdr]
+
+     _Target MMIX options:_
+        [-fixed-special-register-names] [-globalize-symbols]
+        [-gnu-syntax] [-relax] [-no-predefined-symbols]
+        [-no-expand] [-no-merge-gregs] [-x]
+        [-linker-allocated-gregs]
+
+     _Target PDP11 options:_
+        [-mpic|-mno-pic] [-mall] [-mno-extensions]
+        [-mEXTENSION|-mno-EXTENSION]
+        [-mCPU] [-mMACHINE]
+
+     _Target picoJava options:_
+        [-mb|-me]
+
+     _Target PowerPC options:_
+        [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
+         -m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
+         -mbooke32|-mbooke64]
+        [-mcom|-many|-maltivec] [-memb]
+        [-mregnames|-mno-regnames]
+        [-mrelocatable|-mrelocatable-lib]
+        [-mlittle|-mlittle-endian|-mbig|-mbig-endian]
+        [-msolaris|-mno-solaris]
+
+     _Target SPARC options:_
+        [-Av6|-Av7|-Av8|-Asparclet|-Asparclite
+         -Av8plus|-Av8plusa|-Av9|-Av9a]
+        [-xarch=v8plus|-xarch=v8plusa] [-bump]
+        [-32|-64]
+
+     _Target TIC54X options:_
+      [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]
+      [-merrors-to-file <FILENAME>|-me <FILENAME>]
+
+
+     _Target Z80 options:_
+       [-z80] [-r800]
+       [ -ignore-undocumented-instructions] [-Wnud]
+       [ -ignore-unportable-instructions] [-Wnup]
+       [ -warn-undocumented-instructions] [-Wud]
+       [ -warn-unportable-instructions] [-Wup]
+       [ -forbid-undocumented-instructions] [-Fud]
+       [ -forbid-unportable-instructions] [-Fup]
+
+
+     _Target Xtensa options:_
+      [-[no-]text-section-literals] [-[no-]absolute-literals]
+      [-[no-]target-align] [-[no-]longcalls]
+      [-[no-]transform]
+      [-rename-section OLDNAME=NEWNAME]
+
+`@FILE'
+     Read command-line options from FILE.  The options read are
+     inserted in place of the original @FILE option.  If FILE does not
+     exist, or cannot be read, then the option will be treated
+     literally, and not removed.
+
+     Options in FILE are separated by whitespace.  A whitespace
+     character may be included in an option by surrounding the entire
+     option in either single or double quotes.  Any character
+     (including a backslash) may be included by prefixing the character
+     to be included with a backslash.  The FILE may itself contain
+     additional @FILE options; any such options will be processed
+     recursively.
+
+`-a[cdhlmns]'
+     Turn on listings, in any of a variety of ways:
+
+    `-ac'
+          omit false conditionals
+
+    `-ad'
+          omit debugging directives
+
+    `-ah'
+          include high-level source
+
+    `-al'
+          include assembly
+
+    `-am'
+          include macro expansions
+
+    `-an'
+          omit forms processing
+
+    `-as'
+          include symbols
+
+    `=file'
+          set the name of the listing file
+
+     You may combine these options; for example, use `-aln' for assembly
+     listing without forms processing.  The `=file' option, if used,
+     must be the last one.  By itself, `-a' defaults to `-ahls'.
+
+`--alternate'
+     Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
+
+`-D'
+     Ignored.  This option is accepted for script compatibility with
+     calls to other assemblers.
+
+`--defsym SYM=VALUE'
+     Define the symbol SYM to be VALUE before assembling the input file.
+     VALUE must be an integer constant.  As in C, a leading `0x'
+     indicates a hexadecimal value, and a leading `0' indicates an
+     octal value.
+
+`-f'
+     "fast"--skip whitespace and comment preprocessing (assume source is
+     compiler output).
+
+`-g'
+`--gen-debug'
+     Generate debugging information for each assembler source line
+     using whichever debug format is preferred by the target.  This
+     currently means either STABS, ECOFF or DWARF2.
+
+`--gstabs'
+     Generate stabs debugging information for each assembler line.  This
+     may help debugging assembler code, if the debugger can handle it.
+
+`--gstabs+'
+     Generate stabs debugging information for each assembler line, with
+     GNU extensions that probably only gdb can handle, and that could
+     make other debuggers crash or refuse to read your program.  This
+     may help debugging assembler code.  Currently the only GNU
+     extension is the location of the current working directory at
+     assembling time.
+
+`--gdwarf-2'
+     Generate DWARF2 debugging information for each assembler line.
+     This may help debugging assembler code, if the debugger can handle
+     it.  Note--this option is only supported by some targets, not all
+     of them.
+
+`--help'
+     Print a summary of the command line options and exit.
+
+`--target-help'
+     Print a summary of all target specific options and exit.
+
+`-I DIR'
+     Add directory DIR to the search list for `.include' directives.
+
+`-J'
+     Don't warn about signed overflow.
+
+`-K'
+     Issue warnings when difference tables altered for long
+     displacements.
+
+`-L'
+`--keep-locals'
+     Keep (in the symbol table) local symbols.  On traditional a.out
+     systems these start with `L', but different systems have different
+     local label prefixes.
+
+`--listing-lhs-width=NUMBER'
+     Set the maximum width, in words, of the output data column for an
+     assembler listing to NUMBER.
+
+`--listing-lhs-width2=NUMBER'
+     Set the maximum width, in words, of the output data column for
+     continuation lines in an assembler listing to NUMBER.
+
+`--listing-rhs-width=NUMBER'
+     Set the maximum width of an input source line, as displayed in a
+     listing, to NUMBER bytes.
+
+`--listing-cont-lines=NUMBER'
+     Set the maximum number of lines printed in a listing for a single
+     line of input to NUMBER + 1.
+
+`-o OBJFILE'
+     Name the object-file output from `as' OBJFILE.
+
+`-R'
+     Fold the data section into the text section.
+
+     Set the default size of GAS's hash tables to a prime number close
+     to NUMBER.  Increasing this value can reduce the length of time it
+     takes the assembler to perform its tasks, at the expense of
+     increasing the assembler's memory requirements.  Similarly
+     reducing this value can reduce the memory requirements at the
+     expense of speed.
+
+`--reduce-memory-overheads'
+     This option reduces GAS's memory requirements, at the expense of
+     making the assembly processes slower.  Currently this switch is a
+     synonym for `--hash-size=4051', but in the future it may have
+     other effects as well.
+
+`--statistics'
+     Print the maximum space (in bytes) and total time (in seconds)
+     used by assembly.
+
+`--strip-local-absolute'
+     Remove local absolute symbols from the outgoing symbol table.
+
+`-v'
+`-version'
+     Print the `as' version.
+
+`--version'
+     Print the `as' version and exit.
+
+`-W'
+`--no-warn'
+     Suppress warning messages.
+
+`--fatal-warnings'
+     Treat warnings as errors.
+
+`--warn'
+     Don't suppress warning messages or treat them as errors.
+
+`-w'
+     Ignored.
+
+`-x'
+     Ignored.
+
+`-Z'
+     Generate an object file even after errors.
+
+`-- | FILES ...'
+     Standard input, or source files to assemble.
+
+
+   The following options are available when as is configured for an ARC
+processor.
+
+`-marc[5|6|7|8]'
+     This option selects the core processor variant.
+
+`-EB | -EL'
+     Select either big-endian (-EB) or little-endian (-EL) output.
+
+   The following options are available when as is configured for the ARM
+processor family.
+
+`-mcpu=PROCESSOR[+EXTENSION...]'
+     Specify which ARM processor variant is the target.
+
+`-march=ARCHITECTURE[+EXTENSION...]'
+     Specify which ARM architecture variant is used by the target.
+
+`-mfpu=FLOATING-POINT-FORMAT'
+     Select which Floating Point architecture is the target.
+
+`-mfloat-abi=ABI'
+     Select which floating point ABI is in use.
+
+`-mthumb'
+     Enable Thumb only instruction decoding.
+
+`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant'
+     Select which procedure calling convention is in use.
+
+`-EB | -EL'
+     Select either big-endian (-EB) or little-endian (-EL) output.
+
+`-mthumb-interwork'
+     Specify that the code has been generated with interworking between
+     Thumb and ARM code in mind.
+
+`-k'
+     Specify that PIC code has been generated.
+
+   See the info pages for documentation of the CRIS-specific options.
+
+   The following options are available when as is configured for a D10V
+processor.
+`-O'
+     Optimize output by parallelizing instructions.
+
+   The following options are available when as is configured for a D30V
+processor.
+`-O'
+     Optimize output by parallelizing instructions.
+
+`-n'
+     Warn when nops are generated.
+
+`-N'
+     Warn when a nop after a 32-bit multiply instruction is generated.
+
+   The following options are available when as is configured for the
+Intel 80960 processor.
+
+`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
+     Specify which variant of the 960 architecture is the target.
+
+`-b'
+     Add code to collect statistics about branches taken.
+
+`-no-relax'
+     Do not alter compare-and-branch instructions for long
+     displacements; error if necessary.
+
+
+   The following options are available when as is configured for the
+Ubicom IP2K series.
+
+`-mip2022ext'
+     Specifies that the extended IP2022 instructions are allowed.
+
+`-mip2022'
+     Restores the default behaviour, which restricts the permitted
+     instructions to just the basic IP2022 ones.
+
+
+   The following options are available when as is configured for the
+Renesas M32C and M16C processors.
+
+`-m32c'
+     Assemble M32C instructions.
+
+`-m16c'
+     Assemble M16C instructions (the default).
+
+
+   The following options are available when as is configured for the
+Renesas M32R (formerly Mitsubishi M32R) series.
+
+`--m32rx'
+     Specify which processor in the M32R family is the target.  The
+     default is normally the M32R, but this option changes it to the
+     M32RX.
+
+`--warn-explicit-parallel-conflicts or --Wp'
+     Produce warning messages when questionable parallel constructs are
+     encountered.
+
+`--no-warn-explicit-parallel-conflicts or --Wnp'
+     Do not produce warning messages when questionable parallel
+     constructs are encountered.
+
+
+   The following options are available when as is configured for the
+Motorola 68000 series.
+
+`-l'
+     Shorten references to undefined symbols, to one word instead of
+     two.
+
+`-m68000 | -m68008 | -m68010 | -m68020 | -m68030'
+`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332'
+`| -m68333 | -m68340 | -mcpu32 | -m5200'
+     Specify what processor in the 68000 family is the target.  The
+     default is normally the 68020, but this can be changed at
+     configuration time.
+
+`-m68881 | -m68882 | -mno-68881 | -mno-68882'
+     The target machine does (or does not) have a floating-point
+     coprocessor.  The default is to assume a coprocessor for 68020,
+     68030, and cpu32.  Although the basic 68000 is not compatible with
+     the 68881, a combination of the two can be specified, since it's
+     possible to do emulation of the coprocessor instructions with the
+     main processor.
+
+`-m68851 | -mno-68851'
+     The target machine does (or does not) have a memory-management
+     unit coprocessor.  The default is to assume an MMU for 68020 and
+     up.
+
+
+   For details about the PDP-11 machine dependent features options, see
+*Note PDP-11-Options::.
+
+`-mpic | -mno-pic'
+     Generate position-independent (or position-dependent) code.  The
+     default is `-mpic'.
+
+`-mall'
+`-mall-extensions'
+     Enable all instruction set extensions.  This is the default.
+
+`-mno-extensions'
+     Disable all instruction set extensions.
+
+`-mEXTENSION | -mno-EXTENSION'
+     Enable (or disable) a particular instruction set extension.
+
+`-mCPU'
+     Enable the instruction set extensions supported by a particular
+     CPU, and disable all other extensions.
+
+`-mMACHINE'
+     Enable the instruction set extensions supported by a particular
+     machine model, and disable all other extensions.
+
+   The following options are available when as is configured for a
+picoJava processor.
+
+`-mb'
+     Generate "big endian" format output.
+
+`-ml'
+     Generate "little endian" format output.
+
+
+   The following options are available when as is configured for the
+Motorola 68HC11 or 68HC12 series.
+
+`-m68hc11 | -m68hc12 | -m68hcs12'
+     Specify what processor is the target.  The default is defined by
+     the configuration option when building the assembler.
+
+`-mshort'
+     Specify to use the 16-bit integer ABI.
+
+`-mlong'
+     Specify to use the 32-bit integer ABI.
+
+`-mshort-double'
+     Specify to use the 32-bit double ABI.
+
+`-mlong-double'
+     Specify to use the 64-bit double ABI.
+
+`--force-long-branchs'
+     Relative branches are turned into absolute ones. This concerns
+     conditional branches, unconditional branches and branches to a sub
+     routine.
+
+`-S | --short-branchs'
+     Do not turn relative branchs into absolute ones when the offset is
+     out of range.
+
+`--strict-direct-mode'
+     Do not turn the direct addressing mode into extended addressing
+     mode when the instruction does not support direct addressing mode.
+
+`--print-insn-syntax'
+     Print the syntax of instruction in case of error.
+
+`--print-opcodes'
+     print the list of instructions with syntax and then exit.
+
+`--generate-example'
+     print an example of instruction for each possible instruction and
+     then exit.  This option is only useful for testing `as'.
+
+
+   The following options are available when `as' is configured for the
+SPARC architecture:
+
+`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
+`-Av8plus | -Av8plusa | -Av9 | -Av9a'
+     Explicitly select a variant of the SPARC architecture.
+
+     `-Av8plus' and `-Av8plusa' select a 32 bit environment.  `-Av9'
+     and `-Av9a' select a 64 bit environment.
+
+     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
+     UltraSPARC extensions.
+
+`-xarch=v8plus | -xarch=v8plusa'
+     For compatibility with the Solaris v9 assembler.  These options are
+     equivalent to -Av8plus and -Av8plusa, respectively.
+
+`-bump'
+     Warn when the assembler switches to another architecture.
+
+   The following options are available when as is configured for the
+'c54x architecture.
+
+`-mfar-mode'
+     Enable extended addressing mode.  All addresses and relocations
+     will assume extended addressing (usually 23 bits).
+
+`-mcpu=CPU_VERSION'
+     Sets the CPU version being compiled for.
+
+`-merrors-to-file FILENAME'
+     Redirect error output to a file, for broken systems which don't
+     support such behaviour in the shell.
+
+   The following options are available when as is configured for a MIPS
+processor.
+
+`-G NUM'
+     This option sets the largest size of an object that can be
+     referenced implicitly with the `gp' register.  It is only accepted
+     for targets that use ECOFF format, such as a DECstation running
+     Ultrix.  The default value is 8.
+
+`-EB'
+     Generate "big endian" format output.
+
+`-EL'
+     Generate "little endian" format output.
+
+`-mips1'
+`-mips2'
+`-mips3'
+`-mips4'
+`-mips5'
+`-mips32'
+`-mips32r2'
+`-mips64'
+`-mips64r2'
+     Generate code for a particular MIPS Instruction Set Architecture
+     level.  `-mips1' is an alias for `-march=r3000', `-mips2' is an
+     alias for `-march=r6000', `-mips3' is an alias for `-march=r4000'
+     and `-mips4' is an alias for `-march=r8000'.  `-mips5', `-mips32',
+     `-mips32r2', `-mips64', and `-mips64r2' correspond to generic
+     `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64
+     Release 2' ISA processors, respectively.
+
+`-march=CPU'
+     Generate code for a particular MIPS cpu.
+
+`-mtune=CPU'
+     Schedule and tune for a particular MIPS cpu.
+
+`-mfix7000'
+`-mno-fix7000'
+     Cause nops to be inserted if the read of the destination register
+     of an mfhi or mflo instruction occurs in the following two
+     instructions.
+
+`-mdebug'
+`-no-mdebug'
+     Cause stabs-style debugging output to go into an ECOFF-style
+     .mdebug section instead of the standard ELF .stabs sections.
+
+`-mpdr'
+`-mno-pdr'
+     Control generation of `.pdr' sections.
+
+`-mgp32'
+`-mfp32'
+     The register sizes are normally inferred from the ISA and ABI, but
+     these flags force a certain group of registers to be treated as 32
+     bits wide at all times.  `-mgp32' controls the size of
+     general-purpose registers and `-mfp32' controls the size of
+     floating-point registers.
+
+`-mips16'
+`-no-mips16'
+     Generate code for the MIPS 16 processor.  This is equivalent to
+     putting `.set mips16' at the start of the assembly file.
+     `-no-mips16' turns off this option.
+
+`-mips3d'
+`-no-mips3d'
+     Generate code for the MIPS-3D Application Specific Extension.
+     This tells the assembler to accept MIPS-3D instructions.
+     `-no-mips3d' turns off this option.
+
+`-mdmx'
+`-no-mdmx'
+     Generate code for the MDMX Application Specific Extension.  This
+     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
+     off this option.
+
+`-mdsp'
+`-mno-dsp'
+     Generate code for the DSP Application Specific Extension.  This
+     tells the assembler to accept DSP instructions.  `-mno-dsp' turns
+     off this option.
+
+`-mmt'
+`-mno-mt'
+     Generate code for the MT Application Specific Extension.  This
+     tells the assembler to accept MT instructions.  `-mno-mt' turns
+     off this option.
+
+`--construct-floats'
+`--no-construct-floats'
+     The `--no-construct-floats' option disables the construction of
+     double width floating point constants by loading the two halves of
+     the value into the two single width floating point registers that
+     make up the double width register.  By default
+     `--construct-floats' is selected, allowing construction of these
+     floating point constants.
+
+`--emulation=NAME'
+     This option causes `as' to emulate `as' configured for some other
+     target, in all respects, including output format (choosing between
+     ELF and ECOFF only), handling of pseudo-opcodes which may generate
+     debugging information or store symbol table information, and
+     default endianness.  The available configuration names are:
+     `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf',
+     `mipsbelf'.  The first two do not alter the default endianness
+     from that of the primary target for which the assembler was
+     configured; the others change the default to little- or big-endian
+     as indicated by the `b' or `l' in the name.  Using `-EB' or `-EL'
+     will override the endianness selection in any case.
+
+     This option is currently supported only when the primary target
+     `as' is configured for is a MIPS ELF or ECOFF target.
+     Furthermore, the primary target or others specified with
+     `--enable-targets=...' at configuration time must include support
+     for the other format, if both are to be available.  For example,
+     the Irix 5 configuration includes support for both.
+
+     Eventually, this option will support more configurations, with more
+     fine-grained control over the assembler's behavior, and will be
+     supported for more processors.
+
+`-nocpp'
+     `as' ignores this option.  It is accepted for compatibility with
+     the native tools.
+
+`--trap'
+`--no-trap'
+`--break'
+`--no-break'
+     Control how to deal with multiplication overflow and division by
+     zero.  `--trap' or `--no-break' (which are synonyms) take a trap
+     exception (and only work for Instruction Set Architecture level 2
+     and higher); `--break' or `--no-trap' (also synonyms, and the
+     default) take a break exception.
+
+`-n'
+     When this option is used, `as' will issue a warning every time it
+     generates a nop instruction from a macro.
+
+   The following options are available when as is configured for an
+MCore processor.
+
+`-jsri2bsr'
+`-nojsri2bsr'
+     Enable or disable the JSRI to BSR transformation.  By default this
+     is enabled.  The command line option `-nojsri2bsr' can be used to
+     disable it.
+
+`-sifilter'
+`-nosifilter'
+     Enable or disable the silicon filter behaviour.  By default this
+     is disabled.  The default can be overridden by the `-sifilter'
+     command line option.
+
+`-relax'
+     Alter jump instructions for long displacements.
+
+`-mcpu=[210|340]'
+     Select the cpu type on the target hardware.  This controls which
+     instructions can be assembled.
+
+`-EB'
+     Assemble for a big endian target.
+
+`-EL'
+     Assemble for a little endian target.
+
+
+   See the info pages for documentation of the MMIX-specific options.
+
+   The following options are available when as is configured for an
+Xtensa processor.
+
+`--text-section-literals | --no-text-section-literals'
+     With `--text-section-literals', literal pools are interspersed in
+     the text section.  The default is `--no-text-section-literals',
+     which places literals in a separate section in the output file.
+     These options only affect literals referenced via PC-relative
+     `L32R' instructions; literals for absolute mode `L32R'
+     instructions are handled separately.
+
+`--absolute-literals | --no-absolute-literals'
+     Indicate to the assembler whether `L32R' instructions use absolute
+     or PC-relative addressing.  The default is to assume absolute
+     addressing if the Xtensa processor includes the absolute `L32R'
+     addressing option.  Otherwise, only the PC-relative `L32R' mode
+     can be used.
+
+`--target-align | --no-target-align'
+     Enable or disable automatic alignment to reduce branch penalties
+     at the expense of some code density.  The default is
+     `--target-align'.
+
+`--longcalls | --no-longcalls'
+     Enable or disable transformation of call instructions to allow
+     calls across a greater range of addresses.  The default is
+     `--no-longcalls'.
+
+`--transform | --no-transform'
+     Enable or disable all assembler transformations of Xtensa
+     instructions.  The default is `--transform'; `--no-transform'
+     should be used only in the rare cases when the instructions must
+     be exactly as specified in the assembly source.
+
+   The following options are available when as is configured for a Z80
+family processor.
+`-z80'
+     Assemble for Z80 processor.
+
+`-r800'
+     Assemble for R800 processor.
+
+`-ignore-undocumented-instructions'
+`-Wnud'
+     Assemble undocumented Z80 instructions that also work on R800
+     without warning.
+
+`-ignore-unportable-instructions'
+`-Wnup'
+     Assemble all undocumented Z80 instructions without warning.
+
+`-warn-undocumented-instructions'
+`-Wud'
+     Issue a warning for undocumented Z80 instructions that also work
+     on R800.
+
+`-warn-unportable-instructions'
+`-Wup'
+     Issue a warning for undocumented Z80 instructions that do notwork
+     on R800.
+
+`-forbid-undocumented-instructions'
+`-Fud'
+     Treat all undocumented instructions as errors.
+
+`-forbid-unportable-instructions'
+`-Fup'
+     Treat undocumented Z80 intructions that do notwork on R800 as
+     errors.
+
+* Menu:
+
+* Manual::                      Structure of this Manual
+* GNU Assembler::               The GNU Assembler
+* Object Formats::              Object File Formats
+* Command Line::                Command Line
+* Input Files::                 Input Files
+* Object::                      Output (Object) File
+* Errors::                      Error and Warning Messages
+
+
+File: as.info,  Node: Manual,  Next: GNU Assembler,  Up: Overview
+
+1.1 Structure of this Manual
+============================
+
+This manual is intended to describe what you need to know to use GNU
+`as'.  We cover the syntax expected in source files, including notation
+for symbols, constants, and expressions; the directives that `as'
+understands; and of course how to invoke `as'.
+
+   This manual also describes some of the machine-dependent features of
+various flavors of the assembler.
+
+   On the other hand, this manual is _not_ intended as an introduction
+to programming in assembly language--let alone programming in general!
+In a similar vein, we make no attempt to introduce the machine
+architecture; we do _not_ describe the instruction set, standard
+mnemonics, registers or addressing modes that are standard to a
+particular architecture.  You may want to consult the manufacturer's
+machine architecture manual for this information.
+
+
+File: as.info,  Node: GNU Assembler,  Next: Object Formats,  Prev: Manual,  Up: Overview
+
+1.2 The GNU Assembler
+=====================
+
+GNU `as' is really a family of assemblers.  If you use (or have used)
+the GNU assembler on one architecture, you should find a fairly similar
+environment when you use it on another architecture.  Each version has
+much in common with the others, including object file formats, most
+assembler directives (often called "pseudo-ops") and assembler syntax.
+
+   `as' is primarily intended to assemble the output of the GNU C
+compiler `gcc' for use by the linker `ld'.  Nevertheless, we've tried
+to make `as' assemble correctly everything that other assemblers for
+the same machine would assemble.  Any exceptions are documented
+explicitly (*note Machine Dependencies::).  This doesn't mean `as'
+always uses the same syntax as another assembler for the same
+architecture; for example, we know of several incompatible versions of
+680x0 assembly language syntax.
+
+   Unlike older assemblers, `as' is designed to assemble a source
+program in one pass of the source file.  This has a subtle impact on the
+`.org' directive (*note `.org': Org.).
+
+
+File: as.info,  Node: Object Formats,  Next: Command Line,  Prev: GNU Assembler,  Up: Overview
+
+1.3 Object File Formats
+=======================
+
+The GNU assembler can be configured to produce several alternative
+object file formats.  For the most part, this does not affect how you
+write assembly language programs; but directives for debugging symbols
+are typically different in different file formats.  *Note Symbol
+Attributes: Symbol Attributes.
+
+
+File: as.info,  Node: Command Line,  Next: Input Files,  Prev: Object Formats,  Up: Overview
+
+1.4 Command Line
+================
+
+After the program name `as', the command line may contain options and
+file names.  Options may appear in any order, and may be before, after,
+or between file names.  The order of file names is significant.
+
+   `--' (two hyphens) by itself names the standard input file
+explicitly, as one of the files for `as' to assemble.
+
+   Except for `--' any command line argument that begins with a hyphen
+(`-') is an option.  Each option changes the behavior of `as'.  No
+option changes the way another option works.  An option is a `-'
+followed by one or more letters; the case of the letter is important.
+All options are optional.
+
+   Some options expect exactly one file name to follow them.  The file
+name may either immediately follow the option's letter (compatible with
+older assemblers) or it may be the next command argument (GNU
+standard).  These two command lines are equivalent:
+
+     as -o my-object-file.o mumble.s
+     as -omy-object-file.o mumble.s
+
+
+File: as.info,  Node: Input Files,  Next: Object,  Prev: Command Line,  Up: Overview
+
+1.5 Input Files
+===============
+
+We use the phrase "source program", abbreviated "source", to describe
+the program input to one run of `as'.  The program may be in one or
+more files; how the source is partitioned into files doesn't change the
+meaning of the source.
+
+   The source program is a concatenation of the text in all the files,
+in the order specified.
+
+   Each time you run `as' it assembles exactly one source program.  The
+source program is made up of one or more files.  (The standard input is
+also a file.)
+
+   You give `as' a command line that has zero or more input file names.
+The input files are read (from left file name to right).  A command
+line argument (in any position) that has no special meaning is taken to
+be an input file name.
+
+   If you give `as' no file names it attempts to read one input file
+from the `as' standard input, which is normally your terminal.  You may
+have to type <ctl-D> to tell `as' there is no more program to assemble.
+
+   Use `--' if you need to explicitly name the standard input file in
+your command line.
+
+   If the source is empty, `as' produces a small, empty object file.
+
+Filenames and Line-numbers
+--------------------------
+
+There are two ways of locating a line in the input file (or files) and
+either may be used in reporting error messages.  One way refers to a
+line number in a physical file; the other refers to a line number in a
+"logical" file.  *Note Error and Warning Messages: Errors.
+
+   "Physical files" are those files named in the command line given to
+`as'.
+
+   "Logical files" are simply names declared explicitly by assembler
+directives; they bear no relation to physical files.  Logical file
+names help error messages reflect the original source file, when `as'
+source is itself synthesized from other files.  `as' understands the
+`#' directives emitted by the `gcc' preprocessor.  See also *Note
+`.file': File.
+
+
+File: as.info,  Node: Object,  Next: Errors,  Prev: Input Files,  Up: Overview
+
+1.6 Output (Object) File
+========================
+
+Every time you run `as' it produces an output file, which is your
+assembly language program translated into numbers.  This file is the
+object file.  Its default name is `a.out'.  You can give it another
+name by using the `-o' option.  Conventionally, object file names end
+with `.o'.  The default name is used for historical reasons: older
+assemblers were capable of assembling self-contained programs directly
+into a runnable program.  (For some formats, this isn't currently
+possible, but it can be done for the `a.out' format.)
+
+   The object file is meant for input to the linker `ld'.  It contains
+assembled program code, information to help `ld' integrate the
+assembled program into a runnable file, and (optionally) symbolic
+information for the debugger.
+
+
+File: as.info,  Node: Errors,  Prev: Object,  Up: Overview
+
+1.7 Error and Warning Messages
+==============================
+
+`as' may write warnings and error messages to the standard error file
+(usually your terminal).  This should not happen when  a compiler runs
+`as' automatically.  Warnings report an assumption made so that `as'
+could keep assembling a flawed program; errors report a grave problem
+that stops the assembly.
+
+   Warning messages have the format
+
+     file_name:NNN:Warning Message Text
+
+(where NNN is a line number).  If a logical file name has been given
+(*note `.file': File.) it is used for the filename, otherwise the name
+of the current input file is used.  If a logical line number was given
+(*note `.line': Line.)  then it is used to calculate the number printed,
+otherwise the actual line in the current source file is printed.  The
+message text is intended to be self explanatory (in the grand Unix
+tradition).
+
+   Error messages have the format
+     file_name:NNN:FATAL:Error Message Text
+   The file name and line number are derived as for warning messages.
+The actual message text may be rather less explanatory because many of
+them aren't supposed to happen.
+
+
+File: as.info,  Node: Invoking,  Next: Syntax,  Prev: Overview,  Up: Top
+
+2 Command-Line Options
+**********************
+
+This chapter describes command-line options available in _all_ versions
+of the GNU assembler; *note Machine Dependencies::, for options specific
+to particular machine architectures.
+
+   If you are invoking `as' via the GNU C compiler, you can use the
+`-Wa' option to pass arguments through to the assembler.  The assembler
+arguments must be separated from each other (and the `-Wa') by commas.
+For example:
+
+     gcc -c -g -O -Wa,-alh,-L file.c
+
+This passes two options to the assembler: `-alh' (emit a listing to
+standard output with high-level and assembly source) and `-L' (retain
+local symbols in the symbol table).
+
+   Usually you do not need to use this `-Wa' mechanism, since many
+compiler command-line options are automatically passed to the assembler
+by the compiler.  (You can call the GNU compiler driver with the `-v'
+option to see precisely what options it passes to each compilation
+pass, including the assembler.)
+
+* Menu:
+
+* a::             -a[cdhlns] enable listings
+* alternate::     --alternate enable alternate macro syntax
+* D::             -D for compatibility
+* f::             -f to work faster
+* I::             -I for .include search path
+
+* K::             -K for difference tables
+
+* L::             -L to retain local labels
+* listing::       --listing-XXX to configure listing output
+* M::		  -M or --mri to assemble in MRI compatibility mode
+* MD::            --MD for dependency tracking
+* o::             -o to name the object file
+* R::             -R to join data and text sections
+* statistics::    --statistics to see statistics about assembly
+* traditional-format:: --traditional-format for compatible output
+* v::             -v to announce version
+* W::             -W, --no-warn, --warn, --fatal-warnings to control warnings
+* Z::             -Z to make object file even after errors
+
+
+File: as.info,  Node: a,  Next: alternate,  Up: Invoking
+
+2.1 Enable Listings: `-a[cdhlns]'
+=================================
+
+These options enable listing output from the assembler.  By itself,
+`-a' requests high-level, assembly, and symbols listing.  You can use
+other letters to select specific options for the list: `-ah' requests a
+high-level language listing, `-al' requests an output-program assembly
+listing, and `-as' requests a symbol table listing.  High-level
+listings require that a compiler debugging option like `-g' be used,
+and that assembly listings (`-al') be requested also.
+
+   Use the `-ac' option to omit false conditionals from a listing.  Any
+lines which are not assembled because of a false `.if' (or `.ifdef', or
+any other conditional), or a true `.if' followed by an `.else', will be
+omitted from the listing.
+
+   Use the `-ad' option to omit debugging directives from the listing.
+
+   Once you have specified one of these options, you can further control
+listing output and its appearance using the directives `.list',
+`.nolist', `.psize', `.eject', `.title', and `.sbttl'.  The `-an'
+option turns off all forms processing.  If you do not request listing
+output with one of the `-a' options, the listing-control directives
+have no effect.
+
+   The letters after `-a' may be combined into one option, _e.g._,
+`-aln'.
+
+   Note if the assembler source is coming from the standard input (eg
+because it is being created by `gcc' and the `-pipe' command line switch
+is being used) then the listing will not contain any comments or
+preprocessor directives.  This is because the listing code buffers
+input source lines from stdin only after they have been preprocessed by
+the assembler.  This reduces memory usage and makes the code more
+efficient.
+
+
+File: as.info,  Node: alternate,  Next: D,  Prev: a,  Up: Invoking
+
+2.2 `--alternate'
+=================
+
+Begin in alternate macro mode, see *Note `.altmacro': Altmacro.
+
+
+File: as.info,  Node: D,  Next: f,  Prev: alternate,  Up: Invoking
+
+2.3 `-D'
+========
+
+This option has no effect whatsoever, but it is accepted to make it more
+likely that scripts written for other assemblers also work with `as'.
+
+
+File: as.info,  Node: f,  Next: I,  Prev: D,  Up: Invoking
+
+2.4 Work Faster: `-f'
+=====================
+
+`-f' should only be used when assembling programs written by a
+(trusted) compiler.  `-f' stops the assembler from doing whitespace and
+comment preprocessing on the input file(s) before assembling them.
+*Note Preprocessing: Preprocessing.
+
+     _Warning:_ if you use `-f' when the files actually need to be
+     preprocessed (if they contain comments, for example), `as' does
+     not work correctly.
+
+
+File: as.info,  Node: I,  Next: K,  Prev: f,  Up: Invoking
+
+2.5 `.include' Search Path: `-I' PATH
+=====================================
+
+Use this option to add a PATH to the list of directories `as' searches
+for files specified in `.include' directives (*note `.include':
+Include.).  You may use `-I' as many times as necessary to include a
+variety of paths.  The current working directory is always searched
+first; after that, `as' searches any `-I' directories in the same order
+as they were specified (left to right) on the command line.
+
+
+File: as.info,  Node: K,  Next: L,  Prev: I,  Up: Invoking
+
+2.6 Difference Tables: `-K'
+===========================
+
+`as' sometimes alters the code emitted for directives of the form
+`.word SYM1-SYM2'; *note `.word': Word.  You can use the `-K' option if
+you want a warning issued when this is done.
+
+
+File: as.info,  Node: L,  Next: listing,  Prev: K,  Up: Invoking
+
+2.7 Include Local Labels: `-L'
+==============================
+
+Labels beginning with `L' (upper case only) are called "local labels".
+*Note Symbol Names::.  Normally you do not see such labels when
+debugging, because they are intended for the use of programs (like
+compilers) that compose assembler programs, not for your notice.
+Normally both `as' and `ld' discard such labels, so you do not normally
+debug with them.
+
+   This option tells `as' to retain those `L...' symbols in the object
+file.  Usually if you do this you also tell the linker `ld' to preserve
+symbols whose names begin with `L'.
+
+   By default, a local label is any label beginning with `L', but each
+target is allowed to redefine the local label prefix.  On the HPPA
+local labels begin with `L$'.
+
+
+File: as.info,  Node: listing,  Next: M,  Prev: L,  Up: Invoking
+
+2.8 Configuring listing output: `--listing'
+===========================================
+
+The listing feature of the assembler can be enabled via the command
+line switch `-a' (*note a::).  This feature combines the input source
+file(s) with a hex dump of the corresponding locations in the output
+object file, and displays them as a listing file.  The format of this
+listing can be controlled by pseudo ops inside the assembler source
+(*note List:: *note Title:: *note Sbttl:: *note Psize:: *note Eject::)
+and also by the following switches:
+
+`--listing-lhs-width=`number''
+     Sets the maximum width, in words, of the first line of the hex
+     byte dump.  This dump appears on the left hand side of the listing
+     output.
+
+`--listing-lhs-width2=`number''
+     Sets the maximum width, in words, of any further lines of the hex
+     byte dump for a given input source line.  If this value is not
+     specified, it defaults to being the same as the value specified
+     for `--listing-lhs-width'.  If neither switch is used the default
+     is to one.
+
+`--listing-rhs-width=`number''
+     Sets the maximum width, in characters, of the source line that is
+     displayed alongside the hex dump.  The default value for this
+     parameter is 100.  The source line is displayed on the right hand
+     side of the listing output.
+
+`--listing-cont-lines=`number''
+     Sets the maximum number of continuation lines of hex dump that
+     will be displayed for a given single line of source input.  The
+     default value is 4.
+
+
+File: as.info,  Node: M,  Next: MD,  Prev: listing,  Up: Invoking
+
+2.9 Assemble in MRI Compatibility Mode: `-M'
+============================================
+
+The `-M' or `--mri' option selects MRI compatibility mode.  This
+changes the syntax and pseudo-op handling of `as' to make it compatible
+with the `ASM68K' or the `ASM960' (depending upon the configured
+target) assembler from Microtec Research.  The exact nature of the MRI
+syntax will not be documented here; see the MRI manuals for more
+information.  Note in particular that the handling of macros and macro
+arguments is somewhat different.  The purpose of this option is to
+permit assembling existing MRI assembler code using `as'.
+
+   The MRI compatibility is not complete.  Certain operations of the
+MRI assembler depend upon its object file format, and can not be
+supported using other object file formats.  Supporting these would
+require enhancing each object file format individually.  These are:
+
+   * global symbols in common section
+
+     The m68k MRI assembler supports common sections which are merged
+     by the linker.  Other object file formats do not support this.
+     `as' handles common sections by treating them as a single common
+     symbol.  It permits local symbols to be defined within a common
+     section, but it can not support global symbols, since it has no
+     way to describe them.
+
+   * complex relocations
+
+     The MRI assemblers support relocations against a negated section
+     address, and relocations which combine the start addresses of two
+     or more sections.  These are not support by other object file
+     formats.
+
+   * `END' pseudo-op specifying start address
+
+     The MRI `END' pseudo-op permits the specification of a start
+     address.  This is not supported by other object file formats.  The
+     start address may instead be specified using the `-e' option to
+     the linker, or in a linker script.
+
+   * `IDNT', `.ident' and `NAME' pseudo-ops
+
+     The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module
+     name to the output file.  This is not supported by other object
+     file formats.
+
+   * `ORG' pseudo-op
+
+     The m68k MRI `ORG' pseudo-op begins an absolute section at a given
+     address.  This differs from the usual `as' `.org' pseudo-op, which
+     changes the location within the current section.  Absolute
+     sections are not supported by other object file formats.  The
+     address of a section may be assigned within a linker script.
+
+   There are some other features of the MRI assembler which are not
+supported by `as', typically either because they are difficult or
+because they seem of little consequence.  Some of these may be
+supported in future releases.
+
+   * EBCDIC strings
+
+     EBCDIC strings are not supported.
+
+   * packed binary coded decimal
+
+     Packed binary coded decimal is not supported.  This means that the
+     `DC.P' and `DCB.P' pseudo-ops are not supported.
+
+   * `FEQU' pseudo-op
+
+     The m68k `FEQU' pseudo-op is not supported.
+
+   * `NOOBJ' pseudo-op
+
+     The m68k `NOOBJ' pseudo-op is not supported.
+
+   * `OPT' branch control options
+
+     The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL',
+     and `BRW'--are ignored.  `as' automatically relaxes all branches,
+     whether forward or backward, to an appropriate size, so these
+     options serve no purpose.
+
+   * `OPT' list control options
+
+     The following m68k `OPT' list control options are ignored: `C',
+     `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'.
+
+   * other `OPT' options
+
+     The following m68k `OPT' options are ignored: `NEST', `O', `OLD',
+     `OP', `P', `PCO', `PCR', `PCS', `R'.
+
+   * `OPT' `D' option is default
+
+     The m68k `OPT' `D' option is the default, unlike the MRI assembler.
+     `OPT NOD' may be used to turn it off.
+
+   * `XREF' pseudo-op.
+
+     The m68k `XREF' pseudo-op is ignored.
+
+   * `.debug' pseudo-op
+
+     The i960 `.debug' pseudo-op is not supported.
+
+   * `.extended' pseudo-op
+
+     The i960 `.extended' pseudo-op is not supported.
+
+   * `.list' pseudo-op.
+
+     The various options of the i960 `.list' pseudo-op are not
+     supported.
+
+   * `.optimize' pseudo-op
+
+     The i960 `.optimize' pseudo-op is not supported.
+
+   * `.output' pseudo-op
+
+     The i960 `.output' pseudo-op is not supported.
+
+   * `.setreal' pseudo-op
+
+     The i960 `.setreal' pseudo-op is not supported.
+
+
+
+File: as.info,  Node: MD,  Next: o,  Prev: M,  Up: Invoking
+
+2.10 Dependency Tracking: `--MD'
+================================
+
+`as' can generate a dependency file for the file it creates.  This file
+consists of a single rule suitable for `make' describing the
+dependencies of the main source file.
+
+   The rule is written to the file named in its argument.
+
+   This feature is used in the automatic updating of makefiles.
+
+
+File: as.info,  Node: o,  Next: R,  Prev: MD,  Up: Invoking
+
+2.11 Name the Object File: `-o'
+===============================
+
+There is always one object file output when you run `as'.  By default
+it has the name `a.out' (or `b.out', for Intel 960 targets only).  You
+use this option (which takes exactly one filename) to give the object
+file a different name.
+
+   Whatever the object file is called, `as' overwrites any existing
+file of the same name.
+
+
+File: as.info,  Node: R,  Next: statistics,  Prev: o,  Up: Invoking
+
+2.12 Join Data and Text Sections: `-R'
+======================================
+
+`-R' tells `as' to write the object file as if all data-section data
+lives in the text section.  This is only done at the very last moment:
+your binary data are the same, but data section parts are relocated
+differently.  The data section part of your object file is zero bytes
+long because all its bytes are appended to the text section.  (*Note
+Sections and Relocation: Sections.)
+
+   When you specify `-R' it would be possible to generate shorter
+address displacements (because we do not have to cross between text and
+data section).  We refrain from doing this simply for compatibility with
+older versions of `as'.  In future, `-R' may work this way.
+
+   When `as' is configured for COFF or ELF output, this option is only
+useful if you use sections named `.text' and `.data'.
+
+   `-R' is not supported for any of the HPPA targets.  Using `-R'
+generates a warning from `as'.
+
+
+File: as.info,  Node: statistics,  Next: traditional-format,  Prev: R,  Up: Invoking
+
+2.13 Display Assembly Statistics: `--statistics'
+================================================
+
+Use `--statistics' to display two statistics about the resources used by
+`as': the maximum amount of space allocated during the assembly (in
+bytes), and the total execution time taken for the assembly (in CPU
+seconds).
+
+
+File: as.info,  Node: traditional-format,  Next: v,  Prev: statistics,  Up: Invoking
+
+2.14 Compatible Output: `--traditional-format'
+==============================================
+
+For some targets, the output of `as' is different in some ways from the
+output of some existing assembler.  This switch requests `as' to use
+the traditional format instead.
+
+   For example, it disables the exception frame optimizations which
+`as' normally does by default on `gcc' output.
+
+
+File: as.info,  Node: v,  Next: W,  Prev: traditional-format,  Up: Invoking
+
+2.15 Announce Version: `-v'
+===========================
+
+You can find out what version of as is running by including the option
+`-v' (which you can also spell as `-version') on the command line.
+
+
+File: as.info,  Node: W,  Next: Z,  Prev: v,  Up: Invoking
+
+2.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings'
+======================================================================
+
+`as' should never give a warning or error message when assembling
+compiler output.  But programs written by people often cause `as' to
+give a warning that a particular assumption was made.  All such
+warnings are directed to the standard error file.
+
+   If you use the `-W' and `--no-warn' options, no warnings are issued.
+This only affects the warning messages: it does not change any
+particular of how `as' assembles your file.  Errors, which stop the
+assembly, are still reported.
+
+   If you use the `--fatal-warnings' option, `as' considers files that
+generate warnings to be in error.
+
+   You can switch these options off again by specifying `--warn', which
+causes warnings to be output as usual.
+
+
+File: as.info,  Node: Z,  Prev: W,  Up: Invoking
+
+2.17 Generate Object File in Spite of Errors: `-Z'
+==================================================
+
+After an error message, `as' normally produces no output.  If for some
+reason you are interested in object file output even after `as' gives
+an error message on your program, use the `-Z' option.  If there are
+any errors, `as' continues anyways, and writes an object file after a
+final warning message of the form `N errors, M warnings, generating bad
+object file.'
+
+
+File: as.info,  Node: Syntax,  Next: Sections,  Prev: Invoking,  Up: Top
+
+3 Syntax
+********
+
+This chapter describes the machine-independent syntax allowed in a
+source file.  `as' syntax is similar to what many other assemblers use;
+it is inspired by the BSD 4.2 assembler, except that `as' does not
+assemble Vax bit-fields.
+
+* Menu:
+
+* Preprocessing::              Preprocessing
+* Whitespace::                  Whitespace
+* Comments::                    Comments
+* Symbol Intro::                Symbols
+* Statements::                  Statements
+* Constants::                   Constants
+
+
+File: as.info,  Node: Preprocessing,  Next: Whitespace,  Up: Syntax
+
+3.1 Preprocessing
+=================
+
+The `as' internal preprocessor:
+   * adjusts and removes extra whitespace.  It leaves one space or tab
+     before the keywords on a line, and turns any other whitespace on
+     the line into a single space.
+
+   * removes all comments, replacing them with a single space, or an
+     appropriate number of newlines.
+
+   * converts character constants into the appropriate numeric values.
+
+   It does not do macro processing, include file handling, or anything
+else you may get from your C compiler's preprocessor.  You can do
+include file processing with the `.include' directive (*note
+`.include': Include.).  You can use the GNU C compiler driver to get
+other "CPP" style preprocessing by giving the input file a `.S' suffix.
+*Note Options Controlling the Kind of Output: (gcc.info)Overall
+Options.
+
+   Excess whitespace, comments, and character constants cannot be used
+in the portions of the input text that are not preprocessed.
+
+   If the first line of an input file is `#NO_APP' or if you use the
+`-f' option, whitespace and comments are not removed from the input
+file.  Within an input file, you can ask for whitespace and comment
+removal in specific portions of the by putting a line that says `#APP'
+before the text that may contain whitespace or comments, and putting a
+line that says `#NO_APP' after this text.  This feature is mainly
+intend to support `asm' statements in compilers whose output is
+otherwise free of comments and whitespace.
+
+
+File: as.info,  Node: Whitespace,  Next: Comments,  Prev: Preprocessing,  Up: Syntax
+
+3.2 Whitespace
+==============
+
+"Whitespace" is one or more blanks or tabs, in any order.  Whitespace
+is used to separate symbols, and to make programs neater for people to
+read.  Unless within character constants (*note Character Constants:
+Characters.), any whitespace means the same as exactly one space.
+
+
+File: as.info,  Node: Comments,  Next: Symbol Intro,  Prev: Whitespace,  Up: Syntax
+
+3.3 Comments
+============
+
+There are two ways of rendering comments to `as'.  In both cases the
+comment is equivalent to one space.
+
+   Anything from `/*' through the next `*/' is a comment.  This means
+you may not nest these comments.
+
+     /*
+       The only way to include a newline ('\n') in a comment
+       is to use this sort of comment.
+     */
+
+     /* This sort of comment does not nest. */
+
+   Anything from the "line comment" character to the next newline is
+considered a comment and is ignored.  The line comment character is `;'
+on the ARC; `@' on the ARM; `;' for the H8/300 family; `;' for the HPPA;
+`#' on the i386 and x86-64; `#' on the i960; `;' for the PDP-11; `;'
+for picoJava; `#' for Motorola PowerPC; `!' for the Renesas / SuperH SH;
+`!' on the SPARC; `#' on the ip2k; `#' on the m32c; `#' on the m32r;
+`|' on the 680x0; `#' on the 68HC11 and 68HC12; `#' on the Vax; `;' for
+the Z80; `!' for the Z8000; `#' on the V850; `#' for Xtensa systems;
+see *Note Machine Dependencies::.
+
+   On some machines there are two different line comment characters.
+One character only begins a comment if it is the first non-whitespace
+character on a line, while the other always begins a comment.
+
+   The V850 assembler also supports a double dash as starting a comment
+that extends to the end of the line.
+
+   `--';
+
+   To be compatible with past assemblers, lines that begin with `#'
+have a special interpretation.  Following the `#' should be an absolute
+expression (*note Expressions::): the logical line number of the _next_
+line.  Then a string (*note Strings: Strings.) is allowed: if present
+it is a new logical file name.  The rest of the line, if any, should be
+whitespace.
+
+   If the first non-whitespace characters on the line are not numeric,
+the line is ignored.  (Just like a comment.)
+
+                               # This is an ordinary comment.
+     # 42-6 "new_file_name"    # New logical file name
+                               # This is logical line # 36.
+   This feature is deprecated, and may disappear from future versions
+of `as'.
+
+
+File: as.info,  Node: Symbol Intro,  Next: Statements,  Prev: Comments,  Up: Syntax
+
+3.4 Symbols
+===========
+
+A "symbol" is one or more characters chosen from the set of all letters
+(both upper and lower case), digits and the three characters `_.$'.  On
+most machines, you can also use `$' in symbol names; exceptions are
+noted in *Note Machine Dependencies::.  No symbol may begin with a
+digit.  Case is significant.  There is no length limit: all characters
+are significant.  Symbols are delimited by characters not in that set,
+or by the beginning of a file (since the source program must end with a
+newline, the end of a file is not a possible symbol delimiter).  *Note
+Symbols::.  
+
+
+File: as.info,  Node: Statements,  Next: Constants,  Prev: Symbol Intro,  Up: Syntax
+
+3.5 Statements
+==============
+
+A "statement" ends at a newline character (`\n') or line separator
+character.  (The line separator is usually `;', unless this conflicts
+with the comment character; *note Machine Dependencies::.)  The newline
+or separator character is considered part of the preceding statement.
+Newlines and separators within character constants are an exception:
+they do not end statements.
+
+It is an error to end any statement with end-of-file:  the last
+character of any input file should be a newline.
+
+   An empty statement is allowed, and may include whitespace.  It is
+ignored.
+
+   A statement begins with zero or more labels, optionally followed by a
+key symbol which determines what kind of statement it is.  The key
+symbol determines the syntax of the rest of the statement.  If the
+symbol begins with a dot `.' then the statement is an assembler
+directive: typically valid for any computer.  If the symbol begins with
+a letter the statement is an assembly language "instruction": it
+assembles into a machine language instruction.  Different versions of
+`as' for different computers recognize different instructions.  In
+fact, the same symbol may represent a different instruction in a
+different computer's assembly language.
+
+   A label is a symbol immediately followed by a colon (`:').
+Whitespace before a label or after a colon is permitted, but you may not
+have whitespace between a label's symbol and its colon. *Note Labels::.
+
+   For HPPA targets, labels need not be immediately followed by a
+colon, but the definition of a label must begin in column zero.  This
+also implies that only one label may be defined on each line.
+
+     label:     .directive    followed by something
+     another_label:           # This is an empty statement.
+                instruction   operand_1, operand_2, ...
+
+
+File: as.info,  Node: Constants,  Prev: Statements,  Up: Syntax
+
+3.6 Constants
+=============
+
+A constant is a number, written so that its value is known by
+inspection, without knowing any context.  Like this:
+     .byte  74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value.
+     .ascii "Ring the bell\7"                  # A string constant.
+     .octa  0x123456789abcdef0123456789ABCDEF0 # A bignum.
+     .float 0f-314159265358979323846264338327\
+     95028841971.693993751E-40                 # - pi, a flonum.
+
+* Menu:
+
+* Characters::                  Character Constants
+* Numbers::                     Number Constants
+
+
+File: as.info,  Node: Characters,  Next: Numbers,  Up: Constants
+
+3.6.1 Character Constants
+-------------------------
+
+There are two kinds of character constants.  A "character" stands for
+one character in one byte and its value may be used in numeric
+expressions.  String constants (properly called string _literals_) are
+potentially many bytes and their values may not be used in arithmetic
+expressions.
+
+* Menu:
+
+* Strings::                     Strings
+* Chars::                       Characters
+
+
+File: as.info,  Node: Strings,  Next: Chars,  Up: Characters
+
+3.6.1.1 Strings
+...............
+
+A "string" is written between double-quotes.  It may contain
+double-quotes or null characters.  The way to get special characters
+into a string is to "escape" these characters: precede them with a
+backslash `\' character.  For example `\\' represents one backslash:
+the first `\' is an escape which tells `as' to interpret the second
+character literally as a backslash (which prevents `as' from
+recognizing the second `\' as an escape character).  The complete list
+of escapes follows.
+
+`\b'
+     Mnemonic for backspace; for ASCII this is octal code 010.
+
+`\f'
+     Mnemonic for FormFeed; for ASCII this is octal code 014.
+
+`\n'
+     Mnemonic for newline; for ASCII this is octal code 012.
+
+`\r'
+     Mnemonic for carriage-Return; for ASCII this is octal code 015.
+
+`\t'
+     Mnemonic for horizontal Tab; for ASCII this is octal code 011.
+
+`\ DIGIT DIGIT DIGIT'
+     An octal character code.  The numeric code is 3 octal digits.  For
+     compatibility with other Unix systems, 8 and 9 are accepted as
+     digits: for example, `\008' has the value 010, and `\009' the
+     value 011.
+
+`\`x' HEX-DIGITS...'
+     A hex character code.  All trailing hex digits are combined.
+     Either upper or lower case `x' works.
+
+`\\'
+     Represents one `\' character.
+
+`\"'
+     Represents one `"' character.  Needed in strings to represent this
+     character, because an unescaped `"' would end the string.
+
+`\ ANYTHING-ELSE'
+     Any other character when escaped by `\' gives a warning, but
+     assembles as if the `\' was not present.  The idea is that if you
+     used an escape sequence you clearly didn't want the literal
+     interpretation of the following character.  However `as' has no
+     other interpretation, so `as' knows it is giving you the wrong
+     code and warns you of the fact.
+
+   Which characters are escapable, and what those escapes represent,
+varies widely among assemblers.  The current set is what we think the
+BSD 4.2 assembler recognizes, and is a subset of what most C compilers
+recognize.  If you are in doubt, do not use an escape sequence.
+
+
+File: as.info,  Node: Chars,  Prev: Strings,  Up: Characters
+
+3.6.1.2 Characters
+..................
+
+A single character may be written as a single quote immediately
+followed by that character.  The same escapes apply to characters as to
+strings.  So if you want to write the character backslash, you must
+write `'\\' where the first `\' escapes the second `\'.  As you can
+see, the quote is an acute accent, not a grave accent.  A newline
+immediately following an acute accent is taken as a literal character
+and does not count as the end of a statement.  The value of a character
+constant in a numeric expression is the machine's byte-wide code for
+that character.  `as' assumes your character code is ASCII: `'A' means
+65, `'B' means 66, and so on.
+
+
+File: as.info,  Node: Numbers,  Prev: Characters,  Up: Constants
+
+3.6.2 Number Constants
+----------------------
+
+`as' distinguishes three kinds of numbers according to how they are
+stored in the target machine.  _Integers_ are numbers that would fit
+into an `int' in the C language.  _Bignums_ are integers, but they are
+stored in more than 32 bits.  _Flonums_ are floating point numbers,
+described below.
+
+* Menu:
+
+* Integers::                    Integers
+* Bignums::                     Bignums
+* Flonums::                     Flonums
+
+
+File: as.info,  Node: Integers,  Next: Bignums,  Up: Numbers
+
+3.6.2.1 Integers
+................
+
+A binary integer is `0b' or `0B' followed by zero or more of the binary
+digits `01'.
+
+   An octal integer is `0' followed by zero or more of the octal digits
+(`01234567').
+
+   A decimal integer starts with a non-zero digit followed by zero or
+more digits (`0123456789').
+
+   A hexadecimal integer is `0x' or `0X' followed by one or more
+hexadecimal digits chosen from `0123456789abcdefABCDEF'.
+
+   Integers have the usual values.  To denote a negative integer, use
+the prefix operator `-' discussed under expressions (*note Prefix
+Operators: Prefix Ops.).
+
+
+File: as.info,  Node: Bignums,  Next: Flonums,  Prev: Integers,  Up: Numbers
+
+3.6.2.2 Bignums
+...............
+
+A "bignum" has the same syntax and semantics as an integer except that
+the number (or its negative) takes more than 32 bits to represent in
+binary.  The distinction is made because in some places integers are
+permitted while bignums are not.
+
+
+File: as.info,  Node: Flonums,  Prev: Bignums,  Up: Numbers
+
+3.6.2.3 Flonums
+...............
+
+A "flonum" represents a floating point number.  The translation is
+indirect: a decimal floating point number from the text is converted by
+`as' to a generic binary floating point number of more than sufficient
+precision.  This generic floating point number is converted to a
+particular computer's floating point format (or formats) by a portion
+of `as' specialized to that computer.
+
+   A flonum is written by writing (in order)
+   * The digit `0'.  (`0' is optional on the HPPA.)
+
+   * A letter, to tell `as' the rest of the number is a flonum.  `e' is
+     recommended.  Case is not important.
+
+     On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the
+     letter must be one of the letters `DFPRSX' (in upper or lower
+     case).
+
+     On the ARC, the letter must be one of the letters `DFRS' (in upper
+     or lower case).
+
+     On the Intel 960 architecture, the letter must be one of the
+     letters `DFT' (in upper or lower case).
+
+     On the HPPA architecture, the letter must be `E' (upper case only).
+
+   * An optional sign: either `+' or `-'.
+
+   * An optional "integer part": zero or more decimal digits.
+
+   * An optional "fractional part": `.' followed by zero or more
+     decimal digits.
+
+   * An optional exponent, consisting of:
+
+        * An `E' or `e'.
+
+        * Optional sign: either `+' or `-'.
+
+        * One or more decimal digits.
+
+
+   At least one of the integer part or the fractional part must be
+present.  The floating point number has the usual base-10 value.
+
+   `as' does all processing using integers.  Flonums are computed
+independently of any floating point hardware in the computer running
+`as'.
+
+
+File: as.info,  Node: Sections,  Next: Symbols,  Prev: Syntax,  Up: Top
+
+4 Sections and Relocation
+*************************
+
+* Menu:
+
+* Secs Background::             Background
+* Ld Sections::                 Linker Sections
+* As Sections::                 Assembler Internal Sections
+* Sub-Sections::                Sub-Sections
+* bss::                         bss Section
+
+
+File: as.info,  Node: Secs Background,  Next: Ld Sections,  Up: Sections
+
+4.1 Background
+==============
+
+Roughly, a section is a range of addresses, with no gaps; all data "in"
+those addresses is treated the same for some particular purpose.  For
+example there may be a "read only" section.
+
+   The linker `ld' reads many object files (partial programs) and
+combines their contents to form a runnable program.  When `as' emits an
+object file, the partial program is assumed to start at address 0.
+`ld' assigns the final addresses for the partial program, so that
+different partial programs do not overlap.  This is actually an
+oversimplification, but it suffices to explain how `as' uses sections.
+
+   `ld' moves blocks of bytes of your program to their run-time
+addresses.  These blocks slide to their run-time addresses as rigid
+units; their length does not change and neither does the order of bytes
+within them.  Such a rigid unit is called a _section_.  Assigning
+run-time addresses to sections is called "relocation".  It includes the
+task of adjusting mentions of object-file addresses so they refer to
+the proper run-time addresses.  For the H8/300, and for the Renesas /
+SuperH SH, `as' pads sections if needed to ensure they end on a word
+(sixteen bit) boundary.
+
+   An object file written by `as' has at least three sections, any of
+which may be empty.  These are named "text", "data" and "bss" sections.
+
+   When it generates COFF or ELF output, `as' can also generate
+whatever other named sections you specify using the `.section'
+directive (*note `.section': Section.).  If you do not use any
+directives that place output in the `.text' or `.data' sections, these
+sections still exist, but are empty.
+
+   When `as' generates SOM or ELF output for the HPPA, `as' can also
+generate whatever other named sections you specify using the `.space'
+and `.subspace' directives.  See `HP9000 Series 800 Assembly Language
+Reference Manual' (HP 92432-90001) for details on the `.space' and
+`.subspace' assembler directives.
+
+   Additionally, `as' uses different names for the standard text, data,
+and bss sections when generating SOM output.  Program text is placed
+into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'.
+
+   Within the object file, the text section starts at address `0', the
+data section follows, and the bss section follows the data section.
+
+   When generating either SOM or ELF output files on the HPPA, the text
+section starts at address `0', the data section at address `0x4000000',
+and the bss section follows the data section.
+
+   To let `ld' know which data changes when the sections are relocated,
+and how to change that data, `as' also writes to the object file
+details of the relocation needed.  To perform relocation `ld' must
+know, each time an address in the object file is mentioned:
+   * Where in the object file is the beginning of this reference to an
+     address?
+
+   * How long (in bytes) is this reference?
+
+   * Which section does the address refer to?  What is the numeric
+     value of
+          (ADDRESS) - (START-ADDRESS OF SECTION)?
+
+   * Is the reference to an address "Program-Counter relative"?
+
+   In fact, every address `as' ever uses is expressed as
+     (SECTION) + (OFFSET INTO SECTION)
+   Further, most expressions `as' computes have this section-relative
+nature.  (For some object formats, such as SOM for the HPPA, some
+expressions are symbol-relative instead.)
+
+   In this manual we use the notation {SECNAME N} to mean "offset N
+into section SECNAME."
+
+   Apart from text, data and bss sections you need to know about the
+"absolute" section.  When `ld' mixes partial programs, addresses in the
+absolute section remain unchanged.  For example, address `{absolute 0}'
+is "relocated" to run-time address 0 by `ld'.  Although the linker
+never arranges two partial programs' data sections with overlapping
+addresses after linking, _by definition_ their absolute sections must
+overlap.  Address `{absolute 239}' in one part of a program is always
+the same address when the program is running as address `{absolute
+239}' in any other part of the program.
+
+   The idea of sections is extended to the "undefined" section.  Any
+address whose section is unknown at assembly time is by definition
+rendered {undefined U}--where U is filled in later.  Since numbers are
+always defined, the only way to generate an undefined address is to
+mention an undefined symbol.  A reference to a named common block would
+be such a symbol: its value is unknown at assembly time so it has
+section _undefined_.
+
+   By analogy the word _section_ is used to describe groups of sections
+in the linked program.  `ld' puts all partial programs' text sections
+in contiguous addresses in the linked program.  It is customary to
+refer to the _text section_ of a program, meaning all the addresses of
+all partial programs' text sections.  Likewise for data and bss
+sections.
+
+   Some sections are manipulated by `ld'; others are invented for use
+of `as' and have no meaning except during assembly.
+
+
+File: as.info,  Node: Ld Sections,  Next: As Sections,  Prev: Secs Background,  Up: Sections
+
+4.2 Linker Sections
+===================
+
+`ld' deals with just four kinds of sections, summarized below.
+
+*named sections*
+*text section*
+*data section*
+     These sections hold your program.  `as' and `ld' treat them as
+     separate but equal sections.  Anything you can say of one section
+     is true of another.  When the program is running, however, it is
+     customary for the text section to be unalterable.  The text
+     section is often shared among processes: it contains instructions,
+     constants and the like.  The data section of a running program is
+     usually alterable: for example, C variables would be stored in the
+     data section.
+
+*bss section*
+     This section contains zeroed bytes when your program begins
+     running.  It is used to hold uninitialized variables or common
+     storage.  The length of each partial program's bss section is
+     important, but because it starts out containing zeroed bytes there
+     is no need to store explicit zero bytes in the object file.  The
+     bss section was invented to eliminate those explicit zeros from
+     object files.
+
+*absolute section*
+     Address 0 of this section is always "relocated" to runtime address
+     0.  This is useful if you want to refer to an address that `ld'
+     must not change when relocating.  In this sense we speak of
+     absolute addresses being "unrelocatable": they do not change
+     during relocation.
+
+*undefined section*
+     This "section" is a catch-all for address references to objects
+     not in the preceding sections.
+
+   An idealized example of three relocatable sections follows.  The
+example uses the traditional section names `.text' and `.data'.  Memory
+addresses are on the horizontal axis.
+
+                           +-----+----+--+
+     partial program # 1:  |ttttt|dddd|00|
+                           +-----+----+--+
+
+                           text   data bss
+                           seg.   seg. seg.
+
+                           +---+---+---+
+     partial program # 2:  |TTT|DDD|000|
+                           +---+---+---+
+
+                           +--+---+-----+--+----+---+-----+~~
+     linked program:       |  |TTT|ttttt|  |dddd|DDD|00000|
+                           +--+---+-----+--+----+---+-----+~~
+
+         addresses:        0 ...
+
+
+File: as.info,  Node: As Sections,  Next: Sub-Sections,  Prev: Ld Sections,  Up: Sections
+
+4.3 Assembler Internal Sections
+===============================
+
+These sections are meant only for the internal use of `as'.  They have
+no meaning at run-time.  You do not really need to know about these
+sections for most purposes; but they can be mentioned in `as' warning
+messages, so it might be helpful to have an idea of their meanings to
+`as'.  These sections are used to permit the value of every expression
+in your assembly language program to be a section-relative address.
+
+ASSEMBLER-INTERNAL-LOGIC-ERROR!
+     An internal assembler logic error has been found.  This means
+     there is a bug in the assembler.
+
+expr section
+     The assembler stores complex expression internally as combinations
+     of symbols.  When it needs to represent an expression as a symbol,
+     it puts it in the expr section.
+
+
+File: as.info,  Node: Sub-Sections,  Next: bss,  Prev: As Sections,  Up: Sections
+
+4.4 Sub-Sections
+================
+
+Assembled bytes conventionally fall into two sections: text and data.
+You may have separate groups of data in named sections that you want to
+end up near to each other in the object file, even though they are not
+contiguous in the assembler source.  `as' allows you to use
+"subsections" for this purpose.  Within each section, there can be
+numbered subsections with values from 0 to 8192.  Objects assembled
+into the same subsection go into the object file together with other
+objects in the same subsection.  For example, a compiler might want to
+store constants in the text section, but might not want to have them
+interspersed with the program being assembled.  In this case, the
+compiler could issue a `.text 0' before each section of code being
+output, and a `.text 1' before each group of constants being output.
+
+Subsections are optional.  If you do not use subsections, everything
+goes in subsection number zero.
+
+   Each subsection is zero-padded up to a multiple of four bytes.
+(Subsections may be padded a different amount on different flavors of
+`as'.)
+
+   Subsections appear in your object file in numeric order, lowest
+numbered to highest.  (All this to be compatible with other people's
+assemblers.)  The object file contains no representation of
+subsections; `ld' and other programs that manipulate object files see
+no trace of them.  They just see all your text subsections as a text
+section, and all your data subsections as a data section.
+
+   To specify which subsection you want subsequent statements assembled
+into, use a numeric argument to specify it, in a `.text EXPRESSION' or
+a `.data EXPRESSION' statement.  When generating COFF output, you can
+also use an extra subsection argument with arbitrary named sections:
+`.section NAME, EXPRESSION'.  When generating ELF output, you can also
+use the `.subsection' directive (*note SubSection::) to specify a
+subsection: `.subsection EXPRESSION'.  EXPRESSION should be an absolute
+expression.  (*Note Expressions::.)  If you just say `.text' then
+`.text 0' is assumed.  Likewise `.data' means `.data 0'.  Assembly
+begins in `text 0'.  For instance:
+     .text 0     # The default subsection is text 0 anyway.
+     .ascii "This lives in the first text subsection. *"
+     .text 1
+     .ascii "But this lives in the second text subsection."
+     .data 0
+     .ascii "This lives in the data section,"
+     .ascii "in the first data subsection."
+     .text 0
+     .ascii "This lives in the first text section,"
+     .ascii "immediately following the asterisk (*)."
+
+   Each section has a "location counter" incremented by one for every
+byte assembled into that section.  Because subsections are merely a
+convenience restricted to `as' there is no concept of a subsection
+location counter.  There is no way to directly manipulate a location
+counter--but the `.align' directive changes it, and any label
+definition captures its current value.  The location counter of the
+section where statements are being assembled is said to be the "active"
+location counter.
+
+
+File: as.info,  Node: bss,  Prev: Sub-Sections,  Up: Sections
+
+4.5 bss Section
+===============
+
+The bss section is used for local common variable storage.  You may
+allocate address space in the bss section, but you may not dictate data
+to load into it before your program executes.  When your program starts
+running, all the contents of the bss section are zeroed bytes.
+
+   The `.lcomm' pseudo-op defines a symbol in the bss section; see
+*Note `.lcomm': Lcomm.
+
+   The `.comm' pseudo-op may be used to declare a common symbol, which
+is another form of uninitialized symbol; see *Note `.comm': Comm.
+
+   When assembling for a target which supports multiple sections, such
+as ELF or COFF, you may switch into the `.bss' section and define
+symbols as usual; see *Note `.section': Section.  You may only assemble
+zero values into the section.  Typically the section will only contain
+symbol definitions and `.skip' directives (*note `.skip': Skip.).
+
+
+File: as.info,  Node: Symbols,  Next: Expressions,  Prev: Sections,  Up: Top
+
+5 Symbols
+*********
+
+Symbols are a central concept: the programmer uses symbols to name
+things, the linker uses symbols to link, and the debugger uses symbols
+to debug.
+
+     _Warning:_ `as' does not place symbols in the object file in the
+     same order they were declared.  This may break some debuggers.
+
+* Menu:
+
+* Labels::                      Labels
+* Setting Symbols::             Giving Symbols Other Values
+* Symbol Names::                Symbol Names
+* Dot::                         The Special Dot Symbol
+* Symbol Attributes::           Symbol Attributes
+
+
+File: as.info,  Node: Labels,  Next: Setting Symbols,  Up: Symbols
+
+5.1 Labels
+==========
+
+A "label" is written as a symbol immediately followed by a colon `:'.
+The symbol then represents the current value of the active location
+counter, and is, for example, a suitable instruction operand.  You are
+warned if you use the same symbol to represent two different locations:
+the first definition overrides any other definitions.
+
+   On the HPPA, the usual form for a label need not be immediately
+followed by a colon, but instead must start in column zero.  Only one
+label may be defined on a single line.  To work around this, the HPPA
+version of `as' also provides a special directive `.label' for defining
+labels more flexibly.
+
+
+File: as.info,  Node: Setting Symbols,  Next: Symbol Names,  Prev: Labels,  Up: Symbols
+
+5.2 Giving Symbols Other Values
+===============================
+
+A symbol can be given an arbitrary value by writing a symbol, followed
+by an equals sign `=', followed by an expression (*note Expressions::).
+This is equivalent to using the `.set' directive.  *Note `.set': Set.
+In the same way, using a double equals sign `='`=' here represents an
+equivalent of the `.eqv' directive.  *Note `.eqv': Eqv.
+
+
+File: as.info,  Node: Symbol Names,  Next: Dot,  Prev: Setting Symbols,  Up: Symbols
+
+5.3 Symbol Names
+================
+
+Symbol names begin with a letter or with one of `._'.  On most
+machines, you can also use `$' in symbol names; exceptions are noted in
+*Note Machine Dependencies::.  That character may be followed by any
+string of digits, letters, dollar signs (unless otherwise noted in
+*Note Machine Dependencies::), and underscores.
+
+Case of letters is significant: `foo' is a different symbol name than
+`Foo'.
+
+   Each symbol has exactly one name.  Each name in an assembly language
+program refers to exactly one symbol.  You may use that symbol name any
+number of times in a program.
+
+Local Symbol Names
+------------------
+
+Local symbols help compilers and programmers use names temporarily.
+They create symbols which are guaranteed to be unique over the entire
+scope of the input source code and which can be referred to by a simple
+notation.  To define a local symbol, write a label of the form `N:'
+(where N represents any positive integer).  To refer to the most recent
+previous definition of that symbol write `Nb', using the same number as
+when you defined the label.  To refer to the next definition of a local
+label, write `Nf'-- The `b' stands for"backwards" and the `f' stands
+for "forwards".
+
+   There is no restriction on how you can use these labels, and you can
+reuse them too.  So that it is possible to repeatedly define the same
+local label (using the same number `N'), although you can only refer to
+the most recently defined local label of that number (for a backwards
+reference) or the next definition of a specific local label for a
+forward reference.  It is also worth noting that the first 10 local
+labels (`0:'...`9:') are implemented in a slightly more efficient
+manner than the others.
+
+   Here is an example:
+
+     1:        branch 1f
+     2:        branch 1b
+     1:        branch 2f
+     2:        branch 1b
+
+   Which is the equivalent of:
+
+     label_1:  branch label_3
+     label_2:  branch label_1
+     label_3:  branch label_4
+     label_4:  branch label_3
+
+   Local symbol names are only a notational device.  They are
+immediately transformed into more conventional symbol names before the
+assembler uses them.  The symbol names stored in the symbol table,
+appearing in error messages and optionally emitted to the object file.
+The names are constructed using these parts:
+
+`L'
+     All local labels begin with `L'. Normally both `as' and `ld'
+     forget symbols that start with `L'. These labels are used for
+     symbols you are never intended to see.  If you use the `-L' option
+     then `as' retains these symbols in the object file. If you also
+     instruct `ld' to retain these symbols, you may use them in
+     debugging.
+
+`NUMBER'
+     This is the number that was used in the local label definition.
+     So if the label is written `55:' then the number is `55'.
+
+`C-B'
+     This unusual character is included so you do not accidentally
+     invent a symbol of the same name.  The character has ASCII value
+     of `\002' (control-B).
+
+`_ordinal number_'
+     This is a serial number to keep the labels distinct.  The first
+     definition of `0:' gets the number `1'.  The 15th definition of
+     `0:' gets the number `15', and so on.  Likewise the first
+     definition of `1:' gets the number `1' and its 15th defintion gets
+     `15' as well.
+
+   So for example, the first `1:' is named `L1C-B1', the 44th `3:' is
+named `L3C-B44'.
+
+Dollar Local Labels
+-------------------
+
+`as' also supports an even more local form of local labels called
+dollar labels.  These labels go out of scope (ie they become undefined)
+as soon as a non-local label is defined.  Thus they remain valid for
+only a small region of the input source code.  Normal local labels, by
+contrast, remain in scope for the entire file, or until they are
+redefined by another occurrence of the same local label.
+
+   Dollar labels are defined in exactly the same way as ordinary local
+labels, except that instead of being terminated by a colon, they are
+terminated by a dollar sign.  eg `55$'.
+
+   They can also be distinguished from ordinary local labels by their
+transformed name which uses ASCII character `\001' (control-A) as the
+magic character to distinguish them from ordinary labels.  Thus the 5th
+defintion of `6$' is named `L6C-A5'.
+
+
+File: as.info,  Node: Dot,  Next: Symbol Attributes,  Prev: Symbol Names,  Up: Symbols
+
+5.4 The Special Dot Symbol
+==========================
+
+The special symbol `.' refers to the current address that `as' is
+assembling into.  Thus, the expression `melvin: .long .' defines
+`melvin' to contain its own address.  Assigning a value to `.' is
+treated the same as a `.org' directive.  Thus, the expression `.=.+4'
+is the same as saying `.space 4'.
+
+
+File: as.info,  Node: Symbol Attributes,  Prev: Dot,  Up: Symbols
+
+5.5 Symbol Attributes
+=====================
+
+Every symbol has, as well as its name, the attributes "Value" and
+"Type".  Depending on output format, symbols can also have auxiliary
+attributes.
+
+   If you use a symbol without defining it, `as' assumes zero for all
+these attributes, and probably won't warn you.  This makes the symbol
+an externally defined symbol, which is generally what you would want.
+
+* Menu:
+
+* Symbol Value::                Value
+* Symbol Type::                 Type
+
+
+* a.out Symbols::               Symbol Attributes: `a.out'
+
+* COFF Symbols::                Symbol Attributes for COFF
+
+* SOM Symbols::                Symbol Attributes for SOM
+
+
+File: as.info,  Node: Symbol Value,  Next: Symbol Type,  Up: Symbol Attributes
+
+5.5.1 Value
+-----------
+
+The value of a symbol is (usually) 32 bits.  For a symbol which labels a
+location in the text, data, bss or absolute sections the value is the
+number of addresses from the start of that section to the label.
+Naturally for text, data and bss sections the value of a symbol changes
+as `ld' changes section base addresses during linking.  Absolute
+symbols' values do not change during linking: that is why they are
+called absolute.
+
+   The value of an undefined symbol is treated in a special way.  If it
+is 0 then the symbol is not defined in this assembler source file, and
+`ld' tries to determine its value from other files linked into the same
+program.  You make this kind of symbol simply by mentioning a symbol
+name without defining it.  A non-zero value represents a `.comm' common
+declaration.  The value is how much common storage to reserve, in bytes
+(addresses).  The symbol refers to the first address of the allocated
+storage.
+
+
+File: as.info,  Node: Symbol Type,  Next: a.out Symbols,  Prev: Symbol Value,  Up: Symbol Attributes
+
+5.5.2 Type
+----------
+
+The type attribute of a symbol contains relocation (section)
+information, any flag settings indicating that a symbol is external, and
+(optionally), other information for linkers and debuggers.  The exact
+format depends on the object-code output format in use.
+
+
+File: as.info,  Node: a.out Symbols,  Next: COFF Symbols,  Prev: Symbol Type,  Up: Symbol Attributes
+
+5.5.3 Symbol Attributes: `a.out'
+--------------------------------
+
+* Menu:
+
+* Symbol Desc::                 Descriptor
+* Symbol Other::                Other
+
+
+File: as.info,  Node: Symbol Desc,  Next: Symbol Other,  Up: a.out Symbols
+
+5.5.3.1 Descriptor
+..................
+
+This is an arbitrary 16-bit value.  You may establish a symbol's
+descriptor value by using a `.desc' statement (*note `.desc': Desc.).
+A descriptor value means nothing to `as'.
+
+
+File: as.info,  Node: Symbol Other,  Prev: Symbol Desc,  Up: a.out Symbols
+
+5.5.3.2 Other
+.............
+
+This is an arbitrary 8-bit value.  It means nothing to `as'.
+
+
+File: as.info,  Node: COFF Symbols,  Next: SOM Symbols,  Prev: a.out Symbols,  Up: Symbol Attributes
+
+5.5.4 Symbol Attributes for COFF
+--------------------------------
+
+The COFF format supports a multitude of auxiliary symbol attributes;
+like the primary symbol attributes, they are set between `.def' and
+`.endef' directives.
+
+5.5.4.1 Primary Attributes
+..........................
+
+The symbol name is set with `.def'; the value and type, respectively,
+with `.val' and `.type'.
+
+5.5.4.2 Auxiliary Attributes
+............................
+
+The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and
+`.weak' can generate auxiliary symbol table information for COFF.
+
+
+File: as.info,  Node: SOM Symbols,  Prev: COFF Symbols,  Up: Symbol Attributes
+
+5.5.5 Symbol Attributes for SOM
+-------------------------------
+
+The SOM format for the HPPA supports a multitude of symbol attributes
+set with the `.EXPORT' and `.IMPORT' directives.
+
+   The attributes are described in `HP9000 Series 800 Assembly Language
+Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT'
+assembler directive documentation.
+
+
+File: as.info,  Node: Expressions,  Next: Pseudo Ops,  Prev: Symbols,  Up: Top
+
+6 Expressions
+*************
+
+An "expression" specifies an address or numeric value.  Whitespace may
+precede and/or follow an expression.
+
+   The result of an expression must be an absolute number, or else an
+offset into a particular section.  If an expression is not absolute,
+and there is not enough information when `as' sees the expression to
+know its section, a second pass over the source program might be
+necessary to interpret the expression--but the second pass is currently
+not implemented.  `as' aborts with an error message in this situation.
+
+* Menu:
+
+* Empty Exprs::                 Empty Expressions
+* Integer Exprs::               Integer Expressions
+
+
+File: as.info,  Node: Empty Exprs,  Next: Integer Exprs,  Up: Expressions
+
+6.1 Empty Expressions
+=====================
+
+An empty expression has no value: it is just whitespace or null.
+Wherever an absolute expression is required, you may omit the
+expression, and `as' assumes a value of (absolute) 0.  This is
+compatible with other assemblers.
+
+
+File: as.info,  Node: Integer Exprs,  Prev: Empty Exprs,  Up: Expressions
+
+6.2 Integer Expressions
+=======================
+
+An "integer expression" is one or more _arguments_ delimited by
+_operators_.
+
+* Menu:
+
+* Arguments::                   Arguments
+* Operators::                   Operators
+* Prefix Ops::                  Prefix Operators
+* Infix Ops::                   Infix Operators
+
+
+File: as.info,  Node: Arguments,  Next: Operators,  Up: Integer Exprs
+
+6.2.1 Arguments
+---------------
+
+"Arguments" are symbols, numbers or subexpressions.  In other contexts
+arguments are sometimes called "arithmetic operands".  In this manual,
+to avoid confusing them with the "instruction operands" of the machine
+language, we use the term "argument" to refer to parts of expressions
+only, reserving the word "operand" to refer only to machine instruction
+operands.
+
+   Symbols are evaluated to yield {SECTION NNN} where SECTION is one of
+text, data, bss, absolute, or undefined.  NNN is a signed, 2's
+complement 32 bit integer.
+
+   Numbers are usually integers.
+
+   A number can be a flonum or bignum.  In this case, you are warned
+that only the low order 32 bits are used, and `as' pretends these 32
+bits are an integer.  You may write integer-manipulating instructions
+that act on exotic constants, compatible with other assemblers.
+
+   Subexpressions are a left parenthesis `(' followed by an integer
+expression, followed by a right parenthesis `)'; or a prefix operator
+followed by an argument.
+
+
+File: as.info,  Node: Operators,  Next: Prefix Ops,  Prev: Arguments,  Up: Integer Exprs
+
+6.2.2 Operators
+---------------
+
+"Operators" are arithmetic functions, like `+' or `%'.  Prefix
+operators are followed by an argument.  Infix operators appear between
+their arguments.  Operators may be preceded and/or followed by
+whitespace.
+
+
+File: as.info,  Node: Prefix Ops,  Next: Infix Ops,  Prev: Operators,  Up: Integer Exprs
+
+6.2.3 Prefix Operator
+---------------------
+
+`as' has the following "prefix operators".  They each take one
+argument, which must be absolute.
+
+`-'
+     "Negation".  Two's complement negation.
+
+`~'
+     "Complementation".  Bitwise not.
+
+
+File: as.info,  Node: Infix Ops,  Prev: Prefix Ops,  Up: Integer Exprs
+
+6.2.4 Infix Operators
+---------------------
+
+"Infix operators" take two arguments, one on either side.  Operators
+have precedence, but operations with equal precedence are performed left
+to right.  Apart from `+' or `-', both arguments must be absolute, and
+the result is absolute.
+
+  1. Highest Precedence
+
+    `*'
+          "Multiplication".
+
+    `/'
+          "Division".  Truncation is the same as the C operator `/'
+
+    `%'
+          "Remainder".
+
+    `<<'
+          "Shift Left".  Same as the C operator `<<'.
+
+    `>>'
+          "Shift Right".  Same as the C operator `>>'.
+
+  2. Intermediate precedence
+
+    `|'
+          "Bitwise Inclusive Or".
+
+    `&'
+          "Bitwise And".
+
+    `^'
+          "Bitwise Exclusive Or".
+
+    `!'
+          "Bitwise Or Not".
+
+  3. Low Precedence
+
+    `+'
+          "Addition".  If either argument is absolute, the result has
+          the section of the other argument.  You may not add together
+          arguments from different sections.
+
+    `-'
+          "Subtraction".  If the right argument is absolute, the result
+          has the section of the left argument.  If both arguments are
+          in the same section, the result is absolute.  You may not
+          subtract arguments from different sections.
+
+    `=='
+          "Is Equal To"
+
+    `<>'
+    `!='
+          "Is Not Equal To"
+
+    `<'
+          "Is Less Than"
+
+    `>'
+          "Is Greater Than"
+
+    `>='
+          "Is Greater Than Or Equal To"
+
+    `<='
+          "Is Less Than Or Equal To"
+
+          The comparison operators can be used as infix operators.  A
+          true results has a value of -1 whereas a false result has a
+          value of 0.   Note, these operators perform signed
+          comparisons.
+
+  4. Lowest Precedence
+
+    `&&'
+          "Logical And".
+
+    `||'
+          "Logical Or".
+
+          These two logical operations can be used to combine the
+          results of sub expressions.  Note, unlike the comparison
+          operators a true result returns a value of 1 but a false
+          results does still return 0.  Also note that the logical or
+          operator has a slightly lower precedence than logical and.
+
+
+   In short, it's only meaningful to add or subtract the _offsets_ in an
+address; you can only have a defined section in one of the two
+arguments.
+
+
+File: as.info,  Node: Pseudo Ops,  Next: Machine Dependencies,  Prev: Expressions,  Up: Top
+
+7 Assembler Directives
+**********************
+
+All assembler directives have names that begin with a period (`.').
+The rest of the name is letters, usually in lower case.
+
+   This chapter discusses directives that are available regardless of
+the target machine configuration for the GNU assembler.  Some machine
+configurations provide additional directives.  *Note Machine
+Dependencies::.
+
+* Menu:
+
+* Abort::                       `.abort'
+
+* ABORT::                       `.ABORT'
+
+* Align::                       `.align ABS-EXPR , ABS-EXPR'
+* Altmacro::                    `.altmacro'
+* Ascii::                       `.ascii "STRING"'...
+* Asciz::                       `.asciz "STRING"'...
+* Balign::                      `.balign ABS-EXPR , ABS-EXPR'
+* Byte::                        `.byte EXPRESSIONS'
+* Comm::                        `.comm SYMBOL , LENGTH '
+
+* CFI directives::		`.cfi_startproc', `.cfi_endproc', etc.
+
+* Data::                        `.data SUBSECTION'
+
+* Def::                         `.def NAME'
+
+* Desc::                        `.desc SYMBOL, ABS-EXPRESSION'
+
+* Dim::                         `.dim'
+
+* Double::                      `.double FLONUMS'
+* Eject::                       `.eject'
+* Else::                        `.else'
+* Elseif::                      `.elseif'
+* End::				`.end'
+
+* Endef::                       `.endef'
+
+* Endfunc::                     `.endfunc'
+* Endif::                       `.endif'
+* Equ::                         `.equ SYMBOL, EXPRESSION'
+* Equiv::                       `.equiv SYMBOL, EXPRESSION'
+* Eqv::                         `.eqv SYMBOL, EXPRESSION'
+* Err::				`.err'
+* Error::			`.error STRING'
+* Exitm::			`.exitm'
+* Extern::                      `.extern'
+* Fail::			`.fail'
+
+* File::                        `.file STRING'
+
+* Fill::                        `.fill REPEAT , SIZE , VALUE'
+* Float::                       `.float FLONUMS'
+* Func::                        `.func'
+* Global::                      `.global SYMBOL', `.globl SYMBOL'
+
+* Hidden::                      `.hidden NAMES'
+
+* hword::                       `.hword EXPRESSIONS'
+* Ident::                       `.ident'
+* If::                          `.if ABSOLUTE EXPRESSION'
+* Incbin::                      `.incbin "FILE"[,SKIP[,COUNT]]'
+* Include::                     `.include "FILE"'
+* Int::                         `.int EXPRESSIONS'
+
+* Internal::                    `.internal NAMES'
+
+* Irp::				`.irp SYMBOL,VALUES'...
+* Irpc::			`.irpc SYMBOL,VALUES'...
+* Lcomm::                       `.lcomm SYMBOL , LENGTH'
+* Lflags::                      `.lflags'
+
+* Line::                        `.line LINE-NUMBER'
+
+* Linkonce::			`.linkonce [TYPE]'
+* List::                        `.list'
+* Ln::                          `.ln LINE-NUMBER'
+
+* LNS directives::              `.file', `.loc', etc.
+
+* Long::                        `.long EXPRESSIONS'
+
+* Macro::			`.macro NAME ARGS'...
+* MRI::				`.mri VAL'
+* Noaltmacro::                  `.noaltmacro'
+* Nolist::                      `.nolist'
+* Octa::                        `.octa BIGNUMS'
+* Org::                         `.org NEW-LC , FILL'
+* P2align::                     `.p2align ABS-EXPR , ABS-EXPR'
+
+* PopSection::                  `.popsection'
+* Previous::                    `.previous'
+
+* Print::			`.print STRING'
+
+* Protected::                   `.protected NAMES'
+
+* Psize::                       `.psize LINES, COLUMNS'
+* Purgem::			`.purgem NAME'
+
+* PushSection::                 `.pushsection NAME'
+
+* Quad::                        `.quad BIGNUMS'
+* Rept::			`.rept COUNT'
+* Sbttl::                       `.sbttl "SUBHEADING"'
+
+* Scl::                         `.scl CLASS'
+
+* Section::                     `.section NAME'
+
+* Set::                         `.set SYMBOL, EXPRESSION'
+* Short::                       `.short EXPRESSIONS'
+* Single::                      `.single FLONUMS'
+
+* Size::                        `.size [NAME , EXPRESSION]'
+
+* Skip::                        `.skip SIZE , FILL'
+* Sleb128::			`.sleb128 EXPRESSIONS'
+* Space::                       `.space SIZE , FILL'
+
+* Stab::                        `.stabd, .stabn, .stabs'
+
+* String::                      `.string "STR"'
+* Struct::			`.struct EXPRESSION'
+
+* SubSection::                  `.subsection'
+* Symver::                      `.symver NAME,NAME2@NODENAME'
+
+
+* Tag::                         `.tag STRUCTNAME'
+
+* Text::                        `.text SUBSECTION'
+* Title::                       `.title "HEADING"'
+
+* Type::                        `.type <INT | NAME , TYPE DESCRIPTION>'
+
+* Uleb128::                     `.uleb128 EXPRESSIONS'
+
+* Val::                         `.val ADDR'
+
+
+* Version::                     `.version "STRING"'
+* VTableEntry::                 `.vtable_entry TABLE, OFFSET'
+* VTableInherit::               `.vtable_inherit CHILD, PARENT'
+
+* Warning::			`.warning STRING'
+* Weak::                        `.weak NAMES'
+* Weakref::                     `.weakref ALIAS, SYMBOL'
+* Word::                        `.word EXPRESSIONS'
+* Deprecated::                  Deprecated Directives
+
+
+File: as.info,  Node: Abort,  Next: ABORT,  Up: Pseudo Ops
+
+7.1 `.abort'
+============
+
+This directive stops the assembly immediately.  It is for compatibility
+with other assemblers.  The original idea was that the assembly
+language source would be piped into the assembler.  If the sender of
+the source quit, it could use this directive tells `as' to quit also.
+One day `.abort' will not be supported.
+
+
+File: as.info,  Node: ABORT,  Next: Align,  Prev: Abort,  Up: Pseudo Ops
+
+7.2 `.ABORT'
+============
+
+When producing COFF output, `as' accepts this directive as a synonym
+for `.abort'.
+
+
+File: as.info,  Node: Align,  Next: Altmacro,  Prev: ABORT,  Up: Pseudo Ops
+
+7.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR'
+=========================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary.  The first expression (which must be absolute) is the
+alignment required, as described below.
+
+   The second expression (also absolute) gives the fill value to be
+stored in the padding bytes.  It (and the comma) may be omitted.  If it
+is omitted, the padding bytes are normally zero.  However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+   The third expression is also absolute, and is also optional.  If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive.  If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all.  You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+   The way the required alignment is specified varies from system to
+system.  For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
+s390, sparc, tic4x, tic80 and xtensa, the first expression is the
+alignment request in bytes.  For example `.align 8' advances the
+location counter until it is a multiple of 8.  If the location counter
+is already a multiple of 8, no change is needed.  For the tic54x, the
+first expression is the alignment request in words.
+
+   For other systems, including the i386 using a.out format, and the
+arm and strongarm, it is the number of low-order zero bits the location
+counter must have after advancement.  For example `.align 3' advances
+the location counter until it a multiple of 8.  If the location counter
+is already a multiple of 8, no change is needed.
+
+   This inconsistency is due to the different behaviors of the various
+native assemblers for these systems which GAS must emulate.  GAS also
+provides `.balign' and `.p2align' directives, described later, which
+have a consistent behavior across all architectures (but are specific
+to GAS).
+
+
+File: as.info,  Node: Ascii,  Next: Asciz,  Prev: Altmacro,  Up: Pseudo Ops
+
+7.4 `.ascii "STRING"'...
+========================
+
+`.ascii' expects zero or more string literals (*note Strings::)
+separated by commas.  It assembles each string (with no automatic
+trailing zero byte) into consecutive addresses.
+
+
+File: as.info,  Node: Asciz,  Next: Balign,  Prev: Ascii,  Up: Pseudo Ops
+
+7.5 `.asciz "STRING"'...
+========================
+
+`.asciz' is just like `.ascii', but each string is followed by a zero
+byte.  The "z" in `.asciz' stands for "zero".
+
+
+File: as.info,  Node: Balign,  Next: Byte,  Prev: Asciz,  Up: Pseudo Ops
+
+7.6 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+==============================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary.  The first expression (which must be absolute) is the
+alignment request in bytes.  For example `.balign 8' advances the
+location counter until it is a multiple of 8.  If the location counter
+is already a multiple of 8, no change is needed.
+
+   The second expression (also absolute) gives the fill value to be
+stored in the padding bytes.  It (and the comma) may be omitted.  If it
+is omitted, the padding bytes are normally zero.  However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+   The third expression is also absolute, and is also optional.  If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive.  If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all.  You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+   The `.balignw' and `.balignl' directives are variants of the
+`.balign' directive.  The `.balignw' directive treats the fill pattern
+as a two byte word value.  The `.balignl' directives treats the fill
+pattern as a four byte longword value.  For example, `.balignw
+4,0x368d' will align to a multiple of 4.  If it skips two bytes, they
+will be filled in with the value 0x368d (the exact placement of the
+bytes depends upon the endianness of the processor).  If it skips 1 or
+3 bytes, the fill value is undefined.
+
+
+File: as.info,  Node: Byte,  Next: Comm,  Prev: Balign,  Up: Pseudo Ops
+
+7.7 `.byte EXPRESSIONS'
+=======================
+
+`.byte' expects zero or more expressions, separated by commas.  Each
+expression is assembled into the next byte.
+
+
+File: as.info,  Node: Comm,  Next: CFI directives,  Prev: Byte,  Up: Pseudo Ops
+
+7.8 `.comm SYMBOL , LENGTH '
+============================
+
+`.comm' declares a common symbol named SYMBOL.  When linking, a common
+symbol in one object file may be merged with a defined or common symbol
+of the same name in another object file.  If `ld' does not see a
+definition for the symbol-just one or more common symbols-then it will
+allocate LENGTH bytes of uninitialized memory.  LENGTH must be an
+absolute expression.  If `ld' sees multiple common symbols with the
+same name, and they do not all have the same size, it will allocate
+space using the largest size.
+
+   When using ELF, the `.comm' directive takes an optional third
+argument.  This is the desired alignment of the symbol, specified as a
+byte boundary (for example, an alignment of 16 means that the least
+significant 4 bits of the address should be zero).  The alignment must
+be an absolute expression, and it must be a power of two.  If `ld'
+allocates uninitialized memory for the common symbol, it will use the
+alignment when placing the symbol.  If no alignment is specified, `as'
+will set the alignment to the largest power of two less than or equal
+to the size of the symbol, up to a maximum of 16.
+
+   The syntax for `.comm' differs slightly on the HPPA.  The syntax is
+`SYMBOL .comm, LENGTH'; SYMBOL is optional.
+
+
+File: as.info,  Node: CFI directives,  Next: Data,  Prev: Comm,  Up: Pseudo Ops
+
+7.9 `.cfi_startproc'
+====================
+
+`.cfi_startproc' is used at the beginning of each function that should
+have an entry in `.eh_frame'. It initializes some internal data
+structures and emits architecture dependent initial CFI instructions.
+Don't forget to close the function by `.cfi_endproc'.
+
+7.10 `.cfi_endproc'
+===================
+
+`.cfi_endproc' is used at the end of a function where it closes its
+unwind entry previously opened by `.cfi_startproc'. and emits it to
+`.eh_frame'.
+
+7.11 `.cfi_def_cfa REGISTER, OFFSET'
+====================================
+
+`.cfi_def_cfa' defines a rule for computing CFA as: take address from
+REGISTER and add OFFSET to it.
+
+7.12 `.cfi_def_cfa_register REGISTER'
+=====================================
+
+`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on
+REGISTER will be used instead of the old one. Offset remains the same.
+
+7.13 `.cfi_def_cfa_offset OFFSET'
+=================================
+
+`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register
+remains the same, but OFFSET is new. Note that it is the absolute
+offset that will be added to a defined register to compute CFA address.
+
+7.14 `.cfi_adjust_cfa_offset OFFSET'
+====================================
+
+Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is
+added/substracted from the previous offset.
+
+7.15 `.cfi_offset REGISTER, OFFSET'
+===================================
+
+Previous value of REGISTER is saved at offset OFFSET from CFA.
+
+7.16 `.cfi_rel_offset REGISTER, OFFSET'
+=======================================
+
+Previous value of REGISTER is saved at offset OFFSET from the current
+CFA register.  This is transformed to `.cfi_offset' using the known
+displacement of the CFA register from the CFA.  This is often easier to
+use, because the number will match the code it's annotating.
+
+7.17 `.cfi_signal_frame'
+========================
+
+Mark current function as signal trampoline.
+
+7.18 `.cfi_window_save'
+=======================
+
+SPARC register window has been saved.
+
+7.19 `.cfi_escape' EXPRESSION[, ...]
+====================================
+
+Allows the user to add arbitrary bytes to the unwind info.  One might
+use this to add OS-specific CFI opcodes, or generic CFI opcodes that
+GAS does not yet support.
+
+
+File: as.info,  Node: LNS directives,  Next: Long,  Prev: Ln,  Up: Pseudo Ops
+
+7.20 `.file FILENO FILENAME'
+============================
+
+When emitting dwarf2 line number information `.file' assigns filenames
+to the `.debug_line' file name table.  The FILENO operand should be a
+unique positive integer to use as the index of the entry in the table.
+The FILENAME operand is a C string literal.
+
+   The detail of filename indicies is exposed to the user because the
+filename table is shared with the `.debug_info' section of the dwarf2
+debugging information, and thus the user must know the exact indicies
+that table entries will have.
+
+7.21 `.loc FILENO LINENO [COLUMN] [OPTIONS]'
+============================================
+
+The `.loc' directive will add row to the `.debug_line' line number
+matrix corresponding to the immediately following assembly instruction.
+The FILENO, LINENO, and optional COLUMN arguments will be applied to
+the `.debug_line' state machine before the row is added.
+
+   The OPTIONS are a sequence of the following tokens in any order:
+
+`basic_block'
+     This option will set the `basic_block' register in the
+     `.debug_line' state machine to `true'.
+
+`prologue_end'
+     This option will set the `prologue_end' register in the
+     `.debug_line' state machine to `true'.
+
+`epilogue_begin'
+     This option will set the `epilogue_begin' register in the
+     `.debug_line' state machine to `true'.
+
+`is_stmt VALUE'
+     This option will set the `is_stmt' register in the `.debug_line'
+     state machine to `value', which must be either 0 or 1.
+
+`isa VALUE'
+     This directive will set the `isa' register in the `.debug_line'
+     state machine to VALUE, which must be an unsigned integer.
+
+
+7.22 `.loc_mark_blocks ENABLE'
+==============================
+
+The `.loc_mark_blocks' directive makes the assembler emit an entry to
+the `.debug_line' line number matrix with the `basic_block' register in
+the state machine set whenever a code label is seen.  The ENABLE
+argument should be either 1 or 0, to enable or disable this function
+respectively.
+
+
+File: as.info,  Node: Data,  Next: Def,  Prev: CFI directives,  Up: Pseudo Ops
+
+7.23 `.data SUBSECTION'
+=======================
+
+`.data' tells `as' to assemble the following statements onto the end of
+the data subsection numbered SUBSECTION (which is an absolute
+expression).  If SUBSECTION is omitted, it defaults to zero.
+
+
+File: as.info,  Node: Def,  Next: Desc,  Prev: Data,  Up: Pseudo Ops
+
+7.24 `.def NAME'
+================
+
+Begin defining debugging information for a symbol NAME; the definition
+extends until the `.endef' directive is encountered.
+
+
+File: as.info,  Node: Desc,  Next: Dim,  Prev: Def,  Up: Pseudo Ops
+
+7.25 `.desc SYMBOL, ABS-EXPRESSION'
+===================================
+
+This directive sets the descriptor of the symbol (*note Symbol
+Attributes::) to the low 16 bits of an absolute expression.
+
+   The `.desc' directive is not available when `as' is configured for
+COFF output; it is only for `a.out' or `b.out' object format.  For the
+sake of compatibility, `as' accepts it, but produces no output, when
+configured for COFF.
+
+
+File: as.info,  Node: Dim,  Next: Double,  Prev: Desc,  Up: Pseudo Ops
+
+7.26 `.dim'
+===========
+
+This directive is generated by compilers to include auxiliary debugging
+information in the symbol table.  It is only permitted inside
+`.def'/`.endef' pairs.
+
+
+File: as.info,  Node: Double,  Next: Eject,  Prev: Dim,  Up: Pseudo Ops
+
+7.27 `.double FLONUMS'
+======================
+
+`.double' expects zero or more flonums, separated by commas.  It
+assembles floating point numbers.  The exact kind of floating point
+numbers emitted depends on how `as' is configured.  *Note Machine
+Dependencies::.
+
+
+File: as.info,  Node: Eject,  Next: Else,  Prev: Double,  Up: Pseudo Ops
+
+7.28 `.eject'
+=============
+
+Force a page break at this point, when generating assembly listings.
+
+
+File: as.info,  Node: Else,  Next: Elseif,  Prev: Eject,  Up: Pseudo Ops
+
+7.29 `.else'
+============
+
+`.else' is part of the `as' support for conditional assembly; *note
+`.if': If.  It marks the beginning of a section of code to be assembled
+if the condition for the preceding `.if' was false.
+
+
+File: as.info,  Node: Elseif,  Next: End,  Prev: Else,  Up: Pseudo Ops
+
+7.30 `.elseif'
+==============
+
+`.elseif' is part of the `as' support for conditional assembly; *note
+`.if': If.  It is shorthand for beginning a new `.if' block that would
+otherwise fill the entire `.else' section.
+
+
+File: as.info,  Node: End,  Next: Endef,  Prev: Elseif,  Up: Pseudo Ops
+
+7.31 `.end'
+===========
+
+`.end' marks the end of the assembly file.  `as' does not process
+anything in the file past the `.end' directive.
+
+
+File: as.info,  Node: Endef,  Next: Endfunc,  Prev: End,  Up: Pseudo Ops
+
+7.32 `.endef'
+=============
+
+This directive flags the end of a symbol definition begun with `.def'.
+
+
+File: as.info,  Node: Endfunc,  Next: Endif,  Prev: Endef,  Up: Pseudo Ops
+
+7.33 `.endfunc'
+===============
+
+`.endfunc' marks the end of a function specified with `.func'.
+
+
+File: as.info,  Node: Endif,  Next: Equ,  Prev: Endfunc,  Up: Pseudo Ops
+
+7.34 `.endif'
+=============
+
+`.endif' is part of the `as' support for conditional assembly; it marks
+the end of a block of code that is only assembled conditionally.  *Note
+`.if': If.
+
+
+File: as.info,  Node: Equ,  Next: Equiv,  Prev: Endif,  Up: Pseudo Ops
+
+7.35 `.equ SYMBOL, EXPRESSION'
+==============================
+
+This directive sets the value of SYMBOL to EXPRESSION.  It is
+synonymous with `.set'; *note `.set': Set.
+
+   The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'.
+
+   The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'.  On the
+Z80 it is an eror if SYMBOL is already defined, but the symbol is not
+protected from later redefinition, compare *Note Equiv::.
+
+
+File: as.info,  Node: Equiv,  Next: Eqv,  Prev: Equ,  Up: Pseudo Ops
+
+7.36 `.equiv SYMBOL, EXPRESSION'
+================================
+
+The `.equiv' directive is like `.equ' and `.set', except that the
+assembler will signal an error if SYMBOL is already defined.  Note a
+symbol which has been referenced but not actually defined is considered
+to be undefined.
+
+   Except for the contents of the error message, this is roughly
+equivalent to
+     .ifdef SYM
+     .err
+     .endif
+     .equ SYM,VAL
+   plus it protects the symbol from later redefinition.
+
+
+File: as.info,  Node: Eqv,  Next: Err,  Prev: Equiv,  Up: Pseudo Ops
+
+7.37 `.eqv SYMBOL, EXPRESSION'
+==============================
+
+The `.eqv' directive is like `.equiv', but no attempt is made to
+evaluate the expression or any part of it immediately.  Instead each
+time the resulting symbol is used in an expression, a snapshot of its
+current value is taken.
+
+
+File: as.info,  Node: Err,  Next: Error,  Prev: Eqv,  Up: Pseudo Ops
+
+7.38 `.err'
+===========
+
+If `as' assembles a `.err' directive, it will print an error message
+and, unless the `-Z' option was used, it will not generate an object
+file.  This can be used to signal an error in conditionally compiled
+code.
+
+
+File: as.info,  Node: Error,  Next: Exitm,  Prev: Err,  Up: Pseudo Ops
+
+7.39 `.error "STRING"'
+======================
+
+Similarly to `.err', this directive emits an error, but you can specify
+a string that will be emitted as the error message.  If you don't
+specify the message, it defaults to `".error directive invoked in
+source file"'.  *Note Error and Warning Messages: Errors.
+
+      .error "This code has not been assembled and tested."
+
+
+File: as.info,  Node: Exitm,  Next: Extern,  Prev: Error,  Up: Pseudo Ops
+
+7.40 `.exitm'
+=============
+
+Exit early from the current macro definition.  *Note Macro::.
+
+
+File: as.info,  Node: Extern,  Next: Fail,  Prev: Exitm,  Up: Pseudo Ops
+
+7.41 `.extern'
+==============
+
+`.extern' is accepted in the source program--for compatibility with
+other assemblers--but it is ignored.  `as' treats all undefined symbols
+as external.
+
+
+File: as.info,  Node: Fail,  Next: File,  Prev: Extern,  Up: Pseudo Ops
+
+7.42 `.fail EXPRESSION'
+=======================
+
+Generates an error or a warning.  If the value of the EXPRESSION is 500
+or more, `as' will print a warning message.  If the value is less than
+500, `as' will print an error message.  The message will include the
+value of EXPRESSION.  This can occasionally be useful inside complex
+nested macros or conditional assembly.
+
+
+File: as.info,  Node: File,  Next: Fill,  Prev: Fail,  Up: Pseudo Ops
+
+7.43 `.file STRING'
+===================
+
+`.file' tells `as' that we are about to start a new logical file.
+STRING is the new file name.  In general, the filename is recognized
+whether or not it is surrounded by quotes `"'; but if you wish to
+specify an empty file name, you must give the quotes-`""'.  This
+statement may go away in future: it is only recognized to be compatible
+with old `as' programs.
+
+
+File: as.info,  Node: Fill,  Next: Float,  Prev: File,  Up: Pseudo Ops
+
+7.44 `.fill REPEAT , SIZE , VALUE'
+==================================
+
+REPEAT, SIZE and VALUE are absolute expressions.  This emits REPEAT
+copies of SIZE bytes.  REPEAT may be zero or more.  SIZE may be zero or
+more, but if it is more than 8, then it is deemed to have the value 8,
+compatible with other people's assemblers.  The contents of each REPEAT
+bytes is taken from an 8-byte number.  The highest order 4 bytes are
+zero.  The lowest order 4 bytes are VALUE rendered in the byte-order of
+an integer on the computer `as' is assembling for.  Each SIZE bytes in
+a repetition is taken from the lowest order SIZE bytes of this number.
+Again, this bizarre behavior is compatible with other people's
+assemblers.
+
+   SIZE and VALUE are optional.  If the second comma and VALUE are
+absent, VALUE is assumed zero.  If the first comma and following tokens
+are absent, SIZE is assumed to be 1.
+
+
+File: as.info,  Node: Float,  Next: Func,  Prev: Fill,  Up: Pseudo Ops
+
+7.45 `.float FLONUMS'
+=====================
+
+This directive assembles zero or more flonums, separated by commas.  It
+has the same effect as `.single'.  The exact kind of floating point
+numbers emitted depends on how `as' is configured.  *Note Machine
+Dependencies::.
+
+
+File: as.info,  Node: Func,  Next: Global,  Prev: Float,  Up: Pseudo Ops
+
+7.46 `.func NAME[,LABEL]'
+=========================
+
+`.func' emits debugging information to denote function NAME, and is
+ignored unless the file is assembled with debugging enabled.  Only
+`--gstabs[+]' is currently supported.  LABEL is the entry point of the
+function and if omitted NAME prepended with the `leading char' is used.
+`leading char' is usually `_' or nothing, depending on the target.  All
+functions are currently defined to have `void' return type.  The
+function must be terminated with `.endfunc'.
+
+
+File: as.info,  Node: Global,  Next: Hidden,  Prev: Func,  Up: Pseudo Ops
+
+7.47 `.global SYMBOL', `.globl SYMBOL'
+======================================
+
+`.global' makes the symbol visible to `ld'.  If you define SYMBOL in
+your partial program, its value is made available to other partial
+programs that are linked with it.  Otherwise, SYMBOL takes its
+attributes from a symbol of the same name from another file linked into
+the same program.
+
+   Both spellings (`.globl' and `.global') are accepted, for
+compatibility with other assemblers.
+
+   On the HPPA, `.global' is not always enough to make it accessible to
+other partial programs.  You may need the HPPA-only `.EXPORT' directive
+as well.  *Note HPPA Assembler Directives: HPPA Directives.
+
+
+File: as.info,  Node: Hidden,  Next: hword,  Prev: Global,  Up: Pseudo Ops
+
+7.48 `.hidden NAMES'
+====================
+
+This is one of the ELF visibility directives.  The other two are
+`.internal' (*note `.internal': Internal.) and `.protected' (*note
+`.protected': Protected.).
+
+   This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak).  The directive sets
+the visibility to `hidden' which means that the symbols are not visible
+to other components.  Such symbols are always considered to be
+`protected' as well.
+
+
+File: as.info,  Node: hword,  Next: Ident,  Prev: Hidden,  Up: Pseudo Ops
+
+7.49 `.hword EXPRESSIONS'
+=========================
+
+This expects zero or more EXPRESSIONS, and emits a 16 bit number for
+each.
+
+   This directive is a synonym for `.short'; depending on the target
+architecture, it may also be a synonym for `.word'.
+
+
+File: as.info,  Node: Ident,  Next: If,  Prev: hword,  Up: Pseudo Ops
+
+7.50 `.ident'
+=============
+
+This directive is used by some assemblers to place tags in object
+files.  The behavior of this directive varies depending on the target.
+When using the a.out object file format, `as' simply accepts the
+directive for source-file compatibility with existing assemblers, but
+does not emit anything for it.  When using COFF, comments are emitted
+to the `.comment' or `.rdata' section, depending on the target.  When
+using ELF, comments are emitted to the `.comment' section.
+
+
+File: as.info,  Node: If,  Next: Incbin,  Prev: Ident,  Up: Pseudo Ops
+
+7.51 `.if ABSOLUTE EXPRESSION'
+==============================
+
+`.if' marks the beginning of a section of code which is only considered
+part of the source program being assembled if the argument (which must
+be an ABSOLUTE EXPRESSION) is non-zero.  The end of the conditional
+section of code must be marked by `.endif' (*note `.endif': Endif.);
+optionally, you may include code for the alternative condition, flagged
+by `.else' (*note `.else': Else.).  If you have several conditions to
+check, `.elseif' may be used to avoid nesting blocks if/else within
+each subsequent `.else' block.
+
+   The following variants of `.if' are also supported:
+`.ifdef SYMBOL'
+     Assembles the following section of code if the specified SYMBOL
+     has been defined.  Note a symbol which has been referenced but not
+     yet defined is considered to be undefined.
+
+`.ifb TEXT'
+     Assembles the following section of code if the operand is blank
+     (empty).
+
+`.ifc STRING1,STRING2'
+     Assembles the following section of code if the two strings are the
+     same.  The strings may be optionally quoted with single quotes.
+     If they are not quoted, the first string stops at the first comma,
+     and the second string stops at the end of the line.  Strings which
+     contain whitespace should be quoted.  The string comparison is
+     case sensitive.
+
+`.ifeq ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is zero.
+
+`.ifeqs STRING1,STRING2'
+     Another form of `.ifc'.  The strings must be quoted using double
+     quotes.
+
+`.ifge ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is greater
+     than or equal to zero.
+
+`.ifgt ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is greater
+     than zero.
+
+`.ifle ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is less
+     than or equal to zero.
+
+`.iflt ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is less
+     than zero.
+
+`.ifnb TEXT'
+     Like `.ifb', but the sense of the test is reversed: this assembles
+     the following section of code if the operand is non-blank
+     (non-empty).
+
+`.ifnc STRING1,STRING2.'
+     Like `.ifc', but the sense of the test is reversed: this assembles
+     the following section of code if the two strings are not the same.
+
+`.ifndef SYMBOL'
+`.ifnotdef SYMBOL'
+     Assembles the following section of code if the specified SYMBOL
+     has not been defined.  Both spelling variants are equivalent.
+     Note a symbol which has been referenced but not yet defined is
+     considered to be undefined.
+
+`.ifne ABSOLUTE EXPRESSION'
+     Assembles the following section of code if the argument is not
+     equal to zero (in other words, this is equivalent to `.if').
+
+`.ifnes STRING1,STRING2'
+     Like `.ifeqs', but the sense of the test is reversed: this
+     assembles the following section of code if the two strings are not
+     the same.
+
+
+File: as.info,  Node: Incbin,  Next: Include,  Prev: If,  Up: Pseudo Ops
+
+7.52 `.incbin "FILE"[,SKIP[,COUNT]]'
+====================================
+
+The `incbin' directive includes FILE verbatim at the current location.
+You can control the search paths used with the `-I' command-line option
+(*note Command-Line Options: Invoking.).  Quotation marks are required
+around FILE.
+
+   The SKIP argument skips a number of bytes from the start of the
+FILE.  The COUNT argument indicates the maximum number of bytes to
+read.  Note that the data is not aligned in any way, so it is the user's
+responsibility to make sure that proper alignment is provided both
+before and after the `incbin' directive.
+
+
+File: as.info,  Node: Include,  Next: Int,  Prev: Incbin,  Up: Pseudo Ops
+
+7.53 `.include "FILE"'
+======================
+
+This directive provides a way to include supporting files at specified
+points in your source program.  The code from FILE is assembled as if
+it followed the point of the `.include'; when the end of the included
+file is reached, assembly of the original file continues.  You can
+control the search paths used with the `-I' command-line option (*note
+Command-Line Options: Invoking.).  Quotation marks are required around
+FILE.
+
+
+File: as.info,  Node: Int,  Next: Internal,  Prev: Include,  Up: Pseudo Ops
+
+7.54 `.int EXPRESSIONS'
+=======================
+
+Expect zero or more EXPRESSIONS, of any section, separated by commas.
+For each expression, emit a number that, at run time, is the value of
+that expression.  The byte order and bit size of the number depends on
+what kind of target the assembly is for.
+
+
+File: as.info,  Node: Internal,  Next: Irp,  Prev: Int,  Up: Pseudo Ops
+
+7.55 `.internal NAMES'
+======================
+
+This is one of the ELF visibility directives.  The other two are
+`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note
+`.protected': Protected.).
+
+   This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak).  The directive sets
+the visibility to `internal' which means that the symbols are
+considered to be `hidden' (i.e., not visible to other components), and
+that some extra, processor specific processing must also be performed
+upon the  symbols as well.
+
+
+File: as.info,  Node: Irp,  Next: Irpc,  Prev: Internal,  Up: Pseudo Ops
+
+7.56 `.irp SYMBOL,VALUES'...
+============================
+
+Evaluate a sequence of statements assigning different values to SYMBOL.
+The sequence of statements starts at the `.irp' directive, and is
+terminated by an `.endr' directive.  For each VALUE, SYMBOL is set to
+VALUE, and the sequence of statements is assembled.  If no VALUE is
+listed, the sequence of statements is assembled once, with SYMBOL set
+to the null string.  To refer to SYMBOL within the sequence of
+statements, use \SYMBOL.
+
+   For example, assembling
+
+             .irp    param,1,2,3
+             move    d\param,sp@-
+             .endr
+
+   is equivalent to assembling
+
+             move    d1,sp@-
+             move    d2,sp@-
+             move    d3,sp@-
+
+   For some caveats with the spelling of SYMBOL, see also the discussion
+at *Note Macro::.
+
+
+File: as.info,  Node: Irpc,  Next: Lcomm,  Prev: Irp,  Up: Pseudo Ops
+
+7.57 `.irpc SYMBOL,VALUES'...
+=============================
+
+Evaluate a sequence of statements assigning different values to SYMBOL.
+The sequence of statements starts at the `.irpc' directive, and is
+terminated by an `.endr' directive.  For each character in VALUE,
+SYMBOL is set to the character, and the sequence of statements is
+assembled.  If no VALUE is listed, the sequence of statements is
+assembled once, with SYMBOL set to the null string.  To refer to SYMBOL
+within the sequence of statements, use \SYMBOL.
+
+   For example, assembling
+
+             .irpc    param,123
+             move    d\param,sp@-
+             .endr
+
+   is equivalent to assembling
+
+             move    d1,sp@-
+             move    d2,sp@-
+             move    d3,sp@-
+
+   For some caveats with the spelling of SYMBOL, see also the discussion
+at *Note Macro::.
+
+
+File: as.info,  Node: Lcomm,  Next: Lflags,  Prev: Irpc,  Up: Pseudo Ops
+
+7.58 `.lcomm SYMBOL , LENGTH'
+=============================
+
+Reserve LENGTH (an absolute expression) bytes for a local common
+denoted by SYMBOL.  The section and value of SYMBOL are those of the
+new local common.  The addresses are allocated in the bss section, so
+that at run-time the bytes start off zeroed.  SYMBOL is not declared
+global (*note `.global': Global.), so is normally not visible to `ld'.
+
+   Some targets permit a third argument to be used with `.lcomm'.  This
+argument specifies the desired alignment of the symbol in the bss
+section.
+
+   The syntax for `.lcomm' differs slightly on the HPPA.  The syntax is
+`SYMBOL .lcomm, LENGTH'; SYMBOL is optional.
+
+
+File: as.info,  Node: Lflags,  Next: Line,  Prev: Lcomm,  Up: Pseudo Ops
+
+7.59 `.lflags'
+==============
+
+`as' accepts this directive, for compatibility with other assemblers,
+but ignores it.
+
+
+File: as.info,  Node: Line,  Next: Linkonce,  Prev: Lflags,  Up: Pseudo Ops
+
+7.60 `.line LINE-NUMBER'
+========================
+
+   Change the logical line number.  LINE-NUMBER must be an absolute
+expression.  The next line has that logical line number.  Therefore any
+other statements on the current line (after a statement separator
+character) are reported as on logical line number LINE-NUMBER - 1.  One
+day `as' will no longer support this directive: it is recognized only
+for compatibility with existing assembler programs.
+
+   Even though this is a directive associated with the `a.out' or
+`b.out' object-code formats, `as' still recognizes it when producing
+COFF output, and treats `.line' as though it were the COFF `.ln' _if_
+it is found outside a `.def'/`.endef' pair.
+
+   Inside a `.def', `.line' is, instead, one of the directives used by
+compilers to generate auxiliary symbol information for debugging.
+
+
+File: as.info,  Node: Linkonce,  Next: List,  Prev: Line,  Up: Pseudo Ops
+
+7.61 `.linkonce [TYPE]'
+=======================
+
+Mark the current section so that the linker only includes a single copy
+of it.  This may be used to include the same section in several
+different object files, but ensure that the linker will only include it
+once in the final output file.  The `.linkonce' pseudo-op must be used
+for each instance of the section.  Duplicate sections are detected
+based on the section name, so it should be unique.
+
+   This directive is only supported by a few object file formats; as of
+this writing, the only object file format which supports it is the
+Portable Executable format used on Windows NT.
+
+   The TYPE argument is optional.  If specified, it must be one of the
+following strings.  For example:
+     .linkonce same_size
+   Not all types may be supported on all object file formats.
+
+`discard'
+     Silently discard duplicate sections.  This is the default.
+
+`one_only'
+     Warn if there are duplicate sections, but still keep only one copy.
+
+`same_size'
+     Warn if any of the duplicates have different sizes.
+
+`same_contents'
+     Warn if any of the duplicates do not have exactly the same
+     contents.
+
+
+File: as.info,  Node: Ln,  Next: LNS directives,  Prev: List,  Up: Pseudo Ops
+
+7.62 `.ln LINE-NUMBER'
+======================
+
+`.ln' is a synonym for `.line'.
+
+
+File: as.info,  Node: MRI,  Next: Noaltmacro,  Prev: Macro,  Up: Pseudo Ops
+
+7.63 `.mri VAL'
+===============
+
+If VAL is non-zero, this tells `as' to enter MRI mode.  If VAL is zero,
+this tells `as' to exit MRI mode.  This change affects code assembled
+until the next `.mri' directive, or until the end of the file.  *Note
+MRI mode: M.
+
+
+File: as.info,  Node: List,  Next: Ln,  Prev: Linkonce,  Up: Pseudo Ops
+
+7.64 `.list'
+============
+
+Control (in conjunction with the `.nolist' directive) whether or not
+assembly listings are generated.  These two directives maintain an
+internal counter (which is zero initially).   `.list' increments the
+counter, and `.nolist' decrements it.  Assembly listings are generated
+whenever the counter is greater than zero.
+
+   By default, listings are disabled.  When you enable them (with the
+`-a' command line option; *note Command-Line Options: Invoking.), the
+initial value of the listing counter is one.
+
+
+File: as.info,  Node: Long,  Next: Macro,  Prev: LNS directives,  Up: Pseudo Ops
+
+7.65 `.long EXPRESSIONS'
+========================
+
+`.long' is the same as `.int', *note `.int': Int.
+
+
+File: as.info,  Node: Macro,  Next: MRI,  Prev: Long,  Up: Pseudo Ops
+
+7.66 `.macro'
+=============
+
+The commands `.macro' and `.endm' allow you to define macros that
+generate assembly output.  For example, this definition specifies a
+macro `sum' that puts a sequence of numbers into memory:
+
+             .macro  sum from=0, to=5
+             .long   \from
+             .if     \to-\from
+             sum     "(\from+1)",\to
+             .endif
+             .endm
+
+With that definition, `SUM 0,5' is equivalent to this assembly input:
+
+             .long   0
+             .long   1
+             .long   2
+             .long   3
+             .long   4
+             .long   5
+
+`.macro MACNAME'
+`.macro MACNAME MACARGS ...'
+     Begin the definition of a macro called MACNAME.  If your macro
+     definition requires arguments, specify their names after the macro
+     name, separated by commas or spaces.  You can qualify the macro
+     argument to indicate whether all invocations must specify a
+     non-blank value (through `:`req''), or whether it takes all of the
+     remaining arguments (through `:`vararg'').  You can supply a
+     default value for any macro argument by following the name with
+     `=DEFLT'.  You cannot define two macros with the same MACNAME
+     unless it has been subject to the `.purgem' directive (*Note
+     Purgem::.) between the two definitions.  For example, these are
+     all valid `.macro' statements:
+
+    `.macro comm'
+          Begin the definition of a macro called `comm', which takes no
+          arguments.
+
+    `.macro plus1 p, p1'
+    `.macro plus1 p p1'
+          Either statement begins the definition of a macro called
+          `plus1', which takes two arguments; within the macro
+          definition, write `\p' or `\p1' to evaluate the arguments.
+
+    `.macro reserve_str p1=0 p2'
+          Begin the definition of a macro called `reserve_str', with two
+          arguments.  The first argument has a default value, but not
+          the second.  After the definition is complete, you can call
+          the macro either as `reserve_str A,B' (with `\p1' evaluating
+          to A and `\p2' evaluating to B), or as `reserve_str ,B' (with
+          `\p1' evaluating as the default, in this case `0', and `\p2'
+          evaluating to B).
+
+`.macro m p1:req, p2=0, p3:vararg'
+     Begin the definition of a macro called `m', with at least three
+     arguments.  The first argument must always have a value specified,
+     but not the second, which instead has a default value. The third
+     formal will get assigned all remaining arguments specified at
+     invocation time.
+
+     When you call a macro, you can specify the argument values either
+     by position, or by keyword.  For example, `sum 9,17' is equivalent
+     to `sum to=17, from=9'.
+
+     Note that since each of the MACARGS can be an identifier exactly
+     as any other one permitted by the target architecture, there may be
+     occasional problems if the target hand-crafts special meanings to
+     certain characters when they occur in a special position.  For
+     example, if colon (`:') is generally permitted to be part of a
+     symbol name, but the architecture specific code special-cases it
+     when occuring as the final character of a symbol (to denote a
+     label), then the macro parameter replacement code will have no way
+     of knowing that and consider the whole construct (including the
+     colon) an identifier, and check only this identifier for being the
+     subject to parameter substitution.  In this example, besides the
+     potential of just separating identifier and colon by white space,
+     using alternate macro syntax (*Note Altmacro::.) and ampersand
+     (`&') as the character to separate literal text from macro
+     parameters (or macro parameters from one another) would provide a
+     way to achieve the same effect:
+
+          	.altmacro
+          	.macro label l
+          l&:
+          	.endm
+
+     This applies identically to the identifiers used in `.irp' (*Note
+     Irp::.)  and `.irpc' (*Note Irpc::.).
+
+`.endm'
+     Mark the end of a macro definition.
+
+`.exitm'
+     Exit early from the current macro definition.
+
+`\@'
+     `as' maintains a counter of how many macros it has executed in
+     this pseudo-variable; you can copy that number to your output with
+     `\@', but _only within a macro definition_.
+
+`LOCAL NAME [ , ... ]'
+     _Warning: `LOCAL' is only available if you select "alternate macro
+     syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro':
+     Altmacro.
+
+
+File: as.info,  Node: Altmacro,  Next: Ascii,  Prev: Align,  Up: Pseudo Ops
+
+7.67 `.altmacro'
+================
+
+Enable alternate macro mode, enabling:
+
+`LOCAL NAME [ , ... ]'
+     One additional directive, `LOCAL', is available.  It is used to
+     generate a string replacement for each of the NAME arguments, and
+     replace any instances of NAME in each macro expansion.  The
+     replacement string is unique in the assembly, and different for
+     each separate macro expansion.  `LOCAL' allows you to write macros
+     that define symbols, without fear of conflict between separate
+     macro expansions.
+
+`String delimiters'
+     You can write strings delimited in these other ways besides
+     `"STRING"':
+
+    `'STRING''
+          You can delimit strings with single-quote charaters.
+
+    `<STRING>'
+          You can delimit strings with matching angle brackets.
+
+`single-character string escape'
+     To include any single character literally in a string (even if the
+     character would otherwise have some special meaning), you can
+     prefix the character with `!' (an exclamation mark).  For example,
+     you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 >
+     5.4!'.
+
+`Expression results as strings'
+     You can write `%EXPR' to evaluate the expression EXPR and use the
+     result as a string.
+
+
+File: as.info,  Node: Noaltmacro,  Next: Nolist,  Prev: MRI,  Up: Pseudo Ops
+
+7.68 `.noaltmacro'
+==================
+
+Disable alternate macro mode.  *Note Altmacro::
+
+
+File: as.info,  Node: Nolist,  Next: Octa,  Prev: Noaltmacro,  Up: Pseudo Ops
+
+7.69 `.nolist'
+==============
+
+Control (in conjunction with the `.list' directive) whether or not
+assembly listings are generated.  These two directives maintain an
+internal counter (which is zero initially).   `.list' increments the
+counter, and `.nolist' decrements it.  Assembly listings are generated
+whenever the counter is greater than zero.
+
+
+File: as.info,  Node: Octa,  Next: Org,  Prev: Nolist,  Up: Pseudo Ops
+
+7.70 `.octa BIGNUMS'
+====================
+
+This directive expects zero or more bignums, separated by commas.  For
+each bignum, it emits a 16-byte integer.
+
+   The term "octa" comes from contexts in which a "word" is two bytes;
+hence _octa_-word for 16 bytes.
+
+
+File: as.info,  Node: Org,  Next: P2align,  Prev: Octa,  Up: Pseudo Ops
+
+7.71 `.org NEW-LC , FILL'
+=========================
+
+Advance the location counter of the current section to NEW-LC.  NEW-LC
+is either an absolute expression or an expression with the same section
+as the current subsection.  That is, you can't use `.org' to cross
+sections: if NEW-LC has the wrong section, the `.org' directive is
+ignored.  To be compatible with former assemblers, if the section of
+NEW-LC is absolute, `as' issues a warning, then pretends the section of
+NEW-LC is the same as the current subsection.
+
+   `.org' may only increase the location counter, or leave it
+unchanged; you cannot use `.org' to move the location counter backwards.
+
+   Because `as' tries to assemble programs in one pass, NEW-LC may not
+be undefined.  If you really detest this restriction we eagerly await a
+chance to share your improved assembler.
+
+   Beware that the origin is relative to the start of the section, not
+to the start of the subsection.  This is compatible with other people's
+assemblers.
+
+   When the location counter (of the current subsection) is advanced,
+the intervening bytes are filled with FILL which should be an absolute
+expression.  If the comma and FILL are omitted, FILL defaults to zero.
+
+
+File: as.info,  Node: P2align,  Next: PopSection,  Prev: Org,  Up: Pseudo Ops
+
+7.72 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR'
+================================================
+
+Pad the location counter (in the current subsection) to a particular
+storage boundary.  The first expression (which must be absolute) is the
+number of low-order zero bits the location counter must have after
+advancement.  For example `.p2align 3' advances the location counter
+until it a multiple of 8.  If the location counter is already a
+multiple of 8, no change is needed.
+
+   The second expression (also absolute) gives the fill value to be
+stored in the padding bytes.  It (and the comma) may be omitted.  If it
+is omitted, the padding bytes are normally zero.  However, on some
+systems, if the section is marked as containing code and the fill value
+is omitted, the space is filled with no-op instructions.
+
+   The third expression is also absolute, and is also optional.  If it
+is present, it is the maximum number of bytes that should be skipped by
+this alignment directive.  If doing the alignment would require
+skipping more bytes than the specified maximum, then the alignment is
+not done at all.  You can omit the fill value (the second argument)
+entirely by simply using two commas after the required alignment; this
+can be useful if you want the alignment to be filled with no-op
+instructions when appropriate.
+
+   The `.p2alignw' and `.p2alignl' directives are variants of the
+`.p2align' directive.  The `.p2alignw' directive treats the fill
+pattern as a two byte word value.  The `.p2alignl' directives treats the
+fill pattern as a four byte longword value.  For example, `.p2alignw
+2,0x368d' will align to a multiple of 4.  If it skips two bytes, they
+will be filled in with the value 0x368d (the exact placement of the
+bytes depends upon the endianness of the processor).  If it skips 1 or
+3 bytes, the fill value is undefined.
+
+
+File: as.info,  Node: Previous,  Next: Print,  Prev: PopSection,  Up: Pseudo Ops
+
+7.73 `.previous'
+================
+
+This is one of the ELF section stack manipulation directives.  The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.pushsection' (*note PushSection::), and `.popsection'
+(*note PopSection::).
+
+   This directive swaps the current section (and subsection) with most
+recently referenced section (and subsection) prior to this one.
+Multiple `.previous' directives in a row will flip between two sections
+(and their subsections).
+
+   In terms of the section stack, this directive swaps the current
+section with the top section on the section stack.
+
+
+File: as.info,  Node: PopSection,  Next: Previous,  Prev: P2align,  Up: Pseudo Ops
+
+7.74 `.popsection'
+==================
+
+This is one of the ELF section stack manipulation directives.  The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.pushsection' (*note PushSection::), and `.previous'
+(*note Previous::).
+
+   This directive replaces the current section (and subsection) with
+the top section (and subsection) on the section stack.  This section is
+popped off the stack.
+
+
+File: as.info,  Node: Print,  Next: Protected,  Prev: Previous,  Up: Pseudo Ops
+
+7.75 `.print STRING'
+====================
+
+`as' will print STRING on the standard output during assembly.  You
+must put STRING in double quotes.
+
+
+File: as.info,  Node: Protected,  Next: Psize,  Prev: Print,  Up: Pseudo Ops
+
+7.76 `.protected NAMES'
+=======================
+
+This is one of the ELF visibility directives.  The other two are
+`.hidden' (*note Hidden::) and `.internal' (*note Internal::).
+
+   This directive overrides the named symbols default visibility (which
+is set by their binding: local, global or weak).  The directive sets
+the visibility to `protected' which means that any references to the
+symbols from within the components that defines them must be resolved
+to the definition in that component, even if a definition in another
+component would normally preempt this.
+
+
+File: as.info,  Node: Psize,  Next: Purgem,  Prev: Protected,  Up: Pseudo Ops
+
+7.77 `.psize LINES , COLUMNS'
+=============================
+
+Use this directive to declare the number of lines--and, optionally, the
+number of columns--to use for each page, when generating listings.
+
+   If you do not use `.psize', listings use a default line-count of 60.
+You may omit the comma and COLUMNS specification; the default width is
+200 columns.
+
+   `as' generates formfeeds whenever the specified number of lines is
+exceeded (or whenever you explicitly request one, using `.eject').
+
+   If you specify LINES as `0', no formfeeds are generated save those
+explicitly specified with `.eject'.
+
+
+File: as.info,  Node: Purgem,  Next: PushSection,  Prev: Psize,  Up: Pseudo Ops
+
+7.78 `.purgem NAME'
+===================
+
+Undefine the macro NAME, so that later uses of the string will not be
+expanded.  *Note Macro::.
+
+
+File: as.info,  Node: PushSection,  Next: Quad,  Prev: Purgem,  Up: Pseudo Ops
+
+7.79 `.pushsection NAME , SUBSECTION'
+=====================================
+
+This is one of the ELF section stack manipulation directives.  The
+others are `.section' (*note Section::), `.subsection' (*note
+SubSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+   This directive pushes the current section (and subsection) onto the
+top of the section stack, and then replaces the current section and
+subsection with `name' and `subsection'.
+
+
+File: as.info,  Node: Quad,  Next: Rept,  Prev: PushSection,  Up: Pseudo Ops
+
+7.80 `.quad BIGNUMS'
+====================
+
+`.quad' expects zero or more bignums, separated by commas.  For each
+bignum, it emits an 8-byte integer.  If the bignum won't fit in 8
+bytes, it prints a warning message; and just takes the lowest order 8
+bytes of the bignum.  
+
+   The term "quad" comes from contexts in which a "word" is two bytes;
+hence _quad_-word for 8 bytes.
+
+
+File: as.info,  Node: Rept,  Next: Sbttl,  Prev: Quad,  Up: Pseudo Ops
+
+7.81 `.rept COUNT'
+==================
+
+Repeat the sequence of lines between the `.rept' directive and the next
+`.endr' directive COUNT times.
+
+   For example, assembling
+
+             .rept   3
+             .long   0
+             .endr
+
+   is equivalent to assembling
+
+             .long   0
+             .long   0
+             .long   0
+
+
+File: as.info,  Node: Sbttl,  Next: Scl,  Prev: Rept,  Up: Pseudo Ops
+
+7.82 `.sbttl "SUBHEADING"'
+==========================
+
+Use SUBHEADING as the title (third line, immediately after the title
+line) when generating assembly listings.
+
+   This directive affects subsequent pages, as well as the current page
+if it appears within ten lines of the top of a page.
+
+
+File: as.info,  Node: Scl,  Next: Section,  Prev: Sbttl,  Up: Pseudo Ops
+
+7.83 `.scl CLASS'
+=================
+
+Set the storage-class value for a symbol.  This directive may only be
+used inside a `.def'/`.endef' pair.  Storage class may flag whether a
+symbol is static or external, or it may record further symbolic
+debugging information.
+
+
+File: as.info,  Node: Section,  Next: Set,  Prev: Scl,  Up: Pseudo Ops
+
+7.84 `.section NAME'
+====================
+
+Use the `.section' directive to assemble the following code into a
+section named NAME.
+
+   This directive is only supported for targets that actually support
+arbitrarily named sections; on `a.out' targets, for example, it is not
+accepted, even with a standard `a.out' section name.
+
+COFF Version
+------------
+
+   For COFF targets, the `.section' directive is used in one of the
+following ways:
+
+     .section NAME[, "FLAGS"]
+     .section NAME[, SUBSEGMENT]
+
+   If the optional argument is quoted, it is taken as flags to use for
+the section.  Each flag is a single character.  The following flags are
+recognized:
+`b'
+     bss section (uninitialized data)
+
+`n'
+     section is not loaded
+
+`w'
+     writable section
+
+`d'
+     data section
+
+`r'
+     read-only section
+
+`x'
+     executable section
+
+`s'
+     shared section (meaningful for PE targets)
+
+`a'
+     ignored.  (For compatibility with the ELF version)
+
+   If no flags are specified, the default flags depend upon the section
+name.  If the section name is not recognized, the default will be for
+the section to be loaded and writable.  Note the `n' and `w' flags
+remove attributes from the section, rather than adding them, so if they
+are used on their own it will be as if no flags had been specified at
+all.
+
+   If the optional argument to the `.section' directive is not quoted,
+it is taken as a subsegment number (*note Sub-Sections::).
+
+ELF Version
+-----------
+
+   This is one of the ELF section stack manipulation directives.  The
+others are `.subsection' (*note SubSection::), `.pushsection' (*note
+PushSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+   For ELF targets, the `.section' directive is used like this:
+
+     .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]]
+
+   The optional FLAGS argument is a quoted string which may contain any
+combination of the following characters:
+`a'
+     section is allocatable
+
+`w'
+     section is writable
+
+`x'
+     section is executable
+
+`M'
+     section is mergeable
+
+`S'
+     section contains zero terminated strings
+
+`G'
+     section is a member of a section group
+
+`T'
+     section is used for thread-local-storage
+
+   The optional TYPE argument may contain one of the following
+constants:
+`@progbits'
+     section contains data
+
+`@nobits'
+     section does not contain data (i.e., section only occupies space)
+
+`@note'
+     section contains data which is used by things other than the
+     program
+
+`@init_array'
+     section contains an array of pointers to init functions
+
+`@fini_array'
+     section contains an array of pointers to finish functions
+
+`@preinit_array'
+     section contains an array of pointers to pre-init functions
+
+   Many targets only support the first three section types.
+
+   Note on targets where the `@' character is the start of a comment (eg
+ARM) then another character is used instead.  For example the ARM port
+uses the `%' character.
+
+   If FLAGS contains the `M' symbol then the TYPE argument must be
+specified as well as an extra argument - ENTSIZE - like this:
+
+     .section NAME , "FLAGS"M, @TYPE, ENTSIZE
+
+   Sections with the `M' flag but not `S' flag must contain fixed size
+constants, each ENTSIZE octets long. Sections with both `M' and `S'
+must contain zero terminated strings where each character is ENTSIZE
+bytes long. The linker may remove duplicates within sections with the
+same name, same entity size and same flags.  ENTSIZE must be an
+absolute expression.
+
+   If FLAGS contains the `G' symbol then the TYPE argument must be
+present along with an additional field like this:
+
+     .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE]
+
+   The GROUPNAME field specifies the name of the section group to which
+this particular section belongs.  The optional linkage field can
+contain:
+`comdat'
+     indicates that only one copy of this section should be retained
+
+`.gnu.linkonce'
+     an alias for comdat
+
+   Note - if both the M and G flags are present then the fields for the
+Merge flag should come first, like this:
+
+     .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE]
+
+   If no flags are specified, the default flags depend upon the section
+name.  If the section name is not recognized, the default will be for
+the section to have none of the above flags: it will not be allocated
+in memory, nor writable, nor executable.  The section will contain data.
+
+   For ELF targets, the assembler supports another type of `.section'
+directive for compatibility with the Solaris assembler:
+
+     .section "NAME"[, FLAGS...]
+
+   Note that the section name is quoted.  There may be a sequence of
+comma separated flags:
+`#alloc'
+     section is allocatable
+
+`#write'
+     section is writable
+
+`#execinstr'
+     section is executable
+
+`#tls'
+     section is used for thread local storage
+
+   This directive replaces the current section and subsection.  See the
+contents of the gas testsuite directory `gas/testsuite/gas/elf' for
+some examples of how this directive and the other section stack
+directives work.
+
+
+File: as.info,  Node: Set,  Next: Short,  Prev: Section,  Up: Pseudo Ops
+
+7.85 `.set SYMBOL, EXPRESSION'
+==============================
+
+Set the value of SYMBOL to EXPRESSION.  This changes SYMBOL's value and
+type to conform to EXPRESSION.  If SYMBOL was flagged as external, it
+remains flagged (*note Symbol Attributes::).
+
+   You may `.set' a symbol many times in the same assembly.
+
+   If you `.set' a global symbol, the value stored in the object file
+is the last value stored into it.
+
+   The syntax for `set' on the HPPA is `SYMBOL .set EXPRESSION'.
+
+   On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION'
+instead.
+
+
+File: as.info,  Node: Short,  Next: Single,  Prev: Set,  Up: Pseudo Ops
+
+7.86 `.short EXPRESSIONS'
+=========================
+
+`.short' is normally the same as `.word'.  *Note `.word': Word.
+
+   In some configurations, however, `.short' and `.word' generate
+numbers of different lengths; *note Machine Dependencies::.
+
+
+File: as.info,  Node: Single,  Next: Size,  Prev: Short,  Up: Pseudo Ops
+
+7.87 `.single FLONUMS'
+======================
+
+This directive assembles zero or more flonums, separated by commas.  It
+has the same effect as `.float'.  The exact kind of floating point
+numbers emitted depends on how `as' is configured.  *Note Machine
+Dependencies::.
+
+
+File: as.info,  Node: Size,  Next: Skip,  Prev: Single,  Up: Pseudo Ops
+
+7.88 `.size'
+============
+
+This directive is used to set the size associated with a symbol.
+
+COFF Version
+------------
+
+   For COFF targets, the `.size' directive is only permitted inside
+`.def'/`.endef' pairs.  It is used like this:
+
+     .size EXPRESSION
+
+ELF Version
+-----------
+
+   For ELF targets, the `.size' directive is used like this:
+
+     .size NAME , EXPRESSION
+
+   This directive sets the size associated with a symbol NAME.  The
+size in bytes is computed from EXPRESSION which can make use of label
+arithmetic.  This directive is typically used to set the size of
+function symbols.
+
+
+File: as.info,  Node: Sleb128,  Next: Space,  Prev: Skip,  Up: Pseudo Ops
+
+7.89 `.sleb128 EXPRESSIONS'
+===========================
+
+SLEB128 stands for "signed little endian base 128."  This is a compact,
+variable length representation of numbers used by the DWARF symbolic
+debugging format.  *Note `.uleb128': Uleb128.
+
+
+File: as.info,  Node: Skip,  Next: Sleb128,  Prev: Size,  Up: Pseudo Ops
+
+7.90 `.skip SIZE , FILL'
+========================
+
+This directive emits SIZE bytes, each of value FILL.  Both SIZE and
+FILL are absolute expressions.  If the comma and FILL are omitted, FILL
+is assumed to be zero.  This is the same as `.space'.
+
+
+File: as.info,  Node: Space,  Next: Stab,  Prev: Sleb128,  Up: Pseudo Ops
+
+7.91 `.space SIZE , FILL'
+=========================
+
+This directive emits SIZE bytes, each of value FILL.  Both SIZE and
+FILL are absolute expressions.  If the comma and FILL are omitted, FILL
+is assumed to be zero.  This is the same as `.skip'.
+
+     _Warning:_ `.space' has a completely different meaning for HPPA
+     targets; use `.block' as a substitute.  See `HP9000 Series 800
+     Assembly Language Reference Manual' (HP 92432-90001) for the
+     meaning of the `.space' directive.  *Note HPPA Assembler
+     Directives: HPPA Directives, for a summary.
+
+
+File: as.info,  Node: Stab,  Next: String,  Prev: Space,  Up: Pseudo Ops
+
+7.92 `.stabd, .stabn, .stabs'
+=============================
+
+There are three directives that begin `.stab'.  All emit symbols (*note
+Symbols::), for use by symbolic debuggers.  The symbols are not entered
+in the `as' hash table: they cannot be referenced elsewhere in the
+source file.  Up to five fields are required:
+
+STRING
+     This is the symbol's name.  It may contain any character except
+     `\000', so is more general than ordinary symbol names.  Some
+     debuggers used to code arbitrarily complex structures into symbol
+     names using this field.
+
+TYPE
+     An absolute expression.  The symbol's type is set to the low 8
+     bits of this expression.  Any bit pattern is permitted, but `ld'
+     and debuggers choke on silly bit patterns.
+
+OTHER
+     An absolute expression.  The symbol's "other" attribute is set to
+     the low 8 bits of this expression.
+
+DESC
+     An absolute expression.  The symbol's descriptor is set to the low
+     16 bits of this expression.
+
+VALUE
+     An absolute expression which becomes the symbol's value.
+
+   If a warning is detected while reading a `.stabd', `.stabn', or
+`.stabs' statement, the symbol has probably already been created; you
+get a half-formed symbol in your object file.  This is compatible with
+earlier assemblers!
+
+`.stabd TYPE , OTHER , DESC'
+     The "name" of the symbol generated is not even an empty string.
+     It is a null pointer, for compatibility.  Older assemblers used a
+     null pointer so they didn't waste space in object files with empty
+     strings.
+
+     The symbol's value is set to the location counter, relocatably.
+     When your program is linked, the value of this symbol is the
+     address of the location counter when the `.stabd' was assembled.
+
+`.stabn TYPE , OTHER , DESC , VALUE'
+     The name of the symbol is set to the empty string `""'.
+
+`.stabs STRING ,  TYPE , OTHER , DESC , VALUE'
+     All five fields are specified.
+
+
+File: as.info,  Node: String,  Next: Struct,  Prev: Stab,  Up: Pseudo Ops
+
+7.93 `.string' "STR"
+====================
+
+Copy the characters in STR to the object file.  You may specify more
+than one string to copy, separated by commas.  Unless otherwise
+specified for a particular machine, the assembler marks the end of each
+string with a 0 byte.  You can use any of the escape sequences
+described in *Note Strings: Strings.
+
+
+File: as.info,  Node: Struct,  Next: SubSection,  Prev: String,  Up: Pseudo Ops
+
+7.94 `.struct EXPRESSION'
+=========================
+
+Switch to the absolute section, and set the section offset to
+EXPRESSION, which must be an absolute expression.  You might use this
+as follows:
+             .struct 0
+     field1:
+             .struct field1 + 4
+     field2:
+             .struct field2 + 4
+     field3:
+   This would define the symbol `field1' to have the value 0, the symbol
+`field2' to have the value 4, and the symbol `field3' to have the value
+8.  Assembly would be left in the absolute section, and you would need
+to use a `.section' directive of some sort to change to some other
+section before further assembly.
+
+
+File: as.info,  Node: SubSection,  Next: Symver,  Prev: Struct,  Up: Pseudo Ops
+
+7.95 `.subsection NAME'
+=======================
+
+This is one of the ELF section stack manipulation directives.  The
+others are `.section' (*note Section::), `.pushsection' (*note
+PushSection::), `.popsection' (*note PopSection::), and `.previous'
+(*note Previous::).
+
+   This directive replaces the current subsection with `name'.  The
+current section is not changed.  The replaced subsection is put onto
+the section stack in place of the then current top of stack subsection.
+
+
+File: as.info,  Node: Symver,  Next: Tag,  Prev: SubSection,  Up: Pseudo Ops
+
+7.96 `.symver'
+==============
+
+Use the `.symver' directive to bind symbols to specific version nodes
+within a source file.  This is only supported on ELF platforms, and is
+typically used when assembling files to be linked into a shared library.
+There are cases where it may make sense to use this in objects to be
+bound into an application itself so as to override a versioned symbol
+from a shared library.
+
+   For ELF targets, the `.symver' directive can be used like this:
+     .symver NAME, NAME2@NODENAME
+   If the symbol NAME is defined within the file being assembled, the
+`.symver' directive effectively creates a symbol alias with the name
+NAME2@NODENAME, and in fact the main reason that we just don't try and
+create a regular alias is that the @ character isn't permitted in
+symbol names.  The NAME2 part of the name is the actual name of the
+symbol by which it will be externally referenced.  The name NAME itself
+is merely a name of convenience that is used so that it is possible to
+have definitions for multiple versions of a function within a single
+source file, and so that the compiler can unambiguously know which
+version of a function is being mentioned.  The NODENAME portion of the
+alias should be the name of a node specified in the version script
+supplied to the linker when building a shared library.  If you are
+attempting to override a versioned symbol from a shared library, then
+NODENAME should correspond to the nodename of the symbol you are trying
+to override.
+
+   If the symbol NAME is not defined within the file being assembled,
+all references to NAME will be changed to NAME2@NODENAME.  If no
+reference to NAME is made, NAME2@NODENAME will be removed from the
+symbol table.
+
+   Another usage of the `.symver' directive is:
+     .symver NAME, NAME2@@NODENAME
+   In this case, the symbol NAME must exist and be defined within the
+file being assembled. It is similar to NAME2@NODENAME. The difference
+is NAME2@@NODENAME will also be used to resolve references to NAME2 by
+the linker.
+
+   The third usage of the `.symver' directive is:
+     .symver NAME, NAME2@@@NODENAME
+   When NAME is not defined within the file being assembled, it is
+treated as NAME2@NODENAME. When NAME is defined within the file being
+assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME.
+
+
+File: as.info,  Node: Tag,  Next: Text,  Prev: Symver,  Up: Pseudo Ops
+
+7.97 `.tag STRUCTNAME'
+======================
+
+This directive is generated by compilers to include auxiliary debugging
+information in the symbol table.  It is only permitted inside
+`.def'/`.endef' pairs.  Tags are used to link structure definitions in
+the symbol table with instances of those structures.
+
+
+File: as.info,  Node: Text,  Next: Title,  Prev: Tag,  Up: Pseudo Ops
+
+7.98 `.text SUBSECTION'
+=======================
+
+Tells `as' to assemble the following statements onto the end of the
+text subsection numbered SUBSECTION, which is an absolute expression.
+If SUBSECTION is omitted, subsection number zero is used.
+
+
+File: as.info,  Node: Title,  Next: Type,  Prev: Text,  Up: Pseudo Ops
+
+7.99 `.title "HEADING"'
+=======================
+
+Use HEADING as the title (second line, immediately after the source
+file name and pagenumber) when generating assembly listings.
+
+   This directive affects subsequent pages, as well as the current page
+if it appears within ten lines of the top of a page.
+
+
+File: as.info,  Node: Type,  Next: Uleb128,  Prev: Title,  Up: Pseudo Ops
+
+7.100 `.type'
+=============
+
+This directive is used to set the type of a symbol.
+
+COFF Version
+------------
+
+   For COFF targets, this directive is permitted only within
+`.def'/`.endef' pairs.  It is used like this:
+
+     .type INT
+
+   This records the integer INT as the type attribute of a symbol table
+entry.
+
+ELF Version
+-----------
+
+   For ELF targets, the `.type' directive is used like this:
+
+     .type NAME , TYPE DESCRIPTION
+
+   This sets the type of symbol NAME to be either a function symbol or
+an object symbol.  There are five different syntaxes supported for the
+TYPE DESCRIPTION field, in order to provide compatibility with various
+other assemblers.  The syntaxes supported are:
+
+       .type <name>,#function
+       .type <name>,#object
+
+       .type <name>,@function
+       .type <name>,@object
+
+       .type <name>,%function
+       .type <name>,%object
+
+       .type <name>,"function"
+       .type <name>,"object"
+
+       .type <name> STT_FUNCTION
+       .type <name> STT_OBJECT
+
+
+File: as.info,  Node: Uleb128,  Next: Val,  Prev: Type,  Up: Pseudo Ops
+
+7.101 `.uleb128 EXPRESSIONS'
+============================
+
+ULEB128 stands for "unsigned little endian base 128."  This is a
+compact, variable length representation of numbers used by the DWARF
+symbolic debugging format.  *Note `.sleb128': Sleb128.
+
+
+File: as.info,  Node: Val,  Next: Version,  Prev: Uleb128,  Up: Pseudo Ops
+
+7.102 `.val ADDR'
+=================
+
+This directive, permitted only within `.def'/`.endef' pairs, records
+the address ADDR as the value attribute of a symbol table entry.
+
+
+File: as.info,  Node: Version,  Next: VTableEntry,  Prev: Val,  Up: Pseudo Ops
+
+7.103 `.version "STRING"'
+=========================
+
+This directive creates a `.note' section and places into it an ELF
+formatted note of type NT_VERSION.  The note's name is set to `string'.
+
+
+File: as.info,  Node: VTableEntry,  Next: VTableInherit,  Prev: Version,  Up: Pseudo Ops
+
+7.104 `.vtable_entry TABLE, OFFSET'
+===================================
+
+This directive finds or creates a symbol `table' and creates a
+`VTABLE_ENTRY' relocation for it with an addend of `offset'.
+
+
+File: as.info,  Node: VTableInherit,  Next: Warning,  Prev: VTableEntry,  Up: Pseudo Ops
+
+7.105 `.vtable_inherit CHILD, PARENT'
+=====================================
+
+This directive finds the symbol `child' and finds or creates the symbol
+`parent' and then creates a `VTABLE_INHERIT' relocation for the parent
+whose addend is the value of the child symbol.  As a special case the
+parent name of `0' is treated as refering the `*ABS*' section.
+
+
+File: as.info,  Node: Warning,  Next: Weak,  Prev: VTableInherit,  Up: Pseudo Ops
+
+7.106 `.warning "STRING"'
+=========================
+
+Similar to the directive `.error' (*note `.error "STRING"': Error.),
+but just emits a warning.
+
+
+File: as.info,  Node: Weak,  Next: Weakref,  Prev: Warning,  Up: Pseudo Ops
+
+7.107 `.weak NAMES'
+===================
+
+This directive sets the weak attribute on the comma separated list of
+symbol `names'.  If the symbols do not already exist, they will be
+created.
+
+   On COFF targets other than PE, weak symbols are a GNU extension.
+This directive sets the weak attribute on the comma separated list of
+symbol `names'.  If the symbols do not already exist, they will be
+created.
+
+   On the PE target, weak symbols are supported natively as weak
+aliases.  When a weak symbol is created that is not an alias, GAS
+creates an alternate symbol to hold the default value.
+
+
+File: as.info,  Node: Weakref,  Next: Word,  Prev: Weak,  Up: Pseudo Ops
+
+7.108 `.weakref ALIAS, TARGET'
+==============================
+
+This directive creates an alias to the target symbol that enables the
+symbol to be referenced with weak-symbol semantics, but without
+actually making it weak.  If direct references or definitions of the
+symbol are present, then the symbol will not be weak, but if all
+references to it are through weak references, the symbol will be marked
+as weak in the symbol table.
+
+   The effect is equivalent to moving all references to the alias to a
+separate assembly source file, renaming the alias to the symbol in it,
+declaring the symbol as weak there, and running a reloadable link to
+merge the object files resulting from the assembly of the new source
+file and the old source file that had the references to the alias
+removed.
+
+   The alias itself never makes to the symbol table, and is entirely
+handled within the assembler.
+
+
+File: as.info,  Node: Word,  Next: Deprecated,  Prev: Weakref,  Up: Pseudo Ops
+
+7.109 `.word EXPRESSIONS'
+=========================
+
+This directive expects zero or more EXPRESSIONS, of any section,
+separated by commas.
+
+   The size of the number emitted, and its byte order, depend on what
+target computer the assembly is for.
+
+     _Warning: Special Treatment to support Compilers_
+
+   Machines with a 32-bit address space, but that do less than 32-bit
+addressing, require the following special treatment.  If the machine of
+interest to you does 32-bit addressing (or doesn't require it; *note
+Machine Dependencies::), you can ignore this issue.
+
+   In order to assemble compiler output into something that works, `as'
+occasionally does strange things to `.word' directives.  Directives of
+the form `.word sym1-sym2' are often emitted by compilers as part of
+jump tables.  Therefore, when `as' assembles a directive of the form
+`.word sym1-sym2', and the difference between `sym1' and `sym2' does
+not fit in 16 bits, `as' creates a "secondary jump table", immediately
+before the next label.  This secondary jump table is preceded by a
+short-jump to the first byte after the secondary table.  This
+short-jump prevents the flow of control from accidentally falling into
+the new table.  Inside the table is a long-jump to `sym2'.  The
+original `.word' contains `sym1' minus the address of the long-jump to
+`sym2'.
+
+   If there were several occurrences of `.word sym1-sym2' before the
+secondary jump table, all of them are adjusted.  If there was a `.word
+sym3-sym4', that also did not fit in sixteen bits, a long-jump to
+`sym4' is included in the secondary jump table, and the `.word'
+directives are adjusted to contain `sym3' minus the address of the
+long-jump to `sym4'; and so on, for as many entries in the original
+jump table as necessary.
+
+
+File: as.info,  Node: Deprecated,  Prev: Word,  Up: Pseudo Ops
+
+7.110 Deprecated Directives
+===========================
+
+One day these directives won't work.  They are included for
+compatibility with older assemblers.
+.abort
+
+.line
+
+
+File: as.info,  Node: Machine Dependencies,  Next: Reporting Bugs,  Prev: Pseudo Ops,  Up: Top
+
+8 Machine Dependent Features
+****************************
+
+The machine instruction sets are (almost by definition) different on
+each machine where `as' runs.  Floating point representations vary as
+well, and `as' often supports a few additional directives or
+command-line options for compatibility with other assemblers on a
+particular platform.  Finally, some versions of `as' support special
+pseudo-instructions for branch optimization.
+
+   This chapter discusses most of these differences, though it does not
+include details on any machine's instruction set.  For details on that
+subject, see the hardware manufacturer's manual.
+
+* Menu:
+
+
+* Alpha-Dependent::		Alpha Dependent Features
+
+* ARC-Dependent::               ARC Dependent Features
+
+* ARM-Dependent::               ARM Dependent Features
+
+* BFIN-Dependent::		BFIN Dependent Features
+
+* CRIS-Dependent::              CRIS Dependent Features
+
+* D10V-Dependent::              D10V Dependent Features
+
+* D30V-Dependent::              D30V Dependent Features
+
+* H8/300-Dependent::            Renesas H8/300 Dependent Features
+
+* HPPA-Dependent::              HPPA Dependent Features
+
+* ESA/390-Dependent::           IBM ESA/390 Dependent Features
+
+* i386-Dependent::              Intel 80386 and AMD x86-64 Dependent Features
+
+* i860-Dependent::              Intel 80860 Dependent Features
+
+* i960-Dependent::              Intel 80960 Dependent Features
+
+* IA-64-Dependent::             Intel IA-64 Dependent Features
+
+* IP2K-Dependent::              IP2K Dependent Features
+
+* M32C-Dependent::              M32C Dependent Features
+
+* M32R-Dependent::              M32R Dependent Features
+
+* M68K-Dependent::              M680x0 Dependent Features
+
+* M68HC11-Dependent::           M68HC11 and 68HC12 Dependent Features
+
+* MIPS-Dependent::              MIPS Dependent Features
+
+* MMIX-Dependent::              MMIX Dependent Features
+
+* MSP430-Dependent::		MSP430 Dependent Features
+
+* SH-Dependent::                Renesas / SuperH SH Dependent Features
+* SH64-Dependent::              SuperH SH64 Dependent Features
+
+* PDP-11-Dependent::            PDP-11 Dependent Features
+
+* PJ-Dependent::                picoJava Dependent Features
+
+* PPC-Dependent::               PowerPC Dependent Features
+
+* Sparc-Dependent::             SPARC Dependent Features
+
+* TIC54X-Dependent::            TI TMS320C54x Dependent Features
+
+* V850-Dependent::              V850 Dependent Features
+
+* Xtensa-Dependent::            Xtensa Dependent Features
+
+* Z80-Dependent::               Z80 Dependent Features
+
+* Z8000-Dependent::             Z8000 Dependent Features
+
+* Vax-Dependent::               VAX Dependent Features
+
+
+File: as.info,  Node: Alpha-Dependent,  Next: ARC-Dependent,  Up: Machine Dependencies
+
+8.1 Alpha Dependent Features
+============================
+
+* Menu:
+
+* Alpha Notes::                Notes
+* Alpha Options::              Options
+* Alpha Syntax::               Syntax
+* Alpha Floating Point::       Floating Point
+* Alpha Directives::           Alpha Machine Directives
+* Alpha Opcodes::              Opcodes
+
+
+File: as.info,  Node: Alpha Notes,  Next: Alpha Options,  Up: Alpha-Dependent
+
+8.1.1 Notes
+-----------
+
+The documentation here is primarily for the ELF object format.  `as'
+also supports the ECOFF and EVAX formats, but features specific to
+these formats are not yet documented.
+
+
+File: as.info,  Node: Alpha Options,  Next: Alpha Syntax,  Prev: Alpha Notes,  Up: Alpha-Dependent
+
+8.1.2 Options
+-------------
+
+`-mCPU'
+     This option specifies the target processor.  If an attempt is made
+     to assemble an instruction which will not execute on the target
+     processor, the assembler may either expand the instruction as a
+     macro or issue an error message.  This option is equivalent to the
+     `.arch' directive.
+
+     The following processor names are recognized: `21064', `21064a',
+     `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a',
+     `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6',
+     `ev67', `ev68'.  The special name `all' may be used to allow the
+     assembler to accept instructions valid for any Alpha processor.
+
+     In order to support existing practice in OSF/1 with respect to
+     `.arch', and existing practice within `MILO' (the Linux ARC
+     bootloader), the numbered processor names (e.g. 21064) enable the
+     processor-specific PALcode instructions, while the
+     "electro-vlasic" names (e.g. `ev4') do not.
+
+`-mdebug'
+`-no-mdebug'
+     Enables or disables the generation of `.mdebug' encapsulation for
+     stabs directives and procedure descriptors.  The default is to
+     automatically enable `.mdebug' when the first stabs directive is
+     seen.
+
+`-relax'
+     This option forces all relocations to be put into the object file,
+     instead of saving space and resolving some relocations at assembly
+     time.  Note that this option does not propagate all symbol
+     arithmetic into the object file, because not all symbol arithmetic
+     can be represented.  However, the option can still be useful in
+     specific applications.
+
+`-g'
+     This option is used when the compiler generates debug information.
+     When `gcc' is using `mips-tfile' to generate debug information
+     for ECOFF, local labels must be passed through to the object file.
+     Otherwise this option has no effect.
+
+`-GSIZE'
+     A local common symbol larger than SIZE is placed in `.bss', while
+     smaller symbols are placed in `.sbss'.
+
+`-F'
+`-32addr'
+     These options are ignored for backward compatibility.
+
+
+File: as.info,  Node: Alpha Syntax,  Next: Alpha Floating Point,  Prev: Alpha Options,  Up: Alpha-Dependent
+
+8.1.3 Syntax
+------------
+
+The assembler syntax closely follow the Alpha Reference Manual;
+assembler directives and general syntax closely follow the OSF/1 and
+OpenVMS syntax, with a few differences for ELF.
+
+* Menu:
+
+* Alpha-Chars::                Special Characters
+* Alpha-Regs::                 Register Names
+* Alpha-Relocs::               Relocations
+
+
+File: as.info,  Node: Alpha-Chars,  Next: Alpha-Regs,  Up: Alpha Syntax
+
+8.1.3.1 Special Characters
+..........................
+
+`#' is the line comment character.
+
+   `;' can be used instead of a newline to separate statements.
+
+
+File: as.info,  Node: Alpha-Regs,  Next: Alpha-Relocs,  Prev: Alpha-Chars,  Up: Alpha Syntax
+
+8.1.3.2 Register Names
+......................
+
+The 32 integer registers are referred to as `$N' or `$rN'.  In
+addition, registers 15, 28, 29, and 30 may be referred to by the
+symbols `$fp', `$at', `$gp', and `$sp' respectively.
+
+   The 32 floating-point registers are referred to as `$fN'.
+
+
+File: as.info,  Node: Alpha-Relocs,  Prev: Alpha-Regs,  Up: Alpha Syntax
+
+8.1.3.3 Relocations
+...................
+
+Some of these relocations are available for ECOFF, but mostly only for
+ELF.  They are modeled after the relocation format introduced in
+Digital Unix 4.0, but there are additions.
+
+   The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the
+relocation.  In some cases NUMBER is used to relate specific
+instructions.
+
+   The relocation is placed at the end of the instruction like so:
+
+     ldah  $0,a($29)    !gprelhigh
+     lda   $0,a($0)     !gprellow
+     ldq   $1,b($29)    !literal!100
+     ldl   $2,0($1)     !lituse_base!100
+
+`!literal'
+`!literal!N'
+     Used with an `ldq' instruction to load the address of a symbol
+     from the GOT.
+
+     A sequence number N is optional, and if present is used to pair
+     `lituse' relocations with this `literal' relocation.  The `lituse'
+     relocations are used by the linker to optimize the code based on
+     the final location of the symbol.
+
+     Note that these optimizations are dependent on the data flow of the
+     program.  Therefore, if _any_ `lituse' is paired with a `literal'
+     relocation, then _all_ uses of the register set by the `literal'
+     instruction must also be marked with `lituse' relocations.  This
+     is because the original `literal' instruction may be deleted or
+     transformed into another instruction.
+
+     Also note that there may be a one-to-many relationship between
+     `literal' and `lituse', but not a many-to-one.  That is, if there
+     are two code paths that load up the same address and feed the
+     value to a single use, then the use may not use a `lituse'
+     relocation.
+
+`!lituse_base!N'
+     Used with any memory format instruction (e.g. `ldl') to indicate
+     that the literal is used for an address load.  The offset field of
+     the instruction must be zero.  During relaxation, the code may be
+     altered to use a gp-relative load.
+
+`!lituse_jsr!N'
+     Used with a register branch format instruction (e.g. `jsr') to
+     indicate that the literal is used for a call.  During relaxation,
+     the code may be altered to use a direct branch (e.g. `bsr').
+
+`!lituse_jsrdirect!N'
+     Similar to `lituse_jsr', but also that this call cannot be vectored
+     through a PLT entry.  This is useful for functions with special
+     calling conventions which do not allow the normal call-clobbered
+     registers to be clobbered.
+
+`!lituse_bytoff!N'
+     Used with a byte mask instruction (e.g. `extbl') to indicate that
+     only the low 3 bits of the address are relevant.  During
+     relaxation, the code may be altered to use an immediate instead of
+     a register shift.
+
+`!lituse_addr!N'
+     Used with any other instruction to indicate that the original
+     address is in fact used, and the original `ldq' instruction may
+     not be altered or deleted.  This is useful in conjunction with
+     `lituse_jsr' to test whether a weak symbol is defined.
+
+          ldq  $27,foo($29)   !literal!1
+          beq  $27,is_undef   !lituse_addr!1
+          jsr  $26,($27),foo  !lituse_jsr!1
+
+`!lituse_tlsgd!N'
+     Used with a register branch format instruction to indicate that the
+     literal is the call to `__tls_get_addr' used to compute the
+     address of the thread-local storage variable whose descriptor was
+     loaded with `!tlsgd!N'.
+
+`!lituse_tlsldm!N'
+     Used with a register branch format instruction to indicate that the
+     literal is the call to `__tls_get_addr' used to compute the
+     address of the base of the thread-local storage block for the
+     current module.  The descriptor for the module must have been
+     loaded with `!tlsldm!N'.
+
+`!gpdisp!N'
+     Used with `ldah' and `lda' to load the GP from the current
+     address, a-la the `ldgp' macro.  The source register for the
+     `ldah' instruction must contain the address of the `ldah'
+     instruction.  There must be exactly one `lda' instruction paired
+     with the `ldah' instruction, though it may appear anywhere in the
+     instruction stream.  The immediate operands must be zero.
+
+          bsr  $26,foo
+          ldah $29,0($26)     !gpdisp!1
+          lda  $29,0($29)     !gpdisp!1
+
+`!gprelhigh'
+     Used with an `ldah' instruction to add the high 16 bits of a
+     32-bit displacement from the GP.
+
+`!gprellow'
+     Used with any memory format instruction to add the low 16 bits of a
+     32-bit displacement from the GP.
+
+`!gprel'
+     Used with any memory format instruction to add a 16-bit
+     displacement from the GP.
+
+`!samegp'
+     Used with any branch format instruction to skip the GP load at the
+     target address.  The referenced symbol must have the same GP as the
+     source object file, and it must be declared to either not use `$27'
+     or perform a standard GP load in the first two instructions via the
+     `.prologue' directive.
+
+`!tlsgd'
+`!tlsgd!N'
+     Used with an `lda' instruction to load the address of a TLS
+     descriptor for a symbol in the GOT.
+
+     The sequence number N is optional, and if present it used to pair
+     the descriptor load with both the `literal' loading the address of
+     the `__tls_get_addr' function and the `lituse_tlsgd' marking the
+     call to that function.
+
+     For proper relaxation, both the `tlsgd', `literal' and `lituse'
+     relocations must be in the same extended basic block.  That is,
+     the relocation with the lowest address must be executed first at
+     runtime.
+
+`!tlsldm'
+`!tlsldm!N'
+     Used with an `lda' instruction to load the address of a TLS
+     descriptor for the current module in the GOT.
+
+     Similar in other respects to `tlsgd'.
+
+`!gotdtprel'
+     Used with an `ldq' instruction to load the offset of the TLS
+     symbol within its module's thread-local storage block.  Also known
+     as the dynamic thread pointer offset or dtp-relative offset.
+
+`!dtprelhi'
+`!dtprello'
+`!dtprel'
+     Like `gprel' relocations except they compute dtp-relative offsets.
+
+`!gottprel'
+     Used with an `ldq' instruction to load the offset of the TLS
+     symbol from the thread pointer.  Also known as the tp-relative
+     offset.
+
+`!tprelhi'
+`!tprello'
+`!tprel'
+     Like `gprel' relocations except they compute tp-relative offsets.
+
+
+File: as.info,  Node: Alpha Floating Point,  Next: Alpha Directives,  Prev: Alpha Syntax,  Up: Alpha-Dependent
+
+8.1.4 Floating Point
+--------------------
+
+The Alpha family uses both IEEE and VAX floating-point numbers.
+
+
+File: as.info,  Node: Alpha Directives,  Next: Alpha Opcodes,  Prev: Alpha Floating Point,  Up: Alpha-Dependent
+
+8.1.5 Alpha Assembler Directives
+--------------------------------
+
+`as' for the Alpha supports many additional directives for
+compatibility with the native assembler.  This section describes them
+only briefly.
+
+   These are the additional directives in `as' for the Alpha:
+
+`.arch CPU'
+     Specifies the target processor.  This is equivalent to the `-mCPU'
+     command-line option.  *Note Options: Alpha Options, for a list of
+     values for CPU.
+
+`.ent FUNCTION[, N]'
+     Mark the beginning of FUNCTION.  An optional number may follow for
+     compatibility with the OSF/1 assembler, but is ignored.  When
+     generating `.mdebug' information, this will create a procedure
+     descriptor for the function.  In ELF, it will mark the symbol as a
+     function a-la the generic `.type' directive.
+
+`.end FUNCTION'
+     Mark the end of FUNCTION.  In ELF, it will set the size of the
+     symbol a-la the generic `.size' directive.
+
+`.mask MASK, OFFSET'
+     Indicate which of the integer registers are saved in the current
+     function's stack frame.  MASK is interpreted a bit mask in which
+     bit N set indicates that register N is saved.  The registers are
+     saved in a block located OFFSET bytes from the "canonical frame
+     address" (CFA) which is the value of the stack pointer on entry to
+     the function.  The registers are saved sequentially, except that
+     the return address register (normally `$26') is saved first.
+
+     This and the other directives that describe the stack frame are
+     currently only used when generating `.mdebug' information.  They
+     may in the future be used to generate DWARF2 `.debug_frame' unwind
+     information for hand written assembly.
+
+`.fmask MASK, OFFSET'
+     Indicate which of the floating-point registers are saved in the
+     current stack frame.  The MASK and OFFSET parameters are
+     interpreted as with `.mask'.
+
+`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]'
+     Describes the shape of the stack frame.  The frame pointer in use
+     is FRAMEREG; normally this is either `$fp' or `$sp'.  The frame
+     pointer is FRAMEOFFSET bytes below the CFA.  The return address is
+     initially located in RETREG until it is saved as indicated in
+     `.mask'.  For compatibility with OSF/1 an optional ARGOFFSET
+     parameter is accepted and ignored.  It is believed to indicate the
+     offset from the CFA to the saved argument registers.
+
+`.prologue N'
+     Indicate that the stack frame is set up and all registers have been
+     spilled.  The argument N indicates whether and how the function
+     uses the incoming "procedure vector" (the address of the called
+     function) in `$27'.  0 indicates that `$27' is not used; 1
+     indicates that the first two instructions of the function use `$27'
+     to perform a load of the GP register; 2 indicates that `$27' is
+     used in some non-standard way and so the linker cannot elide the
+     load of the procedure vector during relaxation.
+
+`.usepv FUNCTION, WHICH'
+     Used to indicate the use of the `$27' register, similar to
+     `.prologue', but without the other semantics of needing to be
+     inside an open `.ent'/`.end' block.
+
+     The WHICH argument should be either `no', indicating that `$27' is
+     not used, or `std', indicating that the first two instructions of
+     the function perform a GP load.
+
+     One might use this directive instead of `.prologue' if you are
+     also using dwarf2 CFI directives.
+
+`.gprel32 EXPRESSION'
+     Computes the difference between the address in EXPRESSION and the
+     GP for the current object file, and stores it in 4 bytes.  In
+     addition to being smaller than a full 8 byte address, this also
+     does not require a dynamic relocation when used in a shared
+     library.
+
+`.t_floating EXPRESSION'
+     Stores EXPRESSION as an IEEE double precision value.
+
+`.s_floating EXPRESSION'
+     Stores EXPRESSION as an IEEE single precision value.
+
+`.f_floating EXPRESSION'
+     Stores EXPRESSION as a VAX F format value.
+
+`.g_floating EXPRESSION'
+     Stores EXPRESSION as a VAX G format value.
+
+`.d_floating EXPRESSION'
+     Stores EXPRESSION as a VAX D format value.
+
+`.set FEATURE'
+     Enables or disables various assembler features.  Using the positive
+     name of the feature enables while using `noFEATURE' disables.
+
+    `at'
+          Indicates that macro expansions may clobber the "assembler
+          temporary" (`$at' or `$28') register.  Some macros may not be
+          expanded without this and will generate an error message if
+          `noat' is in effect.  When `at' is in effect, a warning will
+          be generated if `$at' is used by the programmer.
+
+    `macro'
+          Enables the expansion of macro instructions.  Note that
+          variants of real instructions, such as `br label' vs `br
+          $31,label' are considered alternate forms and not macros.
+
+    `move'
+    `reorder'
+    `volatile'
+          These control whether and how the assembler may re-order
+          instructions.  Accepted for compatibility with the OSF/1
+          assembler, but `as' does not do instruction scheduling, so
+          these features are ignored.
+
+   The following directives are recognized for compatibility with the
+OSF/1 assembler but are ignored.
+
+     .proc           .aproc
+     .reguse         .livereg
+     .option         .aent
+     .ugen           .eflag
+     .alias          .noalias
+
+
+File: as.info,  Node: Alpha Opcodes,  Prev: Alpha Directives,  Up: Alpha-Dependent
+
+8.1.6 Opcodes
+-------------
+
+For detailed information on the Alpha machine instruction set, see the
+Alpha Architecture Handbook
+(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf).
+
+
+File: as.info,  Node: ARC-Dependent,  Next: ARM-Dependent,  Prev: Alpha-Dependent,  Up: Machine Dependencies
+
+8.2 ARC Dependent Features
+==========================
+
+* Menu:
+
+* ARC Options::              Options
+* ARC Syntax::               Syntax
+* ARC Floating Point::       Floating Point
+* ARC Directives::           ARC Machine Directives
+* ARC Opcodes::              Opcodes
+
+
+File: as.info,  Node: ARC Options,  Next: ARC Syntax,  Up: ARC-Dependent
+
+8.2.1 Options
+-------------
+
+`-marc[5|6|7|8]'
+     This option selects the core processor variant.  Using `-marc' is
+     the same as `-marc6', which is also the default.
+
+    `arc5'
+          Base instruction set.
+
+    `arc6'
+          Jump-and-link (jl) instruction.  No requirement of an
+          instruction between setting flags and conditional jump.  For
+          example:
+
+                 mov.f r0,r1
+                 beq   foo
+
+    `arc7'
+          Break (brk) and sleep (sleep) instructions.
+
+    `arc8'
+          Software interrupt (swi) instruction.
+
+
+     Note: the `.option' directive can to be used to select a core
+     variant from within assembly code.
+
+`-EB'
+     This option specifies that the output generated by the assembler
+     should be marked as being encoded for a big-endian processor.
+
+`-EL'
+     This option specifies that the output generated by the assembler
+     should be marked as being encoded for a little-endian processor -
+     this is the default.
+
+
+
+File: as.info,  Node: ARC Syntax,  Next: ARC Floating Point,  Prev: ARC Options,  Up: ARC-Dependent
+
+8.2.2 Syntax
+------------
+
+* Menu:
+
+* ARC-Chars::                Special Characters
+* ARC-Regs::                 Register Names
+
+
+File: as.info,  Node: ARC-Chars,  Next: ARC-Regs,  Up: ARC Syntax
+
+8.2.2.1 Special Characters
+..........................
+
+*TODO*
+
+
+File: as.info,  Node: ARC-Regs,  Prev: ARC-Chars,  Up: ARC Syntax
+
+8.2.2.2 Register Names
+......................
+
+*TODO*
+
+
+File: as.info,  Node: ARC Floating Point,  Next: ARC Directives,  Prev: ARC Syntax,  Up: ARC-Dependent
+
+8.2.3 Floating Point
+--------------------
+
+The ARC core does not currently have hardware floating point support.
+Software floating point support is provided by `GCC' and uses IEEE
+floating-point numbers.
+
+
+File: as.info,  Node: ARC Directives,  Next: ARC Opcodes,  Prev: ARC Floating Point,  Up: ARC-Dependent
+
+8.2.4 ARC Machine Directives
+----------------------------
+
+The ARC version of `as' supports the following additional machine
+directives:
+
+`.2byte EXPRESSIONS'
+     *TODO*
+
+`.3byte EXPRESSIONS'
+     *TODO*
+
+`.4byte EXPRESSIONS'
+     *TODO*
+
+`.extAuxRegister NAME,ADDRESS,MODE'
+     The ARCtangent A4 has extensible auxiliary register space.  The
+     auxiliary registers can be defined in the assembler source code by
+     using this directive.  The first parameter is the NAME of the new
+     auxiallry register.  The second parameter is the ADDRESS of the
+     register in the auxiliary register memory map for the variant of
+     the ARC.  The third parameter specifies the MODE in which the
+     register can be operated is and it can be one of:
+
+    `r          (readonly)'
+
+    `w          (write only)'
+
+    `r|w        (read or write)'
+
+     For example:
+
+            .extAuxRegister mulhi,0x12,w
+
+     This specifies an extension auxiliary register called _mulhi_
+     which is at address 0x12 in the memory space and which is only
+     writable.
+
+`.extCondCode SUFFIX,VALUE'
+     The condition codes on the ARCtangent A4 are extensible and can be
+     specified by means of this assembler directive.  They are specified
+     by the suffix and the value for the condition code.  They can be
+     used to specify extra condition codes with any values.  For
+     example:
+
+            .extCondCode is_busy,0x14
+
+             add.is_busy  r1,r2,r3
+             bis_busy     _main
+
+`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT'
+     Specifies an extension core register NAME for the application.
+     This allows a register NAME with a valid REGNUM between 0 and 60,
+     with the following as valid values for MODE
+
+    `_r_   (readonly)'
+
+    `_w_   (write only)'
+
+    `_r|w_ (read or write)'
+
+     The other parameter gives a description of the register having a
+     SHORTCUT in the pipeline.  The valid values are:
+
+    `can_shortcut'
+
+    `cannot_shortcut'
+
+     For example:
+
+            .extCoreRegister mlo,57,r,can_shortcut
+
+     This defines an extension core register mlo with the value 57 which
+     can shortcut the pipeline.
+
+`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS'
+     The ARCtangent A4 allows the user to specify extension
+     instructions.  The extension instructions are not macros.  The
+     assembler creates encodings for use of these instructions
+     according to the specification by the user.  The parameters are:
+
+    *NAME
+          Name of the extension instruction
+
+    *OPCODE
+          Opcode to be used. (Bits 27:31 in the encoding).  Valid values
+          0x10-0x1f or 0x03
+
+    *SUBOPCODE
+          Subopcode to be used.  Valid values are from 0x09-0x3f.
+          However the correct value also depends on SYNTAXCLASS
+
+    *SUFFIXCLASS
+          Determines the kinds of suffixes to be allowed.  Valid values
+          are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which
+          indicates the absence or presence of conditional suffixes and
+          flag setting by the extension instruction.  It is also
+          possible to specify that an instruction sets the flags and is
+          conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'.
+
+    *SYNTAXCLASS
+          Determines the syntax class for the instruction.  It can have
+          the following values:
+
+         ``SYNTAX_2OP':'
+               2 Operand Instruction
+
+         ``SYNTAX_3OP':'
+               3 Operand Instruction
+
+          In addition there could be modifiers for the syntax class as
+          described below:
+
+               Syntax Class Modifiers are:
+
+             - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP,
+               specifying that the first operand of a three-operand
+               instruction must be an immediate (i.e. the result is
+               discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it
+               with SYNTAX_3OP as given in the example below.  This
+               could usually be used to set the flags using specific
+               instructions and not retain results.
+
+             - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it
+               specifies that there is an implied immediate destination
+               operand which does not appear in the syntax.  For
+               example, if the source code contains an instruction like:
+
+                    inst r1,r2
+
+               it really means that the first argument is an implied
+               immediate (that is, the result is discarded).  This is
+               the same as though the source code were: inst 0,r1,r2.
+               You use OP1_IMM_IMPLIED by bitwise ORing it with
+               SYNTAX_20P.
+
+
+     For example, defining 64-bit multiplier with immediate operands:
+
+          .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
+                          SYNTAX_3OP|OP1_MUST_BE_IMM
+
+     The above specifies an extension instruction called mp64 which has
+     3 operands, sets the flags, can be used with a condition code, for
+     which the first operand is an immediate.  (Equivalent to
+     discarding the result of the operation).
+
+           .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
+
+     This describes a 2 operand instruction with an implicit first
+     immediate operand.  The result of this operation would be
+     discarded.
+
+`.half EXPRESSIONS'
+     *TODO*
+
+`.long EXPRESSIONS'
+     *TODO*
+
+`.option ARC|ARC5|ARC6|ARC7|ARC8'
+     The `.option' directive must be followed by the desired core
+     version. Again `arc' is an alias for `arc6'.
+
+     Note: the `.option' directive overrides the command line option
+     `-marc'; a warning is emitted when the version is not consistent
+     between the two - even for the implicit default core version
+     (arc6).
+
+`.short EXPRESSIONS'
+     *TODO*
+
+`.word EXPRESSIONS'
+     *TODO*
+
+
+
+File: as.info,  Node: ARC Opcodes,  Prev: ARC Directives,  Up: ARC-Dependent
+
+8.2.5 Opcodes
+-------------
+
+For information on the ARC instruction set, see `ARC Programmers
+Reference Manual', ARC International (www.arc.com)
+
+
+File: as.info,  Node: ARM-Dependent,  Next: BFIN-Dependent,  Prev: ARC-Dependent,  Up: Machine Dependencies
+
+8.3 ARM Dependent Features
+==========================
+
+* Menu:
+
+* ARM Options::              Options
+* ARM Syntax::               Syntax
+* ARM Floating Point::       Floating Point
+* ARM Directives::           ARM Machine Directives
+* ARM Opcodes::              Opcodes
+* ARM Mapping Symbols::      Mapping Symbols
+
+
+File: as.info,  Node: ARM Options,  Next: ARM Syntax,  Up: ARM-Dependent
+
+8.3.1 Options
+-------------
+
+`-mcpu=PROCESSOR[+EXTENSION...]'
+     This option specifies the target processor.  The assembler will
+     issue an error message if an attempt is made to assemble an
+     instruction which will not execute on the target processor.  The
+     following processor names are recognized: `arm1', `arm2', `arm250',
+     `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
+     `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
+     `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t',
+     `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi',
+     `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1',
+     `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920',
+     `arm920t', `arm922t', `arm940t', `arm9tdmi', `arm9e', `arm926e',
+     `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', `arm966e-r0',
+     `arm966e', `arm966e-s', `arm968e-s', `arm10t', `arm10tdmi',
+     `arm10e', `arm1020', `arm1020t', `arm1020e', `arm1022e',
+     `arm1026ej-s', `arm1136j-s', `arm1136jf-s', `arm1156t2-s',
+     `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', `mpcore',
+     `mpcorenovfp', `cortex-a8', `cortex-r4', `cortex-m3', `ep9312'
+     (ARM920 with Cirrus Maverick coprocessor), `i80200' (Intel XScale
+     processor) `iwmmxt' (Intel(r) XScale processor with Wireless
+     MMX(tm) technology coprocessor) and `xscale'.  The special name
+     `all' may be used to allow the assembler to accept instructions
+     valid for any ARM processor.
+
+     In addition to the basic instruction set, the assembler can be
+     told to accept various extension mnemonics that extend the
+     processor using the co-processor instruction space.  For example,
+     `-mcpu=arm920+maverick' is equivalent to specifying
+     `-mcpu=ep9312'.  The following extensions are currently supported:
+     `+maverick' `+iwmmxt' and `+xscale'.
+
+`-march=ARCHITECTURE[+EXTENSION...]'
+     This option specifies the target architecture.  The assembler will
+     issue an error message if an attempt is made to assemble an
+     instruction which will not execute on the target architecture.
+     The following architecture names are recognized: `armv1', `armv2',
+     `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm',
+     `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te',
+     `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk',
+     `armv7', `armv7a', `armv7r', `armv7m', `iwmmxt' and `xscale'.  If
+     both `-mcpu' and `-march' are specified, the assembler will use
+     the setting for `-mcpu'.
+
+     The architecture option can be extended with the same instruction
+     set extension options as the `-mcpu' option.
+
+`-mfpu=FLOATING-POINT-FORMAT'
+     This option specifies the floating point format to assemble for.
+     The assembler will issue an error message if an attempt is made to
+     assemble an instruction which will not execute on the target
+     floating point unit.  The following format options are recognized:
+     `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11',
+     `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0',
+     `vfp9', `vfpxd', `arm1020t', `arm1020e', `arm1136jf-s' and
+     `maverick'.
+
+     In addition to determining which instructions are assembled, this
+     option also affects the way in which the `.double' assembler
+     directive behaves when assembling little-endian code.
+
+     The default is dependent on the processor selected.  For
+     Architecture 5 or later, the default is to assembler for VFP
+     instructions; for earlier architectures the default is to assemble
+     for FPA instructions.
+
+`-mthumb'
+     This option specifies that the assembler should start assembling
+     Thumb instructions; that is, it should behave as though the file
+     starts with a `.code 16' directive.
+
+`-mthumb-interwork'
+     This option specifies that the output generated by the assembler
+     should be marked as supporting interworking.
+
+`-mapcs `[26|32]''
+     This option specifies that the output generated by the assembler
+     should be marked as supporting the indicated version of the Arm
+     Procedure.  Calling Standard.
+
+`-matpcs'
+     This option specifies that the output generated by the assembler
+     should be marked as supporting the Arm/Thumb Procedure Calling
+     Standard.  If enabled this option will cause the assembler to
+     create an empty debugging section in the object file called
+     .arm.atpcs.  Debuggers can use this to determine the ABI being
+     used by.
+
+`-mapcs-float'
+     This indicates the floating point variant of the APCS should be
+     used.  In this variant floating point arguments are passed in FP
+     registers rather than integer registers.
+
+`-mapcs-reentrant'
+     This indicates that the reentrant variant of the APCS should be
+     used.  This variant supports position independent code.
+
+`-mfloat-abi=ABI'
+     This option specifies that the output generated by the assembler
+     should be marked as using specified floating point ABI.  The
+     following values are recognized: `soft', `softfp' and `hard'.
+
+`-meabi=VER'
+     This option specifies which EABI version the produced object files
+     should conform to.  The following values are recognised: `gnu', `4'
+     and `5'.
+
+`-EB'
+     This option specifies that the output generated by the assembler
+     should be marked as being encoded for a big-endian processor.
+
+`-EL'
+     This option specifies that the output generated by the assembler
+     should be marked as being encoded for a little-endian processor.
+
+`-k'
+     This option specifies that the output of the assembler should be
+     marked as position-independent code (PIC).
+
+
+
+File: as.info,  Node: ARM Syntax,  Next: ARM Floating Point,  Prev: ARM Options,  Up: ARM-Dependent
+
+8.3.2 Syntax
+------------
+
+* Menu:
+
+* ARM-Chars::                Special Characters
+* ARM-Regs::                 Register Names
+
+
+File: as.info,  Node: ARM-Chars,  Next: ARM-Regs,  Up: ARM Syntax
+
+8.3.2.1 Special Characters
+..........................
+
+The presence of a `@' on a line indicates the start of a comment that
+extends to the end of the current line.  If a `#' appears as the first
+character of a line, the whole line is treated as a comment.
+
+   The `;' character can be used instead of a newline to separate
+statements.
+
+   Either `#' or `$' can be used to indicate immediate operands.
+
+   *TODO* Explain about /data modifier on symbols.
+
+
+File: as.info,  Node: ARM-Regs,  Prev: ARM-Chars,  Up: ARM Syntax
+
+8.3.2.2 Register Names
+......................
+
+*TODO* Explain about ARM register naming, and the predefined names.
+
+
+File: as.info,  Node: ARM Floating Point,  Next: ARM Directives,  Prev: ARM Syntax,  Up: ARM-Dependent
+
+8.3.3 Floating Point
+--------------------
+
+The ARM family uses IEEE floating-point numbers.
+
+
+File: as.info,  Node: ARM Directives,  Next: ARM Opcodes,  Prev: ARM Floating Point,  Up: ARM-Dependent
+
+8.3.4 ARM Machine Directives
+----------------------------
+
+`.align EXPRESSION [, EXPRESSION]'
+     This is the generic .ALIGN directive.  For the ARM however if the
+     first argument is zero (ie no alignment is needed) the assembler
+     will behave as if the argument had been 2 (ie pad to the next four
+     byte boundary).  This is for compatibility with ARM's own
+     assembler.
+
+`NAME .req REGISTER NAME'
+     This creates an alias for REGISTER NAME called NAME.  For example:
+
+                  foo .req r0
+
+`.unreq ALIAS-NAME'
+     This undefines a register alias which was previously defined using
+     the `req' directive.  For example:
+
+                  foo .req r0
+                  .unreq foo
+
+     An error occurs if the name is undefined.  Note - this pseudo op
+     can be used to delete builtin in register name aliases (eg 'r0').
+     This should only be done if it is really necessary.
+
+`.code `[16|32]''
+     This directive selects the instruction set being generated. The
+     value 16 selects Thumb, with the value 32 selecting ARM.
+
+`.thumb'
+     This performs the same action as .CODE 16.
+
+`.arm'
+     This performs the same action as .CODE 32.
+
+`.force_thumb'
+     This directive forces the selection of Thumb instructions, even if
+     the target processor does not support those instructions
+
+`.thumb_func'
+     This directive specifies that the following symbol is the name of a
+     Thumb encoded function.  This information is necessary in order to
+     allow the assembler and linker to generate correct code for
+     interworking between Arm and Thumb instructions and should be used
+     even if interworking is not going to be performed.  The presence
+     of this directive also implies `.thumb'
+
+`.thumb_set'
+     This performs the equivalent of a `.set' directive in that it
+     creates a symbol which is an alias for another symbol (possibly
+     not yet defined).  This directive also has the added property in
+     that it marks the aliased symbol as being a thumb function entry
+     point, in the same way that the `.thumb_func' directive does.
+
+`.ltorg'
+     This directive causes the current contents of the literal pool to
+     be dumped into the current section (which is assumed to be the
+     .text section) at the current location (aligned to a word
+     boundary).  `GAS' maintains a separate literal pool for each
+     section and each sub-section.  The `.ltorg' directive will only
+     affect the literal pool of the current section and sub-section.
+     At the end of assembly all remaining, un-empty literal pools will
+     automatically be dumped.
+
+     Note - older versions of `GAS' would dump the current literal pool
+     any time a section change occurred.  This is no longer done, since
+     it prevents accurate control of the placement of literal pools.
+
+`.pool'
+     This is a synonym for .ltorg.
+
+`.unwind_fnstart'
+     Marks the start of a function with an unwind table entry.
+
+`.unwind_fnend'
+     Marks the end of a function with an unwind table entry.  The
+     unwind index table entry is created when this directive is
+     processed.
+
+     If no personality routine has been specified then standard
+     personality routine 0 or 1 will be used, depending on the number
+     of unwind opcodes required.
+
+`.cantunwind'
+     Prevents unwinding through the current function.  No personality
+     routine or exception table data is required or permitted.
+
+`.personality NAME'
+     Sets the personality routine for the current function to NAME.
+
+`.personalityindex INDEX'
+     Sets the personality routine for the current function to the EABI
+     standard routine number INDEX
+
+`.handlerdata'
+     Marks the end of the current function, and the start of the
+     exception table entry for that function.  Anything between this
+     directive and the `.fnend' directive will be added to the
+     exception table entry.
+
+     Must be preceded by a `.personality' or `.personalityindex'
+     directive.
+
+`.save REGLIST'
+     Generate unwinder annotations to restore the registers in REGLIST.
+     The format of REGLIST is the same as the corresponding
+     store-multiple instruction.
+
+     _core registers_
+            .save {r4, r5, r6, lr}
+            stmfd sp!, {r4, r5, r6, lr}
+     _FPA registers_
+            .save f4, 2
+            sfmfd f4, 2, [sp]!
+     _VFP registers_
+            .save {d8, d9, d10}
+            fstmdf sp!, {d8, d9, d10}
+     _iWMMXt registers_
+            .save {wr10, wr11}
+            wstrd wr11, [sp, #-8]!
+            wstrd wr10, [sp, #-8]!
+          or
+            .save wr11
+            wstrd wr11, [sp, #-8]!
+            .save wr10
+            wstrd wr10, [sp, #-8]!
+
+`.pad #COUNT'
+     Generate unwinder annotations for a stack adjustment of COUNT
+     bytes.  A positive value indicates the function prologue allocated
+     stack space by decrementing the stack pointer.
+
+`.movsp REG'
+     Tell the unwinder that REG contains the current stack pointer.
+
+`.setfp FPREG, SPREG [, #OFFSET]'
+     Make all unwinder annotations relaive to a frame pointer.  Without
+     this the unwinder will use offsets from the stack pointer.
+
+     The syntax of this directive is the same as the `sub' or `mov'
+     instruction used to set the frame pointer.  SPREG must be either
+     `sp' or mentioned in a previous `.movsp' directive.
+
+          .movsp ip
+          mov ip, sp
+          ...
+          .setfp fp, ip, #4
+          sub fp, ip, #4
+
+`.raw OFFSET, BYTE1, ...'
+     Insert one of more arbitary unwind opcode bytes, which are known
+     to adjust the stack pointer by OFFSET bytes.
+
+     For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save
+     {r0}'
+
+`.cpu NAME'
+     Select the target processor.  Valid values for NAME are the same as
+     for the `-mcpu' commandline option.
+
+`.arch NAME'
+     Select the target architecture.  Valid values for NAME are the
+     same as for the `-march' commandline option.
+
+`.fpu NAME'
+     Select the floating point unit to assemble for.  Valid values for
+     NAME are the same as for the `-mfpu' commandline option.
+
+`.eabi_attribute TAG, VALUE'
+     Set the EABI object attribute number TAG to VALUE.  The value is
+     either a `number', `"string"', or `number, "string"' depending on
+     the tag.
+
+
+
+File: as.info,  Node: ARM Opcodes,  Next: ARM Mapping Symbols,  Prev: ARM Directives,  Up: ARM-Dependent
+
+8.3.5 Opcodes
+-------------
+
+`as' implements all the standard ARM opcodes.  It also implements
+several pseudo opcodes, including several synthetic load instructions.
+
+`NOP'
+            nop
+
+     This pseudo op will always evaluate to a legal ARM instruction
+     that does nothing.  Currently it will evaluate to MOV r0, r0.
+
+`LDR'
+            ldr <register> , = <expression>
+
+     If expression evaluates to a numeric constant then a MOV or MVN
+     instruction will be used in place of the LDR instruction, if the
+     constant can be generated by either of these instructions.
+     Otherwise the constant will be placed into the nearest literal
+     pool (if it not already there) and a PC relative LDR instruction
+     will be generated.
+
+`ADR'
+            adr <register> <label>
+
+     This instruction will load the address of LABEL into the indicated
+     register.  The instruction will evaluate to a PC relative ADD or
+     SUB instruction depending upon where the label is located.  If the
+     label is out of range, or if it is not defined in the same file
+     (and section) as the ADR instruction, then an error will be
+     generated.  This instruction will not make use of the literal pool.
+
+`ADRL'
+            adrl <register> <label>
+
+     This instruction will load the address of LABEL into the indicated
+     register.  The instruction will evaluate to one or two PC relative
+     ADD or SUB instructions depending upon where the label is located.
+     If a second instruction is not needed a NOP instruction will be
+     generated in its place, so that this instruction is always 8 bytes
+     long.
+
+     If the label is out of range, or if it is not defined in the same
+     file (and section) as the ADRL instruction, then an error will be
+     generated.  This instruction will not make use of the literal pool.
+
+
+   For information on the ARM or Thumb instruction sets, see `ARM
+Software Development Toolkit Reference Manual', Advanced RISC Machines
+Ltd.
+
+
+File: as.info,  Node: ARM Mapping Symbols,  Prev: ARM Opcodes,  Up: ARM-Dependent
+
+8.3.6 Mapping Symbols
+---------------------
+
+The ARM ELF specification requires that special symbols be inserted
+into object files to mark certain features:
+
+`$a'
+     At the start of a region of code containing ARM instructions.
+
+`$t'
+     At the start of a region of code containing THUMB instructions.
+
+`$d'
+     At the start of a region of data.
+
+
+   The assembler will automatically insert these symbols for you - there
+is no need to code them yourself.  Support for tagging symbols ($b, $f,
+$p and $m) which is also mentioned in the current ARM ELF specification
+is not implemented.  This is because they have been dropped from the
+new EABI and so tools cannot rely upon their presence.
+
+
+File: as.info,  Node: BFIN-Dependent,  Next: CRIS-Dependent,  Prev: ARM-Dependent,  Up: Machine Dependencies
+
+8.4 Blackfin Dependent Features
+===============================
+
+* Menu:
+
+* BFIN Syntax::			BFIN Syntax
+* BFIN Directives::		BFIN Directives
+
+
+File: as.info,  Node: BFIN Syntax,  Next: BFIN Directives,  Up: BFIN-Dependent
+
+8.4.1 Syntax
+------------
+
+`Special Characters'
+     Assembler input is free format and may appear anywhere on the line.
+     One instruction may extend across multiple lines or more than one
+     instruction may appear on the same line.  White space (space, tab,
+     comments or newline) may appear anywhere between tokens.  A token
+     must not have embedded spaces.  Tokens include numbers, register
+     names, keywords, user identifiers, and also some multicharacter
+     special symbols like "+=", "/*" or "||".
+
+`Instruction Delimiting'
+     A semicolon must terminate every instruction.  Sometimes a complete
+     instruction will consist of more than one operation.  There are two
+     cases where this occurs.  The first is when two general operations
+     are combined.  Normally a comma separates the different parts, as
+     in
+
+          a0= r3.h * r2.l, a1 = r3.l * r2.h ;
+
+     The second case occurs when a general instruction is combined with
+     one or two memory references for joint issue.  The latter portions
+     are set off by a "||" token.
+
+          a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
+
+`Register Names'
+     The assembler treats register names and instruction keywords in a
+     case insensitive manner.  User identifiers are case sensitive.
+     Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the
+     assembler.
+
+     Register names are reserved and may not be used as program
+     identifiers.
+
+     Some operations (such as "Move Register") require a register pair.
+     Register pairs are always data registers and are denoted using a
+     colon, eg., R3:2.  The larger number must be written firsts.  Note
+     that the hardware only supports odd-even pairs, eg., R7:6, R5:4,
+     R3:2, and R1:0.
+
+     Some instructions (such as -SP (Push Multiple)) require a group of
+     adjacent registers.  Adjacent registers are denoted in the syntax
+     by the range enclosed in parentheses and separated by a colon,
+     eg., (R7:3).  Again, the larger number appears first.
+
+     Portions of a particular register may be individually specified.
+     This is written with a dot (".") following the register name and
+     then a letter denoting the desired portion.  For 32-bit registers,
+     ".H" denotes the most significant ("High") portion.  ".L" denotes
+     the least-significant portion.  The subdivisions of the 40-bit
+     registers are described later.
+
+`Accumulators'
+     The set of 40-bit registers A1 and A0 that normally contain data
+     that is being manipulated.  Each accumulator can be accessed in
+     four ways.
+
+    `one 40-bit register'
+          The register will be referred to as A1 or A0.
+
+    `one 32-bit register'
+          The registers are designated as A1.W or A0.W.
+
+    `two 16-bit registers'
+          The registers are designated as A1.H, A1.L, A0.H or A0.L.
+
+    `one 8-bit register'
+          The registers are designated as A1.X or A0.X for the bits that
+          extend beyond bit 31.
+
+`Data Registers'
+     The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7)
+     that normally contain data for manipulation.  These are
+     abbreviated as D-register or Dreg.  Data registers can be accessed
+     as 32-bit registers or as two independent 16-bit registers.  The
+     least significant 16 bits of each register is called the "low"
+     half and is desginated with ".L" following the register name.  The
+     most significant 16 bits are called the "high" half and is
+     designated with ".H". following the name.
+
+             R7.L, r2.h, r4.L, R0.H
+
+`Pointer Registers'
+     The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP)
+     that normally contain byte addresses of data structures.  These are
+     abbreviated as P-register or Preg.
+
+          p2, p5, fp, sp
+
+`Stack Pointer SP'
+     The stack pointer contains the 32-bit address of the last occupied
+     byte location in the stack.  The stack grows by decrementing the
+     stack pointer.
+
+`Frame Pointer FP'
+     The frame pointer contains the 32-bit address of the previous frame
+     pointer in the stack.  It is located at the top of a frame.
+
+`Loop Top'
+     LT0 and LT1.  These registers contain the 32-bit address of the
+     top of a zero overhead loop.
+
+`Loop Count'
+     LC0 and LC1.  These registers contain the 32-bit counter of the
+     zero overhead loop executions.
+
+`Loop Bottom'
+     LB0 and LB1.  These registers contain the 32-bit address of the
+     bottom of a zero overhead loop.
+
+`Index Registers'
+     The set of 32-bit registers (I0, I1, I2, I3) that normally contain
+     byte addresses of data structures.  Abbreviated I-register or Ireg.
+
+`Modify Registers'
+     The set of 32-bit registers (M0, M1, M2, M3) that normally contain
+     offset values that are added and subracted to one of the index
+     registers.  Abbreviated as Mreg.
+
+`Length Registers'
+     The set of 32-bit registers (L0, L1, L2, L3) that normally contain
+     the length in bytes of the circular buffer.  Abbreviated as Lreg.
+     Clear the Lreg to disable circular addressing for the
+     corresponding Ireg.
+
+`Base Registers'
+     The set of 32-bit registers (B0, B1, B2, B3) that normally contain
+     the base address in bytes of the circular buffer.  Abbreviated as
+     Breg.
+
+`Floating Point'
+     The Blackfin family has no hardware floating point but the .float
+     directive generates ieee floating point numbers for use with
+     software floating point libraries.
+
+`Blackfin Opcodes'
+     For detailed information on the Blackfin machine instruction set,
+     see the Blackfin(r) Processor Instruction Set Reference.
+
+
+
+File: as.info,  Node: BFIN Directives,  Prev: BFIN Syntax,  Up: BFIN-Dependent
+
+8.4.2 Directives
+----------------
+
+The following directives are provided for compatibility with the VDSP
+assembler.
+
+`.byte2'
+     Initializes a four byte data object.
+
+`.byte4'
+     Initializes a two byte data object.
+
+`.db'
+     TBD
+
+`.dd'
+     TBD
+
+`.dw'
+     TBD
+
+`.var'
+     Define and initialize a 32 bit data object.
+
+
+File: as.info,  Node: CRIS-Dependent,  Next: D10V-Dependent,  Prev: BFIN-Dependent,  Up: Machine Dependencies
+
+8.5 CRIS Dependent Features
+===========================
+
+* Menu:
+
+* CRIS-Opts::              Command-line Options
+* CRIS-Expand::            Instruction expansion
+* CRIS-Symbols::           Symbols
+* CRIS-Syntax::            Syntax
+
+
+File: as.info,  Node: CRIS-Opts,  Next: CRIS-Expand,  Up: CRIS-Dependent
+
+8.5.1 Command-line Options
+--------------------------
+
+The CRIS version of `as' has these machine-dependent command-line
+options.
+
+   The format of the generated object files can be either ELF or a.out,
+specified by the command-line options `--emulation=crisaout' and
+`--emulation=criself'.  The default is ELF (criself), unless `as' has
+been configured specifically for a.out by using the configuration name
+`cris-axis-aout'.
+
+   There are two different link-incompatible ELF object file variants
+for CRIS, for use in environments where symbols are expected to be
+prefixed by a leading `_' character and for environments without such a
+symbol prefix.  The variant used for GNU/Linux port has no symbol
+prefix.  Which variant to produce is specified by either of the options
+`--underscore' and `--no-underscore'.  The default is `--underscore'.
+Since symbols in CRIS a.out objects are expected to have a `_' prefix,
+specifying `--no-underscore' when generating a.out objects is an error.
+Besides the object format difference, the effect of this option is to
+parse register names differently (*note crisnous::).  The
+`--no-underscore' option makes a `$' register prefix mandatory.
+
+   The option `--pic' must be passed to `as' in order to recognize the
+symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note
+crispic::).  This will also affect expansion of instructions.  The
+expansion with `--pic' will use PC-relative rather than (slightly
+faster) absolute addresses in those expansions.
+
+   The option `--march=ARCHITECTURE' specifies the recognized
+instruction set and recognized register names.  It also controls the
+architecture type of the object file.  Valid values for ARCHITECTURE
+are:
+`v0_v10'
+     All instructions and register names for any architecture variant
+     in the set v0...v10 are recognized.  This is the default if the
+     target is configured as cris-*.
+
+`v10'
+     Only instructions and register names for CRIS v10 (as found in
+     ETRAX 100 LX) are recognized.  This is the default if the target
+     is configured as crisv10-*.
+
+`v32'
+     Only instructions and register names for CRIS v32 (code name
+     Guinness) are recognized.  This is the default if the target is
+     configured as crisv32-*.  This value implies `--no-mul-bug-abort'.
+     (A subsequent `--mul-bug-abort' will turn it back on.)
+
+`common_v10_v32'
+     Only instructions with register names and addressing modes with
+     opcodes common to the v10 and v32 are recognized.
+
+   When `-N' is specified, `as' will emit a warning when a 16-bit
+branch instruction is expanded into a 32-bit multiple-instruction
+construct (*note CRIS-Expand::).
+
+   Some versions of the CRIS v10, for example in the Etrax 100 LX,
+contain a bug that causes destabilizing memory accesses when a multiply
+instruction is executed with certain values in the first operand just
+before a cache-miss.  When the `--mul-bug-abort' command line option is
+active (the default value), `as' will refuse to assemble a file
+containing a multiply instruction at a dangerous offset, one that could
+be the last on a cache-line, or is in a section with insufficient
+alignment.  This placement checking does not catch any case where the
+multiply instruction is dangerously placed because it is located in a
+delay-slot.  The `--mul-bug-abort' command line option turns off the
+checking.
+
+
+File: as.info,  Node: CRIS-Expand,  Next: CRIS-Symbols,  Prev: CRIS-Opts,  Up: CRIS-Dependent
+
+8.5.2 Instruction expansion
+---------------------------
+
+`as' will silently choose an instruction that fits the operand size for
+`[register+constant]' operands.  For example, the offset `127' in
+`move.d [r3+127],r4' fits in an instruction using a signed-byte offset.
+Similarly, `move.d [r2+32767],r1' will generate an instruction using a
+16-bit offset.  For symbolic expressions and constants that do not fit
+in 16 bits including the sign bit, a 32-bit offset is generated.
+
+   For branches, `as' will expand from a 16-bit branch instruction into
+a sequence of instructions that can reach a full 32-bit address.  Since
+this does not correspond to a single instruction, such expansions can
+optionally be warned about.  *Note CRIS-Opts::.
+
+   If the operand is found to fit the range, a `lapc' mnemonic will
+translate to a `lapcq' instruction.  Use `lapc.d' to force the 32-bit
+`lapc' instruction.
+
+   Similarly, the `addo' mnemonic will translate to the shortest
+fitting instruction of `addoq', `addo.w' and `addo.d', when used with a
+operand that is a constant known at assembly time.
+
+
+File: as.info,  Node: CRIS-Symbols,  Next: CRIS-Syntax,  Prev: CRIS-Expand,  Up: CRIS-Dependent
+
+8.5.3 Symbols
+-------------
+
+Some symbols are defined by the assembler.  They're intended to be used
+in conditional assembly, for example:
+      .if ..asm.arch.cris.v32
+      CODE FOR CRIS V32
+      .elseif ..asm.arch.cris.common_v10_v32
+      CODE COMMON TO CRIS V32 AND CRIS V10
+      .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
+      CODE FOR V10
+      .else
+      .error "Code needs to be added here."
+      .endif
+
+   These symbols are defined in the assembler, reflecting command-line
+options, either when specified or the default.  They are always
+defined, to 0 or 1.
+`..asm.arch.cris.any_v0_v10'
+     This symbol is non-zero when `--march=v0_v10' is specified or the
+     default.
+
+`..asm.arch.cris.common_v10_v32'
+     Set according to the option `--march=common_v10_v32'.
+
+`..asm.arch.cris.v10'
+     Reflects the option `--march=v10'.
+
+`..asm.arch.cris.v32'
+     Corresponds to `--march=v10'.
+
+   Speaking of symbols, when a symbol is used in code, it can have a
+suffix modifying its value for use in position-independent code. *Note
+CRIS-Pic::.
+
+
+File: as.info,  Node: CRIS-Syntax,  Prev: CRIS-Symbols,  Up: CRIS-Dependent
+
+8.5.4 Syntax
+------------
+
+There are different aspects of the CRIS assembly syntax.
+
+* Menu:
+
+* CRIS-Chars::		        Special Characters
+* CRIS-Pic::			Position-Independent Code Symbols
+* CRIS-Regs::			Register Names
+* CRIS-Pseudos::		Assembler Directives
+
+
+File: as.info,  Node: CRIS-Chars,  Next: CRIS-Pic,  Up: CRIS-Syntax
+
+8.5.4.1 Special Characters
+..........................
+
+The character `#' is a line comment character.  It starts a comment if
+and only if it is placed at the beginning of a line.
+
+   A `;' character starts a comment anywhere on the line, causing all
+characters up to the end of the line to be ignored.
+
+   A `@' character is handled as a line separator equivalent to a
+logical new-line character (except in a comment), so separate
+instructions can be specified on a single line.
+
+
+File: as.info,  Node: CRIS-Pic,  Next: CRIS-Regs,  Prev: CRIS-Chars,  Up: CRIS-Syntax
+
+8.5.4.2 Symbols in position-independent code
+............................................
+
+When generating position-independent code (SVR4 PIC) for use in
+cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol
+suffixes are used to specify what kind of run-time symbol lookup will
+be used, expressed in the object as different _relocation types_.
+Usually, all absolute symbol values must be located in a table, the
+_global offset table_, leaving the code position-independent;
+independent of values of global symbols and independent of the address
+of the code.  The suffix modifies the value of the symbol, into for
+example an index into the global offset table where the real symbol
+value is entered, or a PC-relative value, or a value relative to the
+start of the global offset table.  All symbol suffixes start with the
+character `:' (omitted in the list below).  Every symbol use in code or
+a read-only section must therefore have a PIC suffix to enable a useful
+shared library to be created.  Usually, these constructs must not be
+used with an additive constant offset as is usually allowed, i.e. no 4
+as in `symbol + 4' is allowed.  This restriction is checked at
+link-time, not at assembly-time.
+
+`GOT'
+     Attaching this suffix to a symbol in an instruction causes the
+     symbol to be entered into the global offset table.  The value is a
+     32-bit index for that symbol into the global offset table.  The
+     name of the corresponding relocation is `R_CRIS_32_GOT'.  Example:
+     `move.d [$r0+extsym:GOT],$r9'
+
+`GOT16'
+     Same as for `GOT', but the value is a 16-bit index into the global
+     offset table.  The corresponding relocation is `R_CRIS_16_GOT'.
+     Example: `move.d [$r0+asymbol:GOT16],$r10'
+
+`PLT'
+     This suffix is used for function symbols.  It causes a _procedure
+     linkage table_, an array of code stubs, to be created at the time
+     the shared object is created or linked against, together with a
+     global offset table entry.  The value is a pc-relative offset to
+     the corresponding stub code in the procedure linkage table.  This
+     arrangement causes the run-time symbol resolver to be called to
+     look up and set the value of the symbol the first time the
+     function is called (at latest; depending environment variables).
+     It is only safe to leave the symbol unresolved this way if all
+     references are function calls.  The name of the relocation is
+     `R_CRIS_32_PLT_PCREL'.  Example: `add.d fnname:PLT,$pc'
+
+`PLTG'
+     Like PLT, but the value is relative to the beginning of the global
+     offset table.  The relocation is `R_CRIS_32_PLT_GOTREL'.  Example:
+     `move.d fnname:PLTG,$r3'
+
+`GOTPLT'
+     Similar to `PLT', but the value of the symbol is a 32-bit index
+     into the global offset table.  This is somewhat of a mix between
+     the effect of the `GOT' and the `PLT' suffix; the difference to
+     `GOT' is that there will be a procedure linkage table entry
+     created, and that the symbol is assumed to be a function entry and
+     will be resolved by the run-time resolver as with `PLT'.  The
+     relocation is `R_CRIS_32_GOTPLT'.  Example: `jsr
+     [$r0+fnname:GOTPLT]'
+
+`GOTPLT16'
+     A variant of `GOTPLT' giving a 16-bit value.  Its relocation name
+     is `R_CRIS_16_GOTPLT'.  Example: `jsr [$r0+fnname:GOTPLT16]'
+
+`GOTOFF'
+     This suffix must only be attached to a local symbol, but may be
+     used in an expression adding an offset.  The value is the address
+     of the symbol relative to the start of the global offset table.
+     The relocation name is `R_CRIS_32_GOTREL'.  Example: `move.d
+     [$r0+localsym:GOTOFF],r3'
+
+
+File: as.info,  Node: CRIS-Regs,  Next: CRIS-Pseudos,  Prev: CRIS-Pic,  Up: CRIS-Syntax
+
+8.5.4.3 Register names
+......................
+
+A `$' character may always prefix a general or special register name in
+an instruction operand but is mandatory when the option
+`--no-underscore' is specified or when the `.syntax register_prefix'
+directive is in effect (*note crisnous::).  Register names are
+case-insensitive.
+
+
+File: as.info,  Node: CRIS-Pseudos,  Prev: CRIS-Regs,  Up: CRIS-Syntax
+
+8.5.4.4 Assembler Directives
+............................
+
+There are a few CRIS-specific pseudo-directives in addition to the
+generic ones.  *Note Pseudo Ops::.  Constants emitted by
+pseudo-directives are in little-endian order for CRIS.  There is no
+support for floating-point-specific directives for CRIS.
+
+`.dword EXPRESSIONS'
+     The `.dword' directive is a synonym for `.int', expecting zero or
+     more EXPRESSIONS, separated by commas.  For each expression, a
+     32-bit little-endian constant is emitted.
+
+`.syntax ARGUMENT'
+     The `.syntax' directive takes as ARGUMENT one of the following
+     case-sensitive choices.
+
+    `no_register_prefix'
+          The `.syntax no_register_prefix' directive makes a `$'
+          character prefix on all registers optional.  It overrides a
+          previous setting, including the corresponding effect of the
+          option `--no-underscore'.  If this directive is used when
+          ordinary symbols do not have a `_' character prefix, care
+          must be taken to avoid ambiguities whether an operand is a
+          register or a symbol; using symbols with names the same as
+          general or special registers then invoke undefined behavior.
+
+    `register_prefix'
+          This directive makes a `$' character prefix on all registers
+          mandatory.  It overrides a previous setting, including the
+          corresponding effect of the option `--underscore'.
+
+    `leading_underscore'
+          This is an assertion directive, emitting an error if the
+          `--no-underscore' option is in effect.
+
+    `no_leading_underscore'
+          This is the opposite of the `.syntax leading_underscore'
+          directive and emits an error if the option `--underscore' is
+          in effect.
+
+`.arch ARGUMENT'
+     This is an assertion directive, giving an error if the specified
+     ARGUMENT is not the same as the specified or default value for the
+     `--march=ARCHITECTURE' option (*note march-option::).
+
+
+
+File: as.info,  Node: D10V-Dependent,  Next: D30V-Dependent,  Prev: CRIS-Dependent,  Up: Machine Dependencies
+
+8.6 D10V Dependent Features
+===========================
+
+* Menu:
+
+* D10V-Opts::                   D10V Options
+* D10V-Syntax::                 Syntax
+* D10V-Float::                  Floating Point
+* D10V-Opcodes::                Opcodes
+
+
+File: as.info,  Node: D10V-Opts,  Next: D10V-Syntax,  Up: D10V-Dependent
+
+8.6.1 D10V Options
+------------------
+
+The Mitsubishi D10V version of `as' has a few machine dependent options.
+
+`-O'
+     The D10V can often execute two sub-instructions in parallel. When
+     this option is used, `as' will attempt to optimize its output by
+     detecting when instructions can be executed in parallel.
+
+`--nowarnswap'
+     To optimize execution performance, `as' will sometimes swap the
+     order of instructions. Normally this generates a warning. When
+     this option is used, no warning will be generated when
+     instructions are swapped.
+
+`--gstabs-packing'
+
+`--no-gstabs-packing'
+     `as' packs adjacent short instructions into a single packed
+     instruction. `--no-gstabs-packing' turns instruction packing off if
+     `--gstabs' is specified as well; `--gstabs-packing' (the default)
+     turns instruction packing on even when `--gstabs' is specified.
+
+
+File: as.info,  Node: D10V-Syntax,  Next: D10V-Float,  Prev: D10V-Opts,  Up: D10V-Dependent
+
+8.6.2 Syntax
+------------
+
+The D10V syntax is based on the syntax in Mitsubishi's D10V
+architecture manual.  The differences are detailed below.
+
+* Menu:
+
+* D10V-Size::                 Size Modifiers
+* D10V-Subs::                 Sub-Instructions
+* D10V-Chars::                Special Characters
+* D10V-Regs::                 Register Names
+* D10V-Addressing::           Addressing Modes
+* D10V-Word::                 @WORD Modifier
+
+
+File: as.info,  Node: D10V-Size,  Next: D10V-Subs,  Up: D10V-Syntax
+
+8.6.2.1 Size Modifiers
+......................
+
+The D10V version of `as' uses the instruction names in the D10V
+Architecture Manual.  However, the names in the manual are sometimes
+ambiguous.  There are instruction names that can assemble to a short or
+long form opcode.  How does the assembler pick the correct form?  `as'
+will always pick the smallest form if it can.  When dealing with a
+symbol that is not defined yet when a line is being assembled, it will
+always use the long form.  If you need to force the assembler to use
+either the short or long form of the instruction, you can append either
+`.s' (short) or `.l' (long) to it.  For example, if you are writing an
+assembly program and you want to do a branch to a symbol that is
+defined later in your program, you can write `bra.s   foo'.  Objdump
+and GDB will always append `.s' or `.l' to instructions which have both
+short and long forms.
+
+
+File: as.info,  Node: D10V-Subs,  Next: D10V-Chars,  Prev: D10V-Size,  Up: D10V-Syntax
+
+8.6.2.2 Sub-Instructions
+........................
+
+The D10V assembler takes as input a series of instructions, either
+one-per-line, or in the special two-per-line format described in the
+next section.  Some of these instructions will be short-form or
+sub-instructions.  These sub-instructions can be packed into a single
+instruction.  The assembler will do this automatically.  It will also
+detect when it should not pack instructions.  For example, when a label
+is defined, the next instruction will never be packaged with the
+previous one.  Whenever a branch and link instruction is called, it
+will not be packaged with the next instruction so the return address
+will be valid.  Nops are automatically inserted when necessary.
+
+   If you do not want the assembler automatically making these
+decisions, you can control the packaging and execution type (parallel
+or sequential) with the special execution symbols described in the next
+section.
+
+
+File: as.info,  Node: D10V-Chars,  Next: D10V-Regs,  Prev: D10V-Subs,  Up: D10V-Syntax
+
+8.6.2.3 Special Characters
+..........................
+
+`;' and `#' are the line comment characters.  Sub-instructions may be
+executed in order, in reverse-order, or in parallel.  Instructions
+listed in the standard one-per-line format will be executed
+sequentially.  To specify the executing order, use the following
+symbols:
+`->'
+     Sequential with instruction on the left first.
+
+`<-'
+     Sequential with instruction on the right first.
+
+`||'
+     Parallel
+   The D10V syntax allows either one instruction per line, one
+instruction per line with the execution symbol, or two instructions per
+line.  For example
+`abs       a1      ->      abs     r0'
+     Execute these sequentially.  The instruction on the right is in
+     the right container and is executed second.
+
+`abs       r0      <-      abs     a1'
+     Execute these reverse-sequentially.  The instruction on the right
+     is in the right container, and is executed first.
+
+`ld2w    r2,@r8+         ||      mac     a0,r0,r7'
+     Execute these in parallel.
+
+`ld2w    r2,@r8+         ||'
+`mac     a0,r0,r7'
+     Two-line format. Execute these in parallel.
+
+`ld2w    r2,@r8+'
+`mac     a0,r0,r7'
+     Two-line format. Execute these sequentially.  Assembler will put
+     them in the proper containers.
+
+`ld2w    r2,@r8+         ->'
+`mac     a0,r0,r7'
+     Two-line format. Execute these sequentially.  Same as above but
+     second instruction will always go into right container.
+   Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info,  Node: D10V-Regs,  Next: D10V-Addressing,  Prev: D10V-Chars,  Up: D10V-Syntax
+
+8.6.2.4 Register Names
+......................
+
+You can use the predefined symbols `r0' through `r15' to refer to the
+D10V registers.  You can also use `sp' as an alias for `r15'.  The
+accumulators are `a0' and `a1'.  There are special register-pair names
+that may optionally be used in opcodes that require even-numbered
+registers. Register names are not case sensitive.
+
+   Register Pairs
+`r0-r1'
+
+`r2-r3'
+
+`r4-r5'
+
+`r6-r7'
+
+`r8-r9'
+
+`r10-r11'
+
+`r12-r13'
+
+`r14-r15'
+
+   The D10V also has predefined symbols for these control registers and
+status bits:
+`psw'
+     Processor Status Word
+
+`bpsw'
+     Backup Processor Status Word
+
+`pc'
+     Program Counter
+
+`bpc'
+     Backup Program Counter
+
+`rpt_c'
+     Repeat Count
+
+`rpt_s'
+     Repeat Start address
+
+`rpt_e'
+     Repeat End address
+
+`mod_s'
+     Modulo Start address
+
+`mod_e'
+     Modulo End address
+
+`iba'
+     Instruction Break Address
+
+`f0'
+     Flag 0
+
+`f1'
+     Flag 1
+
+`c'
+     Carry flag
+
+
+File: as.info,  Node: D10V-Addressing,  Next: D10V-Word,  Prev: D10V-Regs,  Up: D10V-Syntax
+
+8.6.2.5 Addressing Modes
+........................
+
+`as' understands the following addressing modes for the D10V.  `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+`RN'
+     Register direct
+
+`@RN'
+     Register indirect
+
+`@RN+'
+     Register indirect with post-increment
+
+`@RN-'
+     Register indirect with post-decrement
+
+`@-SP'
+     Register indirect with pre-decrement
+
+`@(DISP, RN)'
+     Register indirect with displacement
+
+`ADDR'
+     PC relative address (for branch or rep).
+
+`#IMM'
+     Immediate data (the `#' is optional and ignored)
+
+
+File: as.info,  Node: D10V-Word,  Prev: D10V-Addressing,  Up: D10V-Syntax
+
+8.6.2.6 @WORD Modifier
+......................
+
+Any symbol followed by `@word' will be replaced by the symbol's value
+shifted right by 2.  This is used in situations such as loading a
+register with the address of a function (or any other code fragment).
+For example, if you want to load a register with the location of the
+function `main' then jump to that function, you could do it as follows:
+     ldi     r2, main@word
+     jmp     r2
+
+
+File: as.info,  Node: D10V-Float,  Next: D10V-Opcodes,  Prev: D10V-Syntax,  Up: D10V-Dependent
+
+8.6.3 Floating Point
+--------------------
+
+The D10V has no hardware floating point, but the `.float' and `.double'
+directives generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info,  Node: D10V-Opcodes,  Prev: D10V-Float,  Up: D10V-Dependent
+
+8.6.4 Opcodes
+-------------
+
+For detailed information on the D10V machine instruction set, see `D10V
+Architecture: A VLIW Microprocessor for Multimedia Applications'
+(Mitsubishi Electric Corp.).  `as' implements all the standard D10V
+opcodes.  The only changes are those described in the section on size
+modifiers
+
+
+File: as.info,  Node: D30V-Dependent,  Next: H8/300-Dependent,  Prev: D10V-Dependent,  Up: Machine Dependencies
+
+8.7 D30V Dependent Features
+===========================
+
+* Menu:
+
+* D30V-Opts::                   D30V Options
+* D30V-Syntax::                 Syntax
+* D30V-Float::                  Floating Point
+* D30V-Opcodes::                Opcodes
+
+
+File: as.info,  Node: D30V-Opts,  Next: D30V-Syntax,  Up: D30V-Dependent
+
+8.7.1 D30V Options
+------------------
+
+The Mitsubishi D30V version of `as' has a few machine dependent options.
+
+`-O'
+     The D30V can often execute two sub-instructions in parallel. When
+     this option is used, `as' will attempt to optimize its output by
+     detecting when instructions can be executed in parallel.
+
+`-n'
+     When this option is used, `as' will issue a warning every time it
+     adds a nop instruction.
+
+`-N'
+     When this option is used, `as' will issue a warning if it needs to
+     insert a nop after a 32-bit multiply before a load or 16-bit
+     multiply instruction.
+
+
+File: as.info,  Node: D30V-Syntax,  Next: D30V-Float,  Prev: D30V-Opts,  Up: D30V-Dependent
+
+8.7.2 Syntax
+------------
+
+The D30V syntax is based on the syntax in Mitsubishi's D30V
+architecture manual.  The differences are detailed below.
+
+* Menu:
+
+* D30V-Size::                 Size Modifiers
+* D30V-Subs::                 Sub-Instructions
+* D30V-Chars::                Special Characters
+* D30V-Guarded::              Guarded Execution
+* D30V-Regs::                 Register Names
+* D30V-Addressing::           Addressing Modes
+
+
+File: as.info,  Node: D30V-Size,  Next: D30V-Subs,  Up: D30V-Syntax
+
+8.7.2.1 Size Modifiers
+......................
+
+The D30V version of `as' uses the instruction names in the D30V
+Architecture Manual.  However, the names in the manual are sometimes
+ambiguous.  There are instruction names that can assemble to a short or
+long form opcode.  How does the assembler pick the correct form?  `as'
+will always pick the smallest form if it can.  When dealing with a
+symbol that is not defined yet when a line is being assembled, it will
+always use the long form.  If you need to force the assembler to use
+either the short or long form of the instruction, you can append either
+`.s' (short) or `.l' (long) to it.  For example, if you are writing an
+assembly program and you want to do a branch to a symbol that is
+defined later in your program, you can write `bra.s foo'.  Objdump and
+GDB will always append `.s' or `.l' to instructions which have both
+short and long forms.
+
+
+File: as.info,  Node: D30V-Subs,  Next: D30V-Chars,  Prev: D30V-Size,  Up: D30V-Syntax
+
+8.7.2.2 Sub-Instructions
+........................
+
+The D30V assembler takes as input a series of instructions, either
+one-per-line, or in the special two-per-line format described in the
+next section.  Some of these instructions will be short-form or
+sub-instructions.  These sub-instructions can be packed into a single
+instruction.  The assembler will do this automatically.  It will also
+detect when it should not pack instructions.  For example, when a label
+is defined, the next instruction will never be packaged with the
+previous one.  Whenever a branch and link instruction is called, it
+will not be packaged with the next instruction so the return address
+will be valid.  Nops are automatically inserted when necessary.
+
+   If you do not want the assembler automatically making these
+decisions, you can control the packaging and execution type (parallel
+or sequential) with the special execution symbols described in the next
+section.
+
+
+File: as.info,  Node: D30V-Chars,  Next: D30V-Guarded,  Prev: D30V-Subs,  Up: D30V-Syntax
+
+8.7.2.3 Special Characters
+..........................
+
+`;' and `#' are the line comment characters.  Sub-instructions may be
+executed in order, in reverse-order, or in parallel.  Instructions
+listed in the standard one-per-line format will be executed
+sequentially unless you use the `-O' option.
+
+   To specify the executing order, use the following symbols:
+`->'
+     Sequential with instruction on the left first.
+
+`<-'
+     Sequential with instruction on the right first.
+
+`||'
+     Parallel
+
+   The D30V syntax allows either one instruction per line, one
+instruction per line with the execution symbol, or two instructions per
+line.  For example
+`abs r2,r3 -> abs r4,r5'
+     Execute these sequentially.  The instruction on the right is in
+     the right container and is executed second.
+
+`abs r2,r3 <- abs r4,r5'
+     Execute these reverse-sequentially.  The instruction on the right
+     is in the right container, and is executed first.
+
+`abs r2,r3 || abs r4,r5'
+     Execute these in parallel.
+
+`ldw r2,@(r3,r4) ||'
+`mulx r6,r8,r9'
+     Two-line format. Execute these in parallel.
+
+`mulx a0,r8,r9'
+`stw r2,@(r3,r4)'
+     Two-line format. Execute these sequentially unless `-O' option is
+     used.  If the `-O' option is used, the assembler will determine if
+     the instructions could be done in parallel (the above two
+     instructions can be done in parallel), and if so, emit them as
+     parallel instructions.  The assembler will put them in the proper
+     containers.  In the above example, the assembler will put the
+     `stw' instruction in left container and the `mulx' instruction in
+     the right container.
+
+`stw r2,@(r3,r4) ->'
+`mulx a0,r8,r9'
+     Two-line format.  Execute the `stw' instruction followed by the
+     `mulx' instruction sequentially.  The first instruction goes in the
+     left container and the second instruction goes into right
+     container.  The assembler will give an error if the machine
+     ordering constraints are violated.
+
+`stw r2,@(r3,r4) <-'
+`mulx a0,r8,r9'
+     Same as previous example, except that the `mulx' instruction is
+     executed before the `stw' instruction.
+
+   Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info,  Node: D30V-Guarded,  Next: D30V-Regs,  Prev: D30V-Chars,  Up: D30V-Syntax
+
+8.7.2.4 Guarded Execution
+.........................
+
+`as' supports the full range of guarded execution directives for each
+instruction.  Just append the directive after the instruction proper.
+The directives are:
+
+`/tx'
+     Execute the instruction if flag f0 is true.
+
+`/fx'
+     Execute the instruction if flag f0 is false.
+
+`/xt'
+     Execute the instruction if flag f1 is true.
+
+`/xf'
+     Execute the instruction if flag f1 is false.
+
+`/tt'
+     Execute the instruction if both flags f0 and f1 are true.
+
+`/tf'
+     Execute the instruction if flag f0 is true and flag f1 is false.
+
+
+File: as.info,  Node: D30V-Regs,  Next: D30V-Addressing,  Prev: D30V-Guarded,  Up: D30V-Syntax
+
+8.7.2.5 Register Names
+......................
+
+You can use the predefined symbols `r0' through `r63' to refer to the
+D30V registers.  You can also use `sp' as an alias for `r63' and `link'
+as an alias for `r62'.  The accumulators are `a0' and `a1'.
+
+   The D30V also has predefined symbols for these control registers and
+status bits:
+`psw'
+     Processor Status Word
+
+`bpsw'
+     Backup Processor Status Word
+
+`pc'
+     Program Counter
+
+`bpc'
+     Backup Program Counter
+
+`rpt_c'
+     Repeat Count
+
+`rpt_s'
+     Repeat Start address
+
+`rpt_e'
+     Repeat End address
+
+`mod_s'
+     Modulo Start address
+
+`mod_e'
+     Modulo End address
+
+`iba'
+     Instruction Break Address
+
+`f0'
+     Flag 0
+
+`f1'
+     Flag 1
+
+`f2'
+     Flag 2
+
+`f3'
+     Flag 3
+
+`f4'
+     Flag 4
+
+`f5'
+     Flag 5
+
+`f6'
+     Flag 6
+
+`f7'
+     Flag 7
+
+`s'
+     Same as flag 4 (saturation flag)
+
+`v'
+     Same as flag 5 (overflow flag)
+
+`va'
+     Same as flag 6 (sticky overflow flag)
+
+`c'
+     Same as flag 7 (carry/borrow flag)
+
+`b'
+     Same as flag 7 (carry/borrow flag)
+
+
+File: as.info,  Node: D30V-Addressing,  Prev: D30V-Regs,  Up: D30V-Syntax
+
+8.7.2.6 Addressing Modes
+........................
+
+`as' understands the following addressing modes for the D30V.  `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+`RN'
+     Register direct
+
+`@RN'
+     Register indirect
+
+`@RN+'
+     Register indirect with post-increment
+
+`@RN-'
+     Register indirect with post-decrement
+
+`@-SP'
+     Register indirect with pre-decrement
+
+`@(DISP, RN)'
+     Register indirect with displacement
+
+`ADDR'
+     PC relative address (for branch or rep).
+
+`#IMM'
+     Immediate data (the `#' is optional and ignored)
+
+
+File: as.info,  Node: D30V-Float,  Next: D30V-Opcodes,  Prev: D30V-Syntax,  Up: D30V-Dependent
+
+8.7.3 Floating Point
+--------------------
+
+The D30V has no hardware floating point, but the `.float' and `.double'
+directives generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info,  Node: D30V-Opcodes,  Prev: D30V-Float,  Up: D30V-Dependent
+
+8.7.4 Opcodes
+-------------
+
+For detailed information on the D30V machine instruction set, see `D30V
+Architecture: A VLIW Microprocessor for Multimedia Applications'
+(Mitsubishi Electric Corp.).  `as' implements all the standard D30V
+opcodes.  The only changes are those described in the section on size
+modifiers
+
+
+File: as.info,  Node: H8/300-Dependent,  Next: HPPA-Dependent,  Prev: D30V-Dependent,  Up: Machine Dependencies
+
+8.8 H8/300 Dependent Features
+=============================
+
+* Menu:
+
+* H8/300 Options::              Options
+* H8/300 Syntax::               Syntax
+* H8/300 Floating Point::       Floating Point
+* H8/300 Directives::           H8/300 Machine Directives
+* H8/300 Opcodes::              Opcodes
+
+
+File: as.info,  Node: H8/300 Options,  Next: H8/300 Syntax,  Up: H8/300-Dependent
+
+8.8.1 Options
+-------------
+
+`as' has no additional command-line options for the Renesas (formerly
+Hitachi) H8/300 family.
+
+
+File: as.info,  Node: H8/300 Syntax,  Next: H8/300 Floating Point,  Prev: H8/300 Options,  Up: H8/300-Dependent
+
+8.8.2 Syntax
+------------
+
+* Menu:
+
+* H8/300-Chars::                Special Characters
+* H8/300-Regs::                 Register Names
+* H8/300-Addressing::           Addressing Modes
+
+
+File: as.info,  Node: H8/300-Chars,  Next: H8/300-Regs,  Up: H8/300 Syntax
+
+8.8.2.1 Special Characters
+..........................
+
+`;' is the line comment character.
+
+   `$' can be used instead of a newline to separate statements.
+Therefore _you may not use `$' in symbol names_ on the H8/300.
+
+
+File: as.info,  Node: H8/300-Regs,  Next: H8/300-Addressing,  Prev: H8/300-Chars,  Up: H8/300 Syntax
+
+8.8.2.2 Register Names
+......................
+
+You can use predefined symbols of the form `rNh' and `rNl' to refer to
+the H8/300 registers as sixteen 8-bit general-purpose registers.  N is
+a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid
+register names.
+
+   You can also use the eight predefined symbols `rN' to refer to the
+H8/300 registers as 16-bit registers (you must use this form for
+addressing).
+
+   On the H8/300H, you can also use the eight predefined symbols `erN'
+(`er0' ... `er7') to refer to the 32-bit general purpose registers.
+
+   The two control registers are called `pc' (program counter; a 16-bit
+register, except on the H8/300H where it is 24 bits) and `ccr'
+(condition code register; an 8-bit register).  `r7' is used as the
+stack pointer, and can also be called `sp'.
+
+
+File: as.info,  Node: H8/300-Addressing,  Prev: H8/300-Regs,  Up: H8/300 Syntax
+
+8.8.2.3 Addressing Modes
+........................
+
+as understands the following addressing modes for the H8/300:
+`rN'
+     Register direct
+
+`@rN'
+     Register indirect
+
+`@(D, rN)'
+`@(D:16, rN)'
+`@(D:24, rN)'
+     Register indirect: 16-bit or 24-bit displacement D from register
+     N.  (24-bit displacements are only meaningful on the H8/300H.)
+
+`@rN+'
+     Register indirect with post-increment
+
+`@-rN'
+     Register indirect with pre-decrement
+
+``@'AA'
+``@'AA:8'
+``@'AA:16'
+``@'AA:24'
+     Absolute address `aa'.  (The address size `:24' only makes sense
+     on the H8/300H.)
+
+`#XX'
+`#XX:8'
+`#XX:16'
+`#XX:32'
+     Immediate data XX.  You may specify the `:8', `:16', or `:32' for
+     clarity, if you wish; but `as' neither requires this nor uses
+     it--the data size required is taken from context.
+
+``@'`@'AA'
+``@'`@'AA:8'
+     Memory indirect.  You may specify the `:8' for clarity, if you
+     wish; but `as' neither requires this nor uses it.
+
+
+File: as.info,  Node: H8/300 Floating Point,  Next: H8/300 Directives,  Prev: H8/300 Syntax,  Up: H8/300-Dependent
+
+8.8.3 Floating Point
+--------------------
+
+The H8/300 family has no hardware floating point, but the `.float'
+directive generates IEEE floating-point numbers for compatibility with
+other development tools.
+
+
+File: as.info,  Node: H8/300 Directives,  Next: H8/300 Opcodes,  Prev: H8/300 Floating Point,  Up: H8/300-Dependent
+
+8.8.4 H8/300 Machine Directives
+-------------------------------
+
+`as' has the following machine-dependent directives for the H8/300:
+
+`.h8300h'
+     Recognize and emit additional instructions for the H8/300H
+     variant, and also make `.int' emit 32-bit numbers rather than the
+     usual (16-bit) for the H8/300 family.
+
+`.h8300s'
+     Recognize and emit additional instructions for the H8S variant, and
+     also make `.int' emit 32-bit numbers rather than the usual (16-bit)
+     for the H8/300 family.
+
+`.h8300hn'
+     Recognize and emit additional instructions for the H8/300H variant
+     in normal mode, and also make `.int' emit 32-bit numbers rather
+     than the usual (16-bit) for the H8/300 family.
+
+`.h8300sn'
+     Recognize and emit additional instructions for the H8S variant in
+     normal mode, and also make `.int' emit 32-bit numbers rather than
+     the usual (16-bit) for the H8/300 family.
+
+   On the H8/300 family (including the H8/300H) `.word' directives
+generate 16-bit numbers.
+
+
+File: as.info,  Node: H8/300 Opcodes,  Prev: H8/300 Directives,  Up: H8/300-Dependent
+
+8.8.5 Opcodes
+-------------
+
+For detailed information on the H8/300 machine instruction set, see
+`H8/300 Series Programming Manual'.  For information specific to the
+H8/300H, see `H8/300H Series Programming Manual' (Renesas).
+
+   `as' implements all the standard H8/300 opcodes.  No additional
+pseudo-instructions are needed on this family.
+
+   The following table summarizes the H8/300 opcodes, and their
+arguments.  Entries marked `*' are opcodes used only on the H8/300H.
+
+              Legend:
+                 Rs   source register
+                 Rd   destination register
+                 abs  absolute address
+                 imm  immediate data
+              disp:N  N-bit displacement from a register
+             pcrel:N  N-bit displacement relative to program counter
+
+        add.b #imm,rd              *  andc #imm,ccr
+        add.b rs,rd                   band #imm,rd
+        add.w rs,rd                   band #imm,@rd
+     *  add.w #imm,rd                 band #imm,@abs:8
+     *  add.l rs,rd                   bra  pcrel:8
+     *  add.l #imm,rd              *  bra  pcrel:16
+        adds #imm,rd                  bt   pcrel:8
+        addx #imm,rd               *  bt   pcrel:16
+        addx rs,rd                    brn  pcrel:8
+        and.b #imm,rd              *  brn  pcrel:16
+        and.b rs,rd                   bf   pcrel:8
+     *  and.w rs,rd                *  bf   pcrel:16
+     *  and.w #imm,rd                 bhi  pcrel:8
+     *  and.l #imm,rd              *  bhi  pcrel:16
+     *  and.l rs,rd                   bls  pcrel:8
+
+     *  bls  pcrel:16                 bld  #imm,rd
+        bcc  pcrel:8                  bld  #imm,@rd
+     *  bcc  pcrel:16                 bld  #imm,@abs:8
+        bhs  pcrel:8                  bnot #imm,rd
+     *  bhs  pcrel:16                 bnot #imm,@rd
+        bcs  pcrel:8                  bnot #imm,@abs:8
+     *  bcs  pcrel:16                 bnot rs,rd
+        blo  pcrel:8                  bnot rs,@rd
+     *  blo  pcrel:16                 bnot rs,@abs:8
+        bne  pcrel:8                  bor  #imm,rd
+     *  bne  pcrel:16                 bor  #imm,@rd
+        beq  pcrel:8                  bor  #imm,@abs:8
+     *  beq  pcrel:16                 bset #imm,rd
+        bvc  pcrel:8                  bset #imm,@rd
+     *  bvc  pcrel:16                 bset #imm,@abs:8
+        bvs  pcrel:8                  bset rs,rd
+     *  bvs  pcrel:16                 bset rs,@rd
+        bpl  pcrel:8                  bset rs,@abs:8
+     *  bpl  pcrel:16                 bsr  pcrel:8
+        bmi  pcrel:8                  bsr  pcrel:16
+     *  bmi  pcrel:16                 bst  #imm,rd
+        bge  pcrel:8                  bst  #imm,@rd
+     *  bge  pcrel:16                 bst  #imm,@abs:8
+        blt  pcrel:8                  btst #imm,rd
+     *  blt  pcrel:16                 btst #imm,@rd
+        bgt  pcrel:8                  btst #imm,@abs:8
+     *  bgt  pcrel:16                 btst rs,rd
+        ble  pcrel:8                  btst rs,@rd
+     *  ble  pcrel:16                 btst rs,@abs:8
+        bclr #imm,rd                  bxor #imm,rd
+        bclr #imm,@rd                 bxor #imm,@rd
+        bclr #imm,@abs:8              bxor #imm,@abs:8
+        bclr rs,rd                    cmp.b #imm,rd
+        bclr rs,@rd                   cmp.b rs,rd
+        bclr rs,@abs:8                cmp.w rs,rd
+        biand #imm,rd                 cmp.w rs,rd
+        biand #imm,@rd             *  cmp.w #imm,rd
+        biand #imm,@abs:8          *  cmp.l #imm,rd
+        bild #imm,rd               *  cmp.l rs,rd
+        bild #imm,@rd                 daa  rs
+        bild #imm,@abs:8              das  rs
+        bior #imm,rd                  dec.b rs
+        bior #imm,@rd              *  dec.w #imm,rd
+        bior #imm,@abs:8           *  dec.l #imm,rd
+        bist #imm,rd                  divxu.b rs,rd
+        bist #imm,@rd              *  divxu.w rs,rd
+        bist #imm,@abs:8           *  divxs.b rs,rd
+        bixor #imm,rd              *  divxs.w rs,rd
+        bixor #imm,@rd                eepmov
+        bixor #imm,@abs:8          *  eepmovw
+
+     *  exts.w rd                     mov.w rs,@abs:16
+     *  exts.l rd                  *  mov.l #imm,rd
+     *  extu.w rd                  *  mov.l rs,rd
+     *  extu.l rd                  *  mov.l @rs,rd
+        inc  rs                    *  mov.l @(disp:16,rs),rd
+     *  inc.w #imm,rd              *  mov.l @(disp:24,rs),rd
+     *  inc.l #imm,rd              *  mov.l @rs+,rd
+        jmp  @rs                   *  mov.l @abs:16,rd
+        jmp  abs                   *  mov.l @abs:24,rd
+        jmp  @@abs:8               *  mov.l rs,@rd
+        jsr  @rs                   *  mov.l rs,@(disp:16,rd)
+        jsr  abs                   *  mov.l rs,@(disp:24,rd)
+        jsr  @@abs:8               *  mov.l rs,@-rd
+        ldc  #imm,ccr              *  mov.l rs,@abs:16
+        ldc  rs,ccr                *  mov.l rs,@abs:24
+     *  ldc  @abs:16,ccr              movfpe @abs:16,rd
+     *  ldc  @abs:24,ccr              movtpe rs,@abs:16
+     *  ldc  @(disp:16,rs),ccr        mulxu.b rs,rd
+     *  ldc  @(disp:24,rs),ccr     *  mulxu.w rs,rd
+     *  ldc  @rs+,ccr              *  mulxs.b rs,rd
+     *  ldc  @rs,ccr               *  mulxs.w rs,rd
+     *  mov.b @(disp:24,rs),rd        neg.b rs
+     *  mov.b rs,@(disp:24,rd)     *  neg.w rs
+        mov.b @abs:16,rd           *  neg.l rs
+        mov.b rs,rd                   nop
+        mov.b @abs:8,rd               not.b rs
+        mov.b rs,@abs:8            *  not.w rs
+        mov.b rs,rd                *  not.l rs
+        mov.b #imm,rd                 or.b #imm,rd
+        mov.b @rs,rd                  or.b rs,rd
+        mov.b @(disp:16,rs),rd     *  or.w #imm,rd
+        mov.b @rs+,rd              *  or.w rs,rd
+        mov.b @abs:8,rd            *  or.l #imm,rd
+        mov.b rs,@rd               *  or.l rs,rd
+        mov.b rs,@(disp:16,rd)        orc  #imm,ccr
+        mov.b rs,@-rd                 pop.w rs
+        mov.b rs,@abs:8            *  pop.l rs
+        mov.w rs,@rd                  push.w rs
+     *  mov.w @(disp:24,rs),rd     *  push.l rs
+     *  mov.w rs,@(disp:24,rd)        rotl.b rs
+     *  mov.w @abs:24,rd           *  rotl.w rs
+     *  mov.w rs,@abs:24           *  rotl.l rs
+        mov.w rs,rd                   rotr.b rs
+        mov.w #imm,rd              *  rotr.w rs
+        mov.w @rs,rd               *  rotr.l rs
+        mov.w @(disp:16,rs),rd        rotxl.b rs
+        mov.w @rs+,rd              *  rotxl.w rs
+        mov.w @abs:16,rd           *  rotxl.l rs
+        mov.w rs,@(disp:16,rd)        rotxr.b rs
+        mov.w rs,@-rd              *  rotxr.w rs
+
+     *  rotxr.l rs                 *  stc  ccr,@(disp:24,rd)
+        bpt                        *  stc  ccr,@-rd
+        rte                        *  stc  ccr,@abs:16
+        rts                        *  stc  ccr,@abs:24
+        shal.b rs                     sub.b rs,rd
+     *  shal.w rs                     sub.w rs,rd
+     *  shal.l rs                  *  sub.w #imm,rd
+        shar.b rs                  *  sub.l rs,rd
+     *  shar.w rs                  *  sub.l #imm,rd
+     *  shar.l rs                     subs #imm,rd
+        shll.b rs                     subx #imm,rd
+     *  shll.w rs                     subx rs,rd
+     *  shll.l rs                  *  trapa #imm
+        shlr.b rs                     xor  #imm,rd
+     *  shlr.w rs                     xor  rs,rd
+     *  shlr.l rs                  *  xor.w #imm,rd
+        sleep                      *  xor.w rs,rd
+        stc  ccr,rd                *  xor.l #imm,rd
+     *  stc  ccr,@rs               *  xor.l rs,rd
+     *  stc  ccr,@(disp:16,rd)        xorc #imm,ccr
+
+   Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined
+with variants using the suffixes `.b', `.w', and `.l' to specify the
+size of a memory operand.  `as' supports these suffixes, but does not
+require them; since one of the operands is always a register, `as' can
+deduce the correct size.
+
+   For example, since `r0' refers to a 16-bit register,
+     mov    r0,@foo
+is equivalent to
+     mov.w  r0,@foo
+
+   If you use the size suffixes, `as' issues a warning when the suffix
+and the register size do not match.
+
+
+File: as.info,  Node: HPPA-Dependent,  Next: ESA/390-Dependent,  Prev: H8/300-Dependent,  Up: Machine Dependencies
+
+8.9 HPPA Dependent Features
+===========================
+
+* Menu:
+
+* HPPA Notes::                Notes
+* HPPA Options::              Options
+* HPPA Syntax::               Syntax
+* HPPA Floating Point::       Floating Point
+* HPPA Directives::           HPPA Machine Directives
+* HPPA Opcodes::              Opcodes
+
+
+File: as.info,  Node: HPPA Notes,  Next: HPPA Options,  Up: HPPA-Dependent
+
+8.9.1 Notes
+-----------
+
+As a back end for GNU CC `as' has been throughly tested and should work
+extremely well.  We have tested it only minimally on hand written
+assembly code and no one has tested it much on the assembly output from
+the HP compilers.
+
+   The format of the debugging sections has changed since the original
+`as' port (version 1.3X) was released; therefore, you must rebuild all
+HPPA objects and libraries with the new assembler so that you can debug
+the final executable.
+
+   The HPPA `as' port generates a small subset of the relocations
+available in the SOM and ELF object file formats.  Additional relocation
+support will be added as it becomes necessary.
+
+
+File: as.info,  Node: HPPA Options,  Next: HPPA Syntax,  Prev: HPPA Notes,  Up: HPPA-Dependent
+
+8.9.2 Options
+-------------
+
+`as' has no machine-dependent command-line options for the HPPA.
+
+
+File: as.info,  Node: HPPA Syntax,  Next: HPPA Floating Point,  Prev: HPPA Options,  Up: HPPA-Dependent
+
+8.9.3 Syntax
+------------
+
+The assembler syntax closely follows the HPPA instruction set reference
+manual; assembler directives and general syntax closely follow the HPPA
+assembly language reference manual, with a few noteworthy differences.
+
+   First, a colon may immediately follow a label definition.  This is
+simply for compatibility with how most assembly language programmers
+write code.
+
+   Some obscure expression parsing problems may affect hand written
+code which uses the `spop' instructions, or code which makes significant
+use of the `!' line separator.
+
+   `as' is much less forgiving about missing arguments and other
+similar oversights than the HP assembler.  `as' notifies you of missing
+arguments as syntax errors; this is regarded as a feature, not a bug.
+
+   Finally, `as' allows you to use an external symbol without
+explicitly importing the symbol.  _Warning:_ in the future this will be
+an error for HPPA targets.
+
+   Special characters for HPPA targets include:
+
+   `;' is the line comment character.
+
+   `!' can be used instead of a newline to separate statements.
+
+   Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info,  Node: HPPA Floating Point,  Next: HPPA Directives,  Prev: HPPA Syntax,  Up: HPPA-Dependent
+
+8.9.4 Floating Point
+--------------------
+
+The HPPA family uses IEEE floating-point numbers.
+
+
+File: as.info,  Node: HPPA Directives,  Next: HPPA Opcodes,  Prev: HPPA Floating Point,  Up: HPPA-Dependent
+
+8.9.5 HPPA Assembler Directives
+-------------------------------
+
+`as' for the HPPA supports many additional directives for compatibility
+with the native assembler.  This section describes them only briefly.
+For detailed information on HPPA-specific assembler directives, see
+`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001).
+
+   `as' does _not_ support the following assembler directives described
+in the HP manual:
+
+     .endm           .liston
+     .enter          .locct
+     .leave          .macro
+     .listoff
+
+   Beyond those implemented for compatibility, `as' supports one
+additional assembler directive for the HPPA: `.param'.  It conveys
+register argument locations for static functions.  Its syntax closely
+follows the `.export' directive.
+
+   These are the additional directives in `as' for the HPPA:
+
+`.block N'
+`.blockz N'
+     Reserve N bytes of storage, and initialize them to zero.
+
+`.call'
+     Mark the beginning of a procedure call.  Only the special case
+     with _no arguments_ is allowed.
+
+`.callinfo [ PARAM=VALUE, ... ]  [ FLAG, ... ]'
+     Specify a number of parameters and flags that define the
+     environment for a procedure.
+
+     PARAM may be any of `frame' (frame size), `entry_gr' (end of
+     general register range), `entry_fr' (end of float register range),
+     `entry_sr' (end of space register range).
+
+     The values for FLAG are `calls' or `caller' (proc has
+     subroutines), `no_calls' (proc does not call subroutines),
+     `save_rp' (preserve return pointer), `save_sp' (proc preserves
+     stack pointer), `no_unwind' (do not unwind this proc), `hpux_int'
+     (proc is interrupt routine).
+
+`.code'
+     Assemble into the standard section called `$TEXT$', subsection
+     `$CODE$'.
+
+`.copyright "STRING"'
+     In the SOM object format, insert STRING into the object code,
+     marked as a copyright string.
+
+`.copyright "STRING"'
+     In the ELF object format, insert STRING into the object code,
+     marked as a version string.
+
+`.enter'
+     Not yet supported; the assembler rejects programs containing this
+     directive.
+
+`.entry'
+     Mark the beginning of a procedure.
+
+`.exit'
+     Mark the end of a procedure.
+
+`.export NAME [ ,TYP ]  [ ,PARAM=R ]'
+     Make a procedure NAME available to callers.  TYP, if present, must
+     be one of `absolute', `code' (ELF only, not SOM), `data', `entry',
+     `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.
+
+     PARAM, if present, provides either relocation information for the
+     procedure arguments and result, or a privilege level.  PARAM may be
+     `argwN' (where N ranges from `0' to `3', and indicates one of four
+     one-word arguments); `rtnval' (the procedure's result); or
+     `priv_lev' (privilege level).  For arguments or the result, R
+     specifies how to relocate, and must be one of `no' (not
+     relocatable), `gr' (argument is in general register), `fr' (in
+     floating point register), or `fu' (upper half of float register).
+     For `priv_lev', R is an integer.
+
+`.half N'
+     Define a two-byte integer constant N; synonym for the portable
+     `as' directive `.short'.
+
+`.import NAME [ ,TYP ]'
+     Converse of `.export'; make a procedure available to call.  The
+     arguments use the same conventions as the first two arguments for
+     `.export'.
+
+`.label NAME'
+     Define NAME as a label for the current assembly location.
+
+`.leave'
+     Not yet supported; the assembler rejects programs containing this
+     directive.
+
+`.origin LC'
+     Advance location counter to LC. Synonym for the `as' portable
+     directive `.org'.
+
+`.param NAME [ ,TYP ]  [ ,PARAM=R ]'
+     Similar to `.export', but used for static procedures.
+
+`.proc'
+     Use preceding the first statement of a procedure.
+
+`.procend'
+     Use following the last statement of a procedure.
+
+`LABEL .reg EXPR'
+     Synonym for `.equ'; define LABEL with the absolute expression EXPR
+     as its value.
+
+`.space SECNAME [ ,PARAMS ]'
+     Switch to section SECNAME, creating a new section by that name if
+     necessary.  You may only use PARAMS when creating a new section,
+     not when switching to an existing one.  SECNAME may identify a
+     section by number rather than by name.
+
+     If specified, the list PARAMS declares attributes of the section,
+     identified by keywords.  The keywords recognized are `spnum=EXP'
+     (identify this section by the number EXP, an absolute expression),
+     `sort=EXP' (order sections according to this sort key when linking;
+     EXP is an absolute expression), `unloadable' (section contains no
+     loadable data), `notdefined' (this section defined elsewhere), and
+     `private' (data in this section not available to other programs).
+
+`.spnum SECNAM'
+     Allocate four bytes of storage, and initialize them with the
+     section number of the section named SECNAM.  (You can define the
+     section number with the HPPA `.space' directive.)
+
+`.string "STR"'
+     Copy the characters in the string STR to the object file.  *Note
+     Strings: Strings, for information on escape sequences you can use
+     in `as' strings.
+
+     _Warning!_ The HPPA version of `.string' differs from the usual
+     `as' definition: it does _not_ write a zero byte after copying STR.
+
+`.stringz "STR"'
+     Like `.string', but appends a zero byte after copying STR to object
+     file.
+
+`.subspa NAME [ ,PARAMS ]'
+`.nsubspa NAME [ ,PARAMS ]'
+     Similar to `.space', but selects a subsection NAME within the
+     current section.  You may only specify PARAMS when you create a
+     subsection (in the first instance of `.subspa' for this NAME).
+
+     If specified, the list PARAMS declares attributes of the
+     subsection, identified by keywords.  The keywords recognized are
+     `quad=EXPR' ("quadrant" for this subsection), `align=EXPR'
+     (alignment for beginning of this subsection; a power of two),
+     `access=EXPR' (value for "access rights" field), `sort=EXPR'
+     (sorting order for this subspace in link), `code_only' (subsection
+     contains only code), `unloadable' (subsection cannot be loaded
+     into memory), `comdat' (subsection is comdat), `common'
+     (subsection is common block), `dup_comm' (subsection may have
+     duplicate names), or `zero' (subsection is all zeros, do not write
+     in object file).
+
+     `.nsubspa' always creates a new subspace with the given name, even
+     if one with the same name already exists.
+
+     `comdat', `common' and `dup_comm' can be used to implement various
+     flavors of one-only support when using the SOM linker.  The SOM
+     linker only supports specific combinations of these flags.  The
+     details are not documented.  A brief description is provided here.
+
+     `comdat' provides a form of linkonce support.  It is useful for
+     both code and data subspaces.  A `comdat' subspace has a key symbol
+     marked by the `is_comdat' flag or `ST_COMDAT'.  Only the first
+     subspace for any given key is selected.  The key symbol becomes
+     universal in shared links.  This is similar to the behavior of
+     `secondary_def' symbols.
+
+     `common' provides Fortran named common support.  It is only useful
+     for data subspaces.  Symbols with the flag `is_common' retain this
+     flag in shared links.  Referencing a `is_common' symbol in a shared
+     library from outside the library doesn't work.  Thus, `is_common'
+     symbols must be output whenever they are needed.
+
+     `common' and `dup_comm' together provide Cobol common support.
+     The subspaces in this case must all be the same length.
+     Otherwise, this support is similar to the Fortran common support.
+
+     `dup_comm' by itself provides a type of one-only support for code.
+     Only the first `dup_comm' subspace is selected.  There is a rather
+     complex algorithm to compare subspaces.  Code symbols marked with
+     the `dup_common' flag are hidden.  This support was intended for
+     "C++ duplicate inlines".
+
+     A simplified technique is used to mark the flags of symbols based
+     on the flags of their subspace.  A symbol with the scope
+     SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with
+     the corresponding settings of `comdat', `common' and `dup_comm'
+     from the subspace, respectively.  This avoids having to introduce
+     additional directives to mark these symbols.  The HP assembler
+     sets `is_common' from `common'.  However, it doesn't set the
+     `dup_common' from `dup_comm'.  It doesn't have `comdat' support.
+
+`.version "STR"'
+     Write STR as version identifier in object code.
+
+
+File: as.info,  Node: HPPA Opcodes,  Prev: HPPA Directives,  Up: HPPA-Dependent
+
+8.9.6 Opcodes
+-------------
+
+For detailed information on the HPPA machine instruction set, see
+`PA-RISC Architecture and Instruction Set Reference Manual' (HP
+09740-90039).
+
+
+File: as.info,  Node: ESA/390-Dependent,  Next: i386-Dependent,  Prev: HPPA-Dependent,  Up: Machine Dependencies
+
+8.10 ESA/390 Dependent Features
+===============================
+
+* Menu:
+
+* ESA/390 Notes::                Notes
+* ESA/390 Options::              Options
+* ESA/390 Syntax::               Syntax
+* ESA/390 Floating Point::       Floating Point
+* ESA/390 Directives::           ESA/390 Machine Directives
+* ESA/390 Opcodes::              Opcodes
+
+
+File: as.info,  Node: ESA/390 Notes,  Next: ESA/390 Options,  Up: ESA/390-Dependent
+
+8.10.1 Notes
+------------
+
+The ESA/390 `as' port is currently intended to be a back-end for the
+GNU CC compiler.  It is not HLASM compatible, although it does support
+a subset of some of the HLASM directives.  The only supported binary
+file format is ELF; none of the usual MVS/VM/OE/USS object file
+formats, such as ESD or XSD, are supported.
+
+   When used with the GNU CC compiler, the ESA/390 `as' will produce
+correct, fully relocated, functional binaries, and has been used to
+compile and execute large projects.  However, many aspects should still
+be considered experimental; these include shared library support,
+dynamically loadable objects, and any relocation other than the 31-bit
+relocation.
+
+
+File: as.info,  Node: ESA/390 Options,  Next: ESA/390 Syntax,  Prev: ESA/390 Notes,  Up: ESA/390-Dependent
+
+8.10.2 Options
+--------------
+
+`as' has no machine-dependent command-line options for the ESA/390.
+
+
+File: as.info,  Node: ESA/390 Syntax,  Next: ESA/390 Floating Point,  Prev: ESA/390 Options,  Up: ESA/390-Dependent
+
+8.10.3 Syntax
+-------------
+
+The opcode/operand syntax follows the ESA/390 Principles of Operation
+manual; assembler directives and general syntax are loosely based on the
+prevailing AT&T/SVR4/ELF/Solaris style notation.  HLASM-style directives
+are _not_ supported for the most part, with the exception of those
+described herein.
+
+   A leading dot in front of directives is optional, and the case of
+directives is ignored; thus for example, .using and USING have the same
+effect.
+
+   A colon may immediately follow a label definition.  This is simply
+for compatibility with how most assembly language programmers write
+code.
+
+   `#' is the line comment character.
+
+   `;' can be used instead of a newline to separate statements.
+
+   Since `$' has no special meaning, you may use it in symbol names.
+
+   Registers can be given the symbolic names r0..r15, fp0, fp2, fp4,
+fp6.  By using thesse symbolic names, `as' can detect simple syntax
+errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for
+r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
+for r3 and rpgt or r.pgt for r4.
+
+   `*' is the current location counter.  Unlike `.' it is always
+relative to the last USING directive.  Note that this means that
+expressions cannot use multiplication, as any occurrence of `*' will be
+interpreted as a location counter.
+
+   All labels are relative to the last USING.  Thus, branches to a label
+always imply the use of base+displacement.
+
+   Many of the usual forms of address constants / address literals are
+supported.  Thus,
+     	.using	*,r3
+     	L	r15,=A(some_routine)
+     	LM	r6,r7,=V(some_longlong_extern)
+     	A	r1,=F'12'
+     	AH	r0,=H'42'
+     	ME	r6,=E'3.1416'
+     	MD	r6,=D'3.14159265358979'
+     	O	r6,=XL4'cacad0d0'
+     	.ltorg
+   should all behave as expected: that is, an entry in the literal pool
+will be created (or reused if it already exists), and the instruction
+operands will be the displacement into the literal pool using the
+current base register (as last declared with the `.using' directive).
+
+
+File: as.info,  Node: ESA/390 Floating Point,  Next: ESA/390 Directives,  Prev: ESA/390 Syntax,  Up: ESA/390-Dependent
+
+8.10.4 Floating Point
+---------------------
+
+The assembler generates only IEEE floating-point numbers.  The older
+floating point formats are not supported.
+
+
+File: as.info,  Node: ESA/390 Directives,  Next: ESA/390 Opcodes,  Prev: ESA/390 Floating Point,  Up: ESA/390-Dependent
+
+8.10.5 ESA/390 Assembler Directives
+-----------------------------------
+
+`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler
+directives that are documented in the main part of this documentation.
+Several additional directives are supported in order to implement the
+ESA/390 addressing model.  The most important of these are `.using' and
+`.ltorg'
+
+   These are the additional directives in `as' for the ESA/390:
+
+`.dc'
+     A small subset of the usual DC directive is supported.
+
+`.drop REGNO'
+     Stop using REGNO as the base register.  The REGNO must have been
+     previously declared with a `.using' directive in the same section
+     as the current section.
+
+`.ebcdic STRING'
+     Emit the EBCDIC equivalent of the indicated string.  The emitted
+     string will be null terminated.  Note that the directives
+     `.string' etc. emit ascii strings by default.
+
+`EQU'
+     The standard HLASM-style EQU directive is not supported; however,
+     the standard `as' directive .equ can be used to the same effect.
+
+`.ltorg'
+     Dump the literal pool accumulated so far; begin a new literal pool.
+     The literal pool will be written in the current section; in order
+     to generate correct assembly, a `.using' must have been previously
+     specified in the same section.
+
+`.using EXPR,REGNO'
+     Use REGNO as the base register for all subsequent RX, RS, and SS
+     form instructions. The EXPR will be evaluated to obtain the base
+     address; usually, EXPR will merely be `*'.
+
+     This assembler allows two `.using' directives to be simultaneously
+     outstanding, one in the `.text' section, and one in another section
+     (typically, the `.data' section).  This feature allows dynamically
+     loaded objects to be implemented in a relatively straightforward
+     way.  A `.using' directive must always be specified in the `.text'
+     section; this will specify the base register that will be used for
+     branches in the `.text' section.  A second `.using' may be
+     specified in another section; this will specify the base register
+     that is used for non-label address literals.  When a second
+     `.using' is specified, then the subsequent `.ltorg' must be put in
+     the same section; otherwise an error will result.
+
+     Thus, for example, the following code uses `r3' to address branch
+     targets and `r4' to address the literal pool, which has been
+     written to the `.data' section.  The is, the constants
+     `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in
+     the `.data' section.
+
+          .data
+          	.using  LITPOOL,r4
+          .text
+          	BASR	r3,0
+          	.using	*,r3
+                  B       START
+          	.long	LITPOOL
+          START:
+          	L	r4,4(,r3)
+          	L	r15,=A(some_routine)
+          	LTR	r15,r15
+          	BNE	LABEL
+          	AH	r0,=H'42'
+          LABEL:
+          	ME	r6,=E'3.1416'
+          .data
+          LITPOOL:
+          	.ltorg
+
+     Note that this dual-`.using' directive semantics extends and is
+     not compatible with HLASM semantics.  Note that this assembler
+     directive does not support the full range of HLASM semantics.
+
+
+
+File: as.info,  Node: ESA/390 Opcodes,  Prev: ESA/390 Directives,  Up: ESA/390-Dependent
+
+8.10.6 Opcodes
+--------------
+
+For detailed information on the ESA/390 machine instruction set, see
+`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004).
+
+
+File: as.info,  Node: i386-Dependent,  Next: i860-Dependent,  Prev: ESA/390-Dependent,  Up: Machine Dependencies
+
+8.11 80386 Dependent Features
+=============================
+
+   The i386 version `as' supports both the original Intel 386
+architecture in both 16 and 32-bit mode as well as AMD x86-64
+architecture extending the Intel architecture to 64-bits.
+
+* Menu:
+
+* i386-Options::                Options
+* i386-Syntax::                 AT&T Syntax versus Intel Syntax
+* i386-Mnemonics::              Instruction Naming
+* i386-Regs::                   Register Naming
+* i386-Prefixes::               Instruction Prefixes
+* i386-Memory::                 Memory References
+* i386-Jumps::                  Handling of Jump Instructions
+* i386-Float::                  Floating Point
+* i386-SIMD::                   Intel's MMX and AMD's 3DNow! SIMD Operations
+* i386-16bit::                  Writing 16-bit Code
+* i386-Arch::                   Specifying an x86 CPU architecture
+* i386-Bugs::                   AT&T Syntax bugs
+* i386-Notes::                  Notes
+
+
+File: as.info,  Node: i386-Options,  Next: i386-Syntax,  Up: i386-Dependent
+
+8.11.1 Options
+--------------
+
+The i386 version of `as' has a few machine dependent options:
+
+`--32 | --64'
+     Select the word size, either 32 bits or 64 bits. Selecting 32-bit
+     implies Intel i386 architecture, while 64-bit implies AMD x86-64
+     architecture.
+
+     These options are only available with the ELF object file format,
+     and require that the necessary BFD support has been included (on a
+     32-bit platform you have to add -enable-64-bit-bfd to configure
+     enable 64-bit usage and use x86-64 as target platform).
+
+`-n'
+     By default, x86 GAS replaces multiple nop instructions used for
+     alignment within code sections with multi-byte nop instructions
+     such as leal 0(%esi,1),%esi.  This switch disables the
+     optimization.
+
+`--divide'
+     On SVR4-derived platforms, the character `/' is treated as a
+     comment character, which means that it cannot be used in
+     expressions.  The `--divide' option turns `/' into a normal
+     character.  This does not disable `/' at the beginning of a line
+     starting a comment, or affect using `#' for starting a comment.
+
+
+
+File: as.info,  Node: i386-Syntax,  Next: i386-Mnemonics,  Prev: i386-Options,  Up: i386-Dependent
+
+8.11.2 AT&T Syntax versus Intel Syntax
+--------------------------------------
+
+`as' now supports assembly using Intel assembler syntax.
+`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to
+the usual AT&T mode for compatibility with the output of `gcc'.  Either
+of these directives may have an optional argument, `prefix', or
+`noprefix' specifying whether registers require a `%' prefix.  AT&T
+System V/386 assembler syntax is quite different from Intel syntax.  We
+mention these differences because almost all 80386 documents use Intel
+syntax.  Notable differences between the two syntaxes are:
+
+   * AT&T immediate operands are preceded by `$'; Intel immediate
+     operands are undelimited (Intel `push 4' is AT&T `pushl $4').
+     AT&T register operands are preceded by `%'; Intel register operands
+     are undelimited.  AT&T absolute (as opposed to PC relative)
+     jump/call operands are prefixed by `*'; they are undelimited in
+     Intel syntax.
+
+   * AT&T and Intel syntax use the opposite order for source and
+     destination operands.  Intel `add eax, 4' is `addl $4, %eax'.  The
+     `source, dest' convention is maintained for compatibility with
+     previous Unix assemblers.  Note that instructions with more than
+     one source operand, such as the `enter' instruction, do _not_ have
+     reversed order.  *Note i386-Bugs::.
+
+   * In AT&T syntax the size of memory operands is determined from the
+     last character of the instruction mnemonic.  Mnemonic suffixes of
+     `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long
+     (32-bit) and quadruple word (64-bit) memory references.  Intel
+     syntax accomplishes this by prefixing memory operands (_not_ the
+     instruction mnemonics) with `byte ptr', `word ptr', `dword ptr'
+     and `qword ptr'.  Thus, Intel `mov al, byte ptr FOO' is `movb FOO,
+     %al' in AT&T syntax.
+
+   * Immediate form long jumps and calls are `lcall/ljmp $SECTION,
+     $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far
+     SECTION:OFFSET'.  Also, the far return instruction is `lret
+     $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far
+     STACK-ADJUST'.
+
+   * The AT&T assembler does not provide support for multiple section
+     programs.  Unix style systems expect all programs to be single
+     sections.
+
+
+File: as.info,  Node: i386-Mnemonics,  Next: i386-Regs,  Prev: i386-Syntax,  Up: i386-Dependent
+
+8.11.3 Instruction Naming
+-------------------------
+
+Instruction mnemonics are suffixed with one character modifiers which
+specify the size of operands.  The letters `b', `w', `l' and `q'
+specify byte, word, long and quadruple word operands.  If no suffix is
+specified by an instruction then `as' tries to fill in the missing
+suffix based on the destination register operand (the last one by
+convention).  Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx';
+also, `mov $1, %bx' is equivalent to `movw $1, bx'.  Note that this is
+incompatible with the AT&T Unix assembler which assumes that a missing
+mnemonic suffix implies long operand size.  (This incompatibility does
+not affect compiler output since compilers always explicitly specify
+the mnemonic suffix.)
+
+   Almost all instructions have the same names in AT&T and Intel format.
+There are a few exceptions.  The sign extend and zero extend
+instructions need two sizes to specify them.  They need a size to
+sign/zero extend _from_ and a size to zero extend _to_.  This is
+accomplished by using two instruction mnemonic suffixes in AT&T syntax.
+Base names for sign extend and zero extend are `movs...' and `movz...'
+in AT&T syntax (`movsx' and `movzx' in Intel syntax).  The instruction
+mnemonic suffixes are tacked on to this base name, the _from_ suffix
+before the _to_ suffix.  Thus, `movsbl %al, %edx' is AT&T syntax for
+"move sign extend _from_ %al _to_ %edx."  Possible suffixes, thus, are
+`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to
+long), `bq' (from byte to quadruple word), `wq' (from word to quadruple
+word), and `lq' (from long to quadruple word).
+
+   The Intel-syntax conversion instructions
+
+   * `cbw' -- sign-extend byte in `%al' to word in `%ax',
+
+   * `cwde' -- sign-extend word in `%ax' to long in `%eax',
+
+   * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',
+
+   * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',
+
+   * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64
+     only),
+
+   * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax'
+     (x86-64 only),
+
+are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T
+naming.  `as' accepts either naming for these instructions.
+
+   Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax,
+but are `call far' and `jump far' in Intel convention.
+
+
+File: as.info,  Node: i386-Regs,  Next: i386-Prefixes,  Prev: i386-Mnemonics,  Up: i386-Dependent
+
+8.11.4 Register Naming
+----------------------
+
+Register operands are always prefixed with `%'.  The 80386 registers
+consist of
+
+   * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx',
+     `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp'
+     (the stack pointer).
+
+   * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di',
+     `%si', `%bp', and `%sp'.
+
+   * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl',
+     `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax',
+     `%bx', `%cx', and `%dx')
+
+   * the 6 section registers `%cs' (code section), `%ds' (data
+     section), `%ss' (stack section), `%es', `%fs', and `%gs'.
+
+   * the 3 processor control registers `%cr0', `%cr2', and `%cr3'.
+
+   * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and
+     `%db7'.
+
+   * the 2 test registers `%tr6' and `%tr7'.
+
+   * the 8 floating point register stack `%st' or equivalently
+     `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)',
+     `%st(6)', and `%st(7)'.  These registers are overloaded by 8 MMX
+     registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6'
+     and `%mm7'.
+
+   * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3',
+     `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.
+
+   The AMD x86-64 architecture extends the register set by:
+
+   * enhancing the 8 32-bit registers to 64-bit: `%rax' (the
+     accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the
+     frame pointer), `%rsp' (the stack pointer)
+
+   * the 8 extended registers `%r8'-`%r15'.
+
+   * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d'
+
+   * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w'
+
+   * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b'
+
+   * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'.
+
+   * the 8 debug registers: `%db8'-`%db15'.
+
+   * the 8 SSE registers: `%xmm8'-`%xmm15'.
+
+
+File: as.info,  Node: i386-Prefixes,  Next: i386-Memory,  Prev: i386-Regs,  Up: i386-Dependent
+
+8.11.5 Instruction Prefixes
+---------------------------
+
+Instruction prefixes are used to modify the following instruction.  They
+are used to repeat string instructions, to provide section overrides, to
+perform bus lock operations, and to change operand and address sizes.
+(Most instructions that normally operate on 32-bit operands will use
+16-bit operands if the instruction has an "operand size" prefix.)
+Instruction prefixes are best written on the same line as the
+instruction they act upon. For example, the `scas' (scan string)
+instruction is repeated with:
+
+             repne scas %es:(%edi),%al
+
+   You may also place prefixes on the lines immediately preceding the
+instruction, but this circumvents checks that `as' does with prefixes,
+and will not work with all prefixes.
+
+   Here is a list of instruction prefixes:
+
+   * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'.
+     These are automatically added by specifying using the
+     SECTION:MEMORY-OPERAND form for memory references.
+
+   * Operand/Address size prefixes `data16' and `addr16' change 32-bit
+     operands/addresses into 16-bit operands/addresses, while `data32'
+     and `addr32' change 16-bit ones (in a `.code16' section) into
+     32-bit operands/addresses.  These prefixes _must_ appear on the
+     same line of code as the instruction they modify. For example, in
+     a 16-bit `.code16' section, you might write:
+
+                  addr32 jmpl *(%ebx)
+
+   * The bus lock prefix `lock' inhibits interrupts during execution of
+     the instruction it precedes.  (This is only valid with certain
+     instructions; see a 80386 manual for details).
+
+   * The wait for coprocessor prefix `wait' waits for the coprocessor to
+     complete the current instruction.  This should never be needed for
+     the 80386/80387 combination.
+
+   * The `rep', `repe', and `repne' prefixes are added to string
+     instructions to make them repeat `%ecx' times (`%cx' times if the
+     current address size is 16-bits).  
+
+   * The `rex' family of prefixes is used by x86-64 to encode
+     extensions to i386 instruction set.  The `rex' prefix has four
+     bits -- an operand size overwrite (`64') used to change operand
+     size from 32-bit to 64-bit and X, Y and Z extensions bits used to
+     extend the register set.
+
+     You may write the `rex' prefixes directly. The `rex64xyz'
+     instruction emits `rex' prefix with all the bits set.  By omitting
+     the `64', `x', `y' or `z' you may write other prefixes as well.
+     Normally, there is no need to write the prefixes explicitly, since
+     gas will automatically generate them based on the instruction
+     operands.
+
+
+File: as.info,  Node: i386-Memory,  Next: i386-Jumps,  Prev: i386-Prefixes,  Up: i386-Dependent
+
+8.11.6 Memory References
+------------------------
+
+An Intel syntax indirect memory reference of the form
+
+     SECTION:[BASE + INDEX*SCALE + DISP]
+
+is translated into the AT&T syntax
+
+     SECTION:DISP(BASE, INDEX, SCALE)
+
+where BASE and INDEX are the optional 32-bit base and index registers,
+DISP is the optional displacement, and SCALE, taking the values 1, 2,
+4, and 8, multiplies INDEX to calculate the address of the operand.  If
+no SCALE is specified, SCALE is taken to be 1.  SECTION specifies the
+optional section register for the memory operand, and may override the
+default section register (see a 80386 manual for section register
+defaults). Note that section overrides in AT&T syntax _must_ be
+preceded by a `%'.  If you specify a section override which coincides
+with the default section register, `as' does _not_ output any section
+register override prefixes to assemble the given instruction.  Thus,
+section overrides can be specified to emphasize which section register
+is used for a given memory operand.
+
+   Here are some examples of Intel and AT&T style memory references:
+
+AT&T: `-4(%ebp)', Intel:  `[ebp - 4]'
+     BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default
+     section is used (`%ss' for addressing with `%ebp' as the base
+     register).  INDEX, SCALE are both missing.
+
+AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'
+     INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'.  All other
+     fields are missing.  The section register here defaults to `%ds'.
+
+AT&T: `foo(,1)'; Intel `[foo]'
+     This uses the value pointed to by `foo' as a memory operand.  Note
+     that BASE and INDEX are both missing, but there is only _one_ `,'.
+     This is a syntactic exception.
+
+AT&T: `%gs:foo'; Intel `gs:foo'
+     This selects the contents of the variable `foo' with section
+     register SECTION being `%gs'.
+
+   Absolute (as opposed to PC relative) call and jump operands must be
+prefixed with `*'.  If no `*' is specified, `as' always chooses PC
+relative addressing for jump/call labels.
+
+   Any instruction that has a memory operand, but no register operand,
+_must_ specify its size (byte, word, long, or quadruple) with an
+instruction mnemonic suffix (`b', `w', `l' or `q', respectively).
+
+   The x86-64 architecture adds an RIP (instruction pointer relative)
+addressing.  This addressing mode is specified by using `rip' as a base
+register.  Only constant offsets are valid. For example:
+
+AT&T: `1234(%rip)', Intel: `[rip + 1234]'
+     Points to the address 1234 bytes past the end of the current
+     instruction.
+
+AT&T: `symbol(%rip)', Intel: `[rip + symbol]'
+     Points to the `symbol' in RIP relative way, this is shorter than
+     the default absolute addressing.
+
+   Other addressing modes remain unchanged in x86-64 architecture,
+except registers used are 64-bit instead of 32-bit.
+
+
+File: as.info,  Node: i386-Jumps,  Next: i386-Float,  Prev: i386-Memory,  Up: i386-Dependent
+
+8.11.7 Handling of Jump Instructions
+------------------------------------
+
+Jump instructions are always optimized to use the smallest possible
+displacements.  This is accomplished by using byte (8-bit) displacement
+jumps whenever the target is sufficiently close.  If a byte displacement
+is insufficient a long displacement is used.  We do not support word
+(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
+instruction with the `data16' instruction prefix), since the 80386
+insists upon masking `%eip' to 16 bits after the word displacement is
+added. (See also *note i386-Arch::)
+
+   Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz'
+and `loopne' instructions only come in byte displacements, so that if
+you use these instructions (`gcc' does not use them) you may get an
+error message (and incorrect code).  The AT&T 80386 assembler tries to
+get around this problem by expanding `jcxz foo' to
+
+              jcxz cx_zero
+              jmp cx_nonzero
+     cx_zero: jmp foo
+     cx_nonzero:
+
+
+File: as.info,  Node: i386-Float,  Next: i386-SIMD,  Prev: i386-Jumps,  Up: i386-Dependent
+
+8.11.8 Floating Point
+---------------------
+
+All 80387 floating point types except packed BCD are supported.  (BCD
+support may be added without much difficulty).  These data types are
+16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit),
+and extended (80-bit) precision floating point.  Each supported type
+has an instruction mnemonic suffix and a constructor associated with
+it.  Instruction mnemonic suffixes specify the operand's data type.
+Constructors build these data types into memory.
+
+   * Floating point constructors are `.float' or `.single', `.double',
+     and `.tfloat' for 32-, 64-, and 80-bit formats.  These correspond
+     to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for
+     80-bit (ten byte) real.  The 80387 only supports this format via
+     the `fldt' (load 80-bit real to stack top) and `fstpt' (store
+     80-bit real and pop stack) instructions.
+
+   * Integer constructors are `.word', `.long' or `.int', and `.quad'
+     for the 16-, 32-, and 64-bit integer formats.  The corresponding
+     instruction mnemonic suffixes are `s' (single), `l' (long), and
+     `q' (quad).  As with the 80-bit real format, the 64-bit `q' format
+     is only present in the `fildq' (load quad integer to stack top)
+     and `fistpq' (store quad integer and pop stack) instructions.
+
+   Register to register operations should not use instruction mnemonic
+suffixes.  `fstl %st, %st(1)' will give a warning, and be assembled as
+if you wrote `fst %st, %st(1)', since all register to register
+operations use 80-bit floating point operands. (Contrast this with
+`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating
+point format, then stores the result in the 4 byte location `mem')
+
+
+File: as.info,  Node: i386-SIMD,  Next: i386-16bit,  Prev: i386-Float,  Up: i386-Dependent
+
+8.11.9 Intel's MMX and AMD's 3DNow! SIMD Operations
+---------------------------------------------------
+
+`as' supports Intel's MMX instruction set (SIMD instructions for
+integer data), available on Intel's Pentium MMX processors and Pentium
+II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and
+probably others.  It also supports AMD's 3DNow!  instruction set (SIMD
+instructions for 32-bit floating point data) available on AMD's K6-2
+processor and possibly others in the future.
+
+   Currently, `as' does not support Intel's floating point SIMD, Katmai
+(KNI).
+
+   The eight 64-bit MMX operands, also used by 3DNow!, are called
+`%mm0', `%mm1', ... `%mm7'.  They contain eight 8-bit integers, four
+16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
+floating point values.  The MMX registers cannot be used at the same
+time as the floating point stack.
+
+   See Intel and AMD documentation, keeping in mind that the operand
+order in instructions is reversed from the Intel syntax.
+
+
+File: as.info,  Node: i386-16bit,  Next: i386-Arch,  Prev: i386-SIMD,  Up: i386-Dependent
+
+8.11.10 Writing 16-bit Code
+---------------------------
+
+While `as' normally writes only "pure" 32-bit i386 code or 64-bit
+x86-64 code depending on the default configuration, it also supports
+writing code to run in real mode or in 16-bit protected mode code
+segments.  To do this, put a `.code16' or `.code16gcc' directive before
+the assembly language instructions to be run in 16-bit mode.  You can
+switch `as' back to writing normal 32-bit code with the `.code32'
+directive.
+
+   `.code16gcc' provides experimental support for generating 16-bit
+code from gcc, and differs from `.code16' in that `call', `ret',
+`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf'
+instructions default to 32-bit size.  This is so that the stack pointer
+is manipulated in the same way over function calls, allowing access to
+function parameters at the same stack offsets as in 32-bit mode.
+`.code16gcc' also automatically adds address size prefixes where
+necessary to use the 32-bit addressing modes that gcc generates.
+
+   The code which `as' generates in 16-bit mode will not necessarily
+run on a 16-bit pre-80386 processor.  To write code that runs on such a
+processor, you must refrain from using _any_ 32-bit constructs which
+require `as' to output address or operand size prefixes.
+
+   Note that writing 16-bit code instructions by explicitly specifying a
+prefix or an instruction mnemonic suffix within a 32-bit code section
+generates different machine instructions than those generated for a
+16-bit code segment.  In a 32-bit code section, the following code
+generates the machine opcode bytes `66 6a 04', which pushes the value
+`4' onto the stack, decrementing `%esp' by 2.
+
+             pushw $4
+
+   The same code in a 16-bit code section would generate the machine
+opcode bytes `6a 04' (ie. without the operand size prefix), which is
+correct since the processor default operand size is assumed to be 16
+bits in a 16-bit code section.
+
+
+File: as.info,  Node: i386-Bugs,  Next: i386-Notes,  Prev: i386-Arch,  Up: i386-Dependent
+
+8.11.11 AT&T Syntax bugs
+------------------------
+
+The UnixWare assembler, and probably other AT&T derived ix86 Unix
+assemblers, generate floating point instructions with reversed source
+and destination registers in certain cases.  Unfortunately, gcc and
+possibly many other programs use this reversed syntax, so we're stuck
+with it.
+
+   For example
+
+             fsub %st,%st(3)
+   results in `%st(3)' being updated to `%st - %st(3)' rather than the
+expected `%st(3) - %st'.  This happens with all the non-commutative
+arithmetic floating point operations with two register operands where
+the source register is `%st' and the destination register is `%st(i)'.
+
+
+File: as.info,  Node: i386-Arch,  Next: i386-Bugs,  Prev: i386-16bit,  Up: i386-Dependent
+
+8.11.12 Specifying CPU Architecture
+-----------------------------------
+
+`as' may be told to assemble for a particular CPU (sub-)architecture
+with the `.arch CPU_TYPE' directive.  This directive enables a warning
+when gas detects an instruction that is not supported on the CPU
+specified.  The choices for CPU_TYPE are:
+
+`i8086'        `i186'         `i286'         `i386'
+`i486'         `i586'         `i686'         `pentium'
+`pentiumpro'   `pentiumii'    `pentiumiii'   `pentium4'
+`k6'           `athlon'                      
+               `sledgehammer'                
+`.mmx' `.sse'                                
+`.sse2'                                      
+`.sse3'                                      
+`.3dnow'                                     
+
+   Apart from the warning, there are only two other effects on `as'
+operation;  Firstly, if you specify a CPU other than `i486', then shift
+by one instructions such as `sarl $1, %eax' will automatically use a
+two byte opcode sequence.  The larger three byte opcode sequence is
+used on the 486 (and when no architecture is specified) because it
+executes faster on the 486.  Note that you can explicitly request the
+two byte opcode by writing `sarl %eax'.  Secondly, if you specify
+`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte
+offset conditional jumps will be promoted when necessary to a two
+instruction sequence consisting of a conditional jump of the opposite
+sense around an unconditional jump to the target.
+
+   Following the CPU architecture (but not a sub-architecture, which
+are those starting with a dot), you may specify `jumps' or `nojumps' to
+control automatic promotion of conditional jumps. `jumps' is the
+default, and enables jump promotion;  All external jumps will be of the
+long variety, and file-local jumps will be promoted as necessary.
+(*note i386-Jumps::)  `nojumps' leaves external conditional jumps as
+byte offset jumps, and warns about file-local conditional jumps that
+`as' promotes.  Unconditional jumps are treated as for `jumps'.
+
+   For example
+
+      .arch i8086,nojumps
+
+
+File: as.info,  Node: i386-Notes,  Prev: i386-Bugs,  Up: i386-Dependent
+
+8.11.13 Notes
+-------------
+
+There is some trickery concerning the `mul' and `imul' instructions
+that deserves mention.  The 16-, 32-, 64- and 128-bit expanding
+multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul')
+can be output only in the one operand form.  Thus, `imul %ebx, %eax'
+does _not_ select the expanding multiply; the expanding multiply would
+clobber the `%edx' register, and this would confuse `gcc' output.  Use
+`imul %ebx' to get the 64-bit product in `%edx:%eax'.
+
+   We have added a two operand form of `imul' when the first operand is
+an immediate mode expression and the second operand is a register.
+This is just a shorthand, so that, multiplying `%eax' by 69, for
+example, can be done with `imul $69, %eax' rather than `imul $69, %eax,
+%eax'.
+
+
+File: as.info,  Node: i860-Dependent,  Next: i960-Dependent,  Prev: i386-Dependent,  Up: Machine Dependencies
+
+8.12 Intel i860 Dependent Features
+==================================
+
+* Menu:
+
+* Notes-i860::                  i860 Notes
+* Options-i860::                i860 Command-line Options
+* Directives-i860::             i860 Machine Directives
+* Opcodes for i860::            i860 Opcodes
+
+
+File: as.info,  Node: Notes-i860,  Next: Options-i860,  Up: i860-Dependent
+
+8.12.1 i860 Notes
+-----------------
+
+This is a fairly complete i860 assembler which is compatible with the
+UNIX System V/860 Release 4 assembler. However, it does not currently
+support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT').
+
+   Like the SVR4/860 assembler, the output object format is ELF32.
+Currently, this is the only supported object format. If there is
+sufficient interest, other formats such as COFF may be implemented.
+
+   Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter
+being the default.  One difference is that AT&T syntax requires the '%'
+prefix on register names while Intel syntax does not.  Another
+difference is in the specification of relocatable expressions.  The
+Intel syntax is `ha%expression' whereas the SVR4 syntax is
+`[expression]@ha' (and similarly for the "l" and "h" selectors).
+
+
+File: as.info,  Node: Options-i860,  Next: Directives-i860,  Prev: Notes-i860,  Up: i860-Dependent
+
+8.12.2 i860 Command-line Options
+--------------------------------
+
+8.12.2.1 SVR4 compatibility options
+...................................
+
+`-V'
+     Print assembler version.
+
+`-Qy'
+     Ignored.
+
+`-Qn'
+     Ignored.
+
+8.12.2.2 Other options
+......................
+
+`-EL'
+     Select little endian output (this is the default).
+
+`-EB'
+     Select big endian output. Note that the i860 always reads
+     instructions as little endian data, so this option only effects
+     data and not instructions.
+
+`-mwarn-expand'
+     Emit a warning message if any pseudo-instruction expansions
+     occurred.  For example, a `or' instruction with an immediate
+     larger than 16-bits will be expanded into two instructions. This
+     is a very undesirable feature to rely on, so this flag can help
+     detect any code where it happens. One use of it, for instance, has
+     been to find and eliminate any place where `gcc' may emit these
+     pseudo-instructions.
+
+`-mxp'
+     Enable support for the i860XP instructions and control registers.
+     By default, this option is disabled so that only the base
+     instruction set (i.e., i860XR) is supported.
+
+`-mintel-syntax'
+     The i860 assembler defaults to AT&T/SVR4 syntax.  This option
+     enables the Intel syntax.
+
+
+File: as.info,  Node: Directives-i860,  Next: Opcodes for i860,  Prev: Options-i860,  Up: i860-Dependent
+
+8.12.3 i860 Machine Directives
+------------------------------
+
+`.dual'
+     Enter dual instruction mode. While this directive is supported, the
+     preferred way to use dual instruction mode is to explicitly code
+     the dual bit with the `d.' prefix.
+
+`.enddual'
+     Exit dual instruction mode. While this directive is supported, the
+     preferred way to use dual instruction mode is to explicitly code
+     the dual bit with the `d.' prefix.
+
+`.atmp'
+     Change the temporary register used when expanding pseudo
+     operations. The default register is `r31'.
+
+   The `.dual', `.enddual', and `.atmp' directives are available only
+in the Intel syntax mode.
+
+   Both syntaxes allow for the standard `.align' directive.  However,
+the Intel syntax additionally allows keywords for the alignment
+parameter: "`.align type'", where `type' is one of `.short', `.long',
+`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4,
+and 8, respectively.
+
+
+File: as.info,  Node: Opcodes for i860,  Prev: Directives-i860,  Up: i860-Dependent
+
+8.12.4 i860 Opcodes
+-------------------
+
+All of the Intel i860XR and i860XP machine instructions are supported.
+Please see either _i860 Microprocessor Programmer's Reference Manual_
+or _i860 Microprocessor Architecture_ for more information.
+
+8.12.4.1 Other instruction support (pseudo-instructions)
+........................................................
+
+For compatibility with some other i860 assemblers, a number of
+pseudo-instructions are supported. While these are supported, they are
+a very undesirable feature that should be avoided - in particular, when
+they result in an expansion to multiple actual i860 instructions. Below
+are the pseudo-instructions that result in expansions.
+   * Load large immediate into general register:
+
+     The pseudo-instruction `mov imm,%rn' (where the immediate does not
+     fit within a signed 16-bit field) will be expanded into:
+          orh large_imm@h,%r0,%rn
+          or large_imm@l,%rn,%rn
+
+   * Load/store with relocatable address expression:
+
+     For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will
+     be expanded into:
+          orh addr_exp@ha,%rx,%r31
+          ld.l addr_exp@l(%r31),%rn
+
+     The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x,
+     fst.x', and `pst.x' as well.
+
+   * Signed large immediate with add/subtract:
+
+     If any of the arithmetic operations `adds, addu, subs, subu' are
+     used with an immediate larger than 16-bits (signed), then they
+     will be expanded.  For instance, the pseudo-instruction `adds
+     large_imm,%rx,%rn' expands to:
+          orh large_imm@h,%r0,%r31
+          or large_imm@l,%r31,%r31
+          adds %r31,%rx,%rn
+
+   * Unsigned large immediate with logical operations:
+
+     Logical operations (`or, andnot, or, xor') also result in
+     expansions.  The pseudo-instruction `or large_imm,%rx,%rn' results
+     in:
+          orh large_imm@h,%rx,%r31
+          or large_imm@l,%r31,%rn
+
+     Similarly for the others, except for `and' which expands to:
+          andnot (-1 - large_imm)@h,%rx,%r31
+          andnot (-1 - large_imm)@l,%r31,%rn
+
+
+File: as.info,  Node: i960-Dependent,  Next: IA-64-Dependent,  Prev: i860-Dependent,  Up: Machine Dependencies
+
+8.13 Intel 80960 Dependent Features
+===================================
+
+* Menu:
+
+* Options-i960::                i960 Command-line Options
+* Floating Point-i960::         Floating Point
+* Directives-i960::             i960 Machine Directives
+* Opcodes for i960::            i960 Opcodes
+
+
+File: as.info,  Node: Options-i960,  Next: Floating Point-i960,  Up: i960-Dependent
+
+8.13.1 i960 Command-line Options
+--------------------------------
+
+`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC'
+     Select the 80960 architecture.  Instructions or features not
+     supported by the selected architecture cause fatal errors.
+
+     `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'.
+     Synonyms are provided for compatibility with other tools.
+
+     If you do not specify any of these options, `as' generates code
+     for any instruction or feature that is supported by _some_ version
+     of the 960 (even if this means mixing architectures!).  In
+     principle, `as' attempts to deduce the minimal sufficient
+     processor type if none is specified; depending on the object code
+     format, the processor type may be recorded in the object file.  If
+     it is critical that the `as' output match a specific architecture,
+     specify that architecture explicitly.
+
+`-b'
+     Add code to collect information about conditional branches taken,
+     for later optimization using branch prediction bits.  (The
+     conditional branch instructions have branch prediction bits in the
+     CA, CB, and CC architectures.)  If BR represents a conditional
+     branch instruction, the following represents the code generated by
+     the assembler when `-b' is specified:
+
+                  call    INCREMENT ROUTINE
+                  .word   0       # pre-counter
+          Label:  BR
+                  call    INCREMENT ROUTINE
+                  .word   0       # post-counter
+
+     The counter following a branch records the number of times that
+     branch was _not_ taken; the differenc between the two counters is
+     the number of times the branch _was_ taken.
+
+     A table of every such `Label' is also generated, so that the
+     external postprocessor `gbr960' (supplied by Intel) can locate all
+     the counters.  This table is always labeled `__BRANCH_TABLE__';
+     this is a local symbol to permit collecting statistics for many
+     separate object files.  The table is word aligned, and begins with
+     a two-word header.  The first word, initialized to 0, is used in
+     maintaining linked lists of branch tables.  The second word is a
+     count of the number of entries in the table, which follow
+     immediately: each is a word, pointing to one of the labels
+     illustrated above.
+
+           +------------+------------+------------+ ... +------------+
+           |            |            |            |     |            |
+           |  *NEXT     |  COUNT: N  | *BRLAB 1   |     | *BRLAB N   |
+           |            |            |            |     |            |
+           +------------+------------+------------+ ... +------------+
+
+                         __BRANCH_TABLE__ layout
+
+     The first word of the header is used to locate multiple branch
+     tables, since each object file may contain one. Normally the links
+     are maintained with a call to an initialization routine, placed at
+     the beginning of each function in the file.  The GNU C compiler
+     generates these calls automatically when you give it a `-b' option.
+     For further details, see the documentation of `gbr960'.
+
+`-no-relax'
+     Normally, Compare-and-Branch instructions with targets that require
+     displacements greater than 13 bits (or that have external targets)
+     are replaced with the corresponding compare (or `chkbit') and
+     branch instructions.  You can use the `-no-relax' option to
+     specify that `as' should generate errors instead, if the target
+     displacement is larger than 13 bits.
+
+     This option does not affect the Compare-and-Jump instructions; the
+     code emitted for them is _always_ adjusted when necessary
+     (depending on displacement size), regardless of whether you use
+     `-no-relax'.
+
+
+File: as.info,  Node: Floating Point-i960,  Next: Directives-i960,  Prev: Options-i960,  Up: i960-Dependent
+
+8.13.2 Floating Point
+---------------------
+
+`as' generates IEEE floating-point numbers for the directives `.float',
+`.double', `.extended', and `.single'.
+
+
+File: as.info,  Node: Directives-i960,  Next: Opcodes for i960,  Prev: Floating Point-i960,  Up: i960-Dependent
+
+8.13.3 i960 Machine Directives
+------------------------------
+
+`.bss SYMBOL, LENGTH, ALIGN'
+     Reserve LENGTH bytes in the bss section for a local SYMBOL,
+     aligned to the power of two specified by ALIGN.  LENGTH and ALIGN
+     must be positive absolute expressions.  This directive differs
+     from `.lcomm' only in that it permits you to specify an alignment.
+     *Note `.lcomm': Lcomm.
+
+`.extended FLONUMS'
+     `.extended' expects zero or more flonums, separated by commas; for
+     each flonum, `.extended' emits an IEEE extended-format (80-bit)
+     floating-point number.
+
+`.leafproc CALL-LAB, BAL-LAB'
+     You can use the `.leafproc' directive in conjunction with the
+     optimized `callj' instruction to enable faster calls of leaf
+     procedures.  If a procedure is known to call no other procedures,
+     you may define an entry point that skips procedure prolog code
+     (and that does not depend on system-supplied saved context), and
+     declare it as the BAL-LAB using `.leafproc'.  If the procedure
+     also has an entry point that goes through the normal prolog, you
+     can specify that entry point as CALL-LAB.
+
+     A `.leafproc' declaration is meant for use in conjunction with the
+     optimized call instruction `callj'; the directive records the data
+     needed later to choose between converting the `callj' into a `bal'
+     or a `call'.
+
+     CALL-LAB is optional; if only one argument is present, or if the
+     two arguments are identical, the single argument is assumed to be
+     the `bal' entry point.
+
+`.sysproc NAME, INDEX'
+     The `.sysproc' directive defines a name for a system procedure.
+     After you define it using `.sysproc', you can use NAME to refer to
+     the system procedure identified by INDEX when calling procedures
+     with the optimized call instruction `callj'.
+
+     Both arguments are required; INDEX must be between 0 and 31
+     (inclusive).
+
+
+File: as.info,  Node: Opcodes for i960,  Prev: Directives-i960,  Up: i960-Dependent
+
+8.13.4 i960 Opcodes
+-------------------
+
+All Intel 960 machine instructions are supported; *note i960
+Command-line Options: Options-i960. for a discussion of selecting the
+instruction subset for a particular 960 architecture.
+
+   Some opcodes are processed beyond simply emitting a single
+corresponding instruction: `callj', and Compare-and-Branch or
+Compare-and-Jump instructions with target displacements larger than 13
+bits.
+
+* Menu:
+
+* callj-i960::                  `callj'
+* Compare-and-branch-i960::     Compare-and-Branch
+
+
+File: as.info,  Node: callj-i960,  Next: Compare-and-branch-i960,  Up: Opcodes for i960
+
+8.13.4.1 `callj'
+................
+
+You can write `callj' to have the assembler or the linker determine the
+most appropriate form of subroutine call: `call', `bal', or `calls'.
+If the assembly source contains enough information--a `.leafproc' or
+`.sysproc' directive defining the operand--then `as' translates the
+`callj'; if not, it simply emits the `callj', leaving it for the linker
+to resolve.
+
+
+File: as.info,  Node: Compare-and-branch-i960,  Prev: callj-i960,  Up: Opcodes for i960
+
+8.13.4.2 Compare-and-Branch
+...........................
+
+The 960 architectures provide combined Compare-and-Branch instructions
+that permit you to store the branch target in the lower 13 bits of the
+instruction word itself.  However, if you specify a branch target far
+enough away that its address won't fit in 13 bits, the assembler can
+either issue an error, or convert your Compare-and-Branch instruction
+into separate instructions to do the compare and the branch.
+
+   Whether `as' gives an error or expands the instruction depends on
+two choices you can make: whether you use the `-no-relax' option, and
+whether you use a "Compare and Branch" instruction or a "Compare and
+Jump" instruction.  The "Jump" instructions are _always_ expanded if
+necessary; the "Branch" instructions are expanded when necessary
+_unless_ you specify `-no-relax'--in which case `as' gives an error
+instead.
+
+   These are the Compare-and-Branch instructions, their "Jump" variants,
+and the instruction pairs they may expand into:
+
+             Compare and
+          Branch      Jump       Expanded to
+          ------    ------       ------------
+             bbc                 chkbit; bno
+             bbs                 chkbit; bo
+          cmpibe    cmpije       cmpi; be
+          cmpibg    cmpijg       cmpi; bg
+         cmpibge   cmpijge       cmpi; bge
+          cmpibl    cmpijl       cmpi; bl
+         cmpible   cmpijle       cmpi; ble
+         cmpibno   cmpijno       cmpi; bno
+         cmpibne   cmpijne       cmpi; bne
+          cmpibo    cmpijo       cmpi; bo
+          cmpobe    cmpoje       cmpo; be
+          cmpobg    cmpojg       cmpo; bg
+         cmpobge   cmpojge       cmpo; bge
+          cmpobl    cmpojl       cmpo; bl
+         cmpoble   cmpojle       cmpo; ble
+         cmpobne   cmpojne       cmpo; bne
+
+
+File: as.info,  Node: IA-64-Dependent,  Next: IP2K-Dependent,  Prev: i960-Dependent,  Up: Machine Dependencies
+
+8.14 IA-64 Dependent Features
+=============================
+
+* Menu:
+
+* IA-64 Options::              Options
+* IA-64 Syntax::               Syntax
+* IA-64 Opcodes::              Opcodes
+
+
+File: as.info,  Node: IA-64 Options,  Next: IA-64 Syntax,  Up: IA-64-Dependent
+
+8.14.1 Options
+--------------
+
+`-mconstant-gp'
+     This option instructs the assembler to mark the resulting object
+     file as using the "constant GP" model.  With this model, it is
+     assumed that the entire program uses a single global pointer (GP)
+     value.  Note that this option does not in any fashion affect the
+     machine code emitted by the assembler.  All it does is turn on the
+     EF_IA_64_CONS_GP flag in the ELF file header.
+
+`-mauto-pic'
+     This option instructs the assembler to mark the resulting object
+     file as using the "constant GP without function descriptor" data
+     model.  This model is like the "constant GP" model, except that it
+     additionally does away with function descriptors.  What this means
+     is that the address of a function refers directly to the
+     function's code entry-point.  Normally, such an address would
+     refer to a function descriptor, which contains both the code
+     entry-point and the GP-value needed by the function.  Note that
+     this option does not in any fashion affect the machine code
+     emitted by the assembler.  All it does is turn on the
+     EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header.
+
+`-milp32'
+
+`-milp64'
+
+`-mlp64'
+
+`-mp64'
+     These options select the data model.  The assembler defaults to
+     `-mlp64' (LP64 data model).
+
+`-mle'
+
+`-mbe'
+     These options select the byte order.  The `-mle' option selects
+     little-endian byte order (default) and `-mbe' selects big-endian
+     byte order.  Note that IA-64 machine code always uses
+     little-endian byte order.
+
+`-mtune=itanium1'
+
+`-mtune=itanium2'
+     Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default
+     is ITANIUM2.
+
+`-munwind-check=warning'
+
+`-munwind-check=error'
+     These options control what the assembler will do when performing
+     consistency checks on unwind directives.  `-munwind-check=warning'
+     will make the assembler issue a warning when an unwind directive
+     check fails.  This is the default.  `-munwind-check=error' will
+     make the assembler issue an error when an unwind directive check
+     fails.
+
+`-mhint.b=ok'
+
+`-mhint.b=warning'
+
+`-mhint.b=error'
+     These options control what the assembler will do when the `hint.b'
+     instruction is used.  `-mhint.b=ok' will make the assembler accept
+     `hint.b'.  `-mint.b=warning' will make the assembler issue a
+     warning when `hint.b' is used.  `-mhint.b=error' will make the
+     assembler treat `hint.b' as an error, which is the default.
+
+`-x'
+
+`-xexplicit'
+     These options turn on dependency violation checking.
+
+`-xauto'
+     This option instructs the assembler to automatically insert stop
+     bits where necessary to remove dependency violations.  This is the
+     default mode.
+
+`-xnone'
+     This option turns off dependency violation checking.
+
+`-xdebug'
+     This turns on debug output intended to help tracking down bugs in
+     the dependency violation checker.
+
+`-xdebugn'
+     This is a shortcut for -xnone -xdebug.
+
+`-xdebugx'
+     This is a shortcut for -xexplicit -xdebug.
+
+
+
+File: as.info,  Node: IA-64 Syntax,  Next: IA-64 Opcodes,  Prev: IA-64 Options,  Up: IA-64-Dependent
+
+8.14.2 Syntax
+-------------
+
+The assembler syntax closely follows the IA-64 Assembly Language
+Reference Guide.
+
+* Menu:
+
+* IA-64-Chars::                Special Characters
+* IA-64-Regs::                 Register Names
+* IA-64-Bits::                 Bit Names
+
+
+File: as.info,  Node: IA-64-Chars,  Next: IA-64-Regs,  Up: IA-64 Syntax
+
+8.14.2.1 Special Characters
+...........................
+
+`//' is the line comment token.
+
+   `;' can be used instead of a newline to separate statements.
+
+
+File: as.info,  Node: IA-64-Regs,  Next: IA-64-Bits,  Prev: IA-64-Chars,  Up: IA-64 Syntax
+
+8.14.2.2 Register Names
+.......................
+
+The 128 integer registers are referred to as `rN'.  The 128
+floating-point registers are referred to as `fN'.  The 128 application
+registers are referred to as `arN'.  The 128 control registers are
+referred to as `crN'.  The 64 one-bit predicate registers are referred
+to as `pN'.  The 8 branch registers are referred to as `bN'.  In
+addition, the assembler defines a number of aliases: `gp' (`r1'), `sp'
+(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'),
+`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N').
+
+   For convenience, the assembler also defines aliases for all named
+application and control registers.  For example, `ar.bsp' refers to the
+register backing store pointer (`ar17').  Similarly, `cr.eoi' refers to
+the end-of-interrupt register (`cr67').
+
+
+File: as.info,  Node: IA-64-Bits,  Prev: IA-64-Regs,  Up: IA-64 Syntax
+
+8.14.2.3 IA-64 Processor-Status-Register (PSR) Bit Names
+........................................................
+
+The assembler defines bit masks for each of the bits in the IA-64
+processor status register.  For example, `psr.ic' corresponds to a
+value of 0x2000.  These masks are primarily intended for use with the
+`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere
+else where an integer constant is expected.
+
+
+File: as.info,  Node: IA-64 Opcodes,  Prev: IA-64 Syntax,  Up: IA-64-Dependent
+
+8.14.3 Opcodes
+--------------
+
+For detailed information on the IA-64 machine instruction set, see the
+IA-64 Architecture Handbook
+(http://developer.intel.com/design/itanium/arch_spec.htm).
+
+
+File: as.info,  Node: IP2K-Dependent,  Next: M32C-Dependent,  Prev: IA-64-Dependent,  Up: Machine Dependencies
+
+8.15 IP2K Dependent Features
+============================
+
+* Menu:
+
+* IP2K-Opts::                   IP2K Options
+
+
+File: as.info,  Node: IP2K-Opts,  Up: IP2K-Dependent
+
+8.15.1 IP2K Options
+-------------------
+
+The Ubicom IP2K version of `as' has a few machine dependent options:
+
+`-mip2022ext'
+     `as' can assemble the extended IP2022 instructions, but it will
+     only do so if this is specifically allowed via this command line
+     option.
+
+`-mip2022'
+     This option restores the assembler's default behaviour of not
+     permitting the extended IP2022 instructions to be assembled.
+
+
+
+File: as.info,  Node: M32C-Dependent,  Next: M32R-Dependent,  Prev: IP2K-Dependent,  Up: Machine Dependencies
+
+8.16 M32C Dependent Features
+============================
+
+   `as' can assemble code for several different members of the Renesas
+M32C family.  Normally the default is to assemble code for the M16C
+microprocessor.  The `-m32c' option may be used to change the default
+to the M32C microprocessor.
+
+* Menu:
+
+* M32C-Opts::                   M32C Options
+* M32C-Modifiers::              Symbolic Operand Modifiers
+
+
+File: as.info,  Node: M32C-Opts,  Next: M32C-Modifiers,  Up: M32C-Dependent
+
+8.16.1 M32C Options
+-------------------
+
+The Renesas M32C version of `as' has two machine-dependent options:
+
+`-m32c'
+     Assemble M32C instructions.
+
+`-m16c'
+     Assemble M16C instructions (default).
+
+
+
+File: as.info,  Node: M32C-Modifiers,  Prev: M32C-Opts,  Up: M32C-Dependent
+
+8.16.2 Symbolic Operand Modifiers
+---------------------------------
+
+The assembler supports several modifiers when using symbol addresses in
+M32C instruction operands.  The general syntax is the following:
+
+     %modifier(symbol)
+
+`%dsp8'
+`%dsp16'
+     These modifiers override the assembler's assumptions about how big
+     a symbol's address is.  Normally, when it sees an operand like
+     `sym[a0]' it assumes `sym' may require the widest displacement
+     field (16 bits for `-m16c', 24 bits for `-m32c').  These modifiers
+     tell it to assume the address will fit in an 8 or 16 bit
+     (respectively) unsigned displacement.  Note that, of course, if it
+     doesn't actually fit you will get linker errors.  Example:
+
+          mov.w %dsp8(sym)[a0],r1
+          mov.b #0,%dsp8(sym)[a0]
+
+`%hi8'
+     This modifier allows you to load bits 16 through 23 of a 24 bit
+     address into an 8 bit register.  This is useful with, for example,
+     the M16C `smovf' instruction, which expects a 20 bit address in
+     `r1h' and `a0'.  Example:
+
+          mov.b #%hi8(sym),r1h
+          mov.w #%lo16(sym),a0
+          smovf.b
+
+`%lo16'
+     Likewise, this modifier allows you to load bits 0 through 15 of a
+     24 bit address into a 16 bit register.
+
+`%hi16'
+     This modifier allows you to load bits 16 through 31 of a 32 bit
+     address into a 16 bit register.  While the M32C family only has 24
+     bits of address space, it does support addresses in pairs of 16 bit
+     registers (like `a1a0' for the `lde' instruction).  This modifier
+     is for loading the upper half in such cases.  Example:
+
+          mov.w #%hi16(sym),a1
+          mov.w #%lo16(sym),a0
+          ...
+          lde.w [a1a0],r1
+
+
+
+File: as.info,  Node: M32R-Dependent,  Next: M68K-Dependent,  Prev: M32C-Dependent,  Up: Machine Dependencies
+
+8.17 M32R Dependent Features
+============================
+
+* Menu:
+
+* M32R-Opts::                   M32R Options
+* M32R-Directives::             M32R Directives
+* M32R-Warnings::               M32R Warnings
+
+
+File: as.info,  Node: M32R-Opts,  Next: M32R-Directives,  Up: M32R-Dependent
+
+8.17.1 M32R Options
+-------------------
+
+The Renease M32R version of `as' has a few machine dependent options:
+
+`-m32rx'
+     `as' can assemble code for several different members of the
+     Renesas M32R family.  Normally the default is to assemble code for
+     the M32R microprocessor.  This option may be used to change the
+     default to the M32RX microprocessor, which adds some more
+     instructions to the basic M32R instruction set, and some
+     additional parameters to some of the original instructions.
+
+`-m32r2'
+     This option changes the target processor to the the M32R2
+     microprocessor.
+
+`-m32r'
+     This option can be used to restore the assembler's default
+     behaviour of assembling for the M32R microprocessor.  This can be
+     useful if the default has been changed by a previous command line
+     option.
+
+`-little'
+     This option tells the assembler to produce little-endian code and
+     data.  The default is dependent upon how the toolchain was
+     configured.
+
+`-EL'
+     This is a synonum for _-little_.
+
+`-big'
+     This option tells the assembler to produce big-endian code and
+     data.
+
+`-EB'
+     This is a synonum for _-big_.
+
+`-KPIC'
+     This option specifies that the output of the assembler should be
+     marked as position-independent code (PIC).
+
+`-parallel'
+     This option tells the assembler to attempts to combine two
+     sequential instructions into a single, parallel instruction, where
+     it is legal to do so.
+
+`-no-parallel'
+     This option disables a previously enabled _-parallel_ option.
+
+`-no-bitinst'
+     This option disables the support for the extended bit-field
+     instructions provided by the M32R2.  If this support needs to be
+     re-enabled the _-bitinst_ switch can be used to restore it.
+
+`-O'
+     This option tells the assembler to attempt to optimize the
+     instructions that it produces.  This includes filling delay slots
+     and converting sequential instructions into parallel ones.  This
+     option implies _-parallel_.
+
+`-warn-explicit-parallel-conflicts'
+     Instructs `as' to produce warning messages when questionable
+     parallel instructions are encountered.  This option is enabled by
+     default, but `gcc' disables it when it invokes `as' directly.
+     Questionable instructions are those whoes behaviour would be
+     different if they were executed sequentially.  For example the
+     code fragment `mv r1, r2 || mv r3, r1' produces a different result
+     from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3
+     and then r2 into r1, whereas the later moves r2 into r1 and r3.
+
+`-Wp'
+     This is a shorter synonym for the
+     _-warn-explicit-parallel-conflicts_ option.
+
+`-no-warn-explicit-parallel-conflicts'
+     Instructs `as' not to produce warning messages when questionable
+     parallel instructions are encountered.
+
+`-Wnp'
+     This is a shorter synonym for the
+     _-no-warn-explicit-parallel-conflicts_ option.
+
+`-ignore-parallel-conflicts'
+     This option tells the assembler's to stop checking parallel
+     instructions for contraint violations.  This ability is provided
+     for hardware vendors testing chip designs and should not be used
+     under normal circumstances.
+
+`-no-ignore-parallel-conflicts'
+     This option restores the assembler's default behaviour of checking
+     parallel instructions to detect constraint violations.
+
+`-Ip'
+     This is a shorter synonym for the _-ignore-parallel-conflicts_
+     option.
+
+`-nIp'
+     This is a shorter synonym for the _-no-ignore-parallel-conflicts_
+     option.
+
+`-warn-unmatched-high'
+     This option tells the assembler to produce a warning message if a
+     `.high' pseudo op is encountered without a mathcing `.low' pseudo
+     op.  The presence of such an unmatches pseudo op usually indicates
+     a programming error.
+
+`-no-warn-unmatched-high'
+     Disables a previously enabled _-warn-unmatched-high_ option.
+
+`-Wuh'
+     This is a shorter synonym for the _-warn-unmatched-high_ option.
+
+`-Wnuh'
+     This is a shorter synonym for the _-no-warn-unmatched-high_ option.
+
+
+
+File: as.info,  Node: M32R-Directives,  Next: M32R-Warnings,  Prev: M32R-Opts,  Up: M32R-Dependent
+
+8.17.2 M32R Directives
+----------------------
+
+The Renease M32R version of `as' has a few architecture specific
+directives:
+
+`low EXPRESSION'
+     The `low' directive computes the value of its expression and
+     places the lower 16-bits of the result into the immediate-field of
+     the instruction.  For example:
+
+             or3   r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678
+             add3, r0, r0, #low(fred)   ; compute r0 = r0 + low 16-bits of address of fred
+
+`high EXPRESSION'
+     The `high' directive computes the value of its expression and
+     places the upper 16-bits of the result into the immediate-field of
+     the instruction.  For example:
+
+             seth  r0, #high(0x12345678) ; compute r0 = 0x12340000
+             seth, r0, #high(fred)       ; compute r0 = upper 16-bits of address of fred
+
+`shigh EXPRESSION'
+     The `shigh' directive is very similar to the `high' directive.  It
+     also computes the value of its expression and places the upper
+     16-bits of the result into the immediate-field of the instruction.
+     The difference is that `shigh' also checks to see if the lower
+     16-bits could be interpreted as a signed number, and if so it
+     assumes that a borrow will occur from the upper-16 bits.  To
+     compensate for this the `shigh' directive pre-biases the upper 16
+     bit value by adding one to it.  For example:
+
+     For example:
+
+             seth  r0, #shigh(0x12345678) ; compute r0 = 0x12340000
+             seth  r0, #shigh(0x00008000) ; compute r0 = 0x00010000
+
+     In the second example the lower 16-bits are 0x8000.  If these are
+     treated as a signed value and sign extended to 32-bits then the
+     value becomes 0xffff8000.  If this value is then added to
+     0x00010000 then the result is 0x00008000.
+
+     This behaviour is to allow for the different semantics of the
+     `or3' and `add3' instructions.  The `or3' instruction treats its
+     16-bit immediate argument as unsigned whereas the `add3' treats
+     its 16-bit immediate as a signed value.  So for example:
+
+             seth  r0, #shigh(0x00008000)
+             add3  r0, r0, #low(0x00008000)
+
+     Produces the correct result in r0, whereas:
+
+             seth  r0, #shigh(0x00008000)
+             or3   r0, r0, #low(0x00008000)
+
+     Stores 0xffff8000 into r0.
+
+     Note - the `shigh' directive does not know where in the assembly
+     source code the lower 16-bits of the value are going set, so it
+     cannot check to make sure that an `or3' instruction is being used
+     rather than an `add3' instruction.  It is up to the programmer to
+     make sure that correct directives are used.
+
+`.m32r'
+     The directive performs a similar thing as the _-m32r_ command line
+     option.  It tells the assembler to only accept M32R instructions
+     from now on.  An instructions from later M32R architectures are
+     refused.
+
+`.m32rx'
+     The directive performs a similar thing as the _-m32rx_ command
+     line option.  It tells the assembler to start accepting the extra
+     instructions in the M32RX ISA as well as the ordinary M32R ISA.
+
+`.m32r2'
+     The directive performs a similar thing as the _-m32r2_ command
+     line option.  It tells the assembler to start accepting the extra
+     instructions in the M32R2 ISA as well as the ordinary M32R ISA.
+
+`.little'
+     The directive performs a similar thing as the _-little_ command
+     line option.  It tells the assembler to start producing
+     little-endian code and data.  This option should be used with care
+     as producing mixed-endian binary files is frought with danger.
+
+`.big'
+     The directive performs a similar thing as the _-big_ command line
+     option.  It tells the assembler to start producing big-endian code
+     and data.  This option should be used with care as producing
+     mixed-endian binary files is frought with danger.
+
+
+
+File: as.info,  Node: M32R-Warnings,  Prev: M32R-Directives,  Up: M32R-Dependent
+
+8.17.3 M32R Warnings
+--------------------
+
+There are several warning and error messages that can be produced by
+`as' which are specific to the M32R:
+
+`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?'
+     This message is only produced if warnings for explicit parallel
+     conflicts have been enabled.  It indicates that the assembler has
+     encountered a parallel instruction in which the destination
+     register of the left hand instruction is used as an input register
+     in the right hand instruction.  For example in this code fragment
+     `mv r1, r2 || neg r3, r1' register r1 is the destination of the
+     move instruction and the input to the neg instruction.
+
+`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?'
+     This message is only produced if warnings for explicit parallel
+     conflicts have been enabled.  It indicates that the assembler has
+     encountered a parallel instruction in which the destination
+     register of the right hand instruction is used as an input
+     register in the left hand instruction.  For example in this code
+     fragment `mv r1, r2 || neg r2, r3' register r2 is the destination
+     of the neg instruction and the input to the move instruction.
+
+`instruction `...' is for the M32RX only'
+     This message is produced when the assembler encounters an
+     instruction which is only supported by the M32Rx processor, and
+     the `-m32rx' command line flag has not been specified to allow
+     assembly of such instructions.
+
+`unknown instruction `...''
+     This message is produced when the assembler encounters an
+     instruction which it does not recognise.
+
+`only the NOP instruction can be issued in parallel on the m32r'
+     This message is produced when the assembler encounters a parallel
+     instruction which does not involve a NOP instruction and the
+     `-m32rx' command line flag has not been specified.  Only the M32Rx
+     processor is able to execute two instructions in parallel.
+
+`instruction `...' cannot be executed in parallel.'
+     This message is produced when the assembler encounters a parallel
+     instruction which is made up of one or two instructions which
+     cannot be executed in parallel.
+
+`Instructions share the same execution pipeline'
+     This message is produced when the assembler encounters a parallel
+     instruction whoes components both use the same execution pipeline.
+
+`Instructions write to the same destination register.'
+     This message is produced when the assembler encounters a parallel
+     instruction where both components attempt to modify the same
+     register.  For example these code fragments will produce this
+     message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2,
+     @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx
+     r3, r4' (Both write to the condition bit)
+
+
+
+File: as.info,  Node: M68K-Dependent,  Next: M68HC11-Dependent,  Prev: M32R-Dependent,  Up: Machine Dependencies
+
+8.18 M680x0 Dependent Features
+==============================
+
+* Menu:
+
+* M68K-Opts::                   M680x0 Options
+* M68K-Syntax::                 Syntax
+* M68K-Moto-Syntax::            Motorola Syntax
+* M68K-Float::                  Floating Point
+* M68K-Directives::             680x0 Machine Directives
+* M68K-opcodes::                Opcodes
+
+
+File: as.info,  Node: M68K-Opts,  Next: M68K-Syntax,  Up: M68K-Dependent
+
+8.18.1 M680x0 Options
+---------------------
+
+The Motorola 680x0 version of `as' has a few machine dependent options:
+
+`-march=ARCHITECTURE'
+     This option specifies a target architecture.  The following
+     architectures are recognized: `68000', `68010', `68020', `68030',
+     `68040', `68060', `cpu32', `isaa', `isaaplus', `isab' and `cfv4e'.
+
+`-mcpu=CPU'
+     This option specifies a target cpu.  When used in conjunction with
+     the `-march' option, the cpu must be within the specified
+     architecture.  Also, the generic features of the architecture are
+     used for instruction generation, rather than those of the specific
+     chip.
+
+`-m[no-]68851'
+
+`-m[no-]68881'
+
+`-m[no-]div'
+
+`-m[no-]usp'
+
+`-m[no-]float'
+
+`-m[no-]mac'
+
+`-m[no-]emac'
+     Enable or disable various architecture specific features.  If a
+     chip or architecture by default supports an option (for instance
+     `-march=isaaplus' includes the `-mdiv' option), explicitly
+     disabling the option will override the default.
+
+`-l'
+     You can use the `-l' option to shorten the size of references to
+     undefined symbols.  If you do not use the `-l' option, references
+     to undefined symbols are wide enough for a full `long' (32 bits).
+     (Since `as' cannot know where these symbols end up, `as' can only
+     allocate space for the linker to fill in later.  Since `as' does
+     not know how far away these symbols are, it allocates as much
+     space as it can.)  If you use this option, the references are only
+     one word wide (16 bits).  This may be useful if you want the
+     object file to be as small as possible, and you know that the
+     relevant symbols are always less than 17 bits away.
+
+`--register-prefix-optional'
+     For some configurations, especially those where the compiler
+     normally does not prepend an underscore to the names of user
+     variables, the assembler requires a `%' before any use of a
+     register name.  This is intended to let the assembler distinguish
+     between C variables and functions named `a0' through `a7', and so
+     on.  The `%' is always accepted, but is not required for certain
+     configurations, notably `sun3'.  The `--register-prefix-optional'
+     option may be used to permit omitting the `%' even for
+     configurations for which it is normally required.  If this is
+     done, it will generally be impossible to refer to C variables and
+     functions with the same names as register names.
+
+`--bitwise-or'
+     Normally the character `|' is treated as a comment character, which
+     means that it can not be used in expressions.  The `--bitwise-or'
+     option turns `|' into a normal character.  In this mode, you must
+     either use C style comments, or start comments with a `#' character
+     at the beginning of a line.
+
+`--base-size-default-16  --base-size-default-32'
+     If you use an addressing mode with a base register without
+     specifying the size, `as' will normally use the full 32 bit value.
+     For example, the addressing mode `%a0@(%d0)' is equivalent to
+     `%a0@(%d0:l)'.  You may use the `--base-size-default-16' option to
+     tell `as' to default to using the 16 bit value.  In this case,
+     `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'.  You may use the
+     `--base-size-default-32' option to restore the default behaviour.
+
+`--disp-size-default-16  --disp-size-default-32'
+     If you use an addressing mode with a displacement, and the value
+     of the displacement is not known, `as' will normally assume that
+     the value is 32 bits.  For example, if the symbol `disp' has not
+     been defined, `as' will assemble the addressing mode
+     `%a0@(disp,%d0)' as though `disp' is a 32 bit value.  You may use
+     the `--disp-size-default-16' option to tell `as' to instead assume
+     that the displacement is 16 bits.  In this case, `as' will
+     assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value.  You
+     may use the `--disp-size-default-32' option to restore the default
+     behaviour.
+
+`--pcrel'
+     Always keep branches PC-relative.  In the M680x0 architecture all
+     branches are defined as PC-relative.  However, on some processors
+     they are limited to word displacements maximum.  When `as' needs a
+     long branch that is not available, it normally emits an absolute
+     jump instead.  This option disables this substitution.  When this
+     option is given and no long branches are available, only word
+     branches will be emitted.  An error message will be generated if a
+     word branch cannot reach its target.  This option has no effect on
+     68020 and other processors that have long branches.  *note Branch
+     Improvement: M68K-Branch.
+
+`-m68000'
+     `as' can assemble code for several different members of the
+     Motorola 680x0 family.  The default depends upon how `as' was
+     configured when it was built; normally, the default is to assemble
+     code for the 68020 microprocessor.  The following options may be
+     used to change the default.  These options control which
+     instructions and addressing modes are permitted.  The members of
+     the 680x0 family are very similar.  For detailed information about
+     the differences, see the Motorola manuals.
+
+    `-m68000'
+    `-m68ec000'
+    `-m68hc000'
+    `-m68hc001'
+    `-m68008'
+    `-m68302'
+    `-m68306'
+    `-m68307'
+    `-m68322'
+    `-m68356'
+          Assemble for the 68000. `-m68008', `-m68302', and so on are
+          synonyms for `-m68000', since the chips are the same from the
+          point of view of the assembler.
+
+    `-m68010'
+          Assemble for the 68010.
+
+    `-m68020'
+    `-m68ec020'
+          Assemble for the 68020.  This is normally the default.
+
+    `-m68030'
+    `-m68ec030'
+          Assemble for the 68030.
+
+    `-m68040'
+    `-m68ec040'
+          Assemble for the 68040.
+
+    `-m68060'
+    `-m68ec060'
+          Assemble for the 68060.
+
+    `-mcpu32'
+    `-m68330'
+    `-m68331'
+    `-m68332'
+    `-m68333'
+    `-m68334'
+    `-m68336'
+    `-m68340'
+    `-m68341'
+    `-m68349'
+    `-m68360'
+          Assemble for the CPU32 family of chips.
+
+    `-m5200'
+
+    `-m5202'
+
+    `-m5204'
+
+    `-m5206'
+
+    `-m5206e'
+
+    `-m521x'
+
+    `-m5249'
+
+    `-m528x'
+
+    `-m5307'
+
+    `-m5407'
+
+    `-m547x'
+
+    `-m548x'
+
+    `-mcfv4'
+
+    `-mcfv4e'
+          Assemble for the ColdFire family of chips.
+
+    `-m68881'
+    `-m68882'
+          Assemble 68881 floating point instructions.  This is the
+          default for the 68020, 68030, and the CPU32.  The 68040 and
+          68060 always support floating point instructions.
+
+    `-mno-68881'
+          Do not assemble 68881 floating point instructions.  This is
+          the default for 68000 and the 68010.  The 68040 and 68060
+          always support floating point instructions, even if this
+          option is used.
+
+    `-m68851'
+          Assemble 68851 MMU instructions.  This is the default for the
+          68020, 68030, and 68060.  The 68040 accepts a somewhat
+          different set of MMU instructions; `-m68851' and `-m68040'
+          should not be used together.
+
+    `-mno-68851'
+          Do not assemble 68851 MMU instructions.  This is the default
+          for the 68000, 68010, and the CPU32.  The 68040 accepts a
+          somewhat different set of MMU instructions.
+
+
+File: as.info,  Node: M68K-Syntax,  Next: M68K-Moto-Syntax,  Prev: M68K-Opts,  Up: M68K-Dependent
+
+8.18.2 Syntax
+-------------
+
+This syntax for the Motorola 680x0 was developed at MIT.
+
+   The 680x0 version of `as' uses instructions names and syntax
+compatible with the Sun assembler.  Intervening periods are ignored;
+for example, `movl' is equivalent to `mov.l'.
+
+   In the following table APC stands for any of the address registers
+(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
+relative to the program counter (`%zpc'), a suppressed address register
+(`%za0' through `%za7'), or it may be omitted entirely.  The use of
+SIZE means one of `w' or `l', and it may be omitted, along with the
+leading colon, unless a scale is also specified.  The use of SCALE
+means one of `1', `2', `4', or `8', and it may always be omitted along
+with the leading colon.
+
+   The following addressing modes are understood:
+"Immediate"
+     `#NUMBER'
+
+"Data Register"
+     `%d0' through `%d7'
+
+"Address Register"
+     `%a0' through `%a7'
+     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
+     also known as `%fp', the Frame Pointer.
+
+"Address Register Indirect"
+     `%a0@' through `%a7@'
+
+"Address Register Postincrement"
+     `%a0@+' through `%a7@+'
+
+"Address Register Predecrement"
+     `%a0@-' through `%a7@-'
+
+"Indirect Plus Offset"
+     `APC@(NUMBER)'
+
+"Index"
+     `APC@(NUMBER,REGISTER:SIZE:SCALE)'
+
+     The NUMBER may be omitted.
+
+"Postindex"
+     `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)'
+
+     The ONUMBER or the REGISTER, but not both, may be omitted.
+
+"Preindex"
+     `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)'
+
+     The NUMBER may be omitted.  Omitting the REGISTER produces the
+     Postindex addressing mode.
+
+"Absolute"
+     `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.
+
+
+File: as.info,  Node: M68K-Moto-Syntax,  Next: M68K-Float,  Prev: M68K-Syntax,  Up: M68K-Dependent
+
+8.18.3 Motorola Syntax
+----------------------
+
+The standard Motorola syntax for this chip differs from the syntax
+already discussed (*note Syntax: M68K-Syntax.).  `as' can accept
+Motorola syntax for operands, even if MIT syntax is used for other
+operands in the same instruction.  The two kinds of syntax are fully
+compatible.
+
+   In the following table APC stands for any of the address registers
+(`%a0' through `%a7'), the program counter (`%pc'), the zero-address
+relative to the program counter (`%zpc'), or a suppressed address
+register (`%za0' through `%za7').  The use of SIZE means one of `w' or
+`l', and it may always be omitted along with the leading dot.  The use
+of SCALE means one of `1', `2', `4', or `8', and it may always be
+omitted along with the leading asterisk.
+
+   The following additional addressing modes are understood:
+
+"Address Register Indirect"
+     `(%a0)' through `(%a7)'
+     `%a7' is also known as `%sp', i.e. the Stack Pointer.  `%a6' is
+     also known as `%fp', the Frame Pointer.
+
+"Address Register Postincrement"
+     `(%a0)+' through `(%a7)+'
+
+"Address Register Predecrement"
+     `-(%a0)' through `-(%a7)'
+
+"Indirect Plus Offset"
+     `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'.
+
+     The NUMBER may also appear within the parentheses, as in
+     `(NUMBER,%A0)'.  When used with the PC, the NUMBER may be omitted
+     (with an address register, omitting the NUMBER produces Address
+     Register Indirect mode).
+
+"Index"
+     `NUMBER(APC,REGISTER.SIZE*SCALE)'
+
+     The NUMBER may be omitted, or it may appear within the
+     parentheses.  The APC may be omitted.  The REGISTER and the APC
+     may appear in either order.  If both APC and REGISTER are address
+     registers, and the SIZE and SCALE are omitted, then the first
+     register is taken as the base register, and the second as the
+     index register.
+
+"Postindex"
+     `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)'
+
+     The ONUMBER, or the REGISTER, or both, may be omitted.  Either the
+     NUMBER or the APC may be omitted, but not both.
+
+"Preindex"
+     `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)'
+
+     The NUMBER, or the APC, or the REGISTER, or any two of them, may
+     be omitted.  The ONUMBER may be omitted.  The REGISTER and the APC
+     may appear in either order.  If both APC and REGISTER are address
+     registers, and the SIZE and SCALE are omitted, then the first
+     register is taken as the base register, and the second as the
+     index register.
+
+
+File: as.info,  Node: M68K-Float,  Next: M68K-Directives,  Prev: M68K-Moto-Syntax,  Up: M68K-Dependent
+
+8.18.4 Floating Point
+---------------------
+
+Packed decimal (P) format floating literals are not supported.  Feel
+free to add the code!
+
+   The floating point formats generated by directives are these.
+
+`.float'
+     `Single' precision floating point constants.
+
+`.double'
+     `Double' precision floating point constants.
+
+`.extend'
+`.ldouble'
+     `Extended' precision (`long double') floating point constants.
+
+
+File: as.info,  Node: M68K-Directives,  Next: M68K-opcodes,  Prev: M68K-Float,  Up: M68K-Dependent
+
+8.18.5 680x0 Machine Directives
+-------------------------------
+
+In order to be compatible with the Sun assembler the 680x0 assembler
+understands the following directives.
+
+`.data1'
+     This directive is identical to a `.data 1' directive.
+
+`.data2'
+     This directive is identical to a `.data 2' directive.
+
+`.even'
+     This directive is a special case of the `.align' directive; it
+     aligns the output to an even byte boundary.
+
+`.skip'
+     This directive is identical to a `.space' directive.
+
+`.arch NAME'
+     Select the target architecture and extension features.  Valid
+     valuse for NAME are the same as for the `-march' command line
+     option.  This directive cannot be specified after any instructions
+     have been assembled.  If it is given multiple times, or in
+     conjuction with the `-march' option, all uses must be for the same
+     architecture and extension set.
+
+`.cpu NAME'
+     Select the target cpu.  Valid valuse for NAME are the same as for
+     the `-mcpu' command line option.  This directive cannot be
+     specified after any instructions have been assembled.  If it is
+     given multiple times, or in conjuction with the `-mopt' option,
+     all uses must be for the same cpu.
+
+
+
+File: as.info,  Node: M68K-opcodes,  Prev: M68K-Directives,  Up: M68K-Dependent
+
+8.18.6 Opcodes
+--------------
+
+* Menu:
+
+* M68K-Branch::                 Branch Improvement
+* M68K-Chars::                  Special Characters
+
+
+File: as.info,  Node: M68K-Branch,  Next: M68K-Chars,  Up: M68K-opcodes
+
+8.18.6.1 Branch Improvement
+...........................
+
+Certain pseudo opcodes are permitted for branch instructions.  They
+expand to the shortest branch instruction that reach the target.
+Generally these mnemonics are made by substituting `j' for `b' at the
+start of a Motorola mnemonic.
+
+   The following table summarizes the pseudo-operations.  A `*' flags
+cases that are more fully described after the table:
+
+               Displacement
+               +------------------------------------------------------------
+               |                68020           68000/10, not PC-relative OK
+     Pseudo-Op |BYTE    WORD    LONG            ABSOLUTE LONG JUMP    **
+               +------------------------------------------------------------
+          jbsr |bsrs    bsrw    bsrl            jsr
+           jra |bras    braw    bral            jmp
+     *     jXX |bXXs    bXXw    bXXl            bNXs;jmp
+     *    dbXX | N/A    dbXXw   dbXX;bras;bral  dbXX;bras;jmp
+          fjXX | N/A    fbXXw   fbXXl            N/A
+
+     XX: condition
+     NX: negative of condition XX
+                       `*'--see full description below
+         `**'--this expansion mode is disallowed by `--pcrel'
+
+`jbsr'
+`jra'
+     These are the simplest jump pseudo-operations; they always map to
+     one particular machine instruction, depending on the displacement
+     to the branch target.  This instruction will be a byte or word
+     branch is that is sufficient.  Otherwise, a long branch will be
+     emitted if available.  If no long branches are available and the
+     `--pcrel' option is not given, an absolute long jump will be
+     emitted instead.  If no long branches are available, the `--pcrel'
+     option is given, and a word branch cannot reach the target, an
+     error message is generated.
+
+     In addition to standard branch operands, `as' allows these
+     pseudo-operations to have all operands that are allowed for jsr
+     and jmp, substituting these instructions if the operand given is
+     not valid for a branch instruction.
+
+`jXX'
+     Here, `jXX' stands for an entire family of pseudo-operations,
+     where XX is a conditional branch or condition-code test.  The full
+     list of pseudo-ops in this family is:
+           jhi   jls   jcc   jcs   jne   jeq   jvc
+           jvs   jpl   jmi   jge   jlt   jgt   jle
+
+     Usually, each of these pseudo-operations expands to a single branch
+     instruction.  However, if a word branch is not sufficient, no long
+     branches are available, and the `--pcrel' option is not given, `as'
+     issues a longer code fragment in terms of NX, the opposite
+     condition to XX.  For example, under these conditions:
+              jXX foo
+     gives
+               bNXs oof
+               jmp foo
+           oof:
+
+`dbXX'
+     The full family of pseudo-operations covered here is
+           dbhi   dbls   dbcc   dbcs   dbne   dbeq   dbvc
+           dbvs   dbpl   dbmi   dbge   dblt   dbgt   dble
+           dbf    dbra   dbt
+
+     Motorola `dbXX' instructions allow word displacements only.  When
+     a word displacement is sufficient, each of these pseudo-operations
+     expands to the corresponding Motorola instruction.  When a word
+     displacement is not sufficient and long branches are available,
+     when the source reads `dbXX foo', `as' emits
+               dbXX oo1
+               bras oo2
+           oo1:bral foo
+           oo2:
+
+     If, however, long branches are not available and the `--pcrel'
+     option is not given, `as' emits
+               dbXX oo1
+               bras oo2
+           oo1:jmp foo
+           oo2:
+
+`fjXX'
+     This family includes
+           fjne   fjeq   fjge   fjlt   fjgt   fjle   fjf
+           fjt    fjgl   fjgle  fjnge  fjngl  fjngle fjngt
+           fjnle  fjnlt  fjoge  fjogl  fjogt  fjole  fjolt
+           fjor   fjseq  fjsf   fjsne  fjst   fjueq  fjuge
+           fjugt  fjule  fjult  fjun
+
+     Each of these pseudo-operations always expands to a single Motorola
+     coprocessor branch instruction, word or long.  All Motorola
+     coprocessor branch instructions allow both word and long
+     displacements.
+
+
+
+File: as.info,  Node: M68K-Chars,  Prev: M68K-Branch,  Up: M68K-opcodes
+
+8.18.6.2 Special Characters
+...........................
+
+The immediate character is `#' for Sun compatibility.  The line-comment
+character is `|' (unless the `--bitwise-or' option is used).  If a `#'
+appears at the beginning of a line, it is treated as a comment unless
+it looks like `# line file', in which case it is treated normally.
+
+
+File: as.info,  Node: M68HC11-Dependent,  Next: MIPS-Dependent,  Prev: M68K-Dependent,  Up: Machine Dependencies
+
+8.19 M68HC11 and M68HC12 Dependent Features
+===========================================
+
+* Menu:
+
+* M68HC11-Opts::                   M68HC11 and M68HC12 Options
+* M68HC11-Syntax::                 Syntax
+* M68HC11-Modifiers::              Symbolic Operand Modifiers
+* M68HC11-Directives::             Assembler Directives
+* M68HC11-Float::                  Floating Point
+* M68HC11-opcodes::                Opcodes
+
+
+File: as.info,  Node: M68HC11-Opts,  Next: M68HC11-Syntax,  Up: M68HC11-Dependent
+
+8.19.1 M68HC11 and M68HC12 Options
+----------------------------------
+
+The Motorola 68HC11 and 68HC12 version of `as' have a few machine
+dependent options.
+
+`-m68hc11'
+     This option switches the assembler in the M68HC11 mode. In this
+     mode, the assembler only accepts 68HC11 operands and mnemonics. It
+     produces code for the 68HC11.
+
+`-m68hc12'
+     This option switches the assembler in the M68HC12 mode. In this
+     mode, the assembler also accepts 68HC12 operands and mnemonics. It
+     produces code for the 68HC12. A few 68HC11 instructions are
+     replaced by some 68HC12 instructions as recommended by Motorola
+     specifications.
+
+`-m68hcs12'
+     This option switches the assembler in the M68HCS12 mode.  This
+     mode is similar to `-m68hc12' but specifies to assemble for the
+     68HCS12 series.  The only difference is on the assembling of the
+     `movb' and `movw' instruction when a PC-relative operand is used.
+
+`-mshort'
+     This option controls the ABI and indicates to use a 16-bit integer
+     ABI.  It has no effect on the assembled instructions.  This is the
+     default.
+
+`-mlong'
+     This option controls the ABI and indicates to use a 32-bit integer
+     ABI.
+
+`-mshort-double'
+     This option controls the ABI and indicates to use a 32-bit float
+     ABI.  This is the default.
+
+`-mlong-double'
+     This option controls the ABI and indicates to use a 64-bit float
+     ABI.
+
+`--strict-direct-mode'
+     You can use the `--strict-direct-mode' option to disable the
+     automatic translation of direct page mode addressing into extended
+     mode when the instruction does not support direct mode.  For
+     example, the `clr' instruction does not support direct page mode
+     addressing. When it is used with the direct page mode, `as' will
+     ignore it and generate an absolute addressing.  This option
+     prevents `as' from doing this, and the wrong usage of the direct
+     page mode will raise an error.
+
+`--short-branchs'
+     The `--short-branchs' option turns off the translation of relative
+     branches into absolute branches when the branch offset is out of
+     range. By default `as' transforms the relative branch (`bsr',
+     `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls',
+     `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when
+     the offset is out of the -128 .. 127 range.  In that case, the
+     `bsr' instruction is translated into a `jsr', the `bra'
+     instruction is translated into a `jmp' and the conditional branchs
+     instructions are inverted and followed by a `jmp'. This option
+     disables these translations and `as' will generate an error if a
+     relative branch is out of range. This option does not affect the
+     optimization associated to the `jbra', `jbsr' and `jbXX' pseudo
+     opcodes.
+
+`--force-long-branchs'
+     The `--force-long-branchs' option forces the translation of
+     relative branches into absolute branches. This option does not
+     affect the optimization associated to the `jbra', `jbsr' and
+     `jbXX' pseudo opcodes.
+
+`--print-insn-syntax'
+     You can use the `--print-insn-syntax' option to obtain the syntax
+     description of the instruction when an error is detected.
+
+`--print-opcodes'
+     The `--print-opcodes' option prints the list of all the
+     instructions with their syntax. The first item of each line
+     represents the instruction name and the rest of the line indicates
+     the possible operands for that instruction. The list is printed in
+     alphabetical order. Once the list is printed `as' exits.
+
+`--generate-example'
+     The `--generate-example' option is similar to `--print-opcodes'
+     but it generates an example for each instruction instead.
+
+
+File: as.info,  Node: M68HC11-Syntax,  Next: M68HC11-Modifiers,  Prev: M68HC11-Opts,  Up: M68HC11-Dependent
+
+8.19.2 Syntax
+-------------
+
+In the M68HC11 syntax, the instruction name comes first and it may be
+followed by one or several operands (up to three). Operands are
+separated by comma (`,'). In the normal mode, `as' will complain if too
+many operands are specified for a given instruction. In the MRI mode
+(turned on with `-M' option), it will treat them as comments. Example:
+
+     inx
+     lda  #23
+     bset 2,x #4
+     brclr *bot #8 foo
+
+   The following addressing modes are understood for 68HC11 and 68HC12:
+"Immediate"
+     `#NUMBER'
+
+"Address Register"
+     `NUMBER,X', `NUMBER,Y'
+
+     The NUMBER may be omitted in which case 0 is assumed.
+
+"Direct Addressing mode"
+     `*SYMBOL', or `*DIGITS'
+
+"Absolute"
+     `SYMBOL', or `DIGITS'
+
+   The M68HC12 has other more complex addressing modes. All of them are
+supported and they are represented below:
+
+"Constant Offset Indexed Addressing Mode"
+     `NUMBER,REG'
+
+     The NUMBER may be omitted in which case 0 is assumed.  The
+     register can be either `X', `Y', `SP' or `PC'.  The assembler will
+     use the smaller post-byte definition according to the constant
+     value (5-bit constant offset, 9-bit constant offset or 16-bit
+     constant offset).  If the constant is not known by the assembler
+     it will use the 16-bit constant offset post-byte and the value
+     will be resolved at link time.
+
+"Offset Indexed Indirect"
+     `[NUMBER,REG]'
+
+     The register can be either `X', `Y', `SP' or `PC'.
+
+"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement"
+     `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+'
+
+     The number must be in the range `-8'..`+8' and must not be 0.  The
+     register can be either `X', `Y', `SP' or `PC'.
+
+"Accumulator Offset"
+     `ACC,REG'
+
+     The accumulator register can be either `A', `B' or `D'.  The
+     register can be either `X', `Y', `SP' or `PC'.
+
+"Accumulator D offset indexed-indirect"
+     `[D,REG]'
+
+     The register can be either `X', `Y', `SP' or `PC'.
+
+
+   For example:
+
+     ldab 1024,sp
+     ldd [10,x]
+     orab 3,+x
+     stab -2,y-
+     ldx a,pc
+     sty [d,sp]
+
+
+File: as.info,  Node: M68HC11-Modifiers,  Next: M68HC11-Directives,  Prev: M68HC11-Syntax,  Up: M68HC11-Dependent
+
+8.19.3 Symbolic Operand Modifiers
+---------------------------------
+
+The assembler supports several modifiers when using symbol addresses in
+68HC11 and 68HC12 instruction operands.  The general syntax is the
+following:
+
+     %modifier(symbol)
+
+`%addr'
+     This modifier indicates to the assembler and linker to use the
+     16-bit physical address corresponding to the symbol.  This is
+     intended to be used on memory window systems to map a symbol in
+     the memory bank window.  If the symbol is in a memory expansion
+     part, the physical address corresponds to the symbol address
+     within the memory bank window.  If the symbol is not in a memory
+     expansion part, this is the symbol address (using or not using the
+     %addr modifier has no effect in that case).
+
+`%page'
+     This modifier indicates to use the memory page number corresponding
+     to the symbol.  If the symbol is in a memory expansion part, its
+     page number is computed by the linker as a number used to map the
+     page containing the symbol in the memory bank window.  If the
+     symbol is not in a memory expansion part, the page number is 0.
+
+`%hi'
+     This modifier indicates to use the 8-bit high part of the physical
+     address of the symbol.
+
+`%lo'
+     This modifier indicates to use the 8-bit low part of the physical
+     address of the symbol.
+
+
+   For example a 68HC12 call to a function `foo_example' stored in
+memory expansion part could be written as follows:
+
+     call %addr(foo_example),%page(foo_example)
+
+   and this is equivalent to
+
+     call foo_example
+
+   And for 68HC11 it could be written as follows:
+
+     ldab #%page(foo_example)
+     stab _page_switch
+     jsr  %addr(foo_example)
+
+
+File: as.info,  Node: M68HC11-Directives,  Next: M68HC11-Float,  Prev: M68HC11-Modifiers,  Up: M68HC11-Dependent
+
+8.19.4 Assembler Directives
+---------------------------
+
+The 68HC11 and 68HC12 version of `as' have the following specific
+assembler directives:
+
+`.relax'
+     The relax directive is used by the `GNU Compiler' to emit a
+     specific relocation to mark a group of instructions for linker
+     relaxation.  The sequence of instructions within the group must be
+     known to the linker so that relaxation can be performed.
+
+`.mode [mshort|mlong|mshort-double|mlong-double]'
+     This directive specifies the ABI.  It overrides the `-mshort',
+     `-mlong', `-mshort-double' and `-mlong-double' options.
+
+`.far SYMBOL'
+     This directive marks the symbol as a `far' symbol meaning that it
+     uses a `call/rtc' calling convention as opposed to `jsr/rts'.
+     During a final link, the linker will identify references to the
+     `far' symbol and will verify the proper calling convention.
+
+`.interrupt SYMBOL'
+     This directive marks the symbol as an interrupt entry point.  This
+     information is then used by the debugger to correctly unwind the
+     frame across interrupts.
+
+`.xrefb SYMBOL'
+     This directive is defined for compatibility with the
+     `Specification for Motorola 8 and 16-Bit Assembly Language Input
+     Standard' and is ignored.
+
+
+
+File: as.info,  Node: M68HC11-Float,  Next: M68HC11-opcodes,  Prev: M68HC11-Directives,  Up: M68HC11-Dependent
+
+8.19.5 Floating Point
+---------------------
+
+Packed decimal (P) format floating literals are not supported.  Feel
+free to add the code!
+
+   The floating point formats generated by directives are these.
+
+`.float'
+     `Single' precision floating point constants.
+
+`.double'
+     `Double' precision floating point constants.
+
+`.extend'
+`.ldouble'
+     `Extended' precision (`long double') floating point constants.
+
+
+File: as.info,  Node: M68HC11-opcodes,  Prev: M68HC11-Float,  Up: M68HC11-Dependent
+
+8.19.6 Opcodes
+--------------
+
+* Menu:
+
+* M68HC11-Branch::                 Branch Improvement
+
+
+File: as.info,  Node: M68HC11-Branch,  Up: M68HC11-opcodes
+
+8.19.6.1 Branch Improvement
+...........................
+
+Certain pseudo opcodes are permitted for branch instructions.  They
+expand to the shortest branch instruction that reach the target.
+Generally these mnemonics are made by prepending `j' to the start of
+Motorola mnemonic. These pseudo opcodes are not affected by the
+`--short-branchs' or `--force-long-branchs' options.
+
+   The following table summarizes the pseudo-operations.
+
+                             Displacement Width
+          +-------------------------------------------------------------+
+          |                     Options                                 |
+          |    --short-branchs            --force-long-branchs          |
+          +--------------------------+----------------------------------+
+       Op |BYTE             WORD     | BYTE          WORD               |
+          +--------------------------+----------------------------------+
+      bsr | bsr <pc-rel>    <error>  |               jsr <abs>          |
+      bra | bra <pc-rel>    <error>  |               jmp <abs>          |
+     jbsr | bsr <pc-rel>   jsr <abs> | bsr <pc-rel>  jsr <abs>          |
+     jbra | bra <pc-rel>   jmp <abs> | bra <pc-rel>  jmp <abs>          |
+      bXX | bXX <pc-rel>    <error>  |               bNX +3; jmp <abs>  |
+     jbXX | bXX <pc-rel>   bNX +3;   | bXX <pc-rel>  bNX +3; jmp <abs>  |
+          |                jmp <abs> |                                  |
+          +--------------------------+----------------------------------+
+     XX: condition
+     NX: negative of condition XX
+
+`jbsr'
+`jbra'
+     These are the simplest jump pseudo-operations; they always map to
+     one particular machine instruction, depending on the displacement
+     to the branch target.
+
+`jbXX'
+     Here, `jbXX' stands for an entire family of pseudo-operations,
+     where XX is a conditional branch or condition-code test.  The full
+     list of pseudo-ops in this family is:
+           jbcc   jbeq   jbge   jbgt   jbhi   jbvs   jbpl  jblo
+           jbcs   jbne   jblt   jble   jbls   jbvc   jbmi
+
+     For the cases of non-PC relative displacements and long
+     displacements, `as' issues a longer code fragment in terms of NX,
+     the opposite condition to XX.  For example, for the non-PC
+     relative case:
+              jbXX foo
+     gives
+               bNXs oof
+               jmp foo
+           oof:
+
+
+
+File: as.info,  Node: MIPS-Dependent,  Next: MMIX-Dependent,  Prev: M68HC11-Dependent,  Up: Machine Dependencies
+
+8.20 MIPS Dependent Features
+============================
+
+   GNU `as' for MIPS architectures supports several different MIPS
+processors, and MIPS ISA levels I through V, MIPS32, and MIPS64.  For
+information about the MIPS instruction set, see `MIPS RISC
+Architecture', by Kane and Heindrich (Prentice-Hall).  For an overview
+of MIPS assembly conventions, see "Appendix D: Assembly Language
+Programming" in the same work.
+
+* Menu:
+
+* MIPS Opts::   	Assembler options
+* MIPS Object:: 	ECOFF object code
+* MIPS Stabs::  	Directives for debugging information
+* MIPS ISA::    	Directives to override the ISA level
+* MIPS symbol sizes::   Directives to override the size of symbols
+* MIPS autoextend::	Directives for extending MIPS 16 bit instructions
+* MIPS insn::		Directive to mark data as an instruction
+* MIPS option stack::	Directives to save and restore options
+* MIPS ASE instruction generation overrides:: Directives to control
+  			generation of MIPS ASE instructions
+
+
+File: as.info,  Node: MIPS Opts,  Next: MIPS Object,  Up: MIPS-Dependent
+
+8.20.1 Assembler options
+------------------------
+
+The MIPS configurations of GNU `as' support these special options:
+
+`-G NUM'
+     This option sets the largest size of an object that can be
+     referenced implicitly with the `gp' register.  It is only accepted
+     for targets that use ECOFF format.  The default value is 8.
+
+`-EB'
+`-EL'
+     Any MIPS configuration of `as' can select big-endian or
+     little-endian output at run time (unlike the other GNU development
+     tools, which must be configured for one or the other).  Use `-EB'
+     to select big-endian output, and `-EL' for little-endian.
+
+`-mips1'
+`-mips2'
+`-mips3'
+`-mips4'
+`-mips5'
+`-mips32'
+`-mips32r2'
+`-mips64'
+`-mips64r2'
+     Generate code for a particular MIPS Instruction Set Architecture
+     level.  `-mips1' corresponds to the R2000 and R3000 processors,
+     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
+     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
+     `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to
+     generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64
+     RELEASE 2 ISA processors, respectively.  You can also switch
+     instruction sets during the assembly; see *Note Directives to
+     override the ISA level: MIPS ISA.
+
+`-mgp32'
+`-mfp32'
+     Some macros have different expansions for 32-bit and 64-bit
+     registers.  The register sizes are normally inferred from the ISA
+     and ABI, but these flags force a certain group of registers to be
+     treated as 32 bits wide at all times.  `-mgp32' controls the size
+     of general-purpose registers and `-mfp32' controls the size of
+     floating-point registers.
+
+     On some MIPS variants there is a 32-bit mode flag; when this flag
+     is set, 64-bit instructions generate a trap.  Also, some 32-bit
+     OSes only save the 32-bit registers on a context switch, so it is
+     essential never to use the 64-bit registers.
+
+`-mgp64'
+     Assume that 64-bit general purpose registers are available.  This
+     is provided in the interests of symmetry with -gp32.
+
+`-mips16'
+`-no-mips16'
+     Generate code for the MIPS 16 processor.  This is equivalent to
+     putting `.set mips16' at the start of the assembly file.
+     `-no-mips16' turns off this option.
+
+`-mips3d'
+`-no-mips3d'
+     Generate code for the MIPS-3D Application Specific Extension.
+     This tells the assembler to accept MIPS-3D instructions.
+     `-no-mips3d' turns off this option.
+
+`-mdmx'
+`-no-mdmx'
+     Generate code for the MDMX Application Specific Extension.  This
+     tells the assembler to accept MDMX instructions.  `-no-mdmx' turns
+     off this option.
+
+`-mdsp'
+`-mno-dsp'
+     Generate code for the DSP Application Specific Extension.  This
+     tells the assembler to accept DSP instructions.  `-mno-dsp' turns
+     off this option.
+
+`-mmt'
+`-mno-mt'
+     Generate code for the MT Application Specific Extension.  This
+     tells the assembler to accept MT instructions.  `-mno-mt' turns
+     off this option.
+
+`-mfix7000'
+`-mno-fix7000'
+     Cause nops to be inserted if the read of the destination register
+     of an mfhi or mflo instruction occurs in the following two
+     instructions.
+
+`-mfix-vr4120'
+`-no-mfix-vr4120'
+     Insert nops to work around certain VR4120 errata.  This option is
+     intended to be used on GCC-generated code: it is not designed to
+     catch all problems in hand-written assembler code.
+
+`-mfix-vr4130'
+`-no-mfix-vr4130'
+     Insert nops to work around the VR4130 `mflo'/`mfhi' errata.
+
+`-m4010'
+`-no-m4010'
+     Generate code for the LSI R4010 chip.  This tells the assembler to
+     accept the R4010 specific instructions (`addciu', `ffc', etc.),
+     and to not schedule `nop' instructions around accesses to the `HI'
+     and `LO' registers.  `-no-m4010' turns off this option.
+
+`-m4650'
+`-no-m4650'
+     Generate code for the MIPS R4650 chip.  This tells the assembler
+     to accept the `mad' and `madu' instruction, and to not schedule
+     `nop' instructions around accesses to the `HI' and `LO' registers.
+     `-no-m4650' turns off this option.
+
+`-m3900'
+`-no-m3900'
+`-m4100'
+`-no-m4100'
+     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
+     This tells the assembler to accept instructions specific to that
+     chip, and to schedule for that chip's hazards.
+
+`-march=CPU'
+     Generate code for a particular MIPS cpu.  It is exactly equivalent
+     to `-mCPU', except that there are more value of CPU understood.
+     Valid CPU value are:
+
+          2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
+          vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
+          rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
+          10000, 12000, mips32-4k, sb1
+
+`-mtune=CPU'
+     Schedule and tune for a particular MIPS cpu.  Valid CPU values are
+     identical to `-march=CPU'.
+
+`-mabi=ABI'
+     Record which ABI the source code uses.  The recognized arguments
+     are: `32', `n32', `o64', `64' and `eabi'.
+
+`-msym32'
+`-mno-sym32'
+     Equivalent to adding `.set sym32' or `.set nosym32' to the
+     beginning of the assembler input.  *Note MIPS symbol sizes::.
+
+`-nocpp'
+     This option is ignored.  It is accepted for command-line
+     compatibility with other assemblers, which use it to turn off C
+     style preprocessing.  With GNU `as', there is no need for
+     `-nocpp', because the GNU assembler itself never runs the C
+     preprocessor.
+
+`--construct-floats'
+`--no-construct-floats'
+     The `--no-construct-floats' option disables the construction of
+     double width floating point constants by loading the two halves of
+     the value into the two single width floating point registers that
+     make up the double width register.  This feature is useful if the
+     processor support the FR bit in its status  register, and this bit
+     is known (by the programmer) to be set.  This bit prevents the
+     aliasing of the double width register by the single width
+     registers.
+
+     By default `--construct-floats' is selected, allowing construction
+     of these floating point constants.
+
+`--trap'
+`--no-break'
+     `as' automatically macro expands certain division and
+     multiplication instructions to check for overflow and division by
+     zero.  This option causes `as' to generate code to take a trap
+     exception rather than a break exception when an error is detected.
+     The trap instructions are only supported at Instruction Set
+     Architecture level 2 and higher.
+
+`--break'
+`--no-trap'
+     Generate code to take a break exception rather than a trap
+     exception when an error is detected.  This is the default.
+
+`-mpdr'
+`-mno-pdr'
+     Control generation of `.pdr' sections.  Off by default on IRIX, on
+     elsewhere.
+
+`-mshared'
+`-mno-shared'
+     When generating code using the Unix calling conventions (selected
+     by `-KPIC' or `-mcall_shared'), gas will normally generate code
+     which can go into a shared library.  The `-mno-shared' option
+     tells gas to generate code which uses the calling convention, but
+     can not go into a shared library.  The resulting code is slightly
+     more efficient.  This option only affects the handling of the
+     `.cpload' and `.cpsetup' pseudo-ops.
+
+
+File: as.info,  Node: MIPS Object,  Next: MIPS Stabs,  Prev: MIPS Opts,  Up: MIPS-Dependent
+
+8.20.2 MIPS ECOFF object code
+-----------------------------
+
+Assembling for a MIPS ECOFF target supports some additional sections
+besides the usual `.text', `.data' and `.bss'.  The additional sections
+are `.rdata', used for read-only data, `.sdata', used for small data,
+and `.sbss', used for small common objects.
+
+   When assembling for ECOFF, the assembler uses the `$gp' (`$28')
+register to form the address of a "small object".  Any object in the
+`.sdata' or `.sbss' sections is considered "small" in this sense.  For
+external objects, or for objects in the `.bss' section, you can use the
+`gcc' `-G' option to control the size of objects addressed via `$gp';
+the default value is 8, meaning that a reference to any object eight
+bytes or smaller uses `$gp'.  Passing `-G 0' to `as' prevents it from
+using the `$gp' register on the basis of object size (but the assembler
+uses `$gp' for objects in `.sdata' or `sbss' in any case).  The size of
+an object in the `.bss' section is set by the `.comm' or `.lcomm'
+directive that defines it.  The size of an external object may be set
+with the `.extern' directive.  For example, `.extern sym,4' declares
+that the object at `sym' is 4 bytes in length, whie leaving `sym'
+otherwise undefined.
+
+   Using small ECOFF objects requires linker support, and assumes that
+the `$gp' register is correctly initialized (normally done
+automatically by the startup code).  MIPS ECOFF assembly code must not
+modify the `$gp' register.
+
+
+File: as.info,  Node: MIPS Stabs,  Next: MIPS ISA,  Prev: MIPS Object,  Up: MIPS-Dependent
+
+8.20.3 Directives for debugging information
+-------------------------------------------
+
+MIPS ECOFF `as' supports several directives used for generating
+debugging information which are not support by traditional MIPS
+assemblers.  These are `.def', `.endef', `.dim', `.file', `.scl',
+`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'.
+The debugging information generated by the three `.stab' directives can
+only be read by GDB, not by traditional MIPS debuggers (this
+enhancement is required to fully support C++ debugging).  These
+directives are primarily used by compilers, not assembly language
+programmers!
+
+
+File: as.info,  Node: MIPS symbol sizes,  Next: MIPS autoextend,  Prev: MIPS ISA,  Up: MIPS-Dependent
+
+8.20.4 Directives to override the size of symbols
+-------------------------------------------------
+
+The n64 ABI allows symbols to have any 64-bit value.  Although this
+provides a great deal of flexibility, it means that some macros have
+much longer expansions than their 32-bit counterparts.  For example,
+the non-PIC expansion of `dla $4,sym' is usually:
+
+     lui     $4,%highest(sym)
+     lui     $1,%hi(sym)
+     daddiu  $4,$4,%higher(sym)
+     daddiu  $1,$1,%lo(sym)
+     dsll32  $4,$4,0
+     daddu   $4,$4,$1
+
+   whereas the 32-bit expansion is simply:
+
+     lui     $4,%hi(sym)
+     daddiu  $4,$4,%lo(sym)
+
+   n64 code is sometimes constructed in such a way that all symbolic
+constants are known to have 32-bit values, and in such cases, it's
+preferable to use the 32-bit expansion instead of the 64-bit expansion.
+
+   You can use the `.set sym32' directive to tell the assembler that,
+from this point on, all expressions of the form `SYMBOL' or `SYMBOL +
+OFFSET' have 32-bit values.  For example:
+
+     .set sym32
+     dla     $4,sym
+     lw      $4,sym+16
+     sw      $4,sym+0x8000($4)
+
+   will cause the assembler to treat `sym', `sym+16' and `sym+0x8000'
+as 32-bit values.  The handling of non-symbolic addresses is not
+affected.
+
+   The directive `.set nosym32' ends a `.set sym32' block and reverts
+to the normal behavior.  It is also possible to change the symbol size
+using the command-line options `-msym32' and `-mno-sym32'.
+
+   These options and directives are always accepted, but at present,
+they have no effect for anything other than n64.
+
+
+File: as.info,  Node: MIPS ISA,  Next: MIPS symbol sizes,  Prev: MIPS Stabs,  Up: MIPS-Dependent
+
+8.20.5 Directives to override the ISA level
+-------------------------------------------
+
+GNU `as' supports an additional directive to change the MIPS
+Instruction Set Architecture level on the fly: `.set mipsN'.  N should
+be a number from 0 to 5, or 32, 32r2, 64 or 64r2.  The values other
+than 0 make the assembler accept instructions for the corresponding ISA
+level, from that point on in the assembly.  `.set mipsN' affects not
+only which instructions are permitted, but also how certain macros are
+expanded.  `.set mips0' restores the ISA level to its original level:
+either the level you selected with command line options, or the default
+for your configuration.  You can use this feature to permit specific
+R4000 instructions while assembling in 32 bit mode.  Use this directive
+with care!
+
+   The directive `.set mips16' puts the assembler into MIPS 16 mode, in
+which it will assemble instructions for the MIPS 16 processor.  Use
+`.set nomips16' to return to normal 32 bit mode.
+
+   Traditional MIPS assemblers do not support this directive.
+
+
+File: as.info,  Node: MIPS autoextend,  Next: MIPS insn,  Prev: MIPS symbol sizes,  Up: MIPS-Dependent
+
+8.20.6 Directives for extending MIPS 16 bit instructions
+--------------------------------------------------------
+
+By default, MIPS 16 instructions are automatically extended to 32 bits
+when necessary.  The directive `.set noautoextend' will turn this off.
+When `.set noautoextend' is in effect, any 32 bit instruction must be
+explicitly extended with the `.e' modifier (e.g., `li.e $4,1000').  The
+directive `.set autoextend' may be used to once again automatically
+extend instructions when necessary.
+
+   This directive is only meaningful when in MIPS 16 mode.  Traditional
+MIPS assemblers do not support this directive.
+
+
+File: as.info,  Node: MIPS insn,  Next: MIPS option stack,  Prev: MIPS autoextend,  Up: MIPS-Dependent
+
+8.20.7 Directive to mark data as an instruction
+-----------------------------------------------
+
+The `.insn' directive tells `as' that the following data is actually
+instructions.  This makes a difference in MIPS 16 mode: when loading
+the address of a label which precedes instructions, `as' automatically
+adds 1 to the value, so that jumping to the loaded address will do the
+right thing.
+
+
+File: as.info,  Node: MIPS option stack,  Next: MIPS ASE instruction generation overrides,  Prev: MIPS insn,  Up: MIPS-Dependent
+
+8.20.8 Directives to save and restore options
+---------------------------------------------
+
+The directives `.set push' and `.set pop' may be used to save and
+restore the current settings for all the options which are controlled
+by `.set'.  The `.set push' directive saves the current settings on a
+stack.  The `.set pop' directive pops the stack and restores the
+settings.
+
+   These directives can be useful inside an macro which must change an
+option such as the ISA level or instruction reordering but does not want
+to change the state of the code which invoked the macro.
+
+   Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info,  Node: MIPS ASE instruction generation overrides,  Prev: MIPS option stack,  Up: MIPS-Dependent
+
+8.20.9 Directives to control generation of MIPS ASE instructions
+----------------------------------------------------------------
+
+The directive `.set mips3d' makes the assembler accept instructions
+from the MIPS-3D Application Specific Extension from that point on in
+the assembly.  The `.set nomips3d' directive prevents MIPS-3D
+instructions from being accepted.
+
+   The directive `.set mdmx' makes the assembler accept instructions
+from the MDMX Application Specific Extension from that point on in the
+assembly.  The `.set nomdmx' directive prevents MDMX instructions from
+being accepted.
+
+   The directive `.set dsp' makes the assembler accept instructions
+from the DSP Application Specific Extension from that point on in the
+assembly.  The `.set nodsp' directive prevents DSP instructions from
+being accepted.
+
+   The directive `.set mt' makes the assembler accept instructions from
+the MT Application Specific Extension from that point on in the
+assembly.  The `.set nomt' directive prevents MT instructions from
+being accepted.
+
+   Traditional MIPS assemblers do not support these directives.
+
+
+File: as.info,  Node: MMIX-Dependent,  Next: MSP430-Dependent,  Prev: MIPS-Dependent,  Up: Machine Dependencies
+
+8.21 MMIX Dependent Features
+============================
+
+* Menu:
+
+* MMIX-Opts::              Command-line Options
+* MMIX-Expand::            Instruction expansion
+* MMIX-Syntax::            Syntax
+* MMIX-mmixal::		   Differences to `mmixal' syntax and semantics
+
+
+File: as.info,  Node: MMIX-Opts,  Next: MMIX-Expand,  Up: MMIX-Dependent
+
+8.21.1 Command-line Options
+---------------------------
+
+The MMIX version of `as' has some machine-dependent options.
+
+   When `--fixed-special-register-names' is specified, only the register
+names specified in *Note MMIX-Regs:: are recognized in the instructions
+`PUT' and `GET'.
+
+   You can use the `--globalize-symbols' to make all symbols global.
+This option is useful when splitting up a `mmixal' program into several
+files.
+
+   The `--gnu-syntax' turns off most syntax compatibility with
+`mmixal'.  Its usability is currently doubtful.
+
+   The `--relax' option is not fully supported, but will eventually make
+the object file prepared for linker relaxation.
+
+   If you want to avoid inadvertently calling a predefined symbol and
+would rather get an error, for example when using `as' with a compiler
+or other machine-generated code, specify `--no-predefined-syms'.  This
+turns off built-in predefined definitions of all such symbols,
+including rounding-mode symbols, segment symbols, `BIT' symbols, and
+`TRAP' symbols used in `mmix' "system calls".  It also turns off
+predefined special-register names, except when used in `PUT' and `GET'
+instructions.
+
+   By default, some instructions are expanded to fit the size of the
+operand or an external symbol (*note MMIX-Expand::).  By passing
+`--no-expand', no such expansion will be done, instead causing errors
+at link time if the operand does not fit.
+
+   The `mmixal' documentation (*note mmixsite::) specifies that global
+registers allocated with the `GREG' directive (*note MMIX-greg::) and
+initialized to the same non-zero value, will refer to the same global
+register.  This isn't strictly enforceable in `as' since the final
+addresses aren't known until link-time, but it will do an effort unless
+the `--no-merge-gregs' option is specified.  (Register merging isn't
+yet implemented in `ld'.)
+
+   `as' will warn every time it expands an instruction to fit an
+operand unless the option `-x' is specified.  It is believed that this
+behaviour is more useful than just mimicking `mmixal''s behaviour, in
+which instructions are only expanded if the `-x' option is specified,
+and assembly fails otherwise, when an instruction needs to be expanded.
+It needs to be kept in mind that `mmixal' is both an assembler and
+linker, while `as' will expand instructions that at link stage can be
+contracted.  (Though linker relaxation isn't yet implemented in `ld'.)
+The option `-x' also imples `--linker-allocated-gregs'.
+
+   If instruction expansion is enabled, `as' can expand a `PUSHJ'
+instruction into a series of instructions.  The shortest expansion is
+to not expand it, but just mark the call as redirectable to a stub,
+which `ld' creates at link-time, but only if the original `PUSHJ'
+instruction is found not to reach the target.  The stub consists of the
+necessary instructions to form a jump to the target.  This happens if
+`as' can assert that the `PUSHJ' instruction can reach such a stub.
+The option `--no-pushj-stubs' disables this shorter expansion, and the
+longer series of instructions is then created at assembly-time.  The
+option `--no-stubs' is a synonym, intended for compatibility with
+future releases, where generation of stubs for other instructions may
+be implemented.
+
+   Usually a two-operand-expression (*note GREG-base::) without a
+matching `GREG' directive is treated as an error by `as'.  When the
+option `--linker-allocated-gregs' is in effect, they are instead passed
+through to the linker, which will allocate as many global registers as
+is needed.
+
+
+File: as.info,  Node: MMIX-Expand,  Next: MMIX-Syntax,  Prev: MMIX-Opts,  Up: MMIX-Dependent
+
+8.21.2 Instruction expansion
+----------------------------
+
+When `as' encounters an instruction with an operand that is either not
+known or does not fit the operand size of the instruction, `as' (and
+`ld') will expand the instruction into a sequence of instructions
+semantically equivalent to the operand fitting the instruction.
+Expansion will take place for the following instructions:
+
+`GETA'
+     Expands to a sequence of four instructions: `SETL', `INCML',
+     `INCMH' and `INCH'.  The operand must be a multiple of four.
+
+Conditional branches
+     A branch instruction is turned into a branch with the complemented
+     condition and prediction bit over five instructions; four
+     instructions setting `$255' to the operand value, which like with
+     `GETA' must be a multiple of four, and a final `GO $255,$255,0'.
+
+`PUSHJ'
+     Similar to expansion for conditional branches; four instructions
+     set `$255' to the operand value, followed by a `PUSHGO
+     $255,$255,0'.
+
+`JMP'
+     Similar to conditional branches and `PUSHJ'.  The final instruction
+     is `GO $255,$255,0'.
+
+   The linker `ld' is expected to shrink these expansions for code
+assembled with `--relax' (though not currently implemented).
+
+
+File: as.info,  Node: MMIX-Syntax,  Next: MMIX-mmixal,  Prev: MMIX-Expand,  Up: MMIX-Dependent
+
+8.21.3 Syntax
+-------------
+
+The assembly syntax is supposed to be upward compatible with that
+described in Sections 1.3 and 1.4 of `The Art of Computer Programming,
+Volume 1'.  Draft versions of those chapters as well as other MMIX
+information is located at
+`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'.  Most code
+examples from the mmixal package located there should work unmodified
+when assembled and linked as single files, with a few noteworthy
+exceptions (*note MMIX-mmixal::).
+
+   Before an instruction is emitted, the current location is aligned to
+the next four-byte boundary.  If a label is defined at the beginning of
+the line, its value will be the aligned value.
+
+   In addition to the traditional hex-prefix `0x', a hexadecimal number
+can also be specified by the prefix character `#'.
+
+   After all operands to an MMIX instruction or directive have been
+specified, the rest of the line is ignored, treated as a comment.
+
+* Menu:
+
+* MMIX-Chars::		        Special Characters
+* MMIX-Symbols::		Symbols
+* MMIX-Regs::			Register Names
+* MMIX-Pseudos::		Assembler Directives
+
+
+File: as.info,  Node: MMIX-Chars,  Next: MMIX-Symbols,  Up: MMIX-Syntax
+
+8.21.3.1 Special Characters
+...........................
+
+The characters `*' and `#' are line comment characters; each start a
+comment at the beginning of a line, but only at the beginning of a
+line.  A `#' prefixes a hexadecimal number if found elsewhere on a line.
+
+   Two other characters, `%' and `!', each start a comment anywhere on
+the line.  Thus you can't use the `modulus' and `not' operators in
+expressions normally associated with these two characters.
+
+   A `;' is a line separator, treated as a new-line, so separate
+instructions can be specified on a single line.
+
+
+File: as.info,  Node: MMIX-Symbols,  Next: MMIX-Regs,  Prev: MMIX-Chars,  Up: MMIX-Syntax
+
+8.21.3.2 Symbols
+................
+
+The character `:' is permitted in identifiers.  There are two
+exceptions to it being treated as any other symbol character: if a
+symbol begins with `:', it means that the symbol is in the global
+namespace and that the current prefix should not be prepended to that
+symbol (*note MMIX-prefix::).  The `:' is then not considered part of
+the symbol.  For a symbol in the label position (first on a line), a `:'
+at the end of a symbol is silently stripped off.  A label is permitted,
+but not required, to be followed by a `:', as with many other assembly
+formats.
+
+   The character `@' in an expression, is a synonym for `.', the
+current location.
+
+   In addition to the common forward and backward local symbol formats
+(*note Symbol Names::), they can be specified with upper-case `B' and
+`F', as in `8B' and `9F'.  A local label defined for the current
+position is written with a `H' appended to the number:
+     3H LDB $0,$1,2
+   This and traditional local-label formats cannot be mixed: a label
+must be defined and referred to using the same format.
+
+   There's a minor caveat: just as for the ordinary local symbols, the
+local symbols are translated into ordinary symbols using control
+characters are to hide the ordinal number of the symbol.
+Unfortunately, these symbols are not translated back in error messages.
+Thus you may see confusing error messages when local symbols are used.
+Control characters `\003' (control-C) and `\004' (control-D) are used
+for the MMIX-specific local-symbol syntax.
+
+   The symbol `Main' is handled specially; it is always global.
+
+   By defining the symbols `__.MMIX.start..text' and
+`__.MMIX.start..data', the address of respectively the `.text' and
+`.data' segments of the final program can be defined, though when
+linking more than one object file, the code or data in the object file
+containing the symbol is not guaranteed to be start at that position;
+just the final executable.  *Note MMIX-loc::.
+
+
+File: as.info,  Node: MMIX-Regs,  Next: MMIX-Pseudos,  Prev: MMIX-Symbols,  Up: MMIX-Syntax
+
+8.21.3.3 Register names
+.......................
+
+Local and global registers are specified as `$0' to `$255'.  The
+recognized special register names are `rJ', `rA', `rB', `rC', `rD',
+`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ',
+`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT',
+`rWW', `rXX', `rYY' and `rZZ'.  A leading `:' is optional for special
+register names.
+
+   Local and global symbols can be equated to register names and used in
+place of ordinary registers.
+
+   Similarly for special registers, local and global symbols can be
+used.  Also, symbols equated from numbers and constant expressions are
+allowed in place of a special register, except when either of the
+options `--no-predefined-syms' and `--fixed-special-register-names' are
+specified.  Then only the special register names above are allowed for
+the instructions having a special register operand; `GET' and `PUT'.
+
+
+File: as.info,  Node: MMIX-Pseudos,  Prev: MMIX-Regs,  Up: MMIX-Syntax
+
+8.21.3.4 Assembler Directives
+.............................
+
+`LOC'
+     The `LOC' directive sets the current location to the value of the
+     operand field, which may include changing sections.  If the
+     operand is a constant, the section is set to either `.data' if the
+     value is `0x2000000000000000' or larger, else it is set to `.text'.
+     Within a section, the current location may only be changed to
+     monotonically higher addresses.  A LOC expression must be a
+     previously defined symbol or a "pure" constant.
+
+     An example, which sets the label PREV to the current location, and
+     updates the current location to eight bytes forward:
+          prev LOC @+8
+
+     When a LOC has a constant as its operand, a symbol
+     `__.MMIX.start..text' or `__.MMIX.start..data' is defined
+     depending on the address as mentioned above.  Each such symbol is
+     interpreted as special by the linker, locating the section at that
+     address.  Note that if multiple files are linked, the first object
+     file with that section will be mapped to that address (not
+     necessarily the file with the LOC definition).
+
+`LOCAL'
+     Example:
+           LOCAL external_symbol
+           LOCAL 42
+           .local asymbol
+
+     This directive-operation generates a link-time assertion that the
+     operand does not correspond to a global register.  The operand is
+     an expression that at link-time resolves to a register symbol or a
+     number.  A number is treated as the register having that number.
+     There is one restriction on the use of this directive: the
+     pseudo-directive must be placed in a section with contents, code
+     or data.
+
+`IS'
+     The `IS' directive:
+          asymbol IS an_expression
+     sets the symbol `asymbol' to `an_expression'.  A symbol may not be
+     set more than once using this directive.  Local labels may be set
+     using this directive, for example:
+          5H IS @+4
+
+`GREG'
+     This directive reserves a global register, gives it an initial
+     value and optionally gives it a symbolic name.  Some examples:
+
+          areg GREG
+          breg GREG data_value
+               GREG data_buffer
+               .greg creg, another_data_value
+
+     The symbolic register name can be used in place of a (non-special)
+     register.  If a value isn't provided, it defaults to zero.  Unless
+     the option `--no-merge-gregs' is specified, non-zero registers
+     allocated with this directive may be eliminated by `as'; another
+     register with the same value used in its place.  Any of the
+     instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU',
+     `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW',
+     `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT',
+     `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can
+     have a value nearby an initial value in place of its second and
+     third operands.  Here, "nearby" is defined as within the range
+     0...255 from the initial value of such an allocated register.
+
+          buffer1 BYTE 0,0,0,0,0
+          buffer2 BYTE 0,0,0,0,0
+           ...
+           GREG buffer1
+           LDOU $42,buffer2
+     In the example above, the `Y' field of the `LDOUI' instruction
+     (LDOU with a constant Z) will be replaced with the global register
+     allocated for `buffer1', and the `Z' field will have the value 5,
+     the offset from `buffer1' to `buffer2'.  The result is equivalent
+     to this code:
+          buffer1 BYTE 0,0,0,0,0
+          buffer2 BYTE 0,0,0,0,0
+           ...
+          tmpreg GREG buffer1
+           LDOU $42,tmpreg,(buffer2-buffer1)
+
+     Global registers allocated with this directive are allocated in
+     order higher-to-lower within a file.  Other than that, the exact
+     order of register allocation and elimination is undefined.  For
+     example, the order is undefined when more than one file with such
+     directives are linked together.  With the options `-x' and
+     `--linker-allocated-gregs', `GREG' directives for two-operand
+     cases like the one mentioned above can be omitted.  Sufficient
+     global registers will then be allocated by the linker.
+
+`BYTE'
+     The `BYTE' directive takes a series of operands separated by a
+     comma.  If an operand is a string (*note Strings::), each
+     character of that string is emitted as a byte.  Other operands
+     must be constant expressions without forward references, in the
+     range 0...255.  If you need operands having expressions with
+     forward references, use `.byte' (*note Byte::).  An operand can be
+     omitted, defaulting to a zero value.
+
+`WYDE'
+`TETRA'
+`OCTA'
+     The directives `WYDE', `TETRA' and `OCTA' emit constants of two,
+     four and eight bytes size respectively.  Before anything else
+     happens for the directive, the current location is aligned to the
+     respective constant-size boundary.  If a label is defined at the
+     beginning of the line, its value will be that after the alignment.
+     A single operand can be omitted, defaulting to a zero value
+     emitted for the directive.  Operands can be expressed as strings
+     (*note Strings::), in which case each character in the string is
+     emitted as a separate constant of the size indicated by the
+     directive.
+
+`PREFIX'
+     The `PREFIX' directive sets a symbol name prefix to be prepended to
+     all symbols (except local symbols, *note MMIX-Symbols::), that are
+     not prefixed with `:', until the next `PREFIX' directive.  Such
+     prefixes accumulate.  For example,
+           PREFIX a
+           PREFIX b
+          c IS 0
+     defines a symbol `abc' with the value 0.
+
+`BSPEC'
+`ESPEC'
+     A pair of `BSPEC' and `ESPEC' directives delimit a section of
+     special contents (without specified semantics).  Example:
+           BSPEC 42
+           TETRA 1,2,3
+           ESPEC
+     The single operand to `BSPEC' must be number in the range 0...255.
+     The `BSPEC' number 80 is used by the GNU binutils implementation.
+
+
+File: as.info,  Node: MMIX-mmixal,  Prev: MMIX-Syntax,  Up: MMIX-Dependent
+
+8.21.4 Differences to `mmixal'
+------------------------------
+
+The binutils `as' and `ld' combination has a few differences in
+function compared to `mmixal' (*note mmixsite::).
+
+   The replacement of a symbol with a GREG-allocated register (*note
+GREG-base::) is not handled the exactly same way in `as' as in
+`mmixal'.  This is apparent in the `mmixal' example file `inout.mms',
+where different registers with different offsets, eventually yielding
+the same address, are used in the first instruction.  This type of
+difference should however not affect the function of any program unless
+it has specific assumptions about the allocated register number.
+
+   Line numbers (in the `mmo' object format) are currently not
+supported.
+
+   Expression operator precedence is not that of mmixal: operator
+precedence is that of the C programming language.  It's recommended to
+use parentheses to explicitly specify wanted operator precedence
+whenever more than one type of operators are used.
+
+   The serialize unary operator `&', the fractional division operator
+`//', the logical not operator `!' and the modulus operator `%' are not
+available.
+
+   Symbols are not global by default, unless the option
+`--globalize-symbols' is passed.  Use the `.global' directive to
+globalize symbols (*note Global::).
+
+   Operand syntax is a bit stricter with `as' than `mmixal'.  For
+example, you can't say `addu 1,2,3', instead you must write `addu
+$1,$2,3'.
+
+   You can't LOC to a lower address than those already visited (i.e.
+"backwards").
+
+   A LOC directive must come before any emitted code.
+
+   Predefined symbols are visible as file-local symbols after use.  (In
+the ELF file, that is--the linked mmo file has no notion of a file-local
+symbol.)
+
+   Some mapping of constant expressions to sections in LOC expressions
+is attempted, but that functionality is easily confused and should be
+avoided unless compatibility with `mmixal' is required.  A LOC
+expression to `0x2000000000000000' or higher, maps to the `.data'
+section and lower addresses map to the `.text' section (*note
+MMIX-loc::).
+
+   The code and data areas are each contiguous.  Sparse programs with
+far-away LOC directives will take up the same amount of space as a
+contiguous program with zeros filled in the gaps between the LOC
+directives.  If you need sparse programs, you might try and get the
+wanted effect with a linker script and splitting up the code parts into
+sections (*note Section::).  Assembly code for this, to be compatible
+with `mmixal', would look something like:
+      .if 0
+      LOC away_expression
+      .else
+      .section away,"ax"
+      .fi
+   `as' will not execute the LOC directive and `mmixal' ignores the
+lines with `.'.  This construct can be used generally to help
+compatibility.
+
+   Symbols can't be defined twice-not even to the same value.
+
+   Instruction mnemonics are recognized case-insensitive, though the
+`IS' and `GREG' pseudo-operations must be specified in upper-case
+characters.
+
+   There's no unicode support.
+
+   The following is a list of programs in `mmix.tar.gz', available at
+`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last
+checked with the version dated 2001-08-25 (md5sum
+c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do
+not assemble with `as':
+
+`silly.mms'
+     LOC to a previous address.
+
+`sim.mms'
+     Redefines symbol `Done'.
+
+`test.mms'
+     Uses the serial operator `&'.
+
+
+File: as.info,  Node: MSP430-Dependent,  Next: SH-Dependent,  Prev: MMIX-Dependent,  Up: Machine Dependencies
+
+8.22 MSP 430 Dependent Features
+===============================
+
+* Menu:
+
+* MSP430 Options::              Options
+* MSP430 Syntax::               Syntax
+* MSP430 Floating Point::       Floating Point
+* MSP430 Directives::           MSP 430 Machine Directives
+* MSP430 Opcodes::              Opcodes
+* MSP430 Profiling Capability::	Profiling Capability
+
+
+File: as.info,  Node: MSP430 Options,  Next: MSP430 Syntax,  Up: MSP430-Dependent
+
+8.22.1 Options
+--------------
+
+`-m'
+     select the mpu arch. Currently has no effect.
+
+`-mP'
+     enables polymorph instructions handler.
+
+`-mQ'
+     enables relaxation at assembly time. DANGEROUS!
+
+
+
+File: as.info,  Node: MSP430 Syntax,  Next: MSP430 Floating Point,  Prev: MSP430 Options,  Up: MSP430-Dependent
+
+8.22.2 Syntax
+-------------
+
+* Menu:
+
+* MSP430-Macros::		Macros
+* MSP430-Chars::                Special Characters
+* MSP430-Regs::                 Register Names
+* MSP430-Ext::			Assembler Extensions
+
+
+File: as.info,  Node: MSP430-Macros,  Next: MSP430-Chars,  Up: MSP430 Syntax
+
+8.22.2.1 Macros
+...............
+
+The macro syntax used on the MSP 430 is like that described in the MSP
+430 Family Assembler Specification.  Normal `as' macros should still
+work.
+
+   Additional built-in macros are:
+
+`llo(exp)'
+     Extracts least significant word from 32-bit expression 'exp'.
+
+`lhi(exp)'
+     Extracts most significant word from 32-bit expression 'exp'.
+
+`hlo(exp)'
+     Extracts 3rd word from 64-bit expression 'exp'.
+
+`hhi(exp)'
+     Extracts 4rd word from 64-bit expression 'exp'.
+
+
+   They normally being used as an immediate source operand.
+         mov	#llo(1), r10	;	== mov	#1, r10
+         mov	#lhi(1), r10	;	== mov	#0, r10
+
+
+File: as.info,  Node: MSP430-Chars,  Next: MSP430-Regs,  Prev: MSP430-Macros,  Up: MSP430 Syntax
+
+8.22.2.2 Special Characters
+...........................
+
+`;' is the line comment character.
+
+   The character `$' in jump instructions indicates current location and
+implemented only for TI syntax compatibility.
+
+
+File: as.info,  Node: MSP430-Regs,  Next: MSP430-Ext,  Prev: MSP430-Chars,  Up: MSP430 Syntax
+
+8.22.2.3 Register Names
+.......................
+
+General-purpose registers are represented by predefined symbols of the
+form `rN' (for global registers), where N represents a number between
+`0' and `15'.  The leading letters may be in either upper or lower
+case; for example, `r13' and `R7' are both valid register names.
+
+   Register names `PC', `SP' and `SR' cannot be used as register names
+and will be treated as variables. Use `r0', `r1', and `r2' instead.
+
+
+File: as.info,  Node: MSP430-Ext,  Prev: MSP430-Regs,  Up: MSP430 Syntax
+
+8.22.2.4 Assembler Extensions
+.............................
+
+`@rN'
+     As destination operand being treated as `0(rn)'
+
+`0(rN)'
+     As source operand being treated as `@rn'
+
+`jCOND +N'
+     Skips next N bytes followed by jump instruction and equivalent to
+     `jCOND $+N+2'
+
+
+   Also, there are some instructions, which cannot be found in other
+assemblers.  These are branch instructions, which has different opcodes
+upon jump distance.  They all got PC relative addressing mode.
+
+`beq label'
+     A polymorph instruction which is `jeq label' in case if jump
+     distance within allowed range for cpu's jump instruction. If not,
+     this unrolls into a sequence of
+            jne $+6
+            br  label
+
+`bne label'
+     A polymorph instruction which is `jne label' or `jeq +4; br label'
+
+`blt label'
+     A polymorph instruction which is `jl label' or `jge +4; br label'
+
+`bltn label'
+     A polymorph instruction which is `jn label' or `jn +2; jmp +4; br
+     label'
+
+`bltu label'
+     A polymorph instruction which is `jlo label' or `jhs +2; br label'
+
+`bge label'
+     A polymorph instruction which is `jge label' or `jl +4; br label'
+
+`bgeu label'
+     A polymorph instruction which is `jhs label' or `jlo +4; br label'
+
+`bgt label'
+     A polymorph instruction which is `jeq +2; jge label' or `jeq +6;
+     jl  +4; br label'
+
+`bgtu label'
+     A polymorph instruction which is `jeq +2; jhs label' or `jeq +6;
+     jlo +4; br label'
+
+`bleu label'
+     A polymorph instruction which is `jeq label; jlo label' or `jeq
+     +2; jhs +4; br label'
+
+`ble label'
+     A polymorph instruction which is `jeq label; jl  label' or `jeq
+     +2; jge +4; br label'
+
+`jump label'
+     A polymorph instruction which is `jmp label' or `br label'
+
+
+File: as.info,  Node: MSP430 Floating Point,  Next: MSP430 Directives,  Prev: MSP430 Syntax,  Up: MSP430-Dependent
+
+8.22.3 Floating Point
+---------------------
+
+The MSP 430 family uses IEEE 32-bit floating-point numbers.
+
+
+File: as.info,  Node: MSP430 Directives,  Next: MSP430 Opcodes,  Prev: MSP430 Floating Point,  Up: MSP430-Dependent
+
+8.22.4 MSP 430 Machine Directives
+---------------------------------
+
+`.file'
+     This directive is ignored; it is accepted for compatibility with
+     other MSP 430 assemblers.
+
+          _Warning:_ in other versions of the GNU assembler, `.file' is
+          used for the directive called `.app-file' in the MSP 430
+          support.
+
+`.line'
+     This directive is ignored; it is accepted for compatibility with
+     other MSP 430 assemblers.
+
+`.arch'
+     Currently this directive is ignored; it is accepted for
+     compatibility with other MSP 430 assemblers.
+
+`.profiler'
+     This directive instructs assembler to add new profile entry to the
+     object file.
+
+
+
+File: as.info,  Node: MSP430 Opcodes,  Next: MSP430 Profiling Capability,  Prev: MSP430 Directives,  Up: MSP430-Dependent
+
+8.22.5 Opcodes
+--------------
+
+`as' implements all the standard MSP 430 opcodes.  No additional
+pseudo-instructions are needed on this family.
+
+   For information on the 430 machine instruction set, see `MSP430
+User's Manual, document slau049d', Texas Instrument, Inc.
+
+
+File: as.info,  Node: MSP430 Profiling Capability,  Prev: MSP430 Opcodes,  Up: MSP430-Dependent
+
+8.22.6 Profiling Capability
+---------------------------
+
+It is a performance hit to use gcc's profiling approach for this tiny
+target.  Even more - jtag hardware facility does not perform any
+profiling functions.  However we've got gdb's built-in simulator where
+we can do anything.
+
+   We define new section `.profiler' which holds all profiling
+information.  We define new pseudo operation `.profiler' which will
+instruct assembler to add new profile entry to the object file. Profile
+should take place at the present address.
+
+   Pseudo operation format:
+
+   `.profiler flags,function_to_profile [, cycle_corrector, extra]'
+
+   where:
+
+          `flags' is a combination of the following characters:
+
+    `s'
+          function entry
+
+    `x'
+          function exit
+
+    `i'
+          function is in init section
+
+    `f'
+          function is in fini section
+
+    `l'
+          library call
+
+    `c'
+          libc standard call
+
+    `d'
+          stack value demand
+
+    `I'
+          interrupt service routine
+
+    `P'
+          prologue start
+
+    `p'
+          prologue end
+
+    `E'
+          epilogue start
+
+    `e'
+          epilogue end
+
+    `j'
+          long jump / sjlj unwind
+
+    `a'
+          an arbitrary code fragment
+
+    `t'
+          extra parameter saved (a constant value like frame size)
+
+`function_to_profile'
+     a function address
+
+`cycle_corrector'
+     a value which should be added to the cycle counter, zero if
+     omitted.
+
+`extra'
+     any extra parameter, zero if omitted.
+
+
+   For example:
+     .global fxx
+     .type fxx,@function
+     fxx:
+     .LFrameOffset_fxx=0x08
+     .profiler "scdP", fxx     ; function entry.
+     			  ; we also demand stack value to be saved
+       push r11
+       push r10
+       push r9
+       push r8
+     .profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
+     					  ; (this is a prologue end)
+     					  ; note, that spare var filled with
+     					  ; the farme size
+       mov r15,r8
+     ...
+     .profiler cdE,fxx         ; check stack
+       pop r8
+       pop r9
+       pop r10
+       pop r11
+     .profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
+       ret                     ; cause 'ret' insn takes 3 cycles
+
+
+File: as.info,  Node: PDP-11-Dependent,  Next: PJ-Dependent,  Prev: SH64-Dependent,  Up: Machine Dependencies
+
+8.23 PDP-11 Dependent Features
+==============================
+
+* Menu:
+
+* PDP-11-Options::		Options
+* PDP-11-Pseudos::		Assembler Directives
+* PDP-11-Syntax::		DEC Syntax versus BSD Syntax
+* PDP-11-Mnemonics::		Instruction Naming
+* PDP-11-Synthetic::		Synthetic Instructions
+
+
+File: as.info,  Node: PDP-11-Options,  Next: PDP-11-Pseudos,  Up: PDP-11-Dependent
+
+8.23.1 Options
+--------------
+
+The PDP-11 version of `as' has a rich set of machine dependent options.
+
+8.23.1.1 Code Generation Options
+................................
+
+`-mpic | -mno-pic'
+     Generate position-independent (or position-dependent) code.
+
+     The default is to generate position-independent code.
+
+8.23.1.2 Instruction Set Extension Options
+..........................................
+
+These options enables or disables the use of extensions over the base
+line instruction set as introduced by the first PDP-11 CPU: the KA11.
+Most options come in two variants: a `-m'EXTENSION that enables
+EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION.
+
+   The default is to enable all extensions.
+
+`-mall | -mall-extensions'
+     Enable all instruction set extensions.
+
+`-mno-extensions'
+     Disable all instruction set extensions.
+
+`-mcis | -mno-cis'
+     Enable (or disable) the use of the commercial instruction set,
+     which consists of these instructions: `ADDNI', `ADDN', `ADDPI',
+     `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC',
+     `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI',
+     `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL',
+     `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI',
+     `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC',
+     `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI',
+     `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'.
+
+`-mcsm | -mno-csm'
+     Enable (or disable) the use of the `CSM' instruction.
+
+`-meis | -mno-eis'
+     Enable (or disable) the use of the extended instruction set, which
+     consists of these instructions: `ASHC', `ASH', `DIV', `MARK',
+     `MUL', `RTT', `SOB' `SXT', and `XOR'.
+
+`-mfis | -mkev11'
+`-mno-fis | -mno-kev11'
+     Enable (or disable) the use of the KEV11 floating-point
+     instructions: `FADD', `FDIV', `FMUL', and `FSUB'.
+
+`-mfpp | -mfpu | -mfp-11'
+`-mno-fpp | -mno-fpu | -mno-fp-11'
+     Enable (or disable) the use of FP-11 floating-point instructions:
+     `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF',
+     `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF',
+     `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST',
+     `SUBF', and `TSTF'.
+
+`-mlimited-eis | -mno-limited-eis'
+     Enable (or disable) the use of the limited extended instruction
+     set: `MARK', `RTT', `SOB', `SXT', and `XOR'.
+
+     The -mno-limited-eis options also implies -mno-eis.
+
+`-mmfpt | -mno-mfpt'
+     Enable (or disable) the use of the `MFPT' instruction.
+
+`-mmultiproc | -mno-multiproc'
+     Enable (or disable) the use of multiprocessor instructions:
+     `TSTSET' and `WRTLCK'.
+
+`-mmxps | -mno-mxps'
+     Enable (or disable) the use of the `MFPS' and `MTPS' instructions.
+
+`-mspl | -mno-spl'
+     Enable (or disable) the use of the `SPL' instruction.
+
+     Enable (or disable) the use of the microcode instructions: `LDUB',
+     `MED', and `XFC'.
+
+8.23.1.3 CPU Model Options
+..........................
+
+These options enable the instruction set extensions supported by a
+particular CPU, and disables all other extensions.
+
+`-mka11'
+     KA11 CPU.  Base line instruction set only.
+
+`-mkb11'
+     KB11 CPU.  Enable extended instruction set and `SPL'.
+
+`-mkd11a'
+     KD11-A CPU.  Enable limited extended instruction set.
+
+`-mkd11b'
+     KD11-B CPU.  Base line instruction set only.
+
+`-mkd11d'
+     KD11-D CPU.  Base line instruction set only.
+
+`-mkd11e'
+     KD11-E CPU.  Enable extended instruction set, `MFPS', and `MTPS'.
+
+`-mkd11f | -mkd11h | -mkd11q'
+     KD11-F, KD11-H, or KD11-Q CPU.  Enable limited extended
+     instruction set, `MFPS', and `MTPS'.
+
+`-mkd11k'
+     KD11-K CPU.  Enable extended instruction set, `LDUB', `MED',
+     `MFPS', `MFPT', `MTPS', and `XFC'.
+
+`-mkd11z'
+     KD11-Z CPU.  Enable extended instruction set, `CSM', `MFPS',
+     `MFPT', `MTPS', and `SPL'.
+
+`-mf11'
+     F11 CPU.  Enable extended instruction set, `MFPS', `MFPT', and
+     `MTPS'.
+
+`-mj11'
+     J11 CPU.  Enable extended instruction set, `CSM', `MFPS', `MFPT',
+     `MTPS', `SPL', `TSTSET', and `WRTLCK'.
+
+`-mt11'
+     T11 CPU.  Enable limited extended instruction set, `MFPS', and
+     `MTPS'.
+
+8.23.1.4 Machine Model Options
+..............................
+
+These options enable the instruction set extensions supported by a
+particular machine model, and disables all other extensions.
+
+`-m11/03'
+     Same as `-mkd11f'.
+
+`-m11/04'
+     Same as `-mkd11d'.
+
+`-m11/05 | -m11/10'
+     Same as `-mkd11b'.
+
+`-m11/15 | -m11/20'
+     Same as `-mka11'.
+
+`-m11/21'
+     Same as `-mt11'.
+
+`-m11/23 | -m11/24'
+     Same as `-mf11'.
+
+`-m11/34'
+     Same as `-mkd11e'.
+
+`-m11/34a'
+     Ame as `-mkd11e' `-mfpp'.
+
+`-m11/35 | -m11/40'
+     Same as `-mkd11a'.
+
+`-m11/44'
+     Same as `-mkd11z'.
+
+`-m11/45 | -m11/50 | -m11/55 | -m11/70'
+     Same as `-mkb11'.
+
+`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94'
+     Same as `-mj11'.
+
+`-m11/60'
+     Same as `-mkd11k'.
+
+
+File: as.info,  Node: PDP-11-Pseudos,  Next: PDP-11-Syntax,  Prev: PDP-11-Options,  Up: PDP-11-Dependent
+
+8.23.2 Assembler Directives
+---------------------------
+
+The PDP-11 version of `as' has a few machine dependent assembler
+directives.
+
+`.bss'
+     Switch to the `bss' section.
+
+`.even'
+     Align the location counter to an even number.
+
+
+File: as.info,  Node: PDP-11-Syntax,  Next: PDP-11-Mnemonics,  Prev: PDP-11-Pseudos,  Up: PDP-11-Dependent
+
+8.23.3 PDP-11 Assembly Language Syntax
+--------------------------------------
+
+`as' supports both DEC syntax and BSD syntax.  The only difference is
+that in DEC syntax, a `#' character is used to denote an immediate
+constants, while in BSD syntax the character for this purpose is `$'.
+
+   eneral-purpose registers are named `r0' through `r7'.  Mnemonic
+alternatives for `r6' and `r7' are `sp' and `pc', respectively.
+
+   Floating-point registers are named `ac0' through `ac3', or
+alternatively `fr0' through `fr3'.
+
+   Comments are started with a `#' or a `/' character, and extend to
+the end of the line.  (FIXME: clash with immediates?)
+
+
+File: as.info,  Node: PDP-11-Mnemonics,  Next: PDP-11-Synthetic,  Prev: PDP-11-Syntax,  Up: PDP-11-Dependent
+
+8.23.4 Instruction Naming
+-------------------------
+
+Some instructions have alternative names.
+
+`BCC'
+     `BHIS'
+
+`BCS'
+     `BLO'
+
+`L2DR'
+     `L2D'
+
+`L3DR'
+     `L3D'
+
+`SYS'
+     `TRAP'
+
+
+File: as.info,  Node: PDP-11-Synthetic,  Prev: PDP-11-Mnemonics,  Up: PDP-11-Dependent
+
+8.23.5 Synthetic Instructions
+-----------------------------
+
+The `JBR' and `J'CC synthetic instructions are not supported yet.
+
+
+File: as.info,  Node: PJ-Dependent,  Next: PPC-Dependent,  Prev: PDP-11-Dependent,  Up: Machine Dependencies
+
+8.24 picoJava Dependent Features
+================================
+
+* Menu:
+
+* PJ Options::              Options
+
+
+File: as.info,  Node: PJ Options,  Up: PJ-Dependent
+
+8.24.1 Options
+--------------
+
+`as' has two additional command-line options for the picoJava
+architecture.
+`-ml'
+     This option selects little endian data output.
+
+`-mb'
+     This option selects big endian data output.
+
+
+File: as.info,  Node: PPC-Dependent,  Next: Sparc-Dependent,  Prev: PJ-Dependent,  Up: Machine Dependencies
+
+8.25 PowerPC Dependent Features
+===============================
+
+* Menu:
+
+* PowerPC-Opts::                Options
+* PowerPC-Pseudo::              PowerPC Assembler Directives
+
+
+File: as.info,  Node: PowerPC-Opts,  Next: PowerPC-Pseudo,  Up: PPC-Dependent
+
+8.25.1 Options
+--------------
+
+The PowerPC chip family includes several successive levels, using the
+same core instruction set, but including a few additional instructions
+at each level.  There are exceptions to this however.  For details on
+what instructions each variant supports, please see the chip's
+architecture reference manual.
+
+   The following table lists all available PowerPC options.
+
+`-mpwrx | -mpwr2'
+     Generate code for POWER/2 (RIOS2).
+
+`-mpwr'
+     Generate code for POWER (RIOS1)
+
+`-m601'
+     Generate code for PowerPC 601.
+
+`-mppc, -mppc32, -m603, -m604'
+     Generate code for PowerPC 603/604.
+
+`-m403, -m405'
+     Generate code for PowerPC 403/405.
+
+`-m440'
+     Generate code for PowerPC 440.  BookE and some 405 instructions.
+
+`-m7400, -m7410, -m7450, -m7455'
+     Generate code for PowerPC 7400/7410/7450/7455.
+
+`-mppc64, -m620'
+     Generate code for PowerPC 620/625/630.
+
+`-mppc64bridge'
+     Generate code for PowerPC 64, including bridge insns.
+
+`-mbooke64'
+     Generate code for 64-bit BookE.
+
+`-mbooke, mbooke32'
+     Generate code for 32-bit BookE.
+
+`-me300'
+     Generate code for PowerPC e300 family.
+
+`-maltivec'
+     Generate code for processors with AltiVec instructions.
+
+`-mpower4'
+     Generate code for Power4 architecture.
+
+`-mpower5'
+     Generate code for Power5 architecture.
+
+`-mcom'
+     Generate code Power/PowerPC common instructions.
+
+`-many'
+     Generate code for any architecture (PWR/PWRX/PPC).
+
+`-mregnames'
+     Allow symbolic names for registers.
+
+`-mno-regnames'
+     Do not allow symbolic names for registers.
+
+`-mrelocatable'
+     Support for GCC's -mrelocatble option.
+
+`-mrelocatable-lib'
+     Support for GCC's -mrelocatble-lib option.
+
+`-memb'
+     Set PPC_EMB bit in ELF flags.
+
+`-mlittle, -mlittle-endian'
+     Generate code for a little endian machine.
+
+`-mbig, -mbig-endian'
+     Generate code for a big endian machine.
+
+`-msolaris'
+     Generate code for Solaris.
+
+`-mno-solaris'
+     Do not generate code for Solaris.
+
+
+File: as.info,  Node: PowerPC-Pseudo,  Prev: PowerPC-Opts,  Up: PPC-Dependent
+
+8.25.2 PowerPC Assembler Directives
+-----------------------------------
+
+A number of assembler directives are available for PowerPC.  The
+following table is far from complete.
+
+`.machine "string"'
+     This directive allows you to change the machine for which code is
+     generated.  `"string"' may be any of the -m cpu selection options
+     (without the -m) enclosed in double quotes, `"push"', or `"pop"'.
+     `.machine "push"' saves the currently selected cpu, which may be
+     restored with `.machine "pop"'.
+
+
+File: as.info,  Node: SH-Dependent,  Next: SH64-Dependent,  Prev: MSP430-Dependent,  Up: Machine Dependencies
+
+8.26 Renesas / SuperH SH Dependent Features
+===========================================
+
+* Menu:
+
+* SH Options::              Options
+* SH Syntax::               Syntax
+* SH Floating Point::       Floating Point
+* SH Directives::           SH Machine Directives
+* SH Opcodes::              Opcodes
+
+
+File: as.info,  Node: SH Options,  Next: SH Syntax,  Up: SH-Dependent
+
+8.26.1 Options
+--------------
+
+`as' has following command-line options for the Renesas (formerly
+Hitachi) / SuperH SH family.
+
+`--little'
+     Generate little endian code.
+
+`--big'
+     Generate big endian code.
+
+`--relax'
+     Alter jump instructions for long displacements.
+
+`--small'
+     Align sections to 4 byte boundaries, not 16.
+
+`--dsp'
+     Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`--renesas'
+     Disable optimization with section symbol for compatibility with
+     Renesas assembler.
+
+`--allow-reg-prefix'
+     Allow '$' as a register name prefix.
+
+`--isa=sh4 | sh4a'
+     Specify the sh4 or sh4a instruction set.
+
+`--isa=dsp'
+     Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`--isa=fp'
+     Enable sh2e, sh3e, sh4, and sh4a insn sets.
+
+`--isa=all'
+     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+
+
+
+File: as.info,  Node: SH Syntax,  Next: SH Floating Point,  Prev: SH Options,  Up: SH-Dependent
+
+8.26.2 Syntax
+-------------
+
+* Menu:
+
+* SH-Chars::                Special Characters
+* SH-Regs::                 Register Names
+* SH-Addressing::           Addressing Modes
+
+
+File: as.info,  Node: SH-Chars,  Next: SH-Regs,  Up: SH Syntax
+
+8.26.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+   You can use `;' instead of a newline to separate statements.
+
+   Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info,  Node: SH-Regs,  Next: SH-Addressing,  Prev: SH-Chars,  Up: SH Syntax
+
+8.26.2.2 Register Names
+.......................
+
+You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5',
+`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to
+refer to the SH registers.
+
+   The SH also has these control registers:
+
+`pr'
+     procedure register (holds return address)
+
+`pc'
+     program counter
+
+`mach'
+`macl'
+     high and low multiply accumulator registers
+
+`sr'
+     status register
+
+`gbr'
+     global base register
+
+`vbr'
+     vector base register (for interrupt vectors)
+
+
+File: as.info,  Node: SH-Addressing,  Prev: SH-Regs,  Up: SH Syntax
+
+8.26.2.3 Addressing Modes
+.........................
+
+`as' understands the following addressing modes for the SH.  `RN' in
+the following refers to any of the numbered registers, but _not_ the
+control registers.
+
+`RN'
+     Register direct
+
+`@RN'
+     Register indirect
+
+`@-RN'
+     Register indirect with pre-decrement
+
+`@RN+'
+     Register indirect with post-increment
+
+`@(DISP, RN)'
+     Register indirect with displacement
+
+`@(R0, RN)'
+     Register indexed
+
+`@(DISP, GBR)'
+     `GBR' offset
+
+`@(R0, GBR)'
+     GBR indexed
+
+`ADDR'
+`@(DISP, PC)'
+     PC relative address (for branch or for addressing memory).  The
+     `as' implementation allows you to use the simpler form ADDR
+     anywhere a PC relative address is called for; the alternate form
+     is supported for compatibility with other assemblers.
+
+`#IMM'
+     Immediate data
+
+
+File: as.info,  Node: SH Floating Point,  Next: SH Directives,  Prev: SH Syntax,  Up: SH-Dependent
+
+8.26.3 Floating Point
+---------------------
+
+SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
+SH groups can use `.float' directive to generate IEEE floating-point
+numbers.
+
+   SH2E and SH3E support single-precision floating point calculations as
+well as entirely PCAPI compatible emulation of double-precision
+floating point calculations. SH2E and SH3E instructions are a subset of
+the floating point calculations conforming to the IEEE754 standard.
+
+   In addition to single-precision and double-precision floating-point
+operation capability, the on-chip FPU of SH4 has a 128-bit graphic
+engine that enables 32-bit floating-point data to be processed 128 bits
+at a time. It also supports 4 * 4 array operations and inner product
+operations. Also, a superscalar architecture is employed that enables
+simultaneous execution of two instructions (including FPU
+instructions), providing performance of up to twice that of
+conventional architectures at the same frequency.
+
+
+File: as.info,  Node: SH Directives,  Next: SH Opcodes,  Prev: SH Floating Point,  Up: SH-Dependent
+
+8.26.4 SH Machine Directives
+----------------------------
+
+`uaword'
+`ualong'
+     `as' will issue a warning when a misaligned `.word' or `.long'
+     directive is used.  You may use `.uaword' or `.ualong' to indicate
+     that the value is intentionally misaligned.
+
+
+File: as.info,  Node: SH Opcodes,  Prev: SH Directives,  Up: SH-Dependent
+
+8.26.5 Opcodes
+--------------
+
+For detailed information on the SH machine instruction set, see
+`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core
+Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH).
+
+   `as' implements all the standard SH opcodes.  No additional
+pseudo-instructions are needed on this family.  Note, however, that
+because `as' supports a simpler form of PC-relative addressing, you may
+simply write (for example)
+
+     mov.l  bar,r0
+
+where other assemblers might require an explicit displacement to `bar'
+from the program counter:
+
+     mov.l  @(DISP, PC)
+
+   Here is a summary of SH opcodes:
+
+     Legend:
+     Rn        a numbered register
+     Rm        another numbered register
+     #imm      immediate data
+     disp      displacement
+     disp8     8-bit displacement
+     disp12    12-bit displacement
+
+     add #imm,Rn                    lds.l @Rn+,PR
+     add Rm,Rn                      mac.w @Rm+,@Rn+
+     addc Rm,Rn                     mov #imm,Rn
+     addv Rm,Rn                     mov Rm,Rn
+     and #imm,R0                    mov.b Rm,@(R0,Rn)
+     and Rm,Rn                      mov.b Rm,@-Rn
+     and.b #imm,@(R0,GBR)           mov.b Rm,@Rn
+     bf disp8                       mov.b @(disp,Rm),R0
+     bra disp12                     mov.b @(disp,GBR),R0
+     bsr disp12                     mov.b @(R0,Rm),Rn
+     bt disp8                       mov.b @Rm+,Rn
+     clrmac                         mov.b @Rm,Rn
+     clrt                           mov.b R0,@(disp,Rm)
+     cmp/eq #imm,R0                 mov.b R0,@(disp,GBR)
+     cmp/eq Rm,Rn                   mov.l Rm,@(disp,Rn)
+     cmp/ge Rm,Rn                   mov.l Rm,@(R0,Rn)
+     cmp/gt Rm,Rn                   mov.l Rm,@-Rn
+     cmp/hi Rm,Rn                   mov.l Rm,@Rn
+     cmp/hs Rm,Rn                   mov.l @(disp,Rn),Rm
+     cmp/pl Rn                      mov.l @(disp,GBR),R0
+     cmp/pz Rn                      mov.l @(disp,PC),Rn
+     cmp/str Rm,Rn                  mov.l @(R0,Rm),Rn
+     div0s Rm,Rn                    mov.l @Rm+,Rn
+     div0u                          mov.l @Rm,Rn
+     div1 Rm,Rn                     mov.l R0,@(disp,GBR)
+     exts.b Rm,Rn                   mov.w Rm,@(R0,Rn)
+     exts.w Rm,Rn                   mov.w Rm,@-Rn
+     extu.b Rm,Rn                   mov.w Rm,@Rn
+     extu.w Rm,Rn                   mov.w @(disp,Rm),R0
+     jmp @Rn                        mov.w @(disp,GBR),R0
+     jsr @Rn                        mov.w @(disp,PC),Rn
+     ldc Rn,GBR                     mov.w @(R0,Rm),Rn
+     ldc Rn,SR                      mov.w @Rm+,Rn
+     ldc Rn,VBR                     mov.w @Rm,Rn
+     ldc.l @Rn+,GBR                 mov.w R0,@(disp,Rm)
+     ldc.l @Rn+,SR                  mov.w R0,@(disp,GBR)
+     ldc.l @Rn+,VBR                 mova @(disp,PC),R0
+     lds Rn,MACH                    movt Rn
+     lds Rn,MACL                    muls Rm,Rn
+     lds Rn,PR                      mulu Rm,Rn
+     lds.l @Rn+,MACH                neg Rm,Rn
+     lds.l @Rn+,MACL                negc Rm,Rn
+
+     nop                            stc VBR,Rn
+     not Rm,Rn                      stc.l GBR,@-Rn
+     or #imm,R0                     stc.l SR,@-Rn
+     or Rm,Rn                       stc.l VBR,@-Rn
+     or.b #imm,@(R0,GBR)            sts MACH,Rn
+     rotcl Rn                       sts MACL,Rn
+     rotcr Rn                       sts PR,Rn
+     rotl Rn                        sts.l MACH,@-Rn
+     rotr Rn                        sts.l MACL,@-Rn
+     rte                            sts.l PR,@-Rn
+     rts                            sub Rm,Rn
+     sett                           subc Rm,Rn
+     shal Rn                        subv Rm,Rn
+     shar Rn                        swap.b Rm,Rn
+     shll Rn                        swap.w Rm,Rn
+     shll16 Rn                      tas.b @Rn
+     shll2 Rn                       trapa #imm
+     shll8 Rn                       tst #imm,R0
+     shlr Rn                        tst Rm,Rn
+     shlr16 Rn                      tst.b #imm,@(R0,GBR)
+     shlr2 Rn                       xor #imm,R0
+     shlr8 Rn                       xor Rm,Rn
+     sleep                          xor.b #imm,@(R0,GBR)
+     stc GBR,Rn                     xtrct Rm,Rn
+     stc SR,Rn
+
+
+File: as.info,  Node: SH64-Dependent,  Next: PDP-11-Dependent,  Prev: SH-Dependent,  Up: Machine Dependencies
+
+8.27 SuperH SH64 Dependent Features
+===================================
+
+* Menu:
+
+* SH64 Options::              Options
+* SH64 Syntax::               Syntax
+* SH64 Directives::           SH64 Machine Directives
+* SH64 Opcodes::              Opcodes
+
+
+File: as.info,  Node: SH64 Options,  Next: SH64 Syntax,  Up: SH64-Dependent
+
+8.27.1 Options
+--------------
+
+`-isa=sh4 | sh4a'
+     Specify the sh4 or sh4a instruction set.
+
+`-isa=dsp'
+     Enable sh-dsp insns, and disable sh3e / sh4 insns.
+
+`-isa=fp'
+     Enable sh2e, sh3e, sh4, and sh4a insn sets.
+
+`-isa=all'
+     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
+
+`-isa=shmedia | -isa=shcompact'
+     Specify the default instruction set.  `SHmedia' specifies the
+     32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes
+     compatible with previous SH families.  The default depends on the
+     ABI selected; the default for the 64-bit ABI is SHmedia, and the
+     default for the 32-bit ABI is SHcompact.  If neither the ABI nor
+     the ISA is specified, the default is 32-bit SHcompact.
+
+     Note that the `.mode' pseudo-op is not permitted if the ISA is not
+     specified on the command line.
+
+`-abi=32 | -abi=64'
+     Specify the default ABI.  If the ISA is specified and the ABI is
+     not, the default ABI depends on the ISA, with SHmedia defaulting
+     to 64-bit and SHcompact defaulting to 32-bit.
+
+     Note that the `.abi' pseudo-op is not permitted if the ABI is not
+     specified on the command line.  When the ABI is specified on the
+     command line, any `.abi' pseudo-ops in the source must match it.
+
+`-shcompact-const-crange'
+     Emit code-range descriptors for constants in SHcompact code
+     sections.
+
+`-no-mix'
+     Disallow SHmedia code in the same section as constants and
+     SHcompact code.
+
+`-no-expand'
+     Do not expand MOVI, PT, PTA or PTB instructions.
+
+`-expand-pt32'
+     With -abi=64, expand PT, PTA and PTB instructions to 32 bits only.
+
+
+
+File: as.info,  Node: SH64 Syntax,  Next: SH64 Directives,  Prev: SH64 Options,  Up: SH64-Dependent
+
+8.27.2 Syntax
+-------------
+
+* Menu:
+
+* SH64-Chars::                Special Characters
+* SH64-Regs::                 Register Names
+* SH64-Addressing::           Addressing Modes
+
+
+File: as.info,  Node: SH64-Chars,  Next: SH64-Regs,  Up: SH64 Syntax
+
+8.27.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+   You can use `;' instead of a newline to separate statements.
+
+   Since `$' has no special meaning, you may use it in symbol names.
+
+
+File: as.info,  Node: SH64-Regs,  Next: SH64-Addressing,  Prev: SH64-Chars,  Up: SH64 Syntax
+
+8.27.2.2 Register Names
+.......................
+
+You can use the predefined symbols `r0' through `r63' to refer to the
+SH64 general registers, `cr0' through `cr63' for control registers,
+`tr0' through `tr7' for target address registers, `fr0' through `fr63'
+for single-precision floating point registers, `dr0' through `dr62'
+(even numbered registers only) for double-precision floating point
+registers, `fv0' through `fv60' (multiples of four only) for
+single-precision floating point vectors, `fp0' through `fp62' (even
+numbered registers only) for single-precision floating point pairs,
+`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of
+single-precision floating point registers, `pc' for the program
+counter, and `fpscr' for the floating point status and control register.
+
+   You can also refer to the control registers by the mnemonics `sr',
+`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc',
+`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'.
+
+
+File: as.info,  Node: SH64-Addressing,  Prev: SH64-Regs,  Up: SH64 Syntax
+
+8.27.2.3 Addressing Modes
+.........................
+
+SH64 operands consist of either a register or immediate value.  The
+immediate value can be a constant or label reference (or portion of a
+label reference), as in this example:
+
+     	movi	4,r2
+     	pt	function, tr4
+     	movi	(function >> 16) & 65535,r0
+     	shori	function & 65535, r0
+     	ld.l	r0,4,r0
+
+   Instruction label references can reference labels in either SHmedia
+or SHcompact.  To differentiate between the two, labels in SHmedia
+sections will always have the least significant bit set (i.e. they will
+be odd), which SHcompact labels will have the least significant bit
+reset (i.e. they will be even).  If you need to reference the actual
+address of a label, you can use the `datalabel' modifier, as in this
+example:
+
+     	.long	function
+     	.long	datalabel function
+
+   In that example, the first longword may or may not have the least
+significant bit set depending on whether the label is an SHmedia label
+or an SHcompact label.  The second longword will be the actual address
+of the label, regardless of what type of label it is.
+
+
+File: as.info,  Node: SH64 Directives,  Next: SH64 Opcodes,  Prev: SH64 Syntax,  Up: SH64-Dependent
+
+8.27.3 SH64 Machine Directives
+------------------------------
+
+In addition to the SH directives, the SH64 provides the following
+directives:
+
+`.mode [shmedia|shcompact]'
+`.isa [shmedia|shcompact]'
+     Specify the ISA for the following instructions (the two directives
+     are equivalent).  Note that programs such as `objdump' rely on
+     symbolic labels to determine when such mode switches occur (by
+     checking the least significant bit of the label's address), so
+     such mode/isa changes should always be followed by a label (in
+     practice, this is true anyway).  Note that you cannot use these
+     directives if you didn't specify an ISA on the command line.
+
+`.abi [32|64]'
+     Specify the ABI for the following instructions.  Note that you
+     cannot use this directive unless you specified an ABI on the
+     command line, and the ABIs specified must match.
+
+`.uaquad'
+     Like .uaword and .ualong, this allows you to specify an
+     intentionally unaligned quadword (64 bit word).
+
+
+
+File: as.info,  Node: SH64 Opcodes,  Prev: SH64 Directives,  Up: SH64-Dependent
+
+8.27.4 Opcodes
+--------------
+
+For detailed information on the SH64 machine instruction set, see
+`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.).
+
+   `as' implements all the standard SH64 opcodes.  In addition, the
+following pseudo-opcodes may be expanded into one or more alternate
+opcodes:
+
+`movi'
+     If the value doesn't fit into a standard `movi' opcode, `as' will
+     replace the `movi' with a sequence of `movi' and `shori' opcodes.
+
+`pt'
+     This expands to a sequence of `movi' and `shori' opcode, followed
+     by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on
+     the label referenced.
+
+
+
+File: as.info,  Node: Sparc-Dependent,  Next: TIC54X-Dependent,  Prev: PPC-Dependent,  Up: Machine Dependencies
+
+8.28 SPARC Dependent Features
+=============================
+
+* Menu:
+
+* Sparc-Opts::                  Options
+* Sparc-Aligned-Data::		Option to enforce aligned data
+* Sparc-Float::                 Floating Point
+* Sparc-Directives::            Sparc Machine Directives
+
+
+File: as.info,  Node: Sparc-Opts,  Next: Sparc-Aligned-Data,  Up: Sparc-Dependent
+
+8.28.1 Options
+--------------
+
+The SPARC chip family includes several successive levels, using the same
+core instruction set, but including a few additional instructions at
+each level.  There are exceptions to this however.  For details on what
+instructions each variant supports, please see the chip's architecture
+reference manual.
+
+   By default, `as' assumes the core instruction set (SPARC v6), but
+"bumps" the architecture level as needed: it switches to successively
+higher architectures as it encounters instructions that only exist in
+the higher levels.
+
+   If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump
+passed sparclite by default, an option must be passed to enable the v9
+instructions.
+
+   GAS treats sparclite as being compatible with v8, unless an
+architecture is explicitly requested.  SPARC v9 is always incompatible
+with sparclite.
+
+`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite'
+`-Av8plus | -Av8plusa | -Av9 | -Av9a'
+     Use one of the `-A' options to select one of the SPARC
+     architectures explicitly.  If you select an architecture
+     explicitly, `as' reports a fatal error if it encounters an
+     instruction or feature requiring an incompatible or higher level.
+
+     `-Av8plus' and `-Av8plusa' select a 32 bit environment.
+
+     `-Av9' and `-Av9a' select a 64 bit environment and are not
+     available unless GAS is explicitly configured with 64 bit
+     environment support.
+
+     `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with
+     UltraSPARC extensions.
+
+`-xarch=v8plus | -xarch=v8plusa'
+     For compatibility with the Solaris v9 assembler.  These options are
+     equivalent to -Av8plus and -Av8plusa, respectively.
+
+`-bump'
+     Warn whenever it is necessary to switch to another level.  If an
+     architecture level is explicitly requested, GAS will not issue
+     warnings until that level is reached, and will then bump the level
+     as required (except between incompatible levels).
+
+`-32 | -64'
+     Select the word size, either 32 bits or 64 bits.  These options
+     are only available with the ELF object file format, and require
+     that the necessary BFD support has been included.
+
+
+File: as.info,  Node: Sparc-Aligned-Data,  Next: Sparc-Float,  Prev: Sparc-Opts,  Up: Sparc-Dependent
+
+8.28.2 Enforcing aligned data
+-----------------------------
+
+SPARC GAS normally permits data to be misaligned.  For example, it
+permits the `.long' pseudo-op to be used on a byte boundary.  However,
+the native SunOS and Solaris assemblers issue an error when they see
+misaligned data.
+
+   You can use the `--enforce-aligned-data' option to make SPARC GAS
+also issue an error about misaligned data, just as the SunOS and Solaris
+assemblers do.
+
+   The `--enforce-aligned-data' option is not the default because gcc
+issues misaligned data pseudo-ops when it initializes certain packed
+data structures (structures defined using the `packed' attribute).  You
+may have to assemble with GAS in order to initialize packed data
+structures in your own code.
+
+
+File: as.info,  Node: Sparc-Float,  Next: Sparc-Directives,  Prev: Sparc-Aligned-Data,  Up: Sparc-Dependent
+
+8.28.3 Floating Point
+---------------------
+
+The Sparc uses IEEE floating-point numbers.
+
+
+File: as.info,  Node: Sparc-Directives,  Prev: Sparc-Float,  Up: Sparc-Dependent
+
+8.28.4 Sparc Machine Directives
+-------------------------------
+
+The Sparc version of `as' supports the following additional machine
+directives:
+
+`.align'
+     This must be followed by the desired alignment in bytes.
+
+`.common'
+     This must be followed by a symbol name, a positive number, and
+     `"bss"'.  This behaves somewhat like `.comm', but the syntax is
+     different.
+
+`.half'
+     This is functionally identical to `.short'.
+
+`.nword'
+     On the Sparc, the `.nword' directive produces native word sized
+     value, ie. if assembling with -32 it is equivalent to `.word', if
+     assembling with -64 it is equivalent to `.xword'.
+
+`.proc'
+     This directive is ignored.  Any text following it on the same line
+     is also ignored.
+
+`.register'
+     This directive declares use of a global application or system
+     register.  It must be followed by a register name %g2, %g3, %g6 or
+     %g7, comma and the symbol name for that register.  If symbol name
+     is `#scratch', it is a scratch register, if it is `#ignore', it
+     just suppresses any errors about using undeclared global register,
+     but does not emit any information about it into the object file.
+     This can be useful e.g. if you save the register before use and
+     restore it after.
+
+`.reserve'
+     This must be followed by a symbol name, a positive number, and
+     `"bss"'.  This behaves somewhat like `.lcomm', but the syntax is
+     different.
+
+`.seg'
+     This must be followed by `"text"', `"data"', or `"data1"'.  It
+     behaves like `.text', `.data', or `.data 1'.
+
+`.skip'
+     This is functionally identical to the `.space' directive.
+
+`.word'
+     On the Sparc, the `.word' directive produces 32 bit values,
+     instead of the 16 bit values it produces on many other machines.
+
+`.xword'
+     On the Sparc V9 processor, the `.xword' directive produces 64 bit
+     values.
+
+
+File: as.info,  Node: TIC54X-Dependent,  Next: V850-Dependent,  Prev: Sparc-Dependent,  Up: Machine Dependencies
+
+8.29 TIC54X Dependent Features
+==============================
+
+* Menu:
+
+* TIC54X-Opts::              Command-line Options
+* TIC54X-Block::             Blocking
+* TIC54X-Env::               Environment Settings
+* TIC54X-Constants::         Constants Syntax
+* TIC54X-Subsyms::           String Substitution
+* TIC54X-Locals::            Local Label Syntax
+* TIC54X-Builtins::          Builtin Assembler Math Functions
+* TIC54X-Ext::               Extended Addressing Support
+* TIC54X-Directives::        Directives
+* TIC54X-Macros::            Macro Features
+* TIC54X-MMRegs::            Memory-mapped Registers
+
+
+File: as.info,  Node: TIC54X-Opts,  Next: TIC54X-Block,  Up: TIC54X-Dependent
+
+8.29.1 Options
+--------------
+
+The TMS320C54x version of `as' has a few machine-dependent options.
+
+   You can use the `-mfar-mode' option to enable extended addressing
+mode.  All addresses will be assumed to be > 16 bits, and the
+appropriate relocation types will be used.  This option is equivalent
+to using the `.far_mode' directive in the assembly code.  If you do not
+use the `-mfar-mode' option, all references will be assumed to be 16
+bits.  This option may be abbreviated to `-mf'.
+
+   You can use the `-mcpu' option to specify a particular CPU.  This
+option is equivalent to using the `.version' directive in the assembly
+code.  For recognized CPU codes, see *Note `.version':
+TIC54X-Directives.  The default CPU version is `542'.
+
+   You can use the `-merrors-to-file' option to redirect error output
+to a file (this provided for those deficient environments which don't
+provide adequate output redirection).  This option may be abbreviated to
+`-me'.
+
+
+File: as.info,  Node: TIC54X-Block,  Next: TIC54X-Env,  Prev: TIC54X-Opts,  Up: TIC54X-Dependent
+
+8.29.2 Blocking
+---------------
+
+A blocked section or memory block is guaranteed not to cross the
+blocking boundary (usually a page, or 128 words) if it is smaller than
+the blocking size, or to start on a page boundary if it is larger than
+the blocking size.
+
+
+File: as.info,  Node: TIC54X-Env,  Next: TIC54X-Constants,  Prev: TIC54X-Block,  Up: TIC54X-Dependent
+
+8.29.3 Environment Settings
+---------------------------
+
+`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added
+to the list of directories normally searched for source and include
+files.  `C54XDSP_DIR' will override `A_DIR'.
+
+
+File: as.info,  Node: TIC54X-Constants,  Next: TIC54X-Subsyms,  Prev: TIC54X-Env,  Up: TIC54X-Dependent
+
+8.29.4 Constants Syntax
+-----------------------
+
+The TIC54X version of `as' allows the following additional constant
+formats, using a suffix to indicate the radix:
+
+     Binary                  `000000B, 011000b'
+     Octal                   `10Q, 224q'
+     Hexadecimal             `45h, 0FH'
+
+
+File: as.info,  Node: TIC54X-Subsyms,  Next: TIC54X-Locals,  Prev: TIC54X-Constants,  Up: TIC54X-Dependent
+
+8.29.5 String Substitution
+--------------------------
+
+A subset of allowable symbols (which we'll call subsyms) may be assigned
+arbitrary string values.  This is roughly equivalent to C preprocessor
+#define macros.  When `as' encounters one of these symbols, the symbol
+is replaced in the input stream by its string value.  Subsym names
+*must* begin with a letter.
+
+   Subsyms may be defined using the `.asg' and `.eval' directives
+(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives.
+
+   Expansion is recursive until a previously encountered symbol is
+seen, at which point substitution stops.
+
+   In this example, x is replaced with SYM2; SYM2 is replaced with
+SYM1, and SYM1 is replaced with x.  At this point, x has already been
+encountered and the substitution stops.
+
+      .asg   "x",SYM1
+      .asg   "SYM1",SYM2
+      .asg   "SYM2",x
+      add    x,a             ; final code assembled is "add  x, a"
+
+   Macro parameters are converted to subsyms; a side effect of this is
+the normal `as' '\ARG' dereferencing syntax is unnecessary.  Subsyms
+defined within a macro will have global scope, unless the `.var'
+directive is used to identify the subsym as a local macro variable
+*note `.var': TIC54X-Directives.
+
+   Substitution may be forced in situations where replacement might be
+ambiguous by placing colons on either side of the subsym.  The following
+code:
+
+      .eval  "10",x
+     LAB:X:  add     #x, a
+
+   When assembled becomes:
+
+     LAB10  add     #10, a
+
+   Smaller parts of the string assigned to a subsym may be accessed with
+the following syntax:
+
+``:SYMBOL(CHAR_INDEX):''
+     Evaluates to a single-character string, the character at
+     CHAR_INDEX.
+
+``:SYMBOL(START,LENGTH):''
+     Evaluates to a substring of SYMBOL beginning at START with length
+     LENGTH.
+
+
+File: as.info,  Node: TIC54X-Locals,  Next: TIC54X-Builtins,  Prev: TIC54X-Subsyms,  Up: TIC54X-Dependent
+
+8.29.6 Local Labels
+-------------------
+
+Local labels may be defined in two ways:
+
+   * $N, where N is a decimal number between 0 and 9
+
+   * LABEL?, where LABEL is any legal symbol name.
+
+   Local labels thus defined may be redefined or automatically
+generated.  The scope of a local label is based on when it may be
+undefined or reset.  This happens when one of the following situations
+is encountered:
+
+   * .newblock directive *note `.newblock': TIC54X-Directives.
+
+   * The current section is changed (.sect, .text, or .data)
+
+   * Entering or leaving an included file
+
+   * The macro scope where the label was defined is exited
+
+
+File: as.info,  Node: TIC54X-Builtins,  Next: TIC54X-Ext,  Prev: TIC54X-Locals,  Up: TIC54X-Dependent
+
+8.29.7 Math Builtins
+--------------------
+
+The following built-in functions may be used to generate a
+floating-point value.  All return a floating-point value except `$cvi',
+`$int', and `$sgn', which return an integer value.
+
+``$acos(EXPR)''
+     Returns the floating point arccosine of EXPR.
+
+``$asin(EXPR)''
+     Returns the floating point arcsine of EXPR.
+
+``$atan(EXPR)''
+     Returns the floating point arctangent of EXPR.
+
+``$atan2(EXPR1,EXPR2)''
+     Returns the floating point arctangent of EXPR1 / EXPR2.
+
+``$ceil(EXPR)''
+     Returns the smallest integer not less than EXPR as floating point.
+
+``$cosh(EXPR)''
+     Returns the floating point hyperbolic cosine of EXPR.
+
+``$cos(EXPR)''
+     Returns the floating point cosine of EXPR.
+
+``$cvf(EXPR)''
+     Returns the integer value EXPR converted to floating-point.
+
+``$cvi(EXPR)''
+     Returns the floating point value EXPR converted to integer.
+
+``$exp(EXPR)''
+     Returns the floating point value e ^ EXPR.
+
+``$fabs(EXPR)''
+     Returns the floating point absolute value of EXPR.
+
+``$floor(EXPR)''
+     Returns the largest integer that is not greater than EXPR as
+     floating point.
+
+``$fmod(EXPR1,EXPR2)''
+     Returns the floating point remainder of EXPR1 / EXPR2.
+
+``$int(EXPR)''
+     Returns 1 if EXPR evaluates to an integer, zero otherwise.
+
+``$ldexp(EXPR1,EXPR2)''
+     Returns the floating point value EXPR1 * 2 ^ EXPR2.
+
+``$log10(EXPR)''
+     Returns the base 10 logarithm of EXPR.
+
+``$log(EXPR)''
+     Returns the natural logarithm of EXPR.
+
+``$max(EXPR1,EXPR2)''
+     Returns the floating point maximum of EXPR1 and EXPR2.
+
+``$min(EXPR1,EXPR2)''
+     Returns the floating point minimum of EXPR1 and EXPR2.
+
+``$pow(EXPR1,EXPR2)''
+     Returns the floating point value EXPR1 ^ EXPR2.
+
+``$round(EXPR)''
+     Returns the nearest integer to EXPR as a floating point number.
+
+``$sgn(EXPR)''
+     Returns -1, 0, or 1 based on the sign of EXPR.
+
+``$sin(EXPR)''
+     Returns the floating point sine of EXPR.
+
+``$sinh(EXPR)''
+     Returns the floating point hyperbolic sine of EXPR.
+
+``$sqrt(EXPR)''
+     Returns the floating point square root of EXPR.
+
+``$tan(EXPR)''
+     Returns the floating point tangent of EXPR.
+
+``$tanh(EXPR)''
+     Returns the floating point hyperbolic tangent of EXPR.
+
+``$trunc(EXPR)''
+     Returns the integer value of EXPR truncated towards zero as
+     floating point.
+
+
+
+File: as.info,  Node: TIC54X-Ext,  Next: TIC54X-Directives,  Prev: TIC54X-Builtins,  Up: TIC54X-Dependent
+
+8.29.8 Extended Addressing
+--------------------------
+
+The `LDX' pseudo-op is provided for loading the extended addressing bits
+of a label or address.  For example, if an address `_label' resides in
+extended program memory, the value of `_label' may be loaded as follows:
+      ldx     #_label,16,a    ; loads extended bits of _label
+      or      #_label,a       ; loads lower 16 bits of _label
+      bacc    a               ; full address is in accumulator A
+
+
+File: as.info,  Node: TIC54X-Directives,  Next: TIC54X-Macros,  Prev: TIC54X-Ext,  Up: TIC54X-Dependent
+
+8.29.9 Directives
+-----------------
+
+`.align [SIZE]'
+`.even'
+     Align the section program counter on the next boundary, based on
+     SIZE.  SIZE may be any power of 2.  `.even' is equivalent to
+     `.align' with a SIZE of 2.
+    `1'
+          Align SPC to word boundary
+
+    `2'
+          Align SPC to longword boundary (same as .even)
+
+    `128'
+          Align SPC to page boundary
+
+`.asg STRING, NAME'
+     Assign NAME the string STRING.  String replacement is performed on
+     STRING before assignment.
+
+`.eval STRING, NAME'
+     Evaluate the contents of string STRING and assign the result as a
+     string to the subsym NAME.  String replacement is performed on
+     STRING before assignment.
+
+`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
+     Reserve space for SYMBOL in the .bss section.  SIZE is in words.
+     If present, BLOCKING_FLAG indicates the allocated space should be
+     aligned on a page boundary if it would otherwise cross a page
+     boundary.  If present, ALIGNMENT_FLAG causes the assembler to
+     allocate SIZE on a long word boundary.
+
+`.byte VALUE [,...,VALUE_N]'
+`.ubyte VALUE [,...,VALUE_N]'
+`.char VALUE [,...,VALUE_N]'
+`.uchar VALUE [,...,VALUE_N]'
+     Place one or more bytes into consecutive words of the current
+     section.  The upper 8 bits of each word is zero-filled.  If a
+     label is used, it points to the word allocated for the first byte
+     encountered.
+
+`.clink ["SECTION_NAME"]'
+     Set STYP_CLINK flag for this section, which indicates to the
+     linker that if no symbols from this section are referenced, the
+     section should not be included in the link.  If SECTION_NAME is
+     omitted, the current section is used.
+
+`.c_mode'
+     TBD.
+
+`.copy "FILENAME" | FILENAME'
+`.include "FILENAME" | FILENAME'
+     Read source statements from FILENAME.  The normal include search
+     path is used.  Normally .copy will cause statements from the
+     included file to be printed in the assembly listing and .include
+     will not, but this distinction is not currently implemented.
+
+`.data'
+     Begin assembling code into the .data section.
+
+`.double VALUE [,...,VALUE_N]'
+`.ldouble VALUE [,...,VALUE_N]'
+`.float VALUE [,...,VALUE_N]'
+`.xfloat VALUE [,...,VALUE_N]'
+     Place an IEEE single-precision floating-point representation of
+     one or more floating-point values into the current section.  All
+     but `.xfloat' align the result on a longword boundary.  Values are
+     stored most-significant word first.
+
+`.drlist'
+`.drnolist'
+     Control printing of directives to the listing file.  Ignored.
+
+`.emsg STRING'
+`.mmsg STRING'
+`.wmsg STRING'
+     Emit a user-defined error, message, or warning, respectively.
+
+`.far_mode'
+     Use extended addressing when assembling statements.  This should
+     appear only once per file, and is equivalent to the -mfar-mode
+     option *note `-mfar-mode': TIC54X-Opts.
+
+`.fclist'
+`.fcnolist'
+     Control printing of false conditional blocks to the listing file.
+
+`.field VALUE [,SIZE]'
+     Initialize a bitfield of SIZE bits in the current section.  If
+     VALUE is relocatable, then SIZE must be 16.  SIZE defaults to 16
+     bits.  If VALUE does not fit into SIZE bits, the value will be
+     truncated.  Successive `.field' directives will pack starting at
+     the current word, filling the most significant bits first, and
+     aligning to the start of the next word if the field size does not
+     fit into the space remaining in the current word.  A `.align'
+     directive with an operand of 1 will force the next `.field'
+     directive to begin packing into a new word.  If a label is used, it
+     points to the word that contains the specified field.
+
+`.global SYMBOL [,...,SYMBOL_N]'
+`.def SYMBOL [,...,SYMBOL_N]'
+`.ref SYMBOL [,...,SYMBOL_N]'
+     `.def' nominally identifies a symbol defined in the current file
+     and availalbe to other files.  `.ref' identifies a symbol used in
+     the current file but defined elsewhere.  Both map to the standard
+     `.global' directive.
+
+`.half VALUE [,...,VALUE_N]'
+`.uhalf VALUE [,...,VALUE_N]'
+`.short VALUE [,...,VALUE_N]'
+`.ushort VALUE [,...,VALUE_N]'
+`.int VALUE [,...,VALUE_N]'
+`.uint VALUE [,...,VALUE_N]'
+`.word VALUE [,...,VALUE_N]'
+`.uword VALUE [,...,VALUE_N]'
+     Place one or more values into consecutive words of the current
+     section.  If a label is used, it points to the word allocated for
+     the first value encountered.
+
+`.label SYMBOL'
+     Define a special SYMBOL to refer to the load time address of the
+     current section program counter.
+
+`.length'
+`.width'
+     Set the page length and width of the output listing file.  Ignored.
+
+`.list'
+`.nolist'
+     Control whether the source listing is printed.  Ignored.
+
+`.long VALUE [,...,VALUE_N]'
+`.ulong VALUE [,...,VALUE_N]'
+`.xlong VALUE [,...,VALUE_N]'
+     Place one or more 32-bit values into consecutive words in the
+     current section.  The most significant word is stored first.
+     `.long' and `.ulong' align the result on a longword boundary;
+     `xlong' does not.
+
+`.loop [COUNT]'
+`.break [CONDITION]'
+`.endloop'
+     Repeatedly assemble a block of code.  `.loop' begins the block, and
+     `.endloop' marks its termination.  COUNT defaults to 1024, and
+     indicates the number of times the block should be repeated.
+     `.break' terminates the loop so that assembly begins after the
+     `.endloop' directive.  The optional CONDITION will cause the loop
+     to terminate only if it evaluates to zero.
+
+`MACRO_NAME .macro [PARAM1][,...PARAM_N]'
+`[.mexit]'
+`.endm'
+     See the section on macros for more explanation (*Note
+     TIC54X-Macros::.
+
+`.mlib "FILENAME" | FILENAME'
+     Load the macro library FILENAME.  FILENAME must be an archived
+     library (BFD ar-compatible) of text files, expected to contain
+     only macro definitions.   The standard include search path is used.
+
+`.mlist'
+
+`.mnolist'
+     Control whether to include macro and loop block expansions in the
+     listing output.  Ignored.
+
+`.mmregs'
+     Define global symbolic names for the 'c54x registers.  Supposedly
+     equivalent to executing `.set' directives for each register with
+     its memory-mapped value, but in reality is provided only for
+     compatibility and does nothing.
+
+`.newblock'
+     This directive resets any TIC54X local labels currently defined.
+     Normal `as' local labels are unaffected.
+
+`.option OPTION_LIST'
+     Set listing options.  Ignored.
+
+`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]'
+     Designate SECTION_NAME for blocking.  Blocking guarantees that a
+     section will start on a page boundary (128 words) if it would
+     otherwise cross a page boundary.  Only initialized sections may be
+     designated with this directive.  See also *Note TIC54X-Block::.
+
+`.sect "SECTION_NAME"'
+     Define a named initialized section and make it the current section.
+
+`SYMBOL .set "VALUE"'
+`SYMBOL .equ "VALUE"'
+     Equate a constant VALUE to a SYMBOL, which is placed in the symbol
+     table.  SYMBOL may not be previously defined.
+
+`.space SIZE_IN_BITS'
+`.bes SIZE_IN_BITS'
+     Reserve the given number of bits in the current section and
+     zero-fill them.  If a label is used with `.space', it points to the
+     *first* word reserved.  With `.bes', the label points to the
+     *last* word reserved.
+
+`.sslist'
+`.ssnolist'
+     Controls the inclusion of subsym replacement in the listing
+     output.  Ignored.
+
+`.string "STRING" [,...,"STRING_N"]'
+`.pstring "STRING" [,...,"STRING_N"]'
+     Place 8-bit characters from STRING into the current section.
+     `.string' zero-fills the upper 8 bits of each word, while
+     `.pstring' puts two characters into each word, filling the
+     most-significant bits first.  Unused space is zero-filled.  If a
+     label is used, it points to the first word initialized.
+
+`[STAG] .struct [OFFSET]'
+`[NAME_1] element [COUNT_1]'
+`[NAME_2] element [COUNT_2]'
+`[TNAME] .tag STAGX [TCOUNT]'
+`...'
+`[NAME_N] element [COUNT_N]'
+`[SSIZE] .endstruct'
+`LABEL .tag [STAG]'
+     Assign symbolic offsets to the elements of a structure.  STAG
+     defines a symbol to use to reference the structure.  OFFSET
+     indicates a starting value to use for the first element
+     encountered; otherwise it defaults to zero.  Each element can have
+     a named offset, NAME, which is a symbol assigned the value of the
+     element's offset into the structure.  If STAG is missing, these
+     become global symbols.  COUNT adjusts the offset that many times,
+     as if `element' were an array.  `element' may be one of `.byte',
+     `.word', `.long', `.float', or any equivalent of those, and the
+     structure offset is adjusted accordingly.  `.field' and `.string'
+     are also allowed; the size of `.field' is one bit, and `.string'
+     is considered to be one word in size.  Only element descriptors,
+     structure/union tags, `.align' and conditional assembly directives
+     are allowed within `.struct'/`.endstruct'.  `.align' aligns member
+     offsets to word boundaries only.  SSIZE, if provided, will always
+     be assigned the size of the structure.
+
+     The `.tag' directive, in addition to being used to define a
+     structure/union element within a structure, may be used to apply a
+     structure to a symbol.  Once applied to LABEL, the individual
+     structure elements may be applied to LABEL to produce the desired
+     offsets using LABEL as the structure base.
+
+`.tab'
+     Set the tab size in the output listing.  Ignored.
+
+`[UTAG] .union'
+`[NAME_1] element [COUNT_1]'
+`[NAME_2] element [COUNT_2]'
+`[TNAME] .tag UTAGX[,TCOUNT]'
+`...'
+`[NAME_N] element [COUNT_N]'
+`[USIZE] .endstruct'
+`LABEL .tag [UTAG]'
+     Similar to `.struct', but the offset after each element is reset to
+     zero, and the USIZE is set to the maximum of all defined elements.
+     Starting offset for the union is always zero.
+
+`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]'
+     Reserve space for variables in a named, uninitialized section
+     (similar to .bss).  `.usect' allows definitions sections
+     independent of .bss.  SYMBOL points to the first location reserved
+     by this allocation.  The symbol may be used as a variable name.
+     SIZE is the allocated size in words.  BLOCKING_FLAG indicates
+     whether to block this section on a page boundary (128 words)
+     (*note TIC54X-Block::).  ALIGNMENT FLAG indicates whether the
+     section should be longword-aligned.
+
+`.var SYM[,..., SYM_N]'
+     Define a subsym to be a local variable within a macro.  See *Note
+     TIC54X-Macros::.
+
+`.version VERSION'
+     Set which processor to build instructions for.  Though the
+     following values are accepted, the op is ignored.
+    `541'
+    `542'
+    `543'
+    `545'
+    `545LP'
+    `546LP'
+    `548'
+    `549'
+
+
+File: as.info,  Node: TIC54X-Macros,  Next: TIC54X-MMRegs,  Prev: TIC54X-Directives,  Up: TIC54X-Dependent
+
+8.29.10 Macros
+--------------
+
+Macros do not require explicit dereferencing of arguments (i.e. \ARG).
+
+   During macro expansion, the macro parameters are converted to
+subsyms.  If the number of arguments passed the macro invocation
+exceeds the number of parameters defined, the last parameter is
+assigned the string equivalent of all remaining arguments.  If fewer
+arguments are given than parameters, the missing parameters are
+assigned empty strings.  To include a comma in an argument, you must
+enclose the argument in quotes.
+
+   The following built-in subsym functions allow examination of the
+string value of subsyms (or ordinary strings).  The arguments are
+strings unless otherwise indicated (subsyms passed as args will be
+replaced by the strings they represent).
+``$symlen(STR)''
+     Returns the length of STR.
+
+``$symcmp(STR1,STR2)''
+     Returns 0 if STR1 == STR2, non-zero otherwise.
+
+``$firstch(STR,CH)''
+     Returns index of the first occurrence of character constant CH in
+     STR.
+
+``$lastch(STR,CH)''
+     Returns index of the last occurrence of character constant CH in
+     STR.
+
+``$isdefed(SYMBOL)''
+     Returns zero if the symbol SYMBOL is not in the symbol table,
+     non-zero otherwise.
+
+``$ismember(SYMBOL,LIST)''
+     Assign the first member of comma-separated string LIST to SYMBOL;
+     LIST is reassigned the remainder of the list.  Returns zero if
+     LIST is a null string.  Both arguments must be subsyms.
+
+``$iscons(EXPR)''
+     Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal,
+     4 if a character, 5 if decimal, and zero if not an integer.
+
+``$isname(NAME)''
+     Returns 1 if NAME is a valid symbol name, zero otherwise.
+
+``$isreg(REG)''
+     Returns 1 if REG is a valid predefined register name (AR0-AR7
+     only).
+
+``$structsz(STAG)''
+     Returns the size of the structure or union represented by STAG.
+
+``$structacc(STAG)''
+     Returns the reference point of the structure or union represented
+     by STAG.   Always returns zero.
+
+
+
+File: as.info,  Node: TIC54X-MMRegs,  Prev: TIC54X-Macros,  Up: TIC54X-Dependent
+
+8.29.11 Memory-mapped Registers
+-------------------------------
+
+The following symbols are recognized as memory-mapped registers:
+
+
+
+File: as.info,  Node: Z80-Dependent,  Next: Z8000-Dependent,  Prev: Xtensa-Dependent,  Up: Machine Dependencies
+
+8.30 Z80 Dependent Features
+===========================
+
+* Menu:
+
+* Z80 Options::              Options
+* Z80 Syntax::               Syntax
+* Z80 Floating Point::       Floating Point
+* Z80 Directives::           Z80 Machine Directives
+* Z80 Opcodes::              Opcodes
+
+
+File: as.info,  Node: Z80 Options,  Next: Z80 Syntax,  Up: Z80-Dependent
+
+8.30.1 Options
+--------------
+
+The Zilog Z80 and Ascii R800 version of `as' have a few machine
+dependent options.
+`-z80'
+     Produce code for the Z80 processor. There are additional options to
+     request warnings and error messages for undocumented instructions.
+
+`-ignore-undocumented-instructions'
+`-Wnud'
+     Silently assemble undocumented Z80-instructions that have been
+     adopted as documented R800-instructions.
+
+`-ignore-unportable-instructions'
+`-Wnup'
+     Silently assemble all undocumented Z80-instructions.
+
+`-warn-undocumented-instructions'
+`-Wud'
+     Issue warnings for undocumented Z80-instructions that work on
+     R800, do not assemble other undocumented instructions without
+     warning.
+
+`-warn-unportable-instructions'
+`-Wup'
+     Issue warnings for other undocumented Z80-instructions, do not
+     treat any undocumented instructions as errors.
+
+`-forbid-undocumented-instructions'
+`-Fud'
+     Treat all undocumented z80-instructions as errors.
+
+`-forbid-unportable-instructions'
+`-Fup'
+     Treat undocumented z80-instructions that do not work on R800 as
+     errors.
+
+`-r800'
+     Produce code for the R800 processor. The assembler does not support
+     undocumented instructions for the R800.  In line with common
+     practice, `as' uses Z80 instriction names for the R800 processor,
+     as far as they exist.
+
+
+File: as.info,  Node: Z80 Syntax,  Next: Z80 Floating Point,  Prev: Z80 Options,  Up: Z80-Dependent
+
+8.30.2 Syntax
+-------------
+
+The assembler syntax closely follows the 'Z80 family CPU User Manual' by
+Zilog.  In expressions a single `=' may be used as "is equal to"
+comparison operator.
+
+   Suffices can be used to indicate the radix of integer constants; `H'
+or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o'
+for octal, and `B' for binary.
+
+   The suffix `b' denotes a backreference to local label.
+
+* Menu:
+
+* Z80-Chars::                Special Characters
+* Z80-Regs::                 Register Names
+* Z80-Case::                 Case Sensitivity
+
+
+File: as.info,  Node: Z80-Chars,  Next: Z80-Regs,  Up: Z80 Syntax
+
+8.30.2.1 Special Characters
+...........................
+
+The semicolon `;' is the line comment character;
+
+   The dollar sign `$' can be used as a prefix for hexadecimal numbers
+and as a symbol denoting the current location counter.
+
+   A backslash `\' is an ordinary character for the Z80 assembler.
+
+   The single quote `'' must be followed by a closing quote. If there
+is one character inbetween, it is a character constant, otherwise it is
+a string constant.
+
+
+File: as.info,  Node: Z80-Regs,  Next: Z80-Case,  Prev: Z80-Chars,  Up: Z80 Syntax
+
+8.30.2.2 Register Names
+.......................
+
+The registers are referred to with the letters assigned to them by
+Zilog. In addition `as' recognises `ixl' and `ixh' as the least and
+most significant octet in `ix', and similarly `iyl' and  `iyh' as parts
+of `iy'.
+
+
+File: as.info,  Node: Z80-Case,  Prev: Z80-Regs,  Up: Z80 Syntax
+
+8.30.2.3 Case Sensitivity
+.........................
+
+Upper and lower case are equivalent in register names, opcodes,
+condition codes  and assembler directives.  The case of letters is
+significant in labels and symbol names. The case is also important to
+distinguish the suffix `b' for a backward reference to a local label
+from the suffix `B' for a number in binary notation.
+
+
+File: as.info,  Node: Z80 Floating Point,  Next: Z80 Directives,  Prev: Z80 Syntax,  Up: Z80-Dependent
+
+8.30.3 Floating Point
+---------------------
+
+Floating-point numbers are not supported.
+
+
+File: as.info,  Node: Z80 Directives,  Next: Z80 Opcodes,  Prev: Z80 Floating Point,  Up: Z80-Dependent
+
+8.30.4 Z80 Assembler Directives
+-------------------------------
+
+`as' for the Z80 supports some additional directives for compatibility
+with other assemblers.
+
+   These are the additional directives in `as' for the Z80:
+
+`db EXPRESSION|STRING[,EXPRESSION|STRING...]'
+`defb EXPRESSION|STRING[,EXPRESSION|STRING...]'
+     For each STRING the characters are copied to the object file, for
+     each other EXPRESSION the value is stored in one byte.  A warning
+     is issued in case of an overflow.
+
+`dw EXPRESSION[,EXPRESSION...]'
+`defw EXPRESSION[,EXPRESSION...]'
+     For each EXPRESSION the value is stored in two bytes, ignoring
+     overflow.
+
+`d24 EXPRESSION[,EXPRESSION...]'
+`def24 EXPRESSION[,EXPRESSION...]'
+     For each EXPRESSION the value is stored in three bytes, ignoring
+     overflow.
+
+`d32 EXPRESSION[,EXPRESSION...]'
+`def32 EXPRESSION[,EXPRESSION...]'
+     For each EXPRESSION the value is stored in four bytes, ignoring
+     overflow.
+
+`ds COUNT[, VALUE]'
+`defs COUNT[, VALUE]'
+     Fill COUNT bytes in the object file with VALUE, if VALUE is
+     omitted it defaults to zero.
+
+`SYMBOL equ EXPRESSION'
+`SYMBOL defl EXPRESSION'
+     These directives set the value of SYMBOL to EXPRESSION. If `equ'
+     is used, it is an error if SYMBOL is already defined.  Symbols
+     defined with `equ' are not protected from redefinition.
+
+`set'
+     This is a normal instruction on Z80, and not an assembler
+     directive.
+
+`psect NAME'
+     A synonym for *Note Section::, no second argument should be given.
+
+
+
+File: as.info,  Node: Z80 Opcodes,  Prev: Z80 Directives,  Up: Z80-Dependent
+
+8.30.5 Opcodes
+--------------
+
+In line with commmon practice Z80 mnonics are used for both the Z80 and
+the R800.
+
+   In many instructions it is possible to use one of the half index
+registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general
+purpose register. This yields instructions that are documented on the
+R800 and undocumented on the Z80.  Similarly `in f,(c)' is documented
+on the R800 and undocumented on the Z80.
+
+   The assembler also supports the following undocumented
+Z80-instructions, that have not been adopted in the R800 instruction
+set:
+`out (c),0'
+     Sends zero to the port pointed to by register c.
+
+`sli M'
+     Equivalent to `M = (M<<1)+1', the operand M can be any operand
+     that is valid for `sla'. One can use `sll' as a synonym for `sli'.
+
+`OP (ix+D), R'
+     This is equivalent to
+
+          ld R, (ix+D)
+          OPC R
+          ld (ix+D), R
+
+     The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc',
+     `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R'
+     may be any of `a', `b', `c', `d', `e', `h' and `l'.
+
+`OPC (iy+D), R'
+     As above, but with `iy' instead of `ix'.
+
+   The web site at `http://www.z80.info' is a good starting place to
+find more information on programming the Z80.
+
+
+File: as.info,  Node: Z8000-Dependent,  Next: Vax-Dependent,  Prev: Z80-Dependent,  Up: Machine Dependencies
+
+8.31 Z8000 Dependent Features
+=============================
+
+   The Z8000 as supports both members of the Z8000 family: the
+unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with
+24 bit addresses.
+
+   When the assembler is in unsegmented mode (specified with the
+`unsegm' directive), an address takes up one word (16 bit) sized
+register.  When the assembler is in segmented mode (specified with the
+`segm' directive), a 24-bit address takes up a long (32 bit) register.
+*Note Assembler Directives for the Z8000: Z8000 Directives, for a list
+of other Z8000 specific assembler directives.
+
+* Menu:
+
+* Z8000 Options::               Command-line options for the Z8000
+* Z8000 Syntax::                Assembler syntax for the Z8000
+* Z8000 Directives::            Special directives for the Z8000
+* Z8000 Opcodes::               Opcodes
+
+
+File: as.info,  Node: Z8000 Options,  Next: Z8000 Syntax,  Up: Z8000-Dependent
+
+8.31.1 Options
+--------------
+
+`-z8001'
+     Generate segmented code by default.
+
+`-z8002'
+     Generate unsegmented code by default.
+
+
+File: as.info,  Node: Z8000 Syntax,  Next: Z8000 Directives,  Prev: Z8000 Options,  Up: Z8000-Dependent
+
+8.31.2 Syntax
+-------------
+
+* Menu:
+
+* Z8000-Chars::                Special Characters
+* Z8000-Regs::                 Register Names
+* Z8000-Addressing::           Addressing Modes
+
+
+File: as.info,  Node: Z8000-Chars,  Next: Z8000-Regs,  Up: Z8000 Syntax
+
+8.31.2.1 Special Characters
+...........................
+
+`!' is the line comment character.
+
+   You can use `;' instead of a newline to separate statements.
+
+
+File: as.info,  Node: Z8000-Regs,  Next: Z8000-Addressing,  Prev: Z8000-Chars,  Up: Z8000 Syntax
+
+8.31.2.2 Register Names
+.......................
+
+The Z8000 has sixteen 16 bit registers, numbered 0 to 15.  You can refer
+to different sized groups of registers by register number, with the
+prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for
+64 bit registers.  You can also refer to the contents of the first
+eight (of the sixteen 16 bit registers) by bytes.  They are named `rlN'
+and `rhN'.
+
+_byte registers_
+     rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3
+     rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7
+
+_word registers_
+     r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15
+
+_long word registers_
+     rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14
+
+_quad word registers_
+     rq0 rq4 rq8 rq12
+
+
+File: as.info,  Node: Z8000-Addressing,  Prev: Z8000-Regs,  Up: Z8000 Syntax
+
+8.31.2.3 Addressing Modes
+.........................
+
+as understands the following addressing modes for the Z8000:
+
+`rlN'
+`rhN'
+`rN'
+`rrN'
+`rqN'
+     Register direct:  8bit, 16bit, 32bit, and 64bit registers.
+
+`@rN'
+`@rrN'
+     Indirect register:  @rrN in segmented mode, @rN in unsegmented
+     mode.
+
+`ADDR'
+     Direct: the 16 bit or 24 bit address (depending on whether the
+     assembler is in segmented or unsegmented mode) of the operand is
+     in the instruction.
+
+`address(rN)'
+     Indexed: the 16 or 24 bit address is added to the 16 bit register
+     to produce the final address in memory of the operand.
+
+`rN(#IMM)'
+`rrN(#IMM)'
+     Base Address: the 16 or 24 bit register is added to the 16 bit sign
+     extended immediate displacement to produce the final address in
+     memory of the operand.
+
+`rN(rM)'
+`rrN(rM)'
+     Base Index: the 16 or 24 bit register rN or rrN is added to the
+     sign extended 16 bit index register rM to produce the final
+     address in memory of the operand.
+
+`#XX'
+     Immediate data XX.
+
+
+File: as.info,  Node: Z8000 Directives,  Next: Z8000 Opcodes,  Prev: Z8000 Syntax,  Up: Z8000-Dependent
+
+8.31.3 Assembler Directives for the Z8000
+-----------------------------------------
+
+The Z8000 port of as includes additional assembler directives, for
+compatibility with other Z8000 assemblers.  These do not begin with `.'
+(unlike the ordinary as directives).
+
+`segm'
+`.z8001'
+     Generate code for the segmented Z8001.
+
+`unsegm'
+`.z8002'
+     Generate code for the unsegmented Z8002.
+
+`name'
+     Synonym for `.file'
+
+`global'
+     Synonym for `.global'
+
+`wval'
+     Synonym for `.word'
+
+`lval'
+     Synonym for `.long'
+
+`bval'
+     Synonym for `.byte'
+
+`sval'
+     Assemble a string.  `sval' expects one string literal, delimited by
+     single quotes.  It assembles each byte of the string into
+     consecutive addresses.  You can use the escape sequence `%XX'
+     (where XX represents a two-digit hexadecimal number) to represent
+     the character whose ASCII value is XX.  Use this feature to
+     describe single quote and other characters that may not appear in
+     string literals as themselves.  For example, the C statement
+     `char *a = "he said \"it's 50% off\"";' is represented in Z8000
+     assembly language (shown with the assembler output in hex at the
+     left) as
+
+          68652073    sval    'he said %22it%27s 50%25 off%22%00'
+          61696420
+          22697427
+          73203530
+          25206F66
+          662200
+
+`rsect'
+     synonym for `.section'
+
+`block'
+     synonym for `.space'
+
+`even'
+     special case of `.align'; aligns output to even byte boundary.
+
+
+File: as.info,  Node: Z8000 Opcodes,  Prev: Z8000 Directives,  Up: Z8000-Dependent
+
+8.31.4 Opcodes
+--------------
+
+For detailed information on the Z8000 machine instruction set, see
+`Z8000 Technical Manual'.
+
+   The following table summarizes the opcodes and their arguments:
+
+                 rs   16 bit source register
+                 rd   16 bit destination register
+                 rbs   8 bit source register
+                 rbd   8 bit destination register
+                 rrs   32 bit source register
+                 rrd   32 bit destination register
+                 rqs   64 bit source register
+                 rqd   64 bit destination register
+                 addr 16/24 bit address
+                 imm  immediate data
+
+     adc rd,rs               clrb addr               cpsir @rd,@rs,rr,cc
+     adcb rbd,rbs            clrb addr(rd)           cpsirb @rd,@rs,rr,cc
+     add rd,@rs              clrb rbd                dab rbd
+     add rd,addr             com @rd                 dbjnz rbd,disp7
+     add rd,addr(rs)         com addr                dec @rd,imm4m1
+     add rd,imm16            com addr(rd)            dec addr(rd),imm4m1
+     add rd,rs               com rd                  dec addr,imm4m1
+     addb rbd,@rs            comb @rd                dec rd,imm4m1
+     addb rbd,addr           comb addr               decb @rd,imm4m1
+     addb rbd,addr(rs)       comb addr(rd)           decb addr(rd),imm4m1
+     addb rbd,imm8           comb rbd                decb addr,imm4m1
+     addb rbd,rbs            comflg flags            decb rbd,imm4m1
+     addl rrd,@rs            cp @rd,imm16            di i2
+     addl rrd,addr           cp addr(rd),imm16       div rrd,@rs
+     addl rrd,addr(rs)       cp addr,imm16           div rrd,addr
+     addl rrd,imm32          cp rd,@rs               div rrd,addr(rs)
+     addl rrd,rrs            cp rd,addr              div rrd,imm16
+     and rd,@rs              cp rd,addr(rs)          div rrd,rs
+     and rd,addr             cp rd,imm16             divl rqd,@rs
+     and rd,addr(rs)         cp rd,rs                divl rqd,addr
+     and rd,imm16            cpb @rd,imm8            divl rqd,addr(rs)
+     and rd,rs               cpb addr(rd),imm8       divl rqd,imm32
+     andb rbd,@rs            cpb addr,imm8           divl rqd,rrs
+     andb rbd,addr           cpb rbd,@rs             djnz rd,disp7
+     andb rbd,addr(rs)       cpb rbd,addr            ei i2
+     andb rbd,imm8           cpb rbd,addr(rs)        ex rd,@rs
+     andb rbd,rbs            cpb rbd,imm8            ex rd,addr
+     bit @rd,imm4            cpb rbd,rbs             ex rd,addr(rs)
+     bit addr(rd),imm4       cpd rd,@rs,rr,cc        ex rd,rs
+     bit addr,imm4           cpdb rbd,@rs,rr,cc      exb rbd,@rs
+     bit rd,imm4             cpdr rd,@rs,rr,cc       exb rbd,addr
+     bit rd,rs               cpdrb rbd,@rs,rr,cc     exb rbd,addr(rs)
+     bitb @rd,imm4           cpi rd,@rs,rr,cc        exb rbd,rbs
+     bitb addr(rd),imm4      cpib rbd,@rs,rr,cc      ext0e imm8
+     bitb addr,imm4          cpir rd,@rs,rr,cc       ext0f imm8
+     bitb rbd,imm4           cpirb rbd,@rs,rr,cc     ext8e imm8
+     bitb rbd,rs             cpl rrd,@rs             ext8f imm8
+     bpt                     cpl rrd,addr            exts rrd
+     call @rd                cpl rrd,addr(rs)        extsb rd
+     call addr               cpl rrd,imm32           extsl rqd
+     call addr(rd)           cpl rrd,rrs             halt
+     calr disp12             cpsd @rd,@rs,rr,cc      in rd,@rs
+     clr @rd                 cpsdb @rd,@rs,rr,cc     in rd,imm16
+     clr addr                cpsdr @rd,@rs,rr,cc     inb rbd,@rs
+     clr addr(rd)            cpsdrb @rd,@rs,rr,cc    inb rbd,imm16
+     clr rd                  cpsi @rd,@rs,rr,cc      inc @rd,imm4m1
+     clrb @rd                cpsib @rd,@rs,rr,cc     inc addr(rd),imm4m1
+     inc addr,imm4m1         ldb rbd,rs(rx)          mult rrd,addr(rs)
+     inc rd,imm4m1           ldb rd(imm16),rbs       mult rrd,imm16
+     incb @rd,imm4m1         ldb rd(rx),rbs          mult rrd,rs
+     incb addr(rd),imm4m1    ldctl ctrl,rs           multl rqd,@rs
+     incb addr,imm4m1        ldctl rd,ctrl           multl rqd,addr
+     incb rbd,imm4m1         ldd @rs,@rd,rr          multl rqd,addr(rs)
+     ind @rd,@rs,ra          lddb @rs,@rd,rr         multl rqd,imm32
+     indb @rd,@rs,rba        lddr @rs,@rd,rr         multl rqd,rrs
+     inib @rd,@rs,ra         lddrb @rs,@rd,rr        neg @rd
+     inibr @rd,@rs,ra        ldi @rd,@rs,rr          neg addr
+     iret                    ldib @rd,@rs,rr         neg addr(rd)
+     jp cc,@rd               ldir @rd,@rs,rr         neg rd
+     jp cc,addr              ldirb @rd,@rs,rr        negb @rd
+     jp cc,addr(rd)          ldk rd,imm4             negb addr
+     jr cc,disp8             ldl @rd,rrs             negb addr(rd)
+     ld @rd,imm16            ldl addr(rd),rrs        negb rbd
+     ld @rd,rs               ldl addr,rrs            nop
+     ld addr(rd),imm16       ldl rd(imm16),rrs       or rd,@rs
+     ld addr(rd),rs          ldl rd(rx),rrs          or rd,addr
+     ld addr,imm16           ldl rrd,@rs             or rd,addr(rs)
+     ld addr,rs              ldl rrd,addr            or rd,imm16
+     ld rd(imm16),rs         ldl rrd,addr(rs)        or rd,rs
+     ld rd(rx),rs            ldl rrd,imm32           orb rbd,@rs
+     ld rd,@rs               ldl rrd,rrs             orb rbd,addr
+     ld rd,addr              ldl rrd,rs(imm16)       orb rbd,addr(rs)
+     ld rd,addr(rs)          ldl rrd,rs(rx)          orb rbd,imm8
+     ld rd,imm16             ldm @rd,rs,n            orb rbd,rbs
+     ld rd,rs                ldm addr(rd),rs,n       out @rd,rs
+     ld rd,rs(imm16)         ldm addr,rs,n           out imm16,rs
+     ld rd,rs(rx)            ldm rd,@rs,n            outb @rd,rbs
+     lda rd,addr             ldm rd,addr(rs),n       outb imm16,rbs
+     lda rd,addr(rs)         ldm rd,addr,n           outd @rd,@rs,ra
+     lda rd,rs(imm16)        ldps @rs                outdb @rd,@rs,rba
+     lda rd,rs(rx)           ldps addr               outib @rd,@rs,ra
+     ldar rd,disp16          ldps addr(rs)           outibr @rd,@rs,ra
+     ldb @rd,imm8            ldr disp16,rs           pop @rd,@rs
+     ldb @rd,rbs             ldr rd,disp16           pop addr(rd),@rs
+     ldb addr(rd),imm8       ldrb disp16,rbs         pop addr,@rs
+     ldb addr(rd),rbs        ldrb rbd,disp16         pop rd,@rs
+     ldb addr,imm8           ldrl disp16,rrs         popl @rd,@rs
+     ldb addr,rbs            ldrl rrd,disp16         popl addr(rd),@rs
+     ldb rbd,@rs             mbit                    popl addr,@rs
+     ldb rbd,addr            mreq rd                 popl rrd,@rs
+     ldb rbd,addr(rs)        mres                    push @rd,@rs
+     ldb rbd,imm8            mset                    push @rd,addr
+     ldb rbd,rbs             mult rrd,@rs            push @rd,addr(rs)
+     ldb rbd,rs(imm16)       mult rrd,addr           push @rd,imm16
+     push @rd,rs             set addr,imm4           subl rrd,imm32
+     pushl @rd,@rs           set rd,imm4             subl rrd,rrs
+     pushl @rd,addr          set rd,rs               tcc cc,rd
+     pushl @rd,addr(rs)      setb @rd,imm4           tccb cc,rbd
+     pushl @rd,rrs           setb addr(rd),imm4      test @rd
+     res @rd,imm4            setb addr,imm4          test addr
+     res addr(rd),imm4       setb rbd,imm4           test addr(rd)
+     res addr,imm4           setb rbd,rs             test rd
+     res rd,imm4             setflg imm4             testb @rd
+     res rd,rs               sinb rbd,imm16          testb addr
+     resb @rd,imm4           sinb rd,imm16           testb addr(rd)
+     resb addr(rd),imm4      sind @rd,@rs,ra         testb rbd
+     resb addr,imm4          sindb @rd,@rs,rba       testl @rd
+     resb rbd,imm4           sinib @rd,@rs,ra        testl addr
+     resb rbd,rs             sinibr @rd,@rs,ra       testl addr(rd)
+     resflg imm4             sla rd,imm8             testl rrd
+     ret cc                  slab rbd,imm8           trdb @rd,@rs,rba
+     rl rd,imm1or2           slal rrd,imm8           trdrb @rd,@rs,rba
+     rlb rbd,imm1or2         sll rd,imm8             trib @rd,@rs,rbr
+     rlc rd,imm1or2          sllb rbd,imm8           trirb @rd,@rs,rbr
+     rlcb rbd,imm1or2        slll rrd,imm8           trtdrb @ra,@rb,rbr
+     rldb rbb,rba            sout imm16,rs           trtib @ra,@rb,rr
+     rr rd,imm1or2           soutb imm16,rbs         trtirb @ra,@rb,rbr
+     rrb rbd,imm1or2         soutd @rd,@rs,ra        trtrb @ra,@rb,rbr
+     rrc rd,imm1or2          soutdb @rd,@rs,rba      tset @rd
+     rrcb rbd,imm1or2        soutib @rd,@rs,ra       tset addr
+     rrdb rbb,rba            soutibr @rd,@rs,ra      tset addr(rd)
+     rsvd36                  sra rd,imm8             tset rd
+     rsvd38                  srab rbd,imm8           tsetb @rd
+     rsvd78                  sral rrd,imm8           tsetb addr
+     rsvd7e                  srl rd,imm8             tsetb addr(rd)
+     rsvd9d                  srlb rbd,imm8           tsetb rbd
+     rsvd9f                  srll rrd,imm8           xor rd,@rs
+     rsvdb9                  sub rd,@rs              xor rd,addr
+     rsvdbf                  sub rd,addr             xor rd,addr(rs)
+     sbc rd,rs               sub rd,addr(rs)         xor rd,imm16
+     sbcb rbd,rbs            sub rd,imm16            xor rd,rs
+     sc imm8                 sub rd,rs               xorb rbd,@rs
+     sda rd,rs               subb rbd,@rs            xorb rbd,addr
+     sdab rbd,rs             subb rbd,addr           xorb rbd,addr(rs)
+     sdal rrd,rs             subb rbd,addr(rs)       xorb rbd,imm8
+     sdl rd,rs               subb rbd,imm8           xorb rbd,rbs
+     sdlb rbd,rs             subb rbd,rbs            xorb rbd,rbs
+     sdll rrd,rs             subl rrd,@rs
+     set @rd,imm4            subl rrd,addr
+     set addr(rd),imm4       subl rrd,addr(rs)
+
+
+File: as.info,  Node: Vax-Dependent,  Prev: Z8000-Dependent,  Up: Machine Dependencies
+
+8.32 VAX Dependent Features
+===========================
+
+* Menu:
+
+* VAX-Opts::                    VAX Command-Line Options
+* VAX-float::                   VAX Floating Point
+* VAX-directives::              Vax Machine Directives
+* VAX-opcodes::                 VAX Opcodes
+* VAX-branch::                  VAX Branch Improvement
+* VAX-operands::                VAX Operands
+* VAX-no::                      Not Supported on VAX
+
+
+File: as.info,  Node: VAX-Opts,  Next: VAX-float,  Up: Vax-Dependent
+
+8.32.1 VAX Command-Line Options
+-------------------------------
+
+The Vax version of `as' accepts any of the following options, gives a
+warning message that the option was ignored and proceeds.  These
+options are for compatibility with scripts designed for other people's
+assemblers.
+
+``-D' (Debug)'
+``-S' (Symbol Table)'
+``-T' (Token Trace)'
+     These are obsolete options used to debug old assemblers.
+
+``-d' (Displacement size for JUMPs)'
+     This option expects a number following the `-d'.  Like options
+     that expect filenames, the number may immediately follow the `-d'
+     (old standard) or constitute the whole of the command line
+     argument that follows `-d' (GNU standard).
+
+``-V' (Virtualize Interpass Temporary File)'
+     Some other assemblers use a temporary file.  This option commanded
+     them to keep the information in active memory rather than in a
+     disk file.  `as' always does this, so this option is redundant.
+
+``-J' (JUMPify Longer Branches)'
+     Many 32-bit computers permit a variety of branch instructions to
+     do the same job.  Some of these instructions are short (and fast)
+     but have a limited range; others are long (and slow) but can
+     branch anywhere in virtual memory.  Often there are 3 flavors of
+     branch: short, medium and long.  Some other assemblers would emit
+     short and medium branches, unless told by this option to emit
+     short and long branches.
+
+``-t' (Temporary File Directory)'
+     Some other assemblers may use a temporary file, and this option
+     takes a filename being the directory to site the temporary file.
+     Since `as' does not use a temporary disk file, this option makes
+     no difference.  `-t' needs exactly one filename.
+
+   The Vax version of the assembler accepts additional options when
+compiled for VMS:
+
+`-h N'
+     External symbol or section (used for global variables) names are
+     not case sensitive on VAX/VMS and always mapped to upper case.
+     This is contrary to the C language definition which explicitly
+     distinguishes upper and lower case.  To implement a standard
+     conforming C compiler, names must be changed (mapped) to preserve
+     the case information.  The default mapping is to convert all lower
+     case characters to uppercase and adding an underscore followed by
+     a 6 digit hex value, representing a 24 digit binary value.  The
+     one digits in the binary value represent which characters are
+     uppercase in the original symbol name.
+
+     The `-h N' option determines how we map names.  This takes several
+     values.  No `-h' switch at all allows case hacking as described
+     above.  A value of zero (`-h0') implies names should be upper
+     case, and inhibits the case hack.  A value of 2 (`-h2') implies
+     names should be all lower case, with no case hack.  A value of 3
+     (`-h3') implies that case should be preserved.  The value 1 is
+     unused.  The `-H' option directs `as' to display every mapped
+     symbol during assembly.
+
+     Symbols whose names include a dollar sign `$' are exceptions to the
+     general name mapping.  These symbols are normally only used to
+     reference VMS library names.  Such symbols are always mapped to
+     upper case.
+
+`-+'
+     The `-+' option causes `as' to truncate any symbol name larger
+     than 31 characters.  The `-+' option also prevents some code
+     following the `_main' symbol normally added to make the object
+     file compatible with Vax-11 "C".
+
+`-1'
+     This option is ignored for backward compatibility with `as'
+     version 1.x.
+
+`-H'
+     The `-H' option causes `as' to print every symbol which was
+     changed by case mapping.
+
+
+File: as.info,  Node: VAX-float,  Next: VAX-directives,  Prev: VAX-Opts,  Up: Vax-Dependent
+
+8.32.2 VAX Floating Point
+-------------------------
+
+Conversion of flonums to floating point is correct, and compatible with
+previous assemblers.  Rounding is towards zero if the remainder is
+exactly half the least significant bit.
+
+   `D', `F', `G' and `H' floating point formats are understood.
+
+   Immediate floating literals (_e.g._ `S`$6.9') are rendered
+correctly.  Again, rounding is towards zero in the boundary case.
+
+   The `.float' directive produces `f' format numbers.  The `.double'
+directive produces `d' format numbers.
+
+
+File: as.info,  Node: VAX-directives,  Next: VAX-opcodes,  Prev: VAX-float,  Up: Vax-Dependent
+
+8.32.3 Vax Machine Directives
+-----------------------------
+
+The Vax version of the assembler supports four directives for
+generating Vax floating point constants.  They are described in the
+table below.
+
+`.dfloat'
+     This expects zero or more flonums, separated by commas, and
+     assembles Vax `d' format 64-bit floating point constants.
+
+`.ffloat'
+     This expects zero or more flonums, separated by commas, and
+     assembles Vax `f' format 32-bit floating point constants.
+
+`.gfloat'
+     This expects zero or more flonums, separated by commas, and
+     assembles Vax `g' format 64-bit floating point constants.
+
+`.hfloat'
+     This expects zero or more flonums, separated by commas, and
+     assembles Vax `h' format 128-bit floating point constants.
+
+
+
+File: as.info,  Node: VAX-opcodes,  Next: VAX-branch,  Prev: VAX-directives,  Up: Vax-Dependent
+
+8.32.4 VAX Opcodes
+------------------
+
+All DEC mnemonics are supported.  Beware that `case...' instructions
+have exactly 3 operands.  The dispatch table that follows the `case...'
+instruction should be made with `.word' statements.  This is compatible
+with all unix assemblers we know of.
+
+
+File: as.info,  Node: VAX-branch,  Next: VAX-operands,  Prev: VAX-opcodes,  Up: Vax-Dependent
+
+8.32.5 VAX Branch Improvement
+-----------------------------
+
+Certain pseudo opcodes are permitted.  They are for branch
+instructions.  They expand to the shortest branch instruction that
+reaches the target.  Generally these mnemonics are made by substituting
+`j' for `b' at the start of a DEC mnemonic.  This feature is included
+both for compatibility and to help compilers.  If you do not need this
+feature, avoid these opcodes.  Here are the mnemonics, and the code
+they can expand into.
+
+`jbsb'
+     `Jsb' is already an instruction mnemonic, so we chose `jbsb'.
+    (byte displacement)
+          `bsbb ...'
+
+    (word displacement)
+          `bsbw ...'
+
+    (long displacement)
+          `jsb ...'
+
+`jbr'
+`jr'
+     Unconditional branch.
+    (byte displacement)
+          `brb ...'
+
+    (word displacement)
+          `brw ...'
+
+    (long displacement)
+          `jmp ...'
+
+`jCOND'
+     COND may be any one of the conditional branches `neq', `nequ',
+     `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs',
+     `gequ', `cc', `lssu', `cs'.  COND may also be one of the bit tests
+     `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs',
+     `lbc'.  NOTCOND is the opposite condition to COND.
+    (byte displacement)
+          `bCOND ...'
+
+    (word displacement)
+          `bNOTCOND foo ; brw ... ; foo:'
+
+    (long displacement)
+          `bNOTCOND foo ; jmp ... ; foo:'
+
+`jacbX'
+     X may be one of `b d f g h l w'.
+    (word displacement)
+          `OPCODE ...'
+
+    (long displacement)
+               OPCODE ..., foo ;
+               brb bar ;
+               foo: jmp ... ;
+               bar:
+
+`jaobYYY'
+     YYY may be one of `lss leq'.
+
+`jsobZZZ'
+     ZZZ may be one of `geq gtr'.
+    (byte displacement)
+          `OPCODE ...'
+
+    (word displacement)
+               OPCODE ..., foo ;
+               brb bar ;
+               foo: brw DESTINATION ;
+               bar:
+
+    (long displacement)
+               OPCODE ..., foo ;
+               brb bar ;
+               foo: jmp DESTINATION ;
+               bar:
+
+`aobleq'
+`aoblss'
+`sobgeq'
+`sobgtr'
+
+    (byte displacement)
+          `OPCODE ...'
+
+    (word displacement)
+               OPCODE ..., foo ;
+               brb bar ;
+               foo: brw DESTINATION ;
+               bar:
+
+    (long displacement)
+               OPCODE ..., foo ;
+               brb bar ;
+               foo: jmp DESTINATION ;
+               bar:
+
+
+File: as.info,  Node: VAX-operands,  Next: VAX-no,  Prev: VAX-branch,  Up: Vax-Dependent
+
+8.32.6 VAX Operands
+-------------------
+
+The immediate character is `$' for Unix compatibility, not `#' as DEC
+writes it.
+
+   The indirect character is `*' for Unix compatibility, not `@' as DEC
+writes it.
+
+   The displacement sizing character is ``' (an accent grave) for Unix
+compatibility, not `^' as DEC writes it.  The letter preceding ``' may
+have either case.  `G' is not understood, but all other letters (`b i l
+s w') are understood.
+
+   Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'.  Upper
+and lower case letters are equivalent.
+
+   For instance
+     tstb *w`$4(r5)
+
+   Any expression is permitted in an operand.  Operands are comma
+separated.
+
+
+File: as.info,  Node: VAX-no,  Prev: VAX-operands,  Up: Vax-Dependent
+
+8.32.7 Not Supported on VAX
+---------------------------
+
+Vax bit fields can not be assembled with `as'.  Someone can add the
+required code if they really need it.
+
+
+File: as.info,  Node: V850-Dependent,  Next: Xtensa-Dependent,  Prev: TIC54X-Dependent,  Up: Machine Dependencies
+
+8.33 v850 Dependent Features
+============================
+
+* Menu:
+
+* V850 Options::              Options
+* V850 Syntax::               Syntax
+* V850 Floating Point::       Floating Point
+* V850 Directives::           V850 Machine Directives
+* V850 Opcodes::              Opcodes
+
+
+File: as.info,  Node: V850 Options,  Next: V850 Syntax,  Up: V850-Dependent
+
+8.33.1 Options
+--------------
+
+`as' supports the following additional command-line options for the
+V850 processor family:
+
+`-wsigned_overflow'
+     Causes warnings to be produced when signed immediate values
+     overflow the space available for then within their opcodes.  By
+     default this option is disabled as it is possible to receive
+     spurious warnings due to using exact bit patterns as immediate
+     constants.
+
+`-wunsigned_overflow'
+     Causes warnings to be produced when unsigned immediate values
+     overflow the space available for then within their opcodes.  By
+     default this option is disabled as it is possible to receive
+     spurious warnings due to using exact bit patterns as immediate
+     constants.
+
+`-mv850'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850 processor.  This allows the linker to detect
+     attempts to link such code with code assembled for other
+     processors.
+
+`-mv850e'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850E processor.  This allows the linker to detect
+     attempts to link such code with code assembled for other
+     processors.
+
+`-mv850e1'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850E1 processor.  This allows the linker to
+     detect attempts to link such code with code assembled for other
+     processors.
+
+`-mv850any'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850 processor but support instructions that are
+     specific to the extended variants of the process.  This allows the
+     production of binaries that contain target specific code, but
+     which are also intended to be used in a generic fashion.  For
+     example libgcc.a contains generic routines used by the code
+     produced by GCC for all versions of the v850 architecture,
+     together with support routines only used by the V850E architecture.
+
+`-mrelax'
+     Enables relaxation.  This allows the .longcall and .longjump pseudo
+     ops to be used in the assembler source code.  These ops label
+     sections of code which are either a long function call or a long
+     branch.  The assembler will then flag these sections of code and
+     the linker will attempt to relax them.
+
+
+
+File: as.info,  Node: V850 Syntax,  Next: V850 Floating Point,  Prev: V850 Options,  Up: V850-Dependent
+
+8.33.2 Syntax
+-------------
+
+* Menu:
+
+* V850-Chars::                Special Characters
+* V850-Regs::                 Register Names
+
+
+File: as.info,  Node: V850-Chars,  Next: V850-Regs,  Up: V850 Syntax
+
+8.33.2.1 Special Characters
+...........................
+
+`#' is the line comment character.
+
+
+File: as.info,  Node: V850-Regs,  Prev: V850-Chars,  Up: V850 Syntax
+
+8.33.2.2 Register Names
+.......................
+
+`as' supports the following names for registers:
+`general register 0'
+     r0, zero
+
+`general register 1'
+     r1
+
+`general register 2'
+     r2, hp 
+
+`general register 3'
+     r3, sp 
+
+`general register 4'
+     r4, gp 
+
+`general register 5'
+     r5, tp
+
+`general register 6'
+     r6
+
+`general register 7'
+     r7
+
+`general register 8'
+     r8
+
+`general register 9'
+     r9
+
+`general register 10'
+     r10
+
+`general register 11'
+     r11
+
+`general register 12'
+     r12
+
+`general register 13'
+     r13
+
+`general register 14'
+     r14
+
+`general register 15'
+     r15
+
+`general register 16'
+     r16
+
+`general register 17'
+     r17
+
+`general register 18'
+     r18
+
+`general register 19'
+     r19
+
+`general register 20'
+     r20
+
+`general register 21'
+     r21
+
+`general register 22'
+     r22
+
+`general register 23'
+     r23
+
+`general register 24'
+     r24
+
+`general register 25'
+     r25
+
+`general register 26'
+     r26
+
+`general register 27'
+     r27
+
+`general register 28'
+     r28
+
+`general register 29'
+     r29 
+
+`general register 30'
+     r30, ep 
+
+`general register 31'
+     r31, lp 
+
+`system register 0'
+     eipc 
+
+`system register 1'
+     eipsw 
+
+`system register 2'
+     fepc 
+
+`system register 3'
+     fepsw 
+
+`system register 4'
+     ecr 
+
+`system register 5'
+     psw 
+
+`system register 16'
+     ctpc 
+
+`system register 17'
+     ctpsw 
+
+`system register 18'
+     dbpc 
+
+`system register 19'
+     dbpsw 
+
+`system register 20'
+     ctbp
+
+
+File: as.info,  Node: V850 Floating Point,  Next: V850 Directives,  Prev: V850 Syntax,  Up: V850-Dependent
+
+8.33.3 Floating Point
+---------------------
+
+The V850 family uses IEEE floating-point numbers.
+
+
+File: as.info,  Node: V850 Directives,  Next: V850 Opcodes,  Prev: V850 Floating Point,  Up: V850-Dependent
+
+8.33.4 V850 Machine Directives
+------------------------------
+
+`.offset <EXPRESSION>'
+     Moves the offset into the current section to the specified amount.
+
+`.section "name", <type>'
+     This is an extension to the standard .section directive.  It sets
+     the current section to be <type> and creates an alias for this
+     section called "name".
+
+`.v850'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850 processor.  This allows the linker to detect
+     attempts to link such code with code assembled for other
+     processors.
+
+`.v850e'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850E processor.  This allows the linker to detect
+     attempts to link such code with code assembled for other
+     processors.
+
+`.v850e1'
+     Specifies that the assembled code should be marked as being
+     targeted at the V850E1 processor.  This allows the linker to
+     detect attempts to link such code with code assembled for other
+     processors.
+
+
+
+File: as.info,  Node: V850 Opcodes,  Prev: V850 Directives,  Up: V850-Dependent
+
+8.33.5 Opcodes
+--------------
+
+`as' implements all the standard V850 opcodes.
+
+   `as' also implements the following pseudo ops:
+
+`hi0()'
+     Computes the higher 16 bits of the given expression and stores it
+     into the immediate operand field of the given instruction.  For
+     example:
+
+     `mulhi hi0(here - there), r5, r6'
+
+     computes the difference between the address of labels 'here' and
+     'there', takes the upper 16 bits of this difference, shifts it
+     down 16 bits and then mutliplies it by the lower 16 bits in
+     register 5, putting the result into register 6.
+
+`lo()'
+     Computes the lower 16 bits of the given expression and stores it
+     into the immediate operand field of the given instruction.  For
+     example:
+
+     `addi lo(here - there), r5, r6'
+
+     computes the difference between the address of labels 'here' and
+     'there', takes the lower 16 bits of this difference and adds it to
+     register 5, putting the result into register 6.
+
+`hi()'
+     Computes the higher 16 bits of the given expression and then adds
+     the value of the most significant bit of the lower 16 bits of the
+     expression and stores the result into the immediate operand field
+     of the given instruction.  For example the following code can be
+     used to compute the address of the label 'here' and store it into
+     register 6:
+
+     `movhi hi(here), r0, r6'     `movea lo(here), r6, r6'
+
+     The reason for this special behaviour is that movea performs a sign
+     extension on its immediate operand.  So for example if the address
+     of 'here' was 0xFFFFFFFF then without the special behaviour of the
+     hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6,
+     then the movea instruction would takes its immediate operand,
+     0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it
+     into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E).
+     With the hi() pseudo op adding in the top bit of the lo() pseudo
+     op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 =
+     0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 -
+     the right value.
+
+`hilo()'
+     Computes the 32 bit value of the given expression and stores it
+     into the immediate operand field of the given instruction (which
+     must be a mov instruction).  For example:
+
+     `mov hilo(here), r6'
+
+     computes the absolute address of label 'here' and puts the result
+     into register 6.
+
+`sdaoff()'
+     Computes the offset of the named variable from the start of the
+     Small Data Area (whoes address is held in register 4, the GP
+     register) and stores the result as a 16 bit signed value in the
+     immediate operand field of the given instruction.  For example:
+
+     `ld.w sdaoff(_a_variable)[gp],r6'
+
+     loads the contents of the location pointed to by the label
+     '_a_variable' into register 6, provided that the label is located
+     somewhere within +/- 32K of the address held in the GP register.
+     [Note the linker assumes that the GP register contains a fixed
+     address set to the address of the label called '__gp'.  This can
+     either be set up automatically by the linker, or specifically set
+     by using the `--defsym __gp=<value>' command line option].
+
+`tdaoff()'
+     Computes the offset of the named variable from the start of the
+     Tiny Data Area (whoes address is held in register 30, the EP
+     register) and stores the result as a 4,5, 7 or 8 bit unsigned
+     value in the immediate operand field of the given instruction.
+     For example:
+
+     `sld.w tdaoff(_a_variable)[ep],r6'
+
+     loads the contents of the location pointed to by the label
+     '_a_variable' into register 6, provided that the label is located
+     somewhere within +256 bytes of the address held in the EP
+     register.  [Note the linker assumes that the EP register contains
+     a fixed address set to the address of the label called '__ep'.
+     This can either be set up automatically by the linker, or
+     specifically set by using the `--defsym __ep=<value>' command line
+     option].
+
+`zdaoff()'
+     Computes the offset of the named variable from address 0 and
+     stores the result as a 16 bit signed value in the immediate
+     operand field of the given instruction.  For example:
+
+     `movea zdaoff(_a_variable),zero,r6'
+
+     puts the address of the label '_a_variable' into register 6,
+     assuming that the label is somewhere within the first 32K of
+     memory.  (Strictly speaking it also possible to access the last
+     32K of memory as well, as the offsets are signed).
+
+`ctoff()'
+     Computes the offset of the named variable from the start of the
+     Call Table Area (whoes address is helg in system register 20, the
+     CTBP register) and stores the result a 6 or 16 bit unsigned value
+     in the immediate field of then given instruction or piece of data.
+     For example:
+
+     `callt ctoff(table_func1)'
+
+     will put the call the function whoes address is held in the call
+     table at the location labeled 'table_func1'.
+
+`.longcall `name''
+     Indicates that the following sequence of instructions is a long
+     call to function `name'.  The linker will attempt to shorten this
+     call sequence if `name' is within a 22bit offset of the call.  Only
+     valid if the `-mrelax' command line switch has been enabled.
+
+`.longjump `name''
+     Indicates that the following sequence of instructions is a long
+     jump to label `name'.  The linker will attempt to shorten this code
+     sequence if `name' is within a 22bit offset of the jump.  Only
+     valid if the `-mrelax' command line switch has been enabled.
+
+
+   For information on the V850 instruction set, see `V850 Family
+32-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC.
+Ltd.
+
+
+File: as.info,  Node: Xtensa-Dependent,  Next: Z80-Dependent,  Prev: V850-Dependent,  Up: Machine Dependencies
+
+8.34 Xtensa Dependent Features
+==============================
+
+   This chapter covers features of the GNU assembler that are specific
+to the Xtensa architecture.  For details about the Xtensa instruction
+set, please consult the `Xtensa Instruction Set Architecture (ISA)
+Reference Manual'.
+
+* Menu:
+
+* Xtensa Options::              Command-line Options.
+* Xtensa Syntax::               Assembler Syntax for Xtensa Processors.
+* Xtensa Optimizations::        Assembler Optimizations.
+* Xtensa Relaxation::           Other Automatic Transformations.
+* Xtensa Directives::           Directives for Xtensa Processors.
+
+
+File: as.info,  Node: Xtensa Options,  Next: Xtensa Syntax,  Up: Xtensa-Dependent
+
+8.34.1 Command Line Options
+---------------------------
+
+The Xtensa version of the GNU assembler supports these special options:
+
+`--text-section-literals | --no-text-section-literals'
+     Control the treatment of literal pools.  The default is
+     `--no-text-section-literals', which places literals in a separate
+     section in the output file.  This allows the literal pool to be
+     placed in a data RAM/ROM.  With `--text-section-literals', the
+     literals are interspersed in the text section in order to keep
+     them as close as possible to their references.  This may be
+     necessary for large assembly files, where the literals would
+     otherwise be out of range of the `L32R' instructions in the text
+     section.  These options only affect literals referenced via
+     PC-relative `L32R' instructions; literals for absolute mode `L32R'
+     instructions are handled separately.
+
+`--absolute-literals | --no-absolute-literals'
+     Indicate to the assembler whether `L32R' instructions use absolute
+     or PC-relative addressing.  If the processor includes the absolute
+     addressing option, the default is to use absolute `L32R'
+     relocations.  Otherwise, only the PC-relative `L32R' relocations
+     can be used.
+
+`--target-align | --no-target-align'
+     Enable or disable automatic alignment to reduce branch penalties
+     at some expense in code size.  *Note Automatic Instruction
+     Alignment: Xtensa Automatic Alignment.  This optimization is
+     enabled by default.  Note that the assembler will always align
+     instructions like `LOOP' that have fixed alignment requirements.
+
+`--longcalls | --no-longcalls'
+     Enable or disable transformation of call instructions to allow
+     calls across a greater range of addresses.  *Note Function Call
+     Relaxation: Xtensa Call Relaxation.  This option should be used
+     when call targets can potentially be out of range.  It may degrade
+     both code size and performance, but the linker can generally
+     optimize away the unnecessary overhead when a call ends up within
+     range.  The default is `--no-longcalls'.
+
+`--transform | --no-transform'
+     Enable or disable all assembler transformations of Xtensa
+     instructions, including both relaxation and optimization.  The
+     default is `--transform'; `--no-transform' should only be used in
+     the rare cases when the instructions must be exactly as specified
+     in the assembly source.  Using `--no-transform' causes out of range
+     instruction operands to be errors.
+
+`--rename-section OLDNAME=NEWNAME'
+     Rename the OLDNAME section to NEWNAME.  This option can be used
+     multiple times to rename multiple sections.
+
+
+File: as.info,  Node: Xtensa Syntax,  Next: Xtensa Optimizations,  Prev: Xtensa Options,  Up: Xtensa-Dependent
+
+8.34.2 Assembler Syntax
+-----------------------
+
+Block comments are delimited by `/*' and `*/'.  End of line comments
+may be introduced with either `#' or `//'.
+
+   Instructions consist of a leading opcode or macro name followed by
+whitespace and an optional comma-separated list of operands:
+
+     OPCODE [OPERAND, ...]
+
+   Instructions must be separated by a newline or semicolon.
+
+   FLIX instructions, which bundle multiple opcodes together in a single
+instruction, are specified by enclosing the bundled opcodes inside
+braces:
+
+     {
+     [FORMAT]
+     OPCODE0 [OPERANDS]
+     OPCODE1 [OPERANDS]
+     OPCODE2 [OPERANDS]
+     ...
+     }
+
+   The opcodes in a FLIX instruction are listed in the same order as the
+corresponding instruction slots in the TIE format declaration.
+Directives and labels are not allowed inside the braces of a FLIX
+instruction.  A particular TIE format name can optionally be specified
+immediately after the opening brace, but this is usually unnecessary.
+The assembler will automatically search for a format that can encode the
+specified opcodes, so the format name need only be specified in rare
+cases where there is more than one applicable format and where it
+matters which of those formats is used.  A FLIX instruction can also be
+specified on a single line by separating the opcodes with semicolons:
+
+     { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... }
+
+   The assembler can automatically bundle opcodes into FLIX
+instructions.  It encodes the opcodes in order, one at a time, choosing
+the smallest format where each opcode can be encoded and filling unused
+instruction slots with no-ops.
+
+* Menu:
+
+* Xtensa Opcodes::              Opcode Naming Conventions.
+* Xtensa Registers::            Register Naming.
+
+
+File: as.info,  Node: Xtensa Opcodes,  Next: Xtensa Registers,  Up: Xtensa Syntax
+
+8.34.2.1 Opcode Names
+.....................
+
+See the `Xtensa Instruction Set Architecture (ISA) Reference Manual'
+for a complete list of opcodes and descriptions of their semantics.
+
+   If an opcode name is prefixed with an underscore character (`_'),
+`as' will not transform that instruction in any way.  The underscore
+prefix disables both optimization (*note Xtensa Optimizations: Xtensa
+Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa
+Relaxation.) for that particular instruction.  Only use the underscore
+prefix when it is essential to select the exact opcode produced by the
+assembler.  Using this feature unnecessarily makes the code less
+efficient by disabling assembler optimization and less flexible by
+disabling relaxation.
+
+   Note that this special handling of underscore prefixes only applies
+to Xtensa opcodes, not to either built-in macros or user-defined macros.
+When an underscore prefix is used with a macro (e.g., `_MOV'), it
+refers to a different macro.  The assembler generally provides built-in
+macros both with and without the underscore prefix, where the underscore
+versions behave as if the underscore carries through to the instructions
+in the macros.  For example, `_MOV' may expand to `_MOV.N'.
+
+   The underscore prefix only applies to individual instructions, not to
+series of instructions.  For example, if a series of instructions have
+underscore prefixes, the assembler will not transform the individual
+instructions, but it may insert other instructions between them (e.g.,
+to align a `LOOP' instruction).  To prevent the assembler from
+modifying a series of instructions as a whole, use the `no-transform'
+directive.  *Note transform: Transform Directive.
+
+
+File: as.info,  Node: Xtensa Registers,  Prev: Xtensa Opcodes,  Up: Xtensa Syntax
+
+8.34.2.2 Register Names
+.......................
+
+The assembly syntax for a register file entry is the "short" name for a
+TIE register file followed by the index into that register file.  For
+example, the general-purpose `AR' register file has a short name of
+`a', so these registers are named `a0'...`a15'.  As a special feature,
+`sp' is also supported as a synonym for `a1'.  Additional registers may
+be added by processor configuration options and by designer-defined TIE
+extensions.  An initial `$' character is optional in all register names.
+
+
+File: as.info,  Node: Xtensa Optimizations,  Next: Xtensa Relaxation,  Prev: Xtensa Syntax,  Up: Xtensa-Dependent
+
+8.34.3 Xtensa Optimizations
+---------------------------
+
+The optimizations currently supported by `as' are generation of density
+instructions where appropriate and automatic branch target alignment.
+
+* Menu:
+
+* Density Instructions::        Using Density Instructions.
+* Xtensa Automatic Alignment::  Automatic Instruction Alignment.
+
+
+File: as.info,  Node: Density Instructions,  Next: Xtensa Automatic Alignment,  Up: Xtensa Optimizations
+
+8.34.3.1 Using Density Instructions
+...................................
+
+The Xtensa instruction set has a code density option that provides
+16-bit versions of some of the most commonly used opcodes.  Use of these
+opcodes can significantly reduce code size.  When possible, the
+assembler automatically translates instructions from the core Xtensa
+instruction set into equivalent instructions from the Xtensa code
+density option.  This translation can be disabled by using underscore
+prefixes (*note Opcode Names: Xtensa Opcodes.), by using the
+`--no-transform' command-line option (*note Command Line Options:
+Xtensa Options.), or by using the `no-transform' directive (*note
+transform: Transform Directive.).
+
+   It is a good idea _not_ to use the density instructions directly.
+The assembler will automatically select dense instructions where
+possible.  If you later need to use an Xtensa processor without the code
+density option, the same assembly code will then work without
+modification.
+
+
+File: as.info,  Node: Xtensa Automatic Alignment,  Prev: Density Instructions,  Up: Xtensa Optimizations
+
+8.34.3.2 Automatic Instruction Alignment
+........................................
+
+The Xtensa assembler will automatically align certain instructions, both
+to optimize performance and to satisfy architectural requirements.
+
+   As an optimization to improve performance, the assembler attempts to
+align branch targets so they do not cross instruction fetch boundaries.
+(Xtensa processors can be configured with either 32-bit or 64-bit
+instruction fetch widths.)  An instruction immediately following a call
+is treated as a branch target in this context, because it will be the
+target of a return from the call.  This alignment has the potential to
+reduce branch penalties at some expense in code size.  The assembler
+will not attempt to align labels with the prefixes `.Ln' and `.LM',
+since these labels are used for debugging information and are not
+typically branch targets.  This optimization is enabled by default.
+You can disable it with the `--no-target-align' command-line option
+(*note Command Line Options: Xtensa Options.).
+
+   The target alignment optimization is done without adding instructions
+that could increase the execution time of the program.  If there are
+density instructions in the code preceding a target, the assembler can
+change the target alignment by widening some of those instructions to
+the equivalent 24-bit instructions.  Extra bytes of padding can be
+inserted immediately following unconditional jump and return
+instructions.  This approach is usually successful in aligning many,
+but not all, branch targets.
+
+   The `LOOP' family of instructions must be aligned such that the
+first instruction in the loop body does not cross an instruction fetch
+boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be
+on either a 1 or 2 mod 4 byte boundary).  The assembler knows about
+this restriction and inserts the minimal number of 2 or 3 byte no-op
+instructions to satisfy it.  When no-op instructions are added, any
+label immediately preceding the original loop will be moved in order to
+refer to the loop instruction, not the newly generated no-op
+instruction.  To preserve binary compatibility across processors with
+different fetch widths, the assembler conservatively assumes a 32-bit
+fetch width when aligning `LOOP' instructions (except if the first
+instruction in the loop is a 64-bit instruction).
+
+   Similarly, the `ENTRY' instruction must be aligned on a 0 mod 4 byte
+boundary.  The assembler satisfies this requirement by inserting zero
+bytes when required.  In addition, labels immediately preceding the
+`ENTRY' instruction will be moved to the newly aligned instruction
+location.
+
+
+File: as.info,  Node: Xtensa Relaxation,  Next: Xtensa Directives,  Prev: Xtensa Optimizations,  Up: Xtensa-Dependent
+
+8.34.4 Xtensa Relaxation
+------------------------
+
+When an instruction operand is outside the range allowed for that
+particular instruction field, `as' can transform the code to use a
+functionally-equivalent instruction or sequence of instructions.  This
+process is known as "relaxation".  This is typically done for branch
+instructions because the distance of the branch targets is not known
+until assembly-time.  The Xtensa assembler offers branch relaxation and
+also extends this concept to function calls, `MOVI' instructions and
+other instructions with immediate fields.
+
+* Menu:
+
+* Xtensa Branch Relaxation::        Relaxation of Branches.
+* Xtensa Call Relaxation::          Relaxation of Function Calls.
+* Xtensa Immediate Relaxation::     Relaxation of other Immediate Fields.
+
+
+File: as.info,  Node: Xtensa Branch Relaxation,  Next: Xtensa Call Relaxation,  Up: Xtensa Relaxation
+
+8.34.4.1 Conditional Branch Relaxation
+......................................
+
+When the target of a branch is too far away from the branch itself,
+i.e., when the offset from the branch to the target is too large to fit
+in the immediate field of the branch instruction, it may be necessary to
+replace the branch with a branch around a jump.  For example,
+
+         beqz    a2, L
+
+   may result in:
+
+         bnez.n  a2, M
+         j L
+     M:
+
+   (The `BNEZ.N' instruction would be used in this example only if the
+density option is available.  Otherwise, `BNEZ' would be used.)
+
+   This relaxation works well because the unconditional jump instruction
+has a much larger offset range than the various conditional branches.
+However, an error will occur if a branch target is beyond the range of a
+jump instruction.  `as' cannot relax unconditional jumps.  Similarly,
+an error will occur if the original input contains an unconditional
+jump to a target that is out of range.
+
+   Branch relaxation is enabled by default.  It can be disabled by using
+underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the
+`--no-transform' command-line option (*note Command Line Options:
+Xtensa Options.), or the `no-transform' directive (*note transform:
+Transform Directive.).
+
+
+File: as.info,  Node: Xtensa Call Relaxation,  Next: Xtensa Immediate Relaxation,  Prev: Xtensa Branch Relaxation,  Up: Xtensa Relaxation
+
+8.34.4.2 Function Call Relaxation
+.................................
+
+Function calls may require relaxation because the Xtensa immediate call
+instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a
+PC-relative offset of only 512 Kbytes in either direction.  For larger
+programs, it may be necessary to use indirect calls (`CALLX0',
+`CALLX4', `CALLX8' and `CALLX12') where the target address is specified
+in a register.  The Xtensa assembler can automatically relax immediate
+call instructions into indirect call instructions.  This relaxation is
+done by loading the address of the called function into the callee's
+return address register and then using a `CALLX' instruction.  So, for
+example:
+
+         call8 func
+
+   might be relaxed to:
+
+         .literal .L1, func
+         l32r    a8, .L1
+         callx8  a8
+
+   Because the addresses of targets of function calls are not generally
+known until link-time, the assembler must assume the worst and relax all
+the calls to functions in other source files, not just those that really
+will be out of range.  The linker can recognize calls that were
+unnecessarily relaxed, and it will remove the overhead introduced by the
+assembler for those cases where direct calls are sufficient.
+
+   Call relaxation is disabled by default because it can have a negative
+effect on both code size and performance, although the linker can
+usually eliminate the unnecessary overhead.  If a program is too large
+and some of the calls are out of range, function call relaxation can be
+enabled using the `--longcalls' command-line option or the `longcalls'
+directive (*note longcalls: Longcalls Directive.).
+
+
+File: as.info,  Node: Xtensa Immediate Relaxation,  Prev: Xtensa Call Relaxation,  Up: Xtensa Relaxation
+
+8.34.4.3 Other Immediate Field Relaxation
+.........................................
+
+The assembler normally performs the following other relaxations.  They
+can be disabled by using underscore prefixes (*note Opcode Names:
+Xtensa Opcodes.), the `--no-transform' command-line option (*note
+Command Line Options: Xtensa Options.), or the `no-transform' directive
+(*note transform: Transform Directive.).
+
+   The `MOVI' machine instruction can only materialize values in the
+range from -2048 to 2047.  Values outside this range are best
+materialized with `L32R' instructions.  Thus:
+
+         movi a0, 100000
+
+   is assembled into the following machine code:
+
+         .literal .L1, 100000
+         l32r a0, .L1
+
+   The `L8UI' machine instruction can only be used with immediate
+offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine
+instructions can only be used with offsets from 0 to 510.  The `L32I'
+machine instruction can only be used with offsets from 0 to 1020.  A
+load offset outside these ranges can be materalized with an `L32R'
+instruction if the destination register of the load is different than
+the source address register.  For example:
+
+         l32i a1, a0, 2040
+
+   is translated to:
+
+         .literal .L1, 2040
+         l32r a1, .L1
+         addi a1, a0, a1
+         l32i a1, a1, 0
+
+If the load destination and source address register are the same, an
+out-of-range offset causes an error.
+
+   The Xtensa `ADDI' instruction only allows immediate operands in the
+range from -128 to 127.  There are a number of alternate instruction
+sequences for the `ADDI' operation.  First, if the immediate is 0, the
+`ADDI' will be turned into a `MOV.N' instruction (or the equivalent
+`OR' instruction if the code density option is not available).  If the
+`ADDI' immediate is outside of the range -128 to 127, but inside the
+range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI'
+sequence will be used.  Finally, if the immediate is outside of this
+range and a free register is available, an `L32R'/`ADD' sequence will
+be used with a literal allocated from the literal pool.
+
+   For example:
+
+         addi    a5, a6, 0
+         addi    a5, a6, 512
+         addi    a5, a6, 513
+         addi    a5, a6, 50000
+
+   is assembled into the following:
+
+         .literal .L1, 50000
+         mov.n   a5, a6
+         addmi   a5, a6, 0x200
+         addmi   a5, a6, 0x200
+         addi    a5, a5, 1
+         l32r    a5, .L1
+         add     a5, a6, a5
+
+
+File: as.info,  Node: Xtensa Directives,  Prev: Xtensa Relaxation,  Up: Xtensa-Dependent
+
+8.34.5 Directives
+-----------------
+
+The Xtensa assember supports a region-based directive syntax:
+
+         .begin DIRECTIVE [OPTIONS]
+         ...
+         .end DIRECTIVE
+
+   All the Xtensa-specific directives that apply to a region of code use
+this syntax.
+
+   The directive applies to code between the `.begin' and the `.end'.
+The state of the option after the `.end' reverts to what it was before
+the `.begin'.  A nested `.begin'/`.end' region can further change the
+state of the directive without having to be aware of its outer state.
+For example, consider:
+
+         .begin no-transform
+     L:  add a0, a1, a2
+         .begin transform
+     M:  add a0, a1, a2
+         .end transform
+     N:  add a0, a1, a2
+         .end no-transform
+
+   The `ADD' opcodes at `L' and `N' in the outer `no-transform' region
+both result in `ADD' machine instructions, but the assembler selects an
+`ADD.N' instruction for the `ADD' at `M' in the inner `transform'
+region.
+
+   The advantage of this style is that it works well inside macros
+which can preserve the context of their callers.
+
+   The following directives are available:
+
+* Menu:
+
+* Schedule Directive::         Enable instruction scheduling.
+* Longcalls Directive::        Use Indirect Calls for Greater Range.
+* Transform Directive::        Disable All Assembler Transformations.
+* Literal Directive::          Intermix Literals with Instructions.
+* Literal Position Directive:: Specify Inline Literal Pool Locations.
+* Literal Prefix Directive::   Specify Literal Section Name Prefix.
+* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
+
+
+File: as.info,  Node: Schedule Directive,  Next: Longcalls Directive,  Up: Xtensa Directives
+
+8.34.5.1 schedule
+.................
+
+The `schedule' directive is recognized only for compatibility with
+Tensilica's assembler.
+
+         .begin [no-]schedule
+         .end [no-]schedule
+
+   This directive is ignored and has no effect on `as'.
+
+
+File: as.info,  Node: Longcalls Directive,  Next: Transform Directive,  Prev: Schedule Directive,  Up: Xtensa Directives
+
+8.34.5.2 longcalls
+..................
+
+The `longcalls' directive enables or disables function call relaxation.
+*Note Function Call Relaxation: Xtensa Call Relaxation.
+
+         .begin [no-]longcalls
+         .end [no-]longcalls
+
+   Call relaxation is disabled by default unless the `--longcalls'
+command-line option is specified.  The `longcalls' directive overrides
+the default determined by the command-line options.
+
+
+File: as.info,  Node: Transform Directive,  Next: Literal Directive,  Prev: Longcalls Directive,  Up: Xtensa Directives
+
+8.34.5.3 transform
+..................
+
+This directive enables or disables all assembler transformation,
+including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and
+optimization (*note Xtensa Optimizations: Xtensa Optimizations.).
+
+         .begin [no-]transform
+         .end [no-]transform
+
+   Transformations are enabled by default unless the `--no-transform'
+option is used.  The `transform' directive overrides the default
+determined by the command-line options.  An underscore opcode prefix,
+disabling transformation of that opcode, always takes precedence over
+both directives and command-line flags.
+
+
+File: as.info,  Node: Literal Directive,  Next: Literal Position Directive,  Prev: Transform Directive,  Up: Xtensa Directives
+
+8.34.5.4 literal
+................
+
+The `.literal' directive is used to define literal pool data, i.e.,
+read-only 32-bit data accessed via `L32R' instructions.
+
+         .literal LABEL, VALUE[, VALUE...]
+
+   This directive is similar to the standard `.word' directive, except
+that the actual location of the literal data is determined by the
+assembler and linker, not by the position of the `.literal' directive.
+Using this directive gives the assembler freedom to locate the literal
+data in the most appropriate place and possibly to combine identical
+literals.  For example, the code:
+
+         entry sp, 40
+         .literal .L1, sym
+         l32r    a4, .L1
+
+   can be used to load a pointer to the symbol `sym' into register
+`a4'.  The value of `sym' will not be placed between the `ENTRY' and
+`L32R' instructions; instead, the assembler puts the data in a literal
+pool.
+
+   Literal pools for absolute mode `L32R' instructions (*note Absolute
+Literals Directive::) are placed in a separate `.lit4' section.  By
+default literal pools for PC-relative mode `L32R' instructions are
+placed in a separate `.literal' section; however, when using the
+`--text-section-literals' option (*note Command Line Options: Xtensa
+Options.), the literal pools are placed in the current section.  These
+text section literal pools are created automatically before `ENTRY'
+instructions and manually after `.literal_position' directives (*note
+literal_position: Literal Position Directive.).  If there are no
+preceding `ENTRY' instructions, explicit `.literal_position' directives
+must be used to place the text section literal pools; otherwise, `as'
+will report an error.
+
+
+File: as.info,  Node: Literal Position Directive,  Next: Literal Prefix Directive,  Prev: Literal Directive,  Up: Xtensa Directives
+
+8.34.5.5 literal_position
+.........................
+
+When using `--text-section-literals' to place literals inline in the
+section being assembled, the `.literal_position' directive can be used
+to mark a potential location for a literal pool.
+
+         .literal_position
+
+   The `.literal_position' directive is ignored when the
+`--text-section-literals' option is not used or when `L32R'
+instructions use the absolute addressing mode.
+
+   The assembler will automatically place text section literal pools
+before `ENTRY' instructions, so the `.literal_position' directive is
+only needed to specify some other location for a literal pool.  You may
+need to add an explicit jump instruction to skip over an inline literal
+pool.
+
+   For example, an interrupt vector does not begin with an `ENTRY'
+instruction so the assembler will be unable to automatically find a good
+place to put a literal pool.  Moreover, the code for the interrupt
+vector must be at a specific starting address, so the literal pool
+cannot come before the start of the code.  The literal pool for the
+vector must be explicitly positioned in the middle of the vector (before
+any uses of the literals, due to the negative offsets used by
+PC-relative `L32R' instructions).  The `.literal_position' directive
+can be used to do this.  In the following code, the literal for `M'
+will automatically be aligned correctly and is placed after the
+unconditional jump.
+
+         .global M
+     code_start:
+         j continue
+         .literal_position
+         .align 4
+     continue:
+         movi    a4, M
+
+
+File: as.info,  Node: Literal Prefix Directive,  Next: Absolute Literals Directive,  Prev: Literal Position Directive,  Up: Xtensa Directives
+
+8.34.5.6 literal_prefix
+.......................
+
+The `literal_prefix' directive allows you to specify different sections
+to hold literals from different portions of an assembly file.  With
+this directive, a single assembly file can be used to generate code
+into multiple sections, including literals generated by the assembler.
+
+         .begin literal_prefix [NAME]
+         .end literal_prefix
+
+   By default the assembler places literal pools in sections separate
+from the instructions, using the default literal section names of
+`.literal' for PC-relative mode `L32R' instructions and `.lit4' for
+absolute mode `L32R' instructions (*note Absolute Literals
+Directive::).  The `literal_prefix' directive causes different literal
+sections to be used for the code inside the delimited region.  The new
+literal sections are determined by including NAME as a prefix to the
+default literal section names.  If the NAME argument is omitted, the
+literal sections revert to the defaults.  This directive has no effect
+when using the `--text-section-literals' option (*note Command Line
+Options: Xtensa Options.).
+
+   Except for two special cases, the assembler determines the new
+literal sections by simply prepending NAME to the default section names,
+resulting in `NAME.literal' and `NAME.lit4' sections.  The
+`literal_prefix' directive is often used with the name of the current
+text section as the prefix argument.  To facilitate this usage, the
+assembler uses special case rules when it recognizes NAME as a text
+section name.  First, if NAME ends with `.text', that suffix is not
+included in the literal section name.  For example, if NAME is
+`.iram0.text', then the literal sections will be `.iram0.literal' and
+`.iram0.lit4'.  Second, if NAME begins with `.gnu.linkonce.t.', then
+the literal section names are formed by replacing the `.t' substring
+with `.literal' and `.lit4'.  For example, if NAME is
+`.gnu.linkonce.t.func', the literal sections will be
+`.gnu.linkonce.literal.func' and `.gnu.linkonce.lit4.func'.
+
+
+File: as.info,  Node: Absolute Literals Directive,  Prev: Literal Prefix Directive,  Up: Xtensa Directives
+
+8.34.5.7 absolute-literals
+..........................
+
+The `absolute-literals' and `no-absolute-literals' directives control
+the absolute vs. PC-relative mode for `L32R' instructions.  These are
+relevant only for Xtensa configurations that include the absolute
+addressing option for `L32R' instructions.
+
+         .begin [no-]absolute-literals
+         .end [no-]absolute-literals
+
+   These directives do not change the `L32R' mode--they only cause the
+assembler to emit the appropriate kind of relocation for `L32R'
+instructions and to place the literal values in the appropriate section.
+To change the `L32R' mode, the program must write the `LITBASE' special
+register.  It is the programmer's responsibility to keep track of the
+mode and indicate to the assembler which mode is used in each region of
+code.
+
+   If the Xtensa configuration includes the absolute `L32R' addressing
+option, the default is to assume absolute `L32R' addressing unless the
+`--no-absolute-literals' command-line option is specified.  Otherwise,
+the default is to assume PC-relative `L32R' addressing.  The
+`absolute-literals' directive can then be used to override the default
+determined by the command-line options.
+
+
+File: as.info,  Node: Reporting Bugs,  Next: Acknowledgements,  Prev: Machine Dependencies,  Up: Top
+
+9 Reporting Bugs
+****************
+
+Your bug reports play an essential role in making `as' reliable.
+
+   Reporting a bug may help you by bringing a solution to your problem,
+or it may not.  But in any case the principal function of a bug report
+is to help the entire community by making the next version of `as' work
+better.  Bug reports are your contribution to the maintenance of `as'.
+
+   In order for a bug report to serve its purpose, you must include the
+information that enables us to fix the bug.
+
+* Menu:
+
+* Bug Criteria::                Have you found a bug?
+* Bug Reporting::               How to report bugs
+
+
+File: as.info,  Node: Bug Criteria,  Next: Bug Reporting,  Up: Reporting Bugs
+
+9.1 Have You Found a Bug?
+=========================
+
+If you are not sure whether you have found a bug, here are some
+guidelines:
+
+   * If the assembler gets a fatal signal, for any input whatever, that
+     is a `as' bug.  Reliable assemblers never crash.
+
+   * If `as' produces an error message for valid input, that is a bug.
+
+   * If `as' does not produce an error message for invalid input, that
+     is a bug.  However, you should note that your idea of "invalid
+     input" might be our idea of "an extension" or "support for
+     traditional practice".
+
+   * If you are an experienced user of assemblers, your suggestions for
+     improvement of `as' are welcome in any case.
+
+
+File: as.info,  Node: Bug Reporting,  Prev: Bug Criteria,  Up: Reporting Bugs
+
+9.2 How to Report Bugs
+======================
+
+A number of companies and individuals offer support for GNU products.
+If you obtained `as' from a support organization, we recommend you
+contact that organization first.
+
+   You can find contact information for many support companies and
+individuals in the file `etc/SERVICE' in the GNU Emacs distribution.
+
+   In any event, we also recommend that you send bug reports for `as'
+to `bug-binutils@gnu.org'.
+
+   The fundamental principle of reporting bugs usefully is this:
+*report all the facts*.  If you are not sure whether to state a fact or
+leave it out, state it!
+
+   Often people omit facts because they think they know what causes the
+problem and assume that some details do not matter.  Thus, you might
+assume that the name of a symbol you use in an example does not matter.
+Well, probably it does not, but one cannot be sure.  Perhaps the bug
+is a stray memory reference which happens to fetch from the location
+where that name is stored in memory; perhaps, if the name were
+different, the contents of that location would fool the assembler into
+doing the right thing despite the bug.  Play it safe and give a
+specific, complete example.  That is the easiest thing for you to do,
+and the most helpful.
+
+   Keep in mind that the purpose of a bug report is to enable us to fix
+the bug if it is new to us.  Therefore, always write your bug reports
+on the assumption that the bug has not been reported previously.
+
+   Sometimes people give a few sketchy facts and ask, "Does this ring a
+bell?"  This cannot help us fix a bug, so it is basically useless.  We
+respond by asking for enough details to enable us to investigate.  You
+might as well expedite matters by sending them to begin with.
+
+   To enable us to fix the bug, you should include all these things:
+
+   * The version of `as'.  `as' announces it if you start it with the
+     `--version' argument.
+
+     Without this, we will not know whether there is any point in
+     looking for the bug in the current version of `as'.
+
+   * Any patches you may have applied to the `as' source.
+
+   * The type of machine you are using, and the operating system name
+     and version number.
+
+   * What compiler (and its version) was used to compile `as'--e.g.
+     "`gcc-2.7'".
+
+   * The command arguments you gave the assembler to assemble your
+     example and observe the bug.  To guarantee you will not omit
+     something important, list them all.  A copy of the Makefile (or
+     the output from make) is sufficient.
+
+     If we were to try to guess the arguments, we would probably guess
+     wrong and then we might not encounter the bug.
+
+   * A complete input file that will reproduce the bug.  If the bug is
+     observed when the assembler is invoked via a compiler, send the
+     assembler source, not the high level language source.  Most
+     compilers will produce the assembler source when run with the `-S'
+     option.  If you are using `gcc', use the options `-v
+     --save-temps'; this will save the assembler source in a file with
+     an extension of `.s', and also show you exactly how `as' is being
+     run.
+
+   * A description of what behavior you observe that you believe is
+     incorrect.  For example, "It gets a fatal signal."
+
+     Of course, if the bug is that `as' gets a fatal signal, then we
+     will certainly notice it.  But if the bug is incorrect output, we
+     might not notice unless it is glaringly wrong.  You might as well
+     not give us a chance to make a mistake.
+
+     Even if the problem you experience is a fatal signal, you should
+     still say so explicitly.  Suppose something strange is going on,
+     such as, your copy of `as' is out of synch, or you have
+     encountered a bug in the C library on your system.  (This has
+     happened!)  Your copy might crash and ours would not.  If you told
+     us to expect a crash, then when ours fails to crash, we would know
+     that the bug was not happening for us.  If you had not told us to
+     expect a crash, then we would not be able to draw any conclusion
+     from our observations.
+
+   * If you wish to suggest changes to the `as' source, send us context
+     diffs, as generated by `diff' with the `-u', `-c', or `-p' option.
+     Always send diffs from the old file to the new file.  If you even
+     discuss something in the `as' source, refer to it by context, not
+     by line number.
+
+     The line numbers in our development sources will not match those
+     in your sources.  Your line numbers would convey no useful
+     information to us.
+
+   Here are some things that are not necessary:
+
+   * A description of the envelope of the bug.
+
+     Often people who encounter a bug spend a lot of time investigating
+     which changes to the input file will make the bug go away and which
+     changes will not affect it.
+
+     This is often time consuming and not very useful, because the way
+     we will find the bug is by running a single example under the
+     debugger with breakpoints, not by pure deduction from a series of
+     examples.  We recommend that you save your time for something else.
+
+     Of course, if you can find a simpler example to report _instead_
+     of the original one, that is a convenience for us.  Errors in the
+     output will be easier to spot, running under the debugger will take
+     less time, and so on.
+
+     However, simplification is not vital; if you do not want to do
+     this, report the bug anyway and send us the entire test case you
+     used.
+
+   * A patch for the bug.
+
+     A patch for the bug does help us if it is a good one.  But do not
+     omit the necessary information, such as the test case, on the
+     assumption that a patch is all we need.  We might see problems
+     with your patch and decide to fix the problem another way, or we
+     might not understand it at all.
+
+     Sometimes with a program as complicated as `as' it is very hard to
+     construct an example that will make the program follow a certain
+     path through the code.  If you do not send us the example, we will
+     not be able to construct one, so we will not be able to verify
+     that the bug is fixed.
+
+     And if we cannot understand what bug you are trying to fix, or why
+     your patch should be an improvement, we will not install it.  A
+     test case will help us to understand.
+
+   * A guess about what the bug is or what it depends on.
+
+     Such guesses are usually wrong.  Even we cannot guess right about
+     such things without first using the debugger to find the facts.
+
+
+File: as.info,  Node: Acknowledgements,  Next: GNU Free Documentation License,  Prev: Reporting Bugs,  Up: Top
+
+10 Acknowledgements
+*******************
+
+If you have contributed to GAS and your name isn't listed here, it is
+not meant as a slight.  We just don't know about it.  Send mail to the
+maintainer, and we'll correct the situation.  Currently the maintainer
+is Ken Raeburn (email address `raeburn@cygnus.com').
+
+   Dean Elsner wrote the original GNU assembler for the VAX.(1)
+
+   Jay Fenlason maintained GAS for a while, adding support for
+GDB-specific debug information and the 68k series machines, most of the
+preprocessing pass, and extensive changes in `messages.c',
+`input-file.c', `write.c'.
+
+   K. Richard Pixley maintained GAS for a while, adding various
+enhancements and many bug fixes, including merging support for several
+processors, breaking GAS up to handle multiple object file format back
+ends (including heavy rewrite, testing, an integration of the coff and
+b.out back ends), adding configuration including heavy testing and
+verification of cross assemblers and file splits and renaming,
+converted GAS to strictly ANSI C including full prototypes, added
+support for m680[34]0 and cpu32, did considerable work on i960
+including a COFF port (including considerable amounts of reverse
+engineering), a SPARC opcode file rewrite, DECstation, rs6000, and
+hp300hpux host ports, updated "know" assertions and made them work,
+much other reorganization, cleanup, and lint.
+
+   Ken Raeburn wrote the high-level BFD interface code to replace most
+of the code in format-specific I/O modules.
+
+   The original VMS support was contributed by David L. Kashtan.  Eric
+Youngdale has done much work with it since.
+
+   The Intel 80386 machine description was written by Eliot Dresselhaus.
+
+   Minh Tran-Le at IntelliCorp contributed some AIX 386 support.
+
+   The Motorola 88k machine description was contributed by Devon Bowen
+of Buffalo University and Torbjorn Granlund of the Swedish Institute of
+Computer Science.
+
+   Keith Knowles at the Open Software Foundation wrote the original
+MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format
+support (which hasn't been merged in yet).  Ralph Campbell worked with
+the MIPS code to support a.out format.
+
+   Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
+tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
+Steve Chamberlain of Cygnus Support.  Steve also modified the COFF back
+end to use BFD for some low-level operations, for use with the H8/300
+and AMD 29k targets.
+
+   John Gilmore built the AMD 29000 support, added `.include' support,
+and simplified the configuration of which versions accept which
+directives.  He updated the 68k machine description so that Motorola's
+opcodes always produced fixed-size instructions (e.g., `jsr'), while
+synthetic instructions remained shrinkable (`jbsr').  John fixed many
+bugs, including true tested cross-compilation support, and one bug in
+relaxation that took a week and required the proverbial one-bit fix.
+
+   Ian Lance Taylor of Cygnus Support merged the Motorola and MIT
+syntax for the 68k, completed support for some COFF targets (68k, i386
+SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets,
+wrote the initial RS/6000 and PowerPC assembler, and made a few other
+minor patches.
+
+   Steve Chamberlain made GAS able to generate listings.
+
+   Hewlett-Packard contributed support for the HP9000/300.
+
+   Jeff Law wrote GAS and BFD support for the native HPPA object format
+(SOM) along with a fairly extensive HPPA testsuite (for both SOM and
+ELF object formats).  This work was supported by both the Center for
+Software Science at the University of Utah and Cygnus Support.
+
+   Support for ELF format files has been worked on by Mark Eichin of
+Cygnus Support (original, incomplete implementation for SPARC), Pete
+Hoogenboom and Jeff Law at the University of Utah (HPPA mainly),
+Michael Meissner of the Open Software Foundation (i386 mainly), and Ken
+Raeburn of Cygnus Support (sparc, and some initial 64-bit support).
+
+   Linas Vepstas added GAS support for the ESA/390 "IBM 370"
+architecture.
+
+   Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote
+GAS and BFD support for openVMS/Alpha.
+
+   Timothy Wall, Michael Hayes, and Greg Smart contributed to the
+various tic* flavors.
+
+   David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from
+Tensilica, Inc. added support for Xtensa processors.
+
+   Several engineers at Cygnus Support have also provided many small
+bug fixes and configuration enhancements.
+
+   Many others have contributed large or small bugfixes and
+enhancements.  If you have contributed significant work and are not
+mentioned on this list, and want to be, let us know.  Some of the
+history has been lost; we are not intentionally leaving anyone out.
+
+   ---------- Footnotes ----------
+
+   (1) Any more details?
+
+
+File: as.info,  Node: GNU Free Documentation License,  Next: Index,  Prev: Acknowledgements,  Up: Top
+
+Appendix A GNU Free Documentation License
+*****************************************
+
+                        Version 1.1, March 2000
+
+     Copyright (C) 2000, 2003 Free Software Foundation, Inc.
+     51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
+
+     Everyone is permitted to copy and distribute verbatim copies
+     of this license document, but changing it is not allowed.
+
+
+  0. PREAMBLE
+
+     The purpose of this License is to make a manual, textbook, or other
+     written document "free" in the sense of freedom: to assure everyone
+     the effective freedom to copy and redistribute it, with or without
+     modifying it, either commercially or noncommercially.  Secondarily,
+     this License preserves for the author and publisher a way to get
+     credit for their work, while not being considered responsible for
+     modifications made by others.
+
+     This License is a kind of "copyleft", which means that derivative
+     works of the document must themselves be free in the same sense.
+     It complements the GNU General Public License, which is a copyleft
+     license designed for free software.
+
+     We have designed this License in order to use it for manuals for
+     free software, because free software needs free documentation: a
+     free program should come with manuals providing the same freedoms
+     that the software does.  But this License is not limited to
+     software manuals; it can be used for any textual work, regardless
+     of subject matter or whether it is published as a printed book.
+     We recommend this License principally for works whose purpose is
+     instruction or reference.
+
+
+  1. APPLICABILITY AND DEFINITIONS
+
+     This License applies to any manual or other work that contains a
+     notice placed by the copyright holder saying it can be distributed
+     under the terms of this License.  The "Document", below, refers to
+     any such manual or work.  Any member of the public is a licensee,
+     and is addressed as "you."
+
+     A "Modified Version" of the Document means any work containing the
+     Document or a portion of it, either copied verbatim, or with
+     modifications and/or translated into another language.
+
+     A "Secondary Section" is a named appendix or a front-matter
+     section of the Document that deals exclusively with the
+     relationship of the publishers or authors of the Document to the
+     Document's overall subject (or to related matters) and contains
+     nothing that could fall directly within that overall subject.
+     (For example, if the Document is in part a textbook of
+     mathematics, a Secondary Section may not explain any mathematics.)
+     The relationship could be a matter of historical connection with
+     the subject or with related matters, or of legal, commercial,
+     philosophical, ethical or political position regarding them.
+
+     The "Invariant Sections" are certain Secondary Sections whose
+     titles are designated, as being those of Invariant Sections, in
+     the notice that says that the Document is released under this
+     License.
+
+     The "Cover Texts" are certain short passages of text that are
+     listed, as Front-Cover Texts or Back-Cover Texts, in the notice
+     that says that the Document is released under this License.
+
+     A "Transparent" copy of the Document means a machine-readable copy,
+     represented in a format whose specification is available to the
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+
+     Examples of suitable formats for Transparent copies include plain
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+     Opaque formats include PostScript, PDF, proprietary formats that
+     can be read and edited only by proprietary word processors, SGML
+     or XML for which the DTD and/or processing tools are not generally
+     available, and the machine-generated HTML produced by some word
+     processors for output purposes only.
+
+     The "Title Page" means, for a printed book, the title page itself,
+     plus such following pages as are needed to hold, legibly, the
+     material this License requires to appear in the title page.  For
+     works in formats which do not have any title page as such, "Title
+     Page" means the text near the most prominent appearance of the
+     work's title, preceding the beginning of the body of the text.
+
+  2. VERBATIM COPYING
+
+     You may copy and distribute the Document in any medium, either
+     commercially or noncommercially, provided that this License, the
+     copyright notices, and the license notice saying this License
+     applies to the Document are reproduced in all copies, and that you
+     add no other conditions whatsoever to those of this License.  You
+     may not use technical measures to obstruct or control the reading
+     or further copying of the copies you make or distribute.  However,
+     you may accept compensation in exchange for copies.  If you
+     distribute a large enough number of copies you must also follow
+     the conditions in section 3.
+
+     You may also lend copies, under the same conditions stated above,
+     and you may publicly display copies.
+
+  3. COPYING IN QUANTITY
+
+     If you publish printed copies of the Document numbering more than
+     100, and the Document's license notice requires Cover Texts, you
+     must enclose the copies in covers that carry, clearly and legibly,
+     all these Cover Texts: Front-Cover Texts on the front cover, and
+     Back-Cover Texts on the back cover.  Both covers must also clearly
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+     front cover must present the full title with all words of the
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+     on the covers in addition.  Copying with changes limited to the
+     covers, as long as they preserve the title of the Document and
+     satisfy these conditions, can be treated as verbatim copying in
+     other respects.
+
+     If the required texts for either cover are too voluminous to fit
+     legibly, you should put the first ones listed (as many as fit
+     reasonably) on the actual cover, and continue the rest onto
+     adjacent pages.
+
+     If you publish or distribute Opaque copies of the Document
+     numbering more than 100, you must either include a
+     machine-readable Transparent copy along with each Opaque copy, or
+     state in or with each Opaque copy a publicly-accessible
+     computer-network location containing a complete Transparent copy
+     of the Document, free of added material, which the general
+     network-using public has access to download anonymously at no
+     charge using public-standard network protocols.  If you use the
+     latter option, you must take reasonably prudent steps, when you
+     begin distribution of Opaque copies in quantity, to ensure that
+     this Transparent copy will remain thus accessible at the stated
+     location until at least one year after the last time you
+     distribute an Opaque copy (directly or through your agents or
+     retailers) of that edition to the public.
+
+     It is requested, but not required, that you contact the authors of
+     the Document well before redistributing any large number of
+     copies, to give them a chance to provide you with an updated
+     version of the Document.
+
+  4. MODIFICATIONS
+
+     You may copy and distribute a Modified Version of the Document
+     under the conditions of sections 2 and 3 above, provided that you
+     release the Modified Version under precisely this License, with
+     the Modified Version filling the role of the Document, thus
+     licensing distribution and modification of the Modified Version to
+     whoever possesses a copy of it.  In addition, you must do these
+     things in the Modified Version:
+
+     A. Use in the Title Page (and on the covers, if any) a title
+     distinct    from that of the Document, and from those of previous
+     versions    (which should, if there were any, be listed in the
+     History section    of the Document).  You may use the same title
+     as a previous version    if the original publisher of that version
+     gives permission.
+     B. List on the Title Page, as authors, one or more persons or
+     entities    responsible for authorship of the modifications in the
+     Modified    Version, together with at least five of the principal
+     authors of the    Document (all of its principal authors, if it
+     has less than five).
+     C. State on the Title page the name of the publisher of the
+     Modified Version, as the publisher.
+     D. Preserve all the copyright notices of the Document.
+     E. Add an appropriate copyright notice for your modifications
+     adjacent to the other copyright notices.
+     F. Include, immediately after the copyright notices, a license
+     notice    giving the public permission to use the Modified Version
+     under the    terms of this License, in the form shown in the
+     Addendum below.
+     G. Preserve in that license notice the full lists of Invariant
+     Sections    and required Cover Texts given in the Document's
+     license notice.
+     H. Include an unaltered copy of this License.
+     I. Preserve the section entitled "History", and its title, and add
+     to    it an item stating at least the title, year, new authors, and
+       publisher of the Modified Version as given on the Title Page.
+     If    there is no section entitled "History" in the Document,
+     create one    stating the title, year, authors, and publisher of
+     the Document as    given on its Title Page, then add an item
+     describing the Modified    Version as stated in the previous
+     sentence.
+     J. Preserve the network location, if any, given in the Document for
+       public access to a Transparent copy of the Document, and
+     likewise    the network locations given in the Document for
+     previous versions    it was based on.  These may be placed in the
+     "History" section.     You may omit a network location for a work
+     that was published at    least four years before the Document
+     itself, or if the original    publisher of the version it refers
+     to gives permission.
+     K. In any section entitled "Acknowledgements" or "Dedications",
+     preserve the section's title, and preserve in the section all the
+      substance and tone of each of the contributor acknowledgements
+     and/or dedications given therein.
+     L. Preserve all the Invariant Sections of the Document,
+     unaltered in their text and in their titles.  Section numbers
+     or the equivalent are not considered part of the section titles.
+     M. Delete any section entitled "Endorsements."  Such a section
+     may not be included in the Modified Version.
+     N. Do not retitle any existing section as "Endorsements"    or to
+     conflict in title with any Invariant Section.
+
+     If the Modified Version includes new front-matter sections or
+     appendices that qualify as Secondary Sections and contain no
+     material copied from the Document, you may at your option
+     designate some or all of these sections as invariant.  To do this,
+     add their titles to the list of Invariant Sections in the Modified
+     Version's license notice.  These titles must be distinct from any
+     other section titles.
+
+     You may add a section entitled "Endorsements", provided it contains
+     nothing but endorsements of your Modified Version by various
+     parties-for example, statements of peer review or that the text has
+     been approved by an organization as the authoritative definition
+     of a standard.
+
+     You may add a passage of up to five words as a Front-Cover Text,
+     and a passage of up to 25 words as a Back-Cover Text, to the end
+     of the list of Cover Texts in the Modified Version.  Only one
+     passage of Front-Cover Text and one of Back-Cover Text may be
+     added by (or through arrangements made by) any one entity.  If the
+     Document already includes a cover text for the same cover,
+     previously added by you or by arrangement made by the same entity
+     you are acting on behalf of, you may not add another; but you may
+     replace the old one, on explicit permission from the previous
+     publisher that added the old one.
+
+     The author(s) and publisher(s) of the Document do not by this
+     License give permission to use their names for publicity for or to
+     assert or imply endorsement of any Modified Version.
+
+  5. COMBINING DOCUMENTS
+
+     You may combine the Document with other documents released under
+     this License, under the terms defined in section 4 above for
+     modified versions, provided that you include in the combination
+     all of the Invariant Sections of all of the original documents,
+     unmodified, and list them all as Invariant Sections of your
+     combined work in its license notice.
+
+     The combined work need only contain one copy of this License, and
+     multiple identical Invariant Sections may be replaced with a single
+     copy.  If there are multiple Invariant Sections with the same name
+     but different contents, make the title of each such section unique
+     by adding at the end of it, in parentheses, the name of the
+     original author or publisher of that section if known, or else a
+     unique number.  Make the same adjustment to the section titles in
+     the list of Invariant Sections in the license notice of the
+     combined work.
+
+     In the combination, you must combine any sections entitled
+     "History" in the various original documents, forming one section
+     entitled "History"; likewise combine any sections entitled
+     "Acknowledgements", and any sections entitled "Dedications."  You
+     must delete all sections entitled "Endorsements."
+
+  6. COLLECTIONS OF DOCUMENTS
+
+     You may make a collection consisting of the Document and other
+     documents released under this License, and replace the individual
+     copies of this License in the various documents with a single copy
+     that is included in the collection, provided that you follow the
+     rules of this License for verbatim copying of each of the
+     documents in all other respects.
+
+     You may extract a single document from such a collection, and
+     distribute it individually under this License, provided you insert
+     a copy of this License into the extracted document, and follow
+     this License in all other respects regarding verbatim copying of
+     that document.
+
+  7. AGGREGATION WITH INDEPENDENT WORKS
+
+     A compilation of the Document or its derivatives with other
+     separate and independent documents or works, in or on a volume of
+     a storage or distribution medium, does not as a whole count as a
+     Modified Version of the Document, provided no compilation
+     copyright is claimed for the compilation.  Such a compilation is
+     called an "aggregate", and this License does not apply to the
+     other self-contained works thus compiled with the Document, on
+     account of their being thus compiled, if they are not themselves
+     derivative works of the Document.
+
+     If the Cover Text requirement of section 3 is applicable to these
+     copies of the Document, then if the Document is less than one
+     quarter of the entire aggregate, the Document's Cover Texts may be
+     placed on covers that surround only the Document within the
+     aggregate.  Otherwise they must appear on covers around the whole
+     aggregate.
+
+  8. TRANSLATION
+
+     Translation is considered a kind of modification, so you may
+     distribute translations of the Document under the terms of section
+     4.  Replacing Invariant Sections with translations requires special
+     permission from their copyright holders, but you may include
+     translations of some or all Invariant Sections in addition to the
+     original versions of these Invariant Sections.  You may include a
+     translation of this License provided that you also include the
+     original English version of this License.  In case of a
+     disagreement between the translation and the original English
+     version of this License, the original English version will prevail.
+
+  9. TERMINATION
+
+     You may not copy, modify, sublicense, or distribute the Document
+     except as expressly provided for under this License.  Any other
+     attempt to copy, modify, sublicense or distribute the Document is
+     void, and will automatically terminate your rights under this
+     License.  However, parties who have received copies, or rights,
+     from you under this License will not have their licenses
+     terminated so long as such parties remain in full compliance.
+
+ 10. FUTURE REVISIONS OF THIS LICENSE
+
+     The Free Software Foundation may publish new, revised versions of
+     the GNU Free Documentation License from time to time.  Such new
+     versions will be similar in spirit to the present version, but may
+     differ in detail to address new problems or concerns.  See
+     http://www.gnu.org/copyleft/.
+
+     Each version of the License is given a distinguishing version
+     number.  If the Document specifies that a particular numbered
+     version of this License "or any later version" applies to it, you
+     have the option of following the terms and conditions either of
+     that specified version or of any later version that has been
+     published (not as a draft) by the Free Software Foundation.  If
+     the Document does not specify a version number of this License,
+     you may choose any version ever published (not as a draft) by the
+     Free Software Foundation.
+
+
+ADDENDUM: How to use this License for your documents
+====================================================
+
+To use this License in a document you have written, include a copy of
+the License in the document and put the following copyright and license
+notices just after the title page:
+
+     Copyright (C)  YEAR  YOUR NAME.
+     Permission is granted to copy, distribute and/or modify this document
+     under the terms of the GNU Free Documentation License, Version 1.1
+     or any later version published by the Free Software Foundation;
+     with the Invariant Sections being LIST THEIR TITLES, with the
+     Front-Cover Texts being LIST, and with the Back-Cover Texts being LIST.
+     A copy of the license is included in the section entitled "GNU
+     Free Documentation License."
+
+   If you have no Invariant Sections, write "with no Invariant Sections"
+instead of saying which ones are invariant.  If you have no Front-Cover
+Texts, write "no Front-Cover Texts" instead of "Front-Cover Texts being
+LIST"; likewise for Back-Cover Texts.
+
+   If your document contains nontrivial examples of program code, we
+recommend releasing these examples in parallel under your choice of
+free software license, such as the GNU General Public License, to
+permit their use in free software.
+
+
+File: as.info,  Node: Index,  Prev: GNU Free Documentation License,  Up: Top
+
+Index
+*****
+
+
+* Menu:
+
+* #:                                     Comments.            (line  38)
+* #APP:                                  Preprocessing.       (line  27)
+* #NO_APP:                               Preprocessing.       (line  27)
+* $ in symbol names <1>:                 SH64-Chars.          (line  10)
+* $ in symbol names <2>:                 SH-Chars.            (line  10)
+* $ in symbol names <3>:                 D30V-Chars.          (line  63)
+* $ in symbol names:                     D10V-Chars.          (line  46)
+* $a:                                    ARM Mapping Symbols. (line   9)
+* $acos math builtin, TIC54X:            TIC54X-Builtins.     (line  10)
+* $asin math builtin, TIC54X:            TIC54X-Builtins.     (line  13)
+* $atan math builtin, TIC54X:            TIC54X-Builtins.     (line  16)
+* $atan2 math builtin, TIC54X:           TIC54X-Builtins.     (line  19)
+* $ceil math builtin, TIC54X:            TIC54X-Builtins.     (line  22)
+* $cos math builtin, TIC54X:             TIC54X-Builtins.     (line  28)
+* $cosh math builtin, TIC54X:            TIC54X-Builtins.     (line  25)
+* $cvf math builtin, TIC54X:             TIC54X-Builtins.     (line  31)
+* $cvi math builtin, TIC54X:             TIC54X-Builtins.     (line  34)
+* $d:                                    ARM Mapping Symbols. (line  15)
+* $exp math builtin, TIC54X:             TIC54X-Builtins.     (line  37)
+* $fabs math builtin, TIC54X:            TIC54X-Builtins.     (line  40)
+* $firstch subsym builtin, TIC54X:       TIC54X-Macros.       (line  26)
+* $floor math builtin, TIC54X:           TIC54X-Builtins.     (line  43)
+* $fmod math builtin, TIC54X:            TIC54X-Builtins.     (line  47)
+* $int math builtin, TIC54X:             TIC54X-Builtins.     (line  50)
+* $iscons subsym builtin, TIC54X:        TIC54X-Macros.       (line  43)
+* $isdefed subsym builtin, TIC54X:       TIC54X-Macros.       (line  34)
+* $ismember subsym builtin, TIC54X:      TIC54X-Macros.       (line  38)
+* $isname subsym builtin, TIC54X:        TIC54X-Macros.       (line  47)
+* $isreg subsym builtin, TIC54X:         TIC54X-Macros.       (line  50)
+* $lastch subsym builtin, TIC54X:        TIC54X-Macros.       (line  30)
+* $ldexp math builtin, TIC54X:           TIC54X-Builtins.     (line  53)
+* $log math builtin, TIC54X:             TIC54X-Builtins.     (line  59)
+* $log10 math builtin, TIC54X:           TIC54X-Builtins.     (line  56)
+* $max math builtin, TIC54X:             TIC54X-Builtins.     (line  62)
+* $min math builtin, TIC54X:             TIC54X-Builtins.     (line  65)
+* $pow math builtin, TIC54X:             TIC54X-Builtins.     (line  68)
+* $round math builtin, TIC54X:           TIC54X-Builtins.     (line  71)
+* $sgn math builtin, TIC54X:             TIC54X-Builtins.     (line  74)
+* $sin math builtin, TIC54X:             TIC54X-Builtins.     (line  77)
+* $sinh math builtin, TIC54X:            TIC54X-Builtins.     (line  80)
+* $sqrt math builtin, TIC54X:            TIC54X-Builtins.     (line  83)
+* $structacc subsym builtin, TIC54X:     TIC54X-Macros.       (line  57)
+* $structsz subsym builtin, TIC54X:      TIC54X-Macros.       (line  54)
+* $symcmp subsym builtin, TIC54X:        TIC54X-Macros.       (line  23)
+* $symlen subsym builtin, TIC54X:        TIC54X-Macros.       (line  20)
+* $t:                                    ARM Mapping Symbols. (line  12)
+* $tan math builtin, TIC54X:             TIC54X-Builtins.     (line  86)
+* $tanh math builtin, TIC54X:            TIC54X-Builtins.     (line  89)
+* $trunc math builtin, TIC54X:           TIC54X-Builtins.     (line  92)
+* -+ option, VAX/VMS:                    VAX-Opts.            (line  71)
+* --:                                    Command Line.        (line  10)
+* --32 option, i386:                     i386-Options.        (line   8)
+* --32 option, x86-64:                   i386-Options.        (line   8)
+* --64 option, i386:                     i386-Options.        (line   8)
+* --64 option, x86-64:                   i386-Options.        (line   8)
+* --absolute-literals:                   Xtensa Options.      (line  22)
+* --allow-reg-prefix:                    SH Options.          (line   9)
+* --alternate:                           alternate.           (line   6)
+* --base-size-default-16:                M68K-Opts.           (line  70)
+* --base-size-default-32:                M68K-Opts.           (line  70)
+* --big:                                 SH Options.          (line   9)
+* --bitwise-or option, M680x0:           M68K-Opts.           (line  63)
+* --disp-size-default-16:                M68K-Opts.           (line  79)
+* --disp-size-default-32:                M68K-Opts.           (line  79)
+* --divide option, i386:                 i386-Options.        (line  24)
+* --dsp:                                 SH Options.          (line   9)
+* --emulation=crisaout command line option, CRIS: CRIS-Opts.  (line   9)
+* --emulation=criself command line option, CRIS: CRIS-Opts.   (line   9)
+* --enforce-aligned-data:                Sparc-Aligned-Data.  (line  11)
+* --fatal-warnings:                      W.                   (line  16)
+* --fixed-special-register-names command line option, MMIX: MMIX-Opts.
+                                                              (line   8)
+* --force-long-branchs:                  M68HC11-Opts.        (line  69)
+* --generate-example:                    M68HC11-Opts.        (line  86)
+* --globalize-symbols command line option, MMIX: MMIX-Opts.   (line  12)
+* --gnu-syntax command line option, MMIX: MMIX-Opts.          (line  16)
+* --hash-size=NUMBER:                    Overview.            (line 297)
+* --linker-allocated-gregs command line option, MMIX: MMIX-Opts.
+                                                              (line  67)
+* --listing-cont-lines:                  listing.             (line  33)
+* --listing-lhs-width:                   listing.             (line  15)
+* --listing-lhs-width2:                  listing.             (line  20)
+* --listing-rhs-width:                   listing.             (line  27)
+* --little:                              SH Options.          (line   9)
+* --longcalls:                           Xtensa Options.      (line  36)
+* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts.  (line  33)
+* --MD:                                  MD.                  (line   6)
+* --mul-bug-abort command line option, CRIS: CRIS-Opts.       (line  61)
+* --no-absolute-literals:                Xtensa Options.      (line  22)
+* --no-expand command line option, MMIX: MMIX-Opts.           (line  31)
+* --no-longcalls:                        Xtensa Options.      (line  36)
+* --no-merge-gregs command line option, MMIX: MMIX-Opts.      (line  36)
+* --no-mul-bug-abort command line option, CRIS: CRIS-Opts.    (line  61)
+* --no-predefined-syms command line option, MMIX: MMIX-Opts.  (line  22)
+* --no-pushj-stubs command line option, MMIX: MMIX-Opts.      (line  54)
+* --no-stubs command line option, MMIX:  MMIX-Opts.           (line  54)
+* --no-target-align:                     Xtensa Options.      (line  29)
+* --no-text-section-literals:            Xtensa Options.      (line   9)
+* --no-transform:                        Xtensa Options.      (line  45)
+* --no-underscore command line option, CRIS: CRIS-Opts.       (line  15)
+* --no-warn:                             W.                   (line  11)
+* --pcrel:                               M68K-Opts.           (line  91)
+* --pic command line option, CRIS:       CRIS-Opts.           (line  27)
+* --print-insn-syntax:                   M68HC11-Opts.        (line  75)
+* --print-opcodes:                       M68HC11-Opts.        (line  79)
+* --register-prefix-optional option, M680x0: M68K-Opts.       (line  50)
+* --relax:                               SH Options.          (line   9)
+* --relax command line option, MMIX:     MMIX-Opts.           (line  19)
+* --rename-section:                      Xtensa Options.      (line  53)
+* --renesas:                             SH Options.          (line   9)
+* --short-branchs:                       M68HC11-Opts.        (line  54)
+* --small:                               SH Options.          (line   9)
+* --statistics:                          statistics.          (line   6)
+* --strict-direct-mode:                  M68HC11-Opts.        (line  44)
+* --target-align:                        Xtensa Options.      (line  29)
+* --text-section-literals:               Xtensa Options.      (line   9)
+* --traditional-format:                  traditional-format.  (line   6)
+* --transform:                           Xtensa Options.      (line  45)
+* --underscore command line option, CRIS: CRIS-Opts.          (line  15)
+* --warn:                                W.                   (line  19)
+* -1 option, VAX/VMS:                    VAX-Opts.            (line  77)
+* -32addr command line option, Alpha:    Alpha Options.       (line  50)
+* -a:                                    a.                   (line   6)
+* -A options, i960:                      Options-i960.        (line   6)
+* -ac:                                   a.                   (line   6)
+* -ad:                                   a.                   (line   6)
+* -ah:                                   a.                   (line   6)
+* -al:                                   a.                   (line   6)
+* -an:                                   a.                   (line   6)
+* -as:                                   a.                   (line   6)
+* -Asparclet:                            Sparc-Opts.          (line  25)
+* -Asparclite:                           Sparc-Opts.          (line  25)
+* -Av6:                                  Sparc-Opts.          (line  25)
+* -Av8:                                  Sparc-Opts.          (line  25)
+* -Av9:                                  Sparc-Opts.          (line  25)
+* -Av9a:                                 Sparc-Opts.          (line  25)
+* -b option, i960:                       Options-i960.        (line  22)
+* -big option, M32R:                     M32R-Opts.           (line  35)
+* -construct-floats:                     MIPS Opts.           (line 157)
+* -D:                                    D.                   (line   6)
+* -D, ignored on VAX:                    VAX-Opts.            (line  11)
+* -d, VAX option:                        VAX-Opts.            (line  16)
+* -eabi= command line option, ARM:       ARM Options.         (line 107)
+* -EB command line option, ARC:          ARC Options.         (line  31)
+* -EB command line option, ARM:          ARM Options.         (line 112)
+* -EB option (MIPS):                     MIPS Opts.           (line  13)
+* -EB option, M32R:                      M32R-Opts.           (line  39)
+* -EL command line option, ARC:          ARC Options.         (line  35)
+* -EL command line option, ARM:          ARM Options.         (line 116)
+* -EL option (MIPS):                     MIPS Opts.           (line  13)
+* -EL option, M32R:                      M32R-Opts.           (line  32)
+* -f:                                    f.                   (line   6)
+* -F command line option, Alpha:         Alpha Options.       (line  50)
+* -G command line option, Alpha:         Alpha Options.       (line  46)
+* -g command line option, Alpha:         Alpha Options.       (line  40)
+* -G option (MIPS):                      MIPS Opts.           (line   8)
+* -H option, VAX/VMS:                    VAX-Opts.            (line  81)
+* -h option, VAX/VMS:                    VAX-Opts.            (line  45)
+* -I PATH:                               I.                   (line   6)
+* -ignore-parallel-conflicts option, M32RX: M32R-Opts.        (line  87)
+* -Ip option, M32RX:                     M32R-Opts.           (line  97)
+* -J, ignored on VAX:                    VAX-Opts.            (line  27)
+* -K:                                    K.                   (line   6)
+* -k command line option, ARM:           ARM Options.         (line 120)
+* -KPIC option, M32R:                    M32R-Opts.           (line  42)
+* -L:                                    L.                   (line   6)
+* -l option, M680x0:                     M68K-Opts.           (line  38)
+* -little option, M32R:                  M32R-Opts.           (line  27)
+* -M:                                    M.                   (line   6)
+* -m11/03:                               PDP-11-Options.      (line 140)
+* -m11/04:                               PDP-11-Options.      (line 143)
+* -m11/05:                               PDP-11-Options.      (line 146)
+* -m11/10:                               PDP-11-Options.      (line 146)
+* -m11/15:                               PDP-11-Options.      (line 149)
+* -m11/20:                               PDP-11-Options.      (line 149)
+* -m11/21:                               PDP-11-Options.      (line 152)
+* -m11/23:                               PDP-11-Options.      (line 155)
+* -m11/24:                               PDP-11-Options.      (line 155)
+* -m11/34:                               PDP-11-Options.      (line 158)
+* -m11/34a:                              PDP-11-Options.      (line 161)
+* -m11/35:                               PDP-11-Options.      (line 164)
+* -m11/40:                               PDP-11-Options.      (line 164)
+* -m11/44:                               PDP-11-Options.      (line 167)
+* -m11/45:                               PDP-11-Options.      (line 170)
+* -m11/50:                               PDP-11-Options.      (line 170)
+* -m11/53:                               PDP-11-Options.      (line 173)
+* -m11/55:                               PDP-11-Options.      (line 170)
+* -m11/60:                               PDP-11-Options.      (line 176)
+* -m11/70:                               PDP-11-Options.      (line 170)
+* -m11/73:                               PDP-11-Options.      (line 173)
+* -m11/83:                               PDP-11-Options.      (line 173)
+* -m11/84:                               PDP-11-Options.      (line 173)
+* -m11/93:                               PDP-11-Options.      (line 173)
+* -m11/94:                               PDP-11-Options.      (line 173)
+* -m16c option, M16C:                    M32C-Opts.           (line  12)
+* -m32c option, M32C:                    M32C-Opts.           (line   9)
+* -m32r option, M32R:                    M32R-Opts.           (line  21)
+* -m32rx option, M32R2:                  M32R-Opts.           (line  17)
+* -m32rx option, M32RX:                  M32R-Opts.           (line   9)
+* -m68000 and related options:           M68K-Opts.           (line 103)
+* -m68hc11:                              M68HC11-Opts.        (line   9)
+* -m68hc12:                              M68HC11-Opts.        (line  14)
+* -m68hcs12:                             M68HC11-Opts.        (line  21)
+* -m[no-]68851 command line option, M680x0: M68K-Opts.        (line  20)
+* -m[no-]68881 command line option, M680x0: M68K-Opts.        (line  20)
+* -m[no-]div command line option, M680x0: M68K-Opts.          (line  20)
+* -m[no-]emac command line option, M680x0: M68K-Opts.         (line  20)
+* -m[no-]float command line option, M680x0: M68K-Opts.        (line  20)
+* -m[no-]mac command line option, M680x0: M68K-Opts.          (line  20)
+* -m[no-]usp command line option, M680x0: M68K-Opts.          (line  20)
+* -mall:                                 PDP-11-Options.      (line  26)
+* -mall-extensions:                      PDP-11-Options.      (line  26)
+* -mapcs command line option, ARM:       ARM Options.         (line  80)
+* -mapcs-float command line option, ARM: ARM Options.         (line  93)
+* -mapcs-reentrant command line option, ARM: ARM Options.     (line  98)
+* -marc[5|6|7|8] command line option, ARC: ARC Options.       (line   6)
+* -march= command line option, ARM:      ARM Options.         (line  37)
+* -march= command line option, M680x0:   M68K-Opts.           (line   8)
+* -matpcs command line option, ARM:      ARM Options.         (line  85)
+* -mcis:                                 PDP-11-Options.      (line  32)
+* -mconstant-gp command line option, IA-64: IA-64 Options.    (line   6)
+* -mCPU command line option, Alpha:      Alpha Options.       (line   6)
+* -mcpu option, cpu:                     TIC54X-Opts.         (line  15)
+* -mcpu= command line option, ARM:       ARM Options.         (line   6)
+* -mcpu= command line option, M680x0:    M68K-Opts.           (line  13)
+* -mcsm:                                 PDP-11-Options.      (line  43)
+* -mdebug command line option, Alpha:    Alpha Options.       (line  25)
+* -me option, stderr redirect:           TIC54X-Opts.         (line  20)
+* -meis:                                 PDP-11-Options.      (line  46)
+* -merrors-to-file option, stderr redirect: TIC54X-Opts.      (line  20)
+* -mf option, far-mode:                  TIC54X-Opts.         (line   8)
+* -mf11:                                 PDP-11-Options.      (line 122)
+* -mfar-mode option, far-mode:           TIC54X-Opts.         (line   8)
+* -mfis:                                 PDP-11-Options.      (line  51)
+* -mfloat-abi= command line option, ARM: ARM Options.         (line 102)
+* -mfp-11:                               PDP-11-Options.      (line  56)
+* -mfpp:                                 PDP-11-Options.      (line  56)
+* -mfpu:                                 PDP-11-Options.      (line  56)
+* -mfpu= command line option, ARM:       ARM Options.         (line  52)
+* -mip2022 option, IP2K:                 IP2K-Opts.           (line  14)
+* -mip2022ext option, IP2022:            IP2K-Opts.           (line   9)
+* -mj11:                                 PDP-11-Options.      (line 126)
+* -mka11:                                PDP-11-Options.      (line  92)
+* -mkb11:                                PDP-11-Options.      (line  95)
+* -mkd11a:                               PDP-11-Options.      (line  98)
+* -mkd11b:                               PDP-11-Options.      (line 101)
+* -mkd11d:                               PDP-11-Options.      (line 104)
+* -mkd11e:                               PDP-11-Options.      (line 107)
+* -mkd11f:                               PDP-11-Options.      (line 110)
+* -mkd11h:                               PDP-11-Options.      (line 110)
+* -mkd11k:                               PDP-11-Options.      (line 114)
+* -mkd11q:                               PDP-11-Options.      (line 110)
+* -mkd11z:                               PDP-11-Options.      (line 118)
+* -mkev11:                               PDP-11-Options.      (line  51)
+* -mlimited-eis:                         PDP-11-Options.      (line  64)
+* -mlong:                                M68HC11-Opts.        (line  32)
+* -mlong-double:                         M68HC11-Opts.        (line  40)
+* -mmfpt:                                PDP-11-Options.      (line  70)
+* -mmicrocode:                           PDP-11-Options.      (line  83)
+* -mmutiproc:                            PDP-11-Options.      (line  73)
+* -mmxps:                                PDP-11-Options.      (line  77)
+* -mno-cis:                              PDP-11-Options.      (line  32)
+* -mno-csm:                              PDP-11-Options.      (line  43)
+* -mno-eis:                              PDP-11-Options.      (line  46)
+* -mno-extensions:                       PDP-11-Options.      (line  29)
+* -mno-fis:                              PDP-11-Options.      (line  51)
+* -mno-fp-11:                            PDP-11-Options.      (line  56)
+* -mno-fpp:                              PDP-11-Options.      (line  56)
+* -mno-fpu:                              PDP-11-Options.      (line  56)
+* -mno-kev11:                            PDP-11-Options.      (line  51)
+* -mno-limited-eis:                      PDP-11-Options.      (line  64)
+* -mno-mfpt:                             PDP-11-Options.      (line  70)
+* -mno-microcode:                        PDP-11-Options.      (line  83)
+* -mno-mutiproc:                         PDP-11-Options.      (line  73)
+* -mno-mxps:                             PDP-11-Options.      (line  77)
+* -mno-pic:                              PDP-11-Options.      (line  11)
+* -mno-spl:                              PDP-11-Options.      (line  80)
+* -mno-sym32:                            MIPS Opts.           (line 145)
+* -mpic:                                 PDP-11-Options.      (line  11)
+* -mrelax command line option, V850:     V850 Options.        (line  51)
+* -mshort:                               M68HC11-Opts.        (line  27)
+* -mshort-double:                        M68HC11-Opts.        (line  36)
+* -mspl:                                 PDP-11-Options.      (line  80)
+* -msym32:                               MIPS Opts.           (line 145)
+* -mt11:                                 PDP-11-Options.      (line 130)
+* -mthumb command line option, ARM:      ARM Options.         (line  71)
+* -mthumb-interwork command line option, ARM: ARM Options.    (line  76)
+* -mv850 command line option, V850:      V850 Options.        (line  23)
+* -mv850any command line option, V850:   V850 Options.        (line  41)
+* -mv850e command line option, V850:     V850 Options.        (line  29)
+* -mv850e1 command line option, V850:    V850 Options.        (line  35)
+* -N command line option, CRIS:          CRIS-Opts.           (line  57)
+* -nIp option, M32RX:                    M32R-Opts.           (line 101)
+* -no-bitinst, M32R2:                    M32R-Opts.           (line  54)
+* -no-construct-floats:                  MIPS Opts.           (line 157)
+* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts.     (line  93)
+* -no-mdebug command line option, Alpha: Alpha Options.       (line  25)
+* -no-parallel option, M32RX:            M32R-Opts.           (line  51)
+* -no-relax option, i960:                Options-i960.        (line  66)
+* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts.
+                                                              (line  79)
+* -no-warn-unmatched-high option, M32R:  M32R-Opts.           (line 111)
+* -nocpp ignored (MIPS):                 MIPS Opts.           (line 148)
+* -o:                                    o.                   (line   6)
+* -O option, M32RX:                      M32R-Opts.           (line  59)
+* -parallel option, M32RX:               M32R-Opts.           (line  46)
+* -R:                                    R.                   (line   6)
+* -r800 command line option, Z80:        Z80 Options.         (line  41)
+* -relax command line option, Alpha:     Alpha Options.       (line  32)
+* -S, ignored on VAX:                    VAX-Opts.            (line  11)
+* -t, ignored on VAX:                    VAX-Opts.            (line  36)
+* -T, ignored on VAX:                    VAX-Opts.            (line  11)
+* -v:                                    v.                   (line   6)
+* -V, redundant on VAX:                  VAX-Opts.            (line  22)
+* -version:                              v.                   (line   6)
+* -W:                                    W.                   (line  11)
+* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line  65)
+* -warn-unmatched-high option, M32R:     M32R-Opts.           (line 105)
+* -Wnp option, M32RX:                    M32R-Opts.           (line  83)
+* -Wnuh option, M32RX:                   M32R-Opts.           (line 117)
+* -Wp option, M32RX:                     M32R-Opts.           (line  75)
+* -wsigned_overflow command line option, V850: V850 Options.  (line   9)
+* -Wuh option, M32RX:                    M32R-Opts.           (line 114)
+* -wunsigned_overflow command line option, V850: V850 Options.
+                                                              (line  16)
+* -x command line option, MMIX:          MMIX-Opts.           (line  44)
+* -z80 command line option, Z80:         Z80 Options.         (line   8)
+* -z8001 command line option, Z8000:     Z8000 Options.       (line   6)
+* -z8002 command line option, Z8000:     Z8000 Options.       (line   9)
+* . (symbol):                            Dot.                 (line   6)
+* .arch directive, ARM:                  ARM Directives.      (line 164)
+* .big directive, M32RX:                 M32R-Directives.     (line  88)
+* .cantunwind directive, ARM:            ARM Directives.      (line  87)
+* .cpu directive, ARM:                   ARM Directives.      (line 160)
+* .eabi_attribute directive, ARM:        ARM Directives.      (line 172)
+* .fnend directive, ARM:                 ARM Directives.      (line  78)
+* .fnstart directive, ARM:               ARM Directives.      (line  75)
+* .fpu directive, ARM:                   ARM Directives.      (line 168)
+* .handlerdata directive, ARM:           ARM Directives.      (line  98)
+* .insn:                                 MIPS insn.           (line   6)
+* .little directive, M32RX:              M32R-Directives.     (line  82)
+* .ltorg directive, ARM:                 ARM Directives.      (line  58)
+* .m32r directive, M32R:                 M32R-Directives.     (line  66)
+* .m32r2 directive, M32R2:               M32R-Directives.     (line  77)
+* .m32rx directive, M32RX:               M32R-Directives.     (line  72)
+* .movsp directive, ARM:                 ARM Directives.      (line 136)
+* .o:                                    Object.              (line   6)
+* .pad directive, ARM:                   ARM Directives.      (line 131)
+* .param on HPPA:                        HPPA Directives.     (line  19)
+* .personality directive, ARM:           ARM Directives.      (line  91)
+* .personalityindex directive, ARM:      ARM Directives.      (line  94)
+* .pool directive, ARM:                  ARM Directives.      (line  72)
+* .save directive, ARM:                  ARM Directives.      (line 107)
+* .set autoextend:                       MIPS autoextend.     (line   6)
+* .set dsp:                              MIPS ASE instruction generation overrides.
+                                                              (line  16)
+* .set mdmx:                             MIPS ASE instruction generation overrides.
+                                                              (line  11)
+* .set mips3d:                           MIPS ASE instruction generation overrides.
+                                                              (line   6)
+* .set mipsN:                            MIPS ISA.            (line   6)
+* .set mt:                               MIPS ASE instruction generation overrides.
+                                                              (line  21)
+* .set noautoextend:                     MIPS autoextend.     (line   6)
+* .set nodsp:                            MIPS ASE instruction generation overrides.
+                                                              (line  16)
+* .set nomdmx:                           MIPS ASE instruction generation overrides.
+                                                              (line  11)
+* .set nomips3d:                         MIPS ASE instruction generation overrides.
+                                                              (line   6)
+* .set nomt:                             MIPS ASE instruction generation overrides.
+                                                              (line  21)
+* .set nosym32:                          MIPS symbol sizes.   (line   6)
+* .set pop:                              MIPS option stack.   (line   6)
+* .set push:                             MIPS option stack.   (line   6)
+* .set sym32:                            MIPS symbol sizes.   (line   6)
+* .setfp directive, ARM:                 ARM Directives.      (line 139)
+* .unwind_raw directive, ARM:            ARM Directives.      (line 153)
+* .v850 directive, V850:                 V850 Directives.     (line  14)
+* .v850e directive, V850:                V850 Directives.     (line  20)
+* .v850e1 directive, V850:               V850 Directives.     (line  26)
+* .z8001:                                Z8000 Directives.    (line  11)
+* .z8002:                                Z8000 Directives.    (line  15)
+* 16-bit code, i386:                     i386-16bit.          (line   6)
+* 2byte directive, ARC:                  ARC Directives.      (line   9)
+* 3byte directive, ARC:                  ARC Directives.      (line  12)
+* 3DNow!, i386:                          i386-SIMD.           (line   6)
+* 3DNow!, x86-64:                        i386-SIMD.           (line   6)
+* 430 support:                           MSP430-Dependent.    (line   6)
+* 4byte directive, ARC:                  ARC Directives.      (line  15)
+* : (label):                             Statements.          (line  30)
+* @word modifier, D10V:                  D10V-Word.           (line   6)
+* \" (doublequote character):            Strings.             (line  43)
+* \\ (\ character):                      Strings.             (line  40)
+* \b (backspace character):              Strings.             (line  15)
+* \DDD (octal character code):           Strings.             (line  30)
+* \f (formfeed character):               Strings.             (line  18)
+* \n (newline character):                Strings.             (line  21)
+* \r (carriage return character):        Strings.             (line  24)
+* \t (tab):                              Strings.             (line  27)
+* \XD... (hex character code):           Strings.             (line  36)
+* _ opcode prefix:                       Xtensa Opcodes.      (line   9)
+* a.out:                                 Object.              (line   6)
+* a.out symbol attributes:               a.out Symbols.       (line   6)
+* A_DIR environment variable, TIC54X:    TIC54X-Env.          (line   6)
+* ABI options, SH64:                     SH64 Options.        (line  29)
+* ABORT directive:                       ABORT.               (line   6)
+* abort directive:                       Abort.               (line   6)
+* absolute section:                      Ld Sections.         (line  29)
+* absolute-literals directive:           Absolute Literals Directive.
+                                                              (line   6)
+* ADDI instructions, relaxation:         Xtensa Immediate Relaxation.
+                                                              (line  43)
+* addition, permitted arguments:         Infix Ops.           (line  44)
+* addresses:                             Expressions.         (line   6)
+* addresses, format of:                  Secs Background.     (line  68)
+* addressing modes, D10V:                D10V-Addressing.     (line   6)
+* addressing modes, D30V:                D30V-Addressing.     (line   6)
+* addressing modes, H8/300:              H8/300-Addressing.   (line   6)
+* addressing modes, M680x0:              M68K-Syntax.         (line  21)
+* addressing modes, M68HC11:             M68HC11-Syntax.      (line  17)
+* addressing modes, SH:                  SH-Addressing.       (line   6)
+* addressing modes, SH64:                SH64-Addressing.     (line   6)
+* addressing modes, Z8000:               Z8000-Addressing.    (line   6)
+* ADR reg,<label> pseudo op, ARM:        ARM Opcodes.         (line  25)
+* ADRL reg,<label> pseudo op, ARM:       ARM Opcodes.         (line  35)
+* advancing location counter:            Org.                 (line   6)
+* align directive:                       Align.               (line   6)
+* align directive, ARM:                  ARM Directives.      (line   6)
+* align directive, SPARC:                Sparc-Directives.    (line   9)
+* align directive, TIC54X:               TIC54X-Directives.   (line   6)
+* alignment of branch targets:           Xtensa Automatic Alignment.
+                                                              (line   6)
+* alignment of ENTRY instructions:       Xtensa Automatic Alignment.
+                                                              (line   6)
+* alignment of LOOP instructions:        Xtensa Automatic Alignment.
+                                                              (line   6)
+* Alpha floating point (IEEE):           Alpha Floating Point.
+                                                              (line   6)
+* Alpha line comment character:          Alpha-Chars.         (line   6)
+* Alpha line separator:                  Alpha-Chars.         (line   8)
+* Alpha notes:                           Alpha Notes.         (line   6)
+* Alpha options:                         Alpha Options.       (line   6)
+* Alpha registers:                       Alpha-Regs.          (line   6)
+* Alpha relocations:                     Alpha-Relocs.        (line   6)
+* Alpha support:                         Alpha-Dependent.     (line   6)
+* Alpha Syntax:                          Alpha Options.       (line  54)
+* Alpha-only directives:                 Alpha Directives.    (line  10)
+* altered difference tables:             Word.                (line  12)
+* alternate syntax for the 680x0:        M68K-Moto-Syntax.    (line   6)
+* ARC floating point (IEEE):             ARC Floating Point.  (line   6)
+* ARC machine directives:                ARC Directives.      (line   6)
+* ARC opcodes:                           ARC Opcodes.         (line   6)
+* ARC options (none):                    ARC Options.         (line   6)
+* ARC register names:                    ARC-Regs.            (line   6)
+* ARC special characters:                ARC-Chars.           (line   6)
+* ARC support:                           ARC-Dependent.       (line   6)
+* arc5 arc5, ARC:                        ARC Options.         (line  10)
+* arc6 arc6, ARC:                        ARC Options.         (line  13)
+* arc7 arc7, ARC:                        ARC Options.         (line  21)
+* arc8 arc8, ARC:                        ARC Options.         (line  24)
+* arch directive, i386:                  i386-Arch.           (line   6)
+* arch directive, M680x0:                M68K-Directives.     (line  22)
+* arch directive, x86-64:                i386-Arch.           (line   6)
+* architecture options, i960:            Options-i960.        (line   6)
+* architecture options, IP2022:          IP2K-Opts.           (line   9)
+* architecture options, IP2K:            IP2K-Opts.           (line  14)
+* architecture options, M16C:            M32C-Opts.           (line  12)
+* architecture options, M32C:            M32C-Opts.           (line   9)
+* architecture options, M32R:            M32R-Opts.           (line  21)
+* architecture options, M32R2:           M32R-Opts.           (line  17)
+* architecture options, M32RX:           M32R-Opts.           (line   9)
+* architecture options, M680x0:          M68K-Opts.           (line 103)
+* Architecture variant option, CRIS:     CRIS-Opts.           (line  33)
+* architectures, PowerPC:                PowerPC-Opts.        (line   6)
+* architectures, SPARC:                  Sparc-Opts.          (line   6)
+* arguments for addition:                Infix Ops.           (line  44)
+* arguments for subtraction:             Infix Ops.           (line  49)
+* arguments in expressions:              Arguments.           (line   6)
+* arithmetic functions:                  Operators.           (line   6)
+* arithmetic operands:                   Arguments.           (line   6)
+* arm directive, ARM:                    ARM Directives.      (line  36)
+* ARM floating point (IEEE):             ARM Floating Point.  (line   6)
+* ARM identifiers:                       ARM-Chars.           (line  15)
+* ARM immediate character:               ARM-Chars.           (line  13)
+* ARM line comment character:            ARM-Chars.           (line   6)
+* ARM line separator:                    ARM-Chars.           (line  10)
+* ARM machine directives:                ARM Directives.      (line   6)
+* ARM opcodes:                           ARM Opcodes.         (line   6)
+* ARM options (none):                    ARM Options.         (line   6)
+* ARM register names:                    ARM-Regs.            (line   6)
+* ARM support:                           ARM-Dependent.       (line   6)
+* ascii directive:                       Ascii.               (line   6)
+* asciz directive:                       Asciz.               (line   6)
+* asg directive, TIC54X:                 TIC54X-Directives.   (line  20)
+* assembler bugs, reporting:             Bug Reporting.       (line   6)
+* assembler crash:                       Bug Criteria.        (line   9)
+* assembler directive .arch, CRIS:       CRIS-Pseudos.        (line  45)
+* assembler directive .dword, CRIS:      CRIS-Pseudos.        (line  12)
+* assembler directive .far, M68HC11:     M68HC11-Directives.  (line  20)
+* assembler directive .interrupt, M68HC11: M68HC11-Directives.
+                                                              (line  26)
+* assembler directive .mode, M68HC11:    M68HC11-Directives.  (line  16)
+* assembler directive .relax, M68HC11:   M68HC11-Directives.  (line  10)
+* assembler directive .syntax, CRIS:     CRIS-Pseudos.        (line  17)
+* assembler directive .xrefb, M68HC11:   M68HC11-Directives.  (line  31)
+* assembler directive BSPEC, MMIX:       MMIX-Pseudos.        (line 131)
+* assembler directive BYTE, MMIX:        MMIX-Pseudos.        (line  97)
+* assembler directive ESPEC, MMIX:       MMIX-Pseudos.        (line 131)
+* assembler directive GREG, MMIX:        MMIX-Pseudos.        (line  50)
+* assembler directive IS, MMIX:          MMIX-Pseudos.        (line  42)
+* assembler directive LOC, MMIX:         MMIX-Pseudos.        (line   7)
+* assembler directive LOCAL, MMIX:       MMIX-Pseudos.        (line  28)
+* assembler directive OCTA, MMIX:        MMIX-Pseudos.        (line 108)
+* assembler directive PREFIX, MMIX:      MMIX-Pseudos.        (line 120)
+* assembler directive TETRA, MMIX:       MMIX-Pseudos.        (line 108)
+* assembler directive WYDE, MMIX:        MMIX-Pseudos.        (line 108)
+* assembler directives, CRIS:            CRIS-Pseudos.        (line   6)
+* assembler directives, M68HC11:         M68HC11-Directives.  (line   6)
+* assembler directives, M68HC12:         M68HC11-Directives.  (line   6)
+* assembler directives, MMIX:            MMIX-Pseudos.        (line   6)
+* assembler internal logic error:        As Sections.         (line  13)
+* assembler version:                     v.                   (line   6)
+* assembler, and linker:                 Secs Background.     (line  10)
+* assembly listings, enabling:           a.                   (line   6)
+* assigning values to symbols <1>:       Equ.                 (line   6)
+* assigning values to symbols:           Setting Symbols.     (line   6)
+* atmp directive, i860:                  Directives-i860.     (line  16)
+* att_syntax pseudo op, i386:            i386-Syntax.         (line   6)
+* att_syntax pseudo op, x86-64:          i386-Syntax.         (line   6)
+* attributes, symbol:                    Symbol Attributes.   (line   6)
+* auxiliary attributes, COFF symbols:    COFF Symbols.        (line  19)
+* auxiliary symbol information, COFF:    Dim.                 (line   6)
+* Av7:                                   Sparc-Opts.          (line  25)
+* backslash (\\):                        Strings.             (line  40)
+* backspace (\b):                        Strings.             (line  15)
+* balign directive:                      Balign.              (line   6)
+* balignl directive:                     Balign.              (line  27)
+* balignw directive:                     Balign.              (line  27)
+* bes directive, TIC54X:                 TIC54X-Directives.   (line 197)
+* BFIN directives:                       BFIN Directives.     (line   6)
+* BFIN syntax:                           BFIN Syntax.         (line   6)
+* big endian output, MIPS:               Overview.            (line 606)
+* big endian output, PJ:                 Overview.            (line 513)
+* big-endian output, MIPS:               MIPS Opts.           (line  13)
+* bignums:                               Bignums.             (line   6)
+* binary constants, TIC54X:              TIC54X-Constants.    (line   8)
+* binary files, including:               Incbin.              (line   6)
+* binary integers:                       Integers.            (line   6)
+* bit names, IA-64:                      IA-64-Bits.          (line   6)
+* bitfields, not supported on VAX:       VAX-no.              (line   6)
+* Blackfin support:                      BFIN-Dependent.      (line   6)
+* block:                                 Z8000 Directives.    (line  55)
+* branch improvement, M680x0:            M68K-Branch.         (line   6)
+* branch improvement, M68HC11:           M68HC11-Branch.      (line   6)
+* branch improvement, VAX:               VAX-branch.          (line   6)
+* branch instructions, relaxation:       Xtensa Branch Relaxation.
+                                                              (line   6)
+* branch recording, i960:                Options-i960.        (line  22)
+* branch statistics table, i960:         Options-i960.        (line  40)
+* branch target alignment:               Xtensa Automatic Alignment.
+                                                              (line   6)
+* break directive, TIC54X:               TIC54X-Directives.   (line 143)
+* BSD syntax:                            PDP-11-Syntax.       (line   6)
+* bss directive, i960:                   Directives-i960.     (line   6)
+* bss directive, TIC54X:                 TIC54X-Directives.   (line  29)
+* bss section <1>:                       bss.                 (line   6)
+* bss section:                           Ld Sections.         (line  20)
+* bug criteria:                          Bug Criteria.        (line   6)
+* bug reports:                           Bug Reporting.       (line   6)
+* bugs in assembler:                     Reporting Bugs.      (line   6)
+* Built-in symbols, CRIS:                CRIS-Symbols.        (line   6)
+* builtin math functions, TIC54X:        TIC54X-Builtins.     (line   6)
+* builtin subsym functions, TIC54X:      TIC54X-Macros.       (line  16)
+* bus lock prefixes, i386:               i386-Prefixes.       (line  36)
+* bval:                                  Z8000 Directives.    (line  30)
+* byte directive:                        Byte.                (line   6)
+* byte directive, TIC54X:                TIC54X-Directives.   (line  36)
+* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env.       (line   6)
+* c_mode directive, TIC54X:              TIC54X-Directives.   (line  51)
+* call instructions, i386:               i386-Mnemonics.      (line  51)
+* call instructions, relaxation:         Xtensa Call Relaxation.
+                                                              (line   6)
+* call instructions, x86-64:             i386-Mnemonics.      (line  51)
+* callj, i960 pseudo-opcode:             callj-i960.          (line   6)
+* carriage return (\r):                  Strings.             (line  24)
+* case sensitivity, Z80:                 Z80-Case.            (line   6)
+* cfi_endproc directive:                 CFI directives.      (line  14)
+* cfi_startproc directive:               CFI directives.      (line   6)
+* char directive, TIC54X:                TIC54X-Directives.   (line  36)
+* character constant, Z80:               Z80-Chars.           (line  13)
+* character constants:                   Characters.          (line   6)
+* character escape codes:                Strings.             (line  15)
+* character escapes, Z80:                Z80-Chars.           (line  11)
+* character, single:                     Chars.               (line   6)
+* characters used in symbols:            Symbol Intro.        (line   6)
+* clink directive, TIC54X:               TIC54X-Directives.   (line  45)
+* code directive, ARM:                   ARM Directives.      (line  29)
+* code16 directive, i386:                i386-16bit.          (line   6)
+* code16gcc directive, i386:             i386-16bit.          (line   6)
+* code32 directive, i386:                i386-16bit.          (line   6)
+* code64 directive, i386:                i386-16bit.          (line   6)
+* code64 directive, x86-64:              i386-16bit.          (line   6)
+* COFF auxiliary symbol information:     Dim.                 (line   6)
+* COFF structure debugging:              Tag.                 (line   6)
+* COFF symbol attributes:                COFF Symbols.        (line   6)
+* COFF symbol descriptor:                Desc.                (line   6)
+* COFF symbol storage class:             Scl.                 (line   6)
+* COFF symbol type:                      Type.                (line  11)
+* COFF symbols, debugging:               Def.                 (line   6)
+* COFF value attribute:                  Val.                 (line   6)
+* COMDAT:                                Linkonce.            (line   6)
+* comm directive:                        Comm.                (line   6)
+* command line conventions:              Command Line.        (line   6)
+* command line options, V850:            V850 Options.        (line   9)
+* command-line options ignored, VAX:     VAX-Opts.            (line   6)
+* comments:                              Comments.            (line   6)
+* comments, M680x0:                      M68K-Chars.          (line   6)
+* comments, removed by preprocessor:     Preprocessing.       (line  11)
+* common directive, SPARC:               Sparc-Directives.    (line  12)
+* common sections:                       Linkonce.            (line   6)
+* common variable storage:               bss.                 (line   6)
+* compare and jump expansions, i960:     Compare-and-branch-i960.
+                                                              (line  13)
+* compare/branch instructions, i960:     Compare-and-branch-i960.
+                                                              (line   6)
+* comparison expressions:                Infix Ops.           (line  55)
+* conditional assembly:                  If.                  (line   6)
+* constant, single character:            Chars.               (line   6)
+* constants:                             Constants.           (line   6)
+* constants, bignum:                     Bignums.             (line   6)
+* constants, character:                  Characters.          (line   6)
+* constants, converted by preprocessor:  Preprocessing.       (line  14)
+* constants, floating point:             Flonums.             (line   6)
+* constants, integer:                    Integers.            (line   6)
+* constants, number:                     Numbers.             (line   6)
+* constants, string:                     Strings.             (line   6)
+* constants, TIC54X:                     TIC54X-Constants.    (line   6)
+* conversion instructions, i386:         i386-Mnemonics.      (line  32)
+* conversion instructions, x86-64:       i386-Mnemonics.      (line  32)
+* coprocessor wait, i386:                i386-Prefixes.       (line  40)
+* copy directive, TIC54X:                TIC54X-Directives.   (line  54)
+* cpu directive, M680x0:                 M68K-Directives.     (line  30)
+* crash of assembler:                    Bug Criteria.        (line   9)
+* CRIS --emulation=crisaout command line option: CRIS-Opts.   (line   9)
+* CRIS --emulation=criself command line option: CRIS-Opts.    (line   9)
+* CRIS --march=ARCHITECTURE command line option: CRIS-Opts.   (line  33)
+* CRIS --mul-bug-abort command line option: CRIS-Opts.        (line  61)
+* CRIS --no-mul-bug-abort command line option: CRIS-Opts.     (line  61)
+* CRIS --no-underscore command line option: CRIS-Opts.        (line  15)
+* CRIS --pic command line option:        CRIS-Opts.           (line  27)
+* CRIS --underscore command line option: CRIS-Opts.           (line  15)
+* CRIS -N command line option:           CRIS-Opts.           (line  57)
+* CRIS architecture variant option:      CRIS-Opts.           (line  33)
+* CRIS assembler directive .arch:        CRIS-Pseudos.        (line  45)
+* CRIS assembler directive .dword:       CRIS-Pseudos.        (line  12)
+* CRIS assembler directive .syntax:      CRIS-Pseudos.        (line  17)
+* CRIS assembler directives:             CRIS-Pseudos.        (line   6)
+* CRIS built-in symbols:                 CRIS-Symbols.        (line   6)
+* CRIS instruction expansion:            CRIS-Expand.         (line   6)
+* CRIS line comment characters:          CRIS-Chars.          (line   6)
+* CRIS options:                          CRIS-Opts.           (line   6)
+* CRIS position-independent code:        CRIS-Opts.           (line  27)
+* CRIS pseudo-op .arch:                  CRIS-Pseudos.        (line  45)
+* CRIS pseudo-op .dword:                 CRIS-Pseudos.        (line  12)
+* CRIS pseudo-op .syntax:                CRIS-Pseudos.        (line  17)
+* CRIS pseudo-ops:                       CRIS-Pseudos.        (line   6)
+* CRIS register names:                   CRIS-Regs.           (line   6)
+* CRIS support:                          CRIS-Dependent.      (line   6)
+* CRIS symbols in position-independent code: CRIS-Pic.        (line   6)
+* ctbp register, V850:                   V850-Regs.           (line 131)
+* ctoff pseudo-op, V850:                 V850 Opcodes.        (line 111)
+* ctpc register, V850:                   V850-Regs.           (line 119)
+* ctpsw register, V850:                  V850-Regs.           (line 122)
+* current address:                       Dot.                 (line   6)
+* current address, advancing:            Org.                 (line   6)
+* D10V @word modifier:                   D10V-Word.           (line   6)
+* D10V addressing modes:                 D10V-Addressing.     (line   6)
+* D10V floating point:                   D10V-Float.          (line   6)
+* D10V line comment character:           D10V-Chars.          (line   6)
+* D10V opcode summary:                   D10V-Opcodes.        (line   6)
+* D10V optimization:                     Overview.            (line 391)
+* D10V options:                          D10V-Opts.           (line   6)
+* D10V registers:                        D10V-Regs.           (line   6)
+* D10V size modifiers:                   D10V-Size.           (line   6)
+* D10V sub-instruction ordering:         D10V-Chars.          (line   6)
+* D10V sub-instructions:                 D10V-Subs.           (line   6)
+* D10V support:                          D10V-Dependent.      (line   6)
+* D10V syntax:                           D10V-Syntax.         (line   6)
+* D30V addressing modes:                 D30V-Addressing.     (line   6)
+* D30V floating point:                   D30V-Float.          (line   6)
+* D30V Guarded Execution:                D30V-Guarded.        (line   6)
+* D30V line comment character:           D30V-Chars.          (line   6)
+* D30V nops:                             Overview.            (line 399)
+* D30V nops after 32-bit multiply:       Overview.            (line 402)
+* D30V opcode summary:                   D30V-Opcodes.        (line   6)
+* D30V optimization:                     Overview.            (line 396)
+* D30V options:                          D30V-Opts.           (line   6)
+* D30V registers:                        D30V-Regs.           (line   6)
+* D30V size modifiers:                   D30V-Size.           (line   6)
+* D30V sub-instruction ordering:         D30V-Chars.          (line   6)
+* D30V sub-instructions:                 D30V-Subs.           (line   6)
+* D30V support:                          D30V-Dependent.      (line   6)
+* D30V syntax:                           D30V-Syntax.         (line   6)
+* data alignment on SPARC:               Sparc-Aligned-Data.  (line   6)
+* data and text sections, joining:       R.                   (line   6)
+* data directive:                        Data.                (line   6)
+* data directive, TIC54X:                TIC54X-Directives.   (line  61)
+* data section:                          Ld Sections.         (line   9)
+* data1 directive, M680x0:               M68K-Directives.     (line   9)
+* data2 directive, M680x0:               M68K-Directives.     (line  12)
+* datalabel, SH64:                       SH64-Addressing.     (line  16)
+* dbpc register, V850:                   V850-Regs.           (line 125)
+* dbpsw register, V850:                  V850-Regs.           (line 128)
+* debuggers, and symbol order:           Symbols.             (line  10)
+* debugging COFF symbols:                Def.                 (line   6)
+* DEC syntax:                            PDP-11-Syntax.       (line   6)
+* decimal integers:                      Integers.            (line  12)
+* def directive:                         Def.                 (line   6)
+* def directive, TIC54X:                 TIC54X-Directives.   (line 103)
+* density instructions:                  Density Instructions.
+                                                              (line   6)
+* dependency tracking:                   MD.                  (line   6)
+* deprecated directives:                 Deprecated.          (line   6)
+* desc directive:                        Desc.                (line   6)
+* descriptor, of a.out symbol:           Symbol Desc.         (line   6)
+* dfloat directive, VAX:                 VAX-directives.      (line  10)
+* difference tables altered:             Word.                (line  12)
+* difference tables, warning:            K.                   (line   6)
+* differences, mmixal:                   MMIX-mmixal.         (line   6)
+* dim directive:                         Dim.                 (line   6)
+* directives and instructions:           Statements.          (line  19)
+* directives for PowerPC:                PowerPC-Pseudo.      (line   6)
+* directives, BFIN:                      BFIN Directives.     (line   6)
+* directives, M32R:                      M32R-Directives.     (line   6)
+* directives, M680x0:                    M68K-Directives.     (line   6)
+* directives, machine independent:       Pseudo Ops.          (line   6)
+* directives, Xtensa:                    Xtensa Directives.   (line   6)
+* directives, Z8000:                     Z8000 Directives.    (line   6)
+* displacement sizing character, VAX:    VAX-operands.        (line  12)
+* dollar local symbols:                  Symbol Names.        (line  91)
+* dot (symbol):                          Dot.                 (line   6)
+* double directive:                      Double.              (line   6)
+* double directive, i386:                i386-Float.          (line  14)
+* double directive, M680x0:              M68K-Float.          (line  14)
+* double directive, M68HC11:             M68HC11-Float.       (line  14)
+* double directive, TIC54X:              TIC54X-Directives.   (line  64)
+* double directive, VAX:                 VAX-float.           (line  15)
+* double directive, x86-64:              i386-Float.          (line  14)
+* doublequote (\"):                      Strings.             (line  43)
+* drlist directive, TIC54X:              TIC54X-Directives.   (line  73)
+* drnolist directive, TIC54X:            TIC54X-Directives.   (line  73)
+* dual directive, i860:                  Directives-i860.     (line   6)
+* ECOFF sections:                        MIPS Object.         (line   6)
+* ecr register, V850:                    V850-Regs.           (line 113)
+* eight-byte integer:                    Quad.                (line   9)
+* eipc register, V850:                   V850-Regs.           (line 101)
+* eipsw register, V850:                  V850-Regs.           (line 104)
+* eject directive:                       Eject.               (line   6)
+* ELF symbol type:                       Type.                (line  22)
+* else directive:                        Else.                (line   6)
+* elseif directive:                      Elseif.              (line   6)
+* empty expressions:                     Empty Exprs.         (line   6)
+* emsg directive, TIC54X:                TIC54X-Directives.   (line  77)
+* emulation:                             Overview.            (line 697)
+* end directive:                         End.                 (line   6)
+* enddual directive, i860:               Directives-i860.     (line  11)
+* endef directive:                       Endef.               (line   6)
+* endfunc directive:                     Endfunc.             (line   6)
+* endianness, MIPS:                      Overview.            (line 606)
+* endianness, PJ:                        Overview.            (line 513)
+* endif directive:                       Endif.               (line   6)
+* endloop directive, TIC54X:             TIC54X-Directives.   (line 143)
+* endm directive:                        Macro.               (line  96)
+* endm directive, TIC54X:                TIC54X-Directives.   (line 153)
+* endstruct directive, TIC54X:           TIC54X-Directives.   (line 217)
+* endunion directive, TIC54X:            TIC54X-Directives.   (line 251)
+* ENTRY instructions, alignment:         Xtensa Automatic Alignment.
+                                                              (line   6)
+* environment settings, TIC54X:          TIC54X-Env.          (line   6)
+* EOF, newline must precede:             Statements.          (line  13)
+* ep register, V850:                     V850-Regs.           (line  95)
+* equ directive:                         Equ.                 (line   6)
+* equ directive, TIC54X:                 TIC54X-Directives.   (line 192)
+* equiv directive:                       Equiv.               (line   6)
+* eqv directive:                         Eqv.                 (line   6)
+* err directive:                         Err.                 (line   6)
+* error directive:                       Error.               (line   6)
+* error messages:                        Errors.              (line   6)
+* error on valid input:                  Bug Criteria.        (line  12)
+* errors, caused by warnings:            W.                   (line  16)
+* errors, continuing after:              Z.                   (line   6)
+* ESA/390 floating point (IEEE):         ESA/390 Floating Point.
+                                                              (line   6)
+* ESA/390 support:                       ESA/390-Dependent.   (line   6)
+* ESA/390 Syntax:                        ESA/390 Options.     (line   8)
+* ESA/390-only directives:               ESA/390 Directives.  (line  12)
+* escape codes, character:               Strings.             (line  15)
+* eval directive, TIC54X:                TIC54X-Directives.   (line  24)
+* even:                                  Z8000 Directives.    (line  58)
+* even directive, M680x0:                M68K-Directives.     (line  15)
+* even directive, TIC54X:                TIC54X-Directives.   (line   6)
+* exitm directive:                       Macro.               (line  99)
+* expr (internal section):               As Sections.         (line  17)
+* expression arguments:                  Arguments.           (line   6)
+* expressions:                           Expressions.         (line   6)
+* expressions, comparison:               Infix Ops.           (line  55)
+* expressions, empty:                    Empty Exprs.         (line   6)
+* expressions, integer:                  Integer Exprs.       (line   6)
+* extAuxRegister directive, ARC:         ARC Directives.      (line  18)
+* extCondCode directive, ARC:            ARC Directives.      (line  41)
+* extCoreRegister directive, ARC:        ARC Directives.      (line  53)
+* extend directive M680x0:               M68K-Float.          (line  17)
+* extend directive M68HC11:              M68HC11-Float.       (line  17)
+* extended directive, i960:              Directives-i960.     (line  13)
+* extern directive:                      Extern.              (line   6)
+* extInstruction directive, ARC:         ARC Directives.      (line  78)
+* fail directive:                        Fail.                (line   6)
+* far_mode directive, TIC54X:            TIC54X-Directives.   (line  82)
+* faster processing (-f):                f.                   (line   6)
+* fatal signal:                          Bug Criteria.        (line   9)
+* fclist directive, TIC54X:              TIC54X-Directives.   (line  87)
+* fcnolist directive, TIC54X:            TIC54X-Directives.   (line  87)
+* fepc register, V850:                   V850-Regs.           (line 107)
+* fepsw register, V850:                  V850-Regs.           (line 110)
+* ffloat directive, VAX:                 VAX-directives.      (line  14)
+* field directive, TIC54X:               TIC54X-Directives.   (line  91)
+* file directive <1>:                    File.                (line   6)
+* file directive:                        LNS directives.      (line   6)
+* file directive, MSP 430:               MSP430 Directives.   (line   6)
+* file name, logical:                    File.                (line   6)
+* files, including:                      Include.             (line   6)
+* files, input:                          Input Files.         (line   6)
+* fill directive:                        Fill.                (line   6)
+* filling memory <1>:                    Space.               (line   6)
+* filling memory:                        Skip.                (line   6)
+* FLIX syntax:                           Xtensa Syntax.       (line   6)
+* float directive:                       Float.               (line   6)
+* float directive, i386:                 i386-Float.          (line  14)
+* float directive, M680x0:               M68K-Float.          (line  11)
+* float directive, M68HC11:              M68HC11-Float.       (line  11)
+* float directive, TIC54X:               TIC54X-Directives.   (line  64)
+* float directive, VAX:                  VAX-float.           (line  15)
+* float directive, x86-64:               i386-Float.          (line  14)
+* floating point numbers:                Flonums.             (line   6)
+* floating point numbers (double):       Double.              (line   6)
+* floating point numbers (single) <1>:   Single.              (line   6)
+* floating point numbers (single):       Float.               (line   6)
+* floating point, Alpha (IEEE):          Alpha Floating Point.
+                                                              (line   6)
+* floating point, ARC (IEEE):            ARC Floating Point.  (line   6)
+* floating point, ARM (IEEE):            ARM Floating Point.  (line   6)
+* floating point, D10V:                  D10V-Float.          (line   6)
+* floating point, D30V:                  D30V-Float.          (line   6)
+* floating point, ESA/390 (IEEE):        ESA/390 Floating Point.
+                                                              (line   6)
+* floating point, H8/300 (IEEE):         H8/300 Floating Point.
+                                                              (line   6)
+* floating point, HPPA (IEEE):           HPPA Floating Point. (line   6)
+* floating point, i386:                  i386-Float.          (line   6)
+* floating point, i960 (IEEE):           Floating Point-i960. (line   6)
+* floating point, M680x0:                M68K-Float.          (line   6)
+* floating point, M68HC11:               M68HC11-Float.       (line   6)
+* floating point, MSP 430 (IEEE):        MSP430 Floating Point.
+                                                              (line   6)
+* floating point, SH (IEEE):             SH Floating Point.   (line   6)
+* floating point, SPARC (IEEE):          Sparc-Float.         (line   6)
+* floating point, V850 (IEEE):           V850 Floating Point. (line   6)
+* floating point, VAX:                   VAX-float.           (line   6)
+* floating point, x86-64:                i386-Float.          (line   6)
+* floating point, Z80:                   Z80 Floating Point.  (line   6)
+* flonums:                               Flonums.             (line   6)
+* force_thumb directive, ARM:            ARM Directives.      (line  39)
+* format of error messages:              Errors.              (line  24)
+* format of warning messages:            Errors.              (line  12)
+* formfeed (\f):                         Strings.             (line  18)
+* func directive:                        Func.                (line   6)
+* functions, in expressions:             Operators.           (line   6)
+* gbr960, i960 postprocessor:            Options-i960.        (line  40)
+* gfloat directive, VAX:                 VAX-directives.      (line  18)
+* global:                                Z8000 Directives.    (line  21)
+* global directive:                      Global.              (line   6)
+* global directive, TIC54X:              TIC54X-Directives.   (line 103)
+* gp register, MIPS:                     MIPS Object.         (line  11)
+* gp register, V850:                     V850-Regs.           (line  17)
+* grouping data:                         Sub-Sections.        (line   6)
+* H8/300 addressing modes:               H8/300-Addressing.   (line   6)
+* H8/300 floating point (IEEE):          H8/300 Floating Point.
+                                                              (line   6)
+* H8/300 line comment character:         H8/300-Chars.        (line   6)
+* H8/300 line separator:                 H8/300-Chars.        (line   8)
+* H8/300 machine directives (none):      H8/300 Directives.   (line   6)
+* H8/300 opcode summary:                 H8/300 Opcodes.      (line   6)
+* H8/300 options (none):                 H8/300 Options.      (line   6)
+* H8/300 registers:                      H8/300-Regs.         (line   6)
+* H8/300 size suffixes:                  H8/300 Opcodes.      (line 163)
+* H8/300 support:                        H8/300-Dependent.    (line   6)
+* H8/300H, assembling for:               H8/300 Directives.   (line   8)
+* half directive, ARC:                   ARC Directives.      (line 156)
+* half directive, SPARC:                 Sparc-Directives.    (line  17)
+* half directive, TIC54X:                TIC54X-Directives.   (line 111)
+* hex character code (\XD...):           Strings.             (line  36)
+* hexadecimal integers:                  Integers.            (line  15)
+* hexadecimal prefix, Z80:               Z80-Chars.           (line   8)
+* hfloat directive, VAX:                 VAX-directives.      (line  22)
+* hi pseudo-op, V850:                    V850 Opcodes.        (line  33)
+* hi0 pseudo-op, V850:                   V850 Opcodes.        (line  10)
+* hidden directive:                      Hidden.              (line   6)
+* high directive, M32R:                  M32R-Directives.     (line  18)
+* hilo pseudo-op, V850:                  V850 Opcodes.        (line  55)
+* HPPA directives not supported:         HPPA Directives.     (line  11)
+* HPPA floating point (IEEE):            HPPA Floating Point. (line   6)
+* HPPA Syntax:                           HPPA Options.        (line   8)
+* HPPA-only directives:                  HPPA Directives.     (line  24)
+* hword directive:                       hword.               (line   6)
+* i370 support:                          ESA/390-Dependent.   (line   6)
+* i386 16-bit code:                      i386-16bit.          (line   6)
+* i386 arch directive:                   i386-Arch.           (line   6)
+* i386 att_syntax pseudo op:             i386-Syntax.         (line   6)
+* i386 conversion instructions:          i386-Mnemonics.      (line  32)
+* i386 floating point:                   i386-Float.          (line   6)
+* i386 immediate operands:               i386-Syntax.         (line  15)
+* i386 instruction naming:               i386-Mnemonics.      (line   6)
+* i386 instruction prefixes:             i386-Prefixes.       (line   6)
+* i386 intel_syntax pseudo op:           i386-Syntax.         (line   6)
+* i386 jump optimization:                i386-Jumps.          (line   6)
+* i386 jump, call, return:               i386-Syntax.         (line  38)
+* i386 jump/call operands:               i386-Syntax.         (line  15)
+* i386 memory references:                i386-Memory.         (line   6)
+* i386 mul, imul instructions:           i386-Notes.          (line   6)
+* i386 options:                          i386-Options.        (line   6)
+* i386 register operands:                i386-Syntax.         (line  15)
+* i386 registers:                        i386-Regs.           (line   6)
+* i386 sections:                         i386-Syntax.         (line  44)
+* i386 size suffixes:                    i386-Syntax.         (line  29)
+* i386 source, destination operands:     i386-Syntax.         (line  22)
+* i386 support:                          i386-Dependent.      (line   6)
+* i386 syntax compatibility:             i386-Syntax.         (line   6)
+* i80306 support:                        i386-Dependent.      (line   6)
+* i860 machine directives:               Directives-i860.     (line   6)
+* i860 opcodes:                          Opcodes for i860.    (line   6)
+* i860 support:                          i860-Dependent.      (line   6)
+* i960 architecture options:             Options-i960.        (line   6)
+* i960 branch recording:                 Options-i960.        (line  22)
+* i960 callj pseudo-opcode:              callj-i960.          (line   6)
+* i960 compare and jump expansions:      Compare-and-branch-i960.
+                                                              (line  13)
+* i960 compare/branch instructions:      Compare-and-branch-i960.
+                                                              (line   6)
+* i960 floating point (IEEE):            Floating Point-i960. (line   6)
+* i960 machine directives:               Directives-i960.     (line   6)
+* i960 opcodes:                          Opcodes for i960.    (line   6)
+* i960 options:                          Options-i960.        (line   6)
+* i960 support:                          i960-Dependent.      (line   6)
+* IA-64 line comment character:          IA-64-Chars.         (line   6)
+* IA-64 line separator:                  IA-64-Chars.         (line   8)
+* IA-64 options:                         IA-64 Options.       (line   6)
+* IA-64 Processor-status-Register bit names: IA-64-Bits.      (line   6)
+* IA-64 registers:                       IA-64-Regs.          (line   6)
+* IA-64 support:                         IA-64-Dependent.     (line   6)
+* IA-64 Syntax:                          IA-64 Options.       (line  96)
+* ident directive:                       Ident.               (line   6)
+* identifiers, ARM:                      ARM-Chars.           (line  15)
+* identifiers, MSP 430:                  MSP430-Chars.        (line   8)
+* if directive:                          If.                  (line   6)
+* ifb directive:                         If.                  (line  21)
+* ifc directive:                         If.                  (line  25)
+* ifdef directive:                       If.                  (line  16)
+* ifeq directive:                        If.                  (line  33)
+* ifeqs directive:                       If.                  (line  36)
+* ifge directive:                        If.                  (line  40)
+* ifgt directive:                        If.                  (line  44)
+* ifle directive:                        If.                  (line  48)
+* iflt directive:                        If.                  (line  52)
+* ifnb directive:                        If.                  (line  56)
+* ifnc directive:                        If.                  (line  61)
+* ifndef directive:                      If.                  (line  65)
+* ifne directive:                        If.                  (line  72)
+* ifnes directive:                       If.                  (line  76)
+* ifnotdef directive:                    If.                  (line  65)
+* immediate character, ARM:              ARM-Chars.           (line  13)
+* immediate character, M680x0:           M68K-Chars.          (line   6)
+* immediate character, VAX:              VAX-operands.        (line   6)
+* immediate fields, relaxation:          Xtensa Immediate Relaxation.
+                                                              (line   6)
+* immediate operands, i386:              i386-Syntax.         (line  15)
+* immediate operands, x86-64:            i386-Syntax.         (line  15)
+* imul instruction, i386:                i386-Notes.          (line   6)
+* imul instruction, x86-64:              i386-Notes.          (line   6)
+* incbin directive:                      Incbin.              (line   6)
+* include directive:                     Include.             (line   6)
+* include directive search path:         I.                   (line   6)
+* indirect character, VAX:               VAX-operands.        (line   9)
+* infix operators:                       Infix Ops.           (line   6)
+* inhibiting interrupts, i386:           i386-Prefixes.       (line  36)
+* input:                                 Input Files.         (line   6)
+* input file linenumbers:                Input Files.         (line  35)
+* instruction expansion, CRIS:           CRIS-Expand.         (line   6)
+* instruction expansion, MMIX:           MMIX-Expand.         (line   6)
+* instruction naming, i386:              i386-Mnemonics.      (line   6)
+* instruction naming, x86-64:            i386-Mnemonics.      (line   6)
+* instruction prefixes, i386:            i386-Prefixes.       (line   6)
+* instruction set, M680x0:               M68K-opcodes.        (line   6)
+* instruction set, M68HC11:              M68HC11-opcodes.     (line   6)
+* instruction summary, D10V:             D10V-Opcodes.        (line   6)
+* instruction summary, D30V:             D30V-Opcodes.        (line   6)
+* instruction summary, H8/300:           H8/300 Opcodes.      (line   6)
+* instruction summary, SH:               SH Opcodes.          (line   6)
+* instruction summary, SH64:             SH64 Opcodes.        (line   6)
+* instruction summary, Z8000:            Z8000 Opcodes.       (line   6)
+* instructions and directives:           Statements.          (line  19)
+* int directive:                         Int.                 (line   6)
+* int directive, H8/300:                 H8/300 Directives.   (line   6)
+* int directive, i386:                   i386-Float.          (line  21)
+* int directive, TIC54X:                 TIC54X-Directives.   (line 111)
+* int directive, x86-64:                 i386-Float.          (line  21)
+* integer expressions:                   Integer Exprs.       (line   6)
+* integer, 16-byte:                      Octa.                (line   6)
+* integer, 8-byte:                       Quad.                (line   9)
+* integers:                              Integers.            (line   6)
+* integers, 16-bit:                      hword.               (line   6)
+* integers, 32-bit:                      Int.                 (line   6)
+* integers, binary:                      Integers.            (line   6)
+* integers, decimal:                     Integers.            (line  12)
+* integers, hexadecimal:                 Integers.            (line  15)
+* integers, octal:                       Integers.            (line   9)
+* integers, one byte:                    Byte.                (line   6)
+* intel_syntax pseudo op, i386:          i386-Syntax.         (line   6)
+* intel_syntax pseudo op, x86-64:        i386-Syntax.         (line   6)
+* internal assembler sections:           As Sections.         (line   6)
+* internal directive:                    Internal.            (line   6)
+* invalid input:                         Bug Criteria.        (line  14)
+* invocation summary:                    Overview.            (line   6)
+* IP2K architecture options:             IP2K-Opts.           (line   9)
+* IP2K options:                          IP2K-Opts.           (line   6)
+* IP2K support:                          IP2K-Dependent.      (line   6)
+* irp directive:                         Irp.                 (line   6)
+* irpc directive:                        Irpc.                (line   6)
+* ISA options, SH64:                     SH64 Options.        (line   6)
+* joining text and data sections:        R.                   (line   6)
+* jump instructions, i386:               i386-Mnemonics.      (line  51)
+* jump instructions, x86-64:             i386-Mnemonics.      (line  51)
+* jump optimization, i386:               i386-Jumps.          (line   6)
+* jump optimization, x86-64:             i386-Jumps.          (line   6)
+* jump/call operands, i386:              i386-Syntax.         (line  15)
+* jump/call operands, x86-64:            i386-Syntax.         (line  15)
+* L16SI instructions, relaxation:        Xtensa Immediate Relaxation.
+                                                              (line  23)
+* L16UI instructions, relaxation:        Xtensa Immediate Relaxation.
+                                                              (line  23)
+* L32I instructions, relaxation:         Xtensa Immediate Relaxation.
+                                                              (line  23)
+* L8UI instructions, relaxation:         Xtensa Immediate Relaxation.
+                                                              (line  23)
+* label (:):                             Statements.          (line  30)
+* label directive, TIC54X:               TIC54X-Directives.   (line 123)
+* labels:                                Labels.              (line   6)
+* lcomm directive:                       Lcomm.               (line   6)
+* ld:                                    Object.              (line  15)
+* ldouble directive M680x0:              M68K-Float.          (line  17)
+* ldouble directive M68HC11:             M68HC11-Float.       (line  17)
+* ldouble directive, TIC54X:             TIC54X-Directives.   (line  64)
+* LDR reg,=<label> pseudo op, ARM:       ARM Opcodes.         (line  15)
+* leafproc directive, i960:              Directives-i960.     (line  18)
+* length directive, TIC54X:              TIC54X-Directives.   (line 127)
+* length of symbols:                     Symbol Intro.        (line  14)
+* lflags directive (ignored):            Lflags.              (line   6)
+* line comment character:                Comments.            (line  19)
+* line comment character, Alpha:         Alpha-Chars.         (line   6)
+* line comment character, ARM:           ARM-Chars.           (line   6)
+* line comment character, D10V:          D10V-Chars.          (line   6)
+* line comment character, D30V:          D30V-Chars.          (line   6)
+* line comment character, H8/300:        H8/300-Chars.        (line   6)
+* line comment character, IA-64:         IA-64-Chars.         (line   6)
+* line comment character, M680x0:        M68K-Chars.          (line   6)
+* line comment character, MSP 430:       MSP430-Chars.        (line   6)
+* line comment character, SH:            SH-Chars.            (line   6)
+* line comment character, SH64:          SH64-Chars.          (line   6)
+* line comment character, V850:          V850-Chars.          (line   6)
+* line comment character, Z80:           Z80-Chars.           (line   6)
+* line comment character, Z8000:         Z8000-Chars.         (line   6)
+* line comment characters, CRIS:         CRIS-Chars.          (line   6)
+* line comment characters, MMIX:         MMIX-Chars.          (line   6)
+* line directive:                        Line.                (line   6)
+* line directive, MSP 430:               MSP430 Directives.   (line  14)
+* line numbers, in input files:          Input Files.         (line  35)
+* line numbers, in warnings/errors:      Errors.              (line  16)
+* line separator character:              Statements.          (line   6)
+* line separator, Alpha:                 Alpha-Chars.         (line   8)
+* line separator, ARM:                   ARM-Chars.           (line  10)
+* line separator, H8/300:                H8/300-Chars.        (line   8)
+* line separator, IA-64:                 IA-64-Chars.         (line   8)
+* line separator, SH:                    SH-Chars.            (line   8)
+* line separator, SH64:                  SH64-Chars.          (line   8)
+* line separator, Z8000:                 Z8000-Chars.         (line   8)
+* lines starting with #:                 Comments.            (line  38)
+* linker:                                Object.              (line  15)
+* linker, and assembler:                 Secs Background.     (line  10)
+* linkonce directive:                    Linkonce.            (line   6)
+* list directive:                        List.                (line   6)
+* list directive, TIC54X:                TIC54X-Directives.   (line 131)
+* listing control, turning off:          Nolist.              (line   6)
+* listing control, turning on:           List.                (line   6)
+* listing control: new page:             Eject.               (line   6)
+* listing control: paper size:           Psize.               (line   6)
+* listing control: subtitle:             Sbttl.               (line   6)
+* listing control: title line:           Title.               (line   6)
+* listings, enabling:                    a.                   (line   6)
+* literal directive:                     Literal Directive.   (line   6)
+* literal_position directive:            Literal Position Directive.
+                                                              (line   6)
+* literal_prefix directive:              Literal Prefix Directive.
+                                                              (line   6)
+* little endian output, MIPS:            Overview.            (line 609)
+* little endian output, PJ:              Overview.            (line 516)
+* little-endian output, MIPS:            MIPS Opts.           (line  13)
+* ln directive:                          Ln.                  (line   6)
+* lo pseudo-op, V850:                    V850 Opcodes.        (line  22)
+* loc directive:                         LNS directives.      (line  19)
+* loc_mark_blocks directive:             LNS directives.      (line  50)
+* local common symbols:                  Lcomm.               (line   6)
+* local labels, retaining in output:     L.                   (line   6)
+* local symbol names:                    Symbol Names.        (line  22)
+* location counter:                      Dot.                 (line   6)
+* location counter, advancing:           Org.                 (line   6)
+* location counter, Z80:                 Z80-Chars.           (line   8)
+* logical file name:                     File.                (line   6)
+* logical line number:                   Line.                (line   6)
+* logical line numbers:                  Comments.            (line  38)
+* long directive:                        Long.                (line   6)
+* long directive, ARC:                   ARC Directives.      (line 159)
+* long directive, i386:                  i386-Float.          (line  21)
+* long directive, TIC54X:                TIC54X-Directives.   (line 135)
+* long directive, x86-64:                i386-Float.          (line  21)
+* longcall pseudo-op, V850:              V850 Opcodes.        (line 123)
+* longcalls directive:                   Longcalls Directive. (line   6)
+* longjump pseudo-op, V850:              V850 Opcodes.        (line 129)
+* loop directive, TIC54X:                TIC54X-Directives.   (line 143)
+* LOOP instructions, alignment:          Xtensa Automatic Alignment.
+                                                              (line   6)
+* low directive, M32R:                   M32R-Directives.     (line   9)
+* lp register, V850:                     V850-Regs.           (line  98)
+* lval:                                  Z8000 Directives.    (line  27)
+* M16C architecture option:              M32C-Opts.           (line  12)
+* M32C architecture option:              M32C-Opts.           (line   9)
+* M32C modifiers:                        M32C-Modifiers.      (line   6)
+* M32C options:                          M32C-Opts.           (line   6)
+* M32C support:                          M32C-Dependent.      (line   6)
+* M32R architecture options:             M32R-Opts.           (line   9)
+* M32R directives:                       M32R-Directives.     (line   6)
+* M32R options:                          M32R-Opts.           (line   6)
+* M32R support:                          M32R-Dependent.      (line   6)
+* M32R warnings:                         M32R-Warnings.       (line   6)
+* M680x0 addressing modes:               M68K-Syntax.         (line  21)
+* M680x0 architecture options:           M68K-Opts.           (line 103)
+* M680x0 branch improvement:             M68K-Branch.         (line   6)
+* M680x0 directives:                     M68K-Directives.     (line   6)
+* M680x0 floating point:                 M68K-Float.          (line   6)
+* M680x0 immediate character:            M68K-Chars.          (line   6)
+* M680x0 line comment character:         M68K-Chars.          (line   6)
+* M680x0 opcodes:                        M68K-opcodes.        (line   6)
+* M680x0 options:                        M68K-Opts.           (line   6)
+* M680x0 pseudo-opcodes:                 M68K-Branch.         (line   6)
+* M680x0 size modifiers:                 M68K-Syntax.         (line   8)
+* M680x0 support:                        M68K-Dependent.      (line   6)
+* M680x0 syntax:                         M68K-Syntax.         (line   8)
+* M68HC11 addressing modes:              M68HC11-Syntax.      (line  17)
+* M68HC11 and M68HC12 support:           M68HC11-Dependent.   (line   6)
+* M68HC11 assembler directive .far:      M68HC11-Directives.  (line  20)
+* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line  26)
+* M68HC11 assembler directive .mode:     M68HC11-Directives.  (line  16)
+* M68HC11 assembler directive .relax:    M68HC11-Directives.  (line  10)
+* M68HC11 assembler directive .xrefb:    M68HC11-Directives.  (line  31)
+* M68HC11 assembler directives:          M68HC11-Directives.  (line   6)
+* M68HC11 branch improvement:            M68HC11-Branch.      (line   6)
+* M68HC11 floating point:                M68HC11-Float.       (line   6)
+* M68HC11 modifiers:                     M68HC11-Modifiers.   (line   6)
+* M68HC11 opcodes:                       M68HC11-opcodes.     (line   6)
+* M68HC11 options:                       M68HC11-Opts.        (line   6)
+* M68HC11 pseudo-opcodes:                M68HC11-Branch.      (line   6)
+* M68HC11 syntax:                        M68HC11-Syntax.      (line   6)
+* M68HC12 assembler directives:          M68HC11-Directives.  (line   6)
+* machine dependencies:                  Machine Dependencies.
+                                                              (line   6)
+* machine directives, ARC:               ARC Directives.      (line   6)
+* machine directives, ARM:               ARM Directives.      (line   6)
+* machine directives, H8/300 (none):     H8/300 Directives.   (line   6)
+* machine directives, i860:              Directives-i860.     (line   6)
+* machine directives, i960:              Directives-i960.     (line   6)
+* machine directives, MSP 430:           MSP430 Directives.   (line   6)
+* machine directives, SH:                SH Directives.       (line   6)
+* machine directives, SH64:              SH64 Directives.     (line   9)
+* machine directives, SPARC:             Sparc-Directives.    (line   6)
+* machine directives, TIC54X:            TIC54X-Directives.   (line   6)
+* machine directives, V850:              V850 Directives.     (line   6)
+* machine directives, VAX:               VAX-directives.      (line   6)
+* machine independent directives:        Pseudo Ops.          (line   6)
+* machine instructions (not covered):    Manual.              (line  14)
+* machine-independent syntax:            Syntax.              (line   6)
+* macro directive:                       Macro.               (line  28)
+* macro directive, TIC54X:               TIC54X-Directives.   (line 153)
+* macros:                                Macro.               (line   6)
+* macros, count executed:                Macro.               (line 101)
+* Macros, MSP 430:                       MSP430-Macros.       (line   6)
+* macros, TIC54X:                        TIC54X-Macros.       (line   6)
+* make rules:                            MD.                  (line   6)
+* manual, structure and purpose:         Manual.              (line   6)
+* math builtins, TIC54X:                 TIC54X-Builtins.     (line   6)
+* Maximum number of continuation lines:  listing.             (line  33)
+* memory references, i386:               i386-Memory.         (line   6)
+* memory references, x86-64:             i386-Memory.         (line   6)
+* memory-mapped registers, TIC54X:       TIC54X-MMRegs.       (line   6)
+* merging text and data sections:        R.                   (line   6)
+* messages from assembler:               Errors.              (line   6)
+* minus, permitted arguments:            Infix Ops.           (line  49)
+* MIPS architecture options:             MIPS Opts.           (line  20)
+* MIPS big-endian output:                MIPS Opts.           (line  13)
+* MIPS debugging directives:             MIPS Stabs.          (line   6)
+* MIPS DSP instruction generation override: MIPS ASE instruction generation overrides.
+                                                              (line  16)
+* MIPS ECOFF sections:                   MIPS Object.         (line   6)
+* MIPS endianness:                       Overview.            (line 606)
+* MIPS ISA:                              Overview.            (line 612)
+* MIPS ISA override:                     MIPS ISA.            (line   6)
+* MIPS little-endian output:             MIPS Opts.           (line  13)
+* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides.
+                                                              (line  11)
+* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides.
+                                                              (line   6)
+* MIPS MT instruction generation override: MIPS ASE instruction generation overrides.
+                                                              (line  21)
+* MIPS option stack:                     MIPS option stack.   (line   6)
+* MIPS processor:                        MIPS-Dependent.      (line   6)
+* MIT:                                   M68K-Syntax.         (line   6)
+* mlib directive, TIC54X:                TIC54X-Directives.   (line 159)
+* mlist directive, TIC54X:               TIC54X-Directives.   (line 164)
+* MMIX assembler directive BSPEC:        MMIX-Pseudos.        (line 131)
+* MMIX assembler directive BYTE:         MMIX-Pseudos.        (line  97)
+* MMIX assembler directive ESPEC:        MMIX-Pseudos.        (line 131)
+* MMIX assembler directive GREG:         MMIX-Pseudos.        (line  50)
+* MMIX assembler directive IS:           MMIX-Pseudos.        (line  42)
+* MMIX assembler directive LOC:          MMIX-Pseudos.        (line   7)
+* MMIX assembler directive LOCAL:        MMIX-Pseudos.        (line  28)
+* MMIX assembler directive OCTA:         MMIX-Pseudos.        (line 108)
+* MMIX assembler directive PREFIX:       MMIX-Pseudos.        (line 120)
+* MMIX assembler directive TETRA:        MMIX-Pseudos.        (line 108)
+* MMIX assembler directive WYDE:         MMIX-Pseudos.        (line 108)
+* MMIX assembler directives:             MMIX-Pseudos.        (line   6)
+* MMIX line comment characters:          MMIX-Chars.          (line   6)
+* MMIX options:                          MMIX-Opts.           (line   6)
+* MMIX pseudo-op BSPEC:                  MMIX-Pseudos.        (line 131)
+* MMIX pseudo-op BYTE:                   MMIX-Pseudos.        (line  97)
+* MMIX pseudo-op ESPEC:                  MMIX-Pseudos.        (line 131)
+* MMIX pseudo-op GREG:                   MMIX-Pseudos.        (line  50)
+* MMIX pseudo-op IS:                     MMIX-Pseudos.        (line  42)
+* MMIX pseudo-op LOC:                    MMIX-Pseudos.        (line   7)
+* MMIX pseudo-op LOCAL:                  MMIX-Pseudos.        (line  28)
+* MMIX pseudo-op OCTA:                   MMIX-Pseudos.        (line 108)
+* MMIX pseudo-op PREFIX:                 MMIX-Pseudos.        (line 120)
+* MMIX pseudo-op TETRA:                  MMIX-Pseudos.        (line 108)
+* MMIX pseudo-op WYDE:                   MMIX-Pseudos.        (line 108)
+* MMIX pseudo-ops:                       MMIX-Pseudos.        (line   6)
+* MMIX register names:                   MMIX-Regs.           (line   6)
+* MMIX support:                          MMIX-Dependent.      (line   6)
+* mmixal differences:                    MMIX-mmixal.         (line   6)
+* mmregs directive, TIC54X:              TIC54X-Directives.   (line 170)
+* mmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
+* MMX, i386:                             i386-SIMD.           (line   6)
+* MMX, x86-64:                           i386-SIMD.           (line   6)
+* mnemonic suffixes, i386:               i386-Syntax.         (line  29)
+* mnemonic suffixes, x86-64:             i386-Syntax.         (line  29)
+* mnemonics for opcodes, VAX:            VAX-opcodes.         (line   6)
+* mnemonics, D10V:                       D10V-Opcodes.        (line   6)
+* mnemonics, D30V:                       D30V-Opcodes.        (line   6)
+* mnemonics, H8/300:                     H8/300 Opcodes.      (line   6)
+* mnemonics, SH:                         SH Opcodes.          (line   6)
+* mnemonics, SH64:                       SH64 Opcodes.        (line   6)
+* mnemonics, Z8000:                      Z8000 Opcodes.       (line   6)
+* mnolist directive, TIC54X:             TIC54X-Directives.   (line 164)
+* Motorola syntax for the 680x0:         M68K-Moto-Syntax.    (line   6)
+* MOVI instructions, relaxation:         Xtensa Immediate Relaxation.
+                                                              (line  12)
+* MRI compatibility mode:                M.                   (line   6)
+* mri directive:                         MRI.                 (line   6)
+* MRI mode, temporarily:                 MRI.                 (line   6)
+* MSP 430 floating point (IEEE):         MSP430 Floating Point.
+                                                              (line   6)
+* MSP 430 identifiers:                   MSP430-Chars.        (line   8)
+* MSP 430 line comment character:        MSP430-Chars.        (line   6)
+* MSP 430 machine directives:            MSP430 Directives.   (line   6)
+* MSP 430 macros:                        MSP430-Macros.       (line   6)
+* MSP 430 opcodes:                       MSP430 Opcodes.      (line   6)
+* MSP 430 options (none):                MSP430 Options.      (line   6)
+* MSP 430 profiling capability:          MSP430 Profiling Capability.
+                                                              (line   6)
+* MSP 430 register names:                MSP430-Regs.         (line   6)
+* MSP 430 support:                       MSP430-Dependent.    (line   6)
+* MSP430 Assembler Extensions:           MSP430-Ext.          (line   6)
+* mul instruction, i386:                 i386-Notes.          (line   6)
+* mul instruction, x86-64:               i386-Notes.          (line   6)
+* name:                                  Z8000 Directives.    (line  18)
+* named section:                         Section.             (line   6)
+* named sections:                        Ld Sections.         (line   8)
+* names, symbol:                         Symbol Names.        (line   6)
+* naming object file:                    o.                   (line   6)
+* new page, in listings:                 Eject.               (line   6)
+* newblock directive, TIC54X:            TIC54X-Directives.   (line 176)
+* newline (\n):                          Strings.             (line  21)
+* newline, required at file end:         Statements.          (line  13)
+* no-absolute-literals directive:        Absolute Literals Directive.
+                                                              (line   6)
+* no-longcalls directive:                Longcalls Directive. (line   6)
+* no-schedule directive:                 Schedule Directive.  (line   6)
+* no-transform directive:                Transform Directive. (line   6)
+* nolist directive:                      Nolist.              (line   6)
+* nolist directive, TIC54X:              TIC54X-Directives.   (line 131)
+* NOP pseudo op, ARM:                    ARM Opcodes.         (line   9)
+* notes for Alpha:                       Alpha Notes.         (line   6)
+* null-terminated strings:               Asciz.               (line   6)
+* number constants:                      Numbers.             (line   6)
+* number of macros executed:             Macro.               (line 101)
+* numbered subsections:                  Sub-Sections.        (line   6)
+* numbers, 16-bit:                       hword.               (line   6)
+* numeric values:                        Expressions.         (line   6)
+* nword directive, SPARC:                Sparc-Directives.    (line  20)
+* object file:                           Object.              (line   6)
+* object file format:                    Object Formats.      (line   6)
+* object file name:                      o.                   (line   6)
+* object file, after errors:             Z.                   (line   6)
+* obsolescent directives:                Deprecated.          (line   6)
+* octa directive:                        Octa.                (line   6)
+* octal character code (\DDD):           Strings.             (line  30)
+* octal integers:                        Integers.            (line   9)
+* offset directive, V850:                V850 Directives.     (line   6)
+* opcode mnemonics, VAX:                 VAX-opcodes.         (line   6)
+* opcode names, Xtensa:                  Xtensa Opcodes.      (line   6)
+* opcode summary, D10V:                  D10V-Opcodes.        (line   6)
+* opcode summary, D30V:                  D30V-Opcodes.        (line   6)
+* opcode summary, H8/300:                H8/300 Opcodes.      (line   6)
+* opcode summary, SH:                    SH Opcodes.          (line   6)
+* opcode summary, SH64:                  SH64 Opcodes.        (line   6)
+* opcode summary, Z8000:                 Z8000 Opcodes.       (line   6)
+* opcodes for ARC:                       ARC Opcodes.         (line   6)
+* opcodes for ARM:                       ARM Opcodes.         (line   6)
+* opcodes for MSP 430:                   MSP430 Opcodes.      (line   6)
+* opcodes for V850:                      V850 Opcodes.        (line   6)
+* opcodes, i860:                         Opcodes for i860.    (line   6)
+* opcodes, i960:                         Opcodes for i960.    (line   6)
+* opcodes, M680x0:                       M68K-opcodes.        (line   6)
+* opcodes, M68HC11:                      M68HC11-opcodes.     (line   6)
+* operand delimiters, i386:              i386-Syntax.         (line  15)
+* operand delimiters, x86-64:            i386-Syntax.         (line  15)
+* operand notation, VAX:                 VAX-operands.        (line   6)
+* operands in expressions:               Arguments.           (line   6)
+* operator precedence:                   Infix Ops.           (line  11)
+* operators, in expressions:             Operators.           (line   6)
+* operators, permitted arguments:        Infix Ops.           (line   6)
+* optimization, D10V:                    Overview.            (line 391)
+* optimization, D30V:                    Overview.            (line 396)
+* optimizations:                         Xtensa Optimizations.
+                                                              (line   6)
+* option directive, ARC:                 ARC Directives.      (line 162)
+* option directive, TIC54X:              TIC54X-Directives.   (line 180)
+* option summary:                        Overview.            (line   6)
+* options for Alpha:                     Alpha Options.       (line   6)
+* options for ARC (none):                ARC Options.         (line   6)
+* options for ARM (none):                ARM Options.         (line   6)
+* options for i386:                      i386-Options.        (line   6)
+* options for IA-64:                     IA-64 Options.       (line   6)
+* options for MSP430 (none):             MSP430 Options.      (line   6)
+* options for PDP-11:                    PDP-11-Options.      (line   6)
+* options for PowerPC:                   PowerPC-Opts.        (line   6)
+* options for SPARC:                     Sparc-Opts.          (line   6)
+* options for V850 (none):               V850 Options.        (line   6)
+* options for VAX/VMS:                   VAX-Opts.            (line  42)
+* options for x86-64:                    i386-Options.        (line   6)
+* options for Z80:                       Z80 Options.         (line   6)
+* options, all versions of assembler:    Invoking.            (line   6)
+* options, command line:                 Command Line.        (line  13)
+* options, CRIS:                         CRIS-Opts.           (line   6)
+* options, D10V:                         D10V-Opts.           (line   6)
+* options, D30V:                         D30V-Opts.           (line   6)
+* options, H8/300 (none):                H8/300 Options.      (line   6)
+* options, i960:                         Options-i960.        (line   6)
+* options, IP2K:                         IP2K-Opts.           (line   6)
+* options, M32C:                         M32C-Opts.           (line   6)
+* options, M32R:                         M32R-Opts.           (line   6)
+* options, M680x0:                       M68K-Opts.           (line   6)
+* options, M68HC11:                      M68HC11-Opts.        (line   6)
+* options, MMIX:                         MMIX-Opts.           (line   6)
+* options, PJ:                           PJ Options.          (line   6)
+* options, SH:                           SH Options.          (line   6)
+* options, SH64:                         SH64 Options.        (line   6)
+* options, TIC54X:                       TIC54X-Opts.         (line   6)
+* options, Z8000:                        Z8000 Options.       (line   6)
+* org directive:                         Org.                 (line   6)
+* other attribute, of a.out symbol:      Symbol Other.        (line   6)
+* output file:                           Object.              (line   6)
+* p2align directive:                     P2align.             (line   6)
+* p2alignl directive:                    P2align.             (line  28)
+* p2alignw directive:                    P2align.             (line  28)
+* padding the location counter:          Align.               (line   6)
+* padding the location counter given a power of two: P2align. (line   6)
+* padding the location counter given number of bytes: Balign. (line   6)
+* page, in listings:                     Eject.               (line   6)
+* paper size, for listings:              Psize.               (line   6)
+* paths for .include:                    I.                   (line   6)
+* patterns, writing in memory:           Fill.                (line   6)
+* PDP-11 comments:                       PDP-11-Syntax.       (line  16)
+* PDP-11 floating-point register syntax: PDP-11-Syntax.       (line  13)
+* PDP-11 general-purpose register syntax: PDP-11-Syntax.      (line  10)
+* PDP-11 instruction naming:             PDP-11-Mnemonics.    (line   6)
+* PDP-11 support:                        PDP-11-Dependent.    (line   6)
+* PDP-11 syntax:                         PDP-11-Syntax.       (line   6)
+* PIC code generation for ARM:           ARM Options.         (line 120)
+* PIC code generation for M32R:          M32R-Opts.           (line  42)
+* PJ endianness:                         Overview.            (line 513)
+* PJ options:                            PJ Options.          (line   6)
+* PJ support:                            PJ-Dependent.        (line   6)
+* plus, permitted arguments:             Infix Ops.           (line  44)
+* popsection directive:                  PopSection.          (line   6)
+* Position-independent code, CRIS:       CRIS-Opts.           (line  27)
+* Position-independent code, symbols in, CRIS: CRIS-Pic.      (line   6)
+* PowerPC architectures:                 PowerPC-Opts.        (line   6)
+* PowerPC directives:                    PowerPC-Pseudo.      (line   6)
+* PowerPC options:                       PowerPC-Opts.        (line   6)
+* PowerPC support:                       PPC-Dependent.       (line   6)
+* precedence of operators:               Infix Ops.           (line  11)
+* precision, floating point:             Flonums.             (line   6)
+* prefix operators:                      Prefix Ops.          (line   6)
+* prefixes, i386:                        i386-Prefixes.       (line   6)
+* preprocessing:                         Preprocessing.       (line   6)
+* preprocessing, turning on and off:     Preprocessing.       (line  27)
+* previous directive:                    Previous.            (line   6)
+* primary attributes, COFF symbols:      COFF Symbols.        (line  13)
+* print directive:                       Print.               (line   6)
+* proc directive, SPARC:                 Sparc-Directives.    (line  25)
+* profiler directive, MSP 430:           MSP430 Directives.   (line  22)
+* profiling capability for MSP 430:      MSP430 Profiling Capability.
+                                                              (line   6)
+* protected directive:                   Protected.           (line   6)
+* pseudo-op .arch, CRIS:                 CRIS-Pseudos.        (line  45)
+* pseudo-op .dword, CRIS:                CRIS-Pseudos.        (line  12)
+* pseudo-op .syntax, CRIS:               CRIS-Pseudos.        (line  17)
+* pseudo-op BSPEC, MMIX:                 MMIX-Pseudos.        (line 131)
+* pseudo-op BYTE, MMIX:                  MMIX-Pseudos.        (line  97)
+* pseudo-op ESPEC, MMIX:                 MMIX-Pseudos.        (line 131)
+* pseudo-op GREG, MMIX:                  MMIX-Pseudos.        (line  50)
+* pseudo-op IS, MMIX:                    MMIX-Pseudos.        (line  42)
+* pseudo-op LOC, MMIX:                   MMIX-Pseudos.        (line   7)
+* pseudo-op LOCAL, MMIX:                 MMIX-Pseudos.        (line  28)
+* pseudo-op OCTA, MMIX:                  MMIX-Pseudos.        (line 108)
+* pseudo-op PREFIX, MMIX:                MMIX-Pseudos.        (line 120)
+* pseudo-op TETRA, MMIX:                 MMIX-Pseudos.        (line 108)
+* pseudo-op WYDE, MMIX:                  MMIX-Pseudos.        (line 108)
+* pseudo-opcodes, M680x0:                M68K-Branch.         (line   6)
+* pseudo-opcodes, M68HC11:               M68HC11-Branch.      (line   6)
+* pseudo-ops for branch, VAX:            VAX-branch.          (line   6)
+* pseudo-ops, CRIS:                      CRIS-Pseudos.        (line   6)
+* pseudo-ops, machine independent:       Pseudo Ops.          (line   6)
+* pseudo-ops, MMIX:                      MMIX-Pseudos.        (line   6)
+* psize directive:                       Psize.               (line   6)
+* PSR bits:                              IA-64-Bits.          (line   6)
+* pstring directive, TIC54X:             TIC54X-Directives.   (line 209)
+* psw register, V850:                    V850-Regs.           (line 116)
+* purgem directive:                      Purgem.              (line   6)
+* purpose of GNU assembler:              GNU Assembler.       (line  12)
+* pushsection directive:                 PushSection.         (line   6)
+* quad directive:                        Quad.                (line   6)
+* quad directive, i386:                  i386-Float.          (line  21)
+* quad directive, x86-64:                i386-Float.          (line  21)
+* real-mode code, i386:                  i386-16bit.          (line   6)
+* ref directive, TIC54X:                 TIC54X-Directives.   (line 103)
+* register directive, SPARC:             Sparc-Directives.    (line  29)
+* register names, Alpha:                 Alpha-Regs.          (line   6)
+* register names, ARC:                   ARC-Regs.            (line   6)
+* register names, ARM:                   ARM-Regs.            (line   6)
+* register names, CRIS:                  CRIS-Regs.           (line   6)
+* register names, H8/300:                H8/300-Regs.         (line   6)
+* register names, IA-64:                 IA-64-Regs.          (line   6)
+* register names, MMIX:                  MMIX-Regs.           (line   6)
+* register names, MSP 430:               MSP430-Regs.         (line   6)
+* register names, V850:                  V850-Regs.           (line   6)
+* register names, VAX:                   VAX-operands.        (line  17)
+* register names, Xtensa:                Xtensa Registers.    (line   6)
+* register names, Z80:                   Z80-Regs.            (line   6)
+* register operands, i386:               i386-Syntax.         (line  15)
+* register operands, x86-64:             i386-Syntax.         (line  15)
+* registers, D10V:                       D10V-Regs.           (line   6)
+* registers, D30V:                       D30V-Regs.           (line   6)
+* registers, i386:                       i386-Regs.           (line   6)
+* registers, SH:                         SH-Regs.             (line   6)
+* registers, SH64:                       SH64-Regs.           (line   6)
+* registers, TIC54X memory-mapped:       TIC54X-MMRegs.       (line   6)
+* registers, x86-64:                     i386-Regs.           (line   6)
+* registers, Z8000:                      Z8000-Regs.          (line   6)
+* relaxation:                            Xtensa Relaxation.   (line   6)
+* relaxation of ADDI instructions:       Xtensa Immediate Relaxation.
+                                                              (line  43)
+* relaxation of branch instructions:     Xtensa Branch Relaxation.
+                                                              (line   6)
+* relaxation of call instructions:       Xtensa Call Relaxation.
+                                                              (line   6)
+* relaxation of immediate fields:        Xtensa Immediate Relaxation.
+                                                              (line   6)
+* relaxation of L16SI instructions:      Xtensa Immediate Relaxation.
+                                                              (line  23)
+* relaxation of L16UI instructions:      Xtensa Immediate Relaxation.
+                                                              (line  23)
+* relaxation of L32I instructions:       Xtensa Immediate Relaxation.
+                                                              (line  23)
+* relaxation of L8UI instructions:       Xtensa Immediate Relaxation.
+                                                              (line  23)
+* relaxation of MOVI instructions:       Xtensa Immediate Relaxation.
+                                                              (line  12)
+* relocation:                            Sections.            (line   6)
+* relocation example:                    Ld Sections.         (line  40)
+* relocations, Alpha:                    Alpha-Relocs.        (line   6)
+* repeat prefixes, i386:                 i386-Prefixes.       (line  44)
+* reporting bugs in assembler:           Reporting Bugs.      (line   6)
+* rept directive:                        Rept.                (line   6)
+* req directive, ARM:                    ARM Directives.      (line  13)
+* reserve directive, SPARC:              Sparc-Directives.    (line  39)
+* return instructions, i386:             i386-Syntax.         (line  38)
+* return instructions, x86-64:           i386-Syntax.         (line  38)
+* REX prefixes, i386:                    i386-Prefixes.       (line  46)
+* rsect:                                 Z8000 Directives.    (line  52)
+* sblock directive, TIC54X:              TIC54X-Directives.   (line 183)
+* sbttl directive:                       Sbttl.               (line   6)
+* schedule directive:                    Schedule Directive.  (line   6)
+* scl directive:                         Scl.                 (line   6)
+* sdaoff pseudo-op, V850:                V850 Opcodes.        (line  65)
+* search path for .include:              I.                   (line   6)
+* sect directive, MSP 430:               MSP430 Directives.   (line  18)
+* sect directive, TIC54X:                TIC54X-Directives.   (line 189)
+* section directive (COFF version):      Section.             (line  16)
+* section directive (ELF version):       Section.             (line  67)
+* section directive, V850:               V850 Directives.     (line   9)
+* section override prefixes, i386:       i386-Prefixes.       (line  23)
+* Section Stack <1>:                     SubSection.          (line   6)
+* Section Stack <2>:                     Section.             (line  62)
+* Section Stack <3>:                     PushSection.         (line   6)
+* Section Stack <4>:                     PopSection.          (line   6)
+* Section Stack:                         Previous.            (line   6)
+* section-relative addressing:           Secs Background.     (line  68)
+* sections:                              Sections.            (line   6)
+* sections in messages, internal:        As Sections.         (line   6)
+* sections, i386:                        i386-Syntax.         (line  44)
+* sections, named:                       Ld Sections.         (line   8)
+* sections, x86-64:                      i386-Syntax.         (line  44)
+* seg directive, SPARC:                  Sparc-Directives.    (line  44)
+* segm:                                  Z8000 Directives.    (line  10)
+* set directive:                         Set.                 (line   6)
+* set directive, TIC54X:                 TIC54X-Directives.   (line 192)
+* SH addressing modes:                   SH-Addressing.       (line   6)
+* SH floating point (IEEE):              SH Floating Point.   (line   6)
+* SH line comment character:             SH-Chars.            (line   6)
+* SH line separator:                     SH-Chars.            (line   8)
+* SH machine directives:                 SH Directives.       (line   6)
+* SH opcode summary:                     SH Opcodes.          (line   6)
+* SH options:                            SH Options.          (line   6)
+* SH registers:                          SH-Regs.             (line   6)
+* SH support:                            SH-Dependent.        (line   6)
+* SH64 ABI options:                      SH64 Options.        (line  29)
+* SH64 addressing modes:                 SH64-Addressing.     (line   6)
+* SH64 ISA options:                      SH64 Options.        (line   6)
+* SH64 line comment character:           SH64-Chars.          (line   6)
+* SH64 line separator:                   SH64-Chars.          (line   8)
+* SH64 machine directives:               SH64 Directives.     (line   9)
+* SH64 opcode summary:                   SH64 Opcodes.        (line   6)
+* SH64 options:                          SH64 Options.        (line   6)
+* SH64 registers:                        SH64-Regs.           (line   6)
+* SH64 support:                          SH64-Dependent.      (line   6)
+* shigh directive, M32R:                 M32R-Directives.     (line  26)
+* short directive:                       Short.               (line   6)
+* short directive, ARC:                  ARC Directives.      (line 171)
+* short directive, TIC54X:               TIC54X-Directives.   (line 111)
+* SIMD, i386:                            i386-SIMD.           (line   6)
+* SIMD, x86-64:                          i386-SIMD.           (line   6)
+* single character constant:             Chars.               (line   6)
+* single directive:                      Single.              (line   6)
+* single directive, i386:                i386-Float.          (line  14)
+* single directive, x86-64:              i386-Float.          (line  14)
+* single quote, Z80:                     Z80-Chars.           (line  13)
+* sixteen bit integers:                  hword.               (line   6)
+* sixteen byte integer:                  Octa.                (line   6)
+* size directive (COFF version):         Size.                (line  11)
+* size directive (ELF version):          Size.                (line  19)
+* size modifiers, D10V:                  D10V-Size.           (line   6)
+* size modifiers, D30V:                  D30V-Size.           (line   6)
+* size modifiers, M680x0:                M68K-Syntax.         (line   8)
+* size prefixes, i386:                   i386-Prefixes.       (line  27)
+* size suffixes, H8/300:                 H8/300 Opcodes.      (line 163)
+* sizes operands, i386:                  i386-Syntax.         (line  29)
+* sizes operands, x86-64:                i386-Syntax.         (line  29)
+* skip directive:                        Skip.                (line   6)
+* skip directive, M680x0:                M68K-Directives.     (line  19)
+* skip directive, SPARC:                 Sparc-Directives.    (line  48)
+* sleb128 directive:                     Sleb128.             (line   6)
+* small objects, MIPS ECOFF:             MIPS Object.         (line  11)
+* SOM symbol attributes:                 SOM Symbols.         (line   6)
+* source program:                        Input Files.         (line   6)
+* source, destination operands; i386:    i386-Syntax.         (line  22)
+* source, destination operands; x86-64:  i386-Syntax.         (line  22)
+* sp register:                           Xtensa Registers.    (line   6)
+* sp register, V850:                     V850-Regs.           (line  14)
+* space directive:                       Space.               (line   6)
+* space directive, TIC54X:               TIC54X-Directives.   (line 197)
+* space used, maximum for assembly:      statistics.          (line   6)
+* SPARC architectures:                   Sparc-Opts.          (line   6)
+* SPARC data alignment:                  Sparc-Aligned-Data.  (line   6)
+* SPARC floating point (IEEE):           Sparc-Float.         (line   6)
+* SPARC machine directives:              Sparc-Directives.    (line   6)
+* SPARC options:                         Sparc-Opts.          (line   6)
+* SPARC support:                         Sparc-Dependent.     (line   6)
+* special characters, ARC:               ARC-Chars.           (line   6)
+* special characters, M680x0:            M68K-Chars.          (line   6)
+* special purpose registers, MSP 430:    MSP430-Regs.         (line  11)
+* sslist directive, TIC54X:              TIC54X-Directives.   (line 204)
+* ssnolist directive, TIC54X:            TIC54X-Directives.   (line 204)
+* stabd directive:                       Stab.                (line  38)
+* stabn directive:                       Stab.                (line  48)
+* stabs directive:                       Stab.                (line  51)
+* stabX directives:                      Stab.                (line   6)
+* standard assembler sections:           Secs Background.     (line  27)
+* standard input, as input file:         Command Line.        (line  10)
+* statement separator character:         Statements.          (line   6)
+* statement separator, Alpha:            Alpha-Chars.         (line   8)
+* statement separator, ARM:              ARM-Chars.           (line  10)
+* statement separator, H8/300:           H8/300-Chars.        (line   8)
+* statement separator, IA-64:            IA-64-Chars.         (line   8)
+* statement separator, SH:               SH-Chars.            (line   8)
+* statement separator, SH64:             SH64-Chars.          (line   8)
+* statement separator, Z8000:            Z8000-Chars.         (line   8)
+* statements, structure of:              Statements.          (line   6)
+* statistics, about assembly:            statistics.          (line   6)
+* stopping the assembly:                 Abort.               (line   6)
+* string constants:                      Strings.             (line   6)
+* string directive:                      String.              (line   6)
+* string directive on HPPA:              HPPA Directives.     (line 137)
+* string directive, TIC54X:              TIC54X-Directives.   (line 209)
+* string literals:                       Ascii.               (line   6)
+* string, copying to object file:        String.              (line   6)
+* struct directive:                      Struct.              (line   6)
+* struct directive, TIC54X:              TIC54X-Directives.   (line 217)
+* structure debugging, COFF:             Tag.                 (line   6)
+* sub-instruction ordering, D10V:        D10V-Chars.          (line   6)
+* sub-instruction ordering, D30V:        D30V-Chars.          (line   6)
+* sub-instructions, D10V:                D10V-Subs.           (line   6)
+* sub-instructions, D30V:                D30V-Subs.           (line   6)
+* subexpressions:                        Arguments.           (line  24)
+* subsection directive:                  SubSection.          (line   6)
+* subsym builtins, TIC54X:               TIC54X-Macros.       (line  16)
+* subtitles for listings:                Sbttl.               (line   6)
+* subtraction, permitted arguments:      Infix Ops.           (line  49)
+* summary of options:                    Overview.            (line   6)
+* support:                               HPPA-Dependent.      (line   6)
+* supporting files, including:           Include.             (line   6)
+* suppressing warnings:                  W.                   (line  11)
+* sval:                                  Z8000 Directives.    (line  33)
+* symbol attributes:                     Symbol Attributes.   (line   6)
+* symbol attributes, a.out:              a.out Symbols.       (line   6)
+* symbol attributes, COFF:               COFF Symbols.        (line   6)
+* symbol attributes, SOM:                SOM Symbols.         (line   6)
+* symbol descriptor, COFF:               Desc.                (line   6)
+* symbol modifiers <1>:                  M68HC11-Modifiers.   (line  12)
+* symbol modifiers:                      M32C-Modifiers.      (line  11)
+* symbol names:                          Symbol Names.        (line   6)
+* symbol names, $ in <1>:                SH64-Chars.          (line  10)
+* symbol names, $ in <2>:                SH-Chars.            (line  10)
+* symbol names, $ in <3>:                D30V-Chars.          (line  63)
+* symbol names, $ in:                    D10V-Chars.          (line  46)
+* symbol names, local:                   Symbol Names.        (line  22)
+* symbol names, temporary:               Symbol Names.        (line  22)
+* symbol storage class (COFF):           Scl.                 (line   6)
+* symbol type:                           Symbol Type.         (line   6)
+* symbol type, COFF:                     Type.                (line  11)
+* symbol type, ELF:                      Type.                (line  22)
+* symbol value:                          Symbol Value.        (line   6)
+* symbol value, setting:                 Set.                 (line   6)
+* symbol values, assigning:              Setting Symbols.     (line   6)
+* symbol versioning:                     Symver.              (line   6)
+* symbol, common:                        Comm.                (line   6)
+* symbol, making visible to linker:      Global.              (line   6)
+* symbolic debuggers, information for:   Stab.                (line   6)
+* symbols:                               Symbols.             (line   6)
+* Symbols in position-independent code, CRIS: CRIS-Pic.       (line   6)
+* symbols with uppercase, VAX/VMS:       VAX-Opts.            (line  42)
+* symbols, assigning values to:          Equ.                 (line   6)
+* Symbols, built-in, CRIS:               CRIS-Symbols.        (line   6)
+* Symbols, CRIS, built-in:               CRIS-Symbols.        (line   6)
+* symbols, local common:                 Lcomm.               (line   6)
+* symver directive:                      Symver.              (line   6)
+* syntax compatibility, i386:            i386-Syntax.         (line   6)
+* syntax compatibility, x86-64:          i386-Syntax.         (line   6)
+* syntax, BFIN:                          BFIN Syntax.         (line   6)
+* syntax, D10V:                          D10V-Syntax.         (line   6)
+* syntax, D30V:                          D30V-Syntax.         (line   6)
+* syntax, M32C:                          M32C-Modifiers.      (line   6)
+* syntax, M680x0:                        M68K-Syntax.         (line   8)
+* syntax, M68HC11 <1>:                   M68HC11-Modifiers.   (line   6)
+* syntax, M68HC11:                       M68HC11-Syntax.      (line   6)
+* syntax, machine-independent:           Syntax.              (line   6)
+* syntax, Xtensa assembler:              Xtensa Syntax.       (line   6)
+* sysproc directive, i960:               Directives-i960.     (line  37)
+* tab (\t):                              Strings.             (line  27)
+* tab directive, TIC54X:                 TIC54X-Directives.   (line 248)
+* tag directive:                         Tag.                 (line   6)
+* tag directive, TIC54X:                 TIC54X-Directives.   (line 217)
+* tdaoff pseudo-op, V850:                V850 Opcodes.        (line  81)
+* temporary symbol names:                Symbol Names.        (line  22)
+* text and data sections, joining:       R.                   (line   6)
+* text directive:                        Text.                (line   6)
+* text section:                          Ld Sections.         (line   9)
+* tfloat directive, i386:                i386-Float.          (line  14)
+* tfloat directive, x86-64:              i386-Float.          (line  14)
+* thumb directive, ARM:                  ARM Directives.      (line  33)
+* Thumb support:                         ARM-Dependent.       (line   6)
+* thumb_func directive, ARM:             ARM Directives.      (line  43)
+* thumb_set directive, ARM:              ARM Directives.      (line  51)
+* TIC54X builtin math functions:         TIC54X-Builtins.     (line   6)
+* TIC54X machine directives:             TIC54X-Directives.   (line   6)
+* TIC54X memory-mapped registers:        TIC54X-MMRegs.       (line   6)
+* TIC54X options:                        TIC54X-Opts.         (line   6)
+* TIC54X subsym builtins:                TIC54X-Macros.       (line  16)
+* TIC54X support:                        TIC54X-Dependent.    (line   6)
+* TIC54X-specific macros:                TIC54X-Macros.       (line   6)
+* time, total for assembly:              statistics.          (line   6)
+* title directive:                       Title.               (line   6)
+* tp register, V850:                     V850-Regs.           (line  20)
+* transform directive:                   Transform Directive. (line   6)
+* trusted compiler:                      f.                   (line   6)
+* turning preprocessing on and off:      Preprocessing.       (line  27)
+* type directive (COFF version):         Type.                (line  11)
+* type directive (ELF version):          Type.                (line  22)
+* type of a symbol:                      Symbol Type.         (line   6)
+* ualong directive, SH:                  SH Directives.       (line   6)
+* uaword directive, SH:                  SH Directives.       (line   6)
+* ubyte directive, TIC54X:               TIC54X-Directives.   (line  36)
+* uchar directive, TIC54X:               TIC54X-Directives.   (line  36)
+* uhalf directive, TIC54X:               TIC54X-Directives.   (line 111)
+* uint directive, TIC54X:                TIC54X-Directives.   (line 111)
+* uleb128 directive:                     Uleb128.             (line   6)
+* ulong directive, TIC54X:               TIC54X-Directives.   (line 135)
+* undefined section:                     Ld Sections.         (line  36)
+* union directive, TIC54X:               TIC54X-Directives.   (line 251)
+* unreq directive, ARM:                  ARM Directives.      (line  18)
+* unsegm:                                Z8000 Directives.    (line  14)
+* usect directive, TIC54X:               TIC54X-Directives.   (line 263)
+* ushort directive, TIC54X:              TIC54X-Directives.   (line 111)
+* uword directive, TIC54X:               TIC54X-Directives.   (line 111)
+* V850 command line options:             V850 Options.        (line   9)
+* V850 floating point (IEEE):            V850 Floating Point. (line   6)
+* V850 line comment character:           V850-Chars.          (line   6)
+* V850 machine directives:               V850 Directives.     (line   6)
+* V850 opcodes:                          V850 Opcodes.        (line   6)
+* V850 options (none):                   V850 Options.        (line   6)
+* V850 register names:                   V850-Regs.           (line   6)
+* V850 support:                          V850-Dependent.      (line   6)
+* val directive:                         Val.                 (line   6)
+* value attribute, COFF:                 Val.                 (line   6)
+* value of a symbol:                     Symbol Value.        (line   6)
+* var directive, TIC54X:                 TIC54X-Directives.   (line 273)
+* VAX bitfields not supported:           VAX-no.              (line   6)
+* VAX branch improvement:                VAX-branch.          (line   6)
+* VAX command-line options ignored:      VAX-Opts.            (line   6)
+* VAX displacement sizing character:     VAX-operands.        (line  12)
+* VAX floating point:                    VAX-float.           (line   6)
+* VAX immediate character:               VAX-operands.        (line   6)
+* VAX indirect character:                VAX-operands.        (line   9)
+* VAX machine directives:                VAX-directives.      (line   6)
+* VAX opcode mnemonics:                  VAX-opcodes.         (line   6)
+* VAX operand notation:                  VAX-operands.        (line   6)
+* VAX register names:                    VAX-operands.        (line  17)
+* VAX support:                           Vax-Dependent.       (line   6)
+* Vax-11 C compatibility:                VAX-Opts.            (line  42)
+* VAX/VMS options:                       VAX-Opts.            (line  42)
+* version directive:                     Version.             (line   6)
+* version directive, TIC54X:             TIC54X-Directives.   (line 277)
+* version of assembler:                  v.                   (line   6)
+* versions of symbols:                   Symver.              (line   6)
+* visibility <1>:                        Protected.           (line   6)
+* visibility <2>:                        Internal.            (line   6)
+* visibility:                            Hidden.              (line   6)
+* VMS (VAX) options:                     VAX-Opts.            (line  42)
+* vtable_entry directive:                VTableEntry.         (line   6)
+* vtable_inherit directive:              VTableInherit.       (line   6)
+* warning directive:                     Warning.             (line   6)
+* warning for altered difference tables: K.                   (line   6)
+* warning messages:                      Errors.              (line   6)
+* warnings, causing error:               W.                   (line  16)
+* warnings, M32R:                        M32R-Warnings.       (line   6)
+* warnings, suppressing:                 W.                   (line  11)
+* warnings, switching on:                W.                   (line  19)
+* weak directive:                        Weak.                (line   6)
+* weakref directive:                     Weakref.             (line   6)
+* whitespace:                            Whitespace.          (line   6)
+* whitespace, removed by preprocessor:   Preprocessing.       (line   7)
+* wide floating point directives, VAX:   VAX-directives.      (line  10)
+* width directive, TIC54X:               TIC54X-Directives.   (line 127)
+* Width of continuation lines of disassembly output: listing. (line  20)
+* Width of first line disassembly output: listing.            (line  15)
+* Width of source line output:           listing.             (line  27)
+* wmsg directive, TIC54X:                TIC54X-Directives.   (line  77)
+* word directive:                        Word.                (line   6)
+* word directive, ARC:                   ARC Directives.      (line 174)
+* word directive, H8/300:                H8/300 Directives.   (line   6)
+* word directive, i386:                  i386-Float.          (line  21)
+* word directive, SPARC:                 Sparc-Directives.    (line  51)
+* word directive, TIC54X:                TIC54X-Directives.   (line 111)
+* word directive, x86-64:                i386-Float.          (line  21)
+* writing patterns in memory:            Fill.                (line   6)
+* wval:                                  Z8000 Directives.    (line  24)
+* x86-64 arch directive:                 i386-Arch.           (line   6)
+* x86-64 att_syntax pseudo op:           i386-Syntax.         (line   6)
+* x86-64 conversion instructions:        i386-Mnemonics.      (line  32)
+* x86-64 floating point:                 i386-Float.          (line   6)
+* x86-64 immediate operands:             i386-Syntax.         (line  15)
+* x86-64 instruction naming:             i386-Mnemonics.      (line   6)
+* x86-64 intel_syntax pseudo op:         i386-Syntax.         (line   6)
+* x86-64 jump optimization:              i386-Jumps.          (line   6)
+* x86-64 jump, call, return:             i386-Syntax.         (line  38)
+* x86-64 jump/call operands:             i386-Syntax.         (line  15)
+* x86-64 memory references:              i386-Memory.         (line   6)
+* x86-64 options:                        i386-Options.        (line   6)
+* x86-64 register operands:              i386-Syntax.         (line  15)
+* x86-64 registers:                      i386-Regs.           (line   6)
+* x86-64 sections:                       i386-Syntax.         (line  44)
+* x86-64 size suffixes:                  i386-Syntax.         (line  29)
+* x86-64 source, destination operands:   i386-Syntax.         (line  22)
+* x86-64 support:                        i386-Dependent.      (line   6)
+* x86-64 syntax compatibility:           i386-Syntax.         (line   6)
+* xfloat directive, TIC54X:              TIC54X-Directives.   (line  64)
+* xlong directive, TIC54X:               TIC54X-Directives.   (line 135)
+* Xtensa architecture:                   Xtensa-Dependent.    (line   6)
+* Xtensa assembler syntax:               Xtensa Syntax.       (line   6)
+* Xtensa directives:                     Xtensa Directives.   (line   6)
+* Xtensa opcode names:                   Xtensa Opcodes.      (line   6)
+* Xtensa register names:                 Xtensa Registers.    (line   6)
+* xword directive, SPARC:                Sparc-Directives.    (line  55)
+* Z80 $:                                 Z80-Chars.           (line   8)
+* Z80 ':                                 Z80-Chars.           (line  13)
+* Z80 floating point:                    Z80 Floating Point.  (line   6)
+* Z80 line comment character:            Z80-Chars.           (line   6)
+* Z80 options:                           Z80 Options.         (line   6)
+* Z80 registers:                         Z80-Regs.            (line   6)
+* Z80 support:                           Z80-Dependent.       (line   6)
+* Z80 Syntax:                            Z80 Options.         (line  47)
+* Z80, \:                                Z80-Chars.           (line  11)
+* Z80, case sensitivity:                 Z80-Case.            (line   6)
+* Z80-only directives:                   Z80 Directives.      (line   9)
+* Z800 addressing modes:                 Z8000-Addressing.    (line   6)
+* Z8000 directives:                      Z8000 Directives.    (line   6)
+* Z8000 line comment character:          Z8000-Chars.         (line   6)
+* Z8000 line separator:                  Z8000-Chars.         (line   8)
+* Z8000 opcode summary:                  Z8000 Opcodes.       (line   6)
+* Z8000 options:                         Z8000 Options.       (line   6)
+* Z8000 registers:                       Z8000-Regs.          (line   6)
+* Z8000 support:                         Z8000-Dependent.     (line   6)
+* zdaoff pseudo-op, V850:                V850 Opcodes.        (line  99)
+* zero register, V850:                   V850-Regs.           (line   7)
+* zero-terminated strings:               Asciz.               (line   6)
+
+
+
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+Node: PDP-11-Synthetic430508
+Node: PJ-Dependent430726
+Node: PJ Options430951
+Node: PPC-Dependent431228
+Node: PowerPC-Opts431515
+Node: PowerPC-Pseudo433590
+Node: SH-Dependent434189
+Node: SH Options434601
+Node: SH Syntax435529
+Node: SH-Chars435802
+Node: SH-Regs436096
+Node: SH-Addressing436710
+Node: SH Floating Point437619
+Node: SH Directives438713
+Node: SH Opcodes439083
+Node: SH64-Dependent443405
+Node: SH64 Options443768
+Node: SH64 Syntax445485
+Node: SH64-Chars445768
+Node: SH64-Regs446068
+Node: SH64-Addressing447164
+Node: SH64 Directives448347
+Node: SH64 Opcodes449457
+Node: Sparc-Dependent450173
+Node: Sparc-Opts450558
+Node: Sparc-Aligned-Data452815
+Node: Sparc-Float453670
+Node: Sparc-Directives453871
+Node: TIC54X-Dependent455831
+Node: TIC54X-Opts456557
+Node: TIC54X-Block457600
+Node: TIC54X-Env457960
+Node: TIC54X-Constants458308
+Node: TIC54X-Subsyms458710
+Node: TIC54X-Locals460619
+Node: TIC54X-Builtins461363
+Node: TIC54X-Ext463834
+Node: TIC54X-Directives464405
+Node: TIC54X-Macros475307
+Node: TIC54X-MMRegs477417
+Node: Z80-Dependent477633
+Node: Z80 Options478021
+Node: Z80 Syntax479444
+Node: Z80-Chars480116
+Node: Z80-Regs480649
+Node: Z80-Case481001
+Node: Z80 Floating Point481446
+Node: Z80 Directives481640
+Node: Z80 Opcodes483265
+Node: Z8000-Dependent484607
+Node: Z8000 Options485568
+Node: Z8000 Syntax485785
+Node: Z8000-Chars486075
+Node: Z8000-Regs486308
+Node: Z8000-Addressing487098
+Node: Z8000 Directives488215
+Node: Z8000 Opcodes489824
+Node: Vax-Dependent499766
+Node: VAX-Opts500283
+Node: VAX-float504018
+Node: VAX-directives504650
+Node: VAX-opcodes505511
+Node: VAX-branch505900
+Node: VAX-operands508407
+Node: VAX-no509170
+Node: V850-Dependent509407
+Node: V850 Options509805
+Node: V850 Syntax512194
+Node: V850-Chars512434
+Node: V850-Regs512599
+Node: V850 Floating Point514167
+Node: V850 Directives514373
+Node: V850 Opcodes515516
+Node: Xtensa-Dependent521408
+Node: Xtensa Options522137
+Node: Xtensa Syntax524908
+Node: Xtensa Opcodes526797
+Node: Xtensa Registers528591
+Node: Xtensa Optimizations529224
+Node: Density Instructions529676
+Node: Xtensa Automatic Alignment530778
+Node: Xtensa Relaxation533524
+Node: Xtensa Branch Relaxation534432
+Node: Xtensa Call Relaxation535804
+Node: Xtensa Immediate Relaxation537590
+Node: Xtensa Directives540164
+Node: Schedule Directive541872
+Node: Longcalls Directive542212
+Node: Transform Directive542756
+Node: Literal Directive543498
+Node: Literal Position Directive545283
+Node: Literal Prefix Directive546982
+Node: Absolute Literals Directive549145
+Node: Reporting Bugs550452
+Node: Bug Criteria551176
+Node: Bug Reporting551941
+Node: Acknowledgements558574
+Ref: Acknowledgements-Footnote-1563472
+Node: GNU Free Documentation License563498
+Node: Index583225
+
+End Tag Table
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index d9d23dff59f4..6daaed028c7b 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -1,6 +1,6 @@
 \input texinfo @c                               -*-Texinfo-*-
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003, 2004
+@c  2001, 2002, 2003, 2004, 2005
 @c  Free Software Foundation, Inc.
 @c UPDATE!!  On future updates--
 @c   (1)   check for new machine-dep cmdline options in
@@ -45,9 +45,6 @@
 @ifset H8/300
 @set H8
 @end ifset
-@ifset H8/500
-@set H8
-@end ifset
 @ifset SH
 @set H8
 @end ifset
@@ -226,21 +223,20 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @c to be limited to one line for the header.
 @smallexample
 @c man begin SYNOPSIS
-@value{AS} [@b{-a}[@b{cdhlns}][=@var{file}]] [@b{-D}] [@b{--defsym} @var{sym}=@var{val}]
- [@b{-f}] [@b{--gstabs}] [@b{--gstabs+}] [@b{--gdwarf2}] [@b{--help}]
- [@b{-I} @var{dir}] [@b{-J}] [@b{-K}] [@b{-L}]
- [@b{--listing-lhs-width}=@var{NUM}] [@b{--listing-lhs-width2}=@var{NUM}]
- [@b{--listing-rhs-width}=@var{NUM}] [@b{--listing-cont-lines}=@var{NUM}]
- [@b{--keep-locals}] [@b{-o} @var{objfile}] [@b{-R}] [@b{--statistics}] [@b{-v}]
- [@b{-version}] [@b{--version}] [@b{-W}] [@b{--warn}] [@b{--fatal-warnings}] 
- [@b{-w}] [@b{-x}] [@b{-Z}] [@b{--target-help}] [@var{target-options}] 
+@value{AS} [@b{-a}[@b{cdhlns}][=@var{file}]] [@b{--alternate}] [@b{-D}]
+ [@b{--defsym} @var{sym}=@var{val}] [@b{-f}] [@b{-g}] [@b{--gstabs}]
+ [@b{--gstabs+}] [@b{--gdwarf-2}] [@b{--help}] [@b{-I} @var{dir}] [@b{-J}]
+ [@b{-K}] [@b{-L}] [@b{--listing-lhs-width}=@var{NUM}]
+ [@b{--listing-lhs-width2}=@var{NUM}] [@b{--listing-rhs-width}=@var{NUM}]
+ [@b{--listing-cont-lines}=@var{NUM}] [@b{--keep-locals}] [@b{-o}
+ @var{objfile}] [@b{-R}] [@b{--reduce-memory-overheads}] [@b{--statistics}]
+ [@b{-v}] [@b{-version}] [@b{--version}] [@b{-W}] [@b{--warn}]
+ [@b{--fatal-warnings}] [@b{-w}] [@b{-x}] [@b{-Z}] [@b{@@@var{FILE}}]
+ [@b{--target-help}] [@var{target-options}]
  [@b{--}|@var{files} @dots{}]
 @c
 @c Target dependent options are listed below.  Keep the list sorted.
 @c Add an empty line for separation. 
-@ifset A29K
-@c am29k has no machine-dependent assembler options
-@end ifset
 @ifset ALPHA
 
 @emph{Target Alpha options:}
@@ -263,11 +259,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-march}=@var{architecture}[+@var{extension}@dots{}]]
    [@b{-mfpu}=@var{floating-point-format}]
    [@b{-mfloat-abi}=@var{abi}]
+   [@b{-meabi}=@var{ver}]
    [@b{-mthumb}]
    [@b{-EB}|@b{-EL}]
    [@b{-mapcs-32}|@b{-mapcs-26}|@b{-mapcs-float}|
     @b{-mapcs-reentrant}]
-   [@b{-mthumb-interwork}] [@b{-moabi}] [@b{-k}]
+   [@b{-mthumb-interwork}] [@b{-k}]
 @end ifset
 @ifset CRIS
 
@@ -275,6 +272,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{--underscore} | @b{--no-underscore}]
    [@b{--pic}] [@b{-N}]
    [@b{--emulation=criself} | @b{--emulation=crisaout}]
+   [@b{--march=v0_v10} | @b{--march=v10} | @b{--march=v32} | @b{--march=common_v10_v32}]
 @c Deprecated -- deliberately not documented.
 @c [@b{-h}] [@b{-H}]
 @end ifset
@@ -313,6 +311,9 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mconstant-gp}|@b{-mauto-pic}]
    [@b{-milp32}|@b{-milp64}|@b{-mlp64}|@b{-mp64}]
    [@b{-mle}|@b{mbe}]
+   [@b{-mtune=itanium1}|@b{-mtune=itanium2}]
+   [@b{-munwind-check=warning}|@b{-munwind-check=error}]
+   [@b{-mhint.b=ok}|@b{-mhint.b=warning}|@b{-mhint.b=error}]
    [@b{-x}|@b{-xexplicit}] [@b{-xauto}] [@b{-xdebug}]
 @end ifset
 @ifset IP2K
@@ -320,6 +321,11 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @emph{Target IP2K options:}
    [@b{-mip2022}|@b{-mip2022ext}]
 @end ifset
+@ifset M32C
+
+@emph{Target M32C options:}
+   [@b{-m32c}|@b{-m16c}]
+@end ifset
 @ifset M32R
 
 @emph{Target M32R options:}
@@ -352,7 +358,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @emph{Target MIPS options:}
    [@b{-nocpp}] [@b{-EL}] [@b{-EB}] [@b{-O}[@var{optimization level}]]
    [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}]
-   [@b{-non_shared}] [@b{-xgot}] [@b{--membedded-pic}]
+   [@b{-non_shared}] [@b{-xgot}]
    [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}]
    [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}]
    [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}]
@@ -363,6 +369,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mips16}] [@b{-no-mips16}]
    [@b{-mips3d}] [@b{-no-mips3d}]
    [@b{-mdmx}] [@b{-no-mdmx}]
+   [@b{-mdsp}] [@b{-mno-dsp}]
+   [@b{-mmt}] [@b{-mno-mt}]
    [@b{-mdebug}] [@b{-no-mdebug}]
    [@b{-mpdr}] [@b{-mno-pdr}]
 @end ifset
@@ -413,15 +421,29 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
  [@b{-mcpu=54[123589]}|@b{-mcpu=54[56]lp}] [@b{-mfar-mode}|@b{-mf}] 
  [@b{-merrors-to-file} @var{<filename>}|@b{-me} @var{<filename>}]
 @end ifset
+
+@ifset Z80
+
+@emph{Target Z80 options:}
+  [@b{-z80}] [@b{-r800}]
+  [@b{ -ignore-undocumented-instructions}] [@b{-Wnud}]
+  [@b{ -ignore-unportable-instructions}] [@b{-Wnup}]
+  [@b{ -warn-undocumented-instructions}] [@b{-Wud}]
+  [@b{ -warn-unportable-instructions}] [@b{-Wup}]
+  [@b{ -forbid-undocumented-instructions}] [@b{-Fud}]
+  [@b{ -forbid-unportable-instructions}] [@b{-Fup}]
+@end ifset
+
 @ifset Z8000
 @c Z8000 has no machine-dependent assembler options
 @end ifset
 @ifset XTENSA
 
 @emph{Target Xtensa options:}
- [@b{--[no-]density}] [@b{--[no-]relax}] [@b{--[no-]generics}]
- [@b{--[no-]text-section-literals}]
+ [@b{--[no-]text-section-literals}] [@b{--[no-]absolute-literals}]
  [@b{--[no-]target-align}] [@b{--[no-]longcalls}]
+ [@b{--[no-]transform}]
+ [@b{--rename-section} @var{oldname}=@var{newname}]
 @end ifset
 @c man end
 @end smallexample
@@ -429,6 +451,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
 @c man begin OPTIONS
 
 @table @gcctabopt
+@include at-file.texi
+
 @item -a[cdhlmns]
 Turn on listings, in any of a variety of ways:
 
@@ -462,6 +486,9 @@ You may combine these options; for example, use @samp{-aln} for assembly
 listing without forms processing.  The @samp{=file} option, if used, must be
 the last one.  By itself, @samp{-a} defaults to @samp{-ahls}.
 
+@item --alternate
+Begin in alternate macro mode, see @ref{Altmacro,,@code{.altmacro}}.
+
 @item -D
 Ignored.  This option is accepted for script compatibility with calls to
 other assemblers.
@@ -475,6 +502,12 @@ indicates a hexadecimal value, and a leading @samp{0} indicates an octal value.
 ``fast''---skip whitespace and comment preprocessing (assume source is
 compiler output).
 
+@item -g
+@itemx --gen-debug
+Generate debugging information for each assembler source line using whichever
+debug format is preferred by the target.  This currently means either STABS,
+ECOFF or DWARF2.
+
 @item --gstabs
 Generate stabs debugging information for each assembler line.  This
 may help debugging assembler code, if the debugger can handle it.
@@ -486,7 +519,7 @@ debuggers crash or refuse to read your program.  This
 may help debugging assembler code.  Currently the only GNU extension is
 the location of the current working directory at assembling time.
 
-@item --gdwarf2
+@item --gdwarf-2
 Generate DWARF2 debugging information for each assembler line.  This
 may help debugging assembler code, if the debugger can handle it.  Note---this
 option is only supported by some targets, not all of them.
@@ -539,6 +572,18 @@ Name the object-file output from @command{@value{AS}} @var{objfile}.
 @item -R
 Fold the data section into the text section.
 
+@kindex --hash-size=@var{number}
+Set the default size of GAS's hash tables to a prime number close to
+@var{number}.  Increasing this value can reduce the length of time it takes the
+assembler to perform its tasks, at the expense of increasing the assembler's
+memory requirements.  Similarly reducing this value can reduce the memory
+requirements at the expense of speed.
+
+@item --reduce-memory-overheads
+This option reduces GAS's memory requirements, at the expense of making the
+assembly processes slower.  Currently this switch is a synonym for
+@samp{--hash-size=4051}, but in the future it may have other effects as well.
+
 @item --statistics
 Print the maximum space (in bytes) and total time (in seconds) used by
 assembly.
@@ -604,7 +649,7 @@ Select which Floating Point architecture is the target.
 Select which floating point ABI is in use.
 @item -mthumb
 Enable Thumb only instruction decoding.
-@item -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant | -moabi
+@item -mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant
 Select which procedure calling convention is in use.
 @item -EB | -EL
 Select either big-endian (-EB) or little-endian (-EL) output.
@@ -684,6 +729,21 @@ just the basic IP2022 ones.
 @end table
 @end ifset
 
+@ifset M32C
+The following options are available when @value{AS} is configured for the
+Renesas M32C and M16C processors.
+
+@table @gcctabopt
+
+@item -m32c
+Assemble M32C instructions.
+
+@item -m16c
+Assemble M16C instructions (the default).
+
+@end table
+@end ifset
+
 @ifset M32R
 The following options are available when @value{AS} is configured for the
 Renesas M32R (formerly Mitsubishi M32R) series.
@@ -958,6 +1018,18 @@ Generate code for the MDMX Application Specific Extension.
 This tells the assembler to accept MDMX instructions.
 @samp{-no-mdmx} turns off this option.
 
+@item -mdsp
+@itemx -mno-dsp
+Generate code for the DSP Application Specific Extension.
+This tells the assembler to accept DSP instructions.
+@samp{-mno-dsp} turns off this option.
+
+@item -mmt
+@itemx -mno-mt
+Generate code for the MT Application Specific Extension.
+This tells the assembler to accept MT instructions.
+@samp{-mno-mt} turns off this option.
+
 @item --construct-floats
 @itemx --no-construct-floats
 The @samp{--no-construct-floats} option disables the construction of
@@ -1051,28 +1123,19 @@ The following options are available when @value{AS} is configured for
 an Xtensa processor.
 
 @table @gcctabopt
-@item --density | --no-density
-Enable or disable use of instructions from the Xtensa code density
-option.  This is enabled by default when the Xtensa processor supports
-the code density option.
-
-@item --relax | --no-relax
-Enable or disable instruction relaxation.  This is enabled by default.
-Note: In the current implementation, these options also control whether
-assembler optimizations are performed, making these options equivalent
-to @option{--generics} and @option{--no-generics}.
-
-@item --generics | --no-generics
-Enable or disable all assembler transformations of Xtensa instructions.
-The default is @option{--generics};
-@option{--no-generics} should be used only in the rare cases when the
-instructions must be exactly as specified in the assembly source.
-
 @item --text-section-literals | --no-text-section-literals
 With @option{--text-@-section-@-literals}, literal pools are interspersed
 in the text section.  The default is
 @option{--no-@-text-@-section-@-literals}, which places literals in a
-separate section in the output file.
+separate section in the output file.  These options only affect literals
+referenced via PC-relative @code{L32R} instructions; literals for
+absolute mode @code{L32R} instructions are handled separately.
+
+@item --absolute-literals | --no-absolute-literals
+Indicate to the assembler whether @code{L32R} instructions use absolute
+or PC-relative addressing.  The default is to assume absolute addressing
+if the Xtensa processor includes the absolute @code{L32R} addressing
+option.  Otherwise, only the PC-relative @code{L32R} mode can be used.
 
 @item --target-align | --no-target-align
 Enable or disable automatic alignment to reduce branch penalties at the
@@ -1082,6 +1145,41 @@ expense of some code density.  The default is @option{--target-@-align}.
 Enable or disable transformation of call instructions to allow calls
 across a greater range of addresses.  The default is
 @option{--no-@-longcalls}.
+
+@item --transform | --no-transform
+Enable or disable all assembler transformations of Xtensa instructions.
+The default is @option{--transform};
+@option{--no-transform} should be used only in the rare cases when the
+instructions must be exactly as specified in the assembly source.
+@end table
+@end ifset
+
+@ifset Z80
+The following options are available when @value{AS} is configured for
+a Z80 family processor.
+@table @gcctabopt
+@item -z80
+Assemble for Z80 processor.
+@item -r800
+Assemble for R800 processor.
+@item  -ignore-undocumented-instructions 
+@itemx -Wnud
+Assemble undocumented Z80 instructions that also work on R800 without warning.
+@item  -ignore-unportable-instructions 
+@itemx -Wnup
+Assemble all undocumented Z80 instructions without warning.
+@item  -warn-undocumented-instructions 
+@itemx -Wud
+Issue a warning for undocumented Z80 instructions that also work on R800.
+@item  -warn-unportable-instructions 
+@itemx -Wup
+Issue a warning for undocumented Z80 instructions that do notwork on R800.  
+@item  -forbid-undocumented-instructions 
+@itemx -Fud
+Treat all undocumented instructions as errors.
+@item  -forbid-unportable-instructions 
+@itemx -Fup
+Treat undocumented Z80 intructions that do notwork on R800 as errors.
 @end table
 @end ifset
 
@@ -1132,10 +1230,6 @@ For information on the H8/300 machine instruction set, see @cite{H8/300
 Series Programming Manual}.  For the H8/300H, see @cite{H8/300H Series
 Programming Manual} (Renesas).
 @end ifset
-@ifset H8/500
-For information on the H8/500 machine instruction set, see @cite{H8/500
-Series Programming Manual} (Renesas M21T001).
-@end ifset
 @ifset SH
 For information on the Renesas (formerly Hitachi) / SuperH SH machine instruction set,
 see @cite{SH-Microcomputer User's Manual} (Renesas) or
@@ -1225,10 +1319,6 @@ For the @value{TARGET} target, @command{@value{AS}} is configured to produce
 @value{OBJ-NAME} format object files.
 @end ifclear
 @c The following should exhaust all configs that set MULTI-OBJ, ideally
-@ifset A29K
-On the @value{TARGET}, @command{@value{AS}} can be configured to produce either
-@code{a.out} or COFF format object files.
-@end ifset
 @ifset I960
 On the @value{TARGET}, @command{@value{AS}} can be configured to produce either
 @code{b.out} or COFF format object files.
@@ -1395,14 +1485,6 @@ the current input file is used.  If a logical line number was given
 @ifset GENERIC
 (@pxref{Line,,@code{.line}})
 @end ifset
-@ifclear GENERIC
-@ifclear A29K
-(@pxref{Line,,@code{.line}})
-@end ifclear
-@ifset A29K
-(@pxref{Ln,,@code{.ln}})
-@end ifset
-@end ifclear
 then it is used to calculate the number printed,
 otherwise the actual line in the current source file is printed.  The
 message text is intended to be self explanatory (in the grand Unix
@@ -1456,6 +1538,7 @@ assembler.)
 
 @menu
 * a::             -a[cdhlns] enable listings
+* alternate::     --alternate enable alternate macro syntax
 * D::             -D for compatibility
 * f::             -f to work faster
 * I::             -I for .include search path
@@ -1528,6 +1611,12 @@ directives.  This is because the listing code buffers input source lines from
 stdin only after they have been preprocessed by the assembler.  This reduces
 memory usage and makes the code more efficient.
 
+@node alternate
+@section @option{--alternate}
+
+@kindex --alternate
+Begin in alternate macro mode, see @ref{Altmacro,,@code{.altmacro}}.
+
 @node D
 @section @option{-D}
 
@@ -2035,9 +2124,6 @@ This means you may not nest these comments.
 @cindex line comment character
 Anything from the @dfn{line comment} character to the next newline
 is considered a comment and is ignored.  The line comment character is
-@ifset A29K
-@samp{;} for the AMD 29K family;
-@end ifset
 @ifset ARC
 @samp{;} on the ARC;
 @end ifset
@@ -2047,9 +2133,6 @@ is considered a comment and is ignored.  The line comment character is
 @ifset H8/300
 @samp{;} for the H8/300 family;
 @end ifset
-@ifset H8/500
-@samp{!} for the H8/500 family;
-@end ifset
 @ifset HPPA
 @samp{;} for the HPPA;
 @end ifset
@@ -2077,6 +2160,9 @@ is considered a comment and is ignored.  The line comment character is
 @ifset IP2K
 @samp{#} on the ip2k;
 @end ifset
+@ifset M32C
+@samp{#} on the m32c;
+@end ifset
 @ifset M32R
 @samp{#} on the m32r;
 @end ifset
@@ -2086,12 +2172,12 @@ is considered a comment and is ignored.  The line comment character is
 @ifset M68HC11
 @samp{#} on the 68HC11 and 68HC12;
 @end ifset
-@ifset M880X0
-@samp{;} on the M880x0;
-@end ifset
 @ifset VAX
 @samp{#} on the Vax;
 @end ifset
+@ifset Z80
+@samp{;} for the Z80;
+@end ifset
 @ifset Z8000
 @samp{!} for the Z8000;
 @end ifset
@@ -2181,12 +2267,6 @@ the preceding statement.  Newlines and semicolons within character
 constants are an exception: they do not end statements.
 @end ifclear
 @ifset abnormal-separator
-@ifset A29K
-A @dfn{statement} ends at a newline character (@samp{\n}) or an ``at''
-sign (@samp{@@}).  The newline or at sign is considered part of the
-preceding statement.  Newlines and at signs within character constants
-are an exception: they do not end statements.
-@end ifset
 @ifset HPPA
 A @dfn{statement} ends at a newline character (@samp{\n}) or an exclamation 
 point (@samp{!}).  The newline or exclamation point is considered part of the
@@ -2195,9 +2275,7 @@ constants are an exception: they do not end statements.
 @end ifset
 @ifset H8
 A @dfn{statement} ends at a newline character (@samp{\n}); or (for the
-H8/300) a dollar sign (@samp{$}); or (for the
-Renesas-SH or the
-H8/500) a semicolon
+H8/300) a dollar sign (@samp{$}); or (for the Renesas-SH) a semicolon
 (@samp{;}).  The newline or separator character is considered part of
 the preceding statement.  Newlines and separators within character
 constants are an exception: they do not end statements.
@@ -2416,12 +2494,9 @@ grave accent.  A newline
 (or semicolon @samp{;})
 @end ifclear
 @ifset abnormal-separator
-@ifset A29K
-(or at sign @samp{@@})
-@end ifset
 @ifset H8
 (or dollar sign @samp{$}, for the H8/300; or semicolon @samp{;} for the
-Renesas SH or H8/500)
+Renesas SH)
 @end ifset
 @end ifset
 @end ifclear
@@ -2524,8 +2599,7 @@ A letter, to tell @command{@value{AS}} the rest of the number is a flonum.
 4.2 assembler seems to allow any of @samp{defghDEFGH}.)
 @end ignore
 
-On the H8/300, H8/500,
-Renesas / SuperH SH,
+On the H8/300, Renesas / SuperH SH,
 and AMD 29K architectures, the letter must be
 one of the letters @samp{DFPRSX} (in upper or lower case).
 
@@ -2538,9 +2612,6 @@ one of the letters @samp{DFT} (in upper or lower case).
 On the HPPA architecture, the letter must be @samp{E} (upper case only).
 @end ifset
 @ifclear GENERIC
-@ifset A29K
-One of the letters @samp{DFPRSX} (in upper or lower case).
-@end ifset
 @ifset ARC
 One of the letters @samp{DFRS} (in upper or lower case).
 @end ifset
@@ -2661,8 +2732,7 @@ run-time addresses to sections is called @dfn{relocation}.  It includes
 the task of adjusting mentions of object-file addresses so they refer to
 the proper run-time addresses.
 @ifset H8
-For the H8/300 and H8/500,
-and for the Renesas / SuperH SH,
+For the H8/300, and for the Renesas / SuperH SH,
 @command{@value{AS}} pads sections if needed to
 ensure they end on a word (sixteen bit) boundary.
 @end ifset
@@ -2954,7 +3024,7 @@ of @command{@value{AS}}.)
 @end ifset
 @ifclear GENERIC
 @ifset H8
-On the H8/300 and H8/500 platforms, each subsection is zero-padded to a word
+On the H8/300 platform, each subsection is zero-padded to a word
 boundary (two bytes).
 The same is true on the Renesas SH.
 @end ifset
@@ -2966,10 +3036,6 @@ The same is true on the Renesas SH.
 @c these paragraphs might need to vanish from this manual, and be
 @c discussed in BFD chapter of binutils (or some such).
 @end ifset
-@ifset A29K
-On the AMD 29K family, no particular padding is added to section or
-subsection sizes; @value{AS} forces no alignment on this platform.
-@end ifset
 @end ifclear
 
 Subsections appear in your object file in numeric order, lowest numbered
@@ -2982,9 +3048,9 @@ data subsections as a data section.
 To specify which subsection you want subsequent statements assembled
 into, use a numeric argument to specify it, in a @samp{.text
 @var{expression}} or a @samp{.data @var{expression}} statement.
-@ifset COFF-ELF
+@ifset COFF
 @ifset GENERIC
-When generating COFF or ELF output, you
+When generating COFF output, you
 @end ifset
 @ifclear GENERIC
 You
@@ -2993,6 +3059,16 @@ can also use an extra subsection
 argument with arbitrary named sections: @samp{.section @var{name},
 @var{expression}}.
 @end ifset
+@ifset ELF
+@ifset GENERIC
+When generating ELF output, you
+@end ifset
+@ifclear GENERIC
+You
+@end ifclear
+can also use the @code{.subsection} directive (@pxref{SubSection})
+to specify a subsection: @samp{.subsection @var{expression}}.
+@end ifset
 @var{Expression} should be an absolute expression.
 (@xref{Expressions}.)  If you just say @samp{.text} then @samp{.text 0}
 is assumed.  Likewise @samp{.data} means @samp{.data 0}.  Assembly
@@ -3091,7 +3167,9 @@ provides a special directive @code{.label} for defining labels more flexibly.
 A symbol can be given an arbitrary value by writing a symbol, followed
 by an equals sign @samp{=}, followed by an expression
 (@pxref{Expressions}).  This is equivalent to using the @code{.set}
-directive.  @xref{Set,,@code{.set}}.
+directive.  @xref{Set,,@code{.set}}.  In the same way, using a double
+equals sign @samp{=}@samp{=} here represents an equivalent of the
+@code{.eqv} directive.  @xref{Eqv,,@code{.eqv}}.
 
 @node Symbol Names
 @section Symbol Names
@@ -3105,15 +3183,10 @@ noted in @ref{Machine Dependencies}.  That character may be followed by any
 string of digits, letters, dollar signs (unless otherwise noted in
 @ref{Machine Dependencies}), and underscores.
 @end ifclear
-@ifset A29K
-For the AMD 29K family, @samp{?} is also allowed in the
-body of a symbol name, though not at its beginning.
-@end ifset
-
 @ifset SPECIAL-SYMS
 @ifset H8
 Symbol names begin with a letter or with one of @samp{._}.  On the
-Renesas SH or the H8/500, you can also use @code{$} in symbol names.  That
+Renesas SH you can also use @code{$} in symbol names.  That
 character may be followed by any string of digits, letters, dollar signs (save
 on the H8/300), and underscores.
 @end ifset
@@ -3235,11 +3308,6 @@ directive.  Thus, the expression @samp{.=.+4} is the same as saying
 @ifclear no-space-dir
 @samp{.space 4}.
 @end ifclear
-@ifset no-space-dir
-@ifset A29K
-@samp{.block 4}.
-@end ifset
-@end ifset
 
 @node Symbol Attributes
 @section Symbol Attributes
@@ -3389,8 +3457,8 @@ respectively, with @code{.val} and @code{.type}.
 
 @cindex auxiliary attributes, COFF symbols
 The @command{@value{AS}} directives @code{.dim}, @code{.line}, @code{.scl},
-@code{.size}, and @code{.tag} can generate auxiliary symbol table
-information for COFF.
+@code{.size}, @code{.tag}, and @code{.weak} can generate auxiliary symbol
+table information for COFF.
 @end ifset
 
 @ifset SOM
@@ -3549,12 +3617,10 @@ Highest Precedence
 @item %
 @dfn{Remainder}.
 
-@item <
-@itemx <<
+@item <<
 @dfn{Shift Left}.  Same as the C operator @samp{<<}.
 
-@item >
-@itemx >>
+@item >>
 @dfn{Shift Right}.  Same as the C operator @samp{>>}.
 @end table
 
@@ -3603,14 +3669,15 @@ You may not subtract arguments from different sections.
 @item  ==
 @dfn{Is Equal To}
 @item <>
+@itemx !=
 @dfn{Is Not Equal To}
 @item <
 @dfn{Is Less Than}
-@itemx >
+@item >
 @dfn{Is Greater Than}
-@itemx >=
+@item >=
 @dfn{Is Greater Than Or Equal To}
-@itemx <=
+@item <=
 @dfn{Is Less Than Or Equal To}
 
 The comparison operators can be used as infix operators.  A true results has a
@@ -3666,6 +3733,7 @@ Some machine configurations provide additional directives.
 @end ifset
 
 * Align::                       @code{.align @var{abs-expr} , @var{abs-expr}}
+* Altmacro::                    @code{.altmacro}
 * Ascii::                       @code{.ascii "@var{string}"}@dots{}
 * Asciz::                       @code{.asciz "@var{string}"}@dots{}
 * Balign::                      @code{.balign @var{abs-expr} , @var{abs-expr}}
@@ -3698,7 +3766,9 @@ Some machine configurations provide additional directives.
 * Endif::                       @code{.endif}
 * Equ::                         @code{.equ @var{symbol}, @var{expression}}
 * Equiv::                       @code{.equiv @var{symbol}, @var{expression}}
+* Eqv::                         @code{.eqv @var{symbol}, @var{expression}}
 * Err::				@code{.err}
+* Error::			@code{.error @var{string}}
 * Exitm::			@code{.exitm}
 * Extern::                      @code{.extern}
 * Fail::			@code{.fail}
@@ -3732,9 +3802,12 @@ Some machine configurations provide additional directives.
 * Line::                        @code{.line @var{line-number}}
 @end ifclear
 
-* Ln::                          @code{.ln @var{line-number}}
 * Linkonce::			@code{.linkonce [@var{type}]}
 * List::                        @code{.list}
+* Ln::                          @code{.ln @var{line-number}}
+
+* LNS directives::              @code{.file}, @code{.loc}, etc.
+
 * Long::                        @code{.long @var{expressions}}
 @ignore
 * Lsym::                        @code{.lsym @var{symbol}, @var{expression}}
@@ -3742,6 +3815,7 @@ Some machine configurations provide additional directives.
 
 * Macro::			@code{.macro @var{name} @var{args}}@dots{}
 * MRI::				@code{.mri @var{val}}
+* Noaltmacro::                  @code{.noaltmacro}
 * Nolist::                      @code{.nolist}
 * Octa::                        @code{.octa @var{bignums}}
 * Org::                         @code{.org @var{new-lc} , @var{fill}}
@@ -3812,9 +3886,11 @@ Some machine configurations provide additional directives.
 * Version::                     @code{.version "@var{string}"}
 * VTableEntry::                 @code{.vtable_entry @var{table}, @var{offset}}
 * VTableInherit::               @code{.vtable_inherit @var{child}, @var{parent}}
-* Weak::                        @code{.weak @var{names}}
 @end ifset
 
+* Warning::			@code{.warning @var{string}}
+* Weak::                        @code{.weak @var{names}}
+* Weakref::                     @code{.weakref @var{alias}, @var{symbol}}
 * Word::                        @code{.word @var{expressions}}
 * Deprecated::                  Deprecated Directives
 @end menu
@@ -3868,7 +3944,7 @@ required alignment; this can be useful if you want the alignment to be filled
 with no-op instructions when appropriate.
 
 The way the required alignment is specified varies from system to system.
-For the a29k, arc, hppa, i386 using ELF, i860, iq2000, m68k, m88k, or32,
+For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32,
 s390, sparc, tic4x, tic80 and xtensa, the first expression is the
 alignment request in bytes.  For example @samp{.align 8} advances
 the location counter until it is a multiple of 8.  If the location counter
@@ -4026,6 +4102,9 @@ using the known displacement of the CFA register from the CFA.
 This is often easier to use, because the number will match the
 code it's annotating.
 
+@section @code{.cfi_signal_frame}
+Mark current function as signal trampoline.
+
 @section @code{.cfi_window_save}
 SPARC register window has been saved.
 
@@ -4034,6 +4113,61 @@ Allows the user to add arbitrary bytes to the unwind info.  One
 might use this to add OS-specific CFI opcodes, or generic CFI
 opcodes that GAS does not yet support.
 
+@node LNS directives
+@section @code{.file @var{fileno} @var{filename}}
+@cindex @code{file} directive
+When emitting dwarf2 line number information @code{.file} assigns filenames
+to the @code{.debug_line} file name table.  The @var{fileno} operand should
+be a unique positive integer to use as the index of the entry in the table.
+The @var{filename} operand is a C string literal.
+
+The detail of filename indicies is exposed to the user because the filename
+table is shared with the @code{.debug_info} section of the dwarf2 debugging
+information, and thus the user must know the exact indicies that table
+entries will have.
+
+@section @code{.loc @var{fileno} @var{lineno} [@var{column}] [@var{options}]}
+@cindex @code{loc} directive
+The @code{.loc} directive will add row to the @code{.debug_line} line
+number matrix corresponding to the immediately following assembly
+instruction.  The @var{fileno}, @var{lineno}, and optional @var{column}
+arguments will be applied to the @code{.debug_line} state machine before
+the row is added.
+
+The @var{options} are a sequence of the following tokens in any order:
+
+@table @code
+@item basic_block
+This option will set the @code{basic_block} register in the
+@code{.debug_line} state machine to @code{true}.
+
+@item prologue_end
+This option will set the @code{prologue_end} register in the
+@code{.debug_line} state machine to @code{true}.
+
+@item epilogue_begin
+This option will set the @code{epilogue_begin} register in the
+@code{.debug_line} state machine to @code{true}.
+
+@item is_stmt @var{value}
+This option will set the @code{is_stmt} register in the
+@code{.debug_line} state machine to @code{value}, which must be 
+either 0 or 1.
+
+@item isa @var{value}
+This directive will set the @code{isa} register in the @code{.debug_line}
+state machine to @var{value}, which must be an unsigned integer.
+
+@end table
+
+@section @code{.loc_mark_blocks @var{enable}}
+@cindex @code{loc_mark_blocks} directive
+The @code{.loc_mark_blocks} directive makes the assembler emit an entry
+to the @code{.debug_line} line number matrix with the @code{basic_block}
+register in the state machine set whenever a code label is seen.
+The @var{enable} argument should be either 1 or 0, to enable or disable
+this function respectively.
+
 @node Data
 @section @code{.data @var{subsection}}
 
@@ -4189,6 +4323,14 @@ The syntax for @code{equ} on the HPPA is
 @samp{@var{symbol} .equ @var{expression}}.
 @end ifset
 
+@ifset Z80
+The syntax for @code{equ} on the Z80 is 
+@samp{@var{symbol} equ @var{expression}}. 
+On the Z80 it is an eror if @var{symbol} is already defined,
+but the symbol is not protected from later redefinition, 
+compare @xref{Equiv}.
+@end ifset
+
 @node Equiv
 @section @code{.equiv @var{symbol}, @var{expression}}
 @cindex @code{equiv} directive
@@ -4204,13 +4346,35 @@ Except for the contents of the error message, this is roughly equivalent to
 .endif
 .equ SYM,VAL
 @end smallexample
+plus it protects the symbol from later redefinition.
+
+@node Eqv
+@section @code{.eqv @var{symbol}, @var{expression}}
+@cindex @code{eqv} directive
+The @code{.eqv} directive is like @code{.equiv}, but no attempt is made to
+evaluate the expression or any part of it immediately.  Instead each time
+the resulting symbol is used in an expression, a snapshot of its current
+value is taken.
 
 @node Err
 @section @code{.err}
 @cindex @code{err} directive
 If @command{@value{AS}} assembles a @code{.err} directive, it will print an error
 message and, unless the @option{-Z} option was used, it will not generate an
-object file.  This can be used to signal error an conditionally compiled code.
+object file.  This can be used to signal an error in conditionally compiled code.
+
+@node Error
+@section @code{.error "@var{string}"}
+@cindex error directive
+
+Similarly to @code{.err}, this directive emits an error, but you can specify a
+string that will be emitted as the error message.  If you don't specify the
+message, it defaults to @code{".error directive invoked in source file"}.
+@xref{Errors, ,Error and Warning Messages}.
+
+@smallexample
+ .error "This code has not been assembled and tested."
+@end smallexample
 
 @node Exitm
 @section @code{.exitm}
@@ -4247,10 +4411,6 @@ recognized whether or not it is surrounded by quotes @samp{"}; but if you wish
 to specify an empty file name, you must give the quotes--@code{""}.  This
 statement may go away in future: it is only recognized to be compatible with
 old @command{@value{AS}} programs.
-@ifset A29K
-In some configurations of @command{@value{AS}}, @code{.file} has already been
-removed to avoid conflicts with other assemblers.  @xref{Machine Dependencies}.
-@end ifset
 @end ifclear
 
 @node Fill
@@ -4333,7 +4493,7 @@ partial programs.  You may need the HPPA-only @code{.EXPORT} directive as well.
 
 @cindex @code{hidden} directive
 @cindex visibility
-This one of the ELF visibility directives.  The other two are
+This is one of the ELF visibility directives.  The other two are
 @code{.internal} (@pxref{Internal,,@code{.internal}}) and 
 @code{.protected} (@pxref{Protected,,@code{.protected}}).
 
@@ -4370,10 +4530,14 @@ This directive is a synonym for both @samp{.short} and @samp{.word}.
 @section @code{.ident}
 
 @cindex @code{ident} directive
-This directive is used by some assemblers to place tags in object files.
-@command{@value{AS}} simply accepts the directive for source-file
-compatibility with such assemblers, but does not actually emit anything
-for it.
+
+This directive is used by some assemblers to place tags in object files.  The
+behavior of this directive varies depending on the target.  When using the
+a.out object file format, @command{@value{AS}} simply accepts the directive for
+source-file compatibility with existing assemblers, but does not emit anything
+for it.  When using COFF, comments are emitted to the @code{.comment} or
+@code{.rdata} section, depending on the target.  When using ELF, comments are
+emitted to the @code{.comment} section.
 
 @node If
 @section @code{.if @var{absolute expression}}
@@ -4397,6 +4561,10 @@ Assembles the following section of code if the specified @var{symbol}
 has been defined.  Note a symbol which has been referenced but not yet defined
 is considered to be undefined.
 
+@cindex @code{ifb} directive
+@item .ifb @var{text}
+Assembles the following section of code if the operand is blank (empty).
+
 @cindex @code{ifc} directive
 @item .ifc @var{string1},@var{string2}
 Assembles the following section of code if the two strings are the same.  The
@@ -4431,6 +4599,11 @@ to zero.
 @item .iflt @var{absolute expression}
 Assembles the following section of code if the argument is less than zero.
 
+@cindex @code{ifnb} directive
+@item .ifnb @var{text}
+Like @code{.ifb}, but the sense of the test is reversed: this assembles the
+following section of code if the operand is non-blank (non-empty).
+
 @cindex @code{ifnc} directive
 @item .ifnc @var{string1},@var{string2}.
 Like @code{.ifc}, but the sense of the test is reversed: this assembles the
@@ -4497,7 +4670,7 @@ of target the assembly is for.
 
 @ifclear GENERIC
 @ifset H8
-On the H8/500 and most forms of the H8/300, @code{.int} emits 16-bit
+On most forms of the H8/300, @code{.int} emits 16-bit
 integers.  On the H8/300H and the Renesas SH, however, @code{.int} emits
 32-bit integers.
 @end ifset
@@ -4509,7 +4682,7 @@ integers.  On the H8/300H and the Renesas SH, however, @code{.int} emits
 
 @cindex @code{internal} directive
 @cindex visibility
-This one of the ELF visibility directives.  The other two are
+This is one of the ELF visibility directives.  The other two are
 @code{.hidden} (@pxref{Hidden,,@code{.hidden}}) and 
 @code{.protected} (@pxref{Protected,,@code{.protected}}).
 
@@ -4548,6 +4721,9 @@ is equivalent to assembling
         move    d3,sp@@-
 @end example
 
+For some caveats with the spelling of @var{symbol}, see also the discussion
+at @xref{Macro}.
+
 @node Irpc
 @section @code{.irpc @var{symbol},@var{values}}@dots{}
 
@@ -4576,6 +4752,9 @@ is equivalent to assembling
         move    d3,sp@@-
 @end example
 
+For some caveats with the spelling of @var{symbol}, see also the discussion
+at @xref{Macro}.
+
 @node Lcomm
 @section @code{.lcomm @var{symbol} , @var{length}}
 
@@ -4627,12 +4806,6 @@ reported as on logical line number @var{line-number} @minus{} 1.  One day
 @command{@value{AS}} will no longer support this directive: it is recognized only
 for compatibility with existing assembler programs.
 
-@ifset GENERIC
-@ifset A29K
-@emph{Warning:} In the AMD29K configuration of @value{AS}, this command is
-not available; use the synonym @code{.ln} in that context.
-@end ifset
-@end ifset
 @end ifset
 
 @ifclear no-line-dir
@@ -4792,9 +4965,14 @@ With that definition, @samp{SUM 0,5} is equivalent to this assembly input:
 @cindex @code{macro} directive
 Begin the definition of a macro called @var{macname}.  If your macro
 definition requires arguments, specify their names after the macro name,
-separated by commas or spaces.  You can supply a default value for any
-macro argument by following the name with @samp{=@var{deflt}}.  For
-example, these are all valid @code{.macro} statements:
+separated by commas or spaces.  You can qualify the macro argument to
+indicate whether all invocations must specify a non-blank value (through
+@samp{:@code{req}}), or whether it takes all of the remaining arguments
+(through @samp{:@code{vararg}}).  You can supply a default value for any
+macro argument by following the name with @samp{=@var{deflt}}.  You
+cannot define two macros with the same @var{macname} unless it has been
+subject to the @code{.purgem} directive (@xref{Purgem}.) between the two
+definitions.  For example, these are all valid @code{.macro} statements:
 
 @table @code
 @item .macro comm
@@ -4817,10 +4995,42 @@ After the definition is complete, you can call the macro either as
 @samp{0}, and @samp{\p2} evaluating to @var{b}).
 @end table
 
+@item .macro m p1:req, p2=0, p3:vararg
+Begin the definition of a macro called @code{m}, with at least three
+arguments.  The first argument must always have a value specified, but
+not the second, which instead has a default value. The third formal
+will get assigned all remaining arguments specified at invocation time.
+
 When you call a macro, you can specify the argument values either by
 position, or by keyword.  For example, @samp{sum 9,17} is equivalent to
 @samp{sum to=17, from=9}.
 
+Note that since each of the @var{macargs} can be an identifier exactly
+as any other one permitted by the target architecture, there may be
+occasional problems if the target hand-crafts special meanings to certain
+characters when they occur in a special position.  For example, if colon
+(@code{:}) is generally permitted to be part of a symbol name, but the
+architecture specific code special-cases it when occuring as the final
+character of a symbol (to denote a label), then the macro parameter
+replacement code will have no way of knowing that and consider the whole
+construct (including the colon) an identifier, and check only this
+identifier for being the subject to parameter substitution.  In this
+example, besides the potential of just separating identifier and colon
+by white space, using alternate macro syntax (@xref{Altmacro}.) and
+ampersand (@code{&}) as the character to separate literal text from macro
+parameters (or macro parameters from one another) would provide a way to
+achieve the same effect:
+
+@example
+	.altmacro
+	.macro label l
+l&:
+	.endm
+@end example
+
+This applies identically to the identifiers used in @code{.irp} (@xref{Irp}.)
+and @code{.irpc} (@xref{Irpc}.).
+
 @item .endm
 @cindex @code{endm} directive
 Mark the end of a macro definition.
@@ -4836,20 +5046,52 @@ Exit early from the current macro definition.
 executed in this pseudo-variable; you can copy that number to your
 output with @samp{\@@}, but @emph{only within a macro definition}.
 
-@ignore
 @item LOCAL @var{name} [ , @dots{} ]
 @emph{Warning: @code{LOCAL} is only available if you select ``alternate
-macro syntax'' with @samp{-a} or @samp{--alternate}.}  @xref{Alternate,,
-Alternate macro syntax}.
+macro syntax'' with @samp{--alternate} or @code{.altmacro}.}
+@xref{Altmacro,,@code{.altmacro}}.
+@end ftable
 
-Generate a string replacement for each of the @var{name} arguments, and
+@node Altmacro
+@section @code{.altmacro}
+Enable alternate macro mode, enabling:
+
+@ftable @code
+@item LOCAL @var{name} [ , @dots{} ]
+One additional directive, @code{LOCAL}, is available.  It is used to
+generate a string replacement for each of the @var{name} arguments, and
 replace any instances of @var{name} in each macro expansion.  The
 replacement string is unique in the assembly, and different for each
 separate macro expansion.  @code{LOCAL} allows you to write macros that
 define symbols, without fear of conflict between separate macro expansions.
-@end ignore
+
+@item String delimiters
+You can write strings delimited in these other ways besides
+@code{"@var{string}"}:
+
+@table @code
+@item '@var{string}'
+You can delimit strings with single-quote charaters.
+
+@item <@var{string}>
+You can delimit strings with matching angle brackets.
+@end table
+
+@item single-character string escape
+To include any single character literally in a string (even if the
+character would otherwise have some special meaning), you can prefix the
+character with @samp{!} (an exclamation mark).  For example, you can
+write @samp{<4.3 !> 5.4!!>} to get the literal text @samp{4.3 > 5.4!}.
+
+@item Expression results as strings
+You can write @samp{%@var{expr}} to evaluate the expression @var{expr}
+and use the result as a string.  
 @end ftable
 
+@node Noaltmacro
+@section @code{.noaltmacro}
+Disable alternate macro mode.  @ref{Altmacro}
+
 @node Nolist
 @section @code{.nolist}
 
@@ -4996,7 +5238,7 @@ assembly.  You must put @var{string} in double quotes.
 
 @cindex @code{protected} directive
 @cindex visibility
-This one of the ELF visibility directives.  The other two are
+This is one of the ELF visibility directives.  The other two are
 @code{.hidden} (@pxref{Hidden}) and @code{.internal} (@pxref{Internal}).
 
 This directive overrides the named symbols default visibility (which is set by
@@ -5045,9 +5287,9 @@ This is one of the ELF section stack manipulation directives.  The others are
 @code{.popsection} (@pxref{PopSection}), and @code{.previous} 
 (@pxref{Previous}).
 
-This directive is a synonym for @code{.section}.  It pushes the current section
-(and subsection) onto the top of the section stack, and then replaces the
-current section and subsection with @code{name} and @code{subsection}.
+This directive pushes the current section (and subsection) onto the
+top of the section stack, and then replaces the current section and
+subsection with @code{name} and @code{subsection}.
 @end ifset
 
 @node Quad
@@ -5200,7 +5442,7 @@ This is one of the ELF section stack manipulation directives.  The others are
 For ELF targets, the @code{.section} directive is used like this:
 
 @smallexample
-.section @var{name} [, "@var{flags}"[, @@@var{type}[, @@@var{entsize}]]]
+.section @var{name} [, "@var{flags}"[, @@@var{type}[,@var{flag_specific_arguments}]]]
 @end smallexample
 
 The optional @var{flags} argument is a quoted string which may contain any
@@ -5216,6 +5458,10 @@ section is executable
 section is mergeable
 @item S
 section contains zero terminated strings
+@item G
+section is a member of a section group
+@item T
+section is used for thread-local-storage
 @end table
 
 The optional @var{type} argument may contain one of the following constants:
@@ -5224,18 +5470,58 @@ The optional @var{type} argument may contain one of the following constants:
 section contains data
 @item @@nobits
 section does not contain data (i.e., section only occupies space)
+@item @@note
+section contains data which is used by things other than the program
+@item @@init_array
+section contains an array of pointers to init functions
+@item @@fini_array
+section contains an array of pointers to finish functions
+@item @@preinit_array
+section contains an array of pointers to pre-init functions
 @end table
 
+Many targets only support the first three section types.
+
 Note on targets where the @code{@@} character is the start of a comment (eg
 ARM) then another character is used instead.  For example the ARM port uses the
 @code{%} character.
 
-If @var{flags} contains @code{M} flag, @var{type} argument must be specified
-as well as @var{entsize} argument. Sections with @code{M} flag but not
-@code{S} flag must contain fixed size constants, each @var{entsize} octets
-long. Sections with both @code{M} and @code{S} must contain zero terminated
-strings where each character is @var{entsize} bytes long. The linker may remove
-duplicates within sections with the same name, same entity size and same flags. 
+If @var{flags} contains the @code{M} symbol then the @var{type} argument must
+be specified as well as an extra argument - @var{entsize} - like this:
+
+@smallexample
+.section @var{name} , "@var{flags}"M, @@@var{type}, @var{entsize}
+@end smallexample
+
+Sections with the @code{M} flag but not @code{S} flag must contain fixed size
+constants, each @var{entsize} octets long. Sections with both @code{M} and
+@code{S} must contain zero terminated strings where each character is
+@var{entsize} bytes long. The linker may remove duplicates within sections with
+the same name, same entity size and same flags.  @var{entsize} must be an
+absolute expression.
+
+If @var{flags} contains the @code{G} symbol then the @var{type} argument must
+be present along with an additional field like this:
+
+@smallexample
+.section @var{name} , "@var{flags}"G, @@@var{type}, @var{GroupName}[, @var{linkage}]
+@end smallexample
+
+The @var{GroupName} field specifies the name of the section group to which this
+particular section belongs.  The optional linkage field can contain:
+@table @code
+@item comdat
+indicates that only one copy of this section should be retained
+@item .gnu.linkonce
+an alias for comdat
+@end table
+
+Note - if both the @var{M} and @var{G} flags are present then the fields for
+the Merge flag should come first, like this:
+
+@smallexample
+.section @var{name} , "@var{flags}"MG, @@@var{type}, @var{entsize}, @var{GroupName}[, @var{linkage}]
+@end smallexample
 
 If no flags are specified, the default flags depend upon the section name.  If
 the section name is not recognized, the default will be for the section to have
@@ -5258,12 +5544,14 @@ section is allocatable
 section is writable
 @item #execinstr
 section is executable
+@item #tls
+section is used for thread local storage
 @end table
 
-This directive replaces the current section and subsection.  The replaced
-section and subsection are pushed onto the section stack.  See the contents of
-the gas testsuite directory @code{gas/testsuite/gas/elf} for some examples of
-how this directive and the other section stack directives work.
+This directive replaces the current section and subsection.  See the
+contents of the gas testsuite directory @code{gas/testsuite/gas/elf} for
+some examples of how this directive and the other section stack directives
+work.
 @end ifset
 @end ifset
 
@@ -5287,6 +5575,11 @@ The syntax for @code{set} on the HPPA is
 @samp{@var{symbol} .set @var{expression}}.
 @end ifset
 
+@ifset Z80
+On Z80 @code{set} is a real instruction, use
+@samp{@var{symbol} defl @var{expression}} instead.
+@end ifset
+
 @node Short
 @section @code{.short @var{expressions}}
 
@@ -5413,21 +5706,6 @@ for a summary.
 @end ifset
 @end ifclear
 
-@ifset A29K
-@ifclear GENERIC
-@node Space
-@section @code{.space}
-@cindex @code{space} directive
-@end ifclear
-On the AMD 29K, this directive is ignored; it is accepted for
-compatibility with other AMD 29K assemblers.
-
-@quotation
-@emph{Warning:} In most versions of the @sc{gnu} assembler, the directive
-@code{.space} has the effect of @code{.block}  @xref{Machine Dependencies}.
-@end quotation
-@end ifset
-
 @ifset have-stabs
 @node Stab
 @section @code{.stabd, .stabn, .stabs}
@@ -5745,28 +6023,59 @@ formatted note of type NT_VERSION.  The note's name is set to @code{string}.
 @node VTableEntry
 @section @code{.vtable_entry @var{table}, @var{offset}}
 
-@cindex @code{vtable_entry}
+@cindex @code{vtable_entry} directive
 This directive finds or creates a symbol @code{table} and creates a
 @code{VTABLE_ENTRY} relocation for it with an addend of @code{offset}.
 
 @node VTableInherit
 @section @code{.vtable_inherit @var{child}, @var{parent}}
 
-@cindex @code{vtable_inherit}
+@cindex @code{vtable_inherit} directive
 This directive finds the symbol @code{child} and finds or creates the symbol
 @code{parent} and then creates a @code{VTABLE_INHERIT} relocation for the
 parent whose addend is the value of the child symbol.  As a special case the
 parent name of @code{0} is treated as refering the @code{*ABS*} section.
 @end ifset
 
-@ifset ELF
+@node Warning
+@section @code{.warning "@var{string}"}
+@cindex warning directive
+Similar to the directive @code{.error}
+(@pxref{Error,,@code{.error "@var{string}"}}), but just emits a warning.
+
 @node Weak
 @section @code{.weak @var{names}}
 
 @cindex @code{weak} directive
 This directive sets the weak attribute on the comma separated list of symbol
 @code{names}.  If the symbols do not already exist, they will be created.
-@end ifset
+
+On COFF targets other than PE, weak symbols are a GNU extension.  This 
+directive sets the weak attribute on the comma separated list of symbol
+@code{names}.  If the symbols do not already exist, they will be created.
+
+On the PE target, weak symbols are supported natively as weak aliases.
+When a weak symbol is created that is not an alias, GAS creates an 
+alternate symbol to hold the default value.
+
+@node Weakref
+@section @code{.weakref @var{alias}, @var{target}}
+
+@cindex @code{weakref} directive
+This directive creates an alias to the target symbol that enables the symbol to
+be referenced with weak-symbol semantics, but without actually making it weak.
+If direct references or definitions of the symbol are present, then the symbol
+will not be weak, but if all references to it are through weak references, the
+symbol will be marked as weak in the symbol table.
+
+The effect is equivalent to moving all references to the alias to a separate
+assembly source file, renaming the alias to the symbol in it, declaring the
+symbol as weak there, and running a reloadable link to merge the object files
+resulting from the assembly of the new source file and the old source file that
+had the references to the alias removed.
+
+The alias itself never makes to the symbol table, and is entirely handled
+within the assembler.
 
 @node Word
 @section @code{.word @var{expressions}}
@@ -5864,9 +6173,6 @@ include details on any machine's instruction set.  For details on that
 subject, see the hardware manufacturer's manual.
 
 @menu
-@ifset A29K
-* AMD29K-Dependent::            AMD 29K Dependent Features
-@end ifset
 @ifset ALPHA
 * Alpha-Dependent::		Alpha Dependent Features
 @end ifset
@@ -5876,6 +6182,9 @@ subject, see the hardware manufacturer's manual.
 @ifset ARM
 * ARM-Dependent::               ARM Dependent Features
 @end ifset
+@ifset BFIN
+* BFIN-Dependent::		BFIN Dependent Features
+@end ifset
 @ifset CRIS
 * CRIS-Dependent::              CRIS Dependent Features
 @end ifset
@@ -5888,9 +6197,6 @@ subject, see the hardware manufacturer's manual.
 @ifset H8/300
 * H8/300-Dependent::            Renesas H8/300 Dependent Features
 @end ifset
-@ifset H8/500
-* H8/500-Dependent::            Renesas H8/500 Dependent Features
-@end ifset
 @ifset HPPA
 * HPPA-Dependent::              HPPA Dependent Features
 @end ifset
@@ -5906,9 +6212,15 @@ subject, see the hardware manufacturer's manual.
 @ifset I960
 * i960-Dependent::              Intel 80960 Dependent Features
 @end ifset
+@ifset IA64
+* IA-64-Dependent::             Intel IA-64 Dependent Features
+@end ifset
 @ifset IP2K
 * IP2K-Dependent::              IP2K Dependent Features
 @end ifset
+@ifset M32C
+* M32C-Dependent::              M32C Dependent Features
+@end ifset
 @ifset M32R
 * M32R-Dependent::              M32R Dependent Features
 @end ifset
@@ -5918,9 +6230,6 @@ subject, see the hardware manufacturer's manual.
 @ifset M68HC11
 * M68HC11-Dependent::           M68HC11 and 68HC12 Dependent Features
 @end ifset
-@ifset M880X0
-* M88K-Dependent::		M880x0 Dependent Features
-@end ifset
 @ifset MIPS
 * MIPS-Dependent::              MIPS Dependent Features
 @end ifset
@@ -5955,6 +6264,9 @@ subject, see the hardware manufacturer's manual.
 @ifset XTENSA
 * Xtensa-Dependent::            Xtensa Dependent Features
 @end ifset
+@ifset Z80
+* Z80-Dependent::               Z80 Dependent Features
+@end ifset
 @ifset Z8000
 * Z8000-Dependent::             Z8000 Dependent Features
 @end ifset
@@ -5974,10 +6286,6 @@ subject, see the hardware manufacturer's manual.
 @c node and sectioning commands; hence the repetition of @chapter BLAH
 @c in both conditional blocks.
 
-@ifset A29K
-@include c-a29k.texi
-@end ifset
-
 @ifset ALPHA
 @include c-alpha.texi
 @end ifset
@@ -5990,6 +6298,10 @@ subject, see the hardware manufacturer's manual.
 @include c-arm.texi
 @end ifset
 
+@ifset BFIN
+@include c-bfin.texi
+@end ifset
+
 @ifset CRIS
 @include c-cris.texi
 @end ifset
@@ -6006,7 +6318,6 @@ family.
 
 @menu
 * H8/300-Dependent::            Renesas H8/300 Dependent Features
-* H8/500-Dependent::            Renesas H8/500 Dependent Features
 * SH-Dependent::                Renesas SH Dependent Features
 @end menu
 @lowersections
@@ -6025,10 +6336,6 @@ family.
 @include c-h8300.texi
 @end ifset
 
-@ifset H8/500
-@include c-h8500.texi
-@end ifset
-
 @ifset HPPA
 @include c-hppa.texi
 @end ifset
@@ -6057,6 +6364,10 @@ family.
 @include c-ip2k.texi
 @end ifset
 
+@ifset M32C
+@include c-m32c.texi
+@end ifset
+
 @ifset M32R
 @include c-m32r.texi
 @end ifset
@@ -6069,10 +6380,6 @@ family.
 @include c-m68hc11.texi
 @end ifset
 
-@ifset M880X0
-@include c-m88k.texi
-@end ifset
-
 @ifset MIPS
 @include c-mips.texi
 @end ifset
@@ -6114,6 +6421,10 @@ family.
 @include c-tic54x.texi
 @end ifset
 
+@ifset Z80
+@include c-z80.texi
+@end ifset
+
 @ifset Z8000
 @include c-z8k.texi
 @end ifset
@@ -6340,7 +6651,7 @@ things without first using the debugger to find the facts.
 @node Acknowledgements
 @chapter Acknowledgements
 
-If you have contributed to @command{@value{AS}} and your name isn't listed here,
+If you have contributed to GAS and your name isn't listed here,
 it is not meant as a slight.  We just don't know about it.  Send mail to the
 maintainer, and we'll correct the situation.  Currently 
 @c (January 1994), 
@@ -6382,8 +6693,8 @@ Keith Knowles at the Open Software Foundation wrote the original MIPS back end
 (which hasn't been merged in yet).  Ralph Campbell worked with the MIPS code to
 support a.out format.
 
-Support for the Zilog Z8k and Renesas H8/300 and H8/500 processors (tc-z8k,
-tc-h8300, tc-h8500), and IEEE 695 object file format (obj-ieee), was written by
+Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k,
+tc-h8300), and IEEE 695 object file format (obj-ieee), was written by
 Steve Chamberlain of Cygnus Support.  Steve also modified the COFF back end to
 use BFD for some low-level operations, for use with the H8/300 and AMD 29k
 targets.
@@ -6401,7 +6712,7 @@ Ian Lance Taylor of Cygnus Support merged the Motorola and MIT syntax for the
 added support for MIPS ECOFF and ELF targets, wrote the initial RS/6000 and
 PowerPC assembler, and made a few other minor patches.
 
-Steve Chamberlain made @command{@value{AS}} able to generate listings.
+Steve Chamberlain made GAS able to generate listings.
 
 Hewlett-Packard contributed support for the HP9000/300.
 
diff --git a/gas/doc/asconfig.texi b/gas/doc/asconfig.texi
new file mode 100644
index 000000000000..150685f38fb3
--- /dev/null
+++ b/gas/doc/asconfig.texi
@@ -0,0 +1,90 @@
+@c Copyright 1992, 1993, 1994, 1996, 1997, 1999, 2000, 2001, 2002,
+@c 2003, 2005
+@c Free Software Foundation, Inc.
+@c This file is part of the documentation for the GAS manual
+
+@c Configuration settings for all-inclusive version of manual
+
+@c switches:------------------------------------------------------------
+@c Properties of the manual
+@c ========================
+@c Discuss all architectures?
+@set ALL-ARCH
+@c A generic form of manual (not tailored to specific target)?
+@set GENERIC
+@c Include text on assembler internals?
+@clear INTERNALS
+@c Many object formats supported in this config?
+@set MULTI-OBJ
+
+@c Object formats of interest
+@c ==========================
+@set AOUT
+@set COFF
+@set ELF
+@set SOM
+
+@c CPUs of interest
+@c ================
+@set ALPHA
+@set ARC
+@set ARM
+@set BFIN
+@set CRIS
+@set D10V
+@set D30V
+@set H8/300
+@set HPPA
+@set I370
+@set I80386
+@set I860
+@set I960
+@set IA64
+@set IP2K
+@set M32C
+@set M32R
+@set xc16x
+@set M68HC11
+@set M680X0
+@set MCORE
+@set MIPS
+@set MMIX
+@set MS1
+@set MSP430
+@set PDP11
+@set PJ
+@set PPC
+@set SH
+@set SPARC
+@set TIC54X
+@set V850
+@set VAX
+@set XTENSA
+@set Z80
+@set Z8000
+
+@c Does this version of the assembler use the difference-table kluge?
+@set DIFF-TBL-KLUGE
+
+@c Do all machines described use IEEE floating point?
+@clear IEEEFLOAT
+
+@c Is a word 32 bits, or 16?
+@clear W32
+@set W16
+
+@c Do symbols have different characters than usual?
+@clear SPECIAL-SYMS
+
+@c strings:------------------------------------------------------------
+@c Name of the assembler:
+@set AS as
+@c Name of C compiler:
+@set GCC gcc
+@c Name of linker:
+@set LD ld
+@c Text for target machine (best not used in generic case; but just in case...)
+@set TARGET machine specific
+@c Name of object format NOT SET in generic version
+@clear OBJ-NAME
+@set top_srcdir ../.././gas
diff --git a/gas/doc/c-a29k.texi b/gas/doc/c-a29k.texi
deleted file mode 100644
index 222cfef80410..000000000000
--- a/gas/doc/c-a29k.texi
+++ /dev/null
@@ -1,182 +0,0 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-@c This is part of the GAS manual.
-@c For copying conditions, see the file as.texinfo.
-@ifset GENERIC
-@page
-@node AMD29K-Dependent
-@chapter AMD 29K Dependent Features
-@end ifset
-@ifclear GENERIC
-@node Machine Dependencies
-@chapter AMD 29K Dependent Features
-@end ifclear
-
-@cindex AMD 29K support
-@cindex 29K support
-@menu
-* AMD29K Options::              Options
-* AMD29K Syntax::               Syntax
-* AMD29K Floating Point::       Floating Point
-* AMD29K Directives::           AMD 29K Machine Directives
-* AMD29K Opcodes::              Opcodes
-@end menu
-
-@node AMD29K Options
-@section Options
-@cindex AMD 29K options (none)
-@cindex options for AMD29K (none)
-@code{@value{AS}} has no additional command-line options for the AMD
-29K family.
-
-@node AMD29K Syntax
-@section Syntax
-@menu
-* AMD29K-Macros::		Macros
-* AMD29K-Chars::                Special Characters
-* AMD29K-Regs::                 Register Names
-@end menu
-
-@node AMD29K-Macros
-@subsection Macros
-
-@cindex Macros, AMD 29K
-@cindex AMD 29K macros
-The macro syntax used on the AMD 29K is like that described in the AMD
-29K Family Macro Assembler Specification.  Normal @code{@value{AS}}
-macros should still work.
-
-@node AMD29K-Chars
-@subsection Special Characters
-
-@cindex line comment character, AMD 29K
-@cindex AMD 29K line comment character
-@samp{;} is the line comment character.
-
-@cindex identifiers, AMD 29K
-@cindex AMD 29K identifiers
-The character @samp{?} is permitted in identifiers (but may not begin
-an identifier).
-
-@node AMD29K-Regs
-@subsection Register Names
-
-@cindex AMD 29K register names
-@cindex register names, AMD 29K
-General-purpose registers are represented by predefined symbols of the
-form @samp{GR@var{nnn}} (for global registers) or @samp{LR@var{nnn}}
-(for local registers), where @var{nnn} represents a number between
-@code{0} and @code{127}, written with no leading zeros.  The leading
-letters may be in either upper or lower case; for example, @samp{gr13}
-and @samp{LR7} are both valid register names.
-
-You may also refer to general-purpose registers by specifying the
-register number as the result of an expression (prefixed with @samp{%%}
-to flag the expression as a register number):
-@smallexample
-%%@var{expression}
-@end smallexample
-@noindent
----where @var{expression} must be an absolute expression evaluating to a
-number between @code{0} and @code{255}.  The range [0, 127] refers to
-global registers, and the range [128, 255] to local registers.
-
-@cindex special purpose registers, AMD 29K
-@cindex AMD 29K special purpose registers
-@cindex protected registers, AMD 29K
-@cindex AMD 29K protected registers
-In addition, @code{@value{AS}} understands the following protected
-special-purpose register names for the AMD 29K family:
-
-@smallexample
-  vab    chd    pc0
-  ops    chc    pc1
-  cps    rbp    pc2
-  cfg    tmc    mmu
-  cha    tmr    lru
-@end smallexample
-
-These unprotected special-purpose register names are also recognized:
-@smallexample
-  ipc    alu    fpe
-  ipa    bp     inte
-  ipb    fc     fps
-  q      cr     exop
-@end smallexample
-
-@node AMD29K Floating Point
-@section Floating Point
-
-@cindex floating point, AMD 29K (@sc{ieee})
-@cindex AMD 29K floating point (@sc{ieee})
-The AMD 29K family uses @sc{ieee} floating-point numbers.
-
-@node AMD29K Directives
-@section AMD 29K Machine Directives
-
-@cindex machine directives, AMD 29K
-@cindex AMD 29K machine directives
-@table @code
-@cindex @code{block} directive, AMD 29K
-@item .block @var{size} , @var{fill}
-This directive emits @var{size} bytes, each of value @var{fill}.  Both
-@var{size} and @var{fill} are absolute expressions.  If the comma
-and @var{fill} are omitted, @var{fill} is assumed to be zero.
-
-In other versions of the @sc{gnu} assembler, this directive is called
-@samp{.space}.
-@end table
-
-@table @code
-@cindex @code{cputype} directive, AMD 29K
-@item .cputype
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@cindex @code{file} directive, AMD 29K
-@item .file
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@quotation
-@emph{Warning:} in other versions of the @sc{gnu} assembler, @code{.file} is
-used for the directive called @code{.app-file} in the AMD 29K support.
-@end quotation
-
-@cindex @code{line} directive, AMD 29K
-@item .line
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@ignore
-@c since we're ignoring .lsym...
-@cindex @code{reg} directive, AMD 29K
-@item .reg @var{symbol}, @var{expression}
-@code{.reg} has the same effect as @code{.lsym}; @pxref{Lsym,,@code{.lsym}}.
-@end ignore
-
-@cindex @code{sect} directive, AMD 29K
-@item .sect
-This directive is ignored; it is accepted for compatibility with other
-AMD 29K assemblers.
-
-@cindex @code{use} directive, AMD 29K
-@item .use @var{section name}
-Establishes the section and subsection for the following code;
-@var{section name} may be one of @code{.text}, @code{.data},
-@code{.data1}, or @code{.lit}.  With one of the first three @var{section
-name} options, @samp{.use} is equivalent to the machine directive
-@var{section name}; the remaining case, @samp{.use .lit}, is the same as
-@samp{.data 200}.
-@end table
-
-@node AMD29K Opcodes
-@section Opcodes
-
-@cindex AMD 29K opcodes
-@cindex opcodes for AMD 29K
-@code{@value{AS}} implements all the standard AMD 29K opcodes.  No
-additional pseudo-instructions are needed on this family.
-
-For information on the 29K machine instruction set, see @cite{Am29000
-User's Manual}, Advanced Micro Devices, Inc.
-
diff --git a/gas/doc/c-alpha.texi b/gas/doc/c-alpha.texi
index 0aee06b2d8be..f426b822828d 100644
--- a/gas/doc/c-alpha.texi
+++ b/gas/doc/c-alpha.texi
@@ -1,4 +1,4 @@
-@c Copyright 2002
+@c Copyright 2002, 2003
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -203,6 +203,12 @@ Used with a register branch format instruction (e.g.@: @code{jsr}) to
 indicate that the literal is used for a call.  During relaxation, the
 code may be altered to use a direct branch (e.g.@: @code{bsr}).
 
+@item !lituse_jsrdirect!@var{N}
+Similar to @code{lituse_jsr}, but also that this call cannot be vectored
+through a PLT entry.  This is useful for functions with special calling
+conventions which do not allow the normal call-clobbered registers to be
+clobbered.
+
 @item !lituse_bytoff!@var{N}
 Used with a byte mask instruction (e.g.@: @code{extbl}) to indicate
 that only the low 3 bits of the address are relevant.  During relaxation,
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 700a01d15d8c..04544d1e4951 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -1,4 +1,4 @@
-@c Copyright 2000, 2001 Free Software Foundation, Inc.
+@c Copyright 2000, 2001, 2005 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
@@ -34,7 +34,7 @@
 
 @cindex @code{-marc[5|6|7|8]} command line option, ARC
 @item -marc[5|6|7|8]
-This option selects the core processor variant. Using
+This option selects the core processor variant.  Using
 @code{-marc} is the same as @code{-marc@value{ARC_CORE_DEFAULT}}, which
 is also the default.
 
@@ -46,8 +46,8 @@ Base instruction set.
 
 @cindex @code{arc6} arc6, ARC
 @item arc6
-Jump-and-link (jl) instruction. No requirement of an instruction between
-setting flags and conditional jump. For example:
+Jump-and-link (jl) instruction.  No requirement of an instruction between
+setting flags and conditional jump.  For example:
 
 @smallexample
   mov.f r0,r1
@@ -137,36 +137,161 @@ machine directives:
 
 @cindex @code{extAuxRegister} directive, ARC
 @item .extAuxRegister @var{name},@var{address},@var{mode}
-*TODO*
+The ARCtangent A4 has extensible auxiliary register space.  The
+auxiliary registers can be defined in the assembler source code by
+using this directive.  The first parameter is the @var{name} of the
+new auxiallry register.  The second parameter is the @var{address} of
+the register in the auxiliary register memory map for the variant of
+the ARC.  The third parameter specifies the @var{mode} in which the
+register can be operated is and it can be one of: 
+
+@table @code
+@item r          (readonly) 
+@item w          (write only)
+@item r|w        (read or write)
+@end table
+
+For example:
 
 @smallexample
   .extAuxRegister mulhi,0x12,w
 @end smallexample
 
+This specifies an extension auxiliary register called @emph{mulhi}
+which is at address 0x12 in the memory space and which is only
+writable.
+
 @cindex @code{extCondCode} directive, ARC
 @item .extCondCode @var{suffix},@var{value}
-*TODO*
+The condition codes on the ARCtangent A4 are extensible and can be
+specified by means of this assembler directive.  They are specified
+by the suffix and the value for the condition code.  They can be used to
+specify extra condition codes with any values.  For example:
 
 @smallexample
   .extCondCode is_busy,0x14
+  
+   add.is_busy  r1,r2,r3
+   bis_busy     _main
 @end smallexample
 
 @cindex @code{extCoreRegister} directive, ARC
 @item .extCoreRegister @var{name},@var{regnum},@var{mode},@var{shortcut}
-*TODO*
+Specifies an extension core register @var{name} for the application.
+This allows a register @var{name} with a valid @var{regnum} between 0
+and 60, with the following as valid values for @var{mode} 
+
+@table @samp
+@item @emph{r}   (readonly) 
+@item @emph{w}   (write only)
+@item @emph{r|w} (read or write)
+@end table
+
+
+The other parameter gives a description of the register having a
+@var{shortcut} in the pipeline.  The valid values are:
+
+@table @code
+@item can_shortcut
+@item cannot_shortcut
+@end table
+
+For example:
 
 @smallexample
   .extCoreRegister mlo,57,r,can_shortcut
 @end smallexample
 
+This defines an extension core register mlo with the value 57 which
+can shortcut the pipeline.
+
 @cindex @code{extInstruction} directive, ARC
 @item .extInstruction @var{name},@var{opcode},@var{subopcode},@var{suffixclass},@var{syntaxclass}
-*TODO*
+The ARCtangent A4 allows the user to specify extension instructions.
+The extension instructions are not macros.  The assembler creates
+encodings for use of these instructions according to the specification
+by the user.  The parameters are:
+
+@table @bullet
+@item @var{name}
+Name of the extension instruction 
+
+@item @var{opcode}
+Opcode to be used. (Bits 27:31 in the encoding).  Valid values
+0x10-0x1f or 0x03
+
+@item @var{subopcode}
+Subopcode to be used.  Valid values are from 0x09-0x3f.  However the
+correct value also depends on @var{syntaxclass}
+
+@item @var{suffixclass}
+Determines the kinds of suffixes to be allowed.  Valid values are
+@code{SUFFIX_NONE}, @code{SUFFIX_COND}, 
+@code{SUFFIX_FLAG} which indicates the absence or presence of
+conditional suffixes and flag setting by the extension instruction.
+It is also possible to specify that an instruction sets the flags and
+is conditional by using @code{SUFFIX_CODE} | @code{SUFFIX_FLAG}.
+
+@item @var{syntaxclass}
+Determines the syntax class for the instruction.  It can have the
+following values:
+
+@table @code
+@item @code{SYNTAX_2OP}:
+2 Operand Instruction 
+@item @code{SYNTAX_3OP}:
+3 Operand Instruction 
+@end table
+
+In addition there could be modifiers for the syntax class as described
+below:
+
+@itemize @minus
+Syntax Class Modifiers are:
+
+@item @code{OP1_MUST_BE_IMM}:
+Modifies syntax class SYNTAX_3OP,  specifying that the first operand
+of a three-operand instruction must be an immediate (i.e. the result
+is discarded).  OP1_MUST_BE_IMM is used by bitwise ORing it with
+SYNTAX_3OP as given in the example below.  This could usually be used
+to set the flags using specific instructions and not retain results. 
+
+@item @code{OP1_IMM_IMPLIED}:
+Modifies syntax class SYNTAX_20P, it specifies that there is an
+implied immediate destination operand which does not appear in the
+syntax.  For example, if the source code contains an instruction like:
+
+@smallexample
+inst r1,r2 
+@end smallexample
+
+it really means that the first argument is an implied immediate (that
+is, the result is discarded).  This is the same as though the source
+code were: inst 0,r1,r2.  You use OP1_IMM_IMPLIED by bitwise ORing it
+with SYNTAX_20P.
+
+@end itemize 
+@end table
+
+For example, defining 64-bit multiplier with immediate operands:
 
 @smallexample
-  .extInstruction mul64,0x14,0x0,SUFFIX_COND,SYNTAX_3OP|OP1_MUST_BE_IMM
+.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG ,
+                SYNTAX_3OP|OP1_MUST_BE_IMM
 @end smallexample
 
+The above specifies an extension instruction called mp64 which has 3 operands,
+sets the flags, can be used with a condition code, for which the
+first operand is an immediate.  (Equivalent to discarding the result 
+of the operation).
+
+@smallexample
+ .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
+@end smallexample
+
+This describes a 2 operand instruction with an implicit first
+immediate operand.  The result of this operation would be discarded.
+
 @cindex @code{half} directive, ARC
 @item .half @var{expressions}
 *TODO*
@@ -204,4 +329,5 @@ between the two - even for the implicit default core version
 @cindex opcodes for ARC
 
 For information on the ARC instruction set, see @cite{ARC Programmers
-Reference Manual}, ARC Cores Ltd.
+Reference Manual}, ARC International (www.arc.com)
+
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 23cd7bb3fef6..ca0998bea669 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -1,4 +1,4 @@
-@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2003
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -67,6 +67,7 @@ recognized:
 @code{arm7500fe},
 @code{arm7t},
 @code{arm7tdmi},
+@code{arm7tdmi-s},
 @code{arm8},
 @code{arm810},
 @code{strongarm},
@@ -82,19 +83,33 @@ recognized:
 @code{arm9tdmi},
 @code{arm9e},
 @code{arm926e},
-@code{arm926ejs},
+@code{arm926ej-s},
 @code{arm946e-r0},
 @code{arm946e},
+@code{arm946e-s},
 @code{arm966e-r0},
 @code{arm966e},
+@code{arm966e-s},
+@code{arm968e-s},
 @code{arm10t},
+@code{arm10tdmi},
 @code{arm10e},
 @code{arm1020},
 @code{arm1020t},
 @code{arm1020e},
-@code{arm1026ejs},
-@code{arm1136js},
-@code{arm1136jfs},
+@code{arm1022e},
+@code{arm1026ej-s},
+@code{arm1136j-s},
+@code{arm1136jf-s},
+@code{arm1156t2-s},
+@code{arm1156t2f-s},
+@code{arm1176jz-s},
+@code{arm1176jzf-s},
+@code{mpcore},
+@code{mpcorenovfp},
+@code{cortex-a8},
+@code{cortex-r4},
+@code{cortex-m3},
 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
 @code{i80200} (Intel XScale processor)
 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
@@ -136,6 +151,13 @@ names are recognized:
 @code{armv5texp},
 @code{armv6},
 @code{armv6j},
+@code{armv6k},
+@code{armv6z},
+@code{armv6zk},
+@code{armv7},
+@code{armv7a},
+@code{armv7r},
+@code{armv7m},
 @code{iwmmxt}
 and
 @code{xscale}.
@@ -170,7 +192,7 @@ The following format options are recognized:
 @code{vfpxd},
 @code{arm1020t},
 @code{arm1020e},
-@code{arm1136jfs}
+@code{arm1136jf-s}
 and
 @code{maverick}.
 
@@ -228,6 +250,16 @@ The following values are recognized:
 and
 @code{hard}.
 
+@cindex @code{-eabi=} command line option, ARM
+@item -meabi=@var{ver}
+This option specifies which EABI version the produced object files should
+conform to.
+The following values are recognised:
+@code{gnu},
+@code{4}
+and
+@code{5}.
+
 @cindex @code{-EB} command line option, ARM
 @item -EB
 This option specifies that the output generated by the assembler should
@@ -244,13 +276,6 @@ be marked as being encoded for a little-endian processor.
 This option specifies that the output of the assembler should be marked
 as position-independent code (PIC).
 
-@cindex @code{-moabi} command line option, ARM
-@item -moabi
-This indicates that the code should be assembled using the old ARM ELF
-conventions, based on a beta release release of the ARM-ELF
-specifications, rather than the default conventions which are based on
-the final release of the ARM-ELF specifications.
-
 @end table
 
 
@@ -390,6 +415,125 @@ it prevents accurate control of the placement of literal pools.
 @item .pool
 This is a synonym for .ltorg.
 
+@cindex @code{.fnstart} directive, ARM
+@item .unwind_fnstart
+Marks the start of a function with an unwind table entry.
+
+@cindex @code{.fnend} directive, ARM
+@item .unwind_fnend
+Marks the end of a function with an unwind table entry.  The unwind index
+table entry is created when this directive is processed.
+
+If no personality routine has been specified then standard personality
+routine 0 or 1 will be used, depending on the number of unwind opcodes
+required.
+
+@cindex @code{.cantunwind} directive, ARM
+@item .cantunwind
+Prevents unwinding through the current function.  No personality routine
+or exception table data is required or permitted.
+
+@cindex @code{.personality} directive, ARM
+@item .personality @var{name}
+Sets the personality routine for the current function to @var{name}.
+
+@cindex @code{.personalityindex} directive, ARM
+@item .personalityindex @var{index}
+Sets the personality routine for the current function to the EABI standard
+routine number @var{index}
+
+@cindex @code{.handlerdata} directive, ARM
+@item .handlerdata
+Marks the end of the current function, and the start of the exception table
+entry for that function.  Anything between this directive and the
+@code{.fnend} directive will be added to the exception table entry.
+
+Must be preceded by a @code{.personality} or @code{.personalityindex}
+directive.
+
+@cindex @code{.save} directive, ARM
+@item .save @var{reglist}
+Generate unwinder annotations to restore the registers in @var{reglist}.
+The format of @var{reglist} is the same as the corresponding store-multiple
+instruction.
+
+@smallexample
+@exdent @emph{core registers}
+  .save @{r4, r5, r6, lr@}
+  stmfd sp!, @{r4, r5, r6, lr@}
+@exdent @emph{FPA registers}
+  .save f4, 2
+  sfmfd f4, 2, [sp]!
+@exdent @emph{VFP registers}
+  .save @{d8, d9, d10@}
+  fstmdf sp!, @{d8, d9, d10@}
+@exdent @emph{iWMMXt registers}
+  .save @{wr10, wr11@}
+  wstrd wr11, [sp, #-8]!
+  wstrd wr10, [sp, #-8]!
+or
+  .save wr11
+  wstrd wr11, [sp, #-8]!
+  .save wr10
+  wstrd wr10, [sp, #-8]!
+@end smallexample
+
+@cindex @code{.pad} directive, ARM
+@item .pad #@var{count}
+Generate unwinder annotations for a stack adjustment of @var{count} bytes.
+A positive value indicates the function prologue allocated stack space by
+decrementing the stack pointer.
+
+@cindex @code{.movsp} directive, ARM
+@item .movsp @var{reg}
+Tell the unwinder that @var{reg} contains the current stack pointer.
+
+@cindex @code{.setfp} directive, ARM
+@item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
+Make all unwinder annotations relaive to a frame pointer.  Without this
+the unwinder will use offsets from the stack pointer.
+
+The syntax of this directive is the same as the @code{sub} or @code{mov}
+instruction used to set the frame pointer.  @var{spreg} must be either
+@code{sp} or mentioned in a previous @code{.movsp} directive.
+
+@smallexample
+.movsp ip
+mov ip, sp
+@dots{}
+.setfp fp, ip, #4
+sub fp, ip, #4
+@end smallexample
+
+@cindex @code{.unwind_raw} directive, ARM
+@item .raw @var{offset}, @var{byte1}, @dots{}
+Insert one of more arbitary unwind opcode bytes, which are known to adjust
+the stack pointer by @var{offset} bytes.
+
+For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
+@code{.save @{r0@}}
+
+@cindex @code{.cpu} directive, ARM
+@item .cpu @var{name}
+Select the target processor.  Valid values for @var{name} are the same as
+for the @option{-mcpu} commandline option.
+
+@cindex @code{.arch} directive, ARM
+@item .arch @var{name}
+Select the target architecture.  Valid values for @var{name} are the same as
+for the @option{-march} commandline option.
+
+@cindex @code{.fpu} directive, ARM
+@item .fpu @var{name}
+Select the floating point unit to assemble for.  Valid values for @var{name}
+are the same as for the @option{-mfpu} commandline option.
+
+@cindex @code{.eabi_attribute} directive, ARM
+@item .eabi_attribute @var{tag}, @var{value}
+Set the EABI object attribute number @var{tag} to @var{value}.  The value
+is either a @code{number}, @code{"string"}, or @code{number, "string"}
+depending on the tag.
+
 @end table
 
 @node ARM Opcodes
diff --git a/gas/doc/c-bfin.texi b/gas/doc/c-bfin.texi
new file mode 100644
index 000000000000..dcf649a2b890
--- /dev/null
+++ b/gas/doc/c-bfin.texi
@@ -0,0 +1,187 @@
+@c Copyright 2005
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node BFIN-Dependent
+@chapter Blackfin Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Blackfin Dependent Features
+@end ifclear
+
+@cindex Blackfin support
+@menu
+* BFIN Syntax::			BFIN Syntax
+* BFIN Directives::		BFIN Directives
+@end menu
+
+@node BFIN Syntax
+@section Syntax
+@cindex BFIN syntax
+@cindex syntax, BFIN
+
+@table @code
+@item Special Characters
+Assembler input is free format and may appear anywhere on the line.
+One instruction may extend across multiple lines or more than one
+instruction may appear on the same line.  White space (space, tab,
+comments or newline) may appear anywhere between tokens.  A token must
+not have embedded spaces.  Tokens include numbers, register names,
+keywords, user identifiers, and also some multicharacter special 
+symbols like "+=", "/*" or "||".
+
+@item Instruction Delimiting
+A semicolon must terminate every instruction.  Sometimes a complete
+instruction will consist of more than one operation.  There are two 
+cases where this occurs.  The first is when two general operations
+are combined.  Normally a comma separates the different parts, as in
+
+@smallexample
+a0= r3.h * r2.l, a1 = r3.l * r2.h ;
+@end smallexample
+
+The second case occurs when a general instruction is combined with one
+or two memory references for joint issue.  The latter portions are
+set off by a "||" token.
+
+@smallexample
+a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
+@end smallexample
+
+@item Register Names
+
+The assembler treats register names and instruction keywords in a case
+insensitive manner.  User identifiers are case sensitive.  Thus, R3.l,
+R3.L, r3.l and r3.L are all equivalent input to the assembler.
+
+Register names are reserved and may not be used as program identifiers.
+
+Some operations (such as "Move Register") require a register pair. 
+Register pairs are always data registers and are denoted using a colon,
+eg., R3:2.  The larger number must be written firsts.  Note that the 
+hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
+
+Some instructions (such as --SP (Push Multiple)) require a group of
+adjacent registers.  Adjacent registers are denoted in the syntax by
+the range enclosed in parentheses and separated by a colon, eg., (R7:3).
+Again, the larger number appears first.
+
+Portions of a particular register may be individually specified.  This
+is written with a dot (".") following the register name and then a 
+letter denoting the desired portion.  For 32-bit registers, ".H"
+denotes the most significant ("High") portion.  ".L" denotes the
+least-significant portion.  The subdivisions of the 40-bit registers
+are described later.
+
+@item Accumulators
+The set of 40-bit registers A1 and A0 that normally contain data that
+is being manipulated.  Each accumulator can be accessed in four ways.
+
+@table @code
+@item one 40-bit register
+The register will be referred to as A1 or A0.
+@item one 32-bit register
+The registers are designated as A1.W or A0.W.
+@item two 16-bit registers
+The registers are designated as A1.H, A1.L, A0.H or A0.L.
+@item one 8-bit register
+The registers are designated as A1.X or A0.X for the bits that
+extend beyond bit 31.
+@end table
+
+@item Data Registers
+The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
+normally contain data for manipulation.  These are abbreviated as 
+D-register or Dreg.  Data registers can be accessed as 32-bit registers
+or as two independent 16-bit registers.  The least significant 16 bits
+of each register is called the "low" half and is desginated with ".L"
+following the register name.  The most significant 16 bits are called
+the "high" half and is designated with ".H". following the name.
+
+@smallexample
+   R7.L, r2.h, r4.L, R0.H
+@end smallexample
+
+@item Pointer Registers
+The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
+normally contain byte addresses of data structures.  These are
+abbreviated as P-register or Preg.
+
+@smallexample
+p2, p5, fp, sp
+@end smallexample
+
+@item Stack Pointer SP
+The stack pointer contains the 32-bit address of the last occupied
+byte location in the stack.  The stack grows by decrementing the
+stack pointer.
+
+@item Frame Pointer FP
+The frame pointer contains the 32-bit address of the previous frame
+pointer in the stack.  It is located at the top of a frame.
+
+@item Loop Top
+LT0 and LT1.  These registers contain the 32-bit address of the top of
+a zero overhead loop.
+
+@item Loop Count
+LC0 and LC1.  These registers contain the 32-bit counter of the zero
+overhead loop executions.
+
+@item Loop Bottom
+LB0 and LB1.  These registers contain the 32-bit address of the bottom
+of a zero overhead loop.
+
+@item Index Registers
+The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
+addresses of data structures.  Abbreviated I-register or Ireg.
+
+@item Modify Registers
+The set of 32-bit registers (M0, M1, M2, M3) that normally contain
+offset values that are added and subracted to one of the index
+registers.  Abbreviated as Mreg.
+
+@item Length Registers
+The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
+length in bytes of the circular buffer.  Abbreviated as Lreg.  Clear
+the Lreg to disable circular addressing for the corresponding Ireg.
+
+@item Base Registers
+The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
+base address in bytes of the circular buffer.  Abbreviated as Breg.
+
+@item Floating Point
+The Blackfin family has no hardware floating point but the .float
+directive generates ieee floating point numbers for use with software
+floating point libraries.
+
+@item Blackfin Opcodes
+For detailed information on the Blackfin machine instruction set, see
+the Blackfin(r) Processor Instruction Set Reference.
+
+@end table
+
+@node BFIN Directives
+@section Directives
+@cindex BFIN directives
+@cindex directives, BFIN
+
+The following directives are provided for compatibility with the VDSP assembler.
+
+@table @code
+@item .byte2
+Initializes a four byte data object.
+@item .byte4
+Initializes a two byte data object.
+@item .db
+TBD
+@item .dd
+TBD
+@item .dw
+TBD
+@item .var
+Define and initialize a 32 bit data object.
+@end table
diff --git a/gas/doc/c-cris.texi b/gas/doc/c-cris.texi
index e8147674b95a..0ef16b94028f 100644
--- a/gas/doc/c-cris.texi
+++ b/gas/doc/c-cris.texi
@@ -1,4 +1,4 @@
-@c Copyright 2002 Free Software Foundation, Inc.
+@c Copyright 2002, 2004 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c CRIS description contributed by Axis Communications.
@@ -16,6 +16,7 @@
 @menu
 * CRIS-Opts::              Command-line Options
 * CRIS-Expand::            Instruction expansion
+* CRIS-Symbols::           Symbols
 * CRIS-Syntax::            Syntax
 @end menu
 
@@ -68,6 +69,39 @@ affect expansion of instructions.  The expansion with
 @option{--pic} will use PC-relative rather than (slightly
 faster) absolute addresses in those expansions.
 
+@cindex @option{--march=@var{architecture}} command line option, CRIS
+@cindex CRIS @option{--march=@var{architecture}} command line option
+@cindex Architecture variant option, CRIS
+@cindex CRIS architecture variant option
+The option @option{--march=@var{architecture}}
+@anchor{march-option}specifies the recognized instruction set
+and recognized register names.  It also controls the
+architecture type of the object file.  Valid values for
+@var{architecture} are:
+@table @code
+
+@item v0_v10
+All instructions and register names for any architecture variant
+in the set v0@dots{}v10 are recognized.  This is the
+default if the target is configured as cris-*.
+
+@item v10
+Only instructions and register names for CRIS v10 (as found in
+ETRAX 100 LX) are recognized.  This is the default if the target
+is configured as crisv10-*.
+
+@item v32
+Only instructions and register names for CRIS v32 (code name
+Guinness) are recognized.  This is the default if the target is
+configured as crisv32-*.  This value implies
+@option{--no-mul-bug-abort}.  (A subsequent
+@option{--mul-bug-abort} will turn it back on.)
+
+@item common_v10_v32
+Only instructions with register names and addressing modes with
+opcodes common to the v10 and v32 are recognized.
+@end table
+
 @cindex @option{-N} command line option, CRIS
 @cindex CRIS @option{-N} command line option
 When @option{-N} is specified, @code{@value{AS}} will emit a
@@ -113,6 +147,59 @@ full 32-bit address.  Since this does not correspond to a single
 instruction, such expansions can optionally be warned about.
 @xref{CRIS-Opts}.
 
+If the operand is found to fit the range, a @code{lapc} mnemonic
+will translate to a @code{lapcq} instruction.  Use @code{lapc.d}
+to force the 32-bit @code{lapc} instruction.
+
+Similarly, the @code{addo} mnemonic will translate to the
+shortest fitting instruction of @code{addoq}, @code{addo.w} and
+@code{addo.d}, when used with a operand that is a constant known
+at assembly time.
+
+@node CRIS-Symbols
+@section Symbols
+@cindex Symbols, built-in, CRIS
+@cindex Symbols, CRIS, built-in
+@cindex CRIS built-in symbols
+@cindex Built-in symbols, CRIS
+
+Some symbols are defined by the assembler.  They're intended to
+be used in conditional assembly, for example:
+@smallexample
+ .if ..asm.arch.cris.v32
+ @var{code for CRIS v32}
+ .elseif ..asm.arch.cris.common_v10_v32
+ @var{code common to CRIS v32 and CRIS v10}
+ .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
+ @var{code for v10}
+ .else
+ .error "Code needs to be added here."
+ .endif
+@end smallexample
+
+These symbols are defined in the assembler, reflecting
+command-line options, either when specified or the default.
+They are always defined, to 0 or 1.
+@table @code
+
+@item ..asm.arch.cris.any_v0_v10
+This symbol is non-zero when @option{--march=v0_v10} is specified
+or the default.
+
+@item ..asm.arch.cris.common_v10_v32
+Set according to the option @option{--march=common_v10_v32}.
+
+@item ..asm.arch.cris.v10
+Reflects the option @option{--march=v10}.
+
+@item ..asm.arch.cris.v32
+Corresponds to @option{--march=v10}.
+@end table
+
+Speaking of symbols, when a symbol is used in code, it can have
+a suffix modifying its value for use in position-independent
+code. @xref{CRIS-Pic}.
+
 @node CRIS-Syntax
 @section Syntax
 
@@ -147,7 +234,8 @@ separate instructions can be specified on a single line.
 @cindex Position-independent code, symbols in, CRIS
 
 When generating @anchor{crispic}position-independent code (SVR4
-PIC) for use in cris-axis-linux-gnu shared libraries, symbol
+PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
+shared libraries, symbol
 suffixes are used to specify what kind of run-time symbol lookup
 will be used, expressed in the object as different
 @emph{relocation types}.  Usually, all absolute symbol values
@@ -271,7 +359,7 @@ each expression, a 32-bit little-endian constant is emitted.
 @cindex pseudo-op .syntax, CRIS
 @cindex CRIS assembler directive .syntax
 @cindex CRIS pseudo-op .syntax
-The @code{.syntax} directive takes as ARGUMENT one of the
+The @code{.syntax} directive takes as @var{ARGUMENT} one of the
 following case-sensitive choices.
 
 @table @code
@@ -305,6 +393,16 @@ directive and emits an error if the option @option{--underscore}
 is in effect.
 @end table
 
+@item .arch ARGUMENT
+@cindex assembler directive .arch, CRIS
+@cindex pseudo-op .arch, CRIS
+@cindex CRIS assembler directive .arch
+@cindex CRIS pseudo-op .arch
+This is an assertion directive, giving an error if the specified
+@var{ARGUMENT} is not the same as the specified or default value
+for the @option{--march=@var{architecture}} option
+(@pxref{march-option}).
+
 @c If you compare with md_pseudo_table, you see that we don't
 @c document ".file" and ".loc" here.  This is because we're just
 @c wrapping the corresponding ELF function and emitting an error for
diff --git a/gas/doc/c-d10v.texi b/gas/doc/c-d10v.texi
index 0db379cb6daa..0def48cd7fb1 100644
--- a/gas/doc/c-d10v.texi
+++ b/gas/doc/c-d10v.texi
@@ -1,4 +1,4 @@
-@c Copyright 1996, 2000 Free Software Foundation, Inc.
+@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
diff --git a/gas/doc/c-h8300.texi b/gas/doc/c-h8300.texi
index 4ea8383af07b..d75f7381d777 100644
--- a/gas/doc/c-h8300.texi
+++ b/gas/doc/c-h8300.texi
@@ -1,4 +1,5 @@
-@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003 Free Software Foundation, Inc.
+@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003
+@c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
diff --git a/gas/doc/c-h8500.texi b/gas/doc/c-h8500.texi
deleted file mode 100644
index f0e071cfb902..000000000000
--- a/gas/doc/c-h8500.texi
+++ /dev/null
@@ -1,272 +0,0 @@
-@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-@c This is part of the GAS manual.
-@c For copying conditions, see the file as.texinfo.
-@page
-@node H8/500-Dependent
-@chapter H8/500 Dependent Features
-
-@cindex H8/500 support
-@menu
-* H8/500 Options::              Options
-* H8/500 Syntax::               Syntax
-* H8/500 Floating Point::       Floating Point
-* H8/500 Directives::           H8/500 Machine Directives
-* H8/500 Opcodes::              Opcodes
-@end menu
-
-@node H8/500 Options
-@section Options
-
-@cindex H8/500 options (none)
-@cindex options, H8/500 (none)
-@code{@value{AS}} has no additional command-line options for the
-Renesas (formerly Hitachi) H8/500 family.
-
-@node H8/500 Syntax
-@section Syntax
-
-@menu
-* H8/500-Chars::                Special Characters
-* H8/500-Regs::                 Register Names
-* H8/500-Addressing::           Addressing Modes
-@end menu
-
-@node H8/500-Chars
-@subsection Special Characters
-
-@cindex line comment character, H8/500
-@cindex H8/500 line comment character
-@samp{!} is the line comment character.
-
-@cindex line separator, H8/500
-@cindex statement separator, H8/500
-@cindex H8/500 line separator
-@samp{;} can be used instead of a newline to separate statements.
-
-@cindex symbol names, @samp{$} in
-@cindex @code{$} in symbol names
-Since @samp{$} has no special meaning, you may use it in symbol names.
-
-@node H8/500-Regs
-@subsection Register Names
-
-@cindex H8/500 registers
-@cindex registers, H8/500
-You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
-@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to
-the H8/500 registers.
-
-The H8/500 also has these control registers:
-
-@table @code
-@item cp
-code pointer
-
-@item dp
-data pointer
-
-@item bp
-base pointer
-
-@item tp
-stack top pointer
-
-@item ep
-extra pointer
-
-@item sr
-status register
-
-@item ccr
-condition code register
-@end table
-
-All registers are 16 bits long.  To represent 32 bit numbers, use two
-adjacent registers; for distant memory addresses, use one of the segment
-pointers (@code{cp} for the program counter; @code{dp} for
-@code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and
-@code{tp} for @code{r6} and @code{r7}.
-
-@node H8/500-Addressing
-@subsection Addressing Modes
-
-@cindex addressing modes, H8/500
-@cindex H8/500 addressing modes
-@value{AS} understands the following addressing modes for the H8/500:
-@table @code
-@item R@var{n}
-Register direct
-
-@item @@R@var{n}
-Register indirect
-
-@item @@(d:8, R@var{n})
-Register indirect with 8 bit signed displacement
-
-@item @@(d:16, R@var{n})
-Register indirect with 16 bit signed displacement
-
-@item @@-R@var{n}
-Register indirect with pre-decrement
-
-@item @@R@var{n}+
-Register indirect with post-increment
-
-@item @@@var{aa}:8
-8 bit absolute address
-
-@item @@@var{aa}:16
-16 bit absolute address
-
-@item #@var{xx}:8
-8 bit immediate
-
-@item #@var{xx}:16
-16 bit immediate
-@end table
-
-@node H8/500 Floating Point
-@section Floating Point
-
-@cindex floating point, H8/500 (@sc{ieee})
-@cindex H8/500 floating point (@sc{ieee})
-The H8/500 family has no hardware floating point, but the @code{.float}
-directive generates @sc{ieee} floating-point numbers for compatibility
-with other development tools.
-
-@node H8/500 Directives
-@section H8/500 Machine Directives
-
-@cindex H8/500 machine directives (none)
-@cindex machine directives, H8/500 (none)
-@cindex @code{word} directive, H8/500
-@cindex @code{int} directive, H8/500
-@code{@value{AS}} has no machine-dependent directives for the H8/500.
-However, on this platform the @samp{.int} and @samp{.word} directives
-generate 16-bit numbers.
-
-@node H8/500 Opcodes
-@section Opcodes
-
-@cindex H8/500 opcode summary
-@cindex opcode summary, H8/500
-@cindex mnemonics, H8/500
-@cindex instruction summary, H8/500
-For detailed information on the H8/500 machine instruction set, see
-@cite{H8/500 Series Programming Manual} (Renesas M21T001).
-
-@code{@value{AS}} implements all the standard H8/500 opcodes.  No additional
-pseudo-instructions are needed on this family.
-
-@ifset SMALL
-@c this table, due to the multi-col faking and hardcoded order, looks silly
-@c except in smallbook.  See comments below "@set SMALL" near top of this file.
-
-The following table summarizes H8/500 opcodes and their operands:
-
-@c Use @group if it ever works, instead of @page
-@page
-@smallexample
-@i{Legend:}
-abs8      @r{8-bit absolute address}
-abs16     @r{16-bit absolute address}
-abs24     @r{24-bit absolute address}
-crb       @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}}
-disp8     @r{8-bit displacement}
-ea        @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
-          @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},}
-          @r{@code{#xx:8}, @code{#xx:16}}
-ea_mem    @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
-          @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-ea_noimm  @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
-          @r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
-fp        r6
-imm4      @r{4-bit immediate data}
-imm8      @r{8-bit immediate data}
-imm16     @r{16-bit immediate data}
-pcrel8    @r{8-bit offset from program counter}
-pcrel16   @r{16-bit offset from program counter}
-qim       @r{@code{-2}, @code{-1}, @code{1}, @code{2}}
-rd        @r{any register}
-rs        @r{a register distinct from rd}
-rlist     @r{comma-separated list of registers in parentheses;}
-          @r{register ranges @code{rd-rs} are allowed}
-sp        @r{stack pointer (@code{r7})}
-sr        @r{status register}
-sz        @r{size; @samp{.b} or @samp{.w}.  If omitted, default @samp{.w}}
-
-ldc[.b] ea,crb                 bcc[.w] pcrel16
-ldc[.w] ea,sr                  bcc[.b] pcrel8 
-add[:q] sz qim,ea_noimm        bhs[.w] pcrel16
-add[:g] sz ea,rd               bhs[.b] pcrel8 
-adds sz ea,rd                  bcs[.w] pcrel16
-addx sz ea,rd                  bcs[.b] pcrel8 
-and sz ea,rd                   blo[.w] pcrel16
-andc[.b] imm8,crb              blo[.b] pcrel8 
-andc[.w] imm16,sr              bne[.w] pcrel16
-bpt                            bne[.b] pcrel8 
-bra[.w] pcrel16                beq[.w] pcrel16
-bra[.b] pcrel8                 beq[.b] pcrel8 
-bt[.w] pcrel16                 bvc[.w] pcrel16
-bt[.b] pcrel8                  bvc[.b] pcrel8 
-brn[.w] pcrel16                bvs[.w] pcrel16
-brn[.b] pcrel8                 bvs[.b] pcrel8 
-bf[.w] pcrel16                 bpl[.w] pcrel16
-bf[.b] pcrel8                  bpl[.b] pcrel8 
-bhi[.w] pcrel16                bmi[.w] pcrel16
-bhi[.b] pcrel8                 bmi[.b] pcrel8 
-bls[.w] pcrel16                bge[.w] pcrel16
-bls[.b] pcrel8                 bge[.b] pcrel8 
-@page
-blt[.w] pcrel16                mov[:g][.b] imm8,ea_mem       
-blt[.b] pcrel8                 mov[:g][.w] imm16,ea_mem      
-bgt[.w] pcrel16                movfpe[.b] ea,rd              
-bgt[.b] pcrel8                 movtpe[.b] rs,ea_noimm        
-ble[.w] pcrel16                mulxu sz ea,rd                
-ble[.b] pcrel8                 neg sz ea                     
-bclr sz imm4,ea_noimm          nop                           
-bclr sz rs,ea_noimm            not sz ea                     
-bnot sz imm4,ea_noimm          or sz ea,rd                   
-bnot sz rs,ea_noimm            orc[.b] imm8,crb              
-bset sz imm4,ea_noimm          orc[.w] imm16,sr              
-bset sz rs,ea_noimm            pjmp abs24                    
-bsr[.b] pcrel8                 pjmp @@rd                     
-bsr[.w] pcrel16                pjsr abs24                    
-btst sz imm4,ea_noimm          pjsr @@rd                     
-btst sz rs,ea_noimm            prtd imm8                     
-clr sz ea                      prtd imm16                    
-cmp[:e][.b] imm8,rd            prts                          
-cmp[:i][.w] imm16,rd           rotl sz ea                    
-cmp[:g].b imm8,ea_noimm        rotr sz ea                    
-cmp[:g][.w] imm16,ea_noimm     rotxl sz ea                   
-Cmp[:g] sz ea,rd               rotxr sz ea                   
-dadd rs,rd                     rtd imm8                     
-divxu sz ea,rd                 rtd imm16                    
-dsub rs,rd                     rts                          
-exts[.b] rd                    scb/f rs,pcrel8               
-extu[.b] rd                    scb/ne rs,pcrel8             
-jmp @@rd                        scb/eq rs,pcrel8             
-jmp @@(imm8,rd)                 shal sz ea                   
-jmp @@(imm16,rd)                shar sz ea                    
-jmp abs16                      shll sz ea            
-jsr @@rd                        shlr sz ea            
-jsr @@(imm8,rd)                 sleep                 
-jsr @@(imm16,rd)                stc[.b] crb,ea_noimm  
-jsr abs16                      stc[.w] sr,ea_noimm   
-ldm @@sp+,(rlist)               stm (rlist),@@-sp     
-link fp,imm8                   sub sz ea,rd          
-link fp,imm16                  subs sz ea,rd         
-mov[:e][.b] imm8,rd            subx sz ea,rd         
-mov[:i][.w] imm16,rd           swap[.b] rd           
-mov[:l][.w] abs8,rd            tas[.b] ea     
-mov[:l].b abs8,rd              trapa imm4     
-mov[:s][.w] rs,abs8            trap/vs        
-mov[:s].b rs,abs8              tst sz ea      
-mov[:f][.w] @@(disp8,fp),rd     unlk fp        
-mov[:f][.w] rs,@@(disp8,fp)     xch[.w] rs,rd 
-mov[:f].b @@(disp8,fp),rd       xor sz ea,rd   
-mov[:f].b rs,@@(disp8,fp)       xorc.b imm8,crb
-mov[:g] sz rs,ea_mem           xorc.w imm16,sr
-mov[:g] sz ea,rd              
-@end smallexample
-@end ifset
diff --git a/gas/doc/c-hppa.texi b/gas/doc/c-hppa.texi
index 7e9ea3082da3..9970188ab4f7 100644
--- a/gas/doc/c-hppa.texi
+++ b/gas/doc/c-hppa.texi
@@ -245,14 +245,51 @@ identified by keywords.  The keywords recognized are @samp{quad=@var{expr}}
 beginning of this subsection; a power of two), @samp{access=@var{expr}} (value
 for ``access rights'' field), @samp{sort=@var{expr}} (sorting order for this
 subspace in link), @samp{code_only} (subsection contains only code),
-@samp{unloadable} (subsection cannot be loaded into memory), @samp{common}
-(subsection is common block), @samp{dup_comm} (initialized data may have
-duplicate names), or @samp{zero} (subsection is all zeros, do not write in
-object file).
+@samp{unloadable} (subsection cannot be loaded into memory), @samp{comdat}
+(subsection is comdat), @samp{common} (subsection is common block),
+@samp{dup_comm} (subsection may have duplicate names), or @samp{zero}
+(subsection is all zeros, do not write in object file).
 
 @code{.nsubspa} always creates a new subspace with the given name, even
 if one with the same name already exists.
 
+@samp{comdat}, @samp{common} and @samp{dup_comm} can be used to implement
+various flavors of one-only support when using the SOM linker.  The SOM
+linker only supports specific combinations of these flags.  The details
+are not documented.  A brief description is provided here.
+
+@samp{comdat} provides a form of linkonce support.  It is useful for
+both code and data subspaces.  A @samp{comdat} subspace has a key symbol
+marked by the @samp{is_comdat} flag or @samp{ST_COMDAT}.  Only the first
+subspace for any given key is selected.  The key symbol becomes universal
+in shared links.  This is similar to the behavior of @samp{secondary_def}
+symbols.
+
+@samp{common} provides Fortran named common support.  It is only useful
+for data subspaces.  Symbols with the flag @samp{is_common} retain this
+flag in shared links.  Referencing a @samp{is_common} symbol in a shared
+library from outside the library doesn't work.  Thus, @samp{is_common}
+symbols must be output whenever they are needed.
+
+@samp{common} and @samp{dup_comm} together provide Cobol common support.
+The subspaces in this case must all be the same length.  Otherwise, this
+support is similar to the Fortran common support.
+
+@samp{dup_comm} by itself provides a type of one-only support for code.
+Only the first @samp{dup_comm} subspace is selected.  There is a rather
+complex algorithm to compare subspaces.  Code symbols marked with the
+@samp{dup_common} flag are hidden.  This support was intended for "C++
+duplicate inlines".
+
+A simplified technique is used to mark the flags of symbols based on
+the flags of their subspace.  A symbol with the scope SS_UNIVERSAL and
+type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding
+settings of @samp{comdat}, @samp{common} and @samp{dup_comm} from the
+subspace, respectively.  This avoids having to introduce additional
+directives to mark these symbols.  The HP assembler sets @samp{is_common}
+from @samp{common}.  However, it doesn't set the @samp{dup_common} from
+@samp{dup_comm}.  It doesn't have @samp{comdat} support.
+
 @item .version "@var{str}"
 Write @var{str} as version identifier in object code.
 @end table
diff --git a/gas/doc/c-i370.texi b/gas/doc/c-i370.texi
index 0c28f4432c34..401d07e1ef5c 100644
--- a/gas/doc/c-i370.texi
+++ b/gas/doc/c-i370.texi
@@ -1,4 +1,4 @@
-@c Copyright 2000 Free Software Foundation, Inc.
+@c Copyright 2000, 2002 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index f0047f93825a..81039c4dbe72 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -1,4 +1,5 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000,
+@c 2001, 2003, 2004
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -66,6 +67,15 @@ usage and use x86-64 as target platform).
 By default, x86 GAS replaces multiple nop instructions used for
 alignment within code sections with multi-byte nop instructions such
 as leal 0(%esi,1),%esi.  This switch disables the optimization.
+
+@cindex @samp{--divide} option, i386
+@item --divide
+On SVR4-derived platforms, the character @samp{/} is treated as a comment
+character, which means that it cannot be used in expressions.  The
+@samp{--divide} option turns @samp{/} into a normal character.  This does
+not disable @samp{/} at the beginning of a line starting a comment, or
+affect using @samp{#} for starting a comment.
+
 @end table
 
 @node i386-Syntax
@@ -227,7 +237,7 @@ The Intel-syntax conversion instructions
 (x86-64 only),
 
 @item
-@samp{cdo} --- sign-extend quad in @samp{%rax} to octuple in
+@samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
 @samp{%rdx:%rax} (x86-64 only),
 @end itemize
 
@@ -691,15 +701,16 @@ register is @samp{%st(i)}.
 @cindex x86-64 arch directive
 
 @code{@value{AS}} may be told to assemble for a particular CPU
-architecture with the @code{.arch @var{cpu_type}} directive.  This
+(sub-)architecture with the @code{.arch @var{cpu_type}} directive.  This
 directive enables a warning when gas detects an instruction that is not
 supported on the CPU specified.  The choices for @var{cpu_type} are:
 
 @multitable @columnfractions .20 .20 .20 .20
 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
-@item @samp{pentiumpro} @tab @samp{pentium4} @tab @samp{k6} @tab @samp{athlon}
-@item @samp{sledgehammer}
+@item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
+@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer}
+@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow}
 @end multitable
 
 Apart from the warning, there are only two other effects on
@@ -715,13 +726,14 @@ conditional jumps will be promoted when necessary to a two instruction
 sequence consisting of a conditional jump of the opposite sense around
 an unconditional jump to the target.
 
-Following the CPU architecture, you may specify @samp{jumps} or
-@samp{nojumps} to control automatic promotion of conditional jumps.
-@samp{jumps} is the default, and enables jump promotion;  All external
-jumps will be of the long variety, and file-local jumps will be promoted
-as necessary.  (@pxref{i386-Jumps})  @samp{nojumps} leaves external
-conditional jumps as byte offset jumps, and warns about file-local
-conditional jumps that @code{@value{AS}} promotes.
+Following the CPU architecture (but not a sub-architecture, which are those
+starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
+control automatic promotion of conditional jumps. @samp{jumps} is the
+default, and enables jump promotion;  All external jumps will be of the long
+variety, and file-local jumps will be promoted as necessary.
+(@pxref{i386-Jumps})  @samp{nojumps} leaves external conditional jumps as
+byte offset jumps, and warns about file-local conditional jumps that
+@code{@value{AS}} promotes.
 Unconditional jumps are treated as for @samp{jumps}.
 
 For example
diff --git a/gas/doc/c-i960.texi b/gas/doc/c-i960.texi
index dad2fc4ecbc3..5dca1cf9c111 100644
--- a/gas/doc/c-i960.texi
+++ b/gas/doc/c-i960.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 2002
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
diff --git a/gas/doc/c-ia64.texi b/gas/doc/c-ia64.texi
index b62c05eb88d0..6b0f3a9515d7 100644
--- a/gas/doc/c-ia64.texi
+++ b/gas/doc/c-ia64.texi
@@ -1,4 +1,4 @@
-@c Copyright 2002
+@c Copyright 2002, 2003, 2005
 @c Free Software Foundation, Inc.
 @c   Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 @c This is part of the GAS manual.
@@ -65,19 +65,49 @@ These options select the byte order.  The @code{-mle} option selects little-endi
 byte order (default) and @code{-mbe} selects big-endian byte order.  Note that
 IA-64 machine code always uses little-endian byte order.
 
+@item -mtune=itanium1
+@item -mtune=itanium2
+Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The
+default is @var{itanium2}.
+
+@item -munwind-check=warning
+@item -munwind-check=error
+These options control what the assembler will do when performing
+consistency checks on unwind directives.  @code{-munwind-check=warning}
+will make the assembler issue a warning when an unwind directive check
+fails.  This is the default.  @code{-munwind-check=error} will make the
+assembler issue an error when an unwind directive check fails.
+
+@item -mhint.b=ok
+@item -mhint.b=warning
+@item -mhint.b=error
+These options control what the assembler will do when the @samp{hint.b}
+instruction is used.  @code{-mhint.b=ok} will make the assembler accept
+@samp{hint.b}.  @code{-mint.b=warning} will make the assembler issue a
+warning when @samp{hint.b} is used.  @code{-mhint.b=error} will make
+the assembler treat @samp{hint.b} as an error, which is the default.
+
 @item -x
 @item -xexplicit
-These options turn on dependency violation checking.  This checking is turned on by
-default.
+These options turn on dependency violation checking.
 
 @item -xauto
 This option instructs the assembler to automatically insert stop bits where necessary
-to remove dependency violations.
+to remove dependency violations.  This is the default mode.
+
+@item -xnone
+This option turns off dependency violation checking.
 
 @item -xdebug
 This turns on debug output intended to help tracking down bugs in the dependency
 violation checker.
 
+@item -xdebugn
+This is a shortcut for -xnone -xdebug.
+
+@item -xdebugx
+This is a shortcut for -xexplicit -xdebug.
+
 @end table
 
 @cindex IA-64 Syntax
@@ -90,7 +120,7 @@ Reference Guide.
 * IA-64-Chars::                Special Characters
 * IA-64-Regs::                 Register Names
 * IA-64-Bits::                 Bit Names
-* IA-64-Relocs::               Relocations
+@c * IA-64-Relocs::               Relocations		// to be written
 @end menu
 
 @node IA-64-Chars
@@ -136,7 +166,7 @@ the end-of-interrupt register (@samp{cr67}).
 The assembler defines bit masks for each of the bits in the IA-64
 processor status register.  For example, @samp{psr.ic} corresponds to
 a value of 0x2000.  These masks are primarily intended for use with
-the @sample{ssm}/@sample{sum} and @sample{rsm}/@sample{rum}
+the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum}
 instructions, but they can be used anywhere else where an integer
 constant is expected.
 
diff --git a/gas/doc/c-m32c.texi b/gas/doc/c-m32c.texi
new file mode 100644
index 000000000000..a49fe20b9d4e
--- /dev/null
+++ b/gas/doc/c-m32c.texi
@@ -0,0 +1,116 @@
+@c Copyright 2005
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+@ifset GENERIC
+@page
+@node M32C-Dependent
+@chapter M32C Dependent Features
+@end ifset
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter M32C Dependent Features
+@end ifclear
+ 
+@cindex M32C support
+
+@code{@value{AS}} can assemble code for several different members of
+the Renesas M32C family.  Normally the default is to assemble code for
+the M16C microprocessor.  The @code{-m32c} option may be used to
+change the default to the M32C microprocessor.
+
+@menu
+* M32C-Opts::                   M32C Options
+* M32C-Modifiers::              Symbolic Operand Modifiers
+@end menu
+ 
+@node M32C-Opts
+@section M32C Options
+ 
+@cindex options, M32C
+@cindex M32C options
+ 
+The Renesas M32C version of @code{@value{AS}} has two
+machine-dependent options:
+ 
+@table @code
+@item -m32c
+@cindex @samp{-m32c} option, M32C
+@cindex architecture options, M32C
+@cindex M32C architecture option
+Assemble M32C instructions.
+ 
+@item -m16c
+@cindex @samp{-m16c} option, M16C
+@cindex architecture options, M16C
+@cindex M16C architecture option
+Assemble M16C instructions (default).
+ 
+@end table
+
+@node M32C-Modifiers
+@section Symbolic Operand Modifiers
+
+@cindex M32C modifiers
+@cindex syntax, M32C
+
+The assembler supports several modifiers when using symbol addresses
+in M32C instruction operands.  The general syntax is the following:
+
+@smallexample
+%modifier(symbol)
+@end smallexample
+
+@table @code
+@cindex symbol modifiers
+
+@item %dsp8
+@itemx %dsp16
+
+These modifiers override the assembler's assumptions about how big a
+symbol's address is.  Normally, when it sees an operand like
+@samp{sym[a0]} it assumes @samp{sym} may require the widest
+displacement field (16 bits for @samp{-m16c}, 24 bits for
+@samp{-m32c}).  These modifiers tell it to assume the address will fit
+in an 8 or 16 bit (respectively) unsigned displacement.  Note that, of
+course, if it doesn't actually fit you will get linker errors.  Example:
+
+@smallexample
+mov.w %dsp8(sym)[a0],r1
+mov.b #0,%dsp8(sym)[a0]
+@end smallexample
+
+@item %hi8
+
+This modifier allows you to load bits 16 through 23 of a 24 bit
+address into an 8 bit register.  This is useful with, for example, the
+M16C @samp{smovf} instruction, which expects a 20 bit address in
+@samp{r1h} and @samp{a0}.  Example:
+
+@smallexample
+mov.b #%hi8(sym),r1h
+mov.w #%lo16(sym),a0
+smovf.b
+@end smallexample
+
+@item %lo16
+
+Likewise, this modifier allows you to load bits 0 through 15 of a 24
+bit address into a 16 bit register.
+
+@item %hi16
+
+This modifier allows you to load bits 16 through 31 of a 32 bit
+address into a 16 bit register.  While the M32C family only has 24
+bits of address space, it does support addresses in pairs of 16 bit
+registers (like @samp{a1a0} for the @samp{lde} instruction).  This
+modifier is for loading the upper half in such cases.  Example:
+
+@smallexample
+mov.w #%hi16(sym),a1
+mov.w #%lo16(sym),a0
+@dots{}
+lde.w [a1a0],r1
+@end smallexample
+
+@end table
diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi
index 4360ee6156fd..30cd355aede3 100644
--- a/gas/doc/c-m32r.texi
+++ b/gas/doc/c-m32r.texi
@@ -1,4 +1,5 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2003
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+@c 2000, 2003, 2004
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -91,6 +92,12 @@ do so.
 @cindex @code{-no-parallel} option, M32RX
 This option disables a previously enabled @emph{-parallel} option.
 
+@item -no-bitinst
+@cindex @samp{-no-bitinst}, M32R2
+This option disables the support for the extended bit-field
+instructions provided by the M32R2.  If this support needs to be
+re-enabled the @emph{-bitinst} switch can be used to restore it.
+
 @item -O
 @cindex @code{-O} option, M32RX
 This option tells the assembler to attempt to optimize the
diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi
index 8e2ba0004b90..a41d6fcac07d 100644
--- a/gas/doc/c-m68hc11.texi
+++ b/gas/doc/c-m68hc11.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi
index cafad4d59e6f..d4da2a1ea452 100644
--- a/gas/doc/c-m68k.texi
+++ b/gas/doc/c-m68k.texi
@@ -1,5 +1,5 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003
-@c Free Software Foundation, Inc.
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003,
+@c 2004 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -32,6 +32,50 @@ dependent options:
 
 @table @samp
 
+@cindex @samp{-march=} command line option, M680x0
+@item -march=@var{architecture}
+This option specifies a target architecture.  The following
+architectures are recognized:
+@code{68000},
+@code{68010},
+@code{68020},
+@code{68030},
+@code{68040},
+@code{68060},
+@code{cpu32},
+@code{isaa},
+@code{isaaplus},
+@code{isab} and
+@code{cfv4e}.
+
+
+@cindex @samp{-mcpu=} command line option, M680x0
+@item -mcpu=@var{cpu}
+This option specifies a target cpu.  When used in conjunction with the
+@option{-march} option, the cpu must be within the specified
+architecture.  Also, the generic features of the architecture are used
+for instruction generation, rather than those of the specific chip.
+
+@cindex @samp{-m[no-]68851} command line option, M680x0
+@cindex @samp{-m[no-]68881} command line option, M680x0
+@cindex @samp{-m[no-]div} command line option, M680x0
+@cindex @samp{-m[no-]usp} command line option, M680x0
+@cindex @samp{-m[no-]float} command line option, M680x0
+@cindex @samp{-m[no-]mac} command line option, M680x0
+@cindex @samp{-m[no-]emac} command line option, M680x0
+@item -m[no-]68851
+@item -m[no-]68881
+@item -m[no-]div
+@item -m[no-]usp
+@item -m[no-]float
+@item -m[no-]mac
+@item -m[no-]emac
+
+Enable or disable various architecture specific features.  If a chip
+or architecture by default supports an option (for instance
+@option{-march=isaaplus} includes the @option{-mdiv} option),
+explicitly disabling the option will override the default.
+
 @cindex @samp{-l} option, M680x0
 @item -l
 You can use the @samp{-l} option to shorten the size of references to undefined
@@ -169,9 +213,13 @@ Assemble for the CPU32 family of chips.
 @item -m5204
 @item -m5206
 @item -m5206e
+@item -m521x
+@item -m5249
 @item -m528x
 @item -m5307
 @item -m5407
+@item -m547x
+@item -m548x
 @item -mcfv4
 @item -mcfv4e
 Assemble for the ColdFire family of chips.
@@ -394,6 +442,25 @@ aligns the output to an even byte boundary.
 @cindex @code{skip} directive, M680x0
 @item .skip
 This directive is identical to a @code{.space} directive.
+
+@cindex @code{arch} directive, M680x0
+@item .arch @var{name}
+Select the target architecture and extension features.  Valid valuse
+for @var{name} are the same as for the @option{-march} command line
+option.  This directive cannot be specified after
+any instructions have been assembled.  If it is given multiple times,
+or in conjuction with the @option{-march} option, all uses must be for
+the same architecture and extension set.
+
+@cindex @code{cpu} directive, M680x0
+@item .cpu @var{name}
+Select the target cpu.  Valid valuse
+for @var{name} are the same as for the @option{-mcpu} command line
+option.  This directive cannot be specified after
+any instructions have been assembled.  If it is given multiple times,
+or in conjuction with the @option{-mopt} option, all uses must be for
+the same cpu.
+
 @end table
 
 @need 2000
diff --git a/gas/doc/c-m88k.texi b/gas/doc/c-m88k.texi
deleted file mode 100644
index c7bdb26148c2..000000000000
--- a/gas/doc/c-m88k.texi
+++ /dev/null
@@ -1,66 +0,0 @@
-@c Copyright 2001 Free Software Foundation, Inc.
-@c This is part of the GAS manual.
-@c For copying conditions, see the file as.texinfo.
-@page
-@node M88K-Dependent
-@chapter Motorola M88K Dependent Features
-
-@cindex M88K support
-@menu
-* M88K Directives::     M88K Machine Directives
-@end menu
-
-@node M88K Directives
-@section M88K Machine Directives
-
-The M88K version of the assembler supports the following machine
-directives:
-
-@table @code
-@cindex @code{align} directive, M88K
-@item .align
-This directive aligns the section program counter on the next 4-byte
-boundary.
-
-@cindex @code{dfloat} directive, M88K
-@item .dfloat @var{expr}
-This assembles a double precision (64-bit) floating point constant.
-
-@cindex @code{ffloat} directive, M88K
-@item .ffloat @var{expr}
-This assembles a single precision (32-bit) floating point constant.
-
-@cindex @code{half} directive, M88K
-@item .half @var{expr}
-This directive assembles a half-word (16-bit) constant.
-
-@cindex @code{word} directive, M88K
-@item .word @var{expr}
-This assembles a word (32-bit) constant.
-
-@cindex @code{string} directive, M88K
-@item .string "@var{str}"
-This directive behaves like the standard @code{.ascii} directive for
-copying @var{str} into the object file.  The string is not terminated
-with a null byte.
-
-@cindex @code{set} directive, M88K
-@item .set @var{symbol}, @var{value}
-This directive creates a symbol named @var{symbol} which is an alias for
-another symbol (possibly not yet defined).  This should not be confused
-with the mnemonic @code{set}, which is a legitimate M88K instruction.
-
-@cindex @code{def} directive, M88K
-@item .def @var{symbol}, @var{value}
-This directive is synonymous with @code{.set} and is presumably provided
-for compatibility with other M88K assemblers.
-
-@cindex @code{bss} directive, M88K
-@item .bss @var{symbol}, @var{length}, @var{align}
-Reserve @var{length} bytes in the bss section for a local @var{symbol},
-aligned to the power of two specified by @var{align}.  @var{length} and
-@var{align} must be positive absolute expressions.  This directive
-differs from @samp{.lcomm} only in that it permits you to specify
-an alignment.  @xref{Lcomm,,@code{.lcomm}}.
-
-@end table
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 1375230a673b..3c70ff29bc08 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -26,6 +26,7 @@ Assembly Language Programming'' in the same work.
 * MIPS Object:: 	ECOFF object code
 * MIPS Stabs::  	Directives for debugging information
 * MIPS ISA::    	Directives to override the ISA level
+* MIPS symbol sizes::   Directives to override the size of symbols
 * MIPS autoextend::	Directives for extending MIPS 16 bit instructions
 * MIPS insn::		Directive to mark data as an instruction
 * MIPS option stack::	Directives to save and restore options
@@ -117,6 +118,18 @@ Generate code for the MDMX Application Specific Extension.
 This tells the assembler to accept MDMX instructions.
 @samp{-no-mdmx} turns off this option.
 
+@item -mdsp
+@itemx -mno-dsp
+Generate code for the DSP Application Specific Extension.
+This tells the assembler to accept DSP instructions.
+@samp{-mno-dsp} turns off this option.
+
+@item -mmt
+@itemx -mno-mt
+Generate code for the MT Application Specific Extension.
+This tells the assembler to accept MT instructions.
+@samp{-mno-mt} turns off this option.
+
 @item -mfix7000
 @itemx -mno-fix7000
 Cause nops to be inserted if the read of the destination register
@@ -128,6 +141,10 @@ Insert nops to work around certain VR4120 errata.  This option is
 intended to be used on GCC-generated code: it is not designed to catch
 all problems in hand-written assembler code.
 
+@item -mfix-vr4130
+@itemx -no-mfix-vr4130
+Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
+
 @item -m4010
 @itemx -no-m4010
 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
@@ -197,6 +214,13 @@ identical to @samp{-march=@var{cpu}}.
 Record which ABI the source code uses.  The recognized arguments
 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
 
+@item -msym32
+@itemx -mno-sym32
+@cindex -msym32
+@cindex -mno-sym32
+Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
+the beginning of the assembler input.  @xref{MIPS symbol sizes}.
+
 @cindex @code{-nocpp} ignored (MIPS)
 @item -nocpp
 This option is ignored.  It is accepted for command-line compatibility with
@@ -238,6 +262,16 @@ error is detected.  This is the default.
 @itemx -mno-pdr
 Control generation of @code{.pdr} sections.  Off by default on IRIX, on
 elsewhere.
+
+@item -mshared
+@itemx -mno-shared
+When generating code using the Unix calling conventions (selected by
+@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
+which can go into a shared library.  The @samp{-mno-shared} option
+tells gas to generate code which uses the calling convention, but can
+not go into a shared library.  The resulting code is slightly more
+efficient.  This option only affects the handling of the
+@samp{.cpload} and @samp{.cpsetup} pseudo-ops.
 @end table
 
 @node MIPS Object
@@ -287,6 +321,61 @@ not by traditional @sc{mips} debuggers (this enhancement is required to fully
 support C++ debugging).  These directives are primarily used by compilers, not
 assembly language programmers!
 
+@node MIPS symbol sizes
+@section Directives to override the size of symbols
+
+@cindex @code{.set sym32}
+@cindex @code{.set nosym32}
+The n64 ABI allows symbols to have any 64-bit value.  Although this
+provides a great deal of flexibility, it means that some macros have
+much longer expansions than their 32-bit counterparts.  For example,
+the non-PIC expansion of @samp{dla $4,sym} is usually:
+
+@smallexample
+lui     $4,%highest(sym)
+lui     $1,%hi(sym)
+daddiu  $4,$4,%higher(sym)
+daddiu  $1,$1,%lo(sym)
+dsll32  $4,$4,0
+daddu   $4,$4,$1
+@end smallexample
+
+whereas the 32-bit expansion is simply:
+
+@smallexample
+lui     $4,%hi(sym)
+daddiu  $4,$4,%lo(sym)
+@end smallexample
+
+n64 code is sometimes constructed in such a way that all symbolic
+constants are known to have 32-bit values, and in such cases, it's
+preferable to use the 32-bit expansion instead of the 64-bit
+expansion.
+
+You can use the @code{.set sym32} directive to tell the assembler
+that, from this point on, all expressions of the form
+@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
+have 32-bit values.  For example:
+
+@smallexample
+.set sym32
+dla     $4,sym
+lw      $4,sym+16
+sw      $4,sym+0x8000($4)
+@end smallexample
+
+will cause the assembler to treat @samp{sym}, @code{sym+16} and
+@code{sym+0x8000} as 32-bit values.  The handling of non-symbolic
+addresses is not affected.
+
+The directive @code{.set nosym32} ends a @code{.set sym32} block and
+reverts to the normal behavior.  It is also possible to change the
+symbol size using the command-line options @option{-msym32} and
+@option{-mno-sym32}.
+
+These options and directives are always accepted, but at present,
+they have no effect for anything other than n64.
+
 @node MIPS ISA
 @section Directives to override the ISA level
 
@@ -374,4 +463,20 @@ from the MDMX Application Specific Extension from that point on
 in the assembly.  The @code{.set nomdmx} directive prevents MDMX
 instructions from being accepted.
 
+@cindex MIPS DSP instruction generation override
+@kindex @code{.set dsp}
+@kindex @code{.set nodsp}
+The directive @code{.set dsp} makes the assembler accept instructions
+from the DSP Application Specific Extension from that point on
+in the assembly.  The @code{.set nodsp} directive prevents DSP
+instructions from being accepted.
+
+@cindex MIPS MT instruction generation override
+@kindex @code{.set mt}
+@kindex @code{.set nomt}
+The directive @code{.set mt} makes the assembler accept instructions
+from the MT Application Specific Extension from that point on
+in the assembly.  The @code{.set nomt} directive prevents MT
+instructions from being accepted.
+
 Traditional @sc{mips} assemblers do not support these directives.
diff --git a/gas/doc/c-mmix.texi b/gas/doc/c-mmix.texi
index a31fa83e0dd3..8e47fa4a9799 100644
--- a/gas/doc/c-mmix.texi
+++ b/gas/doc/c-mmix.texi
@@ -1,4 +1,4 @@
-@c Copyright 2001, 2002 Free Software Foundation, Inc.
+@c Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c MMIX description by Hans-Peter Nilsson, hp@bitrange.com
diff --git a/gas/doc/c-msp430.texi b/gas/doc/c-msp430.texi
index 00503598538d..33f3e83ffbc1 100644
--- a/gas/doc/c-msp430.texi
+++ b/gas/doc/c-msp430.texi
@@ -1,4 +1,4 @@
-@c Copyright 2002 Free Software Foundation, Inc.
+@c Copyright 2002, 2004 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
@@ -19,14 +19,24 @@
 * MSP430 Floating Point::       Floating Point
 * MSP430 Directives::           MSP 430 Machine Directives
 * MSP430 Opcodes::              Opcodes
+* MSP430 Profiling Capability::	Profiling Capability
 @end menu
 
 @node MSP430 Options
 @section Options
 @cindex MSP 430 options (none)
 @cindex options for MSP430 (none)
-@code{@value{AS}} has only -m flag which selects the mpu arch. Currently has 
-no effect.
+@table @code
+
+@item -m
+select the mpu arch. Currently has no effect.
+@item -mP 
+enables polymorph instructions handler.
+
+@item -mQ 
+enables relaxation at assembly time. DANGEROUS!
+
+@end table
 
 @node MSP430 Syntax
 @section Syntax
@@ -116,6 +126,54 @@ Skips next N bytes followed by jump instruction and equivalent to
 
 @end table
 
+Also, there are some instructions, which cannot be found in other assemblers.
+These are branch instructions, which has different opcodes upon jump distance.
+They all got PC relative addressing mode.
+
+@table @code
+@item	beq label
+A polymorph instruction which is @samp{jeq label} in case if jump distance
+within allowed range for cpu's jump instruction. If not, this unrolls into
+a sequence of
+@smallexample
+  jne $+6
+  br  label
+@end smallexample
+
+@item bne label
+A polymorph instruction which is @samp{jne label} or @samp{jeq +4; br label}
+
+@item blt label
+A polymorph instruction which is @samp{jl label} or @samp{jge +4; br label}
+
+@item bltn label
+A polymorph instruction which is @samp{jn label} or @samp{jn +2; jmp +4; br label}
+
+@item bltu label
+A polymorph instruction which is @samp{jlo label} or @samp{jhs +2; br label}
+
+@item bge label
+A polymorph instruction which is @samp{jge label} or @samp{jl +4; br label}
+
+@item bgeu label
+A polymorph instruction which is @samp{jhs label} or @samp{jlo +4; br label}
+
+@item bgt label
+A polymorph instruction which is @samp{jeq +2; jge label} or @samp{jeq +6; jl  +4; br label}
+
+@item bgtu label
+A polymorph instruction which is @samp{jeq +2; jhs label} or @samp{jeq +6; jlo +4; br label}
+
+@item bleu label
+A polymorph instruction which is @samp{jeq label; jlo label} or @samp{jeq +2; jhs +4; br label}
+
+@item ble label
+A polymorph instruction which is @samp{jeq label; jl  label} or @samp{jeq +2; jge +4; br label}
+
+@item jump label
+A polymorph instruction which is @samp{jmp label} or @samp{br label}
+@end table
+
 
 @node MSP430 Floating Point
 @section Floating Point
@@ -150,6 +208,10 @@ MSP 430 assemblers.
 Currently this directive is ignored; it is accepted for compatibility with other
 MSP 430 assemblers.
 
+@cindex @code{profiler} directive, MSP 430
+@item .profiler
+This directive instructs assembler to add new profile entry to the object file.
+
 @end table
 
 @node MSP430 Opcodes
@@ -161,4 +223,99 @@ MSP 430 assemblers.
 additional pseudo-instructions are needed on this family.
 
 For information on the 430 machine instruction set, see @cite{MSP430
-User's Manual, document slau049b}, Texas Instrument, Inc.
+User's Manual, document slau049d}, Texas Instrument, Inc.
+
+@node MSP430 Profiling Capability
+@section Profiling Capability
+
+@cindex MSP 430 profiling capability
+@cindex profiling capability for MSP 430
+It is a performance hit to use gcc's profiling approach for this tiny target.
+Even more -- jtag hardware facility does not perform any profiling functions.
+However we've got gdb's built-in simulator where we can do anything.
+
+We define new section @samp{.profiler} which holds all profiling information.
+We define new pseudo operation @samp{.profiler} which will instruct assembler to
+add new profile entry to the object file. Profile should take place at the
+present address.
+
+Pseudo operation format:
+
+@samp{.profiler flags,function_to_profile [, cycle_corrector, extra]}
+
+
+where:
+
+@table @code
+
+@table @code
+
+@samp{flags} is a combination of the following characters:
+
+@item  s 
+function entry
+@item  x  
+function exit
+@item  i  
+function is in init section
+@item  f  
+function is in fini section
+@item  l  
+library call
+@item  c  
+libc standard call
+@item  d  
+stack value demand
+@item  I  
+interrupt service routine
+@item  P  
+prologue start
+@item  p  
+prologue end
+@item  E  
+epilogue start
+@item  e  
+epilogue end
+@item  j  
+long jump / sjlj unwind
+@item  a  
+an arbitrary code fragment
+@item t
+extra parameter saved (a constant value like frame size)
+@end table
+
+@item function_to_profile 
+a function address
+@item cycle_corrector  
+a value which should be added to the cycle counter, zero if omitted.
+@item extra  
+any extra parameter, zero if omitted.
+
+@end table
+
+For example:
+@smallexample
+.global fxx
+.type fxx,@@function
+fxx:
+.LFrameOffset_fxx=0x08
+.profiler "scdP", fxx     ; function entry.
+			  ; we also demand stack value to be saved
+  push r11
+  push r10
+  push r9
+  push r8
+.profiler "cdpt",fxx,0, .LFrameOffset_fxx  ; check stack value at this point
+					  ; (this is a prologue end)
+					  ; note, that spare var filled with 
+					  ; the farme size
+  mov r15,r8
+...
+.profiler cdE,fxx         ; check stack
+  pop r8
+  pop r9
+  pop r10
+  pop r11
+.profiler xcde,fxx,3      ; exit adds 3 to the cycle counter
+  ret                     ; cause 'ret' insn takes 3 cycles
+@end smallexample
diff --git a/gas/doc/c-mt.texi b/gas/doc/c-mt.texi
new file mode 100644
index 000000000000..ca562742b6c7
--- /dev/null
+++ b/gas/doc/c-mt.texi
@@ -0,0 +1,44 @@
+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
+@c Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node MT-Dependent
+@chapter MT Dependent Features
+@end ifset
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter MS1 Dependent Features
+@end ifclear
+
+@cindex MT support
+@menu
+* MT Options::              Options
+@end menu
+
+@node MT Options
+@section Options
+@cindex MT options (none)
+@cindex options for MT (none)
+
+@table @code
+
+@cindex @code{-march=} command line option, MT
+@item -march=@var{processor}
+This option specifies the target processor.  The assembler will issue an
+error message if an attempt is made to assemble an instruction which
+will not execute on the target processor.  The following processor names are
+recognized: 
+@code{ms1-64-001},
+@code{ms1-16-002},
+@code{ms1-16-003},
+and @code{ms2}.
+
+@cindex @code{-nosched} command line option, MT
+@item -nosched
+This option disables scheduling restriction checking.
+
+@end table
diff --git a/gas/doc/c-ns32k.texi b/gas/doc/c-ns32k.texi
index a80075c6998b..e61353ab70aa 100644
--- a/gas/doc/c-ns32k.texi
+++ b/gas/doc/c-ns32k.texi
@@ -1,4 +1,5 @@
-@c  Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c Copyright 1991, 1992, 1993, 1994, 1995, 2002
+@c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
diff --git a/gas/doc/c-pdp11.texi b/gas/doc/c-pdp11.texi
index a9d9c8a42482..d714b28343a6 100644
--- a/gas/doc/c-pdp11.texi
+++ b/gas/doc/c-pdp11.texi
@@ -1,4 +1,4 @@
-@c Copyright 2001 Free Software Foundation, Inc.
+@c Copyright 2001, 2002 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
diff --git a/gas/doc/c-pj.texi b/gas/doc/c-pj.texi
index 76d38d20cf06..542fd13a09f2 100644
--- a/gas/doc/c-pj.texi
+++ b/gas/doc/c-pj.texi
@@ -1,4 +1,4 @@
-@c Copyright 1999 Free Software Foundation, Inc.
+@c Copyright 1999, 2002 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @page
diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi
index be90e336f8bd..4c9c096c055e 100644
--- a/gas/doc/c-ppc.texi
+++ b/gas/doc/c-ppc.texi
@@ -1,4 +1,4 @@
-@c Copyright 2001, 2002
+@c Copyright 2001, 2002, 2003, 2005
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -67,12 +67,18 @@ Generate code for 64-bit BookE.
 @item -mbooke, mbooke32
 Generate code for 32-bit BookE.
 
+@item -me300
+Generate code for PowerPC e300 family.
+
 @item -maltivec
 Generate code for processors with AltiVec instructions.
 
 @item -mpower4
 Generate code for Power4 architecture.
 
+@item -mpower5
+Generate code for Power5 architecture.
+
 @item -mcom
 Generate code Power/PowerPC common instructions.
 
diff --git a/gas/doc/c-sh.texi b/gas/doc/c-sh.texi
index b08f325ee08e..e6dbe4bf5c2c 100644
--- a/gas/doc/c-sh.texi
+++ b/gas/doc/c-sh.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2004
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, 2005
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -24,39 +24,43 @@
 (formerly Hitachi) / SuperH SH family.
 
 @table @code
-@kindex -little
-@kindex -big
-@kindex -relax
-@kindex -small
-@kindex -dsp
-@kindex -renesas
-
-@item -little
+@kindex --little
+@kindex --big
+@kindex --relax
+@kindex --small
+@kindex --dsp
+@kindex --renesas
+@kindex --allow-reg-prefix
+
+@item --little
 Generate little endian code.
 
-@item -big
+@item --big
 Generate big endian code.
 
-@item -relax
+@item --relax
 Alter jump instructions for long displacements.
 
-@item -small
+@item --small
 Align sections to 4 byte boundaries, not 16.
 
-@item -dsp
+@item --dsp
 Enable sh-dsp insns, and disable sh3e / sh4 insns.
 
-@item -renesas
+@item --renesas
 Disable optimization with section symbol for compatibility with
 Renesas assembler.
 
-@item -isa=sh4 | sh4a
+@item --allow-reg-prefix
+Allow '$' as a register name prefix.
+
+@item --isa=sh4 | sh4a
 Specify the sh4 or sh4a instruction set.
-@item -isa=dsp
+@item --isa=dsp
 Enable sh-dsp insns, and disable sh3e / sh4 insns.
-@item -isa=fp
+@item --isa=fp
 Enable sh2e, sh3e, sh4, and sh4a insn sets.
-@item -isa=all
+@item --isa=all
 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.
 
 @end table
diff --git a/gas/doc/c-sh64.texi b/gas/doc/c-sh64.texi
index 60681ee9208f..c38d14e0d8bb 100644
--- a/gas/doc/c-sh64.texi
+++ b/gas/doc/c-sh64.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2001, 2002 Free Software Foundation, Inc.
+@c Copyright (C) 2002, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @page
diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi
index c34950e13f7f..351b300b2f1a 100644
--- a/gas/doc/c-sparc.texi
+++ b/gas/doc/c-sparc.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
diff --git a/gas/doc/c-tic54x.texi b/gas/doc/c-tic54x.texi
index 77db23cb7617..374def39e633 100644
--- a/gas/doc/c-tic54x.texi
+++ b/gas/doc/c-tic54x.texi
@@ -1,4 +1,4 @@
-@c Copyright 1999, 2000 Free Software Foundation, Inc.
+@c Copyright 2000, 2002, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c TI TMS320C54X description by Timothy Wall, twall@cygnus.com
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 5fd4bacb2866..445be057ef35 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -1,4 +1,4 @@
-@c Copyright 1997, 2003 Free Software Foundation, Inc.
+@c Copyright 1997, 2002, 2003 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 
diff --git a/gas/doc/c-vax.texi b/gas/doc/c-vax.texi
index 59d82d2bbace..ac9a4ea700f2 100644
--- a/gas/doc/c-vax.texi
+++ b/gas/doc/c-vax.texi
@@ -1,4 +1,4 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998
+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2002
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
diff --git a/gas/doc/c-xc16x.texi b/gas/doc/c-xc16x.texi
new file mode 100644
index 000000000000..73866e466f7e
--- /dev/null
+++ b/gas/doc/c-xc16x.texi
@@ -0,0 +1,55 @@
+@c Copyright 2006 Free Software Foundation, Inc.
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@page
+@node xc16x-Dependent
+@chapter Infineon xc16x Dependent Features
+
+@cindex xc16x support
+@menu
+* xc16x Directives::     xc16x Machine Directives
+@end menu
+
+@node xc16x Directives
+@section xc16x Machine Directives
+
+The xc16x version of the assembler supports the following machine
+directives:
+
+@table @code
+@cindex @code{align} directive, xc16x
+@item .align
+This directive aligns the section program counter on the next 2-byte
+boundary.
+
+
+@cindex @code{byte} directive, xc16x
+@item .byte @var{expr}
+This directive assembles a half-word (8-bit) constant.
+
+@cindex @code{word} directive, xc16x
+@item .word @var{expr}
+This assembles a word (16-bit) constant.
+
+@cindex @code{ascii} directive, xc16x
+@item .ascii "@var{ascii}"
+This directive used for copying @var{str} into the object file. 
+The string is terminated with a null byte.
+
+@cindex @code{set} directive, xc16x
+@item .set @var{symbol}, @var{value}
+This directive creates a symbol named @var{symbol} which is an alias for
+another symbol (possibly not yet defined).  This should not be confused
+with the mnemonic @code{set}, which is a legitimate xc16x instruction.
+
+
+
+@cindex @code{bss} directive, xc16x
+@item .bss @var{symbol}, @var{length}
+Reserve @var{length} bytes in the bss section for a local @var{symbol},
+aligned to the power of two specified by @var{align}.  @var{length} and
+@var{align} must be positive absolute expressions.  This directive
+differs from @samp{.lcomm} only in that it permits you to specify
+an alignment.  
+@end table
diff --git a/gas/doc/c-xtensa.texi b/gas/doc/c-xtensa.texi
index 5e5f13aac8db..33035ad8b483 100644
--- a/gas/doc/c-xtensa.texi
+++ b/gas/doc/c-xtensa.texi
@@ -1,4 +1,4 @@
-@c Copyright (C) 2002 Free Software Foundation, Inc.
+@c Copyright (C) 2002, 2003, 2004 Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @c
@@ -33,54 +33,28 @@ The Xtensa version of the @sc{gnu} assembler supports these
 special options:
 
 @table @code
-@item --density | --no-density
-@kindex --density
-@kindex --no-density
-@cindex Xtensa density option
-@cindex density option, Xtensa
-Enable or disable use of the Xtensa code density option (16-bit
-instructions).  @xref{Density Instructions, ,Using Density
-Instructions}.  If the processor is configured with the density option,
-this is enabled by default; otherwise, it is always disabled.
-
-@item --relax | --no-relax
-@kindex --relax
-@kindex --no-relax
-Enable or disable relaxation of instructions with immediate operands
-that are outside the legal range for the instructions.  @xref{Xtensa
-Relaxation, ,Xtensa Relaxation}.  The default is @samp{--relax} and this
-default should almost always be used.  If relaxation is disabled with
-@samp{--no-relax}, instruction operands that are out of range will cause
-errors.  Note: In the current implementation, these options also control
-whether assembler optimizations are performed, making these options
-equivalent to @samp{--generics} and @samp{--no-generics}.
-
-@item --generics | --no-generics
-@kindex --generics
-@kindex --no-generics
-Enable or disable all assembler transformations of Xtensa instructions,
-including both relaxation and optimization.  The default is
-@samp{--generics}; @samp{--no-generics} should only be used in the rare
-cases when the instructions must be exactly as specified in the assembly
-source.
-@c The @samp{--no-generics} option is like @samp{--no-relax}
-@c except that it also disables assembler optimizations (@pxref{Xtensa
-@c Optimizations}).
-As with @samp{--no-relax}, using @samp{--no-generics}
-causes out of range instruction operands to be errors.
-
 @item --text-section-literals | --no-text-section-literals
 @kindex --text-section-literals
 @kindex --no-text-section-literals
 Control the treatment of literal pools.  The default is
 @samp{--no-@-text-@-section-@-literals}, which places literals in a
 separate section in the output file.  This allows the literal pool to be
-placed in a data RAM/ROM, and it also allows the linker to combine literal
-pools from separate object files to remove redundant literals and
-improve code size.  With @samp{--text-@-section-@-literals}, the
+placed in a data RAM/ROM.  With @samp{--text-@-section-@-literals}, the
 literals are interspersed in the text section in order to keep them as
 close as possible to their references.  This may be necessary for large
-assembly files.
+assembly files, where the literals would otherwise be out of range of the
+@code{L32R} instructions in the text section.  These options only affect
+literals referenced via PC-relative @code{L32R} instructions; literals
+for absolute mode @code{L32R} instructions are handled separately.
+
+@item --absolute-literals | --no-absolute-literals
+@kindex --absolute-literals
+@kindex --no-absolute-literals
+Indicate to the assembler whether @code{L32R} instructions use absolute
+or PC-relative addressing.  If the processor includes the absolute
+addressing option, the default is to use absolute @code{L32R}
+relocations.  Otherwise, only the PC-relative @code{L32R} relocations
+can be used.
 
 @item --target-align | --no-target-align
 @kindex --target-align
@@ -97,14 +71,32 @@ have fixed alignment requirements.
 Enable or disable transformation of call instructions to allow calls
 across a greater range of addresses.  @xref{Xtensa Call Relaxation,
 ,Function Call Relaxation}.  This option should be used when call
-targets can potentially be out of range, but it degrades both code size
-and performance.  The default is @samp{--no-@-longcalls}.
+targets can potentially be out of range.  It may degrade both code size
+and performance, but the linker can generally optimize away the
+unnecessary overhead when a call ends up within range.  The default is
+@samp{--no-@-longcalls}.
+
+@item --transform | --no-transform
+@kindex --transform
+@kindex --no-transform
+Enable or disable all assembler transformations of Xtensa instructions,
+including both relaxation and optimization.  The default is
+@samp{--transform}; @samp{--no-transform} should only be used in the
+rare cases when the instructions must be exactly as specified in the
+assembly source.  Using @samp{--no-transform} causes out of range
+instruction operands to be errors.
+
+@item --rename-section @var{oldname}=@var{newname}
+@kindex --rename-section
+Rename the @var{oldname} section to @var{newname}.  This option can be used
+multiple times to rename multiple sections.
 @end table
 
 @node Xtensa Syntax
 @section Assembler Syntax
 @cindex syntax, Xtensa assembler
 @cindex Xtensa assembler syntax
+@cindex FLIX syntax
 
 Block comments are delimited by @samp{/*} and @samp{*/}.  End of line
 comments may be introduced with either @samp{#} or @samp{//}.
@@ -113,11 +105,45 @@ Instructions consist of a leading opcode or macro name followed by
 whitespace and an optional comma-separated list of operands:
 
 @smallexample
-@var{opcode} [@var{operand},@dots{}]
+@var{opcode} [@var{operand}, @dots{}]
 @end smallexample
 
 Instructions must be separated by a newline or semicolon.
 
+FLIX instructions, which bundle multiple opcodes together in a single
+instruction, are specified by enclosing the bundled opcodes inside
+braces:
+
+@smallexample
+@{
+[@var{format}]
+@var{opcode0} [@var{operands}]
+@var{opcode1} [@var{operands}]
+@var{opcode2} [@var{operands}]
+@dots{}
+@}
+@end smallexample
+
+The opcodes in a FLIX instruction are listed in the same order as the
+corresponding instruction slots in the TIE format declaration.
+Directives and labels are not allowed inside the braces of a FLIX
+instruction.  A particular TIE format name can optionally be specified
+immediately after the opening brace, but this is usually unnecessary.
+The assembler will automatically search for a format that can encode the
+specified opcodes, so the format name need only be specified in rare
+cases where there is more than one applicable format and where it
+matters which of those formats is used.  A FLIX instruction can also be
+specified on a single line by separating the opcodes with semicolons:
+
+@smallexample
+@{ [@var{format};] @var{opcode0} [@var{operands}]; @var{opcode1} [@var{operands}]; @var{opcode2} [@var{operands}]; @dots{} @}
+@end smallexample
+
+The assembler can automatically bundle opcodes into FLIX instructions.
+It encodes the opcodes in order, one at a time,
+choosing the smallest format where each opcode can be encoded and
+filling unused instruction slots with no-ops.
+
 @menu
 * Xtensa Opcodes::              Opcode Naming Conventions.
 * Xtensa Registers::            Register Naming.
@@ -126,41 +152,30 @@ Instructions must be separated by a newline or semicolon.
 @node Xtensa Opcodes
 @subsection Opcode Names
 @cindex Xtensa opcode names
-@cindex opcode names, Xtenxa
+@cindex opcode names, Xtensa
 
 See the @cite{Xtensa Instruction Set Architecture (ISA) Reference
 Manual} for a complete list of opcodes and descriptions of their
 semantics.
 
-@cindex generic opcodes
-@cindex specific opcodes
 @cindex _ opcode prefix
-The Xtensa assembler distinguishes between @dfn{generic} and
-@dfn{specific} opcodes.  Specific opcodes correspond directly to Xtensa
-machine instructions.  Prefixing an opcode with an underscore character
-(@samp{_}) identifies it as a specific opcode.  Opcodes without a
-leading underscore are generic, which means the assembler is required to
-preserve their semantics but may not translate them directly to the
-specific opcodes with the same names.  Instead, the assembler may
-optimize a generic opcode and select a better instruction to use in its
-place (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}), or the
-assembler may relax the instruction to handle operands that are out of
-range for the corresponding specific opcode (@pxref{Xtensa Relaxation,
-,Xtensa Relaxation}).
-
-Only use specific opcodes when it is essential to select
-the exact machine instructions produced by the assembler.
-Using specific opcodes unnecessarily only makes the code less
-efficient, by disabling assembler optimization, and less flexible, by
-disabling relaxation.
+If an opcode name is prefixed with an underscore character (@samp{_}),
+@command{@value{AS}} will not transform that instruction in any way.  The
+underscore prefix disables both optimization (@pxref{Xtensa
+Optimizations, ,Xtensa Optimizations}) and relaxation (@pxref{Xtensa
+Relaxation, ,Xtensa Relaxation}) for that particular instruction.  Only
+use the underscore prefix when it is essential to select the exact
+opcode produced by the assembler.  Using this feature unnecessarily
+makes the code less efficient by disabling assembler optimization and
+less flexible by disabling relaxation.
 
 Note that this special handling of underscore prefixes only applies to
 Xtensa opcodes, not to either built-in macros or user-defined macros.
-When an underscore prefix is used with a macro (e.g., @code{_NOP}), it
+When an underscore prefix is used with a macro (e.g., @code{_MOV}), it
 refers to a different macro.  The assembler generally provides built-in
 macros both with and without the underscore prefix, where the underscore
 versions behave as if the underscore carries through to the instructions
-in the macros.  For example, @code{_NOP} expands to @code{_OR a1,a1,a1}.
+in the macros.  For example, @code{_MOV} may expand to @code{_MOV.N}@.
 
 The underscore prefix only applies to individual instructions, not to
 series of instructions.  For example, if a series of instructions have
@@ -168,7 +183,7 @@ underscore prefixes, the assembler will not transform the individual
 instructions, but it may insert other instructions between them (e.g.,
 to align a @code{LOOP} instruction).  To prevent the assembler from
 modifying a series of instructions as a whole, use the
-@code{no-generics} directive.  @xref{Generics Directive, ,generics}.
+@code{no-transform} directive.  @xref{Transform Directive, ,transform}.
 
 @node Xtensa Registers
 @subsection Register Names
@@ -176,20 +191,20 @@ modifying a series of instructions as a whole, use the
 @cindex register names, Xtensa
 @cindex sp register
 
-An initial @samp{$} character is optional in all register names.
-General purpose registers are named @samp{a0}@dots{}@samp{a15}.  Additional
-registers may be added by processor configuration options.  In
-particular, the @sc{mac16} option adds a @sc{mr} register bank.  Its
-registers are named @samp{m0}@dots{}@samp{m3}.
-
-As a special feature, @samp{sp} is also supported as a synonym for
-@samp{a1}.
+The assembly syntax for a register file entry is the ``short'' name for
+a TIE register file followed by the index into that register file.  For
+example, the general-purpose @code{AR} register file has a short name of
+@code{a}, so these registers are named @code{a0}@dots{}@code{a15}.
+As a special feature, @code{sp} is also supported as a synonym for
+@code{a1}.  Additional registers may be added by processor configuration
+options and by designer-defined TIE extensions.  An initial @samp{$}
+character is optional in all register names.
 
 @node Xtensa Optimizations
 @section Xtensa Optimizations
 @cindex optimizations
 
-The optimizations currently supported by @code{@value{AS}} are
+The optimizations currently supported by @command{@value{AS}} are
 generation of density instructions where appropriate and automatic
 branch target alignment.
 
@@ -205,18 +220,18 @@ branch target alignment.
 The Xtensa instruction set has a code density option that provides
 16-bit versions of some of the most commonly used opcodes.  Use of these
 opcodes can significantly reduce code size.  When possible, the
-assembler automatically translates generic instructions from the core
+assembler automatically translates instructions from the core
 Xtensa instruction set into equivalent instructions from the Xtensa code
-density option.  This translation can be disabled by using specific
-opcodes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
-@samp{--no-density} command-line option (@pxref{Xtensa Options, ,Command
-Line Options}), or by using the @code{no-density} directive
-(@pxref{Density Directive, ,density}).
+density option.  This translation can be disabled by using underscore
+prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), by using the
+@samp{--no-transform} command-line option (@pxref{Xtensa Options, ,Command
+Line Options}), or by using the @code{no-transform} directive
+(@pxref{Transform Directive, ,transform}).
 
 It is a good idea @emph{not} to use the density instructions directly.
 The assembler will automatically select dense instructions where
-possible.  If you later need to avoid using the code density option, you
-can disable it in the assembler without having to modify the code.
+possible.  If you later need to use an Xtensa processor without the code
+density option, the same assembly code will then work without modification.
 
 @node Xtensa Automatic Alignment
 @subsection Automatic Instruction Alignment
@@ -230,24 +245,42 @@ can disable it in the assembler without having to modify the code.
 The Xtensa assembler will automatically align certain instructions, both
 to optimize performance and to satisfy architectural requirements.
 
-When the @code{--target-@-align} command-line option is enabled
-(@pxref{Xtensa Options, ,Command Line Options}), the assembler attempts
-to widen density instructions preceding a branch target so that the
-target instruction does not cross a 4-byte boundary.  Similarly, the
-assembler also attempts to align each instruction following a call
-instruction.  If there are not enough preceding safe density
-instructions to align a target, no widening will be performed.  This
-alignment has the potential to reduce branch penalties at some expense
-in code size.  The assembler will not attempt to align labels with the
-prefixes @code{.Ln} and @code{.LM}, since these labels are used for
-debugging information and are not typically branch targets.
-
-The @code{LOOP} family of instructions must be aligned on either a 1 or
-2 mod 4 byte boundary.  The assembler knows about this restriction and
-inserts the minimal number of 2 or 3 byte no-op instructions
-to satisfy it.  When no-op instructions are added, any label immediately
-preceding the original loop will be moved in order to refer to the loop
-instruction, not the newly generated no-op instruction.
+As an optimization to improve performance, the assembler attempts to
+align branch targets so they do not cross instruction fetch boundaries.
+(Xtensa processors can be configured with either 32-bit or 64-bit
+instruction fetch widths.)  An
+instruction immediately following a call is treated as a branch target
+in this context, because it will be the target of a return from the
+call.  This alignment has the potential to reduce branch penalties at
+some expense in code size.  The assembler will not attempt to align
+labels with the prefixes @code{.Ln} and @code{.LM}, since these labels
+are used for debugging information and are not typically branch targets.
+This optimization is enabled by default.  You can disable it with the
+@samp{--no-target-@-align} command-line option (@pxref{Xtensa Options,
+,Command Line Options}).
+
+The target alignment optimization is done without adding instructions
+that could increase the execution time of the program.  If there are
+density instructions in the code preceding a target, the assembler can
+change the target alignment by widening some of those instructions to
+the equivalent 24-bit instructions.  Extra bytes of padding can be
+inserted immediately following unconditional jump and return
+instructions.
+This approach is usually successful in aligning many, but not all,
+branch targets.
+
+The @code{LOOP} family of instructions must be aligned such that the
+first instruction in the loop body does not cross an instruction fetch
+boundary (e.g., with a 32-bit fetch width, a @code{LOOP} instruction
+must be on either a 1 or 2 mod 4 byte boundary).  The assembler knows
+about this restriction and inserts the minimal number of 2 or 3 byte
+no-op instructions to satisfy it.  When no-op instructions are added,
+any label immediately preceding the original loop will be moved in order
+to refer to the loop instruction, not the newly generated no-op
+instruction.  To preserve binary compatibility across processors with
+different fetch widths, the assembler conservatively assumes a 32-bit
+fetch width when aligning @code{LOOP} instructions (except if the first
+instruction in the loop is a 64-bit instruction).
 
 Similarly, the @code{ENTRY} instruction must be aligned on a 0 mod 4
 byte boundary.  The assembler satisfies this requirement by inserting
@@ -260,7 +293,7 @@ location.
 @cindex relaxation
 
 When an instruction operand is outside the range allowed for that
-particular instruction field, @code{@value{AS}} can transform the code
+particular instruction field, @command{@value{AS}} can transform the code
 to use a functionally-equivalent instruction or sequence of
 instructions.  This process is known as @dfn{relaxation}.  This is
 typically done for branch instructions because the distance of the
@@ -300,6 +333,19 @@ M:
 (The @code{BNEZ.N} instruction would be used in this example only if the
 density option is available.  Otherwise, @code{BNEZ} would be used.)
 
+This relaxation works well because the unconditional jump instruction
+has a much larger offset range than the various conditional branches.
+However, an error will occur if a branch target is beyond the range of a
+jump instruction.  @command{@value{AS}} cannot relax unconditional jumps.
+Similarly, an error will occur if the original input contains an
+unconditional jump to a target that is out of range.
+
+Branch relaxation is enabled by default.  It can be disabled by using
+underscore prefixes (@pxref{Xtensa Opcodes, ,Opcode Names}), the
+@samp{--no-transform} command-line option (@pxref{Xtensa Options,
+,Command Line Options}), or the @code{no-transform} directive
+(@pxref{Transform Directive, ,transform}).
+
 @node Xtensa Call Relaxation
 @subsection Function Call Relaxation
 @cindex relaxation of call instructions
@@ -332,21 +378,27 @@ Because the addresses of targets of function calls are not generally
 known until link-time, the assembler must assume the worst and relax all
 the calls to functions in other source files, not just those that really
 will be out of range.  The linker can recognize calls that were
-unnecessarily relaxed, but it can only partially remove the overhead
-introduced by the assembler.
+unnecessarily relaxed, and it will remove the overhead introduced by the
+assembler for those cases where direct calls are sufficient.
 
-Call relaxation has a negative effect
-on both code size and performance, so this relaxation is disabled by 
-default.  If a program is too large and some of the calls are out of
-range, function call relaxation can be enabled using the
-@samp{--longcalls} command-line option or the @code{longcalls} directive
-(@pxref{Longcalls Directive, ,longcalls}).
+Call relaxation is disabled by default because it can have a negative
+effect on both code size and performance, although the linker can
+usually eliminate the unnecessary overhead.  If a program is too large
+and some of the calls are out of range, function call relaxation can be
+enabled using the @samp{--longcalls} command-line option or the
+@code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}).
 
 @node Xtensa Immediate Relaxation
 @subsection Other Immediate Field Relaxation
 @cindex immediate fields, relaxation
 @cindex relaxation of immediate fields
 
+The assembler normally performs the following other relaxations.  They
+can be disabled by using underscore prefixes (@pxref{Xtensa Opcodes,
+,Opcode Names}), the @samp{--no-transform} command-line option
+(@pxref{Xtensa Options, ,Command Line Options}), or the
+@code{no-transform} directive (@pxref{Transform Directive, ,transform}).
+
 @cindex @code{MOVI} instructions, relaxation
 @cindex relaxation of @code{MOVI} instructions
 The @code{MOVI} machine instruction can only materialize values in the
@@ -401,7 +453,7 @@ out-of-range offset causes an error.
 @cindex relaxation of @code{ADDI} instructions
 The Xtensa @code{ADDI} instruction only allows immediate operands in the
 range from -128 to 127.  There are a number of alternate instruction
-sequences for the generic @code{ADDI} operation.  First, if the
+sequences for the @code{ADDI} operation.  First, if the
 immediate is 0, the @code{ADDI} will be turned into a @code{MOV.N}
 instruction (or the equivalent @code{OR} instruction if the code density
 option is not available).  If the @code{ADDI} immediate is outside of
@@ -456,87 +508,48 @@ change the state of the directive without having to be aware of its
 outer state.  For example, consider:
 
 @smallexample
-    .begin no-density
+    .begin no-transform
 L:  add a0, a1, a2
-    .begin density
+    .begin transform
 M:  add a0, a1, a2
-    .end density
+    .end transform
 N:  add a0, a1, a2
-    .end no-density
+    .end no-transform
 @end smallexample
 
-The generic @code{ADD} opcodes at @code{L} and @code{N} in the outer
-@code{no-density} region both result in @code{ADD} machine instructions,
-but the assembler selects an @code{ADD.N} instruction for the generic
-@code{ADD} at @code{M} in the inner @code{density} region.
+The @code{ADD} opcodes at @code{L} and @code{N} in the outer
+@code{no-transform} region both result in @code{ADD} machine instructions,
+but the assembler selects an @code{ADD.N} instruction for the
+@code{ADD} at @code{M} in the inner @code{transform} region.
 
 The advantage of this style is that it works well inside macros which can
 preserve the context of their callers.
 
-@cindex precedence of directives
-@cindex directives, precedence
-When command-line options and assembler directives are used at the same
-time and conflict, the one that overrides a default behavior takes
-precedence over one that is the same as the default.  For example, if
-the code density option is available, the default is to select density
-instructions whenever possible.  So, if the above is assembled with the
-@samp{--no-density} flag, which overrides the default, all the generic
-@code{ADD} instructions result in @code{ADD} machine instructions.  If
-assembled with the @samp{--density} flag, which is already the default,
-the @code{no-density} directive takes precedence and only one of
-the generic @code{ADD} instructions is optimized to be a @code{ADD.N}
-machine instruction.  An underscore prefix identifying a specific opcode
-always takes precedence over directives and command-line flags.
-
 The following directives are available:
 @menu
-* Density Directive::          Disable Use of Density Instructions.
-* Relax Directive::            Disable Assembler Relaxation.
+* Schedule Directive::         Enable instruction scheduling.
 * Longcalls Directive::        Use Indirect Calls for Greater Range.
-* Generics Directive::         Disable All Assembler Transformations.
+* Transform Directive::        Disable All Assembler Transformations.
 * Literal Directive::          Intermix Literals with Instructions.
 * Literal Position Directive:: Specify Inline Literal Pool Locations.
 * Literal Prefix Directive::   Specify Literal Section Name Prefix.
-* Freeregs Directive::         List Registers Available for Assembler Use.
-* Frame Directive::            Describe a stack frame.
+* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals.
 @end menu
 
-@node Density Directive
-@subsection density
-@cindex @code{density} directive
-@cindex @code{no-density} directive
+@node Schedule Directive
+@subsection schedule
+@cindex @code{schedule} directive
+@cindex @code{no-schedule} directive
 
-The @code{density} and @code{no-density} directives enable or disable
-optimization of generic instructions into density instructions within
-the region.  @xref{Density Instructions, ,Using Density Instructions}.
+The @code{schedule} directive is recognized only for compatibility with
+Tensilica's assembler.
 
 @smallexample
-    .begin [no-]density
-    .end [no-]density
+    .begin [no-]schedule
+    .end [no-]schedule
 @end smallexample
 
-This optimization is enabled by default unless the Xtensa configuration
-does not support the code density option or the @samp{--no-density}
-command-line option was specified.
-
-@node Relax Directive
-@subsection relax
-@cindex @code{relax} directive
-@cindex @code{no-relax} directive
-
-The @code{relax} directive enables or disables relaxation
-within the region.  @xref{Xtensa Relaxation, ,Xtensa Relaxation}.
-Note: In the current implementation, these directives also control
-whether assembler optimizations are performed, making them equivalent to
-the @code{generics} and @code{no-generics} directives.
-
-@smallexample
-    .begin [no-]relax
-    .end [no-]relax
-@end smallexample
-
-Relaxation is enabled by default unless the @samp{--no-relax}
-command-line option was specified.
+This directive is ignored and has no effect on @command{@value{AS}}.
 
 @node Longcalls Directive
 @subsection longcalls
@@ -552,27 +565,28 @@ relaxation.  @xref{Xtensa Call Relaxation, ,Function Call Relaxation}.
 @end smallexample
 
 Call relaxation is disabled by default unless the @samp{--longcalls}
-command-line option is specified.
+command-line option is specified.  The @code{longcalls} directive
+overrides the default determined by the command-line options.
 
-@node Generics Directive
-@subsection generics
-@cindex @code{generics} directive
-@cindex @code{no-generics} directive
+@node Transform Directive
+@subsection transform
+@cindex @code{transform} directive
+@cindex @code{no-transform} directive
 
 This directive enables or disables all assembler transformation,
 including relaxation (@pxref{Xtensa Relaxation, ,Xtensa Relaxation}) and
 optimization (@pxref{Xtensa Optimizations, ,Xtensa Optimizations}).
 
 @smallexample
-    .begin [no-]generics
-    .end [no-]generics
+    .begin [no-]transform
+    .end [no-]transform
 @end smallexample
 
-Disabling generics is roughly equivalent to adding an underscore prefix
-to every opcode within the region, so that every opcode is treated as a
-specific opcode.  @xref{Xtensa Opcodes, ,Opcode Names}.  In the current
-implementation of @code{@value{AS}}, built-in macros are also disabled
-within a @code{no-generics} region.
+Transformations are enabled by default unless the @samp{--no-transform}
+option is used.  The @code{transform} directive overrides the default
+determined by the command-line options.  An underscore opcode prefix,
+disabling transformation of that opcode, always takes precedence over
+both directives and command-line flags.
 
 @node Literal Directive
 @subsection literal
@@ -603,17 +617,19 @@ can be used to load a pointer to the symbol @code{sym} into register
 @code{ENTRY} and @code{L32R} instructions; instead, the assembler puts
 the data in a literal pool.
 
-By default literal pools are placed in a separate section; however, when
-using the @samp{--text-@-section-@-literals} option (@pxref{Xtensa
-Options, ,Command Line Options}), the literal pools are placed in the
-current section.  These text section literal pools are created
-automatically before @code{ENTRY} instructions and manually after
-@samp{.literal_position} directives (@pxref{Literal Position Directive,
-,literal_position}).  If there are no preceding @code{ENTRY}
-instructions or @code{.literal_position} directives, the assembler will
-print a warning and place the literal pool at the beginning of the
-current section.  In such cases, explicit @code{.literal_position}
-directives should be used to place the literal pools.
+Literal pools for absolute mode @code{L32R} instructions
+(@pxref{Absolute Literals Directive}) are placed in a separate
+@code{.lit4} section.  By default literal pools for PC-relative mode
+@code{L32R} instructions are placed in a separate @code{.literal}
+section; however, when using the @samp{--text-@-section-@-literals}
+option (@pxref{Xtensa Options, ,Command Line Options}), the literal
+pools are placed in the current section.  These text section literal
+pools are created automatically before @code{ENTRY} instructions and
+manually after @samp{.literal_position} directives (@pxref{Literal
+Position Directive, ,literal_position}).  If there are no preceding
+@code{ENTRY} instructions, explicit @code{.literal_position} directives
+must be used to place the text section literal pools; otherwise,
+@command{@value{AS}} will report an error.
 
 @node Literal Position Directive
 @subsection literal_position
@@ -628,7 +644,8 @@ can be used to mark a potential location for a literal pool.
 @end smallexample
 
 The @code{.literal_position} directive is ignored when the
-@samp{--text-@-section-@-literals} option is not used.
+@samp{--text-@-section-@-literals} option is not used or when
+@code{L32R} instructions use the absolute addressing mode.
 
 The assembler will automatically place text section literal pools 
 before @code{ENTRY} instructions, so the @code{.literal_position}
@@ -642,7 +659,8 @@ place to put a literal pool.  Moreover, the code for the interrupt
 vector must be at a specific starting address, so the literal pool
 cannot come before the start of the code.  The literal pool for the
 vector must be explicitly positioned in the middle of the vector (before
-any uses of the literals, of course).  The @code{.literal_position}
+any uses of the literals, due to the negative offsets used by
+PC-relative @code{L32R} instructions).  The @code{.literal_position}
 directive can be used to do this.  In the following code, the literal
 for @samp{M} will automatically be aligned correctly and is placed after
 the unconditional jump.
@@ -671,69 +689,64 @@ into multiple sections, including literals generated by the assembler.
     .end literal_prefix
 @end smallexample
 
-For the code inside the delimited region, the assembler puts literals in
-the section @code{@var{name}.literal}. If this section does not yet
-exist, the assembler creates it.  The @var{name} parameter is
-optional. If @var{name} is not specified, the literal prefix is set to
-the ``default'' for the file.  This default is usually @code{.literal}
-but can be changed with the @samp{--rename-section} command-line
-argument.
-
-@node Freeregs Directive
-@subsection freeregs
-@cindex @code{freeregs} directive
-
-This directive tells the assembler that the given registers are unused
-in the region.
-
-@smallexample
-    .begin freeregs @var{ri}[,@var{ri}@dots{}]
-    .end freeregs
-@end smallexample
-
-This allows the assembler to use these registers for relaxations or
-optimizations.  (They are actually only for relaxations at present, but
-the possibility of optimizations exists in the future.)
-
-Nested @code{freeregs} directives can be used to add additional registers
-to the list of those available to the assembler.  For example:
-
-@smallexample
-    .begin freeregs a3, a4
-    .begin freeregs a5
-@end smallexample
-
-has the effect of declaring @code{a3}, @code{a4}, and @code{a5} all free.
-
-@node Frame Directive
-@subsection frame
-@cindex @code{frame} directive
-
-This directive tells the assembler to emit information to allow the
-debugger to locate a function's stack frame.  The syntax is:
+By default the assembler places literal pools in sections separate from
+the instructions, using the default literal section names of
+@code{.literal} for PC-relative mode @code{L32R} instructions and
+@code{.lit4} for absolute mode @code{L32R} instructions (@pxref{Absolute
+Literals Directive}).  The @code{literal_prefix} directive causes
+different literal sections to be used for the code inside the delimited
+region.  The new literal sections are determined by including @var{name}
+as a prefix to the default literal section names.  If the @var{name}
+argument is omitted, the literal sections revert to the defaults.  This
+directive has no effect when using the
+@samp{--text-@-section-@-literals} option (@pxref{Xtensa Options,
+,Command Line Options}).
+
+Except for two special cases, the assembler determines the new literal
+sections by simply prepending @var{name} to the default section names,
+resulting in @code{@var{name}.literal} and @code{@var{name}.lit4}
+sections.  The @code{literal_prefix} directive is often used with the
+name of the current text section as the prefix argument.  To facilitate
+this usage, the assembler uses special case rules when it recognizes
+@var{name} as a text section name.  First, if @var{name} ends with
+@code{.text}, that suffix is not included in the literal section name.
+For example, if @var{name} is @code{.iram0.text}, then the literal
+sections will be @code{.iram0.literal} and @code{.iram0.lit4}.  Second,
+if @var{name} begins with @code{.gnu.linkonce.t.}, then the literal
+section names are formed by replacing the @code{.t} substring with
+@code{.literal} and @code{.lit4}.  For example, if @var{name} is
+@code{.gnu.linkonce.t.func}, the literal sections will be
+@code{.gnu.linkonce.literal.func} and @code{.gnu.linkonce.lit4.func}.
+
+@node Absolute Literals Directive
+@subsection absolute-literals
+@cindex @code{absolute-literals} directive
+@cindex @code{no-absolute-literals} directive
+
+The @code{absolute-@-literals} and @code{no-@-absolute-@-literals}
+directives control the absolute vs.@: PC-relative mode for @code{L32R}
+instructions.  These are relevant only for Xtensa configurations that
+include the absolute addressing option for @code{L32R} instructions.
 
 @smallexample
-    .frame @var{reg}, @var{size}
+    .begin [no-]absolute-literals
+    .end [no-]absolute-literals
 @end smallexample
 
-where @var{reg} is the register used to hold the frame pointer (usually
-the same as the stack pointer) and @var{size} is the size in bytes of
-the stack frame.  The @code{.frame} directive is typically placed
-immediately after the @code{ENTRY} instruction for a function.
-
-In almost all circumstances, this information just duplicates the
-information given in the function's @code{ENTRY} instruction; however,
-there are two cases where this is not true:
-
-@enumerate
-@item
-The size of the stack frame is too big to fit in the immediate field
-of the @code{ENTRY} instruction.
-
-@item
-The frame pointer is different than the stack pointer, as with functions
-that call @code{alloca}.
-@end enumerate
+These directives do not change the @code{L32R} mode---they only cause
+the assembler to emit the appropriate kind of relocation for @code{L32R}
+instructions and to place the literal values in the appropriate section.
+To change the @code{L32R} mode, the program must write the
+@code{LITBASE} special register.  It is the programmer's responsibility
+to keep track of the mode and indicate to the assembler which mode is
+used in each region of code.
+
+If the Xtensa configuration includes the absolute @code{L32R} addressing
+option, the default is to assume absolute @code{L32R} addressing unless
+the @samp{--no-@-absolute-@-literals} command-line option is specified.
+Otherwise, the default is to assume PC-relative @code{L32R} addressing.
+The @code{absolute-@-literals} directive can then be used to override
+the default determined by the command-line options.
 
 @c Local Variables:
 @c fill-column: 72
diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
new file mode 100644
index 000000000000..76e8410840a4
--- /dev/null
+++ b/gas/doc/c-z80.texi
@@ -0,0 +1,257 @@
+@c This is part of the GAS manual.
+@c For copying conditions, see the file as.texinfo.
+
+@ifset GENERIC
+@page
+@node Z80-Dependent
+@chapter Z80 Dependent Features
+@end ifset
+
+
+@ifclear GENERIC
+@node Machine Dependencies
+@chapter Z80 Dependent Features
+@end ifclear
+
+@cindex Z80 support
+@menu
+* Z80 Options::              Options
+* Z80 Syntax::               Syntax
+* Z80 Floating Point::       Floating Point
+* Z80 Directives::           Z80 Machine Directives
+* Z80 Opcodes::              Opcodes
+@end menu
+
+@node Z80 Options
+@section Options
+@cindex Z80 options
+@cindex options for Z80
+The Zilog Z80 and Ascii R800 version of @code{@value{AS}} have a few machine
+dependent options.
+@table @option
+@cindex @code{-z80} command line option, Z80
+@item -z80
+Produce code for the Z80 processor. There are additional options to
+request warnings and error messages for undocumented instructions.
+@item  -ignore-undocumented-instructions
+@itemx -Wnud
+Silently assemble undocumented Z80-instructions that have been adopted
+as documented R800-instructions.
+@item  -ignore-unportable-instructions
+@itemx -Wnup
+Silently assemble all undocumented Z80-instructions.
+@item  -warn-undocumented-instructions
+@itemx -Wud
+Issue warnings for undocumented Z80-instructions that work on R800, do
+not assemble other undocumented instructions without warning.
+@item  -warn-unportable-instructions
+@itemx -Wup
+Issue warnings for other undocumented Z80-instructions, do not treat any
+undocumented instructions as errors.
+@item  -forbid-undocumented-instructions
+@itemx -Fud
+Treat all undocumented z80-instructions as errors.
+@item  -forbid-unportable-instructions
+@itemx -Fup
+Treat undocumented z80-instructions that do not work on R800 as errors.
+
+@cindex @code{-r800} command line option, Z80
+@item -r800
+Produce code for the R800 processor. The assembler does not support
+undocumented instructions for the R800.
+In line with common practice, @code{@value{AS}} uses Z80 instriction names
+for the R800 processor, as far as they exist.
+@end table
+
+@cindex Z80 Syntax
+@node Z80 Syntax
+@section Syntax
+The assembler syntax closely follows the 'Z80 family CPU User Manual' by
+Zilog.
+In expressions a single @samp{=} may be used as ``is equal to''
+comparison operator.  
+
+Suffices can be used to indicate the radix of integer constants;
+@samp{H} or @samp{h} for hexadecimal, @samp{D} or @samp{d} for decimal,
+@samp{Q}, @samp{O}, @samp{q} or @samp{o} for octal, and @samp{B} for
+binary.
+
+The suffix @samp{b} denotes a backreference to local label.  
+
+@menu
+* Z80-Chars::                Special Characters
+* Z80-Regs::                 Register Names
+* Z80-Case::                 Case Sensitivity
+@end menu
+
+@node Z80-Chars
+@subsection Special Characters
+
+@cindex line comment character, Z80
+@cindex Z80 line comment character
+The semicolon @samp{;} is the line comment character; 
+
+@cindex location counter, Z80
+@cindex hexadecimal prefix, Z80
+@cindex Z80 $
+The dollar sign @samp{$} can be used as a prefix for hexadecimal numbers
+and as a symbol denoting the current location counter.
+
+@cindex character escapes, Z80
+@cindex Z80, \
+A backslash @samp{\} is an ordinary character for the Z80 assembler.
+ 
+@cindex character constant, Z80
+@cindex single quote, Z80
+@cindex Z80 '
+The single quote @samp{'} must be followed by a closing quote. If there
+is one character inbetween, it is a character constant, otherwise it is
+a string constant.
+
+@node Z80-Regs
+@subsection Register Names
+@cindex Z80 registers
+@cindex register names, Z80
+
+The registers are referred to with the letters assigned to them by
+Zilog. In addition @command{@value{AS}} recognises @samp{ixl} and 
+@samp{ixh} as the least and most significant octet in @samp{ix}, and
+similarly @samp{iyl} and  @samp{iyh} as parts of @samp{iy}. 
+
+@c The @samp{'} in @samp{ex af,af'} may be omitted.
+
+@node Z80-Case
+@subsection Case Sensitivity
+@cindex Z80, case sensitivity
+@cindex case sensitivity, Z80
+
+Upper and lower case are equivalent in register names, opcodes,
+condition codes  and assembler directives. 
+The case of letters is significant in labels and symbol names. The case
+is also important to distinguish the suffix @samp{b} for a backward reference
+to a local label from the suffix @samp{B} for a number in binary notation.
+
+@node Z80 Floating Point
+@section Floating Point
+@cindex floating point, Z80
+@cindex Z80 floating point
+Floating-point numbers are not supported.
+
+@node Z80 Directives
+@section Z80 Assembler Directives
+
+@command{@value{AS}} for the Z80 supports some additional directives for
+compatibility with other assemblers. 
+
+@cindex Z80-only directives
+These are the additional directives in @code{@value{AS}} for the Z80:
+
+@table @code
+@item db @var{expression}|@var{string}[,@var{expression}|@var{string}...]
+@itemx defb @var{expression}|@var{string}[,@var{expression}|@var{string}...]
+For each @var{string} the characters are copied to the object file, for
+each other @var{expression} the value is stored in one byte. 
+A warning is issued in case of an overflow. 
+
+@item dw @var{expression}[,@var{expression}...]
+@itemx defw @var{expression}[,@var{expression}...]
+For each @var{expression} the value is stored in two bytes, ignoring
+overflow. 
+
+@item d24 @var{expression}[,@var{expression}...]
+@itemx def24 @var{expression}[,@var{expression}...]
+For each @var{expression} the value is stored in three bytes, ignoring
+overflow. 
+
+@item d32 @var{expression}[,@var{expression}...]
+@itemx def32 @var{expression}[,@var{expression}...]
+For each @var{expression} the value is stored in four bytes, ignoring
+overflow. 
+
+@item ds @var{count}[, @var{value}]
+@itemx defs @var{count}[, @var{value}]
+@c Synonyms for @code{ds.b}, 
+@c which should have been described elsewhre
+Fill @var{count} bytes in the object file with @var{value}, if
+@var{value} is omitted it defaults to zero.
+
+@item @var{symbol} equ @var{expression}
+@itemx @var{symbol} defl @var{expression}
+These directives set the value of @var{symbol} to @var{expression}. If
+@code{equ} is used, it is an error if @var{symbol} is already defined.
+Symbols defined with @code{equ} are not protected from redefinition.
+
+@item set
+This is a normal instruction on Z80, and not an assembler directive. 
+
+@item psect @var{name}
+A synonym for @xref{Section}, no second argument should be given. 
+@ignore
+
+The following attributes will possibly be recognised in the future
+@table @code
+@item abs
+The section is to be absolute. @code{@value{AS}} will issue an error
+message because it can not produce an absolute section.
+@item global
+The section is to be concatenated with other sections of the same name
+by the linker, this is the default.
+@item local
+The section is not global. @code{@value{AS}} will issue a warning if
+object file format is not soff.
+@item ovrld
+The section is to be overlapped with other sections of the same name by
+the linker. @code{@value{AS}} will issue an error message
+because it can not mark a section as such.
+@item pure
+The section is marked as read only.
+@end table
+@end ignore
+
+@end table
+
+@node Z80 Opcodes
+@section Opcodes
+In line with commmon practice Z80 mnonics are used for both the Z80 and
+the R800. 
+
+In many instructions it is possible to use one of the half index
+registers (@samp{ixl},@samp{ixh},@samp{iyl},@samp{iyh}) in stead of an
+8-bit general purpose register. This yields instructions that are
+documented on the R800 and undocumented on the Z80.
+Similarly @code{in f,(c)} is documented on the R800 and undocumented on
+the Z80.
+
+The assembler also supports the following undocumented Z80-instructions,
+that have not been adopted in the R800 instruction set:
+@table @code
+@item out (c),0
+Sends zero to the port pointed to by register c.
+
+@item sli @var{m}
+Equivalent to @code{@var{m} = (@var{m}<<1)+1}, the operand @var{m} can
+be any operand that is valid for @samp{sla}. One can use @samp{sll} as a
+synonym for @samp{sli}.
+
+@item @var{op} (ix+@var{d}), @var{r}
+This is equivalent to 
+
+@example
+ld @var{r}, (ix+@var{d})
+@var{opc} @var{r}
+ld (ix+@var{d}), @var{r}
+@end example
+
+The operation @samp{@var{opc}} may be any of @samp{res @var{b},},
+@samp{set @var{b},}, @samp{rl}, @samp{rlc}, @samp{rr}, @samp{rrc},
+@samp{sla}, @samp{sli}, @samp{sra} and @samp{srl}, and the register
+@samp{@var{r}} may be any of @samp{a}, @samp{b}, @samp{c}, @samp{d},
+@samp{e}, @samp{h} and @samp{l}.
+
+@item @var{opc} (iy+@var{d}), @var{r}
+As above, but with @samp{iy} instead of @samp{ix}.
+@end table
+
+The web site at @uref{http://www.z80.info} is a good starting place to
+find more information on programming the Z80.
+
diff --git a/gas/doc/c-z8k.texi b/gas/doc/c-z8k.texi
index de34237559be..269b6124a3a2 100644
--- a/gas/doc/c-z8k.texi
+++ b/gas/doc/c-z8k.texi
@@ -1,4 +1,5 @@
-@c Copyright 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+@c Copyright 1991, 1992, 1993, 1994, 1995, 2003
+@c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
 @ifset GENERIC
diff --git a/gas/doc/fdl.texi b/gas/doc/fdl.texi
index c6409a3a1a33..cc3cd011e962 100644
--- a/gas/doc/fdl.texi
+++ b/gas/doc/fdl.texi
@@ -4,8 +4,8 @@
 @center Version 1.1, March 2000
 
 @display
-Copyright (C) 2000, Free Software Foundation, Inc.
-59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+Copyright (C) 2000, 2003 Free Software Foundation, Inc.
+51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
 
 Everyone is permitted to copy and distribute verbatim copies
 of this license document, but changing it is not allowed.
diff --git a/gas/doc/gasver.texi b/gas/doc/gasver.texi
index 3610a96b9671..11d1801d6e65 100644
--- a/gas/doc/gasver.texi
+++ b/gas/doc/gasver.texi
@@ -1 +1 @@
-@set VERSION 2.15
+@set VERSION 2.17
diff --git a/gas/doc/internals.texi b/gas/doc/internals.texi
index 6719bbf945d3..dffdb1e04fa9 100644
--- a/gas/doc/internals.texi
+++ b/gas/doc/internals.texi
@@ -1,6 +1,6 @@
 \input texinfo
 @c  Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-@c  2001, 2002, 2003
+@c  2001, 2002, 2003, 2004, 2005
 @c  Free Software Foundation, Inc.
 @setfilename internals.info
 @node Top
@@ -14,7 +14,6 @@ it may help a bit.
 This chapter is not updated regularly, and it may be out of date.
 
 @menu
-* GAS versions::        GAS versions
 * Data types::		Data types
 * GAS processing::      What GAS does when it runs
 * Porting GAS::         Porting GAS
@@ -24,80 +23,6 @@ This chapter is not updated regularly, and it may be out of date.
 * Test suite::          Test suite
 @end menu
 
-@node GAS versions
-@section GAS versions
-
-GAS has acquired layers of code over time.  The original GAS only supported the
-a.out object file format, with three sections.  Support for multiple sections
-has been added in two different ways.
-
-The preferred approach is to use the version of GAS created when the symbol
-@code{BFD_ASSEMBLER} is defined.  The other versions of GAS are documented for
-historical purposes, and to help anybody who has to debug code written for
-them.
-
-The type @code{segT} is used to represent a section in code which must work
-with all versions of GAS.
-
-@menu
-* Original GAS::        Original GAS version
-* MANY_SEGMENTS::       MANY_SEGMENTS gas version
-* BFD_ASSEMBLER::       BFD_ASSEMBLER gas version
-@end menu
-
-@node Original GAS
-@subsection Original GAS
-
-The original GAS only supported the a.out object file format with three
-sections: @samp{.text}, @samp{.data}, and @samp{.bss}.  This is the version of
-GAS that is compiled if neither @code{BFD_ASSEMBLER} nor @code{MANY_SEGMENTS}
-is defined.  This version of GAS is still used for the m68k-aout target, and
-perhaps others.
-
-This version of GAS should not be used for any new development.
-
-There is still code that is specific to this version of GAS, notably in
-@file{write.c}.  There is no way for this code to loop through all the
-sections; it simply looks at global variables like @code{text_frag_root} and
-@code{data_frag_root}.
-
-The type @code{segT} is an enum.
-
-@node MANY_SEGMENTS
-@subsection MANY_SEGMENTS gas version
-@cindex MANY_SEGMENTS
-
-The @code{MANY_SEGMENTS} version of gas is only used for COFF.  It uses the BFD
-library, but it writes out all the data itself using @code{bfd_write}.  This
-version of gas supports up to 40 normal sections.  The section names are stored
-in the @code{seg_name} array.  Other information is stored in the
-@code{segment_info} array.
-
-The type @code{segT} is an enum.  Code that wants to examine all the sections
-can use a @code{segT} variable as loop index from @code{SEG_E0} up to but not
-including @code{SEG_UNKNOWN}.
-
-Most of the code specific to this version of GAS is in the file
-@file{config/obj-coff.c}, in the portion of that file that is compiled when
-@code{BFD_ASSEMBLER} is not defined.
-
-This version of GAS is still used for several COFF targets.
-
-@node BFD_ASSEMBLER
-@subsection BFD_ASSEMBLER gas version
-@cindex BFD_ASSEMBLER
-
-The preferred version of GAS is the @code{BFD_ASSEMBLER} version.  In this
-version of GAS, the output file is a normal BFD, and the BFD routines are used
-to generate the output.
-
-@code{BFD_ASSEMBLER} will automatically be used for certain targets, including
-those that use the ELF, ECOFF, and SOM object file formats, and also all Alpha,
-MIPS, PowerPC, and SPARC targets.  You can force the use of
-@code{BFD_ASSEMBLER} for other targets with the configure option
-@samp{--enable-bfd-assembler}; however, it has not been tested for many
-targets, and can not be assumed to work.
-
 @node Data types
 @section Data types
 @cindex internals, data types
@@ -152,10 +77,8 @@ symbol list.
 
 @item sy_next
 @itemx sy_previous
-These pointers to other @code{symbolS} structures describe a singly or doubly
-linked list.  (If @code{SYMBOLS_NEED_BACKPOINTERS} is not defined, the
-@code{sy_previous} field will be omitted; @code{SYMBOLS_NEED_BACKPOINTERS} is
-always defined if @code{BFD_ASSEMBLER}.)  These fields should be accessed with
+These pointers to other @code{symbolS} structures describe a doubly
+linked list.  These fields should be accessed with
 the @code{symbol_next} and @code{symbol_previous} macros.
 
 @item sy_frag
@@ -170,23 +93,22 @@ responsible for setting it when a symbol is used in backend routines.
 Whether the symbol is an MRI common symbol created by the @code{COMMON}
 pseudo-op when assembling in MRI mode.
 
-@item bsym
-If @code{BFD_ASSEMBLER} is defined, this points to the BFD @code{asymbol} that
-will be used in writing the object file.
+@item sy_volatile
+Whether the symbol can be re-defined.
 
-@item sy_name_offset
-(Only used if @code{BFD_ASSEMBLER} is not defined.)  This is the position of
-the symbol's name in the string table of the object file.  On some formats,
-this will start at position 4, with position 0 reserved for unnamed symbols.
-This field is not used until @code{write_object_file} is called.
+@item sy_forward_ref
+Whether the symbol's value must only be evaluated upon use.
 
-@item sy_symbol
-(Only used if @code{BFD_ASSEMBLER} is not defined.)  This is the
-format-specific symbol structure, as it would be written into the object file.
+@item sy_weakrefr
+Whether the symbol is a @code{weakref} alias to another symbol.
 
-@item sy_number
-(Only used if @code{BFD_ASSEMBLER} is not defined.)  This is a 24-bit symbol
-number, for use in constructing relocation table entries.
+@item sy_weakrefd
+Whether the symbol is or was referenced by one or more @code{weakref} aliases,
+and has not had any direct references.
+
+@item bsym
+This points to the BFD @code{asymbol} that
+will be used in writing the object file.
 
 @item sy_obj
 This format-specific data is of type @code{OBJ_SYMFIELD_TYPE}.  If no macro by
@@ -237,7 +159,27 @@ A synonym for @code{S_IS_EXTERNAL}.  Don't use it.
 
 @item S_IS_WEAK
 @cindex S_IS_WEAK
-Return non-zero if the symbol is weak.
+Return non-zero if the symbol is weak, or if it is a @code{weakref} alias or
+symbol that has not been strongly referenced.
+
+@item S_IS_WEAKREFR
+@cindex S_IS_WEAKREFR
+Return non-zero if the symbol is a @code{weakref} alias.
+
+@item S_IS_WEAKREFD
+@cindex S_IS_WEAKREFD
+Return non-zero if the symbol was aliased by a @code{weakref} alias and has not
+had any strong references.
+
+@item S_IS_VOLATILE
+@cindex S_IS_VOLATILE
+Return non-zero if the symbol may be re-defined. Such symbols get created by
+the @code{=} operator, @code{equ}, or @code{set}.
+
+@item S_IS_FORWARD_REF
+@cindex S_IS_FORWARD_REF
+Return non-zero if the symbol is a forward reference, that is its value must
+only be determined upon use.
 
 @item S_IS_COMMON
 @cindex S_IS_COMMON
@@ -273,6 +215,42 @@ Mark the symbol as not externally visible.
 @cindex S_SET_WEAK
 Mark the symbol as weak.
 
+@item S_SET_WEAKREFR
+@cindex S_SET_WEAKREFR
+Mark the symbol as the referrer in a @code{weakref} directive.  The symbol it
+aliases must have been set to the value expression before this point.  If the
+alias has already been used, the symbol is marked as used too.
+
+@item S_CLEAR_WEAKREFR
+@cindex S_CLEAR_WEAKREFR
+Clear the @code{weakref} alias status of a symbol.  This is implicitly called
+whenever a symbol is defined or set to a new expression.
+
+@item S_SET_WEAKREFD
+@cindex S_SET_WEAKREFD
+Mark the symbol as the referred symbol in a @code{weakref} directive.
+Implicitly marks the symbol as weak, but see below.  It should only be called
+if the referenced symbol has just been added to the symbol table.
+
+@item S_SET_WEAKREFD
+@cindex S_SET_WEAKREFD
+Clear the @code{weakref} aliased status of a symbol.  This is implicitly called
+whenever the symbol is looked up, as part of a direct reference or a
+definition, but not as part of a @code{weakref} directive.
+
+@item S_SET_VOLATILE
+@cindex S_SET_VOLATILE
+Indicate that the symbol may be re-defined.
+
+@item S_CLEAR_VOLATILE
+@cindex S_CLEAR_VOLATILE
+Indicate that the symbol may no longer be re-defined.
+
+@item S_SET_FORWARD_REF
+@cindex S_SET_FORWARD_REF
+Indicate that the symbol is a forward reference, that is its value must only
+be determined upon use.
+
 @item S_GET_TYPE
 @item S_GET_DESC
 @item S_GET_OTHER
@@ -415,7 +393,7 @@ Set the @code{TC_SYMFIELD_TYPE} field of a symbol.
 
 @end table
 
-When @code{BFD_ASSEMBLER} is defined, GAS attempts to store local
+GAS attempts to store local
 symbols--symbols which will not be written to the output file--using a
 different structure, @code{struct local_symbol}.  This structure can only
 represent symbols whose value is an offset within a frag.
@@ -484,8 +462,8 @@ the fixup becomes a relocation entry in the object file.
 @cindex fix_new_exp
 A fixup is created by a call to @code{fix_new} or @code{fix_new_exp}.  Both
 take a frag (@pxref{Frags}), a position within the frag, a size, an indication
-of whether the fixup is PC relative, and a type.  In a @code{BFD_ASSEMBLER}
-GAS, the type is nominally a @code{bfd_reloc_code_real_type}, but several
+of whether the fixup is PC relative, and a type.
+The type is nominally a @code{bfd_reloc_code_real_type}, but several
 targets use other type codes to represent fixups that can not be described as
 relocations.
 
@@ -512,15 +490,14 @@ A number which is added into the fixup.
 
 @item fx_addnumber
 Some CPU backends use this field to convey information between
-@code{md_apply_fix3} and @code{tc_gen_reloc}.  The machine independent code does
+@code{md_apply_fix} and @code{tc_gen_reloc}.  The machine independent code does
 not use it.
 
 @item fx_next
 The next fixup in the section.
 
 @item fx_r_type
-The type of the fixup.  This field is only defined if @code{BFD_ASSEMBLER}, or
-if the target defines @code{NEED_FX_R_TYPE}.
+The type of the fixup.
 
 @item fx_size
 The size of the fixup.  This is mostly used for error checking.
@@ -683,8 +660,7 @@ Indicates the section this frag chain belongs to.
 @item frch_subseg
 Subsection (subsegment) number of this frag chain.
 @item fix_root, fix_tail
-(Defined only if @code{BFD_ASSEMBLER} is defined).  Point to first and last
-@code{fixS} structures associated with this subsection.
+Point to first and last @code{fixS} structures associated with this subsection.
 @item frch_obstack
 Not currently used.  Intended to be used for frag allocation for this
 subsection.  This should reduce frag generation caused by switching sections.
@@ -748,8 +724,7 @@ store relaxation information (@pxref{Relaxation}).
 When the input file is finished, the @code{write_object_file} routine is
 called.  It assigns addresses to all the frags (@code{relax_segment}), resolves
 all the fixups (@code{fixup_segment}), resolves all the symbol values (using
-@code{resolve_symbol_value}), and finally writes out the file (in the
-@code{BFD_ASSEMBLER} case, this is done by simply calling @code{bfd_close}).
+@code{resolve_symbol_value}), and finally writes out the file.
 @end itemize
 
 @node Porting GAS
@@ -858,13 +833,17 @@ independent string passed to @code{getopt}.  @code{md_longopts} is a
 passed to @code{getopt}; you may use @code{OPTION_MD_BASE}, defined in
 @file{as.h}, as the start of a set of long option indices, if necessary.
 @code{md_longopts_size} is a @code{size_t} holding the size @code{md_longopts}.
+
 GAS will call @code{md_parse_option} whenever @code{getopt} returns an
 unrecognized code, presumably indicating a special code value which appears in
-@code{md_longopts}.  GAS will call @code{md_show_usage} when a usage message is
-printed; it should print a description of the machine specific options.
-@code{md_after_pase_args}, if defined, is called after all options are
-processed, to let the backend override settings done by the generic option
-parsing.
+@code{md_longopts}.  This function should return non-zero if it handled the
+option and zero otherwise.  There is no need to print a message about an option
+not being recognised.  This will be handled by the generic code.
+
+GAS will call @code{md_show_usage} when a usage message is printed; it should
+print a description of the machine specific options. @code{md_after_pase_args},
+if defined, is called after all options are processed, to let the backend
+override settings done by the generic option parsing.
 
 @item md_begin
 @cindex md_begin
@@ -1015,6 +994,11 @@ default definition is to accept any name followed by a colon character.
 Same as TC_START_LABEL, but should be used instead of TC_START_LABEL when
 LABELS_WITHOUT_COLONS is defined.
 
+@item TC_FAKE_LABEL
+@cindex TC_FAKE_LABEL
+You may define this macro to control what GAS considers to be a fake
+label.  The default fake label is FAKE_LABEL_NAME.
+
 @item NO_PSEUDO_DOT
 @cindex NO_PSEUDO_DOT
 If you define this macro, GAS will not require pseudo-ops to start with a
@@ -1025,7 +1009,7 @@ If you define this macro, GAS will not require pseudo-ops to start with a
 If you define this macro, it should return nonzero if the instruction is
 permitted to contain an @kbd{=} character.  GAS will call it with two
 arguments, the character before the @kbd{=} character, and the value of
-@code{input_line_pointer} at that point.  GAS uses this macro to decide if a
+the string preceding the equal sign. GAS uses this macro to decide if a
 @kbd{=} is an assignment or an instruction.
 
 @item TC_EOL_IN_INSN
@@ -1118,6 +1102,11 @@ pseudo-op.
 @cindex TC_CONS_FIX_NEW
 You may define this macro to generate a fixup for a data allocation pseudo-op.
 
+@item TC_ADDRESS_BYTES
+@cindex TC_ADDRESS_BYTES
+Define this macro to specify the number of bytes used to store an address.
+Used to implement @code{dc.a}.  The target must have a reloc for this size.
+
 @item TC_INIT_FIX_DATA (@var{fixp})
 @cindex TC_INIT_FIX_DATA
 A C statement to initialize the target specific fields of fixup @var{fixp}.
@@ -1167,12 +1156,6 @@ single precision, @samp{D_PRECISION} for double precision, or
 
 The macro has a default definition which returns 0 for all cases.
 
-@item md_reloc_size
-@cindex md_reloc_size
-This variable is only used in the original version of gas (not
-@code{BFD_ASSEMBLER} and not @code{MANY_SEGMENTS}).  It holds the size of a
-relocation entry.
-
 @item WORKING_DOT_WORD
 @itemx md_short_jump_size
 @itemx md_long_jump_size
@@ -1236,7 +1219,7 @@ given section will be processed when the @var{linkrelax} variable is
 set.  The macro is given the N_TYPE bits for the section in its
 @var{segT} argument.  If the macro evaluates to a non-zero value
 then the fixups will be converted into relocs, otherwise they will
-be passed to @var{md_apply_fix3} as normal.
+be passed to @var{md_apply_fix} as normal.
 
 @item md_convert_frag
 @cindex md_convert_frag
@@ -1263,11 +1246,11 @@ It may be used to change the fixup in @code{struct fix *@var{fixP}} before
 the generic code sees it, or to fully process the fixup.  In the latter case,
 a @code{goto @var{skip}} will bypass the generic code.
 
-@item md_apply_fix3 (@var{fixP}, @var{valP}, @var{seg})
-@cindex md_apply_fix3
+@item md_apply_fix (@var{fixP}, @var{valP}, @var{seg})
+@cindex md_apply_fix
 GAS will call this for each fixup that passes the @code{TC_VALIDATE_FIX} test
 when @var{linkrelax} is not set.  It should store the correct value in the
-object file.  @code{struct fix *@var{fixP}} is the fixup @code{md_apply_fix3}
+object file.  @code{struct fix *@var{fixP}} is the fixup @code{md_apply_fix}
 is operating on.  @code{valueT *@var{valP}} is the value to store into the
 object files, or at least is the generic code's best guess.  Specifically,
 *@var{valP} is the value of the fixup symbol, perhaps modified by
@@ -1275,8 +1258,8 @@ object files, or at least is the generic code's best guess.  Specifically,
 less @code{MD_PCREL_FROM_SECTION} for pc-relative fixups.
 @code{segT @var{seg}} is the section the fix is in.
 @code{fixup_segment} performs a generic overflow check on *@var{valP} after
-@code{md_apply_fix3} returns.  If the overflow check is relevant for the target
-machine, then @code{md_apply_fix3} should modify *@var{valP}, typically to the
+@code{md_apply_fix} returns.  If the overflow check is relevant for the target
+machine, then @code{md_apply_fix} should modify *@var{valP}, typically to the
 value stored in the object file.
 
 @item TC_FORCE_RELOCATION (@var{fix})
@@ -1304,7 +1287,7 @@ returns non-zero, will emit relocs.
 This macro controls resolution of fixup expressions involving the
 difference of two symbols in the same section.  If this macro returns zero,
 the subtrahend will be resolved and @code{fx_subsy} set to @code{NULL} for
-@code{md_apply_fix3}.  If undefined, the default of
+@code{md_apply_fix}.  If undefined, the default of
 @w{@code{! SEG_NORMAL (@var{seg}) || TC_FORCE_RELOCATION (@var{fix})}} will
 be used.
 
@@ -1327,13 +1310,13 @@ This macro is evaluated for any fixup with a @code{fx_subsy} that
 @item MD_APPLY_SYM_VALUE (@var{fix})
 @cindex MD_APPLY_SYM_VALUE
 This macro controls whether the symbol value becomes part of the value passed
-to @code{md_apply_fix3}.  If the macro is undefined, or returns non-zero, the
+to @code{md_apply_fix}.  If the macro is undefined, or returns non-zero, the
 symbol value will be included.  For ELF, a suitable definition might simply be
 @code{0}, because ELF relocations don't include the symbol value in the addend.
 
 @item S_FORCE_RELOC (@var{sym}, @var{strict})
 @cindex S_FORCE_RELOC
-This macro (or function, for @code{BFD_ASSEMBLER} gas) returns true for symbols
+This function returns true for symbols
 that should not be reduced to section symbols or eliminated from expressions,
 because they may be overridden by the linker.  ie. for symbols that are
 undefined or common, and when @var{strict} is set, weak, or global (for ELF
@@ -1347,7 +1330,7 @@ symbols.  If undefined, the default is @code{true} for ELF assemblers, and
 
 @item tc_gen_reloc
 @cindex tc_gen_reloc
-A @code{BFD_ASSEMBLER} GAS will call this to generate a reloc.  GAS will pass
+GAS will call this to generate a reloc.  GAS will pass
 the resulting reloc to @code{bfd_install_relocation}.  This currently works
 poorly, as @code{bfd_install_relocation} often does the wrong thing, and
 instances of @code{tc_gen_reloc} have been written to work around the problems,
@@ -1432,7 +1415,7 @@ whitespace, or concatenated if there is not.
 
 @item tc_frob_section
 @cindex tc_frob_section
-If you define this macro, a @code{BFD_ASSEMBLER} GAS will call it for each
+If you define this macro, GAS will call it for each
 section at the end of the assembly.
 
 @item tc_frob_file_before_adjust
@@ -1520,6 +1503,20 @@ It should return the size of an address, as it should be represented in
 debugging info.  If you don't define this macro, the default definition uses
 the number of bits per address, as defined in @var{bfd}, divided by 8.
 
+@item   MD_DEBUG_FORMAT_SELECTOR
+@cindex MD_DEBUG_FORMAT_SELECTOR
+If defined this macro is the name of a function to be called when the
+@samp{--gen-debug} switch is detected on the assembler's command line.  The
+prototype for the function looks like this:
+
+@smallexample
+   enum debug_info_type MD_DEBUG_FORMAT_SELECTOR (int * use_gnu_extensions)
+@end smallexample
+
+The function should return the debug format that is preferred by the CPU
+backend.  This format will be used when generating assembler specific debug
+information.
+
 @end table
 
 @node Object format backend
@@ -1534,11 +1531,6 @@ defining a number of pseudo-ops.
 
 The object format @file{.h} file must include @file{targ-cpu.h}.
 
-This section will only define the @code{BFD_ASSEMBLER} version of GAS.  It is
-impossible to support a new object file format using any other version anyhow,
-as the original GAS version only supports a.out, and the @code{MANY_SEGMENTS}
-GAS version only supports COFF.
-
 @table @code
 @item OBJ_@var{format}
 @cindex OBJ_@var{format}
@@ -1610,6 +1602,16 @@ If you define this macro, GAS will call it for each symbol.  You can indicate
 that the symbol should not be included in the object file by defining this
 macro to set its second argument to a non-zero value.
 
+@item obj_set_weak_hook
+@cindex obj_set_weak_hook
+If you define this macro, @code{S_SET_WEAK} will call it before modifying the
+symbol's flags.
+
+@item obj_clear_weak_hook
+@cindex obj_clear_weak_hook
+If you define this macro, @code{S_CLEAR_WEAKREFD} will call it after clearning
+the @code{weakrefd} flag, but before modifying any other flags.
+
 @item obj_frob_file
 @cindex obj_frob_file
 If you define this macro, GAS will call it after the symbol table has been
@@ -1623,8 +1625,7 @@ generated.
 @cindex SET_SECTION_RELOCS
 If you define this, it will be called after the relocations have been set for
 the section @var{sec}.  The list of relocations is in @var{relocs}, and the
-number of relocations is in @var{n}.  This is only used with
-@code{BFD_ASSEMBLER}.
+number of relocations is in @var{n}.
 @end table
 
 @node Emulations
@@ -1870,9 +1871,8 @@ after all input has been read, but messages about fixups should refer to the
 original filename and line number that they are applicable to.
 @end deftypefun
 
-@deftypefun @{@} void fprint_value (FILE *@var{file}, valueT @var{val})
-@deftypefunx @{@} void sprint_value (char *@var{buf}, valueT @var{val})
-These functions are helpful for converting a @code{valueT} value into printable
+@deftypefun @{@} void sprint_value (char *@var{buf}, valueT @var{val})
+This function is helpful for converting a @code{valueT} value into printable
 format, in case it's wider than modes that @code{*printf} can handle.  If the
 type is narrow enough, a decimal number will be produced; otherwise, it will be
 in hexadecimal.  The value itself is not examined to make this determination.
diff --git a/gas/dw2gencfi.c b/gas/dw2gencfi.c
index ff0aa35353d2..bfa5d5cf45a6 100644
--- a/gas/dw2gencfi.c
+++ b/gas/dw2gencfi.c
@@ -1,5 +1,5 @@
 /* dw2gencfi.c - Support for generating Dwarf2 CFI information.
-   Copyright 2003 Free Software Foundation, Inc.
+   Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
    Contributed by Michal Ludvig <mludvig@suse.cz>
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 #include "dw2gencfi.h"
@@ -25,7 +25,7 @@
 
 /* We re-use DWARF2_LINE_MIN_INSN_LENGTH for the code alignment field
    of the CIE.  Default to 1 if not otherwise specified.  */
-#ifndef DWARF2_LINE_MIN_INSN_LENGTH
+#ifndef  DWARF2_LINE_MIN_INSN_LENGTH
 # define DWARF2_LINE_MIN_INSN_LENGTH 1
 #endif
 
@@ -33,20 +33,16 @@
    provide the following definitions.  Otherwise provide them to 
    allow compilation to continue.  */
 #ifndef TARGET_USE_CFIPOP
-# ifndef DWARF2_DEFAULT_RETURN_COLUMN
+# ifndef  DWARF2_DEFAULT_RETURN_COLUMN
 #  define DWARF2_DEFAULT_RETURN_COLUMN 0
 # endif
-# ifndef DWARF2_CIE_DATA_ALIGNMENT
+# ifndef  DWARF2_CIE_DATA_ALIGNMENT
 #  define DWARF2_CIE_DATA_ALIGNMENT 1
 # endif
 #endif
 
 #ifndef EH_FRAME_ALIGNMENT
-# ifdef BFD_ASSEMBLER
-#  define EH_FRAME_ALIGNMENT (bfd_get_arch_size (stdoutput) == 64 ? 3 : 2)
-# else
-#  define EH_FRAME_ALIGNMENT 2
-# endif
+# define EH_FRAME_ALIGNMENT (bfd_get_arch_size (stdoutput) == 64 ? 3 : 2)
 #endif
 
 #ifndef tc_cfi_frame_initial_instructions
@@ -92,6 +88,7 @@ struct fde_entry
   struct cfi_insn_data *data;
   struct cfi_insn_data **last;
   unsigned int return_column;
+  unsigned int signal_frame;
 };
 
 struct cie_entry
@@ -99,6 +96,7 @@ struct cie_entry
   struct cie_entry *next;
   symbolS *start_address;
   unsigned int return_column;
+  unsigned int signal_frame;
   struct cfi_insn_data *first, *last;
 };
 
@@ -341,6 +339,8 @@ cfi_add_CFA_restore_state (void)
       cfa_save_stack = p->next;
       free (p);
     }
+  else
+    as_bad (_("CFI state restore without previous remember"));
 }
 
 
@@ -356,6 +356,7 @@ static void dot_cfi_endproc (int);
 #define CFI_return_column	0x101
 #define CFI_rel_offset		0x102
 #define CFI_escape		0x103
+#define CFI_signal_frame	0x104
 
 const pseudo_typeS cfi_pseudo_table[] =
   {
@@ -376,6 +377,7 @@ const pseudo_typeS cfi_pseudo_table[] =
     { "cfi_restore_state", dot_cfi, DW_CFA_restore_state },
     { "cfi_window_save", dot_cfi, DW_CFA_GNU_window_save },
     { "cfi_escape", dot_cfi_escape, 0 },
+    { "cfi_signal_frame", dot_cfi, CFI_signal_frame },
     { NULL, NULL, 0 }
   };
 
@@ -417,7 +419,7 @@ cfi_parse_reg (void)
     }
 #endif
 
-  expression (&exp);
+  expression_and_evaluate (&exp);
   switch (exp.X_op)
     {
     case O_register:
@@ -449,6 +451,7 @@ dot_cfi (int arg)
   if (!cur_fde_data)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
       return;
     }
 
@@ -503,13 +506,27 @@ dot_cfi (int arg)
       break;
 
     case DW_CFA_restore:
-      reg1 = cfi_parse_reg ();
-      cfi_add_CFA_restore (reg1);
+      for (;;)
+	{
+	  reg1 = cfi_parse_reg ();
+	  cfi_add_CFA_restore (reg1);
+	  SKIP_WHITESPACE ();
+	  if (*input_line_pointer != ',')
+	    break;
+	  ++input_line_pointer;
+	}
       break;
 
     case DW_CFA_undefined:
-      reg1 = cfi_parse_reg ();
-      cfi_add_CFA_undefined (reg1);
+      for (;;)
+	{
+	  reg1 = cfi_parse_reg ();
+	  cfi_add_CFA_undefined (reg1);
+	  SKIP_WHITESPACE ();
+	  if (*input_line_pointer != ',')
+	    break;
+	  ++input_line_pointer;
+	}
       break;
 
     case DW_CFA_same_value:
@@ -534,6 +551,10 @@ dot_cfi (int arg)
       cfi_add_CFA_insn (DW_CFA_GNU_window_save);
       break;
 
+    case CFI_signal_frame:
+      cur_fde_data->signal_frame = 1;
+      break;
+
     default:
       abort ();
     }
@@ -550,6 +571,7 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
   if (!cur_fde_data)
     {
       as_bad (_("CFI instruction used without previous .cfi_startproc"));
+      ignore_rest_of_line ();
       return;
     }
 
@@ -572,6 +594,9 @@ dot_cfi_escape (int ignored ATTRIBUTE_UNUSED)
   insn = alloc_cfi_insn_data ();
   insn->insn = CFI_escape;
   insn->u.esc = head;
+
+  --input_line_pointer;
+  demand_empty_rest_of_line ();
 }
 
 static void
@@ -582,6 +607,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
   if (cur_fde_data)
     {
       as_bad (_("previous CFI entry not closed (missing .cfi_endproc)"));
+      ignore_rest_of_line ();
       return;
     }
 
@@ -605,6 +631,7 @@ dot_cfi_startproc (int ignored ATTRIBUTE_UNUSED)
     }
   demand_empty_rest_of_line ();
 
+  cur_cfa_offset = 0;
   if (!simple)
     tc_cfi_frame_initial_instructions ();
 }
@@ -615,10 +642,13 @@ dot_cfi_endproc (int ignored ATTRIBUTE_UNUSED)
   if (! cur_fde_data)
     {
       as_bad (_(".cfi_endproc without corresponding .cfi_startproc"));
+      ignore_rest_of_line ();
       return;
     }
 
   cfi_end_fde (symbol_temp_new_now ());
+
+  demand_empty_rest_of_line ();
 }
 
 
@@ -726,7 +756,7 @@ output_cfi_insn (struct cfi_insn_data *insn)
 	{
 	  out_one (DW_CFA_def_cfa_sf);
 	  out_uleb128 (insn->u.ri.reg);
-	  out_uleb128 (offset);
+	  out_sleb128 (offset / DWARF2_CIE_DATA_ALIGNMENT);
 	}
       else
 	{
@@ -748,7 +778,7 @@ output_cfi_insn (struct cfi_insn_data *insn)
       if (offset < 0)
 	{
 	  out_one (DW_CFA_def_cfa_offset_sf);
-	  out_sleb128 (offset);
+	  out_sleb128 (offset / DWARF2_CIE_DATA_ALIGNMENT);
 	}
       else
 	{
@@ -836,17 +866,22 @@ output_cie (struct cie_entry *cie)
   exp.X_op_symbol = after_size_address;
   exp.X_add_number = 0;
 
-  emit_expr (&exp, 4);				/* Length */
+  emit_expr (&exp, 4);				/* Length.  */
   symbol_set_value_now (after_size_address);
-  out_four (0);					/* CIE id */
-  out_one (DW_CIE_VERSION);			/* Version */
-  out_one ('z');				/* Augmentation */
+  out_four (0);					/* CIE id.  */
+  out_one (DW_CIE_VERSION);			/* Version.  */
+  out_one ('z');				/* Augmentation.  */
   out_one ('R');
+  if (cie->signal_frame)
+    out_one ('S');
   out_one (0);
-  out_uleb128 (DWARF2_LINE_MIN_INSN_LENGTH);	/* Code alignment */
-  out_sleb128 (DWARF2_CIE_DATA_ALIGNMENT);	/* Data alignment */
-  out_one (cie->return_column);			/* Return column */
-  out_uleb128 (1);				/* Augmentation size */
+  out_uleb128 (DWARF2_LINE_MIN_INSN_LENGTH);	/* Code alignment.  */
+  out_sleb128 (DWARF2_CIE_DATA_ALIGNMENT);	/* Data alignment.  */
+  if (DW_CIE_VERSION == 1)			/* Return column.  */
+    out_one (cie->return_column);
+  else
+    out_uleb128 (cie->return_column);
+  out_uleb128 (1);				/* Augmentation size.  */
 #if defined DIFF_EXPR_OK || defined tc_cfi_emit_pcrel_expr
   out_one (DW_EH_PE_pcrel | DW_EH_PE_sdata4);
 #else
@@ -857,7 +892,7 @@ output_cie (struct cie_entry *cie)
     for (i = cie->first; i != cie->last; i = i->next)
       output_cfi_insn (i);
 
-  frag_align (2, 0, 0);
+  frag_align (2, DW_CFA_nop, 0);
   symbol_set_value_now (end_address);
 }
 
@@ -875,39 +910,39 @@ output_fde (struct fde_entry *fde, struct cie_entry *cie,
   exp.X_add_symbol = end_address;
   exp.X_op_symbol = after_size_address;
   exp.X_add_number = 0;
-  emit_expr (&exp, 4);				/* Length */
+  emit_expr (&exp, 4);				/* Length.  */
   symbol_set_value_now (after_size_address);
 
   exp.X_add_symbol = after_size_address;
   exp.X_op_symbol = cie->start_address;
-  emit_expr (&exp, 4);				/* CIE offset */
+  emit_expr (&exp, 4);				/* CIE offset.  */
 
 #ifdef DIFF_EXPR_OK  
   exp.X_add_symbol = fde->start_address;
   exp.X_op_symbol = symbol_temp_new_now ();
-  emit_expr (&exp, 4);				/* Code offset */
+  emit_expr (&exp, 4);				/* Code offset.  */
 #else
   exp.X_op = O_symbol;
   exp.X_add_symbol = fde->start_address;
   exp.X_op_symbol = NULL;
 #ifdef tc_cfi_emit_pcrel_expr
-  tc_cfi_emit_pcrel_expr (&exp, 4);		/* Code offset */
+  tc_cfi_emit_pcrel_expr (&exp, 4);		/* Code offset.  */
 #else
-  emit_expr (&exp, 4);				/* Code offset */
+  emit_expr (&exp, 4);				/* Code offset.  */
 #endif
   exp.X_op = O_subtract;
 #endif
 
   exp.X_add_symbol = fde->end_address;
-  exp.X_op_symbol = fde->start_address;		/* Code length */
+  exp.X_op_symbol = fde->start_address;		/* Code length.  */
   emit_expr (&exp, 4);
 
-  out_uleb128 (0);				/* Augmentation size */
+  out_uleb128 (0);				/* Augmentation size.  */
 
   for (; first; first = first->next)
     output_cfi_insn (first);
 
-  frag_align (align, 0, 0);
+  frag_align (align, DW_CFA_nop, 0);
   symbol_set_value_now (end_address);
 }
 
@@ -919,7 +954,8 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
 
   for (cie = cie_root; cie; cie = cie->next)
     {
-      if (cie->return_column != fde->return_column)
+      if (cie->return_column != fde->return_column
+	  || cie->signal_frame != fde->signal_frame)
 	continue;
       for (i = cie->first, j = fde->data;
 	   i != cie->last && j != NULL;
@@ -930,8 +966,9 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
 	  switch (i->insn)
 	    {
 	    case DW_CFA_advance_loc:
-	      /* We reached the first advance in the FDE, but did not
-		 reach the end of the CIE list.  */
+	    case DW_CFA_remember_state:
+	      /* We reached the first advance/remember in the FDE,
+		 but did not reach the end of the CIE list.  */
 	      goto fail;
 
 	    case DW_CFA_offset:
@@ -972,8 +1009,13 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
 	}
 
       /* Success if we reached the end of the CIE list, and we've either
-	 run out of FDE entries or we've encountered an advance.  */
-      if (i == cie->last && (!j || j->insn == DW_CFA_advance_loc))
+	 run out of FDE entries or we've encountered an advance,
+	 remember, or escape.  */
+      if (i == cie->last
+	  && (!j
+	      || j->insn == DW_CFA_advance_loc
+	      || j->insn == DW_CFA_remember_state
+	      || j->insn == CFI_escape))
 	{
 	  *pfirst = j;
 	  return cie;
@@ -986,10 +1028,13 @@ select_cie_for_fde (struct fde_entry *fde, struct cfi_insn_data **pfirst)
   cie->next = cie_root;
   cie_root = cie;
   cie->return_column = fde->return_column;
+  cie->signal_frame = fde->signal_frame;
   cie->first = fde->data;
 
   for (i = cie->first; i ; i = i->next)
-    if (i->insn == DW_CFA_advance_loc)
+    if (i->insn == DW_CFA_advance_loc
+	|| i->insn == DW_CFA_remember_state
+	|| i->insn == CFI_escape)
       break;
 
   cie->last = i;
@@ -1018,10 +1063,8 @@ cfi_finish (void)
 
   /* Open .eh_frame section.  */
   cfi_seg = subseg_new (".eh_frame", 0);
-#ifdef BFD_ASSEMBLER
   bfd_set_section_flags (stdoutput, cfi_seg,
 			 SEC_ALLOC | SEC_LOAD | SEC_DATA | SEC_READONLY);
-#endif
   subseg_set (cfi_seg, 0);
   record_alignment (cfi_seg, EH_FRAME_ALIGNMENT);
 
diff --git a/gas/dw2gencfi.h b/gas/dw2gencfi.h
index 75b6ec24610a..53a35fcb68de 100644
--- a/gas/dw2gencfi.h
+++ b/gas/dw2gencfi.h
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef DW2GENCFI_H
 #define DW2GENCFI_H
diff --git a/gas/dwarf2dbg.c b/gas/dwarf2dbg.c
index 3336453a4eef..16666fa4f28d 100644
--- a/gas/dwarf2dbg.c
+++ b/gas/dwarf2dbg.c
@@ -1,5 +1,6 @@
 /* dwarf2dbg.c - DWARF2 debug support
-   Copyright 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+   Free Software Foundation, Inc.
    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
 
    This file is part of GAS, the GNU Assembler.
@@ -16,19 +17,20 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Logical line numbers can be controlled by the compiler via the
-   following two directives:
+   following directives:
 
 	.file FILENO "file.c"
-	.loc  FILENO LINENO [COLUMN]
-
-   FILENO is the filenumber.  */
+	.loc  FILENO LINENO [COLUMN] [basic_block] [prologue_end] \
+	      [epilogue_begin] [is_stmt VALUE] [isa VALUE]
+*/
 
 #include "ansidecl.h"
 #include "as.h"
+#include "safe-ctype.h"
 
 #ifdef HAVE_LIMITS_H
 #include <limits.h>
@@ -52,8 +54,6 @@
 # define DWARF2_ADDR_SIZE(bfd) (bfd_arch_bits_per_address (bfd) / 8)
 #endif
 
-#ifdef BFD_ASSEMBLER
-
 #include "subsegs.h"
 
 #include "elf/dwarf2.h"
@@ -69,8 +69,8 @@
 /* First special line opcde - leave room for the standard opcodes.
    Note: If you want to change this, you'll have to update the
    "standard_opcode_lengths" table that is emitted below in
-   dwarf2_finish().  */
-#define DWARF2_LINE_OPCODE_BASE		10
+   out_debug_line().  */
+#define DWARF2_LINE_OPCODE_BASE		13
 
 #ifndef DWARF2_LINE_BASE
   /* Minimum line offset in a special line info. opcode.  This value
@@ -89,10 +89,7 @@
 # define DWARF2_LINE_MIN_INSN_LENGTH	1
 #endif
 
-/* Flag that indicates the initial value of the is_stmt_start flag.
-   In the present implementation, we do not mark any lines as
-   the beginning of a source statement, because that information
-   is not made available by the GCC front-end.  */
+/* Flag that indicates the initial value of the is_stmt_start flag.  */
 #define	DWARF2_LINE_DEFAULT_IS_STMT	1
 
 /* Given a special op, return the line skip amount.  */
@@ -108,8 +105,7 @@
 
 struct line_entry {
   struct line_entry *next;
-  fragS *frag;
-  addressT frag_ofs;
+  symbolS *label;
   struct dwarf2_line_info loc;
 };
 
@@ -150,8 +146,15 @@ static unsigned int dirs_allocated;
    doing work when there's nothing to do.  */
 static bfd_boolean loc_directive_seen;
 
+/* TRUE when we're supposed to set the basic block mark whenever a
+   label is seen.  */
+bfd_boolean dwarf2_loc_mark_labels;
+
 /* Current location as indicated by the most recent .loc directive.  */
-static struct dwarf2_line_info current;
+static struct dwarf2_line_info current = {
+  1, 1, 0, 0,
+  DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0
+};
 
 /* The size of an address on the target.  */
 static unsigned int sizeof_address;
@@ -167,12 +170,11 @@ static void out_four (int);
 static void out_abbrev (int, int);
 static void out_uleb128 (addressT);
 static offsetT get_frag_fix (fragS *);
-static void out_set_addr (segT, fragS *, addressT);
+static void out_set_addr (symbolS *);
 static int size_inc_line_addr (int, addressT);
 static void emit_inc_line_addr (int, addressT, char *, int);
 static void out_inc_line_addr (int, addressT);
-static void relax_inc_line_addr (int, segT, fragS *, addressT,
-				 fragS *, addressT);
+static void relax_inc_line_addr (int, symbolS *, symbolS *);
 static void process_entries (segT, struct line_entry *);
 static void out_file_list (void);
 static void out_debug_line (segT);
@@ -207,21 +209,21 @@ get_line_subseg (segT seg, subsegT subseg)
   static subsegT last_subseg;
   static struct line_subseg *last_line_subseg;
 
-  struct line_seg *s;
+  struct line_seg **ps, *s;
   struct line_subseg **pss, *ss;
 
   if (seg == last_seg && subseg == last_subseg)
     return last_line_subseg;
 
-  for (s = all_segs; s; s = s->next)
+  for (ps = &all_segs; (s = *ps) != NULL; ps = &s->next)
     if (s->seg == seg)
       goto found_seg;
 
   s = (struct line_seg *) xmalloc (sizeof (*s));
-  s->next = all_segs;
+  s->next = NULL;
   s->seg = seg;
   s->head = NULL;
-  all_segs = s;
+  *ps = s;
 
  found_seg:
   for (pss = &s->head; (ss = *pss) != NULL ; pss = &ss->next)
@@ -247,16 +249,34 @@ get_line_subseg (segT seg, subsegT subseg)
   return ss;
 }
 
+/* Record an entry for LOC occurring at LABEL.  */
+
+static void
+dwarf2_gen_line_info_1 (symbolS *label, struct dwarf2_line_info *loc)
+{
+  struct line_subseg *ss;
+  struct line_entry *e;
+
+  e = (struct line_entry *) xmalloc (sizeof (*e));
+  e->next = NULL;
+  e->label = label;
+  e->loc = *loc;
+
+  ss = get_line_subseg (now_seg, now_subseg);
+  *ss->ptail = e;
+  ss->ptail = &e->next;
+}
+
 /* Record an entry for LOC occurring at OFS within the current fragment.  */
 
 void
 dwarf2_gen_line_info (addressT ofs, struct dwarf2_line_info *loc)
 {
-  struct line_subseg *ss;
-  struct line_entry *e;
   static unsigned int line = -1;
   static unsigned int filenum = -1;
 
+  symbolS *sym;
+
   /* Early out for as-yet incomplete location information.  */
   if (loc->filenum == 0 || loc->line == 0)
     return;
@@ -272,17 +292,15 @@ dwarf2_gen_line_info (addressT ofs, struct dwarf2_line_info *loc)
   line = loc->line;
   filenum = loc->filenum;
 
-  e = (struct line_entry *) xmalloc (sizeof (*e));
-  e->next = NULL;
-  e->frag = frag_now;
-  e->frag_ofs = ofs;
-  e->loc = *loc;
-
-  ss = get_line_subseg (now_seg, now_subseg);
-  *ss->ptail = e;
-  ss->ptail = &e->next;
+  sym = symbol_temp_new (now_seg, ofs, frag_now);
+  dwarf2_gen_line_info_1 (sym, loc);
 }
 
+/* Returns the current source information.  If .file directives have
+   been encountered, the info for the corresponding source file is
+   returned.  Otherwise, the info for the assembly source file is
+   returned.  */
+
 void
 dwarf2_where (struct dwarf2_line_info *line)
 {
@@ -292,12 +310,22 @@ dwarf2_where (struct dwarf2_line_info *line)
       as_where (&filename, &line->line);
       line->filenum = get_filenum (filename, 0);
       line->column = 0;
-      line->flags = DWARF2_FLAG_BEGIN_STMT;
+      line->flags = DWARF2_FLAG_IS_STMT;
+      line->isa = current.isa;
     }
   else
     *line = current;
 }
 
+/* A hook to allow the target backend to inform the line number state 
+   machine of isa changes when assembler debug info is enabled.  */
+
+void
+dwarf2_set_isa (unsigned int isa)
+{
+  current.isa = isa;
+}
+
 /* Called for each machine instruction, or relatively atomic group of
    machine instructions (ie built-in macro).  The instruction or group
    is SIZE bytes in length.  If dwarf2 line number generation is called
@@ -325,9 +353,45 @@ dwarf2_emit_insn (int size)
   else if (debug_type != DEBUG_DWARF2)
     return;
   else
-    dwarf2_where (& loc);
+    dwarf2_where (&loc);
 
   dwarf2_gen_line_info (frag_now_fix () - size, &loc);
+
+  current.flags &= ~(DWARF2_FLAG_BASIC_BLOCK
+		     | DWARF2_FLAG_PROLOGUE_END
+		     | DWARF2_FLAG_EPILOGUE_BEGIN);
+}
+
+/* Called for each (preferably code) label.  If dwarf2_loc_mark_labels
+   is enabled, emit a basic block marker.  */
+
+void
+dwarf2_emit_label (symbolS *label)
+{
+  struct dwarf2_line_info loc;
+
+  if (!dwarf2_loc_mark_labels)
+    return;
+  if (S_GET_SEGMENT (label) != now_seg)
+    return;
+  if (!(bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE))
+    return;
+  
+  if (debug_type == DEBUG_DWARF2)
+    dwarf2_where (&loc);
+  else
+    {
+      loc = current;
+      loc_directive_seen = FALSE;
+    }
+
+  loc.flags |= DWARF2_FLAG_BASIC_BLOCK;
+
+  current.flags &= ~(DWARF2_FLAG_BASIC_BLOCK
+		     | DWARF2_FLAG_PROLOGUE_END
+		     | DWARF2_FLAG_EPILOGUE_BEGIN);
+
+  dwarf2_gen_line_info_1 (label, &loc);
 }
 
 /* Get a .debug_line file number for FILENAME.  If NUM is nonzero,
@@ -420,7 +484,8 @@ get_filenum (const char *filename, unsigned int num)
 
   files[i].filename = num ? file : xstrdup (file);
   files[i].dir = dir;
-  files_in_use = i + 1;
+  if (files_in_use < i + 1)
+    files_in_use = i + 1;
   last_used = i;
   last_used_dir_len = dir_len;
 
@@ -450,6 +515,8 @@ dwarf2_directive_file (int dummy ATTRIBUTE_UNUSED)
 
   num = get_absolute_expression ();
   filename = demand_copy_C_string (&filename_len);
+  if (filename == NULL)
+    return NULL;
   demand_empty_rest_of_line ();
 
   if (num < 1)
@@ -472,14 +539,11 @@ dwarf2_directive_file (int dummy ATTRIBUTE_UNUSED)
 void
 dwarf2_directive_loc (int dummy ATTRIBUTE_UNUSED)
 {
-  offsetT filenum, line, column;
+  offsetT filenum, line;
 
   filenum = get_absolute_expression ();
   SKIP_WHITESPACE ();
   line = get_absolute_expression ();
-  SKIP_WHITESPACE ();
-  column = get_absolute_expression ();
-  demand_empty_rest_of_line ();
 
   if (filenum < 1)
     {
@@ -494,10 +558,6 @@ dwarf2_directive_loc (int dummy ATTRIBUTE_UNUSED)
 
   current.filenum = filenum;
   current.line = line;
-  current.column = column;
-  current.flags = DWARF2_FLAG_BEGIN_STMT;
-
-  loc_directive_seen = TRUE;
 
 #ifndef NO_LISTING
   if (listing)
@@ -519,6 +579,92 @@ dwarf2_directive_loc (int dummy ATTRIBUTE_UNUSED)
       listing_source_line (line);
     }
 #endif
+
+  SKIP_WHITESPACE ();
+  if (ISDIGIT (*input_line_pointer))
+    {
+      current.column = get_absolute_expression ();
+      SKIP_WHITESPACE ();
+    }
+
+  while (ISALPHA (*input_line_pointer))
+    {
+      char *p, c;
+      offsetT value;
+
+      p = input_line_pointer;
+      c = get_symbol_end ();
+
+      if (strcmp (p, "basic_block") == 0)
+	{
+	  current.flags |= DWARF2_FLAG_BASIC_BLOCK;
+	  *input_line_pointer = c;
+	}
+      else if (strcmp (p, "prologue_end") == 0)
+	{
+	  current.flags |= DWARF2_FLAG_PROLOGUE_END;
+	  *input_line_pointer = c;
+	}
+      else if (strcmp (p, "epilogue_begin") == 0)
+	{
+	  current.flags |= DWARF2_FLAG_EPILOGUE_BEGIN;
+	  *input_line_pointer = c;
+	}
+      else if (strcmp (p, "is_stmt") == 0)
+	{
+	  *input_line_pointer = c;
+	  value = get_absolute_expression ();
+	  if (value == 0)
+	    current.flags &= ~DWARF2_FLAG_IS_STMT;
+	  else if (value == 1)
+	    current.flags |= DWARF2_FLAG_IS_STMT;
+	  else
+	    {
+	      as_bad (_("is_stmt value not 0 or 1"));
+	      return;
+	    }
+	}
+      else if (strcmp (p, "isa") == 0)
+	{
+          *input_line_pointer = c;
+	  value = get_absolute_expression ();
+	  if (value >= 0)
+	    current.isa = value;
+	  else
+	    {
+	      as_bad (_("isa number less than zero"));
+	      return;
+	    }
+	}
+      else
+	{
+	  as_bad (_("unknown .loc sub-directive `%s'"), p);
+          *input_line_pointer = c;
+	  return;
+	}
+
+      SKIP_WHITESPACE ();
+    }
+
+  demand_empty_rest_of_line ();
+  loc_directive_seen = TRUE;
+}
+
+void
+dwarf2_directive_loc_mark_labels (int dummy ATTRIBUTE_UNUSED)
+{
+  offsetT value = get_absolute_expression ();
+
+  if (value != 0 && value != 1)
+    {
+      as_bad (_("expected 0 or 1"));
+      ignore_rest_of_line ();
+    }
+  else
+    {
+      dwarf2_loc_mark_labels = value != 0;
+      demand_empty_rest_of_line ();
+    }
 }
 
 static struct frag *
@@ -619,12 +765,9 @@ get_frag_fix (fragS *frag)
 /* Set an absolute address (may result in a relocation entry).  */
 
 static void
-out_set_addr (segT seg, fragS *frag, addressT ofs)
+out_set_addr (symbolS *sym)
 {
   expressionS expr;
-  symbolS *sym;
-
-  sym = symbol_temp_new (seg, ofs, frag);
 
   out_opcode (DW_LNS_extended_op);
   out_uleb128 (sizeof_address + 1);
@@ -728,6 +871,10 @@ emit_inc_line_addr (int line_delta, addressT addr_delta, char *p, int len)
   int need_copy = 0;
   char *end = p + len;
 
+  /* Line number sequences cannot go backward in addresses.  This means
+     we've incorrectly ordered the statements in the sequence.  */
+  assert ((offsetT) addr_delta >= 0);
+
   /* Scale the address delta by the minimum instruction length.  */
   scale_addr_delta (&addr_delta);
 
@@ -760,19 +907,19 @@ emit_inc_line_addr (int line_delta, addressT addr_delta, char *p, int len)
       *p++ = DW_LNS_advance_line;
       p += output_leb128 (p, line_delta, 1);
 
-      /* Prettier, I think, to use DW_LNS_copy instead of a
-	 "line +0, addr +0" special opcode.  */
-      if (addr_delta == 0)
-	{
-	  *p++ = DW_LNS_copy;
-	  goto done;
-	}
-
       line_delta = 0;
       tmp = 0 - DWARF2_LINE_BASE;
       need_copy = 1;
     }
 
+  /* Prettier, I think, to use DW_LNS_copy instead of a "line +0, addr +0"
+     special opcode.  */
+  if (line_delta == 0 && addr_delta == 0)
+    {
+      *p++ = DW_LNS_copy;
+      goto done;
+    }
+
   /* Bias the opcode by the special opcode base.  */
   tmp += DWARF2_LINE_OPCODE_BASE;
 
@@ -823,17 +970,11 @@ out_inc_line_addr (int line_delta, addressT addr_delta)
    increments between fragments of the target segment.  */
 
 static void
-relax_inc_line_addr (int line_delta, segT seg,
-		     fragS *to_frag, addressT to_ofs,
-		     fragS *from_frag, addressT from_ofs)
+relax_inc_line_addr (int line_delta, symbolS *to_sym, symbolS *from_sym)
 {
-  symbolS *to_sym, *from_sym;
   expressionS expr;
   int max_chars;
 
-  to_sym = symbol_temp_new (seg, to_ofs, to_frag);
-  from_sym = symbol_temp_new (seg, from_ofs, from_frag);
-
   expr.X_op = O_subtract;
   expr.X_add_symbol = to_sym;
   expr.X_op_symbol = from_sym;
@@ -914,23 +1055,22 @@ process_entries (segT seg, struct line_entry *e)
   unsigned filenum = 1;
   unsigned line = 1;
   unsigned column = 0;
-  unsigned flags = DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_BEGIN_STMT : 0;
-  fragS *frag = NULL;
-  fragS *last_frag;
-  addressT frag_ofs = 0;
-  addressT last_frag_ofs;
+  unsigned isa = 0;
+  unsigned flags = DWARF2_LINE_DEFAULT_IS_STMT ? DWARF2_FLAG_IS_STMT : 0;
+  fragS *last_frag = NULL, *frag;
+  addressT last_frag_ofs = 0, frag_ofs;
+  symbolS *last_lab = NULL, *lab;
   struct line_entry *next;
 
-  while (e)
+  do
     {
-      int changed = 0;
+      int line_delta;
 
       if (filenum != e->loc.filenum)
 	{
 	  filenum = e->loc.filenum;
 	  out_opcode (DW_LNS_set_file);
 	  out_uleb128 (filenum);
-	  changed = 1;
 	}
 
       if (column != e->loc.column)
@@ -938,64 +1078,70 @@ process_entries (segT seg, struct line_entry *e)
 	  column = e->loc.column;
 	  out_opcode (DW_LNS_set_column);
 	  out_uleb128 (column);
-	  changed = 1;
 	}
 
-      if ((e->loc.flags ^ flags) & DWARF2_FLAG_BEGIN_STMT)
+      if (isa != e->loc.isa)
 	{
-	  flags = e->loc.flags;
-	  out_opcode (DW_LNS_negate_stmt);
-	  changed = 1;
+	  isa = e->loc.isa;
+	  out_opcode (DW_LNS_set_isa);
+	  out_uleb128 (isa);
 	}
 
-      if (e->loc.flags & DWARF2_FLAG_BEGIN_BLOCK)
+      if ((e->loc.flags ^ flags) & DWARF2_FLAG_IS_STMT)
 	{
-	  out_opcode (DW_LNS_set_basic_block);
-	  changed = 1;
+	  flags = e->loc.flags;
+	  out_opcode (DW_LNS_negate_stmt);
 	}
 
+      if (e->loc.flags & DWARF2_FLAG_BASIC_BLOCK)
+	out_opcode (DW_LNS_set_basic_block);
+
+      if (e->loc.flags & DWARF2_FLAG_PROLOGUE_END)
+	out_opcode (DW_LNS_set_prologue_end);
+
+      if (e->loc.flags & DWARF2_FLAG_EPILOGUE_BEGIN)
+	out_opcode (DW_LNS_set_epilogue_begin);
+
       /* Don't try to optimize away redundant entries; gdb wants two
 	 entries for a function where the code starts on the same line as
 	 the {, and there's no way to identify that case here.  Trust gcc
 	 to optimize appropriately.  */
-      if (1 /* line != e->loc.line || changed */)
-	{
-	  int line_delta = e->loc.line - line;
-	  if (frag == NULL)
-	    {
-	      out_set_addr (seg, e->frag, e->frag_ofs);
-	      out_inc_line_addr (line_delta, 0);
-	    }
-	  else if (frag == e->frag)
-	    out_inc_line_addr (line_delta, e->frag_ofs - frag_ofs);
-	  else
-	    relax_inc_line_addr (line_delta, seg, e->frag, e->frag_ofs,
-				 frag, frag_ofs);
+      line_delta = e->loc.line - line;
+      lab = e->label;
+      frag = symbol_get_frag (lab);
+      frag_ofs = S_GET_VALUE (lab);
 
-	  frag = e->frag;
-	  frag_ofs = e->frag_ofs;
-	  line = e->loc.line;
-	}
-      else if (frag == NULL)
+      if (last_frag == NULL)
 	{
-	  out_set_addr (seg, e->frag, e->frag_ofs);
-	  frag = e->frag;
-	  frag_ofs = e->frag_ofs;
+	  out_set_addr (lab);
+	  out_inc_line_addr (line_delta, 0);
 	}
+      else if (frag == last_frag)
+	out_inc_line_addr (line_delta, frag_ofs - last_frag_ofs);
+      else
+	relax_inc_line_addr (line_delta, lab, last_lab);
+
+      line = e->loc.line;
+      last_lab = lab;
+      last_frag = frag;
+      last_frag_ofs = frag_ofs;
 
       next = e->next;
       free (e);
       e = next;
     }
+  while (e);
 
   /* Emit a DW_LNE_end_sequence for the end of the section.  */
-  last_frag = last_frag_for_seg (seg);
-  last_frag_ofs = get_frag_fix (last_frag);
+  frag = last_frag_for_seg (seg);
+  frag_ofs = get_frag_fix (frag);
   if (frag == last_frag)
-    out_inc_line_addr (INT_MAX, last_frag_ofs - frag_ofs);
+    out_inc_line_addr (INT_MAX, frag_ofs - last_frag_ofs);
   else
-    relax_inc_line_addr (INT_MAX, seg, last_frag, last_frag_ofs,
-			 frag, frag_ofs);
+    {
+      lab = symbol_temp_new (seg, frag_ofs, frag);
+      relax_inc_line_addr (INT_MAX, lab, last_lab);
+    }
 }
 
 /* Emit the directory and file tables for .debug_line.  */
@@ -1116,6 +1262,9 @@ out_debug_line (segT line_seg)
   out_byte (0);			/* DW_LNS_set_basic_block */
   out_byte (0);			/* DW_LNS_const_add_pc */
   out_byte (1);			/* DW_LNS_fixed_advance_pc */
+  out_byte (0);			/* DW_LNS_set_prologue_end */
+  out_byte (0);			/* DW_LNS_set_epilogue_begin */
+  out_byte (1);			/* DW_LNS_set_isa */
 
   out_file_list ();
 
@@ -1349,21 +1498,28 @@ out_debug_info (segT info_seg, segT abbrev_seg, segT line_seg)
   symbol_set_value_now (info_end);
 }
 
+/* Finish the dwarf2 debug sections.  We emit .debug.line if there
+   were any .file/.loc directives, or --gdwarf2 was given, or if the
+   file has a non-empty .debug_info section.  If we emit .debug_line,
+   and the .debug_info section is empty, we also emit .debug_info,
+   .debug_aranges and .debug_abbrev.  ALL_SEGS will be non-null if
+   there were any .file/.loc directives, or --gdwarf2 was given and
+   there were any located instructions emitted.  */
+
 void
 dwarf2_finish (void)
 {
   segT line_seg;
   struct line_seg *s;
+  segT info_seg;
+  int emit_other_sections = 0;
 
-  /* We don't need to do anything unless:
-     - Some debug information was recorded via .file/.loc
-     - or, we are generating DWARF2 information ourself (--gdwarf2)
-     - or, there is a user-provided .debug_info section which could
-       reference the file table in the .debug_line section we generate
-       below.  */
-  if (all_segs == NULL
-      && debug_type != DEBUG_DWARF2
-      && bfd_get_section_by_name (stdoutput, ".debug_info") == NULL)
+  info_seg = bfd_get_section_by_name (stdoutput, ".debug_info");
+  emit_other_sections = info_seg == NULL || !seg_not_empty_p (info_seg);
+
+  if (!all_segs && emit_other_sections)
+    /* There is no line information and no non-empty .debug_info
+       section.  */
     return;
 
   /* Calculate the size of an address for the target machine.  */
@@ -1371,7 +1527,7 @@ dwarf2_finish (void)
 
   /* Create and switch to the line number section.  */
   line_seg = subseg_new (".debug_line", 0);
-  bfd_set_section_flags (stdoutput, line_seg, SEC_READONLY);
+  bfd_set_section_flags (stdoutput, line_seg, SEC_READONLY | SEC_DEBUGGING);
 
   /* For each subsection, chain the debug entries together.  */
   for (s = all_segs; s; s = s->next)
@@ -1388,21 +1544,26 @@ dwarf2_finish (void)
 
   out_debug_line (line_seg);
 
-  /* If this is assembler generated line info, we need .debug_info
-     and .debug_abbrev sections as well.  */
-  if (all_segs != NULL && debug_type == DEBUG_DWARF2)
+  /* If this is assembler generated line info, and there is no
+     debug_info already, we need .debug_info and .debug_abbrev
+     sections as well.  */
+  if (emit_other_sections)
     {
       segT abbrev_seg;
-      segT info_seg;
       segT aranges_seg;
 
+      assert (all_segs);
+      
       info_seg = subseg_new (".debug_info", 0);
       abbrev_seg = subseg_new (".debug_abbrev", 0);
       aranges_seg = subseg_new (".debug_aranges", 0);
 
-      bfd_set_section_flags (stdoutput, info_seg, SEC_READONLY);
-      bfd_set_section_flags (stdoutput, abbrev_seg, SEC_READONLY);
-      bfd_set_section_flags (stdoutput, aranges_seg, SEC_READONLY);
+      bfd_set_section_flags (stdoutput, info_seg,
+			     SEC_READONLY | SEC_DEBUGGING);
+      bfd_set_section_flags (stdoutput, abbrev_seg,
+			     SEC_READONLY | SEC_DEBUGGING);
+      bfd_set_section_flags (stdoutput, aranges_seg,
+			     SEC_READONLY | SEC_DEBUGGING);
 
       record_alignment (aranges_seg, ffs (2 * sizeof_address) - 1);
 
@@ -1411,54 +1572,3 @@ dwarf2_finish (void)
       out_debug_info (info_seg, abbrev_seg, line_seg);
     }
 }
-
-#else
-void
-dwarf2_finish ()
-{
-}
-
-int
-dwarf2dbg_estimate_size_before_relax (frag)
-     fragS *frag ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("dwarf2 is not supported for this object file format"));
-  return 0;
-}
-
-int
-dwarf2dbg_relax_frag (frag)
-     fragS *frag ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("dwarf2 is not supported for this object file format"));
-  return 0;
-}
-
-void
-dwarf2dbg_convert_frag (frag)
-     fragS *frag ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("dwarf2 is not supported for this object file format"));
-}
-
-void
-dwarf2_emit_insn (size)
-     int size ATTRIBUTE_UNUSED;
-{
-}
-
-char *
-dwarf2_directive_file (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  s_app_file (0);
-  return NULL;
-}
-
-void
-dwarf2_directive_loc (dummy)
-     int dummy ATTRIBUTE_UNUSED;
-{
-  as_fatal (_("dwarf2 is not supported for this object file format"));
-}
-#endif /* BFD_ASSEMBLER */
diff --git a/gas/dwarf2dbg.h b/gas/dwarf2dbg.h
index fe8bf277eaa5..cd1d17b2031f 100644
--- a/gas/dwarf2dbg.h
+++ b/gas/dwarf2dbg.h
@@ -1,5 +1,5 @@
 /* dwarf2dbg.h - DWARF2 debug support
-   Copyright 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,21 +15,24 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef AS_DWARF2DBG_H
 #define AS_DWARF2DBG_H
 
 #include "as.h"
 
-#define DWARF2_FLAG_BEGIN_STMT	(1 << 0)	/* beginning of statement */
-#define DWARF2_FLAG_BEGIN_BLOCK	(1 << 1)	/* beginning of basic block */
+#define DWARF2_FLAG_IS_STMT		(1 << 0)
+#define DWARF2_FLAG_BASIC_BLOCK		(1 << 1)
+#define DWARF2_FLAG_PROLOGUE_END	(1 << 2)
+#define DWARF2_FLAG_EPILOGUE_BEGIN	(1 << 3)
 
 struct dwarf2_line_info {
   unsigned int filenum;
   unsigned int line;
   unsigned int column;
+  unsigned int isa;
   unsigned int flags;
 };
 
@@ -46,12 +49,19 @@ extern char *dwarf2_directive_file (int dummy);
    used.  */
 extern void dwarf2_directive_loc (int dummy);
 
+/* Implements the .loc_mark_labels {0,1} directive.  */
+extern void dwarf2_directive_loc_mark_labels (int dummy);
+
 /* Returns the current source information.  If .file directives have
    been encountered, the info for the corresponding source file is
    returned.  Otherwise, the info for the assembly source file is
    returned.  */
 extern void dwarf2_where (struct dwarf2_line_info *l);
 
+/* A hook to allow the target backend to inform the line number state 
+   machine of isa changes when assembler debug info is enabled.  */
+extern void dwarf2_set_isa (unsigned int isa);
+
 /* This function generates .debug_line info based on the address and
    source information passed in the arguments.  ADDR should be the
    frag-relative offset of the instruction the information is for and
@@ -62,6 +72,14 @@ extern void dwarf2_gen_line_info (addressT addr, struct dwarf2_line_info *l);
 /* Must be called for each generated instruction.  */
 extern void dwarf2_emit_insn (int);
 
+/* Should be called for each code label.  */
+extern void dwarf2_emit_label (symbolS *);
+
+/* True when we're supposed to set the basic block mark whenever a label
+   is seen.  Unless the target is doing Something Weird, just call 
+   dwarf2_emit_label.  */
+bfd_boolean dwarf2_loc_mark_labels;
+
 extern void dwarf2_finish (void);
 
 extern int dwarf2dbg_estimate_size_before_relax (fragS *);
diff --git a/gas/ecoff.c b/gas/ecoff.c
index 1de823e24dfa..45116e86db0d 100644
--- a/gas/ecoff.c
+++ b/gas/ecoff.c
@@ -1,5 +1,6 @@
 /* ECOFF debugging support.
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
+   2003, 2004, 2005
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    This file was put together by Ian Lance Taylor <ian@cygnus.com>.  A
@@ -20,8 +21,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
@@ -2312,7 +2313,7 @@ add_file (const char *file_name, int indx ATTRIBUTE_UNUSED, int fake)
    compiler output, only in hand coded assembler.  */
 
 void
-ecoff_new_file (const char *name)
+ecoff_new_file (const char *name, int appfile ATTRIBUTE_UNUSED)
 {
   if (cur_file_ptr != NULL && strcmp (cur_file_ptr->name, name) == 0)
     return;
@@ -3185,14 +3186,10 @@ ecoff_directive_frame (int ignore ATTRIBUTE_UNUSED)
 
   cur_proc_ptr->pdr.pcreg = tc_get_register (0);
 
-#if 0
   /* Alpha-OSF1 adds "the offset of saved $a0 from $sp", according to
      Sandro.  I don't yet know where this value should be stored, if
-     anywhere.  */
-  demand_empty_rest_of_line ();
-#else
+     anywhere.  Don't call demand_empty_rest_of_line ().  */
   s_ignore (42);
-#endif
 }
 
 /* Parse .mask directives.  */
@@ -3685,6 +3682,8 @@ ecoff_build_lineno (const struct ecoff_debug_swap *backend,
   iline = 0;
   totcount = 0;
 
+  /* FIXME?  Now that MIPS embedded-PIC is gone, it may be safe to
+     remove this code.  */
   /* For some reason the address of the first procedure is ignored
      when reading line numbers.  This doesn't matter if the address of
      the first procedure is 0, but when gcc is generating MIPS
diff --git a/gas/ecoff.h b/gas/ecoff.h
index 2f09afca857e..3fa1293c6da4 100644
--- a/gas/ecoff.h
+++ b/gas/ecoff.h
@@ -1,5 +1,5 @@
 /* ecoff.h -- header file for ECOFF debugging support
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2003, 2005
    Free Software Foundation, Inc.
    Contributed by Cygnus Support.
    Put together by Ian Lance Taylor <ian@cygnus.com>.
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef GAS_ECOFF_H
 #define GAS_ECOFF_H
@@ -38,7 +38,7 @@ extern void ecoff_read_begin_hook (void);
 
 /* This function should be called when the assembler switches to a new
    file.  */
-extern void ecoff_new_file (const char *);
+extern void ecoff_new_file (const char *, int);
 
 /* This function should be called when a new symbol is created, by
    obj_symbol_new_hook.  */
diff --git a/gas/ehopt.c b/gas/ehopt.c
index 451aaff18c94..6b0ac5132370 100644
--- a/gas/ehopt.c
+++ b/gas/ehopt.c
@@ -1,5 +1,5 @@
 /* ehopt.c--optimize gcc exception frame information.
-   Copyright 1998, 2000, 2001, 2003 Free Software Foundation, Inc.
+   Copyright 1998, 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
    Written by Ian Lance Taylor <ian@cygnus.com>.
 
 This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+02110-1301, USA.  */
 
 #include "as.h"
 #include "subsegs.h"
@@ -111,16 +111,8 @@ get_cie_info (struct cie_info *info)
 
   /* We should find the CIE at the start of the section.  */
 
-#if defined (BFD_ASSEMBLER) || defined (MANY_SEGMENTS)
   f = seg_info (now_seg)->frchainP->frch_root;
-#else
-  f = frchain_now->frch_root;
-#endif
-#ifdef BFD_ASSEMBLER
   fix = seg_info (now_seg)->frchainP->fix_root;
-#else
-  fix = *seg_fix_rootP;
-#endif
 
   /* Look through the frags of the section to find the code alignment.  */
 
diff --git a/gas/emul-target.h b/gas/emul-target.h
index 4c1a02a500f0..506fc61f6e24 100644
--- a/gas/emul-target.h
+++ b/gas/emul-target.h
@@ -1,5 +1,5 @@
 /* emul-target.h.  Default values for struct emulation defined in emul.h
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 1995 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef emul_init
 #define emul_init			common_emul_init
diff --git a/gas/emul.h b/gas/emul.h
index e4afa68339f0..6e89ae9efa6d 100644
--- a/gas/emul.h
+++ b/gas/emul.h
@@ -1,5 +1,5 @@
 /* emul.h.  File format emulation routines
-   Copyright 2001 Free Software Foundation, Inc.
+   Copyright 1995, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef EMUL_DEFS
 #define EMUL_DEFS
diff --git a/gas/expr.c b/gas/expr.c
index d520a04bcd30..69f0aaccdb64 100644
--- a/gas/expr.c
+++ b/gas/expr.c
@@ -1,6 +1,6 @@
 /* expr.c -operands, expressions-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002
+   1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This is really a branch office of as-read.c. I split it out to clearly
    distinguish the world of expressions from the world of statements.
@@ -41,7 +41,7 @@ static void integer_constant (int radix, expressionS * expressionP);
 static void mri_char_constant (expressionS *);
 static void current_location (expressionS *);
 static void clean_up_expression (expressionS * expressionP);
-static segT operand (expressionS *);
+static segT operand (expressionS *, enum expr_mode);
 static operatorT operator (int *);
 
 extern const char EXP_CHARS[], FLT_CHARS[];
@@ -157,33 +157,6 @@ expr_build_uconstant (offsetT value)
   return make_expr_symbol (&e);
 }
 
-/* Build an expression for OP s1.  */
-
-symbolS *
-expr_build_unary (operatorT op, symbolS *s1)
-{
-  expressionS e;
-
-  e.X_op = op;
-  e.X_add_symbol = s1;
-  e.X_add_number = 0;
-  return make_expr_symbol (&e);
-}
-
-/* Build an expression for s1 OP s2.  */
-
-symbolS *
-expr_build_binary (operatorT op, symbolS *s1, symbolS *s2)
-{
-  expressionS e;
-
-  e.X_op = op;
-  e.X_add_symbol = s1;
-  e.X_op_symbol = s2;
-  e.X_add_number = 0;
-  return make_expr_symbol (&e);
-}
-
 /* Build an expression for the current location ('.').  */
 
 symbolS *
@@ -213,8 +186,6 @@ FLONUM_TYPE generic_floating_point_number = {
   0				/* sign.  */
 };
 
-/* If nonzero, we've been asked to assemble nan, +inf or -inf.  */
-int generic_floating_point_magic;
 
 static void
 floating_constant (expressionS *expressionP)
@@ -330,7 +301,10 @@ integer_constant (int radix, expressionS *expressionP)
 	{
 	  c = *--suffix;
 	  c = TOUPPER (c);
-	  if (c == 'B')
+	  /* If we have both NUMBERS_WITH_SUFFIX and LOCAL_LABELS_FB,
+	     we distinguish between 'B' and 'b'.  This is the case for
+	     Z80.  */
+	  if ((NUMBERS_WITH_SUFFIX && LOCAL_LABELS_FB ? *suffix : c) == 'B')
 	    radix = 2;
 	  else if (c == 'D')
 	    radix = 10;
@@ -609,10 +583,6 @@ integer_constant (int radix, expressionS *expressionP)
       else
 	{
 	  expressionP->X_op = O_constant;
-#ifdef TARGET_WORD_SIZE
-	  /* Sign extend NUMBER.  */
-	  number |= (-(number >> (TARGET_WORD_SIZE - 1))) << (TARGET_WORD_SIZE - 1);
-#endif
 	  expressionP->X_add_number = number;
 	  input_line_pointer--;	/* Restore following character.  */
 	}			/* Really just a number.  */
@@ -741,7 +711,7 @@ current_location (expressionS *expressionp)
 	Input_line_pointer->(next non-blank) char after operand.  */
 
 static segT
-operand (expressionS *expressionP)
+operand (expressionS *expressionP, enum expr_mode mode)
 {
   char c;
   symbolS *symbolP;	/* Points to symbol.  */
@@ -977,16 +947,14 @@ operand (expressionS *expressionP)
     case '[':
 #endif
       /* Didn't begin with digit & not a name.  */
-      segment = expression (expressionP);
+      if (mode != expr_defer)
+	segment = expression (expressionP);
+      else
+	segment = deferred_expression (expressionP);
       /* expression () will pass trailing whitespace.  */
       if ((c == '(' && *input_line_pointer != ')')
 	  || (c == '[' && *input_line_pointer != ']'))
-	{
-#ifdef RELAX_PAREN_GROUPING
-	  if (c != '(')
-#endif
-	    as_bad (_("missing '%c'"), c == '(' ? ')' : ']');
-	}
+	as_bad (_("missing '%c'"), c == '(' ? ')' : ']');
       else
 	input_line_pointer++;
       SKIP_WHITESPACE ();
@@ -1020,14 +988,6 @@ operand (expressionS *expressionP)
       mri_char_constant (expressionP);
       break;
 
-    case '+':
-      /* Do not accept ++e as +(+e).
-	 Disabled, since the preprocessor removes whitespace.  */
-      if (0 && *input_line_pointer == '+')
-	goto target_op;
-      (void) operand (expressionP);
-      break;
-
 #ifdef TC_M68K
     case '"':
       /* Double quote is the bitwise not operator in MRI mode.  */
@@ -1041,13 +1001,14 @@ operand (expressionS *expressionP)
 	goto isname;
     case '!':
     case '-':
+    case '+':
       {
-        /* Do not accept --e as -(-e)
+	/* Do not accept ++e or --e as +(+e) or -(-e)
 	   Disabled, since the preprocessor removes whitespace.  */
-	if (0 && c == '-' && *input_line_pointer == '-')
+	if (0 && (c == '-' || c == '+') && *input_line_pointer == c)
 	  goto target_op;
 	
-	operand (expressionP);
+	operand (expressionP, mode);
 	if (expressionP->X_op == O_constant)
 	  {
 	    /* input_line_pointer -> char after operand.  */
@@ -1061,7 +1022,7 @@ operand (expressionS *expressionP)
 	      }
 	    else if (c == '~' || c == '"')
 	      expressionP->X_add_number = ~ expressionP->X_add_number;
-	    else
+	    else if (c == '!')
 	      expressionP->X_add_number = ! expressionP->X_add_number;
 	  }
 	else if (expressionP->X_op == O_big
@@ -1076,17 +1037,49 @@ operand (expressionS *expressionP)
 	    else
 	      generic_floating_point_number.sign = 'N';
 	  }
+	else if (expressionP->X_op == O_big
+		 && expressionP->X_add_number > 0)
+	  {
+	    int i;
+
+	    if (c == '~' || c == '-')
+	      {
+		for (i = 0; i < expressionP->X_add_number; ++i)
+		  generic_bignum[i] = ~generic_bignum[i];
+		if (c == '-')
+		  for (i = 0; i < expressionP->X_add_number; ++i)
+		    {
+		      generic_bignum[i] += 1;
+		      if (generic_bignum[i])
+			break;
+		    }
+	      }
+	    else if (c == '!')
+	      {
+		int nonzero = 0;
+		for (i = 0; i < expressionP->X_add_number; ++i)
+		  {
+		    if (generic_bignum[i])
+		      nonzero = 1;
+		    generic_bignum[i] = 0;
+		  }
+		generic_bignum[0] = nonzero;
+	      }
+	  }
 	else if (expressionP->X_op != O_illegal
 		 && expressionP->X_op != O_absent)
 	  {
-	    expressionP->X_add_symbol = make_expr_symbol (expressionP);
-	    if (c == '-')
-	      expressionP->X_op = O_uminus;
-	    else if (c == '~' || c == '"')
-	      expressionP->X_op = O_bit_not;
-	    else
-	      expressionP->X_op = O_logical_not;
-	    expressionP->X_add_number = 0;
+	    if (c != '+')
+	      {
+		expressionP->X_add_symbol = make_expr_symbol (expressionP);
+		if (c == '-')
+		  expressionP->X_op = O_uminus;
+		else if (c == '~' || c == '"')
+		  expressionP->X_op = O_bit_not;
+		else
+		  expressionP->X_op = O_logical_not;
+		expressionP->X_add_number = 0;
+	      }
 	  }
 	else
 	  as_warn (_("Unary operator %c ignored because bad operand follows"),
@@ -1102,10 +1095,10 @@ operand (expressionS *expressionP)
       if (! flag_m68k_mri)
 	goto de_fault;
 #endif
-      if (flag_m68k_mri && hex_p (*input_line_pointer))
+      if (DOLLAR_AMBIGU && hex_p (*input_line_pointer))
 	{
-	  /* In MRI mode, '$' is also used as the prefix for a
-	     hexadecimal constant.  */
+	  /* In MRI mode and on Z80, '$' is also used as the prefix
+	     for a hexadecimal constant.  */
 	  integer_constant (16, expressionP);
 	  break;
 	}
@@ -1227,7 +1220,7 @@ operand (expressionS *expressionP)
 	     specially in certain contexts.  If a name always has a
 	     specific value, it can often be handled by simply
 	     entering it in the symbol table.  */
-	  if (md_parse_name (name, expressionP, &c))
+	  if (md_parse_name (name, expressionP, mode, &c))
 	    {
 	      *input_line_pointer = c;
 	      break;
@@ -1278,12 +1271,12 @@ operand (expressionS *expressionP)
 	  /* If we have an absolute symbol or a reg, then we know its
 	     value now.  */
 	  segment = S_GET_SEGMENT (symbolP);
-	  if (segment == absolute_section)
+	  if (mode != expr_defer && segment == absolute_section)
 	    {
 	      expressionP->X_op = O_constant;
 	      expressionP->X_add_number = S_GET_VALUE (symbolP);
 	    }
-	  else if (segment == reg_section)
+	  else if (mode != expr_defer && segment == reg_section)
 	    {
 	      expressionP->X_op = O_register;
 	      expressionP->X_add_number = S_GET_VALUE (symbolP);
@@ -1327,6 +1320,9 @@ operand (expressionS *expressionP)
   if (expressionP->X_add_symbol)
     symbol_mark_used (expressionP->X_add_symbol);
 
+  expressionP->X_add_symbol = symbol_clone_if_forward_ref (expressionP->X_add_symbol);
+  expressionP->X_op_symbol = symbol_clone_if_forward_ref (expressionP->X_op_symbol);
+
   switch (expressionP->X_op)
     {
     default:
@@ -1394,6 +1390,9 @@ clean_up_expression (expressionS *expressionP)
 
 #undef __
 #define __ O_illegal
+#ifndef O_SINGLE_EQ
+#define O_SINGLE_EQ O_illegal
+#endif
 
 /* Maps ASCII -> operators.  */
 static const operatorT op_encoding[256] = {
@@ -1403,7 +1402,7 @@ static const operatorT op_encoding[256] = {
   __, O_bit_or_not, __, __, __, O_modulus, O_bit_and, __,
   __, __, O_multiply, O_add, __, O_subtract, __, O_divide,
   __, __, __, __, __, __, __, __,
-  __, __, __, __, O_lt, __, O_gt, __,
+  __, __, __, __, O_lt, O_SINGLE_EQ, O_gt, __,
   __, __, __, __, __, __, __, __,
   __, __, __, __, __, __, __, __,
   __, __, __, __, __, __, __, __,
@@ -1600,15 +1599,21 @@ operator (int *num_chars)
       return ret;
 
     case '!':
-      /* We accept !! as equivalent to ^ for MRI compatibility.  */
-      if (input_line_pointer[1] != '!')
+      switch (input_line_pointer[1])
 	{
+	case '!':
+	  /* We accept !! as equivalent to ^ for MRI compatibility. */
+	  *num_chars = 2;
+	  return O_bit_exclusive_or;
+	case '=':
+	  /* We accept != as equivalent to <>.  */
+	  *num_chars = 2;
+	  return O_ne;
+	default:
 	  if (flag_m68k_mri)
 	    return O_bit_inclusive_or;
 	  return op_encoding[c];
 	}
-      *num_chars = 2;
-      return O_bit_exclusive_or;
 
     case '|':
       if (input_line_pointer[1] != '|')
@@ -1632,7 +1637,8 @@ operator (int *num_chars)
 
 segT
 expr (int rankarg,		/* Larger # is higher rank.  */
-      expressionS *resultP	/* Deliver result here.  */)
+      expressionS *resultP,	/* Deliver result here.  */
+      enum expr_mode mode	/* Controls behavior.  */)
 {
   operator_rankT rank = (operator_rankT) rankarg;
   segT retval;
@@ -1647,7 +1653,7 @@ expr (int rankarg,		/* Larger # is higher rank.  */
   if (rank == 0)
     dot_value = frag_now_fix ();
 
-  retval = operand (resultP);
+  retval = operand (resultP, mode);
 
   /* operand () gobbles spaces.  */
   know (*input_line_pointer != ' ');
@@ -1656,10 +1662,11 @@ expr (int rankarg,		/* Larger # is higher rank.  */
   while (op_left != O_illegal && op_rank[(int) op_left] > rank)
     {
       segT rightseg;
+      bfd_vma frag_off;
 
       input_line_pointer += op_chars;	/* -> after operator.  */
 
-      rightseg = expr (op_rank[(int) op_left], &right);
+      rightseg = expr (op_rank[(int) op_left], &right, mode);
       if (right.X_op == O_absent)
 	{
 	  as_warn (_("missing operand; zero assumed"));
@@ -1687,7 +1694,7 @@ expr (int rankarg,		/* Larger # is higher rank.  */
       know (op_right == O_illegal
 	    || op_rank[(int) op_right] <= op_rank[(int) op_left]);
       know ((int) op_left >= (int) O_multiply
-	    && (int) op_left <= (int) O_logical_or);
+	    && (int) op_left <= (int) O_index);
 
       /* input_line_pointer->after right-hand quantity.  */
       /* left-hand quantity in resultP.  */
@@ -1735,12 +1742,15 @@ expr (int rankarg,		/* Larger # is higher rank.  */
       else if (op_left == O_subtract
 	       && right.X_op == O_symbol
 	       && resultP->X_op == O_symbol
-	       && (symbol_get_frag (right.X_add_symbol)
-		   == symbol_get_frag (resultP->X_add_symbol))
+	       && retval == rightseg
 	       && (SEG_NORMAL (rightseg)
-		   || right.X_add_symbol == resultP->X_add_symbol))
+		   || right.X_add_symbol == resultP->X_add_symbol)
+	       && frag_offset_fixed_p (symbol_get_frag (resultP->X_add_symbol),
+				       symbol_get_frag (right.X_add_symbol),
+				       &frag_off))
 	{
 	  resultP->X_add_number -= right.X_add_number;
+	  resultP->X_add_number -= frag_off / OCTETS_PER_BYTE;
 	  resultP->X_add_number += (S_GET_VALUE (resultP->X_add_symbol)
 				    - S_GET_VALUE (right.X_add_symbol));
 	  resultP->X_op = O_constant;
@@ -1874,8 +1884,269 @@ expr (int rankarg,		/* Larger # is higher rank.  */
   if (resultP->X_add_symbol)
     symbol_mark_used (resultP->X_add_symbol);
 
+  if (rank == 0 && mode == expr_evaluate)
+    resolve_expression (resultP);
+
   return resultP->X_op == O_constant ? absolute_section : retval;
 }
+
+/* Resolve an expression without changing any symbols/sub-expressions
+   used.  */
+
+int
+resolve_expression (expressionS *expressionP)
+{
+  /* Help out with CSE.  */
+  valueT final_val = expressionP->X_add_number;
+  symbolS *add_symbol = expressionP->X_add_symbol;
+  symbolS *op_symbol = expressionP->X_op_symbol;
+  operatorT op = expressionP->X_op;
+  valueT left, right;
+  segT seg_left, seg_right;
+  fragS *frag_left, *frag_right;
+  bfd_vma frag_off;
+
+  switch (op)
+    {
+    default:
+      return 0;
+
+    case O_constant:
+    case O_register:
+      left = 0;
+      break;
+
+    case O_symbol:
+    case O_symbol_rva:
+      if (!snapshot_symbol (&add_symbol, &left, &seg_left, &frag_left))
+	return 0;
+
+      break;
+
+    case O_uminus:
+    case O_bit_not:
+    case O_logical_not:
+      if (!snapshot_symbol (&add_symbol, &left, &seg_left, &frag_left))
+	return 0;
+
+      if (seg_left != absolute_section)
+	return 0;
+
+      if (op == O_logical_not)
+	left = !left;
+      else if (op == O_uminus)
+	left = -left;
+      else
+	left = ~left;
+      op = O_constant;
+      break;
+
+    case O_multiply:
+    case O_divide:
+    case O_modulus:
+    case O_left_shift:
+    case O_right_shift:
+    case O_bit_inclusive_or:
+    case O_bit_or_not:
+    case O_bit_exclusive_or:
+    case O_bit_and:
+    case O_add:
+    case O_subtract:
+    case O_eq:
+    case O_ne:
+    case O_lt:
+    case O_le:
+    case O_ge:
+    case O_gt:
+    case O_logical_and:
+    case O_logical_or:
+      if (!snapshot_symbol (&add_symbol, &left, &seg_left, &frag_left)
+	  || !snapshot_symbol (&op_symbol, &right, &seg_right, &frag_right))
+	return 0;
+
+      /* Simplify addition or subtraction of a constant by folding the
+	 constant into X_add_number.  */
+      if (op == O_add)
+	{
+	  if (seg_right == absolute_section)
+	    {
+	      final_val += right;
+	      op = O_symbol;
+	      break;
+	    }
+	  else if (seg_left == absolute_section)
+	    {
+	      final_val += left;
+	      left = right;
+	      seg_left = seg_right;
+	      add_symbol = op_symbol;
+	      op = O_symbol;
+	      break;
+	    }
+	}
+      else if (op == O_subtract)
+	{
+	  if (seg_right == absolute_section)
+	    {
+	      final_val -= right;
+	      op = O_symbol;
+	      break;
+	    }
+	}
+
+      /* Equality and non-equality tests are permitted on anything.
+	 Subtraction, and other comparison operators are permitted if
+	 both operands are in the same section.
+	 Shifts by constant zero are permitted on anything.
+	 Multiplies, bit-ors, and bit-ands with constant zero are
+	 permitted on anything.
+	 Multiplies and divides by constant one are permitted on
+	 anything.
+	 Binary operations with both operands being the same register
+	 or undefined symbol are permitted if the result doesn't depend
+	 on the input value.
+	 Otherwise, both operands must be absolute.  We already handled
+	 the case of addition or subtraction of a constant above.  */
+      frag_off = 0;
+      if (!(seg_left == absolute_section
+	       && seg_right == absolute_section)
+	  && !(op == O_eq || op == O_ne)
+	  && !((op == O_subtract
+		|| op == O_lt || op == O_le || op == O_ge || op == O_gt)
+	       && seg_left == seg_right
+	       && (finalize_syms
+		   || frag_offset_fixed_p (frag_left, frag_right, &frag_off))
+	       && (seg_left != reg_section || left == right)
+	       && (seg_left != undefined_section || add_symbol == op_symbol)))
+	{
+	  if ((seg_left == absolute_section && left == 0)
+	      || (seg_right == absolute_section && right == 0))
+	    {
+	      if (op == O_bit_exclusive_or || op == O_bit_inclusive_or)
+		{
+		  if (seg_right != absolute_section || right != 0)
+		    {
+		      seg_left = seg_right;
+		      left = right;
+		      add_symbol = op_symbol;
+		    }
+		  op = O_symbol;
+		  break;
+		}
+	      else if (op == O_left_shift || op == O_right_shift)
+		{
+		  if (seg_left != absolute_section || left != 0)
+		    {
+		      op = O_symbol;
+		      break;
+		    }
+		}
+	      else if (op != O_multiply
+		       && op != O_bit_or_not && op != O_bit_and)
+	        return 0;
+	    }
+	  else if (op == O_multiply
+		   && seg_left == absolute_section && left == 1)
+	    {
+	      seg_left = seg_right;
+	      left = right;
+	      add_symbol = op_symbol;
+	      op = O_symbol;
+	      break;
+	    }
+	  else if ((op == O_multiply || op == O_divide)
+		   && seg_right == absolute_section && right == 1)
+	    {
+	      op = O_symbol;
+	      break;
+	    }
+	  else if (left != right
+		   || ((seg_left != reg_section || seg_right != reg_section)
+		       && (seg_left != undefined_section
+			   || seg_right != undefined_section
+			   || add_symbol != op_symbol)))
+	    return 0;
+	  else if (op == O_bit_and || op == O_bit_inclusive_or)
+	    {
+	      op = O_symbol;
+	      break;
+	    }
+	  else if (op != O_bit_exclusive_or && op != O_bit_or_not)
+	    return 0;
+	}
+
+      right += frag_off / OCTETS_PER_BYTE;
+      switch (op)
+	{
+	case O_add:			left += right; break;
+	case O_subtract:		left -= right; break;
+	case O_multiply:		left *= right; break;
+	case O_divide:
+	  if (right == 0)
+	    return 0;
+	  left = (offsetT) left / (offsetT) right;
+	  break;
+	case O_modulus:
+	  if (right == 0)
+	    return 0;
+	  left = (offsetT) left % (offsetT) right;
+	  break;
+	case O_left_shift:		left <<= right; break;
+	case O_right_shift:		left >>= right; break;
+	case O_bit_inclusive_or:	left |= right; break;
+	case O_bit_or_not:		left |= ~right; break;
+	case O_bit_exclusive_or:	left ^= right; break;
+	case O_bit_and:			left &= right; break;
+	case O_eq:
+	case O_ne:
+	  left = (left == right
+		  && seg_left == seg_right
+		  && (finalize_syms || frag_left == frag_right)
+		  && (seg_left != undefined_section
+		      || add_symbol == op_symbol)
+		  ? ~ (valueT) 0 : 0);
+	  if (op == O_ne)
+	    left = ~left;
+	  break;
+	case O_lt:
+	  left = (offsetT) left <  (offsetT) right ? ~ (valueT) 0 : 0;
+	  break;
+	case O_le:
+	  left = (offsetT) left <= (offsetT) right ? ~ (valueT) 0 : 0;
+	  break;
+	case O_ge:
+	  left = (offsetT) left >= (offsetT) right ? ~ (valueT) 0 : 0;
+	  break;
+	case O_gt:
+	  left = (offsetT) left >  (offsetT) right ? ~ (valueT) 0 : 0;
+	  break;
+	case O_logical_and:	left = left && right; break;
+	case O_logical_or:	left = left || right; break;
+	default:		abort ();
+	}
+
+      op = O_constant;
+      break;
+    }
+
+  if (op == O_symbol)
+    {
+      if (seg_left == absolute_section)
+	op = O_constant;
+      else if (seg_left == reg_section && final_val == 0)
+	op = O_register;
+      else if (add_symbol != expressionP->X_add_symbol)
+	final_val += left;
+      expressionP->X_add_symbol = add_symbol;
+    }
+  expressionP->X_op = op;
+
+  if (op == O_constant || op == O_register)
+    final_val += left;
+  expressionP->X_add_number = final_val;
+
+  return 1;
+}
 
 /* This lives here because it belongs equally in expr.c & read.c.
    expr.c is just a branch office read.c anyway, and putting it
@@ -1912,6 +2183,6 @@ unsigned int
 get_single_number (void)
 {
   expressionS exp;
-  operand (&exp);
+  operand (&exp, expr_normal);
   return exp.X_add_number;
 }
diff --git a/gas/expr.h b/gas/expr.h
index 382dda9b1f24..6b88d0dfe43c 100644
--- a/gas/expr.h
+++ b/gas/expr.h
@@ -1,6 +1,6 @@
 /* expr.h -> header file for expr.c
-   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
-   Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
+   2002, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*
  * By popular demand, we define a struct to represent an expression.
@@ -143,8 +143,17 @@ typedef struct expressionS {
   unsigned short X_md;
 } expressionS;
 
+enum expr_mode
+{
+  expr_evaluate,
+  expr_normal,
+  expr_defer
+};
+
 /* "result" should be type (expressionS *).  */
-#define expression(result) expr (0, result)
+#define expression(result) expr (0, result, expr_normal)
+#define expression_and_evaluate(result) expr (0, result, expr_evaluate)
+#define deferred_expression(result) expr (0, result, expr_defer)
 
 /* If an expression is O_big, look here for its value. These common
    data may be clobbered whenever expr() is called.  */
@@ -160,12 +169,12 @@ typedef char operator_rankT;
 extern char get_symbol_end (void);
 extern void expr_begin (void);
 extern void expr_set_precedence (void);
-extern segT expr (int rank, expressionS * resultP);
+extern segT expr (int, expressionS *, enum expr_mode);
 extern unsigned int get_single_number (void);
 extern symbolS *make_expr_symbol (expressionS * expressionP);
 extern int expr_symbol_where (symbolS *, char **, unsigned int *);
 
 extern symbolS *expr_build_uconstant (offsetT);
-extern symbolS *expr_build_unary (operatorT, symbolS *);
-extern symbolS *expr_build_binary (operatorT, symbolS *, symbolS *);
 extern symbolS *expr_build_dot (void);
+
+int resolve_expression (expressionS *);
diff --git a/gas/flonum-copy.c b/gas/flonum-copy.c
index e3aba2c4661e..b8b3e5e3cade 100644
--- a/gas/flonum-copy.c
+++ b/gas/flonum-copy.c
@@ -1,5 +1,5 @@
 /* flonum_copy.c - copy a flonum
-   Copyright 1987, 1990, 1991, 1992, 1993, 2000
+   Copyright 1987, 1990, 1991, 1992, 1993, 2000, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
diff --git a/gas/flonum-konst.c b/gas/flonum-konst.c
index 3e606fbfd7d3..9d0cfe6f9c81 100644
--- a/gas/flonum-konst.c
+++ b/gas/flonum-konst.c
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "ansidecl.h"
 #include "flonum.h"
diff --git a/gas/flonum-mult.c b/gas/flonum-mult.c
index 6d17f0a86970..c6dd8ffdd7b1 100644
--- a/gas/flonum-mult.c
+++ b/gas/flonum-mult.c
@@ -1,5 +1,5 @@
 /* flonum_mult.c - multiply two flonums
-   Copyright 1987, 1990, 1991, 1992, 1995, 2000, 2002
+   Copyright 1987, 1990, 1991, 1992, 1995, 2000, 2002, 2003
    Free Software Foundation, Inc.
 
    This file is part of Gas, the GNU Assembler.
diff --git a/gas/flonum.h b/gas/flonum.h
index 22aa7558e835..04f5b8990f98 100644
--- a/gas/flonum.h
+++ b/gas/flonum.h
@@ -1,5 +1,5 @@
 /* flonum.h - Floating point package
-   Copyright 1987, 1990, 1991, 1992, 1994, 1996, 2000
+   Copyright 1987, 1990, 1991, 1992, 1994, 1996, 2000, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /***********************************************************************\
  *									*
diff --git a/gas/frags.c b/gas/frags.c
index 83625d7fbf60..b08ef502cbf7 100644
--- a/gas/frags.c
+++ b/gas/frags.c
@@ -1,6 +1,6 @@
 /* frags.c - manage frags -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2003
+   1999, 2000, 2001, 2003, 2004, 2005, 2006
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 #include "subsegs.h"
@@ -91,7 +91,14 @@ frag_grow (unsigned int nchars)
       frag_wane (frag_now);
       frag_new (0);
       oldc = frchain_now->frch_obstack.chunk_size;
-      frchain_now->frch_obstack.chunk_size = 2 * nchars + SIZEOF_STRUCT_FRAG;
+      /* Try to allocate a bit more than needed right now.  But don't do
+         this if we would waste too much memory.  Especially necessary
+	 for extremely big (like 2GB initialized) frags.  */
+      if (nchars < 0x10000)
+	frchain_now->frch_obstack.chunk_size = 2 * nchars;
+      else
+        frchain_now->frch_obstack.chunk_size = nchars + 0x10000;
+      frchain_now->frch_obstack.chunk_size += SIZEOF_STRUCT_FRAG;
       if (frchain_now->frch_obstack.chunk_size > 0)
 	while ((n = obstack_room (&frchain_now->frch_obstack)) < nchars
 	       && (unsigned long) frchain_now->frch_obstack.chunk_size > nchars)
@@ -376,3 +383,56 @@ frag_append_1_char (int datum)
     }
   obstack_1grow (&frchain_now->frch_obstack, datum);
 }
+
+/* Return TRUE if FRAG1 and FRAG2 have a fixed relationship between
+   their start addresses.  Set OFFSET to the difference in address
+   not already accounted for in the frag FR_ADDRESS.  */
+
+bfd_boolean
+frag_offset_fixed_p (fragS *frag1, fragS *frag2, bfd_vma *offset)
+{
+  fragS *frag;
+  bfd_vma off;
+
+  /* Start with offset initialised to difference between the two frags.
+     Prior to assigning frag addresses this will be zero.  */
+  off = frag1->fr_address - frag2->fr_address;
+  if (frag1 == frag2)
+    {
+      *offset = off;
+      return TRUE;
+    }
+
+  /* Maybe frag2 is after frag1.  */
+  frag = frag1;
+  while (frag->fr_type == rs_fill)
+    {
+      off += frag->fr_fix + frag->fr_offset * frag->fr_var;
+      frag = frag->fr_next;
+      if (frag == NULL)
+	break;
+      if (frag == frag2)
+	{
+	  *offset = off;
+	  return TRUE;
+	}
+    }
+
+  /* Maybe frag1 is after frag2.  */
+  off = frag1->fr_address - frag2->fr_address;
+  frag = frag2;
+  while (frag->fr_type == rs_fill)
+    {
+      off -= frag->fr_fix + frag->fr_offset * frag->fr_var;
+      frag = frag->fr_next;
+      if (frag == NULL)
+	break;
+      if (frag == frag1)
+	{
+	  *offset = off;
+	  return TRUE;
+	}
+    }
+
+  return FALSE;
+}
diff --git a/gas/frags.h b/gas/frags.h
index 52a6cfeb4bd5..880446763a4e 100644
--- a/gas/frags.h
+++ b/gas/frags.h
@@ -1,6 +1,6 @@
 /* frags.h - Header file for the frag concept.
-   Copyright 1987, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001
-   Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001,
+   2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,15 +16,13 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef FRAGS_H
 #define FRAGS_H
 
-#ifdef ANSI_PROTOTYPES
 struct obstack;
-#endif
 
 /* A code fragment (frag) is some known number of chars, followed by some
    unknown number of chars. Typically the unknown number of chars is an
@@ -74,6 +72,11 @@ struct frag {
      fr_address has been adjusted.  */
   unsigned int relax_marker:1;
 
+  /* Used to ensure that all insns are emitted on proper address
+     boundaries.  */
+  unsigned int has_code:1;
+  unsigned int insn_addr:6;
+
   /* What state is my tail in? */
   relax_stateT fr_type;
   relax_substateT fr_subtype;
@@ -114,22 +117,8 @@ COMMON fragS zero_address_frag;
 /* For local common (N_BSS segment) fixups.  */
 COMMON fragS bss_address_frag;
 
-#if 0
-/* A macro to speed up appending exactly 1 char to current frag.  */
-/* JF changed < 1 to <= 1 to avoid a race condition.  */
-#define FRAG_APPEND_1_CHAR(datum)			\
-{							\
-  if (obstack_room (&frags) <= 1)			\
-    {							\
-      frag_wane (frag_now);				\
-      frag_new (0);					\
-    }							\
-  obstack_1grow (&frags, datum);			\
-}
-#else
 extern void frag_append_1_char (int);
 #define FRAG_APPEND_1_CHAR(X) frag_append_1_char (X)
-#endif
 
 void frag_init (void);
 fragS *frag_alloc (struct obstack *);
@@ -159,4 +148,6 @@ char *frag_var (relax_stateT type,
 		offsetT offset,
 		char *opcode);
 
+bfd_boolean frag_offset_fixed_p (fragS *, fragS *, bfd_vma *);
+
 #endif /* FRAGS_H */
diff --git a/gas/hash.c b/gas/hash.c
index a7b82987b20f..6977ceeb5328 100644
--- a/gas/hash.c
+++ b/gas/hash.c
@@ -1,6 +1,6 @@
 /* hash.c -- gas hash table code
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999,
-   2000, 2001, 2002
+   2000, 2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This version of the hash table code is a wholescale replacement of
    the old hash table code, which was fairly bad.  This is based on
@@ -33,10 +33,6 @@
 #include "safe-ctype.h"
 #include "obstack.h"
 
-/* The default number of entries to use when creating a hash table.  */
-
-#define DEFAULT_SIZE (4051)
-
 /* An entry in a hash table.  */
 
 struct hash_entry {
@@ -72,21 +68,55 @@ struct hash_control {
 #endif /* HASH_STATISTICS */
 };
 
+/* The default number of entries to use when creating a hash table.
+   Note this value can be reduced to 4051 by using the command line
+   switch --reduce-memory-overheads, or set to other values by using
+   the --hash-size=<NUMBER> switch.  */
+
+static unsigned long gas_hash_table_size = 65537;
+
+void
+set_gas_hash_table_size (unsigned long size)
+{
+  gas_hash_table_size = size;
+}
+
+/* FIXME: This function should be amalgmated with bfd/hash.c:bfd_hash_set_default_size().  */
+static unsigned long
+get_gas_hash_table_size (void)
+{
+  /* Extend this prime list if you want more granularity of hash table size.  */
+  static const unsigned long hash_size_primes[] =
+    {
+      1021, 4051, 8599, 16699, 65537
+    };
+  unsigned int index;
+
+  /* Work out the best prime number near the hash_size.
+     FIXME: This could be a more sophisticated algorithm,
+     but is it really worth implementing it ?   */
+  for (index = 0; index < ARRAY_SIZE (hash_size_primes) - 1; ++index)
+    if (gas_hash_table_size <= hash_size_primes[index])
+      break;
+
+  return hash_size_primes[index];
+}
+
 /* Create a hash table.  This return a control block.  */
 
 struct hash_control *
 hash_new (void)
 {
-  unsigned int size;
+  unsigned long size;
+  unsigned long alloc;
   struct hash_control *ret;
-  unsigned int alloc;
 
-  size = DEFAULT_SIZE;
+  size = get_gas_hash_table_size ();
 
-  ret = (struct hash_control *) xmalloc (sizeof *ret);
+  ret = xmalloc (sizeof *ret);
   obstack_begin (&ret->memory, chunksize);
   alloc = size * sizeof (struct hash_entry *);
-  ret->table = (struct hash_entry **) obstack_alloc (&ret->memory, alloc);
+  ret->table = obstack_alloc (&ret->memory, alloc);
   memset (ret->table, 0, alloc);
   ret->size = size;
 
@@ -120,19 +150,13 @@ hash_die (struct hash_control *table)
    Each time we look up a string, we move it to the start of the list
    for its hash code, to take advantage of referential locality.  */
 
-static struct hash_entry *hash_lookup (struct hash_control *,
-				       const char *,
-				       struct hash_entry ***,
-				       unsigned long *);
-
 static struct hash_entry *
-hash_lookup (struct hash_control *table, const char *key,
+hash_lookup (struct hash_control *table, const char *key, size_t len,
 	     struct hash_entry ***plist, unsigned long *phash)
 {
-  register unsigned long hash;
-  unsigned int len;
-  register const unsigned char *s;
-  register unsigned int c;
+  unsigned long hash;
+  size_t n;
+  unsigned int c;
   unsigned int index;
   struct hash_entry **list;
   struct hash_entry *p;
@@ -143,13 +167,11 @@ hash_lookup (struct hash_control *table, const char *key,
 #endif
 
   hash = 0;
-  len = 0;
-  s = (const unsigned char *) key;
-  while ((c = *s++) != '\0')
+  for (n = 0; n < len; n++)
     {
+      c = key[n];
       hash += c + (c << 17);
       hash ^= hash >> 2;
-      ++len;
     }
   hash += len + (len << 17);
   hash ^= hash >> 2;
@@ -176,7 +198,7 @@ hash_lookup (struct hash_control *table, const char *key,
 	  ++table->string_compares;
 #endif
 
-	  if (strcmp (p->string, key) == 0)
+	  if (strncmp (p->string, key, len) == 0 && p->string[len] == '\0')
 	    {
 	      if (prev != NULL)
 		{
@@ -207,7 +229,7 @@ hash_insert (struct hash_control *table, const char *key, PTR value)
   struct hash_entry **list;
   unsigned long hash;
 
-  p = hash_lookup (table, key, &list, &hash);
+  p = hash_lookup (table, key, strlen (key), &list, &hash);
   if (p != NULL)
     return "exists";
 
@@ -237,7 +259,7 @@ hash_jam (struct hash_control *table, const char *key, PTR value)
   struct hash_entry **list;
   unsigned long hash;
 
-  p = hash_lookup (table, key, &list, &hash);
+  p = hash_lookup (table, key, strlen (key), &list, &hash);
   if (p != NULL)
     {
 #ifdef HASH_STATISTICS
@@ -274,7 +296,7 @@ hash_replace (struct hash_control *table, const char *key, PTR value)
   struct hash_entry *p;
   PTR ret;
 
-  p = hash_lookup (table, key, NULL, NULL);
+  p = hash_lookup (table, key, strlen (key), NULL, NULL);
   if (p == NULL)
     return NULL;
 
@@ -297,7 +319,22 @@ hash_find (struct hash_control *table, const char *key)
 {
   struct hash_entry *p;
 
-  p = hash_lookup (table, key, NULL, NULL);
+  p = hash_lookup (table, key, strlen (key), NULL, NULL);
+  if (p == NULL)
+    return NULL;
+
+  return p->data;
+}
+
+/* As hash_find, but KEY is of length LEN and is not guaranteed to be
+   NUL-terminated.  */
+
+PTR
+hash_find_n (struct hash_control *table, const char *key, size_t len)
+{
+  struct hash_entry *p;
+
+  p = hash_lookup (table, key, len, NULL, NULL);
   if (p == NULL)
     return NULL;
 
@@ -313,7 +350,7 @@ hash_delete (struct hash_control *table, const char *key)
   struct hash_entry *p;
   struct hash_entry **list;
 
-  p = hash_lookup (table, key, &list, NULL);
+  p = hash_lookup (table, key, strlen (key), &list, NULL);
   if (p == NULL)
     return NULL;
 
diff --git a/gas/hash.h b/gas/hash.h
index 08f41e6c9de5..c2a8a203f94d 100644
--- a/gas/hash.h
+++ b/gas/hash.h
@@ -1,5 +1,6 @@
 /* hash.h -- header file for gas hash table routines
-   Copyright 1987, 1992, 1993, 1995, 1999 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1995, 1999, 2003
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,14 +16,18 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef HASH_H
 #define HASH_H
 
 struct hash_control;
 
+/* Set the size of the hash table used.  */
+
+void set_gas_hash_table_size (unsigned long);
+
 /* Create a hash table.  This return a control block.  */
 
 extern struct hash_control *hash_new (void);
@@ -58,6 +63,11 @@ extern PTR hash_replace (struct hash_control *, const char *key,
 
 extern PTR hash_find (struct hash_control *, const char *key);
 
+/* As hash_find, but KEY is of length LEN and is not guaranteed to be
+   NUL-terminated.  */
+
+extern PTR hash_find_n (struct hash_control *, const char *key, size_t len);
+
 /* Delete an entry from a hash table.  This returns the value stored
    for that entry, or NULL if there is no such entry.  */
 
diff --git a/gas/input-file.c b/gas/input-file.c
index 01cc669feffb..343f0494087c 100644
--- a/gas/input-file.c
+++ b/gas/input-file.c
@@ -1,5 +1,6 @@
 /* input_file.c - Deal with Input Files -
-   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1999, 2000, 2001, 2003
+   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1999, 2000, 2001,
+   2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Confines all details of reading source bytes to this module.
    All O/S specific crocks should live here.
@@ -79,12 +80,6 @@ input_file_buffer_size (void)
   return (BUFFER_SIZE);
 }
 
-int
-input_file_is_open (void)
-{
-  return f_in != (FILE *) 0;
-}
-
 /* Push the state of our input, returning a pointer to saved info that
    can be restored with input_file_pop ().  */
 
@@ -146,21 +141,22 @@ input_file_open (char *filename, /* "" means use stdin. Must not be 0.  */
       file_name = _("{standard input}");
     }
 
-  if (f_in)
-    c = getc (f_in);
+  if (f_in == NULL)
+    {
+      bfd_set_error (bfd_error_system_call);
+      as_perror (_("Can't open %s for reading"), file_name);
+      return;
+    }
+
+  c = getc (f_in);
 
-  if (f_in == NULL || ferror (f_in))
+  if (ferror (f_in))
     {
-#ifdef BFD_ASSEMBLER
       bfd_set_error (bfd_error_system_call);
-#endif
       as_perror (_("Can't open %s for reading"), file_name);
 
-      if (f_in)
-	{
-	  fclose (f_in);
-	  f_in = NULL;
-	}
+      fclose (f_in);
+      f_in = NULL;
       return;
     }
 
@@ -219,9 +215,7 @@ input_file_get (char *buf, int buflen)
   size = fread (buf, sizeof (char), buflen, f_in);
   if (size < 0)
     {
-#ifdef BFD_ASSEMBLER
       bfd_set_error (bfd_error_system_call);
-#endif
       as_perror (_("Can't read from %s"), file_name);
       size = 0;
     }
@@ -248,9 +242,7 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
     size = fread (where, sizeof (char), BUFFER_SIZE, f_in);
   if (size < 0)
     {
-#ifdef BFD_ASSEMBLER
       bfd_set_error (bfd_error_system_call);
-#endif
       as_perror (_("Can't read from %s"), file_name);
       size = 0;
     }
@@ -260,9 +252,7 @@ input_file_give_next_buffer (char *where /* Where to place 1st character of new
     {
       if (fclose (f_in))
 	{
-#ifdef BFD_ASSEMBLER
 	  bfd_set_error (bfd_error_system_call);
-#endif
 	  as_perror (_("Can't close %s"), file_name);
 	}
       f_in = (FILE *) 0;
diff --git a/gas/input-file.h b/gas/input-file.h
index b686a0d06567..bc8289e4e444 100644
--- a/gas/input-file.h
+++ b/gas/input-file.h
@@ -1,5 +1,5 @@
 /* input_file.h header for input-file.c
-   Copyright 1987, 1992, 1993, 2000 Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 2000, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*"input_file.c":Operating-system dependant functions to read source files.*/
 
@@ -58,7 +58,6 @@
 char *input_file_give_next_buffer (char *where);
 char *input_file_push (void);
 unsigned int input_file_buffer_size (void);
-int input_file_is_open (void);
 void input_file_begin (void);
 void input_file_close (void);
 void input_file_end (void);
diff --git a/gas/input-scrub.c b/gas/input-scrub.c
index 7a03965c9672..8562ee25dff3 100644
--- a/gas/input-scrub.c
+++ b/gas/input-scrub.c
@@ -1,6 +1,6 @@
 /* input_scrub.c - Break up input buffers into whole numbers of lines.
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   2000
+   2000, 2001, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <errno.h>		/* Need this to make errno declaration right */
 #include "as.h"
@@ -123,7 +123,6 @@ struct input_save {
 
 static struct input_save *input_scrub_push (char *saved_position);
 static char *input_scrub_pop (struct input_save *arg);
-static void as_1_char (unsigned int c, FILE * stream);
 
 /* Saved information about the file that .include'd this one.  When we hit EOF,
    we automatically pop to that file.  */
@@ -280,7 +279,7 @@ input_scrub_include_sb (sb *from, char *position, int is_expansion)
       /* Add the sentinel required by read.c.  */
       sb_add_char (&from_sb, '\n');
     }
-  sb_add_sb (&from_sb, from);
+  sb_scrub_and_add_sb (&from_sb, from);
   sb_index = 1;
 
   /* These variables are reset by input_scrub_push.  Restore them
@@ -476,39 +475,3 @@ as_where (char **namep, unsigned int *linep)
 	*linep = 0;
     }
 }
-
-/* Output to given stream how much of line we have scanned so far.
-   Assumes we have scanned up to and including input_line_pointer.
-   No free '\n' at end of line.  */
-
-void
-as_howmuch (FILE *stream /* Opened for write please.  */)
-{
-  register char *p;		/* Scan input line.  */
-
-  for (p = input_line_pointer - 1; *p != '\n'; --p)
-    {
-    }
-  ++p;				/* p->1st char of line.  */
-  for (; p <= input_line_pointer; p++)
-    {
-      /* Assume ASCII. EBCDIC & other micro-computer char sets ignored.  */
-      as_1_char ((unsigned char) *p, stream);
-    }
-}
-
-static void
-as_1_char (unsigned int c, FILE *stream)
-{
-  if (c > 127)
-    {
-      (void) putc ('%', stream);
-      c -= 128;
-    }
-  if (c < 32)
-    {
-      (void) putc ('^', stream);
-      c += '@';
-    }
-  (void) putc (c, stream);
-}
diff --git a/gas/itbl-lex.c b/gas/itbl-lex.c
index b10fefb4427c..1180eac13a02 100644
--- a/gas/itbl-lex.c
+++ b/gas/itbl-lex.c
@@ -1,7 +1,7 @@
 /* A lexical scanner generated by flex */
 
 /* Scanner skeleton version:
- * $Header: /cvs/src/src/gas/Attic/itbl-lex.c,v 1.1.12.1 2004/04/09 19:32:17 drow Exp $
+ * $Header: /cvs/src/src/gas/Attic/itbl-lex.c,v 1.1.16.1 2006/04/16 18:36:43 drow Exp $
  */
 
 #define FLEX_SCANNER
@@ -407,7 +407,7 @@ char *yytext;
 #line 1 "itbl-lex.l"
 #define INITIAL 0
 /* itbl-lex.l
-   Copyright 1997, 1998, 2001 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2001, 2002, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -423,13 +423,14 @@ char *yytext;
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 #line 22 "itbl-lex.l"
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
 
+#include "itbl-lex.h"
 #include <itbl-parse.h>
 
 #ifdef DEBUG
@@ -441,7 +442,7 @@ char *yytext;
 #endif
 
 int insntbl_line = 1;
-#line 445 "itbl-lex.c"
+#line 446 "itbl-lex.c"
 
 /* Macros after this point can all be overridden by user definitions in
  * section 1.
@@ -603,10 +604,10 @@ YY_DECL
 	register char *yy_cp, *yy_bp;
 	register int yy_act;
 
-#line 44 "itbl-lex.l"
+#line 45 "itbl-lex.l"
 
 
-#line 610 "itbl-lex.c"
+#line 611 "itbl-lex.c"
 
 	if ( yy_init )
 		{
@@ -691,49 +692,49 @@ do_action:	/* This label is used only to access EOF actions. */
 
 case 1:
 YY_RULE_SETUP
-#line 46 "itbl-lex.l"
+#line 47 "itbl-lex.l"
 {
     return CREG;
   }
 	YY_BREAK
 case 2:
 YY_RULE_SETUP
-#line 49 "itbl-lex.l"
+#line 50 "itbl-lex.l"
 {
     return DREG;
   }
 	YY_BREAK
 case 3:
 YY_RULE_SETUP
-#line 52 "itbl-lex.l"
+#line 53 "itbl-lex.l"
 {
     return GREG;
   }
 	YY_BREAK
 case 4:
 YY_RULE_SETUP
-#line 55 "itbl-lex.l"
+#line 56 "itbl-lex.l"
 {
     return IMMED;
   }
 	YY_BREAK
 case 5:
 YY_RULE_SETUP
-#line 58 "itbl-lex.l"
+#line 59 "itbl-lex.l"
 {
     return ADDR;
   }
 	YY_BREAK
 case 6:
 YY_RULE_SETUP
-#line 61 "itbl-lex.l"
+#line 62 "itbl-lex.l"
 {
     return INSN;
   }
 	YY_BREAK
 case 7:
 YY_RULE_SETUP
-#line 64 "itbl-lex.l"
+#line 65 "itbl-lex.l"
 {
     yytext[yyleng] = 0;
     yylval.processor = strtoul (yytext+1, 0, 0);
@@ -742,7 +743,7 @@ YY_RULE_SETUP
 	YY_BREAK
 case 8:
 YY_RULE_SETUP
-#line 69 "itbl-lex.l"
+#line 70 "itbl-lex.l"
 {
     yytext[yyleng] = 0;
     yylval.num = strtoul (yytext, 0, 0);
@@ -751,7 +752,7 @@ YY_RULE_SETUP
 	YY_BREAK
 case 9:
 YY_RULE_SETUP
-#line 74 "itbl-lex.l"
+#line 75 "itbl-lex.l"
 {
     yytext[yyleng] = 0;
     yylval.num = strtoul (yytext, 0, 0);
@@ -760,7 +761,7 @@ YY_RULE_SETUP
 	YY_BREAK
 case 10:
 YY_RULE_SETUP
-#line 79 "itbl-lex.l"
+#line 80 "itbl-lex.l"
 {
     yytext[yyleng] = 0;
     yylval.str = strdup (yytext);
@@ -769,7 +770,7 @@ YY_RULE_SETUP
 	YY_BREAK
 case 11:
 YY_RULE_SETUP
-#line 84 "itbl-lex.l"
+#line 85 "itbl-lex.l"
 {
     int c;
     while ((c = input ()) !=  EOF) 
@@ -784,7 +785,7 @@ YY_RULE_SETUP
 	YY_BREAK
 case 12:
 YY_RULE_SETUP
-#line 95 "itbl-lex.l"
+#line 96 "itbl-lex.l"
 { 
     insntbl_line++; 
     MDBG (("in lex, NL = %d (x%x)\n", NL, NL));
@@ -793,13 +794,13 @@ YY_RULE_SETUP
 	YY_BREAK
 case 13:
 YY_RULE_SETUP
-#line 100 "itbl-lex.l"
+#line 101 "itbl-lex.l"
 { 
   }
 	YY_BREAK
 case 14:
 YY_RULE_SETUP
-#line 102 "itbl-lex.l"
+#line 103 "itbl-lex.l"
 {
     MDBG (("char = %x, %d\n", yytext[0], yytext[0]));
     return yytext[0];
@@ -807,10 +808,10 @@ YY_RULE_SETUP
 	YY_BREAK
 case 15:
 YY_RULE_SETUP
-#line 106 "itbl-lex.l"
+#line 107 "itbl-lex.l"
 ECHO;
 	YY_BREAK
-#line 814 "itbl-lex.c"
+#line 815 "itbl-lex.c"
 case YY_STATE_EOF(INITIAL):
 	yyterminate();
 
@@ -1700,7 +1701,7 @@ int main()
 	return 0;
 	}
 #endif
-#line 106 "itbl-lex.l"
+#line 107 "itbl-lex.l"
 
 
 #ifndef yywrap
diff --git a/gas/itbl-lex.h b/gas/itbl-lex.h
new file mode 100644
index 000000000000..45c4dacfceeb
--- /dev/null
+++ b/gas/itbl-lex.h
@@ -0,0 +1,23 @@
+/* itbl-lex.h
+   Copyright 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful, 
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+extern int insntbl_line;
+extern int yyparse (void);
+extern int yylex (void);
diff --git a/gas/itbl-lex.l b/gas/itbl-lex.l
index e924efc56ef0..aceeac4f9f03 100644
--- a/gas/itbl-lex.l
+++ b/gas/itbl-lex.l
@@ -1,5 +1,5 @@
 /* itbl-lex.l
-   Copyright 1997, 1998, 2001 Free Software Foundation, Inc.
+   Copyright 1997, 1998, 2001, 2002, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,14 +15,15 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 %{
 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
 
+#include "itbl-lex.h"
 #include <itbl-parse.h>
 
 #ifdef DEBUG
diff --git a/gas/itbl-ops.c b/gas/itbl-ops.c
index 089bff4aac5a..bd1f6473f45c 100644
--- a/gas/itbl-ops.c
+++ b/gas/itbl-ops.c
@@ -1,5 +1,6 @@
 /* itbl-ops.c
-   Copyright 1997, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*======================================================================*/
 /*
@@ -204,18 +205,6 @@ struct itbl_entry *
 itbl_add_reg (int yyprocessor, int yytype, char *regname,
 	      int regnum)
 {
-#if 0
-#include "as.h"
-#include "symbols.h"
-  /* Since register names don't have a prefix, we put them in the symbol table so
-     they can't be used as symbols.  This also simplifies argument parsing as
-     we can let gas parse registers for us.  The recorded register number is
-     regnum.  */
-  /* Use symbol_create here instead of symbol_new so we don't try to
-     output registers into the object file's symbol table.  */
-  symbol_table_insert (symbol_create (regname, reg_section,
-				      regnum, &zero_address_frag));
-#endif
   return alloc_entry (get_processor (yyprocessor), get_type (yytype), regname,
 		      (unsigned long) regnum);
 }
diff --git a/gas/itbl-ops.h b/gas/itbl-ops.h
index 4c98d72da1a1..47dc8b295b19 100644
--- a/gas/itbl-ops.h
+++ b/gas/itbl-ops.h
@@ -1,5 +1,5 @@
 /* itbl-ops.h
-   Copyright 1997, 1999, 2000 Free Software Foundation, Inc.
+   Copyright 1997, 1999, 2000, 2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* External functions, constants and defines for itbl support */
 
diff --git a/gas/itbl-parse.c b/gas/itbl-parse.c
index 1974a7a2c15e..0fd788f0521f 100644
--- a/gas/itbl-parse.c
+++ b/gas/itbl-parse.c
@@ -1,19 +1,89 @@
-/* A Bison parser, made from itbl-parse.y
-   by GNU bison 1.35.  */
-
-#define YYBISON 1  /* Identify Bison output.  */
-
-# define	DREG	257
-# define	CREG	258
-# define	GREG	259
-# define	IMMED	260
-# define	ADDR	261
-# define	INSN	262
-# define	NUM	263
-# define	ID	264
-# define	NL	265
-# define	PNUM	266
+/* A Bison parser, made by GNU Bison 2.1.  */
 
+/* Skeleton parser for Yacc-like parsing with Bison,
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* Written by Richard Stallman by simplifying the original so called
+   ``semantic'' parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.1"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     DREG = 258,
+     CREG = 259,
+     GREG = 260,
+     IMMED = 261,
+     ADDR = 262,
+     INSN = 263,
+     NUM = 264,
+     ID = 265,
+     NL = 266,
+     PNUM = 267
+   };
+#endif
+/* Tokens.  */
+#define DREG 258
+#define CREG 259
+#define GREG 260
+#define IMMED 261
+#define ADDR 262
+#define INSN 263
+#define NUM 264
+#define ID 265
+#define NL 266
+#define PNUM 267
+
+
+
+
+/* Copy the first part of user declarations.  */
 #line 21 "itbl-parse.y"
 
 
@@ -244,6 +314,7 @@ FIXME! hex is ambiguous with any digit
 */
 
 #include <stdio.h>
+#include "itbl-lex.h"
 #include "itbl-ops.h"
 
 /* #define DEBUG */
@@ -270,239 +341,90 @@ FIXME! hex is ambiguous with any digit
 
 static int sbit, ebit;
 static struct itbl_entry *insn=0;
-extern int insntbl_line;
-int yyparse PARAMS ((void));
-int yylex PARAMS ((void));
 static int yyerror PARAMS ((const char *));
 
 
-#line 283 "itbl-parse.y"
-#ifndef YYSTYPE
-typedef union 
-  {
-    char *str;
-    int num;
-    int processor;
-    unsigned long val;
-  } yystype;
-# define YYSTYPE yystype
-# define YYSTYPE_IS_TRIVIAL 1
-#endif
+
+/* Enabling traces.  */
 #ifndef YYDEBUG
 # define YYDEBUG 0
 #endif
 
-
-
-#define	YYFINAL		51
-#define	YYFLAG		-32768
-#define	YYNTBASE	20
-
-/* YYTRANSLATE(YYLEX) -- Bison token number corresponding to YYLEX. */
-#define YYTRANSLATE(x) ((unsigned)(x) <= 266 ? yytranslate[x] : 34)
-
-/* YYTRANSLATE[YYLEX] -- Bison token number corresponding to YYLEX. */
-static const char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,    17,     2,    13,    19,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,    18,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,    15,     2,    16,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,    14,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     3,     4,     5,
-       6,     7,     8,     9,    10,    11,    12
-};
-
-#if YYDEBUG
-static const short yyprhs[] =
-{
-       0,     0,     2,     5,     6,    12,    13,    23,    25,    28,
-      32,    35,    36,    38,    40,    42,    46,    50,    54,    56,
-      59,    60,    65,    66,    68,    70,    72,    74,    76,    78
-};
-static const short yyrhs[] =
-{
-      21,     0,    22,    21,     0,     0,    30,    31,    32,    33,
-      11,     0,     0,    30,     8,    32,    33,    29,    28,    23,
-      24,    11,     0,    11,     0,     1,    11,     0,    13,    26,
-      24,     0,    26,    24,     0,     0,    31,     0,     7,     0,
-       6,     0,    25,    29,    28,     0,     9,    14,    27,     0,
-      15,    27,    16,     0,     9,     0,    17,    27,     0,     0,
-      18,     9,    19,     9,     0,     0,    12,     0,     3,     0,
-       4,     0,     5,     0,    10,     0,     9,     0,     9,     0
-};
-
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
 #endif
 
-#if YYDEBUG
-/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
-static const short yyrline[] =
-{
-       0,   300,   304,   306,   309,   316,   316,   325,   326,   329,
-     331,   332,   335,   341,   346,   353,   362,   367,   371,   377,
-     383,   389,   396,   403,   411,   417,   422,   429,   437,   445
-};
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
 #endif
 
-
-#if (YYDEBUG) || defined YYERROR_VERBOSE
-
-/* YYTNAME[TOKEN_NUM] -- String name of the token TOKEN_NUM. */
-static const char *const yytname[] =
-{
-  "$", "error", "$undefined.", "DREG", "CREG", "GREG", "IMMED", "ADDR", 
-  "INSN", "NUM", "ID", "NL", "PNUM", "','", "'|'", "'['", "']'", "'*'", 
-  "':'", "'-'", "insntbl", "entrys", "entry", "@1", "fieldspecs", "ftype", 
-  "fieldspec", "flagexpr", "flags", "range", "pnum", "regtype", "name", 
-  "value", 0
-};
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 282 "itbl-parse.y"
+typedef union YYSTYPE {
+    char *str;
+    int num;
+    int processor;
+    unsigned long val;
+  } YYSTYPE;
+/* Line 196 of yacc.c.  */
+#line 376 "itbl-parse.c"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
 #endif
 
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
-static const short yyr1[] =
-{
-       0,    20,    21,    21,    22,    23,    22,    22,    22,    24,
-      24,    24,    25,    25,    25,    26,    27,    27,    27,    28,
-      28,    29,    29,    30,    31,    31,    31,    32,    34,    33
-};
 
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
-static const short yyr2[] =
-{
-       0,     1,     2,     0,     5,     0,     9,     1,     2,     3,
-       2,     0,     1,     1,     1,     3,     3,     3,     1,     2,
-       0,     4,     0,     1,     1,     1,     1,     1,     1,     1
-};
 
-/* YYDEFACT[S] -- default rule to reduce with in state S when YYTABLE
-   doesn't specify something else to do.  Zero means the default is an
-   error. */
-static const short yydefact[] =
-{
-       0,     0,     7,    23,     1,     0,     0,     8,     2,    24,
-      25,    26,     0,     0,    27,     0,     0,    29,    22,     0,
-       0,    20,     4,     0,     0,     5,     0,    18,     0,    19,
-      11,    21,     0,     0,    14,    13,     0,     0,    22,    11,
-      12,    16,    17,    11,     6,    20,    10,     9,    15,     0,
-       0,     0
-};
-
-static const short yydefgoto[] =
-{
-      49,     4,     5,    30,    37,    38,    39,    29,    25,    21,
-       6,    40,    15,    18
-};
-
-static const short yypact[] =
-{
-       0,    -9,-32768,-32768,-32768,     0,    12,-32768,-32768,-32768,
-  -32768,-32768,     3,     3,-32768,     9,     9,-32768,    -8,     8,
-      19,    15,-32768,    10,    -6,-32768,    24,    20,    -6,-32768,
-       1,-32768,    -6,    21,-32768,-32768,    18,    25,    -8,     1,
-  -32768,-32768,-32768,     1,-32768,    15,-32768,-32768,-32768,    35,
-      38,-32768
-};
-
-static const short yypgoto[] =
-{
-  -32768,    34,-32768,-32768,   -13,-32768,     4,    -1,    -4,     5,
-  -32768,    36,    31,    29
-};
-
-
-#define	YYLAST		45
-
-
-static const short yytable[] =
-{
-      -3,     1,     7,    27,     9,    10,    11,    34,    35,    28,
-      20,     2,     3,    14,    36,     9,    10,    11,    17,    22,
-      12,     9,    10,    11,    34,    35,    46,    33,    23,    26,
-      47,    41,    24,    31,    32,    50,    44,    42,    51,     8,
-      43,    48,    13,    45,    16,    19
-};
-
-static const short yycheck[] =
-{
-       0,     1,    11,     9,     3,     4,     5,     6,     7,    15,
-      18,    11,    12,    10,    13,     3,     4,     5,     9,    11,
-       8,     3,     4,     5,     6,     7,    39,    28,     9,    19,
-      43,    32,    17,     9,    14,     0,    11,    16,     0,     5,
-      36,    45,     6,    38,    13,    16
-};
-/* -*-C-*-  Note some compilers choke on comments on `#line' lines.  */
-#line 3 "/usr/share/bison-1.35/bison.simple"
-
-/* Skeleton output parser for bison,
-
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002 Free Software
-   Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
+/* Copy the second part of user declarations.  */
 
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
 
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
+/* Line 219 of yacc.c.  */
+#line 388 "itbl-parse.c"
 
-/* This is the parser code that is written into each bison parser when
-   the %semantic_parser declaration is not specified in the grammar.
-   It was written by Richard Stallman by simplifying the hairy parser
-   used when %semantic_parser is specified.  */
+#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
+# define YYSIZE_T __SIZE_TYPE__
+#endif
+#if ! defined (YYSIZE_T) && defined (size_t)
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T)
+# define YYSIZE_T unsigned int
+#endif
 
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
 
-#if ! defined (yyoverflow) || defined (YYERROR_VERBOSE)
+#if ! defined (yyoverflow) || YYERROR_VERBOSE
 
 /* The parser invokes alloca or malloc; define the necessary symbols.  */
 
-# if YYSTACK_USE_ALLOCA
-#  define YYSTACK_ALLOC alloca
-# else
-#  ifndef YYSTACK_USE_ALLOCA
-#   if defined (alloca) || defined (_ALLOCA_H)
-#    define YYSTACK_ALLOC alloca
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
 #   else
-#    ifdef __GNUC__
-#     define YYSTACK_ALLOC __builtin_alloca
+#    define YYSTACK_ALLOC alloca
+#    if defined (__STDC__) || defined (__cplusplus)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     define YYINCLUDED_STDLIB_H
 #    endif
 #   endif
 #  endif
@@ -511,57 +433,74 @@ static const short yycheck[] =
 # ifdef YYSTACK_ALLOC
    /* Pacify GCC's `empty if-body' warning. */
 #  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
+#  endif
 # else
-#  if defined (__STDC__) || defined (__cplusplus)
-#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   define YYSIZE_T size_t
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
+#  endif
+#  ifdef __cplusplus
+extern "C" {
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifdef __cplusplus
+}
 #  endif
-#  define YYSTACK_ALLOC malloc
-#  define YYSTACK_FREE free
 # endif
-#endif /* ! defined (yyoverflow) || defined (YYERROR_VERBOSE) */
+#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
 
 
 #if (! defined (yyoverflow) \
      && (! defined (__cplusplus) \
-	 || (YYLTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
 
 /* A type that is properly aligned for any stack member.  */
 union yyalloc
 {
-  short yyss;
+  short int yyss;
   YYSTYPE yyvs;
-# if YYLSP_NEEDED
-  YYLTYPE yyls;
-# endif
-};
+  };
 
 /* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAX (sizeof (union yyalloc) - 1)
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
 
 /* The size of an array large to enough to hold all stacks, each with
    N elements.  */
-# if YYLSP_NEEDED
-#  define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short) + sizeof (YYSTYPE) + sizeof (YYLTYPE))	\
-      + 2 * YYSTACK_GAP_MAX)
-# else
-#  define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short) + sizeof (YYSTYPE))				\
-      + YYSTACK_GAP_MAX)
-# endif
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
+      + YYSTACK_GAP_MAXIMUM)
 
 /* Copy COUNT objects from FROM to TO.  The source and destination do
    not overlap.  */
 # ifndef YYCOPY
-#  if 1 < __GNUC__
+#  if defined (__GNUC__) && 1 < __GNUC__
 #   define YYCOPY(To, From, Count) \
       __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
 #  else
 #   define YYCOPY(To, From, Count)		\
       do					\
 	{					\
-	  register YYSIZE_T yyi;		\
+	  YYSIZE_T yyi;				\
 	  for (yyi = 0; yyi < (Count); yyi++)	\
 	    (To)[yyi] = (From)[yyi];		\
 	}					\
@@ -580,97 +519,308 @@ union yyalloc
 	YYSIZE_T yynewbytes;						\
 	YYCOPY (&yyptr->Stack, Stack, yysize);				\
 	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAX;	\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
 	yyptr += yynewbytes / sizeof (*yyptr);				\
       }									\
     while (0)
 
 #endif
 
+#if defined (__STDC__) || defined (__cplusplus)
+   typedef signed char yysigned_char;
+#else
+   typedef short int yysigned_char;
+#endif
 
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL  9
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   46
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS  20
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS  15
+/* YYNRULES -- Number of rules. */
+#define YYNRULES  29
+/* YYNRULES -- Number of states. */
+#define YYNSTATES  51
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   267
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const unsigned char yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,    17,     2,    13,    19,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,    18,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,    15,     2,    16,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,    14,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const unsigned char yyprhs[] =
+{
+       0,     0,     3,     5,     8,     9,    15,    16,    26,    28,
+      31,    35,    38,    39,    41,    43,    45,    49,    53,    57,
+      59,    62,    63,    68,    69,    71,    73,    75,    77,    79
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+static const yysigned_char yyrhs[] =
+{
+      21,     0,    -1,    22,    -1,    23,    22,    -1,    -1,    31,
+      32,    33,    34,    11,    -1,    -1,    31,     8,    33,    34,
+      30,    29,    24,    25,    11,    -1,    11,    -1,     1,    11,
+      -1,    13,    27,    25,    -1,    27,    25,    -1,    -1,    32,
+      -1,     7,    -1,     6,    -1,    26,    30,    29,    -1,     9,
+      14,    28,    -1,    15,    28,    16,    -1,     9,    -1,    17,
+      28,    -1,    -1,    18,     9,    19,     9,    -1,    -1,    12,
+      -1,     3,    -1,     4,    -1,     5,    -1,    10,    -1,     9,
+      -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const unsigned short int yyrline[] =
+{
+       0,   299,   299,   303,   304,   308,   315,   314,   323,   324,
+     328,   329,   330,   334,   339,   344,   352,   361,   365,   369,
+     376,   382,   388,   395,   402,   410,   415,   420,   428,   444
+};
 #endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "DREG", "CREG", "GREG", "IMMED", "ADDR",
+  "INSN", "NUM", "ID", "NL", "PNUM", "','", "'|'", "'['", "']'", "'*'",
+  "':'", "'-'", "$accept", "insntbl", "entrys", "entry", "@1",
+  "fieldspecs", "ftype", "fieldspec", "flagexpr", "flags", "range", "pnum",
+  "regtype", "name", "value", 0
+};
 #endif
-#if ! defined (YYSIZE_T)
-# if defined (__STDC__) || defined (__cplusplus)
-#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYSIZE_T size_t
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const unsigned short int yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,    44,   124,    91,    93,    42,    58,    45
+};
 # endif
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
-#endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const unsigned char yyr1[] =
+{
+       0,    20,    21,    22,    22,    23,    24,    23,    23,    23,
+      25,    25,    25,    26,    26,    26,    27,    28,    28,    28,
+      29,    29,    30,    30,    31,    32,    32,    32,    33,    34
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const unsigned char yyr2[] =
+{
+       0,     2,     1,     2,     0,     5,     0,     9,     1,     2,
+       3,     2,     0,     1,     1,     1,     3,     3,     3,     1,
+       2,     0,     4,     0,     1,     1,     1,     1,     1,     1
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const unsigned char yydefact[] =
+{
+       0,     0,     8,    24,     0,     2,     0,     0,     9,     1,
+       3,    25,    26,    27,     0,     0,    28,     0,     0,    29,
+      23,     0,     0,    21,     5,     0,     0,     6,     0,    19,
+       0,    20,    12,    22,     0,     0,    15,    14,     0,     0,
+      23,    12,    13,    17,    18,    12,     7,    21,    11,    10,
+      16
+};
+
+/* YYDEFGOTO[NTERM-NUM]. */
+static const yysigned_char yydefgoto[] =
+{
+      -1,     4,     5,     6,    32,    39,    40,    41,    31,    27,
+      23,     7,    42,    17,    20
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -16
+static const yysigned_char yypact[] =
+{
+       0,    -9,   -16,   -16,    10,   -16,     0,    12,   -16,   -16,
+     -16,   -16,   -16,   -16,     3,     3,   -16,     9,     9,   -16,
+      11,     8,    19,    15,   -16,    14,    -6,   -16,    25,    21,
+      -6,   -16,     1,   -16,    -6,    20,   -16,   -16,    18,    26,
+      11,     1,   -16,   -16,   -16,     1,   -16,    15,   -16,   -16,
+     -16
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const yysigned_char yypgoto[] =
+{
+     -16,   -16,    32,   -16,   -16,   -15,   -16,     2,    -3,    -8,
+       4,   -16,    34,    27,    28
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -5
+static const yysigned_char yytable[] =
+{
+      -4,     1,     8,    29,    11,    12,    13,    36,    37,    30,
+       9,     2,     3,    16,    38,    11,    12,    13,    19,    24,
+      14,    11,    12,    13,    36,    37,    48,    35,    25,    22,
+      49,    43,    26,    28,    33,    34,    44,    46,    10,    50,
+      45,    15,    18,     0,    47,     0,    21
+};
+
+static const yysigned_char yycheck[] =
+{
+       0,     1,    11,     9,     3,     4,     5,     6,     7,    15,
+       0,    11,    12,    10,    13,     3,     4,     5,     9,    11,
+       8,     3,     4,     5,     6,     7,    41,    30,     9,    18,
+      45,    34,    17,    19,     9,    14,    16,    11,     6,    47,
+      38,     7,    15,    -1,    40,    -1,    18
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const unsigned char yystos[] =
+{
+       0,     1,    11,    12,    21,    22,    23,    31,    11,     0,
+      22,     3,     4,     5,     8,    32,    10,    33,    33,     9,
+      34,    34,    18,    30,    11,     9,    17,    29,    19,     9,
+      15,    28,    24,     9,    14,    28,     6,     7,    13,    25,
+      26,    27,    32,    28,    16,    27,    11,    30,    25,    25,
+      29
+};
 
 #define yyerrok		(yyerrstatus = 0)
 #define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		-2
+#define YYEMPTY		(-2)
 #define YYEOF		0
+
 #define YYACCEPT	goto yyacceptlab
-#define YYABORT 	goto yyabortlab
-#define YYERROR		goto yyerrlab1
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
 /* Like YYERROR except do call yyerror.  This remains here temporarily
    to ease the transition to the new meaning of YYERROR, for GCC.
    Once GCC version 2 has supplanted version 1, this can go.  */
+
 #define YYFAIL		goto yyerrlab
+
 #define YYRECOVERING()  (!!yyerrstatus)
+
 #define YYBACKUP(Token, Value)					\
 do								\
   if (yychar == YYEMPTY && yylen == 1)				\
     {								\
       yychar = (Token);						\
       yylval = (Value);						\
-      yychar1 = YYTRANSLATE (yychar);				\
+      yytoken = YYTRANSLATE (yychar);				\
       YYPOPSTACK;						\
       goto yybackup;						\
     }								\
   else								\
-    { 								\
-      yyerror ("syntax error: cannot back up");			\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
       YYERROR;							\
     }								\
 while (0)
 
+
 #define YYTERROR	1
 #define YYERRCODE	256
 
 
-/* YYLLOC_DEFAULT -- Compute the default location (before the actions
-   are run).
-
-   When YYLLOC_DEFAULT is run, CURRENT is set the location of the
-   first token.  By default, to implement support for ranges, extend
-   its range to the last symbol.  */
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
 
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
 #ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)       	\
-   Current.last_line   = Rhs[N].last_line;	\
-   Current.last_column = Rhs[N].last_column;
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (N)								\
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (0)
 #endif
 
 
-/* YYLEX -- calling `yylex' with the right arguments.  */
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+              (Loc).first_line, (Loc).first_column,	\
+              (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
 
-#if YYPURE
-# if YYLSP_NEEDED
-#  ifdef YYLEX_PARAM
-#   define YYLEX		yylex (&yylval, &yylloc, YYLEX_PARAM)
-#  else
-#   define YYLEX		yylex (&yylval, &yylloc)
-#  endif
-# else /* !YYLSP_NEEDED */
-#  ifdef YYLEX_PARAM
-#   define YYLEX		yylex (&yylval, YYLEX_PARAM)
-#  else
-#   define YYLEX		yylex (&yylval)
-#  endif
-# endif /* !YYLSP_NEEDED */
-#else /* !YYPURE */
-# define YYLEX			yylex ()
-#endif /* !YYPURE */
 
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
 
 /* Enable debugging if requested.  */
 #if YYDEBUG
@@ -685,13 +835,86 @@ do {						\
   if (yydebug)					\
     YYFPRINTF Args;				\
 } while (0)
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
+do {								\
+  if (yydebug)							\
+    {								\
+      YYFPRINTF (stderr, "%s ", Title);				\
+      yysymprint (stderr,					\
+                  Type, Value);	\
+      YYFPRINTF (stderr, "\n");					\
+    }								\
+} while (0)
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_stack_print (short int *bottom, short int *top)
+#else
+static void
+yy_stack_print (bottom, top)
+    short int *bottom;
+    short int *top;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (/* Nothing. */; bottom <= top; ++bottom)
+    YYFPRINTF (stderr, " %d", *bottom);
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_reduce_print (int yyrule)
+#else
+static void
+yy_reduce_print (yyrule)
+    int yyrule;
+#endif
+{
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
+             yyrule - 1, yylno);
+  /* Print the symbols being reduced, and their result.  */
+  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
+    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
+  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (Rule);		\
+} while (0)
+
 /* Nonzero means print parse trace.  It is left uninitialized so that
    multiple parsers can coexist.  */
 int yydebug;
 #else /* !YYDEBUG */
 # define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
 #endif /* !YYDEBUG */
 
+
 /* YYINITDEPTH -- initial size of the parser's stacks.  */
 #ifndef	YYINITDEPTH
 # define YYINITDEPTH 200
@@ -701,18 +924,16 @@ int yydebug;
    if the built-in stack extension method is used).
 
    Do not make this value too large; the results are undefined if
-   SIZE_MAX < YYSTACK_BYTES (YYMAXDEPTH)
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
    evaluated with infinite-precision integer arithmetic.  */
 
-#if YYMAXDEPTH == 0
-# undef YYMAXDEPTH
-#endif
-
 #ifndef YYMAXDEPTH
 # define YYMAXDEPTH 10000
 #endif
+
 
-#ifdef YYERROR_VERBOSE
+
+#if YYERROR_VERBOSE
 
 # ifndef yystrlen
 #  if defined (__GLIBC__) && defined (_STRING_H)
@@ -727,7 +948,7 @@ yystrlen (yystr)
      const char *yystr;
 #   endif
 {
-  register const char *yys = yystr;
+  const char *yys = yystr;
 
   while (*yys++ != '\0')
     continue;
@@ -752,8 +973,8 @@ yystpcpy (yydest, yysrc)
      const char *yysrc;
 #   endif
 {
-  register char *yyd = yydest;
-  register const char *yys = yysrc;
+  char *yyd = yydest;
+  const char *yys = yysrc;
 
   while ((*yyd++ = *yys++) != '\0')
     continue;
@@ -762,86 +983,187 @@ yystpcpy (yydest, yysrc)
 }
 #  endif
 # endif
-#endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      size_t yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+#endif /* YYERROR_VERBOSE */
+
 
-#line 315 "/usr/share/bison-1.35/bison.simple"
 
+#if YYDEBUG
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
 
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yysymprint (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+  switch (yytype)
+    {
+      default:
+        break;
+    }
+  YYFPRINTF (yyoutput, ")");
+}
+
+#endif /* ! YYDEBUG */
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+
+      default:
+        break;
+    }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes.  */
 
 #ifdef YYPARSE_PARAM
 # if defined (__STDC__) || defined (__cplusplus)
-#  define YYPARSE_PARAM_ARG void *YYPARSE_PARAM
-#  define YYPARSE_PARAM_DECL
+int yyparse (void *YYPARSE_PARAM);
 # else
-#  define YYPARSE_PARAM_ARG YYPARSE_PARAM
-#  define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
+int yyparse ();
 # endif
-#else /* !YYPARSE_PARAM */
-# define YYPARSE_PARAM_ARG
-# define YYPARSE_PARAM_DECL
-#endif /* !YYPARSE_PARAM */
-
-/* Prevent warning if -Wstrict-prototypes.  */
-#ifdef __GNUC__
-# ifdef YYPARSE_PARAM
-int yyparse (void *);
-# else
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
 int yyparse (void);
-# endif
+#else
+int yyparse ();
 #endif
+#endif /* ! YYPARSE_PARAM */
 
-/* YY_DECL_VARIABLES -- depending whether we use a pure parser,
-   variables are global, or local to YYPARSE.  */
-
-#define YY_DECL_NON_LSP_VARIABLES			\
-/* The lookahead symbol.  */				\
-int yychar;						\
-							\
-/* The semantic value of the lookahead symbol. */	\
-YYSTYPE yylval;						\
-							\
-/* Number of parse errors so far.  */			\
-int yynerrs;
 
-#if YYLSP_NEEDED
-# define YY_DECL_VARIABLES			\
-YY_DECL_NON_LSP_VARIABLES			\
-						\
-/* Location data for the lookahead symbol.  */	\
-YYLTYPE yylloc;
-#else
-# define YY_DECL_VARIABLES			\
-YY_DECL_NON_LSP_VARIABLES
-#endif
+
+/* The look-ahead symbol.  */
+int yychar;
+
+/* The semantic value of the look-ahead symbol.  */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far.  */
+int yynerrs;
 
 
-/* If nonreentrant, generate the variables here. */
 
-#if !YYPURE
-YY_DECL_VARIABLES
-#endif  /* !YYPURE */
+/*----------.
+| yyparse.  |
+`----------*/
 
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM)
+# else
+int yyparse (YYPARSE_PARAM)
+  void *YYPARSE_PARAM;
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
 int
-yyparse (YYPARSE_PARAM_ARG)
-     YYPARSE_PARAM_DECL
+yyparse (void)
+#else
+int
+yyparse ()
+    ;
+#endif
+#endif
 {
-  /* If reentrant, generate the variables here. */
-#if YYPURE
-  YY_DECL_VARIABLES
-#endif  /* !YYPURE */
-
-  register int yystate;
-  register int yyn;
+  
+  int yystate;
+  int yyn;
   int yyresult;
   /* Number of tokens to shift before error messages enabled.  */
   int yyerrstatus;
-  /* Lookahead token as an internal (translated) token number.  */
-  int yychar1 = 0;
+  /* Look-ahead token as an internal (translated) token number.  */
+  int yytoken = 0;
 
   /* Three stacks and their tools:
      `yyss': related to states,
@@ -851,41 +1173,29 @@ yyparse (YYPARSE_PARAM_ARG)
      Refer to the stacks thru separate pointers, to allow yyoverflow
      to reallocate them elsewhere.  */
 
-  /* The state stack. */
-  short	yyssa[YYINITDEPTH];
-  short *yyss = yyssa;
-  register short *yyssp;
+  /* The state stack.  */
+  short int yyssa[YYINITDEPTH];
+  short int *yyss = yyssa;
+  short int *yyssp;
 
   /* The semantic value stack.  */
   YYSTYPE yyvsa[YYINITDEPTH];
   YYSTYPE *yyvs = yyvsa;
-  register YYSTYPE *yyvsp;
+  YYSTYPE *yyvsp;
 
-#if YYLSP_NEEDED
-  /* The location stack.  */
-  YYLTYPE yylsa[YYINITDEPTH];
-  YYLTYPE *yyls = yylsa;
-  YYLTYPE *yylsp;
-#endif
 
-#if YYLSP_NEEDED
-# define YYPOPSTACK   (yyvsp--, yyssp--, yylsp--)
-#else
-# define YYPOPSTACK   (yyvsp--, yyssp--)
-#endif
 
-  YYSIZE_T yystacksize = YYINITDEPTH;
+#define YYPOPSTACK   (yyvsp--, yyssp--)
 
+  YYSIZE_T yystacksize = YYINITDEPTH;
 
   /* The variables used to return semantic value and location from the
      action routines.  */
   YYSTYPE yyval;
-#if YYLSP_NEEDED
-  YYLTYPE yyloc;
-#endif
+
 
   /* When reducing, the number of symbols on the RHS of the reduced
-     rule. */
+     rule.  */
   int yylen;
 
   YYDPRINTF ((stderr, "Starting parse\n"));
@@ -902,9 +1212,7 @@ yyparse (YYPARSE_PARAM_ARG)
 
   yyssp = yyss;
   yyvsp = yyvs;
-#if YYLSP_NEEDED
-  yylsp = yyls;
-#endif
+
   goto yysetstate;
 
 /*------------------------------------------------------------.
@@ -919,7 +1227,7 @@ yyparse (YYPARSE_PARAM_ARG)
  yysetstate:
   *yyssp = yystate;
 
-  if (yyssp >= yyss + yystacksize - 1)
+  if (yyss + yystacksize - 1 <= yyssp)
     {
       /* Get the current used size of the three stacks, in elements.  */
       YYSIZE_T yysize = yyssp - yyss + 1;
@@ -930,52 +1238,43 @@ yyparse (YYPARSE_PARAM_ARG)
 	   these so that the &'s don't force the real ones into
 	   memory.  */
 	YYSTYPE *yyvs1 = yyvs;
-	short *yyss1 = yyss;
+	short int *yyss1 = yyss;
+
 
 	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  */
-# if YYLSP_NEEDED
-	YYLTYPE *yyls1 = yyls;
-	/* This used to be a conditional around just the two extra args,
-	   but that might be undefined if yyoverflow is a macro.  */
-	yyoverflow ("parser stack overflow",
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-		    &yyls1, yysize * sizeof (*yylsp),
-		    &yystacksize);
-	yyls = yyls1;
-# else
-	yyoverflow ("parser stack overflow",
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
 		    &yyss1, yysize * sizeof (*yyssp),
 		    &yyvs1, yysize * sizeof (*yyvsp),
+
 		    &yystacksize);
-# endif
+
 	yyss = yyss1;
 	yyvs = yyvs1;
       }
 #else /* no yyoverflow */
 # ifndef YYSTACK_RELOCATE
-      goto yyoverflowlab;
+      goto yyexhaustedlab;
 # else
       /* Extend the stack our own way.  */
-      if (yystacksize >= YYMAXDEPTH)
-	goto yyoverflowlab;
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
       yystacksize *= 2;
-      if (yystacksize > YYMAXDEPTH)
+      if (YYMAXDEPTH < yystacksize)
 	yystacksize = YYMAXDEPTH;
 
       {
-	short *yyss1 = yyss;
+	short int *yyss1 = yyss;
 	union yyalloc *yyptr =
 	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
 	if (! yyptr)
-	  goto yyoverflowlab;
+	  goto yyexhaustedlab;
 	YYSTACK_RELOCATE (yyss);
 	YYSTACK_RELOCATE (yyvs);
-# if YYLSP_NEEDED
-	YYSTACK_RELOCATE (yyls);
-# endif
-# undef YYSTACK_RELOCATE
+
+#  undef YYSTACK_RELOCATE
 	if (yyss1 != yyssa)
 	  YYSTACK_FREE (yyss1);
       }
@@ -984,14 +1283,12 @@ yyparse (YYPARSE_PARAM_ARG)
 
       yyssp = yyss + yysize - 1;
       yyvsp = yyvs + yysize - 1;
-#if YYLSP_NEEDED
-      yylsp = yyls + yysize - 1;
-#endif
+
 
       YYDPRINTF ((stderr, "Stack size increased to %lu\n",
 		  (unsigned long int) yystacksize));
 
-      if (yyssp >= yyss + yystacksize - 1)
+      if (yyss + yystacksize - 1 <= yyssp)
 	YYABORT;
     }
 
@@ -999,101 +1296,67 @@ yyparse (YYPARSE_PARAM_ARG)
 
   goto yybackup;
 
-
 /*-----------.
 | yybackup.  |
 `-----------*/
 yybackup:
 
 /* Do appropriate processing given the current state.  */
-/* Read a lookahead token if we need one and don't already have one.  */
+/* Read a look-ahead token if we need one and don't already have one.  */
 /* yyresume: */
 
-  /* First try to decide what to do without reference to lookahead token.  */
+  /* First try to decide what to do without reference to look-ahead token.  */
 
   yyn = yypact[yystate];
-  if (yyn == YYFLAG)
+  if (yyn == YYPACT_NINF)
     goto yydefault;
 
-  /* Not known => get a lookahead token if don't already have one.  */
-
-  /* yychar is either YYEMPTY or YYEOF
-     or a valid token in external form.  */
+  /* Not known => get a look-ahead token if don't already have one.  */
 
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
   if (yychar == YYEMPTY)
     {
       YYDPRINTF ((stderr, "Reading a token: "));
       yychar = YYLEX;
     }
 
-  /* Convert token to internal form (in yychar1) for indexing tables with */
-
-  if (yychar <= 0)		/* This means end of input. */
+  if (yychar <= YYEOF)
     {
-      yychar1 = 0;
-      yychar = YYEOF;		/* Don't call YYLEX any more */
-
+      yychar = yytoken = YYEOF;
       YYDPRINTF ((stderr, "Now at end of input.\n"));
     }
   else
     {
-      yychar1 = YYTRANSLATE (yychar);
-
-#if YYDEBUG
-     /* We have to keep this `#if YYDEBUG', since we use variables
-	which are defined only if `YYDEBUG' is set.  */
-      if (yydebug)
-	{
-	  YYFPRINTF (stderr, "Next token is %d (%s",
-		     yychar, yytname[yychar1]);
-	  /* Give the individual parser a way to print the precise
-	     meaning of a token, for further debugging info.  */
-# ifdef YYPRINT
-	  YYPRINT (stderr, yychar, yylval);
-# endif
-	  YYFPRINTF (stderr, ")\n");
-	}
-#endif
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
     }
 
-  yyn += yychar1;
-  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != yychar1)
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
     goto yydefault;
-
   yyn = yytable[yyn];
-
-  /* yyn is what to do for this token type in this state.
-     Negative => reduce, -yyn is rule number.
-     Positive => shift, yyn is new state.
-       New state is final state => don't bother to shift,
-       just return success.
-     0, or most negative number => error.  */
-
-  if (yyn < 0)
+  if (yyn <= 0)
     {
-      if (yyn == YYFLAG)
+      if (yyn == 0 || yyn == YYTABLE_NINF)
 	goto yyerrlab;
       yyn = -yyn;
       goto yyreduce;
     }
-  else if (yyn == 0)
-    goto yyerrlab;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
-  /* Shift the lookahead token.  */
-  YYDPRINTF ((stderr, "Shifting token %d (%s), ",
-	      yychar, yytname[yychar1]));
+  /* Shift the look-ahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
 
   /* Discard the token being shifted unless it is eof.  */
   if (yychar != YYEOF)
     yychar = YYEMPTY;
 
   *++yyvsp = yylval;
-#if YYLSP_NEEDED
-  *++yylsp = yylloc;
-#endif
+
 
   /* Count tokens shifted since error; after three, turn off error
      status.  */
@@ -1124,210 +1387,190 @@ yyreduce:
   /* If YYLEN is nonzero, implement the default value of the action:
      `$$ = $1'.
 
-     Otherwise, the following line sets YYVAL to the semantic value of
-     the lookahead token.  This behavior is undocumented and Bison
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
      users should not rely upon it.  Assigning to YYVAL
      unconditionally makes the parser a bit smaller, and it avoids a
      GCC warning that YYVAL may be used uninitialized.  */
   yyval = yyvsp[1-yylen];
 
-#if YYLSP_NEEDED
-  /* Similarly for the default location.  Let the user run additional
-     commands if for instance locations are ranges.  */
-  yyloc = yylsp[1-yylen];
-  YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen);
-#endif
 
-#if YYDEBUG
-  /* We have to keep this `#if YYDEBUG', since we use variables which
-     are defined only if `YYDEBUG' is set.  */
-  if (yydebug)
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 5:
+#line 309 "itbl-parse.y"
     {
-      int yyi;
-
-      YYFPRINTF (stderr, "Reducing via rule %d (line %d), ",
-		 yyn, yyrline[yyn]);
-
-      /* Print the symbols being reduced, and their result.  */
-      for (yyi = yyprhs[yyn]; yyrhs[yyi] > 0; yyi++)
-	YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
-      YYFPRINTF (stderr, " -> %s\n", yytname[yyr1[yyn]]);
-    }
-#endif
-
-  switch (yyn) {
-
-case 4:
-#line 311 "itbl-parse.y"
-{
 	    DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n", 
-	    	    insntbl_line, yyvsp[-4].num, yyvsp[-3].num, yyvsp[-2].str, yyvsp[-1].val));
-	    itbl_add_reg (yyvsp[-4].num, yyvsp[-3].num, yyvsp[-2].str, yyvsp[-1].val);
+	    	    insntbl_line, (yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val)));
+	    itbl_add_reg ((yyvsp[-4].num), (yyvsp[-3].num), (yyvsp[-2].str), (yyvsp[-1].val));
 	  }
     break;
-case 5:
-#line 317 "itbl-parse.y"
-{
+
+  case 6:
+#line 315 "itbl-parse.y"
+    {
 	    DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
-	    	    insntbl_line, yyvsp[-5].num, yyvsp[-3].str, yyvsp[-2].val));
-	    DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, yyvsp[0].val));
-	    insn=itbl_add_insn (yyvsp[-5].num, yyvsp[-3].str, yyvsp[-2].val, sbit, ebit, yyvsp[0].val);
+	    	    insntbl_line, (yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val)));
+	    DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, (yyvsp[0].val)));
+	    insn=itbl_add_insn ((yyvsp[-5].num), (yyvsp[-3].str), (yyvsp[-2].val), sbit, ebit, (yyvsp[0].val));
 	  }
     break;
-case 6:
-#line 324 "itbl-parse.y"
-{}
+
+  case 7:
+#line 322 "itbl-parse.y"
+    {}
     break;
-case 12:
-#line 337 "itbl-parse.y"
-{
+
+  case 13:
+#line 335 "itbl-parse.y"
+    {
 	    DBGL2 (("ftype\n"));
-	    yyval.num = yyvsp[0].num;
+	    (yyval.num) = (yyvsp[0].num);
 	  }
     break;
-case 13:
-#line 342 "itbl-parse.y"
-{
+
+  case 14:
+#line 340 "itbl-parse.y"
+    {
 	    DBGL2 (("addr\n"));
-	    yyval.num = ADDR;
+	    (yyval.num) = ADDR;
 	  }
     break;
-case 14:
-#line 347 "itbl-parse.y"
-{
+
+  case 15:
+#line 345 "itbl-parse.y"
+    {
 	    DBGL2 (("immed\n"));
-	    yyval.num = IMMED;
+	    (yyval.num) = IMMED;
 	  }
     break;
-case 15:
-#line 355 "itbl-parse.y"
-{
+
+  case 16:
+#line 353 "itbl-parse.y"
+    {
 	    DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n", 
-	    	    insntbl_line, yyvsp[-2].num, sbit, ebit, yyvsp[0].val));
-	    itbl_add_operand (insn, yyvsp[-2].num, sbit, ebit, yyvsp[0].val);
+	    	    insntbl_line, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val)));
+	    itbl_add_operand (insn, (yyvsp[-2].num), sbit, ebit, (yyvsp[0].val));
 	  }
     break;
-case 16:
-#line 364 "itbl-parse.y"
-{
-	    yyval.val = yyvsp[-2].num | yyvsp[0].val;
+
+  case 17:
+#line 362 "itbl-parse.y"
+    {
+	    (yyval.val) = (yyvsp[-2].num) | (yyvsp[0].val);
 	  }
     break;
-case 17:
-#line 368 "itbl-parse.y"
-{
-	    yyval.val = yyvsp[-1].val;
+
+  case 18:
+#line 366 "itbl-parse.y"
+    {
+	    (yyval.val) = (yyvsp[-1].val);
 	  }
     break;
-case 18:
-#line 372 "itbl-parse.y"
-{
-	    yyval.val = yyvsp[0].num;
+
+  case 19:
+#line 370 "itbl-parse.y"
+    {
+	    (yyval.val) = (yyvsp[0].num);
 	  }
     break;
-case 19:
-#line 379 "itbl-parse.y"
-{
-	    DBGL2 (("flags=%d\n", yyvsp[0].val));
-	    yyval.val = yyvsp[0].val;
+
+  case 20:
+#line 377 "itbl-parse.y"
+    {
+	    DBGL2 (("flags=%d\n", (yyvsp[0].val)));
+	    (yyval.val) = (yyvsp[0].val);
 	  }
     break;
-case 20:
-#line 384 "itbl-parse.y"
-{
-	    yyval.val = 0;
+
+  case 21:
+#line 382 "itbl-parse.y"
+    {
+	    (yyval.val) = 0;
 	  }
     break;
-case 21:
-#line 391 "itbl-parse.y"
-{
-	    DBGL2 (("range %d %d\n", yyvsp[-2].num, yyvsp[0].num));
-	    sbit = yyvsp[-2].num;
-	    ebit = yyvsp[0].num;
+
+  case 22:
+#line 389 "itbl-parse.y"
+    {
+	    DBGL2 (("range %d %d\n", (yyvsp[-2].num), (yyvsp[0].num)));
+	    sbit = (yyvsp[-2].num);
+	    ebit = (yyvsp[0].num);
 	  }
     break;
-case 22:
-#line 397 "itbl-parse.y"
-{
+
+  case 23:
+#line 395 "itbl-parse.y"
+    {
 	    sbit = 31;
 	    ebit = 0;
 	  }
     break;
-case 23:
-#line 405 "itbl-parse.y"
-{
-	    DBGL2 (("pnum=%d\n",yyvsp[0].num));
-	    yyval.num = yyvsp[0].num;
+
+  case 24:
+#line 403 "itbl-parse.y"
+    {
+	    DBGL2 (("pnum=%d\n",(yyvsp[0].num)));
+	    (yyval.num) = (yyvsp[0].num);
 	  }
     break;
-case 24:
-#line 413 "itbl-parse.y"
-{
+
+  case 25:
+#line 411 "itbl-parse.y"
+    {
 	    DBGL2 (("dreg\n"));
-	    yyval.num = DREG;
+	    (yyval.num) = DREG;
 	  }
     break;
-case 25:
-#line 418 "itbl-parse.y"
-{
+
+  case 26:
+#line 416 "itbl-parse.y"
+    {
 	    DBGL2 (("creg\n"));
-	    yyval.num = CREG;
+	    (yyval.num) = CREG;
 	  }
     break;
-case 26:
-#line 423 "itbl-parse.y"
-{
+
+  case 27:
+#line 421 "itbl-parse.y"
+    {
 	    DBGL2 (("greg\n"));
-	    yyval.num = GREG;
-	  }
-    break;
-case 27:
-#line 431 "itbl-parse.y"
-{
-	    DBGL2 (("name=%s\n",yyvsp[0].str));
-	    yyval.str = yyvsp[0].str; 
+	    (yyval.num) = GREG;
 	  }
     break;
-case 28:
-#line 439 "itbl-parse.y"
-{
-	    DBGL2 (("num=%d\n",yyvsp[0].num));
-	    yyval.num = yyvsp[0].num;
+
+  case 28:
+#line 429 "itbl-parse.y"
+    {
+	    DBGL2 (("name=%s\n",(yyvsp[0].str)));
+	    (yyval.str) = (yyvsp[0].str); 
 	  }
     break;
-case 29:
-#line 447 "itbl-parse.y"
-{
-	    DBGL2 (("val=x%x\n",yyvsp[0].num));
-	    yyval.val = yyvsp[0].num;
+
+  case 29:
+#line 445 "itbl-parse.y"
+    {
+	    DBGL2 (("val=x%x\n",(yyvsp[0].num)));
+	    (yyval.val) = (yyvsp[0].num);
 	  }
     break;
-}
 
-#line 705 "/usr/share/bison-1.35/bison.simple"
 
+      default: break;
+    }
+
+/* Line 1126 of yacc.c.  */
+#line 1565 "itbl-parse.c"
 
   yyvsp -= yylen;
   yyssp -= yylen;
-#if YYLSP_NEEDED
-  yylsp -= yylen;
-#endif
 
-#if YYDEBUG
-  if (yydebug)
-    {
-      short *yyssp1 = yyss - 1;
-      YYFPRINTF (stderr, "state stack now");
-      while (yyssp1 != yyssp)
-	YYFPRINTF (stderr, " %d", *++yyssp1);
-      YYFPRINTF (stderr, "\n");
-    }
-#endif
+
+  YY_STACK_PRINT (yyss, yyssp);
 
   *++yyvsp = yyval;
-#if YYLSP_NEEDED
-  *++yylsp = yyloc;
-#endif
+
 
   /* Now `shift' the result of the reduction.  Determine what state
      that goes to, based on the state we popped back to and the rule
@@ -1335,11 +1578,11 @@ case 29:
 
   yyn = yyr1[yyn];
 
-  yystate = yypgoto[yyn - YYNTBASE] + *yyssp;
-  if (yystate >= 0 && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
     yystate = yytable[yystate];
   else
-    yystate = yydefgoto[yyn - YYNTBASE];
+    yystate = yydefgoto[yyn - YYNTOKENS];
 
   goto yynewstate;
 
@@ -1352,155 +1595,193 @@ yyerrlab:
   if (!yyerrstatus)
     {
       ++yynerrs;
-
-#ifdef YYERROR_VERBOSE
+#if YYERROR_VERBOSE
       yyn = yypact[yystate];
 
-      if (yyn > YYFLAG && yyn < YYLAST)
+      if (YYPACT_NINF < yyn && yyn < YYLAST)
 	{
-	  YYSIZE_T yysize = 0;
-	  char *yymsg;
-	  int yyx, yycount;
+	  int yytype = YYTRANSLATE (yychar);
+	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+	  YYSIZE_T yysize = yysize0;
+	  YYSIZE_T yysize1;
+	  int yysize_overflow = 0;
+	  char *yymsg = 0;
+#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
+	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+	  int yyx;
+
+#if 0
+	  /* This is so xgettext sees the translatable formats that are
+	     constructed on the fly.  */
+	  YY_("syntax error, unexpected %s");
+	  YY_("syntax error, unexpected %s, expecting %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+#endif
+	  char *yyfmt;
+	  char const *yyf;
+	  static char const yyunexpected[] = "syntax error, unexpected %s";
+	  static char const yyexpecting[] = ", expecting %s";
+	  static char const yyor[] = " or %s";
+	  char yyformat[sizeof yyunexpected
+			+ sizeof yyexpecting - 1
+			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+			   * (sizeof yyor - 1))];
+	  char const *yyprefix = yyexpecting;
 
-	  yycount = 0;
 	  /* Start YYX at -YYN if negative to avoid negative indexes in
 	     YYCHECK.  */
-	  for (yyx = yyn < 0 ? -yyn : 0;
-	       yyx < (int) (sizeof (yytname) / sizeof (char *)); yyx++)
-	    if (yycheck[yyx + yyn] == yyx)
-	      yysize += yystrlen (yytname[yyx]) + 15, yycount++;
-	  yysize += yystrlen ("parse error, unexpected ") + 1;
-	  yysize += yystrlen (yytname[YYTRANSLATE (yychar)]);
-	  yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg != 0)
+	  int yyxbegin = yyn < 0 ? -yyn : 0;
+
+	  /* Stay within bounds of both yycheck and yytname.  */
+	  int yychecklim = YYLAST - yyn;
+	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+	  int yycount = 1;
+
+	  yyarg[0] = yytname[yytype];
+	  yyfmt = yystpcpy (yyformat, yyunexpected);
+
+	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	      {
+		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+		  {
+		    yycount = 1;
+		    yysize = yysize0;
+		    yyformat[sizeof yyunexpected - 1] = '\0';
+		    break;
+		  }
+		yyarg[yycount++] = yytname[yyx];
+		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+		yysize_overflow |= yysize1 < yysize;
+		yysize = yysize1;
+		yyfmt = yystpcpy (yyfmt, yyprefix);
+		yyprefix = yyor;
+	      }
+
+	  yyf = YY_(yyformat);
+	  yysize1 = yysize + yystrlen (yyf);
+	  yysize_overflow |= yysize1 < yysize;
+	  yysize = yysize1;
+
+	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
+	    yymsg = (char *) YYSTACK_ALLOC (yysize);
+	  if (yymsg)
 	    {
-	      char *yyp = yystpcpy (yymsg, "parse error, unexpected ");
-	      yyp = yystpcpy (yyp, yytname[YYTRANSLATE (yychar)]);
-
-	      if (yycount < 5)
+	      /* Avoid sprintf, as that infringes on the user's name space.
+		 Don't have undefined behavior even if the translation
+		 produced a string with the wrong number of "%s"s.  */
+	      char *yyp = yymsg;
+	      int yyi = 0;
+	      while ((*yyp = *yyf))
 		{
-		  yycount = 0;
-		  for (yyx = yyn < 0 ? -yyn : 0;
-		       yyx < (int) (sizeof (yytname) / sizeof (char *));
-		       yyx++)
-		    if (yycheck[yyx + yyn] == yyx)
-		      {
-			const char *yyq = ! yycount ? ", expecting " : " or ";
-			yyp = yystpcpy (yyp, yyq);
-			yyp = yystpcpy (yyp, yytname[yyx]);
-			yycount++;
-		      }
+		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		    {
+		      yyp += yytnamerr (yyp, yyarg[yyi++]);
+		      yyf += 2;
+		    }
+		  else
+		    {
+		      yyp++;
+		      yyf++;
+		    }
 		}
 	      yyerror (yymsg);
 	      YYSTACK_FREE (yymsg);
 	    }
 	  else
-	    yyerror ("parse error; also virtual memory exhausted");
+	    {
+	      yyerror (YY_("syntax error"));
+	      goto yyexhaustedlab;
+	    }
 	}
       else
-#endif /* defined (YYERROR_VERBOSE) */
-	yyerror ("parse error");
+#endif /* YYERROR_VERBOSE */
+	yyerror (YY_("syntax error"));
     }
-  goto yyerrlab1;
 
 
-/*--------------------------------------------------.
-| yyerrlab1 -- error raised explicitly by an action |
-`--------------------------------------------------*/
-yyerrlab1:
+
   if (yyerrstatus == 3)
     {
-      /* If just tried and failed to reuse lookahead token after an
+      /* If just tried and failed to reuse look-ahead token after an
 	 error, discard it.  */
 
-      /* return failure if at end of input */
-      if (yychar == YYEOF)
-	YYABORT;
-      YYDPRINTF ((stderr, "Discarding token %d (%s).\n",
-		  yychar, yytname[yychar1]));
-      yychar = YYEMPTY;
+      if (yychar <= YYEOF)
+        {
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+        }
+      else
+	{
+	  yydestruct ("Error: discarding", yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
     }
 
-  /* Else will try to reuse lookahead token after shifting the error
+  /* Else will try to reuse look-ahead token after shifting the error
      token.  */
+  goto yyerrlab1;
 
-  yyerrstatus = 3;		/* Each real token shifted decrements this */
 
-  goto yyerrhandle;
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
 
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (0)
+     goto yyerrorlab;
 
-/*-------------------------------------------------------------------.
-| yyerrdefault -- current state does not do anything special for the |
-| error token.                                                       |
-`-------------------------------------------------------------------*/
-yyerrdefault:
-#if 0
-  /* This is wrong; only states that explicitly want error tokens
-     should shift them.  */
-
-  /* If its default is to accept any token, ok.  Otherwise pop it.  */
-  yyn = yydefact[yystate];
-  if (yyn)
-    goto yydefault;
-#endif
+yyvsp -= yylen;
+  yyssp -= yylen;
+  yystate = *yyssp;
+  goto yyerrlab1;
 
 
-/*---------------------------------------------------------------.
-| yyerrpop -- pop the current state because it cannot handle the |
-| error token                                                    |
-`---------------------------------------------------------------*/
-yyerrpop:
-  if (yyssp == yyss)
-    YYABORT;
-  yyvsp--;
-  yystate = *--yyssp;
-#if YYLSP_NEEDED
-  yylsp--;
-#endif
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
 
-#if YYDEBUG
-  if (yydebug)
+  for (;;)
     {
-      short *yyssp1 = yyss - 1;
-      YYFPRINTF (stderr, "Error: state stack now");
-      while (yyssp1 != yyssp)
-	YYFPRINTF (stderr, " %d", *++yyssp1);
-      YYFPRINTF (stderr, "\n");
-    }
-#endif
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
 
-/*--------------.
-| yyerrhandle.  |
-`--------------*/
-yyerrhandle:
-  yyn = yypact[yystate];
-  if (yyn == YYFLAG)
-    goto yyerrdefault;
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
 
-  yyn += YYTERROR;
-  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != YYTERROR)
-    goto yyerrdefault;
 
-  yyn = yytable[yyn];
-  if (yyn < 0)
-    {
-      if (yyn == YYFLAG)
-	goto yyerrpop;
-      yyn = -yyn;
-      goto yyreduce;
+      yydestruct ("Error: popping", yystos[yystate], yyvsp);
+      YYPOPSTACK;
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
     }
-  else if (yyn == 0)
-    goto yyerrpop;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
-  YYDPRINTF ((stderr, "Shifting error token, "));
-
   *++yyvsp = yylval;
-#if YYLSP_NEEDED
-  *++yylsp = yylloc;
-#endif
+
+
+  /* Shift the error token. */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
 
   yystate = yyn;
   goto yynewstate;
@@ -1520,22 +1801,35 @@ yyabortlab:
   yyresult = 1;
   goto yyreturn;
 
-/*---------------------------------------------.
-| yyoverflowab -- parser overflow comes here.  |
-`---------------------------------------------*/
-yyoverflowlab:
-  yyerror ("parser stack overflow");
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
   yyresult = 2;
   /* Fall through.  */
+#endif
 
 yyreturn:
+  if (yychar != YYEOF && yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK;
+    }
 #ifndef yyoverflow
   if (yyss != yyssa)
     YYSTACK_FREE (yyss);
 #endif
   return yyresult;
 }
-#line 452 "itbl-parse.y"
+
+
+#line 450 "itbl-parse.y"
 
 
 static int
@@ -1545,3 +1839,4 @@ yyerror (msg)
   printf ("line %d: %s\n", insntbl_line, msg);
   return 0;
 }
+
diff --git a/gas/itbl-parse.h b/gas/itbl-parse.h
index 00bdbdb9df28..9fd500831b79 100644
--- a/gas/itbl-parse.h
+++ b/gas/itbl-parse.h
@@ -1,29 +1,77 @@
-#ifndef BISON_Y_TAB_H
-# define BISON_Y_TAB_H
+/* A Bison parser, made by GNU Bison 2.1.  */
 
-#ifndef YYSTYPE
-typedef union 
-  {
+/* Skeleton parser for Yacc-like parsing with Bison,
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
+
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     DREG = 258,
+     CREG = 259,
+     GREG = 260,
+     IMMED = 261,
+     ADDR = 262,
+     INSN = 263,
+     NUM = 264,
+     ID = 265,
+     NL = 266,
+     PNUM = 267
+   };
+#endif
+/* Tokens.  */
+#define DREG 258
+#define CREG 259
+#define GREG 260
+#define IMMED 261
+#define ADDR 262
+#define INSN 263
+#define NUM 264
+#define ID 265
+#define NL 266
+#define PNUM 267
+
+
+
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 282 "itbl-parse.y"
+typedef union YYSTYPE {
     char *str;
     int num;
     int processor;
     unsigned long val;
-  } yystype;
-# define YYSTYPE yystype
+  } YYSTYPE;
+/* Line 1447 of yacc.c.  */
+#line 69 "itbl-parse.h"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
 # define YYSTYPE_IS_TRIVIAL 1
 #endif
-# define	DREG	257
-# define	CREG	258
-# define	GREG	259
-# define	IMMED	260
-# define	ADDR	261
-# define	INSN	262
-# define	NUM	263
-# define	ID	264
-# define	NL	265
-# define	PNUM	266
-
 
 extern YYSTYPE yylval;
 
-#endif /* not BISON_Y_TAB_H */
+
+
diff --git a/gas/itbl-parse.y b/gas/itbl-parse.y
index 53552d7f31b0..a7a52dfabff9 100644
--- a/gas/itbl-parse.y
+++ b/gas/itbl-parse.y
@@ -1,5 +1,5 @@
 /* itbl-parse.y
-   Copyright 1997 Free Software Foundation, Inc.
+   Copyright 1997, 2002, 2003, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -15,8 +15,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 %{
 
@@ -247,6 +247,7 @@ FIXME! hex is ambiguous with any digit
 */
 
 #include <stdio.h>
+#include "itbl-lex.h"
 #include "itbl-ops.h"
 
 /* #define DEBUG */
@@ -273,9 +274,6 @@ FIXME! hex is ambiguous with any digit
 
 static int sbit, ebit;
 static struct itbl_entry *insn=0;
-extern int insntbl_line;
-int yyparse PARAMS ((void));
-int yylex PARAMS ((void));
 static int yyerror PARAMS ((const char *));
 
 %}
diff --git a/gas/link.cmd b/gas/link.cmd
deleted file mode 100644
index a035ca87daa9..000000000000
--- a/gas/link.cmd
+++ /dev/null
@@ -1,10 +0,0 @@
-ALIGN=1024
-RESNUM 0x0000, 0x8000
-; Putting in .lit1 gives errors.
-ORDER .data=0x80002000, .data1, .lit, .bss
-; Let's put this on the command line so it goes first, which is what
-; GDB expects.
-; LOAD /s2/amd/29k/lib/crt0.o
-LOAD /s2/amd/29k/lib/libqcb0h.lib
-LOAD /s2/amd/29k/lib/libscb0h.lib
-LOAD /s2/amd/29k/lib/libacb0h.lib
diff --git a/gas/listing.c b/gas/listing.c
index aa22c5e99e41..61ef6f55e40f 100644
--- a/gas/listing.c
+++ b/gas/listing.c
@@ -1,6 +1,6 @@
 /* listing.c - maintain assembly listings
    Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
-   2001, 2002, 2003
+   2001, 2002, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Contributed by Steve Chamberlain <sac@cygnus.com>
 
@@ -613,10 +613,6 @@ calc_hex (list_info_type *list)
 	      sprintf (data_buffer + data_buffer_size,
 		       "%02X",
 		       (frag_ptr->fr_literal[var_rep_idx]) & 0xff);
-#if 0
-	      data_buffer[data_buffer_size++] = '*';
-	      data_buffer[data_buffer_size++] = '*';
-#endif
 	      data_buffer_size += 2;
 
 	      var_rep_idx++;
@@ -753,11 +749,10 @@ list_symbol_table (void)
       if (SEG_NORMAL (S_GET_SEGMENT (ptr))
 	  || S_GET_SEGMENT (ptr) == absolute_section)
 	{
-#ifdef BFD_ASSEMBLER
 	  /* Don't report section symbols.  They are not interesting.  */
 	  if (symbol_section_p (ptr))
 	    continue;
-#endif
+
 	  if (S_GET_NAME (ptr))
 	    {
 	      char buf[30], fmt[8];
@@ -1090,9 +1085,7 @@ listing_print (char *name)
 	using_stdout = 0;
       else
 	{
-#ifdef BFD_ASSEMBLER
-      bfd_set_error (bfd_error_system_call);
-#endif
+	  bfd_set_error (bfd_error_system_call);
 	  as_perror (_("can't open list file: %s"), name);
 	  list_file = stdout;
 	  using_stdout = 1;
@@ -1112,9 +1105,7 @@ listing_print (char *name)
     {
       if (fclose (list_file) == EOF)
 	{
-#ifdef BFD_ASSEMBLER
 	  bfd_set_error (bfd_error_system_call);
-#endif
 	  as_perror (_("error closing list file: %s"), name);
 	}
     }
diff --git a/gas/listing.h b/gas/listing.h
index 424b6642d046..e234da4cb403 100644
--- a/gas/listing.h
+++ b/gas/listing.h
@@ -1,6 +1,6 @@
 /* This file is listing.h
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1995, 1997, 1998
-   Free Software Foundation, Inc.
+   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1995, 1997, 1998,
+   2003 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef __listing_h__
 #define __listing_h__
diff --git a/gas/literal.c b/gas/literal.c
index 7315f3eee035..cc3a25749719 100644
--- a/gas/literal.c
+++ b/gas/literal.c
@@ -1,5 +1,5 @@
-/* as.c - GAS literal pool management.
-   Copyright 1994, 2000 Free Software Foundation, Inc.
+/* literal.c - GAS literal pool management.
+   Copyright 1994, 2000, 2005 Free Software Foundation, Inc.
    Written by Ken Raeburn (raeburn@cygnus.com).
 
    This file is part of GAS, the GNU Assembler.
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* This isn't quite a "constant" pool.  Some of the values may get
    adjusted at run time, e.g., for symbolic relocations when shared
@@ -39,7 +39,7 @@
 #include "as.h"
 #include "subsegs.h"
 
-#if defined (BFD_ASSEMBLER) && defined (NEED_LITERAL_POOL)
+#ifdef NEED_LITERAL_POOL
 
 valueT
 add_to_literal_pool (sym, addend, sec, size)
@@ -92,4 +92,4 @@ add_to_literal_pool (sym, addend, sec, size)
   seginfo->literal_pool_size += size;
   return offset;
 }
-#endif /* BFD_ASSEMBLER */
+#endif
diff --git a/gas/m68k-parse.c b/gas/m68k-parse.c
index 3650ba3f8fcb..5258dda60c53 100644
--- a/gas/m68k-parse.c
+++ b/gas/m68k-parse.c
@@ -1,21 +1,92 @@
-/* A Bison parser, made from m68k-parse.y
-   by GNU bison 1.35.  */
+/* A Bison parser, made by GNU Bison 2.1.  */
 
-#define YYBISON 1  /* Identify Bison output.  */
+/* Skeleton parser for Yacc-like parsing with Bison,
+   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
-# define	DR	257
-# define	AR	258
-# define	FPR	259
-# define	FPCR	260
-# define	LPC	261
-# define	ZAR	262
-# define	ZDR	263
-# define	LZPC	264
-# define	CREG	265
-# define	INDEXREG	266
-# define	EXPR	267
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street, Fifth Floor,
+   Boston, MA 02110-1301, USA.  */
 
-#line 27 "m68k-parse.y"
+/* As a special exception, when this file is copied by Bison into a
+   Bison output file, you may use that output file without restriction.
+   This special exception was added by the Free Software Foundation
+   in version 1.24 of Bison.  */
+
+/* Written by Richard Stallman by simplifying the original so called
+   ``semantic'' parser.  */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+   infringing on user name space.  This should be done even for local
+   variables, as they might otherwise be expanded by user macros.
+   There are some unavoidable exceptions within include files to
+   define necessary library symbols; they are noted "INFRINGES ON
+   USER NAME SPACE" below.  */
+
+/* Identify Bison output.  */
+#define YYBISON 1
+
+/* Bison version.  */
+#define YYBISON_VERSION "2.1"
+
+/* Skeleton name.  */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers.  */
+#define YYPURE 0
+
+/* Using locations.  */
+#define YYLSP_NEEDED 0
+
+
+
+/* Tokens.  */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+   /* Put the tokens into the symbol table, so that GDB and other debuggers
+      know about them.  */
+   enum yytokentype {
+     DR = 258,
+     AR = 259,
+     FPR = 260,
+     FPCR = 261,
+     LPC = 262,
+     ZAR = 263,
+     ZDR = 264,
+     LZPC = 265,
+     CREG = 266,
+     INDEXREG = 267,
+     EXPR = 268
+   };
+#endif
+/* Tokens.  */
+#define DR 258
+#define AR 259
+#define FPR 260
+#define FPCR 261
+#define LPC 262
+#define ZAR 263
+#define ZDR 264
+#define LZPC 265
+#define CREG 266
+#define INDEXREG 267
+#define EXPR 268
+
+
+
+
+/* Copy the first part of user declarations.  */
+#line 28 "m68k-parse.y"
 
 
 #include "as.h"
@@ -27,7 +98,7 @@
    etc), as well as gratuitously global symbol names If other parser
    generators (bison, byacc, etc) produce additional global names that
    conflict at link time, then those parser generators need to be
-   fixed instead of adding those names to this list. */
+   fixed instead of adding those names to this list.  */
 
 #define	yymaxdepth m68k_maxdepth
 #define	yyparse	m68k_parse
@@ -74,351 +145,97 @@
 
 /* Internal functions.  */
 
-static enum m68k_register m68k_reg_parse PARAMS ((char **));
-static int yylex PARAMS ((void));
-static void yyerror PARAMS ((const char *));
+static enum m68k_register m68k_reg_parse (char **);
+static int yylex (void);
+static void yyerror (const char *);
 
 /* The parser sets fields pointed to by this global variable.  */
 static struct m68k_op *op;
 
 
-#line 94 "m68k-parse.y"
-#ifndef YYSTYPE
-typedef union
-{
+
+/* Enabling traces.  */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages.  */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table.  */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined (YYSTYPE) && ! defined (YYSTYPE_IS_DECLARED)
+#line 96 "m68k-parse.y"
+typedef union YYSTYPE {
   struct m68k_indexreg indexreg;
   enum m68k_register reg;
   struct m68k_exp exp;
   unsigned long mask;
   int onereg;
-} yystype;
-# define YYSTYPE yystype
+  int trailing_ampersand;
+} YYSTYPE;
+/* Line 196 of yacc.c.  */
+#line 187 "m68k-parse.c"
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
 # define YYSTYPE_IS_TRIVIAL 1
 #endif
-#ifndef YYDEBUG
-# define YYDEBUG 0
-#endif
 
 
 
-#define	YYFINAL		173
-#define	YYFLAG		-32768
-#define	YYNTBASE	25
+/* Copy the second part of user declarations.  */
 
-/* YYTRANSLATE(YYLEX) -- Bison token number corresponding to YYLEX. */
-#define YYTRANSLATE(x) ((unsigned)(x) <= 267 ? yytranslate[x] : 44)
 
-/* YYTRANSLATE[YYLEX] -- Bison token number corresponding to YYLEX. */
-static const char yytranslate[] =
-{
-       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,    14,     2,     2,    15,     2,
-      16,    17,     2,    18,    20,    19,     2,    24,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,    23,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,    21,     2,    22,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
-       2,     2,     2,     2,     2,     2,     1,     3,     4,     5,
-       6,     7,     8,     9,    10,    11,    12,    13
-};
-
-#if YYDEBUG
-static const short yyprhs[] =
-{
-       0,     0,     2,     4,     6,     8,    10,    12,    14,    16,
-      18,    21,    24,    26,    30,    35,    40,    46,    52,    57,
-      61,    65,    69,    77,    85,    92,    98,   105,   111,   118,
-     124,   130,   135,   145,   153,   162,   169,   180,   189,   200,
-     209,   218,   221,   225,   229,   235,   242,   253,   263,   274,
-     276,   278,   280,   282,   284,   286,   288,   290,   292,   294,
-     296,   298,   300,   302,   303,   305,   307,   309,   310,   313,
-     314,   317,   318,   321,   323,   327,   331,   333,   335,   339,
-     343,   347,   349,   351,   353
-};
-static const short yyrhs[] =
-{
-      26,     0,    27,     0,    28,     0,     3,     0,     4,     0,
-       5,     0,     6,     0,    11,     0,    13,     0,    14,    13,
-       0,    15,    13,     0,    40,     0,    16,     4,    17,     0,
-      16,     4,    17,    18,     0,    19,    16,     4,    17,     0,
-      16,    13,    20,    34,    17,     0,    16,    34,    20,    13,
-      17,     0,    13,    16,    34,    17,     0,    16,     7,    17,
-       0,    16,     8,    17,     0,    16,    10,    17,     0,    16,
-      13,    20,    34,    20,    29,    17,     0,    16,    13,    20,
-      34,    20,    36,    17,     0,    16,    13,    20,    30,    37,
-      17,     0,    16,    30,    20,    13,    17,     0,    13,    16,
-      34,    20,    29,    17,     0,    16,    34,    20,    29,    17,
-       0,    13,    16,    34,    20,    36,    17,     0,    16,    34,
-      20,    36,    17,     0,    13,    16,    30,    37,    17,     0,
-      16,    30,    37,    17,     0,    16,    21,    13,    37,    22,
-      20,    29,    38,    17,     0,    16,    21,    13,    37,    22,
-      38,    17,     0,    16,    21,    34,    22,    20,    29,    38,
-      17,     0,    16,    21,    34,    22,    38,    17,     0,    16,
-      21,    13,    20,    34,    20,    29,    22,    38,    17,     0,
-      16,    21,    34,    20,    29,    22,    38,    17,     0,    16,
-      21,    13,    20,    34,    20,    36,    22,    38,    17,     0,
-      16,    21,    34,    20,    36,    22,    38,    17,     0,    16,
-      21,    39,    30,    37,    22,    38,    17,     0,    35,    23,
-       0,    35,    23,    18,     0,    35,    23,    19,     0,    35,
-      23,    16,    13,    17,     0,    35,    23,    16,    39,    29,
-      17,     0,    35,    23,    16,    13,    17,    23,    16,    39,
-      29,    17,     0,    35,    23,    16,    13,    17,    23,    16,
-      13,    17,     0,    35,    23,    16,    39,    29,    17,    23,
-      16,    13,    17,     0,    12,     0,    31,     0,    12,     0,
-      32,     0,    32,     0,     4,     0,     8,     0,     3,     0,
-       9,     0,     4,     0,     7,     0,    33,     0,    10,     0,
-       8,     0,     0,    34,     0,     7,     0,    10,     0,     0,
-      20,    34,     0,     0,    20,    13,     0,     0,    13,    20,
-       0,    42,     0,    42,    24,    41,     0,    43,    24,    41,
-       0,    43,     0,    42,     0,    42,    24,    41,     0,    43,
-      24,    41,     0,    43,    19,    43,     0,     3,     0,     4,
-       0,     5,     0,     6,     0
-};
+/* Line 219 of yacc.c.  */
+#line 199 "m68k-parse.c"
 
+#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
+# define YYSIZE_T __SIZE_TYPE__
 #endif
-
-#if YYDEBUG
-/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
-static const short yyrline[] =
-{
-       0,   117,   119,   120,   125,   131,   136,   141,   146,   151,
-     156,   161,   166,   178,   184,   189,   194,   204,   214,   224,
-     229,   234,   239,   246,   257,   264,   270,   277,   283,   294,
-     304,   311,   317,   325,   332,   339,   345,   353,   360,   372,
-     383,   395,   404,   412,   420,   430,   437,   445,   452,   465,
-     467,   479,   481,   492,   494,   495,   500,   502,   507,   509,
-     515,   517,   518,   523,   528,   533,   535,   540,   545,   553,
-     559,   567,   573,   581,   583,   587,   598,   603,   604,   608,
-     614,   624,   629,   633,   637
-};
+#if ! defined (YYSIZE_T) && defined (size_t)
+# define YYSIZE_T size_t
 #endif
-
-
-#if (YYDEBUG) || defined YYERROR_VERBOSE
-
-/* YYTNAME[TOKEN_NUM] -- String name of the token TOKEN_NUM. */
-static const char *const yytname[] =
-{
-  "$", "error", "$undefined.", "DR", "AR", "FPR", "FPCR", "LPC", "ZAR", 
-  "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'#'", "'&'", "'('", "')'", 
-  "'+'", "'-'", "','", "'['", "']'", "'@'", "'/'", "operand", 
-  "generic_operand", "motorola_operand", "mit_operand", "zireg", "zdireg", 
-  "zadr", "zdr", "apc", "zapc", "optzapc", "zpc", "optczapc", "optcexpr", 
-  "optexprc", "reglist", "ireglist", "reglistpair", "reglistreg", 0
-};
+#if ! defined (YYSIZE_T) && (defined (__STDC__) || defined (__cplusplus))
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+#endif
+#if ! defined (YYSIZE_T)
+# define YYSIZE_T unsigned int
 #endif
 
-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
-static const short yyr1[] =
-{
-       0,    25,    25,    25,    26,    26,    26,    26,    26,    26,
-      26,    26,    26,    27,    27,    27,    27,    27,    27,    27,
-      27,    27,    27,    27,    27,    27,    27,    27,    27,    27,
-      27,    27,    27,    27,    27,    27,    27,    27,    27,    27,
-      27,    28,    28,    28,    28,    28,    28,    28,    28,    29,
-      29,    30,    30,    31,    31,    31,    32,    32,    33,    33,
-      34,    34,    34,    35,    35,    36,    36,    37,    37,    38,
-      38,    39,    39,    40,    40,    40,    41,    41,    41,    41,
-      42,    43,    43,    43,    43
-};
-
-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
-static const short yyr2[] =
-{
-       0,     1,     1,     1,     1,     1,     1,     1,     1,     1,
-       2,     2,     1,     3,     4,     4,     5,     5,     4,     3,
-       3,     3,     7,     7,     6,     5,     6,     5,     6,     5,
-       5,     4,     9,     7,     8,     6,    10,     8,    10,     8,
-       8,     2,     3,     3,     5,     6,    10,     9,    10,     1,
-       1,     1,     1,     1,     1,     1,     1,     1,     1,     1,
-       1,     1,     1,     0,     1,     1,     1,     0,     2,     0,
-       2,     0,     2,     1,     3,     3,     1,     1,     3,     3,
-       3,     1,     1,     1,     1
-};
-
-/* YYDEFACT[S] -- default rule to reduce with in state S when YYTABLE
-   doesn't specify something else to do.  Zero means the default is an
-   error. */
-static const short yydefact[] =
-{
-      63,    81,    82,    83,    84,    59,    62,    61,     8,     9,
-       0,     0,     0,     0,     1,     2,     3,    60,    64,     0,
-      12,    73,     0,     0,    10,    11,    56,    58,    59,    62,
-      57,    61,    51,     0,    71,    67,    52,     0,     0,    41,
-       0,     0,     0,    58,    67,     0,    13,    19,    20,    21,
-       0,    67,     0,     0,     0,     0,     0,     0,    71,    42,
-      43,    81,    82,    83,    84,    74,    77,    76,    80,    75,
-       0,     0,    18,     0,    14,    67,     0,    72,     0,     0,
-      69,    67,     0,    68,    31,    54,    65,    55,    66,    49,
-       0,     0,    50,    53,     0,    15,     0,     0,     0,     0,
-      30,     0,     0,     0,    16,     0,    68,    69,     0,     0,
-       0,     0,     0,    25,    17,    27,    29,    44,    72,     0,
-      78,    79,    26,    28,    24,     0,     0,     0,     0,     0,
-      69,    69,    70,    69,    35,    69,     0,    45,    22,    23,
-       0,     0,    69,    33,     0,     0,     0,     0,     0,    71,
-       0,    69,    69,     0,    37,    39,    34,    40,     0,     0,
-       0,     0,     0,    32,    47,     0,     0,    36,    38,    46,
-      48,     0,     0,     0
-};
-
-static const short yydefgoto[] =
-{
-     171,    14,    15,    16,    91,    35,    92,    93,    17,    83,
-      19,    94,    55,   111,    53,    20,    65,    66,    67
-};
-
-static const short yypact[] =
-{
-      89,    10,    11,    19,    23,-32768,-32768,-32768,-32768,    13,
-      -4,    22,    57,    36,-32768,-32768,-32768,-32768,-32768,    18,
-  -32768,    33,    -2,   114,-32768,-32768,-32768,    46,    62,    66,
-  -32768,    67,-32768,    68,   131,    69,-32768,    70,   105,   147,
-     156,   156,   156,-32768,    94,    25,   101,-32768,-32768,-32768,
-     114,   100,    53,     9,   138,   108,   103,   112,   117,-32768,
-  -32768,-32768,-32768,-32768,-32768,-32768,   119,    12,-32768,-32768,
-      64,   130,-32768,   124,-32768,    94,    81,    64,   135,   124,
-     132,    94,   150,-32768,-32768,-32768,-32768,-32768,-32768,-32768,
-     151,   152,-32768,-32768,   153,-32768,   120,   146,   156,   156,
-  -32768,   154,   155,   157,-32768,   124,   144,   158,   159,   160,
-      73,   162,   161,-32768,-32768,-32768,-32768,   163,-32768,   167,
-  -32768,-32768,-32768,-32768,-32768,   168,   170,   124,    73,   171,
-     169,   169,-32768,   169,-32768,   169,   164,   172,-32768,-32768,
-     174,   175,   169,-32768,   177,   176,   181,   182,   183,   178,
-     185,   169,   169,   186,-32768,-32768,-32768,-32768,   136,   146,
-     179,   187,   188,-32768,-32768,   189,   190,-32768,-32768,-32768,
-  -32768,   173,   194,-32768
-};
-
-static const short yypgoto[] =
-{
-  -32768,-32768,-32768,-32768,   -72,     1,-32768,    -7,-32768,     3,
-  -32768,   -65,   -31,  -103,   -58,-32768,   -40,   202,     6
-};
-
-
-#define	YYLAST		207
-
-
-static const short yytable[] =
-{
-      97,   101,    69,    18,   129,    36,    22,   108,   102,    24,
-      -4,    -5,    26,    71,   109,    37,    36,    41,    30,    -6,
-      78,    32,    42,    -7,    44,   119,    45,   145,   146,    23,
-     147,    41,   148,   125,   -58,    25,    99,    52,   133,   153,
-     126,    39,    72,    36,   103,    73,    36,    68,   161,   162,
-     112,    75,    38,    76,    81,   140,   142,    40,   120,   121,
-      26,    27,   141,    46,    28,    29,    30,    31,    43,    32,
-      33,     5,     6,    79,     7,    80,    26,    85,    34,    47,
-     106,    87,    30,    48,    49,    89,   132,   165,    50,    54,
-      56,   159,     1,     2,     3,     4,     5,     6,   104,     7,
-       8,   105,     9,    10,    11,    12,    26,    85,    13,    57,
-      86,    87,    30,    88,    70,    89,    90,    26,    43,    74,
-      77,     5,     6,    30,     7,    84,    32,    26,    85,    95,
-      96,    86,    87,    30,    88,    43,    89,   117,     5,     6,
-     118,     7,    43,    98,    51,     5,     6,   100,     7,    26,
-      85,    82,   110,   164,    87,    30,   118,   107,    89,    61,
-      62,    63,    64,    58,   127,    59,    60,   113,   114,   115,
-     116,   122,   123,   172,   124,     0,     0,     0,   128,   134,
-     149,   130,   131,   135,   137,   138,   136,   139,   143,   144,
-     132,   158,   166,   154,   173,   150,   151,   152,   155,   156,
-     157,   160,    21,   163,   167,   168,   169,   170
-};
-
-static const short yycheck[] =
-{
-      58,    73,    42,     0,   107,    12,     0,    79,    73,    13,
-       0,     0,     3,    44,    79,    12,    23,    19,     9,     0,
-      51,    12,    24,     0,    23,    97,    23,   130,   131,    16,
-     133,    19,   135,   105,    23,    13,    24,    34,   110,   142,
-     105,    23,    17,    50,    75,    20,    53,    41,   151,   152,
-      81,    50,    16,    50,    53,   127,   128,    24,    98,    99,
-       3,     4,   127,    17,     7,     8,     9,    10,     4,    12,
-      13,     7,     8,    20,    10,    22,     3,     4,    21,    17,
-      77,     8,     9,    17,    17,    12,    13,   159,    20,    20,
-      20,   149,     3,     4,     5,     6,     7,     8,    17,    10,
-      11,    20,    13,    14,    15,    16,     3,     4,    19,     4,
-       7,     8,     9,    10,    20,    12,    13,     3,     4,    18,
-      20,     7,     8,     9,    10,    17,    12,     3,     4,    17,
-      13,     7,     8,     9,    10,     4,    12,    17,     7,     8,
-      20,    10,     4,    24,    13,     7,     8,    17,    10,     3,
-       4,    13,    20,    17,     8,     9,    20,    22,    12,     3,
-       4,     5,     6,    16,    20,    18,    19,    17,    17,    17,
-      17,    17,    17,     0,    17,    -1,    -1,    -1,    20,    17,
-      16,    22,    22,    22,    17,    17,    23,    17,    17,    20,
-      13,    13,    13,    17,     0,    23,    22,    22,    17,    17,
-      17,    16,     0,    17,    17,    17,    17,    17
-};
-/* -*-C-*-  Note some compilers choke on comments on `#line' lines.  */
-#line 3 "/usr/share/bison-1.35/bison.simple"
-
-/* Skeleton output parser for bison,
-
-   Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002 Free Software
-   Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 2, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330,
-   Boston, MA 02111-1307, USA.  */
-
-/* As a special exception, when this file is copied by Bison into a
-   Bison output file, you may use that output file without restriction.
-   This special exception was added by the Free Software Foundation
-   in version 1.24 of Bison.  */
-
-/* This is the parser code that is written into each bison parser when
-   the %semantic_parser declaration is not specified in the grammar.
-   It was written by Richard Stallman by simplifying the hairy parser
-   used when %semantic_parser is specified.  */
-
-/* All symbols defined below should begin with yy or YY, to avoid
-   infringing on user name space.  This should be done even for local
-   variables, as they might otherwise be expanded by user macros.
-   There are some unavoidable exceptions within include files to
-   define necessary library symbols; they are noted "INFRINGES ON
-   USER NAME SPACE" below.  */
+#ifndef YY_
+# if YYENABLE_NLS
+#  if ENABLE_NLS
+#   include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+#   define YY_(msgid) dgettext ("bison-runtime", msgid)
+#  endif
+# endif
+# ifndef YY_
+#  define YY_(msgid) msgid
+# endif
+#endif
 
-#if ! defined (yyoverflow) || defined (YYERROR_VERBOSE)
+#if ! defined (yyoverflow) || YYERROR_VERBOSE
 
 /* The parser invokes alloca or malloc; define the necessary symbols.  */
 
-# if YYSTACK_USE_ALLOCA
-#  define YYSTACK_ALLOC alloca
-# else
-#  ifndef YYSTACK_USE_ALLOCA
-#   if defined (alloca) || defined (_ALLOCA_H)
-#    define YYSTACK_ALLOC alloca
+# ifdef YYSTACK_USE_ALLOCA
+#  if YYSTACK_USE_ALLOCA
+#   ifdef __GNUC__
+#    define YYSTACK_ALLOC __builtin_alloca
 #   else
-#    ifdef __GNUC__
-#     define YYSTACK_ALLOC __builtin_alloca
+#    define YYSTACK_ALLOC alloca
+#    if defined (__STDC__) || defined (__cplusplus)
+#     include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+#     define YYINCLUDED_STDLIB_H
 #    endif
 #   endif
 #  endif
@@ -427,57 +244,74 @@ static const short yycheck[] =
 # ifdef YYSTACK_ALLOC
    /* Pacify GCC's `empty if-body' warning. */
 #  define YYSTACK_FREE(Ptr) do { /* empty */; } while (0)
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+    /* The OS might guarantee only one guard page at the bottom of the stack,
+       and a page size can be as small as 4096 bytes.  So we cannot safely
+       invoke alloca (N) if N exceeds 4096.  Use a slightly smaller number
+       to allow for a few compiler-allocated temporary stack slots.  */
+#   define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2005 */
+#  endif
 # else
-#  if defined (__STDC__) || defined (__cplusplus)
-#   include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
-#   define YYSIZE_T size_t
+#  define YYSTACK_ALLOC YYMALLOC
+#  define YYSTACK_FREE YYFREE
+#  ifndef YYSTACK_ALLOC_MAXIMUM
+#   define YYSTACK_ALLOC_MAXIMUM ((YYSIZE_T) -1)
+#  endif
+#  ifdef __cplusplus
+extern "C" {
+#  endif
+#  ifndef YYMALLOC
+#   define YYMALLOC malloc
+#   if (! defined (malloc) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifndef YYFREE
+#   define YYFREE free
+#   if (! defined (free) && ! defined (YYINCLUDED_STDLIB_H) \
+	&& (defined (__STDC__) || defined (__cplusplus)))
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+#   endif
+#  endif
+#  ifdef __cplusplus
+}
 #  endif
-#  define YYSTACK_ALLOC malloc
-#  define YYSTACK_FREE free
 # endif
-#endif /* ! defined (yyoverflow) || defined (YYERROR_VERBOSE) */
+#endif /* ! defined (yyoverflow) || YYERROR_VERBOSE */
 
 
 #if (! defined (yyoverflow) \
      && (! defined (__cplusplus) \
-	 || (YYLTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+	 || (defined (YYSTYPE_IS_TRIVIAL) && YYSTYPE_IS_TRIVIAL)))
 
 /* A type that is properly aligned for any stack member.  */
 union yyalloc
 {
-  short yyss;
+  short int yyss;
   YYSTYPE yyvs;
-# if YYLSP_NEEDED
-  YYLTYPE yyls;
-# endif
-};
+  };
 
 /* The size of the maximum gap between one aligned stack and the next.  */
-# define YYSTACK_GAP_MAX (sizeof (union yyalloc) - 1)
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
 
 /* The size of an array large to enough to hold all stacks, each with
    N elements.  */
-# if YYLSP_NEEDED
-#  define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short) + sizeof (YYSTYPE) + sizeof (YYLTYPE))	\
-      + 2 * YYSTACK_GAP_MAX)
-# else
-#  define YYSTACK_BYTES(N) \
-     ((N) * (sizeof (short) + sizeof (YYSTYPE))				\
-      + YYSTACK_GAP_MAX)
-# endif
+# define YYSTACK_BYTES(N) \
+     ((N) * (sizeof (short int) + sizeof (YYSTYPE))			\
+      + YYSTACK_GAP_MAXIMUM)
 
 /* Copy COUNT objects from FROM to TO.  The source and destination do
    not overlap.  */
 # ifndef YYCOPY
-#  if 1 < __GNUC__
+#  if defined (__GNUC__) && 1 < __GNUC__
 #   define YYCOPY(To, From, Count) \
       __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
 #  else
 #   define YYCOPY(To, From, Count)		\
       do					\
 	{					\
-	  register YYSIZE_T yyi;		\
+	  YYSIZE_T yyi;				\
 	  for (yyi = 0; yyi < (Count); yyi++)	\
 	    (To)[yyi] = (From)[yyi];		\
 	}					\
@@ -496,98 +330,436 @@ union yyalloc
 	YYSIZE_T yynewbytes;						\
 	YYCOPY (&yyptr->Stack, Stack, yysize);				\
 	Stack = &yyptr->Stack;						\
-	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAX;	\
+	yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
 	yyptr += yynewbytes / sizeof (*yyptr);				\
       }									\
     while (0)
 
 #endif
 
+#if defined (__STDC__) || defined (__cplusplus)
+   typedef signed char yysigned_char;
+#else
+   typedef short int yysigned_char;
+#endif
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL  44
+/* YYLAST -- Last index in YYTABLE.  */
+#define YYLAST   215
 
-#if ! defined (YYSIZE_T) && defined (__SIZE_TYPE__)
-# define YYSIZE_T __SIZE_TYPE__
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS  27
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS  21
+/* YYNRULES -- Number of rules. */
+#define YYNRULES  89
+/* YYNRULES -- Number of states. */
+#define YYNSTATES  180
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX.  */
+#define YYUNDEFTOK  2
+#define YYMAXUTOK   268
+
+#define YYTRANSLATE(YYX)						\
+  ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX.  */
+static const unsigned char yytranslate[] =
+{
+       0,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,    17,     2,     2,    14,     2,
+      18,    19,     2,    20,    22,    21,     2,    26,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+      15,     2,    16,     2,    25,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,    23,     2,    24,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     2,     2,     2,     2,
+       2,     2,     2,     2,     2,     2,     1,     2,     3,     4,
+       5,     6,     7,     8,     9,    10,    11,    12,    13
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+   YYRHS.  */
+static const unsigned short int yyprhs[] =
+{
+       0,     0,     3,     5,     8,    11,    12,    14,    17,    20,
+      22,    24,    26,    28,    30,    32,    35,    38,    40,    44,
+      49,    54,    60,    66,    71,    75,    79,    83,    91,    99,
+     106,   112,   119,   125,   132,   138,   144,   149,   159,   167,
+     176,   183,   194,   203,   214,   223,   232,   235,   239,   243,
+     249,   256,   267,   277,   288,   290,   292,   294,   296,   298,
+     300,   302,   304,   306,   308,   310,   312,   314,   316,   317,
+     319,   321,   323,   324,   327,   328,   331,   332,   335,   337,
+     341,   345,   347,   349,   353,   357,   361,   363,   365,   367
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+static const yysigned_char yyrhs[] =
+{
+      28,     0,    -1,    30,    -1,    31,    29,    -1,    32,    29,
+      -1,    -1,    14,    -1,    15,    15,    -1,    16,    16,    -1,
+       3,    -1,     4,    -1,     5,    -1,     6,    -1,    11,    -1,
+      13,    -1,    17,    13,    -1,    14,    13,    -1,    44,    -1,
+      18,     4,    19,    -1,    18,     4,    19,    20,    -1,    21,
+      18,     4,    19,    -1,    18,    13,    22,    38,    19,    -1,
+      18,    38,    22,    13,    19,    -1,    13,    18,    38,    19,
+      -1,    18,     7,    19,    -1,    18,     8,    19,    -1,    18,
+      10,    19,    -1,    18,    13,    22,    38,    22,    33,    19,
+      -1,    18,    13,    22,    38,    22,    40,    19,    -1,    18,
+      13,    22,    34,    41,    19,    -1,    18,    34,    22,    13,
+      19,    -1,    13,    18,    38,    22,    33,    19,    -1,    18,
+      38,    22,    33,    19,    -1,    13,    18,    38,    22,    40,
+      19,    -1,    18,    38,    22,    40,    19,    -1,    13,    18,
+      34,    41,    19,    -1,    18,    34,    41,    19,    -1,    18,
+      23,    13,    41,    24,    22,    33,    42,    19,    -1,    18,
+      23,    13,    41,    24,    42,    19,    -1,    18,    23,    38,
+      24,    22,    33,    42,    19,    -1,    18,    23,    38,    24,
+      42,    19,    -1,    18,    23,    13,    22,    38,    22,    33,
+      24,    42,    19,    -1,    18,    23,    38,    22,    33,    24,
+      42,    19,    -1,    18,    23,    13,    22,    38,    22,    40,
+      24,    42,    19,    -1,    18,    23,    38,    22,    40,    24,
+      42,    19,    -1,    18,    23,    43,    34,    41,    24,    42,
+      19,    -1,    39,    25,    -1,    39,    25,    20,    -1,    39,
+      25,    21,    -1,    39,    25,    18,    13,    19,    -1,    39,
+      25,    18,    43,    33,    19,    -1,    39,    25,    18,    13,
+      19,    25,    18,    43,    33,    19,    -1,    39,    25,    18,
+      13,    19,    25,    18,    13,    19,    -1,    39,    25,    18,
+      43,    33,    19,    25,    18,    13,    19,    -1,    12,    -1,
+      35,    -1,    12,    -1,    36,    -1,    36,    -1,     4,    -1,
+       8,    -1,     3,    -1,     9,    -1,     4,    -1,     7,    -1,
+      37,    -1,    10,    -1,     8,    -1,    -1,    38,    -1,     7,
+      -1,    10,    -1,    -1,    22,    38,    -1,    -1,    22,    13,
+      -1,    -1,    13,    22,    -1,    46,    -1,    46,    26,    45,
+      -1,    47,    26,    45,    -1,    47,    -1,    46,    -1,    46,
+      26,    45,    -1,    47,    26,    45,    -1,    47,    21,    47,
+      -1,     3,    -1,     4,    -1,     5,    -1,     6,    -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined.  */
+static const unsigned short int yyrline[] =
+{
+       0,   121,   121,   122,   126,   135,   136,   143,   148,   153,
+     158,   163,   168,   173,   178,   183,   188,   193,   206,   211,
+     216,   221,   231,   241,   251,   256,   261,   266,   273,   284,
+     291,   297,   304,   310,   321,   331,   338,   344,   352,   359,
+     366,   372,   380,   387,   399,   410,   423,   431,   439,   447,
+     457,   464,   472,   479,   493,   494,   507,   508,   520,   521,
+     522,   528,   529,   535,   536,   543,   544,   545,   552,   555,
+     561,   562,   569,   572,   582,   586,   596,   600,   609,   610,
+     614,   626,   630,   631,   635,   642,   652,   656,   660,   664
+};
 #endif
-#if ! defined (YYSIZE_T) && defined (size_t)
-# define YYSIZE_T size_t
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+   First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+  "$end", "error", "$undefined", "DR", "AR", "FPR", "FPCR", "LPC", "ZAR",
+  "ZDR", "LZPC", "CREG", "INDEXREG", "EXPR", "'&'", "'<'", "'>'", "'#'",
+  "'('", "')'", "'+'", "'-'", "','", "'['", "']'", "'@'", "'/'", "$accept",
+  "operand", "optional_ampersand", "generic_operand", "motorola_operand",
+  "mit_operand", "zireg", "zdireg", "zadr", "zdr", "apc", "zapc",
+  "optzapc", "zpc", "optczapc", "optcexpr", "optexprc", "reglist",
+  "ireglist", "reglistpair", "reglistreg", 0
+};
 #endif
-#if ! defined (YYSIZE_T)
-# if defined (__STDC__) || defined (__cplusplus)
-#  include <stddef.h> /* INFRINGES ON USER NAME SPACE */
-#  define YYSIZE_T size_t
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+   token YYLEX-NUM.  */
+static const unsigned short int yytoknum[] =
+{
+       0,   256,   257,   258,   259,   260,   261,   262,   263,   264,
+     265,   266,   267,   268,    38,    60,    62,    35,    40,    41,
+      43,    45,    44,    91,    93,    64,    47
+};
 # endif
-#endif
-#if ! defined (YYSIZE_T)
-# define YYSIZE_T unsigned int
-#endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives.  */
+static const unsigned char yyr1[] =
+{
+       0,    27,    28,    28,    28,    29,    29,    30,    30,    30,
+      30,    30,    30,    30,    30,    30,    30,    30,    31,    31,
+      31,    31,    31,    31,    31,    31,    31,    31,    31,    31,
+      31,    31,    31,    31,    31,    31,    31,    31,    31,    31,
+      31,    31,    31,    31,    31,    31,    32,    32,    32,    32,
+      32,    32,    32,    32,    33,    33,    34,    34,    35,    35,
+      35,    36,    36,    37,    37,    38,    38,    38,    39,    39,
+      40,    40,    41,    41,    42,    42,    43,    43,    44,    44,
+      44,    45,    45,    45,    45,    46,    47,    47,    47,    47
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN.  */
+static const unsigned char yyr2[] =
+{
+       0,     2,     1,     2,     2,     0,     1,     2,     2,     1,
+       1,     1,     1,     1,     1,     2,     2,     1,     3,     4,
+       4,     5,     5,     4,     3,     3,     3,     7,     7,     6,
+       5,     6,     5,     6,     5,     5,     4,     9,     7,     8,
+       6,    10,     8,    10,     8,     8,     2,     3,     3,     5,
+       6,    10,     9,    10,     1,     1,     1,     1,     1,     1,
+       1,     1,     1,     1,     1,     1,     1,     1,     0,     1,
+       1,     1,     0,     2,     0,     2,     0,     2,     1,     3,
+       3,     1,     1,     3,     3,     3,     1,     1,     1,     1
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+   STATE-NUM when YYTABLE doesn't specify something else to do.  Zero
+   means the default is an error.  */
+static const unsigned char yydefact[] =
+{
+      68,    86,    87,    88,    89,    64,    67,    66,    13,    14,
+       0,     0,     0,     0,     0,     0,     0,     2,     5,     5,
+      65,    69,     0,    17,    78,     0,     0,    16,     7,     8,
+      15,    61,    63,    64,    67,    62,    66,    56,     0,    76,
+      72,    57,     0,     0,     1,     6,     3,     4,    46,     0,
+       0,     0,    63,    72,     0,    18,    24,    25,    26,     0,
+      72,     0,     0,     0,     0,     0,     0,    76,    47,    48,
+      86,    87,    88,    89,    79,    82,    81,    85,    80,     0,
+       0,    23,     0,    19,    72,     0,    77,     0,     0,    74,
+      72,     0,    73,    36,    59,    70,    60,    71,    54,     0,
+       0,    55,    58,     0,    20,     0,     0,     0,     0,    35,
+       0,     0,     0,    21,     0,    73,    74,     0,     0,     0,
+       0,     0,    30,    22,    32,    34,    49,    77,     0,    83,
+      84,    31,    33,    29,     0,     0,     0,     0,     0,    74,
+      74,    75,    74,    40,    74,     0,    50,    27,    28,     0,
+       0,    74,    38,     0,     0,     0,     0,     0,    76,     0,
+      74,    74,     0,    42,    44,    39,    45,     0,     0,     0,
+       0,     0,    37,    52,     0,     0,    41,    43,    51,    53
+};
+
+/* YYDEFGOTO[NTERM-NUM]. */
+static const yysigned_char yydefgoto[] =
+{
+      -1,    16,    46,    17,    18,    19,   100,    40,   101,   102,
+      20,    92,    22,   103,    64,   120,    62,    23,    74,    75,
+      76
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+   STATE-NUM.  */
+#define YYPACT_NINF -98
+static const short int yypact[] =
+{
+      89,    14,     9,    31,    35,   -98,   -98,   -98,   -98,     0,
+      36,    42,    28,    56,    63,    67,    90,   -98,    75,    75,
+     -98,   -98,    86,   -98,    96,   -15,   123,   -98,   -98,   -98,
+     -98,   -98,    97,   115,   119,   -98,   120,   -98,   122,    16,
+     126,   -98,   127,   157,   -98,   -98,   -98,   -98,    19,   154,
+     154,   154,   -98,   140,    29,   144,   -98,   -98,   -98,   123,
+     141,    99,    18,    70,   147,   105,   148,   152,   -98,   -98,
+     -98,   -98,   -98,   -98,   -98,   142,   -13,   -98,   -98,   146,
+     150,   -98,   133,   -98,   140,    60,   146,   149,   133,   153,
+     140,   151,   -98,   -98,   -98,   -98,   -98,   -98,   -98,   155,
+     158,   -98,   -98,   159,   -98,    62,   143,   154,   154,   -98,
+     160,   161,   162,   -98,   133,   163,   164,   165,   166,   116,
+     168,   167,   -98,   -98,   -98,   -98,   169,   -98,   173,   -98,
+     -98,   -98,   -98,   -98,   174,   176,   133,   116,   177,   175,
+     175,   -98,   175,   -98,   175,   170,   178,   -98,   -98,   180,
+     181,   175,   -98,   171,   179,   182,   183,   187,   186,   189,
+     175,   175,   190,   -98,   -98,   -98,   -98,    79,   143,   195,
+     191,   192,   -98,   -98,   193,   194,   -98,   -98,   -98,   -98
+};
+
+/* YYPGOTO[NTERM-NUM].  */
+static const short int yypgoto[] =
+{
+     -98,   -98,   196,   -98,   -98,   -98,   -81,     6,   -98,    -9,
+     -98,     2,   -98,   -78,   -38,   -97,   -67,   -98,   -48,   172,
+      12
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]].  What to do in state STATE-NUM.  If
+   positive, shift that token.  If negative, reduce the rule which
+   number is the opposite.  If zero, do what YYDEFACT says.
+   If YYTABLE_NINF, syntax error.  */
+#define YYTABLE_NINF -64
+static const short int yytable[] =
+{
+     106,   110,    21,    78,   111,    41,    50,   117,    50,   -10,
+     118,    51,    25,   108,    -9,    80,    42,    41,    26,   138,
+      52,    31,    87,     5,     6,   128,     7,    35,    54,    60,
+      37,   -11,    53,   134,   -63,   -12,   135,    67,   142,    68,
+      69,    61,   154,   155,    29,   156,   112,   157,    81,    27,
+      41,    82,   121,    41,   162,   149,   151,    28,   150,   129,
+     130,    85,    77,   170,   171,    84,    31,    32,    90,    30,
+      33,    34,    35,    36,    52,    37,    38,     5,     6,   113,
+       7,   126,   114,    91,   127,    43,    39,   174,   115,    45,
+      44,   168,     1,     2,     3,     4,     5,     6,   173,     7,
+       8,   127,     9,    10,    11,    12,    13,    14,    31,    94,
+      15,    48,    95,    96,    35,    97,    55,    98,    99,    31,
+      94,    88,    49,    89,    96,    35,    31,    52,    98,   141,
+       5,     6,    35,     7,    56,    37,    31,    94,    57,    58,
+      95,    96,    35,    97,    59,    98,    31,    94,    63,    65,
+      52,    96,    35,     5,     6,    98,     7,    70,    71,    72,
+      73,    66,    79,    86,    83,   105,    93,   104,   107,   109,
+     122,     0,    24,   116,   123,   119,     0,   124,   125,   131,
+     132,   133,     0,     0,   141,   136,   137,   143,   158,   139,
+     140,   144,   146,   147,   145,   148,   152,   153,   163,   167,
+       0,   164,   165,   159,   160,   161,   166,   169,   175,   172,
+     176,   177,   178,   179,     0,    47
+};
+
+static const short int yycheck[] =
+{
+      67,    82,     0,    51,    82,    14,    21,    88,    21,     0,
+      88,    26,     0,    26,     0,    53,    14,    26,    18,   116,
+       4,     3,    60,     7,     8,   106,    10,     9,    26,    13,
+      12,     0,    26,   114,    25,     0,   114,    18,   119,    20,
+      21,    39,   139,   140,    16,   142,    84,   144,    19,    13,
+      59,    22,    90,    62,   151,   136,   137,    15,   136,   107,
+     108,    59,    50,   160,   161,    59,     3,     4,    62,    13,
+       7,     8,     9,    10,     4,    12,    13,     7,     8,    19,
+      10,    19,    22,    13,    22,    18,    23,   168,    86,    14,
+       0,   158,     3,     4,     5,     6,     7,     8,    19,    10,
+      11,    22,    13,    14,    15,    16,    17,    18,     3,     4,
+      21,    25,     7,     8,     9,    10,    19,    12,    13,     3,
+       4,    22,    26,    24,     8,     9,     3,     4,    12,    13,
+       7,     8,     9,    10,    19,    12,     3,     4,    19,    19,
+       7,     8,     9,    10,    22,    12,     3,     4,    22,    22,
+       4,     8,     9,     7,     8,    12,    10,     3,     4,     5,
+       6,     4,    22,    22,    20,    13,    19,    19,    26,    19,
+      19,    -1,     0,    24,    19,    22,    -1,    19,    19,    19,
+      19,    19,    -1,    -1,    13,    22,    22,    19,    18,    24,
+      24,    24,    19,    19,    25,    19,    19,    22,    19,    13,
+      -1,    19,    19,    25,    24,    24,    19,    18,    13,    19,
+      19,    19,    19,    19,    -1,    19
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+   symbol of state STATE-NUM.  */
+static const unsigned char yystos[] =
+{
+       0,     3,     4,     5,     6,     7,     8,    10,    11,    13,
+      14,    15,    16,    17,    18,    21,    28,    30,    31,    32,
+      37,    38,    39,    44,    46,    47,    18,    13,    15,    16,
+      13,     3,     4,     7,     8,     9,    10,    12,    13,    23,
+      34,    36,    38,    18,     0,    14,    29,    29,    25,    26,
+      21,    26,     4,    34,    38,    19,    19,    19,    19,    22,
+      13,    38,    43,    22,    41,    22,     4,    18,    20,    21,
+       3,     4,     5,     6,    45,    46,    47,    47,    45,    22,
+      41,    19,    22,    20,    34,    38,    22,    41,    22,    24,
+      34,    13,    38,    19,     4,     7,     8,    10,    12,    13,
+      33,    35,    36,    40,    19,    13,    43,    26,    26,    19,
+      33,    40,    41,    19,    22,    38,    24,    33,    40,    22,
+      42,    41,    19,    19,    19,    19,    19,    22,    33,    45,
+      45,    19,    19,    19,    33,    40,    22,    22,    42,    24,
+      24,    13,    33,    19,    24,    25,    19,    19,    19,    33,
+      40,    33,    19,    22,    42,    42,    42,    42,    18,    25,
+      24,    24,    42,    19,    19,    19,    19,    13,    43,    18,
+      42,    42,    19,    19,    33,    13,    19,    19,    19,    19
+};
 
 #define yyerrok		(yyerrstatus = 0)
 #define yyclearin	(yychar = YYEMPTY)
-#define YYEMPTY		-2
+#define YYEMPTY		(-2)
 #define YYEOF		0
+
 #define YYACCEPT	goto yyacceptlab
-#define YYABORT 	goto yyabortlab
-#define YYERROR		goto yyerrlab1
+#define YYABORT		goto yyabortlab
+#define YYERROR		goto yyerrorlab
+
+
 /* Like YYERROR except do call yyerror.  This remains here temporarily
    to ease the transition to the new meaning of YYERROR, for GCC.
    Once GCC version 2 has supplanted version 1, this can go.  */
+
 #define YYFAIL		goto yyerrlab
+
 #define YYRECOVERING()  (!!yyerrstatus)
+
 #define YYBACKUP(Token, Value)					\
 do								\
   if (yychar == YYEMPTY && yylen == 1)				\
     {								\
       yychar = (Token);						\
       yylval = (Value);						\
-      yychar1 = YYTRANSLATE (yychar);				\
+      yytoken = YYTRANSLATE (yychar);				\
       YYPOPSTACK;						\
       goto yybackup;						\
     }								\
   else								\
-    { 								\
-      yyerror ("syntax error: cannot back up");			\
+    {								\
+      yyerror (YY_("syntax error: cannot back up")); \
       YYERROR;							\
     }								\
 while (0)
 
+
 #define YYTERROR	1
 #define YYERRCODE	256
 
 
-/* YYLLOC_DEFAULT -- Compute the default location (before the actions
-   are run).
-
-   When YYLLOC_DEFAULT is run, CURRENT is set the location of the
-   first token.  By default, to implement support for ranges, extend
-   its range to the last symbol.  */
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+   If N is 0, then set CURRENT to the empty location which ends
+   the previous symbol: RHS[0] (always defined).  */
 
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
 #ifndef YYLLOC_DEFAULT
-# define YYLLOC_DEFAULT(Current, Rhs, N)       	\
-   Current.last_line   = Rhs[N].last_line;	\
-   Current.last_column = Rhs[N].last_column;
+# define YYLLOC_DEFAULT(Current, Rhs, N)				\
+    do									\
+      if (N)								\
+	{								\
+	  (Current).first_line   = YYRHSLOC (Rhs, 1).first_line;	\
+	  (Current).first_column = YYRHSLOC (Rhs, 1).first_column;	\
+	  (Current).last_line    = YYRHSLOC (Rhs, N).last_line;		\
+	  (Current).last_column  = YYRHSLOC (Rhs, N).last_column;	\
+	}								\
+      else								\
+	{								\
+	  (Current).first_line   = (Current).last_line   =		\
+	    YYRHSLOC (Rhs, 0).last_line;				\
+	  (Current).first_column = (Current).last_column =		\
+	    YYRHSLOC (Rhs, 0).last_column;				\
+	}								\
+    while (0)
 #endif
 
 
-/* YYLEX -- calling `yylex' with the right arguments.  */
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+   This macro was not mandated originally: define only if we know
+   we won't break user code: when these are the locations we know.  */
 
-#if YYPURE
-# if YYLSP_NEEDED
-#  ifdef YYLEX_PARAM
-#   define YYLEX		yylex (&yylval, &yylloc, YYLEX_PARAM)
-#  else
-#   define YYLEX		yylex (&yylval, &yylloc)
-#  endif
-# else /* !YYLSP_NEEDED */
-#  ifdef YYLEX_PARAM
-#   define YYLEX		yylex (&yylval, YYLEX_PARAM)
-#  else
-#   define YYLEX		yylex (&yylval)
-#  endif
-# endif /* !YYLSP_NEEDED */
-#else /* !YYPURE */
-# define YYLEX			yylex ()
-#endif /* !YYPURE */
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+#  define YY_LOCATION_PRINT(File, Loc)			\
+     fprintf (File, "%d.%d-%d.%d",			\
+              (Loc).first_line, (Loc).first_column,	\
+              (Loc).last_line,  (Loc).last_column)
+# else
+#  define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
 
 
+/* YYLEX -- calling `yylex' with the right arguments.  */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
 /* Enable debugging if requested.  */
 #if YYDEBUG
 
@@ -601,13 +773,86 @@ do {						\
   if (yydebug)					\
     YYFPRINTF Args;				\
 } while (0)
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)		\
+do {								\
+  if (yydebug)							\
+    {								\
+      YYFPRINTF (stderr, "%s ", Title);				\
+      yysymprint (stderr,					\
+                  Type, Value);	\
+      YYFPRINTF (stderr, "\n");					\
+    }								\
+} while (0)
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included).                                                   |
+`------------------------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_stack_print (short int *bottom, short int *top)
+#else
+static void
+yy_stack_print (bottom, top)
+    short int *bottom;
+    short int *top;
+#endif
+{
+  YYFPRINTF (stderr, "Stack now");
+  for (/* Nothing. */; bottom <= top; ++bottom)
+    YYFPRINTF (stderr, " %d", *bottom);
+  YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top)				\
+do {								\
+  if (yydebug)							\
+    yy_stack_print ((Bottom), (Top));				\
+} while (0)
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced.  |
+`------------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yy_reduce_print (int yyrule)
+#else
+static void
+yy_reduce_print (yyrule)
+    int yyrule;
+#endif
+{
+  int yyi;
+  unsigned long int yylno = yyrline[yyrule];
+  YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu), ",
+             yyrule - 1, yylno);
+  /* Print the symbols being reduced, and their result.  */
+  for (yyi = yyprhs[yyrule]; 0 <= yyrhs[yyi]; yyi++)
+    YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
+  YYFPRINTF (stderr, "-> %s\n", yytname[yyr1[yyrule]]);
+}
+
+# define YY_REDUCE_PRINT(Rule)		\
+do {					\
+  if (yydebug)				\
+    yy_reduce_print (Rule);		\
+} while (0)
+
 /* Nonzero means print parse trace.  It is left uninitialized so that
    multiple parsers can coexist.  */
 int yydebug;
 #else /* !YYDEBUG */
 # define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
 #endif /* !YYDEBUG */
 
+
 /* YYINITDEPTH -- initial size of the parser's stacks.  */
 #ifndef	YYINITDEPTH
 # define YYINITDEPTH 200
@@ -617,18 +862,16 @@ int yydebug;
    if the built-in stack extension method is used).
 
    Do not make this value too large; the results are undefined if
-   SIZE_MAX < YYSTACK_BYTES (YYMAXDEPTH)
+   YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
    evaluated with infinite-precision integer arithmetic.  */
 
-#if YYMAXDEPTH == 0
-# undef YYMAXDEPTH
-#endif
-
 #ifndef YYMAXDEPTH
 # define YYMAXDEPTH 10000
 #endif
+
 
-#ifdef YYERROR_VERBOSE
+
+#if YYERROR_VERBOSE
 
 # ifndef yystrlen
 #  if defined (__GLIBC__) && defined (_STRING_H)
@@ -643,7 +886,7 @@ yystrlen (yystr)
      const char *yystr;
 #   endif
 {
-  register const char *yys = yystr;
+  const char *yys = yystr;
 
   while (*yys++ != '\0')
     continue;
@@ -668,8 +911,8 @@ yystpcpy (yydest, yysrc)
      const char *yysrc;
 #   endif
 {
-  register char *yyd = yydest;
-  register const char *yys = yysrc;
+  char *yyd = yydest;
+  const char *yys = yysrc;
 
   while ((*yyd++ = *yys++) != '\0')
     continue;
@@ -678,86 +921,187 @@ yystpcpy (yydest, yysrc)
 }
 #  endif
 # endif
-#endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+   quotes and backslashes, so that it's suitable for yyerror.  The
+   heuristic is that double-quoting is unnecessary unless the string
+   contains an apostrophe, a comma, or backslash (other than
+   backslash-backslash).  YYSTR is taken from yytname.  If YYRES is
+   null, do not copy; instead, return the length of what the result
+   would have been.  */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+  if (*yystr == '"')
+    {
+      size_t yyn = 0;
+      char const *yyp = yystr;
+
+      for (;;)
+	switch (*++yyp)
+	  {
+	  case '\'':
+	  case ',':
+	    goto do_not_strip_quotes;
+
+	  case '\\':
+	    if (*++yyp != '\\')
+	      goto do_not_strip_quotes;
+	    /* Fall through.  */
+	  default:
+	    if (yyres)
+	      yyres[yyn] = *yyp;
+	    yyn++;
+	    break;
+
+	  case '"':
+	    if (yyres)
+	      yyres[yyn] = '\0';
+	    return yyn;
+	  }
+    do_not_strip_quotes: ;
+    }
+
+  if (! yyres)
+    return yystrlen (yystr);
+
+  return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+#endif /* YYERROR_VERBOSE */
+
 
-#line 315 "/usr/share/bison-1.35/bison.simple"
+
+#if YYDEBUG
+/*--------------------------------.
+| Print this symbol on YYOUTPUT.  |
+`--------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yysymprint (FILE *yyoutput, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yysymprint (yyoutput, yytype, yyvaluep)
+    FILE *yyoutput;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (yytype < YYNTOKENS)
+    YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+  else
+    YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
 
 
-/* The user can define YYPARSE_PARAM as the name of an argument to be passed
-   into yyparse.  The argument should have type void *.
-   It should actually point to an object.
-   Grammar actions can access the variable by casting it
-   to the proper pointer type.  */
+# ifdef YYPRINT
+  if (yytype < YYNTOKENS)
+    YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# endif
+  switch (yytype)
+    {
+      default:
+        break;
+    }
+  YYFPRINTF (yyoutput, ")");
+}
+
+#endif /* ! YYDEBUG */
+/*-----------------------------------------------.
+| Release the memory associated to this symbol.  |
+`-----------------------------------------------*/
+
+#if defined (__STDC__) || defined (__cplusplus)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+    const char *yymsg;
+    int yytype;
+    YYSTYPE *yyvaluep;
+#endif
+{
+  /* Pacify ``unused variable'' warnings.  */
+  (void) yyvaluep;
+
+  if (!yymsg)
+    yymsg = "Deleting";
+  YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+  switch (yytype)
+    {
+
+      default:
+        break;
+    }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes.  */
 
 #ifdef YYPARSE_PARAM
 # if defined (__STDC__) || defined (__cplusplus)
-#  define YYPARSE_PARAM_ARG void *YYPARSE_PARAM
-#  define YYPARSE_PARAM_DECL
+int yyparse (void *YYPARSE_PARAM);
 # else
-#  define YYPARSE_PARAM_ARG YYPARSE_PARAM
-#  define YYPARSE_PARAM_DECL void *YYPARSE_PARAM;
+int yyparse ();
 # endif
-#else /* !YYPARSE_PARAM */
-# define YYPARSE_PARAM_ARG
-# define YYPARSE_PARAM_DECL
-#endif /* !YYPARSE_PARAM */
-
-/* Prevent warning if -Wstrict-prototypes.  */
-#ifdef __GNUC__
-# ifdef YYPARSE_PARAM
-int yyparse (void *);
-# else
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
 int yyparse (void);
-# endif
+#else
+int yyparse ();
 #endif
+#endif /* ! YYPARSE_PARAM */
 
-/* YY_DECL_VARIABLES -- depending whether we use a pure parser,
-   variables are global, or local to YYPARSE.  */
-
-#define YY_DECL_NON_LSP_VARIABLES			\
-/* The lookahead symbol.  */				\
-int yychar;						\
-							\
-/* The semantic value of the lookahead symbol. */	\
-YYSTYPE yylval;						\
-							\
-/* Number of parse errors so far.  */			\
-int yynerrs;
 
-#if YYLSP_NEEDED
-# define YY_DECL_VARIABLES			\
-YY_DECL_NON_LSP_VARIABLES			\
-						\
-/* Location data for the lookahead symbol.  */	\
-YYLTYPE yylloc;
-#else
-# define YY_DECL_VARIABLES			\
-YY_DECL_NON_LSP_VARIABLES
-#endif
 
+/* The look-ahead symbol.  */
+int yychar;
 
-/* If nonreentrant, generate the variables here. */
+/* The semantic value of the look-ahead symbol.  */
+YYSTYPE yylval;
 
-#if !YYPURE
-YY_DECL_VARIABLES
-#endif  /* !YYPURE */
+/* Number of syntax errors so far.  */
+int yynerrs;
 
+
+
+/*----------.
+| yyparse.  |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+# if defined (__STDC__) || defined (__cplusplus)
+int yyparse (void *YYPARSE_PARAM)
+# else
+int yyparse (YYPARSE_PARAM)
+  void *YYPARSE_PARAM;
+# endif
+#else /* ! YYPARSE_PARAM */
+#if defined (__STDC__) || defined (__cplusplus)
+int
+yyparse (void)
+#else
 int
-yyparse (YYPARSE_PARAM_ARG)
-     YYPARSE_PARAM_DECL
+yyparse ()
+    ;
+#endif
+#endif
 {
-  /* If reentrant, generate the variables here. */
-#if YYPURE
-  YY_DECL_VARIABLES
-#endif  /* !YYPURE */
-
-  register int yystate;
-  register int yyn;
+  
+  int yystate;
+  int yyn;
   int yyresult;
   /* Number of tokens to shift before error messages enabled.  */
   int yyerrstatus;
-  /* Lookahead token as an internal (translated) token number.  */
-  int yychar1 = 0;
+  /* Look-ahead token as an internal (translated) token number.  */
+  int yytoken = 0;
 
   /* Three stacks and their tools:
      `yyss': related to states,
@@ -767,41 +1111,29 @@ yyparse (YYPARSE_PARAM_ARG)
      Refer to the stacks thru separate pointers, to allow yyoverflow
      to reallocate them elsewhere.  */
 
-  /* The state stack. */
-  short	yyssa[YYINITDEPTH];
-  short *yyss = yyssa;
-  register short *yyssp;
+  /* The state stack.  */
+  short int yyssa[YYINITDEPTH];
+  short int *yyss = yyssa;
+  short int *yyssp;
 
   /* The semantic value stack.  */
   YYSTYPE yyvsa[YYINITDEPTH];
   YYSTYPE *yyvs = yyvsa;
-  register YYSTYPE *yyvsp;
+  YYSTYPE *yyvsp;
 
-#if YYLSP_NEEDED
-  /* The location stack.  */
-  YYLTYPE yylsa[YYINITDEPTH];
-  YYLTYPE *yyls = yylsa;
-  YYLTYPE *yylsp;
-#endif
 
-#if YYLSP_NEEDED
-# define YYPOPSTACK   (yyvsp--, yyssp--, yylsp--)
-#else
-# define YYPOPSTACK   (yyvsp--, yyssp--)
-#endif
 
-  YYSIZE_T yystacksize = YYINITDEPTH;
+#define YYPOPSTACK   (yyvsp--, yyssp--)
 
+  YYSIZE_T yystacksize = YYINITDEPTH;
 
   /* The variables used to return semantic value and location from the
      action routines.  */
   YYSTYPE yyval;
-#if YYLSP_NEEDED
-  YYLTYPE yyloc;
-#endif
+
 
   /* When reducing, the number of symbols on the RHS of the reduced
-     rule. */
+     rule.  */
   int yylen;
 
   YYDPRINTF ((stderr, "Starting parse\n"));
@@ -818,9 +1150,7 @@ yyparse (YYPARSE_PARAM_ARG)
 
   yyssp = yyss;
   yyvsp = yyvs;
-#if YYLSP_NEEDED
-  yylsp = yyls;
-#endif
+
   goto yysetstate;
 
 /*------------------------------------------------------------.
@@ -835,7 +1165,7 @@ yyparse (YYPARSE_PARAM_ARG)
  yysetstate:
   *yyssp = yystate;
 
-  if (yyssp >= yyss + yystacksize - 1)
+  if (yyss + yystacksize - 1 <= yyssp)
     {
       /* Get the current used size of the three stacks, in elements.  */
       YYSIZE_T yysize = yyssp - yyss + 1;
@@ -846,52 +1176,43 @@ yyparse (YYPARSE_PARAM_ARG)
 	   these so that the &'s don't force the real ones into
 	   memory.  */
 	YYSTYPE *yyvs1 = yyvs;
-	short *yyss1 = yyss;
+	short int *yyss1 = yyss;
+
 
 	/* Each stack pointer address is followed by the size of the
-	   data in use in that stack, in bytes.  */
-# if YYLSP_NEEDED
-	YYLTYPE *yyls1 = yyls;
-	/* This used to be a conditional around just the two extra args,
-	   but that might be undefined if yyoverflow is a macro.  */
-	yyoverflow ("parser stack overflow",
-		    &yyss1, yysize * sizeof (*yyssp),
-		    &yyvs1, yysize * sizeof (*yyvsp),
-		    &yyls1, yysize * sizeof (*yylsp),
-		    &yystacksize);
-	yyls = yyls1;
-# else
-	yyoverflow ("parser stack overflow",
+	   data in use in that stack, in bytes.  This used to be a
+	   conditional around just the two extra args, but that might
+	   be undefined if yyoverflow is a macro.  */
+	yyoverflow (YY_("memory exhausted"),
 		    &yyss1, yysize * sizeof (*yyssp),
 		    &yyvs1, yysize * sizeof (*yyvsp),
+
 		    &yystacksize);
-# endif
+
 	yyss = yyss1;
 	yyvs = yyvs1;
       }
 #else /* no yyoverflow */
 # ifndef YYSTACK_RELOCATE
-      goto yyoverflowlab;
+      goto yyexhaustedlab;
 # else
       /* Extend the stack our own way.  */
-      if (yystacksize >= YYMAXDEPTH)
-	goto yyoverflowlab;
+      if (YYMAXDEPTH <= yystacksize)
+	goto yyexhaustedlab;
       yystacksize *= 2;
-      if (yystacksize > YYMAXDEPTH)
+      if (YYMAXDEPTH < yystacksize)
 	yystacksize = YYMAXDEPTH;
 
       {
-	short *yyss1 = yyss;
+	short int *yyss1 = yyss;
 	union yyalloc *yyptr =
 	  (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
 	if (! yyptr)
-	  goto yyoverflowlab;
+	  goto yyexhaustedlab;
 	YYSTACK_RELOCATE (yyss);
 	YYSTACK_RELOCATE (yyvs);
-# if YYLSP_NEEDED
-	YYSTACK_RELOCATE (yyls);
-# endif
-# undef YYSTACK_RELOCATE
+
+#  undef YYSTACK_RELOCATE
 	if (yyss1 != yyssa)
 	  YYSTACK_FREE (yyss1);
       }
@@ -900,14 +1221,12 @@ yyparse (YYPARSE_PARAM_ARG)
 
       yyssp = yyss + yysize - 1;
       yyvsp = yyvs + yysize - 1;
-#if YYLSP_NEEDED
-      yylsp = yyls + yysize - 1;
-#endif
+
 
       YYDPRINTF ((stderr, "Stack size increased to %lu\n",
 		  (unsigned long int) yystacksize));
 
-      if (yyssp >= yyss + yystacksize - 1)
+      if (yyss + yystacksize - 1 <= yyssp)
 	YYABORT;
     }
 
@@ -915,101 +1234,67 @@ yyparse (YYPARSE_PARAM_ARG)
 
   goto yybackup;
 
-
 /*-----------.
 | yybackup.  |
 `-----------*/
 yybackup:
 
 /* Do appropriate processing given the current state.  */
-/* Read a lookahead token if we need one and don't already have one.  */
+/* Read a look-ahead token if we need one and don't already have one.  */
 /* yyresume: */
 
-  /* First try to decide what to do without reference to lookahead token.  */
+  /* First try to decide what to do without reference to look-ahead token.  */
 
   yyn = yypact[yystate];
-  if (yyn == YYFLAG)
+  if (yyn == YYPACT_NINF)
     goto yydefault;
 
-  /* Not known => get a lookahead token if don't already have one.  */
-
-  /* yychar is either YYEMPTY or YYEOF
-     or a valid token in external form.  */
+  /* Not known => get a look-ahead token if don't already have one.  */
 
+  /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol.  */
   if (yychar == YYEMPTY)
     {
       YYDPRINTF ((stderr, "Reading a token: "));
       yychar = YYLEX;
     }
 
-  /* Convert token to internal form (in yychar1) for indexing tables with */
-
-  if (yychar <= 0)		/* This means end of input. */
+  if (yychar <= YYEOF)
     {
-      yychar1 = 0;
-      yychar = YYEOF;		/* Don't call YYLEX any more */
-
+      yychar = yytoken = YYEOF;
       YYDPRINTF ((stderr, "Now at end of input.\n"));
     }
   else
     {
-      yychar1 = YYTRANSLATE (yychar);
-
-#if YYDEBUG
-     /* We have to keep this `#if YYDEBUG', since we use variables
-	which are defined only if `YYDEBUG' is set.  */
-      if (yydebug)
-	{
-	  YYFPRINTF (stderr, "Next token is %d (%s",
-		     yychar, yytname[yychar1]);
-	  /* Give the individual parser a way to print the precise
-	     meaning of a token, for further debugging info.  */
-# ifdef YYPRINT
-	  YYPRINT (stderr, yychar, yylval);
-# endif
-	  YYFPRINTF (stderr, ")\n");
-	}
-#endif
+      yytoken = YYTRANSLATE (yychar);
+      YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
     }
 
-  yyn += yychar1;
-  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != yychar1)
+  /* If the proper action on seeing token YYTOKEN is to reduce or to
+     detect an error, take that action.  */
+  yyn += yytoken;
+  if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
     goto yydefault;
-
   yyn = yytable[yyn];
-
-  /* yyn is what to do for this token type in this state.
-     Negative => reduce, -yyn is rule number.
-     Positive => shift, yyn is new state.
-       New state is final state => don't bother to shift,
-       just return success.
-     0, or most negative number => error.  */
-
-  if (yyn < 0)
+  if (yyn <= 0)
     {
-      if (yyn == YYFLAG)
+      if (yyn == 0 || yyn == YYTABLE_NINF)
 	goto yyerrlab;
       yyn = -yyn;
       goto yyreduce;
     }
-  else if (yyn == 0)
-    goto yyerrlab;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
-  /* Shift the lookahead token.  */
-  YYDPRINTF ((stderr, "Shifting token %d (%s), ",
-	      yychar, yytname[yychar1]));
+  /* Shift the look-ahead token.  */
+  YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
 
   /* Discard the token being shifted unless it is eof.  */
   if (yychar != YYEOF)
     yychar = YYEMPTY;
 
   *++yyvsp = yylval;
-#if YYLSP_NEEDED
-  *++yylsp = yylloc;
-#endif
+
 
   /* Count tokens shifted since error; after three, turn off error
      status.  */
@@ -1040,604 +1325,673 @@ yyreduce:
   /* If YYLEN is nonzero, implement the default value of the action:
      `$$ = $1'.
 
-     Otherwise, the following line sets YYVAL to the semantic value of
-     the lookahead token.  This behavior is undocumented and Bison
+     Otherwise, the following line sets YYVAL to garbage.
+     This behavior is undocumented and Bison
      users should not rely upon it.  Assigning to YYVAL
      unconditionally makes the parser a bit smaller, and it avoids a
      GCC warning that YYVAL may be used uninitialized.  */
   yyval = yyvsp[1-yylen];
 
-#if YYLSP_NEEDED
-  /* Similarly for the default location.  Let the user run additional
-     commands if for instance locations are ranges.  */
-  yyloc = yylsp[1-yylen];
-  YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen);
-#endif
 
-#if YYDEBUG
-  /* We have to keep this `#if YYDEBUG', since we use variables which
-     are defined only if `YYDEBUG' is set.  */
-  if (yydebug)
+  YY_REDUCE_PRINT (yyn);
+  switch (yyn)
+    {
+        case 3:
+#line 123 "m68k-parse.y"
     {
-      int yyi;
+		  op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
+		}
+    break;
 
-      YYFPRINTF (stderr, "Reducing via rule %d (line %d), ",
-		 yyn, yyrline[yyn]);
+  case 4:
+#line 127 "m68k-parse.y"
+    {
+		  op->trailing_ampersand = (yyvsp[0].trailing_ampersand);
+		}
+    break;
 
-      /* Print the symbols being reduced, and their result.  */
-      for (yyi = yyprhs[yyn]; yyrhs[yyi] > 0; yyi++)
-	YYFPRINTF (stderr, "%s ", yytname[yyrhs[yyi]]);
-      YYFPRINTF (stderr, " -> %s\n", yytname[yyr1[yyn]]);
-    }
-#endif
+  case 5:
+#line 135 "m68k-parse.y"
+    { (yyval.trailing_ampersand) = 0; }
+    break;
 
-  switch (yyn) {
+  case 6:
+#line 137 "m68k-parse.y"
+    { (yyval.trailing_ampersand) = 1; }
+    break;
 
-case 4:
-#line 127 "m68k-parse.y"
-{
+  case 7:
+#line 144 "m68k-parse.y"
+    {
+		  op->mode = LSH;
+		}
+    break;
+
+  case 8:
+#line 149 "m68k-parse.y"
+    {
+		  op->mode = RSH;
+		}
+    break;
+
+  case 9:
+#line 154 "m68k-parse.y"
+    {
 		  op->mode = DREG;
-		  op->reg = yyvsp[0].reg;
+		  op->reg = (yyvsp[0].reg);
 		}
     break;
-case 5:
-#line 132 "m68k-parse.y"
-{
+
+  case 10:
+#line 159 "m68k-parse.y"
+    {
 		  op->mode = AREG;
-		  op->reg = yyvsp[0].reg;
+		  op->reg = (yyvsp[0].reg);
 		}
     break;
-case 6:
-#line 137 "m68k-parse.y"
-{
+
+  case 11:
+#line 164 "m68k-parse.y"
+    {
 		  op->mode = FPREG;
-		  op->reg = yyvsp[0].reg;
+		  op->reg = (yyvsp[0].reg);
 		}
     break;
-case 7:
-#line 142 "m68k-parse.y"
-{
+
+  case 12:
+#line 169 "m68k-parse.y"
+    {
 		  op->mode = CONTROL;
-		  op->reg = yyvsp[0].reg;
+		  op->reg = (yyvsp[0].reg);
 		}
     break;
-case 8:
-#line 147 "m68k-parse.y"
-{
+
+  case 13:
+#line 174 "m68k-parse.y"
+    {
 		  op->mode = CONTROL;
-		  op->reg = yyvsp[0].reg;
+		  op->reg = (yyvsp[0].reg);
 		}
     break;
-case 9:
-#line 152 "m68k-parse.y"
-{
+
+  case 14:
+#line 179 "m68k-parse.y"
+    {
 		  op->mode = ABSL;
-		  op->disp = yyvsp[0].exp;
+		  op->disp = (yyvsp[0].exp);
 		}
     break;
-case 10:
-#line 157 "m68k-parse.y"
-{
+
+  case 15:
+#line 184 "m68k-parse.y"
+    {
 		  op->mode = IMMED;
-		  op->disp = yyvsp[0].exp;
+		  op->disp = (yyvsp[0].exp);
 		}
     break;
-case 11:
-#line 162 "m68k-parse.y"
-{
+
+  case 16:
+#line 189 "m68k-parse.y"
+    {
 		  op->mode = IMMED;
-		  op->disp = yyvsp[0].exp;
+		  op->disp = (yyvsp[0].exp);
 		}
     break;
-case 12:
-#line 167 "m68k-parse.y"
-{
+
+  case 17:
+#line 194 "m68k-parse.y"
+    {
 		  op->mode = REGLST;
-		  op->mask = yyvsp[0].mask;
+		  op->mask = (yyvsp[0].mask);
 		}
     break;
-case 13:
-#line 180 "m68k-parse.y"
-{
+
+  case 18:
+#line 207 "m68k-parse.y"
+    {
 		  op->mode = AINDR;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 14:
-#line 185 "m68k-parse.y"
-{
+
+  case 19:
+#line 212 "m68k-parse.y"
+    {
 		  op->mode = AINC;
-		  op->reg = yyvsp[-2].reg;
+		  op->reg = (yyvsp[-2].reg);
 		}
     break;
-case 15:
-#line 190 "m68k-parse.y"
-{
+
+  case 20:
+#line 217 "m68k-parse.y"
+    {
 		  op->mode = ADEC;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 16:
-#line 195 "m68k-parse.y"
-{
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-3].exp;
-		  if ((yyvsp[-1].reg >= ZADDR0 && yyvsp[-1].reg <= ZADDR7)
-		      || yyvsp[-1].reg == ZPC)
+
+  case 21:
+#line 222 "m68k-parse.y"
+    {
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-3].exp);
+		  if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
+		      || (yyvsp[-1].reg) == ZPC)
 		    op->mode = BASE;
 		  else
 		    op->mode = DISP;
 		}
     break;
-case 17:
-#line 205 "m68k-parse.y"
-{
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-1].exp;
-		  if ((yyvsp[-3].reg >= ZADDR0 && yyvsp[-3].reg <= ZADDR7)
-		      || yyvsp[-3].reg == ZPC)
+
+  case 22:
+#line 232 "m68k-parse.y"
+    {
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-1].exp);
+		  if (((yyvsp[-3].reg) >= ZADDR0 && (yyvsp[-3].reg) <= ZADDR7)
+		      || (yyvsp[-3].reg) == ZPC)
 		    op->mode = BASE;
 		  else
 		    op->mode = DISP;
 		}
     break;
-case 18:
-#line 215 "m68k-parse.y"
-{
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-3].exp;
-		  if ((yyvsp[-1].reg >= ZADDR0 && yyvsp[-1].reg <= ZADDR7)
-		      || yyvsp[-1].reg == ZPC)
+
+  case 23:
+#line 242 "m68k-parse.y"
+    {
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-3].exp);
+		  if (((yyvsp[-1].reg) >= ZADDR0 && (yyvsp[-1].reg) <= ZADDR7)
+		      || (yyvsp[-1].reg) == ZPC)
 		    op->mode = BASE;
 		  else
 		    op->mode = DISP;
 		}
     break;
-case 19:
-#line 225 "m68k-parse.y"
-{
+
+  case 24:
+#line 252 "m68k-parse.y"
+    {
 		  op->mode = DISP;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 20:
-#line 230 "m68k-parse.y"
-{
+
+  case 25:
+#line 257 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 21:
-#line 235 "m68k-parse.y"
-{
+
+  case 26:
+#line 262 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 22:
-#line 240 "m68k-parse.y"
-{
+
+  case 27:
+#line 267 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->index = yyvsp[-1].indexreg;
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->index = (yyvsp[-1].indexreg);
 		}
     break;
-case 23:
-#line 247 "m68k-parse.y"
-{
-		  if (yyvsp[-3].reg == PC || yyvsp[-3].reg == ZPC)
+
+  case 28:
+#line 274 "m68k-parse.y"
+    {
+		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
 		    yyerror (_("syntax error"));
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->index.reg = yyvsp[-3].reg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->index.reg = (yyvsp[-3].reg);
 		  op->index.size = SIZE_UNSPEC;
 		  op->index.scale = 1;
 		}
     break;
-case 24:
-#line 258 "m68k-parse.y"
-{
+
+  case 29:
+#line 285 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-4].exp;
-		  op->index = yyvsp[-2].indexreg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-4].exp);
+		  op->index = (yyvsp[-2].indexreg);
 		}
     break;
-case 25:
-#line 265 "m68k-parse.y"
-{
+
+  case 30:
+#line 292 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->disp = yyvsp[-1].exp;
-		  op->index = yyvsp[-3].indexreg;
+		  op->disp = (yyvsp[-1].exp);
+		  op->index = (yyvsp[-3].indexreg);
 		}
     break;
-case 26:
-#line 271 "m68k-parse.y"
-{
+
+  case 31:
+#line 298 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->index = yyvsp[-1].indexreg;
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->index = (yyvsp[-1].indexreg);
 		}
     break;
-case 27:
-#line 278 "m68k-parse.y"
-{
+
+  case 32:
+#line 305 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-3].reg;
-		  op->index = yyvsp[-1].indexreg;
+		  op->reg = (yyvsp[-3].reg);
+		  op->index = (yyvsp[-1].indexreg);
 		}
     break;
-case 28:
-#line 284 "m68k-parse.y"
-{
-		  if (yyvsp[-3].reg == PC || yyvsp[-3].reg == ZPC)
+
+  case 33:
+#line 311 "m68k-parse.y"
+    {
+		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
 		    yyerror (_("syntax error"));
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->index.reg = yyvsp[-3].reg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->index.reg = (yyvsp[-3].reg);
 		  op->index.size = SIZE_UNSPEC;
 		  op->index.scale = 1;
 		}
     break;
-case 29:
-#line 295 "m68k-parse.y"
-{
-		  if (yyvsp[-3].reg == PC || yyvsp[-3].reg == ZPC)
+
+  case 34:
+#line 322 "m68k-parse.y"
+    {
+		  if ((yyvsp[-3].reg) == PC || (yyvsp[-3].reg) == ZPC)
 		    yyerror (_("syntax error"));
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->index.reg = yyvsp[-3].reg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->index.reg = (yyvsp[-3].reg);
 		  op->index.size = SIZE_UNSPEC;
 		  op->index.scale = 1;
 		}
     break;
-case 30:
-#line 305 "m68k-parse.y"
-{
+
+  case 35:
+#line 332 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->disp = yyvsp[-4].exp;
-		  op->index = yyvsp[-2].indexreg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->disp = (yyvsp[-4].exp);
+		  op->index = (yyvsp[-2].indexreg);
 		}
     break;
-case 31:
-#line 312 "m68k-parse.y"
-{
+
+  case 36:
+#line 339 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-1].reg;
-		  op->index = yyvsp[-2].indexreg;
+		  op->reg = (yyvsp[-1].reg);
+		  op->index = (yyvsp[-2].indexreg);
 		}
     break;
-case 32:
-#line 318 "m68k-parse.y"
-{
+
+  case 37:
+#line 345 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-5].reg;
-		  op->disp = yyvsp[-6].exp;
-		  op->index = yyvsp[-2].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-5].reg);
+		  op->disp = (yyvsp[-6].exp);
+		  op->index = (yyvsp[-2].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 33:
-#line 326 "m68k-parse.y"
-{
+
+  case 38:
+#line 353 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-4].exp;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-4].exp);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 34:
-#line 333 "m68k-parse.y"
-{
+
+  case 39:
+#line 360 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-5].reg;
-		  op->index = yyvsp[-2].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-5].reg);
+		  op->index = (yyvsp[-2].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 35:
-#line 340 "m68k-parse.y"
-{
+
+  case 40:
+#line 367 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-3].reg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-3].reg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 36:
-#line 346 "m68k-parse.y"
-{
+
+  case 41:
+#line 373 "m68k-parse.y"
+    {
 		  op->mode = PRE;
-		  op->reg = yyvsp[-5].reg;
-		  op->disp = yyvsp[-7].exp;
-		  op->index = yyvsp[-3].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-5].reg);
+		  op->disp = (yyvsp[-7].exp);
+		  op->index = (yyvsp[-3].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 37:
-#line 354 "m68k-parse.y"
-{
+
+  case 42:
+#line 381 "m68k-parse.y"
+    {
 		  op->mode = PRE;
-		  op->reg = yyvsp[-5].reg;
-		  op->index = yyvsp[-3].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-5].reg);
+		  op->index = (yyvsp[-3].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 38:
-#line 361 "m68k-parse.y"
-{
-		  if (yyvsp[-5].reg == PC || yyvsp[-5].reg == ZPC)
+
+  case 43:
+#line 388 "m68k-parse.y"
+    {
+		  if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
 		    yyerror (_("syntax error"));
 		  op->mode = PRE;
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-7].exp;
-		  op->index.reg = yyvsp[-5].reg;
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-7].exp);
+		  op->index.reg = (yyvsp[-5].reg);
 		  op->index.size = SIZE_UNSPEC;
 		  op->index.scale = 1;
-		  op->odisp = yyvsp[-1].exp;
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 39:
-#line 373 "m68k-parse.y"
-{
-		  if (yyvsp[-5].reg == PC || yyvsp[-5].reg == ZPC)
+
+  case 44:
+#line 400 "m68k-parse.y"
+    {
+		  if ((yyvsp[-5].reg) == PC || (yyvsp[-5].reg) == ZPC)
 		    yyerror (_("syntax error"));
 		  op->mode = PRE;
-		  op->reg = yyvsp[-3].reg;
-		  op->index.reg = yyvsp[-5].reg;
+		  op->reg = (yyvsp[-3].reg);
+		  op->index.reg = (yyvsp[-5].reg);
 		  op->index.size = SIZE_UNSPEC;
 		  op->index.scale = 1;
-		  op->odisp = yyvsp[-1].exp;
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 40:
-#line 384 "m68k-parse.y"
-{
+
+  case 45:
+#line 411 "m68k-parse.y"
+    {
 		  op->mode = PRE;
-		  op->reg = yyvsp[-3].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->index = yyvsp[-4].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-3].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->index = (yyvsp[-4].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 41:
-#line 397 "m68k-parse.y"
-{
+
+  case 46:
+#line 424 "m68k-parse.y"
+    {
 		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if (yyvsp[-1].reg < ADDR0 || yyvsp[-1].reg > ADDR7)
+		  if ((yyvsp[-1].reg) < ADDR0 || (yyvsp[-1].reg) > ADDR7)
 		    yyerror (_("syntax error"));
 		  op->mode = AINDR;
-		  op->reg = yyvsp[-1].reg;
+		  op->reg = (yyvsp[-1].reg);
 		}
     break;
-case 42:
-#line 405 "m68k-parse.y"
-{
+
+  case 47:
+#line 432 "m68k-parse.y"
+    {
 		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if (yyvsp[-2].reg < ADDR0 || yyvsp[-2].reg > ADDR7)
+		  if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
 		    yyerror (_("syntax error"));
 		  op->mode = AINC;
-		  op->reg = yyvsp[-2].reg;
+		  op->reg = (yyvsp[-2].reg);
 		}
     break;
-case 43:
-#line 413 "m68k-parse.y"
-{
+
+  case 48:
+#line 440 "m68k-parse.y"
+    {
 		  /* We use optzapc to avoid a shift/reduce conflict.  */
-		  if (yyvsp[-2].reg < ADDR0 || yyvsp[-2].reg > ADDR7)
+		  if ((yyvsp[-2].reg) < ADDR0 || (yyvsp[-2].reg) > ADDR7)
 		    yyerror (_("syntax error"));
 		  op->mode = ADEC;
-		  op->reg = yyvsp[-2].reg;
+		  op->reg = (yyvsp[-2].reg);
 		}
     break;
-case 44:
-#line 421 "m68k-parse.y"
-{
-		  op->reg = yyvsp[-4].reg;
-		  op->disp = yyvsp[-1].exp;
-		  if ((yyvsp[-4].reg >= ZADDR0 && yyvsp[-4].reg <= ZADDR7)
-		      || yyvsp[-4].reg == ZPC)
+
+  case 49:
+#line 448 "m68k-parse.y"
+    {
+		  op->reg = (yyvsp[-4].reg);
+		  op->disp = (yyvsp[-1].exp);
+		  if (((yyvsp[-4].reg) >= ZADDR0 && (yyvsp[-4].reg) <= ZADDR7)
+		      || (yyvsp[-4].reg) == ZPC)
 		    op->mode = BASE;
 		  else
 		    op->mode = DISP;
 		}
     break;
-case 45:
-#line 431 "m68k-parse.y"
-{
+
+  case 50:
+#line 458 "m68k-parse.y"
+    {
 		  op->mode = BASE;
-		  op->reg = yyvsp[-5].reg;
-		  op->disp = yyvsp[-2].exp;
-		  op->index = yyvsp[-1].indexreg;
+		  op->reg = (yyvsp[-5].reg);
+		  op->disp = (yyvsp[-2].exp);
+		  op->index = (yyvsp[-1].indexreg);
 		}
     break;
-case 46:
-#line 438 "m68k-parse.y"
-{
+
+  case 51:
+#line 465 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-9].reg;
-		  op->disp = yyvsp[-6].exp;
-		  op->index = yyvsp[-1].indexreg;
-		  op->odisp = yyvsp[-2].exp;
+		  op->reg = (yyvsp[-9].reg);
+		  op->disp = (yyvsp[-6].exp);
+		  op->index = (yyvsp[-1].indexreg);
+		  op->odisp = (yyvsp[-2].exp);
 		}
     break;
-case 47:
-#line 446 "m68k-parse.y"
-{
+
+  case 52:
+#line 473 "m68k-parse.y"
+    {
 		  op->mode = POST;
-		  op->reg = yyvsp[-8].reg;
-		  op->disp = yyvsp[-5].exp;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-8].reg);
+		  op->disp = (yyvsp[-5].exp);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 48:
-#line 453 "m68k-parse.y"
-{
+
+  case 53:
+#line 480 "m68k-parse.y"
+    {
 		  op->mode = PRE;
-		  op->reg = yyvsp[-9].reg;
-		  op->disp = yyvsp[-6].exp;
-		  op->index = yyvsp[-5].indexreg;
-		  op->odisp = yyvsp[-1].exp;
+		  op->reg = (yyvsp[-9].reg);
+		  op->disp = (yyvsp[-6].exp);
+		  op->index = (yyvsp[-5].indexreg);
+		  op->odisp = (yyvsp[-1].exp);
 		}
     break;
-case 50:
-#line 468 "m68k-parse.y"
-{
-		  yyval.indexreg.reg = yyvsp[0].reg;
-		  yyval.indexreg.size = SIZE_UNSPEC;
-		  yyval.indexreg.scale = 1;
+
+  case 55:
+#line 495 "m68k-parse.y"
+    {
+		  (yyval.indexreg).reg = (yyvsp[0].reg);
+		  (yyval.indexreg).size = SIZE_UNSPEC;
+		  (yyval.indexreg).scale = 1;
 		}
     break;
-case 52:
-#line 482 "m68k-parse.y"
-{
-		  yyval.indexreg.reg = yyvsp[0].reg;
-		  yyval.indexreg.size = SIZE_UNSPEC;
-		  yyval.indexreg.scale = 1;
+
+  case 57:
+#line 509 "m68k-parse.y"
+    {
+		  (yyval.indexreg).reg = (yyvsp[0].reg);
+		  (yyval.indexreg).size = SIZE_UNSPEC;
+		  (yyval.indexreg).scale = 1;
 		}
     break;
-case 63:
-#line 525 "m68k-parse.y"
-{
-		  yyval.reg = ZADDR0;
+
+  case 68:
+#line 552 "m68k-parse.y"
+    {
+		  (yyval.reg) = ZADDR0;
 		}
     break;
-case 67:
-#line 542 "m68k-parse.y"
-{
-		  yyval.reg = ZADDR0;
+
+  case 72:
+#line 569 "m68k-parse.y"
+    {
+		  (yyval.reg) = ZADDR0;
 		}
     break;
-case 68:
-#line 546 "m68k-parse.y"
-{
-		  yyval.reg = yyvsp[0].reg;
+
+  case 73:
+#line 573 "m68k-parse.y"
+    {
+		  (yyval.reg) = (yyvsp[0].reg);
 		}
     break;
-case 69:
-#line 555 "m68k-parse.y"
-{
-		  yyval.exp.exp.X_op = O_absent;
-		  yyval.exp.size = SIZE_UNSPEC;
+
+  case 74:
+#line 582 "m68k-parse.y"
+    {
+		  (yyval.exp).exp.X_op = O_absent;
+		  (yyval.exp).size = SIZE_UNSPEC;
 		}
     break;
-case 70:
-#line 560 "m68k-parse.y"
-{
-		  yyval.exp = yyvsp[0].exp;
+
+  case 75:
+#line 587 "m68k-parse.y"
+    {
+		  (yyval.exp) = (yyvsp[0].exp);
 		}
     break;
-case 71:
-#line 569 "m68k-parse.y"
-{
-		  yyval.exp.exp.X_op = O_absent;
-		  yyval.exp.size = SIZE_UNSPEC;
+
+  case 76:
+#line 596 "m68k-parse.y"
+    {
+		  (yyval.exp).exp.X_op = O_absent;
+		  (yyval.exp).size = SIZE_UNSPEC;
 		}
     break;
-case 72:
-#line 574 "m68k-parse.y"
-{
-		  yyval.exp = yyvsp[-1].exp;
+
+  case 77:
+#line 601 "m68k-parse.y"
+    {
+		  (yyval.exp) = (yyvsp[-1].exp);
 		}
     break;
-case 74:
-#line 584 "m68k-parse.y"
-{
-		  yyval.mask = yyvsp[-2].mask | yyvsp[0].mask;
+
+  case 79:
+#line 611 "m68k-parse.y"
+    {
+		  (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
 		}
     break;
-case 75:
-#line 588 "m68k-parse.y"
-{
-		  yyval.mask = (1 << yyvsp[-2].onereg) | yyvsp[0].mask;
+
+  case 80:
+#line 615 "m68k-parse.y"
+    {
+		  (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
 		}
     break;
-case 76:
-#line 600 "m68k-parse.y"
-{
-		  yyval.mask = 1 << yyvsp[0].onereg;
+
+  case 81:
+#line 627 "m68k-parse.y"
+    {
+		  (yyval.mask) = 1 << (yyvsp[0].onereg);
 		}
     break;
-case 78:
-#line 605 "m68k-parse.y"
-{
-		  yyval.mask = yyvsp[-2].mask | yyvsp[0].mask;
+
+  case 83:
+#line 632 "m68k-parse.y"
+    {
+		  (yyval.mask) = (yyvsp[-2].mask) | (yyvsp[0].mask);
 		}
     break;
-case 79:
-#line 609 "m68k-parse.y"
-{
-		  yyval.mask = (1 << yyvsp[-2].onereg) | yyvsp[0].mask;
+
+  case 84:
+#line 636 "m68k-parse.y"
+    {
+		  (yyval.mask) = (1 << (yyvsp[-2].onereg)) | (yyvsp[0].mask);
 		}
     break;
-case 80:
-#line 616 "m68k-parse.y"
-{
-		  if (yyvsp[-2].onereg <= yyvsp[0].onereg)
-		    yyval.mask = (1 << (yyvsp[0].onereg + 1)) - 1 - ((1 << yyvsp[-2].onereg) - 1);
+
+  case 85:
+#line 643 "m68k-parse.y"
+    {
+		  if ((yyvsp[-2].onereg) <= (yyvsp[0].onereg))
+		    (yyval.mask) = (1 << ((yyvsp[0].onereg) + 1)) - 1 - ((1 << (yyvsp[-2].onereg)) - 1);
 		  else
-		    yyval.mask = (1 << (yyvsp[-2].onereg + 1)) - 1 - ((1 << yyvsp[0].onereg) - 1);
+		    (yyval.mask) = (1 << ((yyvsp[-2].onereg) + 1)) - 1 - ((1 << (yyvsp[0].onereg)) - 1);
 		}
     break;
-case 81:
-#line 626 "m68k-parse.y"
-{
-		  yyval.onereg = yyvsp[0].reg - DATA0;
+
+  case 86:
+#line 653 "m68k-parse.y"
+    {
+		  (yyval.onereg) = (yyvsp[0].reg) - DATA0;
 		}
     break;
-case 82:
-#line 630 "m68k-parse.y"
-{
-		  yyval.onereg = yyvsp[0].reg - ADDR0 + 8;
+
+  case 87:
+#line 657 "m68k-parse.y"
+    {
+		  (yyval.onereg) = (yyvsp[0].reg) - ADDR0 + 8;
 		}
     break;
-case 83:
-#line 634 "m68k-parse.y"
-{
-		  yyval.onereg = yyvsp[0].reg - FP0 + 16;
+
+  case 88:
+#line 661 "m68k-parse.y"
+    {
+		  (yyval.onereg) = (yyvsp[0].reg) - FP0 + 16;
 		}
     break;
-case 84:
-#line 638 "m68k-parse.y"
-{
-		  if (yyvsp[0].reg == FPI)
-		    yyval.onereg = 24;
-		  else if (yyvsp[0].reg == FPS)
-		    yyval.onereg = 25;
+
+  case 89:
+#line 665 "m68k-parse.y"
+    {
+		  if ((yyvsp[0].reg) == FPI)
+		    (yyval.onereg) = 24;
+		  else if ((yyvsp[0].reg) == FPS)
+		    (yyval.onereg) = 25;
 		  else
-		    yyval.onereg = 26;
+		    (yyval.onereg) = 26;
 		}
     break;
-}
 
-#line 705 "/usr/share/bison-1.35/bison.simple"
 
+      default: break;
+    }
+
+/* Line 1126 of yacc.c.  */
+#line 1986 "m68k-parse.c"
 
   yyvsp -= yylen;
   yyssp -= yylen;
-#if YYLSP_NEEDED
-  yylsp -= yylen;
-#endif
 
-#if YYDEBUG
-  if (yydebug)
-    {
-      short *yyssp1 = yyss - 1;
-      YYFPRINTF (stderr, "state stack now");
-      while (yyssp1 != yyssp)
-	YYFPRINTF (stderr, " %d", *++yyssp1);
-      YYFPRINTF (stderr, "\n");
-    }
-#endif
+
+  YY_STACK_PRINT (yyss, yyssp);
 
   *++yyvsp = yyval;
-#if YYLSP_NEEDED
-  *++yylsp = yyloc;
-#endif
+
 
   /* Now `shift' the result of the reduction.  Determine what state
      that goes to, based on the state we popped back to and the rule
@@ -1645,11 +1999,11 @@ case 84:
 
   yyn = yyr1[yyn];
 
-  yystate = yypgoto[yyn - YYNTBASE] + *yyssp;
-  if (yystate >= 0 && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+  yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+  if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
     yystate = yytable[yystate];
   else
-    yystate = yydefgoto[yyn - YYNTBASE];
+    yystate = yydefgoto[yyn - YYNTOKENS];
 
   goto yynewstate;
 
@@ -1662,155 +2016,193 @@ yyerrlab:
   if (!yyerrstatus)
     {
       ++yynerrs;
-
-#ifdef YYERROR_VERBOSE
+#if YYERROR_VERBOSE
       yyn = yypact[yystate];
 
-      if (yyn > YYFLAG && yyn < YYLAST)
+      if (YYPACT_NINF < yyn && yyn < YYLAST)
 	{
-	  YYSIZE_T yysize = 0;
-	  char *yymsg;
-	  int yyx, yycount;
+	  int yytype = YYTRANSLATE (yychar);
+	  YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+	  YYSIZE_T yysize = yysize0;
+	  YYSIZE_T yysize1;
+	  int yysize_overflow = 0;
+	  char *yymsg = 0;
+#	  define YYERROR_VERBOSE_ARGS_MAXIMUM 5
+	  char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+	  int yyx;
+
+#if 0
+	  /* This is so xgettext sees the translatable formats that are
+	     constructed on the fly.  */
+	  YY_("syntax error, unexpected %s");
+	  YY_("syntax error, unexpected %s, expecting %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+	  YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+#endif
+	  char *yyfmt;
+	  char const *yyf;
+	  static char const yyunexpected[] = "syntax error, unexpected %s";
+	  static char const yyexpecting[] = ", expecting %s";
+	  static char const yyor[] = " or %s";
+	  char yyformat[sizeof yyunexpected
+			+ sizeof yyexpecting - 1
+			+ ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+			   * (sizeof yyor - 1))];
+	  char const *yyprefix = yyexpecting;
 
-	  yycount = 0;
 	  /* Start YYX at -YYN if negative to avoid negative indexes in
 	     YYCHECK.  */
-	  for (yyx = yyn < 0 ? -yyn : 0;
-	       yyx < (int) (sizeof (yytname) / sizeof (char *)); yyx++)
-	    if (yycheck[yyx + yyn] == yyx)
-	      yysize += yystrlen (yytname[yyx]) + 15, yycount++;
-	  yysize += yystrlen ("parse error, unexpected ") + 1;
-	  yysize += yystrlen (yytname[YYTRANSLATE (yychar)]);
-	  yymsg = (char *) YYSTACK_ALLOC (yysize);
-	  if (yymsg != 0)
+	  int yyxbegin = yyn < 0 ? -yyn : 0;
+
+	  /* Stay within bounds of both yycheck and yytname.  */
+	  int yychecklim = YYLAST - yyn;
+	  int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+	  int yycount = 1;
+
+	  yyarg[0] = yytname[yytype];
+	  yyfmt = yystpcpy (yyformat, yyunexpected);
+
+	  for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+	    if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+	      {
+		if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+		  {
+		    yycount = 1;
+		    yysize = yysize0;
+		    yyformat[sizeof yyunexpected - 1] = '\0';
+		    break;
+		  }
+		yyarg[yycount++] = yytname[yyx];
+		yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+		yysize_overflow |= yysize1 < yysize;
+		yysize = yysize1;
+		yyfmt = yystpcpy (yyfmt, yyprefix);
+		yyprefix = yyor;
+	      }
+
+	  yyf = YY_(yyformat);
+	  yysize1 = yysize + yystrlen (yyf);
+	  yysize_overflow |= yysize1 < yysize;
+	  yysize = yysize1;
+
+	  if (!yysize_overflow && yysize <= YYSTACK_ALLOC_MAXIMUM)
+	    yymsg = (char *) YYSTACK_ALLOC (yysize);
+	  if (yymsg)
 	    {
-	      char *yyp = yystpcpy (yymsg, "parse error, unexpected ");
-	      yyp = yystpcpy (yyp, yytname[YYTRANSLATE (yychar)]);
-
-	      if (yycount < 5)
+	      /* Avoid sprintf, as that infringes on the user's name space.
+		 Don't have undefined behavior even if the translation
+		 produced a string with the wrong number of "%s"s.  */
+	      char *yyp = yymsg;
+	      int yyi = 0;
+	      while ((*yyp = *yyf))
 		{
-		  yycount = 0;
-		  for (yyx = yyn < 0 ? -yyn : 0;
-		       yyx < (int) (sizeof (yytname) / sizeof (char *));
-		       yyx++)
-		    if (yycheck[yyx + yyn] == yyx)
-		      {
-			const char *yyq = ! yycount ? ", expecting " : " or ";
-			yyp = yystpcpy (yyp, yyq);
-			yyp = yystpcpy (yyp, yytname[yyx]);
-			yycount++;
-		      }
+		  if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+		    {
+		      yyp += yytnamerr (yyp, yyarg[yyi++]);
+		      yyf += 2;
+		    }
+		  else
+		    {
+		      yyp++;
+		      yyf++;
+		    }
 		}
 	      yyerror (yymsg);
 	      YYSTACK_FREE (yymsg);
 	    }
 	  else
-	    yyerror ("parse error; also virtual memory exhausted");
+	    {
+	      yyerror (YY_("syntax error"));
+	      goto yyexhaustedlab;
+	    }
 	}
       else
-#endif /* defined (YYERROR_VERBOSE) */
-	yyerror ("parse error");
+#endif /* YYERROR_VERBOSE */
+	yyerror (YY_("syntax error"));
     }
-  goto yyerrlab1;
 
 
-/*--------------------------------------------------.
-| yyerrlab1 -- error raised explicitly by an action |
-`--------------------------------------------------*/
-yyerrlab1:
+
   if (yyerrstatus == 3)
     {
-      /* If just tried and failed to reuse lookahead token after an
+      /* If just tried and failed to reuse look-ahead token after an
 	 error, discard it.  */
 
-      /* return failure if at end of input */
-      if (yychar == YYEOF)
-	YYABORT;
-      YYDPRINTF ((stderr, "Discarding token %d (%s).\n",
-		  yychar, yytname[yychar1]));
-      yychar = YYEMPTY;
+      if (yychar <= YYEOF)
+        {
+	  /* Return failure if at end of input.  */
+	  if (yychar == YYEOF)
+	    YYABORT;
+        }
+      else
+	{
+	  yydestruct ("Error: discarding", yytoken, &yylval);
+	  yychar = YYEMPTY;
+	}
     }
 
-  /* Else will try to reuse lookahead token after shifting the error
+  /* Else will try to reuse look-ahead token after shifting the error
      token.  */
+  goto yyerrlab1;
 
-  yyerrstatus = 3;		/* Each real token shifted decrements this */
 
-  goto yyerrhandle;
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR.  |
+`---------------------------------------------------*/
+yyerrorlab:
 
+  /* Pacify compilers like GCC when the user code never invokes
+     YYERROR and the label yyerrorlab therefore never appears in user
+     code.  */
+  if (0)
+     goto yyerrorlab;
 
-/*-------------------------------------------------------------------.
-| yyerrdefault -- current state does not do anything special for the |
-| error token.                                                       |
-`-------------------------------------------------------------------*/
-yyerrdefault:
-#if 0
-  /* This is wrong; only states that explicitly want error tokens
-     should shift them.  */
-
-  /* If its default is to accept any token, ok.  Otherwise pop it.  */
-  yyn = yydefact[yystate];
-  if (yyn)
-    goto yydefault;
-#endif
+yyvsp -= yylen;
+  yyssp -= yylen;
+  yystate = *yyssp;
+  goto yyerrlab1;
 
 
-/*---------------------------------------------------------------.
-| yyerrpop -- pop the current state because it cannot handle the |
-| error token                                                    |
-`---------------------------------------------------------------*/
-yyerrpop:
-  if (yyssp == yyss)
-    YYABORT;
-  yyvsp--;
-  yystate = *--yyssp;
-#if YYLSP_NEEDED
-  yylsp--;
-#endif
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR.  |
+`-------------------------------------------------------------*/
+yyerrlab1:
+  yyerrstatus = 3;	/* Each real token shifted decrements this.  */
 
-#if YYDEBUG
-  if (yydebug)
+  for (;;)
     {
-      short *yyssp1 = yyss - 1;
-      YYFPRINTF (stderr, "Error: state stack now");
-      while (yyssp1 != yyssp)
-	YYFPRINTF (stderr, " %d", *++yyssp1);
-      YYFPRINTF (stderr, "\n");
-    }
-#endif
+      yyn = yypact[yystate];
+      if (yyn != YYPACT_NINF)
+	{
+	  yyn += YYTERROR;
+	  if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+	    {
+	      yyn = yytable[yyn];
+	      if (0 < yyn)
+		break;
+	    }
+	}
 
-/*--------------.
-| yyerrhandle.  |
-`--------------*/
-yyerrhandle:
-  yyn = yypact[yystate];
-  if (yyn == YYFLAG)
-    goto yyerrdefault;
+      /* Pop the current state because it cannot handle the error token.  */
+      if (yyssp == yyss)
+	YYABORT;
 
-  yyn += YYTERROR;
-  if (yyn < 0 || yyn > YYLAST || yycheck[yyn] != YYTERROR)
-    goto yyerrdefault;
 
-  yyn = yytable[yyn];
-  if (yyn < 0)
-    {
-      if (yyn == YYFLAG)
-	goto yyerrpop;
-      yyn = -yyn;
-      goto yyreduce;
+      yydestruct ("Error: popping", yystos[yystate], yyvsp);
+      YYPOPSTACK;
+      yystate = *yyssp;
+      YY_STACK_PRINT (yyss, yyssp);
     }
-  else if (yyn == 0)
-    goto yyerrpop;
 
   if (yyn == YYFINAL)
     YYACCEPT;
 
-  YYDPRINTF ((stderr, "Shifting error token, "));
-
   *++yyvsp = yylval;
-#if YYLSP_NEEDED
-  *++yylsp = yylloc;
-#endif
+
+
+  /* Shift the error token. */
+  YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
 
   yystate = yyn;
   goto yynewstate;
@@ -1830,22 +2222,35 @@ yyabortlab:
   yyresult = 1;
   goto yyreturn;
 
-/*---------------------------------------------.
-| yyoverflowab -- parser overflow comes here.  |
-`---------------------------------------------*/
-yyoverflowlab:
-  yyerror ("parser stack overflow");
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here.  |
+`-------------------------------------------------*/
+yyexhaustedlab:
+  yyerror (YY_("memory exhausted"));
   yyresult = 2;
   /* Fall through.  */
+#endif
 
 yyreturn:
+  if (yychar != YYEOF && yychar != YYEMPTY)
+     yydestruct ("Cleanup: discarding lookahead",
+		 yytoken, &yylval);
+  while (yyssp != yyss)
+    {
+      yydestruct ("Cleanup: popping",
+		  yystos[*yyssp], yyvsp);
+      YYPOPSTACK;
+    }
 #ifndef yyoverflow
   if (yyss != yyssa)
     YYSTACK_FREE (yyss);
 #endif
   return yyresult;
 }
-#line 648 "m68k-parse.y"
+
+
+#line 675 "m68k-parse.y"
 
 
 /* The string to parse is stored here, and modified by yylex.  */
@@ -1958,19 +2363,21 @@ yylex ()
     case '/':
     case '[':
     case ']':
+    case '<':
+    case '>':
       return *str++;
     case '+':
       /* It so happens that a '+' can only appear at the end of an
-         operand.  If it appears anywhere else, it must be a unary
-         plus on an expression.  */
-      if (str[1] == '\0')
+	 operand, or if it is trailed by an '&'(see mac load insn).
+	 If it appears anywhere else, it must be a unary.  */
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       break;
     case '-':
       /* A '-' can only appear in -(ar), rn-rn, or ar@-.  If it
          appears anywhere else, it must be a unary minus on an
-         expression.  */
-      if (str[1] == '\0')
+         expression, unless it it trailed by a '&'(see mac load insn).  */
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       s = str + 1;
       if (*s == '(')
@@ -2261,3 +2668,5 @@ yyerror (s)
 {
   op->error = s;
 }
+
+
diff --git a/gas/mac-as.r b/gas/mac-as.r
deleted file mode 100644
index f36c033cb070..000000000000
--- a/gas/mac-as.r
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Resources for GNU AS. */
-
-#include "SysTypes.r"
-
-/* Version resources. */
-
-resource 'vers' (1)  {
-	0,
-	0,
-	0,
-	0,
-	verUs,
-	VERSION_STRING,
-	VERSION_STRING  " (C) 1986-95 FSF, Inc."
-};
-
-resource 'vers' (2, purgeable)  {
-	0,
-	0,
-	0,
-	0,
-	verUs,
-	VERSION_STRING,
-	"GAS " VERSION_STRING " for MPW"
-};
-
-#ifdef WANT_CFRG
-
-#include "CodeFragmentTypes.r"
-
-resource 'cfrg' (0) {
-	{
-		kPowerPC,
-		kFullLib,
-		kNoVersionNum, kNoVersionNum,
-		0,0,
-		kIsApp, kOnDiskFlat, kZeroOffset, kWholeFork,
-		PROG_NAME
-	}
-};
-
-#endif /* WANT_CFRG */
diff --git a/gas/macro.c b/gas/macro.c
index 09917443a1d5..af98bada6a86 100644
--- a/gas/macro.c
+++ b/gas/macro.c
@@ -1,6 +1,6 @@
 /* macro.c - macro support for gas
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-   Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+   2004, 2005 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -19,8 +19,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "config.h"
 
@@ -54,6 +54,7 @@ extern void *alloca ();
 #ifdef HAVE_STDLIB_H
 #include <stdlib.h>
 #endif
+#include "as.h"
 #include "libiberty.h"
 #include "safe-ctype.h"
 #include "sb.h"
@@ -69,13 +70,16 @@ extern void *alloca ();
 
 static int get_token (int, sb *, sb *);
 static int getstring (int, sb *, sb *);
-static int get_any_string (int, sb *, sb *, int, int);
+static int get_any_string (int, sb *, sb *);
+static formal_entry *new_formal (void);
+static void del_formal (formal_entry *);
 static int do_formals (macro_entry *, int, sb *);
 static int get_apost_token (int, sb *, sb *, int);
 static int sub_actual (int, sb *, sb *, struct hash_control *, int, sb *, int);
 static const char *macro_expand_body
-  (sb *, sb *, formal_entry *, struct hash_control *, int);
+  (sb *, sb *, formal_entry *, struct hash_control *, const macro_entry *);
 static const char *macro_expand (int, sb *, macro_entry *, sb *);
+static void free_macro(macro_entry *);
 
 #define ISWHITE(x) ((x) == ' ' || (x) == '\t')
 
@@ -132,6 +136,14 @@ macro_init (int alternate, int mri, int strip_at,
   macro_expr = expr;
 }
 
+/* Switch in and out of alternate mode on the fly.  */
+
+void
+macro_set_alternate (int alternate)
+{
+  macro_alternate = alternate;
+}
+
 /* Switch in and out of MRI mode on the fly.  */
 
 void
@@ -143,6 +155,7 @@ macro_mri_mode (int mri)
 /* Read input lines till we get to a TO string.
    Increase nesting depth if we get a FROM string.
    Put the results into sb at PTR.
+   FROM may be NULL (or will be ignored) if TO is "ENDR".
    Add a new input line to an sb using GET_LINE.
    Return 1 on success, 0 on unexpected EOF.  */
 
@@ -150,59 +163,92 @@ int
 buffer_and_nest (const char *from, const char *to, sb *ptr,
 		 int (*get_line) (sb *))
 {
-  int from_len = strlen (from);
+  int from_len;
   int to_len = strlen (to);
   int depth = 1;
   int line_start = ptr->len;
 
   int more = get_line (ptr);
 
+  if (to_len == 4 && strcasecmp(to, "ENDR") == 0)
+    {
+      from = NULL;
+      from_len = 0;
+    }
+  else
+    from_len = strlen (from);
+
   while (more)
     {
-      /* Try and find the first pseudo op on the line.  */
+      /* Try to find the first pseudo op on the line.  */
       int i = line_start;
 
-      if (! macro_alternate && ! macro_mri)
-	{
-	  /* With normal syntax we can suck what we want till we get
-	     to the dot.  With the alternate, labels have to start in
-	     the first column, since we cant tell what's a label and
-	     whats a pseudoop.  */
+      /* With normal syntax we can suck what we want till we get
+	 to the dot.  With the alternate, labels have to start in
+	 the first column, since we can't tell what's a label and
+	 what's a pseudoop.  */
 
+      if (! LABELS_WITHOUT_COLONS)
+	{
 	  /* Skip leading whitespace.  */
 	  while (i < ptr->len && ISWHITE (ptr->ptr[i]))
 	    i++;
+	}
 
-	  /* Skip over a label.  */
-	  while (i < ptr->len
-		 && (ISALNUM (ptr->ptr[i])
-		     || ptr->ptr[i] == '_'
-		     || ptr->ptr[i] == '$'))
+      for (;;)
+	{
+	  /* Skip over a label, if any.  */
+	  if (i >= ptr->len || ! is_name_beginner (ptr->ptr[i]))
+	    break;
+	  i++;
+	  while (i < ptr->len && is_part_of_name (ptr->ptr[i]))
 	    i++;
-
-	  /* And a colon.  */
-	  if (i < ptr->len
-	      && ptr->ptr[i] == ':')
+	  if (i < ptr->len && is_name_ender (ptr->ptr[i]))
 	    i++;
-
+	  if (LABELS_WITHOUT_COLONS)
+	    break;
+	  /* Skip whitespace.  */
+	  while (i < ptr->len && ISWHITE (ptr->ptr[i]))
+	    i++;
+	  /* Check for the colon.  */
+	  if (i >= ptr->len || ptr->ptr[i] != ':')
+	    {
+	      i = line_start;
+	      break;
+	    }
+	  i++;
+	  line_start = i;
 	}
+
       /* Skip trailing whitespace.  */
       while (i < ptr->len && ISWHITE (ptr->ptr[i]))
 	i++;
 
       if (i < ptr->len && (ptr->ptr[i] == '.'
-			   || macro_alternate
+			   || NO_PSEUDO_DOT
 			   || macro_mri))
 	{
-	  if (ptr->ptr[i] == '.')
+	  if (! flag_m68k_mri && ptr->ptr[i] == '.')
 	    i++;
-	  if (strncasecmp (ptr->ptr + i, from, from_len) == 0
+	  if (from == NULL
+	     && strncasecmp (ptr->ptr + i, "IRPC", from_len = 4) != 0
+	     && strncasecmp (ptr->ptr + i, "IRP", from_len = 3) != 0
+	     && strncasecmp (ptr->ptr + i, "IREPC", from_len = 5) != 0
+	     && strncasecmp (ptr->ptr + i, "IREP", from_len = 4) != 0
+	     && strncasecmp (ptr->ptr + i, "REPT", from_len = 4) != 0
+	     && strncasecmp (ptr->ptr + i, "REP", from_len = 3) != 0)
+	    from_len = 0;
+	  if ((from != NULL
+	       ? strncasecmp (ptr->ptr + i, from, from_len) == 0
+	       : from_len > 0)
 	      && (ptr->len == (i + from_len)
-		  || ! ISALNUM (ptr->ptr[i + from_len])))
+		  || ! (is_part_of_name (ptr->ptr[i + from_len])
+			|| is_name_ender (ptr->ptr[i + from_len]))))
 	    depth++;
 	  if (strncasecmp (ptr->ptr + i, to, to_len) == 0
 	      && (ptr->len == (i + to_len)
-		  || ! ISALNUM (ptr->ptr[i + to_len])))
+		  || ! (is_part_of_name (ptr->ptr[i + to_len])
+			|| is_name_ender (ptr->ptr[i + to_len]))))
 	    {
 	      depth--;
 	      if (depth == 0)
@@ -230,15 +276,16 @@ static int
 get_token (int idx, sb *in, sb *name)
 {
   if (idx < in->len
-      && (ISALPHA (in->ptr[idx])
-	  || in->ptr[idx] == '_'
-	  || in->ptr[idx] == '$'))
+      && is_name_beginner (in->ptr[idx]))
     {
       sb_add_char (name, in->ptr[idx++]);
       while (idx < in->len
-	     && (ISALNUM (in->ptr[idx])
-		 || in->ptr[idx] == '_'
-		 || in->ptr[idx] == '$'))
+	     && is_part_of_name (in->ptr[idx]))
+	{
+	  sb_add_char (name, in->ptr[idx++]);
+	}
+      if (idx < in->len
+	     && is_name_ender (in->ptr[idx]))
 	{
 	  sb_add_char (name, in->ptr[idx++]);
 	}
@@ -254,8 +301,6 @@ get_token (int idx, sb *in, sb *name)
 static int
 getstring (int idx, sb *in, sb *acc)
 {
-  idx = sb_skip_white (idx, in);
-
   while (idx < in->len
 	 && (in->ptr[idx] == '"'
 	     || (in->ptr[idx] == '<' && (macro_alternate || macro_mri))
@@ -334,13 +379,13 @@ getstring (int idx, sb *in, sb *acc)
 /* Fetch string from the input stream,
    rules:
     'Bxyx<whitespace>  	-> return 'Bxyza
-    %<char>		-> return string of decimal value of x
-    "<string>"		-> return string
-    xyx<whitespace>     -> return xyz
-*/
+    %<expr>		-> return string of decimal value of <expr>
+    "string"		-> return string
+    (string)		-> return (string-including-whitespaces)
+    xyx<whitespace>     -> return xyz.  */
 
 static int
-get_any_string (int idx, sb *in, sb *out, int expand, int pretend_quoted)
+get_any_string (int idx, sb *in, sb *out)
 {
   sb_reset (out);
   idx = sb_skip_white (idx, in);
@@ -352,12 +397,11 @@ get_any_string (int idx, sb *in, sb *out, int expand, int pretend_quoted)
 	  while (!ISSEP (in->ptr[idx]))
 	    sb_add_char (out, in->ptr[idx++]);
 	}
-      else if (in->ptr[idx] == '%'
-	       && macro_alternate
-	       && expand)
+      else if (in->ptr[idx] == '%' && macro_alternate)
 	{
 	  int val;
 	  char buf[20];
+
 	  /* Turns the next expression into a string.  */
 	  /* xgettext: no-c-format */
 	  idx = (*macro_expr) (_("% operator needs absolute expression"),
@@ -371,15 +415,12 @@ get_any_string (int idx, sb *in, sb *out, int expand, int pretend_quoted)
 	       || (in->ptr[idx] == '<' && (macro_alternate || macro_mri))
 	       || (macro_alternate && in->ptr[idx] == '\''))
 	{
-	  if (macro_alternate
-	      && ! macro_strip_at
-	      && expand)
+	  if (macro_alternate && ! macro_strip_at && in->ptr[idx] != '<')
 	    {
 	      /* Keep the quotes.  */
-	      sb_add_char (out, '\"');
-
+	      sb_add_char (out, '"');
 	      idx = getstring (idx, in, out);
-	      sb_add_char (out, '\"');
+	      sb_add_char (out, '"');
 	    }
 	  else
 	    {
@@ -388,93 +429,194 @@ get_any_string (int idx, sb *in, sb *out, int expand, int pretend_quoted)
 	}
       else
 	{
+	  char *br_buf = xmalloc(1);
+	  char *in_br = br_buf;
+
+	  *in_br = '\0';
 	  while (idx < in->len
-		 && (in->ptr[idx] == '"'
-		     || in->ptr[idx] == '\''
-		     || pretend_quoted
+		 && (*in_br
 		     || (in->ptr[idx] != ' '
-			 && in->ptr[idx] != '\t'
-			 && in->ptr[idx] != ','
-			 && (in->ptr[idx] != '<'
-			     || (! macro_alternate && ! macro_mri)))))
+			 && in->ptr[idx] != '\t'))
+		 && in->ptr[idx] != ','
+		 && (in->ptr[idx] != '<'
+		     || (! macro_alternate && ! macro_mri)))
 	    {
-	      if (in->ptr[idx] == '"'
-		  || in->ptr[idx] == '\'')
+	      char tchar = in->ptr[idx];
+
+	      switch (tchar)
 		{
-		  char tchar = in->ptr[idx];
+		case '"':
+		case '\'':
 		  sb_add_char (out, in->ptr[idx++]);
 		  while (idx < in->len
 			 && in->ptr[idx] != tchar)
 		    sb_add_char (out, in->ptr[idx++]);
 		  if (idx == in->len)
 		    return idx;
+		  break;
+		case '(':
+		case '[':
+		  if (in_br > br_buf)
+		    --in_br;
+		  else
+		    {
+		      br_buf = xmalloc(strlen(in_br) + 2);
+		      strcpy(br_buf + 1, in_br);
+		      free(in_br);
+		      in_br = br_buf;
+		    }
+		  *in_br = tchar;
+		  break;
+		case ')':
+		  if (*in_br == '(')
+		    ++in_br;
+		  break;
+		case ']':
+		  if (*in_br == '[')
+		    ++in_br;
+		  break;
 		}
-	      sb_add_char (out, in->ptr[idx++]);
+	      sb_add_char (out, tchar);
+	      ++idx;
 	    }
+	  free(br_buf);
 	}
     }
 
   return idx;
 }
 
+/* Allocate a new formal.  */
+
+static formal_entry *
+new_formal (void)
+{
+  formal_entry *formal;
+
+  formal = xmalloc (sizeof (formal_entry));
+
+  sb_new (&formal->name);
+  sb_new (&formal->def);
+  sb_new (&formal->actual);
+  formal->next = NULL;
+  formal->type = FORMAL_OPTIONAL;
+  return formal;
+}
+
+/* Free a formal.  */
+
+static void
+del_formal (formal_entry *formal)
+{
+  sb_kill (&formal->actual);
+  sb_kill (&formal->def);
+  sb_kill (&formal->name);
+  free (formal);
+}
+
 /* Pick up the formal parameters of a macro definition.  */
 
 static int
 do_formals (macro_entry *macro, int idx, sb *in)
 {
   formal_entry **p = &macro->formals;
+  const char *name;
 
-  macro->formal_count = 0;
-  macro->formal_hash = hash_new ();
+  idx = sb_skip_white (idx, in);
   while (idx < in->len)
     {
-      formal_entry *formal;
-
-      formal = (formal_entry *) xmalloc (sizeof (formal_entry));
-
-      sb_new (&formal->name);
-      sb_new (&formal->def);
-      sb_new (&formal->actual);
+      formal_entry *formal = new_formal ();
+      int cidx;
 
-      idx = sb_skip_white (idx, in);
       idx = get_token (idx, in, &formal->name);
       if (formal->name.len == 0)
-	break;
+	{
+	  if (macro->formal_count)
+	    --idx;
+	  break;
+	}
       idx = sb_skip_white (idx, in);
-      if (formal->name.len)
+      /* This is a formal.  */
+      name = sb_terminate (&formal->name);
+      if (! macro_mri
+	  && idx < in->len
+	  && in->ptr[idx] == ':'
+	  && (! is_name_beginner (':')
+	      || idx + 1 >= in->len
+	      || ! is_part_of_name (in->ptr[idx + 1])))
 	{
-	  /* This is a formal.  */
-	  if (idx < in->len && in->ptr[idx] == '=')
+	  /* Got a qualifier.  */
+	  sb qual;
+
+	  sb_new (&qual);
+	  idx = get_token (sb_skip_white (idx + 1, in), in, &qual);
+	  sb_terminate (&qual);
+	  if (qual.len == 0)
+	    as_bad_where (macro->file,
+			  macro->line,
+			  _("Missing parameter qualifier for `%s' in macro `%s'"),
+			  name,
+			  macro->name);
+	  else if (strcmp (qual.ptr, "req") == 0)
+	    formal->type = FORMAL_REQUIRED;
+	  else if (strcmp (qual.ptr, "vararg") == 0)
+	    formal->type = FORMAL_VARARG;
+	  else
+	    as_bad_where (macro->file,
+			  macro->line,
+			  _("`%s' is not a valid parameter qualifier for `%s' in macro `%s'"),
+			  qual.ptr,
+			  name,
+			  macro->name);
+	  sb_kill (&qual);
+	  idx = sb_skip_white (idx, in);
+	}
+      if (idx < in->len && in->ptr[idx] == '=')
+	{
+	  /* Got a default.  */
+	  idx = get_any_string (idx + 1, in, &formal->def);
+	  idx = sb_skip_white (idx, in);
+	  if (formal->type == FORMAL_REQUIRED)
 	    {
-	      /* Got a default.  */
-	      idx = get_any_string (idx + 1, in, &formal->def, 1, 0);
+	      sb_reset (&formal->def);
+	      as_warn_where (macro->file,
+			    macro->line,
+			    _("Pointless default value for required parameter `%s' in macro `%s'"),
+			    name,
+			    macro->name);
 	    }
 	}
 
       /* Add to macro's hash table.  */
-      hash_jam (macro->formal_hash, sb_terminate (&formal->name), formal);
+      if (! hash_find (macro->formal_hash, name))
+	hash_jam (macro->formal_hash, name, formal);
+      else
+	as_bad_where (macro->file,
+		      macro->line,
+		      _("A parameter named `%s' already exists for macro `%s'"),
+		      name,
+		      macro->name);
 
-      formal->index = macro->formal_count;
-      idx = sb_skip_comma (idx, in);
-      macro->formal_count++;
+      formal->index = macro->formal_count++;
       *p = formal;
       p = &formal->next;
-      *p = NULL;
+      if (formal->type == FORMAL_VARARG)
+	break;
+      cidx = idx;
+      idx = sb_skip_comma (idx, in);
+      if (idx != cidx && idx >= in->len)
+	{
+	  idx = cidx;
+	  break;
+	}
     }
 
   if (macro_mri)
     {
-      formal_entry *formal;
-      const char *name;
+      formal_entry *formal = new_formal ();
 
       /* Add a special NARG formal, which macro_expand will set to the
          number of arguments.  */
-      formal = (formal_entry *) xmalloc (sizeof (formal_entry));
-
-      sb_new (&formal->name);
-      sb_new (&formal->def);
-      sb_new (&formal->actual);
-
       /* The same MRI assemblers which treat '@' characters also use
          the name $NARG.  At least until we find an exception.  */
       if (macro_strip_at)
@@ -485,11 +627,16 @@ do_formals (macro_entry *macro, int idx, sb *in)
       sb_add_string (&formal->name, name);
 
       /* Add to macro's hash table.  */
+      if (hash_find (macro->formal_hash, name))
+	as_bad_where (macro->file,
+		      macro->line,
+		      _("Reserved word `%s' used as parameter in macro `%s'"),
+		      name,
+		      macro->name);
       hash_jam (macro->formal_hash, name, formal);
 
       formal->index = NARG_INDEX;
       *p = formal;
-      formal->next = NULL;
     }
 
   return idx;
@@ -501,31 +648,39 @@ do_formals (macro_entry *macro, int idx, sb *in)
 
 const char *
 define_macro (int idx, sb *in, sb *label,
-	      int (*get_line) (sb *), const char **namep)
+	      int (*get_line) (sb *),
+	      char *file, unsigned int line,
+	      const char **namep)
 {
   macro_entry *macro;
   sb name;
-  const char *namestr;
+  const char *error = NULL;
 
   macro = (macro_entry *) xmalloc (sizeof (macro_entry));
   sb_new (&macro->sub);
   sb_new (&name);
+  macro->file = file;
+  macro->line = line;
 
   macro->formal_count = 0;
   macro->formals = 0;
+  macro->formal_hash = hash_new ();
 
   idx = sb_skip_white (idx, in);
   if (! buffer_and_nest ("MACRO", "ENDM", &macro->sub, get_line))
-    return _("unexpected end of file in macro definition");
+    error = _("unexpected end of file in macro `%s' definition");
   if (label != NULL && label->len != 0)
     {
       sb_add_sb (&name, label);
+      macro->name = sb_terminate (&name);
       if (idx < in->len && in->ptr[idx] == '(')
 	{
 	  /* It's the label: MACRO (formals,...)  sort  */
 	  idx = do_formals (macro, idx + 1, in);
-	  if (in->ptr[idx] != ')')
-	    return _("missing ) after formals");
+	  if (idx < in->len && in->ptr[idx] == ')')
+	    idx = sb_skip_white (idx + 1, in);
+	  else if (!error)
+	    error = _("missing `)' after formals in macro definition `%s'");
 	}
       else
 	{
@@ -535,23 +690,39 @@ define_macro (int idx, sb *in, sb *label,
     }
   else
     {
+      int cidx;
+
       idx = get_token (idx, in, &name);
-      idx = sb_skip_comma (idx, in);
-      idx = do_formals (macro, idx, in);
+      macro->name = sb_terminate (&name);
+      if (name.len == 0)
+	error = _("Missing macro name");
+      cidx = sb_skip_white (idx, in);
+      idx = sb_skip_comma (cidx, in);
+      if (idx == cidx || idx < in->len)
+	idx = do_formals (macro, idx, in);
+      else
+	idx = cidx;
     }
+  if (!error && idx < in->len)
+    error = _("Bad parameter list for macro `%s'");
 
   /* And stick it in the macro hash table.  */
   for (idx = 0; idx < name.len; idx++)
     name.ptr[idx] = TOLOWER (name.ptr[idx]);
-  namestr = sb_terminate (&name);
-  hash_jam (macro_hash, namestr, (PTR) macro);
-
-  macro_defined = 1;
+  if (hash_find (macro_hash, macro->name))
+    error = _("Macro `%s' was already defined");
+  if (!error)
+    error = hash_jam (macro_hash, macro->name, (PTR) macro);
 
   if (namep != NULL)
-    *namep = namestr;
+    *namep = macro->name;
 
-  return NULL;
+  if (!error)
+    macro_defined = 1;
+  else
+    free_macro (macro);
+
+  return error;
 }
 
 /* Scan a token, and then skip KIND.  */
@@ -619,16 +790,16 @@ sub_actual (int start, sb *in, sb *t, struct hash_control *formal_hash,
 
 static const char *
 macro_expand_body (sb *in, sb *out, formal_entry *formals,
-		   struct hash_control *formal_hash, int locals)
+		   struct hash_control *formal_hash, const macro_entry *macro)
 {
   sb t;
-  int src = 0;
-  int inquote = 0;
+  int src = 0, inquote = 0, macro_line = 0;
   formal_entry *loclist = NULL;
+  const char *err = NULL;
 
   sb_new (&t);
 
-  while (src < in->len)
+  while (src < in->len && !err)
     {
       if (in->ptr[src] == '&')
 	{
@@ -643,13 +814,15 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	  else
 	    {
 	      /* FIXME: Why do we do this?  */
+	      /* At least in alternate mode this seems correct; without this
+	         one can't append a literal to a parameter.  */
 	      src = sub_actual (src + 1, in, &t, formal_hash, '&', out, 0);
 	    }
 	}
       else if (in->ptr[src] == '\\')
 	{
 	  src++;
-	  if (in->ptr[src] == '(')
+	  if (src < in->len && in->ptr[src] == '(')
 	    {
 	      /* Sub in till the next ')' literally.  */
 	      src++;
@@ -657,12 +830,14 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 		{
 		  sb_add_char (out, in->ptr[src++]);
 		}
-	      if (in->ptr[src] == ')')
+	      if (src < in->len)
 		src++;
+	      else if (!macro)
+		err = _("missing `)'");
 	      else
-		return _("missplaced )");
+		as_bad_where (macro->file, macro->line + macro_line, _("missing `)'"));
 	    }
-	  else if (in->ptr[src] == '@')
+	  else if (src < in->len && in->ptr[src] == '@')
 	    {
 	      /* Sub in the macro invocation number.  */
 
@@ -671,7 +846,7 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	      sprintf (buffer, "%d", macro_number);
 	      sb_add_string (out, buffer);
 	    }
-	  else if (in->ptr[src] == '&')
+	  else if (src < in->len && in->ptr[src] == '&')
 	    {
 	      /* This is a preprocessor variable name, we don't do them
 		 here.  */
@@ -679,7 +854,7 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	      sb_add_char (out, '&');
 	      src++;
 	    }
-	  else if (macro_mri && ISALNUM (in->ptr[src]))
+	  else if (macro_mri && src < in->len && ISALNUM (in->ptr[src]))
 	    {
 	      int ind;
 	      formal_entry *f;
@@ -710,14 +885,12 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	    }
 	}
       else if ((macro_alternate || macro_mri)
-	       && (ISALPHA (in->ptr[src])
-		   || in->ptr[src] == '_'
-		   || in->ptr[src] == '$')
+	       && is_name_beginner (in->ptr[src])
 	       && (! inquote
 		   || ! macro_strip_at
 		   || (src > 0 && in->ptr[src - 1] == '@')))
 	{
-	  if (! locals
+	  if (! macro
 	      || src + 5 >= in->len
 	      || strncasecmp (in->ptr + src, "LOCAL", 5) != 0
 	      || ! ISWHITE (in->ptr[src + 5]))
@@ -729,31 +902,38 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	    }
 	  else
 	    {
-	      formal_entry *f;
-
 	      src = sb_skip_white (src + 5, in);
 	      while (in->ptr[src] != '\n')
 		{
-		  static int loccnt;
-		  char buf[20];
-		  const char *err;
-
-		  f = (formal_entry *) xmalloc (sizeof (formal_entry));
-		  sb_new (&f->name);
-		  sb_new (&f->def);
-		  sb_new (&f->actual);
-		  f->index = LOCAL_INDEX;
-		  f->next = loclist;
-		  loclist = f;
+		  const char *name;
+		  formal_entry *f = new_formal ();
 
 		  src = get_token (src, in, &f->name);
-		  ++loccnt;
-		  sprintf (buf, "LL%04x", loccnt);
-		  sb_add_string (&f->actual, buf);
+		  name = sb_terminate (&f->name);
+		  if (! hash_find (formal_hash, name))
+		    {
+		      static int loccnt;
+		      char buf[20];
 
-		  err = hash_jam (formal_hash, sb_terminate (&f->name), f);
-		  if (err != NULL)
-		    return err;
+		      f->index = LOCAL_INDEX;
+		      f->next = loclist;
+		      loclist = f;
+
+		      sprintf (buf, IS_ELF ? ".LL%04x" : "LL%04x", ++loccnt);
+		      sb_add_string (&f->actual, buf);
+
+		      err = hash_jam (formal_hash, name, f);
+		      if (err != NULL)
+			break;
+		    }
+		  else
+		    {
+		      as_bad_where (macro->file,
+				    macro->line + macro_line,
+				    _("`%s' was already used as parameter (or another local) name"),
+				    name);
+		      del_formal (f);
+		    }
 
 		  src = sb_skip_comma (src, in);
 		}
@@ -813,6 +993,8 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
 	}
       else
 	{
+	  if (in->ptr[src] == '\n')
+	    ++macro_line;
 	  sb_add_char (out, in->ptr[src++]);
 	}
     }
@@ -827,14 +1009,11 @@ macro_expand_body (sb *in, sb *out, formal_entry *formals,
       /* Setting the value to NULL effectively deletes the entry.  We
          avoid calling hash_delete because it doesn't reclaim memory.  */
       hash_jam (formal_hash, sb_terminate (&loclist->name), NULL);
-      sb_kill (&loclist->name);
-      sb_kill (&loclist->def);
-      sb_kill (&loclist->actual);
-      free (loclist);
+      del_formal (loclist);
       loclist = f;
     }
 
-  return NULL;
+  return err;
 }
 
 /* Assign values to the formal parameters of a macro, and expand the
@@ -849,7 +1028,7 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
   int is_positional = 0;
   int is_keyword = 0;
   int narg = 0;
-  const char *err;
+  const char *err = NULL;
 
   sb_new (&t);
 
@@ -873,18 +1052,14 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 		  && in->ptr[idx] != ' '
 		  && in->ptr[idx] != '\t')
 	    {
-	      formal_entry *n;
+	      formal_entry *n = new_formal ();
 
-	      n = (formal_entry *) xmalloc (sizeof (formal_entry));
-	      sb_new (&n->name);
-	      sb_new (&n->def);
-	      sb_new (&n->actual);
 	      n->index = QUAL_INDEX;
 
 	      n->next = m->formals;
 	      m->formals = n;
 
-	      idx = get_any_string (idx, in, &n->actual, 1, 0);
+	      idx = get_any_string (idx, in, &n->actual);
 	    }
 	}
     }
@@ -913,17 +1088,28 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	  sb_reset (&t);
 	  idx = get_token (idx, in, &t);
 	  if (in->ptr[idx] != '=')
-	    return _("confusion in formal parameters");
+	    {
+	      err = _("confusion in formal parameters");
+	      break;
+	    }
 
 	  /* Lookup the formal in the macro's list.  */
 	  ptr = (formal_entry *) hash_find (m->formal_hash, sb_terminate (&t));
 	  if (!ptr)
-	    return _("macro formal argument does not exist");
+	    as_bad (_("Parameter named `%s' does not exist for macro `%s'"),
+		    t.ptr,
+		    m->name);
 	  else
 	    {
 	      /* Insert this value into the right place.  */
-	      sb_reset (&ptr->actual);
-	      idx = get_any_string (idx + 1, in, &ptr->actual, 0, 0);
+	      if (ptr->actual.len)
+		{
+		  as_warn (_("Value for parameter `%s' of macro `%s' was already specified"),
+			   ptr->name.ptr,
+			   m->name);
+		  sb_reset (&ptr->actual);
+		}
+	      idx = get_any_string (idx + 1, in, &ptr->actual);
 	      if (ptr->actual.len > 0)
 		++narg;
 	    }
@@ -933,7 +1119,10 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	  /* This is a positional arg.  */
 	  is_positional = 1;
 	  if (is_keyword)
-	    return _("can't mix positional and keyword arguments");
+	    {
+	      err = _("can't mix positional and keyword arguments");
+	      break;
+	    }
 
 	  if (!f)
 	    {
@@ -941,13 +1130,12 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	      int c;
 
 	      if (!macro_mri)
-		return _("too many positional arguments");
+		{
+		  err = _("too many positional arguments");
+		  break;
+		}
 
-	      f = (formal_entry *) xmalloc (sizeof (formal_entry));
-	      sb_new (&f->name);
-	      sb_new (&f->def);
-	      sb_new (&f->actual);
-	      f->next = NULL;
+	      f = new_formal ();
 
 	      c = -1;
 	      for (pf = &m->formals; *pf != NULL; pf = &(*pf)->next)
@@ -959,8 +1147,13 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	      f->index = c;
 	    }
 
-	  sb_reset (&f->actual);
-	  idx = get_any_string (idx, in, &f->actual, 1, 0);
+	  if (f->type != FORMAL_VARARG)
+	    idx = get_any_string (idx, in, &f->actual);
+	  else
+	    {
+	      sb_add_buffer (&f->actual, in->ptr + idx, in->len - idx);
+	      idx = in->len;
+	    }
 	  if (f->actual.len > 0)
 	    ++narg;
 	  do
@@ -981,21 +1174,29 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	}
     }
 
-  if (macro_mri)
+  if (! err)
     {
-      char buffer[20];
-
-      sb_reset (&t);
-      sb_add_string (&t, macro_strip_at ? "$NARG" : "NARG");
-      ptr = (formal_entry *) hash_find (m->formal_hash, sb_terminate (&t));
-      sb_reset (&ptr->actual);
-      sprintf (buffer, "%d", narg);
-      sb_add_string (&ptr->actual, buffer);
-    }
+      for (ptr = m->formals; ptr; ptr = ptr->next)
+	{
+	  if (ptr->type == FORMAL_REQUIRED && ptr->actual.len == 0)
+	    as_bad (_("Missing value for required parameter `%s' of macro `%s'"),
+		    ptr->name.ptr,
+		    m->name);
+	}
 
-  err = macro_expand_body (&m->sub, out, m->formals, m->formal_hash, 1);
-  if (err != NULL)
-    return err;
+      if (macro_mri)
+	{
+	  char buffer[20];
+
+	  sb_reset (&t);
+	  sb_add_string (&t, macro_strip_at ? "$NARG" : "NARG");
+	  ptr = (formal_entry *) hash_find (m->formal_hash, sb_terminate (&t));
+	  sprintf (buffer, "%d", narg);
+	  sb_add_string (&ptr->actual, buffer);
+	}
+
+      err = macro_expand_body (&m->sub, out, m->formals, m->formal_hash, m);
+    }
 
   /* Discard any unnamed formal arguments.  */
   if (macro_mri)
@@ -1009,20 +1210,18 @@ macro_expand (int idx, sb *in, macro_entry *m, sb *out)
 	    pf = &(*pf)->next;
 	  else
 	    {
-	      sb_kill (&(*pf)->name);
-	      sb_kill (&(*pf)->def);
-	      sb_kill (&(*pf)->actual);
 	      f = (*pf)->next;
-	      free (*pf);
+	      del_formal (*pf);
 	      *pf = f;
 	    }
 	}
     }
 
   sb_kill (&t);
-  macro_number++;
+  if (!err)
+    macro_number++;
 
-  return NULL;
+  return err;
 }
 
 /* Check for a macro.  If one is found, put the expansion into
@@ -1037,16 +1236,14 @@ check_macro (const char *line, sb *expand,
   macro_entry *macro;
   sb line_sb;
 
-  if (! ISALPHA (*line)
-      && *line != '_'
-      && *line != '$'
+  if (! is_name_beginner (*line)
       && (! macro_mri || *line != '.'))
     return 0;
 
   s = line + 1;
-  while (ISALNUM (*s)
-	 || *s == '_'
-	 || *s == '$')
+  while (is_part_of_name (*s))
+    ++s;
+  if (is_name_ender (*s))
     ++s;
 
   copy = (char *) alloca (s - line + 1);
@@ -1077,12 +1274,49 @@ check_macro (const char *line, sb *expand,
   return 1;
 }
 
+/* Free the memory allocated to a macro.  */
+
+static void
+free_macro(macro_entry *macro)
+{
+  formal_entry *formal;
+
+  for (formal = macro->formals; formal; )
+    {
+      formal_entry *f;
+
+      f = formal;
+      formal = formal->next;
+      del_formal (f);
+    }
+  hash_die (macro->formal_hash);
+  sb_kill (&macro->sub);
+  free (macro);
+}
+
 /* Delete a macro.  */
 
 void
 delete_macro (const char *name)
 {
-  hash_delete (macro_hash, name);
+  char *copy;
+  size_t i, len;
+  macro_entry *macro;
+
+  len = strlen (name);
+  copy = (char *) alloca (len + 1);
+  for (i = 0; i < len; ++i)
+    copy[i] = TOLOWER (name[i]);
+  copy[i] = '\0';
+
+  /* Since hash_delete doesn't free memory, just clear out the entry.  */
+  if ((macro = hash_find (macro_hash, copy)) != NULL)
+    {
+      hash_jam (macro_hash, copy, NULL);
+      free_macro (macro);
+    }
+  else
+    as_warn (_("Attempt to purge non-existant macro `%s'"), copy);
 }
 
 /* Handle the MRI IRP and IRPC pseudo-ops.  These are handled as a
@@ -1092,21 +1326,15 @@ delete_macro (const char *name)
 const char *
 expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 {
-  const char *mn;
   sb sub;
   formal_entry f;
   struct hash_control *h;
   const char *err;
 
-  if (irpc)
-    mn = "IRPC";
-  else
-    mn = "IRP";
-
   idx = sb_skip_white (idx, in);
 
   sb_new (&sub);
-  if (! buffer_and_nest (mn, "ENDR", &sub, get_line))
+  if (! buffer_and_nest (NULL, "ENDR", &sub, get_line))
     return _("unexpected end of file in irp or irpc");
 
   sb_new (&f.name);
@@ -1124,6 +1352,7 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 
   f.index = 1;
   f.next = NULL;
+  f.type = FORMAL_OPTIONAL;
 
   sb_reset (out);
 
@@ -1132,8 +1361,6 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
     {
       /* Expand once with a null string.  */
       err = macro_expand_body (&sub, out, &f, h, 0);
-      if (err != NULL)
-	return err;
     }
   else
     {
@@ -1142,7 +1369,7 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
       while (idx < in->len)
 	{
 	  if (!irpc)
-	    idx = get_any_string (idx, in, &f.actual, 1, 0);
+	    idx = get_any_string (idx, in, &f.actual);
 	  else
 	    {
 	      if (in->ptr[idx] == '"')
@@ -1162,7 +1389,7 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
 	    }
 	  err = macro_expand_body (&sub, out, &f, h, 0);
 	  if (err != NULL)
-	    return err;
+	    break;
 	  if (!irpc)
 	    idx = sb_skip_comma (idx, in);
 	  else
@@ -1171,7 +1398,10 @@ expand_irp (int irpc, int idx, sb *in, sb *out, int (*get_line) (sb *))
     }
 
   hash_die (h);
+  sb_kill (&f.actual);
+  sb_kill (&f.def);
+  sb_kill (&f.name);
   sb_kill (&sub);
 
-  return NULL;
+  return err;
 }
diff --git a/gas/macro.h b/gas/macro.h
index a8bffaa0efc7..4fdaa52d0974 100644
--- a/gas/macro.h
+++ b/gas/macro.h
@@ -1,5 +1,5 @@
 /* macro.h - header file for macro support for gas
-   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004
    Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
@@ -19,8 +19,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef MACRO_H
 
@@ -45,6 +45,12 @@ typedef struct formal_struct {
   sb def;			/* The default value.  */
   sb actual;			/* The actual argument (changed on each expansion).  */
   int index;			/* The index of the formal 0..formal_count - 1.  */
+  enum formal_type
+    {
+      FORMAL_OPTIONAL,
+      FORMAL_REQUIRED,
+      FORMAL_VARARG
+    } type;			/* The kind of the formal.  */
 } formal_entry;
 
 /* Other values found in the index field of a formal_entry.  */
@@ -60,6 +66,9 @@ typedef struct macro_struct
   int formal_count;			/* Number of formal args.  */
   formal_entry *formals;		/* Pointer to list of formal_structs.  */
   struct hash_control *formal_hash;	/* Hash table of formals.  */
+  const char *name;			/* Macro name.  */
+  char *file;				/* File the macro was defined in.  */
+  unsigned int line;			/* Line number of definition.  */
 } macro_entry;
 
 /* Whether any macros have been defined.  */
@@ -70,12 +79,17 @@ extern int macro_defined;
 
 extern int macro_nest;
 
+/* The macro hash table.  */
+
+extern struct hash_control *macro_hash;
+
 extern int buffer_and_nest (const char *, const char *, sb *, int (*) (sb *));
 extern void macro_init
   (int, int, int, int (*) (const char *, int, sb *, int *));
+extern void macro_set_alternate (int);
 extern void macro_mri_mode (int);
 extern const char *define_macro
-  (int, sb *, sb *, int (*) (sb *), const char **);
+  (int, sb *, sb *, int (*) (sb *), char *, unsigned int, const char **);
 extern int check_macro (const char *, sb *, const char **, macro_entry **);
 extern void delete_macro (const char *);
 extern const char *expand_irp (int, int, sb *, sb *, int (*) (sb *));
diff --git a/gas/make-gas.com b/gas/make-gas.com
deleted file mode 100644
index d73917004d02..000000000000
--- a/gas/make-gas.com
+++ /dev/null
@@ -1,157 +0,0 @@
-$!make-gas.com
-$! Set the def dir to proper place for use in batch. Works for interactive to.
-$flnm = f$enviroment("PROCEDURE")     ! get current procedure name
-$set default 'f$parse(flnm,,,"DEVICE")''f$parse(flnm,,,"DIRECTORY")'
-$v = 'f$verify(0)'
-$!
-$!	Command file to build a GNU assembler on VMS
-$!
-$!	If you are using a version of GCC that supports global constants
-$!	you should remove the define="const=" from the gcc lines.
-$!
-$!	Caution:  Versions 1.38.1 and earlier had a bug in the handling of
-$!	some static constants. If you are using such a version of the
-$!	assembler, and you wish to compile without the "const=" hack,
-$!	you should first build this version *with* the "const="
-$!	definition, and then use that assembler to rebuild it without the
-$!	"const=" definition.  Failure to do this will result in an assembler
-$!	that will mung floating point constants.
-$!
-$!	Note: The version of gas shipped on the GCC VMS tapes has been patched
-$!	to fix the above mentioned bug.
-$!
-$	!The gcc-vms driver was modified to use `-1' quite some time ago,
-$	!so don't echo this text any more...
-$ !write sys$output "If this assembler is going to be used with GCC 1.n, you"
-$ !write sys$output "need to modify the driver to supply the -1 switch to gas."
-$ !write sys$output "This is required because of a small change in how global"
-$ !write sys$output "constant variables are handled.  Failure to include this"
-$ !write sys$output "will result in linker warning messages about mismatched
-$ !write sys$output "psect attributes."
-$!
-$ gas_host="vms"
-$ arch_indx = 1 + ((f$getsyi("CPU").ge.128).and.1)	! vax==1, alpha==2
-$ arch = f$element(arch_indx,"|","|VAX|Alpha|")
-$ if arch.eqs."VAX"
-$ then
-$  cpu_type="vax"
-$  obj_format="vms"
-$  atof="vax"
-$ else
-$  cpu_type="alpha"
-$  obj_format="evax"
-$  atof="ieee"
-$ endif
-$ emulation="generic"
-$!
-$	COPY	= "copy/noLog"
-$!
-$ C_DEFS :="""VMS"""
-$! C_DEFS :="""VMS""","""const="""
-$ C_INCLUDES	= "/Include=([],[.config],[-.include],[-.include.aout])"
-$ C_FLAGS	= "/noVerbose/Debug" + c_includes
-$!
-$!
-$ on error then  goto bail
-$ if f$search("[-.libiberty]liberty.olb").eqs.""
-$ then	@[-.libiberty]vmsbuild.com
-$	write sys$output "Now building gas."
-$ endif
-$ if "''p1'" .eqs. "LINK" then goto Link
-$!
-$!  This helps gcc 1.nn find the aout/* files.
-$!
-$ aout_dev = f$parse(flnm,,,"DEVICE")
-$ tmp = aout_dev - ":"
-$if f$trnlnm(tmp).nes."" then aout_dev = f$trnlnm(tmp)
-$ aout_dir = aout_dev+f$parse(flnm,,,"DIRECTORY")' -
-	- "GAS]" + "INCLUDE.AOUT.]" - "]["
-$assign 'aout_dir' aout/tran=conc
-$ opcode_dir = aout_dev+f$parse(flnm,,,"DIRECTORY")' -
-	- "GAS]" + "INCLUDE.OPCODE.]" - "]["
-$assign 'opcode_dir' opcode/tran=conc
-$!
-$ set verify
-$!
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]tc-'cpu_type'.obj [.config]tc-'cpu_type'.c
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]obj-'obj_format'.obj [.config]obj-'obj_format'.c
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]atof-'atof'.obj [.config]atof-'atof'.c
-$ gcc 'c_flags'/Define=('C_DEFS') app.c
-$ gcc 'c_flags'/Define=('C_DEFS') as.c
-$ gcc 'c_flags'/Define=('C_DEFS') atof-generic.c
-$ gcc 'c_flags'/Define=('C_DEFS') bignum-copy.c
-$ gcc 'c_flags'/Define=('C_DEFS') cond.c
-$ gcc 'c_flags'/Define=('C_DEFS') depend.c
-$ gcc 'c_flags'/Define=('C_DEFS') dwarf2dbg.c
-$ gcc 'c_flags'/Define=('C_DEFS') dw2gencfi.c
-$ gcc 'c_flags'/Define=('C_DEFS') ehopt.c
-$ gcc 'c_flags'/Define=('C_DEFS') expr.c
-$ gcc 'c_flags'/Define=('C_DEFS') flonum-konst.c
-$ gcc 'c_flags'/Define=('C_DEFS') flonum-copy.c
-$ gcc 'c_flags'/Define=('C_DEFS') flonum-mult.c
-$ gcc 'c_flags'/Define=('C_DEFS') frags.c
-$ gcc 'c_flags'/Define=('C_DEFS') hash.c
-$ gcc 'c_flags'/Define=('C_DEFS') input-file.c
-$ gcc 'c_flags'/Define=('C_DEFS') input-scrub.c
-$ gcc 'c_flags'/Define=('C_DEFS') literal.c
-$ gcc 'c_flags'/Define=('C_DEFS') messages.c
-$ gcc 'c_flags'/Define=('C_DEFS') output-file.c
-$ gcc 'c_flags'/Define=('C_DEFS') read.c
-$ gcc 'c_flags'/Define=('C_DEFS') subsegs.c
-$ gcc 'c_flags'/Define=('C_DEFS') symbols.c
-$ gcc 'c_flags'/Define=('C_DEFS') write.c
-$ gcc 'c_flags'/Define=('C_DEFS') listing.c
-$ gcc 'c_flags'/Define=('C_DEFS') ecoff.c
-$ gcc 'c_flags'/Define=('C_DEFS') stabs.c
-$ gcc 'c_flags'/Define=('C_DEFS') sb.c
-$ gcc 'c_flags'/Define=('C_DEFS') macro.c
-$link:
-$!'f$verify(0)'
-$ if f$trnlnm("IFILE$").nes."" then  close/noLog ifile$
-$ create gcc-as.opt
-!
-!	Linker options file for GNU assembler
-!
-$ open/Append ifile$ gcc-as.opt
-$ write ifile$ "tc-''cpu_type'.obj"
-$ write ifile$ "obj-''obj_format'.obj"
-$ write ifile$ "atof-''atof'.obj"
-$ COPY sys$input: ifile$:
-app.obj,-
-as.obj,-
-atof-generic.obj,-
-bignum-copy.obj,-
-cond.obj,-
-depend.obj,-
-dwarf2dbg.obj,-
-dw2gencfi.obj,-
-ehopt.obj,-
-expr.obj,-
-flonum-konst.obj,-
-flonum-copy.obj,-
-flonum-mult.obj,-
-frags.obj,-
-hash.obj,-
-input-file.obj,-
-input-scrub.obj,-
-literal.obj,-
-messages.obj,-
-output-file.obj,-
-read.obj,-
-subsegs.obj,-
-symbols.obj,-
-write.obj,-
-listing.obj,-
-ecoff.obj,-
-stabs.obj,-
-sb.obj,-
-macro.obj,-
-[-.libiberty]liberty.olb/Lib
-gnu_cc:[000000]gcclib.olb/Lib,sys$library:vaxcrtl.olb/Lib
-! Tell linker exactly what psect attributes we want -- match VAXCRTL.
-psect_attr=ENVIRON,long,pic,ovr,rel,gbl,noshr,noexe,rd,wrt
-$ close ifile$
-$ set verify=(Proc,noImag)
-$ link/noMap/Exec=gcc-as.exe gcc-as.opt/Opt,version.opt/Opt
-$!
-$bail: exit $status + 0*f$verify(v)	!'f$verify(0)'
diff --git a/gas/makefile.vms b/gas/makefile.vms
deleted file mode 100644
index 7016dce987f8..000000000000
--- a/gas/makefile.vms
+++ /dev/null
@@ -1,115 +0,0 @@
-#
-# makefile for gas
-#
-# Created by Klaus K"ampf, kkaempf@progis.de
-#
-CC=gcc
-ifeq ($(ARCH),ALPHA)
-ifeq ($(CC),gcc)
-DEFS=
-CFLAGS=/include=([],[-.bfd],[.config],[-.include],[-])$(DEFS)
-LFLAGS=
-LIBS=,GNU_CC_LIBRARY:libgcc/lib,sys$$library:vaxcrtl.olb/lib,GNU_CC_LIBRARY:crt0.obj
-else
-DEFS=/define=("table_size_of_flonum_powers_of_ten"="tabsiz_flonum_powers_of_ten",\
-"_bfd_generic_get_section_contents_in_window"="_bfd_generic_get_win_section_cont",\
-"_elf_section_from_bfd_section"="_bfd_elf_sec_from_bfd_sec","const=")
-CFLAGS=/noopt/nodebug/include=([],[-.bfd],[.config],[-.include],[-])$(DEFS)\
-/warnings=disable=(missingreturn,implicitfunc,ptrmismatch,undefescap,longextern,duptypespec)
-LFLAGS=
-LIBS=,sys$$library:vaxcrtl.olb/lib
-endif
-
-else	# ARCH not ALPHA
-
-ifeq ($(CC),gcc)
-DEFS=
-CFLAGS=/include=([],[.config],[-.include],[-])$(DEFS)
-LFLAGS=
-LIBS=,GNU_CC_LIBRARY:libgcc/lib,sys$$library:vaxcrtl.olb/lib,GNU_CC_LIBRARY:crtbegin.obj,GNU_CC_LIBRARY:crtend.obj
-#LIBS=,gnu_cc:[000000]gcclib.olb/lib,sys$$library:vaxcrtl.olb/lib
-else
-error DECC is broken on VAX
-DEFS=/define=("table_size_of_flonum_powers_of_ten"="tabsiz_flonum_powers_of_ten","const=")
-CFLAGS=/noopt/debug/include=([],[.config],[-.include],[-])$(DEFS)\
-/warnings=disable=(missingreturn,implicitfunc,ptrmismatch,undefescap,longextern,duptypespec)
-LFLAGS=
-LIBS=,sys$$library:vaxcrtl.olb/lib
-endif
-endif
-
-
-OBJS=targ-cpu.obj,obj-format.obj,atof-targ.obj,app.obj,as.obj,atof-generic.obj,\
-  bignum-copy.obj,cond.obj,depend.obj,expr.obj,flonum-konst.obj,flonum-copy.obj,\
-  flonum-mult.obj,frags.obj,hash.obj,input-file.obj,input-scrub.obj,\
-  literal.obj,messages.obj,output-file.obj,read.obj,subsegs.obj,symbols.obj,\
-  write.obj,listing.obj,ecoff.obj,stabs.obj,sb.obj,macro.obj,ehopt.obj
-
-LIBIBERTY = [-.libiberty]libiberty.olb
-
-ifeq ($(ARCH),ALPHA)
-LIBBFD = [-.bfd]libbfd.olb
-LIBOPCODES = [-.opcodes]libopcodes.olb
-BFDDEP = [-.bfd]bfd.h
-else
-LIBBFD =
-LIBOPCODES =
-BFDDEP =
-endif
-
-all: config.status $(BFDDEP) as.exe
-
-as.exe: $(OBJS) $(LIBOPCODES) $(LIBBFD) $(LIBIBERTY)
-ifeq ($(ARCH),ALPHA)
-	link$(LFLAGS)/exe=$@ $(OBJS),$(LIBOPCODES)/lib,$(LIBBFD)/lib,$(LIBIBERTY)/lib$(LIBS)
-else
-	link$(LFLAGS)/exe=$@ $(OBJS),$(LIBIBERTY)/lib$(LIBS)
-endif
-
-config.status:
-	$$ @config-gas
-
-ifeq ($(ARCH),ALPHA)
-CPU=alpha
-OBJFORMAT=evax
-FLTFORMAT=ieee
-else
-CPU=vax
-OBJFORMAT=vms
-FLTFORMAT=vax
-endif
-
-targ-cpu.c: [.config]tc-$(CPU).c
-	copy $< $@
-targ-cpu.h: [.config]tc-$(CPU).h
-	copy $< $@
-targ-env.h: [.config]te-generic.h
-	copy $< $@
-obj-format.h: [.config]obj-$(OBJFORMAT).h
-	copy $< $@
-obj-format.c: [.config]obj-$(OBJFORMAT).c
-	copy $< $@
-atof-targ.c: [.config]atof-$(FLTFORMAT).c
-	copy $< $@
-
-targ-cpu.obj: targ-cpu.c targ-cpu.h [.config]atof-vax.c
-
-[-.bfd]bfd.h:
-	$(CD) [-.bfd]
-	gmake -f makefile.vms "CC=$(CC)"
-	$(CD) [-.gas]
-
-install: as.exe
-	$(CP) $^ GNU_ROOT\:[BIN]
-
-clean:
-	$$ purge
-	$(RM) *.obj;
-	$(RM) *.exe;
-	$(RM) atof-targ.c;
-	$(RM) obj-format.c;
-	$(RM) obj-format.h;
-	$(RM) targ-env.h;
-	$(RM) targ-cpu.h;
-	$(RM) targ-cpu.c;
-	$(RM) config.status;
diff --git a/gas/messages.c b/gas/messages.c
index 005cd22d417b..b1b94cdf7c6e 100644
--- a/gas/messages.c
+++ b/gas/messages.c
@@ -1,5 +1,6 @@
 /* messages.c - error reporter -
-   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, 2003
+   Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001,
+   2003, 2004, 2005
    Free Software Foundation, Inc.
    This file is part of GAS, the GNU Assembler.
 
@@ -15,33 +16,11 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "as.h"
 
-#include <stdio.h>
-#ifdef HAVE_ERRNO_H
-#include <errno.h>
-#endif
-
-#ifdef USE_STDARG
-#include <stdarg.h>
-#endif
-
-#ifdef USE_VARARGS
-#include <varargs.h>
-#endif
-
-#if !defined (USE_STDARG) && !defined (USE_VARARGS)
-/* Roll our own.  */
-#define va_alist REST
-#define va_dcl
-typedef int * va_list;
-#define va_start(ARGS)	ARGS = &REST
-#define va_end(ARGS)
-#endif
-
 static void identify (char *);
 static void as_show_where (void);
 static void as_warn_internal (char *, unsigned int, char *);
@@ -149,16 +128,10 @@ as_perror (const char *gripe,		/* Unpunctuated error theme.  */
   as_show_where ();
   fprintf (stderr, gripe, filename);
   errno = saved_errno;
-#ifdef BFD_ASSEMBLER
   errtxt = bfd_errmsg (bfd_get_error ());
-#else
-  errtxt = xstrerror (errno);
-#endif
   fprintf (stderr, ": %s\n", errtxt);
   errno = 0;
-#ifdef BFD_ASSEMBLER
   bfd_set_error (bfd_error_no_error);
-#endif
 }
 
 /* Send to stderr a string as a warning, and locate warning
@@ -232,7 +205,7 @@ as_warn (const char *format, ...)
   if (!flag_no_warnings)
     {
       va_start (args, format);
-      vsprintf (buffer, format, args);
+      vsnprintf (buffer, sizeof (buffer), format, args);
       va_end (args);
       as_warn_internal ((char *) NULL, 0, buffer);
     }
@@ -249,7 +222,7 @@ as_warn (format, va_alist)
   if (!flag_no_warnings)
     {
       va_start (args);
-      vsprintf (buffer, format, args);
+      vsnprintf (buffer, sizeof (buffer), format, args);
       va_end (args);
       as_warn_internal ((char *) NULL, 0, buffer);
     }
@@ -270,7 +243,7 @@ as_warn_where (char *file, unsigned int line, const char *format, ...)
   if (!flag_no_warnings)
     {
       va_start (args, format);
-      vsprintf (buffer, format, args);
+      vsnprintf (buffer, sizeof (buffer), format, args);
       va_end (args);
       as_warn_internal (file, line, buffer);
     }
@@ -289,7 +262,7 @@ as_warn_where (file, line, format, va_alist)
   if (!flag_no_warnings)
     {
       va_start (args);
-      vsprintf (buffer, format, args);
+      vsnprintf (buffer, sizeof (buffer), format, args);
       va_end (args);
       as_warn_internal (file, line, buffer);
     }
@@ -331,7 +304,7 @@ as_bad (const char *format, ...)
   char buffer[2000];
 
   va_start (args, format);
-  vsprintf (buffer, format, args);
+  vsnprintf (buffer, sizeof (buffer), format, args);
   va_end (args);
 
   as_bad_internal ((char *) NULL, 0, buffer);
@@ -347,7 +320,7 @@ as_bad (format, va_alist)
   char buffer[2000];
 
   va_start (args);
-  vsprintf (buffer, format, args);
+  vsnprintf (buffer, sizeof (buffer), format, args);
   va_end (args);
 
   as_bad_internal ((char *) NULL, 0, buffer);
@@ -366,7 +339,7 @@ as_bad_where (char *file, unsigned int line, const char *format, ...)
   char buffer[2000];
 
   va_start (args, format);
-  vsprintf (buffer, format, args);
+  vsnprintf (buffer, sizeof (buffer), format, args);
   va_end (args);
 
   as_bad_internal (file, line, buffer);
@@ -384,7 +357,7 @@ as_bad_where (file, line, format, va_alist)
   char buffer[2000];
 
   va_start (args);
-  vsprintf (buffer, format, args);
+  vsnprintf (buffer, sizeof (buffer), format, args);
   va_end (args);
 
   as_bad_internal (file, line, buffer);
@@ -411,7 +384,7 @@ as_fatal (const char *format, ...)
   /* Delete the output file, if it exists.  This will prevent make from
      thinking that a file was created and hence does not need rebuilding.  */
   if (out_file_name != NULL)
-    unlink (out_file_name);
+    unlink_if_ordinary (out_file_name);
   xexit (EXIT_FAILURE);
 }
 #else
@@ -469,37 +442,96 @@ as_abort (const char *file, int line, const char *fn)
 /* Support routines.  */
 
 void
-fprint_value (FILE *file, valueT val)
+sprint_value (char *buf, valueT val)
 {
   if (sizeof (val) <= sizeof (long))
     {
-      fprintf (file, "%ld", (long) val);
+      sprintf (buf, "%ld", (long) val);
       return;
     }
-#ifdef BFD_ASSEMBLER
   if (sizeof (val) <= sizeof (bfd_vma))
     {
-      fprintf_vma (file, val);
+      sprintf_vma (buf, val);
       return;
     }
-#endif
   abort ();
 }
 
-void
-sprint_value (char *buf, valueT val)
+#define HEX_MAX_THRESHOLD	1024
+#define HEX_MIN_THRESHOLD	-(HEX_MAX_THRESHOLD)
+
+static void
+as_internal_value_out_of_range (char *    prefix,
+				offsetT   val,
+				offsetT   min,
+				offsetT   max,
+				char *    file,
+				unsigned  line,
+				int       bad)
 {
-  if (sizeof (val) <= sizeof (long))
+  const char * err;
+
+  if (prefix == NULL)
+    prefix = "";
+
+  if (   val < HEX_MAX_THRESHOLD
+      && min < HEX_MAX_THRESHOLD
+      && max < HEX_MAX_THRESHOLD
+      && val > HEX_MIN_THRESHOLD
+      && min > HEX_MIN_THRESHOLD
+      && max > HEX_MIN_THRESHOLD)
     {
-      sprintf (buf, "%ld", (long) val);
-      return;
+      /* xgettext:c-format  */
+      err = _("%s out of range (%d is not between %d and %d)");
+
+      if (bad)
+	as_bad_where (file, line, err,
+		      prefix, (int) val, (int) min, (int) max);
+      else
+	as_warn_where (file, line, err,
+		       prefix, (int) val, (int) min, (int) max);
     }
-#ifdef BFD_ASSEMBLER
-  if (sizeof (val) <= sizeof (bfd_vma))
+  else
     {
-      sprintf_vma (buf, val);
-      return;
+      char val_buf [sizeof (val) * 3 + 2];
+      char min_buf [sizeof (val) * 3 + 2];
+      char max_buf [sizeof (val) * 3 + 2];
+
+      if (sizeof (val) > sizeof (bfd_vma))
+	abort ();
+
+      sprintf_vma (val_buf, val);
+      sprintf_vma (min_buf, min);
+      sprintf_vma (max_buf, max);
+
+      /* xgettext:c-format.  */
+      err = _("%s out of range (0x%s is not between 0x%s and 0x%s)");
+
+      if (bad)
+	as_bad_where (file, line, err, prefix, val_buf, min_buf, max_buf);
+      else
+	as_warn_where (file, line, err, prefix, val_buf, min_buf, max_buf);
     }
-#endif
-  abort ();
+}
+
+void
+as_warn_value_out_of_range (char *   prefix,
+			   offsetT  value,
+			   offsetT  min,
+			   offsetT  max,
+			   char *   file,
+			   unsigned line)
+{
+  as_internal_value_out_of_range (prefix, value, min, max, file, line, 0);
+}
+
+void
+as_bad_value_out_of_range (char *   prefix,
+			   offsetT  value,
+			   offsetT  min,
+			   offsetT  max,
+			   char *   file,
+			   unsigned line)
+{
+  as_internal_value_out_of_range (prefix, value, min, max, file, line, 1);
 }
diff --git a/gas/mpw-config.in b/gas/mpw-config.in
deleted file mode 100644
index 9e29b1d945cf..000000000000
--- a/gas/mpw-config.in
+++ /dev/null
@@ -1,115 +0,0 @@
-# Configuration fragment for GAS.
-
-Set target_arch `echo {target_canonical} | sed -e 's/-.*-.*//'`
-
-If "{target_arch}" =~ /powerpc/
-	Set short_arch_name "ppc"
-	Set target_cpu "powerpc"
-Else
-	Set short_arch_name "{target_arch}"
-End If
-
-# The following works for many configurations, though not all.
-
-Set obj_format `echo {target_canonical} | sed -e 's/.*-.*-//'`
-Set target_os `echo {target_canonical} | sed -e 's/.*-.*-//'`
-
-Set bfd_gas no
-
-Set TDEFINES ""
-
-Set EXTRA_OBJECTS ""
-
-# Default emulation.
-
-Set em generic
-
-If "{target_canonical}" =~ /m68k-apple-macos/
-	Set obj_format "coff"
-	Set TDEFINES '-d M68KCOFF'
-	Set EXTRA_OBJECTS '"{o}"m68k-parse.c.o'
-
-Else If "{target_canonical}" =~ /powerpc-apple-macos/
-	Set obj_format "coff"
-	Set bfd_gas yes
-	Set em macos
-
-Else If "{target_canonical}" =~ /i386-\Option-x-go32/
-	Set obj_format "coff"
-	Set TDEFINES '-d I386COFF'
-
-Else If "{target_canonical}" =~ /m68k-\Option-x-coff/
-	Set TDEFINES '-d M68KCOFF'
-
-Else If "{target_canonical}" =~ /mips-idt-ecoff/
-	Set bfd_gas yes
-	Set TDEFINES '-d TARGET_BYTES_BIG_ENDIAN=1'
-
-Else If "{target_canonical}" =~ /mips-\Option-x-\Option-x/
-	# Assume other OSes etc use ELF
-	Set obj_format "elf"
-	Set bfd_gas yes
-	Set TDEFINES '-d TARGET_BYTES_BIG_ENDIAN=1'
-	forward-include "{srcroot}"bfd:elf-bfd.h 'bfd/elf-bfd.h'
-
-Else If "{target_canonical}" =~ /sh-\Option-x-hms/
-	Set obj_format "coff"
-	forward-include "{srcroot}"opcodes:sh-opc.h 'opcodes/sh-opc.h'
-End If
-
-forward-include "{srcdir}"config:tc-{short_arch_name}.c targ-cpu.c
-forward-include "{srcdir}"config:tc-{short_arch_name}.h targ-cpu.h
-
-forward-include "{srcdir}"config:obj-{obj_format}.c obj-format.c
-forward-include "{srcdir}"config:obj-{obj_format}.h obj-format.h
-
-forward-include "{srcdir}"config:te-{em}.h targ-env.h
-
-# Special cases for float handling.
-
-If "{target_arch}" =~ /ns32k/
-	forward-include "{srcdir}"config:atof-ns32k.c atof-targ.c
-Else If "{target_arch}" =~ /tahoe/
-	forward-include "{srcdir}"config:atof-tahoe.c atof-targ.c
-Else If "{target_arch}" =~ /vax/
-	forward-include "{srcdir}"config:atof-vax.c atof-targ.c
-Else
-	# Use IEEE by default.
-	forward-include "{srcdir}"config:atof-ieee.c atof-targ.c
-End If
-
-Echo '# From mpw-config.in'     		 > "{o}"mk.tmp
-Echo "TDEFINES = " {TDEFINES}			>> "{o}"mk.tmp
-Echo "EXTRA_OBJECTS = " {EXTRA_OBJECTS}		>> "{o}"mk.tmp
-# (We use the -n option here so as not to get extra spaces inserted)
-Echo -n 'TARG_CPU_DEP = {TARG_CPU_DEP_'		>> "{o}"mk.tmp
-Echo -n {short_arch_name}			>> "{o}"mk.tmp
-Echo -n '}'					>> "{o}"mk.tmp
-Echo '# End from mpw-config.in'			>> "{o}"mk.tmp
-
-Echo '/* conf.  Generated by mpw-configure.  */' > "{o}"conf.new
-Echo -n '#define TARGET_CPU       "'       	>> "{o}"conf.new
-Echo -n "{target_cpu}"       			>> "{o}"conf.new
-Echo    '"'       				>> "{o}"conf.new
-Echo -n '#define TARGET_OS       "'       	>> "{o}"conf.new
-Echo -n "{target_os}"       			>> "{o}"conf.new
-Echo    '"'       				>> "{o}"conf.new
-Echo -n '#define TARGET_ALIAS       "'       	>> "{o}"conf.new
-Echo -n "{target_alias}"       			>> "{o}"conf.new
-Echo    '"'       				>> "{o}"conf.new
-Echo -n '#define TARGET_CANONICAL       "'     	>> "{o}"conf.new
-Echo -n "{target_canonical}"			>> "{o}"conf.new
-Echo    '"'       				>> "{o}"conf.new
-Echo '#include "mpw.h"'				>> "{o}"conf.new
-If "{bfd_gas}" =~ /yes/
-	Echo "#define BFD_ASSEMBLER"		>> "{o}"conf.new
-Else
-	Echo "#define MANY_SEGMENTS"		>> "{o}"conf.new
-End If
-Echo '#define CR_EOL'				>> "{o}"conf.new
-Echo '#define OBJ_COFF_OMIT_TIMESTAMP'		>> "{o}"conf.new
-Echo '#define LOSING_COMPILER'			>> "{o}"conf.new
-
-MoveIfChange "{o}"conf.new "{o}"conf
-
-sed -e "s/@srcdir@/{srcdir}/" "{srcdir}"gdbinit.in > "{o}"_gdbinit
diff --git a/gas/mpw-make.sed b/gas/mpw-make.sed
deleted file mode 100644
index 3bcb0ce758f3..000000000000
--- a/gas/mpw-make.sed
+++ /dev/null
@@ -1,96 +0,0 @@
-# Sed commands that finish translating the GAS Unix Makefile to MPW syntax.
-
-/^# @target_frag@/a\
-\
-HDEFINES = \
-LOCAL_LOADLIBES = \
-
-/^srcroot = /s/^/#/
-/^target_alias = /s/^/#/
-
-/INCLUDES/s/-i "{srcdir}":\([a-z]*\)/-i "{topsrcdir}"\1/
-/INCLUDES/s/-i "{srcdir}"\.\./-i "{topsrcdir}"/
-
-/^INCLUDES = .*$/s/$/ -i "{topsrcdir}"include:mpw: -i ::extra-include:/
-
-/$(TARG_CPU_DEP_@target_cpu_type@)/s/$(TARG_CPU_DEP_@target_cpu_type@)/{TARG_CPU_DEP}/
-
-/@OPCODES_LIB@/s/@OPCODES_LIB@/::opcodes:libopcodes.o/
-/@BFDLIB@/s/@BFDLIB@/::bfd:libbfd.o/
-
-# Point at the libraries directly.
-/@OPCODES_DEP@/s/@OPCODES_DEP@/::opcodes:libopcodes.o/
-/@BFDDEP@/s/@BFDDEP@/::bfd:libbfd.o/
-
-# Don't need this.
-/@HLDFLAGS@/s/@HLDFLAGS@//
-
-/extra_objects@/s/extra_objects@/{EXTRA_OBJECTS}/
-
-/LOADLIBES/s/{LOADLIBES}/{EXTRALIBS}/
-
-/@ALL_OBJ_DEPS@/s/@ALL_OBJ_DEPS@/::bfd:bfd.h/
-
-# This causes problems - not sure why.
-/^tags TAGS/,/etags /d
-
-/^make-gas.com/s/^/#/
-
-/true/s/ ; @true$//
-
-# Remove references to conf.in, we don't need them.
-/conf\.in/s/conf\.in//g
-
-# Use _gdbinit everywhere instead of .gdbinit.
-/gdbinit/s/\.gdbinit/_gdbinit/g
-
-/atof-targ/s/"{s}"atof-targ\.c/"{o}"atof-targ.c/g
-/config/s/"{s}"config\.h/"{o}"config.h/g
-/config/s/^config\.h/"{o}"config.h/
-/obj-format/s/"{s}"obj-format\.c/"{o}"obj-format.c/g
-/obj-format/s/"{s}"obj-format\.h/"{o}"obj-format.h/g
-/targ-cpu/s/"{s}"targ-cpu\.c/"{o}"targ-cpu.c/g
-/targ-cpu/s/"{s}"targ-cpu\.h/"{o}"targ-cpu.h/g
-/targ-env/s/"{s}"targ-env\.h/"{o}"targ-env.h/g
-
-/m68k-parse.c/s/"{s}"m68k-parse\.c/"{o}"m68k-parse.c/g
-/m68k-parse.c/s/^m68k-parse\.c/"{o}"m68k-parse.c/
-
-# Whack out the config.h dependency, it only causes excess rebuilds.
-/{OBJS}/s/{OBJS} \\Option-f "{o}"config.h/{OBJS} \\Option-f/
-
-# ALL_CFLAGS includes TDEFINES, which is not desirable at link time.
-/CC_LD/s/ALL_CFLAGS/CFLAGS/g
-
-# The resource file is called mac-as.r.
-/as.new.r/s/as\.new\.r/mac-as.r/
-
-# ...and the PROG_NAME doesn't have a .new in it.
-/PROG_NAME/s/PROG_NAME='"'as.new'"'/PROG_NAME='"'as'"'/
-
-# Whack out recursive makes, they won't work.
-/^[ 	][ 	]*srcroot=/,/^[ 	][ 	]*(cd /d
-
-# Work around quoting problems by using multiple echo commands.
-/'#define GAS_VERSION "{VERSION}"'/c\
-	Echo -n '#define GAS_VERSION "' >> "{o}"config.new\
-	Echo -n "{VERSION}" >> "{o}"config.new\
-	Echo -n '"' >> "{o}"config.new
-
-# Add a "stamps" target.
-$a\
-stamps \\Option-f config-stamp\
-
-/^install \\Option-f/,/^$/c\
-install \\Option-f all install-only\
-\
-install-only \\Option-f\
-	NewFolderRecursive "{bindir}"\
-	Duplicate -y :as.new "{bindir}"as\
-
-
-# Whack out config-rebuilding targets, they won't work.
-/^Makefile \\Option-f/,/^$/d
-/^config.status \\Option-f/,/^$/d
-
-/^"{o}"config.h \\Option-f/s/^/#/
diff --git a/gas/obj.h b/gas/obj.h
index 497524ac04e9..0cceab066fcd 100644
--- a/gas/obj.h
+++ b/gas/obj.h
@@ -1,8 +1,8 @@
 /* obj.h - defines the object dependent hooks for all object
    format backends.
 
-   Copyright 1987, 1990, 1991, 1992, 1993, 1995, 1996, 1997, 1999, 2000, 2002
-   Free Software Foundation, Inc.
+   Copyright 1987, 1990, 1991, 1992, 1993, 1995, 1996, 1997, 1999, 2000,
+   2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 char *obj_default_output_file_name (void);
 void obj_emit_relocations (char **where, fixS * fixP,
@@ -29,13 +29,6 @@ void obj_emit_symbols (char **where, symbolS * symbols);
 #ifndef obj_read_begin_hook
 void obj_read_begin_hook (void);
 #endif
-#ifndef BFD_ASSEMBLER
-void obj_crawl_symbol_chain (object_headers * headers);
-void obj_header_append (char **where, object_headers * headers);
-#ifndef obj_pre_write_hook
-void obj_pre_write_hook (object_headers * headers);
-#endif
-#endif
 
 #ifndef obj_symbol_new_hook
 void obj_symbol_new_hook (symbolS * symbolP);
@@ -45,13 +38,12 @@ void obj_symbol_to_chars (char **where, symbolS * symbolP);
 
 extern const pseudo_typeS obj_pseudo_table[];
 
-#ifdef BFD_ASSEMBLER
 struct format_ops {
   int flavor;
   unsigned dfl_leading_underscore : 1;
   unsigned emit_section_symbols : 1;
   void (*begin) (void);
-  void (*app_file) (const char *);
+  void (*app_file) (const char *, int);
   void (*frob_symbol) (symbolS *, int *);
   void (*frob_file) (void);
   void (*frob_file_before_adjust) (void);
@@ -89,6 +81,5 @@ extern const struct format_ops aout_format_ops;
 #ifndef this_format
 COMMON const struct format_ops *this_format;
 #endif
-#endif
 
 /* end of obj.h */
diff --git a/gas/output-file.c b/gas/output-file.c
index 4c376b4dcc4b..f94359ab6b0a 100644
--- a/gas/output-file.c
+++ b/gas/output-file.c
@@ -1,6 +1,6 @@
 /* output-file.c -  Deal with the output file
-   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1996, 1998, 1999, 2001, 2003
-   Free Software Foundation, Inc.
+   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1996, 1998, 1999, 2001,
+   2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include <stdio.h>
 
@@ -25,18 +25,10 @@
 
 #include "output-file.h"
 
-#ifdef BFD_HEADERS
-#define USE_BFD
-#endif
-
-#ifdef BFD_ASSEMBLER
-#define USE_BFD
 #ifndef TARGET_MACH
 #define TARGET_MACH 0
 #endif
-#endif
 
-#ifdef USE_BFD
 #include "bfd.h"
 bfd *stdoutput;
 
@@ -48,14 +40,15 @@ output_file_create (char *name)
 
   else if (!(stdoutput = bfd_openw (name, TARGET_FORMAT)))
     {
-      as_perror (_("FATAL: can't create %s"), name);
+      if (bfd_get_error () == bfd_error_invalid_target)
+	as_perror (_("Selected target format '%s' unknown"), TARGET_FORMAT);
+      else
+	as_perror (_("FATAL: can't create %s"), name);
       exit (EXIT_FAILURE);
     }
 
   bfd_set_format (stdoutput, bfd_object);
-#ifdef BFD_ASSEMBLER
   bfd_set_arch_mach (stdoutput, TARGET_ARCH, TARGET_MACH);
-#endif
   if (flag_traditional_format)
     stdoutput->flags |= BFD_TRADITIONAL_FORMAT;
 }
@@ -63,7 +56,6 @@ output_file_create (char *name)
 void
 output_file_close (char *filename)
 {
-#ifdef BFD_ASSEMBLER
   /* Close the bfd.  */
   if (bfd_close (stdoutput) == 0)
     {
@@ -71,84 +63,5 @@ output_file_close (char *filename)
       as_perror (_("FATAL: can't close %s\n"), filename);
       exit (EXIT_FAILURE);
     }
-#else
-  /* Close the bfd without getting bfd to write out anything by itself.  */
-  if (bfd_close_all_done (stdoutput) == 0)
-    {
-      as_perror (_("FATAL: can't close %s\n"), filename);
-      exit (EXIT_FAILURE);
-    }
-#endif
   stdoutput = NULL;		/* Trust nobody!  */
 }
-
-#ifndef BFD_ASSEMBLER
-void
-output_file_append (char *where ATTRIBUTE_UNUSED,
-		    long length ATTRIBUTE_UNUSED,
-		    char *filename ATTRIBUTE_UNUSED)
-{
-  abort ();
-}
-#endif
-
-#else
-
-static FILE *stdoutput;
-
-void
-output_file_create (char *name)
-{
-  if (name[0] == '-' && name[1] == '\0')
-    {
-      stdoutput = stdout;
-      return;
-    }
-
-  stdoutput = fopen (name, FOPEN_WB);
-  if (stdoutput == NULL)
-    {
-#ifdef BFD_ASSEMBLER
-      bfd_set_error (bfd_error_system_call);
-#endif
-      as_perror (_("FATAL: can't create %s"), name);
-      exit (EXIT_FAILURE);
-    }
-}
-
-void
-output_file_close (char *filename)
-{
-  if (EOF == fclose (stdoutput))
-    {
-#ifdef BFD_ASSEMBLER
-      bfd_set_error (bfd_error_system_call);
-#endif
-      as_perror (_("FATAL: can't close %s"), filename);
-      exit (EXIT_FAILURE);
-    }
-
-  /* Trust nobody!  */
-  stdoutput = NULL;
-}
-
-void
-output_file_append (char * where, long length, char * filename)
-{
-  for (; length; length--, where++)
-    {
-      (void) putc (*where, stdoutput);
-
-      if (ferror (stdoutput))
-	{
-#ifdef BFD_ASSEMBLER
-	  bfd_set_error (bfd_error_system_call);
-#endif
-	  as_perror (_("Failed to emit an object byte"), filename);
-	  as_fatal (_("can't continue"));
-	}
-    }
-}
-
-#endif
-
diff --git a/gas/output-file.h b/gas/output-file.h
index 6779e4b40496..137115d5049f 100644
--- a/gas/output-file.h
+++ b/gas/output-file.h
@@ -1,6 +1,6 @@
 /* This file is output-file.h
 
-   Copyright 1987, 1988, 1989, 1990, 1991, 1992
+   Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2003
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,7 +17,7 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 void output_file_append (char *where, long length, char *filename);
 void output_file_close (char *filename);
diff --git a/gas/po/Make-in b/gas/po/Make-in
index 6176dbf78c3c..be09b4cd788b 100644
--- a/gas/po/Make-in
+++ b/gas/po/Make-in
@@ -1,7 +1,8 @@
 # Makefile for program source directory in GNU NLS utilities package.
 # Copyright (C) 1995, 1996, 1997 by Ulrich Drepper <drepper@gnu.ai.mit.edu>
+# Copyright 2003, 2006 Free Software Foundation, Inc.
 #
-# This file file be copied and used freely without restrictions.  It can
+# This file may be copied and used freely without restrictions.  It can
 # be used in projects which are not available under the GNU Public License
 # but which still want to provide support for the GNU gettext functionality.
 # Please note that the actual code is *not* freely available.
@@ -109,6 +110,7 @@ $(srcdir)/stamp-cat-id: $(PACKAGE).pot
 install: install-exec install-data
 install-exec:
 install-info:
+install-html:
 install-data: install-data-@USE_NLS@
 install-data-no: all
 install-data-yes: all
@@ -184,7 +186,7 @@ check: all
 
 cat-id-tbl.o: ../intl/libgettext.h
 
-dvi info tags TAGS ID:
+html dvi pdf ps info tags TAGS ID:
 
 mostlyclean:
 	rm -f core core.* *.pox $(PACKAGE).po *.old.po cat-id-tbl.tmp
diff --git a/gas/po/POTFILES.in b/gas/po/POTFILES.in
index e4e3e4ea6aa7..3a173a536ff3 100644
--- a/gas/po/POTFILES.in
+++ b/gas/po/POTFILES.in
@@ -1,18 +1,12 @@
 app.c
-app.c
-as.c
 as.c
 as.h
 asintl.h
 atof-generic.c
-atof-generic.c
-bignum-copy.c
-bignum-copy.c
 bignum.h
 bit_fix.h
 cgen.h
 cond.c
-cond.c
 config/e-crisaout.c
 config/e-criself.c
 config/e-i386aout.c
@@ -22,8 +16,6 @@ config/e-mipsecoff.c
 config/e-mipself.c
 config/obj-aout.c
 config/obj-aout.h
-config/obj-bout.c
-config/obj-bout.h
 config/obj-coff.c
 config/obj-coff.h
 config/obj-ecoff.c
@@ -32,16 +24,10 @@ config/obj-elf.c
 config/obj-elf.h
 config/obj-evax.c
 config/obj-evax.h
-config/obj-hp300.c
-config/obj-hp300.h
 config/obj-ieee.c
 config/obj-ieee.h
 config/obj-som.c
 config/obj-som.h
-config/obj-vms.c
-config/obj-vms.h
-config/tc-a29k.c
-config/tc-a29k.h
 config/tc-alpha.c
 config/tc-alpha.h
 config/tc-arc.c
@@ -50,8 +36,12 @@ config/tc-arm.c
 config/tc-arm.h
 config/tc-avr.c
 config/tc-avr.h
+config/tc-bfin.c
+config/tc-bfin.h
 config/tc-cris.c
 config/tc-cris.h
+config/tc-crx.c
+config/tc-crx.h
 config/tc-d10v.c
 config/tc-d10v.h
 config/tc-d30v.c
@@ -64,8 +54,6 @@ config/tc-frv.c
 config/tc-frv.h
 config/tc-h8300.c
 config/tc-h8300.h
-config/tc-h8500.c
-config/tc-h8500.h
 config/tc-hppa.c
 config/tc-hppa.h
 config/tc-i370.c
@@ -80,14 +68,14 @@ config/tc-ia64.c
 config/tc-ia64.h
 config/tc-ip2k.c
 config/tc-ip2k.h
+config/tc-m32c.c
+config/tc-m32c.h
 config/tc-m32r.c
 config/tc-m32r.h
 config/tc-m68hc11.c
 config/tc-m68hc11.h
 config/tc-m68k.c
 config/tc-m68k.h
-config/tc-m88k.c
-config/tc-m88k.h
 config/tc-mcore.c
 config/tc-mcore.h
 config/tc-mips.c
@@ -120,94 +108,69 @@ config/tc-sh.c
 config/tc-sh.h
 config/tc-sparc.c
 config/tc-sparc.h
-config/tc-tahoe.c
-config/tc-tahoe.h
 config/tc-tic30.c
 config/tc-tic30.h
 config/tc-tic54x.c
 config/tc-tic54x.h
-config/tc-tic80.c
-config/tc-tic80.h
 config/tc-v850.c
 config/tc-v850.h
 config/tc-vax.c
 config/tc-vax.h
-config/tc-w65.c
-config/tc-w65.h
+config/tc-xc16x.c
+config/tc-xc16x.h
 config/tc-xstormy16.c
 config/tc-xstormy16.h
 config/tc-xtensa.c
 config/tc-xtensa.h
+config/tc-z80.c
+config/tc-z80.h
 config/tc-z8k.c
 config/tc-z8k.h
 depend.c
-depend.c
-dw2gencfi.c
 dw2gencfi.c
 dw2gencfi.h
 dwarf2dbg.c
-dwarf2dbg.c
 dwarf2dbg.h
 ecoff.c
-ecoff.c
 ecoff.h
 ehopt.c
-ehopt.c
 emul.h
 emul-target.h
 expr.c
-expr.c
 expr.h
 flonum-copy.c
-flonum-copy.c
 flonum.h
 flonum-konst.c
-flonum-konst.c
-flonum-mult.c
 flonum-mult.c
 frags.c
-frags.c
 frags.h
 hash.c
-hash.c
 hash.h
 input-file.c
-input-file.c
 input-file.h
 input-scrub.c
-input-scrub.c
+itbl-lex.h
 itbl-ops.c
 itbl-ops.h
 listing.c
-listing.c
 listing.h
 literal.c
-literal.c
-macro.c
 macro.c
 macro.h
 messages.c
-messages.c
 obj.h
 output-file.c
-output-file.c
 output-file.h
 read.c
-read.c
 read.h
 sb.c
-sb.c
 sb.h
 stabs.c
-stabs.c
 struc-symbol.h
 subsegs.c
-subsegs.c
 subsegs.h
 symbols.c
-symbols.c
 symbols.h
 tc.h
 write.c
-write.c
 write.h
diff --git a/gas/po/es.gmo b/gas/po/es.gmo
index 9497cdb075b8..f391e490b221 100644
--- a/gas/po/es.gmo
+++ b/gas/po/es.gmo
diff --git a/gas/po/es.po b/gas/po/es.po
index 374fe0d480da..e7678f705935 100644
--- a/gas/po/es.po
+++ b/gas/po/es.po
@@ -1,84 +1,78 @@
-# Mensajes en español para gas-2.14rel030712.
-# Copyright (C) 2002, 2003 Free Software Foundation, Inc.
-# Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002, 2003.
+# Mensajes en español para gas-2.16.93.
+# Copyright (C) 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
+# Cristian Othón Martínez Vera <cfuga@itam.mx>, 2002, 2003, 2004, 2005, 2006.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: gas 2.14rel030712\n"
-"POT-Creation-Date: 2003-07-11 13:57+0930\n"
-"PO-Revision-Date: 2003-07-14 18:44-0500\n"
+"Project-Id-Version: gas 2.16.93\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2005-10-25 08:41+0930\n"
+"PO-Revision-Date: 2006-05-26 15:10-0500\n"
 "Last-Translator: Cristian Othón Martínez Vera <cfuga@itam.mx>\n"
 "Language-Team: Spanish <es@li.org>\n"
 "MIME-Version: 1.0\n"
 "Content-Type: text/plain; charset=ISO-8859-1\n"
 "Content-Transfer-Encoding: 8-bit\n"
 
-#: app.c:474 app.c:488
+#: app.c:470 app.c:484
 msgid "end of file in comment"
 msgstr "fin de fichero en el comentario"
 
-#: app.c:567
-msgid "end of file in string; inserted '\"'"
-msgstr "fin de fichero en la cadena; se insertó '\"'"
-
-#: app.c:612
-msgid "end of file in string; '\"' inserted"
-msgstr "fin de fichero en la cadena; se insertó '\"'"
+#: app.c:560 app.c:605
+#, c-format
+msgid "end of file in string; '%c' inserted"
+msgstr "fin de fichero en la cadena; se insertó '%c'"
 
-#: app.c:638
+#: app.c:631
 #, c-format
 msgid "unknown escape '\\%c' in string; ignored"
 msgstr "escape '\\%c' desconocido en la cadena; se ignora"
 
-#: app.c:790
+#: app.c:786
 msgid "end of file not at end of a line; newline inserted"
 msgstr "el fin de fichero no está al final de una línea: se insertó línea nueva"
 
-#: app.c:949
+#: app.c:945
 msgid "end of file in multiline comment"
 msgstr "fin de fichero en comentario multilíneas"
 
-#: app.c:1013
+#: app.c:1010
 msgid "end of file after a one-character quote; \\0 inserted"
 msgstr "fin de fichero después de una comilla de un carácter; se insertó \\0"
 
-#: app.c:1021
+#: app.c:1018
 msgid "end of file in escape character"
 msgstr "fin de fichero en carácter de escape"
 
-#: app.c:1033
+#: app.c:1030
 msgid "missing close quote; (assumed)"
 msgstr "falta la comilla que cierra; (se asume)"
 
-#: app.c:1101 app.c:1155 app.c:1166 app.c:1231
+#: app.c:1098 app.c:1152 app.c:1163 app.c:1228
 msgid "end of file in comment; newline inserted"
 msgstr "fin de fichero en comentario; se insertó una línea nueva"
 
-#: as.c:160
+#: as.c:161
 msgid "missing emulation mode name"
 msgstr "falta el nombre del modo de emulación"
 
-#: as.c:175
+#: as.c:176
 #, c-format
 msgid "unrecognized emulation name `%s'"
 msgstr "nombre de emulación `%s' no reconocido"
 
-#: as.c:222
-#, c-format
-msgid "GNU assembler version %s (%s) using BFD version %s"
-msgstr "GNU ensamblador versión %s (%s) utilizando BFD versión %s"
-
-#: as.c:225
+#: as.c:223
 #, c-format
-msgid "GNU assembler version %s (%s)"
-msgstr "GNU ensamblador versión %s (%s)"
+msgid "GNU assembler version %s (%s) using BFD version %s\n"
+msgstr "GNU ensamblador versión %s (%s) utilizando BFD versión %s\n"
 
-#: as.c:234
+#: as.c:230
 #, c-format
 msgid "Usage: %s [option...] [asmfile...]\n"
 msgstr "Modo de empleo: %s [opción...] [ficheroasm...]\n"
 
-#: as.c:236
+#: as.c:232
+#, c-format
 msgid ""
 "Options:\n"
 "  -a[sub-option...]\t  turn on listings\n"
@@ -94,7 +88,7 @@ msgid ""
 msgstr ""
 "Opciones:\n"
 "  -a[sub-opción...]\t  activa listados\n"
-"                      \t  Sub-opciones [por omisión hls]:\n"
+"                      \t  Sub-opciones [por defecto hls]:\n"
 "                      \t  c      omite condicionales falsos\n"
 "                      \t  d      omite directivas de depuración\n"
 "                      \t  h      incluye código de alto nivel\n"
@@ -104,112 +98,169 @@ msgstr ""
 "                      \t  s      incluye símbolos\n"
 "                      \t  =FICH  listar a FICHero (debe ser la última sub-opción)\n"
 
-#: as.c:249
+#: as.c:245
+#, c-format
+msgid "  --alternate             initially turn on alternate macro syntax\n"
+msgstr "  --alternate             activa inicialmente la sintaxis alternativa de macros\n"
+
+#: as.c:247
+#, c-format
 msgid "  -D                      produce assembler debugging messages\n"
 msgstr "  -D                      produce mensajes de depuración de ensamblador\n"
 
-#: as.c:251
+#: as.c:249
+#, c-format
 msgid "  --defsym SYM=VAL        define symbol SYM to given value\n"
 msgstr "  --defsym SIM=VAL        define el símbolo SIM al valor dado\n"
 
-#: as.c:267
+#: as.c:265
 #, c-format
 msgid "                          emulate output (default %s)\n"
-msgstr "                          emula la salida (por omisión %s)\n"
+msgstr "                          emula la salida (por defecto %s)\n"
 
-#: as.c:272
+#: as.c:270
+#, c-format
 msgid "  --execstack             require executable stack for this object\n"
 msgstr "  --execstack             requiere pila ejecutable para este objeto\n"
 
-#: as.c:274
+#: as.c:272
+#, c-format
 msgid "  --noexecstack           don't require executable stack for this object\n"
 msgstr "  --noexecstack           no requiere pila ejecutable para este objeto\n"
 
-#: as.c:277
+#: as.c:275
+#, c-format
 msgid "  -f                      skip whitespace and comment preprocessing\n"
 msgstr "  -f                      salta espacios en blanco y comentarios de preprocesamiento\n"
 
+#: as.c:277
+#, c-format
+msgid "  -g --gen-debug          generate debugging information\n"
+msgstr "  -g --gen-debug          genera información de depuración\n"
+
 #: as.c:279
-msgid "  --gstabs                generate stabs debugging information\n"
-msgstr "  --gstabs                genera información de depuración de cabos\n"
+#, c-format
+msgid "  --gstabs                generate STABS debugging information\n"
+msgstr "  --gstabs                genera información de depuración de STABS\n"
 
 #: as.c:281
-msgid "  --gdwarf2               generate DWARF2 debugging information\n"
-msgstr "  --gdwarf2               genera información de depuración DWARF2\n"
+#, c-format
+msgid "  --gstabs+               generate STABS debug info with GNU extensions\n"
+msgstr "  --gstabs+               genera información de depuración de STABS con extensiones GNU\n"
 
 #: as.c:283
+#, c-format
+msgid "  --gdwarf-2              generate DWARF2 debugging information\n"
+msgstr "  --gdwarf-2              genera información de depuración DWARF2\n"
+
+#: as.c:285
+#, c-format
+msgid "  --hash-size=<value>     set the hash table size close to <value>\n"
+msgstr "  --hash-size=<valor>     establece el tamaño de la tabla de dispersión cerca a <valor>\n"
+
+#: as.c:287
+#, c-format
 msgid "  --help                  show this message and exit\n"
 msgstr "  --help                  muestra este mensaje y termina\n"
 
-#: as.c:285
+#: as.c:289
+#, c-format
 msgid "  --target-help           show target specific options\n"
 msgstr "  --target-help           muestra las opciones específicas del objetivo\n"
 
-#: as.c:287
+#: as.c:291
+#, c-format
 msgid "  -I DIR                  add DIR to search list for .include directives\n"
 msgstr "  -I DIR                  agrega DIR a la lista de búsqueda para directivas .include\n"
 
-#: as.c:289
+#: as.c:293
+#, c-format
 msgid "  -J                      don't warn about signed overflow\n"
 msgstr "  -J                      no avisa sobre desbordamiento con signo\n"
 
-#: as.c:291
+#: as.c:295
+#, c-format
 msgid "  -K                      warn when differences altered for long displacements\n"
 msgstr "  -K                      avisa cuando hay diferencias alteradas por desubicaciones largas\n"
 
-#: as.c:293
+#: as.c:297
+#, c-format
 msgid "  -L,--keep-locals        keep local symbols (e.g. starting with `L')\n"
 msgstr "  -L,--keep-locals        conserva los símbolos locales (p.e. inician con `L')\n"
 
-#: as.c:295
+#: as.c:299
+#, c-format
 msgid "  -M,--mri                assemble in MRI compatibility mode\n"
 msgstr "  -M,--mri                ensambla en modo de compatibilidad MRI\n"
 
-#: as.c:297
+#: as.c:301
+#, c-format
 msgid "  --MD FILE               write dependency information in FILE (default none)\n"
-msgstr "  --MD FICHERO            escribe la información de dependencias en el FICHERO (por omisión ninguno)\n"
+msgstr "  --MD FICHERO            escribe la información de dependencias en el FICHERO (por defecto ninguno)\n"
 
-#: as.c:299
+#: as.c:303
+#, c-format
 msgid "  -nocpp                  ignored\n"
 msgstr "  -nocpp                  ignorado\n"
 
-#: as.c:301
+#: as.c:305
+#, c-format
 msgid "  -o OBJFILE              name the object-file output OBJFILE (default a.out)\n"
-msgstr "  -o FICHOBJ              nombra la salida del objeto fichero FICHOBJ (por omisión a.out)\n"
+msgstr "  -o FICHOBJ              nombra la salida del objeto fichero FICHOBJ (por defecto a.out)\n"
 
-#: as.c:303
+#: as.c:307
+#, c-format
 msgid "  -R                      fold data section into text section\n"
 msgstr "  -R                      pliega la sección de datos en la sección de texto\n"
 
-#: as.c:305
+#: as.c:309
+#, c-format
+msgid ""
+"  --reduce-memory-overheads \n"
+"                          prefer smaller memory use at the cost of longer\n"
+"                          assembly times\n"
+msgstr ""
+"  --reduce-memory-overheads \n"
+"                          prefiere un menor uso de memoria al costo de\n"
+"                          tiempos de ensamblado más largos\n"
+
+#: as.c:313
+#, c-format
 msgid "  --statistics            print various measured statistics from execution\n"
 msgstr "  --statistics            muestra varias estadísticas medidas de la ejecución\n"
 
-#: as.c:307
+#: as.c:315
+#, c-format
 msgid "  --strip-local-absolute  strip local absolute symbols\n"
 msgstr "  --strip-local-absolute  remueve los símbolos locales absolutos\n"
 
-#: as.c:309
+#: as.c:317
+#, c-format
 msgid "  --traditional-format    Use same format as native assembler when possible\n"
 msgstr "  --traditional-format    Usa el mismo formato que el ensamblador nativo en lo posible\n"
 
-#: as.c:311
+#: as.c:319
+#, c-format
 msgid "  --version               print assembler version number and exit\n"
 msgstr "  --version               muestra el número de versión del ensamblador y termina\n"
 
-#: as.c:313
+#: as.c:321
+#, c-format
 msgid "  -W  --no-warn           suppress warnings\n"
 msgstr "  -W  --no-warn           suprime los avisos\n"
 
-#: as.c:315
+#: as.c:323
+#, c-format
 msgid "  --warn                  don't suppress warnings\n"
 msgstr "  --warn                  no suprime los avisos\n"
 
-#: as.c:317
+#: as.c:325
+#, c-format
 msgid "  --fatal-warnings        treat warnings as errors\n"
 msgstr "  --fatal-warnings        trata los avisos como errores\n"
 
-#: as.c:319
+#: as.c:327
+#, c-format
 msgid ""
 "  --itbl INSTTBL          extend instruction set to include instructions\n"
 "                          matching the specifications defined in file INSTTBL\n"
@@ -218,19 +269,23 @@ msgstr ""
 "                          instrucciones que coincidan con las especificaciones\n"
 "                          definidas en el fichero INSTTBL\n"
 
-#: as.c:322
+#: as.c:330
+#, c-format
 msgid "  -w                      ignored\n"
 msgstr "  -w                      ignorado\n"
 
-#: as.c:324
+#: as.c:332
+#, c-format
 msgid "  -X                      ignored\n"
 msgstr "  -X                      ignorado\n"
 
-#: as.c:326
+#: as.c:334
+#, c-format
 msgid "  -Z                      generate object file even after errors\n"
 msgstr "  -Z                      genera el fichero objeto aún después de errores\n"
 
-#: as.c:328
+#: as.c:336
+#, c-format
 msgid ""
 "  --listing-lhs-width     set the width in words of the output data column of\n"
 "                          the listing\n"
@@ -238,7 +293,8 @@ msgstr ""
 "  --listing-lhs-width     establece la anchura en palabras de la columna de\n"
 "                          datos de salida en el listado\n"
 
-#: as.c:331
+#: as.c:339
+#, c-format
 msgid ""
 "  --listing-lhs-width2    set the width in words of the continuation lines\n"
 "                          of the output data column; ignored if smaller than\n"
@@ -249,7 +305,8 @@ msgstr ""
 "                          ignora si es más pequeño que la anchura de la\n"
 "                          primera línea\n"
 
-#: as.c:335
+#: as.c:343
+#, c-format
 msgid ""
 "  --listing-rhs-width     set the max width in characters of the lines from\n"
 "                          the source file\n"
@@ -257,7 +314,8 @@ msgstr ""
 "  --listing-rhs-width     establece la anchura máxima en caracteres de las\n"
 "                          líneas del fichero fuente\n"
 
-#: as.c:338
+#: as.c:346
+#, c-format
 msgid ""
 "  --listing-cont-lines    set the maximum number of continuation lines used\n"
 "                          for the output data column of the listing\n"
@@ -266,21 +324,29 @@ msgstr ""
 "                          utilizadas para la columna de datos de salida del\n"
 "                          listado\n"
 
-#: as.c:345
+#: as.c:353
 #, c-format
 msgid "Report bugs to %s\n"
 msgstr "Reportar bichos a %s\n"
 
-#: as.c:557 as.c:559
+#: as.c:553
+#, c-format
+msgid "unrecognized option -%c%s"
+msgstr "opción -%c%s no reconocida"
+
+#. This output is intended to follow the GNU standards document.
+#: as.c:591
 #, c-format
 msgid "GNU assembler %s\n"
 msgstr "GNU ensamblador %s\n"
 
-#: as.c:561
-msgid "Copyright 2002 Free Software Foundation, Inc.\n"
-msgstr "Copyright 2002 Free Software Foundation, Inc.\n"
+#: as.c:592
+#, c-format
+msgid "Copyright 2005 Free Software Foundation, Inc.\n"
+msgstr "Copyright 2005 Free Software Foundation, Inc.\n"
 
-#: as.c:562
+#: as.c:593
+#, c-format
 msgid ""
 "This program is free software; you may redistribute it under the terms of\n"
 "the GNU General Public License.  This program has absolutely no warranty.\n"
@@ -288,78 +354,82 @@ msgstr ""
 "Este programa es software libre; se puede redistribuir bajo los términos de\n"
 "la Licencia Pública General de GNU.  Este programa no tiene ninguna garantía.\n"
 
-#: as.c:565
+#: as.c:596
 #, c-format
 msgid "This assembler was configured for a target of `%s'.\n"
 msgstr "Este ensamblador se configuró para un objetivo `%s'.\n"
 
-#: as.c:572
+#: as.c:603
 msgid "multiple emulation names specified"
 msgstr "se especificaron múltiples nombres de emulación"
 
-#: as.c:574
+#: as.c:605
 msgid "emulations not handled in this configuration"
 msgstr "las emulaciones no se manejan en esta configuración"
 
-#: as.c:579
+#: as.c:610
 #, c-format
 msgid "alias = %s\n"
 msgstr "alias = %s\n"
 
-#: as.c:580
+#: as.c:611
 #, c-format
 msgid "canonical = %s\n"
 msgstr "canónico = %s\n"
 
-#: as.c:581
+#: as.c:612
 #, c-format
 msgid "cpu-type = %s\n"
 msgstr "tipo-cpu = %s\n"
 
-#: as.c:583
+#: as.c:614
 #, c-format
 msgid "format = %s\n"
 msgstr "formato = %s\n"
 
-#: as.c:586
+#: as.c:617
 #, c-format
 msgid "bfd-target = %s\n"
 msgstr "objetivo-bfd = %s\n"
 
-#: as.c:599
+#: as.c:630
 msgid "bad defsym; format is --defsym name=value"
 msgstr "defsym erróneo; el formato es --defsym nombre=valor"
 
-#: as.c:623
+#: as.c:650
 msgid "no file name following -t option"
 msgstr "no hay un nombre de fichero a continuación de la opción -t"
 
-#: as.c:638
+#: as.c:665
 #, c-format
 msgid "failed to read instruction table %s\n"
 msgstr "falló la lectura de la tabla de instrucciones %s\n"
 
-#: as.c:765
+#: as.c:832
 #, c-format
 msgid "invalid listing option `%c'"
 msgstr "opción de listado `%c' inválida"
 
-#: as.c:984
-#, c-format
-msgid "%d warnings, treating warnings as errors"
-msgstr "%d avisos, tratando los avisos como errores"
+#: as.c:885
+msgid "--hash-size needs a numeric argument"
+msgstr "--hash-size necesita un argumento numérico"
 
-#: as.c:1015
+#: as.c:910
 #, c-format
 msgid "%s: total time in assembly: %ld.%06ld\n"
 msgstr "%s: tiempo total en ensamblado: %ld.%06ld\n"
 
-#: as.c:1018
+#: as.c:913
 #, c-format
 msgid "%s: data size %ld\n"
 msgstr "%s: tamaño de datos %ld\n"
 
-#: as.h:216
+#: as.c:1175
+#, c-format
+msgid "%d warnings, treating warnings as errors"
+msgstr "%d avisos, tratando los avisos como errores"
+
+#: as.h:200
 #, c-format
 msgid "Case value %ld unexpected at line %d of file \"%s\"\n"
 msgstr "Valor de case %ld inesperado en la línea %d del fichero \"%s\"\n"
@@ -368,2320 +438,2269 @@ msgstr "Valor de case %ld inesperado en la línea %d del fichero \"%s\"\n"
 #. * We have a GROSS internal error.
 #. * This should never happen.
 #.
-#: atof-generic.c:437 config/tc-m68k.c:2869
+#: atof-generic.c:419 config/tc-m68k.c:3118
 msgid "failed sanity check"
 msgstr "falló la prueba de sanidad"
 
-#: cond.c:83
+#: cond.c:82
 msgid "invalid identifier for \".ifdef\""
 msgstr "identificador inválido para \".ifdef\""
 
-#: cond.c:151
+#: cond.c:149
 msgid "non-constant expression in \".if\" statement"
 msgstr "expresión no constante en la declaración \".if\""
 
-#: cond.c:247
+#: cond.c:276
 msgid "bad format for ifc or ifnc"
 msgstr "formato erróneo para ifc ó ifnc"
 
-#: cond.c:278
+#: cond.c:306
 msgid "\".elseif\" without matching \".if\""
 msgstr "\".elseif\" sin un \".if\" coincidente"
 
-#: cond.c:282
+#: cond.c:310
 msgid "\".elseif\" after \".else\""
 msgstr "\".elseif\" después de \".else\""
 
-#: cond.c:285 cond.c:393
+#: cond.c:313 cond.c:419
 msgid "here is the previous \"else\""
 msgstr "aquí está el \"else\" anterior"
 
-#: cond.c:288 cond.c:396
+#: cond.c:316 cond.c:422
 msgid "here is the previous \"if\""
 msgstr "aquí está el \"if\" anterior"
 
-#: cond.c:317
+#: cond.c:345
 msgid "non-constant expression in \".elseif\" statement"
 msgstr "expresión no constante en la declaración \".elseif\""
 
-#: cond.c:356
+#: cond.c:383
 msgid "\".endif\" without \".if\""
 msgstr "\".endif\" sin \".if\""
 
-#: cond.c:386
+#: cond.c:412
 msgid "\".else\" without matching \".if\""
 msgstr "\".else\" sin un \".if\" coincidente"
 
-#: cond.c:390
+#: cond.c:416
 msgid "duplicate \"else\""
 msgstr "\"else\" duplicado"
 
-#: cond.c:442
+#: cond.c:467
 msgid ".ifeqs syntax error"
 msgstr "error sintáctico .ifeqs"
 
-#: cond.c:525
+#: cond.c:548
 msgid "end of macro inside conditional"
 msgstr "fin de macro dentro de un condicional"
 
-#: cond.c:527
+#: cond.c:550
 msgid "end of file inside conditional"
 msgstr "fin de fichero dentro de un condicional"
 
-#: cond.c:530
+#: cond.c:553
 msgid "here is the start of the unterminated conditional"
 msgstr "aquí es el inicio del condicional sin terminar"
 
-#: cond.c:534
+#: cond.c:557
 msgid "here is the \"else\" of the unterminated conditional"
 msgstr "aquí está el \"else\" del condicional sin terminar"
 
-#: config/obj-aout.c:162
+#: config/obj-aout.c:85
 #, c-format
 msgid "Attempt to put a common symbol into set %s"
 msgstr "Se intentó poner un símbolo común en el conjunto %s"
 
-#: config/obj-aout.c:166
+#: config/obj-aout.c:89
 #, c-format
 msgid "Attempt to put an undefined symbol into set %s"
 msgstr "Se intentó poner un símbolo indefinido en el conjunto %s"
 
-#: config/obj-aout.c:197 config/obj-coff.c:1276
+#: config/obj-aout.c:116 config/obj-coff.c:1328
 #, c-format
 msgid "Symbol `%s' can not be both weak and common"
 msgstr "El símbolo `%s' no puede ser débil y común al mismo tiempo"
 
-#: config/obj-aout.c:255 config/obj-coff.c:2022
-msgid "unresolved relocation"
-msgstr "reubicación sin resolver"
-
-#: config/obj-aout.c:257 config/obj-coff.c:2024
-#, c-format
-msgid "bad relocation: symbol `%s' not in symbol table"
-msgstr "reubicación errónea: el símbolo `%s' no está en la tabla de símbolos"
-
-#: config/obj-aout.c:344
-#, c-format
-msgid "%s: bad type for weak symbol"
-msgstr "%s: tipo erróneo para un símbolo débil"
-
-#: config/obj-aout.c:458 config/obj-coff.c:2945 write.c:1931
-#, c-format
-msgid "%s: global symbols not supported in common sections"
-msgstr "%s: los símbolos globales no tienen soporte en las secciones comunes"
-
-#: config/obj-aout.c:524
-#, c-format
-msgid "Local symbol %s never defined."
-msgstr "El símbolo local %s nunca se definió."
-
-#: config/obj-bout.c:319 config/obj-vms.c:629
-#, c-format
-msgid "Local symbol %s never defined"
-msgstr "El símbolo local %s nunca se definió"
-
-#: config/obj-coff.c:166
+#: config/obj-coff.c:133
 #, c-format
 msgid "Inserting \"%s\" into structure table failed: %s"
 msgstr "Falló la inserción de \"%s\" en la tabla de estructuras: %s"
 
 #. Zero is used as an end marker in the file.
-#: config/obj-coff.c:469
+#: config/obj-coff.c:354
 msgid "Line numbers must be positive integers\n"
 msgstr "Los números de línea deben ser enteros positivos\n"
 
-#. Wrong context.
-#: config/obj-coff.c:503 config/obj-coff.c:2367
+#: config/obj-coff.c:386
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr "pseudo-operador .ln dentro de .def/.endef: ignorado."
 
-#: config/obj-coff.c:546 ecoff.c:3278
+#: config/obj-coff.c:428 ecoff.c:3240
 msgid ".loc outside of .text"
 msgstr ".loc fuera de .text"
 
-#: config/obj-coff.c:553
+#: config/obj-coff.c:435
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr "pseudo-operador .loc dentro de .def/.endef: ignorado."
 
-#: config/obj-coff.c:641 config/obj-coff.c:2419
+#: config/obj-coff.c:516
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr "pseudo-operador .def usado dentro de .def/.endef: ignorado."
 
-#: config/obj-coff.c:687 config/obj-coff.c:2471
+#: config/obj-coff.c:555
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr "pseudo-operador .endef usado fuera de .def/.endef: ignorado."
 
-#: config/obj-coff.c:725
+#: config/obj-coff.c:594
 #, c-format
 msgid "`%s' symbol without preceding function"
 msgstr "símbolo `%s' sin una función precedente"
 
-#: config/obj-coff.c:812 config/obj-coff.c:2551
+#: config/obj-coff.c:681
 #, c-format
 msgid "unexpected storage class %d"
 msgstr "clase de almacenamiento %d inesperada"
 
-#: config/obj-coff.c:925 config/obj-coff.c:2658
+#: config/obj-coff.c:790
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr "pseudo-operador .dim usado fuera de .def/.endef: ignorado."
 
-#: config/obj-coff.c:945 config/obj-coff.c:2678
+#: config/obj-coff.c:810
 msgid "badly formed .dim directive ignored"
 msgstr "directiva .dim formada erróneamente ignorada"
 
-#: config/obj-coff.c:996 config/obj-coff.c:2738
+#: config/obj-coff.c:859
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr "pseudo-operador .size usado fuera de .def/.endef ignorado."
 
-#: config/obj-coff.c:1012 config/obj-coff.c:2754
+#: config/obj-coff.c:874
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr "pseudo-operador .scl usado fuera de .def/.endef ignorado."
 
-#: config/obj-coff.c:1030 config/obj-coff.c:2772
+#: config/obj-coff.c:891
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr "pseudo-operador .tag usado fuera de .def/.endef ignorado."
 
-#: config/obj-coff.c:1049 config/obj-coff.c:2789
+#: config/obj-coff.c:909
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr "no se encontró una marca para .tag %s"
 
-#: config/obj-coff.c:1064 config/obj-coff.c:2803
+#: config/obj-coff.c:922
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr "pseudo-operador .type usado fuera de .def/.endef ignorado."
 
-#: config/obj-coff.c:1086 config/obj-coff.c:2823
+#: config/obj-coff.c:941
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr "pseudo-operador .val usado fuera de .def/.endef ignorado."
 
-#: config/obj-coff.c:1233 config/obj-coff.c:3016
+#: config/obj-coff.c:1108
+msgid "badly formed .weak directive ignored"
+msgstr "directiva .weak formada erróneamente ignorada"
+
+#: config/obj-coff.c:1286
 msgid "mismatched .eb"
 msgstr ".eb sin coincidencia"
 
-#: config/obj-coff.c:1254 config/obj-coff.c:3054
-msgid "C_EFCN symbol out of scope"
-msgstr "símbolo C_EFCN fuera de ámbito"
+#: config/obj-coff.c:1307
+#, c-format
+msgid "C_EFCN symbol for %s out of scope"
+msgstr "símbolo C_EFCN para %s fuera de ámbito"
 
 #. STYP_INFO
 #. STYP_LIB
 #. STYP_OVER
-#: config/obj-coff.c:1482
+#: config/obj-coff.c:1533
 #, c-format
 msgid "unsupported section attribute '%c'"
 msgstr "atributo de sección '%c' sin soporte"
 
-#: config/obj-coff.c:1487 config/obj-coff.c:3759 config/tc-ppc.c:4508
+#: config/obj-coff.c:1538 config/tc-ppc.c:4610
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr "atributo de sección '%c' desconocido"
 
-#: config/obj-coff.c:1517 config/tc-ppc.c:4526 config/tc-tic54x.c:4339
-#: read.c:2562
+#: config/obj-coff.c:1568 config/tc-ppc.c:4628 config/tc-tic54x.c:4287
+#: read.c:2551
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr "error al establecer las opciones para \"%s\": %s"
 
-#: config/obj-coff.c:1528
+#: config/obj-coff.c:1579
 #, c-format
 msgid "Ignoring changed section attributes for %s"
 msgstr "Ignorando los atributos de sección cambiados para %s"
 
-#: config/obj-coff.c:1664
+#: config/obj-coff.c:1710
 #, c-format
 msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
 msgstr "0x%lx: \"%s\" tipo = %ld, clase = %d, segmento = %d\n"
 
-#: config/obj-coff.c:1849 config/obj-ieee.c:69
-msgid "Out of step\n"
-msgstr "Fuera del paso\n"
-
-#: config/obj-coff.c:2286
-msgid "bfd_coff_swap_scnhdr_out failed"
-msgstr "falló bfd_coff_swap_scnhdr_out"
-
-#: config/obj-coff.c:2507
-msgid "`.bf' symbol without preceding function\n"
-msgstr "símbolo `.bf' sin una función precedente\n"
-
-#: config/obj-coff.c:3457 config/obj-ieee.c:521
-#, c-format
-msgid "FATAL: Can't create %s"
-msgstr "FATAL: No se puede crear %s"
-
-#: config/obj-coff.c:3635
-#, c-format
-msgid "Can't close %s: %s"
-msgstr "No se puede cerrar %s: %s"
-
-#: config/obj-coff.c:3669
-#, c-format
-msgid "Too many new sections; can't add \"%s\""
-msgstr "Demasiadas secciones nuevas; no se puede agregar \"%s\""
-
-#: config/obj-coff.c:4057 config/tc-sparc.c:3635
-msgid "Expected comma after name"
-msgstr "Se esperaba una coma después del nombre"
-
-#: config/obj-coff.c:4063
-msgid "Missing size expression"
-msgstr "Falta una expresión de tamaño"
-
-#: config/obj-coff.c:4069
-#, c-format
-msgid "lcomm length (%d.) <0! Ignored."
-msgstr "¡longitud de lcomm (%d.) <0! Ignorada."
-
-#: config/obj-coff.c:4097
-#, c-format
-msgid "Symbol %s already defined"
-msgstr "El símbolo %s ya está definido"
-
-#: config/obj-coff.c:4193 config/tc-i960.c:3221
-#, c-format
-msgid "No 'bal' entry point for leafproc %s"
-msgstr "No hay un punto de entrada 'bal' para el proceso hoja %s"
-
-#: config/obj-coff.c:4270
-#, c-format
-msgid "Negative of non-absolute symbol %s"
-msgstr "Negativo de un símbolo %s que no es absoluto"
-
-#: config/obj-coff.c:4290
-msgid "callj to difference of 2 symbols"
-msgstr "callj para diferenciar a 2 símbolos"
-
-#: config/obj-coff.c:4334
-#, c-format
-msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
-msgstr "No se puede emitir la reubicación {- %s-seg símbolo \"%s\"} @ dirección del fichero %ld."
-
-#: config/obj-coff.c:4420 config/tc-i960.c:2844
-msgid "can't use COBR format with external label"
-msgstr "no se puede utilizar el formato COBR con una etiqueta externa"
-
-#: config/obj-coff.c:4493
-#, c-format
-msgid "Value of %ld too large for field of %d bytes at 0x%lx"
-msgstr "El valor de %ld es demasiado grande para el campo de %d bytes en 0x%lx"
-
-#: config/obj-coff.c:4507
-#, c-format
-msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
-msgstr "Desbordamiento con signo de .word; el interruptor puede ser demasiado grande; %ld en 0x%lx"
-
-#: config/obj-ecoff.c:192
+#: config/obj-ecoff.c:125
 msgid "Can't set GP value"
 msgstr "No se puede establecer el valor GP"
 
-#: config/obj-ecoff.c:199
+#: config/obj-ecoff.c:132
 msgid "Can't set register masks"
 msgstr "No se pueden establecer las máscaras de registro"
 
-#: config/obj-elf.c:316
-msgid "expected comma after symbol-name"
-msgstr "se esperaba una coma después del nombre del símbolo"
-
-#: config/obj-elf.c:326
-#, c-format
-msgid ".COMMon length (%ld) out of range, ignored."
-msgstr "longitud .COMMún (%ld) fuera de rango, se ignora."
-
-#: config/obj-elf.c:335 ecoff.c:3397 read.c:1406 read.c:1507 read.c:2145
-#: read.c:2234 read.c:2863 read.c:4968 symbols.c:367 symbols.c:466
-#, c-format
-msgid "symbol `%s' is already defined"
-msgstr "el símbolo `%s' ya está definido"
-
-#: config/obj-elf.c:343
-#, c-format
-msgid "length of .comm \"%s\" is already %ld; not changed to %ld"
-msgstr "la longitud de .comm \"%s\" ya es %ld; no se cambia a %ld"
-
-#: config/obj-elf.c:367
-msgid "common alignment negative; 0 assumed"
-msgstr "alineación común negativa; se asume 0"
-
-#: config/obj-elf.c:386
-msgid "common alignment not a power of 2"
-msgstr "la alineación común no es una potencia de 2"
-
-#: config/obj-elf.c:449 config/tc-sparc.c:3931 config/tc-v850.c:461
+#: config/obj-elf.c:318 config/tc-sparc.c:3973 config/tc-v850.c:451
 #, c-format
 msgid "bad .common segment %s"
 msgstr "segmento .common %s erróneo"
 
-#: config/obj-elf.c:717
+#: config/obj-elf.c:596
 #, c-format
 msgid "setting incorrect section type for %s"
 msgstr "se establece un tipo de sección incorrecto para %s"
 
-#: config/obj-elf.c:721
+#: config/obj-elf.c:601
 #, c-format
 msgid "ignoring incorrect section type for %s"
 msgstr "se ignora un tipo de sección incorrecto para %s"
 
-#: config/obj-elf.c:734
+#: config/obj-elf.c:638
 #, c-format
 msgid "setting incorrect section attributes for %s"
 msgstr "se establecen atributos de sección incorrectos para %s"
 
-#: config/obj-elf.c:786
+#: config/obj-elf.c:690
+#, c-format
+msgid "ignoring changed section type for %s"
+msgstr "se ignoran el tipo de sección cambiado para %s"
+
+#: config/obj-elf.c:702
 #, c-format
 msgid "ignoring changed section attributes for %s"
 msgstr "se ignoran los atributos de sección cambiados para %s"
 
-#: config/obj-elf.c:788
+#: config/obj-elf.c:704
 #, c-format
 msgid "ignoring changed section entity size for %s"
 msgstr "se ignoran el tamaño de entidad de sección cambiado para %s"
 
-#: config/obj-elf.c:791
-#, c-format
-msgid "ignoring new section group for %s"
-msgstr "se ignora un grupo de sección nuevo para %s"
-
-#: config/obj-elf.c:845
+#: config/obj-elf.c:757
 msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
 msgstr "atributo de .section no reconocido: se quiere a,w,x,M,S,G,T"
 
-#: config/obj-elf.c:884
+#: config/obj-elf.c:794
 msgid "unrecognized section attribute"
 msgstr "atributo de sección no reconocido"
 
-#: config/obj-elf.c:906 read.c:2545
+#: config/obj-elf.c:822 read.c:2535
 msgid "unrecognized section type"
 msgstr "tipo de sección no reconocido"
 
-#: config/obj-elf.c:936
+#: config/obj-elf.c:852
 msgid "missing name"
 msgstr "falta un nombre"
 
-#: config/obj-elf.c:1048
+#: config/obj-elf.c:963
 msgid "invalid merge entity size"
 msgstr "tamaño de entidad de mezcla inválido"
 
-#: config/obj-elf.c:1055
+#: config/obj-elf.c:970
 msgid "entity size for SHF_MERGE not specified"
 msgstr "no se especificó el tamaño de entidad para SHF_MERGE"
 
-#: config/obj-elf.c:1075
+#: config/obj-elf.c:990
 msgid "group name for SHF_GROUP not specified"
 msgstr "no se especificó el tamaño de entidad para SHF_GROUP"
 
-#: config/obj-elf.c:1088
+#: config/obj-elf.c:1003
 msgid "character following name is not '#'"
 msgstr "el carácter a continuación del nombre no es '#'"
 
-#: config/obj-elf.c:1189
+#: config/obj-elf.c:1118
 msgid ".previous without corresponding .section; ignored"
 msgstr ".previous sin .section correspondiente; ignorado"
 
-#: config/obj-elf.c:1216
+#: config/obj-elf.c:1144
 msgid ".popsection without corresponding .pushsection; ignored"
 msgstr ".popsection sin .pushsection correspondiente; ignorado"
 
-#: config/obj-elf.c:1270
+#: config/obj-elf.c:1196
 msgid "expected comma after name in .symver"
 msgstr "se esperaba una coma después del nombre en .symver"
 
-#: config/obj-elf.c:1294
+#: config/obj-elf.c:1220
 #, c-format
 msgid "missing version name in `%s' for symbol `%s'"
 msgstr "falta el nombre de versión en `%s' para el símbolo `%s'"
 
-#: config/obj-elf.c:1305
+#: config/obj-elf.c:1231
 #, c-format
 msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
 msgstr "versiones múltiples [`%s'|`%s'] para el símbolo `%s'"
 
-#: config/obj-elf.c:1541
+#: config/obj-elf.c:1461
 msgid "expected quoted string"
 msgstr "se esperaba una cadena entre comillas"
 
-#: config/obj-elf.c:1562
+#: config/obj-elf.c:1481
 #, c-format
 msgid "expected comma after name `%s' in .size directive"
 msgstr "se esperaba una coma después del nombre `%s' en la directiva .size"
 
-#: config/obj-elf.c:1571
+#: config/obj-elf.c:1490
 msgid "missing expression in .size directive"
 msgstr "falta una expresión en la directiva .size"
 
-#: config/obj-elf.c:1660
+#: config/obj-elf.c:1577
 #, c-format
 msgid "unrecognized symbol type \"%s\""
 msgstr "tipo de símbolo \"%s\" no reconocido"
 
-#: config/obj-elf.c:1841
+#: config/obj-elf.c:1745
 msgid ".size expression too complicated to fix up"
 msgstr "la expresión .size es demasiado complicada para componerla"
 
-#: config/obj-elf.c:1873
+#: config/obj-elf.c:1777
 #, c-format
 msgid "invalid attempt to declare external version name as default in symbol `%s'"
-msgstr "intento inválido de declarar un nombre de versión externo como valor por omisión en el símbolo `%s'"
+msgstr "intento inválido de declarar un nombre de versión externo como valor por defecto en el símbolo `%s'"
 
-#: config/obj-elf.c:1934 ecoff.c:3642
+#: config/obj-elf.c:1838 ecoff.c:3598
 #, c-format
 msgid "symbol `%s' can not be both weak and common"
 msgstr "el símbolo `%s' no puede ser débil y común al mismo tiempo"
 
-#: config/obj-elf.c:2054
+#: config/obj-elf.c:1945
 #, c-format
 msgid "assuming all members of group `%s' are COMDAT"
 msgstr "se asume que todos los miembros del grupo `%s' son COMDAT"
 
-#: config/obj-elf.c:2076
+#: config/obj-elf.c:1967
 #, c-format
 msgid "can't create group: %s"
 msgstr "no se puede crear un grupo: %s"
 
-#: config/obj-elf.c:2183
+#: config/obj-elf.c:2076
 #, c-format
 msgid "failed to set up debugging information: %s"
 msgstr "falló al establecer la información de depuración: %s"
 
-#: config/obj-elf.c:2203
+#: config/obj-elf.c:2096
 #, c-format
 msgid "can't start writing .mdebug section: %s"
 msgstr "no se puede iniciar la escritura de la sección .mdebug: %s"
 
-#: config/obj-elf.c:2211
+#: config/obj-elf.c:2104
 #, c-format
 msgid "could not write .mdebug section: %s"
 msgstr "no se puede escribir la sección .mdebug: %s"
 
-#: config/obj-ieee.c:455
+#: config/obj-elf.h:140
+#, c-format
+msgid "can't allocate ELF private section data: %s"
+msgstr "no se puede crear la sección de datos privados ELF: %s"
+
+#: config/obj-ieee.c:69
+#, c-format
+msgid "Out of step\n"
+msgstr "Fuera del paso\n"
+
+#: config/obj-ieee.c:449
 msgid "too many sections"
 msgstr "demasiadas secciones"
 
-#: config/obj-som.c:138
+#: config/obj-ieee.c:511
+#, c-format
+msgid "FATAL: Can't create %s"
+msgstr "FATAL: No se puede crear %s"
+
+#: config/obj-som.c:129
 msgid "Only one .version pseudo-op per file!"
 msgstr "¡Sólo un pseudo-operador .version por fichero!"
 
-#: config/obj-som.c:155 config/obj-som.c:201
+#: config/obj-som.c:146 config/obj-som.c:191
 msgid "Expected quoted string"
 msgstr "Se esperaba una cadena entre comillas"
 
-#: config/obj-som.c:164
+#: config/obj-som.c:155
 #, c-format
 msgid "FATAL: Attaching version header %s"
 msgstr "FATAL: Adjuntando el encabezado de versión %s"
 
-#: config/obj-som.c:184
+#: config/obj-som.c:174
 msgid "Only one .copyright pseudo-op per file!"
 msgstr "¡Sólo un pseudo-operador .copyright por fichero!"
 
-#: config/obj-som.c:210
+#: config/obj-som.c:200
 #, c-format
 msgid "FATAL: Attaching copyright header %s"
 msgstr "FATAL: Adjuntando el encabezado de copyright %s"
 
-#: config/obj-vms.c:530
-#, c-format
-msgid "compiler emitted zero-size common symbol `%s' already defined"
-msgstr "el símbolo común de tamaño cero emitido por el compilador `%s' ya está definido"
-
-#: config/obj-vms.c:540
-#, c-format
-msgid "compiler redefined zero-size common symbol `%s'"
-msgstr "símbolo común de tamaño cero `%s' redefinido por el compilador"
-
-#: config/obj-vms.c:663
-#, c-format
-msgid "Couldn't create VMS object file \"%s\""
-msgstr "No se puede crear el fichero objeto VMS \"%s\""
-
-#: config/obj-vms.c:688
-msgid "I/O error writing VMS object file (length prefix)"
-msgstr "Error de E/S al escribir el fichero objeto VMS (longitud del prefijo)"
-
-#: config/obj-vms.c:702
-msgid "I/O error writing VMS object file"
-msgstr "Error de E/S al escribir el fichero objeto VMS"
-
-#: config/obj-vms.c:1292
-#, c-format
-msgid "Couldn't find source file \"%s\", dUmMy=%%X%x"
-msgstr "No se puede encontrar el fichero fuente \"%s\", estado=%%X%x"
-
-#: config/obj-vms.c:1790 config/obj-vms.c:2967
-#, c-format
-msgid "debugger forward reference error, dbx type %d"
-msgstr "error de referencia hacia adelante del depurador, tipo dbx %d"
-
-#: config/obj-vms.c:1865
-#, c-format
-msgid "Variable descriptor %d too complicated.  Defined as `void *'."
-msgstr "El descriptor de variable %d es demasiado complicado.  Se define como `void *'."
-
-#: config/obj-vms.c:2179
-msgid ""
-"***Warning - the assembly code generated by the compiler has placed \n"
-" global constant(s) in the text psect.  These will not be available to \n"
-" other modules, since this is not the correct way to handle this. You \n"
-" have two options: 1) get a patched compiler that does not put global \n"
-" constants in the text psect, or 2) remove the 'const' keyword from \n"
-" definitions of global variables in your source module(s).  Don't say \n"
-" I didn't warn you! \n"
-msgstr ""
-"***Aviso - el código ensamblador generado por el compilador ha colocado \n"
-" constante(s) global(es) en la psect de texto.  Éstas no estarán disponibles \n"
-" para otros módulos, ya que no es la forma correcta de manejarlo. Tiene \n"
-" dos opciones: 1) obtener un compilador parchado que no coloque constantes \n"
-" globales en la psect de texto, o 2) quitar la palabra clave 'const' de \n"
-" las definiciones de las variables globales en el(los) módulo(s) fuente. \n"
-" ¡No diga que no se le advirtió! \n"
-
-#: config/obj-vms.c:2494
-#, c-format
-msgid "debugginer output: %d is an unknown untyped variable."
-msgstr "salida del depurador: %d es una variable sin tipo desconocido."
-
-#: config/obj-vms.c:2712
-#, c-format
-msgid "debugger output: structure element `%s' has undefined type"
-msgstr "salida del depurador: el elmento de la estructura `%s' tiene un tipo indefinido"
-
-#: config/obj-vms.c:2823
-#, c-format
-msgid "debugger output: %d is an unknown type of variable."
-msgstr "salida del depurador: %d es un tipo desconocido de variable."
-
-#: config/obj-vms.c:2956
-#, c-format
-msgid "debugger output: Unable to resolve %d circular references."
-msgstr "salida del depurador: No se pueden resolver %d referencias circulares."
-
-#: config/obj-vms.c:3158
-#, c-format
-msgid "Module name truncated: %s\n"
-msgstr "Nombre de módulo truncado: %s\n"
-
-#: config/obj-vms.c:3436
-#, c-format
-msgid "Symbol %s replaced by %s\n"
-msgstr "El símbolo %s se reemplazó por %s\n"
-
-#. impossible
-#: config/obj-vms.c:3719
-#, c-format
-msgid "Unknown VMS psect type (%ld)"
-msgstr "Tipo psect VMS desconocido (%ld)"
-
-#: config/obj-vms.c:3760
-#, c-format
-msgid "Globalsymbol attribute for symbol %s was unexpected."
-msgstr "El atributo de globalsymbol para el símbolo %s era inesperado."
-
-#: config/obj-vms.c:3909
-msgid "Invalid data type for globalvalue"
-msgstr "Tipo de dato inválido para globalvalue"
-
-#: config/obj-vms.c:3921
-#, c-format
-msgid "Invalid globalvalue of %s"
-msgstr "Globalvalue inválido de %s"
-
-#: config/obj-vms.c:4271
-msgid "Couldn't find fixup fragment when checking for indirect reference"
-msgstr "No se puede encontrar el fragmento de compostura al revisar por referencias indirectas"
-
-#: config/obj-vms.c:4614 config/obj-vms.c:4757
-msgid "Fixup data addsy and subsy don't have the same type"
-msgstr "Los datos de compostura addsy y subsy no tienen el mismo tipo"
-
-#: config/obj-vms.c:4618 config/obj-vms.c:4761
-msgid "Fixup data addsy and subsy don't have an appropriate type"
-msgstr "Los datos de compostura addsy y subsy no tienen un tipo apropiado"
-
-#: config/obj-vms.c:4621 config/obj-vms.c:4764
-msgid "Fixup data is erroneously \"pcrel\""
-msgstr "Los datos de compostura son \"pcrel\" erróneamente"
-
-#: config/obj-vms.c:4637 config/obj-vms.c:4783
-msgid "Fixup datum is not a longword"
-msgstr "El dato de compostura no es un longword"
-
-#: config/obj-vms.c:4641 config/obj-vms.c:4787
-msgid "Fixup datum is not \"fixP->fx_addsy\""
-msgstr "El dato de compostura no es \"fixP->fx_addsy\""
-
-#: config/obj-vms.c:4858
-#, c-format
-msgid ""
-"g++ wrote an extern reference to `%s' as a routine.\n"
-"I will fix it, but I hope that it was note really a routine."
-msgstr ""
-"g++ escribió una referencia externa a `%s' como una rutina.\n"
-"Se compondrá, pero se espera que no sea realmente una rutina."
-
-#: config/obj-vms.c:4990
-msgid "Can't handle global xtors symbols yet."
-msgstr "No se pueden manejar símbolos xtors globales aún."
-
-#: config/obj-vms.c:4993
-#, c-format
-msgid "Unknown %s"
-msgstr "%s desconocido"
-
-#.
-#. *	Error otherwise.
-#.
-#: config/obj-vms.c:5078
-#, c-format
-msgid "unhandled stab type %d"
-msgstr "tipo de cabo %d sin manejar"
-
-#: config/tc-a29k.c:163 config/tc-sparc.c:3983
-msgid "Unknown segment type"
-msgstr "Tipo de segmento desconocido"
-
-#. Probably a memory allocation problem?  Give up now.
-#: config/tc-a29k.c:333 config/tc-dlx.c:369 config/tc-hppa.c:1463
-#: config/tc-mips.c:1107 config/tc-mips.c:1149 config/tc-or32.c:228
-#: config/tc-sparc.c:853
-msgid "Broken assembler.  No assembly attempted."
-msgstr "Ensamblador descompuesto.  No se intentó ensamblar."
-
-#: config/tc-a29k.c:378 config/tc-avr.c:1121 config/tc-d10v.c:545
-#: config/tc-d30v.c:551 config/tc-h8300.c:492 config/tc-h8500.c:283
-#: config/tc-mcore.c:607 config/tc-mmix.c:470 config/tc-mn10200.c:940
-#: config/tc-mn10300.c:1815 config/tc-msp430.c:1544 config/tc-or32.c:334
-#: config/tc-or32.c:390 config/tc-ppc.c:2334 config/tc-s390.c:1236
-#: config/tc-sh.c:1264 config/tc-sh64.c:2254 config/tc-tic80.c:279
-#: config/tc-v850.c:2025 config/tc-w65.c:218 config/tc-z8k.c:376
-msgid "missing operand"
-msgstr "operando faltante"
-
-#: config/tc-a29k.c:417 config/tc-cris.c:1075 config/tc-cris.c:1083
-#: config/tc-dlx.c:834 config/tc-hppa.c:1599 config/tc-i860.c:453
-#: config/tc-i860.c:470 config/tc-i860.c:930 config/tc-sparc.c:1415
-#: config/tc-sparc.c:1421
-#, c-format
-msgid "Unknown opcode: `%s'"
-msgstr "Código de operación desconocido: `%s'"
-
-#: config/tc-a29k.c:422 config/tc-dlx.c:852
-#, c-format
-msgid "Unknown opcode `%s'."
-msgstr "Código de operación desconocido `%s'."
-
-#: config/tc-a29k.c:454 config/tc-dlx.c:913
-#, c-format
-msgid "Too many operands: %s"
-msgstr "Demasiados operandos: %s"
-
-#: config/tc-a29k.c:476 config/tc-a29k.c:507
-#, c-format
-msgid "Immediate value of %ld is too large"
-msgstr "El valor inmediato de %ld es demasiado grande"
-
-#: config/tc-a29k.c:546 config/tc-i860.c:355 config/tc-i860.c:902
-#: config/tc-m68k.c:3171 config/tc-m68k.c:3200 config/tc-sparc.c:2647
-msgid "failed sanity check."
-msgstr "falló la prueba de sanidad."
-
-#: config/tc-a29k.c:892 config/tc-or32.c:1044 config/tc-or32.c:1178
-#, c-format
-msgid "bad relocation type: 0x%02x"
-msgstr "tipo de reubicación erróneo: 0x%02x"
-
-#: config/tc-a29k.c:919
-#, c-format
-msgid "need %o3\n"
-msgstr "se necesita %o3\n"
-
-#: config/tc-a29k.c:935
-msgid "a29k_convert_frag\n"
-msgstr "a29k_convert_frag\n"
-
-#: config/tc-a29k.c:944
-msgid "a29k_estimate_size_before_relax\n"
-msgstr "a29k_estimate_size_before_relax\n"
-
-#: config/tc-a29k.c:1095 config/tc-dlx.c:1283 config/tc-or32.c:1373
-#, c-format
-msgid "label \"$%d\" redefined"
-msgstr "se redefinió la etiqueta \"$%d\""
-
-#: config/tc-a29k.c:1168 config/tc-dlx.c:511 config/tc-or32.c:1466
-#, c-format
-msgid "Invalid expression after %%%%\n"
-msgstr "Expresión inválida después de %%%%\n"
-
-#: config/tc-a29k.c:1179
-msgid "Invalid register in & expression"
-msgstr "Registro inválido en la expresión &"
-
-#: config/tc-alpha.c:826
-#, c-format
-msgid "internal error: can't hash opcode `%s': %s"
-msgstr "error interno: no se puede dispersar el código de operación `%s': %s"
-
-#: config/tc-alpha.c:860
-#, c-format
-msgid "internal error: can't hash macro `%s': %s"
-msgstr "error interno: no se puede dispersar la macro `%s': %s"
-
-#: config/tc-alpha.c:943 config/tc-i960.c:2707 config/tc-xtensa.c:4954
-#: config/tc-xtensa.c:5015
-msgid "syntax error"
-msgstr "error sintáctico"
-
-#: config/tc-alpha.c:1017 config/tc-h8300.c:2099 config/tc-h8500.c:1204
-#: config/tc-hppa.c:4018 config/tc-i860.c:1004 config/tc-m68hc11.c:568
-#: config/tc-m68k.c:4196 config/tc-m88k.c:991 config/tc-ns32k.c:1689
-#: config/tc-or32.c:910 config/tc-sparc.c:2934 config/tc-z8k.c:1371
-msgid "Bad call to MD_ATOF()"
-msgstr "Llamada errónea a MD_ATOF()"
-
-#: config/tc-alpha.c:1067
-#, c-format
-msgid "Unknown CPU identifier `%s'"
-msgstr "Identificador de CPU `%s' desconocido"
-
-#: config/tc-alpha.c:1111
-msgid ""
-"Alpha options:\n"
-"-32addr\t\t\ttreat addresses as 32-bit values\n"
-"-F\t\t\tlack floating point instructions support\n"
-"-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n"
-"\t\t\tspecify variant of Alpha architecture\n"
-"-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n"
-"\t\t\tthese variants include PALcode opcodes\n"
-msgstr ""
-"Opciones Alpha:\n"
-"-32addr\t\t\ttrata direcciones como valores de 32-bit\n"
-"-F\t\t\tfalta el soporte de instrucciones de coma flotante\n"
-"-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n"
-"\t\t\tespecifica variante de la arquitectura Alpha\n"
-"-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n"
-"\t\t\testas variantes incluyen códigos de operación PALcode\n"
-
-#: config/tc-alpha.c:1121
-msgid ""
-"VMS options:\n"
-"-+\t\t\thash encode (don't truncate) names longer than 64 characters\n"
-"-H\t\t\tshow new symbol after hash truncation\n"
-msgstr ""
-"Opciones VMS:\n"
-"-+\t\t\tcodificar por dispersión (no truncar) nombres más largos que 64 caracteres\n"
-"-H\t\t\tmostrar el símbolo nuevo después del truncado por dispersión\n"
-
-#: config/tc-alpha.c:1298
-#, c-format
-msgid "unhandled relocation type %s"
-msgstr "tipo de reubicación %s sin manejar"
-
-#: config/tc-alpha.c:1311
-msgid "non-absolute expression in constant field"
-msgstr "expresión no absoluta en campo constante"
-
-#: config/tc-alpha.c:1325
-#, c-format
-msgid "type %d reloc done?\n"
-msgstr "¿tipo %d de reubicación hecha?\n"
-
-#: config/tc-alpha.c:1373 config/tc-alpha.c:1380 config/tc-mips.c:8602
-msgid "Used $at without \".set noat\""
-msgstr "Se usó $at sin \".set noat\""
-
-#: config/tc-alpha.c:1542
-#, c-format
-msgid "!samegp reloc against symbol without .prologue: %s"
-msgstr "reubicación !samegp contra un símbolo sin .prologue: %s"
-
-#: config/tc-alpha.c:1581 config/tc-xtensa.c:5451
-#, c-format
-msgid "cannot represent `%s' relocation in object file"
-msgstr "no se puede representar la reubicación `%s' en el fichero objeto"
-
-#: config/tc-alpha.c:1588 config/tc-xtensa.c:5458
-#, c-format
-msgid "internal error? cannot generate `%s' relocation"
-msgstr "¿error interno? no se puede generar la reubicación `%s'"
-
-#: config/tc-alpha.c:1642
-#, c-format
-msgid "frame reg expected, using $%d."
-msgstr "se esperaba un marco de registro, se usa $%d."
-
-#: config/tc-alpha.c:1743
+#: config/tc-alpha.c:592
 #, c-format
 msgid "No !literal!%ld was found"
 msgstr "No se encontró una !literal!%ld"
 
-#: config/tc-alpha.c:1750
+#: config/tc-alpha.c:599
 #, c-format
 msgid "No !tlsgd!%ld was found"
 msgstr "No se encontró un !tlsgd!%ld"
 
-#: config/tc-alpha.c:1757
+#: config/tc-alpha.c:606
 #, c-format
 msgid "No !tlsldm!%ld was found"
 msgstr "No se encontró un !tlsldm!%ld"
 
-#: config/tc-alpha.c:1766
+#: config/tc-alpha.c:615
 #, c-format
 msgid "No ldah !gpdisp!%ld was found"
 msgstr "No se encontró un ldah !gpdisp!%ld"
 
-#: config/tc-alpha.c:1816
+#: config/tc-alpha.c:665
 #, c-format
 msgid "too many !literal!%ld for %s"
 msgstr "demasiados !literal!%ld para %s"
 
-#: config/tc-alpha.c:1846
+#: config/tc-alpha.c:695
 #, c-format
 msgid "No lda !gpdisp!%ld was found"
 msgstr "No se encontró un lda !gpdisp!%ld"
 
 #. Only support one relocation op per insn.
-#: config/tc-alpha.c:1994
+#: config/tc-alpha.c:852
 msgid "More than one relocation op per insn"
 msgstr "Más de un operador de reubicación por insn"
 
-#: config/tc-alpha.c:2010
+#: config/tc-alpha.c:868
 msgid "No relocation operand"
 msgstr "No hay un operando de reubicación"
 
-#: config/tc-alpha.c:2020
+#: config/tc-alpha.c:878
 #, c-format
 msgid "Unknown relocation operand: !%s"
 msgstr "Operando de reubicación desconocido: !%s"
 
-#: config/tc-alpha.c:2030
+#: config/tc-alpha.c:888
 #, c-format
 msgid "no sequence number after !%s"
 msgstr "no hay un número de secuencia después de !%s"
 
-#: config/tc-alpha.c:2040
+#: config/tc-alpha.c:898
 #, c-format
 msgid "!%s does not use a sequence number"
 msgstr "!%s no utiliza un número de secuencia"
 
-#: config/tc-alpha.c:2050
+#: config/tc-alpha.c:908
 #, c-format
 msgid "Bad sequence number: !%s!%s"
 msgstr "Secuencia de números errónea: !%s!%s"
 
-#: config/tc-alpha.c:2378
+#: config/tc-alpha.c:1123 config/tc-alpha.c:3139
 #, c-format
-msgid "operand out of range (%s not between %d and %d)"
-msgstr "operador fuera de rango (%s no está entre %d y %d)"
+msgid "inappropriate arguments for opcode `%s'"
+msgstr "argumentos inapropiados para el código de operación `%s'"
 
-#: config/tc-alpha.c:2490 config/tc-alpha.c:2514 config/tc-d10v.c:634
-#: config/tc-d30v.c:639 config/tc-mn10200.c:995 config/tc-mn10300.c:1888
-#: config/tc-ppc.c:2300 config/tc-ppc.c:2517 config/tc-ppc.c:2529
-#: config/tc-s390.c:1246 config/tc-s390.c:1346 config/tc-s390.c:1442
-#: config/tc-v850.c:1805 config/tc-v850.c:1828 config/tc-v850.c:2048
-msgid "too many fixups"
-msgstr "demasiadas composturas"
+#: config/tc-alpha.c:1125 config/tc-alpha.c:3141
+#, c-format
+msgid "opcode `%s' not supported for target %s"
+msgstr "el código de operación `%s' no tiene soporte para el objetivo %s"
 
-#: config/tc-alpha.c:2526
-msgid "invalid relocation for instruction"
-msgstr "reubicación inválida para la instrucción"
+#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1221
+#: config/tc-msp430.c:1870
+#, c-format
+msgid "unknown opcode `%s'"
+msgstr "código de operación `%s' desconocido"
 
-#: config/tc-alpha.c:2537
-msgid "invalid relocation for field"
-msgstr "reubicación inválida para el campo"
+#: config/tc-alpha.c:1209 config/tc-alpha.c:1384
+msgid "overflow in literal (.lita) table"
+msgstr "desbordamiento en la tabla (.lita) literal"
+
+#: config/tc-alpha.c:1216 config/tc-alpha.c:1240 config/tc-alpha.c:1397
+#: config/tc-alpha.c:2049 config/tc-alpha.c:2093 config/tc-alpha.c:2162
+#: config/tc-alpha.c:2245 config/tc-alpha.c:2470 config/tc-alpha.c:2568
+msgid "macro requires $at register while noat in effect"
+msgstr "la macro requiere el registro $at mientras noat está en efecto"
 
-#: config/tc-alpha.c:2642
+#: config/tc-alpha.c:1218 config/tc-alpha.c:1242 config/tc-alpha.c:1399
+msgid "macro requires $at while $at in use"
+msgstr "la macro requiere $at mientras $at está en uso"
+
+#: config/tc-alpha.c:1346
+msgid "bignum invalid; zero assumed"
+msgstr "bignum inválido; se asume cero"
+
+#: config/tc-alpha.c:1348
+msgid "floating point number invalid; zero assumed"
+msgstr "número de coma flotante inválido; se asume cero"
+
+#: config/tc-alpha.c:1353
+msgid "can't handle expression"
+msgstr "no se puede manejar la expresión"
+
+#: config/tc-alpha.c:1390
+msgid "overflow in literal (.lit8) table"
+msgstr "desbordamiento en la tabla (.lit8) literal"
+
+#: config/tc-alpha.c:1674
 #, c-format
 msgid "too many ldah insns for !gpdisp!%ld"
 msgstr "demasiadas instrucciones ldah para !gpdisp!%ld"
 
-#: config/tc-alpha.c:2644 config/tc-alpha.c:2656
+#: config/tc-alpha.c:1676 config/tc-alpha.c:1688
 #, c-format
 msgid "both insns for !gpdisp!%ld must be in the same section"
 msgstr "ambas instrucciones para !gpdisp!%ld deben estar en la misma sección"
 
-#: config/tc-alpha.c:2654
+#: config/tc-alpha.c:1686
 #, c-format
 msgid "too many lda insns for !gpdisp!%ld"
 msgstr "demasiadas instrucciones lda para !gpdisp!%ld"
 
-#: config/tc-alpha.c:2707
+#: config/tc-alpha.c:1742
 #, c-format
 msgid "too many lituse insns for !lituse_tlsgd!%ld"
 msgstr "demasiadas instrucciones lituse para !lituse_tlsgd!%ld"
 
-#: config/tc-alpha.c:2710
+#: config/tc-alpha.c:1745
 #, c-format
 msgid "too many lituse insns for !lituse_tlsldm!%ld"
 msgstr "demasiadas instrucciones lituse para !lituse_tlsldm!%ld"
 
-#: config/tc-alpha.c:2727
+#: config/tc-alpha.c:1762
 #, c-format
 msgid "duplicate !tlsgd!%ld"
 msgstr "!tlsgd!%ld duplicado"
 
-#: config/tc-alpha.c:2729
+#: config/tc-alpha.c:1764
 #, c-format
 msgid "sequence number in use for !tlsldm!%ld"
 msgstr "número de secuencia en uso para !tlsldm!%ld"
 
-#: config/tc-alpha.c:2743
+#: config/tc-alpha.c:1778
 #, c-format
 msgid "duplicate !tlsldm!%ld"
 msgstr "!tlsldm!%ld duplicado"
 
-#: config/tc-alpha.c:2745
+#: config/tc-alpha.c:1780
 #, c-format
 msgid "sequence number in use for !tlsgd!%ld"
 msgstr "número de secuencia en uso para !tlsgd!%ld"
 
-#: config/tc-alpha.c:2790 config/tc-alpha.c:2863
-#, c-format
-msgid "inappropriate arguments for opcode `%s'"
-msgstr "argumentos inapropiados para el código de operación `%s'"
+#: config/tc-alpha.c:1823 config/tc-arc.c:294 config/tc-mn10200.c:889
+#: config/tc-mn10300.c:2600 config/tc-ppc.c:1476 config/tc-s390.c:614
+#: config/tc-v850.c:1573
+msgid "operand"
+msgstr "operando"
+
+#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:585
+#: config/tc-d30v.c:573 config/tc-mn10200.c:1133 config/tc-mn10300.c:1893
+#: config/tc-ppc.c:2348 config/tc-ppc.c:2565 config/tc-ppc.c:2577
+#: config/tc-s390.c:1230 config/tc-s390.c:1330 config/tc-s390.c:1459
+#: config/tc-v850.c:1747 config/tc-v850.c:1770 config/tc-v850.c:1973
+msgid "too many fixups"
+msgstr "demasiadas composturas"
 
-#: config/tc-alpha.c:2792 config/tc-alpha.c:2865
-#, c-format
-msgid "opcode `%s' not supported for target %s"
-msgstr "el código de operación `%s' no tiene soporte para el objetivo %s"
+#: config/tc-alpha.c:1962
+msgid "invalid relocation for instruction"
+msgstr "reubicación inválida para la instrucción"
 
-#: config/tc-alpha.c:2796 config/tc-alpha.c:2869 config/tc-avr.c:1087
-#: config/tc-msp430.c:446
-#, c-format
-msgid "unknown opcode `%s'"
-msgstr "código de operación `%s' desconocido"
+#: config/tc-alpha.c:1973
+msgid "invalid relocation for field"
+msgstr "reubicación inválida para el campo"
 
-#: config/tc-alpha.c:2916
+#: config/tc-alpha.c:2760
 msgid "can not resolve expression"
 msgstr "no se puede resolver la expresión"
 
-#: config/tc-alpha.c:3060 config/tc-alpha.c:3239
-msgid "overflow in literal (.lita) table"
-msgstr "desbordamiento en la tabla (.lita) literal"
-
-#: config/tc-alpha.c:3067 config/tc-alpha.c:3090 config/tc-alpha.c:3252
-#: config/tc-alpha.c:3467 config/tc-alpha.c:3512 config/tc-alpha.c:3586
-#: config/tc-alpha.c:3678 config/tc-alpha.c:3926 config/tc-alpha.c:4025
-msgid "macro requires $at register while noat in effect"
-msgstr "la macro requiere el registro $at mientras noat está en efecto"
-
-#: config/tc-alpha.c:3069 config/tc-alpha.c:3092 config/tc-alpha.c:3254
-msgid "macro requires $at while $at in use"
-msgstr "la macro requiere $at mientras $at está en uso"
-
-#: config/tc-alpha.c:3200
-msgid "bignum invalid; zero assumed"
-msgstr "bignum inválido; se asume cero"
-
-#: config/tc-alpha.c:3202
-msgid "floating point number invalid; zero assumed"
-msgstr "número de coma flotante inválido; se asume cero"
-
-#: config/tc-alpha.c:3207
-msgid "can't handle expression"
-msgstr "no se puede manejar la expresión"
-
-#: config/tc-alpha.c:3245
-msgid "overflow in literal (.lit8) table"
-msgstr "desbordamiento en la tabla (.lit8) literal"
-
-#: config/tc-alpha.c:4262 config/tc-ppc.c:1740 config/tc-ppc.c:4271
+#: config/tc-alpha.c:3275 config/tc-ppc.c:1781 config/tc-ppc.c:4373
 #, c-format
 msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr "¡longitud de .COMM (%ld.) <0! Ignorada."
 
-#: config/tc-alpha.c:4291 config/tc-sparc.c:3799 config/tc-v850.c:256
+#: config/tc-alpha.c:3304 config/tc-sparc.c:3843 config/tc-v850.c:246
 msgid "Ignoring attempt to re-define symbol"
 msgstr "Se ignora el intento de redefinir el símbolo"
 
-#: config/tc-alpha.c:4300 config/tc-alpha.c:4309 config/tc-ppc.c:4308
+#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4410
+#: config/tc-sparc.c:3851
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr "La longitud de .comm \"%s\" ya es %ld. No se cambia a %ld."
 
-#: config/tc-alpha.c:4430 ecoff.c:3082
+#: config/tc-alpha.c:3439 ecoff.c:3054
 msgid ".ent directive has no name"
 msgstr "la directiva .ent no tiene nombre"
 
-#: config/tc-alpha.c:4438
+#: config/tc-alpha.c:3447
 msgid "nested .ent directives"
 msgstr "directivas .ent anidadas"
 
-#: config/tc-alpha.c:4483 ecoff.c:3032
+#: config/tc-alpha.c:3491 ecoff.c:3005
 msgid ".end directive has no name"
 msgstr "la directiva .end no tiene nombre"
 
-#: config/tc-alpha.c:4492
+#: config/tc-alpha.c:3500
 msgid ".end directive without matching .ent"
 msgstr "directiva .end sin una directiva .ent coincidente"
 
-#: config/tc-alpha.c:4494
+#: config/tc-alpha.c:3502
 msgid ".end directive names different symbol than .ent"
 msgstr "la directiva .end nombra un símbolo diferente de .ent"
 
-#: config/tc-alpha.c:4538 ecoff.c:3171
+#: config/tc-alpha.c:3545 ecoff.c:3140
 msgid ".fmask outside of .ent"
 msgstr ".fmask fuera de .ent"
 
-#: config/tc-alpha.c:4540 ecoff.c:3241
+#: config/tc-alpha.c:3547 ecoff.c:3204
 msgid ".mask outside of .ent"
 msgstr ".mask fuera de .ent"
 
-#: config/tc-alpha.c:4548 ecoff.c:3178
+#: config/tc-alpha.c:3555 ecoff.c:3147
 msgid "bad .fmask directive"
 msgstr "directiva .fmask errónea"
 
-#: config/tc-alpha.c:4550 ecoff.c:3248
+#: config/tc-alpha.c:3557 ecoff.c:3211
 msgid "bad .mask directive"
 msgstr "directiva .mask errónea"
 
-#: config/tc-alpha.c:4584 config/tc-mips.c:14142 ecoff.c:3200
+#: config/tc-alpha.c:3590 config/tc-mips.c:14022 ecoff.c:3168
 msgid ".frame outside of .ent"
 msgstr ".frame fuera de .ent"
 
-#: config/tc-alpha.c:4595 ecoff.c:3211
+#: config/tc-alpha.c:3601 ecoff.c:3179
 msgid "bad .frame directive"
 msgstr "directiva .frame errónea"
 
-#: config/tc-alpha.c:4628
+#: config/tc-alpha.c:3633
 msgid ".prologue directive without a preceding .ent directive"
 msgstr "directiva .prolog sin una directiva .ent precedente"
 
-#: config/tc-alpha.c:4646
+#: config/tc-alpha.c:3651
 #, c-format
 msgid "Invalid argument %d to .prologue."
 msgstr "Argumento inválido %d para .prologue."
 
-#: config/tc-alpha.c:4741
+#: config/tc-alpha.c:3742
 msgid "ECOFF debugging is disabled."
 msgstr "La depuración ECOFF está desactivada."
 
-#: config/tc-alpha.c:4755
+#: config/tc-alpha.c:3756
 msgid ".ent directive without matching .end"
 msgstr "directiva .ent sin una directiva .end coincidente"
 
-#: config/tc-alpha.c:4840
+#: config/tc-alpha.c:3841
 msgid ".usepv directive has no name"
 msgstr "la directiva .usepv no tiene nombre"
 
-#: config/tc-alpha.c:4851
+#: config/tc-alpha.c:3852
 msgid ".usepv directive has no type"
 msgstr "la directiva .usepv no tiene tipo"
 
-#: config/tc-alpha.c:4866
+#: config/tc-alpha.c:3867
 msgid "unknown argument for .usepv"
 msgstr "argumento desconocido para .usepv"
 
-#: config/tc-alpha.c:4900
+#: config/tc-alpha.c:3900
 msgid "Unknown section directive"
 msgstr "Directiva de sección desconocida"
 
-#: config/tc-alpha.c:4936
+#: config/tc-alpha.c:3935
 msgid ".ent directive has no symbol"
 msgstr "la directiva .ent no tiene símbolo"
 
-#: config/tc-alpha.c:4963
+#: config/tc-alpha.c:3960
 msgid "Bad .frame directive 1./2. param"
 msgstr "Parámetro 1./2. de directiva .frame erróneo"
 
-#: config/tc-alpha.c:4975
+#: config/tc-alpha.c:3972
 msgid "Bad .frame directive 3./4. param"
 msgstr "Parámetro 3./4. de directiva .frame erróneo"
 
-#: config/tc-alpha.c:5000
+#: config/tc-alpha.c:3994
 msgid ".pdesc directive not in link (.link) section"
 msgstr "la directiva .pdesc no está en la sección de enlace (.link)"
 
-#: config/tc-alpha.c:5008
+#: config/tc-alpha.c:4002
 msgid ".pdesc has no matching .ent"
 msgstr ".pdesc no tiene un .ent coincidente"
 
-#: config/tc-alpha.c:5019
+#: config/tc-alpha.c:4013
 msgid ".pdesc directive has no entry symbol"
 msgstr "la directiva .pdesc no tiene un símbolo de entrada"
 
-#: config/tc-alpha.c:5032
+#: config/tc-alpha.c:4026
 msgid "No comma after .pdesc <entryname>"
 msgstr "No hay una coma después de .pdesc <nombreentrada>"
 
-#: config/tc-alpha.c:5055
+#: config/tc-alpha.c:4046
 msgid "unknown procedure kind"
 msgstr "tipo de procedimiento desconocido"
 
-#: config/tc-alpha.c:5148
+#: config/tc-alpha.c:4136
 msgid ".name directive not in link (.link) section"
 msgstr "la directiva .name no está en la sección de enlace (.link)"
 
-#: config/tc-alpha.c:5156
+#: config/tc-alpha.c:4144
 msgid ".name directive has no symbol"
 msgstr "la directiva .name no tiene símbolo"
 
-#: config/tc-alpha.c:5190
+#: config/tc-alpha.c:4175
 msgid "No symbol after .linkage"
 msgstr "No hay un símbolo después de .linkage"
 
-#: config/tc-alpha.c:5218
+#: config/tc-alpha.c:4199
 msgid "No symbol after .code_address"
 msgstr "No hay un símbolo después de .code_address"
 
-#: config/tc-alpha.c:5251
+#: config/tc-alpha.c:4226
 msgid "Bad .mask directive"
 msgstr "Directiva .mask errónea"
 
-#: config/tc-alpha.c:5272
+#: config/tc-alpha.c:4244
 msgid "Bad .fmask directive"
 msgstr "Directiva .fmask errónea"
 
-#: config/tc-alpha.c:5440
+#: config/tc-alpha.c:4401
 #, c-format
 msgid "Expected comma after name \"%s\""
 msgstr "Se esperaba una coma después del nombre \"%s\""
 
 #. *symbol_get_obj (symbolP) = (signed char) temp;
-#: config/tc-alpha.c:5451
+#: config/tc-alpha.c:4412
 #, c-format
 msgid "unhandled: .proc %s,%d"
 msgstr "sin manejar: .proc %s,%d"
 
-#: config/tc-alpha.c:5486
+#: config/tc-alpha.c:4446
 #, c-format
 msgid "Tried to .set unrecognized mode `%s'"
 msgstr "Se intento hacer .set del modo `%s' no reconocido"
 
-#. not fatal, but it might not work in the end
-#: config/tc-alpha.c:5503
-msgid "File overrides no-base-register option."
-msgstr "El fichero se impone a la opción no-base-register."
-
-#: config/tc-alpha.c:5520
+#: config/tc-alpha.c:4472
 #, c-format
 msgid "Bad base register, using $%d."
 msgstr "Registro base erróneo, utilizando $%d."
 
-#: config/tc-alpha.c:5542
+#: config/tc-alpha.c:4493
 #, c-format
 msgid "Alignment too large: %d. assumed"
 msgstr "Alineación demasiado grande: se asume %d."
 
-#: config/tc-alpha.c:5546 config/tc-d30v.c:2200
+#: config/tc-alpha.c:4497 config/tc-d30v.c:2083
 msgid "Alignment negative: 0 assumed"
 msgstr "Alineación negativa: se asume 0"
 
-#: config/tc-alpha.c:5860
+#: config/tc-alpha.c:4775
 #, c-format
 msgid "Chose GP value of %lx\n"
 msgstr "Valor GP escogido de %lx\n"
 
-#: config/tc-alpha.c:5876
+#: config/tc-alpha.c:4789
 msgid "Bad .section directive: want a,s,w,x,M,S,G,T in string"
 msgstr "Directiva .section errónea: se quiere a,s,w,x,M,S,G,T en la cadena"
 
-#: config/tc-arc.c:1615 config/tc-arm.c:11416 config/tc-ip2k.c:221
+#: config/tc-alpha.c:4878
+#, c-format
+msgid "internal error: can't hash opcode `%s': %s"
+msgstr "error interno: no se puede dispersar el código de operación `%s': %s"
+
+#: config/tc-alpha.c:4914
+#, c-format
+msgid "internal error: can't hash macro `%s': %s"
+msgstr "error interno: no se puede dispersar la macro `%s': %s"
+
+#: config/tc-alpha.c:4998 config/tc-i960.c:710 config/tc-xtensa.c:5112
+#: config/tc-xtensa.c:5181 config/tc-xtensa.c:5227
+msgid "syntax error"
+msgstr "error sintáctico"
+
+#: config/tc-alpha.c:5067 config/tc-h8300.c:2055 config/tc-hppa.c:4041
+#: config/tc-i860.c:1059 config/tc-m68hc11.c:558 config/tc-m68k.c:4524
+#: config/tc-ns32k.c:1945 config/tc-or32.c:579 config/tc-sparc.c:2944
+#: config/tc-z8k.c:1310
+msgid "Bad call to MD_ATOF()"
+msgstr "Llamada errónea a MD_ATOF()"
+
+#: config/tc-alpha.c:5116
+#, c-format
+msgid "Unknown CPU identifier `%s'"
+msgstr "Identificador de CPU `%s' desconocido"
+
+#: config/tc-alpha.c:5159
+msgid ""
+"Alpha options:\n"
+"-32addr\t\t\ttreat addresses as 32-bit values\n"
+"-F\t\t\tlack floating point instructions support\n"
+"-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n"
+"\t\t\tspecify variant of Alpha architecture\n"
+"-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n"
+"\t\t\tthese variants include PALcode opcodes\n"
+msgstr ""
+"Opciones Alpha:\n"
+"-32addr\t\t\ttrata direcciones como valores de 32-bit\n"
+"-F\t\t\tfalta el soporte de instrucciones de coma flotante\n"
+"-mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall\n"
+"\t\t\tespecifica variante de la arquitectura Alpha\n"
+"-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n"
+"\t\t\testas variantes incluyen códigos de operación PALcode\n"
+
+#: config/tc-alpha.c:5169
+msgid ""
+"VMS options:\n"
+"-+\t\t\thash encode (don't truncate) names longer than 64 characters\n"
+"-H\t\t\tshow new symbol after hash truncation\n"
+msgstr ""
+"Opciones VMS:\n"
+"-+\t\t\tcodificar por dispersión (no truncar) nombres más largos que 64 caracteres\n"
+"-H\t\t\tmostrar el símbolo nuevo después del truncado por dispersión\n"
+
+#: config/tc-alpha.c:5346
+#, c-format
+msgid "unhandled relocation type %s"
+msgstr "tipo de reubicación %s sin manejar"
+
+#: config/tc-alpha.c:5359
+msgid "non-absolute expression in constant field"
+msgstr "expresión no absoluta en campo constante"
+
+#: config/tc-alpha.c:5373
+#, c-format
+msgid "type %d reloc done?\n"
+msgstr "¿tipo %d de reubicación hecha?\n"
+
+#: config/tc-alpha.c:5420 config/tc-alpha.c:5427 config/tc-mips.c:8657
+msgid "Used $at without \".set noat\""
+msgstr "Se usó $at sin \".set noat\""
+
+#: config/tc-alpha.c:5589
+#, c-format
+msgid "!samegp reloc against symbol without .prologue: %s"
+msgstr "reubicación !samegp contra un símbolo sin .prologue: %s"
+
+#: config/tc-alpha.c:5626 config/tc-xtensa.c:5739
+#, c-format
+msgid "cannot represent `%s' relocation in object file"
+msgstr "no se puede representar la reubicación `%s' en el fichero objeto"
+
+#: config/tc-alpha.c:5632 config/tc-xtensa.c:5747
+#, c-format
+msgid "internal error? cannot generate `%s' relocation"
+msgstr "¿error interno? no se puede generar la reubicación `%s'"
+
+#: config/tc-alpha.c:5683
+#, c-format
+msgid "frame reg expected, using $%d."
+msgstr "se esperaba un marco de registro, se usa $%d."
+
+#: config/tc-arc.c:1077 config/tc-ip2k.c:249
 msgid "md_estimate_size_before_relax\n"
 msgstr "md_estimate_size_before_relax\n"
 
-#: config/tc-arc.c:1627
+#: config/tc-arc.c:1088
 msgid "md_convert_frag\n"
 msgstr "md_convert_frag\n"
 
 #. We can't actually support subtracting a symbol.
-#: config/tc-arc.c:1898 config/tc-arm.c:6617 config/tc-arm.c:9705
-#: config/tc-arm.c:9805 config/tc-avr.c:854 config/tc-cris.c:3123
-#: config/tc-d10v.c:1710 config/tc-d30v.c:1851 config/tc-mips.c:3629
-#: config/tc-mips.c:4694 config/tc-mips.c:5827 config/tc-mips.c:6516
-#: config/tc-msp430.c:1403 config/tc-ppc.c:5460 config/tc-v850.c:2357
-#: config/tc-xstormy16.c:483
+#: config/tc-arc.c:1288 config/tc-arm.c:1021 config/tc-arm.c:5764
+#: config/tc-arm.c:5815 config/tc-arm.c:6614 config/tc-arm.c:7256
+#: config/tc-arm.c:7284 config/tc-arm.c:7536 config/tc-arm.c:7553
+#: config/tc-arm.c:7674 config/tc-avr.c:970 config/tc-cris.c:3928
+#: config/tc-d10v.c:1539 config/tc-d30v.c:1938 config/tc-mips.c:3794
+#: config/tc-mips.c:4902 config/tc-mips.c:5834 config/tc-mips.c:6428
+#: config/tc-msp430.c:1979 config/tc-ppc.c:5562 config/tc-v850.c:2274
+#: config/tc-xstormy16.c:484
 msgid "expression too complex"
 msgstr "expresión demasiado compleja"
 
-#: config/tc-arm.c:763
+#: config/tc-arm.c:352
 msgid "ARM register expected"
 msgstr "se esperaba un registro ARM"
 
-#: config/tc-arm.c:764 config/tc-arm.c:3174
+#: config/tc-arm.c:353
 msgid "bad or missing co-processor number"
 msgstr "número de co-procesador erróneo o faltante"
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:765 config/tc-arm.c:3229
+#: config/tc-arm.c:354
 msgid "co-processor register expected"
 msgstr "se esperaba un registro de co-procesador"
 
-#: config/tc-arm.c:766
+#: config/tc-arm.c:355
 msgid "FPA register expected"
 msgstr "se esperaba un registro FPA"
 
-#: config/tc-arm.c:767
+#: config/tc-arm.c:356
 msgid "VFP single precision register expected"
 msgstr "Se esperaba un registro de precisión simple VFP"
 
-#: config/tc-arm.c:768
+#: config/tc-arm.c:357
 msgid "VFP double precision register expected"
 msgstr "Se esperaba un registro de precisión doble VFP"
 
-#: config/tc-arm.c:769
+#: config/tc-arm.c:358
+msgid "VFP system register expected"
+msgstr "se esperaba un registro de sistema VFP"
+
+#: config/tc-arm.c:359
 msgid "Maverick MVF register expected"
 msgstr "se esperaba un registro Maverick MVF"
 
-#: config/tc-arm.c:770
+#: config/tc-arm.c:360
 msgid "Maverick MVD register expected"
 msgstr "se esperaba un registro Maverick MVD"
 
-#: config/tc-arm.c:771 config/tc-arm.c:772
+#: config/tc-arm.c:361
 msgid "Maverick MVFX register expected"
 msgstr "se esperaba un registro Maverick MVFX"
 
-#: config/tc-arm.c:773
+#: config/tc-arm.c:362
+msgid "Maverick MVDX register expected"
+msgstr "se esperaba un registro Maverick MVDX"
+
+#: config/tc-arm.c:363
 msgid "Maverick MVAX register expected"
 msgstr "se esperaba un registro Maverick MVAX"
 
-#: config/tc-arm.c:774
+#: config/tc-arm.c:364
 msgid "Maverick DSPSC register expected"
 msgstr "se esperaba un registro Maverick DSPSC"
 
-#: config/tc-arm.c:775
-msgid "Intel Wireless MMX technology register expected"
-msgstr "se esperaba un registro de tecnología Intel Inalámbrico MMX"
+#: config/tc-arm.c:365
+msgid "iWMMXt data register expected"
+msgstr "se esperaba un registro de datos iWMMXt"
+
+#: config/tc-arm.c:366
+msgid "iWMMXt control register expected"
+msgstr "se esperaba un registro de control iWMMXt"
 
-#: config/tc-arm.c:2309
+#: config/tc-arm.c:367
+msgid "iWMMXt scalar register expected"
+msgstr "se esperaba un registro escalar iWMMXt"
+
+#: config/tc-arm.c:368
+msgid "XScale accumulator register expected"
+msgstr "se esperaba un registro acumulador XScale"
+
+#: config/tc-arm.c:499
 msgid "bad arguments to instruction"
 msgstr "argumentos erróneos para la instrucción"
 
-#: config/tc-arm.c:2310
+#: config/tc-arm.c:500
 msgid "r15 not allowed here"
 msgstr "no se permite r15 aquí"
 
-#: config/tc-arm.c:2311
-msgid "instruction is not conditional"
-msgstr "la instrucción no es condicional"
+#: config/tc-arm.c:501
+msgid "instruction cannot be conditional"
+msgstr "la instrucción no puede ser condicional"
 
-#: config/tc-arm.c:2312
-msgid "acc0 expected"
-msgstr "se esperaba acc0"
+#: config/tc-arm.c:502
+msgid "registers may not be the same"
+msgstr "los registros no pueden ser el mismo"
 
-#: config/tc-arm.c:2505
-msgid "literal pool overflow"
-msgstr "desbordamiento de conjunto literal"
+#: config/tc-arm.c:503
+msgid "lo register required"
+msgstr "se requiere el registro lo"
 
-#: config/tc-arm.c:2647
-msgid "invalid syntax for .req directive"
-msgstr "sintaxis inválida para la directiva .req."
+#: config/tc-arm.c:504
+msgid "instruction not supported in Thumb16 mode"
+msgstr "la instrucción no tiene soporte en modo Thumb16"
+
+#: config/tc-arm.c:640
+msgid "immediate expression requires a # prefix"
+msgstr "la expresión inmediata requiere un prefijo #"
+
+#: config/tc-arm.c:666 expr.c:1302 read.c:2228
+msgid "bad expression"
+msgstr "expresión errónea"
+
+#: config/tc-arm.c:677 config/tc-i860.c:1005 config/tc-sparc.c:2844
+msgid "bad segment"
+msgstr "segmento erróneo"
+
+#: config/tc-arm.c:693 config/tc-arm.c:3230 config/tc-i960.c:1302
+msgid "invalid constant"
+msgstr "constante inválida"
 
-#: config/tc-arm.c:2727
+#: config/tc-arm.c:754
+msgid "bad call to MD_ATOF()"
+msgstr "llamada errónea a MD_ATOF()"
+
+#: config/tc-arm.c:821
+msgid "expected #constant"
+msgstr "se esperaba #constant"
+
+#: config/tc-arm.c:953
+msgid "bad range in register list"
+msgstr "rango erróneo en la lista de registros"
+
+#: config/tc-arm.c:961 config/tc-arm.c:970 config/tc-arm.c:1011
 #, c-format
-msgid "alignment too large: %d assumed"
-msgstr "alineación demasiado grande: se asume %d"
+msgid "Warning: duplicated register (r%d) in register list"
+msgstr "Aviso: registro duplicado (r%d) en la lista de registros"
 
-#: config/tc-arm.c:2730
-msgid "alignment negative. 0 assumed."
-msgstr "alineación negativa. Se asume 0."
+#: config/tc-arm.c:973
+msgid "Warning: register range not in ascending order"
+msgstr "Aviso: el rango de registros no está en orden ascendente"
+
+#: config/tc-arm.c:984
+msgid "missing `}'"
+msgstr "falta un `}'"
+
+#: config/tc-arm.c:1000
+msgid "invalid register mask"
+msgstr "máscara de registro inválida"
+
+#: config/tc-arm.c:1091 config/tc-arm.c:1126 config/tc-h8300.c:991
+#: config/tc-mips.c:9797 config/tc-mips.c:9827
+msgid "invalid register list"
+msgstr "lista de registros inválida"
+
+#: config/tc-arm.c:1097 config/tc-arm.c:2402 config/tc-arm.c:2535
+msgid "register list not in ascending order"
+msgstr "la lista de registros no está en orden ascendente"
+
+#: config/tc-arm.c:1118
+msgid "register range not in ascending order"
+msgstr "el rango de registros no está en orden ascendente"
+
+#: config/tc-arm.c:1151
+msgid "non-contiguous register range"
+msgstr "el rango de registro no es contiguo"
 
-#: config/tc-arm.c:2814
+#: config/tc-arm.c:1199
 #, c-format
-msgid "expected comma after name \"%s\""
-msgstr "se esperaba una coma después del nombre \"%s\""
+msgid "ignoring attempt to redefine built-in register '%s'"
+msgstr "se ignora el intento de redefinir el símbolo interno '%s'"
 
-#: config/tc-arm.c:2864 config/tc-m32r.c:420
+#: config/tc-arm.c:1204
 #, c-format
-msgid "symbol `%s' already defined"
-msgstr "el símbolo `%s' ya está definido"
+msgid "ignoring redefinition of register alias '%s'"
+msgstr "se ignora la redefinición del alias de registro '%s'"
+
+#: config/tc-arm.c:1248
+#, c-format
+msgid "unknown register '%s' -- .req ignored"
+msgstr "registro '%s' desconocido -- se ignora .req"
+
+#: config/tc-arm.c:1291
+msgid "invalid syntax for .req directive"
+msgstr "sintaxis inválida para la directiva .req."
 
-#: config/tc-arm.c:2889
+#: config/tc-arm.c:1317
+msgid "invalid syntax for .unreq directive"
+msgstr "sintaxis inválida para la directiva .unreq"
+
+#: config/tc-arm.c:1323
+#, c-format
+msgid "unknown register alias '%s'"
+msgstr "alias de registro '%s' desconocido"
+
+#: config/tc-arm.c:1325
+#, c-format
+msgid "ignoring attempt to undefine built-in register '%s'"
+msgstr "se ignora el intento de eliminar la definición del símbolo interno '%s'"
+
+#: config/tc-arm.c:1456
 msgid "selected processor does not support THUMB opcodes"
 msgstr "el procesador seleccionado no tiene soporte para códigos de operación THUMB"
 
-#: config/tc-arm.c:2902
+#: config/tc-arm.c:1470
 msgid "selected processor does not support ARM opcodes"
 msgstr "el procesador seleccionado no tiene soporte para códigos de operación ARM"
 
-#: config/tc-arm.c:2914
+#: config/tc-arm.c:1483
 #, c-format
 msgid "invalid instruction size selected (%d)"
 msgstr "tamaño de instrucción seleccionado inválido (%d)"
 
-#: config/tc-arm.c:2949
+#: config/tc-arm.c:1515
 #, c-format
 msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
 msgstr "operando inválido para la directiva .code (%d) (se esperaba 16 o 32)"
 
-#: config/tc-arm.c:2960
-msgid "garbage following instruction"
-msgstr "basura a continuación de la instrucción"
-
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:3010
+#: config/tc-arm.c:1571
 #, c-format
-msgid "register expected, not '%.100s'"
-msgstr "se esperaba un registro, no '%.100s'"
+msgid "expected comma after name \"%s\""
+msgstr "se esperaba una coma después del nombre \"%s\""
 
-#. In the few cases where we might be able to accept
-#. something else this error can be overridden.
-#: config/tc-arm.c:3061
+#: config/tc-arm.c:1621 config/tc-m32r.c:589
 #, c-format
-msgid "Intel Wireless MMX technology register expected, not '%.100s'"
-msgstr "se esperaba un registro de tecnología Intel Inalámbrica MMX, no '%.100s'"
+msgid "symbol `%s' already defined"
+msgstr "el símbolo `%s' ya está definido"
 
-#. In the few cases where we might be able to accept
-#. something else this error can be overridden.
-#: config/tc-arm.c:3133
-msgid "flag for {c}psr instruction expected"
-msgstr "se esperaba una opción para la instrucción {c}psr"
+#: config/tc-arm.c:1655
+#, c-format
+msgid "unrecognized syntax mode \"%s\""
+msgstr "modo de sintaxis \"%s\" no reconocido"
 
-#: config/tc-arm.c:3167
-msgid "illegal co-processor number"
-msgstr "número de co-procesador ilegal"
+#: config/tc-arm.c:1675
+#, c-format
+msgid "alignment too large: %d assumed"
+msgstr "alineación demasiado grande: se asume %d"
 
-#: config/tc-arm.c:3199 config/tc-arm.c:4778
-msgid "bad or missing expression"
-msgstr "expresión errónea o faltante"
+#: config/tc-arm.c:1678
+msgid "alignment negative. 0 assumed."
+msgstr "alineación negativa. Se asume 0."
 
-#: config/tc-arm.c:3205
-msgid "immediate co-processor expression too large"
-msgstr "expresión de co-procesador inmediata demasiado grande"
+#: config/tc-arm.c:1816
+msgid "literal pool overflow"
+msgstr "desbordamiento de conjunto literal"
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:3252
-msgid "floating point register expected"
-msgstr "se esperaba un registro de coma flotante"
+#: config/tc-arm.c:1972 config/tc-arm.c:3888
+msgid "unrecognized relocation suffix"
+msgstr "sufijo de reubicación no reconocido"
 
-#: config/tc-arm.c:3269 config/tc-arm.c:3414
-msgid "immediate expression expected"
-msgstr "se esperaba una expresión inmediata"
+#: config/tc-arm.c:1985
+msgid "(plt) is only valid on branch targets"
+msgstr "(plt) sólo es válido en objetivos ramas"
 
-#: config/tc-arm.c:3284
-msgid "co-processor address must be word aligned"
-msgstr "la dirección del co-procesador debe ser alineada con word"
+#: config/tc-arm.c:1991 config/tc-s390.c:1128 config/tc-s390.c:1742
+#: config/tc-xtensa.c:1601
+#, c-format
+msgid "%s relocations do not fit in %d bytes"
+msgstr "%s reubicaciones no caben en %d bytes"
 
-#: config/tc-arm.c:3290 config/tc-arm.c:3429
-msgid "offset too large"
-msgstr "desplazamiento demasiado grande"
+#: config/tc-arm.c:2039 dwarf2dbg.c:659
+msgid "expected 0 or 1"
+msgstr "se esperaba 0 ó 1"
 
-#: config/tc-arm.c:3339 config/tc-arm.c:3477
-msgid "pc may not be used in post-increment"
-msgstr "el pc no se puede usar en post-incremento"
+#: config/tc-arm.c:2043
+msgid "missing comma"
+msgstr "falta una coma"
 
-#: config/tc-arm.c:3355 config/tc-arm.c:3493 config/tc-arm.c:3938
-#: config/tc-arm.c:5197 config/tc-arm.c:6064 config/tc-arm.c:6398
-msgid "pre-indexed expression expected"
-msgstr "se esperaba una expresión pre-indizada"
+#: config/tc-arm.c:2098
+msgid "dupicate .handlerdata directive"
+msgstr "directiva .handlerdata duplicada"
 
-#: config/tc-arm.c:3368 config/tc-arm.c:3506 config/tc-arm.c:3951
-#: config/tc-arm.c:5208 config/tc-arm.c:6076 config/tc-arm.c:6410
-#: config/tc-arm.c:6784 config/tc-arm.c:9448 config/tc-arm.c:9463
-msgid "missing ]"
-msgstr "falta un ]"
+#: config/tc-arm.c:2169
+msgid "personality routine specified for cantunwind frame"
+msgstr "se especificó una rutina personality para el marco cantunwind"
 
-#: config/tc-arm.c:3378 config/tc-arm.c:3516
-msgid "pc may not be used with write-back"
-msgstr "el pc no se puede usar con escritura hacia atrás"
+#: config/tc-arm.c:2183
+msgid "duplicate .personalityindex directive"
+msgstr "directiva .personalityindex duplicada"
 
-#: config/tc-arm.c:3568
-msgid "comma expected after register name"
-msgstr "se esperaba una coma después del nombre de registro"
+#: config/tc-arm.c:2190
+msgid "bad personality routine number"
+msgstr "número de rutina personality erróneo"
 
-#: config/tc-arm.c:3587
-msgid "CPSR or SPSR expected"
-msgstr "se esperaba CPSR ó SPSR"
+#: config/tc-arm.c:2209
+msgid "duplicate .personality directive"
+msgstr "directiva .personality duplicada"
 
-#: config/tc-arm.c:3613
-msgid "comma missing after psr flags"
-msgstr "falta una coma después de las opciones psr"
+#: config/tc-arm.c:2232 config/tc-arm.c:2354
+msgid "expected register list"
+msgstr "se esperaba una lista de registros"
 
-#: config/tc-arm.c:3629 config/tc-arm.c:3639
-msgid "only a register or immediate value can follow a psr flag"
-msgstr "sólo un registro o un valor inmediato puede seguir a una opción psr"
+#: config/tc-arm.c:2310
+msgid "expected , <constant>"
+msgstr "se esperaba , <constante>"
 
-#: config/tc-arm.c:3650
-msgid "immediate value cannot be used to set this field"
-msgstr "no se puede usar un valor inmediato para establecer este campo"
+#: config/tc-arm.c:2319
+msgid "number of registers must be in the range [1:4]"
+msgstr "el número de registros debe estar en el rango [1:4]"
 
-#: config/tc-arm.c:3668 config/tc-arm.c:5424 config/tc-arm.c:5704
-#: config/tc-arm.c:5724 config/tc-i960.c:1935
-msgid "invalid constant"
-msgstr "constante inválida"
+#: config/tc-arm.c:2416 config/tc-arm.c:2549
+msgid "bad register range"
+msgstr "rango de registro erróneo"
 
-#: config/tc-arm.c:3716
-msgid "rdhi, rdlo and rm must all be different"
-msgstr "rdhi, rdlo y rm deben ser todos diferentes"
+#: config/tc-arm.c:2602
+msgid "register expected"
+msgstr "se esperaba un registro"
 
-#: config/tc-arm.c:3770
-msgid "rd and rm should be different in mul"
-msgstr "rd y rm deben ser diferentes en mul"
+#: config/tc-arm.c:2612
+msgid "FPA .unwind_save does not take a register list"
+msgstr ".unwind_save de FPA no toma una lista de registros"
 
-#: config/tc-arm.c:3824
-msgid "rd and rm should be different in mla"
-msgstr "rd y rm deben ser diferentes en mla"
+#: config/tc-arm.c:2625
+msgid ".unwind_save does not support this kind of register"
+msgstr ".unwind_save no tiene soporte para este tipo de registro"
 
-#: config/tc-arm.c:3872
-#, c-format
-msgid "acc0 expected, not '%.100s'"
-msgstr "se esperaba acc0, no '%.100s'"
+#: config/tc-arm.c:2650
+msgid "SP and PC not permitted in .unwind_movsp directive"
+msgstr "no se permiten SP y PC en la directiva .unwind_movsp"
 
-#: config/tc-arm.c:4050
-msgid "rdhi and rdlo must be different"
-msgstr "rdhi y rdlo deben ser diferentes"
+#: config/tc-arm.c:2655
+msgid "unexpected .unwind_movsp directive"
+msgstr "directiva .unwind_movsp inesperada"
 
-#: config/tc-arm.c:4158
-msgid "Warning: instruction unpredictable when using r15"
-msgstr "Aviso: la instrucción es impredecible cuando se utiliza r15"
+#: config/tc-arm.c:2679
+msgid "stack increment must be multiple of 4"
+msgstr "el operando de pila debe ser un múltiplo de 4"
 
-#: config/tc-arm.c:4373
-msgid "use of r15 in bxj is not really useful"
-msgstr "el uso de r15 en bxj no es realmente útil"
+#: config/tc-arm.c:2708
+msgid "expected <reg>, <reg>"
+msgstr "se esperaba <reg>, <reg>"
 
-#: config/tc-arm.c:4400 config/tc-arm.c:4585 config/tc-arm.c:5445 expr.c:1318
-#: read.c:2206
-msgid "bad expression"
-msgstr "expresión errónea"
+#: config/tc-arm.c:2726
+msgid "register must be either sp or set by a previousunwind_movsp directive"
+msgstr "el registro debe ser sp o establecido por una directiva previousunwind_movsp"
 
-#: config/tc-arm.c:4409 config/tc-arm.c:4594 config/tc-arm.c:4786
-#: config/tc-arm.c:8389 config/tc-arm.c:8424 config/tc-arm.c:8434
-#: config/tc-z8k.c:1161 config/tc-z8k.c:1173
-msgid "immediate value out of range"
-msgstr "valor inmediato fuera de rango"
+#: config/tc-arm.c:2762
+msgid "expected <offset>, <opcode>"
+msgstr "se esperaba <desplazamiento>, <códigoop>"
 
-#: config/tc-arm.c:4833
-msgid "only r15 allowed here"
-msgstr "sólo se permite r15 aquí"
+#: config/tc-arm.c:2774
+msgid "unwind opcode too long"
+msgstr "código de operación de desenredo demasiado largo"
 
-#: config/tc-arm.c:5160
-msgid "'[' expected after PLD mnemonic"
-msgstr "se esperaba '[' después del mnemónico PLD"
+#: config/tc-arm.c:2779
+msgid "invalid unwind opcode"
+msgstr "código de operación de desenredo inválido"
 
-#: config/tc-arm.c:5182
-msgid "post-indexed expression used in preload instruction"
-msgstr "se usó una expresión post-indizada en la instrucción de precarga"
+#: config/tc-arm.c:2829
+msgid "expected numeric constant"
+msgstr "se esperaba una constante numérica"
 
-#: config/tc-arm.c:5187 config/tc-arm.c:5217
-msgid "writeback used in preload instruction"
-msgstr "se usó escritura hacia atrás en la instrucción de precarga"
+#: config/tc-arm.c:2838
+msgid "expected comma"
+msgstr "se esperaba una coma"
 
-#: config/tc-arm.c:5259
-msgid "destination register must be even"
-msgstr "el registro de destino debe ser par"
+#: config/tc-arm.c:2877
+msgid "bad string constant"
+msgstr "constante de cadena errónea"
 
-#: config/tc-arm.c:5265
-msgid "r14 not allowed here"
-msgstr "no se permite r14 aquí"
+#: config/tc-arm.c:2881
+msgid "expected <tag> , <value>"
+msgstr "se esperaba <etiq> , <valor>"
 
-#: config/tc-arm.c:5272
-msgid "pre/post-indexing used when modified address register is destination"
-msgstr "se usó pre/post-indizado cuando el registro de dirección modificado es el destino"
+#: config/tc-arm.c:2957
+msgid "constant expression required"
+msgstr "se requiere una expresión constante"
 
-#: config/tc-arm.c:5282
-msgid "ldrd destination registers must not overlap index register"
-msgstr "los registros destino ldrd no deben quedar sobre el registro índice"
+#: config/tc-arm.c:2963 config/tc-arm.c:6472 config/tc-arm.c:11799
+#: config/tc-arm.c:11824 config/tc-arm.c:11832 config/tc-z8k.c:1122
+#: config/tc-z8k.c:1132
+msgid "immediate value out of range"
+msgstr "valor inmediato fuera de rango"
 
-#: config/tc-arm.c:5408
-msgid "bad_segment"
-msgstr "segmento_erróneo"
+#: config/tc-arm.c:3058
+msgid "invalid FPA immediate expression"
+msgstr "expresión inmediata FPA inválida"
 
-#: config/tc-arm.c:5468 config/tc-arm.c:5479
+#: config/tc-arm.c:3108 config/tc-arm.c:3116
 msgid "shift expression expected"
 msgstr "se esperaba una expresión de desplazamiento"
 
-#: config/tc-arm.c:5503
-msgid "shift requires register or #expression"
-msgstr "el desplazamiento requiere un registro o una #expresión"
-
-#: config/tc-arm.c:5504
-msgid "shift requires #expression"
-msgstr "el desplazamiento requiere una #expresión"
+#: config/tc-arm.c:3130
+msgid "'LSL' or 'ASR' required"
+msgstr "se requiere 'LSL' o 'ASR'"
 
-#: config/tc-arm.c:5534
-msgid "shift of 0 ignored."
-msgstr "se ignora un desplazamiento de 0."
+#: config/tc-arm.c:3138
+msgid "'LSL' required"
+msgstr "se requiere 'LSL'"
 
-#: config/tc-arm.c:5540
-msgid "invalid immediate shift"
-msgstr "desplazamiento inmediato inválido"
+#: config/tc-arm.c:3146
+msgid "'ASR' required"
+msgstr "se requiere 'ASR'"
 
-#: config/tc-arm.c:5695 config/tc-arm.c:6112 config/tc-arm.c:6447
-#: config/tc-arm.c:7081 config/tc-v850.c:1908 config/tc-v850.c:1929
+#: config/tc-arm.c:3218 config/tc-arm.c:4349 config/tc-v850.c:1844
+#: config/tc-v850.c:1865
 msgid "constant expression expected"
 msgstr "se esperaba una expresión constante"
 
-#: config/tc-arm.c:5737
-msgid "register or shift expression expected"
-msgstr "se esperaba un registro o una expresión de desplazamiento"
+#: config/tc-arm.c:3225
+msgid "invalid rotation"
+msgstr "rotación inválida"
 
-#: config/tc-arm.c:5790
-msgid "invalid floating point immediate expression"
-msgstr "expresión inmediata de coma flotante inválida"
+#: config/tc-arm.c:3340 config/tc-arm.c:3640
+msgid "']' expected"
+msgstr "se esperaba ']'"
 
-#: config/tc-arm.c:5794
-msgid "floating point register or immediate expression expected"
-msgstr "se esperaba un registro de coma flotante o una expresión inmediata"
+#: config/tc-arm.c:3358
+msgid "'}' expected at end of 'option' field"
+msgstr "se esperaba '}' al final del campo 'option'"
 
-#: config/tc-arm.c:5948 config/tc-arm.c:6278
-msgid "address offset too large"
-msgstr "dirección de desplazamiento demasiado grande"
+#: config/tc-arm.c:3363
+msgid "cannot combine index with option"
+msgstr "no se puede combinar index con option"
 
-#: config/tc-arm.c:6006 config/tc-arm.c:6196 config/tc-arm.c:6338
-msgid "address expected"
-msgstr "se esperaba una dirección"
+#: config/tc-arm.c:3376
+msgid "cannot combine pre- and post-indexing"
+msgstr "no se puede combinar pre y post-indizado"
 
-#: config/tc-arm.c:6036 config/tc-arm.c:6048 config/tc-arm.c:6085
-#: config/tc-arm.c:6214 config/tc-arm.c:6368 config/tc-arm.c:6382
-#: config/tc-arm.c:6419
-#, c-format
-msgid "%s register same as write-back base"
-msgstr "el registro %s es el mismo que la base de escritura-hacia-atrás"
+#: config/tc-arm.c:3472
+msgid "flag for {c}psr instruction expected"
+msgstr "se esperaba una opción para la instrucción {c}psr"
+
+#: config/tc-arm.c:3497
+msgid "unrecognized CPS flag"
+msgstr "opción CPS no reconocida"
+
+#: config/tc-arm.c:3504
+msgid "missing CPS flags"
+msgstr "faltan las opciones CPS"
+
+#: config/tc-arm.c:3527 config/tc-arm.c:3533
+msgid "valid endian specifiers are be or le"
+msgstr "los especificadores endian válidos son be o le"
+
+#: config/tc-arm.c:3555
+msgid "missing rotation field after comma"
+msgstr "falta el campo rotation después de la coma"
+
+#: config/tc-arm.c:3570
+msgid "rotation can only be 0, 8, 16, or 24"
+msgstr "la rotación sólo puede ser 0, 8 , 16 o 24"
+
+#: config/tc-arm.c:3590
+msgid "condition required"
+msgstr "se requiere una condición"
+
+#: config/tc-arm.c:3632
+msgid "invalid shift"
+msgstr "desplazamiento inválido"
+
+#: config/tc-arm.c:3929
+msgid "iWMMXt data or control register expected"
+msgstr "se esperaba un registro de datos o control iWMMXt"
+
+#: config/tc-arm.c:4051
+msgid "garbage following instruction"
+msgstr "basura a continuación de la instrucción"
+
+#: config/tc-arm.c:4185
+msgid "instruction does not accept preindexed addressing"
+msgstr "la instrucción no acepta el direccionamiento preindizado"
+
+#. unindexed - only for coprocessor
+#: config/tc-arm.c:4201 config/tc-arm.c:5857
+msgid "instruction does not accept unindexed addressing"
+msgstr "la instrucción no acepta el direccionamiento sin indizar"
+
+#: config/tc-arm.c:4209
+msgid "destination register same as write-back base"
+msgstr "el registro destino es el mismo que la base de escritura-hacia-atrás"
+
+#: config/tc-arm.c:4210
+msgid "source register same as write-back base"
+msgstr "el registro fuente es el mismo que la base de escritura-hacia-atrás"
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
-msgid "destination"
-msgstr "destino"
+#: config/tc-arm.c:4256
+msgid "instruction does not accept scaled register index"
+msgstr "la instrucción no acepta el índice de registro escalado"
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
-msgid "source"
-msgstr "fuente"
+#: config/tc-arm.c:4295
+msgid "instruction does not support unindexed addressing"
+msgstr "la instrucción no acepta el direccionamiento sin indizar"
 
-#: config/tc-arm.c:6097 config/tc-arm.c:6431 config/tc-arm.c:8695
+#: config/tc-arm.c:4310
+msgid "pc may not be used with write-back"
+msgstr "el pc no se puede usar con escritura hacia atrás"
+
+#: config/tc-arm.c:4315
+msgid "instruction does not support writeback"
+msgstr "la instrucción no tiene soporte para escritura hacia atrás"
+
+#: config/tc-arm.c:4344
 msgid "invalid pseudo operation"
 msgstr "pseudo operación inválida"
 
-#: config/tc-arm.c:6149 config/tc-arm.c:6482
+#: config/tc-arm.c:4390
 msgid "literal pool insertion failed"
 msgstr "falló la inserción en el conjunto de literales"
 
-#: config/tc-arm.c:6244 config/tc-arm.c:6250
-msgid "post-indexed expression expected"
-msgstr "se esperaba una expresión post-indizada"
-
-#: config/tc-arm.c:6548
-msgid "bad range in register list"
-msgstr "rango erróneo en la lista de registros"
+#: config/tc-arm.c:4448
+msgid "Rn must not overlap other operands"
+msgstr "Rn no debe sobreescribir otros operandos"
 
-#: config/tc-arm.c:6556 config/tc-arm.c:6565 config/tc-arm.c:6607
-#, c-format
-msgid "Warning: duplicated register (r%d) in register list"
-msgstr "Aviso: registro duplicado (r%d) en la lista de registros"
+#: config/tc-arm.c:4534 config/tc-arm.c:4553 config/tc-arm.c:4566
+#: config/tc-arm.c:6360 config/tc-arm.c:6380 config/tc-arm.c:6394
+msgid "bit-field extends past end of register"
+msgstr "el campo de bits se extiende más allá del final del registro"
 
-#: config/tc-arm.c:6568
-msgid "Warning: register range not in ascending order"
-msgstr "Aviso: el rango de registros no está en orden ascendente"
+#: config/tc-arm.c:4595
+msgid "the only suffix valid here is '(plt)'"
+msgstr "el único sufijo válido aquí es '(plt)'"
 
-#: config/tc-arm.c:6580
-msgid "missing `}'"
-msgstr "falta un `}'"
+#: config/tc-arm.c:4627
+msgid "use of r15 in blx in ARM mode is not really useful"
+msgstr "el uso de r15 en blx en modo ARM no es realmente útil"
 
-#: config/tc-arm.c:6596
-msgid "invalid register mask"
-msgstr "máscara de registro inválida"
+#: config/tc-arm.c:4645
+msgid "use of r15 in bx in ARM mode is not really useful"
+msgstr "el uso de r15 en bx en modo ARM no es realmente útil"
 
-#: config/tc-arm.c:6655
-msgid "r15 not allowed as base register"
-msgstr "no se permite r15 como registro base"
+#: config/tc-arm.c:4657 config/tc-arm.c:6508
+msgid "use of r15 in bxj is not really useful"
+msgstr "el uso de r15 en bxj no es realmente útil"
 
-#: config/tc-arm.c:6689 config/tc-arm.c:6698
+#: config/tc-arm.c:4761 config/tc-arm.c:4770
 msgid "writeback of base register is UNPREDICTABLE"
 msgstr "la escritura hacia atrás del registro base es IMPREDECIBLE"
 
-#: config/tc-arm.c:6692
+#: config/tc-arm.c:4764
 msgid "writeback of base register when in register list is UNPREDICTABLE"
 msgstr "la escritura hacia atrás del registro base cuando está en la lista de registros es IMPREDECIBLE"
 
-#: config/tc-arm.c:6702
+#: config/tc-arm.c:4774
 msgid "if writeback register is in list, it must be the lowest reg in the list"
 msgstr "si el registro de escritura hacia atrás está en la lista, debe ser el registro más bajo en la lista"
 
-#: config/tc-arm.c:6744 config/tc-arm.c:6758
-msgid "r15 not allowed in swap"
-msgstr "no se permite r15 en el intercambio"
+#: config/tc-arm.c:4789
+msgid "first destination register must be even"
+msgstr "el primer registro de destino debe ser par"
 
-#: config/tc-arm.c:6853
-msgid "use of r15 in bx in ARM mode is not really useful"
-msgstr "el uso de r15 en bx en modo ARM no es realmente útil"
+#: config/tc-arm.c:4792 config/tc-arm.c:4849
+msgid "can only load two consecutive registers"
+msgstr "solamente se pueden cargar dos registros consecutivos"
 
-#: config/tc-arm.c:7087
-msgid "constant value required for number of registers"
-msgstr "se requiere un valor constante para el número de registros"
+#. If op 1 were present and equal to PC, this function wouldn't
+#. have been called in the first place.
+#. If op 2 were present and equal to PC, this function wouldn't
+#. have been called in the first place.
+#: config/tc-arm.c:4793 config/tc-arm.c:4852 config/tc-arm.c:5299
+#: config/tc-arm.c:6886
+msgid "r14 not allowed here"
+msgstr "no se permite r14 aquí"
 
-#: config/tc-arm.c:7095
-msgid "number of registers must be in the range [1:4]"
-msgstr "el número de registros debe estar en el rango [1:4]"
+#: config/tc-arm.c:4794
+msgid "'[' expected"
+msgstr "se esperaba '['"
 
-#: config/tc-arm.c:7156
-msgid "r15 not allowed as base register with write-back"
-msgstr "no se permite r15 como registro base con escritura-hacia-atrás"
+#: config/tc-arm.c:4807
+msgid "base register written back, and overlaps second destination register"
+msgstr "el registro base se escribió hacia atrás, y sobreescribe el segundo registro de destino"
 
-#: config/tc-arm.c:7538
-msgid "only two consecutive VFP SP registers allowed here"
-msgstr "solamente se permiten dos registros SP VFP consecutivos aquí"
+#: config/tc-arm.c:4815
+msgid "index register overlaps destination register"
+msgstr "el registro índice sobreescribe el registro destino"
 
-#: config/tc-arm.c:7706
-msgid "VFP system register expected"
-msgstr "se esperaba un registro de sistema VFP"
+#: config/tc-arm.c:4829 config/tc-arm.c:5272 config/tc-arm.c:6706
+#: config/tc-arm.c:7581
+msgid "instruction does not accept this addressing mode"
+msgstr "la instrucción no acepta este modo de direccionamiento"
 
-#: config/tc-arm.c:7844 config/tc-arm.c:7883 config/tc-arm.c:7896
-#: config/tc-arm.c:7957 config/tc-arm.c:7996 config/tc-arm.c:8009
-#: config/tc-h8300.c:1035 config/tc-mips.c:9722 config/tc-mips.c:9752
-msgid "invalid register list"
-msgstr "lista de registros inválida"
+#: config/tc-arm.c:4835 config/tc-arm.c:5281
+msgid "offset must be zero in ARM encoding"
+msgstr "el desplazamiento debe ser cero en codificación ARM"
 
-#: config/tc-arm.c:7850 config/tc-arm.c:7963
-msgid "register list not in ascending order"
-msgstr "la lista de registros no está en orden ascendente"
+#: config/tc-arm.c:4846 config/tc-arm.c:5293
+msgid "even register required"
+msgstr "se requiere un registro par"
 
-#: config/tc-arm.c:7875 config/tc-arm.c:7988
-msgid "register range not in ascending order"
-msgstr "el rango de registros no está en orden ascendente"
+#: config/tc-arm.c:4877 config/tc-arm.c:4908
+msgid "this instruction requires a post-indexed address"
+msgstr "esta instrucción requiere una dirección post-indizada"
 
-#: config/tc-arm.c:7913 config/tc-arm.c:8026
-msgid "non-contiguous register range"
-msgstr "el rango de registro no es contiguo"
+#: config/tc-arm.c:4935
+msgid "rd and rm should be different in mla"
+msgstr "rd y rm deben ser diferentes en mla"
+
+#: config/tc-arm.c:4967 config/tc-arm.c:7121
+msgid "'CPSR' or 'SPSR' expected"
+msgstr "se esperaba 'CPSR' o 'SPSR'"
+
+#: config/tc-arm.c:5000
+msgid "rd and rm should be different in mul"
+msgstr "rd y rm deben ser diferentes en mul"
+
+#: config/tc-arm.c:5021
+msgid "rdhi, rdlo and rm must all be different"
+msgstr "rdhi, rdlo y rm deben ser todos diferentes"
+
+#: config/tc-arm.c:5083
+msgid "'[' expected after PLD mnemonic"
+msgstr "se esperaba '[' después del mnemónico PLD"
+
+#: config/tc-arm.c:5085
+msgid "post-indexed expression used in preload instruction"
+msgstr "se usó una expresión post-indizada en la instrucción de precarga"
+
+#: config/tc-arm.c:5087
+msgid "writeback used in preload instruction"
+msgstr "se usó escritura hacia atrás en la instrucción de precarga"
+
+#: config/tc-arm.c:5089
+msgid "unindexed addressing used in preload instruction"
+msgstr "se usó un direccionamiento sin indizar en la instrucción de precarga"
+
+#: config/tc-arm.c:5188 config/tc-arm.c:7492
+msgid "source1 and dest must be same register"
+msgstr "source1 y dest debe ser el mismo registro"
 
-#: config/tc-arm.c:8056 config/tc-arm.c:8093
+#: config/tc-arm.c:5238 config/tc-arm.c:7178
+msgid "rdhi and rdlo must be different"
+msgstr "rdhi y rdlo deben ser diferentes"
+
+#: config/tc-arm.c:5296
+msgid "can only store two consecutive registers"
+msgstr "solamente se pueden almacenar dos registros consecutivos"
+
+#: config/tc-arm.c:5391 config/tc-arm.c:5408
+msgid "only two consecutive VFP SP registers allowed here"
+msgstr "solamente se permiten dos registros SP VFP consecutivos aquí"
+
+#: config/tc-arm.c:5436 config/tc-arm.c:5451
 msgid "this addressing mode requires base-register writeback"
 msgstr "este modo de direccionamiento requiere escritura hacia atrás del registro-base"
 
-#: config/tc-arm.c:8253
-msgid "lo register required"
-msgstr "se requiere el registro lo"
+#: config/tc-arm.c:5529
+msgid "this instruction does not support indexing"
+msgstr "esta instrucción no tiene soporte para indizado"
+
+#: config/tc-arm.c:5552
+msgid "only r15 allowed here"
+msgstr "sólo se permite r15 aquí"
 
-#: config/tc-arm.c:8261
-msgid "hi register required"
-msgstr "se requiere el registro hi"
+#: config/tc-arm.c:5757
+msgid "shift by register not allowed in thumb mode"
+msgstr "no se permite desplazar por registro en modo thumb"
 
-#: config/tc-arm.c:8331 config/tc-arm.c:9537
+#: config/tc-arm.c:5769 config/tc-arm.c:11339
+msgid "shift expression is too large"
+msgstr "la expresión de desplazamiento es demasiado grande"
+
+#: config/tc-arm.c:5795
+msgid "Thumb does not support the ldr =N pseudo-operation"
+msgstr "Thumb no tiene soporte para la pseudo-operación ldr =N"
+
+#: config/tc-arm.c:5800
+msgid "cannot use register index with PC-relative addressing"
+msgstr "no se puede usar el índice de registro con direccionamiento relativo al PC"
+
+#: config/tc-arm.c:5801
+msgid "cannot use register index with this instruction"
+msgstr "no se puede usar el índice de registro con esta instrucción"
+
+#: config/tc-arm.c:5803
+msgid "Thumb does not support negative register indexing"
+msgstr "Thumb no tiene soporte para indizado negativo de registro"
+
+#: config/tc-arm.c:5805
+msgid "Thumb does not support register post-indexing"
+msgstr "Thumb no tiene soporte para post-indizado de registro"
+
+#: config/tc-arm.c:5807
+msgid "Thumb does not support register indexing with writeback"
+msgstr "Thumb no tiene soporte para indizado de registro con escritura hacia atrás"
+
+#: config/tc-arm.c:5809
+msgid "Thumb supports only LSL in shifted register indexing"
+msgstr "Thumb sólo da soporte a LSL en inidizado desplazado de registro"
+
+#: config/tc-arm.c:5818
+msgid "shift out of range"
+msgstr "desplazamiento fuera de rango"
+
+#: config/tc-arm.c:5826
+msgid "cannot use writeback with PC-relative addressing"
+msgstr "no se puede usar escritura hacia atrás con el direccionamiento relativo al PC"
+
+#: config/tc-arm.c:5828
+msgid "cannot use writeback with this instruction"
+msgstr "no se puede usar escritura hacia atrás con esta instrucción"
+
+#: config/tc-arm.c:5847
+msgid "cannot use post-indexing with PC-relative addressing"
+msgstr "no se puede usar post-indizado con el direccionamiento relativo al PC"
+
+#: config/tc-arm.c:5848
+msgid "cannot use post-indexing with this instruction"
+msgstr "no se puede usar post-indizado con esta instrucción"
+
+#: config/tc-arm.c:5975
+msgid "PC not allowed as destination"
+msgstr "no se permite PC como destino"
+
+#: config/tc-arm.c:6093 config/tc-arm.c:6234 config/tc-arm.c:6326
+#: config/tc-arm.c:7092
+msgid "shift must be constant"
+msgstr "el desplazamiento debe ser constante"
+
+#: config/tc-arm.c:6120 config/tc-arm.c:6249 config/tc-arm.c:6341
+#: config/tc-arm.c:7105
+msgid "unshifted register required"
+msgstr "se requiere un registro sin desplazar"
+
+#: config/tc-arm.c:6135 config/tc-arm.c:6352 config/tc-arm.c:7165
+msgid "dest must overlap one source register"
+msgstr "dest debe sobreescribir un registro fuente"
+
+#: config/tc-arm.c:6252
 msgid "dest and source1 must be the same register"
 msgstr "dest y source1 debe ser el mismo registro"
 
-#: config/tc-arm.c:8338
-msgid "subtract valid only on lo regs"
-msgstr "subtract válido sólo en registros lo"
+#: config/tc-arm.c:6537
+msgid "Thumb does not support the 2-argument form of this instruction"
+msgstr "Thumb no tiene soporte para la forma con 2 argumentos de esta instrucción"
 
-#: config/tc-arm.c:8362
-msgid "invalid Hi register with immediate"
-msgstr "registro Hi inválido con el inmediato"
+#: config/tc-arm.c:6616
+msgid "Thumb load/store multiple does not support {reglist}^"
+msgstr "load/store Thumb múltiples no tienen soporte para {reglist}^"
 
-#: config/tc-arm.c:8402
-msgid "invalid immediate value for stack adjust"
-msgstr "valor inmediato inválido para el ajuste de la pila"
+#: config/tc-arm.c:6633 config/tc-arm.c:6649 config/tc-arm.c:6680
+#, c-format
+msgid "value stored for r%d is UNPREDICTABLE"
+msgstr "el valor almacenado para r%d es IMPREDECIBLE"
 
-#: config/tc-arm.c:8413
-msgid "invalid immediate for address calculation"
-msgstr "inmediato inválido para el cálculo de dirección"
+#: config/tc-arm.c:6643
+msgid "SP should not be in register list"
+msgstr "SP no debe estar en la lista de registros"
 
-#: config/tc-arm.c:8500
-msgid "source1 and dest must be same register"
-msgstr "source1 y dest debe ser el mismo registro"
+#: config/tc-arm.c:6647
+msgid "PC should not be in register list"
+msgstr "PC no debe estar en la lista de registros"
 
-#: config/tc-arm.c:8534
-msgid "invalid immediate for shift"
-msgstr "inmediato inválido para el desplazamiento"
+#: config/tc-arm.c:6656 config/tc-arm.c:7311
+msgid "LR and PC should not both be in register list"
+msgstr "tanto LR como PC no deben estar en la lista de registros"
 
-#: config/tc-arm.c:8613
-msgid "only lo regs allowed with immediate"
-msgstr "sólo se permiten registros lo con inmediatos"
+#: config/tc-arm.c:6659
+msgid "base register should not be in register list when written back"
+msgstr "el registro base no debe estar en la lista de registros cuando se escribe hacia atrás"
 
-#: config/tc-arm.c:8632
-msgid "invalid immediate"
-msgstr "inmediato inválido"
+#: config/tc-arm.c:6677 config/tc-arm.c:6687
+msgid "this instruction will write back the base register"
+msgstr "esta instrucción escribirá hacia atrás el registro base"
 
-#: config/tc-arm.c:8686
-msgid "expected ']'"
-msgstr "se esperaba ']'"
+#: config/tc-arm.c:6690
+msgid "this instruction will not write back the base register"
+msgstr "esta instrucción no escribirá hacia atrás el registro base"
+
+#: config/tc-arm.c:6719
+msgid "r14 not allowed as first register when second register is omitted"
+msgstr "no se permite r14 como primer registro cuando se omite el segundo registro"
 
-#: config/tc-arm.c:8759
+#: config/tc-arm.c:6809 config/tc-arm.c:6822 config/tc-arm.c:6858
+msgid "Thumb does not support this addressing mode"
+msgstr "Thumb no tiene soporte para este modo de direccionamiento"
+
+#: config/tc-arm.c:6826
 msgid "byte or halfword not valid for base register"
 msgstr "byte o halfword no válido para el registro base"
 
-#: config/tc-arm.c:8764
+#: config/tc-arm.c:6829
 msgid "r15 based store not allowed"
 msgstr "no se permite el almacenamiento basado en r15"
 
-#: config/tc-arm.c:8769
+#: config/tc-arm.c:6831
 msgid "invalid base register for register offset"
 msgstr "registro base inválido para el desplazamiento del registro"
 
-#: config/tc-arm.c:8787 config/tc-arm.c:8822
-msgid "invalid offset"
-msgstr "desplazamiento inválido"
+#: config/tc-arm.c:7032
+msgid "only lo regs allowed with immediate"
+msgstr "sólo se permiten registros lo con inmediatos"
 
-#: config/tc-arm.c:8798
-msgid "invalid base register in load/store"
-msgstr "registro base inválido en carga/almacenamiento"
+#: config/tc-arm.c:7130
+msgid "Thumb encoding does not support an immediate here"
+msgstr "la codificación Thumb no tiene soporte para un inmediato aquí"
 
-#: config/tc-arm.c:9341
-msgid "expecting immediate, 7bit operand"
-msgstr "se espera un operando inmediato de 7 bits"
+#: config/tc-arm.c:7200
+msgid "Thumb does not support NOP with hints"
+msgstr "Thumb no tiene soporte para NOP con pistas"
 
-#: config/tc-arm.c:9356
-msgid "immediate out of range"
-msgstr "inmediato fuera de rango"
+#: config/tc-arm.c:7282
+msgid "push/pop do not support {reglist}^"
+msgstr "push/pop no tienen soporte para {reglist}^"
 
-#: config/tc-arm.c:9399
-msgid "offset expected"
-msgstr "se esperaba un desplazamiento"
+#: config/tc-arm.c:7301
+msgid "SP not allowed in register list"
+msgstr "no se permite SP en la lista de registros"
 
-#: config/tc-arm.c:9408 config/tc-pj.c:537 config/tc-sh.c:3593
-msgid "offset out of range"
-msgstr "desplazamiento fuera de rango"
+#: config/tc-arm.c:7305
+msgid "PC not allowed in register list"
+msgstr "no se permite PC en la lista de registros"
 
-#: config/tc-arm.c:9545
-msgid "Rs and Rd must be different in MUL"
-msgstr "Rs y Rd deben ser diferentes en MUL"
+#: config/tc-arm.c:7328
+msgid "invalid register list to push/pop instruction"
+msgstr "lista de registros inválida para la instrucción push/pop"
 
-#: config/tc-arm.c:9689
-msgid "inserted missing '!': load/store multiple always writes back base register"
-msgstr "se insertó un '!' faltante: los load/store múltiples siempre escribe hacia atrás el registro base"
+#: config/tc-arm.c:7513
+msgid "ror #imm not supported"
+msgstr "ror #imm no tiene soporte"
 
-#: config/tc-arm.c:9711
-msgid "only lo-regs valid in load/store multiple"
-msgstr "sólo los registros lo son válidos en carga/almacenamiento múltiple"
+#: config/tc-arm.c:7638
+msgid "Thumb encoding does not support rotation"
+msgstr "la codificación Thumb no tiene soporte para rotación"
 
-#: config/tc-arm.c:9757
-msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
-msgstr "sintaxis: ldrs[b] Rd, [Rb, Ro]"
+#: config/tc-arm.c:7656
+msgid "PC is not a valid index register"
+msgstr "PC no es un registro índice válido"
 
-#: config/tc-arm.c:9821
-msgid "invalid register list to push/pop instruction"
-msgstr "lista de registros inválida para la instrucción push/pop"
+#: config/tc-arm.c:7658
+msgid "instruction does not allow shifted index"
+msgstr "la instrucción no permite un índice desplazado"
 
-#: config/tc-arm.c:9933 config/tc-arm.c:10159
-msgid "virtual memory exhausted"
-msgstr "memoria agotada"
+#: config/tc-arm.c:7660
+msgid "instruction requires shifted index"
+msgstr "la instrucción requiere un índice desplazado"
+
+#: config/tc-arm.c:7943 config/tc-arm.c:8015
+msgid "conditional infixes are deprecated in unified syntax"
+msgstr "los infijos condicionales son obsoletos en la sintaxis unificada"
 
-#: config/tc-arm.c:10014
+#: config/tc-arm.c:8047
 #, c-format
-msgid "register '%s' does not exist\n"
-msgstr "el registro '%s' no existe\n"
+msgid "bad instruction `%s'"
+msgstr "instrucción `%s' errónea"
 
-#: config/tc-arm.c:10018
+#: config/tc-arm.c:8063 config/tc-arm.c:8126
 #, c-format
-msgid "ignoring redefinition of register alias '%s' to non-existant register '%s'"
-msgstr "se ignora la redefinición del alias de registro '%s' al registro no existente '%s'"
+msgid "selected processor does not support `%s'"
+msgstr "el procesador seleccionado no tiene soporte para `%s'"
+
+#: config/tc-arm.c:8069
+msgid "Thumb does not support conditional execution"
+msgstr "Thumb no tiene soporte para la ejecución condicional"
+
+#: config/tc-arm.c:8080
+msgid "incorrect condition in IT block"
+msgstr "condición incorrecta en el bloque IT"
 
-#: config/tc-arm.c:10027
+#: config/tc-arm.c:8088
+msgid "thumb conditional instrunction not in IT block"
+msgstr "la instrucción condicional thumb no está en el bloque IT"
+
+#: config/tc-arm.c:8108
 #, c-format
-msgid "ignoring redefinition of register alias '%s'"
-msgstr "se ignora la redefinición del alias de registro '%s'"
+msgid "cannot honor width suffix -- `%s'"
+msgstr "no se puede honrar el sufijo de anchura -- `%s'"
 
-#: config/tc-arm.c:10033
-msgid "ignoring incomplete .req pseuso op"
-msgstr "se ignora el pseudo operador incompleto .req"
+#: config/tc-arm.c:8131
+#, c-format
+msgid "width suffixes are invalid in ARM mode -- `%s'"
+msgstr "los sufijos de anchura son inválidos en modo ARM -- `%s'"
 
-#: config/tc-arm.c:10183
-msgid "use of old and new-style options to set CPU type"
-msgstr "se utilizan opciones de estilo antiguo y nuevo para establecer el tipo de CPU"
+#: config/tc-arm.c:10340
+msgid "alignments greater than 32 bytes not supported in .text sections."
+msgstr "las alineaciones más grandes que 32 bytes no tienen soporte en la sección text."
 
-#: config/tc-arm.c:10193
-msgid "use of old and new-style options to set FPU type"
-msgstr "se utilizan opciones de estilo antiguo y nuevo para establecer el tipo de FPU"
+#: config/tc-arm.c:10634
+msgid "handerdata in cantunwind frame"
+msgstr "handerdata en un marco cantunwind"
 
-#: config/tc-arm.c:10473
-msgid "bad call to MD_ATOF()"
-msgstr "llamada errónea a MD_ATOF()"
+#: config/tc-arm.c:10651
+msgid "too many unwind opcodes for personality routine 0"
+msgstr "demasiados códigos de operación de desenredo para la rutina personality 0"
+
+#: config/tc-arm.c:10683
+msgid "too many unwind opcodes"
+msgstr "demasiados códigos de operación de desenredo"
 
-#: config/tc-arm.c:10703
+#: config/tc-arm.c:11085 config/tc-arm.c:11365
+#, c-format
+msgid "undefined symbol %s used as an immediate value"
+msgstr "se usa el símbolo %s indefinido como un valor inmediato"
+
+#: config/tc-arm.c:11099 config/tc-arm.c:11394
 #, c-format
 msgid "invalid constant (%lx) after fixup"
 msgstr "constante inválidoa (%lx) después de la compostura"
 
-#: config/tc-arm.c:10741
+#: config/tc-arm.c:11136
 #, c-format
 msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
 msgstr "no se pueden calcular las instrucciones ADRL para el desplazamiento de PC de 0x%lx"
 
-#: config/tc-arm.c:10771
+#: config/tc-arm.c:11168 config/tc-arm.c:11193
+msgid "invalid literal constant: pool needs to be closer"
+msgstr "constante literal inválida: el conjunto necesita estar más cerca"
+
+#: config/tc-arm.c:11171 config/tc-arm.c:11209
 #, c-format
 msgid "bad immediate value for offset (%ld)"
 msgstr "valor inmediato erróneo para el desplazamiento (%ld)"
 
-#: config/tc-arm.c:10793 config/tc-arm.c:10815
-msgid "invalid literal constant: pool needs to be closer"
-msgstr "constante literal inválida: el conjunto necesita estar más cerca"
-
-#: config/tc-arm.c:10795
+#: config/tc-arm.c:11195
 #, c-format
 msgid "bad immediate value for half-word offset (%ld)"
 msgstr "valor inmediato erróneo para el desplazamiento half-word (%ld)"
 
-#: config/tc-arm.c:10832
-msgid "shift expression is too large"
-msgstr "la expresión de desplazamiento es demasiado grande"
+#: config/tc-arm.c:11250
+msgid "offset not a multiple of 4"
+msgstr "el desplazamiento no es un múltiplo de 4"
+
+#: config/tc-arm.c:11257 config/tc-arm.c:11272 config/tc-arm.c:11287
+#: config/tc-arm.c:11298 config/tc-arm.c:11321 config/tc-pj.c:499
+#: config/tc-sh.c:4084
+msgid "offset out of range"
+msgstr "desplazamiento fuera de rango"
+
+#: config/tc-arm.c:11410
+msgid "invalid smc expression"
+msgstr "expresión smc inválida"
 
-#: config/tc-arm.c:10851 config/tc-arm.c:10860
+#: config/tc-arm.c:11421 config/tc-arm.c:11430
 msgid "invalid swi expression"
 msgstr "expresión swi inválida"
 
-#: config/tc-arm.c:10870
+#: config/tc-arm.c:11440
 msgid "invalid expression in load/store multiple"
 msgstr "expresión inválida en load/store múltiples"
 
-#: config/tc-arm.c:10923
-msgid "GAS can't handle same-section branch dest >= 0x04000000"
-msgstr "GAS no puede manejar un destino de ramificación en la misma sección >= 0x04000000"
+#: config/tc-arm.c:11455
+msgid "misaligned branch destination"
+msgstr "destinaciones ramificadas desalineadas"
 
-#: config/tc-arm.c:10932
-msgid "out of range branch"
-msgstr "ramificación fuera de rango"
-
-#: config/tc-arm.c:10965 config/tc-arm.c:10981
+#: config/tc-arm.c:11459 config/tc-arm.c:11479 config/tc-arm.c:11497
+#: config/tc-arm.c:11510 config/tc-arm.c:11523 config/tc-arm.c:11562
+#: config/tc-arm.c:11587
 msgid "branch out of range"
 msgstr "ramificación fuera de rango"
 
-#: config/tc-arm.c:11005
-msgid "branch with link out of range"
-msgstr "ramificación con enlace fuera de rango"
+#: config/tc-arm.c:11475
+msgid "misaligned BLX destination"
+msgstr "destino BLX desalineado"
+
+#: config/tc-arm.c:11536
+msgid "conditional branch out of range"
+msgstr "ramificación condicional fuera de rango"
 
-#: config/tc-arm.c:11074
-msgid "illegal value for co-processor offset"
-msgstr "valor ilegal para el desplazamiento del co-procesador"
+#: config/tc-arm.c:11657
+msgid "rel31 relocation overflow"
+msgstr "desbordamiento de reubicación rel31"
 
-#: config/tc-arm.c:11086
-msgid "Illegal value for co-processor offset"
-msgstr "Valor ilegal para el desplazamiento del co-procesador"
+#: config/tc-arm.c:11669 config/tc-arm.c:11694
+msgid "co-processor offset out of range"
+msgstr "desplazamiento de coprocesador fuera de rango"
 
-#: config/tc-arm.c:11110
+#: config/tc-arm.c:11710
 #, c-format
-msgid "invalid offset, target not word aligned (0x%08X)"
-msgstr "desplazamiento inválido, el objetivo no está alineado a word (0x%08X)"
+msgid "invalid offset, target not word aligned (0x%08lX)"
+msgstr "desplazamiento inválido, el objetivo no está alineado a word (0x%08lX)"
 
-#: config/tc-arm.c:11116 config/tc-arm.c:11126 config/tc-arm.c:11134
-#: config/tc-arm.c:11142 config/tc-arm.c:11150
+#: config/tc-arm.c:11716 config/tc-arm.c:11725 config/tc-arm.c:11733
+#: config/tc-arm.c:11741 config/tc-arm.c:11749
 #, c-format
 msgid "invalid offset, value too big (0x%08lX)"
 msgstr "desplazamiento inválido, valor demasiado grande (0x%08lX)"
 
-#: config/tc-arm.c:11190
+#: config/tc-arm.c:11790
+msgid "invalid Hi register with immediate"
+msgstr "registro Hi inválido con el inmediato"
+
+#: config/tc-arm.c:11806
 msgid "invalid immediate for stack address calculation"
 msgstr "inmediato inválido para el cálculo de la dirección de la pila"
 
-#: config/tc-arm.c:11199
+#: config/tc-arm.c:11814
 #, c-format
 msgid "invalid immediate for address calculation (value = 0x%08lX)"
 msgstr "inmediato inválido para el cálculo de la dirección (valor = 0x%08lX)"
 
-#: config/tc-arm.c:11209
-msgid "invalid 8bit immediate"
-msgstr "inmediato de 8bit inválido"
-
-#: config/tc-arm.c:11217
-msgid "invalid 3bit immediate"
-msgstr "inmediato de 3bit inválido"
-
-#: config/tc-arm.c:11233
+#: config/tc-arm.c:11844
 #, c-format
 msgid "invalid immediate: %ld is too large"
 msgstr "inmediato inválido: %ld es demasiado grande"
 
-#: config/tc-arm.c:11248
+#: config/tc-arm.c:11856
 #, c-format
-msgid "illegal Thumb shift value: %ld"
-msgstr "valor de desplazamiento Thumb ilegal: %ld"
+msgid "invalid shift value: %ld"
+msgstr "valor de desplazamiento inválid: %ld"
 
-#: config/tc-arm.c:11262
+#: config/tc-arm.c:11875
 #, c-format
 msgid "bad relocation fixup type (%d)"
 msgstr "tipo de compostura de reubicación inválido (%d)"
 
-#: config/tc-arm.c:11333
+#: config/tc-arm.c:11943
 msgid "literal referenced across section boundary"
 msgstr "se referencía una literal a través de un límite de sección"
 
-#: config/tc-arm.c:11346
+#: config/tc-arm.c:11973
 msgid "internal relocation (type: IMMEDIATE) not fixed up"
 msgstr "reubicación interna (tipo: IMMEDIATE) no compuesta"
 
-#: config/tc-arm.c:11351
+#: config/tc-arm.c:11978
 msgid "ADRL used for a symbol not defined in the same file"
 msgstr "se utiliza ADRL para un símbolo que no está definido en el mismo fichero"
 
-#: config/tc-arm.c:11356
+#: config/tc-arm.c:11987
+#, c-format
+msgid "undefined local label `%s'"
+msgstr "etiqueta local `%s' sin definir"
+
+#: config/tc-arm.c:11993
 msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
 msgstr "reubicación_interna (tipo OFFSET_IMM) no compuesta"
 
-#: config/tc-arm.c:11374 config/tc-cris.c:3063 config/tc-mcore.c:2052
-#: config/tc-mmix.c:2867 config/tc-ns32k.c:2396
+#: config/tc-arm.c:12014 config/tc-cris.c:3869 config/tc-mcore.c:1995
+#: config/tc-mmix.c:2888 config/tc-ns32k.c:2284
 msgid "<unknown>"
 msgstr "<desconocido>"
 
-#: config/tc-arm.c:11377 config/tc-arm.c:11398
+#: config/tc-arm.c:12017 config/tc-arm.c:12038
 #, c-format
 msgid "cannot represent %s relocation in this object file format"
 msgstr "no se puede representar la reubicación %s en este formato de fichero objeto"
 
-#: config/tc-arm.c:11494
+#: config/tc-arm.c:12254
 #, c-format
-msgid "no operator -- statement `%s'\n"
-msgstr "no hay operador -- declaración `%s'\n"
+msgid "%s: unexpected function type: %d"
+msgstr "%s: tipo de función inesperado: %d"
 
-#: config/tc-arm.c:11512 config/tc-arm.c:11537
-#, c-format
-msgid "selected processor does not support `%s'"
-msgstr "el procesador seleccionado no tiene soporte para `%s'"
+#: config/tc-arm.c:12331
+msgid "virtual memory exhausted"
+msgstr "memoria agotada"
 
-#: config/tc-arm.c:11554
-#, c-format
-msgid "bad instruction `%s'"
-msgstr "instrucción `%s' errónea"
+#: config/tc-arm.c:12357
+msgid "use of old and new-style options to set CPU type"
+msgstr "se utilizan opciones de estilo antiguo y nuevo para establecer el tipo de CPU"
+
+#: config/tc-arm.c:12367
+msgid "use of old and new-style options to set FPU type"
+msgstr "se utilizan opciones de estilo antiguo y nuevo para establecer el tipo de FPU"
+
+#: config/tc-arm.c:12441
+msgid "hard-float conflicts with specified fpu"
+msgstr "hard-float tiene conflictos con la unidad de coma flotante (fpu) especificada"
 
-#: config/tc-arm.c:11655
+#: config/tc-arm.c:12633
 msgid "generate PIC code"
 msgstr "genera código PIC"
 
-#: config/tc-arm.c:11656
+#: config/tc-arm.c:12634
 msgid "assemble Thumb code"
 msgstr "ensambla código Thumb"
 
-#: config/tc-arm.c:11657
+#: config/tc-arm.c:12635
 msgid "support ARM/Thumb interworking"
 msgstr "soporta la interoperación ARM/Thumb"
 
-#: config/tc-arm.c:11659
-msgid "use old ABI (ELF only)"
-msgstr "usa la ABI antigua (solamente ELF)"
-
-#: config/tc-arm.c:11660
+#: config/tc-arm.c:12637
 msgid "code uses 32-bit program counter"
 msgstr "el código utiliza un contador de programa de 32-bit"
 
-#: config/tc-arm.c:11661
+#: config/tc-arm.c:12638
 msgid "code uses 26-bit program counter"
 msgstr "el código utiliza un contador de programa de 26-bit"
 
-#: config/tc-arm.c:11662
+#: config/tc-arm.c:12639
 msgid "floating point args are in fp regs"
 msgstr "los argumentos de coma flotante están en los registros de coma flotante"
 
-#: config/tc-arm.c:11664
+#: config/tc-arm.c:12641
 msgid "re-entrant code"
 msgstr "código reentrante"
 
-#: config/tc-arm.c:11665
+#: config/tc-arm.c:12642
 msgid "code is ATPCS conformant"
 msgstr "el código es conforme a ATPCS"
 
-#: config/tc-arm.c:11666
+#: config/tc-arm.c:12643
 msgid "assemble for big-endian"
 msgstr "ensamblar para big-endian"
 
-#: config/tc-arm.c:11667
+#: config/tc-arm.c:12644
 msgid "assemble for little-endian"
 msgstr "ensamblar para little-endian"
 
 #. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:11671
+#: config/tc-arm.c:12648
 msgid "use frame pointer"
-msgstr "usar apuntador de marco"
+msgstr "usar puntero de marco"
 
-#: config/tc-arm.c:11672
+#: config/tc-arm.c:12649
 msgid "use stack size checking"
 msgstr "usar revisión del tamaño de la pila"
 
 #. DON'T add any new processors to this list -- we want the whole list
 #. to go away...  Add them to the processors table instead.
-#: config/tc-arm.c:11676 config/tc-arm.c:11677
+#: config/tc-arm.c:12653 config/tc-arm.c:12654
 msgid "use -mcpu=arm1"
 msgstr "usar -mcpu=arm1"
 
-#: config/tc-arm.c:11678 config/tc-arm.c:11679
+#: config/tc-arm.c:12655 config/tc-arm.c:12656
 msgid "use -mcpu=arm2"
 msgstr "usar -mcpu=arm2"
 
-#: config/tc-arm.c:11680 config/tc-arm.c:11681
+#: config/tc-arm.c:12657 config/tc-arm.c:12658
 msgid "use -mcpu=arm250"
 msgstr "usar -mcpu=arm250"
 
-#: config/tc-arm.c:11682 config/tc-arm.c:11683
+#: config/tc-arm.c:12659 config/tc-arm.c:12660
 msgid "use -mcpu=arm3"
 msgstr "usar -mcpu=arm3"
 
-#: config/tc-arm.c:11684 config/tc-arm.c:11685
+#: config/tc-arm.c:12661 config/tc-arm.c:12662
 msgid "use -mcpu=arm6"
 msgstr "usar -mcpu=arm6"
 
-#: config/tc-arm.c:11686 config/tc-arm.c:11687
+#: config/tc-arm.c:12663 config/tc-arm.c:12664
 msgid "use -mcpu=arm600"
 msgstr "usar -mcpu=arm600"
 
-#: config/tc-arm.c:11688 config/tc-arm.c:11689
+#: config/tc-arm.c:12665 config/tc-arm.c:12666
 msgid "use -mcpu=arm610"
 msgstr "usar -mcpu=arm610"
 
-#: config/tc-arm.c:11690 config/tc-arm.c:11691
+#: config/tc-arm.c:12667 config/tc-arm.c:12668
 msgid "use -mcpu=arm620"
 msgstr "usar -mcpu=arm620"
 
-#: config/tc-arm.c:11692 config/tc-arm.c:11693
+#: config/tc-arm.c:12669 config/tc-arm.c:12670
 msgid "use -mcpu=arm7"
 msgstr "usar -mcpu=arm7"
 
-#: config/tc-arm.c:11694 config/tc-arm.c:11695
+#: config/tc-arm.c:12671 config/tc-arm.c:12672
 msgid "use -mcpu=arm70"
 msgstr "usar -mcpu=arm70"
 
-#: config/tc-arm.c:11696 config/tc-arm.c:11697
+#: config/tc-arm.c:12673 config/tc-arm.c:12674
 msgid "use -mcpu=arm700"
 msgstr "usar -mcpu=arm700"
 
-#: config/tc-arm.c:11698 config/tc-arm.c:11699
+#: config/tc-arm.c:12675 config/tc-arm.c:12676
 msgid "use -mcpu=arm700i"
 msgstr "usar -mcpu=arm700i"
 
-#: config/tc-arm.c:11700 config/tc-arm.c:11701
+#: config/tc-arm.c:12677 config/tc-arm.c:12678
 msgid "use -mcpu=arm710"
 msgstr "usar -mcpu=arm710"
 
-#: config/tc-arm.c:11702 config/tc-arm.c:11703
+#: config/tc-arm.c:12679 config/tc-arm.c:12680
 msgid "use -mcpu=arm710c"
 msgstr "usar -mcpu=arm710c"
 
-#: config/tc-arm.c:11704 config/tc-arm.c:11705
+#: config/tc-arm.c:12681 config/tc-arm.c:12682
 msgid "use -mcpu=arm720"
 msgstr "usar -mcpu=arm720"
 
-#: config/tc-arm.c:11706 config/tc-arm.c:11707
+#: config/tc-arm.c:12683 config/tc-arm.c:12684
 msgid "use -mcpu=arm7d"
 msgstr "usar -mcpu=arm7d"
 
-#: config/tc-arm.c:11708 config/tc-arm.c:11709
+#: config/tc-arm.c:12685 config/tc-arm.c:12686
 msgid "use -mcpu=arm7di"
 msgstr "usar -mcpu=arm7di"
 
-#: config/tc-arm.c:11710 config/tc-arm.c:11711
+#: config/tc-arm.c:12687 config/tc-arm.c:12688
 msgid "use -mcpu=arm7m"
 msgstr "usar -mcpu=arm7m"
 
-#: config/tc-arm.c:11712 config/tc-arm.c:11713
+#: config/tc-arm.c:12689 config/tc-arm.c:12690
 msgid "use -mcpu=arm7dm"
 msgstr "usar -mcpu=arm7dm"
 
-#: config/tc-arm.c:11714 config/tc-arm.c:11715
+#: config/tc-arm.c:12691 config/tc-arm.c:12692
 msgid "use -mcpu=arm7dmi"
 msgstr "usar -mcpu=arm7dmi"
 
-#: config/tc-arm.c:11716 config/tc-arm.c:11717
+#: config/tc-arm.c:12693 config/tc-arm.c:12694
 msgid "use -mcpu=arm7100"
 msgstr "usar -mcpu=arm7100"
 
-#: config/tc-arm.c:11718 config/tc-arm.c:11719
+#: config/tc-arm.c:12695 config/tc-arm.c:12696
 msgid "use -mcpu=arm7500"
 msgstr "usar -mcpu=arm7500"
 
-#: config/tc-arm.c:11720 config/tc-arm.c:11721
+#: config/tc-arm.c:12697 config/tc-arm.c:12698
 msgid "use -mcpu=arm7500fe"
 msgstr "usar -mcpu=arm7500fe"
 
-#: config/tc-arm.c:11722 config/tc-arm.c:11723 config/tc-arm.c:11724
-#: config/tc-arm.c:11725
+#: config/tc-arm.c:12699 config/tc-arm.c:12700 config/tc-arm.c:12701
+#: config/tc-arm.c:12702
 msgid "use -mcpu=arm7tdmi"
 msgstr "usar -mcpu=arm7tdmi"
 
-#: config/tc-arm.c:11726 config/tc-arm.c:11727
+#: config/tc-arm.c:12703 config/tc-arm.c:12704
 msgid "use -mcpu=arm710t"
 msgstr "usar -mcpu=arm710t"
 
-#: config/tc-arm.c:11728 config/tc-arm.c:11729
+#: config/tc-arm.c:12705 config/tc-arm.c:12706
 msgid "use -mcpu=arm720t"
 msgstr "usar -mcpu=arm720t"
 
-#: config/tc-arm.c:11730 config/tc-arm.c:11731
+#: config/tc-arm.c:12707 config/tc-arm.c:12708
 msgid "use -mcpu=arm740t"
 msgstr "usar -mcpu=arm740t"
 
-#: config/tc-arm.c:11732 config/tc-arm.c:11733
+#: config/tc-arm.c:12709 config/tc-arm.c:12710
 msgid "use -mcpu=arm8"
 msgstr "usar -mcpu=arm8"
 
-#: config/tc-arm.c:11734 config/tc-arm.c:11735
+#: config/tc-arm.c:12711 config/tc-arm.c:12712
 msgid "use -mcpu=arm810"
 msgstr "usar -mcpu=arm810"
 
-#: config/tc-arm.c:11736 config/tc-arm.c:11737
+#: config/tc-arm.c:12713 config/tc-arm.c:12714
 msgid "use -mcpu=arm9"
 msgstr "usar -mcpu=arm9"
 
-#: config/tc-arm.c:11738 config/tc-arm.c:11739
+#: config/tc-arm.c:12715 config/tc-arm.c:12716
 msgid "use -mcpu=arm9tdmi"
 msgstr "usar -mcpu=arm9tdmi"
 
-#: config/tc-arm.c:11740 config/tc-arm.c:11741
+#: config/tc-arm.c:12717 config/tc-arm.c:12718
 msgid "use -mcpu=arm920"
 msgstr "usar -mcpu=arm920"
 
-#: config/tc-arm.c:11742 config/tc-arm.c:11743
+#: config/tc-arm.c:12719 config/tc-arm.c:12720
 msgid "use -mcpu=arm940"
 msgstr "usar -mcpu=arm940"
 
-#: config/tc-arm.c:11744
+#: config/tc-arm.c:12721
 msgid "use -mcpu=strongarm"
 msgstr "usar -mcpu=strongarm"
 
-#: config/tc-arm.c:11746
+#: config/tc-arm.c:12723
 msgid "use -mcpu=strongarm110"
 msgstr "usar -mcpu=strongarm110"
 
-#: config/tc-arm.c:11748
+#: config/tc-arm.c:12725
 msgid "use -mcpu=strongarm1100"
 msgstr "usar -mcpu=strongarm1100"
 
-#: config/tc-arm.c:11750
+#: config/tc-arm.c:12727
 msgid "use -mcpu=strongarm1110"
 msgstr "usar -mcpu=strongarm1110"
 
-#: config/tc-arm.c:11751
+#: config/tc-arm.c:12728
 msgid "use -mcpu=xscale"
 msgstr "usar -mcpu=xscale"
 
-#: config/tc-arm.c:11752
+#: config/tc-arm.c:12729
 msgid "use -mcpu=iwmmxt"
 msgstr "usar -mcpu=iwmmxt"
 
-#: config/tc-arm.c:11753
+#: config/tc-arm.c:12730
 msgid "use -mcpu=all"
 msgstr "usar -mcpu=all"
 
 #. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:11756 config/tc-arm.c:11757
+#: config/tc-arm.c:12733 config/tc-arm.c:12734
 msgid "use -march=armv2"
 msgstr "usar -march=armv2"
 
-#: config/tc-arm.c:11758 config/tc-arm.c:11759
+#: config/tc-arm.c:12735 config/tc-arm.c:12736
 msgid "use -march=armv2a"
 msgstr "usar -march=armv2a"
 
-#: config/tc-arm.c:11760 config/tc-arm.c:11761
+#: config/tc-arm.c:12737 config/tc-arm.c:12738
 msgid "use -march=armv3"
 msgstr "usar -march=armv3"
 
-#: config/tc-arm.c:11762 config/tc-arm.c:11763
+#: config/tc-arm.c:12739 config/tc-arm.c:12740
 msgid "use -march=armv3m"
 msgstr "usar -march=armv3m"
 
-#: config/tc-arm.c:11764 config/tc-arm.c:11765
+#: config/tc-arm.c:12741 config/tc-arm.c:12742
 msgid "use -march=armv4"
 msgstr "usar -march=armv4"
 
-#: config/tc-arm.c:11766 config/tc-arm.c:11767
+#: config/tc-arm.c:12743 config/tc-arm.c:12744
 msgid "use -march=armv4t"
 msgstr "usar -march=armv4t"
 
-#: config/tc-arm.c:11768 config/tc-arm.c:11769
+#: config/tc-arm.c:12745 config/tc-arm.c:12746
 msgid "use -march=armv5"
 msgstr "usar -march=armv5"
 
-#: config/tc-arm.c:11770 config/tc-arm.c:11771
+#: config/tc-arm.c:12747 config/tc-arm.c:12748
 msgid "use -march=armv5t"
 msgstr "usar -march=armv5t"
 
-#: config/tc-arm.c:11772 config/tc-arm.c:11773
+#: config/tc-arm.c:12749 config/tc-arm.c:12750
 msgid "use -march=armv5te"
 msgstr "usar -march=armv5te"
 
 #. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:11776
+#: config/tc-arm.c:12753
 msgid "use -mfpu=fpe"
 msgstr "usar -mfpu=fpe"
 
-#: config/tc-arm.c:11777
+#: config/tc-arm.c:12754
 msgid "use -mfpu=fpa10"
 msgstr "usar -mfpu=fpa10"
 
-#: config/tc-arm.c:11778
+#: config/tc-arm.c:12755
 msgid "use -mfpu=fpa11"
 msgstr "usar -mfpu=fpa11"
 
-#: config/tc-arm.c:11780
+#: config/tc-arm.c:12757
 msgid "use either -mfpu=softfpa or -mfpu=softvfp"
 msgstr "usar -mfpu=softfpa ó -mfpu=softvfp"
 
-#: config/tc-arm.c:11963
+#: config/tc-arm.c:12986
 msgid "invalid architectural extension"
 msgstr "extensión de arquitectura inválida"
 
-#: config/tc-arm.c:11977
+#: config/tc-arm.c:13000
 msgid "missing architectural extension"
 msgstr "falta la extensión de la arquitectura"
 
-#: config/tc-arm.c:11990
+#: config/tc-arm.c:13013
 #, c-format
 msgid "unknown architectural extnsion `%s'"
 msgstr "extensión de arquitectura `%s' desconocida"
 
-#: config/tc-arm.c:12015
+#: config/tc-arm.c:13037
 #, c-format
 msgid "missing cpu name `%s'"
 msgstr "falta el nombre de cpu `%s'"
 
-#: config/tc-arm.c:12031
+#: config/tc-arm.c:13062 config/tc-arm.c:13389
 #, c-format
 msgid "unknown cpu `%s'"
 msgstr "cpu `%s' desconocido"
 
-#: config/tc-arm.c:12050
+#: config/tc-arm.c:13080
 #, c-format
 msgid "missing architecture name `%s'"
 msgstr "falta el nombre de arquitectura `%s'"
 
-#: config/tc-arm.c:12067
+#: config/tc-arm.c:13097 config/tc-arm.c:13423
 #, c-format
 msgid "unknown architecture `%s'\n"
 msgstr "arquitectura `%s' desconocida\n"
 
-#: config/tc-arm.c:12084
+#: config/tc-arm.c:13113 config/tc-arm.c:13454
 #, c-format
 msgid "unknown floating point format `%s'\n"
 msgstr "formato de coma flotante `%s' desconocido\n"
 
-#: config/tc-arm.c:12090
+#: config/tc-arm.c:13129
+#, c-format
+msgid "unknown floating point abi `%s'\n"
+msgstr "abi de coma flotante `%s' desconocida\n"
+
+#: config/tc-arm.c:13145
+#, c-format
+msgid "unknown EABI `%s'\n"
+msgstr "EABI `%s' desconocida\n"
+
+#: config/tc-arm.c:13152
 msgid "<cpu name>\t  assemble for CPU <cpu name>"
 msgstr "<nombre cpu>\t  ensamblar para el CPU <nombre cpu>"
 
-#: config/tc-arm.c:12092
+#: config/tc-arm.c:13154
 msgid "<arch name>\t  assemble for architecture <arch name>"
 msgstr "<nombre arq>\t  ensamblar para la arquitectura <nombre arq>"
 
-#: config/tc-arm.c:12094
+#: config/tc-arm.c:13156
 msgid "<fpu name>\t  assemble for FPU architecture <fpu name>"
 msgstr "<nombre fpu>\t  ensamblar para la arquitectura de Unidad de Coma Flotante <nombre fpu>"
 
-#: config/tc-arm.c:12136 config/tc-arm.c:12158
+#: config/tc-arm.c:13158
+msgid "<abi>\t  assemble for floating point ABI <abi>"
+msgstr "<abi>\t  ensamblar para la ABI de coma flotante <abi>"
+
+#: config/tc-arm.c:13161
+msgid "<ver>\t  assemble for eabi version <ver>"
+msgstr "<ver>\t  ensamblar para la eabi versión <ver>"
+
+#: config/tc-arm.c:13202 config/tc-arm.c:13224
 #, c-format
 msgid "option `-%c%s' is deprecated: %s"
-msgstr "la opción `-%c%s' está deprecada: %s"
+msgstr "la opción `-%c%s' es obsoleta: %s"
 
-#: config/tc-arm.c:12167
+#: config/tc-arm.c:13245
 #, c-format
-msgid "unrecognized option `-%c%s'"
-msgstr "opción `-%c%s' no reconocida"
-
-#: config/tc-arm.c:12181
 msgid " ARM-specific assembler options:\n"
 msgstr "Opciones de ensamblador específicas de ARM:\n"
 
-#: config/tc-arm.c:12192
+#: config/tc-arm.c:13256
+#, c-format
 msgid "  -EB                     assemble code for a big-endian cpu\n"
 msgstr "  -EB                     ensambla código para un cpu big-endian\n"
 
-#: config/tc-arm.c:12197
+#: config/tc-arm.c:13261
+#, c-format
 msgid "  -EL                     assemble code for a little-endian cpu\n"
 msgstr "  -EL                     ensambla código para un cpu little-endian\n"
 
-#: config/tc-arm.c:12381
+#: config/tc-avr.c:209
 #, c-format
-msgid "%s: unexpected function type: %d"
-msgstr "%s: tipo de función inesperado: %d"
-
-#: config/tc-arm.c:12756
-msgid "alignments greater than 32 bytes not supported in .text sections."
-msgstr "las alineaciones más grandes que 32 bytes no tienen soporte en la sección text."
-
-#: config/tc-arm.h:98
-msgid "arm convert_frag\n"
-msgstr "convert_frag de arm\n"
-
-#: config/tc-avr.c:203
 msgid "Known MCU names:"
 msgstr "Nombres MCU conocidos:"
 
-#: config/tc-avr.c:272
+#: config/tc-avr.c:275
+#, c-format
 msgid ""
 "AVR options:\n"
 "  -mmcu=[avr-name] select microcontroller variant\n"
@@ -2703,7 +2722,8 @@ msgstr ""
 "                   avr5 - ATmega161, ATmega163, ATmega32, AT94K\n"
 "                   o el nombre inmediato del microcontrolador.\n"
 
-#: config/tc-avr.c:282
+#: config/tc-avr.c:285
+#, c-format
 msgid ""
 "  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
 "  -mno-skip-bug    disable warnings for skipping two-word instructions\n"
@@ -2714,388 +2734,675 @@ msgstr ""
 "  -mall-opcodes    acepta todos los códigos de operación AVR, aún si no\n"
 "                   tienen soporte por el MCU\n"
 "  -mno-skip-bug    desactiva los avisos para las instrucciones que saltan\n"
-"                   dos palabras (por omisión para avr4, avr5)\n"
+"                   dos palabras (por defecto para avr4, avr5)\n"
 "  -mno-wrap        rechaza las instrucciones rjmp/rcall con envoltura de 8K\n"
-"                   (por omisión para avr3, avr5)\n"
+"                   (por defecto para avr3, avr5)\n"
 
-#: config/tc-avr.c:330 config/tc-msp430.c:257
+#: config/tc-avr.c:329 config/tc-msp430.c:749
 #, c-format
 msgid "unknown MCU: %s\n"
 msgstr "MCU desconocido: %s\n"
 
-#: config/tc-avr.c:339
+#: config/tc-avr.c:338
 #, c-format
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr "redefinición del tipo de mcu `%s' a `%s'"
 
-#: config/tc-avr.c:390 config/tc-d10v.c:319 config/tc-d30v.c:365
-#: config/tc-mips.c:10136 config/tc-mmix.c:2246 config/tc-mn10200.c:361
-#: config/tc-msp430.c:378 config/tc-pj.c:374 config/tc-ppc.c:5105
-#: config/tc-sh.c:2528 config/tc-v850.c:1245
+#: config/tc-avr.c:385 config/tc-crx.c:491 config/tc-d10v.c:278
+#: config/tc-d30v.c:312 config/tc-mips.c:10241 config/tc-mmix.c:2264
+#: config/tc-mn10200.c:342 config/tc-msp430.c:873 config/tc-pj.c:342
+#: config/tc-ppc.c:5211 config/tc-sh.c:2986 config/tc-v850.c:1199
 msgid "bad call to md_atof"
 msgstr "llamada errónea a md_atof"
 
-#: config/tc-avr.c:453
+#: config/tc-avr.c:447
 msgid "constant value required"
 msgstr "se requiere un valor constante"
 
-#: config/tc-avr.c:456
+#: config/tc-avr.c:450
 #, c-format
 msgid "number must be less than %d"
 msgstr "el número debe ser menor que %d"
 
-#: config/tc-avr.c:508
-msgid "`,' required"
-msgstr "se requiere `,'"
+#: config/tc-avr.c:476 config/tc-avr.c:583
+#, c-format
+msgid "constant out of 8-bit range: %d"
+msgstr "constante fuera del rango de 8-bit: %d"
 
-#: config/tc-avr.c:527
-msgid "undefined combination of operands"
-msgstr "combinación indefinida de operandos"
+#: config/tc-avr.c:488 config/tc-d10v.c:498 config/tc-d30v.c:490
+#: config/tc-h8300.c:451 config/tc-mcore.c:665 config/tc-mmix.c:489
+#: config/tc-mn10200.c:1078 config/tc-mn10300.c:1820 config/tc-msp430.c:457
+#: config/tc-or32.c:306 config/tc-ppc.c:2382 config/tc-s390.c:1220
+#: config/tc-sh64.c:2213 config/tc-sh.c:1272 config/tc-v850.c:1952
+#: config/tc-z8k.c:328
+msgid "missing operand"
+msgstr "operando faltante"
 
-#: config/tc-avr.c:536
-msgid "skipping two-word instruction"
-msgstr "instrucción que salta dos palabras"
+#: config/tc-avr.c:536 read.c:3345
+msgid "illegal expression"
+msgstr "expresión ilegal"
 
-#: config/tc-avr.c:598
+#: config/tc-avr.c:562 config/tc-avr.c:1282
+msgid "`)' required"
+msgstr "se requiere `)'"
+
+#: config/tc-avr.c:638
 msgid "register r16-r23 required"
 msgstr "se requiere los registros r16-r23"
 
-#: config/tc-avr.c:604
+#: config/tc-avr.c:644
 msgid "register number above 15 required"
 msgstr "se requiere un número de registro superior a 15"
 
-#: config/tc-avr.c:610
+#: config/tc-avr.c:650
 msgid "even register number required"
 msgstr "se requieren números de registro par"
 
-#: config/tc-avr.c:616
+#: config/tc-avr.c:656
 msgid "register r24, r26, r28 or r30 required"
 msgstr "se requieren los registros r24, r26, r28 o r30"
 
-#: config/tc-avr.c:622
+#: config/tc-avr.c:662
 msgid "register name or number from 0 to 31 required"
 msgstr "se requiere un nombre de registro o un número del 0 al 31"
 
-#: config/tc-avr.c:640
+#: config/tc-avr.c:680
 msgid "pointer register (X, Y or Z) required"
-msgstr "se requiere un registro apuntador (X, Y o Z)"
+msgstr "se requiere un registro puntero (X, Y o Z)"
 
-#: config/tc-avr.c:647
+#: config/tc-avr.c:687
 msgid "cannot both predecrement and postincrement"
 msgstr "no se puede predecrementar y postincrementar"
 
-#: config/tc-avr.c:655
+#: config/tc-avr.c:695
 msgid "addressing mode not supported"
 msgstr "el modo de direccionamiento no tiene soporte"
 
-#: config/tc-avr.c:661
+#: config/tc-avr.c:701
 msgid "can't predecrement"
 msgstr "no se puede predecrementar"
 
-#: config/tc-avr.c:664
+#: config/tc-avr.c:704
 msgid "pointer register Z required"
-msgstr "se requiere el registro apuntador Z"
+msgstr "se requiere el registro puntero Z"
 
-#: config/tc-avr.c:682
+#: config/tc-avr.c:722
 msgid "pointer register (Y or Z) required"
-msgstr "se requiere un registro apuntador (Y o Z)"
+msgstr "se requiere un registro puntero (Y o Z)"
 
-#: config/tc-avr.c:787
+#: config/tc-avr.c:826
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr "restricción `%c' desconocida"
 
-#: config/tc-avr.c:881 config/tc-avr.c:897 config/tc-avr.c:998
-#: config/tc-msp430.c:1431 config/tc-msp430.c:1448
+#: config/tc-avr.c:878
+msgid "`,' required"
+msgstr "se requiere `,'"
+
+#: config/tc-avr.c:896
+msgid "undefined combination of operands"
+msgstr "combinación indefinida de operandos"
+
+#: config/tc-avr.c:905
+msgid "skipping two-word instruction"
+msgstr "instrucción que salta dos palabras"
+
+#: config/tc-avr.c:997 config/tc-avr.c:1013 config/tc-avr.c:1135
+#: config/tc-msp430.c:2012 config/tc-msp430.c:2030
 #, c-format
 msgid "odd address operand: %ld"
 msgstr "operando de direccón impar: %ld"
 
-#: config/tc-avr.c:889 config/tc-avr.c:908 config/tc-d10v.c:586
-#: config/tc-d30v.c:655 config/tc-msp430.c:1439 config/tc-msp430.c:1453
-#: config/tc-msp430.c:1463
+#: config/tc-avr.c:1005 config/tc-avr.c:1024 config/tc-avr.c:1046
+#: config/tc-avr.c:1053 config/tc-avr.c:1060 config/tc-d10v.c:538
+#: config/tc-d30v.c:589 config/tc-msp430.c:2020 config/tc-msp430.c:2035
+#: config/tc-msp430.c:2045
 #, c-format
 msgid "operand out of range: %ld"
 msgstr "operando fuera de rango: %ld"
 
-#: config/tc-avr.c:1007 config/tc-d10v.c:1793 config/tc-d30v.c:1973
-#: config/tc-msp430.c:1481
+#: config/tc-avr.c:1144 config/tc-d10v.c:1622 config/tc-d30v.c:2060
+#: config/tc-msp430.c:2063
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr "línea %d: tipo de reubicación desconocido: 0x%x"
 
-#: config/tc-avr.c:1021
+#: config/tc-avr.c:1158
 msgid "only constant expression allowed"
 msgstr "sólo se permite una expresión constante"
 
-#: config/tc-avr.c:1057 config/tc-d10v.c:1659 config/tc-d30v.c:1806
-#: config/tc-mn10200.c:1255 config/tc-mn10300.c:2303 config/tc-msp430.c:1520
-#: config/tc-or32.c:1618 config/tc-ppc.c:5919 config/tc-v850.c:2264
+#. xgettext:c-format.
+#: config/tc-avr.c:1192 config/tc-bfin.c:689 config/tc-d10v.c:1494
+#: config/tc-d30v.c:1804 config/tc-mn10200.c:814 config/tc-mn10300.c:2308
+#: config/tc-msp430.c:2098 config/tc-or32.c:1019 config/tc-ppc.c:6064
+#: config/tc-v850.c:2190
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr "la reubicación %d no tiene soporte por el formato del fichero objeto"
 
-#: config/tc-avr.c:1081 config/tc-d10v.c:1248 config/tc-d10v.c:1262
-#: config/tc-h8300.c:1915 config/tc-h8500.c:1106 config/tc-mcore.c:938
-#: config/tc-msp430.c:438 config/tc-pj.c:283 config/tc-sh.c:2096
-#: config/tc-z8k.c:1238
+#: config/tc-avr.c:1215 config/tc-d10v.c:1782 config/tc-d10v.c:1796
+#: config/tc-h8300.c:1868 config/tc-mcore.c:884 config/tc-msp430.c:1862
+#: config/tc-pj.c:254 config/tc-sh.c:2457 config/tc-z8k.c:1194
 msgid "can't find opcode "
 msgstr "no se puede encontrar el código de operación "
 
-#: config/tc-avr.c:1098
+#: config/tc-avr.c:1232
 #, c-format
 msgid "illegal opcode %s for mcu %s"
 msgstr "código de operación %s ilegal para el mcu %s"
 
-#: config/tc-avr.c:1106
+#: config/tc-avr.c:1241
 msgid "garbage at end of line"
 msgstr "basura al final de la línea"
 
-#: config/tc-avr.c:1170 read.c:3226
-msgid "illegal expression"
-msgstr "expresión ilegal"
-
-#: config/tc-avr.c:1196 config/tc-avr.c:1262
-msgid "`)' required"
-msgstr "se requiere `)'"
-
-#: config/tc-avr.c:1216
-#, c-format
-msgid "constant out of 8-bit range: %d"
-msgstr "constante fuera del rango de 8-bit: %d"
-
-#: config/tc-avr.c:1219
-msgid "expression possibly out of 8-bit range"
-msgstr "expresión posiblemente fuera del rango de 8-bit"
-
-#: config/tc-avr.c:1290 config/tc-avr.c:1297
+#: config/tc-avr.c:1309 config/tc-avr.c:1316
 #, c-format
 msgid "illegal %srelocation size: %d"
 msgstr "%s ilegal tamaño de reubicación: %d"
 
-#: config/tc-cris.c:386 config/tc-m68hc11.c:2831
+#: config/tc-bfin.c:263
+#, c-format
+msgid " BFIN specific command line options:\n"
+msgstr " Opciones de línea de comando específicas de BFIN:\n"
+
+#: config/tc-bfin.c:646 config/tc-fr30.c:358 config/tc-frv.c:1600
+#: config/tc-i960.c:1756 config/tc-ip2k.c:371 config/tc-m32c.c:912
+#: config/tc-m32r.c:2143 config/tc-openrisc.c:376 config/tc-xstormy16.c:631
+msgid "Bad call to md_atof()"
+msgstr "Llamada errónea a md_atof()"
+
+#: config/tc-cris.c:532 config/tc-m68hc11.c:2794
 #, c-format
 msgid "internal inconsistency problem in %s: fr_symbol %lx"
 msgstr "problema de inconsistencia interna en %s: fr_symbol %lx"
 
-#: config/tc-cris.c:390 config/tc-m68hc11.c:2835
+#: config/tc-cris.c:536 config/tc-m68hc11.c:2798 config/tc-msp430.c:2289
 #, c-format
 msgid "internal inconsistency problem in %s: resolved symbol"
 msgstr "problema de inconsistencia interna en %s: símbolo resuelto"
 
-#: config/tc-cris.c:396 config/tc-m68hc11.c:2841
+#: config/tc-cris.c:546 config/tc-m68hc11.c:2804
 #, c-format
 msgid "internal inconsistency problem in %s: fr_subtype %d"
 msgstr "problema de inconsistencia interna en %s: fr_subtype %d"
 
-#: config/tc-cris.c:650
+#: config/tc-cris.c:872
+msgid "Relaxation to long branches for .arch common_v10_v32 not implemented"
+msgstr "La relajación a grandes ramificaciones para .arch common_v10_v32 no está implementada"
+
+#: config/tc-cris.c:902
+msgid "Complicated LAPC target operand is not a multiple of two.  Use LAPC.D"
+msgstr "El operando de objetivo complicado LAPC no es un múltiplo de dos.  Use LAPC.D"
+
+#: config/tc-cris.c:907
+#, c-format
+msgid "Internal error found in md_convert_frag: offset %ld.  Please report this."
+msgstr "Se encontró un error interno en md_convert_frag: desplazamiento %ld.  Por favor repórtelo."
+
+#: config/tc-cris.c:932
 #, c-format
 msgid "internal inconsistency in %s: bdapq no symbol"
 msgstr "inconsistencia interna en %s: bdapq no es un símbolo"
 
-#: config/tc-cris.c:663
+#: config/tc-cris.c:945
 #, c-format
 msgid "internal inconsistency in %s: bdap.w with no symbol"
 msgstr "inconsistencia interna en %s: bdap.w sin algún símbolo"
 
-#: config/tc-cris.c:807
+#: config/tc-cris.c:969
+msgid "section alignment must be >= 4 bytes to check MULS/MULU safeness"
+msgstr "la alineación de la sección debe ser >= 4 bytes para revisar la seguridad de MULS/MULU"
+
+#: config/tc-cris.c:978
+msgid "dangerous MULS/MULU location; give it higher alignment"
+msgstr "ubicación de MULS/MULU peligrosa; déles una alineación superior"
+
+#: config/tc-cris.c:1083
+msgid "Out-of-range .word offset handling is not implemented for .arch common_v10_v32"
+msgstr "El manejo del desplazamiento .word fuera de rango no está implementado para .arch common_v10_v32"
+
+#: config/tc-cris.c:1148 config/tc-crx.c:582 config/tc-crx.c:609
+#: config/tc-crx.c:627
 msgid "Virtual memory exhausted"
 msgstr "Memoria agotada"
 
-#: config/tc-cris.c:815
+#: config/tc-cris.c:1182 config/tc-crx.c:592
 #, c-format
 msgid "Can't hash `%s': %s\n"
 msgstr "No se puede dispersar `%s': %s\n"
 
-#: config/tc-cris.c:816
+#: config/tc-cris.c:1183 config/tc-crx.c:593
 msgid "(unknown reason)"
 msgstr "(razón desconocida)"
 
-#: config/tc-cris.c:820
+#: config/tc-cris.c:1187
 #, c-format
 msgid "Buggy opcode: `%s' \"%s\"\n"
 msgstr "Código de operación defectuoso: `%s' \"%s\"\n"
 
-#: config/tc-cris.c:1164
+#: config/tc-cris.c:1493 config/tc-cris.c:1501 config/tc-crx.c:2029
+#: config/tc-dlx.c:685 config/tc-hppa.c:1625 config/tc-i860.c:492
+#: config/tc-i860.c:509 config/tc-i860.c:989 config/tc-sparc.c:1417
+#: config/tc-sparc.c:1425
+#, c-format
+msgid "Unknown opcode: `%s'"
+msgstr "Código de operación desconocido: `%s'"
+
+#: config/tc-cris.c:1599
 #, c-format
 msgid "Immediate value not in 5 bit unsigned range: %ld"
 msgstr "El valor inmediato no está en el rango de 5 bit sin signo: %ld"
 
-#: config/tc-cris.c:1180
+#: config/tc-cris.c:1615
 #, c-format
 msgid "Immediate value not in 4 bit unsigned range: %ld"
 msgstr "El valor inmediato no está en el rango de 4 bit sin signo: %ld"
 
-#: config/tc-cris.c:1219
+#: config/tc-cris.c:1667
 #, c-format
 msgid "Immediate value not in 6 bit range: %ld"
 msgstr "El valor inmediato no está en el rango de 6 bit: %ld"
 
-#: config/tc-cris.c:1234
+#: config/tc-cris.c:1682
 #, c-format
 msgid "Immediate value not in 6 bit unsigned range: %ld"
 msgstr "El valor inmediato no está en el rango de 6 bit sin signo: %ld"
 
 #. Others have a generic warning.
-#: config/tc-cris.c:1324
+#: config/tc-cris.c:1790
 #, c-format
 msgid "Unimplemented register `%s' specified"
 msgstr "Se especificó el registro sin implementar `%s'"
 
 #. We've come to the end of instructions with this
 #. opcode, so it must be an error.
-#: config/tc-cris.c:1483
+#: config/tc-cris.c:2033
 msgid "Illegal operands"
 msgstr "Operandos ilegales"
 
-#: config/tc-cris.c:1514 config/tc-cris.c:1545
+#: config/tc-cris.c:2074 config/tc-cris.c:2114
 #, c-format
 msgid "Immediate value not in 8 bit range: %ld"
 msgstr "El valor inmediato no está en el rango de 8 bit: %ld"
 
-#: config/tc-cris.c:1524 config/tc-cris.c:1552
+#: config/tc-cris.c:2084 config/tc-cris.c:2135
 #, c-format
 msgid "Immediate value not in 16 bit range: %ld"
 msgstr "El valor inmediato no está en el rango de 16 bit: %ld"
 
-#: config/tc-cris.c:1573
+#: config/tc-cris.c:2119
+#, c-format
+msgid "Immediate value not in 8 bit signed range: %ld"
+msgstr "El valor inmediato no está en el rango de 8 bit con signo: %ld"
+
+#: config/tc-cris.c:2124
+#, c-format
+msgid "Immediate value not in 8 bit unsigned range: %ld"
+msgstr "El valor inmediato no está en el rango de 8 bit sin signo: %ld"
+
+#: config/tc-cris.c:2140
+#, c-format
+msgid "Immediate value not in 16 bit signed range: %ld"
+msgstr "El valor inmediato no está en el rango de 16 bit con signo: %ld"
+
+#: config/tc-cris.c:2145
+#, c-format
+msgid "Immediate value not in 16 bit unsigned range: %ld"
+msgstr "El valor inmediato no está en el rango de 16 bit sin signo: %ld"
+
+#: config/tc-cris.c:2167
 msgid "PIC relocation size does not match operand size"
 msgstr "el tamaño de la reubicación PIC no coincide con el tamaño del operando"
 
-#: config/tc-cris.c:2572
+#: config/tc-cris.c:3304
+msgid "Calling gen_cond_branch_32 for .arch common_v10_v32\n"
+msgstr "Se llama a gen_cond_branch_32 para .arch common_v10_v32\n"
+
+#: config/tc-cris.c:3308
 msgid "32-bit conditional branch generated"
 msgstr "se generó una ramificación condicional de 32-bit"
 
-#: config/tc-cris.c:2626
+#: config/tc-cris.c:3367
 msgid "Complex expression not supported"
 msgstr "Las expresiones complejas no tienen soporte"
 
 #. FIXME:  Is this function mentioned in the internals.texi manual?  If
 #. not, add it.
-#: config/tc-cris.c:2747
+#: config/tc-cris.c:3490
 msgid "Bad call to md_atof () - floating point formats are not supported"
 msgstr "Llamada errónea a md_atof () - no tienen soporte los formatos de coma flotante"
 
-#: config/tc-cris.c:2794
+#: config/tc-cris.c:3531
 msgid "PC-relative relocation must be trivially resolved"
 msgstr "La reubicación relativa al PC debe ser resuelta trivialmente"
 
-#: config/tc-cris.c:2837
+#: config/tc-cris.c:3584
 #, c-format
 msgid "Value not in 16 bit range: %ld"
 msgstr "El valor no está en el rango de 16 bit: %ld"
 
-#: config/tc-cris.c:2848
+#: config/tc-cris.c:3595
+#, c-format
+msgid "Value not in 16 bit signed range: %ld"
+msgstr "El valor no está en el rango de 16 bit con signo: %ld"
+
+#: config/tc-cris.c:3606
 #, c-format
 msgid "Value not in 8 bit range: %ld"
 msgstr "El valor no está en el rango de 8 bit: %ld"
 
-#: config/tc-cris.c:2855
+#: config/tc-cris.c:3614
+#, c-format
+msgid "Value not in 8 bit signed range: %ld"
+msgstr "El valor no está en el rango de 8 bit con signo: %ld"
+
+#: config/tc-cris.c:3625
 #, c-format
 msgid "Value not in 4 bit unsigned range: %ld"
 msgstr "El valor no está en el rango de 4 bit sin signo: %ld"
 
-#: config/tc-cris.c:2862
+#: config/tc-cris.c:3633
 #, c-format
 msgid "Value not in 5 bit unsigned range: %ld"
 msgstr "El valor no está en el rango de 5 bit sin signo: %ld"
 
-#: config/tc-cris.c:2869
+#: config/tc-cris.c:3641
 #, c-format
 msgid "Value not in 6 bit range: %ld"
 msgstr "El valor no está en el rango de 6 bit: %ld"
 
-#: config/tc-cris.c:2876
+#: config/tc-cris.c:3649
 #, c-format
 msgid "Value not in 6 bit unsigned range: %ld"
 msgstr "El valor no está en el rango de 6 bit sin signo: %ld"
 
-#: config/tc-cris.c:2924
+#: config/tc-cris.c:3695
+#, c-format
 msgid "Please use --help to see usage and options for this assembler.\n"
 msgstr "Por favor utilice --help para ver el modo de empleo y opciones para este ensamblador.\n"
 
-#: config/tc-cris.c:2936
+#: config/tc-cris.c:3707
 msgid "--no-underscore is invalid with a.out format"
 msgstr "--no-underscore es inválido con el formato a.out"
 
-#: config/tc-cris.c:3012
+#: config/tc-cris.c:3727
+#, c-format
+msgid "invalid <arch> in --march=<arch>: %s"
+msgstr "arquitectura <arq> en --march=<arq> inválida: %s"
+
+#: config/tc-cris.c:3821
 msgid "Semantics error.  This type of operand can not be relocated, it must be an assembly-time constant"
 msgstr "Error de semántica. Este tipo de operando no se puede reubicar, debe ser una constante en el momento de ensamblado"
 
-#: config/tc-cris.c:3064
+#: config/tc-cris.c:3870
 #, c-format
 msgid "Cannot generate relocation type for symbol %s, code %s"
 msgstr "No se puede generar el tipo de reubicación para el símbolo %s, código %s"
 
 #. The messages are formatted to line up with the generic options.
-#: config/tc-cris.c:3078
+#: config/tc-cris.c:3883
+#, c-format
 msgid "CRIS-specific options:\n"
 msgstr "Opciones específicas de CRIS:\n"
 
-#: config/tc-cris.c:3080
+#: config/tc-cris.c:3885
 msgid "  -h, -H                  Don't execute, print this help text.  Deprecated.\n"
 msgstr "  -h, -H                  No ejecutar, muestra este texto de ayuda.  Deprecado.\n"
 
-#: config/tc-cris.c:3082
+#: config/tc-cris.c:3887
 msgid "  -N                      Warn when branches are expanded to jumps.\n"
 msgstr "  -N                      Avisar cuando las ramificaciones se expanden a saltos.\n"
 
-#: config/tc-cris.c:3084
+#: config/tc-cris.c:3889
 msgid "  --underscore            User symbols are normally prepended with underscore.\n"
 msgstr "  --underscore            Los símbolos de usuario generalmente se preceden con subrayado.\n"
 
-#: config/tc-cris.c:3086
+#: config/tc-cris.c:3891
 msgid "                          Registers will not need any prefix.\n"
 msgstr "                          Los registros no necesitarán ningún prefijo.\n"
 
-#: config/tc-cris.c:3088
+#: config/tc-cris.c:3893
 msgid "  --no-underscore         User symbols do not have any prefix.\n"
 msgstr "  --no-underscore         Los símbolos de usuario no tienen ningún prefijo.\n"
 
-#: config/tc-cris.c:3090
+#: config/tc-cris.c:3895
 msgid "                          Registers will require a `$'-prefix.\n"
 msgstr "                          Los registros requerirán un prefijo `$'.\n"
 
-#: config/tc-cris.c:3092
+#: config/tc-cris.c:3897
 msgid "  --pic\t\t\tEnable generation of position-independent code.\n"
 msgstr "  --pic\t\t\tActiva la generación de código independiente de posición.\n"
 
-#: config/tc-cris.c:3115
+#: config/tc-cris.c:3899
+msgid ""
+"  --march=<arch>\t\tGenerate code for <arch>.  Valid choices for <arch>\n"
+"\t\t\t\tare v0_v10, v10, v32 and common_v10_v32.\n"
+msgstr ""
+"  --march=<arq>\t\tGenera código para <arq>.  Las opciones válidas para <arq>\n"
+"\t\t\t\tson v0_v10, v10, v32 y common_v10_v32.\n"
+
+#: config/tc-cris.c:3920
 msgid "Invalid relocation"
 msgstr "Reubicación inválida"
 
-#: config/tc-cris.c:3149
+#: config/tc-cris.c:3957
 msgid "Invalid pc-relative relocation"
 msgstr "Reubicación relativa a pc inválida"
 
-#: config/tc-cris.c:3198
+#: config/tc-cris.c:4002
 #, c-format
 msgid "Adjusted signed .word (%ld) overflows: `switch'-statement too large."
 msgstr "El .word (%ld) con signo ajustado se desborda: la sentencia `switch' es demasiado grande."
 
-#: config/tc-cris.c:3225
+#: config/tc-cris.c:4032
 #, c-format
 msgid ".syntax %s requires command-line option `--underscore'"
 msgstr ".syntax %s requiere de la opción de línea de comandos `--underscore'"
 
-#: config/tc-cris.c:3234
+#: config/tc-cris.c:4041
 #, c-format
 msgid ".syntax %s requires command-line option `--no-underscore'"
 msgstr ".syntax %s requiere de la opción de línea de comandos `--no-underscore'"
 
-#: config/tc-cris.c:3272
+#: config/tc-cris.c:4078
 msgid "Unknown .syntax operand"
 msgstr "Operando .syntax inválido"
 
-#: config/tc-cris.c:3283
+#: config/tc-cris.c:4088
 msgid "Pseudodirective .file is only valid when generating ELF"
 msgstr "La pseudodirectiva .file es válida solamente cuando se genera ELF"
 
-#: config/tc-cris.c:3296
+#: config/tc-cris.c:4100
 msgid "Pseudodirective .loc is only valid when generating ELF"
 msgstr "La pseudodirectiva .loc es válida solamente cuando se genera ELF"
 
-#: config/tc-d10v.c:252
+#: config/tc-cris.c:4243
+msgid "unknown operand to .arch"
+msgstr "operando desconocido para .arch"
+
+#: config/tc-cris.c:4252
+msgid ".arch <arch> requires a matching --march=... option"
+msgstr ".arch <arq> requiere una opción --march=... coincidente"
+
+#: config/tc-crx.c:344 config/tc-mn10200.c:801 write.c:2209
+#, c-format
+msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
+msgstr "no se puede resolver `%s' {sección %s} - `%s' {sección %s}"
+
+#: config/tc-crx.c:360
+#, c-format
+msgid "internal error: reloc %d (`%s') not supported by object file format"
+msgstr "error interno: la reubicación %d (`%s') no tiene soporte por el formato del fichero objeto"
+
+#: config/tc-crx.c:619 config/tc-crx.c:637 config/tc-i386.c:953
+#: config/tc-i386.c:976 config/tc-m68k.c:4149
+#, c-format
+msgid "Internal Error:  Can't hash %s: %s"
+msgstr "Error Interno:  No se puede dispersar %s: %s"
+
+#. Missing or bad expr becomes absolute 0.
+#: config/tc-crx.c:665 config/tc-i386.c:4259
+#, c-format
+msgid "missing or invalid displacement expression `%s' taken as 0"
+msgstr "la expresión de desubicación faltante o inválida `%s' se toma como 0"
+
+#: config/tc-crx.c:803 config/tc-crx.c:823 config/tc-crx.c:838
+#, c-format
+msgid "Illegal register `%s' in Instruction `%s'"
+msgstr "Registro `%s' ilegal en la Instruction `%s'"
+
+#: config/tc-crx.c:866
+#, c-format
+msgid "Illegal Scale - `%d'"
+msgstr "Scale ilegal - `%d'"
+
+#: config/tc-crx.c:982
+#, c-format
+msgid "Illegal operands (whitespace): `%s'"
+msgstr "Operandos ilegales (espacios en blanco): `%s'"
+
+#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
+#: config/tc-crx.c:1804
+#, c-format
+msgid "Missing matching brackets : `%s'"
+msgstr "Faltan las llaves coincidentes : `%s'"
+
+#: config/tc-crx.c:1044
+#, c-format
+msgid "Unknown exception: `%s'"
+msgstr "Excepción desconocida: `%s'"
+
+#: config/tc-crx.c:1140
+#, c-format
+msgid "Illegal `cinv' parameter: `%c'"
+msgstr "Parámetro `cinv' ilegal: `%c'"
+
+#: config/tc-crx.c:1173
+#, c-format
+msgid "Unknown register: `%d'"
+msgstr "Registro desconocido: `%d'"
+
+#. Issue a error message when register is illegal.
+#: config/tc-crx.c:1181
+#, c-format
+msgid "Illegal register (`%s') in Instruction: `%s'"
+msgstr "Registro ilegal (`%s') en Instruction: `%s'"
+
+#: config/tc-crx.c:1310
+#, c-format
+msgid "Illegal Co-processor register in Instruction `%s' "
+msgstr "Registro de co-procesador ilegal en Instruction `%s'"
+
+#: config/tc-crx.c:1317
+#, c-format
+msgid "Illegal Co-processor special register in Instruction `%s' "
+msgstr "Registro especial de co-procesador ilegal en Instruction `%s'"
+
+#: config/tc-crx.c:1616
+msgid "Incorrect number of operands"
+msgstr "Número incorrecto de operandos"
+
+#: config/tc-crx.c:1618
+#, c-format
+msgid "Illegal type of operand (arg %d)"
+msgstr "Tipo de operando ilegal (arg %d)"
+
+#: config/tc-crx.c:1624
+#, c-format
+msgid "Operand out of range (arg %d)"
+msgstr "Operando fuera de rango (arg %d)"
+
+#: config/tc-crx.c:1627
+#, c-format
+msgid "Operand has odd displacement (arg %d)"
+msgstr "El operando tiene un desplazamiento impar (arg %d)"
+
+#: config/tc-crx.c:1630
+#, c-format
+msgid "Invalid DISPU4 operand value (arg %d)"
+msgstr "Valor de operando DISPU4 inválido (arg %d)"
+
+#: config/tc-crx.c:1633
+#, c-format
+msgid "Invalid CST4 operand value (arg %d)"
+msgstr "Valor de operando CST4 inválido (arg %d)"
+
+#: config/tc-crx.c:1636
+#, c-format
+msgid "Operand value is not within upper 64 KB (arg %d)"
+msgstr "El valor del operando no está en los 64 KB superiores (arg %d)"
+
+#: config/tc-crx.c:1640 config/tc-crx.c:1671
+#, c-format
+msgid "Illegal operand (arg %d)"
+msgstr "Operando ilegal (arg %d)"
+
+#: config/tc-crx.c:1702 config/tc-crx.c:1719
+#, c-format
+msgid "Same src/dest register is used (`r%d'), result is undefined"
+msgstr "Se usa el mismo registro fuente/destino (`r%d'), el resultado es indefinido"
+
+#: config/tc-crx.c:1711
+#, c-format
+msgid "`%s' has undefined result"
+msgstr "`%s' tiene un resultado indefinido"
+
+#: config/tc-crx.c:1773
+msgid "Invalid Register in Register List"
+msgstr "Registro inválido en la Lista de Registros"
+
+#: config/tc-crx.c:1827
+#, c-format
+msgid "Illegal register `%s' in cop-register list"
+msgstr "Registro ilegal `%s' en la lista de registros de coprocesador"
+
+#: config/tc-crx.c:1835
+#, c-format
+msgid "Illegal register `%s' in cop-special-register list"
+msgstr "Registro ilegal `%s' en la lista especial de registros de coprocesador"
+
+#: config/tc-crx.c:1854
+#, c-format
+msgid "Illegal register `%s' in user register list"
+msgstr "Registro ilegal `%s' en la lista de registros de usuario"
+
+#: config/tc-crx.c:1873
+#, c-format
+msgid "Illegal register `%s' in register list"
+msgstr "Registro ilegal `%s' en la lista de registros"
+
+#: config/tc-crx.c:1879
+#, c-format
+msgid "Maximum %d bits may be set in `mask16' operand"
+msgstr "Se pueden establecer %d bits como máximo en el operando mask16"
+
+#: config/tc-crx.c:1888
+#, c-format
+msgid "rest of line ignored; first ignored character is `%c'"
+msgstr "se ignora el resto de la línea; el primer carácter ignorado es `%c'"
+
+#: config/tc-crx.c:1896
+#, c-format
+msgid "Illegal `mask16' operand, operation is undefined - `%s'"
+msgstr "Operando `mask16' ilegal, la operación está indefinida - `%s'"
+
+#. HI can't be specified without LO (and vise-versa).
+#: config/tc-crx.c:1902
+msgid "HI/LO registers should be specified together"
+msgstr "Los registros HI/LO se deben especificar juntos"
+
+#: config/tc-crx.c:1908
+msgid "HI/LO registers should be specified without additional registers"
+msgstr "Los registros HI/LO se deben especificar sin registros adicionales"
+
+#. Give an error if a frag containing code is not aligned to a 2-byte
+#. boundary.
+#: config/tc-crx.c:1993 config/tc-crx.h:76
+msgid "instruction address is not a multiple of 2"
+msgstr "la dirección de la instrucción no es un múltiplo de 2"
+
+#: config/tc-d10v.c:217
+#, c-format
 msgid ""
 "D10V options:\n"
 "-O                      Optimize.  Will do some operations in parallel.\n"
@@ -3107,144 +3414,145 @@ msgstr ""
 "Opciones D10V:\n"
 "-O                      Optimizar.  Hará algunas operaciones en paralelo.\n"
 "--gstabs-packing        Empaquetar juntas las instrucciones short adyacentes aún\n"
-"                        cuando se especifique --gstabs.  Activado por omisión.\n"
+"                        cuando se especifique --gstabs.  Activado por defecto.\n"
 "--no-gstabs-packing     Si se especifica --gstabs, no empaqueta juntas\n"
 "                        las instrucciones adjacentes.\n"
 
-#: config/tc-d10v.c:543 config/tc-d30v.c:549 config/tc-mn10200.c:937
-#: config/tc-mn10300.c:1812 config/tc-ppc.c:2332 config/tc-s390.c:1234
-#: config/tc-tic80.c:275 config/tc-v850.c:2022
+#: config/tc-d10v.c:496 config/tc-d30v.c:488 config/tc-mn10200.c:1075
+#: config/tc-mn10300.c:1817 config/tc-ppc.c:2380 config/tc-s390.c:1218
+#: config/tc-v850.c:1949
 msgid "illegal operand"
 msgstr "operando ilegal"
 
-#: config/tc-d10v.c:657
+#: config/tc-d10v.c:608
 msgid "operand is not an immediate"
 msgstr "el operando no es un inmediato"
 
-#: config/tc-d10v.c:675
+#: config/tc-d10v.c:626
 #, c-format
 msgid "operand out of range: %lu"
 msgstr "operando fuera de rango: %lu"
 
-#: config/tc-d10v.c:736
+#: config/tc-d10v.c:684
 msgid "Instruction must be executed in parallel with another instruction."
 msgstr "La instrucción debe ser ejecutada en paralelo con otra instrucción."
 
-#: config/tc-d10v.c:792
+#: config/tc-d10v.c:738 config/tc-d10v.c:746
+#, c-format
+msgid "packing conflict: %s must dispatch sequentially"
+msgstr "conflicto de empaquetado: %s debe despachar secuencialmente"
+
+#: config/tc-d10v.c:845
+#, c-format
+msgid "resource conflict (R%d)"
+msgstr "conflicto de recurso (R%d)"
+
+#: config/tc-d10v.c:848
+#, c-format
+msgid "resource conflict (A%d)"
+msgstr "conflicto de recurso (A%d)"
+
+#: config/tc-d10v.c:850
+msgid "resource conflict (PSW)"
+msgstr "conflicto de recurso (PSW)"
+
+#: config/tc-d10v.c:852
+msgid "resource conflict (C flag)"
+msgstr "conflicto de recurso (opción C)"
+
+#: config/tc-d10v.c:854
+msgid "resource conflict (F flag)"
+msgstr "conflicto de recurso (opción F)"
+
+#: config/tc-d10v.c:1004
 msgid "Instruction must be executed in parallel"
 msgstr "La instrucción debe ser ejecutada en paralelo"
 
-#: config/tc-d10v.c:795
+#: config/tc-d10v.c:1007
 msgid "Long instructions may not be combined."
 msgstr "Las instrucciones long no se pueden combinar."
 
-#: config/tc-d10v.c:828
+#: config/tc-d10v.c:1040
 msgid "One of these instructions may not be executed in parallel."
 msgstr "Una de estas instrucciones no se puede ejecutar en paralelo."
 
-#: config/tc-d10v.c:832 config/tc-d30v.c:876
+#: config/tc-d10v.c:1044 config/tc-d30v.c:1071
 msgid "Two IU instructions may not be executed in parallel"
 msgstr "Dos instrucciones IU no se pueden ejecutar en paralelo"
 
-#: config/tc-d10v.c:834 config/tc-d10v.c:842 config/tc-d10v.c:856
-#: config/tc-d10v.c:871 config/tc-d30v.c:877 config/tc-d30v.c:886
+#: config/tc-d10v.c:1046 config/tc-d10v.c:1054 config/tc-d10v.c:1068
+#: config/tc-d10v.c:1083 config/tc-d30v.c:1072 config/tc-d30v.c:1081
 msgid "Swapping instruction order"
 msgstr "Intercambiando el orden de la instrucción"
 
-#: config/tc-d10v.c:840 config/tc-d30v.c:883
+#: config/tc-d10v.c:1052 config/tc-d30v.c:1078
 msgid "Two MU instructions may not be executed in parallel"
 msgstr "Dos instrucciones MU no se pueden ejecutar en paralelo"
 
-#: config/tc-d10v.c:860 config/tc-d30v.c:903
+#: config/tc-d10v.c:1072 config/tc-d30v.c:1098
 msgid "IU instruction may not be in the left container"
 msgstr "Una instrucción IU no puede estar en el contenedor izquierdo"
 
 # Parece que R es 'right' y L es 'left'. Revisar el código para comprobar
 # y mejorar esta traducción. cfuga
-#: config/tc-d10v.c:862 config/tc-d10v.c:877
+#: config/tc-d10v.c:1074 config/tc-d10v.c:1089
 msgid "Instruction in R container is squashed by flow control instruction in L container."
 msgstr "La instrucción en el contenedor R es aplastada por la instrucción de control de flujo en el contenedor L."
 
-#: config/tc-d10v.c:875 config/tc-d30v.c:914
+#: config/tc-d10v.c:1087 config/tc-d30v.c:1109
 msgid "MU instruction may not be in the right container"
 msgstr "Una instrucción MU no puede estar en el contenedor derecho"
 
-#: config/tc-d10v.c:881 config/tc-d30v.c:926
+#: config/tc-d10v.c:1093 config/tc-d30v.c:1121
 msgid "unknown execution type passed to write_2_short()"
 msgstr "tipo de ejecución desconocido pasado a write_2_short()"
 
-#: config/tc-d10v.c:1072 config/tc-d10v.c:1080
-#, c-format
-msgid "packing conflict: %s must dispatch sequentially"
-msgstr "conflicto de empaquetado: %s debe despachar secuencialmente"
-
-#: config/tc-d10v.c:1179
-#, c-format
-msgid "resource conflict (R%d)"
-msgstr "conflicto de recurso (R%d)"
-
-#: config/tc-d10v.c:1182
-#, c-format
-msgid "resource conflict (A%d)"
-msgstr "conflicto de recurso (A%d)"
-
-#: config/tc-d10v.c:1184
-msgid "resource conflict (PSW)"
-msgstr "conflicto de recurso (PSW)"
-
-#: config/tc-d10v.c:1186
-msgid "resource conflict (C flag)"
-msgstr "conflicto de recurso (opción C)"
-
-#: config/tc-d10v.c:1188
-msgid "resource conflict (F flag)"
-msgstr "conflicto de recurso (opción F)"
-
-#: config/tc-d10v.c:1276 config/tc-d10v.c:1298 config/tc-d30v.c:1410
-msgid "Unable to mix instructions as specified"
-msgstr "No se pueden mezclar las instrucciones como se especificó"
-
-#: config/tc-d10v.c:1345 config/tc-d30v.c:1547
-#, c-format
-msgid "unknown opcode: %s"
-msgstr "código de operación desconocido: %s"
-
-#: config/tc-d10v.c:1428 config/tc-d10v.c:1603 config/tc-tic80.c:532
+#: config/tc-d10v.c:1221 config/tc-d10v.c:1394
 msgid "bad opcode or operands"
 msgstr "código de operación u operandos erróneos"
 
-#: config/tc-d10v.c:1503 config/tc-m68k.c:4305
+#: config/tc-d10v.c:1296 config/tc-m68k.c:4625
 msgid "value out of range"
 msgstr "valor fuera de rango"
 
-#: config/tc-d10v.c:1579
+#: config/tc-d10v.c:1370
 msgid "illegal operand - register name found where none expected"
 msgstr "operando ilegal - se encontró un nombre de registro donde no se esperaba ninguno"
 
-#: config/tc-d10v.c:1614 config/tc-tic80.c:543
+#: config/tc-d10v.c:1405
 msgid "Register number must be EVEN"
 msgstr "El número de registro debe ser PAR"
 
-#: config/tc-d10v.c:1617
+#: config/tc-d10v.c:1408
 msgid "Unsupported use of sp"
 msgstr "Uso sin soporte de sp"
 
-#: config/tc-d10v.c:1636
+#: config/tc-d10v.c:1427
 #, c-format
 msgid "cr%ld is a reserved control register"
 msgstr "cr%ld es un registro de control reservado"
 
-#: config/tc-d10v.c:1773
+#: config/tc-d10v.c:1466 config/tc-d30v.c:1430
+#, c-format
+msgid "unknown opcode: %s"
+msgstr "código de operación desconocido: %s"
+
+#: config/tc-d10v.c:1602
 #, c-format
 msgid "line %d: rep or repi must include at least 4 instructions"
 msgstr "línea %d: rep o repi debe incluir por lo menos 4 instrucciones"
 
-#: config/tc-d30v.c:192
+#: config/tc-d10v.c:1810 config/tc-d10v.c:1832 config/tc-d30v.c:1777
+msgid "Unable to mix instructions as specified"
+msgstr "No se pueden mezclar las instrucciones como se especificó"
+
+#: config/tc-d30v.c:150
 #, c-format
 msgid "Register name %s conflicts with symbol of the same name"
 msgstr "El nombre de registro %s tiene conflictos con el símbolo del mismo nombre"
 
-#: config/tc-d30v.c:287
+#: config/tc-d30v.c:240
+#, c-format
 msgid ""
 "\n"
 "D30V options:\n"
@@ -3260,1289 +3568,1316 @@ msgstr ""
 "-n                      Avisar sobre todos los NOPs insertados por el ensamblador.\n"
 "-N\t\t\tAvisar sobre los NOPs insertados después de los múltiplos de word.\n"
 "-c                      Avisar sobre los símbolos cuyos nombres coincidan con nombres de registros.\n"
-"-C                      Opuesto de -C.  -c es por omisión.\n"
+"-C                      Opuesto de -C.  -c es por defecto.\n"
 
-#: config/tc-d30v.c:461
+#: config/tc-d30v.c:402
 msgid "unexpected 12-bit reloc type"
 msgstr "tipo de reubicación de 12-bit inesperado"
 
-#: config/tc-d30v.c:468
+#: config/tc-d30v.c:409
 msgid "unexpected 18-bit reloc type"
 msgstr "tipo de reubicación de 18-bit inesperado"
 
-#: config/tc-d30v.c:719
+#: config/tc-d30v.c:659
 #, c-format
 msgid "%s NOP inserted"
 msgstr "%s NOP insertados"
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:660
 msgid "sequential"
 msgstr "secuencial"
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:660
 msgid "parallel"
 msgstr "paralelo"
 
-#: config/tc-d30v.c:872
+#: config/tc-d30v.c:1067
 msgid "Instructions may not be executed in parallel"
 msgstr "Las instrucciones no se pueden ejecutar en paralelo"
 
-#: config/tc-d30v.c:885
+#: config/tc-d30v.c:1080
 #, c-format
 msgid "Executing %s in IU may not work"
 msgstr "Ejecutar %s en IU podría no funcionar"
 
-#: config/tc-d30v.c:892
+#: config/tc-d30v.c:1087
 #, c-format
 msgid "Executing %s in IU may not work in parallel execution"
 msgstr "Ejecutar %s en IU podría no funcionar en ejecución paralela"
 
-#: config/tc-d30v.c:905
+#: config/tc-d30v.c:1100
 #, c-format
 msgid "special left instruction `%s' kills instruction `%s' in right container"
 msgstr "la instrucción especial izquierda `%s' mata a la instrucción `%s' en el contenedor derecho"
 
-#: config/tc-d30v.c:916
+#: config/tc-d30v.c:1111
 #, c-format
 msgid "Executing %s in reverse serial with %s may not work"
 msgstr "Ejecutar %s en serie reversa con %s podría no funcionar"
 
-#: config/tc-d30v.c:919
+#: config/tc-d30v.c:1114
 #, c-format
 msgid "Executing %s in IU in reverse serial may not work"
 msgstr "Ejecutar %s en IU en serie reversa podría no funcionar"
 
-#: config/tc-d30v.c:1289 config/tc-d30v.c:1306
+#: config/tc-d30v.c:1303
+msgid "Odd numbered register used as target of multi-register instruction"
+msgstr "Los registros numerados nones se usan como objetivo para una instrucción multi-registro"
+
+#: config/tc-d30v.c:1367 config/tc-d30v.c:1402
+#, c-format
+msgid "unknown condition code: %s"
+msgstr "código de condición desconocido: %s"
+
+#: config/tc-d30v.c:1395
+#, c-format
+msgid "cmpu doesn't support condition code %s"
+msgstr "cmpu no tiene soporte para el código de condición %s"
+
+#: config/tc-d30v.c:1441
+#, c-format
+msgid "operands for opcode `%s' do not match any valid format"
+msgstr "los operandos para el código de operación `%s' no coincide con ningún formato válido"
+
+#: config/tc-d30v.c:1656 config/tc-d30v.c:1673
 msgid "Cannot assemble instruction"
 msgstr "No se puede ensamblar la instrucción"
 
-#: config/tc-d30v.c:1291
+#: config/tc-d30v.c:1658
 msgid "First opcode is long.  Unable to mix instructions as specified."
 msgstr "El primer código de operación es long.  No se pueden mezclar las instrucciones como se especificó."
 
-#: config/tc-d30v.c:1360
+#: config/tc-d30v.c:1727
 msgid "word of NOPs added between word multiply and load"
 msgstr "word de NOPs agregados entre múltiplos de word y load"
 
-#: config/tc-d30v.c:1362
+#: config/tc-d30v.c:1729
 msgid "word of NOPs added between word multiply and 16-bit multiply"
 msgstr "word de NOPs agregados entre múltiplos de word y múltiplos de 16-bit"
 
-#: config/tc-d30v.c:1394
+#: config/tc-d30v.c:1761
 msgid "Instruction uses long version, so it cannot be mixed as specified"
 msgstr "La instrucción usa una versión long, así que no se puede mezclar como se especificó"
 
-#: config/tc-d30v.c:1477 config/tc-d30v.c:1515
-#, c-format
-msgid "unknown condition code: %s"
-msgstr "código de condición desconocido: %s"
-
-#: config/tc-d30v.c:1508
-#, c-format
-msgid "cmpu doesn't support condition code %s"
-msgstr "cmpu no tiene soporte para el código de condición %s"
-
-#: config/tc-d30v.c:1558
+#: config/tc-d30v.c:1888
 #, c-format
-msgid "operands for opcode `%s' do not match any valid format"
-msgstr "los operandos para el código de operación `%s' no coincide con ningún formato válido"
-
-#: config/tc-d30v.c:1776
-msgid "Odd numbered register used as target of multi-register instruction"
-msgstr "Los registros numerados nones se usan como objetivo para una instrucción multi-registro"
+msgid "value too large to fit in %d bits"
+msgstr "valor demasiado grande para caber en %d bits"
 
-#: config/tc-d30v.c:1862
+#: config/tc-d30v.c:1949
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a byte"
 msgstr "línea %d: no se puede colocar la dirección del símbolo '%s' en un byte"
 
-#: config/tc-d30v.c:1865
+#: config/tc-d30v.c:1952
 #, c-format
 msgid "line %d: unable to place value %lx into a byte"
 msgstr "línea %d: no se puede colocar el valor %lx en un byte"
 
-#: config/tc-d30v.c:1873
+#: config/tc-d30v.c:1960
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a short"
 msgstr "línea %d: no se puede colocar la dirección del símbolo '%s' en un short"
 
-#: config/tc-d30v.c:1876
+#: config/tc-d30v.c:1963
 #, c-format
 msgid "line %d: unable to place value %lx into a short"
 msgstr "línea %d: no se puede colocar el valor %lx en un short"
 
-#: config/tc-d30v.c:1884
+#: config/tc-d30v.c:1971
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a quad"
 msgstr "línea %d: no se puede colocar la dirección del símbolo '%s' en un quad"
 
-#: config/tc-d30v.c:2053
-#, c-format
-msgid "value too large to fit in %d bits"
-msgstr "valor demasiado grande para caber en %d bits"
-
-#: config/tc-d30v.c:2196
+#: config/tc-d30v.c:2079
 #, c-format
 msgid "Alignment too large: %d assumed"
 msgstr "Alineación demasiado grande: se asume %d"
 
-#: config/tc-dlx.c:283
+#: config/tc-dlx.c:211
 msgid "missing .proc"
 msgstr "falta un .proc"
 
-#: config/tc-dlx.c:300
+#: config/tc-dlx.c:228
 msgid ".endfunc missing for previous .proc"
 msgstr "falta un .endfunc para el .proc previo"
 
-#: config/tc-dlx.c:498
-#, c-format
-msgid "Expression Error for operand modifier %%hi/%%lo\n"
-msgstr "Error de Expresión para el modificador de operando %%hi/%%lo\n"
+#. Probably a memory allocation problem?  Give up now.
+#: config/tc-dlx.c:297 config/tc-hppa.c:1489 config/tc-mips.c:1415
+#: config/tc-mips.c:1467 config/tc-or32.c:210 config/tc-sparc.c:855
+msgid "Broken assembler.  No assembly attempted."
+msgstr "Ensamblador descompuesto.  No se intentó ensamblar."
 
-#: config/tc-dlx.c:552
+#: config/tc-dlx.c:327
 #, c-format
 msgid "Bad operand for a load instruction: <%s>"
 msgstr "Operando erróneo para una instrucción load <%s>"
 
-#: config/tc-dlx.c:667
+#: config/tc-dlx.c:441
 #, c-format
 msgid "Bad operand for a store instruction: <%s>"
 msgstr "Operando erróneo para una instrucción store <%s>"
 
-#: config/tc-dlx.c:865
+#: config/tc-dlx.c:621
+#, c-format
+msgid "Expression Error for operand modifier %%hi/%%lo\n"
+msgstr "Error de Expresión para el modificador de operando %%hi/%%lo\n"
+
+#: config/tc-dlx.c:634 config/tc-or32.c:873
+#, c-format
+msgid "Invalid expression after %%%%\n"
+msgstr "Expresión inválida después de %%%%\n"
+
+#: config/tc-dlx.c:703
+#, c-format
+msgid "Unknown opcode `%s'."
+msgstr "Código de operación desconocido `%s'."
+
+#: config/tc-dlx.c:716
 msgid "Can not set dlx_skip_hi16_flag"
 msgstr "No se puede establecer dlx_skip_hi16_flag"
 
-#: config/tc-dlx.c:879
+#: config/tc-dlx.c:730
 #, c-format
 msgid "Missing arguments for opcode <%s>."
 msgstr "Faltan argumentos para el código de operación <%s>"
 
-#: config/tc-dlx.c:950
+#: config/tc-dlx.c:764
+#, c-format
+msgid "Too many operands: %s"
+msgstr "Demasiados operandos: %s"
+
+#: config/tc-dlx.c:801
 #, c-format
 msgid "Both the_insn.HI and the_insn.LO are set : %s"
 msgstr "Tanto the_insn.HI como the_insn.LO están activados: %s"
 
-#: config/tc-dlx.c:1022
+#: config/tc-dlx.c:871
 msgid "failed regnum sanity check."
 msgstr "falló la prueba de sanidad regnum."
 
-#: config/tc-dlx.c:1035
+#: config/tc-dlx.c:884
 msgid "failed general register sanity check."
 msgstr "falló la prueba de sanidad de registro general."
 
-#: config/tc-dlx.c:1324
+#: config/tc-dlx.c:1175 config/tc-or32.c:835
+#, c-format
+msgid "label \"$%d\" redefined"
+msgstr "se redefinió la etiqueta \"$%d\""
+
+#: config/tc-dlx.c:1213
 msgid "Invalid expression after # number\n"
 msgstr "Expresión inválida después de # number\n"
 
-#: config/tc-fr30.c:85
+#: config/tc-fr30.c:83
+#, c-format
 msgid " FR30 specific command line options:\n"
 msgstr " Opciones de línea de comando específicas de FR30:\n"
 
-#: config/tc-fr30.c:139 config/tc-openrisc.c:152
+#: config/tc-fr30.c:136
 #, c-format
 msgid "Instruction %s not allowed in a delay slot."
 msgstr "No se permite la instrucción %s en una ranura de retardo."
 
-#: config/tc-fr30.c:383 config/tc-m32r.c:1576
-msgid "Addend to unresolved symbol not on word boundary."
-msgstr "La adición para un símbolo sin resolver no está en un límite de word."
-
-#: config/tc-fr30.c:524 config/tc-frv.c:1289 config/tc-i960.c:798
-#: config/tc-ip2k.c:353 config/tc-m32r.c:1884 config/tc-openrisc.c:452
-#: config/tc-xstormy16.c:636
-msgid "Bad call to md_atof()"
-msgstr "Llamada errónea a md_atof()"
-
-#: config/tc-frv.c:413
+#: config/tc-frv.c:461
+#, c-format
 msgid "FRV specific command line options:\n"
 msgstr "Opciones de línea de comando específicas de FVR:\n"
 
-#: config/tc-frv.c:414
+#: config/tc-frv.c:462
+#, c-format
 msgid "-G n         Data >= n bytes is in small data area\n"
 msgstr "-G n         Datos >= n bytes en el área de datos small\n"
 
-#: config/tc-frv.c:415
+#: config/tc-frv.c:463
+#, c-format
 msgid "-mgpr-32     Note 32 gprs are used\n"
 msgstr "-mgpr-32     Se usa nota de 32 gprs\n"
 
-#: config/tc-frv.c:416
+#: config/tc-frv.c:464
+#, c-format
 msgid "-mgpr-64     Note 64 gprs are used\n"
 msgstr "-mgpr-64     Se usa nota de 64 gprs\n"
 
-#: config/tc-frv.c:417
+#: config/tc-frv.c:465
+#, c-format
 msgid "-mfpr-32     Note 32 fprs are used\n"
 msgstr "-mfpr-32     Se usa nota de 32 fprs\n"
 
-#: config/tc-frv.c:418
+#: config/tc-frv.c:466
+#, c-format
 msgid "-mfpr-64     Note 64 fprs are used\n"
 msgstr "-mfpr-64     Se usa nota de 64 fprs\n"
 
-#: config/tc-frv.c:419
+#: config/tc-frv.c:467
+#, c-format
 msgid "-msoft-float Note software fp is used\n"
 msgstr "-msoft-float Se usa nota de fp de software\n"
 
-#: config/tc-frv.c:420
+#: config/tc-frv.c:468
+#, c-format
 msgid "-mdword      Note stack is aligned to a 8 byte boundary\n"
 msgstr "-mdword      La pila de nota está alineada a un límite de 8 byte\n"
 
-#: config/tc-frv.c:421
+#: config/tc-frv.c:469
+#, c-format
 msgid "-mno-dword   Note stack is aligned to a 4 byte boundary\n"
 msgstr "-mno-dword   La pila de nota está alineada a un límite de 4 byte\n"
 
-#: config/tc-frv.c:422
+#: config/tc-frv.c:470
+#, c-format
 msgid "-mdouble     Note fp double insns are used\n"
 msgstr "-mdouble     Se usan instrucciones nota de fp doble\n"
 
-#: config/tc-frv.c:423
+#: config/tc-frv.c:471
+#, c-format
 msgid "-mmedia      Note media insns are used\n"
 msgstr "-mmedia      Se usan instrucciones nota media\n"
 
-#: config/tc-frv.c:424
+#: config/tc-frv.c:472
+#, c-format
 msgid "-mmuladd     Note multiply add/subtract insns are used\n"
 msgstr "-mmuladd     Se usan instrucciones nota de multiplicación adición/substracción\n"
 
-#: config/tc-frv.c:425
+#: config/tc-frv.c:473
+#, c-format
 msgid "-mpack       Note instructions are packed\n"
 msgstr "-mpack       Las instrucciones nota están empaquetadas\n"
 
-#: config/tc-frv.c:426
+#: config/tc-frv.c:474
+#, c-format
 msgid "-mno-pack    Do not allow instructions to be packed\n"
 msgstr "-mno-pack    No permite que se empaqueten las instrucciones\n"
 
-#: config/tc-frv.c:427
+#: config/tc-frv.c:475
+#, c-format
 msgid "-mpic        Note small position independent code\n"
 msgstr "-mpic        Nota de código independiente de posición small\n"
 
-#: config/tc-frv.c:428
+#: config/tc-frv.c:476
+#, c-format
 msgid "-mPIC        Note large position independent code\n"
 msgstr "-mPIC        Nota de código independiente de posición large\n"
 
-#: config/tc-frv.c:429
+#: config/tc-frv.c:477
+#, c-format
 msgid "-mlibrary-pic Compile library for large position indepedent code\n"
 msgstr "-mlibrary-pic Compila la biblioteca para código independiente de posición large\n"
 
-#: config/tc-frv.c:430
-msgid "-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n"
-msgstr "-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n"
+#: config/tc-frv.c:478
+#, c-format
+msgid "-mfdpic      Assemble for the FDPIC ABI\n"
+msgstr "-mfdpic      Ensambla para la ABI de FDPIC\n"
 
-#: config/tc-frv.c:431
+#: config/tc-frv.c:479
+#, c-format
+msgid "-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"
+msgstr "-mnopic      Desactiva -mpic, -mPIC, -mlibrary-pic y -mfdpic\n"
+
+#: config/tc-frv.c:480
+#, c-format
+msgid "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
+msgstr "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
+
+#: config/tc-frv.c:481
+#, c-format
 msgid "             Record the cpu type\n"
 msgstr "             Graba el tipo de cpu\n"
 
-#: config/tc-frv.c:432
+#: config/tc-frv.c:482
+#, c-format
 msgid "-mtomcat-stats Print out stats for tomcat workarounds\n"
 msgstr "-mtomcat-stats Muestra estadísticas para las alternativas de tomcat\n"
 
-#: config/tc-frv.c:433
+#: config/tc-frv.c:483
+#, c-format
 msgid "-mtomcat-debug Debug tomcat workarounds\n"
 msgstr "-mtomcat-debug Depura las alternativas de tomcat\n"
 
-#: config/tc-frv.c:1012
+#: config/tc-frv.c:1187
 msgid "VLIW packing used for -mno-pack"
 msgstr "Se utilizó empaquetado VLIW para -mno-pack"
 
-#: config/tc-frv.c:1025
+#: config/tc-frv.c:1197
+msgid "Instruction not supported by this architecture"
+msgstr "La instrucción no tiene soporte en esta arquitectura"
+
+#: config/tc-frv.c:1207
 msgid "VLIW packing constraint violation"
 msgstr "Violación de restricción de empaquetado VLIW"
 
-#: config/tc-frv.c:1540
+#: config/tc-frv.c:1874
 #, c-format
 msgid "Relocation %s is not safe for %s"
 msgstr "La reubicación %s no es segura para %s"
 
-#: config/tc-h8300.c:84 config/tc-h8300.c:96 config/tc-h8300.c:109
-#: config/tc-h8300.c:122 config/tc-h8300.c:135 config/tc-h8300.c:149
-#: config/tc-h8300.c:222 config/tc-hppa.c:1423 config/tc-hppa.c:6909
-#: config/tc-hppa.c:6915 config/tc-hppa.c:6921 config/tc-hppa.c:6927
-#: config/tc-mn10300.c:1218 config/tc-mn10300.c:1223 config/tc-mn10300.c:2722
+#: config/tc-h8300.c:78 config/tc-h8300.c:87 config/tc-h8300.c:97
+#: config/tc-h8300.c:107 config/tc-h8300.c:117 config/tc-h8300.c:128
+#: config/tc-h8300.c:195 config/tc-hppa.c:1449 config/tc-hppa.c:6926
+#: config/tc-hppa.c:6932 config/tc-hppa.c:6938 config/tc-hppa.c:6944
+#: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2725
 msgid "could not set architecture and machine"
 msgstr "no se pueden establecer la arquitectura y la máquina"
 
-#: config/tc-h8300.c:436 config/tc-h8300.c:444
+#: config/tc-h8300.c:397 config/tc-h8300.c:405
 msgid "Reg not valid for H8/300"
 msgstr "El registro no es válido para H8/300"
 
-#: config/tc-h8300.c:529
+#: config/tc-h8300.c:486
 msgid "invalid operand size requested"
 msgstr "se solicitó un tamaño de operando inválido"
 
-#: config/tc-h8300.c:626 config/tc-h8300.c:629
+#: config/tc-h8300.c:585
 msgid "Invalid register list for ldm/stm\n"
 msgstr "Lista de registros inválida para ldm/stm\n"
 
-#: config/tc-h8300.c:632
-msgid "Invalid register list for ldm/stm)\n"
-msgstr "Lista de registros inválida para ldm/stm)\n"
-
-#: config/tc-h8300.c:658 config/tc-h8300.c:663 config/tc-h8300.c:670
+#: config/tc-h8300.c:611 config/tc-h8300.c:616 config/tc-h8300.c:623
 msgid "mismatch between register and suffix"
 msgstr "no hay coincidencia entre el registro y el sufijo"
 
-#: config/tc-h8300.c:697
+#: config/tc-h8300.c:650
 msgid "address too high for vector table jmp/jsr"
 msgstr "dirección demasiado alta para la tabla de vectores jmp/jsr"
 
-#: config/tc-h8300.c:722 config/tc-h8300.c:832 config/tc-h8300.c:840
+#: config/tc-h8300.c:677 config/tc-h8300.c:789 config/tc-h8300.c:799
 msgid "Wrong size pointer register for architecture."
-msgstr "Tamaño de apuntador a registro erróneo para la arquitectura."
+msgstr "Tamaño de puntero a registro erróneo para la arquitectura."
 
-#: config/tc-h8300.c:781 config/tc-h8300.c:789 config/tc-h8300.c:818
+#: config/tc-h8300.c:736 config/tc-h8300.c:744 config/tc-h8300.c:773
 msgid "expected @(exp, reg16)"
 msgstr "se esperaba @(exp, reg16)"
 
-#: config/tc-h8300.c:807
+#: config/tc-h8300.c:762
 msgid "expected .L, .W or .B for register in indexed addressing mode"
 msgstr "se esperaba .L, .W ó .B para el registro en modo de direccionamiento indizado"
 
-#: config/tc-h8300.c:1000
+#: config/tc-h8300.c:956
 msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""
 msgstr "se pesperaba un modo de direccionamiento válido para mova: \"@(disp, ea.sz),ERn\""
 
-#: config/tc-h8300.c:1018 config/tc-h8300.c:1027
+#: config/tc-h8300.c:974 config/tc-h8300.c:983
 msgid "expected register"
 msgstr "se esperaba un registro"
 
-#: config/tc-h8300.c:1043
+#: config/tc-h8300.c:999
 msgid "expected closing paren"
 msgstr "se esperaba un paréntesis que cierra"
 
-#: config/tc-h8300.c:1104
+#: config/tc-h8300.c:1058
 #, c-format
 msgid "can't use high part of register in operand %d"
 msgstr "no se puede usar la parte alta del registro en el operando %d"
 
-#: config/tc-h8300.c:1268
+#: config/tc-h8300.c:1215
 #, c-format
 msgid "Opcode `%s' with these operand types not available in %s mode"
 msgstr "El código de operación `%s' con esos tipos de operando no está disponible en el modo %s"
 
-#: config/tc-h8300.c:1277
+#: config/tc-h8300.c:1224
 msgid "mismatch between opcode size and operand size"
 msgstr "no hay coincidencia entre el tamaño del código de operación y el tamaño del operando"
 
-#: config/tc-h8300.c:1316
+#: config/tc-h8300.c:1260
 #, c-format
 msgid "operand %s0x%lx out of range."
 msgstr "operando %s0x%lx fuera de rango."
 
-#: config/tc-h8300.c:1415
+#: config/tc-h8300.c:1356
 msgid "Can't work out size of operand.\n"
 msgstr "No se puede obtener el tamaño del operando.\n"
 
-#: config/tc-h8300.c:1466
+#: config/tc-h8300.c:1405
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300 mode"
 msgstr "El código de operación `%s' con esos tipos de operandos no están disponibles en el modo H8/300"
 
-#: config/tc-h8300.c:1471
+#: config/tc-h8300.c:1410
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300H mode"
 msgstr "El código de operación `%s' con esos tipos de operandos no está disponible en el modo H8/300H"
 
-#: config/tc-h8300.c:1477
+#: config/tc-h8300.c:1416
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300S mode"
 msgstr "El código de operación `%s' con esos tipos de operandos no está disponible en el modo H8/300S"
 
-#: config/tc-h8300.c:1538 config/tc-h8300.c:1558
+#: config/tc-h8300.c:1477 config/tc-h8300.c:1497
 msgid "Need #1 or #2 here"
 msgstr "Se necesita #1 ó #2 aquí"
 
-#: config/tc-h8300.c:1553
+#: config/tc-h8300.c:1492
 msgid "#4 not valid on H8/300."
 msgstr "#4 no es válido en H8/300"
 
-#: config/tc-h8300.c:1645 config/tc-h8300.c:1727
+#: config/tc-h8300.c:1598 config/tc-h8300.c:1680
 #, c-format
 msgid "branch operand has odd offset (%lx)\n"
 msgstr "el operando de ramificación tiene un desplazamiento non (%lx)\n"
 
-#: config/tc-h8300.c:1766
+#: config/tc-h8300.c:1718
 msgid "destination operand must be 16 bit register"
 msgstr "el operando de destino debe ser un registro de 16 bit"
 
-#: config/tc-h8300.c:1775
+#: config/tc-h8300.c:1727
 msgid "source operand must be 8 bit register"
 msgstr "el operando de origen debe ser un registro de 8 bit"
 
-#: config/tc-h8300.c:1783
+#: config/tc-h8300.c:1735
 msgid "destination operand must be 16bit absolute address"
 msgstr "el operando de destino debe ser una dirección absoluta de 16bit"
 
-#: config/tc-h8300.c:1790
+#: config/tc-h8300.c:1742
 msgid "destination operand must be 8 bit register"
 msgstr "el operando de destino debe ser un registro de 8 bit"
 
-#: config/tc-h8300.c:1798
+#: config/tc-h8300.c:1750
 msgid "source operand must be 16bit absolute address"
 msgstr "el operando de origen debe ser una dirección absoluta de 16bit"
 
 #. This seems more sane than saying "too many operands".  We'll
 #. get here only if the trailing trash starts with a comma.
-#: config/tc-h8300.c:1806 config/tc-mmix.c:454 config/tc-mmix.c:466
-#: config/tc-mmix.c:2502 config/tc-mmix.c:2526 config/tc-mmix.c:2802
-#: config/tc-or32.c:640 config/tc-or32.c:854
+#. Types or values of args don't match.
+#: config/tc-h8300.c:1758 config/tc-mmix.c:473 config/tc-mmix.c:485
+#: config/tc-mmix.c:2526 config/tc-mmix.c:2550 config/tc-mmix.c:2823
+#: config/tc-or32.c:527
 msgid "invalid operands"
 msgstr "operandos inválidos"
 
-#: config/tc-h8300.c:1839
+#: config/tc-h8300.c:1789
 msgid "operand/size mis-match"
 msgstr "no coinciden los operandos/tamaños"
 
-#: config/tc-h8300.c:1926 config/tc-h8500.c:1112 config/tc-mips.c:9301
-#: config/tc-sh.c:2363 config/tc-sh64.c:2837 config/tc-w65.c:691
-#: config/tc-z8k.c:1248
+#: config/tc-h8300.c:1885 config/tc-mips.c:9358 config/tc-sh64.c:2795
+#: config/tc-sh.c:2838 config/tc-z8k.c:1204
 msgid "unknown opcode"
 msgstr "código de operación desconocido"
 
-#: config/tc-h8300.c:2031 config/tc-h8500.c:1139 config/tc-sh.c:2483
-#: config/tc-z8k.c:1304
-msgid "call to tc_crawl_symbol_chain \n"
-msgstr "llamada a tc_crawl_symbol_chain \n"
+#: config/tc-h8300.c:1918
+msgid "invalid operand in ldm"
+msgstr "operando inválido en ldm"
 
-#: config/tc-h8300.c:2047 config/tc-h8500.c:1153 config/tc-sh.c:2490
-#: config/tc-z8k.c:1320
-msgid "call to tc_headers_hook \n"
-msgstr "llamada a tc_headers_hook \n"
+#: config/tc-h8300.c:1927
+msgid "invalid operand in stm"
+msgstr "operando inválido en stm"
 
-#: config/tc-h8300.c:2140
+#: config/tc-h8300.c:2093
+#, c-format
 msgid "call to tc_aout_fix_to_chars \n"
 msgstr "llamada a tc_aout_fix_to_chars \n"
 
-#: config/tc-h8300.c:2154
+#: config/tc-h8300.c:2102
+#, c-format
 msgid "call to md_convert_frag \n"
 msgstr "llamada a md_convert_frag \n"
 
-#: config/tc-h8300.c:2216
+#: config/tc-h8300.c:2146
+#, c-format
 msgid "call tomd_estimate_size_before_relax \n"
 msgstr "llamada a tomd_estimate_size_before_relax \n"
 
-#: config/tc-h8300.c:2337 config/tc-mcore.c:2355 config/tc-pj.c:581
-#: config/tc-sh.c:3958
+#: config/tc-h8300.c:2197 config/tc-mcore.c:2282 config/tc-pj.c:538
+#: config/tc-sh.c:4270
 #, c-format
 msgid "Cannot represent relocation type %s"
 msgstr "No se puede representar el tipo de reubicación %s"
 
-#: config/tc-h8500.c:325
-msgid ":24 not valid for this opcode"
-msgstr ":24 no es válido para este código de operación"
-
-#: config/tc-h8500.c:332
-msgid "expect :8,:16 or :24"
-msgstr "se esperaba :8,:16 ó :24"
-
-#: config/tc-h8500.c:391
-msgid "syntax error in reg list"
-msgstr "error sintáctico en la lista de registros"
-
-#: config/tc-h8500.c:409
-msgid "missing final register in range"
-msgstr "falta el registro final en el rango"
-
-#: config/tc-h8500.c:498 config/tc-h8500.c:505 config/tc-h8500.c:511
-msgid "expected @(exp, Rn)"
-msgstr "se esperaba @(exp, Rn)"
-
-#: config/tc-h8500.c:527
-msgid "@Rn+ needs word register"
-msgstr "@Rn+ necesita un registro word"
-
-#: config/tc-h8500.c:537
-msgid "@Rn needs word register"
-msgstr "@Rn necesita un registro word"
-
-#: config/tc-h8500.c:838 config/tc-sh.c:1827
-#, c-format
-msgid "unhandled %d\n"
-msgstr "%d sin manejar\n"
-
-#: config/tc-h8500.c:868
-#, c-format
-msgid "operand must be absolute in range %d..%d"
-msgstr "el operando debe ser absoluto en el rango %d..%d"
-
-#: config/tc-h8500.c:963 config/tc-sh.c:2036
-#, c-format
-msgid "failed for %d\n"
-msgstr "falló para %d\n"
-
-#: config/tc-h8500.c:1128 config/tc-sh.c:2138 config/tc-sh.c:2412
-#: config/tc-w65.c:710
-msgid "invalid operands for opcode"
-msgstr "operandos inválidos para el código de operación"
-
-#. Simple range checking for FIELD againt HIGH and LOW bounds.
+#. Simple range checking for FIELD against HIGH and LOW bounds.
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1156 config/tc-hppa.c:1170
+#. Variant of CHECK_FIELD for use in md_apply_fix and other places where
+#. the current file and line number are not valid.
+#: config/tc-hppa.c:1176 config/tc-hppa.c:1190
 #, c-format
 msgid "Field out of range [%d..%d] (%d)."
 msgstr "Campo fuera de rango [%d..%d] (%d)."
 
-#. Simple alignment checking for FIELD againt ALIGN (a power of two).
+#. Simple alignment checking for FIELD against ALIGN (a power of two).
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1184
+#: config/tc-hppa.c:1204
 #, c-format
 msgid "Field not properly aligned [%d] (%d)."
 msgstr "Campo no alineado adecuadamente [%d] (%d)."
 
-#: config/tc-hppa.c:1213
+#: config/tc-hppa.c:1233
 msgid "Missing .exit\n"
 msgstr "Falta un .exit\n"
 
-#: config/tc-hppa.c:1216
+#: config/tc-hppa.c:1236
 msgid "Missing .procend\n"
 msgstr "Falta un .procend\n"
 
-#: config/tc-hppa.c:1396
+#: config/tc-hppa.c:1422
 #, c-format
 msgid "Invalid field selector.  Assuming F%%."
 msgstr "Selector de campo inválido.  Se asume F%%."
 
-#: config/tc-hppa.c:1429
+#: config/tc-hppa.c:1455
 msgid "-R option not supported on this target."
 msgstr "la opción -R no tiene soporte en este objetivo."
 
-#: config/tc-hppa.c:1445 config/tc-sparc.c:809 config/tc-sparc.c:845
+#: config/tc-hppa.c:1471 config/tc-sparc.c:811 config/tc-sparc.c:847
 #, c-format
 msgid "Internal error: can't hash `%s': %s\n"
 msgstr "Error interno: no se puede dispersar `%s': %s\n"
 
-#: config/tc-hppa.c:1453 config/tc-i860.c:201
+#: config/tc-hppa.c:1479 config/tc-i860.c:238
 #, c-format
 msgid "internal error: losing opcode: `%s' \"%s\"\n"
 msgstr "error interno: se pierde el código de operación: `%s' \"%s\"\n"
 
-#: config/tc-hppa.c:1524 config/tc-hppa.c:7048 config/tc-hppa.c:7105
+#: config/tc-hppa.c:1550 config/tc-hppa.c:7065 config/tc-hppa.c:7122
 msgid "Missing function name for .PROC (corrupted label chain)"
 msgstr "Falta el nombre de función para .PROC (cadena de etiquetas corrupta)"
 
-#: config/tc-hppa.c:1527 config/tc-hppa.c:7108
+#: config/tc-hppa.c:1553 config/tc-hppa.c:7125
 msgid "Missing function name for .PROC"
 msgstr "Falta el nombre de función para .PROC"
 
-#: config/tc-hppa.c:1634 config/tc-hppa.c:4905
-msgid "could not update architecture and machine"
-msgstr "no se puede actualizar la arquitectura y la máquina"
-
-#: config/tc-hppa.c:1842
+#: config/tc-hppa.c:1857
 msgid "Invalid Indexed Load Completer."
 msgstr "Completador de Carga Indizado Inválido."
 
-#: config/tc-hppa.c:1847
+#: config/tc-hppa.c:1862
 msgid "Invalid Indexed Load Completer Syntax."
 msgstr "Sintaxis de Completador de Carga Indizado Inválido."
 
-#: config/tc-hppa.c:1884
+#: config/tc-hppa.c:1896
 msgid "Invalid Short Load/Store Completer."
 msgstr "Completador Short de Load/Store Inválido."
 
-#: config/tc-hppa.c:1944 config/tc-hppa.c:1949
+#: config/tc-hppa.c:1956 config/tc-hppa.c:1961
 msgid "Invalid Store Bytes Short Completer"
 msgstr "Completador de Store Bytes Short Inválido."
 
-#: config/tc-hppa.c:2260 config/tc-hppa.c:2266
+#: config/tc-hppa.c:2272 config/tc-hppa.c:2278
 msgid "Invalid left/right combination completer"
 msgstr "Completador de combinación derecha/izquierda inválido"
 
-#: config/tc-hppa.c:2315 config/tc-hppa.c:2322
+#: config/tc-hppa.c:2327 config/tc-hppa.c:2334
 msgid "Invalid permutation completer"
 msgstr "Completador de permutación inválido"
 
-#: config/tc-hppa.c:2423
+#: config/tc-hppa.c:2434
 #, c-format
 msgid "Invalid Add Condition: %s"
 msgstr "Condición de Adición Inválida: %s"
 
-#: config/tc-hppa.c:2434 config/tc-hppa.c:2444
+#: config/tc-hppa.c:2445 config/tc-hppa.c:2455
 msgid "Invalid Add and Branch Condition"
 msgstr "Condición de Adición y Ramificación Inválida"
 
-#: config/tc-hppa.c:2465 config/tc-hppa.c:2603
+#: config/tc-hppa.c:2476 config/tc-hppa.c:2613
 msgid "Invalid Compare/Subtract Condition"
 msgstr "Condición de Comparación/Sustracción Inválida"
 
-#: config/tc-hppa.c:2505
+#: config/tc-hppa.c:2516
 #, c-format
 msgid "Invalid Bit Branch Condition: %c"
 msgstr "Condición de Ramificación de Bit Inválida: %c"
 
-#: config/tc-hppa.c:2591
+#: config/tc-hppa.c:2601
 #, c-format
 msgid "Invalid Compare/Subtract Condition: %s"
 msgstr "Condición de Comparación/Sustracción Inválida: %s"
 
-#: config/tc-hppa.c:2618
+#: config/tc-hppa.c:2628
 msgid "Invalid Compare and Branch Condition"
 msgstr "Condición de Comparación y Ramificación Inválida"
 
-#: config/tc-hppa.c:2714
+#: config/tc-hppa.c:2724
 msgid "Invalid Logical Instruction Condition."
 msgstr "Condición de Instrucción Lógica Inválida."
 
-#: config/tc-hppa.c:2769
+#: config/tc-hppa.c:2779
 msgid "Invalid Shift/Extract/Deposit Condition."
 msgstr "Condición Desplazar/Extraer/Depositar Inválida."
 
-#: config/tc-hppa.c:2881
+#: config/tc-hppa.c:2891
 msgid "Invalid Unit Instruction Condition."
 msgstr "Condición de Instrucción Unit Inválida."
 
-#: config/tc-hppa.c:3258 config/tc-hppa.c:3290 config/tc-hppa.c:3321
-#: config/tc-hppa.c:3351
+#: config/tc-hppa.c:3270 config/tc-hppa.c:3302 config/tc-hppa.c:3333
+#: config/tc-hppa.c:3363
 msgid "Branch to unaligned address"
 msgstr "Ramificación a dirección sin alinear"
 
-#: config/tc-hppa.c:3529
+#: config/tc-hppa.c:3541
 msgid "Invalid SFU identifier"
 msgstr "Identificador SFU inválido"
 
-#: config/tc-hppa.c:3579
+#: config/tc-hppa.c:3591
 msgid "Invalid COPR identifier"
 msgstr "Identificador COPR inválido"
 
-#: config/tc-hppa.c:3708
+#: config/tc-hppa.c:3720
 msgid "Invalid Floating Point Operand Format."
 msgstr "Formato de Operando de Coma Flotante Inválido."
 
-#: config/tc-hppa.c:3825 config/tc-hppa.c:3845 config/tc-hppa.c:3865
-#: config/tc-hppa.c:3885 config/tc-hppa.c:3905
+#: config/tc-hppa.c:3837 config/tc-hppa.c:3857 config/tc-hppa.c:3877
+#: config/tc-hppa.c:3897 config/tc-hppa.c:3917
 msgid "Invalid register for single precision fmpyadd or fmpysub"
 msgstr "Registro inválido para fmpyadd ó fmpysub de precisión simple"
 
-#: config/tc-hppa.c:3962
+#: config/tc-hppa.c:3968 config/tc-hppa.c:4928
+msgid "could not update architecture and machine"
+msgstr "no se puede actualizar la arquitectura y la máquina"
+
+#: config/tc-hppa.c:3985
 #, c-format
 msgid "Invalid operands %s"
 msgstr "Operandos inválidos %s"
 
-#: config/tc-hppa.c:4080
+#: config/tc-hppa.c:4103
 msgid "Cannot handle fixup"
 msgstr "No se puede manejar la compostura"
 
-#: config/tc-hppa.c:4381
+#: config/tc-hppa.c:4404
+#, c-format
 msgid "  -Q                      ignored\n"
 msgstr "  -Q                      ignorado\n"
 
-#: config/tc-hppa.c:4385
+#: config/tc-hppa.c:4408
+#, c-format
 msgid "  -c                      print a warning if a comment is found\n"
 msgstr "  -c                      mostrar un aviso si se encuentra un comentario\n"
 
-#: config/tc-hppa.c:4456
+#: config/tc-hppa.c:4479
 #, c-format
 msgid "no hppa_fixup entry for fixup type 0x%x"
 msgstr "no hay una entrada hppa_fixup para el tipo de compostura 0x%x"
 
-#: config/tc-hppa.c:4627
+#: config/tc-hppa.c:4650
 msgid "Unknown relocation encountered in md_apply_fix."
 msgstr "Se encontró una reubicación desconocida en md_apply_fix."
 
-#: config/tc-hppa.c:4769 config/tc-hppa.c:4794
+#: config/tc-hppa.c:4792 config/tc-hppa.c:4817
 #, c-format
 msgid "Undefined register: '%s'."
 msgstr "Registro indefinido: '%s'."
 
-#: config/tc-hppa.c:4828
+#: config/tc-hppa.c:4851
 #, c-format
 msgid "Non-absolute symbol: '%s'."
 msgstr "Símbolo no absoluto: '%s'."
 
-#: config/tc-hppa.c:4843
+#: config/tc-hppa.c:4866
 #, c-format
 msgid "Undefined absolute constant: '%s'."
 msgstr "Constante absoluta indefinida: '%s'."
 
-#: config/tc-hppa.c:4944
+#: config/tc-hppa.c:4967
 #, c-format
 msgid "Invalid FP Compare Condition: %s"
 msgstr "Condición de Comparación de FP Inválida: %s"
 
-#: config/tc-hppa.c:5000
+#: config/tc-hppa.c:5023
 #, c-format
 msgid "Invalid FTEST completer: %s"
 msgstr "Completador FTEST inválido: %s"
 
-#: config/tc-hppa.c:5067 config/tc-hppa.c:5105
+#: config/tc-hppa.c:5090 config/tc-hppa.c:5128
 #, c-format
 msgid "Invalid FP Operand Format: %3s"
 msgstr "Formato de Operando FP Inválido: %3s"
 
-#: config/tc-hppa.c:5184
+#: config/tc-hppa.c:5207
 msgid "Bad segment in expression."
 msgstr "Segmento erróneo en la expresión."
 
-#: config/tc-hppa.c:5243
+#: config/tc-hppa.c:5266
 msgid "Bad segment (should be absolute)."
 msgstr "Segmento erróneo (debe ser absoluto)."
 
-#: config/tc-hppa.c:5286
+#: config/tc-hppa.c:5309
 #, c-format
 msgid "Invalid argument location: %s\n"
 msgstr "Ubicación de argumento inválida: %s\n"
 
-#: config/tc-hppa.c:5317
+#: config/tc-hppa.c:5340
 #, c-format
 msgid "Invalid argument description: %d"
 msgstr "Descripción de argumento inválida: %d"
 
-#: config/tc-hppa.c:5340
+#: config/tc-hppa.c:5363
 #, c-format
 msgid "Invalid Nullification: (%c)"
 msgstr "Nulificación Inválida: (%c)"
 
-#: config/tc-hppa.c:6060
+#: config/tc-hppa.c:5960
+msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff"
+msgstr "El argumento para .BLOCK/.BLOCKZ debe estar entre 0 y 0x3fffffff"
+
+#: config/tc-hppa.c:6076
 #, c-format
 msgid "Invalid .CALL argument: %s"
 msgstr "Argumento de .CALL inválido: %s"
 
-#: config/tc-hppa.c:6182
+#: config/tc-hppa.c:6198
 msgid ".callinfo is not within a procedure definition"
 msgstr ".callinfo no está dentro de una definición de procedimiento"
 
-#: config/tc-hppa.c:6202
+#: config/tc-hppa.c:6218
 #, c-format
 msgid "FRAME parameter must be a multiple of 8: %d\n"
 msgstr "El parámetro FRAM debe ser un múltiplo de 8: %d\n"
 
-#: config/tc-hppa.c:6221
+#: config/tc-hppa.c:6237
 msgid "Value for ENTRY_GR must be in the range 3..18\n"
 msgstr "El valor para ENTRY_GR debe estar en el rango 3..18\n"
 
-#: config/tc-hppa.c:6233
+#: config/tc-hppa.c:6249
 msgid "Value for ENTRY_FR must be in the range 12..21\n"
 msgstr "El valor para ENTRY_FR debe estar en el rango 12..21\n"
 
-#: config/tc-hppa.c:6243
+#: config/tc-hppa.c:6259
 msgid "Value for ENTRY_SR must be 3\n"
 msgstr "El valor para ENTRY_SR debe ser 3\n"
 
-#: config/tc-hppa.c:6299
+#: config/tc-hppa.c:6315
 #, c-format
 msgid "Invalid .CALLINFO argument: %s"
 msgstr "Argumento de .CALLINFO inválido: %s"
 
-#: config/tc-hppa.c:6410
+#: config/tc-hppa.c:6427
 msgid "The .ENTER pseudo-op is not supported"
 msgstr "El pseudo-operador .ENTER no tiene soporte"
 
-#: config/tc-hppa.c:6426
+#: config/tc-hppa.c:6443
 msgid "Misplaced .entry. Ignored."
 msgstr ".entry mal colocado. Ignorado."
 
-#: config/tc-hppa.c:6430
+#: config/tc-hppa.c:6447
 msgid "Missing .callinfo."
 msgstr "Falta un .callinfo."
 
-#: config/tc-hppa.c:6496
+#: config/tc-hppa.c:6513
 msgid ".REG expression must be a register"
 msgstr "la expresión .REG debe ser un registro"
 
-#: config/tc-hppa.c:6512
+#: config/tc-hppa.c:6529
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr "expresión absoluta errónea o irreducible; se asume cero"
 
-#: config/tc-hppa.c:6523
+#: config/tc-hppa.c:6540
 msgid ".REG must use a label"
 msgstr ".REG debe usar una etiqueta"
 
-#: config/tc-hppa.c:6525
+#: config/tc-hppa.c:6542
 msgid ".EQU must use a label"
 msgstr ".EQU debe usar una etiqueta"
 
-#: config/tc-hppa.c:6578
+#: config/tc-hppa.c:6595
 msgid ".EXIT must appear within a procedure"
 msgstr ".EXIT debe aparecer dentro de un procedimiento"
 
-#: config/tc-hppa.c:6582
+#: config/tc-hppa.c:6599
 msgid "Missing .callinfo"
 msgstr "Falta un .callinfo"
 
-#: config/tc-hppa.c:6586
+#: config/tc-hppa.c:6603
 msgid "No .ENTRY for this .EXIT"
 msgstr "No hay .ENTRY para este .EXIT"
 
-#: config/tc-hppa.c:6613
+#: config/tc-hppa.c:6630
 #, c-format
 msgid "Cannot define export symbol: %s\n"
 msgstr "No se puede definir el símbolo de exportación: %s\n"
 
-#: config/tc-hppa.c:6671
+#: config/tc-hppa.c:6688
 #, c-format
 msgid "Using ENTRY rather than CODE in export directive for %s"
 msgstr "Utilizando ENTRY en lugar de CODE en la directiva de exportación para %s"
 
-#: config/tc-hppa.c:6788
+#: config/tc-hppa.c:6805
 #, c-format
 msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
 msgstr "Argumento de .EXPORT/.IMPORT indefinido (ignorado): %s"
 
-#: config/tc-hppa.c:6870
+#: config/tc-hppa.c:6887
 msgid "Missing label name on .LABEL"
 msgstr "Falta el nombre de etiqueta en .LABEL"
 
-#: config/tc-hppa.c:6875
+#: config/tc-hppa.c:6892
 msgid "extra .LABEL arguments ignored."
 msgstr "se ignoran los argumentos extra de .LABEL."
 
-#: config/tc-hppa.c:6892
+#: config/tc-hppa.c:6909
 msgid "The .LEAVE pseudo-op is not supported"
 msgstr "El pseudo-operador .LEAVE no tiene soporte"
 
-#: config/tc-hppa.c:6931
+#: config/tc-hppa.c:6948
 msgid "Unrecognized .LEVEL argument\n"
 msgstr "No se reconoce el argumento de .LEVEL\n"
 
-#: config/tc-hppa.c:6967
+#: config/tc-hppa.c:6984
 #, c-format
 msgid "Cannot define static symbol: %s\n"
 msgstr "No se puede definir el símbolo estático: %s\n"
 
-#: config/tc-hppa.c:7002
+#: config/tc-hppa.c:7019
 msgid "Nested procedures"
 msgstr "Procedimientos anidados"
 
-#: config/tc-hppa.c:7012
+#: config/tc-hppa.c:7029
 msgid "Cannot allocate unwind descriptor\n"
 msgstr "No se puede asignar un descriptor de desenredo\n"
 
-#: config/tc-hppa.c:7112
+#: config/tc-hppa.c:7129
 msgid "misplaced .procend"
 msgstr ".procend mal colocado"
 
-#: config/tc-hppa.c:7115
+#: config/tc-hppa.c:7132
 msgid "Missing .callinfo for this procedure"
 msgstr "Falta un .callinfo para este procedimiento"
 
-#: config/tc-hppa.c:7118
+#: config/tc-hppa.c:7135
 msgid "Missing .EXIT for a .ENTRY"
 msgstr "Falta un .EXIT para un .ENTRY"
 
-#: config/tc-hppa.c:7156
+#: config/tc-hppa.c:7173
 msgid "Not in a space.\n"
 msgstr "No está en un espacio.\n"
 
-#: config/tc-hppa.c:7159
+#: config/tc-hppa.c:7176
 msgid "Not in a subspace.\n"
 msgstr "No está en un subespacio.\n"
 
-#: config/tc-hppa.c:7250
+#: config/tc-hppa.c:7267
 msgid "Invalid .SPACE argument"
 msgstr "Argumento de .SPACE inválido"
 
-#: config/tc-hppa.c:7297
+#: config/tc-hppa.c:7314
 msgid "Can't change spaces within a procedure definition. Ignored"
 msgstr "No se pueden cambiar espacios dentro de una definición de procedimiento. Ignorado"
 
-#: config/tc-hppa.c:7426
+#: config/tc-hppa.c:7443
 #, c-format
 msgid "Undefined space: '%s' Assuming space number = 0."
 msgstr "Espacio indefinido: '%s' Se asume que el número de espacio = 0."
 
-#: config/tc-hppa.c:7450
+#: config/tc-hppa.c:7467
 msgid "Must be in a space before changing or declaring subspaces.\n"
 msgstr "Debe estar en un espacio antes de cambiar o declarar subespacios.\n"
 
-#: config/tc-hppa.c:7454
+#: config/tc-hppa.c:7471
 msgid "Can't change subspaces within a procedure definition. Ignored"
 msgstr "No se pueden cambiar subespacios dentro de una definición de procedimiento. Ignorado"
 
-#: config/tc-hppa.c:7489
+#: config/tc-hppa.c:7507
 msgid "Parameters of an existing subspace can't be modified"
 msgstr "No se pueden modificar los parámetros de un subespacio existente"
 
-#: config/tc-hppa.c:7540
+#: config/tc-hppa.c:7559
 msgid "Alignment must be a power of 2"
 msgstr "La alineación debe ser una potencia de 2"
 
-#: config/tc-hppa.c:7582
+#: config/tc-hppa.c:7606
 msgid "FIRST not supported as a .SUBSPACE argument"
 msgstr "FIRST no tiene soporte como un argumento de .SUBSPACE"
 
-#: config/tc-hppa.c:7584
+#: config/tc-hppa.c:7608
 msgid "Invalid .SUBSPACE argument"
 msgstr "Argumento de .SUBSPACE inválido"
 
-#: config/tc-hppa.c:7764
+#: config/tc-hppa.c:7797
 #, c-format
 msgid "Internal error: Unable to find containing space for %s."
 msgstr "Error interno: No se puede encontrar el espacio contenedor para %s."
 
-#: config/tc-hppa.c:7803
+#: config/tc-hppa.c:7837
 #, c-format
 msgid "Out of memory: could not allocate new space chain entry: %s\n"
 msgstr "Memoria agotada: no se puede asignar una nueva entrada de cadena de espacio: %s\n"
 
-#: config/tc-hppa.c:7889
+#: config/tc-hppa.c:7926
 #, c-format
 msgid "Out of memory: could not allocate new subspace chain entry: %s\n"
 msgstr "Memoria agotada: no se puede asignar una nueva entrada de cadena de subespacio: %s\n"
 
-#: config/tc-hppa.c:8622
+#: config/tc-hppa.c:8662
 #, c-format
 msgid "Symbol '%s' could not be created."
 msgstr "No se puede crear el símbolo '%s'."
 
-#: config/tc-hppa.c:8626
+#: config/tc-hppa.c:8666
 msgid "No memory for symbol name."
 msgstr "No hay memoria para el nombre del símbolo."
 
-#: config/tc-i386.c:689
+#: config/tc-i386.c:721
 #, c-format
 msgid "%s shortened to %s"
 msgstr "%s reducido a %s"
 
-#: config/tc-i386.c:745
+#: config/tc-i386.c:777
 msgid "same type of prefix used twice"
 msgstr "se utilizó dos veces el mismo tipo de prefijo"
 
-#: config/tc-i386.c:763
+#: config/tc-i386.c:795
 msgid "64bit mode not supported on this CPU."
 msgstr "el modo de 64bit no tiene soporte en este CPU."
 
-#: config/tc-i386.c:767
+#: config/tc-i386.c:799
 msgid "32bit mode not supported on this CPU."
 msgstr "el modo de 32bit no tiene soporte en este CPU."
 
-#: config/tc-i386.c:800
+#: config/tc-i386.c:832
 msgid "bad argument to syntax directive."
 msgstr "argumento erróneo para la directiva de sintaxis."
 
-#: config/tc-i386.c:844
+#: config/tc-i386.c:884
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr "no hay tal arquitectura: `%s'"
 
-#: config/tc-i386.c:849
+#: config/tc-i386.c:889
 msgid "missing cpu architecture"
 msgstr "falta la arquitectura de cpu"
 
-#: config/tc-i386.c:863
+#: config/tc-i386.c:903
 #, c-format
 msgid "no such architecture modifier: `%s'"
 msgstr "no hay tal modificador de arquitectura: `%s'"
 
-#: config/tc-i386.c:880 config/tc-i386.c:5013
+#: config/tc-i386.c:919 config/tc-i386.c:5342
 msgid "Unknown architecture"
 msgstr "Arquitectura desconocida"
 
-#: config/tc-i386.c:915 config/tc-i386.c:938 config/tc-m68k.c:3816
+#: config/tc-i386.c:1247
 #, c-format
-msgid "Internal Error:  Can't hash %s: %s"
-msgstr "Error Interno:  No se puede dispersar %s: %s"
+msgid "unknown relocation (%u)"
+msgstr "reubicación desconocida (%u)"
+
+#: config/tc-i386.c:1249
+#, c-format
+msgid "%u-byte relocation cannot be applied to %u-byte field"
+msgstr "la reubicación de %u-bytes no se puede aplicar al campo %u-bytes"
 
-#: config/tc-i386.c:1192
-msgid "There are no unsigned pc-relative relocations"
-msgstr "No hay reubicaciones relativas a pc sin signo"
+#: config/tc-i386.c:1253
+msgid "non-pc-relative relocation for pc-relative field"
+msgstr "reubicación no relativa al para el campo relativo al pc"
 
-#: config/tc-i386.c:1199 config/tc-i386.c:5225
+#: config/tc-i386.c:1258
+msgid "relocated field and relocation type differ in signedness"
+msgstr "el campo reubicado y el tipo de reubicación difieren en signo"
+
+#: config/tc-i386.c:1267
+msgid "there are no unsigned pc-relative relocations"
+msgstr "no hay reubicaciones relativas a pc sin signo"
+
+#: config/tc-i386.c:1275
 #, c-format
-msgid "can not do %d byte pc-relative relocation"
-msgstr "no se puede hacer la reubicación relativa a pc de %d bytes"
+msgid "cannot do %u byte pc-relative relocation"
+msgstr "no se puede hacer la reubicación relativa a pc de %u bytes"
+
+#: config/tc-i386.c:1292
+#, c-format
+msgid "cannot do %s %u byte relocation"
+msgstr "no se puede hacer la reubicación %s de %u bytes"
 
-#: config/tc-i386.c:1216
+#: config/tc-i386.c:1496 config/tc-i386.c:2527
 #, c-format
-msgid "can not do %s %d byte relocation"
-msgstr "no se puede hacer la reubicación %s de %d byte"
+msgid "ambiguous operand size for `%s'"
+msgstr "Tamaño de operando ambiguo para `%s'"
 
-#: config/tc-i386.c:1428
+#: config/tc-i386.c:1544
 #, c-format
 msgid "can't use register '%%%s' as operand %d in '%s'."
 msgstr "no se puede utilizar el registro '%%%s' como operando %d en '%s'."
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:1457
+#: config/tc-i386.c:1573
 #, c-format
 msgid "translating to `%sp'"
 msgstr "traduciendo a `%sp'"
 
-#: config/tc-i386.c:1502
+#: config/tc-i386.c:1618
 #, c-format
-msgid "can't encode register '%%%s' in an instruction requiring REX prefix.\n"
-msgstr "No se pueden codificar el registro '%%%s' en una instrucción que requiere el prefijo REX.\n"
+msgid "can't encode register '%%%s' in an instruction requiring REX prefix."
+msgstr "no se pueden codificar el registro '%%%s' en una instrucción que requiere el prefijo REX."
 
-#: config/tc-i386.c:1541 config/tc-i386.c:1636
+#: config/tc-i386.c:1659 config/tc-i386.c:1767
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr "no hay tal instrucción: `%s'"
 
-#: config/tc-i386.c:1551 config/tc-i386.c:1668
+#: config/tc-i386.c:1670 config/tc-i386.c:1799
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr "carácter inválido %s en el mnemónico"
 
-#: config/tc-i386.c:1558
+#: config/tc-i386.c:1677
 msgid "expecting prefix; got nothing"
 msgstr "se esperaba un prefijo; se obtuvo nada"
 
-#: config/tc-i386.c:1560
+#: config/tc-i386.c:1679
 msgid "expecting mnemonic; got nothing"
 msgstr "se esperaba un mnemónico; se obtuvo nada"
 
-#: config/tc-i386.c:1579
+#: config/tc-i386.c:1695 config/tc-i386.c:1818
+#, c-format
+msgid "`%s' is only supported in 64-bit mode"
+msgstr "`%s' sólo tiene soporte en modo de 64-bit"
+
+#: config/tc-i386.c:1696 config/tc-i386.c:1817
+#, c-format
+msgid "`%s' is not supported in 64-bit mode"
+msgstr "`%s' no tiene soporte en modo de 64-bit"
+
+#: config/tc-i386.c:1707
 #, c-format
 msgid "redundant %s prefix"
 msgstr "prefijo %s redundante"
 
-#: config/tc-i386.c:1677
+#: config/tc-i386.c:1824
 #, c-format
-msgid "`%s' is not supported on `%s'"
-msgstr "`%s' no tiene soporte en `%s'"
+msgid "`%s' is not supported on `%s%s'"
+msgstr "`%s' no tiene soporte en `%s%s'"
 
-#: config/tc-i386.c:1682
+#: config/tc-i386.c:1831
 msgid "use .code16 to ensure correct addressing mode"
 msgstr "use .code16 para asegurar el modo de direccionamiento correcto"
 
-#: config/tc-i386.c:1689
+#: config/tc-i386.c:1844
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr "se espera una instrucción de cadena después de `%s'"
 
-#: config/tc-i386.c:1717
+#: config/tc-i386.c:1878
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr "caracter inválido %s antes del operando %d"
 
-#: config/tc-i386.c:1731
+#: config/tc-i386.c:1892
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr "paréntesis sin balancear en el operando %d."
 
-#: config/tc-i386.c:1734
+#: config/tc-i386.c:1895
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr "llaves sin balancear en el operando %d."
 
-#: config/tc-i386.c:1743
+#: config/tc-i386.c:1904
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr "carácter inválido %s en el operando %d"
 
-#: config/tc-i386.c:1770
+#: config/tc-i386.c:1931
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr "operandos espurios; (%d operandos/instrucción máximo)"
 
-#: config/tc-i386.c:1793
+#: config/tc-i386.c:1954
 msgid "expecting operand after ','; got nothing"
 msgstr "se esperaba un operando después de ','; se obtuvo nada"
 
-#: config/tc-i386.c:1798
+#: config/tc-i386.c:1959
 msgid "expecting operand before ','; got nothing"
 msgstr "se esperaba un operando antes de ','; se obtuvo nada"
 
 #. We found no match.
-#: config/tc-i386.c:2140
+#: config/tc-i386.c:2336
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr "sufijo u operandos inválidos para `%s'"
 
-#: config/tc-i386.c:2151
+#: config/tc-i386.c:2347
 #, c-format
 msgid "indirect %s without `*'"
 msgstr "%s indirecto sin `*'"
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:2159
+#: config/tc-i386.c:2355
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr "prefijo `%s' por sí solo"
 
-#: config/tc-i386.c:2188 config/tc-i386.c:2203
+#: config/tc-i386.c:2384 config/tc-i386.c:2399
 #, c-format
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr "`%s' operando %d debe usar el segmento `%%es'"
 
-#: config/tc-i386.c:2283
+#: config/tc-i386.c:2509
 msgid "no instruction mnemonic suffix given and no register operands; can't size instruction"
 msgstr "no se dio un sufijo mnemónico de instrucción y ningún operando de registro; no se puede determinar el tamaño de la instrucción"
 
 #. Prohibit these changes in the 64bit mode, since the
 #. lowering is more complicated.
-#: config/tc-i386.c:2367 config/tc-i386.c:2426 config/tc-i386.c:2443
-#: config/tc-i386.c:2475 config/tc-i386.c:2508
+#: config/tc-i386.c:2610 config/tc-i386.c:2669 config/tc-i386.c:2686
+#: config/tc-i386.c:2718 config/tc-i386.c:2751
 #, c-format
 msgid "Incorrect register `%%%s' used with `%c' suffix"
 msgstr "Se utilizó el registro incorrecto `%%%s' con el sufijo `%c'"
 
-#: config/tc-i386.c:2375 config/tc-i386.c:2433 config/tc-i386.c:2515
+#: config/tc-i386.c:2618 config/tc-i386.c:2676 config/tc-i386.c:2758
 #, c-format
 msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
 msgstr "utilizando `%%%s' en lugar de `%%%s' debido al sufijo `%c'"
 
-#: config/tc-i386.c:2390 config/tc-i386.c:2411 config/tc-i386.c:2462
-#: config/tc-i386.c:2493
+#: config/tc-i386.c:2633 config/tc-i386.c:2654 config/tc-i386.c:2705
+#: config/tc-i386.c:2736
 #, c-format
 msgid "`%%%s' not allowed with `%s%c'"
 msgstr "no se permite `%%%s' con `%s%c'"
 
-#: config/tc-i386.c:2556
+#: config/tc-i386.c:2799
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr "no se dio un sufijo mnemónico de instrucción; no se puede determinar el tamaño inmediato"
 
-#: config/tc-i386.c:2589
+#: config/tc-i386.c:2832
 #, c-format
 msgid "no instruction mnemonic suffix given; can't determine immediate size %x %c"
 msgstr "no se dio un sufijo mnemónico de instrucción; no se puede determinar el tamaño inmediato %x %c"
 
 #. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2638
+#: config/tc-i386.c:2881
 #, c-format
 msgid "translating to `%s %%%s,%%%s'"
 msgstr "traduciendo a `%s %%%s,%%%s'"
 
 #. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2645
+#: config/tc-i386.c:2888
 #, c-format
 msgid "translating to `%s %%%s'"
 msgstr "traduciendo a `%s %%%s'"
 
-#: config/tc-i386.c:2663
+#: config/tc-i386.c:2906
 #, c-format
 msgid "you can't `pop %%cs'"
 msgstr "no se puede hacer `pop %%cs'"
 
-#. lea
-#: config/tc-i386.c:2682
-msgid "segment override on `lea' is ineffectual"
-msgstr "la anulación del segmento en `lea' no tiene efecto"
+#: config/tc-i386.c:2927
+#, c-format
+msgid "segment override on `%s' is ineffectual"
+msgstr "la anulación del segmento en `%s' no tiene efecto"
 
-#: config/tc-i386.c:2991 config/tc-i386.c:3085 config/tc-i386.c:3130
+#: config/tc-i386.c:3236 config/tc-i386.c:3330 config/tc-i386.c:3375
 msgid "skipping prefixes on this instruction"
 msgstr "saltando los prefijos en esta instrucción"
 
-#: config/tc-i386.c:3150
+#: config/tc-i386.c:3395
 msgid "16-bit jump out of range"
 msgstr "salto de 16-bit fuera de rango"
 
-#: config/tc-i386.c:3159
+#: config/tc-i386.c:3404
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr "no se puede manejar un segmento no absoluto en `%s'"
 
-#: config/tc-i386.c:3601
+#: config/tc-i386.c:3897
 #, c-format
-msgid "@%s reloc is not supported in %s bit mode"
-msgstr "las reubicaciones @%s no tienen soporte en modo de %s bits"
+msgid "@%s reloc is not supported with %d-bit output format"
+msgstr "las reubicaciones @%s no tienen soporte con el formato de salida de %d bits"
 
-#: config/tc-i386.c:3677
+#: config/tc-i386.c:3986
 msgid "only 1 or 2 immediate operands are allowed"
 msgstr "sólo se permiten 1 ó dos operandos inmediatos"
 
-#: config/tc-i386.c:3700 config/tc-i386.c:3892
+#: config/tc-i386.c:4007 config/tc-i386.c:4218
 #, c-format
 msgid "junk `%s' after expression"
 msgstr "basura `%s' después de la expresión"
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3711
+#: config/tc-i386.c:4016
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr "la expresión inmediata faltante o inválida `%s' se toma como 0"
 
-#: config/tc-i386.c:3743 config/tc-i386.c:3958
+#: config/tc-i386.c:4041 config/tc-i386.c:4277
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr "segmento %s sin implementar en el operando"
 
-#: config/tc-i386.c:3745 config/tc-i386.c:3960
-#, c-format
-msgid "unimplemented segment type %d in operand"
-msgstr "tipo de segmento %d sin implementar en el operando"
-
-#: config/tc-i386.c:3789 config/tc-i386.c:6002
+#: config/tc-i386.c:4088
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr "se esperaba un factor de escala de 1, 2, 4, u 8: se obtuvo `%s'"
 
-#: config/tc-i386.c:3796
+#: config/tc-i386.c:4097
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr "factor de escala de %d sin un registro índice"
 
-#: config/tc-i386.c:3912
+#: config/tc-i386.c:4236
 #, c-format
 msgid "bad expression used with @%s"
 msgstr "se utilizó una expresión errónea con @%s"
 
-#. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3934
-#, c-format
-msgid "missing or invalid displacement expression `%s' taken as 0"
-msgstr "la expresión de desubicación faltante o inválida `%s' se toma como 0"
-
-#: config/tc-i386.c:4058
+#: config/tc-i386.c:4386
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr "`%s' no es una expresión base/índice válida"
 
-#: config/tc-i386.c:4062
+#: config/tc-i386.c:4390
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr "`%s' no es una expresión de %s bit base/índice válida"
 
-#: config/tc-i386.c:4137
+#: config/tc-i386.c:4464
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr "operando de memoria `%s' erróneo"
 
-#: config/tc-i386.c:4152
+#: config/tc-i386.c:4479
 #, c-format
 msgid "junk `%s' after register"
 msgstr "basura `%s' después del registro"
 
-#: config/tc-i386.c:4161 config/tc-i386.c:4276 config/tc-i386.c:4314
+#: config/tc-i386.c:4488 config/tc-i386.c:4603 config/tc-i386.c:4641
 #, c-format
 msgid "bad register name `%s'"
 msgstr "nombre de registro `%s' erróneo"
 
-#: config/tc-i386.c:4169
+#: config/tc-i386.c:4496
 msgid "immediate operand illegal with absolute jump"
 msgstr "operando inmediato ilegal con salto absoluto"
 
-#: config/tc-i386.c:4191
+#: config/tc-i386.c:4518
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr "demasiadas referencias a memoria para `%s'"
 
-#: config/tc-i386.c:4269
+#: config/tc-i386.c:4596
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr "se esperaba `,' ó `)' después del registro índice en `%s'"
 
-#: config/tc-i386.c:4293
+#: config/tc-i386.c:4620
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr "se esperaba `)' después del factor de escala en `%s'"
 
-#: config/tc-i386.c:4300
+#: config/tc-i386.c:4627
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr "se esperaba un registro índice o un factor de escala después de `,'; se obtuvo '%c'"
 
-#: config/tc-i386.c:4307
+#: config/tc-i386.c:4634
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr "se esperaba `,' ó `)' después del registro base en `%s'"
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:4348
+#: config/tc-i386.c:4675
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr "caracter inválido %s al inicio del operando %d `%s'"
 
-#: config/tc-i386.c:4531
+#: config/tc-i386.c:4850
 msgid "long jump required"
 msgstr "se requiere un salto largo"
 
-#: config/tc-i386.c:4796
+#: config/tc-i386.c:5127
 msgid "Bad call to md_atof ()"
 msgstr "Llamada errónea a md_atof ()"
 
-#: config/tc-i386.c:4964
+#: config/tc-i386.c:5294
 msgid "No compiled in support for x86_64"
 msgstr "No se compiló el soporte para x86_64"
 
-#: config/tc-i386.c:4985
+#: config/tc-i386.c:5315
+#, c-format
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
@@ -4558,7 +4893,8 @@ msgstr ""
 "  -q                      omite algunos avisos\n"
 "  -s                      ignorado\n"
 
-#: config/tc-i386.c:4993
+#: config/tc-i386.c:5323
+#, c-format
 msgid ""
 "  -n                      Do not optimize code alignment\n"
 "  -q                      quieten some warnings\n"
@@ -4566,127 +4902,211 @@ msgstr ""
 "  -n                      No optimiza la alineación de código\n"
 "  -q                      omite algunos avisos\n"
 
-#: config/tc-i386.c:5095 config/tc-s390.c:1841
+#: config/tc-i386.c:5425 config/tc-s390.c:1861
 msgid "GOT already in symbol table"
 msgstr "GOT ya está en la tabla de símbolos"
 
-#: config/tc-i386.c:5240
+#: config/tc-i386.c:5568
+#, c-format
+msgid "can not do %d byte pc-relative relocation"
+msgstr "no se puede hacer la reubicación relativa a pc de %d bytes"
+
+#: config/tc-i386.c:5586
 #, c-format
 msgid "can not do %d byte relocation"
 msgstr "no se puede hacer la reubicación de %d bytes"
 
-#: config/tc-i386.c:5308 config/tc-s390.c:2285
+#: config/tc-i386.c:5657 config/tc-s390.c:2307
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr "no se puede representar el tipo de reubicación %s"
 
-#: config/tc-i386.c:5604
+#: config/tc-i386.c:5912
+#, c-format
+msgid "invalid operand for '%s' ('%s' unexpected)"
+msgstr "operando inválido para '%s' ('%s' inesperado)"
+
+#: config/tc-i386.c:5924
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr "demasiadas referencias a memoria para '%s'"
 
-#: config/tc-i386.c:5767
+#. See the comments in intel_bracket_expr.
+#: config/tc-i386.c:5935
+#, c-format
+msgid "Treating `%s' as memory reference"
+msgstr "Se trata `%s' como una referencia de memoria"
+
+#: config/tc-i386.c:6247
+#, c-format
+msgid "Unknown operand modifier `%s'"
+msgstr "Modificador de operando `%s' desconocido"
+
+#: config/tc-i386.c:6262
+msgid "Conflicting operand modifiers"
+msgstr "Modificadores de operando en conflicto"
+
+#: config/tc-i386.c:6311
+msgid "Invalid operand to `OFFSET'"
+msgstr "Operando inválido para `OFFSET'"
+
+#: config/tc-i386.c:6384
 #, c-format
-msgid "Unknown operand modifier `%s'\n"
-msgstr "Modificador de operando `%s' desconocido\n"
+msgid "`[%.*s]' taken to mean just `%.*s'"
+msgstr "se toma `[%.*s]' y sólo signifiqua `%.*s'"
 
-#: config/tc-i386.c:5974
+#: config/tc-i386.c:6474
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr "`%s' no es un registro de segmento válido"
 
-#: config/tc-i386.c:5984 config/tc-i386.c:6105
-msgid "Register scaling only allowed in memory operands."
-msgstr "El escalamiento de registros sólo se permite en operandos de memoria."
+#: config/tc-i386.c:6478
+msgid "Extra segment override ignored"
+msgstr "Se ignora la sobreescritura de segmento extra"
 
-#: config/tc-i386.c:6015
-msgid "Too many register references in memory operand.\n"
-msgstr "Demasiadas referencias a registros en un operando de memoria.\n"
+#: config/tc-i386.c:6512 config/tc-i386.c:6681
+msgid "Register scaling only allowed in memory operands"
+msgstr "El escalamiento de registros sólo se permite en operandos de memoria"
 
-#: config/tc-i386.c:6084
+#: config/tc-i386.c:6534 config/tc-i386.c:6658
 #, c-format
-msgid "Syntax error. Expecting a constant. Got `%s'.\n"
-msgstr "Error sintáctico. Se esperaba una constante. Se obtuvo `%s'.\n"
+msgid "Syntax error: Expecting a constant, got `%s'"
+msgstr "Error sintáctico: Se esperaba una constante, se obtuvo `%s'"
+
+#: config/tc-i386.c:6562
+msgid "Too many register references in memory operand"
+msgstr "Demasiadas referencias a registros en un operando de memoria"
+
+#: config/tc-i386.c:6573
+msgid "Using register names in OFFSET expressions is deprecated"
+msgstr "El uso de nombres de registro en expresiones OFFSET es obsoleto"
 
-#: config/tc-i386.c:6154
+#: config/tc-i386.c:6586
+msgid "Invalid use of register"
+msgstr "Uso inválido de registro"
+
+#: config/tc-i386.c:6731
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr "Elemento '%s' no reconocido"
 
-#: config/tc-i386.c:6171
+#: config/tc-i386.c:6748
 #, c-format
-msgid "Unexpected token `%s'\n"
-msgstr "Elemento `%s' inesperado\n"
+msgid "Unexpected token `%s'"
+msgstr "Elemento `%s' inesperado"
+
+#: config/tc-i386.c:6910
+msgid "`:' expected"
+msgstr "se esperaba `:'"
 
-#: config/tc-i386.c:6315
+#: config/tc-i386.c:6935
 #, c-format
-msgid "Unrecognized token `%s'\n"
-msgstr "Elemento `%s' no reconocido\n"
+msgid "Unrecognized token `%s'"
+msgstr "Elemento `%s' no reconocido"
+
+#: config/tc-i386.c:7070
+msgid "Bad .section directive: want a,l,w,x,M,S,G,T in string"
+msgstr "Directiva .section errónea: se quiere a,l,w,x,M,S,G,T en la cadena"
+
+#: config/tc-i386.c:7073
+msgid "Bad .section directive: want a,w,x,M,S,G,T in string"
+msgstr "Directiva .section errónea: se quiere a,w,x,M,S,G,T en la cadena"
+
+#: config/tc-i386.c:7092
+msgid ".largecomm supported only in 64bit mode, producing .comm"
+msgstr ".largecomm sólo tiene soporte en modo de 64bit, se produce .comm"
+
+#: config/tc-i860.c:124
+msgid "Directive .dual available only with -mintel-syntax option"
+msgstr "La directiva .dual sólo está disponible con la opción -mintel-syntax"
+
+#: config/tc-i860.c:134
+msgid "Directive .enddual available only with -mintel-syntax option"
+msgstr "La directiva .enddual sólo está disponible con la opción -mintel-syntax"
+
+#: config/tc-i860.c:147
+msgid "Directive .atmp available only with -mintel-syntax option"
+msgstr "La directiva .atmp sólo está disponible con la opción -mintel-syntax"
 
-#: config/tc-i860.c:165 config/tc-i860.c:169
+#: config/tc-i860.c:169 config/tc-i860.c:173
 msgid "Unknown temporary pseudo register"
 msgstr "Pseudo registro temporal desconocido"
 
-#: config/tc-i860.c:192 config/tc-mips.c:1104
+#: config/tc-i860.c:229 config/tc-mips.c:1412
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr "error interno: no se puede dispersar `%s': %s\n"
 
-#: config/tc-i860.c:212
+#: config/tc-i860.c:249
 msgid "Defective assembler.  No assembly attempted."
 msgstr "Ensamblador defectuoso.  No se intentó ensamblar."
 
-#: config/tc-i860.c:362
+#: config/tc-i860.c:395 config/tc-i860.c:940 config/tc-m68k.c:3443
+#: config/tc-m68k.c:3475 config/tc-sparc.c:2657
+msgid "failed sanity check."
+msgstr "falló la prueba de sanidad."
+
+#: config/tc-i860.c:402
 #, c-format
 msgid "Expanded opcode after delayed branch: `%s'"
 msgstr "Código de operación expandido después de la ramificación retardada: `%s'"
 
-#: config/tc-i860.c:366
+#: config/tc-i860.c:406
 #, c-format
 msgid "Expanded opcode in dual mode: `%s'"
 msgstr "Código de operación expandido en modo dual: `%s'"
 
-#: config/tc-i860.c:370
+#: config/tc-i860.c:410
 #, c-format
 msgid "An instruction was expanded (%s)"
 msgstr "Se expandió una instrucción (%s)"
 
 # ¿pipeline tiene traducción al español? cfuga
-#: config/tc-i860.c:643
+#: config/tc-i860.c:676
 msgid "Pipelined instruction: fsrc1 = fdest"
 msgstr "Instrucción en `pipeline':  fsrc1 = fdest"
 
-#: config/tc-i860.c:844 config/tc-i860.c:851 config/tc-i860.c:858
+#: config/tc-i860.c:879 config/tc-i860.c:886 config/tc-i860.c:893
 msgid "Assembler does not yet support PIC"
 msgstr "El ensamblador aún no tiene soporte para PIC"
 
-#: config/tc-i860.c:919
+#: config/tc-i860.c:957
 #, c-format
 msgid "Illegal operands for %s"
 msgstr "Operandos ilegales para %s"
 
-#: config/tc-i860.c:947 config/tc-sparc.c:2834
-msgid "bad segment"
-msgstr "segmento erróneo"
+#: config/tc-i860.c:974
+#, c-format
+msgid "'d.%s' must be 8-byte aligned"
+msgstr "'d.%s' debe estar alineado a 8-bytes"
 
-#: config/tc-i860.c:1037
+#: config/tc-i860.c:982
+#, c-format
+msgid "Prefix 'd.' invalid for instruction `%s'"
+msgstr "Prefijo 'd.' inválido para la instrucción `%s'"
+
+#: config/tc-i860.c:1088
 msgid "i860_estimate_size_before_relax\n"
 msgstr "i860_estimate_size_before_relax\n"
 
-#: config/tc-i860.c:1134
+#: config/tc-i860.c:1187
+#, c-format
 msgid ""
 "  -EL\t\t\t  generate code for little endian mode (default)\n"
 "  -EB\t\t\t  generate code for big endian mode\n"
 "  -mwarn-expand\t\t  warn if pseudo operations are expanded\n"
 "  -mxp\t\t\t  enable i860XP support (disabled by default)\n"
+"  -mintel-syntax\t  enable Intel syntax (default to AT&T/SVR4)\n"
 msgstr ""
-"  -EL\t\t\t  generar código para el modo little endian (por omisión)\n"
+"  -EL\t\t\t  generar código para el modo little endian (por defecto)\n"
 "  -EB\t\t\t  generar código para el modo big endian\n"
 "  -mwarn-expand\t\t  avisar si se expanden las pseudo operaciones\n"
-"  -mxp\t\t\t activar el soporte para i860XP (desactivado por omisión)\n"
+"  -mxp\t\t\t activar el soporte para i860XP (desactivado por defecto)\n"
+"  -mintel-syntax\t activar la sintaxis Intel (AT&T/SVR4 por defecto)\n"
 
 #. SVR4 compatibility flags.
-#: config/tc-i860.c:1141
+#: config/tc-i860.c:1195
+#, c-format
 msgid ""
 "  -V\t\t\t  print assembler version number\n"
 "  -Qy, -Qn\t\t  ignored\n"
@@ -4694,78 +5114,133 @@ msgstr ""
 "  -V\t\t\t  mostrar el número de versión del ensamblador\n"
 "  -Qy, -Qn\t\t  ignorado\n"
 
-#: config/tc-i860.c:1210
+#: config/tc-i860.c:1258
 msgid "This immediate requires 0 MOD 2 alignment"
 msgstr "Este inmediato requiere alineación 0 MOD 2"
 
-#: config/tc-i860.c:1213
+#: config/tc-i860.c:1261
 msgid "This immediate requires 0 MOD 4 alignment"
 msgstr "Este inmediato requiere alineación 0 MOD 4"
 
-#: config/tc-i860.c:1216
+#: config/tc-i860.c:1264
 msgid "This immediate requires 0 MOD 8 alignment"
 msgstr "Este inmediato requiere alineación 0 MOD 8"
 
-#: config/tc-i860.c:1219
+#: config/tc-i860.c:1267
 msgid "This immediate requires 0 MOD 16 alignment"
 msgstr "Este inmediato requiere alineación 0 MOD 16"
 
-#: config/tc-i860.c:1317
+#: config/tc-i860.c:1362
 msgid "5-bit immediate too large"
 msgstr "el inmediato de 5-bit es demasiado grande"
 
-#: config/tc-i860.c:1320
+#: config/tc-i860.c:1365
 msgid "5-bit field must be absolute"
 msgstr "el campo de 5-bit debe ser absoluto"
 
-#: config/tc-i860.c:1365 config/tc-i860.c:1388
+#: config/tc-i860.c:1410 config/tc-i860.c:1433
 msgid "A branch offset requires 0 MOD 4 alignment"
 msgstr "Un desplazamiento de ramificación requiere alineación 0 MOD 4"
 
-#: config/tc-i860.c:1409
+#: config/tc-i860.c:1454
 #, c-format
 msgid "Unrecognized fix-up (0x%08lx)"
 msgstr "Compostura no reconocida (0x%08lx)"
 
-#: config/tc-i860.h:80
+#: config/tc-i860.h:76
 msgid "i860_convert_frag\n"
 msgstr "i860_convert_frag\n"
 
-#: config/tc-i960.c:574
+#: config/tc-i960.c:488
 #, c-format
 msgid "Hashing returned \"%s\"."
 msgstr "La dispersión devolvió \"%s\"."
 
-#. Offset of last character in opcode mnemonic
-#: config/tc-i960.c:608
+#: config/tc-i960.c:584 config/tc-i960.c:1114
+msgid "expression syntax error"
+msgstr "error sintáctico en la expresión"
+
+#: config/tc-i960.c:620
+msgid "attempt to branch into different segment"
+msgstr "se intentó ramificar en un segmento diferente"
+
+#: config/tc-i960.c:624
+#, c-format
+msgid "target of %s instruction must be a label"
+msgstr "el objetivo de la instrucción %s debe ser una etiqueta"
+
+#: config/tc-i960.c:734
+msgid "unaligned register"
+msgstr "registro sin alinear"
+
+#: config/tc-i960.c:756
+msgid "no such sfr in this architecture"
+msgstr "no hay un sfr en esta arquitectura"
+
+#: config/tc-i960.c:794
+msgid "illegal literal"
+msgstr "literal ilegal"
+
+#: config/tc-i960.c:837
+msgid "unmatched '['"
+msgstr "'[' desemparejado"
+
+#: config/tc-i960.c:844
+msgid "garbage after index spec ignored"
+msgstr "se ignora la basura después de la especificación del índice"
+
+#: config/tc-i960.c:944
+msgid "invalid index register"
+msgstr "registro índice inválido"
+
+#: config/tc-i960.c:967
+msgid "invalid scale factor"
+msgstr "factor de escala inválido"
+
+#: config/tc-i960.c:1191
+msgid "architecture of opcode conflicts with that of earlier instruction(s)"
+msgstr "la arquitectura del código de operación tiene conflictos con alguno de una(s) instrucción(es) anterior(es)"
+
+#: config/tc-i960.c:1425 config/tc-xtensa.c:11295
+msgid "too many operands"
+msgstr "demasiados operandos"
+
+#. We never moved: there was no opcode either!
+#: config/tc-i960.c:1473
+msgid "missing opcode"
+msgstr "falta el código de operación"
+
+#: config/tc-i960.c:1613
 msgid "branch prediction invalid on this opcode"
 msgstr "predicción de ramificación inválida en este código de operación"
 
-#: config/tc-i960.c:648
+#: config/tc-i960.c:1651
 #, c-format
 msgid "invalid opcode, \"%s\"."
 msgstr "código de operación inválido, \"%s\"."
 
-#: config/tc-i960.c:653
+#: config/tc-i960.c:1653
 #, c-format
 msgid "improper number of operands.  expecting %d, got %d"
 msgstr "número impropio de operandos.  se esperaban %d, se obtuvieron %d"
 
-#: config/tc-i960.c:877
+#: config/tc-i960.c:1810
 #, c-format
 msgid "Fixup of %ld too large for field width of %d"
 msgstr "La compostura de %ld es demasiado grande para el campo de anchura %d"
 
-#: config/tc-i960.c:994
+#: config/tc-i960.c:1920
 #, c-format
 msgid "invalid architecture %s"
 msgstr "arquitectura %s inválida"
 
-#: config/tc-i960.c:1014
+#: config/tc-i960.c:1940
+#, c-format
 msgid "I960 options:\n"
 msgstr "opciones de I960:\n"
 
-#: config/tc-i960.c:1017
+#: config/tc-i960.c:1943
+#, c-format
 msgid ""
 "\n"
 "\t\t\tspecify variant of 960 architecture\n"
@@ -4783,206 +5258,153 @@ msgstr ""
 "-no-relax\t\tno alterar las instrucciones comparar-y-ramificar para\n"
 "\t\t\tdesubicaciones largas\n"
 
-#: config/tc-i960.c:1419 config/tc-xtensa.c:8604
-msgid "too many operands"
-msgstr "demasiados operandos"
-
-#: config/tc-i960.c:1477 config/tc-i960.c:1702
-msgid "expression syntax error"
-msgstr "error sintáctico en la expresión"
-
-#: config/tc-i960.c:1515
-msgid "attempt to branch into different segment"
-msgstr "se intentó ramificar en un segmento diferente"
-
-#: config/tc-i960.c:1519
-#, c-format
-msgid "target of %s instruction must be a label"
-msgstr "el objetivo de la instrucción %s debe ser una etiqueta"
-
-#: config/tc-i960.c:1557
-msgid "unmatched '['"
-msgstr "'[' desemparejado"
-
-#: config/tc-i960.c:1568
-msgid "garbage after index spec ignored"
-msgstr "se ignora la basura después de la especificación del índice"
-
-#. We never moved: there was no opcode either!
-#: config/tc-i960.c:1633
-msgid "missing opcode"
-msgstr "falta el código de operación"
-
-#: config/tc-i960.c:2046
-msgid "invalid index register"
-msgstr "registro índice inválido"
-
-#: config/tc-i960.c:2069
-msgid "invalid scale factor"
-msgstr "factor de escala inválido"
-
-#: config/tc-i960.c:2250
-msgid "unaligned register"
-msgstr "registro sin alinear"
-
-#: config/tc-i960.c:2273
-msgid "no such sfr in this architecture"
-msgstr "no hay un sfr en esta arquitectura"
-
-#: config/tc-i960.c:2311
-msgid "illegal literal"
-msgstr "literal ilegal"
-
-#. Should not happen: see block comment above
-#: config/tc-i960.c:2539
-#, c-format
-msgid "Trying to 'bal' to %s"
-msgstr "Tratando de hacer 'bal' a %s"
-
-#: config/tc-i960.c:2550
-msgid "Looks like a proc, but can't tell what kind.\n"
-msgstr "Se ve como un proc, no se puede saber de qué tipo.\n"
-
-#: config/tc-i960.c:2582
+#: config/tc-i960.c:2207
 msgid "should have 1 or 2 operands"
 msgstr "debe tener 1 o 2 operandos"
 
-#: config/tc-i960.c:2591 config/tc-i960.c:2610
+#: config/tc-i960.c:2215 config/tc-i960.c:2230
 #, c-format
 msgid "Redefining leafproc %s"
 msgstr "Redefiniendo el proceso hoja %s"
 
-#: config/tc-i960.c:2641
+#: config/tc-i960.c:2260
 msgid "should have two operands"
 msgstr "debe tener dos operandos"
 
-#: config/tc-i960.c:2651
+#: config/tc-i960.c:2270
 msgid "'entry_num' must be absolute number in [0,31]"
 msgstr "'entry_num' debe ser un número absoluto en [0,31]"
 
-#: config/tc-i960.c:2660
+#: config/tc-i960.c:2278
 #, c-format
 msgid "Redefining entrynum for sysproc %s"
 msgstr "Redefiniendo el número de entrada para el proceso del sistema %s"
 
-#: config/tc-i960.c:2764
-msgid "architecture of opcode conflicts with that of earlier instruction(s)"
-msgstr "la arquitectura del código de operación tiene conflictos con alguno de una(s) instrucción(es) anterior(es)"
+#. Should not happen: see block comment above.
+#: config/tc-i960.c:2378
+#, c-format
+msgid "Trying to 'bal' to %s"
+msgstr "Tratando de hacer 'bal' a %s"
 
-#: config/tc-i960.c:2785
+#: config/tc-i960.c:2388
+msgid "Looks like a proc, but can't tell what kind.\n"
+msgstr "Se ve como un proc, no se puede saber de qué tipo.\n"
+
+#: config/tc-i960.c:2407
 msgid "big endian mode is not supported"
 msgstr "el modo big endian no tiene soporte"
 
-#: config/tc-i960.c:2787
+#: config/tc-i960.c:2409
 #, c-format
 msgid "ignoring unrecognized .endian type `%s'"
 msgstr "se ignora el tipo .endian `%s' no reconocido"
 
-#: config/tc-i960.c:3071
-#, c-format
-msgid "leafproc symbol '%s' undefined"
-msgstr "símolo de proceso hoja '%s' indefinido"
-
-#: config/tc-i960.c:3081
-#, c-format
-msgid "Warning: making leafproc entries %s and %s both global\n"
-msgstr "Aviso: haciendo globales las entradas de proceso hoja %s y %s\n"
+#: config/tc-i960.c:2454
+msgid "can't use COBR format with external label"
+msgstr "no se puede utilizar el formato COBR con una etiqueta externa"
 
-#: config/tc-i960.c:3190
+#: config/tc-i960.c:2629
 msgid "option --link-relax is only supported in b.out format"
 msgstr "la opción --link-relax solamente tiene soporte en el formato b.out"
 
-#: config/tc-ia64.c:982
+#: config/tc-i960.c:2656
+#, c-format
+msgid "No 'bal' entry point for leafproc %s"
+msgstr "No hay un punto de entrada 'bal' para el proceso hoja %s"
+
+#: config/tc-ia64.c:1008
 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string"
 msgstr "Directiva .section errónea: se quiere a,o,s,w,x,M,S,G,T en la cadena"
 
-#: config/tc-ia64.c:1105
+#: config/tc-ia64.c:1151
 msgid "Unwind directive not followed by an instruction."
 msgstr "La directiva de desenredo no está seguida por una instrucción."
 
-#: config/tc-ia64.c:4563
+#: config/tc-ia64.c:5114
 msgid "Register name expected"
 msgstr "Se esperaba un nombre de registro"
 
-#: config/tc-ia64.c:4568 config/tc-ia64.c:4854
+#: config/tc-ia64.c:5119 config/tc-ia64.c:5435
 msgid "Comma expected"
 msgstr "Se esperaba una coma"
 
-#: config/tc-ia64.c:4576
+#: config/tc-ia64.c:5127
 msgid "Register value annotation ignored"
 msgstr "Se ignora la anotación del valor del registro"
 
-#: config/tc-ia64.c:4600
+#: config/tc-ia64.c:5168
 msgid "Directive invalid within a bundle"
 msgstr "Directiva inválida dentro de una agrupación"
 
-#: config/tc-ia64.c:4667
+#: config/tc-ia64.c:5261
 msgid "Missing predicate relation type"
 msgstr "Falta el tipo de relación del predicado"
 
-#: config/tc-ia64.c:4683
+#: config/tc-ia64.c:5267
 msgid "Unrecognized predicate relation type"
 msgstr "Tipo de relación de predicado no reconocido"
 
-#: config/tc-ia64.c:4703 config/tc-ia64.c:4728
+#: config/tc-ia64.c:5314
+msgid "Bad register range"
+msgstr "Rango de registro erróneo"
+
+#: config/tc-ia64.c:5323
 msgid "Predicate register expected"
 msgstr "Se esperaba un registro de predicado"
 
-#: config/tc-ia64.c:4715
+#: config/tc-ia64.c:5328
 msgid "Duplicate predicate register ignored"
 msgstr "Se ignora el registro de predicado duplicado"
 
-#: config/tc-ia64.c:4737
-msgid "Bad register range"
-msgstr "Rango de registro erróneo"
-
-#: config/tc-ia64.c:4765
+#: config/tc-ia64.c:5346
 msgid "Predicate source and target required"
 msgstr "Se requiere el predicado fuente y destino"
 
-#: config/tc-ia64.c:4767 config/tc-ia64.c:4779
+#: config/tc-ia64.c:5348 config/tc-ia64.c:5360
 msgid "Use of p0 is not valid in this context"
 msgstr "El uso de p0 no es válido en este contexto"
 
-#: config/tc-ia64.c:4774
+#: config/tc-ia64.c:5355
 msgid "At least two PR arguments expected"
 msgstr "Se esperaban al menos dos argumentos PR"
 
-#: config/tc-ia64.c:4788
+#: config/tc-ia64.c:5369
 msgid "At least one PR argument expected"
 msgstr "Se esperaba al menos un argumento PR"
 
-#: config/tc-ia64.c:4824
+#: config/tc-ia64.c:5405
 #, c-format
 msgid "Inserting \"%s\" into entry hint table failed: %s"
 msgstr "Falló la inserción de \"%s\" en la tabla de entrada de pistas: %s"
 
 #. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:5302
+#: config/tc-ia64.c:5881
 msgid "62-bit relocation not yet implemented"
 msgstr "la reubicación de 62-bits aún no está implementada"
 
 #. XXX technically, this is wrong: we should not be issuing warning
 #. messages until we're sure this instruction pattern is going to
 #. be used!
-#: config/tc-ia64.c:5375
+#: config/tc-ia64.c:5954
 msgid "lower 16 bits of mask ignored"
 msgstr "se ignoran los 16 bits inferiores de la máscara"
 
-#: config/tc-ia64.c:5939
+#: config/tc-ia64.c:6569
 msgid "Value truncated to 62 bits"
 msgstr "Valor truncado a 62 bits"
 
-#: config/tc-ia64.c:6291
-msgid "Additional NOP may be necessary to workaround Itanium processor A/B step errata"
-msgstr "Pueden ser necesario un NOP adicional para evitar el error de paso A/B del procesador Itanium"
+#. Give an error if a frag containing code is not aligned to a 16 byte
+#. boundary.
+#: config/tc-ia64.c:6707 config/tc-ia64.h:171
+msgid "instruction address is not a multiple of 16"
+msgstr "la dirección de la instrucción no es un múltiplo de 16"
 
-#: config/tc-ia64.c:6474
+#: config/tc-ia64.c:7249
 #, c-format
 msgid "Unrecognized option '-x%s'"
 msgstr "Opción '-x%s' no reconocida"
 
-#: config/tc-ia64.c:6502
+#: config/tc-ia64.c:7277
 msgid ""
 "IA-64 options:\n"
 "  --mconstant-gp\t  mark output file as using the constant-GP model\n"
@@ -4992,9 +5414,20 @@ msgid ""
 "\t\t\t  EF_IA_64_NOFUNCDESC_CONS_GP)\n"
 "  -milp32|-milp64|-mlp64|-mp64\tselect data model (default -mlp64)\n"
 "  -mle | -mbe\t\t  select little- or big-endian byte order (default -mle)\n"
-"  -x | -xexplicit\t  turn on dependency violation checking (default)\n"
-"  -xauto\t\t  automagically remove dependency violations\n"
+"  -mtune=[itanium1|itanium2]\n"
+"\t\t\t  tune for a specific CPU (default -mtune=itanium2)\n"
+"  -munwind-check=[warning|error]\n"
+"\t\t\t  unwind directive check (default -munwind-check=warning)\n"
+"  -mhint.b=[ok|warning|error]\n"
+"\t\t\t  hint.b check (default -mhint.b=error)\n"
+"  -x | -xexplicit\t  turn on dependency violation checking\n"
+"  -xauto\t\t  automagically remove dependency violations (default)\n"
+"  -xnone\t\t  turn off dependency violation checking\n"
 "  -xdebug\t\t  debug dependency violation checker\n"
+"  -xdebugn\t\t  debug dependency violation checker but turn off\n"
+"\t\t\t  dependency violation checking\n"
+"  -xdebugx\t\t  debug dependency violation checker and turn on\n"
+"\t\t\t  dependency violation checking\n"
 msgstr ""
 "Opciones de IA-64:\n"
 "  --mconstant-gp\t  marca el fichero de salida como que usa el modelo\n"
@@ -5005,256 +5438,376 @@ msgstr ""
 "\t\t\t  (establece la opción EF_IA_64_NOFUNCDESC_CONS_GP\n"
 "\t\t\t  del encabezado ELF)\n"
 "  -milp32|-milp64|-mlp64|-mp64\tselecciona el modelo de datos\n"
-"                              \t(-mlp64 por omisión)\n"
+"                              \t(-mlp64 por defecto)\n"
 "  -mle | -mbe\t\t  selecciona el orden de bytes little- o big-endian\n"
-"             \t\t  (-mle por omisión)\n"
+"             \t\t  (-mle por defecto)\n"
+"  -mtune=[itanium1|itanium2]\n"
+"\t\t\t  optimiza para un CPU específico\n"
+"\t\t\t  (por defecto -mtune=itanium2)\n"
+"  -munwind-check=[warning|error]\n"
+"\t\t\t  revisión de directiva de desenredo\n"
+"\t\t\t  (-munwind-check=warning por defecto)\n"
+"  -mhint.b=[ok|warning|error]\n"
+"\t\t\t  revisión de hint.b (-mhint.b=error por defecto)\n"
 "  -x | -xexplicit\t  activa la revisión de violaciones de dependencias\n"
-"                 \t  (por omisión)\n"
+"                 \t  (por defecto)\n"
 "  -xauto\t\t  borra automágicamente las violaciones de dependencias\n"
+"        \t\t  (por defecto)\n"
+"  -xnone\t\t  desactiva la revisión de violaciones de dependencias\n"
 "  -xdebug\t\t  depura el revisor de violaciones de dependencias\n"
+"  -xdebugn\t\t  depura el revisor de violaciones de dependencias pero\n"
+"\t\t\t  desactiva la revisión de violaciones de dependencias\n"
+"  -xdebugx\t\t  depura el revisor de violaciones de dependencias y\n"
+"\t\t\t  activa la revisión de violaciones de dependencias\n"
 
-#: config/tc-ia64.c:6521
+#: config/tc-ia64.c:7307
 msgid "--gstabs is not supported for ia64"
 msgstr "--gstabs no tiene soporte para ia64"
 
-#: config/tc-ia64.c:6824 config/tc-mips.c:1093
+#: config/tc-ia64.c:7641 config/tc-mips.c:1401
 msgid "Could not set architecture and machine"
 msgstr "No se pueden establecer la arquitectura y la máquina"
 
-#: config/tc-ia64.c:6931
+#: config/tc-ia64.c:7767
 msgid "Explicit stops are ignored in auto mode"
 msgstr "Se ignoran las paradas explícitas en modo automático"
 
-#: config/tc-ia64.c:6981
+#: config/tc-ia64.c:7789
 msgid "Found '{' after explicit switch to automatic mode"
 msgstr "Se encontró '{' después del cambio explícito al modo automático"
 
-#: config/tc-ia64.c:7428
+#: config/tc-ia64.c:8392
 #, c-format
 msgid "Unhandled dependency %s for %s (%s), note %d"
 msgstr "Dependencia sin manejar %s para %s (%s), nota %d"
 
-#: config/tc-ia64.c:8704
+#: config/tc-ia64.c:9667
 #, c-format
 msgid "Unrecognized dependency specifier %d\n"
 msgstr "Especificador de dependencia %d no reconocido\n"
 
-#: config/tc-ia64.c:9506
+#: config/tc-ia64.c:10561
 msgid "Only the first path encountering the conflict is reported"
 msgstr "Solamente se reporta la primera ruta donde se encuentra el conflicto"
 
-#: config/tc-ia64.c:9509
+#: config/tc-ia64.c:10564
 msgid "This is the location of the conflicting usage"
 msgstr "Esta es la ubicación del uso conflictivo"
 
-#: config/tc-ia64.c:10778 read.c:1370 read.c:1976 read.c:2184 read.c:2795
+#: config/tc-ia64.c:11788
+msgid "Can't add stop bit to mark end of instruction group"
+msgstr "No se puede agregar el bit de parada para marcar el fin del grupo de instrucciones"
+
+#: config/tc-ia64.c:11888 read.c:1440 read.c:2206 read.c:2846 read.c:3173
+#: read.c:3204
 msgid "expected symbol name"
 msgstr "se esperaba un nombre de símbolo"
 
-#: config/tc-ia64.c:10788 read.c:1380 read.c:2194 read.c:2805 stabs.c:478
+#: config/tc-ia64.c:11898 read.c:2216 read.c:2856 read.c:3188 stabs.c:466
 #, c-format
 msgid "expected comma after \"%s\""
 msgstr "se esperaba una coma después de \"%s\""
 
-#: config/tc-ia64.c:10829
+#: config/tc-ia64.c:11940
 #, c-format
 msgid "`%s' is already the alias of %s `%s'"
 msgstr "el símbolo `%s' ya es el alias de %s `%s'"
 
-#: config/tc-ia64.c:10839
+#: config/tc-ia64.c:11950
 #, c-format
 msgid "%s `%s' already has an alias `%s'"
 msgstr "%s `%s' ya tiene un alias `%s'"
 
-#: config/tc-ia64.c:10850
+#: config/tc-ia64.c:11961
 #, c-format
 msgid "inserting \"%s\" into %s alias hash table failed: %s"
 msgstr "falló la inserción de \"%s\" en la tabla de dispersión de alias %s: %s"
 
-#: config/tc-ia64.c:10858
+#: config/tc-ia64.c:11969
 #, c-format
 msgid "inserting \"%s\" into %s name hash table failed: %s"
 msgstr "falló la inserción de \"%s\" en la tabla de dispersión de nombres %s: %s"
 
-#: config/tc-ia64.c:10877
+#: config/tc-ia64.c:11988
 #, c-format
 msgid "symbol `%s' aliased to `%s' is not used"
 msgstr "el símbolo `%s' que es alias de `%s' no se utiliza"
 
-#: config/tc-ia64.c:10899
+#: config/tc-ia64.c:12010
 #, c-format
 msgid "section `%s' aliased to `%s' is not used"
 msgstr "la sección `%s' que es alias de `%s' no se utiliza"
 
-#: config/tc-ip2k.c:125
+#: config/tc-ip2k.c:158
+#, c-format
 msgid "IP2K specific command line options:\n"
 msgstr "Opciones de la línea de comandos específicas de IP2K:\n"
 
-#: config/tc-ip2k.c:126
+#: config/tc-ip2k.c:159
+#, c-format
 msgid "  -mip2022               restrict to IP2022 insns \n"
 msgstr "  -mip2022               restringe a insns de IP2022 \n"
 
-#: config/tc-ip2k.c:127
+#: config/tc-ip2k.c:160
+#, c-format
 msgid "  -mip2022ext            permit extended IP2022 insn\n"
 msgstr "  -mip2022ext            permite insns extendidas de IP2022\n"
 
-#: config/tc-ip2k.c:248
+#: config/tc-ip2k.c:274
 msgid "md_pcrel_from\n"
 msgstr "md_pcrel_from\n"
 
+#: config/tc-m32c.c:128
+#, c-format
+msgid " M32C specific command line options:\n"
+msgstr "Opciones de la línea de comandos específicas de M32C:\n"
+
 #. Pretend that we do not recognise this option.
-#: config/tc-m32r.c:233
+#: config/tc-m32r.c:332
 msgid "Unrecognised option: -hidden"
 msgstr "Opción no reconocida: -hidden"
 
-#: config/tc-m32r.c:267
+#: config/tc-m32r.c:359 config/tc-sparc.c:593
+msgid "Unrecognized option following -K"
+msgstr "Opción no reconocida a continuación de -K"
+
+#: config/tc-m32r.c:374
+#, c-format
 msgid " M32R specific command line options:\n"
 msgstr "Opciones de la línea de comandos específicas de M32R:\n"
 
-#: config/tc-m32r.c:269
+#: config/tc-m32r.c:376
+#, c-format
 msgid "  -m32r                   disable support for the m32rx instruction set\n"
 msgstr "  -m32r                   desactiva el soporte para el conjunto de instrucciones m32rx\n"
 
-#: config/tc-m32r.c:271
+#: config/tc-m32r.c:378
+#, c-format
 msgid "  -m32rx                  support the extended m32rx instruction set\n"
 msgstr "  -m32rx                  da soporte al conjunto extendido de instrucciones m32rx\n"
 
-#: config/tc-m32r.c:273
-msgid "  -O                      try to combine instructions in parallel\n"
-msgstr "  -O                      intenta combinar instrucciones en paralelo\n"
+#: config/tc-m32r.c:380
+#, c-format
+msgid "  -m32r2                  support the extended m32r2 instruction set\n"
+msgstr "  -m32r2                  da soporte al conjunto extendido de instrucciones m32r2\n"
+
+#: config/tc-m32r.c:382
+#, c-format
+msgid "  -EL,-little             produce little endian code and data\n"
+msgstr "  -EL,-little             produce código y datos little endian\n"
+
+#: config/tc-m32r.c:384
+#, c-format
+msgid "  -EB,-big                produce big endian code and data\n"
+msgstr "  -EB,-big                produce código y datos big endian\n"
+
+#: config/tc-m32r.c:386
+#, c-format
+msgid "  -parallel               try to combine instructions in parallel\n"
+msgstr "  -parallel               intenta combinar instrucciones en paralelo\n"
+
+#: config/tc-m32r.c:388
+#, c-format
+msgid "  -no-parallel            disable -parallel\n"
+msgstr "  -no-parallel            desactiva -parallel.\n"
+
+#: config/tc-m32r.c:390
+#, c-format
+msgid "  -no-bitinst             disallow the M32R2's extended bit-field instructions\n"
+msgstr "  -no-bitinst             desactiva las instrucciones extendidas de campos de bit de M32R2\n"
+
+#: config/tc-m32r.c:392
+#, c-format
+msgid "  -O                      try to optimize code.  Implies -parallel\n"
+msgstr "  -O                      intenta optimizar código.  Implica -parallel\n"
 
-#: config/tc-m32r.c:276
+#: config/tc-m32r.c:395
+#, c-format
 msgid "  -warn-explicit-parallel-conflicts     warn when parallel instructions\n"
 msgstr "  -warn-explicit-parallel-conflicts     avisa cuando hay instrucciones paralelas\n"
 
-#: config/tc-m32r.c:278
-msgid "                                         violate contraints\n"
-msgstr "                                         que violan las restricciones\n"
+#: config/tc-m32r.c:397
+#, c-format
+msgid "                                         might violate contraints\n"
+msgstr "                                         que pueden violar las restricciones\n"
 
-#: config/tc-m32r.c:280
+#: config/tc-m32r.c:399
+#, c-format
 msgid "  -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"
 msgstr "  -no-warn-explicit-parallel-conflicts  no avisa cuando las instrucciones\n"
 
-#: config/tc-m32r.c:282
-msgid "                                         instructions violate contraints\n"
-msgstr "                                         paralelas violan restricciones\n"
+#: config/tc-m32r.c:401
+#, c-format
+msgid "                                         instructions might violate contraints\n"
+msgstr "                                         paralelas pueden violar restricciones\n"
 
-#: config/tc-m32r.c:284
+#: config/tc-m32r.c:403
+#, c-format
 msgid "  -Wp                     synonym for -warn-explicit-parallel-conflicts\n"
 msgstr "  -Wp                     sinónimo para -warn-explicit-parallel-conflicts\n"
 
-#: config/tc-m32r.c:286
+#: config/tc-m32r.c:405
+#, c-format
 msgid "  -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"
 msgstr "  -Wnp                    sinónimo para -no-warn-explicit-parallel-conflicts\n"
 
-#: config/tc-m32r.c:289
+#: config/tc-m32r.c:407
+#, c-format
+msgid "  -ignore-parallel-conflicts            do not check parallel instructions\n"
+msgstr "  -ignore-parallel-conflicts            no revisar cuando hay instrucciones paralelas\n"
+
+#: config/tc-m32r.c:409
+#, c-format
+msgid "                                         fo contraint violations\n"
+msgstr "                                         que violan las restricciones\n"
+
+#: config/tc-m32r.c:411
+#, c-format
+msgid "  -no-ignore-parallel-conflicts         check parallel instructions for\n"
+msgstr "  -no-ignore-parallel-conflicts         revisar cuando hay instrucciones paralelas\n"
+
+#: config/tc-m32r.c:413
+#, c-format
+msgid "                                         contraint violations\n"
+msgstr "                                         que violan las restricciones\n"
+
+#: config/tc-m32r.c:415
+#, c-format
+msgid "  -Ip                     synonym for -ignore-parallel-conflicts\n"
+msgstr "  -Ip                     sinónimo para -ignore-parallel-conflicts\n"
+
+#: config/tc-m32r.c:417
+#, c-format
+msgid "  -nIp                    synonym for -no-ignore-parallel-conflicts\n"
+msgstr "  -nIp                    sinónimo para -no-ignore-parallel-conflicts\n"
+
+#: config/tc-m32r.c:420
+#, c-format
 msgid "  -warn-unmatched-high    warn when an (s)high reloc has no matching low reloc\n"
 msgstr "  -warn-unmatched-high    avisa cundo una reubicación (s)high no tiene una reubicación low correspondiente\n"
 
-#: config/tc-m32r.c:291
+#: config/tc-m32r.c:422
+#, c-format
 msgid "  -no-warn-unmatched-high do not warn about missing low relocs\n"
 msgstr "  -no-warn-unmatched-high no avisa cuando faltan reubicaciones low\n"
 
-#: config/tc-m32r.c:293
+#: config/tc-m32r.c:424
+#, c-format
 msgid "  -Wuh                    synonym for -warn-unmatched-high\n"
 msgstr "  -Wuh                    sinónimo para -warn-unmatched-high\n"
 
-#: config/tc-m32r.c:295
+#: config/tc-m32r.c:426
+#, c-format
 msgid "  -Wnuh                   synonym for -no-warn-unmatched-high\n"
 msgstr "  -Wnuh                   sinónimo para -no-warn-unmatched-high\n"
 
-#: config/tc-m32r.c:299
-msgid "  -relax                 create linker relaxable code\n"
-msgstr "  -relax                 crea código relajable para el enlazados\n"
-
-#: config/tc-m32r.c:301
-msgid "  -cpu-desc              provide runtime cpu description file\n"
-msgstr "  -cpu-desc              provee el fichero de descripción del cpu en tiempo de ejecución\n"
+#: config/tc-m32r.c:429
+#, c-format
+msgid "  -KPIC                   generate PIC\n"
+msgstr "  -KPIC                   genera PIC\n"
 
-#: config/tc-m32r.c:700
-msgid "Instructions write to the same destination register."
-msgstr "Las instrucciones escriben al mismo registro de destino."
+#: config/tc-m32r.c:850
+msgid "instructions write to the same destination register."
+msgstr "las instrucciones escriben al mismo registro de destino."
 
-#: config/tc-m32r.c:708
+#: config/tc-m32r.c:858
 msgid "Instructions do not use parallel execution pipelines."
 msgstr "Las instrucciones no usan tuberías de ejecución paralela."
 
-#: config/tc-m32r.c:715
+#: config/tc-m32r.c:866
 msgid "Instructions share the same execution pipeline"
 msgstr "Las instrucciones comparten la misma tubería de ejecución"
 
-#: config/tc-m32r.c:791 config/tc-m32r.c:887
+#: config/tc-m32r.c:931 config/tc-m32r.c:1045
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr "no hay una instrucción 16 bit '%s'"
 
-#: config/tc-m32r.c:798 config/tc-m32r.c:894 config/tc-m32r.c:1050
+#: config/tc-m32r.c:943 config/tc-m32r.c:1057 config/tc-m32r.c:1241
+#, c-format
+msgid "instruction '%s' is for the M32R2 only"
+msgstr "la instrucción '%s' sólo es para el M32R2"
+
+#: config/tc-m32r.c:956 config/tc-m32r.c:1070 config/tc-m32r.c:1254
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr "instrucción '%s' desconocida"
 
-#: config/tc-m32r.c:807 config/tc-m32r.c:901 config/tc-m32r.c:1057
+#: config/tc-m32r.c:965 config/tc-m32r.c:1077 config/tc-m32r.c:1261
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr "la instrucción '%s' sólo es para el M32RX"
 
-#: config/tc-m32r.c:816 config/tc-m32r.c:910
+#: config/tc-m32r.c:974 config/tc-m32r.c:1086
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr "la instrucción '%s' no se puede ejecutar en paralelo."
 
-#: config/tc-m32r.c:871 config/tc-m32r.c:935 config/tc-m32r.c:1107
+#: config/tc-m32r.c:1029 config/tc-m32r.c:1111 config/tc-m32r.c:1318
 msgid "internal error: lookup/get operands failed"
 msgstr "error interno: los operandos lookup/get fallaron."
 
-#: config/tc-m32r.c:920
+#: config/tc-m32r.c:1096
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr "'%s': solamente las instrucciones NOP se puede ejecutar en paralelo en el m32r"
 
-#: config/tc-m32r.c:949
+#: config/tc-m32r.c:1125
 #, c-format
 msgid "%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"
 msgstr "%s: la salida de la 1a instrucción es la misma que una entrada a la 2a instrucción - ¿Esto es intencional?"
 
-#: config/tc-m32r.c:953
+#: config/tc-m32r.c:1129
 #, c-format
 msgid "%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"
 msgstr "%s: la salida de la 2a instrucción es la misma que una entrada a la 1a instrucción - ¿Esto es intencional?"
 
-#: config/tc-m32r.c:1267 config/tc-ppc.c:1732 config/tc-ppc.c:4263
+#: config/tc-m32r.c:1493 config/tc-ppc.c:1773 config/tc-ppc.c:4365
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr "Se esperaba coma después del nombre del símbolo: se ingnora el resto de la línea."
 
-#: config/tc-m32r.c:1277
+#: config/tc-m32r.c:1503
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr "longitud SCOMMon (%ld.) <0!. Se ignora."
 
-#: config/tc-m32r.c:1291 config/tc-ppc.c:1754 config/tc-ppc.c:2899
-#: config/tc-ppc.c:4287
+#: config/tc-m32r.c:1517 config/tc-ppc.c:1795 config/tc-ppc.c:2952
+#: config/tc-ppc.c:4389
 msgid "ignoring bad alignment"
 msgstr "se ignora la alineación errónea"
 
-#: config/tc-m32r.c:1303 config/tc-ppc.c:1791 config/tc-v850.c:335
+#: config/tc-m32r.c:1529 config/tc-ppc.c:1832 config/tc-v850.c:323
 msgid "Common alignment not a power of 2"
 msgstr "La alineación común no es una potencia de 2"
 
-#: config/tc-m32r.c:1318 config/tc-ppc.c:1765 config/tc-ppc.c:4299
+#: config/tc-m32r.c:1544 config/tc-ppc.c:1806 config/tc-ppc.c:4401
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr "Se ignora el intento de redefinir el símbolo `%s'."
 
-#: config/tc-m32r.c:1327
+#: config/tc-m32r.c:1553
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr "La longitud de .scomm \"%s\" ya está %ld. No ha cambiado a %ld."
 
-#: config/tc-m32r.c:1808
+#: config/tc-m32r.c:1789
+msgid "Addend to unresolved symbol not on word boundary."
+msgstr "La adición para un símbolo sin resolver no está en un límite de word."
+
+#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:749
+msgid "Invalid PIC expression."
+msgstr "Expresión PIC inválida."
+
+#: config/tc-m32r.c:2074
 msgid "Unmatched high/shigh reloc"
 msgstr "Reubicación high/shigh sin coincidencia"
 
-#: config/tc-m68hc11.c:372
+#: config/tc-m32r.c:2334 config/tc-sparc.c:3524
+#, c-format
+msgid "internal error: can't export reloc type %d (`%s')"
+msgstr "error interno: no se puede exportar el tipo de reubicación %d (`%s')"
+
+#: config/tc-m68hc11.c:369
 #, c-format
 msgid ""
 "Motorola 68HC11/68HC12/68HCS12 options:\n"
@@ -5276,11 +5829,11 @@ msgid ""
 msgstr ""
 "Opciones para Motorola 68HC11/68HC12/68HCS12:\n"
 "  -m68hc11 | -m68hc12 |\n"
-"  -m68hcs12               especifica el procesador [por omisión %s]\n"
-"  -mshort                 usa la ABI int de 16-bit (por omisión)\n"
+"  -m68hcs12               especifica el procesador [por defecto %s]\n"
+"  -mshort                 usa la ABI int de 16-bit (por defecto)\n"
 "  -mlong                  usa la ABI int de 32-bit\n"
 "  -mshort-double          usa la ABI double de 32-bit\n"
-"  -mlong-double           usa la ABI double de 64-bit (por omisión)\n"
+"  -mlong-double           usa la ABI double de 64-bit (por defecto)\n"
 "  --force-long-branchs    siempre convierte las ramificaciones relativas en\n"
 "                          absolutas\n"
 "  -S,--short-branchs      no convierte las ramificaciones relativas en\n"
@@ -5294,55 +5847,56 @@ msgstr ""
 "  --generate-example      genera un ejemplo de cada instrucción\n"
 "                          (utilizado para pruebas)\n"
 
-#: config/tc-m68hc11.c:418
+#: config/tc-m68hc11.c:415
 #, c-format
 msgid "Default target `%s' is not supported."
-msgstr "El objetivo por omisión `%s' no tiene soporte."
+msgstr "El objetivo por defecto `%s' no tiene soporte."
 
 #. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:437
+#: config/tc-m68hc11.c:433
+#, c-format
 msgid "Name   # Modes  Min ops  Max ops  Modes mask  # Used\n"
 msgstr "Nombre # Modos  Min ops  Max ops  Masc. modos # Usado\n"
 
-#: config/tc-m68hc11.c:505
+#: config/tc-m68hc11.c:499
 #, c-format
 msgid "Option `%s' is not recognized."
 msgstr "No se reconoce la opción `%s'."
 
-#: config/tc-m68hc11.c:737
+#: config/tc-m68hc11.c:721
 msgid "#<imm8>"
 msgstr "#<imm8>"
 
-#: config/tc-m68hc11.c:746
+#: config/tc-m68hc11.c:730
 msgid "#<imm16>"
 msgstr "#<imm16>"
 
-#: config/tc-m68hc11.c:755 config/tc-m68hc11.c:764
+#: config/tc-m68hc11.c:739 config/tc-m68hc11.c:748
 msgid "<imm8>,X"
 msgstr "<imm8>,X"
 
-#: config/tc-m68hc11.c:791
+#: config/tc-m68hc11.c:775
 msgid "*<abs8>"
 msgstr "*<abs8>"
 
-#: config/tc-m68hc11.c:803
+#: config/tc-m68hc11.c:787
 msgid "#<mask>"
 msgstr "#<máscara>"
 
-#: config/tc-m68hc11.c:813
+#: config/tc-m68hc11.c:797
 #, c-format
 msgid "symbol%d"
 msgstr "símbolo%d"
 
-#: config/tc-m68hc11.c:815
+#: config/tc-m68hc11.c:799
 msgid "<abs>"
 msgstr "<abs>"
 
-#: config/tc-m68hc11.c:834
+#: config/tc-m68hc11.c:818
 msgid "<label>"
 msgstr "<etiqueta>"
 
-#: config/tc-m68hc11.c:850
+#: config/tc-m68hc11.c:834
 #, c-format
 msgid ""
 "# Example of `%s' instructions\n"
@@ -5353,625 +5907,681 @@ msgstr ""
 "\t.sect .text\n"
 "_start:\n"
 
-#: config/tc-m68hc11.c:898
+#: config/tc-m68hc11.c:881
 #, c-format
 msgid "Instruction `%s' is not recognized."
 msgstr "No se reconoce la instrucción `%s'."
 
-#: config/tc-m68hc11.c:903
+#: config/tc-m68hc11.c:886
 #, c-format
 msgid "Instruction formats for `%s':"
 msgstr "Formatos de instrucción para `%s':"
 
-#: config/tc-m68hc11.c:1038
+#: config/tc-m68hc11.c:1016
 #, c-format
 msgid "Immediate operand is not allowed for operand %d."
 msgstr "No se permite un operando inmediato para el operando %d."
 
-#: config/tc-m68hc11.c:1082
+#: config/tc-m68hc11.c:1060
 msgid "Indirect indexed addressing is not valid for 68HC11."
 msgstr "El direccionamiento indizado indirecto no es válido para 68HC11."
 
-#: config/tc-m68hc11.c:1102
+#: config/tc-m68hc11.c:1080
 msgid "Spurious `,' or bad indirect register addressing mode."
 msgstr "`,' sobrante o modo de direccionamiento indirecto de registro erróneo."
 
-#: config/tc-m68hc11.c:1124
+#: config/tc-m68hc11.c:1102
 msgid "Missing second register or offset for indexed-indirect mode."
 msgstr "Falta el segundo registro o el desplazamiento para el modo indizado indirecto."
 
-#: config/tc-m68hc11.c:1134
+#: config/tc-m68hc11.c:1112
 msgid "Missing second register for indexed-indirect mode."
 msgstr "Falta el segundo registro para el modo indizado indirecto."
 
-#: config/tc-m68hc11.c:1150
+#: config/tc-m68hc11.c:1128
 msgid "Missing `]' to close indexed-indirect mode."
 msgstr "Falta un `]' para cerrar el modo indizado directo."
 
-#: config/tc-m68hc11.c:1195
+#: config/tc-m68hc11.c:1173
 msgid "Illegal operand."
 msgstr "Operando ilegal."
 
-#: config/tc-m68hc11.c:1200
+#: config/tc-m68hc11.c:1178
 msgid "Missing operand."
 msgstr "Falta un operando."
 
-#: config/tc-m68hc11.c:1253
+#: config/tc-m68hc11.c:1231
 msgid "Pre-increment mode is not valid for 68HC11"
 msgstr "El modo de pre-incremento no es válido para 68HC11"
 
-#: config/tc-m68hc11.c:1266
+#: config/tc-m68hc11.c:1244
 msgid "Wrong register in register indirect mode."
 msgstr "Registro erróneo en el modo indirecto de registro."
 
-#: config/tc-m68hc11.c:1274
+#: config/tc-m68hc11.c:1252
 msgid "Missing `]' to close register indirect operand."
 msgstr "Falta un `]' para cerrar el operando indirecto de registro."
 
-#: config/tc-m68hc11.c:1294
+#: config/tc-m68hc11.c:1272
 msgid "Post-decrement mode is not valid for 68HC11."
 msgstr "El modo de post-decremento no es válido para 68HC11."
 
-#: config/tc-m68hc11.c:1302
+#: config/tc-m68hc11.c:1280
 msgid "Post-increment mode is not valid for 68HC11."
 msgstr "El modo de post-incremento no es válido para 68HC11."
 
-#: config/tc-m68hc11.c:1320
+#: config/tc-m68hc11.c:1298
 msgid "Invalid indexed indirect mode."
 msgstr "Modo indizado indirecto inválido."
 
-#: config/tc-m68hc11.c:1417
+#: config/tc-m68hc11.c:1390
 #, c-format
 msgid "Trap id `%ld' is out of range."
 msgstr "El id de trampa `%ld' está fuera de rango."
 
-#: config/tc-m68hc11.c:1421
+#: config/tc-m68hc11.c:1394
 msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
 msgstr "El id de trampa debe estar dentro de [0x30..0x39] o [0x40..0xff]"
 
-#: config/tc-m68hc11.c:1428
+#: config/tc-m68hc11.c:1401
 #, c-format
 msgid "Operand out of 8-bit range: `%ld'."
 msgstr "Operando fuera del rango de 8-bit: `%ld'."
 
-#: config/tc-m68hc11.c:1435
+#: config/tc-m68hc11.c:1408
 msgid "The trap id must be a constant."
 msgstr "El id de trampa debe ser una constante."
 
-#: config/tc-m68hc11.c:1470
+#: config/tc-m68hc11.c:1443
 #, c-format
 msgid "Operand `%x' not recognized in fixup8."
 msgstr "No se reconoce el operando `%x' en fixup8."
 
-#: config/tc-m68hc11.c:1490 config/tc-m68hc11.c:1542
+#: config/tc-m68hc11.c:1460 config/tc-m68hc11.c:1509
 #, c-format
 msgid "Operand out of 16-bit range: `%ld'."
 msgstr "Operando fuera del rango de 16-bit: `%ld'."
 
-#: config/tc-m68hc11.c:1522 config/tc-m68hc11.c:1558
+#: config/tc-m68hc11.c:1492 config/tc-m68hc11.c:1525
 #, c-format
 msgid "Operand `%x' not recognized in fixup16."
 msgstr "No se reconoce el operando `%x' en fixup16."
 
-#: config/tc-m68hc11.c:1576
+#: config/tc-m68hc11.c:1542
 #, c-format
 msgid "Unexpected branch conversion with `%x'"
 msgstr "Conversión de ramificación inesperada con `%x'"
 
-#: config/tc-m68hc11.c:1671 config/tc-m68hc11.c:1812
+#: config/tc-m68hc11.c:1633 config/tc-m68hc11.c:1771
 #, c-format
 msgid "Operand out of range for a relative branch: `%ld'"
 msgstr "Operando fuera de rango para una ramificación relativa: `%ld'"
 
-#: config/tc-m68hc11.c:1780
+#: config/tc-m68hc11.c:1739
 msgid "Invalid register for dbcc/tbcc instruction."
 msgstr "Registro inválido para la instrucción dbcc/tbcc."
 
-#: config/tc-m68hc11.c:1871
+#: config/tc-m68hc11.c:1827
 #, c-format
 msgid "Increment/decrement value is out of range: `%ld'."
 msgstr "El valor de incremento/decremento está fuera de rango: `%ld'."
 
-#: config/tc-m68hc11.c:1882
+#: config/tc-m68hc11.c:1838
 msgid "Expecting a register."
 msgstr "Se espera un registro."
 
-#: config/tc-m68hc11.c:1897
+#: config/tc-m68hc11.c:1853
 msgid "Invalid register for post/pre increment."
 msgstr "Registro inválido para post/pre incremento."
 
-#: config/tc-m68hc11.c:1927
+#: config/tc-m68hc11.c:1883
 msgid "Invalid register."
 msgstr "Registro inválido."
 
-#: config/tc-m68hc11.c:1934
+#: config/tc-m68hc11.c:1890
 #, c-format
 msgid "Offset out of 16-bit range: %ld."
 msgstr "Desplazamiento fuera del rango de 16-bit: %ld."
 
-#: config/tc-m68hc11.c:1939
+#: config/tc-m68hc11.c:1895
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld."
 msgstr "Desplazamiento fuera del rango de 5-bit para la instrucción movw/movb: %ld."
 
-#: config/tc-m68hc11.c:2020
+#: config/tc-m68hc11.c:2001
 msgid "Expecting register D for indexed indirect mode."
 msgstr "Se esperaba el registro D para el modo indizado indirecto."
 
-#: config/tc-m68hc11.c:2022
+#: config/tc-m68hc11.c:2003
 msgid "Indexed indirect mode is not allowed for movb/movw."
 msgstr "No se permite el modo indizado directo para movb/movw."
 
-#: config/tc-m68hc11.c:2039
+#: config/tc-m68hc11.c:2020
 msgid "Invalid accumulator register."
 msgstr "Registro acumulador inválido."
 
-#: config/tc-m68hc11.c:2064
+#: config/tc-m68hc11.c:2045
 msgid "Invalid indexed register."
 msgstr "Registro indizado inválido."
 
-#: config/tc-m68hc11.c:2072
+#: config/tc-m68hc11.c:2053
 msgid "Addressing mode not implemented yet."
 msgstr "Modo de direccionamiento aún no implementado."
 
-#: config/tc-m68hc11.c:2087
+#: config/tc-m68hc11.c:2066
 msgid "Invalid source register for this instruction, use 'tfr'."
 msgstr "Registro fuente inválido para esta instrucción, utilice 'tfr'."
 
-#: config/tc-m68hc11.c:2089
+#: config/tc-m68hc11.c:2068
 msgid "Invalid source register."
 msgstr "Registro fuente inválido."
 
-#: config/tc-m68hc11.c:2094
+#: config/tc-m68hc11.c:2073
 msgid "Invalid destination register for this instruction, use 'tfr'."
 msgstr "Registro destino inválido para esta instrucción, utilice 'tfr'."
 
-#: config/tc-m68hc11.c:2096
+#: config/tc-m68hc11.c:2075
 msgid "Invalid destination register."
 msgstr "Registro destino inválido."
 
-#: config/tc-m68hc11.c:2194
+#: config/tc-m68hc11.c:2171
 msgid "Invalid indexed register, expecting register X."
 msgstr "Registro indizado inválido, se esperaba el registro X."
 
-#: config/tc-m68hc11.c:2196
+#: config/tc-m68hc11.c:2173
 msgid "Invalid indexed register, expecting register Y."
 msgstr "Registro indizado inválido, se esperaba el registro Y."
 
-#: config/tc-m68hc11.c:2508
+#: config/tc-m68hc11.c:2479
 msgid "No instruction or missing opcode."
 msgstr "No hay instrucción o falta el código de operación."
 
-#: config/tc-m68hc11.c:2573
+#: config/tc-m68hc11.c:2544
 #, c-format
 msgid "Opcode `%s' is not recognized."
 msgstr "No se reconoce el código de operación `%s'."
 
-#: config/tc-m68hc11.c:2595
+#: config/tc-m68hc11.c:2566
 #, c-format
 msgid "Garbage at end of instruction: `%s'."
 msgstr "Basura al final de la instrucción: `%s'."
 
-#: config/tc-m68hc11.c:2618
+#: config/tc-m68hc11.c:2589
 #, c-format
 msgid "Invalid operand for `%s'"
 msgstr "Operando inválido para `%s'"
 
-#: config/tc-m68hc11.c:2670
+#: config/tc-m68hc11.c:2640
 #, c-format
 msgid "Invalid mode: %s\n"
 msgstr "Modo inválido: %s\n"
 
-#: config/tc-m68hc11.c:2732
+#: config/tc-m68hc11.c:2700
 msgid "bad .relax format"
 msgstr "formato de .relax erróneo"
 
-#: config/tc-m68hc11.c:2779
+#: config/tc-m68hc11.c:2744
 #, c-format
 msgid "Relocation %d is not supported by object file format."
 msgstr "La reubicación %d no tiene soporte por el formato del fichero objeto."
 
-#: config/tc-m68hc11.c:3065
+#: config/tc-m68hc11.c:3023
 msgid "bra or bsr with undefined symbol."
 msgstr "bra o bsr con símbolo indefinido."
 
-#: config/tc-m68hc11.c:3168 config/tc-m68hc11.c:3225
+#: config/tc-m68hc11.c:3126 config/tc-m68hc11.c:3183
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr "No se reconoce el subtipo %d."
 
-#: config/tc-m68hc11.c:3289
+#: config/tc-m68hc11.c:3242
 msgid "Expression too complex."
 msgstr "Expresión demasiado compleja."
 
-#: config/tc-m68hc11.c:3322
+#: config/tc-m68hc11.c:3275
 msgid "Value out of 16-bit range."
 msgstr "Valor fuera del rango de 16-bit."
 
-#: config/tc-m68hc11.c:3346
+#: config/tc-m68hc11.c:3293
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr "El valor %ld es demasiado grande para la ramificación de 8-bit relativa al PC."
 
-#: config/tc-m68hc11.c:3353
+#: config/tc-m68hc11.c:3300
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr "El auto incremento/decremento del desplazamiento '%ld' está fuera de rango."
 
-#: config/tc-m68hc11.c:3371
+#: config/tc-m68hc11.c:3313
+#, c-format
+msgid "Offset out of 5-bit range for movw/movb insn: %ld"
+msgstr "Desplazamiento fuera del rango de 5-bit para la instrucción movw/movb: %ld"
+
+#: config/tc-m68hc11.c:3329
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr "Línea %d: tipo de reubicación desconocido: 0x%x."
 
-#: config/tc-m68k.c:678
-msgid "Unknown PC relative instruction"
-msgstr "Instrucción relativa al PC desconocida"
+#: config/tc-m68k.c:696
+msgid "no matching ColdFire architectures found"
+msgstr "no se encontraron arquitecturas ColdFire coincidentes"
+
+#: config/tc-m68k.c:710
+msgid " or "
+msgstr " o "
+
+#: config/tc-m68k.c:715
+msgid ", or "
+msgstr ", o "
 
-#: config/tc-m68k.c:817
+#: config/tc-m68k.c:732
+msgid ", or aliases"
+msgstr ", o los aliases"
+
+#: config/tc-m68k.c:843
 #, c-format
 msgid "Can not do %d byte pc-relative relocation"
 msgstr "No se puede hacer la reubicación relativa al pc de %d bytes"
 
-#: config/tc-m68k.c:819
+#: config/tc-m68k.c:845
 #, c-format
 msgid "Can not do %d byte pc-relative pic relocation"
 msgstr "No se puede hacer la reubicación pic relativa al pc de %d bytes"
 
-#: config/tc-m68k.c:824
+#: config/tc-m68k.c:850
 #, c-format
 msgid "Can not do %d byte relocation"
 msgstr "No se puede hacer la reubicación de %d byres"
 
-#: config/tc-m68k.c:826
+#: config/tc-m68k.c:852
 #, c-format
 msgid "Can not do %d byte pic relocation"
 msgstr "No se puede hacer la reubicación pic de %d bytes"
 
-#: config/tc-m68k.c:894
+#: config/tc-m68k.c:915
 #, c-format
 msgid "Unable to produce reloc against symbol '%s'"
 msgstr "No se puede producir una reubicación contra el símbolo '%s'"
 
-#: config/tc-m68k.c:938 config/tc-mips.c:13321 config/tc-vax.c:3441
+#: config/tc-m68k.c:959 config/tc-vax.c:3435
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr "No se puede hacer la reubicación relativa al PC %s"
 
-#: config/tc-m68k.c:1031 config/tc-tahoe.c:1495 config/tc-vax.c:1889
+#: config/tc-m68k.c:1050 config/tc-vax.c:1890
 msgid "No operator"
 msgstr "No hay operador"
 
-#: config/tc-m68k.c:1061 config/tc-tahoe.c:1512 config/tc-vax.c:1906
+#: config/tc-m68k.c:1080 config/tc-vax.c:1907
 msgid "Unknown operator"
 msgstr "Operador desconocido"
 
-#: config/tc-m68k.c:1836
+#: config/tc-m68k.c:1944
 msgid "invalid instruction for this architecture; needs "
 msgstr "instrucción inválida para esta arquitectura; necesita "
 
-#: config/tc-m68k.c:1841
+#: config/tc-m68k.c:1950
+msgid "ColdFire ISA_A"
+msgstr "ISA_A de ColdFire"
+
+#: config/tc-m68k.c:1958
+msgid "ColdFire hardware divide"
+msgstr "divide por hardware de ColdFire"
+
+#: config/tc-m68k.c:1966
+msgid "ColdFire ISA_A+"
+msgstr "ISA_A+ de ColdFire"
+
+#: config/tc-m68k.c:1974
+msgid "ColdFire ISA_B"
+msgstr "ISA_B de ColdFire"
+
+#: config/tc-m68k.c:1982
+msgid "ColdFire fpu"
+msgstr "unidad de coma flotante de ColdFire"
+
+#: config/tc-m68k.c:1989
 msgid "fpu (68040, 68060 or 68881/68882)"
 msgstr "fpu (68040, 68060 o 68881/68882)"
 
-#: config/tc-m68k.c:1844
+#: config/tc-m68k.c:1992
 msgid "mmu (68030 or 68851)"
 msgstr "mmu (68030 o 68851)"
 
-#: config/tc-m68k.c:1847
+#: config/tc-m68k.c:1995
 msgid "68020 or higher"
 msgstr "68020 o superior"
 
-#: config/tc-m68k.c:1850
+#: config/tc-m68k.c:1998
 msgid "68000 or higher"
 msgstr "68000 o superior"
 
-#: config/tc-m68k.c:1853
+#: config/tc-m68k.c:2001
 msgid "68010 or higher"
 msgstr "68010 o superior"
 
-#: config/tc-m68k.c:1882
+#: config/tc-m68k.c:2029
 msgid "operands mismatch"
 msgstr "no coinciden los operandos"
 
-#: config/tc-m68k.c:1939 config/tc-m68k.c:1945 config/tc-m68k.c:1951
-#: config/tc-mmix.c:2464 config/tc-mmix.c:2488
+#: config/tc-m68k.c:2090 config/tc-m68k.c:2096 config/tc-m68k.c:2102
+#: config/tc-mmix.c:2488 config/tc-mmix.c:2512
 msgid "operand out of range"
 msgstr "operando fuera de rango"
 
-#: config/tc-m68k.c:2008
+#: config/tc-m68k.c:2159
 #, c-format
 msgid "Bignum too big for %c format; truncated"
 msgstr "Número grande demasiado grande para el formato %c; truncado"
 
-#: config/tc-m68k.c:2076
+#: config/tc-m68k.c:2236
 msgid "displacement too large for this architecture; needs 68020 or higher"
 msgstr "desubicación demasiado grande para esta arquitectura; necesita 68020 o superior"
 
-#: config/tc-m68k.c:2186
+#: config/tc-m68k.c:2347
 msgid "scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
 msgstr "factor de escala inválido en esta arquitectura; necesita cpu32 o 68020 o superior"
 
-#: config/tc-m68k.c:2191
+#: config/tc-m68k.c:2352
 msgid "invalid index size for coldfire"
 msgstr "tamaño de índice inválido para coldfire"
 
-#: config/tc-m68k.c:2244
+#: config/tc-m68k.c:2405
 msgid "Forcing byte displacement"
 msgstr "Forzando la desubicación de byte"
 
-#: config/tc-m68k.c:2246
+#: config/tc-m68k.c:2407
 msgid "byte displacement out of range"
 msgstr "Desubicación de byte fuera de rango"
 
-#: config/tc-m68k.c:2293 config/tc-m68k.c:2331
+#: config/tc-m68k.c:2455 config/tc-m68k.c:2493
 msgid "invalid operand mode for this architecture; needs 68020 or higher"
 msgstr "modo de operando inválido para esta arquitectura; necesita 68020 o superior"
 
-#: config/tc-m68k.c:2317 config/tc-m68k.c:2351
+#: config/tc-m68k.c:2479 config/tc-m68k.c:2513
 msgid ":b not permitted; defaulting to :w"
-msgstr "no se permite :b; cambiando por omisión a :w"
+msgstr "no se permite :b; cambiando por defecto a :w"
 
-#: config/tc-m68k.c:2428
+#: config/tc-m68k.c:2590
 msgid "unsupported byte value; use a different suffix"
 msgstr "valor de byte sin soporte; utilice un sufijo diferente"
 
-#: config/tc-m68k.c:2442
+#: config/tc-m68k.c:2605
 msgid "unknown/incorrect operand"
 msgstr "operando desconocido/incorrecto"
 
-#: config/tc-m68k.c:2475 config/tc-m68k.c:2483 config/tc-m68k.c:2490
-#: config/tc-m68k.c:2497
+#: config/tc-m68k.c:2648 config/tc-m68k.c:2656 config/tc-m68k.c:2663
+#: config/tc-m68k.c:2670
 msgid "out of range"
 msgstr "fuera de rango"
 
-#: config/tc-m68k.c:2543
+#: config/tc-m68k.c:2716
 msgid "Can't use long branches on 68000/68010/5200"
 msgstr "No se pueden usar ramificaciones long en 68000/68010/5200"
 
-#: config/tc-m68k.c:2653
+#: config/tc-m68k.c:2833
 msgid "Expression out of range, using 0"
 msgstr "Expresión fuera de rango, utilizando 0"
 
-#: config/tc-m68k.c:2765 config/tc-m68k.c:2781
+#: config/tc-m68k.c:3014 config/tc-m68k.c:3030
 msgid "Floating point register in register list"
 msgstr "Registro de coma flotante en la lista de registros"
 
-#: config/tc-m68k.c:2771
+#: config/tc-m68k.c:3020
 msgid "Wrong register in floating-point reglist"
 msgstr "Registro erróneo en la lista de registros de coma flotante"
 
-#: config/tc-m68k.c:2787
+#: config/tc-m68k.c:3036
 msgid "incorrect register in reglist"
 msgstr "registro incorrecto en la lista de registros"
 
-#: config/tc-m68k.c:2793
+#: config/tc-m68k.c:3042
 msgid "wrong register in floating-point reglist"
 msgstr "registro erróneo en la lista de registros de coma flotante"
 
-#. ERROR
-#: config/tc-m68k.c:3234
+#. ERROR.
+#: config/tc-m68k.c:3505
 msgid "Extra )"
 msgstr ") extra"
 
-#. ERROR
-#: config/tc-m68k.c:3245
+#. ERROR.
+#: config/tc-m68k.c:3516
 msgid "Missing )"
 msgstr "Falta )"
 
-#: config/tc-m68k.c:3262
+#: config/tc-m68k.c:3533
 msgid "Missing operand"
 msgstr "Falta un operando"
 
-#: config/tc-m68k.c:3594
+#: config/tc-m68k.c:3890
 #, c-format
 msgid "%s -- statement `%s' ignored"
 msgstr "%s -- se ignora la declaración `%s'"
 
-#: config/tc-m68k.c:3643
+#: config/tc-m68k.c:3939
 #, c-format
 msgid "Don't know how to figure width of %c in md_assemble()"
 msgstr "No se sabe comó reconocer la anchura de %c en md_assemble()"
 
-#: config/tc-m68k.c:3825 config/tc-m68k.c:3863
+#: config/tc-m68k.c:4108
+#, c-format
+msgid "Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"
+msgstr "Error Interno:  No se puede alojar m68k_sorted_opcodes de tamaño %d"
+
+#: config/tc-m68k.c:4159 config/tc-m68k.c:4198
 #, c-format
 msgid "Internal Error: Can't find %s in hash table"
 msgstr "Error Interno: No se puede encontrar %s en la tabla de dispersión"
 
-#: config/tc-m68k.c:3828 config/tc-m68k.c:3866
+#: config/tc-m68k.c:4162 config/tc-m68k.c:4201
 #, c-format
 msgid "Internal Error: Can't hash %s: %s"
 msgstr "Error Interno: No se puede dispersar %s: %s"
 
-#: config/tc-m68k.c:3948
+#: config/tc-m68k.c:4282
 msgid "architecture not yet selected: defaulting to 68020"
-msgstr "no se ha seleccionado una arquitectura: cambiando por omisión a 68020"
+msgstr "no se ha seleccionado una arquitectura: cambiando por defecto a 68020"
 
-#: config/tc-m68k.c:3997
+#: config/tc-m68k.c:4342
 #, c-format
 msgid "unrecognized default cpu `%s' ???"
-msgstr "¿¿¿ cpu por omisión `%s' no reconocido ???"
+msgstr "¿¿¿ cpu por defecto `%s' no reconocido ???"
 
-#: config/tc-m68k.c:4009
+#: config/tc-m68k.c:4353
 msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
 msgstr "se especificaron 68040 y 68851; las instrucciones mmu podrían ensamblar incorrectamente"
 
-#: config/tc-m68k.c:4029
+#: config/tc-m68k.c:4370
 msgid "options for 68881 and no-68881 both given"
 msgstr "se dieron opciones para 68881 y para no-68881"
 
-#: config/tc-m68k.c:4031
+#: config/tc-m68k.c:4373
 msgid "options for 68851 and no-68851 both given"
 msgstr "se dieron opciones para 68851 y para no-68851"
 
-#: config/tc-m68k.c:4102
+#: config/tc-m68k.c:4434
 #, c-format
 msgid "text label `%s' aligned to odd boundary"
 msgstr "la etiqueta de texto `%s' está alineada a un límite impar"
 
-#: config/tc-m68k.c:4321
+#: config/tc-m68k.c:4638
 msgid "invalid byte branch offset"
 msgstr "desplazamiento de ramificación byte inválido"
 
-#: config/tc-m68k.c:4358
+#: config/tc-m68k.c:4674
 msgid "short branch with zero offset: use :w"
 msgstr "ramificación corta con desplazamiento cero: utilice :w"
 
-#: config/tc-m68k.c:4827 config/tc-m68k.c:4838
+#: config/tc-m68k.c:4698
+msgid "Tried to convert PC relative BSR to absolute JSR"
+msgstr "Se intentó convertir un BSR relativo al PC a un JSR absoluto"
+
+#: config/tc-m68k.c:4708 config/tc-m68k.c:5054
+msgid "Tried to convert PC relative branch to absolute jump"
+msgstr "Se trató de convertir una ramificación relativa al PC a un salto absoluto"
+
+#: config/tc-m68k.c:4724 config/tc-m68k.c:4783 config/tc-m68k.c:4847
+msgid "Tried to convert PC relative conditional branch to absolute jump"
+msgstr "Se intentó convertir una ramificación condicional relativa al PC a un salto absoluto"
+
+#: config/tc-m68k.c:4764
+msgid "Tried to convert DBcc to absolute jump"
+msgstr "Se intentó convertir DBcc a un salto absoluto"
+
+#: config/tc-m68k.c:5098 config/tc-m68k.c:5109 config/tc-m68k.c:5149
 msgid "expression out of range: defaulting to 1"
-msgstr "expresión fuera de rango: cambiando por omisión a 1"
+msgstr "expresión fuera de rango: cambiando por defecto a 1"
 
-#: config/tc-m68k.c:4870
+#: config/tc-m68k.c:5141
 msgid "expression out of range: defaulting to 0"
-msgstr "expresión fuera de rango: cambiando por omisión a 0"
+msgstr "expresión fuera de rango: cambiando por defecto a 0"
 
-#: config/tc-m68k.c:4903 config/tc-m68k.c:4915
+#: config/tc-m68k.c:5182 config/tc-m68k.c:5194
 #, c-format
 msgid "Can't deal with expression; defaulting to %ld"
-msgstr "No se puede lidiar con la expresión; cambiando por omisión a %ld"
+msgstr "No se puede lidiar con la expresión; cambiando por defecto a %ld"
 
-#: config/tc-m68k.c:4929
+#: config/tc-m68k.c:5208
 msgid "expression doesn't fit in BYTE"
 msgstr "la expresión no cabe en BYTE"
 
-#: config/tc-m68k.c:4933
+#: config/tc-m68k.c:5212
 msgid "expression doesn't fit in WORD"
 msgstr "la expresión no cabe en WORD"
 
-#: config/tc-m68k.c:5026
+#: config/tc-m68k.c:5299
 #, c-format
 msgid "%s: unrecognized processor name"
 msgstr "%s: nombre de procesador no reconocido"
 
-#: config/tc-m68k.c:5091
+#: config/tc-m68k.c:5363
 msgid "bad coprocessor id"
 msgstr "id de coprocesador erróneo"
 
-#: config/tc-m68k.c:5097
+#: config/tc-m68k.c:5369
 msgid "unrecognized fopt option"
 msgstr "opción fopt no reconocida"
 
-#: config/tc-m68k.c:5231
+#: config/tc-m68k.c:5502
 #, c-format
 msgid "option `%s' may not be negated"
 msgstr "la opción `%s' podría no estar negada"
 
-#: config/tc-m68k.c:5242
+#: config/tc-m68k.c:5513
 #, c-format
 msgid "option `%s' not recognized"
 msgstr "no se reconoce la opción `%s'"
 
-#: config/tc-m68k.c:5275
+#: config/tc-m68k.c:5542
 msgid "bad format of OPT NEST=depth"
 msgstr "formato erróneo de OPT NEST=profundidad"
 
-#: config/tc-m68k.c:5338
+#: config/tc-m68k.c:5598
 msgid "missing label"
 msgstr "etiqueta faltante"
 
-#: config/tc-m68k.c:5362 config/tc-m68k.c:5391
+#: config/tc-m68k.c:5622 config/tc-m68k.c:5651
 msgid "bad register list"
 msgstr "lista de registros errónea"
 
-#: config/tc-m68k.c:5364
+#: config/tc-m68k.c:5624
 #, c-format
 msgid "bad register list: %s"
 msgstr "lista de registros errónea: %s"
 
-#: config/tc-m68k.c:5462
+#: config/tc-m68k.c:5722
 msgid "restore without save"
 msgstr "restore sin save"
 
-#: config/tc-m68k.c:5636 config/tc-m68k.c:6023
+#: config/tc-m68k.c:5876 config/tc-m68k.c:6246
 msgid "syntax error in structured control directive"
 msgstr "error sintáctico en la directiva estructurada de control"
 
-#: config/tc-m68k.c:5685
+#: config/tc-m68k.c:5921
 msgid "missing condition code in structured control directive"
 msgstr "falta el código de condición en la directiva estructurada de control"
 
-#: config/tc-m68k.c:5757
+#: config/tc-m68k.c:5992
 #, c-format
 msgid "Condition <%c%c> in structured control directive can not be encoded correctly"
 msgstr "La condición <%c%c> en la directiva de contro estructurado no se puede codificar correctamente"
 
-#: config/tc-m68k.c:6066
+#: config/tc-m68k.c:6288
 msgid "missing then"
 msgstr "then faltante"
 
-#: config/tc-m68k.c:6148
+#: config/tc-m68k.c:6369
 msgid "else without matching if"
 msgstr "else sin if coincidente"
 
-#: config/tc-m68k.c:6182
+#: config/tc-m68k.c:6402
 msgid "endi without matching if"
 msgstr "endi sin if coincidente"
 
-#: config/tc-m68k.c:6223
+#: config/tc-m68k.c:6442
 msgid "break outside of structured loop"
 msgstr "break fuera de un loop estructurado"
 
-#: config/tc-m68k.c:6262
+#: config/tc-m68k.c:6480
 msgid "next outside of structured loop"
 msgstr "next fuera de un loop estructurado"
 
-#: config/tc-m68k.c:6314
+#: config/tc-m68k.c:6531
 msgid "missing ="
 msgstr "= faltante"
 
-#: config/tc-m68k.c:6352
+#: config/tc-m68k.c:6569
 msgid "missing to or downto"
 msgstr "to o downto faltante"
 
-#: config/tc-m68k.c:6388 config/tc-m68k.c:6422 config/tc-m68k.c:6641
+#: config/tc-m68k.c:6605 config/tc-m68k.c:6639 config/tc-m68k.c:6853
 msgid "missing do"
 msgstr "do faltante"
 
-#: config/tc-m68k.c:6525
+#: config/tc-m68k.c:6740
 msgid "endf without for"
 msgstr "endf sin for"
 
-#: config/tc-m68k.c:6581
+#: config/tc-m68k.c:6794
 msgid "until without repeat"
 msgstr "until sin repeat"
 
-#: config/tc-m68k.c:6677
+#: config/tc-m68k.c:6888
 msgid "endw without while"
 msgstr "endw sin while"
 
-#: config/tc-m68k.c:6801
-#, c-format
-msgid "unrecognized option `%s'"
-msgstr "opción `%s' no reconocida"
-
-#: config/tc-m68k.c:6846
+#: config/tc-m68k.c:7050
 #, c-format
 msgid "unrecognized architecture specification `%s'"
 msgstr "especificación de arquitectura `%s' no reconocida"
 
-#: config/tc-m68k.c:6940
+#: config/tc-m68k.c:7143
 #, c-format
 msgid ""
 "680X0 options:\n"
 "-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
 "-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
 "-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m5307  | -m5407\n"
+"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
+"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
 "\t\t\tspecify variant of 680X0 architecture [default %s]\n"
 "-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
 "\t\t\ttarget has/lacks floating-point coprocessor\n"
 "\t\t\t[default yes for 68020, 68030, and cpu32]\n"
 msgstr ""
 "Opciones de 680X0:\n"
-"-l\t\t\tusa 1 word para referencias a símbolos indefinidos [por omisión 2]\n"
+"-l\t\t\tusa 1 word para referencias a símbolos indefinidos [por defecto 2]\n"
 "-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
 "-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m5307  | -m5407\n"
-"\t\t\tespecifica la variación de la arquitectura 680X0 [por omisión %s]\n"
+"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
+"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
+"\t\t\tespecifica la variación de la arquitectura 680X0 [por defecto %s]\n"
 "-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
 "\t\t\tel objetivo tiene un/carece de coprocesador de coma flotante\n"
-"\t\t\t[por omisión sí para 68020, 68030, y cpu32]\n"
+"\t\t\t[por defecto sí para 68020, 68030, y cpu32]\n"
 
-#: config/tc-m68k.c:6951
+#: config/tc-m68k.c:7155
+#, c-format
 msgid ""
 "-m68851 | -mno-68851\n"
 "\t\t\ttarget has/lacks memory-management unit coprocessor\n"
@@ -5985,7 +6595,7 @@ msgid ""
 msgstr ""
 "-m68851 | -mno-68851\n"
 "\t\t\tel objetivo tiene un/carece de coprocesador de unidad de administración de memoria\n"
-"\t\t\t[por omisión sí para 68020 y superior]\n"
+"\t\t\t[por defecto sí para 68020 y superior]\n"
 "-pic, -k\t\tgenera código independiente de posición\n"
 "-S\t\t\tconvierte jbsr en jsr\n"
 "--pcrel                 nunca convierte ramificaciones relativas al PC en saltos absolutos\n"
@@ -5993,7 +6603,8 @@ msgstr ""
 "\t\t\treconoce los nombres de registro sin carácter de prefijo\n"
 "--bitwise-or\t\tno trata `|' como un carácter de comentario\n"
 
-#: config/tc-m68k.c:6961
+#: config/tc-m68k.c:7165
+#, c-format
 msgid ""
 "--base-size-default-16\tbase reg without size is 16 bits\n"
 "--base-size-default-32\tbase reg without size is 32 bits (default)\n"
@@ -6001,226 +6612,179 @@ msgid ""
 "--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n"
 msgstr ""
 "--base-size-default-16\tel registro base sin tamaño es de 16 bits\n"
-"--base-size-default-32\tel registro base sin tamaño es de 32 bits (por omisión)\n"
+"--base-size-default-32\tel registro base sin tamaño es de 32 bits (por defecto)\n"
 "--disp-size-default-16\tla desubicación de tamaño desconocido es de 16 bits\n"
-"--disp-size-default-32\tla desubicación de tamaño desconocido es de 32 bits (por omisión)\n"
+"--disp-size-default-32\tla desubicación de tamaño desconocido es de 32 bits (por defecto)\n"
 
-#: config/tc-m68k.c:6996
+#: config/tc-m68k.c:7200
 #, c-format
 msgid "Error %s in %s\n"
 msgstr "Error %s en %s\n"
 
-#: config/tc-m68k.c:7000
+#: config/tc-m68k.c:7204
 #, c-format
 msgid "Opcode(%d.%s): "
 msgstr "Código de operación(%d.%s): "
 
-#: config/tc-m88k.c:201
-#, c-format
-msgid "Can't hash instruction '%s':%s"
-msgstr "No se puede dispersar la instrucción '%s':%s"
-
-#: config/tc-m88k.c:250
-#, c-format
-msgid "Invalid mnemonic '%s'"
-msgstr "Mnemónico inválido '%s'"
-
-#: config/tc-m88k.c:268
-msgid "Parameter syntax error"
-msgstr "Error sintáctico de parámetros"
-
-#: config/tc-m88k.c:321
-msgid "Unknown relocation type"
-msgstr "Tipo de reubicación desconocido"
-
-#. Having this here repeats the warning somtimes.
-#. But can't we stand that?
-#: config/tc-m88k.c:434
-msgid "Use of obsolete instruction"
-msgstr "Uso de una instrucción obsoleta"
-
-#: config/tc-m88k.c:551
-msgid "Expression truncated to 16 bits"
-msgstr "Expresión truncada a 16 bits"
-
-#: config/tc-m88k.c:617 config/tc-m88k.c:639
-msgid "Expression truncated to 5 bits"
-msgstr "Expresión truncada a 5 bits"
-
-#: config/tc-m88k.c:856
-msgid "Expression truncated to 9 bits"
-msgstr "Expresión truncada a 9 bits"
-
-#: config/tc-m88k.c:878
-msgid "Removed lower 2 bits of expression"
-msgstr "Se borraron los 2 bits inferiores de la expresión"
-
-#: config/tc-m88k.c:1057
-msgid "Relaxation should never occur"
-msgstr "La relajación nunca debe ocurrir"
-
-#: config/tc-m88k.h:78
-msgid "m88k convert_frag\n"
-msgstr "m88k convert_frag\n"
-
-#: config/tc-mcore.c:460
+#: config/tc-mcore.c:524
 #, c-format
 msgid "register expected, but saw '%.6s'"
 msgstr "se esperaba un registro, pero se vio '%.6s'"
 
-#: config/tc-mcore.c:544
+#: config/tc-mcore.c:606
 #, c-format
 msgid "control register expected, but saw '%.6s'"
 msgstr "se esperaba un registro de control, pero se vio '%.6s'"
 
-#: config/tc-mcore.c:582
+#: config/tc-mcore.c:642
 msgid "bad/missing psr specifier"
 msgstr "especificador psr erróneo/faltante"
 
-#: config/tc-mcore.c:743
+#: config/tc-mcore.c:692
 msgid "more than 65K literal pools"
 msgstr "más de 65K de conjuntos literales"
 
-#: config/tc-mcore.c:797
+#: config/tc-mcore.c:746
 msgid "missing ']'"
 msgstr "falta un ']'"
 
-#: config/tc-mcore.c:837
+#: config/tc-mcore.c:785
 msgid "operand must be a constant"
 msgstr "el operando debe ser una constante"
 
-#: config/tc-mcore.c:839
+#: config/tc-mcore.c:787
 #, c-format
 msgid "operand must be absolute in range %u..%u, not %ld"
 msgstr "el operando debe ser un absoluto en el rango %u..%u, no %ld"
 
-#: config/tc-mcore.c:875
+#: config/tc-mcore.c:822
 msgid "operand must be a multiple of 4"
 msgstr "el operando debe ser un múltiplo de 4"
 
-#: config/tc-mcore.c:882
+#: config/tc-mcore.c:829
 msgid "operand must be a multiple of 2"
 msgstr "el operando debe ser un múltiplo de 2"
 
-#: config/tc-mcore.c:896 config/tc-mcore.c:1410 config/tc-mcore.c:1464
+#: config/tc-mcore.c:843 config/tc-mcore.c:1359 config/tc-mcore.c:1413
 msgid "base register expected"
 msgstr "se esperaba un registro base"
 
-#: config/tc-mcore.c:945
+#: config/tc-mcore.c:891
 #, c-format
 msgid "unknown opcode \"%s\""
 msgstr "código de operación \"%s\" desconocido"
 
-#: config/tc-mcore.c:988
+#: config/tc-mcore.c:934
 msgid "invalid register: r15 illegal"
 msgstr "registro inválido: r15 ilegal"
 
-#: config/tc-mcore.c:1036 config/tc-mcore.c:1614
+#: config/tc-mcore.c:983 config/tc-mcore.c:1564
 msgid "M340 specific opcode used when assembling for M210"
 msgstr "se utilizó un código de operación específico de M340 cuando se ensamblaba para M210"
 
-#: config/tc-mcore.c:1054 config/tc-mcore.c:1093 config/tc-mcore.c:1112
-#: config/tc-mcore.c:1131 config/tc-mcore.c:1158 config/tc-mcore.c:1187
-#: config/tc-mcore.c:1224 config/tc-mcore.c:1259 config/tc-mcore.c:1278
-#: config/tc-mcore.c:1297 config/tc-mcore.c:1331 config/tc-mcore.c:1356
-#: config/tc-mcore.c:1413 config/tc-mcore.c:1467 config/tc-mcore.c:1503
-#: config/tc-mcore.c:1561 config/tc-mcore.c:1583 config/tc-mcore.c:1606
+#: config/tc-mcore.c:1001 config/tc-mcore.c:1041 config/tc-mcore.c:1060
+#: config/tc-mcore.c:1079 config/tc-mcore.c:1107 config/tc-mcore.c:1136
+#: config/tc-mcore.c:1173 config/tc-mcore.c:1208 config/tc-mcore.c:1227
+#: config/tc-mcore.c:1246 config/tc-mcore.c:1280 config/tc-mcore.c:1305
+#: config/tc-mcore.c:1362 config/tc-mcore.c:1416 config/tc-mcore.c:1452
+#: config/tc-mcore.c:1511 config/tc-mcore.c:1533 config/tc-mcore.c:1556
 msgid "second operand missing"
 msgstr "falta el segundo operando"
 
-#: config/tc-mcore.c:1069
+#: config/tc-mcore.c:1017
 msgid "destination register must be r1"
 msgstr "el registro destino debe ser r1"
 
-#: config/tc-mcore.c:1090
+#: config/tc-mcore.c:1038
 msgid "source register must be r1"
 msgstr "el registro fuente debe ser r1"
 
-#: config/tc-mcore.c:1153 config/tc-mcore.c:1210
+#: config/tc-mcore.c:1102 config/tc-mcore.c:1159
 msgid "immediate is not a power of two"
 msgstr "el inmediato no es una potencia de dos"
 
-#: config/tc-mcore.c:1181
+#: config/tc-mcore.c:1130
 msgid "translating bgeni to movi"
 msgstr "traduciendo bgeni a movi"
 
-#: config/tc-mcore.c:1218
+#: config/tc-mcore.c:1167
 msgid "translating mgeni to movi"
 msgstr "traduciendo mgeni a movi"
 
-#: config/tc-mcore.c:1250
+#: config/tc-mcore.c:1199
 msgid "translating bmaski to movi"
 msgstr "traduciendo bmaski a movi"
 
-#: config/tc-mcore.c:1326
+#: config/tc-mcore.c:1275
 #, c-format
 msgid "displacement too large (%d)"
 msgstr "desubicación demasiado grande (%d)"
 
-#: config/tc-mcore.c:1340
+#: config/tc-mcore.c:1289
 msgid "Invalid register: r0 and r15 illegal"
 msgstr "Registro inválido: r0 y r15 ilegales"
 
-#: config/tc-mcore.c:1371
+#: config/tc-mcore.c:1320
 msgid "bad starting register: r0 and r15 invalid"
 msgstr "registro de inicio erróneo: r0 y r15 inválidos"
 
-#: config/tc-mcore.c:1384
+#: config/tc-mcore.c:1333
 msgid "ending register must be r15"
 msgstr "el registro final debe ser r15"
 
-#: config/tc-mcore.c:1404
+#: config/tc-mcore.c:1353
 msgid "bad base register: must be r0"
 msgstr "registro base erróneo: debe ser r0"
 
-#: config/tc-mcore.c:1422
+#: config/tc-mcore.c:1371
 msgid "first register must be r4"
 msgstr "el primer registro debe ser r4"
 
-#: config/tc-mcore.c:1433
+#: config/tc-mcore.c:1382
 msgid "last register must be r7"
 msgstr "el último registro debe ser r7"
 
-#: config/tc-mcore.c:1470
+#: config/tc-mcore.c:1419
 msgid "reg-reg expected"
 msgstr "se esperaba registro-registro"
 
-#: config/tc-mcore.c:1580
+#: config/tc-mcore.c:1530
 msgid "second operand must be 1"
 msgstr "el segundo operando debe ser 1"
 
-#: config/tc-mcore.c:1601
+#: config/tc-mcore.c:1551
 msgid "zero used as immediate value"
 msgstr "se utiliza cero como un valor inmediato"
 
-#: config/tc-mcore.c:1628
+#: config/tc-mcore.c:1578
 msgid "duplicated psr bit specifier"
 msgstr "especificador de bit psr duplicado"
 
-#: config/tc-mcore.c:1634
+#: config/tc-mcore.c:1584
 msgid "`af' must appear alone"
 msgstr "`af' debe aparecer solo"
 
-#: config/tc-mcore.c:1641
+#: config/tc-mcore.c:1591
 #, c-format
 msgid "unimplemented opcode \"%s\""
 msgstr "código de operación \"%s\" sin implementar"
 
-#: config/tc-mcore.c:1650
+#: config/tc-mcore.c:1600
 #, c-format
 msgid "ignoring operands: %s "
 msgstr "se ignoran los operandos: %s "
 
-#: config/tc-mcore.c:1718 config/tc-w65.c:772
+#: config/tc-mcore.c:1665
 msgid "Bad call to MD_NTOF()"
 msgstr "Llamada errónea a MD_NTOF()"
 
-#: config/tc-mcore.c:1788
+#: config/tc-mcore.c:1736
 #, c-format
 msgid "unrecognised cpu type '%s'"
 msgstr "tipo de cpu '%s' no reconocido"
 
-#: config/tc-mcore.c:1807
+#: config/tc-mcore.c:1754
+#, c-format
 msgid ""
 "MCORE specific options:\n"
 "  -{no-}jsri2bsr\t  {dis}able jsri to bsr transformation (def: dis)\n"
@@ -6233,682 +6797,676 @@ msgstr ""
 "  -{no-}jsri2bsr\t  {des}activa la transformación de jsri a bsr (def: des)\n"
 "  -{no-}sifilter\t  {des}activa el comportamiento de filtro del silicón (def: des)\n"
 "  -cpu=[210|340]          selecciona el tipo de CPU\n"
-"  -EB                     ensambla para un sistema big endian (por omisión)\n"
+"  -EB                     ensambla para un sistema big endian (por defecto)\n"
 "  -EL                     ensambla para un sistema little endian\n"
 
-#: config/tc-mcore.c:1826
+#: config/tc-mcore.c:1772
 msgid "failed sanity check: short_jump"
 msgstr "falló la prueba de sanidad: short_jump"
 
-#: config/tc-mcore.c:1837
+#: config/tc-mcore.c:1782
 msgid "failed sanity check: long_jump"
 msgstr "falló la prueba de sanidad: long_jump"
 
-#: config/tc-mcore.c:1863
+#: config/tc-mcore.c:1808
 #, c-format
 msgid "odd displacement at %x"
 msgstr "desubicación impar en %x"
 
-#: config/tc-mcore.c:2047
+#: config/tc-mcore.c:1990
 msgid "unknown"
 msgstr "desconocido"
 
-#: config/tc-mcore.c:2073
+#: config/tc-mcore.c:2017
 #, c-format
 msgid "odd distance branch (0x%lx bytes)"
 msgstr "distancia de ramificación impar (0x%lx bytes)"
 
-#: config/tc-mcore.c:2077
+#: config/tc-mcore.c:2021
 #, c-format
 msgid "pcrel for branch to %s too far (0x%lx)"
 msgstr "el pcrel para la ramificación a %s está demasiado lejos (0x%lx)"
 
-#: config/tc-mcore.c:2096
+#: config/tc-mcore.c:2041
 #, c-format
 msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"
 msgstr "el pcrel para lrw/jmpi/jsri a %s está demasiado lejos (0x%lx)"
 
-#: config/tc-mcore.c:2107
+#: config/tc-mcore.c:2053
 #, c-format
 msgid "pcrel for loopt too far (0x%lx)"
 msgstr "el pcrel para loopt está demasiado lejos (0x%lx)"
 
-#: config/tc-mcore.c:2336
+#: config/tc-mcore.c:2263
 #, c-format
 msgid "Can not do %d byte %srelocation"
 msgstr "No se puede hacer la reubicación de %d byte %s"
 
-#: config/tc-mcore.c:2338
+#: config/tc-mcore.c:2265
 msgid "pc-relative"
 msgstr "relativo al pc"
 
 #. Prototypes for static functions.
-#: config/tc-mips.c:817
+#: config/tc-mips.c:957
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr "Error interno, línea %d, %s"
 
-#: config/tc-mips.c:1130
+#: config/tc-mips.c:1443
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr "interno: no se puede dispersar `%s': %s"
 
-#: config/tc-mips.c:1138
+#: config/tc-mips.c:1451
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr "error interno: código de operación mips16 erróneo: %s %s\n"
 
-#: config/tc-mips.c:1331
+#: config/tc-mips.c:1652
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr "devuelto de mips_ip(%s) insn_opcode = 0x%x\n"
 
-#: config/tc-mips.c:1975 config/tc-mips.c:13665
+#: config/tc-mips.c:2327 config/tc-mips.c:13480
 msgid "extended instruction in delay slot"
 msgstr "instrucción extendida en ranuta de retardo"
 
-#: config/tc-mips.c:2021 config/tc-mips.c:2031
+#: config/tc-mips.c:2391 config/tc-mips.c:2401
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr "salto a una dirección mal alineada (0x%lx)"
 
-#: config/tc-mips.c:2024 config/tc-mips.c:2034
+#: config/tc-mips.c:2394 config/tc-mips.c:2404
 #, c-format
 msgid "jump address range overflow (0x%lx)"
 msgstr "desbordamiento de rango de salto de dirección (0x%lx)"
 
-#: config/tc-mips.c:2804 config/tc-mips.c:3193
-msgid "Macro instruction expanded into multiple instructions"
-msgstr "Instrucción macro expandida en instrucciones múltiples"
-
-#: config/tc-mips.c:2816
+#: config/tc-mips.c:2893
 msgid "Macro instruction expanded into multiple instructions in a branch delay slot"
 msgstr "Instrucción macro expandida en instrucciones múltiples en una ranura de retraso de ramificación"
 
-#: config/tc-mips.c:3224 config/tc-mips.c:7548 config/tc-mips.c:7574
-#: config/tc-mips.c:7652 config/tc-mips.c:7677
+#: config/tc-mips.c:2896
+msgid "Macro instruction expanded into multiple instructions"
+msgstr "Instrucción macro expandida en instrucciones múltiples"
+
+#: config/tc-mips.c:3414 config/tc-mips.c:7338 config/tc-mips.c:7362
+#: config/tc-mips.c:7435 config/tc-mips.c:7458
 msgid "operand overflow"
 msgstr "desbordamiento de operando"
 
-#: config/tc-mips.c:3250 config/tc-mips.c:6901 config/tc-mips.c:7753
+#: config/tc-mips.c:3433 config/tc-mips.c:4033 config/tc-mips.c:6734
+#: config/tc-mips.c:7525
 msgid "Macro used $at after \".set noat\""
 msgstr "La macro utilizó $at después de \".set noat\""
 
-#: config/tc-mips.c:3280
+#: config/tc-mips.c:3462
 msgid "unsupported large constant"
 msgstr "constante large sin soporte"
 
-#: config/tc-mips.c:3282
+#: config/tc-mips.c:3464
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr "La instrucción %s requiere una expresión absoluta"
 
-#: config/tc-mips.c:3421
+#: config/tc-mips.c:3597 config/tc-mips.c:5844 config/tc-mips.c:6438
 #, c-format
-msgid "Number (0x%lx) larger than 32 bits"
-msgstr "El número (0x%lx) es más grande que 32 bits"
+msgid "Number (0x%s) larger than 32 bits"
+msgstr "El número (0x%s) es más grande que 32 bits"
 
-#: config/tc-mips.c:3443
+#: config/tc-mips.c:3617
 msgid "Number larger than 64 bits"
 msgstr "El número es más grande que 64 bits"
 
-#: config/tc-mips.c:3746 config/tc-mips.c:3786 config/tc-mips.c:3828
-#: config/tc-mips.c:3885 config/tc-mips.c:6068 config/tc-mips.c:6110
-#: config/tc-mips.c:6162 config/tc-mips.c:6660 config/tc-mips.c:6715
+#: config/tc-mips.c:3911 config/tc-mips.c:3939 config/tc-mips.c:3977
+#: config/tc-mips.c:4022 config/tc-mips.c:6053 config/tc-mips.c:6092
+#: config/tc-mips.c:6131 config/tc-mips.c:6553 config/tc-mips.c:6605
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr "Desbordamiento del desplazamiento del código PIC (máx 16 bits con signo)"
 
-#: config/tc-mips.c:4145
-#, c-format
-msgid "Branch %s is always false (nop)"
-msgstr "La ramificación %s es siempre falsa (nop)"
-
-#: config/tc-mips.c:4152
-#, c-format
-msgid "Branch likely %s is always false"
-msgstr "La ramificación como %s es siempre falsa"
-
-#: config/tc-mips.c:4159 config/tc-mips.c:4227 config/tc-mips.c:4319
-#: config/tc-mips.c:4368 config/tc-mips.c:7856 config/tc-mips.c:7864
-#: config/tc-mips.c:7871 config/tc-mips.c:7978
+#: config/tc-mips.c:4328 config/tc-mips.c:4394 config/tc-mips.c:4482
+#: config/tc-mips.c:4529 config/tc-mips.c:4590 config/tc-mips.c:4638
+#: config/tc-mips.c:7619 config/tc-mips.c:7626 config/tc-mips.c:7633
+#: config/tc-mips.c:7740
 msgid "Unsupported large constant"
 msgstr "Constante large sin soporte"
 
 #. result is always true
-#: config/tc-mips.c:4193
+#: config/tc-mips.c:4360
 #, c-format
 msgid "Branch %s is always true"
 msgstr "La ramificación %s es siempre verdadera"
 
-#: config/tc-mips.c:4436 config/tc-mips.c:4539
+#: config/tc-mips.c:4601 config/tc-mips.c:4649 config/tc-mips.c:8309
+#, c-format
+msgid "Improper position (%lu)"
+msgstr "Posición impropia (%lu)"
+
+#: config/tc-mips.c:4607 config/tc-mips.c:8376
+#, c-format
+msgid "Improper extract size (%lu, position %lu)"
+msgstr "Tamaño de extract impropio (%lu, posición %lu)"
+
+#: config/tc-mips.c:4655 config/tc-mips.c:8340
+#, c-format
+msgid "Improper insert size (%lu, position %lu)"
+msgstr "Tamaño de insert impropio (%lu, posición %lu)"
+
+#: config/tc-mips.c:4692 config/tc-mips.c:4789
 msgid "Divide by zero."
 msgstr "División por cero."
 
-#: config/tc-mips.c:4621
+#: config/tc-mips.c:4875
 msgid "dla used to load 32-bit register"
 msgstr "Se usa dla para cargar registros de 32-bit"
 
-#: config/tc-mips.c:4624
+#: config/tc-mips.c:4878
 msgid "la used to load 64-bit address"
 msgstr "Se usa la para cargar registros de 64-bit"
 
-#: config/tc-mips.c:4999 config/tc-mips.c:5352
+#: config/tc-mips.c:4990
+msgid "offset too large"
+msgstr "desplazamiento demasiado grande"
+
+#: config/tc-mips.c:5162 config/tc-mips.c:5441
 msgid "PIC code offset overflow (max 32 signed bits)"
 msgstr "Desbordamiento del desplazamiento del código PIC (máx 32 bits con signo)"
 
-#: config/tc-mips.c:5418
+#: config/tc-mips.c:5487
 msgid "MIPS PIC call to register other than $25"
 msgstr "Llamada PIC MIPS a un registro diferente de $25"
 
-#: config/tc-mips.c:5424 config/tc-mips.c:5435 config/tc-mips.c:5573
-#: config/tc-mips.c:5584
+#: config/tc-mips.c:5493 config/tc-mips.c:5504 config/tc-mips.c:5628
+#: config/tc-mips.c:5639
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr "No se utilizó el pseudo-operador .cprestore en el código PIC"
 
-#: config/tc-mips.c:5429 config/tc-mips.c:5578
+#: config/tc-mips.c:5498 config/tc-mips.c:5633
 msgid "No .frame pseudo-op used in PIC code"
 msgstr "No se utilizó el pseudo-operador .frame en el código PIC"
 
-#: config/tc-mips.c:5656 config/tc-mips.c:5745 config/tc-mips.c:6413
-#: config/tc-mips.c:6452 config/tc-mips.c:6470 config/tc-mips.c:7220
+#: config/tc-mips.c:5704 config/tc-mips.c:5792 config/tc-mips.c:6338
+#: config/tc-mips.c:6369 config/tc-mips.c:6387 config/tc-mips.c:7037
 msgid "opcode not supported on this processor"
 msgstr "el código de operación no tiene soporte en este procesador"
 
-#: config/tc-mips.c:5969
-msgid "load/store address overflow (max 32 bits)"
-msgstr "desbordamiento de dirección load/store (máx 32 bits)"
-
-#: config/tc-mips.c:7083 config/tc-mips.c:7116 config/tc-mips.c:7166
-#: config/tc-mips.c:7198
+#: config/tc-mips.c:6903 config/tc-mips.c:6934 config/tc-mips.c:6985
+#: config/tc-mips.c:7015
 msgid "Improper rotate count"
 msgstr "Cuenta de rotación impropia"
 
-#: config/tc-mips.c:7259
+#: config/tc-mips.c:7070
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr "Instrucción %s: el resultado es siempre falso"
 
-#: config/tc-mips.c:7417
+#: config/tc-mips.c:7216
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr "Instrucción %s: el resultado es siempre verdadero"
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:7749
+#: config/tc-mips.c:7521
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr "La macro %s aún no está implementada"
 
-#: config/tc-mips.c:8009
+#: config/tc-mips.c:7771
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr "interno: código de operación mips erróneo (error de máscara): %s %s"
 
-#: config/tc-mips.c:8029 config/tc-mips.c:8360
+#: config/tc-mips.c:7799 config/tc-mips.c:8430
 #, c-format
 msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
 msgstr "interno: código de operación mips erróneo (tipo de operando `+%c' desconocido): %s %s"
 
-#: config/tc-mips.c:8090
+#: config/tc-mips.c:7876
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr "interno: código de operación mips erróneo (tipo de operando `%c' desconocido): %s %s"
 
-#: config/tc-mips.c:8097
+#: config/tc-mips.c:7883
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr "interno: código de operación mips erróneo (bits 0x%lx indefinidos): %s %s"
 
-#: config/tc-mips.c:8211
+#: config/tc-mips.c:8000
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr "el código de operación no tiene soporte en este procesador: %s (%s)"
 
-#: config/tc-mips.c:8292
+#: config/tc-mips.c:8031 config/tc-mips.c:8045 config/tc-mips.c:8059
+#: config/tc-mips.c:8073 config/tc-mips.c:8100 config/tc-mips.c:8147
 #, c-format
-msgid "Improper position (%lu)"
-msgstr "Posición impropia (%lu)"
+msgid "DSP immediate not in range 0..%d (%lu)"
+msgstr "el inmediato DSP no está en el rango 0..%d (%lu)"
+
+#: config/tc-mips.c:8092 config/tc-mips.c:8120
+msgid "Invalid dsp acc register"
+msgstr "Registro acc dsc inválido"
 
-#: config/tc-mips.c:8318
+#: config/tc-mips.c:8131 config/tc-mips.c:8165 config/tc-mips.c:8184
 #, c-format
-msgid "Improper insert size (%lu, position %lu)"
-msgstr "Tamaño de insert impropio (%lu, posición %lu)"
+msgid "DSP immediate not in range %ld..%ld (%ld)"
+msgstr "El inmediato DSP no está en el rango %ld..%ld (%ld)"
 
-#: config/tc-mips.c:8344
+#: config/tc-mips.c:8200 config/tc-mips.c:8214
 #, c-format
-msgid "Improper extract size (%lu, position %lu)"
-msgstr "Tamaño de extract impropio (%lu, posición %lu)"
+msgid "MT immediate not in range 0..%d (%lu)"
+msgstr "El inmediato MT no está en el rango 0..%d (%lu)"
+
+#: config/tc-mips.c:8233 config/tc-mips.c:8246
+msgid "Invalid dsp/smartmips acc register"
+msgstr "Registro acc dsp/smartmips inválido"
+
+#: config/tc-mips.c:8395 config/tc-mips.c:8899
+msgid "absolute expression required"
+msgstr "se requiere una expresión absoluta"
 
-#: config/tc-mips.c:8378
+#: config/tc-mips.c:8418 config/tc-mips.c:8579
+#, c-format
+msgid "Invalid register number (%d)"
+msgstr "Número de registro inválido (%d)"
+
+#: config/tc-mips.c:8426
+msgid "Invalid coprocessor 0 register number"
+msgstr "Número de registro 0 de coprocesador inválido"
+
+#: config/tc-mips.c:8447
 #, c-format
 msgid "Improper shift amount (%lu)"
 msgstr "Cantidad de desplazamiento impropia (%lu)"
 
-#: config/tc-mips.c:8404 config/tc-mips.c:9654 config/tc-mips.c:9769
+#: config/tc-mips.c:8470 config/tc-mips.c:9731 config/tc-mips.c:9844
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr "Valor inválido para `%s' (%lu)"
 
-#: config/tc-mips.c:8422
+#: config/tc-mips.c:8485
 #, c-format
 msgid "Illegal break code (%lu)"
 msgstr "Código de interrupción ilegal (%lu)"
 
-#: config/tc-mips.c:8436
+#: config/tc-mips.c:8496
 #, c-format
 msgid "Illegal lower break code (%lu)"
 msgstr "Código de interrupción inferior ilegal (%lu)"
 
-#: config/tc-mips.c:8449
+#: config/tc-mips.c:8507
 #, c-format
 msgid "Illegal 20-bit code (%lu)"
 msgstr "Código de 20-bit ilegal (%lu)"
 
-#: config/tc-mips.c:8461
+#: config/tc-mips.c:8519
 #, c-format
 msgid "Coproccesor code > 25 bits (%lu)"
 msgstr "Código de coprocesador > 25 bits (%lu)"
 
-#: config/tc-mips.c:8474
+#: config/tc-mips.c:8532
 #, c-format
 msgid "Illegal 19-bit code (%lu)"
 msgstr "Código de 19-bit ilegal (%lu)"
 
-#: config/tc-mips.c:8486
+#: config/tc-mips.c:8543
 #, c-format
 msgid "Invalid performance register (%lu)"
 msgstr "Registro de rendimiento inválido (%lu)"
 
-#: config/tc-mips.c:8524
-#, c-format
-msgid "Invalid register number (%d)"
-msgstr "Número de registro inválido (%d)"
-
-#: config/tc-mips.c:8702
+#: config/tc-mips.c:8754
 #, c-format
 msgid "Invalid MDMX Immediate (%ld)"
 msgstr "Inmediato MDMX inválido (%ld)"
 
-#: config/tc-mips.c:8745
+#: config/tc-mips.c:8794
 #, c-format
 msgid "Invalid float register number (%d)"
 msgstr "Número de registro de coma flotante inválido (%d)"
 
-#: config/tc-mips.c:8755
+#: config/tc-mips.c:8810
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr "El registro de coma flotante debería ser par, era %d"
 
-#: config/tc-mips.c:8794
+#: config/tc-mips.c:8849
 #, c-format
 msgid "Bad element selector %ld"
 msgstr "Selector de elemento %ld erróneo"
 
-#: config/tc-mips.c:8801
+#: config/tc-mips.c:8857
 #, c-format
 msgid "Expecting ']' found '%s'"
 msgstr "Se esperaba ']', se encontró '%s'"
 
-#: config/tc-mips.c:8843
-msgid "absolute expression required"
-msgstr "se requiere una expresión absoluta"
-
-#: config/tc-mips.c:8911
+#: config/tc-mips.c:8963
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr "Constante de coma flotante errónea: %s"
 
-#: config/tc-mips.c:9039
+#: config/tc-mips.c:9084
 msgid "Can't use floating point insn in this section"
 msgstr "No se pueden utilizar instrucciones de coma flotante en esta sección"
 
-#: config/tc-mips.c:9100
+#: config/tc-mips.c:9145
 msgid "expression out of range"
 msgstr "expresión fuera de rango"
 
-#: config/tc-mips.c:9140
+#: config/tc-mips.c:9185
 msgid "lui expression not in range 0..65535"
 msgstr "la expresión de 16 bit no está en el rango 0..65535"
 
-#: config/tc-mips.c:9164
+#: config/tc-mips.c:9209
 #, c-format
-msgid "invalid condition code register $fcc%d"
-msgstr "registro de código de condición $fcc%d inválido"
+msgid "Invalid condition code register $fcc%d"
+msgstr "Registro de código de condición $fcc%d inválido"
 
-#: config/tc-mips.c:9189
+#: config/tc-mips.c:9214
+#, c-format
+msgid "Condition code register should be even for %s, was %d"
+msgstr "El registro de código de condición debería ser par para %s, era %d"
+
+#: config/tc-mips.c:9219
+#, c-format
+msgid "Condition code register should be 0 or 4 for %s, was %d"
+msgstr "El registro de código de condición debería ser 0 o 4 para %s, era %d"
+
+#: config/tc-mips.c:9245
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr "valor de subselección de coprocesador (0-7) inválido"
 
-#: config/tc-mips.c:9201 config/tc-mips.c:9218
+#: config/tc-mips.c:9257 config/tc-mips.c:9274
 #, c-format
 msgid "bad byte vector index (%ld)"
 msgstr "índice de vector de byte erróneo (%ld)"
 
-#: config/tc-mips.c:9229
+#: config/tc-mips.c:9285
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr "carácter erróneo = '%c'\n"
 
-#: config/tc-mips.c:9240 config/tc-mips.c:9245 config/tc-mips.c:9794
+#: config/tc-mips.c:9296 config/tc-mips.c:9301 config/tc-mips.c:9869
 msgid "illegal operands"
 msgstr "operandos ilegales"
 
-#: config/tc-mips.c:9310
+#: config/tc-mips.c:9367
 msgid "unrecognized opcode"
 msgstr "códigos de operación no reconocidos"
 
-#: config/tc-mips.c:9422
+#: config/tc-mips.c:9504
 #, c-format
 msgid "invalid register number (%d)"
 msgstr "número de registro inválido (%d)"
 
-#: config/tc-mips.c:9513
+#: config/tc-mips.c:9595
 msgid "used $at without \".set noat\""
 msgstr "se utilizó $at sin \".set noat\""
 
-#: config/tc-mips.c:9688
+#: config/tc-mips.c:9763
 msgid "can't parse register list"
 msgstr "no se puede decodificar la lista de registros"
 
-#: config/tc-mips.c:9912
+#: config/tc-mips.c:9987
 msgid "extended operand requested but not required"
 msgstr "se solicitó un operando extendido pero no es necesario"
 
-#: config/tc-mips.c:9914
+#: config/tc-mips.c:9989
 msgid "invalid unextended operand value"
 msgstr "valor de operando no extendido inválido"
 
-#: config/tc-mips.c:9942
+#: config/tc-mips.c:10017
 msgid "operand value out of range for instruction"
 msgstr "el valor del operando está fuera de rango por la instrucción"
 
-#: config/tc-mips.c:10340
+#: config/tc-mips.c:10469
 #, c-format
 msgid "A different %s was already specified, is now %s"
 msgstr "Ya se había especificado un %s diferente, ahora es %s"
 
-#: config/tc-mips.c:10501
-msgid "-G may not be used with embedded PIC code"
-msgstr "-G no se puede utilizar con código PIC imbuído"
-
-#: config/tc-mips.c:10530
+#: config/tc-mips.c:10689
 msgid "-call_shared is supported only for ELF format"
 msgstr "-call_shared sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10537 config/tc-mips.c:11848 config/tc-mips.c:12086
+#: config/tc-mips.c:10696 config/tc-mips.c:10725 config/tc-mips.c:11834
+#: config/tc-mips.c:12060
 msgid "-G may not be used with SVR4 PIC code"
 msgstr "-G no se puede utilizar con código PIC de SVR4"
 
-#: config/tc-mips.c:10546
+#: config/tc-mips.c:10705
 msgid "-non_shared is supported only for ELF format"
 msgstr "-non_shared sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10564
-msgid "-G is not supported for this configuration"
-msgstr "-G no tiene soporte para esta configuración"
-
-#: config/tc-mips.c:10569
-msgid "-G may not be used with SVR4 or embedded PIC code"
-msgstr "-G no se puede utilizar con código PIC de SVR4 o imbuído"
-
-#: config/tc-mips.c:10583
+#: config/tc-mips.c:10736
 msgid "-32 is supported for ELF format only"
 msgstr "-32 sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10592
+#: config/tc-mips.c:10745
 msgid "-n32 is supported for ELF format only"
 msgstr "-n32 sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10601
+#: config/tc-mips.c:10754
 msgid "-64 is supported for ELF format only"
 msgstr "-64 sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10606 config/tc-mips.c:10643
+#: config/tc-mips.c:10759 config/tc-mips.c:10796
 msgid "No compiled in support for 64 bit object file format"
 msgstr "No se compiló el soporte para el formato de fichero objeto de 64 bit"
 
-#: config/tc-mips.c:10630
+#: config/tc-mips.c:10783
 msgid "-mabi is supported for ELF format only"
 msgstr "-mabi sólo tiene soporte para el formato ELF"
 
-#: config/tc-mips.c:10650
+#: config/tc-mips.c:10803
 #, c-format
 msgid "invalid abi -mabi=%s"
 msgstr "interruptor abi -mabi=%s inválido"
 
-#: config/tc-mips.c:10717
+#: config/tc-mips.c:10877
 msgid "-G not supported in this configuration."
 msgstr "-G no tiene soporte en esta configuración."
 
-#: config/tc-mips.c:10743
+#: config/tc-mips.c:10903
 #, c-format
 msgid "-%s conflicts with the other architecture options, which imply -%s"
 msgstr "-%s tiene conflictos con las otras opciones de arquitectura, las cuales implican -%s"
 
-#: config/tc-mips.c:10774
+#: config/tc-mips.c:10934
 msgid "-mgp64 used with a 32-bit processor"
 msgstr "Se utilizó -mgp64 con un procesador de 32-bit"
 
-#: config/tc-mips.c:10776
+#: config/tc-mips.c:10936
 msgid "-mgp32 used with a 64-bit ABI"
 msgstr "se utilizó -mgp32 con un ABI de 64-bit"
 
-#: config/tc-mips.c:10778
+#: config/tc-mips.c:10938
 msgid "-mgp64 used with a 32-bit ABI"
 msgstr "se utilizó -mgp64 con un ABI de 32-bit"
 
-#: config/tc-mips.c:10808
+#: config/tc-mips.c:10968
 msgid "trap exception not supported at ISA 1"
 msgstr "la excepciónd de trampa no tiene soporte en ISA 1"
 
-#: config/tc-mips.c:10956
-#, c-format
-msgid "Unmatched %%hi reloc"
-msgstr "Reubicación %%hi sin coincidencia"
-
-#: config/tc-mips.c:11048
+#: config/tc-mips.c:11229
 msgid "Cannot branch to undefined symbol."
 msgstr "No se puede ramificar hacia un símbolo indefinido."
 
-#: config/tc-mips.c:11055
+#: config/tc-mips.c:11236
 msgid "Cannot branch to symbol in another section."
 msgstr "No se puede ramificar hacia un símbolo en otra sección."
 
-#: config/tc-mips.c:11064
+#: config/tc-mips.c:11245
 msgid "Pretending global symbol used as branch target is local."
 msgstr "Pretender que se use un símbolo global como objetivo de ramificación es local."
 
-#: config/tc-mips.c:11229
-msgid "Invalid PC relative reloc"
-msgstr "Reubicación relativa al PC inválida"
-
-#: config/tc-mips.c:11324 config/tc-sparc.c:3185 config/tc-sparc.c:3192
-#: config/tc-sparc.c:3199 config/tc-sparc.c:3206 config/tc-sparc.c:3213
-#: config/tc-sparc.c:3222 config/tc-sparc.c:3233 config/tc-sparc.c:3255
-#: config/tc-sparc.c:3279 write.c:998 write.c:1070
+#: config/tc-mips.c:11402 config/tc-sparc.c:3229 config/tc-sparc.c:3236
+#: config/tc-sparc.c:3243 config/tc-sparc.c:3250 config/tc-sparc.c:3257
+#: config/tc-sparc.c:3266 config/tc-sparc.c:3277 config/tc-sparc.c:3299
+#: config/tc-sparc.c:3323 write.c:861 write.c:933
 msgid "relocation overflow"
 msgstr "desbordamiento de reubicación"
 
-#: config/tc-mips.c:11334
+#: config/tc-mips.c:11412
 #, c-format
 msgid "Branch to odd address (%lx)"
 msgstr "Ramificación a una dirección impar (%lx)"
 
-#: config/tc-mips.c:11383
+#: config/tc-mips.c:11461
 msgid "Branch out of range"
 msgstr "Ramificación fuera de rango"
 
-#: config/tc-mips.c:11490
-#, c-format
-msgid "%08lx  UNDEFINED\n"
-msgstr "%08lx  SIN DEFINIR\n"
-
-#: config/tc-mips.c:11549
+#: config/tc-mips.c:11540
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr "Alineación demasiado grande: se asume %d."
 
-#: config/tc-mips.c:11552
+#: config/tc-mips.c:11543
 msgid "Alignment negative: 0 assumed."
 msgstr "Alineación negativa: se asume 0."
 
-#: config/tc-mips.c:11639
-msgid "No read only data section in this object file format"
-msgstr "No hay sección de datos de sólo lectura en este formato de fichero objeto"
-
-#: config/tc-mips.c:11662
-msgid "Global pointers not supported; recompile -G 0"
-msgstr "Los apuntadores globales no tienen soporte; recompile -G 0"
-
-#: config/tc-mips.c:11804
+#: config/tc-mips.c:11780
 #, c-format
 msgid "%s: no such section"
 msgstr "%s: no existe la sección"
 
-#: config/tc-mips.c:11843
+#: config/tc-mips.c:11829
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ".option pic%d no tiene soporte"
 
-#: config/tc-mips.c:11854
+#: config/tc-mips.c:11840
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr "Opción \"%s\" no reconocida"
 
-#: config/tc-mips.c:11916
+#: config/tc-mips.c:11893
 msgid "`noreorder' must be set before `nomacro'"
 msgstr "se debe establecer `noreorder' antes de `nomacro'"
 
-#: config/tc-mips.c:11988
+#: config/tc-mips.c:11952
 #, c-format
 msgid "unknown architecture %s"
 msgstr "arquitectura %s desconocida"
 
-#: config/tc-mips.c:11996 config/tc-mips.c:12017
+#: config/tc-mips.c:11965 config/tc-mips.c:11995
 #, c-format
 msgid "unknown ISA level %s"
 msgstr "nivel ISA %s desconocido"
 
-#: config/tc-mips.c:12045
+#: config/tc-mips.c:11973
+#, c-format
+msgid "unknown ISA or architecture %s"
+msgstr "ISA o arquitectura %s desconocidos"
+
+#: config/tc-mips.c:12023
 msgid ".set pop with no .set push"
 msgstr ".set pop sin .set push"
 
-#: config/tc-mips.c:12069
+#: config/tc-mips.c:12044
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr "Se trató de establecer el símbolo no reconocido: %s\n"
 
-#: config/tc-mips.c:12119
+#: config/tc-mips.c:12102
 msgid ".cpload not in noreorder section"
 msgstr ".cpload no está en la sección noreorder"
 
-#: config/tc-mips.c:12175 config/tc-mips.c:12194
+#: config/tc-mips.c:12171 config/tc-mips.c:12190
 msgid "missing argument separator ',' for .cpsetup"
 msgstr "falta el separador de argumentos ',' para .cpsetup"
 
-#: config/tc-mips.c:12372
+#: config/tc-mips.c:12380
 msgid "Unsupported use of .gpword"
 msgstr "Uso sin soporte de .gpword"
 
-#: config/tc-mips.c:12408
+#: config/tc-mips.c:12416
 msgid "Unsupported use of .gpdword"
 msgstr "Uso sin soporte de .gpdword"
 
-#: config/tc-mips.c:12543
+#: config/tc-mips.c:12548
 msgid "expected `$'"
 msgstr "se esperaba `$'"
 
-#: config/tc-mips.c:12551
+#: config/tc-mips.c:12556
 msgid "Bad register number"
 msgstr "Número de registro erróneo"
 
-#: config/tc-mips.c:12599
+#: config/tc-mips.c:12604
 msgid "Unrecognized register name"
 msgstr "Nombre de registro no reconocido"
 
-#: config/tc-mips.c:12834
+#: config/tc-mips.c:12837
 msgid "unsupported PC relative reference to different section"
 msgstr "referencia relativa al PC sin soporte a una sección diferente"
 
-#: config/tc-mips.c:12947
+#: config/tc-mips.c:12950 config/tc-xtensa.c:1593 config/tc-xtensa.c:1804
 msgid "unsupported relocation"
 msgstr "reubicación sin soporte"
 
-#: config/tc-mips.c:13062
-msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
-msgstr "se utilizó AT después de \".set noat\" o se utilizó una macro después de \".set nomacro\""
-
-#: config/tc-mips.c:13125
-msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
-msgstr "Revise dos veces fx_r_type en tc-mips.c:tc_gen_reloc"
-
-#: config/tc-mips.c:13340 config/tc-sh.c:3800
+#: config/tc-mips.c:13158
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr "No se puede representar la reubicación %s en este formato de fichero objeto"
 
-#: config/tc-mips.c:13429
+#: config/tc-mips.c:13244
 msgid "relaxed out-of-range branch into a jump"
 msgstr "ramificación relajada fuera de rango en un salto"
 
-#: config/tc-mips.c:13902
+#: config/tc-mips.c:13766
 msgid "missing .end at end of assembly"
 msgstr "falta un .end al final del ensamblado"
 
-#: config/tc-mips.c:13917
+#: config/tc-mips.c:13781
 msgid "expected simple number"
 msgstr "se esperaba un número simple"
 
-#: config/tc-mips.c:13943
+#: config/tc-mips.c:13807
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr " *input_line_pointer == '%c' 0x%02x\n"
 
-#: config/tc-mips.c:13945
+#: config/tc-mips.c:13809
 msgid "invalid number"
 msgstr "número inválido"
 
-#: config/tc-mips.c:14018
+#: config/tc-mips.c:13882
 msgid ".end not in text section"
 msgstr ".end no está en la sección text"
 
-#: config/tc-mips.c:14022
+#: config/tc-mips.c:13886
 msgid ".end directive without a preceding .ent directive."
 msgstr "directiva .end sin una directiva .ent precedente."
 
-#: config/tc-mips.c:14031
+#: config/tc-mips.c:13895
 msgid ".end symbol does not match .ent symbol."
 msgstr "el símbolo .end no coincide con el símbolo .ent."
 
-#: config/tc-mips.c:14038
+#: config/tc-mips.c:13902
 msgid ".end directive missing or unknown symbol"
 msgstr "falta la directiva .end o hay un símbolo desconocido"
 
-#: config/tc-mips.c:14098
+#: config/tc-mips.c:13978
 msgid ".ent or .aent not in text section."
 msgstr ".ent o .aent no están en la sección text."
 
-#: config/tc-mips.c:14101
+#: config/tc-mips.c:13981
 msgid "missing .end"
 msgstr "falta un .end"
 
-#: config/tc-mips.c:14153
+#: config/tc-mips.c:14033
 msgid "Bad .frame directive"
 msgstr "Directiva .frame errónea"
 
-#: config/tc-mips.c:14185
+#: config/tc-mips.c:14065
 msgid ".mask/.fmask outside of .ent"
 msgstr ".mask/.fmask fuera de .ent"
 
-#: config/tc-mips.c:14192
+#: config/tc-mips.c:14072
 msgid "Bad .mask/.fmask directive"
 msgstr "Directiva .mask/.fmask errónea"
 
-#: config/tc-mips.c:14470
+#: config/tc-mips.c:14337
+#, c-format
 msgid ""
 "MIPS options:\n"
-"-membedded-pic\t\tgenerate embedded position independent code\n"
 "-EB\t\t\tgenerate big endian output\n"
 "-EL\t\t\tgenerate little endian output\n"
 "-g, -g2\t\t\tdo not remove unneeded NOPs or swap branches\n"
@@ -6916,14 +7474,14 @@ msgid ""
 "\t\t\timplicitly with the gp register [default 8]\n"
 msgstr ""
 "Opciones MIPS:\n"
-"-membedded-pic\t\tgenera código independiente de posición imbuído\n"
 "-EB\t\t\tgenera salida big endian\n"
 "-EL\t\t\tgenera salida little endian\n"
 "-g, -g2\t\t\tno borra NOPs innecesarios o intercambia ramificaciones\n"
 "-G NUM\t\t\tpermite la referencia a objetos hasta NUM bytes\n"
-"\t\t\timplícitamente con el registro gp [por omisión 8]\n"
+"\t\t\timplícitamente con el registro gp [por defecto 8]\n"
 
-#: config/tc-mips.c:14478
+#: config/tc-mips.c:14344
+#, c-format
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
 "-mips2\t\t\tgenerate MIPS ISA II instructions\n"
@@ -6933,6 +7491,7 @@ msgid ""
 "-mips32                 generate MIPS32 ISA instructions\n"
 "-mips32r2               generate MIPS32 release 2 ISA instructions\n"
 "-mips64                 generate MIPS64 ISA instructions\n"
+"-mips64r2               generate MIPS64 release 2 ISA instructions\n"
 "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
 msgstr ""
 "-mips1\t\t\tgenera instrucciones MIPS ISA I\n"
@@ -6943,9 +7502,10 @@ msgstr ""
 "-mips32                 genera instrucciones MIPS32 ISA\n"
 "-mips32r2               genera instrucciones MIPS32 versión 2 ISA\n"
 "-mips64                 genera instrucciones MIPS64 ISA\n"
-"-mcpu=CPU/-mtune=CPU\tgenera código/calendarización para el CPU, donde CPU es uno de:\n"
+"-march=CPU/-mtune=CPU\tgenera código/calendarización para el CPU, donde CPU es uno de:\n"
 
-#: config/tc-mips.c:14496
+#: config/tc-mips.c:14363
+#, c-format
 msgid ""
 "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
 "-no-mCPU\t\tdon't generate code specific to CPU.\n"
@@ -6955,7 +7515,8 @@ msgstr ""
 "-no-mCPU\t\tno genera código específico para el CPU.\n"
 "\t\t\tPara -mCPU y -no-mCPU, CPU debe ser uno de:\n"
 
-#: config/tc-mips.c:14509
+#: config/tc-mips.c:14376
+#, c-format
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
@@ -6963,52 +7524,88 @@ msgstr ""
 "-mips16\t\t\tgenera instrucciones mips16\n"
 "-no-mips16\t\tno genera instrucciones mips16\n"
 
-#: config/tc-mips.c:14512
+#: config/tc-mips.c:14379
+#, c-format
+msgid ""
+"-mdsp\t\t\tgenerate DSP instructions\n"
+"-mno-dsp\t\tdo not generate DSP instructions\n"
+msgstr ""
+"-mdsp\t\t\tgenera instrucciones DSP\n"
+"-mno-dsp\t\tno genera instrucciones DSP\n"
+
+#: config/tc-mips.c:14382
+#, c-format
+msgid ""
+"-mmt\t\t\tgenerate MT instructions\n"
+"-mno-mt\t\t\tdo not generate MT instructions\n"
+msgstr ""
+"-mmt\t\t\tgenera instrucciones MT\n"
+"-mno-mt\t\tno genera instrucciones MT\n"
+
+#: config/tc-mips.c:14385
+#, c-format
 msgid ""
+"-mfix-vr4120\t\twork around certain VR4120 errata\n"
+"-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n"
 "-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n"
 "-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n"
+"-mno-shared\t\toptimize output for executables\n"
+"-msym32\t\t\tassume all symbols have 32-bit values\n"
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
-"-n\t\t\twarn about NOPs generated from macros\n"
 "--[no-]construct-floats [dis]allow floating point values to be constructed\n"
 "--trap, --no-break\ttrap exception on div by 0 and mult overflow\n"
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
 msgstr ""
+"-mfix-vr4120\t\tevita ciertos errores de VR4120\n"
+"-mfix-vr4130\t\tevita los errores mflo/mfhi de VR4130\n"
 "-mgp32\t\t\tusa GPRs de 32-bit, sin importar el ISA escogido\n"
 "-mfp32\t\t\tusa FPRS de 32-bit, sin importar el ISA escogido\n"
+"-mno-shared\t\toptimiza la salida para ejecutables\n"
+"-msym32\t\t\tasume que todos los símbolos tiene valores de 32-bit\n"
 "-O0\t\t\telimina NOPs innecesarios, no intercambia ramificaciones\n"
 "-O\t\t\telimina NOPs innecesarios e intercambia ramificaciones\n"
 "--[no-]construct-floats [des]activa los valores de coma flotante a ser construídos\n"
 "--trap, --no-break\texcepción de trampa en div por 0 y desbordamiento de mult\n"
 "--break, --no-trap\texcepción de interrupción en div por 0 y desbordamiento de mult\n"
 
-#: config/tc-mips.c:14522
+#: config/tc-mips.c:14398
+#, c-format
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
 "-xgot\t\t\tassume a 32 bit GOT\n"
+"-mpdr, -mno-pdr\t\tenable/disable creation of .pdr sections\n"
+"-mshared, -mno-shared   disable/enable .cpload optimization for\n"
+"                        non-shared code\n"
 "-mabi=ABI\t\tcreate ABI conformant object file for:\n"
 msgstr ""
 "-KPIC, -call_shared\tgenera código SVR4 independiente de posición\n"
 "-non_shared\t\tno genera código independiente de posición\n"
 "-xgot\t\t\tasume un GOT de 32 bit\n"
+"-mpdr, -mno-pdr\t\tactiva/desactiva la creación de secciones .pdr\n"
+"-mshared, -mno-shared   desactiva/activa la optimización .cpload para\n"
+"                        código que no es compartido\n"
 "-mabi=ABI\t\tcrea un fichero objeto que cumple con el ABI para:\n"
 
-#: config/tc-mips.c:14538
+#: config/tc-mips.c:14417
+#, c-format
 msgid ""
 "-32\t\t\tcreate o32 ABI object file (default)\n"
 "-n32\t\t\tcreate n32 ABI object file\n"
 "-64\t\t\tcreate 64 ABI object file\n"
 msgstr ""
-"-32\t\t\tcrea ficheros objeto ABI o32 (por omisión)\n"
+"-32\t\t\tcrea ficheros objeto ABI o32 (por defecto)\n"
 "-n32\t\t\tcrea ficheros objeto ABI o32\n"
 "-64\t\t\tcrea ficheros objeto ABI 64\n"
 
-#: config/tc-mmix.c:677
+#: config/tc-mmix.c:694
+#, c-format
 msgid " MMIX-specific command line options:\n"
 msgstr "Opciones de la línea de comandos específicas de MMIX:\n"
 
-#: config/tc-mmix.c:678
+#: config/tc-mmix.c:695
+#, c-format
 msgid ""
 "  -fixed-special-register-names\n"
 "                          Allow only the original special register names.\n"
@@ -7016,19 +7613,23 @@ msgstr ""
 "  -fixed-special-register-names\n"
 "                          Sólo permite los nombres de registros especiales originales.\n"
 
-#: config/tc-mmix.c:681
+#: config/tc-mmix.c:698
+#, c-format
 msgid "  -globalize-symbols      Make all symbols global.\n"
 msgstr "  -globalize-symbols      Hace que todos los símbolos sean globales.\n"
 
-#: config/tc-mmix.c:683
+#: config/tc-mmix.c:700
+#, c-format
 msgid "  -gnu-syntax             Turn off mmixal syntax compatibility.\n"
 msgstr "  -gnu-syntax             Desactiva la compatibilidad con la sintaxis mmixal.\n"
 
-#: config/tc-mmix.c:685
+#: config/tc-mmix.c:702
+#, c-format
 msgid "  -relax                  Create linker relaxable code.\n"
 msgstr "  -relax                  Crea código relajable para el enlazador.\n"
 
-#: config/tc-mmix.c:687
+#: config/tc-mmix.c:704
+#, c-format
 msgid ""
 "  -no-predefined-syms     Do not provide mmixal built-in constants.\n"
 "                          Implies -fixed-special-register-names.\n"
@@ -7036,7 +7637,8 @@ msgstr ""
 "  -no-predefined-syms     No provee las constantes internas de mmixal.\n"
 "                          Implica -fixed-special-register-names.\n"
 
-#: config/tc-mmix.c:690
+#: config/tc-mmix.c:707
+#, c-format
 msgid ""
 "  -no-expand              Do not expand GETA, branches, PUSHJ or JUMP\n"
 "                          into multiple instructions.\n"
@@ -7044,15 +7646,18 @@ msgstr ""
 "  -no-expand              No expande GETA, ramificaciones, PUSHJ ó JUMP\n"
 "                          a instrucciones múltiples.\n"
 
-#: config/tc-mmix.c:693
+#: config/tc-mmix.c:710
+#, c-format
 msgid "  -no-merge-gregs         Do not merge GREG definitions with nearby values.\n"
 msgstr "  -no-merge-gregs         No mezcla las definiciones GREG con los valores cercanos.\n"
 
-#: config/tc-mmix.c:695
+#: config/tc-mmix.c:712
+#, c-format
 msgid "  -linker-allocated-gregs If there's no suitable GREG definition for the                          operands of an instruction, let the linker resolve.\n"
 msgstr "  -linker-allocated-gregs Si no hay una definición GREG adecuada para                          los operandos de una instrucción, dejar resolver al enlazador.\n"
 
-#: config/tc-mmix.c:698
+#: config/tc-mmix.c:715
+#, c-format
 msgid ""
 "  -x                      Do not warn when an operand to GETA, a branch,\n"
 "                          PUSHJ or JUMP is not known to be within range.\n"
@@ -7064,185 +7669,185 @@ msgstr ""
 "                          del rango. El enlazador atrapará cualquier error.\n"
 "                          Implica -linker-allocated-gregs."
 
-#: config/tc-mmix.c:825
+#: config/tc-mmix.c:841
 #, c-format
 msgid "unknown opcode: `%s'"
 msgstr "código de operación desconocido: `%s'"
 
-#: config/tc-mmix.c:947 config/tc-mmix.c:962
+#: config/tc-mmix.c:963 config/tc-mmix.c:978
 msgid "specified location wasn't TETRA-aligned"
 msgstr "la ubicación especificada no estaba TETRA alineada"
 
-#: config/tc-mmix.c:949 config/tc-mmix.c:964 config/tc-mmix.c:4015
-#: config/tc-mmix.c:4031
+#: config/tc-mmix.c:965 config/tc-mmix.c:980 config/tc-mmix.c:4124
+#: config/tc-mmix.c:4140
 msgid "unaligned data at an absolute location is not supported"
 msgstr "los datos sin alinear en una ubicación absoluta no tienen soporte"
 
-#: config/tc-mmix.c:1074
+#: config/tc-mmix.c:1090
 #, c-format
 msgid "invalid operand to opcode %s: `%s'"
 msgstr "operandos inválidos para el código de operación %s: `%s'"
 
-#: config/tc-mmix.c:1096 config/tc-mmix.c:1123 config/tc-mmix.c:1156
-#: config/tc-mmix.c:1164 config/tc-mmix.c:1181 config/tc-mmix.c:1209
-#: config/tc-mmix.c:1230 config/tc-mmix.c:1255 config/tc-mmix.c:1303
-#: config/tc-mmix.c:1401 config/tc-mmix.c:1426 config/tc-mmix.c:1458
-#: config/tc-mmix.c:1490 config/tc-mmix.c:1520 config/tc-mmix.c:1573
-#: config/tc-mmix.c:1590 config/tc-mmix.c:1617 config/tc-mmix.c:1645
-#: config/tc-mmix.c:1672 config/tc-mmix.c:1698 config/tc-mmix.c:1714
-#: config/tc-mmix.c:1740 config/tc-mmix.c:1756 config/tc-mmix.c:1772
-#: config/tc-mmix.c:1835 config/tc-mmix.c:1851
+#: config/tc-mmix.c:1112 config/tc-mmix.c:1139 config/tc-mmix.c:1172
+#: config/tc-mmix.c:1180 config/tc-mmix.c:1197 config/tc-mmix.c:1225
+#: config/tc-mmix.c:1246 config/tc-mmix.c:1271 config/tc-mmix.c:1319
+#: config/tc-mmix.c:1417 config/tc-mmix.c:1442 config/tc-mmix.c:1474
+#: config/tc-mmix.c:1506 config/tc-mmix.c:1536 config/tc-mmix.c:1589
+#: config/tc-mmix.c:1606 config/tc-mmix.c:1633 config/tc-mmix.c:1661
+#: config/tc-mmix.c:1688 config/tc-mmix.c:1714 config/tc-mmix.c:1730
+#: config/tc-mmix.c:1756 config/tc-mmix.c:1772 config/tc-mmix.c:1788
+#: config/tc-mmix.c:1851 config/tc-mmix.c:1867
 #, c-format
 msgid "invalid operands to opcode %s: `%s'"
 msgstr "operandos inválidos para el código de operación %s: `%s'"
 
-#: config/tc-mmix.c:1828
+#: config/tc-mmix.c:1844
 #, c-format
 msgid "unsupported operands to %s: `%s'"
 msgstr "operandos sin soporte para %s: `%s'"
 
-#: config/tc-mmix.c:1956
+#: config/tc-mmix.c:1969
 msgid "internal: mmix_prefix_name but empty prefix"
 msgstr "interno: hay un mmix_prefix_name pero es un prefijo vacío"
 
-#: config/tc-mmix.c:2001
+#: config/tc-mmix.c:2013
 #, c-format
 msgid "too many GREG registers allocated (max %d)"
 msgstr "se asignaron demasiados registros GREG (máximo %d)"
 
-#: config/tc-mmix.c:2061
+#: config/tc-mmix.c:2071
 msgid "BSPEC already active.  Nesting is not supported."
 msgstr "BSPEC ya está activo.  El anidamiento no tiene soporte."
 
-#: config/tc-mmix.c:2070
+#: config/tc-mmix.c:2080
 msgid "invalid BSPEC expression"
 msgstr "expresión BSPEC inválida"
 
-#: config/tc-mmix.c:2086
+#: config/tc-mmix.c:2096
 #, c-format
 msgid "can't create section %s"
 msgstr "no se puede crear la sección %s"
 
-#: config/tc-mmix.c:2091
+#: config/tc-mmix.c:2101
 #, c-format
 msgid "can't set section flags for section %s"
 msgstr "no se pueden establecer las opciones para la sección %s"
 
-#: config/tc-mmix.c:2113
+#: config/tc-mmix.c:2122
 msgid "ESPEC without preceding BSPEC"
 msgstr "ESPEC sin un BSPEC precedente"
 
-#: config/tc-mmix.c:2143
+#: config/tc-mmix.c:2151
 msgid "missing local expression"
 msgstr "falta una expresión local"
 
-#: config/tc-mmix.c:2363
+#: config/tc-mmix.c:2389
 msgid "operand out of range, instruction expanded"
 msgstr "el operando está fuera de rango, se expande la instrucción"
 
 #. The BFD_RELOC_MMIX_LOCAL-specific message is supposed to be
 #. user-friendly, though a little bit non-substantial.
-#: config/tc-mmix.c:2620
+#: config/tc-mmix.c:2640
 msgid "directive LOCAL must be placed in code or data"
 msgstr "la directiva LOCAL debe estar colocada en el código o en los datos"
 
-#: config/tc-mmix.c:2621
+#: config/tc-mmix.c:2641
 msgid "internal confusion: relocation in a section without contents"
 msgstr "confusión interna: reubiación en una sección sin contenido"
 
-#: config/tc-mmix.c:2734
+#: config/tc-mmix.c:2755
 msgid "internal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to section"
 msgstr "interno: BFD_RELOC_MMIX_BASE_PLUS_OFFSET no resuelve a la sección"
 
-#: config/tc-mmix.c:2782
+#: config/tc-mmix.c:2803
 msgid "no suitable GREG definition for operands"
 msgstr "no hay una definición GREG adecuada para los operandos"
 
-#: config/tc-mmix.c:2841
+#: config/tc-mmix.c:2862
 msgid "operands were not reducible at assembly-time"
 msgstr "los operandos no son reducibles en el momento del ensamblado"
 
-#: config/tc-mmix.c:2868
+#: config/tc-mmix.c:2889
 #, c-format
 msgid "cannot generate relocation type for symbol %s, code %s"
 msgstr "no se puede generar el tipo de reubicación para el símbolo %s, código %s"
 
-#: config/tc-mmix.c:2888
+#: config/tc-mmix.c:2909
 #, c-format
 msgid "internal: unhandled label %s"
 msgstr "interno: etiqueta %s sin manejar"
 
-#: config/tc-mmix.c:2942
+#: config/tc-mmix.c:2939
 msgid "[0-9]H labels may not appear alone on a line"
 msgstr "las etiquetas [0-9]H no pueden aparecer solas en una línea"
 
-#: config/tc-mmix.c:2951
+#: config/tc-mmix.c:2948
 msgid "[0-9]H labels do not mix with dot-pseudos"
 msgstr "las etiquetas [0-9]H no se mezclan con pseudo-puntos"
 
-#: config/tc-mmix.c:3015
+#: config/tc-mmix.c:3036
 msgid "invalid characters in input"
 msgstr "caracteres inválidos en la entrada"
 
-#: config/tc-mmix.c:3119
+#: config/tc-mmix.c:3140
 msgid "empty label field for IS"
 msgstr "campo de etiqueta vacío para IS"
 
-#: config/tc-mmix.c:3344
+#: config/tc-mmix.c:3466
 #, c-format
 msgid "internal: unexpected relax type %d:%d"
 msgstr "interno: tipo de relajación inesperado %d:%d"
 
-#: config/tc-mmix.c:3366
+#: config/tc-mmix.c:3488
 msgid "BSPEC without ESPEC."
 msgstr "BSPEC sin un ESPEC."
 
-#: config/tc-mmix.c:3568
+#: config/tc-mmix.c:3688
 msgid "GREG expression too complicated"
 msgstr "expresión GREG demasiado complicada"
 
-#: config/tc-mmix.c:3583
+#: config/tc-mmix.c:3703
 msgid "internal: GREG expression not resolved to section"
 msgstr "interno: la expresión GREG no resuelva a la sección"
 
-#: config/tc-mmix.c:3634
+#: config/tc-mmix.c:3752
 msgid "register section has contents\n"
 msgstr "la sección de registros tiene contenido\n"
 
-#: config/tc-mmix.c:3768
+#: config/tc-mmix.c:3879
 msgid "section change from within a BSPEC/ESPEC pair is not supported"
 msgstr "el cambio de sección desde dentro de una pareja BSPEC/ESPEC no tiene soporte"
 
-#: config/tc-mmix.c:3790
+#: config/tc-mmix.c:3900
 msgid "directive LOC from within a BSPEC/ESPEC pair is not supported"
 msgstr "una directiva LOC desde dentro de una pareja BSPEC/ESPEC no tiene soporte"
 
-#: config/tc-mmix.c:3801
+#: config/tc-mmix.c:3911
 msgid "invalid LOC expression"
 msgstr "expresión LOC inválida"
 
-#: config/tc-mmix.c:3826 config/tc-mmix.c:3852
+#: config/tc-mmix.c:3936 config/tc-mmix.c:3962
 msgid "LOC expression stepping backwards is not supported"
 msgstr "el paso hacia atrás de una expresión LOC no tiene soporte"
 
 #. We will only get here in rare cases involving #NO_APP,
 #. where the unterminated string is not recognized by the
 #. preformatting pass.
-#: config/tc-mmix.c:3936 config/tc-mmix.c:4097
+#: config/tc-mmix.c:4046 config/tc-mmix.c:4206
 msgid "unterminated string"
 msgstr "cadena sin terminar"
 
-#: config/tc-mmix.c:3953
+#: config/tc-mmix.c:4063
 msgid "BYTE expression not a pure number"
 msgstr "la expresión BYTE no es un número puro"
 
 #. Note that mmixal does not allow negative numbers in
 #. BYTE sequences, so neither should we.
-#: config/tc-mmix.c:3962
+#: config/tc-mmix.c:4072
 msgid "BYTE expression not in the range 0..255"
 msgstr "la expresión BYTE no está en el rango 0..255"
 
-#: config/tc-mmix.c:4013 config/tc-mmix.c:4029
+#: config/tc-mmix.c:4122 config/tc-mmix.c:4138
 msgid "data item with alignment larger than location"
 msgstr "elemento de datos con una alineación más grande que la ubicación"
 
@@ -7252,7 +7857,8 @@ msgstr "elemento de datos con una alineación más grande que la ubicación"
 msgid "`&' serial number operator is not supported"
 msgstr "el operador de número serial `&' no tiene soporte"
 
-#: config/tc-mn10200.c:319
+#: config/tc-mn10200.c:305
+#, c-format
 msgid ""
 "MN10200 options:\n"
 "none yet\n"
@@ -7260,30 +7866,20 @@ msgstr ""
 "Opciones MN10200:\n"
 "ninguna aún\n"
 
-#: config/tc-mn10200.c:793 config/tc-mn10300.c:1387 config/tc-ppc.c:2088
-#: config/tc-s390.c:1540 config/tc-v850.c:1678
+#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2135
+#: config/tc-s390.c:1557 config/tc-v850.c:1621
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr "Código de operación no reconocido: `%s'"
 
-#: config/tc-mn10200.c:1036 config/tc-mn10300.c:1960 config/tc-ppc.c:2566
-#: config/tc-s390.c:1455 config/tc-v850.c:2101
+#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2614
+#: config/tc-s390.c:1472 config/tc-v850.c:2026
 #, c-format
 msgid "junk at end of line: `%s'"
 msgstr "basura al final de la línea: `%s'"
 
-#: config/tc-mn10200.c:1242 write.c:2691
+#: config/tc-mn10300.c:695
 #, c-format
-msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
-msgstr "no se puede resolver `%s' {sección %s} - `%s' {sección %s}"
-
-#: config/tc-mn10200.c:1347 config/tc-mn10300.c:2589 config/tc-ppc.c:1426
-#: config/tc-v850.c:1607
-#, c-format
-msgid "operand out of range (%s not between %ld and %ld)"
-msgstr "operando fuera de rango (%s no está entre %ld y %ld)"
-
-#: config/tc-mn10300.c:690
 msgid ""
 "MN10300 options:\n"
 "none yet\n"
@@ -7291,35 +7887,57 @@ msgstr ""
 "Opciones de MN10300:\n"
 "ninguna aún\n"
 
-#: config/tc-mn10300.c:1356 config/tc-sh.c:805 config/tc-xtensa.c:5177
-#: read.c:3764
+#: config/tc-mn10300.c:1361 config/tc-sh.c:778 read.c:3871
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr "tamaño de reubicación BFD %u sin soporte"
 
-#: config/tc-mn10300.c:1404
+#: config/tc-mn10300.c:1409
 msgid "Invalid opcode/operands"
 msgstr "Código de operación/operandos inválidos"
 
-#: config/tc-mn10300.c:1931
+#: config/tc-mn10300.c:1936
 msgid "Invalid register specification."
 msgstr "Especificación de registro inválida."
 
-#: config/tc-mn10300.c:2514
+#: config/tc-mn10300.c:2518
 #, c-format
 msgid "Bad relocation fixup type (%d)"
 msgstr "Tipo de compostura de reubicación inválido (%d)"
 
-#: config/tc-msp430.c:170
+#: config/tc-msp430.c:552
+msgid ".profiler pseudo requires at least two operands."
+msgstr "el seudo .profiler requiere por lo menos dos operandos."
+
+#: config/tc-msp430.c:611
+msgid "unknown profiling flag - ignored."
+msgstr "opción de perfilado desconocida - se ignora."
+
+#: config/tc-msp430.c:627
+msgid "ambigious flags combination - '.profiler' directive ignored."
+msgstr "combinación de opciones ambigua - se ignora la directiva '.profiler'."
+
+#: config/tc-msp430.c:637
+msgid "profiling in absolute section? Hm..."
+msgstr "¿perfilando en la sección absoluta? Hm..."
+
+#: config/tc-msp430.c:726
+#, c-format
 msgid "Known MCU names:\n"
 msgstr "Nombres MCU conocidos:\n"
 
-#: config/tc-msp430.c:173
+#: config/tc-msp430.c:729
 #, c-format
 msgid "\t %s\n"
 msgstr "\t %s\n"
 
-#: config/tc-msp430.c:183
+#: config/tc-msp430.c:755
+#, c-format
+msgid "redefinition of mcu type %s' to %s'"
+msgstr "redefinición del tipo de mcu %s' a %s'"
+
+#: config/tc-msp430.c:798
+#, c-format
 msgid ""
 "MSP430 options:\n"
 "  -mmcu=[msp430-name] select microcontroller type\n"
@@ -7333,10 +7951,14 @@ msgid ""
 "                  msp430x147  msp430x148  msp430x149\n"
 "                  msp430x155  msp430x156  msp430x157\n"
 "                  msp430x167  msp430x168  msp430x169\n"
+"                  msp430x1610 msp430x1611 msp430x1612\n"
 "                  msp430x311  msp430x312  msp430x313  msp430x314  msp430x315\n"
 "                  msp430x323  msp430x325\n"
 "                  msp430x336  msp430x337\n"
-"                  msp430x412  msp430x413\n"
+"                  msp430x412  msp430x413  msp430x415  msp430x417\n"
+"                  msp430xE423 msp430xE425 msp430E427\n"
+"                  msp430xW423 msp430xW425 msp430W427\n"
+"                  msp430xG437 msp430xG438 msp430G439\n"
 "                  msp430x435  msp430x436  msp430x437\n"
 "                  msp430x447  msp430x448  msp430x449\n"
 msgstr ""
@@ -7352,293 +7974,336 @@ msgstr ""
 "                  msp430x147  msp430x148  msp430x149\n"
 "                  msp430x155  msp430x156  msp430x157\n"
 "                  msp430x167  msp430x168  msp430x169\n"
+"                  msp430x1610 msp430x1611 msp430x1612\n"
 "                  msp430x311  msp430x312  msp430x313  msp430x314  msp430x315\n"
 "                  msp430x323  msp430x325\n"
 "                  msp430x336  msp430x337\n"
-"                  msp430x412  msp430x413\n"
+"                  msp430x412  msp430x413  msp430x415  msp430x417\n"
+"                  msp430xE423 msp430xE425 msp430E427\n"
+"                  msp430xW423 msp430xW425 msp430W427\n"
+"                  msp430xG437 msp430xG438 msp430G439\n"
 "                  msp430x435  msp430x436  msp430x437\n"
 "                  msp430x447  msp430x448  msp430x449\n"
 
-#: config/tc-msp430.c:263
-#, c-format
-msgid "redefinition of mcu type %s' to %s'"
-msgstr "redefinición del tipo de mcu %s' a %s'"
-
-#: config/tc-msp430.c:496
-#, c-format
-msgid "instruction %s requires %d operand(s)"
-msgstr "La instrucción %s requiere de %d operando(s)"
-
-#: config/tc-msp430.c:743
-#, c-format
-msgid "Even number required. Rounded to %d"
-msgstr "Se requiere un número par. Se redondea a %d"
-
-#: config/tc-msp430.c:754
-#, c-format
-msgid "Wrong displacement  %d"
-msgstr "Desubicación errónea  %d"
-
-#: config/tc-msp430.c:771
-msgid "instruction requires label sans '$'"
-msgstr "la instrucción requiere una etiqueta sin '$'"
-
-#: config/tc-msp430.c:777
-msgid "instruction requires label or value in range -511:512"
-msgstr "la instrucción requiere una etiqueta o valor en el rango -511:512"
-
-#: config/tc-msp430.c:783
-msgid "instruction requires label"
-msgstr "La instrucción requiere una etiqueta"
-
-#: config/tc-msp430.c:789
-msgid "Ilegal instruction or not implmented opcode."
-msgstr "Instrucción ilegal o código de operación no implementado."
-
-#: config/tc-msp430.c:817
+#: config/tc-msp430.c:821
 #, c-format
-msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
-msgstr "Bicho interno. Intente utilizar 0(r%d) en lugar de @r%d"
-
-#: config/tc-msp430.c:827
-msgid "this addressing mode is not applicable for destination operand"
-msgstr "Este modo de direccionamiento no se puede aplicar al operando destino"
+msgid ""
+"  -mQ - enable relaxation at assembly time. DANGEROUS!\n"
+"  -mP - enable polymorph instructions\n"
+msgstr ""
+"  -mQ - permite la relajación en tiempo de ensamblado. ¡PELIGROSO!\n"
+"  -mP - permite las instrucciones polimórficas\n"
 
-#: config/tc-msp430.c:944
+#: config/tc-msp430.c:1011
 #, c-format
-msgid "value %ld out of range. Use #lo() or #hi()"
-msgstr "el valor %ld está fuera de rango. Utilice #lo() o #hi()"
+msgid "value %d out of range. Use #lo() or #hi()"
+msgstr "el valor %d está fuera de rango. Utilice #lo() o #hi()"
 
-#: config/tc-msp430.c:1040
+#: config/tc-msp430.c:1099
 #, c-format
 msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
 msgstr "expresión desconocida en el operando %s. Utilice #llo() #lhi() #hlo() #hhi() "
 
-#: config/tc-msp430.c:1090 config/tc-msp430.c:1304
+#: config/tc-msp430.c:1150
+#, c-format
+msgid "Registers cannot be used within immediate expression [%s]"
+msgstr "Los registros no se pueden usar en la expresión inmediata [%s]"
+
+#: config/tc-msp430.c:1152
 #, c-format
 msgid "unknown operand %s"
 msgstr "operando %s desconocido"
 
-#: config/tc-msp430.c:1111 config/tc-msp430.c:1242
+#: config/tc-msp430.c:1174 config/tc-msp430.c:1309
 #, c-format
 msgid "value out of range: %d"
 msgstr "valor fuera de rango: %d"
 
-#: config/tc-msp430.c:1120 config/tc-msp430.c:1259
+#: config/tc-msp430.c:1185
+#, c-format
+msgid "Registers cannot be used within absolute expression [%s]"
+msgstr "Los registros no se pueden usar en la expresión absoluta [%s]"
+
+#: config/tc-msp430.c:1187 config/tc-msp430.c:1330
 #, c-format
 msgid "unknown expression in operand %s"
 msgstr "expresión desconocida en el operando %s"
 
-#: config/tc-msp430.c:1134 config/tc-msp430.c:1141
+#: config/tc-msp430.c:1201 config/tc-msp430.c:1208
 #, c-format
 msgid "unknown addressing mode %s"
 msgstr "modo de direccionamiento %s desconocido"
 
-#: config/tc-msp430.c:1149
+#: config/tc-msp430.c:1216
 #, c-format
 msgid "Bad register name r%s"
 msgstr "Nombre de registro r%s erróneo"
 
-#: config/tc-msp430.c:1161
+#: config/tc-msp430.c:1228
 #, c-format
 msgid "MSP430 does not have %d registers"
 msgstr "MSP430 no tiene %d registros"
 
-#: config/tc-msp430.c:1181
+#: config/tc-msp430.c:1248
 msgid "')' required"
 msgstr "se requiere ')'"
 
-#: config/tc-msp430.c:1194
+#: config/tc-msp430.c:1261
 #, c-format
 msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
 msgstr "operador %s desconocido. ¿ Quiere decir X(Rn) ó #[hl][hl][oi](CONST) ?"
 
-#: config/tc-msp430.c:1203
+#: config/tc-msp430.c:1270
 #, c-format
 msgid "unknown operator (r%s substituded as a register name"
 msgstr "operador desconocido (se sustituyó r%s como un nombre de registro"
 
-#: config/tc-msp430.c:1215 config/tc-msp430.c:1226
+#: config/tc-msp430.c:1282 config/tc-msp430.c:1293
 #, c-format
 msgid "unknown operator %s"
 msgstr "operador %s desconocido"
 
-#: config/tc-msp430.c:1220
+#: config/tc-msp430.c:1287
 msgid "r2 should not be used in indexed addressing mode"
 msgstr "no se debe usar r2 en el modo de direccionamiento indizado"
 
+#: config/tc-msp430.c:1328
+#, c-format
+msgid "Registers cannot be used as a prefix of indexed expression [%s]"
+msgstr "Los registros no se pueden usar en la expresión indizada [%s]"
+
 #. Unreachable.
-#: config/tc-msp430.c:1321
+#: config/tc-msp430.c:1377
 #, c-format
 msgid "unknown addressing mode for operand %s"
 msgstr "modo de direccionamiento desconocido para el operando %s"
 
-#: config/tc-ns32k.c:449
+#: config/tc-msp430.c:1402
+#, c-format
+msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
+msgstr "Bicho interno. Intente utilizar 0(r%d) en lugar de @r%d"
+
+#: config/tc-msp430.c:1412
+msgid "this addressing mode is not applicable for destination operand"
+msgstr "Este modo de direccionamiento no se puede aplicar al operando destino"
+
+#: config/tc-msp430.c:1456
+#, c-format
+msgid "instruction %s requires %d operand(s)"
+msgstr "La instrucción %s requiere de %d operando(s)"
+
+#: config/tc-msp430.c:1709
+#, c-format
+msgid "Even number required. Rounded to %d"
+msgstr "Se requiere un número par. Se redondea a %d"
+
+#: config/tc-msp430.c:1720
+#, c-format
+msgid "Wrong displacement  %d"
+msgstr "Desubicación errónea  %d"
+
+#: config/tc-msp430.c:1737
+msgid "instruction requires label sans '$'"
+msgstr "la instrucción requiere una etiqueta sin '$'"
+
+#: config/tc-msp430.c:1742
+msgid "instruction requires label or value in range -511:512"
+msgstr "la instrucción requiere una etiqueta o valor en el rango -511:512"
+
+#: config/tc-msp430.c:1749 config/tc-msp430.c:1793 config/tc-msp430.c:1832
+msgid "instruction requires label"
+msgstr "La instrucción requiere una etiqueta"
+
+#: config/tc-msp430.c:1757 config/tc-msp430.c:1799
+msgid "polymorphs are not enabled. Use -mP option to enable."
+msgstr "los polimórficos no están activados. Use la opción -mP para activar."
+
+#: config/tc-msp430.c:1836
+msgid "Ilegal instruction or not implmented opcode."
+msgstr "Instrucción ilegal o código de operación no implementado."
+
+#: config/tc-msp430.c:2187
+#, c-format
+msgid "internal inconsistency problem in %s: insn %04lx"
+msgstr "problema de inconsistencia interna en %s: insn %04lx"
+
+#: config/tc-msp430.c:2217 config/tc-msp430.c:2240
+#, c-format
+msgid "internal inconsistency problem in %s: ext. insn %04lx"
+msgstr "problema de inconsistencia interna en %s: ext. insn %04lx"
+
+#: config/tc-msp430.c:2252
+#, c-format
+msgid "internal inconsistency problem in %s:  %lx"
+msgstr "problema de inconsistencia interna en %s:  %lx"
+
+#: config/tc-ns32k.c:441
 msgid "Invalid syntax in PC-relative addressing mode"
 msgstr "Sintaxis inválida en el modo de direccionamiento relativo al PC"
 
-#: config/tc-ns32k.c:473
+#: config/tc-ns32k.c:465
 msgid "Invalid syntax in External addressing mode"
 msgstr "Sintaxis inválida en el modo de direccionamiento Externo"
 
-#: config/tc-ns32k.c:554
+#: config/tc-ns32k.c:546
 msgid "Invalid syntax in Memory Relative addressing mode"
 msgstr "Sintaxis inválida en el modo de direccionamiento Relativo a Memoria"
 
-#: config/tc-ns32k.c:621
+#: config/tc-ns32k.c:613
 msgid "Invalid scaled-indexed mode, use (b,w,d,q)"
 msgstr "Modo escalado-indizado inválido, utilice (b,w,d,q)"
 
-#: config/tc-ns32k.c:626
+#: config/tc-ns32k.c:618
 msgid "Syntax in scaled-indexed mode, use [Rn:m] where n=[0..7] m={b,w,d,q}"
 msgstr "Sintaxis en el modo escalado-indizado, utilice [Rn:m] donde n=[0..7] m={b,w,d,q}"
 
-#: config/tc-ns32k.c:631
+#: config/tc-ns32k.c:623
 msgid "Scaled-indexed addressing mode combined with scaled-index"
 msgstr "Modo de direccionamiento escalado-indizado combinado con índice-escalado"
 
-#: config/tc-ns32k.c:642
+#: config/tc-ns32k.c:634
 msgid "Invalid or illegal addressing mode combined with scaled-index"
 msgstr "Modo de direccionamiento inválido o ilegal combiando con índice-escalado"
 
 #: config/tc-ns32k.c:757
 msgid "Premature end of suffix -- Defaulting to d"
-msgstr "Fin de sufijo prematuro -- Cambiando por omisión a d"
+msgstr "Fin de sufijo prematuro -- Cambiando por defecto a d"
 
 #: config/tc-ns32k.c:770
 msgid "Bad suffix after ':' use {b|w|d} Defaulting to d"
-msgstr "Sufijo erróneo después de ':' utilice {b|w|d} Cambiando por omisión a d"
+msgstr "Sufijo erróneo después de ':' utilice {b|w|d} Cambiando por defecto a d"
 
-#: config/tc-ns32k.c:817
+#: config/tc-ns32k.c:815
 msgid "Very short instr to option, ie you can't do it on a NULLstr"
 msgstr "Instrucción muy corta para la opción, p.e. no lo puede hacer en un NULLstr"
 
-#: config/tc-ns32k.c:870
+#: config/tc-ns32k.c:865
 msgid "No such entry in list. (cpu/mmu register)"
 msgstr "No existe esa entrada en la lista. (registros cpu/mmu)"
 
-#: config/tc-ns32k.c:915
+#: config/tc-ns32k.c:922
 msgid "Internal consistency error.  check ns32k-opcode.h"
 msgstr "Error de consistencia interno.  revise ns32k-opcode.h"
 
-#: config/tc-ns32k.c:939
+#: config/tc-ns32k.c:946
 msgid "Address of immediate operand"
 msgstr "Dirección del operando inmediato"
 
-#: config/tc-ns32k.c:940
+#: config/tc-ns32k.c:947
 msgid "Invalid immediate write operand."
 msgstr "Operando de escritura inmediato inválido."
 
-#: config/tc-ns32k.c:1070
+#: config/tc-ns32k.c:1077
 msgid "Bad opcode-table-option, check in file ns32k-opcode.h"
 msgstr "Opción-de-tabla-de-códigos-de-operación errónea, revise en el fichero ns32k-opcode.h"
 
-#: config/tc-ns32k.c:1107
+#: config/tc-ns32k.c:1110
 msgid "No such opcode"
 msgstr "No existe ese código de operación"
 
-#: config/tc-ns32k.c:1184
+#: config/tc-ns32k.c:1185
 msgid "Bad suffix, defaulting to d"
-msgstr "Sufijo erróneo, cambiando por omisión a d"
+msgstr "Sufijo erróneo, cambiando por defecto a d"
 
 #: config/tc-ns32k.c:1212
 msgid "Too many operands passed to instruction"
 msgstr "Se pasaron demasiados operandos a la instrucción"
 
 #. Check error in default.
-#: config/tc-ns32k.c:1225
+#: config/tc-ns32k.c:1224
 msgid "Wrong numbers of operands in default, check ns32k-opcodes.h"
-msgstr "Número erróneo de operandos por omisión, revise ns32k-opcodes.h"
+msgstr "Número erróneo de operandos por defecto, revise ns32k-opcodes.h"
 
-#: config/tc-ns32k.c:1229
+#: config/tc-ns32k.c:1227
 msgid "Wrong number of operands"
 msgstr "Número erróneo de operandos"
 
-#: config/tc-ns32k.c:1355
-msgid "iif convert internal pcrel/binary"
-msgstr "iif convierte a pcrel/binario interno"
-
-#: config/tc-ns32k.c:1372
-msgid "Bignum too big for long"
-msgstr "Número grande demasiado grande para long"
-
-#: config/tc-ns32k.c:1451
-msgid "iif convert internal pcrel/pointer"
-msgstr "iif convierte a pcrel/apuntador interno"
-
-#: config/tc-ns32k.c:1456
-msgid "Internal logic error in iif.iifP[n].type"
-msgstr "Error interno de lógica en iif.iifP[n].tipo"
-
-#. We cant relax this case.
-#: config/tc-ns32k.c:1493
-msgid "Can't relax difference"
-msgstr "No se puede relajar la diferencia"
-
-#: config/tc-ns32k.c:1541
-msgid "Displacement to large for :d"
-msgstr "Desubicación demasiado grande para :d"
-
-#: config/tc-ns32k.c:1554
-msgid "Internal logic error in iif.iifP[].type"
-msgstr "Error interno de lógica en iif.iifP[].tipo"
-
-#: config/tc-ns32k.c:1614
+#: config/tc-ns32k.c:1300
 #, c-format
 msgid "Can not do %d byte pc-relative relocation for storage type %d"
 msgstr "No se puede hacer la reubicación relativa al pc de %d byte para el tipo de almacenamiento %d"
 
-#: config/tc-ns32k.c:1617
+#: config/tc-ns32k.c:1303
 #, c-format
 msgid "Can not do %d byte relocation for storage type %d"
 msgstr "No se puede hacer la reubicación de %d byte para el tipo de almacenamiento %d"
 
-#. Fatal.
-#: config/tc-ns32k.c:1652
-#, c-format
-msgid "Can't hash %s: %s"
-msgstr "No se puede dispersar %s: %s"
-
-#: config/tc-ns32k.c:1740
+#: config/tc-ns32k.c:1395
 #, c-format
 msgid "value of %ld out of byte displacement range."
 msgstr "valor de %ld fuera del rango de desubicación de byte."
 
-#: config/tc-ns32k.c:1749
+#: config/tc-ns32k.c:1405
 #, c-format
 msgid "value of %ld out of word displacement range."
 msgstr "valor de %ld fuera del rango de desubicación de word."
 
-#: config/tc-ns32k.c:1763
+#: config/tc-ns32k.c:1420
 #, c-format
 msgid "value of %ld out of double word displacement range."
 msgstr "valor de %ld fuera del rango de desubicación de doble word."
 
-#: config/tc-ns32k.c:1783
+#: config/tc-ns32k.c:1441
 #, c-format
 msgid "Internal logic error.  line %d, file \"%s\""
 msgstr "Error lógico interno.  línea %d, fichero \"%s\""
 
-#: config/tc-ns32k.c:1831
+#: config/tc-ns32k.c:1489
 #, c-format
 msgid "Internal logic error. line %d, file \"%s\""
 msgstr "Error lógico interno. línea %d, fichero \"%s\""
 
-#: config/tc-ns32k.c:1936
+#: config/tc-ns32k.c:1590
 msgid "Bit field out of range"
 msgstr "Campo de bits fuera de rango"
 
-#: config/tc-ns32k.c:2183
+#: config/tc-ns32k.c:1690
+msgid "iif convert internal pcrel/binary"
+msgstr "iif convierte a pcrel/binario interno"
+
+#: config/tc-ns32k.c:1707
+msgid "Bignum too big for long"
+msgstr "Número grande demasiado grande para long"
+
+#: config/tc-ns32k.c:1784
+msgid "iif convert internal pcrel/pointer"
+msgstr "iif convierte a pcrel/puntero interno"
+
+#: config/tc-ns32k.c:1789
+msgid "Internal logic error in iif.iifP[n].type"
+msgstr "Error interno de lógica en iif.iifP[n].tipo"
+
+#. We cant relax this case.
+#: config/tc-ns32k.c:1825
+msgid "Can't relax difference"
+msgstr "No se puede relajar la diferencia"
+
+#: config/tc-ns32k.c:1866
+msgid "Displacement to large for :d"
+msgstr "Desubicación demasiado grande para :d"
+
+#: config/tc-ns32k.c:1879
+msgid "Internal logic error in iif.iifP[].type"
+msgstr "Error interno de lógica en iif.iifP[].tipo"
+
+#. Fatal.
+#: config/tc-ns32k.c:1911
+#, c-format
+msgid "Can't hash %s: %s"
+msgstr "No se puede dispersar %s: %s"
+
+#: config/tc-ns32k.c:2181
 #, c-format
 msgid "invalid architecture option -m%s, ignored"
 msgstr "opción de arquitectura -m%s inválida, se ignora"
 
-#: config/tc-ns32k.c:2196
+#: config/tc-ns32k.c:2194
 #, c-format
 msgid "invalid default displacement size \"%s\". Defaulting to %d."
-msgstr "tamaño de desubicación por omisión \"%s\" inválido. Cambiando a %d por omisión."
+msgstr "tamaño de desubicación por defecto \"%s\" inválido. Cambiando a %d por defecto."
 
-#: config/tc-ns32k.c:2213
+#: config/tc-ns32k.c:2210
+#, c-format
 msgid ""
 "NS32K options:\n"
 "-m32032 | -m32532\tselect variant of NS32K architecture\n"
@@ -7648,74 +8313,72 @@ msgstr ""
 "-m32032 | -m32532\tselecciona la variante de la arquitectura NS32K\n"
 "--disp-size-default=<1|2|4>\n"
 
-#: config/tc-ns32k.c:2397
+#: config/tc-ns32k.c:2285
 #, c-format
 msgid "Cannot find relocation type for symbol %s, code %d"
 msgstr "No se puede encontrar el tipo de reubicación para el símbolo %s, código %d"
 
-#: config/tc-or32.c:465 config/tc-or32.c:680
+#: config/tc-or32.c:360
 #, c-format
 msgid "unknown opcode1: `%s'"
 msgstr "código de operación1 desconocido: `%s'"
 
-#: config/tc-or32.c:471 config/tc-or32.c:686
+#: config/tc-or32.c:366
 #, c-format
 msgid "unknown opcode2 `%s'."
 msgstr "código de operación2 `%s' desconocido."
 
-#: config/tc-or32.c:510 config/tc-or32.c:725
+#: config/tc-or32.c:403
 #, c-format
 msgid "instruction not allowed: %s"
 msgstr "no se permite la instrucción: %s"
 
-#: config/tc-or32.c:513 config/tc-or32.c:728
+#: config/tc-or32.c:406
 #, c-format
 msgid "too many operands: %s"
 msgstr "demasiados operandos: %s"
 
-#: config/tc-or32.c:603 config/tc-or32.c:819
+#: config/tc-or32.c:490
 msgid "call/jmp target out of range (1)"
 msgstr "objetivo call/jmp fuera de rango (1)"
 
-#: config/tc-or32.c:1016 config/tc-or32.c:1133
-msgid "the linker will not handle this relocation correctly (1)"
-msgstr "el enlazador no manejará correctamente esta reubicación (1)"
-
-#: config/tc-or32.c:1025 config/tc-or32.c:1142
+#: config/tc-or32.c:674
 msgid "call/jmp target out of range (2)"
 msgstr "objetivo call/jmp fuera de rango (2)"
 
-#: config/tc-or32.c:1433
-msgid "register out of range"
-msgstr "registro fuera de rango"
+#: config/tc-or32.c:693
+#, c-format
+msgid "bad relocation type: 0x%02x"
+msgstr "tipo de reubicación erróneo: 0x%02x"
 
-#: config/tc-or32.c:1478
+#: config/tc-or32.c:885
 msgid "invalid register in & expression"
 msgstr "registro inválido en la expresión &"
 
-#: config/tc-pdp11.c:454
+#: config/tc-pdp11.c:490
 msgid "Low order bits truncated in immediate float operand"
 msgstr "Se truncaron los bits de orden inferior en el operando de coma flotante inmediato"
 
-#: config/tc-pdp11.c:665
+#: config/tc-pdp11.c:679
 #, c-format
 msgid "Unknown instruction '%s'"
 msgstr "Instrucción '%s' desconocida"
 
-#: config/tc-pj.c:82 config/tc-pj.c:90
+#: config/tc-pj.c:66 config/tc-pj.c:75
 msgid "confusing relocation expressions"
 msgstr "expresiones de reubicación confusas"
 
-#: config/tc-pj.c:181
+#: config/tc-pj.c:158
 msgid "can't have relocation for ipush"
 msgstr "no se puede tener una reubicación para ipush"
 
-#: config/tc-pj.c:290 config/tc-xtensa.c:4976
+#: config/tc-pj.c:261
 #, c-format
 msgid "unknown opcode %s"
 msgstr "código de operación %s desconocido"
 
-#: config/tc-pj.c:439
+#: config/tc-pj.c:404
+#, c-format
 msgid ""
 "PJ options:\n"
 "-little\t\t\tgenerate little endian code\n"
@@ -7725,8 +8388,8 @@ msgstr ""
 "-little\t\t\tgenera código little endian\n"
 "-big\t\t\tgenera código big endian\n"
 
-#: config/tc-pj.c:469 config/tc-sh.c:3464 config/tc-sh.c:3471
-#: config/tc-sh.c:3478 config/tc-sh.c:3485
+#: config/tc-pj.c:431 config/tc-sh.c:3955 config/tc-sh.c:3962
+#: config/tc-sh.c:3969 config/tc-sh.c:3976
 msgid "pcrel too far"
 msgstr "pcrel demasiado lejos"
 
@@ -7738,17 +8401,18 @@ msgstr "convert_frag\n"
 msgid "estimate size\n"
 msgstr "tamaño estimado\n"
 
-#: config/tc-ppc.c:879
+#: config/tc-ppc.c:991
 #, c-format
 msgid "%s unsupported"
 msgstr "%s no tiene soporte"
 
-#: config/tc-ppc.c:1029 config/tc-s390.c:414 config/tc-s390.c:421
+#: config/tc-ppc.c:1057 config/tc-s390.c:417 config/tc-s390.c:424
 #, c-format
 msgid "invalid switch -m%s"
 msgstr "interruptor -m%s inválido"
 
-#: config/tc-ppc.c:1066
+#: config/tc-ppc.c:1094
+#, c-format
 msgid ""
 "PowerPC options:\n"
 "-a32\t\t\tgenerate ELF32/XCOFF32\n"
@@ -7760,6 +8424,7 @@ msgid ""
 "-mppc, -mppc32, -m603, -m604\n"
 "\t\t\tgenerate code for PowerPC 603/604\n"
 "-m403, -m405\t\tgenerate code for PowerPC 403/405\n"
+"-m440\t\t\tgenerate code for PowerPC 440\n"
 "-m7400, -m7410, -m7450, -m7455\n"
 "\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"
 msgstr ""
@@ -7776,13 +8441,15 @@ msgstr ""
 "-m7400, -m7410, -m7450, -m7455\n"
 "\t\t\tgenera código para PowerPC 7400/7410/7450/7455\n"
 
-#: config/tc-ppc.c:1079
+#: config/tc-ppc.c:1108
+#, c-format
 msgid ""
 "-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n"
 "-mppc64bridge\t\tgenerate code for PowerPC 64, including bridge insns\n"
 "-mbooke64\t\tgenerate code for 64-bit PowerPC BookE\n"
 "-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n"
 "-mpower4\t\tgenerate code for Power4 architecture\n"
+"-mpower5\t\tgenerate code for Power5 architecture\n"
 "-mcom\t\t\tgenerate code Power/PowerPC common instructions\n"
 "-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"
 msgstr ""
@@ -7792,24 +8459,29 @@ msgstr ""
 "-mbooke64\t\tgenera código para PowerPC BookE de 64-bit\n"
 "-mbooke, mbooke32\tgenera código para PowerPC BookE de 32-bit\n"
 "-mpower4\t\tgenera código para la arquitectura Power4\n"
+"-mpower5\t\tgenera código para la arquitectura Power5\n"
 "-mcom\t\t\tgenera código de instrucciones comunes Power/PowerPC\n"
 "-many\t\t\tgenera código para cualquier arquitectura (PWR/PWRX/PPC)\n"
 
-#: config/tc-ppc.c:1087
+#: config/tc-ppc.c:1117
+#, c-format
 msgid ""
 "-maltivec\t\tgenerate code for AltiVec\n"
+"-me300\t\t\tgenerate code for PowerPC e300 family\n"
 "-me500, -me500x2\tgenerate code for Motorola e500 core complex\n"
 "-mspe\t\t\tgenerate code for Motorola SPE instructions\n"
 "-mregnames\t\tAllow symbolic names for registers\n"
 "-mno-regnames\t\tDo not allow symbolic names for registers\n"
 msgstr ""
 "-maltivec\t\tgenera código para AltiVec\n"
+"-me300\t\t\tgenera código para la familia PowerPC e300\n"
 "-me500, -me500x2\tgenera código para el núcleo complejo Motorola e500\n"
 "-mspe\t\t\tgenera código para las instrucciones Motorola SPE\n"
 "-mregnames\t\tPermite nombres simbólicos para los registros\n"
 "-mno-regnames\t\tNo permite nombres simbólicos para los registros\n"
 
-#: config/tc-ppc.c:1094
+#: config/tc-ppc.c:1125
+#, c-format
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
 "-mrelocatable-lib\tsupport for GCC's -mrelocatble-lib option\n"
@@ -7835,221 +8507,252 @@ msgstr ""
 "-V\t\t\tmuestra el número de versión del ensamblador\n"
 "-Qy, -Qn\t\tse ignora\n"
 
-#: config/tc-ppc.c:1136
+#: config/tc-ppc.c:1162
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
-msgstr "Cpu por omisión desconocido = %s, os = %s"
+msgstr "Cpu por defecto desconocido = %s, os = %s"
 
-#: config/tc-ppc.c:1161
+#: config/tc-ppc.c:1188
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr "No se escogieron los códigos de operación Power ni PowerPC"
 
-#: config/tc-ppc.c:1257 config/tc-s390.c:516
+#: config/tc-ppc.c:1285 config/tc-s390.c:519
 #, c-format
 msgid "Internal assembler error for instruction %s"
 msgstr "Error interno del ensamblador para la instrucción %s"
 
-#: config/tc-ppc.c:1277
+#: config/tc-ppc.c:1309
 #, c-format
 msgid "Internal assembler error for macro %s"
 msgstr "Error interno del ensamblador para la macro %s"
 
-#: config/tc-ppc.c:1599
+#: config/tc-ppc.c:1640
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr "identificador+constante@got significa identificador@got+constante"
 
-#: config/tc-ppc.c:1666
+#: config/tc-ppc.c:1707
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr "%s reubicaciones no caben en %d bytes\n"
 
-#: config/tc-ppc.c:1773
+#: config/tc-ppc.c:1814
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr "La longitud de .lcomm \"%s\" ya es %ld. No se cambió a %ld."
 
-#: config/tc-ppc.c:1855
+#: config/tc-ppc.c:1896
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr "No se puede hacer la reubicación cuando se utiliza -mrelocatable"
 
-#: config/tc-ppc.c:1981
+#: config/tc-ppc.c:1945
+msgid "TOC section size exceeds 64k"
+msgstr "el tamaño de la sección TOC excede los 64k"
+
+#: config/tc-ppc.c:2027
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr "error sintáctico: especificador de tabla de contenidos `%s' inválido"
 
-#: config/tc-ppc.c:1995
+#: config/tc-ppc.c:2041
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr "error sintáctico: se esperaba `]', se obtuvo  `%c'"
 
-#: config/tc-ppc.c:2272
+#: config/tc-ppc.c:2320
 msgid "[tocv] symbol is not a toc symbol"
 msgstr "el símbolo [tocv] no es un símbolo de tabla de contenido"
 
-#: config/tc-ppc.c:2283
+#: config/tc-ppc.c:2331
 msgid "Unimplemented toc32 expression modifier"
 msgstr "Modificador de expresión toc32 sin implementar"
 
-#: config/tc-ppc.c:2288
+#: config/tc-ppc.c:2336
 msgid "Unimplemented toc64 expression modifier"
 msgstr "Modificador de expresión toc64 sin implementar"
 
-#: config/tc-ppc.c:2292
+#: config/tc-ppc.c:2340
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr "¡Valor de devolución inesperado [%d] de parse_toc_entry!\n"
 
-#: config/tc-ppc.c:2510
+#: config/tc-ppc.c:2558
 msgid "unsupported relocation for DS offset field"
 msgstr "tipo de reubicación sin soporte para el campo de desplazamiento DS"
 
-#: config/tc-ppc.c:2554
+#: config/tc-ppc.c:2602
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr "error sintáctico; se encontró `%c' pero se esperaba `%c'"
 
-#: config/tc-ppc.c:2703
+#: config/tc-ppc.c:2645 config/tc-ppc.h:111
+msgid "instruction address is not a multiple of 4"
+msgstr "la dirección de la instrucción no es un múltiplo de 4"
+
+#: config/tc-ppc.c:2756
 msgid "wrong number of operands"
 msgstr "número erróneo de operandos"
 
-#: config/tc-ppc.c:2759
+#: config/tc-ppc.c:2812
 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string"
 msgstr "Directiva .section errónea: se quiere a,e,w,x,M,S,G,T en la cadena"
 
-#: config/tc-ppc.c:2874
+#: config/tc-ppc.c:2927
 msgid "missing size"
 msgstr "falta el tamaño"
 
-#: config/tc-ppc.c:2883
+#: config/tc-ppc.c:2936
 msgid "negative size"
 msgstr "tamaño negativo"
 
-#: config/tc-ppc.c:2920
+#: config/tc-ppc.c:2973
 msgid "missing real symbol name"
 msgstr "falta el nombre real del símbolo"
 
-#: config/tc-ppc.c:2941
+#: config/tc-ppc.c:2994
 msgid "attempt to redefine symbol"
 msgstr "se intentó redefinir el símbolo"
 
-#: config/tc-ppc.c:3188
+#: config/tc-ppc.c:3241
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr "El formato del fichero XCOFF no tiene soporte para secciones arbitrarias"
 
-#: config/tc-ppc.c:3265
+#: config/tc-ppc.c:3318
 msgid "missing rename string"
 msgstr "falta la cadena para renombrar"
 
-#: config/tc-ppc.c:3296 config/tc-ppc.c:3851 read.c:3060
+#: config/tc-ppc.c:3349 config/tc-ppc.c:3904 read.c:3064
 msgid "missing value"
 msgstr "falta el valor"
 
-#: config/tc-ppc.c:3314
+#: config/tc-ppc.c:3367
 msgid "illegal .stabx expression; zero assumed"
 msgstr "expresión .stabx ilegal; se asume cero"
 
-#: config/tc-ppc.c:3346
+#: config/tc-ppc.c:3399
 msgid "missing class"
 msgstr "falta la clase"
 
-#: config/tc-ppc.c:3355
+#: config/tc-ppc.c:3408
 msgid "missing type"
 msgstr "falta el tipo"
 
-#: config/tc-ppc.c:3436
+#: config/tc-ppc.c:3489
 msgid "missing symbol name"
 msgstr "falta el nombre del símbolo"
 
-#: config/tc-ppc.c:3630
+#: config/tc-ppc.c:3683
 msgid "nested .bs blocks"
 msgstr "bloques .bs anidados"
 
-#: config/tc-ppc.c:3663
+#: config/tc-ppc.c:3716
 msgid ".es without preceding .bs"
 msgstr ".es sin un .bs precedente"
 
-#: config/tc-ppc.c:3843
+#: config/tc-ppc.c:3896
 msgid "non-constant byte count"
 msgstr "cuenta de byte no constante"
 
-#: config/tc-ppc.c:3891
+#: config/tc-ppc.c:3944
 msgid ".tc not in .toc section"
 msgstr ".tc no está en la sección .toc"
 
-#: config/tc-ppc.c:3910
+#: config/tc-ppc.c:3963
 msgid ".tc with no label"
 msgstr ".tc sin etiqueta"
 
-#: config/tc-ppc.c:4021
+#: config/tc-ppc.c:4055
+msgid ".machine stack overflow"
+msgstr "desbordamiento de pila en .machine"
+
+#: config/tc-ppc.c:4062
+msgid ".machine stack underflow"
+msgstr "desbordamiento por debajo de la pila en .machine"
+
+#: config/tc-ppc.c:4069
+#, c-format
+msgid "invalid machine `%s'"
+msgstr "máquina `%s' inválida"
+
+#: config/tc-ppc.c:4123
 msgid "No previous section to return to. Directive ignored."
 msgstr "No hay sección previa a la cual regresar. Se ignora la directiva."
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:4438
+#: config/tc-ppc.c:4540
 msgid "Unsupported section attribute -- 'a'"
 msgstr "Atributo de sección sin soporte -- 'a'"
 
-#: config/tc-ppc.c:4627
+#: config/tc-ppc.c:4729
 msgid "bad symbol suffix"
 msgstr "sufijo de símbolo erróneo"
 
-#: config/tc-ppc.c:4720
+#: config/tc-ppc.c:4822
 msgid "Unrecognized symbol suffix"
 msgstr "sufijo de símbolo no reconocido"
 
-#: config/tc-ppc.c:4806
+#: config/tc-ppc.c:4912
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr "dos pseudo-operadores .function sin un .ef que intervenga"
 
-#: config/tc-ppc.c:4819
+#: config/tc-ppc.c:4925
 msgid ".ef with no preceding .function"
 msgstr ".ef sin un .function precedente"
 
-#: config/tc-ppc.c:4947
+#: config/tc-ppc.c:5053
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr "aviso: el símbolo %s no tiene csect"
 
-#: config/tc-ppc.c:5251
+#: config/tc-ppc.c:5357
 msgid "symbol in .toc does not match any .tc"
 msgstr "el símbolo en .toc no coincide con ningún .tc"
 
-#: config/tc-ppc.c:5584 config/tc-s390.c:2072 config/tc-v850.c:2402
-#: config/tc-xstormy16.c:537
+#: config/tc-ppc.c:5686 config/tc-s390.c:2092 config/tc-v850.c:2314
+#: config/tc-xstormy16.c:538
 msgid "unresolved expression that must be resolved"
 msgstr "expresión sin resolver que debe ser resuelta"
 
-#: config/tc-ppc.c:5587
+#: config/tc-ppc.c:5689
 #, c-format
 msgid "unsupported relocation against %s"
 msgstr "reubicación sin soporte contra %s"
 
-#: config/tc-ppc.c:5662
+#: config/tc-ppc.c:5762
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr "no se puede emitir la reubicación %s relativa al PC contra %s"
 
-#: config/tc-ppc.c:5667
+#: config/tc-ppc.c:5767
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr "no se puede emitir la reubicación %s relativa al PC"
 
-#: config/tc-ppc.c:5841
+#: config/tc-ppc.c:5949
+#, c-format
+msgid "Unable to handle reference to symbol %s"
+msgstr "No se puede manejar la referencia al símbolo %s"
+
+#: config/tc-ppc.c:5952
+msgid "Unable to resolve expression"
+msgstr "No se puede resolver la expresión"
+
+#: config/tc-ppc.c:5979
 msgid "must branch to an address a multiple of 4"
 msgstr "se debe ramificar a una dirección que sea múltiplo de 4"
 
-#: config/tc-ppc.c:5845
+#: config/tc-ppc.c:5983
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr "el destino de la ramificación @local o @plt está demasiado lejos, %ld bytes"
 
-#: config/tc-ppc.c:5876
+#: config/tc-ppc.c:6014
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr "Falla de gas, valor de reubicación %d\n"
 
-#: config/tc-s390.c:457
+#: config/tc-s390.c:460
+#, c-format
 msgid ""
 "        S390 options:\n"
 "        -mregnames        Allow symbolic names for registers\n"
@@ -8065,7 +8768,8 @@ msgstr ""
 "        -m31              Establece el formato del fichero al formato 31 bit\n"
 "        -m64              Establece el formato del fichero al formato 64 bit\n"
 
-#: config/tc-s390.c:464
+#: config/tc-s390.c:467
+#, c-format
 msgid ""
 "        -V                print assembler version number\n"
 "        -Qy, -Qn          ignored\n"
@@ -8073,542 +8777,596 @@ msgstr ""
 "        -V                muestra el número de versión del ensamblador\n"
 "        -Qy, -Qn          se ignora\n"
 
-#: config/tc-s390.c:500
+#: config/tc-s390.c:503
 #, c-format
 msgid "Internal assembler error for instruction format %s"
 msgstr "Error interno del ensamblador para la el formato de instrucción %s"
 
-#: config/tc-s390.c:782
+#: config/tc-s390.c:766
 #, c-format
 msgid "identifier+constant@%s means identifier@%s+constant"
 msgstr "identificador+constante@%s significa identificador@%s+constante"
 
-#: config/tc-s390.c:865
+#: config/tc-s390.c:849
 msgid "Can't handle O_big in s390_exp_compare"
 msgstr "No se puede manejar O_big en s390_exp_compare"
 
-#: config/tc-s390.c:949
+#: config/tc-s390.c:933
 msgid "Invalid suffix for literal pool entry"
 msgstr "Sufijo inválido para la entrada de conjunto de literales"
 
-#: config/tc-s390.c:1006
+#: config/tc-s390.c:990
 msgid "Big number is too big"
 msgstr "El número grande es demasiado grande"
 
-#: config/tc-s390.c:1144 config/tc-s390.c:1722
-#, c-format
-msgid "%s relocations do not fit in %d bytes"
-msgstr "%s reubicaciones no caben en %d bytes"
-
-#: config/tc-s390.c:1154
+#: config/tc-s390.c:1138
 msgid "relocation not applicable"
 msgstr "la reubicación no es aplicable"
 
-#: config/tc-s390.c:1342
+#: config/tc-s390.c:1326
 msgid "invalid operand suffix"
 msgstr "sufijo de operando inválido"
 
-#: config/tc-s390.c:1365
+#: config/tc-s390.c:1349
 msgid "syntax error; missing '(' after displacement"
 msgstr "error sintáctico; falta un '(' después de la desubicación"
 
-#: config/tc-s390.c:1375 config/tc-s390.c:1408 config/tc-s390.c:1427
+#: config/tc-s390.c:1365 config/tc-s390.c:1409 config/tc-s390.c:1439
 msgid "syntax error; expected ,"
 msgstr "error sintáctico; se esperaba ,"
 
-#: config/tc-s390.c:1402
+#: config/tc-s390.c:1397
 msgid "syntax error; missing ')' after base register"
 msgstr "error sintáctico; falta un '(' después del registro base"
 
-#: config/tc-s390.c:1420
+#: config/tc-s390.c:1426
 msgid "syntax error; ')' not allowed here"
 msgstr "errór sintáctico; no se permite aquí un ')'"
 
-#: config/tc-s390.c:1602 config/tc-s390.c:1622 config/tc-s390.c:1635
+#: config/tc-s390.c:1619 config/tc-s390.c:1642 config/tc-s390.c:1655
 msgid "Invalid .insn format\n"
 msgstr "Formato .insn inválido\n"
 
-#: config/tc-s390.c:1610
+#: config/tc-s390.c:1627
 #, c-format
 msgid "Unrecognized opcode format: `%s'"
 msgstr "Formato de código de operación no reconocido: `%s'"
 
-#: config/tc-s390.c:1638
+#: config/tc-s390.c:1658
 msgid "second operand of .insn not a constant\n"
 msgstr "el operando de .insn no es una constante\n"
 
-#: config/tc-s390.c:1641
+#: config/tc-s390.c:1661
 msgid "missing comma after insn constant\n"
 msgstr "falta una coma después de la constante insn\n"
 
-#: config/tc-s390.c:2075
+#: config/tc-s390.c:2095
 msgid "unsupported relocation type"
 msgstr "tipo de reubicación sin soporte"
 
-#: config/tc-sh.c:91
+#: config/tc-sh64.c:568
+msgid "This operand must be constant at assembly time"
+msgstr "El operando debe ser una constante al momento de ensamblar"
+
+#: config/tc-sh64.c:681
+msgid "Invalid operand expression"
+msgstr "Expresión de operando inválido"
+
+#: config/tc-sh64.c:773 config/tc-sh64.c:877
+msgid "PTB operand is a SHmedia symbol"
+msgstr "El operando PTB es un símbolo SHmedia"
+
+#: config/tc-sh64.c:776 config/tc-sh64.c:874
+msgid "PTA operand is a SHcompact symbol"
+msgstr "El operando PTA es un símbolo SHcompact"
+
+#: config/tc-sh64.c:792
+msgid "invalid expression in operand"
+msgstr "expresión inválida en el operando"
+
+#: config/tc-sh64.c:1483
+#, c-format
+msgid "invalid operand, not a 5-bit unsigned value: %d"
+msgstr "operando inválido, no es un valor de 5-bit sin signo: %d"
+
+#: config/tc-sh64.c:1488
+#, c-format
+msgid "invalid operand, not a 6-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 6-bit con signo: %d"
+
+#: config/tc-sh64.c:1493
+#, c-format
+msgid "invalid operand, not a 6-bit unsigned value: %d"
+msgstr "operando inválido, no es un valor de 6-bit sin signo: %d"
+
+#: config/tc-sh64.c:1498 config/tc-sh64.c:1510
+#, c-format
+msgid "invalid operand, not a 11-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 11-bit con signo: %d"
+
+#: config/tc-sh64.c:1500
+#, c-format
+msgid "invalid operand, not a multiple of 32: %d"
+msgstr "operando inválido, no es un múltiplo de 32: %d"
+
+#: config/tc-sh64.c:1505
+#, c-format
+msgid "invalid operand, not a 10-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 10-bit con signo: %d"
+
+#: config/tc-sh64.c:1512
+#, c-format
+msgid "invalid operand, not an even value: %d"
+msgstr "operando inválido, no es un valor impar: %d"
+
+#: config/tc-sh64.c:1517
+#, c-format
+msgid "invalid operand, not a 12-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 12-bit con signo: %d"
+
+#: config/tc-sh64.c:1519
+#, c-format
+msgid "invalid operand, not a multiple of 4: %d"
+msgstr "operando inválido, no es un múltiplo de 4: %d"
+
+#: config/tc-sh64.c:1524
+#, c-format
+msgid "invalid operand, not a 13-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 13-bit con signo: %d"
+
+#: config/tc-sh64.c:1526
+#, c-format
+msgid "invalid operand, not a multiple of 8: %d"
+msgstr "operando inválido, no es un múltiplo de 8: %d"
+
+#: config/tc-sh64.c:1531
+#, c-format
+msgid "invalid operand, not a 16-bit signed value: %d"
+msgstr "operando inválido, no es un valor de 16-bit con signo: %d"
+
+#: config/tc-sh64.c:1536
+#, c-format
+msgid "invalid operand, not an 16-bit unsigned value: %d"
+msgstr "operando inválido, no es un valor de 16-bit sin signo: %d"
+
+#: config/tc-sh64.c:1542
+msgid "operand out of range for PT, PTA and PTB"
+msgstr "operando fuera de rango para PT, PTA y PTB"
+
+#: config/tc-sh64.c:1544
+#, c-format
+msgid "operand not a multiple of 4 for PT, PTA or PTB: %d"
+msgstr "el operando no es un múltiplo de 4 para PT, PTA o PTB: %d"
+
+#: config/tc-sh64.c:2064
+#, c-format
+msgid "MOVI operand is not a 32-bit signed value: 0x%8x%08x"
+msgstr "el operando MOVI no es un valor de 32-bit con signo: 0x%8x%08x"
+
+#: config/tc-sh64.c:2421 config/tc-sh64.c:2584 config/tc-sh64.c:2599
+msgid "invalid PIC reference"
+msgstr "referencia PIC inválida"
+
+#: config/tc-sh64.c:2478
+msgid "can't find opcode"
+msgstr "no se puede encontrar el código de operación"
+
+#: config/tc-sh64.c:2681 config/tc-sh64.c:2721
+msgid "invalid operand: expression in PT target"
+msgstr "operando inválido: expresión en el objetivo PT"
+
+#: config/tc-sh64.c:2812
+#, c-format
+msgid "invalid operands to %s"
+msgstr "operandos inválidos para %s"
+
+#: config/tc-sh64.c:2818
+#, c-format
+msgid "excess operands to %s"
+msgstr "exceso de operandos para %s"
+
+#: config/tc-sh64.c:2863
+#, c-format
+msgid "The `.mode %s' directive is not valid with this architecture"
+msgstr "La directiva `.mode %s' no es válida para esta arquitectura"
+
+#: config/tc-sh64.c:2871
+#, c-format
+msgid "Invalid argument to .mode: %s"
+msgstr "Argumento inválido para .mode: %s"
+
+#: config/tc-sh64.c:2901
+#, c-format
+msgid "The `.abi %s' directive is not valid with this architecture"
+msgstr "La directiva `.abi %s' no es válida para esta arquitectura"
+
+#: config/tc-sh64.c:2907
+msgid "`.abi 64' but command-line options do not specify 64-bit ABI"
+msgstr "`.abi 64' pero las opciones de la línea de órdenes no especifica la ABI de 64-bit"
+
+#: config/tc-sh64.c:2912
+msgid "`.abi 32' but command-line options do not specify 32-bit ABI"
+msgstr "`.abi 32' pero las opciones de la línea de órdenes no especifica la ABI de 32-bit"
+
+#: config/tc-sh64.c:2915
+#, c-format
+msgid "Invalid argument to .abi: %s"
+msgstr "Argumento inválido para .abi: %s"
+
+#: config/tc-sh64.c:2970
+msgid "-no-mix is invalid without specifying SHcompact or SHmedia"
+msgstr "-no-mix es inválido sin especificar SHcompact o SHmedia"
+
+#: config/tc-sh64.c:2975
+msgid "-shcompact-const-crange is invalid without SHcompact"
+msgstr "-shcompact-const-crange es inválido sin SHcompact"
+
+#: config/tc-sh64.c:2978
+msgid "-expand-pt32 only valid with -abi=64"
+msgstr "-expand-pt32 sólo es válido con -abi=64"
+
+#: config/tc-sh64.c:2981
+msgid "-no-expand only valid with SHcompact or SHmedia"
+msgstr "-no-expand sólo es válido con SHcompact o SHmedia"
+
+#: config/tc-sh64.c:2984
+msgid "-expand-pt32 invalid together with -no-expand"
+msgstr "-expand-pt32 es inválido junto con -no-expand"
+
+#: config/tc-sh64.c:3201
+msgid "SHmedia code not allowed in same section as constants and SHcompact code"
+msgstr "No se permite código SHmedia en la misma sección que las constantes y el código SHcompact"
+
+#: config/tc-sh64.c:3219
+msgid "No segment info for current section"
+msgstr "No hay información de segmento para la sección actual"
+
+#: config/tc-sh64.c:3258
+msgid "duplicate datalabel operator ignored"
+msgstr "se ignora el operador datalabel duplicado"
+
+#: config/tc-sh64.c:3328
+msgid "Invalid DataLabel expression"
+msgstr "Expresión DataLabel inválida"
+
+#: config/tc-sh.c:65
 msgid "directive .big encountered when option -big required"
 msgstr "se encontró una directiva .big cuando se requirió una opción -big"
 
-#: config/tc-sh.c:102
+#: config/tc-sh.c:75
 msgid "directive .little encountered when option -little required"
 msgstr "se encontró una directiva .little cuando se requirió una opción -little"
 
-#: config/tc-sh.c:776
-msgid "Invalid PIC expression."
-msgstr "Expresión PIC inválida."
-
-#: config/tc-sh.c:1269
+#: config/tc-sh.c:1277
 msgid "misplaced PIC operand"
 msgstr "operando PIC mal colocado"
 
-#: config/tc-sh.c:1310
+#: config/tc-sh.c:1315
+msgid "illegal double indirection"
+msgstr "doble indirección ilegal"
+
+#: config/tc-sh.c:1324
 msgid "illegal register after @-"
 msgstr "registro ilegal después de @-"
 
-#: config/tc-sh.c:1326
+#: config/tc-sh.c:1340
 msgid "must be @(r0,...)"
 msgstr "debe ser @(r0,...)"
 
-#: config/tc-sh.c:1350
+#: config/tc-sh.c:1364
 msgid "syntax error in @(r0,...)"
 msgstr "error sintáctico en @(r0,...)"
 
-#: config/tc-sh.c:1355
+#: config/tc-sh.c:1369
 msgid "syntax error in @(r0...)"
 msgstr "error sintáctico en @(r0...)"
 
-#: config/tc-sh.c:1396
+#: config/tc-sh.c:1414
 msgid "Deprecated syntax."
 msgstr "Sintaxis deprecada."
 
-#: config/tc-sh.c:1408 config/tc-sh.c:1413
+#: config/tc-sh.c:1426 config/tc-sh.c:1431
 msgid "syntax error in @(disp,[Rn, gbr, pc])"
 msgstr "error sintáctico en @(disp,[Rn, gbr, pc])"
 
-#: config/tc-sh.c:1418
+#: config/tc-sh.c:1436
 msgid "expecting )"
 msgstr "se esperaba )"
 
-#: config/tc-sh.c:1426
+#: config/tc-sh.c:1444
 msgid "illegal register after @"
 msgstr "registro ilegal después de @"
 
-#: config/tc-sh.c:1977
+#: config/tc-sh.c:2115
+#, c-format
+msgid "unhandled %d\n"
+msgstr "%d sin manejar\n"
+
+#: config/tc-sh.c:2281
 #, c-format
 msgid "Invalid register: 'r%d'"
 msgstr "Registro inválido: 'r%d'"
 
-#: config/tc-sh.c:2143
+#: config/tc-sh.c:2385
+#, c-format
+msgid "failed for %d\n"
+msgstr "falló para %d\n"
+
+#: config/tc-sh.c:2498 config/tc-sh.c:2894
+msgid "invalid operands for opcode"
+msgstr "operandos inválidos para el código de operación"
+
+#: config/tc-sh.c:2503
 msgid "insn can't be combined with parallel processing insn"
 msgstr "las instrucciones no se pueden combinar con instrucciones de procesamiento paralelo"
 
-#: config/tc-sh.c:2150 config/tc-sh.c:2161
+#: config/tc-sh.c:2510 config/tc-sh.c:2521 config/tc-sh.c:2553
 msgid "multiple movx specifications"
 msgstr "especificaciones movx múltiples"
 
-#: config/tc-sh.c:2155 config/tc-sh.c:2182
+#: config/tc-sh.c:2515 config/tc-sh.c:2537 config/tc-sh.c:2576
 msgid "multiple movy specifications"
 msgstr "especificaciones movy múltiples"
 
-#: config/tc-sh.c:2163
+#: config/tc-sh.c:2524 config/tc-sh.c:2557
 msgid "invalid movx address register"
 msgstr "registro de dirección movx inválido"
 
-#: config/tc-sh.c:2169 config/tc-sh.c:2174
+#: config/tc-sh.c:2526
+msgid "insn cannot be combined with non-nopy"
+msgstr "las instrucciones no se pueden combinar con las que no son nopy"
+
+#: config/tc-sh.c:2540 config/tc-sh.c:2596
+msgid "invalid movy address register"
+msgstr "registro de dirección movy inválido"
+
+#: config/tc-sh.c:2542
+msgid "insn cannot be combined with non-nopx"
+msgstr "las instrucciones no se pueden combinar con las que no son nopx"
+
+#: config/tc-sh.c:2555
+msgid "previous movy requires nopx"
+msgstr "el movy previo requiere nopx"
+
+#: config/tc-sh.c:2563 config/tc-sh.c:2568
 msgid "invalid movx dsp register"
 msgstr "registro dsp movx inválido"
 
-#: config/tc-sh.c:2191 config/tc-sh.c:2196
+#: config/tc-sh.c:2578
+msgid "previous movx requires nopy"
+msgstr "el movx previo requiere nopy"
+
+#: config/tc-sh.c:2587 config/tc-sh.c:2592
 msgid "invalid movy dsp register"
 msgstr "registro dsp movy inválido"
 
-#: config/tc-sh.c:2200
-msgid "invalid movy address register"
-msgstr "registro de dirección movy inválido"
-
-#: config/tc-sh.c:2206
+#: config/tc-sh.c:2602
 msgid "dsp immediate shift value not constant"
 msgstr "el valor de desplazamiento inmediato dsp no es constante"
 
-#: config/tc-sh.c:2213 config/tc-sh.c:2226
+#: config/tc-sh.c:2616 config/tc-sh.c:2642
 msgid "multiple parallel processing specifications"
 msgstr "especificaciones múltiples de procesamiento paralelo"
 
-#: config/tc-sh.c:2219
+#: config/tc-sh.c:2635
 msgid "multiple condition specifications"
 msgstr "especificaciones múltiples de condición"
 
-#: config/tc-sh.c:2235
+#: config/tc-sh.c:2673
 msgid "insn cannot be combined with pmuls"
 msgstr "las instrucciones no se pueden combinar con pmuls"
 
-#: config/tc-sh.c:2252
-msgid "bad padd / psub pmuls output operand"
-msgstr "operando de salida pmuls padd / psub erróneo"
+#: config/tc-sh.c:2689
+msgid "bad combined pmuls output operand"
+msgstr "operando de salida pmuls mal combinado"
 
-#: config/tc-sh.c:2262
+#: config/tc-sh.c:2699
 msgid "destination register is same for parallel insns"
 msgstr "el registro de destino es el mismo para instrucciones paralelas"
 
-#: config/tc-sh.c:2271
+#: config/tc-sh.c:2708
 msgid "condition not followed by conditionalizable insn"
 msgstr "la condición no está seguida por una instrucción condicionalizable"
 
-#: config/tc-sh.c:2281
+#: config/tc-sh.c:2718
 msgid "unrecognized characters at end of parallel processing insn"
 msgstr "caracteres no reconocidos al final de la instrucción de procesamiento paralelo"
 
-#: config/tc-sh.c:2417
+#: config/tc-sh.c:2834
+msgid "opcode not valid for this cpu variant"
+msgstr "el código de operación no es válido para esta variante de cpu"
+
+#: config/tc-sh.c:2867
+msgid "Delayed branches not available on SH1"
+msgstr "Las ramificaciones postergadas no están disponibles en SH1"
+
+#: config/tc-sh.c:2899
 #, c-format
 msgid "excess operands: '%s'"
 msgstr "exceso de operandos: '%s'"
 
-#: config/tc-sh.c:2569
+#: config/tc-sh.c:3026
 msgid ".uses pseudo-op seen when not relaxing"
 msgstr "se vio el pseudo-operador .uses cuando no se estaba relajando"
 
-#: config/tc-sh.c:2575
+#: config/tc-sh.c:3032
 msgid "bad .uses format"
 msgstr "formato de .uses erróneo"
 
-#: config/tc-sh.c:2654
+#: config/tc-sh.c:3130
 msgid "Invalid combination: --isa=SHcompact with --isa=SHmedia"
 msgstr "Combinación inválida: --isa=SHcompact con --isa=SHmedia"
 
-#: config/tc-sh.c:2660
+#: config/tc-sh.c:3136
 msgid "Invalid combination: --isa=SHmedia with --isa=SHcompact"
 msgstr "Combinación inválida: --isa=SHmedia con --isa=SHcompact"
 
-#: config/tc-sh.c:2662
+#: config/tc-sh.c:3138
 msgid "Invalid combination: --abi=64 with --isa=SHcompact"
 msgstr "Combinación inválida: --abi=64 con --isa=SHcompact"
 
-#: config/tc-sh.c:2675
+#: config/tc-sh.c:3179
 msgid "Invalid combination: --abi=32 with --abi=64"
 msgstr "Combinación inválida: --abi=32 con --abi=64"
 
-#: config/tc-sh.c:2681
+#: config/tc-sh.c:3185
 msgid "Invalid combination: --abi=64 with --abi=32"
 msgstr "Combinación inválida: --abi=64 con --abi=32"
 
-#: config/tc-sh.c:2683
+#: config/tc-sh.c:3187
 msgid "Invalid combination: --isa=SHcompact with --abi=64"
 msgstr "Combinación inválida: --isa=SHcompact con --abi=64"
 
-#: config/tc-sh.c:2718
+#: config/tc-sh.c:3221
+#, c-format
 msgid ""
 "SH options:\n"
-"-little\t\t\tgenerate little endian code\n"
-"-big\t\t\tgenerate big endian code\n"
-"-relax\t\t\talter jump instructions for long displacements\n"
-"-small\t\t\talign sections to 4 byte boundaries, not 16\n"
-"-dsp\t\t\tenable sh-dsp insns, and disable sh2e/sh3e/sh4 insns.\n"
+"--little\t\tgenerate little endian code\n"
+"--big\t\t\tgenerate big endian code\n"
+"--relax\t\t\talter jump instructions for long displacements\n"
+"--renesas\t\tdisable optimization with section symbol for\n"
+"\t\t\tcompatibility with Renesas assembler.\n"
+"--small\t\t\talign sections to 4 byte boundaries, not 16\n"
+"--dsp\t\t\tenable sh-dsp insns, and disable floating-point ISAs.\n"
+"--allow-reg-prefix\tallow '$' as a register name prefix.\n"
+"--isa=[any\t\tuse most appropriate isa\n"
+"    | dsp               same as '-dsp'\n"
+"    | fp"
 msgstr ""
 "Opciones de SH:\n"
-"-little\t\t\tgenera código little endian\n"
-"-big\t\t\tgenera código big endian\n"
-"-relax\t\t\taltera las instrucciones de salto para desubicaciones long\n"
-"-small\t\t\talinea las secciones a límites de 4 bytes, no 16\n"
-"-dsp\t\t\tactiva instrucciones sh-dsp, y desactiva instrucciones sh2e/sh3e/sh4.\n"
+"--little\t\t\tgenera código little endian\n"
+"--big\t\t\tgenera código big endian\n"
+"--relax\t\t\taltera las instrucciones de salto para\n"
+"\t\t\tdesubicaciones long\n"
+"--renesas\t\tdesactiva la optimización con símbolos de\n"
+"\t\t\tsección por compatibilidad con el ensamblador Renesas.\n"
+"--small\t\t\talinea las secciones a límites de 4 bytes, no 16\n"
+"--dsp\t\t\tactiva insns sh-dsp, y desactiva ISAs de coma flotante.\n"
+"--isa=[any\t\tusa la isa más apropiada\n"
+"    | dsp               igual que '-dsp'\n"
+"    | fp"
+
+#: config/tc-sh.c:3247
+#, c-format
+msgid ""
+"--isa=[shmedia\t\tset as the default instruction set for SH64\n"
+"    | SHmedia\n"
+"    | shcompact\n"
+"    | SHcompact]\n"
+msgstr ""
+"--isa=[shmedia\t\testablece el conjunto de instrucciones por defecto\n"
+"              \t\tpara SH64\n"
+"    | SHmedia\n"
+"    | shcompact\n"
+"    | SHcompact]\n"
 
-#: config/tc-sh.c:2726
+#: config/tc-sh.c:3252
+#, c-format
 msgid ""
-"-isa=[shmedia\t\tset default instruction set for SH64\n"
-"      | SHmedia\n"
-"      | shcompact\n"
-"      | SHcompact]\n"
-"-abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
+"--abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
 "\t\t\tfile type\n"
-"-shcompact-const-crange\temit code-range descriptors for constants in\n"
+"--shcompact-const-crange  emit code-range descriptors for constants in\n"
 "\t\t\tSHcompact code sections\n"
-"-no-mix\t\t\tdisallow SHmedia code in the same section as\n"
+"--no-mix\t\tdisallow SHmedia code in the same section as\n"
 "\t\t\tconstants and SHcompact code\n"
-"-no-expand\t\tdo not expand MOVI, PT, PTA or PTB instructions\n"
-"-expand-pt32\t\twith -abi=64, expand PT, PTA and PTB instructions\n"
-"\t\t\tto 32 bits only"
+"--no-expand\t\tdo not expand MOVI, PT, PTA or PTB instructions\n"
+"--expand-pt32\t\twith -abi=64, expand PT, PTA and PTB instructions\n"
+"\t\t\tto 32 bits only\n"
 msgstr ""
-"-isa=[shmedia\t\testablece el conjunto de instrucciones por omisión\n"
-"             \t\tpara SH64\n"
-"      | SHmedia\n"
-"      | shcompact\n"
-"      | SHcompact]\n"
-"-abi=[32|64]\t\testablece el tamaño de los operandos SHmedia\n"
+"--abi=[32|64]\t\testablece el tamaño de los operandos SHmedia\n"
 "\t\t\texpandidos y el tipo del fichero objeto\n"
-"-shcompact-const-crange\temite descriptores de código-rango para\n"
+"--shcompact-const-crange\temite descriptores de código-rango para\n"
 "\t\t\tconstantes en las secciones de código SHcompact\n"
-"-no-mix\t\t\tdesactiva el código SHmedia en la misma sección que\n"
+"--no-mix\t\t\tdesactiva el código SHmedia en la misma sección que\n"
 "\t\t\tlas constantes y el código SHcompact\n"
-"-no-expand\t\tno expande las instrucciones MOVI, PT, PTA ó PTB\n"
-"-expand-pt32\t\tcon -abi=64, expande las instrucciones PT, PTA y PTB\n"
-"\t\t\tsolamente a 32 bits"
+"--no-expand\t\tno expande las instrucciones MOVI, PT, PTA ó PTB\n"
+"--expand-pt32\t\tcon -abi=64, expande las instrucciones PT, PTA y PTB\n"
+"\t\t\tsolamente a 32 bits\n"
 
-#: config/tc-sh.c:2823
+#: config/tc-sh.c:3336
 msgid ".uses does not refer to a local symbol in the same section"
 msgstr ".uses no se refiere a un símbolo local en la misma sección"
 
-#: config/tc-sh.c:2842
+#: config/tc-sh.c:3355
 msgid "can't find fixup pointed to by .uses"
 msgstr "no se puede encontrar la compostura señalada por .uses"
 
-#: config/tc-sh.c:2865
+#: config/tc-sh.c:3375
 msgid ".uses target does not refer to a local symbol in the same section"
 msgstr "el objetivo .uses no se refiere a un símbolo local en la misma sección"
 
-#: config/tc-sh.c:2967
+#: config/tc-sh.c:3452
 msgid "displacement overflows 12-bit field"
 msgstr "la desubicación desborda el campo de 12-bits"
 
-#: config/tc-sh.c:2970
+#: config/tc-sh.c:3455
 #, c-format
 msgid "displacement to defined symbol %s overflows 12-bit field"
 msgstr "la desubicación del símbolo definido %s desborda el campo de 12-bits"
 
-#: config/tc-sh.c:2974
+#: config/tc-sh.c:3459
 #, c-format
 msgid "displacement to undefined symbol %s overflows 12-bit field"
 msgstr "la desubicación del símbolo indefinido %s desborda el campo de 12-bits"
 
-#: config/tc-sh.c:3052
+#: config/tc-sh.c:3532
 msgid "displacement overflows 8-bit field"
 msgstr "la desubicación desborda el campo de 8-bits"
 
-#: config/tc-sh.c:3055
+#: config/tc-sh.c:3535
 #, c-format
 msgid "displacement to defined symbol %s overflows 8-bit field"
 msgstr "la desubicación del símbolo definido %s desborda el campo de 8-bits"
 
-#: config/tc-sh.c:3059
+#: config/tc-sh.c:3539
 #, c-format
 msgid "displacement to undefined symbol %s overflows 8-bit field "
 msgstr "la desubicación del símbolo indefinido %s desborda el campo de 8-bits"
 
-#: config/tc-sh.c:3076
+#: config/tc-sh.c:3556
 #, c-format
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr "desbordamiento en la ramificación a %s; se convirtió en una secuencia de instrucciones más larga"
 
-#: config/tc-sh.c:3151 config/tc-sh.c:3199 config/tc-sparc.c:4192
-#: config/tc-sparc.c:4217
+#: config/tc-sh.c:3622 config/tc-sh.c:3669 config/tc-sparc.c:4234
+#: config/tc-sparc.c:4259
 msgid "misaligned data"
 msgstr "datos desalineados"
 
-#: config/tc-sh.c:3585
+#: config/tc-sh.c:4076
 msgid "misaligned offset"
 msgstr "desplazamiento desalineado"
 
-#: config/tc-sh64.c:596
-msgid "This operand must be constant at assembly time"
-msgstr "El operando debe ser una constante al momento de ensamblar"
-
-#: config/tc-sh64.c:711
-msgid "Invalid operand expression"
-msgstr "Expresión de operando inválido"
-
-#: config/tc-sh64.c:798 config/tc-sh64.c:904
-msgid "PTB operand is a SHmedia symbol"
-msgstr "El operando PTB es un símbolo SHmedia"
-
-#: config/tc-sh64.c:801 config/tc-sh64.c:901
-msgid "PTA operand is a SHcompact symbol"
-msgstr "El operando PTA es un símbolo SHcompact"
-
-#: config/tc-sh64.c:817
-msgid "invalid expression in operand"
-msgstr "expresión inválida en el operando"
-
-#: config/tc-sh64.c:1514
-#, c-format
-msgid "invalid operand, not a 5-bit unsigned value: %d"
-msgstr "operando inválido, no es un valor de 5-bit sin signo: %d"
-
-#: config/tc-sh64.c:1519
-#, c-format
-msgid "invalid operand, not a 6-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 6-bit con signo: %d"
-
-#: config/tc-sh64.c:1524
-#, c-format
-msgid "invalid operand, not a 6-bit unsigned value: %d"
-msgstr "operando inválido, no es un valor de 6-bit sin signo: %d"
-
-#: config/tc-sh64.c:1529 config/tc-sh64.c:1541
-#, c-format
-msgid "invalid operand, not a 11-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 11-bit con signo: %d"
-
-#: config/tc-sh64.c:1531
-#, c-format
-msgid "invalid operand, not a multiple of 32: %d"
-msgstr "operando inválido, no es un múltiplo de 32: %d"
-
-#: config/tc-sh64.c:1536
-#, c-format
-msgid "invalid operand, not a 10-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 10-bit con signo: %d"
-
-#: config/tc-sh64.c:1543
-#, c-format
-msgid "invalid operand, not an even value: %d"
-msgstr "operando inválido, no es un valor impar: %d"
-
-#: config/tc-sh64.c:1548
-#, c-format
-msgid "invalid operand, not a 12-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 12-bit con signo: %d"
-
-#: config/tc-sh64.c:1550
-#, c-format
-msgid "invalid operand, not a multiple of 4: %d"
-msgstr "operando inválido, no es un múltiplo de 4: %d"
-
-#: config/tc-sh64.c:1555
-#, c-format
-msgid "invalid operand, not a 13-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 13-bit con signo: %d"
-
-#: config/tc-sh64.c:1557
-#, c-format
-msgid "invalid operand, not a multiple of 8: %d"
-msgstr "operando inválido, no es un múltiplo de 8: %d"
-
-#: config/tc-sh64.c:1562
-#, c-format
-msgid "invalid operand, not a 16-bit signed value: %d"
-msgstr "operando inválido, no es un valor de 16-bit con signo: %d"
-
-#: config/tc-sh64.c:1567
-#, c-format
-msgid "invalid operand, not an 16-bit unsigned value: %d"
-msgstr "operando inválido, no es un valor de 16-bit sin signo: %d"
-
-#: config/tc-sh64.c:1573
-msgid "operand out of range for PT, PTA and PTB"
-msgstr "operando fuera de rango para PT, PTA y PTB"
-
-#: config/tc-sh64.c:1575
-#, c-format
-msgid "operand not a multiple of 4 for PT, PTA or PTB: %d"
-msgstr "el operando no es un múltiplo de 4 para PT, PTA o PTB: %d"
-
-#: config/tc-sh64.c:2103
-#, c-format
-msgid "MOVI operand is not a 32-bit signed value: 0x%8x%08x"
-msgstr "el operando MOVI no es un valor de 32-bit con signo: 0x%8x%08x"
-
-#: config/tc-sh64.c:2466 config/tc-sh64.c:2631 config/tc-sh64.c:2646
-msgid "invalid PIC reference"
-msgstr "referencia PIC inválida"
-
-#: config/tc-sh64.c:2524
-msgid "can't find opcode"
-msgstr "no se puede encontrar el código de operación"
-
-#: config/tc-sh64.c:2854
-#, c-format
-msgid "invalid operands to %s"
-msgstr "operandos inválidos para %s"
-
-#: config/tc-sh64.c:2860
-#, c-format
-msgid "excess operands to %s"
-msgstr "exceso de operandos para %s"
-
-#: config/tc-sh64.c:2906
-#, c-format
-msgid "The `.mode %s' directive is not valid with this architecture"
-msgstr "La directiva `.mode %s' no es válida para esta arquitectura"
-
-#: config/tc-sh64.c:2914
-#, c-format
-msgid "Invalid argument to .mode: %s"
-msgstr "Argumento inválido para .mode: %s"
-
-#: config/tc-sh64.c:2945
-#, c-format
-msgid "The `.abi %s' directive is not valid with this architecture"
-msgstr "La directiva `.abi %s' no es válida para esta arquitectura"
-
-#: config/tc-sh64.c:2951
-msgid "`.abi 64' but command-line options do not specify 64-bit ABI"
-msgstr "`.abi 64' pero las opciones de la línea de órdenes no especifica la ABI de 64-bit"
-
-#: config/tc-sh64.c:2956
-msgid "`.abi 32' but command-line options do not specify 32-bit ABI"
-msgstr "`.abi 32' pero las opciones de la línea de órdenes no especifica la ABI de 32-bit"
-
-#: config/tc-sh64.c:2959
-#, c-format
-msgid "Invalid argument to .abi: %s"
-msgstr "Argumento inválido para .abi: %s"
-
-#: config/tc-sh64.c:3014
-msgid "-no-mix is invalid without specifying SHcompact or SHmedia"
-msgstr "-no-mix es inválido sin especificar SHcompact o SHmedia"
-
-#: config/tc-sh64.c:3019
-msgid "-shcompact-const-crange is invalid without SHcompact"
-msgstr "-shcompact-const-crange es inválido sin SHcompact"
-
-#: config/tc-sh64.c:3022
-msgid "-expand-pt32 only valid with -abi=64"
-msgstr "-expand-pt32 sólo es válido con -abi=64"
-
-#: config/tc-sh64.c:3025
-msgid "-no-expand only valid with SHcompact or SHmedia"
-msgstr "-no-expand sólo es válido con SHcompact o SHmedia"
-
-#: config/tc-sh64.c:3028
-msgid "-expand-pt32 invalid together with -no-expand"
-msgstr "-expand-pt32 es inválido junto con -no-expand"
-
-#: config/tc-sh64.c:3250
-msgid "SHmedia code not allowed in same section as constants and SHcompact code"
-msgstr "No se permite código SHmedia en la misma sección que las constantes y el código SHcompact"
-
-#: config/tc-sh64.c:3268
-msgid "No segment info for current section"
-msgstr "No hay información de segmento para la sección actual"
-
-#: config/tc-sh64.c:3310
-msgid "duplicate datalabel operator ignored"
-msgstr "se ignora el operador datalabel duplicado"
-
-#: config/tc-sh64.c:3380
-msgid "Invalid DataLabel expression"
-msgstr "Expresión DataLabel inválida"
-
-#: config/tc-sparc.c:287
+#: config/tc-sparc.c:288
 msgid "Invalid default architecture, broken assembler."
-msgstr "Arquitectura por omisión inválida, ensamblador descompuesto."
+msgstr "Arquitectura por defecto inválida, ensamblador descompuesto."
 
-#: config/tc-sparc.c:291 config/tc-sparc.c:494
+#: config/tc-sparc.c:292 config/tc-sparc.c:495
 msgid "Bad opcode table, broken assembler."
 msgstr "Tabla de códigos de operación errónea, ensamblador descompuesto."
 
-#: config/tc-sparc.c:486
+#: config/tc-sparc.c:487
 #, c-format
 msgid "invalid architecture -xarch=%s"
 msgstr "arquitectura -xarch=%s inválida"
 
-#: config/tc-sparc.c:488
+#: config/tc-sparc.c:489
 #, c-format
 msgid "invalid architecture -A%s"
 msgstr "arquitectura inválida -A%s"
 
-#: config/tc-sparc.c:555
+#: config/tc-sparc.c:556
 #, c-format
 msgid "No compiled in support for %d bit object file format"
 msgstr "No se compiló el soporte para el formato de fichero objeto de %d bit"
 
-#: config/tc-sparc.c:592
-msgid "Unrecognized option following -K"
-msgstr "Opción no reconocida a continuación de -K"
-
-#: config/tc-sparc.c:633
+#: config/tc-sparc.c:634
+#, c-format
 msgid "SPARC options:\n"
 msgstr "Opciones SPARC:\n"
 
-#: config/tc-sparc.c:662
+#: config/tc-sparc.c:663
+#, c-format
 msgid ""
 "\n"
 "\t\t\tspecify variant of SPARC architecture\n"
@@ -8623,14 +9381,16 @@ msgstr ""
 "-bump\t\t\tavisa cuando el ensamblador cambia entre arquitecturas\n"
 "-sparc\t\t\tse ignora\n"
 "--enforce-aligned-data\tfuerza .long, etc., a ser alineados correctamente\n"
-"-relax\t\t\trelaja saltos y ramificaciones (por omisión)\n"
+"-relax\t\t\trelaja saltos y ramificaciones (por defecto)\n"
 "-no-relax\t\tevita cambiar cualquier salto y ramificación\n"
 
-#: config/tc-sparc.c:670
+#: config/tc-sparc.c:671
+#, c-format
 msgid "-k\t\t\tgenerate PIC\n"
 msgstr "-k\t\t\tgenera PIC\n"
 
-#: config/tc-sparc.c:674
+#: config/tc-sparc.c:675
+#, c-format
 msgid ""
 "-32\t\t\tcreate 32 bit object file\n"
 "-64\t\t\tcreate 64 bit object file\n"
@@ -8638,12 +9398,13 @@ msgstr ""
 "-32\t\t\tcrea ficheros objeto de 32 bits\n"
 "-64\t\t\tcrea ficheros objeto de 64 bits\n"
 
-#: config/tc-sparc.c:677
+#: config/tc-sparc.c:678
 #, c-format
 msgid "\t\t\t[default is %d]\n"
-msgstr "\t\t\t[por omisión es %d]\n"
+msgstr "\t\t\t[por defecto es %d]\n"
 
-#: config/tc-sparc.c:679
+#: config/tc-sparc.c:680
+#, c-format
 msgid ""
 "-TSO\t\t\tuse Total Store Ordering\n"
 "-PSO\t\t\tuse Partial Store Ordering\n"
@@ -8653,12 +9414,13 @@ msgstr ""
 "-PSO\t\t\tusa el Ordenamiento de Almacenamiento Parcial\n"
 "-RMO\t\t\tusa el Ordenamiento de Memoria Relajado\n"
 
-#: config/tc-sparc.c:683
+#: config/tc-sparc.c:684
 #, c-format
 msgid "\t\t\t[default is %s]\n"
-msgstr "\t\t\t[por omisión es %s]\n"
+msgstr "\t\t\t[por defecto es %s]\n"
 
-#: config/tc-sparc.c:685
+#: config/tc-sparc.c:686
+#, c-format
 msgid ""
 "-KPIC\t\t\tgenerate PIC\n"
 "-V\t\t\tprint assembler version number\n"
@@ -8673,14 +9435,15 @@ msgstr ""
 "-KPIC\t\t\tgenera PIC\n"
 "-V\t\t\tmuestra el número de versión del ensamblador\n"
 "-undeclared-regs\tignora el uso del registro global de aplicaciones sin\n"
-"\t\t\tla directiva .register apropiada (por omisión)\n"
+"\t\t\tla directiva .register apropiada (por defecto)\n"
 "-no-undeclared-regs\tfuerza un error en el uso del registro global de\n"
 "\t\t\taplicaciones sin una directiva .register apropiada\n"
 "-q\t\t\tse ignora\n"
 "-Qy, -Qn\t\tse ignora\n"
 "-s\t\t\tignored\n"
 
-#: config/tc-sparc.c:697
+#: config/tc-sparc.c:698
+#, c-format
 msgid ""
 "-EL\t\t\tgenerate code for a little endian machine\n"
 "-EB\t\t\tgenerate code for a big endian machine\n"
@@ -8692,1399 +9455,1151 @@ msgstr ""
 "--little-endian-data\tgenera código para una máquina que tenga instrucciones\n"
 "                        big endian y datos little endian.\n"
 
-#: config/tc-sparc.c:817
+#: config/tc-sparc.c:819
 #, c-format
 msgid "Internal error: losing opcode: `%s' \"%s\"\n"
 msgstr "Error interno: se pierde el código de operación: `%s' \"%s\"\n"
 
-#: config/tc-sparc.c:836
+#: config/tc-sparc.c:838
 #, c-format
 msgid "Internal error: can't find opcode `%s' for `%s'\n"
 msgstr "Error interno: no se puede encontrar el código de operación `%s' para `%s'\n"
 
-#: config/tc-sparc.c:982
+#: config/tc-sparc.c:984
 msgid "Support for 64-bit arithmetic not compiled in."
 msgstr "No se compiló el soporte para aritmética de 64-bit."
 
-#: config/tc-sparc.c:1029
+#: config/tc-sparc.c:1031
 msgid "set: number not in 0..4294967295 range"
 msgstr "set: el número no está en el rango 0..4294967295"
 
-#: config/tc-sparc.c:1036
+#: config/tc-sparc.c:1038
 msgid "set: number not in -2147483648..4294967295 range"
 msgstr "set: el número no está en el rango -2147483648..4294967295"
 
-#: config/tc-sparc.c:1096
+#: config/tc-sparc.c:1098
 msgid "setsw: number not in -2147483648..4294967295 range"
 msgstr "setsw: el número no está en el rango -2147483648..4294967295"
 
-#: config/tc-sparc.c:1145
+#: config/tc-sparc.c:1147
 msgid "setx: temporary register same as destination register"
 msgstr "setx: el registro temporal es el mismo que el registro destino"
 
-#: config/tc-sparc.c:1216
+#: config/tc-sparc.c:1218
 msgid "setx: illegal temporary register g0"
 msgstr "setx: registro temporal ilegal g0"
 
-#: config/tc-sparc.c:1313
+#: config/tc-sparc.c:1316
 msgid "FP branch in delay slot"
 msgstr "ramificación FP en la ranura de retraso"
 
-#: config/tc-sparc.c:1329
+#: config/tc-sparc.c:1331
 msgid "FP branch preceded by FP instruction; NOP inserted"
 msgstr "ramificación FP precedida por una instrucción FP; se insertó NOP"
 
-#: config/tc-sparc.c:1369
+#: config/tc-sparc.c:1371
 msgid "failed special case insn sanity check"
 msgstr "falló la prueba de sanidad de la instrucción especial case"
 
-#: config/tc-sparc.c:1457
+#: config/tc-sparc.c:1461
 msgid ": invalid membar mask name"
 msgstr ": nombre de máscara de barra de memoria inválido"
 
-#: config/tc-sparc.c:1473
+#: config/tc-sparc.c:1477
 msgid ": invalid membar mask expression"
 msgstr ": expresión de máscara de barra de memoria inválida"
 
-#: config/tc-sparc.c:1478
+#: config/tc-sparc.c:1482
 msgid ": invalid membar mask number"
 msgstr ": número de máscara de barra de memoria inválido"
 
-#: config/tc-sparc.c:1493
+#: config/tc-sparc.c:1497
 msgid ": invalid siam mode expression"
 msgstr ": expresión de modo siam inválida"
 
-#: config/tc-sparc.c:1498
+#: config/tc-sparc.c:1502
 msgid ": invalid siam mode number"
 msgstr ": número de modi siam inválido"
 
-#: config/tc-sparc.c:1514
+#: config/tc-sparc.c:1518
 msgid ": invalid prefetch function name"
 msgstr ": nombre de función de precargado inválido"
 
-#: config/tc-sparc.c:1522
+#: config/tc-sparc.c:1526
 msgid ": invalid prefetch function expression"
 msgstr ": expresión de función de precargado inválida"
 
-#: config/tc-sparc.c:1527
+#: config/tc-sparc.c:1531
 msgid ": invalid prefetch function number"
 msgstr ": número de función de precargado inválido"
 
-#: config/tc-sparc.c:1555 config/tc-sparc.c:1567
+#: config/tc-sparc.c:1559 config/tc-sparc.c:1571
 msgid ": unrecognizable privileged register"
 msgstr ": registro privilegiado no reconocible"
 
-#: config/tc-sparc.c:1591 config/tc-sparc.c:1616
+#: config/tc-sparc.c:1595 config/tc-sparc.c:1620
 msgid ": unrecognizable v9a or v9b ancillary state register"
 msgstr ": registro de estado ancilar v9a o v9b no reconocible"
 
-#: config/tc-sparc.c:1596
+#: config/tc-sparc.c:1600
 msgid ": rd on write only ancillary state register"
 msgstr ": rd en registro de estado ancilar de sólo escritura"
 
 #. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1604
+#: config/tc-sparc.c:1608
 msgid ": unrecognizable v9a ancillary state register"
 msgstr ": registro de estado ancilar v9a no reconocible"
 
-#: config/tc-sparc.c:1640
+#: config/tc-sparc.c:1644
 msgid ": asr number must be between 16 and 31"
 msgstr ": el número asr debe estar entre 16 y 31"
 
-#: config/tc-sparc.c:1648
+#: config/tc-sparc.c:1652
 msgid ": asr number must be between 0 and 31"
 msgstr ": el número asr debe estar entre 0 y 31"
 
-#: config/tc-sparc.c:1658
+#: config/tc-sparc.c:1662
 #, c-format
 msgid ": expecting %asrN"
 msgstr ": se esperaba %asrN"
 
-#: config/tc-sparc.c:1840 config/tc-sparc.c:1878 config/tc-sparc.c:2279
-#: config/tc-sparc.c:2315
+#: config/tc-sparc.c:1844 config/tc-sparc.c:1882 config/tc-sparc.c:2289
+#: config/tc-sparc.c:2325
 #, c-format
 msgid "Illegal operands: %%%s requires arguments in ()"
 msgstr "Operandos ilegales: %%%s requiere de argumentos en ()"
 
-#: config/tc-sparc.c:1846
+#: config/tc-sparc.c:1850
 #, c-format
 msgid "Illegal operands: %%%s cannot be used together with other relocs in the insn ()"
 msgstr "Operandos ilegales: %%%s no se puede usar junto con otras reubicaciones en la insn ()"
 
-#: config/tc-sparc.c:1857
+#: config/tc-sparc.c:1861
 #, c-format
 msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
 msgstr "Operando ilegales: %%%s sólo se puede usar con la llamada __tls_get_addr"
 
-#: config/tc-sparc.c:2064
+#: config/tc-sparc.c:2068
 msgid "detected global register use not covered by .register pseudo-op"
 msgstr "se detectó el uso de un registro global que no está cubierto por el pseudo-operador .register"
 
-#: config/tc-sparc.c:2135
+#: config/tc-sparc.c:2139
 msgid ": There are only 64 f registers; [0-63]"
 msgstr ": Solamente hay 64 registros f; [0-63]"
 
-#: config/tc-sparc.c:2137 config/tc-sparc.c:2149
+#: config/tc-sparc.c:2141 config/tc-sparc.c:2159
 msgid ": There are only 32 f registers; [0-31]"
 msgstr ": Solamente hay 32 registros f; [0-31]"
 
-#: config/tc-sparc.c:2327
+#: config/tc-sparc.c:2151
+msgid ": There are only 32 single precision f registers; [0-31]"
+msgstr ": Solamente hay 32 registros f de precisión sencilla; [0-31]"
+
+#: config/tc-sparc.c:2337
 #, c-format
 msgid "Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
 msgstr "Operandos ilegales: No se puede hacer aritmética aparte de + y - que involucre %%%s()"
 
-#: config/tc-sparc.c:2437
+#: config/tc-sparc.c:2447
 #, c-format
 msgid "Illegal operands: Can't add non-constant expression to %%%s()"
 msgstr "Operandos ilegales: No se puede agregar una expresión que no es constante a %%%s()"
 
-#: config/tc-sparc.c:2447
+#: config/tc-sparc.c:2457
 #, c-format
 msgid "Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"
 msgstr "Operandos ilegales: No se puede hacer aritmética que involucre a %%%s() de un símbolo reubicable"
 
-#: config/tc-sparc.c:2465
+#: config/tc-sparc.c:2475
 msgid ": PC-relative operand can't be a constant"
 msgstr ": el operando relativo al PC no puede ser una constante"
 
-#: config/tc-sparc.c:2472
+#: config/tc-sparc.c:2482
 msgid ": TLS operand can't be a constant"
 msgstr ": el operando TLS no puede ser una constante"
 
-#: config/tc-sparc.c:2505
+#: config/tc-sparc.c:2515
 msgid ": invalid ASI name"
 msgstr ": nombre ASI inválido"
 
-#: config/tc-sparc.c:2513
+#: config/tc-sparc.c:2523
 msgid ": invalid ASI expression"
 msgstr ": expresión ASI inválida"
 
-#: config/tc-sparc.c:2518
+#: config/tc-sparc.c:2528
 msgid ": invalid ASI number"
 msgstr ": número ASI inválido"
 
-#: config/tc-sparc.c:2615
+#: config/tc-sparc.c:2625
 msgid "OPF immediate operand out of range (0-0x1ff)"
 msgstr "operador inmediato OPF fuera de rango (0-0x1ff)"
 
-#: config/tc-sparc.c:2620
+#: config/tc-sparc.c:2630
 msgid "non-immediate OPF operand, ignored"
 msgstr "operando OPF que no es inmediato, se ignora"
 
-#: config/tc-sparc.c:2639
+#: config/tc-sparc.c:2649
 msgid ": invalid cpreg name"
 msgstr ": nombre cpreg inválido"
 
-#: config/tc-sparc.c:2668
+#: config/tc-sparc.c:2678
 #, c-format
 msgid "Illegal operands%s"
 msgstr "Operando%s ilegal(es)"
 
-#: config/tc-sparc.c:2702
+#: config/tc-sparc.c:2712
 #, c-format
 msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
 msgstr "la arquitectura saltó de \"%s\" a \"%s\" en \"%s\""
 
-#: config/tc-sparc.c:2738
+#: config/tc-sparc.c:2748
 #, c-format
 msgid "Architecture mismatch on \"%s\"."
 msgstr "No hay coincidencia de arquitectura en \"%s\"."
 
-#: config/tc-sparc.c:2739
+#: config/tc-sparc.c:2749
 #, c-format
 msgid " (Requires %s; requested architecture is %s.)"
 msgstr " (Se requiere %s; la arquitectura solicitada es %s.)"
 
-#: config/tc-sparc.c:3325
+#: config/tc-sparc.c:3369
 #, c-format
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr "tipo de reubicación errónea o sin manejar: 0x%02x"
 
-#: config/tc-sparc.c:3480
-#, c-format
-msgid "internal error: can't export reloc type %d (`%s')"
-msgstr "error interno: no se puede exportar el tipo de reubicación %d (`%s')"
+#: config/tc-sparc.c:3679
+msgid "Expected comma after name"
+msgstr "Se esperaba una coma después del nombre"
 
-#: config/tc-sparc.c:3644
+#: config/tc-sparc.c:3688
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr "¡Longitud BSS (%d.) <0! Se ignora."
 
-#: config/tc-sparc.c:3656
+#: config/tc-sparc.c:3700
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr "segmento .reserve erróneo -- se esperaba el segmento BSS"
 
-#: config/tc-sparc.c:3673 read.c:2048
+#: config/tc-sparc.c:3717
 msgid "missing alignment"
 msgstr "falta la alineación"
 
-#: config/tc-sparc.c:3684 config/tc-sparc.c:3835
+#: config/tc-sparc.c:3728
 #, c-format
 msgid "alignment too large; assuming %d"
 msgstr "alineación demasiado grande; se asume %d"
 
-#: config/tc-sparc.c:3690 config/tc-sparc.c:3841
+#: config/tc-sparc.c:3734 config/tc-sparc.c:3885
 msgid "negative alignment"
 msgstr "alineación negativa"
 
-#: config/tc-sparc.c:3700 config/tc-sparc.c:3864 read.c:1251 read.c:2064
+#: config/tc-sparc.c:3744 config/tc-sparc.c:3908 read.c:1313 read.c:2143
 msgid "alignment not a power of 2"
 msgstr "la alineación no es una potencia de 2"
 
-#: config/tc-sparc.c:3778 config/tc-v850.c:233
+#: config/tc-sparc.c:3822 config/tc-v850.c:223
 msgid "Expected comma after symbol-name"
 msgstr "Se esperaba una coma después del nombre del símbolo"
 
-#: config/tc-sparc.c:3788 read.c:1392
+#: config/tc-sparc.c:3832
 #, c-format
 msgid ".COMMon length (%lu) out of range ignored"
 msgstr "se ignora la longitud .COMMún (%lu) fuera de rango"
 
-#: config/tc-sparc.c:3807 config/tc-v850.c:266
-#, c-format
-msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
-msgstr "La longitud de .comm \"%s\" ya es %ld. No se cambia a %d."
-
-#: config/tc-sparc.c:3821
+#: config/tc-sparc.c:3865
 msgid "Expected comma after common length"
 msgstr "Se esperaba una coma después de la longitud común"
 
-#: config/tc-sparc.c:4062 config/tc-sparc.c:4072
+#: config/tc-sparc.c:3879
+#, c-format
+msgid "alignment too large; assuming %ld"
+msgstr "alineación demasiado grande; se asume %ld"
+
+#: config/tc-sparc.c:4025
+msgid "Unknown segment type"
+msgstr "Tipo de segmento desconocido"
+
+#: config/tc-sparc.c:4104 config/tc-sparc.c:4114
 #, c-format
 msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
 msgstr "la sintaxis de registro es .register %%g[2367],{#scratch|nombresimbolo|#ignore}"
 
-#: config/tc-sparc.c:4090
+#: config/tc-sparc.c:4132
 msgid "redefinition of global register"
 msgstr "redefinición del registro global"
 
-#: config/tc-sparc.c:4101
+#: config/tc-sparc.c:4143
 #, c-format
 msgid "Register symbol %s already defined."
 msgstr "El símbolo de registro %s ya estaba definido."
 
-#: config/tc-sparc.c:4310
+#: config/tc-sparc.c:4352
 #, c-format
 msgid "Illegal operands: %%r_plt in %d-byte data field"
 msgstr "Operandos ilegales: %%r_plt en el campo de datos de %d-bytes"
 
-#: config/tc-sparc.c:4320
+#: config/tc-sparc.c:4362
 #, c-format
 msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
 msgstr "Operandos ilegales: %%r_tls_dtpoff en el campo de datos de %d-bytes"
 
-#: config/tc-sparc.c:4357
+#: config/tc-sparc.c:4399
 #, c-format
 msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
 msgstr "Operandos ilegales: Sólo se permite %%r_%s%d en campos de datos de %d-bytes"
 
-#: config/tc-sparc.c:4365 config/tc-sparc.c:4396 config/tc-sparc.c:4405
+#: config/tc-sparc.c:4407 config/tc-sparc.c:4438 config/tc-sparc.c:4447
 #, c-format
 msgid "Illegal operands: %%r_%s%d requires arguments in ()"
 msgstr "Operandos ilegales: %%r_%s%d requiere argumentos en ()"
 
-#: config/tc-sparc.c:4414
+#: config/tc-sparc.c:4456
 #, c-format
 msgid "Illegal operands: garbage after %%r_%s%d()"
 msgstr "Operandos ilegales: hay basura después de %%r_%s%d()"
 
-#: config/tc-sparc.h:55
+#: config/tc-sparc.h:46
 msgid "sparc convert_frag\n"
 msgstr "convert_frag de sparc\n"
 
-#: config/tc-sparc.h:57
+#: config/tc-sparc.h:48
 msgid "estimate_size_before_relax called"
 msgstr "se llamó a estimate_size_before_relax"
 
-#: config/tc-tahoe.c:403
-msgid "The -a option doesn't exist. (Despite what the man page says!"
-msgstr "La opción -a no existe. (¡A pesar de lo que diga la página del manual!)"
-
-#: config/tc-tahoe.c:407 config/tc-vax.c:3285
-#, c-format
-msgid "Displacement length %s ignored!"
-msgstr "¡Se ignora la longitud de desubicación %s!"
-
-#: config/tc-tahoe.c:411 config/tc-vax.c:3277
-msgid "SYMBOL TABLE not implemented"
-msgstr "SYMBOL TABLE no está implementado"
-
-#: config/tc-tahoe.c:415 config/tc-vax.c:3281
-msgid "TOKEN TRACE not implemented"
-msgstr "TOKEN TRACE no está implementado"
-
-#: config/tc-tahoe.c:419 config/tc-vax.c:3289
-#, c-format
-msgid "I don't need or use temp. file \"%s\"."
-msgstr "No se necesita o se utiliza el fichero temporal \"%s\"."
-
-#: config/tc-tahoe.c:423 config/tc-vax.c:3293
-msgid "I don't use an interpass file! -V ignored"
-msgstr "¡No se usa un fichero entre pasos! Se ignora -V"
-
-#: config/tc-tahoe.c:437
-msgid ""
-"Tahoe options:\n"
-"-a\t\t\tignored\n"
-"-d LENGTH\t\tignored\n"
-"-J\t\t\tignored\n"
-"-S\t\t\tignored\n"
-"-t FILE\t\t\tignored\n"
-"-T\t\t\tignored\n"
-"-V\t\t\tignored\n"
-msgstr ""
-"Opciones de Tahoe:\n"
-"-a\t\t\tse ignora\n"
-"-d LENGTH\t\tse ignora\n"
-"-J\t\t\tse ignora\n"
-"-S\t\t\tse ignora\n"
-"-t FILE\t\t\tse ignora\n"
-"-T\t\t\tse ignora\n"
-"-V\t\t\tse ignora\n"
-
-#: config/tc-tahoe.c:1066
-msgid "Casting a branch displacement is bad form, and is ignored."
-msgstr "La conversión de una desubicación de ramificación es una forma errónea, y se ignora."
-
-#: config/tc-tahoe.c:1122
-msgid "Couldn't parse the [index] in this operand."
-msgstr "No se puede decodificar el [index] en este operando."
-
-#: config/tc-tahoe.c:1128
-msgid "Couldn't find the opening '[' for the index of this operand."
-msgstr "No se puede encontrar el '[' que abre para el índice de este operando."
-
-#: config/tc-tahoe.c:1168
-msgid "Couldn't find the opening '(' for the deref of this operand."
-msgstr "No se puede encontrar el '(' que abre para la dereferencia de este operando."
-
-#: config/tc-tahoe.c:1178
-msgid "Operand can't be both pre-inc and post-dec."
-msgstr "El operando no puede ser pre-incremento y post-decremento al mismo tiempo."
-
-#: config/tc-tahoe.c:1208
-msgid "I parsed 2 registers in this operand."
-msgstr "Se decodificaron 2 registros en este operando."
-
-#: config/tc-tahoe.c:1258
-msgid "Can't relocate expression error."
-msgstr "No se puede reubicar la expresión de error."
-
-#. This is an error. Tahoe doesn't allow any expressions
-#. bigger that a 32 bit long word. Any bigger has to be referenced
-#. by address.
-#: config/tc-tahoe.c:1265
-msgid "Expression is too large for a 32 bits."
-msgstr "La expresión es demasiado grande para 32 bits."
-
-#: config/tc-tahoe.c:1270
-msgid "Junk at end of expression."
-msgstr "Basura al final de la expresión."
-
-#: config/tc-tahoe.c:1309
-msgid "Syntax error in direct register mode."
-msgstr "Error sintáctico en el modo directo de registro."
-
-#: config/tc-tahoe.c:1311
-msgid "You can't index a register in direct register mode."
-msgstr "No se puede indizar un registro en el modo directo de registro."
-
-#: config/tc-tahoe.c:1314
-msgid "SP can't be the source operand with direct register addressing."
-msgstr "SP no puede ser el operando fuente con direccionamiento directo de registro."
-
-#: config/tc-tahoe.c:1316
-msgid "Can't take the address of a register."
-msgstr "No se puede tomar la dirección de un registro."
-
-#: config/tc-tahoe.c:1318
-msgid "Direct Register can't be used in a branch."
-msgstr "Un Registro Directo no se puede utilizar en una ramificación."
-
-#: config/tc-tahoe.c:1320
-msgid "For quad access, the register must be even and < 14."
-msgstr "Para acceso cuadrático, el registro debe ser par y < 14."
-
-#: config/tc-tahoe.c:1322
-msgid "You can't cast a direct register."
-msgstr "No se puede convertir un registro directo."
-
-# `tromp' se utiliza aquí como verbo transitivo. cfuga
-# Referencia: http://www.dictionary.com/search?q=tromp
-#: config/tc-tahoe.c:1328
-msgid "Using reg 14 for quadwords can tromp the FP register."
-msgstr "El uso del registro 14 para quadwords puede noquear el registro FP."
-
-#: config/tc-tahoe.c:1340
-msgid "Syntax error in auto-dec mode."
-msgstr "Error sintáctico en el modo auto-dec."
-
-#: config/tc-tahoe.c:1342
-msgid "You can't have an index auto dec mode."
-msgstr "No se puede tener un índice en modo auto dec"
-
-#: config/tc-tahoe.c:1344
-msgid "Auto dec mode cant be used for reading."
-msgstr "El modo auto dec no se puede usar para lectura."
-
-#: config/tc-tahoe.c:1346
-msgid "Auto dec only works of the SP register."
-msgstr "El modo auto dec solamente funciona en los registros SP."
-
-#: config/tc-tahoe.c:1348
-msgid "Auto dec can't be used in a branch."
-msgstr "No se puede utilizar auto dec en una ramificación."
-
-#: config/tc-tahoe.c:1350
-msgid "Auto dec won't work with quadwords."
-msgstr "Auto dec no funciona con quadwords."
-
-#: config/tc-tahoe.c:1357
-msgid "Syntax error in one of the auto-inc modes."
-msgstr "Error sintáctico en uno de los modos auto-inc."
-
-#: config/tc-tahoe.c:1363
-msgid "Auto inc deferred only works of the SP register."
-msgstr "El modo auto inc diferido solamente funciona en los registros SP."
-
-#: config/tc-tahoe.c:1365
-msgid "You can't have an index auto inc deferred mode."
-msgstr "No se puede tener un índice en modo auto inc diferido"
-
-#: config/tc-tahoe.c:1367 config/tc-tahoe.c:1378
-msgid "Auto inc can't be used in a branch."
-msgstr "No se puede utilizar auto inc en una ramificación."
-
-#: config/tc-tahoe.c:1374
-msgid "You can't write to an auto inc register."
-msgstr "No se puede escribir en un registro auto inc."
-
-#: config/tc-tahoe.c:1376
-msgid "Auto inc only works of the SP register."
-msgstr "El modo auto inc funciona solamente en los registros SP."
-
-#: config/tc-tahoe.c:1380
-msgid "Auto inc won't work with quadwords."
-msgstr "Auto inc no funciona con quadwords."
-
-#: config/tc-tahoe.c:1382
-msgid "You can't have an index in auto inc mode."
-msgstr "No se puede tener un índice en el modo auto inc."
-
-#: config/tc-tahoe.c:1390
-msgid "You can't index the sp register."
-msgstr "No se puede indizar el registro sp."
-
-#: config/tc-tahoe.c:1396
-msgid "Syntax error in register displaced mode."
-msgstr "Error sintáctico en el registro en modo desubicado."
-
-#: config/tc-tahoe.c:1415
-msgid "An offest is needed for this operand."
-msgstr "Se necesita un desplazamiento para este operando."
-
-#: config/tc-tahoe.c:1427
-msgid "You can't index a register in immediate mode."
-msgstr "No se puede indizar un registro en modo inmediato."
-
-#: config/tc-tahoe.c:1429
-msgid "Immediate access can't be used as an address."
-msgstr "No se puede utilizar el acceso inmediato como una dirección"
-
-#: config/tc-tahoe.c:1540
-#, c-format
-msgid "Compiler bug: ODD number of bytes in arg structure %s."
-msgstr "Bicho del compilador: número de bytes IMPAR en la estructura de argumentos %s."
-
-#: config/tc-tahoe.c:1567 config/tc-vax.c:1962
-msgid "Not enough operands"
-msgstr "No hay suficientes operandos"
-
-#: config/tc-tahoe.c:1577 config/tc-vax.c:1969
-msgid "Too many operands"
-msgstr "Demasiados operandos"
-
-#: config/tc-tahoe.c:1628 config/tc-vax.c:403
-#, c-format
-msgid "Ignoring statement due to \"%s\""
-msgstr "Se ignora la declaración debido a \"%s\""
-
-#: config/tc-tahoe.c:1723
-#, c-format
-msgid "Compliler bug: Got a case (%d) I wasn't expecting."
-msgstr "Bicho del compilador: Se obtuvo un case (%d) que no se esperaba."
-
-#: config/tc-tahoe.c:1817
-msgid "Real branch displacements must be expressions."
-msgstr "Las desubicaciones de ramificaciones reales deben ser expresiones."
-
-#: config/tc-tahoe.c:1820
-#, c-format
-msgid "Complier error: I got an unknown synthetic branch :%c"
-msgstr "Error del compilador: Se obtuvo una ramificación sintética desconocida :%c"
-
-# En México se utilizaría `guácala' por `barf', como una expresión
-# que simboliza vómito, pero no es comprensible para todos los
-# hispanoparlantes. :-)    cfuga
-#: config/tc-tahoe.c:1961
-#, c-format
-msgid "Barf, bad mode %x\n"
-msgstr "Ugh, modo erróneo %x\n"
-
 #. Only word (et al.), align, or conditionals are allowed within
 #. .struct/.union.
-#: config/tc-tic54x.c:224
+#: config/tc-tic54x.c:222
 msgid "pseudo-op illegal within .struct/.union"
 msgstr "pseudo-operación ilegal dentro de .struct/.union"
 
-#: config/tc-tic54x.c:349
+#: config/tc-tic54x.c:347
+#, c-format
 msgid "C54x-specific command line  options:\n"
 msgstr "Opciones de línea de comandos específicas de C54x:\n"
 
-#: config/tc-tic54x.c:350
+#: config/tc-tic54x.c:348
+#, c-format
 msgid "-mfar-mode | -mf          Use extended addressing\n"
 msgstr "-mfar-mode | -mf          Utiliza direccionamiento extendido\n"
 
-#: config/tc-tic54x.c:351
+#: config/tc-tic54x.c:349
+#, c-format
 msgid "-mcpu=<CPU version>       Specify the CPU version\n"
 msgstr "-mcpu=<versión CPU>       Especifica la versión del CPU\n"
 
-#: config/tc-tic54x.c:353
-msgid "-mcoff-version={0|1|2}    Select COFF version\n"
-msgstr "-mcoff-version={0|1|2}    Selecciona la versión de COFF\n"
-
-#: config/tc-tic54x.c:355
+#: config/tc-tic54x.c:350
+#, c-format
 msgid "-merrors-to-file <filename>\n"
 msgstr "-merrors-to-file <nombre fichero>\n"
 
-#: config/tc-tic54x.c:356
+#: config/tc-tic54x.c:351
+#, c-format
 msgid "-me <filename>            Redirect errors to a file\n"
 msgstr "-me <nombre fichero>      Redirige los errores a un fichero\n"
 
-#: config/tc-tic54x.c:478
+#: config/tc-tic54x.c:473
 msgid "Comma and symbol expected for '.asg STRING, SYMBOL'"
 msgstr "Se esperaban una coma y un símbolo para '.asg CADENA, SÍMBOLO'"
 
-#: config/tc-tic54x.c:532
+#: config/tc-tic54x.c:527
 msgid "Unterminated string after absolute expression"
 msgstr "Cadena sin terminar después de una expresión absoluta"
 
-#: config/tc-tic54x.c:540
+#: config/tc-tic54x.c:535
 msgid "Comma and symbol expected for '.eval EXPR, SYMBOL'"
 msgstr "Se esperaban una coma y un símbolo para '.eval EXPR, SÍMBOLO'"
 
-#: config/tc-tic54x.c:552
+#: config/tc-tic54x.c:547
 msgid "symbols assigned with .eval must begin with a letter"
 msgstr "los símbolos asignados con .eval deben comenzar con una letra"
 
-#: config/tc-tic54x.c:810
+#: config/tc-tic54x.c:805
 msgid "Offset on nested structures is ignored"
 msgstr "Se ignora el desplazamiento en estructuras anidadas"
 
-#: config/tc-tic54x.c:861
+#: config/tc-tic54x.c:856
 #, c-format
 msgid ".end%s without preceding .%s"
 msgstr ".end%s sin un .%s precedente"
 
-#: config/tc-tic54x.c:928
+#: config/tc-tic54x.c:923
 #, c-format
 msgid "Unrecognized struct/union tag '%s'"
 msgstr "Marca de struct/union '%s' no reconocida"
 
-#: config/tc-tic54x.c:930
+#: config/tc-tic54x.c:925
 msgid ".tag requires a structure tag"
 msgstr ".tag requiere una estructura tag"
 
-#: config/tc-tic54x.c:936
+#: config/tc-tic54x.c:931
 msgid "Label required for .tag"
 msgstr "Se requiere una etiqueta para .tag"
 
-#: config/tc-tic54x.c:955
+#: config/tc-tic54x.c:950
 #, c-format
 msgid ".tag target '%s' undefined"
 msgstr "el objetivo .tag '%s' está indefinido"
 
-#: config/tc-tic54x.c:1018
+#: config/tc-tic54x.c:1013
 #, c-format
 msgid ".field count '%d' out of range (1 <= X <= 32)"
 msgstr "la cuenta de .field '%d' está fuera de rango (1 <= X <= 32)"
 
-#: config/tc-tic54x.c:1046
+#: config/tc-tic54x.c:1041
 #, c-format
 msgid "Unrecognized field type '%c'"
 msgstr "Tipo de campo '%c' no reconocido"
 
 #. Disallow .byte with a non constant expression that will
 #. require relocation.
-#: config/tc-tic54x.c:1183
+#: config/tc-tic54x.c:1178
 msgid "Relocatable values require at least WORD storage"
 msgstr "Los valores reubicables requieren por lo menos almacenamiento WORD"
 
-#: config/tc-tic54x.c:1245
+#: config/tc-tic54x.c:1240
 msgid "Use of .def/.ref is deprecated.  Use .global instead"
 msgstr "El uso de .def/.ref está deprecado.  Utilice en su lugar .global"
 
-#: config/tc-tic54x.c:1444
+#: config/tc-tic54x.c:1439
 msgid ".space/.bes repeat count is negative, ignored"
 msgstr "la cuenta de repetición .space/.bes es negativa, se ignora"
 
-#: config/tc-tic54x.c:1449
+#: config/tc-tic54x.c:1444
 msgid ".space/.bes repeat count is zero, ignored"
 msgstr "la cuenta de repetición .space/.bes es cero, se ignora"
 
-#: config/tc-tic54x.c:1527
+#: config/tc-tic54x.c:1522
 msgid "Missing size argument"
 msgstr "Falta el tamaño del argumento"
 
-#: config/tc-tic54x.c:1664
+#: config/tc-tic54x.c:1659
 msgid "CPU version has already been set"
 msgstr "La versión de CPU ya se había establecido"
 
-#: config/tc-tic54x.c:1668
+#: config/tc-tic54x.c:1663
 #, c-format
 msgid "Unrecognized version '%s'"
 msgstr "Versión '%s' no reconocida"
 
-#: config/tc-tic54x.c:1674
+#: config/tc-tic54x.c:1669
 msgid "Changing of CPU version on the fly not supported"
 msgstr "No hay soporte para el cambio de la versión del CPU al vuelo"
 
-#: config/tc-tic54x.c:1810
+#: config/tc-tic54x.c:1805
 msgid "p2align not supported on this target"
 msgstr "p2align no tiene soporte en este objetivo"
 
-#: config/tc-tic54x.c:1823
+#: config/tc-tic54x.c:1818
 msgid "Argument to .even ignored"
 msgstr "Se ignora el argumento para .even"
 
-#: config/tc-tic54x.c:1870
+#: config/tc-tic54x.c:1865
 msgid "Invalid field size, must be from 1 to 32"
 msgstr "Tamaño de campo inválido, debe ser de 1 a 32"
 
-#: config/tc-tic54x.c:1883
+#: config/tc-tic54x.c:1878
 msgid "field size must be 16 when value is relocatable"
 msgstr "el tamaño del campo debe ser 16 cuando el valor es reubicable"
 
-#: config/tc-tic54x.c:1898
+#: config/tc-tic54x.c:1893
 msgid "field value truncated"
 msgstr "se trunca valor del campo"
 
-#: config/tc-tic54x.c:2007 config/tc-tic54x.c:2324
+#: config/tc-tic54x.c:2002 config/tc-tic54x.c:2319
 #, c-format
 msgid "Unrecognized section '%s'"
 msgstr "Sección '%s' no reconocida"
 
-#: config/tc-tic54x.c:2016
+#: config/tc-tic54x.c:2011
 msgid "Current section is unitialized, section name required for .clink"
 msgstr "La sección actual no está iniciada, se requiere el nombre de sección para .clink"
 
-#: config/tc-tic54x.c:2230
+#: config/tc-tic54x.c:2225
 msgid "ENDLOOP without corresponding LOOP"
 msgstr "ENDLOOP sin un LOOP correspondiente"
 
-#: config/tc-tic54x.c:2274
+#: config/tc-tic54x.c:2269
 msgid "Mixing of normal and extended addressing not supported"
 msgstr "No se da soporte a la mezcla de direccionamiento normal y extendido"
 
-#: config/tc-tic54x.c:2280
+#: config/tc-tic54x.c:2275
 msgid "Extended addressing not supported on the specified CPU"
 msgstr "No se da soporte a direccionamiento extendido en el CPU especificado"
 
-#: config/tc-tic54x.c:2330
+#: config/tc-tic54x.c:2325
 msgid ".sblock may be used for initialized sections only"
 msgstr ".sblock se puede utilizar únicamente para secciones sin iniciar"
 
-#: config/tc-tic54x.c:2361
+#: config/tc-tic54x.c:2356
 msgid "Symbol missing for .set/.equ"
 msgstr "Falta el símbolo para .set/.equ"
 
-#: config/tc-tic54x.c:2420
+#: config/tc-tic54x.c:2415
 msgid ".var may only be used within a macro definition"
 msgstr ".var solamente se puede usar dentro de una definición de macro"
 
-#: config/tc-tic54x.c:2428
+#: config/tc-tic54x.c:2423
 msgid "Substitution symbols must begin with a letter"
 msgstr "Los símbolos de sustitución deben empezar con una letra"
 
-#: config/tc-tic54x.c:2522
+#: config/tc-tic54x.c:2517
 #, c-format
 msgid "Can't open macro library file '%s' for reading."
 msgstr "No se puede abrir el fichero de biblioteca de macro '%s' para lectura."
 
-#: config/tc-tic54x.c:2529
+#: config/tc-tic54x.c:2524
 #, c-format
 msgid "File '%s' not in macro archive format"
 msgstr "El fichero '%s' no está en el formato de archivo de macro"
 
-#: config/tc-tic54x.c:2689
+#: config/tc-tic54x.c:2656
 #, c-format
 msgid "Bad COFF version '%s'"
 msgstr "Versión COFF '%s' errónea"
 
-#: config/tc-tic54x.c:2698
+#: config/tc-tic54x.c:2665
 #, c-format
 msgid "Bad CPU version '%s'"
 msgstr "Versión de CPU '%s' errónea"
 
-#: config/tc-tic54x.c:2711 config/tc-tic54x.c:2714
+#: config/tc-tic54x.c:2678 config/tc-tic54x.c:2681
 #, c-format
 msgid "Can't redirect stderr to the file '%s'"
 msgstr "No se puede redirigir la salida de error estándard al fichero '%s'"
 
-#: config/tc-tic54x.c:2861
+#: config/tc-tic54x.c:2809
 #, c-format
 msgid "Undefined substitution symbol '%s'"
 msgstr "Símbolo de sustitución '%s' indefinido"
 
-#: config/tc-tic54x.c:3518
+#: config/tc-tic54x.c:3466
 msgid "Badly formed address expression"
 msgstr "Expresión de dirección mal formada"
 
-#: config/tc-tic54x.c:3782
+#: config/tc-tic54x.c:3730
 #, c-format
 msgid "Invalid dmad syntax '%s'"
 msgstr "Sintaxis de dmad '%s' inválida"
 
-#: config/tc-tic54x.c:3848
+#: config/tc-tic54x.c:3796
 #, c-format
 msgid "Use the .mmregs directive to use memory-mapped register names such as '%s'"
 msgstr "Usa la directiva .mmregs para utilizar nombres de registro mapeados en memoria tales como '%s'"
 
-#: config/tc-tic54x.c:3901
+#: config/tc-tic54x.c:3849
 msgid "Address mode *+ARx is write-only. Results of reading are undefined."
 msgstr "El modo de dirección *+ARx es de sólo escritura. El resultado de la lectura está indefinido."
 
-#: config/tc-tic54x.c:3921
+#: config/tc-tic54x.c:3869
 #, c-format
 msgid "Unrecognized indirect address format \"%s\""
 msgstr "Formato de dirección indirecta \"%s\" no reconocido"
 
-#: config/tc-tic54x.c:3960
+#: config/tc-tic54x.c:3908
 #, c-format
 msgid "Operand '%s' out of range (%d <= x <= %d)"
 msgstr "El operando '%s' está fuera de rango (%d <= x <= %d)"
 
-#: config/tc-tic54x.c:3980
+#: config/tc-tic54x.c:3928
 msgid "Error in relocation handling"
 msgstr "Error en el manejo de la reubicación"
 
-#: config/tc-tic54x.c:4001 config/tc-tic54x.c:4065 config/tc-tic54x.c:4097
+#: config/tc-tic54x.c:3949 config/tc-tic54x.c:4013 config/tc-tic54x.c:4045
 #, c-format
 msgid "Unrecognized condition code \"%s\""
 msgstr "Código de condición \"%s\" no reconocido"
 
-#: config/tc-tic54x.c:4018
+#: config/tc-tic54x.c:3966
 #, c-format
 msgid "Condition \"%s\" does not match preceding group"
 msgstr "La condición \"%s\" no coincide con el grupo precedente"
 
-#: config/tc-tic54x.c:4026
+#: config/tc-tic54x.c:3974
 #, c-format
 msgid "Condition \"%s\" uses a different accumulator from a preceding condition"
 msgstr "La condición \"%s\" utiliza un acumulador diferente de una condición precedente"
 
-#: config/tc-tic54x.c:4033
+#: config/tc-tic54x.c:3981
 msgid "Only one comparison conditional allowed"
 msgstr "Sólo se permite una comparación condicional"
 
-#: config/tc-tic54x.c:4038
+#: config/tc-tic54x.c:3986
 msgid "Only one overflow conditional allowed"
 msgstr "Sólo se permite un desbordamiento condicional"
 
-#: config/tc-tic54x.c:4046
+#: config/tc-tic54x.c:3994
 #, c-format
 msgid "Duplicate %s conditional"
 msgstr "Condicional %s duplicado"
 
-#: config/tc-tic54x.c:4081
+#: config/tc-tic54x.c:4029
 msgid "Invalid auxiliary register (use AR0-AR7)"
 msgstr "Registro auxiliar inválido (utilice AR0-AR7)"
 
-#: config/tc-tic54x.c:4117
+#: config/tc-tic54x.c:4065
 msgid "lk addressing modes are invalid for memory-mapped register addressing"
 msgstr "Los modos de direccionamiento lk son inválidos para el direccionamiento de registros mapeados en memoria"
 
-#: config/tc-tic54x.c:4125
+#: config/tc-tic54x.c:4073
 msgid "Address mode *+ARx is not allowed in memory-mapped register addressing.  Resulting behavior is undefined."
 msgstr "El modo de dirección *+ARx no se permite en el direccionamiento de registros mapeados en memoria.  El comportamiento resultante está indefinido."
 
-#: config/tc-tic54x.c:4151
+#: config/tc-tic54x.c:4099
 msgid "Destination accumulator for each part of this parallel instruction must be different"
 msgstr "El acumulador de destino para cada parte de esta instrucción paralela debe ser diferente"
 
-#: config/tc-tic54x.c:4200
+#: config/tc-tic54x.c:4148
 #, c-format
 msgid "Memory mapped register \"%s\" out of range"
 msgstr "El registro mapeado en memoria \"%s\" está fuera de rango"
 
-#: config/tc-tic54x.c:4239
+#: config/tc-tic54x.c:4187
 msgid "Invalid operand (use 1, 2, or 3)"
 msgstr "Operando inválido (utilice 1, 2, ó 3)"
 
-#: config/tc-tic54x.c:4264
+#: config/tc-tic54x.c:4212
 msgid "A status register or status bit name is required"
 msgstr "Se requiere un registro de estado o un nombre de bit de estado"
 
-#: config/tc-tic54x.c:4274
+#: config/tc-tic54x.c:4222
 #, c-format
 msgid "Unrecognized status bit \"%s\""
 msgstr "Bit de estado \"%s\" no reconocido"
 
-#: config/tc-tic54x.c:4297
+#: config/tc-tic54x.c:4245
 #, c-format
 msgid "Invalid status register \"%s\""
 msgstr "Registro de estado \"%s\" inválido"
 
-#: config/tc-tic54x.c:4309
+#: config/tc-tic54x.c:4257
 #, c-format
 msgid "Operand \"%s\" out of range (use 1 or 2)"
 msgstr "El operando \"%s\" está fuera de rango (utilice 1 ó 2)"
 
-#: config/tc-tic54x.c:4517
+#: config/tc-tic54x.c:4465
 #, c-format
 msgid "Unrecognized instruction \"%s\""
 msgstr "Instrucción \"%s\" no reconocida"
 
-#: config/tc-tic54x.c:4546
+#: config/tc-tic54x.c:4494
 #, c-format
 msgid "Unrecognized operand list '%s' for instruction '%s'"
 msgstr "Lista de operando '%s' no reconocida para la instrucción '%s'"
 
-#: config/tc-tic54x.c:4578
+#: config/tc-tic54x.c:4526
 #, c-format
 msgid "Unrecognized parallel instruction \"%s\""
 msgstr "Instrucción paralela \"%s\" no reconocida"
 
-#: config/tc-tic54x.c:4629
+#: config/tc-tic54x.c:4577
 #, c-format
 msgid "Invalid operand (s) for parallel instruction \"%s\""
 msgstr "Operando(s) inválido(s) para la instrucción paralela \"%s\""
 
-#: config/tc-tic54x.c:4632
+#: config/tc-tic54x.c:4580
 #, c-format
 msgid "Unrecognized parallel instruction combination \"%s || %s\""
 msgstr "Combinación de instrucciones paralelas \"%s || %s\" no reconocida"
 
-#: config/tc-tic54x.c:4869
+#: config/tc-tic54x.c:4817
 #, c-format
 msgid "%s symbol recursion stopped at second appearance of '%s'"
 msgstr "La recursión del símbolo %s se detuvo en la segunda aparición de '%s'"
 
-#: config/tc-tic54x.c:4909
+#: config/tc-tic54x.c:4857
 msgid "Unrecognized substitution symbol function"
 msgstr "Función de sustitución de símbolo no reconocida"
 
-#: config/tc-tic54x.c:4914
+#: config/tc-tic54x.c:4862
 msgid "Missing '(' after substitution symbol function"
 msgstr "Falta un '(' después de la función de sustitución de símbolo"
 
-#: config/tc-tic54x.c:4928
+#: config/tc-tic54x.c:4876
 msgid "Expecting second argument"
 msgstr "Se esperaba un segundo argumento"
 
-#: config/tc-tic54x.c:4941 config/tc-tic54x.c:4991
+#: config/tc-tic54x.c:4889 config/tc-tic54x.c:4939
 msgid "Extra junk in function call, expecting ')'"
 msgstr "Basura extra en la llamada a función, se esperaba ')'"
 
-#: config/tc-tic54x.c:4967
+#: config/tc-tic54x.c:4915
 msgid "Function expects two arguments"
 msgstr "La función espera dos argumentos"
 
-#: config/tc-tic54x.c:4980
+#: config/tc-tic54x.c:4928
 msgid "Expecting character constant argument"
 msgstr "Se espera una constante de carácter como argumento"
 
-#: config/tc-tic54x.c:4986
+#: config/tc-tic54x.c:4934
 msgid "Both arguments must be substitution symbols"
 msgstr "Ambos argumentos deben ser símbolos de sustitución"
 
-#: config/tc-tic54x.c:5039
+#: config/tc-tic54x.c:4987
 #, c-format
 msgid "Invalid subscript (use 1 to %d)"
 msgstr "Subíndice inválido (utilice de 1 a %d)"
 
-#: config/tc-tic54x.c:5049
+#: config/tc-tic54x.c:4997
 #, c-format
 msgid "Invalid length (use 0 to %d"
 msgstr "Longitud inválida (utilice de 0 a %d)"
 
-#: config/tc-tic54x.c:5059
+#: config/tc-tic54x.c:5007
 msgid "Missing ')' in subscripted substitution symbol expression"
 msgstr "Falta un ')' en la expresión del símbolo de sustitución suscrito"
 
-#: config/tc-tic54x.c:5079
+#: config/tc-tic54x.c:5027
 msgid "Missing forced substitution terminator ':'"
 msgstr "Falta el terminador de sustitución forzada ':'"
 
-#: config/tc-tic54x.c:5252
+#: config/tc-tic54x.c:5182
 #, c-format
 msgid "Instruction does not fit in available delay slots (%d-word insn, %d slots left)"
 msgstr "La instrucción no cabe en las ranuras de retardo disponibles (%d instrucciones word, %d ranuras restantes)"
 
-#: config/tc-tic54x.c:5293
+#: config/tc-tic54x.c:5223
 #, c-format
 msgid "Unrecognized parallel instruction '%s'"
 msgstr "Instrucción paralela '%s' no reconocida"
 
-#: config/tc-tic54x.c:5305
+#: config/tc-tic54x.c:5235
 #, c-format
 msgid "Instruction '%s' requires an LP cpu version"
 msgstr "La instrucción '%s' requiere una versión de cpu LP"
 
-#: config/tc-tic54x.c:5312
+#: config/tc-tic54x.c:5242
 #, c-format
 msgid "Instruction '%s' requires far mode addressing"
 msgstr "La instrucción '%s' requiere el modo de direccionamiento lejano"
 
-#: config/tc-tic54x.c:5324
+#: config/tc-tic54x.c:5254
 #, c-format
 msgid "Instruction does not fit in available delay slots (%d-word insn, %d slots left). Resulting behavior is undefined."
 msgstr "La instrucción no cabe en las ranuras de retardo disponibles (%d instrucciones word, %d ranuras restantes). El comportamiento resultante está indefinida."
 
-#: config/tc-tic54x.c:5334
+#: config/tc-tic54x.c:5264
 msgid "Instructions which cause PC discontinuity are not allowed in a delay slot. Resulting behavior is undefined."
 msgstr "Las instrucciones que causan discontinuidad en el PC no se permiten en una ranura de retardo. El comportamiento resultante está indefinido."
 
-#: config/tc-tic54x.c:5345
+#: config/tc-tic54x.c:5275
 #, c-format
 msgid "'%s' is not repeatable. Resulting behavior is undefined."
 msgstr "'%s' no se puede repetir. El comportamiento resultante está indefinido."
 
-#: config/tc-tic54x.c:5349
+#: config/tc-tic54x.c:5279
 msgid "Instructions using long offset modifiers or absolute addresses are not repeatable. Resulting behavior is undefined."
 msgstr "Las instrucciones que usan modificadores de desplazamiento long o direcciones absolutas no se pueden repetir. El comportamiento resultante está indefinido."
 
-#: config/tc-tic54x.c:5545
+#: config/tc-tic54x.c:5459
 #, c-format
 msgid "Unsupported relocation size %d"
 msgstr "Tamaño de reubicación %d sin soporte"
 
-#: config/tc-tic54x.c:5699
+#: config/tc-tic54x.c:5602
 msgid "non-absolute value used with .space/.bes"
 msgstr "se utilizó un valor no absoluto con .space/.bes"
 
-#: config/tc-tic54x.c:5703
+#: config/tc-tic54x.c:5606
 #, c-format
 msgid "negative value ignored in %s"
 msgstr "se ignora el valor negativo en %s"
 
-#: config/tc-tic54x.c:5792
+#: config/tc-tic54x.c:5695
 #, c-format
 msgid "attempt to .space/.bes backwards? (%ld)"
 msgstr "¿se intentó hacer .space/.bes hacia atrás? (%ld)"
 
-#: config/tc-tic54x.c:5826
+#: config/tc-tic54x.c:5729
 #, c-format
 msgid "Invalid label '%s'"
 msgstr "Etiqueta '%s' inválida"
 
-#: config/tc-tic80.c:26
-#, c-format
-msgid "internal error:%s:%d: %s\n"
-msgstr "error interno:%s:%d: %s\n"
-
-#: config/tc-tic80.c:29
-#, c-format
-msgid "internal error:%s:%d: %s %ld\n"
-msgstr "error interno:%s:%d: %s %ld\n"
-
-#: config/tc-tic80.c:89
-msgid "Relaxation is a luxury we can't afford"
-msgstr "La relajación es un lujo que no se puede conceder"
-
-#: config/tc-tic80.c:138
-msgid "bad call to md_atof ()"
-msgstr "llamada errónea a md_atof ()"
-
-#: config/tc-tic80.c:235
-msgid "':' not followed by 'm' or 's'"
-msgstr "':' no está seguido por 'm' o 's'"
-
-#: config/tc-tic80.c:248
-msgid "paren nesting"
-msgstr "anidamiento de paréntesis"
-
-#: config/tc-tic80.c:262
-msgid "mismatched parenthesis"
-msgstr "paréntesis sin coincidencia"
-
-#: config/tc-tic80.c:464
-msgid "unhandled expression type"
-msgstr "tipo de expresión sin manejar"
-
-#: config/tc-tic80.c:678
-msgid "symbol reloc that is not PC relative or 32 bits"
-msgstr "reubicación de símbolo que no es relativo al PC o de 32 bits"
-
-#: config/tc-tic80.c:707
-msgid "unhandled operand modifier"
-msgstr "modificador de operando sin manejar"
-
-#: config/tc-tic80.c:749
-msgid "unhandled expression"
-msgstr "expresión sin manejar"
-
-#: config/tc-tic80.c:797
-#, c-format
-msgid "Invalid mnemonic: '%s'"
-msgstr "Mnemónico inválido: '%s'"
-
-#: config/tc-tic80.c:810
-#, c-format
-msgid "Invalid operands: '%s'"
-msgstr "Operandos inválidos: '%s'"
-
-#: config/tc-tic80.c:888
-msgid "unhandled predefined symbol bits"
-msgstr "bits de símbolo predefinido sin manejar"
-
-#: config/tc-tic80.c:983
-#, c-format
-msgid "PC offset 0x%lx outside range 0x%lx-0x%lx"
-msgstr "desplazamiento del PC 0x%lx fuera del rango 0x%lx-0x%lx"
-
-#: config/tc-tic80.c:998
-msgid "unhandled relocation type in fixup"
-msgstr "typo de reubicación sin manejar en la compostura"
-
-#: config/tc-tic80.c:1037
-msgid "md_convert_frag() not implemented yet"
-msgstr "md_convert_frag() aún no está implementado"
-
-#: config/tc-v850.c:244
+#: config/tc-v850.c:234
 #, c-format
 msgid ".COMMon length (%d.) < 0! Ignored."
 msgstr "¡Longitud .COMMún (%d.) < 0! Se ignora."
 
-#: config/tc-v850.c:293
+#: config/tc-v850.c:255
+#, c-format
+msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
+msgstr "La longitud de .comm \"%s\" ya es %ld. No se cambia a %d."
+
+#: config/tc-v850.c:281
 msgid "Common alignment negative; 0 assumed"
 msgstr "Alineación común negativa; se asume 0"
 
-#: config/tc-v850.c:974
+#: config/tc-v850.c:939
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr "operando de desplazamiento desconocido: %x\n"
 
-#: config/tc-v850.c:975
+#: config/tc-v850.c:940
 msgid "internal failure in parse_register_list"
 msgstr "falla interna en parse_register_list"
 
-#: config/tc-v850.c:991
+#: config/tc-v850.c:956
 msgid "constant expression or register list expected"
 msgstr "se esperaba una expresión constante o una lista de registros"
 
-#: config/tc-v850.c:996 config/tc-v850.c:1009 config/tc-v850.c:1028
+#: config/tc-v850.c:961 config/tc-v850.c:974 config/tc-v850.c:993
 msgid "high bits set in register list expression"
 msgstr "se establecieron los bits altos en la expresión de lista de registros"
 
-#: config/tc-v850.c:1067 config/tc-v850.c:1130
+#: config/tc-v850.c:1032 config/tc-v850.c:1095
 msgid "illegal register included in list"
 msgstr "se incluyó un registro ilegal en la lista"
 
-#: config/tc-v850.c:1073
+#: config/tc-v850.c:1038
 msgid "system registers cannot be included in list"
 msgstr "los registros del sistema no pueden estar incluídos en la lista"
 
-#: config/tc-v850.c:1078
+#: config/tc-v850.c:1043
 msgid "PSW cannot be included in list"
 msgstr "PSW no se puede incluir en la lista"
 
-#: config/tc-v850.c:1085
+#: config/tc-v850.c:1050
 msgid "High value system registers cannot be included in list"
 msgstr "Los registros altos de valores del sistema no se pueden incluir en la lista"
 
-#: config/tc-v850.c:1109
+#: config/tc-v850.c:1074
 msgid "second register should follow dash in register list"
 msgstr "el segundo registro debe estar a continuación de un guión en la lista de registros"
 
-#: config/tc-v850.c:1154
+#: config/tc-v850.c:1119
+#, c-format
 msgid " V850 options:\n"
 msgstr "Opciones de V850:\n"
 
-#: config/tc-v850.c:1155
+#: config/tc-v850.c:1120
+#, c-format
 msgid "  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"
 msgstr "  -mwarn-signed-overflow    Avisa si los valores inmediatos con signo desbordan\n"
 
-#: config/tc-v850.c:1156
+#: config/tc-v850.c:1121
+#, c-format
 msgid "  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"
 msgstr "  -mwarn-unsigned-overflow  Avisa si los valores inmediato sin signo desbordan\n"
 
-#: config/tc-v850.c:1157
+#: config/tc-v850.c:1122
+#, c-format
 msgid "  -mv850                    The code is targeted at the v850\n"
 msgstr "  -mv850                    El código está destinado para el v850\n"
 
-#: config/tc-v850.c:1158
+#: config/tc-v850.c:1123
+#, c-format
 msgid "  -mv850e                   The code is targeted at the v850e\n"
 msgstr "  -mv850e                   El código está destinado para el v850e\n"
 
-#: config/tc-v850.c:1159
+#: config/tc-v850.c:1124
+#, c-format
+msgid "  -mv850e1                  The code is targeted at the v850e1\n"
+msgstr "  -mv850e1                  El código está destinado para el v850e1\n"
+
+#: config/tc-v850.c:1125
+#, c-format
 msgid "  -mv850any                 The code is generic, despite any processor specific instructions\n"
 msgstr "  -mv850any                 El código es genérico, a pesar de cualquier instrucción específica de procesador\n"
 
-#: config/tc-v850.c:1160
+#: config/tc-v850.c:1126
+#, c-format
 msgid "  -mrelax                   Enable relaxation\n"
 msgstr "  -mrelax                   Activa la relajación.\n"
 
-#: config/tc-v850.c:1173 config/tc-v850.c:1208
-#, c-format
-msgid "unknown command line option: -%c%s\n"
-msgstr "opción de línea de comandos desconocida: -%c%s\n"
-
-#: config/tc-v850.c:1349
+#: config/tc-v850.c:1308
 #, c-format
 msgid "Unable to determine default target processor from string: %s"
-msgstr "No se puede determinar el procesador objetivo por omisión de la cadena: %s"
+msgstr "No se puede determinar el procesador objetivo por defecto de la cadena: %s"
+
+#: config/tc-v850.c:1343
+msgid "lo() relocation used on an instruction which does not support it"
+msgstr "se utilizó una reubicación lo() en una instrucción que no la soporta"
 
-#: config/tc-v850.c:1386
+#: config/tc-v850.c:1360
 msgid "ctoff() relocation used on an instruction which does not support it"
 msgstr "se utilizó una reubicación ctoff() en una instrucción que no la soporta"
 
-#: config/tc-v850.c:1412
+#: config/tc-v850.c:1382
 msgid "sdaoff() relocation used on an instruction which does not support it"
 msgstr "se utilizó una reubicación sdaoff() en una instrucción que no la soporta"
 
-#: config/tc-v850.c:1438
+#: config/tc-v850.c:1404
 msgid "zdaoff() relocation used on an instruction which does not support it"
 msgstr "se utilizó una reubicación zdaoff() en una instrucción que no la soporta"
 
-#: config/tc-v850.c:1475
+#: config/tc-v850.c:1437
 msgid "tdaoff() relocation used on an instruction which does not support it"
 msgstr "se utilizó una reubicación tdaoff() en una instrucción que no la soporta"
 
-#: config/tc-v850.c:1699
+#: config/tc-v850.c:1642
 msgid "Target processor does not support this instruction."
 msgstr "El procesador objetivo no tiene soporte para esta instrucción."
 
-#: config/tc-v850.c:1789 config/tc-v850.c:1818 config/tc-v850.c:2006
+#: config/tc-v850.c:1731 config/tc-v850.c:1760 config/tc-v850.c:1940
 msgid "immediate operand is too large"
 msgstr "el operando inmediato es demasiado grande"
 
-#: config/tc-v850.c:1800
+#: config/tc-v850.c:1742
 msgid "AAARG -> unhandled constant reloc"
 msgstr "AAARG -> reubicación de constante sin manejar"
 
-#: config/tc-v850.c:1844
+#: config/tc-v850.c:1785
 msgid "invalid register name"
 msgstr "nombre de registro inválido"
 
-#: config/tc-v850.c:1849
+#: config/tc-v850.c:1789
 msgid "register r0 cannot be used here"
 msgstr "el registro r0 no se puede usar aquí"
 
-#: config/tc-v850.c:1861
+#: config/tc-v850.c:1800
 msgid "invalid system register name"
 msgstr "nombre de registro de sistema inválido"
 
-#: config/tc-v850.c:1874
+#: config/tc-v850.c:1812
 msgid "expected EP register"
 msgstr "se esperaba el registro EP"
 
-#: config/tc-v850.c:1891
+#: config/tc-v850.c:1828
 msgid "invalid condition code name"
 msgstr "nombre de código de condición inválido"
 
-#: config/tc-v850.c:1912 config/tc-v850.c:1916
+#: config/tc-v850.c:1848 config/tc-v850.c:1852
 msgid "constant too big to fit into instruction"
 msgstr "la constante es demasiado grande para caber en la instrucción"
 
-#: config/tc-v850.c:1969
+#: config/tc-v850.c:1905
 msgid "syntax error: value is missing before the register name"
 msgstr "error sintáctico: falta el valor antes del nombre de registro"
 
-#: config/tc-v850.c:1971
+#: config/tc-v850.c:1907
 msgid "syntax error: register not expected"
 msgstr "error sintáctico: no se esperaba un registro"
 
-#: config/tc-v850.c:1985
+#: config/tc-v850.c:1920
 msgid "syntax error: system register not expected"
 msgstr "error sintáctico: no se esperaba un registro de sistema"
 
-#: config/tc-v850.c:1990
+#: config/tc-v850.c:1924
 msgid "syntax error: condition code not expected"
 msgstr "error sintáctico: no es esperaba código de condición"
 
-#: config/tc-v850.c:2031
+#: config/tc-v850.c:1958
 msgid "invalid operand"
 msgstr "operando inválido"
 
-#: config/tc-vax.c:285
+#: config/tc-vax.c:290
 #, c-format
 msgid "VIP_BEGIN error:%s"
 msgstr "error VIP_BEGIN:%s"
 
-#: config/tc-vax.c:422
+#: config/tc-vax.c:461
+#, c-format
+msgid "Ignoring statement due to \"%s\""
+msgstr "Se ignora la declaración debido a \"%s\""
+
+#: config/tc-vax.c:480
 #, c-format
 msgid "Aborting because statement has \"%s\""
 msgstr "Se aborta porque la declaración tiene \"%s\""
 
-#: config/tc-vax.c:469
+#: config/tc-vax.c:527
 msgid "Can't relocate expression"
 msgstr "No se puede reubicar la expresión"
 
-#: config/tc-vax.c:572
+#: config/tc-vax.c:630
 msgid "Bignum not permitted in short literal. Immediate mode assumed."
 msgstr "No se permite un número grande en una literal short. Se asume el modo inmediato."
 
-#: config/tc-vax.c:581
+#: config/tc-vax.c:639
 msgid "Can't do flonum short literal: immediate mode used."
 msgstr "No se puede hacer una literal short de un número de coma flotante: se usa el modo inmediato."
 
-#: config/tc-vax.c:626
+#: config/tc-vax.c:684
 #, c-format
 msgid "A bignum/flonum may not be a displacement: 0x%lx used"
 msgstr "Un número grande/de coma flotante no puede ser una desubicación: se usa 0x%lx"
 
-#: config/tc-vax.c:961
+#: config/tc-vax.c:1007
 #, c-format
 msgid "Short literal overflow(%ld.), immediate mode assumed."
 msgstr "Desbordamiento de la literal short (%ld.), se asume el modo inmediato."
 
-#: config/tc-vax.c:970
+#: config/tc-vax.c:1016
 #, c-format
 msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
 msgstr "Se fuerza la literal short a modo inmediato. now_seg=%s to_seg=%s"
 
-#: config/tc-vax.c:1035
+#: config/tc-vax.c:1081
 msgid "Length specification ignored. Address mode 9F used"
 msgstr "Se ignora la especificación de longitud. Se usa el modo de direccionamiento 9F"
 
-#: config/tc-vax.c:1096
+#: config/tc-vax.c:1142
 msgid "Invalid operand:  immediate value used as base address."
 msgstr "Operando inválido: se utilizó un valor inmediato como dirección base."
 
-#: config/tc-vax.c:1098
+#: config/tc-vax.c:1144
 msgid "Invalid operand:  immediate value used as address."
 msgstr "Operando inválido: se utilizó un valor inmediato como dirección"
 
-#: config/tc-vax.c:1123
+#: config/tc-vax.c:1169
 msgid "Symbol used as immediate operand in PIC mode."
 msgstr "Se utiliza un símbolo como operando inmediato en modo PIC."
 
-#: config/tc-vax.c:1941
+#: config/tc-vax.c:1942
 msgid "odd number of bytes in operand description"
 msgstr "número impar de bytes en la descripción del operando"
 
-#: config/tc-vax.c:1957
+#: config/tc-vax.c:1958
 msgid "Bad operand"
 msgstr "Operando erróneo"
 
-#: config/tc-vax.c:2532
+#: config/tc-vax.c:1963
+msgid "Not enough operands"
+msgstr "No hay suficientes operandos"
+
+#: config/tc-vax.c:1970
+msgid "Too many operands"
+msgstr "Demasiados operandos"
+
+#: config/tc-vax.c:2533
 msgid "no '[' to match ']'"
 msgstr "no hay '[' que coincida con ']'"
 
-#: config/tc-vax.c:2552
+#: config/tc-vax.c:2553
 msgid "bad register in []"
 msgstr "registro erróneo en []"
 
-#: config/tc-vax.c:2554
+#: config/tc-vax.c:2555
 msgid "[PC] index banned"
 msgstr "índice [PC] prohibido"
 
-#: config/tc-vax.c:2589
+#: config/tc-vax.c:2590
 msgid "no '(' to match ')'"
 msgstr "no hay '(' que coincida con ')'"
 
-#: config/tc-vax.c:2729
+#: config/tc-vax.c:2730
 msgid "invalid branch operand"
 msgstr "operando de ramificación inválido"
 
-#: config/tc-vax.c:2758
+#: config/tc-vax.c:2759
 msgid "address prohibits @"
 msgstr "la dirección prohibe @"
 
-#: config/tc-vax.c:2760
+#: config/tc-vax.c:2761
 msgid "address prohibits #"
 msgstr "la dirección prohibe #"
 
-#: config/tc-vax.c:2764
+#: config/tc-vax.c:2765
 msgid "address prohibits -()"
 msgstr "la dirección prohibe -()"
 
-#: config/tc-vax.c:2766
+#: config/tc-vax.c:2767
 msgid "address prohibits ()+"
 msgstr "la dirección prohibe ()+"
 
-#: config/tc-vax.c:2769
+#: config/tc-vax.c:2770
 msgid "address prohibits ()"
 msgstr "la dirección prohibe ()"
 
-#: config/tc-vax.c:2771
+#: config/tc-vax.c:2772
 msgid "address prohibits []"
 msgstr "la dirección prohibe []"
 
-#: config/tc-vax.c:2773
+#: config/tc-vax.c:2774
 msgid "address prohibits register"
 msgstr "la dirección prohibe un registro"
 
-#: config/tc-vax.c:2775
+#: config/tc-vax.c:2776
 msgid "address prohibits displacement length specifier"
 msgstr "la dirección prohibe un especificador de longitud de desubicación"
 
-#: config/tc-vax.c:2805
+#: config/tc-vax.c:2806
 msgid "invalid operand of S^#"
 msgstr "operando inválido de S^#"
 
-#: config/tc-vax.c:2822
+#: config/tc-vax.c:2823
 msgid "S^# needs expression"
 msgstr "S^# necesita una expresión"
 
-#: config/tc-vax.c:2829
+#: config/tc-vax.c:2830
 msgid "S^# may only read-access"
 msgstr "S^# tal vez sea solamente para acceso por lectura"
 
-#: config/tc-vax.c:2854
+#: config/tc-vax.c:2855
 msgid "invalid operand of -()"
 msgstr "operando inválido de -()"
 
-#: config/tc-vax.c:2860
+#: config/tc-vax.c:2861
 msgid "-(PC) unpredictable"
 msgstr "-(PC) impredecible"
 
-#: config/tc-vax.c:2862
+#: config/tc-vax.c:2863
 msgid "[]index same as -()register: unpredictable"
 msgstr "[]índice igual que -()registro: impredecible"
 
-#: config/tc-vax.c:2898
+#: config/tc-vax.c:2899
 msgid "invalid operand of ()+"
 msgstr "operando inválido de ()+"
 
-#: config/tc-vax.c:2904
+#: config/tc-vax.c:2905
 msgid "(PC)+ unpredictable"
 msgstr "(PC)+ impredecible"
 
-#: config/tc-vax.c:2906
+#: config/tc-vax.c:2907
 msgid "[]index same as ()+register: unpredictable"
 msgstr "[]índice igual que ()+registro: impredecible"
 
-#: config/tc-vax.c:2931
+#: config/tc-vax.c:2932
 msgid "# conflicts length"
 msgstr "# tiene conflictos con la longitud"
 
-#: config/tc-vax.c:2933
+#: config/tc-vax.c:2934
 msgid "# bars register"
 msgstr "# prohibe el registro"
 
-#: config/tc-vax.c:2955
+#: config/tc-vax.c:2956
 msgid "writing or modifying # is unpredictable"
 msgstr "escribir o modificar # es impredecible"
 
-#: config/tc-vax.c:2985
+#: config/tc-vax.c:2986
 msgid "length not needed"
 msgstr "no se necesita la longitud"
 
-#: config/tc-vax.c:2992
+#: config/tc-vax.c:2993
 msgid "can't []index a register, because it has no address"
 msgstr "no se puede []indizar un registro, porque no tiene dirección"
 
-#: config/tc-vax.c:2994
+#: config/tc-vax.c:2995
 msgid "a register has no address"
 msgstr "un registro no tiene dirección"
 
-#: config/tc-vax.c:3005
+#: config/tc-vax.c:3006
 msgid "PC part of operand unpredictable"
 msgstr "la parte PC del operando es impredecible"
 
-#: config/tc-vax.c:3345
+#: config/tc-vax.c:3281
+msgid "SYMBOL TABLE not implemented"
+msgstr "SYMBOL TABLE no está implementado"
+
+#: config/tc-vax.c:3285
+msgid "TOKEN TRACE not implemented"
+msgstr "TOKEN TRACE no está implementado"
+
+#: config/tc-vax.c:3289
+#, c-format
+msgid "Displacement length %s ignored!"
+msgstr "¡Se ignora la longitud de desubicación %s!"
+
+#: config/tc-vax.c:3293
+#, c-format
+msgid "I don't need or use temp. file \"%s\"."
+msgstr "No se necesita o se utiliza el fichero temporal \"%s\"."
+
+#: config/tc-vax.c:3297
+msgid "I don't use an interpass file! -V ignored"
+msgstr "¡No se usa un fichero entre pasos! Se ignora -V"
+
+#: config/tc-vax.c:3354
+#, c-format
 msgid ""
 "VAX options:\n"
 "-d LENGTH\t\tignored\n"
@@ -10102,7 +10617,8 @@ msgstr ""
 "-T\t\t\tse ignora\n"
 "-V\t\t\tse ignora\n"
 
-#: config/tc-vax.c:3354
+#: config/tc-vax.c:3363
+#, c-format
 msgid ""
 "VMS options:\n"
 "-+\t\t\thash encode names longer than 31 characters\n"
@@ -10120,533 +10636,721 @@ msgstr ""
 "\t\t\t0 = mayúsculas, 2 = minúsculas, 3 = preservar mayúsculas/minúsculas\n"
 "-v\"VERSION\"\t\tel código a ensamblar fue producido por el compilador \"VERSION\"\n"
 
-#: config/tc-w65.c:145
-msgid "need on or off."
-msgstr "necesita on u off."
-
-#: config/tc-w65.c:281 config/tc-w65.c:324
-msgid "syntax error after <exp"
-msgstr "error sintáctico después de <exp"
-
-#: config/tc-xstormy16.c:80
+#: config/tc-xstormy16.c:78
+#, c-format
 msgid " XSTORMY16 specific command line options:\n"
 msgstr " Opciones de línea de comando específicas de XSTROMY16:\n"
 
-#: config/tc-xstormy16.c:562
+#: config/tc-xstormy16.c:563
 #, c-format
 msgid "internal error: can't install fix for reloc type %d (`%s')"
 msgstr "error interno: no se puede instalar la compostura para el tipo de reubicación %d (`%s')"
 
-#: config/tc-xtensa.c:929
-msgid "'--density' option not supported in this Xtensa configuration"
-msgstr "la opción '--density' no tiene soporte en esta configuración Xtensa"
+#: config/tc-xtensa.c:590
+msgid "illegal range of target hardware versions"
+msgstr "rango ilegal de versiones de hardware objetivo"
+
+#: config/tc-xtensa.c:738
+msgid "--density option is ignored"
+msgstr "se ignora la opción --density"
+
+#: config/tc-xtensa.c:741
+msgid "--no-density option is ignored"
+msgstr "se ignora la opción --no-density"
+
+#: config/tc-xtensa.c:750
+msgid "--generics is deprecated; use --transform instead"
+msgstr "--generics es obsoleto; utilice en su lugar --transform"
+
+#: config/tc-xtensa.c:753
+msgid "--no-generics is deprecated; use --no-transform instead"
+msgstr "--no-generics es obsoleto; utilice en su lugar --no-transform"
+
+#: config/tc-xtensa.c:756
+msgid "--relax is deprecated; use --transform instead"
+msgstr "--relax es obsoleto; utilice en su lugar --transform"
 
-#: config/tc-xtensa.c:1030
-msgid "'--literal-section-name' is deprecated; use '--rename-section .literal=NEWNAME'"
-msgstr "'--literal-section-name' es obsoleto; utilice '--rename-section .literal=NOMBRENUEVO'"
+#: config/tc-xtensa.c:759
+msgid "--no-relax is deprecated; use --no-transform instead"
+msgstr "--no-relax es obsoleto; utilice en su lugar --no-transform"
 
-#: config/tc-xtensa.c:1036
-msgid "'--text-section-name' is deprecated; use '--rename-section .text=NEWNAME'"
-msgstr "'--text-section-name' es obsoleto; utilice '--rename-section .text=NOMBRENUEVO'"
+#: config/tc-xtensa.c:776
+msgid "--absolute-literals option not supported in this Xtensa configuration"
+msgstr "la opción --absolute-literals no tiene soporte en esta configuración Xtensa"
 
-#: config/tc-xtensa.c:1042
-msgid "'--data-section-name' is deprecated; use '--rename-section .data=NEWNAME'"
-msgstr "'--data-section-name' es obsoleto; utilice '--rename-section .data=NOMBRENUEVO'"
+#: config/tc-xtensa.c:849
+msgid "prefer-l32r conflicts with prefer-const16"
+msgstr "prefer-l32r tiene conflictos con prefer-const16"
 
-#: config/tc-xtensa.c:1048
-msgid "'--bss-section-name' is deprecated; use '--rename-section .bss=NEWNAME'"
-msgstr "'--bss-section-name' es obsoleto; utilice '--rename-section .bss=NOMBRENUEVO'"
+#: config/tc-xtensa.c:855
+msgid "prefer-const16 conflicts with prefer-l32r"
+msgstr "prefer-const16 tiene conflictos con prefer-l32r"
 
-#: config/tc-xtensa.c:1186
+#: config/tc-xtensa.c:863 config/tc-xtensa.c:872 config/tc-xtensa.c:876
+msgid "invalid target hardware version"
+msgstr "versión de hardware objetivo inválido"
+
+#: config/tc-xtensa.c:1078
 msgid "unmatched end directive"
 msgstr "directiva end sin coincidencia"
 
-#: config/tc-xtensa.c:1215
+#: config/tc-xtensa.c:1107
 msgid ".begin directive with no matching .end directive"
 msgstr "directiva .begin sin una directiva .end coincidente"
 
-#: config/tc-xtensa.c:1259
+#: config/tc-xtensa.c:1148
+msgid "[no-]generics is deprecated; use [no-]transform instead"
+msgstr "[no-]generics es obsoleto; utilice en su lugar [no-]transform"
+
+#: config/tc-xtensa.c:1153
+msgid "[no-]relax is deprecated; use [no-]transform instead"
+msgstr "[no-]relax es obsoleto; utilice en su lugar [no-]transform"
+
+#: config/tc-xtensa.c:1166
 #, c-format
-msgid "directive %s can't be negated"
+msgid "directive %s cannot be negated"
 msgstr "la directiva %s no se puede negar"
 
-#: config/tc-xtensa.c:1265
+#: config/tc-xtensa.c:1172
 msgid "unknown directive"
 msgstr "directiva desconocida"
 
-#: config/tc-xtensa.c:1300
+#: config/tc-xtensa.c:1194 config/tc-xtensa.c:1300 config/tc-xtensa.c:1573
+#: config/tc-xtensa.c:5496
+msgid "directives are not valid inside bundles"
+msgstr "las directivas no son válidas dentro de una agrupación"
+
+#: config/tc-xtensa.c:1206
+msgid ".begin literal is deprecated; use .literal instead"
+msgstr "El uso de .begin literal es obsoleto.  Utilice en su lugar .literal"
+
+#: config/tc-xtensa.c:1220
 msgid "cannot set literal_prefix inside literal fragment"
 msgstr "no se puede establecer literal_prefix dentro de un fragmento literal"
 
-#: config/tc-xtensa.c:1337 config/tc-xtensa.c:1371
-msgid "Xtensa density option not supported; ignored"
-msgstr "la opción de densidad Xtensa no tiene soporte; se ignora"
+#: config/tc-xtensa.c:1263
+msgid ".begin [no-]density is ignored"
+msgstr "se ignora .begin [no-]density"
+
+#: config/tc-xtensa.c:1270 config/tc-xtensa.c:1320
+msgid "Xtensa absolute literals option not supported; ignored"
+msgstr "la opción de literales absolutos Xtensa no tiene soporte; se ignora"
 
-#: config/tc-xtensa.c:1383
+#: config/tc-xtensa.c:1313
+msgid ".end [no-]density is ignored"
+msgstr "se ignora .end [no-]density"
+
+#: config/tc-xtensa.c:1338
 #, c-format
 msgid "does not match begin %s%s at %s:%d"
 msgstr "no coincide inicio %s%s en %s:%d"
 
-#: config/tc-xtensa.c:1429
+#: config/tc-xtensa.c:1393
 msgid ".literal_position inside literal directive; ignoring"
 msgstr ".literal_position dentro de una directiva literal; se ignora"
 
-#: config/tc-xtensa.c:1480
+#: config/tc-xtensa.c:1413
+msgid ".literal not allowed inside .begin literal region"
+msgstr ".literal no se permite dentro de una región .begin literal"
+
+#: config/tc-xtensa.c:1449
 msgid "expected comma or colon after symbol name; rest of line ignored"
 msgstr "se esperaba coma o punto y coma después del nombre del símbolo: se ingnora el resto de la línea"
 
-#: config/tc-xtensa.c:1655 config/tc-xtensa.c:1672
+#: config/tc-xtensa.c:1542
+msgid "fall through frequency must be greater than 0"
+msgstr "la frecuencia de caída debe ser mayor a 0"
+
+#: config/tc-xtensa.c:1550
+msgid "branch target frequency must be greater than 0"
+msgstr "la frecuencia de ramificación de objetivo debe ser mayor a 0"
+
+#: config/tc-xtensa.c:1598
+#, c-format
+msgid "opcode-specific %s relocation used outside an instruction"
+msgstr "se usó la reubicación %s específica de código de operación fuera de una instrucción"
+
+#: config/tc-xtensa.c:1751 config/tc-xtensa.c:1768
 #, c-format
 msgid "bad register name: %s"
 msgstr "nombre de registro erróneo: %s"
 
-#: config/tc-xtensa.c:1661
+#: config/tc-xtensa.c:1757
 #, c-format
 msgid "bad register number: %s"
 msgstr "número de registro erróneo: %s"
 
-#: config/tc-xtensa.c:1724
+#: config/tc-xtensa.c:1836
 msgid "register number out of range"
 msgstr "número de registro fuera de rango"
 
-#: config/tc-xtensa.c:1836
+#: config/tc-xtensa.c:1920
+msgid "extra comma"
+msgstr "coma extra"
+
+#: config/tc-xtensa.c:1922
+msgid "extra colon"
+msgstr "punto y coma extra"
+
+#: config/tc-xtensa.c:1924
+msgid "missing argument"
+msgstr "falta el argumento"
+
+#: config/tc-xtensa.c:1926
+msgid "missing comma or colon"
+msgstr "falta una coma o punto y coma"
+
+#: config/tc-xtensa.c:1983
+msgid "incorrect register number, ignoring"
+msgstr "múmero de registro incorrecto, se ignora"
+
+#: config/tc-xtensa.c:1990
 msgid "too many arguments"
 msgstr "demasiados argumentos"
 
-#: config/tc-xtensa.c:1922
+#: config/tc-xtensa.c:2063
+#, c-format
+msgid "cannot encode opcode \"%s\""
+msgstr "no se puede codificar el código de operación \"%s\""
+
+#: config/tc-xtensa.c:2157
 #, c-format
 msgid "not enough operands (%d) for '%s'; expected %d"
 msgstr "no hay suficientes operandos (%d) para '%s'; se esperaban %d"
 
-#: config/tc-xtensa.c:1929
+#: config/tc-xtensa.c:2164
 #, c-format
 msgid "too many operands (%d) for '%s'; expected %d"
 msgstr "demasiados operandos (%d) para '%s'; se esperaban %d"
 
-#: config/tc-xtensa.c:1973
-#, c-format
-msgid "register number for `%s' is not a constant"
-msgstr "el número de registro para `%s' no es una constante"
-
-#: config/tc-xtensa.c:1978
+#: config/tc-xtensa.c:2219
 #, c-format
-msgid "register number (%ld) for `%s' is out of range"
-msgstr "el número de registro (%ld) para `%s' está fuera de rango"
+msgid "invalid register '%s' for '%s' instruction"
+msgstr "registros '%s' inválido para la instrucción '%s'"
 
-#: config/tc-xtensa.c:2464
+#: config/tc-xtensa.c:2226
 #, c-format
-msgid "operand %d not properly aligned for '%s'"
-msgstr "el operando %d no está alineado adecuadamente '%s'"
+msgid "invalid register number (%ld) for '%s' instruction"
+msgstr "número de registro (%ld) inválido para la instrucción `%s'"
 
-#: config/tc-xtensa.c:2469
+#: config/tc-xtensa.c:2295
 #, c-format
-msgid "operand %d not in immediate table for '%s'"
-msgstr "el operando %d no está en la tabla de inmediatos para '%s'"
+msgid "invalid register number (%ld) for '%s'"
+msgstr "número de registro inválido (%ld) para '%s'"
 
-#: config/tc-xtensa.c:2474
+#: config/tc-xtensa.c:2685
 #, c-format
-msgid "operand %d too large for '%s'"
-msgstr "el operando %d es demasiado grande para '%s'"
+msgid "operand %d of '%s' has out of range value '%u'"
+msgstr "el operando %d de '%s' está el valor fuera de rango '%u'"
 
-#: config/tc-xtensa.c:2479
+#: config/tc-xtensa.c:2691
 #, c-format
-msgid "operand %d too small for '%s'"
-msgstr "el operando %d es demasiado pequeño para '%s'"
+msgid "operand %d of '%s' has invalid value '%u'"
+msgstr "el operando %d de '%s' tiene el valor inválido '%u'"
 
-#: config/tc-xtensa.c:2484
+#: config/tc-xtensa.c:2739
 #, c-format
-msgid "operand %d is invalid for '%s'"
-msgstr "el operando %d es inválido para '%s'"
+msgid "internal error: unknown option name '%s'"
+msgstr "error interno: nombre de opción '%s' desconocido"
 
-#: config/tc-xtensa.c:3716
+#: config/tc-xtensa.c:3791
 msgid "INSTR_LABEL_DEF not supported yet"
 msgstr "INSTR_LABEL_DEF aún no tiene soporte"
 
-#: config/tc-xtensa.c:3745
+#: config/tc-xtensa.c:3820
 msgid "can't handle generation of literal/labels yet"
 msgstr "aún no se puede manejar la generación de literales/etiquetas"
 
-#: config/tc-xtensa.c:3749
+#: config/tc-xtensa.c:3824
 msgid "can't handle undefined OP TYPE"
 msgstr "no se puede manejar un OP TYPE indefinido"
 
-#: config/tc-xtensa.c:3810
+#: config/tc-xtensa.c:3885
 #, c-format
 msgid "found %d operands for '%s':  Expected %d"
 msgstr "se encontraron %d operandos para '%s':  Se esperaban %d"
 
-#: config/tc-xtensa.c:3817
+#: config/tc-xtensa.c:3892
 #, c-format
 msgid "found too many (%d) operands for '%s':  Expected %d"
 msgstr "se econtraron demasiados (%d) operandos para '%s':  Se esperaban %d"
 
-#: config/tc-xtensa.c:4072
-msgid "instruction fragment may contain data"
-msgstr "el fragmento de instrucción puede contener datos"
+#: config/tc-xtensa.c:4029
+msgid "invalid immediate"
+msgstr "inmediato inválido"
 
-#: config/tc-xtensa.c:4105
+#: config/tc-xtensa.c:4140
 #, c-format
-msgid "invalid operand %d on '%s'"
-msgstr "operando %d inválido en '%s'"
+msgid "invalid relocation for operand %i of '%s'"
+msgstr "reubicación inválida para el operando %i de '%s'"
 
-#: config/tc-xtensa.c:4116
+#: config/tc-xtensa.c:4150
 #, c-format
-msgid "invalid expression for operand %d on '%s'"
-msgstr "expresión inválida para el operando %d en '%s'"
+msgid "invalid expression for operand %i of '%s'"
+msgstr "expresión inválida para el operando %i en '%s'"
 
-#: config/tc-xtensa.c:4177
+#: config/tc-xtensa.c:4160
 #, c-format
-msgid "invalid relocation operand %i on '%s'"
-msgstr "operando de reubicación %i inválido en '%s'"
+msgid "invalid relocation in instruction slot %i"
+msgstr "reubicación inválida en la ranura de instrucción %i"
 
-#: config/tc-xtensa.c:4186
+#: config/tc-xtensa.c:4167
 #, c-format
-msgid "undefined symbol for opcode \"%s\"."
-msgstr "símbolo indefinido para el código de operación \"%s\"."
-
-#: config/tc-xtensa.c:4280
-msgid "instruction with constant operands does not fit"
-msgstr "la instrucción con operandos constantes no cabe"
+msgid "undefined symbol for opcode \"%s\""
+msgstr "símbolo indefinido para el código de operación \"%s\""
 
-#: config/tc-xtensa.c:4289
-msgid "instruction with constant operands does not fit without widening"
-msgstr "la instrucción con operandos constantes no cabe sin ensanchar"
-
-#: config/tc-xtensa.c:4379
-msgid "instruction's constant operands do not fit"
-msgstr "los operandos constantes de la instrucción no caben"
-
-#: config/tc-xtensa.c:4718
+#: config/tc-xtensa.c:4608
 msgid "opcode 'NOP.N' unavailable in this configuration"
 msgstr "el código de operación 'NOP.N' no está disponible en esta configuración"
 
-#: config/tc-xtensa.c:4727
-msgid "opcode 'OR' unavailable in this configuration"
-msgstr "el código de operación 'OR' no está disponible en esta configuración"
+#: config/tc-xtensa.c:4668
+msgid "get_expanded_loop_offset: invalid opcode"
+msgstr "get_expanded_loop_offset: código de operación inválido"
 
-#: config/tc-xtensa.c:4737
+#: config/tc-xtensa.c:4751
 #, c-format
-msgid "invalid %d-byte NOP requested"
-msgstr "se requirió un NOP de %d-byte inválido"
+msgid "assembly state not set for first frag in section %s"
+msgstr "no se estableció el estado de ensamblado para el primer fragmento en la sección %s"
 
-#: config/tc-xtensa.c:4757
-msgid "get_expanded_loop_offset: undefined opcode"
-msgstr "get_expanded_loop_offset: código de operación indefinido"
+#: config/tc-xtensa.c:4804
+#, c-format
+msgid "unaligned branch target: %d bytes at 0x%lx"
+msgstr "ramificación de objetivo no alineada: %d bytes en 0x%lx"
 
-#: config/tc-xtensa.c:4764
-msgid "get_expanded_loop_offset: invalid opcode"
-msgstr "get_expanded_loop_offset: código de operación inválido"
+#: config/tc-xtensa.c:4843
+#, c-format
+msgid "unaligned loop: %d bytes at 0x%lx"
+msgstr "ciclo no alineado: %d bytes en 0x%lx"
+
+#: config/tc-xtensa.c:4867
+msgid "unexpected fix"
+msgstr "fix inesperado"
+
+#: config/tc-xtensa.c:4878 config/tc-xtensa.c:4882
+msgid "undecodable fix"
+msgstr "fix que no se puede decodificar"
+
+#: config/tc-xtensa.c:5012
+msgid "labels are not valid inside bundles"
+msgstr "las etiquetas no son válidas dentro de una agrupación"
 
-#: config/tc-xtensa.c:4880
+#: config/tc-xtensa.c:5032
 msgid "invalid last instruction for a zero-overhead loop"
 msgstr "instrucción last inválida para un ciclo con cero adelanto"
 
-#: config/tc-xtensa.c:4935
+#: config/tc-xtensa.c:5097
+msgid "extra opening brace"
+msgstr "llave que abre extra"
+
+#: config/tc-xtensa.c:5107
+msgid "extra closing brace"
+msgstr "llave que cierra extra"
+
+#: config/tc-xtensa.c:5125
+msgid "missing closing brace"
+msgstr "falta una llave que cierra"
+
+#: config/tc-xtensa.c:5205
 #, c-format
-msgid "cannot assemble '%s' into a literal fragment"
-msgstr "no se puede ensamblar '%s' en un fragmento literal"
+msgid "unknown opcode or format name '%s'"
+msgstr "código de operación o nombre de formato `%s' desconocido"
 
-#: config/tc-xtensa.c:4937
-msgid "..."
-msgstr "..."
+#: config/tc-xtensa.c:5211
+msgid "format names only valid inside bundles"
+msgstr "los nombres de formato sólo son válidos dentro de agregados"
 
-#: config/tc-xtensa.c:5071
+#: config/tc-xtensa.c:5216
+#, c-format
+msgid "multiple formats specified for one bundle; using '%s'"
+msgstr "se especificaron múltiples formatos para un agregado; se usa '%s'"
+
+#: config/tc-xtensa.c:5271
 msgid "entry instruction with stack decrement < 16"
 msgstr "onstrucción entry con decremento de pila < 16"
 
-#: config/tc-xtensa.c:5075
+#: config/tc-xtensa.c:5275
 msgid "entry instruction with non-constant decrement"
 msgstr "instrucción entry con decremento que no es constante"
 
-#: config/tc-xtensa.c:5152
-#, c-format
-msgid "undefined @ suffix '%s', expected '%s'"
-msgstr "sufijo @ '%s' indefinido, se esperaba '%s'"
+#: config/tc-xtensa.c:5330
+msgid "unaligned entry instruction"
+msgstr "entrada de instrucción desalineada"
 
-#: config/tc-xtensa.c:5242
-#, c-format
-msgid "invalid operand relocation for '%s' instruction"
-msgstr "operando de reubicación inválido para la instrucción '%s'"
+#: config/tc-xtensa.c:5389
+msgid "bad instruction format"
+msgstr "formato de instrucción erróneo"
 
-#: config/tc-xtensa.c:5245
-#, c-format
-msgid "invalid relocation for operand %d in '%s' instruction"
-msgstr "reubicación inválida para el operando %d en la instrucción '%s'"
+#: config/tc-xtensa.c:5392
+msgid "invalid relocation"
+msgstr "reubicación inválida"
 
-#: config/tc-xtensa.c:5252
+#: config/tc-xtensa.c:5403
 #, c-format
-msgid "invalid relocation type %d for %s instruction"
-msgstr "tipo de reubicación %d inválida para la instrucción %s"
+msgid "invalid relocation for '%s' instruction"
+msgstr "reubicación inválida para la instrucción '%s'"
 
-#: config/tc-xtensa.c:5261
+#: config/tc-xtensa.c:5415
 #, c-format
 msgid "invalid relocation for operand %d of '%s'"
 msgstr "reubicación inválida para el operando %d de '%s'"
 
-#: config/tc-xtensa.c:5269
-#, c-format
-msgid "non-PCREL relocation operand %d for '%s': %s"
-msgstr "operando de reubicación %d que no es PCREL para '%s': %s"
+#: config/tc-xtensa.c:5572
+msgid "cannot represent subtraction with an offset"
+msgstr "no se puede representar la sustracción con un desplazamiento"
 
-#: config/tc-xtensa.c:5328 config/tc-xtensa.c:5366
+#: config/tc-xtensa.c:5660
 #, c-format
 msgid "unhandled local relocation fix %s"
 msgstr "tipo de reubicación fix %s sin manejar"
 
-#: config/tc-xtensa.c:5350
-msgid "undecodable FIX"
-msgstr "FIX que no se puede decodificar"
+#: config/tc-xtensa.c:5968
+msgid "couldn't find a valid instruction format"
+msgstr "no se puede encontrar un formato de instrucción válido"
 
-#: config/tc-xtensa.c:5478
-msgid "emitting simplification relocation"
-msgstr "emitiendo simplificación de reubicación"
+#: config/tc-xtensa.c:5969
+#, c-format
+msgid "    ops were: "
+msgstr "los ops fueron:"
 
-#: config/tc-xtensa.c:5482
-msgid "emitting unknown relocation"
-msgstr "emitiendo reubicación desconocida"
+#: config/tc-xtensa.c:5971
+#, c-format
+msgid " %s;"
+msgstr " %s;"
 
-#: config/tc-xtensa.c:5814
+#: config/tc-xtensa.c:5974
 #, c-format
-msgid "fr_var %lu < length %d; ignoring"
-msgstr "fr_var %lu < longitud %d; se ignora"
+msgid "\n"
+msgstr "\n"
 
-#: config/tc-xtensa.c:6000 config/tc-xtensa.c:6044
-msgid "undecodable instruction in instruction frag"
-msgstr "instrucción no decodificable en la instrucción frag"
+#: config/tc-xtensa.c:5982
+#, c-format
+msgid "format '%s' allows %d slots, but there are %d opcodes"
+msgstr "el formato '%s' permite %d ranuras, pero hay %d códigos de operación"
 
-#: config/tc-xtensa.c:6092
-msgid "invalid empty loop"
-msgstr "ciclo vacío inválido"
+#: config/tc-xtensa.c:5993 config/tc-xtensa.c:6091
+msgid "illegal resource usage in bundle"
+msgstr "se incluyó un recurso ilegal en el agregado"
 
-#: config/tc-xtensa.c:6097
-msgid "loop target does not follow loop instruction in section"
-msgstr "el objetivo del ciclo no sigue la instrucción loop en la sección"
+#: config/tc-xtensa.c:6178
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"
+msgstr "los códigos de operación '%s' (ranura %d) y '%s' (ranura %d) escriben en el mismo registro"
 
-#: config/tc-xtensa.c:6215
-msgid "get_text_align_power: argument too large"
-msgstr "get_text_align_power: argumento demasiado grande"
+#: config/tc-xtensa.c:6183
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"
+msgstr "los códigos de operación '%s' (ranura %d) y '%s' (ranura %d) escriben en el mismo estado"
 
-#: config/tc-xtensa.c:6420 config/tc-xtensa.c:6566
-msgid "invalid opcode for RELAX_ALIGN_NEXT_OPCODE"
-msgstr "código de operación inválido para RELAX_ALIGN_NEXT_OPCODE"
+#: config/tc-xtensa.c:6188
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"
+msgstr "los códigos de operación '%s' (ranura %d) y '%s' (ranura %d) escriben en la misma cola"
+
+#: config/tc-xtensa.c:6193
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"
+msgstr "ambos códigos de operación '%s' (ranura %d) y '%s' (ranura %d) tienen acceso volatile a la cola"
+
+#: config/tc-xtensa.c:6209
+msgid "multiple branches or jumps in the same bundle"
+msgstr "múltiples ramificaciones o saltos en el mismo agregado"
+
+#: config/tc-xtensa.c:6664
+msgid "cannot assemble into a literal fragment"
+msgstr "no se puede ensamblar en un fragmento literal"
+
+#: config/tc-xtensa.c:6666
+msgid "..."
+msgstr "..."
+
+#: config/tc-xtensa.c:7175
+msgid "instruction sequence (write a0, branch, retw) may trigger hardware errata"
+msgstr "la secuencia de instrucción (write a0, branch, retw) puede activar errores de hardware"
+
+#: config/tc-xtensa.c:7285
+msgid "branching or jumping to a loop end may trigger hardware errata"
+msgstr "la ramificación o salto al final de un ciclo puede activar errores de hardware"
+
+#: config/tc-xtensa.c:7384
+msgid "loop end too close to another loop end may trigger hardware errata"
+msgstr "el final de un ciclo demasiado cerca a otro final de ciclo puede activar errores de hardware"
 
-#: config/tc-xtensa.c:6421 config/tc-xtensa.c:6567
-msgid "cannot continue"
-msgstr "no se puede continuar"
+#: config/tc-xtensa.c:7393
+#, c-format
+msgid "fr_var %lu < length %d"
+msgstr "fr_var %lu < longitud %d"
 
-#: config/tc-xtensa.c:6458
-msgid "expected loop opcode in relax align next target"
-msgstr "se esperaba un código de operación de ciclo en el objetivo de relajación de alineación del siguiente"
+#: config/tc-xtensa.c:7564
+msgid "loop containing less than three instructions may trigger hardware errata"
+msgstr "un ciclo que contiene menos de tres instrucciones puede activar errores de hardware"
 
-#: config/tc-xtensa.c:6475
-msgid "expected align_code or RELAX_ALIGN_NEXT_OPCODE"
-msgstr "se esperaba align_code o RELAX_ALIGN_NEXT_OPCODE"
+#: config/tc-xtensa.c:7636
+msgid "undecodable instruction in instruction frag"
+msgstr "instrucción no decodificable en la instrucción frag"
 
-#: config/tc-xtensa.c:6549 config/tc-xtensa.c:6587 config/tc-xtensa.c:6591
-#: config/tc-xtensa.c:6595
-msgid "internal error aligning"
-msgstr "error interno al alinear"
+#: config/tc-xtensa.c:7745
+msgid "invalid empty loop"
+msgstr "ciclo vacío inválido"
 
-#: config/tc-xtensa.c:6676
+#: config/tc-xtensa.c:7750
+msgid "loop target does not follow loop instruction in section"
+msgstr "el objetivo del ciclo no sigue la instrucción loop en la sección"
+
+#: config/tc-xtensa.c:8287
 msgid "bad relaxation state"
 msgstr "estado de relajación erróneo"
 
-#: config/tc-xtensa.c:6752
+#: config/tc-xtensa.c:8345
 #, c-format
-msgid "fr_var (%ld) < length (%d); ignoring"
-msgstr "fr_var (%ld) < longitud (%d); se ignora"
+msgid "fr_var (%ld) < length (%d)"
+msgstr "fr_var (%ld) < longitud (%d)"
 
-#: config/tc-xtensa.c:6928
+#: config/tc-xtensa.c:8846
 msgid "internal error: relaxation failed"
 msgstr "error interno: la relajación falló"
 
-#: config/tc-xtensa.c:6934
+#: config/tc-xtensa.c:8852
 msgid "internal error: relaxation requires too many steps"
 msgstr "error interno: la relajación requiere demasiados pasos"
 
-#: config/tc-xtensa.c:7055
+#: config/tc-xtensa.c:9027
 msgid "invalid relaxation fragment result"
 msgstr "resultado de fragmento de relajación inválido"
 
-#: config/tc-xtensa.c:7128
+#: config/tc-xtensa.c:9107
 msgid "unable to widen instruction"
 msgstr "no se puede ensanchar la instrucción"
 
-#: config/tc-xtensa.c:7215
+#: config/tc-xtensa.c:9250
 msgid "multiple literals in expansion"
 msgstr "literales múltiples en la expansión"
 
-#: config/tc-xtensa.c:7219
+#: config/tc-xtensa.c:9254
 msgid "no registered fragment for literal"
 msgstr "no hay un fragmento registrado para la literal"
 
-#: config/tc-xtensa.c:7221
+#: config/tc-xtensa.c:9256
 msgid "number of literal tokens != 1"
 msgstr "número de elementos literales != 1"
 
-#: config/tc-xtensa.c:7298 config/tc-xtensa.c:7304
+#: config/tc-xtensa.c:9400 config/tc-xtensa.c:9406
 #, c-format
 msgid "unresolved loop target symbol: %s"
 msgstr "símbolo objetivo del ciclo sin resolver: %s"
 
-#: config/tc-xtensa.c:7401
-msgid "loop relaxation specification does not correspond"
-msgstr "la especificación de relajación del ciclo no corresponde"
-
-#: config/tc-xtensa.c:7428
-msgid "loop too long for LOOP instruction"
-msgstr "ciclo demasiado largo para la instrucción LOOP"
-
-#: config/tc-xtensa.c:7465
+#: config/tc-xtensa.c:9512
 #, c-format
 msgid "invalid expression evaluation type %d"
 msgstr "tipo de evaluación expresión %d inválido"
 
-#: config/tc-xtensa.c:7702
+#: config/tc-xtensa.c:9534
+msgid "loop too long for LOOP instruction"
+msgstr "ciclo demasiado largo para la instrucción LOOP"
+
+#: config/tc-xtensa.c:9805
 #, c-format
 msgid "fixes not all moved from %s"
 msgstr "no se movieron todas las composturas de %s"
 
-#: config/tc-xtensa.c:7835
-msgid "inlining literal pool; specify location with .literal_position."
-msgstr "conjunto de literales inlining; especificar la ubicación con .literal_position."
+#: config/tc-xtensa.c:9947
+msgid "literal pool location required for text-section-literals; specify with .literal_position"
+msgstr "se requiere la ubicación del conjunto de literales para text-section-literals; especifique con .literal_position"
 
-#: config/tc-xtensa.c:8230
+#: config/tc-xtensa.c:10456
 #, c-format
 msgid "could not create section %s"
 msgstr "no se puede crear la sección %s"
 
-#: config/tc-xtensa.c:8232
+#: config/tc-xtensa.c:10458
 #, c-format
 msgid "invalid flag combination on section %s"
 msgstr "combinación de opciones inválida en la sección %s"
 
-#: config/tc-xtensa.c:8481
+#: config/tc-xtensa.c:10844
+msgid "too many operands in instruction"
+msgstr "demasiados operandos en la instrucción"
+
+#: config/tc-xtensa.c:11078
 #, c-format
 msgid "invalid symbolic operand %d on '%s'"
 msgstr "operando simbólico %d inválido en '%s'"
 
-#: config/tc-xtensa.c:8545
+#: config/tc-xtensa.c:11147 config/tc-xtensa.c:11221
 msgid "operand number mismatch"
 msgstr "no coinciden el número de operandos"
 
-#: config/tc-xtensa.c:8592
+#: config/tc-xtensa.c:11150
+msgid "cannot encode opcode"
+msgstr "no se codificar el código de operación"
+
+#: config/tc-xtensa.c:11225
+#, c-format
+msgid "cannot encode opcode \"%s\" in the given format \"%s\""
+msgstr "no se codificar el código de operación \"%s\" en el formato dado \"%s\""
+
+#: config/tc-xtensa.c:11250
+#, c-format
+msgid "xtensa-isa failure: %s"
+msgstr "fallo xtensa-isa: %s"
+
+#: config/tc-xtensa.c:11283
 msgid "invalid opcode"
 msgstr "código de operación inválido"
 
-#: config/tc-xtensa.c:8598
+#: config/tc-xtensa.c:11289
 msgid "too few operands"
 msgstr "muy pocos operandos"
 
-#: config/tc-xtensa.c:8817
+#: config/tc-xtensa.c:11416 config/tc-xtensa.c:11424
+msgid "out of memory"
+msgstr "memoria agotada"
+
+#: config/tc-xtensa.c:11536
+msgid "instruction with constant operands does not fit"
+msgstr "la instrucción con operandos constantes no cabe"
+
+#: config/tc-xtensa.c:11545 config/tc-xtensa.c:11566
+#, c-format
+msgid "invalid operand %d on '%s'"
+msgstr "operando %d inválido en '%s'"
+
+#: config/tc-xtensa.c:11557
+msgid "invalid subtract operand"
+msgstr "operando de sustracción inválido"
+
+#: config/tc-xtensa.c:11571
+#, c-format
+msgid "invalid expression for operand %d on '%s'"
+msgstr "expresión inválida para el operando %d en '%s'"
+
+#: config/tc-xtensa.c:11601
+msgid "cannot decode instruction format"
+msgstr "no se puede codificar el formato de instrucción"
+
+#: config/tc-xtensa.c:11760
 msgid "ignoring extra '-rename-section' delimiter ':'"
 msgstr "se ignora el delimitador '-rename-section' ':' extra"
 
-#: config/tc-xtensa.c:8822
+#: config/tc-xtensa.c:11765
 #, c-format
 msgid "ignoring invalid '-rename-section' specification: '%s'"
 msgstr "se ignora la especificación '-rename-section' inválida: %s"
 
-#: config/tc-xtensa.c:8845
+#: config/tc-xtensa.c:11776
 #, c-format
 msgid "section %s renamed multiple times"
 msgstr "se renombró la sección %s varias veces"
 
-#: config/tc-xtensa.c:8847
+#: config/tc-xtensa.c:11778
 #, c-format
 msgid "multiple sections remapped to output section %s"
 msgstr "secciones múltiples remapeadas a la sección de salida %s"
 
-#: config/tc-z8k.c:314
+#: config/tc-z8k.c:268
 #, c-format
 msgid "register rr%d out of range"
 msgstr "registro rr%d fuera de rango"
 
-#: config/tc-z8k.c:316
+#: config/tc-z8k.c:270
 #, c-format
 msgid "register rr%d does not exist"
 msgstr "el registro rr%d no existe"
 
-#: config/tc-z8k.c:326
+#: config/tc-z8k.c:280
 #, c-format
 msgid "register rh%d out of range"
 msgstr "registro rh%d fuera de rango"
 
-#: config/tc-z8k.c:336
+#: config/tc-z8k.c:290
 #, c-format
 msgid "register rl%d out of range"
 msgstr "registro rl%d fuera de rango"
 
-#: config/tc-z8k.c:347
+#: config/tc-z8k.c:301
 #, c-format
 msgid "register rq%d out of range"
 msgstr "registro rq%d fuera de rango"
 
-#: config/tc-z8k.c:349
+#: config/tc-z8k.c:303
 #, c-format
 msgid "register rq%d does not exist"
 msgstr "el registro rq%d no existe"
 
-#: config/tc-z8k.c:359
+#: config/tc-z8k.c:313
 #, c-format
 msgid "register r%d out of range"
 msgstr "registro r%d fuera de rango"
 
-#: config/tc-z8k.c:404
+#: config/tc-z8k.c:354
 #, c-format
 msgid "expected %c"
 msgstr "se esperaba %c"
 
-#: config/tc-z8k.c:421
+#: config/tc-z8k.c:369
 #, c-format
 msgid "register is wrong size for a word %s"
 msgstr "el registro tiene el tamaño erróneo para un word %s"
 
-#: config/tc-z8k.c:437
+#: config/tc-z8k.c:383
 #, c-format
 msgid "register is wrong size for address %s"
 msgstr "el registro tiene el tamaño erróneo para la dirección %s"
 
+#: config/tc-z8k.c:517
+#, c-format
+msgid "unknown interrupt %s"
+msgstr "opción %s desconocida"
+
 #. No interrupt type specified, opcode won't do anything.
-#: config/tc-z8k.c:585
+#: config/tc-z8k.c:540
 msgid "opcode has no effect"
 msgstr "el código de operación no tiene efecto"
 
-#: config/tc-z8k.c:697
+#: config/tc-z8k.c:651
 msgid "Missing ) in ra(rb)"
 msgstr "Falta un ) en ra(rb)"
 
-#: config/tc-z8k.c:919 config/tc-z8k.c:925
+#: config/tc-z8k.c:731 config/tc-z8k.c:770
+#, c-format
+msgid "invalid condition code '%s'"
+msgstr "código de condición '%s' inválido"
+
+#: config/tc-z8k.c:743
+#, c-format
+msgid "invalid flag '%s'"
+msgstr "etiqueta '%s' inválida"
+
+#: config/tc-z8k.c:897 config/tc-z8k.c:903
 msgid "invalid indirect register size"
 msgstr "tamaño de registro indirecto inválido"
 
-#: config/tc-z8k.c:971
-#, c-format
-msgid "operand %s0x%x out of range"
-msgstr "el operando %s0x%x está fuera de rango"
+#: config/tc-z8k.c:920 config/tc-z8k.c:1068 config/tc-z8k.c:1073
+msgid "invalid control register name"
+msgstr "nombre de registro de control inválido"
 
-#: config/tc-z8k.c:1099
+#: config/tc-z8k.c:1057
 msgid "immediate must be 1 or 2"
 msgstr "el inmediato debe ser 1 o 2"
 
-#: config/tc-z8k.c:1102
+#: config/tc-z8k.c:1060
 msgid "immediate 1 or 2 expected"
 msgstr "se esperaba un inmediato 1 o 2"
 
-#: config/tc-z8k.c:1129
+#: config/tc-z8k.c:1091
 msgid "can't use R0 here"
 msgstr "no se puede usar R0 aquí"
 
-#: config/tc-z8k.c:1292
+#: config/tc-z8k.c:1249
 msgid "Can't find opcode to match operands"
 msgstr "No se puede encontrar el código de operación que coincida con los operandos"
 
-#: config/tc-z8k.c:1411
+#: config/tc-z8k.c:1348
 #, c-format
 msgid "invalid architecture -z%s"
 msgstr "arquitectura -z%s inválida"
 
-#: config/tc-z8k.c:1432
+#: config/tc-z8k.c:1368
+#, c-format
 msgid ""
 " Z8K options:\n"
 "  -z8001                  generate segmented code\n"
@@ -10658,391 +11362,408 @@ msgstr ""
 "  -z8002                  genera código sin segmentar\n"
 "  -linkrelax              crea código relajable por el enlazador\n"
 
-#: config/tc-z8k.c:1445
+#: config/tc-z8k.c:1380
+#, c-format
 msgid "call to md_convert_frag\n"
 msgstr "llamada a md_convert_frag\n"
 
-#: config/tc-z8k.c:1476 config/tc-z8k.c:1487
+#: config/tc-z8k.c:1487 config/tc-z8k.c:1527 config/tc-z8k.c:1550
 msgid "cannot branch to odd address"
 msgstr "No se puede ramificar a una dirección impar"
 
-#: config/tc-z8k.c:1479 config/tc-z8k.c:1490
+#: config/tc-z8k.c:1491 config/tc-z8k.c:1554
 msgid "relative jump out of range"
 msgstr "salto relativo fuera de rango"
 
-#: config/tc-z8k.c:1497
-msgid "relative call out of range"
-msgstr "llamada relativa fuera de rango"
-
-#: config/tc-z8k.c:1523
+#: config/tc-z8k.c:1509
 msgid "relative address out of range"
 msgstr "dirección relativa fuera de rango"
 
-#: config/tc-z8k.c:1543
+#: config/tc-z8k.c:1530
+msgid "relative call out of range"
+msgstr "llamada relativa fuera de rango"
+
+#: config/tc-z8k.c:1562
 #, c-format
-msgid "md_apply_fix3: unknown r_type 0x%x\n"
-msgstr "md_apply_fix3: r_type desconocido: 0x%x\n"
+msgid "md_apply_fix: unknown r_type 0x%x\n"
+msgstr "md_apply_fix: r_type 0x%x desconocido\n"
 
-#: config/tc-z8k.c:1556
+#: config/tc-z8k.c:1574
+#, c-format
 msgid "call to md_estimate_size_before_relax\n"
 msgstr "llamada a md_estimate_size_before_relax\n"
 
-#: config/tc-z8k.c:1600
-#, c-format
-msgid "Can't subtract symbols in different sections %s %s"
-msgstr "No se pueden sustraer los símbolos en secciones diferentes %s %s"
-
-#: depend.c:200
+#: depend.c:193
 #, c-format
 msgid "can't open `%s' for writing"
 msgstr "no se puede abrir `%s' para escritura"
 
-#: depend.c:212
+#: depend.c:205
 #, c-format
 msgid "can't close `%s'"
 msgstr "no se puede cerrar `%s'"
 
-#: dw2gencfi.c:262
+#: dw2gencfi.c:258
 #, c-format
 msgid "register save offset not a multiple of %u"
 msgstr "el desplazamiento del registro save no es un múltiplo de %u"
 
-#: dw2gencfi.c:388
+#: dw2gencfi.c:341
+msgid "CFI state restore without previous remember"
+msgstr "se usó un state restore de CFI sin un remember previo"
+
+#: dw2gencfi.c:387
 msgid "missing separator"
 msgstr "falta el separador"
 
-#: dw2gencfi.c:410 dw2gencfi.c:428
+#: dw2gencfi.c:409 dw2gencfi.c:427
 msgid "bad register expression"
 msgstr "expresión de registro inválida"
 
-#: dw2gencfi.c:450 dw2gencfi.c:547
+#: dw2gencfi.c:449 dw2gencfi.c:551
 msgid "CFI instruction used without previous .cfi_startproc"
 msgstr "se utilizó la instrucción CFI sin un .cfi_startproc precedente"
 
-#: dw2gencfi.c:579
+#: dw2gencfi.c:587
 msgid "previous CFI entry not closed (missing .cfi_endproc)"
 msgstr "la entrada CFI previa no está cerrada (falta un .cfi_endproc)"
 
-#: dw2gencfi.c:612
+#: dw2gencfi.c:622
 msgid ".cfi_endproc without corresponding .cfi_startproc"
 msgstr ".cfi_endproc sin un .cfi_startproc correspondiente"
 
-#: dw2gencfi.c:987
+#: dw2gencfi.c:1031
 msgid "open CFI at the end of file; missing .cfi_endproc directive"
 msgstr "un CFI abierto al final del fichero; falta una directiva .cfi_endproc"
 
-#: dwarf2dbg.c:468 dwarf2dbg.c:498
+#: dwarf2dbg.c:523 dwarf2dbg.c:549
 msgid "file number less than one"
 msgstr "número de fichero menor que uno"
 
-#: dwarf2dbg.c:474
+#: dwarf2dbg.c:529
 #, c-format
 msgid "file number %ld already allocated"
 msgstr "el número de fichero %ld ya está reservado"
 
-#: dwarf2dbg.c:503 dwarf2dbg.c:1068
+#: dwarf2dbg.c:554 dwarf2dbg.c:1169
 #, c-format
 msgid "unassigned file number %ld"
 msgstr "número de fichero %ld sin asignar"
 
-#: dwarf2dbg.c:1134 dwarf2dbg.c:1331
+#: dwarf2dbg.c:622
+msgid "is_stmt value not 0 or 1"
+msgstr "el valor is_stmt no es 0 ó 1"
+
+#: dwarf2dbg.c:634
+msgid "isa number less than zero"
+msgstr "número isa menor que uno"
+
+#: dwarf2dbg.c:640
+#, c-format
+msgid "unknown .loc sub-directive `%s'"
+msgstr "sub-directiva .loc `%s' desconocida"
+
+#: dwarf2dbg.c:1234 dwarf2dbg.c:1428
 msgid "internal error: unknown dwarf2 format"
 msgstr "error interno: formato dwarf2 desconocido"
 
-#: dwarf2dbg.c:1476 dwarf2dbg.c:1484 dwarf2dbg.c:1492 dwarf2dbg.c:1513
-msgid "dwarf2 is not supported for this object file format"
-msgstr "dwarf2 no tiene soporte para este formato de fichero objeto"
-
-#: ecoff.c:1556
+#: ecoff.c:1552
 #, c-format
 msgid "string too big (%lu bytes)"
 msgstr "cadena demasiado grande (%lu bytes)"
 
-#: ecoff.c:1582
+#: ecoff.c:1578
 #, c-format
 msgid "inserting \"%s\" into string hash table: %s"
 msgstr "se inserta \"%s\" en la tabla de de dispersión de cadenas: %s"
 
-#: ecoff.c:1614 ecoff.c:1808 ecoff.c:1833 ecoff.c:1865 ecoff.c:2019
-#: ecoff.c:2132
+#: ecoff.c:1609 ecoff.c:1802 ecoff.c:1825 ecoff.c:1856 ecoff.c:2009
+#: ecoff.c:2120
 msgid "no current file pointer"
-msgstr "no hay un apuntador a fichero actualmente"
+msgstr "no hay un puntero a fichero actualmente"
 
-#: ecoff.c:1701
+#: ecoff.c:1696
 msgid "too many st_End's"
 msgstr "demasiados st_End's"
 
-#: ecoff.c:2044
+#: ecoff.c:2034
 #, c-format
 msgid "inserting \"%s\" into tag hash table: %s"
 msgstr "se inserta \"%s\" en la tabla de de dispersión de marcas: %s"
 
-#: ecoff.c:2210
+#: ecoff.c:2195
 msgid "fake .file after real one"
 msgstr ".file falso después del real"
 
-#: ecoff.c:2300
+#: ecoff.c:2285
 msgid "filename goes over one page boundary"
 msgstr "el nombre de fichero sobrepasa el límite de una página."
 
-#: ecoff.c:2435
+#: ecoff.c:2418
 msgid ".begin directive without a preceding .file directive"
 msgstr "directiva .begin sin una directiva .file precedente"
 
-#: ecoff.c:2442
+#: ecoff.c:2425
 msgid ".begin directive without a preceding .ent directive"
 msgstr "directiva .begin sin una directiva .ent precedente"
 
-#: ecoff.c:2474
+#: ecoff.c:2456
 msgid ".bend directive without a preceding .file directive"
 msgstr "directiva .bend sin una directiva .file precedente"
 
-#: ecoff.c:2481
+#: ecoff.c:2463
 msgid ".bend directive without a preceding .ent directive"
 msgstr "directiva .bend sin una directiva .ent precedente"
 
-#: ecoff.c:2494
+#: ecoff.c:2476
 msgid ".bend directive names unknown symbol"
 msgstr "símbolo desconocido en los nombres de la directiva .bend"
 
-#: ecoff.c:2538
+#: ecoff.c:2519
 msgid ".def pseudo-op used inside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .def dentro de .def/.endef; se ignora"
 
-#: ecoff.c:2540
+#: ecoff.c:2521
 msgid "empty symbol name in .def; ignored"
 msgstr "nombre de símbolo vacío en .def; se ignora"
 
-#: ecoff.c:2578
+#: ecoff.c:2558
 msgid ".dim pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .dim fuera de .def/.endef; se ignora"
 
-#: ecoff.c:2593
+#: ecoff.c:2573
 msgid "badly formed .dim directive"
 msgstr "directiva .dim mal formada"
 
-#: ecoff.c:2606
+#: ecoff.c:2586
 msgid "too many .dim entries"
 msgstr "demasiadas entradas .dim"
 
-#: ecoff.c:2627
+#: ecoff.c:2606
 msgid ".scl pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .scl fuera de .def/.endef; se ignora"
 
-#: ecoff.c:2653
+#: ecoff.c:2631
 msgid ".size pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .size fuera de .def/.endef; se ignora"
 
-#: ecoff.c:2668
+#: ecoff.c:2646
 msgid "badly formed .size directive"
 msgstr "directiva .size mal formada"
 
-#: ecoff.c:2681
+#: ecoff.c:2659
 msgid "too many .size entries"
 msgstr "demasiadas entradas .size"
 
-#: ecoff.c:2704
+#: ecoff.c:2681
 msgid ".type pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .type fuera de .def/.endef; se ignora"
 
 #. FIXME: We could handle this by setting the continued bit.
 #. There would still be a limit: the .type argument can not
 #. be infinite.
-#: ecoff.c:2722
+#: ecoff.c:2699
 #, c-format
 msgid "the type of %s is too complex; it will be simplified"
 msgstr "el tipo de %s es demasiado complejo; se simplificará"
 
-#: ecoff.c:2733
+#: ecoff.c:2710
 msgid "Unrecognized .type argument"
 msgstr "Argumento .type no reconocido"
 
-#: ecoff.c:2772
+#: ecoff.c:2748
 msgid ".tag pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .tag fuera de .def/.endef; se ignora"
 
-#: ecoff.c:2798
+#: ecoff.c:2773
 msgid ".val pseudo-op used outside of .def/.endef; ignored"
 msgstr "se utiliza el pseudo-operador .val fuera de .def/.endef; se ignora"
 
-#: ecoff.c:2806
+#: ecoff.c:2781
 msgid ".val expression is too copmlex"
 msgstr "la expresión .val es demasiado compleja"
 
-#: ecoff.c:2837
+#: ecoff.c:2811
 msgid ".endef pseudo-op used before .def; ignored"
 msgstr "se utiliza el pseudo-operador .endef antes de .def; se ignora"
 
-#: ecoff.c:2863 ecoff.c:2944
+#: ecoff.c:2837 ecoff.c:2918
 msgid "bad COFF debugging information"
 msgstr "información de depuración COFF errónea"
 
-#: ecoff.c:2912
+#: ecoff.c:2886
 #, c-format
 msgid "no tag specified for %s"
 msgstr "no se especificó una marca para %s"
 
-#: ecoff.c:3015
+#: ecoff.c:2988
 msgid ".end directive without a preceding .file directive"
 msgstr "directiva .end sin una directiva .file precedente"
 
-#: ecoff.c:3022
+#: ecoff.c:2995
 msgid ".end directive without a preceding .ent directive"
 msgstr "directiva .end sin una directiva .ent precedente"
 
-#: ecoff.c:3044
+#: ecoff.c:3017
 msgid ".end directive names unknown symbol"
 msgstr "símbolo desconocido en los nombres de la directiva .end"
 
-#: ecoff.c:3072
+#: ecoff.c:3044
 msgid "second .ent directive found before .end directive"
 msgstr "se encontró una segunda directiva .ent antes de la directiva .end"
 
-#: ecoff.c:3146
+#: ecoff.c:3116
 msgid "no way to handle .file within .ent/.end section"
 msgstr "no es posible manejar un .file dentro de una sección .ent/.end"
 
-#: ecoff.c:3271
+#: ecoff.c:3233
 msgid ".loc before .file"
 msgstr ".loc antes de .file"
 
-#: ecoff.c:3410
+#: ecoff.c:3355 read.c:1473 read.c:1579 read.c:2256 read.c:2803 symbols.c:327
+#: symbols.c:423
+#, c-format
+msgid "symbol `%s' is already defined"
+msgstr "el símbolo `%s' ya está definido"
+
+#: ecoff.c:3368
 msgid "bad .weakext directive"
 msgstr "directiva .weakext errónea"
 
-#: ecoff.c:3479
+#: ecoff.c:3436
 #, c-format
 msgid ".stab%c is not supported"
 msgstr ".stab%c no tiene soporte"
 
-#: ecoff.c:3489
+#: ecoff.c:3446
 #, c-format
 msgid ".stab%c: ignoring non-zero other field"
 msgstr ".stab%c: se ignora el otro campo que no es cero"
 
-#: ecoff.c:3523
+#: ecoff.c:3480
 #, c-format
 msgid "line number (%d) for .stab%c directive cannot fit in index field (20 bits)"
 msgstr "el número de línea (%d) para la directiva .stab%c no cabe en el campo de índice (20 bits)"
 
-#: ecoff.c:3559
+#: ecoff.c:3516
 #, c-format
 msgid "illegal .stab%c directive, bad character"
 msgstr "directiva .stab%c ilegal, carácter erróneo"
 
-#: ecoff.c:4021 ecoff.c:4210 ecoff.c:4235
+#: ecoff.c:3975 ecoff.c:4164 ecoff.c:4189
 msgid ".begin/.bend in different segments"
 msgstr ".begin/.bend en segmentos diferentes"
 
-#: ecoff.c:4737
+#: ecoff.c:4685
 msgid "missing .end or .bend at end of file"
 msgstr "falta un .end o un .bend al final del fichero"
 
-#: ecoff.c:5227
+#: ecoff.c:5170
 msgid "GP prologue size exceeds field size, using 0 instead"
 msgstr "el tamaño del prólogo GP excede el tamaño del campo, se utiliza 0 en su lugar"
 
-#: expr.c:83 read.c:3232
+#: expr.c:82 read.c:3351
 msgid "bignum invalid"
 msgstr "bignum inválido"
 
-#: expr.c:85 read.c:3234 read.c:3574 read.c:4474
+#: expr.c:84 read.c:3353 read.c:3702 read.c:4550
 msgid "floating point number invalid"
 msgstr "número de coma flotante inválido"
 
-#: expr.c:243
+#: expr.c:203
 msgid "bad floating-point constant: exponent overflow"
 msgstr "constante de coma flotante errónea: desbordamiento del exponente"
 
-#: expr.c:247
+#: expr.c:207
 #, c-format
 msgid "bad floating-point constant: unknown error code=%d"
 msgstr "constante de coma flotante errónea: código de error desconocido=%d"
 
-#: expr.c:425
+#: expr.c:383
 msgid "a bignum with underscores may not have more than 8 hex digits in any word"
 msgstr "un número grande con subrayados no puede tener más de 8 dígitos hexadecimales en cualquier palabra"
 
-#: expr.c:448
+#: expr.c:406
 msgid "a bignum with underscores must have exactly 4 words"
 msgstr "un número grande con subrayados debe tener exactamente 4 palabras"
 
 #. Either not seen or not defined.
 #. @@ Should print out the original string instead of
 #. the parsed number.
-#: expr.c:571
+#: expr.c:529
 #, c-format
 msgid "backward ref to unknown label \"%d:\""
 msgstr "referencia hacia atrás a la etiqueta desconocida \"%d:\""
 
-#: expr.c:694
+#: expr.c:647
 msgid "character constant too large"
 msgstr "la constante de carácter es demasiado grande"
 
-#: expr.c:942
+#: expr.c:893
 #, c-format
 msgid "expr.c(operand): bad atof_generic return val %d"
 msgstr "expr.c(operando): valor de devolución %d atof_generic erróneo"
 
-#: expr.c:1004
+#: expr.c:954
 #, c-format
 msgid "missing '%c'"
 msgstr "falta un '%c'"
 
-#: expr.c:1016 read.c:3945
+#: expr.c:965 read.c:4034
 msgid "EBCDIC constants are not supported"
 msgstr "las constantes EBCDIC no tienen soporte"
 
-#: expr.c:1099
+#: expr.c:1082
 #, c-format
 msgid "Unary operator %c ignored because bad operand follows"
 msgstr "Se ignora el operador unario %c porque hay un operando erróneo a continuación"
 
-#: expr.c:1145 expr.c:1170
+#: expr.c:1128 expr.c:1153
 msgid "syntax error in .startof. or .sizeof."
 msgstr "error sintáctico en .startof. o .sizeof."
 
-#: expr.c:1666
+#: expr.c:1665
 msgid "missing operand; zero assumed"
 msgstr "falta un operando; se asume cero"
 
-#: expr.c:1701
+#: expr.c:1700
 msgid "left operand is a bignum; integer 0 assumed"
 msgstr "el operando izquierdo es un número grande; se asume el entero 0"
 
-#: expr.c:1703
+#: expr.c:1702
 msgid "left operand is a float; integer 0 assumed"
 msgstr "el operando izquierdo es un número de coma flotante; se asume el entero 0"
 
-#: expr.c:1712
+#: expr.c:1711
 msgid "right operand is a bignum; integer 0 assumed"
 msgstr "el operando derecho es un número grande; se asume el entero 0"
 
-#: expr.c:1714
+#: expr.c:1713
 msgid "right operand is a float; integer 0 assumed"
 msgstr "el operando derecho es un número de coma flotante; se asume el entero 0"
 
-#: expr.c:1770 symbols.c:1191
+#: expr.c:1769 symbols.c:1207
 msgid "division by zero"
 msgstr "división por cero"
 
-#: expr.c:1868
+#: expr.c:1867
 msgid "operation combines symbols in different segments"
 msgstr "la operación combina símbolos en segmentos diferentes"
 
-#: frags.c:87
-#, c-format
-msgid "can't extend frag %u chars"
-msgstr "no se pueden extender %u caracteres de fragmento"
-
-#: frags.c:168
+#: frags.c:48
 msgid "attempt to allocate data in absolute section"
 msgstr "se intentó alojar datos en la sección absoluta"
 
-#: frags.c:174
+#: frags.c:54
 msgid "attempt to allocate data in common section"
 msgstr "se intentó alojar datos en la sección común"
 
+#: frags.c:112
+#, c-format
+msgid "can't extend frag %u chars"
+msgstr "no se pueden extender %u caracteres de fragmento"
+
+#. For error messages.
 #. Detect if we are reading from stdin by examining the file
 #. name returned by as_where().
 #.
@@ -11054,508 +11775,615 @@ msgstr "se intentó alojar datos en la sección común"
 #. line here (assuming of course that we actually have a line of
 #. input to read), so that it can be displayed in the listing
 #. that is produced at the end of the assembly.
-#: input-file.c:145 input-scrub.c:242 listing.c:343
+#: input-file.c:141 input-scrub.c:238 listing.c:332
 msgid "{standard input}"
 msgstr "{entrada estándar}"
 
-#: input-file.c:149
+#: input-file.c:147 input-file.c:156
 #, c-format
-msgid "can't open %s for reading"
-msgstr "no se puede abrir %s para lectura"
+msgid "Can't open %s for reading"
+msgstr "No se puede abrir %s para lectura"
 
-#: input-file.c:212 input-file.c:239
+#: input-file.c:219 input-file.c:246
 #, c-format
 msgid "Can't read from %s"
 msgstr "No se puede leer de %s"
 
-#: input-file.c:247
+#: input-file.c:256
 #, c-format
 msgid "Can't close %s"
 msgstr "No se puede cerrar %s"
 
-#: input-scrub.c:272
+#: input-scrub.c:263
 msgid "macros nested too deeply"
 msgstr "macros anidadas con demasiada profundidad"
 
-#: input-scrub.c:375 input-scrub.c:397
+#: input-scrub.c:365 input-scrub.c:387
 msgid "partial line at end of file ignored"
 msgstr "se ignora la línea parcial al final del fichero"
 
-#: itbl-ops.c:351
+#: itbl-ops.c:338
+#, c-format
 msgid "Unable to allocate memory for new instructions\n"
 msgstr "No se puede reservar memoria para las instrucciones nuevas\n"
 
-#: listing.c:243
+#: listing.c:238
 msgid "Warning:"
 msgstr "Aviso:"
 
-#: listing.c:250
+#: listing.c:244
 msgid "Error:"
 msgstr "Error:"
 
-#: listing.c:1130
+#: listing.c:1089
 #, c-format
 msgid "can't open list file: %s"
 msgstr "no se puede abrir el fichero de lista: %s"
 
-#: listing.c:1154
+#: listing.c:1109
 #, c-format
 msgid "error closing list file: %s"
 msgstr "error al cerrar el fichero de lista: %s"
 
-#: listing.c:1233
+#: listing.c:1182
 msgid "strange paper height, set to no form"
 msgstr "tamaño de papel extraño, se establece a sin forma"
 
-#: listing.c:1299
+#: listing.c:1246
 msgid "new line in title"
 msgstr "línea nueva en el título"
 
 #. Turns the next expression into a string.
-#: macro.c:382
+#: macro.c:436
 #, no-c-format
 msgid "% operator needs absolute expression"
 msgstr "el operador % necesita una expresión absoluta"
 
-#: macro.c:545
-msgid "unexpected end of file in macro definition"
-msgstr "fin de fichero inesperado en la definición de macro"
+#: macro.c:558
+#, c-format
+msgid "Missing parameter qualifier for `%s' in macro `%s'"
+msgstr "Falta el calificador de parámetro para `%s' en la macro `%s'"
+
+#: macro.c:568
+#, c-format
+msgid "`%s' is not a valid parameter qualifier for `%s' in macro `%s'"
+msgstr "`%s' no es un calificador de parámetro válido para `%s' en la macro `%s'"
+
+#: macro.c:585
+#, c-format
+msgid "Pointless default value for required parameter `%s' in macro `%s'"
+msgstr "Valor por defecto sin sentido para el parámetro requerido `%s' en la macro `%s'"
+
+#: macro.c:597
+#, c-format
+msgid "A parameter named `%s' already exists for macro `%s'"
+msgstr "Ya existe un parámetro llamado `%s' para la macro `%s'"
+
+#: macro.c:634
+#, c-format
+msgid "Reserved word `%s' used as parameter in macro `%s'"
+msgstr "Se usó la palabra reservada `%s' como un parámetro en la macro `%s'"
+
+#: macro.c:672
+#, c-format
+msgid "unexpected end of file in macro `%s' definition"
+msgstr "fin de fichero inesperado en la definición de macro `%s'"
+
+#: macro.c:684
+#, c-format
+msgid "missing `)' after formals in macro definition `%s'"
+msgstr "falta `)' después de los formales en la definición de macro `%s'"
 
-#: macro.c:554
-msgid "missing ) after formals"
-msgstr "falta ) después de los formales"
+#: macro.c:699
+msgid "Missing macro name"
+msgstr "Falta el nombre de macro"
 
-#: macro.c:703
-msgid "missplaced )"
-msgstr ") mal colocado"
+#: macro.c:708
+#, c-format
+msgid "Bad parameter list for macro `%s'"
+msgstr "Lista de parámetros errónea para la macro `%s'"
 
-#: macro.c:960
+#: macro.c:714
+#, c-format
+msgid "Macro `%s' was already defined"
+msgstr "La macro `%s' ya está definida"
+
+#: macro.c:837 macro.c:839
+msgid "missing `)'"
+msgstr "falta un `)'"
+
+#: macro.c:934
+#, c-format
+msgid "`%s' was already used as parameter (or another local) name"
+msgstr "Ya se usó `%s' como nombre (u otro local) de parámetro"
+
+#: macro.c:1093
 msgid "confusion in formal parameters"
 msgstr "confusión en los parámetros formales"
 
-#: macro.c:965
-msgid "macro formal argument does not exist"
-msgstr "el argumento formal de macro no existe"
+#: macro.c:1100
+#, c-format
+msgid "Parameter named `%s' does not exist for macro `%s'"
+msgstr "El parámetro nombrado '%s' no existe para la macro `%s'"
+
+#: macro.c:1108
+#, c-format
+msgid "Value for parameter `%s' of macro `%s' was already specified"
+msgstr "Ya se había especificado el valor para el parámetro `%s' de la macro `%s'"
 
-#: macro.c:980
+#: macro.c:1124
 msgid "can't mix positional and keyword arguments"
 msgstr "no se pueden mezclar argumentos posicionales y palabras clave"
 
-#: macro.c:988
+#: macro.c:1135
 msgid "too many positional arguments"
 msgstr "demasiados argumentos posicionales"
 
-#: macro.c:1163
+#: macro.c:1183
+#, c-format
+msgid "Missing value for required parameter `%s' of macro `%s'"
+msgstr "Falta el valor para el parámetro requerido `%s' de la macro `%s'"
+
+#: macro.c:1320
+#, c-format
+msgid "Attempt to purge non-existant macro `%s'"
+msgstr "se intentó purgar la macro inexistente `%s'"
+
+#: macro.c:1339
 msgid "unexpected end of file in irp or irpc"
 msgstr "fin de fichero inesperado en irp ó irpc"
 
-#: macro.c:1171
+#: macro.c:1347
 msgid "missing model parameter"
 msgstr "falta el parámetro modelo"
 
 #: messages.c:104
+#, c-format
 msgid "Assembler messages:\n"
 msgstr "Mensajes del ensamblador:\n"
 
-#: messages.c:214
+#: messages.c:206
+#, c-format
 msgid "Warning: "
 msgstr "Aviso: "
 
-#: messages.c:318
+#: messages.c:307
+#, c-format
 msgid "Error: "
 msgstr "Error: "
 
-#: messages.c:413 messages.c:433
+#: messages.c:402 messages.c:422
+#, c-format
 msgid "Fatal error: "
 msgstr "Error fatal: "
 
-#: messages.c:450
+#: messages.c:437
+#, c-format
 msgid "Internal error!\n"
 msgstr "¡Error interno!\n"
 
-#: messages.c:452
+#: messages.c:439
 #, c-format
 msgid "Assertion failure in %s at %s line %d.\n"
 msgstr "Falla de afirmación en %s en %s línea %d.\n"
 
-#: messages.c:455
+#: messages.c:442
 #, c-format
 msgid "Assertion failure at %s line %d.\n"
 msgstr "Falla de afirmación en %s línea %d.\n"
 
-#: messages.c:456 messages.c:475
+#: messages.c:443 messages.c:460
+#, c-format
 msgid "Please report this bug.\n"
 msgstr "Por favor reporte este bicho.\n"
 
-#: messages.c:470
+#: messages.c:455
 #, c-format
 msgid "Internal error, aborting at %s line %d in %s\n"
 msgstr "Error interno, abortando en %s línea %d en %s\n"
 
-#: messages.c:473
+#: messages.c:458
 #, c-format
 msgid "Internal error, aborting at %s line %d\n"
 msgstr "Error interno, abortando en %s línea %d\n"
 
-#: output-file.c:48
+#: messages.c:507
+#, c-format
+msgid "%s out of range (%d is not between %d and %d)"
+msgstr "%s fuera de rango (%d no está entre %d y %d)"
+
+#. xgettext:c-format.
+#: messages.c:530
+#, c-format
+msgid "%s out of range (0x%s is not between 0x%s and 0x%s)"
+msgstr "%s fuera de rango (0x%s no está entre 0x%s y 0x%s)"
+
+#: output-file.c:39
 #, c-format
 msgid "can't open a bfd on stdout %s"
 msgstr "no se puede abrir un bfd en la salida estándar %s"
 
-#: output-file.c:52 output-file.c:115
+#: output-file.c:44
+#, c-format
+msgid "Selected target format '%s' unknown"
+msgstr "Formato de objetivo seleccionado '%s' desconocido"
+
+#: output-file.c:46
 #, c-format
 msgid "FATAL: can't create %s"
 msgstr "FATAL: no se puede crear %s"
 
-#: output-file.c:73 output-file.c:80
+#: output-file.c:63
 #, c-format
 msgid "FATAL: can't close %s\n"
 msgstr "FATAL: no se puede cerrar %s\n"
 
-#: output-file.c:126
-#, c-format
-msgid "FATAL: can't close %s"
-msgstr "FATAL: no se puede cerrar %s"
-
-#: output-file.c:147
-msgid "Failed to emit an object byte"
-msgstr "Falló al emitir un byte objeto"
-
-#: output-file.c:148
-msgid "can't continue"
-msgstr "no se puede continuar"
+#: read.c:450
+msgid "bad or irreducible absolute expression"
+msgstr "expresión absoluta errónea o irreducible"
 
-#: read.c:442
+#: read.c:476
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr "error al construir la tabla de pseudo-operadores %s: %s"
 
-#: read.c:809
+#: read.c:896
 #, c-format
 msgid "unknown pseudo-op: `%s'"
 msgstr "pseudo-operador desconocido: `%s'"
 
-#: read.c:940
+#: read.c:983
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr "etiqueta \"%d$\" redefinida"
 
-#: read.c:1152
+#: read.c:1214
 msgid ".abort detected.  Abandoning ship."
 msgstr "se detectó .abort.  Abandonando la nave."
 
-#: read.c:1174 read.c:2413
+#: read.c:1232 read.c:2406
 msgid "ignoring fill value in absolute section"
 msgstr "se ignora el valor de relleno en la sección absoluta"
 
-#: read.c:1260
+#: read.c:1322
 #, c-format
 msgid "alignment too large: %u assumed"
 msgstr "la alineación es demasiado grande: se asume %u"
 
-#: read.c:1292
+#: read.c:1354
 msgid "expected fill pattern missing"
 msgstr "falta el patrón de relleno esperado"
 
-#: read.c:1417
+#: read.c:1457
+msgid "missing size expression"
+msgstr "falta una expresión de tamaño"
+
+#: read.c:1463
 #, c-format
-msgid "length of .comm \"%s\" is already %ld; not changing to %ld"
-msgstr "la longitud de .comm \"%s\" ya es %ld; no se cambia a %ld"
+msgid "size (%ld) out of range, ignored"
+msgstr "tamaño (%ld) fuera de rango, se ignora"
+
+#: read.c:1483
+#, c-format
+msgid "size of \"%s\" is already %ld; not changing to %ld"
+msgstr "la longitud de \"%s\" ya es %ld; no se cambia a %ld"
 
 #. Some of the back ends can't deal with non-positive line numbers.
-#. Besides, it's silly.
-#: read.c:1636
+#. Besides, it's silly.  GCC however will generate a line number of
+#. zero when it is pre-processing builtins for assembler-with-cpp files:
+#.
+#. # 0 "<built-in>"
+#.
+#. We do not want to barf on this, especially since such files are used
+#. in the GCC and GDB testsuites.  So we check for negative line numbers
+#. rather than non-positive line numbers.
+#: read.c:1712
 #, c-format
 msgid "line numbers must be positive; line number %d rejected"
 msgstr "los números de línea deben ser positivos; se rechazó el número de línea %d."
 
-#: read.c:1664
+#: read.c:1739
 msgid "start address not supported"
 msgstr "la dirección de inicio no tiene soporte"
 
-#: read.c:1674
+#: read.c:1748
 msgid ".err encountered"
 msgstr "se encontró .err"
 
-#: read.c:1693 read.c:1695
+#: read.c:1764
+msgid ".error directive invoked in source file"
+msgstr "se invocó la directiva .error en el fichero fuente"
+
+#: read.c:1765
+msgid ".warning directive invoked in source file"
+msgstr "se invocó la directiva .warning en el fichero fuente"
+
+#: read.c:1771
+#, c-format
+msgid "%s argument must be a string"
+msgstr "el argumento %s debe ser una cadena"
+
+#: read.c:1803 read.c:1805
 #, c-format
 msgid ".fail %ld encountered"
 msgstr "se encontró .fail %ld"
 
-#: read.c:1732
+#: read.c:1841
 #, c-format
 msgid ".fill size clamped to %d"
 msgstr "el tamaño de fill se restringe a %d"
 
-#: read.c:1737
+#: read.c:1846
 msgid "size negative; .fill ignored"
 msgstr "tamaño negativo; se ignora .fill"
 
-#: read.c:1743
+#: read.c:1852
 msgid "repeat < 0; .fill ignored"
 msgstr "repetición < 0; se ignora .fill"
 
-#: read.c:1903
+#: read.c:2010
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr "tipo .linkonce `%s' no reconocido"
 
-#: read.c:1916 read.c:1942
+#: read.c:2022
 msgid ".linkonce is not supported for this object file format"
 msgstr ".linkonce no tiene soporte en este formato de fichero objeto"
 
-#: read.c:1938
+#: read.c:2044
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr "bfd_set_section_flags: %s"
 
-#: read.c:1993
-msgid "missing size expression"
-msgstr "falta una expresión de tamaño"
-
-#: read.c:1999
-#, c-format
-msgid "BSS length (%d) < 0 ignored"
-msgstr "se ignora la longitud BSS (%d) <0"
-
-#: read.c:2015
+#: read.c:2070
 #, c-format
 msgid "error setting flags for \".sbss\": %s"
 msgstr "error al establecer las opciones para \".sbss\": %s"
 
-#: read.c:2038
-msgid "expected comma after size"
-msgstr "se esperaba una coma después del tamaño"
+#: read.c:2117
+msgid "expected alignment after size"
+msgstr "se esperaba alineación después del tamaño"
 
-#: read.c:2072
-#, c-format
-msgid "alignment too large; %d assumed"
-msgstr "alineación demasiado grande; se asume %d"
-
-#: read.c:2077
+#: read.c:2131
 msgid "alignment negative; 0 assumed"
 msgstr "alineación negativa; se asume 0"
 
-#: read.c:2342
+#: read.c:2340
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr "se ignora el intento de redefinir el pseudo-operador `%s'"
 
-#: read.c:2408
+#: read.c:2401
 #, c-format
 msgid "invalid segment \"%s\""
 msgstr "segmento \"%s\" inválido"
 
-#: read.c:2416
+#: read.c:2409
 msgid "only constant offsets supported in absolute section"
 msgstr "sólo los desplazamientos constantes tienen soporte en la sección absoluta"
 
-#: read.c:2456
+#: read.c:2448
 msgid "MRI style ORG pseudo-op not supported"
 msgstr "el pseudo-operador ORG de estilo MRI no tiene soporte"
 
-#: read.c:2613
+#: read.c:2601
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr "tipo de sección `%s' no reconocido"
 
-#: read.c:2627
+#: read.c:2615
 msgid "absolute sections are not supported"
 msgstr "las secciones absolutas no tienen soporte"
 
-#: read.c:2642
+#: read.c:2630
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr "comando de sección `%s' no reconocido"
 
-#: read.c:2708
-msgid ".endr encountered without preceeding .rept, .irc, or .irp"
-msgstr "se encontró una directiva .endr sin una directiva .rept, .irc, ó .irp precedente"
+#: read.c:2694
+#, c-format
+msgid ".end%c encountered without preceeding %s"
+msgstr "se encontró .end%c sin un %s precedente"
 
-#: read.c:2740
+#: read.c:2724
 #, c-format
 msgid "%s without %s"
 msgstr "%s sin %s"
 
-#: read.c:2949
+#: read.c:2951
 msgid "unsupported variable size or fill value"
 msgstr "tamaño de variable o valor de relleno sin soporte"
 
-#: read.c:2974
+#: read.c:2979
 msgid ".space repeat count is zero, ignored"
 msgstr "la cuenta de repetición .space es cero, se ignora"
 
-#: read.c:2976
+#: read.c:2981
 msgid ".space repeat count is negative, ignored"
 msgstr "la cuenta de repetición .space es negativa, se ignora"
 
-#: read.c:3005
+#: read.c:3010
 msgid "space allocation too complex in absolute section"
 msgstr "la asignación de espacio es demasiado compleja en la sección absoluta"
 
-#: read.c:3011
+#: read.c:3016
 msgid "space allocation too complex in common section"
 msgstr "la asignación de espacio es demasiado compleja en la sección común"
 
-#: read.c:3099 read.c:4190
+#: read.c:3103 read.c:4276
 #, c-format
 msgid "bad floating literal: %s"
 msgstr "literal de coma flotante errónea: %s"
 
-#: read.c:3172
+#: read.c:3243
 #, c-format
-msgid "rest of line ignored; first ignored character is `%c'"
-msgstr "se ignora el resto de la línea; el primer carácter ignorado es `%c'"
+msgid "%s: would close weakref loop: %s"
+msgstr "%s: cerraría el ciclo weakref: %s"
+
+#: read.c:3286
+#, c-format
+msgid "junk at end of line, first unrecognized character is `%c'"
+msgstr "basura al final de la línea; el primer carácter ignorado es `%c'"
 
-#: read.c:3175
+#: read.c:3289
 #, c-format
-msgid "rest of line ignored; first ignored character valued 0x%x"
-msgstr "se ignora el resto de la línea; el primer carácter ignorado tiene valor 0x%x"
+msgid "junk at end of line, first unrecognized character valued 0x%x"
+msgstr "basura al final de la línea; el primer carácter ignorado tiene valor 0x%x"
 
-#: read.c:3228
+#: read.c:3347
 msgid "missing expression"
 msgstr "falta una expresión"
 
-#: read.c:3404
+#: read.c:3408
+#, c-format
+msgid "`%s' can't be equated to common symbol '%s'"
+msgstr "`%s' no se puede igualar al símbolo común '%s'"
+
+#: read.c:3536
 msgid "rva without symbol"
 msgstr "rva sin símbolo"
 
-#: read.c:3530
+#: read.c:3658
 msgid "attempt to store value in absolute section"
 msgstr "se intentó almacenar un valor en la sección absoluta"
 
-#: read.c:3568 read.c:4468
+#: read.c:3696 read.c:4544
 msgid "zero assumed for missing expression"
 msgstr "se asume cero para la expresión faltante"
 
-#: read.c:3580 read.c:4480 write.c:322
+#: read.c:3708 read.c:4556 write.c:265
 msgid "register value used as expression"
 msgstr "se usó un valor de registro como una expresión"
 
 #. Leading bits contain both 0s & 1s.
-#: read.c:3671
+#: read.c:3786
 #, c-format
 msgid "value 0x%lx truncated to 0x%lx"
 msgstr "el valor 0x%lx se truncó a 0x%lx"
 
-#: read.c:3687
+#: read.c:3802
 #, c-format
 msgid "bignum truncated to %d bytes"
 msgstr "se truncó el número grande a %d bytes"
 
-#: read.c:3854
+#: read.c:3943
 msgid "using a bit field width of zero"
 msgstr "se usa una anchura de campo de bit de cero"
 
-#: read.c:3862
+#: read.c:3951
 #, c-format
 msgid "field width \"%s\" too complex for a bitfield"
 msgstr "la anchura de campo \"%s\" es demasiado compleja para un campo de bits"
 
-#: read.c:3870
+#: read.c:3959
 #, c-format
 msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
 msgstr "la anchura de campo %lu es demasiado grande para caber en %d bytes: se truncó a %d bits"
 
-#: read.c:3892
+#: read.c:3981
 #, c-format
 msgid "field value \"%s\" too complex for a bitfield"
 msgstr "el valor del campo \"%s\" es demasiado complejo para un campo de bits"
 
-#: read.c:4018 read.c:4212
+#: read.c:4107 read.c:4298
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr "cuenta de repetición sin resolver o no positiva; se utiliza 1"
 
-#: read.c:4069
+#: read.c:4156
 #, c-format
 msgid "unknown floating type type '%c'"
 msgstr "tipo de coma flotante desconocido tipo '%c'"
 
-#: read.c:4091
+#: read.c:4178
 msgid "floating point constant too large"
 msgstr "constante de coma flotante demasiado grande"
 
-#: read.c:4581
+#: read.c:4670
 msgid "strings must be placed into a section"
 msgstr "las cadenas se deben colocar en una sección"
 
-#: read.c:4631
+#: read.c:4720
 msgid "expected <nn>"
 msgstr "se esperaba <nn>"
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4664 read.c:4750
+#: read.c:4753 read.c:4839
 msgid "unterminated string; newline inserted"
 msgstr "cadena sin terminar; se insertó una línea nueva"
 
-#: read.c:4758
+#: read.c:4847
 msgid "bad escaped character in string"
 msgstr "carácter escapado erróneamente en la cadena"
 
-#: read.c:4784
+#: read.c:4872
 msgid "expected address expression"
 msgstr "se esperaba una expresión de dirección"
 
-#: read.c:4804
+#: read.c:4891
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr "el símbolo \"%s\" está indefinido; se asume cero"
 
-#: read.c:4807
+#: read.c:4894
 msgid "some symbol undefined; zero assumed"
 msgstr "algunos símbolos indefinidos; se asume cero"
 
-#: read.c:4824
-msgid "bad or irreducible absolute expression"
-msgstr "expresión absoluta errónea o irreducible"
-
-#: read.c:4867
+#: read.c:4930
 msgid "this string may not contain '\\0'"
 msgstr "esta cadena no puede contener '\\0'"
 
-#: read.c:4904
+#: read.c:4966
 msgid "missing string"
 msgstr "falta una cadena"
 
-#: read.c:5027
+#: read.c:5053
 #, c-format
 msgid ".incbin count zero, ignoring `%s'"
 msgstr "la cuenta .incbin es cero, se ignora `%s'"
 
-#: read.c:5053
+#: read.c:5079
 #, c-format
 msgid "file not found: %s"
 msgstr "no se encontró el fichero: %s"
 
-#: read.c:5067
+#: read.c:5093
 #, c-format
 msgid "seek to end of .incbin file failed `%s'"
 msgstr "falló la búsqueda del final del fichero .incbin `%s'"
 
-#: read.c:5078
+#: read.c:5104
 #, c-format
-msgid "skip (%ld) + count (%ld) larger than file size (%ld)"
-msgstr "salto (%ld) + cuenta (%ld) es más grande que el tamaño del fichero (%ld)"
+msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
+msgstr "salto (%ld) o cuenta (%ld) inválidos para el tamaño del fichero (%ld)"
 
-#: read.c:5085
+#: read.c:5111
 #, c-format
 msgid "could not skip to %ld in file `%s'"
 msgstr "no se puede saltar a %ld en el fichero `%s'"
 
-#: read.c:5094
+#: read.c:5120
 #, c-format
 msgid "truncated file `%s', %ld of %ld bytes read"
 msgstr "el fichero `%s' está truncado, se leyeron %ld de %ld bytes"
 
-#: read.c:5257
+#: read.c:5278
 msgid "missing .func"
 msgstr "falta un .func"
 
-#: read.c:5274
+#: read.c:5295
 msgid ".endfunc missing for previous .func"
 msgstr "falta un .endfunc para el .func previo"
 
-#: stabs.c:220 stabs.c:228 stabs.c:236 stabs.c:255
+#: read.c:5418
+#, c-format
+msgid "missing closing `%c'"
+msgstr "falta un `%c' que cierra"
+
+#: read.c:5420
+msgid "stray `\\'"
+msgstr "`\\' basura"
+
+#: stabs.c:212 stabs.c:220 stabs.c:228 stabs.c:247
 #, c-format
 msgid ".stab%c: missing comma"
 msgstr ".stab%c: falta una coma"
@@ -11563,196 +12391,1095 @@ msgstr ".stab%c: falta una coma"
 #. This could happen for example with a source file with a huge
 #. number of lines.  The only cure is to use a different debug
 #. format, probably DWARF.
-#: stabs.c:248
+#: stabs.c:240
 #, c-format
 msgid ".stab%c: description field '%x' too big, try a different debug format"
 msgstr ".stab%c: la descripción del campo '%x' es demasiado grande, intente un formato de depuración diferente"
 
-#: stabs.c:433
+#: stabs.c:421
 msgid "comma missing in .xstabs"
 msgstr "falta una coma en .xstabs"
 
-#: subsegs.c:377
-#, c-format
-msgid "attempt to switch to nonexistent segment \"%s\""
-msgstr "se intentó cambiar a un segmento \"%s\" que no existe"
-
-#: symbols.c:318
+#: symbols.c:278
 #, c-format
 msgid "cannot define symbol `%s' in absolute section"
 msgstr "no se puede definir el símbolo `%s' en la sección absoluta"
 
-#: symbols.c:452
+#: symbols.c:409
 #, c-format
 msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
 msgstr "el símbolo \"%s\" ya está definido como \"%s\"/%s%ld"
 
-#: symbols.c:529 symbols.c:536
+#: symbols.c:483 symbols.c:490
 #, c-format
 msgid "inserting \"%s\" into symbol table failed: %s"
 msgstr "falló la inserción de \"%s\" en la tabla de símbolos: %s"
 
-#: symbols.c:874 symbols.c:878
+#: symbols.c:864 symbols.c:868
 #, c-format
 msgid "undefined symbol `%s' in operation"
 msgstr "símbolo indefinido `%s' en la operación"
 
-#: symbols.c:885
+#: symbols.c:875
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s'"
 msgstr "secciones inválidas para la operación en `%s' y `%s'"
 
-#: symbols.c:889
+#: symbols.c:879
 #, c-format
 msgid "invalid section for operation on `%s'"
 msgstr "sección inválida para la operación en `%s'"
 
-#: symbols.c:897 symbols.c:900
+#: symbols.c:887 symbols.c:890
 #, c-format
 msgid "undefined symbol `%s' in operation setting `%s'"
 msgstr "símbolo indefinido `%s' en la operación que establece `%s'"
 
-#: symbols.c:907
+#: symbols.c:897
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s' setting `%s'"
 msgstr "secciones inválidas para la operación en `%s' y `%s' que establece `%s'"
 
-#: symbols.c:911
+#: symbols.c:901
 #, c-format
 msgid "invalid section for operation on `%s' setting `%s'"
 msgstr "sección inválida para la operación en `%s' que establece `%s'"
 
-#: symbols.c:964
+#: symbols.c:951
 #, c-format
 msgid "symbol definition loop encountered at `%s'"
 msgstr "se encontró un ciclo de definición de símbolo en %s"
 
-#: symbols.c:1193
+#: symbols.c:1209
 #, c-format
 msgid "division by zero when setting `%s'"
 msgstr "división por cero al establecer `%s'"
 
-#: symbols.c:1280 write.c:2008
+#: symbols.c:1291 write.c:1545
 #, c-format
 msgid "can't resolve value for symbol `%s'"
 msgstr "no se puede resolver el valor para el símbolo `%s'"
 
-#: symbols.c:1674
+#: symbols.c:1738
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr "\"%d\" (número de instancia %d de una etiqueta %s)"
 
-#: symbols.c:1711
+#: symbols.c:1775
 #, c-format
 msgid "attempt to get value of unresolved symbol `%s'"
 msgstr "se intentó obtener el valor del símbolo sin resolver `%s'"
 
-#: symbols.c:1971
+#: symbols.c:2045
 msgid "section symbols are already global"
 msgstr "los símbolos de sección ya son globales"
 
-#: symbols.c:2014
+#: symbols.c:2150
 #, c-format
 msgid "Accessing function `%s' as thread-local object"
 msgstr "Se accesa a la función `%s' como un objeto de hilo local"
 
-#: symbols.c:2018
+#: symbols.c:2154
 #, c-format
 msgid "Accessing `%s' as thread-local object"
 msgstr "Se accesa `%s' como un objeto de hilo local"
 
-#: write.c:215
+#: write.c:164
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr "el campo fx_size es demasiado pequeño para contener %d"
 
-#: write.c:349
-msgid "rva not supported"
-msgstr "rva no tiene soporte"
-
-#: write.c:570
+#: write.c:440
 #, c-format
 msgid "attempt to .org/.space backwards? (%ld)"
 msgstr "¿se intentó hacer .org/.space hacia atrás? (%ld)"
 
-#: write.c:1002 write.c:1074
+#: write.c:691
+#, c-format
+msgid "Local symbol `%s' can't be equated to undefined symbol `%s'"
+msgstr "El símbolo local `%s' no se puede igualar al símbolo sin definir `%s'"
+
+#: write.c:865 write.c:937
 msgid "relocation out of range"
 msgstr "reubicación fuera de rango"
 
-#: write.c:1005 write.c:1077
+#: write.c:868 write.c:940
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr "%s:%u: devolución errónea de bfd_install_relocation: %x"
 
-#: write.c:1057
+#: write.c:920
 msgid "internal error: fixup not contained within frag"
 msgstr "error interno: la compostura no está contenida en un fragmento"
 
-#: write.c:1164 write.c:1188
+#: write.c:1026 write.c:1050
 #, c-format
 msgid "FATAL: Can't write %s"
 msgstr "FATAL: No se puede escribir %s"
 
-#: write.c:1220
+#: write.c:1082
 msgid "cannot write to output file"
 msgstr "no se puede escribir al fichero de salida"
 
-#: write.c:1477
+#: write.c:1223
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file"
 msgstr "%d error%s, %d aviso%s, se genera un fichero objeto erróneo"
 
-#: write.c:1484
+#: write.c:1230
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated"
 msgstr "%d erro%s, %d aviso%s, no se genera un fichero objeto"
 
-#: write.c:1945
+#: write.c:1464
+#, c-format
+msgid "%s: global symbols not supported in common sections"
+msgstr "%s: los símbolos globales no tienen soporte en las secciones comunes"
+
+#: write.c:1478
 #, c-format
 msgid "local label `%s' is not defined"
 msgstr "la etiqueta local `%s' no está definida"
 
-#: write.c:2244
+#: write.c:1498
+#, c-format
+msgid "Local symbol `%s' can't be equated to common symbol `%s'"
+msgstr "El símbolo local `%s' no se puede igualar al símbolo común `%s'"
+
+#: write.c:1768
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr "el relleno de alineación (%lu bytes) no es un múltiplo de %ld"
 
-#: write.c:2361
+#: write.c:1900
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ".word %s-%s+%s no cabe"
 
-#: write.c:2446
+#: write.c:1976
 msgid "attempt to move .org backwards"
 msgstr "se intentó mover .org hacia atrás"
 
-#: write.c:2474
+#: write.c:2004
 msgid ".space specifies non-absolute value"
 msgstr ".space especifica un valor no absoluto"
 
-#: write.c:2481
+#: write.c:2011
 msgid ".space or .fill with negative value, ignored"
 msgstr ".space ó .fill con valor negativo, se ignora"
 
-#: write.c:2773
+#: write.c:2067
+#, c-format
+msgid "Infinite loop encountered whilst attempting to compute the addresses of symbols in section %s"
+msgstr "Se encontró un ciclo infinito al intentar computar las direcciones de los símbolos en la sección %s"
+
+#: write.c:2289
 #, c-format
 msgid "value of %s too large for field of %d bytes at %s"
 msgstr "el valor de %s es demasiado grande para el campo de %d bytes en %s"
 
-#: write.c:2785
+#: write.c:2301
 #, c-format
 msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado grande; %ld en 0x%lx"
 
+#~ msgid "end of file in string; inserted '\"'"
+#~ msgstr "fin de fichero en la cadena; se insertó '\"'"
+
+#~ msgid "GNU assembler version %s (%s)"
+#~ msgstr "GNU ensamblador versión %s (%s)"
+
+#~ msgid "unresolved relocation"
+#~ msgstr "reubicación sin resolver"
+
+#~ msgid "bad relocation: symbol `%s' not in symbol table"
+#~ msgstr "reubicación errónea: el símbolo `%s' no está en la tabla de símbolos"
+
+#~ msgid "%s: bad type for weak symbol"
+#~ msgstr "%s: tipo erróneo para un símbolo débil"
+
+#~ msgid "Local symbol %s never defined."
+#~ msgstr "El símbolo local %s nunca se definió."
+
+#~ msgid "Local symbol %s never defined"
+#~ msgstr "El símbolo local %s nunca se definió"
+
+#~ msgid "bfd_coff_swap_scnhdr_out failed"
+#~ msgstr "falló bfd_coff_swap_scnhdr_out"
+
+#~ msgid "`.bf' symbol without preceding function\n"
+#~ msgstr "símbolo `.bf' sin una función precedente\n"
+
+#~ msgid "Too many new sections; can't add \"%s\""
+#~ msgstr "Demasiadas secciones nuevas; no se puede agregar \"%s\""
+
+#~ msgid "Negative of non-absolute symbol %s"
+#~ msgstr "Negativo de un símbolo %s que no es absoluto"
+
+#~ msgid "callj to difference of 2 symbols"
+#~ msgstr "callj para diferenciar a 2 símbolos"
+
+#~ msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
+#~ msgstr "No se puede emitir la reubicación {- %s-seg símbolo \"%s\"} @ dirección del fichero %ld."
+
+#~ msgid "Value of %ld too large for field of %d bytes at 0x%lx"
+#~ msgstr "El valor de %ld es demasiado grande para el campo de %d bytes en 0x%lx"
+
+#~ msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
+#~ msgstr "Desbordamiento con signo de .word; el interruptor puede ser demasiado grande; %ld en 0x%lx"
+
+#~ msgid "compiler emitted zero-size common symbol `%s' already defined"
+#~ msgstr "el símbolo común de tamaño cero emitido por el compilador `%s' ya está definido"
+
+#~ msgid "compiler redefined zero-size common symbol `%s'"
+#~ msgstr "símbolo común de tamaño cero `%s' redefinido por el compilador"
+
+#~ msgid "Couldn't create VMS object file \"%s\""
+#~ msgstr "No se puede crear el fichero objeto VMS \"%s\""
+
+#~ msgid "I/O error writing VMS object file (length prefix)"
+#~ msgstr "Error de E/S al escribir el fichero objeto VMS (longitud del prefijo)"
+
+#~ msgid "I/O error writing VMS object file"
+#~ msgstr "Error de E/S al escribir el fichero objeto VMS"
+
+#~ msgid "Couldn't find source file \"%s\", status=%%X%x"
+#~ msgstr "No se puede encontrar el fichero fuente \"%s\", estado=%%X%x"
+
+#~ msgid "debugger forward reference error, dbx type %d"
+#~ msgstr "error de referencia hacia adelante del depurador, tipo dbx %d"
+
+#~ msgid "Variable descriptor %d too complicated.  Defined as `void *'."
+#~ msgstr "El descriptor de variable %d es demasiado complicado.  Se define como `void *'."
+
+#~ msgid ""
+#~ "***Warning - the assembly code generated by the compiler has placed \n"
+#~ " global constant(s) in the text psect.  These will not be available to \n"
+#~ " other modules, since this is not the correct way to handle this. You \n"
+#~ " have two options: 1) get a patched compiler that does not put global \n"
+#~ " constants in the text psect, or 2) remove the 'const' keyword from \n"
+#~ " definitions of global variables in your source module(s).  Don't say \n"
+#~ " I didn't warn you! \n"
+#~ msgstr ""
+#~ "***Aviso - el código ensamblador generado por el compilador ha colocado \n"
+#~ " constante(s) global(es) en la psect de texto.  Éstas no estarán disponibles \n"
+#~ " para otros módulos, ya que no es la forma correcta de manejarlo. Tiene \n"
+#~ " dos opciones: 1) obtener un compilador parchado que no coloque constantes \n"
+#~ " globales en la psect de texto, o 2) quitar la palabra clave 'const' de \n"
+#~ " las definiciones de las variables globales en el(los) módulo(s) fuente. \n"
+#~ " ¡No diga que no se le advirtió! \n"
+
+#~ msgid "debugginer output: %d is an unknown untyped variable."
+#~ msgstr "salida del depurador: %d es una variable sin tipo desconocido."
+
+#~ msgid "debugger output: structure element `%s' has undefined type"
+#~ msgstr "salida del depurador: el elmento de la estructura `%s' tiene un tipo indefinido"
+
+#~ msgid "debugger output: %d is an unknown type of variable."
+#~ msgstr "salida del depurador: %d es un tipo desconocido de variable."
+
+#~ msgid "debugger output: Unable to resolve %d circular references."
+#~ msgstr "salida del depurador: No se pueden resolver %d referencias circulares."
+
+#~ msgid "Module name truncated: %s\n"
+#~ msgstr "Nombre de módulo truncado: %s\n"
+
+#~ msgid "Symbol %s replaced by %s\n"
+#~ msgstr "El símbolo %s se reemplazó por %s\n"
+
+#~ msgid "Unknown VMS psect type (%ld)"
+#~ msgstr "Tipo psect VMS desconocido (%ld)"
+
+#~ msgid "Globalsymbol attribute for symbol %s was unexpected."
+#~ msgstr "El atributo de globalsymbol para el símbolo %s era inesperado."
+
+#~ msgid "Invalid data type for globalvalue"
+#~ msgstr "Tipo de dato inválido para globalvalue"
+
+#~ msgid "Invalid globalvalue of %s"
+#~ msgstr "Globalvalue inválido de %s"
+
+#~ msgid "Couldn't find fixup fragment when checking for indirect reference"
+#~ msgstr "No se puede encontrar el fragmento de compostura al revisar por referencias indirectas"
+
+#~ msgid "Fixup data addsy and subsy don't have the same type"
+#~ msgstr "Los datos de compostura addsy y subsy no tienen el mismo tipo"
+
+#~ msgid "Fixup data addsy and subsy don't have an appropriate type"
+#~ msgstr "Los datos de compostura addsy y subsy no tienen un tipo apropiado"
+
+#~ msgid "Fixup data is erroneously \"pcrel\""
+#~ msgstr "Los datos de compostura son \"pcrel\" erróneamente"
+
+#~ msgid "Fixup datum is not a longword"
+#~ msgstr "El dato de compostura no es un longword"
+
+#~ msgid "Fixup datum is not \"fixP->fx_addsy\""
+#~ msgstr "El dato de compostura no es \"fixP->fx_addsy\""
+
+#~ msgid "Can't handle global xtors symbols yet."
+#~ msgstr "No se pueden manejar símbolos xtors globales aún."
+
+#~ msgid "Unknown %s"
+#~ msgstr "%s desconocido"
+
+#~ msgid "unhandled stab type %d"
+#~ msgstr "tipo de cabo %d sin manejar"
+
+#~ msgid "Immediate value of %ld is too large"
+#~ msgstr "El valor inmediato de %ld es demasiado grande"
+
+#~ msgid "need %o3\n"
+#~ msgstr "se necesita %o3\n"
+
+#~ msgid "a29k_convert_frag\n"
+#~ msgstr "a29k_convert_frag\n"
+
+#~ msgid "a29k_estimate_size_before_relax\n"
+#~ msgstr "a29k_estimate_size_before_relax\n"
+
+#~ msgid "Invalid register in & expression"
+#~ msgstr "Registro inválido en la expresión &"
+
+#~ msgid "Intel Wireless MMX technology register expected"
+#~ msgstr "se esperaba un registro de tecnología Intel Inalámbrico MMX"
+
+#~ msgid "unreq: missing hash entry for \"%s\""
+#~ msgstr "unreq: falta la entrada de hash para \"%s\""
+
+#~ msgid ".unreq: unrecognized symbol \"%s\""
+#~ msgstr ".unreq: símbolo \"%s\" no reconocido"
+
+#~ msgid "bad_segment"
+#~ msgstr "segmento_erróneo"
+
+#~ msgid "register expected, not '%.100s'"
+#~ msgstr "se esperaba un registro, no '%.100s'"
+
+#~ msgid "Intel Wireless MMX technology register expected, not '%.100s'"
+#~ msgstr "se esperaba un registro de tecnología Intel Inalámbrica MMX, no '%.100s'"
+
+#~ msgid "illegal co-processor number"
+#~ msgstr "número de co-procesador ilegal"
+
+#~ msgid "bad or missing expression"
+#~ msgstr "expresión errónea o faltante"
+
+#~ msgid "immediate co-processor expression too large"
+#~ msgstr "expresión de co-procesador inmediata demasiado grande"
+
+#~ msgid "co-processor address must be word aligned"
+#~ msgstr "la dirección del co-procesador debe ser alineada con word"
+
+#~ msgid "comma expected after closing square bracket"
+#~ msgstr "se esperaba una coma después del paréntesis cuadrado que cierra"
+
+#~ msgid "pc may not be used in post-increment"
+#~ msgstr "el pc no se puede usar en post-incremento"
+
+#~ msgid "'option' field too large"
+#~ msgstr "campo 'option' demasiado grande"
+
+#~ msgid "non-constant expressions for 'option' field not supported"
+#~ msgstr "no hay soporte para expresiones no constantes para el campo 'option'"
+
+#~ msgid "# or { expected after comma"
+#~ msgstr "se esperaba # o { después de la coma"
+
+#~ msgid "pre-indexed expression expected"
+#~ msgstr "se esperaba una expresión pre-indizada"
+
+#~ msgid "missing ]"
+#~ msgstr "falta un ]"
+
+#~ msgid "Invalid NOP hint"
+#~ msgstr "Pista NOP inválida"
+
+#~ msgid "comma expected after register name"
+#~ msgstr "se esperaba una coma después del nombre de registro"
+
+#~ msgid "comma missing after psr flags"
+#~ msgstr "falta una coma después de las opciones psr"
+
+#~ msgid "only a register or immediate value can follow a psr flag"
+#~ msgstr "sólo un registro o un valor inmediato puede seguir a una opción psr"
+
+#~ msgid "acc0 expected, not '%.100s'"
+#~ msgstr "se esperaba acc0, no '%.100s'"
+
+#~ msgid "address offset too large"
+#~ msgstr "dirección de desplazamiento demasiado grande"
+
+#~ msgid "Warning: instruction unpredictable when using r15"
+#~ msgstr "Aviso: la instrucción es impredecible cuando se utiliza r15"
+
+#~ msgid "Rd equal to Rm or Rn yields unpredictable results"
+#~ msgstr "Rd igual a Rm o Rn produce resultados impredecibles"
+
+#~ msgid "shift requires register or #expression"
+#~ msgstr "el desplazamiento requiere un registro o una #expresión"
+
+#~ msgid "shift requires #expression"
+#~ msgstr "el desplazamiento requiere una #expresión"
+
+#~ msgid "shift of 0 ignored."
+#~ msgstr "se ignora un desplazamiento de 0."
+
+#~ msgid "invalid immediate shift"
+#~ msgstr "desplazamiento inmediato inválido"
+
+#~ msgid "missing endian specifier"
+#~ msgstr "falta el especificador endian"
+
+#~ msgid "rotation can be 8, 16, 24 or 0 when field is ommited"
+#~ msgstr "rotation puede ser 8, 16, 24 o 0 cuando se omite el campo"
+
+#~ msgid "no 'a', 'i', or 'f' flags for 'cps'"
+#~ msgstr "no hay opciones 'a', 'i', o 'f' para 'cps'"
+
+#~ msgid "conditional execution not supported with control register"
+#~ msgstr "la ejecución condicional no tiene soporte con un registro de control"
+
+#~ msgid "pre/post-indexing used when modified address register is destination"
+#~ msgstr "se usó pre/post-indizado cuando el registro de dirección modificado es el destino"
+
+#~ msgid "ldrd destination registers must not overlap index register"
+#~ msgstr "los registros destino ldrd no deben quedar sobre el registro índice"
+
+#~ msgid "invalid floating point immediate expression"
+#~ msgstr "expresión inmediata de coma flotante inválida"
+
+#~ msgid "floating point register or immediate expression expected"
+#~ msgstr "se esperaba un registro de coma flotante o una expresión inmediata"
+
+#~ msgid "address expected"
+#~ msgstr "se esperaba una dirección"
+
+#~ msgid "destination"
+#~ msgstr "destino"
+
+#~ msgid "source"
+#~ msgstr "fuente"
+
+#~ msgid "post-indexed expression expected"
+#~ msgstr "se esperaba una expresión post-indizada"
+
+#~ msgid "r15 not allowed in swap"
+#~ msgstr "no se permite r15 en el intercambio"
+
+#~ msgid "constant value required for number of registers"
+#~ msgstr "se requiere un valor constante para el número de registros"
+
+#~ msgid "subtract valid only on lo regs"
+#~ msgstr "subtract válido sólo en registros lo"
+
+#~ msgid "invalid immediate value for stack adjust"
+#~ msgstr "valor inmediato inválido para el ajuste de la pila"
+
+#~ msgid "invalid immediate for address calculation"
+#~ msgstr "inmediato inválido para el cálculo de dirección"
+
+#~ msgid "invalid immediate for shift"
+#~ msgstr "inmediato inválido para el desplazamiento"
+
+#~ msgid "expected ']'"
+#~ msgstr "se esperaba ']'"
+
+#~ msgid "invalid base register in load/store"
+#~ msgstr "registro base inválido en carga/almacenamiento"
+
+#~ msgid "expecting immediate, 7bit operand"
+#~ msgstr "se espera un operando inmediato de 7 bits"
+
+#~ msgid "offset expected"
+#~ msgstr "se esperaba un desplazamiento"
+
+#~ msgid "Rs and Rd must be different in MUL"
+#~ msgstr "Rs y Rd deben ser diferentes en MUL"
+
+#~ msgid "inserted missing '!': load/store multiple always writes back base register"
+#~ msgstr "se insertó un '!' faltante: los load/store múltiples siempre escribe hacia atrás el registro base"
+
+#~ msgid "only lo-regs valid in load/store multiple"
+#~ msgstr "sólo los registros lo son válidos en carga/almacenamiento múltiple"
+
+#~ msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
+#~ msgstr "sintaxis: ldrs[b] Rd, [Rb, Ro]"
+
+#~ msgid "failed to create an alias for %s, reason: %s"
+#~ msgstr "falló la creación de un alias para %s, razón: %s"
+
+#~ msgid "ignoring redefinition of register alias '%s' to non-existant register '%s'"
+#~ msgstr "se ignora la redefinición del alias de registro '%s' al registro no existente '%s'"
+
+#~ msgid "ignoring incomplete .req pseuso op"
+#~ msgstr "se ignora el pseudo operador incompleto .req"
+
+#~ msgid "GAS can't handle same-section branch dest >= 0x04000000"
+#~ msgstr "GAS no puede manejar un destino de ramificación en la misma sección >= 0x04000000"
+
+#~ msgid "out of range branch"
+#~ msgstr "ramificación fuera de rango"
+
+#~ msgid "branch with link out of range"
+#~ msgstr "ramificación con enlace fuera de rango"
+
+#~ msgid "illegal value for co-processor offset"
+#~ msgstr "valor ilegal para el desplazamiento del co-procesador"
+
+#~ msgid "Illegal value for co-processor offset"
+#~ msgstr "Valor ilegal para el desplazamiento del co-procesador"
+
+#~ msgid "invalid 8bit immediate"
+#~ msgstr "inmediato de 8bit inválido"
+
+#~ msgid "invalid 3bit immediate"
+#~ msgstr "inmediato de 3bit inválido"
+
+#~ msgid "no operator -- statement `%s'\n"
+#~ msgstr "no hay operador -- declaración `%s'\n"
+
+#~ msgid "expected wr or wcgr"
+#~ msgstr "se esperaba wr o wcgr"
+
+#~ msgid "inconsistent register types"
+#~ msgstr "tipos de registro inconsistentes"
+
+#~ msgid "unrecognised register"
+#~ msgstr "registro no reconocido"
+
+#~ msgid "arm convert_frag\n"
+#~ msgstr "convert_frag de arm\n"
+
+#~ msgid "call to tc_crawl_symbol_chain \n"
+#~ msgstr "llamada a tc_crawl_symbol_chain \n"
+
+#~ msgid "call to tc_headers_hook \n"
+#~ msgstr "llamada a tc_headers_hook \n"
+
+#~ msgid ":24 not valid for this opcode"
+#~ msgstr ":24 no es válido para este código de operación"
+
+#~ msgid "expect :8,:16 or :24"
+#~ msgstr "se esperaba :8,:16 ó :24"
+
+#~ msgid "syntax error in reg list"
+#~ msgstr "error sintáctico en la lista de registros"
+
+#~ msgid "missing final register in range"
+#~ msgstr "falta el registro final en el rango"
+
+#~ msgid "expected @(exp, Rn)"
+#~ msgstr "se esperaba @(exp, Rn)"
+
+#~ msgid "@Rn+ needs word register"
+#~ msgstr "@Rn+ necesita un registro word"
+
+#~ msgid "@Rn needs word register"
+#~ msgstr "@Rn necesita un registro word"
+
+#~ msgid "operand must be absolute in range %d..%d"
+#~ msgstr "el operando debe ser absoluto en el rango %d..%d"
+
+#~ msgid "leafproc symbol '%s' undefined"
+#~ msgstr "símolo de proceso hoja '%s' indefinido"
+
+#~ msgid "Warning: making leafproc entries %s and %s both global\n"
+#~ msgstr "Aviso: haciendo globales las entradas de proceso hoja %s y %s\n"
+
+#~ msgid "Unknown PC relative instruction"
+#~ msgstr "Instrucción relativa al PC desconocida"
+
+#~ msgid "Can't hash instruction '%s':%s"
+#~ msgstr "No se puede dispersar la instrucción '%s':%s"
+
+#~ msgid "Invalid mnemonic '%s'"
+#~ msgstr "Mnemónico inválido '%s'"
+
+#~ msgid "Parameter syntax error"
+#~ msgstr "Error sintáctico de parámetros"
+
+#~ msgid "Use of obsolete instruction"
+#~ msgstr "Uso de una instrucción obsoleta"
+
+#~ msgid "Expression truncated to 16 bits"
+#~ msgstr "Expresión truncada a 16 bits"
+
+#~ msgid "Expression truncated to 5 bits"
+#~ msgstr "Expresión truncada a 5 bits"
+
+#~ msgid "Expression truncated to 9 bits"
+#~ msgstr "Expresión truncada a 9 bits"
+
+#~ msgid "Removed lower 2 bits of expression"
+#~ msgstr "Se borraron los 2 bits inferiores de la expresión"
+
+#~ msgid "Relaxation should never occur"
+#~ msgstr "La relajación nunca debe ocurrir"
+
+#~ msgid "m88k convert_frag\n"
+#~ msgstr "m88k convert_frag\n"
+
+#~ msgid "constant too large"
+#~ msgstr "constante demasiado grande"
+
+#~ msgid "register out of range"
+#~ msgstr "registro fuera de rango"
+
+#~ msgid "The -a option doesn't exist. (Despite what the man page says!"
+#~ msgstr "La opción -a no existe. (¡A pesar de lo que diga la página del manual!)"
+
+#~ msgid ""
+#~ "Tahoe options:\n"
+#~ "-a\t\t\tignored\n"
+#~ "-d LENGTH\t\tignored\n"
+#~ "-J\t\t\tignored\n"
+#~ "-S\t\t\tignored\n"
+#~ "-t FILE\t\t\tignored\n"
+#~ "-T\t\t\tignored\n"
+#~ "-V\t\t\tignored\n"
+#~ msgstr ""
+#~ "Opciones de Tahoe:\n"
+#~ "-a\t\t\tse ignora\n"
+#~ "-d LENGTH\t\tse ignora\n"
+#~ "-J\t\t\tse ignora\n"
+#~ "-S\t\t\tse ignora\n"
+#~ "-t FILE\t\t\tse ignora\n"
+#~ "-T\t\t\tse ignora\n"
+#~ "-V\t\t\tse ignora\n"
+
+#~ msgid "Casting a branch displacement is bad form, and is ignored."
+#~ msgstr "La conversión de una desubicación de ramificación es una forma errónea, y se ignora."
+
+#~ msgid "Couldn't parse the [index] in this operand."
+#~ msgstr "No se puede decodificar el [index] en este operando."
+
+#~ msgid "Couldn't find the opening '[' for the index of this operand."
+#~ msgstr "No se puede encontrar el '[' que abre para el índice de este operando."
+
+#~ msgid "Couldn't find the opening '(' for the deref of this operand."
+#~ msgstr "No se puede encontrar el '(' que abre para la dereferencia de este operando."
+
+#~ msgid "Operand can't be both pre-inc and post-dec."
+#~ msgstr "El operando no puede ser pre-incremento y post-decremento al mismo tiempo."
+
+#~ msgid "I parsed 2 registers in this operand."
+#~ msgstr "Se decodificaron 2 registros en este operando."
+
+#~ msgid "Can't relocate expression error."
+#~ msgstr "No se puede reubicar la expresión de error."
+
+#~ msgid "Expression is too large for a 32 bits."
+#~ msgstr "La expresión es demasiado grande para 32 bits."
+
+#~ msgid "Junk at end of expression."
+#~ msgstr "Basura al final de la expresión."
+
+#~ msgid "Syntax error in direct register mode."
+#~ msgstr "Error sintáctico en el modo directo de registro."
+
+#~ msgid "You can't index a register in direct register mode."
+#~ msgstr "No se puede indizar un registro en el modo directo de registro."
+
+#~ msgid "SP can't be the source operand with direct register addressing."
+#~ msgstr "SP no puede ser el operando fuente con direccionamiento directo de registro."
+
+#~ msgid "Can't take the address of a register."
+#~ msgstr "No se puede tomar la dirección de un registro."
+
+#~ msgid "Direct Register can't be used in a branch."
+#~ msgstr "Un Registro Directo no se puede utilizar en una ramificación."
+
+#~ msgid "For quad access, the register must be even and < 14."
+#~ msgstr "Para acceso cuadrático, el registro debe ser par y < 14."
+
+#~ msgid "You can't cast a direct register."
+#~ msgstr "No se puede convertir un registro directo."
+
+# `tromp' se utiliza aquí como verbo transitivo. cfuga
+# Referencia: http://www.dictionary.com/search?q=tromp
+#~ msgid "Using reg 14 for quadwords can tromp the FP register."
+#~ msgstr "El uso del registro 14 para quadwords puede noquear el registro FP."
+
+#~ msgid "Syntax error in auto-dec mode."
+#~ msgstr "Error sintáctico en el modo auto-dec."
+
+#~ msgid "You can't have an index auto dec mode."
+#~ msgstr "No se puede tener un índice en modo auto dec"
+
+#~ msgid "Auto dec mode cant be used for reading."
+#~ msgstr "El modo auto dec no se puede usar para lectura."
+
+#~ msgid "Auto dec only works of the SP register."
+#~ msgstr "El modo auto dec solamente funciona en los registros SP."
+
+#~ msgid "Auto dec can't be used in a branch."
+#~ msgstr "No se puede utilizar auto dec en una ramificación."
+
+#~ msgid "Auto dec won't work with quadwords."
+#~ msgstr "Auto dec no funciona con quadwords."
+
+#~ msgid "Syntax error in one of the auto-inc modes."
+#~ msgstr "Error sintáctico en uno de los modos auto-inc."
+
+#~ msgid "Auto inc deferred only works of the SP register."
+#~ msgstr "El modo auto inc diferido solamente funciona en los registros SP."
+
+#~ msgid "You can't have an index auto inc deferred mode."
+#~ msgstr "No se puede tener un índice en modo auto inc diferido"
+
+#~ msgid "Auto inc can't be used in a branch."
+#~ msgstr "No se puede utilizar auto inc en una ramificación."
+
+#~ msgid "You can't write to an auto inc register."
+#~ msgstr "No se puede escribir en un registro auto inc."
+
+#~ msgid "Auto inc only works of the SP register."
+#~ msgstr "El modo auto inc funciona solamente en los registros SP."
+
+#~ msgid "Auto inc won't work with quadwords."
+#~ msgstr "Auto inc no funciona con quadwords."
+
+#~ msgid "You can't have an index in auto inc mode."
+#~ msgstr "No se puede tener un índice en el modo auto inc."
+
+#~ msgid "You can't index the sp register."
+#~ msgstr "No se puede indizar el registro sp."
+
+#~ msgid "Syntax error in register displaced mode."
+#~ msgstr "Error sintáctico en el registro en modo desubicado."
+
+#~ msgid "An offest is needed for this operand."
+#~ msgstr "Se necesita un desplazamiento para este operando."
+
+#~ msgid "You can't index a register in immediate mode."
+#~ msgstr "No se puede indizar un registro en modo inmediato."
+
+#~ msgid "Immediate access can't be used as an address."
+#~ msgstr "No se puede utilizar el acceso inmediato como una dirección"
+
+#~ msgid "Compiler bug: ODD number of bytes in arg structure %s."
+#~ msgstr "Bicho del compilador: número de bytes IMPAR en la estructura de argumentos %s."
+
+#~ msgid "Compliler bug: Got a case (%d) I wasn't expecting."
+#~ msgstr "Bicho del compilador: Se obtuvo un case (%d) que no se esperaba."
+
+#~ msgid "Real branch displacements must be expressions."
+#~ msgstr "Las desubicaciones de ramificaciones reales deben ser expresiones."
+
+#~ msgid "Complier error: I got an unknown synthetic branch :%c"
+#~ msgstr "Error del compilador: Se obtuvo una ramificación sintética desconocida :%c"
+
+# En México se utilizaría `guácala' por `barf', como una expresión
+# que simboliza vómito, pero no es comprensible para todos los
+# hispanoparlantes. :-)    cfuga
+#~ msgid "Barf, bad mode %x\n"
+#~ msgstr "Ugh, modo erróneo %x\n"
+
+#~ msgid "internal error:%s:%d: %s\n"
+#~ msgstr "error interno:%s:%d: %s\n"
+
+#~ msgid "internal error:%s:%d: %s %ld\n"
+#~ msgstr "error interno:%s:%d: %s %ld\n"
+
+#~ msgid "Relaxation is a luxury we can't afford"
+#~ msgstr "La relajación es un lujo que no se puede conceder"
+
+#~ msgid "bad call to md_atof ()"
+#~ msgstr "llamada errónea a md_atof ()"
+
+#~ msgid "':' not followed by 'm' or 's'"
+#~ msgstr "':' no está seguido por 'm' o 's'"
+
+#~ msgid "paren nesting"
+#~ msgstr "anidamiento de paréntesis"
+
+#~ msgid "mismatched parenthesis"
+#~ msgstr "paréntesis sin coincidencia"
+
+#~ msgid "unhandled expression type"
+#~ msgstr "tipo de expresión sin manejar"
+
+#~ msgid "symbol reloc that is not PC relative or 32 bits"
+#~ msgstr "reubicación de símbolo que no es relativo al PC o de 32 bits"
+
+#~ msgid "unhandled operand modifier"
+#~ msgstr "modificador de operando sin manejar"
+
+#~ msgid "unhandled expression"
+#~ msgstr "expresión sin manejar"
+
+#~ msgid "Invalid mnemonic: '%s'"
+#~ msgstr "Mnemónico inválido: '%s'"
+
+#~ msgid "Invalid operands: '%s'"
+#~ msgstr "Operandos inválidos: '%s'"
+
+#~ msgid "unhandled predefined symbol bits"
+#~ msgstr "bits de símbolo predefinido sin manejar"
+
+#~ msgid "PC offset 0x%lx outside range 0x%lx-0x%lx"
+#~ msgstr "desplazamiento del PC 0x%lx fuera del rango 0x%lx-0x%lx"
+
+#~ msgid "unhandled relocation type in fixup"
+#~ msgstr "typo de reubicación sin manejar en la compostura"
+
+#~ msgid "md_convert_frag() not implemented yet"
+#~ msgstr "md_convert_frag() aún no está implementado"
+
+#~ msgid "need on or off."
+#~ msgstr "necesita on u off."
+
+#~ msgid "syntax error after <exp"
+#~ msgstr "error sintáctico después de <exp"
+
+#~ msgid "value of %ld too large"
+#~ msgstr "el valor de %ld es demasiado grande"
+
+#~ msgid "emitting simplification relocation"
+#~ msgstr "emitiendo simplificación de reubicación"
+
+#~ msgid "emitting unknown relocation"
+#~ msgstr "emitiendo reubicación desconocida"
+
+#~ msgid "Can't subtract symbols in different sections %s %s"
+#~ msgstr "No se pueden sustraer los símbolos en secciones diferentes %s %s"
+
+#~ msgid "dwarf2 is not supported for this object file format"
+#~ msgstr "dwarf2 no tiene soporte para este formato de fichero objeto"
+
+#~ msgid "Macro with this name was already defined"
+#~ msgstr "Ya estaba definida una macro con ese nombre"
+
+#~ msgid "missplaced )"
+#~ msgstr ") mal colocado"
+
+#~ msgid "macro formal argument does not exist"
+#~ msgstr "el argumento formal de macro no existe"
+
+#~ msgid "FATAL: can't close %s"
+#~ msgstr "FATAL: no se puede cerrar %s"
+
+#~ msgid "Failed to emit an object byte"
+#~ msgstr "Falló al emitir un byte objeto"
+
+#~ msgid "can't continue"
+#~ msgstr "no se puede continuar"
+
+#~ msgid "attempt to switch to nonexistent segment \"%s\""
+#~ msgstr "se intentó cambiar a un segmento \"%s\" que no existe"
+
+#~ msgid "Can't close %s: %s"
+#~ msgstr "No se puede cerrar %s: %s"
+
+#~ msgid "Missing size expression"
+#~ msgstr "Falta una expresión de tamaño"
+
+#~ msgid "lcomm length (%d.) <0! Ignored."
+#~ msgstr "¡longitud de lcomm (%d.) <0! Ignorada."
+
+#~ msgid "Symbol %s already defined"
+#~ msgstr "El símbolo %s ya está definido"
+
+#~ msgid "expected comma after symbol-name"
+#~ msgstr "se esperaba una coma después del nombre del símbolo"
+
+#~ msgid "length of .comm \"%s\" is already %ld; not changed to %ld"
+#~ msgstr "la longitud de .comm \"%s\" ya es %ld; no se cambia a %ld"
+
+#~ msgid "common alignment negative; 0 assumed"
+#~ msgstr "alineación común negativa; se asume 0"
+
+#~ msgid "common alignment not a power of 2"
+#~ msgstr "la alineación común no es una potencia de 2"
+
+#~ msgid "ignoring new section group for %s"
+#~ msgstr "se ignora un grupo de sección nuevo para %s"
+
+#~ msgid ""
+#~ "g++ wrote an extern reference to `%s' as a routine.\n"
+#~ "I will fix it, but I hope that it was note really a routine."
+#~ msgstr ""
+#~ "g++ escribió una referencia externa a `%s' como una rutina.\n"
+#~ "Se compondrá, pero se espera que no sea realmente una rutina."
+
+#~ msgid "File overrides no-base-register option."
+#~ msgstr "El fichero se impone a la opción no-base-register."
+
+#~ msgid "immediate value cannot be used to set this field"
+#~ msgstr "no se puede usar un valor inmediato para establecer este campo"
+
+#~ msgid "use old ABI (ELF only)"
+#~ msgstr "usa la ABI antigua (solamente ELF)"
+
+#~ msgid "expression possibly out of 8-bit range"
+#~ msgstr "expresión posiblemente fuera del rango de 8-bit"
+
+#~ msgid "Invalid register list for ldm/stm)\n"
+#~ msgstr "Lista de registros inválida para ldm/stm)\n"
+
+#~ msgid "unimplemented segment type %d in operand"
+#~ msgstr "tipo de segmento %d sin implementar en el operando"
+
+#~ msgid "Additional NOP may be necessary to workaround Itanium processor A/B step errata"
+#~ msgstr "Pueden ser necesario un NOP adicional para evitar el error de paso A/B del procesador Itanium"
+
+#~ msgid "  -relax                 create linker relaxable code\n"
+#~ msgstr "  -relax                 crea código relajable para el enlazados\n"
+
+#~ msgid "  -cpu-desc              provide runtime cpu description file\n"
+#~ msgstr "  -cpu-desc              provee el fichero de descripción del cpu en tiempo de ejecución\n"
+
+#~ msgid "Branch %s is always false (nop)"
+#~ msgstr "La ramificación %s es siempre falsa (nop)"
+
+#~ msgid "Branch likely %s is always false"
+#~ msgstr "La ramificación como %s es siempre falsa"
+
+#~ msgid "load/store address overflow (max 32 bits)"
+#~ msgstr "desbordamiento de dirección load/store (máx 32 bits)"
+
+#~ msgid "-G may not be used with embedded PIC code"
+#~ msgstr "-G no se puede utilizar con código PIC imbuído"
+
+#~ msgid "-G is not supported for this configuration"
+#~ msgstr "-G no tiene soporte para esta configuración"
+
+#~ msgid "-G may not be used with SVR4 or embedded PIC code"
+#~ msgstr "-G no se puede utilizar con código PIC de SVR4 o imbuído"
+
+#~ msgid "Unmatched %%hi reloc"
+#~ msgstr "Reubicación %%hi sin coincidencia"
+
+#~ msgid "Invalid PC relative reloc"
+#~ msgstr "Reubicación relativa al PC inválida"
+
+#~ msgid "%08lx  UNDEFINED\n"
+#~ msgstr "%08lx  SIN DEFINIR\n"
+
+#~ msgid "No read only data section in this object file format"
+#~ msgstr "No hay sección de datos de sólo lectura en este formato de fichero objeto"
+
+#~ msgid "Global pointers not supported; recompile -G 0"
+#~ msgstr "Los punteros globales no tienen soporte; recompile -G 0"
+
+#~ msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
+#~ msgstr "se utilizó AT después de \".set noat\" o se utilizó una macro después de \".set nomacro\""
+
+#~ msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
+#~ msgstr "Revise dos veces fx_r_type en tc-mips.c:tc_gen_reloc"
+
+#~ msgid "operand out of range (%s not between %ld and %ld)"
+#~ msgstr "operando fuera de rango (%s no está entre %ld y %ld)"
+
+#~ msgid "the linker will not handle this relocation correctly (1)"
+#~ msgstr "el enlazador no manejará correctamente esta reubicación (1)"
+
+#~ msgid "-mcoff-version={0|1|2}    Select COFF version\n"
+#~ msgstr "-mcoff-version={0|1|2}    Selecciona la versión de COFF\n"
+
+#~ msgid "unknown command line option: -%c%s\n"
+#~ msgstr "opción de línea de comandos desconocida: -%c%s\n"
+
+#~ msgid "'--literal-section-name' is deprecated; use '--rename-section .literal=NEWNAME'"
+#~ msgstr "'--literal-section-name' es obsoleto; utilice '--rename-section .literal=NOMBRENUEVO'"
+
+#~ msgid "'--text-section-name' is deprecated; use '--rename-section .text=NEWNAME'"
+#~ msgstr "'--text-section-name' es obsoleto; utilice '--rename-section .text=NOMBRENUEVO'"
+
+#~ msgid "'--data-section-name' is deprecated; use '--rename-section .data=NEWNAME'"
+#~ msgstr "'--data-section-name' es obsoleto; utilice '--rename-section .data=NOMBRENUEVO'"
+
+#~ msgid "'--bss-section-name' is deprecated; use '--rename-section .bss=NEWNAME'"
+#~ msgstr "'--bss-section-name' es obsoleto; utilice '--rename-section .bss=NOMBRENUEVO'"
+
+#~ msgid "register number for `%s' is not a constant"
+#~ msgstr "el número de registro para `%s' no es una constante"
+
+#~ msgid "operand %d not properly aligned for '%s'"
+#~ msgstr "el operando %d no está alineado adecuadamente '%s'"
+
+#~ msgid "operand %d not in immediate table for '%s'"
+#~ msgstr "el operando %d no está en la tabla de inmediatos para '%s'"
+
+#~ msgid "operand %d too small for '%s'"
+#~ msgstr "el operando %d es demasiado pequeño para '%s'"
+
+#~ msgid "instruction fragment may contain data"
+#~ msgstr "el fragmento de instrucción puede contener datos"
+
+#~ msgid "invalid relocation operand %i on '%s'"
+#~ msgstr "operando de reubicación %i inválido en '%s'"
+
+#~ msgid "instruction with constant operands does not fit without widening"
+#~ msgstr "la instrucción con operandos constantes no cabe sin ensanchar"
+
+#~ msgid "instruction's constant operands do not fit"
+#~ msgstr "los operandos constantes de la instrucción no caben"
+
+#~ msgid "opcode 'OR' unavailable in this configuration"
+#~ msgstr "el código de operación 'OR' no está disponible en esta configuración"
+
+#~ msgid "invalid %d-byte NOP requested"
+#~ msgstr "se requirió un NOP de %d-byte inválido"
+
+#~ msgid "get_expanded_loop_offset: undefined opcode"
+#~ msgstr "get_expanded_loop_offset: código de operación indefinido"
+
+#~ msgid "undefined @ suffix '%s', expected '%s'"
+#~ msgstr "sufijo @ '%s' indefinido, se esperaba '%s'"
+
+#~ msgid "invalid operand relocation for '%s' instruction"
+#~ msgstr "operando de reubicación inválido para la instrucción '%s'"
+
+#~ msgid "invalid relocation for operand %d in '%s' instruction"
+#~ msgstr "reubicación inválida para el operando %d en la instrucción '%s'"
+
+#~ msgid "non-PCREL relocation operand %d for '%s': %s"
+#~ msgstr "operando de reubicación %d que no es PCREL para '%s': %s"
+
+#~ msgid "get_text_align_power: argument too large"
+#~ msgstr "get_text_align_power: argumento demasiado grande"
+
+#~ msgid "invalid opcode for RELAX_ALIGN_NEXT_OPCODE"
+#~ msgstr "código de operación inválido para RELAX_ALIGN_NEXT_OPCODE"
+
+#~ msgid "cannot continue"
+#~ msgstr "no se puede continuar"
+
+#~ msgid "expected loop opcode in relax align next target"
+#~ msgstr "se esperaba un código de operación de ciclo en el objetivo de relajación de alineación del siguiente"
+
+#~ msgid "expected align_code or RELAX_ALIGN_NEXT_OPCODE"
+#~ msgstr "se esperaba align_code o RELAX_ALIGN_NEXT_OPCODE"
+
+#~ msgid "internal error aligning"
+#~ msgstr "error interno al alinear"
+
+#~ msgid "loop relaxation specification does not correspond"
+#~ msgstr "la especificación de relajación del ciclo no corresponde"
+
+#~ msgid "inlining literal pool; specify location with .literal_position."
+#~ msgstr "conjunto de literales inlining; especificar la ubicación con .literal_position."
+
+#~ msgid "operand %s0x%x out of range"
+#~ msgstr "el operando %s0x%x está fuera de rango"
+
+#~ msgid "BSS length (%d) < 0 ignored"
+#~ msgstr "se ignora la longitud BSS (%d) <0"
+
+#~ msgid "alignment too large; %d assumed"
+#~ msgstr "alineación demasiado grande; se asume %d"
+
+#~ msgid ".endr encountered without preceeding .rept, .irc, or .irp"
+#~ msgstr "se encontró una directiva .endr sin una directiva .rept, .irc, ó .irp precedente"
+
 #~ msgid "subsegment index too high"
 #~ msgstr "índice de subsegmento demasiado alto"
 
 #~ msgid ".COMMon length (%d.) <0! Ignored."
 #~ msgstr "¡longitud de .COMM (%d.) <0! Ignorada."
 
-#~ msgid "operand out of range: %d"
-#~ msgstr "operando fuera de rango: %d"
-
 #~ msgid "expect :8 or :16 here"
 #~ msgstr "se esperaba :8 ó :16 aquí"
 
@@ -11762,9 +13489,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "i860_number_to_field\n"
 #~ msgstr "i860_number_to_field\n"
 
-#~ msgid "callj to difference of two symbols"
-#~ msgstr "callj para diferenciar dos símbolos"
-
 #~ msgid "md_number_to_disp not defined"
 #~ msgstr "md_number_to_disp no está definido"
 
@@ -11789,9 +13513,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "invalid architecture -mtune=%s"
 #~ msgstr "arquitectura -mtune=%s inválida"
 
-#~ msgid "invalid architecture -march=%s"
-#~ msgstr "arquitectura -march=%s inválida"
-
 #~ msgid "invalid architecture -mcpu=%s"
 #~ msgstr "arquitectura -mcpu=%s inválida"
 
@@ -11873,9 +13594,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "End of file not at start of line.\n"
 #~ msgstr "El final del fichero no está el inicio de la línea.\n"
 
-#~ msgid "Illegal base character %c.\n"
-#~ msgstr "Carácter base %c ilegal.\n"
-
 #~ msgid "radix is %c must be one of b, q, d or h"
 #~ msgstr "el radical es %c debe ser uno de b, q, d ó h"
 
@@ -11976,9 +13694,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "AENDW without a AENDW.\n"
 #~ msgstr "AWHILE sin un AENDW.\n"
 
-#~ msgid "AREPEAT must have absolute operand.\n"
-#~ msgstr "AREPEAT debe tener un operando absoluto.\n"
-
 #~ msgid "AREPEAT without a AENDR at %d.\n"
 #~ msgstr "AREPEAT sin un AENDR en %d.\n"
 
@@ -12165,9 +13880,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "Unrecognized section type"
 #~ msgstr "Tipo de sección no reconocido"
 
-#~ msgid "Missing section name"
-#~ msgstr "Falta el nombre de sección"
-
 #~ msgid "Cannot use !%s!%d with %s"
 #~ msgstr "No se puede usar !%s!%d con %s"
 
@@ -12225,9 +13937,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "Bad COFF debugging info"
 #~ msgstr "Información de depuración COFF errónea"
 
-#~ msgid "Ignoring attempt to redefine symbol `%s'."
-#~ msgstr "Se ignora el intento de redefinir el símbolo `%s'."
-
 #~ msgid "Missing '%c' assumed"
 #~ msgstr "Se asume que falta '%c'"
 
@@ -12240,9 +13949,6 @@ msgstr "desbordamiento con signo de .word; el interruptor puede ser demasiado gr
 #~ msgid "Alignment not a power of 2"
 #~ msgstr "La alineación no es una potencia de 2"
 
-#~ msgid "attempt to re-define symbol `%s'"
-#~ msgstr "se intentó re-definir el símbolo `%s'"
-
 #~ msgid "Missing alignment"
 #~ msgstr "Falta la alineación"
 
diff --git a/gas/po/gas.pot b/gas/po/gas.pot
index ae3cbabd833d..122a678aa4a0 100644
--- a/gas/po/gas.pot
+++ b/gas/po/gas.pot
@@ -1,12 +1,14 @@
 # SOME DESCRIPTIVE TITLE.
-# Copyright (C) YEAR Free Software Foundation, Inc.
+# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER
+# This file is distributed under the same license as the PACKAGE package.
 # FIRST AUTHOR <EMAIL@ADDRESS>, YEAR.
 #
 #, fuzzy
 msgid ""
 msgstr ""
 "Project-Id-Version: PACKAGE VERSION\n"
-"POT-Creation-Date: 2003-07-17 14:56+0100\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2005-10-25 08:41+0930\n"
 "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
 "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
 "Language-Team: LANGUAGE <LL@li.org>\n"
@@ -14,72 +16,65 @@ msgstr ""
 "Content-Type: text/plain; charset=CHARSET\n"
 "Content-Transfer-Encoding: 8bit\n"
 
-#: app.c:474 app.c:488
+#: app.c:470 app.c:484
 msgid "end of file in comment"
 msgstr ""
 
-#: app.c:567
-msgid "end of file in string; inserted '\"'"
-msgstr ""
-
-#: app.c:612
-msgid "end of file in string; '\"' inserted"
+#: app.c:560 app.c:605
+#, c-format
+msgid "end of file in string; '%c' inserted"
 msgstr ""
 
-#: app.c:638
+#: app.c:631
 #, c-format
 msgid "unknown escape '\\%c' in string; ignored"
 msgstr ""
 
-#: app.c:790
+#: app.c:786
 msgid "end of file not at end of a line; newline inserted"
 msgstr ""
 
-#: app.c:949
+#: app.c:945
 msgid "end of file in multiline comment"
 msgstr ""
 
-#: app.c:1013
+#: app.c:1010
 msgid "end of file after a one-character quote; \\0 inserted"
 msgstr ""
 
-#: app.c:1021
+#: app.c:1018
 msgid "end of file in escape character"
 msgstr ""
 
-#: app.c:1033
+#: app.c:1030
 msgid "missing close quote; (assumed)"
 msgstr ""
 
-#: app.c:1101 app.c:1155 app.c:1166 app.c:1231
+#: app.c:1098 app.c:1152 app.c:1163 app.c:1228
 msgid "end of file in comment; newline inserted"
 msgstr ""
 
-#: as.c:160
+#: as.c:161
 msgid "missing emulation mode name"
 msgstr ""
 
-#: as.c:175
+#: as.c:176
 #, c-format
 msgid "unrecognized emulation name `%s'"
 msgstr ""
 
-#: as.c:222
-#, c-format
-msgid "GNU assembler version %s (%s) using BFD version %s"
-msgstr ""
-
-#: as.c:225
+#: as.c:223
 #, c-format
-msgid "GNU assembler version %s (%s)"
+msgid "GNU assembler version %s (%s) using BFD version %s\n"
 msgstr ""
 
-#: as.c:234
+#: as.c:230
 #, c-format
 msgid "Usage: %s [option...] [asmfile...]\n"
 msgstr ""
 
-#: as.c:236
+#: as.c:232
+#, c-format
 msgid ""
 "Options:\n"
 "  -a[sub-option...]\t  turn on listings\n"
@@ -94,148 +89,208 @@ msgid ""
 "                      \t  =FILE  list to FILE (must be last sub-option)\n"
 msgstr ""
 
-#: as.c:249
+#: as.c:245
+#, c-format
+msgid "  --alternate             initially turn on alternate macro syntax\n"
+msgstr ""
+
+#: as.c:247
+#, c-format
 msgid "  -D                      produce assembler debugging messages\n"
 msgstr ""
 
-#: as.c:251
+#: as.c:249
+#, c-format
 msgid "  --defsym SYM=VAL        define symbol SYM to given value\n"
 msgstr ""
 
-#: as.c:267
+#: as.c:265
 #, c-format
 msgid "                          emulate output (default %s)\n"
 msgstr ""
 
-#: as.c:272
+#: as.c:270
+#, c-format
 msgid "  --execstack             require executable stack for this object\n"
 msgstr ""
 
-#: as.c:274
+#: as.c:272
+#, c-format
 msgid ""
 "  --noexecstack           don't require executable stack for this object\n"
 msgstr ""
 
-#: as.c:277
+#: as.c:275
+#, c-format
 msgid "  -f                      skip whitespace and comment preprocessing\n"
 msgstr ""
 
+#: as.c:277
+#, c-format
+msgid "  -g --gen-debug          generate debugging information\n"
+msgstr ""
+
 #: as.c:279
-msgid "  --gstabs                generate stabs debugging information\n"
+#, c-format
+msgid "  --gstabs                generate STABS debugging information\n"
 msgstr ""
 
 #: as.c:281
-msgid "  --gdwarf2               generate DWARF2 debugging information\n"
+#, c-format
+msgid ""
+"  --gstabs+               generate STABS debug info with GNU extensions\n"
 msgstr ""
 
 #: as.c:283
-msgid "  --help                  show this message and exit\n"
+#, c-format
+msgid "  --gdwarf-2              generate DWARF2 debugging information\n"
 msgstr ""
 
 #: as.c:285
-msgid "  --target-help           show target specific options\n"
+#, c-format
+msgid "  --hash-size=<value>     set the hash table size close to <value>\n"
 msgstr ""
 
 #: as.c:287
+#, c-format
+msgid "  --help                  show this message and exit\n"
+msgstr ""
+
+#: as.c:289
+#, c-format
+msgid "  --target-help           show target specific options\n"
+msgstr ""
+
+#: as.c:291
+#, c-format
 msgid ""
 "  -I DIR                  add DIR to search list for .include directives\n"
 msgstr ""
 
-#: as.c:289
+#: as.c:293
+#, c-format
 msgid "  -J                      don't warn about signed overflow\n"
 msgstr ""
 
-#: as.c:291
+#: as.c:295
+#, c-format
 msgid ""
 "  -K                      warn when differences altered for long "
 "displacements\n"
 msgstr ""
 
-#: as.c:293
+#: as.c:297
+#, c-format
 msgid "  -L,--keep-locals        keep local symbols (e.g. starting with `L')\n"
 msgstr ""
 
-#: as.c:295
+#: as.c:299
+#, c-format
 msgid "  -M,--mri                assemble in MRI compatibility mode\n"
 msgstr ""
 
-#: as.c:297
+#: as.c:301
+#, c-format
 msgid ""
 "  --MD FILE               write dependency information in FILE (default "
 "none)\n"
 msgstr ""
 
-#: as.c:299
+#: as.c:303
+#, c-format
 msgid "  -nocpp                  ignored\n"
 msgstr ""
 
-#: as.c:301
+#: as.c:305
+#, c-format
 msgid ""
 "  -o OBJFILE              name the object-file output OBJFILE (default a."
 "out)\n"
 msgstr ""
 
-#: as.c:303
+#: as.c:307
+#, c-format
 msgid "  -R                      fold data section into text section\n"
 msgstr ""
 
-#: as.c:305
+#: as.c:309
+#, c-format
+msgid ""
+"  --reduce-memory-overheads \n"
+"                          prefer smaller memory use at the cost of longer\n"
+"                          assembly times\n"
+msgstr ""
+
+#: as.c:313
+#, c-format
 msgid ""
 "  --statistics            print various measured statistics from execution\n"
 msgstr ""
 
-#: as.c:307
+#: as.c:315
+#, c-format
 msgid "  --strip-local-absolute  strip local absolute symbols\n"
 msgstr ""
 
-#: as.c:309
+#: as.c:317
+#, c-format
 msgid ""
 "  --traditional-format    Use same format as native assembler when possible\n"
 msgstr ""
 
-#: as.c:311
+#: as.c:319
+#, c-format
 msgid "  --version               print assembler version number and exit\n"
 msgstr ""
 
-#: as.c:313
+#: as.c:321
+#, c-format
 msgid "  -W  --no-warn           suppress warnings\n"
 msgstr ""
 
-#: as.c:315
+#: as.c:323
+#, c-format
 msgid "  --warn                  don't suppress warnings\n"
 msgstr ""
 
-#: as.c:317
+#: as.c:325
+#, c-format
 msgid "  --fatal-warnings        treat warnings as errors\n"
 msgstr ""
 
-#: as.c:319
+#: as.c:327
+#, c-format
 msgid ""
 "  --itbl INSTTBL          extend instruction set to include instructions\n"
 "                          matching the specifications defined in file "
 "INSTTBL\n"
 msgstr ""
 
-#: as.c:322
+#: as.c:330
+#, c-format
 msgid "  -w                      ignored\n"
 msgstr ""
 
-#: as.c:324
+#: as.c:332
+#, c-format
 msgid "  -X                      ignored\n"
 msgstr ""
 
-#: as.c:326
+#: as.c:334
+#, c-format
 msgid "  -Z                      generate object file even after errors\n"
 msgstr ""
 
-#: as.c:328
+#: as.c:336
+#, c-format
 msgid ""
 "  --listing-lhs-width     set the width in words of the output data column "
 "of\n"
 "                          the listing\n"
 msgstr ""
 
-#: as.c:331
+#: as.c:339
+#, c-format
 msgid ""
 "  --listing-lhs-width2    set the width in words of the continuation lines\n"
 "                          of the output data column; ignored if smaller "
@@ -243,110 +298,124 @@ msgid ""
 "                          the width of the first line\n"
 msgstr ""
 
-#: as.c:335
+#: as.c:343
+#, c-format
 msgid ""
 "  --listing-rhs-width     set the max width in characters of the lines from\n"
 "                          the source file\n"
 msgstr ""
 
-#: as.c:338
+#: as.c:346
+#, c-format
 msgid ""
 "  --listing-cont-lines    set the maximum number of continuation lines used\n"
 "                          for the output data column of the listing\n"
 msgstr ""
 
-#: as.c:345
+#: as.c:353
 #, c-format
 msgid "Report bugs to %s\n"
 msgstr ""
 
-#: as.c:557 as.c:559
+#: as.c:553
+#, c-format
+msgid "unrecognized option -%c%s"
+msgstr ""
+
+#. This output is intended to follow the GNU standards document.
+#: as.c:591
 #, c-format
 msgid "GNU assembler %s\n"
 msgstr ""
 
-#: as.c:561
-msgid "Copyright 2002 Free Software Foundation, Inc.\n"
+#: as.c:592
+#, c-format
+msgid "Copyright 2005 Free Software Foundation, Inc.\n"
 msgstr ""
 
-#: as.c:562
+#: as.c:593
+#, c-format
 msgid ""
 "This program is free software; you may redistribute it under the terms of\n"
 "the GNU General Public License.  This program has absolutely no warranty.\n"
 msgstr ""
 
-#: as.c:565
+#: as.c:596
 #, c-format
 msgid "This assembler was configured for a target of `%s'.\n"
 msgstr ""
 
-#: as.c:572
+#: as.c:603
 msgid "multiple emulation names specified"
 msgstr ""
 
-#: as.c:574
+#: as.c:605
 msgid "emulations not handled in this configuration"
 msgstr ""
 
-#: as.c:579
+#: as.c:610
 #, c-format
 msgid "alias = %s\n"
 msgstr ""
 
-#: as.c:580
+#: as.c:611
 #, c-format
 msgid "canonical = %s\n"
 msgstr ""
 
-#: as.c:581
+#: as.c:612
 #, c-format
 msgid "cpu-type = %s\n"
 msgstr ""
 
-#: as.c:583
+#: as.c:614
 #, c-format
 msgid "format = %s\n"
 msgstr ""
 
-#: as.c:586
+#: as.c:617
 #, c-format
 msgid "bfd-target = %s\n"
 msgstr ""
 
-#: as.c:599
+#: as.c:630
 msgid "bad defsym; format is --defsym name=value"
 msgstr ""
 
-#: as.c:623
+#: as.c:650
 msgid "no file name following -t option"
 msgstr ""
 
-#: as.c:638
+#: as.c:665
 #, c-format
 msgid "failed to read instruction table %s\n"
 msgstr ""
 
-#: as.c:765
+#: as.c:832
 #, c-format
 msgid "invalid listing option `%c'"
 msgstr ""
 
-#: as.c:984
-#, c-format
-msgid "%d warnings, treating warnings as errors"
+#: as.c:885
+msgid "--hash-size needs a numeric argument"
 msgstr ""
 
-#: as.c:1015
+#: as.c:910
 #, c-format
 msgid "%s: total time in assembly: %ld.%06ld\n"
 msgstr ""
 
-#: as.c:1018
+#: as.c:913
 #, c-format
 msgid "%s: data size %ld\n"
 msgstr ""
 
-#: as.h:216
+#: as.c:1175
+#, c-format
+msgid "%d warnings, treating warnings as errors"
+msgstr ""
+
+#: as.h:200
 #, c-format
 msgid "Case value %ld unexpected at line %d of file \"%s\"\n"
 msgstr ""
@@ -355,772 +424,791 @@ msgstr ""
 #. * We have a GROSS internal error.
 #. * This should never happen.
 #.
-#: atof-generic.c:437 config/tc-m68k.c:2869
+#: atof-generic.c:419 config/tc-m68k.c:3118
 msgid "failed sanity check"
 msgstr ""
 
-#: cond.c:83
+#: cond.c:82
 msgid "invalid identifier for \".ifdef\""
 msgstr ""
 
-#: cond.c:151
+#: cond.c:149
 msgid "non-constant expression in \".if\" statement"
 msgstr ""
 
-#: cond.c:247
+#: cond.c:276
 msgid "bad format for ifc or ifnc"
 msgstr ""
 
-#: cond.c:278
+#: cond.c:306
 msgid "\".elseif\" without matching \".if\""
 msgstr ""
 
-#: cond.c:282
+#: cond.c:310
 msgid "\".elseif\" after \".else\""
 msgstr ""
 
-#: cond.c:285 cond.c:393
+#: cond.c:313 cond.c:419
 msgid "here is the previous \"else\""
 msgstr ""
 
-#: cond.c:288 cond.c:396
+#: cond.c:316 cond.c:422
 msgid "here is the previous \"if\""
 msgstr ""
 
-#: cond.c:317
+#: cond.c:345
 msgid "non-constant expression in \".elseif\" statement"
 msgstr ""
 
-#: cond.c:356
+#: cond.c:383
 msgid "\".endif\" without \".if\""
 msgstr ""
 
-#: cond.c:386
+#: cond.c:412
 msgid "\".else\" without matching \".if\""
 msgstr ""
 
-#: cond.c:390
+#: cond.c:416
 msgid "duplicate \"else\""
 msgstr ""
 
-#: cond.c:442
+#: cond.c:467
 msgid ".ifeqs syntax error"
 msgstr ""
 
-#: cond.c:525
+#: cond.c:548
 msgid "end of macro inside conditional"
 msgstr ""
 
-#: cond.c:527
+#: cond.c:550
 msgid "end of file inside conditional"
 msgstr ""
 
-#: cond.c:530
+#: cond.c:553
 msgid "here is the start of the unterminated conditional"
 msgstr ""
 
-#: cond.c:534
+#: cond.c:557
 msgid "here is the \"else\" of the unterminated conditional"
 msgstr ""
 
-#: config/obj-aout.c:162
+#: config/obj-aout.c:85
 #, c-format
 msgid "Attempt to put a common symbol into set %s"
 msgstr ""
 
-#: config/obj-aout.c:166
+#: config/obj-aout.c:89
 #, c-format
 msgid "Attempt to put an undefined symbol into set %s"
 msgstr ""
 
-#: config/obj-aout.c:197 config/obj-coff.c:1276
+#: config/obj-aout.c:116 config/obj-coff.c:1328
 #, c-format
 msgid "Symbol `%s' can not be both weak and common"
 msgstr ""
 
-#: config/obj-aout.c:255 config/obj-coff.c:2022
-msgid "unresolved relocation"
-msgstr ""
-
-#: config/obj-aout.c:257 config/obj-coff.c:2024
-#, c-format
-msgid "bad relocation: symbol `%s' not in symbol table"
-msgstr ""
-
-#: config/obj-aout.c:344
-#, c-format
-msgid "%s: bad type for weak symbol"
-msgstr ""
-
-#: config/obj-aout.c:458 config/obj-coff.c:2945 write.c:1931
-#, c-format
-msgid "%s: global symbols not supported in common sections"
-msgstr ""
-
-#: config/obj-aout.c:524
-#, c-format
-msgid "Local symbol %s never defined."
-msgstr ""
-
-#: config/obj-bout.c:319 config/obj-vms.c:629
-#, c-format
-msgid "Local symbol %s never defined"
-msgstr ""
-
-#: config/obj-coff.c:166
+#: config/obj-coff.c:133
 #, c-format
 msgid "Inserting \"%s\" into structure table failed: %s"
 msgstr ""
 
 #. Zero is used as an end marker in the file.
-#: config/obj-coff.c:469
+#: config/obj-coff.c:354
 msgid "Line numbers must be positive integers\n"
 msgstr ""
 
-#. Wrong context.
-#: config/obj-coff.c:503 config/obj-coff.c:2367
+#: config/obj-coff.c:386
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:546 ecoff.c:3278
+#: config/obj-coff.c:428 ecoff.c:3240
 msgid ".loc outside of .text"
 msgstr ""
 
-#: config/obj-coff.c:553
+#: config/obj-coff.c:435
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:641 config/obj-coff.c:2419
+#: config/obj-coff.c:516
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:687 config/obj-coff.c:2471
+#: config/obj-coff.c:555
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:725
+#: config/obj-coff.c:594
 #, c-format
 msgid "`%s' symbol without preceding function"
 msgstr ""
 
-#: config/obj-coff.c:812 config/obj-coff.c:2551
+#: config/obj-coff.c:681
 #, c-format
 msgid "unexpected storage class %d"
 msgstr ""
 
-#: config/obj-coff.c:925 config/obj-coff.c:2658
+#: config/obj-coff.c:790
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr ""
 
-#: config/obj-coff.c:945 config/obj-coff.c:2678
+#: config/obj-coff.c:810
 msgid "badly formed .dim directive ignored"
 msgstr ""
 
-#: config/obj-coff.c:996 config/obj-coff.c:2738
+#: config/obj-coff.c:859
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1012 config/obj-coff.c:2754
+#: config/obj-coff.c:874
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1030 config/obj-coff.c:2772
+#: config/obj-coff.c:891
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1049 config/obj-coff.c:2789
+#: config/obj-coff.c:909
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr ""
 
-#: config/obj-coff.c:1064 config/obj-coff.c:2803
+#: config/obj-coff.c:922
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1086 config/obj-coff.c:2823
+#: config/obj-coff.c:941
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr ""
 
-#: config/obj-coff.c:1233 config/obj-coff.c:3016
+#: config/obj-coff.c:1108
+msgid "badly formed .weak directive ignored"
+msgstr ""
+
+#: config/obj-coff.c:1286
 msgid "mismatched .eb"
 msgstr ""
 
-#: config/obj-coff.c:1254 config/obj-coff.c:3054
-msgid "C_EFCN symbol out of scope"
+#: config/obj-coff.c:1307
+#, c-format
+msgid "C_EFCN symbol for %s out of scope"
 msgstr ""
 
 #. STYP_INFO
 #. STYP_LIB
 #. STYP_OVER
-#: config/obj-coff.c:1482
+#: config/obj-coff.c:1533
 #, c-format
 msgid "unsupported section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1487 config/obj-coff.c:3759 config/tc-ppc.c:4508
+#: config/obj-coff.c:1538 config/tc-ppc.c:4610
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr ""
 
-#: config/obj-coff.c:1517 config/tc-ppc.c:4526 config/tc-tic54x.c:4339
-#: read.c:2562
+#: config/obj-coff.c:1568 config/tc-ppc.c:4628 config/tc-tic54x.c:4287
+#: read.c:2551
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr ""
 
-#: config/obj-coff.c:1528
+#: config/obj-coff.c:1579
 #, c-format
 msgid "Ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-coff.c:1664
+#: config/obj-coff.c:1710
 #, c-format
 msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
 msgstr ""
 
-#: config/obj-coff.c:1849 config/obj-ieee.c:69
-msgid "Out of step\n"
+#: config/obj-ecoff.c:125
+msgid "Can't set GP value"
 msgstr ""
 
-#: config/obj-coff.c:2286
-msgid "bfd_coff_swap_scnhdr_out failed"
+#: config/obj-ecoff.c:132
+msgid "Can't set register masks"
 msgstr ""
 
-#: config/obj-coff.c:2507
-msgid "`.bf' symbol without preceding function\n"
+#: config/obj-elf.c:318 config/tc-sparc.c:3973 config/tc-v850.c:451
+#, c-format
+msgid "bad .common segment %s"
 msgstr ""
 
-#: config/obj-coff.c:3457 config/obj-ieee.c:521
+#: config/obj-elf.c:596
 #, c-format
-msgid "FATAL: Can't create %s"
+msgid "setting incorrect section type for %s"
 msgstr ""
 
-#: config/obj-coff.c:3635
+#: config/obj-elf.c:601
 #, c-format
-msgid "Can't close %s: %s"
+msgid "ignoring incorrect section type for %s"
 msgstr ""
 
-#: config/obj-coff.c:3669
+#: config/obj-elf.c:638
 #, c-format
-msgid "Too many new sections; can't add \"%s\""
+msgid "setting incorrect section attributes for %s"
 msgstr ""
 
-#: config/obj-coff.c:4057 config/tc-sparc.c:3635
-msgid "Expected comma after name"
+#: config/obj-elf.c:690
+#, c-format
+msgid "ignoring changed section type for %s"
 msgstr ""
 
-#: config/obj-coff.c:4063
-msgid "Missing size expression"
+#: config/obj-elf.c:702
+#, c-format
+msgid "ignoring changed section attributes for %s"
 msgstr ""
 
-#: config/obj-coff.c:4069
+#: config/obj-elf.c:704
 #, c-format
-msgid "lcomm length (%d.) <0! Ignored."
+msgid "ignoring changed section entity size for %s"
 msgstr ""
 
-#: config/obj-coff.c:4097
-#, c-format
-msgid "Symbol %s already defined"
+#: config/obj-elf.c:757
+msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
 msgstr ""
 
-#: config/obj-coff.c:4193 config/tc-i960.c:3221
-#, c-format
-msgid "No 'bal' entry point for leafproc %s"
+#: config/obj-elf.c:794
+msgid "unrecognized section attribute"
 msgstr ""
 
-#: config/obj-coff.c:4270
-#, c-format
-msgid "Negative of non-absolute symbol %s"
+#: config/obj-elf.c:822 read.c:2535
+msgid "unrecognized section type"
 msgstr ""
 
-#: config/obj-coff.c:4290
-msgid "callj to difference of 2 symbols"
+#: config/obj-elf.c:852
+msgid "missing name"
 msgstr ""
 
-#: config/obj-coff.c:4334
-#, c-format
-msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
+#: config/obj-elf.c:963
+msgid "invalid merge entity size"
 msgstr ""
 
-#: config/obj-coff.c:4420 config/tc-i960.c:2844
-msgid "can't use COBR format with external label"
+#: config/obj-elf.c:970
+msgid "entity size for SHF_MERGE not specified"
 msgstr ""
 
-#: config/obj-coff.c:4493
-#, c-format
-msgid "Value of %ld too large for field of %d bytes at 0x%lx"
+#: config/obj-elf.c:990
+msgid "group name for SHF_GROUP not specified"
 msgstr ""
 
-#: config/obj-coff.c:4507
-#, c-format
-msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
+#: config/obj-elf.c:1003
+msgid "character following name is not '#'"
 msgstr ""
 
-#: config/obj-ecoff.c:192
-msgid "Can't set GP value"
+#: config/obj-elf.c:1118
+msgid ".previous without corresponding .section; ignored"
 msgstr ""
 
-#: config/obj-ecoff.c:199
-msgid "Can't set register masks"
+#: config/obj-elf.c:1144
+msgid ".popsection without corresponding .pushsection; ignored"
 msgstr ""
 
-#: config/obj-elf.c:316
-msgid "expected comma after symbol-name"
+#: config/obj-elf.c:1196
+msgid "expected comma after name in .symver"
 msgstr ""
 
-#: config/obj-elf.c:326
+#: config/obj-elf.c:1220
 #, c-format
-msgid ".COMMon length (%ld) out of range, ignored."
+msgid "missing version name in `%s' for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:335 ecoff.c:3397 read.c:1406 read.c:1507 read.c:2145
-#: read.c:2234 read.c:2863 read.c:4968 symbols.c:367 symbols.c:466
+#: config/obj-elf.c:1231
 #, c-format
-msgid "symbol `%s' is already defined"
+msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:343
-#, c-format
-msgid "length of .comm \"%s\" is already %ld; not changed to %ld"
+#: config/obj-elf.c:1461
+msgid "expected quoted string"
 msgstr ""
 
-#: config/obj-elf.c:367
-msgid "common alignment negative; 0 assumed"
+#: config/obj-elf.c:1481
+#, c-format
+msgid "expected comma after name `%s' in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:386
-msgid "common alignment not a power of 2"
+#: config/obj-elf.c:1490
+msgid "missing expression in .size directive"
 msgstr ""
 
-#: config/obj-elf.c:449 config/tc-sparc.c:3931 config/tc-v850.c:461
+#: config/obj-elf.c:1577
 #, c-format
-msgid "bad .common segment %s"
+msgid "unrecognized symbol type \"%s\""
 msgstr ""
 
-#: config/obj-elf.c:717
-#, c-format
-msgid "setting incorrect section type for %s"
+#: config/obj-elf.c:1745
+msgid ".size expression too complicated to fix up"
 msgstr ""
 
-#: config/obj-elf.c:721
+#: config/obj-elf.c:1777
 #, c-format
-msgid "ignoring incorrect section type for %s"
+msgid ""
+"invalid attempt to declare external version name as default in symbol `%s'"
 msgstr ""
 
-#: config/obj-elf.c:734
+#: config/obj-elf.c:1838 ecoff.c:3598
 #, c-format
-msgid "setting incorrect section attributes for %s"
+msgid "symbol `%s' can not be both weak and common"
 msgstr ""
 
-#: config/obj-elf.c:786
+#: config/obj-elf.c:1945
 #, c-format
-msgid "ignoring changed section attributes for %s"
+msgid "assuming all members of group `%s' are COMDAT"
 msgstr ""
 
-#: config/obj-elf.c:788
+#: config/obj-elf.c:1967
 #, c-format
-msgid "ignoring changed section entity size for %s"
+msgid "can't create group: %s"
 msgstr ""
 
-#: config/obj-elf.c:791
+#: config/obj-elf.c:2076
 #, c-format
-msgid "ignoring new section group for %s"
+msgid "failed to set up debugging information: %s"
 msgstr ""
 
-#: config/obj-elf.c:845
-msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
+#: config/obj-elf.c:2096
+#, c-format
+msgid "can't start writing .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.c:884
-msgid "unrecognized section attribute"
+#: config/obj-elf.c:2104
+#, c-format
+msgid "could not write .mdebug section: %s"
 msgstr ""
 
-#: config/obj-elf.c:906 read.c:2545
-msgid "unrecognized section type"
+#: config/obj-elf.h:140
+#, c-format
+msgid "can't allocate ELF private section data: %s"
 msgstr ""
 
-#: config/obj-elf.c:936
-msgid "missing name"
+#: config/obj-ieee.c:69
+#, c-format
+msgid "Out of step\n"
 msgstr ""
 
-#: config/obj-elf.c:1048
-msgid "invalid merge entity size"
+#: config/obj-ieee.c:449
+msgid "too many sections"
 msgstr ""
 
-#: config/obj-elf.c:1055
-msgid "entity size for SHF_MERGE not specified"
+#: config/obj-ieee.c:511
+#, c-format
+msgid "FATAL: Can't create %s"
 msgstr ""
 
-#: config/obj-elf.c:1075
-msgid "group name for SHF_GROUP not specified"
+#: config/obj-som.c:129
+msgid "Only one .version pseudo-op per file!"
 msgstr ""
 
-#: config/obj-elf.c:1088
-msgid "character following name is not '#'"
+#: config/obj-som.c:146 config/obj-som.c:191
+msgid "Expected quoted string"
 msgstr ""
 
-#: config/obj-elf.c:1189
-msgid ".previous without corresponding .section; ignored"
+#: config/obj-som.c:155
+#, c-format
+msgid "FATAL: Attaching version header %s"
 msgstr ""
 
-#: config/obj-elf.c:1216
-msgid ".popsection without corresponding .pushsection; ignored"
+#: config/obj-som.c:174
+msgid "Only one .copyright pseudo-op per file!"
 msgstr ""
 
-#: config/obj-elf.c:1270
-msgid "expected comma after name in .symver"
+#: config/obj-som.c:200
+#, c-format
+msgid "FATAL: Attaching copyright header %s"
 msgstr ""
 
-#: config/obj-elf.c:1294
+#: config/tc-alpha.c:592
 #, c-format
-msgid "missing version name in `%s' for symbol `%s'"
+msgid "No !literal!%ld was found"
 msgstr ""
 
-#: config/obj-elf.c:1305
+#: config/tc-alpha.c:599
 #, c-format
-msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
+msgid "No !tlsgd!%ld was found"
 msgstr ""
 
-#: config/obj-elf.c:1541
-msgid "expected quoted string"
+#: config/tc-alpha.c:606
+#, c-format
+msgid "No !tlsldm!%ld was found"
 msgstr ""
 
-#: config/obj-elf.c:1562
+#: config/tc-alpha.c:615
 #, c-format
-msgid "expected comma after name `%s' in .size directive"
+msgid "No ldah !gpdisp!%ld was found"
 msgstr ""
 
-#: config/obj-elf.c:1571
-msgid "missing expression in .size directive"
+#: config/tc-alpha.c:665
+#, c-format
+msgid "too many !literal!%ld for %s"
 msgstr ""
 
-#: config/obj-elf.c:1660
+#: config/tc-alpha.c:695
 #, c-format
-msgid "unrecognized symbol type \"%s\""
+msgid "No lda !gpdisp!%ld was found"
 msgstr ""
 
-#: config/obj-elf.c:1841
-msgid ".size expression too complicated to fix up"
+#. Only support one relocation op per insn.
+#: config/tc-alpha.c:852
+msgid "More than one relocation op per insn"
 msgstr ""
 
-#: config/obj-elf.c:1873
+#: config/tc-alpha.c:868
+msgid "No relocation operand"
+msgstr ""
+
+#: config/tc-alpha.c:878
 #, c-format
-msgid ""
-"invalid attempt to declare external version name as default in symbol `%s'"
+msgid "Unknown relocation operand: !%s"
 msgstr ""
 
-#: config/obj-elf.c:1934 ecoff.c:3642
+#: config/tc-alpha.c:888
 #, c-format
-msgid "symbol `%s' can not be both weak and common"
+msgid "no sequence number after !%s"
 msgstr ""
 
-#: config/obj-elf.c:2054
+#: config/tc-alpha.c:898
 #, c-format
-msgid "assuming all members of group `%s' are COMDAT"
+msgid "!%s does not use a sequence number"
 msgstr ""
 
-#: config/obj-elf.c:2076
+#: config/tc-alpha.c:908
 #, c-format
-msgid "can't create group: %s"
+msgid "Bad sequence number: !%s!%s"
 msgstr ""
 
-#: config/obj-elf.c:2183
+#: config/tc-alpha.c:1123 config/tc-alpha.c:3139
 #, c-format
-msgid "failed to set up debugging information: %s"
+msgid "inappropriate arguments for opcode `%s'"
 msgstr ""
 
-#: config/obj-elf.c:2203
+#: config/tc-alpha.c:1125 config/tc-alpha.c:3141
 #, c-format
-msgid "can't start writing .mdebug section: %s"
+msgid "opcode `%s' not supported for target %s"
 msgstr ""
 
-#: config/obj-elf.c:2211
+#: config/tc-alpha.c:1129 config/tc-alpha.c:3145 config/tc-avr.c:1221
+#: config/tc-msp430.c:1870
 #, c-format
-msgid "could not write .mdebug section: %s"
+msgid "unknown opcode `%s'"
 msgstr ""
 
-#: config/obj-ieee.c:455
-msgid "too many sections"
+#: config/tc-alpha.c:1209 config/tc-alpha.c:1384
+msgid "overflow in literal (.lita) table"
 msgstr ""
 
-#: config/obj-som.c:138
-msgid "Only one .version pseudo-op per file!"
+#: config/tc-alpha.c:1216 config/tc-alpha.c:1240 config/tc-alpha.c:1397
+#: config/tc-alpha.c:2049 config/tc-alpha.c:2093 config/tc-alpha.c:2162
+#: config/tc-alpha.c:2245 config/tc-alpha.c:2470 config/tc-alpha.c:2568
+msgid "macro requires $at register while noat in effect"
 msgstr ""
 
-#: config/obj-som.c:155 config/obj-som.c:201
-msgid "Expected quoted string"
+#: config/tc-alpha.c:1218 config/tc-alpha.c:1242 config/tc-alpha.c:1399
+msgid "macro requires $at while $at in use"
 msgstr ""
 
-#: config/obj-som.c:164
-#, c-format
-msgid "FATAL: Attaching version header %s"
+#: config/tc-alpha.c:1346
+msgid "bignum invalid; zero assumed"
 msgstr ""
 
-#: config/obj-som.c:184
-msgid "Only one .copyright pseudo-op per file!"
+#: config/tc-alpha.c:1348
+msgid "floating point number invalid; zero assumed"
+msgstr ""
+
+#: config/tc-alpha.c:1353
+msgid "can't handle expression"
 msgstr ""
 
-#: config/obj-som.c:210
+#: config/tc-alpha.c:1390
+msgid "overflow in literal (.lit8) table"
+msgstr ""
+
+#: config/tc-alpha.c:1674
 #, c-format
-msgid "FATAL: Attaching copyright header %s"
+msgid "too many ldah insns for !gpdisp!%ld"
 msgstr ""
 
-#: config/obj-vms.c:530
+#: config/tc-alpha.c:1676 config/tc-alpha.c:1688
 #, c-format
-msgid "compiler emitted zero-size common symbol `%s' already defined"
+msgid "both insns for !gpdisp!%ld must be in the same section"
 msgstr ""
 
-#: config/obj-vms.c:540
+#: config/tc-alpha.c:1686
 #, c-format
-msgid "compiler redefined zero-size common symbol `%s'"
+msgid "too many lda insns for !gpdisp!%ld"
 msgstr ""
 
-#: config/obj-vms.c:663
+#: config/tc-alpha.c:1742
 #, c-format
-msgid "Couldn't create VMS object file \"%s\""
+msgid "too many lituse insns for !lituse_tlsgd!%ld"
 msgstr ""
 
-#: config/obj-vms.c:688
-msgid "I/O error writing VMS object file (length prefix)"
+#: config/tc-alpha.c:1745
+#, c-format
+msgid "too many lituse insns for !lituse_tlsldm!%ld"
 msgstr ""
 
-#: config/obj-vms.c:702
-msgid "I/O error writing VMS object file"
+#: config/tc-alpha.c:1762
+#, c-format
+msgid "duplicate !tlsgd!%ld"
 msgstr ""
 
-#: config/obj-vms.c:1292
+#: config/tc-alpha.c:1764
 #, c-format
-msgid "Couldn't find source file \"%s\", status=%%X%x"
+msgid "sequence number in use for !tlsldm!%ld"
 msgstr ""
 
-#: config/obj-vms.c:1790 config/obj-vms.c:2967
+#: config/tc-alpha.c:1778
 #, c-format
-msgid "debugger forward reference error, dbx type %d"
+msgid "duplicate !tlsldm!%ld"
 msgstr ""
 
-#: config/obj-vms.c:1865
+#: config/tc-alpha.c:1780
 #, c-format
-msgid "Variable descriptor %d too complicated.  Defined as `void *'."
+msgid "sequence number in use for !tlsgd!%ld"
 msgstr ""
 
-#: config/obj-vms.c:2179
-msgid ""
-"***Warning - the assembly code generated by the compiler has placed \n"
-" global constant(s) in the text psect.  These will not be available to \n"
-" other modules, since this is not the correct way to handle this. You \n"
-" have two options: 1) get a patched compiler that does not put global \n"
-" constants in the text psect, or 2) remove the 'const' keyword from \n"
-" definitions of global variables in your source module(s).  Don't say \n"
-" I didn't warn you! \n"
+#: config/tc-alpha.c:1823 config/tc-arc.c:294 config/tc-mn10200.c:889
+#: config/tc-mn10300.c:2600 config/tc-ppc.c:1476 config/tc-s390.c:614
+#: config/tc-v850.c:1573
+msgid "operand"
 msgstr ""
 
-#: config/obj-vms.c:2494
-#, c-format
-msgid "debugginer output: %d is an unknown untyped variable."
+#: config/tc-alpha.c:1926 config/tc-alpha.c:1950 config/tc-d10v.c:585
+#: config/tc-d30v.c:573 config/tc-mn10200.c:1133 config/tc-mn10300.c:1893
+#: config/tc-ppc.c:2348 config/tc-ppc.c:2565 config/tc-ppc.c:2577
+#: config/tc-s390.c:1230 config/tc-s390.c:1330 config/tc-s390.c:1459
+#: config/tc-v850.c:1747 config/tc-v850.c:1770 config/tc-v850.c:1973
+msgid "too many fixups"
 msgstr ""
 
-#: config/obj-vms.c:2712
-#, c-format
-msgid "debugger output: structure element `%s' has undefined type"
+#: config/tc-alpha.c:1962
+msgid "invalid relocation for instruction"
 msgstr ""
 
-#: config/obj-vms.c:2823
-#, c-format
-msgid "debugger output: %d is an unknown type of variable."
+#: config/tc-alpha.c:1973
+msgid "invalid relocation for field"
 msgstr ""
 
-#: config/obj-vms.c:2956
-#, c-format
-msgid "debugger output: Unable to resolve %d circular references."
+#: config/tc-alpha.c:2760
+msgid "can not resolve expression"
 msgstr ""
 
-#: config/obj-vms.c:3158
+#: config/tc-alpha.c:3275 config/tc-ppc.c:1781 config/tc-ppc.c:4373
 #, c-format
-msgid "Module name truncated: %s\n"
+msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/obj-vms.c:3436
-#, c-format
-msgid "Symbol %s replaced by %s\n"
+#: config/tc-alpha.c:3304 config/tc-sparc.c:3843 config/tc-v850.c:246
+msgid "Ignoring attempt to re-define symbol"
 msgstr ""
 
-#. impossible
-#: config/obj-vms.c:3719
+#: config/tc-alpha.c:3313 config/tc-alpha.c:3322 config/tc-ppc.c:4410
+#: config/tc-sparc.c:3851
 #, c-format
-msgid "Unknown VMS psect type (%ld)"
+msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/obj-vms.c:3760
-#, c-format
-msgid "Globalsymbol attribute for symbol %s was unexpected."
+#: config/tc-alpha.c:3439 ecoff.c:3054
+msgid ".ent directive has no name"
 msgstr ""
 
-#: config/obj-vms.c:3909
-msgid "Invalid data type for globalvalue"
+#: config/tc-alpha.c:3447
+msgid "nested .ent directives"
 msgstr ""
 
-#: config/obj-vms.c:3921
-#, c-format
-msgid "Invalid globalvalue of %s"
+#: config/tc-alpha.c:3491 ecoff.c:3005
+msgid ".end directive has no name"
 msgstr ""
 
-#: config/obj-vms.c:4271
-msgid "Couldn't find fixup fragment when checking for indirect reference"
+#: config/tc-alpha.c:3500
+msgid ".end directive without matching .ent"
 msgstr ""
 
-#: config/obj-vms.c:4614 config/obj-vms.c:4757
-msgid "Fixup data addsy and subsy don't have the same type"
+#: config/tc-alpha.c:3502
+msgid ".end directive names different symbol than .ent"
 msgstr ""
 
-#: config/obj-vms.c:4618 config/obj-vms.c:4761
-msgid "Fixup data addsy and subsy don't have an appropriate type"
+#: config/tc-alpha.c:3545 ecoff.c:3140
+msgid ".fmask outside of .ent"
 msgstr ""
 
-#: config/obj-vms.c:4621 config/obj-vms.c:4764
-msgid "Fixup data is erroneously \"pcrel\""
+#: config/tc-alpha.c:3547 ecoff.c:3204
+msgid ".mask outside of .ent"
 msgstr ""
 
-#: config/obj-vms.c:4637 config/obj-vms.c:4783
-msgid "Fixup datum is not a longword"
+#: config/tc-alpha.c:3555 ecoff.c:3147
+msgid "bad .fmask directive"
 msgstr ""
 
-#: config/obj-vms.c:4641 config/obj-vms.c:4787
-msgid "Fixup datum is not \"fixP->fx_addsy\""
+#: config/tc-alpha.c:3557 ecoff.c:3211
+msgid "bad .mask directive"
 msgstr ""
 
-#: config/obj-vms.c:4858
-#, c-format
-msgid ""
-"g++ wrote an extern reference to `%s' as a routine.\n"
-"I will fix it, but I hope that it was note really a routine."
+#: config/tc-alpha.c:3590 config/tc-mips.c:14022 ecoff.c:3168
+msgid ".frame outside of .ent"
 msgstr ""
 
-#: config/obj-vms.c:4990
-msgid "Can't handle global xtors symbols yet."
+#: config/tc-alpha.c:3601 ecoff.c:3179
+msgid "bad .frame directive"
 msgstr ""
 
-#: config/obj-vms.c:4993
-#, c-format
-msgid "Unknown %s"
+#: config/tc-alpha.c:3633
+msgid ".prologue directive without a preceding .ent directive"
 msgstr ""
 
-#.
-#. *	Error otherwise.
-#.
-#: config/obj-vms.c:5078
+#: config/tc-alpha.c:3651
 #, c-format
-msgid "unhandled stab type %d"
+msgid "Invalid argument %d to .prologue."
 msgstr ""
 
-#: config/tc-a29k.c:163 config/tc-sparc.c:3983
-msgid "Unknown segment type"
+#: config/tc-alpha.c:3742
+msgid "ECOFF debugging is disabled."
 msgstr ""
 
-#. Probably a memory allocation problem?  Give up now.
-#: config/tc-a29k.c:333 config/tc-dlx.c:369 config/tc-hppa.c:1463
-#: config/tc-mips.c:1108 config/tc-mips.c:1150 config/tc-or32.c:228
-#: config/tc-sparc.c:853
-msgid "Broken assembler.  No assembly attempted."
+#: config/tc-alpha.c:3756
+msgid ".ent directive without matching .end"
 msgstr ""
 
-#: config/tc-a29k.c:378 config/tc-avr.c:1121 config/tc-d10v.c:545
-#: config/tc-d30v.c:551 config/tc-h8300.c:492 config/tc-h8500.c:283
-#: config/tc-mcore.c:607 config/tc-mmix.c:470 config/tc-mn10200.c:940
-#: config/tc-mn10300.c:1815 config/tc-msp430.c:1544 config/tc-or32.c:334
-#: config/tc-or32.c:390 config/tc-ppc.c:2334 config/tc-s390.c:1236
-#: config/tc-sh.c:1264 config/tc-sh64.c:2254 config/tc-tic80.c:279
-#: config/tc-v850.c:2024 config/tc-w65.c:218 config/tc-z8k.c:376
-msgid "missing operand"
+#: config/tc-alpha.c:3841
+msgid ".usepv directive has no name"
 msgstr ""
 
-#: config/tc-a29k.c:417 config/tc-cris.c:1075 config/tc-cris.c:1083
-#: config/tc-dlx.c:834 config/tc-hppa.c:1599 config/tc-i860.c:453
-#: config/tc-i860.c:470 config/tc-i860.c:930 config/tc-sparc.c:1415
-#: config/tc-sparc.c:1421
-#, c-format
-msgid "Unknown opcode: `%s'"
+#: config/tc-alpha.c:3852
+msgid ".usepv directive has no type"
 msgstr ""
 
-#: config/tc-a29k.c:422 config/tc-dlx.c:852
-#, c-format
-msgid "Unknown opcode `%s'."
+#: config/tc-alpha.c:3867
+msgid "unknown argument for .usepv"
 msgstr ""
 
-#: config/tc-a29k.c:454 config/tc-dlx.c:913
-#, c-format
-msgid "Too many operands: %s"
+#: config/tc-alpha.c:3900
+msgid "Unknown section directive"
 msgstr ""
 
-#: config/tc-a29k.c:476 config/tc-a29k.c:507
-#, c-format
-msgid "Immediate value of %ld is too large"
+#: config/tc-alpha.c:3935
+msgid ".ent directive has no symbol"
 msgstr ""
 
-#: config/tc-a29k.c:546 config/tc-i860.c:355 config/tc-i860.c:902
-#: config/tc-m68k.c:3171 config/tc-m68k.c:3200 config/tc-sparc.c:2647
-msgid "failed sanity check."
+#: config/tc-alpha.c:3960
+msgid "Bad .frame directive 1./2. param"
+msgstr ""
+
+#: config/tc-alpha.c:3972
+msgid "Bad .frame directive 3./4. param"
+msgstr ""
+
+#: config/tc-alpha.c:3994
+msgid ".pdesc directive not in link (.link) section"
+msgstr ""
+
+#: config/tc-alpha.c:4002
+msgid ".pdesc has no matching .ent"
+msgstr ""
+
+#: config/tc-alpha.c:4013
+msgid ".pdesc directive has no entry symbol"
+msgstr ""
+
+#: config/tc-alpha.c:4026
+msgid "No comma after .pdesc <entryname>"
+msgstr ""
+
+#: config/tc-alpha.c:4046
+msgid "unknown procedure kind"
+msgstr ""
+
+#: config/tc-alpha.c:4136
+msgid ".name directive not in link (.link) section"
+msgstr ""
+
+#: config/tc-alpha.c:4144
+msgid ".name directive has no symbol"
+msgstr ""
+
+#: config/tc-alpha.c:4175
+msgid "No symbol after .linkage"
+msgstr ""
+
+#: config/tc-alpha.c:4199
+msgid "No symbol after .code_address"
+msgstr ""
+
+#: config/tc-alpha.c:4226
+msgid "Bad .mask directive"
 msgstr ""
 
-#: config/tc-a29k.c:892 config/tc-or32.c:1044 config/tc-or32.c:1178
+#: config/tc-alpha.c:4244
+msgid "Bad .fmask directive"
+msgstr ""
+
+#: config/tc-alpha.c:4401
 #, c-format
-msgid "bad relocation type: 0x%02x"
+msgid "Expected comma after name \"%s\""
 msgstr ""
 
-#: config/tc-a29k.c:919
+#. *symbol_get_obj (symbolP) = (signed char) temp;
+#: config/tc-alpha.c:4412
 #, c-format
-msgid "need %o3\n"
+msgid "unhandled: .proc %s,%d"
 msgstr ""
 
-#: config/tc-a29k.c:935
-msgid "a29k_convert_frag\n"
+#: config/tc-alpha.c:4446
+#, c-format
+msgid "Tried to .set unrecognized mode `%s'"
 msgstr ""
 
-#: config/tc-a29k.c:944
-msgid "a29k_estimate_size_before_relax\n"
+#: config/tc-alpha.c:4472
+#, c-format
+msgid "Bad base register, using $%d."
 msgstr ""
 
-#: config/tc-a29k.c:1095 config/tc-dlx.c:1283 config/tc-or32.c:1373
+#: config/tc-alpha.c:4493
 #, c-format
-msgid "label \"$%d\" redefined"
+msgid "Alignment too large: %d. assumed"
 msgstr ""
 
-#: config/tc-a29k.c:1168 config/tc-dlx.c:511 config/tc-or32.c:1466
+#: config/tc-alpha.c:4497 config/tc-d30v.c:2083
+msgid "Alignment negative: 0 assumed"
+msgstr ""
+
+#: config/tc-alpha.c:4775
 #, c-format
-msgid "Invalid expression after %%%%\n"
+msgid "Chose GP value of %lx\n"
 msgstr ""
 
-#: config/tc-a29k.c:1179
-msgid "Invalid register in & expression"
+#: config/tc-alpha.c:4789
+msgid "Bad .section directive: want a,s,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-alpha.c:826
+#: config/tc-alpha.c:4878
 #, c-format
 msgid "internal error: can't hash opcode `%s': %s"
 msgstr ""
 
-#: config/tc-alpha.c:860
+#: config/tc-alpha.c:4914
 #, c-format
 msgid "internal error: can't hash macro `%s': %s"
 msgstr ""
 
-#: config/tc-alpha.c:943 config/tc-i960.c:2707 config/tc-xtensa.c:4954
-#: config/tc-xtensa.c:5015
+#: config/tc-alpha.c:4998 config/tc-i960.c:710 config/tc-xtensa.c:5112
+#: config/tc-xtensa.c:5181 config/tc-xtensa.c:5227
 msgid "syntax error"
 msgstr ""
 
-#: config/tc-alpha.c:1017 config/tc-h8300.c:2099 config/tc-h8500.c:1204
-#: config/tc-hppa.c:4018 config/tc-i860.c:1004 config/tc-m68hc11.c:568
-#: config/tc-m68k.c:4196 config/tc-m88k.c:991 config/tc-ns32k.c:1689
-#: config/tc-or32.c:910 config/tc-sparc.c:2934 config/tc-z8k.c:1371
+#: config/tc-alpha.c:5067 config/tc-h8300.c:2055 config/tc-hppa.c:4041
+#: config/tc-i860.c:1059 config/tc-m68hc11.c:558 config/tc-m68k.c:4524
+#: config/tc-ns32k.c:1945 config/tc-or32.c:579 config/tc-sparc.c:2944
+#: config/tc-z8k.c:1310
 msgid "Bad call to MD_ATOF()"
 msgstr ""
 
-#: config/tc-alpha.c:1067
+#: config/tc-alpha.c:5116
 #, c-format
 msgid "Unknown CPU identifier `%s'"
 msgstr ""
 
-#: config/tc-alpha.c:1111
+#: config/tc-alpha.c:5159
 msgid ""
 "Alpha options:\n"
 "-32addr\t\t\ttreat addresses as 32-bit values\n"
@@ -1132,1528 +1220,1465 @@ msgid ""
 "\t\t\tthese variants include PALcode opcodes\n"
 msgstr ""
 
-#: config/tc-alpha.c:1121
+#: config/tc-alpha.c:5169
 msgid ""
 "VMS options:\n"
 "-+\t\t\thash encode (don't truncate) names longer than 64 characters\n"
 "-H\t\t\tshow new symbol after hash truncation\n"
 msgstr ""
 
-#: config/tc-alpha.c:1298
+#: config/tc-alpha.c:5346
 #, c-format
 msgid "unhandled relocation type %s"
 msgstr ""
 
-#: config/tc-alpha.c:1311
+#: config/tc-alpha.c:5359
 msgid "non-absolute expression in constant field"
 msgstr ""
 
-#: config/tc-alpha.c:1325
+#: config/tc-alpha.c:5373
 #, c-format
 msgid "type %d reloc done?\n"
 msgstr ""
 
-#: config/tc-alpha.c:1373 config/tc-alpha.c:1380 config/tc-mips.c:8603
+#: config/tc-alpha.c:5420 config/tc-alpha.c:5427 config/tc-mips.c:8657
 msgid "Used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-alpha.c:1542
+#: config/tc-alpha.c:5589
 #, c-format
 msgid "!samegp reloc against symbol without .prologue: %s"
 msgstr ""
 
-#: config/tc-alpha.c:1581 config/tc-xtensa.c:5451
+#: config/tc-alpha.c:5626 config/tc-xtensa.c:5739
 #, c-format
 msgid "cannot represent `%s' relocation in object file"
 msgstr ""
 
-#: config/tc-alpha.c:1588 config/tc-xtensa.c:5458
+#: config/tc-alpha.c:5632 config/tc-xtensa.c:5747
 #, c-format
 msgid "internal error? cannot generate `%s' relocation"
 msgstr ""
 
-#: config/tc-alpha.c:1642
+#: config/tc-alpha.c:5683
 #, c-format
 msgid "frame reg expected, using $%d."
 msgstr ""
 
-#: config/tc-alpha.c:1743
-#, c-format
-msgid "No !literal!%ld was found"
-msgstr ""
-
-#: config/tc-alpha.c:1750
-#, c-format
-msgid "No !tlsgd!%ld was found"
-msgstr ""
-
-#: config/tc-alpha.c:1757
-#, c-format
-msgid "No !tlsldm!%ld was found"
-msgstr ""
-
-#: config/tc-alpha.c:1766
-#, c-format
-msgid "No ldah !gpdisp!%ld was found"
-msgstr ""
-
-#: config/tc-alpha.c:1816
-#, c-format
-msgid "too many !literal!%ld for %s"
-msgstr ""
-
-#: config/tc-alpha.c:1846
-#, c-format
-msgid "No lda !gpdisp!%ld was found"
+#: config/tc-arc.c:1077 config/tc-ip2k.c:249
+msgid "md_estimate_size_before_relax\n"
 msgstr ""
 
-#. Only support one relocation op per insn.
-#: config/tc-alpha.c:1994
-msgid "More than one relocation op per insn"
+#: config/tc-arc.c:1088
+msgid "md_convert_frag\n"
 msgstr ""
 
-#: config/tc-alpha.c:2010
-msgid "No relocation operand"
+#. We can't actually support subtracting a symbol.
+#: config/tc-arc.c:1288 config/tc-arm.c:1021 config/tc-arm.c:5764
+#: config/tc-arm.c:5815 config/tc-arm.c:6614 config/tc-arm.c:7256
+#: config/tc-arm.c:7284 config/tc-arm.c:7536 config/tc-arm.c:7553
+#: config/tc-arm.c:7674 config/tc-avr.c:970 config/tc-cris.c:3928
+#: config/tc-d10v.c:1539 config/tc-d30v.c:1938 config/tc-mips.c:3794
+#: config/tc-mips.c:4902 config/tc-mips.c:5834 config/tc-mips.c:6428
+#: config/tc-msp430.c:1979 config/tc-ppc.c:5562 config/tc-v850.c:2274
+#: config/tc-xstormy16.c:484
+msgid "expression too complex"
 msgstr ""
 
-#: config/tc-alpha.c:2020
-#, c-format
-msgid "Unknown relocation operand: !%s"
+#: config/tc-arm.c:352
+msgid "ARM register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2030
-#, c-format
-msgid "no sequence number after !%s"
+#: config/tc-arm.c:353
+msgid "bad or missing co-processor number"
 msgstr ""
 
-#: config/tc-alpha.c:2040
-#, c-format
-msgid "!%s does not use a sequence number"
+#: config/tc-arm.c:354
+msgid "co-processor register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2050
-#, c-format
-msgid "Bad sequence number: !%s!%s"
+#: config/tc-arm.c:355
+msgid "FPA register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2378
-#, c-format
-msgid "operand out of range (%s not between %d and %d)"
+#: config/tc-arm.c:356
+msgid "VFP single precision register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2490 config/tc-alpha.c:2514 config/tc-d10v.c:634
-#: config/tc-d30v.c:639 config/tc-mn10200.c:995 config/tc-mn10300.c:1888
-#: config/tc-ppc.c:2300 config/tc-ppc.c:2517 config/tc-ppc.c:2529
-#: config/tc-s390.c:1246 config/tc-s390.c:1346 config/tc-s390.c:1442
-#: config/tc-v850.c:1804 config/tc-v850.c:1827 config/tc-v850.c:2047
-msgid "too many fixups"
+#: config/tc-arm.c:357
+msgid "VFP double precision register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2526
-msgid "invalid relocation for instruction"
+#: config/tc-arm.c:358
+msgid "VFP system register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2537
-msgid "invalid relocation for field"
+#: config/tc-arm.c:359
+msgid "Maverick MVF register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2642
-#, c-format
-msgid "too many ldah insns for !gpdisp!%ld"
+#: config/tc-arm.c:360
+msgid "Maverick MVD register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2644 config/tc-alpha.c:2656
-#, c-format
-msgid "both insns for !gpdisp!%ld must be in the same section"
+#: config/tc-arm.c:361
+msgid "Maverick MVFX register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2654
-#, c-format
-msgid "too many lda insns for !gpdisp!%ld"
+#: config/tc-arm.c:362
+msgid "Maverick MVDX register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2707
-#, c-format
-msgid "too many lituse insns for !lituse_tlsgd!%ld"
+#: config/tc-arm.c:363
+msgid "Maverick MVAX register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2710
-#, c-format
-msgid "too many lituse insns for !lituse_tlsldm!%ld"
+#: config/tc-arm.c:364
+msgid "Maverick DSPSC register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2727
-#, c-format
-msgid "duplicate !tlsgd!%ld"
+#: config/tc-arm.c:365
+msgid "iWMMXt data register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2729
-#, c-format
-msgid "sequence number in use for !tlsldm!%ld"
+#: config/tc-arm.c:366
+msgid "iWMMXt control register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2743
-#, c-format
-msgid "duplicate !tlsldm!%ld"
+#: config/tc-arm.c:367
+msgid "iWMMXt scalar register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2745
-#, c-format
-msgid "sequence number in use for !tlsgd!%ld"
+#: config/tc-arm.c:368
+msgid "XScale accumulator register expected"
 msgstr ""
 
-#: config/tc-alpha.c:2790 config/tc-alpha.c:2863
-#, c-format
-msgid "inappropriate arguments for opcode `%s'"
+#: config/tc-arm.c:499
+msgid "bad arguments to instruction"
 msgstr ""
 
-#: config/tc-alpha.c:2792 config/tc-alpha.c:2865
-#, c-format
-msgid "opcode `%s' not supported for target %s"
+#: config/tc-arm.c:500
+msgid "r15 not allowed here"
 msgstr ""
 
-#: config/tc-alpha.c:2796 config/tc-alpha.c:2869 config/tc-avr.c:1087
-#: config/tc-msp430.c:446
-#, c-format
-msgid "unknown opcode `%s'"
+#: config/tc-arm.c:501
+msgid "instruction cannot be conditional"
 msgstr ""
 
-#: config/tc-alpha.c:2916
-msgid "can not resolve expression"
+#: config/tc-arm.c:502
+msgid "registers may not be the same"
 msgstr ""
 
-#: config/tc-alpha.c:3060 config/tc-alpha.c:3239
-msgid "overflow in literal (.lita) table"
+#: config/tc-arm.c:503
+msgid "lo register required"
 msgstr ""
 
-#: config/tc-alpha.c:3067 config/tc-alpha.c:3090 config/tc-alpha.c:3252
-#: config/tc-alpha.c:3467 config/tc-alpha.c:3512 config/tc-alpha.c:3586
-#: config/tc-alpha.c:3678 config/tc-alpha.c:3926 config/tc-alpha.c:4025
-msgid "macro requires $at register while noat in effect"
+#: config/tc-arm.c:504
+msgid "instruction not supported in Thumb16 mode"
 msgstr ""
 
-#: config/tc-alpha.c:3069 config/tc-alpha.c:3092 config/tc-alpha.c:3254
-msgid "macro requires $at while $at in use"
+#: config/tc-arm.c:640
+msgid "immediate expression requires a # prefix"
 msgstr ""
 
-#: config/tc-alpha.c:3200
-msgid "bignum invalid; zero assumed"
+#: config/tc-arm.c:666 expr.c:1302 read.c:2228
+msgid "bad expression"
 msgstr ""
 
-#: config/tc-alpha.c:3202
-msgid "floating point number invalid; zero assumed"
+#: config/tc-arm.c:677 config/tc-i860.c:1005 config/tc-sparc.c:2844
+msgid "bad segment"
 msgstr ""
 
-#: config/tc-alpha.c:3207
-msgid "can't handle expression"
+#: config/tc-arm.c:693 config/tc-arm.c:3230 config/tc-i960.c:1302
+msgid "invalid constant"
 msgstr ""
 
-#: config/tc-alpha.c:3245
-msgid "overflow in literal (.lit8) table"
+#: config/tc-arm.c:754
+msgid "bad call to MD_ATOF()"
 msgstr ""
 
-#: config/tc-alpha.c:4262 config/tc-ppc.c:1740 config/tc-ppc.c:4271
-#, c-format
-msgid ".COMMon length (%ld.) <0! Ignored."
+#: config/tc-arm.c:821
+msgid "expected #constant"
 msgstr ""
 
-#: config/tc-alpha.c:4291 config/tc-sparc.c:3799 config/tc-v850.c:256
-msgid "Ignoring attempt to re-define symbol"
+#: config/tc-arm.c:953
+msgid "bad range in register list"
 msgstr ""
 
-#: config/tc-alpha.c:4300 config/tc-alpha.c:4309 config/tc-ppc.c:4308
+#: config/tc-arm.c:961 config/tc-arm.c:970 config/tc-arm.c:1011
 #, c-format
-msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
-msgstr ""
-
-#: config/tc-alpha.c:4430 ecoff.c:3082
-msgid ".ent directive has no name"
-msgstr ""
-
-#: config/tc-alpha.c:4438
-msgid "nested .ent directives"
-msgstr ""
-
-#: config/tc-alpha.c:4483 ecoff.c:3032
-msgid ".end directive has no name"
+msgid "Warning: duplicated register (r%d) in register list"
 msgstr ""
 
-#: config/tc-alpha.c:4492
-msgid ".end directive without matching .ent"
+#: config/tc-arm.c:973
+msgid "Warning: register range not in ascending order"
 msgstr ""
 
-#: config/tc-alpha.c:4494
-msgid ".end directive names different symbol than .ent"
+#: config/tc-arm.c:984
+msgid "missing `}'"
 msgstr ""
 
-#: config/tc-alpha.c:4538 ecoff.c:3171
-msgid ".fmask outside of .ent"
+#: config/tc-arm.c:1000
+msgid "invalid register mask"
 msgstr ""
 
-#: config/tc-alpha.c:4540 ecoff.c:3241
-msgid ".mask outside of .ent"
+#: config/tc-arm.c:1091 config/tc-arm.c:1126 config/tc-h8300.c:991
+#: config/tc-mips.c:9797 config/tc-mips.c:9827
+msgid "invalid register list"
 msgstr ""
 
-#: config/tc-alpha.c:4548 ecoff.c:3178
-msgid "bad .fmask directive"
+#: config/tc-arm.c:1097 config/tc-arm.c:2402 config/tc-arm.c:2535
+msgid "register list not in ascending order"
 msgstr ""
 
-#: config/tc-alpha.c:4550 ecoff.c:3248
-msgid "bad .mask directive"
+#: config/tc-arm.c:1118
+msgid "register range not in ascending order"
 msgstr ""
 
-#: config/tc-alpha.c:4584 config/tc-mips.c:14143 ecoff.c:3200
-msgid ".frame outside of .ent"
+#: config/tc-arm.c:1151
+msgid "non-contiguous register range"
 msgstr ""
 
-#: config/tc-alpha.c:4595 ecoff.c:3211
-msgid "bad .frame directive"
+#: config/tc-arm.c:1199
+#, c-format
+msgid "ignoring attempt to redefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-alpha.c:4628
-msgid ".prologue directive without a preceding .ent directive"
+#: config/tc-arm.c:1204
+#, c-format
+msgid "ignoring redefinition of register alias '%s'"
 msgstr ""
 
-#: config/tc-alpha.c:4646
+#: config/tc-arm.c:1248
 #, c-format
-msgid "Invalid argument %d to .prologue."
+msgid "unknown register '%s' -- .req ignored"
 msgstr ""
 
-#: config/tc-alpha.c:4741
-msgid "ECOFF debugging is disabled."
+#: config/tc-arm.c:1291
+msgid "invalid syntax for .req directive"
 msgstr ""
 
-#: config/tc-alpha.c:4755
-msgid ".ent directive without matching .end"
+#: config/tc-arm.c:1317
+msgid "invalid syntax for .unreq directive"
 msgstr ""
 
-#: config/tc-alpha.c:4840
-msgid ".usepv directive has no name"
+#: config/tc-arm.c:1323
+#, c-format
+msgid "unknown register alias '%s'"
 msgstr ""
 
-#: config/tc-alpha.c:4851
-msgid ".usepv directive has no type"
+#: config/tc-arm.c:1325
+#, c-format
+msgid "ignoring attempt to undefine built-in register '%s'"
 msgstr ""
 
-#: config/tc-alpha.c:4866
-msgid "unknown argument for .usepv"
+#: config/tc-arm.c:1456
+msgid "selected processor does not support THUMB opcodes"
 msgstr ""
 
-#: config/tc-alpha.c:4900
-msgid "Unknown section directive"
+#: config/tc-arm.c:1470
+msgid "selected processor does not support ARM opcodes"
 msgstr ""
 
-#: config/tc-alpha.c:4936
-msgid ".ent directive has no symbol"
+#: config/tc-arm.c:1483
+#, c-format
+msgid "invalid instruction size selected (%d)"
 msgstr ""
 
-#: config/tc-alpha.c:4963
-msgid "Bad .frame directive 1./2. param"
+#: config/tc-arm.c:1515
+#, c-format
+msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
 msgstr ""
 
-#: config/tc-alpha.c:4975
-msgid "Bad .frame directive 3./4. param"
+#: config/tc-arm.c:1571
+#, c-format
+msgid "expected comma after name \"%s\""
 msgstr ""
 
-#: config/tc-alpha.c:5000
-msgid ".pdesc directive not in link (.link) section"
+#: config/tc-arm.c:1621 config/tc-m32r.c:589
+#, c-format
+msgid "symbol `%s' already defined"
 msgstr ""
 
-#: config/tc-alpha.c:5008
-msgid ".pdesc has no matching .ent"
+#: config/tc-arm.c:1655
+#, c-format
+msgid "unrecognized syntax mode \"%s\""
 msgstr ""
 
-#: config/tc-alpha.c:5019
-msgid ".pdesc directive has no entry symbol"
+#: config/tc-arm.c:1675
+#, c-format
+msgid "alignment too large: %d assumed"
 msgstr ""
 
-#: config/tc-alpha.c:5032
-msgid "No comma after .pdesc <entryname>"
+#: config/tc-arm.c:1678
+msgid "alignment negative. 0 assumed."
 msgstr ""
 
-#: config/tc-alpha.c:5055
-msgid "unknown procedure kind"
+#: config/tc-arm.c:1816
+msgid "literal pool overflow"
 msgstr ""
 
-#: config/tc-alpha.c:5148
-msgid ".name directive not in link (.link) section"
+#: config/tc-arm.c:1972 config/tc-arm.c:3888
+msgid "unrecognized relocation suffix"
 msgstr ""
 
-#: config/tc-alpha.c:5156
-msgid ".name directive has no symbol"
+#: config/tc-arm.c:1985
+msgid "(plt) is only valid on branch targets"
 msgstr ""
 
-#: config/tc-alpha.c:5190
-msgid "No symbol after .linkage"
+#: config/tc-arm.c:1991 config/tc-s390.c:1128 config/tc-s390.c:1742
+#: config/tc-xtensa.c:1601
+#, c-format
+msgid "%s relocations do not fit in %d bytes"
 msgstr ""
 
-#: config/tc-alpha.c:5218
-msgid "No symbol after .code_address"
+#: config/tc-arm.c:2039 dwarf2dbg.c:659
+msgid "expected 0 or 1"
 msgstr ""
 
-#: config/tc-alpha.c:5251
-msgid "Bad .mask directive"
+#: config/tc-arm.c:2043
+msgid "missing comma"
 msgstr ""
 
-#: config/tc-alpha.c:5272
-msgid "Bad .fmask directive"
+#: config/tc-arm.c:2098
+msgid "dupicate .handlerdata directive"
 msgstr ""
 
-#: config/tc-alpha.c:5440
-#, c-format
-msgid "Expected comma after name \"%s\""
+#: config/tc-arm.c:2169
+msgid "personality routine specified for cantunwind frame"
 msgstr ""
 
-#. *symbol_get_obj (symbolP) = (signed char) temp;
-#: config/tc-alpha.c:5451
-#, c-format
-msgid "unhandled: .proc %s,%d"
+#: config/tc-arm.c:2183
+msgid "duplicate .personalityindex directive"
 msgstr ""
 
-#: config/tc-alpha.c:5486
-#, c-format
-msgid "Tried to .set unrecognized mode `%s'"
+#: config/tc-arm.c:2190
+msgid "bad personality routine number"
 msgstr ""
 
-#. not fatal, but it might not work in the end
-#: config/tc-alpha.c:5503
-msgid "File overrides no-base-register option."
+#: config/tc-arm.c:2209
+msgid "duplicate .personality directive"
 msgstr ""
 
-#: config/tc-alpha.c:5520
-#, c-format
-msgid "Bad base register, using $%d."
+#: config/tc-arm.c:2232 config/tc-arm.c:2354
+msgid "expected register list"
 msgstr ""
 
-#: config/tc-alpha.c:5542
-#, c-format
-msgid "Alignment too large: %d. assumed"
+#: config/tc-arm.c:2310
+msgid "expected , <constant>"
 msgstr ""
 
-#: config/tc-alpha.c:5546 config/tc-d30v.c:2200
-msgid "Alignment negative: 0 assumed"
+#: config/tc-arm.c:2319
+msgid "number of registers must be in the range [1:4]"
 msgstr ""
 
-#: config/tc-alpha.c:5860
-#, c-format
-msgid "Chose GP value of %lx\n"
+#: config/tc-arm.c:2416 config/tc-arm.c:2549
+msgid "bad register range"
 msgstr ""
 
-#: config/tc-alpha.c:5876
-msgid "Bad .section directive: want a,s,w,x,M,S,G,T in string"
+#: config/tc-arm.c:2602
+msgid "register expected"
 msgstr ""
 
-#: config/tc-arc.c:1615 config/tc-arm.c:11416 config/tc-ip2k.c:219
-msgid "md_estimate_size_before_relax\n"
+#: config/tc-arm.c:2612
+msgid "FPA .unwind_save does not take a register list"
 msgstr ""
 
-#: config/tc-arc.c:1627
-msgid "md_convert_frag\n"
+#: config/tc-arm.c:2625
+msgid ".unwind_save does not support this kind of register"
 msgstr ""
 
-#. We can't actually support subtracting a symbol.
-#: config/tc-arc.c:1898 config/tc-arm.c:6617 config/tc-arm.c:9705
-#: config/tc-arm.c:9805 config/tc-avr.c:854 config/tc-cris.c:3123
-#: config/tc-d10v.c:1710 config/tc-d30v.c:1851 config/tc-mips.c:3630
-#: config/tc-mips.c:4695 config/tc-mips.c:5828 config/tc-mips.c:6517
-#: config/tc-msp430.c:1403 config/tc-ppc.c:5460 config/tc-v850.c:2356
-#: config/tc-xstormy16.c:483
-msgid "expression too complex"
+#: config/tc-arm.c:2650
+msgid "SP and PC not permitted in .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:763
-msgid "ARM register expected"
+#: config/tc-arm.c:2655
+msgid "unexpected .unwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:764 config/tc-arm.c:3174
-msgid "bad or missing co-processor number"
+#: config/tc-arm.c:2679
+msgid "stack increment must be multiple of 4"
 msgstr ""
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:765 config/tc-arm.c:3229
-msgid "co-processor register expected"
+#: config/tc-arm.c:2708
+msgid "expected <reg>, <reg>"
 msgstr ""
 
-#: config/tc-arm.c:766
-msgid "FPA register expected"
+#: config/tc-arm.c:2726
+msgid "register must be either sp or set by a previousunwind_movsp directive"
 msgstr ""
 
-#: config/tc-arm.c:767
-msgid "VFP single precision register expected"
+#: config/tc-arm.c:2762
+msgid "expected <offset>, <opcode>"
 msgstr ""
 
-#: config/tc-arm.c:768
-msgid "VFP double precision register expected"
+#: config/tc-arm.c:2774
+msgid "unwind opcode too long"
 msgstr ""
 
-#: config/tc-arm.c:769
-msgid "Maverick MVF register expected"
+#: config/tc-arm.c:2779
+msgid "invalid unwind opcode"
 msgstr ""
 
-#: config/tc-arm.c:770
-msgid "Maverick MVD register expected"
+#: config/tc-arm.c:2829
+msgid "expected numeric constant"
 msgstr ""
 
-#: config/tc-arm.c:771 config/tc-arm.c:772
-msgid "Maverick MVFX register expected"
+#: config/tc-arm.c:2838
+msgid "expected comma"
 msgstr ""
 
-#: config/tc-arm.c:773
-msgid "Maverick MVAX register expected"
+#: config/tc-arm.c:2877
+msgid "bad string constant"
 msgstr ""
 
-#: config/tc-arm.c:774
-msgid "Maverick DSPSC register expected"
+#: config/tc-arm.c:2881
+msgid "expected <tag> , <value>"
 msgstr ""
 
-#: config/tc-arm.c:775
-msgid "Intel Wireless MMX technology register expected"
+#: config/tc-arm.c:2957
+msgid "constant expression required"
 msgstr ""
 
-#: config/tc-arm.c:2309
-msgid "bad arguments to instruction"
+#: config/tc-arm.c:2963 config/tc-arm.c:6472 config/tc-arm.c:11799
+#: config/tc-arm.c:11824 config/tc-arm.c:11832 config/tc-z8k.c:1122
+#: config/tc-z8k.c:1132
+msgid "immediate value out of range"
 msgstr ""
 
-#: config/tc-arm.c:2310
-msgid "r15 not allowed here"
+#: config/tc-arm.c:3058
+msgid "invalid FPA immediate expression"
 msgstr ""
 
-#: config/tc-arm.c:2311
-msgid "instruction is not conditional"
+#: config/tc-arm.c:3108 config/tc-arm.c:3116
+msgid "shift expression expected"
 msgstr ""
 
-#: config/tc-arm.c:2312
-msgid "acc0 expected"
+#: config/tc-arm.c:3130
+msgid "'LSL' or 'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:2505
-msgid "literal pool overflow"
+#: config/tc-arm.c:3138
+msgid "'LSL' required"
 msgstr ""
 
-#: config/tc-arm.c:2647
-msgid "invalid syntax for .req directive"
+#: config/tc-arm.c:3146
+msgid "'ASR' required"
 msgstr ""
 
-#: config/tc-arm.c:2727
-#, c-format
-msgid "alignment too large: %d assumed"
+#: config/tc-arm.c:3218 config/tc-arm.c:4349 config/tc-v850.c:1844
+#: config/tc-v850.c:1865
+msgid "constant expression expected"
 msgstr ""
 
-#: config/tc-arm.c:2730
-msgid "alignment negative. 0 assumed."
+#: config/tc-arm.c:3225
+msgid "invalid rotation"
 msgstr ""
 
-#: config/tc-arm.c:2814
-#, c-format
-msgid "expected comma after name \"%s\""
+#: config/tc-arm.c:3340 config/tc-arm.c:3640
+msgid "']' expected"
 msgstr ""
 
-#: config/tc-arm.c:2864 config/tc-m32r.c:420
-#, c-format
-msgid "symbol `%s' already defined"
+#: config/tc-arm.c:3358
+msgid "'}' expected at end of 'option' field"
 msgstr ""
 
-#: config/tc-arm.c:2889
-msgid "selected processor does not support THUMB opcodes"
+#: config/tc-arm.c:3363
+msgid "cannot combine index with option"
 msgstr ""
 
-#: config/tc-arm.c:2902
-msgid "selected processor does not support ARM opcodes"
+#: config/tc-arm.c:3376
+msgid "cannot combine pre- and post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:2914
-#, c-format
-msgid "invalid instruction size selected (%d)"
+#: config/tc-arm.c:3472
+msgid "flag for {c}psr instruction expected"
 msgstr ""
 
-#: config/tc-arm.c:2949
-#, c-format
-msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
+#: config/tc-arm.c:3497
+msgid "unrecognized CPS flag"
 msgstr ""
 
-#: config/tc-arm.c:2960
-msgid "garbage following instruction"
+#: config/tc-arm.c:3504
+msgid "missing CPS flags"
 msgstr ""
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:3010
-#, c-format
-msgid "register expected, not '%.100s'"
+#: config/tc-arm.c:3527 config/tc-arm.c:3533
+msgid "valid endian specifiers are be or le"
 msgstr ""
 
-#. In the few cases where we might be able to accept
-#. something else this error can be overridden.
-#: config/tc-arm.c:3061
-#, c-format
-msgid "Intel Wireless MMX technology register expected, not '%.100s'"
+#: config/tc-arm.c:3555
+msgid "missing rotation field after comma"
 msgstr ""
 
-#. In the few cases where we might be able to accept
-#. something else this error can be overridden.
-#: config/tc-arm.c:3133
-msgid "flag for {c}psr instruction expected"
+#: config/tc-arm.c:3570
+msgid "rotation can only be 0, 8, 16, or 24"
 msgstr ""
 
-#: config/tc-arm.c:3167
-msgid "illegal co-processor number"
+#: config/tc-arm.c:3590
+msgid "condition required"
 msgstr ""
 
-#: config/tc-arm.c:3199 config/tc-arm.c:4778
-msgid "bad or missing expression"
+#: config/tc-arm.c:3632
+msgid "invalid shift"
 msgstr ""
 
-#: config/tc-arm.c:3205
-msgid "immediate co-processor expression too large"
+#: config/tc-arm.c:3929
+msgid "iWMMXt data or control register expected"
 msgstr ""
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:3252
-msgid "floating point register expected"
+#: config/tc-arm.c:4051
+msgid "garbage following instruction"
 msgstr ""
 
-#: config/tc-arm.c:3269 config/tc-arm.c:3414
-msgid "immediate expression expected"
+#: config/tc-arm.c:4185
+msgid "instruction does not accept preindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:3284
-msgid "co-processor address must be word aligned"
+#. unindexed - only for coprocessor
+#: config/tc-arm.c:4201 config/tc-arm.c:5857
+msgid "instruction does not accept unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:3290 config/tc-arm.c:3429
-msgid "offset too large"
+#: config/tc-arm.c:4209
+msgid "destination register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:3339 config/tc-arm.c:3477
-msgid "pc may not be used in post-increment"
+#: config/tc-arm.c:4210
+msgid "source register same as write-back base"
 msgstr ""
 
-#: config/tc-arm.c:3355 config/tc-arm.c:3493 config/tc-arm.c:3938
-#: config/tc-arm.c:5197 config/tc-arm.c:6064 config/tc-arm.c:6398
-msgid "pre-indexed expression expected"
+#: config/tc-arm.c:4256
+msgid "instruction does not accept scaled register index"
 msgstr ""
 
-#: config/tc-arm.c:3368 config/tc-arm.c:3506 config/tc-arm.c:3951
-#: config/tc-arm.c:5208 config/tc-arm.c:6076 config/tc-arm.c:6410
-#: config/tc-arm.c:6784 config/tc-arm.c:9448 config/tc-arm.c:9463
-msgid "missing ]"
+#: config/tc-arm.c:4295
+msgid "instruction does not support unindexed addressing"
 msgstr ""
 
-#: config/tc-arm.c:3378 config/tc-arm.c:3516
+#: config/tc-arm.c:4310
 msgid "pc may not be used with write-back"
 msgstr ""
 
-#: config/tc-arm.c:3568
-msgid "comma expected after register name"
+#: config/tc-arm.c:4315
+msgid "instruction does not support writeback"
 msgstr ""
 
-#: config/tc-arm.c:3587
-msgid "CPSR or SPSR expected"
+#: config/tc-arm.c:4344
+msgid "invalid pseudo operation"
 msgstr ""
 
-#: config/tc-arm.c:3613
-msgid "comma missing after psr flags"
+#: config/tc-arm.c:4390
+msgid "literal pool insertion failed"
 msgstr ""
 
-#: config/tc-arm.c:3629 config/tc-arm.c:3639
-msgid "only a register or immediate value can follow a psr flag"
+#: config/tc-arm.c:4448
+msgid "Rn must not overlap other operands"
 msgstr ""
 
-#: config/tc-arm.c:3650
-msgid "immediate value cannot be used to set this field"
+#: config/tc-arm.c:4534 config/tc-arm.c:4553 config/tc-arm.c:4566
+#: config/tc-arm.c:6360 config/tc-arm.c:6380 config/tc-arm.c:6394
+msgid "bit-field extends past end of register"
 msgstr ""
 
-#: config/tc-arm.c:3668 config/tc-arm.c:5424 config/tc-arm.c:5704
-#: config/tc-arm.c:5724 config/tc-i960.c:1935
-msgid "invalid constant"
+#: config/tc-arm.c:4595
+msgid "the only suffix valid here is '(plt)'"
 msgstr ""
 
-#: config/tc-arm.c:3716
-msgid "rdhi, rdlo and rm must all be different"
+#: config/tc-arm.c:4627
+msgid "use of r15 in blx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:3770
-msgid "rd and rm should be different in mul"
+#: config/tc-arm.c:4645
+msgid "use of r15 in bx in ARM mode is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:3824
-msgid "rd and rm should be different in mla"
+#: config/tc-arm.c:4657 config/tc-arm.c:6508
+msgid "use of r15 in bxj is not really useful"
 msgstr ""
 
-#: config/tc-arm.c:3872
-#, c-format
-msgid "acc0 expected, not '%.100s'"
+#: config/tc-arm.c:4761 config/tc-arm.c:4770
+msgid "writeback of base register is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4050
-msgid "rdhi and rdlo must be different"
+#: config/tc-arm.c:4764
+msgid "writeback of base register when in register list is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:4158
-msgid "Warning: instruction unpredictable when using r15"
+#: config/tc-arm.c:4774
+msgid "if writeback register is in list, it must be the lowest reg in the list"
 msgstr ""
 
-#: config/tc-arm.c:4373
-msgid "use of r15 in bxj is not really useful"
+#: config/tc-arm.c:4789
+msgid "first destination register must be even"
 msgstr ""
 
-#: config/tc-arm.c:4400 config/tc-arm.c:4585 config/tc-arm.c:5445 expr.c:1318
-#: read.c:2206
-msgid "bad expression"
+#: config/tc-arm.c:4792 config/tc-arm.c:4849
+msgid "can only load two consecutive registers"
 msgstr ""
 
-#: config/tc-arm.c:4409 config/tc-arm.c:4594 config/tc-arm.c:4786
-#: config/tc-arm.c:8389 config/tc-arm.c:8424 config/tc-arm.c:8434
-#: config/tc-z8k.c:1161 config/tc-z8k.c:1173
-msgid "immediate value out of range"
+#. If op 1 were present and equal to PC, this function wouldn't
+#. have been called in the first place.
+#. If op 2 were present and equal to PC, this function wouldn't
+#. have been called in the first place.
+#: config/tc-arm.c:4793 config/tc-arm.c:4852 config/tc-arm.c:5299
+#: config/tc-arm.c:6886
+msgid "r14 not allowed here"
 msgstr ""
 
-#: config/tc-arm.c:4833
-msgid "only r15 allowed here"
+#: config/tc-arm.c:4794
+msgid "'[' expected"
 msgstr ""
 
-#: config/tc-arm.c:5160
-msgid "'[' expected after PLD mnemonic"
+#: config/tc-arm.c:4807
+msgid "base register written back, and overlaps second destination register"
 msgstr ""
 
-#: config/tc-arm.c:5182
-msgid "post-indexed expression used in preload instruction"
+#: config/tc-arm.c:4815
+msgid "index register overlaps destination register"
 msgstr ""
 
-#: config/tc-arm.c:5187 config/tc-arm.c:5217
-msgid "writeback used in preload instruction"
+#: config/tc-arm.c:4829 config/tc-arm.c:5272 config/tc-arm.c:6706
+#: config/tc-arm.c:7581
+msgid "instruction does not accept this addressing mode"
 msgstr ""
 
-#: config/tc-arm.c:5259
-msgid "destination register must be even"
+#: config/tc-arm.c:4835 config/tc-arm.c:5281
+msgid "offset must be zero in ARM encoding"
 msgstr ""
 
-#: config/tc-arm.c:5265
-msgid "r14 not allowed here"
+#: config/tc-arm.c:4846 config/tc-arm.c:5293
+msgid "even register required"
 msgstr ""
 
-#: config/tc-arm.c:5272
-msgid "pre/post-indexing used when modified address register is destination"
+#: config/tc-arm.c:4877 config/tc-arm.c:4908
+msgid "this instruction requires a post-indexed address"
 msgstr ""
 
-#: config/tc-arm.c:5282
-msgid "ldrd destination registers must not overlap index register"
+#: config/tc-arm.c:4935
+msgid "rd and rm should be different in mla"
 msgstr ""
 
-#: config/tc-arm.c:5408
-msgid "bad_segment"
+#: config/tc-arm.c:4967 config/tc-arm.c:7121
+msgid "'CPSR' or 'SPSR' expected"
 msgstr ""
 
-#: config/tc-arm.c:5468 config/tc-arm.c:5479
-msgid "shift expression expected"
+#: config/tc-arm.c:5000
+msgid "rd and rm should be different in mul"
 msgstr ""
 
-#: config/tc-arm.c:5503
-msgid "shift requires register or #expression"
+#: config/tc-arm.c:5021
+msgid "rdhi, rdlo and rm must all be different"
 msgstr ""
 
-#: config/tc-arm.c:5504
-msgid "shift requires #expression"
+#: config/tc-arm.c:5083
+msgid "'[' expected after PLD mnemonic"
 msgstr ""
 
-#: config/tc-arm.c:5534
-msgid "shift of 0 ignored."
+#: config/tc-arm.c:5085
+msgid "post-indexed expression used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5540
-msgid "invalid immediate shift"
+#: config/tc-arm.c:5087
+msgid "writeback used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5695 config/tc-arm.c:6112 config/tc-arm.c:6447
-#: config/tc-arm.c:7081 config/tc-v850.c:1907 config/tc-v850.c:1928
-msgid "constant expression expected"
+#: config/tc-arm.c:5089
+msgid "unindexed addressing used in preload instruction"
 msgstr ""
 
-#: config/tc-arm.c:5737
-msgid "register or shift expression expected"
+#: config/tc-arm.c:5188 config/tc-arm.c:7492
+msgid "source1 and dest must be same register"
 msgstr ""
 
-#: config/tc-arm.c:5790
-msgid "invalid floating point immediate expression"
+#: config/tc-arm.c:5238 config/tc-arm.c:7178
+msgid "rdhi and rdlo must be different"
 msgstr ""
 
-#: config/tc-arm.c:5794
-msgid "floating point register or immediate expression expected"
+#: config/tc-arm.c:5296
+msgid "can only store two consecutive registers"
 msgstr ""
 
-#: config/tc-arm.c:5948 config/tc-arm.c:6278
-msgid "address offset too large"
+#: config/tc-arm.c:5391 config/tc-arm.c:5408
+msgid "only two consecutive VFP SP registers allowed here"
 msgstr ""
 
-#: config/tc-arm.c:6006 config/tc-arm.c:6196 config/tc-arm.c:6338
-msgid "address expected"
+#: config/tc-arm.c:5436 config/tc-arm.c:5451
+msgid "this addressing mode requires base-register writeback"
 msgstr ""
 
-#: config/tc-arm.c:6036 config/tc-arm.c:6048 config/tc-arm.c:6085
-#: config/tc-arm.c:6214 config/tc-arm.c:6368 config/tc-arm.c:6382
-#: config/tc-arm.c:6419
-#, c-format
-msgid "%s register same as write-back base"
+#: config/tc-arm.c:5529
+msgid "this instruction does not support indexing"
 msgstr ""
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
-msgid "destination"
+#: config/tc-arm.c:5552
+msgid "only r15 allowed here"
 msgstr ""
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
-msgid "source"
+#: config/tc-arm.c:5757
+msgid "shift by register not allowed in thumb mode"
 msgstr ""
 
-#: config/tc-arm.c:6097 config/tc-arm.c:6431 config/tc-arm.c:8695
-msgid "invalid pseudo operation"
+#: config/tc-arm.c:5769 config/tc-arm.c:11339
+msgid "shift expression is too large"
 msgstr ""
 
-#: config/tc-arm.c:6149 config/tc-arm.c:6482
-msgid "literal pool insertion failed"
+#: config/tc-arm.c:5795
+msgid "Thumb does not support the ldr =N pseudo-operation"
 msgstr ""
 
-#: config/tc-arm.c:6244 config/tc-arm.c:6250
-msgid "post-indexed expression expected"
+#: config/tc-arm.c:5800
+msgid "cannot use register index with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:6548
-msgid "bad range in register list"
+#: config/tc-arm.c:5801
+msgid "cannot use register index with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:6556 config/tc-arm.c:6565 config/tc-arm.c:6607
-#, c-format
-msgid "Warning: duplicated register (r%d) in register list"
+#: config/tc-arm.c:5803
+msgid "Thumb does not support negative register indexing"
 msgstr ""
 
-#: config/tc-arm.c:6568
-msgid "Warning: register range not in ascending order"
+#: config/tc-arm.c:5805
+msgid "Thumb does not support register post-indexing"
 msgstr ""
 
-#: config/tc-arm.c:6580
-msgid "missing `}'"
+#: config/tc-arm.c:5807
+msgid "Thumb does not support register indexing with writeback"
 msgstr ""
 
-#: config/tc-arm.c:6596
-msgid "invalid register mask"
+#: config/tc-arm.c:5809
+msgid "Thumb supports only LSL in shifted register indexing"
 msgstr ""
 
-#: config/tc-arm.c:6655
-msgid "r15 not allowed as base register"
+#: config/tc-arm.c:5818
+msgid "shift out of range"
 msgstr ""
 
-#: config/tc-arm.c:6689 config/tc-arm.c:6698
-msgid "writeback of base register is UNPREDICTABLE"
+#: config/tc-arm.c:5826
+msgid "cannot use writeback with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:6692
-msgid "writeback of base register when in register list is UNPREDICTABLE"
+#: config/tc-arm.c:5828
+msgid "cannot use writeback with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:6702
-msgid "if writeback register is in list, it must be the lowest reg in the list"
+#: config/tc-arm.c:5847
+msgid "cannot use post-indexing with PC-relative addressing"
 msgstr ""
 
-#: config/tc-arm.c:6744 config/tc-arm.c:6758
-msgid "r15 not allowed in swap"
+#: config/tc-arm.c:5848
+msgid "cannot use post-indexing with this instruction"
 msgstr ""
 
-#: config/tc-arm.c:6853
-msgid "use of r15 in bx in ARM mode is not really useful"
+#: config/tc-arm.c:5975
+msgid "PC not allowed as destination"
 msgstr ""
 
-#: config/tc-arm.c:7087
-msgid "constant value required for number of registers"
-msgstr ""
-
-#: config/tc-arm.c:7095
-msgid "number of registers must be in the range [1:4]"
+#: config/tc-arm.c:6093 config/tc-arm.c:6234 config/tc-arm.c:6326
+#: config/tc-arm.c:7092
+msgid "shift must be constant"
 msgstr ""
 
-#: config/tc-arm.c:7156
-msgid "r15 not allowed as base register with write-back"
+#: config/tc-arm.c:6120 config/tc-arm.c:6249 config/tc-arm.c:6341
+#: config/tc-arm.c:7105
+msgid "unshifted register required"
 msgstr ""
 
-#: config/tc-arm.c:7538
-msgid "only two consecutive VFP SP registers allowed here"
+#: config/tc-arm.c:6135 config/tc-arm.c:6352 config/tc-arm.c:7165
+msgid "dest must overlap one source register"
 msgstr ""
 
-#: config/tc-arm.c:7706
-msgid "VFP system register expected"
+#: config/tc-arm.c:6252
+msgid "dest and source1 must be the same register"
 msgstr ""
 
-#: config/tc-arm.c:7844 config/tc-arm.c:7883 config/tc-arm.c:7896
-#: config/tc-arm.c:7957 config/tc-arm.c:7996 config/tc-arm.c:8009
-#: config/tc-h8300.c:1035 config/tc-mips.c:9723 config/tc-mips.c:9753
-msgid "invalid register list"
+#: config/tc-arm.c:6537
+msgid "Thumb does not support the 2-argument form of this instruction"
 msgstr ""
 
-#: config/tc-arm.c:7850 config/tc-arm.c:7963
-msgid "register list not in ascending order"
+#: config/tc-arm.c:6616
+msgid "Thumb load/store multiple does not support {reglist}^"
 msgstr ""
 
-#: config/tc-arm.c:7875 config/tc-arm.c:7988
-msgid "register range not in ascending order"
+#: config/tc-arm.c:6633 config/tc-arm.c:6649 config/tc-arm.c:6680
+#, c-format
+msgid "value stored for r%d is UNPREDICTABLE"
 msgstr ""
 
-#: config/tc-arm.c:7913 config/tc-arm.c:8026
-msgid "non-contiguous register range"
+#: config/tc-arm.c:6643
+msgid "SP should not be in register list"
 msgstr ""
 
-#: config/tc-arm.c:8056 config/tc-arm.c:8093
-msgid "this addressing mode requires base-register writeback"
+#: config/tc-arm.c:6647
+msgid "PC should not be in register list"
 msgstr ""
 
-#: config/tc-arm.c:8253
-msgid "lo register required"
+#: config/tc-arm.c:6656 config/tc-arm.c:7311
+msgid "LR and PC should not both be in register list"
 msgstr ""
 
-#: config/tc-arm.c:8261
-msgid "hi register required"
+#: config/tc-arm.c:6659
+msgid "base register should not be in register list when written back"
 msgstr ""
 
-#: config/tc-arm.c:8331 config/tc-arm.c:9537
-msgid "dest and source1 must be the same register"
+#: config/tc-arm.c:6677 config/tc-arm.c:6687
+msgid "this instruction will write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:8338
-msgid "subtract valid only on lo regs"
+#: config/tc-arm.c:6690
+msgid "this instruction will not write back the base register"
 msgstr ""
 
-#: config/tc-arm.c:8362
-msgid "invalid Hi register with immediate"
+#: config/tc-arm.c:6719
+msgid "r14 not allowed as first register when second register is omitted"
 msgstr ""
 
-#: config/tc-arm.c:8402
-msgid "invalid immediate value for stack adjust"
+#: config/tc-arm.c:6809 config/tc-arm.c:6822 config/tc-arm.c:6858
+msgid "Thumb does not support this addressing mode"
 msgstr ""
 
-#: config/tc-arm.c:8413
-msgid "invalid immediate for address calculation"
+#: config/tc-arm.c:6826
+msgid "byte or halfword not valid for base register"
 msgstr ""
 
-#: config/tc-arm.c:8500
-msgid "source1 and dest must be same register"
+#: config/tc-arm.c:6829
+msgid "r15 based store not allowed"
 msgstr ""
 
-#: config/tc-arm.c:8534
-msgid "invalid immediate for shift"
+#: config/tc-arm.c:6831
+msgid "invalid base register for register offset"
 msgstr ""
 
-#: config/tc-arm.c:8613
+#: config/tc-arm.c:7032
 msgid "only lo regs allowed with immediate"
 msgstr ""
 
-#: config/tc-arm.c:8632
-msgid "invalid immediate"
+#: config/tc-arm.c:7130
+msgid "Thumb encoding does not support an immediate here"
 msgstr ""
 
-#: config/tc-arm.c:8686
-msgid "expected ']'"
+#: config/tc-arm.c:7200
+msgid "Thumb does not support NOP with hints"
 msgstr ""
 
-#: config/tc-arm.c:8759
-msgid "byte or halfword not valid for base register"
+#: config/tc-arm.c:7282
+msgid "push/pop do not support {reglist}^"
 msgstr ""
 
-#: config/tc-arm.c:8764
-msgid "r15 based store not allowed"
+#: config/tc-arm.c:7301
+msgid "SP not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:8769
-msgid "invalid base register for register offset"
+#: config/tc-arm.c:7305
+msgid "PC not allowed in register list"
 msgstr ""
 
-#: config/tc-arm.c:8787 config/tc-arm.c:8822
-msgid "invalid offset"
+#: config/tc-arm.c:7328
+msgid "invalid register list to push/pop instruction"
 msgstr ""
 
-#: config/tc-arm.c:8798
-msgid "invalid base register in load/store"
+#: config/tc-arm.c:7513
+msgid "ror #imm not supported"
 msgstr ""
 
-#: config/tc-arm.c:9341
-msgid "expecting immediate, 7bit operand"
+#: config/tc-arm.c:7638
+msgid "Thumb encoding does not support rotation"
 msgstr ""
 
-#: config/tc-arm.c:9356
-msgid "immediate out of range"
+#: config/tc-arm.c:7656
+msgid "PC is not a valid index register"
 msgstr ""
 
-#: config/tc-arm.c:9399
-msgid "offset expected"
+#: config/tc-arm.c:7658
+msgid "instruction does not allow shifted index"
 msgstr ""
 
-#: config/tc-arm.c:9408 config/tc-pj.c:537 config/tc-sh.c:3593
-msgid "offset out of range"
+#: config/tc-arm.c:7660
+msgid "instruction requires shifted index"
 msgstr ""
 
-#: config/tc-arm.c:9545
-msgid "Rs and Rd must be different in MUL"
+#: config/tc-arm.c:7943 config/tc-arm.c:8015
+msgid "conditional infixes are deprecated in unified syntax"
 msgstr ""
 
-#: config/tc-arm.c:9689
-msgid ""
-"inserted missing '!': load/store multiple always writes back base register"
+#: config/tc-arm.c:8047
+#, c-format
+msgid "bad instruction `%s'"
 msgstr ""
 
-#: config/tc-arm.c:9711
-msgid "only lo-regs valid in load/store multiple"
+#: config/tc-arm.c:8063 config/tc-arm.c:8126
+#, c-format
+msgid "selected processor does not support `%s'"
 msgstr ""
 
-#: config/tc-arm.c:9757
-msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
+#: config/tc-arm.c:8069
+msgid "Thumb does not support conditional execution"
 msgstr ""
 
-#: config/tc-arm.c:9821
-msgid "invalid register list to push/pop instruction"
+#: config/tc-arm.c:8080
+msgid "incorrect condition in IT block"
 msgstr ""
 
-#: config/tc-arm.c:9933 config/tc-arm.c:10159
-msgid "virtual memory exhausted"
+#: config/tc-arm.c:8088
+msgid "thumb conditional instrunction not in IT block"
 msgstr ""
 
-#: config/tc-arm.c:10014
+#: config/tc-arm.c:8108
 #, c-format
-msgid "register '%s' does not exist\n"
+msgid "cannot honor width suffix -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:10018
+#: config/tc-arm.c:8131
 #, c-format
-msgid ""
-"ignoring redefinition of register alias '%s' to non-existant register '%s'"
+msgid "width suffixes are invalid in ARM mode -- `%s'"
 msgstr ""
 
-#: config/tc-arm.c:10027
-#, c-format
-msgid "ignoring redefinition of register alias '%s'"
+#: config/tc-arm.c:10340
+msgid "alignments greater than 32 bytes not supported in .text sections."
 msgstr ""
 
-#: config/tc-arm.c:10033
-msgid "ignoring incomplete .req pseuso op"
+#: config/tc-arm.c:10634
+msgid "handerdata in cantunwind frame"
 msgstr ""
 
-#: config/tc-arm.c:10183
-msgid "use of old and new-style options to set CPU type"
+#: config/tc-arm.c:10651
+msgid "too many unwind opcodes for personality routine 0"
 msgstr ""
 
-#: config/tc-arm.c:10193
-msgid "use of old and new-style options to set FPU type"
+#: config/tc-arm.c:10683
+msgid "too many unwind opcodes"
 msgstr ""
 
-#: config/tc-arm.c:10473
-msgid "bad call to MD_ATOF()"
+#: config/tc-arm.c:11085 config/tc-arm.c:11365
+#, c-format
+msgid "undefined symbol %s used as an immediate value"
 msgstr ""
 
-#: config/tc-arm.c:10703
+#: config/tc-arm.c:11099 config/tc-arm.c:11394
 #, c-format
 msgid "invalid constant (%lx) after fixup"
 msgstr ""
 
-#: config/tc-arm.c:10741
+#: config/tc-arm.c:11136
 #, c-format
 msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
 msgstr ""
 
-#: config/tc-arm.c:10771
-#, c-format
-msgid "bad immediate value for offset (%ld)"
+#: config/tc-arm.c:11168 config/tc-arm.c:11193
+msgid "invalid literal constant: pool needs to be closer"
 msgstr ""
 
-#: config/tc-arm.c:10793 config/tc-arm.c:10815
-msgid "invalid literal constant: pool needs to be closer"
+#: config/tc-arm.c:11171 config/tc-arm.c:11209
+#, c-format
+msgid "bad immediate value for offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:10795
+#: config/tc-arm.c:11195
 #, c-format
 msgid "bad immediate value for half-word offset (%ld)"
 msgstr ""
 
-#: config/tc-arm.c:10832
-msgid "shift expression is too large"
+#: config/tc-arm.c:11250
+msgid "offset not a multiple of 4"
 msgstr ""
 
-#: config/tc-arm.c:10851 config/tc-arm.c:10860
+#: config/tc-arm.c:11257 config/tc-arm.c:11272 config/tc-arm.c:11287
+#: config/tc-arm.c:11298 config/tc-arm.c:11321 config/tc-pj.c:499
+#: config/tc-sh.c:4084
+msgid "offset out of range"
+msgstr ""
+
+#: config/tc-arm.c:11410
+msgid "invalid smc expression"
+msgstr ""
+
+#: config/tc-arm.c:11421 config/tc-arm.c:11430
 msgid "invalid swi expression"
 msgstr ""
 
-#: config/tc-arm.c:10870
+#: config/tc-arm.c:11440
 msgid "invalid expression in load/store multiple"
 msgstr ""
 
-#: config/tc-arm.c:10923
-msgid "GAS can't handle same-section branch dest >= 0x04000000"
+#: config/tc-arm.c:11455
+msgid "misaligned branch destination"
 msgstr ""
 
-#: config/tc-arm.c:10932
-msgid "out of range branch"
+#: config/tc-arm.c:11459 config/tc-arm.c:11479 config/tc-arm.c:11497
+#: config/tc-arm.c:11510 config/tc-arm.c:11523 config/tc-arm.c:11562
+#: config/tc-arm.c:11587
+msgid "branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:10965 config/tc-arm.c:10981
-msgid "branch out of range"
+#: config/tc-arm.c:11475
+msgid "misaligned BLX destination"
 msgstr ""
 
-#: config/tc-arm.c:11005
-msgid "branch with link out of range"
+#: config/tc-arm.c:11536
+msgid "conditional branch out of range"
 msgstr ""
 
-#: config/tc-arm.c:11074
-msgid "illegal value for co-processor offset"
+#: config/tc-arm.c:11657
+msgid "rel31 relocation overflow"
 msgstr ""
 
-#: config/tc-arm.c:11086
-msgid "Illegal value for co-processor offset"
+#: config/tc-arm.c:11669 config/tc-arm.c:11694
+msgid "co-processor offset out of range"
 msgstr ""
 
-#: config/tc-arm.c:11110
+#: config/tc-arm.c:11710
 #, c-format
-msgid "invalid offset, target not word aligned (0x%08X)"
+msgid "invalid offset, target not word aligned (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11116 config/tc-arm.c:11126 config/tc-arm.c:11134
-#: config/tc-arm.c:11142 config/tc-arm.c:11150
+#: config/tc-arm.c:11716 config/tc-arm.c:11725 config/tc-arm.c:11733
+#: config/tc-arm.c:11741 config/tc-arm.c:11749
 #, c-format
 msgid "invalid offset, value too big (0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11190
+#: config/tc-arm.c:11790
+msgid "invalid Hi register with immediate"
+msgstr ""
+
+#: config/tc-arm.c:11806
 msgid "invalid immediate for stack address calculation"
 msgstr ""
 
-#: config/tc-arm.c:11199
+#: config/tc-arm.c:11814
 #, c-format
 msgid "invalid immediate for address calculation (value = 0x%08lX)"
 msgstr ""
 
-#: config/tc-arm.c:11209
-msgid "invalid 8bit immediate"
-msgstr ""
-
-#: config/tc-arm.c:11217
-msgid "invalid 3bit immediate"
-msgstr ""
-
-#: config/tc-arm.c:11233
+#: config/tc-arm.c:11844
 #, c-format
 msgid "invalid immediate: %ld is too large"
 msgstr ""
 
-#: config/tc-arm.c:11248
+#: config/tc-arm.c:11856
 #, c-format
-msgid "illegal Thumb shift value: %ld"
+msgid "invalid shift value: %ld"
 msgstr ""
 
-#: config/tc-arm.c:11262
+#: config/tc-arm.c:11875
 #, c-format
 msgid "bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-arm.c:11333
+#: config/tc-arm.c:11943
 msgid "literal referenced across section boundary"
 msgstr ""
 
-#: config/tc-arm.c:11346
+#: config/tc-arm.c:11973
 msgid "internal relocation (type: IMMEDIATE) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:11351
+#: config/tc-arm.c:11978
 msgid "ADRL used for a symbol not defined in the same file"
 msgstr ""
 
-#: config/tc-arm.c:11356
+#: config/tc-arm.c:11987
+#, c-format
+msgid "undefined local label `%s'"
+msgstr ""
+
+#: config/tc-arm.c:11993
 msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
 msgstr ""
 
-#: config/tc-arm.c:11374 config/tc-cris.c:3063 config/tc-mcore.c:2052
-#: config/tc-mmix.c:2867 config/tc-ns32k.c:2396
+#: config/tc-arm.c:12014 config/tc-cris.c:3869 config/tc-mcore.c:1995
+#: config/tc-mmix.c:2888 config/tc-ns32k.c:2284
 msgid "<unknown>"
 msgstr ""
 
-#: config/tc-arm.c:11377 config/tc-arm.c:11398
+#: config/tc-arm.c:12017 config/tc-arm.c:12038
 #, c-format
 msgid "cannot represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-arm.c:11494
+#: config/tc-arm.c:12254
 #, c-format
-msgid "no operator -- statement `%s'\n"
+msgid "%s: unexpected function type: %d"
 msgstr ""
 
-#: config/tc-arm.c:11512 config/tc-arm.c:11537
-#, c-format
-msgid "selected processor does not support `%s'"
+#: config/tc-arm.c:12331
+msgid "virtual memory exhausted"
 msgstr ""
 
-#: config/tc-arm.c:11554
-#, c-format
-msgid "bad instruction `%s'"
+#: config/tc-arm.c:12357
+msgid "use of old and new-style options to set CPU type"
+msgstr ""
+
+#: config/tc-arm.c:12367
+msgid "use of old and new-style options to set FPU type"
+msgstr ""
+
+#: config/tc-arm.c:12441
+msgid "hard-float conflicts with specified fpu"
 msgstr ""
 
-#: config/tc-arm.c:11655
+#: config/tc-arm.c:12633
 msgid "generate PIC code"
 msgstr ""
 
-#: config/tc-arm.c:11656
+#: config/tc-arm.c:12634
 msgid "assemble Thumb code"
 msgstr ""
 
-#: config/tc-arm.c:11657
+#: config/tc-arm.c:12635
 msgid "support ARM/Thumb interworking"
 msgstr ""
 
-#: config/tc-arm.c:11659
-msgid "use old ABI (ELF only)"
-msgstr ""
-
-#: config/tc-arm.c:11660
+#: config/tc-arm.c:12637
 msgid "code uses 32-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:11661
+#: config/tc-arm.c:12638
 msgid "code uses 26-bit program counter"
 msgstr ""
 
-#: config/tc-arm.c:11662
+#: config/tc-arm.c:12639
 msgid "floating point args are in fp regs"
 msgstr ""
 
-#: config/tc-arm.c:11664
+#: config/tc-arm.c:12641
 msgid "re-entrant code"
 msgstr ""
 
-#: config/tc-arm.c:11665
+#: config/tc-arm.c:12642
 msgid "code is ATPCS conformant"
 msgstr ""
 
-#: config/tc-arm.c:11666
+#: config/tc-arm.c:12643
 msgid "assemble for big-endian"
 msgstr ""
 
-#: config/tc-arm.c:11667
+#: config/tc-arm.c:12644
 msgid "assemble for little-endian"
 msgstr ""
 
 #. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:11671
+#: config/tc-arm.c:12648
 msgid "use frame pointer"
 msgstr ""
 
-#: config/tc-arm.c:11672
+#: config/tc-arm.c:12649
 msgid "use stack size checking"
 msgstr ""
 
 #. DON'T add any new processors to this list -- we want the whole list
 #. to go away...  Add them to the processors table instead.
-#: config/tc-arm.c:11676 config/tc-arm.c:11677
+#: config/tc-arm.c:12653 config/tc-arm.c:12654
 msgid "use -mcpu=arm1"
 msgstr ""
 
-#: config/tc-arm.c:11678 config/tc-arm.c:11679
+#: config/tc-arm.c:12655 config/tc-arm.c:12656
 msgid "use -mcpu=arm2"
 msgstr ""
 
-#: config/tc-arm.c:11680 config/tc-arm.c:11681
+#: config/tc-arm.c:12657 config/tc-arm.c:12658
 msgid "use -mcpu=arm250"
 msgstr ""
 
-#: config/tc-arm.c:11682 config/tc-arm.c:11683
+#: config/tc-arm.c:12659 config/tc-arm.c:12660
 msgid "use -mcpu=arm3"
 msgstr ""
 
-#: config/tc-arm.c:11684 config/tc-arm.c:11685
+#: config/tc-arm.c:12661 config/tc-arm.c:12662
 msgid "use -mcpu=arm6"
 msgstr ""
 
-#: config/tc-arm.c:11686 config/tc-arm.c:11687
+#: config/tc-arm.c:12663 config/tc-arm.c:12664
 msgid "use -mcpu=arm600"
 msgstr ""
 
-#: config/tc-arm.c:11688 config/tc-arm.c:11689
+#: config/tc-arm.c:12665 config/tc-arm.c:12666
 msgid "use -mcpu=arm610"
 msgstr ""
 
-#: config/tc-arm.c:11690 config/tc-arm.c:11691
+#: config/tc-arm.c:12667 config/tc-arm.c:12668
 msgid "use -mcpu=arm620"
 msgstr ""
 
-#: config/tc-arm.c:11692 config/tc-arm.c:11693
+#: config/tc-arm.c:12669 config/tc-arm.c:12670
 msgid "use -mcpu=arm7"
 msgstr ""
 
-#: config/tc-arm.c:11694 config/tc-arm.c:11695
+#: config/tc-arm.c:12671 config/tc-arm.c:12672
 msgid "use -mcpu=arm70"
 msgstr ""
 
-#: config/tc-arm.c:11696 config/tc-arm.c:11697
+#: config/tc-arm.c:12673 config/tc-arm.c:12674
 msgid "use -mcpu=arm700"
 msgstr ""
 
-#: config/tc-arm.c:11698 config/tc-arm.c:11699
+#: config/tc-arm.c:12675 config/tc-arm.c:12676
 msgid "use -mcpu=arm700i"
 msgstr ""
 
-#: config/tc-arm.c:11700 config/tc-arm.c:11701
+#: config/tc-arm.c:12677 config/tc-arm.c:12678
 msgid "use -mcpu=arm710"
 msgstr ""
 
-#: config/tc-arm.c:11702 config/tc-arm.c:11703
+#: config/tc-arm.c:12679 config/tc-arm.c:12680
 msgid "use -mcpu=arm710c"
 msgstr ""
 
-#: config/tc-arm.c:11704 config/tc-arm.c:11705
+#: config/tc-arm.c:12681 config/tc-arm.c:12682
 msgid "use -mcpu=arm720"
 msgstr ""
 
-#: config/tc-arm.c:11706 config/tc-arm.c:11707
+#: config/tc-arm.c:12683 config/tc-arm.c:12684
 msgid "use -mcpu=arm7d"
 msgstr ""
 
-#: config/tc-arm.c:11708 config/tc-arm.c:11709
+#: config/tc-arm.c:12685 config/tc-arm.c:12686
 msgid "use -mcpu=arm7di"
 msgstr ""
 
-#: config/tc-arm.c:11710 config/tc-arm.c:11711
+#: config/tc-arm.c:12687 config/tc-arm.c:12688
 msgid "use -mcpu=arm7m"
 msgstr ""
 
-#: config/tc-arm.c:11712 config/tc-arm.c:11713
+#: config/tc-arm.c:12689 config/tc-arm.c:12690
 msgid "use -mcpu=arm7dm"
 msgstr ""
 
-#: config/tc-arm.c:11714 config/tc-arm.c:11715
+#: config/tc-arm.c:12691 config/tc-arm.c:12692
 msgid "use -mcpu=arm7dmi"
 msgstr ""
 
-#: config/tc-arm.c:11716 config/tc-arm.c:11717
+#: config/tc-arm.c:12693 config/tc-arm.c:12694
 msgid "use -mcpu=arm7100"
 msgstr ""
 
-#: config/tc-arm.c:11718 config/tc-arm.c:11719
+#: config/tc-arm.c:12695 config/tc-arm.c:12696
 msgid "use -mcpu=arm7500"
 msgstr ""
 
-#: config/tc-arm.c:11720 config/tc-arm.c:11721
+#: config/tc-arm.c:12697 config/tc-arm.c:12698
 msgid "use -mcpu=arm7500fe"
 msgstr ""
 
-#: config/tc-arm.c:11722 config/tc-arm.c:11723 config/tc-arm.c:11724
-#: config/tc-arm.c:11725
+#: config/tc-arm.c:12699 config/tc-arm.c:12700 config/tc-arm.c:12701
+#: config/tc-arm.c:12702
 msgid "use -mcpu=arm7tdmi"
 msgstr ""
 
-#: config/tc-arm.c:11726 config/tc-arm.c:11727
+#: config/tc-arm.c:12703 config/tc-arm.c:12704
 msgid "use -mcpu=arm710t"
 msgstr ""
 
-#: config/tc-arm.c:11728 config/tc-arm.c:11729
+#: config/tc-arm.c:12705 config/tc-arm.c:12706
 msgid "use -mcpu=arm720t"
 msgstr ""
 
-#: config/tc-arm.c:11730 config/tc-arm.c:11731
+#: config/tc-arm.c:12707 config/tc-arm.c:12708
 msgid "use -mcpu=arm740t"
 msgstr ""
 
-#: config/tc-arm.c:11732 config/tc-arm.c:11733
+#: config/tc-arm.c:12709 config/tc-arm.c:12710
 msgid "use -mcpu=arm8"
 msgstr ""
 
-#: config/tc-arm.c:11734 config/tc-arm.c:11735
+#: config/tc-arm.c:12711 config/tc-arm.c:12712
 msgid "use -mcpu=arm810"
 msgstr ""
 
-#: config/tc-arm.c:11736 config/tc-arm.c:11737
+#: config/tc-arm.c:12713 config/tc-arm.c:12714
 msgid "use -mcpu=arm9"
 msgstr ""
 
-#: config/tc-arm.c:11738 config/tc-arm.c:11739
+#: config/tc-arm.c:12715 config/tc-arm.c:12716
 msgid "use -mcpu=arm9tdmi"
 msgstr ""
 
-#: config/tc-arm.c:11740 config/tc-arm.c:11741
+#: config/tc-arm.c:12717 config/tc-arm.c:12718
 msgid "use -mcpu=arm920"
 msgstr ""
 
-#: config/tc-arm.c:11742 config/tc-arm.c:11743
+#: config/tc-arm.c:12719 config/tc-arm.c:12720
 msgid "use -mcpu=arm940"
 msgstr ""
 
-#: config/tc-arm.c:11744
+#: config/tc-arm.c:12721
 msgid "use -mcpu=strongarm"
 msgstr ""
 
-#: config/tc-arm.c:11746
+#: config/tc-arm.c:12723
 msgid "use -mcpu=strongarm110"
 msgstr ""
 
-#: config/tc-arm.c:11748
+#: config/tc-arm.c:12725
 msgid "use -mcpu=strongarm1100"
 msgstr ""
 
-#: config/tc-arm.c:11750
+#: config/tc-arm.c:12727
 msgid "use -mcpu=strongarm1110"
 msgstr ""
 
-#: config/tc-arm.c:11751
+#: config/tc-arm.c:12728
 msgid "use -mcpu=xscale"
 msgstr ""
 
-#: config/tc-arm.c:11752
+#: config/tc-arm.c:12729
 msgid "use -mcpu=iwmmxt"
 msgstr ""
 
-#: config/tc-arm.c:11753
+#: config/tc-arm.c:12730
 msgid "use -mcpu=all"
 msgstr ""
 
 #. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:11756 config/tc-arm.c:11757
+#: config/tc-arm.c:12733 config/tc-arm.c:12734
 msgid "use -march=armv2"
 msgstr ""
 
-#: config/tc-arm.c:11758 config/tc-arm.c:11759
+#: config/tc-arm.c:12735 config/tc-arm.c:12736
 msgid "use -march=armv2a"
 msgstr ""
 
-#: config/tc-arm.c:11760 config/tc-arm.c:11761
+#: config/tc-arm.c:12737 config/tc-arm.c:12738
 msgid "use -march=armv3"
 msgstr ""
 
-#: config/tc-arm.c:11762 config/tc-arm.c:11763
+#: config/tc-arm.c:12739 config/tc-arm.c:12740
 msgid "use -march=armv3m"
 msgstr ""
 
-#: config/tc-arm.c:11764 config/tc-arm.c:11765
+#: config/tc-arm.c:12741 config/tc-arm.c:12742
 msgid "use -march=armv4"
 msgstr ""
 
-#: config/tc-arm.c:11766 config/tc-arm.c:11767
+#: config/tc-arm.c:12743 config/tc-arm.c:12744
 msgid "use -march=armv4t"
 msgstr ""
 
-#: config/tc-arm.c:11768 config/tc-arm.c:11769
+#: config/tc-arm.c:12745 config/tc-arm.c:12746
 msgid "use -march=armv5"
 msgstr ""
 
-#: config/tc-arm.c:11770 config/tc-arm.c:11771
+#: config/tc-arm.c:12747 config/tc-arm.c:12748
 msgid "use -march=armv5t"
 msgstr ""
 
-#: config/tc-arm.c:11772 config/tc-arm.c:11773
+#: config/tc-arm.c:12749 config/tc-arm.c:12750
 msgid "use -march=armv5te"
 msgstr ""
 
 #. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:11776
+#: config/tc-arm.c:12753
 msgid "use -mfpu=fpe"
 msgstr ""
 
-#: config/tc-arm.c:11777
+#: config/tc-arm.c:12754
 msgid "use -mfpu=fpa10"
 msgstr ""
 
-#: config/tc-arm.c:11778
+#: config/tc-arm.c:12755
 msgid "use -mfpu=fpa11"
 msgstr ""
 
-#: config/tc-arm.c:11780
+#: config/tc-arm.c:12757
 msgid "use either -mfpu=softfpa or -mfpu=softvfp"
 msgstr ""
 
-#: config/tc-arm.c:11963
+#: config/tc-arm.c:12986
 msgid "invalid architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:11977
+#: config/tc-arm.c:13000
 msgid "missing architectural extension"
 msgstr ""
 
-#: config/tc-arm.c:11990
+#: config/tc-arm.c:13013
 #, c-format
 msgid "unknown architectural extnsion `%s'"
 msgstr ""
 
-#: config/tc-arm.c:12015
+#: config/tc-arm.c:13037
 #, c-format
 msgid "missing cpu name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:12031
+#: config/tc-arm.c:13062 config/tc-arm.c:13389
 #, c-format
 msgid "unknown cpu `%s'"
 msgstr ""
 
-#: config/tc-arm.c:12050
+#: config/tc-arm.c:13080
 #, c-format
 msgid "missing architecture name `%s'"
 msgstr ""
 
-#: config/tc-arm.c:12067
+#: config/tc-arm.c:13097 config/tc-arm.c:13423
 #, c-format
 msgid "unknown architecture `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:12084
+#: config/tc-arm.c:13113 config/tc-arm.c:13454
 #, c-format
 msgid "unknown floating point format `%s'\n"
 msgstr ""
 
-#: config/tc-arm.c:12090
+#: config/tc-arm.c:13129
+#, c-format
+msgid "unknown floating point abi `%s'\n"
+msgstr ""
+
+#: config/tc-arm.c:13145
+#, c-format
+msgid "unknown EABI `%s'\n"
+msgstr ""
+
+#: config/tc-arm.c:13152
 msgid "<cpu name>\t  assemble for CPU <cpu name>"
 msgstr ""
 
-#: config/tc-arm.c:12092
+#: config/tc-arm.c:13154
 msgid "<arch name>\t  assemble for architecture <arch name>"
 msgstr ""
 
-#: config/tc-arm.c:12094
+#: config/tc-arm.c:13156
 msgid "<fpu name>\t  assemble for FPU architecture <fpu name>"
 msgstr ""
 
-#: config/tc-arm.c:12136 config/tc-arm.c:12158
-#, c-format
-msgid "option `-%c%s' is deprecated: %s"
+#: config/tc-arm.c:13158
+msgid "<abi>\t  assemble for floating point ABI <abi>"
+msgstr ""
+
+#: config/tc-arm.c:13161
+msgid "<ver>\t  assemble for eabi version <ver>"
 msgstr ""
 
-#: config/tc-arm.c:12167
+#: config/tc-arm.c:13202 config/tc-arm.c:13224
 #, c-format
-msgid "unrecognized option `-%c%s'"
+msgid "option `-%c%s' is deprecated: %s"
 msgstr ""
 
-#: config/tc-arm.c:12181
+#: config/tc-arm.c:13245
+#, c-format
 msgid " ARM-specific assembler options:\n"
 msgstr ""
 
-#: config/tc-arm.c:12192
+#: config/tc-arm.c:13256
+#, c-format
 msgid "  -EB                     assemble code for a big-endian cpu\n"
 msgstr ""
 
-#: config/tc-arm.c:12197
+#: config/tc-arm.c:13261
+#, c-format
 msgid "  -EL                     assemble code for a little-endian cpu\n"
 msgstr ""
 
-#: config/tc-arm.c:12381
+#: config/tc-avr.c:209
 #, c-format
-msgid "%s: unexpected function type: %d"
-msgstr ""
-
-#: config/tc-arm.c:12756
-msgid "alignments greater than 32 bytes not supported in .text sections."
-msgstr ""
-
-#: config/tc-arm.h:98
-msgid "arm convert_frag\n"
-msgstr ""
-
-#: config/tc-avr.c:203
 msgid "Known MCU names:"
 msgstr ""
 
-#: config/tc-avr.c:272
+#: config/tc-avr.c:275
+#, c-format
 msgid ""
 "AVR options:\n"
 "  -mmcu=[avr-name] select microcontroller variant\n"
@@ -2666,7 +2691,8 @@ msgid ""
 "                   or immediate microcontroller name.\n"
 msgstr ""
 
-#: config/tc-avr.c:282
+#: config/tc-avr.c:285
+#, c-format
 msgid ""
 "  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
 "  -mno-skip-bug    disable warnings for skipping two-word instructions\n"
@@ -2675,532 +2701,821 @@ msgid ""
 "                   (default for avr3, avr5)\n"
 msgstr ""
 
-#: config/tc-avr.c:330 config/tc-msp430.c:257
+#: config/tc-avr.c:329 config/tc-msp430.c:749
 #, c-format
 msgid "unknown MCU: %s\n"
 msgstr ""
 
-#: config/tc-avr.c:339
+#: config/tc-avr.c:338
 #, c-format
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr ""
 
-#: config/tc-avr.c:390 config/tc-d10v.c:319 config/tc-d30v.c:365
-#: config/tc-mips.c:10137 config/tc-mmix.c:2246 config/tc-mn10200.c:361
-#: config/tc-msp430.c:378 config/tc-pj.c:374 config/tc-ppc.c:5105
-#: config/tc-sh.c:2528 config/tc-v850.c:1244
+#: config/tc-avr.c:385 config/tc-crx.c:491 config/tc-d10v.c:278
+#: config/tc-d30v.c:312 config/tc-mips.c:10241 config/tc-mmix.c:2264
+#: config/tc-mn10200.c:342 config/tc-msp430.c:873 config/tc-pj.c:342
+#: config/tc-ppc.c:5211 config/tc-sh.c:2986 config/tc-v850.c:1199
 msgid "bad call to md_atof"
 msgstr ""
 
-#: config/tc-avr.c:453
+#: config/tc-avr.c:447
 msgid "constant value required"
 msgstr ""
 
-#: config/tc-avr.c:456
+#: config/tc-avr.c:450
 #, c-format
 msgid "number must be less than %d"
 msgstr ""
 
-#: config/tc-avr.c:508
-msgid "`,' required"
+#: config/tc-avr.c:476 config/tc-avr.c:583
+#, c-format
+msgid "constant out of 8-bit range: %d"
 msgstr ""
 
-#: config/tc-avr.c:527
-msgid "undefined combination of operands"
+#: config/tc-avr.c:488 config/tc-d10v.c:498 config/tc-d30v.c:490
+#: config/tc-h8300.c:451 config/tc-mcore.c:665 config/tc-mmix.c:489
+#: config/tc-mn10200.c:1078 config/tc-mn10300.c:1820 config/tc-msp430.c:457
+#: config/tc-or32.c:306 config/tc-ppc.c:2382 config/tc-s390.c:1220
+#: config/tc-sh64.c:2213 config/tc-sh.c:1272 config/tc-v850.c:1952
+#: config/tc-z8k.c:328
+msgid "missing operand"
 msgstr ""
 
-#: config/tc-avr.c:536
-msgid "skipping two-word instruction"
+#: config/tc-avr.c:536 read.c:3345
+msgid "illegal expression"
 msgstr ""
 
-#: config/tc-avr.c:598
+#: config/tc-avr.c:562 config/tc-avr.c:1282
+msgid "`)' required"
+msgstr ""
+
+#: config/tc-avr.c:638
 msgid "register r16-r23 required"
 msgstr ""
 
-#: config/tc-avr.c:604
+#: config/tc-avr.c:644
 msgid "register number above 15 required"
 msgstr ""
 
-#: config/tc-avr.c:610
+#: config/tc-avr.c:650
 msgid "even register number required"
 msgstr ""
 
-#: config/tc-avr.c:616
+#: config/tc-avr.c:656
 msgid "register r24, r26, r28 or r30 required"
 msgstr ""
 
-#: config/tc-avr.c:622
+#: config/tc-avr.c:662
 msgid "register name or number from 0 to 31 required"
 msgstr ""
 
-#: config/tc-avr.c:640
+#: config/tc-avr.c:680
 msgid "pointer register (X, Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:647
+#: config/tc-avr.c:687
 msgid "cannot both predecrement and postincrement"
 msgstr ""
 
-#: config/tc-avr.c:655
+#: config/tc-avr.c:695
 msgid "addressing mode not supported"
 msgstr ""
 
-#: config/tc-avr.c:661
+#: config/tc-avr.c:701
 msgid "can't predecrement"
 msgstr ""
 
-#: config/tc-avr.c:664
+#: config/tc-avr.c:704
 msgid "pointer register Z required"
 msgstr ""
 
-#: config/tc-avr.c:682
+#: config/tc-avr.c:722
 msgid "pointer register (Y or Z) required"
 msgstr ""
 
-#: config/tc-avr.c:787
+#: config/tc-avr.c:826
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr ""
 
-#: config/tc-avr.c:881 config/tc-avr.c:897 config/tc-avr.c:998
-#: config/tc-msp430.c:1431 config/tc-msp430.c:1448
+#: config/tc-avr.c:878
+msgid "`,' required"
+msgstr ""
+
+#: config/tc-avr.c:896
+msgid "undefined combination of operands"
+msgstr ""
+
+#: config/tc-avr.c:905
+msgid "skipping two-word instruction"
+msgstr ""
+
+#: config/tc-avr.c:997 config/tc-avr.c:1013 config/tc-avr.c:1135
+#: config/tc-msp430.c:2012 config/tc-msp430.c:2030
 #, c-format
 msgid "odd address operand: %ld"
 msgstr ""
 
-#: config/tc-avr.c:889 config/tc-avr.c:908 config/tc-d10v.c:586
-#: config/tc-d30v.c:655 config/tc-msp430.c:1439 config/tc-msp430.c:1453
-#: config/tc-msp430.c:1463
+#: config/tc-avr.c:1005 config/tc-avr.c:1024 config/tc-avr.c:1046
+#: config/tc-avr.c:1053 config/tc-avr.c:1060 config/tc-d10v.c:538
+#: config/tc-d30v.c:589 config/tc-msp430.c:2020 config/tc-msp430.c:2035
+#: config/tc-msp430.c:2045
 #, c-format
 msgid "operand out of range: %ld"
 msgstr ""
 
-#: config/tc-avr.c:1007 config/tc-d10v.c:1793 config/tc-d30v.c:1973
-#: config/tc-msp430.c:1481
+#: config/tc-avr.c:1144 config/tc-d10v.c:1622 config/tc-d30v.c:2060
+#: config/tc-msp430.c:2063
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr ""
 
-#: config/tc-avr.c:1021
+#: config/tc-avr.c:1158
 msgid "only constant expression allowed"
 msgstr ""
 
-#: config/tc-avr.c:1057 config/tc-d10v.c:1659 config/tc-d30v.c:1806
-#: config/tc-mn10200.c:1255 config/tc-mn10300.c:2303 config/tc-msp430.c:1520
-#: config/tc-or32.c:1618 config/tc-ppc.c:5919 config/tc-v850.c:2263
+#. xgettext:c-format.
+#: config/tc-avr.c:1192 config/tc-bfin.c:689 config/tc-d10v.c:1494
+#: config/tc-d30v.c:1804 config/tc-mn10200.c:814 config/tc-mn10300.c:2308
+#: config/tc-msp430.c:2098 config/tc-or32.c:1019 config/tc-ppc.c:6064
+#: config/tc-v850.c:2190
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr ""
 
-#: config/tc-avr.c:1081 config/tc-d10v.c:1248 config/tc-d10v.c:1262
-#: config/tc-h8300.c:1915 config/tc-h8500.c:1106 config/tc-mcore.c:938
-#: config/tc-msp430.c:438 config/tc-pj.c:283 config/tc-sh.c:2096
-#: config/tc-z8k.c:1238
+#: config/tc-avr.c:1215 config/tc-d10v.c:1782 config/tc-d10v.c:1796
+#: config/tc-h8300.c:1868 config/tc-mcore.c:884 config/tc-msp430.c:1862
+#: config/tc-pj.c:254 config/tc-sh.c:2457 config/tc-z8k.c:1194
 msgid "can't find opcode "
 msgstr ""
 
-#: config/tc-avr.c:1098
+#: config/tc-avr.c:1232
 #, c-format
 msgid "illegal opcode %s for mcu %s"
 msgstr ""
 
-#: config/tc-avr.c:1106
+#: config/tc-avr.c:1241
 msgid "garbage at end of line"
 msgstr ""
 
-#: config/tc-avr.c:1170 read.c:3226
-msgid "illegal expression"
-msgstr ""
-
-#: config/tc-avr.c:1196 config/tc-avr.c:1262
-msgid "`)' required"
-msgstr ""
-
-#: config/tc-avr.c:1216
+#: config/tc-avr.c:1309 config/tc-avr.c:1316
 #, c-format
-msgid "constant out of 8-bit range: %d"
+msgid "illegal %srelocation size: %d"
 msgstr ""
 
-#: config/tc-avr.c:1219
-msgid "expression possibly out of 8-bit range"
+#: config/tc-bfin.c:263
+#, c-format
+msgid " BFIN specific command line options:\n"
 msgstr ""
 
-#: config/tc-avr.c:1290 config/tc-avr.c:1297
-#, c-format
-msgid "illegal %srelocation size: %d"
+#: config/tc-bfin.c:646 config/tc-fr30.c:358 config/tc-frv.c:1600
+#: config/tc-i960.c:1756 config/tc-ip2k.c:371 config/tc-m32c.c:912
+#: config/tc-m32r.c:2143 config/tc-openrisc.c:376 config/tc-xstormy16.c:631
+msgid "Bad call to md_atof()"
 msgstr ""
 
-#: config/tc-cris.c:386 config/tc-m68hc11.c:2831
+#: config/tc-cris.c:532 config/tc-m68hc11.c:2794
 #, c-format
 msgid "internal inconsistency problem in %s: fr_symbol %lx"
 msgstr ""
 
-#: config/tc-cris.c:390 config/tc-m68hc11.c:2835
+#: config/tc-cris.c:536 config/tc-m68hc11.c:2798 config/tc-msp430.c:2289
 #, c-format
 msgid "internal inconsistency problem in %s: resolved symbol"
 msgstr ""
 
-#: config/tc-cris.c:396 config/tc-m68hc11.c:2841
+#: config/tc-cris.c:546 config/tc-m68hc11.c:2804
 #, c-format
 msgid "internal inconsistency problem in %s: fr_subtype %d"
 msgstr ""
 
-#: config/tc-cris.c:650
+#: config/tc-cris.c:872
+msgid "Relaxation to long branches for .arch common_v10_v32 not implemented"
+msgstr ""
+
+#: config/tc-cris.c:902
+msgid "Complicated LAPC target operand is not a multiple of two.  Use LAPC.D"
+msgstr ""
+
+#: config/tc-cris.c:907
+#, c-format
+msgid ""
+"Internal error found in md_convert_frag: offset %ld.  Please report this."
+msgstr ""
+
+#: config/tc-cris.c:932
 #, c-format
 msgid "internal inconsistency in %s: bdapq no symbol"
 msgstr ""
 
-#: config/tc-cris.c:663
+#: config/tc-cris.c:945
 #, c-format
 msgid "internal inconsistency in %s: bdap.w with no symbol"
 msgstr ""
 
-#: config/tc-cris.c:807
+#: config/tc-cris.c:969
+msgid "section alignment must be >= 4 bytes to check MULS/MULU safeness"
+msgstr ""
+
+#: config/tc-cris.c:978
+msgid "dangerous MULS/MULU location; give it higher alignment"
+msgstr ""
+
+#: config/tc-cris.c:1083
+msgid ""
+"Out-of-range .word offset handling is not implemented for .arch "
+"common_v10_v32"
+msgstr ""
+
+#: config/tc-cris.c:1148 config/tc-crx.c:582 config/tc-crx.c:609
+#: config/tc-crx.c:627
 msgid "Virtual memory exhausted"
 msgstr ""
 
-#: config/tc-cris.c:815
+#: config/tc-cris.c:1182 config/tc-crx.c:592
 #, c-format
 msgid "Can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-cris.c:816
+#: config/tc-cris.c:1183 config/tc-crx.c:593
 msgid "(unknown reason)"
 msgstr ""
 
-#: config/tc-cris.c:820
+#: config/tc-cris.c:1187
 #, c-format
 msgid "Buggy opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-cris.c:1164
+#: config/tc-cris.c:1493 config/tc-cris.c:1501 config/tc-crx.c:2029
+#: config/tc-dlx.c:685 config/tc-hppa.c:1625 config/tc-i860.c:492
+#: config/tc-i860.c:509 config/tc-i860.c:989 config/tc-sparc.c:1417
+#: config/tc-sparc.c:1425
+#, c-format
+msgid "Unknown opcode: `%s'"
+msgstr ""
+
+#: config/tc-cris.c:1599
 #, c-format
 msgid "Immediate value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1180
+#: config/tc-cris.c:1615
 #, c-format
 msgid "Immediate value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1219
+#: config/tc-cris.c:1667
 #, c-format
 msgid "Immediate value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1234
+#: config/tc-cris.c:1682
 #, c-format
 msgid "Immediate value not in 6 bit unsigned range: %ld"
 msgstr ""
 
 #. Others have a generic warning.
-#: config/tc-cris.c:1324
+#: config/tc-cris.c:1790
 #, c-format
 msgid "Unimplemented register `%s' specified"
 msgstr ""
 
 #. We've come to the end of instructions with this
 #. opcode, so it must be an error.
-#: config/tc-cris.c:1483
+#: config/tc-cris.c:2033
 msgid "Illegal operands"
 msgstr ""
 
-#: config/tc-cris.c:1514 config/tc-cris.c:1545
+#: config/tc-cris.c:2074 config/tc-cris.c:2114
 #, c-format
 msgid "Immediate value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1524 config/tc-cris.c:1552
+#: config/tc-cris.c:2084 config/tc-cris.c:2135
 #, c-format
 msgid "Immediate value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:1573
+#: config/tc-cris.c:2119
+#, c-format
+msgid "Immediate value not in 8 bit signed range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:2124
+#, c-format
+msgid "Immediate value not in 8 bit unsigned range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:2140
+#, c-format
+msgid "Immediate value not in 16 bit signed range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:2145
+#, c-format
+msgid "Immediate value not in 16 bit unsigned range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:2167
 msgid "PIC relocation size does not match operand size"
 msgstr ""
 
-#: config/tc-cris.c:2572
+#: config/tc-cris.c:3304
+msgid "Calling gen_cond_branch_32 for .arch common_v10_v32\n"
+msgstr ""
+
+#: config/tc-cris.c:3308
 msgid "32-bit conditional branch generated"
 msgstr ""
 
-#: config/tc-cris.c:2626
+#: config/tc-cris.c:3367
 msgid "Complex expression not supported"
 msgstr ""
 
 #. FIXME:  Is this function mentioned in the internals.texi manual?  If
 #. not, add it.
-#: config/tc-cris.c:2747
+#: config/tc-cris.c:3490
 msgid "Bad call to md_atof () - floating point formats are not supported"
 msgstr ""
 
-#: config/tc-cris.c:2794
+#: config/tc-cris.c:3531
 msgid "PC-relative relocation must be trivially resolved"
 msgstr ""
 
-#: config/tc-cris.c:2837
+#: config/tc-cris.c:3584
 #, c-format
 msgid "Value not in 16 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2848
+#: config/tc-cris.c:3595
+#, c-format
+msgid "Value not in 16 bit signed range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:3606
 #, c-format
 msgid "Value not in 8 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2855
+#: config/tc-cris.c:3614
+#, c-format
+msgid "Value not in 8 bit signed range: %ld"
+msgstr ""
+
+#: config/tc-cris.c:3625
 #, c-format
 msgid "Value not in 4 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2862
+#: config/tc-cris.c:3633
 #, c-format
 msgid "Value not in 5 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2869
+#: config/tc-cris.c:3641
 #, c-format
 msgid "Value not in 6 bit range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2876
+#: config/tc-cris.c:3649
 #, c-format
 msgid "Value not in 6 bit unsigned range: %ld"
 msgstr ""
 
-#: config/tc-cris.c:2924
+#: config/tc-cris.c:3695
+#, c-format
 msgid "Please use --help to see usage and options for this assembler.\n"
 msgstr ""
 
-#: config/tc-cris.c:2936
+#: config/tc-cris.c:3707
 msgid "--no-underscore is invalid with a.out format"
 msgstr ""
 
-#: config/tc-cris.c:3012
+#: config/tc-cris.c:3727
+#, c-format
+msgid "invalid <arch> in --march=<arch>: %s"
+msgstr ""
+
+#: config/tc-cris.c:3821
 msgid ""
 "Semantics error.  This type of operand can not be relocated, it must be an "
 "assembly-time constant"
 msgstr ""
 
-#: config/tc-cris.c:3064
+#: config/tc-cris.c:3870
 #, c-format
 msgid "Cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
 #. The messages are formatted to line up with the generic options.
-#: config/tc-cris.c:3078
+#: config/tc-cris.c:3883
+#, c-format
 msgid "CRIS-specific options:\n"
 msgstr ""
 
-#: config/tc-cris.c:3080
+#: config/tc-cris.c:3885
 msgid ""
 "  -h, -H                  Don't execute, print this help text.  Deprecated.\n"
 msgstr ""
 
-#: config/tc-cris.c:3082
+#: config/tc-cris.c:3887
 msgid "  -N                      Warn when branches are expanded to jumps.\n"
 msgstr ""
 
-#: config/tc-cris.c:3084
+#: config/tc-cris.c:3889
 msgid ""
 "  --underscore            User symbols are normally prepended with "
 "underscore.\n"
 msgstr ""
 
-#: config/tc-cris.c:3086
+#: config/tc-cris.c:3891
 msgid "                          Registers will not need any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3088
+#: config/tc-cris.c:3893
 msgid "  --no-underscore         User symbols do not have any prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3090
+#: config/tc-cris.c:3895
 msgid "                          Registers will require a `$'-prefix.\n"
 msgstr ""
 
-#: config/tc-cris.c:3092
+#: config/tc-cris.c:3897
 msgid "  --pic\t\t\tEnable generation of position-independent code.\n"
 msgstr ""
 
-#: config/tc-cris.c:3115
+#: config/tc-cris.c:3899
+msgid ""
+"  --march=<arch>\t\tGenerate code for <arch>.  Valid choices for <arch>\n"
+"\t\t\t\tare v0_v10, v10, v32 and common_v10_v32.\n"
+msgstr ""
+
+#: config/tc-cris.c:3920
 msgid "Invalid relocation"
 msgstr ""
 
-#: config/tc-cris.c:3149
+#: config/tc-cris.c:3957
 msgid "Invalid pc-relative relocation"
 msgstr ""
 
-#: config/tc-cris.c:3198
+#: config/tc-cris.c:4002
 #, c-format
 msgid "Adjusted signed .word (%ld) overflows: `switch'-statement too large."
 msgstr ""
 
-#: config/tc-cris.c:3225
+#: config/tc-cris.c:4032
 #, c-format
 msgid ".syntax %s requires command-line option `--underscore'"
 msgstr ""
 
-#: config/tc-cris.c:3234
+#: config/tc-cris.c:4041
 #, c-format
 msgid ".syntax %s requires command-line option `--no-underscore'"
 msgstr ""
 
-#: config/tc-cris.c:3272
+#: config/tc-cris.c:4078
 msgid "Unknown .syntax operand"
 msgstr ""
 
-#: config/tc-cris.c:3283
+#: config/tc-cris.c:4088
 msgid "Pseudodirective .file is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-cris.c:3296
+#: config/tc-cris.c:4100
 msgid "Pseudodirective .loc is only valid when generating ELF"
 msgstr ""
 
-#: config/tc-d10v.c:252
-msgid ""
-"D10V options:\n"
-"-O                      Optimize.  Will do some operations in parallel.\n"
-"--gstabs-packing        Pack adjacent short instructions together even\n"
-"                        when --gstabs is specified.  On by default.\n"
-"--no-gstabs-packing     If --gstabs is specified, do not pack adjacent\n"
-"                        instructions together.\n"
+#: config/tc-cris.c:4243
+msgid "unknown operand to .arch"
 msgstr ""
 
-#: config/tc-d10v.c:543 config/tc-d30v.c:549 config/tc-mn10200.c:937
-#: config/tc-mn10300.c:1812 config/tc-ppc.c:2332 config/tc-s390.c:1234
-#: config/tc-tic80.c:275 config/tc-v850.c:2021
-msgid "illegal operand"
+#: config/tc-cris.c:4252
+msgid ".arch <arch> requires a matching --march=... option"
 msgstr ""
 
-#: config/tc-d10v.c:657
-msgid "operand is not an immediate"
+#: config/tc-crx.c:344 config/tc-mn10200.c:801 write.c:2209
+#, c-format
+msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
 msgstr ""
 
-#: config/tc-d10v.c:675
+#: config/tc-crx.c:360
 #, c-format
-msgid "operand out of range: %lu"
+msgid "internal error: reloc %d (`%s') not supported by object file format"
 msgstr ""
 
-#: config/tc-d10v.c:736
-msgid "Instruction must be executed in parallel with another instruction."
+#: config/tc-crx.c:619 config/tc-crx.c:637 config/tc-i386.c:953
+#: config/tc-i386.c:976 config/tc-m68k.c:4149
+#, c-format
+msgid "Internal Error:  Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-d10v.c:792
-msgid "Instruction must be executed in parallel"
+#. Missing or bad expr becomes absolute 0.
+#: config/tc-crx.c:665 config/tc-i386.c:4259
+#, c-format
+msgid "missing or invalid displacement expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-d10v.c:795
-msgid "Long instructions may not be combined."
+#: config/tc-crx.c:803 config/tc-crx.c:823 config/tc-crx.c:838
+#, c-format
+msgid "Illegal register `%s' in Instruction `%s'"
 msgstr ""
 
-#: config/tc-d10v.c:828
-msgid "One of these instructions may not be executed in parallel."
+#: config/tc-crx.c:866
+#, c-format
+msgid "Illegal Scale - `%d'"
 msgstr ""
 
-#: config/tc-d10v.c:832 config/tc-d30v.c:876
-msgid "Two IU instructions may not be executed in parallel"
+#: config/tc-crx.c:982
+#, c-format
+msgid "Illegal operands (whitespace): `%s'"
 msgstr ""
 
-#: config/tc-d10v.c:834 config/tc-d10v.c:842 config/tc-d10v.c:856
-#: config/tc-d10v.c:871 config/tc-d30v.c:877 config/tc-d30v.c:886
-msgid "Swapping instruction order"
+#: config/tc-crx.c:994 config/tc-crx.c:1001 config/tc-crx.c:1018
+#: config/tc-crx.c:1804
+#, c-format
+msgid "Missing matching brackets : `%s'"
 msgstr ""
 
-#: config/tc-d10v.c:840 config/tc-d30v.c:883
-msgid "Two MU instructions may not be executed in parallel"
+#: config/tc-crx.c:1044
+#, c-format
+msgid "Unknown exception: `%s'"
 msgstr ""
 
-#: config/tc-d10v.c:860 config/tc-d30v.c:903
-msgid "IU instruction may not be in the left container"
+#: config/tc-crx.c:1140
+#, c-format
+msgid "Illegal `cinv' parameter: `%c'"
+msgstr ""
+
+#: config/tc-crx.c:1173
+#, c-format
+msgid "Unknown register: `%d'"
+msgstr ""
+
+#. Issue a error message when register is illegal.
+#: config/tc-crx.c:1181
+#, c-format
+msgid "Illegal register (`%s') in Instruction: `%s'"
+msgstr ""
+
+#: config/tc-crx.c:1310
+#, c-format
+msgid "Illegal Co-processor register in Instruction `%s' "
+msgstr ""
+
+#: config/tc-crx.c:1317
+#, c-format
+msgid "Illegal Co-processor special register in Instruction `%s' "
+msgstr ""
+
+#: config/tc-crx.c:1616
+msgid "Incorrect number of operands"
+msgstr ""
+
+#: config/tc-crx.c:1618
+#, c-format
+msgid "Illegal type of operand (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1624
+#, c-format
+msgid "Operand out of range (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1627
+#, c-format
+msgid "Operand has odd displacement (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1630
+#, c-format
+msgid "Invalid DISPU4 operand value (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1633
+#, c-format
+msgid "Invalid CST4 operand value (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1636
+#, c-format
+msgid "Operand value is not within upper 64 KB (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1640 config/tc-crx.c:1671
+#, c-format
+msgid "Illegal operand (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1702 config/tc-crx.c:1719
+#, c-format
+msgid "Same src/dest register is used (`r%d'), result is undefined"
+msgstr ""
+
+#: config/tc-crx.c:1711
+#, c-format
+msgid "`%s' has undefined result"
 msgstr ""
 
-#: config/tc-d10v.c:862 config/tc-d10v.c:877
+#: config/tc-crx.c:1773
+msgid "Invalid Register in Register List"
+msgstr ""
+
+#: config/tc-crx.c:1827
+#, c-format
+msgid "Illegal register `%s' in cop-register list"
+msgstr ""
+
+#: config/tc-crx.c:1835
+#, c-format
+msgid "Illegal register `%s' in cop-special-register list"
+msgstr ""
+
+#: config/tc-crx.c:1854
+#, c-format
+msgid "Illegal register `%s' in user register list"
+msgstr ""
+
+#: config/tc-crx.c:1873
+#, c-format
+msgid "Illegal register `%s' in register list"
+msgstr ""
+
+#: config/tc-crx.c:1879
+#, c-format
+msgid "Maximum %d bits may be set in `mask16' operand"
+msgstr ""
+
+#: config/tc-crx.c:1888
+#, c-format
+msgid "rest of line ignored; first ignored character is `%c'"
+msgstr ""
+
+#: config/tc-crx.c:1896
+#, c-format
+msgid "Illegal `mask16' operand, operation is undefined - `%s'"
+msgstr ""
+
+#. HI can't be specified without LO (and vise-versa).
+#: config/tc-crx.c:1902
+msgid "HI/LO registers should be specified together"
+msgstr ""
+
+#: config/tc-crx.c:1908
+msgid "HI/LO registers should be specified without additional registers"
+msgstr ""
+
+#. Give an error if a frag containing code is not aligned to a 2-byte
+#. boundary.
+#: config/tc-crx.c:1993 config/tc-crx.h:76
+msgid "instruction address is not a multiple of 2"
+msgstr ""
+
+#: config/tc-d10v.c:217
+#, c-format
 msgid ""
-"Instruction in R container is squashed by flow control instruction in L "
-"container."
+"D10V options:\n"
+"-O                      Optimize.  Will do some operations in parallel.\n"
+"--gstabs-packing        Pack adjacent short instructions together even\n"
+"                        when --gstabs is specified.  On by default.\n"
+"--no-gstabs-packing     If --gstabs is specified, do not pack adjacent\n"
+"                        instructions together.\n"
 msgstr ""
 
-#: config/tc-d10v.c:875 config/tc-d30v.c:914
-msgid "MU instruction may not be in the right container"
+#: config/tc-d10v.c:496 config/tc-d30v.c:488 config/tc-mn10200.c:1075
+#: config/tc-mn10300.c:1817 config/tc-ppc.c:2380 config/tc-s390.c:1218
+#: config/tc-v850.c:1949
+msgid "illegal operand"
 msgstr ""
 
-#: config/tc-d10v.c:881 config/tc-d30v.c:926
-msgid "unknown execution type passed to write_2_short()"
+#: config/tc-d10v.c:608
+msgid "operand is not an immediate"
 msgstr ""
 
-#: config/tc-d10v.c:1072 config/tc-d10v.c:1080
+#: config/tc-d10v.c:626
+#, c-format
+msgid "operand out of range: %lu"
+msgstr ""
+
+#: config/tc-d10v.c:684
+msgid "Instruction must be executed in parallel with another instruction."
+msgstr ""
+
+#: config/tc-d10v.c:738 config/tc-d10v.c:746
 #, c-format
 msgid "packing conflict: %s must dispatch sequentially"
 msgstr ""
 
-#: config/tc-d10v.c:1179
+#: config/tc-d10v.c:845
 #, c-format
 msgid "resource conflict (R%d)"
 msgstr ""
 
-#: config/tc-d10v.c:1182
+#: config/tc-d10v.c:848
 #, c-format
 msgid "resource conflict (A%d)"
 msgstr ""
 
-#: config/tc-d10v.c:1184
+#: config/tc-d10v.c:850
 msgid "resource conflict (PSW)"
 msgstr ""
 
-#: config/tc-d10v.c:1186
+#: config/tc-d10v.c:852
 msgid "resource conflict (C flag)"
 msgstr ""
 
-#: config/tc-d10v.c:1188
+#: config/tc-d10v.c:854
 msgid "resource conflict (F flag)"
 msgstr ""
 
-#: config/tc-d10v.c:1276 config/tc-d10v.c:1298 config/tc-d30v.c:1410
-msgid "Unable to mix instructions as specified"
+#: config/tc-d10v.c:1004
+msgid "Instruction must be executed in parallel"
 msgstr ""
 
-#: config/tc-d10v.c:1345 config/tc-d30v.c:1547
-#, c-format
-msgid "unknown opcode: %s"
+#: config/tc-d10v.c:1007
+msgid "Long instructions may not be combined."
 msgstr ""
 
-#: config/tc-d10v.c:1428 config/tc-d10v.c:1603 config/tc-tic80.c:532
+#: config/tc-d10v.c:1040
+msgid "One of these instructions may not be executed in parallel."
+msgstr ""
+
+#: config/tc-d10v.c:1044 config/tc-d30v.c:1071
+msgid "Two IU instructions may not be executed in parallel"
+msgstr ""
+
+#: config/tc-d10v.c:1046 config/tc-d10v.c:1054 config/tc-d10v.c:1068
+#: config/tc-d10v.c:1083 config/tc-d30v.c:1072 config/tc-d30v.c:1081
+msgid "Swapping instruction order"
+msgstr ""
+
+#: config/tc-d10v.c:1052 config/tc-d30v.c:1078
+msgid "Two MU instructions may not be executed in parallel"
+msgstr ""
+
+#: config/tc-d10v.c:1072 config/tc-d30v.c:1098
+msgid "IU instruction may not be in the left container"
+msgstr ""
+
+#: config/tc-d10v.c:1074 config/tc-d10v.c:1089
+msgid ""
+"Instruction in R container is squashed by flow control instruction in L "
+"container."
+msgstr ""
+
+#: config/tc-d10v.c:1087 config/tc-d30v.c:1109
+msgid "MU instruction may not be in the right container"
+msgstr ""
+
+#: config/tc-d10v.c:1093 config/tc-d30v.c:1121
+msgid "unknown execution type passed to write_2_short()"
+msgstr ""
+
+#: config/tc-d10v.c:1221 config/tc-d10v.c:1394
 msgid "bad opcode or operands"
 msgstr ""
 
-#: config/tc-d10v.c:1503 config/tc-m68k.c:4305
+#: config/tc-d10v.c:1296 config/tc-m68k.c:4625
 msgid "value out of range"
 msgstr ""
 
-#: config/tc-d10v.c:1579
+#: config/tc-d10v.c:1370
 msgid "illegal operand - register name found where none expected"
 msgstr ""
 
-#: config/tc-d10v.c:1614 config/tc-tic80.c:543
+#: config/tc-d10v.c:1405
 msgid "Register number must be EVEN"
 msgstr ""
 
-#: config/tc-d10v.c:1617
+#: config/tc-d10v.c:1408
 msgid "Unsupported use of sp"
 msgstr ""
 
-#: config/tc-d10v.c:1636
+#: config/tc-d10v.c:1427
 #, c-format
 msgid "cr%ld is a reserved control register"
 msgstr ""
 
-#: config/tc-d10v.c:1773
+#: config/tc-d10v.c:1466 config/tc-d30v.c:1430
+#, c-format
+msgid "unknown opcode: %s"
+msgstr ""
+
+#: config/tc-d10v.c:1602
 #, c-format
 msgid "line %d: rep or repi must include at least 4 instructions"
 msgstr ""
 
-#: config/tc-d30v.c:192
+#: config/tc-d10v.c:1810 config/tc-d10v.c:1832 config/tc-d30v.c:1777
+msgid "Unable to mix instructions as specified"
+msgstr ""
+
+#: config/tc-d30v.c:150
 #, c-format
 msgid "Register name %s conflicts with symbol of the same name"
 msgstr ""
 
-#: config/tc-d30v.c:287
+#: config/tc-d30v.c:240
+#, c-format
 msgid ""
 "\n"
 "D30V options:\n"
@@ -3213,1097 +3528,1134 @@ msgid ""
 "-C                      Opposite of -C.  -c is the default.\n"
 msgstr ""
 
-#: config/tc-d30v.c:461
+#: config/tc-d30v.c:402
 msgid "unexpected 12-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:468
+#: config/tc-d30v.c:409
 msgid "unexpected 18-bit reloc type"
 msgstr ""
 
-#: config/tc-d30v.c:719
+#: config/tc-d30v.c:659
 #, c-format
 msgid "%s NOP inserted"
 msgstr ""
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:660
 msgid "sequential"
 msgstr ""
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:660
 msgid "parallel"
 msgstr ""
 
-#: config/tc-d30v.c:872
+#: config/tc-d30v.c:1067
 msgid "Instructions may not be executed in parallel"
 msgstr ""
 
-#: config/tc-d30v.c:885
+#: config/tc-d30v.c:1080
 #, c-format
 msgid "Executing %s in IU may not work"
 msgstr ""
 
-#: config/tc-d30v.c:892
+#: config/tc-d30v.c:1087
 #, c-format
 msgid "Executing %s in IU may not work in parallel execution"
 msgstr ""
 
-#: config/tc-d30v.c:905
+#: config/tc-d30v.c:1100
 #, c-format
 msgid "special left instruction `%s' kills instruction `%s' in right container"
 msgstr ""
 
-#: config/tc-d30v.c:916
+#: config/tc-d30v.c:1111
 #, c-format
 msgid "Executing %s in reverse serial with %s may not work"
 msgstr ""
 
-#: config/tc-d30v.c:919
+#: config/tc-d30v.c:1114
 #, c-format
 msgid "Executing %s in IU in reverse serial may not work"
 msgstr ""
 
-#: config/tc-d30v.c:1289 config/tc-d30v.c:1306
-msgid "Cannot assemble instruction"
+#: config/tc-d30v.c:1303
+msgid "Odd numbered register used as target of multi-register instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1291
-msgid "First opcode is long.  Unable to mix instructions as specified."
+#: config/tc-d30v.c:1367 config/tc-d30v.c:1402
+#, c-format
+msgid "unknown condition code: %s"
 msgstr ""
 
-#: config/tc-d30v.c:1360
-msgid "word of NOPs added between word multiply and load"
+#: config/tc-d30v.c:1395
+#, c-format
+msgid "cmpu doesn't support condition code %s"
 msgstr ""
 
-#: config/tc-d30v.c:1362
-msgid "word of NOPs added between word multiply and 16-bit multiply"
+#: config/tc-d30v.c:1441
+#, c-format
+msgid "operands for opcode `%s' do not match any valid format"
 msgstr ""
 
-#: config/tc-d30v.c:1394
-msgid "Instruction uses long version, so it cannot be mixed as specified"
+#: config/tc-d30v.c:1656 config/tc-d30v.c:1673
+msgid "Cannot assemble instruction"
 msgstr ""
 
-#: config/tc-d30v.c:1477 config/tc-d30v.c:1515
-#, c-format
-msgid "unknown condition code: %s"
+#: config/tc-d30v.c:1658
+msgid "First opcode is long.  Unable to mix instructions as specified."
 msgstr ""
 
-#: config/tc-d30v.c:1508
-#, c-format
-msgid "cmpu doesn't support condition code %s"
+#: config/tc-d30v.c:1727
+msgid "word of NOPs added between word multiply and load"
 msgstr ""
 
-#: config/tc-d30v.c:1558
-#, c-format
-msgid "operands for opcode `%s' do not match any valid format"
+#: config/tc-d30v.c:1729
+msgid "word of NOPs added between word multiply and 16-bit multiply"
 msgstr ""
 
-#: config/tc-d30v.c:1776
-msgid "Odd numbered register used as target of multi-register instruction"
+#: config/tc-d30v.c:1761
+msgid "Instruction uses long version, so it cannot be mixed as specified"
+msgstr ""
+
+#: config/tc-d30v.c:1888
+#, c-format
+msgid "value too large to fit in %d bits"
 msgstr ""
 
-#: config/tc-d30v.c:1862
+#: config/tc-d30v.c:1949
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1865
+#: config/tc-d30v.c:1952
 #, c-format
 msgid "line %d: unable to place value %lx into a byte"
 msgstr ""
 
-#: config/tc-d30v.c:1873
+#: config/tc-d30v.c:1960
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1876
+#: config/tc-d30v.c:1963
 #, c-format
 msgid "line %d: unable to place value %lx into a short"
 msgstr ""
 
-#: config/tc-d30v.c:1884
+#: config/tc-d30v.c:1971
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a quad"
 msgstr ""
 
-#: config/tc-d30v.c:2053
-#, c-format
-msgid "value too large to fit in %d bits"
-msgstr ""
-
-#: config/tc-d30v.c:2196
+#: config/tc-d30v.c:2079
 #, c-format
 msgid "Alignment too large: %d assumed"
 msgstr ""
 
-#: config/tc-dlx.c:283
+#: config/tc-dlx.c:211
 msgid "missing .proc"
 msgstr ""
 
-#: config/tc-dlx.c:300
+#: config/tc-dlx.c:228
 msgid ".endfunc missing for previous .proc"
 msgstr ""
 
-#: config/tc-dlx.c:498
-#, c-format
-msgid "Expression Error for operand modifier %%hi/%%lo\n"
+#. Probably a memory allocation problem?  Give up now.
+#: config/tc-dlx.c:297 config/tc-hppa.c:1489 config/tc-mips.c:1415
+#: config/tc-mips.c:1467 config/tc-or32.c:210 config/tc-sparc.c:855
+msgid "Broken assembler.  No assembly attempted."
 msgstr ""
 
-#: config/tc-dlx.c:552
+#: config/tc-dlx.c:327
 #, c-format
 msgid "Bad operand for a load instruction: <%s>"
 msgstr ""
 
-#: config/tc-dlx.c:667
+#: config/tc-dlx.c:441
 #, c-format
 msgid "Bad operand for a store instruction: <%s>"
 msgstr ""
 
-#: config/tc-dlx.c:865
+#: config/tc-dlx.c:621
+#, c-format
+msgid "Expression Error for operand modifier %%hi/%%lo\n"
+msgstr ""
+
+#: config/tc-dlx.c:634 config/tc-or32.c:873
+#, c-format
+msgid "Invalid expression after %%%%\n"
+msgstr ""
+
+#: config/tc-dlx.c:703
+#, c-format
+msgid "Unknown opcode `%s'."
+msgstr ""
+
+#: config/tc-dlx.c:716
 msgid "Can not set dlx_skip_hi16_flag"
 msgstr ""
 
-#: config/tc-dlx.c:879
+#: config/tc-dlx.c:730
 #, c-format
 msgid "Missing arguments for opcode <%s>."
 msgstr ""
 
-#: config/tc-dlx.c:950
+#: config/tc-dlx.c:764
+#, c-format
+msgid "Too many operands: %s"
+msgstr ""
+
+#: config/tc-dlx.c:801
 #, c-format
 msgid "Both the_insn.HI and the_insn.LO are set : %s"
 msgstr ""
 
-#: config/tc-dlx.c:1022
+#: config/tc-dlx.c:871
 msgid "failed regnum sanity check."
 msgstr ""
 
-#: config/tc-dlx.c:1035
+#: config/tc-dlx.c:884
 msgid "failed general register sanity check."
 msgstr ""
 
-#: config/tc-dlx.c:1324
+#: config/tc-dlx.c:1175 config/tc-or32.c:835
+#, c-format
+msgid "label \"$%d\" redefined"
+msgstr ""
+
+#: config/tc-dlx.c:1213
 msgid "Invalid expression after # number\n"
 msgstr ""
 
-#: config/tc-fr30.c:85
+#: config/tc-fr30.c:83
+#, c-format
 msgid " FR30 specific command line options:\n"
 msgstr ""
 
-#: config/tc-fr30.c:139 config/tc-openrisc.c:152
+#: config/tc-fr30.c:136
 #, c-format
 msgid "Instruction %s not allowed in a delay slot."
 msgstr ""
 
-#: config/tc-fr30.c:383 config/tc-m32r.c:1576
-msgid "Addend to unresolved symbol not on word boundary."
-msgstr ""
-
-#: config/tc-fr30.c:524 config/tc-frv.c:1289 config/tc-i960.c:798
-#: config/tc-ip2k.c:351 config/tc-m32r.c:1884 config/tc-openrisc.c:452
-#: config/tc-xstormy16.c:636
-msgid "Bad call to md_atof()"
-msgstr ""
-
-#: config/tc-frv.c:413
+#: config/tc-frv.c:461
+#, c-format
 msgid "FRV specific command line options:\n"
 msgstr ""
 
-#: config/tc-frv.c:414
+#: config/tc-frv.c:462
+#, c-format
 msgid "-G n         Data >= n bytes is in small data area\n"
 msgstr ""
 
-#: config/tc-frv.c:415
+#: config/tc-frv.c:463
+#, c-format
 msgid "-mgpr-32     Note 32 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:416
+#: config/tc-frv.c:464
+#, c-format
 msgid "-mgpr-64     Note 64 gprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:417
+#: config/tc-frv.c:465
+#, c-format
 msgid "-mfpr-32     Note 32 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:418
+#: config/tc-frv.c:466
+#, c-format
 msgid "-mfpr-64     Note 64 fprs are used\n"
 msgstr ""
 
-#: config/tc-frv.c:419
+#: config/tc-frv.c:467
+#, c-format
 msgid "-msoft-float Note software fp is used\n"
 msgstr ""
 
-#: config/tc-frv.c:420
+#: config/tc-frv.c:468
+#, c-format
 msgid "-mdword      Note stack is aligned to a 8 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:421
+#: config/tc-frv.c:469
+#, c-format
 msgid "-mno-dword   Note stack is aligned to a 4 byte boundary\n"
 msgstr ""
 
-#: config/tc-frv.c:422
+#: config/tc-frv.c:470
+#, c-format
 msgid "-mdouble     Note fp double insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:423
+#: config/tc-frv.c:471
+#, c-format
 msgid "-mmedia      Note media insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:424
+#: config/tc-frv.c:472
+#, c-format
 msgid "-mmuladd     Note multiply add/subtract insns are used\n"
 msgstr ""
 
-#: config/tc-frv.c:425
+#: config/tc-frv.c:473
+#, c-format
 msgid "-mpack       Note instructions are packed\n"
 msgstr ""
 
-#: config/tc-frv.c:426
+#: config/tc-frv.c:474
+#, c-format
 msgid "-mno-pack    Do not allow instructions to be packed\n"
 msgstr ""
 
-#: config/tc-frv.c:427
+#: config/tc-frv.c:475
+#, c-format
 msgid "-mpic        Note small position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:428
+#: config/tc-frv.c:476
+#, c-format
 msgid "-mPIC        Note large position independent code\n"
 msgstr ""
 
-#: config/tc-frv.c:429
+#: config/tc-frv.c:477
+#, c-format
 msgid "-mlibrary-pic Compile library for large position indepedent code\n"
 msgstr ""
 
-#: config/tc-frv.c:430
-msgid "-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n"
+#: config/tc-frv.c:478
+#, c-format
+msgid "-mfdpic      Assemble for the FDPIC ABI\n"
+msgstr ""
+
+#: config/tc-frv.c:479
+#, c-format
+msgid "-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"
+msgstr ""
+
+#: config/tc-frv.c:480
+#, c-format
+msgid "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
 msgstr ""
 
-#: config/tc-frv.c:431
+#: config/tc-frv.c:481
+#, c-format
 msgid "             Record the cpu type\n"
 msgstr ""
 
-#: config/tc-frv.c:432
+#: config/tc-frv.c:482
+#, c-format
 msgid "-mtomcat-stats Print out stats for tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:433
+#: config/tc-frv.c:483
+#, c-format
 msgid "-mtomcat-debug Debug tomcat workarounds\n"
 msgstr ""
 
-#: config/tc-frv.c:1012
+#: config/tc-frv.c:1187
 msgid "VLIW packing used for -mno-pack"
 msgstr ""
 
-#: config/tc-frv.c:1025
+#: config/tc-frv.c:1197
+msgid "Instruction not supported by this architecture"
+msgstr ""
+
+#: config/tc-frv.c:1207
 msgid "VLIW packing constraint violation"
 msgstr ""
 
-#: config/tc-frv.c:1540
+#: config/tc-frv.c:1874
 #, c-format
 msgid "Relocation %s is not safe for %s"
 msgstr ""
 
-#: config/tc-h8300.c:84 config/tc-h8300.c:96 config/tc-h8300.c:109
-#: config/tc-h8300.c:122 config/tc-h8300.c:135 config/tc-h8300.c:149
-#: config/tc-h8300.c:222 config/tc-hppa.c:1423 config/tc-hppa.c:6909
-#: config/tc-hppa.c:6915 config/tc-hppa.c:6921 config/tc-hppa.c:6927
-#: config/tc-mn10300.c:1218 config/tc-mn10300.c:1223 config/tc-mn10300.c:2722
+#: config/tc-h8300.c:78 config/tc-h8300.c:87 config/tc-h8300.c:97
+#: config/tc-h8300.c:107 config/tc-h8300.c:117 config/tc-h8300.c:128
+#: config/tc-h8300.c:195 config/tc-hppa.c:1449 config/tc-hppa.c:6926
+#: config/tc-hppa.c:6932 config/tc-hppa.c:6938 config/tc-hppa.c:6944
+#: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2725
 msgid "could not set architecture and machine"
 msgstr ""
 
-#: config/tc-h8300.c:436 config/tc-h8300.c:444
+#: config/tc-h8300.c:397 config/tc-h8300.c:405
 msgid "Reg not valid for H8/300"
 msgstr ""
 
-#: config/tc-h8300.c:529
+#: config/tc-h8300.c:486
 msgid "invalid operand size requested"
 msgstr ""
 
-#: config/tc-h8300.c:626 config/tc-h8300.c:629
+#: config/tc-h8300.c:585
 msgid "Invalid register list for ldm/stm\n"
 msgstr ""
 
-#: config/tc-h8300.c:632
-msgid "Invalid register list for ldm/stm)\n"
-msgstr ""
-
-#: config/tc-h8300.c:658 config/tc-h8300.c:663 config/tc-h8300.c:670
+#: config/tc-h8300.c:611 config/tc-h8300.c:616 config/tc-h8300.c:623
 msgid "mismatch between register and suffix"
 msgstr ""
 
-#: config/tc-h8300.c:697
+#: config/tc-h8300.c:650
 msgid "address too high for vector table jmp/jsr"
 msgstr ""
 
-#: config/tc-h8300.c:722 config/tc-h8300.c:832 config/tc-h8300.c:840
+#: config/tc-h8300.c:677 config/tc-h8300.c:789 config/tc-h8300.c:799
 msgid "Wrong size pointer register for architecture."
 msgstr ""
 
-#: config/tc-h8300.c:781 config/tc-h8300.c:789 config/tc-h8300.c:818
+#: config/tc-h8300.c:736 config/tc-h8300.c:744 config/tc-h8300.c:773
 msgid "expected @(exp, reg16)"
 msgstr ""
 
-#: config/tc-h8300.c:807
+#: config/tc-h8300.c:762
 msgid "expected .L, .W or .B for register in indexed addressing mode"
 msgstr ""
 
-#: config/tc-h8300.c:1000
+#: config/tc-h8300.c:956
 msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""
 msgstr ""
 
-#: config/tc-h8300.c:1018 config/tc-h8300.c:1027
+#: config/tc-h8300.c:974 config/tc-h8300.c:983
 msgid "expected register"
 msgstr ""
 
-#: config/tc-h8300.c:1043
+#: config/tc-h8300.c:999
 msgid "expected closing paren"
 msgstr ""
 
-#: config/tc-h8300.c:1104
+#: config/tc-h8300.c:1058
 #, c-format
 msgid "can't use high part of register in operand %d"
 msgstr ""
 
-#: config/tc-h8300.c:1268
+#: config/tc-h8300.c:1215
 #, c-format
 msgid "Opcode `%s' with these operand types not available in %s mode"
 msgstr ""
 
-#: config/tc-h8300.c:1277
+#: config/tc-h8300.c:1224
 msgid "mismatch between opcode size and operand size"
 msgstr ""
 
-#: config/tc-h8300.c:1316
+#: config/tc-h8300.c:1260
 #, c-format
 msgid "operand %s0x%lx out of range."
 msgstr ""
 
-#: config/tc-h8300.c:1415
+#: config/tc-h8300.c:1356
 msgid "Can't work out size of operand.\n"
 msgstr ""
 
-#: config/tc-h8300.c:1466
+#: config/tc-h8300.c:1405
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300 mode"
 msgstr ""
 
-#: config/tc-h8300.c:1471
+#: config/tc-h8300.c:1410
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300H mode"
 msgstr ""
 
-#: config/tc-h8300.c:1477
+#: config/tc-h8300.c:1416
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300S mode"
 msgstr ""
 
-#: config/tc-h8300.c:1538 config/tc-h8300.c:1558
+#: config/tc-h8300.c:1477 config/tc-h8300.c:1497
 msgid "Need #1 or #2 here"
 msgstr ""
 
-#: config/tc-h8300.c:1553
+#: config/tc-h8300.c:1492
 msgid "#4 not valid on H8/300."
 msgstr ""
 
-#: config/tc-h8300.c:1645 config/tc-h8300.c:1727
+#: config/tc-h8300.c:1598 config/tc-h8300.c:1680
 #, c-format
 msgid "branch operand has odd offset (%lx)\n"
 msgstr ""
 
-#: config/tc-h8300.c:1766
+#: config/tc-h8300.c:1718
 msgid "destination operand must be 16 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1775
+#: config/tc-h8300.c:1727
 msgid "source operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1783
+#: config/tc-h8300.c:1735
 msgid "destination operand must be 16bit absolute address"
 msgstr ""
 
-#: config/tc-h8300.c:1790
+#: config/tc-h8300.c:1742
 msgid "destination operand must be 8 bit register"
 msgstr ""
 
-#: config/tc-h8300.c:1798
+#: config/tc-h8300.c:1750
 msgid "source operand must be 16bit absolute address"
 msgstr ""
 
 #. This seems more sane than saying "too many operands".  We'll
 #. get here only if the trailing trash starts with a comma.
-#: config/tc-h8300.c:1806 config/tc-mmix.c:454 config/tc-mmix.c:466
-#: config/tc-mmix.c:2502 config/tc-mmix.c:2526 config/tc-mmix.c:2802
-#: config/tc-or32.c:640 config/tc-or32.c:854
+#. Types or values of args don't match.
+#: config/tc-h8300.c:1758 config/tc-mmix.c:473 config/tc-mmix.c:485
+#: config/tc-mmix.c:2526 config/tc-mmix.c:2550 config/tc-mmix.c:2823
+#: config/tc-or32.c:527
 msgid "invalid operands"
 msgstr ""
 
-#: config/tc-h8300.c:1839
+#: config/tc-h8300.c:1789
 msgid "operand/size mis-match"
 msgstr ""
 
-#: config/tc-h8300.c:1926 config/tc-h8500.c:1112 config/tc-mips.c:9302
-#: config/tc-sh.c:2363 config/tc-sh64.c:2837 config/tc-w65.c:691
-#: config/tc-z8k.c:1248
+#: config/tc-h8300.c:1885 config/tc-mips.c:9358 config/tc-sh64.c:2795
+#: config/tc-sh.c:2838 config/tc-z8k.c:1204
 msgid "unknown opcode"
 msgstr ""
 
-#: config/tc-h8300.c:2031 config/tc-h8500.c:1139 config/tc-sh.c:2483
-#: config/tc-z8k.c:1304
-msgid "call to tc_crawl_symbol_chain \n"
+#: config/tc-h8300.c:1918
+msgid "invalid operand in ldm"
 msgstr ""
 
-#: config/tc-h8300.c:2047 config/tc-h8500.c:1153 config/tc-sh.c:2490
-#: config/tc-z8k.c:1320
-msgid "call to tc_headers_hook \n"
+#: config/tc-h8300.c:1927
+msgid "invalid operand in stm"
 msgstr ""
 
-#: config/tc-h8300.c:2140
+#: config/tc-h8300.c:2093
+#, c-format
 msgid "call to tc_aout_fix_to_chars \n"
 msgstr ""
 
-#: config/tc-h8300.c:2154
+#: config/tc-h8300.c:2102
+#, c-format
 msgid "call to md_convert_frag \n"
 msgstr ""
 
-#: config/tc-h8300.c:2216
+#: config/tc-h8300.c:2146
+#, c-format
 msgid "call tomd_estimate_size_before_relax \n"
 msgstr ""
 
-#: config/tc-h8300.c:2337 config/tc-mcore.c:2355 config/tc-pj.c:581
-#: config/tc-sh.c:3956
+#: config/tc-h8300.c:2197 config/tc-mcore.c:2282 config/tc-pj.c:538
+#: config/tc-sh.c:4270
 #, c-format
 msgid "Cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-h8500.c:325
-msgid ":24 not valid for this opcode"
-msgstr ""
-
-#: config/tc-h8500.c:332
-msgid "expect :8,:16 or :24"
-msgstr ""
-
-#: config/tc-h8500.c:391
-msgid "syntax error in reg list"
-msgstr ""
-
-#: config/tc-h8500.c:409
-msgid "missing final register in range"
-msgstr ""
-
-#: config/tc-h8500.c:498 config/tc-h8500.c:505 config/tc-h8500.c:511
-msgid "expected @(exp, Rn)"
-msgstr ""
-
-#: config/tc-h8500.c:527
-msgid "@Rn+ needs word register"
-msgstr ""
-
-#: config/tc-h8500.c:537
-msgid "@Rn needs word register"
-msgstr ""
-
-#: config/tc-h8500.c:838 config/tc-sh.c:1827
-#, c-format
-msgid "unhandled %d\n"
-msgstr ""
-
-#: config/tc-h8500.c:868
-#, c-format
-msgid "operand must be absolute in range %d..%d"
-msgstr ""
-
-#: config/tc-h8500.c:963 config/tc-sh.c:2036
-#, c-format
-msgid "failed for %d\n"
-msgstr ""
-
-#: config/tc-h8500.c:1128 config/tc-sh.c:2138 config/tc-sh.c:2412
-#: config/tc-w65.c:710
-msgid "invalid operands for opcode"
-msgstr ""
-
-#. Simple range checking for FIELD againt HIGH and LOW bounds.
+#. Simple range checking for FIELD against HIGH and LOW bounds.
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1156 config/tc-hppa.c:1170
+#. Variant of CHECK_FIELD for use in md_apply_fix and other places where
+#. the current file and line number are not valid.
+#: config/tc-hppa.c:1176 config/tc-hppa.c:1190
 #, c-format
 msgid "Field out of range [%d..%d] (%d)."
 msgstr ""
 
-#. Simple alignment checking for FIELD againt ALIGN (a power of two).
+#. Simple alignment checking for FIELD against ALIGN (a power of two).
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1184
+#: config/tc-hppa.c:1204
 #, c-format
 msgid "Field not properly aligned [%d] (%d)."
 msgstr ""
 
-#: config/tc-hppa.c:1213
+#: config/tc-hppa.c:1233
 msgid "Missing .exit\n"
 msgstr ""
 
-#: config/tc-hppa.c:1216
+#: config/tc-hppa.c:1236
 msgid "Missing .procend\n"
 msgstr ""
 
-#: config/tc-hppa.c:1396
+#: config/tc-hppa.c:1422
 #, c-format
 msgid "Invalid field selector.  Assuming F%%."
 msgstr ""
 
-#: config/tc-hppa.c:1429
+#: config/tc-hppa.c:1455
 msgid "-R option not supported on this target."
 msgstr ""
 
-#: config/tc-hppa.c:1445 config/tc-sparc.c:809 config/tc-sparc.c:845
+#: config/tc-hppa.c:1471 config/tc-sparc.c:811 config/tc-sparc.c:847
 #, c-format
 msgid "Internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:1453 config/tc-i860.c:201
+#: config/tc-hppa.c:1479 config/tc-i860.c:238
 #, c-format
 msgid "internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-hppa.c:1524 config/tc-hppa.c:7048 config/tc-hppa.c:7105
+#: config/tc-hppa.c:1550 config/tc-hppa.c:7065 config/tc-hppa.c:7122
 msgid "Missing function name for .PROC (corrupted label chain)"
 msgstr ""
 
-#: config/tc-hppa.c:1527 config/tc-hppa.c:7108
+#: config/tc-hppa.c:1553 config/tc-hppa.c:7125
 msgid "Missing function name for .PROC"
 msgstr ""
 
-#: config/tc-hppa.c:1634 config/tc-hppa.c:4905
-msgid "could not update architecture and machine"
-msgstr ""
-
-#: config/tc-hppa.c:1842
+#: config/tc-hppa.c:1857
 msgid "Invalid Indexed Load Completer."
 msgstr ""
 
-#: config/tc-hppa.c:1847
+#: config/tc-hppa.c:1862
 msgid "Invalid Indexed Load Completer Syntax."
 msgstr ""
 
-#: config/tc-hppa.c:1884
+#: config/tc-hppa.c:1896
 msgid "Invalid Short Load/Store Completer."
 msgstr ""
 
-#: config/tc-hppa.c:1944 config/tc-hppa.c:1949
+#: config/tc-hppa.c:1956 config/tc-hppa.c:1961
 msgid "Invalid Store Bytes Short Completer"
 msgstr ""
 
-#: config/tc-hppa.c:2260 config/tc-hppa.c:2266
+#: config/tc-hppa.c:2272 config/tc-hppa.c:2278
 msgid "Invalid left/right combination completer"
 msgstr ""
 
-#: config/tc-hppa.c:2315 config/tc-hppa.c:2322
+#: config/tc-hppa.c:2327 config/tc-hppa.c:2334
 msgid "Invalid permutation completer"
 msgstr ""
 
-#: config/tc-hppa.c:2423
+#: config/tc-hppa.c:2434
 #, c-format
 msgid "Invalid Add Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2434 config/tc-hppa.c:2444
+#: config/tc-hppa.c:2445 config/tc-hppa.c:2455
 msgid "Invalid Add and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:2465 config/tc-hppa.c:2603
+#: config/tc-hppa.c:2476 config/tc-hppa.c:2613
 msgid "Invalid Compare/Subtract Condition"
 msgstr ""
 
-#: config/tc-hppa.c:2505
+#: config/tc-hppa.c:2516
 #, c-format
 msgid "Invalid Bit Branch Condition: %c"
 msgstr ""
 
-#: config/tc-hppa.c:2591
+#: config/tc-hppa.c:2601
 #, c-format
 msgid "Invalid Compare/Subtract Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:2618
+#: config/tc-hppa.c:2628
 msgid "Invalid Compare and Branch Condition"
 msgstr ""
 
-#: config/tc-hppa.c:2714
+#: config/tc-hppa.c:2724
 msgid "Invalid Logical Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:2769
+#: config/tc-hppa.c:2779
 msgid "Invalid Shift/Extract/Deposit Condition."
 msgstr ""
 
-#: config/tc-hppa.c:2881
+#: config/tc-hppa.c:2891
 msgid "Invalid Unit Instruction Condition."
 msgstr ""
 
-#: config/tc-hppa.c:3258 config/tc-hppa.c:3290 config/tc-hppa.c:3321
-#: config/tc-hppa.c:3351
+#: config/tc-hppa.c:3270 config/tc-hppa.c:3302 config/tc-hppa.c:3333
+#: config/tc-hppa.c:3363
 msgid "Branch to unaligned address"
 msgstr ""
 
-#: config/tc-hppa.c:3529
+#: config/tc-hppa.c:3541
 msgid "Invalid SFU identifier"
 msgstr ""
 
-#: config/tc-hppa.c:3579
+#: config/tc-hppa.c:3591
 msgid "Invalid COPR identifier"
 msgstr ""
 
-#: config/tc-hppa.c:3708
+#: config/tc-hppa.c:3720
 msgid "Invalid Floating Point Operand Format."
 msgstr ""
 
-#: config/tc-hppa.c:3825 config/tc-hppa.c:3845 config/tc-hppa.c:3865
-#: config/tc-hppa.c:3885 config/tc-hppa.c:3905
+#: config/tc-hppa.c:3837 config/tc-hppa.c:3857 config/tc-hppa.c:3877
+#: config/tc-hppa.c:3897 config/tc-hppa.c:3917
 msgid "Invalid register for single precision fmpyadd or fmpysub"
 msgstr ""
 
-#: config/tc-hppa.c:3962
+#: config/tc-hppa.c:3968 config/tc-hppa.c:4928
+msgid "could not update architecture and machine"
+msgstr ""
+
+#: config/tc-hppa.c:3985
 #, c-format
 msgid "Invalid operands %s"
 msgstr ""
 
-#: config/tc-hppa.c:4080
+#: config/tc-hppa.c:4103
 msgid "Cannot handle fixup"
 msgstr ""
 
-#: config/tc-hppa.c:4381
+#: config/tc-hppa.c:4404
+#, c-format
 msgid "  -Q                      ignored\n"
 msgstr ""
 
-#: config/tc-hppa.c:4385
+#: config/tc-hppa.c:4408
+#, c-format
 msgid "  -c                      print a warning if a comment is found\n"
 msgstr ""
 
-#: config/tc-hppa.c:4456
+#: config/tc-hppa.c:4479
 #, c-format
 msgid "no hppa_fixup entry for fixup type 0x%x"
 msgstr ""
 
-#: config/tc-hppa.c:4627
+#: config/tc-hppa.c:4650
 msgid "Unknown relocation encountered in md_apply_fix."
 msgstr ""
 
-#: config/tc-hppa.c:4769 config/tc-hppa.c:4794
+#: config/tc-hppa.c:4792 config/tc-hppa.c:4817
 #, c-format
 msgid "Undefined register: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:4828
+#: config/tc-hppa.c:4851
 #, c-format
 msgid "Non-absolute symbol: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:4843
+#: config/tc-hppa.c:4866
 #, c-format
 msgid "Undefined absolute constant: '%s'."
 msgstr ""
 
-#: config/tc-hppa.c:4944
+#: config/tc-hppa.c:4967
 #, c-format
 msgid "Invalid FP Compare Condition: %s"
 msgstr ""
 
-#: config/tc-hppa.c:5000
+#: config/tc-hppa.c:5023
 #, c-format
 msgid "Invalid FTEST completer: %s"
 msgstr ""
 
-#: config/tc-hppa.c:5067 config/tc-hppa.c:5105
+#: config/tc-hppa.c:5090 config/tc-hppa.c:5128
 #, c-format
 msgid "Invalid FP Operand Format: %3s"
 msgstr ""
 
-#: config/tc-hppa.c:5184
+#: config/tc-hppa.c:5207
 msgid "Bad segment in expression."
 msgstr ""
 
-#: config/tc-hppa.c:5243
+#: config/tc-hppa.c:5266
 msgid "Bad segment (should be absolute)."
 msgstr ""
 
-#: config/tc-hppa.c:5286
+#: config/tc-hppa.c:5309
 #, c-format
 msgid "Invalid argument location: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:5317
+#: config/tc-hppa.c:5340
 #, c-format
 msgid "Invalid argument description: %d"
 msgstr ""
 
-#: config/tc-hppa.c:5340
+#: config/tc-hppa.c:5363
 #, c-format
 msgid "Invalid Nullification: (%c)"
 msgstr ""
 
-#: config/tc-hppa.c:6060
+#: config/tc-hppa.c:5960
+msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff"
+msgstr ""
+
+#: config/tc-hppa.c:6076
 #, c-format
 msgid "Invalid .CALL argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6182
+#: config/tc-hppa.c:6198
 msgid ".callinfo is not within a procedure definition"
 msgstr ""
 
-#: config/tc-hppa.c:6202
+#: config/tc-hppa.c:6218
 #, c-format
 msgid "FRAME parameter must be a multiple of 8: %d\n"
 msgstr ""
 
-#: config/tc-hppa.c:6221
+#: config/tc-hppa.c:6237
 msgid "Value for ENTRY_GR must be in the range 3..18\n"
 msgstr ""
 
-#: config/tc-hppa.c:6233
+#: config/tc-hppa.c:6249
 msgid "Value for ENTRY_FR must be in the range 12..21\n"
 msgstr ""
 
-#: config/tc-hppa.c:6243
+#: config/tc-hppa.c:6259
 msgid "Value for ENTRY_SR must be 3\n"
 msgstr ""
 
-#: config/tc-hppa.c:6299
+#: config/tc-hppa.c:6315
 #, c-format
 msgid "Invalid .CALLINFO argument: %s"
 msgstr ""
 
-#: config/tc-hppa.c:6410
+#: config/tc-hppa.c:6427
 msgid "The .ENTER pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6426
+#: config/tc-hppa.c:6443
 msgid "Misplaced .entry. Ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6430
+#: config/tc-hppa.c:6447
 msgid "Missing .callinfo."
 msgstr ""
 
-#: config/tc-hppa.c:6496
+#: config/tc-hppa.c:6513
 msgid ".REG expression must be a register"
 msgstr ""
 
-#: config/tc-hppa.c:6512
+#: config/tc-hppa.c:6529
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr ""
 
-#: config/tc-hppa.c:6523
+#: config/tc-hppa.c:6540
 msgid ".REG must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6525
+#: config/tc-hppa.c:6542
 msgid ".EQU must use a label"
 msgstr ""
 
-#: config/tc-hppa.c:6578
+#: config/tc-hppa.c:6595
 msgid ".EXIT must appear within a procedure"
 msgstr ""
 
-#: config/tc-hppa.c:6582
+#: config/tc-hppa.c:6599
 msgid "Missing .callinfo"
 msgstr ""
 
-#: config/tc-hppa.c:6586
+#: config/tc-hppa.c:6603
 msgid "No .ENTRY for this .EXIT"
 msgstr ""
 
-#: config/tc-hppa.c:6613
+#: config/tc-hppa.c:6630
 #, c-format
 msgid "Cannot define export symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:6671
+#: config/tc-hppa.c:6688
 #, c-format
 msgid "Using ENTRY rather than CODE in export directive for %s"
 msgstr ""
 
-#: config/tc-hppa.c:6788
+#: config/tc-hppa.c:6805
 #, c-format
 msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
 msgstr ""
 
-#: config/tc-hppa.c:6870
+#: config/tc-hppa.c:6887
 msgid "Missing label name on .LABEL"
 msgstr ""
 
-#: config/tc-hppa.c:6875
+#: config/tc-hppa.c:6892
 msgid "extra .LABEL arguments ignored."
 msgstr ""
 
-#: config/tc-hppa.c:6892
+#: config/tc-hppa.c:6909
 msgid "The .LEAVE pseudo-op is not supported"
 msgstr ""
 
-#: config/tc-hppa.c:6931
+#: config/tc-hppa.c:6948
 msgid "Unrecognized .LEVEL argument\n"
 msgstr ""
 
-#: config/tc-hppa.c:6967
+#: config/tc-hppa.c:6984
 #, c-format
 msgid "Cannot define static symbol: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7002
+#: config/tc-hppa.c:7019
 msgid "Nested procedures"
 msgstr ""
 
-#: config/tc-hppa.c:7012
+#: config/tc-hppa.c:7029
 msgid "Cannot allocate unwind descriptor\n"
 msgstr ""
 
-#: config/tc-hppa.c:7112
+#: config/tc-hppa.c:7129
 msgid "misplaced .procend"
 msgstr ""
 
-#: config/tc-hppa.c:7115
+#: config/tc-hppa.c:7132
 msgid "Missing .callinfo for this procedure"
 msgstr ""
 
-#: config/tc-hppa.c:7118
+#: config/tc-hppa.c:7135
 msgid "Missing .EXIT for a .ENTRY"
 msgstr ""
 
-#: config/tc-hppa.c:7156
+#: config/tc-hppa.c:7173
 msgid "Not in a space.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7159
+#: config/tc-hppa.c:7176
 msgid "Not in a subspace.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7250
+#: config/tc-hppa.c:7267
 msgid "Invalid .SPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7297
+#: config/tc-hppa.c:7314
 msgid "Can't change spaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7426
+#: config/tc-hppa.c:7443
 #, c-format
 msgid "Undefined space: '%s' Assuming space number = 0."
 msgstr ""
 
-#: config/tc-hppa.c:7450
+#: config/tc-hppa.c:7467
 msgid "Must be in a space before changing or declaring subspaces.\n"
 msgstr ""
 
-#: config/tc-hppa.c:7454
+#: config/tc-hppa.c:7471
 msgid "Can't change subspaces within a procedure definition. Ignored"
 msgstr ""
 
-#: config/tc-hppa.c:7489
+#: config/tc-hppa.c:7507
 msgid "Parameters of an existing subspace can't be modified"
 msgstr ""
 
-#: config/tc-hppa.c:7540
+#: config/tc-hppa.c:7559
 msgid "Alignment must be a power of 2"
 msgstr ""
 
-#: config/tc-hppa.c:7582
+#: config/tc-hppa.c:7606
 msgid "FIRST not supported as a .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7584
+#: config/tc-hppa.c:7608
 msgid "Invalid .SUBSPACE argument"
 msgstr ""
 
-#: config/tc-hppa.c:7764
+#: config/tc-hppa.c:7797
 #, c-format
 msgid "Internal error: Unable to find containing space for %s."
 msgstr ""
 
-#: config/tc-hppa.c:7803
+#: config/tc-hppa.c:7837
 #, c-format
 msgid "Out of memory: could not allocate new space chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:7889
+#: config/tc-hppa.c:7926
 #, c-format
 msgid "Out of memory: could not allocate new subspace chain entry: %s\n"
 msgstr ""
 
-#: config/tc-hppa.c:8622
+#: config/tc-hppa.c:8662
 #, c-format
 msgid "Symbol '%s' could not be created."
 msgstr ""
 
-#: config/tc-hppa.c:8626
+#: config/tc-hppa.c:8666
 msgid "No memory for symbol name."
 msgstr ""
 
-#: config/tc-i386.c:689
+#: config/tc-i386.c:721
 #, c-format
 msgid "%s shortened to %s"
 msgstr ""
 
-#: config/tc-i386.c:745
+#: config/tc-i386.c:777
 msgid "same type of prefix used twice"
 msgstr ""
 
-#: config/tc-i386.c:763
+#: config/tc-i386.c:795
 msgid "64bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:767
+#: config/tc-i386.c:799
 msgid "32bit mode not supported on this CPU."
 msgstr ""
 
-#: config/tc-i386.c:800
+#: config/tc-i386.c:832
 msgid "bad argument to syntax directive."
 msgstr ""
 
-#: config/tc-i386.c:844
+#: config/tc-i386.c:884
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:849
+#: config/tc-i386.c:889
 msgid "missing cpu architecture"
 msgstr ""
 
-#: config/tc-i386.c:863
+#: config/tc-i386.c:903
 #, c-format
 msgid "no such architecture modifier: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:880 config/tc-i386.c:5022
+#: config/tc-i386.c:919 config/tc-i386.c:5342
 msgid "Unknown architecture"
 msgstr ""
 
-#: config/tc-i386.c:915 config/tc-i386.c:938 config/tc-m68k.c:3816
+#: config/tc-i386.c:1247
 #, c-format
-msgid "Internal Error:  Can't hash %s: %s"
+msgid "unknown relocation (%u)"
 msgstr ""
 
-#: config/tc-i386.c:1192
-msgid "There are no unsigned pc-relative relocations"
+#: config/tc-i386.c:1249
+#, c-format
+msgid "%u-byte relocation cannot be applied to %u-byte field"
+msgstr ""
+
+#: config/tc-i386.c:1253
+msgid "non-pc-relative relocation for pc-relative field"
+msgstr ""
+
+#: config/tc-i386.c:1258
+msgid "relocated field and relocation type differ in signedness"
 msgstr ""
 
-#: config/tc-i386.c:1199 config/tc-i386.c:5234
+#: config/tc-i386.c:1267
+msgid "there are no unsigned pc-relative relocations"
+msgstr ""
+
+#: config/tc-i386.c:1275
 #, c-format
-msgid "can not do %d byte pc-relative relocation"
+msgid "cannot do %u byte pc-relative relocation"
+msgstr ""
+
+#: config/tc-i386.c:1292
+#, c-format
+msgid "cannot do %s %u byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:1216
+#: config/tc-i386.c:1496 config/tc-i386.c:2527
 #, c-format
-msgid "can not do %s %d byte relocation"
+msgid "ambiguous operand size for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1428
+#: config/tc-i386.c:1544
 #, c-format
 msgid "can't use register '%%%s' as operand %d in '%s'."
 msgstr ""
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:1457
+#: config/tc-i386.c:1573
 #, c-format
 msgid "translating to `%sp'"
 msgstr ""
 
-#: config/tc-i386.c:1502
+#: config/tc-i386.c:1618
 #, c-format
-msgid "can't encode register '%%%s' in an instruction requiring REX prefix.\n"
+msgid "can't encode register '%%%s' in an instruction requiring REX prefix."
 msgstr ""
 
-#: config/tc-i386.c:1541 config/tc-i386.c:1636
+#: config/tc-i386.c:1659 config/tc-i386.c:1767
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1551 config/tc-i386.c:1668
+#: config/tc-i386.c:1670 config/tc-i386.c:1799
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr ""
 
-#: config/tc-i386.c:1558
+#: config/tc-i386.c:1677
 msgid "expecting prefix; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1560
+#: config/tc-i386.c:1679
 msgid "expecting mnemonic; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1579
+#: config/tc-i386.c:1695 config/tc-i386.c:1818
+#, c-format
+msgid "`%s' is only supported in 64-bit mode"
+msgstr ""
+
+#: config/tc-i386.c:1696 config/tc-i386.c:1817
+#, c-format
+msgid "`%s' is not supported in 64-bit mode"
+msgstr ""
+
+#: config/tc-i386.c:1707
 #, c-format
 msgid "redundant %s prefix"
 msgstr ""
 
-#: config/tc-i386.c:1677
+#: config/tc-i386.c:1824
 #, c-format
-msgid "`%s' is not supported on `%s'"
+msgid "`%s' is not supported on `%s%s'"
 msgstr ""
 
-#: config/tc-i386.c:1682
+#: config/tc-i386.c:1831
 msgid "use .code16 to ensure correct addressing mode"
 msgstr ""
 
-#: config/tc-i386.c:1689
+#: config/tc-i386.c:1844
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr ""
 
-#: config/tc-i386.c:1717
+#: config/tc-i386.c:1878
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1731
+#: config/tc-i386.c:1892
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1734
+#: config/tc-i386.c:1895
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr ""
 
-#: config/tc-i386.c:1743
+#: config/tc-i386.c:1904
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr ""
 
-#: config/tc-i386.c:1770
+#: config/tc-i386.c:1931
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr ""
 
-#: config/tc-i386.c:1793
+#: config/tc-i386.c:1954
 msgid "expecting operand after ','; got nothing"
 msgstr ""
 
-#: config/tc-i386.c:1798
+#: config/tc-i386.c:1959
 msgid "expecting operand before ','; got nothing"
 msgstr ""
 
 #. We found no match.
-#: config/tc-i386.c:2140
+#: config/tc-i386.c:2336
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:2151
+#: config/tc-i386.c:2347
 #, c-format
 msgid "indirect %s without `*'"
 msgstr ""
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:2159
+#: config/tc-i386.c:2355
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr ""
 
-#: config/tc-i386.c:2188 config/tc-i386.c:2203
+#: config/tc-i386.c:2384 config/tc-i386.c:2399
 #, c-format
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr ""
 
-#: config/tc-i386.c:2283
+#: config/tc-i386.c:2509
 msgid ""
 "no instruction mnemonic suffix given and no register operands; can't size "
 "instruction"
@@ -4311,192 +4663,182 @@ msgstr ""
 
 #. Prohibit these changes in the 64bit mode, since the
 #. lowering is more complicated.
-#: config/tc-i386.c:2367 config/tc-i386.c:2426 config/tc-i386.c:2443
-#: config/tc-i386.c:2475 config/tc-i386.c:2508
+#: config/tc-i386.c:2610 config/tc-i386.c:2669 config/tc-i386.c:2686
+#: config/tc-i386.c:2718 config/tc-i386.c:2751
 #, c-format
 msgid "Incorrect register `%%%s' used with `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2375 config/tc-i386.c:2433 config/tc-i386.c:2515
+#: config/tc-i386.c:2618 config/tc-i386.c:2676 config/tc-i386.c:2758
 #, c-format
 msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
 msgstr ""
 
-#: config/tc-i386.c:2390 config/tc-i386.c:2411 config/tc-i386.c:2462
-#: config/tc-i386.c:2493
+#: config/tc-i386.c:2633 config/tc-i386.c:2654 config/tc-i386.c:2705
+#: config/tc-i386.c:2736
 #, c-format
 msgid "`%%%s' not allowed with `%s%c'"
 msgstr ""
 
-#: config/tc-i386.c:2556
+#: config/tc-i386.c:2799
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr ""
 
-#: config/tc-i386.c:2589
+#: config/tc-i386.c:2832
 #, c-format
 msgid ""
 "no instruction mnemonic suffix given; can't determine immediate size %x %c"
 msgstr ""
 
 #. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2638
+#: config/tc-i386.c:2881
 #, c-format
 msgid "translating to `%s %%%s,%%%s'"
 msgstr ""
 
 #. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2645
+#: config/tc-i386.c:2888
 #, c-format
 msgid "translating to `%s %%%s'"
 msgstr ""
 
-#: config/tc-i386.c:2663
+#: config/tc-i386.c:2906
 #, c-format
 msgid "you can't `pop %%cs'"
 msgstr ""
 
-#. lea
-#: config/tc-i386.c:2682
-msgid "segment override on `lea' is ineffectual"
+#: config/tc-i386.c:2927
+#, c-format
+msgid "segment override on `%s' is ineffectual"
 msgstr ""
 
-#: config/tc-i386.c:2991 config/tc-i386.c:3085 config/tc-i386.c:3130
+#: config/tc-i386.c:3236 config/tc-i386.c:3330 config/tc-i386.c:3375
 msgid "skipping prefixes on this instruction"
 msgstr ""
 
-#: config/tc-i386.c:3150
+#: config/tc-i386.c:3395
 msgid "16-bit jump out of range"
 msgstr ""
 
-#: config/tc-i386.c:3159
+#: config/tc-i386.c:3404
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3601
+#: config/tc-i386.c:3897
 #, c-format
-msgid "@%s reloc is not supported in %s bit mode"
+msgid "@%s reloc is not supported with %d-bit output format"
 msgstr ""
 
-#: config/tc-i386.c:3677
+#: config/tc-i386.c:3986
 msgid "only 1 or 2 immediate operands are allowed"
 msgstr ""
 
-#: config/tc-i386.c:3700 config/tc-i386.c:3892
+#: config/tc-i386.c:4007 config/tc-i386.c:4218
 #, c-format
 msgid "junk `%s' after expression"
 msgstr ""
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3711
+#: config/tc-i386.c:4016
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr ""
 
-#: config/tc-i386.c:3743 config/tc-i386.c:3958
+#: config/tc-i386.c:4041 config/tc-i386.c:4277
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr ""
 
-#: config/tc-i386.c:3745 config/tc-i386.c:3960
-#, c-format
-msgid "unimplemented segment type %d in operand"
-msgstr ""
-
-#: config/tc-i386.c:3789 config/tc-i386.c:6011
+#: config/tc-i386.c:4088
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr ""
 
-#: config/tc-i386.c:3796
+#: config/tc-i386.c:4097
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr ""
 
-#: config/tc-i386.c:3912
+#: config/tc-i386.c:4236
 #, c-format
 msgid "bad expression used with @%s"
 msgstr ""
 
-#. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3934
-#, c-format
-msgid "missing or invalid displacement expression `%s' taken as 0"
-msgstr ""
-
-#: config/tc-i386.c:4058
+#: config/tc-i386.c:4386
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4062
+#: config/tc-i386.c:4390
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr ""
 
-#: config/tc-i386.c:4137
+#: config/tc-i386.c:4464
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4152
+#: config/tc-i386.c:4479
 #, c-format
 msgid "junk `%s' after register"
 msgstr ""
 
-#: config/tc-i386.c:4161 config/tc-i386.c:4276 config/tc-i386.c:4314
+#: config/tc-i386.c:4488 config/tc-i386.c:4603 config/tc-i386.c:4641
 #, c-format
 msgid "bad register name `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4169
+#: config/tc-i386.c:4496
 msgid "immediate operand illegal with absolute jump"
 msgstr ""
 
-#: config/tc-i386.c:4191
+#: config/tc-i386.c:4518
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4269
+#: config/tc-i386.c:4596
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4293
+#: config/tc-i386.c:4620
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4300
+#: config/tc-i386.c:4627
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr ""
 
-#: config/tc-i386.c:4307
+#: config/tc-i386.c:4634
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr ""
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:4348
+#: config/tc-i386.c:4675
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr ""
 
-#: config/tc-i386.c:4531
+#: config/tc-i386.c:4850
 msgid "long jump required"
 msgstr ""
 
-#: config/tc-i386.c:4805
+#: config/tc-i386.c:5127
 msgid "Bad call to md_atof ()"
 msgstr ""
 
-#: config/tc-i386.c:4973
+#: config/tc-i386.c:5294
 msgid "No compiled in support for x86_64"
 msgstr ""
 
-#: config/tc-i386.c:4994
+#: config/tc-i386.c:5315
+#, c-format
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
@@ -4506,417 +4848,501 @@ msgid ""
 "  -s                      ignored\n"
 msgstr ""
 
-#: config/tc-i386.c:5002
+#: config/tc-i386.c:5323
+#, c-format
 msgid ""
 "  -n                      Do not optimize code alignment\n"
 "  -q                      quieten some warnings\n"
 msgstr ""
 
-#: config/tc-i386.c:5104 config/tc-s390.c:1841
+#: config/tc-i386.c:5425 config/tc-s390.c:1861
 msgid "GOT already in symbol table"
 msgstr ""
 
-#: config/tc-i386.c:5249
+#: config/tc-i386.c:5568
+#, c-format
+msgid "can not do %d byte pc-relative relocation"
+msgstr ""
+
+#: config/tc-i386.c:5586
 #, c-format
 msgid "can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-i386.c:5317 config/tc-s390.c:2285
+#: config/tc-i386.c:5657 config/tc-s390.c:2307
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr ""
 
-#: config/tc-i386.c:5613
+#: config/tc-i386.c:5912
+#, c-format
+msgid "invalid operand for '%s' ('%s' unexpected)"
+msgstr ""
+
+#: config/tc-i386.c:5924
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr ""
 
-#: config/tc-i386.c:5776
+#. See the comments in intel_bracket_expr.
+#: config/tc-i386.c:5935
 #, c-format
-msgid "Unknown operand modifier `%s'\n"
+msgid "Treating `%s' as memory reference"
 msgstr ""
 
-#: config/tc-i386.c:5983
+#: config/tc-i386.c:6247
+#, c-format
+msgid "Unknown operand modifier `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6262
+msgid "Conflicting operand modifiers"
+msgstr ""
+
+#: config/tc-i386.c:6311
+msgid "Invalid operand to `OFFSET'"
+msgstr ""
+
+#: config/tc-i386.c:6384
+#, c-format
+msgid "`[%.*s]' taken to mean just `%.*s'"
+msgstr ""
+
+#: config/tc-i386.c:6474
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr ""
 
-#: config/tc-i386.c:5993 config/tc-i386.c:6114
-msgid "Register scaling only allowed in memory operands."
+#: config/tc-i386.c:6478
+msgid "Extra segment override ignored"
 msgstr ""
 
-#: config/tc-i386.c:6024
-msgid "Too many register references in memory operand.\n"
+#: config/tc-i386.c:6512 config/tc-i386.c:6681
+msgid "Register scaling only allowed in memory operands"
 msgstr ""
 
-#: config/tc-i386.c:6093
+#: config/tc-i386.c:6534 config/tc-i386.c:6658
 #, c-format
-msgid "Syntax error. Expecting a constant. Got `%s'.\n"
+msgid "Syntax error: Expecting a constant, got `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6562
+msgid "Too many register references in memory operand"
+msgstr ""
+
+#: config/tc-i386.c:6573
+msgid "Using register names in OFFSET expressions is deprecated"
 msgstr ""
 
-#: config/tc-i386.c:6163
+#: config/tc-i386.c:6586
+msgid "Invalid use of register"
+msgstr ""
+
+#: config/tc-i386.c:6731
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr ""
 
-#: config/tc-i386.c:6180
+#: config/tc-i386.c:6748
 #, c-format
-msgid "Unexpected token `%s'\n"
+msgid "Unexpected token `%s'"
+msgstr ""
+
+#: config/tc-i386.c:6910
+msgid "`:' expected"
 msgstr ""
 
-#: config/tc-i386.c:6324
+#: config/tc-i386.c:6935
 #, c-format
-msgid "Unrecognized token `%s'\n"
+msgid "Unrecognized token `%s'"
+msgstr ""
+
+#: config/tc-i386.c:7070
+msgid "Bad .section directive: want a,l,w,x,M,S,G,T in string"
+msgstr ""
+
+#: config/tc-i386.c:7073
+msgid "Bad .section directive: want a,w,x,M,S,G,T in string"
+msgstr ""
+
+#: config/tc-i386.c:7092
+msgid ".largecomm supported only in 64bit mode, producing .comm"
+msgstr ""
+
+#: config/tc-i860.c:124
+msgid "Directive .dual available only with -mintel-syntax option"
+msgstr ""
+
+#: config/tc-i860.c:134
+msgid "Directive .enddual available only with -mintel-syntax option"
+msgstr ""
+
+#: config/tc-i860.c:147
+msgid "Directive .atmp available only with -mintel-syntax option"
 msgstr ""
 
-#: config/tc-i860.c:165 config/tc-i860.c:169
+#: config/tc-i860.c:169 config/tc-i860.c:173
 msgid "Unknown temporary pseudo register"
 msgstr ""
 
-#: config/tc-i860.c:192 config/tc-mips.c:1105
+#: config/tc-i860.c:229 config/tc-mips.c:1412
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr ""
 
-#: config/tc-i860.c:212
+#: config/tc-i860.c:249
 msgid "Defective assembler.  No assembly attempted."
 msgstr ""
 
-#: config/tc-i860.c:362
+#: config/tc-i860.c:395 config/tc-i860.c:940 config/tc-m68k.c:3443
+#: config/tc-m68k.c:3475 config/tc-sparc.c:2657
+msgid "failed sanity check."
+msgstr ""
+
+#: config/tc-i860.c:402
 #, c-format
 msgid "Expanded opcode after delayed branch: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:366
+#: config/tc-i860.c:406
 #, c-format
 msgid "Expanded opcode in dual mode: `%s'"
 msgstr ""
 
-#: config/tc-i860.c:370
+#: config/tc-i860.c:410
 #, c-format
 msgid "An instruction was expanded (%s)"
 msgstr ""
 
-#: config/tc-i860.c:643
+#: config/tc-i860.c:676
 msgid "Pipelined instruction: fsrc1 = fdest"
 msgstr ""
 
-#: config/tc-i860.c:844 config/tc-i860.c:851 config/tc-i860.c:858
+#: config/tc-i860.c:879 config/tc-i860.c:886 config/tc-i860.c:893
 msgid "Assembler does not yet support PIC"
 msgstr ""
 
-#: config/tc-i860.c:919
+#: config/tc-i860.c:957
 #, c-format
 msgid "Illegal operands for %s"
 msgstr ""
 
-#: config/tc-i860.c:947 config/tc-sparc.c:2834
-msgid "bad segment"
+#: config/tc-i860.c:974
+#, c-format
+msgid "'d.%s' must be 8-byte aligned"
 msgstr ""
 
-#: config/tc-i860.c:1037
+#: config/tc-i860.c:982
+#, c-format
+msgid "Prefix 'd.' invalid for instruction `%s'"
+msgstr ""
+
+#: config/tc-i860.c:1088
 msgid "i860_estimate_size_before_relax\n"
 msgstr ""
 
-#: config/tc-i860.c:1134
+#: config/tc-i860.c:1187
+#, c-format
 msgid ""
 "  -EL\t\t\t  generate code for little endian mode (default)\n"
 "  -EB\t\t\t  generate code for big endian mode\n"
 "  -mwarn-expand\t\t  warn if pseudo operations are expanded\n"
 "  -mxp\t\t\t  enable i860XP support (disabled by default)\n"
+"  -mintel-syntax\t  enable Intel syntax (default to AT&T/SVR4)\n"
 msgstr ""
 
 #. SVR4 compatibility flags.
-#: config/tc-i860.c:1141
+#: config/tc-i860.c:1195
+#, c-format
 msgid ""
 "  -V\t\t\t  print assembler version number\n"
 "  -Qy, -Qn\t\t  ignored\n"
 msgstr ""
 
-#: config/tc-i860.c:1210
+#: config/tc-i860.c:1258
 msgid "This immediate requires 0 MOD 2 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1213
+#: config/tc-i860.c:1261
 msgid "This immediate requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1216
+#: config/tc-i860.c:1264
 msgid "This immediate requires 0 MOD 8 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1219
+#: config/tc-i860.c:1267
 msgid "This immediate requires 0 MOD 16 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1317
+#: config/tc-i860.c:1362
 msgid "5-bit immediate too large"
 msgstr ""
 
-#: config/tc-i860.c:1320
+#: config/tc-i860.c:1365
 msgid "5-bit field must be absolute"
 msgstr ""
 
-#: config/tc-i860.c:1365 config/tc-i860.c:1388
+#: config/tc-i860.c:1410 config/tc-i860.c:1433
 msgid "A branch offset requires 0 MOD 4 alignment"
 msgstr ""
 
-#: config/tc-i860.c:1409
+#: config/tc-i860.c:1454
 #, c-format
 msgid "Unrecognized fix-up (0x%08lx)"
 msgstr ""
 
-#: config/tc-i860.h:80
+#: config/tc-i860.h:76
 msgid "i860_convert_frag\n"
 msgstr ""
 
-#: config/tc-i960.c:574
+#: config/tc-i960.c:488
 #, c-format
 msgid "Hashing returned \"%s\"."
 msgstr ""
 
-#. Offset of last character in opcode mnemonic
-#: config/tc-i960.c:608
-msgid "branch prediction invalid on this opcode"
-msgstr ""
-
-#: config/tc-i960.c:648
-#, c-format
-msgid "invalid opcode, \"%s\"."
+#: config/tc-i960.c:584 config/tc-i960.c:1114
+msgid "expression syntax error"
 msgstr ""
 
-#: config/tc-i960.c:653
-#, c-format
-msgid "improper number of operands.  expecting %d, got %d"
+#: config/tc-i960.c:620
+msgid "attempt to branch into different segment"
 msgstr ""
 
-#: config/tc-i960.c:877
+#: config/tc-i960.c:624
 #, c-format
-msgid "Fixup of %ld too large for field width of %d"
+msgid "target of %s instruction must be a label"
 msgstr ""
 
-#: config/tc-i960.c:994
-#, c-format
-msgid "invalid architecture %s"
+#: config/tc-i960.c:734
+msgid "unaligned register"
 msgstr ""
 
-#: config/tc-i960.c:1014
-msgid "I960 options:\n"
+#: config/tc-i960.c:756
+msgid "no such sfr in this architecture"
 msgstr ""
 
-#: config/tc-i960.c:1017
-msgid ""
-"\n"
-"\t\t\tspecify variant of 960 architecture\n"
-"-b\t\t\tadd code to collect statistics about branches taken\n"
-"-link-relax\t\tpreserve individual alignment directives so linker\n"
-"\t\t\tcan do relaxing (b.out format only)\n"
-"-no-relax\t\tdon't alter compare-and-branch instructions for\n"
-"\t\t\tlong displacements\n"
+#: config/tc-i960.c:794
+msgid "illegal literal"
 msgstr ""
 
-#: config/tc-i960.c:1419 config/tc-xtensa.c:8604
-msgid "too many operands"
+#: config/tc-i960.c:837
+msgid "unmatched '['"
 msgstr ""
 
-#: config/tc-i960.c:1477 config/tc-i960.c:1702
-msgid "expression syntax error"
+#: config/tc-i960.c:844
+msgid "garbage after index spec ignored"
 msgstr ""
 
-#: config/tc-i960.c:1515
-msgid "attempt to branch into different segment"
+#: config/tc-i960.c:944
+msgid "invalid index register"
 msgstr ""
 
-#: config/tc-i960.c:1519
-#, c-format
-msgid "target of %s instruction must be a label"
+#: config/tc-i960.c:967
+msgid "invalid scale factor"
 msgstr ""
 
-#: config/tc-i960.c:1557
-msgid "unmatched '['"
+#: config/tc-i960.c:1191
+msgid "architecture of opcode conflicts with that of earlier instruction(s)"
 msgstr ""
 
-#: config/tc-i960.c:1568
-msgid "garbage after index spec ignored"
+#: config/tc-i960.c:1425 config/tc-xtensa.c:11295
+msgid "too many operands"
 msgstr ""
 
 #. We never moved: there was no opcode either!
-#: config/tc-i960.c:1633
+#: config/tc-i960.c:1473
 msgid "missing opcode"
 msgstr ""
 
-#: config/tc-i960.c:2046
-msgid "invalid index register"
+#: config/tc-i960.c:1613
+msgid "branch prediction invalid on this opcode"
 msgstr ""
 
-#: config/tc-i960.c:2069
-msgid "invalid scale factor"
+#: config/tc-i960.c:1651
+#, c-format
+msgid "invalid opcode, \"%s\"."
 msgstr ""
 
-#: config/tc-i960.c:2250
-msgid "unaligned register"
+#: config/tc-i960.c:1653
+#, c-format
+msgid "improper number of operands.  expecting %d, got %d"
 msgstr ""
 
-#: config/tc-i960.c:2273
-msgid "no such sfr in this architecture"
+#: config/tc-i960.c:1810
+#, c-format
+msgid "Fixup of %ld too large for field width of %d"
 msgstr ""
 
-#: config/tc-i960.c:2311
-msgid "illegal literal"
+#: config/tc-i960.c:1920
+#, c-format
+msgid "invalid architecture %s"
 msgstr ""
 
-#. Should not happen: see block comment above
-#: config/tc-i960.c:2539
+#: config/tc-i960.c:1940
 #, c-format
-msgid "Trying to 'bal' to %s"
+msgid "I960 options:\n"
 msgstr ""
 
-#: config/tc-i960.c:2550
-msgid "Looks like a proc, but can't tell what kind.\n"
+#: config/tc-i960.c:1943
+#, c-format
+msgid ""
+"\n"
+"\t\t\tspecify variant of 960 architecture\n"
+"-b\t\t\tadd code to collect statistics about branches taken\n"
+"-link-relax\t\tpreserve individual alignment directives so linker\n"
+"\t\t\tcan do relaxing (b.out format only)\n"
+"-no-relax\t\tdon't alter compare-and-branch instructions for\n"
+"\t\t\tlong displacements\n"
 msgstr ""
 
-#: config/tc-i960.c:2582
+#: config/tc-i960.c:2207
 msgid "should have 1 or 2 operands"
 msgstr ""
 
-#: config/tc-i960.c:2591 config/tc-i960.c:2610
+#: config/tc-i960.c:2215 config/tc-i960.c:2230
 #, c-format
 msgid "Redefining leafproc %s"
 msgstr ""
 
-#: config/tc-i960.c:2641
+#: config/tc-i960.c:2260
 msgid "should have two operands"
 msgstr ""
 
-#: config/tc-i960.c:2651
+#: config/tc-i960.c:2270
 msgid "'entry_num' must be absolute number in [0,31]"
 msgstr ""
 
-#: config/tc-i960.c:2660
+#: config/tc-i960.c:2278
 #, c-format
 msgid "Redefining entrynum for sysproc %s"
 msgstr ""
 
-#: config/tc-i960.c:2764
-msgid "architecture of opcode conflicts with that of earlier instruction(s)"
+#. Should not happen: see block comment above.
+#: config/tc-i960.c:2378
+#, c-format
+msgid "Trying to 'bal' to %s"
+msgstr ""
+
+#: config/tc-i960.c:2388
+msgid "Looks like a proc, but can't tell what kind.\n"
 msgstr ""
 
-#: config/tc-i960.c:2785
+#: config/tc-i960.c:2407
 msgid "big endian mode is not supported"
 msgstr ""
 
-#: config/tc-i960.c:2787
+#: config/tc-i960.c:2409
 #, c-format
 msgid "ignoring unrecognized .endian type `%s'"
 msgstr ""
 
-#: config/tc-i960.c:3071
-#, c-format
-msgid "leafproc symbol '%s' undefined"
+#: config/tc-i960.c:2454
+msgid "can't use COBR format with external label"
 msgstr ""
 
-#: config/tc-i960.c:3081
-#, c-format
-msgid "Warning: making leafproc entries %s and %s both global\n"
+#: config/tc-i960.c:2629
+msgid "option --link-relax is only supported in b.out format"
 msgstr ""
 
-#: config/tc-i960.c:3190
-msgid "option --link-relax is only supported in b.out format"
+#: config/tc-i960.c:2656
+#, c-format
+msgid "No 'bal' entry point for leafproc %s"
 msgstr ""
 
-#: config/tc-ia64.c:982
+#: config/tc-ia64.c:1008
 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ia64.c:1105
+#: config/tc-ia64.c:1151
 msgid "Unwind directive not followed by an instruction."
 msgstr ""
 
-#: config/tc-ia64.c:4563
+#: config/tc-ia64.c:5114
 msgid "Register name expected"
 msgstr ""
 
-#: config/tc-ia64.c:4568 config/tc-ia64.c:4854
+#: config/tc-ia64.c:5119 config/tc-ia64.c:5435
 msgid "Comma expected"
 msgstr ""
 
-#: config/tc-ia64.c:4576
+#: config/tc-ia64.c:5127
 msgid "Register value annotation ignored"
 msgstr ""
 
-#: config/tc-ia64.c:4600
+#: config/tc-ia64.c:5168
 msgid "Directive invalid within a bundle"
 msgstr ""
 
-#: config/tc-ia64.c:4667
+#: config/tc-ia64.c:5261
 msgid "Missing predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:4683
+#: config/tc-ia64.c:5267
 msgid "Unrecognized predicate relation type"
 msgstr ""
 
-#: config/tc-ia64.c:4703 config/tc-ia64.c:4728
-msgid "Predicate register expected"
+#: config/tc-ia64.c:5314
+msgid "Bad register range"
 msgstr ""
 
-#: config/tc-ia64.c:4715
-msgid "Duplicate predicate register ignored"
+#: config/tc-ia64.c:5323
+msgid "Predicate register expected"
 msgstr ""
 
-#: config/tc-ia64.c:4737
-msgid "Bad register range"
+#: config/tc-ia64.c:5328
+msgid "Duplicate predicate register ignored"
 msgstr ""
 
-#: config/tc-ia64.c:4765
+#: config/tc-ia64.c:5346
 msgid "Predicate source and target required"
 msgstr ""
 
-#: config/tc-ia64.c:4767 config/tc-ia64.c:4779
+#: config/tc-ia64.c:5348 config/tc-ia64.c:5360
 msgid "Use of p0 is not valid in this context"
 msgstr ""
 
-#: config/tc-ia64.c:4774
+#: config/tc-ia64.c:5355
 msgid "At least two PR arguments expected"
 msgstr ""
 
-#: config/tc-ia64.c:4788
+#: config/tc-ia64.c:5369
 msgid "At least one PR argument expected"
 msgstr ""
 
-#: config/tc-ia64.c:4824
+#: config/tc-ia64.c:5405
 #, c-format
 msgid "Inserting \"%s\" into entry hint table failed: %s"
 msgstr ""
 
 #. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:5302
+#: config/tc-ia64.c:5881
 msgid "62-bit relocation not yet implemented"
 msgstr ""
 
 #. XXX technically, this is wrong: we should not be issuing warning
 #. messages until we're sure this instruction pattern is going to
 #. be used!
-#: config/tc-ia64.c:5375
+#: config/tc-ia64.c:5954
 msgid "lower 16 bits of mask ignored"
 msgstr ""
 
-#: config/tc-ia64.c:5939
+#: config/tc-ia64.c:6569
 msgid "Value truncated to 62 bits"
 msgstr ""
 
-#: config/tc-ia64.c:6291
-msgid ""
-"Additional NOP may be necessary to workaround Itanium processor A/B step "
-"errata"
+#. Give an error if a frag containing code is not aligned to a 16 byte
+#. boundary.
+#: config/tc-ia64.c:6707 config/tc-ia64.h:171
+msgid "instruction address is not a multiple of 16"
 msgstr ""
 
-#: config/tc-ia64.c:6474
+#: config/tc-ia64.c:7249
 #, c-format
 msgid "Unrecognized option '-x%s'"
 msgstr ""
 
-#: config/tc-ia64.c:6502
+#: config/tc-ia64.c:7277
 msgid ""
 "IA-64 options:\n"
 "  --mconstant-gp\t  mark output file as using the constant-GP model\n"
@@ -4926,264 +5352,386 @@ msgid ""
 "\t\t\t  EF_IA_64_NOFUNCDESC_CONS_GP)\n"
 "  -milp32|-milp64|-mlp64|-mp64\tselect data model (default -mlp64)\n"
 "  -mle | -mbe\t\t  select little- or big-endian byte order (default -mle)\n"
-"  -x | -xexplicit\t  turn on dependency violation checking (default)\n"
-"  -xauto\t\t  automagically remove dependency violations\n"
+"  -mtune=[itanium1|itanium2]\n"
+"\t\t\t  tune for a specific CPU (default -mtune=itanium2)\n"
+"  -munwind-check=[warning|error]\n"
+"\t\t\t  unwind directive check (default -munwind-check=warning)\n"
+"  -mhint.b=[ok|warning|error]\n"
+"\t\t\t  hint.b check (default -mhint.b=error)\n"
+"  -x | -xexplicit\t  turn on dependency violation checking\n"
+"  -xauto\t\t  automagically remove dependency violations (default)\n"
+"  -xnone\t\t  turn off dependency violation checking\n"
 "  -xdebug\t\t  debug dependency violation checker\n"
+"  -xdebugn\t\t  debug dependency violation checker but turn off\n"
+"\t\t\t  dependency violation checking\n"
+"  -xdebugx\t\t  debug dependency violation checker and turn on\n"
+"\t\t\t  dependency violation checking\n"
 msgstr ""
 
-#: config/tc-ia64.c:6521
+#: config/tc-ia64.c:7307
 msgid "--gstabs is not supported for ia64"
 msgstr ""
 
-#: config/tc-ia64.c:6824 config/tc-mips.c:1094
+#: config/tc-ia64.c:7641 config/tc-mips.c:1401
 msgid "Could not set architecture and machine"
 msgstr ""
 
-#: config/tc-ia64.c:6931
+#: config/tc-ia64.c:7767
 msgid "Explicit stops are ignored in auto mode"
 msgstr ""
 
-#: config/tc-ia64.c:6981
+#: config/tc-ia64.c:7789
 msgid "Found '{' after explicit switch to automatic mode"
 msgstr ""
 
-#: config/tc-ia64.c:7428
+#: config/tc-ia64.c:8392
 #, c-format
 msgid "Unhandled dependency %s for %s (%s), note %d"
 msgstr ""
 
-#: config/tc-ia64.c:8704
+#: config/tc-ia64.c:9667
 #, c-format
 msgid "Unrecognized dependency specifier %d\n"
 msgstr ""
 
-#: config/tc-ia64.c:9506
+#: config/tc-ia64.c:10561
 msgid "Only the first path encountering the conflict is reported"
 msgstr ""
 
-#: config/tc-ia64.c:9509
+#: config/tc-ia64.c:10564
 msgid "This is the location of the conflicting usage"
 msgstr ""
 
-#: config/tc-ia64.c:10778 read.c:1370 read.c:1976 read.c:2184 read.c:2795
+#: config/tc-ia64.c:11788
+msgid "Can't add stop bit to mark end of instruction group"
+msgstr ""
+
+#: config/tc-ia64.c:11888 read.c:1440 read.c:2206 read.c:2846 read.c:3173
+#: read.c:3204
 msgid "expected symbol name"
 msgstr ""
 
-#: config/tc-ia64.c:10788 read.c:1380 read.c:2194 read.c:2805 stabs.c:478
+#: config/tc-ia64.c:11898 read.c:2216 read.c:2856 read.c:3188 stabs.c:466
 #, c-format
 msgid "expected comma after \"%s\""
 msgstr ""
 
-#: config/tc-ia64.c:10829
+#: config/tc-ia64.c:11940
 #, c-format
 msgid "`%s' is already the alias of %s `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:10839
+#: config/tc-ia64.c:11950
 #, c-format
 msgid "%s `%s' already has an alias `%s'"
 msgstr ""
 
-#: config/tc-ia64.c:10850
+#: config/tc-ia64.c:11961
 #, c-format
 msgid "inserting \"%s\" into %s alias hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:10858
+#: config/tc-ia64.c:11969
 #, c-format
 msgid "inserting \"%s\" into %s name hash table failed: %s"
 msgstr ""
 
-#: config/tc-ia64.c:10877
+#: config/tc-ia64.c:11988
 #, c-format
 msgid "symbol `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ia64.c:10899
+#: config/tc-ia64.c:12010
 #, c-format
 msgid "section `%s' aliased to `%s' is not used"
 msgstr ""
 
-#: config/tc-ip2k.c:123
+#: config/tc-ip2k.c:158
+#, c-format
 msgid "IP2K specific command line options:\n"
 msgstr ""
 
-#: config/tc-ip2k.c:124
+#: config/tc-ip2k.c:159
+#, c-format
 msgid "  -mip2022               restrict to IP2022 insns \n"
 msgstr ""
 
-#: config/tc-ip2k.c:125
+#: config/tc-ip2k.c:160
+#, c-format
 msgid "  -mip2022ext            permit extended IP2022 insn\n"
 msgstr ""
 
-#: config/tc-ip2k.c:246
+#: config/tc-ip2k.c:274
 msgid "md_pcrel_from\n"
 msgstr ""
 
+#: config/tc-m32c.c:128
+#, c-format
+msgid " M32C specific command line options:\n"
+msgstr ""
+
 #. Pretend that we do not recognise this option.
-#: config/tc-m32r.c:233
+#: config/tc-m32r.c:332
 msgid "Unrecognised option: -hidden"
 msgstr ""
 
-#: config/tc-m32r.c:267
+#: config/tc-m32r.c:359 config/tc-sparc.c:593
+msgid "Unrecognized option following -K"
+msgstr ""
+
+#: config/tc-m32r.c:374
+#, c-format
 msgid " M32R specific command line options:\n"
 msgstr ""
 
-#: config/tc-m32r.c:269
+#: config/tc-m32r.c:376
+#, c-format
 msgid ""
 "  -m32r                   disable support for the m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:271
+#: config/tc-m32r.c:378
+#, c-format
 msgid "  -m32rx                  support the extended m32rx instruction set\n"
 msgstr ""
 
-#: config/tc-m32r.c:273
-msgid "  -O                      try to combine instructions in parallel\n"
+#: config/tc-m32r.c:380
+#, c-format
+msgid "  -m32r2                  support the extended m32r2 instruction set\n"
+msgstr ""
+
+#: config/tc-m32r.c:382
+#, c-format
+msgid "  -EL,-little             produce little endian code and data\n"
+msgstr ""
+
+#: config/tc-m32r.c:384
+#, c-format
+msgid "  -EB,-big                produce big endian code and data\n"
 msgstr ""
 
-#: config/tc-m32r.c:276
+#: config/tc-m32r.c:386
+#, c-format
+msgid "  -parallel               try to combine instructions in parallel\n"
+msgstr ""
+
+#: config/tc-m32r.c:388
+#, c-format
+msgid "  -no-parallel            disable -parallel\n"
+msgstr ""
+
+#: config/tc-m32r.c:390
+#, c-format
+msgid ""
+"  -no-bitinst             disallow the M32R2's extended bit-field "
+"instructions\n"
+msgstr ""
+
+#: config/tc-m32r.c:392
+#, c-format
+msgid "  -O                      try to optimize code.  Implies -parallel\n"
+msgstr ""
+
+#: config/tc-m32r.c:395
+#, c-format
 msgid ""
 "  -warn-explicit-parallel-conflicts     warn when parallel instructions\n"
 msgstr ""
 
-#: config/tc-m32r.c:278
-msgid "                                         violate contraints\n"
+#: config/tc-m32r.c:397
+#, c-format
+msgid "                                         might violate contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:280
+#: config/tc-m32r.c:399
+#, c-format
 msgid "  -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"
 msgstr ""
 
-#: config/tc-m32r.c:282
+#: config/tc-m32r.c:401
+#, c-format
 msgid ""
-"                                         instructions violate contraints\n"
+"                                         instructions might violate "
+"contraints\n"
 msgstr ""
 
-#: config/tc-m32r.c:284
+#: config/tc-m32r.c:403
+#, c-format
 msgid ""
 "  -Wp                     synonym for -warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:286
+#: config/tc-m32r.c:405
+#, c-format
 msgid ""
 "  -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"
 msgstr ""
 
-#: config/tc-m32r.c:289
+#: config/tc-m32r.c:407
+#, c-format
+msgid ""
+"  -ignore-parallel-conflicts            do not check parallel instructions\n"
+msgstr ""
+
+#: config/tc-m32r.c:409
+#, c-format
+msgid "                                         fo contraint violations\n"
+msgstr ""
+
+#: config/tc-m32r.c:411
+#, c-format
+msgid ""
+"  -no-ignore-parallel-conflicts         check parallel instructions for\n"
+msgstr ""
+
+#: config/tc-m32r.c:413
+#, c-format
+msgid "                                         contraint violations\n"
+msgstr ""
+
+#: config/tc-m32r.c:415
+#, c-format
+msgid "  -Ip                     synonym for -ignore-parallel-conflicts\n"
+msgstr ""
+
+#: config/tc-m32r.c:417
+#, c-format
+msgid "  -nIp                    synonym for -no-ignore-parallel-conflicts\n"
+msgstr ""
+
+#: config/tc-m32r.c:420
+#, c-format
 msgid ""
 "  -warn-unmatched-high    warn when an (s)high reloc has no matching low "
 "reloc\n"
 msgstr ""
 
-#: config/tc-m32r.c:291
+#: config/tc-m32r.c:422
+#, c-format
 msgid "  -no-warn-unmatched-high do not warn about missing low relocs\n"
 msgstr ""
 
-#: config/tc-m32r.c:293
+#: config/tc-m32r.c:424
+#, c-format
 msgid "  -Wuh                    synonym for -warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:295
+#: config/tc-m32r.c:426
+#, c-format
 msgid "  -Wnuh                   synonym for -no-warn-unmatched-high\n"
 msgstr ""
 
-#: config/tc-m32r.c:299
-msgid "  -relax                 create linker relaxable code\n"
-msgstr ""
-
-#: config/tc-m32r.c:301
-msgid "  -cpu-desc              provide runtime cpu description file\n"
+#: config/tc-m32r.c:429
+#, c-format
+msgid "  -KPIC                   generate PIC\n"
 msgstr ""
 
-#: config/tc-m32r.c:700
-msgid "Instructions write to the same destination register."
+#: config/tc-m32r.c:850
+msgid "instructions write to the same destination register."
 msgstr ""
 
-#: config/tc-m32r.c:708
+#: config/tc-m32r.c:858
 msgid "Instructions do not use parallel execution pipelines."
 msgstr ""
 
-#: config/tc-m32r.c:715
+#: config/tc-m32r.c:866
 msgid "Instructions share the same execution pipeline"
 msgstr ""
 
-#: config/tc-m32r.c:791 config/tc-m32r.c:887
+#: config/tc-m32r.c:931 config/tc-m32r.c:1045
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:798 config/tc-m32r.c:894 config/tc-m32r.c:1050
+#: config/tc-m32r.c:943 config/tc-m32r.c:1057 config/tc-m32r.c:1241
+#, c-format
+msgid "instruction '%s' is for the M32R2 only"
+msgstr ""
+
+#: config/tc-m32r.c:956 config/tc-m32r.c:1070 config/tc-m32r.c:1254
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr ""
 
-#: config/tc-m32r.c:807 config/tc-m32r.c:901 config/tc-m32r.c:1057
+#: config/tc-m32r.c:965 config/tc-m32r.c:1077 config/tc-m32r.c:1261
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr ""
 
-#: config/tc-m32r.c:816 config/tc-m32r.c:910
+#: config/tc-m32r.c:974 config/tc-m32r.c:1086
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr ""
 
-#: config/tc-m32r.c:871 config/tc-m32r.c:935 config/tc-m32r.c:1107
+#: config/tc-m32r.c:1029 config/tc-m32r.c:1111 config/tc-m32r.c:1318
 msgid "internal error: lookup/get operands failed"
 msgstr ""
 
-#: config/tc-m32r.c:920
+#: config/tc-m32r.c:1096
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr ""
 
-#: config/tc-m32r.c:949
+#: config/tc-m32r.c:1125
 #, c-format
 msgid ""
 "%s: output of 1st instruction is the same as an input to 2nd instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:953
+#: config/tc-m32r.c:1129
 #, c-format
 msgid ""
 "%s: output of 2nd instruction is the same as an input to 1st instruction - "
 "is this intentional ?"
 msgstr ""
 
-#: config/tc-m32r.c:1267 config/tc-ppc.c:1732 config/tc-ppc.c:4263
+#: config/tc-m32r.c:1493 config/tc-ppc.c:1773 config/tc-ppc.c:4365
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1277
+#: config/tc-m32r.c:1503
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr ""
 
-#: config/tc-m32r.c:1291 config/tc-ppc.c:1754 config/tc-ppc.c:2899
-#: config/tc-ppc.c:4287
+#: config/tc-m32r.c:1517 config/tc-ppc.c:1795 config/tc-ppc.c:2952
+#: config/tc-ppc.c:4389
 msgid "ignoring bad alignment"
 msgstr ""
 
-#: config/tc-m32r.c:1303 config/tc-ppc.c:1791 config/tc-v850.c:335
+#: config/tc-m32r.c:1529 config/tc-ppc.c:1832 config/tc-v850.c:323
 msgid "Common alignment not a power of 2"
 msgstr ""
 
-#: config/tc-m32r.c:1318 config/tc-ppc.c:1765 config/tc-ppc.c:4299
+#: config/tc-m32r.c:1544 config/tc-ppc.c:1806 config/tc-ppc.c:4401
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr ""
 
-#: config/tc-m32r.c:1327
+#: config/tc-m32r.c:1553
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-m32r.c:1808
+#: config/tc-m32r.c:1789
+msgid "Addend to unresolved symbol not on word boundary."
+msgstr ""
+
+#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:749
+msgid "Invalid PIC expression."
+msgstr ""
+
+#: config/tc-m32r.c:2074
 msgid "Unmatched high/shigh reloc"
 msgstr ""
 
-#: config/tc-m68hc11.c:372
+#: config/tc-m32r.c:2334 config/tc-sparc.c:3524
+#, c-format
+msgid "internal error: can't export reloc type %d (`%s')"
+msgstr ""
+
+#: config/tc-m68hc11.c:369
 #, c-format
 msgid ""
 "Motorola 68HC11/68HC12/68HCS12 options:\n"
@@ -5204,55 +5752,56 @@ msgid ""
 "                          (used for testing)\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:418
+#: config/tc-m68hc11.c:415
 #, c-format
 msgid "Default target `%s' is not supported."
 msgstr ""
 
 #. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:437
+#: config/tc-m68hc11.c:433
+#, c-format
 msgid "Name   # Modes  Min ops  Max ops  Modes mask  # Used\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:505
+#: config/tc-m68hc11.c:499
 #, c-format
 msgid "Option `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:737
+#: config/tc-m68hc11.c:721
 msgid "#<imm8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:746
+#: config/tc-m68hc11.c:730
 msgid "#<imm16>"
 msgstr ""
 
-#: config/tc-m68hc11.c:755 config/tc-m68hc11.c:764
+#: config/tc-m68hc11.c:739 config/tc-m68hc11.c:748
 msgid "<imm8>,X"
 msgstr ""
 
-#: config/tc-m68hc11.c:791
+#: config/tc-m68hc11.c:775
 msgid "*<abs8>"
 msgstr ""
 
-#: config/tc-m68hc11.c:803
+#: config/tc-m68hc11.c:787
 msgid "#<mask>"
 msgstr ""
 
-#: config/tc-m68hc11.c:813
+#: config/tc-m68hc11.c:797
 #, c-format
 msgid "symbol%d"
 msgstr ""
 
-#: config/tc-m68hc11.c:815
+#: config/tc-m68hc11.c:799
 msgid "<abs>"
 msgstr ""
 
-#: config/tc-m68hc11.c:834
+#: config/tc-m68hc11.c:818
 msgid "<label>"
 msgstr ""
 
-#: config/tc-m68hc11.c:850
+#: config/tc-m68hc11.c:834
 #, c-format
 msgid ""
 "# Example of `%s' instructions\n"
@@ -5260,618 +5809,673 @@ msgid ""
 "_start:\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:898
+#: config/tc-m68hc11.c:881
 #, c-format
 msgid "Instruction `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:903
+#: config/tc-m68hc11.c:886
 #, c-format
 msgid "Instruction formats for `%s':"
 msgstr ""
 
-#: config/tc-m68hc11.c:1038
+#: config/tc-m68hc11.c:1016
 #, c-format
 msgid "Immediate operand is not allowed for operand %d."
 msgstr ""
 
-#: config/tc-m68hc11.c:1082
+#: config/tc-m68hc11.c:1060
 msgid "Indirect indexed addressing is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1102
+#: config/tc-m68hc11.c:1080
 msgid "Spurious `,' or bad indirect register addressing mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1124
+#: config/tc-m68hc11.c:1102
 msgid "Missing second register or offset for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1134
+#: config/tc-m68hc11.c:1112
 msgid "Missing second register for indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1150
+#: config/tc-m68hc11.c:1128
 msgid "Missing `]' to close indexed-indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1195
+#: config/tc-m68hc11.c:1173
 msgid "Illegal operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1200
+#: config/tc-m68hc11.c:1178
 msgid "Missing operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1253
+#: config/tc-m68hc11.c:1231
 msgid "Pre-increment mode is not valid for 68HC11"
 msgstr ""
 
-#: config/tc-m68hc11.c:1266
+#: config/tc-m68hc11.c:1244
 msgid "Wrong register in register indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1274
+#: config/tc-m68hc11.c:1252
 msgid "Missing `]' to close register indirect operand."
 msgstr ""
 
-#: config/tc-m68hc11.c:1294
+#: config/tc-m68hc11.c:1272
 msgid "Post-decrement mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1302
+#: config/tc-m68hc11.c:1280
 msgid "Post-increment mode is not valid for 68HC11."
 msgstr ""
 
-#: config/tc-m68hc11.c:1320
+#: config/tc-m68hc11.c:1298
 msgid "Invalid indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:1417
+#: config/tc-m68hc11.c:1390
 #, c-format
 msgid "Trap id `%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:1421
+#: config/tc-m68hc11.c:1394
 msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
 msgstr ""
 
-#: config/tc-m68hc11.c:1428
+#: config/tc-m68hc11.c:1401
 #, c-format
 msgid "Operand out of 8-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1435
+#: config/tc-m68hc11.c:1408
 msgid "The trap id must be a constant."
 msgstr ""
 
-#: config/tc-m68hc11.c:1470
+#: config/tc-m68hc11.c:1443
 #, c-format
 msgid "Operand `%x' not recognized in fixup8."
 msgstr ""
 
-#: config/tc-m68hc11.c:1490 config/tc-m68hc11.c:1542
+#: config/tc-m68hc11.c:1460 config/tc-m68hc11.c:1509
 #, c-format
 msgid "Operand out of 16-bit range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1522 config/tc-m68hc11.c:1558
+#: config/tc-m68hc11.c:1492 config/tc-m68hc11.c:1525
 #, c-format
 msgid "Operand `%x' not recognized in fixup16."
 msgstr ""
 
-#: config/tc-m68hc11.c:1576
+#: config/tc-m68hc11.c:1542
 #, c-format
 msgid "Unexpected branch conversion with `%x'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1671 config/tc-m68hc11.c:1812
+#: config/tc-m68hc11.c:1633 config/tc-m68hc11.c:1771
 #, c-format
 msgid "Operand out of range for a relative branch: `%ld'"
 msgstr ""
 
-#: config/tc-m68hc11.c:1780
+#: config/tc-m68hc11.c:1739
 msgid "Invalid register for dbcc/tbcc instruction."
 msgstr ""
 
-#: config/tc-m68hc11.c:1871
+#: config/tc-m68hc11.c:1827
 #, c-format
 msgid "Increment/decrement value is out of range: `%ld'."
 msgstr ""
 
-#: config/tc-m68hc11.c:1882
+#: config/tc-m68hc11.c:1838
 msgid "Expecting a register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1897
+#: config/tc-m68hc11.c:1853
 msgid "Invalid register for post/pre increment."
 msgstr ""
 
-#: config/tc-m68hc11.c:1927
+#: config/tc-m68hc11.c:1883
 msgid "Invalid register."
 msgstr ""
 
-#: config/tc-m68hc11.c:1934
+#: config/tc-m68hc11.c:1890
 #, c-format
 msgid "Offset out of 16-bit range: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:1939
+#: config/tc-m68hc11.c:1895
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld."
 msgstr ""
 
-#: config/tc-m68hc11.c:2020
+#: config/tc-m68hc11.c:2001
 msgid "Expecting register D for indexed indirect mode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2022
+#: config/tc-m68hc11.c:2003
 msgid "Indexed indirect mode is not allowed for movb/movw."
 msgstr ""
 
-#: config/tc-m68hc11.c:2039
+#: config/tc-m68hc11.c:2020
 msgid "Invalid accumulator register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2064
+#: config/tc-m68hc11.c:2045
 msgid "Invalid indexed register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2072
+#: config/tc-m68hc11.c:2053
 msgid "Addressing mode not implemented yet."
 msgstr ""
 
-#: config/tc-m68hc11.c:2087
+#: config/tc-m68hc11.c:2066
 msgid "Invalid source register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2089
+#: config/tc-m68hc11.c:2068
 msgid "Invalid source register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2094
+#: config/tc-m68hc11.c:2073
 msgid "Invalid destination register for this instruction, use 'tfr'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2096
+#: config/tc-m68hc11.c:2075
 msgid "Invalid destination register."
 msgstr ""
 
-#: config/tc-m68hc11.c:2194
+#: config/tc-m68hc11.c:2171
 msgid "Invalid indexed register, expecting register X."
 msgstr ""
 
-#: config/tc-m68hc11.c:2196
+#: config/tc-m68hc11.c:2173
 msgid "Invalid indexed register, expecting register Y."
 msgstr ""
 
-#: config/tc-m68hc11.c:2508
+#: config/tc-m68hc11.c:2479
 msgid "No instruction or missing opcode."
 msgstr ""
 
-#: config/tc-m68hc11.c:2573
+#: config/tc-m68hc11.c:2544
 #, c-format
 msgid "Opcode `%s' is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:2595
+#: config/tc-m68hc11.c:2566
 #, c-format
 msgid "Garbage at end of instruction: `%s'."
 msgstr ""
 
-#: config/tc-m68hc11.c:2618
+#: config/tc-m68hc11.c:2589
 #, c-format
 msgid "Invalid operand for `%s'"
 msgstr ""
 
-#: config/tc-m68hc11.c:2670
+#: config/tc-m68hc11.c:2640
 #, c-format
 msgid "Invalid mode: %s\n"
 msgstr ""
 
-#: config/tc-m68hc11.c:2732
+#: config/tc-m68hc11.c:2700
 msgid "bad .relax format"
 msgstr ""
 
-#: config/tc-m68hc11.c:2779
+#: config/tc-m68hc11.c:2744
 #, c-format
 msgid "Relocation %d is not supported by object file format."
 msgstr ""
 
-#: config/tc-m68hc11.c:3065
+#: config/tc-m68hc11.c:3023
 msgid "bra or bsr with undefined symbol."
 msgstr ""
 
-#: config/tc-m68hc11.c:3168 config/tc-m68hc11.c:3225
+#: config/tc-m68hc11.c:3126 config/tc-m68hc11.c:3183
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr ""
 
-#: config/tc-m68hc11.c:3289
+#: config/tc-m68hc11.c:3242
 msgid "Expression too complex."
 msgstr ""
 
-#: config/tc-m68hc11.c:3322
+#: config/tc-m68hc11.c:3275
 msgid "Value out of 16-bit range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3346
+#: config/tc-m68hc11.c:3293
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr ""
 
-#: config/tc-m68hc11.c:3353
+#: config/tc-m68hc11.c:3300
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr ""
 
-#: config/tc-m68hc11.c:3371
+#: config/tc-m68hc11.c:3313
+#, c-format
+msgid "Offset out of 5-bit range for movw/movb insn: %ld"
+msgstr ""
+
+#: config/tc-m68hc11.c:3329
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr ""
 
-#: config/tc-m68k.c:678
-msgid "Unknown PC relative instruction"
+#: config/tc-m68k.c:696
+msgid "no matching ColdFire architectures found"
+msgstr ""
+
+#: config/tc-m68k.c:710
+msgid " or "
+msgstr ""
+
+#: config/tc-m68k.c:715
+msgid ", or "
+msgstr ""
+
+#: config/tc-m68k.c:732
+msgid ", or aliases"
 msgstr ""
 
-#: config/tc-m68k.c:817
+#: config/tc-m68k.c:843
 #, c-format
 msgid "Can not do %d byte pc-relative relocation"
 msgstr ""
 
-#: config/tc-m68k.c:819
+#: config/tc-m68k.c:845
 #, c-format
 msgid "Can not do %d byte pc-relative pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:824
+#: config/tc-m68k.c:850
 #, c-format
 msgid "Can not do %d byte relocation"
 msgstr ""
 
-#: config/tc-m68k.c:826
+#: config/tc-m68k.c:852
 #, c-format
 msgid "Can not do %d byte pic relocation"
 msgstr ""
 
-#: config/tc-m68k.c:894
+#: config/tc-m68k.c:915
 #, c-format
 msgid "Unable to produce reloc against symbol '%s'"
 msgstr ""
 
-#: config/tc-m68k.c:938 config/tc-mips.c:13322 config/tc-vax.c:3441
+#: config/tc-m68k.c:959 config/tc-vax.c:3435
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr ""
 
-#: config/tc-m68k.c:1031 config/tc-tahoe.c:1495 config/tc-vax.c:1889
+#: config/tc-m68k.c:1050 config/tc-vax.c:1890
 msgid "No operator"
 msgstr ""
 
-#: config/tc-m68k.c:1061 config/tc-tahoe.c:1512 config/tc-vax.c:1906
+#: config/tc-m68k.c:1080 config/tc-vax.c:1907
 msgid "Unknown operator"
 msgstr ""
 
-#: config/tc-m68k.c:1836
+#: config/tc-m68k.c:1944
 msgid "invalid instruction for this architecture; needs "
 msgstr ""
 
-#: config/tc-m68k.c:1841
+#: config/tc-m68k.c:1950
+msgid "ColdFire ISA_A"
+msgstr ""
+
+#: config/tc-m68k.c:1958
+msgid "ColdFire hardware divide"
+msgstr ""
+
+#: config/tc-m68k.c:1966
+msgid "ColdFire ISA_A+"
+msgstr ""
+
+#: config/tc-m68k.c:1974
+msgid "ColdFire ISA_B"
+msgstr ""
+
+#: config/tc-m68k.c:1982
+msgid "ColdFire fpu"
+msgstr ""
+
+#: config/tc-m68k.c:1989
 msgid "fpu (68040, 68060 or 68881/68882)"
 msgstr ""
 
-#: config/tc-m68k.c:1844
+#: config/tc-m68k.c:1992
 msgid "mmu (68030 or 68851)"
 msgstr ""
 
-#: config/tc-m68k.c:1847
+#: config/tc-m68k.c:1995
 msgid "68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:1850
+#: config/tc-m68k.c:1998
 msgid "68000 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:1853
+#: config/tc-m68k.c:2001
 msgid "68010 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:1882
+#: config/tc-m68k.c:2029
 msgid "operands mismatch"
 msgstr ""
 
-#: config/tc-m68k.c:1939 config/tc-m68k.c:1945 config/tc-m68k.c:1951
-#: config/tc-mmix.c:2464 config/tc-mmix.c:2488
+#: config/tc-m68k.c:2090 config/tc-m68k.c:2096 config/tc-m68k.c:2102
+#: config/tc-mmix.c:2488 config/tc-mmix.c:2512
 msgid "operand out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2008
+#: config/tc-m68k.c:2159
 #, c-format
 msgid "Bignum too big for %c format; truncated"
 msgstr ""
 
-#: config/tc-m68k.c:2076
+#: config/tc-m68k.c:2236
 msgid "displacement too large for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2186
+#: config/tc-m68k.c:2347
 msgid ""
 "scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2191
+#: config/tc-m68k.c:2352
 msgid "invalid index size for coldfire"
 msgstr ""
 
-#: config/tc-m68k.c:2244
+#: config/tc-m68k.c:2405
 msgid "Forcing byte displacement"
 msgstr ""
 
-#: config/tc-m68k.c:2246
+#: config/tc-m68k.c:2407
 msgid "byte displacement out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2293 config/tc-m68k.c:2331
+#: config/tc-m68k.c:2455 config/tc-m68k.c:2493
 msgid "invalid operand mode for this architecture; needs 68020 or higher"
 msgstr ""
 
-#: config/tc-m68k.c:2317 config/tc-m68k.c:2351
+#: config/tc-m68k.c:2479 config/tc-m68k.c:2513
 msgid ":b not permitted; defaulting to :w"
 msgstr ""
 
-#: config/tc-m68k.c:2428
+#: config/tc-m68k.c:2590
 msgid "unsupported byte value; use a different suffix"
 msgstr ""
 
-#: config/tc-m68k.c:2442
+#: config/tc-m68k.c:2605
 msgid "unknown/incorrect operand"
 msgstr ""
 
-#: config/tc-m68k.c:2475 config/tc-m68k.c:2483 config/tc-m68k.c:2490
-#: config/tc-m68k.c:2497
+#: config/tc-m68k.c:2648 config/tc-m68k.c:2656 config/tc-m68k.c:2663
+#: config/tc-m68k.c:2670
 msgid "out of range"
 msgstr ""
 
-#: config/tc-m68k.c:2543
+#: config/tc-m68k.c:2716
 msgid "Can't use long branches on 68000/68010/5200"
 msgstr ""
 
-#: config/tc-m68k.c:2653
+#: config/tc-m68k.c:2833
 msgid "Expression out of range, using 0"
 msgstr ""
 
-#: config/tc-m68k.c:2765 config/tc-m68k.c:2781
+#: config/tc-m68k.c:3014 config/tc-m68k.c:3030
 msgid "Floating point register in register list"
 msgstr ""
 
-#: config/tc-m68k.c:2771
+#: config/tc-m68k.c:3020
 msgid "Wrong register in floating-point reglist"
 msgstr ""
 
-#: config/tc-m68k.c:2787
+#: config/tc-m68k.c:3036
 msgid "incorrect register in reglist"
 msgstr ""
 
-#: config/tc-m68k.c:2793
+#: config/tc-m68k.c:3042
 msgid "wrong register in floating-point reglist"
 msgstr ""
 
-#. ERROR
-#: config/tc-m68k.c:3234
+#. ERROR.
+#: config/tc-m68k.c:3505
 msgid "Extra )"
 msgstr ""
 
-#. ERROR
-#: config/tc-m68k.c:3245
+#. ERROR.
+#: config/tc-m68k.c:3516
 msgid "Missing )"
 msgstr ""
 
-#: config/tc-m68k.c:3262
+#: config/tc-m68k.c:3533
 msgid "Missing operand"
 msgstr ""
 
-#: config/tc-m68k.c:3594
+#: config/tc-m68k.c:3890
 #, c-format
 msgid "%s -- statement `%s' ignored"
 msgstr ""
 
-#: config/tc-m68k.c:3643
+#: config/tc-m68k.c:3939
 #, c-format
 msgid "Don't know how to figure width of %c in md_assemble()"
 msgstr ""
 
-#: config/tc-m68k.c:3825 config/tc-m68k.c:3863
+#: config/tc-m68k.c:4108
+#, c-format
+msgid "Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"
+msgstr ""
+
+#: config/tc-m68k.c:4159 config/tc-m68k.c:4198
 #, c-format
 msgid "Internal Error: Can't find %s in hash table"
 msgstr ""
 
-#: config/tc-m68k.c:3828 config/tc-m68k.c:3866
+#: config/tc-m68k.c:4162 config/tc-m68k.c:4201
 #, c-format
 msgid "Internal Error: Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-m68k.c:3948
+#: config/tc-m68k.c:4282
 msgid "architecture not yet selected: defaulting to 68020"
 msgstr ""
 
-#: config/tc-m68k.c:3997
+#: config/tc-m68k.c:4342
 #, c-format
 msgid "unrecognized default cpu `%s' ???"
 msgstr ""
 
-#: config/tc-m68k.c:4009
+#: config/tc-m68k.c:4353
 msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
 msgstr ""
 
-#: config/tc-m68k.c:4029
+#: config/tc-m68k.c:4370
 msgid "options for 68881 and no-68881 both given"
 msgstr ""
 
-#: config/tc-m68k.c:4031
+#: config/tc-m68k.c:4373
 msgid "options for 68851 and no-68851 both given"
 msgstr ""
 
-#: config/tc-m68k.c:4102
+#: config/tc-m68k.c:4434
 #, c-format
 msgid "text label `%s' aligned to odd boundary"
 msgstr ""
 
-#: config/tc-m68k.c:4321
+#: config/tc-m68k.c:4638
 msgid "invalid byte branch offset"
 msgstr ""
 
-#: config/tc-m68k.c:4358
+#: config/tc-m68k.c:4674
 msgid "short branch with zero offset: use :w"
 msgstr ""
 
-#: config/tc-m68k.c:4827 config/tc-m68k.c:4838
+#: config/tc-m68k.c:4698
+msgid "Tried to convert PC relative BSR to absolute JSR"
+msgstr ""
+
+#: config/tc-m68k.c:4708 config/tc-m68k.c:5054
+msgid "Tried to convert PC relative branch to absolute jump"
+msgstr ""
+
+#: config/tc-m68k.c:4724 config/tc-m68k.c:4783 config/tc-m68k.c:4847
+msgid "Tried to convert PC relative conditional branch to absolute jump"
+msgstr ""
+
+#: config/tc-m68k.c:4764
+msgid "Tried to convert DBcc to absolute jump"
+msgstr ""
+
+#: config/tc-m68k.c:5098 config/tc-m68k.c:5109 config/tc-m68k.c:5149
 msgid "expression out of range: defaulting to 1"
 msgstr ""
 
-#: config/tc-m68k.c:4870
+#: config/tc-m68k.c:5141
 msgid "expression out of range: defaulting to 0"
 msgstr ""
 
-#: config/tc-m68k.c:4903 config/tc-m68k.c:4915
+#: config/tc-m68k.c:5182 config/tc-m68k.c:5194
 #, c-format
 msgid "Can't deal with expression; defaulting to %ld"
 msgstr ""
 
-#: config/tc-m68k.c:4929
+#: config/tc-m68k.c:5208
 msgid "expression doesn't fit in BYTE"
 msgstr ""
 
-#: config/tc-m68k.c:4933
+#: config/tc-m68k.c:5212
 msgid "expression doesn't fit in WORD"
 msgstr ""
 
-#: config/tc-m68k.c:5026
+#: config/tc-m68k.c:5299
 #, c-format
 msgid "%s: unrecognized processor name"
 msgstr ""
 
-#: config/tc-m68k.c:5091
+#: config/tc-m68k.c:5363
 msgid "bad coprocessor id"
 msgstr ""
 
-#: config/tc-m68k.c:5097
+#: config/tc-m68k.c:5369
 msgid "unrecognized fopt option"
 msgstr ""
 
-#: config/tc-m68k.c:5231
+#: config/tc-m68k.c:5502
 #, c-format
 msgid "option `%s' may not be negated"
 msgstr ""
 
-#: config/tc-m68k.c:5242
+#: config/tc-m68k.c:5513
 #, c-format
 msgid "option `%s' not recognized"
 msgstr ""
 
-#: config/tc-m68k.c:5275
+#: config/tc-m68k.c:5542
 msgid "bad format of OPT NEST=depth"
 msgstr ""
 
-#: config/tc-m68k.c:5338
+#: config/tc-m68k.c:5598
 msgid "missing label"
 msgstr ""
 
-#: config/tc-m68k.c:5362 config/tc-m68k.c:5391
+#: config/tc-m68k.c:5622 config/tc-m68k.c:5651
 msgid "bad register list"
 msgstr ""
 
-#: config/tc-m68k.c:5364
+#: config/tc-m68k.c:5624
 #, c-format
 msgid "bad register list: %s"
 msgstr ""
 
-#: config/tc-m68k.c:5462
+#: config/tc-m68k.c:5722
 msgid "restore without save"
 msgstr ""
 
-#: config/tc-m68k.c:5636 config/tc-m68k.c:6023
+#: config/tc-m68k.c:5876 config/tc-m68k.c:6246
 msgid "syntax error in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5685
+#: config/tc-m68k.c:5921
 msgid "missing condition code in structured control directive"
 msgstr ""
 
-#: config/tc-m68k.c:5757
+#: config/tc-m68k.c:5992
 #, c-format
 msgid ""
 "Condition <%c%c> in structured control directive can not be encoded correctly"
 msgstr ""
 
-#: config/tc-m68k.c:6066
+#: config/tc-m68k.c:6288
 msgid "missing then"
 msgstr ""
 
-#: config/tc-m68k.c:6148
+#: config/tc-m68k.c:6369
 msgid "else without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6182
+#: config/tc-m68k.c:6402
 msgid "endi without matching if"
 msgstr ""
 
-#: config/tc-m68k.c:6223
+#: config/tc-m68k.c:6442
 msgid "break outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6262
+#: config/tc-m68k.c:6480
 msgid "next outside of structured loop"
 msgstr ""
 
-#: config/tc-m68k.c:6314
+#: config/tc-m68k.c:6531
 msgid "missing ="
 msgstr ""
 
-#: config/tc-m68k.c:6352
+#: config/tc-m68k.c:6569
 msgid "missing to or downto"
 msgstr ""
 
-#: config/tc-m68k.c:6388 config/tc-m68k.c:6422 config/tc-m68k.c:6641
+#: config/tc-m68k.c:6605 config/tc-m68k.c:6639 config/tc-m68k.c:6853
 msgid "missing do"
 msgstr ""
 
-#: config/tc-m68k.c:6525
+#: config/tc-m68k.c:6740
 msgid "endf without for"
 msgstr ""
 
-#: config/tc-m68k.c:6581
+#: config/tc-m68k.c:6794
 msgid "until without repeat"
 msgstr ""
 
-#: config/tc-m68k.c:6677
+#: config/tc-m68k.c:6888
 msgid "endw without while"
 msgstr ""
 
-#: config/tc-m68k.c:6801
-#, c-format
-msgid "unrecognized option `%s'"
-msgstr ""
-
-#: config/tc-m68k.c:6846
+#: config/tc-m68k.c:7050
 #, c-format
 msgid "unrecognized architecture specification `%s'"
 msgstr ""
 
-#: config/tc-m68k.c:6940
+#: config/tc-m68k.c:7143
 #, c-format
 msgid ""
 "680X0 options:\n"
 "-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
 "-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
 "-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m5307  | -m5407\n"
+"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
+"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
 "\t\t\tspecify variant of 680X0 architecture [default %s]\n"
 "-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
 "\t\t\ttarget has/lacks floating-point coprocessor\n"
 "\t\t\t[default yes for 68020, 68030, and cpu32]\n"
 msgstr ""
 
-#: config/tc-m68k.c:6951
+#: config/tc-m68k.c:7155
+#, c-format
 msgid ""
 "-m68851 | -mno-68851\n"
 "\t\t\ttarget has/lacks memory-management unit coprocessor\n"
@@ -5884,7 +6488,8 @@ msgid ""
 "--bitwise-or\t\tdo not treat `|' as a comment character\n"
 msgstr ""
 
-#: config/tc-m68k.c:6961
+#: config/tc-m68k.c:7165
+#, c-format
 msgid ""
 "--base-size-default-16\tbase reg without size is 16 bits\n"
 "--base-size-default-32\tbase reg without size is 32 bits (default)\n"
@@ -5892,222 +6497,175 @@ msgid ""
 "--disp-size-default-32\tdisplacement with unknown size is 32 bits (default)\n"
 msgstr ""
 
-#: config/tc-m68k.c:6996
+#: config/tc-m68k.c:7200
 #, c-format
 msgid "Error %s in %s\n"
 msgstr ""
 
-#: config/tc-m68k.c:7000
+#: config/tc-m68k.c:7204
 #, c-format
 msgid "Opcode(%d.%s): "
 msgstr ""
 
-#: config/tc-m88k.c:201
-#, c-format
-msgid "Can't hash instruction '%s':%s"
-msgstr ""
-
-#: config/tc-m88k.c:250
-#, c-format
-msgid "Invalid mnemonic '%s'"
-msgstr ""
-
-#: config/tc-m88k.c:268
-msgid "Parameter syntax error"
-msgstr ""
-
-#: config/tc-m88k.c:321
-msgid "Unknown relocation type"
-msgstr ""
-
-#. Having this here repeats the warning somtimes.
-#. But can't we stand that?
-#: config/tc-m88k.c:434
-msgid "Use of obsolete instruction"
-msgstr ""
-
-#: config/tc-m88k.c:551
-msgid "Expression truncated to 16 bits"
-msgstr ""
-
-#: config/tc-m88k.c:617 config/tc-m88k.c:639
-msgid "Expression truncated to 5 bits"
-msgstr ""
-
-#: config/tc-m88k.c:856
-msgid "Expression truncated to 9 bits"
-msgstr ""
-
-#: config/tc-m88k.c:878
-msgid "Removed lower 2 bits of expression"
-msgstr ""
-
-#: config/tc-m88k.c:1057
-msgid "Relaxation should never occur"
-msgstr ""
-
-#: config/tc-m88k.h:78
-msgid "m88k convert_frag\n"
-msgstr ""
-
-#: config/tc-mcore.c:460
+#: config/tc-mcore.c:524
 #, c-format
 msgid "register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:544
+#: config/tc-mcore.c:606
 #, c-format
 msgid "control register expected, but saw '%.6s'"
 msgstr ""
 
-#: config/tc-mcore.c:582
+#: config/tc-mcore.c:642
 msgid "bad/missing psr specifier"
 msgstr ""
 
-#: config/tc-mcore.c:743
+#: config/tc-mcore.c:692
 msgid "more than 65K literal pools"
 msgstr ""
 
-#: config/tc-mcore.c:797
+#: config/tc-mcore.c:746
 msgid "missing ']'"
 msgstr ""
 
-#: config/tc-mcore.c:837
+#: config/tc-mcore.c:785
 msgid "operand must be a constant"
 msgstr ""
 
-#: config/tc-mcore.c:839
+#: config/tc-mcore.c:787
 #, c-format
 msgid "operand must be absolute in range %u..%u, not %ld"
 msgstr ""
 
-#: config/tc-mcore.c:875
+#: config/tc-mcore.c:822
 msgid "operand must be a multiple of 4"
 msgstr ""
 
-#: config/tc-mcore.c:882
+#: config/tc-mcore.c:829
 msgid "operand must be a multiple of 2"
 msgstr ""
 
-#: config/tc-mcore.c:896 config/tc-mcore.c:1410 config/tc-mcore.c:1464
+#: config/tc-mcore.c:843 config/tc-mcore.c:1359 config/tc-mcore.c:1413
 msgid "base register expected"
 msgstr ""
 
-#: config/tc-mcore.c:945
+#: config/tc-mcore.c:891
 #, c-format
 msgid "unknown opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:988
+#: config/tc-mcore.c:934
 msgid "invalid register: r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:1036 config/tc-mcore.c:1614
+#: config/tc-mcore.c:983 config/tc-mcore.c:1564
 msgid "M340 specific opcode used when assembling for M210"
 msgstr ""
 
-#: config/tc-mcore.c:1054 config/tc-mcore.c:1093 config/tc-mcore.c:1112
-#: config/tc-mcore.c:1131 config/tc-mcore.c:1158 config/tc-mcore.c:1187
-#: config/tc-mcore.c:1224 config/tc-mcore.c:1259 config/tc-mcore.c:1278
-#: config/tc-mcore.c:1297 config/tc-mcore.c:1331 config/tc-mcore.c:1356
-#: config/tc-mcore.c:1413 config/tc-mcore.c:1467 config/tc-mcore.c:1503
-#: config/tc-mcore.c:1561 config/tc-mcore.c:1583 config/tc-mcore.c:1606
+#: config/tc-mcore.c:1001 config/tc-mcore.c:1041 config/tc-mcore.c:1060
+#: config/tc-mcore.c:1079 config/tc-mcore.c:1107 config/tc-mcore.c:1136
+#: config/tc-mcore.c:1173 config/tc-mcore.c:1208 config/tc-mcore.c:1227
+#: config/tc-mcore.c:1246 config/tc-mcore.c:1280 config/tc-mcore.c:1305
+#: config/tc-mcore.c:1362 config/tc-mcore.c:1416 config/tc-mcore.c:1452
+#: config/tc-mcore.c:1511 config/tc-mcore.c:1533 config/tc-mcore.c:1556
 msgid "second operand missing"
 msgstr ""
 
-#: config/tc-mcore.c:1069
+#: config/tc-mcore.c:1017
 msgid "destination register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1090
+#: config/tc-mcore.c:1038
 msgid "source register must be r1"
 msgstr ""
 
-#: config/tc-mcore.c:1153 config/tc-mcore.c:1210
+#: config/tc-mcore.c:1102 config/tc-mcore.c:1159
 msgid "immediate is not a power of two"
 msgstr ""
 
-#: config/tc-mcore.c:1181
+#: config/tc-mcore.c:1130
 msgid "translating bgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1218
+#: config/tc-mcore.c:1167
 msgid "translating mgeni to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1250
+#: config/tc-mcore.c:1199
 msgid "translating bmaski to movi"
 msgstr ""
 
-#: config/tc-mcore.c:1326
+#: config/tc-mcore.c:1275
 #, c-format
 msgid "displacement too large (%d)"
 msgstr ""
 
-#: config/tc-mcore.c:1340
+#: config/tc-mcore.c:1289
 msgid "Invalid register: r0 and r15 illegal"
 msgstr ""
 
-#: config/tc-mcore.c:1371
+#: config/tc-mcore.c:1320
 msgid "bad starting register: r0 and r15 invalid"
 msgstr ""
 
-#: config/tc-mcore.c:1384
+#: config/tc-mcore.c:1333
 msgid "ending register must be r15"
 msgstr ""
 
-#: config/tc-mcore.c:1404
+#: config/tc-mcore.c:1353
 msgid "bad base register: must be r0"
 msgstr ""
 
-#: config/tc-mcore.c:1422
+#: config/tc-mcore.c:1371
 msgid "first register must be r4"
 msgstr ""
 
-#: config/tc-mcore.c:1433
+#: config/tc-mcore.c:1382
 msgid "last register must be r7"
 msgstr ""
 
-#: config/tc-mcore.c:1470
+#: config/tc-mcore.c:1419
 msgid "reg-reg expected"
 msgstr ""
 
-#: config/tc-mcore.c:1580
+#: config/tc-mcore.c:1530
 msgid "second operand must be 1"
 msgstr ""
 
-#: config/tc-mcore.c:1601
+#: config/tc-mcore.c:1551
 msgid "zero used as immediate value"
 msgstr ""
 
-#: config/tc-mcore.c:1628
+#: config/tc-mcore.c:1578
 msgid "duplicated psr bit specifier"
 msgstr ""
 
-#: config/tc-mcore.c:1634
+#: config/tc-mcore.c:1584
 msgid "`af' must appear alone"
 msgstr ""
 
-#: config/tc-mcore.c:1641
+#: config/tc-mcore.c:1591
 #, c-format
 msgid "unimplemented opcode \"%s\""
 msgstr ""
 
-#: config/tc-mcore.c:1650
+#: config/tc-mcore.c:1600
 #, c-format
 msgid "ignoring operands: %s "
 msgstr ""
 
-#: config/tc-mcore.c:1718 config/tc-w65.c:772
+#: config/tc-mcore.c:1665
 msgid "Bad call to MD_NTOF()"
 msgstr ""
 
-#: config/tc-mcore.c:1788
+#: config/tc-mcore.c:1736
 #, c-format
 msgid "unrecognised cpu type '%s'"
 msgstr ""
 
-#: config/tc-mcore.c:1807
+#: config/tc-mcore.c:1754
+#, c-format
 msgid ""
 "MCORE specific options:\n"
 "  -{no-}jsri2bsr\t  {dis}able jsri to bsr transformation (def: dis)\n"
@@ -6117,680 +6675,674 @@ msgid ""
 "  -EL                     assemble for a little endian system\n"
 msgstr ""
 
-#: config/tc-mcore.c:1826
+#: config/tc-mcore.c:1772
 msgid "failed sanity check: short_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1837
+#: config/tc-mcore.c:1782
 msgid "failed sanity check: long_jump"
 msgstr ""
 
-#: config/tc-mcore.c:1863
+#: config/tc-mcore.c:1808
 #, c-format
 msgid "odd displacement at %x"
 msgstr ""
 
-#: config/tc-mcore.c:2047
+#: config/tc-mcore.c:1990
 msgid "unknown"
 msgstr ""
 
-#: config/tc-mcore.c:2073
+#: config/tc-mcore.c:2017
 #, c-format
 msgid "odd distance branch (0x%lx bytes)"
 msgstr ""
 
-#: config/tc-mcore.c:2077
+#: config/tc-mcore.c:2021
 #, c-format
 msgid "pcrel for branch to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2096
+#: config/tc-mcore.c:2041
 #, c-format
 msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2107
+#: config/tc-mcore.c:2053
 #, c-format
 msgid "pcrel for loopt too far (0x%lx)"
 msgstr ""
 
-#: config/tc-mcore.c:2336
+#: config/tc-mcore.c:2263
 #, c-format
 msgid "Can not do %d byte %srelocation"
 msgstr ""
 
-#: config/tc-mcore.c:2338
+#: config/tc-mcore.c:2265
 msgid "pc-relative"
 msgstr ""
 
 #. Prototypes for static functions.
-#: config/tc-mips.c:818
+#: config/tc-mips.c:957
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr ""
 
-#: config/tc-mips.c:1131
+#: config/tc-mips.c:1443
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr ""
 
-#: config/tc-mips.c:1139
+#: config/tc-mips.c:1451
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr ""
 
-#: config/tc-mips.c:1332
+#: config/tc-mips.c:1652
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr ""
 
-#: config/tc-mips.c:1976 config/tc-mips.c:13666
+#: config/tc-mips.c:2327 config/tc-mips.c:13480
 msgid "extended instruction in delay slot"
 msgstr ""
 
-#: config/tc-mips.c:2022 config/tc-mips.c:2032
+#: config/tc-mips.c:2391 config/tc-mips.c:2401
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2025 config/tc-mips.c:2035
+#: config/tc-mips.c:2394 config/tc-mips.c:2404
 #, c-format
 msgid "jump address range overflow (0x%lx)"
 msgstr ""
 
-#: config/tc-mips.c:2805 config/tc-mips.c:3194
-msgid "Macro instruction expanded into multiple instructions"
-msgstr ""
-
-#: config/tc-mips.c:2817
+#: config/tc-mips.c:2893
 msgid ""
 "Macro instruction expanded into multiple instructions in a branch delay slot"
 msgstr ""
 
-#: config/tc-mips.c:3225 config/tc-mips.c:7549 config/tc-mips.c:7575
-#: config/tc-mips.c:7653 config/tc-mips.c:7678
+#: config/tc-mips.c:2896
+msgid "Macro instruction expanded into multiple instructions"
+msgstr ""
+
+#: config/tc-mips.c:3414 config/tc-mips.c:7338 config/tc-mips.c:7362
+#: config/tc-mips.c:7435 config/tc-mips.c:7458
 msgid "operand overflow"
 msgstr ""
 
-#: config/tc-mips.c:3251 config/tc-mips.c:6902 config/tc-mips.c:7754
+#: config/tc-mips.c:3433 config/tc-mips.c:4033 config/tc-mips.c:6734
+#: config/tc-mips.c:7525
 msgid "Macro used $at after \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:3281
+#: config/tc-mips.c:3462
 msgid "unsupported large constant"
 msgstr ""
 
-#: config/tc-mips.c:3283
+#: config/tc-mips.c:3464
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr ""
 
-#: config/tc-mips.c:3422
+#: config/tc-mips.c:3597 config/tc-mips.c:5844 config/tc-mips.c:6438
 #, c-format
-msgid "Number (0x%lx) larger than 32 bits"
+msgid "Number (0x%s) larger than 32 bits"
 msgstr ""
 
-#: config/tc-mips.c:3444
+#: config/tc-mips.c:3617
 msgid "Number larger than 64 bits"
 msgstr ""
 
-#: config/tc-mips.c:3747 config/tc-mips.c:3787 config/tc-mips.c:3829
-#: config/tc-mips.c:3886 config/tc-mips.c:6069 config/tc-mips.c:6111
-#: config/tc-mips.c:6163 config/tc-mips.c:6661 config/tc-mips.c:6716
+#: config/tc-mips.c:3911 config/tc-mips.c:3939 config/tc-mips.c:3977
+#: config/tc-mips.c:4022 config/tc-mips.c:6053 config/tc-mips.c:6092
+#: config/tc-mips.c:6131 config/tc-mips.c:6553 config/tc-mips.c:6605
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:4146
+#: config/tc-mips.c:4328 config/tc-mips.c:4394 config/tc-mips.c:4482
+#: config/tc-mips.c:4529 config/tc-mips.c:4590 config/tc-mips.c:4638
+#: config/tc-mips.c:7619 config/tc-mips.c:7626 config/tc-mips.c:7633
+#: config/tc-mips.c:7740
+msgid "Unsupported large constant"
+msgstr ""
+
+#. result is always true
+#: config/tc-mips.c:4360
 #, c-format
-msgid "Branch %s is always false (nop)"
+msgid "Branch %s is always true"
 msgstr ""
 
-#: config/tc-mips.c:4153
+#: config/tc-mips.c:4601 config/tc-mips.c:4649 config/tc-mips.c:8309
 #, c-format
-msgid "Branch likely %s is always false"
+msgid "Improper position (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:4160 config/tc-mips.c:4228 config/tc-mips.c:4320
-#: config/tc-mips.c:4369 config/tc-mips.c:7857 config/tc-mips.c:7865
-#: config/tc-mips.c:7872 config/tc-mips.c:7979
-msgid "Unsupported large constant"
+#: config/tc-mips.c:4607 config/tc-mips.c:8376
+#, c-format
+msgid "Improper extract size (%lu, position %lu)"
 msgstr ""
 
-#. result is always true
-#: config/tc-mips.c:4194
+#: config/tc-mips.c:4655 config/tc-mips.c:8340
 #, c-format
-msgid "Branch %s is always true"
+msgid "Improper insert size (%lu, position %lu)"
 msgstr ""
 
-#: config/tc-mips.c:4437 config/tc-mips.c:4540
+#: config/tc-mips.c:4692 config/tc-mips.c:4789
 msgid "Divide by zero."
 msgstr ""
 
-#: config/tc-mips.c:4622
+#: config/tc-mips.c:4875
 msgid "dla used to load 32-bit register"
 msgstr ""
 
-#: config/tc-mips.c:4625
+#: config/tc-mips.c:4878
 msgid "la used to load 64-bit address"
 msgstr ""
 
-#: config/tc-mips.c:5000 config/tc-mips.c:5353
+#: config/tc-mips.c:4990
+msgid "offset too large"
+msgstr ""
+
+#: config/tc-mips.c:5162 config/tc-mips.c:5441
 msgid "PIC code offset overflow (max 32 signed bits)"
 msgstr ""
 
-#: config/tc-mips.c:5419
+#: config/tc-mips.c:5487
 msgid "MIPS PIC call to register other than $25"
 msgstr ""
 
-#: config/tc-mips.c:5425 config/tc-mips.c:5436 config/tc-mips.c:5574
-#: config/tc-mips.c:5585
+#: config/tc-mips.c:5493 config/tc-mips.c:5504 config/tc-mips.c:5628
+#: config/tc-mips.c:5639
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5430 config/tc-mips.c:5579
+#: config/tc-mips.c:5498 config/tc-mips.c:5633
 msgid "No .frame pseudo-op used in PIC code"
 msgstr ""
 
-#: config/tc-mips.c:5657 config/tc-mips.c:5746 config/tc-mips.c:6414
-#: config/tc-mips.c:6453 config/tc-mips.c:6471 config/tc-mips.c:7221
+#: config/tc-mips.c:5704 config/tc-mips.c:5792 config/tc-mips.c:6338
+#: config/tc-mips.c:6369 config/tc-mips.c:6387 config/tc-mips.c:7037
 msgid "opcode not supported on this processor"
 msgstr ""
 
-#: config/tc-mips.c:5970
-msgid "load/store address overflow (max 32 bits)"
-msgstr ""
-
-#: config/tc-mips.c:7084 config/tc-mips.c:7117 config/tc-mips.c:7167
-#: config/tc-mips.c:7199
+#: config/tc-mips.c:6903 config/tc-mips.c:6934 config/tc-mips.c:6985
+#: config/tc-mips.c:7015
 msgid "Improper rotate count"
 msgstr ""
 
-#: config/tc-mips.c:7260
+#: config/tc-mips.c:7070
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr ""
 
-#: config/tc-mips.c:7418
+#: config/tc-mips.c:7216
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr ""
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:7750
+#: config/tc-mips.c:7521
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr ""
 
-#: config/tc-mips.c:8010
+#: config/tc-mips.c:7771
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8030 config/tc-mips.c:8361
+#: config/tc-mips.c:7799 config/tc-mips.c:8430
 #, c-format
 msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8091
+#: config/tc-mips.c:7876
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8098
+#: config/tc-mips.c:7883
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr ""
 
-#: config/tc-mips.c:8212
+#: config/tc-mips.c:8000
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr ""
 
-#: config/tc-mips.c:8293
+#: config/tc-mips.c:8031 config/tc-mips.c:8045 config/tc-mips.c:8059
+#: config/tc-mips.c:8073 config/tc-mips.c:8100 config/tc-mips.c:8147
 #, c-format
-msgid "Improper position (%lu)"
+msgid "DSP immediate not in range 0..%d (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8319
+#: config/tc-mips.c:8092 config/tc-mips.c:8120
+msgid "Invalid dsp acc register"
+msgstr ""
+
+#: config/tc-mips.c:8131 config/tc-mips.c:8165 config/tc-mips.c:8184
 #, c-format
-msgid "Improper insert size (%lu, position %lu)"
+msgid "DSP immediate not in range %ld..%ld (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8345
+#: config/tc-mips.c:8200 config/tc-mips.c:8214
 #, c-format
-msgid "Improper extract size (%lu, position %lu)"
+msgid "MT immediate not in range 0..%d (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8379
+#: config/tc-mips.c:8233 config/tc-mips.c:8246
+msgid "Invalid dsp/smartmips acc register"
+msgstr ""
+
+#: config/tc-mips.c:8395 config/tc-mips.c:8899
+msgid "absolute expression required"
+msgstr ""
+
+#: config/tc-mips.c:8418 config/tc-mips.c:8579
+#, c-format
+msgid "Invalid register number (%d)"
+msgstr ""
+
+#: config/tc-mips.c:8426
+msgid "Invalid coprocessor 0 register number"
+msgstr ""
+
+#: config/tc-mips.c:8447
 #, c-format
 msgid "Improper shift amount (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8405 config/tc-mips.c:9655 config/tc-mips.c:9770
+#: config/tc-mips.c:8470 config/tc-mips.c:9731 config/tc-mips.c:9844
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8423
+#: config/tc-mips.c:8485
 #, c-format
 msgid "Illegal break code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8437
+#: config/tc-mips.c:8496
 #, c-format
 msgid "Illegal lower break code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8450
+#: config/tc-mips.c:8507
 #, c-format
 msgid "Illegal 20-bit code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8462
+#: config/tc-mips.c:8519
 #, c-format
 msgid "Coproccesor code > 25 bits (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8475
+#: config/tc-mips.c:8532
 #, c-format
 msgid "Illegal 19-bit code (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8487
+#: config/tc-mips.c:8543
 #, c-format
 msgid "Invalid performance register (%lu)"
 msgstr ""
 
-#: config/tc-mips.c:8525
-#, c-format
-msgid "Invalid register number (%d)"
-msgstr ""
-
-#: config/tc-mips.c:8703
+#: config/tc-mips.c:8754
 #, c-format
 msgid "Invalid MDMX Immediate (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:8746
+#: config/tc-mips.c:8794
 #, c-format
 msgid "Invalid float register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:8756
+#: config/tc-mips.c:8810
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr ""
 
-#: config/tc-mips.c:8795
+#: config/tc-mips.c:8849
 #, c-format
 msgid "Bad element selector %ld"
 msgstr ""
 
-#: config/tc-mips.c:8802
+#: config/tc-mips.c:8857
 #, c-format
 msgid "Expecting ']' found '%s'"
 msgstr ""
 
-#: config/tc-mips.c:8844
-msgid "absolute expression required"
-msgstr ""
-
-#: config/tc-mips.c:8912
+#: config/tc-mips.c:8963
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr ""
 
-#: config/tc-mips.c:9040
+#: config/tc-mips.c:9084
 msgid "Can't use floating point insn in this section"
 msgstr ""
 
-#: config/tc-mips.c:9101
+#: config/tc-mips.c:9145
 msgid "expression out of range"
 msgstr ""
 
-#: config/tc-mips.c:9141
+#: config/tc-mips.c:9185
 msgid "lui expression not in range 0..65535"
 msgstr ""
 
-#: config/tc-mips.c:9165
+#: config/tc-mips.c:9209
+#, c-format
+msgid "Invalid condition code register $fcc%d"
+msgstr ""
+
+#: config/tc-mips.c:9214
+#, c-format
+msgid "Condition code register should be even for %s, was %d"
+msgstr ""
+
+#: config/tc-mips.c:9219
 #, c-format
-msgid "invalid condition code register $fcc%d"
+msgid "Condition code register should be 0 or 4 for %s, was %d"
 msgstr ""
 
-#: config/tc-mips.c:9190
+#: config/tc-mips.c:9245
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr ""
 
-#: config/tc-mips.c:9202 config/tc-mips.c:9219
+#: config/tc-mips.c:9257 config/tc-mips.c:9274
 #, c-format
 msgid "bad byte vector index (%ld)"
 msgstr ""
 
-#: config/tc-mips.c:9230
+#: config/tc-mips.c:9285
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr ""
 
-#: config/tc-mips.c:9241 config/tc-mips.c:9246 config/tc-mips.c:9795
+#: config/tc-mips.c:9296 config/tc-mips.c:9301 config/tc-mips.c:9869
 msgid "illegal operands"
 msgstr ""
 
-#: config/tc-mips.c:9311
+#: config/tc-mips.c:9367
 msgid "unrecognized opcode"
 msgstr ""
 
-#: config/tc-mips.c:9423
+#: config/tc-mips.c:9504
 #, c-format
 msgid "invalid register number (%d)"
 msgstr ""
 
-#: config/tc-mips.c:9514
+#: config/tc-mips.c:9595
 msgid "used $at without \".set noat\""
 msgstr ""
 
-#: config/tc-mips.c:9689
+#: config/tc-mips.c:9763
 msgid "can't parse register list"
 msgstr ""
 
-#: config/tc-mips.c:9913
+#: config/tc-mips.c:9987
 msgid "extended operand requested but not required"
 msgstr ""
 
-#: config/tc-mips.c:9915
+#: config/tc-mips.c:9989
 msgid "invalid unextended operand value"
 msgstr ""
 
-#: config/tc-mips.c:9943
+#: config/tc-mips.c:10017
 msgid "operand value out of range for instruction"
 msgstr ""
 
-#: config/tc-mips.c:10341
+#: config/tc-mips.c:10469
 #, c-format
 msgid "A different %s was already specified, is now %s"
 msgstr ""
 
-#: config/tc-mips.c:10502
-msgid "-G may not be used with embedded PIC code"
-msgstr ""
-
-#: config/tc-mips.c:10531
+#: config/tc-mips.c:10689
 msgid "-call_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10538 config/tc-mips.c:11849 config/tc-mips.c:12087
+#: config/tc-mips.c:10696 config/tc-mips.c:10725 config/tc-mips.c:11834
+#: config/tc-mips.c:12060
 msgid "-G may not be used with SVR4 PIC code"
 msgstr ""
 
-#: config/tc-mips.c:10547
+#: config/tc-mips.c:10705
 msgid "-non_shared is supported only for ELF format"
 msgstr ""
 
-#: config/tc-mips.c:10565
-msgid "-G is not supported for this configuration"
-msgstr ""
-
-#: config/tc-mips.c:10570
-msgid "-G may not be used with SVR4 or embedded PIC code"
-msgstr ""
-
-#: config/tc-mips.c:10584
+#: config/tc-mips.c:10736
 msgid "-32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10593
+#: config/tc-mips.c:10745
 msgid "-n32 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10602
+#: config/tc-mips.c:10754
 msgid "-64 is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10607 config/tc-mips.c:10644
+#: config/tc-mips.c:10759 config/tc-mips.c:10796
 msgid "No compiled in support for 64 bit object file format"
 msgstr ""
 
-#: config/tc-mips.c:10631
+#: config/tc-mips.c:10783
 msgid "-mabi is supported for ELF format only"
 msgstr ""
 
-#: config/tc-mips.c:10651
+#: config/tc-mips.c:10803
 #, c-format
 msgid "invalid abi -mabi=%s"
 msgstr ""
 
-#: config/tc-mips.c:10718
+#: config/tc-mips.c:10877
 msgid "-G not supported in this configuration."
 msgstr ""
 
-#: config/tc-mips.c:10744
+#: config/tc-mips.c:10903
 #, c-format
 msgid "-%s conflicts with the other architecture options, which imply -%s"
 msgstr ""
 
-#: config/tc-mips.c:10775
+#: config/tc-mips.c:10934
 msgid "-mgp64 used with a 32-bit processor"
 msgstr ""
 
-#: config/tc-mips.c:10777
+#: config/tc-mips.c:10936
 msgid "-mgp32 used with a 64-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10779
+#: config/tc-mips.c:10938
 msgid "-mgp64 used with a 32-bit ABI"
 msgstr ""
 
-#: config/tc-mips.c:10809
+#: config/tc-mips.c:10968
 msgid "trap exception not supported at ISA 1"
 msgstr ""
 
-#: config/tc-mips.c:10957
-#, c-format
-msgid "Unmatched %%hi reloc"
-msgstr ""
-
-#: config/tc-mips.c:11049
+#: config/tc-mips.c:11229
 msgid "Cannot branch to undefined symbol."
 msgstr ""
 
-#: config/tc-mips.c:11056
+#: config/tc-mips.c:11236
 msgid "Cannot branch to symbol in another section."
 msgstr ""
 
-#: config/tc-mips.c:11065
+#: config/tc-mips.c:11245
 msgid "Pretending global symbol used as branch target is local."
 msgstr ""
 
-#: config/tc-mips.c:11230
-msgid "Invalid PC relative reloc"
-msgstr ""
-
-#: config/tc-mips.c:11325 config/tc-sparc.c:3185 config/tc-sparc.c:3192
-#: config/tc-sparc.c:3199 config/tc-sparc.c:3206 config/tc-sparc.c:3213
-#: config/tc-sparc.c:3222 config/tc-sparc.c:3233 config/tc-sparc.c:3255
-#: config/tc-sparc.c:3279 write.c:998 write.c:1070
+#: config/tc-mips.c:11402 config/tc-sparc.c:3229 config/tc-sparc.c:3236
+#: config/tc-sparc.c:3243 config/tc-sparc.c:3250 config/tc-sparc.c:3257
+#: config/tc-sparc.c:3266 config/tc-sparc.c:3277 config/tc-sparc.c:3299
+#: config/tc-sparc.c:3323 write.c:861 write.c:933
 msgid "relocation overflow"
 msgstr ""
 
-#: config/tc-mips.c:11335
+#: config/tc-mips.c:11412
 #, c-format
 msgid "Branch to odd address (%lx)"
 msgstr ""
 
-#: config/tc-mips.c:11384
+#: config/tc-mips.c:11461
 msgid "Branch out of range"
 msgstr ""
 
-#: config/tc-mips.c:11491
-#, c-format
-msgid "%08lx  UNDEFINED\n"
-msgstr ""
-
-#: config/tc-mips.c:11550
+#: config/tc-mips.c:11540
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr ""
 
-#: config/tc-mips.c:11553
+#: config/tc-mips.c:11543
 msgid "Alignment negative: 0 assumed."
 msgstr ""
 
-#: config/tc-mips.c:11640
-msgid "No read only data section in this object file format"
-msgstr ""
-
-#: config/tc-mips.c:11663
-msgid "Global pointers not supported; recompile -G 0"
-msgstr ""
-
-#: config/tc-mips.c:11805
+#: config/tc-mips.c:11780
 #, c-format
 msgid "%s: no such section"
 msgstr ""
 
-#: config/tc-mips.c:11844
+#: config/tc-mips.c:11829
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ""
 
-#: config/tc-mips.c:11855
+#: config/tc-mips.c:11840
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr ""
 
-#: config/tc-mips.c:11917
+#: config/tc-mips.c:11893
 msgid "`noreorder' must be set before `nomacro'"
 msgstr ""
 
-#: config/tc-mips.c:11989
+#: config/tc-mips.c:11952
 #, c-format
 msgid "unknown architecture %s"
 msgstr ""
 
-#: config/tc-mips.c:11997 config/tc-mips.c:12018
+#: config/tc-mips.c:11965 config/tc-mips.c:11995
 #, c-format
 msgid "unknown ISA level %s"
 msgstr ""
 
-#: config/tc-mips.c:12046
+#: config/tc-mips.c:11973
+#, c-format
+msgid "unknown ISA or architecture %s"
+msgstr ""
+
+#: config/tc-mips.c:12023
 msgid ".set pop with no .set push"
 msgstr ""
 
-#: config/tc-mips.c:12070
+#: config/tc-mips.c:12044
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr ""
 
-#: config/tc-mips.c:12120
+#: config/tc-mips.c:12102
 msgid ".cpload not in noreorder section"
 msgstr ""
 
-#: config/tc-mips.c:12176 config/tc-mips.c:12195
+#: config/tc-mips.c:12171 config/tc-mips.c:12190
 msgid "missing argument separator ',' for .cpsetup"
 msgstr ""
 
-#: config/tc-mips.c:12373
+#: config/tc-mips.c:12380
 msgid "Unsupported use of .gpword"
 msgstr ""
 
-#: config/tc-mips.c:12409
+#: config/tc-mips.c:12416
 msgid "Unsupported use of .gpdword"
 msgstr ""
 
-#: config/tc-mips.c:12544
+#: config/tc-mips.c:12548
 msgid "expected `$'"
 msgstr ""
 
-#: config/tc-mips.c:12552
+#: config/tc-mips.c:12556
 msgid "Bad register number"
 msgstr ""
 
-#: config/tc-mips.c:12600
+#: config/tc-mips.c:12604
 msgid "Unrecognized register name"
 msgstr ""
 
-#: config/tc-mips.c:12835
+#: config/tc-mips.c:12837
 msgid "unsupported PC relative reference to different section"
 msgstr ""
 
-#: config/tc-mips.c:12948
+#: config/tc-mips.c:12950 config/tc-xtensa.c:1593 config/tc-xtensa.c:1804
 msgid "unsupported relocation"
 msgstr ""
 
-#: config/tc-mips.c:13063
-msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
-msgstr ""
-
-#: config/tc-mips.c:13126
-msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
-msgstr ""
-
-#: config/tc-mips.c:13341 config/tc-sh.c:3800
+#: config/tc-mips.c:13158
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr ""
 
-#: config/tc-mips.c:13430
+#: config/tc-mips.c:13244
 msgid "relaxed out-of-range branch into a jump"
 msgstr ""
 
-#: config/tc-mips.c:13903
+#: config/tc-mips.c:13766
 msgid "missing .end at end of assembly"
 msgstr ""
 
-#: config/tc-mips.c:13918
+#: config/tc-mips.c:13781
 msgid "expected simple number"
 msgstr ""
 
-#: config/tc-mips.c:13944
+#: config/tc-mips.c:13807
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr ""
 
-#: config/tc-mips.c:13946
+#: config/tc-mips.c:13809
 msgid "invalid number"
 msgstr ""
 
-#: config/tc-mips.c:14019
+#: config/tc-mips.c:13882
 msgid ".end not in text section"
 msgstr ""
 
-#: config/tc-mips.c:14023
+#: config/tc-mips.c:13886
 msgid ".end directive without a preceding .ent directive."
 msgstr ""
 
-#: config/tc-mips.c:14032
+#: config/tc-mips.c:13895
 msgid ".end symbol does not match .ent symbol."
 msgstr ""
 
-#: config/tc-mips.c:14039
+#: config/tc-mips.c:13902
 msgid ".end directive missing or unknown symbol"
 msgstr ""
 
-#: config/tc-mips.c:14099
+#: config/tc-mips.c:13978
 msgid ".ent or .aent not in text section."
 msgstr ""
 
-#: config/tc-mips.c:14102
+#: config/tc-mips.c:13981
 msgid "missing .end"
 msgstr ""
 
-#: config/tc-mips.c:14154
+#: config/tc-mips.c:14033
 msgid "Bad .frame directive"
 msgstr ""
 
-#: config/tc-mips.c:14186
+#: config/tc-mips.c:14065
 msgid ".mask/.fmask outside of .ent"
 msgstr ""
 
-#: config/tc-mips.c:14193
+#: config/tc-mips.c:14072
 msgid "Bad .mask/.fmask directive"
 msgstr ""
 
-#: config/tc-mips.c:14472
+#: config/tc-mips.c:14337
+#, c-format
 msgid ""
 "MIPS options:\n"
-"-membedded-pic\t\tgenerate embedded position independent code\n"
 "-EB\t\t\tgenerate big endian output\n"
 "-EL\t\t\tgenerate little endian output\n"
 "-g, -g2\t\t\tdo not remove unneeded NOPs or swap branches\n"
@@ -6798,7 +7350,8 @@ msgid ""
 "\t\t\timplicitly with the gp register [default 8]\n"
 msgstr ""
 
-#: config/tc-mips.c:14480
+#: config/tc-mips.c:14344
+#, c-format
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
 "-mips2\t\t\tgenerate MIPS ISA II instructions\n"
@@ -6808,96 +7361,132 @@ msgid ""
 "-mips32                 generate MIPS32 ISA instructions\n"
 "-mips32r2               generate MIPS32 release 2 ISA instructions\n"
 "-mips64                 generate MIPS64 ISA instructions\n"
+"-mips64r2               generate MIPS64 release 2 ISA instructions\n"
 "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14498
+#: config/tc-mips.c:14363
+#, c-format
 msgid ""
 "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
 "-no-mCPU\t\tdon't generate code specific to CPU.\n"
 "\t\t\tFor -mCPU and -no-mCPU, CPU must be one of:\n"
 msgstr ""
 
-#: config/tc-mips.c:14511
+#: config/tc-mips.c:14376
+#, c-format
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
 msgstr ""
 
-#: config/tc-mips.c:14514
+#: config/tc-mips.c:14379
+#, c-format
 msgid ""
+"-mdsp\t\t\tgenerate DSP instructions\n"
+"-mno-dsp\t\tdo not generate DSP instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14382
+#, c-format
+msgid ""
+"-mmt\t\t\tgenerate MT instructions\n"
+"-mno-mt\t\t\tdo not generate MT instructions\n"
+msgstr ""
+
+#: config/tc-mips.c:14385
+#, c-format
+msgid ""
+"-mfix-vr4120\t\twork around certain VR4120 errata\n"
+"-mfix-vr4130\t\twork around VR4130 mflo/mfhi errata\n"
 "-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n"
 "-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n"
+"-mno-shared\t\toptimize output for executables\n"
+"-msym32\t\t\tassume all symbols have 32-bit values\n"
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
-"-n\t\t\twarn about NOPs generated from macros\n"
 "--[no-]construct-floats [dis]allow floating point values to be constructed\n"
 "--trap, --no-break\ttrap exception on div by 0 and mult overflow\n"
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
 msgstr ""
 
-#: config/tc-mips.c:14524
+#: config/tc-mips.c:14398
+#, c-format
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
 "-xgot\t\t\tassume a 32 bit GOT\n"
+"-mpdr, -mno-pdr\t\tenable/disable creation of .pdr sections\n"
+"-mshared, -mno-shared   disable/enable .cpload optimization for\n"
+"                        non-shared code\n"
 "-mabi=ABI\t\tcreate ABI conformant object file for:\n"
 msgstr ""
 
-#: config/tc-mips.c:14540
+#: config/tc-mips.c:14417
+#, c-format
 msgid ""
 "-32\t\t\tcreate o32 ABI object file (default)\n"
 "-n32\t\t\tcreate n32 ABI object file\n"
 "-64\t\t\tcreate 64 ABI object file\n"
 msgstr ""
 
-#: config/tc-mmix.c:677
+#: config/tc-mmix.c:694
+#, c-format
 msgid " MMIX-specific command line options:\n"
 msgstr ""
 
-#: config/tc-mmix.c:678
+#: config/tc-mmix.c:695
+#, c-format
 msgid ""
 "  -fixed-special-register-names\n"
 "                          Allow only the original special register names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:681
+#: config/tc-mmix.c:698
+#, c-format
 msgid "  -globalize-symbols      Make all symbols global.\n"
 msgstr ""
 
-#: config/tc-mmix.c:683
+#: config/tc-mmix.c:700
+#, c-format
 msgid "  -gnu-syntax             Turn off mmixal syntax compatibility.\n"
 msgstr ""
 
-#: config/tc-mmix.c:685
+#: config/tc-mmix.c:702
+#, c-format
 msgid "  -relax                  Create linker relaxable code.\n"
 msgstr ""
 
-#: config/tc-mmix.c:687
+#: config/tc-mmix.c:704
+#, c-format
 msgid ""
 "  -no-predefined-syms     Do not provide mmixal built-in constants.\n"
 "                          Implies -fixed-special-register-names.\n"
 msgstr ""
 
-#: config/tc-mmix.c:690
+#: config/tc-mmix.c:707
+#, c-format
 msgid ""
 "  -no-expand              Do not expand GETA, branches, PUSHJ or JUMP\n"
 "                          into multiple instructions.\n"
 msgstr ""
 
-#: config/tc-mmix.c:693
+#: config/tc-mmix.c:710
+#, c-format
 msgid ""
 "  -no-merge-gregs         Do not merge GREG definitions with nearby values.\n"
 msgstr ""
 
-#: config/tc-mmix.c:695
+#: config/tc-mmix.c:712
+#, c-format
 msgid ""
 "  -linker-allocated-gregs If there's no suitable GREG definition for "
 "the                          operands of an instruction, let the linker "
 "resolve.\n"
 msgstr ""
 
-#: config/tc-mmix.c:698
+#: config/tc-mmix.c:715
+#, c-format
 msgid ""
 "  -x                      Do not warn when an operand to GETA, a branch,\n"
 "                          PUSHJ or JUMP is not known to be within range.\n"
@@ -6905,185 +7494,185 @@ msgid ""
 "                          -linker-allocated-gregs."
 msgstr ""
 
-#: config/tc-mmix.c:825
+#: config/tc-mmix.c:841
 #, c-format
 msgid "unknown opcode: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:947 config/tc-mmix.c:962
+#: config/tc-mmix.c:963 config/tc-mmix.c:978
 msgid "specified location wasn't TETRA-aligned"
 msgstr ""
 
-#: config/tc-mmix.c:949 config/tc-mmix.c:964 config/tc-mmix.c:4015
-#: config/tc-mmix.c:4031
+#: config/tc-mmix.c:965 config/tc-mmix.c:980 config/tc-mmix.c:4124
+#: config/tc-mmix.c:4140
 msgid "unaligned data at an absolute location is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:1074
+#: config/tc-mmix.c:1090
 #, c-format
 msgid "invalid operand to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1096 config/tc-mmix.c:1123 config/tc-mmix.c:1156
-#: config/tc-mmix.c:1164 config/tc-mmix.c:1181 config/tc-mmix.c:1209
-#: config/tc-mmix.c:1230 config/tc-mmix.c:1255 config/tc-mmix.c:1303
-#: config/tc-mmix.c:1401 config/tc-mmix.c:1426 config/tc-mmix.c:1458
-#: config/tc-mmix.c:1490 config/tc-mmix.c:1520 config/tc-mmix.c:1573
-#: config/tc-mmix.c:1590 config/tc-mmix.c:1617 config/tc-mmix.c:1645
-#: config/tc-mmix.c:1672 config/tc-mmix.c:1698 config/tc-mmix.c:1714
-#: config/tc-mmix.c:1740 config/tc-mmix.c:1756 config/tc-mmix.c:1772
-#: config/tc-mmix.c:1835 config/tc-mmix.c:1851
+#: config/tc-mmix.c:1112 config/tc-mmix.c:1139 config/tc-mmix.c:1172
+#: config/tc-mmix.c:1180 config/tc-mmix.c:1197 config/tc-mmix.c:1225
+#: config/tc-mmix.c:1246 config/tc-mmix.c:1271 config/tc-mmix.c:1319
+#: config/tc-mmix.c:1417 config/tc-mmix.c:1442 config/tc-mmix.c:1474
+#: config/tc-mmix.c:1506 config/tc-mmix.c:1536 config/tc-mmix.c:1589
+#: config/tc-mmix.c:1606 config/tc-mmix.c:1633 config/tc-mmix.c:1661
+#: config/tc-mmix.c:1688 config/tc-mmix.c:1714 config/tc-mmix.c:1730
+#: config/tc-mmix.c:1756 config/tc-mmix.c:1772 config/tc-mmix.c:1788
+#: config/tc-mmix.c:1851 config/tc-mmix.c:1867
 #, c-format
 msgid "invalid operands to opcode %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1828
+#: config/tc-mmix.c:1844
 #, c-format
 msgid "unsupported operands to %s: `%s'"
 msgstr ""
 
-#: config/tc-mmix.c:1956
+#: config/tc-mmix.c:1969
 msgid "internal: mmix_prefix_name but empty prefix"
 msgstr ""
 
-#: config/tc-mmix.c:2001
+#: config/tc-mmix.c:2013
 #, c-format
 msgid "too many GREG registers allocated (max %d)"
 msgstr ""
 
-#: config/tc-mmix.c:2061
+#: config/tc-mmix.c:2071
 msgid "BSPEC already active.  Nesting is not supported."
 msgstr ""
 
-#: config/tc-mmix.c:2070
+#: config/tc-mmix.c:2080
 msgid "invalid BSPEC expression"
 msgstr ""
 
-#: config/tc-mmix.c:2086
+#: config/tc-mmix.c:2096
 #, c-format
 msgid "can't create section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2091
+#: config/tc-mmix.c:2101
 #, c-format
 msgid "can't set section flags for section %s"
 msgstr ""
 
-#: config/tc-mmix.c:2113
+#: config/tc-mmix.c:2122
 msgid "ESPEC without preceding BSPEC"
 msgstr ""
 
-#: config/tc-mmix.c:2143
+#: config/tc-mmix.c:2151
 msgid "missing local expression"
 msgstr ""
 
-#: config/tc-mmix.c:2363
+#: config/tc-mmix.c:2389
 msgid "operand out of range, instruction expanded"
 msgstr ""
 
 #. The BFD_RELOC_MMIX_LOCAL-specific message is supposed to be
 #. user-friendly, though a little bit non-substantial.
-#: config/tc-mmix.c:2620
+#: config/tc-mmix.c:2640
 msgid "directive LOCAL must be placed in code or data"
 msgstr ""
 
-#: config/tc-mmix.c:2621
+#: config/tc-mmix.c:2641
 msgid "internal confusion: relocation in a section without contents"
 msgstr ""
 
-#: config/tc-mmix.c:2734
+#: config/tc-mmix.c:2755
 msgid "internal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:2782
+#: config/tc-mmix.c:2803
 msgid "no suitable GREG definition for operands"
 msgstr ""
 
-#: config/tc-mmix.c:2841
+#: config/tc-mmix.c:2862
 msgid "operands were not reducible at assembly-time"
 msgstr ""
 
-#: config/tc-mmix.c:2868
+#: config/tc-mmix.c:2889
 #, c-format
 msgid "cannot generate relocation type for symbol %s, code %s"
 msgstr ""
 
-#: config/tc-mmix.c:2888
+#: config/tc-mmix.c:2909
 #, c-format
 msgid "internal: unhandled label %s"
 msgstr ""
 
-#: config/tc-mmix.c:2942
+#: config/tc-mmix.c:2939
 msgid "[0-9]H labels may not appear alone on a line"
 msgstr ""
 
-#: config/tc-mmix.c:2951
+#: config/tc-mmix.c:2948
 msgid "[0-9]H labels do not mix with dot-pseudos"
 msgstr ""
 
-#: config/tc-mmix.c:3015
+#: config/tc-mmix.c:3036
 msgid "invalid characters in input"
 msgstr ""
 
-#: config/tc-mmix.c:3119
+#: config/tc-mmix.c:3140
 msgid "empty label field for IS"
 msgstr ""
 
-#: config/tc-mmix.c:3344
+#: config/tc-mmix.c:3466
 #, c-format
 msgid "internal: unexpected relax type %d:%d"
 msgstr ""
 
-#: config/tc-mmix.c:3366
+#: config/tc-mmix.c:3488
 msgid "BSPEC without ESPEC."
 msgstr ""
 
-#: config/tc-mmix.c:3568
+#: config/tc-mmix.c:3688
 msgid "GREG expression too complicated"
 msgstr ""
 
-#: config/tc-mmix.c:3583
+#: config/tc-mmix.c:3703
 msgid "internal: GREG expression not resolved to section"
 msgstr ""
 
-#: config/tc-mmix.c:3634
+#: config/tc-mmix.c:3752
 msgid "register section has contents\n"
 msgstr ""
 
-#: config/tc-mmix.c:3768
+#: config/tc-mmix.c:3879
 msgid "section change from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3790
+#: config/tc-mmix.c:3900
 msgid "directive LOC from within a BSPEC/ESPEC pair is not supported"
 msgstr ""
 
-#: config/tc-mmix.c:3801
+#: config/tc-mmix.c:3911
 msgid "invalid LOC expression"
 msgstr ""
 
-#: config/tc-mmix.c:3826 config/tc-mmix.c:3852
+#: config/tc-mmix.c:3936 config/tc-mmix.c:3962
 msgid "LOC expression stepping backwards is not supported"
 msgstr ""
 
 #. We will only get here in rare cases involving #NO_APP,
 #. where the unterminated string is not recognized by the
 #. preformatting pass.
-#: config/tc-mmix.c:3936 config/tc-mmix.c:4097
+#: config/tc-mmix.c:4046 config/tc-mmix.c:4206
 msgid "unterminated string"
 msgstr ""
 
-#: config/tc-mmix.c:3953
+#: config/tc-mmix.c:4063
 msgid "BYTE expression not a pure number"
 msgstr ""
 
 #. Note that mmixal does not allow negative numbers in
 #. BYTE sequences, so neither should we.
-#: config/tc-mmix.c:3962
+#: config/tc-mmix.c:4072
 msgid "BYTE expression not in the range 0..255"
 msgstr ""
 
-#: config/tc-mmix.c:4013 config/tc-mmix.c:4029
+#: config/tc-mmix.c:4122 config/tc-mmix.c:4138
 msgid "data item with alignment larger than location"
 msgstr ""
 
@@ -7093,70 +7682,83 @@ msgstr ""
 msgid "`&' serial number operator is not supported"
 msgstr ""
 
-#: config/tc-mn10200.c:319
+#: config/tc-mn10200.c:305
+#, c-format
 msgid ""
 "MN10200 options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10200.c:793 config/tc-mn10300.c:1387 config/tc-ppc.c:2088
-#: config/tc-s390.c:1540 config/tc-v850.c:1677
+#: config/tc-mn10200.c:931 config/tc-mn10300.c:1392 config/tc-ppc.c:2135
+#: config/tc-s390.c:1557 config/tc-v850.c:1621
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr ""
 
-#: config/tc-mn10200.c:1036 config/tc-mn10300.c:1960 config/tc-ppc.c:2566
-#: config/tc-s390.c:1455 config/tc-v850.c:2100
+#: config/tc-mn10200.c:1174 config/tc-mn10300.c:1965 config/tc-ppc.c:2614
+#: config/tc-s390.c:1472 config/tc-v850.c:2026
 #, c-format
 msgid "junk at end of line: `%s'"
 msgstr ""
 
-#: config/tc-mn10200.c:1242 write.c:2691
+#: config/tc-mn10300.c:695
 #, c-format
-msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
-msgstr ""
-
-#: config/tc-mn10200.c:1347 config/tc-mn10300.c:2589 config/tc-ppc.c:1426
-#: config/tc-v850.c:1606
-#, c-format
-msgid "operand out of range (%s not between %ld and %ld)"
-msgstr ""
-
-#: config/tc-mn10300.c:690
 msgid ""
 "MN10300 options:\n"
 "none yet\n"
 msgstr ""
 
-#: config/tc-mn10300.c:1356 config/tc-sh.c:805 config/tc-xtensa.c:5177
-#: read.c:3764
+#: config/tc-mn10300.c:1361 config/tc-sh.c:778 read.c:3871
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr ""
 
-#: config/tc-mn10300.c:1404
+#: config/tc-mn10300.c:1409
 msgid "Invalid opcode/operands"
 msgstr ""
 
-#: config/tc-mn10300.c:1931
+#: config/tc-mn10300.c:1936
 msgid "Invalid register specification."
 msgstr ""
 
-#: config/tc-mn10300.c:2514
+#: config/tc-mn10300.c:2518
 #, c-format
 msgid "Bad relocation fixup type (%d)"
 msgstr ""
 
-#: config/tc-msp430.c:170
+#: config/tc-msp430.c:552
+msgid ".profiler pseudo requires at least two operands."
+msgstr ""
+
+#: config/tc-msp430.c:611
+msgid "unknown profiling flag - ignored."
+msgstr ""
+
+#: config/tc-msp430.c:627
+msgid "ambigious flags combination - '.profiler' directive ignored."
+msgstr ""
+
+#: config/tc-msp430.c:637
+msgid "profiling in absolute section? Hm..."
+msgstr ""
+
+#: config/tc-msp430.c:726
+#, c-format
 msgid "Known MCU names:\n"
 msgstr ""
 
-#: config/tc-msp430.c:173
+#: config/tc-msp430.c:729
 #, c-format
 msgid "\t %s\n"
 msgstr ""
 
-#: config/tc-msp430.c:183
+#: config/tc-msp430.c:755
+#, c-format
+msgid "redefinition of mcu type %s' to %s'"
+msgstr ""
+
+#: config/tc-msp430.c:798
+#, c-format
 msgid ""
 "MSP430 options:\n"
 "  -mmcu=[msp430-name] select microcontroller type\n"
@@ -7170,154 +7772,194 @@ msgid ""
 "                  msp430x147  msp430x148  msp430x149\n"
 "                  msp430x155  msp430x156  msp430x157\n"
 "                  msp430x167  msp430x168  msp430x169\n"
+"                  msp430x1610 msp430x1611 msp430x1612\n"
 "                  msp430x311  msp430x312  msp430x313  msp430x314  "
 "msp430x315\n"
 "                  msp430x323  msp430x325\n"
 "                  msp430x336  msp430x337\n"
-"                  msp430x412  msp430x413\n"
+"                  msp430x412  msp430x413  msp430x415  msp430x417\n"
+"                  msp430xE423 msp430xE425 msp430E427\n"
+"                  msp430xW423 msp430xW425 msp430W427\n"
+"                  msp430xG437 msp430xG438 msp430G439\n"
 "                  msp430x435  msp430x436  msp430x437\n"
 "                  msp430x447  msp430x448  msp430x449\n"
 msgstr ""
 
-#: config/tc-msp430.c:263
+#: config/tc-msp430.c:821
 #, c-format
-msgid "redefinition of mcu type %s' to %s'"
+msgid ""
+"  -mQ - enable relaxation at assembly time. DANGEROUS!\n"
+"  -mP - enable polymorph instructions\n"
 msgstr ""
 
-#: config/tc-msp430.c:496
+#: config/tc-msp430.c:1011
 #, c-format
-msgid "instruction %s requires %d operand(s)"
+msgid "value %d out of range. Use #lo() or #hi()"
 msgstr ""
 
-#: config/tc-msp430.c:743
+#: config/tc-msp430.c:1099
 #, c-format
-msgid "Even number required. Rounded to %d"
+msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
 msgstr ""
 
-#: config/tc-msp430.c:754
+#: config/tc-msp430.c:1150
 #, c-format
-msgid "Wrong displacement  %d"
+msgid "Registers cannot be used within immediate expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:771
-msgid "instruction requires label sans '$'"
+#: config/tc-msp430.c:1152
+#, c-format
+msgid "unknown operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:777
-msgid "instruction requires label or value in range -511:512"
+#: config/tc-msp430.c:1174 config/tc-msp430.c:1309
+#, c-format
+msgid "value out of range: %d"
 msgstr ""
 
-#: config/tc-msp430.c:783
-msgid "instruction requires label"
+#: config/tc-msp430.c:1185
+#, c-format
+msgid "Registers cannot be used within absolute expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:789
-msgid "Ilegal instruction or not implmented opcode."
+#: config/tc-msp430.c:1187 config/tc-msp430.c:1330
+#, c-format
+msgid "unknown expression in operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:817
+#: config/tc-msp430.c:1201 config/tc-msp430.c:1208
 #, c-format
-msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
+msgid "unknown addressing mode %s"
 msgstr ""
 
-#: config/tc-msp430.c:827
-msgid "this addressing mode is not applicable for destination operand"
+#: config/tc-msp430.c:1216
+#, c-format
+msgid "Bad register name r%s"
 msgstr ""
 
-#: config/tc-msp430.c:944
+#: config/tc-msp430.c:1228
 #, c-format
-msgid "value %ld out of range. Use #lo() or #hi()"
+msgid "MSP430 does not have %d registers"
 msgstr ""
 
-#: config/tc-msp430.c:1040
-#, c-format
-msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
+#: config/tc-msp430.c:1248
+msgid "')' required"
 msgstr ""
 
-#: config/tc-msp430.c:1090 config/tc-msp430.c:1304
+#: config/tc-msp430.c:1261
 #, c-format
-msgid "unknown operand %s"
+msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
 msgstr ""
 
-#: config/tc-msp430.c:1111 config/tc-msp430.c:1242
+#: config/tc-msp430.c:1270
 #, c-format
-msgid "value out of range: %d"
+msgid "unknown operator (r%s substituded as a register name"
 msgstr ""
 
-#: config/tc-msp430.c:1120 config/tc-msp430.c:1259
+#: config/tc-msp430.c:1282 config/tc-msp430.c:1293
 #, c-format
-msgid "unknown expression in operand %s"
+msgid "unknown operator %s"
+msgstr ""
+
+#: config/tc-msp430.c:1287
+msgid "r2 should not be used in indexed addressing mode"
 msgstr ""
 
-#: config/tc-msp430.c:1134 config/tc-msp430.c:1141
+#: config/tc-msp430.c:1328
 #, c-format
-msgid "unknown addressing mode %s"
+msgid "Registers cannot be used as a prefix of indexed expression [%s]"
 msgstr ""
 
-#: config/tc-msp430.c:1149
+#. Unreachable.
+#: config/tc-msp430.c:1377
 #, c-format
-msgid "Bad register name r%s"
+msgid "unknown addressing mode for operand %s"
 msgstr ""
 
-#: config/tc-msp430.c:1161
+#: config/tc-msp430.c:1402
 #, c-format
-msgid "MSP430 does not have %d registers"
+msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
 msgstr ""
 
-#: config/tc-msp430.c:1181
-msgid "')' required"
+#: config/tc-msp430.c:1412
+msgid "this addressing mode is not applicable for destination operand"
 msgstr ""
 
-#: config/tc-msp430.c:1194
+#: config/tc-msp430.c:1456
 #, c-format
-msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
+msgid "instruction %s requires %d operand(s)"
 msgstr ""
 
-#: config/tc-msp430.c:1203
+#: config/tc-msp430.c:1709
 #, c-format
-msgid "unknown operator (r%s substituded as a register name"
+msgid "Even number required. Rounded to %d"
 msgstr ""
 
-#: config/tc-msp430.c:1215 config/tc-msp430.c:1226
+#: config/tc-msp430.c:1720
 #, c-format
-msgid "unknown operator %s"
+msgid "Wrong displacement  %d"
 msgstr ""
 
-#: config/tc-msp430.c:1220
-msgid "r2 should not be used in indexed addressing mode"
+#: config/tc-msp430.c:1737
+msgid "instruction requires label sans '$'"
 msgstr ""
 
-#. Unreachable.
-#: config/tc-msp430.c:1321
+#: config/tc-msp430.c:1742
+msgid "instruction requires label or value in range -511:512"
+msgstr ""
+
+#: config/tc-msp430.c:1749 config/tc-msp430.c:1793 config/tc-msp430.c:1832
+msgid "instruction requires label"
+msgstr ""
+
+#: config/tc-msp430.c:1757 config/tc-msp430.c:1799
+msgid "polymorphs are not enabled. Use -mP option to enable."
+msgstr ""
+
+#: config/tc-msp430.c:1836
+msgid "Ilegal instruction or not implmented opcode."
+msgstr ""
+
+#: config/tc-msp430.c:2187
 #, c-format
-msgid "unknown addressing mode for operand %s"
+msgid "internal inconsistency problem in %s: insn %04lx"
+msgstr ""
+
+#: config/tc-msp430.c:2217 config/tc-msp430.c:2240
+#, c-format
+msgid "internal inconsistency problem in %s: ext. insn %04lx"
 msgstr ""
 
-#: config/tc-ns32k.c:449
+#: config/tc-msp430.c:2252
+#, c-format
+msgid "internal inconsistency problem in %s:  %lx"
+msgstr ""
+
+#: config/tc-ns32k.c:441
 msgid "Invalid syntax in PC-relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:473
+#: config/tc-ns32k.c:465
 msgid "Invalid syntax in External addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:554
+#: config/tc-ns32k.c:546
 msgid "Invalid syntax in Memory Relative addressing mode"
 msgstr ""
 
-#: config/tc-ns32k.c:621
+#: config/tc-ns32k.c:613
 msgid "Invalid scaled-indexed mode, use (b,w,d,q)"
 msgstr ""
 
-#: config/tc-ns32k.c:626
+#: config/tc-ns32k.c:618
 msgid "Syntax in scaled-indexed mode, use [Rn:m] where n=[0..7] m={b,w,d,q}"
 msgstr ""
 
-#: config/tc-ns32k.c:631
+#: config/tc-ns32k.c:623
 msgid "Scaled-indexed addressing mode combined with scaled-index"
 msgstr ""
 
-#: config/tc-ns32k.c:642
+#: config/tc-ns32k.c:634
 msgid "Invalid or illegal addressing mode combined with scaled-index"
 msgstr ""
 
@@ -7329,35 +7971,35 @@ msgstr ""
 msgid "Bad suffix after ':' use {b|w|d} Defaulting to d"
 msgstr ""
 
-#: config/tc-ns32k.c:817
+#: config/tc-ns32k.c:815
 msgid "Very short instr to option, ie you can't do it on a NULLstr"
 msgstr ""
 
-#: config/tc-ns32k.c:870
+#: config/tc-ns32k.c:865
 msgid "No such entry in list. (cpu/mmu register)"
 msgstr ""
 
-#: config/tc-ns32k.c:915
+#: config/tc-ns32k.c:922
 msgid "Internal consistency error.  check ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:939
+#: config/tc-ns32k.c:946
 msgid "Address of immediate operand"
 msgstr ""
 
-#: config/tc-ns32k.c:940
+#: config/tc-ns32k.c:947
 msgid "Invalid immediate write operand."
 msgstr ""
 
-#: config/tc-ns32k.c:1070
+#: config/tc-ns32k.c:1077
 msgid "Bad opcode-table-option, check in file ns32k-opcode.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1107
+#: config/tc-ns32k.c:1110
 msgid "No such opcode"
 msgstr ""
 
-#: config/tc-ns32k.c:1184
+#: config/tc-ns32k.c:1185
 msgid "Bad suffix, defaulting to d"
 msgstr ""
 
@@ -7366,181 +8008,180 @@ msgid "Too many operands passed to instruction"
 msgstr ""
 
 #. Check error in default.
-#: config/tc-ns32k.c:1225
+#: config/tc-ns32k.c:1224
 msgid "Wrong numbers of operands in default, check ns32k-opcodes.h"
 msgstr ""
 
-#: config/tc-ns32k.c:1229
+#: config/tc-ns32k.c:1227
 msgid "Wrong number of operands"
 msgstr ""
 
-#: config/tc-ns32k.c:1355
-msgid "iif convert internal pcrel/binary"
+#: config/tc-ns32k.c:1300
+#, c-format
+msgid "Can not do %d byte pc-relative relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1372
-msgid "Bignum too big for long"
+#: config/tc-ns32k.c:1303
+#, c-format
+msgid "Can not do %d byte relocation for storage type %d"
 msgstr ""
 
-#: config/tc-ns32k.c:1451
-msgid "iif convert internal pcrel/pointer"
+#: config/tc-ns32k.c:1395
+#, c-format
+msgid "value of %ld out of byte displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1456
-msgid "Internal logic error in iif.iifP[n].type"
+#: config/tc-ns32k.c:1405
+#, c-format
+msgid "value of %ld out of word displacement range."
 msgstr ""
 
-#. We cant relax this case.
-#: config/tc-ns32k.c:1493
-msgid "Can't relax difference"
+#: config/tc-ns32k.c:1420
+#, c-format
+msgid "value of %ld out of double word displacement range."
 msgstr ""
 
-#: config/tc-ns32k.c:1541
-msgid "Displacement to large for :d"
+#: config/tc-ns32k.c:1441
+#, c-format
+msgid "Internal logic error.  line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1554
-msgid "Internal logic error in iif.iifP[].type"
+#: config/tc-ns32k.c:1489
+#, c-format
+msgid "Internal logic error. line %d, file \"%s\""
 msgstr ""
 
-#: config/tc-ns32k.c:1614
-#, c-format
-msgid "Can not do %d byte pc-relative relocation for storage type %d"
+#: config/tc-ns32k.c:1590
+msgid "Bit field out of range"
 msgstr ""
 
-#: config/tc-ns32k.c:1617
-#, c-format
-msgid "Can not do %d byte relocation for storage type %d"
+#: config/tc-ns32k.c:1690
+msgid "iif convert internal pcrel/binary"
 msgstr ""
 
-#. Fatal.
-#: config/tc-ns32k.c:1652
-#, c-format
-msgid "Can't hash %s: %s"
+#: config/tc-ns32k.c:1707
+msgid "Bignum too big for long"
 msgstr ""
 
-#: config/tc-ns32k.c:1740
-#, c-format
-msgid "value of %ld out of byte displacement range."
+#: config/tc-ns32k.c:1784
+msgid "iif convert internal pcrel/pointer"
 msgstr ""
 
-#: config/tc-ns32k.c:1749
-#, c-format
-msgid "value of %ld out of word displacement range."
+#: config/tc-ns32k.c:1789
+msgid "Internal logic error in iif.iifP[n].type"
 msgstr ""
 
-#: config/tc-ns32k.c:1763
-#, c-format
-msgid "value of %ld out of double word displacement range."
+#. We cant relax this case.
+#: config/tc-ns32k.c:1825
+msgid "Can't relax difference"
 msgstr ""
 
-#: config/tc-ns32k.c:1783
-#, c-format
-msgid "Internal logic error.  line %d, file \"%s\""
+#: config/tc-ns32k.c:1866
+msgid "Displacement to large for :d"
 msgstr ""
 
-#: config/tc-ns32k.c:1831
-#, c-format
-msgid "Internal logic error. line %d, file \"%s\""
+#: config/tc-ns32k.c:1879
+msgid "Internal logic error in iif.iifP[].type"
 msgstr ""
 
-#: config/tc-ns32k.c:1936
-msgid "Bit field out of range"
+#. Fatal.
+#: config/tc-ns32k.c:1911
+#, c-format
+msgid "Can't hash %s: %s"
 msgstr ""
 
-#: config/tc-ns32k.c:2183
+#: config/tc-ns32k.c:2181
 #, c-format
 msgid "invalid architecture option -m%s, ignored"
 msgstr ""
 
-#: config/tc-ns32k.c:2196
+#: config/tc-ns32k.c:2194
 #, c-format
 msgid "invalid default displacement size \"%s\". Defaulting to %d."
 msgstr ""
 
-#: config/tc-ns32k.c:2213
+#: config/tc-ns32k.c:2210
+#, c-format
 msgid ""
 "NS32K options:\n"
 "-m32032 | -m32532\tselect variant of NS32K architecture\n"
 "--disp-size-default=<1|2|4>\n"
 msgstr ""
 
-#: config/tc-ns32k.c:2397
+#: config/tc-ns32k.c:2285
 #, c-format
 msgid "Cannot find relocation type for symbol %s, code %d"
 msgstr ""
 
-#: config/tc-or32.c:465 config/tc-or32.c:680
+#: config/tc-or32.c:360
 #, c-format
 msgid "unknown opcode1: `%s'"
 msgstr ""
 
-#: config/tc-or32.c:471 config/tc-or32.c:686
+#: config/tc-or32.c:366
 #, c-format
 msgid "unknown opcode2 `%s'."
 msgstr ""
 
-#: config/tc-or32.c:510 config/tc-or32.c:725
+#: config/tc-or32.c:403
 #, c-format
 msgid "instruction not allowed: %s"
 msgstr ""
 
-#: config/tc-or32.c:513 config/tc-or32.c:728
+#: config/tc-or32.c:406
 #, c-format
 msgid "too many operands: %s"
 msgstr ""
 
-#: config/tc-or32.c:603 config/tc-or32.c:819
+#: config/tc-or32.c:490
 msgid "call/jmp target out of range (1)"
 msgstr ""
 
-#: config/tc-or32.c:1016 config/tc-or32.c:1133
-msgid "the linker will not handle this relocation correctly (1)"
-msgstr ""
-
-#: config/tc-or32.c:1025 config/tc-or32.c:1142
+#: config/tc-or32.c:674
 msgid "call/jmp target out of range (2)"
 msgstr ""
 
-#: config/tc-or32.c:1433
-msgid "register out of range"
+#: config/tc-or32.c:693
+#, c-format
+msgid "bad relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-or32.c:1478
+#: config/tc-or32.c:885
 msgid "invalid register in & expression"
 msgstr ""
 
-#: config/tc-pdp11.c:454
+#: config/tc-pdp11.c:490
 msgid "Low order bits truncated in immediate float operand"
 msgstr ""
 
-#: config/tc-pdp11.c:665
+#: config/tc-pdp11.c:679
 #, c-format
 msgid "Unknown instruction '%s'"
 msgstr ""
 
-#: config/tc-pj.c:82 config/tc-pj.c:90
+#: config/tc-pj.c:66 config/tc-pj.c:75
 msgid "confusing relocation expressions"
 msgstr ""
 
-#: config/tc-pj.c:181
+#: config/tc-pj.c:158
 msgid "can't have relocation for ipush"
 msgstr ""
 
-#: config/tc-pj.c:290 config/tc-xtensa.c:4976
+#: config/tc-pj.c:261
 #, c-format
 msgid "unknown opcode %s"
 msgstr ""
 
-#: config/tc-pj.c:439
+#: config/tc-pj.c:404
+#, c-format
 msgid ""
 "PJ options:\n"
 "-little\t\t\tgenerate little endian code\n"
 "-big\t\t\tgenerate big endian code\n"
 msgstr ""
 
-#: config/tc-pj.c:469 config/tc-sh.c:3464 config/tc-sh.c:3471
-#: config/tc-sh.c:3478 config/tc-sh.c:3485
+#: config/tc-pj.c:431 config/tc-sh.c:3955 config/tc-sh.c:3962
+#: config/tc-sh.c:3969 config/tc-sh.c:3976
 msgid "pcrel too far"
 msgstr ""
 
@@ -7552,17 +8193,18 @@ msgstr ""
 msgid "estimate size\n"
 msgstr ""
 
-#: config/tc-ppc.c:879
+#: config/tc-ppc.c:991
 #, c-format
 msgid "%s unsupported"
 msgstr ""
 
-#: config/tc-ppc.c:1029 config/tc-s390.c:414 config/tc-s390.c:421
+#: config/tc-ppc.c:1057 config/tc-s390.c:417 config/tc-s390.c:424
 #, c-format
 msgid "invalid switch -m%s"
 msgstr ""
 
-#: config/tc-ppc.c:1066
+#: config/tc-ppc.c:1094
+#, c-format
 msgid ""
 "PowerPC options:\n"
 "-a32\t\t\tgenerate ELF32/XCOFF32\n"
@@ -7574,31 +8216,37 @@ msgid ""
 "-mppc, -mppc32, -m603, -m604\n"
 "\t\t\tgenerate code for PowerPC 603/604\n"
 "-m403, -m405\t\tgenerate code for PowerPC 403/405\n"
+"-m440\t\t\tgenerate code for PowerPC 440\n"
 "-m7400, -m7410, -m7450, -m7455\n"
 "\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"
 msgstr ""
 
-#: config/tc-ppc.c:1079
+#: config/tc-ppc.c:1108
+#, c-format
 msgid ""
 "-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n"
 "-mppc64bridge\t\tgenerate code for PowerPC 64, including bridge insns\n"
 "-mbooke64\t\tgenerate code for 64-bit PowerPC BookE\n"
 "-mbooke, mbooke32\tgenerate code for 32-bit PowerPC BookE\n"
 "-mpower4\t\tgenerate code for Power4 architecture\n"
+"-mpower5\t\tgenerate code for Power5 architecture\n"
 "-mcom\t\t\tgenerate code Power/PowerPC common instructions\n"
 "-many\t\t\tgenerate code for any architecture (PWR/PWRX/PPC)\n"
 msgstr ""
 
-#: config/tc-ppc.c:1087
+#: config/tc-ppc.c:1117
+#, c-format
 msgid ""
 "-maltivec\t\tgenerate code for AltiVec\n"
+"-me300\t\t\tgenerate code for PowerPC e300 family\n"
 "-me500, -me500x2\tgenerate code for Motorola e500 core complex\n"
 "-mspe\t\t\tgenerate code for Motorola SPE instructions\n"
 "-mregnames\t\tAllow symbolic names for registers\n"
 "-mno-regnames\t\tDo not allow symbolic names for registers\n"
 msgstr ""
 
-#: config/tc-ppc.c:1094
+#: config/tc-ppc.c:1125
+#, c-format
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
 "-mrelocatable-lib\tsupport for GCC's -mrelocatble-lib option\n"
@@ -7613,221 +8261,252 @@ msgid ""
 "-Qy, -Qn\t\tignored\n"
 msgstr ""
 
-#: config/tc-ppc.c:1136
+#: config/tc-ppc.c:1162
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
 msgstr ""
 
-#: config/tc-ppc.c:1161
+#: config/tc-ppc.c:1188
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr ""
 
-#: config/tc-ppc.c:1257 config/tc-s390.c:516
+#: config/tc-ppc.c:1285 config/tc-s390.c:519
 #, c-format
 msgid "Internal assembler error for instruction %s"
 msgstr ""
 
-#: config/tc-ppc.c:1277
+#: config/tc-ppc.c:1309
 #, c-format
 msgid "Internal assembler error for macro %s"
 msgstr ""
 
-#: config/tc-ppc.c:1599
+#: config/tc-ppc.c:1640
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr ""
 
-#: config/tc-ppc.c:1666
+#: config/tc-ppc.c:1707
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr ""
 
-#: config/tc-ppc.c:1773
+#: config/tc-ppc.c:1814
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ""
 
-#: config/tc-ppc.c:1855
+#: config/tc-ppc.c:1896
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr ""
 
-#: config/tc-ppc.c:1981
+#: config/tc-ppc.c:1945
+msgid "TOC section size exceeds 64k"
+msgstr ""
+
+#: config/tc-ppc.c:2027
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr ""
 
-#: config/tc-ppc.c:1995
+#: config/tc-ppc.c:2041
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2272
+#: config/tc-ppc.c:2320
 msgid "[tocv] symbol is not a toc symbol"
 msgstr ""
 
-#: config/tc-ppc.c:2283
+#: config/tc-ppc.c:2331
 msgid "Unimplemented toc32 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2288
+#: config/tc-ppc.c:2336
 msgid "Unimplemented toc64 expression modifier"
 msgstr ""
 
-#: config/tc-ppc.c:2292
+#: config/tc-ppc.c:2340
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr ""
 
-#: config/tc-ppc.c:2510
+#: config/tc-ppc.c:2558
 msgid "unsupported relocation for DS offset field"
 msgstr ""
 
-#: config/tc-ppc.c:2554
+#: config/tc-ppc.c:2602
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr ""
 
-#: config/tc-ppc.c:2703
+#: config/tc-ppc.c:2645 config/tc-ppc.h:111
+msgid "instruction address is not a multiple of 4"
+msgstr ""
+
+#: config/tc-ppc.c:2756
 msgid "wrong number of operands"
 msgstr ""
 
-#: config/tc-ppc.c:2759
+#: config/tc-ppc.c:2812
 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string"
 msgstr ""
 
-#: config/tc-ppc.c:2874
+#: config/tc-ppc.c:2927
 msgid "missing size"
 msgstr ""
 
-#: config/tc-ppc.c:2883
+#: config/tc-ppc.c:2936
 msgid "negative size"
 msgstr ""
 
-#: config/tc-ppc.c:2920
+#: config/tc-ppc.c:2973
 msgid "missing real symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:2941
+#: config/tc-ppc.c:2994
 msgid "attempt to redefine symbol"
 msgstr ""
 
-#: config/tc-ppc.c:3188
+#: config/tc-ppc.c:3241
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr ""
 
-#: config/tc-ppc.c:3265
+#: config/tc-ppc.c:3318
 msgid "missing rename string"
 msgstr ""
 
-#: config/tc-ppc.c:3296 config/tc-ppc.c:3851 read.c:3060
+#: config/tc-ppc.c:3349 config/tc-ppc.c:3904 read.c:3064
 msgid "missing value"
 msgstr ""
 
-#: config/tc-ppc.c:3314
+#: config/tc-ppc.c:3367
 msgid "illegal .stabx expression; zero assumed"
 msgstr ""
 
-#: config/tc-ppc.c:3346
+#: config/tc-ppc.c:3399
 msgid "missing class"
 msgstr ""
 
-#: config/tc-ppc.c:3355
+#: config/tc-ppc.c:3408
 msgid "missing type"
 msgstr ""
 
-#: config/tc-ppc.c:3436
+#: config/tc-ppc.c:3489
 msgid "missing symbol name"
 msgstr ""
 
-#: config/tc-ppc.c:3630
+#: config/tc-ppc.c:3683
 msgid "nested .bs blocks"
 msgstr ""
 
-#: config/tc-ppc.c:3663
+#: config/tc-ppc.c:3716
 msgid ".es without preceding .bs"
 msgstr ""
 
-#: config/tc-ppc.c:3843
+#: config/tc-ppc.c:3896
 msgid "non-constant byte count"
 msgstr ""
 
-#: config/tc-ppc.c:3891
+#: config/tc-ppc.c:3944
 msgid ".tc not in .toc section"
 msgstr ""
 
-#: config/tc-ppc.c:3910
+#: config/tc-ppc.c:3963
 msgid ".tc with no label"
 msgstr ""
 
-#: config/tc-ppc.c:4021
+#: config/tc-ppc.c:4055
+msgid ".machine stack overflow"
+msgstr ""
+
+#: config/tc-ppc.c:4062
+msgid ".machine stack underflow"
+msgstr ""
+
+#: config/tc-ppc.c:4069
+#, c-format
+msgid "invalid machine `%s'"
+msgstr ""
+
+#: config/tc-ppc.c:4123
 msgid "No previous section to return to. Directive ignored."
 msgstr ""
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:4438
+#: config/tc-ppc.c:4540
 msgid "Unsupported section attribute -- 'a'"
 msgstr ""
 
-#: config/tc-ppc.c:4627
+#: config/tc-ppc.c:4729
 msgid "bad symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4720
+#: config/tc-ppc.c:4822
 msgid "Unrecognized symbol suffix"
 msgstr ""
 
-#: config/tc-ppc.c:4806
+#: config/tc-ppc.c:4912
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr ""
 
-#: config/tc-ppc.c:4819
+#: config/tc-ppc.c:4925
 msgid ".ef with no preceding .function"
 msgstr ""
 
-#: config/tc-ppc.c:4947
+#: config/tc-ppc.c:5053
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr ""
 
-#: config/tc-ppc.c:5251
+#: config/tc-ppc.c:5357
 msgid "symbol in .toc does not match any .tc"
 msgstr ""
 
-#: config/tc-ppc.c:5584 config/tc-s390.c:2072 config/tc-v850.c:2401
-#: config/tc-xstormy16.c:537
+#: config/tc-ppc.c:5686 config/tc-s390.c:2092 config/tc-v850.c:2314
+#: config/tc-xstormy16.c:538
 msgid "unresolved expression that must be resolved"
 msgstr ""
 
-#: config/tc-ppc.c:5587
+#: config/tc-ppc.c:5689
 #, c-format
 msgid "unsupported relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5662
+#: config/tc-ppc.c:5762
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr ""
 
-#: config/tc-ppc.c:5667
+#: config/tc-ppc.c:5767
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr ""
 
-#: config/tc-ppc.c:5841
+#: config/tc-ppc.c:5949
+#, c-format
+msgid "Unable to handle reference to symbol %s"
+msgstr ""
+
+#: config/tc-ppc.c:5952
+msgid "Unable to resolve expression"
+msgstr ""
+
+#: config/tc-ppc.c:5979
 msgid "must branch to an address a multiple of 4"
 msgstr ""
 
-#: config/tc-ppc.c:5845
+#: config/tc-ppc.c:5983
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr ""
 
-#: config/tc-ppc.c:5876
+#: config/tc-ppc.c:6014
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr ""
 
-#: config/tc-s390.c:457
+#: config/tc-s390.c:460
+#, c-format
 msgid ""
 "        S390 options:\n"
 "        -mregnames        Allow symbolic names for registers\n"
@@ -7837,529 +8516,578 @@ msgid ""
 "        -m64              Set file format to 64 bit format\n"
 msgstr ""
 
-#: config/tc-s390.c:464
+#: config/tc-s390.c:467
+#, c-format
 msgid ""
 "        -V                print assembler version number\n"
 "        -Qy, -Qn          ignored\n"
 msgstr ""
 
-#: config/tc-s390.c:500
+#: config/tc-s390.c:503
 #, c-format
 msgid "Internal assembler error for instruction format %s"
 msgstr ""
 
-#: config/tc-s390.c:782
+#: config/tc-s390.c:766
 #, c-format
 msgid "identifier+constant@%s means identifier@%s+constant"
 msgstr ""
 
-#: config/tc-s390.c:865
+#: config/tc-s390.c:849
 msgid "Can't handle O_big in s390_exp_compare"
 msgstr ""
 
-#: config/tc-s390.c:949
+#: config/tc-s390.c:933
 msgid "Invalid suffix for literal pool entry"
 msgstr ""
 
-#: config/tc-s390.c:1006
+#: config/tc-s390.c:990
 msgid "Big number is too big"
 msgstr ""
 
-#: config/tc-s390.c:1144 config/tc-s390.c:1722
-#, c-format
-msgid "%s relocations do not fit in %d bytes"
-msgstr ""
-
-#: config/tc-s390.c:1154
+#: config/tc-s390.c:1138
 msgid "relocation not applicable"
 msgstr ""
 
-#: config/tc-s390.c:1342
+#: config/tc-s390.c:1326
 msgid "invalid operand suffix"
 msgstr ""
 
-#: config/tc-s390.c:1365
+#: config/tc-s390.c:1349
 msgid "syntax error; missing '(' after displacement"
 msgstr ""
 
-#: config/tc-s390.c:1375 config/tc-s390.c:1408 config/tc-s390.c:1427
+#: config/tc-s390.c:1365 config/tc-s390.c:1409 config/tc-s390.c:1439
 msgid "syntax error; expected ,"
 msgstr ""
 
-#: config/tc-s390.c:1402
+#: config/tc-s390.c:1397
 msgid "syntax error; missing ')' after base register"
 msgstr ""
 
-#: config/tc-s390.c:1420
+#: config/tc-s390.c:1426
 msgid "syntax error; ')' not allowed here"
 msgstr ""
 
-#: config/tc-s390.c:1602 config/tc-s390.c:1622 config/tc-s390.c:1635
+#: config/tc-s390.c:1619 config/tc-s390.c:1642 config/tc-s390.c:1655
 msgid "Invalid .insn format\n"
 msgstr ""
 
-#: config/tc-s390.c:1610
+#: config/tc-s390.c:1627
 #, c-format
 msgid "Unrecognized opcode format: `%s'"
 msgstr ""
 
-#: config/tc-s390.c:1638
+#: config/tc-s390.c:1658
 msgid "second operand of .insn not a constant\n"
 msgstr ""
 
-#: config/tc-s390.c:1641
+#: config/tc-s390.c:1661
 msgid "missing comma after insn constant\n"
 msgstr ""
 
-#: config/tc-s390.c:2075
+#: config/tc-s390.c:2095
 msgid "unsupported relocation type"
 msgstr ""
 
-#: config/tc-sh64.c:596
+#: config/tc-sh64.c:568
 msgid "This operand must be constant at assembly time"
 msgstr ""
 
-#: config/tc-sh64.c:711
+#: config/tc-sh64.c:681
 msgid "Invalid operand expression"
 msgstr ""
 
-#: config/tc-sh64.c:798 config/tc-sh64.c:904
+#: config/tc-sh64.c:773 config/tc-sh64.c:877
 msgid "PTB operand is a SHmedia symbol"
 msgstr ""
 
-#: config/tc-sh64.c:801 config/tc-sh64.c:901
+#: config/tc-sh64.c:776 config/tc-sh64.c:874
 msgid "PTA operand is a SHcompact symbol"
 msgstr ""
 
-#: config/tc-sh64.c:817
+#: config/tc-sh64.c:792
 msgid "invalid expression in operand"
 msgstr ""
 
-#: config/tc-sh64.c:1514
+#: config/tc-sh64.c:1483
 #, c-format
 msgid "invalid operand, not a 5-bit unsigned value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1519
+#: config/tc-sh64.c:1488
 #, c-format
 msgid "invalid operand, not a 6-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1524
+#: config/tc-sh64.c:1493
 #, c-format
 msgid "invalid operand, not a 6-bit unsigned value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1529 config/tc-sh64.c:1541
+#: config/tc-sh64.c:1498 config/tc-sh64.c:1510
 #, c-format
 msgid "invalid operand, not a 11-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1531
+#: config/tc-sh64.c:1500
 #, c-format
 msgid "invalid operand, not a multiple of 32: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1536
+#: config/tc-sh64.c:1505
 #, c-format
 msgid "invalid operand, not a 10-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1543
+#: config/tc-sh64.c:1512
 #, c-format
 msgid "invalid operand, not an even value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1548
+#: config/tc-sh64.c:1517
 #, c-format
 msgid "invalid operand, not a 12-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1550
+#: config/tc-sh64.c:1519
 #, c-format
 msgid "invalid operand, not a multiple of 4: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1555
+#: config/tc-sh64.c:1524
 #, c-format
 msgid "invalid operand, not a 13-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1557
+#: config/tc-sh64.c:1526
 #, c-format
 msgid "invalid operand, not a multiple of 8: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1562
+#: config/tc-sh64.c:1531
 #, c-format
 msgid "invalid operand, not a 16-bit signed value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1567
+#: config/tc-sh64.c:1536
 #, c-format
 msgid "invalid operand, not an 16-bit unsigned value: %d"
 msgstr ""
 
-#: config/tc-sh64.c:1573
+#: config/tc-sh64.c:1542
 msgid "operand out of range for PT, PTA and PTB"
 msgstr ""
 
-#: config/tc-sh64.c:1575
+#: config/tc-sh64.c:1544
 #, c-format
 msgid "operand not a multiple of 4 for PT, PTA or PTB: %d"
 msgstr ""
 
-#: config/tc-sh64.c:2103
+#: config/tc-sh64.c:2064
 #, c-format
 msgid "MOVI operand is not a 32-bit signed value: 0x%8x%08x"
 msgstr ""
 
-#: config/tc-sh64.c:2466 config/tc-sh64.c:2631 config/tc-sh64.c:2646
+#: config/tc-sh64.c:2421 config/tc-sh64.c:2584 config/tc-sh64.c:2599
 msgid "invalid PIC reference"
 msgstr ""
 
-#: config/tc-sh64.c:2524
+#: config/tc-sh64.c:2478
 msgid "can't find opcode"
 msgstr ""
 
-#: config/tc-sh64.c:2854
+#: config/tc-sh64.c:2681 config/tc-sh64.c:2721
+msgid "invalid operand: expression in PT target"
+msgstr ""
+
+#: config/tc-sh64.c:2812
 #, c-format
 msgid "invalid operands to %s"
 msgstr ""
 
-#: config/tc-sh64.c:2860
+#: config/tc-sh64.c:2818
 #, c-format
 msgid "excess operands to %s"
 msgstr ""
 
-#: config/tc-sh64.c:2906
+#: config/tc-sh64.c:2863
 #, c-format
 msgid "The `.mode %s' directive is not valid with this architecture"
 msgstr ""
 
-#: config/tc-sh64.c:2914
+#: config/tc-sh64.c:2871
 #, c-format
 msgid "Invalid argument to .mode: %s"
 msgstr ""
 
-#: config/tc-sh64.c:2945
+#: config/tc-sh64.c:2901
 #, c-format
 msgid "The `.abi %s' directive is not valid with this architecture"
 msgstr ""
 
-#: config/tc-sh64.c:2951
+#: config/tc-sh64.c:2907
 msgid "`.abi 64' but command-line options do not specify 64-bit ABI"
 msgstr ""
 
-#: config/tc-sh64.c:2956
+#: config/tc-sh64.c:2912
 msgid "`.abi 32' but command-line options do not specify 32-bit ABI"
 msgstr ""
 
-#: config/tc-sh64.c:2959
+#: config/tc-sh64.c:2915
 #, c-format
 msgid "Invalid argument to .abi: %s"
 msgstr ""
 
-#: config/tc-sh64.c:3014
+#: config/tc-sh64.c:2970
 msgid "-no-mix is invalid without specifying SHcompact or SHmedia"
 msgstr ""
 
-#: config/tc-sh64.c:3019
+#: config/tc-sh64.c:2975
 msgid "-shcompact-const-crange is invalid without SHcompact"
 msgstr ""
 
-#: config/tc-sh64.c:3022
+#: config/tc-sh64.c:2978
 msgid "-expand-pt32 only valid with -abi=64"
 msgstr ""
 
-#: config/tc-sh64.c:3025
+#: config/tc-sh64.c:2981
 msgid "-no-expand only valid with SHcompact or SHmedia"
 msgstr ""
 
-#: config/tc-sh64.c:3028
+#: config/tc-sh64.c:2984
 msgid "-expand-pt32 invalid together with -no-expand"
 msgstr ""
 
-#: config/tc-sh64.c:3250
+#: config/tc-sh64.c:3201
 msgid ""
 "SHmedia code not allowed in same section as constants and SHcompact code"
 msgstr ""
 
-#: config/tc-sh64.c:3268
+#: config/tc-sh64.c:3219
 msgid "No segment info for current section"
 msgstr ""
 
-#: config/tc-sh64.c:3310
+#: config/tc-sh64.c:3258
 msgid "duplicate datalabel operator ignored"
 msgstr ""
 
-#: config/tc-sh64.c:3380
+#: config/tc-sh64.c:3328
 msgid "Invalid DataLabel expression"
 msgstr ""
 
-#: config/tc-sh.c:91
+#: config/tc-sh.c:65
 msgid "directive .big encountered when option -big required"
 msgstr ""
 
-#: config/tc-sh.c:102
+#: config/tc-sh.c:75
 msgid "directive .little encountered when option -little required"
 msgstr ""
 
-#: config/tc-sh.c:776
-msgid "Invalid PIC expression."
+#: config/tc-sh.c:1277
+msgid "misplaced PIC operand"
 msgstr ""
 
-#: config/tc-sh.c:1269
-msgid "misplaced PIC operand"
+#: config/tc-sh.c:1315
+msgid "illegal double indirection"
 msgstr ""
 
-#: config/tc-sh.c:1310
+#: config/tc-sh.c:1324
 msgid "illegal register after @-"
 msgstr ""
 
-#: config/tc-sh.c:1326
+#: config/tc-sh.c:1340
 msgid "must be @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1350
+#: config/tc-sh.c:1364
 msgid "syntax error in @(r0,...)"
 msgstr ""
 
-#: config/tc-sh.c:1355
+#: config/tc-sh.c:1369
 msgid "syntax error in @(r0...)"
 msgstr ""
 
-#: config/tc-sh.c:1396
+#: config/tc-sh.c:1414
 msgid "Deprecated syntax."
 msgstr ""
 
-#: config/tc-sh.c:1408 config/tc-sh.c:1413
+#: config/tc-sh.c:1426 config/tc-sh.c:1431
 msgid "syntax error in @(disp,[Rn, gbr, pc])"
 msgstr ""
 
-#: config/tc-sh.c:1418
+#: config/tc-sh.c:1436
 msgid "expecting )"
 msgstr ""
 
-#: config/tc-sh.c:1426
+#: config/tc-sh.c:1444
 msgid "illegal register after @"
 msgstr ""
 
-#: config/tc-sh.c:1977
+#: config/tc-sh.c:2115
+#, c-format
+msgid "unhandled %d\n"
+msgstr ""
+
+#: config/tc-sh.c:2281
 #, c-format
 msgid "Invalid register: 'r%d'"
 msgstr ""
 
-#: config/tc-sh.c:2143
+#: config/tc-sh.c:2385
+#, c-format
+msgid "failed for %d\n"
+msgstr ""
+
+#: config/tc-sh.c:2498 config/tc-sh.c:2894
+msgid "invalid operands for opcode"
+msgstr ""
+
+#: config/tc-sh.c:2503
 msgid "insn can't be combined with parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2150 config/tc-sh.c:2161
+#: config/tc-sh.c:2510 config/tc-sh.c:2521 config/tc-sh.c:2553
 msgid "multiple movx specifications"
 msgstr ""
 
-#: config/tc-sh.c:2155 config/tc-sh.c:2182
+#: config/tc-sh.c:2515 config/tc-sh.c:2537 config/tc-sh.c:2576
 msgid "multiple movy specifications"
 msgstr ""
 
-#: config/tc-sh.c:2163
+#: config/tc-sh.c:2524 config/tc-sh.c:2557
 msgid "invalid movx address register"
 msgstr ""
 
-#: config/tc-sh.c:2169 config/tc-sh.c:2174
+#: config/tc-sh.c:2526
+msgid "insn cannot be combined with non-nopy"
+msgstr ""
+
+#: config/tc-sh.c:2540 config/tc-sh.c:2596
+msgid "invalid movy address register"
+msgstr ""
+
+#: config/tc-sh.c:2542
+msgid "insn cannot be combined with non-nopx"
+msgstr ""
+
+#: config/tc-sh.c:2555
+msgid "previous movy requires nopx"
+msgstr ""
+
+#: config/tc-sh.c:2563 config/tc-sh.c:2568
 msgid "invalid movx dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2191 config/tc-sh.c:2196
-msgid "invalid movy dsp register"
+#: config/tc-sh.c:2578
+msgid "previous movx requires nopy"
 msgstr ""
 
-#: config/tc-sh.c:2200
-msgid "invalid movy address register"
+#: config/tc-sh.c:2587 config/tc-sh.c:2592
+msgid "invalid movy dsp register"
 msgstr ""
 
-#: config/tc-sh.c:2206
+#: config/tc-sh.c:2602
 msgid "dsp immediate shift value not constant"
 msgstr ""
 
-#: config/tc-sh.c:2213 config/tc-sh.c:2226
+#: config/tc-sh.c:2616 config/tc-sh.c:2642
 msgid "multiple parallel processing specifications"
 msgstr ""
 
-#: config/tc-sh.c:2219
+#: config/tc-sh.c:2635
 msgid "multiple condition specifications"
 msgstr ""
 
-#: config/tc-sh.c:2235
+#: config/tc-sh.c:2673
 msgid "insn cannot be combined with pmuls"
 msgstr ""
 
-#: config/tc-sh.c:2252
-msgid "bad padd / psub pmuls output operand"
+#: config/tc-sh.c:2689
+msgid "bad combined pmuls output operand"
 msgstr ""
 
-#: config/tc-sh.c:2262
+#: config/tc-sh.c:2699
 msgid "destination register is same for parallel insns"
 msgstr ""
 
-#: config/tc-sh.c:2271
+#: config/tc-sh.c:2708
 msgid "condition not followed by conditionalizable insn"
 msgstr ""
 
-#: config/tc-sh.c:2281
+#: config/tc-sh.c:2718
 msgid "unrecognized characters at end of parallel processing insn"
 msgstr ""
 
-#: config/tc-sh.c:2417
+#: config/tc-sh.c:2834
+msgid "opcode not valid for this cpu variant"
+msgstr ""
+
+#: config/tc-sh.c:2867
+msgid "Delayed branches not available on SH1"
+msgstr ""
+
+#: config/tc-sh.c:2899
 #, c-format
 msgid "excess operands: '%s'"
 msgstr ""
 
-#: config/tc-sh.c:2569
+#: config/tc-sh.c:3026
 msgid ".uses pseudo-op seen when not relaxing"
 msgstr ""
 
-#: config/tc-sh.c:2575
+#: config/tc-sh.c:3032
 msgid "bad .uses format"
 msgstr ""
 
-#: config/tc-sh.c:2654
+#: config/tc-sh.c:3130
 msgid "Invalid combination: --isa=SHcompact with --isa=SHmedia"
 msgstr ""
 
-#: config/tc-sh.c:2660
+#: config/tc-sh.c:3136
 msgid "Invalid combination: --isa=SHmedia with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:2662
+#: config/tc-sh.c:3138
 msgid "Invalid combination: --abi=64 with --isa=SHcompact"
 msgstr ""
 
-#: config/tc-sh.c:2675
+#: config/tc-sh.c:3179
 msgid "Invalid combination: --abi=32 with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:2681
+#: config/tc-sh.c:3185
 msgid "Invalid combination: --abi=64 with --abi=32"
 msgstr ""
 
-#: config/tc-sh.c:2683
+#: config/tc-sh.c:3187
 msgid "Invalid combination: --isa=SHcompact with --abi=64"
 msgstr ""
 
-#: config/tc-sh.c:2718
+#: config/tc-sh.c:3221
+#, c-format
 msgid ""
 "SH options:\n"
-"-little\t\t\tgenerate little endian code\n"
-"-big\t\t\tgenerate big endian code\n"
-"-relax\t\t\talter jump instructions for long displacements\n"
-"-small\t\t\talign sections to 4 byte boundaries, not 16\n"
-"-dsp\t\t\tenable sh-dsp insns, and disable sh2e/sh3e/sh4 insns.\n"
+"--little\t\tgenerate little endian code\n"
+"--big\t\t\tgenerate big endian code\n"
+"--relax\t\t\talter jump instructions for long displacements\n"
+"--renesas\t\tdisable optimization with section symbol for\n"
+"\t\t\tcompatibility with Renesas assembler.\n"
+"--small\t\t\talign sections to 4 byte boundaries, not 16\n"
+"--dsp\t\t\tenable sh-dsp insns, and disable floating-point ISAs.\n"
+"--allow-reg-prefix\tallow '$' as a register name prefix.\n"
+"--isa=[any\t\tuse most appropriate isa\n"
+"    | dsp               same as '-dsp'\n"
+"    | fp"
+msgstr ""
+
+#: config/tc-sh.c:3247
+#, c-format
+msgid ""
+"--isa=[shmedia\t\tset as the default instruction set for SH64\n"
+"    | SHmedia\n"
+"    | shcompact\n"
+"    | SHcompact]\n"
 msgstr ""
 
-#: config/tc-sh.c:2726
+#: config/tc-sh.c:3252
+#, c-format
 msgid ""
-"-isa=[shmedia\t\tset default instruction set for SH64\n"
-"      | SHmedia\n"
-"      | shcompact\n"
-"      | SHcompact]\n"
-"-abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
+"--abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
 "\t\t\tfile type\n"
-"-shcompact-const-crange\temit code-range descriptors for constants in\n"
+"--shcompact-const-crange  emit code-range descriptors for constants in\n"
 "\t\t\tSHcompact code sections\n"
-"-no-mix\t\t\tdisallow SHmedia code in the same section as\n"
+"--no-mix\t\tdisallow SHmedia code in the same section as\n"
 "\t\t\tconstants and SHcompact code\n"
-"-no-expand\t\tdo not expand MOVI, PT, PTA or PTB instructions\n"
-"-expand-pt32\t\twith -abi=64, expand PT, PTA and PTB instructions\n"
-"\t\t\tto 32 bits only"
+"--no-expand\t\tdo not expand MOVI, PT, PTA or PTB instructions\n"
+"--expand-pt32\t\twith -abi=64, expand PT, PTA and PTB instructions\n"
+"\t\t\tto 32 bits only\n"
 msgstr ""
 
-#: config/tc-sh.c:2823
+#: config/tc-sh.c:3336
 msgid ".uses does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:2842
+#: config/tc-sh.c:3355
 msgid "can't find fixup pointed to by .uses"
 msgstr ""
 
-#: config/tc-sh.c:2865
+#: config/tc-sh.c:3375
 msgid ".uses target does not refer to a local symbol in the same section"
 msgstr ""
 
-#: config/tc-sh.c:2967
+#: config/tc-sh.c:3452
 msgid "displacement overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:2970
+#: config/tc-sh.c:3455
 #, c-format
 msgid "displacement to defined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:2974
+#: config/tc-sh.c:3459
 #, c-format
 msgid "displacement to undefined symbol %s overflows 12-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3052
+#: config/tc-sh.c:3532
 msgid "displacement overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3055
+#: config/tc-sh.c:3535
 #, c-format
 msgid "displacement to defined symbol %s overflows 8-bit field"
 msgstr ""
 
-#: config/tc-sh.c:3059
+#: config/tc-sh.c:3539
 #, c-format
 msgid "displacement to undefined symbol %s overflows 8-bit field "
 msgstr ""
 
-#: config/tc-sh.c:3076
+#: config/tc-sh.c:3556
 #, c-format
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr ""
 
-#: config/tc-sh.c:3151 config/tc-sh.c:3199 config/tc-sparc.c:4192
-#: config/tc-sparc.c:4217
+#: config/tc-sh.c:3622 config/tc-sh.c:3669 config/tc-sparc.c:4234
+#: config/tc-sparc.c:4259
 msgid "misaligned data"
 msgstr ""
 
-#: config/tc-sh.c:3585
+#: config/tc-sh.c:4076
 msgid "misaligned offset"
 msgstr ""
 
-#: config/tc-sparc.c:287
+#: config/tc-sparc.c:288
 msgid "Invalid default architecture, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:291 config/tc-sparc.c:494
+#: config/tc-sparc.c:292 config/tc-sparc.c:495
 msgid "Bad opcode table, broken assembler."
 msgstr ""
 
-#: config/tc-sparc.c:486
+#: config/tc-sparc.c:487
 #, c-format
 msgid "invalid architecture -xarch=%s"
 msgstr ""
 
-#: config/tc-sparc.c:488
+#: config/tc-sparc.c:489
 #, c-format
 msgid "invalid architecture -A%s"
 msgstr ""
 
-#: config/tc-sparc.c:555
+#: config/tc-sparc.c:556
 #, c-format
 msgid "No compiled in support for %d bit object file format"
 msgstr ""
 
-#: config/tc-sparc.c:592
-msgid "Unrecognized option following -K"
-msgstr ""
-
-#: config/tc-sparc.c:633
+#: config/tc-sparc.c:634
+#, c-format
 msgid "SPARC options:\n"
 msgstr ""
 
-#: config/tc-sparc.c:662
+#: config/tc-sparc.c:663
+#, c-format
 msgid ""
 "\n"
 "\t\t\tspecify variant of SPARC architecture\n"
@@ -8370,34 +9098,38 @@ msgid ""
 "-no-relax\t\tavoid changing any jumps and branches\n"
 msgstr ""
 
-#: config/tc-sparc.c:670
+#: config/tc-sparc.c:671
+#, c-format
 msgid "-k\t\t\tgenerate PIC\n"
 msgstr ""
 
-#: config/tc-sparc.c:674
+#: config/tc-sparc.c:675
+#, c-format
 msgid ""
 "-32\t\t\tcreate 32 bit object file\n"
 "-64\t\t\tcreate 64 bit object file\n"
 msgstr ""
 
-#: config/tc-sparc.c:677
+#: config/tc-sparc.c:678
 #, c-format
 msgid "\t\t\t[default is %d]\n"
 msgstr ""
 
-#: config/tc-sparc.c:679
+#: config/tc-sparc.c:680
+#, c-format
 msgid ""
 "-TSO\t\t\tuse Total Store Ordering\n"
 "-PSO\t\t\tuse Partial Store Ordering\n"
 "-RMO\t\t\tuse Relaxed Memory Ordering\n"
 msgstr ""
 
-#: config/tc-sparc.c:683
+#: config/tc-sparc.c:684
 #, c-format
 msgid "\t\t\t[default is %s]\n"
 msgstr ""
 
-#: config/tc-sparc.c:685
+#: config/tc-sparc.c:686
+#, c-format
 msgid ""
 "-KPIC\t\t\tgenerate PIC\n"
 "-V\t\t\tprint assembler version number\n"
@@ -8410,7 +9142,8 @@ msgid ""
 "-s\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-sparc.c:697
+#: config/tc-sparc.c:698
+#, c-format
 msgid ""
 "-EL\t\t\tgenerate code for a little endian machine\n"
 "-EB\t\t\tgenerate code for a big endian machine\n"
@@ -8418,1407 +9151,1173 @@ msgid ""
 "                        instructions and little endian data.\n"
 msgstr ""
 
-#: config/tc-sparc.c:817
+#: config/tc-sparc.c:819
 #, c-format
 msgid "Internal error: losing opcode: `%s' \"%s\"\n"
 msgstr ""
 
-#: config/tc-sparc.c:836
+#: config/tc-sparc.c:838
 #, c-format
 msgid "Internal error: can't find opcode `%s' for `%s'\n"
 msgstr ""
 
-#: config/tc-sparc.c:982
+#: config/tc-sparc.c:984
 msgid "Support for 64-bit arithmetic not compiled in."
 msgstr ""
 
-#: config/tc-sparc.c:1029
+#: config/tc-sparc.c:1031
 msgid "set: number not in 0..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1036
+#: config/tc-sparc.c:1038
 msgid "set: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1096
+#: config/tc-sparc.c:1098
 msgid "setsw: number not in -2147483648..4294967295 range"
 msgstr ""
 
-#: config/tc-sparc.c:1145
+#: config/tc-sparc.c:1147
 msgid "setx: temporary register same as destination register"
 msgstr ""
 
-#: config/tc-sparc.c:1216
+#: config/tc-sparc.c:1218
 msgid "setx: illegal temporary register g0"
 msgstr ""
 
-#: config/tc-sparc.c:1313
+#: config/tc-sparc.c:1316
 msgid "FP branch in delay slot"
 msgstr ""
 
-#: config/tc-sparc.c:1329
+#: config/tc-sparc.c:1331
 msgid "FP branch preceded by FP instruction; NOP inserted"
 msgstr ""
 
-#: config/tc-sparc.c:1369
+#: config/tc-sparc.c:1371
 msgid "failed special case insn sanity check"
 msgstr ""
 
-#: config/tc-sparc.c:1457
+#: config/tc-sparc.c:1461
 msgid ": invalid membar mask name"
 msgstr ""
 
-#: config/tc-sparc.c:1473
+#: config/tc-sparc.c:1477
 msgid ": invalid membar mask expression"
 msgstr ""
 
-#: config/tc-sparc.c:1478
+#: config/tc-sparc.c:1482
 msgid ": invalid membar mask number"
 msgstr ""
 
-#: config/tc-sparc.c:1493
+#: config/tc-sparc.c:1497
 msgid ": invalid siam mode expression"
 msgstr ""
 
-#: config/tc-sparc.c:1498
+#: config/tc-sparc.c:1502
 msgid ": invalid siam mode number"
 msgstr ""
 
-#: config/tc-sparc.c:1514
+#: config/tc-sparc.c:1518
 msgid ": invalid prefetch function name"
 msgstr ""
 
-#: config/tc-sparc.c:1522
+#: config/tc-sparc.c:1526
 msgid ": invalid prefetch function expression"
 msgstr ""
 
-#: config/tc-sparc.c:1527
+#: config/tc-sparc.c:1531
 msgid ": invalid prefetch function number"
 msgstr ""
 
-#: config/tc-sparc.c:1555 config/tc-sparc.c:1567
+#: config/tc-sparc.c:1559 config/tc-sparc.c:1571
 msgid ": unrecognizable privileged register"
 msgstr ""
 
-#: config/tc-sparc.c:1591 config/tc-sparc.c:1616
+#: config/tc-sparc.c:1595 config/tc-sparc.c:1620
 msgid ": unrecognizable v9a or v9b ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1596
+#: config/tc-sparc.c:1600
 msgid ": rd on write only ancillary state register"
 msgstr ""
 
 #. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1604
+#: config/tc-sparc.c:1608
 msgid ": unrecognizable v9a ancillary state register"
 msgstr ""
 
-#: config/tc-sparc.c:1640
+#: config/tc-sparc.c:1644
 msgid ": asr number must be between 16 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1648
+#: config/tc-sparc.c:1652
 msgid ": asr number must be between 0 and 31"
 msgstr ""
 
-#: config/tc-sparc.c:1658
+#: config/tc-sparc.c:1662
+#, c-format
 msgid ": expecting %asrN"
 msgstr ""
 
-#: config/tc-sparc.c:1840 config/tc-sparc.c:1878 config/tc-sparc.c:2279
-#: config/tc-sparc.c:2315
+#: config/tc-sparc.c:1844 config/tc-sparc.c:1882 config/tc-sparc.c:2289
+#: config/tc-sparc.c:2325
 #, c-format
 msgid "Illegal operands: %%%s requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:1846
+#: config/tc-sparc.c:1850
 #, c-format
 msgid ""
 "Illegal operands: %%%s cannot be used together with other relocs in the insn "
 "()"
 msgstr ""
 
-#: config/tc-sparc.c:1857
+#: config/tc-sparc.c:1861
 #, c-format
 msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
 msgstr ""
 
-#: config/tc-sparc.c:2064
+#: config/tc-sparc.c:2068
 msgid "detected global register use not covered by .register pseudo-op"
 msgstr ""
 
-#: config/tc-sparc.c:2135
+#: config/tc-sparc.c:2139
 msgid ": There are only 64 f registers; [0-63]"
 msgstr ""
 
-#: config/tc-sparc.c:2137 config/tc-sparc.c:2149
+#: config/tc-sparc.c:2141 config/tc-sparc.c:2159
 msgid ": There are only 32 f registers; [0-31]"
 msgstr ""
 
-#: config/tc-sparc.c:2327
+#: config/tc-sparc.c:2151
+msgid ": There are only 32 single precision f registers; [0-31]"
+msgstr ""
+
+#: config/tc-sparc.c:2337
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2437
+#: config/tc-sparc.c:2447
 #, c-format
 msgid "Illegal operands: Can't add non-constant expression to %%%s()"
 msgstr ""
 
-#: config/tc-sparc.c:2447
+#: config/tc-sparc.c:2457
 #, c-format
 msgid ""
 "Illegal operands: Can't do arithmetics involving %%%s() of a relocatable "
 "symbol"
 msgstr ""
 
-#: config/tc-sparc.c:2465
+#: config/tc-sparc.c:2475
 msgid ": PC-relative operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2472
+#: config/tc-sparc.c:2482
 msgid ": TLS operand can't be a constant"
 msgstr ""
 
-#: config/tc-sparc.c:2505
+#: config/tc-sparc.c:2515
 msgid ": invalid ASI name"
 msgstr ""
 
-#: config/tc-sparc.c:2513
+#: config/tc-sparc.c:2523
 msgid ": invalid ASI expression"
 msgstr ""
 
-#: config/tc-sparc.c:2518
+#: config/tc-sparc.c:2528
 msgid ": invalid ASI number"
 msgstr ""
 
-#: config/tc-sparc.c:2615
+#: config/tc-sparc.c:2625
 msgid "OPF immediate operand out of range (0-0x1ff)"
 msgstr ""
 
-#: config/tc-sparc.c:2620
+#: config/tc-sparc.c:2630
 msgid "non-immediate OPF operand, ignored"
 msgstr ""
 
-#: config/tc-sparc.c:2639
+#: config/tc-sparc.c:2649
 msgid ": invalid cpreg name"
 msgstr ""
 
-#: config/tc-sparc.c:2668
+#: config/tc-sparc.c:2678
 #, c-format
 msgid "Illegal operands%s"
 msgstr ""
 
-#: config/tc-sparc.c:2702
+#: config/tc-sparc.c:2712
 #, c-format
 msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
 msgstr ""
 
-#: config/tc-sparc.c:2738
+#: config/tc-sparc.c:2748
 #, c-format
 msgid "Architecture mismatch on \"%s\"."
 msgstr ""
 
-#: config/tc-sparc.c:2739
+#: config/tc-sparc.c:2749
 #, c-format
 msgid " (Requires %s; requested architecture is %s.)"
 msgstr ""
 
-#: config/tc-sparc.c:3325
+#: config/tc-sparc.c:3369
 #, c-format
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr ""
 
-#: config/tc-sparc.c:3480
-#, c-format
-msgid "internal error: can't export reloc type %d (`%s')"
+#: config/tc-sparc.c:3679
+msgid "Expected comma after name"
 msgstr ""
 
-#: config/tc-sparc.c:3644
+#: config/tc-sparc.c:3688
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr ""
 
-#: config/tc-sparc.c:3656
+#: config/tc-sparc.c:3700
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr ""
 
-#: config/tc-sparc.c:3673 read.c:2048
+#: config/tc-sparc.c:3717
 msgid "missing alignment"
 msgstr ""
 
-#: config/tc-sparc.c:3684 config/tc-sparc.c:3835
+#: config/tc-sparc.c:3728
 #, c-format
 msgid "alignment too large; assuming %d"
 msgstr ""
 
-#: config/tc-sparc.c:3690 config/tc-sparc.c:3841
+#: config/tc-sparc.c:3734 config/tc-sparc.c:3885
 msgid "negative alignment"
 msgstr ""
 
-#: config/tc-sparc.c:3700 config/tc-sparc.c:3864 read.c:1251 read.c:2064
+#: config/tc-sparc.c:3744 config/tc-sparc.c:3908 read.c:1313 read.c:2143
 msgid "alignment not a power of 2"
 msgstr ""
 
-#: config/tc-sparc.c:3778 config/tc-v850.c:233
+#: config/tc-sparc.c:3822 config/tc-v850.c:223
 msgid "Expected comma after symbol-name"
 msgstr ""
 
-#: config/tc-sparc.c:3788 read.c:1392
+#: config/tc-sparc.c:3832
 #, c-format
 msgid ".COMMon length (%lu) out of range ignored"
 msgstr ""
 
-#: config/tc-sparc.c:3807 config/tc-v850.c:266
+#: config/tc-sparc.c:3865
+msgid "Expected comma after common length"
+msgstr ""
+
+#: config/tc-sparc.c:3879
 #, c-format
-msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
+msgid "alignment too large; assuming %ld"
 msgstr ""
 
-#: config/tc-sparc.c:3821
-msgid "Expected comma after common length"
+#: config/tc-sparc.c:4025
+msgid "Unknown segment type"
 msgstr ""
 
-#: config/tc-sparc.c:4062 config/tc-sparc.c:4072
+#: config/tc-sparc.c:4104 config/tc-sparc.c:4114
 #, c-format
 msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
 msgstr ""
 
-#: config/tc-sparc.c:4090
+#: config/tc-sparc.c:4132
 msgid "redefinition of global register"
 msgstr ""
 
-#: config/tc-sparc.c:4101
+#: config/tc-sparc.c:4143
 #, c-format
 msgid "Register symbol %s already defined."
 msgstr ""
 
-#: config/tc-sparc.c:4310
+#: config/tc-sparc.c:4352
 #, c-format
 msgid "Illegal operands: %%r_plt in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4320
+#: config/tc-sparc.c:4362
 #, c-format
 msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
 msgstr ""
 
-#: config/tc-sparc.c:4357
+#: config/tc-sparc.c:4399
 #, c-format
 msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
 msgstr ""
 
-#: config/tc-sparc.c:4365 config/tc-sparc.c:4396 config/tc-sparc.c:4405
+#: config/tc-sparc.c:4407 config/tc-sparc.c:4438 config/tc-sparc.c:4447
 #, c-format
 msgid "Illegal operands: %%r_%s%d requires arguments in ()"
 msgstr ""
 
-#: config/tc-sparc.c:4414
+#: config/tc-sparc.c:4456
 #, c-format
 msgid "Illegal operands: garbage after %%r_%s%d()"
 msgstr ""
 
-#: config/tc-sparc.h:55
+#: config/tc-sparc.h:46
 msgid "sparc convert_frag\n"
 msgstr ""
 
-#: config/tc-sparc.h:57
+#: config/tc-sparc.h:48
 msgid "estimate_size_before_relax called"
 msgstr ""
 
-#: config/tc-tahoe.c:403
-msgid "The -a option doesn't exist. (Despite what the man page says!"
-msgstr ""
-
-#: config/tc-tahoe.c:407 config/tc-vax.c:3285
-#, c-format
-msgid "Displacement length %s ignored!"
-msgstr ""
-
-#: config/tc-tahoe.c:411 config/tc-vax.c:3277
-msgid "SYMBOL TABLE not implemented"
-msgstr ""
-
-#: config/tc-tahoe.c:415 config/tc-vax.c:3281
-msgid "TOKEN TRACE not implemented"
-msgstr ""
-
-#: config/tc-tahoe.c:419 config/tc-vax.c:3289
-#, c-format
-msgid "I don't need or use temp. file \"%s\"."
-msgstr ""
-
-#: config/tc-tahoe.c:423 config/tc-vax.c:3293
-msgid "I don't use an interpass file! -V ignored"
-msgstr ""
-
-#: config/tc-tahoe.c:437
-msgid ""
-"Tahoe options:\n"
-"-a\t\t\tignored\n"
-"-d LENGTH\t\tignored\n"
-"-J\t\t\tignored\n"
-"-S\t\t\tignored\n"
-"-t FILE\t\t\tignored\n"
-"-T\t\t\tignored\n"
-"-V\t\t\tignored\n"
-msgstr ""
-
-#: config/tc-tahoe.c:1066
-msgid "Casting a branch displacement is bad form, and is ignored."
-msgstr ""
-
-#: config/tc-tahoe.c:1122
-msgid "Couldn't parse the [index] in this operand."
-msgstr ""
-
-#: config/tc-tahoe.c:1128
-msgid "Couldn't find the opening '[' for the index of this operand."
-msgstr ""
-
-#: config/tc-tahoe.c:1168
-msgid "Couldn't find the opening '(' for the deref of this operand."
-msgstr ""
-
-#: config/tc-tahoe.c:1178
-msgid "Operand can't be both pre-inc and post-dec."
-msgstr ""
-
-#: config/tc-tahoe.c:1208
-msgid "I parsed 2 registers in this operand."
-msgstr ""
-
-#: config/tc-tahoe.c:1258
-msgid "Can't relocate expression error."
-msgstr ""
-
-#. This is an error. Tahoe doesn't allow any expressions
-#. bigger that a 32 bit long word. Any bigger has to be referenced
-#. by address.
-#: config/tc-tahoe.c:1265
-msgid "Expression is too large for a 32 bits."
-msgstr ""
-
-#: config/tc-tahoe.c:1270
-msgid "Junk at end of expression."
-msgstr ""
-
-#: config/tc-tahoe.c:1309
-msgid "Syntax error in direct register mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1311
-msgid "You can't index a register in direct register mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1314
-msgid "SP can't be the source operand with direct register addressing."
-msgstr ""
-
-#: config/tc-tahoe.c:1316
-msgid "Can't take the address of a register."
-msgstr ""
-
-#: config/tc-tahoe.c:1318
-msgid "Direct Register can't be used in a branch."
-msgstr ""
-
-#: config/tc-tahoe.c:1320
-msgid "For quad access, the register must be even and < 14."
-msgstr ""
-
-#: config/tc-tahoe.c:1322
-msgid "You can't cast a direct register."
-msgstr ""
-
-#: config/tc-tahoe.c:1328
-msgid "Using reg 14 for quadwords can tromp the FP register."
-msgstr ""
-
-#: config/tc-tahoe.c:1340
-msgid "Syntax error in auto-dec mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1342
-msgid "You can't have an index auto dec mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1344
-msgid "Auto dec mode cant be used for reading."
-msgstr ""
-
-#: config/tc-tahoe.c:1346
-msgid "Auto dec only works of the SP register."
-msgstr ""
-
-#: config/tc-tahoe.c:1348
-msgid "Auto dec can't be used in a branch."
-msgstr ""
-
-#: config/tc-tahoe.c:1350
-msgid "Auto dec won't work with quadwords."
-msgstr ""
-
-#: config/tc-tahoe.c:1357
-msgid "Syntax error in one of the auto-inc modes."
-msgstr ""
-
-#: config/tc-tahoe.c:1363
-msgid "Auto inc deferred only works of the SP register."
-msgstr ""
-
-#: config/tc-tahoe.c:1365
-msgid "You can't have an index auto inc deferred mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1367 config/tc-tahoe.c:1378
-msgid "Auto inc can't be used in a branch."
-msgstr ""
-
-#: config/tc-tahoe.c:1374
-msgid "You can't write to an auto inc register."
-msgstr ""
-
-#: config/tc-tahoe.c:1376
-msgid "Auto inc only works of the SP register."
-msgstr ""
-
-#: config/tc-tahoe.c:1380
-msgid "Auto inc won't work with quadwords."
-msgstr ""
-
-#: config/tc-tahoe.c:1382
-msgid "You can't have an index in auto inc mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1390
-msgid "You can't index the sp register."
-msgstr ""
-
-#: config/tc-tahoe.c:1396
-msgid "Syntax error in register displaced mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1415
-msgid "An offest is needed for this operand."
-msgstr ""
-
-#: config/tc-tahoe.c:1427
-msgid "You can't index a register in immediate mode."
-msgstr ""
-
-#: config/tc-tahoe.c:1429
-msgid "Immediate access can't be used as an address."
-msgstr ""
-
-#: config/tc-tahoe.c:1540
-#, c-format
-msgid "Compiler bug: ODD number of bytes in arg structure %s."
-msgstr ""
-
-#: config/tc-tahoe.c:1567 config/tc-vax.c:1962
-msgid "Not enough operands"
-msgstr ""
-
-#: config/tc-tahoe.c:1577 config/tc-vax.c:1969
-msgid "Too many operands"
-msgstr ""
-
-#: config/tc-tahoe.c:1628 config/tc-vax.c:403
-#, c-format
-msgid "Ignoring statement due to \"%s\""
-msgstr ""
-
-#: config/tc-tahoe.c:1723
-#, c-format
-msgid "Compliler bug: Got a case (%d) I wasn't expecting."
-msgstr ""
-
-#: config/tc-tahoe.c:1817
-msgid "Real branch displacements must be expressions."
-msgstr ""
-
-#: config/tc-tahoe.c:1820
-#, c-format
-msgid "Complier error: I got an unknown synthetic branch :%c"
-msgstr ""
-
-#: config/tc-tahoe.c:1961
-#, c-format
-msgid "Barf, bad mode %x\n"
-msgstr ""
-
 #. Only word (et al.), align, or conditionals are allowed within
 #. .struct/.union.
-#: config/tc-tic54x.c:224
+#: config/tc-tic54x.c:222
 msgid "pseudo-op illegal within .struct/.union"
 msgstr ""
 
-#: config/tc-tic54x.c:349
+#: config/tc-tic54x.c:347
+#, c-format
 msgid "C54x-specific command line  options:\n"
 msgstr ""
 
-#: config/tc-tic54x.c:350
+#: config/tc-tic54x.c:348
+#, c-format
 msgid "-mfar-mode | -mf          Use extended addressing\n"
 msgstr ""
 
-#: config/tc-tic54x.c:351
+#: config/tc-tic54x.c:349
+#, c-format
 msgid "-mcpu=<CPU version>       Specify the CPU version\n"
 msgstr ""
 
-#: config/tc-tic54x.c:353
-msgid "-mcoff-version={0|1|2}    Select COFF version\n"
-msgstr ""
-
-#: config/tc-tic54x.c:355
+#: config/tc-tic54x.c:350
+#, c-format
 msgid "-merrors-to-file <filename>\n"
 msgstr ""
 
-#: config/tc-tic54x.c:356
+#: config/tc-tic54x.c:351
+#, c-format
 msgid "-me <filename>            Redirect errors to a file\n"
 msgstr ""
 
-#: config/tc-tic54x.c:478
+#: config/tc-tic54x.c:473
 msgid "Comma and symbol expected for '.asg STRING, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:532
+#: config/tc-tic54x.c:527
 msgid "Unterminated string after absolute expression"
 msgstr ""
 
-#: config/tc-tic54x.c:540
+#: config/tc-tic54x.c:535
 msgid "Comma and symbol expected for '.eval EXPR, SYMBOL'"
 msgstr ""
 
-#: config/tc-tic54x.c:552
+#: config/tc-tic54x.c:547
 msgid "symbols assigned with .eval must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:810
+#: config/tc-tic54x.c:805
 msgid "Offset on nested structures is ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:861
+#: config/tc-tic54x.c:856
 #, c-format
 msgid ".end%s without preceding .%s"
 msgstr ""
 
-#: config/tc-tic54x.c:928
+#: config/tc-tic54x.c:923
 #, c-format
 msgid "Unrecognized struct/union tag '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:930
+#: config/tc-tic54x.c:925
 msgid ".tag requires a structure tag"
 msgstr ""
 
-#: config/tc-tic54x.c:936
+#: config/tc-tic54x.c:931
 msgid "Label required for .tag"
 msgstr ""
 
-#: config/tc-tic54x.c:955
+#: config/tc-tic54x.c:950
 #, c-format
 msgid ".tag target '%s' undefined"
 msgstr ""
 
-#: config/tc-tic54x.c:1018
+#: config/tc-tic54x.c:1013
 #, c-format
 msgid ".field count '%d' out of range (1 <= X <= 32)"
 msgstr ""
 
-#: config/tc-tic54x.c:1046
+#: config/tc-tic54x.c:1041
 #, c-format
 msgid "Unrecognized field type '%c'"
 msgstr ""
 
 #. Disallow .byte with a non constant expression that will
 #. require relocation.
-#: config/tc-tic54x.c:1183
+#: config/tc-tic54x.c:1178
 msgid "Relocatable values require at least WORD storage"
 msgstr ""
 
-#: config/tc-tic54x.c:1245
+#: config/tc-tic54x.c:1240
 msgid "Use of .def/.ref is deprecated.  Use .global instead"
 msgstr ""
 
-#: config/tc-tic54x.c:1444
+#: config/tc-tic54x.c:1439
 msgid ".space/.bes repeat count is negative, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1449
+#: config/tc-tic54x.c:1444
 msgid ".space/.bes repeat count is zero, ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1527
+#: config/tc-tic54x.c:1522
 msgid "Missing size argument"
 msgstr ""
 
-#: config/tc-tic54x.c:1664
+#: config/tc-tic54x.c:1659
 msgid "CPU version has already been set"
 msgstr ""
 
-#: config/tc-tic54x.c:1668
+#: config/tc-tic54x.c:1663
 #, c-format
 msgid "Unrecognized version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:1674
+#: config/tc-tic54x.c:1669
 msgid "Changing of CPU version on the fly not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:1810
+#: config/tc-tic54x.c:1805
 msgid "p2align not supported on this target"
 msgstr ""
 
-#: config/tc-tic54x.c:1823
+#: config/tc-tic54x.c:1818
 msgid "Argument to .even ignored"
 msgstr ""
 
-#: config/tc-tic54x.c:1870
+#: config/tc-tic54x.c:1865
 msgid "Invalid field size, must be from 1 to 32"
 msgstr ""
 
-#: config/tc-tic54x.c:1883
+#: config/tc-tic54x.c:1878
 msgid "field size must be 16 when value is relocatable"
 msgstr ""
 
-#: config/tc-tic54x.c:1898
+#: config/tc-tic54x.c:1893
 msgid "field value truncated"
 msgstr ""
 
-#: config/tc-tic54x.c:2007 config/tc-tic54x.c:2324
+#: config/tc-tic54x.c:2002 config/tc-tic54x.c:2319
 #, c-format
 msgid "Unrecognized section '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2016
+#: config/tc-tic54x.c:2011
 msgid "Current section is unitialized, section name required for .clink"
 msgstr ""
 
-#: config/tc-tic54x.c:2230
+#: config/tc-tic54x.c:2225
 msgid "ENDLOOP without corresponding LOOP"
 msgstr ""
 
-#: config/tc-tic54x.c:2274
+#: config/tc-tic54x.c:2269
 msgid "Mixing of normal and extended addressing not supported"
 msgstr ""
 
-#: config/tc-tic54x.c:2280
+#: config/tc-tic54x.c:2275
 msgid "Extended addressing not supported on the specified CPU"
 msgstr ""
 
-#: config/tc-tic54x.c:2330
+#: config/tc-tic54x.c:2325
 msgid ".sblock may be used for initialized sections only"
 msgstr ""
 
-#: config/tc-tic54x.c:2361
+#: config/tc-tic54x.c:2356
 msgid "Symbol missing for .set/.equ"
 msgstr ""
 
-#: config/tc-tic54x.c:2420
+#: config/tc-tic54x.c:2415
 msgid ".var may only be used within a macro definition"
 msgstr ""
 
-#: config/tc-tic54x.c:2428
+#: config/tc-tic54x.c:2423
 msgid "Substitution symbols must begin with a letter"
 msgstr ""
 
-#: config/tc-tic54x.c:2522
+#: config/tc-tic54x.c:2517
 #, c-format
 msgid "Can't open macro library file '%s' for reading."
 msgstr ""
 
-#: config/tc-tic54x.c:2529
+#: config/tc-tic54x.c:2524
 #, c-format
 msgid "File '%s' not in macro archive format"
 msgstr ""
 
-#: config/tc-tic54x.c:2689
+#: config/tc-tic54x.c:2656
 #, c-format
 msgid "Bad COFF version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2698
+#: config/tc-tic54x.c:2665
 #, c-format
 msgid "Bad CPU version '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2711 config/tc-tic54x.c:2714
+#: config/tc-tic54x.c:2678 config/tc-tic54x.c:2681
 #, c-format
 msgid "Can't redirect stderr to the file '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:2861
+#: config/tc-tic54x.c:2809
 #, c-format
 msgid "Undefined substitution symbol '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3518
+#: config/tc-tic54x.c:3466
 msgid "Badly formed address expression"
 msgstr ""
 
-#: config/tc-tic54x.c:3782
+#: config/tc-tic54x.c:3730
 #, c-format
 msgid "Invalid dmad syntax '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3848
+#: config/tc-tic54x.c:3796
 #, c-format
 msgid ""
 "Use the .mmregs directive to use memory-mapped register names such as '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:3901
+#: config/tc-tic54x.c:3849
 msgid "Address mode *+ARx is write-only. Results of reading are undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:3921
+#: config/tc-tic54x.c:3869
 #, c-format
 msgid "Unrecognized indirect address format \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:3960
+#: config/tc-tic54x.c:3908
 #, c-format
 msgid "Operand '%s' out of range (%d <= x <= %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:3980
+#: config/tc-tic54x.c:3928
 msgid "Error in relocation handling"
 msgstr ""
 
-#: config/tc-tic54x.c:4001 config/tc-tic54x.c:4065 config/tc-tic54x.c:4097
+#: config/tc-tic54x.c:3949 config/tc-tic54x.c:4013 config/tc-tic54x.c:4045
 #, c-format
 msgid "Unrecognized condition code \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4018
+#: config/tc-tic54x.c:3966
 #, c-format
 msgid "Condition \"%s\" does not match preceding group"
 msgstr ""
 
-#: config/tc-tic54x.c:4026
+#: config/tc-tic54x.c:3974
 #, c-format
 msgid ""
 "Condition \"%s\" uses a different accumulator from a preceding condition"
 msgstr ""
 
-#: config/tc-tic54x.c:4033
+#: config/tc-tic54x.c:3981
 msgid "Only one comparison conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:4038
+#: config/tc-tic54x.c:3986
 msgid "Only one overflow conditional allowed"
 msgstr ""
 
-#: config/tc-tic54x.c:4046
+#: config/tc-tic54x.c:3994
 #, c-format
 msgid "Duplicate %s conditional"
 msgstr ""
 
-#: config/tc-tic54x.c:4081
+#: config/tc-tic54x.c:4029
 msgid "Invalid auxiliary register (use AR0-AR7)"
 msgstr ""
 
-#: config/tc-tic54x.c:4117
+#: config/tc-tic54x.c:4065
 msgid "lk addressing modes are invalid for memory-mapped register addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:4125
+#: config/tc-tic54x.c:4073
 msgid ""
 "Address mode *+ARx is not allowed in memory-mapped register addressing.  "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:4151
+#: config/tc-tic54x.c:4099
 msgid ""
 "Destination accumulator for each part of this parallel instruction must be "
 "different"
 msgstr ""
 
-#: config/tc-tic54x.c:4200
+#: config/tc-tic54x.c:4148
 #, c-format
 msgid "Memory mapped register \"%s\" out of range"
 msgstr ""
 
-#: config/tc-tic54x.c:4239
+#: config/tc-tic54x.c:4187
 msgid "Invalid operand (use 1, 2, or 3)"
 msgstr ""
 
-#: config/tc-tic54x.c:4264
+#: config/tc-tic54x.c:4212
 msgid "A status register or status bit name is required"
 msgstr ""
 
-#: config/tc-tic54x.c:4274
+#: config/tc-tic54x.c:4222
 #, c-format
 msgid "Unrecognized status bit \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4297
+#: config/tc-tic54x.c:4245
 #, c-format
 msgid "Invalid status register \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4309
+#: config/tc-tic54x.c:4257
 #, c-format
 msgid "Operand \"%s\" out of range (use 1 or 2)"
 msgstr ""
 
-#: config/tc-tic54x.c:4517
+#: config/tc-tic54x.c:4465
 #, c-format
 msgid "Unrecognized instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4546
+#: config/tc-tic54x.c:4494
 #, c-format
 msgid "Unrecognized operand list '%s' for instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4578
+#: config/tc-tic54x.c:4526
 #, c-format
 msgid "Unrecognized parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4629
+#: config/tc-tic54x.c:4577
 #, c-format
 msgid "Invalid operand (s) for parallel instruction \"%s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4632
+#: config/tc-tic54x.c:4580
 #, c-format
 msgid "Unrecognized parallel instruction combination \"%s || %s\""
 msgstr ""
 
-#: config/tc-tic54x.c:4869
+#: config/tc-tic54x.c:4817
 #, c-format
 msgid "%s symbol recursion stopped at second appearance of '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:4909
+#: config/tc-tic54x.c:4857
 msgid "Unrecognized substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4914
+#: config/tc-tic54x.c:4862
 msgid "Missing '(' after substitution symbol function"
 msgstr ""
 
-#: config/tc-tic54x.c:4928
+#: config/tc-tic54x.c:4876
 msgid "Expecting second argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4941 config/tc-tic54x.c:4991
+#: config/tc-tic54x.c:4889 config/tc-tic54x.c:4939
 msgid "Extra junk in function call, expecting ')'"
 msgstr ""
 
-#: config/tc-tic54x.c:4967
+#: config/tc-tic54x.c:4915
 msgid "Function expects two arguments"
 msgstr ""
 
-#: config/tc-tic54x.c:4980
+#: config/tc-tic54x.c:4928
 msgid "Expecting character constant argument"
 msgstr ""
 
-#: config/tc-tic54x.c:4986
+#: config/tc-tic54x.c:4934
 msgid "Both arguments must be substitution symbols"
 msgstr ""
 
-#: config/tc-tic54x.c:5039
+#: config/tc-tic54x.c:4987
 #, c-format
 msgid "Invalid subscript (use 1 to %d)"
 msgstr ""
 
-#: config/tc-tic54x.c:5049
+#: config/tc-tic54x.c:4997
 #, c-format
 msgid "Invalid length (use 0 to %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5059
+#: config/tc-tic54x.c:5007
 msgid "Missing ')' in subscripted substitution symbol expression"
 msgstr ""
 
-#: config/tc-tic54x.c:5079
+#: config/tc-tic54x.c:5027
 msgid "Missing forced substitution terminator ':'"
 msgstr ""
 
-#: config/tc-tic54x.c:5252
+#: config/tc-tic54x.c:5182
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left)"
 msgstr ""
 
-#: config/tc-tic54x.c:5293
+#: config/tc-tic54x.c:5223
 #, c-format
 msgid "Unrecognized parallel instruction '%s'"
 msgstr ""
 
-#: config/tc-tic54x.c:5305
+#: config/tc-tic54x.c:5235
 #, c-format
 msgid "Instruction '%s' requires an LP cpu version"
 msgstr ""
 
-#: config/tc-tic54x.c:5312
+#: config/tc-tic54x.c:5242
 #, c-format
 msgid "Instruction '%s' requires far mode addressing"
 msgstr ""
 
-#: config/tc-tic54x.c:5324
+#: config/tc-tic54x.c:5254
 #, c-format
 msgid ""
 "Instruction does not fit in available delay slots (%d-word insn, %d slots "
 "left). Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5334
+#: config/tc-tic54x.c:5264
 msgid ""
 "Instructions which cause PC discontinuity are not allowed in a delay slot. "
 "Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5345
+#: config/tc-tic54x.c:5275
 #, c-format
 msgid "'%s' is not repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5349
+#: config/tc-tic54x.c:5279
 msgid ""
 "Instructions using long offset modifiers or absolute addresses are not "
 "repeatable. Resulting behavior is undefined."
 msgstr ""
 
-#: config/tc-tic54x.c:5545
+#: config/tc-tic54x.c:5459
 #, c-format
 msgid "Unsupported relocation size %d"
 msgstr ""
 
-#: config/tc-tic54x.c:5699
+#: config/tc-tic54x.c:5602
 msgid "non-absolute value used with .space/.bes"
 msgstr ""
 
-#: config/tc-tic54x.c:5703
+#: config/tc-tic54x.c:5606
 #, c-format
 msgid "negative value ignored in %s"
 msgstr ""
 
-#: config/tc-tic54x.c:5792
+#: config/tc-tic54x.c:5695
 #, c-format
 msgid "attempt to .space/.bes backwards? (%ld)"
 msgstr ""
 
-#: config/tc-tic54x.c:5826
+#: config/tc-tic54x.c:5729
 #, c-format
 msgid "Invalid label '%s'"
 msgstr ""
 
-#: config/tc-tic80.c:26
-#, c-format
-msgid "internal error:%s:%d: %s\n"
-msgstr ""
-
-#: config/tc-tic80.c:29
-#, c-format
-msgid "internal error:%s:%d: %s %ld\n"
-msgstr ""
-
-#: config/tc-tic80.c:89
-msgid "Relaxation is a luxury we can't afford"
-msgstr ""
-
-#: config/tc-tic80.c:138
-msgid "bad call to md_atof ()"
-msgstr ""
-
-#: config/tc-tic80.c:235
-msgid "':' not followed by 'm' or 's'"
-msgstr ""
-
-#: config/tc-tic80.c:248
-msgid "paren nesting"
-msgstr ""
-
-#: config/tc-tic80.c:262
-msgid "mismatched parenthesis"
-msgstr ""
-
-#: config/tc-tic80.c:464
-msgid "unhandled expression type"
-msgstr ""
-
-#: config/tc-tic80.c:678
-msgid "symbol reloc that is not PC relative or 32 bits"
-msgstr ""
-
-#: config/tc-tic80.c:707
-msgid "unhandled operand modifier"
-msgstr ""
-
-#: config/tc-tic80.c:749
-msgid "unhandled expression"
-msgstr ""
-
-#: config/tc-tic80.c:797
-#, c-format
-msgid "Invalid mnemonic: '%s'"
-msgstr ""
-
-#: config/tc-tic80.c:810
-#, c-format
-msgid "Invalid operands: '%s'"
-msgstr ""
-
-#: config/tc-tic80.c:888
-msgid "unhandled predefined symbol bits"
-msgstr ""
-
-#: config/tc-tic80.c:983
+#: config/tc-v850.c:234
 #, c-format
-msgid "PC offset 0x%lx outside range 0x%lx-0x%lx"
-msgstr ""
-
-#: config/tc-tic80.c:998
-msgid "unhandled relocation type in fixup"
-msgstr ""
-
-#: config/tc-tic80.c:1037
-msgid "md_convert_frag() not implemented yet"
+msgid ".COMMon length (%d.) < 0! Ignored."
 msgstr ""
 
-#: config/tc-v850.c:244
+#: config/tc-v850.c:255
 #, c-format
-msgid ".COMMon length (%d.) < 0! Ignored."
+msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
 msgstr ""
 
-#: config/tc-v850.c:293
+#: config/tc-v850.c:281
 msgid "Common alignment negative; 0 assumed"
 msgstr ""
 
-#: config/tc-v850.c:974
+#: config/tc-v850.c:939
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr ""
 
-#: config/tc-v850.c:975
+#: config/tc-v850.c:940
 msgid "internal failure in parse_register_list"
 msgstr ""
 
-#: config/tc-v850.c:991
+#: config/tc-v850.c:956
 msgid "constant expression or register list expected"
 msgstr ""
 
-#: config/tc-v850.c:996 config/tc-v850.c:1009 config/tc-v850.c:1028
+#: config/tc-v850.c:961 config/tc-v850.c:974 config/tc-v850.c:993
 msgid "high bits set in register list expression"
 msgstr ""
 
-#: config/tc-v850.c:1067 config/tc-v850.c:1130
+#: config/tc-v850.c:1032 config/tc-v850.c:1095
 msgid "illegal register included in list"
 msgstr ""
 
-#: config/tc-v850.c:1073
+#: config/tc-v850.c:1038
 msgid "system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1078
+#: config/tc-v850.c:1043
 msgid "PSW cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1085
+#: config/tc-v850.c:1050
 msgid "High value system registers cannot be included in list"
 msgstr ""
 
-#: config/tc-v850.c:1109
+#: config/tc-v850.c:1074
 msgid "second register should follow dash in register list"
 msgstr ""
 
-#: config/tc-v850.c:1154
+#: config/tc-v850.c:1119
+#, c-format
 msgid " V850 options:\n"
 msgstr ""
 
-#: config/tc-v850.c:1155
+#: config/tc-v850.c:1120
+#, c-format
 msgid "  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1156
+#: config/tc-v850.c:1121
+#, c-format
 msgid ""
 "  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"
 msgstr ""
 
-#: config/tc-v850.c:1157
+#: config/tc-v850.c:1122
+#, c-format
 msgid "  -mv850                    The code is targeted at the v850\n"
 msgstr ""
 
-#: config/tc-v850.c:1158
+#: config/tc-v850.c:1123
+#, c-format
 msgid "  -mv850e                   The code is targeted at the v850e\n"
 msgstr ""
 
-#: config/tc-v850.c:1159
+#: config/tc-v850.c:1124
+#, c-format
+msgid "  -mv850e1                  The code is targeted at the v850e1\n"
+msgstr ""
+
+#: config/tc-v850.c:1125
+#, c-format
 msgid ""
 "  -mv850any                 The code is generic, despite any processor "
 "specific instructions\n"
 msgstr ""
 
-#: config/tc-v850.c:1160
+#: config/tc-v850.c:1126
+#, c-format
 msgid "  -mrelax                   Enable relaxation\n"
 msgstr ""
 
-#: config/tc-v850.c:1172 config/tc-v850.c:1207
+#: config/tc-v850.c:1308
 #, c-format
-msgid "unknown command line option: -%c%s\n"
+msgid "Unable to determine default target processor from string: %s"
 msgstr ""
 
-#: config/tc-v850.c:1348
-#, c-format
-msgid "Unable to determine default target processor from string: %s"
+#: config/tc-v850.c:1343
+msgid "lo() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1385
+#: config/tc-v850.c:1360
 msgid "ctoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1411
+#: config/tc-v850.c:1382
 msgid "sdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1437
+#: config/tc-v850.c:1404
 msgid "zdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1474
+#: config/tc-v850.c:1437
 msgid "tdaoff() relocation used on an instruction which does not support it"
 msgstr ""
 
-#: config/tc-v850.c:1698
+#: config/tc-v850.c:1642
 msgid "Target processor does not support this instruction."
 msgstr ""
 
-#: config/tc-v850.c:1788 config/tc-v850.c:1817 config/tc-v850.c:2005
+#: config/tc-v850.c:1731 config/tc-v850.c:1760 config/tc-v850.c:1940
 msgid "immediate operand is too large"
 msgstr ""
 
-#: config/tc-v850.c:1799
+#: config/tc-v850.c:1742
 msgid "AAARG -> unhandled constant reloc"
 msgstr ""
 
-#: config/tc-v850.c:1843
+#: config/tc-v850.c:1785
 msgid "invalid register name"
 msgstr ""
 
-#: config/tc-v850.c:1848
+#: config/tc-v850.c:1789
 msgid "register r0 cannot be used here"
 msgstr ""
 
-#: config/tc-v850.c:1860
+#: config/tc-v850.c:1800
 msgid "invalid system register name"
 msgstr ""
 
-#: config/tc-v850.c:1873
+#: config/tc-v850.c:1812
 msgid "expected EP register"
 msgstr ""
 
-#: config/tc-v850.c:1890
+#: config/tc-v850.c:1828
 msgid "invalid condition code name"
 msgstr ""
 
-#: config/tc-v850.c:1911 config/tc-v850.c:1915
+#: config/tc-v850.c:1848 config/tc-v850.c:1852
 msgid "constant too big to fit into instruction"
 msgstr ""
 
-#: config/tc-v850.c:1968
+#: config/tc-v850.c:1905
 msgid "syntax error: value is missing before the register name"
 msgstr ""
 
-#: config/tc-v850.c:1970
+#: config/tc-v850.c:1907
 msgid "syntax error: register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1984
+#: config/tc-v850.c:1920
 msgid "syntax error: system register not expected"
 msgstr ""
 
-#: config/tc-v850.c:1989
+#: config/tc-v850.c:1924
 msgid "syntax error: condition code not expected"
 msgstr ""
 
-#: config/tc-v850.c:2030
+#: config/tc-v850.c:1958
 msgid "invalid operand"
 msgstr ""
 
-#: config/tc-vax.c:285
+#: config/tc-vax.c:290
 #, c-format
 msgid "VIP_BEGIN error:%s"
 msgstr ""
 
-#: config/tc-vax.c:422
+#: config/tc-vax.c:461
+#, c-format
+msgid "Ignoring statement due to \"%s\""
+msgstr ""
+
+#: config/tc-vax.c:480
 #, c-format
 msgid "Aborting because statement has \"%s\""
 msgstr ""
 
-#: config/tc-vax.c:469
+#: config/tc-vax.c:527
 msgid "Can't relocate expression"
 msgstr ""
 
-#: config/tc-vax.c:572
+#: config/tc-vax.c:630
 msgid "Bignum not permitted in short literal. Immediate mode assumed."
 msgstr ""
 
-#: config/tc-vax.c:581
+#: config/tc-vax.c:639
 msgid "Can't do flonum short literal: immediate mode used."
 msgstr ""
 
-#: config/tc-vax.c:626
+#: config/tc-vax.c:684
 #, c-format
 msgid "A bignum/flonum may not be a displacement: 0x%lx used"
 msgstr ""
 
-#: config/tc-vax.c:961
+#: config/tc-vax.c:1007
 #, c-format
 msgid "Short literal overflow(%ld.), immediate mode assumed."
 msgstr ""
 
-#: config/tc-vax.c:970
+#: config/tc-vax.c:1016
 #, c-format
 msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
 msgstr ""
 
-#: config/tc-vax.c:1035
+#: config/tc-vax.c:1081
 msgid "Length specification ignored. Address mode 9F used"
 msgstr ""
 
-#: config/tc-vax.c:1096
+#: config/tc-vax.c:1142
 msgid "Invalid operand:  immediate value used as base address."
 msgstr ""
 
-#: config/tc-vax.c:1098
+#: config/tc-vax.c:1144
 msgid "Invalid operand:  immediate value used as address."
 msgstr ""
 
-#: config/tc-vax.c:1123
+#: config/tc-vax.c:1169
 msgid "Symbol used as immediate operand in PIC mode."
 msgstr ""
 
-#: config/tc-vax.c:1941
+#: config/tc-vax.c:1942
 msgid "odd number of bytes in operand description"
 msgstr ""
 
-#: config/tc-vax.c:1957
+#: config/tc-vax.c:1958
 msgid "Bad operand"
 msgstr ""
 
-#: config/tc-vax.c:2532
+#: config/tc-vax.c:1963
+msgid "Not enough operands"
+msgstr ""
+
+#: config/tc-vax.c:1970
+msgid "Too many operands"
+msgstr ""
+
+#: config/tc-vax.c:2533
 msgid "no '[' to match ']'"
 msgstr ""
 
-#: config/tc-vax.c:2552
+#: config/tc-vax.c:2553
 msgid "bad register in []"
 msgstr ""
 
-#: config/tc-vax.c:2554
+#: config/tc-vax.c:2555
 msgid "[PC] index banned"
 msgstr ""
 
-#: config/tc-vax.c:2589
+#: config/tc-vax.c:2590
 msgid "no '(' to match ')'"
 msgstr ""
 
-#: config/tc-vax.c:2729
+#: config/tc-vax.c:2730
 msgid "invalid branch operand"
 msgstr ""
 
-#: config/tc-vax.c:2758
+#: config/tc-vax.c:2759
 msgid "address prohibits @"
 msgstr ""
 
-#: config/tc-vax.c:2760
+#: config/tc-vax.c:2761
 msgid "address prohibits #"
 msgstr ""
 
-#: config/tc-vax.c:2764
+#: config/tc-vax.c:2765
 msgid "address prohibits -()"
 msgstr ""
 
-#: config/tc-vax.c:2766
+#: config/tc-vax.c:2767
 msgid "address prohibits ()+"
 msgstr ""
 
-#: config/tc-vax.c:2769
+#: config/tc-vax.c:2770
 msgid "address prohibits ()"
 msgstr ""
 
-#: config/tc-vax.c:2771
+#: config/tc-vax.c:2772
 msgid "address prohibits []"
 msgstr ""
 
-#: config/tc-vax.c:2773
+#: config/tc-vax.c:2774
 msgid "address prohibits register"
 msgstr ""
 
-#: config/tc-vax.c:2775
+#: config/tc-vax.c:2776
 msgid "address prohibits displacement length specifier"
 msgstr ""
 
-#: config/tc-vax.c:2805
+#: config/tc-vax.c:2806
 msgid "invalid operand of S^#"
 msgstr ""
 
-#: config/tc-vax.c:2822
+#: config/tc-vax.c:2823
 msgid "S^# needs expression"
 msgstr ""
 
-#: config/tc-vax.c:2829
+#: config/tc-vax.c:2830
 msgid "S^# may only read-access"
 msgstr ""
 
-#: config/tc-vax.c:2854
+#: config/tc-vax.c:2855
 msgid "invalid operand of -()"
 msgstr ""
 
-#: config/tc-vax.c:2860
+#: config/tc-vax.c:2861
 msgid "-(PC) unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2862
+#: config/tc-vax.c:2863
 msgid "[]index same as -()register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2898
+#: config/tc-vax.c:2899
 msgid "invalid operand of ()+"
 msgstr ""
 
-#: config/tc-vax.c:2904
+#: config/tc-vax.c:2905
 msgid "(PC)+ unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2906
+#: config/tc-vax.c:2907
 msgid "[]index same as ()+register: unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2931
+#: config/tc-vax.c:2932
 msgid "# conflicts length"
 msgstr ""
 
-#: config/tc-vax.c:2933
+#: config/tc-vax.c:2934
 msgid "# bars register"
 msgstr ""
 
-#: config/tc-vax.c:2955
+#: config/tc-vax.c:2956
 msgid "writing or modifying # is unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:2985
+#: config/tc-vax.c:2986
 msgid "length not needed"
 msgstr ""
 
-#: config/tc-vax.c:2992
+#: config/tc-vax.c:2993
 msgid "can't []index a register, because it has no address"
 msgstr ""
 
-#: config/tc-vax.c:2994
+#: config/tc-vax.c:2995
 msgid "a register has no address"
 msgstr ""
 
-#: config/tc-vax.c:3005
+#: config/tc-vax.c:3006
 msgid "PC part of operand unpredictable"
 msgstr ""
 
-#: config/tc-vax.c:3345
+#: config/tc-vax.c:3281
+msgid "SYMBOL TABLE not implemented"
+msgstr ""
+
+#: config/tc-vax.c:3285
+msgid "TOKEN TRACE not implemented"
+msgstr ""
+
+#: config/tc-vax.c:3289
+#, c-format
+msgid "Displacement length %s ignored!"
+msgstr ""
+
+#: config/tc-vax.c:3293
+#, c-format
+msgid "I don't need or use temp. file \"%s\"."
+msgstr ""
+
+#: config/tc-vax.c:3297
+msgid "I don't use an interpass file! -V ignored"
+msgstr ""
+
+#: config/tc-vax.c:3354
+#, c-format
 msgid ""
 "VAX options:\n"
 "-d LENGTH\t\tignored\n"
@@ -9829,7 +10328,8 @@ msgid ""
 "-V\t\t\tignored\n"
 msgstr ""
 
-#: config/tc-vax.c:3354
+#: config/tc-vax.c:3363
+#, c-format
 msgid ""
 "VMS options:\n"
 "-+\t\t\thash encode names longer than 31 characters\n"
@@ -9840,537 +10340,726 @@ msgid ""
 "-v\"VERSION\"\t\tcode being assembled was produced by compiler \"VERSION\"\n"
 msgstr ""
 
-#: config/tc-w65.c:145
-msgid "need on or off."
+#: config/tc-xstormy16.c:78
+#, c-format
+msgid " XSTORMY16 specific command line options:\n"
 msgstr ""
 
-#: config/tc-w65.c:281 config/tc-w65.c:324
-msgid "syntax error after <exp"
+#: config/tc-xstormy16.c:563
+#, c-format
+msgid "internal error: can't install fix for reloc type %d (`%s')"
 msgstr ""
 
-#: config/tc-xstormy16.c:80
-msgid " XSTORMY16 specific command line options:\n"
+#: config/tc-xtensa.c:590
+msgid "illegal range of target hardware versions"
 msgstr ""
 
-#: config/tc-xstormy16.c:562
-#, c-format
-msgid "internal error: can't install fix for reloc type %d (`%s')"
+#: config/tc-xtensa.c:738
+msgid "--density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:929
-msgid "'--density' option not supported in this Xtensa configuration"
+#: config/tc-xtensa.c:741
+msgid "--no-density option is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1030
-msgid ""
-"'--literal-section-name' is deprecated; use '--rename-section ."
-"literal=NEWNAME'"
+#: config/tc-xtensa.c:750
+msgid "--generics is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1036
-msgid ""
-"'--text-section-name' is deprecated; use '--rename-section .text=NEWNAME'"
+#: config/tc-xtensa.c:753
+msgid "--no-generics is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1042
-msgid ""
-"'--data-section-name' is deprecated; use '--rename-section .data=NEWNAME'"
+#: config/tc-xtensa.c:756
+msgid "--relax is deprecated; use --transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1048
-msgid "'--bss-section-name' is deprecated; use '--rename-section .bss=NEWNAME'"
+#: config/tc-xtensa.c:759
+msgid "--no-relax is deprecated; use --no-transform instead"
 msgstr ""
 
-#: config/tc-xtensa.c:1186
+#: config/tc-xtensa.c:776
+msgid "--absolute-literals option not supported in this Xtensa configuration"
+msgstr ""
+
+#: config/tc-xtensa.c:849
+msgid "prefer-l32r conflicts with prefer-const16"
+msgstr ""
+
+#: config/tc-xtensa.c:855
+msgid "prefer-const16 conflicts with prefer-l32r"
+msgstr ""
+
+#: config/tc-xtensa.c:863 config/tc-xtensa.c:872 config/tc-xtensa.c:876
+msgid "invalid target hardware version"
+msgstr ""
+
+#: config/tc-xtensa.c:1078
 msgid "unmatched end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1215
+#: config/tc-xtensa.c:1107
 msgid ".begin directive with no matching .end directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1259
+#: config/tc-xtensa.c:1148
+msgid "[no-]generics is deprecated; use [no-]transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:1153
+msgid "[no-]relax is deprecated; use [no-]transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:1166
 #, c-format
-msgid "directive %s can't be negated"
+msgid "directive %s cannot be negated"
 msgstr ""
 
-#: config/tc-xtensa.c:1265
+#: config/tc-xtensa.c:1172
 msgid "unknown directive"
 msgstr ""
 
-#: config/tc-xtensa.c:1300
+#: config/tc-xtensa.c:1194 config/tc-xtensa.c:1300 config/tc-xtensa.c:1573
+#: config/tc-xtensa.c:5496
+msgid "directives are not valid inside bundles"
+msgstr ""
+
+#: config/tc-xtensa.c:1206
+msgid ".begin literal is deprecated; use .literal instead"
+msgstr ""
+
+#: config/tc-xtensa.c:1220
 msgid "cannot set literal_prefix inside literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:1337 config/tc-xtensa.c:1371
-msgid "Xtensa density option not supported; ignored"
+#: config/tc-xtensa.c:1263
+msgid ".begin [no-]density is ignored"
+msgstr ""
+
+#: config/tc-xtensa.c:1270 config/tc-xtensa.c:1320
+msgid "Xtensa absolute literals option not supported; ignored"
+msgstr ""
+
+#: config/tc-xtensa.c:1313
+msgid ".end [no-]density is ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1383
+#: config/tc-xtensa.c:1338
 #, c-format
 msgid "does not match begin %s%s at %s:%d"
 msgstr ""
 
-#: config/tc-xtensa.c:1429
+#: config/tc-xtensa.c:1393
 msgid ".literal_position inside literal directive; ignoring"
 msgstr ""
 
-#: config/tc-xtensa.c:1480
+#: config/tc-xtensa.c:1413
+msgid ".literal not allowed inside .begin literal region"
+msgstr ""
+
+#: config/tc-xtensa.c:1449
 msgid "expected comma or colon after symbol name; rest of line ignored"
 msgstr ""
 
-#: config/tc-xtensa.c:1655 config/tc-xtensa.c:1672
+#: config/tc-xtensa.c:1542
+msgid "fall through frequency must be greater than 0"
+msgstr ""
+
+#: config/tc-xtensa.c:1550
+msgid "branch target frequency must be greater than 0"
+msgstr ""
+
+#: config/tc-xtensa.c:1598
+#, c-format
+msgid "opcode-specific %s relocation used outside an instruction"
+msgstr ""
+
+#: config/tc-xtensa.c:1751 config/tc-xtensa.c:1768
 #, c-format
 msgid "bad register name: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1661
+#: config/tc-xtensa.c:1757
 #, c-format
 msgid "bad register number: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:1724
+#: config/tc-xtensa.c:1836
 msgid "register number out of range"
 msgstr ""
 
-#: config/tc-xtensa.c:1836
-msgid "too many arguments"
+#: config/tc-xtensa.c:1920
+msgid "extra comma"
 msgstr ""
 
 #: config/tc-xtensa.c:1922
+msgid "extra colon"
+msgstr ""
+
+#: config/tc-xtensa.c:1924
+msgid "missing argument"
+msgstr ""
+
+#: config/tc-xtensa.c:1926
+msgid "missing comma or colon"
+msgstr ""
+
+#: config/tc-xtensa.c:1983
+msgid "incorrect register number, ignoring"
+msgstr ""
+
+#: config/tc-xtensa.c:1990
+msgid "too many arguments"
+msgstr ""
+
+#: config/tc-xtensa.c:2063
 #, c-format
-msgid "not enough operands (%d) for '%s'; expected %d"
+msgid "cannot encode opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:1929
+#: config/tc-xtensa.c:2157
 #, c-format
-msgid "too many operands (%d) for '%s'; expected %d"
+msgid "not enough operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:1973
+#: config/tc-xtensa.c:2164
 #, c-format
-msgid "register number for `%s' is not a constant"
+msgid "too many operands (%d) for '%s'; expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:1978
+#: config/tc-xtensa.c:2219
 #, c-format
-msgid "register number (%ld) for `%s' is out of range"
+msgid "invalid register '%s' for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2464
+#: config/tc-xtensa.c:2226
 #, c-format
-msgid "operand %d not properly aligned for '%s'"
+msgid "invalid register number (%ld) for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:2469
+#: config/tc-xtensa.c:2295
 #, c-format
-msgid "operand %d not in immediate table for '%s'"
+msgid "invalid register number (%ld) for '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:2474
+#: config/tc-xtensa.c:2685
 #, c-format
-msgid "operand %d too large for '%s'"
+msgid "operand %d of '%s' has out of range value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2479
+#: config/tc-xtensa.c:2691
 #, c-format
-msgid "operand %d too small for '%s'"
+msgid "operand %d of '%s' has invalid value '%u'"
 msgstr ""
 
-#: config/tc-xtensa.c:2484
+#: config/tc-xtensa.c:2739
 #, c-format
-msgid "operand %d is invalid for '%s'"
+msgid "internal error: unknown option name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:3716
+#: config/tc-xtensa.c:3791
 msgid "INSTR_LABEL_DEF not supported yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3745
+#: config/tc-xtensa.c:3820
 msgid "can't handle generation of literal/labels yet"
 msgstr ""
 
-#: config/tc-xtensa.c:3749
+#: config/tc-xtensa.c:3824
 msgid "can't handle undefined OP TYPE"
 msgstr ""
 
-#: config/tc-xtensa.c:3810
+#: config/tc-xtensa.c:3885
 #, c-format
 msgid "found %d operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:3817
+#: config/tc-xtensa.c:3892
 #, c-format
 msgid "found too many (%d) operands for '%s':  Expected %d"
 msgstr ""
 
-#: config/tc-xtensa.c:4072
-msgid "instruction fragment may contain data"
+#: config/tc-xtensa.c:4029
+msgid "invalid immediate"
 msgstr ""
 
-#: config/tc-xtensa.c:4105
+#: config/tc-xtensa.c:4140
 #, c-format
-msgid "invalid operand %d on '%s'"
+msgid "invalid relocation for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4116
+#: config/tc-xtensa.c:4150
 #, c-format
-msgid "invalid expression for operand %d on '%s'"
+msgid "invalid expression for operand %i of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4177
+#: config/tc-xtensa.c:4160
 #, c-format
-msgid "invalid relocation operand %i on '%s'"
+msgid "invalid relocation in instruction slot %i"
 msgstr ""
 
-#: config/tc-xtensa.c:4186
+#: config/tc-xtensa.c:4167
 #, c-format
-msgid "undefined symbol for opcode \"%s\"."
+msgid "undefined symbol for opcode \"%s\""
 msgstr ""
 
-#: config/tc-xtensa.c:4280
-msgid "instruction with constant operands does not fit"
+#: config/tc-xtensa.c:4608
+msgid "opcode 'NOP.N' unavailable in this configuration"
 msgstr ""
 
-#: config/tc-xtensa.c:4289
-msgid "instruction with constant operands does not fit without widening"
+#: config/tc-xtensa.c:4668
+msgid "get_expanded_loop_offset: invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:4379
-msgid "instruction's constant operands do not fit"
+#: config/tc-xtensa.c:4751
+#, c-format
+msgid "assembly state not set for first frag in section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:4718
-msgid "opcode 'NOP.N' unavailable in this configuration"
+#: config/tc-xtensa.c:4804
+#, c-format
+msgid "unaligned branch target: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4727
-msgid "opcode 'OR' unavailable in this configuration"
+#: config/tc-xtensa.c:4843
+#, c-format
+msgid "unaligned loop: %d bytes at 0x%lx"
 msgstr ""
 
-#: config/tc-xtensa.c:4737
-#, c-format
-msgid "invalid %d-byte NOP requested"
+#: config/tc-xtensa.c:4867
+msgid "unexpected fix"
 msgstr ""
 
-#: config/tc-xtensa.c:4757
-msgid "get_expanded_loop_offset: undefined opcode"
+#: config/tc-xtensa.c:4878 config/tc-xtensa.c:4882
+msgid "undecodable fix"
 msgstr ""
 
-#: config/tc-xtensa.c:4764
-msgid "get_expanded_loop_offset: invalid opcode"
+#: config/tc-xtensa.c:5012
+msgid "labels are not valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:4880
+#: config/tc-xtensa.c:5032
 msgid "invalid last instruction for a zero-overhead loop"
 msgstr ""
 
-#: config/tc-xtensa.c:4935
+#: config/tc-xtensa.c:5097
+msgid "extra opening brace"
+msgstr ""
+
+#: config/tc-xtensa.c:5107
+msgid "extra closing brace"
+msgstr ""
+
+#: config/tc-xtensa.c:5125
+msgid "missing closing brace"
+msgstr ""
+
+#: config/tc-xtensa.c:5205
 #, c-format
-msgid "cannot assemble '%s' into a literal fragment"
+msgid "unknown opcode or format name '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:4937
-msgid "..."
+#: config/tc-xtensa.c:5211
+msgid "format names only valid inside bundles"
 msgstr ""
 
-#: config/tc-xtensa.c:5071
+#: config/tc-xtensa.c:5216
+#, c-format
+msgid "multiple formats specified for one bundle; using '%s'"
+msgstr ""
+
+#: config/tc-xtensa.c:5271
 msgid "entry instruction with stack decrement < 16"
 msgstr ""
 
-#: config/tc-xtensa.c:5075
+#: config/tc-xtensa.c:5275
 msgid "entry instruction with non-constant decrement"
 msgstr ""
 
-#: config/tc-xtensa.c:5152
+#: config/tc-xtensa.c:5330
+msgid "unaligned entry instruction"
+msgstr ""
+
+#: config/tc-xtensa.c:5389
+msgid "bad instruction format"
+msgstr ""
+
+#: config/tc-xtensa.c:5392
+msgid "invalid relocation"
+msgstr ""
+
+#: config/tc-xtensa.c:5403
 #, c-format
-msgid "undefined @ suffix '%s', expected '%s'"
+msgid "invalid relocation for '%s' instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:5242
+#: config/tc-xtensa.c:5415
 #, c-format
-msgid "invalid operand relocation for '%s' instruction"
+msgid "invalid relocation for operand %d of '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:5245
+#: config/tc-xtensa.c:5572
+msgid "cannot represent subtraction with an offset"
+msgstr ""
+
+#: config/tc-xtensa.c:5660
 #, c-format
-msgid "invalid relocation for operand %d in '%s' instruction"
+msgid "unhandled local relocation fix %s"
 msgstr ""
 
-#: config/tc-xtensa.c:5252
+#: config/tc-xtensa.c:5968
+msgid "couldn't find a valid instruction format"
+msgstr ""
+
+#: config/tc-xtensa.c:5969
 #, c-format
-msgid "invalid relocation type %d for %s instruction"
+msgid "    ops were: "
 msgstr ""
 
-#: config/tc-xtensa.c:5261
+#: config/tc-xtensa.c:5971
 #, c-format
-msgid "invalid relocation for operand %d of '%s'"
+msgid " %s;"
 msgstr ""
 
-#: config/tc-xtensa.c:5269
+#: config/tc-xtensa.c:5974
 #, c-format
-msgid "non-PCREL relocation operand %d for '%s': %s"
+msgid "\n"
 msgstr ""
 
-#: config/tc-xtensa.c:5328 config/tc-xtensa.c:5366
+#: config/tc-xtensa.c:5982
 #, c-format
-msgid "unhandled local relocation fix %s"
+msgid "format '%s' allows %d slots, but there are %d opcodes"
 msgstr ""
 
-#: config/tc-xtensa.c:5350
-msgid "undecodable FIX"
+#: config/tc-xtensa.c:5993 config/tc-xtensa.c:6091
+msgid "illegal resource usage in bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:5478
-msgid "emitting simplification relocation"
+#: config/tc-xtensa.c:6178
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"
 msgstr ""
 
-#: config/tc-xtensa.c:5482
-msgid "emitting unknown relocation"
+#: config/tc-xtensa.c:6183
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"
 msgstr ""
 
-#: config/tc-xtensa.c:5814
+#: config/tc-xtensa.c:6188
 #, c-format
-msgid "fr_var %lu < length %d; ignoring"
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"
 msgstr ""
 
-#: config/tc-xtensa.c:6000 config/tc-xtensa.c:6044
-msgid "undecodable instruction in instruction frag"
+#: config/tc-xtensa.c:6193
+#, c-format
+msgid ""
+"opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"
 msgstr ""
 
-#: config/tc-xtensa.c:6092
-msgid "invalid empty loop"
+#: config/tc-xtensa.c:6209
+msgid "multiple branches or jumps in the same bundle"
 msgstr ""
 
-#: config/tc-xtensa.c:6097
-msgid "loop target does not follow loop instruction in section"
+#: config/tc-xtensa.c:6664
+msgid "cannot assemble into a literal fragment"
 msgstr ""
 
-#: config/tc-xtensa.c:6215
-msgid "get_text_align_power: argument too large"
+#: config/tc-xtensa.c:6666
+msgid "..."
 msgstr ""
 
-#: config/tc-xtensa.c:6420 config/tc-xtensa.c:6566
-msgid "invalid opcode for RELAX_ALIGN_NEXT_OPCODE"
+#: config/tc-xtensa.c:7175
+msgid ""
+"instruction sequence (write a0, branch, retw) may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:6421 config/tc-xtensa.c:6567
-msgid "cannot continue"
+#: config/tc-xtensa.c:7285
+msgid "branching or jumping to a loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:6458
-msgid "expected loop opcode in relax align next target"
+#: config/tc-xtensa.c:7384
+msgid "loop end too close to another loop end may trigger hardware errata"
 msgstr ""
 
-#: config/tc-xtensa.c:6475
-msgid "expected align_code or RELAX_ALIGN_NEXT_OPCODE"
+#: config/tc-xtensa.c:7393
+#, c-format
+msgid "fr_var %lu < length %d"
 msgstr ""
 
-#: config/tc-xtensa.c:6549 config/tc-xtensa.c:6587 config/tc-xtensa.c:6591
-#: config/tc-xtensa.c:6595
-msgid "internal error aligning"
+#: config/tc-xtensa.c:7564
+msgid ""
+"loop containing less than three instructions may trigger hardware errata"
+msgstr ""
+
+#: config/tc-xtensa.c:7636
+msgid "undecodable instruction in instruction frag"
+msgstr ""
+
+#: config/tc-xtensa.c:7745
+msgid "invalid empty loop"
+msgstr ""
+
+#: config/tc-xtensa.c:7750
+msgid "loop target does not follow loop instruction in section"
 msgstr ""
 
-#: config/tc-xtensa.c:6676
+#: config/tc-xtensa.c:8287
 msgid "bad relaxation state"
 msgstr ""
 
-#: config/tc-xtensa.c:6752
+#: config/tc-xtensa.c:8345
 #, c-format
-msgid "fr_var (%ld) < length (%d); ignoring"
+msgid "fr_var (%ld) < length (%d)"
 msgstr ""
 
-#: config/tc-xtensa.c:6928
+#: config/tc-xtensa.c:8846
 msgid "internal error: relaxation failed"
 msgstr ""
 
-#: config/tc-xtensa.c:6934
+#: config/tc-xtensa.c:8852
 msgid "internal error: relaxation requires too many steps"
 msgstr ""
 
-#: config/tc-xtensa.c:7055
+#: config/tc-xtensa.c:9027
 msgid "invalid relaxation fragment result"
 msgstr ""
 
-#: config/tc-xtensa.c:7128
+#: config/tc-xtensa.c:9107
 msgid "unable to widen instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:7215
+#: config/tc-xtensa.c:9250
 msgid "multiple literals in expansion"
 msgstr ""
 
-#: config/tc-xtensa.c:7219
+#: config/tc-xtensa.c:9254
 msgid "no registered fragment for literal"
 msgstr ""
 
-#: config/tc-xtensa.c:7221
+#: config/tc-xtensa.c:9256
 msgid "number of literal tokens != 1"
 msgstr ""
 
-#: config/tc-xtensa.c:7298 config/tc-xtensa.c:7304
+#: config/tc-xtensa.c:9400 config/tc-xtensa.c:9406
 #, c-format
 msgid "unresolved loop target symbol: %s"
 msgstr ""
 
-#: config/tc-xtensa.c:7401
-msgid "loop relaxation specification does not correspond"
+#: config/tc-xtensa.c:9512
+#, c-format
+msgid "invalid expression evaluation type %d"
 msgstr ""
 
-#: config/tc-xtensa.c:7428
+#: config/tc-xtensa.c:9534
 msgid "loop too long for LOOP instruction"
 msgstr ""
 
-#: config/tc-xtensa.c:7465
-#, c-format
-msgid "invalid expression evaluation type %d"
-msgstr ""
-
-#: config/tc-xtensa.c:7702
+#: config/tc-xtensa.c:9805
 #, c-format
 msgid "fixes not all moved from %s"
 msgstr ""
 
-#: config/tc-xtensa.c:7835
-msgid "inlining literal pool; specify location with .literal_position."
+#: config/tc-xtensa.c:9947
+msgid ""
+"literal pool location required for text-section-literals; specify with ."
+"literal_position"
 msgstr ""
 
-#: config/tc-xtensa.c:8230
+#: config/tc-xtensa.c:10456
 #, c-format
 msgid "could not create section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:8232
+#: config/tc-xtensa.c:10458
 #, c-format
 msgid "invalid flag combination on section %s"
 msgstr ""
 
-#: config/tc-xtensa.c:8481
+#: config/tc-xtensa.c:10844
+msgid "too many operands in instruction"
+msgstr ""
+
+#: config/tc-xtensa.c:11078
 #, c-format
 msgid "invalid symbolic operand %d on '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:8545
+#: config/tc-xtensa.c:11147 config/tc-xtensa.c:11221
 msgid "operand number mismatch"
 msgstr ""
 
-#: config/tc-xtensa.c:8592
+#: config/tc-xtensa.c:11150
+msgid "cannot encode opcode"
+msgstr ""
+
+#: config/tc-xtensa.c:11225
+#, c-format
+msgid "cannot encode opcode \"%s\" in the given format \"%s\""
+msgstr ""
+
+#: config/tc-xtensa.c:11250
+#, c-format
+msgid "xtensa-isa failure: %s"
+msgstr ""
+
+#: config/tc-xtensa.c:11283
 msgid "invalid opcode"
 msgstr ""
 
-#: config/tc-xtensa.c:8598
+#: config/tc-xtensa.c:11289
 msgid "too few operands"
 msgstr ""
 
-#: config/tc-xtensa.c:8817
+#: config/tc-xtensa.c:11416 config/tc-xtensa.c:11424
+msgid "out of memory"
+msgstr ""
+
+#: config/tc-xtensa.c:11536
+msgid "instruction with constant operands does not fit"
+msgstr ""
+
+#: config/tc-xtensa.c:11545 config/tc-xtensa.c:11566
+#, c-format
+msgid "invalid operand %d on '%s'"
+msgstr ""
+
+#: config/tc-xtensa.c:11557
+msgid "invalid subtract operand"
+msgstr ""
+
+#: config/tc-xtensa.c:11571
+#, c-format
+msgid "invalid expression for operand %d on '%s'"
+msgstr ""
+
+#: config/tc-xtensa.c:11601
+msgid "cannot decode instruction format"
+msgstr ""
+
+#: config/tc-xtensa.c:11760
 msgid "ignoring extra '-rename-section' delimiter ':'"
 msgstr ""
 
-#: config/tc-xtensa.c:8822
+#: config/tc-xtensa.c:11765
 #, c-format
 msgid "ignoring invalid '-rename-section' specification: '%s'"
 msgstr ""
 
-#: config/tc-xtensa.c:8845
+#: config/tc-xtensa.c:11776
 #, c-format
 msgid "section %s renamed multiple times"
 msgstr ""
 
-#: config/tc-xtensa.c:8847
+#: config/tc-xtensa.c:11778
 #, c-format
 msgid "multiple sections remapped to output section %s"
 msgstr ""
 
-#: config/tc-z8k.c:314
+#: config/tc-z8k.c:268
 #, c-format
 msgid "register rr%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:316
+#: config/tc-z8k.c:270
 #, c-format
 msgid "register rr%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:326
+#: config/tc-z8k.c:280
 #, c-format
 msgid "register rh%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:336
+#: config/tc-z8k.c:290
 #, c-format
 msgid "register rl%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:347
+#: config/tc-z8k.c:301
 #, c-format
 msgid "register rq%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:349
+#: config/tc-z8k.c:303
 #, c-format
 msgid "register rq%d does not exist"
 msgstr ""
 
-#: config/tc-z8k.c:359
+#: config/tc-z8k.c:313
 #, c-format
 msgid "register r%d out of range"
 msgstr ""
 
-#: config/tc-z8k.c:404
+#: config/tc-z8k.c:354
 #, c-format
 msgid "expected %c"
 msgstr ""
 
-#: config/tc-z8k.c:421
+#: config/tc-z8k.c:369
 #, c-format
 msgid "register is wrong size for a word %s"
 msgstr ""
 
-#: config/tc-z8k.c:437
+#: config/tc-z8k.c:383
 #, c-format
 msgid "register is wrong size for address %s"
 msgstr ""
 
+#: config/tc-z8k.c:517
+#, c-format
+msgid "unknown interrupt %s"
+msgstr ""
+
 #. No interrupt type specified, opcode won't do anything.
-#: config/tc-z8k.c:585
+#: config/tc-z8k.c:540
 msgid "opcode has no effect"
 msgstr ""
 
-#: config/tc-z8k.c:697
+#: config/tc-z8k.c:651
 msgid "Missing ) in ra(rb)"
 msgstr ""
 
-#: config/tc-z8k.c:919 config/tc-z8k.c:925
-msgid "invalid indirect register size"
+#: config/tc-z8k.c:731 config/tc-z8k.c:770
+#, c-format
+msgid "invalid condition code '%s'"
 msgstr ""
 
-#: config/tc-z8k.c:971
+#: config/tc-z8k.c:743
 #, c-format
-msgid "operand %s0x%x out of range"
+msgid "invalid flag '%s'"
+msgstr ""
+
+#: config/tc-z8k.c:897 config/tc-z8k.c:903
+msgid "invalid indirect register size"
+msgstr ""
+
+#: config/tc-z8k.c:920 config/tc-z8k.c:1068 config/tc-z8k.c:1073
+msgid "invalid control register name"
 msgstr ""
 
-#: config/tc-z8k.c:1099
+#: config/tc-z8k.c:1057
 msgid "immediate must be 1 or 2"
 msgstr ""
 
-#: config/tc-z8k.c:1102
+#: config/tc-z8k.c:1060
 msgid "immediate 1 or 2 expected"
 msgstr ""
 
-#: config/tc-z8k.c:1129
+#: config/tc-z8k.c:1091
 msgid "can't use R0 here"
 msgstr ""
 
-#: config/tc-z8k.c:1292
+#: config/tc-z8k.c:1249
 msgid "Can't find opcode to match operands"
 msgstr ""
 
-#: config/tc-z8k.c:1411
+#: config/tc-z8k.c:1348
 #, c-format
 msgid "invalid architecture -z%s"
 msgstr ""
 
-#: config/tc-z8k.c:1432
+#: config/tc-z8k.c:1368
+#, c-format
 msgid ""
 " Z8K options:\n"
 "  -z8001                  generate segmented code\n"
@@ -10378,377 +11067,393 @@ msgid ""
 "  -linkrelax              create linker relaxable code\n"
 msgstr ""
 
-#: config/tc-z8k.c:1445
+#: config/tc-z8k.c:1380
+#, c-format
 msgid "call to md_convert_frag\n"
 msgstr ""
 
-#: config/tc-z8k.c:1476 config/tc-z8k.c:1487
+#: config/tc-z8k.c:1487 config/tc-z8k.c:1527 config/tc-z8k.c:1550
 msgid "cannot branch to odd address"
 msgstr ""
 
-#: config/tc-z8k.c:1479 config/tc-z8k.c:1490
+#: config/tc-z8k.c:1491 config/tc-z8k.c:1554
 msgid "relative jump out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1497
-msgid "relative call out of range"
-msgstr ""
-
-#: config/tc-z8k.c:1523
+#: config/tc-z8k.c:1509
 msgid "relative address out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1543
-#, c-format
-msgid "md_apply_fix3: unknown r_type 0x%x\n"
+#: config/tc-z8k.c:1530
+msgid "relative call out of range"
 msgstr ""
 
-#: config/tc-z8k.c:1556
-msgid "call to md_estimate_size_before_relax\n"
+#: config/tc-z8k.c:1562
+#, c-format
+msgid "md_apply_fix: unknown r_type 0x%x\n"
 msgstr ""
 
-#: config/tc-z8k.c:1600
+#: config/tc-z8k.c:1574
 #, c-format
-msgid "Can't subtract symbols in different sections %s %s"
+msgid "call to md_estimate_size_before_relax\n"
 msgstr ""
 
-#: depend.c:200
+#: depend.c:193
 #, c-format
 msgid "can't open `%s' for writing"
 msgstr ""
 
-#: depend.c:212
+#: depend.c:205
 #, c-format
 msgid "can't close `%s'"
 msgstr ""
 
-#: dw2gencfi.c:262
+#: dw2gencfi.c:258
 #, c-format
 msgid "register save offset not a multiple of %u"
 msgstr ""
 
-#: dw2gencfi.c:388
+#: dw2gencfi.c:341
+msgid "CFI state restore without previous remember"
+msgstr ""
+
+#: dw2gencfi.c:387
 msgid "missing separator"
 msgstr ""
 
-#: dw2gencfi.c:410 dw2gencfi.c:428
+#: dw2gencfi.c:409 dw2gencfi.c:427
 msgid "bad register expression"
 msgstr ""
 
-#: dw2gencfi.c:450 dw2gencfi.c:547
+#: dw2gencfi.c:449 dw2gencfi.c:551
 msgid "CFI instruction used without previous .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:579
+#: dw2gencfi.c:587
 msgid "previous CFI entry not closed (missing .cfi_endproc)"
 msgstr ""
 
-#: dw2gencfi.c:612
+#: dw2gencfi.c:622
 msgid ".cfi_endproc without corresponding .cfi_startproc"
 msgstr ""
 
-#: dw2gencfi.c:987
+#: dw2gencfi.c:1031
 msgid "open CFI at the end of file; missing .cfi_endproc directive"
 msgstr ""
 
-#: dwarf2dbg.c:468 dwarf2dbg.c:498
+#: dwarf2dbg.c:523 dwarf2dbg.c:549
 msgid "file number less than one"
 msgstr ""
 
-#: dwarf2dbg.c:474
+#: dwarf2dbg.c:529
 #, c-format
 msgid "file number %ld already allocated"
 msgstr ""
 
-#: dwarf2dbg.c:503 dwarf2dbg.c:1064
+#: dwarf2dbg.c:554 dwarf2dbg.c:1169
 #, c-format
 msgid "unassigned file number %ld"
 msgstr ""
 
-#: dwarf2dbg.c:1130 dwarf2dbg.c:1327
-msgid "internal error: unknown dwarf2 format"
+#: dwarf2dbg.c:622
+msgid "is_stmt value not 0 or 1"
+msgstr ""
+
+#: dwarf2dbg.c:634
+msgid "isa number less than zero"
 msgstr ""
 
-#: dwarf2dbg.c:1472 dwarf2dbg.c:1480 dwarf2dbg.c:1488 dwarf2dbg.c:1509
-msgid "dwarf2 is not supported for this object file format"
+#: dwarf2dbg.c:640
+#, c-format
+msgid "unknown .loc sub-directive `%s'"
+msgstr ""
+
+#: dwarf2dbg.c:1234 dwarf2dbg.c:1428
+msgid "internal error: unknown dwarf2 format"
 msgstr ""
 
-#: ecoff.c:1556
+#: ecoff.c:1552
 #, c-format
 msgid "string too big (%lu bytes)"
 msgstr ""
 
-#: ecoff.c:1582
+#: ecoff.c:1578
 #, c-format
 msgid "inserting \"%s\" into string hash table: %s"
 msgstr ""
 
-#: ecoff.c:1614 ecoff.c:1808 ecoff.c:1833 ecoff.c:1865 ecoff.c:2019
-#: ecoff.c:2132
+#: ecoff.c:1609 ecoff.c:1802 ecoff.c:1825 ecoff.c:1856 ecoff.c:2009
+#: ecoff.c:2120
 msgid "no current file pointer"
 msgstr ""
 
-#: ecoff.c:1701
+#: ecoff.c:1696
 msgid "too many st_End's"
 msgstr ""
 
-#: ecoff.c:2044
+#: ecoff.c:2034
 #, c-format
 msgid "inserting \"%s\" into tag hash table: %s"
 msgstr ""
 
-#: ecoff.c:2210
+#: ecoff.c:2195
 msgid "fake .file after real one"
 msgstr ""
 
-#: ecoff.c:2300
+#: ecoff.c:2285
 msgid "filename goes over one page boundary"
 msgstr ""
 
-#: ecoff.c:2435
+#: ecoff.c:2418
 msgid ".begin directive without a preceding .file directive"
 msgstr ""
 
-#: ecoff.c:2442
+#: ecoff.c:2425
 msgid ".begin directive without a preceding .ent directive"
 msgstr ""
 
-#: ecoff.c:2474
+#: ecoff.c:2456
 msgid ".bend directive without a preceding .file directive"
 msgstr ""
 
-#: ecoff.c:2481
+#: ecoff.c:2463
 msgid ".bend directive without a preceding .ent directive"
 msgstr ""
 
-#: ecoff.c:2494
+#: ecoff.c:2476
 msgid ".bend directive names unknown symbol"
 msgstr ""
 
-#: ecoff.c:2538
+#: ecoff.c:2519
 msgid ".def pseudo-op used inside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2540
+#: ecoff.c:2521
 msgid "empty symbol name in .def; ignored"
 msgstr ""
 
-#: ecoff.c:2578
+#: ecoff.c:2558
 msgid ".dim pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2593
+#: ecoff.c:2573
 msgid "badly formed .dim directive"
 msgstr ""
 
-#: ecoff.c:2606
+#: ecoff.c:2586
 msgid "too many .dim entries"
 msgstr ""
 
-#: ecoff.c:2627
+#: ecoff.c:2606
 msgid ".scl pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2653
+#: ecoff.c:2631
 msgid ".size pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2668
+#: ecoff.c:2646
 msgid "badly formed .size directive"
 msgstr ""
 
-#: ecoff.c:2681
+#: ecoff.c:2659
 msgid "too many .size entries"
 msgstr ""
 
-#: ecoff.c:2704
+#: ecoff.c:2681
 msgid ".type pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
 #. FIXME: We could handle this by setting the continued bit.
 #. There would still be a limit: the .type argument can not
 #. be infinite.
-#: ecoff.c:2722
+#: ecoff.c:2699
 #, c-format
 msgid "the type of %s is too complex; it will be simplified"
 msgstr ""
 
-#: ecoff.c:2733
+#: ecoff.c:2710
 msgid "Unrecognized .type argument"
 msgstr ""
 
-#: ecoff.c:2772
+#: ecoff.c:2748
 msgid ".tag pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2798
+#: ecoff.c:2773
 msgid ".val pseudo-op used outside of .def/.endef; ignored"
 msgstr ""
 
-#: ecoff.c:2806
+#: ecoff.c:2781
 msgid ".val expression is too copmlex"
 msgstr ""
 
-#: ecoff.c:2837
+#: ecoff.c:2811
 msgid ".endef pseudo-op used before .def; ignored"
 msgstr ""
 
-#: ecoff.c:2863 ecoff.c:2944
+#: ecoff.c:2837 ecoff.c:2918
 msgid "bad COFF debugging information"
 msgstr ""
 
-#: ecoff.c:2912
+#: ecoff.c:2886
 #, c-format
 msgid "no tag specified for %s"
 msgstr ""
 
-#: ecoff.c:3015
+#: ecoff.c:2988
 msgid ".end directive without a preceding .file directive"
 msgstr ""
 
-#: ecoff.c:3022
+#: ecoff.c:2995
 msgid ".end directive without a preceding .ent directive"
 msgstr ""
 
-#: ecoff.c:3044
+#: ecoff.c:3017
 msgid ".end directive names unknown symbol"
 msgstr ""
 
-#: ecoff.c:3072
+#: ecoff.c:3044
 msgid "second .ent directive found before .end directive"
 msgstr ""
 
-#: ecoff.c:3146
+#: ecoff.c:3116
 msgid "no way to handle .file within .ent/.end section"
 msgstr ""
 
-#: ecoff.c:3271
+#: ecoff.c:3233
 msgid ".loc before .file"
 msgstr ""
 
-#: ecoff.c:3410
+#: ecoff.c:3355 read.c:1473 read.c:1579 read.c:2256 read.c:2803 symbols.c:327
+#: symbols.c:423
+#, c-format
+msgid "symbol `%s' is already defined"
+msgstr ""
+
+#: ecoff.c:3368
 msgid "bad .weakext directive"
 msgstr ""
 
-#: ecoff.c:3479
+#: ecoff.c:3436
 #, c-format
 msgid ".stab%c is not supported"
 msgstr ""
 
-#: ecoff.c:3489
+#: ecoff.c:3446
 #, c-format
 msgid ".stab%c: ignoring non-zero other field"
 msgstr ""
 
-#: ecoff.c:3523
+#: ecoff.c:3480
 #, c-format
 msgid ""
 "line number (%d) for .stab%c directive cannot fit in index field (20 bits)"
 msgstr ""
 
-#: ecoff.c:3559
+#: ecoff.c:3516
 #, c-format
 msgid "illegal .stab%c directive, bad character"
 msgstr ""
 
-#: ecoff.c:4021 ecoff.c:4210 ecoff.c:4235
+#: ecoff.c:3975 ecoff.c:4164 ecoff.c:4189
 msgid ".begin/.bend in different segments"
 msgstr ""
 
-#: ecoff.c:4737
+#: ecoff.c:4685
 msgid "missing .end or .bend at end of file"
 msgstr ""
 
-#: ecoff.c:5227
+#: ecoff.c:5170
 msgid "GP prologue size exceeds field size, using 0 instead"
 msgstr ""
 
-#: expr.c:83 read.c:3232
+#: expr.c:82 read.c:3351
 msgid "bignum invalid"
 msgstr ""
 
-#: expr.c:85 read.c:3234 read.c:3574 read.c:4474
+#: expr.c:84 read.c:3353 read.c:3702 read.c:4550
 msgid "floating point number invalid"
 msgstr ""
 
-#: expr.c:243
+#: expr.c:203
 msgid "bad floating-point constant: exponent overflow"
 msgstr ""
 
-#: expr.c:247
+#: expr.c:207
 #, c-format
 msgid "bad floating-point constant: unknown error code=%d"
 msgstr ""
 
-#: expr.c:425
+#: expr.c:383
 msgid ""
 "a bignum with underscores may not have more than 8 hex digits in any word"
 msgstr ""
 
-#: expr.c:448
+#: expr.c:406
 msgid "a bignum with underscores must have exactly 4 words"
 msgstr ""
 
 #. Either not seen or not defined.
 #. @@ Should print out the original string instead of
 #. the parsed number.
-#: expr.c:571
+#: expr.c:529
 #, c-format
 msgid "backward ref to unknown label \"%d:\""
 msgstr ""
 
-#: expr.c:694
+#: expr.c:647
 msgid "character constant too large"
 msgstr ""
 
-#: expr.c:942
+#: expr.c:893
 #, c-format
 msgid "expr.c(operand): bad atof_generic return val %d"
 msgstr ""
 
-#: expr.c:1004
+#: expr.c:954
 #, c-format
 msgid "missing '%c'"
 msgstr ""
 
-#: expr.c:1016 read.c:3945
+#: expr.c:965 read.c:4034
 msgid "EBCDIC constants are not supported"
 msgstr ""
 
-#: expr.c:1099
+#: expr.c:1082
 #, c-format
 msgid "Unary operator %c ignored because bad operand follows"
 msgstr ""
 
-#: expr.c:1145 expr.c:1170
+#: expr.c:1128 expr.c:1153
 msgid "syntax error in .startof. or .sizeof."
 msgstr ""
 
-#: expr.c:1666
+#: expr.c:1665
 msgid "missing operand; zero assumed"
 msgstr ""
 
-#: expr.c:1701
+#: expr.c:1700
 msgid "left operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1703
+#: expr.c:1702
 msgid "left operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1712
+#: expr.c:1711
 msgid "right operand is a bignum; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1714
+#: expr.c:1713
 msgid "right operand is a float; integer 0 assumed"
 msgstr ""
 
-#: expr.c:1770 symbols.c:1191
+#: expr.c:1769 symbols.c:1207
 msgid "division by zero"
 msgstr ""
 
-#: expr.c:1868
+#: expr.c:1867
 msgid "operation combines symbols in different segments"
 msgstr ""
 
@@ -10760,11 +11465,12 @@ msgstr ""
 msgid "attempt to allocate data in common section"
 msgstr ""
 
-#: frags.c:107
+#: frags.c:112
 #, c-format
 msgid "can't extend frag %u chars"
 msgstr ""
 
+#. For error messages.
 #. Detect if we are reading from stdin by examining the file
 #. name returned by as_where().
 #.
@@ -10776,508 +11482,615 @@ msgstr ""
 #. line here (assuming of course that we actually have a line of
 #. input to read), so that it can be displayed in the listing
 #. that is produced at the end of the assembly.
-#: input-file.c:145 input-scrub.c:242 listing.c:343
+#: input-file.c:141 input-scrub.c:238 listing.c:332
 msgid "{standard input}"
 msgstr ""
 
-#: input-file.c:149
+#: input-file.c:147 input-file.c:156
 #, c-format
-msgid "can't open %s for reading"
+msgid "Can't open %s for reading"
 msgstr ""
 
-#: input-file.c:212 input-file.c:239
+#: input-file.c:219 input-file.c:246
 #, c-format
 msgid "Can't read from %s"
 msgstr ""
 
-#: input-file.c:247
+#: input-file.c:256
 #, c-format
 msgid "Can't close %s"
 msgstr ""
 
-#: input-scrub.c:272
+#: input-scrub.c:263
 msgid "macros nested too deeply"
 msgstr ""
 
-#: input-scrub.c:375 input-scrub.c:397
+#: input-scrub.c:365 input-scrub.c:387
 msgid "partial line at end of file ignored"
 msgstr ""
 
-#: itbl-ops.c:351
+#: itbl-ops.c:338
+#, c-format
 msgid "Unable to allocate memory for new instructions\n"
 msgstr ""
 
-#: listing.c:243
+#: listing.c:238
 msgid "Warning:"
 msgstr ""
 
-#: listing.c:250
+#: listing.c:244
 msgid "Error:"
 msgstr ""
 
-#: listing.c:1130
+#: listing.c:1089
 #, c-format
 msgid "can't open list file: %s"
 msgstr ""
 
-#: listing.c:1154
+#: listing.c:1109
 #, c-format
 msgid "error closing list file: %s"
 msgstr ""
 
-#: listing.c:1233
+#: listing.c:1182
 msgid "strange paper height, set to no form"
 msgstr ""
 
-#: listing.c:1299
+#: listing.c:1246
 msgid "new line in title"
 msgstr ""
 
 #. Turns the next expression into a string.
-#: macro.c:382
+#: macro.c:436
 #, no-c-format
 msgid "% operator needs absolute expression"
 msgstr ""
 
-#: macro.c:545
-msgid "unexpected end of file in macro definition"
+#: macro.c:558
+#, c-format
+msgid "Missing parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:554
-msgid "missing ) after formals"
+#: macro.c:568
+#, c-format
+msgid "`%s' is not a valid parameter qualifier for `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:703
-msgid "missplaced )"
+#: macro.c:585
+#, c-format
+msgid "Pointless default value for required parameter `%s' in macro `%s'"
 msgstr ""
 
-#: macro.c:960
+#: macro.c:597
+#, c-format
+msgid "A parameter named `%s' already exists for macro `%s'"
+msgstr ""
+
+#: macro.c:634
+#, c-format
+msgid "Reserved word `%s' used as parameter in macro `%s'"
+msgstr ""
+
+#: macro.c:672
+#, c-format
+msgid "unexpected end of file in macro `%s' definition"
+msgstr ""
+
+#: macro.c:684
+#, c-format
+msgid "missing `)' after formals in macro definition `%s'"
+msgstr ""
+
+#: macro.c:699
+msgid "Missing macro name"
+msgstr ""
+
+#: macro.c:708
+#, c-format
+msgid "Bad parameter list for macro `%s'"
+msgstr ""
+
+#: macro.c:714
+#, c-format
+msgid "Macro `%s' was already defined"
+msgstr ""
+
+#: macro.c:837 macro.c:839
+msgid "missing `)'"
+msgstr ""
+
+#: macro.c:934
+#, c-format
+msgid "`%s' was already used as parameter (or another local) name"
+msgstr ""
+
+#: macro.c:1093
 msgid "confusion in formal parameters"
 msgstr ""
 
-#: macro.c:965
-msgid "macro formal argument does not exist"
+#: macro.c:1100
+#, c-format
+msgid "Parameter named `%s' does not exist for macro `%s'"
 msgstr ""
 
-#: macro.c:980
+#: macro.c:1108
+#, c-format
+msgid "Value for parameter `%s' of macro `%s' was already specified"
+msgstr ""
+
+#: macro.c:1124
 msgid "can't mix positional and keyword arguments"
 msgstr ""
 
-#: macro.c:988
+#: macro.c:1135
 msgid "too many positional arguments"
 msgstr ""
 
-#: macro.c:1163
+#: macro.c:1183
+#, c-format
+msgid "Missing value for required parameter `%s' of macro `%s'"
+msgstr ""
+
+#: macro.c:1320
+#, c-format
+msgid "Attempt to purge non-existant macro `%s'"
+msgstr ""
+
+#: macro.c:1339
 msgid "unexpected end of file in irp or irpc"
 msgstr ""
 
-#: macro.c:1171
+#: macro.c:1347
 msgid "missing model parameter"
 msgstr ""
 
 #: messages.c:104
+#, c-format
 msgid "Assembler messages:\n"
 msgstr ""
 
-#: messages.c:214
+#: messages.c:206
+#, c-format
 msgid "Warning: "
 msgstr ""
 
-#: messages.c:318
+#: messages.c:307
+#, c-format
 msgid "Error: "
 msgstr ""
 
-#: messages.c:413 messages.c:433
+#: messages.c:402 messages.c:422
+#, c-format
 msgid "Fatal error: "
 msgstr ""
 
-#: messages.c:450
+#: messages.c:437
+#, c-format
 msgid "Internal error!\n"
 msgstr ""
 
-#: messages.c:452
+#: messages.c:439
 #, c-format
 msgid "Assertion failure in %s at %s line %d.\n"
 msgstr ""
 
-#: messages.c:455
+#: messages.c:442
 #, c-format
 msgid "Assertion failure at %s line %d.\n"
 msgstr ""
 
-#: messages.c:456 messages.c:475
+#: messages.c:443 messages.c:460
+#, c-format
 msgid "Please report this bug.\n"
 msgstr ""
 
-#: messages.c:470
+#: messages.c:455
 #, c-format
 msgid "Internal error, aborting at %s line %d in %s\n"
 msgstr ""
 
-#: messages.c:473
+#: messages.c:458
 #, c-format
 msgid "Internal error, aborting at %s line %d\n"
 msgstr ""
 
-#: output-file.c:48
+#: messages.c:507
 #, c-format
-msgid "can't open a bfd on stdout %s"
+msgid "%s out of range (%d is not between %d and %d)"
 msgstr ""
 
-#: output-file.c:52 output-file.c:115
+#. xgettext:c-format.
+#: messages.c:530
 #, c-format
-msgid "FATAL: can't create %s"
+msgid "%s out of range (0x%s is not between 0x%s and 0x%s)"
 msgstr ""
 
-#: output-file.c:73 output-file.c:80
+#: output-file.c:39
 #, c-format
-msgid "FATAL: can't close %s\n"
+msgid "can't open a bfd on stdout %s"
 msgstr ""
 
-#: output-file.c:126
+#: output-file.c:44
 #, c-format
-msgid "FATAL: can't close %s"
+msgid "Selected target format '%s' unknown"
 msgstr ""
 
-#: output-file.c:147
-msgid "Failed to emit an object byte"
+#: output-file.c:46
+#, c-format
+msgid "FATAL: can't create %s"
 msgstr ""
 
-#: output-file.c:148
-msgid "can't continue"
+#: output-file.c:63
+#, c-format
+msgid "FATAL: can't close %s\n"
 msgstr ""
 
-#: read.c:442
+#: read.c:450
+msgid "bad or irreducible absolute expression"
+msgstr ""
+
+#: read.c:476
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr ""
 
-#: read.c:809
+#: read.c:896
 #, c-format
 msgid "unknown pseudo-op: `%s'"
 msgstr ""
 
-#: read.c:940
+#: read.c:983
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr ""
 
-#: read.c:1152
+#: read.c:1214
 msgid ".abort detected.  Abandoning ship."
 msgstr ""
 
-#: read.c:1174 read.c:2413
+#: read.c:1232 read.c:2406
 msgid "ignoring fill value in absolute section"
 msgstr ""
 
-#: read.c:1260
+#: read.c:1322
 #, c-format
 msgid "alignment too large: %u assumed"
 msgstr ""
 
-#: read.c:1292
+#: read.c:1354
 msgid "expected fill pattern missing"
 msgstr ""
 
-#: read.c:1417
+#: read.c:1457
+msgid "missing size expression"
+msgstr ""
+
+#: read.c:1463
 #, c-format
-msgid "length of .comm \"%s\" is already %ld; not changing to %ld"
+msgid "size (%ld) out of range, ignored"
+msgstr ""
+
+#: read.c:1483
+#, c-format
+msgid "size of \"%s\" is already %ld; not changing to %ld"
 msgstr ""
 
 #. Some of the back ends can't deal with non-positive line numbers.
-#. Besides, it's silly.
-#: read.c:1636
+#. Besides, it's silly.  GCC however will generate a line number of
+#. zero when it is pre-processing builtins for assembler-with-cpp files:
+#.
+#. # 0 "<built-in>"
+#.
+#. We do not want to barf on this, especially since such files are used
+#. in the GCC and GDB testsuites.  So we check for negative line numbers
+#. rather than non-positive line numbers.
+#: read.c:1712
 #, c-format
 msgid "line numbers must be positive; line number %d rejected"
 msgstr ""
 
-#: read.c:1664
+#: read.c:1739
 msgid "start address not supported"
 msgstr ""
 
-#: read.c:1674
+#: read.c:1748
 msgid ".err encountered"
 msgstr ""
 
-#: read.c:1693 read.c:1695
+#: read.c:1764
+msgid ".error directive invoked in source file"
+msgstr ""
+
+#: read.c:1765
+msgid ".warning directive invoked in source file"
+msgstr ""
+
+#: read.c:1771
+#, c-format
+msgid "%s argument must be a string"
+msgstr ""
+
+#: read.c:1803 read.c:1805
 #, c-format
 msgid ".fail %ld encountered"
 msgstr ""
 
-#: read.c:1732
+#: read.c:1841
 #, c-format
 msgid ".fill size clamped to %d"
 msgstr ""
 
-#: read.c:1737
+#: read.c:1846
 msgid "size negative; .fill ignored"
 msgstr ""
 
-#: read.c:1743
+#: read.c:1852
 msgid "repeat < 0; .fill ignored"
 msgstr ""
 
-#: read.c:1903
+#: read.c:2010
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr ""
 
-#: read.c:1916 read.c:1942
+#: read.c:2022
 msgid ".linkonce is not supported for this object file format"
 msgstr ""
 
-#: read.c:1938
+#: read.c:2044
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr ""
 
-#: read.c:1993
-msgid "missing size expression"
-msgstr ""
-
-#: read.c:1999
-#, c-format
-msgid "BSS length (%d) < 0 ignored"
-msgstr ""
-
-#: read.c:2015
+#: read.c:2070
 #, c-format
 msgid "error setting flags for \".sbss\": %s"
 msgstr ""
 
-#: read.c:2038
-msgid "expected comma after size"
+#: read.c:2117
+msgid "expected alignment after size"
 msgstr ""
 
-#: read.c:2072
-#, c-format
-msgid "alignment too large; %d assumed"
-msgstr ""
-
-#: read.c:2077
+#: read.c:2131
 msgid "alignment negative; 0 assumed"
 msgstr ""
 
-#: read.c:2342
+#: read.c:2340
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr ""
 
-#: read.c:2408
+#: read.c:2401
 #, c-format
 msgid "invalid segment \"%s\""
 msgstr ""
 
-#: read.c:2416
+#: read.c:2409
 msgid "only constant offsets supported in absolute section"
 msgstr ""
 
-#: read.c:2456
+#: read.c:2448
 msgid "MRI style ORG pseudo-op not supported"
 msgstr ""
 
-#: read.c:2613
+#: read.c:2601
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr ""
 
-#: read.c:2627
+#: read.c:2615
 msgid "absolute sections are not supported"
 msgstr ""
 
-#: read.c:2642
+#: read.c:2630
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr ""
 
-#: read.c:2708
-msgid ".endr encountered without preceeding .rept, .irc, or .irp"
+#: read.c:2694
+#, c-format
+msgid ".end%c encountered without preceeding %s"
 msgstr ""
 
-#: read.c:2740
+#: read.c:2724
 #, c-format
 msgid "%s without %s"
 msgstr ""
 
-#: read.c:2949
+#: read.c:2951
 msgid "unsupported variable size or fill value"
 msgstr ""
 
-#: read.c:2974
+#: read.c:2979
 msgid ".space repeat count is zero, ignored"
 msgstr ""
 
-#: read.c:2976
+#: read.c:2981
 msgid ".space repeat count is negative, ignored"
 msgstr ""
 
-#: read.c:3005
+#: read.c:3010
 msgid "space allocation too complex in absolute section"
 msgstr ""
 
-#: read.c:3011
+#: read.c:3016
 msgid "space allocation too complex in common section"
 msgstr ""
 
-#: read.c:3099 read.c:4190
+#: read.c:3103 read.c:4276
 #, c-format
 msgid "bad floating literal: %s"
 msgstr ""
 
-#: read.c:3172
+#: read.c:3243
 #, c-format
-msgid "rest of line ignored; first ignored character is `%c'"
+msgid "%s: would close weakref loop: %s"
 msgstr ""
 
-#: read.c:3175
+#: read.c:3286
 #, c-format
-msgid "rest of line ignored; first ignored character valued 0x%x"
+msgid "junk at end of line, first unrecognized character is `%c'"
 msgstr ""
 
-#: read.c:3228
+#: read.c:3289
+#, c-format
+msgid "junk at end of line, first unrecognized character valued 0x%x"
+msgstr ""
+
+#: read.c:3347
 msgid "missing expression"
 msgstr ""
 
-#: read.c:3404
+#: read.c:3408
+#, c-format
+msgid "`%s' can't be equated to common symbol '%s'"
+msgstr ""
+
+#: read.c:3536
 msgid "rva without symbol"
 msgstr ""
 
-#: read.c:3530
+#: read.c:3658
 msgid "attempt to store value in absolute section"
 msgstr ""
 
-#: read.c:3568 read.c:4468
+#: read.c:3696 read.c:4544
 msgid "zero assumed for missing expression"
 msgstr ""
 
-#: read.c:3580 read.c:4480 write.c:322
+#: read.c:3708 read.c:4556 write.c:265
 msgid "register value used as expression"
 msgstr ""
 
 #. Leading bits contain both 0s & 1s.
-#: read.c:3671
+#: read.c:3786
 #, c-format
 msgid "value 0x%lx truncated to 0x%lx"
 msgstr ""
 
-#: read.c:3687
+#: read.c:3802
 #, c-format
 msgid "bignum truncated to %d bytes"
 msgstr ""
 
-#: read.c:3854
+#: read.c:3943
 msgid "using a bit field width of zero"
 msgstr ""
 
-#: read.c:3862
+#: read.c:3951
 #, c-format
 msgid "field width \"%s\" too complex for a bitfield"
 msgstr ""
 
-#: read.c:3870
+#: read.c:3959
 #, c-format
 msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
 msgstr ""
 
-#: read.c:3892
+#: read.c:3981
 #, c-format
 msgid "field value \"%s\" too complex for a bitfield"
 msgstr ""
 
-#: read.c:4018 read.c:4212
+#: read.c:4107 read.c:4298
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr ""
 
-#: read.c:4069
+#: read.c:4156
 #, c-format
 msgid "unknown floating type type '%c'"
 msgstr ""
 
-#: read.c:4091
+#: read.c:4178
 msgid "floating point constant too large"
 msgstr ""
 
-#: read.c:4581
+#: read.c:4670
 msgid "strings must be placed into a section"
 msgstr ""
 
-#: read.c:4631
+#: read.c:4720
 msgid "expected <nn>"
 msgstr ""
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4664 read.c:4750
+#: read.c:4753 read.c:4839
 msgid "unterminated string; newline inserted"
 msgstr ""
 
-#: read.c:4758
+#: read.c:4847
 msgid "bad escaped character in string"
 msgstr ""
 
-#: read.c:4784
+#: read.c:4872
 msgid "expected address expression"
 msgstr ""
 
-#: read.c:4804
+#: read.c:4891
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr ""
 
-#: read.c:4807
+#: read.c:4894
 msgid "some symbol undefined; zero assumed"
 msgstr ""
 
-#: read.c:4824
-msgid "bad or irreducible absolute expression"
-msgstr ""
-
-#: read.c:4867
+#: read.c:4930
 msgid "this string may not contain '\\0'"
 msgstr ""
 
-#: read.c:4904
+#: read.c:4966
 msgid "missing string"
 msgstr ""
 
-#: read.c:5027
+#: read.c:5053
 #, c-format
 msgid ".incbin count zero, ignoring `%s'"
 msgstr ""
 
-#: read.c:5053
+#: read.c:5079
 #, c-format
 msgid "file not found: %s"
 msgstr ""
 
-#: read.c:5067
+#: read.c:5093
 #, c-format
 msgid "seek to end of .incbin file failed `%s'"
 msgstr ""
 
-#: read.c:5078
+#: read.c:5104
 #, c-format
-msgid "skip (%ld) + count (%ld) larger than file size (%ld)"
+msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
 msgstr ""
 
-#: read.c:5085
+#: read.c:5111
 #, c-format
 msgid "could not skip to %ld in file `%s'"
 msgstr ""
 
-#: read.c:5094
+#: read.c:5120
 #, c-format
 msgid "truncated file `%s', %ld of %ld bytes read"
 msgstr ""
 
-#: read.c:5257
+#: read.c:5278
 msgid "missing .func"
 msgstr ""
 
-#: read.c:5274
+#: read.c:5295
 msgid ".endfunc missing for previous .func"
 msgstr ""
 
-#: stabs.c:220 stabs.c:228 stabs.c:236 stabs.c:255
+#: read.c:5418
+#, c-format
+msgid "missing closing `%c'"
+msgstr ""
+
+#: read.c:5420
+msgid "stray `\\'"
+msgstr ""
+
+#: stabs.c:212 stabs.c:220 stabs.c:228 stabs.c:247
 #, c-format
 msgid ".stab%c: missing comma"
 msgstr ""
@@ -11285,183 +12098,196 @@ msgstr ""
 #. This could happen for example with a source file with a huge
 #. number of lines.  The only cure is to use a different debug
 #. format, probably DWARF.
-#: stabs.c:248
+#: stabs.c:240
 #, c-format
 msgid ".stab%c: description field '%x' too big, try a different debug format"
 msgstr ""
 
-#: stabs.c:433
+#: stabs.c:421
 msgid "comma missing in .xstabs"
 msgstr ""
 
-#: subsegs.c:377
-#, c-format
-msgid "attempt to switch to nonexistent segment \"%s\""
-msgstr ""
-
-#: symbols.c:318
+#: symbols.c:278
 #, c-format
 msgid "cannot define symbol `%s' in absolute section"
 msgstr ""
 
-#: symbols.c:452
+#: symbols.c:409
 #, c-format
 msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
 msgstr ""
 
-#: symbols.c:529 symbols.c:536
+#: symbols.c:483 symbols.c:490
 #, c-format
 msgid "inserting \"%s\" into symbol table failed: %s"
 msgstr ""
 
-#: symbols.c:874 symbols.c:878
+#: symbols.c:864 symbols.c:868
 #, c-format
 msgid "undefined symbol `%s' in operation"
 msgstr ""
 
-#: symbols.c:885
+#: symbols.c:875
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s'"
 msgstr ""
 
-#: symbols.c:889
+#: symbols.c:879
 #, c-format
 msgid "invalid section for operation on `%s'"
 msgstr ""
 
-#: symbols.c:897 symbols.c:900
+#: symbols.c:887 symbols.c:890
 #, c-format
 msgid "undefined symbol `%s' in operation setting `%s'"
 msgstr ""
 
-#: symbols.c:907
+#: symbols.c:897
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:911
+#: symbols.c:901
 #, c-format
 msgid "invalid section for operation on `%s' setting `%s'"
 msgstr ""
 
-#: symbols.c:964
+#: symbols.c:951
 #, c-format
 msgid "symbol definition loop encountered at `%s'"
 msgstr ""
 
-#: symbols.c:1193
+#: symbols.c:1209
 #, c-format
 msgid "division by zero when setting `%s'"
 msgstr ""
 
-#: symbols.c:1280 write.c:2008
+#: symbols.c:1291 write.c:1545
 #, c-format
 msgid "can't resolve value for symbol `%s'"
 msgstr ""
 
-#: symbols.c:1674
+#: symbols.c:1738
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr ""
 
-#: symbols.c:1711
+#: symbols.c:1775
 #, c-format
 msgid "attempt to get value of unresolved symbol `%s'"
 msgstr ""
 
-#: symbols.c:1971
+#: symbols.c:2045
 msgid "section symbols are already global"
 msgstr ""
 
-#: symbols.c:2014
+#: symbols.c:2150
 #, c-format
 msgid "Accessing function `%s' as thread-local object"
 msgstr ""
 
-#: symbols.c:2018
+#: symbols.c:2154
 #, c-format
 msgid "Accessing `%s' as thread-local object"
 msgstr ""
 
-#: write.c:215
+#: write.c:164
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr ""
 
-#: write.c:349
-msgid "rva not supported"
+#: write.c:440
+#, c-format
+msgid "attempt to .org/.space backwards? (%ld)"
 msgstr ""
 
-#: write.c:570
+#: write.c:691
 #, c-format
-msgid "attempt to .org/.space backwards? (%ld)"
+msgid "Local symbol `%s' can't be equated to undefined symbol `%s'"
 msgstr ""
 
-#: write.c:1002 write.c:1074
+#: write.c:865 write.c:937
 msgid "relocation out of range"
 msgstr ""
 
-#: write.c:1005 write.c:1077
+#: write.c:868 write.c:940
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr ""
 
-#: write.c:1057
+#: write.c:920
 msgid "internal error: fixup not contained within frag"
 msgstr ""
 
-#: write.c:1164 write.c:1188
+#: write.c:1026 write.c:1050
 #, c-format
 msgid "FATAL: Can't write %s"
 msgstr ""
 
-#: write.c:1220
+#: write.c:1082
 msgid "cannot write to output file"
 msgstr ""
 
-#: write.c:1477
+#: write.c:1223
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file"
 msgstr ""
 
-#: write.c:1484
+#: write.c:1230
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated"
 msgstr ""
 
-#: write.c:1945
+#: write.c:1464
+#, c-format
+msgid "%s: global symbols not supported in common sections"
+msgstr ""
+
+#: write.c:1478
 #, c-format
 msgid "local label `%s' is not defined"
 msgstr ""
 
-#: write.c:2244
+#: write.c:1498
+#, c-format
+msgid "Local symbol `%s' can't be equated to common symbol `%s'"
+msgstr ""
+
+#: write.c:1768
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr ""
 
-#: write.c:2361
+#: write.c:1900
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ""
 
-#: write.c:2446
+#: write.c:1976
 msgid "attempt to move .org backwards"
 msgstr ""
 
-#: write.c:2474
+#: write.c:2004
 msgid ".space specifies non-absolute value"
 msgstr ""
 
-#: write.c:2481
+#: write.c:2011
 msgid ".space or .fill with negative value, ignored"
 msgstr ""
 
-#: write.c:2773
+#: write.c:2067
+#, c-format
+msgid ""
+"Infinite loop encountered whilst attempting to compute the addresses of "
+"symbols in section %s"
+msgstr ""
+
+#: write.c:2289
 #, c-format
 msgid "value of %s too large for field of %d bytes at %s"
 msgstr ""
 
-#: write.c:2785
+#: write.c:2301
 #, c-format
 msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr ""
diff --git a/gas/po/rw.gmo b/gas/po/rw.gmo
new file mode 100644
index 000000000000..35ffd398da00
--- /dev/null
+++ b/gas/po/rw.gmo
diff --git a/gas/po/rw.po b/gas/po/rw.po
new file mode 100644
index 000000000000..18a020836d76
--- /dev/null
+++ b/gas/po/rw.po
@@ -0,0 +1,3100 @@
+# Kinyarwanda translations for bfd package.
+# Copyright (C) 2005 Free Software Foundation, Inc.
+# This file is distributed under the same license as the bfd package.
+# Steve Murphy <murf@e-tools.com>, 2005.
+# Steve performed initial rough translation from compendium built from translations provided by the following translators:
+# Philibert Ndandali  <ndandali@yahoo.fr>, 2005.
+# Viateur MUGENZI <muvia1@yahoo.fr>, 2005.
+# Noëlla Mupole <s24211045@tuks.co.za>, 2005.
+# Carole Karema <karemacarole@hotmail.com>, 2005.
+# JEAN BAPTISTE NGENDAHAYO <ngenda_denis@yahoo.co.uk>, 2005.
+# Augustin KIBERWA  <akiberwa@yahoo.co.uk>, 2005.
+# Donatien NSENGIYUMVA <ndonatienuk@yahoo.co.uk>, 2005.
+# Antoine Bigirimana <antoine@e-tools.com>, 2005.
+#
+msgid ""
+msgstr ""
+"Project-Id-Version: bfd 2.14rel030712\n"
+"POT-Creation-Date: 2003-07-11 13:53+0930\n"
+"PO-Revision-Date: 2005-04-04 10:55-0700\n"
+"Last-Translator: Steven Michael Murphy <murf@e-tools.com>\n"
+"Language-Team: Kinyarwanda <translation-team-rw@lists.sourceforge.net>\n"
+"MIME-Version: 1.0\n"
+"Content-Type: text/plain; charset=UTF-8\n"
+"Content-Transfer-Encoding: 8bit\n"
+
+#: aout-adobe.c:204
+#, fuzzy, c-format
+msgid "%s: Unknown section type in a.out.adobe file: %x\n"
+msgstr "%s:Inyuma."
+
+#: aout-cris.c:207
+#, fuzzy, c-format
+msgid "%s: Invalid relocation type exported: %d"
+msgstr "%s:Ubwoko"
+
+#: aout-cris.c:251
+#, fuzzy, c-format
+msgid "%s: Invalid relocation type imported: %d"
+msgstr "%s:Ubwoko cyavuye ahandi/ cyatumijwe"
+
+#: aout-cris.c:262
+#, fuzzy, c-format
+msgid "%s: Bad relocation record imported: %d"
+msgstr "%s:Icyabitswe cyavuye ahandi/ cyatumijwe"
+
+#: aoutx.h:1295 aoutx.h:1716
+#, fuzzy, c-format
+msgid "%s: can not represent section `%s' in a.out object file format"
+msgstr "%s:OYA Icyiciro in a Inyuma Igikoresho IDOSIYE Imiterere"
+
+#: aoutx.h:1682
+#, fuzzy, c-format
+msgid "%s: can not represent section for symbol `%s' in a.out object file format"
+msgstr "%s:OYA Icyiciro kugirango IKIMENYETSO in a Inyuma Igikoresho IDOSIYE Imiterere"
+
+#: aoutx.h:1684
+#, fuzzy
+msgid "*unknown*"
+msgstr "*Itazwi>"
+
+#: aoutx.h:3776
+#, fuzzy, c-format
+msgid "%s: relocatable link from %s to %s not supported"
+msgstr "%s:Ihuza Bivuye Kuri OYA"
+
+#: archive.c:1751
+#, fuzzy
+msgid "Warning: writing archive was slow: rewriting timestamp\n"
+msgstr "Buhoro"
+
+#: archive.c:2014
+#, fuzzy
+msgid "Reading archive file mod timestamp"
+msgstr "IDOSIYE MOD"
+
+#: archive.c:2040
+msgid "Writing updated armap timestamp"
+msgstr ""
+
+#: bfd.c:280
+msgid "No error"
+msgstr "Nta kosa"
+
+#: bfd.c:281
+#, fuzzy
+msgid "System call error"
+msgstr "Ikosa"
+
+#: bfd.c:282
+#, fuzzy
+msgid "Invalid bfd target"
+msgstr "Intego"
+
+#: bfd.c:283
+#, fuzzy
+msgid "File in wrong format"
+msgstr "Idosiye in Imiterere"
+
+#: bfd.c:284
+#, fuzzy
+msgid "Archive object file in wrong format"
+msgstr "Igikoresho IDOSIYE in Imiterere"
+
+#: bfd.c:285
+msgid "Invalid operation"
+msgstr ""
+
+#: bfd.c:286
+msgid "Memory exhausted"
+msgstr ""
+
+#: bfd.c:287
+#, fuzzy
+msgid "No symbols"
+msgstr "Ibimenyetso"
+
+#: bfd.c:288
+#, fuzzy
+msgid "Archive has no index; run ranlib to add one"
+msgstr "Oya Umubarendanga Gukoresha Kuri Kongeramo"
+
+#: bfd.c:289
+#, fuzzy
+msgid "No more archived files"
+msgstr "Birenzeho Idosiye"
+
+#: bfd.c:290
+msgid "Malformed archive"
+msgstr ""
+
+#: bfd.c:291
+#, fuzzy
+msgid "File format not recognized"
+msgstr "Idosiye Imiterere OYA"
+
+#: bfd.c:292
+#, fuzzy
+msgid "File format is ambiguous"
+msgstr "Idosiye Imiterere ni"
+
+#: bfd.c:293
+#, fuzzy
+msgid "Section has no contents"
+msgstr "Oya Ibigize"
+
+#: bfd.c:294
+#, fuzzy
+msgid "Nonrepresentable section on output"
+msgstr "Icyiciro ku Ibisohoka"
+
+#: bfd.c:295
+#, fuzzy
+msgid "Symbol needs debug section which does not exist"
+msgstr "Kosora amakosa Icyiciro OYA"
+
+#: bfd.c:296
+#, fuzzy
+msgid "Bad value"
+msgstr "Agaciro"
+
+#: bfd.c:297
+#, fuzzy
+msgid "File truncated"
+msgstr "Idosiye"
+
+#: bfd.c:298
+#, fuzzy
+msgid "File too big"
+msgstr "Idosiye"
+
+#: bfd.c:299
+#, fuzzy
+msgid "#<Invalid error code>"
+msgstr "#<Ikosa ITEGEKONGENGA"
+
+#: bfd.c:687
+#, c-format
+msgid "BFD %s assertion fail %s:%d"
+msgstr ""
+
+#: bfd.c:703
+#, fuzzy, c-format
+msgid "BFD %s internal error, aborting at %s line %d in %s\n"
+msgstr "By'imbere Ikosa ku Umurongo in"
+
+#: bfd.c:707
+#, fuzzy, c-format
+msgid "BFD %s internal error, aborting at %s line %d\n"
+msgstr "By'imbere Ikosa ku Umurongo"
+
+#: bfd.c:709
+#, fuzzy
+msgid "Please report this bug.\n"
+msgstr "Icyegeranyo iyi"
+
+#: bfdwin.c:202
+#, fuzzy, c-format
+msgid "not mapping: data=%lx mapped=%d\n"
+msgstr "OYA Igereranya Ibyatanzwe"
+
+#: bfdwin.c:205
+#, fuzzy
+msgid "not mapping: env var not set\n"
+msgstr "OYA Igereranya VAR OYA"
+
+#: binary.c:306
+#, fuzzy, c-format
+msgid "Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx."
+msgstr "Icyiciro Kuri IDOSIYE Nta- boneza"
+
+#: coff-a29k.c:120
+msgid "Missing IHCONST"
+msgstr ""
+
+#: coff-a29k.c:181
+msgid "Missing IHIHALF"
+msgstr ""
+
+#: coff-a29k.c:213 coff-or32.c:236
+msgid "Unrecognized reloc"
+msgstr ""
+
+#: coff-a29k.c:409
+#, fuzzy
+msgid "missing IHCONST reloc"
+msgstr "Ibuze"
+
+#: coff-a29k.c:499
+#, fuzzy
+msgid "missing IHIHALF reloc"
+msgstr "Ibuze"
+
+#: coff-alpha.c:884 coff-alpha.c:921 coff-alpha.c:1992 coff-mips.c:1397
+#, fuzzy
+msgid "GP relative relocation used when GP not defined"
+msgstr "Bifitanye isano Ryari: OYA"
+
+#: coff-alpha.c:1488
+#, fuzzy
+msgid "using multiple gp values"
+msgstr "ikoresha Igikubo Uduciro"
+
+#: coff-arm.c:1066 elf32-arm.h:294
+#, fuzzy, c-format
+msgid "%s: unable to find THUMB glue '%s' for `%s'"
+msgstr "%s:Kuri Gushaka kugirango"
+
+#: coff-arm.c:1096 elf32-arm.h:329
+#, fuzzy, c-format
+msgid "%s: unable to find ARM glue '%s' for `%s'"
+msgstr "%s:Kuri Gushaka kugirango"
+
+#: coff-arm.c:1394 coff-arm.c:1489 elf32-arm.h:892 elf32-arm.h:999
+#, fuzzy, c-format
+msgid "%s(%s): warning: interworking not enabled."
+msgstr "%s(%s):Iburira OYA Bikora"
+
+#: coff-arm.c:1398 elf32-arm.h:1002
+#, fuzzy, c-format
+msgid "  first occurrence: %s: arm call to thumb"
+msgstr "Itangira ukugaragara Kuri"
+
+#: coff-arm.c:1493 elf32-arm.h:895
+#, fuzzy, c-format
+msgid "  first occurrence: %s: thumb call to arm"
+msgstr "Itangira ukugaragara Kuri"
+
+#: coff-arm.c:1496
+#, fuzzy
+msgid "  consider relinking with --support-old-code enabled"
+msgstr "Na: Gushigikira ki/ bishaje ITEGEKONGENGA Bikora"
+
+#: coff-arm.c:1788 coff-tic80.c:687 cofflink.c:3038
+#, fuzzy, c-format
+msgid "%s: bad reloc address 0x%lx in section `%s'"
+msgstr "%s:Aderesi in Icyiciro"
+
+#: coff-arm.c:2132
+#, fuzzy, c-format
+msgid "%s: illegal symbol index in reloc: %d"
+msgstr "%s:IKIMENYETSO Umubarendanga in"
+
+#: coff-arm.c:2265
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled for APCS-%d, whereas %s is compiled for APCS-%d"
+msgstr "ni kugirango ni kugirango"
+
+#: coff-arm.c:2280 elf32-arm.h:2328
+#, fuzzy, c-format
+msgid "ERROR: %s passes floats in float registers, whereas %s passes them in integer registers"
+msgstr "in Kureremba in Umubare wuzuye"
+
+#: coff-arm.c:2283 elf32-arm.h:2333
+#, fuzzy, c-format
+msgid "ERROR: %s passes floats in integer registers, whereas %s passes them in float registers"
+msgstr "in Umubare wuzuye in Kureremba"
+
+#: coff-arm.c:2298
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled as position independent code, whereas target %s is absolute position"
+msgstr "ni Nka Ibirindiro ITEGEKONGENGA Intego ni Ibirindiro"
+
+#: coff-arm.c:2301
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled as absolute position code, whereas target %s is position independent"
+msgstr "ni Nka Ibirindiro ITEGEKONGENGA Intego ni Ibirindiro"
+
+#: coff-arm.c:2330 elf32-arm.h:2405
+#, fuzzy, c-format
+msgid "Warning: %s supports interworking, whereas %s does not"
+msgstr "OYA"
+
+#: coff-arm.c:2333 elf32-arm.h:2412
+#, fuzzy, c-format
+msgid "Warning: %s does not support interworking, whereas %s does"
+msgstr "OYA Gushigikira"
+
+#: coff-arm.c:2360
+#, fuzzy, c-format
+msgid "private flags = %x:"
+msgstr "By'umwihariko Amabendera"
+
+#: coff-arm.c:2368 elf32-arm.h:2467
+#, fuzzy
+msgid " [floats passed in float registers]"
+msgstr "[in Kureremba"
+
+#: coff-arm.c:2370
+#, fuzzy
+msgid " [floats passed in integer registers]"
+msgstr "[in Umubare wuzuye"
+
+#: coff-arm.c:2373 elf32-arm.h:2470
+#, fuzzy
+msgid " [position independent]"
+msgstr "[Ibirindiro"
+
+#: coff-arm.c:2375
+#, fuzzy
+msgid " [absolute position]"
+msgstr "[Ibirindiro"
+
+#: coff-arm.c:2379
+#, fuzzy
+msgid " [interworking flag not initialised]"
+msgstr "[Ibendera OYA"
+
+#: coff-arm.c:2381
+msgid " [interworking supported]"
+msgstr ""
+
+#: coff-arm.c:2383
+#, fuzzy
+msgid " [interworking not supported]"
+msgstr "[OYA"
+
+#: coff-arm.c:2431 elf32-arm.h:2150
+#, fuzzy, c-format
+msgid "Warning: Not setting interworking flag of %s since it has already been specified as non-interworking"
+msgstr "Igenamiterere Ibendera Bya guhera Nka"
+
+#: coff-arm.c:2435 elf32-arm.h:2154
+#, fuzzy, c-format
+msgid "Warning: Clearing the interworking flag of %s due to outside request"
+msgstr "i Ibendera Bya Kuri Hanze Kubaza..."
+
+#: coff-h8300.c:1096
+#, fuzzy, c-format
+msgid "cannot handle R_MEM_INDIRECT reloc when using %s output"
+msgstr "Ryari: ikoresha Ibisohoka"
+
+#: coff-i960.c:137 coff-i960.c:486
+#, fuzzy
+msgid "uncertain calling convention for non-COFF symbol"
+msgstr "kugirango IKIMENYETSO"
+
+#: coff-m68k.c:482 coff-mips.c:2394 elf32-m68k.c:2193 elf32-mips.c:1783
+#, fuzzy
+msgid "unsupported reloc type"
+msgstr "Ubwoko"
+
+#: coff-mips.c:839 elf32-mips.c:1088 elf64-mips.c:1590 elfn32-mips.c:1554
+#, fuzzy
+msgid "GP relative relocation when _gp not defined"
+msgstr "Bifitanye isano Ryari: OYA"
+
+#. No other sections should appear in -membedded-pic
+#. code.
+#: coff-mips.c:2431
+#, fuzzy
+msgid "reloc against unsupported section"
+msgstr "Icyiciro"
+
+#: coff-mips.c:2439
+#, fuzzy
+msgid "reloc not properly aligned"
+msgstr "OYA"
+
+#: coff-rs6000.c:2790
+#, fuzzy, c-format
+msgid "%s: unsupported relocation type 0x%02x"
+msgstr "%s:Ubwoko"
+
+#: coff-rs6000.c:2883
+#, fuzzy, c-format
+msgid "%s: TOC reloc at 0x%x to symbol `%s' with no TOC entry"
+msgstr "%s:ku Kuri IKIMENYETSO Na: Oya Icyinjijwe"
+
+#: coff-rs6000.c:3616 coff64-rs6000.c:2109
+#, fuzzy, c-format
+msgid "%s: symbol `%s' has unrecognized smclas %d"
+msgstr "%s:IKIMENYETSO"
+
+#: coff-tic4x.c:170 coff-tic54x.c:288 coff-tic80.c:450
+#, fuzzy, c-format
+msgid "Unrecognized reloc type 0x%x"
+msgstr "Ubwoko"
+
+#: coff-tic4x.c:218 coff-tic54x.c:373 coffcode.h:5045
+#, fuzzy, c-format
+msgid "%s: warning: illegal symbol index %ld in relocs"
+msgstr "%s:Iburira IKIMENYETSO Umubarendanga in"
+
+#: coff-w65.c:364
+#, c-format
+msgid "ignoring reloc %s\n"
+msgstr ""
+
+#: coffcode.h:1108
+#, fuzzy, c-format
+msgid "%s (%s): Section flag %s (0x%x) ignored"
+msgstr "%s(%s):Ibendera"
+
+#: coffcode.h:2214
+#, fuzzy, c-format
+msgid "Unrecognized TI COFF target id '0x%x'"
+msgstr "Intego ID"
+
+#: coffcode.h:4437
+#, fuzzy, c-format
+msgid "%s: warning: illegal symbol index %ld in line numbers"
+msgstr "%s:Iburira IKIMENYETSO Umubarendanga in Umurongo Imibare"
+
+#: coffcode.h:4451
+#, fuzzy, c-format
+msgid "%s: warning: duplicate line number information for `%s'"
+msgstr "%s:Iburira Gusubiramo Umurongo Umubare Ibisobanuro kugirango"
+
+#: coffcode.h:4805
+#, fuzzy, c-format
+msgid "%s: Unrecognized storage class %d for %s symbol `%s'"
+msgstr "%s:ishuri kugirango IKIMENYETSO"
+
+#: coffcode.h:4938
+#, fuzzy, c-format
+msgid "warning: %s: local symbol `%s' has no section"
+msgstr "Iburira IKIMENYETSO Oya Icyiciro"
+
+#: coffcode.h:5083
+#, fuzzy, c-format
+msgid "%s: illegal relocation type %d at address 0x%lx"
+msgstr "%s:Ubwoko ku Aderesi"
+
+#: coffgen.c:1666
+#, fuzzy, c-format
+msgid "%s: bad string table size %lu"
+msgstr "%s:Ikurikiranyanyuguti imbonerahamwe# Ingano"
+
+#: cofflink.c:538 elflink.h:1276
+#, fuzzy, c-format
+msgid "Warning: type of symbol `%s' changed from %d to %d in %s"
+msgstr "Ubwoko Bya IKIMENYETSO Byahinduwe Bivuye Kuri in"
+
+#: cofflink.c:2328
+#, fuzzy, c-format
+msgid "%s: relocs in section `%s', but it has no contents"
+msgstr "%s:in Icyiciro Oya Ibigize"
+
+#: cofflink.c:2671 coffswap.h:890
+#, fuzzy, c-format
+msgid "%s: %s: reloc overflow: 0x%lx > 0xffff"
+msgstr "%s:%s:Byarenze urugero"
+
+#: cofflink.c:2680 coffswap.h:876
+#, fuzzy, c-format
+msgid "%s: warning: %s: line number overflow: 0x%lx > 0xffff"
+msgstr "%s:Iburira Umurongo Umubare Byarenze urugero"
+
+#: cpu-arm.c:196 cpu-arm.c:206
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled for the EP9312, whereas %s is compiled for XScale"
+msgstr "ni kugirango i ni kugirango"
+
+#: cpu-arm.c:344
+#, fuzzy, c-format
+msgid "warning: unable to update contents of %s section in %s"
+msgstr "Iburira Kuri Kuvugurura Ibigize Bya Icyiciro in"
+
+#: dwarf2.c:380
+#, fuzzy
+msgid "Dwarf Error: Can't find .debug_str section."
+msgstr "Gushaka Icyiciro"
+
+#: dwarf2.c:397
+#, fuzzy, c-format
+msgid "Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu)."
+msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano"
+
+#: dwarf2.c:541
+#, fuzzy
+msgid "Dwarf Error: Can't find .debug_abbrev section."
+msgstr "Gushaka Icyiciro"
+
+#: dwarf2.c:556
+#, fuzzy, c-format
+msgid "Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu)."
+msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano"
+
+#: dwarf2.c:756
+#, fuzzy, c-format
+msgid "Dwarf Error: Invalid or unhandled FORM value: %u."
+msgstr "Cyangwa Agaciro"
+
+#: dwarf2.c:933
+#, fuzzy
+msgid "Dwarf Error: mangled line number section (bad file number)."
+msgstr "Umurongo Umubare Icyiciro IDOSIYE Umubare"
+
+#: dwarf2.c:1032
+#, fuzzy
+msgid "Dwarf Error: Can't find .debug_line section."
+msgstr "Gushaka Icyiciro"
+
+#: dwarf2.c:1049
+#, fuzzy, c-format
+msgid "Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu)."
+msgstr "Nta- boneza Biruta Cyangwa bingana Kuri Ingano"
+
+#: dwarf2.c:1255
+#, fuzzy
+msgid "Dwarf Error: mangled line number section."
+msgstr "Umurongo Umubare Icyiciro"
+
+#: dwarf2.c:1470 dwarf2.c:1620
+#, fuzzy, c-format
+msgid "Dwarf Error: Could not find abbrev number %u."
+msgstr "OYA Gushaka Umubare"
+
+#: dwarf2.c:1581
+#, fuzzy, c-format
+msgid "Dwarf Error: found dwarf version '%u', this reader only handles version 2 information."
+msgstr "Byabonetse Verisiyo iyi Verisiyo 2. Ibisobanuro"
+
+#: dwarf2.c:1588
+#, fuzzy, c-format
+msgid "Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'."
+msgstr "Byabonetse Aderesi Ingano iyi OYA Biruta"
+
+#: dwarf2.c:1611
+#, fuzzy, c-format
+msgid "Dwarf Error: Bad abbrev number: %u."
+msgstr "Umubare"
+
+#: ecoff.c:1339
+#, fuzzy, c-format
+msgid "Unknown basic type %d"
+msgstr "BASIC Ubwoko"
+
+#: ecoff.c:1599
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      End+1 symbol: %ld"
+msgstr "Impera 1. IKIMENYETSO"
+
+#: ecoff.c:1606 ecoff.c:1609
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      First symbol: %ld"
+msgstr "IKIMENYETSO"
+
+#: ecoff.c:1621
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      End+1 symbol: %-7ld   Type:  %s"
+msgstr "Impera 1. IKIMENYETSO"
+
+#: ecoff.c:1628
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      Local symbol: %ld"
+msgstr "IKIMENYETSO"
+
+#: ecoff.c:1636
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      struct; End+1 symbol: %ld"
+msgstr "Impera 1. IKIMENYETSO"
+
+#: ecoff.c:1641
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      union; End+1 symbol: %ld"
+msgstr "Ihuza Impera 1. IKIMENYETSO"
+
+#: ecoff.c:1646
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      enum; End+1 symbol: %ld"
+msgstr "Impera 1. IKIMENYETSO"
+
+# #-#-#-#-#  dbaccess.pot (PACKAGE VERSION)  #-#-#-#-#
+# #-#-#-#-#  dbaccess.pot (PACKAGE VERSION)  #-#-#-#-#
+#: ecoff.c:1652
+#, fuzzy, c-format
+msgid ""
+"\n"
+"      Type: %s"
+msgstr "Ubwoko"
+
+#: elf-hppa.h:1458 elf-hppa.h:1491 elf-m10300.c:1628 elf64-sh64.c:1704
+#, fuzzy, c-format
+msgid "%s: warning: unresolvable relocation against symbol `%s' from %s section"
+msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro"
+
+#: elf-m10200.c:442 elf-m10300.c:1695 elf32-arm.h:2088 elf32-avr.c:812
+#: elf32-cris.c:1390 elf32-d10v.c:570 elf32-fr30.c:634 elf32-frv.c:815
+#: elf32-h8300.c:528 elf32-i860.c:1028 elf32-ip2k.c:1586 elf32-iq2000.c:699
+#: elf32-m32r.c:1283 elf32-m68hc1x.c:1305 elf32-msp430.c:510
+#: elf32-openrisc.c:436 elf32-v850.c:1777 elf32-xstormy16.c:976
+#: elf64-mmix.c:1332
+#, fuzzy
+msgid "internal error: out of range error"
+msgstr "By'imbere Ikosa Inyuma Bya Urutonde Ikosa"
+
+#: elf-m10200.c:446 elf-m10300.c:1699 elf32-arm.h:2092 elf32-avr.c:816
+#: elf32-cris.c:1394 elf32-d10v.c:574 elf32-fr30.c:638 elf32-frv.c:819
+#: elf32-h8300.c:532 elf32-i860.c:1032 elf32-iq2000.c:703 elf32-m32r.c:1287
+#: elf32-m68hc1x.c:1309 elf32-msp430.c:514 elf32-openrisc.c:440
+#: elf32-v850.c:1781 elf32-xstormy16.c:980 elf64-mmix.c:1336 elfxx-mips.c:6452
+#, fuzzy
+msgid "internal error: unsupported relocation error"
+msgstr "By'imbere Ikosa Ikosa"
+
+#: elf-m10200.c:450 elf-m10300.c:1703 elf32-arm.h:2096 elf32-d10v.c:578
+#: elf32-h8300.c:536 elf32-m32r.c:1291 elf32-m68hc1x.c:1313
+#, fuzzy
+msgid "internal error: dangerous error"
+msgstr "By'imbere Ikosa Ikosa"
+
+#: elf-m10200.c:454 elf-m10300.c:1707 elf32-arm.h:2100 elf32-avr.c:824
+#: elf32-cris.c:1402 elf32-d10v.c:582 elf32-fr30.c:646 elf32-frv.c:827
+#: elf32-h8300.c:540 elf32-i860.c:1040 elf32-ip2k.c:1601 elf32-iq2000.c:711
+#: elf32-m32r.c:1295 elf32-m68hc1x.c:1317 elf32-msp430.c:522
+#: elf32-openrisc.c:448 elf32-v850.c:1801 elf32-xstormy16.c:988
+#: elf64-mmix.c:1344
+#, fuzzy
+msgid "internal error: unknown error"
+msgstr "By'imbere Ikosa Kitazwi Ikosa"
+
+#: elf.c:372
+#, fuzzy, c-format
+msgid "%s: invalid string offset %u >= %lu for section `%s'"
+msgstr "%s:Sibyo Ikurikiranyanyuguti Nta- boneza kugirango Icyiciro"
+
+#: elf.c:624
+#, fuzzy, c-format
+msgid "%s: invalid SHT_GROUP entry"
+msgstr "%s:Sibyo Icyinjijwe"
+
+#: elf.c:695
+#, fuzzy, c-format
+msgid "%s: no group info for section %s"
+msgstr "%s:Oya Itsinda Ibisobanuro kugirango Icyiciro"
+
+#: elf.c:1055
+msgid ""
+"\n"
+"Program Header:\n"
+msgstr ""
+
+#: elf.c:1106
+msgid ""
+"\n"
+"Dynamic Section:\n"
+msgstr ""
+
+#: elf.c:1235
+msgid ""
+"\n"
+"Version definitions:\n"
+msgstr ""
+
+#: elf.c:1258
+msgid ""
+"\n"
+"Version References:\n"
+msgstr ""
+
+#: elf.c:1263
+#, fuzzy, c-format
+msgid "  required from %s:\n"
+msgstr "Bya ngombwa Bivuye"
+
+#: elf.c:1944
+#, fuzzy, c-format
+msgid "%s: invalid link %lu for reloc section %s (index %u)"
+msgstr "%s:Sibyo Ihuza kugirango Icyiciro Umubarendanga"
+
+#: elf.c:3686
+#, fuzzy, c-format
+msgid "%s: Not enough room for program headers (allocated %u, need %u)"
+msgstr "%s:kugirango Porogaramu Imitwe"
+
+#: elf.c:3791
+#, fuzzy, c-format
+msgid "%s: Not enough room for program headers, try linking with -N"
+msgstr "%s:kugirango Porogaramu Imitwe Impuza Na:"
+
+#: elf.c:3922
+#, fuzzy, c-format
+msgid "Error: First section in segment (%s) starts at 0x%x whereas the segment starts at 0x%x"
+msgstr "Icyiciro in ku i ku"
+
+#: elf.c:4242
+#, fuzzy, c-format
+msgid "%s: warning: allocated section `%s' not in segment"
+msgstr "%s:Iburira Icyiciro OYA in"
+
+#: elf.c:4566
+#, fuzzy, c-format
+msgid "%s: symbol `%s' required but not present"
+msgstr "%s:IKIMENYETSO Bya ngombwa OYA"
+
+#: elf.c:4854
+#, fuzzy, c-format
+msgid "%s: warning: Empty loadable segment detected, is this intentional ?\n"
+msgstr "%s:Iburira ni iyi"
+
+#: elf.c:5485
+#, fuzzy, c-format
+msgid "Unable to find equivalent output section for symbol '%s' from section '%s'"
+msgstr "Kuri Gushaka Ibisohoka Icyiciro kugirango IKIMENYETSO Bivuye Icyiciro"
+
+#: elf.c:6298
+#, fuzzy, c-format
+msgid "%s: unsupported relocation type %s"
+msgstr "%s:Ubwoko"
+
+#: elf32-arm.h:1228
+#, fuzzy, c-format
+msgid "%s: Warning: Arm BLX instruction targets Arm function '%s'."
+msgstr "%s:Umumaro"
+
+#: elf32-arm.h:1424
+#, fuzzy, c-format
+msgid "%s: Warning: Thumb BLX instruction targets thumb function '%s'."
+msgstr "%s:Umumaro"
+
+#: elf32-arm.h:1918 elf32-sh.c:4706 elf64-sh64.c:1613
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): %s relocation against SEC_MERGE section"
+msgstr "%s(%s+0x%lx):%sIcyiciro"
+
+#: elf32-arm.h:2012
+#, fuzzy, c-format
+msgid "%s: warning: unresolvable relocation %d against symbol `%s' from %s section"
+msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-arm.h:2202
+#, fuzzy, c-format
+msgid "Warning: Clearing the interworking flag of %s because non-interworking code in %s has been linked with it"
+msgstr "i Ibendera Bya ITEGEKONGENGA in Na:"
+
+#: elf32-arm.h:2302
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled for EABI version %d, whereas %s is compiled for version %d"
+msgstr "ni kugirango Verisiyo ni kugirango Verisiyo"
+
+#: elf32-arm.h:2316
+#, fuzzy, c-format
+msgid "ERROR: %s is compiled for APCS-%d, whereas target %s uses APCS-%d"
+msgstr "ni kugirango Intego"
+
+#: elf32-arm.h:2344
+#, fuzzy, c-format
+msgid "ERROR: %s uses VFP instructions, whereas %s does not"
+msgstr "Amabwiriza OYA"
+
+#: elf32-arm.h:2349
+#, fuzzy, c-format
+msgid "ERROR: %s uses FPA instructions, whereas %s does not"
+msgstr "Amabwiriza OYA"
+
+#: elf32-arm.h:2360 elf32-arm.h:2365
+#, fuzzy, c-format
+msgid "ERROR: %s uses Maverick instructions, whereas %s does not"
+msgstr "Amabwiriza OYA"
+
+#: elf32-arm.h:2385
+#, c-format
+msgid "ERROR: %s uses software FP, whereas %s uses hardware FP"
+msgstr ""
+
+#: elf32-arm.h:2390
+#, c-format
+msgid "ERROR: %s uses hardware FP, whereas %s uses software FP"
+msgstr ""
+
+#. Ignore init flag - it may not be set, despite the flags field
+#. containing valid data.
+#: elf32-arm.h:2443 elf32-cris.c:2975 elf32-m68hc1x.c:1459 elf32-m68k.c:397
+#: elf32-vax.c:546 elfxx-mips.c:9238
+#, fuzzy, c-format
+msgid "private flags = %lx:"
+msgstr "By'umwihariko Amabendera"
+
+#: elf32-arm.h:2452
+#, fuzzy
+msgid " [interworking enabled]"
+msgstr "[Bikora"
+
+#: elf32-arm.h:2460
+#, fuzzy
+msgid " [VFP float format]"
+msgstr "[Kureremba Imiterere"
+
+#: elf32-arm.h:2462
+#, fuzzy
+msgid " [Maverick float format]"
+msgstr "[Kureremba Imiterere"
+
+#: elf32-arm.h:2464
+#, fuzzy
+msgid " [FPA float format]"
+msgstr "[Kureremba Imiterere"
+
+#: elf32-arm.h:2473
+#, fuzzy
+msgid " [new ABI]"
+msgstr "[Gishya"
+
+#: elf32-arm.h:2476
+#, fuzzy
+msgid " [old ABI]"
+msgstr "[ki/ bishaje"
+
+#: elf32-arm.h:2479
+msgid " [software FP]"
+msgstr ""
+
+#: elf32-arm.h:2488
+msgid " [Version1 EABI]"
+msgstr ""
+
+#: elf32-arm.h:2491 elf32-arm.h:2502
+#, fuzzy
+msgid " [sorted symbol table]"
+msgstr "[bishunguwe IKIMENYETSO imbonerahamwe#"
+
+#: elf32-arm.h:2493 elf32-arm.h:2504
+#, fuzzy
+msgid " [unsorted symbol table]"
+msgstr "[bitashunguye IKIMENYETSO imbonerahamwe#"
+
+#: elf32-arm.h:2499
+msgid " [Version2 EABI]"
+msgstr ""
+
+#: elf32-arm.h:2507
+#, fuzzy
+msgid " [dynamic symbols use segment index]"
+msgstr "[Ibimenyetso Gukoresha Umubarendanga"
+
+#: elf32-arm.h:2510
+#, fuzzy
+msgid " [mapping symbols precede others]"
+msgstr "[Igereranya Ibimenyetso Ibindi"
+
+#: elf32-arm.h:2517
+#, fuzzy
+msgid " <EABI version unrecognised>"
+msgstr "<Verisiyo"
+
+#: elf32-arm.h:2524
+msgid " [relocatable executable]"
+msgstr ""
+
+#: elf32-arm.h:2527
+#, fuzzy
+msgid " [has entry point]"
+msgstr "[Icyinjijwe Akadomo"
+
+#: elf32-arm.h:2532
+#, fuzzy
+msgid "<Unrecognised flag bits set>"
+msgstr "<Ibendera Gushyiraho"
+
+#: elf32-avr.c:820 elf32-cris.c:1398 elf32-fr30.c:642 elf32-frv.c:823
+#: elf32-i860.c:1036 elf32-ip2k.c:1597 elf32-iq2000.c:707 elf32-msp430.c:518
+#: elf32-openrisc.c:444 elf32-v850.c:1785 elf32-xstormy16.c:984
+#: elf64-mmix.c:1340
+#, fuzzy
+msgid "internal error: dangerous relocation"
+msgstr "By'imbere Ikosa"
+
+#: elf32-cris.c:931
+#, fuzzy, c-format
+msgid "%s: unresolvable relocation %s against symbol `%s' from %s section"
+msgstr "%s:IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-cris.c:993
+#, fuzzy, c-format
+msgid "%s: No PLT nor GOT for relocation %s against symbol `%s' from %s section"
+msgstr "%s:kugirango IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-cris.c:996 elf32-cris.c:1122
+#, fuzzy
+msgid "[whose name is lost]"
+msgstr "[bya Izina: ni"
+
+#: elf32-cris.c:1111
+#, fuzzy, c-format
+msgid "%s: relocation %s with non-zero addend %d against local symbol from %s section"
+msgstr "%s:Na: Zeru IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-cris.c:1118
+#, fuzzy, c-format
+msgid "%s: relocation %s with non-zero addend %d against symbol `%s' from %s section"
+msgstr "%s:Na: Zeru IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-cris.c:1143
+#, fuzzy, c-format
+msgid "%s: relocation %s is not allowed for global symbol: `%s' from %s section"
+msgstr "%s:ni OYA kugirango IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-cris.c:1158
+#, fuzzy, c-format
+msgid "%s: relocation %s in section %s with no GOT created"
+msgstr "%s:in Icyiciro Na: Oya Byaremwe"
+
+#: elf32-cris.c:1277
+#, fuzzy, c-format
+msgid "%s: Internal inconsistency; no relocation section %s"
+msgstr "%s:Oya Icyiciro"
+
+#: elf32-cris.c:2500
+#, fuzzy, c-format
+msgid ""
+"%s, section %s:\n"
+"  relocation %s should not be used in a shared object; recompile with -fPIC"
+msgstr "%s,Icyiciro OYA in a Igikoresho Na:"
+
+#: elf32-cris.c:2978
+#, fuzzy
+msgid " [symbols have a _ prefix]"
+msgstr "[Ibimenyetso a Imbanziriza"
+
+#: elf32-cris.c:3017
+#, fuzzy, c-format
+msgid "%s: uses _-prefixed symbols, but writing file with non-prefixed symbols"
+msgstr "%s:Ibimenyetso IDOSIYE Na: Ibimenyetso"
+
+#: elf32-cris.c:3018
+#, fuzzy, c-format
+msgid "%s: uses non-prefixed symbols, but writing file with _-prefixed symbols"
+msgstr "%s:Ibimenyetso IDOSIYE Na: Ibimenyetso"
+
+#: elf32-frv.c:1223
+#, fuzzy, c-format
+msgid "%s: compiled with %s and linked with modules that use non-pic relocations"
+msgstr "%s:Na: Na Na: Modire Gukoresha"
+
+#: elf32-frv.c:1273 elf32-iq2000.c:895
+#, fuzzy, c-format
+msgid "%s: compiled with %s and linked with modules compiled with %s"
+msgstr "%s:Na: Na Na: Modire Na:"
+
+#: elf32-frv.c:1285
+#, fuzzy, c-format
+msgid "%s: uses different unknown e_flags (0x%lx) fields than previous modules (0x%lx)"
+msgstr "%s:Kitazwi Imyanya Ibanjirije Modire"
+
+#: elf32-frv.c:1321 elf32-iq2000.c:933
+#, fuzzy, c-format
+msgid "private flags = 0x%lx:"
+msgstr "By'umwihariko Amabendera"
+
+#: elf32-gen.c:83 elf64-gen.c:82
+#, fuzzy, c-format
+msgid "%s: Relocations in generic ELF (EM: %d)"
+msgstr "%s:in Gifitanye isano"
+
+#: elf32-hppa.c:672 elf32-m68hc1x.c:176 elf64-ppc.c:3118
+#, fuzzy, c-format
+msgid "%s: cannot create stub entry %s"
+msgstr "%s:Kurema Icyinjijwe"
+
+#: elf32-hppa.c:957 elf32-hppa.c:3538
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): cannot reach %s, recompile with -ffunction-sections"
+msgstr "%s(%s+0x%lx):Na: Ibyatoranyijwe"
+
+#: elf32-hppa.c:1340 elf64-x86-64.c:672 elf64-x86-64.c:797
+#, fuzzy, c-format
+msgid "%s: relocation %s can not be used when making a shared object; recompile with -fPIC"
+msgstr "%s:OYA Ryari: a Igikoresho Na:"
+
+#: elf32-hppa.c:1360
+#, fuzzy, c-format
+msgid "%s: relocation %s should not be used when making a shared object; recompile with -fPIC"
+msgstr "%s:OYA Ryari: a Igikoresho Na:"
+
+#: elf32-hppa.c:1553
+#, fuzzy, c-format
+msgid "Could not find relocation section for %s"
+msgstr "OYA Gushaka Icyiciro kugirango"
+
+#: elf32-hppa.c:2828
+#, fuzzy, c-format
+msgid "%s: duplicate export stub %s"
+msgstr "%s:Gusubiramo Kohereza"
+
+#: elf32-hppa.c:3416
+#, c-format
+msgid "%s(%s+0x%lx): fixing %s"
+msgstr ""
+
+#: elf32-hppa.c:4039
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): cannot handle %s for %s"
+msgstr "%s(%s+0x%lx):kugirango"
+
+#: elf32-hppa.c:4357
+#, fuzzy
+msgid ".got section not immediately after .plt section"
+msgstr ""
+".Project- Id- Version: basctl\n"
+"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n"
+"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n"
+"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n"
+"Content- Type: text/ plain; charset= UTF- 8\n"
+"Content- Transfer- Encoding: 8bit\n"
+"X- Generator: KBabel 1. 0\n"
+"."
+
+#: elf32-i386.c:326
+#, fuzzy, c-format
+msgid "%s: invalid relocation type %d"
+msgstr "%s:Sibyo Ubwoko"
+
+#: elf32-i386.c:841 elf32-s390.c:990 elf32-sparc.c:887 elf32-xtensa.c:637
+#: elf64-s390.c:943 elf64-x86-64.c:650
+#, fuzzy, c-format
+msgid "%s: bad symbol index: %d"
+msgstr "%s:IKIMENYETSO Umubarendanga"
+
+#: elf32-i386.c:949 elf32-s390.c:1168 elf32-sh.c:6426 elf32-sparc.c:1011
+#: elf64-s390.c:1129
+#, fuzzy, c-format
+msgid "%s: `%s' accessed both as normal and thread local symbol"
+msgstr "%s:`%s'birabonetse Byombi Nka Bisanzwe Na Urudodo IKIMENYETSO"
+
+#: elf32-i386.c:1064 elf32-s390.c:1279 elf64-ppc.c:3929 elf64-s390.c:1243
+#: elf64-x86-64.c:886
+#, fuzzy, c-format
+msgid "%s: bad relocation section name `%s'"
+msgstr "%s:Icyiciro Izina:"
+
+#: elf32-i386.c:2908 elf32-m68k.c:1757 elf32-s390.c:3022 elf32-sparc.c:2879
+#: elf32-xtensa.c:2193 elf64-s390.c:3018 elf64-sparc.c:2664
+#: elf64-x86-64.c:2452
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): unresolvable relocation against symbol `%s'"
+msgstr "%s(%s+0x%lx):IKIMENYETSO"
+
+#: elf32-i386.c:2947 elf32-m68k.c:1796 elf32-s390.c:3072 elf64-s390.c:3068
+#: elf64-x86-64.c:2490
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): reloc against `%s': error %d"
+msgstr "%s(%s+0x%lx):Ikosa"
+
+#: elf32-ip2k.c:565 elf32-ip2k.c:571 elf32-ip2k.c:734 elf32-ip2k.c:740
+#, fuzzy
+msgid "ip2k relaxer: switch table without complete matching relocation information."
+msgstr "Hindura imbonerahamwe# Byuzuye Ibisobanuro"
+
+#: elf32-ip2k.c:588 elf32-ip2k.c:767
+#, fuzzy
+msgid "ip2k relaxer: switch table header corrupt."
+msgstr "Hindura imbonerahamwe# Umutwempangano"
+
+#: elf32-ip2k.c:1395
+#, fuzzy, c-format
+msgid "ip2k linker: missing page instruction at 0x%08lx (dest = 0x%08lx)."
+msgstr "Ibuze Ipaji ku"
+
+#: elf32-ip2k.c:1409
+#, fuzzy, c-format
+msgid "ip2k linker: redundant page instruction at 0x%08lx (dest = 0x%08lx)."
+msgstr "Ipaji ku"
+
+#. Only if it's not an unresolved symbol.
+#: elf32-ip2k.c:1593
+#, fuzzy
+msgid "unsupported relocation between data/insn address spaces"
+msgstr "hagati Ibyatanzwe Aderesi Imyanya"
+
+#: elf32-iq2000.c:907 elf32-m68hc1x.c:1431 elf32-ppc.c:2175 elf64-sparc.c:3072
+#: elfxx-mips.c:9195
+#, fuzzy, c-format
+msgid "%s: uses different e_flags (0x%lx) fields than previous modules (0x%lx)"
+msgstr "%s:Imyanya Ibanjirije Modire"
+
+#: elf32-m32r.c:930
+#, fuzzy
+msgid "SDA relocation when _SDA_BASE_ not defined"
+msgstr "Ryari: OYA"
+
+#: elf32-m32r.c:1018 elf64-alpha.c:4279 elf64-alpha.c:4407 elf32-ia64.c:3958
+#: elf64-ia64.c:3958
+#, fuzzy, c-format
+msgid "%s: unknown relocation type %d"
+msgstr "%s:Kitazwi Ubwoko"
+
+#: elf32-m32r.c:1226
+#, fuzzy, c-format
+msgid "%s: The target (%s) of an %s relocation is in the wrong section (%s)"
+msgstr "%s:Intego Bya ni in i Icyiciro"
+
+#: elf32-m32r.c:1952
+#, fuzzy, c-format
+msgid "%s: Instruction set mismatch with previous modules"
+msgstr "%s:Gushyiraho Na: Ibanjirije Modire"
+
+#: elf32-m32r.c:1975
+#, fuzzy, c-format
+msgid "private flags = %lx"
+msgstr "By'umwihariko Amabendera"
+
+#: elf32-m32r.c:1980
+#, fuzzy
+msgid ": m32r instructions"
+msgstr ":Amabwiriza"
+
+#: elf32-m32r.c:1981
+#, fuzzy
+msgid ": m32rx instructions"
+msgstr ":Amabwiriza"
+
+#: elf32-m68hc1x.c:1217
+#, fuzzy, c-format
+msgid "Reference to the far symbol `%s' using a wrong relocation may result in incorrect execution"
+msgstr "Kuri i IKIMENYETSO ikoresha a Gicurasi Igisubizo in"
+
+#: elf32-m68hc1x.c:1240
+#, fuzzy, c-format
+msgid "banked address [%lx:%04lx] (%lx) is not in the same bank as current banked address [%lx:%04lx] (%lx)"
+msgstr "Aderesi ni OYA in i Nka KIGEZWEHO Aderesi"
+
+#: elf32-m68hc1x.c:1259
+#, fuzzy, c-format
+msgid "reference to a banked address [%lx:%04lx] in the normal address space at %04lx"
+msgstr "Indango Kuri a Aderesi in i Bisanzwe Aderesi Umwanya ku"
+
+#: elf32-m68hc1x.c:1396
+#, fuzzy, c-format
+msgid "%s: linking files compiled for 16-bit integers (-mshort) and others for 32-bit integers"
+msgstr "%s:Impuza Idosiye kugirango Na Ibindi kugirango"
+
+#: elf32-m68hc1x.c:1404
+#, fuzzy, c-format
+msgid "%s: linking files compiled for 32-bit double (-fshort-double) and others for 64-bit double"
+msgstr "%s:Impuza Idosiye kugirango MAHARAKUBIRI MAHARAKUBIRI Na Ibindi kugirango MAHARAKUBIRI"
+
+#: elf32-m68hc1x.c:1414
+#, fuzzy, c-format
+msgid "%s: linking files compiled for HCS12 with others compiled for HC12"
+msgstr "%s:Impuza Idosiye kugirango Na: Ibindi kugirango"
+
+#: elf32-m68hc1x.c:1462
+#, fuzzy
+msgid "[abi=32-bit int, "
+msgstr "[INT"
+
+#: elf32-m68hc1x.c:1464
+#, fuzzy
+msgid "[abi=16-bit int, "
+msgstr "[INT"
+
+#: elf32-m68hc1x.c:1467
+#, fuzzy
+msgid "64-bit double, "
+msgstr "MAHARAKUBIRI"
+
+#: elf32-m68hc1x.c:1469
+#, fuzzy
+msgid "32-bit double, "
+msgstr "MAHARAKUBIRI"
+
+#: elf32-m68hc1x.c:1472
+#, fuzzy
+msgid "cpu=HC11]"
+msgstr "CPU"
+
+#: elf32-m68hc1x.c:1474
+#, fuzzy
+msgid "cpu=HCS12]"
+msgstr "CPU"
+
+#: elf32-m68hc1x.c:1476
+#, fuzzy
+msgid "cpu=HC12]"
+msgstr "CPU"
+
+#: elf32-m68hc1x.c:1479
+#, fuzzy
+msgid " [memory=bank-model]"
+msgstr "[Ububiko Urugero"
+
+#: elf32-m68hc1x.c:1481
+#, fuzzy
+msgid " [memory=flat]"
+msgstr "[Ububiko Kirambuye"
+
+#: elf32-m68k.c:400
+msgid " [cpu32]"
+msgstr ""
+
+#: elf32-m68k.c:403
+msgid " [m68000]"
+msgstr ""
+
+#: elf32-mcore.c:353 elf32-mcore.c:456
+#, fuzzy, c-format
+msgid "%s: Relocation %s (%d) is not currently supported.\n"
+msgstr "%s:ni OYA"
+
+#: elf32-mcore.c:441
+#, fuzzy, c-format
+msgid "%s: Unknown relocation type %d\n"
+msgstr "%s:Ubwoko"
+
+#: elf32-mips.c:1170 elf64-mips.c:1717 elfn32-mips.c:1664
+#, fuzzy
+msgid "32bits gp relative relocation occurs for an external symbol"
+msgstr "Bifitanye isano kugirango external IKIMENYETSO"
+
+#: elf32-mips.c:1314 elf64-mips.c:1830 elfn32-mips.c:1783
+#, fuzzy, c-format
+msgid "Linking mips16 objects into %s format is not supported"
+msgstr "Ibintu Imiterere ni OYA"
+
+#: elf32-ppc.c:2056
+#, fuzzy, c-format
+msgid "generic linker can't handle %s"
+msgstr "Gifitanye isano"
+
+#: elf32-ppc.c:2138
+#, fuzzy, c-format
+msgid "%s: compiled with -mrelocatable and linked with modules compiled normally"
+msgstr "%s:Na: Na Na: Modire"
+
+#: elf32-ppc.c:2147
+#, fuzzy, c-format
+msgid "%s: compiled normally and linked with modules compiled with -mrelocatable"
+msgstr "%s:Na Na: Modire Na:"
+
+#: elf32-ppc.c:3413
+#, fuzzy, c-format
+msgid "%s: relocation %s cannot be used when making a shared object"
+msgstr "%s:Ryari: a Igikoresho"
+
+#. It does not make sense to have a procedure linkage
+#. table entry for a local symbol.
+#: elf32-ppc.c:3619
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): %s reloc against local symbol"
+msgstr "%s(%s+0x%lx):%sIKIMENYETSO"
+
+#: elf32-ppc.c:4862 elf64-ppc.c:7789
+#, fuzzy, c-format
+msgid "%s: unknown relocation type %d for symbol %s"
+msgstr "%s:Kitazwi Ubwoko kugirango IKIMENYETSO"
+
+#: elf32-ppc.c:5113
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): non-zero addend on %s reloc against `%s'"
+msgstr "%s(%s+0x%lx):Zeru ku"
+
+#: elf32-ppc.c:5399 elf32-ppc.c:5425 elf32-ppc.c:5484
+#, fuzzy, c-format
+msgid "%s: the target (%s) of a %s relocation is in the wrong output section (%s)"
+msgstr "%s:i Intego Bya a ni in i Ibisohoka Icyiciro"
+
+#: elf32-ppc.c:5539
+#, fuzzy, c-format
+msgid "%s: relocation %s is not yet supported for symbol %s."
+msgstr "%s:ni OYA kugirango IKIMENYETSO"
+
+#: elf32-ppc.c:5594 elf64-ppc.c:8461
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): unresolvable %s relocation against symbol `%s'"
+msgstr "%s(%s+0x%lx):IKIMENYETSO"
+
+#: elf32-ppc.c:5644 elf64-ppc.c:8507
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): %s reloc against `%s': error %d"
+msgstr "%s(%s+0x%lx):%sIkosa"
+
+#: elf32-ppc.c:5888
+#, fuzzy, c-format
+msgid "corrupt or empty %s section in %s"
+msgstr "Cyangwa ubusa Icyiciro in"
+
+#: elf32-ppc.c:5895
+#, fuzzy, c-format
+msgid "unable to read in %s section from %s"
+msgstr "Kuri Gusoma in Icyiciro Bivuye"
+
+#: elf32-ppc.c:5901
+#, fuzzy, c-format
+msgid "corrupt %s section in %s"
+msgstr "Icyiciro in"
+
+#: elf32-ppc.c:5944
+#, fuzzy, c-format
+msgid "warning: unable to set size of %s section in %s"
+msgstr "Iburira Kuri Gushyiraho Ingano Bya Icyiciro in"
+
+#: elf32-ppc.c:5994
+#, fuzzy
+msgid "failed to allocate space for new APUinfo section."
+msgstr "Byanze Kuri Umwanya kugirango Gishya Icyiciro"
+
+#: elf32-ppc.c:6013
+#, fuzzy
+msgid "failed to compute new APUinfo section."
+msgstr "Byanze Kuri Gishya Icyiciro"
+
+#: elf32-ppc.c:6016
+#, fuzzy
+msgid "failed to install new APUinfo section."
+msgstr "Byanze Kuri Kwinjiza porogaramu Gishya Icyiciro"
+
+#: elf32-s390.c:2256 elf64-s390.c:2226
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): invalid instruction for TLS relocation %s"
+msgstr "%s(%s+0x%lx):Sibyo kugirango"
+
+#: elf32-sh.c:2103
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: bad R_SH_USES offset"
+msgstr "%s:Iburira Nta- boneza"
+
+#: elf32-sh.c:2115
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x"
+msgstr "%s:Iburira Utudomo Kuri"
+
+#: elf32-sh.c:2132
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: bad R_SH_USES load offset"
+msgstr "%s:Iburira Ibirimo Nta- boneza"
+
+#: elf32-sh.c:2147
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: could not find expected reloc"
+msgstr "%s:Iburira OYA Gushaka Ikitezwe:"
+
+#: elf32-sh.c:2175
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: symbol in unexpected section"
+msgstr "%s:Iburira IKIMENYETSO in Icyiciro"
+
+#: elf32-sh.c:2300
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: could not find expected COUNT reloc"
+msgstr "%s:Iburira OYA Gushaka Ikitezwe:"
+
+#: elf32-sh.c:2309
+#, fuzzy, c-format
+msgid "%s: 0x%lx: warning: bad count"
+msgstr "%s:Iburira IBARA"
+
+#: elf32-sh.c:2712 elf32-sh.c:3088
+#, fuzzy, c-format
+msgid "%s: 0x%lx: fatal: reloc overflow while relaxing"
+msgstr "%s:Byarenze urugero"
+
+#: elf32-sh.c:4654 elf64-sh64.c:1585
+#, fuzzy
+msgid "Unexpected STO_SH5_ISA32 on local symbol is not handled"
+msgstr "ku IKIMENYETSO ni OYA"
+
+#: elf32-sh.c:4809
+#, fuzzy, c-format
+msgid "%s: unresolvable relocation against symbol `%s' from %s section"
+msgstr "%s:IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-sh.c:4881
+#, fuzzy, c-format
+msgid "%s: 0x%lx: fatal: unaligned branch target for relax-support relocation"
+msgstr "%s:Intego kugirango Gushigikira"
+
+#: elf32-sh.c:6627 elf64-alpha.c:4848
+#, fuzzy, c-format
+msgid "%s: TLS local exec code cannot be linked into shared objects"
+msgstr "%s:ITEGEKONGENGA Ibintu"
+
+#: elf32-sh64.c:221 elf64-sh64.c:2407
+#, fuzzy, c-format
+msgid "%s: compiled as 32-bit object and %s is 64-bit"
+msgstr "%s:Nka Igikoresho Na ni"
+
+#: elf32-sh64.c:224 elf64-sh64.c:2410
+#, fuzzy, c-format
+msgid "%s: compiled as 64-bit object and %s is 32-bit"
+msgstr "%s:Nka Igikoresho Na ni"
+
+#: elf32-sh64.c:226 elf64-sh64.c:2412
+#, fuzzy, c-format
+msgid "%s: object size does not match that of target %s"
+msgstr "%s:Igikoresho Ingano OYA BIHUYE Bya Intego"
+
+#: elf32-sh64.c:461 elf64-sh64.c:2990
+#, fuzzy, c-format
+msgid "%s: encountered datalabel symbol in input"
+msgstr "%s:IKIMENYETSO in Iyinjiza"
+
+#: elf32-sh64.c:544
+#, fuzzy
+msgid "PTB mismatch: a SHmedia address (bit 0 == 1)"
+msgstr "a Aderesi 0 1."
+
+#: elf32-sh64.c:547
+#, fuzzy
+msgid "PTA mismatch: a SHcompact address (bit 0 == 0)"
+msgstr "a Aderesi 0 0"
+
+#: elf32-sh64.c:565
+#, fuzzy, c-format
+msgid "%s: GAS error: unexpected PTB insn with R_SH_PT_16"
+msgstr "%s:Ikosa Na:"
+
+#: elf32-sh64.c:614 elf64-sh64.c:1748
+#, fuzzy, c-format
+msgid "%s: error: unaligned relocation type %d at %08x reloc %08x\n"
+msgstr "%s:Ikosa Ubwoko ku"
+
+#: elf32-sh64.c:698
+#, fuzzy, c-format
+msgid "%s: could not write out added .cranges entries"
+msgstr "%s:OYA Kwandika Inyuma Kyongewe Ibyinjijwe"
+
+#: elf32-sh64.c:760
+#, fuzzy, c-format
+msgid "%s: could not write out sorted .cranges entries"
+msgstr "%s:OYA Kwandika Inyuma bishunguwe Ibyinjijwe"
+
+#: elf32-sparc.c:2521 elf64-sparc.c:2314
+#, c-format
+msgid "%s: probably compiled without -fPIC?"
+msgstr ""
+
+#: elf32-sparc.c:3348
+#, fuzzy, c-format
+msgid "%s: compiled for a 64 bit system and target is 32 bit"
+msgstr "%s:kugirango a Sisitemu Na Intego ni"
+
+#: elf32-sparc.c:3362
+#, fuzzy, c-format
+msgid "%s: linking little endian files with big endian files"
+msgstr "%s:Impuza Idosiye Na: Idosiye"
+
+#: elf32-v850.c:753
+#, fuzzy, c-format
+msgid "Variable `%s' cannot occupy in multiple small data regions"
+msgstr "in Igikubo Gitoya Ibyatanzwe"
+
+#: elf32-v850.c:756
+#, fuzzy, c-format
+msgid "Variable `%s' can only be in one of the small, zero, and tiny data regions"
+msgstr "in Bya i Gitoya Zeru Na Bito Ibyatanzwe"
+
+#: elf32-v850.c:759
+#, fuzzy, c-format
+msgid "Variable `%s' cannot be in both small and zero data regions simultaneously"
+msgstr "in Byombi Gitoya Na Zeru Ibyatanzwe"
+
+#: elf32-v850.c:762
+#, fuzzy, c-format
+msgid "Variable `%s' cannot be in both small and tiny data regions simultaneously"
+msgstr "in Byombi Gitoya Na Bito Ibyatanzwe"
+
+#: elf32-v850.c:765
+#, fuzzy, c-format
+msgid "Variable `%s' cannot be in both zero and tiny data regions simultaneously"
+msgstr "in Byombi Zeru Na Bito Ibyatanzwe"
+
+#: elf32-v850.c:1144
+#, fuzzy
+msgid "FAILED to find previous HI16 reloc\n"
+msgstr "Kuri Gushaka Ibanjirije"
+
+#: elf32-v850.c:1789
+#, fuzzy
+msgid "could not locate special linker symbol __gp"
+msgstr "OYA Bidasanzwe IKIMENYETSO"
+
+#: elf32-v850.c:1793
+#, fuzzy
+msgid "could not locate special linker symbol __ep"
+msgstr "OYA Bidasanzwe IKIMENYETSO"
+
+#: elf32-v850.c:1797
+#, fuzzy
+msgid "could not locate special linker symbol __ctbp"
+msgstr "OYA Bidasanzwe IKIMENYETSO"
+
+#: elf32-v850.c:1963
+#, fuzzy, c-format
+msgid "%s: Architecture mismatch with previous modules"
+msgstr "%s:Na: Ibanjirije Modire"
+
+#: elf32-v850.c:1983
+#, fuzzy, c-format
+msgid "private flags = %lx: "
+msgstr "By'umwihariko Amabendera"
+
+#: elf32-v850.c:1988
+msgid "v850 architecture"
+msgstr ""
+
+#: elf32-v850.c:1989
+msgid "v850e architecture"
+msgstr ""
+
+#: elf32-vax.c:549
+msgid " [nonpic]"
+msgstr ""
+
+#: elf32-vax.c:552
+#, fuzzy
+msgid " [d-float]"
+msgstr "[D Kureremba"
+
+#: elf32-vax.c:555
+#, fuzzy
+msgid " [g-float]"
+msgstr "[g Kureremba"
+
+#: elf32-vax.c:663
+#, fuzzy, c-format
+msgid "%s: warning: GOT addend of %ld to `%s' does not match previous GOT addend of %ld"
+msgstr "%s:Iburira Bya Kuri OYA BIHUYE Ibanjirije Bya"
+
+#: elf32-vax.c:1667
+#, fuzzy, c-format
+msgid "%s: warning: PLT addend of %d to `%s' from %s section ignored"
+msgstr "%s:Iburira Bya Kuri Bivuye Icyiciro"
+
+#: elf32-vax.c:1802
+#, fuzzy, c-format
+msgid "%s: warning: %s relocation against symbol `%s' from %s section"
+msgstr "%s:Iburira IKIMENYETSO Bivuye Icyiciro"
+
+#: elf32-vax.c:1808
+#, fuzzy, c-format
+msgid "%s: warning: %s relocation to 0x%x from %s section"
+msgstr "%s:Iburira Kuri Bivuye Icyiciro"
+
+#: elf32-xstormy16.c:462 elf32-ia64.c:2450 elf64-ia64.c:2450
+#, fuzzy
+msgid "non-zero addend in @fptr reloc"
+msgstr "Zeru in"
+
+#: elf64-alpha.c:1108
+#, fuzzy
+msgid "GPDISP relocation did not find ldah and lda instructions"
+msgstr "OYA Gushaka Na Amabwiriza"
+
+#: elf64-alpha.c:3731
+#, fuzzy, c-format
+msgid "%s: .got subsegment exceeds 64K (size %d)"
+msgstr ""
+"%s:.Project- Id- Version: basctl\n"
+"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n"
+"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n"
+"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n"
+"Content- Type: text/ plain; charset= UTF- 8\n"
+"Content- Transfer- Encoding: 8bit\n"
+"X- Generator: KBabel 1. 0\n"
+"."
+
+#: elf64-alpha.c:4602 elf64-alpha.c:4614
+#, fuzzy, c-format
+msgid "%s: gp-relative relocation against dynamic symbol %s"
+msgstr "%s:Bifitanye isano IKIMENYETSO"
+
+#: elf64-alpha.c:4640 elf64-alpha.c:4773
+#, fuzzy, c-format
+msgid "%s: pc-relative relocation against dynamic symbol %s"
+msgstr "%s:Bifitanye isano IKIMENYETSO"
+
+#: elf64-alpha.c:4668
+#, fuzzy, c-format
+msgid "%s: change in gp: BRSGP %s"
+msgstr "%s:Guhindura>> in"
+
+#: elf64-alpha.c:4693
+#, fuzzy
+msgid "<unknown>"
+msgstr "<Itazwi>"
+
+#: elf64-alpha.c:4698
+#, fuzzy, c-format
+msgid "%s: !samegp reloc against symbol without .prologue: %s"
+msgstr "%s:!IKIMENYETSO"
+
+#: elf64-alpha.c:4749
+#, c-format
+msgid "%s: unhandled dynamic relocation against %s"
+msgstr ""
+
+#: elf64-alpha.c:4832
+#, fuzzy, c-format
+msgid "%s: dtp-relative relocation against dynamic symbol %s"
+msgstr "%s:Bifitanye isano IKIMENYETSO"
+
+#: elf64-alpha.c:4855
+#, fuzzy, c-format
+msgid "%s: tp-relative relocation against dynamic symbol %s"
+msgstr "%s:Bifitanye isano IKIMENYETSO"
+
+#: elf64-hppa.c:2086
+#, fuzzy, c-format
+msgid "stub entry for %s cannot load .plt, dp offset = %ld"
+msgstr "Icyinjijwe kugirango Ibirimo Nta- boneza"
+
+#: elf64-mmix.c:1032
+#, fuzzy, c-format
+msgid ""
+"%s: Internal inconsistency error for value for\n"
+" linker-allocated global register: linked: 0x%lx%08lx != relaxed: 0x%lx%08lx\n"
+msgstr "%s:Ikosa kugirango Agaciro Kwiyandikisha"
+
+#: elf64-mmix.c:1416
+#, fuzzy, c-format
+msgid "%s: base-plus-offset relocation against register symbol: (unknown) in %s"
+msgstr "%s:SHINGIRO Guteranya Nta- boneza Kwiyandikisha IKIMENYETSO Kitazwi in"
+
+#: elf64-mmix.c:1421
+#, fuzzy, c-format
+msgid "%s: base-plus-offset relocation against register symbol: %s in %s"
+msgstr "%s:SHINGIRO Guteranya Nta- boneza Kwiyandikisha IKIMENYETSO in"
+
+#: elf64-mmix.c:1465
+#, fuzzy, c-format
+msgid "%s: register relocation against non-register symbol: (unknown) in %s"
+msgstr "%s:Kwiyandikisha Kwiyandikisha IKIMENYETSO Kitazwi in"
+
+#: elf64-mmix.c:1470
+#, fuzzy, c-format
+msgid "%s: register relocation against non-register symbol: %s in %s"
+msgstr "%s:Kwiyandikisha Kwiyandikisha IKIMENYETSO in"
+
+#: elf64-mmix.c:1507
+#, fuzzy, c-format
+msgid "%s: directive LOCAL valid only with a register or absolute value"
+msgstr "%s:Byemewe Na: a Kwiyandikisha Cyangwa Agaciro"
+
+#: elf64-mmix.c:1535
+#, fuzzy, c-format
+msgid "%s: LOCAL directive: Register $%ld is not a local register.  First global register is $%ld."
+msgstr "%s:ni OYA a Kwiyandikisha Kwiyandikisha ni"
+
+#: elf64-mmix.c:1994
+#, fuzzy, c-format
+msgid "%s: Error: multiple definition of `%s'; start of %s is set in a earlier linked file\n"
+msgstr "%s:Igikubo Insobanuro Bya Gutangira Bya ni Gushyiraho in a"
+
+#: elf64-mmix.c:2053
+#, fuzzy
+msgid "Register section has contents\n"
+msgstr "Icyiciro"
+
+#: elf64-mmix.c:2216
+#, fuzzy, c-format
+msgid ""
+"Internal inconsistency: remaining %u != max %u.\n"
+"  Please report this bug."
+msgstr "KININI Icyegeranyo iyi"
+
+#: elf64-ppc.c:2388 libbfd.c:831
+#, fuzzy, c-format
+msgid "%s: compiled for a big endian system and target is little endian"
+msgstr "%s:kugirango a Sisitemu Na Intego ni"
+
+#: elf64-ppc.c:2391 libbfd.c:833
+#, fuzzy, c-format
+msgid "%s: compiled for a little endian system and target is big endian"
+msgstr "%s:kugirango a Sisitemu Na Intego ni"
+
+#: elf64-ppc.c:4857
+#, fuzzy, c-format
+msgid "%s: unexpected reloc type %u in .opd section"
+msgstr "%s:Ubwoko in Icyiciro"
+
+#: elf64-ppc.c:4877
+#, fuzzy, c-format
+msgid "%s: .opd is not a regular array of opd entries"
+msgstr ""
+"%s:.Project- Id- Version: basctl\n"
+"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n"
+"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n"
+"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n"
+"Content- Type: text/ plain; charset= UTF- 8\n"
+"Content- Transfer- Encoding: 8bit\n"
+"X- Generator: KBabel 1. 0\n"
+"."
+
+#: elf64-ppc.c:4897
+#, fuzzy, c-format
+msgid "%s: undefined sym `%s' in .opd section"
+msgstr "%s:kidasobanuye in Icyiciro"
+
+#: elf64-ppc.c:6136
+#, fuzzy, c-format
+msgid "can't find branch stub `%s'"
+msgstr "Gushaka"
+
+#: elf64-ppc.c:6175 elf64-ppc.c:6250
+#, fuzzy, c-format
+msgid "linkage table error against `%s'"
+msgstr "imbonerahamwe# Ikosa"
+
+#: elf64-ppc.c:6340
+#, c-format
+msgid "can't build branch stub `%s'"
+msgstr ""
+
+#: elf64-ppc.c:7047
+#, fuzzy
+msgid ".glink and .plt too far apart"
+msgstr ""
+".Project- Id- Version: basctl\n"
+"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n"
+"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n"
+"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n"
+"Content- Type: text/ plain; charset= UTF- 8\n"
+"Content- Transfer- Encoding: 8bit\n"
+"X- Generator: KBabel 1. 0\n"
+"."
+
+#: elf64-ppc.c:7135
+#, fuzzy
+msgid "stubs don't match calculated size"
+msgstr "BIHUYE Ingano"
+
+#: elf64-ppc.c:7147
+#, fuzzy, c-format
+msgid ""
+"linker stubs in %u groups\n"
+"  branch       %lu\n"
+"  toc adjust   %lu\n"
+"  long branch  %lu\n"
+"  long toc adj %lu\n"
+"  plt call     %lu"
+msgstr "in"
+
+#: elf64-ppc.c:7723
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): automatic multiple TOCs not supported using your crt files; recompile with -mminimal-toc or upgrade gcc"
+msgstr "%s(%s+0x%lx):Byikoresha Igikubo OYA ikoresha Idosiye Na: Cyangwa"
+
+#: elf64-ppc.c:7731
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): sibling call optimization to `%s' does not allow automatic multiple TOCs; recompile with -mminimal-toc or -fno-optimize-sibling-calls, or make `%s' extern"
+msgstr "%s(%s+0x%lx):Kuri OYA Kwemerera Byikoresha Igikubo Na: Cyangwa Kugeza ku ndunduro Amahamagara: Cyangwa Ubwoko"
+
+#: elf64-ppc.c:8329
+#, fuzzy, c-format
+msgid "%s: relocation %s is not supported for symbol %s."
+msgstr "%s:ni OYA kugirango IKIMENYETSO"
+
+#: elf64-ppc.c:8408
+#, fuzzy, c-format
+msgid "%s: error: relocation %s not a multiple of %d"
+msgstr "%s:Ikosa OYA a Igikubo Bya"
+
+#: elf64-sparc.c:1370
+#, fuzzy, c-format
+msgid "%s: check_relocs: unhandled reloc type %d"
+msgstr "%s:Ubwoko"
+
+#: elf64-sparc.c:1407
+#, fuzzy, c-format
+msgid "%s: Only registers %%g[2367] can be declared using STT_REGISTER"
+msgstr "%s:ikoresha"
+
+#: elf64-sparc.c:1427
+#, fuzzy, c-format
+msgid "Register %%g%d used incompatibly: %s in %s, previously %s in %s"
+msgstr "in in"
+
+#: elf64-sparc.c:1450
+#, fuzzy, c-format
+msgid "Symbol `%s' has differing types: REGISTER in %s, previously %s in %s"
+msgstr "in in"
+
+#: elf64-sparc.c:1496
+#, fuzzy, c-format
+msgid "Symbol `%s' has differing types: %s in %s, previously REGISTER in %s"
+msgstr "in in"
+
+#: elf64-sparc.c:3053
+#, fuzzy, c-format
+msgid "%s: linking UltraSPARC specific with HAL specific code"
+msgstr "%s:Impuza Na: ITEGEKONGENGA"
+
+#: elf64-x86-64.c:739
+#, fuzzy, c-format
+msgid "%s: %s' accessed both as normal and thread local symbol"
+msgstr "%s:%s'birabonetse Byombi Nka Bisanzwe Na Urudodo IKIMENYETSO"
+
+#: elfcode.h:1113
+#, fuzzy, c-format
+msgid "%s: version count (%ld) does not match symbol count (%ld)"
+msgstr "%s:Verisiyo IBARA OYA BIHUYE IKIMENYETSO IBARA"
+
+#: elfcode.h:1342
+#, fuzzy, c-format
+msgid "%s(%s): relocation %d has invalid symbol index %ld"
+msgstr "%s(%s):Sibyo IKIMENYETSO Umubarendanga"
+
+#: elflink.c:1456
+#, fuzzy, c-format
+msgid "%s: warning: unexpected redefinition of indirect versioned symbol `%s'"
+msgstr "%s:Iburira Bya BUZIGUYE IKIMENYETSO"
+
+#: elflink.c:1807
+#, fuzzy, c-format
+msgid "%s: undefined versioned symbol name %s"
+msgstr "%s:kidasobanuye IKIMENYETSO Izina:"
+
+#: elflink.c:2142
+#, fuzzy, c-format
+msgid "%s: relocation size mismatch in %s section %s"
+msgstr "%s:Ingano in Icyiciro"
+
+#: elflink.c:2434
+#, fuzzy, c-format
+msgid "warning: type and size of dynamic symbol `%s' are not defined"
+msgstr "Iburira Ubwoko Na Ingano Bya IKIMENYETSO OYA"
+
+#: elflink.h:1022
+#, fuzzy, c-format
+msgid "%s: %s: invalid version %u (max %d)"
+msgstr "%s:%s:Sibyo Verisiyo KININI"
+
+#: elflink.h:1063
+#, fuzzy, c-format
+msgid "%s: %s: invalid needed version %d"
+msgstr "%s:%s:Sibyo Verisiyo"
+
+#: elflink.h:1238
+#, fuzzy, c-format
+msgid "Warning: alignment %u of symbol `%s' in %s is smaller than %u in %s"
+msgstr "Itunganya Bya IKIMENYETSO in ni Gitoya in"
+
+#: elflink.h:1252
+#, fuzzy, c-format
+msgid "Warning: size of symbol `%s' changed from %lu in %s to %lu in %s"
+msgstr "Ingano Bya IKIMENYETSO Byahinduwe Bivuye in Kuri in"
+
+#: elflink.h:2160
+#, fuzzy, c-format
+msgid "%s: undefined version: %s"
+msgstr "%s:kidasobanuye Verisiyo"
+
+#: elflink.h:2226
+#, fuzzy, c-format
+msgid "%s: .preinit_array section is not allowed in DSO"
+msgstr ""
+"%s:.Project- Id- Version: basctl\n"
+"POT- Creation- Date: 2003- 12- 07 17: 13+ 02\n"
+"PO- Revision- Date: 2004- 11- 04 10: 13- 0700\n"
+"Last- Translator: Language- Team:< en@ li. org> MIME- Version: 1. 0\n"
+"Content- Type: text/ plain; charset= UTF- 8\n"
+"Content- Transfer- Encoding: 8bit\n"
+"X- Generator: KBabel 1. 0\n"
+"."
+
+#: elflink.h:3078
+#, fuzzy
+msgid "Not enough memory to sort relocations"
+msgstr "Ububiko Kuri Ishungura"
+
+#: elflink.h:3958 elflink.h:4001
+#, fuzzy, c-format
+msgid "%s: could not find output section %s"
+msgstr "%s:OYA Gushaka Ibisohoka Icyiciro"
+
+#: elflink.h:3964
+#, fuzzy, c-format
+msgid "warning: %s section has zero size"
+msgstr "Iburira Icyiciro Zeru Ingano"
+
+#: elflink.h:4483
+#, fuzzy, c-format
+msgid "%s: %s symbol `%s' in %s is referenced by DSO"
+msgstr "%s:%sIKIMENYETSO in ni ku"
+
+#: elflink.h:4564
+#, fuzzy, c-format
+msgid "%s: could not find output section %s for input section %s"
+msgstr "%s:OYA Gushaka Ibisohoka Icyiciro kugirango Iyinjiza Icyiciro"
+
+#: elflink.h:4666
+#, fuzzy, c-format
+msgid "%s: %s symbol `%s' isn't defined"
+msgstr "%s:%sIKIMENYETSO si"
+
+#: elflink.h:5053 elflink.h:5095
+#, fuzzy
+msgid "%T: discarded in section `%s' from %s\n"
+msgstr "%T:in Icyiciro Bivuye"
+
+#: elfxx-mips.c:887
+#, fuzzy
+msgid "static procedure (no name)"
+msgstr "Oya Izina:"
+
+#: elfxx-mips.c:1897
+#, fuzzy
+msgid "not enough GOT space for local GOT entries"
+msgstr "OYA Umwanya kugirango Ibyinjijwe"
+
+#: elfxx-mips.c:3691
+#, fuzzy, c-format
+msgid "%s: %s+0x%lx: jump to stub routine which is not jal"
+msgstr "%s:%s+0x%lx:Simbuka Kuri ni OYA"
+
+#: elfxx-mips.c:5192
+#, fuzzy, c-format
+msgid "%s: Malformed reloc detected for section %s"
+msgstr "%s:kugirango Icyiciro"
+
+#: elfxx-mips.c:5266
+#, fuzzy, c-format
+msgid "%s: CALL16 reloc at 0x%lx not against global symbol"
+msgstr "%s:ku OYA IKIMENYETSO"
+
+#: elfxx-mips.c:8692
+#, fuzzy, c-format
+msgid "%s: illegal section name `%s'"
+msgstr "%s:Icyiciro Izina:"
+
+#: elfxx-mips.c:9025
+#, fuzzy, c-format
+msgid "%s: endianness incompatible with that of the selected emulation"
+msgstr "%s:Na: Bya i Byahiswemo"
+
+#: elfxx-mips.c:9037
+#, fuzzy, c-format
+msgid "%s: ABI is incompatible with that of the selected emulation"
+msgstr "%s:ni Na: Bya i Byahiswemo"
+
+#: elfxx-mips.c:9104
+#, fuzzy, c-format
+msgid "%s: warning: linking PIC files with non-PIC files"
+msgstr "%s:Iburira Impuza Idosiye Na: Idosiye"
+
+#: elfxx-mips.c:9121
+#, fuzzy, c-format
+msgid "%s: linking 32-bit code with 64-bit code"
+msgstr "%s:Impuza ITEGEKONGENGA Na: ITEGEKONGENGA"
+
+#: elfxx-mips.c:9149
+#, fuzzy, c-format
+msgid "%s: linking %s module with previous %s modules"
+msgstr "%s:Impuza Modire Na: Ibanjirije Modire"
+
+#: elfxx-mips.c:9172
+#, fuzzy, c-format
+msgid "%s: ABI mismatch: linking %s module with previous %s modules"
+msgstr "%s:Impuza Modire Na: Ibanjirije Modire"
+
+#: elfxx-mips.c:9241
+msgid " [abi=O32]"
+msgstr ""
+
+#: elfxx-mips.c:9243
+msgid " [abi=O64]"
+msgstr ""
+
+#: elfxx-mips.c:9245
+msgid " [abi=EABI32]"
+msgstr ""
+
+#: elfxx-mips.c:9247
+msgid " [abi=EABI64]"
+msgstr ""
+
+#: elfxx-mips.c:9249
+#, fuzzy
+msgid " [abi unknown]"
+msgstr "[Kitazwi"
+
+#: elfxx-mips.c:9251
+msgid " [abi=N32]"
+msgstr ""
+
+#: elfxx-mips.c:9253
+msgid " [abi=64]"
+msgstr ""
+
+#: elfxx-mips.c:9255
+#, fuzzy
+msgid " [no abi set]"
+msgstr "[Oya Gushyiraho"
+
+#: elfxx-mips.c:9258
+msgid " [mips1]"
+msgstr ""
+
+#: elfxx-mips.c:9260
+msgid " [mips2]"
+msgstr ""
+
+#: elfxx-mips.c:9262
+msgid " [mips3]"
+msgstr ""
+
+#: elfxx-mips.c:9264
+msgid " [mips4]"
+msgstr ""
+
+#: elfxx-mips.c:9266
+msgid " [mips5]"
+msgstr ""
+
+#: elfxx-mips.c:9268
+msgid " [mips32]"
+msgstr ""
+
+#: elfxx-mips.c:9270
+msgid " [mips64]"
+msgstr ""
+
+#: elfxx-mips.c:9272
+msgid " [mips32r2]"
+msgstr ""
+
+#: elfxx-mips.c:9274
+#, fuzzy
+msgid " [unknown ISA]"
+msgstr "[Kitazwi"
+
+#: elfxx-mips.c:9277
+msgid " [mdmx]"
+msgstr ""
+
+#: elfxx-mips.c:9280
+msgid " [mips16]"
+msgstr ""
+
+#: elfxx-mips.c:9283
+msgid " [32bitmode]"
+msgstr ""
+
+#: elfxx-mips.c:9285
+#, fuzzy
+msgid " [not 32bitmode]"
+msgstr "[OYA"
+
+#: i386linux.c:457 m68klinux.c:461 sparclinux.c:458
+#, fuzzy, c-format
+msgid "Output file requires shared library `%s'\n"
+msgstr "IDOSIYE Isomero"
+
+#: i386linux.c:465 m68klinux.c:469 sparclinux.c:466
+#, fuzzy, c-format
+msgid "Output file requires shared library `%s.so.%s'\n"
+msgstr "IDOSIYE Isomero"
+
+#: i386linux.c:654 i386linux.c:704 m68klinux.c:661 m68klinux.c:709
+#: sparclinux.c:656 sparclinux.c:706
+#, fuzzy, c-format
+msgid "Symbol %s not defined for fixups\n"
+msgstr "OYA kugirango"
+
+#: i386linux.c:728 m68klinux.c:733 sparclinux.c:730
+#, fuzzy
+msgid "Warning: fixup count mismatch\n"
+msgstr "IBARA"
+
+#: ieee.c:293
+#, fuzzy, c-format
+msgid "%s: string too long (%d chars, max 65535)"
+msgstr "%s:Ikurikiranyanyuguti KININI"
+
+#: ieee.c:428
+#, fuzzy, c-format
+msgid "%s: unrecognized symbol `%s' flags 0x%x"
+msgstr "%s:IKIMENYETSO Amabendera"
+
+#: ieee.c:938
+#, fuzzy, c-format
+msgid "%s: unimplemented ATI record %u for symbol %u"
+msgstr "%s:Icyabitswe kugirango IKIMENYETSO"
+
+#: ieee.c:963
+#, fuzzy, c-format
+msgid "%s: unexpected ATN type %d in external part"
+msgstr "%s:Ubwoko in external"
+
+#: ieee.c:985
+#, fuzzy, c-format
+msgid "%s: unexpected type after ATN"
+msgstr "%s:Ubwoko Nyuma"
+
+#: ihex.c:264
+#, fuzzy, c-format
+msgid "%s:%d: unexpected character `%s' in Intel Hex file\n"
+msgstr "%s:%d:Inyuguti in"
+
+#: ihex.c:372
+#, fuzzy, c-format
+msgid "%s:%u: bad checksum in Intel Hex file (expected %u, found %u)"
+msgstr "%s:%u:in IDOSIYE Ikitezwe: Byabonetse"
+
+#: ihex.c:426
+#, fuzzy, c-format
+msgid "%s:%u: bad extended address record length in Intel Hex file"
+msgstr "%s:%u:Byongerewe... Aderesi Icyabitswe Uburebure in IDOSIYE"
+
+#: ihex.c:443
+#, fuzzy, c-format
+msgid "%s:%u: bad extended start address length in Intel Hex file"
+msgstr "%s:%u:Byongerewe... Gutangira Aderesi Uburebure in IDOSIYE"
+
+#: ihex.c:460
+#, fuzzy, c-format
+msgid "%s:%u: bad extended linear address record length in Intel Hex file"
+msgstr "%s:%u:Byongerewe... By'umurongo Aderesi Icyabitswe Uburebure in IDOSIYE"
+
+#: ihex.c:477
+#, fuzzy, c-format
+msgid "%s:%u: bad extended linear start address length in Intel Hex file"
+msgstr "%s:%u:Byongerewe... By'umurongo Gutangira Aderesi Uburebure in IDOSIYE"
+
+#: ihex.c:494
+#, fuzzy, c-format
+msgid "%s:%u: unrecognized ihex type %u in Intel Hex file\n"
+msgstr "%s:%u:Ubwoko in"
+
+#: ihex.c:619
+#, fuzzy, c-format
+msgid "%s: internal error in ihex_read_section"
+msgstr "%s:By'imbere Ikosa in"
+
+#: ihex.c:654
+#, fuzzy, c-format
+msgid "%s: bad section length in ihex_read_section"
+msgstr "%s:Icyiciro Uburebure in"
+
+#: ihex.c:872
+#, fuzzy, c-format
+msgid "%s: address 0x%s out of range for Intel Hex file"
+msgstr "%s:Aderesi Inyuma Bya Urutonde kugirango IDOSIYE"
+
+#: libbfd.c:861
+#, fuzzy, c-format
+msgid "Deprecated %s called at %s line %d in %s\n"
+msgstr "ku Umurongo in"
+
+#: libbfd.c:864
+#, c-format
+msgid "Deprecated %s called\n"
+msgstr ""
+
+#: linker.c:1829
+#, fuzzy, c-format
+msgid "%s: indirect symbol `%s' to `%s' is a loop"
+msgstr "%s:BUZIGUYE IKIMENYETSO Kuri ni a"
+
+#: linker.c:2697
+#, fuzzy, c-format
+msgid "Attempt to do relocatable link with %s input and %s output"
+msgstr "Kuri Ihuza Na: Iyinjiza Na Ibisohoka"
+
+#: merge.c:896
+#, fuzzy, c-format
+msgid "%s: access beyond end of merged section (%ld + %ld)"
+msgstr "%s:Impera Bya Icyiciro"
+
+#: mmo.c:503
+#, fuzzy, c-format
+msgid "%s: No core to allocate section name %s\n"
+msgstr "%s:Kuri Icyiciro Izina:"
+
+#: mmo.c:579
+#, fuzzy, c-format
+msgid "%s: No core to allocate a symbol %d bytes long\n"
+msgstr "%s:Kuri a IKIMENYETSO Bayite"
+
+#: mmo.c:1287
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: initialization value for $255 is not `Main'\n"
+msgstr "%s:Sibyo IDOSIYE Agaciro kugirango ni OYA"
+
+#: mmo.c:1433
+#, fuzzy, c-format
+msgid "%s: unsupported wide character sequence 0x%02X 0x%02X after symbol name starting with `%s'\n"
+msgstr "%s:Inyuguti Nyuma IKIMENYETSO Izina: Na:"
+
+#: mmo.c:1674
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: unsupported lopcode `%d'\n"
+msgstr "%s:Sibyo IDOSIYE"
+
+#: mmo.c:1684
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: expected YZ = 1 got YZ = %d for lop_quote\n"
+msgstr "%s:Sibyo IDOSIYE Ikitezwe: 1. kugirango"
+
+#: mmo.c:1720
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_loc\n"
+msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z 1. Cyangwa Z 2. Z kugirango"
+
+#: mmo.c:1766
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: expected z = 1 or z = 2, got z = %d for lop_fixo\n"
+msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z 1. Cyangwa Z 2. Z kugirango"
+
+#: mmo.c:1805
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: expected y = 0, got y = %d for lop_fixrx\n"
+msgstr "%s:Sibyo IDOSIYE Ikitezwe: Y 0 Y kugirango"
+
+#: mmo.c:1814
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: expected z = 16 or z = 24, got z = %d for lop_fixrx\n"
+msgstr "%s:Sibyo IDOSIYE Ikitezwe: Z Cyangwa Z Z kugirango"
+
+#: mmo.c:1837
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: leading byte of operand word must be 0 or 1, got %d for lop_fixrx\n"
+msgstr "%s:Sibyo IDOSIYE Nyobora Bayite Bya ijambo 0 Cyangwa 1. kugirango"
+
+#: mmo.c:1860
+#, fuzzy, c-format
+msgid "%s: cannot allocate file name for file number %d, %d bytes\n"
+msgstr "%s:IDOSIYE Izina: kugirango IDOSIYE Umubare"
+
+#: mmo.c:1880
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: file number %d `%s', was already entered as `%s'\n"
+msgstr "%s:Sibyo IDOSIYE IDOSIYE Umubare Nka"
+
+#: mmo.c:1893
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: file name for number %d was not specified before use\n"
+msgstr "%s:Sibyo IDOSIYE IDOSIYE Izina: kugirango Umubare OYA Mbere"
+
+#: mmo.c:1999
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: fields y and z of lop_stab non-zero, y: %d, z: %d\n"
+msgstr "%s:Sibyo IDOSIYE Imyanya Y Na Z Bya Zeru Y Z"
+
+#: mmo.c:2035
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: lop_end not last item in file\n"
+msgstr "%s:Sibyo IDOSIYE OYA Iheruka Ikintu in"
+
+#: mmo.c:2048
+#, fuzzy, c-format
+msgid "%s: invalid mmo file: YZ of lop_end (%ld) not equal to the number of tetras to the preceding lop_stab (%ld)\n"
+msgstr "%s:Sibyo IDOSIYE Bya OYA bingana Kuri i Umubare Bya Kuri i"
+
+#: mmo.c:2698
+#, fuzzy, c-format
+msgid "%s: invalid symbol table: duplicate symbol `%s'\n"
+msgstr "%s:Sibyo IKIMENYETSO imbonerahamwe# Gusubiramo IKIMENYETSO"
+
+#: mmo.c:2949
+#, fuzzy, c-format
+msgid "%s: Bad symbol definition: `Main' set to %s rather than the start address %s\n"
+msgstr "%s:IKIMENYETSO Insobanuro Gushyiraho Kuri i Gutangira Aderesi"
+
+#: mmo.c:3039
+#, fuzzy, c-format
+msgid "%s: warning: symbol table too large for mmo, larger than 65535 32-bit words: %d.  Only `Main' will be emitted.\n"
+msgstr "%s:Iburira IKIMENYETSO imbonerahamwe# Binini kugirango Kinini Amagambo"
+
+#: mmo.c:3084
+#, fuzzy, c-format
+msgid "%s: internal error, symbol table changed size from %d to %d words\n"
+msgstr "%s:By'imbere Ikosa IKIMENYETSO imbonerahamwe# Byahinduwe Ingano Bivuye Kuri"
+
+#: mmo.c:3139
+#, fuzzy, c-format
+msgid "%s: internal error, internal register section %s had contents\n"
+msgstr "%s:By'imbere Ikosa By'imbere Kwiyandikisha Icyiciro"
+
+#: mmo.c:3191
+#, fuzzy, c-format
+msgid "%s: no initialized registers; section length 0\n"
+msgstr "%s:Oya Icyiciro Uburebure"
+
+#: mmo.c:3197
+#, fuzzy, c-format
+msgid "%s: too many initialized registers; section length %ld\n"
+msgstr "%s:Icyiciro Uburebure"
+
+#: mmo.c:3202
+#, fuzzy, c-format
+msgid "%s: invalid start address for initialized registers of length %ld: 0x%lx%08lx\n"
+msgstr "%s:Sibyo Gutangira Aderesi kugirango Bya Uburebure"
+
+#: oasys.c:1052
+#, fuzzy, c-format
+msgid "%s: can not represent section `%s' in oasys"
+msgstr "%s:OYA Icyiciro in"
+
+#: osf-core.c:137
+#, fuzzy, c-format
+msgid "Unhandled OSF/1 core file section type %d\n"
+msgstr "1. IDOSIYE Icyiciro Ubwoko"
+
+#: pe-mips.c:659
+#, fuzzy, c-format
+msgid "%s: `ld -r' not supported with PE MIPS objects\n"
+msgstr "%s:`OYA Na:"
+
+#. OK, at this point the following variables are set up:
+#. src = VMA of the memory we're fixing up
+#. mem = pointer to memory we're fixing up
+#. val = VMA of what we need to refer to
+#.
+#: pe-mips.c:795
+#, c-format
+msgid "%s: unimplemented %s\n"
+msgstr ""
+
+#: pe-mips.c:821
+#, fuzzy, c-format
+msgid "%s: jump too far away\n"
+msgstr "%s:Simbuka"
+
+#: pe-mips.c:848
+#, fuzzy, c-format
+msgid "%s: bad pair/reflo after refhi\n"
+msgstr "%s:Nyuma"
+
+#. XXX code yet to be written.
+#: peicode.h:787
+#, fuzzy, c-format
+msgid "%s: Unhandled import type; %x"
+msgstr "%s:Kuzana Ubwoko"
+
+#: peicode.h:792
+#, fuzzy, c-format
+msgid "%s: Unrecognised import type; %x"
+msgstr "%s:Kuzana Ubwoko"
+
+#: peicode.h:806
+#, fuzzy, c-format
+msgid "%s: Unrecognised import name type; %x"
+msgstr "%s:Kuzana Izina: Ubwoko"
+
+#: peicode.h:1164
+#, fuzzy, c-format
+msgid "%s: Unrecognised machine type (0x%x) in Import Library Format archive"
+msgstr "%s:Ubwoko in"
+
+#: peicode.h:1176
+#, fuzzy, c-format
+msgid "%s: Recognised but unhandled machine type (0x%x) in Import Library Format archive"
+msgstr "%s:Ubwoko in"
+
+#: peicode.h:1193
+#, fuzzy, c-format
+msgid "%s: size field is zero in Import Library Format header"
+msgstr "%s:Ingano Umwanya ni Zeru in Umutwempangano"
+
+#: peicode.h:1224
+#, fuzzy, c-format
+msgid "%s: string not null terminated in ILF object file."
+msgstr "%s:Ikurikiranyanyuguti OYA NTAGIHARI in Igikoresho IDOSIYE"
+
+#: ppcboot.c:416
+#, fuzzy
+msgid ""
+"\n"
+"ppcboot header:\n"
+msgstr "Umutwempangano"
+
+#: ppcboot.c:417
+#, fuzzy, c-format
+msgid "Entry offset        = 0x%.8lx (%ld)\n"
+msgstr "Nta- boneza"
+
+#: ppcboot.c:418
+#, c-format
+msgid "Length              = 0x%.8lx (%ld)\n"
+msgstr ""
+
+#: ppcboot.c:421
+#, fuzzy, c-format
+msgid "Flag field          = 0x%.2x\n"
+msgstr "Umwanya"
+
+#: ppcboot.c:427
+#, fuzzy, c-format
+msgid "Partition name      = \"%s\"\n"
+msgstr "Izina:"
+
+#: ppcboot.c:446
+#, fuzzy, c-format
+msgid ""
+"\n"
+"Partition[%d] start  = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+msgstr "Gutangira"
+
+#: ppcboot.c:452
+#, fuzzy, c-format
+msgid "Partition[%d] end    = { 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x }\n"
+msgstr "Impera"
+
+#: ppcboot.c:458
+#, c-format
+msgid "Partition[%d] sector = 0x%.8lx (%ld)\n"
+msgstr ""
+
+#: ppcboot.c:459
+#, fuzzy, c-format
+msgid "Partition[%d] length = 0x%.8lx (%ld)\n"
+msgstr "Uburebure"
+
+#: som.c:5422
+msgid "som_sizeof_headers unimplemented"
+msgstr ""
+
+#: srec.c:302
+#, fuzzy, c-format
+msgid "%s:%d: Unexpected character `%s' in S-record file\n"
+msgstr "%s:%d:Inyuguti in Icyabitswe"
+
+#: stabs.c:319
+#, fuzzy, c-format
+msgid "%s(%s+0x%lx): Stabs entry has invalid string index."
+msgstr "%s(%s+0x%lx):Icyinjijwe Sibyo Ikurikiranyanyuguti Umubarendanga"
+
+#: syms.c:1019
+msgid "Unsupported .stab relocation"
+msgstr ""
+
+#: vms-gsd.c:356
+#, fuzzy, c-format
+msgid "bfd_make_section (%s) failed"
+msgstr "Byanze"
+
+#: vms-gsd.c:371
+#, fuzzy, c-format
+msgid "bfd_set_section_flags (%s, %x) failed"
+msgstr "Byanze"
+
+#: vms-gsd.c:407
+#, fuzzy, c-format
+msgid "Size mismatch section %s=%lx, %s=%lx"
+msgstr "Icyiciro"
+
+#: vms-gsd.c:704
+#, fuzzy, c-format
+msgid "unknown gsd/egsd subtype %d"
+msgstr "Kitazwi"
+
+#: vms-hdr.c:408
+#, fuzzy
+msgid "Object module NOT error-free !\n"
+msgstr "Modire Ikosa Kigenga"
+
+#: vms-misc.c:541
+#, fuzzy, c-format
+msgid "Stack overflow (%d) in _bfd_vms_push"
+msgstr "Byarenze urugero in"
+
+#: vms-misc.c:559
+#, fuzzy
+msgid "Stack underflow in _bfd_vms_pop"
+msgstr "in"
+
+#: vms-misc.c:918
+#, fuzzy
+msgid "_bfd_vms_output_counted called with zero bytes"
+msgstr "Na: Zeru Bayite"
+
+#: vms-misc.c:923
+#, fuzzy
+msgid "_bfd_vms_output_counted called with too many bytes"
+msgstr "Na: Bayite"
+
+#: vms-misc.c:1054
+#, fuzzy, c-format
+msgid "Symbol %s replaced by %s\n"
+msgstr "ku"
+
+#: vms-misc.c:1117
+#, fuzzy, c-format
+msgid "failed to enter %s"
+msgstr "Byanze Kuri Injiza"
+
+#: vms-tir.c:102
+msgid "No Mem !"
+msgstr ""
+
+#: vms-tir.c:383
+#, fuzzy, c-format
+msgid "bad section index in %s"
+msgstr "Icyiciro Umubarendanga in"
+
+#: vms-tir.c:396
+#, fuzzy, c-format
+msgid "unsupported STA cmd %s"
+msgstr "Cmd+"
+
+#: vms-tir.c:401 vms-tir.c:1261
+#, fuzzy, c-format
+msgid "reserved STA cmd %d"
+msgstr "Cmd+"
+
+#: vms-tir.c:512 vms-tir.c:535
+#, fuzzy, c-format
+msgid "%s: no symbol \"%s\""
+msgstr "%s:Oya IKIMENYETSO"
+
+#. unsigned shift
+#. rotate
+#. Redefine symbol to current location.
+#. Define a literal.
+#: vms-tir.c:602 vms-tir.c:714 vms-tir.c:824 vms-tir.c:842 vms-tir.c:850
+#: vms-tir.c:859 vms-tir.c:1584
+#, fuzzy, c-format
+msgid "%s: not supported"
+msgstr "%s:OYA"
+
+#: vms-tir.c:607 vms-tir.c:1439
+#, fuzzy, c-format
+msgid "%s: not implemented"
+msgstr "%s:OYA"
+
+#: vms-tir.c:611 vms-tir.c:1443
+#, fuzzy, c-format
+msgid "reserved STO cmd %d"
+msgstr "Cmd+"
+
+#: vms-tir.c:729 vms-tir.c:1589
+#, fuzzy, c-format
+msgid "reserved OPR cmd %d"
+msgstr "Cmd+"
+
+#: vms-tir.c:797 vms-tir.c:1653
+#, fuzzy, c-format
+msgid "reserved CTL cmd %d"
+msgstr "Cmd+"
+
+#. stack byte from image
+#. arg: none.
+#: vms-tir.c:1169
+#, fuzzy
+msgid "stack-from-image not implemented"
+msgstr "Bivuye Ishusho OYA"
+
+#: vms-tir.c:1187
+#, fuzzy
+msgid "stack-entry-mask not fully implemented"
+msgstr "Icyinjijwe OYA"
+
+#. compare procedure argument
+#. arg: cs	symbol name
+#. by	argument index
+#. da	argument descriptor
+#.
+#. compare argument descriptor with symbol argument (ARG$V_PASSMECH)
+#. and stack TRUE (args match) or FALSE (args dont match) value.
+#: vms-tir.c:1201
+#, fuzzy
+msgid "PASSMECH not fully implemented"
+msgstr "OYA"
+
+#: vms-tir.c:1220
+#, fuzzy
+msgid "stack-local-symbol not fully implemented"
+msgstr "IKIMENYETSO OYA"
+
+#: vms-tir.c:1233
+#, fuzzy
+msgid "stack-literal not fully implemented"
+msgstr "OYA"
+
+#: vms-tir.c:1254
+#, fuzzy
+msgid "stack-local-symbol-entry-point-mask not fully implemented"
+msgstr "IKIMENYETSO Icyinjijwe Akadomo OYA"
+
+#: vms-tir.c:1531 vms-tir.c:1543 vms-tir.c:1555 vms-tir.c:1567 vms-tir.c:1632
+#: vms-tir.c:1640 vms-tir.c:1648
+#, fuzzy, c-format
+msgid "%s: not fully implemented"
+msgstr "%s:OYA"
+
+#: vms-tir.c:1705
+#, fuzzy, c-format
+msgid "obj code %d not found"
+msgstr "ITEGEKONGENGA OYA Byabonetse"
+
+#: vms-tir.c:2043
+#, fuzzy, c-format
+msgid "SEC_RELOC with no relocs in section %s"
+msgstr "Na: Oya in Icyiciro"
+
+#: vms-tir.c:2331
+#, c-format
+msgid "Unhandled relocation %s"
+msgstr ""
+
+#: xcofflink.c:1244
+#, fuzzy, c-format
+msgid "%s: `%s' has line numbers but no enclosing section"
+msgstr "%s:`%s'Umurongo Imibare Oya Icyiciro"
+
+#: xcofflink.c:1297
+#, fuzzy, c-format
+msgid "%s: class %d symbol `%s' has no aux entries"
+msgstr "%s:ishuri IKIMENYETSO Oya Ibyinjijwe"
+
+#: xcofflink.c:1320
+#, fuzzy, c-format
+msgid "%s: symbol `%s' has unrecognized csect type %d"
+msgstr "%s:IKIMENYETSO Ubwoko"
+
+#: xcofflink.c:1332
+#, fuzzy, c-format
+msgid "%s: bad XTY_ER symbol `%s': class %d scnum %d scnlen %d"
+msgstr "%s:IKIMENYETSO ishuri"
+
+#: xcofflink.c:1368
+#, fuzzy, c-format
+msgid "%s: XMC_TC0 symbol `%s' is class %d scnlen %d"
+msgstr "%s:IKIMENYETSO ni ishuri"
+
+#: xcofflink.c:1520
+#, fuzzy, c-format
+msgid "%s: csect `%s' not in enclosing section"
+msgstr "%s:OYA in Icyiciro"
+
+#: xcofflink.c:1627
+#, c-format
+msgid "%s: misplaced XTY_LD `%s'"
+msgstr ""
+
+#: xcofflink.c:1958
+#, fuzzy, c-format
+msgid "%s: reloc %s:%d not in csect"
+msgstr "%s:OYA in"
+
+#: xcofflink.c:2095
+#, fuzzy, c-format
+msgid "%s: XCOFF shared object when not producing XCOFF output"
+msgstr "%s:Igikoresho Ryari: OYA Ibisohoka"
+
+#: xcofflink.c:2116
+#, fuzzy, c-format
+msgid "%s: dynamic object with no .loader section"
+msgstr "%s:Igikoresho Na: Oya Icyiciro"
+
+#: xcofflink.c:2761
+#, fuzzy, c-format
+msgid "%s: no such symbol"
+msgstr "%s:Oya IKIMENYETSO"
+
+#: xcofflink.c:2894
+#, fuzzy
+msgid "error: undefined symbol __rtinit"
+msgstr "Ikosa kidasobanuye IKIMENYETSO"
+
+#: xcofflink.c:3455
+#, fuzzy, c-format
+msgid "warning: attempt to export undefined symbol `%s'"
+msgstr "Iburira Kuri Kohereza kidasobanuye IKIMENYETSO"
+
+#: xcofflink.c:4448
+#, fuzzy, c-format
+msgid "TOC overflow: 0x%lx > 0x10000; try -mminimal-toc when compiling"
+msgstr "Byarenze urugero Ryari:"
+
+#: xcofflink.c:5288 xcofflink.c:5755 xcofflink.c:5817 xcofflink.c:6119
+#, fuzzy, c-format
+msgid "%s: loader reloc in unrecognized section `%s'"
+msgstr "%s:in Icyiciro"
+
+#: xcofflink.c:5310 xcofflink.c:6130
+#, fuzzy, c-format
+msgid "%s: `%s' in loader reloc but not loader sym"
+msgstr "%s:`%s'in OYA"
+
+#: xcofflink.c:5325
+#, fuzzy, c-format
+msgid "%s: loader reloc in read-only section %s"
+msgstr "%s:in Gusoma Icyiciro"
+
+#: elf32-ia64.c:2392 elf64-ia64.c:2392
+#, fuzzy
+msgid "@pltoff reloc against local symbol"
+msgstr "@IKIMENYETSO"
+
+#: elf32-ia64.c:3804 elf64-ia64.c:3804
+#, fuzzy, c-format
+msgid "%s: short data segment overflowed (0x%lx >= 0x400000)"
+msgstr "%s:Ibyatanzwe"
+
+#: elf32-ia64.c:3815 elf64-ia64.c:3815
+#, fuzzy, c-format
+msgid "%s: __gp does not cover short data segment"
+msgstr "%s:_OYA Ibyatanzwe"
+
+#: elf32-ia64.c:4131 elf64-ia64.c:4131
+#, fuzzy, c-format
+msgid "%s: linking non-pic code in a shared library"
+msgstr "%s:Impuza ITEGEKONGENGA in a Isomero"
+
+#: elf32-ia64.c:4164 elf64-ia64.c:4164
+#, fuzzy, c-format
+msgid "%s: @gprel relocation against dynamic symbol %s"
+msgstr "%s:@IKIMENYETSO"
+
+#: elf32-ia64.c:4224 elf64-ia64.c:4224
+#, fuzzy, c-format
+msgid "%s: linking non-pic code in a position independent executable"
+msgstr "%s:Impuza ITEGEKONGENGA in a Ibirindiro"
+
+#: elf32-ia64.c:4363 elf64-ia64.c:4363
+#, fuzzy, c-format
+msgid "%s: @internal branch to dynamic symbol %s"
+msgstr "%s:@By'imbere Kuri IKIMENYETSO"
+
+#: elf32-ia64.c:4365 elf64-ia64.c:4365
+#, fuzzy, c-format
+msgid "%s: speculation fixup to dynamic symbol %s"
+msgstr "%s:Kuri IKIMENYETSO"
+
+#: elf32-ia64.c:4367 elf64-ia64.c:4367
+#, fuzzy, c-format
+msgid "%s: @pcrel relocation against dynamic symbol %s"
+msgstr "%s:@IKIMENYETSO"
+
+#: elf32-ia64.c:4579 elf64-ia64.c:4579
+msgid "unsupported reloc"
+msgstr ""
+
+#: elf32-ia64.c:4858 elf64-ia64.c:4858
+#, fuzzy, c-format
+msgid "%s: linking trap-on-NULL-dereference with non-trapping files"
+msgstr "%s:Impuza ku Na: Idosiye"
+
+#: elf32-ia64.c:4867 elf64-ia64.c:4867
+#, fuzzy, c-format
+msgid "%s: linking big-endian files with little-endian files"
+msgstr "%s:Impuza Idosiye Na: Idosiye"
+
+#: elf32-ia64.c:4876 elf64-ia64.c:4876
+#, fuzzy, c-format
+msgid "%s: linking 64-bit files with 32-bit files"
+msgstr "%s:Impuza Idosiye Na: Idosiye"
+
+#: elf32-ia64.c:4885 elf64-ia64.c:4885
+#, fuzzy, c-format
+msgid "%s: linking constant-gp files with non-constant-gp files"
+msgstr "%s:Impuza Idosiye Na: Idosiye"
+
+#: elf32-ia64.c:4895 elf64-ia64.c:4895
+#, fuzzy, c-format
+msgid "%s: linking auto-pic files with non-auto-pic files"
+msgstr "%s:Impuza Ikiyega Idosiye Na: Ikiyega Idosiye"
+
+#: peigen.c:985 pepigen.c:985
+#, fuzzy, c-format
+msgid "%s: line number overflow: 0x%lx > 0xffff"
+msgstr "%s:Umurongo Umubare Byarenze urugero"
+
+#: peigen.c:1002 pepigen.c:1002
+#, fuzzy, c-format
+msgid "%s: reloc overflow 1: 0x%lx > 0xffff"
+msgstr "%s:Byarenze urugero 1."
+
+#: peigen.c:1016 pepigen.c:1016
+#, fuzzy
+msgid "Export Directory [.edata (or where ever we found it)]"
+msgstr "Cyangwa Twebwe Byabonetse"
+
+#: peigen.c:1017 pepigen.c:1017
+#, fuzzy
+msgid "Import Directory [parts of .idata]"
+msgstr "Bya"
+
+#: peigen.c:1018 pepigen.c:1018
+msgid "Resource Directory [.rsrc]"
+msgstr ""
+
+#: peigen.c:1019 pepigen.c:1019
+msgid "Exception Directory [.pdata]"
+msgstr ""
+
+#: peigen.c:1020 pepigen.c:1020
+msgid "Security Directory"
+msgstr ""
+
+#: peigen.c:1021 pepigen.c:1021
+#, fuzzy
+msgid "Base Relocation Directory [.reloc]"
+msgstr "Base"
+
+#: peigen.c:1022 pepigen.c:1022
+msgid "Debug Directory"
+msgstr ""
+
+#: peigen.c:1023 pepigen.c:1023
+msgid "Description Directory"
+msgstr ""
+
+#: peigen.c:1024 pepigen.c:1024
+msgid "Special Directory"
+msgstr ""
+
+#: peigen.c:1025 pepigen.c:1025
+#, fuzzy
+msgid "Thread Storage Directory [.tls]"
+msgstr "TLS"
+
+#: peigen.c:1026 pepigen.c:1026
+msgid "Load Configuration Directory"
+msgstr ""
+
+#: peigen.c:1027 pepigen.c:1027
+msgid "Bound Import Directory"
+msgstr ""
+
+#: peigen.c:1028 pepigen.c:1028
+msgid "Import Address Table Directory"
+msgstr ""
+
+#: peigen.c:1029 pepigen.c:1029
+msgid "Delay Import Directory"
+msgstr ""
+
+#: peigen.c:1030 peigen.c:1031 pepigen.c:1030 pepigen.c:1031
+msgid "Reserved"
+msgstr ""
+
+#: peigen.c:1094 pepigen.c:1094
+#, fuzzy
+msgid ""
+"\n"
+"There is an import table, but the section containing it could not be found\n"
+msgstr "ni Kuzana imbonerahamwe# i Icyiciro OYA"
+
+#: peigen.c:1099 pepigen.c:1099
+#, fuzzy, c-format
+msgid ""
+"\n"
+"There is an import table in %s at 0x%lx\n"
+msgstr "ni Kuzana imbonerahamwe# in ku"
+
+#: peigen.c:1136 pepigen.c:1136
+#, fuzzy, c-format
+msgid ""
+"\n"
+"Function descriptor located at the start address: %04lx\n"
+msgstr "ku i Gutangira Aderesi"
+
+#: peigen.c:1139 pepigen.c:1139
+#, fuzzy, c-format
+msgid "\tcode-base %08lx toc (loadable/actual) %08lx/%08lx\n"
+msgstr "ITEGEKONGENGA SHINGIRO"
+
+#: peigen.c:1145 pepigen.c:1145
+#, fuzzy
+msgid ""
+"\n"
+"No reldata section! Function descriptor not decoded.\n"
+msgstr "Icyiciro OYA"
+
+#: peigen.c:1150 pepigen.c:1150
+#, fuzzy, c-format
+msgid ""
+"\n"
+"The Import Tables (interpreted %s section contents)\n"
+msgstr "Icyiciro Ibigize"
+
+#: peigen.c:1153 pepigen.c:1153
+msgid ""
+" vma:            Hint    Time      Forward  DLL       First\n"
+"                 Table   Stamp     Chain    Name      Thunk\n"
+msgstr ""
+
+#: peigen.c:1204 pepigen.c:1204
+#, c-format
+msgid ""
+"\n"
+"\tDLL Name: %s\n"
+msgstr ""
+
+#: peigen.c:1215 pepigen.c:1215
+msgid "\tvma:  Hint/Ord Member-Name Bound-To\n"
+msgstr ""
+
+#: peigen.c:1240 pepigen.c:1240
+#, fuzzy
+msgid ""
+"\n"
+"There is a first thunk, but the section containing it could not be found\n"
+msgstr "ni a Itangira i Icyiciro OYA"
+
+#: peigen.c:1380 pepigen.c:1380
+#, fuzzy
+msgid ""
+"\n"
+"There is an export table, but the section containing it could not be found\n"
+msgstr "ni Kohereza imbonerahamwe# i Icyiciro OYA"
+
+#: peigen.c:1385 pepigen.c:1385
+#, fuzzy, c-format
+msgid ""
+"\n"
+"There is an export table in %s at 0x%lx\n"
+msgstr "ni Kohereza imbonerahamwe# in ku"
+
+#: peigen.c:1416 pepigen.c:1416
+#, fuzzy, c-format
+msgid ""
+"\n"
+"The Export Tables (interpreted %s section contents)\n"
+"\n"
+msgstr "Icyiciro Ibigize"
+
+#: peigen.c:1420 pepigen.c:1420
+#, c-format
+msgid "Export Flags \t\t\t%lx\n"
+msgstr ""
+
+#: peigen.c:1423 pepigen.c:1423
+#, c-format
+msgid "Time/Date stamp \t\t%lx\n"
+msgstr ""
+
+#: peigen.c:1426 pepigen.c:1426
+#, c-format
+msgid "Major/Minor \t\t\t%d/%d\n"
+msgstr ""
+
+#: peigen.c:1429 pepigen.c:1429
+#, fuzzy
+msgid "Name \t\t\t\t"
+msgstr "Izina"
+
+#: peigen.c:1435 pepigen.c:1435
+#, fuzzy, c-format
+msgid "Ordinal Base \t\t\t%ld\n"
+msgstr "Base"
+
+#: peigen.c:1438 pepigen.c:1438
+#, fuzzy
+msgid "Number in:\n"
+msgstr "in"
+
+#: peigen.c:1441 pepigen.c:1441
+#, c-format
+msgid "\tExport Address Table \t\t%08lx\n"
+msgstr ""
+
+#: peigen.c:1445 pepigen.c:1445
+#, c-format
+msgid "\t[Name Pointer/Ordinal] Table\t%08lx\n"
+msgstr ""
+
+#: peigen.c:1448 pepigen.c:1448
+msgid "Table Addresses\n"
+msgstr ""
+
+#: peigen.c:1451 pepigen.c:1451
+msgid "\tExport Address Table \t\t"
+msgstr ""
+
+#: peigen.c:1456 pepigen.c:1456
+msgid "\tName Pointer Table \t\t"
+msgstr ""
+
+#: peigen.c:1461 pepigen.c:1461
+msgid "\tOrdinal Table \t\t\t"
+msgstr ""
+
+#: peigen.c:1476 pepigen.c:1476
+#, fuzzy, c-format
+msgid ""
+"\n"
+"Export Address Table -- Ordinal Base %ld\n"
+msgstr "Base"
+
+#: peigen.c:1495 pepigen.c:1495
+msgid "Forwarder RVA"
+msgstr ""
+
+#: peigen.c:1506 pepigen.c:1506
+msgid "Export RVA"
+msgstr ""
+
+#: peigen.c:1513 pepigen.c:1513
+msgid ""
+"\n"
+"[Ordinal/Name Pointer] Table\n"
+msgstr ""
+
+#: peigen.c:1568 pepigen.c:1568
+#, fuzzy, c-format
+msgid "Warning, .pdata section size (%ld) is not a multiple of %d\n"
+msgstr "Icyiciro Ingano ni OYA a Igikubo Bya"
+
+#: peigen.c:1572 pepigen.c:1572
+#, fuzzy
+msgid ""
+"\n"
+"The Function Table (interpreted .pdata section contents)\n"
+msgstr "Icyiciro Ibigize"
+
+#: peigen.c:1575 pepigen.c:1575
+#, fuzzy
+msgid " vma:\t\t\tBegin Address    End Address      Unwind Info\n"
+msgstr "Impera"
+
+#: peigen.c:1577 pepigen.c:1577
+#, fuzzy
+msgid ""
+" vma:\t\tBegin    End      EH       EH       PrologEnd  Exception\n"
+"     \t\tAddress  Address  Handler  Data     Address    Mask\n"
+msgstr "Impera"
+
+#: peigen.c:1647 pepigen.c:1647
+#, fuzzy
+msgid " Register save millicode"
+msgstr "Kubika"
+
+#: peigen.c:1650 pepigen.c:1650
+#, fuzzy
+msgid " Register restore millicode"
+msgstr "Kugarura"
+
+#: peigen.c:1653 pepigen.c:1653
+#, fuzzy
+msgid " Glue code sequence"
+msgstr "ITEGEKONGENGA"
+
+#: peigen.c:1705 pepigen.c:1705
+#, fuzzy
+msgid ""
+"\n"
+"\n"
+"PE File Base Relocations (interpreted .reloc section contents)\n"
+msgstr "Idosiye Base Icyiciro Ibigize"
+
+#: peigen.c:1735 pepigen.c:1735
+#, fuzzy, c-format
+msgid ""
+"\n"
+"Virtual Address: %08lx Chunk size %ld (0x%lx) Number of fixups %ld\n"
+msgstr "Ingano Bya"
+
+#: peigen.c:1748 pepigen.c:1748
+#, fuzzy, c-format
+msgid "\treloc %4d offset %4x [%4lx] %s"
+msgstr "Nta- boneza"
+
+#. The MS dumpbin program reportedly ands with 0xff0f before
+#. printing the characteristics field.  Not sure why.  No reason to
+#. emulate it here.
+#: peigen.c:1788 pepigen.c:1788
+#, c-format
+msgid ""
+"\n"
+"Characteristics 0x%x\n"
+msgstr ""
diff --git a/gas/po/tr.gmo b/gas/po/tr.gmo
index 10635394c1d4..fe95cfbeb132 100644
--- a/gas/po/tr.gmo
+++ b/gas/po/tr.gmo
diff --git a/gas/po/tr.po b/gas/po/tr.po
index e0e05c826202..475a94615e12 100644
--- a/gas/po/tr.po
+++ b/gas/po/tr.po
@@ -1,85 +1,87 @@
-# translation of gas-2.14rel030712.tr.po to Turkish
-# Copyright (C) 2003 Free Software Foundation, Inc.
-# Deniz Akkus Kanca <deniz@arayan.com>, 2002,2003.
+# translation of gas-2.15.96.tr.po to Turkish
+# Copyright (C) 2003, 2005 Free Software Foundation, Inc.
+# Deniz Akkus Kanca <deniz@arayan.com>, 2002,2003, 2005.
 #
 msgid ""
 msgstr ""
-"Project-Id-Version: gas 2.14rel030712\n"
-"POT-Creation-Date: 2003-07-11 13:57+0930\n"
-"PO-Revision-Date: 2003-08-17 12:43+0300\n"
+"Project-Id-Version: gas 2.15.96\n"
+"Report-Msgid-Bugs-To: \n"
+"POT-Creation-Date: 2005-03-05 20:33+1030\n"
+"PO-Revision-Date: 2005-03-14 04:41+0200\n"
 "Last-Translator: Deniz Akkus Kanca <deniz@arayan.com>\n"
 "Language-Team: Turkish <gnu-tr-u12a@lists.sourceforge.net>\n"
 "MIME-Version: 1.0\n"
 "Content-Type: text/plain; charset=UTF-8\n"
 "Content-Transfer-Encoding: 8bit\n"
-"X-Generator: KBabel 1.0\n"
+"X-Generator: KBabel 1.9.1\n"
 
-#: app.c:474 app.c:488
+#: app.c:468 app.c:482
 msgid "end of file in comment"
 msgstr "açıklama içinde dosya sonu (EOF)"
 
-#: app.c:567
+#: app.c:561
 msgid "end of file in string; inserted '\"'"
 msgstr "dizge içinde dosya sonu (EOF): '\"' eklendi"
 
-#: app.c:612
+#: app.c:606
 msgid "end of file in string; '\"' inserted"
 msgstr "Dizgede dosya sonu: '\"' eklendi"
 
-#: app.c:638
+#: app.c:632
 #, c-format
 msgid "unknown escape '\\%c' in string; ignored"
 msgstr "Dizgede bilinmeyen kaçış '\\%c': Yoksayıldı"
 
-#: app.c:790
+#: app.c:788
 msgid "end of file not at end of a line; newline inserted"
 msgstr "dosya sonu satır sonunda değil; yenisatır eklendi"
 
-#: app.c:949
+#: app.c:947
 msgid "end of file in multiline comment"
 msgstr "çok satırlı açıklama içinde dosya sonu (EOF)"
 
-#: app.c:1013
+#: app.c:1011
 msgid "end of file after a one-character quote; \\0 inserted"
 msgstr "bir karakterlik alıntı sonrasında dosya sonu (EOF); \\0 eklendi"
 
-#: app.c:1021
+#: app.c:1019
 msgid "end of file in escape character"
 msgstr "kaçış karakterinde dosya sonu (EOF)"
 
-#: app.c:1033
+#: app.c:1031
 msgid "missing close quote; (assumed)"
 msgstr "Eksik kapanış tırnağı: (varsayıldı)"
 
-#: app.c:1101 app.c:1155 app.c:1166 app.c:1231
+#: app.c:1099 app.c:1153 app.c:1164 app.c:1229
 msgid "end of file in comment; newline inserted"
 msgstr "açıklama içinde dosya sonu (EOF); yenisatır eklendi"
 
-#: as.c:160
+#: as.c:165
 msgid "missing emulation mode name"
 msgstr "eksik öykünüm kipi adı"
 
-#: as.c:175
+#: as.c:180
 #, c-format
 msgid "unrecognized emulation name `%s'"
 msgstr "bilinmeyen öykünüm adı `%s'"
 
-#: as.c:222
+#: as.c:228
 #, c-format
 msgid "GNU assembler version %s (%s) using BFD version %s"
 msgstr "GNU çevirici %s (%s) sürümü BFD %s sürümü"
 
-#: as.c:225
+#: as.c:231
 #, c-format
 msgid "GNU assembler version %s (%s)"
 msgstr "GNU çevirici %s (%s) sürümü"
 
-#: as.c:234
+#: as.c:239
 #, c-format
 msgid "Usage: %s [option...] [asmfile...]\n"
 msgstr "Kullanım: %s [seçenek...] [asmdosya...]\n"
 
-#: as.c:236
+#: as.c:241
+#, c-format
 msgid ""
 "Options:\n"
 "  -a[sub-option...]\t  turn on listings\n"
@@ -105,114 +107,155 @@ msgstr ""
 "                      \t  s      sembolleri içerir\n"
 "                      \t  =DOSYA DOSYA'ya listeler (en son alt seçenek olmalı)\n"
 
-#: as.c:249
+#: as.c:254
+#, c-format
+msgid "  --alternate             initially turn on alternate macro syntax\n"
+msgstr ""
+
+#: as.c:256
+#, c-format
 msgid "  -D                      produce assembler debugging messages\n"
 msgstr "  -D                      çevirici hata ayıklama iletileri üretir\n"
 
-#: as.c:251
+#: as.c:258
+#, c-format
 msgid "  --defsym SYM=VAL        define symbol SYM to given value\n"
 msgstr "  --defsym SEM=DEÄž        sembol SEM'i verilen deÄŸere atar\n"
 
-#: as.c:267
+#: as.c:274
 #, c-format
 msgid "                          emulate output (default %s)\n"
 msgstr "                          çıktıda öykünüm uygular (öntanımlı %s)\n"
 
-#: as.c:272
+#: as.c:279
+#, c-format
 msgid "  --execstack             require executable stack for this object\n"
 msgstr "  --execstack             bu nesne için işlenebilir yığıt şartı koyar\n"
 
-#: as.c:274
+#: as.c:281
+#, c-format
 msgid "  --noexecstack           don't require executable stack for this object\n"
 msgstr "  --noexecstack           bu nesne için işlenebilir yığıt şartı koymaz\n"
 
-#: as.c:277
+#: as.c:284
+#, c-format
 msgid "  -f                      skip whitespace and comment preprocessing\n"
 msgstr "  -f                      boşlukları ve açıklama önişlemelerini atlar\n"
 
-#: as.c:279
-msgid "  --gstabs                generate stabs debugging information\n"
+#: as.c:286
+#, fuzzy, c-format
+msgid "  -g --gen-debug          generate debugging information\n"
 msgstr "  --gstabs                stabs hata ayıklama bilgisi üretir\n"
 
-#: as.c:281
-msgid "  --gdwarf2               generate DWARF2 debugging information\n"
+#: as.c:288
+#, fuzzy, c-format
+msgid "  --gstabs                generate STABS debugging information\n"
+msgstr "  --gstabs                stabs hata ayıklama bilgisi üretir\n"
+
+#: as.c:290
+#, fuzzy, c-format
+msgid "  --gstabs+               generate STABS debug info with GNU extensions\n"
+msgstr "  --gstabs                stabs hata ayıklama bilgisi üretir\n"
+
+#: as.c:292
+#, fuzzy, c-format
+msgid "  --gdwarf-2              generate DWARF2 debugging information\n"
 msgstr "  --gdwarf2               DWARF2 hata ayıklama bilgisi üretir\n"
 
-#: as.c:283
+#: as.c:294
+#, c-format
 msgid "  --help                  show this message and exit\n"
 msgstr "  --help                  bu yardımı gösterir ve çıkar\n"
 
-#: as.c:285
+#: as.c:296
+#, c-format
 msgid "  --target-help           show target specific options\n"
 msgstr "  --target-help           hedefe özel seçenekleri gösterir\n"
 
-#: as.c:287
+#: as.c:298
+#, c-format
 msgid "  -I DIR                  add DIR to search list for .include directives\n"
 msgstr "  -I DİZ                  DİZ'i .include yönergeleri için arama listesine ekler\n"
 
-#: as.c:289
+#: as.c:300
+#, c-format
 msgid "  -J                      don't warn about signed overflow\n"
 msgstr "  -J                      signed taşmalarında uyarmaz\n"
 
-#: as.c:291
+#: as.c:302
+#, c-format
 msgid "  -K                      warn when differences altered for long displacements\n"
 msgstr "  -K                      farklar uzak yerdeğişimler için değiştiğinde uyarır\n"
 
-#: as.c:293
+#: as.c:304
+#, c-format
 msgid "  -L,--keep-locals        keep local symbols (e.g. starting with `L')\n"
 msgstr "  -L,--keep-locals        yerel sembolleri tutar (örn. `L' ile başlayanları)\n"
 
-#: as.c:295
+#: as.c:306
+#, c-format
 msgid "  -M,--mri                assemble in MRI compatibility mode\n"
 msgstr "  -M,--mri                MRI uyumluluk kipinde çevirir\n"
 
-#: as.c:297
+#: as.c:308
+#, c-format
 msgid "  --MD FILE               write dependency information in FILE (default none)\n"
 msgstr "  --MD DOSYA              DOSYA'ya bağımlılık bilgisini yazar (öntanımlı hiçbiri)\n"
 
-#: as.c:299
+#: as.c:310
+#, c-format
 msgid "  -nocpp                  ignored\n"
 msgstr "  -nocpp                  yoksayılır\n"
 
-#: as.c:301
+#: as.c:312
+#, c-format
 msgid "  -o OBJFILE              name the object-file output OBJFILE (default a.out)\n"
 msgstr ""
 "  -o NESDOS               nesne dosyası çıktısını NESDOS olarak adlandırır\n"
 "                            (öntanımlı a.out)\n"
 
-#: as.c:303
+#: as.c:314
+#, c-format
 msgid "  -R                      fold data section into text section\n"
 msgstr "  -R                      veri bölümünü metin bölümüne ilave eder\n"
 
-#: as.c:305
+#: as.c:316
+#, c-format
 msgid "  --statistics            print various measured statistics from execution\n"
 msgstr "  --statistics            çalıştırma esnasında ölçülen istatistikleri gösterir\n"
 
-#: as.c:307
+#: as.c:318
+#, c-format
 msgid "  --strip-local-absolute  strip local absolute symbols\n"
 msgstr "  --strip-local-absolute  yerel bağımsız sembolleri soyar\n"
 
-#: as.c:309
+#: as.c:320
+#, c-format
 msgid "  --traditional-format    Use same format as native assembler when possible\n"
 msgstr "  --traditional-format    Mümkün oldukça yerel çevirici biçemini kullanır\n"
 
-#: as.c:311
+#: as.c:322
+#, c-format
 msgid "  --version               print assembler version number and exit\n"
 msgstr "  --version               çevirici sürüm numarasını gösterir ve çıkar\n"
 
-#: as.c:313
+#: as.c:324
+#, c-format
 msgid "  -W  --no-warn           suppress warnings\n"
 msgstr "  -W  --no-warn           uyarıları göstermez\n"
 
-#: as.c:315
+#: as.c:326
+#, c-format
 msgid "  --warn                  don't suppress warnings\n"
 msgstr "  --warn                  uyarıları gösterir\n"
 
-#: as.c:317
+#: as.c:328
+#, c-format
 msgid "  --fatal-warnings        treat warnings as errors\n"
 msgstr "  --fatal-warnings        uyarıları hata kabul eder\n"
 
-#: as.c:319
+#: as.c:330
+#, c-format
 msgid ""
 "  --itbl INSTTBL          extend instruction set to include instructions\n"
 "                          matching the specifications defined in file INSTTBL\n"
@@ -220,19 +263,23 @@ msgstr ""
 "  --itbl YÖNER            işlem kümesini YÖNER dosyasında tanımlanan\n"
 "                          niteliklere uygun işlemlerle arttırır\n"
 
-#: as.c:322
+#: as.c:333
+#, c-format
 msgid "  -w                      ignored\n"
 msgstr "  -w                      yoksayılır\n"
 
-#: as.c:324
+#: as.c:335
+#, c-format
 msgid "  -X                      ignored\n"
 msgstr "  -X                      yoksayılır\n"
 
-#: as.c:326
+#: as.c:337
+#, c-format
 msgid "  -Z                      generate object file even after errors\n"
 msgstr "  -Z                      hatalardan sonra dahi nesne dosyası oluşturur\n"
 
-#: as.c:328
+#: as.c:339
+#, c-format
 msgid ""
 "  --listing-lhs-width     set the width in words of the output data column of\n"
 "                          the listing\n"
@@ -240,7 +287,8 @@ msgstr ""
 "  --listing-lhs-width     listelemede çıktı verisi sütun genişliğini word \n"
 "                          cinsinden belirtir\n"
 
-#: as.c:331
+#: as.c:342
+#, c-format
 msgid ""
 "  --listing-lhs-width2    set the width in words of the continuation lines\n"
 "                          of the output data column; ignored if smaller than\n"
@@ -250,7 +298,8 @@ msgstr ""
 "                          genişliğini word cinsinden belirtir; eğer ilk satırın\n"
 "                          genişliğinden az ise, yoksayılır\n"
 
-#: as.c:335
+#: as.c:346
+#, c-format
 msgid ""
 "  --listing-rhs-width     set the max width in characters of the lines from\n"
 "                          the source file\n"
@@ -258,7 +307,8 @@ msgstr ""
 "  --listing-rhs-width     kaynak dosyadan alınan satırların maksimum \n"
 "                          geniÅŸliÄŸini harf cinsinden belirtir\n"
 
-#: as.c:338
+#: as.c:349
+#, c-format
 msgid ""
 "  --listing-cont-lines    set the maximum number of continuation lines used\n"
 "                          for the output data column of the listing\n"
@@ -266,23 +316,30 @@ msgstr ""
 "  --listing-cont-lines    listelemede çıktı verisi uzatma satırları için\n"
 "                          maksimum satır sayısını belirtir\n"
 
-#: as.c:345
+#: as.c:356
 #, c-format
 msgid "Report bugs to %s\n"
 msgstr ""
 "Yazılım hatalarını %s adresine,\n"
-"çeviri hatalarını <gnu-tr-u12a@lists.sourceforge.net> adresine gönderin\n"
+"çeviri hatalarını <gnu-tr@belgeler.org> adresine gönderin\n"
+
+#: as.c:549
+#, fuzzy, c-format
+msgid "unrecognized option -%c%s"
+msgstr "bilinmeyen seçenek: `-%c%s'"
 
-#: as.c:557 as.c:559
+#: as.c:588 as.c:590
 #, c-format
 msgid "GNU assembler %s\n"
 msgstr "GNU çevirici %s\n"
 
-#: as.c:561
-msgid "Copyright 2002 Free Software Foundation, Inc.\n"
+#: as.c:592
+#, fuzzy, c-format
+msgid "Copyright 2005 Free Software Foundation, Inc.\n"
 msgstr "Telif Hakkı (c) 2002 Free Software Foundation, Inc.\n"
 
-#: as.c:562
+#: as.c:593
+#, c-format
 msgid ""
 "This program is free software; you may redistribute it under the terms of\n"
 "the GNU General Public License.  This program has absolutely no warranty.\n"
@@ -291,78 +348,78 @@ msgstr ""
 "yapabilir ve/veya yeniden dağıtabilirsiniz. \n"
 "Bu yazılımın herhangi bir garantisi yoktur.\n"
 
-#: as.c:565
+#: as.c:596
 #, c-format
 msgid "This assembler was configured for a target of `%s'.\n"
 msgstr "Bu çevirici, `%s' hedefi için ayarlanmıştır.\n"
 
-#: as.c:572
+#: as.c:603
 msgid "multiple emulation names specified"
 msgstr "çoklu öykünüm isimleri belirtilmiş"
 
-#: as.c:574
+#: as.c:605
 msgid "emulations not handled in this configuration"
 msgstr "öykünümler bu ayarlarda desteklenmemektedir"
 
-#: as.c:579
+#: as.c:610
 #, c-format
 msgid "alias = %s\n"
 msgstr "rumuz = %s\n"
 
-#: as.c:580
+#: as.c:611
 #, c-format
 msgid "canonical = %s\n"
 msgstr "canonical = %s\n"
 
-#: as.c:581
+#: as.c:612
 #, c-format
 msgid "cpu-type = %s\n"
 msgstr "cpu türü = %s\n"
 
-#: as.c:583
+#: as.c:614
 #, c-format
 msgid "format = %s\n"
 msgstr "biçem = %s\n"
 
-#: as.c:586
+#: as.c:617
 #, c-format
 msgid "bfd-target = %s\n"
 msgstr "bfd hedefi = %s\n"
 
-#: as.c:599
+#: as.c:630
 msgid "bad defsym; format is --defsym name=value"
 msgstr "hatalı defsym; biçem: --defsym name=değer"
 
-#: as.c:623
+#: as.c:654
 msgid "no file name following -t option"
 msgstr "-t seçeneğinden sonra dosya ismi bulunamadı"
 
-#: as.c:638
+#: as.c:669
 #, c-format
 msgid "failed to read instruction table %s\n"
 msgstr "İşlem tablosu %s okunamadı\n"
 
-#: as.c:765
+#: as.c:830
 #, c-format
 msgid "invalid listing option `%c'"
 msgstr "geçersiz listeleme seçeneği `%c'"
 
-#: as.c:984
-#, c-format
-msgid "%d warnings, treating warnings as errors"
-msgstr "%d uyarı, uyarılar hata olarak değerlendiriliyor"
-
-#: as.c:1015
+#: as.c:890
 #, c-format
 msgid "%s: total time in assembly: %ld.%06ld\n"
 msgstr "%s: çeviride geçen toplam zaman: %ld.%06ld\n"
 
-#: as.c:1018
+#: as.c:893
 #, c-format
 msgid "%s: data size %ld\n"
 msgstr "%s: veri boyu %ld\n"
 
-#: as.h:216
+#: as.c:1202
+#, c-format
+msgid "%d warnings, treating warnings as errors"
+msgstr "%d uyarı, uyarılar hata olarak değerlendiriliyor"
+
+#: as.h:199
 #, c-format
 msgid "Case value %ld unexpected at line %d of file \"%s\"\n"
 msgstr "\"%3$s\" dosyası, %2$d satırında beklenmeyen case değeri: %1$ld\n"
@@ -371,71 +428,71 @@ msgstr "\"%3$s\" dosyası, %2$d satırında beklenmeyen case değeri: %1$ld\n"
 #. * We have a GROSS internal error.
 #. * This should never happen.
 #.
-#: atof-generic.c:437 config/tc-m68k.c:2869
+#: atof-generic.c:419 config/tc-m68k.c:3160
 msgid "failed sanity check"
 msgstr "başarısız kontrol"
 
-#: cond.c:83
+#: cond.c:82
 msgid "invalid identifier for \".ifdef\""
 msgstr "\".ifdef\" için geçersiz tanıtıcı"
 
-#: cond.c:151
+#: cond.c:149
 msgid "non-constant expression in \".if\" statement"
 msgstr "\".if\" deyiminde sabit olmayan ifade"
 
-#: cond.c:247
+#: cond.c:242
 msgid "bad format for ifc or ifnc"
 msgstr "ifc veya ifnc için hatalı biçem"
 
-#: cond.c:278
+#: cond.c:272
 msgid "\".elseif\" without matching \".if\""
 msgstr "\".if\" ile eÅŸlenemeyen \".elseif\""
 
-#: cond.c:282
+#: cond.c:276
 msgid "\".elseif\" after \".else\""
 msgstr "\".else\"den sonra \".elseif\""
 
-#: cond.c:285 cond.c:393
+#: cond.c:279 cond.c:385
 msgid "here is the previous \"else\""
 msgstr "bir önceki \"else\" burada"
 
-#: cond.c:288 cond.c:396
+#: cond.c:282 cond.c:388
 msgid "here is the previous \"if\""
 msgstr "bir önceki \"if\" burada"
 
-#: cond.c:317
+#: cond.c:311
 msgid "non-constant expression in \".elseif\" statement"
 msgstr "\".elseif\" deyiminde sabit olmayan ifade"
 
-#: cond.c:356
+#: cond.c:349
 msgid "\".endif\" without \".if\""
 msgstr "\".if\" ile eÅŸleÅŸmeyen \".endif\""
 
-#: cond.c:386
+#: cond.c:378
 msgid "\".else\" without matching \".if\""
 msgstr "`if' ile eÅŸleÅŸmeyen `else'"
 
-#: cond.c:390
+#: cond.c:382
 msgid "duplicate \"else\""
 msgstr "birden fazla \"else\""
 
-#: cond.c:442
+#: cond.c:433
 msgid ".ifeqs syntax error"
 msgstr ".ifeqs sözdizim hatası"
 
-#: cond.c:525
+#: cond.c:514
 msgid "end of macro inside conditional"
 msgstr "Macro koşulun içinde bitiyor"
 
-#: cond.c:527
+#: cond.c:516
 msgid "end of file inside conditional"
 msgstr "Dosya koşulun içinde sonlanmış"
 
-#: cond.c:530
+#: cond.c:519
 msgid "here is the start of the unterminated conditional"
 msgstr "sonlanmamış koşulun başlangıcı"
 
-#: cond.c:534
+#: cond.c:523
 msgid "here is the \"else\" of the unterminated conditional"
 msgstr "sonlanmamış koşulun \"else\" bölümü"
 
@@ -449,225 +506,209 @@ msgstr "%s kümesine ortak sembol ekleme denemesi"
 msgid "Attempt to put an undefined symbol into set %s"
 msgstr "%s kümesine tanımlanmamış sembol ekleme denemesi"
 
-#: config/obj-aout.c:197 config/obj-coff.c:1276
+#: config/obj-aout.c:197 config/obj-coff.c:1415
 #, c-format
 msgid "Symbol `%s' can not be both weak and common"
 msgstr "`%s' sembolü hem zayıf hem ortak olamaz"
 
-#: config/obj-aout.c:255 config/obj-coff.c:2022
+#: config/obj-aout.c:255 config/obj-coff.c:2156
 msgid "unresolved relocation"
 msgstr "çözümlenmemiş yerdeğişim"
 
-#: config/obj-aout.c:257 config/obj-coff.c:2024
+#: config/obj-aout.c:257 config/obj-coff.c:2158
 #, c-format
 msgid "bad relocation: symbol `%s' not in symbol table"
 msgstr "hatalı yerdeğişim: `%s' sembolü sembol tablosunda değil"
 
-#: config/obj-aout.c:344
+#: config/obj-aout.c:353
 #, c-format
 msgid "%s: bad type for weak symbol"
 msgstr "%s: zayıf sembol için hatalı tür"
 
-#: config/obj-aout.c:458 config/obj-coff.c:2945 write.c:1931
+#: config/obj-aout.c:459 config/obj-coff.c:3076 write.c:1904
 #, c-format
 msgid "%s: global symbols not supported in common sections"
 msgstr "%s: ortak bölümlerde evrensel semboller"
 
-#: config/obj-aout.c:524
+#: config/obj-aout.c:529
 #, c-format
 msgid "Local symbol %s never defined."
 msgstr "Yerel %s sembolü tanımlanmamış."
 
-#: config/obj-bout.c:319 config/obj-vms.c:629
+#: config/obj-bout.c:312 config/obj-vms.c:449
 #, c-format
 msgid "Local symbol %s never defined"
 msgstr "Yerel %s sembolü tanımlanmamış"
 
-#: config/obj-coff.c:166
+#: config/obj-coff.c:165
 #, c-format
 msgid "Inserting \"%s\" into structure table failed: %s"
 msgstr "Yapı tablosuna \"%s\" eklenmesi başarısız: %s"
 
 #. Zero is used as an end marker in the file.
-#: config/obj-coff.c:469
+#: config/obj-coff.c:426
 msgid "Line numbers must be positive integers\n"
 msgstr "Satır sayıları pozitif tamsayı olmalı\n"
 
 #. Wrong context.
-#: config/obj-coff.c:503 config/obj-coff.c:2367
+#: config/obj-coff.c:460 config/obj-coff.c:2501
 msgid ".ln pseudo-op inside .def/.endef: ignored."
 msgstr ".def/.endef içinde .ln pseudo-op: yoksayıldı."
 
-#: config/obj-coff.c:546 ecoff.c:3278
+#: config/obj-coff.c:503 ecoff.c:3240
 msgid ".loc outside of .text"
 msgstr ".text dışında .loc"
 
-#: config/obj-coff.c:553
+#: config/obj-coff.c:510
 msgid ".loc pseudo-op inside .def/.endef: ignored."
 msgstr ".def/.endef içinde .loc pseudo-op: yoksayıldı."
 
-#: config/obj-coff.c:641 config/obj-coff.c:2419
+#: config/obj-coff.c:598 config/obj-coff.c:2553
 msgid ".def pseudo-op used inside of .def/.endef: ignored."
 msgstr ".def/.endef içinde .def pseudo-op kullanılmış: yoksayıldı."
 
-#: config/obj-coff.c:687 config/obj-coff.c:2471
+#: config/obj-coff.c:644 config/obj-coff.c:2605
 msgid ".endef pseudo-op used outside of .def/.endef: ignored."
 msgstr ".endef pseudo-op .def/.endef dışında kullanılmış: yoksayıldı."
 
-#: config/obj-coff.c:725
+#: config/obj-coff.c:682
 #, c-format
 msgid "`%s' symbol without preceding function"
 msgstr "Öncesinde işlev olmadan `%s' sembolü"
 
-#: config/obj-coff.c:812 config/obj-coff.c:2551
+#: config/obj-coff.c:769 config/obj-coff.c:2685
 #, c-format
 msgid "unexpected storage class %d"
 msgstr "beklenmeyen saklama sınıfı %d"
 
-#: config/obj-coff.c:925 config/obj-coff.c:2658
+#: config/obj-coff.c:882 config/obj-coff.c:2792
 msgid ".dim pseudo-op used outside of .def/.endef: ignored."
 msgstr ".dim pseudo-op, .def/.endef dışında kullanılmış: yoksayıldı."
 
-#: config/obj-coff.c:945 config/obj-coff.c:2678
+#: config/obj-coff.c:902 config/obj-coff.c:2812
 msgid "badly formed .dim directive ignored"
 msgstr "hatalı oluşturulmuş .dim yönergesi yoksayıldı"
 
-#: config/obj-coff.c:996 config/obj-coff.c:2738
+#: config/obj-coff.c:953 config/obj-coff.c:2869
 msgid ".size pseudo-op used outside of .def/.endef ignored."
 msgstr ".def/.endef dışında kullanılan .size pseudo-op yoksayıldı."
 
-#: config/obj-coff.c:1012 config/obj-coff.c:2754
+#: config/obj-coff.c:969 config/obj-coff.c:2885
 msgid ".scl pseudo-op used outside of .def/.endef ignored."
 msgstr ".def/.endef dışında kullanılan .scl pseudo-op yoksayıldı."
 
-#: config/obj-coff.c:1030 config/obj-coff.c:2772
+#: config/obj-coff.c:987 config/obj-coff.c:2903
 msgid ".tag pseudo-op used outside of .def/.endef ignored."
 msgstr ".def/.endef dışında kullanılan .tag pseudo-op yoksayıldı."
 
-#: config/obj-coff.c:1049 config/obj-coff.c:2789
+#: config/obj-coff.c:1006 config/obj-coff.c:2920
 #, c-format
 msgid "tag not found for .tag %s"
 msgstr ".tag %s için etiket bulunamadı"
 
-#: config/obj-coff.c:1064 config/obj-coff.c:2803
+#: config/obj-coff.c:1021 config/obj-coff.c:2934
 msgid ".type pseudo-op used outside of .def/.endef ignored."
 msgstr ".def/.endef dışında kullanılan .type pseudo-op yoksayıldı."
 
-#: config/obj-coff.c:1086 config/obj-coff.c:2823
+#: config/obj-coff.c:1043 config/obj-coff.c:2954
 msgid ".val pseudo-op used outside of .def/.endef ignored."
 msgstr ".def/.endef dışında kullanılan .val pseudo-op yoksayıldı."
 
-#: config/obj-coff.c:1233 config/obj-coff.c:3016
+#: config/obj-coff.c:1180
+#, fuzzy
+msgid "badly formed .weak directive ignored"
+msgstr "hatalı oluşturulmuş .dim yönergesi yoksayıldı"
+
+#: config/obj-coff.c:1372 config/obj-coff.c:3147
 msgid "mismatched .eb"
 msgstr "eÅŸlenmeyen .eb"
 
-#: config/obj-coff.c:1254 config/obj-coff.c:3054
+#: config/obj-coff.c:1393 config/obj-coff.c:3178
 msgid "C_EFCN symbol out of scope"
 msgstr "C_EFCN sembolü kapsam dışı"
 
 #. STYP_INFO
 #. STYP_LIB
 #. STYP_OVER
-#: config/obj-coff.c:1482
+#: config/obj-coff.c:1621
 #, c-format
 msgid "unsupported section attribute '%c'"
 msgstr "desteklenmeyen bölüm özniteliği '%c'"
 
-#: config/obj-coff.c:1487 config/obj-coff.c:3759 config/tc-ppc.c:4508
+#: config/obj-coff.c:1626 config/obj-coff.c:3874 config/tc-ppc.c:4595
 #, c-format
 msgid "unknown section attribute '%c'"
 msgstr "bilinmeyen bölüm özniteliği '%c'"
 
-#: config/obj-coff.c:1517 config/tc-ppc.c:4526 config/tc-tic54x.c:4339
-#: read.c:2562
+#: config/obj-coff.c:1656 config/tc-ppc.c:4613 config/tc-tic54x.c:4306
+#: read.c:2545
 #, c-format
 msgid "error setting flags for \"%s\": %s"
 msgstr "\"%s\" için bayrak atanırken hata oluştu: %s"
 
-#: config/obj-coff.c:1528
+#: config/obj-coff.c:1667
 #, c-format
 msgid "Ignoring changed section attributes for %s"
 msgstr "%s için değişmiş bölüm öznitelikleri yoksayıldı"
 
-#: config/obj-coff.c:1664
+#: config/obj-coff.c:1803
 #, c-format
 msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n"
 msgstr "0x%lx: \"%s\" tür = %ld, sınıf = %d, bölüm = %d\n"
 
-#: config/obj-coff.c:1849 config/obj-ieee.c:69
+#: config/obj-coff.c:1983 config/obj-ieee.c:69
+#, c-format
 msgid "Out of step\n"
 msgstr "Uygun adım dışında\n"
 
-#: config/obj-coff.c:2286
+#: config/obj-coff.c:2420
 msgid "bfd_coff_swap_scnhdr_out failed"
 msgstr "bfd_coff_swap_scnhdr_out başarısız"
 
-#: config/obj-coff.c:2507
+#: config/obj-coff.c:2641
+#, c-format
 msgid "`.bf' symbol without preceding function\n"
 msgstr "öncesinde işlev olmadan `.bf' sembolü\n"
 
-#: config/obj-coff.c:3457 config/obj-ieee.c:521
+#: config/obj-coff.c:3581 config/obj-ieee.c:511
 #, c-format
 msgid "FATAL: Can't create %s"
 msgstr "ÖLÜMCÜL: %s oluşturulamadı"
 
-#: config/obj-coff.c:3635
-#, c-format
-msgid "Can't close %s: %s"
-msgstr "%s kapatılamadı: %s"
-
-#: config/obj-coff.c:3669
+#: config/obj-coff.c:3784
 #, c-format
 msgid "Too many new sections; can't add \"%s\""
 msgstr "Çok fazla sayıda yeni bölüm; \"%s\" eklenemedi"
 
-#: config/obj-coff.c:4057 config/tc-sparc.c:3635
-msgid "Expected comma after name"
-msgstr "İsimden sonra virgül beklendi"
-
-#: config/obj-coff.c:4063
-msgid "Missing size expression"
-msgstr "Boyut ifadesi eksik"
-
-#: config/obj-coff.c:4069
-#, c-format
-msgid "lcomm length (%d.) <0! Ignored."
-msgstr "lcomm uzunluğu (%d.) <0! Yoksayıldı."
-
-#: config/obj-coff.c:4097
-#, c-format
-msgid "Symbol %s already defined"
-msgstr "Sembol %s daha önce tanımlanmış"
-
-#: config/obj-coff.c:4193 config/tc-i960.c:3221
+#: config/obj-coff.c:4247 config/tc-i960.c:3222
 #, c-format
 msgid "No 'bal' entry point for leafproc %s"
 msgstr "Leafproc %s için 'bal' giriş noktası yok"
 
-#: config/obj-coff.c:4270
+#: config/obj-coff.c:4323
 #, c-format
 msgid "Negative of non-absolute symbol %s"
 msgstr "Bağımsız olmayan sembol %s'nin negatifi"
 
-#: config/obj-coff.c:4290
+#: config/obj-coff.c:4343
 msgid "callj to difference of 2 symbols"
 msgstr "2 sembolün farkına callj"
 
-#: config/obj-coff.c:4334
+#: config/obj-coff.c:4383
 #, c-format
 msgid "Can't emit reloc {- %s-seg symbol \"%s\"} @ file address %ld."
 msgstr "%3$ld dosya adresinde yerdeğişim {- %1$s-seg sembol \"%2$s\"} üretilemedi."
 
-#: config/obj-coff.c:4420 config/tc-i960.c:2844
+#: config/obj-coff.c:4469 config/tc-i960.c:2849
 msgid "can't use COBR format with external label"
 msgstr "Dış etiketle COBR biçemi kullanılamaz"
 
-#: config/obj-coff.c:4493
+#: config/obj-coff.c:4542
 #, c-format
 msgid "Value of %ld too large for field of %d bytes at 0x%lx"
 msgstr "0x%3$lx adresinde %2$d baytlık alan için %1$ld değeri fazla yüksek"
 
-#: config/obj-coff.c:4507
+#: config/obj-coff.c:4556
 #, c-format
 msgid "Signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr "Signed .word taşması; bayrak çok büyük olabilir; 0x%2$lx de %1$ld"
@@ -680,245 +721,222 @@ msgstr "GP değeri atanamadı"
 msgid "Can't set register masks"
 msgstr "Yazmaç maskeleri ayarlanamadı"
 
-#: config/obj-elf.c:316
-msgid "expected comma after symbol-name"
-msgstr "Sembol adından sonra virgül beklendi"
-
-#: config/obj-elf.c:326
-#, c-format
-msgid ".COMMon length (%ld) out of range, ignored."
-msgstr ".COMM ortak uzunluğu (%ld) kapsam dışı, yoksayıldı."
-
-#: config/obj-elf.c:335 ecoff.c:3397 read.c:1406 read.c:1507 read.c:2145
-#: read.c:2234 read.c:2863 read.c:4968 symbols.c:367 symbols.c:466
-#, c-format
-msgid "symbol `%s' is already defined"
-msgstr "`%s' sembolü zaten tanımlanmış"
-
-#: config/obj-elf.c:343
-#, c-format
-msgid "length of .comm \"%s\" is already %ld; not changed to %ld"
-msgstr ".comm \"%s\" uzunluÄŸu zaten %ld. %ld olarak deÄŸiÅŸtirilmedi."
-
-#: config/obj-elf.c:367
-msgid "common alignment negative; 0 assumed"
-msgstr "Ortak hizalama negatif; 0 varsayıldı"
-
-#: config/obj-elf.c:386
-msgid "common alignment not a power of 2"
-msgstr "Ortak hizalama 2'nin kuvveti deÄŸil"
-
-#: config/obj-elf.c:449 config/tc-sparc.c:3931 config/tc-v850.c:461
+#: config/obj-elf.c:307 config/tc-sparc.c:3976 config/tc-v850.c:461
 #, c-format
 msgid "bad .common segment %s"
 msgstr "ortak .common bölümü %s"
 
-#: config/obj-elf.c:717
+#: config/obj-elf.c:574
 #, c-format
 msgid "setting incorrect section type for %s"
 msgstr "%s için hatalı bölüm türü atanıyor"
 
-#: config/obj-elf.c:721
+#: config/obj-elf.c:579
 #, c-format
 msgid "ignoring incorrect section type for %s"
 msgstr "%s için hatalı bölüm türü yoksayıldı"
 
-#: config/obj-elf.c:734
+#: config/obj-elf.c:616
 #, c-format
 msgid "setting incorrect section attributes for %s"
 msgstr "%s için hatalı bölüm öznitelikleri atanıyor"
 
-#: config/obj-elf.c:786
+#: config/obj-elf.c:668
+#, fuzzy, c-format
+msgid "ignoring changed section type for %s"
+msgstr "%s için değişmiş bölüm öznitelikleri yoksayıldı"
+
+#: config/obj-elf.c:680
 #, c-format
 msgid "ignoring changed section attributes for %s"
 msgstr "%s için değişmiş bölüm öznitelikleri yoksayıldı"
 
-#: config/obj-elf.c:788
+#: config/obj-elf.c:682
 #, c-format
 msgid "ignoring changed section entity size for %s"
 msgstr "%s için değişmiş bölüm öznitelikleri yoksayıldı"
 
-#: config/obj-elf.c:791
-#, c-format
-msgid "ignoring new section group for %s"
-msgstr "%s için yeni bölüm grubu yoksayıldı"
-
-#: config/obj-elf.c:845
+#: config/obj-elf.c:735
 msgid "unrecognized .section attribute: want a,w,x,M,S,G,T"
 msgstr "Bilinmeyen .section özniteliği: a,w,x,M,S,G,T olabilir"
 
-#: config/obj-elf.c:884
+#: config/obj-elf.c:772
 msgid "unrecognized section attribute"
 msgstr "Bilinmeyen bölüm özniteliği"
 
-#: config/obj-elf.c:906 read.c:2545
+#: config/obj-elf.c:800 read.c:2528
 msgid "unrecognized section type"
 msgstr "bilinmeyen bölüm türü"
 
-#: config/obj-elf.c:936
+#: config/obj-elf.c:830
 msgid "missing name"
 msgstr "isim eksik"
 
-#: config/obj-elf.c:1048
+#: config/obj-elf.c:941
 msgid "invalid merge entity size"
 msgstr "geçersiz nesne boy birleştirmesi"
 
-#: config/obj-elf.c:1055
+#: config/obj-elf.c:948
 msgid "entity size for SHF_MERGE not specified"
 msgstr "SHF_MERGE için nesne boyu belirtilmemiş"
 
-#: config/obj-elf.c:1075
+#: config/obj-elf.c:968
 msgid "group name for SHF_GROUP not specified"
 msgstr "SHF_GROUP için grup adı belirtilmemiş"
 
-#: config/obj-elf.c:1088
+#: config/obj-elf.c:981
 msgid "character following name is not '#'"
 msgstr "ismi takip eden karakter '#' deÄŸil"
 
-#: config/obj-elf.c:1189
+#: config/obj-elf.c:1078
 msgid ".previous without corresponding .section; ignored"
 msgstr ".section ile eşleşmeyen .previous; yoksayıldı"
 
-#: config/obj-elf.c:1216
+#: config/obj-elf.c:1104
 msgid ".popsection without corresponding .pushsection; ignored"
 msgstr ".pushsection ile eşleşmeyen .popsection; yoksayıldı"
 
-#: config/obj-elf.c:1270
+#: config/obj-elf.c:1156
 msgid "expected comma after name in .symver"
 msgstr ".symver'de isimden sonra virgül beklendi"
 
-#: config/obj-elf.c:1294
+#: config/obj-elf.c:1180
 #, c-format
 msgid "missing version name in `%s' for symbol `%s'"
 msgstr "`%s' içinde `%s' sembolü için eksik sürüm ismi"
 
-#: config/obj-elf.c:1305
+#: config/obj-elf.c:1191
 #, c-format
 msgid "multiple versions [`%s'|`%s'] for symbol `%s'"
 msgstr "`%3$s' sembolü için çoklu sürüm [`%1$s'|`%2$s']"
 
-#: config/obj-elf.c:1541
+#: config/obj-elf.c:1421
 msgid "expected quoted string"
 msgstr "Tırnak içinde bir dizge beklendi"
 
-#: config/obj-elf.c:1562
+#: config/obj-elf.c:1441
 #, c-format
 msgid "expected comma after name `%s' in .size directive"
 msgstr ".size yönergesinde `%s' isminden sonra virgül beklendi"
 
-#: config/obj-elf.c:1571
+#: config/obj-elf.c:1450
 msgid "missing expression in .size directive"
 msgstr ".size yönergesinde eksik ifade"
 
-#: config/obj-elf.c:1660
+#: config/obj-elf.c:1537
 #, c-format
 msgid "unrecognized symbol type \"%s\""
 msgstr "\"%s\" bilinmeyen sembol türü"
 
-#: config/obj-elf.c:1841
+#: config/obj-elf.c:1705
 msgid ".size expression too complicated to fix up"
 msgstr ".size ifadesi düzeltme için çok karmaşık"
 
-#: config/obj-elf.c:1873
+#: config/obj-elf.c:1737
 #, c-format
 msgid "invalid attempt to declare external version name as default in symbol `%s'"
 msgstr "`%s' sembolünde dış sürüm ismini öntanımlı olarak tanımlama girişimi geçersiz"
 
-#: config/obj-elf.c:1934 ecoff.c:3642
+#: config/obj-elf.c:1798 ecoff.c:3598
 #, c-format
 msgid "symbol `%s' can not be both weak and common"
 msgstr "`%s' sembolü hem zayıf hem ortak olamaz"
 
-#: config/obj-elf.c:2054
+#: config/obj-elf.c:1905
 #, c-format
 msgid "assuming all members of group `%s' are COMDAT"
 msgstr "`%s' grubunun bütün öğelerinin COMDAT olduğu varsayıldı"
 
-#: config/obj-elf.c:2076
+#: config/obj-elf.c:1927
 #, c-format
 msgid "can't create group: %s"
 msgstr "%s grubu oluşturulamadı"
 
-#: config/obj-elf.c:2183
+#: config/obj-elf.c:2036
 #, c-format
 msgid "failed to set up debugging information: %s"
 msgstr "Hata ayıklama bilgisi oluşturma başarısız: %s"
 
-#: config/obj-elf.c:2203
+#: config/obj-elf.c:2056
 #, c-format
 msgid "can't start writing .mdebug section: %s"
 msgstr ".mdebug bölümü yazılamıyor: %s"
 
-#: config/obj-elf.c:2211
+#: config/obj-elf.c:2064
 #, c-format
 msgid "could not write .mdebug section: %s"
 msgstr ".mdebug bölümü yazılamadı: %s"
 
-#: config/obj-ieee.c:455
+#: config/obj-elf.h:140
+#, fuzzy, c-format
+msgid "can't allocate ELF private section data: %s"
+msgstr "%s bölümü oluşturulamıyor"
+
+#: config/obj-ieee.c:449
 msgid "too many sections"
 msgstr "çok fazla sayıda bölüm"
 
-#: config/obj-som.c:138
+#: config/obj-som.c:140
 msgid "Only one .version pseudo-op per file!"
 msgstr "Her dosyada bir adet .version pseudo-op olabilir!"
 
-#: config/obj-som.c:155 config/obj-som.c:201
+#: config/obj-som.c:157 config/obj-som.c:203
 msgid "Expected quoted string"
 msgstr "Tırnak içinde bir dizge beklendi"
 
-#: config/obj-som.c:164
+#: config/obj-som.c:166
 #, c-format
 msgid "FATAL: Attaching version header %s"
 msgstr "ÖLÜMCÜL: Sürüm başlığı %s ekte"
 
-#: config/obj-som.c:184
+#: config/obj-som.c:186
 msgid "Only one .copyright pseudo-op per file!"
 msgstr "Her dosyada bir adet .copyright pseudo-op olabilir!"
 
-#: config/obj-som.c:210
+#: config/obj-som.c:212
 #, c-format
 msgid "FATAL: Attaching copyright header %s"
 msgstr "ÖLÜMCÜL: Telif hakkı başlığı %s ekte"
 
-#: config/obj-vms.c:530
+#: config/obj-vms.c:367
 #, c-format
 msgid "compiler emitted zero-size common symbol `%s' already defined"
 msgstr "derleyici tarafından oluşturulan sıfır boylu ortak sembol `%s' önceden tanımlı"
 
-#: config/obj-vms.c:540
+#: config/obj-vms.c:375
 #, c-format
 msgid "compiler redefined zero-size common symbol `%s'"
 msgstr "derleyici tarafından tekrar tanımlanan sıfır boylu ortak sembol `%s'"
 
-#: config/obj-vms.c:663
+#: config/obj-vms.c:482
 #, c-format
 msgid "Couldn't create VMS object file \"%s\""
 msgstr "VMS nesne dosyası \"%s\" oluşturulamadı"
 
-#: config/obj-vms.c:688
+#: config/obj-vms.c:507
 msgid "I/O error writing VMS object file (length prefix)"
 msgstr "VMS nesne dosyası yazılırken G/Ç (I/O) hatası (uzunluk öneki)"
 
-#: config/obj-vms.c:702
+#: config/obj-vms.c:521
 msgid "I/O error writing VMS object file"
 msgstr "VMS nesne dosyası yazılırken G/Ç hatası (I/O)"
 
-#: config/obj-vms.c:1292
+#: config/obj-vms.c:1057
 #, c-format
-msgid "Couldn't find source file \"%s\", dUmMy=%%X%x"
+msgid "Couldn't find source file \"%s\", status=%%X%x"
 msgstr "Kaynak dosyası \"%s\" bulunamadı, durum=%%X%x"
 
-#: config/obj-vms.c:1790 config/obj-vms.c:2967
+#: config/obj-vms.c:1505 config/obj-vms.c:2677
 #, c-format
 msgid "debugger forward reference error, dbx type %d"
 msgstr "hata ayıklayıcı öne referans hatası, dbx türü %d"
 
-#: config/obj-vms.c:1865
+#: config/obj-vms.c:1579
 #, c-format
 msgid "Variable descriptor %d too complicated.  Defined as `void *'."
 msgstr "%d değişken betimleyicisi fazla karmaşık. `void *' olarak tanımlandı."
 
-#: config/obj-vms.c:2179
+#: config/obj-vms.c:1894
 msgid ""
 "***Warning - the assembly code generated by the compiler has placed \n"
 " global constant(s) in the text psect.  These will not be available to \n"
@@ -935,94 +953,85 @@ msgstr ""
 "veya 2) kaynak kodlarınızda evrensel değişken tanımlarından 'const' anahtar\n"
 "kelimesini kaldırmak. Sonra uyarılmadığınızı söylemeyin!\n"
 
-#: config/obj-vms.c:2494
+#: config/obj-vms.c:2199
 #, c-format
 msgid "debugginer output: %d is an unknown untyped variable."
 msgstr "Hata ayıklayıcı çıktısı: %d, bilinmeyen, türlenmemiş bir değişken."
 
-#: config/obj-vms.c:2712
+#: config/obj-vms.c:2419
 #, c-format
 msgid "debugger output: structure element `%s' has undefined type"
 msgstr "Hata ayıklayıcı çıktısı: yapı öğesi `%s', tanımsız türe sahip"
 
-#: config/obj-vms.c:2823
+#: config/obj-vms.c:2530
 #, c-format
 msgid "debugger output: %d is an unknown type of variable."
 msgstr "Hata ayıklayıcı çıktısı: %d bilinmeyen bir tür değişken."
 
-#: config/obj-vms.c:2956
+#: config/obj-vms.c:2666
 #, c-format
 msgid "debugger output: Unable to resolve %d circular references."
 msgstr "Hata ayıklayıcı çıktısı: %d çevrimsel referans çözümlenemedi."
 
-#: config/obj-vms.c:3158
+#: config/obj-vms.c:2854
 #, c-format
 msgid "Module name truncated: %s\n"
 msgstr "Modül ismi budandı: %s\n"
 
-#: config/obj-vms.c:3436
+#: config/obj-vms.c:3096
 #, c-format
 msgid "Symbol %s replaced by %s\n"
 msgstr "%s sembolü %s ile değiştirildi\n"
 
 #. impossible
-#: config/obj-vms.c:3719
+#: config/obj-vms.c:3322
 #, c-format
 msgid "Unknown VMS psect type (%ld)"
 msgstr "Bilinmeyen VMS psect türü (%ld)"
 
-#: config/obj-vms.c:3760
+#: config/obj-vms.c:3360
 #, c-format
 msgid "Globalsymbol attribute for symbol %s was unexpected."
 msgstr "%s sembolü için evrensel sembol özniteliği beklenmiyordu."
 
-#: config/obj-vms.c:3909
+#: config/obj-vms.c:3484
 msgid "Invalid data type for globalvalue"
 msgstr "Evrensel değer (globalvalue) için geçersiz veri türü"
 
-#: config/obj-vms.c:3921
+#: config/obj-vms.c:3496
 #, c-format
 msgid "Invalid globalvalue of %s"
 msgstr "%s'nin evrensel değeri (globalvalue) geçersiz"
 
-#: config/obj-vms.c:4271
+#: config/obj-vms.c:3736
 msgid "Couldn't find fixup fragment when checking for indirect reference"
 msgstr "Endirekt referans için düzeltme fragmanı bulunamadı"
 
-#: config/obj-vms.c:4614 config/obj-vms.c:4757
+#: config/obj-vms.c:4014 config/obj-vms.c:4149
 msgid "Fixup data addsy and subsy don't have the same type"
 msgstr "Düzeltme verisi addsy ve subsy aynı türden değil"
 
-#: config/obj-vms.c:4618 config/obj-vms.c:4761
+#: config/obj-vms.c:4018 config/obj-vms.c:4153
 msgid "Fixup data addsy and subsy don't have an appropriate type"
 msgstr "Düzeltme verisi addsy ve subsy uygun bir türden değil"
 
-#: config/obj-vms.c:4621 config/obj-vms.c:4764
+#: config/obj-vms.c:4021 config/obj-vms.c:4156
 msgid "Fixup data is erroneously \"pcrel\""
 msgstr "Düzeltme verisi hatalı olarak \"pcrel\""
 
-#: config/obj-vms.c:4637 config/obj-vms.c:4783
+#: config/obj-vms.c:4037 config/obj-vms.c:4173
 msgid "Fixup datum is not a longword"
 msgstr "Düzeltme verisi longword değil"
 
-#: config/obj-vms.c:4641 config/obj-vms.c:4787
+#: config/obj-vms.c:4041 config/obj-vms.c:4177
 msgid "Fixup datum is not \"fixP->fx_addsy\""
 msgstr "Düzeltme verisi \"fixP->fx_addsy\" değil"
 
-#: config/obj-vms.c:4858
-#, c-format
-msgid ""
-"g++ wrote an extern reference to `%s' as a routine.\n"
-"I will fix it, but I hope that it was note really a routine."
-msgstr ""
-"g++, `%s'a extern referansını bir işlev tanımı olarak yazdı.\n"
-"Bu düzeltildi, fakat gerçekten bir işlev ise, hatalı sonuç verecek."
-
-#: config/obj-vms.c:4990
+#: config/obj-vms.c:4353
 msgid "Can't handle global xtors symbols yet."
 msgstr "Evrensel xtors sembolleri henüz desteklenmiyor."
 
-#: config/obj-vms.c:4993
+#: config/obj-vms.c:4356
 #, c-format
 msgid "Unknown %s"
 msgstr "Bilinmeyen %s"
@@ -1030,120 +1039,120 @@ msgstr "Bilinmeyen %s"
 #.
 #. *	Error otherwise.
 #.
-#: config/obj-vms.c:5078
+#: config/obj-vms.c:4441
 #, c-format
 msgid "unhandled stab type %d"
 msgstr "desteklenmeyen stab türü %d"
 
-#: config/tc-a29k.c:163 config/tc-sparc.c:3983
+#: config/tc-a29k.c:164 config/tc-sparc.c:4028
 msgid "Unknown segment type"
 msgstr "Bilinmeyen bölüm türü"
 
 #. Probably a memory allocation problem?  Give up now.
-#: config/tc-a29k.c:333 config/tc-dlx.c:369 config/tc-hppa.c:1463
-#: config/tc-mips.c:1107 config/tc-mips.c:1149 config/tc-or32.c:228
-#: config/tc-sparc.c:853
+#: config/tc-a29k.c:334 config/tc-dlx.c:331 config/tc-hppa.c:1480
+#: config/tc-mips.c:1152 config/tc-mips.c:1194 config/tc-or32.c:228
+#: config/tc-sparc.c:858
 msgid "Broken assembler.  No assembly attempted."
 msgstr "Çalışmayan çevirici. Çevrilmedi."
 
-#: config/tc-a29k.c:378 config/tc-avr.c:1121 config/tc-d10v.c:545
-#: config/tc-d30v.c:551 config/tc-h8300.c:492 config/tc-h8500.c:283
-#: config/tc-mcore.c:607 config/tc-mmix.c:470 config/tc-mn10200.c:940
-#: config/tc-mn10300.c:1815 config/tc-msp430.c:1544 config/tc-or32.c:334
-#: config/tc-or32.c:390 config/tc-ppc.c:2334 config/tc-s390.c:1236
-#: config/tc-sh.c:1264 config/tc-sh64.c:2254 config/tc-tic80.c:279
-#: config/tc-v850.c:2025 config/tc-w65.c:218 config/tc-z8k.c:376
+#: config/tc-a29k.c:379 config/tc-avr.c:1179 config/tc-d10v.c:545
+#: config/tc-d30v.c:552 config/tc-h8300.c:470 config/tc-h8500.c:283
+#: config/tc-mcore.c:608 config/tc-mmix.c:502 config/tc-mn10200.c:940
+#: config/tc-mn10300.c:1820 config/tc-msp430.c:407 config/tc-or32.c:334
+#: config/tc-or32.c:390 config/tc-ppc.c:2367 config/tc-s390.c:1218
+#: config/tc-sh64.c:2213 config/tc-sh.c:1240 config/tc-tic80.c:280
+#: config/tc-v850.c:2034 config/tc-w65.c:215 config/tc-z8k.c:331
 msgid "missing operand"
 msgstr "iÅŸlenen eksik"
 
-#: config/tc-a29k.c:417 config/tc-cris.c:1075 config/tc-cris.c:1083
-#: config/tc-dlx.c:834 config/tc-hppa.c:1599 config/tc-i860.c:453
-#: config/tc-i860.c:470 config/tc-i860.c:930 config/tc-sparc.c:1415
-#: config/tc-sparc.c:1421
+#: config/tc-a29k.c:418 config/tc-cris.c:1515 config/tc-cris.c:1523
+#: config/tc-crx.c:2028 config/tc-dlx.c:808 config/tc-hppa.c:1616
+#: config/tc-i860.c:492 config/tc-i860.c:509 config/tc-i860.c:989
+#: config/tc-sparc.c:1420 config/tc-sparc.c:1426
 #, c-format
 msgid "Unknown opcode: `%s'"
 msgstr "Bilinmeyen opkod: `%s'"
 
-#: config/tc-a29k.c:422 config/tc-dlx.c:852
+#: config/tc-a29k.c:423 config/tc-dlx.c:826
 #, c-format
 msgid "Unknown opcode `%s'."
 msgstr "Bilinmeyen opkod `%s'."
 
-#: config/tc-a29k.c:454 config/tc-dlx.c:913
+#: config/tc-a29k.c:455 config/tc-dlx.c:887
 #, c-format
 msgid "Too many operands: %s"
 msgstr "Çok fazla işlenen: %s"
 
-#: config/tc-a29k.c:476 config/tc-a29k.c:507
+#: config/tc-a29k.c:477 config/tc-a29k.c:508
 #, c-format
 msgid "Immediate value of %ld is too large"
 msgstr "%ld'nin şimdiki değeri fazla büyük"
 
-#: config/tc-a29k.c:546 config/tc-i860.c:355 config/tc-i860.c:902
-#: config/tc-m68k.c:3171 config/tc-m68k.c:3200 config/tc-sparc.c:2647
+#: config/tc-a29k.c:547 config/tc-i860.c:395 config/tc-i860.c:940
+#: config/tc-m68k.c:3485 config/tc-m68k.c:3517 config/tc-sparc.c:2658
 msgid "failed sanity check."
 msgstr "başarısız kontrol."
 
-#: config/tc-a29k.c:892 config/tc-or32.c:1044 config/tc-or32.c:1178
+#: config/tc-a29k.c:891 config/tc-or32.c:1023 config/tc-or32.c:1147
 #, c-format
 msgid "bad relocation type: 0x%02x"
 msgstr "hatalı yerdeğişim türü: 0x%02x"
 
-#: config/tc-a29k.c:919
+#: config/tc-a29k.c:918
 #, c-format
 msgid "need %o3\n"
 msgstr "%o3 gerekli\n"
 
-#: config/tc-a29k.c:935
+#: config/tc-a29k.c:934
 msgid "a29k_convert_frag\n"
 msgstr "a29k_convert_frag\n"
 
-#: config/tc-a29k.c:944
+#: config/tc-a29k.c:943
 msgid "a29k_estimate_size_before_relax\n"
 msgstr "a29k_estimate_size_before_relax\n"
 
-#: config/tc-a29k.c:1095 config/tc-dlx.c:1283 config/tc-or32.c:1373
+#: config/tc-a29k.c:1037 config/tc-dlx.c:1251 config/tc-or32.c:1342
 #, c-format
 msgid "label \"$%d\" redefined"
 msgstr "\"$%d\" etiketi yeniden tanımlandı"
 
-#: config/tc-a29k.c:1168 config/tc-dlx.c:511 config/tc-or32.c:1466
+#: config/tc-a29k.c:1110 config/tc-dlx.c:485 config/tc-or32.c:1435
 #, c-format
 msgid "Invalid expression after %%%%\n"
 msgstr "%%%%'den sonra geçersiz ifade\n"
 
-#: config/tc-a29k.c:1179
+#: config/tc-a29k.c:1121
 msgid "Invalid register in & expression"
 msgstr "& ifadesinde geçersiz yazmaç"
 
-#: config/tc-alpha.c:826
+#: config/tc-alpha.c:802
 #, c-format
 msgid "internal error: can't hash opcode `%s': %s"
 msgstr "İç hata: `%s' opkodu hash'lenemedi: %s"
 
-#: config/tc-alpha.c:860
+#: config/tc-alpha.c:836
 #, c-format
 msgid "internal error: can't hash macro `%s': %s"
 msgstr "İç hata: `%s' makrosu hash'lenemedi: %s"
 
-#: config/tc-alpha.c:943 config/tc-i960.c:2707 config/tc-xtensa.c:4954
-#: config/tc-xtensa.c:5015
+#: config/tc-alpha.c:919 config/tc-i960.c:2712 config/tc-xtensa.c:5191
+#: config/tc-xtensa.c:5260 config/tc-xtensa.c:5311
 msgid "syntax error"
 msgstr "sözdizimi hatası"
 
-#: config/tc-alpha.c:1017 config/tc-h8300.c:2099 config/tc-h8500.c:1204
-#: config/tc-hppa.c:4018 config/tc-i860.c:1004 config/tc-m68hc11.c:568
-#: config/tc-m68k.c:4196 config/tc-m88k.c:991 config/tc-ns32k.c:1689
-#: config/tc-or32.c:910 config/tc-sparc.c:2934 config/tc-z8k.c:1371
+#: config/tc-alpha.c:993 config/tc-h8300.c:2092 config/tc-h8500.c:1204
+#: config/tc-hppa.c:4033 config/tc-i860.c:1059 config/tc-m68hc11.c:558
+#: config/tc-m68k.c:4576 config/tc-m88k.c:991 config/tc-ns32k.c:1689
+#: config/tc-or32.c:902 config/tc-sparc.c:2945 config/tc-z8k.c:1328
 msgid "Bad call to MD_ATOF()"
 msgstr "MD_ATOF()'a hatalı çağrı"
 
-#: config/tc-alpha.c:1067
+#: config/tc-alpha.c:1043
 #, c-format
 msgid "Unknown CPU identifier `%s'"
 msgstr "Bilinmeyen CPU tanımlayıcısı `%s'"
 
-#: config/tc-alpha.c:1111
+#: config/tc-alpha.c:1087
 msgid ""
 "Alpha options:\n"
 "-32addr\t\t\ttreat addresses as 32-bit values\n"
@@ -1161,7 +1170,7 @@ msgstr ""
 "-m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b\n"
 "\t\t\tbu alt mimariler PALcode opkodları içerir\n"
 
-#: config/tc-alpha.c:1121
+#: config/tc-alpha.c:1097
 msgid ""
 "VMS options:\n"
 "-+\t\t\thash encode (don't truncate) names longer than 64 characters\n"
@@ -1171,1521 +1180,1785 @@ msgstr ""
 "-+\t\t\t64 karakterden uzun isimleri hash ile kodlar (budamaz)\n"
 "-H\t\t\thash budamasından sonra yeni sembolü gösterir\n"
 
-#: config/tc-alpha.c:1298
+#: config/tc-alpha.c:1274
 #, c-format
 msgid "unhandled relocation type %s"
 msgstr "desteklenmeyen yerdeğişim türü %s"
 
-#: config/tc-alpha.c:1311
+#: config/tc-alpha.c:1287
 msgid "non-absolute expression in constant field"
 msgstr "sabit alanda sabit olmayan ifade"
 
-#: config/tc-alpha.c:1325
+#: config/tc-alpha.c:1301
 #, c-format
 msgid "type %d reloc done?\n"
 msgstr "tür %d yerdeğişim tamam mı?\n"
 
-#: config/tc-alpha.c:1373 config/tc-alpha.c:1380 config/tc-mips.c:8602
+#: config/tc-alpha.c:1349 config/tc-alpha.c:1356 config/tc-mips.c:8442
 msgid "Used $at without \".set noat\""
 msgstr "\".set noat\" olmaksızın $at kullanıldı"
 
-#: config/tc-alpha.c:1542
+#: config/tc-alpha.c:1518
 #, c-format
 msgid "!samegp reloc against symbol without .prologue: %s"
 msgstr ".prologue olmaksızın sembole !samegp yerdeğişimi: %s"
 
-#: config/tc-alpha.c:1581 config/tc-xtensa.c:5451
+#: config/tc-alpha.c:1557 config/tc-xtensa.c:5831
 #, c-format
 msgid "cannot represent `%s' relocation in object file"
 msgstr "Nesne dosyasında `%s' yerdeğişimi gösterilemiyor"
 
-#: config/tc-alpha.c:1588 config/tc-xtensa.c:5458
+#: config/tc-alpha.c:1564 config/tc-xtensa.c:5839
 #, c-format
 msgid "internal error? cannot generate `%s' relocation"
 msgstr "iç hata? `%s' yerdeğişimi üretilemedi"
 
-#: config/tc-alpha.c:1642
+#: config/tc-alpha.c:1618
 #, c-format
 msgid "frame reg expected, using $%d."
 msgstr "frame reg beklendi, $%d kullanılıyor."
 
-#: config/tc-alpha.c:1743
+#: config/tc-alpha.c:1719
 #, c-format
 msgid "No !literal!%ld was found"
 msgstr "!literal!%ld bulunamadı"
 
-#: config/tc-alpha.c:1750
+#: config/tc-alpha.c:1726
 #, c-format
 msgid "No !tlsgd!%ld was found"
 msgstr "!tlsgd!%ld bulunamadı"
 
-#: config/tc-alpha.c:1757
+#: config/tc-alpha.c:1733
 #, c-format
 msgid "No !tlsldm!%ld was found"
 msgstr "!tlsldm!%ld bulunamadı"
 
-#: config/tc-alpha.c:1766
+#: config/tc-alpha.c:1742
 #, c-format
 msgid "No ldah !gpdisp!%ld was found"
 msgstr "ldah !gpdisp!%ld bulunamadı"
 
-#: config/tc-alpha.c:1816
+#: config/tc-alpha.c:1792
 #, c-format
 msgid "too many !literal!%ld for %s"
 msgstr "%2$s için çok fazla !literal!%1$ld "
 
-#: config/tc-alpha.c:1846
+#: config/tc-alpha.c:1822
 #, c-format
 msgid "No lda !gpdisp!%ld was found"
 msgstr "lda !gpdisp!%ld bulunamadı"
 
 #. Only support one relocation op per insn.
-#: config/tc-alpha.c:1994
+#: config/tc-alpha.c:1970
 msgid "More than one relocation op per insn"
 msgstr "Bir işlemde birden fazla yerdeğişim yönergesi"
 
-#: config/tc-alpha.c:2010
+#: config/tc-alpha.c:1986
 msgid "No relocation operand"
 msgstr "YerdeÄŸiÅŸim iÅŸleneni yok"
 
-#: config/tc-alpha.c:2020
+#: config/tc-alpha.c:1996
 #, c-format
 msgid "Unknown relocation operand: !%s"
 msgstr "Bilinmeyen yerdeÄŸiÅŸim iÅŸleneni: !%s"
 
-#: config/tc-alpha.c:2030
+#: config/tc-alpha.c:2006
 #, c-format
 msgid "no sequence number after !%s"
 msgstr "!%s'den sonra sıra numarası yok"
 
-#: config/tc-alpha.c:2040
+#: config/tc-alpha.c:2016
 #, c-format
 msgid "!%s does not use a sequence number"
 msgstr "!%s bir sıra numarası kullanmıyor"
 
-#: config/tc-alpha.c:2050
+#: config/tc-alpha.c:2026
 #, c-format
 msgid "Bad sequence number: !%s!%s"
 msgstr "Hatalı sıra numarası: !%s!%s"
 
-#: config/tc-alpha.c:2378
-#, c-format
-msgid "operand out of range (%s not between %d and %d)"
-msgstr "işlenen kapsam dışı (%s, %d ve %d arasında değil)"
+#: config/tc-alpha.c:2352 config/tc-arc.c:331 config/tc-mn10200.c:1344
+#: config/tc-mn10300.c:2601 config/tc-ppc.c:1461 config/tc-s390.c:612
+#: config/tc-v850.c:1644
+#, fuzzy
+msgid "operand"
+msgstr "Hatalı işlenen"
 
-#: config/tc-alpha.c:2490 config/tc-alpha.c:2514 config/tc-d10v.c:634
-#: config/tc-d30v.c:639 config/tc-mn10200.c:995 config/tc-mn10300.c:1888
-#: config/tc-ppc.c:2300 config/tc-ppc.c:2517 config/tc-ppc.c:2529
-#: config/tc-s390.c:1246 config/tc-s390.c:1346 config/tc-s390.c:1442
-#: config/tc-v850.c:1805 config/tc-v850.c:1828 config/tc-v850.c:2048
+#: config/tc-alpha.c:2456 config/tc-alpha.c:2480 config/tc-d10v.c:634
+#: config/tc-d30v.c:640 config/tc-mn10200.c:995 config/tc-mn10300.c:1893
+#: config/tc-ppc.c:2333 config/tc-ppc.c:2550 config/tc-ppc.c:2562
+#: config/tc-s390.c:1228 config/tc-s390.c:1328 config/tc-s390.c:1424
+#: config/tc-v850.c:1821 config/tc-v850.c:1844 config/tc-v850.c:2057
 msgid "too many fixups"
 msgstr "çok fazla düzeltme"
 
-#: config/tc-alpha.c:2526
+#: config/tc-alpha.c:2492
 msgid "invalid relocation for instruction"
 msgstr "işlem için geçersiz yerdeğişim"
 
-#: config/tc-alpha.c:2537
+#: config/tc-alpha.c:2503
 msgid "invalid relocation for field"
 msgstr "Alan için geçersiz yerdeğişim"
 
-#: config/tc-alpha.c:2642
+#: config/tc-alpha.c:2608
 #, c-format
 msgid "too many ldah insns for !gpdisp!%ld"
 msgstr "!gpdisp!%ld için çok fazla ldah işlemi"
 
-#: config/tc-alpha.c:2644 config/tc-alpha.c:2656
+#: config/tc-alpha.c:2610 config/tc-alpha.c:2622
 #, c-format
 msgid "both insns for !gpdisp!%ld must be in the same section"
 msgstr "!gpdisp!%ld için her iki işlem de aynı bölümde olmalı"
 
-#: config/tc-alpha.c:2654
+#: config/tc-alpha.c:2620
 #, c-format
 msgid "too many lda insns for !gpdisp!%ld"
 msgstr "!gpdisp!%ld için çok fazla lda işlemi"
 
-#: config/tc-alpha.c:2707
+#: config/tc-alpha.c:2673
 #, c-format
 msgid "too many lituse insns for !lituse_tlsgd!%ld"
 msgstr "!lituse_tlsgd!%ld için çok fazla lituse işlemi"
 
-#: config/tc-alpha.c:2710
+#: config/tc-alpha.c:2676
 #, c-format
 msgid "too many lituse insns for !lituse_tlsldm!%ld"
 msgstr "!lituse_tlsldm!%ld için çok fazla lituse işlemi"
 
-#: config/tc-alpha.c:2727
+#: config/tc-alpha.c:2693
 #, c-format
 msgid "duplicate !tlsgd!%ld"
 msgstr "birden fazla !tlsgd!%ld"
 
-#: config/tc-alpha.c:2729
+#: config/tc-alpha.c:2695
 #, c-format
 msgid "sequence number in use for !tlsldm!%ld"
 msgstr "!tlsldm!%ld'nın sıra numarası kullanılmakta"
 
-#: config/tc-alpha.c:2743
+#: config/tc-alpha.c:2709
 #, c-format
 msgid "duplicate !tlsldm!%ld"
 msgstr "birden fazla !tlsldm!%ld"
 
-#: config/tc-alpha.c:2745
+#: config/tc-alpha.c:2711
 #, c-format
 msgid "sequence number in use for !tlsgd!%ld"
 msgstr "!tlsgd!%ld sıra numarası kullanılmakta"
 
-#: config/tc-alpha.c:2790 config/tc-alpha.c:2863
+#: config/tc-alpha.c:2756 config/tc-alpha.c:2829
 #, c-format
 msgid "inappropriate arguments for opcode `%s'"
 msgstr "`%s' opkodu için uygun olmayan argümanlar"
 
-#: config/tc-alpha.c:2792 config/tc-alpha.c:2865
+#: config/tc-alpha.c:2758 config/tc-alpha.c:2831
 #, c-format
 msgid "opcode `%s' not supported for target %s"
 msgstr "%2$s hedefi için `%1$s' opkodu desteklenmiyor"
 
-#: config/tc-alpha.c:2796 config/tc-alpha.c:2869 config/tc-avr.c:1087
-#: config/tc-msp430.c:446
+#: config/tc-alpha.c:2762 config/tc-alpha.c:2835 config/tc-avr.c:1145
+#: config/tc-msp430.c:1777
 #, c-format
 msgid "unknown opcode `%s'"
 msgstr "bilinmeyen opkod `%s'"
 
-#: config/tc-alpha.c:2916
+#: config/tc-alpha.c:2882
 msgid "can not resolve expression"
 msgstr "ifade çözümlenemedi"
 
-#: config/tc-alpha.c:3060 config/tc-alpha.c:3239
+#: config/tc-alpha.c:3026 config/tc-alpha.c:3205
 msgid "overflow in literal (.lita) table"
 msgstr "literal (.lita) tablosunda taÅŸma"
 
-#: config/tc-alpha.c:3067 config/tc-alpha.c:3090 config/tc-alpha.c:3252
-#: config/tc-alpha.c:3467 config/tc-alpha.c:3512 config/tc-alpha.c:3586
-#: config/tc-alpha.c:3678 config/tc-alpha.c:3926 config/tc-alpha.c:4025
+#: config/tc-alpha.c:3033 config/tc-alpha.c:3056 config/tc-alpha.c:3218
+#: config/tc-alpha.c:3433 config/tc-alpha.c:3478 config/tc-alpha.c:3552
+#: config/tc-alpha.c:3644 config/tc-alpha.c:3892 config/tc-alpha.c:3991
 msgid "macro requires $at register while noat in effect"
 msgstr "makro $at yazmacını gerektiriyor ama noat geçerli"
 
-#: config/tc-alpha.c:3069 config/tc-alpha.c:3092 config/tc-alpha.c:3254
+#: config/tc-alpha.c:3035 config/tc-alpha.c:3058 config/tc-alpha.c:3220
 msgid "macro requires $at while $at in use"
 msgstr "makro, $at kullanımdayken $at gerektiriyor"
 
-#: config/tc-alpha.c:3200
+#: config/tc-alpha.c:3166
 msgid "bignum invalid; zero assumed"
 msgstr "bignum geçersiz; 0 varsayıldı"
 
-#: config/tc-alpha.c:3202
+#: config/tc-alpha.c:3168
 msgid "floating point number invalid; zero assumed"
 msgstr "kayan nokta sayısı geçersiz; sıfır varsayıldı"
 
-#: config/tc-alpha.c:3207
+#: config/tc-alpha.c:3173
 msgid "can't handle expression"
 msgstr "ifade iÅŸlenemedi"
 
-#: config/tc-alpha.c:3245
+#: config/tc-alpha.c:3211
 msgid "overflow in literal (.lit8) table"
 msgstr "literal (.lit8) tablosunda taÅŸma"
 
-#: config/tc-alpha.c:4262 config/tc-ppc.c:1740 config/tc-ppc.c:4271
+#: config/tc-alpha.c:4228 config/tc-ppc.c:1766 config/tc-ppc.c:4358
 #, c-format
 msgid ".COMMon length (%ld.) <0! Ignored."
 msgstr ".COMMon uzunluk (%ld.) <0! Yoksayıldı."
 
-#: config/tc-alpha.c:4291 config/tc-sparc.c:3799 config/tc-v850.c:256
+#: config/tc-alpha.c:4257 config/tc-sparc.c:3844 config/tc-v850.c:256
 msgid "Ignoring attempt to re-define symbol"
 msgstr "Sembolü yeniden tanımlama denemesi yoksayıldı"
 
-#: config/tc-alpha.c:4300 config/tc-alpha.c:4309 config/tc-ppc.c:4308
+#: config/tc-alpha.c:4266 config/tc-alpha.c:4275 config/tc-ppc.c:4395
+#: config/tc-sparc.c:3852
 #, c-format
 msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld."
 msgstr ".comm \"%s\" uzunluÄŸu zaten %ld. %ld olarak deÄŸiÅŸtirilmedi."
 
-#: config/tc-alpha.c:4430 ecoff.c:3082
+#: config/tc-alpha.c:4396 ecoff.c:3054
 msgid ".ent directive has no name"
 msgstr ".ent yönergesinin ismi yok"
 
-#: config/tc-alpha.c:4438
+#: config/tc-alpha.c:4404
 msgid "nested .ent directives"
 msgstr "içiçe .ent yönergeleri"
 
-#: config/tc-alpha.c:4483 ecoff.c:3032
+#: config/tc-alpha.c:4449 ecoff.c:3005
 msgid ".end directive has no name"
 msgstr ".end yönergesinin ismi yok"
 
-#: config/tc-alpha.c:4492
+#: config/tc-alpha.c:4458
 msgid ".end directive without matching .ent"
 msgstr "eşleşen .ent yönergesi olmaksızın .end yönergesi"
 
-#: config/tc-alpha.c:4494
+#: config/tc-alpha.c:4460
 msgid ".end directive names different symbol than .ent"
 msgstr ".end yönergesi .ent'ten farklı bir sembolü gösteriyor"
 
-#: config/tc-alpha.c:4538 ecoff.c:3171
+#: config/tc-alpha.c:4504 ecoff.c:3140
 msgid ".fmask outside of .ent"
 msgstr ".ent dışında .fmask"
 
-#: config/tc-alpha.c:4540 ecoff.c:3241
+#: config/tc-alpha.c:4506 ecoff.c:3204
 msgid ".mask outside of .ent"
 msgstr ".ent dışında .mask"
 
-#: config/tc-alpha.c:4548 ecoff.c:3178
+#: config/tc-alpha.c:4514 ecoff.c:3147
 msgid "bad .fmask directive"
 msgstr "hatalı .fmask yönergesi"
 
-#: config/tc-alpha.c:4550 ecoff.c:3248
+#: config/tc-alpha.c:4516 ecoff.c:3211
 msgid "bad .mask directive"
 msgstr "hatalı .mask yönergesi"
 
-#: config/tc-alpha.c:4584 config/tc-mips.c:14142 ecoff.c:3200
+#: config/tc-alpha.c:4550 config/tc-mips.c:13757 ecoff.c:3168
 msgid ".frame outside of .ent"
 msgstr ".ent dışında .frame"
 
-#: config/tc-alpha.c:4595 ecoff.c:3211
+#: config/tc-alpha.c:4561 ecoff.c:3179
 msgid "bad .frame directive"
 msgstr "hatalı .frame yönergesi"
 
-#: config/tc-alpha.c:4628
+#: config/tc-alpha.c:4594
 msgid ".prologue directive without a preceding .ent directive"
 msgstr "öncesinde .ent yönergesi olmaksızın .prologue yönergesi"
 
-#: config/tc-alpha.c:4646
+#: config/tc-alpha.c:4612
 #, c-format
 msgid "Invalid argument %d to .prologue."
 msgstr ".prologue için geçersiz %d argümanı."
 
-#: config/tc-alpha.c:4741
+#: config/tc-alpha.c:4707
 msgid "ECOFF debugging is disabled."
 msgstr "ECOFF hata ayıklaması etkinleştirilmemiş."
 
-#: config/tc-alpha.c:4755
+#: config/tc-alpha.c:4721
 msgid ".ent directive without matching .end"
 msgstr "eşleşen .end yönergesi olmaksızın .ent yönergesi"
 
-#: config/tc-alpha.c:4840
+#: config/tc-alpha.c:4806
 msgid ".usepv directive has no name"
 msgstr ".usepv yönergesinin ismi yok"
 
-#: config/tc-alpha.c:4851
+#: config/tc-alpha.c:4817
 msgid ".usepv directive has no type"
 msgstr ".usepv yönergesinin türü yok"
 
-#: config/tc-alpha.c:4866
+#: config/tc-alpha.c:4832
 msgid "unknown argument for .usepv"
 msgstr ".usepv için bilinmeyen argüman"
 
-#: config/tc-alpha.c:4900
+#: config/tc-alpha.c:4866
 msgid "Unknown section directive"
 msgstr "Bilinmeyen bölüm yönergesi"
 
-#: config/tc-alpha.c:4936
+#: config/tc-alpha.c:4902
 msgid ".ent directive has no symbol"
 msgstr ".ent yönergesinde sembol yok"
 
-#: config/tc-alpha.c:4963
+#: config/tc-alpha.c:4928
 msgid "Bad .frame directive 1./2. param"
 msgstr "Hatalı .frame yönergesi 1./2. parametre"
 
-#: config/tc-alpha.c:4975
+#: config/tc-alpha.c:4940
 msgid "Bad .frame directive 3./4. param"
 msgstr "Hatalı .frame yönergesi 3./4. parametre"
 
-#: config/tc-alpha.c:5000
+#: config/tc-alpha.c:4963
 msgid ".pdesc directive not in link (.link) section"
 msgstr ".pdesc yönergesi link (.link) bölümünde değil"
 
-#: config/tc-alpha.c:5008
+#: config/tc-alpha.c:4971
 msgid ".pdesc has no matching .ent"
 msgstr ".pdesc'le eÅŸleÅŸen .ent yok"
 
-#: config/tc-alpha.c:5019
+#: config/tc-alpha.c:4982
 msgid ".pdesc directive has no entry symbol"
 msgstr ".pdesc yönergesinin giriş sembolü yok"
 
-#: config/tc-alpha.c:5032
+#: config/tc-alpha.c:4995
 msgid "No comma after .pdesc <entryname>"
 msgstr ".pdesc <girişadı> sonrasında virgül yok"
 
-#: config/tc-alpha.c:5055
+#: config/tc-alpha.c:5018
 msgid "unknown procedure kind"
 msgstr "bilinmeyen yordam türü"
 
-#: config/tc-alpha.c:5148
+#: config/tc-alpha.c:5109
 msgid ".name directive not in link (.link) section"
 msgstr ".name yönergesi link (.link) bölümünde değil"
 
-#: config/tc-alpha.c:5156
+#: config/tc-alpha.c:5117
 msgid ".name directive has no symbol"
 msgstr ".name yönergesinde sembol yok"
 
-#: config/tc-alpha.c:5190
+#: config/tc-alpha.c:5149
 msgid "No symbol after .linkage"
 msgstr ".linkage'dan sonra sembol yok"
 
-#: config/tc-alpha.c:5218
+#: config/tc-alpha.c:5175
 msgid "No symbol after .code_address"
 msgstr ".code_address'ten sonra sembol yok"
 
-#: config/tc-alpha.c:5251
+#: config/tc-alpha.c:5205
 msgid "Bad .mask directive"
 msgstr "Hatalı .mask yönergesi"
 
-#: config/tc-alpha.c:5272
+#: config/tc-alpha.c:5224
 msgid "Bad .fmask directive"
 msgstr "Hatalı .fmask yönergesi"
 
-#: config/tc-alpha.c:5440
+#: config/tc-alpha.c:5386
 #, c-format
 msgid "Expected comma after name \"%s\""
 msgstr "\"%s\" isminden sonra virgül beklendi"
 
 #. *symbol_get_obj (symbolP) = (signed char) temp;
-#: config/tc-alpha.c:5451
+#: config/tc-alpha.c:5397
 #, c-format
 msgid "unhandled: .proc %s,%d"
 msgstr "Desteklenmiyor: .proc %s,%d"
 
-#: config/tc-alpha.c:5486
+#: config/tc-alpha.c:5432
 #, c-format
 msgid "Tried to .set unrecognized mode `%s'"
 msgstr "Bilinmeyen `%s' kipine atanmaya (.set) çalışıldı"
 
-#. not fatal, but it might not work in the end
-#: config/tc-alpha.c:5503
-msgid "File overrides no-base-register option."
-msgstr "Dosya no-base-register seçeneğini etkisizleştirdi"
-
-#: config/tc-alpha.c:5520
+#: config/tc-alpha.c:5457
 #, c-format
 msgid "Bad base register, using $%d."
 msgstr "Hatalı temel yazmaç, $%d kullanıldı."
 
-#: config/tc-alpha.c:5542
+#: config/tc-alpha.c:5479
 #, c-format
 msgid "Alignment too large: %d. assumed"
 msgstr "Hizalama fazla büyük: %d. varsayıldı"
 
-#: config/tc-alpha.c:5546 config/tc-d30v.c:2200
+#: config/tc-alpha.c:5483 config/tc-d30v.c:2183
 msgid "Alignment negative: 0 assumed"
 msgstr "Hizalama negatif: 0 varsayıldı"
 
-#: config/tc-alpha.c:5860
+#: config/tc-alpha.c:5790
 #, c-format
 msgid "Chose GP value of %lx\n"
 msgstr "GP değeri olarak %lx seçildi\n"
 
-#: config/tc-alpha.c:5876
+#: config/tc-alpha.c:5806
 msgid "Bad .section directive: want a,s,w,x,M,S,G,T in string"
 msgstr "Hatalı .section yönergesi: dizgede a,s,w,x,M,S,T olmalı"
 
-#: config/tc-arc.c:1615 config/tc-arm.c:11416 config/tc-ip2k.c:221
+#: config/tc-arc.c:1574 config/tc-arm.c:12232 config/tc-ip2k.c:219
 msgid "md_estimate_size_before_relax\n"
 msgstr "md_estimate_size_before_relax\n"
 
-#: config/tc-arc.c:1627
+#: config/tc-arc.c:1586
 msgid "md_convert_frag\n"
 msgstr "md_convert_frag\n"
 
 #. We can't actually support subtracting a symbol.
-#: config/tc-arc.c:1898 config/tc-arm.c:6617 config/tc-arm.c:9705
-#: config/tc-arm.c:9805 config/tc-avr.c:854 config/tc-cris.c:3123
-#: config/tc-d10v.c:1710 config/tc-d30v.c:1851 config/tc-mips.c:3629
-#: config/tc-mips.c:4694 config/tc-mips.c:5827 config/tc-mips.c:6516
-#: config/tc-msp430.c:1403 config/tc-ppc.c:5460 config/tc-v850.c:2357
-#: config/tc-xstormy16.c:483
+#: config/tc-arc.c:1856 config/tc-arm.c:6622 config/tc-arm.c:9378
+#: config/tc-arm.c:9470 config/tc-avr.c:891 config/tc-cris.c:3999
+#: config/tc-d10v.c:1708 config/tc-d30v.c:1836 config/tc-mips.c:3835
+#: config/tc-mips.c:4949 config/tc-mips.c:5881 config/tc-mips.c:6469
+#: config/tc-msp430.c:1871 config/tc-ppc.c:5542 config/tc-v850.c:2367
+#: config/tc-xstormy16.c:499
 msgid "expression too complex"
 msgstr "ifade fazla karmaşık"
 
-#: config/tc-arm.c:763
+#: config/tc-arm.c:758 config/tc-arm.c:14522
 msgid "ARM register expected"
 msgstr "ARM yazmacı beklendi"
 
-#: config/tc-arm.c:764 config/tc-arm.c:3174
+#: config/tc-arm.c:759
 msgid "bad or missing co-processor number"
 msgstr "Hatalı veya eksik yardımcı işlemci numarası"
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:765 config/tc-arm.c:3229
+#: config/tc-arm.c:760
 msgid "co-processor register expected"
 msgstr "Yardımcı işlemci yazmacı beklendi"
 
-#: config/tc-arm.c:766
+#: config/tc-arm.c:761
 msgid "FPA register expected"
 msgstr "FPA yazmacı beklendi"
 
-#: config/tc-arm.c:767
+#: config/tc-arm.c:762
 msgid "VFP single precision register expected"
 msgstr "tek doğruluklu VFP yazmacı beklendi"
 
-#: config/tc-arm.c:768
+#: config/tc-arm.c:763
 msgid "VFP double precision register expected"
 msgstr "Çift doğruluklu VFP yazmacı beklendi"
 
-#: config/tc-arm.c:769
+#: config/tc-arm.c:764
 msgid "Maverick MVF register expected"
 msgstr "Maverick MVF yazmacı beklendi"
 
-#: config/tc-arm.c:770
+#: config/tc-arm.c:765
 msgid "Maverick MVD register expected"
 msgstr "Maverick MVD yazmacı beklendi"
 
-#: config/tc-arm.c:771 config/tc-arm.c:772
+#: config/tc-arm.c:766
 msgid "Maverick MVFX register expected"
 msgstr "Maverick MVFX yazmacı beklendi"
 
-#: config/tc-arm.c:773
+#: config/tc-arm.c:767
+#, fuzzy
+msgid "Maverick MVDX register expected"
+msgstr "Maverick MVD yazmacı beklendi"
+
+#: config/tc-arm.c:768
 msgid "Maverick MVAX register expected"
 msgstr "Maverick MVAX yazmacı beklendi"
 
-#: config/tc-arm.c:774
+#: config/tc-arm.c:769
 msgid "Maverick DSPSC register expected"
 msgstr "Maverick DSPSC yazmacı beklendi"
 
-#: config/tc-arm.c:775
+#: config/tc-arm.c:770
 msgid "Intel Wireless MMX technology register expected"
 msgstr "Intel Wireless MMX teknoloji yazmacı beklendi"
 
-#: config/tc-arm.c:2309
+#: config/tc-arm.c:964
 msgid "bad arguments to instruction"
 msgstr "İşleme hatalı argümanlar verilmiş"
 
-#: config/tc-arm.c:2310
+#: config/tc-arm.c:965
 msgid "r15 not allowed here"
 msgstr "r15 burada kullanılamaz"
 
-#: config/tc-arm.c:2311
+#: config/tc-arm.c:966
 msgid "instruction is not conditional"
 msgstr "Ä°ÅŸlem koÅŸullu deÄŸil"
 
-#: config/tc-arm.c:2312
+#: config/tc-arm.c:967
 msgid "acc0 expected"
 msgstr "acc0 beklendi"
 
-#: config/tc-arm.c:2505
+#: config/tc-arm.c:1100
 msgid "literal pool overflow"
 msgstr "Literal Havuz Taşması"
 
-#: config/tc-arm.c:2647
+#: config/tc-arm.c:1475
+msgid "selected processor does not support THUMB opcodes"
+msgstr "seçilen işlemci THUMB opkodlarını desteklemiyor"
+
+#: config/tc-arm.c:1489
+msgid "selected processor does not support ARM opcodes"
+msgstr "seçilen işlemci ARM opkodlarını desteklemiyor"
+
+#: config/tc-arm.c:1502
+#, c-format
+msgid "invalid instruction size selected (%d)"
+msgstr "geçersiz işlem boyutu seçildi (%d)"
+
+#: config/tc-arm.c:1509
 msgid "invalid syntax for .req directive"
 msgstr ".req yönergesi için geçersiz sözdizimi"
 
-#: config/tc-arm.c:2727
+#: config/tc-arm.c:1552
+#, c-format
+msgid "unreq: missing hash entry for \"%s\""
+msgstr ""
+
+#: config/tc-arm.c:1571 config/tc-arm.c:1574
+#, fuzzy, c-format
+msgid ".unreq: unrecognized symbol \"%s\""
+msgstr "\"%s\" bilinmeyen sembol türü"
+
+#: config/tc-arm.c:1577
+#, fuzzy
+msgid "invalid syntax for .unreq directive"
+msgstr ".req yönergesi için geçersiz sözdizimi"
+
+#: config/tc-arm.c:1659
 #, c-format
 msgid "alignment too large: %d assumed"
 msgstr "Hizalama fazla büyük: %d varsayıldı"
 
-#: config/tc-arm.c:2730
+#: config/tc-arm.c:1662
 msgid "alignment negative. 0 assumed."
 msgstr "Hizalama negatif. 0 varsayıldı."
 
-#: config/tc-arm.c:2814
+#: config/tc-arm.c:1743
 #, c-format
 msgid "expected comma after name \"%s\""
 msgstr "\"%s\" isminden sonra virgül beklendi"
 
-#: config/tc-arm.c:2864 config/tc-m32r.c:420
+#: config/tc-arm.c:1793 config/tc-m32r.c:617
 #, c-format
 msgid "symbol `%s' already defined"
 msgstr "`%s' sembolü zaten tanımlanmış"
 
-#: config/tc-arm.c:2889
-msgid "selected processor does not support THUMB opcodes"
-msgstr "seçilen işlemci THUMB opkodlarını desteklemiyor"
-
-#: config/tc-arm.c:2902
-msgid "selected processor does not support ARM opcodes"
-msgstr "seçilen işlemci ARM opkodlarını desteklemiyor"
-
-#: config/tc-arm.c:2914
-#, c-format
-msgid "invalid instruction size selected (%d)"
-msgstr "geçersiz işlem boyutu seçildi (%d)"
-
-#: config/tc-arm.c:2949
+#: config/tc-arm.c:1836
 #, c-format
 msgid "invalid operand to .code directive (%d) (expecting 16 or 32)"
 msgstr ".code yönergesine geçersiz işlenen (%d) verilmiş (16 veya 32 beklendi)"
 
-#: config/tc-arm.c:2960
+#: config/tc-arm.c:1846
 msgid "garbage following instruction"
 msgstr "Ä°ÅŸlemden sonra bozulma"
 
+#: config/tc-arm.c:1916
+msgid "bad_segment"
+msgstr "hatalı_bölüm"
+
+#: config/tc-arm.c:1932 config/tc-arm.c:2699 config/tc-arm.c:3889
+#: config/tc-arm.c:5841 config/tc-arm.c:5861 config/tc-i960.c:1940
+msgid "invalid constant"
+msgstr "geçersiz sabit"
+
 #. In the few cases where we might be able to accept something else
 #. this error can be overridden.
-#: config/tc-arm.c:3010
+#: config/tc-arm.c:1967
 #, c-format
 msgid "register expected, not '%.100s'"
 msgstr "Yazmaç beklendi, '%.100s' değil"
 
 #. In the few cases where we might be able to accept
 #. something else this error can be overridden.
-#: config/tc-arm.c:3061
+#: config/tc-arm.c:2017
 #, c-format
 msgid "Intel Wireless MMX technology register expected, not '%.100s'"
 msgstr "Intel Wireless MMX teknoloji yazmacı beklendi, '%.100s' değil"
 
 #. In the few cases where we might be able to accept
 #. something else this error can be overridden.
-#: config/tc-arm.c:3133
+#: config/tc-arm.c:2087
 msgid "flag for {c}psr instruction expected"
 msgstr "{c}psr işlemi için bayrak beklendi"
 
-#: config/tc-arm.c:3167
+#: config/tc-arm.c:2120
 msgid "illegal co-processor number"
 msgstr "Geçersiz yardımcı işlemci numarası"
 
-#: config/tc-arm.c:3199 config/tc-arm.c:4778
+#: config/tc-arm.c:2149 config/tc-arm.c:5101
 msgid "bad or missing expression"
 msgstr "hatalı veya eksik ifade"
 
-#: config/tc-arm.c:3205
+#: config/tc-arm.c:2155
 msgid "immediate co-processor expression too large"
 msgstr "şimdiki yardımcı işlemci ifadesi fazla büyük"
 
-#. In the few cases where we might be able to accept something else
-#. this error can be overridden.
-#: config/tc-arm.c:3252
-msgid "floating point register expected"
-msgstr "Kayan nokta yazmacı beklendi"
-
-#: config/tc-arm.c:3269 config/tc-arm.c:3414
+#: config/tc-arm.c:2214 config/tc-arm.c:2427 config/tc-arm.c:3718
+#: config/tc-arm.c:3804 config/tc-arm.c:3868 config/tc-arm.c:4106
+#: config/tc-arm.c:4208
 msgid "immediate expression expected"
 msgstr "ÅŸimdi ifade beklendi"
 
-#: config/tc-arm.c:3284
+#: config/tc-arm.c:2229
 msgid "co-processor address must be word aligned"
 msgstr "yardımcı işlemci adresi word hizalı olmalı"
 
-#: config/tc-arm.c:3290 config/tc-arm.c:3429
+#: config/tc-arm.c:2235 config/tc-arm.c:2442 config/tc-mips.c:5037
 msgid "offset too large"
 msgstr "göreli konum fazla büyük"
 
-#: config/tc-arm.c:3339 config/tc-arm.c:3477
+#: config/tc-arm.c:2290
+#, fuzzy
+msgid "comma expected after closing square bracket"
+msgstr "yazmaç adından sonra virgül beklendi"
+
+#: config/tc-arm.c:2305 config/tc-arm.c:2489
 msgid "pc may not be used in post-increment"
 msgstr "pc arttırma sonrası kullanılamaz"
 
-#: config/tc-arm.c:3355 config/tc-arm.c:3493 config/tc-arm.c:3938
-#: config/tc-arm.c:5197 config/tc-arm.c:6064 config/tc-arm.c:6398
+#: config/tc-arm.c:2333
+#, fuzzy
+msgid "'option' field too large"
+msgstr "göreli konum fazla büyük"
+
+#: config/tc-arm.c:2341
+msgid "'}' expected at end of 'option' field"
+msgstr ""
+
+#: config/tc-arm.c:2353
+#, fuzzy
+msgid "non-constant expressions for 'option' field not supported"
+msgstr "\".if\" deyiminde sabit olmayan ifade"
+
+#: config/tc-arm.c:2359
+#, fuzzy
+msgid "# or { expected after comma"
+msgstr "PLD ipucundan sonra '[' beklendi"
+
+#: config/tc-arm.c:2369 config/tc-arm.c:2505 config/tc-arm.c:3020
+#: config/tc-arm.c:5530 config/tc-arm.c:6134 config/tc-arm.c:6405
 msgid "pre-indexed expression expected"
 msgstr "önceden indekslenmiş ifade beklendi"
 
-#: config/tc-arm.c:3368 config/tc-arm.c:3506 config/tc-arm.c:3951
-#: config/tc-arm.c:5208 config/tc-arm.c:6076 config/tc-arm.c:6410
-#: config/tc-arm.c:6784 config/tc-arm.c:9448 config/tc-arm.c:9463
+#: config/tc-arm.c:2382 config/tc-arm.c:2518 config/tc-arm.c:3033
+#: config/tc-arm.c:5541 config/tc-arm.c:6146 config/tc-arm.c:6417
+#: config/tc-arm.c:6800 config/tc-arm.c:9110 config/tc-arm.c:9125
 msgid "missing ]"
 msgstr "eksik ]"
 
-#: config/tc-arm.c:3378 config/tc-arm.c:3516
+#: config/tc-arm.c:2392 config/tc-arm.c:2528
 msgid "pc may not be used with write-back"
 msgstr "pc, geri-yazma (write-back) ile kullanılamaz"
 
-#: config/tc-arm.c:3568
+#: config/tc-arm.c:2577
+#, fuzzy
+msgid "Invalid NOP hint"
+msgstr "Geçersiz COPR tanımlayıcısı"
+
+#: config/tc-arm.c:2612
 msgid "comma expected after register name"
 msgstr "yazmaç adından sonra virgül beklendi"
 
-#: config/tc-arm.c:3587
+#: config/tc-arm.c:2631
 msgid "CPSR or SPSR expected"
 msgstr "CPSR veya SPSR beklendi"
 
-#: config/tc-arm.c:3613
+#: config/tc-arm.c:2656
 msgid "comma missing after psr flags"
 msgstr "psr bayraklarından sonra virgül eksik"
 
-#: config/tc-arm.c:3629 config/tc-arm.c:3639
+#: config/tc-arm.c:2672 config/tc-arm.c:2682
 msgid "only a register or immediate value can follow a psr flag"
 msgstr "bir psr bayrağından sonra yalnızca yazmaç veya şimdiki değer gelebilir"
 
-#: config/tc-arm.c:3650
-msgid "immediate value cannot be used to set this field"
-msgstr "şimdiki değer, bu alanı değere atamak için kullanılamaz"
-
-#: config/tc-arm.c:3668 config/tc-arm.c:5424 config/tc-arm.c:5704
-#: config/tc-arm.c:5724 config/tc-i960.c:1935
-msgid "invalid constant"
-msgstr "geçersiz sabit"
-
-#: config/tc-arm.c:3716
+#: config/tc-arm.c:2746
 msgid "rdhi, rdlo and rm must all be different"
 msgstr "rdhi, rdlo ve rm'un hepsi farklı olmalıdır"
 
-#: config/tc-arm.c:3770
+#: config/tc-arm.c:2798
 msgid "rd and rm should be different in mul"
 msgstr "mul içinde rd ve rm farklı olmalıdır"
 
-#: config/tc-arm.c:3824
+#: config/tc-arm.c:2850
 msgid "rd and rm should be different in mla"
 msgstr "mla içinde rd ve rm farklı olmalıdır"
 
-#: config/tc-arm.c:3872
+#: config/tc-arm.c:2896
 #, c-format
 msgid "acc0 expected, not '%.100s'"
 msgstr "acc0 beklendi, '%.100s' deÄŸil"
 
-#: config/tc-arm.c:4050
+#: config/tc-arm.c:2925 config/tc-arm.c:5439
+msgid "address offset too large"
+msgstr "adres göreli konumu fazla büyük"
+
+#: config/tc-arm.c:3130
 msgid "rdhi and rdlo must be different"
 msgstr "rdhi ve rdlo farklı olmalıdır"
 
-#: config/tc-arm.c:4158
+#: config/tc-arm.c:3235
 msgid "Warning: instruction unpredictable when using r15"
 msgstr "Uyarı: r15 kullanılırken işlem sonucu belirsiz"
 
-#: config/tc-arm.c:4373
+#: config/tc-arm.c:3444
+msgid "use of r15 in bx in ARM mode is not really useful"
+msgstr "ARM kipinde bx içinde r15 kullanılması pek faydalı değil"
+
+#: config/tc-arm.c:3466
 msgid "use of r15 in bxj is not really useful"
 msgstr "bxj içinde r15 kullanılması pek faydalı değil"
 
-#: config/tc-arm.c:4400 config/tc-arm.c:4585 config/tc-arm.c:5445 expr.c:1318
-#: read.c:2206
+#: config/tc-arm.c:3524 config/tc-arm.c:3548
+msgid "Rd equal to Rm or Rn yields unpredictable results"
+msgstr ""
+
+#: config/tc-arm.c:3577 config/tc-arm.c:3588
+msgid "shift expression expected"
+msgstr "Kaydırma ifadesi beklendi"
+
+#: config/tc-arm.c:3598
+#, fuzzy
+msgid "'LSL' or 'ASR' required"
+msgstr "')' gerekli"
+
+#: config/tc-arm.c:3604
+#, fuzzy
+msgid "'LSL' required"
+msgstr "')' gerekli"
+
+#: config/tc-arm.c:3610
+#, fuzzy
+msgid "'ASR' required"
+msgstr "')' gerekli"
+
+#: config/tc-arm.c:3632
+msgid "shift requires register or #expression"
+msgstr "Kaydırma, yazmaç veya #ifade gerektiriyor"
+
+#: config/tc-arm.c:3633
+msgid "shift requires #expression"
+msgstr "Kaydırma #ifade gerektiriyor"
+
+#: config/tc-arm.c:3663
+msgid "shift of 0 ignored."
+msgstr "Sıfırlık kaydırma yoksayıldı."
+
+#: config/tc-arm.c:3669
+msgid "invalid immediate shift"
+msgstr "Geçersiz şimdiki kaydırma"
+
+#: config/tc-arm.c:3723 config/tc-arm.c:3809 config/tc-arm.c:3875
+#: config/tc-arm.c:4112 config/tc-arm.c:4214 config/tc-arm.c:4536
+#: config/tc-arm.c:4760 config/tc-arm.c:5698 expr.c:1332 read.c:2198
 msgid "bad expression"
 msgstr "geçersiz ifade"
 
-#: config/tc-arm.c:4409 config/tc-arm.c:4594 config/tc-arm.c:4786
-#: config/tc-arm.c:8389 config/tc-arm.c:8424 config/tc-arm.c:8434
-#: config/tc-z8k.c:1161 config/tc-z8k.c:1173
+#: config/tc-arm.c:3728 config/tc-arm.c:3814 config/tc-arm.c:3881
+#: config/tc-arm.c:4118 config/tc-arm.c:4220 config/tc-arm.c:5832
+#: config/tc-arm.c:6182 config/tc-arm.c:6454 config/tc-arm.c:7063
+#: config/tc-v850.c:1924 config/tc-v850.c:1945
+msgid "constant expression expected"
+msgstr "sabit ifade beklendi"
+
+#: config/tc-arm.c:3734 config/tc-arm.c:3820 config/tc-arm.c:4545
+#: config/tc-arm.c:4769 config/tc-arm.c:5109 config/tc-arm.c:8198
+#: config/tc-arm.c:8233 config/tc-arm.c:8243 config/tc-z8k.c:1125
+#: config/tc-z8k.c:1137
 msgid "immediate value out of range"
 msgstr "şimdiki değer kapsam dışı"
 
-#: config/tc-arm.c:4833
+#: config/tc-arm.c:4020
+#, fuzzy
+msgid "missing endian specifier"
+msgstr "hatalı/eksik psr belirteci"
+
+#: config/tc-arm.c:4029
+msgid "valid endian specifiers are be or le"
+msgstr ""
+
+#: config/tc-arm.c:4096 config/tc-arm.c:4198
+#, fuzzy
+msgid "missing rotation field after comma"
+msgstr "resmi parametrelerden sonra eksik )"
+
+#: config/tc-arm.c:4140 config/tc-arm.c:4243
+msgid "rotation can be 8, 16, 24 or 0 when field is ommited"
+msgstr ""
+
+#: config/tc-arm.c:4492
+#, fuzzy
+msgid "unrecognized flag"
+msgstr "bilinmeyen opkod"
+
+#: config/tc-arm.c:4499
+msgid "no 'a', 'i', or 'f' flags for 'cps'"
+msgstr ""
+
+#: config/tc-arm.c:4810
+msgid "lo register required"
+msgstr "lo yazmacı gerekli"
+
+#: config/tc-arm.c:4818
+msgid "hi register required"
+msgstr "hi yazmacı gerekli"
+
+#: config/tc-arm.c:4886
+msgid "only lo regs allowed with immediate"
+msgstr "Şimdiki ile yalnızca lo yazmaçları kullanılabilir"
+
+#: config/tc-arm.c:4905 config/tc-xtensa.c:4123
+msgid "invalid immediate"
+msgstr "geçersiz şimdiki"
+
+#: config/tc-arm.c:5141 config/tc-arm.c:5285
+#, fuzzy
+msgid "non-word size not supported with control register"
+msgstr "cr%ld rezerveli bir kontrol yazmacı"
+
+#: config/tc-arm.c:5155
 msgid "only r15 allowed here"
 msgstr "burada ancak r15 kullanılabilir"
 
-#: config/tc-arm.c:5160
+#: config/tc-arm.c:5283
+msgid "conditional execution not supported with control register"
+msgstr ""
+
+#: config/tc-arm.c:5493
 msgid "'[' expected after PLD mnemonic"
 msgstr "PLD ipucundan sonra '[' beklendi"
 
-#: config/tc-arm.c:5182
+#: config/tc-arm.c:5515
 msgid "post-indexed expression used in preload instruction"
 msgstr "önyükleme işleminde sonradan indekslenen ifade kullanıldı"
 
-#: config/tc-arm.c:5187 config/tc-arm.c:5217
+#: config/tc-arm.c:5520 config/tc-arm.c:5550
 msgid "writeback used in preload instruction"
 msgstr "önyükleme işleminde geri-yazma (write-back) kullanıldı"
 
-#: config/tc-arm.c:5259
+#: config/tc-arm.c:5591
 msgid "destination register must be even"
 msgstr "Hedef yazmaç çift sayı olmalı"
 
-#: config/tc-arm.c:5265
+#: config/tc-arm.c:5597
 msgid "r14 not allowed here"
 msgstr "r14 burada kullanılamaz"
 
-#: config/tc-arm.c:5272
+#: config/tc-arm.c:5604
 msgid "pre/post-indexing used when modified address register is destination"
 msgstr "Hedef değiştirilmiş adres yazmacı olduğu zaman önce/sonra indeksleme kullanılır"
 
-#: config/tc-arm.c:5282
+#: config/tc-arm.c:5614
 msgid "ldrd destination registers must not overlap index register"
 msgstr "ldrd hedef yazmacları indeks yazmacı ile örtüşmemeli"
 
-#: config/tc-arm.c:5408
-msgid "bad_segment"
-msgstr "hatalı_bölüm"
-
-#: config/tc-arm.c:5468 config/tc-arm.c:5479
-msgid "shift expression expected"
-msgstr "Kaydırma ifadesi beklendi"
-
-#: config/tc-arm.c:5503
-msgid "shift requires register or #expression"
-msgstr "Kaydırma, yazmaç veya #ifade gerektiriyor"
-
-#: config/tc-arm.c:5504
-msgid "shift requires #expression"
-msgstr "Kaydırma #ifade gerektiriyor"
-
-#: config/tc-arm.c:5534
-msgid "shift of 0 ignored."
-msgstr "Sıfırlık kaydırma yoksayıldı."
-
-#: config/tc-arm.c:5540
-msgid "invalid immediate shift"
-msgstr "Geçersiz şimdiki kaydırma"
-
-#: config/tc-arm.c:5695 config/tc-arm.c:6112 config/tc-arm.c:6447
-#: config/tc-arm.c:7081 config/tc-v850.c:1908 config/tc-v850.c:1929
-msgid "constant expression expected"
-msgstr "sabit ifade beklendi"
-
-#: config/tc-arm.c:5737
+#: config/tc-arm.c:5874
 msgid "register or shift expression expected"
 msgstr "Yazmaç veya kaydırma ifadesi beklendi"
 
-#: config/tc-arm.c:5790
+#: config/tc-arm.c:5926
 msgid "invalid floating point immediate expression"
 msgstr "Geçersiz kayan nokta şimdiki ifadesi"
 
-#: config/tc-arm.c:5794
+#: config/tc-arm.c:5930
 msgid "floating point register or immediate expression expected"
 msgstr "Kayan nokta yazmacı veya şimdiki ifade beklendi"
 
-#: config/tc-arm.c:5948 config/tc-arm.c:6278
-msgid "address offset too large"
-msgstr "adres göreli konumu fazla büyük"
-
-#: config/tc-arm.c:6006 config/tc-arm.c:6196 config/tc-arm.c:6338
+#: config/tc-arm.c:6076 config/tc-arm.c:6264 config/tc-arm.c:6345
 msgid "address expected"
 msgstr "Adres beklendi"
 
-#: config/tc-arm.c:6036 config/tc-arm.c:6048 config/tc-arm.c:6085
-#: config/tc-arm.c:6214 config/tc-arm.c:6368 config/tc-arm.c:6382
-#: config/tc-arm.c:6419
+#: config/tc-arm.c:6106 config/tc-arm.c:6118 config/tc-arm.c:6155
+#: config/tc-arm.c:6282 config/tc-arm.c:6375 config/tc-arm.c:6389
+#: config/tc-arm.c:6426
 #, c-format
 msgid "%s register same as write-back base"
 msgstr "%s yazmacı geri-yazma (write-back) temeli ile aynı"
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
+#: config/tc-arm.c:6108 config/tc-arm.c:6120 config/tc-arm.c:6157
+#: config/tc-arm.c:6284 config/tc-arm.c:6377 config/tc-arm.c:6391
+#: config/tc-arm.c:6428
 msgid "destination"
 msgstr "hedef"
 
-#: config/tc-arm.c:6038 config/tc-arm.c:6050 config/tc-arm.c:6087
-#: config/tc-arm.c:6216 config/tc-arm.c:6370 config/tc-arm.c:6384
-#: config/tc-arm.c:6421
+#: config/tc-arm.c:6108 config/tc-arm.c:6120 config/tc-arm.c:6157
+#: config/tc-arm.c:6284 config/tc-arm.c:6377 config/tc-arm.c:6391
+#: config/tc-arm.c:6428
 msgid "source"
 msgstr "kaynak"
 
-#: config/tc-arm.c:6097 config/tc-arm.c:6431 config/tc-arm.c:8695
+#: config/tc-arm.c:6167 config/tc-arm.c:6438 config/tc-arm.c:8411
 msgid "invalid pseudo operation"
 msgstr "geçersiz sanal işlem"
 
-#: config/tc-arm.c:6149 config/tc-arm.c:6482
+#: config/tc-arm.c:6219 config/tc-arm.c:6489
 msgid "literal pool insertion failed"
 msgstr "literal havuza ekleme başarısız"
 
-#: config/tc-arm.c:6244 config/tc-arm.c:6250
+#: config/tc-arm.c:6312 config/tc-arm.c:6318
 msgid "post-indexed expression expected"
 msgstr "sonradan indekslenmiÅŸ ifade beklendi"
 
-#: config/tc-arm.c:6548
+#: config/tc-arm.c:6553
 msgid "bad range in register list"
 msgstr "Yazmaç listesinde hatalı aralık"
 
-#: config/tc-arm.c:6556 config/tc-arm.c:6565 config/tc-arm.c:6607
+#: config/tc-arm.c:6561 config/tc-arm.c:6570 config/tc-arm.c:6612
 #, c-format
 msgid "Warning: duplicated register (r%d) in register list"
 msgstr "Uyarı: Yazmaç listesinde tekrarlanan yazmaç (r%d)"
 
-#: config/tc-arm.c:6568
+#: config/tc-arm.c:6573
 msgid "Warning: register range not in ascending order"
 msgstr "Uyarı: Yazmaç aralığı artan sıralamada değil"
 
-#: config/tc-arm.c:6580
+#: config/tc-arm.c:6585
 msgid "missing `}'"
 msgstr "Eksik `}'"
 
-#: config/tc-arm.c:6596
+#: config/tc-arm.c:6601
 msgid "invalid register mask"
 msgstr "geçersiz yazmaç maskesi"
 
-#: config/tc-arm.c:6655
+#: config/tc-arm.c:6659
 msgid "r15 not allowed as base register"
 msgstr "r15 temel yazmaç olarak kullanılamaz"
 
-#: config/tc-arm.c:6689 config/tc-arm.c:6698
+#: config/tc-arm.c:6693 config/tc-arm.c:6702
 msgid "writeback of base register is UNPREDICTABLE"
 msgstr "temel yazmaca geri yazım sonuçları TAHMİN EDİLEMEZ"
 
-#: config/tc-arm.c:6692
+#: config/tc-arm.c:6696
 msgid "writeback of base register when in register list is UNPREDICTABLE"
 msgstr "yazmaç listesinde bulunan temel yazmaca geri yazım sonuçları TAHMİN EDİLEMEZ"
 
-#: config/tc-arm.c:6702
+#: config/tc-arm.c:6706
 msgid "if writeback register is in list, it must be the lowest reg in the list"
 msgstr "eğer listede geriyazım yazmacı varsa, listedeki en düşük yazmaç olmalıdır"
 
-#: config/tc-arm.c:6744 config/tc-arm.c:6758
+#: config/tc-arm.c:6760 config/tc-arm.c:6774
 msgid "r15 not allowed in swap"
 msgstr "r15 takasta kullanılamaz"
 
-#: config/tc-arm.c:6853
-msgid "use of r15 in bx in ARM mode is not really useful"
-msgstr "ARM kipinde bx içinde r15 kullanılması pek faydalı değil"
-
-#: config/tc-arm.c:7087
+#: config/tc-arm.c:7069
 msgid "constant value required for number of registers"
 msgstr "Yazmaç sayısı için sabit değer gerekli"
 
-#: config/tc-arm.c:7095
+#: config/tc-arm.c:7077 config/tc-arm.c:14226
 msgid "number of registers must be in the range [1:4]"
 msgstr "Yazmaç sayısı aralık içinde olmalı [1:4]"
 
-#: config/tc-arm.c:7156
+#: config/tc-arm.c:7138
 msgid "r15 not allowed as base register with write-back"
 msgstr "R15, geri-yazmalı (write-back) temel yazmaç olarak kullanılamaz"
 
-#: config/tc-arm.c:7538
-msgid "only two consecutive VFP SP registers allowed here"
-msgstr "burada yalnızca iki ardışık VFP SP yazmacına izin var"
-
-#: config/tc-arm.c:7706
-msgid "VFP system register expected"
-msgstr "VFP sistem yazmacı beklendi"
-
-#: config/tc-arm.c:7844 config/tc-arm.c:7883 config/tc-arm.c:7896
-#: config/tc-arm.c:7957 config/tc-arm.c:7996 config/tc-arm.c:8009
-#: config/tc-h8300.c:1035 config/tc-mips.c:9722 config/tc-mips.c:9752
+#: config/tc-arm.c:7533 config/tc-arm.c:7572 config/tc-h8300.c:1010
+#: config/tc-mips.c:9585 config/tc-mips.c:9615
 msgid "invalid register list"
 msgstr "geçersiz yazmaç listesi"
 
-#: config/tc-arm.c:7850 config/tc-arm.c:7963
+#: config/tc-arm.c:7539 config/tc-arm.c:14310 config/tc-arm.c:14317
 msgid "register list not in ascending order"
 msgstr "Yazmaç listesi artan sıralamada değil"
 
-#: config/tc-arm.c:7875 config/tc-arm.c:7988
+#: config/tc-arm.c:7564
 msgid "register range not in ascending order"
 msgstr "Yazmaç aralığı artan sıralamada değil"
 
-#: config/tc-arm.c:7913 config/tc-arm.c:8026
+#: config/tc-arm.c:7597
 msgid "non-contiguous register range"
 msgstr "ardışık olmayan yazmaç aralığı"
 
-#: config/tc-arm.c:8056 config/tc-arm.c:8093
-msgid "this addressing mode requires base-register writeback"
-msgstr "bu adresleme kip temel yazmaca geriyazma (write-back) gerektiriyor"
+#: config/tc-arm.c:7626 config/tc-arm.c:7663
+msgid "only two consecutive VFP SP registers allowed here"
+msgstr "burada yalnızca iki ardışık VFP SP yazmacına izin var"
 
-#: config/tc-arm.c:8253
-msgid "lo register required"
-msgstr "lo yazmacı gerekli"
+#: config/tc-arm.c:7810
+msgid "VFP system register expected"
+msgstr "VFP sistem yazmacı beklendi"
 
-#: config/tc-arm.c:8261
-msgid "hi register required"
-msgstr "hi yazmacı gerekli"
+#: config/tc-arm.c:7921 config/tc-arm.c:7958
+msgid "this addressing mode requires base-register writeback"
+msgstr "bu adresleme kip temel yazmaca geriyazma (write-back) gerektiriyor"
 
-#: config/tc-arm.c:8331 config/tc-arm.c:9537
+#: config/tc-arm.c:8140 config/tc-arm.c:9219
 msgid "dest and source1 must be the same register"
 msgstr "hedef ve kaynak1 aynı yazmaç olmalı"
 
-#: config/tc-arm.c:8338
+#: config/tc-arm.c:8147
 msgid "subtract valid only on lo regs"
 msgstr "çıkarma yalnızca lo yazmaçlarında geçerli"
 
-#: config/tc-arm.c:8362
+#: config/tc-arm.c:8171
 msgid "invalid Hi register with immediate"
 msgstr "Şimdiki ile geçersiz hi yazmacı"
 
-#: config/tc-arm.c:8402
+#: config/tc-arm.c:8211
 msgid "invalid immediate value for stack adjust"
 msgstr "Yığıt düzeltme için geçersiz şimdiki değer"
 
-#: config/tc-arm.c:8413
+#: config/tc-arm.c:8222
 msgid "invalid immediate for address calculation"
 msgstr "Adres hesaplaması için geçersiz şimdiki"
 
-#: config/tc-arm.c:8500
+#: config/tc-arm.c:8307
 msgid "source1 and dest must be same register"
 msgstr "kaynak1 ve hedef aynı yazmaç olmalı"
 
-#: config/tc-arm.c:8534
+#: config/tc-arm.c:8341
 msgid "invalid immediate for shift"
 msgstr "Kaydırma için geçersiz şimdiki"
 
-#: config/tc-arm.c:8613
-msgid "only lo regs allowed with immediate"
-msgstr "Şimdiki ile yalnızca lo yazmaçları kullanılabilir"
-
-#: config/tc-arm.c:8632
-msgid "invalid immediate"
-msgstr "geçersiz şimdiki"
-
-#: config/tc-arm.c:8686
+#: config/tc-arm.c:8402
 msgid "expected ']'"
 msgstr "']' beklendi"
 
-#: config/tc-arm.c:8759
+#: config/tc-arm.c:8475
 msgid "byte or halfword not valid for base register"
 msgstr "bayt veya halfword temel yazmaç için geçersiz"
 
-#: config/tc-arm.c:8764
+#: config/tc-arm.c:8480
 msgid "r15 based store not allowed"
 msgstr "R15 temelli saklama geçersiz"
 
-#: config/tc-arm.c:8769
+#: config/tc-arm.c:8485
 msgid "invalid base register for register offset"
 msgstr "Yazmaç göreli konumu için geçersiz temel yazmaç"
 
-#: config/tc-arm.c:8787 config/tc-arm.c:8822
+#: config/tc-arm.c:8503 config/tc-arm.c:8538
 msgid "invalid offset"
 msgstr "geçersiz göreli konum"
 
-#: config/tc-arm.c:8798
+#: config/tc-arm.c:8514
 msgid "invalid base register in load/store"
 msgstr "yükle/sakla için geçersiz temel yazmaç"
 
-#: config/tc-arm.c:9341
+#: config/tc-arm.c:8990
 msgid "expecting immediate, 7bit operand"
 msgstr "ÅŸimdiki, 7bitlik iÅŸlenen beklendi"
 
-#: config/tc-arm.c:9356
+#: config/tc-arm.c:9005
 msgid "immediate out of range"
 msgstr "şimdiki değer kapsam dışı"
 
-#: config/tc-arm.c:9399
+#: config/tc-arm.c:9058
 msgid "offset expected"
 msgstr "görece beklendi"
 
-#: config/tc-arm.c:9408 config/tc-pj.c:537 config/tc-sh.c:3593
+#: config/tc-arm.c:9067 config/tc-pj.c:536 config/tc-sh.c:4107
 msgid "offset out of range"
 msgstr "göreli konum kapsam dışı"
 
-#: config/tc-arm.c:9545
+#: config/tc-arm.c:9072
+#, fuzzy
+msgid "offset not a multiple of 4"
+msgstr "yazmaç sakla görecesi %u'nun katı değil"
+
+#: config/tc-arm.c:9227
 msgid "Rs and Rd must be different in MUL"
 msgstr "MUL içinde Rs ve Rd farklı olmalı"
 
-#: config/tc-arm.c:9689
+#: config/tc-arm.c:9362
 msgid "inserted missing '!': load/store multiple always writes back base register"
 msgstr "Eksik '!' eklendi: yükle/sakla çoğulu hep temel yazmaca geri yazar"
 
-#: config/tc-arm.c:9711
+#: config/tc-arm.c:9384
 msgid "only lo-regs valid in load/store multiple"
 msgstr "yükle/sakla çoğulunda yalnız lo yazmaçları geçerli"
 
-#: config/tc-arm.c:9757
+#: config/tc-arm.c:9426
 msgid "syntax: ldrs[b] Rd, [Rb, Ro]"
 msgstr "Sözdizim: ldrs[b] Rd, [Rb, Ro]"
 
-#: config/tc-arm.c:9821
+#: config/tc-arm.c:9486
 msgid "invalid register list to push/pop instruction"
 msgstr "emme/basma işlemi için geçersiz yazmaç listesi"
 
-#: config/tc-arm.c:9933 config/tc-arm.c:10159
+#: config/tc-arm.c:9589 config/tc-arm.c:10966
 msgid "virtual memory exhausted"
 msgstr "Sanal bellek tükendi"
 
-#: config/tc-arm.c:10014
+#: config/tc-arm.c:9613
+#, fuzzy, c-format
+msgid "failed to create an alias for %s, reason: %s"
+msgstr "Hata ayıklama bilgisi oluşturma başarısız: %s"
+
+#: config/tc-arm.c:9677
 #, c-format
 msgid "register '%s' does not exist\n"
 msgstr "'%s' yazmacı yok\n"
 
-#: config/tc-arm.c:10018
+#: config/tc-arm.c:9681
 #, c-format
 msgid "ignoring redefinition of register alias '%s' to non-existant register '%s'"
 msgstr ""
 "'%s' yazmaç rumuzunun var olmayan '%s' yazmacı olarak yeniden tanımlanması\n"
 "yoksayıldı"
 
-#: config/tc-arm.c:10027
+#: config/tc-arm.c:9690
 #, c-format
 msgid "ignoring redefinition of register alias '%s'"
 msgstr "'%s' yazmaç rumuzunun yeniden tanımlanması yoksayıldı"
 
-#: config/tc-arm.c:10033
+#: config/tc-arm.c:9696
 msgid "ignoring incomplete .req pseuso op"
 msgstr "eksik .req pseudo-op yoksayıldı"
 
-#: config/tc-arm.c:10183
+#: config/tc-arm.c:10990
 msgid "use of old and new-style options to set CPU type"
 msgstr "CPU türünü belirlemekte hem eski hem de yeni tarz seçeneği kullanılmış"
 
-#: config/tc-arm.c:10193
+#: config/tc-arm.c:11000
 msgid "use of old and new-style options to set FPU type"
 msgstr "FPU türünü belirlemekte hem eski hem de yeni tarz seçeneği kullanılmış"
 
-#: config/tc-arm.c:10473
+#: config/tc-arm.c:11062
+msgid "hard-float conflicts with specified fpu"
+msgstr ""
+
+#: config/tc-arm.c:11246
 msgid "bad call to MD_ATOF()"
 msgstr "MD_ATOF()'a hatalı çağrı"
 
-#: config/tc-arm.c:10703
+#: config/tc-arm.c:11402
+#, fuzzy, c-format
+msgid "undefined symbol %s used as an immediate value"
+msgstr "şimdiki değer olarak sıfır kullanıldı"
+
+#: config/tc-arm.c:11416
 #, c-format
 msgid "invalid constant (%lx) after fixup"
 msgstr "düzeltmeden sonra geçersiz sabit (%lx)"
 
-#: config/tc-arm.c:10741
+#: config/tc-arm.c:11453
 #, c-format
 msgid "unable to compute ADRL instructions for PC offset of 0x%lx"
 msgstr "0x%lx PC göreli konumu için ADRL işlemleri hesaplanamadı"
 
-#: config/tc-arm.c:10771
+#: config/tc-arm.c:11483
 #, c-format
 msgid "bad immediate value for offset (%ld)"
 msgstr "göreli konum (%ld) için hatalı şimdiki değer"
 
-#: config/tc-arm.c:10793 config/tc-arm.c:10815
+#: config/tc-arm.c:11505 config/tc-arm.c:11527
 msgid "invalid literal constant: pool needs to be closer"
 msgstr "geçersiz literal sabit: havuz daha yakın olmalı"
 
-#: config/tc-arm.c:10795
+#: config/tc-arm.c:11507
 #, c-format
 msgid "bad immediate value for half-word offset (%ld)"
 msgstr "halfword göreli konumu (%ld) için hatalı şimdiki değer"
 
-#: config/tc-arm.c:10832
+#: config/tc-arm.c:11544
 msgid "shift expression is too large"
 msgstr "kaydırma ifadesi fazla büyük"
 
-#: config/tc-arm.c:10851 config/tc-arm.c:10860
+#: config/tc-arm.c:11561
+#, fuzzy
+msgid "invalid smi expression"
+msgstr "geçersiz swi ifadesi"
+
+#: config/tc-arm.c:11572 config/tc-arm.c:11581
 msgid "invalid swi expression"
 msgstr "geçersiz swi ifadesi"
 
-#: config/tc-arm.c:10870
+#: config/tc-arm.c:11591
 msgid "invalid expression in load/store multiple"
 msgstr "yükle/sakla çoğulunda geçersiz ifade"
 
-#: config/tc-arm.c:10923
+#: config/tc-arm.c:11641
 msgid "GAS can't handle same-section branch dest >= 0x04000000"
 msgstr "GAS aynı bölüm dal hedefini desteklemiyor >= 0x04000000"
 
-#: config/tc-arm.c:10932
+#: config/tc-arm.c:11650
 msgid "out of range branch"
 msgstr "dal kapsamı dışında"
 
-#: config/tc-arm.c:10965 config/tc-arm.c:10981
+#: config/tc-arm.c:11707 config/tc-arm.c:11732
 msgid "branch out of range"
 msgstr "dal kapsam dışı"
 
-#: config/tc-arm.c:11005
+#: config/tc-arm.c:11765
 msgid "branch with link out of range"
 msgstr "dal ile bağlantı kapsam dışı"
 
-#: config/tc-arm.c:11074
+#: config/tc-arm.c:11858
+#, fuzzy
+msgid "rel31 relocation overflow"
+msgstr "yerdeğişim taşması"
+
+#: config/tc-arm.c:11874
 msgid "illegal value for co-processor offset"
 msgstr "yardımcı işlemci göreli konumu için geçersiz değer"
 
-#: config/tc-arm.c:11086
+#: config/tc-arm.c:11886
 msgid "Illegal value for co-processor offset"
 msgstr "Yardımcı işlemci göreli konumu için geçersiz değer"
 
-#: config/tc-arm.c:11110
+#: config/tc-arm.c:11910
 #, c-format
 msgid "invalid offset, target not word aligned (0x%08X)"
 msgstr "geçersiz göreli konum, hedef word hizalı değil (0x%08X)"
 
-#: config/tc-arm.c:11116 config/tc-arm.c:11126 config/tc-arm.c:11134
-#: config/tc-arm.c:11142 config/tc-arm.c:11150
+#: config/tc-arm.c:11916 config/tc-arm.c:11926 config/tc-arm.c:11934
+#: config/tc-arm.c:11942 config/tc-arm.c:11950
 #, c-format
 msgid "invalid offset, value too big (0x%08lX)"
 msgstr "geçersiz göreli konum, değer fazla büyük (0x%08lX)"
 
-#: config/tc-arm.c:11190
+#: config/tc-arm.c:11990
 msgid "invalid immediate for stack address calculation"
 msgstr "yığıt adres hesaplaması için geçersiz şimdiki"
 
-#: config/tc-arm.c:11199
+#: config/tc-arm.c:11999
 #, c-format
 msgid "invalid immediate for address calculation (value = 0x%08lX)"
 msgstr "adres hesaplaması için geçersiz şimdiki (değer = 0x%08lX)"
 
-#: config/tc-arm.c:11209
+#: config/tc-arm.c:12009
 msgid "invalid 8bit immediate"
 msgstr "geçersiz 8bitlik şimdiki"
 
-#: config/tc-arm.c:11217
+#: config/tc-arm.c:12017
 msgid "invalid 3bit immediate"
 msgstr "geçersiz 3bitlik şimdiki"
 
-#: config/tc-arm.c:11233
+#: config/tc-arm.c:12033
 #, c-format
 msgid "invalid immediate: %ld is too large"
 msgstr "geçersiz şimdiki: %ld fazla büyük"
 
-#: config/tc-arm.c:11248
+#: config/tc-arm.c:12048
 #, c-format
 msgid "illegal Thumb shift value: %ld"
 msgstr "geçersiz Thumb kaydırma değeri: %ld"
 
-#: config/tc-arm.c:11262
+#: config/tc-arm.c:12062
 #, c-format
 msgid "bad relocation fixup type (%d)"
 msgstr "hatalı yerdeğişim düzeltme türü (%d)"
 
-#: config/tc-arm.c:11333
+#: config/tc-arm.c:12133
 msgid "literal referenced across section boundary"
 msgstr "literal bölüm sınırı ötesinden çağrılmış"
 
-#: config/tc-arm.c:11346
+#: config/tc-arm.c:12151
 msgid "internal relocation (type: IMMEDIATE) not fixed up"
 msgstr "iç yerdeğişim (türü: ŞİMDİKİ) düzeltilmemiş"
 
-#: config/tc-arm.c:11351
+#: config/tc-arm.c:12156
 msgid "ADRL used for a symbol not defined in the same file"
 msgstr "Aynı dosyada tanımlanmamış bir sembol için ADRL kullanılmış"
 
-#: config/tc-arm.c:11356
+#: config/tc-arm.c:12165
+#, c-format
+msgid "undefined local label `%s'"
+msgstr ""
+
+#: config/tc-arm.c:12171
 msgid "internal_relocation (type: OFFSET_IMM) not fixed up"
 msgstr "iç yerdeğişim (türü: OFFSET_IMM) düzeltilmemiş"
 
-#: config/tc-arm.c:11374 config/tc-cris.c:3063 config/tc-mcore.c:2052
-#: config/tc-mmix.c:2867 config/tc-ns32k.c:2396
+#: config/tc-arm.c:12191 config/tc-cris.c:3936 config/tc-mcore.c:2053
+#: config/tc-mmix.c:2930 config/tc-ns32k.c:2393
 msgid "<unknown>"
 msgstr "<bilinmiyor>"
 
-#: config/tc-arm.c:11377 config/tc-arm.c:11398
+#: config/tc-arm.c:12194 config/tc-arm.c:12215
 #, c-format
 msgid "cannot represent %s relocation in this object file format"
 msgstr "bu nesne dosya biçeminde %s yerdeğişimi gösterilemez"
 
-#: config/tc-arm.c:11494
+#: config/tc-arm.c:12342
 #, c-format
 msgid "no operator -- statement `%s'\n"
 msgstr "iÅŸlemimi yok -- `%s' deyimi\n"
 
-#: config/tc-arm.c:11512 config/tc-arm.c:11537
+#: config/tc-arm.c:12360 config/tc-arm.c:12386
 #, c-format
 msgid "selected processor does not support `%s'"
 msgstr "seçilen işlemci `%s'ı desteklemiyor"
 
-#: config/tc-arm.c:11554
+#: config/tc-arm.c:12404
 #, c-format
 msgid "bad instruction `%s'"
 msgstr "hatalı işlem `%s'"
 
-#: config/tc-arm.c:11655
+#: config/tc-arm.c:12505
 msgid "generate PIC code"
 msgstr "PIC kodu üretir"
 
-#: config/tc-arm.c:11656
+#: config/tc-arm.c:12506
 msgid "assemble Thumb code"
 msgstr "Thumb kodunu çevirir"
 
-#: config/tc-arm.c:11657
+#: config/tc-arm.c:12507
 msgid "support ARM/Thumb interworking"
 msgstr "ARM/Thumb beraber çalışmasını destekler"
 
-#: config/tc-arm.c:11659
-msgid "use old ABI (ELF only)"
-msgstr "eski ABI'yi kullanır (yalnız ELF)"
-
-#: config/tc-arm.c:11660
+#: config/tc-arm.c:12509
 msgid "code uses 32-bit program counter"
 msgstr "kod, 32 bit yazılım sayacı kullanıyor"
 
-#: config/tc-arm.c:11661
+#: config/tc-arm.c:12510
 msgid "code uses 26-bit program counter"
 msgstr "kod, 26 bitlik yazılım sayacı kullanıyor"
 
-#: config/tc-arm.c:11662
+#: config/tc-arm.c:12511
 msgid "floating point args are in fp regs"
 msgstr "kayan nokta argümanları kayan nokta yazmaçlarında"
 
-#: config/tc-arm.c:11664
+#: config/tc-arm.c:12513
 msgid "re-entrant code"
 msgstr "yeniden giriÅŸli kod"
 
-#: config/tc-arm.c:11665
+#: config/tc-arm.c:12514
 msgid "code is ATPCS conformant"
 msgstr "kod ATPCS uyumlu"
 
-#: config/tc-arm.c:11666
+#: config/tc-arm.c:12515
 msgid "assemble for big-endian"
 msgstr "büyük sonlu için çevirir"
 
-#: config/tc-arm.c:11667
+#: config/tc-arm.c:12516
 msgid "assemble for little-endian"
 msgstr "küçük-sonlu için çevirir"
 
 #. These are recognized by the assembler, but have no affect on code.
-#: config/tc-arm.c:11671
+#: config/tc-arm.c:12520
 msgid "use frame pointer"
 msgstr "çerçeve imleyicisi kullanır"
 
-#: config/tc-arm.c:11672
+#: config/tc-arm.c:12521
 msgid "use stack size checking"
 msgstr "yığıt boyu sağlaması kullanır"
 
 #. DON'T add any new processors to this list -- we want the whole list
 #. to go away...  Add them to the processors table instead.
-#: config/tc-arm.c:11676 config/tc-arm.c:11677
+#: config/tc-arm.c:12525 config/tc-arm.c:12526
 msgid "use -mcpu=arm1"
 msgstr " -mcpu=arm1 seçeneğini kullanır"
 
-#: config/tc-arm.c:11678 config/tc-arm.c:11679
+#: config/tc-arm.c:12527 config/tc-arm.c:12528
 msgid "use -mcpu=arm2"
 msgstr " -mcpu=arm2 seçeneğini kullanır"
 
-#: config/tc-arm.c:11680 config/tc-arm.c:11681
+#: config/tc-arm.c:12529 config/tc-arm.c:12530
 msgid "use -mcpu=arm250"
 msgstr " -mcpu=arm250 seçeneğini kullanır"
 
-#: config/tc-arm.c:11682 config/tc-arm.c:11683
+#: config/tc-arm.c:12531 config/tc-arm.c:12532
 msgid "use -mcpu=arm3"
 msgstr " -mcpu=arm3 seçeneğini kullanır"
 
-#: config/tc-arm.c:11684 config/tc-arm.c:11685
+#: config/tc-arm.c:12533 config/tc-arm.c:12534
 msgid "use -mcpu=arm6"
 msgstr " -mcpu=arm6 seçeneğini kullanır"
 
-#: config/tc-arm.c:11686 config/tc-arm.c:11687
+#: config/tc-arm.c:12535 config/tc-arm.c:12536
 msgid "use -mcpu=arm600"
 msgstr " -mcpu=arm600 seçeneğini kullanır"
 
-#: config/tc-arm.c:11688 config/tc-arm.c:11689
+#: config/tc-arm.c:12537 config/tc-arm.c:12538
 msgid "use -mcpu=arm610"
 msgstr " -mcpu=arm610 seçeneğini kullanır"
 
-#: config/tc-arm.c:11690 config/tc-arm.c:11691
+#: config/tc-arm.c:12539 config/tc-arm.c:12540
 msgid "use -mcpu=arm620"
 msgstr " -mcpu=arm620 seçeneğini kullanır"
 
-#: config/tc-arm.c:11692 config/tc-arm.c:11693
+#: config/tc-arm.c:12541 config/tc-arm.c:12542
 msgid "use -mcpu=arm7"
 msgstr " -mcpu=arm7 seçeneğini kullanır"
 
-#: config/tc-arm.c:11694 config/tc-arm.c:11695
+#: config/tc-arm.c:12543 config/tc-arm.c:12544
 msgid "use -mcpu=arm70"
 msgstr " -mcpu=arm70 seçeneğini kullanır"
 
-#: config/tc-arm.c:11696 config/tc-arm.c:11697
+#: config/tc-arm.c:12545 config/tc-arm.c:12546
 msgid "use -mcpu=arm700"
 msgstr " -mcpu=arm700 seçeneğini kullanır"
 
-#: config/tc-arm.c:11698 config/tc-arm.c:11699
+#: config/tc-arm.c:12547 config/tc-arm.c:12548
 msgid "use -mcpu=arm700i"
 msgstr " -mcpu=arm700i seçeneğini kullanır"
 
-#: config/tc-arm.c:11700 config/tc-arm.c:11701
+#: config/tc-arm.c:12549 config/tc-arm.c:12550
 msgid "use -mcpu=arm710"
 msgstr " -mcpu=arm710 seçeneğini kullanır"
 
-#: config/tc-arm.c:11702 config/tc-arm.c:11703
+#: config/tc-arm.c:12551 config/tc-arm.c:12552
 msgid "use -mcpu=arm710c"
 msgstr " -mcpu=arm710c seçeneğini kullanır"
 
-#: config/tc-arm.c:11704 config/tc-arm.c:11705
+#: config/tc-arm.c:12553 config/tc-arm.c:12554
 msgid "use -mcpu=arm720"
 msgstr " -mcpu=arm720 seçeneğini kullanır"
 
-#: config/tc-arm.c:11706 config/tc-arm.c:11707
+#: config/tc-arm.c:12555 config/tc-arm.c:12556
 msgid "use -mcpu=arm7d"
 msgstr " -mcpu=arm7d seçeneğini kullanır"
 
-#: config/tc-arm.c:11708 config/tc-arm.c:11709
+#: config/tc-arm.c:12557 config/tc-arm.c:12558
 msgid "use -mcpu=arm7di"
 msgstr " -mcpu=arm7di seçeneğini kullanır"
 
-#: config/tc-arm.c:11710 config/tc-arm.c:11711
+#: config/tc-arm.c:12559 config/tc-arm.c:12560
 msgid "use -mcpu=arm7m"
 msgstr " -mcpu=arm7m seçeneğini kullanır"
 
-#: config/tc-arm.c:11712 config/tc-arm.c:11713
+#: config/tc-arm.c:12561 config/tc-arm.c:12562
 msgid "use -mcpu=arm7dm"
 msgstr " -mcpu=arm7dm seçeneğini kullanır"
 
-#: config/tc-arm.c:11714 config/tc-arm.c:11715
+#: config/tc-arm.c:12563 config/tc-arm.c:12564
 msgid "use -mcpu=arm7dmi"
 msgstr " -mcpu=arm7dmi seçeneğini kullanır"
 
-#: config/tc-arm.c:11716 config/tc-arm.c:11717
+#: config/tc-arm.c:12565 config/tc-arm.c:12566
 msgid "use -mcpu=arm7100"
 msgstr " -mcpu=arm7100 seçeneğini kullanır"
 
-#: config/tc-arm.c:11718 config/tc-arm.c:11719
+#: config/tc-arm.c:12567 config/tc-arm.c:12568
 msgid "use -mcpu=arm7500"
 msgstr " -mcpu=arm7500 seçeneğini kullanır"
 
-#: config/tc-arm.c:11720 config/tc-arm.c:11721
+#: config/tc-arm.c:12569 config/tc-arm.c:12570
 msgid "use -mcpu=arm7500fe"
 msgstr " -mcpu=arm7500fe seçeneğini kullanır"
 
-#: config/tc-arm.c:11722 config/tc-arm.c:11723 config/tc-arm.c:11724
-#: config/tc-arm.c:11725
+#: config/tc-arm.c:12571 config/tc-arm.c:12572 config/tc-arm.c:12573
+#: config/tc-arm.c:12574
 msgid "use -mcpu=arm7tdmi"
 msgstr " -mcpu=arm7tdmi seçeneğini kullanır"
 
-#: config/tc-arm.c:11726 config/tc-arm.c:11727
+#: config/tc-arm.c:12575 config/tc-arm.c:12576
 msgid "use -mcpu=arm710t"
 msgstr " -mcpu=arm710t seçeneğini kullanır"
 
-#: config/tc-arm.c:11728 config/tc-arm.c:11729
+#: config/tc-arm.c:12577 config/tc-arm.c:12578
 msgid "use -mcpu=arm720t"
 msgstr " -mcpu=arm720t seçeneğini kullanır"
 
-#: config/tc-arm.c:11730 config/tc-arm.c:11731
+#: config/tc-arm.c:12579 config/tc-arm.c:12580
 msgid "use -mcpu=arm740t"
 msgstr " -mcpu=arm740t seçeneğini kullanır"
 
-#: config/tc-arm.c:11732 config/tc-arm.c:11733
+#: config/tc-arm.c:12581 config/tc-arm.c:12582
 msgid "use -mcpu=arm8"
 msgstr " -mcpu=arm8 seçeneğini kullanır"
 
-#: config/tc-arm.c:11734 config/tc-arm.c:11735
+#: config/tc-arm.c:12583 config/tc-arm.c:12584
 msgid "use -mcpu=arm810"
 msgstr " -mcpu=arm810 seçeneğini kullanır"
 
-#: config/tc-arm.c:11736 config/tc-arm.c:11737
+#: config/tc-arm.c:12585 config/tc-arm.c:12586
 msgid "use -mcpu=arm9"
 msgstr " -mcpu=arm9 seçeneğini kullanır"
 
-#: config/tc-arm.c:11738 config/tc-arm.c:11739
+#: config/tc-arm.c:12587 config/tc-arm.c:12588
 msgid "use -mcpu=arm9tdmi"
 msgstr " -mcpu=arm9tdmi seçeneğini kullanır"
 
-#: config/tc-arm.c:11740 config/tc-arm.c:11741
+#: config/tc-arm.c:12589 config/tc-arm.c:12590
 msgid "use -mcpu=arm920"
 msgstr " -mcpu=arm920 seçeneğini kullanır"
 
-#: config/tc-arm.c:11742 config/tc-arm.c:11743
+#: config/tc-arm.c:12591 config/tc-arm.c:12592
 msgid "use -mcpu=arm940"
 msgstr " -mcpu=arm940 seçeneğini kullanır"
 
-#: config/tc-arm.c:11744
+#: config/tc-arm.c:12593
 msgid "use -mcpu=strongarm"
 msgstr " -mcpu=strongarm seçeneğini kullanır"
 
-#: config/tc-arm.c:11746
+#: config/tc-arm.c:12595
 msgid "use -mcpu=strongarm110"
 msgstr " -mcpu=strongarm110 seçeneğini kullanır"
 
-#: config/tc-arm.c:11748
+#: config/tc-arm.c:12597
 msgid "use -mcpu=strongarm1100"
 msgstr " -mcpu=strongarm1100 seçeneğini kullanır"
 
-#: config/tc-arm.c:11750
+#: config/tc-arm.c:12599
 msgid "use -mcpu=strongarm1110"
 msgstr " -mcpu=strongarm1110 seçeneğini kullanır"
 
-#: config/tc-arm.c:11751
+#: config/tc-arm.c:12600
 msgid "use -mcpu=xscale"
 msgstr " -mcpu=xscale seçeneğini kullanır"
 
-#: config/tc-arm.c:11752
+#: config/tc-arm.c:12601
 msgid "use -mcpu=iwmmxt"
 msgstr "-mcpu=iwmmxt kullanın"
 
-#: config/tc-arm.c:11753
+#: config/tc-arm.c:12602
 msgid "use -mcpu=all"
 msgstr " -mcpu=all seçeneğini kullanır"
 
 #. Architecture variants -- don't add any more to this list either.
-#: config/tc-arm.c:11756 config/tc-arm.c:11757
+#: config/tc-arm.c:12605 config/tc-arm.c:12606
 msgid "use -march=armv2"
 msgstr " -march=armv2 seçeneğini kullanır"
 
-#: config/tc-arm.c:11758 config/tc-arm.c:11759
+#: config/tc-arm.c:12607 config/tc-arm.c:12608
 msgid "use -march=armv2a"
 msgstr " -march=armv2a seçeneğini kullanır"
 
-#: config/tc-arm.c:11760 config/tc-arm.c:11761
+#: config/tc-arm.c:12609 config/tc-arm.c:12610
 msgid "use -march=armv3"
 msgstr " -march=armv3 seçeneğini kullanır"
 
-#: config/tc-arm.c:11762 config/tc-arm.c:11763
+#: config/tc-arm.c:12611 config/tc-arm.c:12612
 msgid "use -march=armv3m"
 msgstr " -march=armv3m seçeneğini kullanır"
 
-#: config/tc-arm.c:11764 config/tc-arm.c:11765
+#: config/tc-arm.c:12613 config/tc-arm.c:12614
 msgid "use -march=armv4"
 msgstr " -march=armv4 seçeneğini kullanır"
 
-#: config/tc-arm.c:11766 config/tc-arm.c:11767
+#: config/tc-arm.c:12615 config/tc-arm.c:12616
 msgid "use -march=armv4t"
 msgstr " -march=armv4t seçeneğini kullanır"
 
-#: config/tc-arm.c:11768 config/tc-arm.c:11769
+#: config/tc-arm.c:12617 config/tc-arm.c:12618
 msgid "use -march=armv5"
 msgstr " -march=armv5 seçeneğini kullanır"
 
-#: config/tc-arm.c:11770 config/tc-arm.c:11771
+#: config/tc-arm.c:12619 config/tc-arm.c:12620
 msgid "use -march=armv5t"
 msgstr " -march=armv5t seçeneğini kullanır"
 
-#: config/tc-arm.c:11772 config/tc-arm.c:11773
+#: config/tc-arm.c:12621 config/tc-arm.c:12622
 msgid "use -march=armv5te"
 msgstr " -march=armv5te seçeneğini kullanır"
 
 #. Floating point variants -- don't add any more to this list either.
-#: config/tc-arm.c:11776
+#: config/tc-arm.c:12625
 msgid "use -mfpu=fpe"
 msgstr " -mfpu=fpe seçeneğini kullanır"
 
-#: config/tc-arm.c:11777
+#: config/tc-arm.c:12626
 msgid "use -mfpu=fpa10"
 msgstr " -mfpu=fpa10 seçeneğini kullanır"
 
-#: config/tc-arm.c:11778
+#: config/tc-arm.c:12627
 msgid "use -mfpu=fpa11"
 msgstr " -mfpu=fpa11 seçeneğini kullanır"
 
-#: config/tc-arm.c:11780
+#: config/tc-arm.c:12629
 msgid "use either -mfpu=softfpa or -mfpu=softvfp"
 msgstr "ya -mfpu=softfpa ya da -mfpu=softvfp seçeneğini kullanır"
 
-#: config/tc-arm.c:11963
+#: config/tc-arm.c:12862
 msgid "invalid architectural extension"
 msgstr "geçersiz mimari eklenti"
 
-#: config/tc-arm.c:11977
+#: config/tc-arm.c:12876
 msgid "missing architectural extension"
 msgstr "eksik mimari eklenti"
 
-#: config/tc-arm.c:11990
+#: config/tc-arm.c:12889
 #, c-format
 msgid "unknown architectural extnsion `%s'"
 msgstr "`%s' mimari yapısı bilinmiyor"
 
-#: config/tc-arm.c:12015
+#: config/tc-arm.c:12913
 #, c-format
 msgid "missing cpu name `%s'"
 msgstr "`%s' cpu adı eksik"
 
-#: config/tc-arm.c:12031
+#: config/tc-arm.c:12929
 #, c-format
 msgid "unknown cpu `%s'"
 msgstr "bilinmeyen cpu `%s'"
 
-#: config/tc-arm.c:12050
+#: config/tc-arm.c:12947
 #, c-format
 msgid "missing architecture name `%s'"
 msgstr "`%s' mimari ismi eksik"
 
-#: config/tc-arm.c:12067
+#: config/tc-arm.c:12964
 #, c-format
 msgid "unknown architecture `%s'\n"
 msgstr "`%s' mimarisi bilinmiyor\n"
 
-#: config/tc-arm.c:12084
+#: config/tc-arm.c:12980
 #, c-format
 msgid "unknown floating point format `%s'\n"
 msgstr "bilinmeyen kayan nokta biçemi '%s'\n"
 
-#: config/tc-arm.c:12090
+#: config/tc-arm.c:12996
+#, fuzzy, c-format
+msgid "unknown floating point abi `%s'\n"
+msgstr "bilinmeyen kayan nokta biçemi '%s'\n"
+
+#: config/tc-arm.c:13012
+#, fuzzy, c-format
+msgid "unknown EABI `%s'\n"
+msgstr "bilinmeyen cpu `%s'"
+
+#: config/tc-arm.c:13019
 msgid "<cpu name>\t  assemble for CPU <cpu name>"
 msgstr "<cpu adı>\t  <cpu adı> CPU'su için çevirir"
 
-#: config/tc-arm.c:12092
+#: config/tc-arm.c:13021
 msgid "<arch name>\t  assemble for architecture <arch name>"
 msgstr "<mimari adı>\t  <mimari adı> mimarisi için çevirir"
 
-#: config/tc-arm.c:12094
+#: config/tc-arm.c:13023
 msgid "<fpu name>\t  assemble for FPU architecture <fpu name>"
 msgstr "<fpu adı>\t  <fpu adı> FPU mimarisi için çevirir"
 
-#: config/tc-arm.c:12136 config/tc-arm.c:12158
+#: config/tc-arm.c:13025
+msgid "<abi>\t  assemble for floating point ABI <abi>"
+msgstr ""
+
+#: config/tc-arm.c:13028
+#, fuzzy
+msgid "<ver>\t  assemble for eabi version <ver>"
+msgstr "<mimari adı>\t  <mimari adı> mimarisi için çevirir"
+
+#: config/tc-arm.c:13069 config/tc-arm.c:13091
 #, c-format
 msgid "option `-%c%s' is deprecated: %s"
 msgstr "`-%c%s' seçeneği artık kullanılmıyor: %s"
 
-#: config/tc-arm.c:12167
+#: config/tc-arm.c:13112
 #, c-format
-msgid "unrecognized option `-%c%s'"
-msgstr "bilinmeyen seçenek: `-%c%s'"
-
-#: config/tc-arm.c:12181
 msgid " ARM-specific assembler options:\n"
 msgstr " ARM'a özgü çevirici seçenekleri:\n"
 
-#: config/tc-arm.c:12192
+#: config/tc-arm.c:13123
+#, c-format
 msgid "  -EB                     assemble code for a big-endian cpu\n"
 msgstr "  -EB                     büyük-sonlu bir cpu için kod çevrimi yapar\n"
 
-#: config/tc-arm.c:12197
+#: config/tc-arm.c:13128
+#, c-format
 msgid "  -EL                     assemble code for a little-endian cpu\n"
 msgstr "  -EL                     küçük-sonlu bir cpu için kod çevrimi yapar\n"
 
-#: config/tc-arm.c:12381
+#: config/tc-arm.c:13270
 #, c-format
 msgid "%s: unexpected function type: %d"
 msgstr "%s: beklenmeyen işlev türü: %d"
 
-#: config/tc-arm.c:12756
+#: config/tc-arm.c:13540
+#, fuzzy
+msgid "expected 0 or 1"
+msgstr "%c beklendi"
+
+#: config/tc-arm.c:13545
+#, fuzzy
+msgid "missing comma"
+msgstr "`do' eksik"
+
+#: config/tc-arm.c:13838
+msgid "handerdata in cantunwind frame"
+msgstr ""
+
+#: config/tc-arm.c:13855
+msgid "too many unwind opcodes for personality routine 0"
+msgstr ""
+
+#: config/tc-arm.c:13887
+#, fuzzy
+msgid "too many unwind opcodes"
+msgstr "çok fazla işlenen"
+
+#: config/tc-arm.c:14017
+#, fuzzy
+msgid "dupicate .handlerdata directive"
+msgstr "eşleşmeyen end yönergesi"
+
+#: config/tc-arm.c:14071
+msgid "personality routine specified for cantunwind frame"
+msgstr ""
+
+#: config/tc-arm.c:14085
+#, fuzzy
+msgid "duplicate .personalityindex directive"
+msgstr "eşleşmeyen end yönergesi"
+
+#: config/tc-arm.c:14094
+msgid "bad personality routine number"
+msgstr ""
+
+#: config/tc-arm.c:14113
+#, fuzzy
+msgid "duplicate .personality directive"
+msgstr "psr bit belirteci tekrarlandı"
+
+#: config/tc-arm.c:14139 config/tc-arm.c:14261
+#, fuzzy
+msgid "expected register list"
+msgstr "yazmaç beklendi"
+
+#: config/tc-arm.c:14217
+#, fuzzy
+msgid "expected , <constant>"
+msgstr "<nn> beklendi"
+
+#: config/tc-arm.c:14322
+#, fuzzy
+msgid "expected wr or wcgr"
+msgstr "%c beklendi"
+
+#: config/tc-arm.c:14343
+#, fuzzy
+msgid "bad register range"
+msgstr "Hatalı yazmaç aralığı"
+
+#: config/tc-arm.c:14358
+#, fuzzy
+msgid "inconsistent register types"
+msgstr "yazmaç listesinde hatalı yazmaç"
+
+#. TODO: Maverick registers.
+#: config/tc-arm.c:14506
+#, fuzzy
+msgid "unrecognised register"
+msgstr "Bilinmeyen yazmaç ismi"
+
+#: config/tc-arm.c:14529
+#, c-format
+msgid "r%d not permitted in .unwind_movsp directive"
+msgstr ""
+
+#: config/tc-arm.c:14535
+#, fuzzy
+msgid "unexpected .unwind_movsp directive"
+msgstr "içiçe .ent yönergeleri"
+
+#: config/tc-arm.c:14567
+#, fuzzy
+msgid "expected #constant"
+msgstr "<nn> beklendi"
+
+#: config/tc-arm.c:14587
+#, fuzzy
+msgid "stack increment must be multiple of 4"
+msgstr "işlenen 4'ün katı olmalı"
+
+#: config/tc-arm.c:14616
+#, fuzzy
+msgid "expected <reg>, <reg>"
+msgstr "@(exp, reg16) beklendi"
+
+#: config/tc-arm.c:14634
+msgid "register must be either sp or set by a previousunwind_movsp directive"
+msgstr ""
+
+#: config/tc-arm.c:14671
+msgid "expected <offset>, <opcode>"
+msgstr ""
+
+#: config/tc-arm.c:14683
+#, fuzzy
+msgid "unwind opcode too long"
+msgstr "bilinmeyen opkod %s"
+
+#: config/tc-arm.c:14688
+#, fuzzy
+msgid "invalid unwind opcode"
+msgstr "geçersiz opkod"
+
+#: config/tc-arm.c:14783
 msgid "alignments greater than 32 bytes not supported in .text sections."
 msgstr "32 bayttan daha büyük hizalamalar .text bölümlerinde desteklenmiyor."
 
-#: config/tc-arm.h:98
+#: config/tc-arm.h:84
 msgid "arm convert_frag\n"
 msgstr "arm convert_frag\n"
 
-#: config/tc-avr.c:203
+#: config/tc-avr.c:215
+#, c-format
 msgid "Known MCU names:"
 msgstr "Bilinen MCU adları:"
 
-#: config/tc-avr.c:272
+#: config/tc-avr.c:284
+#, c-format
 msgid ""
 "AVR options:\n"
 "  -mmcu=[avr-name] select microcontroller variant\n"
@@ -2707,7 +2980,8 @@ msgstr ""
 "                   avr5 - ATmega161, ATmega163, ATmega32, AT94K\n"
 "                   veya şimdiki mikrodenetçi adı.\n"
 
-#: config/tc-avr.c:282
+#: config/tc-avr.c:294
+#, c-format
 msgid ""
 "  -mall-opcodes    accept all AVR opcodes, even if not supported by MCU\n"
 "  -mno-skip-bug    disable warnings for skipping two-word instructions\n"
@@ -2722,386 +2996,646 @@ msgstr ""
 "  -mno-wrap        8K baÅŸa sarmaya sahip rjmp/rcall iÅŸlemlerini reddeder\n"
 "                   (avr3, avr5 için öntanımlı)\n"
 
-#: config/tc-avr.c:330 config/tc-msp430.c:257
+#: config/tc-avr.c:342 config/tc-msp430.c:697
 #, c-format
 msgid "unknown MCU: %s\n"
 msgstr "bilinmeyen MCU: %s\n"
 
-#: config/tc-avr.c:339
+#: config/tc-avr.c:351
 #, c-format
 msgid "redefinition of mcu type `%s' to `%s'"
 msgstr "mcu türü `%s'den `%s'ye yeniden tanımlandı"
 
-#: config/tc-avr.c:390 config/tc-d10v.c:319 config/tc-d30v.c:365
-#: config/tc-mips.c:10136 config/tc-mmix.c:2246 config/tc-mn10200.c:361
-#: config/tc-msp430.c:378 config/tc-pj.c:374 config/tc-ppc.c:5105
-#: config/tc-sh.c:2528 config/tc-v850.c:1245
+#: config/tc-avr.c:402 config/tc-crx.c:490 config/tc-d10v.c:319
+#: config/tc-d30v.c:366 config/tc-mips.c:10029 config/tc-mmix.c:2297
+#: config/tc-mn10200.c:361 config/tc-msp430.c:805 config/tc-pj.c:373
+#: config/tc-ppc.c:5192 config/tc-sh.c:2972 config/tc-v850.c:1242
 msgid "bad call to md_atof"
 msgstr "md_atof'a hatalı çağrı"
 
-#: config/tc-avr.c:453
+#: config/tc-avr.c:465
 msgid "constant value required"
 msgstr "sabit deÄŸer gerekli"
 
-#: config/tc-avr.c:456
+#: config/tc-avr.c:468
 #, c-format
 msgid "number must be less than %d"
 msgstr "sayı %d'den daha az olmalı"
 
-#: config/tc-avr.c:508
+#: config/tc-avr.c:520
 msgid "`,' required"
 msgstr "`,' gerekli"
 
-#: config/tc-avr.c:527
+#: config/tc-avr.c:539
 msgid "undefined combination of operands"
 msgstr "tanımlanmamış işlenenler bileşimi"
 
-#: config/tc-avr.c:536
+#: config/tc-avr.c:549
 msgid "skipping two-word instruction"
 msgstr "iki-wordluk işlem atlandı"
 
-#: config/tc-avr.c:598
+#: config/tc-avr.c:582 config/tc-avr.c:1274
+#, c-format
+msgid "constant out of 8-bit range: %d"
+msgstr "8-bitlik aralık dışında sabit: %d"
+
+#: config/tc-avr.c:636
 msgid "register r16-r23 required"
 msgstr "r16-r23 yazmaçları gerekli"
 
-#: config/tc-avr.c:604
+#: config/tc-avr.c:642
 msgid "register number above 15 required"
 msgstr "yazmaç numarası 15'den büyük olmalı"
 
-#: config/tc-avr.c:610
+#: config/tc-avr.c:648
 msgid "even register number required"
 msgstr "yazmaç numarası çift olmalı"
 
-#: config/tc-avr.c:616
+#: config/tc-avr.c:654
 msgid "register r24, r26, r28 or r30 required"
 msgstr "r24, r26, r28 veya r30 yazmaçları gerekli"
 
-#: config/tc-avr.c:622
+#: config/tc-avr.c:660
 msgid "register name or number from 0 to 31 required"
 msgstr "yazmaç ismi veya 0'dan 31'e kadar numara gerekli"
 
-#: config/tc-avr.c:640
+#: config/tc-avr.c:678
 msgid "pointer register (X, Y or Z) required"
 msgstr "imleyici yazmacı (X, Y veya Z) gerekli"
 
-#: config/tc-avr.c:647
+#: config/tc-avr.c:685
 msgid "cannot both predecrement and postincrement"
 msgstr "ön-eksiltme ve sonra-arttırma işlemlerinin ikisi birden uygulanamaz"
 
-#: config/tc-avr.c:655
+#: config/tc-avr.c:693
 msgid "addressing mode not supported"
 msgstr "adresleme kipi desteklenmiyor"
 
-#: config/tc-avr.c:661
+#: config/tc-avr.c:699
 msgid "can't predecrement"
 msgstr "ön-eksiltme yapılamaz"
 
-#: config/tc-avr.c:664
+#: config/tc-avr.c:702
 msgid "pointer register Z required"
 msgstr "imleyici yazmacı Z gerekli"
 
-#: config/tc-avr.c:682
+#: config/tc-avr.c:720
 msgid "pointer register (Y or Z) required"
 msgstr "imleyici yazmacı (Y veya Z) gerekli"
 
-#: config/tc-avr.c:787
+#: config/tc-avr.c:824
 #, c-format
 msgid "unknown constraint `%c'"
 msgstr "`%c' bilinmeyen kısıtı"
 
-#: config/tc-avr.c:881 config/tc-avr.c:897 config/tc-avr.c:998
-#: config/tc-msp430.c:1431 config/tc-msp430.c:1448
+#: config/tc-avr.c:918 config/tc-avr.c:934 config/tc-avr.c:1056
+#: config/tc-msp430.c:1899 config/tc-msp430.c:1917
 #, c-format
 msgid "odd address operand: %ld"
 msgstr "tek sayılı adres işleneni: %ld"
 
-#: config/tc-avr.c:889 config/tc-avr.c:908 config/tc-d10v.c:586
-#: config/tc-d30v.c:655 config/tc-msp430.c:1439 config/tc-msp430.c:1453
-#: config/tc-msp430.c:1463
+#: config/tc-avr.c:926 config/tc-avr.c:945 config/tc-avr.c:967
+#: config/tc-avr.c:974 config/tc-avr.c:981 config/tc-d10v.c:586
+#: config/tc-d30v.c:656 config/tc-msp430.c:1907 config/tc-msp430.c:1922
+#: config/tc-msp430.c:1932
 #, c-format
 msgid "operand out of range: %ld"
 msgstr "işlenen kapsam dışı: %ld"
 
-#: config/tc-avr.c:1007 config/tc-d10v.c:1793 config/tc-d30v.c:1973
-#: config/tc-msp430.c:1481
+#: config/tc-avr.c:1065 config/tc-d10v.c:1791 config/tc-d30v.c:1958
+#: config/tc-msp430.c:1950
 #, c-format
 msgid "line %d: unknown relocation type: 0x%x"
 msgstr "satır %d: bilinmeyen yerdeğişim türü: 0x%x"
 
-#: config/tc-avr.c:1021
+#: config/tc-avr.c:1079
 msgid "only constant expression allowed"
 msgstr "yalnız sabit ifadeler kullanılabilir"
 
-#: config/tc-avr.c:1057 config/tc-d10v.c:1659 config/tc-d30v.c:1806
-#: config/tc-mn10200.c:1255 config/tc-mn10300.c:2303 config/tc-msp430.c:1520
-#: config/tc-or32.c:1618 config/tc-ppc.c:5919 config/tc-v850.c:2264
+#: config/tc-avr.c:1115 config/tc-d10v.c:1657 config/tc-d30v.c:1791
+#: config/tc-mn10200.c:1262 config/tc-mn10300.c:2308 config/tc-msp430.c:1986
+#: config/tc-or32.c:1587 config/tc-ppc.c:6013 config/tc-v850.c:2274
 #, c-format
 msgid "reloc %d not supported by object file format"
 msgstr "%d yerdeğişimi nesne dosya biçeminde desteklenmiyor"
 
-#: config/tc-avr.c:1081 config/tc-d10v.c:1248 config/tc-d10v.c:1262
-#: config/tc-h8300.c:1915 config/tc-h8500.c:1106 config/tc-mcore.c:938
-#: config/tc-msp430.c:438 config/tc-pj.c:283 config/tc-sh.c:2096
-#: config/tc-z8k.c:1238
+#: config/tc-avr.c:1139 config/tc-d10v.c:1248 config/tc-d10v.c:1262
+#: config/tc-h8300.c:1887 config/tc-h8500.c:1106 config/tc-mcore.c:939
+#: config/tc-msp430.c:1769 config/tc-pj.c:282 config/tc-sh.c:2425
+#: config/tc-z8k.c:1200
 msgid "can't find opcode "
 msgstr "opkod bulunamadı"
 
-#: config/tc-avr.c:1098
+#: config/tc-avr.c:1156
 #, c-format
 msgid "illegal opcode %s for mcu %s"
 msgstr "mcu %2$s için geçersiz %1$s opkodu"
 
-#: config/tc-avr.c:1106
+#: config/tc-avr.c:1164
 msgid "garbage at end of line"
 msgstr "satırsonunda bozukluk"
 
-#: config/tc-avr.c:1170 read.c:3226
+#: config/tc-avr.c:1228 read.c:3203
 msgid "illegal expression"
 msgstr "geçersiz ifade"
 
-#: config/tc-avr.c:1196 config/tc-avr.c:1262
+#: config/tc-avr.c:1254 config/tc-avr.c:1318
 msgid "`)' required"
 msgstr "`)' gerekli"
 
-#: config/tc-avr.c:1216
-#, c-format
-msgid "constant out of 8-bit range: %d"
-msgstr "8-bitlik aralık dışında sabit: %d"
-
-#: config/tc-avr.c:1219
-msgid "expression possibly out of 8-bit range"
-msgstr "ifade 8-bitlik aralık dışında olabilir"
-
-#: config/tc-avr.c:1290 config/tc-avr.c:1297
+#: config/tc-avr.c:1346 config/tc-avr.c:1353
 #, c-format
 msgid "illegal %srelocation size: %d"
 msgstr "geçersiz %s yerdeğişim boyu: %d"
 
-#: config/tc-cris.c:386 config/tc-m68hc11.c:2831
+#: config/tc-cris.c:540 config/tc-m68hc11.c:2794
 #, c-format
 msgid "internal inconsistency problem in %s: fr_symbol %lx"
 msgstr "%s içinde iç tutarlılık problemi: fr_symbol %lx"
 
-#: config/tc-cris.c:390 config/tc-m68hc11.c:2835
+#: config/tc-cris.c:544 config/tc-m68hc11.c:2798 config/tc-msp430.c:2177
 #, c-format
 msgid "internal inconsistency problem in %s: resolved symbol"
 msgstr "%s içinde iç tutarlılık problemi: çözümlenmiş sembol"
 
-#: config/tc-cris.c:396 config/tc-m68hc11.c:2841
+#: config/tc-cris.c:554 config/tc-m68hc11.c:2804
 #, c-format
 msgid "internal inconsistency problem in %s: fr_subtype %d"
 msgstr "%s içinde iç tutarlılık problemi: fr_subtype %d"
 
-#: config/tc-cris.c:650
+#: config/tc-cris.c:885
+msgid "Relaxation to long branches for .arch common_v10_v32 not implemented"
+msgstr ""
+
+#: config/tc-cris.c:915
+msgid "Complicated LAPC target operand is not a multiple of two.  Use LAPC.D"
+msgstr ""
+
+#: config/tc-cris.c:920
+#, c-format
+msgid "Internal error found in md_convert_frag: offset %ld.  Please report this."
+msgstr ""
+
+#: config/tc-cris.c:945
 #, c-format
 msgid "internal inconsistency in %s: bdapq no symbol"
 msgstr "%s içinde iç tutarlılık problemi: bdapq sembol yok"
 
-#: config/tc-cris.c:663
+#: config/tc-cris.c:958
 #, c-format
 msgid "internal inconsistency in %s: bdap.w with no symbol"
 msgstr "%s içinde iç tutarlılık problemi: bdap w ile sembol yok"
 
-#: config/tc-cris.c:807
+#: config/tc-cris.c:982
+msgid "section alignment must be >= 4 bytes to check MULS/MULU safeness"
+msgstr ""
+
+#: config/tc-cris.c:991
+msgid "dangerous MULS/MULU location; give it higher alignment"
+msgstr ""
+
+#: config/tc-cris.c:1103
+msgid "Out-of-range .word offset handling is not implemented for .arch common_v10_v32"
+msgstr ""
+
+#: config/tc-cris.c:1168 config/tc-crx.c:581 config/tc-crx.c:608
+#: config/tc-crx.c:626
 msgid "Virtual memory exhausted"
 msgstr "Sanal bellek tükendi"
 
-#: config/tc-cris.c:815
+#: config/tc-cris.c:1201 config/tc-crx.c:591
 #, c-format
 msgid "Can't hash `%s': %s\n"
 msgstr "`%s' hash'lenemedi: %s\n"
 
-#: config/tc-cris.c:816
+#: config/tc-cris.c:1202 config/tc-crx.c:592
 msgid "(unknown reason)"
 msgstr "(bilinmeyen sebep)"
 
-#: config/tc-cris.c:820
+#: config/tc-cris.c:1206
 #, c-format
 msgid "Buggy opcode: `%s' \"%s\"\n"
 msgstr "Hatalı opkod: `%s' \"%s\"\n"
 
-#: config/tc-cris.c:1164
+#: config/tc-cris.c:1621
 #, c-format
 msgid "Immediate value not in 5 bit unsigned range: %ld"
 msgstr "Şimdiki değer 5bitlik unsigned aralıkta değil: %ld"
 
-#: config/tc-cris.c:1180
+#: config/tc-cris.c:1637
 #, c-format
 msgid "Immediate value not in 4 bit unsigned range: %ld"
 msgstr "Şimdiki değer 4bitlik unsigned aralıkta değil: %ld"
 
-#: config/tc-cris.c:1219
+#: config/tc-cris.c:1689
 #, c-format
 msgid "Immediate value not in 6 bit range: %ld"
 msgstr "Şimdiki değer 6bitlik aralıkta değil: %ld"
 
-#: config/tc-cris.c:1234
+#: config/tc-cris.c:1704
 #, c-format
 msgid "Immediate value not in 6 bit unsigned range: %ld"
 msgstr "Şimdiki değer 6bitlik unsigned aralıkta değil: %ld"
 
 #. Others have a generic warning.
-#: config/tc-cris.c:1324
+#: config/tc-cris.c:1812
 #, c-format
 msgid "Unimplemented register `%s' specified"
 msgstr "Desteklenmeyen `%s' yazmacı belirtilmiş"
 
 #. We've come to the end of instructions with this
 #. opcode, so it must be an error.
-#: config/tc-cris.c:1483
+#: config/tc-cris.c:2055
 msgid "Illegal operands"
 msgstr "Geçersiz işlenenler"
 
-#: config/tc-cris.c:1514 config/tc-cris.c:1545
+#: config/tc-cris.c:2096 config/tc-cris.c:2136
 #, c-format
 msgid "Immediate value not in 8 bit range: %ld"
 msgstr "Şimdiki değer 8bit aralığında değil: %ld"
 
-#: config/tc-cris.c:1524 config/tc-cris.c:1552
+#: config/tc-cris.c:2106 config/tc-cris.c:2157
 #, c-format
 msgid "Immediate value not in 16 bit range: %ld"
 msgstr "Şimdiki değer 16bit aralığında değil: %ld"
 
-#: config/tc-cris.c:1573
+#: config/tc-cris.c:2141
+#, fuzzy, c-format
+msgid "Immediate value not in 8 bit signed range: %ld"
+msgstr "Şimdiki değer 5bitlik unsigned aralıkta değil: %ld"
+
+#: config/tc-cris.c:2146
+#, fuzzy, c-format
+msgid "Immediate value not in 8 bit unsigned range: %ld"
+msgstr "Şimdiki değer 6bitlik unsigned aralıkta değil: %ld"
+
+#: config/tc-cris.c:2162
+#, fuzzy, c-format
+msgid "Immediate value not in 16 bit signed range: %ld"
+msgstr "Şimdiki değer 6bitlik unsigned aralıkta değil: %ld"
+
+#: config/tc-cris.c:2167
+#, fuzzy, c-format
+msgid "Immediate value not in 16 bit unsigned range: %ld"
+msgstr "Şimdiki değer 6bitlik unsigned aralıkta değil: %ld"
+
+#: config/tc-cris.c:2189
 msgid "PIC relocation size does not match operand size"
 msgstr "PIC yerdeÄŸiÅŸim boyu iÅŸlenen boyuyla eÅŸleÅŸmiyor"
 
-#: config/tc-cris.c:2572
+#: config/tc-cris.c:3355
+msgid "Calling gen_cond_branch_32 for .arch common_v10_v32\n"
+msgstr ""
+
+#: config/tc-cris.c:3359
 msgid "32-bit conditional branch generated"
 msgstr "32-bit koÅŸullu dal oluÅŸturuldu"
 
-#: config/tc-cris.c:2626
+#: config/tc-cris.c:3418
 msgid "Complex expression not supported"
 msgstr "Karmaşık ifadeler desteklenmiyor"
 
 #. FIXME:  Is this function mentioned in the internals.texi manual?  If
 #. not, add it.
-#: config/tc-cris.c:2747
+#: config/tc-cris.c:3546
 msgid "Bad call to md_atof () - floating point formats are not supported"
 msgstr "md_atof()'a hatalı çağrı -- kayan noktalı biçemler desteklenmiyor"
 
-#: config/tc-cris.c:2794
+#: config/tc-cris.c:3592
 msgid "PC-relative relocation must be trivially resolved"
 msgstr "PC-göreceli yerdeğişimler basitçe çözümlenmeli"
 
-#: config/tc-cris.c:2837
+#: config/tc-cris.c:3645
 #, c-format
 msgid "Value not in 16 bit range: %ld"
 msgstr "Değer 16bit aralığında değil: %ld"
 
-#: config/tc-cris.c:2848
+#: config/tc-cris.c:3656
+#, fuzzy, c-format
+msgid "Value not in 16 bit signed range: %ld"
+msgstr "Değer 6bit unsigned aralığında değil: %ld"
+
+#: config/tc-cris.c:3667
 #, c-format
 msgid "Value not in 8 bit range: %ld"
 msgstr "Değer 8bit aralığında değil: %ld"
 
-#: config/tc-cris.c:2855
+#: config/tc-cris.c:3675
+#, fuzzy, c-format
+msgid "Value not in 8 bit signed range: %ld"
+msgstr "Değer 6bit unsigned aralığında değil: %ld"
+
+#: config/tc-cris.c:3686
 #, c-format
 msgid "Value not in 4 bit unsigned range: %ld"
 msgstr "Değer 4bit unsigned aralığında değil: %ld"
 
-#: config/tc-cris.c:2862
+#: config/tc-cris.c:3694
 #, c-format
 msgid "Value not in 5 bit unsigned range: %ld"
 msgstr "Değer 5bit unsigned aralığında değil: %ld"
 
-#: config/tc-cris.c:2869
+#: config/tc-cris.c:3702
 #, c-format
 msgid "Value not in 6 bit range: %ld"
 msgstr "Değer 6bit aralığında değil: %ld"
 
-#: config/tc-cris.c:2876
+#: config/tc-cris.c:3710
 #, c-format
 msgid "Value not in 6 bit unsigned range: %ld"
 msgstr "Değer 6bit unsigned aralığında değil: %ld"
 
-#: config/tc-cris.c:2924
+#: config/tc-cris.c:3758
+#, c-format
 msgid "Please use --help to see usage and options for this assembler.\n"
 msgstr "Kullanım ve seçenek bilgileri için lütfen --help seçeneğini kullanın.\n"
 
-#: config/tc-cris.c:2936
+#: config/tc-cris.c:3770
 msgid "--no-underscore is invalid with a.out format"
 msgstr "--no-underscore seçeneği a.out biçemi ile kullanılamaz"
 
-#: config/tc-cris.c:3012
+#: config/tc-cris.c:3790
+#, fuzzy, c-format
+msgid "invalid <arch> in --march=<arch>: %s"
+msgstr "geçersiz yapı -march=%s"
+
+#: config/tc-cris.c:3888
 msgid "Semantics error.  This type of operand can not be relocated, it must be an assembly-time constant"
 msgstr "Sözdizim hatası. Bu tür işlenenin yeri değiştirilemez, çevrim sırasında sabit olmalıdır."
 
-#: config/tc-cris.c:3064
+#: config/tc-cris.c:3937
 #, c-format
 msgid "Cannot generate relocation type for symbol %s, code %s"
 msgstr "%s sembolü, %s kodu için yerdeğişim oluşturulamadı."
 
 #. The messages are formatted to line up with the generic options.
-#: config/tc-cris.c:3078
+#: config/tc-cris.c:3951
+#, c-format
 msgid "CRIS-specific options:\n"
 msgstr "CRIS'a özgü seçenekler:\n"
 
-#: config/tc-cris.c:3080
+#: config/tc-cris.c:3953
 msgid "  -h, -H                  Don't execute, print this help text.  Deprecated.\n"
 msgstr ""
 "  -h, -H                  İşlem yapmaz, bu yardım iletisini gösterir. \n"
 "                          Artık kullanılmıyor.\n"
 
-#: config/tc-cris.c:3082
+#: config/tc-cris.c:3955
 msgid "  -N                      Warn when branches are expanded to jumps.\n"
 msgstr "  -N                      Dallar atlama olarak genişletildiği zaman uyarır\n"
 
-#: config/tc-cris.c:3084
+#: config/tc-cris.c:3957
 msgid "  --underscore            User symbols are normally prepended with underscore.\n"
 msgstr "  --underscore            Kullanıcı sembolleri altçizgi ile başlatılır.\n"
 
-#: config/tc-cris.c:3086
+#: config/tc-cris.c:3959
 msgid "                          Registers will not need any prefix.\n"
 msgstr "                          Yazmaçların öneklere ihtiyacı yoktur.\n"
 
-#: config/tc-cris.c:3088
+#: config/tc-cris.c:3961
 msgid "  --no-underscore         User symbols do not have any prefix.\n"
 msgstr "  --no-underscore         Kullanıcı sembolleri önek içermez.\n"
 
-#: config/tc-cris.c:3090
+#: config/tc-cris.c:3963
 msgid "                          Registers will require a `$'-prefix.\n"
 msgstr "                          Yazmaçlar `$' öneki gerektirir.\n"
 
-#: config/tc-cris.c:3092
+#: config/tc-cris.c:3965
 msgid "  --pic\t\t\tEnable generation of position-independent code.\n"
 msgstr "  --pic\t\t\tYerden bağımsız kodun üretimine izin verir.\n"
 
-#: config/tc-cris.c:3115
+#: config/tc-cris.c:3967
+msgid ""
+"  --march=<arch>\t\tGenerate code for <arch>.  Valid choices for <arch>\n"
+"\t\t\t\tare v0_v10, v10, v32 and common_v10_v32.\n"
+msgstr ""
+
+#: config/tc-cris.c:3991
 msgid "Invalid relocation"
 msgstr "Geçersiz yerdeğişim"
 
-#: config/tc-cris.c:3149
+#: config/tc-cris.c:4029
 msgid "Invalid pc-relative relocation"
 msgstr "Geçersiz pc-göreli yerdeğişimi"
 
-#: config/tc-cris.c:3198
+#: config/tc-cris.c:4078
 #, c-format
 msgid "Adjusted signed .word (%ld) overflows: `switch'-statement too large."
 msgstr "Signed .word (%ld) taşmaları düzeltildi: `switch' deyimi fazla büyük."
 
-#: config/tc-cris.c:3225
+#: config/tc-cris.c:4105
 #, c-format
 msgid ".syntax %s requires command-line option `--underscore'"
 msgstr "%s .syntax sözdizimi `--underscore' komut satırı seçeneğini gerektirir"
 
-#: config/tc-cris.c:3234
+#: config/tc-cris.c:4114
 #, c-format
 msgid ".syntax %s requires command-line option `--no-underscore'"
 msgstr "%s .syntax sözdizimi `--no-underscore' komut satırı seçeneğini gerektirir"
 
-#: config/tc-cris.c:3272
+#: config/tc-cris.c:4152
 msgid "Unknown .syntax operand"
 msgstr "Bilinmeyen .syntax iÅŸleneni"
 
-#: config/tc-cris.c:3283
+#: config/tc-cris.c:4163
 msgid "Pseudodirective .file is only valid when generating ELF"
 msgstr ".file sanalyönergesi yalnız ELF üretilirken geçerli"
 
-#: config/tc-cris.c:3296
+#: config/tc-cris.c:4176
 msgid "Pseudodirective .loc is only valid when generating ELF"
 msgstr ".loc sanal yönergesi yalnız ELF üretilirken geçerli"
 
+#: config/tc-cris.c:4322
+#, fuzzy
+msgid "unknown operand to .arch"
+msgstr "bilinmeyen iÅŸlenen %s"
+
+#: config/tc-cris.c:4331
+msgid ".arch <arch> requires a matching --march=... option"
+msgstr ""
+
+#: config/tc-crx.c:343 config/tc-mn10200.c:1249 write.c:2649
+#, c-format
+msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
+msgstr "`%s' çözümlenemedi {%s bölümü} - `%s' {%s bölümü}"
+
+#: config/tc-crx.c:359
+#, fuzzy, c-format
+msgid "internal error: reloc %d (`%s') not supported by object file format"
+msgstr "%d yerdeğişimi nesne dosya biçeminde desteklenmiyor"
+
+#: config/tc-crx.c:618 config/tc-crx.c:636 config/tc-i386.c:938
+#: config/tc-i386.c:961 config/tc-m68k.c:4193
+#, c-format
+msgid "Internal Error:  Can't hash %s: %s"
+msgstr "İç Hata: %s hash'lenemedi: %s"
+
+#. Missing or bad expr becomes absolute 0.
+#: config/tc-crx.c:664 config/tc-i386.c:4111
+#, c-format
+msgid "missing or invalid displacement expression `%s' taken as 0"
+msgstr "eksik veya hatalı yerdeğişim ifadesi `%s' 0 varsayıldı"
+
+#: config/tc-crx.c:802 config/tc-crx.c:822 config/tc-crx.c:837
+#, fuzzy, c-format
+msgid "Illegal register `%s' in Instruction `%s'"
+msgstr "listede geçersiz yazmaç var"
+
+#: config/tc-crx.c:865
+#, c-format
+msgid "Illegal Scale - `%d'"
+msgstr ""
+
+#: config/tc-crx.c:981
+#, fuzzy, c-format
+msgid "Illegal operands (whitespace): `%s'"
+msgstr "%s için geçersiz işlenen"
+
+#: config/tc-crx.c:993 config/tc-crx.c:1000 config/tc-crx.c:1017
+#: config/tc-crx.c:1803
+#, fuzzy, c-format
+msgid "Missing matching brackets : `%s'"
+msgstr "`%s' mimari ismi eksik"
+
+#: config/tc-crx.c:1043
+#, fuzzy, c-format
+msgid "Unknown exception: `%s'"
+msgstr "Bilinmeyen opkod: `%s'"
+
+#: config/tc-crx.c:1139
+#, fuzzy, c-format
+msgid "Illegal `cinv' parameter: `%c'"
+msgstr "Geçersiz temel karakter %c.\n"
+
+#: config/tc-crx.c:1172
+#, fuzzy, c-format
+msgid "Unknown register: `%d'"
+msgstr "Tanımlanmamış yazmaç: '%s'."
+
+#. Issue a error message when register is illegal.
+#: config/tc-crx.c:1180
+#, fuzzy, c-format
+msgid "Illegal register (`%s') in Instruction: `%s'"
+msgstr "Ä°ÅŸlemin sonunda bozukluk: `%s'."
+
+#: config/tc-crx.c:1309
+#, fuzzy, c-format
+msgid "Illegal Co-processor register in Instruction `%s' "
+msgstr "Bu işlem için geçersiz kaynak yazmacı, 'tfr' kullanın."
+
+#: config/tc-crx.c:1316
+#, c-format
+msgid "Illegal Co-processor special register in Instruction `%s' "
+msgstr ""
+
+#: config/tc-crx.c:1615
+#, fuzzy
+msgid "Incorrect number of operands"
+msgstr "Hatalı sayıda işlenen"
+
+#: config/tc-crx.c:1617
+#, fuzzy, c-format
+msgid "Illegal type of operand (arg %d)"
+msgstr "%s için geçersiz işlenen"
+
+#: config/tc-crx.c:1623
+#, fuzzy, c-format
+msgid "Operand out of range (arg %d)"
+msgstr "işlenen aralık dışı: %d"
+
+#: config/tc-crx.c:1626
+#, fuzzy, c-format
+msgid "Operand has odd displacement (arg %d)"
+msgstr "%x'da tek sayılı sıçrama"
+
+#: config/tc-crx.c:1629
+#, fuzzy, c-format
+msgid "Invalid DISPU4 operand value (arg %d)"
+msgstr "Geçersiz işlenen (1, 2 veya 3 kullanın)"
+
+#: config/tc-crx.c:1632
+#, fuzzy, c-format
+msgid "Invalid CST4 operand value (arg %d)"
+msgstr "Geçersiz işlenen (1, 2 veya 3 kullanın)"
+
+#: config/tc-crx.c:1635
+#, c-format
+msgid "Operand value is not within upper 64 KB (arg %d)"
+msgstr ""
+
+#: config/tc-crx.c:1639 config/tc-crx.c:1670
+#, fuzzy, c-format
+msgid "Illegal operand (arg %d)"
+msgstr "%s için geçersiz işlenen"
+
+#: config/tc-crx.c:1701 config/tc-crx.c:1718
+#, c-format
+msgid "Same src/dest register is used (`r%d'), result is undefined"
+msgstr ""
+
+#: config/tc-crx.c:1710
+#, c-format
+msgid "`%s' has undefined result"
+msgstr ""
+
+#: config/tc-crx.c:1772
+#, fuzzy
+msgid "Invalid Register in Register List"
+msgstr "geçersiz yazmaç listesi"
+
+#: config/tc-crx.c:1826
+#, fuzzy, c-format
+msgid "Illegal register `%s' in cop-register list"
+msgstr "listede geçersiz yazmaç var"
+
+#: config/tc-crx.c:1834
+#, fuzzy, c-format
+msgid "Illegal register `%s' in cop-special-register list"
+msgstr "listede geçersiz yazmaç var"
+
+#: config/tc-crx.c:1853
+#, fuzzy, c-format
+msgid "Illegal register `%s' in user register list"
+msgstr "listede geçersiz yazmaç var"
+
+#: config/tc-crx.c:1872
+#, fuzzy, c-format
+msgid "Illegal register `%s' in register list"
+msgstr "Kayan nokta yazmacı yazmaç listesinde"
+
+#: config/tc-crx.c:1878
+#, c-format
+msgid "Maximum %d bits may be set in `mask16' operand"
+msgstr ""
+
+#: config/tc-crx.c:1887
+#, c-format
+msgid "rest of line ignored; first ignored character is `%c'"
+msgstr "satırın geri kalanı yoksayıldı; ilk yoksayılan karakter `%c'."
+
+#: config/tc-crx.c:1895
+#, c-format
+msgid "Illegal `mask16' operand, operation is undefined - `%s'"
+msgstr ""
+
+#. HI can't be specified without LO (and vise-versa).
+#: config/tc-crx.c:1901
+msgid "HI/LO registers should be specified together"
+msgstr ""
+
+#: config/tc-crx.c:1907
+msgid "HI/LO registers should be specified without additional registers"
+msgstr ""
+
+#. Give an error if a frag containing code is not aligned to a 2-byte
+#. boundary.
+#: config/tc-crx.c:1992 config/tc-crx.h:78
+#, fuzzy
+msgid "instruction address is not a multiple of 2"
+msgstr "4'ün katı olan bir adrese dallanmak gerekli"
+
 #: config/tc-d10v.c:252
+#, c-format
 msgid ""
 "D10V options:\n"
 "-O                      Optimize.  Will do some operations in parallel.\n"
@@ -3117,9 +3651,9 @@ msgstr ""
 "--no-gstabs-packing     --gstabs belirtilmiÅŸse yanyana olan iÅŸlemleri\n"
 "                        birleÅŸtirmez.\n"
 
-#: config/tc-d10v.c:543 config/tc-d30v.c:549 config/tc-mn10200.c:937
-#: config/tc-mn10300.c:1812 config/tc-ppc.c:2332 config/tc-s390.c:1234
-#: config/tc-tic80.c:275 config/tc-v850.c:2022
+#: config/tc-d10v.c:543 config/tc-d30v.c:550 config/tc-mn10200.c:937
+#: config/tc-mn10300.c:1817 config/tc-ppc.c:2365 config/tc-s390.c:1216
+#: config/tc-tic80.c:276 config/tc-v850.c:2031
 msgid "illegal operand"
 msgstr "geçersiz işlenen"
 
@@ -3148,20 +3682,20 @@ msgstr "Uzun iÅŸlemler birleÅŸtirilemez."
 msgid "One of these instructions may not be executed in parallel."
 msgstr "Bu iÅŸlemlerin biri paralel iÅŸlenemez."
 
-#: config/tc-d10v.c:832 config/tc-d30v.c:876
+#: config/tc-d10v.c:832 config/tc-d30v.c:877
 msgid "Two IU instructions may not be executed in parallel"
 msgstr "Ä°ki IU iÅŸlemi paralel iÅŸlenemez."
 
 #: config/tc-d10v.c:834 config/tc-d10v.c:842 config/tc-d10v.c:856
-#: config/tc-d10v.c:871 config/tc-d30v.c:877 config/tc-d30v.c:886
+#: config/tc-d10v.c:871 config/tc-d30v.c:878 config/tc-d30v.c:887
 msgid "Swapping instruction order"
 msgstr "İşlem sırası takas ediliyor."
 
-#: config/tc-d10v.c:840 config/tc-d30v.c:883
+#: config/tc-d10v.c:840 config/tc-d30v.c:884
 msgid "Two MU instructions may not be executed in parallel"
 msgstr "Ä°ki MU iÅŸlemi paralel iÅŸlenemez."
 
-#: config/tc-d10v.c:860 config/tc-d30v.c:903
+#: config/tc-d10v.c:860 config/tc-d30v.c:904
 msgid "IU instruction may not be in the left container"
 msgstr "IU işlemi sol taşıyıcıda tutulamaz."
 
@@ -3171,11 +3705,11 @@ msgstr ""
 "R taşıyıcısındaki işlem, L taşıyıcısındaki flow control işlemi tarafından\n"
 "etkisizleÅŸtirildi."
 
-#: config/tc-d10v.c:875 config/tc-d30v.c:914
+#: config/tc-d10v.c:875 config/tc-d30v.c:915
 msgid "MU instruction may not be in the right container"
 msgstr "MU işlemi sağ taşıyıcıda olamaz."
 
-#: config/tc-d10v.c:881 config/tc-d30v.c:926
+#: config/tc-d10v.c:881 config/tc-d30v.c:927
 msgid "unknown execution type passed to write_2_short()"
 msgstr "write_2_short()'a bilinmeyen işlem türü geçirildi."
 
@@ -3206,51 +3740,52 @@ msgstr "kaynak çelişkisi (C bayrağı)"
 msgid "resource conflict (F flag)"
 msgstr "kaynak çelişkisi (F bayrağı)"
 
-#: config/tc-d10v.c:1276 config/tc-d10v.c:1298 config/tc-d30v.c:1410
+#: config/tc-d10v.c:1276 config/tc-d10v.c:1298 config/tc-d30v.c:1408
 msgid "Unable to mix instructions as specified"
 msgstr "işlemler belirtilen şekilde harmanlanamadı"
 
-#: config/tc-d10v.c:1345 config/tc-d30v.c:1547
+#: config/tc-d10v.c:1343 config/tc-d30v.c:1538
 #, c-format
 msgid "unknown opcode: %s"
 msgstr "bilinmeyen opkod: %s"
 
-#: config/tc-d10v.c:1428 config/tc-d10v.c:1603 config/tc-tic80.c:532
+#: config/tc-d10v.c:1426 config/tc-d10v.c:1601
 msgid "bad opcode or operands"
 msgstr "hatalı opkod veya işlenenler"
 
-#: config/tc-d10v.c:1503 config/tc-m68k.c:4305
+#: config/tc-d10v.c:1501 config/tc-m68k.c:4679
 msgid "value out of range"
 msgstr "değer aralık dışı"
 
-#: config/tc-d10v.c:1579
+#: config/tc-d10v.c:1577
 msgid "illegal operand - register name found where none expected"
 msgstr "hatalı işlenen -- beklenmeyen yerde yazmaç adı"
 
-#: config/tc-d10v.c:1614 config/tc-tic80.c:543
+#: config/tc-d10v.c:1612
 msgid "Register number must be EVEN"
 msgstr "Yazmaç numarası ÇİFT sayı olmalı"
 
-#: config/tc-d10v.c:1617
+#: config/tc-d10v.c:1615
 msgid "Unsupported use of sp"
 msgstr "sp'nin desteklenmeyen kullanımı"
 
-#: config/tc-d10v.c:1636
+#: config/tc-d10v.c:1634
 #, c-format
 msgid "cr%ld is a reserved control register"
 msgstr "cr%ld rezerveli bir kontrol yazmacı"
 
-#: config/tc-d10v.c:1773
+#: config/tc-d10v.c:1771
 #, c-format
 msgid "line %d: rep or repi must include at least 4 instructions"
 msgstr "satır %d: rep veya repi en az 4 işlem içermeli"
 
-#: config/tc-d30v.c:192
+#: config/tc-d30v.c:193
 #, c-format
 msgid "Register name %s conflicts with symbol of the same name"
 msgstr "Yazmaç ismi %s, aynı isimde sembolle çakışıyor"
 
-#: config/tc-d30v.c:287
+#: config/tc-d30v.c:288
+#, c-format
 msgid ""
 "\n"
 "D30V options:\n"
@@ -3270,464 +3805,509 @@ msgstr ""
 "                        uyarır.\n"
 "-C                      -c'nin tersi. -c, öntanımlıdır.\n"
 
-#: config/tc-d30v.c:461
+#: config/tc-d30v.c:462
 msgid "unexpected 12-bit reloc type"
 msgstr "beklenmeyen 12bitlik yerdeğişim türü"
 
-#: config/tc-d30v.c:468
+#: config/tc-d30v.c:469
 msgid "unexpected 18-bit reloc type"
 msgstr "beklenmeyen 18bitlik yerdeğişim türü"
 
-#: config/tc-d30v.c:719
+#: config/tc-d30v.c:720
 #, c-format
 msgid "%s NOP inserted"
 msgstr "%s NOP eklendi"
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:721
 msgid "sequential"
 msgstr "ardışık sıralı"
 
-#: config/tc-d30v.c:720
+#: config/tc-d30v.c:721
 msgid "parallel"
 msgstr "paralel"
 
-#: config/tc-d30v.c:872
+#: config/tc-d30v.c:873
 msgid "Instructions may not be executed in parallel"
 msgstr "Ä°ÅŸlemler paralel iÅŸlenemez"
 
-#: config/tc-d30v.c:885
+#: config/tc-d30v.c:886
 #, c-format
 msgid "Executing %s in IU may not work"
 msgstr "%s'i IU'da işlemek çalışmayabilir"
 
-#: config/tc-d30v.c:892
+#: config/tc-d30v.c:893
 #, c-format
 msgid "Executing %s in IU may not work in parallel execution"
 msgstr "%s'i IU'da işlemek paralel işlemede çalışmayabilir"
 
-#: config/tc-d30v.c:905
+#: config/tc-d30v.c:906
 #, c-format
 msgid "special left instruction `%s' kills instruction `%s' in right container"
 msgstr "`%s' özel sol işlemi, sağ taşıyıcıdaki `%s' işlemini etkisizleştiriyor."
 
-#: config/tc-d30v.c:916
+#: config/tc-d30v.c:917
 #, c-format
 msgid "Executing %s in reverse serial with %s may not work"
 msgstr "%s'yi %s ile ters ardışık sırada çalıştırmak başarılı olmayabilir"
 
-#: config/tc-d30v.c:919
+#: config/tc-d30v.c:920
 #, c-format
 msgid "Executing %s in IU in reverse serial may not work"
 msgstr "%s'i IU'da ters ardışık sırada çalıştırmak başarılı olmayabilir"
 
-#: config/tc-d30v.c:1289 config/tc-d30v.c:1306
+#: config/tc-d30v.c:1287 config/tc-d30v.c:1304
 msgid "Cannot assemble instruction"
 msgstr "İşlem çevrimlenemedi"
 
-#: config/tc-d30v.c:1291
+#: config/tc-d30v.c:1289
 msgid "First opcode is long.  Unable to mix instructions as specified."
 msgstr "İlk opkod uzun. İşlemler belirtildiği şekilde harmanlanamadı."
 
-#: config/tc-d30v.c:1360
+#: config/tc-d30v.c:1358
 msgid "word of NOPs added between word multiply and load"
 msgstr "Word çarpma ve yükleme arasına NOP word'u eklendi"
 
-#: config/tc-d30v.c:1362
+#: config/tc-d30v.c:1360
 msgid "word of NOPs added between word multiply and 16-bit multiply"
 msgstr "Word çarpma ve 16bit çarpma arasına word NOP'u eklendi"
 
-#: config/tc-d30v.c:1394
+#: config/tc-d30v.c:1392
 msgid "Instruction uses long version, so it cannot be mixed as specified"
 msgstr "İşlem uzun biçemi kullanıyor, belirtildiği şekilde harmanlanamaz"
 
-#: config/tc-d30v.c:1477 config/tc-d30v.c:1515
+#: config/tc-d30v.c:1475 config/tc-d30v.c:1510
 #, c-format
 msgid "unknown condition code: %s"
 msgstr "bilinmeyen koÅŸul: %s"
 
-#: config/tc-d30v.c:1508
+#: config/tc-d30v.c:1503
 #, c-format
 msgid "cmpu doesn't support condition code %s"
 msgstr "cmpu %s koÅŸulunu desteklemiyor"
 
-#: config/tc-d30v.c:1558
+#: config/tc-d30v.c:1549
 #, c-format
 msgid "operands for opcode `%s' do not match any valid format"
 msgstr "`%s' opkodunun işlenenleri geçerli bir biçemle eşleşmiyor"
 
-#: config/tc-d30v.c:1776
+#: config/tc-d30v.c:1764
 msgid "Odd numbered register used as target of multi-register instruction"
 msgstr "Tek numaralı yazmaç, çoklu yazmaç işleminin hedefi olarak kullanıldı"
 
-#: config/tc-d30v.c:1862
+#: config/tc-d30v.c:1847
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a byte"
 msgstr "satır %d: '%s' sembolünün adresi bir bayta sığdırılamadı"
 
-#: config/tc-d30v.c:1865
+#: config/tc-d30v.c:1850
 #, c-format
 msgid "line %d: unable to place value %lx into a byte"
 msgstr "satır %d: %lx değeri bir bayta sığdırılamadı."
 
-#: config/tc-d30v.c:1873
+#: config/tc-d30v.c:1858
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a short"
 msgstr "satır %d: '%s' sembolünün adresi bir short'a sığdırılamadı"
 
-#: config/tc-d30v.c:1876
+#: config/tc-d30v.c:1861
 #, c-format
 msgid "line %d: unable to place value %lx into a short"
 msgstr "satır %d: %lx değeri bir short'a sığdırılamadı"
 
-#: config/tc-d30v.c:1884
+#: config/tc-d30v.c:1869
 #, c-format
 msgid "line %d: unable to place address of symbol '%s' into a quad"
 msgstr "satır %d: '%s' sembolünün değeri bir quad'a sığdırılamadı"
 
-#: config/tc-d30v.c:2053
+#: config/tc-d30v.c:2038
 #, c-format
 msgid "value too large to fit in %d bits"
 msgstr "değer, %d bite sığdırmak için fazla büyük"
 
-#: config/tc-d30v.c:2196
+#: config/tc-d30v.c:2179
 #, c-format
 msgid "Alignment too large: %d assumed"
 msgstr "Hizalama fazla büyük: %d varsayıldı"
 
-#: config/tc-dlx.c:283
+#: config/tc-dlx.c:245
 msgid "missing .proc"
 msgstr ".proc eksik"
 
-#: config/tc-dlx.c:300
+#: config/tc-dlx.c:262
 msgid ".endfunc missing for previous .proc"
 msgstr "önceki .proc için eksik .endfunc"
 
-#: config/tc-dlx.c:498
+#: config/tc-dlx.c:472
 #, c-format
 msgid "Expression Error for operand modifier %%hi/%%lo\n"
 msgstr "%%hi/%%lo işlenen değiştiricisi için ifade hatası\n"
 
-#: config/tc-dlx.c:552
+#: config/tc-dlx.c:526
 #, c-format
 msgid "Bad operand for a load instruction: <%s>"
 msgstr "Yükleme işlemi için hatalı işlenen: <%s>"
 
-#: config/tc-dlx.c:667
+#: config/tc-dlx.c:641
 #, c-format
 msgid "Bad operand for a store instruction: <%s>"
 msgstr "Saklama işlemi için hatalı işlenen: <%s>"
 
-#: config/tc-dlx.c:865
+#: config/tc-dlx.c:839
 msgid "Can not set dlx_skip_hi16_flag"
 msgstr "dlx_skip_hi16_flag bayrağı işaretlenemedi"
 
-#: config/tc-dlx.c:879
+#: config/tc-dlx.c:853
 #, c-format
 msgid "Missing arguments for opcode <%s>."
 msgstr "`%s' opkodu için eksik argümanlar"
 
-#: config/tc-dlx.c:950
+#: config/tc-dlx.c:924
 #, c-format
 msgid "Both the_insn.HI and the_insn.LO are set : %s"
 msgstr "Hem the_insn.HI hem de the_insn.LO iÅŸaretli : %s"
 
-#: config/tc-dlx.c:1022
+#: config/tc-dlx.c:994
 msgid "failed regnum sanity check."
 msgstr "başarısız regnum kontrolü."
 
-#: config/tc-dlx.c:1035
+#: config/tc-dlx.c:1007
 msgid "failed general register sanity check."
 msgstr "genel yazmaç hata kontrolü başarısız."
 
-#: config/tc-dlx.c:1324
+#: config/tc-dlx.c:1292
 msgid "Invalid expression after # number\n"
 msgstr "# sayısından sonra geçersiz ifade\n"
 
 #: config/tc-fr30.c:85
+#, c-format
 msgid " FR30 specific command line options:\n"
 msgstr " FR30'a özgü komut satırı seçenekleri:\n"
 
-#: config/tc-fr30.c:139 config/tc-openrisc.c:152
+#: config/tc-fr30.c:139
 #, c-format
 msgid "Instruction %s not allowed in a delay slot."
 msgstr "%s işlemi gecikme yuvasında olamaz."
 
-#: config/tc-fr30.c:383 config/tc-m32r.c:1576
-msgid "Addend to unresolved symbol not on word boundary."
-msgstr "Word sınırında olmayan çözümlenmemiş sembole addend eklendi."
-
-#: config/tc-fr30.c:524 config/tc-frv.c:1289 config/tc-i960.c:798
-#: config/tc-ip2k.c:353 config/tc-m32r.c:1884 config/tc-openrisc.c:452
-#: config/tc-xstormy16.c:636
+#: config/tc-fr30.c:378 config/tc-frv.c:1600 config/tc-i960.c:798
+#: config/tc-ip2k.c:350 config/tc-m32r.c:2205 config/tc-openrisc.c:401
+#: config/tc-xstormy16.c:654
 msgid "Bad call to md_atof()"
 msgstr "md_atof()'a hatalı çağrı"
 
-#: config/tc-frv.c:413
+#: config/tc-frv.c:461
+#, c-format
 msgid "FRV specific command line options:\n"
 msgstr "FRV'ye özgü komut satırı seçenekleri:\n"
 
-#: config/tc-frv.c:414
+#: config/tc-frv.c:462
+#, c-format
 msgid "-G n         Data >= n bytes is in small data area\n"
 msgstr "-G n         Veri >= n bayt, küçük veri bölgesinde tutulur\n"
 
-#: config/tc-frv.c:415
+#: config/tc-frv.c:463
+#, c-format
 msgid "-mgpr-32     Note 32 gprs are used\n"
 msgstr "-mgpr-32     32 gprs kullanılır\n"
 
-#: config/tc-frv.c:416
+#: config/tc-frv.c:464
+#, c-format
 msgid "-mgpr-64     Note 64 gprs are used\n"
 msgstr "-mgpr-64     64 gprs kullanılır\n"
 
-#: config/tc-frv.c:417
+#: config/tc-frv.c:465
+#, c-format
 msgid "-mfpr-32     Note 32 fprs are used\n"
 msgstr "-mfpr-32     32 fprs kullanılır\n"
 
-#: config/tc-frv.c:418
+#: config/tc-frv.c:466
+#, c-format
 msgid "-mfpr-64     Note 64 fprs are used\n"
 msgstr "-mfpr-64     64 fprs kullanılır\n"
 
-#: config/tc-frv.c:419
+#: config/tc-frv.c:467
+#, c-format
 msgid "-msoft-float Note software fp is used\n"
 msgstr "-msoft-float yazılım fp'si kullanılır\n"
 
-#: config/tc-frv.c:420
+#: config/tc-frv.c:468
+#, c-format
 msgid "-mdword      Note stack is aligned to a 8 byte boundary\n"
 msgstr "-mdword      Yığıt 8bayt sınırına hizalanır\n"
 
-#: config/tc-frv.c:421
+#: config/tc-frv.c:469
+#, c-format
 msgid "-mno-dword   Note stack is aligned to a 4 byte boundary\n"
 msgstr "-mno-dword   Yığıt 4 bayt sınırına hizalanır\n"
 
-#: config/tc-frv.c:422
+#: config/tc-frv.c:470
+#, c-format
 msgid "-mdouble     Note fp double insns are used\n"
 msgstr "-mdouble     fp double işlemleri kullanılır\n"
 
-#: config/tc-frv.c:423
+#: config/tc-frv.c:471
+#, c-format
 msgid "-mmedia      Note media insns are used\n"
 msgstr "-mmedia      media işlemleri kullanılır\n"
 
-#: config/tc-frv.c:424
+#: config/tc-frv.c:472
+#, c-format
 msgid "-mmuladd     Note multiply add/subtract insns are used\n"
 msgstr "-mmuladd     çarpma toplama/çıkarma işlemleri kullanılır\n"
 
-#: config/tc-frv.c:425
+#: config/tc-frv.c:473
+#, c-format
 msgid "-mpack       Note instructions are packed\n"
 msgstr "-mpack       iÅŸlemler paketlenir\n"
 
-#: config/tc-frv.c:426
+#: config/tc-frv.c:474
+#, c-format
 msgid "-mno-pack    Do not allow instructions to be packed\n"
 msgstr "-mno-pack    Ä°ÅŸlemler paketlenmez\n"
 
-#: config/tc-frv.c:427
+#: config/tc-frv.c:475
+#, c-format
 msgid "-mpic        Note small position independent code\n"
 msgstr "-mpic        yerden bağımsız küçük kod bulunur\n"
 
-#: config/tc-frv.c:428
+#: config/tc-frv.c:476
+#, c-format
 msgid "-mPIC        Note large position independent code\n"
 msgstr "-mPIC        yerden bağımsız büyük kod bulunur\n"
 
-#: config/tc-frv.c:429
+#: config/tc-frv.c:477
+#, c-format
 msgid "-mlibrary-pic Compile library for large position indepedent code\n"
 msgstr "-mlibrary-pic Kitaplık, yerden bağımsız büyük kod için derlenir\n"
 
-#: config/tc-frv.c:430
-msgid "-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n"
+#: config/tc-frv.c:478
+#, c-format
+msgid "-mfdpic      Assemble for the FDPIC ABI\n"
+msgstr ""
+
+#: config/tc-frv.c:479
+#, c-format
+msgid "-mnopic      Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"
+msgstr ""
+
+#: config/tc-frv.c:480
+#, fuzzy, c-format
+msgid "-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"
 msgstr "-mcpu={fr500|fr400|fr300|frv|simple|tomcat}\n"
 
-#: config/tc-frv.c:431
+#: config/tc-frv.c:481
+#, c-format
 msgid "             Record the cpu type\n"
 msgstr "             cpu türünü yazdırır\n"
 
-#: config/tc-frv.c:432
+#: config/tc-frv.c:482
+#, c-format
 msgid "-mtomcat-stats Print out stats for tomcat workarounds\n"
 msgstr "-mtomcat-stats Tomcat kestirmeleri için istatistik yazdırır\n"
 
-#: config/tc-frv.c:433
+#: config/tc-frv.c:483
+#, c-format
 msgid "-mtomcat-debug Debug tomcat workarounds\n"
 msgstr "-mtomcat-debug Tomcat kestirmelerinde hata ayıklar\n"
 
-#: config/tc-frv.c:1012
+#: config/tc-frv.c:1187
 msgid "VLIW packing used for -mno-pack"
 msgstr " -mno-pack için VLIW paketlemesi kullanır"
 
-#: config/tc-frv.c:1025
+#: config/tc-frv.c:1197
+#, fuzzy
+msgid "Instruction not supported by this architecture"
+msgstr "-R seçeneği bu hedef için desteklenmiyor."
+
+#: config/tc-frv.c:1207
 msgid "VLIW packing constraint violation"
 msgstr "VLIW paketleme kısıtlama ihlali"
 
-#: config/tc-frv.c:1540
+#: config/tc-frv.c:1874
 #, c-format
 msgid "Relocation %s is not safe for %s"
 msgstr "%s yerdeğişimi %s için tehlikeli"
 
-#: config/tc-h8300.c:84 config/tc-h8300.c:96 config/tc-h8300.c:109
-#: config/tc-h8300.c:122 config/tc-h8300.c:135 config/tc-h8300.c:149
-#: config/tc-h8300.c:222 config/tc-hppa.c:1423 config/tc-hppa.c:6909
-#: config/tc-hppa.c:6915 config/tc-hppa.c:6921 config/tc-hppa.c:6927
-#: config/tc-mn10300.c:1218 config/tc-mn10300.c:1223 config/tc-mn10300.c:2722
+#: config/tc-h8300.c:82 config/tc-h8300.c:93 config/tc-h8300.c:105
+#: config/tc-h8300.c:117 config/tc-h8300.c:129 config/tc-h8300.c:142
+#: config/tc-h8300.c:213 config/tc-hppa.c:1440 config/tc-hppa.c:6925
+#: config/tc-hppa.c:6931 config/tc-hppa.c:6937 config/tc-hppa.c:6943
+#: config/tc-mn10300.c:1223 config/tc-mn10300.c:1228 config/tc-mn10300.c:2726
 msgid "could not set architecture and machine"
 msgstr "Yapı ve makina atanamadı"
 
-#: config/tc-h8300.c:436 config/tc-h8300.c:444
+#: config/tc-h8300.c:416 config/tc-h8300.c:424
 msgid "Reg not valid for H8/300"
 msgstr "Yazmaç, H8/300 için geçersiz"
 
-#: config/tc-h8300.c:529
+#: config/tc-h8300.c:505
 msgid "invalid operand size requested"
 msgstr "geçersiz işlenen boyu istendi"
 
-#: config/tc-h8300.c:626 config/tc-h8300.c:629
+#: config/tc-h8300.c:604
 msgid "Invalid register list for ldm/stm\n"
 msgstr "ldm/stm için geçersiz yazmaç listesi\n"
 
-#: config/tc-h8300.c:632
-msgid "Invalid register list for ldm/stm)\n"
-msgstr "ldm/stm için geçersiz yazmaç listesi)\n"
-
-#: config/tc-h8300.c:658 config/tc-h8300.c:663 config/tc-h8300.c:670
+#: config/tc-h8300.c:630 config/tc-h8300.c:635 config/tc-h8300.c:642
 msgid "mismatch between register and suffix"
 msgstr "yazmaç ve sonek arasında uyumsuzluk"
 
-#: config/tc-h8300.c:697
+#: config/tc-h8300.c:669
 msgid "address too high for vector table jmp/jsr"
 msgstr "vektör tablosu jmp/jsr için adres fazla yüksek"
 
-#: config/tc-h8300.c:722 config/tc-h8300.c:832 config/tc-h8300.c:840
+#: config/tc-h8300.c:696 config/tc-h8300.c:808 config/tc-h8300.c:818
 msgid "Wrong size pointer register for architecture."
 msgstr "Yapı için hatalı boyda imleyici."
 
-#: config/tc-h8300.c:781 config/tc-h8300.c:789 config/tc-h8300.c:818
+#: config/tc-h8300.c:755 config/tc-h8300.c:763 config/tc-h8300.c:792
 msgid "expected @(exp, reg16)"
 msgstr "@(exp, reg16) beklendi"
 
-#: config/tc-h8300.c:807
+#: config/tc-h8300.c:781
 msgid "expected .L, .W or .B for register in indexed addressing mode"
 msgstr "indeksli adresleme kipindeki yazmaç için .L, .W veya .B beklendi"
 
-#: config/tc-h8300.c:1000
+#: config/tc-h8300.c:975
 msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\""
 msgstr "mova için geçerli adresleme kipi beklendi: \"@(disp, ea.sz),ERn\""
 
-#: config/tc-h8300.c:1018 config/tc-h8300.c:1027
+#: config/tc-h8300.c:993 config/tc-h8300.c:1002
 msgid "expected register"
 msgstr "yazmaç beklendi"
 
-#: config/tc-h8300.c:1043
+#: config/tc-h8300.c:1018
 msgid "expected closing paren"
 msgstr "kapanış parantezi beklendi"
 
-#: config/tc-h8300.c:1104
+#: config/tc-h8300.c:1077
 #, c-format
 msgid "can't use high part of register in operand %d"
 msgstr "%d işleneninde yazmacın yüksek tarafı kullanılamaz"
 
-#: config/tc-h8300.c:1268
+#: config/tc-h8300.c:1234
 #, c-format
 msgid "Opcode `%s' with these operand types not available in %s mode"
 msgstr "%2$s kipinde bu tür işlenenlerle çalışan `%1$s' opkodu yok"
 
-#: config/tc-h8300.c:1277
+#: config/tc-h8300.c:1243
 msgid "mismatch between opcode size and operand size"
 msgstr "opkod boyu ve işlenen boyu arasında uyumsuzluk"
 
-#: config/tc-h8300.c:1316
+#: config/tc-h8300.c:1279
 #, c-format
 msgid "operand %s0x%lx out of range."
 msgstr "%s0x%lx işleneni kapsam dışı."
 
-#: config/tc-h8300.c:1415
+#: config/tc-h8300.c:1375
 msgid "Can't work out size of operand.\n"
 msgstr "İşlenenin boyu hesaplanamadı.\n"
 
-#: config/tc-h8300.c:1466
+#: config/tc-h8300.c:1424
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300 mode"
 msgstr "H8/300 kipinde bu tür işlenenlerle çalışan `%s' opkodu yok"
 
-#: config/tc-h8300.c:1471
+#: config/tc-h8300.c:1429
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300H mode"
 msgstr "H8/300H kipinde bu tür işlenenlerle çalışan `%s' opkodu yok"
 
-#: config/tc-h8300.c:1477
+#: config/tc-h8300.c:1435
 #, c-format
 msgid "Opcode `%s' with these operand types not available in H8/300S mode"
 msgstr "H8/300S kipinde bu tür işlenenlerle çalışan `%s' opkodu yok"
 
-#: config/tc-h8300.c:1538 config/tc-h8300.c:1558
+#: config/tc-h8300.c:1496 config/tc-h8300.c:1516
 msgid "Need #1 or #2 here"
 msgstr "Burada #1 veya #2 gerekli"
 
-#: config/tc-h8300.c:1553
+#: config/tc-h8300.c:1511
 msgid "#4 not valid on H8/300."
 msgstr "#4, H8/300 için geçersiz."
 
-#: config/tc-h8300.c:1645 config/tc-h8300.c:1727
+#: config/tc-h8300.c:1617 config/tc-h8300.c:1699
 #, c-format
 msgid "branch operand has odd offset (%lx)\n"
 msgstr "dal işleneni tek sayılı göreli konuma sahip (%lx)\n"
 
-#: config/tc-h8300.c:1766
+#: config/tc-h8300.c:1737
 msgid "destination operand must be 16 bit register"
 msgstr "hedef işlenen 16bitlik yazmaç olmalı"
 
-#: config/tc-h8300.c:1775
+#: config/tc-h8300.c:1746
 msgid "source operand must be 8 bit register"
 msgstr "kaynak işleneni 8bitlik yazmaç olmalı"
 
-#: config/tc-h8300.c:1783
+#: config/tc-h8300.c:1754
 msgid "destination operand must be 16bit absolute address"
 msgstr "hedef işleneni 16bitlik yere bağımlı adres olmalı"
 
-#: config/tc-h8300.c:1790
+#: config/tc-h8300.c:1761
 msgid "destination operand must be 8 bit register"
 msgstr "hedef işleneni 8bitlik yazmaç olmalı"
 
-#: config/tc-h8300.c:1798
+#: config/tc-h8300.c:1769
 msgid "source operand must be 16bit absolute address"
 msgstr "kaynak işleneni 16bitlik yere bağımlı adres olmalı"
 
 #. This seems more sane than saying "too many operands".  We'll
 #. get here only if the trailing trash starts with a comma.
-#: config/tc-h8300.c:1806 config/tc-mmix.c:454 config/tc-mmix.c:466
-#: config/tc-mmix.c:2502 config/tc-mmix.c:2526 config/tc-mmix.c:2802
-#: config/tc-or32.c:640 config/tc-or32.c:854
+#. Types or values of args don't match.
+#: config/tc-h8300.c:1777 config/tc-mmix.c:486 config/tc-mmix.c:498
+#: config/tc-mmix.c:2564 config/tc-mmix.c:2588 config/tc-mmix.c:2865
+#: config/tc-or32.c:636 config/tc-or32.c:846
 msgid "invalid operands"
 msgstr "geçersiz işlenen"
 
-#: config/tc-h8300.c:1839
+#: config/tc-h8300.c:1808
 msgid "operand/size mis-match"
 msgstr "işlenenler/boy uyuşmazlığı"
 
-#: config/tc-h8300.c:1926 config/tc-h8500.c:1112 config/tc-mips.c:9301
-#: config/tc-sh.c:2363 config/tc-sh64.c:2837 config/tc-w65.c:691
-#: config/tc-z8k.c:1248
+#: config/tc-h8300.c:1904 config/tc-h8500.c:1112 config/tc-mips.c:9141
+#: config/tc-sh64.c:2795 config/tc-sh.c:2806 config/tc-w65.c:688
+#: config/tc-z8k.c:1210
 msgid "unknown opcode"
 msgstr "bilinmeyen opkod"
 
-#: config/tc-h8300.c:2031 config/tc-h8500.c:1139 config/tc-sh.c:2483
-#: config/tc-z8k.c:1304
+#: config/tc-h8300.c:1937
+#, fuzzy
+msgid "invalid operand in ldm"
+msgstr "geçersiz işlenen"
+
+#: config/tc-h8300.c:1946
+#, fuzzy
+msgid "invalid operand in stm"
+msgstr "geçersiz işlenen"
+
+#: config/tc-h8300.c:2029 config/tc-h8500.c:1139 config/tc-sh.c:2931
+#: config/tc-z8k.c:1266
+#, c-format
 msgid "call to tc_crawl_symbol_chain \n"
 msgstr "tc_crawl_symbol_chain'e çağrı\n"
 
-#: config/tc-h8300.c:2047 config/tc-h8500.c:1153 config/tc-sh.c:2490
-#: config/tc-z8k.c:1320
+#: config/tc-h8300.c:2043 config/tc-h8500.c:1153 config/tc-sh.c:2937
+#: config/tc-z8k.c:1280
+#, c-format
 msgid "call to tc_headers_hook \n"
 msgstr "tc_headers_hook'e çağrı \n"
 
-#: config/tc-h8300.c:2140
+#: config/tc-h8300.c:2130
+#, c-format
 msgid "call to tc_aout_fix_to_chars \n"
 msgstr "tc_aout_fix_to_chars'e çağrı \n"
 
-#: config/tc-h8300.c:2154
+#: config/tc-h8300.c:2144
+#, c-format
 msgid "call to md_convert_frag \n"
 msgstr "md_convert_frag'e çağrı \n"
 
-#: config/tc-h8300.c:2216
+#: config/tc-h8300.c:2198
+#, c-format
 msgid "call tomd_estimate_size_before_relax \n"
 msgstr "md_estimate_size_before_relax'e çağrı \n"
 
-#: config/tc-h8300.c:2337 config/tc-mcore.c:2355 config/tc-pj.c:581
-#: config/tc-sh.c:3958
+#: config/tc-h8300.c:2309 config/tc-mcore.c:2356 config/tc-pj.c:580
+#: config/tc-sh.c:4455
 #, c-format
 msgid "Cannot represent relocation type %s"
 msgstr "Yerdeğişim türü %s gösterilemedi"
@@ -3760,7 +4340,7 @@ msgstr "@Rn+ için word yazmacı gerekli"
 msgid "@Rn needs word register"
 msgstr "@Rn için word yazmacı gerekli"
 
-#: config/tc-h8500.c:838 config/tc-sh.c:1827
+#: config/tc-h8500.c:838 config/tc-sh.c:2083
 #, c-format
 msgid "unhandled %d\n"
 msgstr "%d desteklenmiyor\n"
@@ -3770,789 +4350,793 @@ msgstr "%d desteklenmiyor\n"
 msgid "operand must be absolute in range %d..%d"
 msgstr "%d..%d aralığında işlenen kesin olmalı"
 
-#: config/tc-h8500.c:963 config/tc-sh.c:2036
+#: config/tc-h8500.c:963 config/tc-sh.c:2353
 #, c-format
 msgid "failed for %d\n"
 msgstr "%d için başarısız\n"
 
-#: config/tc-h8500.c:1128 config/tc-sh.c:2138 config/tc-sh.c:2412
-#: config/tc-w65.c:710
+#: config/tc-h8500.c:1128 config/tc-sh.c:2466 config/tc-sh.c:2862
+#: config/tc-w65.c:707
 msgid "invalid operands for opcode"
 msgstr "opkod için geçersiz işlenenler"
 
-#. Simple range checking for FIELD againt HIGH and LOW bounds.
+#. Simple range checking for FIELD against HIGH and LOW bounds.
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1156 config/tc-hppa.c:1170
+#. Variant of CHECK_FIELD for use in md_apply_fix3 and other places where
+#. the current file and line number are not valid.
+#: config/tc-hppa.c:1171 config/tc-hppa.c:1185
 #, c-format
 msgid "Field out of range [%d..%d] (%d)."
 msgstr "Alan kapsam dışı [%d..%d] (%d)."
 
-#. Simple alignment checking for FIELD againt ALIGN (a power of two).
+#. Simple alignment checking for FIELD against ALIGN (a power of two).
 #. IGNORE is used to suppress the error message.
-#: config/tc-hppa.c:1184
+#: config/tc-hppa.c:1199
 #, c-format
 msgid "Field not properly aligned [%d] (%d)."
 msgstr "Alan doğru hizalanmamış [%d] (%d)."
 
-#: config/tc-hppa.c:1213
+#: config/tc-hppa.c:1228
 msgid "Missing .exit\n"
 msgstr ".exit eksik\n"
 
-#: config/tc-hppa.c:1216
+#: config/tc-hppa.c:1231
 msgid "Missing .procend\n"
 msgstr ".procend eksik\n"
 
-#: config/tc-hppa.c:1396
+#: config/tc-hppa.c:1413
 #, c-format
 msgid "Invalid field selector.  Assuming F%%."
 msgstr "Geçersiz alan seçicisi. F%% varsayıldı."
 
-#: config/tc-hppa.c:1429
+#: config/tc-hppa.c:1446
 msgid "-R option not supported on this target."
 msgstr "-R seçeneği bu hedef için desteklenmiyor."
 
-#: config/tc-hppa.c:1445 config/tc-sparc.c:809 config/tc-sparc.c:845
+#: config/tc-hppa.c:1462 config/tc-sparc.c:814 config/tc-sparc.c:850
 #, c-format
 msgid "Internal error: can't hash `%s': %s\n"
 msgstr "İç hata: `%s' hash'lenemedi: %s\n"
 
-#: config/tc-hppa.c:1453 config/tc-i860.c:201
+#: config/tc-hppa.c:1470 config/tc-i860.c:238
 #, c-format
 msgid "internal error: losing opcode: `%s' \"%s\"\n"
 msgstr "İç hata: opkod kaybedildi: `%s' \"%s\"\n"
 
-#: config/tc-hppa.c:1524 config/tc-hppa.c:7048 config/tc-hppa.c:7105
+#: config/tc-hppa.c:1541 config/tc-hppa.c:7064 config/tc-hppa.c:7121
 msgid "Missing function name for .PROC (corrupted label chain)"
 msgstr ".PROC için eksik işlev adı (bozuk etiket zinciri)"
 
-#: config/tc-hppa.c:1527 config/tc-hppa.c:7108
+#: config/tc-hppa.c:1544 config/tc-hppa.c:7124
 msgid "Missing function name for .PROC"
 msgstr ".PROC için eksik işlev adı"
 
-#: config/tc-hppa.c:1634 config/tc-hppa.c:4905
+#: config/tc-hppa.c:1651 config/tc-hppa.c:4920
 msgid "could not update architecture and machine"
 msgstr "Yapı ve makina güncellenemedi"
 
-#: config/tc-hppa.c:1842
+#: config/tc-hppa.c:1859
 msgid "Invalid Indexed Load Completer."
 msgstr "Geçersiz İndeksli Yükleme Tamamlayıcısı."
 
-#: config/tc-hppa.c:1847
+#: config/tc-hppa.c:1864
 msgid "Invalid Indexed Load Completer Syntax."
 msgstr "Geçersiz İndeksli Yükleme Tamamlayıcısı Sözdizimi."
 
-#: config/tc-hppa.c:1884
+#: config/tc-hppa.c:1901
 msgid "Invalid Short Load/Store Completer."
 msgstr "Geçersiz Short Yükle/Sakla Tamamlayıcısı."
 
-#: config/tc-hppa.c:1944 config/tc-hppa.c:1949
+#: config/tc-hppa.c:1961 config/tc-hppa.c:1966
 msgid "Invalid Store Bytes Short Completer"
 msgstr "Geçersiz Short Bayt Saklama Tamamlayıcısı"
 
-#: config/tc-hppa.c:2260 config/tc-hppa.c:2266
+#: config/tc-hppa.c:2277 config/tc-hppa.c:2283
 msgid "Invalid left/right combination completer"
 msgstr "Geçersiz sol/sağ bileşim tamamlayıcısı"
 
-#: config/tc-hppa.c:2315 config/tc-hppa.c:2322
+#: config/tc-hppa.c:2332 config/tc-hppa.c:2339
 msgid "Invalid permutation completer"
 msgstr "Geçersiz permütasyon tamamlayıcısı"
 
-#: config/tc-hppa.c:2423
+#: config/tc-hppa.c:2439
 #, c-format
 msgid "Invalid Add Condition: %s"
 msgstr "Geçersiz Ekleme Koşulu: %s"
 
-#: config/tc-hppa.c:2434 config/tc-hppa.c:2444
+#: config/tc-hppa.c:2450 config/tc-hppa.c:2460
 msgid "Invalid Add and Branch Condition"
 msgstr "Geçersiz Ekleme ve Dal Koşulları"
 
-#: config/tc-hppa.c:2465 config/tc-hppa.c:2603
+#: config/tc-hppa.c:2481 config/tc-hppa.c:2618
 msgid "Invalid Compare/Subtract Condition"
 msgstr "Geçersiz Karşılaştırma/Çıkarma Koşulu"
 
-#: config/tc-hppa.c:2505
+#: config/tc-hppa.c:2521
 #, c-format
 msgid "Invalid Bit Branch Condition: %c"
 msgstr "Geçersiz Bit Dalı Koşulu: %c"
 
-#: config/tc-hppa.c:2591
+#: config/tc-hppa.c:2606
 #, c-format
 msgid "Invalid Compare/Subtract Condition: %s"
 msgstr "Geçersiz Karşılaştırma/Çıkarma Koşulu: %s"
 
-#: config/tc-hppa.c:2618
+#: config/tc-hppa.c:2633
 msgid "Invalid Compare and Branch Condition"
 msgstr "Geçersiz Karşılaştırma ve Dal Koşulu"
 
-#: config/tc-hppa.c:2714
+#: config/tc-hppa.c:2729
 msgid "Invalid Logical Instruction Condition."
 msgstr "Geçersiz Mantıksal İşlem Koşulu."
 
-#: config/tc-hppa.c:2769
+#: config/tc-hppa.c:2784
 msgid "Invalid Shift/Extract/Deposit Condition."
 msgstr "Geçersiz Kaydırma/Çıkartma/Sokma Koşulu."
 
-#: config/tc-hppa.c:2881
+#: config/tc-hppa.c:2896
 msgid "Invalid Unit Instruction Condition."
 msgstr "Geçersiz Birim İşlem Koşulu."
 
-#: config/tc-hppa.c:3258 config/tc-hppa.c:3290 config/tc-hppa.c:3321
-#: config/tc-hppa.c:3351
+#: config/tc-hppa.c:3273 config/tc-hppa.c:3305 config/tc-hppa.c:3336
+#: config/tc-hppa.c:3366
 msgid "Branch to unaligned address"
 msgstr "Hizalanmamış adrese dal"
 
-#: config/tc-hppa.c:3529
+#: config/tc-hppa.c:3544
 msgid "Invalid SFU identifier"
 msgstr "Geçersiz SFU tanımlayıcısı"
 
-#: config/tc-hppa.c:3579
+#: config/tc-hppa.c:3594
 msgid "Invalid COPR identifier"
 msgstr "Geçersiz COPR tanımlayıcısı"
 
-#: config/tc-hppa.c:3708
+#: config/tc-hppa.c:3723
 msgid "Invalid Floating Point Operand Format."
 msgstr "Geçersiz Kayan Nokta İşlenen Biçemi."
 
-#: config/tc-hppa.c:3825 config/tc-hppa.c:3845 config/tc-hppa.c:3865
-#: config/tc-hppa.c:3885 config/tc-hppa.c:3905
+#: config/tc-hppa.c:3840 config/tc-hppa.c:3860 config/tc-hppa.c:3880
+#: config/tc-hppa.c:3900 config/tc-hppa.c:3920
 msgid "Invalid register for single precision fmpyadd or fmpysub"
 msgstr "Tek duyarlılıkta fmpyadd veya fmpysub için geçersiz yazmaç"
 
-#: config/tc-hppa.c:3962
+#: config/tc-hppa.c:3977
 #, c-format
 msgid "Invalid operands %s"
 msgstr "Geçersiz işlenenler: %s"
 
-#: config/tc-hppa.c:4080
+#: config/tc-hppa.c:4095
 msgid "Cannot handle fixup"
 msgstr "düzeltme başarısız"
 
-#: config/tc-hppa.c:4381
+#: config/tc-hppa.c:4396
+#, c-format
 msgid "  -Q                      ignored\n"
 msgstr "  -Q                      yoksayıldı\n"
 
-#: config/tc-hppa.c:4385
+#: config/tc-hppa.c:4400
+#, c-format
 msgid "  -c                      print a warning if a comment is found\n"
 msgstr "  -c                      eğer açıklama bulunursa bir uyarı yazdırır\n"
 
-#: config/tc-hppa.c:4456
+#: config/tc-hppa.c:4471
 #, c-format
 msgid "no hppa_fixup entry for fixup type 0x%x"
 msgstr "düzeltme türü 0x%x için hppa_fixup girdisi yok"
 
-#: config/tc-hppa.c:4627
+#: config/tc-hppa.c:4642
 msgid "Unknown relocation encountered in md_apply_fix."
 msgstr "md_apply_fix'de bilinmeyen yerdeğişime rastlandı."
 
-#: config/tc-hppa.c:4769 config/tc-hppa.c:4794
+#: config/tc-hppa.c:4784 config/tc-hppa.c:4809
 #, c-format
 msgid "Undefined register: '%s'."
 msgstr "Tanımlanmamış yazmaç: '%s'."
 
-#: config/tc-hppa.c:4828
+#: config/tc-hppa.c:4843
 #, c-format
 msgid "Non-absolute symbol: '%s'."
 msgstr "Yerden bağımsız sembol: '%s'."
 
-#: config/tc-hppa.c:4843
+#: config/tc-hppa.c:4858
 #, c-format
 msgid "Undefined absolute constant: '%s'."
 msgstr "Tanımsız kesin sabit: '%s'."
 
-#: config/tc-hppa.c:4944
+#: config/tc-hppa.c:4959
 #, c-format
 msgid "Invalid FP Compare Condition: %s"
 msgstr "Geçersiz FP Karşılaştırma Koşulu: %s"
 
-#: config/tc-hppa.c:5000
+#: config/tc-hppa.c:5015
 #, c-format
 msgid "Invalid FTEST completer: %s"
 msgstr "Geçersiz FTEST tamamlayıcısı: %s"
 
-#: config/tc-hppa.c:5067 config/tc-hppa.c:5105
+#: config/tc-hppa.c:5082 config/tc-hppa.c:5120
 #, c-format
 msgid "Invalid FP Operand Format: %3s"
 msgstr "Geçersiz FP İşlenen Biçemi: %3s"
 
-#: config/tc-hppa.c:5184
+#: config/tc-hppa.c:5199
 msgid "Bad segment in expression."
 msgstr "İfadede hatalı bölüm."
 
-#: config/tc-hppa.c:5243
+#: config/tc-hppa.c:5258
 msgid "Bad segment (should be absolute)."
 msgstr "Hatalı bölüm (kesin olmalı)."
 
-#: config/tc-hppa.c:5286
+#: config/tc-hppa.c:5301
 #, c-format
 msgid "Invalid argument location: %s\n"
 msgstr "Geçersiz argüman yeri: %s\n"
 
-#: config/tc-hppa.c:5317
+#: config/tc-hppa.c:5332
 #, c-format
 msgid "Invalid argument description: %d"
 msgstr "Geçersiz argüman anlatımı: %d"
 
-#: config/tc-hppa.c:5340
+#: config/tc-hppa.c:5355
 #, c-format
 msgid "Invalid Nullification: (%c)"
 msgstr "Geçersiz Sıfırlama: (%c)"
 
-#: config/tc-hppa.c:6060
+#: config/tc-hppa.c:6075
 #, c-format
 msgid "Invalid .CALL argument: %s"
 msgstr "Geçersiz .CALL argümanı: %s"
 
-#: config/tc-hppa.c:6182
+#: config/tc-hppa.c:6197
 msgid ".callinfo is not within a procedure definition"
 msgstr ".callinfo bir altyordam tanımı içinde değil"
 
-#: config/tc-hppa.c:6202
+#: config/tc-hppa.c:6217
 #, c-format
 msgid "FRAME parameter must be a multiple of 8: %d\n"
 msgstr "FRAME parametresi 8'in katı olmalı: %d\n"
 
-#: config/tc-hppa.c:6221
+#: config/tc-hppa.c:6236
 msgid "Value for ENTRY_GR must be in the range 3..18\n"
 msgstr "ENTRY_GR değeri 3..18 aralığında olmalı\n"
 
-#: config/tc-hppa.c:6233
+#: config/tc-hppa.c:6248
 msgid "Value for ENTRY_FR must be in the range 12..21\n"
 msgstr "ENTRY_FR değeri 12..21 aralığında olmalı\n"
 
-#: config/tc-hppa.c:6243
+#: config/tc-hppa.c:6258
 msgid "Value for ENTRY_SR must be 3\n"
 msgstr "ENTRY_SR değeri 3 olmalı\n"
 
-#: config/tc-hppa.c:6299
+#: config/tc-hppa.c:6314
 #, c-format
 msgid "Invalid .CALLINFO argument: %s"
 msgstr "Geçersiz .CALLINFO argümanı: %s"
 
-#: config/tc-hppa.c:6410
+#: config/tc-hppa.c:6426
 msgid "The .ENTER pseudo-op is not supported"
 msgstr ".ENTER sanal-op'u desteklenmiyor"
 
-#: config/tc-hppa.c:6426
+#: config/tc-hppa.c:6442
 msgid "Misplaced .entry. Ignored."
 msgstr ".entry yanlış yerde. Yoksayıldı."
 
-#: config/tc-hppa.c:6430
+#: config/tc-hppa.c:6446
 msgid "Missing .callinfo."
 msgstr ".callinfo eksik."
 
-#: config/tc-hppa.c:6496
+#: config/tc-hppa.c:6512
 msgid ".REG expression must be a register"
 msgstr ".REG ifadesi bir yazmaç olmalı"
 
-#: config/tc-hppa.c:6512
+#: config/tc-hppa.c:6528
 msgid "bad or irreducible absolute expression; zero assumed"
 msgstr "hatalı veya indirgenemeyen kesin ifade; sıfır varsayıldı"
 
-#: config/tc-hppa.c:6523
+#: config/tc-hppa.c:6539
 msgid ".REG must use a label"
 msgstr ".REG bir etiket kullanmalı"
 
-#: config/tc-hppa.c:6525
+#: config/tc-hppa.c:6541
 msgid ".EQU must use a label"
 msgstr ".EQU bir etiket kullanmalı"
 
-#: config/tc-hppa.c:6578
+#: config/tc-hppa.c:6594
 msgid ".EXIT must appear within a procedure"
 msgstr ".EXIT bir altyordam içinde olmalı"
 
-#: config/tc-hppa.c:6582
+#: config/tc-hppa.c:6598
 msgid "Missing .callinfo"
 msgstr ".callinfo eksik"
 
-#: config/tc-hppa.c:6586
+#: config/tc-hppa.c:6602
 msgid "No .ENTRY for this .EXIT"
 msgstr "Bu .EXIT için bir .ENTRY yok"
 
-#: config/tc-hppa.c:6613
+#: config/tc-hppa.c:6629
 #, c-format
 msgid "Cannot define export symbol: %s\n"
 msgstr "İhraç sembolü tanımlanamadı: %s\n"
 
-#: config/tc-hppa.c:6671
+#: config/tc-hppa.c:6687
 #, c-format
 msgid "Using ENTRY rather than CODE in export directive for %s"
 msgstr "%s ihraç yönergesinde CODE yerine ENTRY kullanıldı"
 
-#: config/tc-hppa.c:6788
+#: config/tc-hppa.c:6804
 #, c-format
 msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s"
 msgstr "Tanımsız .EXPORT/.IMPORT argümanı (yoksayıldı): %s"
 
-#: config/tc-hppa.c:6870
+#: config/tc-hppa.c:6886
 msgid "Missing label name on .LABEL"
 msgstr ".LABEL'da etiket ismi eksik"
 
-#: config/tc-hppa.c:6875
+#: config/tc-hppa.c:6891
 msgid "extra .LABEL arguments ignored."
 msgstr "fazla .LABEL argümanları yoksayıldı."
 
-#: config/tc-hppa.c:6892
+#: config/tc-hppa.c:6908
 msgid "The .LEAVE pseudo-op is not supported"
 msgstr ".LEAVE sanal op'u desteklenmiyor"
 
-#: config/tc-hppa.c:6931
+#: config/tc-hppa.c:6947
 msgid "Unrecognized .LEVEL argument\n"
 msgstr "Bilinmeyen .LEVEL argümanı\n"
 
-#: config/tc-hppa.c:6967
+#: config/tc-hppa.c:6983
 #, c-format
 msgid "Cannot define static symbol: %s\n"
 msgstr "Statik sembol tanımlanamadı: %s\n"
 
-#: config/tc-hppa.c:7002
+#: config/tc-hppa.c:7018
 msgid "Nested procedures"
 msgstr "İçiçe altyordamlar"
 
-#: config/tc-hppa.c:7012
+#: config/tc-hppa.c:7028
 msgid "Cannot allocate unwind descriptor\n"
 msgstr "Unwind betimleyicisine bellek ayrılamadı\n"
 
-#: config/tc-hppa.c:7112
+#: config/tc-hppa.c:7128
 msgid "misplaced .procend"
 msgstr ".procend yanlış yerde"
 
-#: config/tc-hppa.c:7115
+#: config/tc-hppa.c:7131
 msgid "Missing .callinfo for this procedure"
 msgstr "Bu altyordam için .callinfo eksik"
 
-#: config/tc-hppa.c:7118
+#: config/tc-hppa.c:7134
 msgid "Missing .EXIT for a .ENTRY"
 msgstr ".ENTRY için .EXIT eksik"
 
-#: config/tc-hppa.c:7156
+#: config/tc-hppa.c:7172
 msgid "Not in a space.\n"
 msgstr "BoÅŸluk deÄŸil.\n"
 
-#: config/tc-hppa.c:7159
+#: config/tc-hppa.c:7175
 msgid "Not in a subspace.\n"
 msgstr "AltboÅŸlukta deÄŸil.\n"
 
-#: config/tc-hppa.c:7250
+#: config/tc-hppa.c:7266
 msgid "Invalid .SPACE argument"
 msgstr "Geçersiz .SPACE argümanı"
 
-#: config/tc-hppa.c:7297
+#: config/tc-hppa.c:7313
 msgid "Can't change spaces within a procedure definition. Ignored"
 msgstr "Bir altyordam tanımı içinde boşluklar değiştirilemez. Yoksayıldı"
 
-#: config/tc-hppa.c:7426
+#: config/tc-hppa.c:7442
 #, c-format
 msgid "Undefined space: '%s' Assuming space number = 0."
 msgstr "Tanımsız boşluk: '%s' Boşluk sayısı = 0 varsayıldı"
 
-#: config/tc-hppa.c:7450
+#: config/tc-hppa.c:7466
 msgid "Must be in a space before changing or declaring subspaces.\n"
 msgstr ""
 "Altboşluklar değiştirilmeden veya tanımlanmadan önce bir boşluk içinde olmak\n"
 "gerekli.\n"
 
-#: config/tc-hppa.c:7454
+#: config/tc-hppa.c:7470
 msgid "Can't change subspaces within a procedure definition. Ignored"
 msgstr "Bir altyordam tanımı içinde altboşluklar değiştirilemez. Yoksayıldı"
 
-#: config/tc-hppa.c:7489
+#: config/tc-hppa.c:7506
 msgid "Parameters of an existing subspace can't be modified"
 msgstr "Var olan bir altboÅŸluÄŸun parametreleri deÄŸiÅŸtirilemez"
 
-#: config/tc-hppa.c:7540
+#: config/tc-hppa.c:7558
 msgid "Alignment must be a power of 2"
 msgstr "Hizalama 2'nin kuvvetleri olmalı"
 
-#: config/tc-hppa.c:7582
+#: config/tc-hppa.c:7605
 msgid "FIRST not supported as a .SUBSPACE argument"
 msgstr "FIRST, bir .SUBSPACE argümanı olarak desteklenmiyor"
 
-#: config/tc-hppa.c:7584
+#: config/tc-hppa.c:7607
 msgid "Invalid .SUBSPACE argument"
 msgstr "Geçersiz .SUBSPACE argümanı"
 
-#: config/tc-hppa.c:7764
+#: config/tc-hppa.c:7796
 #, c-format
 msgid "Internal error: Unable to find containing space for %s."
 msgstr "İç hata: %s için taşıyıcı boşluk bulunamadı."
 
-#: config/tc-hppa.c:7803
+#: config/tc-hppa.c:7836
 #, c-format
 msgid "Out of memory: could not allocate new space chain entry: %s\n"
 msgstr "Bellek tükendi: Yeni boşluk zincir girdisine bellek ayrılamadı: %s\n"
 
-#: config/tc-hppa.c:7889
+#: config/tc-hppa.c:7925
 #, c-format
 msgid "Out of memory: could not allocate new subspace chain entry: %s\n"
 msgstr "Bellek tükendi: Yeni altboşluk zincir girdisine bellek ayrılamadı: %s\n"
 
-#: config/tc-hppa.c:8622
+#: config/tc-hppa.c:8661
 #, c-format
 msgid "Symbol '%s' could not be created."
 msgstr "Sembol '%s' oluşturulamadı."
 
-#: config/tc-hppa.c:8626
+#: config/tc-hppa.c:8665
 msgid "No memory for symbol name."
 msgstr "Sembol ismi için bellek yok."
 
-#: config/tc-i386.c:689
+#: config/tc-i386.c:706
 #, c-format
 msgid "%s shortened to %s"
 msgstr "%s, %s olarak kısaltıldı"
 
-#: config/tc-i386.c:745
+#: config/tc-i386.c:762
 msgid "same type of prefix used twice"
 msgstr "Aynı tür önek iki kez kullanıldı"
 
-#: config/tc-i386.c:763
+#: config/tc-i386.c:780
 msgid "64bit mode not supported on this CPU."
 msgstr "Bu CPU'da 64bit kipi desteklenmiyor."
 
-#: config/tc-i386.c:767
+#: config/tc-i386.c:784
 msgid "32bit mode not supported on this CPU."
 msgstr "Bu CPU'da 32bit kipi desteklenmiyor."
 
-#: config/tc-i386.c:800
+#: config/tc-i386.c:817
 msgid "bad argument to syntax directive."
 msgstr "Sözdizim yönergesine hatalı argüman."
 
-#: config/tc-i386.c:844
+#: config/tc-i386.c:869
 #, c-format
 msgid "no such architecture: `%s'"
 msgstr "Böyle bir yapı yok: `%s'"
 
-#: config/tc-i386.c:849
+#: config/tc-i386.c:874
 msgid "missing cpu architecture"
 msgstr "eksik cpu yapısı"
 
-#: config/tc-i386.c:863
+#: config/tc-i386.c:888
 #, c-format
 msgid "no such architecture modifier: `%s'"
 msgstr "Böyle bir yapı yok: `%s'"
 
-#: config/tc-i386.c:880 config/tc-i386.c:5013
+#: config/tc-i386.c:904 config/tc-i386.c:5169
 msgid "Unknown architecture"
 msgstr "Bilinmeyen yapı"
 
-#: config/tc-i386.c:915 config/tc-i386.c:938 config/tc-m68k.c:3816
-#, c-format
-msgid "Internal Error:  Can't hash %s: %s"
-msgstr "İç Hata: %s hash'lenemedi: %s"
-
-#: config/tc-i386.c:1192
+#: config/tc-i386.c:1218
 msgid "There are no unsigned pc-relative relocations"
 msgstr "İşaretsiz (unsigned) pc-göreli yerdeğişimler yok"
 
-#: config/tc-i386.c:1199 config/tc-i386.c:5225
+#: config/tc-i386.c:1225 config/tc-i386.c:5379
 #, c-format
 msgid "can not do %d byte pc-relative relocation"
 msgstr "%d baytlık pc-göreli yerdeğişimler yapılamaz"
 
-#: config/tc-i386.c:1216
+#: config/tc-i386.c:1242
 #, c-format
 msgid "can not do %s %d byte relocation"
 msgstr "%s %d baytlık yerdeğişim yapılamaz"
 
-#: config/tc-i386.c:1428
+#: config/tc-i386.c:1438 config/tc-i386.c:2416
+#, fuzzy, c-format
+msgid "ambiguous operand size for `%s'"
+msgstr "`%s' için geçersiz işlenen"
+
+#: config/tc-i386.c:1486
 #, c-format
 msgid "can't use register '%%%s' as operand %d in '%s'."
 msgstr "'%3$s' içinde '%%%1$s' yazmacı %2$d işleneni olarak kullanılamaz."
 
 #. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.
-#: config/tc-i386.c:1457
+#: config/tc-i386.c:1515
 #, c-format
 msgid "translating to `%sp'"
 msgstr "`%sp'e çevrildi"
 
-#: config/tc-i386.c:1502
-#, c-format
-msgid "can't encode register '%%%s' in an instruction requiring REX prefix.\n"
+#: config/tc-i386.c:1560
+#, fuzzy, c-format
+msgid "can't encode register '%%%s' in an instruction requiring REX prefix."
 msgstr "'%%%s' yazmaçları REX öneki gerektiren işlemde kodlanamaz.\n"
 
-#: config/tc-i386.c:1541 config/tc-i386.c:1636
+#: config/tc-i386.c:1601 config/tc-i386.c:1699
 #, c-format
 msgid "no such instruction: `%s'"
 msgstr "Ä°ÅŸlem yok: `%s'"
 
-#: config/tc-i386.c:1551 config/tc-i386.c:1668
+#: config/tc-i386.c:1611 config/tc-i386.c:1731
 #, c-format
 msgid "invalid character %s in mnemonic"
 msgstr "İpucunda geçersiz %s karakteri"
 
-#: config/tc-i386.c:1558
+#: config/tc-i386.c:1618
 msgid "expecting prefix; got nothing"
 msgstr "önek beklendi; hiç bir şey bulunamadı"
 
-#: config/tc-i386.c:1560
+#: config/tc-i386.c:1620
 msgid "expecting mnemonic; got nothing"
 msgstr "ipucu beklendi; hiç bir şey bulunamadı"
 
-#: config/tc-i386.c:1579
+#: config/tc-i386.c:1639
 #, c-format
 msgid "redundant %s prefix"
 msgstr "fazla %s öneki"
 
-#: config/tc-i386.c:1677
-#, c-format
-msgid "`%s' is not supported on `%s'"
+#: config/tc-i386.c:1749
+#, fuzzy, c-format
+msgid "`%s' is not supported in 64-bit mode"
+msgstr "@%s yerdeÄŸiÅŸimleri %s bit kipinde desteklenmiyor"
+
+#: config/tc-i386.c:1750
+#, fuzzy, c-format
+msgid "`%s' is only supported in 64-bit mode"
+msgstr "@%s yerdeÄŸiÅŸimleri %s bit kipinde desteklenmiyor"
+
+#: config/tc-i386.c:1756
+#, fuzzy, c-format
+msgid "`%s' is not supported on `%s%s'"
 msgstr "`%s', `%s' üzerinde desteklenmiyor"
 
-#: config/tc-i386.c:1682
+#: config/tc-i386.c:1763
 msgid "use .code16 to ensure correct addressing mode"
 msgstr "doğru adresleme kipi için .code16 kullanın"
 
-#: config/tc-i386.c:1689
+#: config/tc-i386.c:1770
 #, c-format
 msgid "expecting string instruction after `%s'"
 msgstr "`%s'den sonra dizge iÅŸlemi beklendi"
 
-#: config/tc-i386.c:1717
+#: config/tc-i386.c:1798
 #, c-format
 msgid "invalid character %s before operand %d"
 msgstr "%2$d işleneninden önce geçersiz %1$s karakteri"
 
-#: config/tc-i386.c:1731
+#: config/tc-i386.c:1812
 #, c-format
 msgid "unbalanced parenthesis in operand %d."
 msgstr "%d iÅŸleneninde eÅŸlenmeyen parantez"
 
-#: config/tc-i386.c:1734
+#: config/tc-i386.c:1815
 #, c-format
 msgid "unbalanced brackets in operand %d."
 msgstr "%d işleneninde eşleşmeyen köşeli parantez"
 
-#: config/tc-i386.c:1743
+#: config/tc-i386.c:1824
 #, c-format
 msgid "invalid character %s in operand %d"
 msgstr "%2$d işleneninde geçersiz %1$s karakteri"
 
-#: config/tc-i386.c:1770
+#: config/tc-i386.c:1851
 #, c-format
 msgid "spurious operands; (%d operands/instruction max)"
 msgstr "gereksiz iÅŸlenenler; (%d iÅŸlenen/iÅŸlem maksimumu)"
 
-#: config/tc-i386.c:1793
+#: config/tc-i386.c:1874
 msgid "expecting operand after ','; got nothing"
 msgstr "işlenenden sonra ',' beklendi; hiç bir şey bulunamadı"
 
-#: config/tc-i386.c:1798
+#: config/tc-i386.c:1879
 msgid "expecting operand before ','; got nothing"
 msgstr "','den önce işlenen beklendi; hiç bir şey bulunamadı"
 
 #. We found no match.
-#: config/tc-i386.c:2140
+#: config/tc-i386.c:2225
 #, c-format
 msgid "suffix or operands invalid for `%s'"
 msgstr "`%s' için sonek veya işlenenler geçersiz"
 
-#: config/tc-i386.c:2151
+#: config/tc-i386.c:2236
 #, c-format
 msgid "indirect %s without `*'"
 msgstr "`*' olmaksızın endirekt %s"
 
 #. Warn them that a data or address size prefix doesn't
 #. affect assembly of the next line of code.
-#: config/tc-i386.c:2159
+#: config/tc-i386.c:2244
 #, c-format
 msgid "stand-alone `%s' prefix"
 msgstr "tek kullanılabilen `%s' öneki"
 
-#: config/tc-i386.c:2188 config/tc-i386.c:2203
+#: config/tc-i386.c:2273 config/tc-i386.c:2288
 #, c-format
 msgid "`%s' operand %d must use `%%es' segment"
 msgstr "`%s' işleneni %d `%%es' bölümünü kullanmalı"
 
-#: config/tc-i386.c:2283
+#: config/tc-i386.c:2398
 msgid "no instruction mnemonic suffix given and no register operands; can't size instruction"
 msgstr "işlem ipucu soneki verilmemiş ve yazmaç işlenenleri yok; işlem boyu hesaplanamıyor"
 
 #. Prohibit these changes in the 64bit mode, since the
 #. lowering is more complicated.
-#: config/tc-i386.c:2367 config/tc-i386.c:2426 config/tc-i386.c:2443
-#: config/tc-i386.c:2475 config/tc-i386.c:2508
+#: config/tc-i386.c:2499 config/tc-i386.c:2558 config/tc-i386.c:2575
+#: config/tc-i386.c:2607 config/tc-i386.c:2640
 #, c-format
 msgid "Incorrect register `%%%s' used with `%c' suffix"
 msgstr "Hatalı `%%%s' yazmacı `%c' soneki ile kullanılmış"
 
-#: config/tc-i386.c:2375 config/tc-i386.c:2433 config/tc-i386.c:2515
+#: config/tc-i386.c:2507 config/tc-i386.c:2565 config/tc-i386.c:2647
 #, c-format
 msgid "using `%%%s' instead of `%%%s' due to `%c' suffix"
 msgstr "`%3$c' soneki yüzünden `%%%2$s' yerine `%%%1$s' kullanılıyor"
 
-#: config/tc-i386.c:2390 config/tc-i386.c:2411 config/tc-i386.c:2462
-#: config/tc-i386.c:2493
+#: config/tc-i386.c:2522 config/tc-i386.c:2543 config/tc-i386.c:2594
+#: config/tc-i386.c:2625
 #, c-format
 msgid "`%%%s' not allowed with `%s%c'"
 msgstr "`%%%s', `%s%c' ile kullanılamaz"
 
-#: config/tc-i386.c:2556
+#: config/tc-i386.c:2688
 msgid "no instruction mnemonic suffix given; can't determine immediate size"
 msgstr "işlem ipucu soneki verilmemiş; şimdiki boy hesaplanamıyor"
 
-#: config/tc-i386.c:2589
+#: config/tc-i386.c:2721
 #, c-format
 msgid "no instruction mnemonic suffix given; can't determine immediate size %x %c"
 msgstr "işlem ipucu soneki verilmemiş; şimdiki boy %x %c hesaplanamıyor"
 
 #. Reversed arguments on faddp, fsubp, etc.
-#: config/tc-i386.c:2638
+#: config/tc-i386.c:2770
 #, c-format
 msgid "translating to `%s %%%s,%%%s'"
 msgstr "`%s %%%s,%%%s'e çevrildi"
 
 #. Extraneous `l' suffix on fp insn.
-#: config/tc-i386.c:2645
+#: config/tc-i386.c:2777
 #, c-format
 msgid "translating to `%s %%%s'"
 msgstr "`%s %%%s'e çevrildi"
 
-#: config/tc-i386.c:2663
+#: config/tc-i386.c:2795
 #, c-format
 msgid "you can't `pop %%cs'"
 msgstr "`pop %%cs' emme işlemi yapılamıyor"
 
 #. lea
-#: config/tc-i386.c:2682
+#: config/tc-i386.c:2814
 msgid "segment override on `lea' is ineffectual"
 msgstr "`lea' üzerinde bölüm üstüne yazması sonuçsuz"
 
-#: config/tc-i386.c:2991 config/tc-i386.c:3085 config/tc-i386.c:3130
+#: config/tc-i386.c:3123 config/tc-i386.c:3217 config/tc-i386.c:3262
 msgid "skipping prefixes on this instruction"
 msgstr "bu işlemde önekler atlanıyor"
 
-#: config/tc-i386.c:3150
+#: config/tc-i386.c:3282
 msgid "16-bit jump out of range"
 msgstr "16bitlik sıçrama kapsam dışı"
 
-#: config/tc-i386.c:3159
+#: config/tc-i386.c:3291
 #, c-format
 msgid "can't handle non absolute segment in `%s'"
 msgstr "`%s' içinde kesin olmayan bölüm desteklenmiyor"
 
-#: config/tc-i386.c:3601
+#: config/tc-i386.c:3749
 #, c-format
 msgid "@%s reloc is not supported in %s bit mode"
 msgstr "@%s yerdeÄŸiÅŸimleri %s bit kipinde desteklenmiyor"
 
-#: config/tc-i386.c:3677
+#: config/tc-i386.c:3867
 msgid "only 1 or 2 immediate operands are allowed"
 msgstr "yalnız 1 veya 2 şimdiki işlenen kullanılabilir"
 
-#: config/tc-i386.c:3700 config/tc-i386.c:3892
+#: config/tc-i386.c:3890 config/tc-i386.c:4071
 #, c-format
 msgid "junk `%s' after expression"
 msgstr "ifade sonrasında hatalı `%s'"
 
 #. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3711
+#: config/tc-i386.c:3901
 #, c-format
 msgid "missing or invalid immediate expression `%s' taken as 0"
 msgstr "eksik veya hatalı şimdiki `%s' ifadesi 0 varsayıldı"
 
-#: config/tc-i386.c:3743 config/tc-i386.c:3958
+#: config/tc-i386.c:3926 config/tc-i386.c:4129
 #, c-format
 msgid "unimplemented segment %s in operand"
 msgstr "işlenende desteklenmeyen %s bölümü"
 
-#: config/tc-i386.c:3745 config/tc-i386.c:3960
-#, c-format
-msgid "unimplemented segment type %d in operand"
-msgstr "işlenende desteklenmeyen bölüm türü %d"
-
-#: config/tc-i386.c:3789 config/tc-i386.c:6002
+#: config/tc-i386.c:3968 config/tc-i386.c:6264
 #, c-format
 msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'"
 msgstr "Ölçek çarpanı 1, 2, 4 veya 8 beklendi: `%s' bulundu"
 
-#: config/tc-i386.c:3796
+#: config/tc-i386.c:3975
 #, c-format
 msgid "scale factor of %d without an index register"
 msgstr "indeks yazmaçsız ölçek çarpanı %d"
 
-#: config/tc-i386.c:3912
+#: config/tc-i386.c:4090
 #, c-format
 msgid "bad expression used with @%s"
 msgstr "@%s ile kullanılmış geçersiz ifade"
 
-#. Missing or bad expr becomes absolute 0.
-#: config/tc-i386.c:3934
-#, c-format
-msgid "missing or invalid displacement expression `%s' taken as 0"
-msgstr "eksik veya hatalı yerdeğişim ifadesi `%s' 0 varsayıldı"
-
-#: config/tc-i386.c:4058
+#: config/tc-i386.c:4213
 #, c-format
 msgid "`%s' is not a valid base/index expression"
 msgstr "`%s' geçerli bir temel/indeks ifadesi değil"
 
-#: config/tc-i386.c:4062
+#: config/tc-i386.c:4217
 #, c-format
 msgid "`%s' is not a valid %s bit base/index expression"
 msgstr "`%s' geçerli %s bitlik temel/indeks ifadesi değil"
 
-#: config/tc-i386.c:4137
+#: config/tc-i386.c:4291
 #, c-format
 msgid "bad memory operand `%s'"
 msgstr "hatalı bellek işleneni `%s'"
 
-#: config/tc-i386.c:4152
+#: config/tc-i386.c:4306
 #, c-format
 msgid "junk `%s' after register"
 msgstr "yazmaçtan sonra bozuk `%s'"
 
-#: config/tc-i386.c:4161 config/tc-i386.c:4276 config/tc-i386.c:4314
+#: config/tc-i386.c:4315 config/tc-i386.c:4430 config/tc-i386.c:4468
 #, c-format
 msgid "bad register name `%s'"
 msgstr "hatalı yazmaç ismi `%s'"
 
-#: config/tc-i386.c:4169
+#: config/tc-i386.c:4323
 msgid "immediate operand illegal with absolute jump"
 msgstr "şimdiki işlenen, kesin sıçrama ile geçersiz"
 
-#: config/tc-i386.c:4191
+#: config/tc-i386.c:4345
 #, c-format
 msgid "too many memory references for `%s'"
 msgstr "`%s' için çok fazla bellek başvurusu"
 
-#: config/tc-i386.c:4269
+#: config/tc-i386.c:4423
 #, c-format
 msgid "expecting `,' or `)' after index register in `%s'"
 msgstr "%s içinde indeks yazmacından sonra `,' veya `)' beklendi"
 
-#: config/tc-i386.c:4293
+#: config/tc-i386.c:4447
 #, c-format
 msgid "expecting `)' after scale factor in `%s'"
 msgstr "`%s' içinde ölçek çarpanından sonra `)' beklendi"
 
-#: config/tc-i386.c:4300
+#: config/tc-i386.c:4454
 #, c-format
 msgid "expecting index register or scale factor after `,'; got '%c'"
 msgstr "`,'den sonra indeks yazmacı veya ölçek çarpanı beklendi; '%c' bulundu"
 
-#: config/tc-i386.c:4307
+#: config/tc-i386.c:4461
 #, c-format
 msgid "expecting `,' or `)' after base register in `%s'"
 msgstr "`%s' içinde temel yazmaçtan sonra `,' veya `)' beklendi"
 
 #. It's not a memory operand; argh!
-#: config/tc-i386.c:4348
+#: config/tc-i386.c:4502
 #, c-format
 msgid "invalid char %s beginning operand %d `%s'"
 msgstr "%2$d `%3$s' işleneninin başında geçersiz karakter %1$s"
 
-#: config/tc-i386.c:4531
+#: config/tc-i386.c:4677
 msgid "long jump required"
 msgstr "uzun atlama gerekli"
 
-#: config/tc-i386.c:4796
+#: config/tc-i386.c:4954
 msgid "Bad call to md_atof ()"
 msgstr "md_atof()'a hatalı çağrı"
 
-#: config/tc-i386.c:4964
+#: config/tc-i386.c:5121
 msgid "No compiled in support for x86_64"
 msgstr "x86_64 için derlenmiş destek yok"
 
-#: config/tc-i386.c:4985
+#: config/tc-i386.c:5142
+#, c-format
 msgid ""
 "  -Q                      ignored\n"
 "  -V                      print assembler version number\n"
@@ -4568,7 +5152,8 @@ msgstr ""
 "  -q                      bazı uyarıları durdurur\n"
 "  -s                      yoksayılır\n"
 
-#: config/tc-i386.c:4993
+#: config/tc-i386.c:5150
+#, c-format
 msgid ""
 "  -n                      Do not optimize code alignment\n"
 "  -q                      quieten some warnings\n"
@@ -4576,118 +5161,153 @@ msgstr ""
 "  -n                      kod hizalamasını optimize etmez\n"
 "  -q                      bazı uyarıları durdurur\n"
 
-#: config/tc-i386.c:5095 config/tc-s390.c:1841
+#: config/tc-i386.c:5250 config/tc-s390.c:1826
 msgid "GOT already in symbol table"
 msgstr "GOT zaten sembol tablosunda"
 
-#: config/tc-i386.c:5240
+#: config/tc-i386.c:5394
 #, c-format
 msgid "can not do %d byte relocation"
 msgstr "%d baytlık yerdeğişim yapılamaz"
 
-#: config/tc-i386.c:5308 config/tc-s390.c:2285
+#: config/tc-i386.c:5463 config/tc-s390.c:2272
 #, c-format
 msgid "cannot represent relocation type %s"
 msgstr "%s yerdeğişim türü gösterilemiyor"
 
-#: config/tc-i386.c:5604
+#: config/tc-i386.c:5709
+#, fuzzy, c-format
+msgid "invalid operand for '%s' ('%s' unexpected)"
+msgstr "'%2$s' için %1$d işlenen bulundu:  %3$d beklendi"
+
+#: config/tc-i386.c:5721
 #, c-format
 msgid "too many memory references for '%s'"
 msgstr "'%s' için çok fazla bellek başvurusu"
 
-#: config/tc-i386.c:5767
-#, c-format
-msgid "Unknown operand modifier `%s'\n"
+#: config/tc-i386.c:5996
+#, fuzzy, c-format
+msgid "Unknown operand modifier `%s'"
 msgstr "Bilinmeyen `%s' iÅŸlenen deÄŸiÅŸtiricisi\n"
 
-#: config/tc-i386.c:5974
+#: config/tc-i386.c:6006
+#, fuzzy
+msgid "Conflicting operand modifiers"
+msgstr "desteklenmeyen iÅŸlenen deÄŸiÅŸtiricisi"
+
+#: config/tc-i386.c:6236
 #, c-format
 msgid "`%s' is not a valid segment register"
 msgstr "`%s' geçerli bir bölüm yazmacı değil"
 
-#: config/tc-i386.c:5984 config/tc-i386.c:6105
+#: config/tc-i386.c:6246 config/tc-i386.c:6373
 msgid "Register scaling only allowed in memory operands."
 msgstr "Yazmaç ölçeklenmesi yalnız bellek işlenenleri için geçerli."
 
-#: config/tc-i386.c:6015
-msgid "Too many register references in memory operand.\n"
+#: config/tc-i386.c:6277
+#, fuzzy
+msgid "Too many register references in memory operand."
 msgstr "Bellek işleneninde çok fazla yazmaç başvurusu.\n"
 
-#: config/tc-i386.c:6084
-#, c-format
-msgid "Syntax error. Expecting a constant. Got `%s'.\n"
+#: config/tc-i386.c:6352
+#, fuzzy, c-format
+msgid "Syntax error. Expecting a constant. Got `%s'."
 msgstr "Sözdizim hatası. Sabit beklendi. `%s' bulundu.\n"
 
-#: config/tc-i386.c:6154
+#: config/tc-i386.c:6422
 #, c-format
 msgid "Unrecognized token '%s'"
 msgstr "Bilinmeyen '%s' dizgeciÄŸi"
 
-#: config/tc-i386.c:6171
-#, c-format
-msgid "Unexpected token `%s'\n"
+#: config/tc-i386.c:6439
+#, fuzzy, c-format
+msgid "Unexpected token `%s'"
 msgstr "Beklenmeyen `%s' dizgeciÄŸi\n"
 
-#: config/tc-i386.c:6315
-#, c-format
-msgid "Unrecognized token `%s'\n"
+#: config/tc-i386.c:6622
+#, fuzzy, c-format
+msgid "Unrecognized token `%s'"
 msgstr "Bilinmeyen `%s' dizgeciÄŸi\n"
 
-#: config/tc-i860.c:165 config/tc-i860.c:169
+#: config/tc-i860.c:124
+msgid "Directive .dual available only with -mintel-syntax option"
+msgstr ""
+
+#: config/tc-i860.c:134
+msgid "Directive .enddual available only with -mintel-syntax option"
+msgstr ""
+
+#: config/tc-i860.c:147
+msgid "Directive .atmp available only with -mintel-syntax option"
+msgstr ""
+
+#: config/tc-i860.c:169 config/tc-i860.c:173
 msgid "Unknown temporary pseudo register"
 msgstr "Bilinmeyen geçici sanal yazmaç"
 
-#: config/tc-i860.c:192 config/tc-mips.c:1104
+#: config/tc-i860.c:229 config/tc-mips.c:1149
 #, c-format
 msgid "internal error: can't hash `%s': %s\n"
 msgstr "İç hata: `%s' hash'lenemedi: %s\n"
 
-#: config/tc-i860.c:212
+#: config/tc-i860.c:249
 msgid "Defective assembler.  No assembly attempted."
 msgstr "Çevirici problemli. Çeviri yapılamıyor."
 
-#: config/tc-i860.c:362
+#: config/tc-i860.c:402
 #, c-format
 msgid "Expanded opcode after delayed branch: `%s'"
 msgstr "Gecikmeli daldan sonra geniÅŸletilmiÅŸ opkod: `%s'"
 
-#: config/tc-i860.c:366
+#: config/tc-i860.c:406
 #, c-format
 msgid "Expanded opcode in dual mode: `%s'"
 msgstr "Çiftli kipte genişletilmiş opkod: `%s'"
 
-#: config/tc-i860.c:370
+#: config/tc-i860.c:410
 #, c-format
 msgid "An instruction was expanded (%s)"
 msgstr "Ä°ÅŸlem geniÅŸletildi (%s)"
 
-#: config/tc-i860.c:643
+#: config/tc-i860.c:676
 msgid "Pipelined instruction: fsrc1 = fdest"
 msgstr "Veriyollanmış işlem: fsrc1 = fdest"
 
-#: config/tc-i860.c:844 config/tc-i860.c:851 config/tc-i860.c:858
+#: config/tc-i860.c:879 config/tc-i860.c:886 config/tc-i860.c:893
 msgid "Assembler does not yet support PIC"
 msgstr "Çevirici henüz PIC desteklemiyor"
 
-#: config/tc-i860.c:919
+#: config/tc-i860.c:957
 #, c-format
 msgid "Illegal operands for %s"
 msgstr "%s için geçersiz işlenen"
 
-#: config/tc-i860.c:947 config/tc-sparc.c:2834
+#: config/tc-i860.c:974
+#, c-format
+msgid "'d.%s' must be 8-byte aligned"
+msgstr ""
+
+#: config/tc-i860.c:982
+#, fuzzy, c-format
+msgid "Prefix 'd.' invalid for instruction `%s'"
+msgstr "Ä°ÅŸlemin sonunda bozukluk: `%s'."
+
+#: config/tc-i860.c:1005 config/tc-sparc.c:2845
 msgid "bad segment"
 msgstr "hatalı bölüm"
 
-#: config/tc-i860.c:1037
+#: config/tc-i860.c:1088
 msgid "i860_estimate_size_before_relax\n"
 msgstr "i860_estimate_size_before_relax\n"
 
-#: config/tc-i860.c:1134
+#: config/tc-i860.c:1187
+#, fuzzy, c-format
 msgid ""
 "  -EL\t\t\t  generate code for little endian mode (default)\n"
 "  -EB\t\t\t  generate code for big endian mode\n"
 "  -mwarn-expand\t\t  warn if pseudo operations are expanded\n"
 "  -mxp\t\t\t  enable i860XP support (disabled by default)\n"
+"  -mintel-syntax\t  enable Intel syntax (default to AT&T/SVR4)\n"
 msgstr ""
 "  -EL\t\t\t  küçük sonlu kipte kod üretir (öntanımlı)\n"
 "  -EB\t\t\t  büyük sonlu kipte kod üretir\n"
@@ -4695,7 +5315,8 @@ msgstr ""
 "  -mxp\t\t\t  i860XP desteğini etkinleştirir (öntanımlı etkisiz)\n"
 
 #. SVR4 compatibility flags.
-#: config/tc-i860.c:1141
+#: config/tc-i860.c:1195
+#, c-format
 msgid ""
 "  -V\t\t\t  print assembler version number\n"
 "  -Qy, -Qn\t\t  ignored\n"
@@ -4703,35 +5324,35 @@ msgstr ""
 "  -V\t\t\t  çevirici sürüm numarasını yazdırır\n"
 "  -Qy, -Qn\t\t  yoksayılır\n"
 
-#: config/tc-i860.c:1210
+#: config/tc-i860.c:1258
 msgid "This immediate requires 0 MOD 2 alignment"
 msgstr "Şimdiki için 0 MOD 2 hizalaması gerekli"
 
-#: config/tc-i860.c:1213
+#: config/tc-i860.c:1261
 msgid "This immediate requires 0 MOD 4 alignment"
 msgstr "Şimdiki için 0 MOD 4 hizalaması gerekli"
 
-#: config/tc-i860.c:1216
+#: config/tc-i860.c:1264
 msgid "This immediate requires 0 MOD 8 alignment"
 msgstr "Şimdiki için 0 MOD 8 hizalaması gerekli"
 
-#: config/tc-i860.c:1219
+#: config/tc-i860.c:1267
 msgid "This immediate requires 0 MOD 16 alignment"
 msgstr "Şimdiki için 0 MOD 16 hizalaması gerekli"
 
-#: config/tc-i860.c:1317
+#: config/tc-i860.c:1362
 msgid "5-bit immediate too large"
 msgstr "5bitlik şimdiki fazla büyük"
 
-#: config/tc-i860.c:1320
+#: config/tc-i860.c:1365
 msgid "5-bit field must be absolute"
 msgstr "5bitlik alan kesin olmalı"
 
-#: config/tc-i860.c:1365 config/tc-i860.c:1388
+#: config/tc-i860.c:1410 config/tc-i860.c:1433
 msgid "A branch offset requires 0 MOD 4 alignment"
 msgstr "Dal göreli konumu için 0 MOD 4 hizalaması gerekli"
 
-#: config/tc-i860.c:1409
+#: config/tc-i860.c:1454
 #, c-format
 msgid "Unrecognized fix-up (0x%08lx)"
 msgstr "Bilinmeyen düzeltme (0x%08lx)"
@@ -4771,10 +5392,12 @@ msgid "invalid architecture %s"
 msgstr "geçersiz yapı %s"
 
 #: config/tc-i960.c:1014
+#, c-format
 msgid "I960 options:\n"
 msgstr "I960 seçenekleri:\n"
 
 #: config/tc-i960.c:1017
+#, c-format
 msgid ""
 "\n"
 "\t\t\tspecify variant of 960 architecture\n"
@@ -4792,112 +5415,112 @@ msgstr ""
 "-no-relax\t\tkarşılaştır-ve-dallan işlemlerini uzak yerdeğişimler için\n"
 "\t\t\tdeÄŸiÅŸtirmez\n"
 
-#: config/tc-i960.c:1419 config/tc-xtensa.c:8604
+#: config/tc-i960.c:1424 config/tc-xtensa.c:11516
 msgid "too many operands"
 msgstr "çok fazla işlenen"
 
-#: config/tc-i960.c:1477 config/tc-i960.c:1702
+#: config/tc-i960.c:1482 config/tc-i960.c:1707
 msgid "expression syntax error"
 msgstr "ifade sözdizim hatası"
 
-#: config/tc-i960.c:1515
+#: config/tc-i960.c:1520
 msgid "attempt to branch into different segment"
 msgstr "değişik bölüme dallanma denemesi"
 
-#: config/tc-i960.c:1519
+#: config/tc-i960.c:1524
 #, c-format
 msgid "target of %s instruction must be a label"
 msgstr "%s işleminin hedefi etiket olmalı"
 
-#: config/tc-i960.c:1557
+#: config/tc-i960.c:1562
 msgid "unmatched '['"
 msgstr "'[' eÅŸleÅŸmiyor"
 
-#: config/tc-i960.c:1568
+#: config/tc-i960.c:1573
 msgid "garbage after index spec ignored"
 msgstr "indeks tanımından sonraki bozukluk yoksayıldı"
 
 #. We never moved: there was no opcode either!
-#: config/tc-i960.c:1633
+#: config/tc-i960.c:1638
 msgid "missing opcode"
 msgstr "eksik opkod"
 
-#: config/tc-i960.c:2046
+#: config/tc-i960.c:2051
 msgid "invalid index register"
 msgstr "geçersiz indeks yazmacı"
 
-#: config/tc-i960.c:2069
+#: config/tc-i960.c:2074
 msgid "invalid scale factor"
 msgstr "geçersiz ölçek çarpanı"
 
-#: config/tc-i960.c:2250
+#: config/tc-i960.c:2255
 msgid "unaligned register"
 msgstr "hizalanmamış yazmaç"
 
-#: config/tc-i960.c:2273
+#: config/tc-i960.c:2278
 msgid "no such sfr in this architecture"
 msgstr "bu yapıda sfr yok"
 
-#: config/tc-i960.c:2311
+#: config/tc-i960.c:2316
 msgid "illegal literal"
 msgstr "geçersiz sabit"
 
 #. Should not happen: see block comment above
-#: config/tc-i960.c:2539
+#: config/tc-i960.c:2544
 #, c-format
 msgid "Trying to 'bal' to %s"
 msgstr "%s'e 'bal' yapılmaya çalışılıyor"
 
-#: config/tc-i960.c:2550
+#: config/tc-i960.c:2555
 msgid "Looks like a proc, but can't tell what kind.\n"
 msgstr "Alt yordama benziyor ama türü belirlenemedi.\n"
 
-#: config/tc-i960.c:2582
+#: config/tc-i960.c:2587
 msgid "should have 1 or 2 operands"
 msgstr "1 veya 2 işlenen olmalı"
 
-#: config/tc-i960.c:2591 config/tc-i960.c:2610
+#: config/tc-i960.c:2596 config/tc-i960.c:2615
 #, c-format
 msgid "Redefining leafproc %s"
 msgstr "leafproc %s yeniden tanımlanıyor"
 
-#: config/tc-i960.c:2641
+#: config/tc-i960.c:2646
 msgid "should have two operands"
 msgstr "iki işleneni olmalı"
 
-#: config/tc-i960.c:2651
+#: config/tc-i960.c:2656
 msgid "'entry_num' must be absolute number in [0,31]"
 msgstr "'entry_num' [0,31] aralığında kesin bir sayı olmalı"
 
-#: config/tc-i960.c:2660
+#: config/tc-i960.c:2665
 #, c-format
 msgid "Redefining entrynum for sysproc %s"
 msgstr "sysproc %s için entrynum yeniden tanımlanıyor"
 
-#: config/tc-i960.c:2764
+#: config/tc-i960.c:2769
 msgid "architecture of opcode conflicts with that of earlier instruction(s)"
 msgstr "opkod'un yapısı önceki işlem(ler)in yapısı ile çakışıyor"
 
-#: config/tc-i960.c:2785
+#: config/tc-i960.c:2790
 msgid "big endian mode is not supported"
 msgstr "büyük sonlu kip desteklenmiyor"
 
-#: config/tc-i960.c:2787
+#: config/tc-i960.c:2792
 #, c-format
 msgid "ignoring unrecognized .endian type `%s'"
 msgstr "bilinmeyen .endian türü `%s' yoksayıldı "
 
-#: config/tc-i960.c:3071
+#: config/tc-i960.c:3076
 #, c-format
 msgid "leafproc symbol '%s' undefined"
 msgstr "leafproc sembolü '%s' tanımlanmamış"
 
-#: config/tc-i960.c:3081
+#: config/tc-i960.c:3086
 #, c-format
 msgid "Warning: making leafproc entries %s and %s both global\n"
 msgstr "Uyarı: leafproc girdileri %s ve %s evrenselleştirildi\n"
 
-#: config/tc-i960.c:3190
+#: config/tc-i960.c:3191
 msgid "option --link-relax is only supported in b.out format"
 msgstr "--link-relax seçeneği yalnız b.out biçeminde destekleniyor"
 
@@ -4905,93 +5528,97 @@ msgstr "--link-relax seçeneği yalnız b.out biçeminde destekleniyor"
 msgid "Bad .section directive: want a,o,s,w,x,M,S,G,T in string"
 msgstr "Hatalı .section yönergesi: dizgede a,o,s,w,x,M,S,G,T olmalı"
 
-#: config/tc-ia64.c:1105
+#: config/tc-ia64.c:1119
 msgid "Unwind directive not followed by an instruction."
 msgstr "Geriye sarma yönergesi sonrasında bir işlem yok."
 
-#: config/tc-ia64.c:4563
+#: config/tc-ia64.c:4930
 msgid "Register name expected"
 msgstr "Yazmaç ismi beklendi"
 
-#: config/tc-ia64.c:4568 config/tc-ia64.c:4854
+#: config/tc-ia64.c:4935 config/tc-ia64.c:5251
 msgid "Comma expected"
 msgstr "Virgül beklendi"
 
-#: config/tc-ia64.c:4576
+#: config/tc-ia64.c:4943
 msgid "Register value annotation ignored"
 msgstr "Yazmaç değeri açıklaması yoksayıldı"
 
-#: config/tc-ia64.c:4600
+#: config/tc-ia64.c:4984
 msgid "Directive invalid within a bundle"
 msgstr "İşlem balya (bundle) içinde geçersiz"
 
-#: config/tc-ia64.c:4667
+#: config/tc-ia64.c:5077
 msgid "Missing predicate relation type"
 msgstr "Dayanak ilişki türü eksik"
 
-#: config/tc-ia64.c:4683
+#: config/tc-ia64.c:5083
 msgid "Unrecognized predicate relation type"
 msgstr "Bilinmeyen dayanak ilişki türü"
 
-#: config/tc-ia64.c:4703 config/tc-ia64.c:4728
+#: config/tc-ia64.c:5130
+msgid "Bad register range"
+msgstr "Hatalı yazmaç aralığı"
+
+#: config/tc-ia64.c:5139
 msgid "Predicate register expected"
 msgstr "Dayanak yazmacı beklendi"
 
-#: config/tc-ia64.c:4715
+#: config/tc-ia64.c:5144
 msgid "Duplicate predicate register ignored"
 msgstr "Çoklu dayanak yazmacı yoksayıldı"
 
-#: config/tc-ia64.c:4737
-msgid "Bad register range"
-msgstr "Hatalı yazmaç aralığı"
-
-#: config/tc-ia64.c:4765
+#: config/tc-ia64.c:5162
 msgid "Predicate source and target required"
 msgstr "Dayanak kaynak ve hedefi gerekli"
 
-#: config/tc-ia64.c:4767 config/tc-ia64.c:4779
+#: config/tc-ia64.c:5164 config/tc-ia64.c:5176
 msgid "Use of p0 is not valid in this context"
 msgstr "Bu bağlamda p0 kullanımı geçersiz"
 
-#: config/tc-ia64.c:4774
+#: config/tc-ia64.c:5171
 msgid "At least two PR arguments expected"
 msgstr "En az iki PR argümanı beklendi"
 
-#: config/tc-ia64.c:4788
+#: config/tc-ia64.c:5185
 msgid "At least one PR argument expected"
 msgstr "En az bir PR argümanı beklendi"
 
-#: config/tc-ia64.c:4824
+#: config/tc-ia64.c:5221
 #, c-format
 msgid "Inserting \"%s\" into entry hint table failed: %s"
 msgstr "Girdi ipucu tablosuna \"%s\" eklenmesi başarısız: %s"
 
 #. FIXME -- need 62-bit relocation type
-#: config/tc-ia64.c:5302
+#: config/tc-ia64.c:5697
 msgid "62-bit relocation not yet implemented"
 msgstr "62 bitlik yerdeğişim henüz desteklenmiyor"
 
 #. XXX technically, this is wrong: we should not be issuing warning
 #. messages until we're sure this instruction pattern is going to
 #. be used!
-#: config/tc-ia64.c:5375
+#: config/tc-ia64.c:5770
 msgid "lower 16 bits of mask ignored"
 msgstr "maskenin alt 16 biti yoksayıldı"
 
-#: config/tc-ia64.c:5939
+#: config/tc-ia64.c:6389
 msgid "Value truncated to 62 bits"
 msgstr "Değer 62 bite budandı"
 
-#: config/tc-ia64.c:6291
-msgid "Additional NOP may be necessary to workaround Itanium processor A/B step errata"
-msgstr "Itanium işlemcisi A/B adım hatasını bertaraf etmek için ek NOP gerekebilir"
+#. Give an error if a frag containing code is not aligned to a 16 byte
+#. boundary.
+#: config/tc-ia64.c:6527 config/tc-ia64.h:171
+#, fuzzy
+msgid "instruction address is not a multiple of 16"
+msgstr "4'ün katı olan bir adrese dallanmak gerekli"
 
-#: config/tc-ia64.c:6474
+#: config/tc-ia64.c:7049
 #, c-format
 msgid "Unrecognized option '-x%s'"
 msgstr "Bilinmeyen seçenek: '-x%s'"
 
-#: config/tc-ia64.c:6502
+#: config/tc-ia64.c:7077
+#, fuzzy
 msgid ""
 "IA-64 options:\n"
 "  --mconstant-gp\t  mark output file as using the constant-GP model\n"
@@ -5001,9 +5628,18 @@ msgid ""
 "\t\t\t  EF_IA_64_NOFUNCDESC_CONS_GP)\n"
 "  -milp32|-milp64|-mlp64|-mp64\tselect data model (default -mlp64)\n"
 "  -mle | -mbe\t\t  select little- or big-endian byte order (default -mle)\n"
-"  -x | -xexplicit\t  turn on dependency violation checking (default)\n"
-"  -xauto\t\t  automagically remove dependency violations\n"
+"  -munwind-check=[warning|error]\n"
+"\t\t\t  unwind directive check (default -munwind-check=warning)\n"
+"  -mhint.b=[ok|warning|error]\n"
+"\t\t\t  hint.b check (default -mhint.b=error)\n"
+"  -x | -xexplicit\t  turn on dependency violation checking\n"
+"  -xauto\t\t  automagically remove dependency violations (default)\n"
+"  -xnone\t\t  turn off dependency violation checking\n"
 "  -xdebug\t\t  debug dependency violation checker\n"
+"  -xdebugn\t\t  debug dependency violation checker but turn off\n"
+"\t\t\t  dependency violation checking\n"
+"  -xdebugx\t\t  debug dependency violation checker and turn on\n"
+"\t\t\t  dependency violation checking\n"
 msgstr ""
 "IA-64 seçenekleri:\n"
 "  --mconstant-gp\t  çıktı dosyasını sabit GP modelini kullanıyor olarak\n"
@@ -5017,250 +5653,352 @@ msgstr ""
 "  -xauto\t\t  bağımlılık ihlallerini otomatik kaldırır\n"
 "  -xdebug\t\t  bağımlılık ihlal kontrolünde hata ayıklar\n"
 
-#: config/tc-ia64.c:6521
+#: config/tc-ia64.c:7105
 msgid "--gstabs is not supported for ia64"
 msgstr "--gstabs ia64 için desteklenmiyor"
 
-#: config/tc-ia64.c:6824 config/tc-mips.c:1093
+#: config/tc-ia64.c:7408 config/tc-mips.c:1138
 msgid "Could not set architecture and machine"
 msgstr "Yapı ve makina ayarlanamadı"
 
-#: config/tc-ia64.c:6931
+#: config/tc-ia64.c:7524
 msgid "Explicit stops are ignored in auto mode"
 msgstr "Açık durmalar otomatik kipte yoksayılır"
 
-#: config/tc-ia64.c:6981
+#: config/tc-ia64.c:7576
 msgid "Found '{' after explicit switch to automatic mode"
 msgstr "Otomatik kipe açık girişten sonra '{' bulundu"
 
-#: config/tc-ia64.c:7428
+#: config/tc-ia64.c:8142
 #, c-format
 msgid "Unhandled dependency %s for %s (%s), note %d"
 msgstr "%2$s (%3$s) için çözümlenmemiş %1$s bağımlılığı, not: %4$d"
 
-#: config/tc-ia64.c:8704
+#: config/tc-ia64.c:9417
 #, c-format
 msgid "Unrecognized dependency specifier %d\n"
 msgstr "Bilinmeyen bağımlılık belirteci %d\n"
 
-#: config/tc-ia64.c:9506
+#: config/tc-ia64.c:10311
 msgid "Only the first path encountering the conflict is reported"
 msgstr "Sadece uyuşmazlığa ilk rastlanan yol bildirildi"
 
-#: config/tc-ia64.c:9509
+#: config/tc-ia64.c:10314
 msgid "This is the location of the conflicting usage"
 msgstr "Uyumsuz kullanımın yeri burası"
 
-#: config/tc-ia64.c:10778 read.c:1370 read.c:1976 read.c:2184 read.c:2795
+#: config/tc-ia64.c:11528
+#, fuzzy
+msgid "Can't add stop bit to mark end of instruction group"
+msgstr "sabit işleme sığmak için fazla büyük"
+
+#: config/tc-ia64.c:11628 read.c:1411 read.c:2176 read.c:2772
 msgid "expected symbol name"
 msgstr "sembol adı beklendi."
 
-#: config/tc-ia64.c:10788 read.c:1380 read.c:2194 read.c:2805 stabs.c:478
+#: config/tc-ia64.c:11638 read.c:2186 read.c:2782 stabs.c:471
 #, c-format
 msgid "expected comma after \"%s\""
 msgstr "\"%s\"dan sonra virgül beklendi"
 
-#: config/tc-ia64.c:10829
+#: config/tc-ia64.c:11680
 #, c-format
 msgid "`%s' is already the alias of %s `%s'"
 msgstr "\"%s\" sembolü zaten %s `%s' rumuzu olarak tanımlanmış"
 
-#: config/tc-ia64.c:10839
+#: config/tc-ia64.c:11690
 #, c-format
 msgid "%s `%s' already has an alias `%s'"
 msgstr "%s `%s'un zaten `%s' rumuzu var"
 
-#: config/tc-ia64.c:10850
+#: config/tc-ia64.c:11701
 #, c-format
 msgid "inserting \"%s\" into %s alias hash table failed: %s"
 msgstr "%2$s rumuz hash tablosuna \"%1$s\" eklenmesi başarısız: %3$s"
 
-#: config/tc-ia64.c:10858
+#: config/tc-ia64.c:11709
 #, c-format
 msgid "inserting \"%s\" into %s name hash table failed: %s"
 msgstr "%2$s isim hash tablosuna \"%1$s\" eklenmesi başarısız: %3$s"
 
-#: config/tc-ia64.c:10877
+#: config/tc-ia64.c:11728
 #, c-format
 msgid "symbol `%s' aliased to `%s' is not used"
 msgstr "`%2$s' rumuzlu `%1$s' sembolü kullanılmamış"
 
-#: config/tc-ia64.c:10899
+#: config/tc-ia64.c:11750
 #, c-format
 msgid "section `%s' aliased to `%s' is not used"
 msgstr "`%2$s' rumuzlu `%1$s' bölümü kullanılmamış"
 
-#: config/tc-ip2k.c:125
+#: config/tc-ip2k.c:123
+#, c-format
 msgid "IP2K specific command line options:\n"
 msgstr "IP2K'ya özgü komut satırı seçenekleri:\n"
 
-#: config/tc-ip2k.c:126
+#: config/tc-ip2k.c:124
+#, c-format
 msgid "  -mip2022               restrict to IP2022 insns \n"
 msgstr "  -mip2022               yalnız IP2022 işlemlerini kullanır\n"
 
-#: config/tc-ip2k.c:127
+#: config/tc-ip2k.c:125
+#, c-format
 msgid "  -mip2022ext            permit extended IP2022 insn\n"
 msgstr "  -mip2022ext            geniÅŸletilmiÅŸ IP2022 iÅŸlemlerine izin verir\n"
 
-#: config/tc-ip2k.c:248
+#: config/tc-ip2k.c:246
 msgid "md_pcrel_from\n"
 msgstr "md_pcrel_from\n"
 
 #. Pretend that we do not recognise this option.
-#: config/tc-m32r.c:233
+#: config/tc-m32r.c:334
 msgid "Unrecognised option: -hidden"
 msgstr "Bilinmeyen seçenek: -hidden"
 
-#: config/tc-m32r.c:267
+#: config/tc-m32r.c:361 config/tc-sparc.c:596
+msgid "Unrecognized option following -K"
+msgstr "-K'dan sonra bilinmeyen seçenek"
+
+#: config/tc-m32r.c:377
+#, c-format
 msgid " M32R specific command line options:\n"
 msgstr " M32R'a özgü komut satırı seçenekleri:\n"
 
-#: config/tc-m32r.c:269
+#: config/tc-m32r.c:379
+#, c-format
 msgid "  -m32r                   disable support for the m32rx instruction set\n"
 msgstr "  -m32r                   m32rx işlem kümesi için desteği etkisizleştirir\n"
 
-#: config/tc-m32r.c:271
+#: config/tc-m32r.c:381
+#, c-format
 msgid "  -m32rx                  support the extended m32rx instruction set\n"
 msgstr "  -m32rx                  genişletilmiş m32rx işlem kümesini destekler\n"
 
-#: config/tc-m32r.c:273
-msgid "  -O                      try to combine instructions in parallel\n"
+#: config/tc-m32r.c:383
+#, fuzzy, c-format
+msgid "  -m32r2                  support the extended m32r2 instruction set\n"
+msgstr "  -m32rx                  genişletilmiş m32rx işlem kümesini destekler\n"
+
+#: config/tc-m32r.c:385
+#, c-format
+msgid "  -EL,-little             produce little endian code and data\n"
+msgstr ""
+
+#: config/tc-m32r.c:387
+#, fuzzy, c-format
+msgid "  -EB,-big                produce big endian code and data\n"
+msgstr "  -EB                     büyük-sonlu bir cpu için kod çevrimi yapar\n"
+
+#: config/tc-m32r.c:389
+#, fuzzy, c-format
+msgid "  -parallel               try to combine instructions in parallel\n"
+msgstr "  -O                      işlemleri paralel birleştirmeye çalışır\n"
+
+#: config/tc-m32r.c:391
+#, fuzzy, c-format
+msgid "  -no-parallel            disable -parallel\n"
+msgstr "  -mrelax                 bağlayıcı tarafından gevşetilebilen kod üretir\n"
+
+#: config/tc-m32r.c:393
+#, fuzzy, c-format
+msgid "  -no-bitinst             disallow the M32R2's extended bit-field instructions\n"
+msgstr "  -m32rx                  genişletilmiş m32rx işlem kümesini destekler\n"
+
+#: config/tc-m32r.c:395
+#, fuzzy, c-format
+msgid "  -O                      try to optimize code.  Implies -parallel\n"
 msgstr "  -O                      işlemleri paralel birleştirmeye çalışır\n"
 
-#: config/tc-m32r.c:276
+#: config/tc-m32r.c:398
+#, c-format
 msgid "  -warn-explicit-parallel-conflicts     warn when parallel instructions\n"
 msgstr "  -warn-explicit-parallel-conflicts     paralel işlemlerde uyarır\n"
 
-#: config/tc-m32r.c:278
-msgid "                                         violate contraints\n"
+#: config/tc-m32r.c:400
+#, fuzzy, c-format
+msgid "                                         might violate contraints\n"
 msgstr "                                         sınır ihlallerinde\n"
 
-#: config/tc-m32r.c:280
+#: config/tc-m32r.c:402
+#, c-format
 msgid "  -no-warn-explicit-parallel-conflicts  do not warn when parallel\n"
 msgstr "  -no-warn-explicit-parallel-conflicts  paralel olduÄŸu zaman uyarmaz\n"
 
-#: config/tc-m32r.c:282
-msgid "                                         instructions violate contraints\n"
+#: config/tc-m32r.c:404
+#, fuzzy, c-format
+msgid "                                         instructions might violate contraints\n"
 msgstr "                                         sınır ihlallerinde\n"
 
-#: config/tc-m32r.c:284
+#: config/tc-m32r.c:406
+#, c-format
 msgid "  -Wp                     synonym for -warn-explicit-parallel-conflicts\n"
 msgstr "  -Wp                     -warn-explicit-parallel-conflicts ile aynı\n"
 
-#: config/tc-m32r.c:286
+#: config/tc-m32r.c:408
+#, c-format
 msgid "  -Wnp                    synonym for -no-warn-explicit-parallel-conflicts\n"
 msgstr "  -Wnp                    -no-warn-explicit-parallel-conflicts ile aynı\n"
 
-#: config/tc-m32r.c:289
+#: config/tc-m32r.c:410
+#, fuzzy, c-format
+msgid "  -ignore-parallel-conflicts            do not check parallel instructions\n"
+msgstr "  -warn-explicit-parallel-conflicts     paralel işlemlerde uyarır\n"
+
+#: config/tc-m32r.c:412
+#, fuzzy, c-format
+msgid "                                         fo contraint violations\n"
+msgstr "                                         sınır ihlallerinde\n"
+
+#: config/tc-m32r.c:414
+#, fuzzy, c-format
+msgid "  -no-ignore-parallel-conflicts         check parallel instructions for\n"
+msgstr "  -warn-explicit-parallel-conflicts     paralel işlemlerde uyarır\n"
+
+#: config/tc-m32r.c:416
+#, fuzzy, c-format
+msgid "                                         contraint violations\n"
+msgstr "                                         sınır ihlallerinde\n"
+
+#: config/tc-m32r.c:418
+#, fuzzy, c-format
+msgid "  -Ip                     synonym for -ignore-parallel-conflicts\n"
+msgstr "  -Wp                     -warn-explicit-parallel-conflicts ile aynı\n"
+
+#: config/tc-m32r.c:420
+#, fuzzy, c-format
+msgid "  -nIp                    synonym for -no-ignore-parallel-conflicts\n"
+msgstr "  -Wnp                    -no-warn-explicit-parallel-conflicts ile aynı\n"
+
+#: config/tc-m32r.c:423
+#, c-format
 msgid "  -warn-unmatched-high    warn when an (s)high reloc has no matching low reloc\n"
 msgstr ""
 "  -warn-unmatched-high    üst yerdeğişimin eşleşen alt yerdeğişimi olmadığı\n"
 "                          zaman uyarır\n"
 
-#: config/tc-m32r.c:291
+#: config/tc-m32r.c:425
+#, c-format
 msgid "  -no-warn-unmatched-high do not warn about missing low relocs\n"
 msgstr "  -no-warn-unmatched-high eksik alt yerdeğişimler için uyarmaz\n"
 
-#: config/tc-m32r.c:293
+#: config/tc-m32r.c:427
+#, c-format
 msgid "  -Wuh                    synonym for -warn-unmatched-high\n"
 msgstr "  -Wuh                    -warn-unmatched-high ile aynı\n"
 
-#: config/tc-m32r.c:295
+#: config/tc-m32r.c:429
+#, c-format
 msgid "  -Wnuh                   synonym for -no-warn-unmatched-high\n"
 msgstr "  -Wnuh                   -no-warn-unmatched-high ile aynı\n"
 
-#: config/tc-m32r.c:299
-msgid "  -relax                 create linker relaxable code\n"
-msgstr "  -relax                 bağlayıcı tarafından gevşetilebilen kod üretir\n"
-
-#: config/tc-m32r.c:301
-msgid "  -cpu-desc              provide runtime cpu description file\n"
-msgstr "  -cpu-desc              çalışma zamanı cpu tasvir dosyası üretir\n"
+#: config/tc-m32r.c:432
+#, fuzzy, c-format
+msgid "  -KPIC                   generate PIC\n"
+msgstr "  -Q                      yoksayıldı\n"
 
-#: config/tc-m32r.c:700
-msgid "Instructions write to the same destination register."
+#: config/tc-m32r.c:892
+#, fuzzy
+msgid "instructions write to the same destination register."
 msgstr "İşlemler aynı hedef yazmacına yazıyor."
 
-#: config/tc-m32r.c:708
+#: config/tc-m32r.c:900
 msgid "Instructions do not use parallel execution pipelines."
 msgstr "İşlemler paralel çalışma yolları kullanmıyor."
 
-#: config/tc-m32r.c:715
+#: config/tc-m32r.c:908
 msgid "Instructions share the same execution pipeline"
 msgstr "İşlemler aynı çalışma yolunu paylaşıyor."
 
-#: config/tc-m32r.c:791 config/tc-m32r.c:887
+#: config/tc-m32r.c:984 config/tc-m32r.c:1098
 #, c-format
 msgid "not a 16 bit instruction '%s'"
 msgstr "'%s' 16bitlik iÅŸlem deÄŸil"
 
-#: config/tc-m32r.c:798 config/tc-m32r.c:894 config/tc-m32r.c:1050
+#: config/tc-m32r.c:996 config/tc-m32r.c:1110 config/tc-m32r.c:1295
+#, fuzzy, c-format
+msgid "instruction '%s' is for the M32R2 only"
+msgstr "'%s' işlemi yalnız M32RX için geçerli"
+
+#: config/tc-m32r.c:1009 config/tc-m32r.c:1123 config/tc-m32r.c:1308
 #, c-format
 msgid "unknown instruction '%s'"
 msgstr "bilinmeyen iÅŸlem '%s'"
 
-#: config/tc-m32r.c:807 config/tc-m32r.c:901 config/tc-m32r.c:1057
+#: config/tc-m32r.c:1018 config/tc-m32r.c:1130 config/tc-m32r.c:1315
 #, c-format
 msgid "instruction '%s' is for the M32RX only"
 msgstr "'%s' işlemi yalnız M32RX için geçerli"
 
-#: config/tc-m32r.c:816 config/tc-m32r.c:910
+#: config/tc-m32r.c:1027 config/tc-m32r.c:1139
 #, c-format
 msgid "instruction '%s' cannot be executed in parallel."
 msgstr "'%s' işlemi paralel çalıştırılamaz."
 
-#: config/tc-m32r.c:871 config/tc-m32r.c:935 config/tc-m32r.c:1107
+#: config/tc-m32r.c:1082 config/tc-m32r.c:1164 config/tc-m32r.c:1372
 msgid "internal error: lookup/get operands failed"
 msgstr "iç hata: sorgu/al işlenenleri başarısız"
 
-#: config/tc-m32r.c:920
+#: config/tc-m32r.c:1149
 #, c-format
 msgid "'%s': only the NOP instruction can be issued in parallel on the m32r"
 msgstr "'%s': m32r üzerinde yalnız NOP işlemi paralel çalıştırılabilir"
 
-#: config/tc-m32r.c:949
+#: config/tc-m32r.c:1178
 #, c-format
 msgid "%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"
 msgstr "%s: 1. işleminin çıktısı 2. işleminin girdisi ile aynı - bu istendi mi?"
 
-#: config/tc-m32r.c:953
+#: config/tc-m32r.c:1182
 #, c-format
 msgid "%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"
 msgstr "%s: 2. işleminin çıktısı 1. işleminin girdisi ile aynı - bu istendi mi?"
 
-#: config/tc-m32r.c:1267 config/tc-ppc.c:1732 config/tc-ppc.c:4263
+#: config/tc-m32r.c:1551 config/tc-ppc.c:1758 config/tc-ppc.c:4350
 msgid "Expected comma after symbol-name: rest of line ignored."
 msgstr "sembol isminden sonra virgül beklendi: satırın gerisi yoksayıldı."
 
-#: config/tc-m32r.c:1277
+#: config/tc-m32r.c:1561
 #, c-format
 msgid ".SCOMMon length (%ld.) <0! Ignored."
 msgstr ".SCOMMon uzunluğu (%ld.) <0! Yoksayıldı."
 
-#: config/tc-m32r.c:1291 config/tc-ppc.c:1754 config/tc-ppc.c:2899
-#: config/tc-ppc.c:4287
+#: config/tc-m32r.c:1575 config/tc-ppc.c:1780 config/tc-ppc.c:2937
+#: config/tc-ppc.c:4374
 msgid "ignoring bad alignment"
 msgstr "hatalı hizalama yoksayıldı"
 
-#: config/tc-m32r.c:1303 config/tc-ppc.c:1791 config/tc-v850.c:335
+#: config/tc-m32r.c:1587 config/tc-ppc.c:1817 config/tc-v850.c:335
 msgid "Common alignment not a power of 2"
 msgstr "Ortak hizalama 2'nin kuvveti deÄŸil"
 
-#: config/tc-m32r.c:1318 config/tc-ppc.c:1765 config/tc-ppc.c:4299
+#: config/tc-m32r.c:1602 config/tc-ppc.c:1791 config/tc-ppc.c:4386
 #, c-format
 msgid "Ignoring attempt to re-define symbol `%s'."
 msgstr "`%s' sembolünü yeniden tanımlama denemesi yoksayıldı."
 
-#: config/tc-m32r.c:1327
+#: config/tc-m32r.c:1611
 #, c-format
 msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ".scomm \"%s\" uzunluÄŸu zaten %ld. %ld'e deÄŸiÅŸtirilmedi."
 
-#: config/tc-m32r.c:1808
+#: config/tc-m32r.c:1839
+msgid "Addend to unresolved symbol not on word boundary."
+msgstr "Word sınırında olmayan çözümlenmemiş sembole addend eklendi."
+
+#: config/tc-m32r.c:1988 config/tc-m32r.c:2038 config/tc-sh.c:747
+msgid "Invalid PIC expression."
+msgstr "geçersiz PIC ifadesi"
+
+#: config/tc-m32r.c:2129
 msgid "Unmatched high/shigh reloc"
 msgstr "EÅŸlenmemiÅŸ high/shigh yerdeÄŸiÅŸimi"
 
-#: config/tc-m68hc11.c:372
+#: config/tc-m32r.c:2380 config/tc-sparc.c:3525
+#, c-format
+msgid "internal error: can't export reloc type %d (`%s')"
+msgstr "iç hata: %d yerdeğişim türü ihraç edilemedi (`%s')"
+
+#: config/tc-m68hc11.c:369
 #, c-format
 msgid ""
 "Motorola 68HC11/68HC12/68HCS12 options:\n"
@@ -5297,55 +6035,56 @@ msgstr ""
 "  --generate-example      her işlem için bir örnek oluşturur\n"
 "                          (test amaçlı kullanılır)\n"
 
-#: config/tc-m68hc11.c:418
+#: config/tc-m68hc11.c:415
 #, c-format
 msgid "Default target `%s' is not supported."
 msgstr "Öntanımlı `%s' hedefi desteklenmiyor."
 
 #. Dump the opcode statistics table.
-#: config/tc-m68hc11.c:437
+#: config/tc-m68hc11.c:433
+#, c-format
 msgid "Name   # Modes  Min ops  Max ops  Modes mask  # Used\n"
 msgstr "Ä°sim   # Kipler Min op   Maks op  Kip maskesi # Kull\n"
 
-#: config/tc-m68hc11.c:505
+#: config/tc-m68hc11.c:499
 #, c-format
 msgid "Option `%s' is not recognized."
 msgstr "`%s' seçeneği bilinmiyor."
 
-#: config/tc-m68hc11.c:737
+#: config/tc-m68hc11.c:721
 msgid "#<imm8>"
 msgstr "#<imm8>"
 
-#: config/tc-m68hc11.c:746
+#: config/tc-m68hc11.c:730
 msgid "#<imm16>"
 msgstr "#<imm16>"
 
-#: config/tc-m68hc11.c:755 config/tc-m68hc11.c:764
+#: config/tc-m68hc11.c:739 config/tc-m68hc11.c:748
 msgid "<imm8>,X"
 msgstr "<imm8>,X"
 
-#: config/tc-m68hc11.c:791
+#: config/tc-m68hc11.c:775
 msgid "*<abs8>"
 msgstr "*<abs8>"
 
-#: config/tc-m68hc11.c:803
+#: config/tc-m68hc11.c:787
 msgid "#<mask>"
 msgstr "#<mask>"
 
-#: config/tc-m68hc11.c:813
+#: config/tc-m68hc11.c:797
 #, c-format
 msgid "symbol%d"
 msgstr "sembol%d"
 
-#: config/tc-m68hc11.c:815
+#: config/tc-m68hc11.c:799
 msgid "<abs>"
 msgstr "<abs>"
 
-#: config/tc-m68hc11.c:834
+#: config/tc-m68hc11.c:818
 msgid "<label>"
 msgstr "<label>"
 
-#: config/tc-m68hc11.c:850
+#: config/tc-m68hc11.c:834
 #, c-format
 msgid ""
 "# Example of `%s' instructions\n"
@@ -5356,609 +6095,669 @@ msgstr ""
 "\t.sect .text\n"
 "_start:\n"
 
-#: config/tc-m68hc11.c:898
+#: config/tc-m68hc11.c:881
 #, c-format
 msgid "Instruction `%s' is not recognized."
 msgstr "`%s' iÅŸlemi bilinmiyor."
 
-#: config/tc-m68hc11.c:903
+#: config/tc-m68hc11.c:886
 #, c-format
 msgid "Instruction formats for `%s':"
 msgstr "`%s' için işlem biçemleri:"
 
-#: config/tc-m68hc11.c:1038
+#: config/tc-m68hc11.c:1016
 #, c-format
 msgid "Immediate operand is not allowed for operand %d."
 msgstr "%d işleneni için şimdiki işlenen kullanılamaz."
 
-#: config/tc-m68hc11.c:1082
+#: config/tc-m68hc11.c:1060
 msgid "Indirect indexed addressing is not valid for 68HC11."
 msgstr "Dolaylı indeksli adresleme, 68HC11 için geçersiz."
 
-#: config/tc-m68hc11.c:1102
+#: config/tc-m68hc11.c:1080
 msgid "Spurious `,' or bad indirect register addressing mode."
 msgstr "Gereksiz `,' veya hatalı dolaylı yazmaç adreslemesi kipi."
 
-#: config/tc-m68hc11.c:1124
+#: config/tc-m68hc11.c:1102
 msgid "Missing second register or offset for indexed-indirect mode."
 msgstr "İkinci yazmaç veya indeksli-dolaylı kip için göreli konum eksik."
 
-#: config/tc-m68hc11.c:1134
+#: config/tc-m68hc11.c:1112
 msgid "Missing second register for indexed-indirect mode."
 msgstr "İndeksli-dolaylı kip için ikinci yazmaç eksik"
 
-#: config/tc-m68hc11.c:1150
+#: config/tc-m68hc11.c:1128
 msgid "Missing `]' to close indexed-indirect mode."
 msgstr "İndeksli-dolaylı kip için `]' eksik."
 
-#: config/tc-m68hc11.c:1195
+#: config/tc-m68hc11.c:1173
 msgid "Illegal operand."
 msgstr "Geçersiz işlenen."
 
-#: config/tc-m68hc11.c:1200
+#: config/tc-m68hc11.c:1178
 msgid "Missing operand."
 msgstr "Eksik iÅŸlenen."
 
-#: config/tc-m68hc11.c:1253
+#: config/tc-m68hc11.c:1231
 msgid "Pre-increment mode is not valid for 68HC11"
 msgstr "Ön-arttırma kipi 68HC11 için geçerli değil"
 
-#: config/tc-m68hc11.c:1266
+#: config/tc-m68hc11.c:1244
 msgid "Wrong register in register indirect mode."
 msgstr "Dolaylı yazmaç kipinde yanlış yazmaç."
 
-#: config/tc-m68hc11.c:1274
+#: config/tc-m68hc11.c:1252
 msgid "Missing `]' to close register indirect operand."
 msgstr "dolaylı yazmaç işleneni kapatmak için eksik `]'."
 
-#: config/tc-m68hc11.c:1294
+#: config/tc-m68hc11.c:1272
 msgid "Post-decrement mode is not valid for 68HC11."
 msgstr "Son-eksiltme kipi 68HC11 için geçersiz."
 
-#: config/tc-m68hc11.c:1302
+#: config/tc-m68hc11.c:1280
 msgid "Post-increment mode is not valid for 68HC11."
 msgstr "Son-arttırma kipi, 68HC11 için geçersiz."
 
-#: config/tc-m68hc11.c:1320
+#: config/tc-m68hc11.c:1298
 msgid "Invalid indexed indirect mode."
 msgstr "Geçersiz indeksli dolaylı kip."
 
-#: config/tc-m68hc11.c:1417
+#: config/tc-m68hc11.c:1390
 #, c-format
 msgid "Trap id `%ld' is out of range."
 msgstr "Tuzak kimliği `%ld' kapsam dışı."
 
-#: config/tc-m68hc11.c:1421
+#: config/tc-m68hc11.c:1394
 msgid "Trap id must be within [0x30..0x39] or [0x40..0xff]."
 msgstr "Tuzak kimliği [0x30..0x39] veya [0x40..0xff] aralığında olmalı."
 
-#: config/tc-m68hc11.c:1428
+#: config/tc-m68hc11.c:1401
 #, c-format
 msgid "Operand out of 8-bit range: `%ld'."
 msgstr "İşlenen 8bit aralığının dışında: `%ld'."
 
-#: config/tc-m68hc11.c:1435
+#: config/tc-m68hc11.c:1408
 msgid "The trap id must be a constant."
 msgstr "Tuzak kimliği sabit olmalı."
 
-#: config/tc-m68hc11.c:1470
+#: config/tc-m68hc11.c:1443
 #, c-format
 msgid "Operand `%x' not recognized in fixup8."
 msgstr "`%x' iÅŸleneni fixup8'de bilinmiyor."
 
-#: config/tc-m68hc11.c:1490 config/tc-m68hc11.c:1542
+#: config/tc-m68hc11.c:1460 config/tc-m68hc11.c:1509
 #, c-format
 msgid "Operand out of 16-bit range: `%ld'."
 msgstr "İşlenen 16 bit aralığının dışında: `%ld'."
 
-#: config/tc-m68hc11.c:1522 config/tc-m68hc11.c:1558
+#: config/tc-m68hc11.c:1492 config/tc-m68hc11.c:1525
 #, c-format
 msgid "Operand `%x' not recognized in fixup16."
 msgstr "`%x' iÅŸleneni fixup16'da bilinmiyor."
 
-#: config/tc-m68hc11.c:1576
+#: config/tc-m68hc11.c:1542
 #, c-format
 msgid "Unexpected branch conversion with `%x'"
 msgstr "`%x' ile beklenmeyen dal çevrimi"
 
-#: config/tc-m68hc11.c:1671 config/tc-m68hc11.c:1812
+#: config/tc-m68hc11.c:1633 config/tc-m68hc11.c:1771
 #, c-format
 msgid "Operand out of range for a relative branch: `%ld'"
 msgstr "Göreli dal için işlenen kapsam dışı: `%ld'"
 
-#: config/tc-m68hc11.c:1780
+#: config/tc-m68hc11.c:1739
 msgid "Invalid register for dbcc/tbcc instruction."
 msgstr "dbcc/tbcc işlemi için geçersiz yazmaç."
 
-#: config/tc-m68hc11.c:1871
+#: config/tc-m68hc11.c:1827
 #, c-format
 msgid "Increment/decrement value is out of range: `%ld'."
 msgstr "Artırma/eksiltme değeri kapsam dışı: `%ld'."
 
-#: config/tc-m68hc11.c:1882
+#: config/tc-m68hc11.c:1838
 msgid "Expecting a register."
 msgstr "Yazmaç beklendi."
 
-#: config/tc-m68hc11.c:1897
+#: config/tc-m68hc11.c:1853
 msgid "Invalid register for post/pre increment."
 msgstr "Son/ön arttırma için geçersiz yazmaç."
 
-#: config/tc-m68hc11.c:1927
+#: config/tc-m68hc11.c:1883
 msgid "Invalid register."
 msgstr "Geçersiz yazmaç."
 
-#: config/tc-m68hc11.c:1934
+#: config/tc-m68hc11.c:1890
 #, c-format
 msgid "Offset out of 16-bit range: %ld."
 msgstr "Göreli konum 16 bitlik aralığın dışında: %ld."
 
-#: config/tc-m68hc11.c:1939
+#: config/tc-m68hc11.c:1895
 #, c-format
 msgid "Offset out of 5-bit range for movw/movb insn: %ld."
 msgstr "Göreli konum, movw/movb işlemi için 5 bitlik aralığın dışında: %ld"
 
-#: config/tc-m68hc11.c:2020
+#: config/tc-m68hc11.c:2001
 msgid "Expecting register D for indexed indirect mode."
 msgstr "İndeksli dolaylı kip için D yazmacı beklendi."
 
-#: config/tc-m68hc11.c:2022
+#: config/tc-m68hc11.c:2003
 msgid "Indexed indirect mode is not allowed for movb/movw."
 msgstr "İndeksli dolaylı kip movb/movw için geçersiz."
 
-#: config/tc-m68hc11.c:2039
+#: config/tc-m68hc11.c:2020
 msgid "Invalid accumulator register."
 msgstr "Geçersiz biriktirici yazmaç."
 
-#: config/tc-m68hc11.c:2064
+#: config/tc-m68hc11.c:2045
 msgid "Invalid indexed register."
 msgstr "Geçersiz indeksli yazmaç."
 
-#: config/tc-m68hc11.c:2072
+#: config/tc-m68hc11.c:2053
 msgid "Addressing mode not implemented yet."
 msgstr "Adresleme kipi henüz desteklenmiyor."
 
-#: config/tc-m68hc11.c:2087
+#: config/tc-m68hc11.c:2066
 msgid "Invalid source register for this instruction, use 'tfr'."
 msgstr "Bu işlem için geçersiz kaynak yazmacı, 'tfr' kullanın."
 
-#: config/tc-m68hc11.c:2089
+#: config/tc-m68hc11.c:2068
 msgid "Invalid source register."
 msgstr "Geçersiz kaynak yazmacı."
 
-#: config/tc-m68hc11.c:2094
+#: config/tc-m68hc11.c:2073
 msgid "Invalid destination register for this instruction, use 'tfr'."
 msgstr "Bu işlem için geçersiz hedef yazmacı, 'tfr' kullanın."
 
-#: config/tc-m68hc11.c:2096
+#: config/tc-m68hc11.c:2075
 msgid "Invalid destination register."
 msgstr "Geçersiz hedef yazmacı."
 
-#: config/tc-m68hc11.c:2194
+#: config/tc-m68hc11.c:2171
 msgid "Invalid indexed register, expecting register X."
 msgstr "Geçersiz indeksli yazmaç, X yazmacı beklendi."
 
-#: config/tc-m68hc11.c:2196
+#: config/tc-m68hc11.c:2173
 msgid "Invalid indexed register, expecting register Y."
 msgstr "Geçersiz indeksli yazmaç, Y yazmacı beklendi."
 
-#: config/tc-m68hc11.c:2508
+#: config/tc-m68hc11.c:2479
 msgid "No instruction or missing opcode."
 msgstr "Ä°ÅŸlem yok veya eksik opkod."
 
-#: config/tc-m68hc11.c:2573
+#: config/tc-m68hc11.c:2544
 #, c-format
 msgid "Opcode `%s' is not recognized."
 msgstr "`%s' opkodu bilinmiyor."
 
-#: config/tc-m68hc11.c:2595
+#: config/tc-m68hc11.c:2566
 #, c-format
 msgid "Garbage at end of instruction: `%s'."
 msgstr "Ä°ÅŸlemin sonunda bozukluk: `%s'."
 
-#: config/tc-m68hc11.c:2618
+#: config/tc-m68hc11.c:2589
 #, c-format
 msgid "Invalid operand for `%s'"
 msgstr "`%s' için geçersiz işlenen"
 
-#: config/tc-m68hc11.c:2670
+#: config/tc-m68hc11.c:2640
 #, c-format
 msgid "Invalid mode: %s\n"
 msgstr "Geçersiz kip: %s\n"
 
-#: config/tc-m68hc11.c:2732
+#: config/tc-m68hc11.c:2700
 msgid "bad .relax format"
 msgstr "hatalı .relax biçemi"
 
-#: config/tc-m68hc11.c:2779
+#: config/tc-m68hc11.c:2744
 #, c-format
 msgid "Relocation %d is not supported by object file format."
 msgstr "%d yerdeğişimi nesne dosyası biçeminde desteklenmiyor."
 
-#: config/tc-m68hc11.c:3065
+#: config/tc-m68hc11.c:3023
 msgid "bra or bsr with undefined symbol."
 msgstr "Tanımsız sembollü bra veya bsr."
 
-#: config/tc-m68hc11.c:3168 config/tc-m68hc11.c:3225
+#: config/tc-m68hc11.c:3126 config/tc-m68hc11.c:3183
 #, c-format
 msgid "Subtype %d is not recognized."
 msgstr "%d alttürü bilinmiyor."
 
-#: config/tc-m68hc11.c:3289
+#: config/tc-m68hc11.c:3242
 msgid "Expression too complex."
 msgstr "İfade fazla karmaşık."
 
-#: config/tc-m68hc11.c:3322
+#: config/tc-m68hc11.c:3275
 msgid "Value out of 16-bit range."
 msgstr "Değer 16 bit aralığının dışında."
 
-#: config/tc-m68hc11.c:3346
+#: config/tc-m68hc11.c:3293
 #, c-format
 msgid "Value %ld too large for 8-bit PC-relative branch."
 msgstr "%ld değeri, 8 bitlik PC-göreli dal için fazla büyük."
 
-#: config/tc-m68hc11.c:3353
+#: config/tc-m68hc11.c:3300
 #, c-format
 msgid "Auto increment/decrement offset '%ld' is out of range."
 msgstr "Otomatik arttırma/eksiltme görecesi '%ld', kapsam dışı."
 
-#: config/tc-m68hc11.c:3371
+#: config/tc-m68hc11.c:3313
+#, fuzzy, c-format
+msgid "Offset out of 5-bit range for movw/movb insn: %ld"
+msgstr "Göreli konum, movw/movb işlemi için 5 bitlik aralığın dışında: %ld"
+
+#: config/tc-m68hc11.c:3329
 #, c-format
 msgid "Line %d: unknown relocation type: 0x%x."
 msgstr "Satır %d: bilinmeyen yerdeğişim türü: 0x%x"
 
-#: config/tc-m68k.c:678
+#: config/tc-m68k.c:693
+#, fuzzy
+msgid "no matching ColdFire architectures found"
+msgstr "bu yapıda sfr yok"
+
+#: config/tc-m68k.c:707
+msgid " or "
+msgstr ""
+
+#: config/tc-m68k.c:712
+msgid ", or "
+msgstr ""
+
+#: config/tc-m68k.c:729
+msgid ", or aliases"
+msgstr ""
+
+#: config/tc-m68k.c:753 config/tc-m68k.c:4765 config/tc-m68k.c:5156
+msgid "Tried to convert PC relative branch to absolute jump"
+msgstr ""
+
+#: config/tc-m68k.c:760 config/tc-m68k.c:4755
+msgid "Tried to convert PC relative BSR to absolute JSR"
+msgstr ""
+
+#: config/tc-m68k.c:765
 msgid "Unknown PC relative instruction"
 msgstr "Bilinmeyen PC göreli işlemi"
 
-#: config/tc-m68k.c:817
+#: config/tc-m68k.c:897
 #, c-format
 msgid "Can not do %d byte pc-relative relocation"
 msgstr "%d baytlık pc-göreli yerdeğişim yapılamaz"
 
-#: config/tc-m68k.c:819
+#: config/tc-m68k.c:899
 #, c-format
 msgid "Can not do %d byte pc-relative pic relocation"
 msgstr "%d baytlık pc-göreli pic yerdeğişimi yapılamaz"
 
-#: config/tc-m68k.c:824
+#: config/tc-m68k.c:904
 #, c-format
 msgid "Can not do %d byte relocation"
 msgstr "%d baytlık yerdeğişim yapılamaz"
 
-#: config/tc-m68k.c:826
+#: config/tc-m68k.c:906
 #, c-format
 msgid "Can not do %d byte pic relocation"
 msgstr "%d baytlık pic yerdeğişimi yapılamaz"
 
-#: config/tc-m68k.c:894
+#: config/tc-m68k.c:971
 #, c-format
 msgid "Unable to produce reloc against symbol '%s'"
 msgstr "'%s' sembolüne yerdeğişim üretilemedi"
 
-#: config/tc-m68k.c:938 config/tc-mips.c:13321 config/tc-vax.c:3441
+#: config/tc-m68k.c:1015 config/tc-vax.c:3456
 #, c-format
 msgid "Cannot make %s relocation PC relative"
 msgstr "%s yerdeğişimi PC göreli yapılamaz"
 
-#: config/tc-m68k.c:1031 config/tc-tahoe.c:1495 config/tc-vax.c:1889
+#: config/tc-m68k.c:1107 config/tc-tahoe.c:1495 config/tc-vax.c:1895
 msgid "No operator"
 msgstr "Ä°ÅŸlemimi yok"
 
-#: config/tc-m68k.c:1061 config/tc-tahoe.c:1512 config/tc-vax.c:1906
+#: config/tc-m68k.c:1137 config/tc-tahoe.c:1512 config/tc-vax.c:1912
 msgid "Unknown operator"
 msgstr "Bilinmeyen operatör"
 
-#: config/tc-m68k.c:1836
+#: config/tc-m68k.c:1990
 msgid "invalid instruction for this architecture; needs "
 msgstr "bu yapı için geçersiz işlem; gereken: "
 
-#: config/tc-m68k.c:1841
+#: config/tc-m68k.c:1996
+msgid "ColdFire ISA_A"
+msgstr ""
+
+#: config/tc-m68k.c:2004
+msgid "ColdFire hardware divide"
+msgstr ""
+
+#: config/tc-m68k.c:2012
+msgid "ColdFire ISA_A+"
+msgstr ""
+
+#: config/tc-m68k.c:2020
+msgid "ColdFire ISA_B"
+msgstr ""
+
+#: config/tc-m68k.c:2028
+msgid "ColdFire fpu"
+msgstr ""
+
+#: config/tc-m68k.c:2035
 msgid "fpu (68040, 68060 or 68881/68882)"
 msgstr "fpu (68040, 68060 veya 68881/68882)"
 
-#: config/tc-m68k.c:1844
+#: config/tc-m68k.c:2038
 msgid "mmu (68030 or 68851)"
 msgstr "mmu (68030 veya 68851)"
 
-#: config/tc-m68k.c:1847
+#: config/tc-m68k.c:2041
 msgid "68020 or higher"
 msgstr "68020 veya üstü"
 
-#: config/tc-m68k.c:1850
+#: config/tc-m68k.c:2044
 msgid "68000 or higher"
 msgstr "68000 veya üstü"
 
-#: config/tc-m68k.c:1853
+#: config/tc-m68k.c:2047
 msgid "68010 or higher"
 msgstr "68010 veya üstü"
 
-#: config/tc-m68k.c:1882
+#: config/tc-m68k.c:2075
 msgid "operands mismatch"
 msgstr "iÅŸlenenler uyuÅŸmuyor"
 
-#: config/tc-m68k.c:1939 config/tc-m68k.c:1945 config/tc-m68k.c:1951
-#: config/tc-mmix.c:2464 config/tc-mmix.c:2488
+#: config/tc-m68k.c:2136 config/tc-m68k.c:2142 config/tc-m68k.c:2148
+#: config/tc-mmix.c:2526 config/tc-mmix.c:2550
 msgid "operand out of range"
 msgstr "işlenen kapsam dışı"
 
-#: config/tc-m68k.c:2008
+#: config/tc-m68k.c:2205
 #, c-format
 msgid "Bignum too big for %c format; truncated"
 msgstr "Büyük sayı (bignum) %c biçemi için fazla büyük; budandı"
 
-#: config/tc-m68k.c:2076
+#: config/tc-m68k.c:2286
 msgid "displacement too large for this architecture; needs 68020 or higher"
 msgstr "bu yapı için yerdeğiştirme fazla büyük; 68020 veya üstü gerekli"
 
-#: config/tc-m68k.c:2186
+#: config/tc-m68k.c:2397
 msgid "scale factor invalid on this architecture; needs cpu32 or 68020 or higher"
 msgstr "ölçek çarpanı bu yapıda geçersiz; cpu32 veya 68020 ve üstü gerekli"
 
-#: config/tc-m68k.c:2191
+#: config/tc-m68k.c:2402
 msgid "invalid index size for coldfire"
 msgstr "coldfire için geçersiz indeks boyu"
 
-#: config/tc-m68k.c:2244
+#: config/tc-m68k.c:2455
 msgid "Forcing byte displacement"
 msgstr "Bayt yerdeğişimi zorlandı"
 
-#: config/tc-m68k.c:2246
+#: config/tc-m68k.c:2457
 msgid "byte displacement out of range"
 msgstr "bayt yerdeğişimi kapsam dışı"
 
-#: config/tc-m68k.c:2293 config/tc-m68k.c:2331
+#: config/tc-m68k.c:2504 config/tc-m68k.c:2542
 msgid "invalid operand mode for this architecture; needs 68020 or higher"
 msgstr "bu yapı için geçersiz işlenen kipi; 68020 veya üstü gerekli"
 
-#: config/tc-m68k.c:2317 config/tc-m68k.c:2351
+#: config/tc-m68k.c:2528 config/tc-m68k.c:2562
 msgid ":b not permitted; defaulting to :w"
 msgstr ":b kullanılamaz; :w varsayıldı"
 
-#: config/tc-m68k.c:2428
+#: config/tc-m68k.c:2639
 msgid "unsupported byte value; use a different suffix"
 msgstr "desteklenmeyen bayt değeri; farklı bir sonek kullanın"
 
-#: config/tc-m68k.c:2442
+#: config/tc-m68k.c:2654
 msgid "unknown/incorrect operand"
 msgstr "bilinmeyen/geçersiz işlenen"
 
-#: config/tc-m68k.c:2475 config/tc-m68k.c:2483 config/tc-m68k.c:2490
-#: config/tc-m68k.c:2497
+#: config/tc-m68k.c:2697 config/tc-m68k.c:2705 config/tc-m68k.c:2712
+#: config/tc-m68k.c:2719
 msgid "out of range"
 msgstr "kapsam dışı"
 
-#: config/tc-m68k.c:2543
+#: config/tc-m68k.c:2765
 msgid "Can't use long branches on 68000/68010/5200"
 msgstr "68000/68010/5200 üzerinde uzun dal kullanılamaz"
 
-#: config/tc-m68k.c:2653
+#: config/tc-m68k.c:2875
 msgid "Expression out of range, using 0"
 msgstr "İfade kapsam dışı, 0 kullanıldı"
 
-#: config/tc-m68k.c:2765 config/tc-m68k.c:2781
+#: config/tc-m68k.c:3056 config/tc-m68k.c:3072
 msgid "Floating point register in register list"
 msgstr "Kayan nokta yazmacı yazmaç listesinde"
 
-#: config/tc-m68k.c:2771
+#: config/tc-m68k.c:3062
 msgid "Wrong register in floating-point reglist"
 msgstr "Kayan nokta yazmaç listesinde hatalı yazmaç"
 
-#: config/tc-m68k.c:2787
+#: config/tc-m68k.c:3078
 msgid "incorrect register in reglist"
 msgstr "yazmaç listesinde hatalı yazmaç"
 
-#: config/tc-m68k.c:2793
+#: config/tc-m68k.c:3084
 msgid "wrong register in floating-point reglist"
 msgstr "kayan nokta yazmaç listesinde hatalı yazmaç"
 
-#. ERROR
-#: config/tc-m68k.c:3234
+#. ERROR.
+#: config/tc-m68k.c:3547
 msgid "Extra )"
 msgstr "Fazla )"
 
-#. ERROR
-#: config/tc-m68k.c:3245
+#. ERROR.
+#: config/tc-m68k.c:3558
 msgid "Missing )"
 msgstr "Eksik )"
 
-#: config/tc-m68k.c:3262
+#: config/tc-m68k.c:3575
 msgid "Missing operand"
 msgstr "Ä°ÅŸlenen eksik"
 
-#: config/tc-m68k.c:3594
+#: config/tc-m68k.c:3937
 #, c-format
 msgid "%s -- statement `%s' ignored"
 msgstr "%s -- `%s' deyimi yoksayıldı"
 
-#: config/tc-m68k.c:3643
+#: config/tc-m68k.c:3986
 #, c-format
 msgid "Don't know how to figure width of %c in md_assemble()"
 msgstr "md_assemble()'da %c'nin genişliğinin nasıl belirtileceği bilinmiyor"
 
-#: config/tc-m68k.c:3825 config/tc-m68k.c:3863
+#: config/tc-m68k.c:4152
+#, fuzzy, c-format
+msgid "Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"
+msgstr "İç Hata: %s hash'lenemedi: %s"
+
+#: config/tc-m68k.c:4203 config/tc-m68k.c:4242
 #, c-format
 msgid "Internal Error: Can't find %s in hash table"
 msgstr "İç Hata: %s hash tablosunda bulunamadı"
 
-#: config/tc-m68k.c:3828 config/tc-m68k.c:3866
+#: config/tc-m68k.c:4206 config/tc-m68k.c:4245
 #, c-format
 msgid "Internal Error: Can't hash %s: %s"
 msgstr "İç Hata: %s hash'lenemedi: %s"
 
-#: config/tc-m68k.c:3948
+#: config/tc-m68k.c:4326
 msgid "architecture not yet selected: defaulting to 68020"
 msgstr "mimari seçilmemiş: 68020 varsayılıyor"
 
-#: config/tc-m68k.c:3997
+#: config/tc-m68k.c:4386
 #, c-format
 msgid "unrecognized default cpu `%s' ???"
 msgstr "bilinmeyen öntanımlı cpu `%s' ???"
 
-#: config/tc-m68k.c:4009
+#: config/tc-m68k.c:4397
 msgid "68040 and 68851 specified; mmu instructions may assemble incorrectly"
 msgstr "68040 ve 68851 belirtilmiş; mmu işlemleri doğru çevrilmeyebilir"
 
-#: config/tc-m68k.c:4029
+#: config/tc-m68k.c:4414
 msgid "options for 68881 and no-68881 both given"
 msgstr "hem 68881, hem de no-68881 seçenekleri verilmiş"
 
-#: config/tc-m68k.c:4031
+#: config/tc-m68k.c:4417
 msgid "options for 68851 and no-68851 both given"
 msgstr "hem 68851, hem de no-68851 seçenekleri verilmiş"
 
-#: config/tc-m68k.c:4102
+#: config/tc-m68k.c:4486
 #, c-format
 msgid "text label `%s' aligned to odd boundary"
 msgstr "`%s' metin etiketi tek sayılı sınıra hizalanmış"
 
-#: config/tc-m68k.c:4321
+#: config/tc-m68k.c:4695
 msgid "invalid byte branch offset"
 msgstr "geçersiz bayt dalı görecesi"
 
-#: config/tc-m68k.c:4358
+#: config/tc-m68k.c:4731
 msgid "short branch with zero offset: use :w"
 msgstr "sıfır göreceli kısa dal: :w kullanın"
 
-#: config/tc-m68k.c:4827 config/tc-m68k.c:4838
+#: config/tc-m68k.c:4781 config/tc-m68k.c:4840 config/tc-m68k.c:4904
+msgid "Tried to convert PC relative conditional branch to absolute jump"
+msgstr ""
+
+#: config/tc-m68k.c:4821
+#, fuzzy
+msgid "Tried to convert DBcc to absolute jump"
+msgstr "şimdiki işlenen, kesin sıçrama ile geçersiz"
+
+#: config/tc-m68k.c:5200 config/tc-m68k.c:5211 config/tc-m68k.c:5252
 msgid "expression out of range: defaulting to 1"
 msgstr "ifade kapsam dışı: 1 varsayıldı"
 
-#: config/tc-m68k.c:4870
+#: config/tc-m68k.c:5243
 msgid "expression out of range: defaulting to 0"
 msgstr "ifade kapsam dışı: 0 varsayıldı"
 
-#: config/tc-m68k.c:4903 config/tc-m68k.c:4915
+#: config/tc-m68k.c:5285 config/tc-m68k.c:5297
 #, c-format
 msgid "Can't deal with expression; defaulting to %ld"
 msgstr "ifade çözümlenemedi; %ld varsayıldı"
 
-#: config/tc-m68k.c:4929
+#: config/tc-m68k.c:5311
 msgid "expression doesn't fit in BYTE"
 msgstr "ifade BAYT'a sığmıyor"
 
-#: config/tc-m68k.c:4933
+#: config/tc-m68k.c:5315
 msgid "expression doesn't fit in WORD"
 msgstr "ifade WORD'e sığmıyor"
 
-#: config/tc-m68k.c:5026
+#: config/tc-m68k.c:5402
 #, c-format
 msgid "%s: unrecognized processor name"
 msgstr "%s: bilinmeyen işlemci adı"
 
-#: config/tc-m68k.c:5091
+#: config/tc-m68k.c:5466
 msgid "bad coprocessor id"
 msgstr "hatalı yardımcı işlemci kimliği"
 
-#: config/tc-m68k.c:5097
+#: config/tc-m68k.c:5472
 msgid "unrecognized fopt option"
 msgstr "bilinmeyen fopt seçeneği"
 
-#: config/tc-m68k.c:5231
+#: config/tc-m68k.c:5605
 #, c-format
 msgid "option `%s' may not be negated"
 msgstr "`%s' seçeneği olumsuzlanamaz"
 
-#: config/tc-m68k.c:5242
+#: config/tc-m68k.c:5616
 #, c-format
 msgid "option `%s' not recognized"
 msgstr "`%s' seçeneği bilinmiyor"
 
-#: config/tc-m68k.c:5275
+#: config/tc-m68k.c:5645
 msgid "bad format of OPT NEST=depth"
 msgstr "OPT NEST=derinlik için hatalı biçem"
 
-#: config/tc-m68k.c:5338
+#: config/tc-m68k.c:5701
 msgid "missing label"
 msgstr "etiket eksik"
 
-#: config/tc-m68k.c:5362 config/tc-m68k.c:5391
+#: config/tc-m68k.c:5725 config/tc-m68k.c:5754
 msgid "bad register list"
 msgstr "Hatalı yazmaç listesi"
 
-#: config/tc-m68k.c:5364
+#: config/tc-m68k.c:5727
 #, c-format
 msgid "bad register list: %s"
 msgstr "hatalı yazmaç listesi: %s"
 
-#: config/tc-m68k.c:5462
+#: config/tc-m68k.c:5825
 msgid "restore without save"
 msgstr "kaydetmeden eski haline getirir"
 
-#: config/tc-m68k.c:5636 config/tc-m68k.c:6023
+#: config/tc-m68k.c:5979 config/tc-m68k.c:6349
 msgid "syntax error in structured control directive"
 msgstr "yapılandırılmış denetim yönergesinde biçem hatası"
 
-#: config/tc-m68k.c:5685
+#: config/tc-m68k.c:6024
 msgid "missing condition code in structured control directive"
 msgstr "yapılandırılmış denetim yönergesinde eksik koşul kodu"
 
-#: config/tc-m68k.c:5757
+#: config/tc-m68k.c:6095
 #, c-format
 msgid "Condition <%c%c> in structured control directive can not be encoded correctly"
 msgstr "yapılandırılmış denetim yönergesindeki <%c%c> koşulu doğru kodlanamıyor"
 
-#: config/tc-m68k.c:6066
+#: config/tc-m68k.c:6391
 msgid "missing then"
 msgstr "`then' eksik"
 
-#: config/tc-m68k.c:6148
+#: config/tc-m68k.c:6472
 msgid "else without matching if"
 msgstr "`if' ile eÅŸleÅŸmeyen `else'"
 
-#: config/tc-m68k.c:6182
+#: config/tc-m68k.c:6505
 msgid "endi without matching if"
 msgstr "`if' ile eÅŸleÅŸmeyen `endi'"
 
-#: config/tc-m68k.c:6223
+#: config/tc-m68k.c:6545
 msgid "break outside of structured loop"
 msgstr "yapılandırılmış döngünün dışında `break' (durma)"
 
-#: config/tc-m68k.c:6262
+#: config/tc-m68k.c:6583
 msgid "next outside of structured loop"
 msgstr "yapılandırılmış döngünün dışında `next' (sonraki)"
 
-#: config/tc-m68k.c:6314
+#: config/tc-m68k.c:6634
 msgid "missing ="
 msgstr "= eksik"
 
-#: config/tc-m68k.c:6352
+#: config/tc-m68k.c:6672
 msgid "missing to or downto"
 msgstr "`to' veya `downto' eksik"
 
-#: config/tc-m68k.c:6388 config/tc-m68k.c:6422 config/tc-m68k.c:6641
+#: config/tc-m68k.c:6708 config/tc-m68k.c:6742 config/tc-m68k.c:6956
 msgid "missing do"
 msgstr "`do' eksik"
 
-#: config/tc-m68k.c:6525
+#: config/tc-m68k.c:6843
 msgid "endf without for"
 msgstr "`for' ile eÅŸleÅŸmeyen `endf'"
 
-#: config/tc-m68k.c:6581
+#: config/tc-m68k.c:6897
 msgid "until without repeat"
 msgstr "`repeat' ile eÅŸleÅŸmeyen `until'"
 
-#: config/tc-m68k.c:6677
+#: config/tc-m68k.c:6991
 msgid "endw without while"
 msgstr "`while' ile eÅŸleÅŸmeyen `endw'"
 
-#: config/tc-m68k.c:6801
-#, c-format
-msgid "unrecognized option `%s'"
-msgstr "bilinmeyen seçenek: `%s'"
-
-#: config/tc-m68k.c:6846
+#: config/tc-m68k.c:7153
 #, c-format
 msgid "unrecognized architecture specification `%s'"
 msgstr "bilinmeyen yapı tanımı `%s'"
 
-#: config/tc-m68k.c:6940
-#, c-format
+#: config/tc-m68k.c:7246
+#, fuzzy, c-format
 msgid ""
 "680X0 options:\n"
 "-l\t\t\tuse 1 word for refs to undefined symbols [default 2]\n"
 "-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n"
 "-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n"
-"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m5307  | -m5407\n"
+"-m5200  | -m5202  | -m5204  | -m5206  | -m5206e | -m521x  | -m5249  |\n"
+"-m528x  | -m5307  | -m5407  | -m547x  | -m548x  | -mcfv4  | -mcfv4e\n"
 "\t\t\tspecify variant of 680X0 architecture [default %s]\n"
 "-m68881 | -m68882 | -mno-68881 | -mno-68882\n"
 "\t\t\ttarget has/lacks floating-point coprocessor\n"
@@ -5974,7 +6773,8 @@ msgstr ""
 "\t\t\thedefte kayan nokta yardımcı işlemcisi var/yok\n"
 "\t\t\t[öntanımlı: 68020, 68030 ve cpu32 için `yes' (var)]\n"
 
-#: config/tc-m68k.c:6951
+#: config/tc-m68k.c:7258
+#, c-format
 msgid ""
 "-m68851 | -mno-68851\n"
 "\t\t\ttarget has/lacks memory-management unit coprocessor\n"
@@ -5996,7 +6796,8 @@ msgstr ""
 "\t\t\tyazmaç isimlerini önek karakteri olmaksızın tanır\n"
 "--bitwise-or\t\t`|'ı bir açıklama karakteri olarak işlemez\n"
 
-#: config/tc-m68k.c:6961
+#: config/tc-m68k.c:7268
+#, c-format
 msgid ""
 "--base-size-default-16\tbase reg without size is 16 bits\n"
 "--base-size-default-32\tbase reg without size is 32 bits (default)\n"
@@ -6008,12 +6809,12 @@ msgstr ""
 "--disp-size-default-16\tbilinmeyen boyda yerdeÄŸiÅŸim 16 bit\n"
 "--disp-size-default-32\tbilinmeyen boyda yerdeğişim 32 bit (öntanımlı)\n"
 
-#: config/tc-m68k.c:6996
+#: config/tc-m68k.c:7303
 #, c-format
 msgid "Error %s in %s\n"
 msgstr "%s hatası %s içerisinde\n"
 
-#: config/tc-m68k.c:7000
+#: config/tc-m68k.c:7307
 #, c-format
 msgid "Opcode(%d.%s): "
 msgstr "Opkod(%d.%s):"
@@ -6066,164 +6867,165 @@ msgstr "Gevşetme hiç bir zaman olmamalı"
 msgid "m88k convert_frag\n"
 msgstr "m88k convert_frag\n"
 
-#: config/tc-mcore.c:460
+#: config/tc-mcore.c:461
 #, c-format
 msgid "register expected, but saw '%.6s'"
 msgstr "yazmaç beklendi fakat '%.6s' bulundu"
 
-#: config/tc-mcore.c:544
+#: config/tc-mcore.c:545
 #, c-format
 msgid "control register expected, but saw '%.6s'"
 msgstr "denetim yazmacı beklendi fakat '%.6s' bulundu"
 
-#: config/tc-mcore.c:582
+#: config/tc-mcore.c:583
 msgid "bad/missing psr specifier"
 msgstr "hatalı/eksik psr belirteci"
 
-#: config/tc-mcore.c:743
+#: config/tc-mcore.c:744
 msgid "more than 65K literal pools"
 msgstr "65K sabit (literal) havuzdan fazla"
 
-#: config/tc-mcore.c:797
+#: config/tc-mcore.c:798
 msgid "missing ']'"
 msgstr "eksik ']'"
 
-#: config/tc-mcore.c:837
+#: config/tc-mcore.c:838
 msgid "operand must be a constant"
 msgstr "işlenen sabit olmalı"
 
-#: config/tc-mcore.c:839
+#: config/tc-mcore.c:840
 #, c-format
 msgid "operand must be absolute in range %u..%u, not %ld"
 msgstr "işlenen, %3$ld değil, %1$u..%2$u aralığında kesin olmalı"
 
-#: config/tc-mcore.c:875
+#: config/tc-mcore.c:876
 msgid "operand must be a multiple of 4"
 msgstr "işlenen 4'ün katı olmalı"
 
-#: config/tc-mcore.c:882
+#: config/tc-mcore.c:883
 msgid "operand must be a multiple of 2"
 msgstr "işlenen 2'nin katı olmalı"
 
-#: config/tc-mcore.c:896 config/tc-mcore.c:1410 config/tc-mcore.c:1464
+#: config/tc-mcore.c:897 config/tc-mcore.c:1411 config/tc-mcore.c:1465
 msgid "base register expected"
 msgstr "temel yazmaç beklendi"
 
-#: config/tc-mcore.c:945
+#: config/tc-mcore.c:946
 #, c-format
 msgid "unknown opcode \"%s\""
 msgstr "bilinmeyen opkod \"%s\""
 
-#: config/tc-mcore.c:988
+#: config/tc-mcore.c:989
 msgid "invalid register: r15 illegal"
 msgstr "geçersiz yazmaç: r15 hatalı"
 
-#: config/tc-mcore.c:1036 config/tc-mcore.c:1614
+#: config/tc-mcore.c:1037 config/tc-mcore.c:1615
 msgid "M340 specific opcode used when assembling for M210"
 msgstr "M210 için çevrilirken M340'a özgü opkod kullanlmış"
 
-#: config/tc-mcore.c:1054 config/tc-mcore.c:1093 config/tc-mcore.c:1112
-#: config/tc-mcore.c:1131 config/tc-mcore.c:1158 config/tc-mcore.c:1187
-#: config/tc-mcore.c:1224 config/tc-mcore.c:1259 config/tc-mcore.c:1278
-#: config/tc-mcore.c:1297 config/tc-mcore.c:1331 config/tc-mcore.c:1356
-#: config/tc-mcore.c:1413 config/tc-mcore.c:1467 config/tc-mcore.c:1503
-#: config/tc-mcore.c:1561 config/tc-mcore.c:1583 config/tc-mcore.c:1606
+#: config/tc-mcore.c:1055 config/tc-mcore.c:1094 config/tc-mcore.c:1113
+#: config/tc-mcore.c:1132 config/tc-mcore.c:1159 config/tc-mcore.c:1188
+#: config/tc-mcore.c:1225 config/tc-mcore.c:1260 config/tc-mcore.c:1279
+#: config/tc-mcore.c:1298 config/tc-mcore.c:1332 config/tc-mcore.c:1357
+#: config/tc-mcore.c:1414 config/tc-mcore.c:1468 config/tc-mcore.c:1504
+#: config/tc-mcore.c:1562 config/tc-mcore.c:1584 config/tc-mcore.c:1607
 msgid "second operand missing"
 msgstr "ikinci iÅŸlenen eksik"
 
-#: config/tc-mcore.c:1069
+#: config/tc-mcore.c:1070
 msgid "destination register must be r1"
 msgstr "hedef yazmacı r1 olmalı"
 
-#: config/tc-mcore.c:1090
+#: config/tc-mcore.c:1091
 msgid "source register must be r1"
 msgstr "kaynak yazmacı r1 olmalı"
 
-#: config/tc-mcore.c:1153 config/tc-mcore.c:1210
+#: config/tc-mcore.c:1154 config/tc-mcore.c:1211
 msgid "immediate is not a power of two"
 msgstr "şimdiki, ikinin kuvveti olmalı"
 
-#: config/tc-mcore.c:1181
+#: config/tc-mcore.c:1182
 msgid "translating bgeni to movi"
 msgstr "bgeni, movi'ye çevriliyor"
 
-#: config/tc-mcore.c:1218
+#: config/tc-mcore.c:1219
 msgid "translating mgeni to movi"
 msgstr "mgeni, movi'ye çevriliyor"
 
-#: config/tc-mcore.c:1250
+#: config/tc-mcore.c:1251
 msgid "translating bmaski to movi"
 msgstr "bmaski, movi'ye çevriliyor"
 
-#: config/tc-mcore.c:1326
+#: config/tc-mcore.c:1327
 #, c-format
 msgid "displacement too large (%d)"
 msgstr "yerdeğişim fazla büyük (%d)"
 
-#: config/tc-mcore.c:1340
+#: config/tc-mcore.c:1341
 msgid "Invalid register: r0 and r15 illegal"
 msgstr "Geçersiz yazmaç: r0 ve r15 hatalı"
 
-#: config/tc-mcore.c:1371
+#: config/tc-mcore.c:1372
 msgid "bad starting register: r0 and r15 invalid"
 msgstr "hatalı başlangıç yazmacı: r0 ve r15 hatalı"
 
-#: config/tc-mcore.c:1384
+#: config/tc-mcore.c:1385
 msgid "ending register must be r15"
 msgstr "son yazmaç r15 olmalı"
 
-#: config/tc-mcore.c:1404
+#: config/tc-mcore.c:1405
 msgid "bad base register: must be r0"
 msgstr "hatalı temel yazmaç: r0 olmalı"
 
-#: config/tc-mcore.c:1422
+#: config/tc-mcore.c:1423
 msgid "first register must be r4"
 msgstr "ilk yazmaç r4 olmalı"
 
-#: config/tc-mcore.c:1433
+#: config/tc-mcore.c:1434
 msgid "last register must be r7"
 msgstr "son yazmaç r7 olmalı"
 
-#: config/tc-mcore.c:1470
+#: config/tc-mcore.c:1471
 msgid "reg-reg expected"
 msgstr "yazmaç-yazmaç beklendi"
 
-#: config/tc-mcore.c:1580
+#: config/tc-mcore.c:1581
 msgid "second operand must be 1"
 msgstr "ikinci işlenen 1 olmalı"
 
-#: config/tc-mcore.c:1601
+#: config/tc-mcore.c:1602
 msgid "zero used as immediate value"
 msgstr "şimdiki değer olarak sıfır kullanıldı"
 
-#: config/tc-mcore.c:1628
+#: config/tc-mcore.c:1629
 msgid "duplicated psr bit specifier"
 msgstr "psr bit belirteci tekrarlandı"
 
-#: config/tc-mcore.c:1634
+#: config/tc-mcore.c:1635
 msgid "`af' must appear alone"
 msgstr "`af' tek başına olmalı"
 
-#: config/tc-mcore.c:1641
+#: config/tc-mcore.c:1642
 #, c-format
 msgid "unimplemented opcode \"%s\""
 msgstr "henüz desteklenmeyen opkod \"%s\""
 
-#: config/tc-mcore.c:1650
+#: config/tc-mcore.c:1651
 #, c-format
 msgid "ignoring operands: %s "
 msgstr "işlenenler yoksayıldı: %s"
 
-#: config/tc-mcore.c:1718 config/tc-w65.c:772
+#: config/tc-mcore.c:1719 config/tc-w65.c:769
 msgid "Bad call to MD_NTOF()"
 msgstr "MD_NTOF()'ye hatalı çağrı"
 
-#: config/tc-mcore.c:1788
+#: config/tc-mcore.c:1789
 #, c-format
 msgid "unrecognised cpu type '%s'"
 msgstr "bilinmeyen cpu türü '%s'"
 
-#: config/tc-mcore.c:1807
+#: config/tc-mcore.c:1808
+#, c-format
 msgid ""
 "MCORE specific options:\n"
 "  -{no-}jsri2bsr\t  {dis}able jsri to bsr transformation (def: dis)\n"
@@ -6241,681 +7043,646 @@ msgstr ""
 "  -EB                     büyük sonlu sistem için çevrim yapar (öntanımlı)\n"
 "  -EL                     küçük sonlu sistem için çevrim yapar\n"
 
-#: config/tc-mcore.c:1826
+#: config/tc-mcore.c:1827
 msgid "failed sanity check: short_jump"
 msgstr "başarısız kontrol: short_jump"
 
-#: config/tc-mcore.c:1837
+#: config/tc-mcore.c:1838
 msgid "failed sanity check: long_jump"
 msgstr "başarısız kontrol: long_jump"
 
-#: config/tc-mcore.c:1863
+#: config/tc-mcore.c:1864
 #, c-format
 msgid "odd displacement at %x"
 msgstr "%x'da tek sayılı sıçrama"
 
-#: config/tc-mcore.c:2047
+#: config/tc-mcore.c:2048
 msgid "unknown"
 msgstr "bilinmeyen"
 
-#: config/tc-mcore.c:2073
+#: config/tc-mcore.c:2074
 #, c-format
 msgid "odd distance branch (0x%lx bytes)"
 msgstr "tek sayılı uzaklık dalı (0x%lx bayt)"
 
-#: config/tc-mcore.c:2077
+#: config/tc-mcore.c:2078
 #, c-format
 msgid "pcrel for branch to %s too far (0x%lx)"
 msgstr "%s'ye dal için pcrel fazla uzak (0x%lx)"
 
-#: config/tc-mcore.c:2096
+#: config/tc-mcore.c:2097
 #, c-format
 msgid "pcrel for lrw/jmpi/jsri to %s too far (0x%lx)"
 msgstr "%s'ye lrw/jmpi/jsri için pcrel fazla uzak (0x%lx)"
 
-#: config/tc-mcore.c:2107
+#: config/tc-mcore.c:2108
 #, c-format
 msgid "pcrel for loopt too far (0x%lx)"
 msgstr "loopt için pcrel fazla uzak (0x%lx)"
 
-#: config/tc-mcore.c:2336
+#: config/tc-mcore.c:2337
 #, c-format
 msgid "Can not do %d byte %srelocation"
 msgstr "%d baytlık %s yerdeğişimi yapılamaz"
 
-#: config/tc-mcore.c:2338
+#: config/tc-mcore.c:2339
 msgid "pc-relative"
 msgstr "pc-göreli"
 
 #. Prototypes for static functions.
-#: config/tc-mips.c:817
+#: config/tc-mips.c:862
 #, c-format
 msgid "internal Error, line %d, %s"
 msgstr "İç Hata, %d satırı, %s"
 
-#: config/tc-mips.c:1130
+#: config/tc-mips.c:1175
 #, c-format
 msgid "internal: can't hash `%s': %s"
 msgstr "iç: `%s' hash'lenemedi: %s"
 
-#: config/tc-mips.c:1138
+#: config/tc-mips.c:1183
 #, c-format
 msgid "internal error: bad mips16 opcode: %s %s\n"
 msgstr "iç hata: hatalı mips16 opkodu: %s %s\n"
 
-#: config/tc-mips.c:1331
+#: config/tc-mips.c:1376
 #, c-format
 msgid "returned from mips_ip(%s) insn_opcode = 0x%x\n"
 msgstr "geri dönüş: mips_ip(%s) insn_opcode = 0x%x\n"
 
-#: config/tc-mips.c:1975 config/tc-mips.c:13665
+#: config/tc-mips.c:2085 config/tc-mips.c:13223
 msgid "extended instruction in delay slot"
 msgstr "gecikme yuvasında genişletilmiş işlem"
 
-#: config/tc-mips.c:2021 config/tc-mips.c:2031
+#: config/tc-mips.c:2145 config/tc-mips.c:2155
 #, c-format
 msgid "jump to misaligned address (0x%lx)"
 msgstr "hizalanmamış adrese sıçrama (0x%lx)"
 
-#: config/tc-mips.c:2024 config/tc-mips.c:2034
+#: config/tc-mips.c:2148 config/tc-mips.c:2158
 #, c-format
 msgid "jump address range overflow (0x%lx)"
 msgstr "sıçrama adres aralık taşması (0x%lx)"
 
-#: config/tc-mips.c:2804 config/tc-mips.c:3193
+#: config/tc-mips.c:2937
+msgid "Macro instruction expanded into multiple instructions in a branch delay slot"
+msgstr "Makro işlemi bir gecikme dalında birden fazla işlem olarak genişletildi"
+
+#: config/tc-mips.c:2940
 msgid "Macro instruction expanded into multiple instructions"
 msgstr "Makro iÅŸlemi birden fazla iÅŸlem olarak geniÅŸletildi"
 
-#: config/tc-mips.c:2816
-msgid "Macro instruction expanded into multiple instructions in a branch delay slot"
-msgstr "Makro işlemi bir gecikme dalında birden fazla işlem olarak genişletildi"
+#: config/tc-mips.c:3436 config/tc-mips.c:3602 config/tc-mips.c:5891
+#, fuzzy
+msgid "constant too large"
+msgstr "karakter sabiti fazla büyük"
 
-#: config/tc-mips.c:3224 config/tc-mips.c:7548 config/tc-mips.c:7574
-#: config/tc-mips.c:7652 config/tc-mips.c:7677
+#: config/tc-mips.c:3444 config/tc-mips.c:7375 config/tc-mips.c:7399
+#: config/tc-mips.c:7472 config/tc-mips.c:7495
 msgid "operand overflow"
 msgstr "işlenen taşması"
 
-#: config/tc-mips.c:3250 config/tc-mips.c:6901 config/tc-mips.c:7753
+#: config/tc-mips.c:3463 config/tc-mips.c:4074 config/tc-mips.c:6765
+#: config/tc-mips.c:7562
 msgid "Macro used $at after \".set noat\""
 msgstr "Macro, \".set noat\" sonrasında $at kullanmış"
 
-#: config/tc-mips.c:3280
+#: config/tc-mips.c:3500
 msgid "unsupported large constant"
 msgstr "desteklenmeyen büyük sabit"
 
-#: config/tc-mips.c:3282
+#: config/tc-mips.c:3502
 #, c-format
 msgid "Instruction %s requires absolute expression"
 msgstr "%s iÅŸlemi kesin ifade gerektirir"
 
-#: config/tc-mips.c:3421
+#: config/tc-mips.c:3637
 #, c-format
 msgid "Number (0x%lx) larger than 32 bits"
 msgstr "Sayı (0x%lx) 32 bitten büyük"
 
-#: config/tc-mips.c:3443
+#: config/tc-mips.c:3658
 msgid "Number larger than 64 bits"
 msgstr "Sayı 64 bitten büyük"
 
-#: config/tc-mips.c:3746 config/tc-mips.c:3786 config/tc-mips.c:3828
-#: config/tc-mips.c:3885 config/tc-mips.c:6068 config/tc-mips.c:6110
-#: config/tc-mips.c:6162 config/tc-mips.c:6660 config/tc-mips.c:6715
+#: config/tc-mips.c:3952 config/tc-mips.c:3980 config/tc-mips.c:4018
+#: config/tc-mips.c:4063 config/tc-mips.c:6094 config/tc-mips.c:6133
+#: config/tc-mips.c:6172 config/tc-mips.c:6584 config/tc-mips.c:6636
 msgid "PIC code offset overflow (max 16 signed bits)"
 msgstr "PIC kodu görece taşması (maksimum 16 signed bit)"
 
-#: config/tc-mips.c:4145
-#, c-format
-msgid "Branch %s is always false (nop)"
-msgstr "%s dalı her zaman yanlış (nop)"
-
-#: config/tc-mips.c:4152
-#, c-format
-msgid "Branch likely %s is always false"
-msgstr "Olası %s dalı her zaman yanlış"
-
-#: config/tc-mips.c:4159 config/tc-mips.c:4227 config/tc-mips.c:4319
-#: config/tc-mips.c:4368 config/tc-mips.c:7856 config/tc-mips.c:7864
-#: config/tc-mips.c:7871 config/tc-mips.c:7978
+#: config/tc-mips.c:4371 config/tc-mips.c:4437 config/tc-mips.c:4525
+#: config/tc-mips.c:4572 config/tc-mips.c:4633 config/tc-mips.c:4681
+#: config/tc-mips.c:7660 config/tc-mips.c:7667 config/tc-mips.c:7674
+#: config/tc-mips.c:7781
 msgid "Unsupported large constant"
 msgstr "Desteklenmeyen büyük sabit"
 
 #. result is always true
-#: config/tc-mips.c:4193
+#: config/tc-mips.c:4403
 #, c-format
 msgid "Branch %s is always true"
 msgstr "%s dalı her zaman doğru"
 
-#: config/tc-mips.c:4436 config/tc-mips.c:4539
+#: config/tc-mips.c:4644 config/tc-mips.c:4692 config/tc-mips.c:8106
+#, c-format
+msgid "Improper position (%lu)"
+msgstr "Geçersiz yer (%lu)"
+
+#: config/tc-mips.c:4650 config/tc-mips.c:8174
+#, c-format
+msgid "Improper extract size (%lu, position %lu)"
+msgstr "Geçersiz çıkarma boyu (%lu, yer %lu)"
+
+#: config/tc-mips.c:4698 config/tc-mips.c:8138
+#, c-format
+msgid "Improper insert size (%lu, position %lu)"
+msgstr "Geçersiz ekleme boyu (%lu, yer %lu)"
+
+#: config/tc-mips.c:4735 config/tc-mips.c:4834
 msgid "Divide by zero."
 msgstr "Sıfırla bölüm."
 
-#: config/tc-mips.c:4621
+#: config/tc-mips.c:4922
 msgid "dla used to load 32-bit register"
 msgstr "dla 32 bit yazmaç yüklemekte kullanıldı"
 
-#: config/tc-mips.c:4624
+#: config/tc-mips.c:4925
 msgid "la used to load 64-bit address"
 msgstr "la 64 bit adres yüklemekte kullanıldı"
 
-#: config/tc-mips.c:4999 config/tc-mips.c:5352
+#: config/tc-mips.c:5209 config/tc-mips.c:5488
 msgid "PIC code offset overflow (max 32 signed bits)"
 msgstr "PIC kodu görece taşması (maksimum 32 signed bit)"
 
-#: config/tc-mips.c:5418
+#: config/tc-mips.c:5534
 msgid "MIPS PIC call to register other than $25"
 msgstr "$25'ten başka yazmaca MIPS PIC çağrısı"
 
-#: config/tc-mips.c:5424 config/tc-mips.c:5435 config/tc-mips.c:5573
-#: config/tc-mips.c:5584
+#: config/tc-mips.c:5540 config/tc-mips.c:5551 config/tc-mips.c:5675
+#: config/tc-mips.c:5686
 msgid "No .cprestore pseudo-op used in PIC code"
 msgstr "PIC kodunda .cprestore sanal işlemi kullanılmamış"
 
-#: config/tc-mips.c:5429 config/tc-mips.c:5578
+#: config/tc-mips.c:5545 config/tc-mips.c:5680
 msgid "No .frame pseudo-op used in PIC code"
 msgstr "PIC kodunda .frame sanal işlemi kullanılmamış"
 
-#: config/tc-mips.c:5656 config/tc-mips.c:5745 config/tc-mips.c:6413
-#: config/tc-mips.c:6452 config/tc-mips.c:6470 config/tc-mips.c:7220
+#: config/tc-mips.c:5751 config/tc-mips.c:5839 config/tc-mips.c:6379
+#: config/tc-mips.c:6410 config/tc-mips.c:6428 config/tc-mips.c:7072
 msgid "opcode not supported on this processor"
 msgstr "bu iÅŸlemcide bu opkod desteklenmiyor"
 
-#: config/tc-mips.c:5969
-msgid "load/store address overflow (max 32 bits)"
-msgstr "adres yükle/sakla taşması (maksimum 32 bit)"
-
-#: config/tc-mips.c:7083 config/tc-mips.c:7116 config/tc-mips.c:7166
-#: config/tc-mips.c:7198
+#: config/tc-mips.c:6938 config/tc-mips.c:6969 config/tc-mips.c:7020
+#: config/tc-mips.c:7050
 msgid "Improper rotate count"
 msgstr "Geçersiz döndürme sayısı"
 
-#: config/tc-mips.c:7259
+#: config/tc-mips.c:7105
 #, c-format
 msgid "Instruction %s: result is always false"
 msgstr "%s işlemi: sonuç her zaman yanlış"
 
-#: config/tc-mips.c:7417
+#: config/tc-mips.c:7251
 #, c-format
 msgid "Instruction %s: result is always true"
 msgstr "%s işlemi: sonuç her zaman doğru"
 
 #. FIXME: Check if this is one of the itbl macros, since they
 #. are added dynamically.
-#: config/tc-mips.c:7749
+#: config/tc-mips.c:7558
 #, c-format
 msgid "Macro %s not implemented yet"
 msgstr "%s macrosu henüz desteklenmiyor"
 
-#: config/tc-mips.c:8009
+#: config/tc-mips.c:7812
 #, c-format
 msgid "internal: bad mips opcode (mask error): %s %s"
 msgstr "iç hata: hatalı mips opkodu (maske hatası): %s %s"
 
-#: config/tc-mips.c:8029 config/tc-mips.c:8360
+#: config/tc-mips.c:7837 config/tc-mips.c:8200
 #, c-format
 msgid "internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"
 msgstr "iç hata: hatalı mips opkodu (bilinmeyen genişletilmiş işlenen türü `+%c'): %s %s"
 
-#: config/tc-mips.c:8090
+#: config/tc-mips.c:7898
 #, c-format
 msgid "internal: bad mips opcode (unknown operand type `%c'): %s %s"
 msgstr "iç hata: hatalı mips opkodu (bilinmeyen işlenen türü `%c'): %s %s"
 
-#: config/tc-mips.c:8097
+#: config/tc-mips.c:7905
 #, c-format
 msgid "internal: bad mips opcode (bits 0x%lx undefined): %s %s"
 msgstr "iç hata: hatalı mips opkodu (0x%lx bitleri tanımsız): %s %s"
 
-#: config/tc-mips.c:8211
+#: config/tc-mips.c:8019
 #, c-format
 msgid "opcode not supported on this processor: %s (%s)"
 msgstr "opkod bu iÅŸlemcide desteklenmiyor: %s (%s)"
 
-#: config/tc-mips.c:8292
-#, c-format
-msgid "Improper position (%lu)"
-msgstr "Geçersiz yer (%lu)"
-
-#: config/tc-mips.c:8318
-#, c-format
-msgid "Improper insert size (%lu, position %lu)"
-msgstr "Geçersiz ekleme boyu (%lu, yer %lu)"
-
-#: config/tc-mips.c:8344
-#, c-format
-msgid "Improper extract size (%lu, position %lu)"
-msgstr "Geçersiz çıkarma boyu (%lu, yer %lu)"
+#: config/tc-mips.c:8194 config/tc-mips.c:8684
+msgid "absolute expression required"
+msgstr "kesin ifade gerekli"
 
-#: config/tc-mips.c:8378
+#: config/tc-mips.c:8218
 #, c-format
 msgid "Improper shift amount (%lu)"
 msgstr "Geçersiz kaydırma miktarı (%lu)"
 
-#: config/tc-mips.c:8404 config/tc-mips.c:9654 config/tc-mips.c:9769
+#: config/tc-mips.c:8244 config/tc-mips.c:9517 config/tc-mips.c:9632
 #, c-format
 msgid "Invalid value for `%s' (%lu)"
 msgstr "`%s' için geçersiz değer (%lu)"
 
-#: config/tc-mips.c:8422
+#: config/tc-mips.c:8262
 #, c-format
 msgid "Illegal break code (%lu)"
 msgstr "Geçersiz durma (break) kodu (%lu)"
 
-#: config/tc-mips.c:8436
+#: config/tc-mips.c:8276
 #, c-format
 msgid "Illegal lower break code (%lu)"
 msgstr "Geçersiz alt durma (break) kodu (%lu)"
 
-#: config/tc-mips.c:8449
+#: config/tc-mips.c:8289
 #, c-format
 msgid "Illegal 20-bit code (%lu)"
 msgstr "Geçersiz 20 bit kod (%lu)"
 
-#: config/tc-mips.c:8461
+#: config/tc-mips.c:8301
 #, c-format
 msgid "Coproccesor code > 25 bits (%lu)"
 msgstr "Yardımcı işlemci kodu > 25 bit (%lu)"
 
-#: config/tc-mips.c:8474
+#: config/tc-mips.c:8314
 #, c-format
 msgid "Illegal 19-bit code (%lu)"
 msgstr "Geçersiz 19 bitlik kod (%lu)"
 
-#: config/tc-mips.c:8486
+#: config/tc-mips.c:8326
 #, c-format
 msgid "Invalid performance register (%lu)"
 msgstr "Başarım yazmacı geçersiz (%lu)"
 
-#: config/tc-mips.c:8524
+#: config/tc-mips.c:8364
 #, c-format
 msgid "Invalid register number (%d)"
 msgstr "Geçersiz yazmaç numarası (%d)"
 
-#: config/tc-mips.c:8702
+#: config/tc-mips.c:8542
 #, c-format
 msgid "Invalid MDMX Immediate (%ld)"
 msgstr "geçersiz MDMX şimdiki (%ld)"
 
-#: config/tc-mips.c:8745
+#: config/tc-mips.c:8585
 #, c-format
 msgid "Invalid float register number (%d)"
 msgstr "Geçersiz kayan nokta yazmaç numarası (%d)"
 
-#: config/tc-mips.c:8755
+#: config/tc-mips.c:8595
 #, c-format
 msgid "Float register should be even, was %d"
 msgstr "Kayan noktalı yazmaç çift sayılı olmalı, %d bulundu"
 
-#: config/tc-mips.c:8794
+#: config/tc-mips.c:8634
 #, c-format
 msgid "Bad element selector %ld"
 msgstr "Hatalı öğe seçici %ld"
 
-#: config/tc-mips.c:8801
+#: config/tc-mips.c:8642
 #, c-format
 msgid "Expecting ']' found '%s'"
 msgstr "']' beklendi, '%s' bulundu"
 
-#: config/tc-mips.c:8843
-msgid "absolute expression required"
-msgstr "kesin ifade gerekli"
-
-#: config/tc-mips.c:8911
+#: config/tc-mips.c:8746
 #, c-format
 msgid "Bad floating point constant: %s"
 msgstr "Hatalı kayan noktalı sabit: %s"
 
-#: config/tc-mips.c:9039
+#: config/tc-mips.c:8867
 msgid "Can't use floating point insn in this section"
 msgstr "Bu bölümde kayan noktalı işlem kullanılamaz"
 
-#: config/tc-mips.c:9100
+#: config/tc-mips.c:8928
 msgid "expression out of range"
 msgstr "İfade kapsam dışı"
 
-#: config/tc-mips.c:9140
+#: config/tc-mips.c:8968
 msgid "lui expression not in range 0..65535"
 msgstr "lui ifadesi 0..65535 aralığında değil"
 
-#: config/tc-mips.c:9164
-#, c-format
-msgid "invalid condition code register $fcc%d"
+#: config/tc-mips.c:8992
+#, fuzzy, c-format
+msgid "Invalid condition code register $fcc%d"
 msgstr "hatalı koşul kodu yazmacı $fcc%d"
 
-#: config/tc-mips.c:9189
+#: config/tc-mips.c:8997
+#, fuzzy, c-format
+msgid "Condition code register should be even for %s, was %d"
+msgstr "Kayan noktalı yazmaç çift sayılı olmalı, %d bulundu"
+
+#: config/tc-mips.c:9002
+#, fuzzy, c-format
+msgid "Condition code register should be 0 or 4 for %s, was %d"
+msgstr "Kayan noktalı yazmaç çift sayılı olmalı, %d bulundu"
+
+#: config/tc-mips.c:9028
 msgid "invalid coprocessor sub-selection value (0-7)"
 msgstr "hatalı yardımcı işlemci alt seçim değeri (0-7)"
 
-#: config/tc-mips.c:9201 config/tc-mips.c:9218
+#: config/tc-mips.c:9040 config/tc-mips.c:9057
 #, c-format
 msgid "bad byte vector index (%ld)"
 msgstr "hatalı bayt vektör indeksi (%ld)"
 
-#: config/tc-mips.c:9229
+#: config/tc-mips.c:9068
 #, c-format
 msgid "bad char = '%c'\n"
 msgstr "hatalı karakter = '%c'\n"
 
-#: config/tc-mips.c:9240 config/tc-mips.c:9245 config/tc-mips.c:9794
+#: config/tc-mips.c:9079 config/tc-mips.c:9084 config/tc-mips.c:9657
 msgid "illegal operands"
 msgstr "geçersiz işlenenler"
 
-#: config/tc-mips.c:9310
+#: config/tc-mips.c:9150
 msgid "unrecognized opcode"
 msgstr "bilinmeyen opkod"
 
-#: config/tc-mips.c:9422
+#: config/tc-mips.c:9289
 #, c-format
 msgid "invalid register number (%d)"
 msgstr "geçersiz yazmaç numarası (%d)"
 
-#: config/tc-mips.c:9513
+#: config/tc-mips.c:9380
 msgid "used $at without \".set noat\""
 msgstr "\".set noat\" olmaksızın $at kullanılmış"
 
-#: config/tc-mips.c:9688
+#: config/tc-mips.c:9551
 msgid "can't parse register list"
 msgstr "yazmaç listesi ayrıştırılamadı"
 
-#: config/tc-mips.c:9912
+#: config/tc-mips.c:9775
 msgid "extended operand requested but not required"
 msgstr "geniÅŸletilmiÅŸ iÅŸlenen tercih edilir fakat ÅŸart deÄŸil"
 
-#: config/tc-mips.c:9914
+#: config/tc-mips.c:9777
 msgid "invalid unextended operand value"
 msgstr "geçersiz genişletilmemiş işlenen değeri"
 
-#: config/tc-mips.c:9942
+#: config/tc-mips.c:9805
 msgid "operand value out of range for instruction"
 msgstr "işlenen değeri işlem için kapsam dışı"
 
-#: config/tc-mips.c:10340
+#: config/tc-mips.c:10245
 #, c-format
 msgid "A different %s was already specified, is now %s"
 msgstr "Farklı bir %s zaten belirtilmişti, şimdi %s oldu"
 
-#: config/tc-mips.c:10501
-msgid "-G may not be used with embedded PIC code"
-msgstr "-G gömülü PIC kodu ile kullanılamaz"
-
-#: config/tc-mips.c:10530
+#: config/tc-mips.c:10441
 msgid "-call_shared is supported only for ELF format"
 msgstr "-call_shared yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10537 config/tc-mips.c:11848 config/tc-mips.c:12086
+#: config/tc-mips.c:10448 config/tc-mips.c:10477 config/tc-mips.c:11571
+#: config/tc-mips.c:11805
 msgid "-G may not be used with SVR4 PIC code"
 msgstr "-G SVR4 PIC kodu ile kullanılamaz"
 
-#: config/tc-mips.c:10546
+#: config/tc-mips.c:10457
 msgid "-non_shared is supported only for ELF format"
 msgstr "-non_shared yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10564
-msgid "-G is not supported for this configuration"
-msgstr "-G bu ayarlarda desteklenmiyor"
-
-#: config/tc-mips.c:10569
-msgid "-G may not be used with SVR4 or embedded PIC code"
-msgstr "-G SVR4 veya gömülü PIC kodu ile kullanılamaz"
-
-#: config/tc-mips.c:10583
+#: config/tc-mips.c:10488
 msgid "-32 is supported for ELF format only"
 msgstr "-32 yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10592
+#: config/tc-mips.c:10497
 msgid "-n32 is supported for ELF format only"
 msgstr "-n32 yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10601
+#: config/tc-mips.c:10506
 msgid "-64 is supported for ELF format only"
 msgstr "-64 yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10606 config/tc-mips.c:10643
+#: config/tc-mips.c:10511 config/tc-mips.c:10548
 msgid "No compiled in support for 64 bit object file format"
 msgstr "64 bitlik nesne dosyası biçemi için derlenmiş destek yok"
 
-#: config/tc-mips.c:10630
+#: config/tc-mips.c:10535
 msgid "-mabi is supported for ELF format only"
 msgstr "-mabi yalnız ELF biçemi için destekleniyor"
 
-#: config/tc-mips.c:10650
+#: config/tc-mips.c:10555
 #, c-format
 msgid "invalid abi -mabi=%s"
 msgstr "geçersiz abi -mabi=%s"
 
-#: config/tc-mips.c:10717
+#: config/tc-mips.c:10629
 msgid "-G not supported in this configuration."
 msgstr "-G bu ayarlarda desteklenmiyor."
 
-#: config/tc-mips.c:10743
+#: config/tc-mips.c:10655
 #, c-format
 msgid "-%s conflicts with the other architecture options, which imply -%s"
 msgstr "-%s, -%s gerektiren diğer mimari seçenekleri ile çelişiyor"
 
-#: config/tc-mips.c:10774
+#: config/tc-mips.c:10686
 msgid "-mgp64 used with a 32-bit processor"
 msgstr "32 bitlik işlemci ile -mgp64 kullanılmış"
 
-#: config/tc-mips.c:10776
+#: config/tc-mips.c:10688
 msgid "-mgp32 used with a 64-bit ABI"
 msgstr "64 bit ABI ile -mgp32 kullanılmış"
 
-#: config/tc-mips.c:10778
+#: config/tc-mips.c:10690
 msgid "-mgp64 used with a 32-bit ABI"
 msgstr "32 bit ABI ile -mgp64 kullanılmış"
 
-#: config/tc-mips.c:10808
+#: config/tc-mips.c:10720
 msgid "trap exception not supported at ISA 1"
 msgstr "tuzak olağandışılığı ISA 1'de desteklenmiyor"
 
-#: config/tc-mips.c:10956
-#, c-format
-msgid "Unmatched %%hi reloc"
-msgstr "EÅŸleÅŸmeyen %%hi yerdeÄŸiÅŸimi"
-
-#: config/tc-mips.c:11048
+#: config/tc-mips.c:10974
 msgid "Cannot branch to undefined symbol."
 msgstr "Tanımsız sembole dallanılamaz."
 
-#: config/tc-mips.c:11055
+#: config/tc-mips.c:10981
 msgid "Cannot branch to symbol in another section."
 msgstr "Değişik bölümdeki sembole dallanılamaz."
 
-#: config/tc-mips.c:11064
+#: config/tc-mips.c:10990
 msgid "Pretending global symbol used as branch target is local."
 msgstr "Dal hedefi olarak kullanılan global sembol, yerel gibi değerlendirildi."
 
-#: config/tc-mips.c:11229
-msgid "Invalid PC relative reloc"
-msgstr "Geçersiz PC göreli yerdeğişim"
-
-#: config/tc-mips.c:11324 config/tc-sparc.c:3185 config/tc-sparc.c:3192
-#: config/tc-sparc.c:3199 config/tc-sparc.c:3206 config/tc-sparc.c:3213
-#: config/tc-sparc.c:3222 config/tc-sparc.c:3233 config/tc-sparc.c:3255
-#: config/tc-sparc.c:3279 write.c:998 write.c:1070
+#: config/tc-mips.c:11147 config/tc-sparc.c:3230 config/tc-sparc.c:3237
+#: config/tc-sparc.c:3244 config/tc-sparc.c:3251 config/tc-sparc.c:3258
+#: config/tc-sparc.c:3267 config/tc-sparc.c:3278 config/tc-sparc.c:3300
+#: config/tc-sparc.c:3324 write.c:962 write.c:1034
 msgid "relocation overflow"
 msgstr "yerdeğişim taşması"
 
-#: config/tc-mips.c:11334
+#: config/tc-mips.c:11157
 #, c-format
 msgid "Branch to odd address (%lx)"
 msgstr "Tek sayılı adrese dal (%lx)"
 
-#: config/tc-mips.c:11383
+#: config/tc-mips.c:11206
 msgid "Branch out of range"
 msgstr "Dal kapsam dışı"
 
-#: config/tc-mips.c:11490
-#, c-format
-msgid "%08lx  UNDEFINED\n"
-msgstr "%08lx  TANIMSIZ\n"
-
-#: config/tc-mips.c:11549
+#: config/tc-mips.c:11285
 #, c-format
 msgid "Alignment too large: %d. assumed."
 msgstr "Hizalama fazla büyük: %d. varsayıldı."
 
-#: config/tc-mips.c:11552
+#: config/tc-mips.c:11288
 msgid "Alignment negative: 0 assumed."
 msgstr "Hizalama negatif: 0 varsayıldı."
 
-#: config/tc-mips.c:11639
-msgid "No read only data section in this object file format"
-msgstr "Bu nesne dosyası biçeminde salt okunur veri bölümü yok"
-
-#: config/tc-mips.c:11662
-msgid "Global pointers not supported; recompile -G 0"
-msgstr "Evrensel imleyiciler desteklenmiyor; -G 0 ile yeniden derleyin"
-
-#: config/tc-mips.c:11804
+#: config/tc-mips.c:11527
 #, c-format
 msgid "%s: no such section"
 msgstr "%s: böyle bir bölüm yok"
 
-#: config/tc-mips.c:11843
+#: config/tc-mips.c:11566
 #, c-format
 msgid ".option pic%d not supported"
 msgstr ".option pic%d desteklenmiyor"
 
-#: config/tc-mips.c:11854
+#: config/tc-mips.c:11577
 #, c-format
 msgid "Unrecognized option \"%s\""
 msgstr "Bilinmeyen seçenek \"%s\""
 
-#: config/tc-mips.c:11916
+#: config/tc-mips.c:11639
 msgid "`noreorder' must be set before `nomacro'"
 msgstr "`nomacro'dan önce `noreorder' atanmalı"
 
-#: config/tc-mips.c:11988
+#: config/tc-mips.c:11690
 #, c-format
 msgid "unknown architecture %s"
 msgstr "`%s' mimarisi bilinmiyor"
 
-#: config/tc-mips.c:11996 config/tc-mips.c:12017
+#: config/tc-mips.c:11703 config/tc-mips.c:11733
 #, c-format
 msgid "unknown ISA level %s"
 msgstr "bilinmeyen ISA seviyesi %s"
 
-#: config/tc-mips.c:12045
+#: config/tc-mips.c:11711
+#, fuzzy, c-format
+msgid "unknown ISA or architecture %s"
+msgstr "`%s' mimarisi bilinmiyor"
+
+#: config/tc-mips.c:11761
 msgid ".set pop with no .set push"
 msgstr ".set push olmaksızın .set pop"
 
-#: config/tc-mips.c:12069
+#: config/tc-mips.c:11789
 #, c-format
 msgid "Tried to set unrecognized symbol: %s\n"
 msgstr "Bilinmeyen sembol atanmaya çalışıldı: %s\n"
 
-#: config/tc-mips.c:12119
+#: config/tc-mips.c:11847
 msgid ".cpload not in noreorder section"
 msgstr ".cpload, `noreorder' bölümünde değil"
 
-#: config/tc-mips.c:12175 config/tc-mips.c:12194
+#: config/tc-mips.c:11916 config/tc-mips.c:11935
 msgid "missing argument separator ',' for .cpsetup"
 msgstr ".cpsetup için eksik argüman ayracı ','"
 
-#: config/tc-mips.c:12372
+#: config/tc-mips.c:12125
 msgid "Unsupported use of .gpword"
 msgstr ".gpword'un desteklenmeyen kullanımı"
 
-#: config/tc-mips.c:12408
+#: config/tc-mips.c:12161
 msgid "Unsupported use of .gpdword"
 msgstr ".gpdword'un desteklenmeyen kullanımı"
 
-#: config/tc-mips.c:12543
+#: config/tc-mips.c:12293
 msgid "expected `$'"
 msgstr "`$' beklendi"
 
-#: config/tc-mips.c:12551
+#: config/tc-mips.c:12301
 msgid "Bad register number"
 msgstr "Hatalı yazmaç numarası"
 
-#: config/tc-mips.c:12599
+#: config/tc-mips.c:12349
 msgid "Unrecognized register name"
 msgstr "Bilinmeyen yazmaç ismi"
 
-#: config/tc-mips.c:12834
+#: config/tc-mips.c:12582
 msgid "unsupported PC relative reference to different section"
 msgstr "Değişik bölüme desteklenmeyen PC göreli başvuru"
 
-#: config/tc-mips.c:12947
+#: config/tc-mips.c:12695 config/tc-xtensa.c:1624 config/tc-xtensa.c:1835
 msgid "unsupported relocation"
 msgstr "desteklenmeyen yerdeÄŸiÅŸim"
 
-#: config/tc-mips.c:13062
-msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
-msgstr ""
-"\".set noat\"dan sonra kullanılan AT veya \".set nomacro\"dan sonra\n"
-"kullanılan makro"
-
-#: config/tc-mips.c:13125
-msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
-msgstr "tc-mips.c:tc_gen_reloc içinde fx_r_type'ı tekrar kontrol edin"
-
-#: config/tc-mips.c:13340 config/tc-sh.c:3800
+#: config/tc-mips.c:12901 config/tc-sh.c:4302
 #, c-format
 msgid "Can not represent %s relocation in this object file format"
 msgstr "Bu nesne dosya biçeminde %s yerdeğişimi gösterilemez"
 
-#: config/tc-mips.c:13429
+#: config/tc-mips.c:12987
 msgid "relaxed out-of-range branch into a jump"
 msgstr "kapsam dışı dal, sıçrama olarak esnetildi"
 
-#: config/tc-mips.c:13902
+#: config/tc-mips.c:13501
 msgid "missing .end at end of assembly"
 msgstr "çevrimin sonunda `.end' eksik"
 
-#: config/tc-mips.c:13917
+#: config/tc-mips.c:13516
 msgid "expected simple number"
 msgstr "Basit sayı beklendi."
 
-#: config/tc-mips.c:13943
+#: config/tc-mips.c:13542
 #, c-format
 msgid " *input_line_pointer == '%c' 0x%02x\n"
 msgstr " *input_line_pointer == '%c' 0x%02x\n"
 
-#: config/tc-mips.c:13945
+#: config/tc-mips.c:13544
 msgid "invalid number"
 msgstr "Geçersiz sayı"
 
-#: config/tc-mips.c:14018
+#: config/tc-mips.c:13617
 msgid ".end not in text section"
 msgstr ".end metin bölümünde değil"
 
-#: config/tc-mips.c:14022
+#: config/tc-mips.c:13621
 msgid ".end directive without a preceding .ent directive."
 msgstr "Öncesinde .ent yönergesi olmayan .end yönergesi"
 
-#: config/tc-mips.c:14031
+#: config/tc-mips.c:13630
 msgid ".end symbol does not match .ent symbol."
 msgstr ".end sembolü .ent sembolü ile eşleşmiyor."
 
-#: config/tc-mips.c:14038
+#: config/tc-mips.c:13637
 msgid ".end directive missing or unknown symbol"
 msgstr ".end yönergesi eksik veya bilinmeyen sembol"
 
-#: config/tc-mips.c:14098
+#: config/tc-mips.c:13713
 msgid ".ent or .aent not in text section."
 msgstr ".ent veya .aent metin bölümünde değil."
 
-#: config/tc-mips.c:14101
+#: config/tc-mips.c:13716
 msgid "missing .end"
 msgstr "eksik `.end'"
 
-#: config/tc-mips.c:14153
+#: config/tc-mips.c:13768
 msgid "Bad .frame directive"
 msgstr "Hatalı .frame yönergesi"
 
-#: config/tc-mips.c:14185
+#: config/tc-mips.c:13800
 msgid ".mask/.fmask outside of .ent"
 msgstr ".ent dışında .mask/.fmask"
 
-#: config/tc-mips.c:14192
+#: config/tc-mips.c:13807
 msgid "Bad .mask/.fmask directive"
 msgstr "Hatalı .mask/.fmask yönergesi"
 
-#: config/tc-mips.c:14470
+#: config/tc-mips.c:14064
+#, fuzzy, c-format
 msgid ""
 "MIPS options:\n"
-"-membedded-pic\t\tgenerate embedded position independent code\n"
 "-EB\t\t\tgenerate big endian output\n"
 "-EL\t\t\tgenerate little endian output\n"
 "-g, -g2\t\t\tdo not remove unneeded NOPs or swap branches\n"
@@ -6930,7 +7697,8 @@ msgstr ""
 "-G SAYI             SAYI bayta kadar nesnelere başvuruya örtük olarak gp\n"
 "                    yazmacı ile izin verir [öntanımlı 8]\n"
 
-#: config/tc-mips.c:14478
+#: config/tc-mips.c:14071
+#, fuzzy, c-format
 msgid ""
 "-mips1\t\t\tgenerate MIPS ISA I instructions\n"
 "-mips2\t\t\tgenerate MIPS ISA II instructions\n"
@@ -6940,6 +7708,7 @@ msgid ""
 "-mips32                 generate MIPS32 ISA instructions\n"
 "-mips32r2               generate MIPS32 release 2 ISA instructions\n"
 "-mips64                 generate MIPS64 ISA instructions\n"
+"-mips64r2               generate MIPS64 release 2 ISA instructions\n"
 "-march=CPU/-mtune=CPU\tgenerate code/schedule for CPU, where CPU is one of:\n"
 msgstr ""
 "-mips1              MIPS ISA I işlemleri üretir\n"
@@ -6952,7 +7721,8 @@ msgstr ""
 "-mips64             MIPS64 ISA işlemleri üretir\n"
 "-march=İŞL/-mtune=İŞL      İŞL işlemcisi için kod üretir. İŞL seçenekleri:\n"
 
-#: config/tc-mips.c:14496
+#: config/tc-mips.c:14090
+#, c-format
 msgid ""
 "-mCPU\t\t\tequivalent to -march=CPU -mtune=CPU. Deprecated.\n"
 "-no-mCPU\t\tdon't generate code specific to CPU.\n"
@@ -6962,7 +7732,8 @@ msgstr ""
 "-no-mİŞL            İŞL işlemcisine özgü kod üretmez.\n"
 "                    -mİŞL ve -no-mİŞL için İŞL seçenekleri:\n"
 
-#: config/tc-mips.c:14509
+#: config/tc-mips.c:14103
+#, c-format
 msgid ""
 "-mips16\t\t\tgenerate mips16 instructions\n"
 "-no-mips16\t\tdo not generate mips16 instructions\n"
@@ -6970,13 +7741,16 @@ msgstr ""
 "-mips16             mips16 işlemleri üretir\n"
 "-no-mips16          mips16 işlemleri üretmez\n"
 
-#: config/tc-mips.c:14512
+#: config/tc-mips.c:14106
+#, fuzzy, c-format
 msgid ""
+"-mfix-vr4120\t\twork around certain VR4120 errata\n"
 "-mgp32\t\t\tuse 32-bit GPRs, regardless of the chosen ISA\n"
 "-mfp32\t\t\tuse 32-bit FPRs, regardless of the chosen ISA\n"
+"-mno-shared\t\toptimize output for executables\n"
+"-msym32\t\t\tassume all symbols have 32-bit values\n"
 "-O0\t\t\tremove unneeded NOPs, do not swap branches\n"
 "-O\t\t\tremove unneeded NOPs and swap branches\n"
-"-n\t\t\twarn about NOPs generated from macros\n"
 "--[no-]construct-floats [dis]allow floating point values to be constructed\n"
 "--trap, --no-break\ttrap exception on div by 0 and mult overflow\n"
 "--break, --no-trap\tbreak exception on div by 0 and mult overflow\n"
@@ -6993,11 +7767,15 @@ msgstr ""
 "--break, --no-trap          sıfırla bölme ve çarpma taşmasında olağandışılığı\n"
 "                            yakalamaz, durdurur\n"
 
-#: config/tc-mips.c:14522
+#: config/tc-mips.c:14118
+#, fuzzy, c-format
 msgid ""
 "-KPIC, -call_shared\tgenerate SVR4 position independent code\n"
 "-non_shared\t\tdo not generate position independent code\n"
 "-xgot\t\t\tassume a 32 bit GOT\n"
+"-mpdr, -mno-pdr\t\tenable/disable creation of .pdr sections\n"
+"-mshared, -mno-shared   disable/enable .cpload optimization for\n"
+"                        non-shared code\n"
 "-mabi=ABI\t\tcreate ABI conformant object file for:\n"
 msgstr ""
 "-KPIC, -call_shared    SVR4 için yerden bağımsız kod üretir\n"
@@ -7005,7 +7783,8 @@ msgstr ""
 "-xgot                  32 bitlik GOT varsayar\n"
 "-mabi=ABI              ABI uyumlu nesne dosyası oluşturur:\n"
 
-#: config/tc-mips.c:14538
+#: config/tc-mips.c:14137
+#, c-format
 msgid ""
 "-32\t\t\tcreate o32 ABI object file (default)\n"
 "-n32\t\t\tcreate n32 ABI object file\n"
@@ -7015,11 +7794,13 @@ msgstr ""
 "-n32\t\t\tn32 ABI nesne dosyası oluşturur\n"
 "-64\t\t\t64 ABI nesne dosyası oluşturur\n"
 
-#: config/tc-mmix.c:677
+#: config/tc-mmix.c:713
+#, c-format
 msgid " MMIX-specific command line options:\n"
 msgstr " MMIX'a özgü komut satırı seçenekleri:\n"
 
-#: config/tc-mmix.c:678
+#: config/tc-mmix.c:714
+#, c-format
 msgid ""
 "  -fixed-special-register-names\n"
 "                          Allow only the original special register names.\n"
@@ -7027,19 +7808,23 @@ msgstr ""
 "  -fixed-special-register-names\n"
 "                          Yalnız orjinal özel yazmaç adlarına izin verir.\n"
 
-#: config/tc-mmix.c:681
+#: config/tc-mmix.c:717
+#, c-format
 msgid "  -globalize-symbols      Make all symbols global.\n"
 msgstr "  -globalize-symbols      Bütün sembolleri evrensel yapar.\n"
 
-#: config/tc-mmix.c:683
+#: config/tc-mmix.c:719
+#, c-format
 msgid "  -gnu-syntax             Turn off mmixal syntax compatibility.\n"
 msgstr "  -gnu-syntax             mmixal sözdizim uyumluluğunu etkisizleştirir.\n"
 
-#: config/tc-mmix.c:685
+#: config/tc-mmix.c:721
+#, c-format
 msgid "  -relax                  Create linker relaxable code.\n"
 msgstr "  -relax                 bağlayıcı tarafından gevşetilebilen kod üretir\n"
 
-#: config/tc-mmix.c:687
+#: config/tc-mmix.c:723
+#, c-format
 msgid ""
 "  -no-predefined-syms     Do not provide mmixal built-in constants.\n"
 "                          Implies -fixed-special-register-names.\n"
@@ -7048,7 +7833,8 @@ msgstr ""
 "                          -fixed-special-register-names seçeneğini örtük\n"
 "                          olarak etkinleÅŸtirir.\n"
 
-#: config/tc-mmix.c:690
+#: config/tc-mmix.c:726
+#, c-format
 msgid ""
 "  -no-expand              Do not expand GETA, branches, PUSHJ or JUMP\n"
 "                          into multiple instructions.\n"
@@ -7056,17 +7842,20 @@ msgstr ""
 "  -no-expand              GETA, dallar, PUSHJ veya JUMP'ı birden fazla işlem\n"
 "                          olarak açmaz.\n"
 
-#: config/tc-mmix.c:693
+#: config/tc-mmix.c:729
+#, c-format
 msgid "  -no-merge-gregs         Do not merge GREG definitions with nearby values.\n"
 msgstr "  -no-merge-gregs         GREG tanımlarını yaklaşık değerlerle birleştirmez.\n"
 
-#: config/tc-mmix.c:695
+#: config/tc-mmix.c:731
+#, c-format
 msgid "  -linker-allocated-gregs If there's no suitable GREG definition for the                          operands of an instruction, let the linker resolve.\n"
 msgstr ""
 "  -linker-allocated-gregs Eğer bir işlemin işlenenleri için uygun GREG tanımı\n"
 "                          yoksa, bağlayıcının çözümlemesine bırakır.\n"
 
-#: config/tc-mmix.c:698
+#: config/tc-mmix.c:734
+#, c-format
 msgid ""
 "  -x                      Do not warn when an operand to GETA, a branch,\n"
 "                          PUSHJ or JUMP is not known to be within range.\n"
@@ -7079,185 +7868,185 @@ msgstr ""
 "                          -linker-allocated-gregs seçeneğinin kullanıldığını\n"
 "                          varsayar."
 
-#: config/tc-mmix.c:825
+#: config/tc-mmix.c:861
 #, c-format
 msgid "unknown opcode: `%s'"
 msgstr "bilinmeyen opkod `%s'"
 
-#: config/tc-mmix.c:947 config/tc-mmix.c:962
+#: config/tc-mmix.c:983 config/tc-mmix.c:998
 msgid "specified location wasn't TETRA-aligned"
 msgstr "belirtilen konum TETRA hizalanmamış."
 
-#: config/tc-mmix.c:949 config/tc-mmix.c:964 config/tc-mmix.c:4015
-#: config/tc-mmix.c:4031
+#: config/tc-mmix.c:985 config/tc-mmix.c:1000 config/tc-mmix.c:4186
+#: config/tc-mmix.c:4202
 msgid "unaligned data at an absolute location is not supported"
 msgstr "kesin konumlarda hizalanmamış veri desteklenmiyor"
 
-#: config/tc-mmix.c:1074
+#: config/tc-mmix.c:1110
 #, c-format
 msgid "invalid operand to opcode %s: `%s'"
 msgstr "opkod %s için geçersiz işlenen: `%s'"
 
-#: config/tc-mmix.c:1096 config/tc-mmix.c:1123 config/tc-mmix.c:1156
-#: config/tc-mmix.c:1164 config/tc-mmix.c:1181 config/tc-mmix.c:1209
-#: config/tc-mmix.c:1230 config/tc-mmix.c:1255 config/tc-mmix.c:1303
-#: config/tc-mmix.c:1401 config/tc-mmix.c:1426 config/tc-mmix.c:1458
-#: config/tc-mmix.c:1490 config/tc-mmix.c:1520 config/tc-mmix.c:1573
-#: config/tc-mmix.c:1590 config/tc-mmix.c:1617 config/tc-mmix.c:1645
-#: config/tc-mmix.c:1672 config/tc-mmix.c:1698 config/tc-mmix.c:1714
-#: config/tc-mmix.c:1740 config/tc-mmix.c:1756 config/tc-mmix.c:1772
-#: config/tc-mmix.c:1835 config/tc-mmix.c:1851
+#: config/tc-mmix.c:1132 config/tc-mmix.c:1159 config/tc-mmix.c:1192
+#: config/tc-mmix.c:1200 config/tc-mmix.c:1217 config/tc-mmix.c:1245
+#: config/tc-mmix.c:1266 config/tc-mmix.c:1291 config/tc-mmix.c:1339
+#: config/tc-mmix.c:1437 config/tc-mmix.c:1462 config/tc-mmix.c:1494
+#: config/tc-mmix.c:1526 config/tc-mmix.c:1556 config/tc-mmix.c:1609
+#: config/tc-mmix.c:1626 config/tc-mmix.c:1653 config/tc-mmix.c:1681
+#: config/tc-mmix.c:1708 config/tc-mmix.c:1734 config/tc-mmix.c:1750
+#: config/tc-mmix.c:1776 config/tc-mmix.c:1792 config/tc-mmix.c:1808
+#: config/tc-mmix.c:1871 config/tc-mmix.c:1887
 #, c-format
 msgid "invalid operands to opcode %s: `%s'"
 msgstr "opkod %s için geçersiz işlenenler: `%s'"
 
-#: config/tc-mmix.c:1828
+#: config/tc-mmix.c:1864
 #, c-format
 msgid "unsupported operands to %s: `%s'"
 msgstr "%s için desteklenmeyen işlenenler: `%s'"
 
-#: config/tc-mmix.c:1956
+#: config/tc-mmix.c:1992
 msgid "internal: mmix_prefix_name but empty prefix"
 msgstr "iç: mmix_prefix_name verilmiş fakat önek boş"
 
-#: config/tc-mmix.c:2001
+#: config/tc-mmix.c:2037
 #, c-format
 msgid "too many GREG registers allocated (max %d)"
 msgstr "çok fazla GREG yazmacı ayrılmış (maksimum %d)"
 
-#: config/tc-mmix.c:2061
+#: config/tc-mmix.c:2097
 msgid "BSPEC already active.  Nesting is not supported."
 msgstr "BSPEC zaten etkin.  Yuvalanma desteklenmiyor."
 
-#: config/tc-mmix.c:2070
+#: config/tc-mmix.c:2106
 msgid "invalid BSPEC expression"
 msgstr "geçersiz BSPEC ifadesi"
 
-#: config/tc-mmix.c:2086
+#: config/tc-mmix.c:2122
 #, c-format
 msgid "can't create section %s"
 msgstr "%s bölümü oluşturulamıyor"
 
-#: config/tc-mmix.c:2091
+#: config/tc-mmix.c:2127
 #, c-format
 msgid "can't set section flags for section %s"
 msgstr "%s bölümü için bölüm bayrakları atanamadı"
 
-#: config/tc-mmix.c:2113
+#: config/tc-mmix.c:2149
 msgid "ESPEC without preceding BSPEC"
 msgstr "öncesinde BSPEC olmayan ESPEC"
 
-#: config/tc-mmix.c:2143
+#: config/tc-mmix.c:2179
 msgid "missing local expression"
 msgstr "Yerel ifade eksik"
 
-#: config/tc-mmix.c:2363
+#: config/tc-mmix.c:2424
 msgid "operand out of range, instruction expanded"
 msgstr "işlenen değeri işlem için kapsam dışı, işlem genişletildi"
 
 #. The BFD_RELOC_MMIX_LOCAL-specific message is supposed to be
 #. user-friendly, though a little bit non-substantial.
-#: config/tc-mmix.c:2620
+#: config/tc-mmix.c:2682
 msgid "directive LOCAL must be placed in code or data"
 msgstr "LOCAL (yerel) yönergesi kod veya veri içine yerleştirilmelidir"
 
-#: config/tc-mmix.c:2621
+#: config/tc-mmix.c:2683
 msgid "internal confusion: relocation in a section without contents"
 msgstr "iç karışıklık: içeriği olmayan bir bölüme yerdeğişim"
 
-#: config/tc-mmix.c:2734
+#: config/tc-mmix.c:2797
 msgid "internal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to section"
 msgstr "içsel: BFD_RELOC_MMIX_BASE_PLUS_OFFSET bölüme çözümlenmedi"
 
-#: config/tc-mmix.c:2782
+#: config/tc-mmix.c:2845
 msgid "no suitable GREG definition for operands"
 msgstr "işlenenler için uygun GREG tanımı yok"
 
-#: config/tc-mmix.c:2841
+#: config/tc-mmix.c:2904
 msgid "operands were not reducible at assembly-time"
 msgstr "işlenenler çevrim esnasında indirgenemiyor"
 
-#: config/tc-mmix.c:2868
+#: config/tc-mmix.c:2931
 #, c-format
 msgid "cannot generate relocation type for symbol %s, code %s"
 msgstr "%s sembolü, %s kodu için yerdeğişim oluşturulamadı."
 
-#: config/tc-mmix.c:2888
+#: config/tc-mmix.c:2951
 #, c-format
 msgid "internal: unhandled label %s"
 msgstr "desteklenmeyen etiket türü %s"
 
-#: config/tc-mmix.c:2942
+#: config/tc-mmix.c:3005
 msgid "[0-9]H labels may not appear alone on a line"
 msgstr " [0-9]H etiketleri bir satırda tek başına olamaz"
 
-#: config/tc-mmix.c:2951
+#: config/tc-mmix.c:3014
 msgid "[0-9]H labels do not mix with dot-pseudos"
 msgstr "[0-9]H etiketleri dot-pseudo'larla karıştırılamaz"
 
-#: config/tc-mmix.c:3015
+#: config/tc-mmix.c:3078
 msgid "invalid characters in input"
 msgstr "Girdide geçersiz karakterler"
 
-#: config/tc-mmix.c:3119
+#: config/tc-mmix.c:3182
 msgid "empty label field for IS"
 msgstr "IS için boş etiket alanı"
 
-#: config/tc-mmix.c:3344
+#: config/tc-mmix.c:3515
 #, c-format
 msgid "internal: unexpected relax type %d:%d"
 msgstr "iç hata: beklenmeyen genişleme türü %d:%d"
 
-#: config/tc-mmix.c:3366
+#: config/tc-mmix.c:3537
 msgid "BSPEC without ESPEC."
 msgstr "ESPEC'siz BSPEC."
 
-#: config/tc-mmix.c:3568
+#: config/tc-mmix.c:3739
 msgid "GREG expression too complicated"
 msgstr "GREG ifadesi fazla karmaşık"
 
-#: config/tc-mmix.c:3583
+#: config/tc-mmix.c:3754
 msgid "internal: GREG expression not resolved to section"
 msgstr "içsel: GREG ifadesi bölüme çözümlenmedi"
 
-#: config/tc-mmix.c:3634
+#: config/tc-mmix.c:3805
 msgid "register section has contents\n"
 msgstr "yazmaç bölümünde içerik var\n"
 
-#: config/tc-mmix.c:3768
+#: config/tc-mmix.c:3939
 msgid "section change from within a BSPEC/ESPEC pair is not supported"
 msgstr "BSPEC/ESPEC çiftinin içinden bölüm değişikliği desteklenmiyor"
 
-#: config/tc-mmix.c:3790
+#: config/tc-mmix.c:3961
 msgid "directive LOC from within a BSPEC/ESPEC pair is not supported"
 msgstr "BSPEC/ESPEC çiftinin içinden LOC yönergesi desteklenmiyor"
 
-#: config/tc-mmix.c:3801
+#: config/tc-mmix.c:3972
 msgid "invalid LOC expression"
 msgstr "geçersiz LOC ifadesi"
 
-#: config/tc-mmix.c:3826 config/tc-mmix.c:3852
+#: config/tc-mmix.c:3997 config/tc-mmix.c:4023
 msgid "LOC expression stepping backwards is not supported"
 msgstr "LOC ifadesi geri adımlama desteklenmiyor"
 
 #. We will only get here in rare cases involving #NO_APP,
 #. where the unterminated string is not recognized by the
 #. preformatting pass.
-#: config/tc-mmix.c:3936 config/tc-mmix.c:4097
+#: config/tc-mmix.c:4107 config/tc-mmix.c:4268
 msgid "unterminated string"
 msgstr "sonlanmamış dizge"
 
-#: config/tc-mmix.c:3953
+#: config/tc-mmix.c:4124
 msgid "BYTE expression not a pure number"
 msgstr "BYTE ifadesi salt sayı değil"
 
 #. Note that mmixal does not allow negative numbers in
 #. BYTE sequences, so neither should we.
-#: config/tc-mmix.c:3962
+#: config/tc-mmix.c:4133
 msgid "BYTE expression not in the range 0..255"
 msgstr "BYTE ifadesi 0..255 aralığında değil"
 
-#: config/tc-mmix.c:4013 config/tc-mmix.c:4029
+#: config/tc-mmix.c:4184 config/tc-mmix.c:4200
 msgid "data item with alignment larger than location"
 msgstr "yerden daha büyük hizalamalı veri"
 
@@ -7268,6 +8057,7 @@ msgid "`&' serial number operator is not supported"
 msgstr "`&' seri sayı işlemimi desteklenmiyor"
 
 #: config/tc-mn10200.c:319
+#, c-format
 msgid ""
 "MN10200 options:\n"
 "none yet\n"
@@ -7275,30 +8065,20 @@ msgstr ""
 "MN10200 seçenekleri:\n"
 "henüz yok\n"
 
-#: config/tc-mn10200.c:793 config/tc-mn10300.c:1387 config/tc-ppc.c:2088
-#: config/tc-s390.c:1540 config/tc-v850.c:1678
+#: config/tc-mn10200.c:793 config/tc-mn10300.c:1392 config/tc-ppc.c:2120
+#: config/tc-s390.c:1522 config/tc-v850.c:1693
 #, c-format
 msgid "Unrecognized opcode: `%s'"
 msgstr "Bilinmeyen opkod: `%s'"
 
-#: config/tc-mn10200.c:1036 config/tc-mn10300.c:1960 config/tc-ppc.c:2566
-#: config/tc-s390.c:1455 config/tc-v850.c:2101
+#: config/tc-mn10200.c:1036 config/tc-mn10300.c:1965 config/tc-ppc.c:2599
+#: config/tc-s390.c:1437 config/tc-v850.c:2110
 #, c-format
 msgid "junk at end of line: `%s'"
 msgstr "satır sonunda bozukluk: `%s'"
 
-#: config/tc-mn10200.c:1242 write.c:2691
+#: config/tc-mn10300.c:695
 #, c-format
-msgid "can't resolve `%s' {%s section} - `%s' {%s section}"
-msgstr "`%s' çözümlenemedi {%s bölümü} - `%s' {%s bölümü}"
-
-#: config/tc-mn10200.c:1347 config/tc-mn10300.c:2589 config/tc-ppc.c:1426
-#: config/tc-v850.c:1607
-#, c-format
-msgid "operand out of range (%s not between %ld and %ld)"
-msgstr "işlenen kapsam dışında (%s, %ld ve %ld arasında değil)"
-
-#: config/tc-mn10300.c:690
 msgid ""
 "MN10300 options:\n"
 "none yet\n"
@@ -7306,35 +8086,59 @@ msgstr ""
 "MN10300 seçenekleri:\n"
 "henüz yok\n"
 
-#: config/tc-mn10300.c:1356 config/tc-sh.c:805 config/tc-xtensa.c:5177
-#: read.c:3764
+#: config/tc-mn10300.c:1361 config/tc-sh.c:776 read.c:3729
 #, c-format
 msgid "unsupported BFD relocation size %u"
 msgstr "desteklenmeyen BFD yerdeÄŸiÅŸim boyu %u"
 
-#: config/tc-mn10300.c:1404
+#: config/tc-mn10300.c:1409
 msgid "Invalid opcode/operands"
 msgstr "Geçersiz opkod/işlenenler"
 
-#: config/tc-mn10300.c:1931
+#: config/tc-mn10300.c:1936
 msgid "Invalid register specification."
 msgstr "Geçersiz yazmaç bildirimi."
 
-#: config/tc-mn10300.c:2514
+#: config/tc-mn10300.c:2519
 #, c-format
 msgid "Bad relocation fixup type (%d)"
 msgstr "Hatalı yerdeğişim düzeltme türü (%d)"
 
-#: config/tc-msp430.c:170
+#: config/tc-msp430.c:502
+msgid ".profiler pseudo requires at least two operands."
+msgstr ""
+
+#: config/tc-msp430.c:561
+msgid "unknown profiling flag - ignored."
+msgstr ""
+
+#: config/tc-msp430.c:577
+#, fuzzy
+msgid "ambigious flags combination - '.profiler' directive ignored."
+msgstr "Geri dönülecek önceki bölüm yok. Yönerge yoksayıldı."
+
+#: config/tc-msp430.c:587
+#, fuzzy
+msgid "profiling in absolute section? Hm..."
+msgstr "kesin bölümde dolgu değeri yoksayıldı"
+
+#: config/tc-msp430.c:674
+#, c-format
 msgid "Known MCU names:\n"
 msgstr "Bilinen MCU adları:\n"
 
-#: config/tc-msp430.c:173
+#: config/tc-msp430.c:677
 #, c-format
 msgid "\t %s\n"
 msgstr "\t %s\n"
 
-#: config/tc-msp430.c:183
+#: config/tc-msp430.c:703
+#, c-format
+msgid "redefinition of mcu type %s' to %s'"
+msgstr "mcu türü `%s'den `%s'ye yeniden tanımlandı"
+
+#: config/tc-msp430.c:733
+#, fuzzy, c-format
 msgid ""
 "MSP430 options:\n"
 "  -mmcu=[msp430-name] select microcontroller type\n"
@@ -7348,10 +8152,14 @@ msgid ""
 "                  msp430x147  msp430x148  msp430x149\n"
 "                  msp430x155  msp430x156  msp430x157\n"
 "                  msp430x167  msp430x168  msp430x169\n"
+"                  msp430x1610 msp430x1611 msp430x1612\n"
 "                  msp430x311  msp430x312  msp430x313  msp430x314  msp430x315\n"
 "                  msp430x323  msp430x325\n"
 "                  msp430x336  msp430x337\n"
-"                  msp430x412  msp430x413\n"
+"                  msp430x412  msp430x413  msp430x415  msp430x417\n"
+"                  msp430xE423 msp430xE425 msp430E427\n"
+"                  msp430xW423 msp430xW425 msp430W427\n"
+"                  msp430xG437 msp430xG438 msp430G439\n"
 "                  msp430x435  msp430x436  msp430x437\n"
 "                  msp430x447  msp430x448  msp430x449\n"
 msgstr ""
@@ -7374,120 +8182,145 @@ msgstr ""
 "                  msp430x435  msp430x436  msp430x437\n"
 "                  msp430x447  msp430x448  msp430x449\n"
 
-#: config/tc-msp430.c:263
-#, c-format
-msgid "redefinition of mcu type %s' to %s'"
-msgstr "mcu türü `%s'den `%s'ye yeniden tanımlandı"
-
-#: config/tc-msp430.c:496
-#, c-format
-msgid "instruction %s requires %d operand(s)"
-msgstr "'%s' işlemi için %d işlenen gerekli"
-
-#: config/tc-msp430.c:743
-#, c-format
-msgid "Even number required. Rounded to %d"
-msgstr "Çift sayı gerekli. %d'ye yuvarlandı"
-
-#: config/tc-msp430.c:754
-#, c-format
-msgid "Wrong displacement  %d"
-msgstr "Yanlış yerdeğiştirme  %d"
-
-#: config/tc-msp430.c:771
-msgid "instruction requires label sans '$'"
-msgstr "işlem, '$' içermeyen etiket gerektirir"
-
-#: config/tc-msp430.c:777
-msgid "instruction requires label or value in range -511:512"
-msgstr "işlem etiket veya -511:512 aralığında değer gerektirir"
-
-#: config/tc-msp430.c:783
-msgid "instruction requires label"
-msgstr "iÅŸlem etiket gerektirir"
-
-#: config/tc-msp430.c:789
-msgid "Ilegal instruction or not implmented opcode."
-msgstr "Geçersiz işlem veya eksik opkod."
-
-#: config/tc-msp430.c:817
-#, c-format
-msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
-msgstr "İç hata. @r%2$d yerine 0(r%1$d) kullanmayı deneyin"
-
-#: config/tc-msp430.c:827
-msgid "this addressing mode is not applicable for destination operand"
-msgstr "bu adresleme kipi hedef işlenen için geçerli değil"
-
-#: config/tc-msp430.c:944
-#, c-format
-msgid "value %ld out of range. Use #lo() or #hi()"
+#: config/tc-msp430.c:943
+#, fuzzy, c-format
+msgid "value %d out of range. Use #lo() or #hi()"
 msgstr "%ld değeri aralık dışı #lo() veya #hi() kullanın"
 
-#: config/tc-msp430.c:1040
+#: config/tc-msp430.c:1031
 #, c-format
 msgid "unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "
 msgstr "%s işleneninde bilinmeyen ifade. #llo() #lhi() #hlo() #hhi() kullanın"
 
-#: config/tc-msp430.c:1090 config/tc-msp430.c:1304
+#: config/tc-msp430.c:1082
+#, fuzzy, c-format
+msgid "Registers cannot be used within immediate expression [%s]"
+msgstr "yazmaç değeri ifade olarak kullanıldı"
+
+#: config/tc-msp430.c:1084
 #, c-format
 msgid "unknown operand %s"
 msgstr "bilinmeyen iÅŸlenen %s"
 
-#: config/tc-msp430.c:1111 config/tc-msp430.c:1242
+#: config/tc-msp430.c:1106 config/tc-msp430.c:1241
 #, c-format
 msgid "value out of range: %d"
 msgstr "değer aralık dışı: %d"
 
-#: config/tc-msp430.c:1120 config/tc-msp430.c:1259
+#: config/tc-msp430.c:1117
+#, fuzzy, c-format
+msgid "Registers cannot be used within absolute expression [%s]"
+msgstr "yazmaç değeri ifade olarak kullanıldı"
+
+#: config/tc-msp430.c:1119 config/tc-msp430.c:1262
 #, c-format
 msgid "unknown expression in operand %s"
 msgstr "%s iÅŸleneninde bilinmeyen ifade"
 
-#: config/tc-msp430.c:1134 config/tc-msp430.c:1141
+#: config/tc-msp430.c:1133 config/tc-msp430.c:1140
 #, c-format
 msgid "unknown addressing mode %s"
 msgstr "bilinmeyen adresleme kipi %s"
 
-#: config/tc-msp430.c:1149
+#: config/tc-msp430.c:1148
 #, c-format
 msgid "Bad register name r%s"
 msgstr "Hatalı yazmaç ismi r%s"
 
-#: config/tc-msp430.c:1161
+#: config/tc-msp430.c:1160
 #, c-format
 msgid "MSP430 does not have %d registers"
 msgstr "MSP430'da %d yazmaç yok"
 
-#: config/tc-msp430.c:1181
+#: config/tc-msp430.c:1180
 msgid "')' required"
 msgstr "')' gerekli"
 
-#: config/tc-msp430.c:1194
+#: config/tc-msp430.c:1193
 #, c-format
 msgid "unknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?"
 msgstr "bilinmeyen işlemimi %s. X(Rn) veya #[hl][hl][oi](CONST) mı kastettiniz?"
 
-#: config/tc-msp430.c:1203
+#: config/tc-msp430.c:1202
 #, c-format
 msgid "unknown operator (r%s substituded as a register name"
 msgstr "bilinmeyen işlemimi (r%s yazmaç adı olarak kullanıldı"
 
-#: config/tc-msp430.c:1215 config/tc-msp430.c:1226
+#: config/tc-msp430.c:1214 config/tc-msp430.c:1225
 #, c-format
 msgid "unknown operator %s"
 msgstr "bilinmeyen iÅŸlemimi %s"
 
-#: config/tc-msp430.c:1220
+#: config/tc-msp430.c:1219
 msgid "r2 should not be used in indexed addressing mode"
 msgstr "r2 indeksli adresleme kipinde kullanılmamalı"
 
+#: config/tc-msp430.c:1260
+#, fuzzy, c-format
+msgid "Registers cannot be used as a prefix of indexed expression [%s]"
+msgstr "yazmaç değeri ifade olarak kullanıldı"
+
 #. Unreachable.
-#: config/tc-msp430.c:1321
+#: config/tc-msp430.c:1309
 #, c-format
 msgid "unknown addressing mode for operand %s"
 msgstr "%s işleneni için bilinmeyen adresleme kipi"
 
+#: config/tc-msp430.c:1334
+#, c-format
+msgid "Internal bug. Try to use 0(r%d) instead of @r%d"
+msgstr "İç hata. @r%2$d yerine 0(r%1$d) kullanmayı deneyin"
+
+#: config/tc-msp430.c:1344
+msgid "this addressing mode is not applicable for destination operand"
+msgstr "bu adresleme kipi hedef işlenen için geçerli değil"
+
+#: config/tc-msp430.c:1388
+#, c-format
+msgid "instruction %s requires %d operand(s)"
+msgstr "'%s' işlemi için %d işlenen gerekli"
+
+#: config/tc-msp430.c:1634
+#, c-format
+msgid "Even number required. Rounded to %d"
+msgstr "Çift sayı gerekli. %d'ye yuvarlandı"
+
+#: config/tc-msp430.c:1645
+#, c-format
+msgid "Wrong displacement  %d"
+msgstr "Yanlış yerdeğiştirme  %d"
+
+#: config/tc-msp430.c:1662
+msgid "instruction requires label sans '$'"
+msgstr "işlem, '$' içermeyen etiket gerektirir"
+
+#: config/tc-msp430.c:1668
+msgid "instruction requires label or value in range -511:512"
+msgstr "işlem etiket veya -511:512 aralığında değer gerektirir"
+
+#: config/tc-msp430.c:1674 config/tc-msp430.c:1707 config/tc-msp430.c:1739
+msgid "instruction requires label"
+msgstr "iÅŸlem etiket gerektirir"
+
+#: config/tc-msp430.c:1743
+msgid "Ilegal instruction or not implmented opcode."
+msgstr "Geçersiz işlem veya eksik opkod."
+
+#: config/tc-msp430.c:2075
+#, fuzzy, c-format
+msgid "internal inconsistency problem in %s: insn %04lx"
+msgstr "%s içinde iç tutarlılık problemi: fr_symbol %lx"
+
+#: config/tc-msp430.c:2105 config/tc-msp430.c:2128
+#, fuzzy, c-format
+msgid "internal inconsistency problem in %s: ext. insn %04lx"
+msgstr "%s içinde iç tutarlılık problemi: fr_symbol %lx"
+
+#: config/tc-msp430.c:2140
+#, fuzzy, c-format
+msgid "internal inconsistency problem in %s:  %lx"
+msgstr "%s içinde iç tutarlılık problemi: fr_symbol %lx"
+
 #: config/tc-ns32k.c:449
 msgid "Invalid syntax in PC-relative addressing mode"
 msgstr "PC-göreli adresleme kipinde geçersiz sözdizimi"
@@ -7643,17 +8476,18 @@ msgstr "İç mantıksal hata. Satır %d, dosya \"%s\""
 msgid "Bit field out of range"
 msgstr "Bit alanı kapsam dışı"
 
-#: config/tc-ns32k.c:2183
+#: config/tc-ns32k.c:2180
 #, c-format
 msgid "invalid architecture option -m%s, ignored"
 msgstr "geçersiz yapı seçeneği -m%s, yoksayıldı"
 
-#: config/tc-ns32k.c:2196
+#: config/tc-ns32k.c:2193
 #, c-format
 msgid "invalid default displacement size \"%s\". Defaulting to %d."
 msgstr "geçersiz öntanımlı yerdeğişim boyu \"%s\". %d varsayılıyor."
 
-#: config/tc-ns32k.c:2213
+#: config/tc-ns32k.c:2210
+#, c-format
 msgid ""
 "NS32K options:\n"
 "-m32032 | -m32532\tselect variant of NS32K architecture\n"
@@ -7663,74 +8497,71 @@ msgstr ""
 "-m32032 | -m32532\tNS32K yapısının alt türlerini belirtir\n"
 "--disp-size-default=<1|2|4>\n"
 
-#: config/tc-ns32k.c:2397
+#: config/tc-ns32k.c:2394
 #, c-format
 msgid "Cannot find relocation type for symbol %s, code %d"
 msgstr "%s sembolü, %d kodu için yerdeğişim türü bulunamadı"
 
-#: config/tc-or32.c:465 config/tc-or32.c:680
+#: config/tc-or32.c:465 config/tc-or32.c:676
 #, c-format
 msgid "unknown opcode1: `%s'"
 msgstr "bilinmeyen opkod `%s'"
 
-#: config/tc-or32.c:471 config/tc-or32.c:686
+#: config/tc-or32.c:471 config/tc-or32.c:682
 #, c-format
 msgid "unknown opcode2 `%s'."
 msgstr "bilinmeyen opkod2 `%s'"
 
-#: config/tc-or32.c:510 config/tc-or32.c:725
+#: config/tc-or32.c:510 config/tc-or32.c:721
 #, c-format
 msgid "instruction not allowed: %s"
 msgstr "iÅŸleme izin yok: %s"
 
-#: config/tc-or32.c:513 config/tc-or32.c:728
+#: config/tc-or32.c:513 config/tc-or32.c:724
 #, c-format
 msgid "too many operands: %s"
 msgstr "Çok fazla işlenen: %s"
 
-#: config/tc-or32.c:603 config/tc-or32.c:819
+#: config/tc-or32.c:599 config/tc-or32.c:811
 msgid "call/jmp target out of range (1)"
 msgstr "call/jmp hedefi aralık dışı (1)"
 
-#: config/tc-or32.c:1016 config/tc-or32.c:1133
-msgid "the linker will not handle this relocation correctly (1)"
-msgstr "bağlayıcı bu yerdeğişimi doğru uygulayamaz (1)"
-
-#: config/tc-or32.c:1025 config/tc-or32.c:1142
+#: config/tc-or32.c:1004 config/tc-or32.c:1112
 msgid "call/jmp target out of range (2)"
 msgstr "call/jmp hedefi aralık dışı (2)"
 
-#: config/tc-or32.c:1433
+#: config/tc-or32.c:1402
 msgid "register out of range"
 msgstr "yazmaç kapsam dışı"
 
-#: config/tc-or32.c:1478
+#: config/tc-or32.c:1447
 msgid "invalid register in & expression"
 msgstr "& ifadesinde geçersiz yazmaç"
 
-#: config/tc-pdp11.c:454
+#: config/tc-pdp11.c:431
 msgid "Low order bits truncated in immediate float operand"
 msgstr "Şimdiki kayan nokta işleneninde düşük basamaklı bitler budandı"
 
-#: config/tc-pdp11.c:665
+#: config/tc-pdp11.c:620
 #, c-format
 msgid "Unknown instruction '%s'"
 msgstr "Bilinmeyen iÅŸlem '%s'"
 
-#: config/tc-pj.c:82 config/tc-pj.c:90
+#: config/tc-pj.c:83 config/tc-pj.c:91
 msgid "confusing relocation expressions"
 msgstr "yerdeğişim ifadeleri karmaşık"
 
-#: config/tc-pj.c:181
+#: config/tc-pj.c:182
 msgid "can't have relocation for ipush"
 msgstr "ipush için yerdeğişim yapılamaz"
 
-#: config/tc-pj.c:290 config/tc-xtensa.c:4976
+#: config/tc-pj.c:289
 #, c-format
 msgid "unknown opcode %s"
 msgstr "bilinmeyen opkod %s"
 
-#: config/tc-pj.c:439
+#: config/tc-pj.c:438
+#, c-format
 msgid ""
 "PJ options:\n"
 "-little\t\t\tgenerate little endian code\n"
@@ -7740,8 +8571,8 @@ msgstr ""
 "-little\t\t\tküçük sonlu kod üretir\n"
 "-big\t\t\tbüyük sonlu kod üretir\n"
 
-#: config/tc-pj.c:469 config/tc-sh.c:3464 config/tc-sh.c:3471
-#: config/tc-sh.c:3478 config/tc-sh.c:3485
+#: config/tc-pj.c:468 config/tc-sh.c:3978 config/tc-sh.c:3985
+#: config/tc-sh.c:3992 config/tc-sh.c:3999
 msgid "pcrel too far"
 msgstr "pcrel fazla uzak"
 
@@ -7753,17 +8584,18 @@ msgstr "convert_frag\n"
 msgid "estimate size\n"
 msgstr "boyut tahmini\n"
 
-#: config/tc-ppc.c:879
+#: config/tc-ppc.c:980
 #, c-format
 msgid "%s unsupported"
 msgstr "%s desteklenmiyor"
 
-#: config/tc-ppc.c:1029 config/tc-s390.c:414 config/tc-s390.c:421
+#: config/tc-ppc.c:1046 config/tc-s390.c:415 config/tc-s390.c:422
 #, c-format
 msgid "invalid switch -m%s"
 msgstr "geçersiz bayrak -m%s"
 
-#: config/tc-ppc.c:1066
+#: config/tc-ppc.c:1083
+#, fuzzy, c-format
 msgid ""
 "PowerPC options:\n"
 "-a32\t\t\tgenerate ELF32/XCOFF32\n"
@@ -7775,6 +8607,7 @@ msgid ""
 "-mppc, -mppc32, -m603, -m604\n"
 "\t\t\tgenerate code for PowerPC 603/604\n"
 "-m403, -m405\t\tgenerate code for PowerPC 403/405\n"
+"-m440\t\t\tgenerate code for PowerPC 440\n"
 "-m7400, -m7410, -m7450, -m7455\n"
 "\t\t\tgenerate code For PowerPC 7400/7410/7450/7455\n"
 msgstr ""
@@ -7791,7 +8624,8 @@ msgstr ""
 "-m7400, -m7410, -m7450, -m7455\n"
 "\t\t\tPowerPC 7400/7410/7450/7455 için kod üretir\n"
 
-#: config/tc-ppc.c:1079
+#: config/tc-ppc.c:1097
+#, c-format
 msgid ""
 "-mppc64, -m620\t\tgenerate code for PowerPC 620/625/630\n"
 "-mppc64bridge\t\tgenerate code for PowerPC 64, including bridge insns\n"
@@ -7809,7 +8643,8 @@ msgstr ""
 "-mcom\t\t\tPower/PowerPC ortak işlemleri için kod üretir\n"
 "-many\t\t\tBütün mimariler (PWR/PWRX/PPC) için kod üretir\n"
 
-#: config/tc-ppc.c:1087
+#: config/tc-ppc.c:1105
+#, c-format
 msgid ""
 "-maltivec\t\tgenerate code for AltiVec\n"
 "-me500, -me500x2\tgenerate code for Motorola e500 core complex\n"
@@ -7823,7 +8658,8 @@ msgstr ""
 "-mregnames\t\tYazmaçlarda sembolik isimlere izin verir\n"
 "-mno-regnames\t\tYazmaçlarda sembolik isimlere izin vermez\n"
 
-#: config/tc-ppc.c:1094
+#: config/tc-ppc.c:1112
+#, c-format
 msgid ""
 "-mrelocatable\t\tsupport for GCC's -mrelocatble option\n"
 "-mrelocatable-lib\tsupport for GCC's -mrelocatble-lib option\n"
@@ -7848,221 +8684,254 @@ msgstr ""
 "-V\t\t\tçeviricinin sürüm numarasını yazdırır\n"
 "-Qy, -Qn\t\tyoksayılır\n"
 
-#: config/tc-ppc.c:1136
+#: config/tc-ppc.c:1154
 #, c-format
 msgid "Unknown default cpu = %s, os = %s"
 msgstr "Bilinmeyen öntanımlı işlemci = %s, os = %s"
 
-#: config/tc-ppc.c:1161
+#: config/tc-ppc.c:1180
 msgid "Neither Power nor PowerPC opcodes were selected."
 msgstr "Ne Power ne de PowerPC opkodları belirtilmiş."
 
-#: config/tc-ppc.c:1257 config/tc-s390.c:516
+#: config/tc-ppc.c:1270 config/tc-s390.c:517
 #, c-format
 msgid "Internal assembler error for instruction %s"
 msgstr "%s işlemi için iç çevirici hatası"
 
-#: config/tc-ppc.c:1277
+#: config/tc-ppc.c:1294
 #, c-format
 msgid "Internal assembler error for macro %s"
 msgstr "%s makrosu için iç çevirici hatası"
 
-#: config/tc-ppc.c:1599
+#: config/tc-ppc.c:1625
 msgid "identifier+constant@got means identifier@got+constant"
 msgstr "tanımlayıcı+sabit@got, tanımlayıcı@got+sabit ile aynı"
 
-#: config/tc-ppc.c:1666
+#: config/tc-ppc.c:1692
 #, c-format
 msgid "%s relocations do not fit in %d bytes\n"
 msgstr "%s yerdeğişimleri %d bayta sığmıyor\n"
 
-#: config/tc-ppc.c:1773
+#: config/tc-ppc.c:1799
 #, c-format
 msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld."
 msgstr ".lcomm uzunluÄŸu \"%s\" zaten %ld. %ld olarak deÄŸiÅŸtirilmedi."
 
-#: config/tc-ppc.c:1855
+#: config/tc-ppc.c:1881
 msgid "Relocation cannot be done when using -mrelocatable"
 msgstr "-mrelocatable kullanılırken yerdeğişim yapılamaz"
 
-#: config/tc-ppc.c:1981
+#: config/tc-ppc.c:1930
+msgid "TOC section size exceeds 64k"
+msgstr ""
+
+#: config/tc-ppc.c:2012
 #, c-format
 msgid "syntax error: invalid toc specifier `%s'"
 msgstr "sözdizim hatası: geçersiz toc belirteci `%s'"
 
-#: config/tc-ppc.c:1995
+#: config/tc-ppc.c:2026
 #, c-format
 msgid "syntax error: expected `]', found  `%c'"
 msgstr "sözdizim hatası: `]' beklendi, `%c' bulundu"
 
-#: config/tc-ppc.c:2272
+#: config/tc-ppc.c:2305
 msgid "[tocv] symbol is not a toc symbol"
 msgstr "[tocv] sembolü toc sembolü değil"
 
-#: config/tc-ppc.c:2283
+#: config/tc-ppc.c:2316
 msgid "Unimplemented toc32 expression modifier"
 msgstr "toc32 ifade değiştiricisi henüz desteklenmiyor"
 
-#: config/tc-ppc.c:2288
+#: config/tc-ppc.c:2321
 msgid "Unimplemented toc64 expression modifier"
 msgstr "toc64 ifade değiştiricisi henüz desteklenmiyor"
 
-#: config/tc-ppc.c:2292
+#: config/tc-ppc.c:2325
 #, c-format
 msgid "Unexpected return value [%d] from parse_toc_entry!\n"
 msgstr "parse_toc_entry'den beklenmeyen geri dönüş değeri [%d]!\n"
 
-#: config/tc-ppc.c:2510
+#: config/tc-ppc.c:2543
 msgid "unsupported relocation for DS offset field"
 msgstr "DS görece alanı için desteklenmeyen yerdeğişim türü"
 
-#: config/tc-ppc.c:2554
+#: config/tc-ppc.c:2587
 #, c-format
 msgid "syntax error; found `%c' but expected `%c'"
 msgstr "sözdizim hatası; `%2$c' beklendi fakat `%1$c' bulundu"
 
-#: config/tc-ppc.c:2703
+#: config/tc-ppc.c:2630 config/tc-ppc.h:117
+#, fuzzy
+msgid "instruction address is not a multiple of 4"
+msgstr "4'ün katı olan bir adrese dallanmak gerekli"
+
+#: config/tc-ppc.c:2741
 msgid "wrong number of operands"
 msgstr "işlenen sayısı yanlış"
 
-#: config/tc-ppc.c:2759
+#: config/tc-ppc.c:2797
 msgid "Bad .section directive: want a,e,w,x,M,S,G,T in string"
 msgstr "Hatalı .section yönergesi: dizgede a,e,w,x,M,S,T olmalı"
 
-#: config/tc-ppc.c:2874
+#: config/tc-ppc.c:2912
 msgid "missing size"
 msgstr "boy eksik"
 
-#: config/tc-ppc.c:2883
+#: config/tc-ppc.c:2921
 msgid "negative size"
 msgstr "boy negatif"
 
-#: config/tc-ppc.c:2920
+#: config/tc-ppc.c:2958
 msgid "missing real symbol name"
 msgstr "gerçek sembol ismi eksik"
 
-#: config/tc-ppc.c:2941
+#: config/tc-ppc.c:2979
 msgid "attempt to redefine symbol"
 msgstr "sembolü yeniden tanımlama denemesi"
 
-#: config/tc-ppc.c:3188
+#: config/tc-ppc.c:3226
 msgid "The XCOFF file format does not support arbitrary sections"
 msgstr "XCOFF dosya biçemi, gelişigüzel bölümleri desteklemiyor"
 
-#: config/tc-ppc.c:3265
+#: config/tc-ppc.c:3303
 msgid "missing rename string"
 msgstr "isim deÄŸiÅŸim dizgesi eksik"
 
-#: config/tc-ppc.c:3296 config/tc-ppc.c:3851 read.c:3060
+#: config/tc-ppc.c:3334 config/tc-ppc.c:3889 read.c:3035
 msgid "missing value"
 msgstr "deÄŸer eksik"
 
-#: config/tc-ppc.c:3314
+#: config/tc-ppc.c:3352
 msgid "illegal .stabx expression; zero assumed"
 msgstr "geçersiz .stabx ifadesi; sıfır varsayıldı"
 
-#: config/tc-ppc.c:3346
+#: config/tc-ppc.c:3384
 msgid "missing class"
 msgstr "eksik sınıf"
 
-#: config/tc-ppc.c:3355
+#: config/tc-ppc.c:3393
 msgid "missing type"
 msgstr "eksik tür"
 
-#: config/tc-ppc.c:3436
+#: config/tc-ppc.c:3474
 msgid "missing symbol name"
 msgstr "eksik sembol adı"
 
-#: config/tc-ppc.c:3630
+#: config/tc-ppc.c:3668
 msgid "nested .bs blocks"
 msgstr "içiçe .bs blokları"
 
-#: config/tc-ppc.c:3663
+#: config/tc-ppc.c:3701
 msgid ".es without preceding .bs"
 msgstr "öncesinde .bs olmayan .es"
 
-#: config/tc-ppc.c:3843
+#: config/tc-ppc.c:3881
 msgid "non-constant byte count"
 msgstr "sabit olmayan bayt sayısı"
 
-#: config/tc-ppc.c:3891
+#: config/tc-ppc.c:3929
 msgid ".tc not in .toc section"
 msgstr ".tc, .toc bölümünde değil"
 
-#: config/tc-ppc.c:3910
+#: config/tc-ppc.c:3948
 msgid ".tc with no label"
 msgstr "etiketi olmayan .tc"
 
-#: config/tc-ppc.c:4021
+#: config/tc-ppc.c:4040
+msgid ".machine stack overflow"
+msgstr ""
+
+#: config/tc-ppc.c:4047
+msgid ".machine stack underflow"
+msgstr ""
+
+#: config/tc-ppc.c:4054
+#, fuzzy, c-format
+msgid "invalid machine `%s'"
+msgstr "geçersiz yapı %s"
+
+#: config/tc-ppc.c:4108
 msgid "No previous section to return to. Directive ignored."
 msgstr "Geri dönülecek önceki bölüm yok. Yönerge yoksayıldı."
 
 #. Section Contents
 #. unknown
-#: config/tc-ppc.c:4438
+#: config/tc-ppc.c:4525
 msgid "Unsupported section attribute -- 'a'"
 msgstr "Desteklenmeyen bölüm özniteliği -- 'a'"
 
-#: config/tc-ppc.c:4627
+#: config/tc-ppc.c:4714
 msgid "bad symbol suffix"
 msgstr "hatalı sembol soneki"
 
-#: config/tc-ppc.c:4720
+#: config/tc-ppc.c:4807
 msgid "Unrecognized symbol suffix"
 msgstr "Bilinmeyen sembol soneki"
 
-#: config/tc-ppc.c:4806
+#: config/tc-ppc.c:4893
 msgid "two .function pseudo-ops with no intervening .ef"
 msgstr "arada .ef olmaksızın iki .function sanal-op'u "
 
-#: config/tc-ppc.c:4819
+#: config/tc-ppc.c:4906
 msgid ".ef with no preceding .function"
 msgstr "öncesinde .function olmayan .ef"
 
-#: config/tc-ppc.c:4947
+#: config/tc-ppc.c:5034
 #, c-format
 msgid "warning: symbol %s has no csect"
 msgstr "uyarı: %s sembolünde csect yok"
 
-#: config/tc-ppc.c:5251
+#: config/tc-ppc.c:5338
 msgid "symbol in .toc does not match any .tc"
 msgstr ".toc'daki sembol .tc'de eÅŸleÅŸmiyor"
 
-#: config/tc-ppc.c:5584 config/tc-s390.c:2072 config/tc-v850.c:2402
-#: config/tc-xstormy16.c:537
+#: config/tc-ppc.c:5666 config/tc-s390.c:2057 config/tc-v850.c:2408
+#: config/tc-xstormy16.c:555
 msgid "unresolved expression that must be resolved"
 msgstr "Çözümlenmesi gereken çözümlenmemiş ifade"
 
-#: config/tc-ppc.c:5587
+#: config/tc-ppc.c:5669
 #, c-format
 msgid "unsupported relocation against %s"
 msgstr "%s'e karşı desteklenmeyen yerdeğişim"
 
-#: config/tc-ppc.c:5662
+#: config/tc-ppc.c:5744
 #, c-format
 msgid "cannot emit PC relative %s relocation against %s"
 msgstr "%2$s'ye göreli PC göreli %1$s yerdeğişimi üretilemedi"
 
-#: config/tc-ppc.c:5667
+#: config/tc-ppc.c:5749
 #, c-format
 msgid "cannot emit PC relative %s relocation"
 msgstr "PC göreli %s yerdeğişimi üretilemedi"
 
-#: config/tc-ppc.c:5841
+#: config/tc-ppc.c:5905
+#, fuzzy, c-format
+msgid "Unable to handle reference to symbol %s"
+msgstr "iki sembolün farkına callj"
+
+#: config/tc-ppc.c:5908
+#, fuzzy
+msgid "Unable to resolve expression"
+msgstr "ifade çözümlenemedi"
+
+#: config/tc-ppc.c:5935
 msgid "must branch to an address a multiple of 4"
 msgstr "4'ün katı olan bir adrese dallanmak gerekli"
 
-#: config/tc-ppc.c:5845
+#: config/tc-ppc.c:5939
 #, c-format
 msgid "@local or @plt branch destination is too far away, %ld bytes"
 msgstr "@local veya @plt dal hedefi fazla uzak, %ld bayt"
 
-#: config/tc-ppc.c:5876
+#: config/tc-ppc.c:5970
 #, c-format
 msgid "Gas failure, reloc value %d\n"
 msgstr "Gas hatası, yerdeğişim değeri %d\n"
 
-#: config/tc-s390.c:457
+#: config/tc-s390.c:458
+#, c-format
 msgid ""
 "        S390 options:\n"
 "        -mregnames        Allow symbolic names for registers\n"
@@ -8078,7 +8947,8 @@ msgstr ""
 "        -m31              Dosya biçemini 31 bit biçemi olarak ayarlar\n"
 "        -m64              Dosya biçemini 64 bit biçemi olarak ayarlar\n"
 
-#: config/tc-s390.c:464
+#: config/tc-s390.c:465
+#, c-format
 msgid ""
 "        -V                print assembler version number\n"
 "        -Qy, -Qn          ignored\n"
@@ -8086,236 +8956,457 @@ msgstr ""
 "  -V\t\t\t  çevirici sürüm numarasını yazdırır\n"
 "  -Qy, -Qn\t\t  yoksayılır\n"
 
-#: config/tc-s390.c:500
+#: config/tc-s390.c:501
 #, c-format
 msgid "Internal assembler error for instruction format %s"
 msgstr "%s işlem biçemi için iç çevirici hatası"
 
-#: config/tc-s390.c:782
+#: config/tc-s390.c:764
 #, c-format
 msgid "identifier+constant@%s means identifier@%s+constant"
 msgstr "tanımlayıcı+sabit@%s, tanımlayıcı@%s+sabit ile aynı"
 
-#: config/tc-s390.c:865
+#: config/tc-s390.c:847
 msgid "Can't handle O_big in s390_exp_compare"
 msgstr "s390_exp_compare içinde O_big işlenemiyor"
 
-#: config/tc-s390.c:949
+#: config/tc-s390.c:931
 msgid "Invalid suffix for literal pool entry"
 msgstr "Literal havuz girdisi için geçersiz sonek"
 
-#: config/tc-s390.c:1006
+#: config/tc-s390.c:988
 msgid "Big number is too big"
 msgstr "Büyük sayı fazla büyük"
 
-#: config/tc-s390.c:1144 config/tc-s390.c:1722
+#: config/tc-s390.c:1126 config/tc-s390.c:1707 config/tc-xtensa.c:1632
 #, c-format
 msgid "%s relocations do not fit in %d bytes"
 msgstr "%s yerdeğişimleri %d bayta sığmıyor"
 
-#: config/tc-s390.c:1154
+#: config/tc-s390.c:1136
 msgid "relocation not applicable"
 msgstr "yerdeğişim kapsam dışı"
 
-#: config/tc-s390.c:1342
+#: config/tc-s390.c:1324
 msgid "invalid operand suffix"
 msgstr "geçersiz işlenen soneki"
 
-#: config/tc-s390.c:1365
+#: config/tc-s390.c:1347
 msgid "syntax error; missing '(' after displacement"
 msgstr "sözdizim hatası; yerdeğişim sonrası '(' eksik"
 
-#: config/tc-s390.c:1375 config/tc-s390.c:1408 config/tc-s390.c:1427
+#: config/tc-s390.c:1357 config/tc-s390.c:1390 config/tc-s390.c:1409
 msgid "syntax error; expected ,"
 msgstr "sözdizim hatası: , beklendi"
 
-#: config/tc-s390.c:1402
+#: config/tc-s390.c:1384
 msgid "syntax error; missing ')' after base register"
 msgstr "sözdizim hatası: temel yazmaçtan sonra ')' eksik"
 
-#: config/tc-s390.c:1420
+#: config/tc-s390.c:1402
 msgid "syntax error; ')' not allowed here"
 msgstr "sözdizim hatası; ')' burada kullanılamaz"
 
-#: config/tc-s390.c:1602 config/tc-s390.c:1622 config/tc-s390.c:1635
+#: config/tc-s390.c:1584 config/tc-s390.c:1607 config/tc-s390.c:1620
 msgid "Invalid .insn format\n"
 msgstr "Geçersiz .insn biçemi\n"
 
-#: config/tc-s390.c:1610
+#: config/tc-s390.c:1592
 #, c-format
 msgid "Unrecognized opcode format: `%s'"
 msgstr "Bilinmeyen opkod biçemi: `%s'"
 
-#: config/tc-s390.c:1638
+#: config/tc-s390.c:1623
 msgid "second operand of .insn not a constant\n"
 msgstr "iÅŸlemin ikinci iÅŸleneni sabit deÄŸil\n"
 
-#: config/tc-s390.c:1641
+#: config/tc-s390.c:1626
 msgid "missing comma after insn constant\n"
 msgstr "işlem sabitinden sonra virgül eksik\n"
 
-#: config/tc-s390.c:2075
+#: config/tc-s390.c:2060
 msgid "unsupported relocation type"
 msgstr "desteklenmeyen yerdeğişim türü"
 
-#: config/tc-sh.c:91
+#: config/tc-sh64.c:568
+msgid "This operand must be constant at assembly time"
+msgstr "Bu işlenen çevrim esnasında sabit olmalı"
+
+#: config/tc-sh64.c:681
+msgid "Invalid operand expression"
+msgstr "Geçersiz işlenen ifadesi"
+
+#: config/tc-sh64.c:773 config/tc-sh64.c:877
+msgid "PTB operand is a SHmedia symbol"
+msgstr "PTB işleneni bir SHmedia sembolü"
+
+#: config/tc-sh64.c:776 config/tc-sh64.c:874
+msgid "PTA operand is a SHcompact symbol"
+msgstr "PTA işleneni bir SHcompact sembolü"
+
+#: config/tc-sh64.c:792
+msgid "invalid expression in operand"
+msgstr "İşlenende geçersiz ifade"
+
+#: config/tc-sh64.c:1483
+#, c-format
+msgid "invalid operand, not a 5-bit unsigned value: %d"
+msgstr "Geçersiz işlenen; değeri 5bit unsigned değil: %d"
+
+#: config/tc-sh64.c:1488
+#, c-format
+msgid "invalid operand, not a 6-bit signed value: %d"
+msgstr "Geçersiz işlenen; değeri 6bit unsigned değil: %d"
+
+#: config/tc-sh64.c:1493
+#, c-format
+msgid "invalid operand, not a 6-bit unsigned value: %d"
+msgstr "geçersiz işlenen; değeri 6bit unsigned değil: %d"
+
+#: config/tc-sh64.c:1498 config/tc-sh64.c:1510
+#, c-format
+msgid "invalid operand, not a 11-bit signed value: %d"
+msgstr "geçersiz işlenen; değeri 11bit signed değil: %d"
+
+#: config/tc-sh64.c:1500
+#, c-format
+msgid "invalid operand, not a multiple of 32: %d"
+msgstr "geçersiz işlenen; 32'nin katı değil: %d"
+
+#: config/tc-sh64.c:1505
+#, c-format
+msgid "invalid operand, not a 10-bit signed value: %d"
+msgstr "geçersiz işlenen; değeri 10 bit signed değil: %d"
+
+#: config/tc-sh64.c:1512
+#, c-format
+msgid "invalid operand, not an even value: %d"
+msgstr "geçersiz işlenen; değeri çift sayı değil: %d"
+
+#: config/tc-sh64.c:1517
+#, c-format
+msgid "invalid operand, not a 12-bit signed value: %d"
+msgstr "geçersiz işlenen; değeri 12 bit signed değil: %d"
+
+#: config/tc-sh64.c:1519
+#, c-format
+msgid "invalid operand, not a multiple of 4: %d"
+msgstr "geçersiz işlenen; 4'ün katı değil: %d"
+
+#: config/tc-sh64.c:1524
+#, c-format
+msgid "invalid operand, not a 13-bit signed value: %d"
+msgstr "geçersiz işlenen; değeri 13 bit signed değil: %d"
+
+#: config/tc-sh64.c:1526
+#, c-format
+msgid "invalid operand, not a multiple of 8: %d"
+msgstr "geçersiz işlenen; 8'in katı değil: %d"
+
+#: config/tc-sh64.c:1531
+#, c-format
+msgid "invalid operand, not a 16-bit signed value: %d"
+msgstr "geçersiz işlenen; değeri 16 bit signed değil: %d"
+
+#: config/tc-sh64.c:1536
+#, c-format
+msgid "invalid operand, not an 16-bit unsigned value: %d"
+msgstr "geçersiz işlenen; değeri 16 bit unsigned değil: %d"
+
+#: config/tc-sh64.c:1542
+msgid "operand out of range for PT, PTA and PTB"
+msgstr "işlenen PT, PTA ve PTB için aralık dışı"
+
+#: config/tc-sh64.c:1544
+#, c-format
+msgid "operand not a multiple of 4 for PT, PTA or PTB: %d"
+msgstr "işlenen PT, PTA ve PTB için 4'ün katı olmalı: %d"
+
+#: config/tc-sh64.c:2064
+#, c-format
+msgid "MOVI operand is not a 32-bit signed value: 0x%8x%08x"
+msgstr "MOVI iÅŸleneni 32 bit signed deÄŸil: 0x%8x%08x"
+
+#: config/tc-sh64.c:2421 config/tc-sh64.c:2584 config/tc-sh64.c:2599
+msgid "invalid PIC reference"
+msgstr "geçersiz PIC referansı"
+
+#: config/tc-sh64.c:2478
+msgid "can't find opcode"
+msgstr "opkod bulunamadı"
+
+#: config/tc-sh64.c:2681 config/tc-sh64.c:2721
+#, fuzzy
+msgid "invalid operand: expression in PT target"
+msgstr "Geçersiz işlenen ifadesi"
+
+#: config/tc-sh64.c:2812
+#, c-format
+msgid "invalid operands to %s"
+msgstr "Geçersiz işlenenler: %s"
+
+#: config/tc-sh64.c:2818
+#, c-format
+msgid "excess operands to %s"
+msgstr "fazla iÅŸlenenler: '%s'"
+
+#: config/tc-sh64.c:2863
+#, c-format
+msgid "The `.mode %s' directive is not valid with this architecture"
+msgstr "'.mode %s' yönergesi bu mimari için geçerli değil"
+
+#: config/tc-sh64.c:2871
+#, c-format
+msgid "Invalid argument to .mode: %s"
+msgstr ".mode için geçersiz argüman: %s"
+
+#: config/tc-sh64.c:2901
+#, c-format
+msgid "The `.abi %s' directive is not valid with this architecture"
+msgstr "'.abi %s' yönergesi bu mimari için geçerli değil"
+
+#: config/tc-sh64.c:2907
+msgid "`.abi 64' but command-line options do not specify 64-bit ABI"
+msgstr "'.abi 64' fakat komut satırı seçenekleri 64 bit ABI belirtmiyor"
+
+#: config/tc-sh64.c:2912
+msgid "`.abi 32' but command-line options do not specify 32-bit ABI"
+msgstr "'.abi 32' fakat komut satırı seçenekleri 32 bit ABI belirtmiyor"
+
+#: config/tc-sh64.c:2915
+#, c-format
+msgid "Invalid argument to .abi: %s"
+msgstr ".abi'ye geçersiz argüman: %s"
+
+#: config/tc-sh64.c:2970
+msgid "-no-mix is invalid without specifying SHcompact or SHmedia"
+msgstr "-no-mix, SHcompact veya SHmedia belirtilmeden geçersiz"
+
+#: config/tc-sh64.c:2975
+msgid "-shcompact-const-crange is invalid without SHcompact"
+msgstr "-shcompact-const-crange SHcompact seçeneği olmadan geçersizdir"
+
+#: config/tc-sh64.c:2978
+msgid "-expand-pt32 only valid with -abi=64"
+msgstr "-expand-pt32 ancak -abi=64 ile birlikte geçerli olur"
+
+#: config/tc-sh64.c:2981
+msgid "-no-expand only valid with SHcompact or SHmedia"
+msgstr "-no-expand ancak SHcompact veya SHmedia ile birlikte geçerli olur"
+
+#: config/tc-sh64.c:2984
+msgid "-expand-pt32 invalid together with -no-expand"
+msgstr "-expand-pt32, -no-expand ile birlikte geçersiz olur"
+
+#: config/tc-sh64.c:3201
+msgid "SHmedia code not allowed in same section as constants and SHcompact code"
+msgstr "SHmedia kodu, SHcompact kodu ve sabitlerle aynı bölümde bulunamaz"
+
+#: config/tc-sh64.c:3219
+msgid "No segment info for current section"
+msgstr "Şimdiki bölüm için segment bilgisi yok"
+
+#: config/tc-sh64.c:3257
+msgid "duplicate datalabel operator ignored"
+msgstr "Çoklu veri etiket işlemimi yoksayıldı"
+
+#: config/tc-sh64.c:3327
+msgid "Invalid DataLabel expression"
+msgstr "geçersiz Veri Etiketi ifadesi"
+
+#: config/tc-sh.c:65
 msgid "directive .big encountered when option -big required"
 msgstr "seçenek -big gereken yerde .big yönergesi bulundu"
 
-#: config/tc-sh.c:102
+#: config/tc-sh.c:75
 msgid "directive .little encountered when option -little required"
 msgstr "seçenek -little gereken yerde .little yönergesi bulundu"
 
-#: config/tc-sh.c:776
-msgid "Invalid PIC expression."
-msgstr "geçersiz PIC ifadesi"
-
-#: config/tc-sh.c:1269
+#: config/tc-sh.c:1245
 msgid "misplaced PIC operand"
 msgstr "PIC işleneni yanlış yerde"
 
-#: config/tc-sh.c:1310
+#: config/tc-sh.c:1283
+#, fuzzy
+msgid "illegal double indirection"
+msgstr "geçersiz ifade"
+
+#: config/tc-sh.c:1292
 msgid "illegal register after @-"
 msgstr "@- sonrasında geçersiz yazmaç"
 
-#: config/tc-sh.c:1326
+#: config/tc-sh.c:1308
 msgid "must be @(r0,...)"
 msgstr "@(r0,...) olmalı"
 
-#: config/tc-sh.c:1350
+#: config/tc-sh.c:1332
 msgid "syntax error in @(r0,...)"
 msgstr "@(r0,...) içinde sözdizim hatası"
 
-#: config/tc-sh.c:1355
+#: config/tc-sh.c:1337
 msgid "syntax error in @(r0...)"
 msgstr "@(r0...) içinde sözdizim hatası"
 
-#: config/tc-sh.c:1396
+#: config/tc-sh.c:1382
 msgid "Deprecated syntax."
 msgstr "Artık kullanılmayan biçem."
 
-#: config/tc-sh.c:1408 config/tc-sh.c:1413
+#: config/tc-sh.c:1394 config/tc-sh.c:1399
 msgid "syntax error in @(disp,[Rn, gbr, pc])"
 msgstr "@(disp,[Rn, gbr, pc]) içinde sözdizim hatası"
 
-#: config/tc-sh.c:1418
+#: config/tc-sh.c:1404
 msgid "expecting )"
 msgstr ") beklendi"
 
-#: config/tc-sh.c:1426
+#: config/tc-sh.c:1412
 msgid "illegal register after @"
 msgstr "@ sonrasında geçersiz yazmaç"
 
-#: config/tc-sh.c:1977
+#: config/tc-sh.c:2249
 #, c-format
 msgid "Invalid register: 'r%d'"
 msgstr "Geçersiz yazmaç: 'r%d'"
 
-#: config/tc-sh.c:2143
+#: config/tc-sh.c:2471
 msgid "insn can't be combined with parallel processing insn"
 msgstr "iÅŸlem, paralel iÅŸlenen iÅŸlem ile birleÅŸtirilemez"
 
-#: config/tc-sh.c:2150 config/tc-sh.c:2161
+#: config/tc-sh.c:2478 config/tc-sh.c:2489 config/tc-sh.c:2521
 msgid "multiple movx specifications"
 msgstr "birden fazla movx tanımı"
 
-#: config/tc-sh.c:2155 config/tc-sh.c:2182
+#: config/tc-sh.c:2483 config/tc-sh.c:2505 config/tc-sh.c:2544
 msgid "multiple movy specifications"
 msgstr "birden fazla movy tanımı"
 
-#: config/tc-sh.c:2163
+#: config/tc-sh.c:2492 config/tc-sh.c:2525
 msgid "invalid movx address register"
 msgstr "geçersiz movx adres yazmacı"
 
-#: config/tc-sh.c:2169 config/tc-sh.c:2174
+#: config/tc-sh.c:2494
+#, fuzzy
+msgid "insn cannot be combined with non-nopy"
+msgstr "iÅŸlem 'pmuls' ile birleÅŸtirilemez"
+
+#: config/tc-sh.c:2508 config/tc-sh.c:2564
+msgid "invalid movy address register"
+msgstr "geçersiz movy adres yazmacı"
+
+#: config/tc-sh.c:2510
+#, fuzzy
+msgid "insn cannot be combined with non-nopx"
+msgstr "iÅŸlem 'pmuls' ile birleÅŸtirilemez"
+
+#: config/tc-sh.c:2523
+msgid "previous movy requires nopx"
+msgstr ""
+
+#: config/tc-sh.c:2531 config/tc-sh.c:2536
 msgid "invalid movx dsp register"
 msgstr "geçersiz movx dsp yazmacı"
 
-#: config/tc-sh.c:2191 config/tc-sh.c:2196
+#: config/tc-sh.c:2546
+msgid "previous movx requires nopy"
+msgstr ""
+
+#: config/tc-sh.c:2555 config/tc-sh.c:2560
 msgid "invalid movy dsp register"
 msgstr "geçersiz movy dsp yazmacı"
 
-#: config/tc-sh.c:2200
-msgid "invalid movy address register"
-msgstr "geçersiz movy adres yazmacı"
-
-#: config/tc-sh.c:2206
+#: config/tc-sh.c:2570
 msgid "dsp immediate shift value not constant"
 msgstr "dsp şimdiki kaydırma değeri sabit değil"
 
-#: config/tc-sh.c:2213 config/tc-sh.c:2226
+#: config/tc-sh.c:2584 config/tc-sh.c:2610
 msgid "multiple parallel processing specifications"
 msgstr "birden fazla paralel işleme tanımı"
 
-#: config/tc-sh.c:2219
+#: config/tc-sh.c:2603
 msgid "multiple condition specifications"
 msgstr "birden fazla koşul tanımı"
 
-#: config/tc-sh.c:2235
+#: config/tc-sh.c:2641
 msgid "insn cannot be combined with pmuls"
 msgstr "iÅŸlem 'pmuls' ile birleÅŸtirilemez"
 
-#: config/tc-sh.c:2252
-msgid "bad padd / psub pmuls output operand"
+#: config/tc-sh.c:2657
+#, fuzzy
+msgid "bad combined pmuls output operand"
 msgstr "hatalı padd / psub pmuls çıktı işleneni"
 
-#: config/tc-sh.c:2262
+#: config/tc-sh.c:2667
 msgid "destination register is same for parallel insns"
 msgstr "Paralel işlemler için hedef yazmaç aynı"
 
-#: config/tc-sh.c:2271
+#: config/tc-sh.c:2676
 msgid "condition not followed by conditionalizable insn"
 msgstr "koÅŸuldan sonra koÅŸullanabilir iÅŸlem yok"
 
-#: config/tc-sh.c:2281
+#: config/tc-sh.c:2686
 msgid "unrecognized characters at end of parallel processing insn"
 msgstr "paralel iÅŸlenen iÅŸlemin sonunda bilinmeyen karakterler"
 
-#: config/tc-sh.c:2417
+#: config/tc-sh.c:2802
+#, fuzzy
+msgid "opcode not valid for this cpu variant"
+msgstr ":24 bu opkod için geçersiz"
+
+#: config/tc-sh.c:2835
+msgid "Delayed branches not available on SH1"
+msgstr ""
+
+#: config/tc-sh.c:2867
 #, c-format
 msgid "excess operands: '%s'"
 msgstr "fazla iÅŸlenenler: '%s'"
 
-#: config/tc-sh.c:2569
+#: config/tc-sh.c:3012
 msgid ".uses pseudo-op seen when not relaxing"
 msgstr ".uses sanal-op'u gevşetme olmadığı halde bulundu"
 
-#: config/tc-sh.c:2575
+#: config/tc-sh.c:3018
 msgid "bad .uses format"
 msgstr "hatalı .uses biçemi"
 
-#: config/tc-sh.c:2654
+#: config/tc-sh.c:3104
 msgid "Invalid combination: --isa=SHcompact with --isa=SHmedia"
 msgstr "Geçersiz birleşim: --isa=SHcompact ve --isa=SHmedia"
 
-#: config/tc-sh.c:2660
+#: config/tc-sh.c:3110
 msgid "Invalid combination: --isa=SHmedia with --isa=SHcompact"
 msgstr "Geçersiz birleşim: --isa=SHmedia ve --isa=SHcompact"
 
-#: config/tc-sh.c:2662
+#: config/tc-sh.c:3112
 msgid "Invalid combination: --abi=64 with --isa=SHcompact"
 msgstr "Geçersiz birleşim: --abi=64 ve --isa=SHcompact"
 
-#: config/tc-sh.c:2675
+#: config/tc-sh.c:3152
 msgid "Invalid combination: --abi=32 with --abi=64"
 msgstr "Geçersiz birleşim: --abi=32 ve --abi=64"
 
-#: config/tc-sh.c:2681
+#: config/tc-sh.c:3158
 msgid "Invalid combination: --abi=64 with --abi=32"
 msgstr "Geçersiz birleşim: --abi=64 ve --abi=32"
 
-#: config/tc-sh.c:2683
+#: config/tc-sh.c:3160
 msgid "Invalid combination: --isa=SHcompact with --abi=64"
 msgstr "Geçersiz birleşim: --isa=SHcompact ve --abi=64"
 
-#: config/tc-sh.c:2718
+#: config/tc-sh.c:3194
+#, fuzzy, c-format
 msgid ""
 "SH options:\n"
 "-little\t\t\tgenerate little endian code\n"
 "-big\t\t\tgenerate big endian code\n"
 "-relax\t\t\talter jump instructions for long displacements\n"
+"-renesas\t\tdisable optimization with section symbol for\n"
+"\t\t\tcompatibility with Renesas assembler.\n"
 "-small\t\t\talign sections to 4 byte boundaries, not 16\n"
-"-dsp\t\t\tenable sh-dsp insns, and disable sh2e/sh3e/sh4 insns.\n"
+"-dsp\t\t\tenable sh-dsp insns, and disable floating-point ISAs.\n"
+"-isa=[any\t\tuse most appropriate isa\n"
+"    | dsp               same as '-dsp'\n"
+"    | fp"
 msgstr ""
 "SH seçenekleri:\n"
 "-little\t\t\tküçük sonlu kod üretir\n"
@@ -8325,12 +9416,18 @@ msgstr ""
 "-dsp\t\t\tsh-dsp iÅŸlemlerini etkinleÅŸtirir,\n"
 "\t\t\t\tsh3e/sh4 işlemlerini etkisiz kılar.\n"
 
-#: config/tc-sh.c:2726
+#: config/tc-sh.c:3218
+#, c-format
+msgid ""
+"-isa=[shmedia\t\tset as the default instruction set for SH64\n"
+"    | SHmedia\n"
+"    | shcompact\n"
+"    | SHcompact]\n"
+msgstr ""
+
+#: config/tc-sh.c:3223
+#, fuzzy, c-format
 msgid ""
-"-isa=[shmedia\t\tset default instruction set for SH64\n"
-"      | SHmedia\n"
-"      | shcompact\n"
-"      | SHcompact]\n"
 "-abi=[32|64]\t\tset size of expanded SHmedia operands and object\n"
 "\t\t\tfile type\n"
 "-shcompact-const-crange\temit code-range descriptors for constants in\n"
@@ -8339,7 +9436,7 @@ msgid ""
 "\t\t\tconstants and SHcompact code\n"
 "-no-expand\t\tdo not expand MOVI, PT, PTA or PTB instructions\n"
 "-expand-pt32\t\twith -abi=64, expand PT, PTA and PTB instructions\n"
-"\t\t\tto 32 bits only"
+"\t\t\tto 32 bits only\n"
 msgstr ""
 "-isa=[shmedia\t\tSH64 için öntanımlı işlem kümesini belirler\n"
 "      | SHmedia\n"
@@ -8355,273 +9452,90 @@ msgstr ""
 "-expand-pt32\t\t-abi=64 ile PT, PTA ve PTB işlemleri yalnız 32 bite\n"
 "\t\t\t geniÅŸletilir"
 
-#: config/tc-sh.c:2823
+#: config/tc-sh.c:3311
 msgid ".uses does not refer to a local symbol in the same section"
 msgstr ".uses aynı bölümde yerel bir sembole başvurmuyor"
 
-#: config/tc-sh.c:2842
+#: config/tc-sh.c:3330
 msgid "can't find fixup pointed to by .uses"
 msgstr ".uses tarafından imlenen düzeltme bulunamadı"
 
-#: config/tc-sh.c:2865
+#: config/tc-sh.c:3353
 msgid ".uses target does not refer to a local symbol in the same section"
 msgstr ".uses hedefi aynı bölümde yerel bir sembole başvurmuyor"
 
-#: config/tc-sh.c:2967
+#: config/tc-sh.c:3453
 msgid "displacement overflows 12-bit field"
 msgstr "yerdeğişim 12 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:2970
+#: config/tc-sh.c:3456
 #, c-format
 msgid "displacement to defined symbol %s overflows 12-bit field"
 msgstr "tanımlı %s sembolüne yerdeğişim 12 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:2974
+#: config/tc-sh.c:3460
 #, c-format
 msgid "displacement to undefined symbol %s overflows 12-bit field"
 msgstr "tanımlanmamış %s sembolüne yerdeğişim 12 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:3052
+#: config/tc-sh.c:3538
 msgid "displacement overflows 8-bit field"
 msgstr "yerdeğişim 12 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:3055
+#: config/tc-sh.c:3541
 #, c-format
 msgid "displacement to defined symbol %s overflows 8-bit field"
 msgstr "tanımlı %s sembolüne yerdeğişim 8 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:3059
+#: config/tc-sh.c:3545
 #, c-format
 msgid "displacement to undefined symbol %s overflows 8-bit field "
 msgstr "tanımlanmamış %s sembolüne yerdeğişim 8 bitlik alana sığmıyor"
 
-#: config/tc-sh.c:3076
+#: config/tc-sh.c:3562
 #, c-format
 msgid "overflow in branch to %s; converted into longer instruction sequence"
 msgstr "dalda %s'ye taşma; daha uzun işlem dizisine çevrildi"
 
-#: config/tc-sh.c:3151 config/tc-sh.c:3199 config/tc-sparc.c:4192
-#: config/tc-sparc.c:4217
+#: config/tc-sh.c:3633 config/tc-sh.c:3680 config/tc-sparc.c:4237
+#: config/tc-sparc.c:4262
 msgid "misaligned data"
 msgstr "hatalı hizalanmış veri"
 
-#: config/tc-sh.c:3585
+#: config/tc-sh.c:4099
 msgid "misaligned offset"
 msgstr "hatalı hizalanmış görece"
 
-#: config/tc-sh64.c:596
-msgid "This operand must be constant at assembly time"
-msgstr "Bu işlenen çevrim esnasında sabit olmalı"
-
-#: config/tc-sh64.c:711
-msgid "Invalid operand expression"
-msgstr "Geçersiz işlenen ifadesi"
-
-#: config/tc-sh64.c:798 config/tc-sh64.c:904
-msgid "PTB operand is a SHmedia symbol"
-msgstr "PTB işleneni bir SHmedia sembolü"
-
-#: config/tc-sh64.c:801 config/tc-sh64.c:901
-msgid "PTA operand is a SHcompact symbol"
-msgstr "PTA işleneni bir SHcompact sembolü"
-
-#: config/tc-sh64.c:817
-msgid "invalid expression in operand"
-msgstr "İşlenende geçersiz ifade"
-
-#: config/tc-sh64.c:1514
-#, c-format
-msgid "invalid operand, not a 5-bit unsigned value: %d"
-msgstr "Geçersiz işlenen; değeri 5bit unsigned değil: %d"
-
-#: config/tc-sh64.c:1519
-#, c-format
-msgid "invalid operand, not a 6-bit signed value: %d"
-msgstr "Geçersiz işlenen; değeri 6bit unsigned değil: %d"
-
-#: config/tc-sh64.c:1524
-#, c-format
-msgid "invalid operand, not a 6-bit unsigned value: %d"
-msgstr "geçersiz işlenen; değeri 6bit unsigned değil: %d"
-
-#: config/tc-sh64.c:1529 config/tc-sh64.c:1541
-#, c-format
-msgid "invalid operand, not a 11-bit signed value: %d"
-msgstr "geçersiz işlenen; değeri 11bit signed değil: %d"
-
-#: config/tc-sh64.c:1531
-#, c-format
-msgid "invalid operand, not a multiple of 32: %d"
-msgstr "geçersiz işlenen; 32'nin katı değil: %d"
-
-#: config/tc-sh64.c:1536
-#, c-format
-msgid "invalid operand, not a 10-bit signed value: %d"
-msgstr "geçersiz işlenen; değeri 10 bit signed değil: %d"
-
-#: config/tc-sh64.c:1543
-#, c-format
-msgid "invalid operand, not an even value: %d"
-msgstr "geçersiz işlenen; değeri çift sayı değil: %d"
-
-#: config/tc-sh64.c:1548
-#, c-format
-msgid "invalid operand, not a 12-bit signed value: %d"
-msgstr "geçersiz işlenen; değeri 12 bit signed değil: %d"
-
-#: config/tc-sh64.c:1550
-#, c-format
-msgid "invalid operand, not a multiple of 4: %d"
-msgstr "geçersiz işlenen; 4'ün katı değil: %d"
-
-#: config/tc-sh64.c:1555
-#, c-format
-msgid "invalid operand, not a 13-bit signed value: %d"
-msgstr "geçersiz işlenen; değeri 13 bit signed değil: %d"
-
-#: config/tc-sh64.c:1557
-#, c-format
-msgid "invalid operand, not a multiple of 8: %d"
-msgstr "geçersiz işlenen; 8'in katı değil: %d"
-
-#: config/tc-sh64.c:1562
-#, c-format
-msgid "invalid operand, not a 16-bit signed value: %d"
-msgstr "geçersiz işlenen; değeri 16 bit signed değil: %d"
-
-#: config/tc-sh64.c:1567
-#, c-format
-msgid "invalid operand, not an 16-bit unsigned value: %d"
-msgstr "geçersiz işlenen; değeri 16 bit unsigned değil: %d"
-
-#: config/tc-sh64.c:1573
-msgid "operand out of range for PT, PTA and PTB"
-msgstr "işlenen PT, PTA ve PTB için aralık dışı"
-
-#: config/tc-sh64.c:1575
-#, c-format
-msgid "operand not a multiple of 4 for PT, PTA or PTB: %d"
-msgstr "işlenen PT, PTA ve PTB için 4'ün katı olmalı: %d"
-
-#: config/tc-sh64.c:2103
-#, c-format
-msgid "MOVI operand is not a 32-bit signed value: 0x%8x%08x"
-msgstr "MOVI iÅŸleneni 32 bit signed deÄŸil: 0x%8x%08x"
-
-#: config/tc-sh64.c:2466 config/tc-sh64.c:2631 config/tc-sh64.c:2646
-msgid "invalid PIC reference"
-msgstr "geçersiz PIC referansı"
-
-#: config/tc-sh64.c:2524
-msgid "can't find opcode"
-msgstr "opkod bulunamadı"
-
-#: config/tc-sh64.c:2854
-#, c-format
-msgid "invalid operands to %s"
-msgstr "Geçersiz işlenenler: %s"
-
-#: config/tc-sh64.c:2860
-#, c-format
-msgid "excess operands to %s"
-msgstr "fazla iÅŸlenenler: '%s'"
-
-#: config/tc-sh64.c:2906
-#, c-format
-msgid "The `.mode %s' directive is not valid with this architecture"
-msgstr "'.mode %s' yönergesi bu mimari için geçerli değil"
-
-#: config/tc-sh64.c:2914
-#, c-format
-msgid "Invalid argument to .mode: %s"
-msgstr ".mode için geçersiz argüman: %s"
-
-#: config/tc-sh64.c:2945
-#, c-format
-msgid "The `.abi %s' directive is not valid with this architecture"
-msgstr "'.abi %s' yönergesi bu mimari için geçerli değil"
-
-#: config/tc-sh64.c:2951
-msgid "`.abi 64' but command-line options do not specify 64-bit ABI"
-msgstr "'.abi 64' fakat komut satırı seçenekleri 64 bit ABI belirtmiyor"
-
-#: config/tc-sh64.c:2956
-msgid "`.abi 32' but command-line options do not specify 32-bit ABI"
-msgstr "'.abi 32' fakat komut satırı seçenekleri 32 bit ABI belirtmiyor"
-
-#: config/tc-sh64.c:2959
-#, c-format
-msgid "Invalid argument to .abi: %s"
-msgstr ".abi'ye geçersiz argüman: %s"
-
-#: config/tc-sh64.c:3014
-msgid "-no-mix is invalid without specifying SHcompact or SHmedia"
-msgstr "-no-mix, SHcompact veya SHmedia belirtilmeden geçersiz"
-
-#: config/tc-sh64.c:3019
-msgid "-shcompact-const-crange is invalid without SHcompact"
-msgstr "-shcompact-const-crange SHcompact seçeneği olmadan geçersizdir"
-
-#: config/tc-sh64.c:3022
-msgid "-expand-pt32 only valid with -abi=64"
-msgstr "-expand-pt32 ancak -abi=64 ile birlikte geçerli olur"
-
-#: config/tc-sh64.c:3025
-msgid "-no-expand only valid with SHcompact or SHmedia"
-msgstr "-no-expand ancak SHcompact veya SHmedia ile birlikte geçerli olur"
-
-#: config/tc-sh64.c:3028
-msgid "-expand-pt32 invalid together with -no-expand"
-msgstr "-expand-pt32, -no-expand ile birlikte geçersiz olur"
-
-#: config/tc-sh64.c:3250
-msgid "SHmedia code not allowed in same section as constants and SHcompact code"
-msgstr "SHmedia kodu, SHcompact kodu ve sabitlerle aynı bölümde bulunamaz"
-
-#: config/tc-sh64.c:3268
-msgid "No segment info for current section"
-msgstr "Şimdiki bölüm için segment bilgisi yok"
-
-#: config/tc-sh64.c:3310
-msgid "duplicate datalabel operator ignored"
-msgstr "Çoklu veri etiket işlemimi yoksayıldı"
-
-#: config/tc-sh64.c:3380
-msgid "Invalid DataLabel expression"
-msgstr "geçersiz Veri Etiketi ifadesi"
-
-#: config/tc-sparc.c:287
+#: config/tc-sparc.c:291
 msgid "Invalid default architecture, broken assembler."
 msgstr "Geçersiz öntanımlı yapı, hatalı çevirici."
 
-#: config/tc-sparc.c:291 config/tc-sparc.c:494
+#: config/tc-sparc.c:295 config/tc-sparc.c:498
 msgid "Bad opcode table, broken assembler."
 msgstr "Hatalı opkod tablosu, hatalı çevirici"
 
-#: config/tc-sparc.c:486
+#: config/tc-sparc.c:490
 #, c-format
 msgid "invalid architecture -xarch=%s"
 msgstr "geçersiz yapı -xarch=%s"
 
-#: config/tc-sparc.c:488
+#: config/tc-sparc.c:492
 #, c-format
 msgid "invalid architecture -A%s"
 msgstr "geçersiz yapı -A%s"
 
-#: config/tc-sparc.c:555
+#: config/tc-sparc.c:559
 #, c-format
 msgid "No compiled in support for %d bit object file format"
 msgstr "%d bitlik nesne dosyası biçemi için derlenmiş destek yok"
 
-#: config/tc-sparc.c:592
-msgid "Unrecognized option following -K"
-msgstr "-K'dan sonra bilinmeyen seçenek"
-
-#: config/tc-sparc.c:633
+#: config/tc-sparc.c:637
+#, c-format
 msgid "SPARC options:\n"
 msgstr "SPARC seçenekleri:\n"
 
-#: config/tc-sparc.c:662
+#: config/tc-sparc.c:666
+#, c-format
 msgid ""
 "\n"
 "\t\t\tspecify variant of SPARC architecture\n"
@@ -8639,11 +9553,13 @@ msgstr ""
 "-relax\t\t\tsıçrama ve dalları gevşetir (öntanımlı)\n"
 "-no-relax\t\tsıçrama ve dalları değiştirmez\n"
 
-#: config/tc-sparc.c:670
+#: config/tc-sparc.c:674
+#, c-format
 msgid "-k\t\t\tgenerate PIC\n"
 msgstr "-k\t\t\tPIC üretir\n"
 
-#: config/tc-sparc.c:674
+#: config/tc-sparc.c:678
+#, c-format
 msgid ""
 "-32\t\t\tcreate 32 bit object file\n"
 "-64\t\t\tcreate 64 bit object file\n"
@@ -8651,12 +9567,13 @@ msgstr ""
 "-32\t\t\t32 bit nesne dosyası oluşturur\n"
 "-64\t\t\t64 bit nesne dosyası oluşturur\n"
 
-#: config/tc-sparc.c:677
+#: config/tc-sparc.c:681
 #, c-format
 msgid "\t\t\t[default is %d]\n"
 msgstr "\t\t\t[öntanımlı: %d]\n"
 
-#: config/tc-sparc.c:679
+#: config/tc-sparc.c:683
+#, c-format
 msgid ""
 "-TSO\t\t\tuse Total Store Ordering\n"
 "-PSO\t\t\tuse Partial Store Ordering\n"
@@ -8666,12 +9583,13 @@ msgstr ""
 "-PSO\t\t\tKısmi Saklama Sıralaması kullanır\n"
 "-RMO\t\t\tGevşetilmiş Bellek Sıralaması kullanır\n"
 
-#: config/tc-sparc.c:683
+#: config/tc-sparc.c:687
 #, c-format
 msgid "\t\t\t[default is %s]\n"
 msgstr "\t\t\t[öntanımlı: %s]\n"
 
-#: config/tc-sparc.c:685
+#: config/tc-sparc.c:689
+#, c-format
 msgid ""
 "-KPIC\t\t\tgenerate PIC\n"
 "-V\t\t\tprint assembler version number\n"
@@ -8693,7 +9611,8 @@ msgstr ""
 "-Qy, -Qn\t\tyoksayılır\n"
 "-s\t\t\tyoksayılır\n"
 
-#: config/tc-sparc.c:697
+#: config/tc-sparc.c:701
+#, c-format
 msgid ""
 "-EL\t\t\tgenerate code for a little endian machine\n"
 "-EB\t\t\tgenerate code for a big endian machine\n"
@@ -8705,309 +9624,313 @@ msgstr ""
 "--little-endian-data\tbüyük sonlu işlemler ve küçük sonlu veriye sahip\n"
 "                        makinalar için işlem üretir\n"
 
-#: config/tc-sparc.c:817
+#: config/tc-sparc.c:822
 #, c-format
 msgid "Internal error: losing opcode: `%s' \"%s\"\n"
 msgstr "İç hata: opkod kaybedildi:  `%s' \"%s\"\n"
 
-#: config/tc-sparc.c:836
+#: config/tc-sparc.c:841
 #, c-format
 msgid "Internal error: can't find opcode `%s' for `%s'\n"
 msgstr "İç hata: `%2$s' için `%1$s' opkodu bulunamadı\n"
 
-#: config/tc-sparc.c:982
+#: config/tc-sparc.c:987
 msgid "Support for 64-bit arithmetic not compiled in."
 msgstr "64 bitlik aritmetik desteği içine derlenmemiş."
 
-#: config/tc-sparc.c:1029
+#: config/tc-sparc.c:1034
 msgid "set: number not in 0..4294967295 range"
 msgstr "set: sayı 0..4294967295 aralığında değil"
 
-#: config/tc-sparc.c:1036
+#: config/tc-sparc.c:1041
 msgid "set: number not in -2147483648..4294967295 range"
 msgstr "set: sayı -2147483648..4294967295 aralığında değil"
 
-#: config/tc-sparc.c:1096
+#: config/tc-sparc.c:1101
 msgid "setsw: number not in -2147483648..4294967295 range"
 msgstr "setsw: sayı -2147483648..4294967295 aralığında değil"
 
-#: config/tc-sparc.c:1145
+#: config/tc-sparc.c:1150
 msgid "setx: temporary register same as destination register"
 msgstr "setx: geçici yazmaç, hedef yazmaçla aynı"
 
-#: config/tc-sparc.c:1216
+#: config/tc-sparc.c:1221
 msgid "setx: illegal temporary register g0"
 msgstr "setx: geçersiz geçici yazmaç g0"
 
-#: config/tc-sparc.c:1313
+#: config/tc-sparc.c:1318
 msgid "FP branch in delay slot"
 msgstr "gecikme yuvasında FP dalı"
 
-#: config/tc-sparc.c:1329
+#: config/tc-sparc.c:1334
 msgid "FP branch preceded by FP instruction; NOP inserted"
 msgstr "FP dalından önce FP işlemi geldi; NOP eklendi"
 
-#: config/tc-sparc.c:1369
+#: config/tc-sparc.c:1374
 msgid "failed special case insn sanity check"
 msgstr "özel durum işlem kontrolü başarısız"
 
-#: config/tc-sparc.c:1457
+#: config/tc-sparc.c:1462
 msgid ": invalid membar mask name"
 msgstr ": geçersiz membar maske adı"
 
-#: config/tc-sparc.c:1473
+#: config/tc-sparc.c:1478
 msgid ": invalid membar mask expression"
 msgstr ": geçersiz membar maske ifadesi"
 
-#: config/tc-sparc.c:1478
+#: config/tc-sparc.c:1483
 msgid ": invalid membar mask number"
 msgstr ": geçersiz membar maske numarası"
 
-#: config/tc-sparc.c:1493
+#: config/tc-sparc.c:1498
 msgid ": invalid siam mode expression"
 msgstr ": geçersiz siam kipi ifadesi"
 
-#: config/tc-sparc.c:1498
+#: config/tc-sparc.c:1503
 msgid ": invalid siam mode number"
 msgstr ": geçersiz siam kip numarası"
 
-#: config/tc-sparc.c:1514
+#: config/tc-sparc.c:1519
 msgid ": invalid prefetch function name"
 msgstr ": geçersiz prefetch işlev adı"
 
-#: config/tc-sparc.c:1522
+#: config/tc-sparc.c:1527
 msgid ": invalid prefetch function expression"
 msgstr ": geçersiz prefetch işlev ifadesi"
 
-#: config/tc-sparc.c:1527
+#: config/tc-sparc.c:1532
 msgid ": invalid prefetch function number"
 msgstr ": geçersiz prefetch işlev numarası"
 
-#: config/tc-sparc.c:1555 config/tc-sparc.c:1567
+#: config/tc-sparc.c:1560 config/tc-sparc.c:1572
 msgid ": unrecognizable privileged register"
 msgstr ": bilinmeyen ayrıcalıklı yazmaç"
 
-#: config/tc-sparc.c:1591 config/tc-sparc.c:1616
+#: config/tc-sparc.c:1596 config/tc-sparc.c:1621
 msgid ": unrecognizable v9a or v9b ancillary state register"
 msgstr ": bilinmeyen v9a veya v9b yardımcı durum yazmacı"
 
-#: config/tc-sparc.c:1596
+#: config/tc-sparc.c:1601
 msgid ": rd on write only ancillary state register"
 msgstr ": salt yazılır yardımcı durum yazmacında rd (okuma)"
 
 #. %sys_tick and %sys_tick_cmpr are v9bnotv9a
-#: config/tc-sparc.c:1604
+#: config/tc-sparc.c:1609
 msgid ": unrecognizable v9a ancillary state register"
 msgstr ": bilinmeyen v9a yardımcı durum yazmacı"
 
-#: config/tc-sparc.c:1640
+#: config/tc-sparc.c:1645
 msgid ": asr number must be between 16 and 31"
 msgstr ": asr sayısı 16 ve 31 arasında olmalı"
 
-#: config/tc-sparc.c:1648
+#: config/tc-sparc.c:1653
 msgid ": asr number must be between 0 and 31"
 msgstr ": asr numarası 0 ve 31 arasında olmalı"
 
-#: config/tc-sparc.c:1658
+#: config/tc-sparc.c:1663
 #, c-format
 msgid ": expecting %asrN"
 msgstr ": %asrN beklendi"
 
-#: config/tc-sparc.c:1840 config/tc-sparc.c:1878 config/tc-sparc.c:2279
-#: config/tc-sparc.c:2315
+#: config/tc-sparc.c:1845 config/tc-sparc.c:1883 config/tc-sparc.c:2290
+#: config/tc-sparc.c:2326
 #, c-format
 msgid "Illegal operands: %%%s requires arguments in ()"
 msgstr "Geçersiz işlenen: %%%s, () içinde argüman istiyor"
 
-#: config/tc-sparc.c:1846
+#: config/tc-sparc.c:1851
 #, c-format
 msgid "Illegal operands: %%%s cannot be used together with other relocs in the insn ()"
 msgstr "Geçersiz işlenen: %%%s, () işlemindeki başka yerdeğişimlerle beraber kullanılamaz"
 
-#: config/tc-sparc.c:1857
+#: config/tc-sparc.c:1862
 #, c-format
 msgid "Illegal operands: %%%s can be only used with call __tls_get_addr"
 msgstr "Geçersiz işlenen: %%%s ancak __tls_get_addr çağrısı ile beraber kullanılabilir"
 
-#: config/tc-sparc.c:2064
+#: config/tc-sparc.c:2069
 msgid "detected global register use not covered by .register pseudo-op"
 msgstr ".register sanal op tarafından desteklenmeyen evrensel yazmaç kullanımı bulundu"
 
-#: config/tc-sparc.c:2135
+#: config/tc-sparc.c:2140
 msgid ": There are only 64 f registers; [0-63]"
 msgstr ": Yalnızca 64 f yazmacı var; [0-63]"
 
-#: config/tc-sparc.c:2137 config/tc-sparc.c:2149
+#: config/tc-sparc.c:2142 config/tc-sparc.c:2160
 msgid ": There are only 32 f registers; [0-31]"
 msgstr ": Yalnız 32 f yazmacı var; [0-31]"
 
-#: config/tc-sparc.c:2327
+#: config/tc-sparc.c:2152
+#, fuzzy
+msgid ": There are only 32 single precision f registers; [0-31]"
+msgstr ": Yalnız 32 f yazmacı var; [0-31]"
+
+#: config/tc-sparc.c:2338
 #, c-format
 msgid "Illegal operands: Can't do arithmetics other than + and - involving %%%s()"
 msgstr "Geçersiz işlenenler: %%%s() ile ilgili + ve -'den başka aritmetik yapılamaz"
 
-#: config/tc-sparc.c:2437
+#: config/tc-sparc.c:2448
 #, c-format
 msgid "Illegal operands: Can't add non-constant expression to %%%s()"
 msgstr "Geçersiz işlenenler: Sabit olmayan ifade %%%s()'e eklenemez"
 
-#: config/tc-sparc.c:2447
+#: config/tc-sparc.c:2458
 #, c-format
 msgid "Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"
 msgstr ""
 "Geçersiz işlenenler: Yerdeğiştirebilen bir sembolün %%%s()'ı ile ilgili\n"
 "aritmetik yapılamaz"
 
-#: config/tc-sparc.c:2465
+#: config/tc-sparc.c:2476
 msgid ": PC-relative operand can't be a constant"
 msgstr ": PC göreli işlenen sabit olamaz"
 
-#: config/tc-sparc.c:2472
+#: config/tc-sparc.c:2483
 msgid ": TLS operand can't be a constant"
 msgstr ": TLS iÅŸleneni sabit olamaz"
 
-#: config/tc-sparc.c:2505
+#: config/tc-sparc.c:2516
 msgid ": invalid ASI name"
 msgstr ": geçersiz ASI ismi"
 
-#: config/tc-sparc.c:2513
+#: config/tc-sparc.c:2524
 msgid ": invalid ASI expression"
 msgstr ": geçersiz ASI ifadesi"
 
-#: config/tc-sparc.c:2518
+#: config/tc-sparc.c:2529
 msgid ": invalid ASI number"
 msgstr ": geçersiz ASI sayısı"
 
-#: config/tc-sparc.c:2615
+#: config/tc-sparc.c:2626
 msgid "OPF immediate operand out of range (0-0x1ff)"
 msgstr "OPF şimdiki işlenenleri aralık dışı (0-0x1ff)"
 
-#: config/tc-sparc.c:2620
+#: config/tc-sparc.c:2631
 msgid "non-immediate OPF operand, ignored"
 msgstr "şimdiki olmayan OPF işleneni, yoksayıldı"
 
-#: config/tc-sparc.c:2639
+#: config/tc-sparc.c:2650
 msgid ": invalid cpreg name"
 msgstr ": geçersiz cpreg ismi"
 
-#: config/tc-sparc.c:2668
+#: config/tc-sparc.c:2679
 #, c-format
 msgid "Illegal operands%s"
 msgstr "Geçersiz işlenen %s"
 
-#: config/tc-sparc.c:2702
+#: config/tc-sparc.c:2713
 #, c-format
 msgid "architecture bumped from \"%s\" to \"%s\" on \"%s\""
 msgstr "\"%3$s\" üzerinde yapı, \"%1$s\"den \"%2$s\"e yükseltildi"
 
-#: config/tc-sparc.c:2738
+#: config/tc-sparc.c:2749
 #, c-format
 msgid "Architecture mismatch on \"%s\"."
 msgstr "\"%s\" üzerinde yapı uyumsuzluğu"
 
-#: config/tc-sparc.c:2739
+#: config/tc-sparc.c:2750
 #, c-format
 msgid " (Requires %s; requested architecture is %s.)"
 msgstr " (%s gerekli; talep edilen yapı: %s.)"
 
-#: config/tc-sparc.c:3325
+#: config/tc-sparc.c:3370
 #, c-format
 msgid "bad or unhandled relocation type: 0x%02x"
 msgstr "hatalı veya desteklenmeyen yerdeğişim türü: 0x%02x"
 
-#: config/tc-sparc.c:3480
-#, c-format
-msgid "internal error: can't export reloc type %d (`%s')"
-msgstr "iç hata: %d yerdeğişim türü ihraç edilemedi (`%s')"
+#: config/tc-sparc.c:3680
+msgid "Expected comma after name"
+msgstr "İsimden sonra virgül beklendi"
 
-#: config/tc-sparc.c:3644
+#: config/tc-sparc.c:3689
 #, c-format
 msgid "BSS length (%d.) <0! Ignored."
 msgstr "BSS uzunluğu (%d.) <0! Yoksayıldı."
 
-#: config/tc-sparc.c:3656
+#: config/tc-sparc.c:3701
 msgid "bad .reserve segment -- expected BSS segment"
 msgstr "hatalı .reserve bölümü -- BSS bölümü beklendi"
 
-#: config/tc-sparc.c:3673 read.c:2048
+#: config/tc-sparc.c:3718
 msgid "missing alignment"
 msgstr "hizalama eksik"
 
-#: config/tc-sparc.c:3684 config/tc-sparc.c:3835
+#: config/tc-sparc.c:3729
 #, c-format
 msgid "alignment too large; assuming %d"
 msgstr "hizalama fazla büyük; %d varsayıldı"
 
-#: config/tc-sparc.c:3690 config/tc-sparc.c:3841
+#: config/tc-sparc.c:3735 config/tc-sparc.c:3886
 msgid "negative alignment"
 msgstr "negatif hizalama"
 
-#: config/tc-sparc.c:3700 config/tc-sparc.c:3864 read.c:1251 read.c:2064
+#: config/tc-sparc.c:3745 config/tc-sparc.c:3909 read.c:1284 read.c:2113
 msgid "alignment not a power of 2"
 msgstr "hizalama 2'nin kuvveti deÄŸil"
 
-#: config/tc-sparc.c:3778 config/tc-v850.c:233
+#: config/tc-sparc.c:3823 config/tc-v850.c:233
 msgid "Expected comma after symbol-name"
 msgstr "Sembol adından sonra virgül beklendi"
 
-#: config/tc-sparc.c:3788 read.c:1392
+#: config/tc-sparc.c:3833
 #, c-format
 msgid ".COMMon length (%lu) out of range ignored"
 msgstr ".COMM ortak uzunluğu (%lu) kapsam dışı, yoksayıldı"
 
-#: config/tc-sparc.c:3807 config/tc-v850.c:266
-#, c-format
-msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
-msgstr ".comm \"%s\" uzunluÄŸu zaten %ld. %d olarak deÄŸiÅŸtirilmedi."
-
-#: config/tc-sparc.c:3821
+#: config/tc-sparc.c:3866
 msgid "Expected comma after common length"
 msgstr "Ortak uzunluktan sonra virgül beklendi"
 
-#: config/tc-sparc.c:4062 config/tc-sparc.c:4072
+#: config/tc-sparc.c:3880
+#, fuzzy, c-format
+msgid "alignment too large; assuming %ld"
+msgstr "hizalama fazla büyük; %d varsayıldı"
+
+#: config/tc-sparc.c:4107 config/tc-sparc.c:4117
 #, c-format
 msgid "register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"
 msgstr "yazmaç sözdizimi .register %%g[2367],{#scratch|sembolismi|#ignore} olmalı"
 
-#: config/tc-sparc.c:4090
+#: config/tc-sparc.c:4135
 msgid "redefinition of global register"
 msgstr "evrensel yazmaç yeniden tanımlanmış"
 
-#: config/tc-sparc.c:4101
+#: config/tc-sparc.c:4146
 #, c-format
 msgid "Register symbol %s already defined."
 msgstr "Yazmaç sembolü %s zaten tanımlı."
 
-#: config/tc-sparc.c:4310
+#: config/tc-sparc.c:4355
 #, c-format
 msgid "Illegal operands: %%r_plt in %d-byte data field"
 msgstr "Geçersiz işlenenler: %d-bayt veri alanında %%r_plt"
 
-#: config/tc-sparc.c:4320
+#: config/tc-sparc.c:4365
 #, c-format
 msgid "Illegal operands: %%r_tls_dtpoff in %d-byte data field"
 msgstr "Geçersiz işlenenler: %d-bayt veri alanında %%r_tls_dtpoff"
 
-#: config/tc-sparc.c:4357
+#: config/tc-sparc.c:4402
 #, c-format
 msgid "Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"
 msgstr "Geçersiz işlenenler: %3$d-bayt veri alanlarında yalnız %%r_%1$s%2$d"
 
-#: config/tc-sparc.c:4365 config/tc-sparc.c:4396 config/tc-sparc.c:4405
+#: config/tc-sparc.c:4410 config/tc-sparc.c:4441 config/tc-sparc.c:4450
 #, c-format
 msgid "Illegal operands: %%r_%s%d requires arguments in ()"
 msgstr "Geçersiz işlenen: %%r_%s%d, () içinde argüman istiyor"
 
-#: config/tc-sparc.c:4414
+#: config/tc-sparc.c:4459
 #, c-format
 msgid "Illegal operands: garbage after %%r_%s%d()"
 msgstr "Geçersiz işlenen: %%r_%s%d() sonrasında karmaşıklık"
 
-#: config/tc-sparc.h:55
+#: config/tc-sparc.h:48
 msgid "sparc convert_frag\n"
 msgstr "sparc convert_frag\n"
 
-#: config/tc-sparc.h:57
+#: config/tc-sparc.h:50
 msgid "estimate_size_before_relax called"
 msgstr "estimate_size_before_relax çağrısı"
 
@@ -9015,29 +9938,30 @@ msgstr "estimate_size_before_relax çağrısı"
 msgid "The -a option doesn't exist. (Despite what the man page says!"
 msgstr "-a seçeneği mevcut değil. (man sayfası ne derse desin!)"
 
-#: config/tc-tahoe.c:407 config/tc-vax.c:3285
+#: config/tc-tahoe.c:407 config/tc-vax.c:3295
 #, c-format
 msgid "Displacement length %s ignored!"
 msgstr "Kaydırma uzunluğu %s yoksayıldı!"
 
-#: config/tc-tahoe.c:411 config/tc-vax.c:3277
+#: config/tc-tahoe.c:411 config/tc-vax.c:3287
 msgid "SYMBOL TABLE not implemented"
 msgstr "SEMBOL TABLOsu henüz desteklenmiyor"
 
-#: config/tc-tahoe.c:415 config/tc-vax.c:3281
+#: config/tc-tahoe.c:415 config/tc-vax.c:3291
 msgid "TOKEN TRACE not implemented"
 msgstr "DİZGECİK İZLEMESİ (token trace) henüz desteklenmiyor"
 
-#: config/tc-tahoe.c:419 config/tc-vax.c:3289
+#: config/tc-tahoe.c:419 config/tc-vax.c:3299
 #, c-format
 msgid "I don't need or use temp. file \"%s\"."
 msgstr "\"%s\" geçici dosyası istenmiyor ve kullanılmıyor."
 
-#: config/tc-tahoe.c:423 config/tc-vax.c:3293
+#: config/tc-tahoe.c:423 config/tc-vax.c:3303
 msgid "I don't use an interpass file! -V ignored"
 msgstr "Interpass dosyası kullanılmıyor! -V yoksayıldı"
 
 #: config/tc-tahoe.c:437
+#, c-format
 msgid ""
 "Tahoe options:\n"
 "-a\t\t\tignored\n"
@@ -9209,15 +10133,15 @@ msgstr "Şimdiki erişim bir adres olarak kullanılamaz."
 msgid "Compiler bug: ODD number of bytes in arg structure %s."
 msgstr "Derleyici hatası: Argüman yapısı %s'da TEK sayılı bayt."
 
-#: config/tc-tahoe.c:1567 config/tc-vax.c:1962
+#: config/tc-tahoe.c:1567 config/tc-vax.c:1968
 msgid "Not enough operands"
 msgstr "Yeteri kadar iÅŸlenen yok"
 
-#: config/tc-tahoe.c:1577 config/tc-vax.c:1969
+#: config/tc-tahoe.c:1577 config/tc-vax.c:1975
 msgid "Too many operands"
 msgstr "Çok fazla işlenen"
 
-#: config/tc-tahoe.c:1628 config/tc-vax.c:403
+#: config/tc-tahoe.c:1628 config/tc-vax.c:408
 #, c-format
 msgid "Ignoring statement due to \"%s\""
 msgstr "\"%s\" yüzünden deyim yoksayıldı"
@@ -9243,523 +10167,524 @@ msgstr "Hatalı %x kipi\n"
 
 #. Only word (et al.), align, or conditionals are allowed within
 #. .struct/.union.
-#: config/tc-tic54x.c:224
+#: config/tc-tic54x.c:222
 msgid "pseudo-op illegal within .struct/.union"
 msgstr "sanal op .struct/.union içinde geçersiz"
 
-#: config/tc-tic54x.c:349
+#: config/tc-tic54x.c:347
+#, c-format
 msgid "C54x-specific command line  options:\n"
 msgstr "C54x'e özgü komut satırı seçenekleri:\n"
 
-#: config/tc-tic54x.c:350
+#: config/tc-tic54x.c:348
+#, c-format
 msgid "-mfar-mode | -mf          Use extended addressing\n"
 msgstr "-mfar-mode | -mf          Genişletilmiş adresleme kullanır\n"
 
-#: config/tc-tic54x.c:351
+#: config/tc-tic54x.c:349
+#, c-format
 msgid "-mcpu=<CPU version>       Specify the CPU version\n"
 msgstr "-mcpu=<işlemci sürümü>    İşlemci sürümünü belirtir\n"
 
-#: config/tc-tic54x.c:353
-msgid "-mcoff-version={0|1|2}    Select COFF version\n"
-msgstr "-mcoff-version={0|1|2}    COFF sürümünü belirtir\n"
-
-#: config/tc-tic54x.c:355
+#: config/tc-tic54x.c:350
+#, c-format
 msgid "-merrors-to-file <filename>\n"
 msgstr "-merrors-to-file <dosya adı>\n"
 
-#: config/tc-tic54x.c:356
+#: config/tc-tic54x.c:351
+#, c-format
 msgid "-me <filename>            Redirect errors to a file\n"
 msgstr "-me <dosya adı>           Hataları bir dosyaya yönlendirir\n"
 
-#: config/tc-tic54x.c:478
+#: config/tc-tic54x.c:473
 msgid "Comma and symbol expected for '.asg STRING, SYMBOL'"
 msgstr "'.asg DİZGE, SEMBOL' için virgül ve sembol beklendi"
 
-#: config/tc-tic54x.c:532
+#: config/tc-tic54x.c:527
 msgid "Unterminated string after absolute expression"
 msgstr "Kesin ifadeden sonra sonlanmamış dizge"
 
-#: config/tc-tic54x.c:540
+#: config/tc-tic54x.c:535
 msgid "Comma and symbol expected for '.eval EXPR, SYMBOL'"
 msgstr "'.eval İFADE, SEMBOL' için virgül ve sembol beklendi"
 
-#: config/tc-tic54x.c:552
+#: config/tc-tic54x.c:547
 msgid "symbols assigned with .eval must begin with a letter"
 msgstr ".eval ile atanmış semboller bir harfle başlamalı"
 
-#: config/tc-tic54x.c:810
+#: config/tc-tic54x.c:805
 msgid "Offset on nested structures is ignored"
 msgstr "İçiçe yapılarda görece yoksayılır"
 
-#: config/tc-tic54x.c:861
+#: config/tc-tic54x.c:856
 #, c-format
 msgid ".end%s without preceding .%s"
 msgstr "öncesinde .%s olmayan .end%s"
 
-#: config/tc-tic54x.c:928
+#: config/tc-tic54x.c:923
 #, c-format
 msgid "Unrecognized struct/union tag '%s'"
 msgstr "Bilinmeyen struct/union etiketi '%s'"
 
-#: config/tc-tic54x.c:930
+#: config/tc-tic54x.c:925
 msgid ".tag requires a structure tag"
 msgstr ".tag bir yapı etiketi gerektirir"
 
-#: config/tc-tic54x.c:936
+#: config/tc-tic54x.c:931
 msgid "Label required for .tag"
 msgstr ".tag için etiket gerekli"
 
-#: config/tc-tic54x.c:955
+#: config/tc-tic54x.c:950
 #, c-format
 msgid ".tag target '%s' undefined"
 msgstr ".tag hedefi '%s' tanımlanmamış"
 
-#: config/tc-tic54x.c:1018
+#: config/tc-tic54x.c:1013
 #, c-format
 msgid ".field count '%d' out of range (1 <= X <= 32)"
 msgstr ".field (alan) sayısı '%d' aralık dışı (1 <= X <= 32)"
 
-#: config/tc-tic54x.c:1046
+#: config/tc-tic54x.c:1041
 #, c-format
 msgid "Unrecognized field type '%c'"
 msgstr "Bilinmeyen alan türü '%c'"
 
 #. Disallow .byte with a non constant expression that will
 #. require relocation.
-#: config/tc-tic54x.c:1183
+#: config/tc-tic54x.c:1178
 msgid "Relocatable values require at least WORD storage"
 msgstr "Yerdeğiştirebilen değerler en az WORD saklama türünden olmalıdır"
 
-#: config/tc-tic54x.c:1245
+#: config/tc-tic54x.c:1240
 msgid "Use of .def/.ref is deprecated.  Use .global instead"
 msgstr ".def/.ref kullanımı artık geçersiz. Yerine .global kullanın"
 
-#: config/tc-tic54x.c:1444
+#: config/tc-tic54x.c:1439
 msgid ".space/.bes repeat count is negative, ignored"
 msgstr ".space/.bes tekrar sayısı negatif, yoksayıldı"
 
-#: config/tc-tic54x.c:1449
+#: config/tc-tic54x.c:1444
 msgid ".space/.bes repeat count is zero, ignored"
 msgstr ".space/.bes tekrar sayısı sıfır, yoksayıldı"
 
-#: config/tc-tic54x.c:1527
+#: config/tc-tic54x.c:1522
 msgid "Missing size argument"
 msgstr "Eksik boyut argümanı"
 
-#: config/tc-tic54x.c:1664
+#: config/tc-tic54x.c:1659
 msgid "CPU version has already been set"
 msgstr "İşlemci sürümü zaten belirtilmiş"
 
-#: config/tc-tic54x.c:1668
+#: config/tc-tic54x.c:1663
 #, c-format
 msgid "Unrecognized version '%s'"
 msgstr "Bilinmeyen sürüm '%s'"
 
-#: config/tc-tic54x.c:1674
+#: config/tc-tic54x.c:1669
 msgid "Changing of CPU version on the fly not supported"
 msgstr "İşlemci sürümünü çevrim içinde değiştirmek desteklenmiyor"
 
-#: config/tc-tic54x.c:1810
+#: config/tc-tic54x.c:1805
 msgid "p2align not supported on this target"
 msgstr "p2align bu hedef üzerinde desteklenmiyor"
 
-#: config/tc-tic54x.c:1823
+#: config/tc-tic54x.c:1818
 msgid "Argument to .even ignored"
 msgstr ".even'a argüman yoksayıldı"
 
-#: config/tc-tic54x.c:1870
+#: config/tc-tic54x.c:1865
 msgid "Invalid field size, must be from 1 to 32"
 msgstr "Geçersiz alan boyutu, 1'den 32'ye kadar olmalı"
 
-#: config/tc-tic54x.c:1883
+#: config/tc-tic54x.c:1878
 msgid "field size must be 16 when value is relocatable"
 msgstr "değer yerdeğişebilir olduğu zaman alan boyu 16 olmalı"
 
-#: config/tc-tic54x.c:1898
+#: config/tc-tic54x.c:1893
 msgid "field value truncated"
 msgstr "alan değeri budandı"
 
-#: config/tc-tic54x.c:2007 config/tc-tic54x.c:2324
+#: config/tc-tic54x.c:2002 config/tc-tic54x.c:2319
 #, c-format
 msgid "Unrecognized section '%s'"
 msgstr "Bilinmeyen bölüm '%s'"
 
-#: config/tc-tic54x.c:2016
+#: config/tc-tic54x.c:2011
 msgid "Current section is unitialized, section name required for .clink"
 msgstr "Şimdiki bölüm ilklenmemiş, .clink için bölüm ismi gerekli"
 
-#: config/tc-tic54x.c:2230
+#: config/tc-tic54x.c:2225
 msgid "ENDLOOP without corresponding LOOP"
 msgstr "LOOP olmaksızın ENDLOOP"
 
-#: config/tc-tic54x.c:2274
+#: config/tc-tic54x.c:2269
 msgid "Mixing of normal and extended addressing not supported"
 msgstr "Normal ve genişletilmiş adreslemelerin karışımı desteklenmiyor"
 
-#: config/tc-tic54x.c:2280
+#: config/tc-tic54x.c:2275
 msgid "Extended addressing not supported on the specified CPU"
 msgstr "Belirtilen iÅŸlemcide geniÅŸletilmiÅŸ adresleme desteklenmiyor"
 
-#: config/tc-tic54x.c:2330
+#: config/tc-tic54x.c:2325
 msgid ".sblock may be used for initialized sections only"
 msgstr ".sblock yalnız ilklenmiş bölümler için kullanılabilir"
 
-#: config/tc-tic54x.c:2361
+#: config/tc-tic54x.c:2356
 msgid "Symbol missing for .set/.equ"
 msgstr ".set/.equ için sembol eksik"
 
-#: config/tc-tic54x.c:2420
+#: config/tc-tic54x.c:2415
 msgid ".var may only be used within a macro definition"
 msgstr ".var yalnız bir makro tanımı içinde kullanılabilir"
 
-#: config/tc-tic54x.c:2428
+#: config/tc-tic54x.c:2423
 msgid "Substitution symbols must begin with a letter"
 msgstr "İkame sembolleri bir harfle başlamalı"
 
-#: config/tc-tic54x.c:2522
+#: config/tc-tic54x.c:2517
 #, c-format
 msgid "Can't open macro library file '%s' for reading."
 msgstr "Makro kitaplık dosyası '%s' okuma için açılamadı."
 
-#: config/tc-tic54x.c:2529
+#: config/tc-tic54x.c:2524
 #, c-format
 msgid "File '%s' not in macro archive format"
 msgstr "'%s' dosyası makro arşiv biçeminde değil"
 
-#: config/tc-tic54x.c:2689
+#: config/tc-tic54x.c:2656
 #, c-format
 msgid "Bad COFF version '%s'"
 msgstr "Hatalı COFF sürümü '%s'"
 
-#: config/tc-tic54x.c:2698
+#: config/tc-tic54x.c:2665
 #, c-format
 msgid "Bad CPU version '%s'"
 msgstr "Hatalı işlemci sürümü '%s'"
 
-#: config/tc-tic54x.c:2711 config/tc-tic54x.c:2714
+#: config/tc-tic54x.c:2678 config/tc-tic54x.c:2681
 #, c-format
 msgid "Can't redirect stderr to the file '%s'"
 msgstr "Standart hata (stderr) '%s' dosyasına yönlendirilemez"
 
-#: config/tc-tic54x.c:2861
+#: config/tc-tic54x.c:2828
 #, c-format
 msgid "Undefined substitution symbol '%s'"
 msgstr "Tanımsız ikame sembolü '%s'"
 
-#: config/tc-tic54x.c:3518
+#: config/tc-tic54x.c:3485
 msgid "Badly formed address expression"
 msgstr "Hatalı oluşturulmuş adres ifadesi"
 
-#: config/tc-tic54x.c:3782
+#: config/tc-tic54x.c:3749
 #, c-format
 msgid "Invalid dmad syntax '%s'"
 msgstr "Geçersiz dmad sözdizimi '%s'"
 
-#: config/tc-tic54x.c:3848
+#: config/tc-tic54x.c:3815
 #, c-format
 msgid "Use the .mmregs directive to use memory-mapped register names such as '%s'"
 msgstr ""
 "'%s' gibi bellek eşlemeli yazmaç adlarını kullanmak için .mmregs yönergesini\n"
 "kullanın"
 
-#: config/tc-tic54x.c:3901
+#: config/tc-tic54x.c:3868
 msgid "Address mode *+ARx is write-only. Results of reading are undefined."
 msgstr "Adres kipi *+ARx salt yazılır. Okuma sonuçları tanımsız."
 
-#: config/tc-tic54x.c:3921
+#: config/tc-tic54x.c:3888
 #, c-format
 msgid "Unrecognized indirect address format \"%s\""
 msgstr "Bilinmeyen dolaylı adresleme biçemi \"%s\""
 
-#: config/tc-tic54x.c:3960
+#: config/tc-tic54x.c:3927
 #, c-format
 msgid "Operand '%s' out of range (%d <= x <= %d)"
 msgstr "'%s' işleneni aralık dışı (%d <= x <= %d)"
 
-#: config/tc-tic54x.c:3980
+#: config/tc-tic54x.c:3947
 msgid "Error in relocation handling"
 msgstr "YerdeÄŸiÅŸim desteÄŸinde hata"
 
-#: config/tc-tic54x.c:4001 config/tc-tic54x.c:4065 config/tc-tic54x.c:4097
+#: config/tc-tic54x.c:3968 config/tc-tic54x.c:4032 config/tc-tic54x.c:4064
 #, c-format
 msgid "Unrecognized condition code \"%s\""
 msgstr "Bilinmeyen koÅŸul kodu \"%s\""
 
-#: config/tc-tic54x.c:4018
+#: config/tc-tic54x.c:3985
 #, c-format
 msgid "Condition \"%s\" does not match preceding group"
 msgstr "\"%s\" koşulu önceki grupla eşleşmiyor"
 
-#: config/tc-tic54x.c:4026
+#: config/tc-tic54x.c:3993
 #, c-format
 msgid "Condition \"%s\" uses a different accumulator from a preceding condition"
 msgstr "\"%s\" koşulu önceki koşuldan daha farklı bir biriktirici kullanıyor"
 
-#: config/tc-tic54x.c:4033
+#: config/tc-tic54x.c:4000
 msgid "Only one comparison conditional allowed"
 msgstr "Yalnızca bir karşılaştırma koşulu kullanılabilir"
 
-#: config/tc-tic54x.c:4038
+#: config/tc-tic54x.c:4005
 msgid "Only one overflow conditional allowed"
 msgstr "Yalnızca bir taşma koşulu kullanılabilir"
 
-#: config/tc-tic54x.c:4046
+#: config/tc-tic54x.c:4013
 #, c-format
 msgid "Duplicate %s conditional"
 msgstr "Birden fazla %s koÅŸulu"
 
-#: config/tc-tic54x.c:4081
+#: config/tc-tic54x.c:4048
 msgid "Invalid auxiliary register (use AR0-AR7)"
 msgstr "Geçersiz yardımcı yazmaç (AR0-AR7 kullanın)"
 
-#: config/tc-tic54x.c:4117
+#: config/tc-tic54x.c:4084
 msgid "lk addressing modes are invalid for memory-mapped register addressing"
 msgstr "1k adresleme kipleri bellek-eşlemeli yazmaç adreslemesi için geçersiz"
 
-#: config/tc-tic54x.c:4125
+#: config/tc-tic54x.c:4092
 msgid "Address mode *+ARx is not allowed in memory-mapped register addressing.  Resulting behavior is undefined."
 msgstr "*+ARx adresleme kipi bellek eşlemeli yazmaç adreslemesinde kullanılamaz. Oluşan durum tanımsız."
 
-#: config/tc-tic54x.c:4151
+#: config/tc-tic54x.c:4118
 msgid "Destination accumulator for each part of this parallel instruction must be different"
 msgstr "Bu paralel işlemin her parçası için hedef biriktirici farklı olmalı."
 
-#: config/tc-tic54x.c:4200
+#: config/tc-tic54x.c:4167
 #, c-format
 msgid "Memory mapped register \"%s\" out of range"
 msgstr "Bellek eşlemeli \"%s\" yazmacı kapsam dışı"
 
-#: config/tc-tic54x.c:4239
+#: config/tc-tic54x.c:4206
 msgid "Invalid operand (use 1, 2, or 3)"
 msgstr "Geçersiz işlenen (1, 2 veya 3 kullanın)"
 
-#: config/tc-tic54x.c:4264
+#: config/tc-tic54x.c:4231
 msgid "A status register or status bit name is required"
 msgstr "Durum yazmacı veya durum bit ismi gerekli"
 
-#: config/tc-tic54x.c:4274
+#: config/tc-tic54x.c:4241
 #, c-format
 msgid "Unrecognized status bit \"%s\""
 msgstr "Bilinmeyen durum biti \"%s\""
 
-#: config/tc-tic54x.c:4297
+#: config/tc-tic54x.c:4264
 #, c-format
 msgid "Invalid status register \"%s\""
 msgstr "Geçersiz durum yazmacı \"%s\""
 
-#: config/tc-tic54x.c:4309
+#: config/tc-tic54x.c:4276
 #, c-format
 msgid "Operand \"%s\" out of range (use 1 or 2)"
 msgstr "\"%s\" işleneni aralık dışı (1 veya 2 kullanın)"
 
-#: config/tc-tic54x.c:4517
+#: config/tc-tic54x.c:4484
 #, c-format
 msgid "Unrecognized instruction \"%s\""
 msgstr "Bilinmeyen iÅŸlem \"%s\""
 
-#: config/tc-tic54x.c:4546
+#: config/tc-tic54x.c:4513
 #, c-format
 msgid "Unrecognized operand list '%s' for instruction '%s'"
 msgstr "'%2$s' işlemi için bilinmeyen işlenen listesi '%1$s'"
 
-#: config/tc-tic54x.c:4578
+#: config/tc-tic54x.c:4545
 #, c-format
 msgid "Unrecognized parallel instruction \"%s\""
 msgstr "Bilinmeyen paralel iÅŸlem \"%s\""
 
-#: config/tc-tic54x.c:4629
+#: config/tc-tic54x.c:4596
 #, c-format
 msgid "Invalid operand (s) for parallel instruction \"%s\""
 msgstr "\"%s\" paralel işlemi için geçersiz işlenen(ler)"
 
-#: config/tc-tic54x.c:4632
+#: config/tc-tic54x.c:4599
 #, c-format
 msgid "Unrecognized parallel instruction combination \"%s || %s\""
 msgstr "Bilinmeyen paralel iÅŸlem birleÅŸimi \"%s || %s\""
 
-#: config/tc-tic54x.c:4869
+#: config/tc-tic54x.c:4836
 #, c-format
 msgid "%s symbol recursion stopped at second appearance of '%s'"
 msgstr "%s sembol çevrimi '%s'nın ikinci görülmesinde durduruldu"
 
-#: config/tc-tic54x.c:4909
+#: config/tc-tic54x.c:4876
 msgid "Unrecognized substitution symbol function"
 msgstr "Bilinmeyen ikame sembol iÅŸlevi"
 
-#: config/tc-tic54x.c:4914
+#: config/tc-tic54x.c:4881
 msgid "Missing '(' after substitution symbol function"
 msgstr "Ä°kame sembol iÅŸlevinden sonra eksik '('"
 
-#: config/tc-tic54x.c:4928
+#: config/tc-tic54x.c:4895
 msgid "Expecting second argument"
 msgstr "İkinci argüman bekleniyor"
 
-#: config/tc-tic54x.c:4941 config/tc-tic54x.c:4991
+#: config/tc-tic54x.c:4908 config/tc-tic54x.c:4958
 msgid "Extra junk in function call, expecting ')'"
 msgstr "İşlev çağrısında bozukluk, ')' beklendi"
 
-#: config/tc-tic54x.c:4967
+#: config/tc-tic54x.c:4934
 msgid "Function expects two arguments"
 msgstr "İşlev iki argüman gerektiriyor"
 
-#: config/tc-tic54x.c:4980
+#: config/tc-tic54x.c:4947
 msgid "Expecting character constant argument"
 msgstr "Karakter sabiti argüman beklendi"
 
-#: config/tc-tic54x.c:4986
+#: config/tc-tic54x.c:4953
 msgid "Both arguments must be substitution symbols"
 msgstr "Her iki argüman da ikame sembolü olmalı"
 
-#: config/tc-tic54x.c:5039
+#: config/tc-tic54x.c:5006
 #, c-format
 msgid "Invalid subscript (use 1 to %d)"
 msgstr "Geçersiz altsimge (1'den %d'e kadar kullanın)"
 
-#: config/tc-tic54x.c:5049
+#: config/tc-tic54x.c:5016
 #, c-format
 msgid "Invalid length (use 0 to %d"
 msgstr "Geçersiz uzunluk (0'dan %d'e kadar kullanın)"
 
-#: config/tc-tic54x.c:5059
+#: config/tc-tic54x.c:5026
 msgid "Missing ')' in subscripted substitution symbol expression"
 msgstr "Altsimgeli ikame sembol ifadesinde eksik ')'"
 
-#: config/tc-tic54x.c:5079
+#: config/tc-tic54x.c:5046
 msgid "Missing forced substitution terminator ':'"
 msgstr "Zorlanmış ikame sonlayıcısı ':' eksik"
 
-#: config/tc-tic54x.c:5252
+#: config/tc-tic54x.c:5201
 #, c-format
 msgid "Instruction does not fit in available delay slots (%d-word insn, %d slots left)"
 msgstr "İşlem mevcut gecikme yuvalarına sığmıyor (%d word işlem, %d yuva kaldı)"
 
-#: config/tc-tic54x.c:5293
+#: config/tc-tic54x.c:5242
 #, c-format
 msgid "Unrecognized parallel instruction '%s'"
 msgstr "Bilinmeyen paralel iÅŸlem '%s'"
 
-#: config/tc-tic54x.c:5305
+#: config/tc-tic54x.c:5254
 #, c-format
 msgid "Instruction '%s' requires an LP cpu version"
 msgstr "'%s' işlemi LP işlemci sürümü gerektiriyor"
 
-#: config/tc-tic54x.c:5312
+#: config/tc-tic54x.c:5261
 #, c-format
 msgid "Instruction '%s' requires far mode addressing"
 msgstr "'%s' iÅŸlemi uzak kip adreslemesi gerektiriyor"
 
-#: config/tc-tic54x.c:5324
+#: config/tc-tic54x.c:5273
 #, c-format
 msgid "Instruction does not fit in available delay slots (%d-word insn, %d slots left). Resulting behavior is undefined."
 msgstr "İşlem mevcut gecikme yuvalarına sığmıyor (%d word işlem, %d yuva kalmış). Oluşacak durum tanımlı değil."
 
-#: config/tc-tic54x.c:5334
+#: config/tc-tic54x.c:5283
 msgid "Instructions which cause PC discontinuity are not allowed in a delay slot. Resulting behavior is undefined."
 msgstr "PC kesintisi oluşturan işlemler gecikme yuvasında olamaz. Oluşacak durum tanımlı değil."
 
-#: config/tc-tic54x.c:5345
+#: config/tc-tic54x.c:5294
 #, c-format
 msgid "'%s' is not repeatable. Resulting behavior is undefined."
 msgstr "'%s' tekrarlanabilir değil. Oluşacak durum tanımlı değil."
 
-#: config/tc-tic54x.c:5349
+#: config/tc-tic54x.c:5298
 msgid "Instructions using long offset modifiers or absolute addresses are not repeatable. Resulting behavior is undefined."
 msgstr "Uzun görece değiştiricileri veya kesin adresler kullanan işlemler tekrarlanabilir değil. Oluşacak durum tanımlı değil."
 
-#: config/tc-tic54x.c:5545
+#: config/tc-tic54x.c:5478
 #, c-format
 msgid "Unsupported relocation size %d"
 msgstr "Desteklenmeyen yerdeÄŸiÅŸim boyu %d"
 
-#: config/tc-tic54x.c:5699
+#: config/tc-tic54x.c:5632
 msgid "non-absolute value used with .space/.bes"
 msgstr ".space/.bes ile kesin olmayan değer kullanılmış"
 
-#: config/tc-tic54x.c:5703
+#: config/tc-tic54x.c:5636
 #, c-format
 msgid "negative value ignored in %s"
 msgstr "%s'deki negatif değer yoksayıldı"
 
-#: config/tc-tic54x.c:5792
+#: config/tc-tic54x.c:5725
 #, c-format
 msgid "attempt to .space/.bes backwards? (%ld)"
 msgstr ".space/.bes geri mi yapılmaya çalışılmış? (%ld)"
 
-#: config/tc-tic54x.c:5826
+#: config/tc-tic54x.c:5759
 #, c-format
 msgid "Invalid label '%s'"
 msgstr "Geçersiz etiket '%s'"
 
-#: config/tc-tic80.c:26
+#: config/tc-tic80.c:27
 #, c-format
 msgid "internal error:%s:%d: %s\n"
 msgstr "iç hata:%s:%d: %s\n"
 
-#: config/tc-tic80.c:29
+#: config/tc-tic80.c:30
 #, c-format
 msgid "internal error:%s:%d: %s %ld\n"
 msgstr "iç hata:%s:%d: %s %ld\n"
 
-#: config/tc-tic80.c:89
+#: config/tc-tic80.c:90
 msgid "Relaxation is a luxury we can't afford"
 msgstr "Gevşetme bizim için fazla lüks"
 
-#: config/tc-tic80.c:138
+#: config/tc-tic80.c:139
 msgid "bad call to md_atof ()"
 msgstr "md_atof()'a hatalı çağrı"
 
-#: config/tc-tic80.c:235
+#: config/tc-tic80.c:236
 msgid "':' not followed by 'm' or 's'"
 msgstr "':' 'm' veya 's' ile izlenmiyor"
 
-#: config/tc-tic80.c:248
+#: config/tc-tic80.c:249
 msgid "paren nesting"
 msgstr "içiçe parantez"
 
-#: config/tc-tic80.c:262
+#: config/tc-tic80.c:263
 msgid "mismatched parenthesis"
 msgstr "eÅŸleÅŸmeyen parantez"
 
-#: config/tc-tic80.c:464
+#: config/tc-tic80.c:461
 msgid "unhandled expression type"
 msgstr "desteklenmeyen ifade türü"
 
-#: config/tc-tic80.c:678
+#: config/tc-tic80.c:592
 msgid "symbol reloc that is not PC relative or 32 bits"
 msgstr "PC göreli veya 32 bit olmayan sembol yerdeğişimi"
 
-#: config/tc-tic80.c:707
+#: config/tc-tic80.c:621
 msgid "unhandled operand modifier"
 msgstr "desteklenmeyen iÅŸlenen deÄŸiÅŸtiricisi"
 
-#: config/tc-tic80.c:749
+#: config/tc-tic80.c:663
 msgid "unhandled expression"
 msgstr "desteklenmeyen ifade"
 
-#: config/tc-tic80.c:797
+#: config/tc-tic80.c:711
 #, c-format
 msgid "Invalid mnemonic: '%s'"
 msgstr "Geçersiz ipucu: '%s'"
 
-#: config/tc-tic80.c:810
+#: config/tc-tic80.c:724
 #, c-format
 msgid "Invalid operands: '%s'"
 msgstr "Geçersiz işlenenler: '%s'"
 
-#: config/tc-tic80.c:888
+#: config/tc-tic80.c:802
 msgid "unhandled predefined symbol bits"
 msgstr "desteklenmeyen önceden tanımlı sembol bitleri"
 
-#: config/tc-tic80.c:983
+#: config/tc-tic80.c:897
 #, c-format
 msgid "PC offset 0x%lx outside range 0x%lx-0x%lx"
 msgstr "PC görecesi 0x%lx, 0x%lx-0x%lx aralığının dışında"
 
-#: config/tc-tic80.c:998
+#: config/tc-tic80.c:912
 msgid "unhandled relocation type in fixup"
 msgstr "düzeltmede desteklenmeyen yerdeğişim türü"
 
-#: config/tc-tic80.c:1037
+#: config/tc-tic80.c:951
 msgid "md_convert_frag() not implemented yet"
 msgstr "md_convert_frag() henüz desteklenmiyor"
 
@@ -9768,335 +10693,353 @@ msgstr "md_convert_frag() henüz desteklenmiyor"
 msgid ".COMMon length (%d.) < 0! Ignored."
 msgstr ".COMM ortak uzunluğu (%d.) < 0! Yoksayıldı"
 
+#: config/tc-v850.c:266
+#, c-format
+msgid "Length of .comm \"%s\" is already %ld. Not changed to %d."
+msgstr ".comm \"%s\" uzunluÄŸu zaten %ld. %d olarak deÄŸiÅŸtirilmedi."
+
 #: config/tc-v850.c:293
 msgid "Common alignment negative; 0 assumed"
 msgstr "Ortak hizalama negatif; 0 varsayıldı"
 
-#: config/tc-v850.c:974
+#: config/tc-v850.c:976
 #, c-format
 msgid "unknown operand shift: %x\n"
 msgstr "bilinmeyen terim kaydırması: %x\n"
 
-#: config/tc-v850.c:975
+#: config/tc-v850.c:977
 msgid "internal failure in parse_register_list"
 msgstr "parse_register_list'te iç hata"
 
-#: config/tc-v850.c:991
+#: config/tc-v850.c:993
 msgid "constant expression or register list expected"
 msgstr "sabit ifade veya yazmaç listesi beklendi"
 
-#: config/tc-v850.c:996 config/tc-v850.c:1009 config/tc-v850.c:1028
+#: config/tc-v850.c:998 config/tc-v850.c:1011 config/tc-v850.c:1030
 msgid "high bits set in register list expression"
 msgstr "yazmaç liste ifadesinde yüksek bitler atanmış"
 
-#: config/tc-v850.c:1067 config/tc-v850.c:1130
+#: config/tc-v850.c:1069 config/tc-v850.c:1132
 msgid "illegal register included in list"
 msgstr "listede geçersiz yazmaç var"
 
-#: config/tc-v850.c:1073
+#: config/tc-v850.c:1075
 msgid "system registers cannot be included in list"
 msgstr "sistem yazmaçları listeye dahil edilemez"
 
-#: config/tc-v850.c:1078
+#: config/tc-v850.c:1080
 msgid "PSW cannot be included in list"
 msgstr "PSW listeye dahil edilemez"
 
-#: config/tc-v850.c:1085
+#: config/tc-v850.c:1087
 msgid "High value system registers cannot be included in list"
 msgstr "Yüksek değerli sistem yazmaçları listeye dahil edilemez"
 
-#: config/tc-v850.c:1109
+#: config/tc-v850.c:1111
 msgid "second register should follow dash in register list"
 msgstr "ikinci yazmaç yazmaç listesinde tireyi takip etmeli"
 
-#: config/tc-v850.c:1154
+#: config/tc-v850.c:1156
+#, c-format
 msgid " V850 options:\n"
 msgstr " V850 seçenekleri:\n"
 
-#: config/tc-v850.c:1155
+#: config/tc-v850.c:1157
+#, c-format
 msgid "  -mwarn-signed-overflow    Warn if signed immediate values overflow\n"
 msgstr "  -mwarn-signed-overflow    Eğer signed şimdiki değerler taşarsa uyarır\n"
 
-#: config/tc-v850.c:1156
+#: config/tc-v850.c:1158
+#, c-format
 msgid "  -mwarn-unsigned-overflow  Warn if unsigned immediate values overflow\n"
 msgstr "  -mwarn-unsigned-overflow  Eğer unsigned şimdiki değerler taşarsa uyarır\n"
 
-#: config/tc-v850.c:1157
+#: config/tc-v850.c:1159
+#, c-format
 msgid "  -mv850                    The code is targeted at the v850\n"
 msgstr "  -mv850                    v850 için kod üretilir\n"
 
-#: config/tc-v850.c:1158
+#: config/tc-v850.c:1160
+#, c-format
 msgid "  -mv850e                   The code is targeted at the v850e\n"
 msgstr "  -mv850e                   v850e için kod üretilir\n"
 
-#: config/tc-v850.c:1159
+#: config/tc-v850.c:1161
+#, fuzzy, c-format
+msgid "  -mv850e1                  The code is targeted at the v850e1\n"
+msgstr "  -mv850e                   v850e için kod üretilir\n"
+
+#: config/tc-v850.c:1162
+#, c-format
 msgid "  -mv850any                 The code is generic, despite any processor specific instructions\n"
 msgstr "  -mv850any                 İşlemciye özgü işlemlere rağmen kod genel amaçlı\n"
 
-#: config/tc-v850.c:1160
+#: config/tc-v850.c:1163
+#, c-format
 msgid "  -mrelax                   Enable relaxation\n"
 msgstr "  -mrelax                 bağlayıcı tarafından gevşetilebilen kod üretir\n"
 
-#: config/tc-v850.c:1173 config/tc-v850.c:1208
-#, c-format
-msgid "unknown command line option: -%c%s\n"
-msgstr "bilinmeyen komut satırı seçeneği: -%c%s\n"
-
-#: config/tc-v850.c:1349
+#: config/tc-v850.c:1354
 #, c-format
 msgid "Unable to determine default target processor from string: %s"
 msgstr "Öntanımlı hedef işlemci dizgeden belirlenemedi: %s"
 
-#: config/tc-v850.c:1386
+#: config/tc-v850.c:1389
+#, fuzzy
+msgid "lo() relocation used on an instruction which does not support it"
+msgstr "ctoff() yerdeğişimi, bunu desteklemeyen bir işlem için kullanıldı"
+
+#: config/tc-v850.c:1410
 msgid "ctoff() relocation used on an instruction which does not support it"
 msgstr "ctoff() yerdeğişimi, bunu desteklemeyen bir işlem için kullanıldı"
 
-#: config/tc-v850.c:1412
+#: config/tc-v850.c:1436
 msgid "sdaoff() relocation used on an instruction which does not support it"
 msgstr "sdaoff() yerdeğişimi, bunu desteklemeyen bir işlem için kullanıldı"
 
-#: config/tc-v850.c:1438
+#: config/tc-v850.c:1462
 msgid "zdaoff() relocation used on an instruction which does not support it"
 msgstr "zdaoff() yerdeğişimi, bunu desteklemeyen bir işlem için kullanıldı"
 
-#: config/tc-v850.c:1475
+#: config/tc-v850.c:1499
 msgid "tdaoff() relocation used on an instruction which does not support it"
 msgstr "tdaoff() yerdeğişimi, bunu desteklemeyen bir işlem için kullanıldı"
 
-#: config/tc-v850.c:1699
+#: config/tc-v850.c:1714
 msgid "Target processor does not support this instruction."
 msgstr "Hedef iÅŸlemci bu iÅŸlemi desteklemiyor."
 
-#: config/tc-v850.c:1789 config/tc-v850.c:1818 config/tc-v850.c:2006
+#: config/tc-v850.c:1805 config/tc-v850.c:1834 config/tc-v850.c:2022
 msgid "immediate operand is too large"
 msgstr "şimdiki işlenen fazla büyük"
 
-#: config/tc-v850.c:1800
+#: config/tc-v850.c:1816
 msgid "AAARG -> unhandled constant reloc"
 msgstr "AAARG -> desteklenmeyen sabit yerdeÄŸiÅŸimi"
 
-#: config/tc-v850.c:1844
+#: config/tc-v850.c:1860
 msgid "invalid register name"
 msgstr "geçersiz yazmaç ismi"
 
-#: config/tc-v850.c:1849
+#: config/tc-v850.c:1865
 msgid "register r0 cannot be used here"
 msgstr "r0 yazmacı burada kullanılamaz"
 
-#: config/tc-v850.c:1861
+#: config/tc-v850.c:1877
 msgid "invalid system register name"
 msgstr "geçersiz sistem yazmaç ismi"
 
-#: config/tc-v850.c:1874
+#: config/tc-v850.c:1890
 msgid "expected EP register"
 msgstr "EP yazmacı beklendi"
 
-#: config/tc-v850.c:1891
+#: config/tc-v850.c:1907
 msgid "invalid condition code name"
 msgstr "geçersiz koşul kodu ismi"
 
-#: config/tc-v850.c:1912 config/tc-v850.c:1916
+#: config/tc-v850.c:1928 config/tc-v850.c:1932
 msgid "constant too big to fit into instruction"
 msgstr "sabit işleme sığmak için fazla büyük"
 
-#: config/tc-v850.c:1969
+#: config/tc-v850.c:1985
 msgid "syntax error: value is missing before the register name"
 msgstr "sözdizim hatası: yazmaç adından önce değer eksik"
 
-#: config/tc-v850.c:1971
+#: config/tc-v850.c:1987
 msgid "syntax error: register not expected"
 msgstr "sözdizim hatası: beklenmeyen yerde yazmaç bulundu"
 
-#: config/tc-v850.c:1985
+#: config/tc-v850.c:2001
 msgid "syntax error: system register not expected"
 msgstr "sözdizim hatası: beklenmeyen yerde sistem yazmacı bulundu"
 
-#: config/tc-v850.c:1990
+#: config/tc-v850.c:2006
 msgid "syntax error: condition code not expected"
 msgstr "sözdizim hatası: beklenmeyen yerde koşul kodu bulundu"
 
-#: config/tc-v850.c:2031
+#: config/tc-v850.c:2040
 msgid "invalid operand"
 msgstr "geçersiz işlenen"
 
-#: config/tc-vax.c:285
+#: config/tc-vax.c:290
 #, c-format
 msgid "VIP_BEGIN error:%s"
 msgstr "VIP_BEGIN hatası:%s"
 
-#: config/tc-vax.c:422
+#: config/tc-vax.c:427
 #, c-format
 msgid "Aborting because statement has \"%s\""
 msgstr "İşlem durduruluyor çünkü deyimde \"%s\" var"
 
-#: config/tc-vax.c:469
+#: config/tc-vax.c:474
 msgid "Can't relocate expression"
 msgstr "Ä°fade yerdeÄŸiÅŸtirtilemez"
 
-#: config/tc-vax.c:572
+#: config/tc-vax.c:577
 msgid "Bignum not permitted in short literal. Immediate mode assumed."
 msgstr "Büyüksayı (bignum) short sabitte kullanılamaz. Şimdiki kip varsayıldı."
 
-#: config/tc-vax.c:581
+#: config/tc-vax.c:586
 msgid "Can't do flonum short literal: immediate mode used."
 msgstr "Kayan noktalı short sabit kullanılamaz: şimdiki kip kullanıldı."
 
-#: config/tc-vax.c:626
+#: config/tc-vax.c:631
 #, c-format
 msgid "A bignum/flonum may not be a displacement: 0x%lx used"
 msgstr "Büyüksayı/kayan noktalı yerdeğişim olamaz: 0x%lx kullanıldı"
 
-#: config/tc-vax.c:961
+#: config/tc-vax.c:967
 #, c-format
 msgid "Short literal overflow(%ld.), immediate mode assumed."
 msgstr "Short sabit taşması (%ld), şimdiki kip varsayıldı."
 
-#: config/tc-vax.c:970
+#: config/tc-vax.c:976
 #, c-format
 msgid "Forced short literal to immediate mode. now_seg=%s to_seg=%s"
 msgstr "Short sabit şimdiki kipe zorlandı. now_seg=%s to_seg=%s"
 
-#: config/tc-vax.c:1035
+#: config/tc-vax.c:1041
 msgid "Length specification ignored. Address mode 9F used"
 msgstr "Uzunluk tanımı yoksayıldı. 9F adresleme kipi kullanıldı"
 
-#: config/tc-vax.c:1096
+#: config/tc-vax.c:1102
 msgid "Invalid operand:  immediate value used as base address."
 msgstr "Geçersiz işlenen: şimdiki değer temel adres olarak kullanıldı."
 
-#: config/tc-vax.c:1098
+#: config/tc-vax.c:1104
 msgid "Invalid operand:  immediate value used as address."
 msgstr "Geçersiz işlenen: şimdiki değer adres olarak kullanıldı."
 
-#: config/tc-vax.c:1123
+#: config/tc-vax.c:1129
 msgid "Symbol used as immediate operand in PIC mode."
 msgstr "Sembol PIC kipinde şimdiki işlenen olarak kullanıldı"
 
-#: config/tc-vax.c:1941
+#: config/tc-vax.c:1947
 msgid "odd number of bytes in operand description"
 msgstr "işlenen tanımında tek sayılı bayt."
 
-#: config/tc-vax.c:1957
+#: config/tc-vax.c:1963
 msgid "Bad operand"
 msgstr "Hatalı işlenen"
 
-#: config/tc-vax.c:2532
+#: config/tc-vax.c:2538
 msgid "no '[' to match ']'"
 msgstr "']' ile eÅŸleÅŸen '[' yok"
 
-#: config/tc-vax.c:2552
+#: config/tc-vax.c:2558
 msgid "bad register in []"
 msgstr "[]'da hatalı yazmaç"
 
-#: config/tc-vax.c:2554
+#: config/tc-vax.c:2560
 msgid "[PC] index banned"
 msgstr "[PC] indeksi yasaklandı"
 
-#: config/tc-vax.c:2589
+#: config/tc-vax.c:2595
 msgid "no '(' to match ')'"
 msgstr "')' ile eÅŸleÅŸen '(' yok"
 
-#: config/tc-vax.c:2729
+#: config/tc-vax.c:2735
 msgid "invalid branch operand"
 msgstr "geçersiz dal işleneni"
 
-#: config/tc-vax.c:2758
+#: config/tc-vax.c:2764
 msgid "address prohibits @"
 msgstr "adres @'i yasaklıyor"
 
-#: config/tc-vax.c:2760
+#: config/tc-vax.c:2766
 msgid "address prohibits #"
 msgstr "adres #'i yasaklıyor"
 
-#: config/tc-vax.c:2764
+#: config/tc-vax.c:2770
 msgid "address prohibits -()"
 msgstr "adres -()'i yasaklıyor"
 
-#: config/tc-vax.c:2766
+#: config/tc-vax.c:2772
 msgid "address prohibits ()+"
 msgstr "adres ()+'i yasaklıyor"
 
-#: config/tc-vax.c:2769
+#: config/tc-vax.c:2775
 msgid "address prohibits ()"
 msgstr "adres ()'i yasaklıyor"
 
-#: config/tc-vax.c:2771
+#: config/tc-vax.c:2777
 msgid "address prohibits []"
 msgstr "adres []'i yasaklıyor"
 
-#: config/tc-vax.c:2773
+#: config/tc-vax.c:2779
 msgid "address prohibits register"
 msgstr "adres yazmacı yasaklıyor"
 
-#: config/tc-vax.c:2775
+#: config/tc-vax.c:2781
 msgid "address prohibits displacement length specifier"
 msgstr "adres yerdeğişim uzunluk belirleyicisini yasaklıyor"
 
-#: config/tc-vax.c:2805
+#: config/tc-vax.c:2811
 msgid "invalid operand of S^#"
 msgstr "S^# için geçersiz işlenen"
 
-#: config/tc-vax.c:2822
+#: config/tc-vax.c:2828
 msgid "S^# needs expression"
 msgstr "S^# için ifade gerekli"
 
-#: config/tc-vax.c:2829
+#: config/tc-vax.c:2835
 msgid "S^# may only read-access"
 msgstr "S^# yalnız salt okunur erişime izin verir"
 
-#: config/tc-vax.c:2854
+#: config/tc-vax.c:2860
 msgid "invalid operand of -()"
 msgstr "-() için geçersiz işlenen"
 
-#: config/tc-vax.c:2860
+#: config/tc-vax.c:2866
 msgid "-(PC) unpredictable"
 msgstr "-(PC)'nin sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:2862
+#: config/tc-vax.c:2868
 msgid "[]index same as -()register: unpredictable"
 msgstr "[]indeks, -()yazmaç ile aynı: sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:2898
+#: config/tc-vax.c:2904
 msgid "invalid operand of ()+"
 msgstr "()+ için geçersiz işlenen"
 
-#: config/tc-vax.c:2904
+#: config/tc-vax.c:2910
 msgid "(PC)+ unpredictable"
 msgstr "(PC)+'nin sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:2906
+#: config/tc-vax.c:2912
 msgid "[]index same as ()+register: unpredictable"
 msgstr "[]indeks, ()+yazmaç ile aynı: sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:2931
+#: config/tc-vax.c:2937
 msgid "# conflicts length"
 msgstr "#, uzunluk ile çakışıyor"
 
-#: config/tc-vax.c:2933
+#: config/tc-vax.c:2939
 msgid "# bars register"
 msgstr "#, yazmacı yasaklıyor"
 
-#: config/tc-vax.c:2955
+#: config/tc-vax.c:2961
 msgid "writing or modifying # is unpredictable"
 msgstr "#'i yazmak veya değiştirmenin sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:2985
+#: config/tc-vax.c:2991
 msgid "length not needed"
 msgstr "uzunluk gerekli deÄŸil"
 
-#: config/tc-vax.c:2992
+#: config/tc-vax.c:2998
 msgid "can't []index a register, because it has no address"
 msgstr "bir yazmaca []indeks uygulanamaz, çünkü adresi yoktur"
 
-#: config/tc-vax.c:2994
+#: config/tc-vax.c:3000
 msgid "a register has no address"
 msgstr "bir yazmacın adresi yoktur"
 
-#: config/tc-vax.c:3005
+#: config/tc-vax.c:3011
 msgid "PC part of operand unpredictable"
 msgstr "İşlenenin PC bölümünün sonuçları tahmin edilemez"
 
-#: config/tc-vax.c:3345
+#: config/tc-vax.c:3360
+#, c-format
 msgid ""
 "VAX options:\n"
 "-d LENGTH\t\tignored\n"
@@ -10114,7 +11057,8 @@ msgstr ""
 "-T\t\t\tyoksayıldı\n"
 "-V\t\t\tyoksayıldı\n"
 
-#: config/tc-vax.c:3354
+#: config/tc-vax.c:3369
+#, c-format
 msgid ""
 "VMS options:\n"
 "-+\t\t\thash encode names longer than 31 characters\n"
@@ -10134,533 +11078,762 @@ msgstr ""
 "-v\"SÜRÜM\"\t\tçevrimi yapılan kod, \"SÜRÜM\" sürümündeki\n"
 "\t\t\tderleyici ile üretilir\n"
 
-#: config/tc-w65.c:145
+#: config/tc-w65.c:142
 msgid "need on or off."
 msgstr "açık veya kapalı."
 
-#: config/tc-w65.c:281 config/tc-w65.c:324
+#: config/tc-w65.c:278 config/tc-w65.c:321
 msgid "syntax error after <exp"
 msgstr "<exp sonrasında sözdizim hatası"
 
 #: config/tc-xstormy16.c:80
+#, c-format
 msgid " XSTORMY16 specific command line options:\n"
 msgstr " XSTORMY16'ya özgü komut satırı seçenekleri:\n"
 
-#: config/tc-xstormy16.c:562
+#: config/tc-xstormy16.c:580
 #, c-format
 msgid "internal error: can't install fix for reloc type %d (`%s')"
 msgstr "iç hata: %d yerdeğişim türünün düzeltmesi kurulamadı (`%s')"
 
-#: config/tc-xtensa.c:929
-msgid "'--density' option not supported in this Xtensa configuration"
-msgstr "'--density' seçeneği bu Xtensa ayarlarında desteklenmiyor"
+#: config/tc-xtensa.c:588
+msgid "illegal range of target hardware versions"
+msgstr ""
 
-#: config/tc-xtensa.c:1030
-msgid "'--literal-section-name' is deprecated; use '--rename-section .literal=NEWNAME'"
-msgstr "'--literal-section-name' eski; '--rename-section .literal=YENİAD' kullanın"
+#: config/tc-xtensa.c:736
+#, fuzzy
+msgid "--density option is ignored"
+msgstr "Xtensa yoğunluk seçeneği desteklenmiyor; yoksayıldı"
 
-#: config/tc-xtensa.c:1036
-msgid "'--text-section-name' is deprecated; use '--rename-section .text=NEWNAME'"
-msgstr "'--text-section-name' eski; '--rename-section .text=YENİİSİM' kullanın"
+#: config/tc-xtensa.c:739
+#, fuzzy
+msgid "--no-density option is ignored"
+msgstr "Xtensa yoğunluk seçeneği desteklenmiyor; yoksayıldı"
 
-#: config/tc-xtensa.c:1042
-msgid "'--data-section-name' is deprecated; use '--rename-section .data=NEWNAME'"
-msgstr "'--data-section-name' eski; '--rename-section .data=YENİİSİM' kullanın"
+#: config/tc-xtensa.c:748
+msgid "--generics is deprecated; use --transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:751
+msgid "--no-generics is deprecated; use --no-transform instead"
+msgstr ""
 
-#: config/tc-xtensa.c:1048
-msgid "'--bss-section-name' is deprecated; use '--rename-section .bss=NEWNAME'"
-msgstr "'--bss-section-name' eski; '--rename-section .bss=YENİİSİM' kullanın"
+#: config/tc-xtensa.c:754
+msgid "--relax is deprecated; use --transform instead"
+msgstr ""
 
-#: config/tc-xtensa.c:1186
+#: config/tc-xtensa.c:757
+msgid "--no-relax is deprecated; use --no-transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:774
+#, fuzzy
+msgid "--absolute-literals option not supported in this Xtensa configuration"
+msgstr "'--density' seçeneği bu Xtensa ayarlarında desteklenmiyor"
+
+#: config/tc-xtensa.c:847
+msgid "prefer-l32r conflicts with prefer-const16"
+msgstr ""
+
+#: config/tc-xtensa.c:853
+msgid "prefer-const16 conflicts with prefer-l32r"
+msgstr ""
+
+#: config/tc-xtensa.c:861 config/tc-xtensa.c:870 config/tc-xtensa.c:874
+#, fuzzy
+msgid "invalid target hardware version"
+msgstr "geçersiz mimari eklenti"
+
+#: config/tc-xtensa.c:1086
 msgid "unmatched end directive"
 msgstr "eşleşmeyen end yönergesi"
 
-#: config/tc-xtensa.c:1215
+#: config/tc-xtensa.c:1115
 msgid ".begin directive with no matching .end directive"
 msgstr "eşleşen .end yönergesi olmaksızın .begin yönergesi"
 
-#: config/tc-xtensa.c:1259
-#, c-format
-msgid "directive %s can't be negated"
+#: config/tc-xtensa.c:1156
+msgid "[no-]generics is deprecated; use [no-]transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:1161
+msgid "[no-]relax is deprecated; use [no-]transform instead"
+msgstr ""
+
+#: config/tc-xtensa.c:1174
+#, fuzzy, c-format
+msgid "directive %s cannot be negated"
 msgstr "`%s' yönergesi olumsuzlanamaz"
 
-#: config/tc-xtensa.c:1265
+#: config/tc-xtensa.c:1180
 msgid "unknown directive"
 msgstr "bilinmeyen yönerge"
 
-#: config/tc-xtensa.c:1300
+#: config/tc-xtensa.c:1202 config/tc-xtensa.c:1308 config/tc-xtensa.c:1604
+#: config/tc-xtensa.c:5552
+#, fuzzy
+msgid "directives are not valid inside bundles"
+msgstr "İşlem balya (bundle) içinde geçersiz"
+
+#: config/tc-xtensa.c:1214
+#, fuzzy
+msgid ".begin literal is deprecated; use .literal instead"
+msgstr ".def/.ref kullanımı artık geçersiz. Yerine .global kullanın"
+
+#: config/tc-xtensa.c:1228
 msgid "cannot set literal_prefix inside literal fragment"
 msgstr "literal parça içerisinde literal_prefix atanamaz"
 
-#: config/tc-xtensa.c:1337 config/tc-xtensa.c:1371
-msgid "Xtensa density option not supported; ignored"
+#: config/tc-xtensa.c:1271
+msgid ".begin [no-]density is ignored"
+msgstr ""
+
+#: config/tc-xtensa.c:1278 config/tc-xtensa.c:1328
+#, fuzzy
+msgid "Xtensa absolute literals option not supported; ignored"
 msgstr "Xtensa yoğunluk seçeneği desteklenmiyor; yoksayıldı"
 
-#: config/tc-xtensa.c:1383
+#: config/tc-xtensa.c:1321
+msgid ".end [no-]density is ignored"
+msgstr ""
+
+#: config/tc-xtensa.c:1346
 #, c-format
 msgid "does not match begin %s%s at %s:%d"
 msgstr "%3$s:%4$d adresinde begin %1$s%2$s ile eÅŸleÅŸmiyor"
 
-#: config/tc-xtensa.c:1429
+#: config/tc-xtensa.c:1424
 msgid ".literal_position inside literal directive; ignoring"
 msgstr "literal yönerge içinde .literal_position; yoksayıldı"
 
+#: config/tc-xtensa.c:1444
+#, fuzzy
+msgid ".literal not allowed inside .begin literal region"
+msgstr "literal yönerge içinde .literal_position; yoksayıldı"
+
 #: config/tc-xtensa.c:1480
 msgid "expected comma or colon after symbol name; rest of line ignored"
 msgstr "sembol adından sonra virgül veya noktalıvirgül beklendi; satırın gerisi yoksayıldı"
 
-#: config/tc-xtensa.c:1655 config/tc-xtensa.c:1672
+#: config/tc-xtensa.c:1573
+msgid "fall through frequency must be greater than 0"
+msgstr ""
+
+#: config/tc-xtensa.c:1581
+msgid "branch target frequency must be greater than 0"
+msgstr ""
+
+#: config/tc-xtensa.c:1629
+#, fuzzy, c-format
+msgid "opcode-specific %s relocation used outside an instruction"
+msgstr "%2$s işlemi için %1$d türü yerdeğişim geçersiz"
+
+#: config/tc-xtensa.c:1782 config/tc-xtensa.c:1799
 #, c-format
 msgid "bad register name: %s"
 msgstr "hatalı yazmaç ismi: %s"
 
-#: config/tc-xtensa.c:1661
+#: config/tc-xtensa.c:1788
 #, c-format
 msgid "bad register number: %s"
 msgstr "hatalı yazmaç numarası: %s"
 
-#: config/tc-xtensa.c:1724
+#: config/tc-xtensa.c:1867
 msgid "register number out of range"
 msgstr "yazmaç numarası kapsam dışı"
 
-#: config/tc-xtensa.c:1836
+#: config/tc-xtensa.c:1951
+msgid "extra comma"
+msgstr ""
+
+#: config/tc-xtensa.c:1953
+msgid "extra colon"
+msgstr ""
+
+#: config/tc-xtensa.c:1955
+#, fuzzy
+msgid "missing argument"
+msgstr "hizalama eksik"
+
+#: config/tc-xtensa.c:1957
+#, fuzzy
+msgid "missing comma or colon"
+msgstr "`to' veya `downto' eksik"
+
+#: config/tc-xtensa.c:2014
+#, fuzzy
+msgid "incorrect register number, ignoring"
+msgstr "yazmaç listesinde hatalı yazmaç"
+
+#: config/tc-xtensa.c:2021
 msgid "too many arguments"
 msgstr "çok fazla argüman"
 
-#: config/tc-xtensa.c:1922
+#: config/tc-xtensa.c:2094
+#, fuzzy, c-format
+msgid "cannot encode opcode \"%s\""
+msgstr "bilinmeyen opkod \"%s\""
+
+#: config/tc-xtensa.c:2188
 #, c-format
 msgid "not enough operands (%d) for '%s'; expected %d"
 msgstr "'%2$s' için yeterli işlenen (%1$d) yok; %3$d beklendi"
 
-#: config/tc-xtensa.c:1929
+#: config/tc-xtensa.c:2195
 #, c-format
 msgid "too many operands (%d) for '%s'; expected %d"
 msgstr "'%2$s' için çok fazla işlenen (%1$d) var; %3$d beklendi"
 
-#: config/tc-xtensa.c:1973
-#, c-format
-msgid "register number for `%s' is not a constant"
-msgstr "`%s' için yazmaç sayısı sabit değil"
+#: config/tc-xtensa.c:2250
+#, fuzzy, c-format
+msgid "invalid register '%s' for '%s' instruction"
+msgstr "emme/basma işlemi için geçersiz yazmaç listesi"
 
-#: config/tc-xtensa.c:1978
-#, c-format
-msgid "register number (%ld) for `%s' is out of range"
+#: config/tc-xtensa.c:2257
+#, fuzzy, c-format
+msgid "invalid register number (%ld) for '%s' instruction"
 msgstr "`%2$s' için yazmaç numarası (%1$ld) kapsam dışı"
 
-#: config/tc-xtensa.c:2464
-#, c-format
-msgid "operand %d not properly aligned for '%s'"
-msgstr "'%2$s' için %1$d işleneni doğru hizalanmamış"
-
-#: config/tc-xtensa.c:2469
-#, c-format
-msgid "operand %d not in immediate table for '%s'"
-msgstr "'%2$s' için %1$d işleneni şimdiki tablosunda değil"
+#: config/tc-xtensa.c:2326
+#, fuzzy, c-format
+msgid "invalid register number (%ld) for '%s'"
+msgstr "geçersiz yazmaç numarası (%d)"
 
-#: config/tc-xtensa.c:2474
-#, c-format
-msgid "operand %d too large for '%s'"
+#: config/tc-xtensa.c:2716
+#, fuzzy, c-format
+msgid "operand %u is out of range for '%s'"
 msgstr "'%2$s' için %1$d işleneni fazla büyük"
 
-#: config/tc-xtensa.c:2479
-#, c-format
-msgid "operand %d too small for '%s'"
-msgstr "'%2$s' için %1$d işleneni çok küçük"
-
-#: config/tc-xtensa.c:2484
-#, c-format
-msgid "operand %d is invalid for '%s'"
+#: config/tc-xtensa.c:2720
+#, fuzzy, c-format
+msgid "operand %u is invalid for '%s'"
 msgstr "'%2$s' için %1$d işleneni geçersiz"
 
-#: config/tc-xtensa.c:3716
+#: config/tc-xtensa.c:2766
+#, fuzzy, c-format
+msgid "internal error: unknown option name '%s'"
+msgstr "iç hata: bilinmeyen dwarf2 biçemi"
+
+#: config/tc-xtensa.c:3873
 msgid "INSTR_LABEL_DEF not supported yet"
 msgstr "INSTR_LABEL_DEF henüz desteklenmiyor"
 
-#: config/tc-xtensa.c:3745
+#: config/tc-xtensa.c:3902
 msgid "can't handle generation of literal/labels yet"
 msgstr "literal/etiketlerin üretimi henüz desteklenmiyor"
 
-#: config/tc-xtensa.c:3749
+#: config/tc-xtensa.c:3906
 msgid "can't handle undefined OP TYPE"
 msgstr "tanımlanmamış OP TYPE henüz desteklenmiyor"
 
-#: config/tc-xtensa.c:3810
+#: config/tc-xtensa.c:3966
 #, c-format
 msgid "found %d operands for '%s':  Expected %d"
 msgstr "'%2$s' için %1$d işlenen bulundu:  %3$d beklendi"
 
-#: config/tc-xtensa.c:3817
+#: config/tc-xtensa.c:3973
 #, c-format
 msgid "found too many (%d) operands for '%s':  Expected %d"
 msgstr "'%2$s' için çok fazla işlenen (%1$d) bulundu:  %3$d beklendi"
 
-#: config/tc-xtensa.c:4072
-msgid "instruction fragment may contain data"
-msgstr "İşlem parçacığı veri içerebilir"
-
-#: config/tc-xtensa.c:4105
-#, c-format
-msgid "invalid operand %d on '%s'"
-msgstr "'%2$s' için geçersiz %1$d işleneni"
+#: config/tc-xtensa.c:4234
+#, fuzzy, c-format
+msgid "invalid relocation for operand %i of '%s'"
+msgstr "'%2$s'nın %1$d işleneni için geçersiz yerdeğişim"
 
-#: config/tc-xtensa.c:4116
-#, c-format
-msgid "invalid expression for operand %d on '%s'"
+#: config/tc-xtensa.c:4244
+#, fuzzy, c-format
+msgid "invalid expression for operand %i of '%s'"
 msgstr "'%2$s' içinde %1$d işleneninde geçersiz ifade"
 
-#: config/tc-xtensa.c:4177
-#, c-format
-msgid "invalid relocation operand %i on '%s'"
-msgstr "'%2$s' içinde geçersiz yer değişim işleneni %1$i"
+#: config/tc-xtensa.c:4254
+#, fuzzy, c-format
+msgid "invalid relocation in instruction slot %i"
+msgstr "işlem için geçersiz yerdeğişim"
 
-#: config/tc-xtensa.c:4186
-#, c-format
-msgid "undefined symbol for opcode \"%s\"."
+#: config/tc-xtensa.c:4261
+#, fuzzy, c-format
+msgid "undefined symbol for opcode \"%s\""
 msgstr "\"%s\" opkodu için tanımsız sembol"
 
-#: config/tc-xtensa.c:4280
-msgid "instruction with constant operands does not fit"
-msgstr "sabit işlenenli işlem sığmıyor"
-
-#: config/tc-xtensa.c:4289
-msgid "instruction with constant operands does not fit without widening"
-msgstr "sabit işlenenli işlem, genişletme olmadan sığmıyor"
-
-#: config/tc-xtensa.c:4379
-msgid "instruction's constant operands do not fit"
-msgstr "işlemin sabit işlenenleri sığmıyor"
-
-#: config/tc-xtensa.c:4718
+#: config/tc-xtensa.c:4700
 msgid "opcode 'NOP.N' unavailable in this configuration"
 msgstr "'NOP.N' opkodu bu ayarlarda desteklenmemektedir"
 
-#: config/tc-xtensa.c:4727
-msgid "opcode 'OR' unavailable in this configuration"
-msgstr "'OR' opkodu bu ayarlarda desteklenmemektedir"
+#: config/tc-xtensa.c:4759
+msgid "get_expanded_loop_offset: invalid opcode"
+msgstr "get_expanded_loop_offset: geçersiz opkod"
+
+#: config/tc-xtensa.c:4840
+#, fuzzy, c-format
+msgid "assembly state not set for first frag in section %s"
+msgstr "%s bölümü için bölüm bayrakları atanamadı"
 
-#: config/tc-xtensa.c:4737
+#: config/tc-xtensa.c:4889
 #, c-format
-msgid "invalid %d-byte NOP requested"
-msgstr "geçersiz %d baytlık NOP istendi"
+msgid "unaligned branch target: %d bytes at 0x%lx"
+msgstr ""
 
-#: config/tc-xtensa.c:4757
-msgid "get_expanded_loop_offset: undefined opcode"
-msgstr "get_expanded_loop_offset: tanımsız opkod"
+#: config/tc-xtensa.c:4927
+#, fuzzy, c-format
+msgid "unaligned loop: %d bytes at 0x%lx"
+msgstr "0x%3$lx adresinde %2$d baytlık alan için %1$ld değeri fazla yüksek"
 
-#: config/tc-xtensa.c:4764
-msgid "get_expanded_loop_offset: invalid opcode"
-msgstr "get_expanded_loop_offset: geçersiz opkod"
+#: config/tc-xtensa.c:4951
+#, fuzzy
+msgid "unexpected fix"
+msgstr "%c beklendi"
+
+#: config/tc-xtensa.c:4962 config/tc-xtensa.c:4966
+#, fuzzy
+msgid "undecodable fix"
+msgstr "anlaşılamayan FIX"
 
-#: config/tc-xtensa.c:4880
+#: config/tc-xtensa.c:5105
 msgid "invalid last instruction for a zero-overhead loop"
 msgstr "sıfır-masraflı döngü için geçersiz son işlem"
 
-#: config/tc-xtensa.c:4935
-#, c-format
-msgid "cannot assemble '%s' into a literal fragment"
-msgstr "'%s' sabit parçacık haline getirilemedi"
+#: config/tc-xtensa.c:5176
+msgid "extra opening brace"
+msgstr ""
 
-#: config/tc-xtensa.c:4937
-msgid "..."
-msgstr "..."
+#: config/tc-xtensa.c:5186
+#, fuzzy
+msgid "extra closing brace"
+msgstr "kapanış parantezi beklendi"
 
-#: config/tc-xtensa.c:5071
+#: config/tc-xtensa.c:5204
+#, fuzzy
+msgid "missing closing brace"
+msgstr "eksik dizge"
+
+#: config/tc-xtensa.c:5284
+#, fuzzy, c-format
+msgid "unknown opcode or format name '%s'"
+msgstr "bilinmeyen opkod `%s'"
+
+#: config/tc-xtensa.c:5290
+msgid "format names only valid inside bundles"
+msgstr ""
+
+#: config/tc-xtensa.c:5295
+#, c-format
+msgid "multiple formats specified for one bundle; using '%s'"
+msgstr ""
+
+#: config/tc-xtensa.c:5351
 msgid "entry instruction with stack decrement < 16"
 msgstr "yığıt azaltımı 16'dan küçük olan giriş işlemi"
 
-#: config/tc-xtensa.c:5075
+#: config/tc-xtensa.c:5355
 msgid "entry instruction with non-constant decrement"
 msgstr "sabit olmayan azaltımlı giriş işlemi"
 
-#: config/tc-xtensa.c:5152
-#, c-format
-msgid "undefined @ suffix '%s', expected '%s'"
-msgstr "tanımsız @ soneki '%s', '%s' beklendi"
+#: config/tc-xtensa.c:5410
+#, fuzzy
+msgid "unaligned entry instruction"
+msgstr "iÅŸlem geniÅŸletilemedi"
 
-#: config/tc-xtensa.c:5242
-#, c-format
-msgid "invalid operand relocation for '%s' instruction"
-msgstr "'%s' işlemi için geçersiz işlenen yerdeğişimi"
+#: config/tc-xtensa.c:5472
+#, fuzzy
+msgid "bad instruction format"
+msgstr "hatalı işlem `%s'"
 
-#: config/tc-xtensa.c:5245
-#, c-format
-msgid "invalid relocation for operand %d in '%s' instruction"
-msgstr "'%2$s' işleminin %1$d işleneni için geçersiz yerdeğişim"
+#: config/tc-xtensa.c:5475
+#, fuzzy
+msgid "invalid relocation"
+msgstr "Geçersiz yerdeğişim"
 
-#: config/tc-xtensa.c:5252
-#, c-format
-msgid "invalid relocation type %d for %s instruction"
-msgstr "%2$s işlemi için %1$d türü yerdeğişim geçersiz"
+#: config/tc-xtensa.c:5485
+#, fuzzy, c-format
+msgid "invalid relocation for '%s' instruction"
+msgstr "işlem için geçersiz yerdeğişim"
 
-#: config/tc-xtensa.c:5261
+#: config/tc-xtensa.c:5497
 #, c-format
 msgid "invalid relocation for operand %d of '%s'"
 msgstr "'%2$s'nın %1$d işleneni için geçersiz yerdeğişim"
 
-#: config/tc-xtensa.c:5269
-#, c-format
-msgid "non-PCREL relocation operand %d for '%s': %s"
-msgstr "'%2$s' için PCREL olmayan yerdeğişim işleneni %1$d: %3$s"
-
-#: config/tc-xtensa.c:5328 config/tc-xtensa.c:5366
+#: config/tc-xtensa.c:5611 config/tc-xtensa.c:5629
 #, c-format
 msgid "unhandled local relocation fix %s"
 msgstr "desteklenmeyen yerel yerdeğişim düzeltmesi %s"
 
-#: config/tc-xtensa.c:5350
-msgid "undecodable FIX"
-msgstr "anlaşılamayan FIX"
+#: config/tc-xtensa.c:5741
+#, fuzzy
+msgid "cannot represent subtraction with an offset"
+msgstr "%s yerdeğişim türü gösterilemiyor"
+
+#: config/tc-xtensa.c:5757
+#, fuzzy, c-format
+msgid "value of %ld too large"
+msgstr "%ld'nin şimdiki değeri fazla büyük"
 
-#: config/tc-xtensa.c:5478
+#: config/tc-xtensa.c:5819
 msgid "emitting simplification relocation"
 msgstr "basitleştirme yerdeğişimi üretiliyor"
 
-#: config/tc-xtensa.c:5482
+#: config/tc-xtensa.c:5823
 msgid "emitting unknown relocation"
 msgstr "bilinmeyen yerdeğişim üretiliyor"
 
-#: config/tc-xtensa.c:5814
+#: config/tc-xtensa.c:6076
+#, fuzzy
+msgid "couldn't find a valid instruction format"
+msgstr "işlem parçacığında anlaşılamayan işlem"
+
+#: config/tc-xtensa.c:6077
 #, c-format
-msgid "fr_var %lu < length %d; ignoring"
+msgid "    ops were: "
+msgstr ""
+
+#: config/tc-xtensa.c:6079
+#, fuzzy, c-format
+msgid " %s;"
+msgstr "\t %s\n"
+
+#: config/tc-xtensa.c:6082
+#, c-format
+msgid "\n"
+msgstr ""
+
+#: config/tc-xtensa.c:6090
+#, c-format
+msgid "format '%s' allows %d slots, but there are %d opcodes"
+msgstr ""
+
+#: config/tc-xtensa.c:6101 config/tc-xtensa.c:6197
+#, fuzzy
+msgid "illegal resource usage in bundle"
+msgstr "listede geçersiz yazmaç var"
+
+#: config/tc-xtensa.c:6284
+#, fuzzy, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"
+msgstr "hedef ve kaynak1 aynı yazmaç olmalı"
+
+#: config/tc-xtensa.c:6289
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"
+msgstr ""
+
+#: config/tc-xtensa.c:6294
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) write the same queue"
+msgstr ""
+
+#: config/tc-xtensa.c:6299
+#, c-format
+msgid "opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile queue accesses"
+msgstr ""
+
+#: config/tc-xtensa.c:6315
+msgid "multiple branches or jumps in the same bundle"
+msgstr ""
+
+#: config/tc-xtensa.c:6780
+#, fuzzy
+msgid "cannot assemble into a literal fragment"
+msgstr "'%s' sabit parçacık haline getirilemedi"
+
+#: config/tc-xtensa.c:6782
+msgid "..."
+msgstr "..."
+
+#: config/tc-xtensa.c:7336
+msgid "instruction sequence (write a0, branch, retw) may trigger hardware errata"
+msgstr ""
+
+#: config/tc-xtensa.c:7444
+msgid "branching or jumping to a loop end may trigger hardware errata"
+msgstr ""
+
+#: config/tc-xtensa.c:7542
+msgid "loop end too close to another loop end may trigger hardware errata"
+msgstr ""
+
+#: config/tc-xtensa.c:7551
+#, fuzzy, c-format
+msgid "fr_var %lu < length %d"
 msgstr "fr_var %lu < %d uzunluğu; yoksayıldı"
 
-#: config/tc-xtensa.c:6000 config/tc-xtensa.c:6044
+#: config/tc-xtensa.c:7724
+msgid "loop containing less than three instructions may trigger hardware errata"
+msgstr ""
+
+#: config/tc-xtensa.c:7795
 msgid "undecodable instruction in instruction frag"
 msgstr "işlem parçacığında anlaşılamayan işlem"
 
-#: config/tc-xtensa.c:6092
+#: config/tc-xtensa.c:7903
 msgid "invalid empty loop"
 msgstr "geçersiz boş döngü"
 
-#: config/tc-xtensa.c:6097
+#: config/tc-xtensa.c:7908
 msgid "loop target does not follow loop instruction in section"
 msgstr "döngü hedefi bölümde döngü işlemini takip etmiyor"
 
-#: config/tc-xtensa.c:6215
-msgid "get_text_align_power: argument too large"
-msgstr "get_text_align_power: argüman fazla büyük"
-
-#: config/tc-xtensa.c:6420 config/tc-xtensa.c:6566
-msgid "invalid opcode for RELAX_ALIGN_NEXT_OPCODE"
-msgstr "RELAX_ALIGN_NEXT_OPCODE için geçersiz opkod"
-
-#: config/tc-xtensa.c:6421 config/tc-xtensa.c:6567
-msgid "cannot continue"
-msgstr "devam edilemez"
-
-#: config/tc-xtensa.c:6458
-msgid "expected loop opcode in relax align next target"
-msgstr "'gevşet, sonraki hedefi hizala' içinde döngü opkodu beklendi"
-
-#: config/tc-xtensa.c:6475
-msgid "expected align_code or RELAX_ALIGN_NEXT_OPCODE"
-msgstr "align_code veya RELAX_ALIGN_NEXT_OPCODE beklendi"
-
-#: config/tc-xtensa.c:6549 config/tc-xtensa.c:6587 config/tc-xtensa.c:6591
-#: config/tc-xtensa.c:6595
-msgid "internal error aligning"
-msgstr "hizalamada iç hata"
-
-#: config/tc-xtensa.c:6676
+#: config/tc-xtensa.c:8471
 msgid "bad relaxation state"
 msgstr "hatalı gevşeme durumu"
 
-#: config/tc-xtensa.c:6752
-#, c-format
-msgid "fr_var (%ld) < length (%d); ignoring"
+#: config/tc-xtensa.c:8529
+#, fuzzy, c-format
+msgid "fr_var (%ld) < length (%d)"
 msgstr "fr_var (%ld) < length (%d); yoksayıldı"
 
-#: config/tc-xtensa.c:6928
+#: config/tc-xtensa.c:9038
 msgid "internal error: relaxation failed"
 msgstr "iç hata: gevşetme başarısız"
 
-#: config/tc-xtensa.c:6934
+#: config/tc-xtensa.c:9044
 msgid "internal error: relaxation requires too many steps"
 msgstr "iç hata: gevşetme çok fazla adım gerektiriyor"
 
-#: config/tc-xtensa.c:7055
+#: config/tc-xtensa.c:9218
 msgid "invalid relaxation fragment result"
 msgstr "geçersiz gevşetme parçacık sonucu"
 
-#: config/tc-xtensa.c:7128
+#: config/tc-xtensa.c:9300
 msgid "unable to widen instruction"
 msgstr "iÅŸlem geniÅŸletilemedi"
 
-#: config/tc-xtensa.c:7215
+#: config/tc-xtensa.c:9442
 msgid "multiple literals in expansion"
 msgstr "açılımda birden fazla sabit"
 
-#: config/tc-xtensa.c:7219
+#: config/tc-xtensa.c:9446
 msgid "no registered fragment for literal"
 msgstr "sabit için yazmaçlanmış parçacık yok"
 
-#: config/tc-xtensa.c:7221
+#: config/tc-xtensa.c:9448
 msgid "number of literal tokens != 1"
 msgstr "sabit dizgecik sayısı != 1"
 
-#: config/tc-xtensa.c:7298 config/tc-xtensa.c:7304
+#: config/tc-xtensa.c:9592 config/tc-xtensa.c:9598
 #, c-format
 msgid "unresolved loop target symbol: %s"
 msgstr "çözümlenmemiş döngü hedef sembolü: %s"
 
-#: config/tc-xtensa.c:7401
-msgid "loop relaxation specification does not correspond"
-msgstr "döngü genişletme bildirimi eşleşmiyor"
-
-#: config/tc-xtensa.c:7428
-msgid "loop too long for LOOP instruction"
-msgstr "döngü, LOOP işlemi için fazla uzun"
-
-#: config/tc-xtensa.c:7465
+#: config/tc-xtensa.c:9704
 #, c-format
 msgid "invalid expression evaluation type %d"
 msgstr "geçersiz ifade değerlendirme türü %d"
 
-#: config/tc-xtensa.c:7702
+#: config/tc-xtensa.c:9726
+msgid "loop too long for LOOP instruction"
+msgstr "döngü, LOOP işlemi için fazla uzun"
+
+#: config/tc-xtensa.c:10027
 #, c-format
 msgid "fixes not all moved from %s"
 msgstr "%s'den bütün düzeltmeler kaldırılmadı"
 
-#: config/tc-xtensa.c:7835
-msgid "inlining literal pool; specify location with .literal_position."
-msgstr "sabit havuz 'inline' haline getirildi; yerini .literal_position ile bildirin"
+#: config/tc-xtensa.c:10169
+msgid "literal pool location required for text-section-literals; specify with .literal_position"
+msgstr ""
 
-#: config/tc-xtensa.c:8230
+#: config/tc-xtensa.c:10678
 #, c-format
 msgid "could not create section %s"
 msgstr "%s bölümü oluşturulamıyor"
 
-#: config/tc-xtensa.c:8232
+#: config/tc-xtensa.c:10680
 #, c-format
 msgid "invalid flag combination on section %s"
 msgstr "%s bölümünde geçersiz bayrak bileşimi"
 
-#: config/tc-xtensa.c:8481
+#: config/tc-xtensa.c:11066
+#, fuzzy
+msgid "too many operands in instruction"
+msgstr "İşleme çok fazla işlenen geçirildi"
+
+#: config/tc-xtensa.c:11300
 #, c-format
 msgid "invalid symbolic operand %d on '%s'"
 msgstr "'%2$s' için geçersiz sembolik işlenen %1$d"
 
-#: config/tc-xtensa.c:8545
+#: config/tc-xtensa.c:11369 config/tc-xtensa.c:11443
 msgid "operand number mismatch"
 msgstr "işlenen sayısı uyuşmuyor"
 
-#: config/tc-xtensa.c:8592
+#: config/tc-xtensa.c:11372
+#, fuzzy
+msgid "cannot encode opcode"
+msgstr "opkod bulunamadı"
+
+#: config/tc-xtensa.c:11447
+#, c-format
+msgid "cannot encode opcode \"%s\" in the given format \"%s\""
+msgstr ""
+
+#: config/tc-xtensa.c:11471
+#, fuzzy, c-format
+msgid "xtensa-isa failure: %s"
+msgstr "Liste dosyası açılamadı: %s"
+
+#: config/tc-xtensa.c:11504
 msgid "invalid opcode"
 msgstr "geçersiz opkod"
 
-#: config/tc-xtensa.c:8598
+#: config/tc-xtensa.c:11510
 msgid "too few operands"
 msgstr "çok az işlenen"
 
-#: config/tc-xtensa.c:8817
+#: config/tc-xtensa.c:11637 config/tc-xtensa.c:11645
+#, fuzzy
+msgid "out of memory"
+msgstr "kapsam dışı"
+
+#: config/tc-xtensa.c:11757
+msgid "instruction with constant operands does not fit"
+msgstr "sabit işlenenli işlem sığmıyor"
+
+#: config/tc-xtensa.c:11766 config/tc-xtensa.c:11787
+#, c-format
+msgid "invalid operand %d on '%s'"
+msgstr "'%2$s' için geçersiz %1$d işleneni"
+
+#: config/tc-xtensa.c:11778
+#, fuzzy
+msgid "invalid subtract operand"
+msgstr "geçersiz dal işleneni"
+
+#: config/tc-xtensa.c:11792
+#, c-format
+msgid "invalid expression for operand %d on '%s'"
+msgstr "'%2$s' içinde %1$d işleneninde geçersiz ifade"
+
+#: config/tc-xtensa.c:11822
+#, fuzzy
+msgid "cannot decode instruction format"
+msgstr "İşlem çevrimlenemedi"
+
+#: config/tc-xtensa.c:11981
 msgid "ignoring extra '-rename-section' delimiter ':'"
 msgstr "fazla '-rename-section' sınırlayıcısı ':' yoksayıldı"
 
-#: config/tc-xtensa.c:8822
+#: config/tc-xtensa.c:11986
 #, c-format
 msgid "ignoring invalid '-rename-section' specification: '%s'"
 msgstr "geçersiz '-rename-section' bildirimi '%s' yoksayıldı"
 
-#: config/tc-xtensa.c:8845
+#: config/tc-xtensa.c:11997
 #, c-format
 msgid "section %s renamed multiple times"
 msgstr "%s bölümü birden fazla defa yeniden adlandırıldı"
 
-#: config/tc-xtensa.c:8847
+#: config/tc-xtensa.c:11999
 #, c-format
 msgid "multiple sections remapped to output section %s"
 msgstr "birden fazla bölüm %s çıktı bölümüne eşlendi"
 
-#: config/tc-z8k.c:314
+#: config/tc-z8k.c:271
 #, c-format
 msgid "register rr%d out of range"
 msgstr "rr%d yazmacı kapsam dışı"
 
-#: config/tc-z8k.c:316
+#: config/tc-z8k.c:273
 #, c-format
 msgid "register rr%d does not exist"
 msgstr "rr%d yazmacı yok"
 
-#: config/tc-z8k.c:326
+#: config/tc-z8k.c:283
 #, c-format
 msgid "register rh%d out of range"
 msgstr "rh%d yazmacı kapsam dışı"
 
-#: config/tc-z8k.c:336
+#: config/tc-z8k.c:293
 #, c-format
 msgid "register rl%d out of range"
 msgstr "rl%d yazmacı kapsam dışı"
 
-#: config/tc-z8k.c:347
+#: config/tc-z8k.c:304
 #, c-format
 msgid "register rq%d out of range"
 msgstr "rq%d yazmacı kapsam dışı"
 
-#: config/tc-z8k.c:349
+#: config/tc-z8k.c:306
 #, c-format
 msgid "register rq%d does not exist"
 msgstr "rq%d yazmacı yok"
 
-#: config/tc-z8k.c:359
+#: config/tc-z8k.c:316
 #, c-format
 msgid "register r%d out of range"
 msgstr "r%d yazmacı kapsam dışı"
 
-#: config/tc-z8k.c:404
+#: config/tc-z8k.c:357
 #, c-format
 msgid "expected %c"
 msgstr "%c beklendi"
 
-#: config/tc-z8k.c:421
+#: config/tc-z8k.c:372
 #, c-format
 msgid "register is wrong size for a word %s"
 msgstr "Word %s'i için yazmaç yanlış boyda"
 
-#: config/tc-z8k.c:437
+#: config/tc-z8k.c:386
 #, c-format
 msgid "register is wrong size for address %s"
 msgstr "%s adresi için yazmaç yanlış boyda"
 
+#: config/tc-z8k.c:520
+#, fuzzy, c-format
+msgid "unknown interrupt %s"
+msgstr "bilinmeyen iÅŸlem '%s'"
+
 #. No interrupt type specified, opcode won't do anything.
-#: config/tc-z8k.c:585
+#: config/tc-z8k.c:543
 msgid "opcode has no effect"
 msgstr "opkod etkisiz"
 
-#: config/tc-z8k.c:697
+#: config/tc-z8k.c:654
 msgid "Missing ) in ra(rb)"
 msgstr "ra(rb) içinde eksik )"
 
-#: config/tc-z8k.c:919 config/tc-z8k.c:925
+#: config/tc-z8k.c:734 config/tc-z8k.c:773
+#, fuzzy, c-format
+msgid "invalid condition code '%s'"
+msgstr "geçersiz koşul kodu ismi"
+
+#: config/tc-z8k.c:746
+#, fuzzy, c-format
+msgid "invalid flag '%s'"
+msgstr "Geçersiz etiket '%s'"
+
+#: config/tc-z8k.c:900 config/tc-z8k.c:906
 msgid "invalid indirect register size"
 msgstr "geçersiz dolaylı yazmaç boyu"
 
-#: config/tc-z8k.c:971
-#, c-format
-msgid "operand %s0x%x out of range"
-msgstr "%s0x%x işleneni kapsam dışı"
+#: config/tc-z8k.c:923 config/tc-z8k.c:1070 config/tc-z8k.c:1075
+#, fuzzy
+msgid "invalid control register name"
+msgstr "geçersiz yazmaç ismi"
 
-#: config/tc-z8k.c:1099
+#: config/tc-z8k.c:1059
 msgid "immediate must be 1 or 2"
 msgstr "şimdiki 1 veya 2 olmalı"
 
-#: config/tc-z8k.c:1102
+#: config/tc-z8k.c:1062
 msgid "immediate 1 or 2 expected"
 msgstr "ÅŸimdiki 1 veya 2 beklendi"
 
-#: config/tc-z8k.c:1129
+#: config/tc-z8k.c:1093
 msgid "can't use R0 here"
 msgstr "burada R0 kullanılamaz"
 
-#: config/tc-z8k.c:1292
+#: config/tc-z8k.c:1255
 msgid "Can't find opcode to match operands"
 msgstr "işlenenlerle eşleşen opkod bulunamadı"
 
-#: config/tc-z8k.c:1411
+#: config/tc-z8k.c:1366
 #, c-format
 msgid "invalid architecture -z%s"
 msgstr "geçersiz yapı -z%s"
 
-#: config/tc-z8k.c:1432
+#: config/tc-z8k.c:1386
+#, c-format
 msgid ""
 " Z8K options:\n"
 "  -z8001                  generate segmented code\n"
@@ -10672,46 +11845,48 @@ msgstr ""
 "  -z8002                  bölümlenmemiş kod üretir\n"
 "  -linkrelax              bağlayıcı tarafından genişletilebilen kod üretir\n"
 
-#: config/tc-z8k.c:1445
+#: config/tc-z8k.c:1398
+#, c-format
 msgid "call to md_convert_frag\n"
 msgstr "md_convert_frag'e çağrı \n"
 
-#: config/tc-z8k.c:1476 config/tc-z8k.c:1487
+#: config/tc-z8k.c:1434 config/tc-z8k.c:1455 config/tc-z8k.c:1476
 msgid "cannot branch to odd address"
 msgstr "Tek sayılı adrese dallanılamaz"
 
-#: config/tc-z8k.c:1479 config/tc-z8k.c:1490
+#: config/tc-z8k.c:1438 config/tc-z8k.c:1459
 msgid "relative jump out of range"
 msgstr "göreceli yerdeğişim kapsam dışı"
 
-#: config/tc-z8k.c:1497
+#: config/tc-z8k.c:1479
 msgid "relative call out of range"
 msgstr "göreceli çağrı kapsam dışı"
 
-#: config/tc-z8k.c:1523
+#: config/tc-z8k.c:1509
 msgid "relative address out of range"
 msgstr "göreceli adres kapsam dışı"
 
-#: config/tc-z8k.c:1543
+#: config/tc-z8k.c:1520
 #, c-format
 msgid "md_apply_fix3: unknown r_type 0x%x\n"
 msgstr "md_apply_fix3: bilinmeyen r_type 0x%x\n"
 
-#: config/tc-z8k.c:1556
+#: config/tc-z8k.c:1532
+#, c-format
 msgid "call to md_estimate_size_before_relax\n"
 msgstr "md_estimate_size_before_relax'e çağrı \n"
 
-#: config/tc-z8k.c:1600
+#: config/tc-z8k.c:1569
 #, c-format
 msgid "Can't subtract symbols in different sections %s %s"
 msgstr "Değişik bölümlerdeki semboller birbirinden çıkartılamaz %s %s"
 
-#: depend.c:200
+#: depend.c:193
 #, c-format
 msgid "can't open `%s' for writing"
 msgstr "`%s' yazmak için açılamadı"
 
-#: depend.c:212
+#: depend.c:205
 #, c-format
 msgid "can't close `%s'"
 msgstr "`%s' kapatılamadı"
@@ -10721,344 +11896,356 @@ msgstr "`%s' kapatılamadı"
 msgid "register save offset not a multiple of %u"
 msgstr "yazmaç sakla görecesi %u'nun katı değil"
 
-#: dw2gencfi.c:388
+#: dw2gencfi.c:345
+#, fuzzy
+msgid "CFI state restore without previous remember"
+msgstr "öncesinde .cfi_startproc olmadan CFI işlemi kullanılmış"
+
+#: dw2gencfi.c:391
 msgid "missing separator"
 msgstr "eksik ayraç"
 
-#: dw2gencfi.c:410 dw2gencfi.c:428
+#: dw2gencfi.c:413 dw2gencfi.c:431
 msgid "bad register expression"
 msgstr "geçersiz yazmaç ifadesi"
 
-#: dw2gencfi.c:450 dw2gencfi.c:547
+#: dw2gencfi.c:453 dw2gencfi.c:554
 msgid "CFI instruction used without previous .cfi_startproc"
 msgstr "öncesinde .cfi_startproc olmadan CFI işlemi kullanılmış"
 
-#: dw2gencfi.c:579
+#: dw2gencfi.c:586
 msgid "previous CFI entry not closed (missing .cfi_endproc)"
 msgstr "önceki CFI girdisi kapatılmamış (eksik .cfi_endproc)"
 
-#: dw2gencfi.c:612
+#: dw2gencfi.c:620
 msgid ".cfi_endproc without corresponding .cfi_startproc"
 msgstr ".cfi_startproc ile eÅŸleÅŸmeyen .cfi_endproc"
 
-#: dw2gencfi.c:987
+#: dw2gencfi.c:1026
 msgid "open CFI at the end of file; missing .cfi_endproc directive"
 msgstr "dosyasonunda açık CFI; .cfi_endproc yönergesi eksik"
 
-#: dwarf2dbg.c:468 dwarf2dbg.c:498
+#: dwarf2dbg.c:458 dwarf2dbg.c:487
 msgid "file number less than one"
 msgstr "Dosya numarası birden küçük"
 
-#: dwarf2dbg.c:474
+#: dwarf2dbg.c:464
 #, c-format
 msgid "file number %ld already allocated"
 msgstr "%ld dosya sayısı zaten ayrılmış"
 
-#: dwarf2dbg.c:503 dwarf2dbg.c:1068
+#: dwarf2dbg.c:492 dwarf2dbg.c:1025
 #, c-format
 msgid "unassigned file number %ld"
 msgstr "verilmemiş dosya numarası %ld"
 
-#: dwarf2dbg.c:1134 dwarf2dbg.c:1331
+#: dwarf2dbg.c:1090 dwarf2dbg.c:1281
 msgid "internal error: unknown dwarf2 format"
 msgstr "iç hata: bilinmeyen dwarf2 biçemi"
 
-#: dwarf2dbg.c:1476 dwarf2dbg.c:1484 dwarf2dbg.c:1492 dwarf2dbg.c:1513
+#: dwarf2dbg.c:1438 dwarf2dbg.c:1446 dwarf2dbg.c:1454 dwarf2dbg.c:1475
 msgid "dwarf2 is not supported for this object file format"
 msgstr "bu nesne dosyası biçemi için dwarf2 desteklenmiyor"
 
-#: ecoff.c:1556
+#: ecoff.c:1552
 #, c-format
 msgid "string too big (%lu bytes)"
 msgstr "dizge fazla büyük (%lu bayt)"
 
-#: ecoff.c:1582
+#: ecoff.c:1578
 #, c-format
 msgid "inserting \"%s\" into string hash table: %s"
 msgstr "dizge hash tablosuna \"%s\" ekleniyor: %s"
 
-#: ecoff.c:1614 ecoff.c:1808 ecoff.c:1833 ecoff.c:1865 ecoff.c:2019
-#: ecoff.c:2132
+#: ecoff.c:1609 ecoff.c:1802 ecoff.c:1825 ecoff.c:1856 ecoff.c:2009
+#: ecoff.c:2120
 msgid "no current file pointer"
 msgstr "mevcut dosya imleyicisi yok"
 
-#: ecoff.c:1701
+#: ecoff.c:1696
 msgid "too many st_End's"
 msgstr "çok fazla sayıda st_End"
 
-#: ecoff.c:2044
+#: ecoff.c:2034
 #, c-format
 msgid "inserting \"%s\" into tag hash table: %s"
 msgstr "etiket hash tablosuna \"%s\" eklendi: %s"
 
-#: ecoff.c:2210
+#: ecoff.c:2195
 msgid "fake .file after real one"
 msgstr "gerçek olanından sonra yalancı .file"
 
-#: ecoff.c:2300
+#: ecoff.c:2285
 msgid "filename goes over one page boundary"
 msgstr "dosya adı bir sayfa sınırının dışında."
 
-#: ecoff.c:2435
+#: ecoff.c:2418
 msgid ".begin directive without a preceding .file directive"
 msgstr "öncesinde .file yönergesi olmadan .begin yönergesi"
 
-#: ecoff.c:2442
+#: ecoff.c:2425
 msgid ".begin directive without a preceding .ent directive"
 msgstr "öncesinde .ent yönergesi olmaksızın .begin yönergesi"
 
-#: ecoff.c:2474
+#: ecoff.c:2456
 msgid ".bend directive without a preceding .file directive"
 msgstr "öncesinde .file yönergesi olmaksızın .bend yönergesi"
 
-#: ecoff.c:2481
+#: ecoff.c:2463
 msgid ".bend directive without a preceding .ent directive"
 msgstr "öncesinde .ent yönergesi olmaksızın .bend yönergesi"
 
-#: ecoff.c:2494
+#: ecoff.c:2476
 msgid ".bend directive names unknown symbol"
 msgstr ".bend yönergesi bilinmeyen sembolden bahsediyor"
 
-#: ecoff.c:2538
+#: ecoff.c:2519
 msgid ".def pseudo-op used inside of .def/.endef; ignored"
 msgstr ".def/.endef içinde .def sanal-op'u kullanılmış; yoksayıldı"
 
-#: ecoff.c:2540
+#: ecoff.c:2521
 msgid "empty symbol name in .def; ignored"
 msgstr ".def içinde boş sembol adı; yoksayıldı"
 
-#: ecoff.c:2578
+#: ecoff.c:2558
 msgid ".dim pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .dim sanal-op'u; yoksayıldı"
 
-#: ecoff.c:2593
+#: ecoff.c:2573
 msgid "badly formed .dim directive"
 msgstr "hatalı biçemlenmiş .dim yönergesi"
 
-#: ecoff.c:2606
+#: ecoff.c:2586
 msgid "too many .dim entries"
 msgstr "çok fazla .dim girdisi"
 
-#: ecoff.c:2627
+#: ecoff.c:2606
 msgid ".scl pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .scl sanal-op'u; yoksayıldı"
 
-#: ecoff.c:2653
+#: ecoff.c:2631
 msgid ".size pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .size sanal op'u; yoksayıldı"
 
-#: ecoff.c:2668
+#: ecoff.c:2646
 msgid "badly formed .size directive"
 msgstr "hatalı biçemlenmiş .size yönergesi"
 
-#: ecoff.c:2681
+#: ecoff.c:2659
 msgid "too many .size entries"
 msgstr "çok fazla .size girdisi"
 
-#: ecoff.c:2704
+#: ecoff.c:2681
 msgid ".type pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .type sanal-op'u; yoksayıldı"
 
 #. FIXME: We could handle this by setting the continued bit.
 #. There would still be a limit: the .type argument can not
 #. be infinite.
-#: ecoff.c:2722
+#: ecoff.c:2699
 #, c-format
 msgid "the type of %s is too complex; it will be simplified"
 msgstr "%s türü fazla karmaşık; basitleştirilecek"
 
-#: ecoff.c:2733
+#: ecoff.c:2710
 msgid "Unrecognized .type argument"
 msgstr "Bilinmeyen .type argümanı"
 
-#: ecoff.c:2772
+#: ecoff.c:2748
 msgid ".tag pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .tag sanal-op'u; yoksayıldı"
 
-#: ecoff.c:2798
+#: ecoff.c:2773
 msgid ".val pseudo-op used outside of .def/.endef; ignored"
 msgstr ".def/.endef dışında kullanılan .val sanal-op'u; yoksayıldı"
 
-#: ecoff.c:2806
+#: ecoff.c:2781
 msgid ".val expression is too copmlex"
 msgstr ".val ifadesi fazla karmaşık"
 
-#: ecoff.c:2837
+#: ecoff.c:2811
 msgid ".endef pseudo-op used before .def; ignored"
 msgstr ".def öncesinde kullanılan .endef sanal-op'u; yoksayıldı"
 
-#: ecoff.c:2863 ecoff.c:2944
+#: ecoff.c:2837 ecoff.c:2918
 msgid "bad COFF debugging information"
 msgstr "Hatalı COFF hata ayıklama bilgisi"
 
-#: ecoff.c:2912
+#: ecoff.c:2886
 #, c-format
 msgid "no tag specified for %s"
 msgstr "%s için etiket belirtilmemiş"
 
-#: ecoff.c:3015
+#: ecoff.c:2988
 msgid ".end directive without a preceding .file directive"
 msgstr "öncesinde .file yönergesi olmaksızın .end yönergesi"
 
-#: ecoff.c:3022
+#: ecoff.c:2995
 msgid ".end directive without a preceding .ent directive"
 msgstr "öncesinde .ent yönergesi olmaksızın .end yönergesi"
 
-#: ecoff.c:3044
+#: ecoff.c:3017
 msgid ".end directive names unknown symbol"
 msgstr ".end yönergesi bilinmeyen sembolden bahsediyor"
 
-#: ecoff.c:3072
+#: ecoff.c:3044
 msgid "second .ent directive found before .end directive"
 msgstr "öncesinde .end yönergesi olmaksızın ikinci .ent yönergesi"
 
-#: ecoff.c:3146
+#: ecoff.c:3116
 msgid "no way to handle .file within .ent/.end section"
 msgstr ".ent/.end bölümü içinde .file desteklenmiyor"
 
-#: ecoff.c:3271
+#: ecoff.c:3233
 msgid ".loc before .file"
 msgstr ".file'dan önce .loc"
 
-#: ecoff.c:3410
+#: ecoff.c:3355 read.c:1446 read.c:1552 read.c:2226 read.c:2840 read.c:4925
+#: symbols.c:358 symbols.c:457
+#, c-format
+msgid "symbol `%s' is already defined"
+msgstr "`%s' sembolü zaten tanımlanmış"
+
+#: ecoff.c:3368
 msgid "bad .weakext directive"
 msgstr "hatalı .weakext yönergesi"
 
-#: ecoff.c:3479
+#: ecoff.c:3436
 #, c-format
 msgid ".stab%c is not supported"
 msgstr ".stab%c desteklenmiyor"
 
-#: ecoff.c:3489
+#: ecoff.c:3446
 #, c-format
 msgid ".stab%c: ignoring non-zero other field"
 msgstr ".stab%c: sıfır olmayan başka alan yoksayıldı"
 
-#: ecoff.c:3523
+#: ecoff.c:3480
 #, c-format
 msgid "line number (%d) for .stab%c directive cannot fit in index field (20 bits)"
 msgstr ".stab%2$c yönergesi satır numarası (%1$d) indeks alanına sığmadı (20 bit)"
 
-#: ecoff.c:3559
+#: ecoff.c:3516
 #, c-format
 msgid "illegal .stab%c directive, bad character"
 msgstr "geçersiz .stab%c yönergesi, hatalı karakter"
 
-#: ecoff.c:4021 ecoff.c:4210 ecoff.c:4235
+#: ecoff.c:3975 ecoff.c:4164 ecoff.c:4189
 msgid ".begin/.bend in different segments"
 msgstr ".begin/.bend farklı bölümlerde"
 
-#: ecoff.c:4737
+#: ecoff.c:4685
 msgid "missing .end or .bend at end of file"
 msgstr "dosya sonunda eksik .end veya .bend"
 
-#: ecoff.c:5227
+#: ecoff.c:5170
 msgid "GP prologue size exceeds field size, using 0 instead"
 msgstr "GP önbilgi boyu dosya boyundan büyük, 0 kullanıldı"
 
-#: expr.c:83 read.c:3232
+#: expr.c:82 read.c:3209
 msgid "bignum invalid"
 msgstr "bignum geçersiz"
 
-#: expr.c:85 read.c:3234 read.c:3574 read.c:4474
+#: expr.c:84 read.c:3211 read.c:3552 read.c:4426
 msgid "floating point number invalid"
 msgstr "kayan nokta sayısı geçersiz"
 
-#: expr.c:243
+#: expr.c:232
 msgid "bad floating-point constant: exponent overflow"
 msgstr "hatalı kayan nokta sabiti: kuvvet taşması"
 
-#: expr.c:247
+#: expr.c:236
 #, c-format
 msgid "bad floating-point constant: unknown error code=%d"
 msgstr "hatalı kayan nokta sabiti: bilinmeyen hata kodu=%d"
 
-#: expr.c:425
+#: expr.c:412
 msgid "a bignum with underscores may not have more than 8 hex digits in any word"
 msgstr ""
 "Alt tire içeren bir büyüksayı (bignum) her word içinde 8 onaltılık basamaktan\n"
 "fazla bulunduramaz."
 
-#: expr.c:448
+#: expr.c:435
 msgid "a bignum with underscores must have exactly 4 words"
 msgstr "Alt tire içeren bir büyüksayı (bignum) tam 4 word'e sahip olmalı."
 
 #. Either not seen or not defined.
 #. @@ Should print out the original string instead of
 #. the parsed number.
-#: expr.c:571
+#: expr.c:558
 #, c-format
 msgid "backward ref to unknown label \"%d:\""
 msgstr "bilinmeyen etiket \"%d:\"e geri baÅŸvuru"
 
-#: expr.c:694
+#: expr.c:676
 msgid "character constant too large"
 msgstr "karakter sabiti fazla büyük"
 
-#: expr.c:942
+#: expr.c:922
 #, c-format
 msgid "expr.c(operand): bad atof_generic return val %d"
 msgstr "expr.c(işlenen): hatalı atof_generic geridönüş değeri %d"
 
-#: expr.c:1004
+#: expr.c:980
 #, c-format
 msgid "missing '%c'"
 msgstr "eksik '%c'"
 
-#: expr.c:1016 read.c:3945
+#: expr.c:991 read.c:3910
 msgid "EBCDIC constants are not supported"
 msgstr "EBCDIC sabitleri desteklenmiyor"
 
-#: expr.c:1099
+#: expr.c:1112
 #, c-format
 msgid "Unary operator %c ignored because bad operand follows"
 msgstr "Sonrasından gelen hatalı işlenenler yüzünden tekli işlemimi %c yoksayıldı"
 
-#: expr.c:1145 expr.c:1170
+#: expr.c:1158 expr.c:1183
 msgid "syntax error in .startof. or .sizeof."
 msgstr ".startof veya .sizeof içinde sözdizim hatası."
 
-#: expr.c:1666
+#: expr.c:1685
 msgid "missing operand; zero assumed"
 msgstr "eksik işlenen; sıfır varsayıldı"
 
-#: expr.c:1701
+#: expr.c:1720
 msgid "left operand is a bignum; integer 0 assumed"
 msgstr "sol işlenen büyüksayı (bignum); tamsayı 0 varsayıldı"
 
-#: expr.c:1703
+#: expr.c:1722
 msgid "left operand is a float; integer 0 assumed"
 msgstr "sol işlenen kayan noktalı; tamsayı 0 varsayıldı"
 
-#: expr.c:1712
+#: expr.c:1731
 msgid "right operand is a bignum; integer 0 assumed"
 msgstr "sağ işlenen büyüksayı (bignum); tamsayı 0 varsayıldı"
 
-#: expr.c:1714
+#: expr.c:1733
 msgid "right operand is a float; integer 0 assumed"
 msgstr "sağ işlenen kayan noktalı; tamsayı 0 varsayıldı"
 
-#: expr.c:1770 symbols.c:1191
+#: expr.c:1789 symbols.c:1160
 msgid "division by zero"
 msgstr "sıfırla bölüm"
 
-#: expr.c:1868
+#: expr.c:1887
 msgid "operation combines symbols in different segments"
 msgstr "işlem başka bölümlerdeki sembolleri birleştiriyor"
 
-#: frags.c:87
-#, c-format
-msgid "can't extend frag %u chars"
-msgstr "frag %u. chars uzatılamadı"
-
-#: frags.c:168
+#: frags.c:48
 msgid "attempt to allocate data in absolute section"
 msgstr "kesin bölüm için veri ayırma denemesi"
 
-#: frags.c:174
+#: frags.c:54
 msgid "attempt to allocate data in common section"
 msgstr "ortak bölümde veri ayırma denemesi"
 
+#: frags.c:105
+#, c-format
+msgid "can't extend frag %u chars"
+msgstr "frag %u. chars uzatılamadı"
+
+#. For error messages.
 #. Detect if we are reading from stdin by examining the file
 #. name returned by as_where().
 #.
@@ -11070,508 +12257,556 @@ msgstr "ortak bölümde veri ayırma denemesi"
 #. line here (assuming of course that we actually have a line of
 #. input to read), so that it can be displayed in the listing
 #. that is produced at the end of the assembly.
-#: input-file.c:145 input-scrub.c:242 listing.c:343
+#: input-file.c:147 input-scrub.c:239 listing.c:332
 msgid "{standard input}"
 msgstr "{standart girdi}"
 
-#: input-file.c:149
-#, c-format
-msgid "can't open %s for reading"
+#: input-file.c:155 input-file.c:166
+#, fuzzy, c-format
+msgid "Can't open %s for reading"
 msgstr "%s okuma için açılamadı."
 
-#: input-file.c:212 input-file.c:239
+#: input-file.c:231 input-file.c:260
 #, c-format
 msgid "Can't read from %s"
 msgstr "%s'den okunamıyor"
 
-#: input-file.c:247
+#: input-file.c:272
 #, c-format
 msgid "Can't close %s"
 msgstr "%s kapatılamıyor"
 
-#: input-scrub.c:272
+#: input-scrub.c:264
 msgid "macros nested too deeply"
 msgstr "makrolar çok derin içiçe"
 
-#: input-scrub.c:375 input-scrub.c:397
+#: input-scrub.c:366 input-scrub.c:388
 msgid "partial line at end of file ignored"
 msgstr "dosyasonunda satır parçası yoksayıldı"
 
-#: itbl-ops.c:351
+#: itbl-ops.c:338
+#, c-format
 msgid "Unable to allocate memory for new instructions\n"
 msgstr "Yeni işlemler için bellek ayrılamadı\n"
 
-#: listing.c:243
+#: listing.c:238
 msgid "Warning:"
 msgstr "Uyarı:"
 
-#: listing.c:250
+#: listing.c:244
 msgid "Error:"
 msgstr "Hata:"
 
-#: listing.c:1130
+#: listing.c:1092
 #, c-format
 msgid "can't open list file: %s"
 msgstr "Liste dosyası açılamadı: %s"
 
-#: listing.c:1154
+#: listing.c:1114
 #, c-format
 msgid "error closing list file: %s"
 msgstr "liste dosyası kapatılırken hata: %s"
 
-#: listing.c:1233
+#: listing.c:1187
 msgid "strange paper height, set to no form"
 msgstr "kağıt yüksekliği garip, bir forma atanmadı"
 
-#: listing.c:1299
+#: listing.c:1251
 msgid "new line in title"
 msgstr "başlıkta yenisatır"
 
 #. Turns the next expression into a string.
-#: macro.c:382
+#: macro.c:391
 #, no-c-format
 msgid "% operator needs absolute expression"
 msgstr "% işlemimi için kesin ifade gerekli"
 
-#: macro.c:545
+#: macro.c:555
 msgid "unexpected end of file in macro definition"
 msgstr "Makro tanımında beklenmeyen dosyasonu"
 
-#: macro.c:554
+#: macro.c:564
 msgid "missing ) after formals"
 msgstr "resmi parametrelerden sonra eksik )"
 
-#: macro.c:703
+#: macro.c:579
+#, fuzzy
+msgid "Missing macro name"
+msgstr "eksik sembol adı"
+
+#: macro.c:588
+#, fuzzy
+msgid "Bad macro parameter list"
+msgstr "Hatalı yazmaç listesi"
+
+#: macro.c:595
+#, fuzzy
+msgid "Macro with this name was already defined"
+msgstr "Yazmaç sembolü %s zaten tanımlı."
+
+#: macro.c:712
 msgid "missplaced )"
 msgstr "yanlış yerde )"
 
-#: macro.c:960
+#: macro.c:965
 msgid "confusion in formal parameters"
 msgstr "resmi parametrelerde karışıklık"
 
-#: macro.c:965
+#: macro.c:970
 msgid "macro formal argument does not exist"
 msgstr "resmi makro argümanı yok"
 
-#: macro.c:980
+#: macro.c:985
 msgid "can't mix positional and keyword arguments"
 msgstr "yere bağımlı ve anahtar kelime argümanları birarada kullanılamaz"
 
-#: macro.c:988
+#: macro.c:993
 msgid "too many positional arguments"
 msgstr "çok fazla yere bağımlı argüman"
 
-#: macro.c:1163
+#: macro.c:1153
 msgid "unexpected end of file in irp or irpc"
 msgstr "irp veya irpc içinde beklenmeyen dosyasonu"
 
-#: macro.c:1171
+#: macro.c:1161
 msgid "missing model parameter"
 msgstr "eksik model parametresi"
 
 #: messages.c:104
+#, c-format
 msgid "Assembler messages:\n"
 msgstr "Çevirici iletileri:\n"
 
-#: messages.c:214
+#: messages.c:212
+#, c-format
 msgid "Warning: "
 msgstr "Uyarı: "
 
-#: messages.c:318
+#: messages.c:313
+#, c-format
 msgid "Error: "
 msgstr "Hata: "
 
-#: messages.c:413 messages.c:433
+#: messages.c:408 messages.c:428
+#, c-format
 msgid "Fatal error: "
 msgstr "Ölümcül hata: "
 
-#: messages.c:450
+#: messages.c:443
+#, c-format
 msgid "Internal error!\n"
 msgstr "İç hata!\n"
 
-#: messages.c:452
+#: messages.c:445
 #, c-format
 msgid "Assertion failure in %s at %s line %d.\n"
 msgstr "%s içinde %s'de, %d satırında olumlama başarısız.\n"
 
-#: messages.c:455
+#: messages.c:448
 #, c-format
 msgid "Assertion failure at %s line %d.\n"
 msgstr "%s'de %d satırında olumlama başarısız.\n"
 
-#: messages.c:456 messages.c:475
+#: messages.c:449 messages.c:466
+#, c-format
 msgid "Please report this bug.\n"
 msgstr "Lütfen bu hatayı bildirin.\n"
 
-#: messages.c:470
+#: messages.c:461
 #, c-format
 msgid "Internal error, aborting at %s line %d in %s\n"
 msgstr "İç hata, %s'de %d satırında, %s içinde durduruldu\n"
 
-#: messages.c:473
+#: messages.c:464
 #, c-format
 msgid "Internal error, aborting at %s line %d\n"
 msgstr "İç hata, %s'de %d satırında durduruldu\n"
 
-#: output-file.c:48
+#: messages.c:535
+#, fuzzy, c-format
+msgid "%s out of range (%d is not between %d and %d)"
+msgstr "işlenen kapsam dışı (%s, %d ve %d arasında değil)"
+
+#. xgettext:c-format.
+#: messages.c:559
+#, fuzzy, c-format
+msgid "%s out of range (0x%s is not between 0x%s and 0x%s)"
+msgstr "işlenen kapsam dışı (%s, %d ve %d arasında değil)"
+
+#: output-file.c:47
 #, c-format
 msgid "can't open a bfd on stdout %s"
 msgstr "%s standart çıktısında bfd açılamadı "
 
-#: output-file.c:52 output-file.c:115
+#: output-file.c:52
+#, c-format
+msgid "Selected target format '%s' unknown"
+msgstr ""
+
+#: output-file.c:54 output-file.c:117
 #, c-format
 msgid "FATAL: can't create %s"
 msgstr "ÖLÜMCÜL: %s oluşturulamadı"
 
-#: output-file.c:73 output-file.c:80
+#: output-file.c:74 output-file.c:81
 #, c-format
 msgid "FATAL: can't close %s\n"
 msgstr "ÖLÜMCÜL: %s kapatılamadı\n"
 
-#: output-file.c:126
+#: output-file.c:130
 #, c-format
 msgid "FATAL: can't close %s"
 msgstr "ÖLÜMCÜL: %s kapatılamadı"
 
-#: output-file.c:147
+#: output-file.c:150
 msgid "Failed to emit an object byte"
 msgstr "Bir nesne baytı üretilemedi"
 
-#: output-file.c:148
+#: output-file.c:151
 msgid "can't continue"
 msgstr "devam edilemez"
 
-#: read.c:442
+#: read.c:453
 #, c-format
 msgid "error constructing %s pseudo-op table: %s"
 msgstr "%s sanal op tablosu oluÅŸturulurken hata: %s"
 
-#: read.c:809
+#: read.c:819
 #, c-format
 msgid "unknown pseudo-op: `%s'"
 msgstr "bilinmeyen sanal op:  `%s'"
 
-#: read.c:940
+#: read.c:950
 #, c-format
 msgid "label \"%d$\" redefined"
 msgstr "\"%d$\" etiketi yeniden tanımlandı"
 
-#: read.c:1152
+#: read.c:1181
 msgid ".abort detected.  Abandoning ship."
 msgstr ".abort bulundu. Terk ediliyor."
 
-#: read.c:1174 read.c:2413
+#: read.c:1199 read.c:2398
 msgid "ignoring fill value in absolute section"
 msgstr "kesin bölümde dolgu değeri yoksayıldı"
 
-#: read.c:1260
+#: read.c:1293
 #, c-format
 msgid "alignment too large: %u assumed"
 msgstr "hizalama fazla büyük: %u varsayıldı"
 
-#: read.c:1292
+#: read.c:1325
 msgid "expected fill pattern missing"
 msgstr "beklenen dolgu kalıbı eksik"
 
-#: read.c:1417
-#, c-format
-msgid "length of .comm \"%s\" is already %ld; not changing to %ld"
+#: read.c:1430
+msgid "missing size expression"
+msgstr "boyut ifadesi eksik"
+
+#: read.c:1436
+#, fuzzy, c-format
+msgid "size (%ld) out of range, ignored"
+msgstr ".COMM ortak uzunluğu (%ld) kapsam dışı, yoksayıldı."
+
+#: read.c:1456
+#, fuzzy, c-format
+msgid "size of \"%s\" is already %ld; not changing to %ld"
 msgstr ".comm \"%s\" uzunluÄŸu zaten %ld; %ld olarak deÄŸiÅŸtirilmedi."
 
 #. Some of the back ends can't deal with non-positive line numbers.
 #. Besides, it's silly.
-#: read.c:1636
+#: read.c:1677
 #, c-format
 msgid "line numbers must be positive; line number %d rejected"
 msgstr "satır numaraları pozitif olmalı; %d satır numarası reddedildi"
 
-#: read.c:1664
+#: read.c:1704
 msgid "start address not supported"
 msgstr "başlangıç adresi desteklenmiyor"
 
-#: read.c:1674
+#: read.c:1713
 msgid ".err encountered"
 msgstr ".err bulundu"
 
-#: read.c:1693 read.c:1695
+#: read.c:1729
+msgid ".error directive invoked in source file"
+msgstr ""
+
+#: read.c:1730
+msgid ".warning directive invoked in source file"
+msgstr ""
+
+#: read.c:1736
+#, fuzzy, c-format
+msgid "%s argument must be a string"
+msgstr "Her iki argüman da ikame sembolü olmalı"
+
+#: read.c:1768 read.c:1770
 #, c-format
 msgid ".fail %ld encountered"
 msgstr ".fail %ld bulundu"
 
-#: read.c:1732
+#: read.c:1806
 #, c-format
 msgid ".fill size clamped to %d"
 msgstr ".fill boyu %d'e bağlandı."
 
-#: read.c:1737
+#: read.c:1811
 msgid "size negative; .fill ignored"
 msgstr "Boy negatif: .fill yoksayıldı."
 
-#: read.c:1743
+#: read.c:1817
 msgid "repeat < 0; .fill ignored"
 msgstr "tekrar < 0, .fill yoksayıldı"
 
-#: read.c:1903
+#: read.c:1974
 #, c-format
 msgid "unrecognized .linkonce type `%s'"
 msgstr "bilinmeyen .linkonce türü `%s'"
 
-#: read.c:1916 read.c:1942
+#: read.c:1987 read.c:2013
 msgid ".linkonce is not supported for this object file format"
 msgstr ".linkonce bu nesne dosya biçemi için desteklenmiyor"
 
-#: read.c:1938
+#: read.c:2009
 #, c-format
 msgid "bfd_set_section_flags: %s"
 msgstr "bfd_set_section_flags: %s"
 
-#: read.c:1993
-msgid "missing size expression"
-msgstr "boyut ifadesi eksik"
-
-#: read.c:1999
-#, c-format
-msgid "BSS length (%d) < 0 ignored"
-msgstr "BSS uzunluğu (%d) <0 yoksayıldı."
-
-#: read.c:2015
+#: read.c:2039
 #, c-format
 msgid "error setting flags for \".sbss\": %s"
 msgstr "\".sbss\" için bayrak atanırken hata: %s"
 
-#: read.c:2038
-msgid "expected comma after size"
+#: read.c:2087
+#, fuzzy
+msgid "expected alignment after size"
 msgstr "boydan sonra virgül beklendi"
 
-#: read.c:2072
-#, c-format
-msgid "alignment too large; %d assumed"
-msgstr "hizalama fazla büyük: %d varsayıldı"
-
-#: read.c:2077
+#: read.c:2101
 msgid "alignment negative; 0 assumed"
 msgstr "hizalama negatif: 0 varsayıldı"
 
-#: read.c:2342
+#: read.c:2332
 #, c-format
 msgid "attempt to redefine pseudo-op `%s' ignored"
 msgstr "`%s' sanal op'unu yeniden tanımlama denemesi yoksayıldı"
 
-#: read.c:2408
+#: read.c:2393
 #, c-format
 msgid "invalid segment \"%s\""
 msgstr "geçersiz bölüm, \"%s\""
 
-#: read.c:2416
+#: read.c:2401
 msgid "only constant offsets supported in absolute section"
 msgstr "kesin bölümde yalnız sabit göreceler destekleniyor"
 
-#: read.c:2456
+#: read.c:2440
 msgid "MRI style ORG pseudo-op not supported"
 msgstr "MRI tarzı ORG sanal op'u desteklenmiyor"
 
-#: read.c:2613
+#: read.c:2596
 #, c-format
 msgid "unrecognized section type `%s'"
 msgstr "bilinmeyen bölüm türü `%s'"
 
-#: read.c:2627
+#: read.c:2610
 msgid "absolute sections are not supported"
 msgstr "kesin bölümler desteklenmiyor"
 
-#: read.c:2642
+#: read.c:2625
 #, c-format
 msgid "unrecognized section command `%s'"
 msgstr "bilinmeyen bölüm komutu `%s'"
 
-#: read.c:2708
-msgid ".endr encountered without preceeding .rept, .irc, or .irp"
-msgstr "öncesinde .rept, .irc veya .irp olmaksızın .endr"
+#: read.c:2689
+#, fuzzy, c-format
+msgid ".end%c encountered without preceeding %s"
+msgstr "öncesinde .%s olmayan .end%s"
 
-#: read.c:2740
+#: read.c:2719
 #, c-format
 msgid "%s without %s"
 msgstr "%2$s olmaksızın %1$s"
 
-#: read.c:2949
+#: read.c:2925
 msgid "unsupported variable size or fill value"
 msgstr "desteklenmeyen deÄŸiÅŸken boyu veya dolgu deÄŸeri"
 
-#: read.c:2974
+#: read.c:2950
 msgid ".space repeat count is zero, ignored"
 msgstr ".space tekrar sayısı sıfır, yoksayıldı"
 
-#: read.c:2976
+#: read.c:2952
 msgid ".space repeat count is negative, ignored"
 msgstr ".space tekrar sayısı sıfır, yoksayıldı"
 
-#: read.c:3005
+#: read.c:2981
 msgid "space allocation too complex in absolute section"
 msgstr "kesin bölümde yer ayırması fazla karmaşık"
 
-#: read.c:3011
+#: read.c:2987
 msgid "space allocation too complex in common section"
 msgstr "ortak bölümde yer ayırması fazla karmaşık"
 
-#: read.c:3099 read.c:4190
+#: read.c:3074 read.c:4152
 #, c-format
 msgid "bad floating literal: %s"
 msgstr "hatalı kayan noktalı sabit: %s"
 
-#: read.c:3172
-#, c-format
-msgid "rest of line ignored; first ignored character is `%c'"
+#: read.c:3139
+#, fuzzy, c-format
+msgid "junk at end of line, first unrecognized character is `%c'"
 msgstr "satırın geri kalanı yoksayıldı; ilk yoksayılan karakter `%c'."
 
-#: read.c:3175
-#, c-format
-msgid "rest of line ignored; first ignored character valued 0x%x"
+#: read.c:3142
+#, fuzzy, c-format
+msgid "junk at end of line, first unrecognized character valued 0x%x"
 msgstr "satırın geri kalanı yoksayıldı; ilk yoksayılan karakterin değeri 0x%x."
 
-#: read.c:3228
+#: read.c:3205
 msgid "missing expression"
 msgstr "eksik ifade"
 
-#: read.c:3404
+#: read.c:3386
 msgid "rva without symbol"
 msgstr "sembol olmaksızın rva"
 
-#: read.c:3530
+#: read.c:3508
 msgid "attempt to store value in absolute section"
 msgstr "kesin bölümde değer saklama denemesi"
 
-#: read.c:3568 read.c:4468
+#: read.c:3546 read.c:4420
 msgid "zero assumed for missing expression"
 msgstr "eksik ifade için sıfır varsayıldı"
 
-#: read.c:3580 read.c:4480 write.c:322
+#: read.c:3558 read.c:4432 write.c:313
 msgid "register value used as expression"
 msgstr "yazmaç değeri ifade olarak kullanıldı"
 
 #. Leading bits contain both 0s & 1s.
-#: read.c:3671
+#: read.c:3636
 #, c-format
 msgid "value 0x%lx truncated to 0x%lx"
 msgstr "0x%lx değeri 0x%lx olarak budandı."
 
-#: read.c:3687
+#: read.c:3652
 #, c-format
 msgid "bignum truncated to %d bytes"
 msgstr "büyüksayı (bignum) %d bayta budandı"
 
-#: read.c:3854
+#: read.c:3819
 msgid "using a bit field width of zero"
 msgstr "bit alan genişliği sıfır kullanılıyor"
 
-#: read.c:3862
+#: read.c:3827
 #, c-format
 msgid "field width \"%s\" too complex for a bitfield"
 msgstr "\"%s\" alan genişliği bit alanı için fazla karmaşık"
 
-#: read.c:3870
+#: read.c:3835
 #, c-format
 msgid "field width %lu too big to fit in %d bytes: truncated to %d bits"
 msgstr "%lu alan genişliği %d bayta sığmak için fazla büyük: %d bite budandı"
 
-#: read.c:3892
+#: read.c:3857
 #, c-format
 msgid "field value \"%s\" too complex for a bitfield"
 msgstr "\"%s\" alan değeri bit alanı için fazla karmaşık"
 
-#: read.c:4018 read.c:4212
+#: read.c:3983 read.c:4174
 msgid "unresolvable or nonpositive repeat count; using 1"
 msgstr "çözümlenemeyen veya pozitif olmayan tekrar sayısı; 1 kullanıldı"
 
-#: read.c:4069
+#: read.c:4032
 #, c-format
 msgid "unknown floating type type '%c'"
 msgstr "bilinmeyen kayan nokta türü '%c'"
 
-#: read.c:4091
+#: read.c:4054
 msgid "floating point constant too large"
 msgstr "kayan nokta sabiti fazla büyük"
 
-#: read.c:4581
+#: read.c:4546
 msgid "strings must be placed into a section"
 msgstr "dizgeler bir bölüm içine yerleştirilmeli"
 
-#: read.c:4631
+#: read.c:4596
 msgid "expected <nn>"
 msgstr "<nn> beklendi"
 
 #. To be compatible with BSD 4.2 as: give the luser a linefeed!!
-#: read.c:4664 read.c:4750
+#: read.c:4629 read.c:4715
 msgid "unterminated string; newline inserted"
 msgstr "sonlanmamış dizge; yenisatır eklendi."
 
-#: read.c:4758
+#: read.c:4723
 msgid "bad escaped character in string"
 msgstr "dizgede hatalı kaçışlı karakter"
 
-#: read.c:4784
+#: read.c:4748
 msgid "expected address expression"
 msgstr "adres ifadesi beklendi"
 
-#: read.c:4804
+#: read.c:4767
 #, c-format
 msgid "symbol \"%s\" undefined; zero assumed"
 msgstr "\"%s\" sembolü tanımsız; sıfır varsayıldı"
 
-#: read.c:4807
+#: read.c:4770
 msgid "some symbol undefined; zero assumed"
 msgstr "bir sembol tanımsız; sıfır varsayıldı"
 
-#: read.c:4824
+#: read.c:4786
 msgid "bad or irreducible absolute expression"
 msgstr "hatalı veya indirgenemeyen kesin ifade"
 
-#: read.c:4867
+#: read.c:4827
 msgid "this string may not contain '\\0'"
 msgstr "bu dizgede '\\0' olamaz"
 
-#: read.c:4904
+#: read.c:4863
 msgid "missing string"
 msgstr "eksik dizge"
 
-#: read.c:5027
+#: read.c:4983
 #, c-format
 msgid ".incbin count zero, ignoring `%s'"
 msgstr ".incbin sayısı sıfır, `%s' yoksayıldı"
 
-#: read.c:5053
+#: read.c:5009
 #, c-format
 msgid "file not found: %s"
 msgstr "dosya bulunamadı: %s"
 
-#: read.c:5067
+#: read.c:5023
 #, c-format
 msgid "seek to end of .incbin file failed `%s'"
 msgstr ".incbin dosyasının sonuna arama başarısız `%s'"
 
-#: read.c:5078
-#, c-format
-msgid "skip (%ld) + count (%ld) larger than file size (%ld)"
+#: read.c:5034
+#, fuzzy, c-format
+msgid "skip (%ld) or count (%ld) invalid for file size (%ld)"
 msgstr "atlama (%ld) + sayı (%ld) dosya boyundan büyük (%ld)"
 
-#: read.c:5085
+#: read.c:5041
 #, c-format
 msgid "could not skip to %ld in file `%s'"
 msgstr "`%2$s' dosyasında %1$ld'ye atlanamadı"
 
-#: read.c:5094
+#: read.c:5050
 #, c-format
 msgid "truncated file `%s', %ld of %ld bytes read"
 msgstr "`%s' dosyası budandı, %ld/%ld bayt okundu"
 
-#: read.c:5257
+#: read.c:5208
 msgid "missing .func"
 msgstr "eksik .func"
 
-#: read.c:5274
+#: read.c:5225
 msgid ".endfunc missing for previous .func"
 msgstr "önceki .func için eksik .endfunc"
 
-#: stabs.c:220 stabs.c:228 stabs.c:236 stabs.c:255
+#: stabs.c:215 stabs.c:223 stabs.c:231 stabs.c:250
 #, c-format
 msgid ".stab%c: missing comma"
 msgstr ".stab%c: eksik virgül"
@@ -11579,196 +12814,411 @@ msgstr ".stab%c: eksik virgül"
 #. This could happen for example with a source file with a huge
 #. number of lines.  The only cure is to use a different debug
 #. format, probably DWARF.
-#: stabs.c:248
+#: stabs.c:243
 #, c-format
 msgid ".stab%c: description field '%x' too big, try a different debug format"
 msgstr ".stab%c: '%x' tanım alanı fazla büyük, başka bir hata ayıklama biçemi deneyin"
 
-#: stabs.c:433
+#: stabs.c:426
 msgid "comma missing in .xstabs"
 msgstr ".xstabs içinde eksik virgül"
 
-#: subsegs.c:377
+#: subsegs.c:373
 #, c-format
 msgid "attempt to switch to nonexistent segment \"%s\""
 msgstr "Olmayan \"%s\" bölümüne geçiş denemesi"
 
-#: symbols.c:318
+#: symbols.c:309
 #, c-format
 msgid "cannot define symbol `%s' in absolute section"
 msgstr "kesin bölüm içinde `%s' sembolü tanımlanamaz"
 
-#: symbols.c:452
+#: symbols.c:443
 #, c-format
 msgid "symbol `%s' is already defined as \"%s\"/%s%ld"
 msgstr "\"%s\" sembolü zaten \"%s\"/%s%ld olarak tanımlanmış."
 
-#: symbols.c:529 symbols.c:536
+#: symbols.c:519 symbols.c:526
 #, c-format
 msgid "inserting \"%s\" into symbol table failed: %s"
 msgstr "sembol tablosuna \"%s\" eklenmesi başarısız: %s"
 
-#: symbols.c:874 symbols.c:878
+#: symbols.c:840 symbols.c:844
 #, c-format
 msgid "undefined symbol `%s' in operation"
 msgstr "işlemde tanımsız %s sembolü"
 
-#: symbols.c:885
+#: symbols.c:851
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s'"
 msgstr "`%s' ve `%s' üzerinde işlem için geçersiz bölümler"
 
-#: symbols.c:889
+#: symbols.c:855
 #, c-format
 msgid "invalid section for operation on `%s'"
 msgstr "`%s' üzerinde işlem için geçersiz bölüm"
 
-#: symbols.c:897 symbols.c:900
+#: symbols.c:863 symbols.c:866
 #, c-format
 msgid "undefined symbol `%s' in operation setting `%s'"
 msgstr "işlemde tanımsız %s sembolü %s'i atıyor"
 
-#: symbols.c:907
+#: symbols.c:873
 #, c-format
 msgid "invalid sections for operation on `%s' and `%s' setting `%s'"
 msgstr "`%s' ve `%s' üzerinde ve `%s'i atayan işlem için geçersiz bölümler"
 
-#: symbols.c:911
+#: symbols.c:877
 #, c-format
 msgid "invalid section for operation on `%s' setting `%s'"
 msgstr "`%s' üzerinde `%s'i atayan işlem için geçersiz bölüm"
 
-#: symbols.c:964
+#: symbols.c:929
 #, c-format
 msgid "symbol definition loop encountered at `%s'"
 msgstr "%s'de sembol tanım döngüsü bulundu"
 
-#: symbols.c:1193
+#: symbols.c:1162
 #, c-format
 msgid "division by zero when setting `%s'"
 msgstr "%s atanırken sıfırla bölüm"
 
-#: symbols.c:1280 write.c:2008
+#: symbols.c:1249 write.c:1977
 #, c-format
 msgid "can't resolve value for symbol `%s'"
 msgstr "\"%s\" sembolü için değer çözümlenemedi"
 
-#: symbols.c:1674
+#: symbols.c:1637
 #, c-format
 msgid "\"%d\" (instance number %d of a %s label)"
 msgstr "\"%1$d\" (%3$s etiketinde gerçekleme sayısı %2$d)"
 
-#: symbols.c:1711
+#: symbols.c:1673
 #, c-format
 msgid "attempt to get value of unresolved symbol `%s'"
 msgstr "tanımsız %s sembolünün değerini alma denemesi"
 
-#: symbols.c:1971
+#: symbols.c:1916
 msgid "section symbols are already global"
 msgstr "bölüm sembolleri zaten evrensel"
 
-#: symbols.c:2014
+#: symbols.c:1961
 #, c-format
 msgid "Accessing function `%s' as thread-local object"
 msgstr "`%s' işlevine iplikçiğe yerel nesne olarak erişildi"
 
-#: symbols.c:2018
+#: symbols.c:1965
 #, c-format
 msgid "Accessing `%s' as thread-local object"
 msgstr "`%s'e iplikçiğe yerel nesne olarak erişildi"
 
-#: write.c:215
+#: write.c:208
 #, c-format
 msgid "field fx_size too small to hold %d"
 msgstr "fx_size alanı %d'i tutmak için çok küçük"
 
-#: write.c:349
+#: write.c:340
 msgid "rva not supported"
 msgstr "rva desteklenmiyor"
 
-#: write.c:570
+#: write.c:540
 #, c-format
 msgid "attempt to .org/.space backwards? (%ld)"
 msgstr "Geriye .org/.space denemesi? (%ld)"
 
-#: write.c:1002 write.c:1074
+#: write.c:966 write.c:1038
 msgid "relocation out of range"
 msgstr "yerdeğişim kapsam dışı"
 
-#: write.c:1005 write.c:1077
+#: write.c:969 write.c:1041
 #, c-format
 msgid "%s:%u: bad return from bfd_install_relocation: %x"
 msgstr "%s:%u: bfd_install_relocation'dan hatalı geri dönüş: %x"
 
-#: write.c:1057
+#: write.c:1021
 msgid "internal error: fixup not contained within frag"
 msgstr "iç hata: düzeltme parça içinde değil"
 
-#: write.c:1164 write.c:1188
+#: write.c:1127 write.c:1151
 #, c-format
 msgid "FATAL: Can't write %s"
 msgstr "ÖLÜMCÜL: %s yazılamadı"
 
-#: write.c:1220
+#: write.c:1183
 msgid "cannot write to output file"
 msgstr "çıktı dosyasına yazılamadı."
 
-#: write.c:1477
+#: write.c:1440
 #, c-format
 msgid "%d error%s, %d warning%s, generating bad object file"
 msgstr "%d hata%s, %d uyarı%s, hatalı nesne dosyası üretiliyor"
 
-#: write.c:1484
+#: write.c:1447
 #, c-format
 msgid "%d error%s, %d warning%s, no object file generated"
 msgstr "%d hata%s, %d uyarı%s, nesne dosyası üretilmedi"
 
-#: write.c:1945
+#: write.c:1918
 #, c-format
 msgid "local label `%s' is not defined"
 msgstr "yerel %s etiketi tanımsız"
 
-#: write.c:2244
+#: write.c:1931
+#, c-format
+msgid "`%s' can't be equated to common symbol"
+msgstr ""
+
+#: write.c:2209
 #, c-format
 msgid "alignment padding (%lu bytes) not a multiple of %ld"
 msgstr "hizalama dolgusu (%lu bayt) %ld'nin katı değil"
 
-#: write.c:2361
+#: write.c:2326
 #, c-format
 msgid ".word %s-%s+%s didn't fit"
 msgstr ".word %s-%s+%s sığmadı"
 
-#: write.c:2446
+#: write.c:2413
 msgid "attempt to move .org backwards"
 msgstr ".org'u geriye taşıma denemesi"
 
-#: write.c:2474
+#: write.c:2441
 msgid ".space specifies non-absolute value"
 msgstr ".space kesin olmayan deÄŸer belirtiyor"
 
-#: write.c:2481
+#: write.c:2448
 msgid ".space or .fill with negative value, ignored"
 msgstr "negatif değerli .space veya .fill; yoksayıldı"
 
-#: write.c:2773
+#: write.c:2731
 #, c-format
 msgid "value of %s too large for field of %d bytes at %s"
 msgstr "%s değeri %d baytlık alan için %s'de çok büyük"
 
-#: write.c:2785
+#: write.c:2743
 #, c-format
 msgid "signed .word overflow; switch may be too large; %ld at 0x%lx"
 msgstr "signed .word taşması; bayrak çok büyük olabilir; 0x%2$lx de %1$ld"
 
+#~ msgid "Can't close %s: %s"
+#~ msgstr "%s kapatılamadı: %s"
+
+#~ msgid "Missing size expression"
+#~ msgstr "Boyut ifadesi eksik"
+
+#~ msgid "lcomm length (%d.) <0! Ignored."
+#~ msgstr "lcomm uzunluğu (%d.) <0! Yoksayıldı."
+
+#~ msgid "Symbol %s already defined"
+#~ msgstr "Sembol %s daha önce tanımlanmış"
+
+#~ msgid "expected comma after symbol-name"
+#~ msgstr "Sembol adından sonra virgül beklendi"
+
+#~ msgid "length of .comm \"%s\" is already %ld; not changed to %ld"
+#~ msgstr ".comm \"%s\" uzunluÄŸu zaten %ld. %ld olarak deÄŸiÅŸtirilmedi."
+
+#~ msgid "common alignment negative; 0 assumed"
+#~ msgstr "Ortak hizalama negatif; 0 varsayıldı"
+
+#~ msgid "common alignment not a power of 2"
+#~ msgstr "Ortak hizalama 2'nin kuvveti deÄŸil"
+
+#~ msgid "ignoring new section group for %s"
+#~ msgstr "%s için yeni bölüm grubu yoksayıldı"
+
+#~ msgid ""
+#~ "g++ wrote an extern reference to `%s' as a routine.\n"
+#~ "I will fix it, but I hope that it was note really a routine."
+#~ msgstr ""
+#~ "g++, `%s'a extern referansını bir işlev tanımı olarak yazdı.\n"
+#~ "Bu düzeltildi, fakat gerçekten bir işlev ise, hatalı sonuç verecek."
+
+#~ msgid "File overrides no-base-register option."
+#~ msgstr "Dosya no-base-register seçeneğini etkisizleştirdi"
+
+#~ msgid "floating point register expected"
+#~ msgstr "Kayan nokta yazmacı beklendi"
+
+#~ msgid "immediate value cannot be used to set this field"
+#~ msgstr "şimdiki değer, bu alanı değere atamak için kullanılamaz"
+
+#~ msgid "use old ABI (ELF only)"
+#~ msgstr "eski ABI'yi kullanır (yalnız ELF)"
+
+#~ msgid "expression possibly out of 8-bit range"
+#~ msgstr "ifade 8-bitlik aralık dışında olabilir"
+
+#~ msgid "Invalid register list for ldm/stm)\n"
+#~ msgstr "ldm/stm için geçersiz yazmaç listesi)\n"
+
+#~ msgid "unimplemented segment type %d in operand"
+#~ msgstr "işlenende desteklenmeyen bölüm türü %d"
+
+#~ msgid "Additional NOP may be necessary to workaround Itanium processor A/B step errata"
+#~ msgstr "Itanium işlemcisi A/B adım hatasını bertaraf etmek için ek NOP gerekebilir"
+
+#~ msgid "  -relax                 create linker relaxable code\n"
+#~ msgstr "  -relax                 bağlayıcı tarafından gevşetilebilen kod üretir\n"
+
+#~ msgid "  -cpu-desc              provide runtime cpu description file\n"
+#~ msgstr "  -cpu-desc              çalışma zamanı cpu tasvir dosyası üretir\n"
+
+#~ msgid "unrecognized option `%s'"
+#~ msgstr "bilinmeyen seçenek: `%s'"
+
+#~ msgid "Branch %s is always false (nop)"
+#~ msgstr "%s dalı her zaman yanlış (nop)"
+
+#~ msgid "Branch likely %s is always false"
+#~ msgstr "Olası %s dalı her zaman yanlış"
+
+#~ msgid "load/store address overflow (max 32 bits)"
+#~ msgstr "adres yükle/sakla taşması (maksimum 32 bit)"
+
+#~ msgid "-G may not be used with embedded PIC code"
+#~ msgstr "-G gömülü PIC kodu ile kullanılamaz"
+
+#~ msgid "-G is not supported for this configuration"
+#~ msgstr "-G bu ayarlarda desteklenmiyor"
+
+#~ msgid "-G may not be used with SVR4 or embedded PIC code"
+#~ msgstr "-G SVR4 veya gömülü PIC kodu ile kullanılamaz"
+
+#~ msgid "Unmatched %%hi reloc"
+#~ msgstr "EÅŸleÅŸmeyen %%hi yerdeÄŸiÅŸimi"
+
+#~ msgid "Invalid PC relative reloc"
+#~ msgstr "Geçersiz PC göreli yerdeğişim"
+
+#~ msgid "%08lx  UNDEFINED\n"
+#~ msgstr "%08lx  TANIMSIZ\n"
+
+#~ msgid "No read only data section in this object file format"
+#~ msgstr "Bu nesne dosyası biçeminde salt okunur veri bölümü yok"
+
+#~ msgid "Global pointers not supported; recompile -G 0"
+#~ msgstr "Evrensel imleyiciler desteklenmiyor; -G 0 ile yeniden derleyin"
+
+#~ msgid "AT used after \".set noat\" or macro used after \".set nomacro\""
+#~ msgstr ""
+#~ "\".set noat\"dan sonra kullanılan AT veya \".set nomacro\"dan sonra\n"
+#~ "kullanılan makro"
+
+#~ msgid "Double check fx_r_type in tc-mips.c:tc_gen_reloc"
+#~ msgstr "tc-mips.c:tc_gen_reloc içinde fx_r_type'ı tekrar kontrol edin"
+
+#~ msgid "operand out of range (%s not between %ld and %ld)"
+#~ msgstr "işlenen kapsam dışında (%s, %ld ve %ld arasında değil)"
+
+#~ msgid "the linker will not handle this relocation correctly (1)"
+#~ msgstr "bağlayıcı bu yerdeğişimi doğru uygulayamaz (1)"
+
+#~ msgid "-mcoff-version={0|1|2}    Select COFF version\n"
+#~ msgstr "-mcoff-version={0|1|2}    COFF sürümünü belirtir\n"
+
+#~ msgid "unknown command line option: -%c%s\n"
+#~ msgstr "bilinmeyen komut satırı seçeneği: -%c%s\n"
+
+#~ msgid "'--literal-section-name' is deprecated; use '--rename-section .literal=NEWNAME'"
+#~ msgstr "'--literal-section-name' eski; '--rename-section .literal=YENİAD' kullanın"
+
+#~ msgid "'--text-section-name' is deprecated; use '--rename-section .text=NEWNAME'"
+#~ msgstr "'--text-section-name' eski; '--rename-section .text=YENİİSİM' kullanın"
+
+#~ msgid "'--data-section-name' is deprecated; use '--rename-section .data=NEWNAME'"
+#~ msgstr "'--data-section-name' eski; '--rename-section .data=YENİİSİM' kullanın"
+
+#~ msgid "'--bss-section-name' is deprecated; use '--rename-section .bss=NEWNAME'"
+#~ msgstr "'--bss-section-name' eski; '--rename-section .bss=YENİİSİM' kullanın"
+
+#~ msgid "register number for `%s' is not a constant"
+#~ msgstr "`%s' için yazmaç sayısı sabit değil"
+
+#~ msgid "operand %d not properly aligned for '%s'"
+#~ msgstr "'%2$s' için %1$d işleneni doğru hizalanmamış"
+
+#~ msgid "operand %d not in immediate table for '%s'"
+#~ msgstr "'%2$s' için %1$d işleneni şimdiki tablosunda değil"
+
+#~ msgid "operand %d too small for '%s'"
+#~ msgstr "'%2$s' için %1$d işleneni çok küçük"
+
+#~ msgid "instruction fragment may contain data"
+#~ msgstr "İşlem parçacığı veri içerebilir"
+
+#~ msgid "invalid relocation operand %i on '%s'"
+#~ msgstr "'%2$s' içinde geçersiz yer değişim işleneni %1$i"
+
+#~ msgid "instruction with constant operands does not fit without widening"
+#~ msgstr "sabit işlenenli işlem, genişletme olmadan sığmıyor"
+
+#~ msgid "instruction's constant operands do not fit"
+#~ msgstr "işlemin sabit işlenenleri sığmıyor"
+
+#~ msgid "opcode 'OR' unavailable in this configuration"
+#~ msgstr "'OR' opkodu bu ayarlarda desteklenmemektedir"
+
+#~ msgid "invalid %d-byte NOP requested"
+#~ msgstr "geçersiz %d baytlık NOP istendi"
+
+#~ msgid "get_expanded_loop_offset: undefined opcode"
+#~ msgstr "get_expanded_loop_offset: tanımsız opkod"
+
+#~ msgid "undefined @ suffix '%s', expected '%s'"
+#~ msgstr "tanımsız @ soneki '%s', '%s' beklendi"
+
+#~ msgid "invalid operand relocation for '%s' instruction"
+#~ msgstr "'%s' işlemi için geçersiz işlenen yerdeğişimi"
+
+#~ msgid "invalid relocation for operand %d in '%s' instruction"
+#~ msgstr "'%2$s' işleminin %1$d işleneni için geçersiz yerdeğişim"
+
+#~ msgid "non-PCREL relocation operand %d for '%s': %s"
+#~ msgstr "'%2$s' için PCREL olmayan yerdeğişim işleneni %1$d: %3$s"
+
+#~ msgid "get_text_align_power: argument too large"
+#~ msgstr "get_text_align_power: argüman fazla büyük"
+
+#~ msgid "invalid opcode for RELAX_ALIGN_NEXT_OPCODE"
+#~ msgstr "RELAX_ALIGN_NEXT_OPCODE için geçersiz opkod"
+
+#~ msgid "cannot continue"
+#~ msgstr "devam edilemez"
+
+#~ msgid "expected loop opcode in relax align next target"
+#~ msgstr "'gevşet, sonraki hedefi hizala' içinde döngü opkodu beklendi"
+
+#~ msgid "expected align_code or RELAX_ALIGN_NEXT_OPCODE"
+#~ msgstr "align_code veya RELAX_ALIGN_NEXT_OPCODE beklendi"
+
+#~ msgid "internal error aligning"
+#~ msgstr "hizalamada iç hata"
+
+#~ msgid "loop relaxation specification does not correspond"
+#~ msgstr "döngü genişletme bildirimi eşleşmiyor"
+
+#~ msgid "inlining literal pool; specify location with .literal_position."
+#~ msgstr "sabit havuz 'inline' haline getirildi; yerini .literal_position ile bildirin"
+
+#~ msgid "operand %s0x%x out of range"
+#~ msgstr "%s0x%x işleneni kapsam dışı"
+
+#~ msgid "BSS length (%d) < 0 ignored"
+#~ msgstr "BSS uzunluğu (%d) <0 yoksayıldı."
+
+#~ msgid "alignment too large; %d assumed"
+#~ msgstr "hizalama fazla büyük: %d varsayıldı"
+
+#~ msgid ".endr encountered without preceeding .rept, .irc, or .irp"
+#~ msgstr "öncesinde .rept, .irc veya .irp olmaksızın .endr"
+
 #~ msgid "subsegment index too high"
 #~ msgstr "altbölüm indeksi fazla yüksek"
 
 #~ msgid ".COMMon length (%d.) <0! Ignored."
 #~ msgstr ".COMM ortak uzunluk (%d.) <0! Yoksayıldı."
 
-#~ msgid "operand out of range: %d"
-#~ msgstr "işlenen aralık dışı: %d"
-
 #~ msgid "expect :8 or :16 here"
 #~ msgstr "Burada :8 veya :16 beklendi"
 
@@ -11778,9 +13228,6 @@ msgstr "signed .word taşması; bayrak çok büyük olabilir; 0x%2$lx de %1$ld"
 #~ msgid "i860_number_to_field\n"
 #~ msgstr "i860_number_to_field\n"
 
-#~ msgid "callj to difference of two symbols"
-#~ msgstr "iki sembolün farkına callj"
-
 #~ msgid "md_number_to_disp not defined"
 #~ msgstr "md_number_to_disp tanımlanmamış"
 
@@ -11805,9 +13252,6 @@ msgstr "signed .word taşması; bayrak çok büyük olabilir; 0x%2$lx de %1$ld"
 #~ msgid "invalid architecture -mtune=%s"
 #~ msgstr "geçersiz yapı -mtune=%s"
 
-#~ msgid "invalid architecture -march=%s"
-#~ msgstr "geçersiz yapı -march=%s"
-
 #~ msgid "invalid architecture -mcpu=%s"
 #~ msgstr "geçersiz yapı -mcpu=%s"
 
@@ -11889,9 +13333,6 @@ msgstr "signed .word taşması; bayrak çok büyük olabilir; 0x%2$lx de %1$ld"
 #~ msgid "End of file not at start of line.\n"
 #~ msgstr "Dosyasonu satır başında değil.\n"
 
-#~ msgid "Illegal base character %c.\n"
-#~ msgstr "Geçersiz temel karakter %c.\n"
-
 #~ msgid "radix is %c must be one of b, q, d or h"
 #~ msgstr "radix, %c b,q,d veya h'den biri olmalı"
 
diff --git a/gas/read.c b/gas/read.c
index f97bd25d2fb6..0485d72dec67 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -1,6 +1,7 @@
 /* read.c - read a source file -
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
+   Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
 
@@ -16,17 +17,13 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+02110-1301, USA.  */
 
-#if 0
-/* If your chars aren't 8 bits, you will change this a bit.
+/* If your chars aren't 8 bits, you will change this a bit (eg. to 0xFF).
    But then, GNU isn't spozed to run on your machine anyway.
    (RMS is so shortsighted sometimes.)  */
-#define MASK_CHAR (0xFF)
-#else
 #define MASK_CHAR ((int)(unsigned char) -1)
-#endif
 
 /* This is the largest known floating point format (for now). It will
    grow when we do 4361 style flonums.  */
@@ -75,7 +72,6 @@ die horribly;
 #endif
 
 #ifndef LEX_AT
-/* The m88k unfortunately uses @ as a label beginner.  */
 #define LEX_AT 0
 #endif
 
@@ -101,7 +97,6 @@ die horribly;
 #endif
 
 #ifndef LEX_DOLLAR
-/* The a29k assembler does not permits labels to start with $.  */
 #define LEX_DOLLAR 3
 #endif
 
@@ -214,13 +209,17 @@ static int dwarf_file_string;
 #endif
 #endif
 
+static void do_s_func (int end_p, const char *default_prefix);
 static void do_align (int, char *, int, int);
 static void s_align (int, int);
+static void s_altmacro (int);
+static void s_bad_end (int);
 static int hex_float (int, char *);
 static segT get_known_segmented_expression (expressionS * expP);
 static void pobegin (void);
 static int get_line_sb (sb *);
 static void generate_file_debug (void);
+static char *_find_end_of_line (char *, int, int);
 
 void
 read_begin (void)
@@ -244,6 +243,22 @@ read_begin (void)
     lex_type['?'] = 3;
 }
 
+#ifndef TC_ADDRESS_BYTES
+#define TC_ADDRESS_BYTES address_bytes
+
+static inline int
+address_bytes (void)
+{
+  /* Choose smallest of 1, 2, 4, 8 bytes that is large enough to
+     contain an address.  */
+  int n = (stdoutput->arch_info->bits_per_address - 1) / 8;
+  n |= n >> 1;
+  n |= n >> 2;
+  n += 1;
+  return n;
+}
+#endif
+
 /* Set up pseudo-op tables.  */
 
 static struct hash_control *po_hash;
@@ -251,6 +266,7 @@ static struct hash_control *po_hash;
 static const pseudo_typeS potable[] = {
   {"abort", s_abort, 0},
   {"align", s_align_ptwo, 0},
+  {"altmacro", s_altmacro, 1},
   {"ascii", stringer, 0},
   {"asciz", stringer, 1},
   {"balign", s_align_bytes, 0},
@@ -263,6 +279,9 @@ static const pseudo_typeS potable[] = {
   {"common.s", s_mri_common, 1},
   {"data", s_data, 0},
   {"dc", cons, 2},
+#ifdef TC_ADDRESS_BYTES
+  {"dc.a", cons, 0},
+#endif
   {"dc.b", cons, 1},
   {"dc.d", float_cons, 'd'},
   {"dc.l", cons, 4},
@@ -299,11 +318,14 @@ static const pseudo_typeS potable[] = {
   {"endc", s_endif, 0},
   {"endfunc", s_func, 1},
   {"endif", s_endif, 0},
-  {"endr", s_bad_endr, 0},
+  {"endm", s_bad_end, 0},
+  {"endr", s_bad_end, 1},
 /* endef  */
   {"equ", s_set, 0},
   {"equiv", s_set, 1},
+  {"eqv", s_set, -1},
   {"err", s_err, 0},
+  {"error", s_errwarn, 1},
   {"exitm", s_mexit, 0},
 /* extend  */
   {"extern", s_ignore, 0},	/* We treat all undef as ext.  */
@@ -319,6 +341,7 @@ static const pseudo_typeS potable[] = {
   {"globl", s_globl, 0},
   {"hword", cons, 2},
   {"if", s_if, (int) O_ne},
+  {"ifb", s_ifb, 1},
   {"ifc", s_ifc, 0},
   {"ifdef", s_ifdef, 0},
   {"ifeq", s_if, (int) O_eq},
@@ -327,6 +350,7 @@ static const pseudo_typeS potable[] = {
   {"ifgt", s_if, (int) O_gt},
   {"ifle", s_if, (int) O_le},
   {"iflt", s_if, (int) O_lt},
+  {"ifnb", s_ifb, 0},
   {"ifnc", s_ifc, 1},
   {"ifndef", s_ifdef, 1},
   {"ifne", s_if, (int) O_ne},
@@ -351,6 +375,7 @@ static const pseudo_typeS potable[] = {
   {"mri", s_mri, 0},
   {".mri", s_mri, 0},	/* Special case so .mri works in MRI mode.  */
   {"name", s_ignore, 0},
+  {"noaltmacro", s_altmacro, 0},
   {"noformat", s_ignore, 0},
   {"nolist", listing_list, 0},	/* Turn listing off.  */
   {"nopage", listing_nopage, 0},
@@ -408,11 +433,34 @@ static const pseudo_typeS potable[] = {
   {"xdef", s_globl, 0},
   {"xref", s_ignore, 0},
   {"xstabs", s_xstab, 's'},
+  {"warning", s_errwarn, 0},
+  {"weakref", s_weakref, 0},
   {"word", cons, 2},
   {"zero", s_space, 0},
   {NULL, NULL, 0}			/* End sentinel.  */
 };
 
+static offsetT
+get_absolute_expr (expressionS *exp)
+{
+  expression_and_evaluate (exp);
+  if (exp->X_op != O_constant)
+    {
+      if (exp->X_op != O_absent)
+	as_bad (_("bad or irreducible absolute expression"));
+      exp->X_add_number = 0;
+    }
+  return exp->X_add_number;
+}
+
+offsetT
+get_absolute_expression (void)
+{
+  expressionS exp;
+
+  return get_absolute_expr (&exp);
+}
+
 static int pop_override_ok = 0;
 static const char *pop_table_name;
 
@@ -470,9 +518,11 @@ pobegin (void)
 #define HANDLE_CONDITIONAL_ASSEMBLY()					\
   if (ignore_input ())							\
     {									\
-      while (!is_end_of_line[(unsigned char) *input_line_pointer++])	\
-	if (input_line_pointer == buffer_limit)				\
-	  break;							\
+      char *eol = find_end_of_line (input_line_pointer, flag_m68k_mri);	\
+      input_line_pointer = (input_line_pointer <= buffer_limit		\
+			    && eol >= buffer_limit)			\
+			   ? buffer_limit				\
+			   : eol + 1;					\
       continue;								\
     }
 
@@ -495,6 +545,32 @@ scrub_from_string (char *buf, int buflen)
   return copy;
 }
 
+/* Helper function of read_a_source_file, which tries to expand a macro.  */
+static int
+try_macro (char term, const char *line)
+{
+  sb out;
+  const char *err;
+  macro_entry *macro;
+
+  if (check_macro (line, &out, &err, &macro))
+    {
+      if (err != NULL)
+	as_bad ("%s", err);
+      *input_line_pointer++ = term;
+      input_scrub_include_sb (&out,
+			      input_line_pointer, 1);
+      sb_kill (&out);
+      buffer_limit =
+	input_scrub_next_buffer (&input_line_pointer);
+#ifdef md_macro_info
+      md_macro_info (macro);
+#endif
+      return 1;
+    }
+  return 0;
+}
+
 /* We read the file, putting things into a web that represents what we
    have been reading.  */
 void
@@ -522,6 +598,13 @@ read_a_source_file (char *name)
 
   while ((buffer_limit = input_scrub_next_buffer (&input_line_pointer)) != 0)
     {				/* We have another line to parse.  */
+#ifndef NO_LISTING
+      /* In order to avoid listing macro expansion lines with labels
+	 multiple times, keep track of which line was last issued.  */
+      static char *last_eol;
+
+      last_eol = NULL;
+#endif
       know (buffer_limit[-1] == '\n');	/* Must have a sentinel.  */
 
       while (input_line_pointer < buffer_limit)
@@ -637,21 +720,23 @@ read_a_source_file (char *name)
 		  int len;
 
 		  /* Find the end of the current expanded macro line.  */
-		  for (s = input_line_pointer - 1; *s; ++s)
-		    if (is_end_of_line[(unsigned char) *s])
-		      break;
+		  s = find_end_of_line (input_line_pointer - 1, flag_m68k_mri);
 
-		  /* Copy it for safe keeping.  Also give an indication of
-		     how much macro nesting is involved at this point.  */
-		  len = s - (input_line_pointer - 1);
-		  copy = (char *) xmalloc (len + macro_nest + 2);
-		  memset (copy, '>', macro_nest);
-		  copy[macro_nest] = ' ';
-		  memcpy (copy + macro_nest + 1, input_line_pointer - 1, len);
-		  copy[macro_nest + 1 + len] = '\0';
-
-		  /* Install the line with the listing facility.  */
-		  listing_newline (copy);
+		  if (s != last_eol)
+		    {
+		      last_eol = s;
+		      /* Copy it for safe keeping.  Also give an indication of
+			 how much macro nesting is involved at this point.  */
+		      len = s - (input_line_pointer - 1);
+		      copy = (char *) xmalloc (len + macro_nest + 2);
+		      memset (copy, '>', macro_nest);
+		      copy[macro_nest] = ' ';
+		      memcpy (copy + macro_nest + 1, input_line_pointer - 1, len);
+		      copy[macro_nest + 1 + len] = '\0';
+
+		      /* Install the line with the listing facility.  */
+		      listing_newline (copy);
+		    }
 		}
 	      else
 		listing_newline (NULL);
@@ -704,13 +789,21 @@ read_a_source_file (char *name)
 		  /* Input_line_pointer->after ':'.  */
 		  SKIP_WHITESPACE ();
 		}
-	      else if (c == '='
-		       || ((c == ' ' || c == '\t')
-			   && input_line_pointer[1] == '='
+              else if (input_line_pointer[1] == '='
+		       && (c == '='
+			   || ((c == ' ' || c == '\t')
+			       && input_line_pointer[2] == '=')))
+		{
+		  equals (s, -1);
+		  demand_empty_rest_of_line ();
+		}
+              else if ((c == '='
+                       || ((c == ' ' || c == '\t')
+                            && input_line_pointer[1] == '='))
 #ifdef TC_EQUAL_IN_INSN
-			   && !TC_EQUAL_IN_INSN (c, input_line_pointer)
+                           && !TC_EQUAL_IN_INSN (c, s)
 #endif
-			   ))
+                           )
 		{
 		  equals (s, 1);
 		  demand_empty_rest_of_line ();
@@ -736,8 +829,8 @@ read_a_source_file (char *name)
 #endif
 		  if (NO_PSEUDO_DOT || flag_m68k_mri)
 		    {
-		      /* The MRI assembler and the m88k use pseudo-ops
-			 without a period.  */
+		      /* The MRI assembler uses pseudo-ops without
+			 a period.  */
 		      pop = (pseudo_typeS *) hash_find (po_hash, s);
 		      if (pop != NULL && pop->poc_handler == NULL)
 			pop = NULL;
@@ -791,9 +884,18 @@ read_a_source_file (char *name)
 		      /* Print the error msg now, while we still can.  */
 		      if (pop == NULL)
 			{
-			  as_bad (_("unknown pseudo-op: `%s'"), s);
+			  char *end = input_line_pointer;
+
 			  *input_line_pointer = c;
 			  s_ignore (0);
+			  c = *--input_line_pointer;
+			  *input_line_pointer = '\0';
+			  if (! macro_defined || ! try_macro (c, s))
+			    {
+			      *end = '\0';
+			      as_bad (_("unknown pseudo-op: `%s'"), s);
+			      *input_line_pointer++ = c;
+			    }
 			  continue;
 			}
 
@@ -816,61 +918,17 @@ read_a_source_file (char *name)
 		    }
 		  else
 		    {
-		      int inquote = 0;
-#ifdef QUOTES_IN_INSN
-		      int inescape = 0;
-#endif
-
 		      /* WARNING: c has char, which may be end-of-line.  */
 		      /* Also: input_line_pointer->`\0` where c was.  */
 		      *input_line_pointer = c;
-		      while (!is_end_of_line[(unsigned char) *input_line_pointer]
-			     || inquote
-#ifdef TC_EOL_IN_INSN
-			     || TC_EOL_IN_INSN (input_line_pointer)
-#endif
-			     )
-			{
-			  if (flag_m68k_mri && *input_line_pointer == '\'')
-			    inquote = !inquote;
-#ifdef QUOTES_IN_INSN
-			  if (inescape)
-			    inescape = 0;
-			  else if (*input_line_pointer == '"')
-			    inquote = !inquote;
-			  else if (*input_line_pointer == '\\')
-			    inescape = 1;
-#endif
-			  input_line_pointer++;
-			}
-
+		      input_line_pointer = _find_end_of_line (input_line_pointer, flag_m68k_mri, 1);
 		      c = *input_line_pointer;
 		      *input_line_pointer = '\0';
 
 		      generate_lineno_debug ();
 
-		      if (macro_defined)
-			{
-			  sb out;
-			  const char *err;
-			  macro_entry *macro;
-
-			  if (check_macro (s, &out, &err, &macro))
-			    {
-			      if (err != NULL)
-				as_bad ("%s", err);
-			      *input_line_pointer++ = c;
-			      input_scrub_include_sb (&out,
-						      input_line_pointer, 1);
-			      sb_kill (&out);
-			      buffer_limit =
-				input_scrub_next_buffer (&input_line_pointer);
-#ifdef md_macro_info
-			      md_macro_info (macro);
-#endif
-			      continue;
-			    }
-			}
+		      if (macro_defined && try_macro (c, s))
+			continue;
 
 		      if (mri_pending_align)
 			{
@@ -1077,6 +1135,29 @@ read_a_source_file (char *name)
 #endif
 }
 
+/* Convert O_constant expression EXP into the equivalent O_big representation.
+   Take the sign of the number from X_unsigned rather than X_add_number.  */
+
+static void
+convert_to_bignum (expressionS *exp)
+{
+  valueT value;
+  unsigned int i;
+
+  value = exp->X_add_number;
+  for (i = 0; i < sizeof (exp->X_add_number) / CHARS_PER_LITTLENUM; i++)
+    {
+      generic_bignum[i] = value & LITTLENUM_MASK;
+      value >>= LITTLENUM_NUMBER_OF_BITS;
+    }
+  /* Add a sequence of sign bits if the top bit of X_add_number is not
+     the sign of the original value.  */
+  if ((exp->X_add_number < 0) != !exp->X_unsigned)
+    generic_bignum[i++] = exp->X_unsigned ? 0 : LITTLENUM_MASK;
+  exp->X_op = O_big;
+  exp->X_add_number = i;
+}
+
 /* For most MRI pseudo-ops, the line actually ends at the first
    nonquoted space.  This function looks for that point, stuffs a null
    in, and sets *STOPCP to the character that used to be there, and
@@ -1155,6 +1236,9 @@ do_align (int n, char *fill, int len, int max)
       len = 0;
     }
 
+#ifdef md_flush_pending_output
+  md_flush_pending_output ();
+#endif
 #ifdef md_do_align
   md_do_align (n, fill, len, max, just_record_alignment);
 #endif
@@ -1187,10 +1271,13 @@ do_align (int n, char *fill, int len, int max)
    fill pattern.  BYTES_P is non-zero if the alignment value should be
    interpreted as the byte boundary, rather than the power of 2.  */
 
+#define ALIGN_LIMIT (stdoutput->arch_info->bits_per_address - 1)
+
 static void
 s_align (int arg, int bytes_p)
 {
-  register unsigned int align;
+  unsigned int align_limit = ALIGN_LIMIT;
+  unsigned int align;
   char *stop = NULL;
   char stopc;
   offsetT fill = 0;
@@ -1229,9 +1316,9 @@ s_align (int arg, int bytes_p)
 	}
     }
 
-  if (align > 15)
+  if (align > align_limit)
     {
-      align = 15;
+      align = align_limit;
       as_warn (_("alignment too large: %u assumed"), align);
     }
 
@@ -1317,6 +1404,15 @@ s_align_ptwo (int arg)
   s_align (arg, 0);
 }
 
+/* Switch in and out of alternate macro mode.  */
+
+void
+s_altmacro (int on)
+{
+  demand_empty_rest_of_line ();
+  macro_set_alternate (on);
+}
+
 symbolS *
 s_comm_internal (int param,
 		 symbolS *(*comm_parse_extra) (int, symbolS *, addressT))
@@ -1342,7 +1438,7 @@ s_comm_internal (int param,
   if (name == p)
     {
       as_bad (_("expected symbol name"));
-      discard_rest_of_line ();
+      ignore_rest_of_line ();
       goto out;
     }
 
@@ -1353,35 +1449,43 @@ s_comm_internal (int param,
   if (*input_line_pointer == ',')
     input_line_pointer++;
 
-  *p = 0;
   temp = get_absolute_expr (&exp);
   size = temp;
-#ifdef BFD_ASSEMBLER
   size &= ((offsetT) 2 << (stdoutput->arch_info->bits_per_address - 1)) - 1;
-#endif
   if (exp.X_op == O_absent)
     {
       as_bad (_("missing size expression"));
-      *p = c;
       ignore_rest_of_line ();
       goto out;
     }
   else if (temp != size || !exp.X_unsigned)
     {
       as_warn (_("size (%ld) out of range, ignored"), (long) temp);
-      *p = c;
       ignore_rest_of_line ();
       goto out;
     }
 
+  *p = 0;
   symbolP = symbol_find_or_make (name);
-  if (S_IS_DEFINED (symbolP) && !S_IS_COMMON (symbolP))
+  if ((S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
+      && !S_IS_COMMON (symbolP))
     {
-      symbolP = NULL;
-      as_bad (_("symbol `%s' is already defined"), name);
-      *p = c;
-      ignore_rest_of_line ();
-      goto out;
+      if (!S_IS_VOLATILE (symbolP))
+	{
+	  symbolP = NULL;
+	  as_bad (_("symbol `%s' is already defined"), name);
+	  *p = c;
+	  ignore_rest_of_line ();
+	  goto out;
+	}
+      /* This could be avoided when the symbol wasn't used so far, but
+	 the comment in struc-symbol.h says this flag isn't reliable.  */
+      if (1 || !symbol_used_p (symbolP))
+	symbolP = symbol_clone (symbolP, 1);
+      S_SET_SEGMENT (symbolP, undefined_section);
+      S_SET_VALUE (symbolP, 0);
+      symbol_set_frag (symbolP, &zero_address_frag);
+      S_CLEAR_VOLATILE (symbolP);
     }
 
   size = S_GET_VALUE (symbolP);
@@ -1398,6 +1502,7 @@ s_comm_internal (int param,
     {
       S_SET_VALUE (symbolP, (valueT) size);
       S_SET_EXTERNAL (symbolP);
+      S_SET_SEGMENT (symbolP, bfd_com_section_ptr);
 #ifdef OBJ_VMS
       {
 	extern int flag_one;
@@ -1407,7 +1512,6 @@ s_comm_internal (int param,
 #endif
     }
 
-  know (symbolP == NULL || symbolP->sy_frag == &zero_address_frag);
   demand_empty_rest_of_line ();
  out:
   if (flag_mri)
@@ -1492,6 +1596,7 @@ s_mri_common (int small ATTRIBUTE_UNUSED)
     }
 
   S_SET_EXTERNAL (sym);
+  S_SET_SEGMENT (sym, bfd_com_section_ptr);
   mri_common_symbol = sym;
 
 #ifdef S_SET_ALIGN
@@ -1555,7 +1660,7 @@ s_data (int ignore ATTRIBUTE_UNUSED)
    .file.  */
 
 void
-s_app_file_string (char *file)
+s_app_file_string (char *file, int appfile ATTRIBUTE_UNUSED)
 {
 #ifdef LISTING
   if (listing)
@@ -1563,7 +1668,7 @@ s_app_file_string (char *file)
 #endif
   register_dependency (file);
 #ifdef obj_app_file
-  obj_app_file (file);
+  obj_app_file (file, appfile);
 #endif
 }
 
@@ -1591,7 +1696,7 @@ s_app_file (int appfile)
 
       demand_empty_rest_of_line ();
       if (!may_omit)
-	s_app_file_string (s);
+	s_app_file_string (s, appfile);
     }
 }
 
@@ -1607,9 +1712,17 @@ s_app_line (int ignore ATTRIBUTE_UNUSED)
 
   /* The given number is that of the next line.  */
   l = get_absolute_expression () - 1;
-  if (l < 0)
+
+  if (l < -1)
     /* Some of the back ends can't deal with non-positive line numbers.
-       Besides, it's silly.  */
+       Besides, it's silly.  GCC however will generate a line number of
+       zero when it is pre-processing builtins for assembler-with-cpp files:
+
+          # 0 "<built-in>"
+
+       We do not want to barf on this, especially since such files are used
+       in the GCC and GDB testsuites.  So we check for negative line numbers
+       rather than non-positive line numbers.  */
     as_warn (_("line numbers must be positive; line number %d rejected"),
 	     l + 1);
   else
@@ -1650,6 +1763,43 @@ s_err (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
+/* Handle the .error and .warning pseudo-ops.  */
+
+void
+s_errwarn (int err)
+{
+  int len;
+  /* The purpose for the conditional assignment is not to
+     internationalize the directive itself, but that we need a
+     self-contained message, one that can be passed like the
+     demand_copy_C_string return value, and with no assumption on the
+     location of the name of the directive within the message.  */
+  char *msg
+    = (err ? _(".error directive invoked in source file")
+       : _(".warning directive invoked in source file"));
+
+  if (!is_it_end_of_statement ())
+    {
+      if (*input_line_pointer != '\"')
+	{
+	  as_bad (_("%s argument must be a string"),
+		  err ? ".error" : ".warning");
+	  ignore_rest_of_line ();
+	  return;
+	}
+
+      msg = demand_copy_C_string (&len);
+      if (msg == NULL)
+	return;
+    }
+
+  if (err)
+    as_bad ("%s", msg);
+  else
+    as_warn ("%s", msg);
+  demand_empty_rest_of_line ();
+}
+
 /* Handle the MRI fail pseudo-op.  */
 
 void
@@ -1815,7 +1965,7 @@ s_globl (int ignore ATTRIBUTE_UNUSED)
 void
 s_irp (int irpc)
 {
-  char *file;
+  char *file, *eol;
   unsigned int line;
   sb s;
   const char *err;
@@ -1824,8 +1974,9 @@ s_irp (int irpc)
   as_where (&file, &line);
 
   sb_new (&s);
-  while (!is_end_of_line[(unsigned char) *input_line_pointer])
-    sb_add_char (&s, *input_line_pointer++);
+  eol = find_end_of_line (input_line_pointer, 0);
+  sb_add_buffer (&s, input_line_pointer, eol - input_line_pointer);
+  input_line_pointer = eol;
 
   sb_new (&out);
 
@@ -1878,7 +2029,6 @@ s_linkonce (int ignore ATTRIBUTE_UNUSED)
 #ifdef obj_handle_link_once
   obj_handle_link_once (type);
 #else /* ! defined (obj_handle_link_once) */
-#ifdef BFD_ASSEMBLER
   {
     flagword flags;
 
@@ -1908,9 +2058,6 @@ s_linkonce (int ignore ATTRIBUTE_UNUSED)
       as_bad (_("bfd_set_section_flags: %s"),
 	      bfd_errmsg (bfd_get_error ()));
   }
-#else /* ! defined (BFD_ASSEMBLER) */
-  as_warn (_(".linkonce is not supported for this object file format"));
-#endif /* ! defined (BFD_ASSEMBLER) */
 #endif /* ! defined (obj_handle_link_once) */
 
   demand_empty_rest_of_line ();
@@ -1933,11 +2080,9 @@ bss_alloc (symbolS *symbolP, addressT size, int align)
 	{
 	  bss_seg = subseg_new (".sbss", 1);
 	  seg_info (bss_seg)->bss = 1;
-#ifdef BFD_ASSEMBLER
 	  if (!bfd_set_section_flags (stdoutput, bss_seg, SEC_ALLOC))
 	    as_warn (_("error setting flags for \".sbss\": %s"),
 		     bfd_errmsg (bfd_get_error ()));
-#endif
 	}
     }
 #endif
@@ -2073,7 +2218,7 @@ s_lsym (int ignore ATTRIBUTE_UNUSED)
   if (name == p)
     {
       as_bad (_("expected symbol name"));
-      discard_rest_of_line ();
+      ignore_rest_of_line ();
       return;
     }
 
@@ -2089,7 +2234,7 @@ s_lsym (int ignore ATTRIBUTE_UNUSED)
     }
 
   input_line_pointer++;
-  expression (&exp);
+  expression_and_evaluate (&exp);
 
   if (exp.X_op != O_constant
       && exp.X_op != O_register)
@@ -2102,15 +2247,7 @@ s_lsym (int ignore ATTRIBUTE_UNUSED)
   *p = 0;
   symbolP = symbol_find_or_make (name);
 
-  /* FIXME-SOON I pulled a (&& symbolP->sy_other == 0 &&
-     symbolP->sy_desc == 0) out of this test because coff doesn't have
-     those fields, and I can't see when they'd ever be tripped.  I
-     don't think I understand why they were here so I may have
-     introduced a bug. As recently as 1.37 didn't have this test
-     anyway.  xoxorich.  */
-
-  if (S_GET_SEGMENT (symbolP) == undefined_section
-      && S_GET_VALUE (symbolP) == 0)
+  if (S_GET_SEGMENT (symbolP) == undefined_section)
     {
       /* The name might be an undefined .global symbol; be sure to
 	 keep the "external" bit.  */
@@ -2135,8 +2272,7 @@ s_lsym (int ignore ATTRIBUTE_UNUSED)
 static int
 get_line_sb (sb *line)
 {
-  char quote1, quote2, inquote;
-  unsigned char c;
+  char *eol;
 
   if (input_line_pointer[-1] == '\n')
     bump_line_counters ();
@@ -2148,45 +2284,16 @@ get_line_sb (sb *line)
 	return 0;
     }
 
-  /* If app.c sets any other characters to LEX_IS_STRINGQUOTE, this
-     code needs to be changed.  */
-  if (!flag_m68k_mri)
-    quote1 = '"';
-  else
-    quote1 = '\0';
-
-  quote2 = '\0';
-  if (flag_m68k_mri)
-    quote2 = '\'';
-#ifdef LEX_IS_STRINGQUOTE
-  quote2 = '\'';
-#endif
-
-  inquote = '\0';
-
-  while ((c = * input_line_pointer ++) != 0
-	 && (!is_end_of_line[c]
-	     || (inquote != '\0' && c != '\n')))
-    {
-      if (inquote == c)
-	inquote = '\0';
-      else if (inquote == '\0')
-	{
-	  if (c == quote1)
-	    inquote = quote1;
-	  else if (c == quote2)
-	    inquote = quote2;
-	}
-
-      sb_add_char (line, c);
-    }
+  eol = find_end_of_line (input_line_pointer, flag_m68k_mri);
+  sb_add_buffer (line, input_line_pointer, eol - input_line_pointer);
+  input_line_pointer = eol;
 
   /* Don't skip multiple end-of-line characters, because that breaks support
      for the IA-64 stop bit (;;) which looks like two consecutive end-of-line
      characters but isn't.  Instead just skip one end of line character and
      return the character skipped so that the caller can re-insert it if
      necessary.   */
-  return c;
+  return *input_line_pointer++;
 }
 
 /* Define a macro.  This is an interface to macro.c.  */
@@ -2194,31 +2301,37 @@ get_line_sb (sb *line)
 void
 s_macro (int ignore ATTRIBUTE_UNUSED)
 {
-  char *file;
+  char *file, *eol;
   unsigned int line;
   sb s;
-  sb label;
   const char *err;
   const char *name;
 
   as_where (&file, &line);
 
   sb_new (&s);
-  while (!is_end_of_line[(unsigned char) *input_line_pointer])
-    sb_add_char (&s, *input_line_pointer++);
+  eol = find_end_of_line (input_line_pointer, 0);
+  sb_add_buffer (&s, input_line_pointer, eol - input_line_pointer);
+  input_line_pointer = eol;
 
-  sb_new (&label);
   if (line_label != NULL)
-    sb_add_string (&label, S_GET_NAME (line_label));
+    {
+      sb label;
 
-  err = define_macro (0, &s, &label, get_line_sb, &name);
+      sb_new (&label);
+      sb_add_string (&label, S_GET_NAME (line_label));
+      err = define_macro (0, &s, &label, get_line_sb, file, line, &name);
+      sb_kill (&label);
+    }
+  else
+    err = define_macro (0, &s, NULL, get_line_sb, file, line, &name);
   if (err != NULL)
-    as_bad_where (file, line, "%s", err);
+    as_bad_where (file, line, err, name);
   else
     {
       if (line_label != NULL)
 	{
-	  S_SET_SEGMENT (line_label, undefined_section);
+	  S_SET_SEGMENT (line_label, absolute_section);
 	  S_SET_VALUE (line_label, 0);
 	  symbol_set_frag (line_label, &zero_address_frag);
 	}
@@ -2228,7 +2341,9 @@ s_macro (int ignore ATTRIBUTE_UNUSED)
 	  || (!flag_m68k_mri
 	      && *name == '.'
 	      && hash_find (po_hash, name + 1) != NULL))
-	as_warn (_("attempt to redefine pseudo-op `%s' ignored"),
+	as_warn_where (file,
+		 line,
+		 _("attempt to redefine pseudo-op `%s' ignored"),
 		 name);
     }
 
@@ -2372,8 +2487,7 @@ s_org (int ignore ATTRIBUTE_UNUSED)
    called by the obj-format routine which handles section changing
    when in MRI mode.  It will create a new section, and return it.  It
    will set *TYPE to the section type: one of 'C' (code), 'D' (data),
-   'M' (mixed), or 'R' (romable).  If BFD_ASSEMBLER is defined, the
-   flags will be set in the section.  */
+   'M' (mixed), or 'R' (romable).  The flags will be set in the section.  */
 
 void
 s_mri_sect (char *type ATTRIBUTE_UNUSED)
@@ -2427,7 +2541,6 @@ s_mri_sect (char *type ATTRIBUTE_UNUSED)
 	as_bad (_("unrecognized section type"));
       ++input_line_pointer;
 
-#ifdef BFD_ASSEMBLER
       {
 	flagword flags;
 
@@ -2446,7 +2559,6 @@ s_mri_sect (char *type ATTRIBUTE_UNUSED)
 		       bfd_errmsg (bfd_get_error ()));
 	  }
       }
-#endif
     }
 
   /* Ignore the HP type.  */
@@ -2580,12 +2692,14 @@ s_purgem (int ignore ATTRIBUTE_UNUSED)
   demand_empty_rest_of_line ();
 }
 
-/* Handle the .rept pseudo-op.  */
+/* Handle the .endm/.endr pseudo-ops.  */
 
-void
-s_bad_endr (int ignore ATTRIBUTE_UNUSED)
+static void
+s_bad_end (int endr)
 {
-  as_warn (_(".endr encountered without preceeding .rept, .irc, or .irp"));
+  as_warn (_(".end%c encountered without preceeding %s"),
+	   endr ? 'r' : 'm',
+	   endr ? ".rept, .irp, or .irpc" : ".macro");
   demand_empty_rest_of_line ();
 }
 
@@ -2644,51 +2758,15 @@ end_repeat (int extra)
     buffer_limit = input_scrub_next_buffer (&input_line_pointer);
 }
 
-/* Handle the .equ, .equiv and .set directives.  If EQUIV is 1, then
-   this is .equiv, and it is an error if the symbol is already
-   defined.  */
-
-void
-s_set (int equiv)
+static void
+assign_symbol (char *name, int mode)
 {
-  register char *name;
-  register char delim;
-  register char *end_name;
-  register symbolS *symbolP;
-
-  /* Especial apologies for the random logic:
-     this just grew, and could be parsed much more simply!
-     Dean in haste.  */
-  name = input_line_pointer;
-  delim = get_symbol_end ();
-  end_name = input_line_pointer;
-  *end_name = delim;
-
-  if (name == end_name)
-    {
-      as_bad (_("expected symbol name"));
-      discard_rest_of_line ();
-      return;
-    }
-
-  SKIP_WHITESPACE ();
-
-  if (*input_line_pointer != ',')
-    {
-      *end_name = 0;
-      as_bad (_("expected comma after \"%s\""), name);
-      *end_name = delim;
-      ignore_rest_of_line ();
-      return;
-    }
-
-  input_line_pointer++;
-  *end_name = 0;
+  symbolS *symbolP;
 
   if (name[0] == '.' && name[1] == '\0')
     {
       /* Turn '. = mumble' into a .org mumble.  */
-      register segT segment;
+      segT segment;
       expressionS exp;
 
       segment = get_known_segmented_expression (&exp);
@@ -2696,13 +2774,13 @@ s_set (int equiv)
       if (!need_pass_2)
 	do_org (segment, &exp, 0);
 
-      *end_name = delim;
       return;
     }
 
   if ((symbolP = symbol_find (name)) == NULL
       && (symbolP = md_undefined_symbol (name)) == NULL)
     {
+      symbolP = symbol_find_or_make (name);
 #ifndef NO_LISTING
       /* When doing symbol listings, play games with dummy fragments living
 	 outside the normal fragment chain to record the file and line info
@@ -2710,33 +2788,89 @@ s_set (int equiv)
       if (listing & LISTING_SYMBOLS)
 	{
 	  extern struct list_info_struct *listing_tail;
-	  fragS *dummy_frag = (fragS *) xmalloc (sizeof (fragS));
-	  memset (dummy_frag, 0, sizeof (fragS));
-	  dummy_frag->fr_type = rs_fill;
+	  fragS *dummy_frag = (fragS *) xcalloc (1, sizeof (fragS));
 	  dummy_frag->line = listing_tail;
-	  symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
 	  dummy_frag->fr_symbol = symbolP;
+	  symbol_set_frag (symbolP, dummy_frag);
 	}
-      else
 #endif
-	symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
-
 #ifdef OBJ_COFF
       /* "set" symbols are local unless otherwise specified.  */
       SF_SET_LOCAL (symbolP);
-#endif /* OBJ_COFF */
+#endif
+    }
+
+  if (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
+    {
+      /* Permit register names to be redefined.  */
+      if ((mode != 0 || !S_IS_VOLATILE (symbolP))
+	  && S_GET_SEGMENT (symbolP) != reg_section)
+	{
+	  as_bad (_("symbol `%s' is already defined"), name);
+	  symbolP = symbol_clone (symbolP, 0);
+	}
+      /* If the symbol is volatile, copy the symbol and replace the
+	 original with the copy, so that previous uses of the symbol will
+	 retain the value of the symbol at the point of use.  */
+      else if (S_IS_VOLATILE (symbolP)
+	  /* This could be avoided when the symbol wasn't used so far, but
+	     the comment in struc-symbol.h says this flag isn't reliable.  */
+	  && (1 || symbol_used_p (symbolP)))
+	symbolP = symbol_clone (symbolP, 1);
     }
 
-  symbol_table_insert (symbolP);
+  if (mode == 0)
+    S_SET_VOLATILE (symbolP);
+  else if (mode < 0)
+    S_SET_FORWARD_REF (symbolP);
+
+  pseudo_set (symbolP);
+}
+
+/* Handle the .equ, .equiv, .eqv, and .set directives.  If EQUIV is 1,
+   then this is .equiv, and it is an error if the symbol is already
+   defined.  If EQUIV is -1, the symbol additionally is a forward
+   reference.  */
+
+void
+s_set (int equiv)
+{
+  char *name;
+  char delim;
+  char *end_name;
 
+  /* Especial apologies for the random logic:
+     this just grew, and could be parsed much more simply!
+     Dean in haste.  */
+  name = input_line_pointer;
+  delim = get_symbol_end ();
+  end_name = input_line_pointer;
   *end_name = delim;
 
-  if (equiv
-      && S_IS_DEFINED (symbolP)
-      && S_GET_SEGMENT (symbolP) != reg_section)
-    as_bad (_("symbol `%s' is already defined"), S_GET_NAME (symbolP));
+  if (name == end_name)
+    {
+      as_bad (_("expected symbol name"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
+    {
+      *end_name = 0;
+      as_bad (_("expected comma after \"%s\""), name);
+      *end_name = delim;
+      ignore_rest_of_line ();
+      return;
+    }
+
+  input_line_pointer++;
+  *end_name = 0;
+
+  assign_symbol (name, equiv);
+  *end_name = delim;
 
-  pseudo_set (symbolP);
   demand_empty_rest_of_line ();
 }
 
@@ -2818,6 +2952,7 @@ s_space (int mult)
       || val.X_add_number > 0xff
       || (mult != 0 && mult != 1 && val.X_add_number != 0))
     {
+      resolve_expression (&exp);
       if (exp.X_op != O_constant)
 	as_bad (_("unsupported variable size or fill value"));
       else
@@ -2833,6 +2968,9 @@ s_space (int mult)
     }
   else
     {
+      if (now_seg == absolute_section || mri_common_symbol != NULL)
+	resolve_expression (&exp);
+
       if (exp.X_op == O_constant)
 	{
 	  long repeat;
@@ -3019,6 +3157,140 @@ s_text (int ignore ATTRIBUTE_UNUSED)
   const_flag &= ~IN_DEFAULT_SECTION;
 #endif
 }
+
+/* .weakref x, y sets x as an alias to y that, as long as y is not
+   referenced directly, will cause y to become a weak symbol.  */
+void
+s_weakref (int ignore ATTRIBUTE_UNUSED)
+{
+  char *name;
+  char delim;
+  char *end_name;
+  symbolS *symbolP;
+  symbolS *symbolP2;
+  expressionS exp;
+
+  name = input_line_pointer;
+  delim = get_symbol_end ();
+  end_name = input_line_pointer;
+
+  if (name == end_name)
+    {
+      as_bad (_("expected symbol name"));
+      *end_name = delim;
+      ignore_rest_of_line ();
+      return;
+    }
+
+  symbolP = symbol_find_or_make (name);
+
+  if (S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
+    {
+      if(!S_IS_VOLATILE (symbolP))
+	{
+	  as_bad (_("symbol `%s' is already defined"), name);
+	  *end_name = delim;
+	  ignore_rest_of_line ();
+	  return;
+	}
+      /* This could be avoided when the symbol wasn't used so far, but
+	 the comment in struc-symbol.h says this flag isn't reliable.  */
+      if (1 || !symbol_used_p (symbolP))
+	symbolP = symbol_clone (symbolP, 1);
+      S_CLEAR_VOLATILE (symbolP);
+    }
+
+  *end_name = delim;
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
+    {
+      *end_name = 0;
+      as_bad (_("expected comma after \"%s\""), name);
+      *end_name = delim;
+      ignore_rest_of_line ();
+      return;
+    }
+
+  input_line_pointer++;
+
+  SKIP_WHITESPACE ();
+
+  name = input_line_pointer;
+  delim = get_symbol_end ();
+  end_name = input_line_pointer;
+
+  if (name == end_name)
+    {
+      as_bad (_("expected symbol name"));
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if ((symbolP2 = symbol_find_noref (name, 1)) == NULL
+      && (symbolP2 = md_undefined_symbol (name)) == NULL)
+    {
+      symbolP2 = symbol_find_or_make (name);
+      S_SET_WEAKREFD (symbolP2);
+    }
+  else
+    {
+      symbolS *symp = symbolP2;
+
+      while (S_IS_WEAKREFR (symp) && symp != symbolP)
+	{
+	  expressionS *expP = symbol_get_value_expression (symp);
+
+	  assert (expP->X_op == O_symbol
+		  && expP->X_add_number == 0);
+	  symp = expP->X_add_symbol;
+	}
+      if (symp == symbolP)
+	{
+	  char *loop;
+
+	  loop = concat (S_GET_NAME (symbolP),
+			 " => ", S_GET_NAME (symbolP2), NULL);
+
+	  symp = symbolP2;
+	  while (symp != symbolP)
+	    {
+	      char *old_loop = loop;
+	      symp = symbol_get_value_expression (symp)->X_add_symbol;
+	      loop = concat (loop, " => ", S_GET_NAME (symp), NULL);
+	      free (old_loop);
+	    }
+
+	  as_bad (_("%s: would close weakref loop: %s"),
+		  S_GET_NAME (symbolP), loop);
+
+	  free (loop);
+
+	  *end_name = delim;
+	  ignore_rest_of_line ();
+	  return;
+	}
+
+      /* Short-circuiting instead of just checking here might speed
+	 things up a tiny little bit, but loop error messages would
+	 miss intermediate links.  */
+      /* symbolP2 = symp; */
+    }
+
+  *end_name = delim;
+
+  memset (&exp, 0, sizeof (exp));
+  exp.X_op = O_symbol;
+  exp.X_add_symbol = symbolP2;
+
+  S_SET_SEGMENT (symbolP, undefined_section);
+  symbol_set_value_expression (symbolP, &exp);
+  symbol_set_frag (symbolP, &zero_address_frag);
+  S_SET_WEAKREFR (symbolP);
+
+  demand_empty_rest_of_line ();
+}
 
 
 /* Verify that we are at the end of a line.  If not, issue an error and
@@ -3061,17 +3333,14 @@ ignore_rest_of_line (void)
   know (is_end_of_line[(unsigned char) input_line_pointer[-1]]);
 }
 
-void
-discard_rest_of_line (void)
-{
-  while (input_line_pointer < buffer_limit
-	 && !is_end_of_line[(unsigned char) *input_line_pointer])
-    input_line_pointer++;
-
-  input_line_pointer++;
+/* Sets frag for given symbol to zero_address_frag, except when the
+   symbol frag is already set to a dummy listing frag.  */
 
-  /* Return pointing just after end-of-line.  */
-  know (is_end_of_line[(unsigned char) input_line_pointer[-1]]);
+static void
+set_zero_frag (symbolS *symbolP)
+{
+  if (symbol_get_frag (symbolP)->fr_type != rs_dummy)
+    symbol_set_frag (symbolP, &zero_address_frag);
 }
 
 /* In:	Pointer to a symbol.
@@ -3085,16 +3354,14 @@ void
 pseudo_set (symbolS *symbolP)
 {
   expressionS exp;
-#if (defined (OBJ_AOUT) || defined (OBJ_BOUT)) && ! defined (BFD_ASSEMBLER)
-  int ext;
-#endif /* OBJ_AOUT or OBJ_BOUT */
+  segT seg;
 
   know (symbolP);		/* NULL pointer is logic error.  */
-#if (defined (OBJ_AOUT) || defined (OBJ_BOUT)) && ! defined (BFD_ASSEMBLER)
-  ext = S_IS_EXTERNAL (symbolP);
-#endif /* OBJ_AOUT or OBJ_BOUT */
 
-  (void) expression (&exp);
+  if (!S_IS_FORWARD_REF (symbolP))
+    (void) expression (&exp);
+  else
+    (void) deferred_expression (&exp);
 
   if (exp.X_op == O_illegal)
     as_bad (_("illegal expression"));
@@ -3108,6 +3375,7 @@ pseudo_set (symbolS *symbolP)
 	as_bad (_("floating point number invalid"));
     }
   else if (exp.X_op == O_subtract
+	   && !S_IS_FORWARD_REF (symbolP)
 	   && SEG_NORMAL (S_GET_SEGMENT (exp.X_add_symbol))
 	   && (symbol_get_frag (exp.X_add_symbol)
 	       == symbol_get_frag (exp.X_op_symbol)))
@@ -3117,6 +3385,12 @@ pseudo_set (symbolS *symbolP)
 			  - S_GET_VALUE (exp.X_op_symbol));
     }
 
+  if (symbol_section_p (symbolP))
+    {
+      as_bad ("attempt to set value of section symbol");
+      return;
+    }
+
   switch (exp.X_op)
     {
     case O_illegal:
@@ -3126,51 +3400,52 @@ pseudo_set (symbolS *symbolP)
       /* Fall through.  */
     case O_constant:
       S_SET_SEGMENT (symbolP, absolute_section);
-#if (defined (OBJ_AOUT) || defined (OBJ_BOUT)) && ! defined (BFD_ASSEMBLER)
-      if (ext)
-	S_SET_EXTERNAL (symbolP);
-      else
-	S_CLEAR_EXTERNAL (symbolP);
-#endif /* OBJ_AOUT or OBJ_BOUT */
       S_SET_VALUE (symbolP, (valueT) exp.X_add_number);
-      if (exp.X_op != O_constant)
-	symbol_set_frag (symbolP, &zero_address_frag);
+      set_zero_frag (symbolP);
       break;
 
     case O_register:
       S_SET_SEGMENT (symbolP, reg_section);
       S_SET_VALUE (symbolP, (valueT) exp.X_add_number);
-      symbol_set_frag (symbolP, &zero_address_frag);
+      set_zero_frag (symbolP);
       break;
 
     case O_symbol:
-      if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section
-	  || exp.X_add_number != 0)
-	symbol_set_value_expression (symbolP, &exp);
-      else if (symbol_section_p (symbolP))
-	as_bad ("attempt to set value of section symbol");
-      else
+      seg = S_GET_SEGMENT (exp.X_add_symbol);
+      /* For x=undef+const, create an expression symbol.
+	 For x=x+const, just update x except when x is an undefined symbol
+	 For x=defined+const, evaluate x.  */
+      if (symbolP == exp.X_add_symbol
+	  && (seg != undefined_section
+	      || !symbol_constant_p (symbolP)))
+	{
+	  *symbol_X_add_number (symbolP) += exp.X_add_number;
+	  break;
+	}
+      else if (!S_IS_FORWARD_REF (symbolP) && seg != undefined_section)
 	{
 	  symbolS *s = exp.X_add_symbol;
 
-	  S_SET_SEGMENT (symbolP, S_GET_SEGMENT (s));
-#if (defined (OBJ_AOUT) || defined (OBJ_BOUT)) && ! defined (BFD_ASSEMBLER)
-	  if (ext)
-	    S_SET_EXTERNAL (symbolP);
-	  else
-	    S_CLEAR_EXTERNAL (symbolP);
-#endif /* OBJ_AOUT or OBJ_BOUT */
-	  S_SET_VALUE (symbolP,
-		       exp.X_add_number + S_GET_VALUE (s));
+	  if (S_IS_COMMON (s))
+	    as_bad (_("`%s' can't be equated to common symbol '%s'"),
+		    S_GET_NAME (symbolP), S_GET_NAME (s));
+
+	  S_SET_SEGMENT (symbolP, seg);
+	  S_SET_VALUE (symbolP, exp.X_add_number + S_GET_VALUE (s));
 	  symbol_set_frag (symbolP, symbol_get_frag (s));
 	  copy_symbol_attributes (symbolP, s);
+	  break;
 	}
+      S_SET_SEGMENT (symbolP, undefined_section);
+      symbol_set_value_expression (symbolP, &exp);
+      set_zero_frag (symbolP);
       break;
 
     default:
-      /* The value is some complex expression.
-	 FIXME: Should we set the segment to anything?  */
+      /* The value is some complex expression.  */
+      S_SET_SEGMENT (symbolP, expr_section);
       symbol_set_value_expression (symbolP, &exp);
+      set_zero_frag (symbolP);
       break;
     }
 }
@@ -3256,6 +3531,11 @@ cons_worker (register int nbytes,	/* 1=.byte, 2=.word, 4=.long.  */
       return;
     }
 
+#ifdef TC_ADDRESS_BYTES
+  if (nbytes == 0)
+    nbytes = TC_ADDRESS_BYTES ();
+#endif
+
 #ifdef md_cons_align
   md_cons_align (nbytes);
 #endif
@@ -3482,22 +3762,9 @@ emit_expr (expressionS *exp, unsigned int nbytes)
      pass to md_number_to_chars, handle it as a bignum.  */
   if (op == O_constant && nbytes > sizeof (valueT))
     {
-      valueT val;
-      int gencnt;
-
-      if (!exp->X_unsigned && exp->X_add_number < 0)
-	extra_digit = (valueT) -1;
-      val = (valueT) exp->X_add_number;
-      gencnt = 0;
-      do
-	{
-	  generic_bignum[gencnt] = val & LITTLENUM_MASK;
-	  val >>= LITTLENUM_NUMBER_OF_BITS;
-	  ++gencnt;
-	}
-      while (val != 0);
-      op = exp->X_op = O_big;
-      exp->X_add_number = gencnt;
+      extra_digit = exp->X_unsigned ? 0 : -1;
+      convert_to_bignum (exp);
+      op = O_big;
     }
 
   if (op == O_constant)
@@ -3600,16 +3867,8 @@ emit_expr (expressionS *exp, unsigned int nbytes)
     {
       memset (p, 0, nbytes);
 
-      /* Now we need to generate a fixS to record the symbol value.
-	 This is easy for BFD.  For other targets it can be more
-	 complex.  For very complex cases (currently, the HPPA and
-	 NS32K), you can define TC_CONS_FIX_NEW to do whatever you
-	 want.  For simpler cases, you can define TC_CONS_RELOC to be
-	 the name of the reloc code that should be stored in the fixS.
-	 If neither is defined, the code uses NO_RELOC if it is
-	 defined, and otherwise uses 0.  */
+      /* Now we need to generate a fixS to record the symbol value.  */
 
-#ifdef BFD_ASSEMBLER
 #ifdef TC_CONS_FIX_NEW
       TC_CONS_FIX_NEW (frag_now, p - frag_now->fr_literal, nbytes, exp);
 #else
@@ -3639,24 +3898,6 @@ emit_expr (expressionS *exp, unsigned int nbytes)
 		     0, r);
       }
 #endif
-#else
-#ifdef TC_CONS_FIX_NEW
-      TC_CONS_FIX_NEW (frag_now, p - frag_now->fr_literal, nbytes, exp);
-#else
-      /* Figure out which reloc number to use.  Use TC_CONS_RELOC if
-	 it is defined, otherwise use NO_RELOC if it is defined,
-	 otherwise use 0.  */
-#ifndef TC_CONS_RELOC
-#ifdef NO_RELOC
-#define TC_CONS_RELOC NO_RELOC
-#else
-#define TC_CONS_RELOC 0
-#endif
-#endif
-      fix_new_exp (frag_now, p - frag_now->fr_literal, (int) nbytes, exp, 0,
-		   TC_CONS_RELOC);
-#endif /* TC_CONS_FIX_NEW */
-#endif /* BFD_ASSEMBLER */
     }
 }
 
@@ -4217,36 +4458,48 @@ output_big_sleb128 (char *p, LITTLENUM_TYPE *bignum, int size)
   unsigned byte;
 
   /* Strip leading sign extensions off the bignum.  */
-  while (size > 0 && bignum[size - 1] == (LITTLENUM_TYPE) -1)
+  while (size > 1
+	 && bignum[size - 1] == LITTLENUM_MASK
+	 && bignum[size - 2] > LITTLENUM_MASK / 2)
     size--;
 
   do
     {
-      if (loaded < 7 && size > 0)
-	{
-	  val |= (*bignum << loaded);
-	  loaded += 8 * CHARS_PER_LITTLENUM;
-	  size--;
-	  bignum++;
-	}
-
-      byte = val & 0x7f;
-      loaded -= 7;
-      val >>= 7;
+      /* OR in the next part of the littlenum.  */
+      val |= (*bignum << loaded);
+      loaded += LITTLENUM_NUMBER_OF_BITS;
+      size--;
+      bignum++;
 
-      if (size == 0)
+      /* Add bytes until there are less than 7 bits left in VAL
+	 or until every non-sign bit has been written.  */
+      do
 	{
-	  if ((val == 0 && (byte & 0x40) == 0)
-	      || (~(val | ~(((valueT) 1 << loaded) - 1)) == 0
-		  && (byte & 0x40) != 0))
+	  byte = val & 0x7f;
+	  loaded -= 7;
+	  val >>= 7;
+	  if (size > 0
+	      || val != ((byte & 0x40) == 0 ? 0 : ((valueT) 1 << loaded) - 1))
 	    byte |= 0x80;
+
+	  if (orig)
+	    *p = byte;
+	  p++;
 	}
+      while ((byte & 0x80) != 0 && loaded >= 7);
+    }
+  while (size > 0);
 
+  /* Mop up any left-over bits (of which there will be less than 7).  */
+  if ((byte & 0x80) != 0)
+    {
+      /* Sign-extend VAL.  */
+      if (val & (1 << (loaded - 1)))
+	val |= ~0 << loaded;
       if (orig)
-	*p = byte;
+	*p = val & 0x7f;
       p++;
     }
-  while (byte & 0x80);
 
   return p - orig;
 }
@@ -4302,11 +4555,11 @@ output_big_leb128 (char *p, LITTLENUM_TYPE *bignum, int size, int sign)
 /* Generate the appropriate fragments for a given expression to emit a
    leb128 value.  */
 
-void
+static void
 emit_leb128_expr (expressionS *exp, int sign)
 {
   operatorT op = exp->X_op;
-  int nbytes;
+  unsigned int nbytes;
 
   if (op == O_absent || op == O_illegal)
     {
@@ -4325,10 +4578,20 @@ emit_leb128_expr (expressionS *exp, int sign)
       as_warn (_("register value used as expression"));
       op = O_constant;
     }
+  else if (op == O_constant
+	   && sign
+	   && (exp->X_add_number < 0) != !exp->X_unsigned)
+    {
+      /* We're outputting a signed leb128 and the sign of X_add_number
+	 doesn't reflect the sign of the original value.  Convert EXP
+	 to a correctly-extended bignum instead.  */
+      convert_to_bignum (exp);
+      op = O_big;
+    }
 
   /* Let check_eh_frame know that data is being emitted.  nbytes == -1 is
      a signal that this is leb128 data.  It shouldn't optimize this away.  */
-  nbytes = -1;
+  nbytes = (unsigned int) -1;
   if (check_eh_frame (exp, &nbytes))
     abort ();
 
@@ -4381,10 +4644,6 @@ s_leb128 (int sign)
   md_flush_pending_output ();
 #endif
 
-#ifdef md_flush_pending_output
-  md_flush_pending_output ();
-#endif
-
   do
     {
       expression (&exp);
@@ -4663,27 +4922,6 @@ get_known_segmented_expression (register expressionS *expP)
   return (retval);
 }
 
-offsetT
-get_absolute_expr (expressionS *exp)
-{
-  expression (exp);
-  if (exp->X_op != O_constant)
-    {
-      if (exp->X_op != O_absent)
-	as_bad (_("bad or irreducible absolute expression"));
-      exp->X_add_number = 0;
-    }
-  return exp->X_add_number;
-}
-
-offsetT
-get_absolute_expression (void)
-{
-  expressionS exp;
-
-  return get_absolute_expr (&exp);
-}
-
 char				/* Return terminator.  */
 get_absolute_expression_and_terminator (long *val_pointer /* Return value of expression.  */)
 {
@@ -4771,13 +5009,14 @@ is_it_end_of_statement (void)
 void
 equals (char *sym_name, int reassign)
 {
-  register symbolS *symbolP;	/* Symbol we are working with.  */
   char *stop = NULL;
   char stopc;
 
   input_line_pointer++;
   if (*input_line_pointer == '=')
     input_line_pointer++;
+  if (reassign < 0 && *input_line_pointer == '=')
+    input_line_pointer++;
 
   while (*input_line_pointer == ' ' || *input_line_pointer == '\t')
     input_line_pointer++;
@@ -4785,44 +5024,10 @@ equals (char *sym_name, int reassign)
   if (flag_mri)
     stop = mri_comment_field (&stopc);
 
-  if (sym_name[0] == '.' && sym_name[1] == '\0')
-    {
-      /* Turn '. = mumble' into a .org mumble.  */
-      register segT segment;
-      expressionS exp;
-
-      segment = get_known_segmented_expression (&exp);
-      if (!need_pass_2)
-	do_org (segment, &exp, 0);
-    }
-  else
-    {
-#ifdef OBJ_COFF
-      int local;
-
-      symbolP = symbol_find (sym_name);
-      local = symbolP == NULL;
-      if (local)
-#endif /* OBJ_COFF */
-      symbolP = symbol_find_or_make (sym_name);
-      /* Permit register names to be redefined.  */
-      if (!reassign
-	  && S_IS_DEFINED (symbolP)
-	  && S_GET_SEGMENT (symbolP) != reg_section)
-	as_bad (_("symbol `%s' is already defined"), S_GET_NAME (symbolP));
-
-#ifdef OBJ_COFF
-      /* "set" symbols are local unless otherwise specified.  */
-      if (local)
-	SF_SET_LOCAL (symbolP);
-#endif /* OBJ_COFF */
-
-      pseudo_set (symbolP);
-    }
+  assign_symbol (sym_name, reassign >= 0 ? !reassign : reassign);
 
   if (flag_mri)
     {
-      /* Check garbage after the expression.  */
       demand_empty_rest_of_line ();
       mri_comment_end (stop, stopc);
     }
@@ -4912,13 +5117,13 @@ s_incbin (int x ATTRIBUTE_UNUSED)
 	}
       file_len = ftell (binfile);
 
-      /* If a count was not specified use the size of the file.  */
+      /* If a count was not specified use the remainder of the file.  */
       if (count == 0)
-	count = file_len;
+	count = file_len - skip;
 
-      if (skip + count > file_len)
+      if (skip < 0 || count < 0 || file_len < 0 || skip + count > file_len)
 	{
-	  as_bad (_("skip (%ld) + count (%ld) larger than file size (%ld)"),
+	  as_bad (_("skip (%ld) or count (%ld) invalid for file size (%ld)"),
 		  skip, count, file_len);
 	  goto done;
 	}
@@ -5079,7 +5284,7 @@ s_func (int end_p)
 /* Subroutine of s_func so targets can choose a different default prefix.
    If DEFAULT_PREFIX is NULL, use the target's "leading char".  */
 
-void
+static void
 do_s_func (int end_p, const char *default_prefix)
 {
   /* Record the current function so that we can issue an error message for
@@ -5125,10 +5330,7 @@ do_s_func (int end_p, const char *default_prefix)
 	    asprintf (&label, "%s%s", default_prefix, name);
 	  else
 	    {
-	      char leading_char = 0;
-#ifdef BFD_ASSEMBLER
-	      leading_char = bfd_get_symbol_leading_char (stdoutput);
-#endif
+	      char leading_char = bfd_get_symbol_leading_char (stdoutput);
 	      /* Missing entry point, use function's name with the leading
 		 char prepended.  */
 	      if (leading_char)
@@ -5160,11 +5362,7 @@ do_s_func (int end_p, const char *default_prefix)
 void
 s_ignore (int arg ATTRIBUTE_UNUSED)
 {
-  while (!is_end_of_line[(unsigned char) *input_line_pointer])
-    {
-      ++input_line_pointer;
-    }
-  ++input_line_pointer;
+  ignore_rest_of_line ();
 }
 
 void
@@ -5202,3 +5400,51 @@ input_scrub_insert_file (char *path)
   input_scrub_include_file (path, input_line_pointer);
   buffer_limit = input_scrub_next_buffer (&input_line_pointer);
 }
+
+/* Find the end of a line, considering quotation and escaping of quotes.  */
+
+#if !defined(TC_SINGLE_QUOTE_STRINGS) && defined(SINGLE_QUOTE_STRINGS)
+# define TC_SINGLE_QUOTE_STRINGS 1
+#endif
+
+static char *
+_find_end_of_line (char *s, int mri_string, int insn ATTRIBUTE_UNUSED)
+{
+  char inquote = '\0';
+  int inescape = 0;
+
+  while (!is_end_of_line[(unsigned char) *s]
+	 || (inquote && !ISCNTRL (*s))
+	 || (inquote == '\'' && flag_mri)
+#ifdef TC_EOL_IN_INSN
+	 || (insn && TC_EOL_IN_INSN (s))
+#endif
+	)
+    {
+      if (mri_string && *s == '\'')
+	inquote ^= *s;
+      else if (inescape)
+	inescape = 0;
+      else if (*s == '\\')
+	inescape = 1;
+      else if (!inquote
+	       ? *s == '"'
+#ifdef TC_SINGLE_QUOTE_STRINGS
+		 || (TC_SINGLE_QUOTE_STRINGS && *s == '\'')
+#endif
+	       : *s == inquote)
+	inquote ^= *s;
+      ++s;
+    }
+  if (inquote)
+    as_warn (_("missing closing `%c'"), inquote);
+  if (inescape)
+    as_warn (_("stray `\\'"));
+  return s;
+}
+
+char *
+find_end_of_line (char *s, int mri_string)
+{
+  return _find_end_of_line (s, mri_string, 0);
+}
diff --git a/gas/read.h b/gas/read.h
index b89ffcb4fbfd..a18272d8882c 100644
--- a/gas/read.h
+++ b/gas/read.h
@@ -1,6 +1,6 @@
 /* read.h - of read.c
    Copyright 1986, 1990, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2002, 2003
+   2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 extern char *input_line_pointer;	/* -> char we are parsing now.  */
 
@@ -56,6 +56,7 @@ extern char lex_type[];
 extern char is_end_of_line[];
 
 extern int is_it_end_of_statement (void);
+extern char *find_end_of_line (char *, int);
 
 extern int target_big_endian;
 
@@ -101,7 +102,6 @@ extern void aout_process_stab (int, const char *, int, int, int);
 extern char *demand_copy_string (int *lenP);
 extern char *demand_copy_C_string (int *len_pointer);
 extern char get_absolute_expression_and_terminator (long *val_pointer);
-extern offsetT get_absolute_expr (expressionS *);
 extern offsetT get_absolute_expression (void);
 extern unsigned int next_char_of_string (void);
 extern void s_mri_sect (char *);
@@ -111,11 +111,10 @@ extern void add_include_dir (char *path);
 extern void cons (int nbytes);
 extern void demand_empty_rest_of_line (void);
 extern void emit_expr (expressionS *exp, unsigned int nbytes);
-extern void emit_leb128_expr (expressionS *, int);
 extern void equals (char *sym_name, int reassign);
 extern void float_cons (int float_type);
 extern void ignore_rest_of_line (void);
-extern void discard_rest_of_line (void);
+#define discard_rest_of_line ignore_rest_of_line
 extern int output_leb128 (char *, valueT, int sign);
 extern void pseudo_set (symbolS * symbolP);
 extern void read_a_source_file (char *name);
@@ -139,10 +138,9 @@ extern void bss_alloc (symbolS *, addressT, int);
 extern offsetT parse_align (int);
 extern symbolS *s_comm_internal (int, symbolS *(*) (int, symbolS *, addressT));
 extern symbolS *s_lcomm_internal (int, symbolS *, addressT);
-extern void s_app_file_string (char *);
+extern void s_app_file_string (char *, int);
 extern void s_app_file (int);
 extern void s_app_line (int);
-extern void s_bad_endr (int);
 extern void s_comm (int);
 extern void s_data (int);
 extern void s_desc (int);
@@ -151,13 +149,14 @@ extern void s_elseif (int arg);
 extern void s_end (int arg);
 extern void s_endif (int arg);
 extern void s_err (int);
+extern void s_errwarn (int);
 extern void s_fail (int);
 extern void s_fill (int);
 extern void s_float_space (int mult);
 extern void s_func (int);
-extern void do_s_func (int, const char *);
 extern void s_globl (int arg);
 extern void s_if (int arg);
+extern void s_ifb (int arg);
 extern void s_ifc (int arg);
 extern void s_ifdef (int arg);
 extern void s_ifeqs (int arg);
@@ -186,3 +185,4 @@ extern void stringer (int append_zero);
 extern void s_xstab (int what);
 extern void s_rva (int);
 extern void s_incbin (int);
+extern void s_weakref (int);
diff --git a/gas/sb.c b/gas/sb.c
index 27b29eee9cdc..ecd772c30c02 100644
--- a/gas/sb.c
+++ b/gas/sb.c
@@ -1,5 +1,5 @@
 /* sb.c - string buffer manipulation routines
-   Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #include "config.h"
 #include <stdio.h>
@@ -33,6 +33,7 @@
 #endif
 #include "libiberty.h"
 #include "sb.h"
+#include "as.h"
 
 /* These routines are about manipulating strings.
 
@@ -46,28 +47,23 @@
    sb_new (&foo);
    sb_grow... (&foo,...);
    use foo->ptr[*];
-   sb_kill (&foo);
-
-*/
-
-#define dsize 5
+   sb_kill (&foo);  */
 
+static int dsize = 5;
 static void sb_check (sb *, int);
 
 /* Statistics of sb structures.  */
-
-int string_count[sb_max_power_two];
+static int string_count[sb_max_power_two];
 
 /* Free list of sb structures.  */
-
 static sb_list_vector free_list;
 
-/* initializes an sb.  */
+/* Initializes an sb.  */
 
-void
+static void
 sb_build (sb *ptr, int size)
 {
-  /* see if we can find one to allocate */
+  /* See if we can find one to allocate.  */
   sb_element *e;
 
   if (size > sb_max_power_two)
@@ -76,7 +72,7 @@ sb_build (sb *ptr, int size)
   e = free_list.size[size];
   if (!e)
     {
-      /* nothing there, allocate one and stick into the free list */
+      /* Nothing there, allocate one and stick into the free list.  */
       e = (sb_element *) xmalloc (sizeof (sb_element) + (1 << size));
       e->next = free_list.size[size];
       e->size = 1 << size;
@@ -84,11 +80,10 @@ sb_build (sb *ptr, int size)
       string_count[size]++;
     }
 
-  /* remove from free list */
-
+  /* Remove from free list.  */
   free_list.size[size] = e->next;
 
-  /* copy into callers world */
+  /* Copy into callers world.  */
   ptr->ptr = e->data;
   ptr->pot = size;
   ptr->len = 0;
@@ -101,17 +96,17 @@ sb_new (sb *ptr)
   sb_build (ptr, dsize);
 }
 
-/* deallocate the sb at ptr */
+/* Deallocate the sb at ptr.  */
 
 void
 sb_kill (sb *ptr)
 {
-  /* return item to free list */
+  /* Return item to free list.  */
   ptr->item->next = free_list.size[ptr->pot];
   free_list.size[ptr->pot] = ptr->item;
 }
 
-/* add the sb at s to the end of the sb at ptr */
+/* Add the sb at s to the end of the sb at ptr.  */
 
 void
 sb_add_sb (sb *ptr, sb *s)
@@ -121,7 +116,39 @@ sb_add_sb (sb *ptr, sb *s)
   ptr->len += s->len;
 }
 
-/* make sure that the sb at ptr has room for another len characters,
+/* Helper for sb_scrub_and_add_sb.  */
+
+static sb *sb_to_scrub;
+static char *scrub_position;
+static int
+scrub_from_sb (char *buf, int buflen)
+{
+  int copy;
+  copy = sb_to_scrub->len - (scrub_position - sb_to_scrub->ptr);
+  if (copy > buflen)
+    copy = buflen;
+  memcpy (buf, scrub_position, copy);
+  scrub_position += copy;
+  return copy;
+}
+
+/* Run the sb at s through do_scrub_chars and add the result to the sb
+   at ptr.  */
+
+void
+sb_scrub_and_add_sb (sb *ptr, sb *s)
+{
+  sb_to_scrub = s;
+  scrub_position = s->ptr;
+  
+  sb_check (ptr, s->len);
+  ptr->len += do_scrub_chars (scrub_from_sb, ptr->ptr + ptr->len, s->len);
+
+  sb_to_scrub = 0;
+  scrub_position = 0;
+}
+
+/* Make sure that the sb at ptr has room for another len characters,
    and grow it if it doesn't.  */
 
 static void
@@ -131,6 +158,7 @@ sb_check (sb *ptr, int len)
     {
       sb tmp;
       int pot = ptr->pot;
+
       while (ptr->len + len >= 1 << pot)
 	pot++;
       sb_build (&tmp, pot);
@@ -140,7 +168,7 @@ sb_check (sb *ptr, int len)
     }
 }
 
-/* make the sb at ptr point back to the beginning.  */
+/* Make the sb at ptr point back to the beginning.  */
 
 void
 sb_reset (sb *ptr)
@@ -148,7 +176,7 @@ sb_reset (sb *ptr)
   ptr->len = 0;
 }
 
-/* add character c to the end of the sb at ptr.  */
+/* Add character c to the end of the sb at ptr.  */
 
 void
 sb_add_char (sb *ptr, int c)
@@ -157,7 +185,7 @@ sb_add_char (sb *ptr, int c)
   ptr->ptr[ptr->len++] = c;
 }
 
-/* add null terminated string s to the end of sb at ptr.  */
+/* Add null terminated string s to the end of sb at ptr.  */
 
 void
 sb_add_string (sb *ptr, const char *s)
@@ -168,7 +196,7 @@ sb_add_string (sb *ptr, const char *s)
   ptr->len += len;
 }
 
-/* add string at s of length len to sb at ptr */
+/* Add string at s of length len to sb at ptr */
 
 void
 sb_add_buffer (sb *ptr, const char *s, int len)
@@ -178,45 +206,7 @@ sb_add_buffer (sb *ptr, const char *s, int len)
   ptr->len += len;
 }
 
-/* print the sb at ptr to the output file */
-
-void
-sb_print (FILE *outfile, sb *ptr)
-{
-  int i;
-  int nc = 0;
-
-  for (i = 0; i < ptr->len; i++)
-    {
-      if (nc)
-	{
-	  fprintf (outfile, ",");
-	}
-      fprintf (outfile, "%d", ptr->ptr[i]);
-      nc = 1;
-    }
-}
-
-void
-sb_print_at (FILE *outfile, int idx, sb *ptr)
-{
-  int i;
-  for (i = idx; i < ptr->len; i++)
-    putc (ptr->ptr[i], outfile);
-}
-
-/* put a null at the end of the sb at in and return the start of the
-   string, so that it can be used as an arg to printf %s.  */
-
-char *
-sb_name (sb *in)
-{
-  /* stick a null on the end of the string */
-  sb_add_char (in, 0);
-  return in->ptr;
-}
-
-/* like sb_name, but don't include the null byte in the string.  */
+/* Like sb_name, but don't include the null byte in the string.  */
 
 char *
 sb_terminate (sb *in)
@@ -226,8 +216,8 @@ sb_terminate (sb *in)
   return in->ptr;
 }
 
-/* start at the index idx into the string in sb at ptr and skip
-   whitespace. return the index of the first non whitespace character */
+/* Start at the index idx into the string in sb at ptr and skip
+   whitespace. return the index of the first non whitespace character.  */
 
 int
 sb_skip_white (int idx, sb *ptr)
@@ -239,7 +229,7 @@ sb_skip_white (int idx, sb *ptr)
   return idx;
 }
 
-/* start at the index idx into the sb at ptr. skips whitespace,
+/* Start at the index idx into the sb at ptr. skips whitespace,
    a comma and any following whitespace. returns the index of the
    next character.  */
 
diff --git a/gas/sb.h b/gas/sb.h
index 30e5bc3a02d6..5732688315f7 100644
--- a/gas/sb.h
+++ b/gas/sb.h
@@ -1,5 +1,5 @@
 /* sb.h - header file for string buffer manipulation routines
-   Copyright 1994, 1995, 2000 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 2000, 2003 Free Software Foundation, Inc.
 
    Written by Steve and Judy Chamberlain of Cygnus Support,
       sac@cygnus.com
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef SB_H
 
@@ -28,7 +28,7 @@
 #include <stdio.h>
 #include "ansidecl.h"
 
-/* string blocks
+/* String blocks
 
    I had a couple of choices when deciding upon this data structure.
    gas uses null terminated strings for all its internal work.  This
@@ -46,49 +46,46 @@
 
    An sb is allocated by the caller, and is initialized to point to an
    sb_element.  sb_elements are kept on a free lists, and used when
-   needed, replaced onto the free list when unused.
- */
+   needed, replaced onto the free list when unused.  */
+
+#define sb_max_power_two    30	/* Don't allow strings more than
+			           2^sb_max_power_two long.  */
 
-#define sb_max_power_two    30	/* don't allow strings more than
-			           2^sb_max_power_two long */
-/* structure of an sb */
 typedef struct sb
-  {
-    char *ptr;			/* points to the current block.  */
-    int len;			/* how much is used.  */
-    int pot;			/* the maximum length is 1<<pot */
-    struct le *item;
-  }
+{
+  char *ptr;			/* Points to the current block.  */
+  int len;			/* How much is used.  */
+  int pot;			/* The maximum length is 1<<pot.  */
+  struct le *item;
+}
 sb;
 
-/* Structure of the free list object of an sb */
+/* Structure of the free list object of a string block.  */
+
 typedef struct le
-  {
-    struct le *next;
-    int size;
-    char data[1];
-  }
+{
+  struct le *next;
+  int size;
+  char data[1];
+}
 sb_element;
 
-/* The free list */
-typedef struct
-  {
-    sb_element *size[sb_max_power_two];
-  } sb_list_vector;
+/* The free list.  */
 
-extern int string_count[sb_max_power_two];
+typedef struct
+{
+  sb_element *size[sb_max_power_two];
+}
+sb_list_vector;
 
-extern void sb_build (sb *, int);
 extern void sb_new (sb *);
 extern void sb_kill (sb *);
 extern void sb_add_sb (sb *, sb *);
+extern void sb_scrub_and_add_sb (sb *, sb *);
 extern void sb_reset (sb *);
 extern void sb_add_char (sb *, int);
 extern void sb_add_string (sb *, const char *);
 extern void sb_add_buffer (sb *, const char *, int);
-extern void sb_print (FILE *, sb *);
-extern void sb_print_at (FILE *, int, sb *);
-extern char *sb_name (sb *);
 extern char *sb_terminate (sb *);
 extern int sb_skip_white (int, sb *);
 extern int sb_skip_comma (int, sb *);
diff --git a/gas/stabs.c b/gas/stabs.c
index f8acdc842575..0b5c83b324a8 100644
--- a/gas/stabs.c
+++ b/gas/stabs.c
@@ -1,6 +1,6 @@
 /* Generic stabs parsing for gas.
    Copyright 1989, 1990, 1991, 1993, 1995, 1996, 1997, 1998, 2000, 2001
-   Free Software Foundation, Inc.
+   2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
 This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@ the GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with GAS; see the file COPYING.  If not, write to the Free
-Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-02111-1307, USA.  */
+Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+02110-1301, USA.  */
 
 #include "as.h"
 #include "obstack.h"
@@ -107,11 +107,9 @@ get_stab_string_offset (const char *string, const char *stabstr_secname)
       p = frag_more (1);
       *p = 0;
       retval = seg_info (seg)->stabu.stab_string_size = 1;
-#ifdef BFD_ASSEMBLER
       bfd_set_section_flags (stdoutput, seg, SEC_READONLY | SEC_DEBUGGING);
       if (seg->name == stabstr_secname)
 	seg->name = xstrdup (stabstr_secname);
-#endif
     }
 
   if (length > 0)
@@ -150,11 +148,10 @@ aout_process_stab (what, string, type, other, desc)
      ends in "\" and the debug info is continued in the next .stabs
      directive) from being separated by other random symbols.  */
   symbol = symbol_create (string, undefined_section, 0,
-			  (struct frag *) NULL);
+			  &zero_address_frag);
   if (what == 's' || what == 'n')
     {
       /* Pick up the value from the input line.  */
-      symbol_set_frag (symbol, &zero_address_frag);
       pseudo_set (symbol);
     }
   else
@@ -332,10 +329,8 @@ s_stab_generic (int what, char *stab_secname, char *stabstr_secname)
 
       if (! seg_info (seg)->hadone)
 	{
-#ifdef BFD_ASSEMBLER
 	  bfd_set_section_flags (stdoutput, seg,
 				 SEC_READONLY | SEC_RELOC | SEC_DEBUGGING);
-#endif
 #ifdef INIT_STAB_SECTION
 	  INIT_STAB_SECTION (seg);
 #endif
diff --git a/gas/struc-symbol.h b/gas/struc-symbol.h
index 90945c433bc3..75e22076ca8e 100644
--- a/gas/struc-symbol.h
+++ b/gas/struc-symbol.h
@@ -1,5 +1,5 @@
 /* struct_symbol.h - Internal symbol structure
-   Copyright 1987, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001
+   Copyright 1987, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,49 +16,27 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef __struc_symbol_h__
 #define __struc_symbol_h__
 
-#ifdef BFD_ASSEMBLER
-/* The BFD code wants to walk the list in both directions.  */
-#undef  SYMBOLS_NEED_BACKPOINTERS
-#define SYMBOLS_NEED_BACKPOINTERS
-#endif
-
 /* The information we keep for a symbol.  Note that the symbol table
    holds pointers both to this and to local_symbol structures.  See
    below.  */
 
 struct symbol
 {
-#ifdef BFD_ASSEMBLER
   /* BFD symbol */
   asymbol *bsym;
-#else
-  /* The (4-origin) position of sy_name in the symbol table of the object
-     file.  This will be 0 for (nameless) .stabd symbols.
-
-     Not used until write_object_file() time.  */
-  unsigned long sy_name_offset;
-
-  /* What we write in .o file (if permitted).  */
-  obj_symbol_type sy_symbol;
-
-  /* The 24 bit symbol number.  Symbol numbers start at 0 and are unsigned.  */
-  long sy_number;
-#endif
 
   /* The value of the symbol.  */
   expressionS sy_value;
 
   /* Forwards and (optionally) backwards chain pointers.  */
   struct symbol *sy_next;
-#ifdef SYMBOLS_NEED_BACKPOINTERS
   struct symbol *sy_previous;
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
 
   /* Pointer to the frag this symbol is attached to, if any.
      Otherwise, NULL.  */
@@ -82,12 +60,27 @@ struct symbol
      a symbol is used in backend routines.  */
   unsigned int sy_used : 1;
 
+  /* Whether the symbol can be re-defined.  */
+  unsigned int sy_volatile : 1;
+
+  /* Whether the symbol is a forward reference.  */
+  unsigned int sy_forward_ref : 1;
+
   /* This is set if the symbol is defined in an MRI common section.
      We handle such sections as single common symbols, so symbols
      defined within them must be treated specially by the relocation
      routines.  */
   unsigned int sy_mri_common : 1;
 
+  /* This is set if the symbol is set with a .weakref directive.  */
+  unsigned int sy_weakrefr : 1;
+
+  /* This is set when the symbol is referenced as part of a .weakref
+     directive, but only if the symbol was not in the symbol table
+     before.  It is cleared as soon as any direct reference to the
+     symbol is present.  */
+  unsigned int sy_weakrefd : 1;
+
 #ifdef OBJ_SYMFIELD_TYPE
   OBJ_SYMFIELD_TYPE sy_obj;
 #endif
@@ -101,8 +94,6 @@ struct symbol
 #endif
 };
 
-#ifdef BFD_ASSEMBLER
-
 /* A pointer in the symbol may point to either a complete symbol
    (struct symbol above) or to a local symbol (struct local_symbol
    defined here).  The symbol code can detect the case by examining
@@ -154,6 +145,4 @@ struct local_symbol
 #define local_symbol_get_real_symbol(l) ((l)->u.lsy_sym)
 #define local_symbol_set_real_symbol(l, s) ((l)->u.lsy_sym = (s))
 
-#endif /* BFD_ASSEMBLER */
-
 #endif /* __struc_symbol_h__ */
diff --git a/gas/subsegs.c b/gas/subsegs.c
index b2432e9a1f80..9401d61a834c 100644
--- a/gas/subsegs.c
+++ b/gas/subsegs.c
@@ -1,6 +1,6 @@
 /* subsegs.c - subsegments -
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2002
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Segments & sub-segments.  */
 
@@ -31,45 +31,11 @@ frchainS *frchain_root, *frchain_now;
 
 static struct obstack frchains;
 
-#ifndef BFD_ASSEMBLER
-#ifdef MANY_SEGMENTS
-segment_info_type segment_info[SEG_MAXIMUM_ORDINAL];
-
-#else
-/* Commented in "subsegs.h".  */
-frchainS *data0_frchainP, *bss0_frchainP;
-
-#endif /* MANY_SEGMENTS */
-char const *const seg_name[] = {
-  "absolute",
-#ifdef MANY_SEGMENTS
-  "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "e8", "e9",
-  "e10", "e11", "e12", "e13", "e14", "e15", "e16", "e17", "e18", "e19",
-  "e20", "e21", "e22", "e23", "e24", "e25", "e26", "e27", "e28", "e29",
-  "e30", "e31", "e32", "e33", "e34", "e35", "e36", "e37", "e38", "e39",
-#else
-  "text",
-  "data",
-  "bss",
-#endif /* MANY_SEGMENTS */
-  "unknown",
-  "ASSEMBLER-INTERNAL-LOGIC-ERROR!",
-  "expr",
-  "debug",
-  "transfert vector preload",
-  "transfert vector postload",
-  "register",
-  "",
-};				/* Used by error reporters, dumpers etc.  */
-#else /* BFD_ASSEMBLER */
-
 /* Gas segment information for bfd_abs_section_ptr and
    bfd_und_section_ptr.  */
 static segment_info_type *abs_seg_info;
 static segment_info_type *und_seg_info;
 
-#endif /* BFD_ASSEMBLER */
-
 static void subseg_set_rest (segT, subsegT);
 
 static fragS dummy_frag;
@@ -79,22 +45,6 @@ static frchainS absolute_frchain;
 void
 subsegs_begin (void)
 {
-  /* Check table(s) seg_name[], seg_N_TYPE[] is in correct order */
-#if !defined (MANY_SEGMENTS) && !defined (BFD_ASSEMBLER)
-  know (SEG_ABSOLUTE == 0);
-  know (SEG_TEXT == 1);
-  know (SEG_DATA == 2);
-  know (SEG_BSS == 3);
-  know (SEG_UNKNOWN == 4);
-  know (SEG_GOOF == 5);
-  know (SEG_EXPR == 6);
-  know (SEG_DEBUG == 7);
-  know (SEG_NTV == 8);
-  know (SEG_PTV == 9);
-  know (SEG_REGISTER == 10);
-  know (SEG_MAXIMUM_ORDINAL == SEG_REGISTER);
-#endif
-
   obstack_begin (&frchains, chunksize);
 #if __GNUC__ >= 2
   obstack_alignment_mask (&frchains) = __alignof__ (frchainS) - 1;
@@ -105,32 +55,9 @@ subsegs_begin (void)
 
   frag_now = &dummy_frag;
 
-#ifndef BFD_ASSEMBLER
-  now_subseg = 42;		/* Lie for 1st call to subseg_new.  */
-#ifdef MANY_SEGMENTS
-  {
-    int i;
-    for (i = SEG_E0; i < SEG_UNKNOWN; i++)
-      {
-	subseg_set (i, 0);
-	segment_info[i].frchainP = frchain_now;
-      }
-  }
-#else
-  subseg_set (SEG_DATA, 0);	/* .data 0 */
-  data0_frchainP = frchain_now;
-
-  subseg_set (SEG_BSS, 0);
-  bss0_frchainP = frchain_now;
-
-#endif /* ! MANY_SEGMENTS */
-#endif /* ! BFD_ASSEMBLER */
-
   absolute_frchain.frch_seg = absolute_section;
   absolute_frchain.frch_subseg = 0;
-#ifdef BFD_ASSEMBLER
   absolute_frchain.fix_root = absolute_frchain.fix_tail = 0;
-#endif
   absolute_frchain.frch_frag_now = &zero_address_frag;
   absolute_frchain.frch_root = absolute_frchain.frch_last = &zero_address_frag;
 }
@@ -148,56 +75,29 @@ subsegs_begin (void)
 void
 subseg_change (register segT seg, register int subseg)
 {
+  segment_info_type *seginfo;
   now_seg = seg;
   now_subseg = subseg;
 
   if (now_seg == absolute_section)
     return;
 
-#ifdef BFD_ASSEMBLER
-  {
-    segment_info_type *seginfo;
-    seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
-    if (! seginfo)
-      {
-	seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
-	memset ((PTR) seginfo, 0, sizeof (*seginfo));
-	seginfo->fix_root = NULL;
-	seginfo->fix_tail = NULL;
-	seginfo->bfd_section = seg;
-	seginfo->sym = 0;
-	if (seg == bfd_abs_section_ptr)
-	  abs_seg_info = seginfo;
-	else if (seg == bfd_und_section_ptr)
-	  und_seg_info = seginfo;
-	else
-	  bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
-      }
-  }
-#else
-#ifdef MANY_SEGMENTS
-  seg_fix_rootP = &segment_info[seg].fix_root;
-  seg_fix_tailP = &segment_info[seg].fix_tail;
-#else
-  if (seg == SEG_DATA)
-    {
-      seg_fix_rootP = &data_fix_root;
-      seg_fix_tailP = &data_fix_tail;
-    }
-  else if (seg == SEG_TEXT)
-    {
-      seg_fix_rootP = &text_fix_root;
-      seg_fix_tailP = &text_fix_tail;
-    }
-  else
+  seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg);
+  if (! seginfo)
     {
-      know (seg == SEG_BSS);
-      seg_fix_rootP = &bss_fix_root;
-      seg_fix_tailP = &bss_fix_tail;
+      seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo));
+      memset ((PTR) seginfo, 0, sizeof (*seginfo));
+      seginfo->fix_root = NULL;
+      seginfo->fix_tail = NULL;
+      seginfo->bfd_section = seg;
+      seginfo->sym = 0;
+      if (seg == bfd_abs_section_ptr)
+	abs_seg_info = seginfo;
+      else if (seg == bfd_und_section_ptr)
+	und_seg_info = seginfo;
+      else
+	bfd_set_section_userdata (stdoutput, seg, (PTR) seginfo);
     }
-
-#endif
-#endif
 }
 
 static void
@@ -274,13 +174,13 @@ subseg_set_rest (segT seg, subsegT subseg)
       /*
        * This should be the only code that creates a frchainS.
        */
+      segment_info_type *seginfo;
+
       newP = (frchainS *) obstack_alloc (&frchains, sizeof (frchainS));
       newP->frch_subseg = subseg;
       newP->frch_seg = seg;
-#ifdef BFD_ASSEMBLER
       newP->fix_root = NULL;
       newP->fix_tail = NULL;
-#endif
       obstack_begin (&newP->frch_obstack, chunksize);
 #if __GNUC__ >= 2
       obstack_alignment_mask (&newP->frch_obstack) = __alignof__ (fragS) - 1;
@@ -293,14 +193,9 @@ subseg_set_rest (segT seg, subsegT subseg)
       *lastPP = newP;
       newP->frch_next = frcP;	/* perhaps NULL */
 
-#ifdef BFD_ASSEMBLER
-      {
-	segment_info_type *seginfo;
-	seginfo = seg_info (seg);
-	if (seginfo && seginfo->frchainP == frcP)
-	  seginfo->frchainP = newP;
-      }
-#endif
+      seginfo = seg_info (seg);
+      if (seginfo && (!seginfo->frchainP || seginfo->frchainP == frcP))
+	seginfo->frchainP = newP;
 
       frcP = newP;
     }
@@ -329,73 +224,6 @@ subseg_set_rest (segT seg, subsegT subseg)
  *	Frchain_root updated if needed.
  */
 
-#ifndef BFD_ASSEMBLER
-
-segT
-subseg_new (segname, subseg)
-     const char *segname;
-     subsegT subseg;
-{
-  int i;
-
-  for (i = 0; i < (int) SEG_MAXIMUM_ORDINAL; i++)
-    {
-      const char *s;
-
-      s = segment_name ((segT) i);
-      if (strcmp (segname, s) == 0
-	  || (segname[0] == '.'
-	      && strcmp (segname + 1, s) == 0))
-	{
-	  subseg_set ((segT) i, subseg);
-	  return (segT) i;
-	}
-#ifdef obj_segment_name
-      s = obj_segment_name ((segT) i);
-      if (strcmp (segname, s) == 0
-	  || (segname[0] == '.'
-	      && strcmp (segname + 1, s) == 0))
-	{
-	  subseg_set ((segT) i, subseg);
-	  return (segT) i;
-	}
-#endif
-    }
-
-#ifdef obj_add_segment
-  {
-    segT new_seg;
-    new_seg = obj_add_segment (segname);
-    subseg_set (new_seg, subseg);
-    return new_seg;
-  }
-#else
-  as_bad (_("attempt to switch to nonexistent segment \"%s\""), segname);
-  return now_seg;
-#endif
-}
-
-void
-subseg_set (seg, subseg)	/* begin assembly for a new sub-segment */
-     register segT seg;		/* SEG_DATA or SEG_TEXT */
-     register subsegT subseg;
-{
-#ifndef MANY_SEGMENTS
-  know (seg == SEG_DATA
-	|| seg == SEG_TEXT
-	|| seg == SEG_BSS
-	|| seg == SEG_ABSOLUTE);
-#endif
-
-  if (seg != now_seg || subseg != now_subseg)
-    {				/* we just changed sub-segments */
-      subseg_set_rest (seg, subseg);
-    }
-  mri_common_symbol = NULL;
-}
-
-#else /* BFD_ASSEMBLER */
-
 segT
 subseg_get (const char *segname, int force_new)
 {
@@ -523,16 +351,18 @@ section_symbol (segT sec)
     }
   else
     {
-      s = symbol_find_base (sec->symbol->name, 0);
-      if (s == NULL)
+      segT seg;
+      s = symbol_find (sec->symbol->name);
+      /* We have to make sure it is the right symbol when we
+	 have multiple sections with the same section name.  */
+      if (s == NULL
+	  || ((seg = S_GET_SEGMENT (s)) != sec
+	      && seg != undefined_section))
 	s = symbol_new (sec->symbol->name, sec, 0, &zero_address_frag);
-      else
+      else if (seg == undefined_section)
 	{
-	  if (S_GET_SEGMENT (s) == undefined_section)
-	    {
-	      S_SET_SEGMENT (s, sec);
-	      symbol_set_frag (s, &zero_address_frag);
-	    }
+	  S_SET_SEGMENT (s, sec);
+	  symbol_set_frag (s, &zero_address_frag);
 	}
     }
 
@@ -548,49 +378,40 @@ section_symbol (segT sec)
   return s;
 }
 
-#endif /* BFD_ASSEMBLER */
-
 /* Return whether the specified segment is thought to hold text.  */
 
-#ifndef BFD_ASSEMBLER
-const char * const nontext_section_names[] = {
-  ".eh_frame",
-  ".gcc_except_table",
-#ifdef OBJ_COFF
-#ifndef COFF_LONG_SECTION_NAMES
-  ".eh_fram",
-  ".gcc_exc",
-#endif
-#endif
-  NULL
-};
-#endif /* ! BFD_ASSEMBLER */
-
 int
 subseg_text_p (segT sec)
 {
-#ifdef BFD_ASSEMBLER
   return (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) != 0;
-#else /* ! BFD_ASSEMBLER */
-  const char * const *p;
+}
 
-  if (sec == data_section || sec == bss_section || sec == absolute_section)
-    return 0;
+/* Return non zero if SEC has at least one byte of data.  It is
+   possible that we'll return zero even on a non-empty section because
+   we don't know all the fragment types, and it is possible that an
+   fr_fix == 0 one still contributes data.  Think of this as
+   seg_definitely_not_empty_p.  */
 
-  for (p = nontext_section_names; *p != NULL; ++p)
-    {
-      if (strcmp (segment_name (sec), *p) == 0)
-	return 0;
+int
+seg_not_empty_p (segT sec ATTRIBUTE_UNUSED)
+{
+  segment_info_type *seginfo = seg_info (sec);
+  frchainS *chain;
+  fragS *frag;
 
-#ifdef obj_segment_name
-      if (strcmp (obj_segment_name (sec), *p) == 0)
-	return 0;
-#endif
+  if (!seginfo)
+    return 0;
+  
+  for (chain = seginfo->frchainP; chain; chain = chain->frch_next)
+    {
+      for (frag = chain->frch_root; frag; frag = frag->fr_next)
+	if (frag->fr_fix)
+	  return 1;
+      if (obstack_next_free (&chain->frch_obstack)
+	  != chain->frch_last->fr_literal)
+	return 1;
     }
-
-  return 1;
-
-#endif /* ! BFD_ASSEMBLER */
+  return 0;
 }
 
 void
@@ -614,27 +435,6 @@ subsegs_print_statistics (FILE *file)
 
       for (fragp = frchp->frch_root; fragp; fragp = fragp->fr_next)
 	{
-#if 0
-	  switch (fragp->fr_type)
-	    {
-	    case rs_fill:
-	      fprintf (file, "f"); break;
-	    case rs_align:
-	      fprintf (file, "a"); break;
-	    case rs_align_code:
-	      fprintf (file, "c"); break;
-	    case rs_org:
-	      fprintf (file, "o"); break;
-	    case rs_machine_dependent:
-	      fprintf (file, "m"); break;
-	    case rs_space:
-	      fprintf (file, "s"); break;
-	    case 0:
-	      fprintf (file, "0"); break;
-	    default:
-	      fprintf (file, "?"); break;
-	    }
-#endif
 	  count++;
 	}
       fprintf (file, "\n");
diff --git a/gas/subsegs.h b/gas/subsegs.h
index 331c55709f5d..23ab4f9cf48e 100644
--- a/gas/subsegs.h
+++ b/gas/subsegs.h
@@ -1,5 +1,5 @@
 /* subsegs.h -> subsegs.c
-   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000
+   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2003, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /*
  * For every sub-segment the user mentions in the ASsembler program,
@@ -47,10 +47,8 @@ struct frchain			/* control building of a frag chain */
   struct frchain *frch_next;	/* next in chain of struct frchain-s */
   segT frch_seg;		/* SEG_TEXT or SEG_DATA.  */
   subsegT frch_subseg;		/* subsegment number of this chain */
-#ifdef BFD_ASSEMBLER
   fixS *fix_root;		/* Root of fixups for this subsegment.  */
   fixS *fix_tail;		/* Last fixup for this subsegment.  */
-#endif
   struct obstack frch_obstack;	/* for objects in this frag chain */
   fragS *frch_frag_now;		/* frag_now for this subsegment */
 };
@@ -77,30 +75,22 @@ typedef struct segment_info_struct {
 
   int user_stuff;
 
-  /* Fixups for this segment.  If BFD_ASSEMBLER, this is only valid
-     after the frchains are run together.  */
+  /* Fixups for this segment.  This is only valid after the frchains
+     are run together.  */
   fixS *fix_root;
   fixS *fix_tail;
 
-#if defined (MANY_SEGMENTS) && !defined (BFD_ASSEMBLER)
-  struct internal_scnhdr scnhdr;
-  enum linkonce_type linkonce;
-  const char *name;
-#endif
-
   symbolS *dot;
 
   struct lineno_list *lineno_list_head;
   struct lineno_list *lineno_list_tail;
 
-#ifdef BFD_ASSEMBLER
   /* Which BFD section does this gas segment correspond to?  */
   asection *bfd_section;
 
   /* NULL, or pointer to the gas symbol that is the section symbol for
      this section.  sym->bsym and bfd_section->symbol should be the same.  */
   symbolS *sym;
-#endif
 
   union {
     /* Current size of section holding stabs strings.  */
@@ -119,37 +109,7 @@ typedef struct segment_info_struct {
 #endif
 } segment_info_type;
 
-#ifdef BFD_ASSEMBLER
-
 extern segment_info_type *seg_info (segT);
 extern symbolS *section_symbol (segT);
 
-#else /* ! BFD_ASSEMBLER */
-
-#ifdef MANY_SEGMENTS
-
-extern segment_info_type segment_info[];
-
-#define seg_info(SEC)	(&segment_info[SEC])
-
-#else
-
-/* Sentinel for frchain crawling.  Points to the 1st data-segment
-   frchain.  (Which is pointed to by the last text-segment frchain.) */
-extern frchainS *data0_frchainP;
-extern frchainS *bss0_frchainP;
-
-/* Dummy so stuff can compile.  Should never be used.  */
-struct seg_info_trash {
-  struct {
-    unsigned stab_string_size : 1;
-  } stabu;
-  unsigned hadone : 1;
-};
-#define seg_info(S)	(abort (), (struct seg_info_trash *) 0)
-
-#endif
-
-#endif /* ! BFD_ASSEMBLER */
-
 extern void subsegs_print_statistics (FILE *);
diff --git a/gas/symbols.c b/gas/symbols.c
index 761a0208515b..5935a7477ae0 100644
--- a/gas/symbols.c
+++ b/gas/symbols.c
@@ -1,6 +1,6 @@
 /* symbols.c -symbol table-
    Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-   1999, 2000, 2001, 2002, 2003
+   1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* #define DEBUG_SYMS / * to debug symbol list maintenance.  */
 
@@ -59,6 +59,11 @@ symbolS abs_symbol;
 #define LOCAL_LABEL_CHAR	'\002'
 
 struct obstack notes;
+#ifdef USE_UNIQUE
+/* The name of an external symbol which is
+   used to make weak PE symbol names unique.  */
+const char * an_external_name;
+#endif
 
 static char *save_symbol_name (const char *);
 static void fb_label_init (void);
@@ -83,13 +88,11 @@ symbol_new (const char *name, segT segment, valueT valu, fragS *frag)
   symbolS *symbolP = symbol_create (name, segment, valu, frag);
 
   /* Link to end of symbol chain.  */
-#ifdef BFD_ASSEMBLER
   {
     extern int symbol_table_frozen;
     if (symbol_table_frozen)
       abort ();
   }
-#endif
   symbol_append (symbolP, symbol_lastP, &symbol_rootP, &symbol_lastP);
 
   return symbolP;
@@ -108,11 +111,6 @@ save_symbol_name (const char *name)
   obstack_grow (&notes, name, name_length);
   ret = obstack_finish (&notes);
 
-#ifdef STRIP_UNDERSCORE
-  if (ret[0] == '_')
-    ++ret;
-#endif
-
 #ifdef tc_canonicalize_symbol_name
   ret = tc_canonicalize_symbol_name (ret);
 #endif
@@ -144,12 +142,10 @@ symbol_create (const char *name, /* It is copied, the caller can destroy/modify.
   /* symbol must be born in some fixed state.  This seems as good as any.  */
   memset (symbolP, 0, sizeof (symbolS));
 
-#ifdef BFD_ASSEMBLER
   symbolP->bsym = bfd_make_empty_symbol (stdoutput);
   if (symbolP->bsym == NULL)
     as_perror ("%s", "bfd_make_empty_symbol");
   symbolP->bsym->udata.p = (PTR) symbolP;
-#endif
   S_SET_NAME (symbolP, preserved_copy_of_name);
 
   S_SET_SEGMENT (symbolP, segment);
@@ -157,10 +153,6 @@ symbol_create (const char *name, /* It is copied, the caller can destroy/modify.
   symbol_clear_list_pointers (symbolP);
 
   symbolP->sy_frag = frag;
-#ifndef BFD_ASSEMBLER
-  symbolP->sy_number = ~0;
-  symbolP->sy_name_offset = (unsigned int) ~0;
-#endif
 
   obj_symbol_new_hook (symbolP);
 
@@ -171,7 +163,6 @@ symbol_create (const char *name, /* It is copied, the caller can destroy/modify.
   return symbolP;
 }
 
-#ifdef BFD_ASSEMBLER
 
 /* Local symbol support.  If we can get away with it, we keep only a
    small amount of information for local symbols.  */
@@ -197,7 +188,7 @@ static unsigned long local_symbol_conversion_count;
 
 /* Create a local symbol and insert it into the local hash table.  */
 
-struct local_symbol *
+static struct local_symbol *
 local_symbol_make (const char *name, segT section, valueT value, fragS *frag)
 {
   char *name_copy;
@@ -255,13 +246,6 @@ local_symbol_convert (struct local_symbol *locsym)
 
   return ret;
 }
-
-#else /* ! BFD_ASSEMBLER */
-
-#define LOCAL_SYMBOL_CHECK(s) 0
-#define local_symbol_convert(s) ((symbolS *) s)
-
-#endif /* ! BFD_ASSEMBLER */
 
 /* We have just seen "<name>:".
    Creates a struct symbol unless it already exists.
@@ -277,19 +261,9 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 
   /* Sun local labels go out of scope whenever a non-local symbol is
      defined.  */
-  if (LOCAL_LABELS_DOLLAR)
-    {
-      int local;
-
-#ifdef BFD_ASSEMBLER
-      local = bfd_is_local_label_name (stdoutput, sym_name);
-#else
-      local = LOCAL_LABEL (sym_name);
-#endif
-
-      if (! local)
-	dollar_label_clear ();
-    }
+  if (LOCAL_LABELS_DOLLAR
+      && !bfd_is_local_label_name (stdoutput, sym_name))
+    dollar_label_clear ();
 
 #ifndef WORKING_DOT_WORD
   if (new_broken_words)
@@ -299,9 +273,6 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
       fragS *frag_tmp;
       char *frag_opcode;
 
-      extern const int md_short_jump_size;
-      extern const int md_long_jump_size;
-
       if (now_seg == absolute_section)
 	{
 	  as_bad (_("cannot define symbol `%s' in absolute section"), sym_name);
@@ -338,6 +309,7 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 
   if ((symbolP = symbol_find (sym_name)) != 0)
     {
+      S_CLEAR_WEAKREFR (symbolP);
 #ifdef RESOLVE_SYMBOL_REDEFINITION
       if (RESOLVE_SYMBOL_REDEFINITION (symbolP))
 	return symbolP;
@@ -345,7 +317,6 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
       /* Now check for undefined symbols.  */
       if (LOCAL_SYMBOL_CHECK (symbolP))
 	{
-#ifdef BFD_ASSEMBLER
 	  struct local_symbol *locsym = (struct local_symbol *) symbolP;
 
 	  if (locsym->lsy_section != undefined_section
@@ -360,10 +331,20 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 	  locsym->lsy_section = now_seg;
 	  local_symbol_set_frag (locsym, frag_now);
 	  locsym->lsy_value = frag_now_fix ();
-#endif
 	}
-      else if (!S_IS_DEFINED (symbolP) || S_IS_COMMON (symbolP))
+      else if (!(S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP))
+	       || S_IS_COMMON (symbolP)
+	       || S_IS_VOLATILE (symbolP))
 	{
+	  if (S_IS_VOLATILE (symbolP)
+	      /* This could be avoided when the symbol wasn't used so far, but
+		 the comment in struc-symbol.h says this flag isn't reliable.  */
+	      && (1 || !symbol_used_p (symbolP)))
+	    {
+	      symbolP = symbol_clone (symbolP, 1);
+	      S_SET_VALUE (symbolP, 0);
+	      S_CLEAR_VOLATILE (symbolP);
+	    }
 	  if (S_GET_VALUE (symbolP) == 0)
 	    {
 	      symbolP->sy_frag = frag_now;
@@ -395,6 +376,7 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 		    && S_IS_EXTERNAL (symbolP))
 		   || S_GET_SEGMENT (symbolP) == bss_section)
 		  && (now_seg == data_section
+		      || now_seg == bss_section
 		      || now_seg == S_GET_SEGMENT (symbolP)))
 		{
 		  /* Select which of the 2 cases this is.  */
@@ -431,9 +413,7 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 #else
 		  char od_buf[100];
 		  od_buf[0] = '\0';
-#ifdef BFD_ASSEMBLER
 		  if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
-#endif
 		    sprintf (od_buf, "%d.%d.",
 			     S_GET_OTHER (symbolP),
 			     S_GET_DESC (symbolP));
@@ -452,18 +432,19 @@ colon (/* Just seen "x:" - rattle symbols & frags.  */
 	  if (!(frag_now == symbolP->sy_frag
 		&& S_GET_VALUE (symbolP) == frag_now_fix ()
 		&& S_GET_SEGMENT (symbolP) == now_seg))
-	    as_bad (_("symbol `%s' is already defined"), sym_name);
+	    {
+	      as_bad (_("symbol `%s' is already defined"), sym_name);
+	      symbolP = symbol_clone (symbolP, 0);
+	    }
 	}
 
     }
-#ifdef BFD_ASSEMBLER
   else if (! flag_keep_locals && bfd_is_local_label_name (stdoutput, sym_name))
     {
       symbolP = (symbolS *) local_symbol_make (sym_name, now_seg,
 					       (valueT) frag_now_fix (),
 					       frag_now);
     }
-#endif /* BFD_ASSEMBLER */
   else
     {
       symbolP = symbol_new (sym_name, now_seg, (valueT) frag_now_fix (),
@@ -538,7 +519,6 @@ symbol_find_or_make (const char *name)
 
   if (symbolP == NULL)
     {
-#ifdef BFD_ASSEMBLER
       if (! flag_keep_locals && bfd_is_local_label_name (stdoutput, name))
 	{
 	  symbolP = md_undefined_symbol ((char *) name);
@@ -550,7 +530,6 @@ symbol_find_or_make (const char *name)
 						   &zero_address_frag);
 	  return symbolP;
 	}
-#endif
 
       symbolP = symbol_make (name);
 
@@ -575,6 +554,114 @@ symbol_make (const char *name)
 }
 
 symbolS *
+symbol_clone (symbolS *orgsymP, int replace)
+{
+  symbolS *newsymP;
+  asymbol *bsymorg, *bsymnew;
+
+  /* Running local_symbol_convert on a clone that's not the one currently
+     in local_hash would incorrectly replace the hash entry.  Thus the
+     symbol must be converted here.  Note that the rest of the function
+     depends on not encountering an unconverted symbol.  */
+  if (LOCAL_SYMBOL_CHECK (orgsymP))
+    orgsymP = local_symbol_convert ((struct local_symbol *) orgsymP);
+  bsymorg = orgsymP->bsym;
+
+  know (S_IS_DEFINED (orgsymP));
+
+  newsymP = obstack_alloc (&notes, sizeof (*newsymP));
+  *newsymP = *orgsymP;
+  bsymnew = bfd_make_empty_symbol (bfd_asymbol_bfd (bsymorg));
+  if (bsymnew == NULL)
+    as_perror ("%s", "bfd_make_empty_symbol");
+  newsymP->bsym = bsymnew;
+  bsymnew->name = bsymorg->name;
+  bsymnew->flags =  bsymorg->flags;
+  bsymnew->section =  bsymorg->section;
+  bsymnew->udata.p = (PTR) newsymP;
+  bfd_copy_private_symbol_data (bfd_asymbol_bfd (bsymorg), bsymorg,
+				bfd_asymbol_bfd (bsymnew), bsymnew);
+
+#ifdef obj_symbol_clone_hook
+  obj_symbol_clone_hook (newsymP, orgsymP);
+#endif
+
+#ifdef tc_symbol_clone_hook
+  tc_symbol_clone_hook (newsymP, orgsymP);
+#endif
+
+  if (replace)
+    {
+      if (symbol_rootP == orgsymP)
+	symbol_rootP = newsymP;
+      else if (orgsymP->sy_previous)
+	{
+	  orgsymP->sy_previous->sy_next = newsymP;
+	  orgsymP->sy_previous = NULL;
+	}
+      if (symbol_lastP == orgsymP)
+	symbol_lastP = newsymP;
+      else if (orgsymP->sy_next)
+	orgsymP->sy_next->sy_previous = newsymP;
+      orgsymP->sy_next = NULL;
+      debug_verify_symchain (symbol_rootP, symbol_lastP);
+
+      symbol_table_insert (newsymP);
+    }
+
+  return newsymP;
+}
+
+/* Referenced symbols, if they are forward references, need to be cloned
+   (without replacing the original) so that the value of the referenced
+   symbols at the point of use .  */
+
+#undef symbol_clone_if_forward_ref
+symbolS *
+symbol_clone_if_forward_ref (symbolS *symbolP, int is_forward)
+{
+  if (symbolP && !LOCAL_SYMBOL_CHECK (symbolP))
+    {
+      symbolS *add_symbol = symbolP->sy_value.X_add_symbol;
+      symbolS *op_symbol = symbolP->sy_value.X_op_symbol;
+
+      if (symbolP->sy_forward_ref)
+	is_forward = 1;
+
+      if (is_forward)
+	{
+	  /* assign_symbol() clones volatile symbols; pre-existing expressions
+	     hold references to the original instance, but want the current
+	     value.  Just repeat the lookup.  */
+	  if (add_symbol && S_IS_VOLATILE (add_symbol))
+	    add_symbol = symbol_find_exact (S_GET_NAME (add_symbol));
+	  if (op_symbol && S_IS_VOLATILE (op_symbol))
+	    op_symbol = symbol_find_exact (S_GET_NAME (op_symbol));
+	}
+
+      /* Re-using sy_resolving here, as this routine cannot get called from
+	 symbol resolution code.  */
+      if (symbolP->bsym->section == expr_section && !symbolP->sy_resolving)
+	{
+	  symbolP->sy_resolving = 1;
+	  add_symbol = symbol_clone_if_forward_ref (add_symbol, is_forward);
+	  op_symbol = symbol_clone_if_forward_ref (op_symbol, is_forward);
+	  symbolP->sy_resolving = 0;
+	}
+
+      if (symbolP->sy_forward_ref
+	  || add_symbol != symbolP->sy_value.X_add_symbol
+	  || op_symbol != symbolP->sy_value.X_op_symbol)
+	symbolP = symbol_clone (symbolP, 0);
+
+      symbolP->sy_value.X_add_symbol = add_symbol;
+      symbolP->sy_value.X_op_symbol = op_symbol;
+    }
+
+  return symbolP;
+}
+
+symbolS *
 symbol_temp_new (segT seg, valueT ofs, fragS *frag)
 {
   return symbol_new (FAKE_LABEL_NAME, seg, ofs, frag);
@@ -598,37 +685,43 @@ symbol_temp_make (void)
    of a struct symbol associated with that name.  */
 
 symbolS *
-symbol_find (const char *name)
+symbol_find_exact (const char *name)
 {
-#ifdef STRIP_UNDERSCORE
-  return (symbol_find_base (name, 1));
-#else /* STRIP_UNDERSCORE */
-  return (symbol_find_base (name, 0));
-#endif /* STRIP_UNDERSCORE */
+  return symbol_find_exact_noref (name, 0);
 }
 
 symbolS *
-symbol_find_exact (const char *name)
+symbol_find_exact_noref (const char *name, int noref)
 {
-#ifdef BFD_ASSEMBLER
-  {
-    struct local_symbol *locsym;
+  struct local_symbol *locsym;
+  symbolS* sym;
 
-    locsym = (struct local_symbol *) hash_find (local_hash, name);
-    if (locsym != NULL)
-      return (symbolS *) locsym;
-  }
-#endif
+  locsym = (struct local_symbol *) hash_find (local_hash, name);
+  if (locsym != NULL)
+    return (symbolS *) locsym;
+
+  sym = ((symbolS *) hash_find (sy_hash, name));
+
+  /* Any references to the symbol, except for the reference in
+     .weakref, must clear this flag, such that the symbol does not
+     turn into a weak symbol.  Note that we don't have to handle the
+     local_symbol case, since a weakrefd is always promoted out of the
+     local_symbol table when it is turned into a weak symbol.  */
+  if (sym && ! noref)
+    S_CLEAR_WEAKREFD (sym);
 
-  return ((symbolS *) hash_find (sy_hash, name));
+  return sym;
 }
 
 symbolS *
-symbol_find_base (const char *name, int strip_underscore)
+symbol_find (const char *name)
 {
-  if (strip_underscore && *name == '_')
-    name++;
+  return symbol_find_noref (name, 0);
+}
 
+symbolS *
+symbol_find_noref (const char *name, int noref)
+{
 #ifdef tc_canonicalize_symbol_name
   {
     char *copy;
@@ -656,7 +749,7 @@ symbol_find_base (const char *name, int strip_underscore)
       *copy = '\0';
     }
 
-  return symbol_find_exact (name);
+  return symbol_find_exact_noref (name, noref);
 }
 
 /* Once upon a time, symbols were kept in a singly linked list.  At
@@ -681,9 +774,7 @@ symbol_append (symbolS *addme, symbolS *target,
       know (*rootPP == NULL);
       know (*lastPP == NULL);
       addme->sy_next = NULL;
-#ifdef SYMBOLS_NEED_BACKPOINTERS
       addme->sy_previous = NULL;
-#endif
       *rootPP = addme;
       *lastPP = addme;
       return;
@@ -691,9 +782,7 @@ symbol_append (symbolS *addme, symbolS *target,
 
   if (target->sy_next != NULL)
     {
-#ifdef SYMBOLS_NEED_BACKPOINTERS
       target->sy_next->sy_previous = addme;
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
     }
   else
     {
@@ -703,10 +792,7 @@ symbol_append (symbolS *addme, symbolS *target,
 
   addme->sy_next = target->sy_next;
   target->sy_next = addme;
-
-#ifdef SYMBOLS_NEED_BACKPOINTERS
   addme->sy_previous = target;
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
 
   debug_verify_symchain (symbol_rootP, symbol_lastP);
 }
@@ -719,12 +805,9 @@ symbol_clear_list_pointers (symbolS *symbolP)
   if (LOCAL_SYMBOL_CHECK (symbolP))
     abort ();
   symbolP->sy_next = NULL;
-#ifdef SYMBOLS_NEED_BACKPOINTERS
   symbolP->sy_previous = NULL;
-#endif
 }
 
-#ifdef SYMBOLS_NEED_BACKPOINTERS
 /* Remove SYMBOLP from the list.  */
 
 void
@@ -784,8 +867,6 @@ symbol_insert (symbolS *addme, symbolS *target,
   debug_verify_symchain (*rootPP, *lastPP);
 }
 
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
-
 void
 verify_symbol_chain (symbolS *rootP, symbolS *lastP)
 {
@@ -796,33 +877,13 @@ verify_symbol_chain (symbolS *rootP, symbolS *lastP)
 
   for (; symbol_next (symbolP) != NULL; symbolP = symbol_next (symbolP))
     {
-#ifdef BFD_ASSEMBLER
       assert (symbolP->bsym != NULL);
-#endif
-#ifdef SYMBOLS_NEED_BACKPOINTERS
       assert (symbolP->sy_next->sy_previous == symbolP);
-#else
-      /* Walk the list anyways, to make sure pointers are still good.  */
-      ;
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
     }
 
   assert (lastP == symbolP);
 }
 
-void
-verify_symbol_chain_2 (symbolS *sym)
-{
-  symbolS *p = sym, *n = sym;
-#ifdef SYMBOLS_NEED_BACKPOINTERS
-  while (symbol_previous (p))
-    p = symbol_previous (p);
-#endif
-  while (symbol_next (n))
-    n = symbol_next (n);
-  verify_symbol_chain (p, n);
-}
-
 static void
 report_op_error (symbolS *symp, symbolS *left, symbolS *right)
 {
@@ -867,13 +928,11 @@ report_op_error (symbolS *symp, symbolS *left, symbolS *right)
 	  && seg_right != undefined_section)
 	{
 	  if (right)
-	    as_bad_where (file, line,
-			  _("invalid sections for operation on `%s' and `%s' setting `%s'"),
-			  S_GET_NAME (left), S_GET_NAME (right), S_GET_NAME (symp));
+	    as_bad (_("invalid sections for operation on `%s' and `%s' setting `%s'"),
+		    S_GET_NAME (left), S_GET_NAME (right), S_GET_NAME (symp));
 	  else
-	    as_bad_where (file, line,
-			  _("invalid section for operation on `%s' setting `%s'"),
-			  S_GET_NAME (left), S_GET_NAME (symp));
+	    as_bad (_("invalid section for operation on `%s' setting `%s'"),
+		    S_GET_NAME (left), S_GET_NAME (symp));
 	}
     }
 }
@@ -889,7 +948,6 @@ resolve_symbol_value (symbolS *symp)
   valueT final_val = 0;
   segT final_seg;
 
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (symp))
     {
       struct local_symbol *locsym = (struct local_symbol *) symp;
@@ -908,7 +966,6 @@ resolve_symbol_value (symbolS *symp)
 
       return final_val;
     }
-#endif
 
   if (symp->sy_resolved)
     {
@@ -935,6 +992,7 @@ resolve_symbol_value (symbolS *symp)
       offsetT left, right;
       segT seg_left, seg_right;
       operatorT op;
+      int move_seg_ok;
 
       symp->sy_resolving = 1;
 
@@ -969,6 +1027,19 @@ resolve_symbol_value (symbolS *symp)
 	    symp->sy_value.X_op_symbol = NULL;
 
 	do_symbol:
+	  if (S_IS_WEAKREFR (symp))
+	    {
+	      assert (final_val == 0);
+	      if (S_IS_WEAKREFR (add_symbol))
+		{
+		  assert (add_symbol->sy_value.X_op == O_symbol
+			  && add_symbol->sy_value.X_add_number == 0);
+		  add_symbol = add_symbol->sy_value.X_add_symbol;
+		  assert (! S_IS_WEAKREFR (add_symbol));
+		  symp->sy_value.X_add_symbol = add_symbol;
+		}
+	    }
+
 	  if (symp->sy_mri_common)
 	    {
 	      /* This is a symbol inside an MRI common section.  The
@@ -992,7 +1063,11 @@ resolve_symbol_value (symbolS *symp)
 	     relocation to detect this case, and convert the
 	     relocation to be against the symbol to which this symbol
 	     is equated.  */
-	  if (! S_IS_DEFINED (add_symbol) || S_IS_COMMON (add_symbol))
+	  if (! S_IS_DEFINED (add_symbol)
+#if defined (OBJ_COFF) && defined (TE_PE)
+	      || S_IS_WEAK (add_symbol)
+#endif
+	      || S_IS_COMMON (add_symbol))
 	    {
 	      if (finalize_syms)
 		{
@@ -1034,6 +1109,8 @@ resolve_symbol_value (symbolS *symp)
 	    }
 
 	  resolved = symbol_resolved_p (add_symbol);
+	  if (S_IS_WEAKREFR (symp))
+	    goto exit_dont_set_value;
 	  break;
 
 	case O_uminus:
@@ -1116,18 +1193,15 @@ resolve_symbol_value (symbolS *symp)
 		}
 	    }
 
+	  move_seg_ok = 1;
 	  /* Equality and non-equality tests are permitted on anything.
 	     Subtraction, and other comparison operators are permitted if
 	     both operands are in the same section.  Otherwise, both
 	     operands must be absolute.  We already handled the case of
 	     addition or subtraction of a constant above.  This will
 	     probably need to be changed for an object file format which
-	     supports arbitrary expressions, such as IEEE-695.
-
-	     Don't emit messages unless we're finalizing the symbol value,
-	     otherwise we may get the same message multiple times.  */
-	  if (finalize_syms
-	      && !(seg_left == absolute_section
+	     supports arbitrary expressions, such as IEEE-695.  */
+	  if (!(seg_left == absolute_section
 		   && seg_right == absolute_section)
 	      && !(op == O_eq || op == O_ne)
 	      && !((op == O_subtract
@@ -1135,9 +1209,21 @@ resolve_symbol_value (symbolS *symp)
 		   && seg_left == seg_right
 		   && (seg_left != undefined_section
 		       || add_symbol == op_symbol)))
-	    report_op_error (symp, add_symbol, op_symbol);
+	    {
+	      /* Don't emit messages unless we're finalizing the symbol value,
+		 otherwise we may get the same message multiple times.  */
+	      if (finalize_syms)
+		report_op_error (symp, add_symbol, op_symbol);
+	      /* However do not move the symbol into the absolute section
+		 if it cannot currently be resolved - this would confuse
+		 other parts of the assembler into believing that the
+		 expression had been evaluated to zero.  */
+	      else
+		move_seg_ok = 0;
+	    }
 
-	  if (final_seg == expr_section || final_seg == undefined_section)
+	  if (move_seg_ok
+	      && (final_seg == expr_section || final_seg == undefined_section))
 	    final_seg = absolute_section;
 
 	  /* Check for division by zero.  */
@@ -1226,11 +1312,6 @@ resolve_symbol_value (symbolS *symp)
 exit_dont_set_value:
   /* Always set the segment, even if not finalizing the value.
      The segment is used to determine whether a symbol is defined.  */
-#if defined (OBJ_AOUT) && ! defined (BFD_ASSEMBLER)
-  /* The old a.out backend does not handle S_SET_SEGMENT correctly
-     for a stab symbol, so we use this bad hack.  */
-  if (final_seg != S_GET_SEGMENT (symp))
-#endif
     S_SET_SEGMENT (symp, final_seg);
 
   /* Don't worry if we can't resolve an expr_section symbol.  */
@@ -1249,8 +1330,6 @@ exit_dont_set_value:
   return final_val;
 }
 
-#ifdef BFD_ASSEMBLER
-
 static void resolve_local_symbol (const char *, PTR);
 
 /* A static function passed to hash_traverse.  */
@@ -1262,16 +1341,80 @@ resolve_local_symbol (const char *key ATTRIBUTE_UNUSED, PTR value)
     resolve_symbol_value (value);
 }
 
-#endif
-
 /* Resolve all local symbols.  */
 
 void
 resolve_local_symbol_values (void)
 {
-#ifdef BFD_ASSEMBLER
   hash_traverse (local_hash, resolve_local_symbol);
-#endif
+}
+
+/* Obtain the current value of a symbol without changing any
+   sub-expressions used.  */
+
+int
+snapshot_symbol (symbolS **symbolPP, valueT *valueP, segT *segP, fragS **fragPP)
+{
+  symbolS *symbolP = *symbolPP;
+
+  if (LOCAL_SYMBOL_CHECK (symbolP))
+    {
+      struct local_symbol *locsym = (struct local_symbol *) symbolP;
+
+      *valueP = locsym->lsy_value;
+      *segP = locsym->lsy_section;
+      *fragPP = local_symbol_get_frag (locsym);
+    }
+  else
+    {
+      expressionS expr = symbolP->sy_value;
+
+      if (!symbolP->sy_resolved && expr.X_op != O_illegal)
+	{
+	  int resolved;
+
+	  if (symbolP->sy_resolving)
+	    return 0;
+	  symbolP->sy_resolving = 1;
+	  resolved = resolve_expression (&expr);
+	  symbolP->sy_resolving = 0;
+	  if (!resolved)
+	    return 0;
+
+	  switch (expr.X_op)
+	    {
+	    case O_constant:
+	    case O_register:
+	      if (!symbol_equated_p (symbolP))
+		break;
+	      /* Fall thru.  */
+	    case O_symbol:
+	    case O_symbol_rva:
+	      symbolP = expr.X_add_symbol;
+	      break;
+	    default:
+	      return 0;
+	    }
+	}
+
+      /* Never change a defined symbol.  */
+      if (symbolP->bsym->section == undefined_section
+	  || symbolP->bsym->section == expr_section)
+	*symbolPP = symbolP;
+      *valueP = expr.X_add_number;
+      *segP = symbolP->bsym->section;
+      *fragPP = symbolP->sy_frag;
+
+      if (*segP == expr_section)
+	switch (expr.X_op)
+	  {
+	  case O_constant: *segP = absolute_section; break;
+	  case O_register: *segP = reg_section; break;
+	  default: break;
+	  }
+    }
+
+  return 1;
 }
 
 /* Dollar labels look like a number followed by a dollar sign.  Eg, "42$".
@@ -1555,7 +1698,11 @@ fb_label_name (long n,	/* We just saw "n:", "nf" or "nb" : n a number.  */
   char symbol_name_temporary[20];	/* Build up a number, BACKWARDS.  */
 
   know (n >= 0);
-  know (augend == 0 || augend == 1);
+#ifdef TC_MMIX
+  know ((unsigned long) augend <= 2 /* See mmix_fb_label.  */);
+#else
+  know ((unsigned long) augend <= 1);
+#endif
   p = symbol_name_build;
 #ifdef LOCAL_LABEL_PREFIX
   *p++ = LOCAL_LABEL_PREFIX;
@@ -1636,10 +1783,8 @@ decode_local_label_name (char *s)
 valueT
 S_GET_VALUE (symbolS *s)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     return resolve_symbol_value (s);
-#endif
 
   if (!s->sy_resolved)
     {
@@ -1647,22 +1792,16 @@ S_GET_VALUE (symbolS *s)
       if (!finalize_syms)
 	return val;
     }
+  if (S_IS_WEAKREFR (s))
+    return S_GET_VALUE (s->sy_value.X_add_symbol);
+
   if (s->sy_value.X_op != O_constant)
     {
-      static symbolS *recur;
-
-      /* FIXME: In non BFD assemblers, S_IS_DEFINED and S_IS_COMMON
-	 may call S_GET_VALUE.  We use a static symbol to avoid the
-	 immediate recursion.  */
-      if (recur == s)
-	return (valueT) s->sy_value.X_add_number;
-      recur = s;
       if (! s->sy_resolved
 	  || s->sy_value.X_op != O_symbol
 	  || (S_IS_DEFINED (s) && ! S_IS_COMMON (s)))
 	as_bad (_("attempt to get value of unresolved symbol `%s'"),
 		S_GET_NAME (s));
-      recur = NULL;
     }
   return (valueT) s->sy_value.X_add_number;
 }
@@ -1672,17 +1811,16 @@ S_GET_VALUE (symbolS *s)
 void
 S_SET_VALUE (symbolS *s, valueT val)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     {
       ((struct local_symbol *) s)->lsy_value = val;
       return;
     }
-#endif
 
   s->sy_value.X_op = O_constant;
   s->sy_value.X_add_number = (offsetT) val;
   s->sy_value.X_unsigned = 0;
+  S_CLEAR_WEAKREFR (s);
 }
 
 void
@@ -1693,20 +1831,16 @@ copy_symbol_attributes (symbolS *dest, symbolS *src)
   if (LOCAL_SYMBOL_CHECK (src))
     src = local_symbol_convert ((struct local_symbol *) src);
 
-#ifdef BFD_ASSEMBLER
   /* In an expression, transfer the settings of these flags.
      The user can override later, of course.  */
 #define COPIED_SYMFLAGS	(BSF_FUNCTION | BSF_OBJECT)
   dest->bsym->flags |= src->bsym->flags & COPIED_SYMFLAGS;
-#endif
 
 #ifdef OBJ_COPY_SYMBOL_ATTRIBUTES
   OBJ_COPY_SYMBOL_ATTRIBUTES (dest, src);
 #endif
 }
 
-#ifdef BFD_ASSEMBLER
-
 int
 S_IS_FUNCTION (symbolS *s)
 {
@@ -1742,10 +1876,32 @@ S_IS_WEAK (symbolS *s)
 {
   if (LOCAL_SYMBOL_CHECK (s))
     return 0;
+  /* Conceptually, a weakrefr is weak if the referenced symbol is.  We
+     could probably handle a WEAKREFR as always weak though.  E.g., if
+     the referenced symbol has lost its weak status, there's no reason
+     to keep handling the weakrefr as if it was weak.  */
+  if (S_IS_WEAKREFR (s))
+    return S_IS_WEAK (s->sy_value.X_add_symbol);
   return (s->bsym->flags & BSF_WEAK) != 0;
 }
 
 int
+S_IS_WEAKREFR (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_weakrefr != 0;
+}
+
+int
+S_IS_WEAKREFD (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_weakrefd != 0;
+}
+
+int
 S_IS_COMMON (symbolS *s)
 {
   if (LOCAL_SYMBOL_CHECK (s))
@@ -1812,7 +1968,9 @@ S_IS_LOCAL (symbolS *s)
     return 1;
 
   if (flag_strip_local_absolute
-      && (flags & BSF_GLOBAL) == 0
+      /* Keep BSF_FILE symbols in order to allow debuggers to identify
+	 the source file even when the object file is stripped.  */
+      && (flags & (BSF_GLOBAL | BSF_FILE)) == 0
       && bfd_get_section (s->bsym) == absolute_section)
     return 1;
 
@@ -1829,15 +1987,25 @@ S_IS_LOCAL (symbolS *s)
 }
 
 int
-S_IS_EXTERN (symbolS *s)
+S_IS_STABD (symbolS *s)
 {
-  return S_IS_EXTERNAL (s);
+  return S_GET_NAME (s) == 0;
 }
 
 int
-S_IS_STABD (symbolS *s)
+S_IS_VOLATILE (const symbolS *s)
 {
-  return S_GET_NAME (s) == 0;
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_volatile;
+}
+
+int
+S_IS_FORWARD_REF (const symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return 0;
+  return s->sy_forward_ref;
 }
 
 const char *
@@ -1906,6 +2074,11 @@ S_SET_EXTERNAL (symbolS *s)
     }
   s->bsym->flags |= BSF_GLOBAL;
   s->bsym->flags &= ~(BSF_LOCAL | BSF_WEAK);
+
+#ifdef USE_UNIQUE
+  if (! an_external_name && S_GET_NAME(s)[0] != '.')
+    an_external_name = S_GET_NAME (s);
+#endif
 }
 
 void
@@ -1927,11 +2100,71 @@ S_SET_WEAK (symbolS *s)
 {
   if (LOCAL_SYMBOL_CHECK (s))
     s = local_symbol_convert ((struct local_symbol *) s);
+#ifdef obj_set_weak_hook
+  obj_set_weak_hook (s);
+#endif
   s->bsym->flags |= BSF_WEAK;
   s->bsym->flags &= ~(BSF_GLOBAL | BSF_LOCAL);
 }
 
 void
+S_SET_WEAKREFR (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    s = local_symbol_convert ((struct local_symbol *) s);
+  s->sy_weakrefr = 1;
+  /* If the alias was already used, make sure we mark the target as
+     used as well, otherwise it might be dropped from the symbol
+     table.  This may have unintended side effects if the alias is
+     later redirected to another symbol, such as keeping the unused
+     previous target in the symbol table.  Since it will be weak, it's
+     not a big deal.  */
+  if (s->sy_used)
+    symbol_mark_used (s->sy_value.X_add_symbol);
+}
+
+void
+S_CLEAR_WEAKREFR (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return;
+  s->sy_weakrefr = 0;
+}
+
+void
+S_SET_WEAKREFD (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    s = local_symbol_convert ((struct local_symbol *) s);
+  s->sy_weakrefd = 1;
+  S_SET_WEAK (s);
+}
+
+void
+S_CLEAR_WEAKREFD (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return;
+  if (s->sy_weakrefd)
+    {
+      s->sy_weakrefd = 0;
+      /* If a weakref target symbol is weak, then it was never
+	 referenced directly before, not even in a .global directive,
+	 so decay it to local.  If it remains undefined, it will be
+	 later turned into a global, like any other undefined
+	 symbol.  */
+      if (s->bsym->flags & BSF_WEAK)
+	{
+#ifdef obj_clear_weak_hook
+	  obj_clear_weak_hook (s);
+#endif
+	  s->bsym->flags &= ~BSF_WEAK;
+	  s->bsym->flags |= BSF_LOCAL;
+	}
+    }
+}
+
+void
 S_SET_THREAD_LOCAL (symbolS *s)
 {
   if (LOCAL_SYMBOL_CHECK (s))
@@ -1950,7 +2183,7 @@ S_SET_THREAD_LOCAL (symbolS *s)
 }
 
 void
-S_SET_NAME (symbolS *s, char *name)
+S_SET_NAME (symbolS *s, const char *name)
 {
   if (LOCAL_SYMBOL_CHECK (s))
     {
@@ -1959,9 +2192,29 @@ S_SET_NAME (symbolS *s, char *name)
     }
   s->bsym->name = name;
 }
-#endif /* BFD_ASSEMBLER */
 
-#ifdef SYMBOLS_NEED_BACKPOINTERS
+void
+S_SET_VOLATILE (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    s = local_symbol_convert ((struct local_symbol *) s);
+  s->sy_volatile = 1;
+}
+
+void
+S_CLEAR_VOLATILE (symbolS *s)
+{
+  if (!LOCAL_SYMBOL_CHECK (s))
+    s->sy_volatile = 0;
+}
+
+void
+S_SET_FORWARD_REF (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    s = local_symbol_convert ((struct local_symbol *) s);
+  s->sy_forward_ref = 1;
+}
 
 /* Return the previous symbol in a chain.  */
 
@@ -1973,8 +2226,6 @@ symbol_previous (symbolS *s)
   return s->sy_previous;
 }
 
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
-
 /* Return the next symbol in a chain.  */
 
 symbolS *
@@ -2003,6 +2254,18 @@ symbol_set_value_expression (symbolS *s, const expressionS *exp)
   if (LOCAL_SYMBOL_CHECK (s))
     s = local_symbol_convert ((struct local_symbol *) s);
   s->sy_value = *exp;
+  S_CLEAR_WEAKREFR (s);
+}
+
+/* Return a pointer to the X_add_number component of a symbol.  */
+
+offsetT *
+symbol_X_add_number (symbolS *s)
+{
+  if (LOCAL_SYMBOL_CHECK (s))
+    return (offsetT *) &((struct local_symbol *) s)->lsy_value;
+
+  return &s->sy_value.X_add_number;
 }
 
 /* Set the value of SYM to the current position in the current segment.  */
@@ -2020,14 +2283,13 @@ symbol_set_value_now (symbolS *sym)
 void
 symbol_set_frag (symbolS *s, fragS *f)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     {
       local_symbol_set_frag ((struct local_symbol *) s, f);
       return;
     }
-#endif
   s->sy_frag = f;
+  S_CLEAR_WEAKREFR (s);
 }
 
 /* Return the frag of a symbol.  */
@@ -2035,10 +2297,8 @@ symbol_set_frag (symbolS *s, fragS *f)
 fragS *
 symbol_get_frag (symbolS *s)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     return local_symbol_get_frag ((struct local_symbol *) s);
-#endif
   return s->sy_frag;
 }
 
@@ -2050,6 +2310,8 @@ symbol_mark_used (symbolS *s)
   if (LOCAL_SYMBOL_CHECK (s))
     return;
   s->sy_used = 1;
+  if (S_IS_WEAKREFR (s))
+    symbol_mark_used (s->sy_value.X_add_symbol);
 }
 
 /* Clear the mark of whether a symbol has been used.  */
@@ -2167,13 +2429,11 @@ symbol_written_p (symbolS *s)
 void
 symbol_mark_resolved (symbolS *s)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     {
       local_symbol_mark_resolved ((struct local_symbol *) s);
       return;
     }
-#endif
   s->sy_resolved = 1;
 }
 
@@ -2182,10 +2442,8 @@ symbol_mark_resolved (symbolS *s)
 int
 symbol_resolved_p (symbolS *s)
 {
-#ifdef BFD_ASSEMBLER
   if (LOCAL_SYMBOL_CHECK (s))
     return local_symbol_resolved_p ((struct local_symbol *) s);
-#endif
   return s->sy_resolved;
 }
 
@@ -2196,12 +2454,7 @@ symbol_section_p (symbolS *s ATTRIBUTE_UNUSED)
 {
   if (LOCAL_SYMBOL_CHECK (s))
     return 0;
-#ifdef BFD_ASSEMBLER
   return (s->bsym->flags & BSF_SECTION_SYM) != 0;
-#else
-  /* FIXME.  */
-  return 0;
-#endif
 }
 
 /* Return whether a symbol is equated to another symbol.  */
@@ -2226,6 +2479,9 @@ symbol_equated_reloc_p (symbolS *s)
      resolve_symbol_value to flag expression syms that have been
      equated.  */
   return (s->sy_value.X_op == O_symbol
+#if defined (OBJ_COFF) && defined (TE_PE)
+	  && ! S_IS_WEAK (s)
+#endif
 	  && ((s->sy_resolved && s->sy_value.X_op_symbol != NULL)
 	      || ! S_IS_DEFINED (s)
 	      || S_IS_COMMON (s)));
@@ -2241,8 +2497,6 @@ symbol_constant_p (symbolS *s)
   return s->sy_value.X_op == O_constant;
 }
 
-#ifdef BFD_ASSEMBLER
-
 /* Return the BFD symbol for a symbol.  */
 
 asymbol *
@@ -2260,11 +2514,18 @@ symbol_set_bfdsym (symbolS *s, asymbol *bsym)
 {
   if (LOCAL_SYMBOL_CHECK (s))
     s = local_symbol_convert ((struct local_symbol *) s);
-  s->bsym = bsym;
+  /* Usually, it is harmless to reset a symbol to a BFD section
+     symbol. For example, obj_elf_change_section sets the BFD symbol
+     of an old symbol with the newly created section symbol. But when
+     we have multiple sections with the same name, the newly created
+     section may have the same name as an old section. We check if the
+     old symbol has been already marked as a section symbol before
+     resetting it.  */
+  if ((s->bsym->flags & BSF_SECTION_SYM) == 0)
+    s->bsym = bsym;
+  /* else XXX - What do we do now ?  */
 }
 
-#endif /* BFD_ASSEMBLER */
-
 #ifdef OBJ_SYMFIELD_TYPE
 
 /* Get a pointer to the object format information for a symbol.  */
@@ -2319,19 +2580,12 @@ symbol_begin (void)
   symbol_lastP = NULL;
   symbol_rootP = NULL;		/* In case we have 0 symbols (!!)  */
   sy_hash = hash_new ();
-#ifdef BFD_ASSEMBLER
   local_hash = hash_new ();
-#endif
 
   memset ((char *) (&abs_symbol), '\0', sizeof (abs_symbol));
-#ifdef BFD_ASSEMBLER
 #if defined (EMIT_SECTION_SYMBOLS) || !defined (RELOC_REQUIRES_SYMBOL)
   abs_symbol.bsym = bfd_abs_section.symbol;
 #endif
-#else
-  /* Can't initialise a union. Sigh.  */
-  S_SET_SEGMENT (&abs_symbol, absolute_section);
-#endif
   abs_symbol.sy_value.X_op = O_constant;
   abs_symbol.sy_frag = &zero_address_frag;
 
@@ -2343,17 +2597,7 @@ int indent_level;
 
 /* Maximum indent level.
    Available for modification inside a gdb session.  */
-int max_indent_level = 8;
-
-#if 0
-
-static void
-indent (void)
-{
-  printf ("%*s", indent_level * 4, "");
-}
-
-#endif
+static int max_indent_level = 8;
 
 void
 print_symbol_value_1 (FILE *file, symbolS *sym)
@@ -2365,7 +2609,6 @@ print_symbol_value_1 (FILE *file, symbolS *sym)
 
   if (LOCAL_SYMBOL_CHECK (sym))
     {
-#ifdef BFD_ASSEMBLER
       struct local_symbol *locsym = (struct local_symbol *) sym;
       if (local_symbol_get_frag (locsym) != &zero_address_frag
 	  && local_symbol_get_frag (locsym) != NULL)
@@ -2373,7 +2616,6 @@ print_symbol_value_1 (FILE *file, symbolS *sym)
       if (local_symbol_resolved_p (locsym))
 	fprintf (file, " resolved");
       fprintf (file, " local");
-#endif
     }
   else
     {
@@ -2391,13 +2633,19 @@ print_symbol_value_1 (FILE *file, symbolS *sym)
 	fprintf (file, " used");
       if (S_IS_LOCAL (sym))
 	fprintf (file, " local");
-      if (S_IS_EXTERN (sym))
+      if (S_IS_EXTERNAL (sym))
 	fprintf (file, " extern");
+      if (S_IS_WEAK (sym))
+	fprintf (file, " weak");
       if (S_IS_DEBUG (sym))
 	fprintf (file, " debug");
       if (S_IS_DEFINED (sym))
 	fprintf (file, " defined");
     }
+  if (S_IS_WEAKREFR (sym))
+    fprintf (file, " weakrefr");
+  if (S_IS_WEAKREFD (sym))
+    fprintf (file, " weakrefd");
   fprintf (file, " %s", segment_name (S_GET_SEGMENT (sym)));
   if (symbol_resolved_p (sym))
     {
@@ -2412,12 +2660,10 @@ print_symbol_value_1 (FILE *file, symbolS *sym)
     {
       indent_level++;
       fprintf (file, "\n%*s<", indent_level * 4, "");
-#ifdef BFD_ASSEMBLER
       if (LOCAL_SYMBOL_CHECK (sym))
 	fprintf (file, "constant %lx",
 		 (long) ((struct local_symbol *) sym)->lsy_value);
       else
-#endif
 	print_expr_1 (file, &sym->sy_value);
       fprintf (file, ">");
       indent_level--;
@@ -2568,9 +2814,7 @@ void
 symbol_print_statistics (FILE *file)
 {
   hash_print_statistics (file, "symbol table", sy_hash);
-#ifdef BFD_ASSEMBLER
   hash_print_statistics (file, "mini local symbol table", local_hash);
   fprintf (file, "%lu mini local symbols created, %lu converted\n",
 	   local_symbol_count, local_symbol_conversion_count);
-#endif
 }
diff --git a/gas/symbols.h b/gas/symbols.h
index 15dc2639bf8d..7a4b8f7a6da3 100644
--- a/gas/symbols.h
+++ b/gas/symbols.h
@@ -1,6 +1,6 @@
 /* symbols.h -
    Copyright 1987, 1990, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
-   2002, 2003 Free Software Foundation, Inc.
+   2002, 2003, 2004, 2005 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,20 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
-
-#ifdef BFD_ASSEMBLER
-/* The BFD code wants to walk the list in both directions.  */
-#undef  SYMBOLS_NEED_BACKPOINTERS
-#define SYMBOLS_NEED_BACKPOINTERS
-#endif
-
-#ifndef BFD_ASSEMBLER
-/* The non-BFD code expects to be able to manipulate the symbol fields
-   directly.  */
-#include "struc-symbol.h"
-#endif
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 extern struct obstack notes;	/* eg FixS live here.  */
 
@@ -49,16 +37,19 @@ extern int symbols_case_sensitive;
 
 char *decode_local_label_name (char *s);
 symbolS *symbol_find (const char *name);
+symbolS *symbol_find_noref (const char *name, int noref);
 symbolS *symbol_find_exact (const char *name);
-symbolS *symbol_find_base (const char *name, int strip_underscore);
+symbolS *symbol_find_exact_noref (const char *name, int noref);
 symbolS *symbol_find_or_make (const char *name);
 symbolS *symbol_make (const char *name);
 symbolS *symbol_new (const char *name, segT segment, valueT value,
 		     fragS * frag);
 symbolS *symbol_create (const char *name, segT segment, valueT value,
 			fragS * frag);
-struct local_symbol *local_symbol_make (const char *name, segT section,
-					valueT value, fragS * frag);
+symbolS *symbol_clone (symbolS *, int);
+#undef symbol_clone_if_forward_ref
+symbolS *symbol_clone_if_forward_ref (symbolS *, int);
+#define symbol_clone_if_forward_ref(s) symbol_clone_if_forward_ref (s, 0)
 symbolS *symbol_temp_new (segT, valueT, fragS *);
 symbolS *symbol_temp_new_now (void);
 symbolS *symbol_temp_make (void);
@@ -70,6 +61,7 @@ void symbol_print_statistics (FILE *);
 void symbol_table_insert (symbolS * symbolP);
 valueT resolve_symbol_value (symbolS *);
 void resolve_local_symbol_values (void);
+int snapshot_symbol (symbolS **, valueT *, segT *, fragS **);
 
 void print_symbol_value (symbolS *);
 void print_expr (expressionS *);
@@ -90,26 +82,34 @@ extern void copy_symbol_attributes (symbolS *, symbolS *);
 extern valueT S_GET_VALUE (symbolS *);
 extern void S_SET_VALUE (symbolS *, valueT);
 
-#ifdef BFD_ASSEMBLER
 extern int S_IS_FUNCTION (symbolS *);
 extern int S_IS_EXTERNAL (symbolS *);
 extern int S_IS_WEAK (symbolS *);
+extern int S_IS_WEAKREFR (symbolS *);
+extern int S_IS_WEAKREFD (symbolS *);
 extern int S_IS_COMMON (symbolS *);
 extern int S_IS_DEFINED (symbolS *);
 extern int S_FORCE_RELOC (symbolS *, int);
 extern int S_IS_DEBUG (symbolS *);
 extern int S_IS_LOCAL (symbolS *);
-extern int S_IS_EXTERN (symbolS *);
 extern int S_IS_STABD (symbolS *);
+extern int S_IS_VOLATILE (const symbolS *);
+extern int S_IS_FORWARD_REF (const symbolS *);
 extern const char *S_GET_NAME (symbolS *);
 extern segT S_GET_SEGMENT (symbolS *);
 extern void S_SET_SEGMENT (symbolS *, segT);
 extern void S_SET_EXTERNAL (symbolS *);
-extern void S_SET_NAME (symbolS *, char *);
+extern void S_SET_NAME (symbolS *, const char *);
 extern void S_CLEAR_EXTERNAL (symbolS *);
 extern void S_SET_WEAK (symbolS *);
+extern void S_SET_WEAKREFR (symbolS *);
+extern void S_CLEAR_WEAKREFR (symbolS *);
+extern void S_SET_WEAKREFD (symbolS *);
+extern void S_CLEAR_WEAKREFD (symbolS *);
 extern void S_SET_THREAD_LOCAL (symbolS *);
-#endif
+extern void S_SET_VOLATILE (symbolS *);
+extern void S_CLEAR_VOLATILE (symbolS *);
+extern void S_SET_FORWARD_REF (symbolS *);
 
 #ifndef WORKING_DOT_WORD
 struct broken_word
@@ -154,8 +154,6 @@ extern const short seg_N_TYPE[];/* subseg.c */
 
 void symbol_clear_list_pointers (symbolS * symbolP);
 
-#ifdef SYMBOLS_NEED_BACKPOINTERS
-
 void symbol_insert (symbolS * addme, symbolS * target,
 		    symbolS ** rootP, symbolS ** lastP);
 void symbol_remove (symbolS * symbolP, symbolS ** rootP,
@@ -163,10 +161,7 @@ void symbol_remove (symbolS * symbolP, symbolS ** rootP,
 
 extern symbolS *symbol_previous (symbolS *);
 
-#endif /* SYMBOLS_NEED_BACKPOINTERS */
-
 void verify_symbol_chain (symbolS * rootP, symbolS * lastP);
-void verify_symbol_chain_2 (symbolS * symP);
 
 void symbol_append (symbolS * addme, symbolS * target,
 		    symbolS ** rootP, symbolS ** lastP);
@@ -175,6 +170,7 @@ extern symbolS *symbol_next (symbolS *);
 
 extern expressionS *symbol_get_value_expression (symbolS *);
 extern void symbol_set_value_expression (symbolS *, const expressionS *);
+extern offsetT *symbol_X_add_number (symbolS *);
 extern void symbol_set_value_now (symbolS *);
 extern void symbol_set_frag (symbolS *, fragS *);
 extern fragS *symbol_get_frag (symbolS *);
@@ -196,11 +192,8 @@ extern int symbol_section_p (symbolS *);
 extern int symbol_equated_p (symbolS *);
 extern int symbol_equated_reloc_p (symbolS *);
 extern int symbol_constant_p (symbolS *);
-
-#ifdef BFD_ASSEMBLER
 extern asymbol *symbol_get_bfdsym (symbolS *);
 extern void symbol_set_bfdsym (symbolS *, asymbol *);
-#endif
 
 #ifdef OBJ_SYMFIELD_TYPE
 OBJ_SYMFIELD_TYPE *symbol_get_obj (symbolS *);
diff --git a/gas/tc.h b/gas/tc.h
index f4a2826ae07f..ec2f73159b53 100644
--- a/gas/tc.h
+++ b/gas/tc.h
@@ -1,6 +1,7 @@
 /* tc.h - target cpu dependent
 
-   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 2000, 2001, 2003
+   Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 2000, 2001, 2003,
+   2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,96 +18,59 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to
-   the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* In theory (mine, at least!) the machine dependent part of the assembler
    should only have to include one file.  This one.  -- JF */
 
 extern const pseudo_typeS md_pseudo_table[];
 
-/* JF moved this here from as.h under the theory that nobody except MACHINE.c
-   and write.c care about it anyway.  */
-
-struct relax_type
-{
-  /* Forward reach. Signed number. > 0.  */
-  long rlx_forward;
-  /* Backward reach. Signed number. < 0.  */
-  long rlx_backward;
-
-  /* Bytes length of this address.  */
-  unsigned char rlx_length;
-
-  /* Next longer relax-state.  0 means there is no 'next' relax-state.  */
-  relax_substateT rlx_more;
-};
-
-typedef struct relax_type relax_typeS;
-
-extern const int md_reloc_size;	/* Size of a relocation record */
-
-char *md_atof (int what_statement_type, char *literalP, int *sizeP);
-#ifndef md_estimate_size_before_relax
-int md_estimate_size_before_relax (fragS * fragP, segT segment);
+char * md_atof (int, char *, int *);
+int    md_parse_option (int, char *);
+void   md_show_usage (FILE *);
+void   md_assemble (char *);
+void   md_begin (void);
+void   md_number_to_chars (char *, valueT, int);
+void   md_apply_fix (fixS *, valueT *, segT);
+
+#ifndef WORKING_DOT_WORD
+extern int md_short_jump_size;
+extern int md_long_jump_size;
 #endif
-int md_parse_option (int c, char *arg);
-void md_show_usage (FILE *);
-#ifndef md_pcrel_from
-long md_pcrel_from (fixS * fixP);
+
+#ifdef USE_UNIQUE
+/* The name of an external symbol which is
+   used to make weak PE symbol names unique.  */
+extern const char * an_external_name;
 #endif
-short tc_coff_fix2rtype (fixS * fixP);
-void md_assemble (char *str);
-void md_begin (void);
+
 #ifndef md_create_long_jump
-void md_create_long_jump (char *ptr, addressT from_addr,
-			  addressT to_addr, fragS * frag,
-			  symbolS * to_symbol);
+void    md_create_long_jump (char *, addressT, addressT, fragS *, symbolS *);
 #endif
 #ifndef md_create_short_jump
-void md_create_short_jump (char *ptr, addressT from_addr,
-			   addressT to_addr, fragS * frag,
-			   symbolS * to_symbol);
+void    md_create_short_jump (char *, addressT, addressT, fragS *, symbolS *);
+#endif
+#ifndef md_pcrel_from
+long    md_pcrel_from (fixS *);
 #endif
-void md_number_to_chars (char *buf, valueT val, int n);
-
 #ifndef md_operand
-void md_operand (expressionS * expressionP);
+void    md_operand (expressionS *);
+#endif
+#ifndef md_estimate_size_before_relax
+int     md_estimate_size_before_relax (fragS * fragP, segT);
+#endif
+#ifndef md_section_align
+valueT  md_section_align (segT, valueT);
+#endif
+#ifndef  md_undefined_symbol
+symbolS *md_undefined_symbol (char *);
 #endif
 
-void md_apply_fix3 (fixS *, valueT *, segT);
-
-#ifdef BFD_ASSEMBLER
 #ifndef md_convert_frag
-void md_convert_frag (bfd * headers, segT sec, fragS * fragP);
-#endif
-#ifndef tc_headers_hook
-void tc_headers_hook (segT *, fixS *);
+void    md_convert_frag (bfd *, segT, fragS *);
 #endif
 #ifndef RELOC_EXPANSION_POSSIBLE
 extern arelent *tc_gen_reloc (asection *, fixS *);
 #else
 extern arelent **tc_gen_reloc (asection *, fixS *);
 #endif
-#else /* not BFD_ASSEMBLER */
-#ifndef md_convert_frag
-void md_convert_frag (object_headers * headers, segT, fragS * fragP);
-#endif
-
-#ifndef tc_crawl_symbol_chain
-void tc_crawl_symbol_chain (object_headers * headers);
-#endif /* tc_crawl_symbol_chain */
-
-#ifndef tc_headers_hook
-void tc_headers_hook (object_headers * headers);
-#endif /* tc_headers_hook */
-#endif /* BFD_ASSEMBLER */
-
-#ifndef md_section_align
-valueT md_section_align (segT seg, valueT size);
-#endif
-
-#ifndef md_undefined_symbol
-symbolS *md_undefined_symbol (char *name);
-#endif
-
-/* end of tc.h */
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d0a41887f46e..6637ab929508 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,268 +1,348 @@
-2005-03-10  Aldy Hernandez  <aldyh@redhat.com>
+2006-06-14  Thiemo Seufer  <ths@mips.com>
 
-        * gas/ppc/e500.d: Fix encoding of efscfd.
+	* gas/mips/mips16e-jrc.d, gas/mips/mips16e-save.d,
+	gas/mips/mips32-dsp.d, gas/mips/mips32-mt.d: Explicitly specify
+	o32 ABI.
 
-2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
+2006-05-26  Richard Sandiford  <richard@codesourcery.com>
 
-	* gas/ppc/e500.s: Add double-precision instructions.
-	* gas/ppc/e500.d: Same.
+	* gas/m68k/mcf-fpu.s: Add fmovemd and fmovem instructions.
+	* gas/m68k/mcf-fpu.d: Adjust accordingly.
 
-2004-09-07  Eric Botcazou  <ebotcazou@libertysurf.fr>
+2006-05-22  Nick Clifton  <nickc@redhat.com>
 
-	Merge from mainline:
-	2004-04-19  Jakub Jelinek  <jakub@redhat.com>
-	* gas/cfi/cfi-sparc64-1.d: Update.
+	* gas/mips/mips32-dsp.l: Fix expected unsigned decoding of -1 in
+	warning messages.
+	* gas/mips/mips32-mt.l: Likewise.
 
-2004-08-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+2006-05-19  Thiemo Seufer  <ths@mips.com>
 
-	* gas/mips/branch-swap.s: New testcase.
-	* gas/mips/branch-swap.d: New testcase.
-	* gas/mips/mips.exp: Run the testcase.
+	* gas/mips/vxworks1-el.d, gas/mips/vxworks1-xgot-el.d: Add little
+	endian testcases.
+	* gas/mips/vxworks1.d, gas/mips/vxworks1-xgot.d: Build as big endian.
+	* gas/mips/mips.exp: Run new testcases.
 
-2004-07-30  Michal Ludvig  <mludvig@suse.cz>
+2006-05-11  Thiemo Seufer  <ths@mips.com>
 
-	* gas/i386/padlock.s, gas/i386/padlock.d: New tests for
-	VIA PadLock instructions.
+	* gas/mips/jal-range.l: Don't check the range of j or jal
+	addresses.
 
-2004-05-11  Daniel Jacobowitz  <dan@debian.org>
+2006-05-04  Thiemo Seufer  <ths@mips.com>
 
-	Revert patch for 2.15:
-	2004-02-09  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
-	* gas/sh/sh64/err-dsp.s: Fix expected error message.
+	* gas/mips/mips32-mt.d: Fix mftr argument order.
 
-2004-05-06  Daniel Jacobowitz  <dan@debian.org>
+2006-05-02  Joseph Myers  <joseph@codesourcery.com>
 
-	Merge from mainline:
-	2004-04-23  Nick Clifton  <nickc@redhat.com>
-	* gas/symver/symver1.d: Cope with extra symbols inserted by
-	arm-elf toolchains.
-	* gas/symver/symver0.d: Likewise
-	* gas/elf/symver.d: Likewise.
+	* gas/arm/iwmmxt.s: Increase offsets for wstrb and wstrh.
+	* gas/arm/iwmmxt.d: Update expected results.
+	* gas/arm/iwmmxt-bad2.s: Test wstrb, wstrh, wldrb and wldrh.
+	* gas/arm/iwmmxt-bad2.l: Update expected error messages.
 
-2004-05-05  Alexandre Oliva  <aoliva@redhat.com>
+2006-04-16  Nick Clifton  <nickc@redhat.com>
 
-	* gas/frv/reloc1.d: Match elf32-frvfdpic as well.
+	* gas/arm/arch7.d: Skip test for non-ELF targets.
+	* gas/arm/blx-local.d: Likewise.
+	* gas/arm/svc.d: Likewise.
+	* gas/arm/thumb2_bcond.d: Likewise.
+	* gas/arm/thumb2_it_bad.d: Likewise.
 
-2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+2006-04-07  Paul Brook  <paul@codesourcery.com>
 
-	* gas/mips/vr4122.[sd]: Change option to -mfix-vr4120.
+	* gas/arm/blx-local.d: New test.
+	* gas/arm/blx-local.d: New test.
 
-2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+2006-04-07  Paul Brook  <paul@codesourcery.com>
 
-	* gas/elf/section2.e-mips: Allow named section symbols.
-	* gas/mips/{,el}empic.d, gas/mips/mips{,el}16-[ef].d: Likewise.
+	* gas/arm/thumb2_pool.d: New test.
+	* gas/arm/thumb2_pool.s: New test.
 
-2004-04-09  Daniel Jacobowitz  <drow@mvista.com>
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
 
-	Merge from mainline:
-	2004-04-01  Asgari Jinia  <asgarij@kpitcummins.com>
-	* gas/sh/renesas-1.s, gas/sh/renesas-1.d: New test for -renesas
-	option.
-	* gas/sh/basic.exp: Run the new test.
+	* gas/sparc/vxworks-pic.s, gas/sparc/vxworks-pic.d: New test.
+	* gas/sparc/sparc.exp: Run it.  Remove sparc*-*-vxworks* XFAILs.
 
-	2004-04-01  Dave Korn  <dk@artimi.com>
-	* gas/dlx/alltests.exp: Execute new lohi test.
-	* gas/dlx/lohi.s: New test for spurious lo16/hi16
-	reloc overflow checking.
-	* gas/dlx/lohi.d: New file: expected output.
-	* gas/dlx/lhi.d: Updated to properly expect lo16
-	relocations where asked for.
-	* gas/dlx/itype.d: Likewise.
-	* gas/dlx/lhi.d: Corrected cut+paste error in test name.
+2006-03-23  H.J. Lu  <hongjiu.lu@intel.com>
 
-	2004-03-23  Andreas Schwab  <schwab@suse.de>
-	* gas/cfi/cfi-m68k.d: Adjust offsets.
+	* gas/i386/rep.s: Pad with .p2align.
+	* gas/i386/rep.d: Adjust.
 
-	2004-03-08  Andreas Jaeger  <aj@suse.de>
-	* gas/cfi/cfi-s390x-1.d: Adjust offsets.
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
 
-	2004-03-07  Richard Henderson  <rth@redhat.com>
-	* gas/cfi/cfi-common-2.d, gas/cfi/cfi-i386.d: Adjust offsets.
+	* gas/mips/vxworks1.s, gas/mips/vxworks1.d,
+	* gas/mips/vxworks1-xgot.d: New tests.
+	* gas/mips/mips.exp: Run them.  Do not run other tests on VxWorks.
+	
+2006-03-21  Paul Brook  <paul@codesourcery.com>
 
-	2004-03-07  Andreas Jaeger  <aj@suse.de>
-	* gas/cfi/cfi-x86_64.d: Adjust offsets.
+	* gas/arm/thumb32.d: Correct expected output.
 
-	2004-03-07  Richard Henderson  <rth@redhat.com>
-	* gas/alpha/elf-reloc-8.d, gas/cfi/cfi-alpha-1.d,
-	gas/cfi/cfi-alpha-2.d, gas/cfi/cfi-alpha-3.d, gas/cfi/cfi-common-1.d,
-	gas/cfi/cfi-common-2.d, gas/cfi/cfi-common-3.d: Adjust offsets.
+2006-03-20  Paul Brook  <paul@codesourcery.com>
 
-	2004-03-03  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
-	* gas/sh/sh64/err-dsp.s: Fix expected error message.
+	* gas/arm/thumb2_bcond.d: New test.
+	* gas/arm/thumb2_bcond.s: New test.
+	* gas/arm/thumb2_it_bad.d: New test.
+	* gas/arm/thumb2_it_bad.l: New test.
+	* gas/arm/thumb2_it_bad.s: New test.
 
-2004-03-22  Hans-Peter Nilsson  <hp@axis.com>
+2006-03-17  Paul Brook  <paul@codesourcery.com>
 
-	* gas/cris/regreg.d: Assemble with --no-mul-bug-abort.
-	* gas/cris/mulbug-err-1.s, gas/cris/rd-mulbug-1.d: New tests.
+	* gas/arm/thumb32.d: Add ldm and stm tests.
+	* gas/arm/thumb32.s: Ditto.
 
-2004-03-17  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+2006-03-16  Bernd Schmidt  <bernd.schmidt@analog.com>
 
-	* gas/cfi/cfi-sh-1.d: New file.
-	* gas/cfi/cfi-sh-1.s: Likewise.	
-	* gas/cfi/cfi.exp: Add SH case.
+	* gas/bfin/shift2.s: Add new tests.
+	* gas/bfin/shift.d: Match changed disassembler behaviour.
+	* gas/bfin/parallel2.d: Likewise.
+	* gas/bfin/shift2.d: Likewise; also match new tests.
 
-2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+2006-03-16  Paul Brook  <paul@codesourcery.com>
 
-	* gas/ppc/altivec.d: Update.
-	* gas/ppc/altivec_xcoff.d: Update.
-	* gas/ppc/altivec_xcoff64.d: Update.
-	* gas/ppc/astest.d: Update.
-	* gas/ppc/astest2.d: Update.
-	* gas/ppc/astest2_64.d: Update.
-	* gas/ppc/astest64.d: Update.
-	* gas/ppc/booke.d: Update.
-	* gas/ppc/booke_xcoff.d: Update.
-	* gas/ppc/booke_xcoff64.d: Update.
-	* gas/ppc/e500.d: Update.
-	* gas/ppc/power4.d: Update.
-	* gas/ppc/test1elf32.d: Update.
-	* gas/ppc/test1elf64.d: Update.
-	* gas/ppc/test1xcoff32.d: Update.
+	* gas/arm/svc.d: New test.
+	* gas/arm/svc.s: New test.
+	* gas/arm/inst.d: Accept svc mnemonic.
+	* gas/arm/thumb.d: Ditto.
+	* gas/arm/wince_inst.d: Ditto.
 
-2004-03-15  Alan Modra  <amodra@bigpond.net.au>
+2006-03-09  Paul Brook  <paul@codesourcery.com>
 
-	* gas/i386/padlock.s: Pad with .p2align.
-	* gas/i386/padlock.d: Adjust.
+	* gas/arm/nomapping.d: New test.
+	* gas/arm/nomapping.s: New test.
 
-2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+2006-03-07  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* gas/i386/padlock.s, gas/i386/padlock.d: New tests for
-	VIA PadLock instructions.
-	* gas/i386/i386.exp: Run padlock tests.
+	PR binutils/2428
+	* gas/i386/i386.exp: Add rep, rep-suffix, x86-64-rep and
+	x86-64-rep-suffix.
 
-2004-02-17  Petko Manolov  <petkan@nucleusys.com>
+	* gas/i386/naked.d: Replace repz with rep.
+	* gas/i386/x86_64.d: Likewise.
 
-	* gas/arm/maverick.c: DSPSC to/from opcode fixes.
-	* gas/arm/maverick.d: Likewise.
-	* gas/arm/maverick.s: Likewise.
+	* gas/i386/rep-suffix.d: New file. 
+	* gas/i386/rep-suffix.s: Likewise.
+	* gas/i386/rep.d: Likewise.
+	* gas/i386/rep.s: Likewise.
+	* gas/i386/x86-64-rep-suffix.d: Likewise.
+	* gas/i386/x86-64-rep-suffix.s: Likewise.
+	* gas/i386/x86-64-rep.d: Likewise.
+	* gas/i386/x86-64-rep.s: Likewise.
 
-2004-02-09  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
 
-	* gas/sh/basic.exp: Don't do sh4a tests for sh5.
+	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
+	* gas/arm/pic.d: Skip for *-*-vxworks*...
+	* gas/arm/pic_vxworks.d: ...use this version instead.
+	* gas/arm/unwind_vxworks.d: Fix expected output.
 
-2004-02-06  Nathan Sidwell  <nathan@codesourcery.com>
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
 
-	* gas/macros/test2.s: Lowercase it.
+	* gas/m68k/arch-cpu-1.s: Tweak.
+	* gas/m68k/arch-cpu-1.d: Tweak.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/altmacro.s: Adjust.
+	* gas/all/altmac2.s: Adjust.
+
+2006-02-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/paren[sd]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add merom and x86-64-merom.
+
+	* gas/i386/merom.d: New file.
+	* gas/i386/merom.s: Likewise.
+	* gas/i386/x86-64-merom.d: Likewise.
+	* gas/i386/x86-64-merom.s: Likewise.
+
+2006-02-24  David S. Miller  <davem@sunset.davemloft.net>
+
+	* gas/sparc/rdhpr.s: New test.
+	* gas/sparc/rdhpr.d: New test.
+	* gas/sparc/wrhpr.s: New test.
+	* gas/sparc/wrhpr.d: New test.
+	* gas/sparc/window.s: New test.
+	* gas/sparc/window.d: New test.
+	* gas/sparc/rdpr.s: Add case for reading %gl register.
+	* gas/sparc/rdpr.d: Likewise.
+	* gas/sparc/wrpr.s: Add case for writing %gl register.
+	* gas/sparc/wrpr.d: Likewise.
+	* gas/sparc/sparc.exp: Update for new tests.
+	
+2006-02-24  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Fix expected msr and mrs output.
+	* gas/arm/arch7.d: New test.
+	* gas/arm/arch7.s: New test.
+	* gas/arm/arch7m-bad.l: New test.
+	* gas/arm/arch7m-bad.d: New test.
+	* gas/arm/arch7m-bad.s: New test.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/opc-i.s: Add tests for tf.
+	* gas/ia64/pseudo.s: Likewise.
+	* gas/ia64/opc-i.d: Updated.
+	* gas/ia64/pseudo.d: Likewise.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/dv-raw-err.s: Add check for vmsw.0.
+	* gas/ia64/dv-raw-err.l: Updated.
+
+	* gas/ia64/opc-b.s: Add vmsw.0 and vmsw.1.
+	* gas/ia64/opc-b.d: Updated.
 
-2004-02-02  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+2005-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Fix expected pld opcode.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
 
-	* gas/mips/div.d: Update to accomodate changes in macro
-	expansions.
-	gas/mips/elf-rel-got-n32.d: Likewise.
-	gas/mips/elf-rel-got-n64.d: Likewise.
-	gas/mips/elf-rel-xgot-n32.d: Likewise.
-	gas/mips/elf-rel-xgot-n64.d: Likewise.
-	gas/mips/la-svr4pic.d: Likewise.
-	gas/mips/la-xgot.d: Likewise.
-	gas/mips/lca-svr4pic.d: Likewise.
-	gas/mips/lca-xgot.d: Likewise.
+	* gas/xc16x: New directory.
+	* gas/xc16x/xc16x.exp: New file
+	* gas/xc16x/add.s: New file
+	* gas/xc16x/add_test.s: New file
+	* gas/xc16x/addb.s: New file
+	* gas/xc16x/addc.s: New file
+	* gas/xc16x/addcb.s: New file   
+	* gas/xc16x/and.s: New file
+	* gas/xc16x/andb.s: New file
+	* gas/xc16x/bfldl.s: New file
+	* gas/xc16x/bit.s: New file
+	* gas/xc16x/calla.s: New file
+	* gas/xc16x/calli.s: New file
+	* gas/xc16x/cmp.s: New file  
+	* gas/xc16x/cmp_test.s: New file
+	* gas/xc16x/cmpb.s: New file
+	* gas/xc16x/cmpi.s: New file
+	* gas/xc16x/cpl.s: New file
+	* gas/xc16x/div.s: New file
+	* gas/xc16x/jmpa.s: New file
+	* gas/xc16x/jmpi.s: New file
+	* gas/xc16x/jmpr.s: New file
+	* gas/xc16x/mov.s: New file
+	* gas/xc16x/mov_test.s: New file 
+	* gas/xc16x/movb.s: New file
+	* gas/xc16x/movbs.s: New file
+	* gas/xc16x/movbz.s: New file  
+	* gas/xc16x/mul.s: New file
+	* gas/xc16x/neg.s: New file
+	* gas/xc16x/nop.s: New file
+	* gas/xc16x/or.s: New file
+	* gas/xc16x/orb.s: New file
+	* gas/xc16x/prior.s: New file
+	* gas/xc16x/pushpop.s: New file
+	* gas/xc16x/ret.s: New file
+	* gas/xc16x/scxt.s: New file
+	* gas/xc16x/shlrol.s: New file
+	* gas/xc16x/sub.s: New file
+	* gas/xc16x/sub_test.s: New file 
+	* gas/xc16x/subb.s: New file
+	* gas/xc16x/subcb.s: New file
+	* gas/xc16x/syscontrol1.s: New file
+	* gas/xc16x/syscontrol2.s: New file
+	* gas/xc16x/trap.s: New file
+	* gas/xc16x/xor.s: New file
+	* gas/xc16x/xorb.s: New file
+
+2006-02-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-crx-suffix.d: Undo the last change.
+
+2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add "x86-64-drx" and "x86-64-drx-suffix".
+
+	* gas/i386/x86-64-crx-suffix.d: Minor update.
+
+	* gas/i386/x86-64-drx-suffix.d: New file.
+	* gas/i386/x86-64-drx.d: Likewise.
+	* gas/i386/x86-64-drx.s: Likewise.
+
+2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add "x86-64-crx" and "x86-64-crx-suffix".
+
+	* gas/i386/x86-64-crx-suffix.d: New file.
+	* gas/i386/x86-64-crx.d: Likewise.
+	* gas/i386/x86-64-crx.s: Likewise.
+
+2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* testsuite/gas/m68k/all.exp: Add arch-cpu-1 test.
+	* testsuite/gas/m68k/arch-cpu-1.[sd]: New.
+
+2005-02-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_invert.d: New test.
+	* gas/arm/thumb2_invert.s: New test.
+
+2006-01-31  Paul Brook  <paul@codesourcery.com>
+
+	* gas/testsuite/gas/arm/iwmmxt-bad.s: Add check for bad register name.
+	* gas/testsuite/gas/arm/iwmmxt-bad.l: Ditto.
+
+2006-01-18  Arnold Metselaar  <arnoldm@sourceware.org>
+
+	* gas/z80/z80.exp: Add offset.
+	* gas/z80/offset.d: New file.
+	* gas/z80/offset.s: New file.
+
+2006-01-16  Paul Brook  <paul@codesourcery.com>
+
+	* gas/m68k/all.exp: Add mcf-fpu.
+	* gas/m68k/mcf-fpu.d: New file.
+	* gas/m68k/mcf-fpu.s: New file.
+
+2006-01-11  Nick Clifton  <nickc@redhat.com>
+
+	* gas/tic54x/address.d: Work with 64bit hosts.
+	* gas/tic54x/addrfar.d: Likewise.
+	* gas/tic54x/align.d: Likewise.
+	* gas/tic54x/all-opcodes.d: Likewise.
+	* gas/tic54x/asg.d: Likewise.
+	* gas/tic54x/cons.d: Likewise.
+	* gas/tic54x/consfar.d: Likewise.
+	* gas/tic54x/extaddr.d: Likewise.
+	* gas/tic54x/field.d: Likewise.
+	* gas/tic54x/labels.d: Likewise.
+	* gas/tic54x/loop.d: Likewise.
+	* gas/tic54x/lp.d: Likewise.
+	* gas/tic54x/macro.d: Likewise.
+	* gas/tic54x/math.d: Likewise.
+	* gas/tic54x/opcodes.d: Likewise.
+	* gas/tic54x/sections.d: Likewise.
+	* gas/tic54x/set.d: Likewise.
+	* gas/tic54x/struct.d: Likewise.
+	* gas/tic54x/subsym.d: Likewise.
+
+2006-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/2117
+	* gas/ia64/ia64.exp: Add ltoff22x-2, ltoff22x-3, ltoff22x-4 and
+	ltoff22x-5.
+
+	* gas/ia64/ltoff22x-2.d: New file.
+	* gas/ia64/ltoff22x-2.s: Likewise.
+	* gas/ia64/ltoff22x-3.d: Likewise.
+	* gas/ia64/ltoff22x-3.s: Likewise.
+	* gas/ia64/ltoff22x-4.d: Likewise.
+	* gas/ia64/ltoff22x-4.s: Likewise.
+	* gas/ia64/ltoff22x-5.d: Likewise.
+	* gas/ia64/ltoff22x-5.s: Likewise.
 
-2004-02-01  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
 
-	* gas/sh/sh4a-fp.d: Fix opcode name fssra to fsrra.
-	* gas/sh/sh4a-fp.s: Likewise.
-	* gas/sh/err-sh4a-fp.s: Likewise.
+	PR gas/2101
+	* gas/mmix/hex2.s, gas/mmix/hex2.d: New test.
 
-2004-01-24  Chris Demetriou  <cgd@broadcom.com>
-
-	* gas/mips/relax-swap1.s: Add extra space at end, so the
-	disassembly will consistently have "..." at its end.
-	* gas/mips/relax-swap2.s: Likewise.
-	* gas/mips/relax-swap1-mips2.d: Expect "..." at end of disassembly.
-
-2004-01-23  Daniel Jacobowitz  <drow@mvista.com>
-
-	* gas/arm/arm.exp: Add "undefined" test.
-	* gas/arm/undefined.s, gas/arm/undefined.l: New files.
-
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
-
-	* gas/mips/macro-warn-[1234].[sdl]: New tests.
-	* gas/mips/macro-warn-[12]-n32.[dl]: New tests.
-	* gas/mips/mips.exp: Run them.
-
-2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
-
-	* gas/mips/elf-rel19.[sd]: New test.
-	* gas/mips/mips.exp: Run it.
-
-2004-01-11 Tom Rix   <tcrix@worldnet.att.net>
-
-	* gas/m68hc11/movb.s: Add m68hc12 movb and movw dump test.
-	* gas/m68hc11/movb.d: Likewise.
-	* gas/m68hc11/m68hc11.exp: Likewise.  Add more movb failure tests.
-
-2004-01-19  Alan Modra  <amodra@bigpond.net.au>
-
-	* gas/i386/katmai.d: Adjust for changed sib printing.
-	* gas/i386/prescott.d: Likewise.
-	* gas/i386/sse2.d: Likewise.
-	* gas/i386/ssemmx2.d: Likewise.
-
-2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
-
-	* gas/mn10300/mov5.s: New.
-	* gas/mn10300/basic.exp (do_mov5): New.
-
-2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
-
-	* gas/mips/relax-swap1-mips1.d: New test for branch relaxation
-	with swapping for MIPS1.
-	* gas/mips/relax-swap1-mips2.d: New test for branch relaxation
-	with swapping for MIPS2.
-	* gas/mips/relax-swap1.l: Stderr output for the new tests.
-	* gas/mips/relax-swap1.s: Source for the new tests.
-	* gas/mips/relax-swap2.d: New test for branch likely relaxation
-	with swapping.
-	* gas/mips/relax-swap2.l: Stderr output for the new test.
-	* gas/mips/relax-swap2.s: Source for the new test.
-	* gas/mips/mips.exp: Run the new tests.
-
-2004-01-13  Ian Lance Taylor  <ian@wasabisystems.com>
-
-	* gas/mips/mips16-64.d: New test.
-	* gas/mips/mips.exp: Run it.
-
-2004-01-12  Richard Sandiford  <rsandifo@redhat.com>
-
-	* gas/mips/elf-rel18.[sd]: New test.
-	* gas/mips/mips.exp: Run it.
-
-2004-01-09  Paul Brook  <paul@codesourcery.com>
-
-	* gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
-	* gas/arm/arm.exp: Add them.
-
-2004-01-08  Ian Lance Taylor  <ian@wasabisystems.com>
-
-	* gas/mips/ldstla-n64.d: Pass -64 to assembler, not -n64.
-	* gas/mips/ldstla-n64-shared.d: Likewise.
-
-2004-01-07  Nick Clifton  <nickc@redhat.com>
-
-	* gas/cris/rd-dw2-1.d: Expect a pointer size from readelf.
-
-2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
-
-	2003-11-05  Alexandre Oliva  <aoliva@redhat.com>
-	* lib/gas-defs.exp (is_elf_format): Match frv-uclinux.
-	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
-	* gas/frv/fdpic.s, gas/frv/fdpic.d: Renamed from ucpic*.
-	2003-09-15  Alexandre Oliva  <aoliva@redhat.com>
-	* gas/frv/ucpic.s, gas/frv/ucpic.d: Use gr15 as PIC register.  Use
-	gprel12 for rodata symbol and gotoff12 for sdata symbol.
-	2003-08-08  Alexandre Oliva  <aoliva@redhat.com>
-	* gas/frv/ucpic.d: Test gotoff and gotofffuncdesc.
-	2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
-	* gas/frv/ucpic.d, gas/frv/ucpic.s: New.
-	* gas/frv/allinsns.exp: Run it.
-
-2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
-
-	* gas/msp430/opcode.s: Add test for an 'add' instruction which
-	looks similar to an 'rla' instruction.
-
-For older changes see ChangeLog-9303
+For older changes see ChangeLog-2005
 
 Local Variables:
 mode: change-log
diff --git a/gas/testsuite/ChangeLog-2004 b/gas/testsuite/ChangeLog-2004
new file mode 100644
index 000000000000..122809b62a09
--- /dev/null
+++ b/gas/testsuite/ChangeLog-2004
@@ -0,0 +1,1156 @@
+2004-12-31  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/elf/elf.exp: Don't list reloc sections.
+	* gas/elf/section5.e: Remove reloc sections.
+
+2004-12-21  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/beq_insn.d: Update reference file according to
+	disassembler printing method.
+	* gas/crx/bit_insn.d: Likewise.
+	* gas/crx/br_insn.d: Likewise.
+	* gas/crx/cmpbr_insn.d: Likewise.
+	* gas/crx/cop_insn.d: Likewise.
+	* gas/crx/load_stor_insn.d: Likewise.
+
+2004-12-21  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/elf/section5.e, gas/elf/section5.l: Replace [:digit:],
+	[:xdigit:] and {N} in regexps with [0-9], [0-9a-fA-F] and N
+	copies, to cater to tcl versions before Tcl 8.2.3.
+
+2004-12-20  Nick Clifton  <nickc@redhat.com>
+
+	* gas/elf/section5.[ls]: Use % instead of @ in .section
+	directives.
+
+2004-12-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/v850/split-lo16.{s,d}: New test.
+	* gas/v850/v850.exp: Run it.
+
+2004-12-15 Jan Beulich  <jbeulich@novell.com>
+
+	* gas/elf/section5.[els]: New.
+
+2004-12-13  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel25.d, gas/mips/elf-rel25a.d: Cope with different
+	.text alignments.
+
+2004-12-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/alpha/elf-usepv-1.d: Update for changed section syms.
+	* gas/arm/mapping.d: Likewise.
+	* gas/mips/tmips16-e.d: Likewise.
+	* gas/mips/tmips16-f.d: Likewise.
+	* gas/mmix/align-1.d: Likewise.
+	* gas/mmix/basep-10.d: Likewise.
+	* gas/mmix/basep-11.d: Likewise.
+	* gas/mmix/basep-7.d: Likewise.
+	* gas/mmix/basep-8.d: Likewise.
+	* gas/mmix/basep-9.d: Likewise.
+	* gas/mmix/builtin1.d: Likewise.
+	* gas/mmix/builtin2.d: Likewise.
+	* gas/mmix/builtin3.d: Likewise.
+	* gas/mmix/bz-c.d: Likewise.
+	* gas/mmix/comment-2.d: Likewise.
+	* gas/mmix/comment-3.d: Likewise.
+	* gas/mmix/cons-2.d: Likewise.
+	* gas/mmix/fb-1.d: Likewise.
+	* gas/mmix/fb-2.d: Likewise.
+	* gas/mmix/geta-c.d: Likewise.
+	* gas/mmix/greg1.d: Likewise.
+	* gas/mmix/greg1a.d: Likewise.
+	* gas/mmix/greg2.d: Likewise.
+	* gas/mmix/greg2a.d: Likewise.
+	* gas/mmix/greg3.d: Likewise.
+	* gas/mmix/greg4.d: Likewise.
+	* gas/mmix/greg5.d: Likewise.
+	* gas/mmix/greg6.d: Likewise.
+	* gas/mmix/greg7.d: Likewise.
+	* gas/mmix/greg8.d: Likewise.
+	* gas/mmix/is-1.d: Likewise.
+	* gas/mmix/jump-c.d: Likewise.
+	* gas/mmix/local-1.d: Likewise.
+	* gas/mmix/locall1.d: Likewise.
+	* gas/mmix/odd-1.d: Likewise.
+	* gas/mmix/op-0-1.d: Likewise.
+	* gas/mmix/op-0-1s.d: Likewise.
+	* gas/mmix/op-0-2.d: Likewise.
+	* gas/mmix/prefix1.d: Likewise.
+	* gas/mmix/prefix2.d: Likewise.
+	* gas/mmix/prefix3.d: Likewise.
+	* gas/mmix/pseudo-1.d: Likewise.
+	* gas/mmix/pushj-c.d: Likewise.
+	* gas/mmix/pushj-cs.d: Likewise.
+	* gas/mmix/sym-1.d: Likewise.
+	* gas/mmix/weak1-s.d: Likewise.
+	* gas/mmix/weak1.d: Likewise.
+	* gas/mmix/zerop-1.d: Likewise.
+	* gas/ppc/power4.d: Likewise.
+	* gas/ppc/test1elf32.d: Likewise.
+	* gas/ppc/test1elf64.d: Likewise.
+	* gas/sh/sh64/datal32-3.d: Likewise.
+	* gas/sh/sh64/datal64-3.d: Likewise.
+	* gas/sh/sh64/localcom-1.d: Likewise.
+
+2004-12-10  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* gas/mips/elf-rel23a.d: New test.
+	* gas/mips/elf-rel23b.d: New test.
+	* gas/mips/elf-rel25.s: New test.
+	* gas/mips/elf-rel25.d: New test.
+	* gas/mips/elf-rel25a.d: New test.
+	* gas/mips/mips.exp: Run new tests.
+
+2004-12-09  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/unwind.d: Expect R_ARM_PREL31 relocations.
+
+2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* gas/mips/branch-swap.d: Pass -32 to as.
+
+2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/br_insn.d: Fix error in expected disassembly.
+
+2004-11-29  Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/rela-1.s: New test.
+	* gas/m32r/rela-1.d: Expected disassembly.
+	* gas/m32r/m32r.exp: Run the new test.
+	* gas/m32r/relax-1.d: Update for fixed pcrel reloc
+	generation.
+
+2004-11-27  Richard Earnshaw  <rearnsha@arm.com>
+
+	* gas/arm/thumbv6.d (setend): Remove stray tab at end
+	of dump pattern.
+
+2004-11-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/group-1.d: Adjust expected secion ordering.
+
+2004-11-25 Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
+
+2004-11-24  Paul Brook  <paul@codesourcery.com>
+
+	* gas/elf/group0a.d: Adjust expected secion ordering.
+	* gas/elf/group1a.d: Ditto.
+	* gas/elf/section4.d: Ditto.
+
+2004-11-24  Nick Clifton  <nickc@redhat.com>
+
+	* gas/iq2000/allinsn.exp: Remove IQ10 tests.
+	* gas/iq2000/q10allinsn.d: Delete.
+	* gas/iq2000/q10allinsn.s: Delete.
+	* gas/iq2000/q10hazard4.s: Delete.
+	* gas/iq2000/q10hazard5.s: Delete.
+	* gas/iq2000/q10load-hazards.exp: Delete.
+	* gas/iq2000/q10nohazard.s: Delete.
+	* gas/iq2000/q10noyield.s: Delete.
+	* gas/iq2000/q10test0.d: Delete.
+	* gas/iq2000/q10test0.s: Delete.
+	* gas/iq2000/q10test1.d: Delete.
+	* gas/iq2000/q10test1.s: Delete.
+	* gas/iq2000/q10test10.d: Delete.
+	* gas/iq2000/q10test10.s: Delete.
+	* gas/iq2000/q10test11.d: Delete.
+	* gas/iq2000/q10test11.s: Delete.
+	* gas/iq2000/q10test12.d: Delete.
+	* gas/iq2000/q10test12.s: Delete.
+	* gas/iq2000/q10test2.d: Delete.
+	* gas/iq2000/q10test2.s: Delete.
+	* gas/iq2000/q10test3.d: Delete.
+	* gas/iq2000/q10test3.s: Delete.
+	* gas/iq2000/q10test4.d: Delete.
+	* gas/iq2000/q10test4.s: Delete.
+	* gas/iq2000/q10test5.d: Delete.
+	* gas/iq2000/q10test5.s: Delete.
+	* gas/iq2000/q10test6.d: Delete.
+	* gas/iq2000/q10test6.s: Delete.
+	* gas/iq2000/q10test7.d: Delete.
+	* gas/iq2000/q10test7.s: Delete.
+	* gas/iq2000/q10test8.d: Delete.
+	* gas/iq2000/q10test8.s: Delete.
+	* gas/iq2000/q10test9.d: Delete.
+	* gas/iq2000/q10test9.s: Delete.
+	* gas/iq2000/q10yield.exp: Delete.
+	* gas/iq2000/test.exp: Delete.
+
+2004-11-24  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* gas/arc/st.s: Add checks for other variants of the sr and st
+	instruction.
+	* gas/arc/st.d: Update the expected disassembly.
+
+2004-11-23  Nick Clifton  <nickc@redhat.com>
+
+	* gas/mn10300/relax.s: Add further tests of the relaxing of branch
+	instructions.
+	* gas/mn10300/relax.d: Add expected relocations.
+
+2004-11-22  Ravi Ramaseshan  <ravi.ramaseshan@codito.com>
+
+	* gas/arc/ld.s: Add check of load of a long immediate.
+	* gas/arc/ld.d: Add expected disassembly.
+
+2004-11-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/all/gas.exp: Run dg-runtest for all err-*.s and warn-*.s.
+	* gas/all/err-1.s, gas/all/warn-1.s: New tests.
+
+2004-11-18  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+
+	* gas/maxq10/call.d: Fix expected results now that bfd assembler
+	support is enabled by default.
+	* gas/maxq10/range.d: Likewise.
+	* gas/maxq20/call.d: Likewise.
+
+2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/mapping.d: Expect F markers for Thumb code.
+	* gas/arm/unwind.d: Update big-endian pattern.
+
+2004-11-12  Nick Clifton  <nickc@redhat.com>
+
+	* gas/mn10300/basic.exp: Add relax test.
+	* gas/mn10300/relax.s: New test.
+	* gas/mn10300/relax.d: Expected results.  Make sure that the
+	correct size of instruction has been selected.
+
+2004-11-11  Bob Wilson  <bob.wilson@acm.org>
+
+	* gas/xtensa/short_branch_offset.s: New.
+	* gas/xtensa/short_branch_offset.d: New.
+	* gas/xtensa/all.exp: Run new test.
+
+2004-11-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/opcode.s: Pad section.
+	* gas/i386/intelok.s: Likewise.
+	* gas/i386/opcode.d: Update.
+	* gas/i386/intelok.d: Update.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* gas/maxq10: New directory.  Contains tests for maxq port.
+	* gas/maxq20: Likewise.
+
+2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/general.s: Add movzb.
+	* gas/i386/general.l: Updated.
+
+2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/all/gas.exp: Exclude float.s for crisv32-*-*.
+	* gas/cris/operand-err-1.s (test.m constant): Remove xfail marker
+	and update rationale.  Mark "ba [external_symbol]" and "ba [r3]"
+	as invalid.
+	* gas/ieee-fp/x930509a.exp: setup_xfail for crisv32-*-*.
+	* gas/macros/macros.exp: setup_xfail strings for crisv32-*-*.
+	* gas/cris/abs32-1.s, gas/cris/arch-err-1.s,
+	gas/cris/arch-err-2.s, gas/cris/arch-err-3.s,
+	gas/cris/arch-err-4.s, gas/cris/arch-err-5.s,
+	gas/cris/bound-err-1.s, gas/cris/brokw-3b.s,
+	gas/cris/march-err-1.s, gas/cris/march-err-2.s,
+	gas/cris/push-err-1.s, gas/cris/push-err-2.s,
+	gas/cris/pushpopv32.s, gas/cris/rd-abs32-1.d,
+	gas/cris/rd-abs32-2.d, gas/cris/rd-arch-1.d, gas/cris/rd-arch-2.d,
+	gas/cris/rd-arch-3.d, gas/cris/rd-bkw1b.d, gas/cris/rd-bkw2b.d,
+	gas/cris/rd-bkw3b.d, gas/cris/rd-bound1.d, gas/cris/rd-bound1.s,
+	gas/cris/rd-bound2.d, gas/cris/rd-bound3.d, gas/cris/rd-bound4.d,
+	gas/cris/rd-break32.d, gas/cris/rd-ppv1032.d, gas/cris/rd-ppv32.d,
+	gas/cris/rd-spr-1.d, gas/cris/rd-spr-1.s, gas/cris/rd-usp-1.d,
+	gas/cris/rd-usp-1b.d, gas/cris/rd-v10_32o-1.d,
+	gas/cris/rd-v10_32o-2.d, gas/cris/rd-v10_32o-2.s,
+	gas/cris/rd-v32-b1.d, gas/cris/rd-v32-b1.s, gas/cris/rd-v32-b2.d,
+	gas/cris/rd-v32-b2.s, gas/cris/rd-v32-b3.d, gas/cris/rd-v32-b3.s,
+	gas/cris/rd-v32-f1.d, gas/cris/rd-v32-f1.s, gas/cris/rd-v32-i1.d,
+	gas/cris/rd-v32-i1.s, gas/cris/rd-v32-l1.d, gas/cris/rd-v32-l1.s,
+	gas/cris/rd-v32-l3.d, gas/cris/rd-v32-l3.s, gas/cris/rd-v32-l4.d,
+	gas/cris/rd-v32-l4.s, gas/cris/rd-v32o-1.d, gas/cris/rd-v32s-1.d,
+	gas/cris/rd-v32s-2.d, gas/cris/rd-v32s-2.s, gas/cris/rd-v32s-3.d,
+	gas/cris/rd-v32s-3.s, gas/cris/rd-v32s-4.d, gas/cris/rd-v32s-4.s,
+	gas/cris/rd-vao-1.d, gas/cris/v32-err-1.s, gas/cris/v32-err-10.s,
+	gas/cris/v32-err-11.s, gas/cris/v32-err-2.s, gas/cris/v32-err-3.s,
+	gas/cris/v32-err-4.s, gas/cris/v32-err-5.s, gas/cris/v32-err-6.s,
+	gas/cris/v32-err-7.s, gas/cris/v32-err-8.s, gas/cris/v32-err-9.s:
+	New tests.
+
+2004-11-04 Jan Beulich <jbeulich@novell.com>
+
+	* gas/i386/i386.exp: Execute new tests intelbad and intelok.
+	* gas/i386/intelbad.[sl]: New test to check for various things not
+	permitted in Intel mode.
+	* gas/i386/intel.d, gas/i386/opcode.d, gas/i386/x86-64-opcode.d:
+	Adjust for change to segment register store.
+	* gas/i386/intelok.[sd]: New test to check various Intel mode specific
+	things get handled correctly.
+	* gas/i386/x86_64.[sd]: Remove unsupported constructs referring to
+	'high' and 'low' parts of an operand, which the parser previously
+	accepted while neither telling that it's not supported nor that it
+	ignored the remainder of the line following these supposed keywords.
+
+2004-10-28  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/cop_insn.d: Regenerate (after a bug fix in Assembler).
+
+2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/cop_insn.s: Test new Co-Processor instruction 'cpi'.
+	* gas/crx/list_insn.s: Add hi/lo/u<N> registers tests, fix test bugs.
+	* gas/crx/cop_insn.d: Regenerate.
+	* gas/crx/list_insn.d: Likewise.
+
+2004-10-23  Daniel Jacobowitz  <dan@debian.org>
+
+	* gas/cfi/cfi-arm-1.d, gas/cfi/cfi-arm-1.s: New files.
+	* gas/cfi/cfi.exp: Run cfi-arm-1 test.
+
+2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/cop_insn.s: Reverse operands order in store co-processor
+	instructions.
+	* gas/crx/list_insn.s: Remove test for unsupported 'popa' instruction.
+	* gas/crx/cop_insn.d: Regenerate.
+	* gas/crx/list_insn.d: Likewise.
+
+2004-10-14  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/mapping.d: Pass --special-syms to objdump.
+
+2004-10-08  Daniel Jacobowitz  <dan@debian.org>
+
+	* gas/i386/i386.exp: Don't run divide test for targets where '/'
+	is a comment.  Run x86-64-unwind for 64-bit ELF targets.
+	* gas/i386/x86-64-unwind.d, gas/i386/x86-64-unwind.s: New.
+
+2004-10-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/cfi/cfi-common-4.d: Correct for 64 bit targets.
+
+2004-10-07  Bob Wilson  <bob.wilson@acm.org>
+
+	* gas/xtensa/all.exp: Adjust expected error message for j_too_far.
+	Change entry_align test to expect an error.
+	* gas/xtensa/entry_misalign2.s: Use no-transform instead of
+	no-generics directives.
+
+2004-10-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel{23,24}.[sd]: New tests.
+	* gas/mips/mips.exp: New test.
+
+2004-10-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel22.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-10-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel21.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-10-07  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/cfi/cfi-common-4.[ds]: New.
+	* gas/cfi/cfi.exp: Run new test.
+
+2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx/cop_insn.s: New file.
+	* gas/crx/cop_insn.d: Likewise.
+	* gas/crx/load_stor_insn.s: Move Co-processor insns to a separate
+	test.
+	* gas/crx/misc_insn.s: Likewise.
+	* gas/crx/load_stor_insn.d: Regenerate.
+	* gas/crx/misc_insn.d: Likewise.
+
+2004-10-06  Aldy Hernandez  <aldyh@redhat.com>
+
+	* gas/ppc/e500.s: Add double-precision instructions.
+	* gas/ppc/e500.d: Same.
+
+2004-10-05  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arm.exp: Add unwind table test.  Recognise
+	arm-symbian-symbianelf and arm-none-eabi.
+	* gas/arm/unwind.s: New file.
+	* gas/arm/unwind.d: New file.
+
+2004-10-01  Bill Farmer  <Bill@the-farmers.freeserve.co.uk>
+
+	* gas/pdp11/opcode.d: Fix sob opcode value.
+
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arch6zk.d: New file.
+	* gas/arm/arch6zk.s: New file.
+	* gas/arm/arm.exp: Add them.
+
+2004-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/secrel.s: Pad .rdata out to 16 byte boundary.
+	* gas/i386/secrel.d: Adjust to suit.
+
+2004-09-19  Paul Brook  <paul@codesourcery.com>
+
+	* gas/elf/elf.exp: Recognise additional arm elf targets.
+
+2004-09-17  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/pic.s: Add (target2).
+	* gas/arm/pic.d: Ditto.
+
+2004-09-13  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/pic.d: Rename RELABS to TARGET1.
+	* gas/arm/pic.s: Ditto.
+
+2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/crx: New directory.
+	* gas/crx/allinsn.exp: New test script.
+	* gas/crx/arith_insn.s: New file.
+	* gas/crx/arith_insn.d: Likewise.
+	* gas/crx/beq_insn.s: Likewise.
+	* gas/crx/beq_insn.d: Likewise.
+	* gas/crx/bit_insn.s: Likewise.
+	* gas/crx/bit_insn.d: Likewise.
+	* gas/crx/br_insn.s: Likewise.
+	* gas/crx/br_insn.d: Likewise.
+	* gas/crx/cmov_insn.s: Likewise.
+	* gas/crx/cmov_insn.d: Likewise.
+	* gas/crx/cmpbr_insn.s: Likewise.
+	* gas/crx/cmpbr_insn.d: Likewise.
+	* gas/crx/jscond_insn.s: Likewise.
+	* gas/crx/jscond_insn.d: Likewise.
+	* gas/crx/list_insn.s: Likewise.
+	* gas/crx/list_insn.d: Likewise.
+	* gas/crx/load_stor_insn.s: Likewise.
+	* gas/crx/load_stor_insn.d: Likewise.
+	* gas/crx/misc_insn.s: Likewise.
+	* gas/crx/misc_insn.d: Likewise.
+	* gas/crx/no_op_insn.s: Likewise.
+	* gas/crx/no_op_insn.d: Likewise.
+	* gas/crx/shift_insn.s: Likewise.
+	* gas/crx/shift_insn.d: Likewise.
+
+2004-08-27  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/frv/fr550-pack1.[sd]: New test.
+	* gas/frv/allinsn.exp: Run it.
+
+2004-08-27  Nick Clifton  <nickc@redhat.com>
+
+	* gas/i386/i386.exp: Allow pcrel test for COFF targets as well,
+	but not for PE targets.  Similarly for the absrel test.
+
+2004-08-26  Nick Clifton  <nickc@redhat.com>
+
+	* gas/i386/i386.exp: Group ELF specific tests together.  Move the
+	pcrel test into the ELF only section.  Use is_elf_format to test
+	for ELF based toolchains.
+
+2004-08-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/all/gas.exp: Use `string match ""' instead of `eq ""'.
+
+2004-08-24  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/altmacro.[sd]: Split out part from here...
+	* gas/all/altmac2.[sd]: ... to here.
+	* gas/all/excl.s: New.
+	* gas/all/gas.exp: Suppress both tests for a few targets known to
+	break. Run the new (split out) test only when the target doesn't
+	use '!' as a comment character.
+
+2004-08-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* gas/mips/branch-swap.s: New testcase.
+	* gas/mips/branch-swap.d: New testcase.
+	* gas/mips/mips.exp: Run the testcase.
+
+2004-08-18  Nick Clifton  <nickc@redhat.com>
+
+	* gas/macros/strings.s: Remove #NO_APP, accidentally committed as
+	part of another patch.
+
+2004-08-15  Nick Clifton  <nickc@redhat.com>
+
+	* gas/all/altmacro.d: Allow for rest of frag being padded to an
+	alignment boundary.
+
+	* gas/arm/arm.exp: Run bignum test for ELF based targets only.
+
+2004-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/cfi/cfi-alpha-1.d: Adjust for readelf fix.
+	* gas/cfi/cfi-alpha-3.d: Likewise.
+	* gas/cfi/cfi-i386.d: Likewise.
+	* gas/cfi/cfi-m68k.d: Likewise.
+	* gas/cfi/cfi-ppc-1.d: Likewise.
+	* gas/cfi/cfi-s390-1.d: Likewise.
+	* gas/cfi/cfi-s390x-1.d: Likewise.
+	* gas/cfi/cfi-sh-1.d: Likewise.
+	* gas/cfi/cfi-sparc-1.d: Likewise.
+	* gas/cfi/cfi-sparc64-1.d: Likewise.
+	* gas/cfi/cfi-x86_64.d: Likewise.
+
+2004-08-13 Jan Beulich <jbeulich@novell.com>
+
+	* gas/all/altmacro.[sd]: New test.
+	* gas/all/gas.exp: Run the new test.
+
+2004-08-10  Mark Mitchell  <mark@codesourcery.com>
+
+	* gas/arm/bignum1.s: New test.
+	* gas/arm/arm.exp: Run it.
+
+2004-08-06  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/pic.s,d: Test RELABS and SBREL relocations.
+
+2004-08-05  Nitin Yewale  <nitiny@kpitcummins.com>
+
+	* h8300/h8300.exp: Addition of new test case to check rx
+	generation with adds and subs instruction for plain H8/300 target.
+	* h8300/addsubrxcheck.s: New test source file.
+
+2004-08-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* gas/m68hc11/m68hc11.exp: Fix tests for 2.15
+	* gas/elf/elf.exp: Test obj-elf for m6811-* and m6812-*
+	* gas/symver/symver.exp: Likewise for symver tests.
+
+2004-07-30  Michal Ludvig  <mludvig@suse.cz>
+
+	* gas/i386/padlock.s, gas/i386/padlock.d: New tests for
+	VIA PadLock instructions.
+
+2004-07-29  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/basic.exp: Don't do sh2a test for sh5.
+	* gas/sh/sh2a.d: Match elf32-sh* format too.
+
+2004-07-29  Alexandre Oliva  <aoliva@redhat.com>
+
+	2003-12-30  DJ Delorie  <dj@redhat.com>
+	* gas/sh/sh2a.s: New.
+	* gas/sh/sh2a.d: New.
+	* gas/sh/basic.exp: Add it.
+
+2004-07-27  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* gas/all/gas.exp (do_930509a): Disable test for crx.
+
+2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-inval.l: Remove the leading `+'.
+
+2004-07-22  Nick Clifton  <nickc@redhat.com>
+
+	PR/280
+	* gas/h8300/ffxx1-coff.d: Remove duplicated raw insn values.
+	* gas/h8300/ffxx1-elf.d: Likewise.
+	* gas/h8300/h8sx_disp2.d: Likewise.
+	* gas/h8300/h8sx_mov_imm.d: Likewise.
+	* gas/h8300/h8sx_rtsl.d: Likewise.
+	* gas/h8300/ffxx1-coff.s: Remove inappropriate insn width specifier.
+	* gas/h8300/ffxx1-elf.s: Likewise.
+
+2004-07-21  Jan Beulich <jbeulich@novell.com>
+
+	* gas/i386/x86-64-addr32.[ds]: New test for x86-64 32-bit
+	addressing in 64-bit mode.
+	* gas/i386/x86-64-rip.[ds]: New test for x86-64 rip-relative
+	addressing.
+	* gas/i386/i386.exp: Run the two new tests.
+
+	* gas/cfi/cfi-x86_64.d: Adjust expectation for leave to	not have a
+	rex prefix.
+	* gas/i386/x86-64-inval.[ls]: Add a bunch of instructions illegal
+	in 64-bit mode.
+
+2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/elf-rel19.d: Pass -march=mips1 to gas as the test
+	expects load delay slots.
+
+2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/vr5400.d: Update for a correct disassembly of
+	"racm.ob".
+
+2004-07-20  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/mips32.s: Adjust for the unified "break" syntax.  Add
+	another "break" case.  Update the comment accordingly.
+	* gas/mips/set-arch.s: Likewise.
+	* gas/mips/mips32.d: Adjust for the new output.
+	* gas/mips/set-arch.d: Likewise.
+
+2004-07-15  Nitin Yewale <nitiny@kpitcummins.com>
+
+	* gas/h8300/h8300.exp (do_h8300hn_addressgen): Addition of
+	new test case for H8300H normal target to check symbol
+	address generation.
+	* gas/h8300/symaddgen.s: New test.
+
+2004-07-13  Nick Clifton  <nickc@redhat.com>
+
+	* gas/i386/intel.s: Add test of newly expand arithmetic support
+	for Intel mode assembler.
+	* gas/i386/intel.d: Add expected disassmbly.
+
+2004-07-13  Nick Clifton  <nickc@redhat.com>
+
+	* gas/vtable: Delete directory.  These tests are no longer needed
+	as the VTABLE_ reloc support is obsolete.
+
+2004-07-08  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/pic.exp: Add New Test case for @GOTOFF, @GOT, @PLT.
+	* gas/m32r/pic2.s: New file: Test case for @GOTOFF, @GOT, @PLT.
+	* gas/m32r/pic2.d: New file: Expected results.
+
+2004-07-08  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel7.d: Expect relocations against bar to refer to bar.
+	* gas/mips/elf-refl19.d: Likewise L2.
+
+2004-07-03  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf{,el}-rel.d: Adjust so that the earliest %hi() matches
+	the earliest %lo().
+	* gas/mips/elf-rel11.d: Don't expect the relocs to be reordered.
+	* gas/mips/elf-rel20.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-07-03  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/elf-rel9.[sd]: Fix typo in %lo() expression.
+
+2004-07-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/group-1.d: New.
+	* gas/ia64/group-1.s: Likewise.
+
+	* gas/ia64/ia64.exp: Add group-1 to test comdat group.
+
+2004-06-30  James E Wilson  <wilson@specifixinc.com>
+
+	* gas/ia64/dv-imply.d: Update.
+	* gas/ia64/dv-mutex.d: Likewise.
+	* gas/ia64/dv-safe.d: Likewise.
+
+2004-06-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/m68k/mode5.s: Pad section.
+	* gas/m68k/mode5.d: Update.
+
+2004-06-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/ppc/power4.d: Update.
+
+2004-06-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/prescott.s: Remove fisttpd and fisttpq.
+	* gas/i386/prescott.d: Update.
+
+2004-06-08  Jakub Jelinek  <jakub@redhat.com>
+
+	* gas/ia64/dv-raw-err.s: Add some new postinc tests.
+	* gas/ia64/dv-raw-err.l: Updated.
+
+2004-05-28  Peter Barada <peter@the-baradas.com>
+
+	* gas/m68k/mode5.s: New test file.  Checks conversion of mode 5
+	addressing with zero offset into mode 2 addressing.
+	* gas/m68k/mode5.d: New file: Expected disassmbly.
+	* gas/m68k/all.exp: Run new test.
+
+2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	* gas/sh/arch: New directory.
+	* gas/sh/arch/arch.exp: New test script.
+	* gas/sh/arch/arch_expected.txt: New file.
+	* gas/sh/arch/sh.s: New file.
+	* gas/sh/arch/sh2.s: New file.
+	* gas/sh/arch/sh-dsp.s: New file.
+	* gas/sh/arch/sh2e.s: New file.
+	* gas/sh/arch/sh3-nommu.s: New file.
+	* gas/sh/arch/sh3.s: New file.
+	* gas/sh/arch/sh3-dsp.s: New file.
+	* gas/sh/arch/sh3e.s: New file.
+	* gas/sh/arch/sh4-nommu-nofpu.s: New file.
+	* gas/sh/arch/sh4-nofpu.s: New file.
+	* gas/sh/arch/sh4.s: New file.
+	* gas/sh/arch/sh4a-nofpu.s: New file.
+	* gas/sh/arch/sh4al-dsp.s: New file.
+	* gas/sh/arch/sh4a.s: New file.
+
+2004-05-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/regs.d: Updated.
+
+2004-05-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/ia64.exp: Run invalid-ar.
+
+	* gas/ia64/invalid-ar.l: New file. Test invalid AR access.
+	* gas/ia64/invalid-ar.s: Likewise.
+
+2004-05-24  Peter Barada  <peter@the-baradas.com>
+
+	* gas/m68k/mcf-emac.d: Provide correct disassembler results.
+	* gas/m68k/mcf-mac.d: Provide correct disassembler results.
+
+2004-05-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/dv-srlz.d: Fix a typo.
+
+2004-05-12  Ben Elliston  <bje@au.ibm.com>
+
+	* gas/h8300/t03_add.exp: Remove stray semicolons.
+	* gas/h8300/t04_sub.exp: Likewise.
+	* gas/h8300/t05_cmp.exp: Likewise.
+	* gas/h8300/t08_or.exp: Likewise.
+	* gas/h8300/t09_xor.exp: Likewise.
+	* gas/h8300/t10_and.exp: Likewise.
+	* gas/hppa/reloc/reloc.exp: Likewise.
+	* gas/hppa/unsorted/unsorted.exp: Likewise.
+	* gas/i386/i386.exp: Likewise.
+	* gas/m68hc11/m68hc11.exp: Likewise.
+	* gas/mips/mips.exp: Likewise.
+	* gas/sparc/sparc.exp: Likewise.
+	* lib/gas-defs.exp: Likewise.
+
+2004-05-11  Nick Clifton  <nickc@redhat.com>
+
+	* gas/elf/section4.s: New test.  Checks label arithmetic when
+	multiple same-name sections exist.
+	* gas/elf/section4.d: New file: Expected section list
+	* gas/elf/elf.exp: Run the new test.
+	* gas/elf/group0.s: Use % instead of @ for type argument to
+	.section directive (for compatability with ARM port).
+	* gas/elf/group1.s: Likewise.
+
+2004-05-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/vr4122.[sd]: Rename to...
+	* gas/mips/vr4120-2.[sd]: ...and add tests for VR4181A errata
+	MD(1) and MD(4).
+	* gas/mips/mips.exp: Update accordingly.
+
+2004-05-05  Alexandre Oliva  <aoliva@redhat.com>
+
+	* gas/frv/reloc1.d: Match elf32-frvfdpic as well.
+	* gas/frv/fr405-insn.d: Likewise.
+	* gas/frv/fr450-insn.d: Likewise.
+
+2004-04-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/elf/elf.exp: Remove group1, add group1a and group1b for
+	section group.
+
+	* gas/elf/group1a.d: New file.
+	* gas/elf/group1b.d: Likewise.
+
+	* gas/elf/group1.e: Removed.
+
+2004-04-30  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/reg-alias.s: New file: Test case sensitive register
+	aliases.
+	* gas/arm/reg-alias.d: New file: Expected test output.
+	* gas/arm/arm.exp: Run reg-alias test.
+	Arrange tests in a more orderly fashion.
+
+2004-04-30  Ben Elliston  <bje@au.ibm.com>
+
+	* gas/ppc/power4.s: Add dcbz and dcbzl test cases.
+	* gas/ppc/power4.d: Update accordingly.
+
+2004-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/elf/elf.exp: Add group0a, group0b and group1 for section
+	group.
+
+	* gas/elf/group0.s: New file.
+	* gas/elf/group0a.d: Likewise.
+	* gas/elf/group0b.d: Likewise.
+	* gas/elf/group1.e: Likewise.
+	* gas/elf/group1.s: Likewise.
+
+2004-04-23  Nick Clifton  <nickc@redhat.com>
+
+	* gas/symver/symver1.d: Cope with extra symbols inserted by
+	arm-elf toolchains.
+	* gas/symver/symver0.d: Likewise
+	* gas/elf/symver.d: Likewise.
+
+2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/pcrel2.d: Update.
+	* gas/sh/tlsd.d: Update.
+	* gas/sh/tlsnopic.d: Update.
+	* gas/sh/tlspic.d: Update.
+
+2004-04-22  Mark Kettenis  <kettenis@gnu.org>
+
+	* lib/gas-defs.exp (is_elf_format): Add OpenBSD support.
+
+2004-04-22  Atsushi Nemoto  <anemo@mba.ocn.ne.jp>
+
+	* gas/mips/lb-xgot-ilocks.d: Remove nops in load delay slot.
+	* gas/mips/mips-abi32-pic.d: Likewise.
+	* gas/mips/mips-abi32-pic2.d: Likewise.
+	* gas/mips/mips-gp32-fp32-pic.d: Likewise.
+	* gas/mips/mips-gp32-fp64-pic.d: Likewise.
+	* gas/mips/mips-gp64-fp32-pic.d: Likewise.
+	* gas/mips/mips-gp64-fp64-pic.d: Likewise.
+	* gas/mips/relax-swap1-mips2.d: Likewise.
+	* gas/mips/lb-svr4pic-ilocks.d: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-04-22  Paul Brook  <paul@codesourcery.com>
+
+	* maverick.c (off8s): Test full shifted operand range.
+	(MCC2): Define.
+	(MVDSPACC, MVACCDSP): Use it.
+	* maverick.d, maverick.s: Regenerate.
+
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* gas/m68k/mcf-mac.s: New test: Check ColdFire MAC instructions.
+	* gas/m68k/mcf-emac.s: New test: Similar checks.
+	* gas/m68k/mcf-mac.d: New test: Expected output.
+	* gas/m68k/mcf-emac.d: New test: Likewise.
+	* gas/m68k/all.exp: Run new tests.
+
+2004-04-21  Chris Demetriou  <cgd@broadcom.com>
+
+	* gas/mips/elempic.d: File removed as part of -membedded-pic removal.
+	* gas/mips/empic.d: Likewise.
+	* gas/mips/empic.l: Likewise.
+	* gas/mips/empic.s: Likewise.
+	* gas/mips/empic2.d: Likewise.
+	* gas/mips/empic2.s: Likewise.
+	* gas/mips/empic3_e.d: Likewise.
+	* gas/mips/empic3_e.s: Likewise.
+	* gas/mips/empic3_g1.d: Likewise.
+	* gas/mips/empic3_g1.s: Likewise.
+	* gas/mips/empic3_g2.d: Likewise.
+	* gas/mips/empic3_g2.s: Likewise.
+	* gas/mips/jal-empic-elf-2.d: Likewise.
+	* gas/mips/jal-empic-elf-2.s: Likewise.
+	* gas/mips/jal-empic-elf-3.d: Likewise.
+	* gas/mips/jal-empic-elf-3.s: Likewise.
+	* gas/mips/jal-empic-elf.d: Likewise.
+	* gas/mips/jal-empic.d: Likewise.
+	* gas/mips/la-empic.d: Likewise.
+	* gas/mips/la-empic.s: Likewise.
+	* gas/mips/lb-empic.d: Likewise.
+	* gas/mips/ld-empic.d: Likewise.
+	* gas/mips/lif-empic.d: Likewise.
+	* gas/mips/telempic.d: Likewise.
+	* gas/mips/tempic.d: Likewise.
+	* gas/mips/ulh-empic.d: Likewise.
+	* gas/mips/ld-pic.s: Remove code conditional on EMPIC.
+	* gas/mips/lifloat.s: Likewise.
+	* gas/mips/mips.exp: Remove -membedded-pic tests and related comments.
+
+2004-04-20  Brian Ford  <ford@vss.fsi.com>
+	    DJ Delorie  <dj@redhat.com>
+
+	* gas/i386/secrel.s: New test for .secrel32.
+	* gas/i386/secrel.d: Likewise.
+	* gas/i386/i386.exp: Call it for PE targets.
+
+2004-04-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* gas/cfi/cfi-sparc64-1.d: Update.
+
+2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/vr4122.[sd]: Change option to -mfix-vr4120.
+
+2004-04-14  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/elf/section2.e-mips: Allow named section symbols.
+	* gas/mips/{,el}empic.d, gas/mips/mips{,el}16-[ef].d: Likewise.
+
+2004-04-13  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/parallel-2.s: New file: Test	case for parallel code.
+	* gas/m32r/parallel-2.d: New file: Expected results.
+	* gas/m32r/m32r2.exp: Run the test.
+
+	* gas/m32r/seth.s: New file: Test for seth.
+	* gas/m32r/seth.d: New file: Expected results.
+	* gas/m32r/m32r.exp: Run the new test.
+
+2004-04-01  Asgari Jinia  <asgarij@kpitcummins.com>
+
+	* gas/sh/renesas-1.s, gas/sh/renesas-1.d: New test for -renesas
+	option.
+	* gas/sh/basic.exp: Run the new test.
+
+2004-04-01  Dave Korn  <dk@artimi.com>
+
+	* gas/dlx/alltests.exp: Execute new lohi test.
+	* gas/dlx/lohi.s: New test for spurious lo16/hi16
+	reloc overflow checking.
+	* gas/dlx/lohi.d: New file: expected output.
+	* gas/dlx/lhi.d: Updated to properly expect lo16
+	relocations where asked for.
+	* gas/dlx/itype.d: Likewise.
+	* gas/dlx/lhi.d: Corrected cut+paste error in test name.
+
+2004-03-30  Stan Shebs  <shebs@apple.com>
+
+	* gas/macros/macros.exp: Remove mention of MPW config.
+
+2004-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i860/dir-intel03-err.l: Update for junk at end line becoming
+	an error.
+	* gas/m68hc11/m68hc11.exp: Likewise.
+
+2004-03-23  Andreas Schwab  <schwab@suse.de>
+
+	* gas/cfi/cfi-m68k.d: Adjust offsets.
+
+2004-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/cris/regreg.d: Assemble with --no-mul-bug-abort.
+	* gas/cris/mulbug-err-1.s, gas/cris/rd-mulbug-1.d: New tests.
+
+2004-03-17  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/cfi/cfi-sh-1.d: New file.
+	* gas/cfi/cfi-sh-1.s: Likewise.
+	* gas/cfi/cfi.exp: Add SH case.
+
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/ppc/altivec.d: Update.
+	* gas/ppc/altivec_xcoff.d: Update.
+	* gas/ppc/altivec_xcoff64.d: Update.
+	* gas/ppc/astest.d: Update.
+	* gas/ppc/astest2.d: Update.
+	* gas/ppc/astest2_64.d: Update.
+	* gas/ppc/astest64.d: Update.
+	* gas/ppc/booke.d: Update.
+	* gas/ppc/booke_xcoff.d: Update.
+	* gas/ppc/booke_xcoff64.d: Update.
+	* gas/ppc/e500.d: Update.
+	* gas/ppc/power4.d: Update.
+	* gas/ppc/test1elf32.d: Update.
+	* gas/ppc/test1elf64.d: Update.
+	* gas/ppc/test1xcoff32.d: Update.
+
+2004-03-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/padlock.s: Pad with .p2align.
+	* gas/i386/padlock.d: Adjust.
+
+2004-03-12  Michal Ludvig  <mludvig@suse.cz>
+
+	* gas/i386/padlock.s, gas/i386/padlock.d: New tests for
+	VIA PadLock instructions.
+	* gas/i386/i386.exp: Run padlock tests.
+
+2004-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/katmai.d: Revert last change.
+
+	* gas/i386/katmai.d: Adjust for clflush change.
+
+2004-03-08  Andreas Jaeger  <aj@suse.de>
+
+	* gas/cfi/cfi-s390x-1.d: Adjust offsets.
+
+2004-03-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/cfi/cfi-common-2.d, gas/cfi/cfi-i386.d: Adjust offsets.
+
+2004-03-07  Andreas Jaeger  <aj@suse.de>
+
+	* gas/cfi/cfi-x86_64.d: Adjust offsets.
+
+2004-03-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/alpha/elf-reloc-8.d, gas/cfi/cfi-alpha-1.d,
+	gas/cfi/cfi-alpha-2.d, gas/cfi/cfi-alpha-3.d, gas/cfi/cfi-common-1.d,
+	gas/cfi/cfi-common-2.d, gas/cfi/cfi-common-3.d: Adjust offsets.
+
+2004-03-03  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/sh64/err-dsp.s: Fix expected error message.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/frv/fr405-insn.[sdl]: New test.
+	* gas/frv/fr450-spr.[sd]: New test.
+	* gas/frv/fr450-insn.[sdl]: New test.
+	* gas/frv/fr450-media-issue.[sl]: New test.
+	* gas/frv/allinsn.exp: Run new tests.  Ensure fr405 instructions
+	aren't accepted for -mcpu=fr400 or -mcpu=fr500.  Ensure fr450
+	instructions aren't accepted for -mcpu=fr400, -mcpu=fr405 or
+	-mcpu=fr500.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
+	(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
+	* gas/frv/allinsn.d: Update accordingly.
+
+2004-02-17  Petko Manolov  <petkan@nucleusys.com>
+
+	* gas/arm/maverick.c: DSPSC to/from opcode fixes.
+	* gas/arm/maverick.d: Likewise.
+	* gas/arm/maverick.s: Likewise.
+
+2004-02-09  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/basic.exp: Don't do sh4a tests for sh5.
+
+2004-02-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/macros/test2.s: Lowercase it.
+
+2004-02-02  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* gas/mips/div.d: Update to accomodate changes in macro
+	expansions.
+	gas/mips/elf-rel-got-n32.d: Likewise.
+	gas/mips/elf-rel-got-n64.d: Likewise.
+	gas/mips/elf-rel-xgot-n32.d: Likewise.
+	gas/mips/elf-rel-xgot-n64.d: Likewise.
+	gas/mips/la-svr4pic.d: Likewise.
+	gas/mips/la-xgot.d: Likewise.
+	gas/mips/lca-svr4pic.d: Likewise.
+	gas/mips/lca-xgot.d: Likewise.
+
+2004-02-01  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* gas/sh/sh4a-fp.d: Fix opcode name fssra to fsrra.
+	* gas/sh/sh4a-fp.s: Likewise.
+	* gas/sh/err-sh4a-fp.s: Likewise.
+
+2004-01-24  Chris Demetriou  <cgd@broadcom.com>
+
+	* gas/mips/relax-swap1.s: Add extra space at end, so the
+	disassembly will consistently have "..." at its end.
+	* gas/mips/relax-swap2.s: Likewise.
+	* gas/mips/relax-swap1-mips2.d: Expect "..." at end of disassembly.
+
+2004-01-23  Daniel Jacobowitz  <drow@mvista.com>
+
+	* gas/arm/arm.exp: Add "undefined" test.
+	* gas/arm/undefined.s, gas/arm/undefined.l: New files.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/macro-warn-[1234].[sdl]: New tests.
+	* gas/mips/macro-warn-[12]-n32.[dl]: New tests.
+	* gas/mips/mips.exp: Run them.
+
+2004-01-23  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel19.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-01-11 Tom Rix   <tcrix@worldnet.att.net>
+
+	* gas/m68hc11/movb.s: Add m68hc12 movb and movw dump test.
+	* gas/m68hc11/movb.d: Likewise.
+	* gas/m68hc11/m68hc11.exp: Likewise.  Add more movb failure tests.
+
+2004-01-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/katmai.d: Adjust for changed sib printing.
+	* gas/i386/prescott.d: Likewise.
+	* gas/i386/sse2.d: Likewise.
+	* gas/i386/ssemmx2.d: Likewise.
+
+2004-01-16  Alexandre Oliva  <aoliva@redhat.com>
+
+	* gas/mn10300/mov5.s: New.
+	* gas/mn10300/basic.exp (do_mov5): New.
+
+2004-01-14  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
+
+	* gas/mips/relax-swap1-mips1.d: New test for branch relaxation
+	with swapping for MIPS1.
+	* gas/mips/relax-swap1-mips2.d: New test for branch relaxation
+	with swapping for MIPS2.
+	* gas/mips/relax-swap1.l: Stderr output for the new tests.
+	* gas/mips/relax-swap1.s: Source for the new tests.
+	* gas/mips/relax-swap2.d: New test for branch likely relaxation
+	with swapping.
+	* gas/mips/relax-swap2.l: Stderr output for the new test.
+	* gas/mips/relax-swap2.s: Source for the new test.
+	* gas/mips/mips.exp: Run the new tests.
+
+2004-01-13  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* gas/mips/mips16-64.d: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-01-12  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/elf-rel18.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2004-01-09  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/vfp2.s, gas/arm/vfp2.d: New test.
+	* gas/arm/arm.exp: Add them.
+
+2004-01-08  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* gas/mips/ldstla-n64.d: Pass -64 to assembler, not -n64.
+	* gas/mips/ldstla-n64-shared.d: Likewise.
+
+2004-01-07  Nick Clifton  <nickc@redhat.com>
+
+	* gas/cris/rd-dw2-1.d: Expect a pointer size from readelf.
+
+2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	2003-11-05  Alexandre Oliva  <aoliva@redhat.com>
+	* lib/gas-defs.exp (is_elf_format): Match frv-uclinux.
+	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
+	* gas/frv/fdpic.s, gas/frv/fdpic.d: Renamed from ucpic*.
+	2003-09-15  Alexandre Oliva  <aoliva@redhat.com>
+	* gas/frv/ucpic.s, gas/frv/ucpic.d: Use gr15 as PIC register.  Use
+	gprel12 for rodata symbol and gotoff12 for sdata symbol.
+	2003-08-08  Alexandre Oliva  <aoliva@redhat.com>
+	* gas/frv/ucpic.d: Test gotoff and gotofffuncdesc.
+	2003-08-04  Alexandre Oliva  <aoliva@redhat.com>
+	* gas/frv/ucpic.d, gas/frv/ucpic.s: New.
+	* gas/frv/allinsns.exp: Run it.
+
+2004-01-02  Albert Bartoszko  <albar@nt.kegel.com.pl>
+
+	* gas/msp430/opcode.s: Add test for an 'add' instruction which
+	looks similar to an 'rla' instruction.
+
+For older changes see ChangeLog-9303
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/testsuite/ChangeLog-2005 b/gas/testsuite/ChangeLog-2005
new file mode 100644
index 000000000000..838222eaa2be
--- /dev/null
+++ b/gas/testsuite/ChangeLog-2005
@@ -0,0 +1,1679 @@
+2005-12-22  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/cond.s: Also check .if works on equates to undefined
+	when the expression value can be known without knowing the
+	value of the symbol.
+	* gas/all/cond.l: Adjust.
+	* gas/i386/equ.s: Also check .if works on (equates to)
+	registers when the expression value can be known without
+	knowing the value of the register.
+	* gas/i386/equ.e: Adjust.
+
+2005-12-14  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/rex.[sd]: New.
+	* gas/i386/i386.exp: Run new test.
+
+2005-12-12  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* gas/mt: Renamed from ms1 dir.  Update file names as needed.
+	* gas/mt/errors.exp: Replace ms1 arch with mt arch.
+	* gas/mt/mt.exp: Replace ms1 arch with mt arch.
+	* gas/mt/relocs.exp: Replace ms1 arch with mt arch.
+
+2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/cris/rd-bcnst-pic.d, gas/cris/rd-branch-pic.d,
+	gas/cris/rd-brokw-pic-1.d, gas/cris/rd-brokw-pic-2.d,
+	gas/cris/rd-brokw-pic-3.d, gas/cris/rd-fragtest-pic.d: New tests.
+
+2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR gas/1874
+	* gas/i386/i386.exp: Add x86-64-prescott for 64bit.
+
+	* gas/i386/prescott.s: Test address size override for monitor.
+	* gas/i386/prescott.d: Updated.
+
+	* gas/i386/x86-64-prescott.d: New file.
+	* gas/i386/x86-64-prescott.s: Likewise.
+
+2005-12-06  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/cris/rd-pcplus.s, gas/cris/rd-pcplus.d: New test.
+
+2005-11-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* gas/macros/purge.l: Increment line numbers.
+	* gas/macros/purge.s: Add ".data" line.
+
+	Bug gas/1896
+	* gas/all/redef2.d: Allow "$DATA$" as well as ".data" in matches.
+	* gas/all/weakref1.d: Allow "$CODE$" as well as ".text" in matches.
+	* gas/hppa/reloc/reloc.exp: Adjust regexp for new output.
+
+2005-11-23  Daniel Jacobowitz  <dan@codesourcery.com>
+	    Thiemo Seufer <ths@networkno.de>
+
+	* gas/mips/bge.d, gas/mips/bge.s, gas/mips/bgeu.d, gas/mips/bgeu.s,
+	gas/mips/blt.d, gas/mips/blt.s, gas/mips/bltu.d,
+	gas/mips/bltu.s: Reactivate external branch tests.
+	* gas/mips/branch-misc-2.d, gas/mips/branch-misc-2pic.d,
+	gas/mips/branch-misc-2-64.d, gas/mips/branch-misc-2pic-64.d: New
+	tests.
+	* gas/mips/branch-misc-2.l, gas/mips/branch-misc-2pic.l,
+	gas/testsuite/gas/mips/branch-misc-2pic.s: Remove.
+	* gas/mips/mips.exp: Adjust branch-misc-2 tests.  Add 64-bit
+	variants.
+
+2005-11-22  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* gas/all/quad.d: Add -j "\$DATA\$".  Modify regexp to check for
+	"$DATA$" as well as ".data".
+	* gas/all/sleb128.d: Likewise.
+
+2005-11-20  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	Bug gas/1894 Bug gas/1895
+	* gas/all/gas.exp (redef3): xfail on hppa*-*-hpux*.
+	* gas/all/redef.d: Add -j "\$DATA\$".  Modify regexp to check for
+	"$DATA$" as well as ".data".
+	* gas/all/redef2.d: Likewise.
+
+	Bug gas/1879
+	* gas/all/weakref1.d: Check for "$CODE$" as well as ".text".
+	* gas/all/weakref1.s: Indent "-ld1 = l".
+	* gas/all/weakref1g.d: Remove --no-sort option.
+	* gas/all/weakref1l.d: Likewise.
+	* gas/all/weakref1u.d: Likewise.  Sort expected results.
+	* gas/all/weakref1w.d: Likewise.
+	* gas/all/weakref2.s: Indent directives.
+	* gas/all/weakref3.s: Likewise.
+
+2005-11-17  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/cond.s: Also check ifdef works on equates and
+	commons.
+	* gas/all/cond.l: Adjust.
+	* gas/all/redef2.s: Also test redefining equate to label.
+	* gas/all/redef2.d: Adjust.
+	* gas/all/redef3.[sd]: New.
+	* gas/all/redef4.s: New.
+	* gas/all/redef5.s: New.
+	* gas/elf/redef.s: New, copied from original gas/all/redef2.s.
+	* gas/elf/redef.d: Remove #source.
+	* gas/all/gas.exp: Remove exclusion of iq2000-*-* from and
+	adjust xfails for redefinition tests. Run new tests. Exclude
+	alpha*-*-*, mips*-*-*, *c54x*-*-* from weakref tests.
+
+2005-11-16  Richard Henderson  <rth@redhat.com>
+
+	* gas/all/weakref1.s: Use "=" instead of ".set" for equivalence.
+
+2005-11-15  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/unwind.s, gas/arm/unwind.d, gas/arm/unwind_vxworks.d: Add
+	a test for saving only the low registers.
+
+2005-11-14  Thiemo Seufer  <ths@networkno.de>
+
+	* gas/testsuite/gas/mips/mips16e-jrc.d: Tighten file format
+	check, relax whitespace checking.
+
+2005-11-14  David Ung  <davidu@mips.com>
+
+	* gas/mips/mips.exp: Run new save/restore tests.
+	* gas/testsuite/gas/mips/mips16e-save.s: New test for generating
+	different styles of save/restore instructions.
+	* gas/testsuite/gas/mips/mips16e-save.d: New.
+
+2005-11-10  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intelbad.d: Add tests for ill registers in brackets.
+	* gas/i386/intelbad.l: Adjust.
+
+2005-11-10  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/archv6t2-bad.s: Add tests of badly composed ldrex and
+	strex instructions.
+	* gas/arm/archv6t2-bad.l: Add expected error messages.
+	* gas/arm/r15-bad.l: Adjust error messages for r15 usage in ldrex
+	and strex instructions.
+
+2005-11-08  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* gas/all/cofftag.s: Convert numbers in .type 
+	directives to decimal.
+	* gas/all/gas.exp: enable cofftag-test for z80-*-coff.
+
+2005-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	Add ms2.
+	* gas/ms1/allinsn.d: Adjust pcrel disassembly.
+	* gas/ms1/errors.exp: Fix target triplet.
+	* gas/ms1/ms1-16-003.d: Adjust pcrel disassembly.
+	* gas/ms1/ms1-16-003.s: Tweak label.
+	* gas/ms1/ms1.exp: Adjust target triplet.  Add ms2 test.
+	* gas/ms1/ms2.d, gas/ms1/ms2.s: New.
+	* gas/ms1/relocs.d: Adjust expected machine name and pcrel
+	disassembly. 
+	* gas/ms1/relocs.exp: Adjust target triplet.
+
+2005-11-07  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/redef2.[sd]: New.
+	* gas/all/gas.exp: Run new test.
+	* gas/elf/redef.d: New.
+	* gas/elf/elf.exp: Run new test.
+
+2005-11-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/i386/divide.s: Test line comment starting with '/'.
+	* gas/i386/divide.d: Pass --divide to gas.
+	* gas/i386/intelok.d: Likewise.
+	* gas/i386/i386.exp (divide): Run for all targets.
+
+2005-11-07  Arnold Metselaar <arnold.metselaar@planet.nl>
+
+	* gas/z80/z80.exp: Added "suffix" test.
+	* gas/z80/suffix.s: New file.
+	* gas/z80/suffix.d: New file.
+
+2005-11-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/padlock.d: Support 64bit BFD.
+
+2005-11-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* gas/all/gas.exp: Remove weakref xfail.  Run weakref4.s.
+	* gas/all/weakref1.s: Move redefinition bits to...
+	* gas/all/weakref4.s: ... new file.
+	* gas/all/weakref1.d: Remove command moved to weakref1u.  Adjust
+	remaining command for leading tabs.  Regenerate.
+	* gas/all/weakref1l.d: Regenerate.
+	* gas/all/weakref1u.d: Likewise.
+	* gas/all/wealref1w.d: Likewise.
+
+2005-11-04  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/gas.exp: xfail weakref dump tests for all targets.
+
+2005-10-29  Hans-Peter Nilsson  <hp@axis.com>
+
+	PR gas/1630
+	* gas/all/gas.exp <weakref1, weakref1g, weakref1l, weakref1u,
+	weakref1w>: Xfail for cris-*-* and mmix-*-*.
+
+2005-10-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/equ.d: Fix typo.
+	* gas/i386/equ.s: Don't globalize r.
+
+2005-10-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/gas.exp: Don't xfail equiv1 test anymore.
+
+2005-10-26  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/archv6.d: Adjust expected output.
+
+2005-10-26  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intel.s: Replace register used in offset expression.
+	* gas/i386/intel.e: Adjust.
+	* gas/i386/intelbad.l: Adjust.
+	* gas/i386/equ.[sed]: New.
+	* gas/i386/i386.exp: Run new test.
+
+2005-10-26  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* gas/z80/z80.exp: Fix misplaced-open-brace typo.
+
+2005-10-25  Arnold Metselaar  <arnold.metselaar@planet.nl>
+
+	* gas/all/gas.exp: Exclude Z80-*-* from floating point, string,
+	and cofftag test.
+	* gas/macros/macros.exp: Expect z80-*-* to fail the strings test
+	because it has no string escapes.
+	* gas/z80/quotes.d: New file
+	* gas/z80/quotes.d: New file
+	* gas/z80/quotes.s: New file
+	* gas/z80/redef.d: New file
+	* gas/z80/redef.s: New file
+	* gas/z80/z80.exp: New file
+	
+2005-10-24  Bernd Schmidt  <bernd.schmidt@analog.com>
+
+	* gas/bfin/flow2.d: Match changed assembler behaviour.
+	* gas/bfin/reloc.d: Likewise.
+
+2005-10-24  Alexandre Oliva  <aoliva@redhat.com>
+
+	* gas/all/weakref1.s, gas/all/weakref1.d: New test.
+	* gas/all/weakref1g.d, gas/all/weakref1l.d: New tests.
+	* gas/all/weakref1u.d, gas/all/weakref1w.d: New tests.
+	* gas/all/weakref2.s, gas/all/weakref3.s: New tests.
+	* gas/all/gas.exp: Run new tests.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/index.[sl]: New.
+	* gas/ia64/rotX.[sl]: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/regs.pl: Also check tp alias of r13.
+	* gas/ia64/regs.s: Regenerate.
+	* gas/ia64/regs.d: Adjust.
+
+2005-10-19  David Ung  <davidu@mips.com>
+
+	* gas/mips/mips.exp: Run new test.
+	* gas/testsuite/gas/mips/mips16e-jrc.s: New test for converting
+	jalr/jr to the compact jalrc/jrc instructions.
+	* gas/testsuite/gas/mips/mips16e-jrc.d: New.
+
+2005-10-19  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* gas/s390/zarch-z9-109.s: Add tests for unnormalized hfp multiply
+	and multiply-and-add instructions.
+	* gas/s390/zarch-z9-109.d: Update expected result.
+
+2005-10-17  Richard Earnshaw  <richard.earnshaw@arm.com>
+
+	* gas/arm/copro.d: 'mcrlt' instruction should not be disassembled as
+	'cfsh64lt'.
+
+2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* gas/hppa/basic/basic.exp (do_system): Adjust for removal of lha
+	instructions from system.s.
+	* gas/hppa/basic/system.s (lha): Remove.
+
+2005-10-12  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/forward.[sd]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-10-11  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/cond.s: Add test for resolution of fully resolvable
+	forward references in .if/.endif.
+	* gas/all/cond.d: Rename to:
+	* gas/all/cond.l: New.
+	* gas/all/assign-bad.s: New.
+	* gas/all/assign-ok.s: New.
+	* gas/all/equ-bad.s: New.
+	* gas/all/equ-ok.s: New.
+	* gas/all/equiv1.s: New.
+	* gas/all/equiv2.s: New.
+	* gas/all/eqv-bad.s: New.
+	* gas/all/eqv-ok.s: New.
+	* gas/all/eval.[sd]: New.
+	* gas/all/forward.[sd]: New.
+	* gas/all/redef.[sd]: New.
+	* gas/all/gas.exp: Run new tests, but xfail equiv1 (PR/1387).
+
+2005-10-10  Nick Clifton  <nickc@redhat.com>
+
+	* gas/sh/reg-prefix.s: Use mov.l instruction in preference to
+	movli.l.
+	* gas/sh/reg-prefix.d: Force little endian assembly.
+
+2005-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/eabi_attr_1.s: New test.
+	* gas/arm/eabi_attr_1.d: New test.
+	* gas/arm/arm7t.d: Only disassemble code sections.
+	* gas/arm/bignum1.d: Ignore Arm object attribute sections.
+	* gas/arm/mapping.d: Ditto.
+	* gas/arm/unwind.d: Ditto.
+	* gas/elf/section0.d: Ditto.
+	* gas/elf/section1.d: Ditto.
+	* gas/elf/elf.exp: Set target_machine for Arm EABI based targets.
+	* gas/elf/section2.e-armeabi: New file.
+
+2005-10-06  Khem Raj  <kraj@mvista.com>
+            NIIBE Yutaka  <gniibe@m17n.org>
+
+	* gas/sh/basic.exp:  Run reg-prefix test.
+	* gas/sh/reg-prefix.s: New
+	* gas/sh/reg-prefix.d: New 
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* gas/bfin: New testsuite for bfin.
+	* gas/all/gas.exp (bfin-*-*): Expected failure for alternate
+	macro syntax.
+
+2005-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/fpa-mem.s: Remove incorrect comments.
+	* gas/arm/fpa-mem.d: Update expected results.
+
+2005-09-29  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/alloc.[sl]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/x86-64-stack.s, gas/i386/x86-64-stack.d,
+	gas/i386/x86-64-stack-suffix.d, gas/i386/x86-64-stack-intel.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/mixed-mode-reloc.s: Enable all insns.
+	* gas/i386/mixed-mode-reloc32.d: Adjust.
+	* gas/i386/mixed-mode-reloc64.d: Adjust.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/reloc64.s: Also test .slong.
+	* gas/i386/reloc64.l: Adjust.
+	* gas/i386/reloc64.d: Adjust.
+
+2005-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/lns/lns.exp (lns-common-1): Don't run on targets without
+	a bare nop insn.
+
+2005-09-20  Richard Henderson  <rth@redhat.com>
+
+	* gas/cris/rd-dw2-1.d, gas/cris/rd-dw2-10.d, gas/cris/rd-dw2-11.d,
+	gas/cris/rd-dw2-12.d, gas/cris/rd-dw2-13.d, gas/cris/rd-dw2-14.d,
+	gas/cris/rd-dw2-15.d, gas/cris/rd-dw2-2.d, gas/cris/rd-dw2-3.d,
+	gas/cris/rd-dw2-4.d, gas/cris/rd-dw2-5.d, gas/cris/rd-dw2-6.d,
+	gas/cris/rd-dw2-7.d, gas/cris/rd-dw2-8.d, gas/cris/rd-dw2-9.d,
+	gas/mips/mips16-dwarf2-n32.d, gas/mips/mips16-dwarf2.d: Add 0x
+	prefix in "Advance PC" lines.
+
+2005-09-08  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arch6zk.d: Rename smi to smc.
+	* gas/arm/arch6zk.s: Ditto.
+	* gas/arm/thumb32.d: Ditto.
+	* gas/arm/thumb32.s: Ditto.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/lns/lns-common-1.d: Don't match header or special opcode numbers.
+	* gas/lns/lns-common-1.s: Update for syntax change.
+	* gas/lns/lns-diag-1.[sl]: Likewise.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/mips/mips16-dwarf2.d: Don't match anything but address and line
+	number increments.  Adjust relocation address.
+	* gas/mips/mips16-dwarf2-n32.d: Likewise.  Add "N32" to test name.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/cris/rd-dw2-1.d: Don't match anything but address and line
+	number increments.
+	* gas/cris/rd-dw2-10.d, gas/cris/rd-dw2-11.d, gas/cris/rd-dw2-12.d,
+	gas/cris/rd-dw2-13.d, gas/cris/rd-dw2-14.d, gas/cris/rd-dw2-15.d,
+	gas/cris/rd-dw2-2.d, gas/cris/rd-dw2-3.d, gas/cris/rd-dw2-4.d,
+	gas/cris/rd-dw2-5.d, gas/cris/rd-dw2-6.d, gas/cris/rd-dw2-7.d,
+	gas/cris/rd-dw2-8.d, gas/cris/rd-dw2-9.d: Likewise.
+
+2005-09-07  Richard Henderson  <rth@redhat.com>
+
+	* gas/lns/lns.exp: New file.
+	* gas/lns/lns-common-1.[sd]: New test.
+	* gas/lns/lns-diag-1.[sl]: New test.
+
+2005-09-06  Chao-ying Fu  <fu@mips.com>
+
+	* gas/mips/mips.exp: Run MT test for mips32r2 only.
+	* gas/mips/mips32-mt.[sdl]: New test.
+
+2005-09-06  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_relax.d: New test.
+	* gas/arm/thumb2_relax.s: New test.
+	* gas/arm/thumb32.d: Adjust expected results to include relaxation.
+	* gas/arm/thumb32.s: Tweak for better coverage of relaxable
+	instructions.  Remove load/store tests.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/arm3-bad.s: New test.
+	* gas/arm/arm3-bad.d: New test.
+	* gas/arm/arm3.s: Avoid illegal instructions.
+	* gas/arm/arm3.d: Ditto.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/vfp-bad_t2.d, gas/arm/vfp-bad_t2.l, arm/vfp-bad_t2.s,
+	gas/arm/vfp1_t2.d, gas/arm/vfp1_t2.s, gas/arm/vfp1xD_t2.d,
+	gas/arm/vfp1xD_t2.s, gas/arm/vfp2_t2.d, gas/arm/vfp2_t2.s): New files.
+
+2005-09-02  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/fpa-mem.d: Test "stfpls".
+	* gas/arm/fpa-mem.s: Ditto.
+
+2005-09-01  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/cris: Adjust all files for testing target
+	cris-axis-linux-gnu.
+
+2005-08-30  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb.d: Change "sub rn, rn, rn" to "subs rn, rn, rn".
+	* gas/arm/thumb32.d: Ditto.
+
+2005-08-26  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intel.s: Adjust.
+	* gas/i386/intelok.s: Add two more insns.
+	* gas/i386/intelok.d: Adjust.
+
+2005-08-26  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intelok.d: Adjust.
+
+2005-08-25  Chao-ying Fu  <fu@mips.com>
+
+	* gas/mips/mips.exp: Run DSP test.
+	* gas/mips/mips32-dsp.[sdl]: New test.
+
+2005-08-22  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/mixed-mode-reloc.s, gas/i386/mixed-mode-reloc32.d,
+	gas/i386/mixed-mode-reloc64.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2005-08-15  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_it.s: Add more instruction variants.
+	* gas/arm/thumb2_it.d: Ditto.
+
+2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* gas/testsuite/gas/s390/s390.exp: Reorganize gas testsuite for s390
+	and add tests for new cpu type z9-109.
+	* gas/testsuite/gas/s390/esa-g5.d: New.
+	* gas/testsuite/gas/s390/esa-g5.s: New.
+	* gas/testsuite/gas/s390/esa-operands.d: New.
+	* gas/testsuite/gas/s390/esa-operands.s: New.
+	* gas/testsuite/gas/s390/esa-reloc.d: New.
+	* gas/testsuite/gas/s390/esa-reloc.s: New.
+	* gas/testsuite/gas/s390/esa-z9-109.d: New.
+	* gas/testsuite/gas/s390/esa-z9-109.s: New.
+	* gas/testsuite/gas/s390/esa-z900.d: New.
+	* gas/testsuite/gas/s390/esa-z900.s: New.
+	* gas/testsuite/gas/s390/esa-z990.d: New.
+	* gas/testsuite/gas/s390/esa-z990.s: New.
+	* gas/testsuite/gas/s390/zarch-operands.d: New.
+	* gas/testsuite/gas/s390/zarch-operands.s: New.
+	* gas/testsuite/gas/s390/zarch-reloc.d: New.
+	* gas/testsuite/gas/s390/zarch-reloc.s: New.
+	* gas/testsuite/gas/s390/zarch-z9-109.d: New.
+	* gas/testsuite/gas/s390/zarch-z9-109.s: New.
+	* gas/testsuite/gas/s390/zarch-z900.d: New.
+	* gas/testsuite/gas/s390/zarch-z900.s: New.
+	* gas/testsuite/gas/s390/zarch-z990.d: New.
+	* gas/testsuite/gas/s390/zarch-z990.s: New.
+	* gas/testsuite/gas/s390/opcode.d: Delete.
+	* gas/testsuite/gas/s390/opcode.s: Delete.
+	* gas/testsuite/gas/s390/opcode64.d: Delete.
+	* gas/testsuite/gas/s390/opcode64.s: Delete.
+	* gas/testsuite/gas/s390/operands.d: Delete.
+	* gas/testsuite/gas/s390/operands.s: Delete.
+	* gas/testsuite/gas/s390/operands64.d: Delete.
+	* gas/testsuite/gas/s390/operands64.s: Delete.
+	* gas/testsuite/gas/s390/reloc.d: Likewise.
+	* gas/testsuite/gas/s390/reloc.s: Likewise.
+	* gas/testsuite/gas/s390/reloc64.d: Likewise.
+	* gas/testsuite/gas/s390/reloc64.s: Likewise.
+
+2005-08-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/all/gas.exp: Remove a29k and m88k support.
+	* gas/m88k/allinsn.d: Delete.
+	* gas/m88k/allinsn.s: Delete.
+	* gas/m88k/init.d: Delete.
+	* gas/m88k/init.s: Delete.
+	* gas/m88k/m88k.exp: Delete.
+	* gas/tic80/add.d: Delete.
+	* gas/tic80/add.lst: Delete.
+	* gas/tic80/add.s: Delete.
+	* gas/tic80/align.d: Delete.
+	* gas/tic80/align.lst: Delete.
+	* gas/tic80/align.s: Delete.
+	* gas/tic80/bitnum.d: Delete.
+	* gas/tic80/bitnum.lst: Delete.
+	* gas/tic80/bitnum.s: Delete.
+	* gas/tic80/ccode.d: Delete.
+	* gas/tic80/ccode.lst: Delete.
+	* gas/tic80/ccode.s: Delete.
+	* gas/tic80/cregops.d: Delete.
+	* gas/tic80/cregops.lst: Delete.
+	* gas/tic80/cregops.s: Delete.
+	* gas/tic80/endmask.d: Delete.
+	* gas/tic80/endmask.lst: Delete.
+	* gas/tic80/endmask.s: Delete.
+	* gas/tic80/float.d: Delete.
+	* gas/tic80/float.lst: Delete.
+	* gas/tic80/float.s: Delete.
+	* gas/tic80/regops.d: Delete.
+	* gas/tic80/regops.lst: Delete.
+	* gas/tic80/regops.s: Delete.
+	* gas/tic80/regops2.d: Delete.
+	* gas/tic80/regops2.lst: Delete.
+	* gas/tic80/regops2.s: Delete.
+	* gas/tic80/regops3.d: Delete.
+	* gas/tic80/regops3.lst: Delete.
+	* gas/tic80/regops3.s: Delete.
+	* gas/tic80/regops4.d: Delete.
+	* gas/tic80/regops4.lst: Delete.
+	* gas/tic80/regops4.s: Delete.
+	* gas/tic80/relocs1.c: Delete.
+	* gas/tic80/relocs1.d: Delete.
+	* gas/tic80/relocs1.lst: Delete.
+	* gas/tic80/relocs1.s: Delete.
+	* gas/tic80/relocs1b.d: Delete.
+	* gas/tic80/relocs2.c: Delete.
+	* gas/tic80/relocs2.d: Delete.
+	* gas/tic80/relocs2.lst: Delete.
+	* gas/tic80/relocs2.s: Delete.
+	* gas/tic80/relocs2b.d: Delete.
+	* gas/tic80/tic80.exp: Delete.
+
+2005-08-05  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* gas/hppa/reloc/reloc.exp (do_function_reloc_bug): Add "L%" to regexp.
+
+2005-08-05  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Use correct conditional suffixes inside IT
+	blocks.
+	* gas/arm/thumb2_it.d, gas/arm/thumb2_it.s: New test.
+
+2005-08-05  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Update ldm/stm dests.
+	* gas/arm/thumb32.s: Ditto.
+
+2005-08-03  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/iwmmxt-bad2.s: New file: Check for error messages about
+	erroneous offsets in iwmmxt instructions.  Cannot be part of
+	iwmmxt-bad.s because the errors there stop the assembler before it
+	gets to check the offsets in instructions.
+	* gas/arm/iwmmxt-bad2.d: New file.
+	* gas/arm/iwmmxt-bad2.l: New file: Expected error messages.
+
+2005-08-02  Khem Raj  <kraj@mvista.com>
+
+	* gas/arm/iwmmxt.s: Change the offset values of the WLDRD, WSTRD
+	and WSTRW instructions to be larger than +/-255.
+	* gas/arm/iwmmxt.d: Fix the expected results for these
+	instructions.
+
+2005-07-29  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.d: Fix expected output for writeback addressing
+	modes.  Add single high reg push/pop test.
+	* gas/asm/thumb32.s: Add single high reg push/pop test.
+
+2005-07-29  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Add tests for addw, subw, tbb and tbh.
+	* gas/arm/thumb32.d: Ditto.
+
+2005-07-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/unwind-bad.l: Uncomment patterns matching new warnings.
+	* gas/ia64/unwind-ok.d: Correct expectations.
+
+2005-07-26  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/immed32.[sd]: New.
+	* gas/i386/immed64.[sd]: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2005-07-21  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb32.s: Add tests for [pc, #imm] addressing modes.
+	* gas/arm/thumb32.d: Ditto.
+
+2005-07-20  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+	* gas/m32r/rel32.exp: New file. 
+	* gas/m32r/rel32.s: New file. 
+	* gas/m32r/rel32.d: New file. 
+	* gas/m32r/rel32-pic.s: New file. 
+	* gas/m32r/rel32-pic.d: New file. 
+	* gas/m32r/rel32-err.s: New file. 
+	* gas/m32r/error.exp: Added rel32-err. 
+
+2005-07-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add suffix.
+
+	* gas/i386/suffix.d: New file.
+	* gas/i386/suffix.s: Likewise.
+
+2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* gas/hppa/basic/fp_comp.s: Add level 1.1 directive.
+	* gas/hppa/basic/special.s, gas/hppa/basic/system.s: Likewise.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/reloc32.[sdl]: New.
+	* gas/i386/reloc64.[sdl]: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Add vmx and x86-64-vmx.
+
+	* gas/i386/vmx.d: New file.
+	* gas/i386/vmx.s: Likewise.
+	* gas/i386/x86-64-vmx.d: Likewise.
+	* gas/i386/x86-64-vmx.s: Likewise.
+
+2005-07-14  Nick Clifton  <nickc@redhat.com>
+
+	PR 1063
+	* gas/crx/gas-segfault.d: New file.
+	* gas/crx/gas-segfault.s: New file.
+
+2005-07-12  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* gas/mmix/relax1-n.d, gas/mmix/relax1-rn.d: Avoid "# FIXME: "
+	first on a line, adjusting for testsuite framework change.
+
+2005-07-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386/x86_64.s: Add absolute siged 32bit addressing tests for
+	mov.
+	* i386/x86_64.d: Updated.
+
+2005-07-08  Hans-Peter Nilsson  <hp@axis.com>
+
+	PR gas/1049
+	* gas/cris/rd-pic-2.d, gas/cris/rd-pic-2.s: New test.
+	* gas/cris/rd-abs32-1.d: Tweak for not emitting reloc-related
+	garbage for global symbols.
+
+2005-07-07  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/vfp1xD.d: Adjust expected fadds disassemblies now that
+	the dissassembler has been fixed.
+
+2005-05-07  Paul Brook  <paul@codesourcery.com>
+
+	* gas/ppc/altivec.d: Match all powerpc target vecs.
+	* gas/ppc/booke.d: Ditto.
+	* gas/ppc/e500.d: Ditto.
+
+2005-07-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* gas/ms1: New directory.
+	* gas/ms1/allinsn.d: New.
+	* gas/ms1/allinsn.s: New.
+	* gas/ms1/badinsn.s: New.
+	* gas/ms1/badinsn1.s: New.
+	* gas/ms1/badoffsethigh.s: New.
+	* gas/ms1/badoffsetlow.s: New.
+	* gas/ms1/badorder.s: New.
+	* gas/ms1/badreg.s: New.
+	* gas/ms1/badsignedimmhigh.s: New.
+	* gas/ms1/badsignedimmlow.s: New.
+	* gas/ms1/badsyntax.s: New.
+	* gas/ms1/badsyntax1.s: New.
+	* gas/ms1/badunsignedimmhigh.s: New.
+	* gas/ms1/badunsignedimmlow.s: New.
+	* gas/ms1/errors.exp: New.
+	* gas/ms1/ldst.s: New.
+	* gas/ms1/misc.d: New.
+	* gas/ms1/misc.s: New.
+	* gas/ms1/ms1-16-003.d: New.
+	* gas/ms1/ms1-16-003.s: New.
+	* gas/ms1/ms1.exp: New.
+	* gas/ms1/msys.d: New.
+	* gas/ms1/msys.s: New.
+	* gas/ms1/relocs.d: New.
+	* gas/ms1/relocs.exp: New.
+	* testsuite/gas/ms1/relocs1.s: New.
+	* testsuite/gas/ms1/relocs2.s: New.
+
+2005-07-05  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/svme.d: New.
+	* gas/i386/svme.s: New.
+	* gas/i386/svme64.d: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2005-07-04  Zack Weinberg  <zack@codesourcery.com>
+
+	* lib/gas-defs.exp (run_dump_tests): New proc.
+	(run_dump_test): Add support for new options: target, not-target,
+	skip, not-skip, error-output.  Document stderr.  Tidy a
+	little.
+	(slurp_options): If a line doesn't match the option regexp, but
+	does begin with #, ignore it; don't stop parsing options.
+	* gas/arm/arm.exp: Remove most code.  Use run_dump_tests.
+
+	* gas/arm/archv6t2-bad.d, gas/arm/armv1.d, gas/arm/iwmmxt-bad.d
+	* gas/arm/r15-bad.d, gas/arm/req.d, gas/arm/t16-bad.d
+	* gas/arm/undefined.d, gas/arm/undefined_coff.d, gas/arm/vfp-bad.d:
+	New files.
+	* gas/arm/bignum1.d, gas/arm/mapping.d, gas/arm/pic.d:
+	Only run on ELF targets.
+	* gas/arm/tls.d, gas/arm/unwind.d: Only run on ELF targets.
+	Skip on VxWorks.
+	* gas/arm/tls_vxworks.d, gas/arm/unwind_vxworks.d: New files.
+	* gas/arm/thumb.d, gas/arm/thumb32.d: Don't run on aout or pe.
+	* gas/arm/le-fpconst.d: Only run on *-*-pe.
+	* gas/arm/inst.d: Skip on WinCE.
+	* gas/arm/wince_inst.d: Skip unless WinCE.
+	* gas/arm/el_segundo.d: Mark up for actual use; adjust
+	expectations.
+	* gas/arm/el_segundo.s: Remove irrelevant junk.  Add padding
+	for a.out's sake.
+
+2005-07-01  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/group-2.s: Use register as second operand of .prologue.
+	* gas/ia64/unwind-err.s: Add check for .vframesp.
+	* gas/ia64/unwind-err.l: Adjust.
+	* gas/ia64/strange.[sd]: New.
+	* gas/ia64/unwind-bad.[sl]: New.
+	* gas/ia64/unwind-ok.[sd]: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-06-30  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/arm.exp: Don't special case ldconst, arm7t, or copro
+	for *-wince-*.
+	* gas/arm/wince_arm7t.d, gas/arm/wince_copro.d
+	* gas/arm/wince_ldconst.d: Delete.
+
+2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 1013
+	* i386/x86_64.s: Add absolute 64bit addressing tests for mov.
+	* i386/x86_64.d: Updated.
+
+2005-06-17  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/x86-64-pcrel.s: Add insn requiring 64-bit pc-relative
+	relocation. Add insns for all widths of non-pc-relative relocations.
+	* gas/i386/x86-64-pcrel.d: Adjust.
+
+2005-06-13  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/thumb.s: Only branch to labels defined in this file.
+	* gas/arm/thumb.d, gas/arm/thumb32.d: Adjust expected output.
+
+2005-06-01  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/ldstla-32-1.l: Update to handle leading zeroes.
+	* gas/mips/ldstla-32-mips3-1.l: Likewise.
+
+2005-05-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/proc.l: Adjust.
+
+2005-05-25  Steve Ellcey  <sje@cup.hp.com>
+
+	* gas/ia64/global.d: Change --sym to --syms.
+
+2005-05-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/group-1.d: Updated.
+	* gas/ia64/group-2.d: Likewise.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/radix.s: New.
+	* gas/ia64/radix.l: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-05-25  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intelok.d: Account for 32-bit displacements being shown
+	in hex.
+
+2005-05-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/elf/group0b.d: Updated.
+	* gas/elf/group1b.d: Likewise.
+
+2005-05-19  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/reloc-uw.s: New.
+	* gas/ia64/reloc-uw.d: New.
+	* gas/ia64/reloc-uw-ilp32.d: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-05-18  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/altmacro.s: Parenthesize operand of %.
+
+2005-05-17  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/arm.exp: Convert all existing "gas_test" tests to
+	"run_dump_test" tests.  Run more tests unconditionally.  Run new tests.
+	* gas/arm/arch4t.s, gas/arm/arch6zk.s, gas/arm/arm3.s, gas/arm/arm6.s
+	* gas/arm/arm7dm.s, gas/arm/bignum1.s, gas/arm/float.s
+	* gas/arm/immed.s, gas/arm/iwmmxt.s, gas/arm/offset.s, gas/arm/thumb.s:
+	Adjust to work as a dump test.
+	* gas/arm/arch4t.d, gas/arm/arch6zk.d, gas/arm/arm3.d, gas/arm/arm6.d
+	* gas/arm/arm7dm.d, gas/arm/bignum1.d, gas/arm/float.d
+	* gas/arm/immed.d, gas/arm/iwmmxt.d, gas/arm/offset.d, gas/arm/thumb.d:
+	New files.
+
+	* gas/arm/armv1-bad.l, gas/arm/armv1-bad.s: Remove tests for
+	diagnostics that don't happen in the first pass anymore.
+
+	* gas/arm/iwmmxt-bad.l, gas/arm/r15-bad.l, gas/arm/req.l
+	* gas/arm/vfp-bad.l:
+	Update expected diagnostics.
+	* gas/arm/pic.d: Update expected reloc name.
+	* gas/arm/thumbv6.d: CPY no longer appears in disassembly.
+	* gas/arm/r15-bad.s: Avoid two-argument mul.
+	* gas/arm/req.s: Adjust comments.
+	* gas/arm/maverick.d, gas/arm/maverick.s: Avoid inappropriate
+	use of PC.
+
+	* gas/arm/macro-1.d, gas/arm/macro1.s
+	* gas/arm/t16-bad.l, gas/arm/t16-bad.s
+	* gas/arm/tcompat.d, gas/arm/tcompat.s
+	* gas/arm/tcompat2.d, gas/arm/tcompat2.s
+	* gas/arm/thumb32.d, gas/arm/thumb32.s
+	New test pair.
+
+2005-05-17  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/mmix/err-byte1.s: Adjust expected error text on line 10.
+
+2005-05-17  Nick Clifton  <nickc@redhat.com>
+
+	* gas/v850/split-lo16.s: Add test for a lo() pseudo reloc
+	corrupting an ld.w instruction.
+	* gas/v850/split-lo16.d: Add expected, correct (ie not corrupt)
+	output.
+
+2005-05-10  Michael Matz  <matz@suse.de>
+
+	* gas/hppa/parse/block1.s: Use official limit (0x3fffffff) for
+	.block.
+
+2005-05-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* gas/mmix/relax2.s: Drop ":" off label definitions.
+
+2005-05-09  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/tlsd.[sd]: Adjust to not assume zero displacement will
+	actually be present in memory addressing.
+	* gas/i386/tlspic.[sd]: Likewise.
+
+2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 940
+	* gas/ia64/group-2.d: New.
+	* gas/ia64/group-2.s: New.
+
+	* gas/ia64/ia64.exp: Add "group-2".
+
+2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 843
+	* gas/i386/i386.exp: Add x86-64-branch.
+
+	* gas/i386/x86-64-branch.d: New.
+	* gas/i386/x86-64-branch.s: New.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/badarg.s: Add check for bad qualifier specification.
+	* gas/macros/badarg.l: Adjust.
+	* gas/macros/vararg.[sd]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/all/cond.s: Also test .ifb/.ifnb.
+	* gas/all/cond.d: Adjust.
+
+2005-05-06  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/dot.s: Don't use pseudo-ops in first column.
+	* gas/macros/dot.l: Match broader range of possible outputs.
+	* gas/macros/purge.l: Likewise.
+	* gas/macros/purge.s: Start generated macro names with an underscore.
+
+2005-05-05  Paul Brook  <paul@codesourcery.com>
+
+	* gas/i386/i386.exp: Don't run divide test on vxworks.
+
+2005-05-05  Nick Clifton  <nickc@redhat.com>
+
+	* Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	gas/all/itbl-test.c, gas/all/test-example.c, gas/all/test-gen.c,
+	gas/arm/maverick.c, gas/cris/cris.exp, gas/hppa/basic/basic.exp,
+	gas/hppa/parse/parse.exp, gas/hppa/reloc/reloc.exp,
+	gas/hppa/unsorted/unsorted.exp, gas/m88k/m88k.exp,
+	gas/mmix/mmix-err.exp, gas/mmix/mmix-list.exp, gas/mmix/mmix.exp,
+	gas/mn10200/basic.exp, gas/mn10300/am33-2.c,
+	gas/mn10300/basic.exp, gas/pdp11/opcode.s, gas/ppc/aix.exp,
+	gas/sh/basic.exp, gas/sh/err.exp, gas/sh/arch/arch.exp,
+	gas/sh/sh64/sh64.exp, gas/v850/basic.exp, lib/gas-defs.exp
+
+2005-05-05  Mike Frysinger  <vapier@gentoo.org>
+
+	* gas/sh/basic.exp: Replace linux-gnu with linux-* to allow for
+	versions of Linux which do not use glibc.
+	* gas/vax/vax.exp: Likewise.
+
+2005-05-05  Paul Brook  <paul@codesourcery.com>
+
+	* lib/gas-defs.exp (regexp_diff): Pass test if last line is "#...".
+
+2005-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/all/assign.s: Make `x' and `y' global.
+
+2005-04-25  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/badarg.s: Add tests for collisions between/among macro
+	parameters and local symbols.
+	* gas/macros/badarg.l: Adjust.
+
+2005-04-20  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/elf/struct.s: Adjust to not get into alignment issues.
+	* gas/elf/struct.d: Adjust for the above and the test's name.
+
+2005-04-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/padlock.d: Updated.
+
+2005-04-19  Andreas Schwab  <schwab@suse.de>
+
+	* gas/ia64/invalid-ar.l: Adapt to changed error message.
+
+2005-04-18  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/purge.[ls]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2005-04-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/elf/struct.[sd]: New.
+	* gas/elf/elf.exp: Run new test.
+
+2005-04-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/all/assign.s: New.
+	* gas/all/assign.d: New.
+	* gas/all/gas.exp: Run it.
+
+2005-04-13  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* gas/mips/ldstla-32.s: Exclude offsets that are now meant to fail
+	and include more instructions/offsets that are meant to succeed.
+	Use $4 instead $3 to avoid register dependencies.
+	* gas/mips/ldstla-32.d: Update accordingly.
+	* gas/mips/ldstla-32-shared.d: Likewise.
+	* gas/mips/ldstla-32-mips3.d: New test based on the above, except
+	for mips3.
+	* gas/mips/ldstla-32-mips3-shared.d: Similarly, for PIC.
+	* gas/mips/ldstla-32-mips3.s: Source for the new tests.
+	* gas/mips/ldstla-32-1.s: New test for offsets that are meant to
+	fail.
+	* gas/mips/ldstla-32-mips3-1.s: Likewise, for mips3.
+	* gas/mips/ldstla-32-1.l: Stderr output for the new test.
+	* gas/mips/ldstla-32-mips3-1.l: Likewise.
+	* gas/mips/mips.exp: Run the new tests.
+
+2005-04-11  Mark Kettenis  <kettenis@gnu.org>
+
+	* gas/all/gas.exp: Don't run fastcall labels test on
+	i*86-*-openbsd*.
+
+2005-04-11  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/dot.[ls]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2005-04-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/x86-64-pcrel.s: Test R_X86_64_32S.
+	* gas/i386/x86-64-pcrel.d: Updated.
+
+2005-04-01  Jan-Benedict Glaw  <jbglaw@lug-owl.de>
+
+	* gas/vax/flonum.s: New testcase: Encode some flonums.
+	* gas/vax/flonum.d: Expected result of new testcase.
+	* gas/vax/vax.exp: Call the new testcase.
+
+	* gas/vax/elf-rel.d: Call gas with -k. Thanks to Matt Thomas for
+	figuring out.
+	* gas/vax/vax.exp: Run elf-rel.[sd] for NetBSD-ELF and Linux.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/bss.[sd]: New.
+	* gas/i386/i386.exp: Run new test.
+
+2005-04-01  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/x86-64-pcrel.[sd]: New.
+	* gas/i386/i386.exp: Run new test.
+
+2005-03-30  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/mapping.d: Update expected output due to mapping symbols
+	being untyped.
+
+2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/i386/i386.exp: Run segment and inval-seg for i386. Run
+	x86-64-segment and x86-64-inval-seg for x86-64.
+
+	* gas/i386/intel.d: Expect movw for moving between memory and
+	segment register.
+	* gas/i386/naked.d: Likewise.
+	* gas/i386/opcode.d: Likewise.
+	* gas/i386/x86-64-opcode.d: Likewise.
+
+	* gas/i386/opcode.s: Use movw for moving between memory and
+	segment register.
+	* gas/i386/x86-64-opcode.s: Likewise.
+
+	* : Likewise.
+
+	* gas/i386/inval-seg.l: New.
+	* gas/i386/inval-seg.s: New.
+	* gas/i386/segment.l: New.
+	* gas/i386/segment.s: New.
+	* gas/i386/x86-64-inval-seg.l: New.
+	* gas/i386/x86-64-inval-seg.s: New.
+	* gas/i386/x86-64-segment.l: New.
+	* gas/i386/x86-64-segment.s: New.
+
+2005-03-29  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/tls.s, gas/arm/tls.d: New files.
+	* gas/arm/arm.exp: Run TLS test.
+
+2005-03-29  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/unwind.d: Update expected output.
+
+2005-03-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 803
+	* gas/ia64/dv-imply.d: Pass -mtune=itanium1 to as.
+	* gas/ia64/dv-mutex.d : Likewise.
+	* gas/ia64/dv-safe.d: Likewise.
+	* gas/ia64/dv-srlz.d.nop: Likewise.
+	* gas/ia64/ldxmov-1.d: Likewise.
+	* gas/ia64/opc-b.d: Likewise.
+	* gas/ia64/opc-f.d: Likewise.
+	* gas/ia64/opc-i.d: Likewise.
+	* gas/ia64/opc-m.d: Likewise.
+	* gas/ia64/operand-or.d: Likewise.
+	* gas/ia64/pcrel.d: Likewise.
+	* gas/ia64/pseudo.d: Likewise.
+	* gas/ia64/tls.d: Likewise.
+
+2005-03-24  Hans-Peter Nilsson  <hp@axis.com>
+
+	* gas/cris/range-err-1.s: Adjust expected messages for hosts with
+	64-bit longs.
+
+2005-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/elf/section5.s: Don't start directives in first column.
+
+2005-03-21  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/iwmmxt.s: Update instructions that use the "never" value
+	in the conditional field to use "le" instead.  This is so that the
+	disassembler will disassemble them.
+	* gas/arm/iwmmxt.d: Update expected disassemblies.
+
+2005-03-17  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intel.d: Add stderr directive.
+	* gas/i386/intel.e: New.
+	* gas/i386/intel16.d: Add stderr directive. Adjust for changed
+	source.
+	* gas/i386/intel16.e: New.
+	* gas/i386/intel16.s: Add instances of addressing forms with base
+	and index specified in reverse order.
+	* gas/i386/intelbad.l: Adjust for changed source.
+	* gas/i386/intelbad.s: Add more operand forms to check.
+	* gas/i386/intelok.d: Remove -r from objdump options. Add stderr
+	directive. Adjust for changed source.
+	* gas/i386/intelok.e: New.
+	* gas/i386/intelok.s: Define MASM constants byte, word, etc. Add
+	more operand forms to check.
+	* gas/i386/x86_64.d: Add stderr directive.
+	* gas/i386/x86_64.e: New.
+	* gas/i386/x86_64.s: Adjust for parser changes.
+
+2005-03-15  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/archv6t2.d, gas/arm/archv6t2.s: New dump test.
+	* gas/arm/archv6t2-bad.l, gas/arm/archv6t2-bad.l: New errors test.
+	* gas/arm/arm.exp: Run them.
+
+2005-03-14  Eric Christopher  <echristo@redhat.com>
+
+	* gas/cfi/cfi-mips-1.d, gas/cfi/cfi-mips-1.s: New dump test.
+	* gas/cfi/cfi.exp: Run it.
+	* gas/cfi/cfi-common-1.d: Update.
+	* gas/cfi/cfi-common-2.d: Ditto.
+	* gas/cfi/cfi-common-3.d: Ditto.
+	* gas/cfi/cfi-common-4.d: Ditto.
+
+2005-03-12  Zack Weinberg  <zack@codesourcery.com>
+
+	* gas/arm/thumbv6k.d, gas/arm/thumbv6k.s: New dump test.
+	* gas/arm/arm.exp: Run it.
+
+2005-03-10  Aldy Hernandez  <aldyh@redhat.com>
+
+	* gas/ppc/e500.d: Fix encoding of efscfd.
+
+2005-03-10  Jeff Baker  <jbaker@qnx.com>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/ppc/booke.s: Add new m[t,f]sprg testcases.
+	* gas/ppc/booke.d: Likewise.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/vr4130.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/relax-swap1-mips[12].d: Expect the delay slots of
+	bc1f and bc1t to be filled.
+	* gas/mips/branch-misc-3.[sd]: New test.
+	* gas/mips/mips.exp: Run it.
+
+2005-03-09  Ben Elliston  <bje@au.ibm.com>
+
+	* gas/maxq10/maxq10.exp: Remove stray semicolons.
+	* gas/maxq20/maxq20.exp: Likewise.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/no-fit.[ls]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/xdata.[sd], gas/ia64/xdata-ilp32.d: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-03-08  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/pcrel.d: Account for big endian target.
+	* gas/ia64/reloc-bad.s: Enforce 64-bit ABI.
+
+2005-03-08  Hans-Peter Nilsson  <hp@axis.com>
+
+	Adjust testsuite for cris-axis-aout.
+	* gas/cris/rd-bcnst.d, gas/cris/rd-usp-1.d: Adjust regexps for a.out output.
+	* gas/cris/mulbug-err-1.s, gas/cris/rd-arch-1.d,
+	gas/cris/rd-arch-2.d, gas/cris/rd-arch-3.d, gas/cris/rd-break32.d,
+	gas/cris/rd-pcrel2.d, gas/cris/rd-ppv1032.d, gas/cris/rd-ppv32.d,
+	gas/cris/rd-usp-1b.d, gas/cris/v32-err-7.s: Pass --em=criself.
+
+2005-03-04  David Daney  <ddaney@avtrex.com>
+
+	* gas/mips/elf-rel23b.d: Use '__gnu_local_gp' instead of '_gp'
+	for -mno-shared optimization.
+	* gas/mips/elf-rel25a.d: Ditto.
+
+2005-03-04  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/arm.exp: Fix test for running the "undefined" to catch
+	more non-ELF cases.
+	* gas/arm/pic.d: Fix for vxworks target.
+	* gas/arm/basic.d: Likewise.
+	* gas/arm/unwind.d: Likewise.
+
+2005-03-04  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/ldstla-{n32.s, n32.d, n32-shared.d}: Delete.
+	* gas/mips/ldstla-{n64.d, n64-shared.d}: Adjust expected output
+	for loads and stores from constant addresses.
+	* gas/mips/ldstla-{sym32.s, eabi64.d, n64-sym32.d}: New tests.
+	* gas/mips/mips.exp: Run them.
+
+2005-03-03  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/mips.exp: Move tls tests to main $elf block.
+
+2005-03-03  Nick Clifton  <nickc@redhat.com>
+
+	* gas/macros/macros.exp (and.s): Expect this test to fail for the
+	tic4x-coff target because it uses the '&' character as a line
+	separator.
+
+	* gas/sh/basic.exp: Add an sh-hms version of the pcrel test.
+	* gas/sh/pcrel-hms.d: New file.  Adjusted form of pcrel-coff.d for
+	the sh-hms target.
+	* gas/sh/arch/arch.exp: Expect the same failures for sh-hms port
+	as for the sh-coff port.
+
+	* gas/macros/macros.exp (run_list_test): Also expect the msp430
+	port to fail the strings test because it defines
+	ONLY_STANDARD_ESCAPES.
+
+	* gas/arm/arch6zk.s: Add three nop instructions in order to pad
+	the .text section out to a 32-byte boundary as will automatically
+	be done by the arm-aout target.
+	* gas/arm/arch6zk.d: Add expected nop disassemblies.
+
+	* gas/d30v/serial.l: Remove listing lines that are no longer
+	emitted and fix up expected binary encoding.
+	* gas/d30v/serial2.l: Likewise.
+	* gas/d30v/serial2O.l: Likewise.
+
+2005-03-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* gas/arc/extensions.s: Add tests for extcoreregister.
+	* gas/arc/extensions.d: Likewise.
+	* gas/arc/warn.s: Warnings for readonly core registers accessed.
+	* gas/arc/warn.d: Likewise.
+	* gas/arc/arc.exp: Run extensions testcase.
+
+2005-03-03  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/mips/noat-1.d: Add -mips1 to assembler options.
+
+2005-03-03  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* gas/arc/ld.s: Add checks for short immediates with ld.
+	* gas/arc/ld.d: Likewise.
+
+2005-03-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/mips/tls-o32.d, gas/mips/tls-o32.s, gas/mips/tls-ill.l,
+	gas/mips/tls-ill.s: New files.
+	* gas/mips/mips.exp: Run TLS tests.
+
+2005-03-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/ppc/astest.d: Adjust for relocs reduced to section sym.
+	* gas/ppc/astest2.d: Likewise.
+	* gas/ppc/astest2_64.d: Likewise.
+	* ppc/astest64.d: Likewise.
+	* ppc/booke.d: Likewise.
+	* ppc/power4.d: Likewise.
+	* ppc/test1elf32.d: Likewise.
+	* ppc/test1elf64.d: Likewise.
+
+2005-03-02  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/cr-err.[ls]: New.
+	* gas/i386/crx.[ds]: New.
+	* gas/i386/i386.exp: Run new tests.
+
+2005-03-02  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intelok.d: Add -r to objdump options. Adjust expectations.
+	* gas/i386/intelok.s: Add checks for various special memory operands.
+
+2005-03-01  Ramana Radhakrishnan  <ramana.radhakrishnan@codito.com>
+
+	* gas/arc/extensions.s: New file.
+	* gas/arc/extensions.d: New file.
+
+2005-03-01  Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/arm.exp (undefined): Run a COFF variant of this test for
+	COFF based ports.
+	* gas/arm/undefined_coff.s: New file: Variant of undefined.s but
+	with a COFF formated local label name.
+	* gas/arm/undefined_coff.l: New file.  Variant of undefined.l.
+
+2005-03-01  Stig Petter Olsroed  <stigpo@users.sourceforge.net>
+	    Nick Clifton  <nickc@redhat.com>
+
+	* gas/arm/inst.d: Allow for ARM ports which decode the reloc
+	associated with branches and so show the exact symbolic
+	destination address rather than an offset from the start of the
+	section.
+	* gas/arm/pic.d: Likewise.
+
+2005-03-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/m68k/mcf-emac.d: Allow for 64-bit addresses.
+	* gas/m68k/mcf-mac.d: Likewise.
+	* gas/m68k/mcf-mov3q.d: Likewise.
+	* gas/m68k/mode5.d: Likewise.
+
+2005-02-22  Eric Christopher  <echristo@redhat.com>
+
+	* gas/mips/elf-rel10.d: Update for label change.
+
+2005-02-22  Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/mips16-dwarf2.d: Pass -mabi=32.  Include relocation
+	information.
+	* gas/mips/mips16-dwarf2-n32.d: New test to check DWARF2 line
+	information for MIPS16 for the n32 ABI.
+	* gas/mips/mips.exp. Run the new test.
+
+2005-02-22  Eric Christopher  <echristo@redhat.com>
+
+	* gas/mips/elf-rel10.s: Add label for frob.
+
+2005-02-22  Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/mips16-dwarf2.d: New test to check DWARF2 line
+	information for MIPS16.
+	* gas/mips/mips16-dwarf2.s: Source for the new test.
+	* gas/mips/mips.exp: Run the new test.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/d10v/instruction_packing-005.d: Adjust.
+	* gas/d10v/instruction_packing-008.d: Ignore disassembled stabs.
+	* gas/d10v/instruction_packing-009.d: Likewise.
+	* gas/d10v/instruction_packing-010.d: Likewise.
+	* gas/d10v/warning-001.d: Use #warning instead of #error.
+	* gas/d10v/warning-002.d: Likewise.
+	* gas/d10v/warning-003.d: Likewise.
+	* gas/d10v/warning-004.d: Likewise.
+	* gas/d10v/warning-005.d: Likewise.
+	* gas/d10v/warning-006.d: Likewise.
+	* gas/d10v/warning-007.d: Likewise.
+	* gas/d10v/warning-008.d: Likewise.
+	* gas/d10v/warning-009.d: Likewise.
+	* gas/d10v/warning-010.d: Likewise.
+	* gas/d10v/warning-011.d: Likewise.
+	* gas/d10v/warning-012.d: Likewise.
+	* gas/d10v/warning-013.d: Likewise.
+	* gas/d10v/warning-015.d: Likewise.
+	* gas/d10v/warning-016.d: Likewise.
+	* gas/d10v/warning-017.d: Likewise.
+	* gas/d10v/warning-018.d: Likewise.
+	* gas/d10v/warning-019.d: Likewise.
+	* lib/gas-defs.exp (run_dump_test): Don't require a dump program if
+	#warning given.  Rearrange to allow $program to remain unset.
+	Fail the test if warning not found when expected.  Conversely fail
+	the test if assembler errors or warnings given when not expected.
+
+2005-02-18  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
+
+	* gas/mips/noat-1.s, gas/mips/noat-1.d, gas/mips/noat-2.s,
+	gas/mips/noat2.l, gas/mips/noat-3.s, gas/mips/noat-3.l,
+	gas/mips/noat-4.s, gas/mips/noat-4.l, gas/mips/noat-5.s,
+	gas/mips/noat-5.l, gas/mips/noat-6.s, gas/mips/noat-6.l,
+	gas/mips/noat-7.s, gas/mips/noat-7.l: New files, testcases for
+	.set noat in macro expansions.
+	* gas/mips/mips.exp: Run new testcases.
+	* gas/mips/rol-hw.d, gas/mips/rol-hw.l, gas/mips/rol.d,
+	gas/mips/rol.l, gas/mips/rol.s, gas/mips/rol64-hw.d,
+	gas/mips/rol64-hw.l, gas/mips/rol64.d, gas/mips/rol64.l,
+	gas/mips/rol64.s, gas/mips/uld2-eb.d, gas/mips/uld2-el.d,
+	gas/mips/uld2.l, gas/mips/uld2.s, gas/mips/ulh2-eb.d,
+	gas/mips/ulh2-el.d, gas/mips/ulh2.l, gas/mips/ulh2.s,
+	gas/mips/ulw2-eb-ilocks.d, gas/mips/ulw2-eb.d,
+	gas/mips/ulw2-el-ilocks.d, gas/mips/ulw2-el.d, gas/mips/ulw2.l,
+	gas/mips/ulw2.s: Don't try to test .set noat.
+
+2005-02-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/hint.b-err.l: New file.
+	* gas/ia64/hint.b-err.s: Likewise.
+	* gas/ia64/hint.b-warn.l: Likewise.
+	* gas/ia64/hint.b-warn.s: Likewise.
+
+	* gas/ia64/ia64.exp: Run hint.b-err and hint.b-warn.
+
+	* gas/ia64/opc-b.d: Pass -mhint.b=ok to as.
+
+2005-02-17  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/nostkreg.[ds]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-02-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* gas/all/gas.exp (quad): Don't run on i960.
+
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* gas/mips/mips16-hilo.d: New test for the R_MIPS16_HI16 and
+	R_MIPS16_LO16 relocs.
+	* gas/mips/mips16-hilo-n32.d: Likewise, for the n32 ABI.
+	* gas/mips/mips16-hilo.s: Source for the new tests.
+	* gas/mips/mips.exp: Run the new tests.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/pcrel.[ds]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/dv-raw-err.l: Expect specific resource for RAW
+	violation on b0.
+	* gas/ia64/regval.[ls]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/dv-raw-err.s: Don't use r0 or f0 as output operand.
+	* gas/ia64/dv-waw-err.s: Likewise.
+	* gas/ia64/reg-err.[ls]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/reloc.[ds]: New.
+	* gas/ia64/reloc-bad.[ls]: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-02-15  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/operand-or.d: Pass -xnone to assembler.
+
+2005-02-13  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/label.l: Adjust line numbers.
+	* gas/ia64/label.s: Add .explicit.
+	* gas/ia64/nop_x.s: Likewise.
+	* gas/ia64/opc-a.d: Add assembler option -xnone.
+	* gas/ia64/opc-b.d: Likewise.
+	* gas/ia64/opc-f.d: Likewise.
+	* gas/ia64/opc-i.d: Likewise.
+	* gas/ia64/opc-m.d: Likewise.
+	* gas/ia64/opc-x.d: Likewise.
+	* gas/ia64/pseudo.d: Likewise.
+	* gas/ia64/regs.d: Likewise.
+	* gas/ia64/tls.d: Likewise.
+	* gas/ia64/unwind-err.l: Adjust line numbers.
+	* gas/ia64/unwind-err.s: Remove explicit stops.
+
+2005-02-13  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/pound.[ls]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/ia64.exp: Add "operand-or".
+
+	* gas/ia64/operand-or.d: New file.
+	* gas/ia64/operand-or.s: Likewise.
+
+2005-02-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* gas/ia64/ia64.exp: Pass -munwind-check=error for unwind-err
+	and proc.
+
+2005-02-10  Julian Brown  <julian@codesourcery.com>
+
+	* gas/arm/unwind.d: Alter expected output to include dependency on
+	__aeabi_unwind_cpp_pr[01].
+
+2005-02-09  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/i386/intelok.s: Remove comments disabling alternative forms of
+	fbld, fbstp, and fldcw.
+	* gas/i386/intelok.d: Expect two instances of fbld, fbstp, and fldcw.
+
+2005-02-07  Inderpreet Singh <inderpreetb@noida.hcltech.com>
+
+	* gas/maxq10/jump.d: Fixed relative jump offset.
+	* gas/maxq10/call.d: Likewise.
+	* gas/maxq20/jump.d: Likewise.
+	* gas/maxq20/call.d: Likewise.
+
+2005-02-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* lib/gas-defs.exp: Support new directive "warning".
+
+2005-02-02  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/pred-rel.s: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-01-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/mips/elf-rel23.d, gas/mips/elf-rel23a.d: Accept little-endian.
+	* gas/mips/tmipsel16-e.d, gas/mips/tmipsel16-f.d: Accept section
+	symbol names.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/repeat.[ds]: New.
+	* gas/macros/macros.exp: Run new test.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/macros/badarg.[ls]: New.
+	* gas/macros/end.[ls]: New.
+	* gas/macros/redef.[ls]: New.
+	* gas/macros/macros.exp (run_list_test): Copy from elsewhere.
+	Run new tests.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/operands.[ls]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/proc.[ls]: New.
+	* gas/ia64/unwind-err.[ls]: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/bundling.[ds]: New.
+	* gas/ia64/label.[ls]: New.
+	* gas/ia64/last.[ls]: New.
+	* gas/ia64/slot2.[ls]: New.
+	* gas/ia64/ia64.exp: Run new tests.
+
+2005-01-31  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/pseudo.[ds]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-01-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/nop_x.[ds]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-01-27  Jan Beulich  <jbeulich@novell.com>
+
+	* gas/ia64/dv-waw-err.l: Don't expect ar112 move warning to refer to
+	M-unit.
+	* gas/ia64/mov-ar.[ds]: New.
+	* gas/ia64/ia64.exp: Run new test.
+
+2005-01-24  Nick Clifton  <nickc@redhat.com>
+
+	* gas/all/sleb128.d: Do not assume an 8-bit byte.
+	* gas/all/quad.d: Likewise.  Also allow for ports which order
+	bytes within words in other than simple big-endian or
+	little-endian fashions.
+
+2005-01-19  Richard Sandiford  <rsandifo@redhat.com>
+
+	* gas/all/sleb128.[sd]: New test.
+	* gas/all/quad.[sd]: New test.
+	* gas/all/gas.exp: Run them.
+
+2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* gas/sh/arch/arch.exp: Correct the email address.
+	Correct a few comment typos.
+	Add new tests to ensure that the assembler will only accept
+	instructions valid in each architecture and vice-versa.
+	* gas/sh/arch/arch_expected.txt: Update/Correct the test results.
+	* gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
+	* gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
+	* gas/sh/arch/sh2a-nofpu.s: Generate new file.
+	* gas/sh/arch/sh2a-or-sh3e.s: Regenerate.
+	* gas/sh/arch/sh2a-or-sh4.s: Regenerate.
+	* gas/sh/arch/sh2a.s: Generate new file.
+	* gas/sh/arch/sh2e.s: Regenerate.
+	* gas/sh/arch/sh2.s: Regenerate.
+	* gas/sh/arch/sh3-dsp.s: Regenerate.
+	* gas/sh/arch/sh3e.s: Regenerate.
+	* gas/sh/arch/sh3-nommu.s: Regenerate.
+	* gas/sh/arch/sh3.s: Regenerate.
+	* gas/sh/arch/sh4al-dsp.s: Regenerate.
+	* gas/sh/arch/sh4a-nofpu.s: Regenerate.
+	* gas/sh/arch/sh4a.s: Regenerate.
+	* gas/sh/arch/sh4-nofpu.s: Regenerate.
+	* gas/sh/arch/sh4-nommu-nofpu.s: Regenerate.
+	* gas/sh/arch/sh4.s: Regenerate.
+	* gas/sh/arch/sh-dsp.s: Regenerate.
+	* gas/sh/arch/sh.s: Regenerate.
+
+2005-01-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386/i386.exp: Run "sib".
+
+	* gas/i386/sib.d: New file.
+	* gas/i386/sib.s: Likewise.
+
+2005-01-09  Andreas Schwab  <schwab@suse.de>
+
+	* gas/i386/intel16.d: Ignore trailing text with #pass.
+	* gas/i386/intelok.d: Likewise.
+	* gas/i386/prefix.d: Likewise.
+	* gas/i386/sub.d: Likewise.
+	* gas/i386/padlock.d: Likewise.
+	* gas/i386/x86_64.d: Likewise.
+
+2005-01-05  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* gas/elf/elf.exp (section5): Use 0-9 instead of [:digit:].
+
+For older changes see ChangeLog-2004
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/gas/testsuite/gas/all/altmac2.d b/gas/testsuite/gas/all/altmac2.d
new file mode 100644
index 000000000000..59fb32706e9c
--- /dev/null
+++ b/gas/testsuite/gas/all/altmac2.d
@@ -0,0 +1,10 @@
+#as: --alternate
+#objdump: -s -j .data
+#name: alternate macro syntax (escape)
+
+# Test the alternate macro syntax.
+
+.*: .*
+
+Contents of section .data:
+ 0000 3e3c21.*
diff --git a/gas/testsuite/gas/all/altmac2.s b/gas/testsuite/gas/all/altmac2.s
new file mode 100644
index 000000000000..05f79afdd220
--- /dev/null
+++ b/gas/testsuite/gas/all/altmac2.s
@@ -0,0 +1,7 @@
+.macro	m1 str
+	.ascii	"&str"
+.endm
+
+	.data
+
+m1	<!>!<!!>
diff --git a/gas/testsuite/gas/all/altmacro.d b/gas/testsuite/gas/all/altmacro.d
new file mode 100644
index 000000000000..aa72f6d67383
--- /dev/null
+++ b/gas/testsuite/gas/all/altmacro.d
@@ -0,0 +1,11 @@
+#as: --alternate
+#objdump: -s -j .data
+#name: alternate macro syntax
+
+# Test the alternate macro syntax.
+
+.*: .*
+
+Contents of section .data:
+ 0000 01020912 61626331 32332121 3c3e2721 .*
+ 0010 3c3e27.*
diff --git a/gas/testsuite/gas/all/altmacro.s b/gas/testsuite/gas/all/altmacro.s
new file mode 100644
index 000000000000..d2955391dd2e
--- /dev/null
+++ b/gas/testsuite/gas/all/altmacro.s
@@ -0,0 +1,35 @@
+.macro	m1 v1, v2
+	LOCAL l1, l2
+label&v1:
+l1:	.byte	v1
+label&v2:
+l2:	.byte	v2
+.endm
+
+.macro	m2 v1, v2
+	m1 %(v1), %(v2-v1)
+.endm
+
+.macro	m3 str
+	.ascii	&str
+.endm
+
+	.data
+
+m2	1, 3
+m2	9, 27
+
+m3	"abc"
+m3	<"1", "23">
+
+	.noaltmacro
+
+.macro	m4 str
+	.ascii	"&str"
+.endm
+
+m4	"!!<>'"
+
+	.altmacro
+
+m3	"!!<>'"
diff --git a/gas/testsuite/gas/all/assign-bad.s b/gas/testsuite/gas/all/assign-bad.s
new file mode 100644
index 000000000000..3c7a2d7c9fa9
--- /dev/null
+++ b/gas/testsuite/gas/all/assign-bad.s
@@ -0,0 +1,2 @@
+ yyy == 3
+ yyy == 4
diff --git a/gas/testsuite/gas/all/assign-ok.s b/gas/testsuite/gas/all/assign-ok.s
new file mode 100644
index 000000000000..fb8e06fe83d8
--- /dev/null
+++ b/gas/testsuite/gas/all/assign-ok.s
@@ -0,0 +1,3 @@
+ xxx = 1
+ xxx = 2
+ yyy == 3
diff --git a/gas/testsuite/gas/all/assign.d b/gas/testsuite/gas/all/assign.d
new file mode 100644
index 000000000000..fce74661594a
--- /dev/null
+++ b/gas/testsuite/gas/all/assign.d
@@ -0,0 +1,6 @@
+#objdump : -r
+#name : assignment tests
+
+#...
+.*zzz.*
+.*zzz.*
diff --git a/gas/testsuite/gas/all/assign.s b/gas/testsuite/gas/all/assign.s
new file mode 100644
index 000000000000..5f94392dc9ac
--- /dev/null
+++ b/gas/testsuite/gas/all/assign.s
@@ -0,0 +1,9 @@
+ .global x
+ x = zzz
+ x = x+1
+ .long x
+
+ .global y
+ y = 1
+ y = y+zzz
+ .long y
diff --git a/gas/testsuite/gas/all/cofftag.s b/gas/testsuite/gas/all/cofftag.s
index 8156599b1294..814d3edeeda0 100644
--- a/gas/testsuite/gas/all/cofftag.s
+++ b/gas/testsuite/gas/all/cofftag.s
@@ -6,6 +6,9 @@
 	};
 	 
 	enum token what= operator;
+
+   Type numbers have been converted to decimal to make this test pass on
+   ports having NUMBERS_WITH_SUFFIX.
  */
 
 	.file	"foo.c"
@@ -18,18 +21,18 @@ _token:
 .text
 	.def	_token
 	.scl	15
-	.type	012
+	.type	10
 	.size	4
 	.endef
 	.def	_operator
 	.val	0
 	.scl	16
-	.type	013
+	.type	11
 	.endef
 	.def	_flags
 	.val	1
 	.scl	16
-	.type	013
+	.type	11
 	.endef
 	.def	.eos
 	.val	4
@@ -46,12 +49,12 @@ _what:
 	.def	_token
 	.val	_token
 	.scl	2
-	.type	02
+	.type	2
 	.endef
 	.def	_what
 	.val	_what
 	.scl	2
 	.tag	_token
 	.size	4
-	.type	012
+	.type	10
 	.endef
diff --git a/gas/testsuite/gas/all/cond.d b/gas/testsuite/gas/all/cond.d
deleted file mode 100644
index 4d0da366f7f8..000000000000
--- a/gas/testsuite/gas/all/cond.d
+++ /dev/null
@@ -1,30 +0,0 @@
-# This should match the output of gas -alc cond.s.
-
-.*cond.s.*
-
-
-   1[ 	]+.if	0
-   8[ 	]+.else
-   9[ 	]+.if	1
-  10[ 	]+.endc
-  11 0000 0[02] ?00 ?00 ?0[02][ 	]+.long[ 	]+2
-  12[ 	]+.if	0
-  14[ 	]+.else
-  15 0004 0[04] ?00 ?00 ?0[04][ 	]+.long[ 	]+4
-  16[ 	]+.endc
-  17[ 	]+.endc
-  18[ 	]+
-  19[ 	]+.if	0
-  21[ 	]+.elseif	1
-  22[ 	]+.if	0
-  24[ 	]+.elseif	1
-  25 0008 0[07] ?00 ?00 ?0[07][ 	]+.long[ 	]+7
-  26[ 	]+.endif
-  27[ 	]+.elseif	1
-  29[ 	]+.else
-  31[ 	]+.endif
-  32 000c 00 ?00 ?00 ?00[ 	]+.p2align 5,0
-  32[ 	]+00 ?00 ?00 ?00 
-  32[ 	]+00 ?00 ?00 ?00 
-  32[ 	]+00 ?00 ?00 ?00 
-  32[ 	]+00 ?00 ?00 ?00 
diff --git a/gas/testsuite/gas/all/cond.l b/gas/testsuite/gas/all/cond.l
new file mode 100644
index 000000000000..36f006644400
--- /dev/null
+++ b/gas/testsuite/gas/all/cond.l
@@ -0,0 +1,71 @@
+# This should match the output of gas -alc cond.s.
+
+.*cond.s.*
+
+
+   1[ 	]+.if	0
+   8[ 	]+.else
+   9[ 	]+.if	1
+  10[ 	]+.endc
+  11 0000 0[02] ?00 ?00 ?0[02][ 	]+.long[ 	]+2
+  12[ 	]+.if	0
+  14[ 	]+.else
+  15 0004 0[04] ?00 ?00 ?0[04][ 	]+.long[ 	]+4
+  16[ 	]+.endc
+  17[ 	]+.endc
+  18[ 	]+
+  19[ 	]+.if	0
+  21[ 	]+.elseif	1
+  22[ 	]+.if	0
+  24[ 	]+.elseif	1
+  25 0008 0[07] ?00 ?00 ?0[07][ 	]+.long[ 	]+7
+  26[ 	]+.endif
+  27[ 	]+.elseif	1
+  29[ 	]+.else
+  31[ 	]+.endif
+[ 	]*[1-9][0-9]*[ 	]+
+[ 	]*[1-9][0-9]*[ 	]+\.comm[ 	]+c,[ 	]*1[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.ifndef[ 	]+c[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+x[ 	]*<>[ 	]*x[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.equiv[ 	]+y,[ 	]*x[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.ifndef[ 	]+y[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+x[ 	]*<>[ 	]*y[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.equiv[ 	]+z,[ 	]*x[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+y[ 	]*<>[ 	]*z[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.equiv[ 	]+a,[ 	]*y[ 	]*\+[ 	]*1[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.equiv[ 	]+b,[ 	]*z[ 	]*-[ 	]*1[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+a[ 	]*==[ 	]*x[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+a[ 	]*-[ 	]*1[ 	]*<>[ 	]*x[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+a[ 	]*<>[ 	]*b[ 	]*\+[ 	]*2[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+a[ 	]*-[ 	]*b[ 	]*<>[ 	]*2[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.equiv[ 	]+x,[ 	]*0[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.if[ 	]+y[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.elseif[ 	]+y[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+\.endif[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+
+[ 	]*[1-9][0-9]*[ 	]+\.macro[ 	]+m[ 	]+x,[ 	]*y[ 	]*
+#...
+[ 	]*[1-9][0-9]*[ 	]+\.endm[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+[0-9a-f]+[048c] FF ?FF ?FF ?FF[ 	]+m[ 	]+,[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+FF ?FF ?FF ?FF[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+[0-9a-f]+[048c] FF ?FF ?FF ?FF[ 	]+m[ 	]+,[ 	]*10[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+0[0A] ?00 ?00 ?0[0A][ 	]*
+[ 	]*[1-9][0-9]*[ 	]+[0-9a-f]+[048c] 0[0B] ?00 ?00 ?0[0B][ 	]+m[ 	]+11,[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+FF ?FF ?FF ?FF[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+[0-9a-f]+[048c] 0[0C] ?00 ?00 ?0[0C][ 	]+m[ 	]+12,[ 	]*13[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+0[0D] ?00 ?00 ?0[0D][ 	]*
+[ 	]*[1-9][0-9]*[ 	]+
+[ 	]*[1-9][0-9]*[ 	]+.*\.p2align 5,0
+#pass
diff --git a/gas/testsuite/gas/all/cond.s b/gas/testsuite/gas/all/cond.s
index ba4bd6ca612a..164e055b12bf 100644
--- a/gas/testsuite/gas/all/cond.s
+++ b/gas/testsuite/gas/all/cond.s
@@ -29,4 +29,64 @@
 	.else
 	.long	9
 	.endif
+
+	.comm	c, 1
+	.ifndef c
+	.err
+	.endif
+
+	.if	x <> x
+	.err
+	.endif
+	.equiv	y, x
+	.ifndef	y
+	.err
+	.endif
+	.if	x <> y
+	.err
+	.endif
+	.equiv	z, x
+	.if	y <> z
+	.err
+	.endif
+
+	.equiv	a, y + 1
+	.equiv	b, z - 1
+	.if	a == x
+	.err
+	.endif
+	.if	a - 1 <> x
+	.err
+	.endif
+	.if	a <> b + 2
+	.err
+	.endif
+	.if	a - b <> 2
+	.err
+	.endif
+
+	.equiv	x, 0
+	.if	y
+	.err
+	.elseif	y
+	.err
+	.endif
+
+	.macro	m x, y
+	.ifb \x
+	.long	-1
+	.else
+	.long	\x
+	.endif
+	.ifnb \y
+	.long	\y
+	.else
+	.long	-1
+	.endif
+	.endm
+	m	,
+	m	, 10
+	m	11,
+	m	12, 13
+
 	.p2align 5,0
diff --git a/gas/testsuite/gas/all/equ-bad.s b/gas/testsuite/gas/all/equ-bad.s
new file mode 100644
index 000000000000..4e3f9310e13f
--- /dev/null
+++ b/gas/testsuite/gas/all/equ-bad.s
@@ -0,0 +1,2 @@
+ .equ x, 1
+ .eqv x, 2
diff --git a/gas/testsuite/gas/all/equ-ok.s b/gas/testsuite/gas/all/equ-ok.s
new file mode 100644
index 000000000000..c620e9708416
--- /dev/null
+++ b/gas/testsuite/gas/all/equ-ok.s
@@ -0,0 +1,2 @@
+ .equ x, 1
+ .equ x, 2
diff --git a/gas/testsuite/gas/all/equiv1.s b/gas/testsuite/gas/all/equiv1.s
new file mode 100644
index 000000000000..cd59bda1d036
--- /dev/null
+++ b/gas/testsuite/gas/all/equiv1.s
@@ -0,0 +1,5 @@
+;# Re-definition of an already .equiv-ed symbol (to another symbol).
+;# The assembler should reject this.
+ .equiv x, y
+ .equiv y, 1
+ .equiv x, 0
diff --git a/gas/testsuite/gas/all/equiv2.s b/gas/testsuite/gas/all/equiv2.s
new file mode 100644
index 000000000000..c533af7b21c3
--- /dev/null
+++ b/gas/testsuite/gas/all/equiv2.s
@@ -0,0 +1,6 @@
+;# Re-definition of an already .equiv-ed symbol (to an expression).
+;# The assembler should reject this.
+ .equiv x, y-z
+ .equiv y, 1
+ .equiv z, 1
+ .equiv x, 1
diff --git a/gas/testsuite/gas/all/eqv-bad.s b/gas/testsuite/gas/all/eqv-bad.s
new file mode 100644
index 000000000000..66172b3f5f6e
--- /dev/null
+++ b/gas/testsuite/gas/all/eqv-bad.s
@@ -0,0 +1,2 @@
+ .eqv x, 1
+ .eqv x, 2
diff --git a/gas/testsuite/gas/all/eqv-ok.s b/gas/testsuite/gas/all/eqv-ok.s
new file mode 100644
index 000000000000..2fe13d5d4f89
--- /dev/null
+++ b/gas/testsuite/gas/all/eqv-ok.s
@@ -0,0 +1 @@
+ .eqv x, 1
diff --git a/gas/testsuite/gas/all/err-1.s b/gas/testsuite/gas/all/err-1.s
new file mode 100644
index 000000000000..68fbad548908
--- /dev/null
+++ b/gas/testsuite/gas/all/err-1.s
@@ -0,0 +1,7 @@
+;# Test .error directive.
+;# { dg-do assemble }
+ .error "an error message"	;# { dg-error "Error: an error message" }
+ .error an error message	;# { dg-error "Error: .error argument must be a string" }
+ .error				;# { dg-error "Error: .error directive invoked in source file" }
+ .error ".error directive invoked in source file" ;# { dg-error "Error: .error directive invoked in source file" }
+ .error ""			;# { dg-error "Error: " }
diff --git a/gas/testsuite/gas/all/eval.d b/gas/testsuite/gas/all/eval.d
new file mode 100644
index 000000000000..9a7e9e88fa19
--- /dev/null
+++ b/gas/testsuite/gas/all/eval.d
@@ -0,0 +1,8 @@
+#objdump: -s -j .data
+#name: evaluation of simple expressions
+
+.*: .*
+
+Contents of section .data:
+ 0000 01010101 010101.. ........ ........  ................
+#pass
diff --git a/gas/testsuite/gas/all/eval.s b/gas/testsuite/gas/all/eval.s
new file mode 100644
index 000000000000..14efe94c7fe4
--- /dev/null
+++ b/gas/testsuite/gas/all/eval.s
@@ -0,0 +1,48 @@
+.equ zero, 0
+.equ one, 1
+.equ two, 2
+
+
+ .data
+
+ .if two > one
+   .byte one
+ .else
+   .byte two
+ .endif
+
+ .if one == one
+   .byte one
+  .else
+    .byte two
+  .endif
+
+  .if one < two
+    .byte one
+  .else
+    .byte two
+  .endif
+
+  .if one <> two
+    .byte one
+  .else
+    .byte two
+  .endif
+
+  .if one != two
+    .byte one
+  .else
+    .byte two
+  .endif
+
+  .if one <= two
+    .byte one
+  .else
+    .byte two
+  .endif
+
+  .if two >= one
+    .byte one
+  .else
+    .byte two
+  .endif
diff --git a/gas/testsuite/gas/all/excl.s b/gas/testsuite/gas/all/excl.s
new file mode 100644
index 000000000000..cf84a95981ce
--- /dev/null
+++ b/gas/testsuite/gas/all/excl.s
@@ -0,0 +1 @@
+.equ	a,!0
diff --git a/gas/testsuite/gas/all/forward.d b/gas/testsuite/gas/all/forward.d
new file mode 100644
index 000000000000..8e45201c2299
--- /dev/null
+++ b/gas/testsuite/gas/all/forward.d
@@ -0,0 +1,8 @@
+#objdump: -s -j .data
+#name: forward references
+
+.*: .*
+
+Contents of section .data:
+ 0000 01020304 ff0203fc 01020304 ff0203fc  ................
+#pass
diff --git a/gas/testsuite/gas/all/forward.s b/gas/testsuite/gas/all/forward.s
new file mode 100644
index 000000000000..d51103ce9da2
--- /dev/null
+++ b/gas/testsuite/gas/all/forward.s
@@ -0,0 +1,44 @@
+ .equiv two, 2*one
+ .equiv minus_one, -one
+ .equ one, 1
+ .equiv three, 3*one
+ .eqv four, 4*one
+
+ .data
+
+ .if two > one
+  .byte one
+  .byte two
+ .endif
+	
+ .if four > one
+  .byte three
+  .byte four
+ .endif
+
+ .equ one, -1
+ .byte one
+ .byte two
+	
+ .if four < one
+  .byte three
+  .byte four
+ .endif
+
+ .equ one, -minus_one
+ .byte one
+ .byte two
+	
+ .if four > one
+  .byte three
+  .byte four
+ .endif
+
+ .equ one, minus_one
+ .byte one
+ .byte two
+
+ .if four < one
+  .byte three
+  .byte four
+ .endif
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index 31cfa4eabe4d..928dd88348e2 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -23,8 +23,9 @@ if { [istarget hppa*-*-*] || [istarget *c54x*-*-*] } then {
     gas_test "p1480.s" "" "-a>" "simplifiable double subtraction"
 }
 
-# No floating point support in assembly code for CRIS.
-if ![istarget cris-*-*] then {
+# No floating point support in assembly code for CRIS and Z80.
+if { ![istarget cris-*-*] && ![istarget crisv32-*-*] 
+     && ![istarget z80-*-*] } then {
     gas_test "float.s" ""   "" "simple FP constants"
 }
 
@@ -34,6 +35,66 @@ if ![istarget hppa*-*-*] then {
     gas_test_error "diff1.s" "" "difference of two undefined symbols"
 }
 
+gas_test_error "equiv1.s" "" ".equiv for symbol already set to another one"
+gas_test_error "equiv2.s" "" ".equiv for symbol already set to an expression"
+
+# .equ works differently on some targets.
+case $target_triplet in {
+    { hppa*-*-* } { }
+    { *c54x*-*-* } { }
+    default {
+	gas_test "equ-ok.s" "" "" ".equ for symbol already set"
+	gas_test_error "equ-bad.s" "" ".equ for symbol already set through .eqv"
+    }
+}
+
+gas_test "eqv-ok.s" "" "" ".eqv support"
+gas_test_error "eqv-bad.s" "" ".eqv for symbol already set"
+
+gas_test "assign-ok.s" "" "" "== assignment support"
+gas_test_error "assign-bad.s" "" "== assignment for symbol already set"
+
+# .equ works differently on some targets.
+# linkrelax-ing prevents most forward references from working.
+case $target_triplet in {
+    { crx*-*-* } { }
+    { h8300*-*-* } { }
+    { hppa*-*-* } { }
+    { mn10\[23\]00*-*-* } { }
+    { *c54x*-*-* } { }
+    default {
+	# Some targets don't manage to resolve BFD_RELOC_8 for constants.
+	setup_xfail "alpha*-*-*" "avr-*-*" "*c30*-*-*" "*c4x*-*-*" \
+	    "d\[13\]0v*-*-*" "i860-*-*" "mips*-*-*" "msp430-*-*" \
+	    "pdp11-*-*" "sparc*-*-*" "xtensa-*-*"
+	run_dump_test forward
+    }
+}
+
+# .set works differently on some targets.
+case $target_triplet in {
+    { alpha*-*-* } { }
+    { mips*-*-* } { }
+    { *c54x*-*-* } { }
+    { z80-*-* } { }
+    default {
+	setup_xfail "*c30*-*-*" "*c4x*-*-*" "pdp11-*-*"
+	run_dump_test redef
+	setup_xfail "*c30*-*-*" "*c4x*-*-*" "*arm*-*-*aout*" "*arm*-*-*coff" \
+	    "*arm*-*-pe" "crx*-*-*" "h8300*-*-*" "m68hc*-*-*" "maxq-*-*" \
+	    "pdp11-*-*" "vax*-*-*" "z8k-*-*"
+	run_dump_test redef2
+	setup_xfail "*-*-aix*" "*-*-coff" "*-*-cygwin" "*-*-mingw*" "*-*-pe*" \
+	    "bfin-*-*" "*c4x*-*-*" "crx*-*-*" "h8300*-*-*" "hppa*-*-hpux*" \
+	    "m68hc*-*-*" "maxq-*-*" "or32-*-*" "pdp11-*-*" "vax*-*-*" "z8k-*-*"
+	run_dump_test redef3
+	setup_xfail "*c4x*-*-*"
+	gas_test_error "redef4.s" "" ".set for symbol already used as label"
+	setup_xfail "*c4x*-*-*"
+	gas_test_error "redef5.s" "" ".set for symbol already defined through .comm"
+    }
+}
+
 proc do_comment {} {
     set testname "comment.s: comments in listings"
     set x1 0
@@ -85,12 +146,13 @@ proc do_930509a {} {
     if !$x then { fail $testname }
 }
 
-# This test is meaningless for the PA; the difference of two symbols
+# This test is meaningless for the PA and CRX; the difference of two symbols
 # must not be resolved by the assembler.
 # C54x assembler (for compatibility) does not allow differences between
 # forward references
 # C30 counts a four byte offset as a difference of one.
 if { ![istarget hppa*-*-*] &&
+     ![istarget  crx*-*-*] &&
      ![istarget *c30*-*-*] &&
      ![istarget *c4x*-*-*] &&
      ![istarget *c54x*-*-*] } then {
@@ -113,17 +175,33 @@ case $target_triplet in {
     }
 }
 
+# '<' and '>' appear to have special meanings on the excluded targets
+case $target_triplet in {
+    { frv-*-* } { }
+    { hppa*-*-* } { }
+    { m32r-*-* } { }
+    { mmix-*-* } { }
+    { *c4x*-*-* } { }
+    { *c54x*-*-* } { }
+    { bfin-*-* } { }
+    default {
+	run_dump_test altmacro
+	# The second test is valid only when '!' is not a comment
+	# character (it is allowed to be a line comment character).
+	if [string match "" [lindex [gas_run excl.s "-o /dev/null" ""] 0]] {
+	    run_dump_test altmac2
+	    # Similarly this test does not work when ! is a line seperator.
+	    run_dump_test eval
+	}
+    }
+}
+
 # This test is for any COFF target.
-# We omit m88k COFF because it uses weird pseudo-op names.
 # We omit the ARM toolchains because they define locals to
 #  start with '.', which eliminates .eos, .text etc from the output.
 # Omit c54x, since .tag and .def mean something different on that target
-if {   ([istarget *-*-coff*] && ![istarget m88*-*-*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
+if {   ([istarget *-*-coff*] && ![istarget *arm*-*-coff] && ![istarget thumb*-*-coff] && ![istarget xscale-*-coff] && ![istarget *c4x*-*-coff] && ![istarget *c54x*-*-coff]) \
      ||([istarget *-*-pe*] && ![istarget arm*-*-pe*] && ![istarget thumb*-*-pe*]) \
-     || [istarget a29k-*-udi*] \
-     || [istarget a29k-*-ebmon*] \
-     || [istarget a29k-*-sym*] \
-     || [istarget a29k-*-vxworks*] \
      || [istarget i*86-*-aix*] \
      || [istarget i*86-*-sco*] \
      || [istarget i*86-*-isc*] \
@@ -147,7 +225,7 @@ proc test_cond {} {
 	send_log "$comp_output\n"
 	fail $testname
     } else {
-	if { [regexp_diff dump.out $srcdir/$subdir/cond.d] } {
+	if { [regexp_diff dump.out $srcdir/$subdir/cond.l] } {
 	    fail $testname
 	} else {
 	    pass $testname
@@ -169,8 +247,40 @@ case $target_triplet in {
     }
 }
 
-if {   [istarget "i*86-*-*pe*"] \
+if {  ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \
     || [istarget "i*86-*-cygwin*"] \
     || [istarget "i*86-*-mingw32*"] } {
   gas_test "fastcall.s" ""   "" "fastcall labels"
 }
+
+run_dump_test assign
+run_dump_test sleb128
+
+# .quad is 16 bytes on i960.
+if { ![istarget "i960-*-*"] } {
+    run_dump_test quad
+}
+
+
+# .set works differently on some targets.
+case $target_triplet in {
+    { alpha*-*-* } { }
+    { mips*-*-* } { }
+    { *c54x*-*-* } { }
+    { z80-*-* } { }
+    default {
+	run_dump_test weakref1
+	run_dump_test weakref1g
+	run_dump_test weakref1l
+	run_dump_test weakref1u
+	run_dump_test weakref1w
+    }
+}
+gas_test_error "weakref2.s" "" "e: would close weakref loop: e => a => b => c => d => e"
+gas_test_error "weakref3.s" "" "a: would close weakref loop: a => b => c => d => e => a"
+gas_test_error "weakref4.s" "" "is already defined"
+
+load_lib gas-dg.exp
+dg-init
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/err-*.s $srcdir/$subdir/warn-*.s]] "" ""
+dg-finish
diff --git a/gas/testsuite/gas/all/itbl-test.c b/gas/testsuite/gas/all/itbl-test.c
index d97454ebf843..4900185811dc 100644
--- a/gas/testsuite/gas/all/itbl-test.c
+++ b/gas/testsuite/gas/all/itbl-test.c
@@ -18,8 +18,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* Stand-alone test for instruction specification table support.
    Run using "itbl-test <itbl> <asm.s>"
diff --git a/gas/testsuite/gas/all/quad.d b/gas/testsuite/gas/all/quad.d
new file mode 100644
index 000000000000..d0a8ddeec42b
--- /dev/null
+++ b/gas/testsuite/gas/all/quad.d
@@ -0,0 +1,12 @@
+#objdump : -s -j .data -j "\$DATA\$"
+#name : .quad tests
+
+.*: .*
+
+Contents of section (\.data|\$DATA\$):
+ 0000 (00000000 76543210 00000000 80000000|10325476 00000000 00000080 00000000|00000000 54761032 00000000 00800000|32107654 00000000 00008000 00000000) .*
+ 00.. (00000000 87654321 00000000 ffffffff|21436587 00000000 ffffffff 00000000|00000000 65872143 00000000 ffffffff|43218765 00000000 ffffffff 00000000) .*
+ 00.. (ffffffff 89abcdf0 ffffffff 80000000|f0cdab89 ffffffff 00000080 ffffffff|ffffffff ab89f0cd ffffffff 00800000|cdf089ab ffffffff 00008000 ffffffff) .*
+ 00.. (ffffffff 789abcdf ffffffff 00000001|dfbc9a78 ffffffff 01000000 ffffffff|ffffffff 9a78dfbc ffffffff 00000100|bcdf789a ffffffff 00010000 ffffffff) .*
+ 00.. (01234567 89abcdef fedcba98 76543211|efcdab89 67452301 11325476 98badcfe|23016745 ab89efcd dcfe98ba 54761132|cdef89ab 45670123 32117654 ba98fedc) .*
+#pass
diff --git a/gas/testsuite/gas/all/quad.s b/gas/testsuite/gas/all/quad.s
new file mode 100644
index 000000000000..af250cda3db6
--- /dev/null
+++ b/gas/testsuite/gas/all/quad.s
@@ -0,0 +1,12 @@
+	.data
+	.quad	0x76543210
+	.quad	0x80000000
+	.quad	0x87654321
+	.quad	0xffffffff
+	.quad	-0x76543210
+	.quad	-0x80000000
+	.quad	-0x87654321
+	.quad	-0xffffffff
+
+	.quad	0x123456789abcdef
+	.quad	-0x123456789abcdef
diff --git a/gas/testsuite/gas/all/redef.d b/gas/testsuite/gas/all/redef.d
new file mode 100644
index 000000000000..33e149ca8e51
--- /dev/null
+++ b/gas/testsuite/gas/all/redef.d
@@ -0,0 +1,8 @@
+#objdump: -s -j .data -j "\$DATA\$"
+#name: .equ redefinitions
+
+.*: .*
+
+Contents of section (\.data|\$DATA\$):
+ 0000 00000000 0[04]00000[04] 0[08]00000[08] 0[0c]00000[0c][ 	]+................[ 	]*
+#pass
diff --git a/gas/testsuite/gas/all/redef.s b/gas/testsuite/gas/all/redef.s
new file mode 100644
index 000000000000..896c460724ca
--- /dev/null
+++ b/gas/testsuite/gas/all/redef.s
@@ -0,0 +1,11 @@
+ .data
+_start:
+ .set x, .-_start
+ .long x
+ .balign 4
+ .set x, .-_start
+ .long x
+ .set x, .-_start
+ .long x
+ .set x, .-_start
+ .long x
diff --git a/gas/testsuite/gas/all/redef2.d b/gas/testsuite/gas/all/redef2.d
new file mode 100644
index 000000000000..244d33dd6802
--- /dev/null
+++ b/gas/testsuite/gas/all/redef2.d
@@ -0,0 +1,15 @@
+#objdump: -rs -j .data -j "\$DATA\$"
+#name: .equ redefinitions (2)
+
+.*: .*
+
+RELOCATION RECORDS FOR .*
+.*
+0+00.*(here|\.data|\$DATA\$)
+0+08.*xtrn
+0+10.*(sym|(\.data|\$DATA\$)(\+0x0+10)?)
+#...
+Contents of section (\.data|\$DATA\$):
+ 0000 00000000 11111111 00000000 22222222[ 	]+................[ 	]*
+ 0010 [01]00000[01]0 .*
+#pass
diff --git a/gas/testsuite/gas/all/redef2.s b/gas/testsuite/gas/all/redef2.s
new file mode 100644
index 000000000000..89a29ac13842
--- /dev/null
+++ b/gas/testsuite/gas/all/redef2.s
@@ -0,0 +1,12 @@
+ .data
+here:
+ .set sym, here
+ .long sym
+ .set sym, 0x11111111
+ .long sym
+ .set sym, xtrn
+ .long sym
+ .set sym, 0x22222222
+ .long sym
+sym:
+ .long sym
diff --git a/gas/testsuite/gas/all/redef3.d b/gas/testsuite/gas/all/redef3.d
new file mode 100644
index 000000000000..85843bb02eb5
--- /dev/null
+++ b/gas/testsuite/gas/all/redef3.d
@@ -0,0 +1,15 @@
+#objdump: -rsj .data
+#name: .equ redefinitions (3)
+
+.*: .*
+
+RELOCATION RECORDS FOR .*
+.*
+0+00.*(here|\.data)
+0+08.*xtrn
+0+10.*sym
+#...
+Contents of section \.data:
+ 0000 00000000 11111111 00000000 22222222[ 	]+................[ 	]*
+ 0010 00000000 .*
+#pass
diff --git a/gas/testsuite/gas/all/redef3.s b/gas/testsuite/gas/all/redef3.s
new file mode 100644
index 000000000000..2296d744ab52
--- /dev/null
+++ b/gas/testsuite/gas/all/redef3.s
@@ -0,0 +1,12 @@
+ .data
+here:
+ .set sym, here
+ .long sym
+ .set sym, 0x11111111
+ .long sym
+ .set sym, xtrn
+ .long sym
+ .set sym, 0x22222222
+ .long sym
+ .comm sym, 1
+ .long sym
diff --git a/gas/testsuite/gas/all/redef4.s b/gas/testsuite/gas/all/redef4.s
new file mode 100644
index 000000000000..8bd39438a9f2
--- /dev/null
+++ b/gas/testsuite/gas/all/redef4.s
@@ -0,0 +1,3 @@
+ .data
+sym:
+ .set sym, 0
diff --git a/gas/testsuite/gas/all/redef5.s b/gas/testsuite/gas/all/redef5.s
new file mode 100644
index 000000000000..8a3a67a1ecb1
--- /dev/null
+++ b/gas/testsuite/gas/all/redef5.s
@@ -0,0 +1,2 @@
+ .comm sym, 1
+ .set sym, 0
diff --git a/gas/testsuite/gas/all/sleb128.d b/gas/testsuite/gas/all/sleb128.d
new file mode 100644
index 000000000000..993921ef5be6
--- /dev/null
+++ b/gas/testsuite/gas/all/sleb128.d
@@ -0,0 +1,57 @@
+#objdump : -s -j .data -j "\$DATA\$"
+#name : .sleb128 tests
+
+.*: .*
+
+Contents of section (\.data|\$DATA\$):
+#
+# 0x76543210   :           000_0111 0110_010 1_0100_00 11_0010_0 001_0000
+# 0x80000000   :           000_1000 0000_000 0_0000_00 00_0000_0 000_0000
+# 0x87654321   :           000_1000 0111_011 0_0101_01 00_0011_0 010_0001
+# 0xffffffff   :           ..................................... 111_1111
+#
+ 0000 90e4d0b2 07808080 8008a186 95bb08ff .*
+#
+# 0xffffffff   :           000_1111 1111_111 1_1111_11 11_1111_1 ........
+# -0x76543210  :           111_1000 1001_101 0_1011_11 00_1101_1 111_0000
+# -0x80000000  :           111_1000 0000_000 0_0000_00 00_0000_0 000_0000
+# -0x87654321  :           ........................... 11_1100_1 101_1111
+#
+ 00.. ffffff0f f09bafcd 78808080 8078dff9 .*
+#
+# -0x87654321  :           111_0111 1000_100 1_1010_10 ..................
+# -0xffffffff  :           111_0000 0000_000 0_0000_00 00_0000_0 000_0001
+#    789abcdef :           111_1000 1001_101 0_1011_11 00_1101_1 110_1111
+# 0x123456     :           ........ 0010_001 1_0100_01 01_0110_0
+#
+ 00.. eac47781 80808070 ef9bafcd f8acd191 .*
+#
+# 0x123456     :           000_0001 ............................
+#    789abcdef :           000_0111 0110_010 1_0100_00 11_0010_0 001_0001
+# -0x123456    :           111_1110 1101_110 0_1011_10 01_1001_1
+#    fffffffff :           000_0000 0000_000 0_0000_00 00_0000_0 000_0001
+# -0x7ff       :                             ......... 00_0000_0
+#
+ 00.. 0191e4d0 b287d3ae ee7e8180 80808080 .*
+#
+# -0x7ff       :                             1_1000_00 .........
+#    000000000 :           000_0000 0000_000 0_0000_00 00_0000_0 000_0000
+# -0x800       :                             1_1000_00 00_0000_0
+#    fffffffff :           000_0000 0000_000 0_0000_00 00_0000_0 000_0001
+# -0x7ffffff   : .................. 0000_000 0_0000_00 00_0000_0
+#
+ 00.. 60808080 80808060 81808080 80808080 .*
+#
+# -0x7ffffff   : 11_1111_1 000_0000 ............................
+#    000000000 :           000_0000 0000_000 0_0000_00 00_0000_0 000_0000
+# -0x8000000   : 11_1111_1 000_0000 0000_000 0_0000_00 00_0000_0
+# -0x100000000 :           ........ 0000_000 0_0000_00 00_0000_0 000_0000
+#
+ 00.. 807f8080 80808080 8080807f 80808080 .*
+#
+# -0x100000000 :           111_0000 .....................................
+#    000000000 :           000_0000 0000_000 0_0000_00 00_0000_0 000_0000
+# -0x1000      :                             1_0000_00 00_0000_0
+#
+ 00.. 70808080 80808040 00000000 00000000 .*
+#pass
diff --git a/gas/testsuite/gas/all/sleb128.s b/gas/testsuite/gas/all/sleb128.s
new file mode 100644
index 000000000000..e8997ca175d4
--- /dev/null
+++ b/gas/testsuite/gas/all/sleb128.s
@@ -0,0 +1,22 @@
+	.data
+	.sleb128	0x76543210
+	.sleb128	0x80000000
+	.sleb128	0x87654321
+	.sleb128	0xffffffff
+	.sleb128	-0x76543210
+	.sleb128	-0x80000000
+	.sleb128	-0x87654321
+	.sleb128	-0xffffffff
+
+	.sleb128	0x123456789abcdef
+	.sleb128	-0x123456789abcdef
+
+	.sleb128	-0x7fffffffffff
+	.sleb128	-0x800000000000
+	.sleb128	-0x7fffffffffffffff
+	.sleb128	-0x8000000000000000
+
+	.sleb128	-0x100000000
+	.sleb128	-0x1000000000000
+
+	.fill		32
diff --git a/gas/testsuite/gas/all/test-example.c b/gas/testsuite/gas/all/test-example.c
index a6474264349f..9a7f19ffce9e 100644
--- a/gas/testsuite/gas/all/test-example.c
+++ b/gas/testsuite/gas/all/test-example.c
@@ -13,7 +13,7 @@
   
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* Generator of tests for insns introduced in AM33 2.0.
   
diff --git a/gas/testsuite/gas/all/test-gen.c b/gas/testsuite/gas/all/test-gen.c
index 50412d3d66e6..bb175dbe5292 100644
--- a/gas/testsuite/gas/all/test-gen.c
+++ b/gas/testsuite/gas/all/test-gen.c
@@ -16,7 +16,7 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* This is a source file with infra-structure to test generators for
    assemblers and disassemblers.
diff --git a/gas/testsuite/gas/all/warn-1.s b/gas/testsuite/gas/all/warn-1.s
new file mode 100644
index 000000000000..873f2308534a
--- /dev/null
+++ b/gas/testsuite/gas/all/warn-1.s
@@ -0,0 +1,7 @@
+;# Test .warning directive.
+;# { dg-do assemble }
+ .warning "a warning message"	;# { dg-warning "Warning: a warning message" }
+ .warning a warning message	;# { dg-error "Error: .warning argument must be a string" }
+ .warning			;# { dg-warning "Warning: .warning directive invoked in source file" }
+ .warning ".warning directive invoked in source file"	;# { dg-warning "Warning: .warning directive invoked in source file" }
+ .warning ""			;# { dg-warning "Warning: " }
diff --git a/gas/testsuite/gas/all/weakref1.d b/gas/testsuite/gas/all/weakref1.d
new file mode 100644
index 000000000000..ee37d977009b
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1.d
@@ -0,0 +1,96 @@
+#objdump: -r
+#name: weakref tests, relocations
+# ecoff (OSF/alpha) lacks .weak support
+# pdp11 lacks .long
+# the following must be present in all weakref1*.d
+#not-target: alpha*-*-osf* *-*-ecoff pdp11-*-aout
+
+#...
+RELOCATION RECORDS FOR \[(\.text|\$CODE\$)\]:
+OFFSET +TYPE +VALUE *
+# the rest of this file is generated with the following script:
+# # script begin
+# echo \#...
+# sed -n 's:^[ 	]*\.long \(W\|\)\(.*[^a-z]\)[a-z]*\(\| - .*\)$:\2:p' weakref1.s | sed -e 's,^[lg].*,(&|\\.text)(\\+0x[0-9a-f]+)?,' | sed 's,^,[0-9a-f]+ [^ ]*  +,'
+# # script output:
+#...
+[0-9a-f]+ [^ ]*  +wa1
+[0-9a-f]+ [^ ]*  +ua2
+[0-9a-f]+ [^ ]*  +ua3
+[0-9a-f]+ [^ ]*  +ua3
+[0-9a-f]+ [^ ]*  +ua4
+[0-9a-f]+ [^ ]*  +ua4
+[0-9a-f]+ [^ ]*  +wb1
+[0-9a-f]+ [^ ]*  +ub2
+[0-9a-f]+ [^ ]*  +ub3
+[0-9a-f]+ [^ ]*  +ub3
+[0-9a-f]+ [^ ]*  +ub4
+[0-9a-f]+ [^ ]*  +ub4
+[0-9a-f]+ [^ ]*  +wc1
+[0-9a-f]+ [^ ]*  +wc1
+[0-9a-f]+ [^ ]*  +uc2
+[0-9a-f]+ [^ ]*  +uc2
+[0-9a-f]+ [^ ]*  +uc3
+[0-9a-f]+ [^ ]*  +uc3
+[0-9a-f]+ [^ ]*  +uc3
+[0-9a-f]+ [^ ]*  +uc3
+[0-9a-f]+ [^ ]*  +uc4
+[0-9a-f]+ [^ ]*  +uc4
+[0-9a-f]+ [^ ]*  +uc4
+[0-9a-f]+ [^ ]*  +uc4
+[0-9a-f]+ [^ ]*  +uc5
+[0-9a-f]+ [^ ]*  +uc5
+[0-9a-f]+ [^ ]*  +uc5
+[0-9a-f]+ [^ ]*  +uc5
+[0-9a-f]+ [^ ]*  +uc6
+[0-9a-f]+ [^ ]*  +uc6
+[0-9a-f]+ [^ ]*  +uc6
+[0-9a-f]+ [^ ]*  +uc6
+[0-9a-f]+ [^ ]*  +uc7
+[0-9a-f]+ [^ ]*  +uc7
+[0-9a-f]+ [^ ]*  +uc8
+[0-9a-f]+ [^ ]*  +uc8
+[0-9a-f]+ [^ ]*  +uc9
+[0-9a-f]+ [^ ]*  +uc9
+[0-9a-f]+ [^ ]*  +uc9
+[0-9a-f]+ [^ ]*  +ww1
+[0-9a-f]+ [^ ]*  +ww2
+[0-9a-f]+ [^ ]*  +ww3
+[0-9a-f]+ [^ ]*  +ww3
+[0-9a-f]+ [^ ]*  +ww4
+[0-9a-f]+ [^ ]*  +ww4
+[0-9a-f]+ [^ ]*  +ww5
+[0-9a-f]+ [^ ]*  +ww5
+[0-9a-f]+ [^ ]*  +ww6
+[0-9a-f]+ [^ ]*  +ww7
+[0-9a-f]+ [^ ]*  +ww8
+[0-9a-f]+ [^ ]*  +ww8
+[0-9a-f]+ [^ ]*  +ww9
+[0-9a-f]+ [^ ]*  +ww9
+[0-9a-f]+ [^ ]*  +ww10
+[0-9a-f]+ [^ ]*  +ww10
+[0-9a-f]+ [^ ]*  +um5
+[0-9a-f]+ [^ ]*  +wm6
+[0-9a-f]+ [^ ]*  +wm7
+[0-9a-f]+ [^ ]*  +wm8
+[0-9a-f]+ [^ ]*  +wh2
+[0-9a-f]+ [^ ]*  +wh3
+[0-9a-f]+ [^ ]*  +wh4
+[0-9a-f]+ [^ ]*  +wh5
+[0-9a-f]+ [^ ]*  +wh6
+[0-9a-f]+ [^ ]*  +wh7
+[0-9a-f]+ [^ ]*  +uh8
+[0-9a-f]+ [^ ]*  +uh8
+[0-9a-f]+ [^ ]*  +uh9
+[0-9a-f]+ [^ ]*  +uh9
+[0-9a-f]+ [^ ]*  +(ld1|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld2|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld3|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld4|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +ud5
+[0-9a-f]+ [^ ]*  +(gd6|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(gd7|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld8|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld8|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld9|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
+[0-9a-f]+ [^ ]*  +(ld9|\.text|\$CODE\$)(\+0x[0-9a-f]+)?
diff --git a/gas/testsuite/gas/all/weakref1.s b/gas/testsuite/gas/all/weakref1.s
new file mode 100644
index 000000000000..ce550d842a9e
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1.s
@@ -0,0 +1,232 @@
+	.text
+l:
+/* a# test references after weakref. */
+	.weakref Wwa1, wa1
+	.long Wwa1
+
+	.weakref Wua2, ua2
+	.long ua2
+
+	.weakref Wua3, ua3
+	.long Wua3
+	.long ua3
+
+	.weakref Wua4, ua4
+	.long ua4
+	.long Wua4
+
+	.weakref Wna5, na5
+
+/* b# test references before weakref.  */
+	.long Wwb1
+	.weakref Wwb1, wb1
+
+	.long ub2
+	.weakref Wub2, ub2
+
+	.long Wub3
+	.long ub3
+	.weakref Wub3, ub3
+
+	.long ub4
+	.long Wub4
+	.weakref Wub4, ub4
+
+/* c# test combinations of references before and after weakref.  */
+	.long Wwc1
+	.weakref Wwc1, wc1
+	.long Wwc1
+
+	.long uc2
+	.weakref Wuc2, uc2
+	.long uc2
+
+	.long Wuc3
+	.long uc3
+	.weakref Wuc3, uc3
+	.long Wuc3
+	.long uc3
+
+	.long uc4
+	.long Wuc4
+	.weakref Wuc4, uc4
+	.long uc4
+	.long Wuc4
+
+	.long Wuc5
+	.long uc5
+	.weakref Wuc5, uc5
+	.long uc5
+	.long Wuc5
+
+	.long uc6
+	.long Wuc6
+	.weakref Wuc6, uc6
+	.long uc6
+	.long Wuc6
+
+	.long uc7
+	.weakref Wuc7, uc7
+	.long Wuc7
+
+	.long Wuc8
+	.weakref Wuc8, uc8
+	.long uc8
+
+	.long Wuc9
+	.weakref Wuc9, uc9
+	.long Wuc9
+	.long uc9
+
+/* w# test that explicitly weak target don't lose the weak status */
+	.weakref Www1, ww1
+	.weak ww1
+	.long ww1
+
+	.weak ww2
+	.weakref Www2, ww2
+	.long ww2
+
+	.weak ww3
+	.long ww3
+	.weakref Www3, ww3
+	.long ww3
+
+	.long ww4
+	.weakref Www4, ww4
+	.weak ww4
+	.long ww4
+
+	.long ww5
+	.weakref Www5, ww5
+	.long ww5
+	.weak ww5
+
+	.weakref Www6, ww6
+	.weak ww6
+	.long Www6
+
+	.weak ww7
+	.weakref Www7, ww7
+	.long Www7
+
+	.weak ww8
+	.long Www8
+	.weakref Www8, ww8
+	.long Www8
+
+	.long Www9
+	.weakref Www9, ww9
+	.weak ww9
+	.long Www9
+
+	.long Www10
+	.weakref Www10, ww10
+	.long Www10
+	.weak ww10
+
+/* m# test multiple weakrefs */
+	.weakref Wnm4a, nm4
+	.weakref Wnm4b, nm4
+
+	.weakref Wum5a, um5
+	.weakref Wum5b, um5
+	.long um5
+
+	.weakref Wwm6a, wm6
+	.weakref Wwm6b, wm6
+	.long Wwm6a
+
+	.weakref Wwm7a, wm7
+	.weakref Wwm7b, wm7
+	.long Wwm7b
+
+	.weakref Wwm8a, wm8
+	.long Wwm8b
+	.weakref Wwm8b, wm8
+
+/* h# test weakref chain */
+	.weakref Wnh1a, nh1
+	.weakref Wnh1b, Wnh1a
+	.weakref Wnh1c, Wnh1b
+
+	.weakref Wwh2a, wh2
+	.weakref Wwh2b, Wwh2a
+	.long Wwh2b
+
+	.weakref Wwh3a, wh3
+	.weakref Wwh3b, Wwh3a
+	.long Wwh3a
+
+	.weakref Wwh4b, Wwh4a
+	.weakref Wwh4a, wh4
+	.long Wwh4b
+
+	.long Wwh5b
+	.weakref Wwh5a, wh5
+	.weakref Wwh5b, Wwh5a
+
+	.long Wwh6b
+	.weakref Wwh6b, Wwh6a
+	.weakref Wwh6a, wh6
+
+	.weakref Wwh7b, Wwh7a
+	.long Wwh7b
+	.weakref Wwh7a, wh7
+
+	.long Wuh8c
+	.weakref Wuh8a, uh8
+	.weakref Wuh8b, Wuh8a
+	.weakref Wuh8c, Wuh8b
+	.long uh8
+
+	.long Wuh9c
+	.weakref Wuh9c, Wuh9b
+	.weakref Wuh9b, Wuh9a
+	.weakref Wuh9a, uh9
+	.long uh9
+
+/* d# target symbol definitions */
+	.weakref Wld1, ld1
+	.long Wld1
+	ld1 = l
+
+	.weakref Wld2, ld2
+	.long Wld2
+ld2:
+
+ld3:
+	.weakref Wld3, ld3
+	.long Wld3
+
+ld4:
+	.long Wld4
+	.weakref Wld4, ld4
+
+	.global ud5
+	.weakref Wud5, ud5
+	.long Wud5
+
+	.global gd6
+	.weakref Wgd6, gd6
+	.long Wgd6
+gd6:
+
+	.weakref Wgd7, gd7
+	.long Wgd7
+	.global gd7
+gd7:
+
+	.long Wld8c
+	.weakref Wld8a, ld8
+	.weakref Wld8b, Wld8a
+	.weakref Wld8c, Wld8b
+	.long ld8
+ld8:
+
+	.long Wld9c
+	.weakref Wld9c, Wld9b
+	.weakref Wld9b, Wld9a
+	.weakref Wld9a, ld9
+	.long ld9
+ld9:
diff --git a/gas/testsuite/gas/all/weakref1g.d b/gas/testsuite/gas/all/weakref1g.d
new file mode 100644
index 000000000000..039c599786bd
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1g.d
@@ -0,0 +1,18 @@
+#nm: --defined-only --extern-only
+#name: weakref tests, global syms
+#source: weakref1.s
+# see weakref1.d for comments on the not-targets
+# ecoff (OSF/alpha) lacks .weak support
+# pdp11 lacks .long
+#not-target: alpha*-*-osf* *-*-ecoff pdp11-*-aout
+
+# the rest of this file is generated with the following script:
+# # script begin
+# echo \#...
+# sed -n 's,^[ 	]*\.global \(g.*\),.* T \1,p' weakref1.s | uniq
+# echo \#pass
+# # script output:
+#...
+.* T gd6
+.* T gd7
+#pass
diff --git a/gas/testsuite/gas/all/weakref1l.d b/gas/testsuite/gas/all/weakref1l.d
new file mode 100644
index 000000000000..05ba4583b459
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1l.d
@@ -0,0 +1,27 @@
+#nm: --defined-only
+#name: weakref tests, local syms
+#source: weakref1.s
+# aix drops local symbols
+# see weakref1.d for comments on the other not-targets
+#not-target: *-*-aix* alpha*-*-osf* *-*-ecoff pdp11-*-aout
+
+# the rest of this file is generated with the following script:
+# # script begin
+# sed -n 's,^\(l[^ ]*\)[ 	]*:.*,.* t \1,p;s:^[ 	]*\.set[ 	][ 	]*\(l[^ ]*\)[ 	]*,.*:.* t \1:p' weakref1.s | uniq | while read line; do echo "#..."; echo "$line"; done
+# echo \#pass
+# # script output:
+#...
+.* t l
+#...
+.* t ld1
+#...
+.* t ld2
+#...
+.* t ld3
+#...
+.* t ld4
+#...
+.* t ld8
+#...
+.* t ld9
+#pass
diff --git a/gas/testsuite/gas/all/weakref1u.d b/gas/testsuite/gas/all/weakref1u.d
new file mode 100644
index 000000000000..f140addc338d
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1u.d
@@ -0,0 +1,49 @@
+#nm: --undefined-only
+#name: weakref tests, strong undefined syms
+#source: weakref1.s
+# aout turns undefined into *ABS* symbols.
+# see weakref1.d for comments on the other not-targets
+#not-target: *-*-aout ns32k-*-netbsd alpha*-*-osf* *-*-ecoff pdp11-*-aout
+
+# the rest of this file is generated with the following script:
+# # script begin
+# sed -n 's:^[ 	]*\.weakref .*, \(u.*\)$:.* U \1:p' weakref1.s | uniq | while read line; do echo "#..."; echo "$line"; done
+# echo \#pass
+# # script output:
+#...
+.* U ua2
+#...
+.* U ua3
+#...
+.* U ua4
+#...
+.* U ub2
+#...
+.* U ub3
+#...
+.* U ub4
+#...
+.* U uc2
+#...
+.* U uc3
+#...
+.* U uc4
+#...
+.* U uc5
+#...
+.* U uc6
+#...
+.* U uc7
+#...
+.* U uc8
+#...
+.* U uc9
+#...
+.* U ud5
+#...
+.* U uh8
+#...
+.* U uh9
+#...
+.* U um5
+#pass
diff --git a/gas/testsuite/gas/all/weakref1w.d b/gas/testsuite/gas/all/weakref1w.d
new file mode 100644
index 000000000000..459877616aca
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref1w.d
@@ -0,0 +1,56 @@
+#nm: --undefined-only
+#name: weakref tests, weak undefined syms
+#source: weakref1.s
+# see weakref1.d for comments on the not-targets
+#not-target: alpha*-*-osf* *-*-ecoff pdp11-*-aout
+
+# the rest of this file is generated with the following script:
+# # script begin
+# sed -n 's:^[ 	]*\.weakref .*, \(w.*\)$:.* w \1:p' weakref1.s | uniq | while read line; do echo "#..."; echo "$line"; done
+# echo \#pass
+# # script output:
+#...
+.* w wa1
+#...
+.* w wb1
+#...
+.* w wc1
+#...
+.* w wh2
+#...
+.* w wh3
+#...
+.* w wh4
+#...
+.* w wh5
+#...
+.* w wh6
+#...
+.* w wh7
+#...
+.* w wm6
+#...
+.* w wm7
+#...
+.* w wm8
+#...
+.* w ww1
+#...
+.* w ww10
+#...
+.* w ww2
+#...
+.* w ww3
+#...
+.* w ww4
+#...
+.* w ww5
+#...
+.* w ww6
+#...
+.* w ww7
+#...
+.* w ww8
+#...
+.* w ww9
+#pass
diff --git a/gas/testsuite/gas/all/weakref2.s b/gas/testsuite/gas/all/weakref2.s
new file mode 100644
index 000000000000..049f1ec8e1e5
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref2.s
@@ -0,0 +1,5 @@
+	.weakref a,b
+	.weakref b,c
+	.weakref c,d
+	.weakref d,e
+	.weakref e,a
diff --git a/gas/testsuite/gas/all/weakref3.s b/gas/testsuite/gas/all/weakref3.s
new file mode 100644
index 000000000000..48f69877271b
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref3.s
@@ -0,0 +1,5 @@
+	.weakref e,a
+	.weakref d,e
+	.weakref c,d
+	.weakref b,c
+	.weakref a,b
diff --git a/gas/testsuite/gas/all/weakref4.s b/gas/testsuite/gas/all/weakref4.s
new file mode 100644
index 000000000000..b984c64d3ca2
--- /dev/null
+++ b/gas/testsuite/gas/all/weakref4.s
@@ -0,0 +1,45 @@
+/* m# test multiple weakrefs */
+	.weakref Wnm1, nm1
+	.weakref Wnm1, nm1
+
+	.weakref Wum2, um2
+	.weakref Wum2, um2
+	.long um2
+
+	.weakref Wwm3, wm3
+	.weakref Wwm3, wm3
+	.long Wwm3
+
+/* r# weakref redefinitions, to and from */
+	.weakref lr1, nr1
+	.long lr1
+	.set lr1, l
+	.long lr1
+
+	.long lr2
+	.weakref lr2, nr2
+	.set lr2, l
+	.long lr2
+
+	.set Wwr3, l
+	.long Wwr3
+	.weakref Wwr3, wr3
+	.long Wwr3
+
+	.set Wwr4, l
+	.weakref Wwr4, wr4
+	.long Wwr4
+
+	.set Wwr5, l
+	.long Wwr5
+	.weakref Wwr5, wr5
+
+	.weakref lr6, ur6
+	.long lr6
+	.set lr6, l
+	.long ur6
+
+	.weakref lr7, nr7
+	.long lr7
+lr7:
+	.long lr7
diff --git a/gas/testsuite/gas/alpha/elf-usepv-1.d b/gas/testsuite/gas/alpha/elf-usepv-1.d
index cd0603ffff1b..115eb691c29c 100644
--- a/gas/testsuite/gas/alpha/elf-usepv-1.d
+++ b/gas/testsuite/gas/alpha/elf-usepv-1.d
@@ -4,8 +4,8 @@
 .*:     file format elf64-alpha.*
 
 SYMBOL TABLE:
-0*0000000 l    d  .text	0*0000000 
-0*0000000 l    d  .data	0*0000000 
-0*0000000 l    d  .bss	0*0000000 
-0*0000000 l       .text	0*0000000 0x80 foo
-0*0000004 l       .text	0*0000000 0x88 bar
+0*0000000 l    d  \.text	0*0000000 (|\.text)
+0*0000000 l    d  \.data	0*0000000 (|\.data)
+0*0000000 l    d  \.bss	0*0000000 (|\.bss)
+0*0000000 l       \.text	0*0000000 0x80 foo
+0*0000004 l       \.text	0*0000000 0x88 bar
diff --git a/gas/testsuite/gas/arc/arc.exp b/gas/testsuite/gas/arc/arc.exp
index 2e115f926552..3947bbee0171 100644
--- a/gas/testsuite/gas/arc/arc.exp
+++ b/gas/testsuite/gas/arc/arc.exp
@@ -37,6 +37,7 @@ if [istarget arc*-*-*] then {
     run_dump_test bic
     run_dump_test xor
     run_dump_test nop
+    run_dump_test extensions
 }
 
 # ARC library extensions
diff --git a/gas/testsuite/gas/arc/extensions.d b/gas/testsuite/gas/arc/extensions.d
new file mode 100644
index 000000000000..dc0d80b5f51d
--- /dev/null
+++ b/gas/testsuite/gas/arc/extensions.d
@@ -0,0 +1,12 @@
+#as: -EL -marc8
+#objdump: -dr -EL
+
+.*: +file format elf32-.*arc
+
+Disassembly of section .text:
+
+00000000 <condcodeTest>:
+   0:	12 02 00 40 	40000212     add.isbusy r0,r0,r1
+   4:	00 02 60 45 	45600200     add        rwscreg,r0,r1
+   8:	00 d8 00 40 	4000d800     add        r0,r1,roscreg
+   c:	00 02 a0 45 	45a00200     add        woscreg,r0,r1
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/extensions.s b/gas/testsuite/gas/arc/extensions.s
new file mode 100644
index 000000000000..44484eb06e86
--- /dev/null
+++ b/gas/testsuite/gas/arc/extensions.s
@@ -0,0 +1,10 @@
+.extCondCode   isbusy, 0x12
+.extCoreRegister rwscreg,43,r|w,can_shortcut
+.extCoreRegister roscreg,44,r,can_shortcut
+.extCoreRegister woscreg,45,w,can_shortcut
+	.section .text
+condcodeTest:
+	add.isbusy r0,r0,r1
+	add 	rwscreg,r0,r1
+	add 	r0,r1,roscreg
+	add	woscreg,r0,r1
diff --git a/gas/testsuite/gas/arc/ld.d b/gas/testsuite/gas/arc/ld.d
index b989f8b8683c..2680ae9fdfb8 100644
--- a/gas/testsuite/gas/arc/ld.d
+++ b/gas/testsuite/gas/arc/ld.d
@@ -11,3 +11,6 @@ Disassembly of section .text:
    8:	08 88 21 00 	00218808     ld.a       r1,\[r3,r4\]
    c:	05 06 21 00 	00210605     ldw.x      r1,\[r2,r3\]
   10:	0d 88 41 00 	0041880d     ldw.x.a    r2,\[r3,r4\]
+  14:	00 80 1f 08 	081f8000     ld         r0,\[0\]
+  18:	1e 80 00 08 	0800801e     ld         r0,\[r1,30\]
+  1c:	ec 01 21 08 	082101ec     ld         r1,\[r2,-20\]
diff --git a/gas/testsuite/gas/arc/ld.s b/gas/testsuite/gas/arc/ld.s
index 36edf9cae630..7d0a5b839fac 100644
--- a/gas/testsuite/gas/arc/ld.s
+++ b/gas/testsuite/gas/arc/ld.s
@@ -5,3 +5,6 @@
 	ld.a	r1,[r3,r4]
 	ldw.x	r1,[r2,r3]
 	ldw.x.a	r2,[r3,r4]
+	ld	r0,[0]
+        ld      r0,[r1,30]
+        ld      r1,[r2,-20]
diff --git a/gas/testsuite/gas/arc/st.d b/gas/testsuite/gas/arc/st.d
index 65ee84070304..813f1aa33fae 100644
--- a/gas/testsuite/gas/arc/st.d
+++ b/gas/testsuite/gas/arc/st.d
@@ -31,3 +31,12 @@ Disassembly of section .text:
 			4c: R_ARC_B26	.text
   50:	00 02 01 12 	12010200     sr         r1,\[r2\]
   54:	0e 82 1f 12 	121f820e     sr         r1,\[0xe\]
+  58:	00 fc 00 12 	1200fc00     sr         0x3e8,\[r1\]
+  5c:	e8 03 00 00 
+  60:	64 7e 01 12 	12017e64     sr         100,\[r2\]
+  64:	00 02 1f 12 	121f0200     sr         r1,\[0x2710\]
+  68:	10 27 00 00 
+  6c:	64 7e 1f 12 	121f7e64     sr         100,\[0x2710\]
+  70:	10 27 00 00 
+  74:	64 fc 1f 12 	121ffc64     sr         0x2710,\[0x64\]
+  78:	10 27 00 00 
diff --git a/gas/testsuite/gas/arc/st.s b/gas/testsuite/gas/arc/st.s
index 38ba009b5035..9acd9f5aa98f 100644
--- a/gas/testsuite/gas/arc/st.s
+++ b/gas/testsuite/gas/arc/st.s
@@ -20,3 +20,8 @@
 
 	sr	r1,[r2]
 	sr	r1,[14]
+	sr	1000, [r1]
+	sr	100,  [r2]
+	sr	r1,[10000]
+	sr	100,[10000]
+	sr	10000,[100]
diff --git a/gas/testsuite/gas/arc/warn.s b/gas/testsuite/gas/arc/warn.s
index 060a74edab16..6df1185dadbe 100644
--- a/gas/testsuite/gas/arc/warn.s
+++ b/gas/testsuite/gas/arc/warn.s
@@ -9,3 +9,8 @@
 	mov r0,r1
 
 foo:
+.extCoreRegister roscreg,45,r,can_shortcut
+.extCoreRegister woscreg,46,w,can_shortcut
+        .section .text
+         add    r0,woscreg,r1   ; { dg-warning "Error: attempt to read writeonly register" }
+         add    roscreg,r1,r2   ; { dg-warning "Error: attempt to set readonly register" }
diff --git a/gas/testsuite/gas/arm/abs12.d b/gas/testsuite/gas/arm/abs12.d
new file mode 100644
index 000000000000..5d4bb3b35e01
--- /dev/null
+++ b/gas/testsuite/gas/arm/abs12.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+#not-skip: *-vxworks
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	e5910000 	ldr	r0, \[r1\]
+			0: R_ARM_ABS12	global
+   4:	e5910000 	ldr	r0, \[r1\]
+			4: R_ARM_ABS12	global\+0xc
+   8:	e5910000 	ldr	r0, \[r1\]
+			8: R_ARM_ABS12	global\+0x100000
+   c:	e5910000 	ldr	r0, \[r1\]
+			c: R_ARM_ABS12	\.text\+0x18
+  10:	e5910000 	ldr	r0, \[r1\]
+			10: R_ARM_ABS12	\.text\+0x24
+  14:	e5910000 	ldr	r0, \[r1\]
+			14: R_ARM_ABS12	\.text\+0x100018
diff --git a/gas/testsuite/gas/arm/abs12.s b/gas/testsuite/gas/arm/abs12.s
new file mode 100644
index 000000000000..9c2faa559d20
--- /dev/null
+++ b/gas/testsuite/gas/arm/abs12.s
@@ -0,0 +1,7 @@
+	ldr	r0,[r1,#global]
+	ldr	r0,[r1,#global + 12]
+	ldr	r0,[r1,#global + 0x100000]
+	ldr	r0,[r1,#local]
+	ldr	r0,[r1,#local + 12]
+	ldr	r0,[r1,#local + 0x100000]
+local:
diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d
new file mode 100644
index 000000000000..0fdaa8fdecbe
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch4t.d
@@ -0,0 +1,36 @@
+# name: ARM architecture 4t instructions
+# as: -march=armv4t
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e12fff10 ?	bx	r0
+0+04 <[^>]+> 012fff11 ?	bxeq	r1
+0+08 <[^>]+> e15f30b8 ?	ldrh	r3, \[pc, #-8\]	; 0+08 <[^>]+>
+0+0c <[^>]+> e1d540f0 ?	ldrsh	r4, \[r5\]
+0+10 <[^>]+> e19140d3 ?	ldrsb	r4, \[r1, r3\]
+0+14 <[^>]+> e1b410f4 ?	ldrsh	r1, \[r4, r4\]!
+0+18 <[^>]+> 011510d3 ?	ldreqsb	r1, \[r5, -r3\]
+0+1c <[^>]+> 109620b7 ?	ldrneh	r2, \[r6\], r7
+0+20 <[^>]+> 309720f8 ?	ldrccsh	r2, \[r7\], r8
+0+24 <[^>]+> e1d32fdf ?	ldrsb	r2, \[r3, #255\]
+0+28 <[^>]+> e1541ffa ?	ldrsh	r1, \[r4, #-250\]
+0+2c <[^>]+> e1d51fd0 ?	ldrsb	r1, \[r5, #240\]
+0+30 <[^>]+> e1cf23b0 ?	strh	r2, \[pc, #48\]	; 0+68 <[^>]+>
+0+34 <[^>]+> 11c330b0 ?	strneh	r3, \[r3\]
+0+38 <[^>]+> e328f002 ?	msr	CPSR_f, #2	; 0x2
+0+3c <[^>]+> e121f003 ?	msr	CPSR_c, r3
+0+40 <[^>]+> e122f004 ?	msr	CPSR_x, r4
+0+44 <[^>]+> e124f005 ?	msr	CPSR_s, r5
+0+48 <[^>]+> e128f006 ?	msr	CPSR_f, r6
+0+4c <[^>]+> e129f007 ?	msr	CPSR_fc, r7
+0+50 <[^>]+> e368f004 ?	msr	SPSR_f, #4	; 0x4
+0+54 <[^>]+> e161f008 ?	msr	SPSR_c, r8
+0+58 <[^>]+> e162f009 ?	msr	SPSR_x, r9
+0+5c <[^>]+> e164f00a ?	msr	SPSR_s, sl
+0+60 <[^>]+> e168f00b ?	msr	SPSR_f, fp
+0+64 <[^>]+> e169f00c ?	msr	SPSR_fc, ip
+0+68 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+6c <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+
diff --git a/gas/testsuite/gas/arm/arch4t.s b/gas/testsuite/gas/arm/arch4t.s
index 417b3c6beecb..984829d82641 100644
--- a/gas/testsuite/gas/arm/arch4t.s
+++ b/gas/testsuite/gas/arm/arch4t.s
@@ -1,6 +1,6 @@
-.text
-.align 0
-	
+	.text
+	.align 0
+l:
 	bx	r0
 	bxeq	r1
 
@@ -33,3 +33,6 @@ foo:
 	msr	SPSR_f, r11
 	msr	SPSR_all, r12
 bar:
+	@ section padding for a.out's benefit
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/arch6zk.d b/gas/testsuite/gas/arm/arch6zk.d
new file mode 100644
index 000000000000..e9dee215f4c6
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch6zk.d
@@ -0,0 +1,32 @@
+#name: ARM V6 instructions
+#as: -march=armv6zk
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> f57ff01f ?	clrex
+0+004 <[^>]*> e1dc4f9f ?	ldrexb	r4, \[ip\]
+0+008 <[^>]*> 11d4cf9f ?	ldrexbne	ip, \[r4\]
+0+00c <[^>]*> e1bc4f9f ?	ldrexd	r4, \[ip\]
+0+010 <[^>]*> 11b4cf9f ?	ldrexdne	ip, \[r4\]
+0+014 <[^>]*> e1fc4f9f ?	ldrexh	r4, \[ip\]
+0+018 <[^>]*> 11f4cf9f ?	ldrexhne	ip, \[r4\]
+0+01c <[^>]*> e320f080 ?	nop	\{128\}
+0+020 <[^>]*> 1320f07f ?	nopne	\{127\}
+0+024 <[^>]*> e320f004 ?	sev
+0+028 <[^>]*> e1c74f9c ?	strexb	r4, ip, \[r7\]
+0+02c <[^>]*> 11c8cf94 ?	strexbne	ip, r4, \[r8\]
+0+030 <[^>]*> e1a74f9c ?	strexd	r4, ip, \[r7\]
+0+034 <[^>]*> 11a8cf94 ?	strexdne	ip, r4, \[r8\]
+0+038 <[^>]*> e1e74f9c ?	strexh	r4, ip, \[r7\]
+0+03c <[^>]*> 11e8cf94 ?	strexhne	ip, r4, \[r8\]
+0+040 <[^>]*> e320f002 ?	wfe
+0+044 <[^>]*> e320f003 ?	wfi
+0+048 <[^>]*> e320f001 ?	yield
+0+04c <[^>]*> e16ec371 ?	smc	60465
+0+050 <[^>]*> 11613c7e ?	smcne	5070
+0+054 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
+0+058 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
+0+05c <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
+
diff --git a/gas/testsuite/gas/arm/arch6zk.s b/gas/testsuite/gas/arm/arch6zk.s
new file mode 100644
index 000000000000..93398675b828
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch6zk.s
@@ -0,0 +1,33 @@
+.text
+.align 0
+
+label:
+	# ARMV6K instructions
+	clrex
+	ldrexb		r4, [r12]
+	ldrexbne	r12, [r4]
+	ldrexd		r4, [r12]
+	ldrexdne	r12, [r4]
+	ldrexh		r4, [r12]
+	ldrexhne	r12, [r4]
+	nop 		{128}
+	nopne		{127}
+	sev
+	strexb		r4, r12, [r7]
+	strexbne	r12, r4, [r8]
+	strexd		r4, r12, [r7]
+	strexdne	r12, r4, [r8]
+	strexh		r4, r12, [r7]
+	strexhne	r12, r4, [r8]
+	wfe
+	wfi
+	yield
+	# ARMV6Z instructions
+	smc 0xec31
+	smcne 0x13ce
+
+	# Add three nop instructions to ensure that the 
+	# output is 32-byte aligned as required for arm-aout.
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/arch7.d b/gas/testsuite/gas/arm/arch7.d
new file mode 100644
index 000000000000..992948b83314
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7.d
@@ -0,0 +1,77 @@
+#name: ARM V7 instructions
+#as: -march=armv7r
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> f6d6f008 	pli	\[r6, r8\]
+0+004 <[^>]*> f6d9f007 	pli	\[r9, r7\]
+0+008 <[^>]*> f6d0f101 	pli	\[r0, r1, lsl #2\]
+0+00c <[^>]*> f4d5f000 	pli	\[r5\]
+0+010 <[^>]*> f4d5ffff 	pli	\[r5, #4095\]
+0+014 <[^>]*> f455ffff 	pli	\[r5, #-4095\]
+0+018 <[^>]*> e320f0f0 	dbg	#0
+0+01c <[^>]*> e320f0ff 	dbg	#15
+0+020 <[^>]*> f57ff05f 	dmb	sy
+0+024 <[^>]*> f57ff05f 	dmb	sy
+0+028 <[^>]*> f57ff04f 	dsb	sy
+0+02c <[^>]*> f57ff04f 	dsb	sy
+0+030 <[^>]*> f57ff047 	dsb	un
+0+034 <[^>]*> f57ff04e 	dsb	st
+0+038 <[^>]*> f57ff046 	dsb	unst
+0+03c <[^>]*> f57ff06f 	isb	sy
+0+040 <[^>]*> f57ff06f 	isb	sy
+0+044 <[^>]*> f916 f008 	pli	\[r6, r8\]
+0+048 <[^>]*> f919 f007 	pli	\[r9, r7\]
+0+04c <[^>]*> f910 f021 	pli	\[r0, r1, lsl #2\]
+0+050 <[^>]*> f995 f000 	pli	\[r5\]
+0+054 <[^>]*> f995 ffff 	pli	\[r5, #4095\]
+0+058 <[^>]*> f915 fcff 	pli	\[r5, #-255\]
+0+05c <[^>]*> f99f ffff 	pli	\[pc, #4095\]	; 0000105f <[^>]*>
+0+060 <[^>]*> f91f ffff 	pli	\[pc, #-4095\]	; fffff065 <[^>]*>
+0+064 <[^>]*> f3af 80f0 	dbg	#0
+0+068 <[^>]*> f3af 80ff 	dbg	#15
+0+06c <[^>]*> f3bf 8f5f 	dmb	sy
+0+070 <[^>]*> f3bf 8f5f 	dmb	sy
+0+074 <[^>]*> f3bf 8f4f 	dsb	sy
+0+078 <[^>]*> f3bf 8f4f 	dsb	sy
+0+07c <[^>]*> f3bf 8f47 	dsb	un
+0+080 <[^>]*> f3bf 8f4e 	dsb	st
+0+084 <[^>]*> f3bf 8f46 	dsb	unst
+0+088 <[^>]*> f3bf 8f6f 	isb	sy
+0+08c <[^>]*> f3bf 8f6f 	isb	sy
+0+090 <[^>]*> fb99 f6fc 	sdiv	r6, r9, ip
+0+094 <[^>]*> fb96 f9f3 	sdiv	r9, r6, r3
+0+098 <[^>]*> fbb6 f9f3 	udiv	r9, r6, r3
+0+09c <[^>]*> fbb9 f6fc 	udiv	r6, r9, ip
+# V7M APSR has the same encoding as V7A CPSR_f
+0+0a0 <[^>]*> f3ef 8000 	mrs	r0, (CPSR|APSR)
+0+0a4 <[^>]*> f3ef 8001 	mrs	r0, IAPSR
+0+0a8 <[^>]*> f3ef 8002 	mrs	r0, EAPSR
+0+0ac <[^>]*> f3ef 8003 	mrs	r0, PSR
+0+0b0 <[^>]*> f3ef 8005 	mrs	r0, IPSR
+0+0b4 <[^>]*> f3ef 8006 	mrs	r0, EPSR
+0+0b8 <[^>]*> f3ef 8007 	mrs	r0, IEPSR
+0+0bc <[^>]*> f3ef 8008 	mrs	r0, MSP
+0+0c0 <[^>]*> f3ef 8009 	mrs	r0, PSP
+0+0c4 <[^>]*> f3ef 8010 	mrs	r0, PRIMASK
+0+0c8 <[^>]*> f3ef 8011 	mrs	r0, BASEPRI
+0+0cc <[^>]*> f3ef 8012 	mrs	r0, BASEPRI_MASK
+0+0d0 <[^>]*> f3ef 8013 	mrs	r0, FAULTMASK
+0+0d4 <[^>]*> f3ef 8014 	mrs	r0, CONTROL
+0+0d8 <[^>]*> f380 8800 	msr	(CPSR_f|APSR), r0
+0+0dc <[^>]*> f380 8801 	msr	IAPSR, r0
+0+0e0 <[^>]*> f380 8802 	msr	EAPSR, r0
+0+0e4 <[^>]*> f380 8803 	msr	PSR, r0
+0+0e8 <[^>]*> f380 8805 	msr	IPSR, r0
+0+0ec <[^>]*> f380 8806 	msr	EPSR, r0
+0+0f0 <[^>]*> f380 8807 	msr	IEPSR, r0
+0+0f4 <[^>]*> f380 8808 	msr	MSP, r0
+0+0f8 <[^>]*> f380 8809 	msr	PSP, r0
+0+0fc <[^>]*> f380 8810 	msr	PRIMASK, r0
+0+100 <[^>]*> f380 8811 	msr	BASEPRI, r0
+0+104 <[^>]*> f380 8812 	msr	BASEPRI_MASK, r0
+0+108 <[^>]*> f380 8813 	msr	FAULTMASK, r0
+0+10c <[^>]*> f380 8814 	msr	CONTROL, r0
diff --git a/gas/testsuite/gas/arm/arch7.s b/gas/testsuite/gas/arm/arch7.s
new file mode 100644
index 000000000000..9b30aa27cb12
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7.s
@@ -0,0 +1,79 @@
+	# ARMV7 instructions
+	.text
+	.arch armv7r
+label1:
+	pli	[r6, r8]
+	pli	[r9, r7]
+	pli	[r0, r1, lsl #2]
+	pli	[r5]
+	pli	[r5, #4095]
+	pli	[r5, #-4095]
+
+	dbg	#0
+	dbg	#15
+	dmb
+	dmb	sy
+	dsb
+	dsb	sy
+	dsb	un
+	dsb	st
+	dsb	unst
+	isb
+	isb	sy
+	.thumb
+	.thumb_func
+label2:
+	pli	[r6, r8]
+	pli	[r9, r7]
+	pli	[r0, r1, lsl #2]
+	pli	[r5]
+	pli	[r5, #4095]
+	pli	[r5, #-255]
+	pli	[pc, #4095]
+	pli	[pc, #-4095]
+
+	dbg	#0
+	dbg	#15
+	dmb
+	dmb	sy
+	dsb
+	dsb	sy
+	dsb	un
+	dsb	st
+	dsb	unst
+	isb
+	isb	sy
+
+	sdiv	r6, r9, r12
+	sdiv	r9, r6, r3
+	udiv	r9, r6, r3
+	udiv	r6, r9, r12
+	.arch armv7m
+	mrs	r0, apsr
+	mrs	r0, iapsr
+	mrs	r0, eapsr
+	mrs	r0, psr
+	mrs	r0, ipsr
+	mrs	r0, epsr
+	mrs	r0, iepsr
+	mrs	r0, msp
+	mrs	r0, psp
+	mrs	r0, primask
+	mrs	r0, basepri
+	mrs	r0, basepri_max
+	mrs	r0, faultmask
+	mrs	r0, control
+	msr	apsr, r0
+	msr	iapsr, r0
+	msr	eapsr, r0
+	msr	psr, r0
+	msr	ipsr, r0
+	msr	epsr, r0
+	msr	iepsr, r0
+	msr	msp, r0
+	msr	psp, r0
+	msr	primask, r0
+	msr	basepri, r0
+	msr	basepri_max, r0
+	msr	faultmask, r0
+	msr	control, r0
diff --git a/gas/testsuite/gas/arm/arch7m-bad.d b/gas/testsuite/gas/arm/arch7m-bad.d
new file mode 100644
index 000000000000..b7a3336cb300
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid V7M instructions
+#as: -march=armv7m
+#error-output: arch7m-bad.l
+
diff --git a/gas/testsuite/gas/arm/arch7m-bad.l b/gas/testsuite/gas/arm/arch7m-bad.l
new file mode 100644
index 000000000000..c962dacdf03d
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:5: Error: selected processor does not support 'A' form of this instruction -- `cpsie a'
+[^:]*:6: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie i,#0x10'
+[^:]*:7: Error: selected processor does not support `cps #0x10'
+
diff --git a/gas/testsuite/gas/arm/arch7m-bad.s b/gas/testsuite/gas/arm/arch7m-bad.s
new file mode 100644
index 000000000000..78ff86495e92
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch7m-bad.s
@@ -0,0 +1,7 @@
+	.text
+	.thumb
+	.thumb_func
+label:
+	cpsie a
+	cpsie i, #0x10
+	cps #0x10
diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d
index 8bb7703d1a1b..1dbaad3a714f 100644
--- a/gas/testsuite/gas/arm/archv6.d
+++ b/gas/testsuite/gas/arm/archv6.d
@@ -64,8 +64,8 @@ Disassembly of section .text:
 0+0e0 <[^>]*> 16a42475 ?	sxtabne	r2, r4, r5, ROR #8
 0+0e4 <[^>]*> e6142f37 ?	saddaddx	r2, r4, r7
 0+0e8 <[^>]*> 16142f37 ?	saddaddxne	r2, r4, r7
-0+0ec <[^>]*> e68210b3 ?	sel	r1, r2, r3
-0+0f0 <[^>]*> 168210b3 ?	selne	r1, r2, r3
+0+0ec <[^>]*> e6821fb3 ?	sel	r1, r2, r3
+0+0f0 <[^>]*> 16821fb3 ?	selne	r1, r2, r3
 0+0f4 <[^>]*> f1010200 ?	setend	be
 0+0f8 <[^>]*> f1010000 ?	setend	le
 0+0fc <[^>]*> e6342f17 ?	shadd16	r2, r4, r7
diff --git a/gas/testsuite/gas/arm/archv6t2-bad.d b/gas/testsuite/gas/arm/archv6t2-bad.d
new file mode 100644
index 000000000000..9b8e1b901512
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv6t2-bad.d
@@ -0,0 +1,3 @@
+#name: Invalid V6T2 instructions
+#as: -march=armv6t2
+#error-output: archv6t2-bad.l
diff --git a/gas/testsuite/gas/arm/archv6t2-bad.l b/gas/testsuite/gas/arm/archv6t2-bad.l
new file mode 100644
index 000000000000..0f00db37b2b8
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv6t2-bad.l
@@ -0,0 +1,40 @@
+[^:]*: Assembler messages:
+[^:]*:6: Error: r15 not allowed here -- `bfc pc,#0,#1'
+[^:]*:7: Error: r15 not allowed here -- `bfi pc,r0,#0,#1'
+[^:]*:8: Error: r15 not allowed here -- `movw pc,#0'
+[^:]*:9: Error: r15 not allowed here -- `movt pc,#0'
+[^:]*:12: Error: immediate value out of range -- `bfc r0,#0,#0'
+[^:]*:13: Error: immediate value out of range -- `bfc r0,#32,#0'
+[^:]*:14: Error: immediate value out of range -- `bfc r0,#0,#33'
+[^:]*:15: Error: immediate value out of range -- `bfc r0,#33,#1'
+[^:]*:16: Error: immediate value out of range -- `bfc r0,#32,#1'
+[^:]*:17: Error: bit-field extends past end of register -- `bfc r0,#28,#10'
+[^:]*:19: Error: immediate value out of range -- `bfi r0,r1,#0,#0'
+[^:]*:20: Error: immediate value out of range -- `bfi r0,r1,#32,#0'
+[^:]*:21: Error: immediate value out of range -- `bfi r0,r1,#0,#33'
+[^:]*:22: Error: immediate value out of range -- `bfi r0,r1,#33,#1'
+[^:]*:23: Error: immediate value out of range -- `bfi r0,r1,#32,#1'
+[^:]*:24: Error: bit-field extends past end of register -- `bfi r0,r1,#28,#10'
+[^:]*:26: Error: immediate value out of range -- `sbfx r0,r1,#0,#0'
+[^:]*:27: Error: immediate value out of range -- `sbfx r0,r1,#32,#0'
+[^:]*:28: Error: immediate value out of range -- `sbfx r0,r1,#0,#33'
+[^:]*:29: Error: immediate value out of range -- `sbfx r0,r1,#33,#1'
+[^:]*:30: Error: immediate value out of range -- `sbfx r0,r1,#32,#1'
+[^:]*:31: Error: bit-field extends past end of register -- `sbfx r0,r1,#28,#10'
+[^:]*:33: Error: immediate value out of range -- `ubfx r0,r1,#0,#0'
+[^:]*:34: Error: immediate value out of range -- `ubfx r0,r1,#32,#0'
+[^:]*:35: Error: immediate value out of range -- `ubfx r0,r1,#0,#33'
+[^:]*:36: Error: immediate value out of range -- `ubfx r0,r1,#33,#1'
+[^:]*:37: Error: immediate value out of range -- `ubfx r0,r1,#32,#1'
+[^:]*:38: Error: bit-field extends past end of register -- `ubfx r0,r1,#28,#10'
+[^:]*:41: Error: immediate value out of range -- `bfi r0,#1,#2,#3'
+[^:]*:44: Error: immediate value out of range -- `movt r0,#65537'
+[^:]*:45: Error: immediate value out of range -- `movw r0,#65537'
+[^:]*:46: Error: immediate value out of range -- `movt r0,#-1'
+[^:]*:47: Error: immediate value out of range -- `movw r0,#-1'
+[^:]*:50: Warning: destination register same as write-back base
+[^:]*:51: Warning: destination register same as write-back base
+[^:]*:52: Warning: destination register same as write-back base
+[^:]*:53: Warning: source register same as write-back base
+[^:]*:59: Error: instruction does not accept this addressing mode -- `ldrex r0,r2'
+[^:]*:60: Error: instruction does not accept this addressing mode -- `strex r1,r0,r2'
diff --git a/gas/testsuite/gas/arm/archv6t2-bad.s b/gas/testsuite/gas/arm/archv6t2-bad.s
new file mode 100644
index 000000000000..af1397271b62
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv6t2-bad.s
@@ -0,0 +1,61 @@
+	@ We do not bother testing simple cases, e.g. immediates where
+	@ registers belong, trailing junk at end of line.
+	.text
+x:
+	@ pc not allowed
+	bfc	pc,#0,#1
+	bfi	pc,r0,#0,#1
+	movw	pc,#0
+	movt	pc,#0
+
+	@ bitfield range limits
+	bfc	r0,#0,#0
+	bfc	r0,#32,#0
+	bfc	r0,#0,#33
+	bfc	r0,#33,#1
+	bfc	r0,#32,#1
+	bfc	r0,#28,#10
+
+	bfi	r0,r1,#0,#0
+	bfi	r0,r1,#32,#0
+	bfi	r0,r1,#0,#33
+	bfi	r0,r1,#33,#1
+	bfi	r0,r1,#32,#1
+	bfi	r0,r1,#28,#10
+
+	sbfx	r0,r1,#0,#0
+	sbfx	r0,r1,#32,#0
+	sbfx	r0,r1,#0,#33
+	sbfx	r0,r1,#33,#1
+	sbfx	r0,r1,#32,#1
+	sbfx	r0,r1,#28,#10
+
+	ubfx	r0,r1,#0,#0
+	ubfx	r0,r1,#32,#0
+	ubfx	r0,r1,#0,#33
+	ubfx	r0,r1,#33,#1
+	ubfx	r0,r1,#32,#1
+	ubfx	r0,r1,#28,#10
+
+	@ bfi accepts only #0 in Rm position
+	bfi	r0,#1,#2,#3
+
+	@ mov16 range limits
+	movt	r0,#65537
+	movw	r0,#65537
+	movt	r0,#-1
+	movw	r0,#-1
+
+	@ ldsttv4 Rd == Rn (warning)
+	ldrht	r0,[r0]
+	ldrsbt	r0,[r0]
+	ldrsht	r0,[r0]
+	strht	r0,[r0]
+
+	@ Bug reported by user.  GAS used to issue an error message
+	@ "r15 not allowed here" for these two instructions because
+	@ it thought that the "r2" operand was a PC-relative branch
+	@ to a label called "r2".
+	ldrex	r0, r2
+	strex	r1, r0, r2
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/arm/archv6t2.d b/gas/testsuite/gas/arm/archv6t2.d
new file mode 100644
index 000000000000..8e8b0387a336
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv6t2.d
@@ -0,0 +1,51 @@
+#name: ARM V6T2 instructions
+#as: -march=armv6t2
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e7c00010 	bfi	r0, r0, #0, #1
+0+04 <[^>]+> 17c00010 	bfine	r0, r0, #0, #1
+0+08 <[^>]+> e7c09010 	bfi	r9, r0, #0, #1
+0+0c <[^>]+> e7c00019 	bfi	r0, r9, #0, #1
+0+10 <[^>]+> e7d10010 	bfi	r0, r0, #0, #18
+0+14 <[^>]+> e7d10890 	bfi	r0, r0, #17, #1
+0+18 <[^>]+> e7c0001f 	bfc	r0, #0, #1
+0+1c <[^>]+> e7c0001f 	bfc	r0, #0, #1
+0+20 <[^>]+> 17c0001f 	bfcne	r0, #0, #1
+0+24 <[^>]+> e7c0901f 	bfc	r9, #0, #1
+0+28 <[^>]+> e7d1001f 	bfc	r0, #0, #18
+0+2c <[^>]+> e7d1089f 	bfc	r0, #17, #1
+0+30 <[^>]+> e7a00050 	sbfx	r0, r0, #0, #1
+0+34 <[^>]+> 17a00050 	sbfxne	r0, r0, #0, #1
+0+38 <[^>]+> e7e00050 	ubfx	r0, r0, #0, #1
+0+3c <[^>]+> e7a09050 	sbfx	r9, r0, #0, #1
+0+40 <[^>]+> e7a00059 	sbfx	r0, r9, #0, #1
+0+44 <[^>]+> e7a008d0 	sbfx	r0, r0, #17, #1
+0+48 <[^>]+> e7b10050 	sbfx	r0, r0, #0, #18
+0+4c <[^>]+> e3ff0f30 	rbit	r0, r0
+0+50 <[^>]+> 13ff0f30 	rbitne	r0, r0
+0+54 <[^>]+> e3ff9f30 	rbit	r9, r0
+0+58 <[^>]+> e3ff0f39 	rbit	r0, r9
+0+5c <[^>]+> e0600090 	mls	r0, r0, r0, r0
+0+60 <[^>]+> 10600090 	mlsne	r0, r0, r0, r0
+0+64 <[^>]+> e0690090 	mls	r9, r0, r0, r0
+0+68 <[^>]+> e0600099 	mls	r0, r9, r0, r0
+0+6c <[^>]+> e0600990 	mls	r0, r0, r9, r0
+0+70 <[^>]+> e0609090 	mls	r0, r0, r0, r9
+0+74 <[^>]+> e3000000 	movw	r0, #0	; 0x0
+0+78 <[^>]+> e3400000 	movt	r0, #0	; 0x0
+0+7c <[^>]+> 13000000 	movwne	r0, #0	; 0x0
+0+80 <[^>]+> e3009000 	movw	r9, #0	; 0x0
+0+84 <[^>]+> e3000999 	movw	r0, #2457	; 0x999
+0+88 <[^>]+> e3090000 	movw	r0, #36864	; 0x9000
+0+8c <[^>]+> e0f900b0 	ldrht	r0, \[r9\]
+0+90 <[^>]+> e0f900f0 	ldrsht	r0, \[r9\]
+0+94 <[^>]+> e0f900d0 	ldrsbt	r0, \[r9\]
+0+98 <[^>]+> e0e900b0 	strht	r0, \[r9\]
+0+9c <[^>]+> 10f900b0 	ldrneht	r0, \[r9\]
+0+a0 <[^>]+> e0b090b9 	ldrht	r9, \[r0\], r9
+0+a4 <[^>]+> e03090b9 	ldrht	r9, \[r0\], -r9
+0+a8 <[^>]+> e0f099b9 	ldrht	r9, \[r0\], #153
+0+ac <[^>]+> e07099b9 	ldrht	r9, \[r0\], #-153
diff --git a/gas/testsuite/gas/arm/archv6t2.s b/gas/testsuite/gas/arm/archv6t2.s
new file mode 100644
index 000000000000..292f11cf5db2
--- /dev/null
+++ b/gas/testsuite/gas/arm/archv6t2.s
@@ -0,0 +1,55 @@
+	.text
+x:
+	bfi	r0, r0, #0, #1
+	bfine	r0, r0, #0, #1
+
+	bfi	r9, r0, #0, #1
+	bfi	r0, r9, #0, #1
+	bfi	r0, r0, #0, #18
+	bfi	r0, r0, #17, #1
+
+	bfi	r0, #0, #0, #1
+	bfc	r0, #0, #1
+	bfcne	r0, #0, #1
+	bfc	r9, #0, #1
+	bfc	r0, #0, #18
+	bfc	r0, #17, #1
+
+	sbfx	r0, r0, #0, #1
+	sbfxne	r0, r0, #0, #1
+	ubfx	r0, r0, #0, #1
+	sbfx	r9, r0, #0, #1
+	sbfx	r0, r9, #0, #1
+	sbfx	r0, r0, #17, #1
+	sbfx	r0, r0, #0, #18
+	
+	rbit	r0, r0
+	rbitne	r0, r0
+	rbit	r9, r0
+	rbit	r0, r9
+
+	mls	r0, r0, r0, r0
+	mlsne	r0, r0, r0, r0
+	mls	r9, r0, r0, r0
+	mls	r0, r9, r0, r0
+	mls	r0, r0, r9, r0
+	mls	r0, r0, r0, r9
+	
+	movw	r0, #0
+	movt	r0, #0
+	movwne	r0, #0
+	movw	r9, #0
+	movw	r0, #0x0999
+	movw	r0, #0x9000
+
+	@ for these, we must avoid write-back warnings
+	ldrht	r0, [r9]
+	ldrsht	r0, [r9]
+	ldrsbt	r0, [r9]
+	strht	r0, [r9]
+	ldrneht	r0, [r9]
+
+	ldrht	r9, [r0], r9
+	ldrht	r9, [r0], -r9
+	ldrht	r9, [r0], #0x99
+	ldrht	r9, [r0], #-0x99
diff --git a/gas/testsuite/gas/arm/arm.exp b/gas/testsuite/gas/arm/arm.exp
index e5ec8be41268..56aef3b869aa 100644
--- a/gas/testsuite/gas/arm/arm.exp
+++ b/gas/testsuite/gas/arm/arm.exp
@@ -1,106 +1,7 @@
 #
 # Some ARM tests
 #
-proc run_errors_test { name opts tname} {
-    global srcdir subdir
-    set testname "$tname"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&${name}.out"
-    if { [regexp_diff "${name}.out" "${file}.l"] } then {
-        fail $testname
-        verbose "output is [file_contents "${name}.out"]" 2
-        return
-    }
-    pass $testname
-}
-
-if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
-
-    if {[istarget *-wince-*]} then {
-	run_dump_test "wince_inst"
-	run_dump_test "wince_ldconst"
-	run_dump_test "wince_arm7t"
-	run_dump_test "wince_copro"
-    } else {
-	run_dump_test "inst"
-	run_dump_test "ldconst"
-	run_dump_test "arm7t"
-	run_dump_test "copro"
-    }
-
-    run_dump_test "armv1"
-
-    run_errors_test "armv1-bad" "-mcpu=arm7m" "ARM v1 errors"
-
-    gas_test "arm3.s" "-mcpu=arm3" $stdoptlist "Arm 3 instructions"
-
-    gas_test "arm6.s" "-mcpu=arm6" $stdoptlist "Arm 6 instructions"
-
-    gas_test "arm7dm.s" "-mcpu=arm7dm" $stdoptlist "Arm 7DM instructions"
-
-    if {! [istarget arm*-*-aout] && ![istarget arm-*-pe]} then {
-	# The arm-aout port does not support Thumb mode.
-	gas_test "thumb.s" "-mcpu=arm7t" $stdoptlist "Thumb instructions"
-    }
-
-    gas_test "arch4t.s" "-march=armv4t" $stdoptlist "Arm architecture 4t instructions"
-
-    run_dump_test "arch5tej"
-
-    gas_test "immed.s" "" $stdoptlist "immediate expressions"
-
-    gas_test "float.s" "-mcpu=arm7tdmi -mfpu=fpa" $stdoptlist "Core floating point instructions"
-
-    run_dump_test "fpa-monadic"
-
-    run_dump_test "fpa-dyadic"
-
-    run_dump_test "fpa-mem"
-
-    run_dump_test "vfp1xD"
-
-    run_dump_test "vfp1"
-
-    run_dump_test "vfp2"
-
-    run_errors_test "vfp-bad" "-mfpu=vfp" "VFP errors"
-
-    run_dump_test "xscale"
-
-    run_dump_test "adrl"
-    
-    run_errors_test "req" "-mcpu=arm7m" ".req errors"
-
-    run_dump_test "maverick"
-    
-    run_dump_test "archv6"
-
-    run_dump_test "thumbv6"
-
-    run_errors_test "r15-bad" "" "Invalid use of r15 errors"
-
-    if {[istarget *-*-elf*] || [istarget *-*-linux*]} then {
-	run_dump_test "pic"
-
-	run_dump_test "mapping"
-    }
-
-    gas_test "offset.s" "" $stdoptlist "OFFSET_IMM regression"
-
-    run_errors_test "undefined" "" "Undefined local label error"
-}
-
-# Not all arm targets are bi-endian, so only run this test on ones
-# we know that are.  FIXME: We should probably also key off armeb/armel.
-
-if [istarget arm-*-pe] {
-    run_dump_test "le-fpconst"
-
-    # Since big-endian numbers have the normal format, this doesn't exist.
-    #run_dump_test "be-fpconst"
-}
 
-if [istarget xscale-*] {
-    run_dump_test "iwmmxt"
-    run_errors_test "iwmmxt-bad" "-mcpu=iwmmxt" "iWMMXt errors"
+if {[istarget *arm*-*-*] || [istarget *xscale*-*-*]} {
+    run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
 }
diff --git a/gas/testsuite/gas/arm/arm3-bad.d b/gas/testsuite/gas/arm/arm3-bad.d
new file mode 100644
index 000000000000..29449b22193c
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm3-bad.d
@@ -0,0 +1,3 @@
+# name: ARM 3 errors
+# as: -mcpu=arm3
+# error-output: arm3-bad.l
diff --git a/gas/testsuite/gas/arm/arm3-bad.l b/gas/testsuite/gas/arm/arm3-bad.l
new file mode 100644
index 000000000000..d55a9b61512c
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm3-bad.l
@@ -0,0 +1,3 @@
+.*arm3-bad.s: Assembler messages:
+.*arm3-bad.s:4: Error: Rn must not overlap other operands -- `swp r0,r1,\[r0\]'
+.*arm3-bad.s:5: Error: Rn must not overlap other operands -- `swp r1,r0,\[r0\]'
diff --git a/gas/testsuite/gas/arm/arm3-bad.s b/gas/testsuite/gas/arm/arm3-bad.s
new file mode 100644
index 000000000000..d3415a044c56
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm3-bad.s
@@ -0,0 +1,7 @@
+	.text
+	.align 0
+l:
+	swp	r0, r1, [r0]
+	swp	r1, r0, [r0]
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/arm3.d b/gas/testsuite/gas/arm/arm3.d
new file mode 100644
index 000000000000..06323b1c0cdf
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm3.d
@@ -0,0 +1,11 @@
+# name: ARM 3 instructions
+# as: -mcpu=arm3
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0 <[^>]*> e1080091 ?	swp	r0, r1, \[r8\]
+0+4 <[^>]*> e1423093 ?	swpb	r3, r3, \[r2\]
+0+8 <[^>]*> a1454091 ?	swpgeb	r4, r1, \[r5\]
+0+c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/arm3.s b/gas/testsuite/gas/arm/arm3.s
index ebcf915ccb13..b3fd794cd9f7 100644
--- a/gas/testsuite/gas/arm/arm3.s
+++ b/gas/testsuite/gas/arm/arm3.s
@@ -1,6 +1,7 @@
-.text
-.align 0
+	.text
+	.align 0
+l:
 	swp	r0, r1, [r8]
-	swpb	r2, r3, [r3]
-	swpgeb	r4, r1, [r4]
-
+	swpb	r3, r3, [r2]
+	swpgeb	r4, r1, [r5]
+	nop
diff --git a/gas/testsuite/gas/arm/arm6.d b/gas/testsuite/gas/arm/arm6.d
new file mode 100644
index 000000000000..3fc0de8198ba
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm6.d
@@ -0,0 +1,19 @@
+# name: ARM 6 instructions
+# as: -mcpu=arm6
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e10f8000 ?	mrs	r8, CPSR
+0+04 <[^>]+> e14f2000 ?	mrs	r2, SPSR
+0+08 <[^>]+> e129f001 ?	msr	CPSR_fc, r1
+0+0c <[^>]+> 1328f20f ?	msrne	CPSR_f, #-268435456	; 0xf0000000
+0+10 <[^>]+> e168f008 ?	msr	SPSR_f, r8
+0+14 <[^>]+> e169f009 ?	msr	SPSR_fc, r9
+0+18 <[^>]+> e10f8000 ?	mrs	r8, CPSR
+0+1c <[^>]+> e14f2000 ?	mrs	r2, SPSR
+0+20 <[^>]+> e129f001 ?	msr	CPSR_fc, r1
+0+24 <[^>]+> 1328f20f ?	msrne	CPSR_f, #-268435456	; 0xf0000000
+0+28 <[^>]+> e168f008 ?	msr	SPSR_f, r8
+0+2c <[^>]+> e169f009 ?	msr	SPSR_fc, r9
diff --git a/gas/testsuite/gas/arm/arm6.s b/gas/testsuite/gas/arm/arm6.s
index e82837f71b81..1883ebad7b87 100644
--- a/gas/testsuite/gas/arm/arm6.s
+++ b/gas/testsuite/gas/arm/arm6.s
@@ -1,6 +1,6 @@
-.text
-.align 0
-	
+	.text
+	.align 0
+l:
 	mrs	r8, cpsr
 	mrs	r2, spsr
 
@@ -16,4 +16,3 @@
 	msrne	CPSR_flg, #0xf0000000
 	msr	SPSR_flg, r8
 	msr	SPSR_all, r9
-
diff --git a/gas/testsuite/gas/arm/arm7dm.d b/gas/testsuite/gas/arm/arm7dm.d
new file mode 100644
index 000000000000..ef47ca6c6689
--- /dev/null
+++ b/gas/testsuite/gas/arm/arm7dm.d
@@ -0,0 +1,19 @@
+# name: ARM 7DM instructions
+# as: -mcpu=arm7dm
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e0c10392 ?	smull	r0, r1, r2, r3
+0+04 <[^>]+> e0810392 ?	umull	r0, r1, r2, r3
+0+08 <[^>]+> e0e10392 ?	smlal	r0, r1, r2, r3
+0+0c <[^>]+> e0a10394 ?	umlal	r0, r1, r4, r3
+0+10 <[^>]+> 10c10493 ?	smullne	r0, r1, r3, r4
+0+14 <[^>]+> e0d01b99 ?	smulls	r1, r0, r9, fp
+0+18 <[^>]+> 00b92994 ?	umlaleqs	r2, r9, r4, r9
+0+1c <[^>]+> a0eaee98 ?	smlalge	lr, sl, r8, lr
+0+20 <[^>]+> e322f000 ?	msr	CPSR_x, #0	; 0x0
+0+24 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+28 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+2c <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/arm7dm.s b/gas/testsuite/gas/arm/arm7dm.s
index 99eaa9fd5125..ee62e8c89346 100644
--- a/gas/testsuite/gas/arm/arm7dm.s
+++ b/gas/testsuite/gas/arm/arm7dm.s
@@ -1,6 +1,6 @@
-.text
-.align 0
-	
+	.text
+	.align 0
+l:
 	smull	r0, r1, r2, r3
 	umull	r0, r1, r2, r3
 	smlal	r0, r1, r2, r3
@@ -11,4 +11,10 @@
 	umlaleqs r2, r9, r4, r9
 	smlalge r14, r10, r8, r14
 
-	msr	CPSR_x, #0	@ This used to be illegal, but rev 2 of the ARM ARM allows it.
+	@ This used to be illegal, but rev 2 of the ARM ARM allows it.
+	msr	CPSR_x, #0
+
+	@ padding for a.out's sake
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/arm7t.d b/gas/testsuite/gas/arm/arm7t.d
index 768ce139c9e0..17e4e9d4fb5e 100644
--- a/gas/testsuite/gas/arm/arm7t.d
+++ b/gas/testsuite/gas/arm/arm7t.d
@@ -1,4 +1,4 @@
-#objdump: -Dr --prefix-addresses --show-raw-insn
+#objdump: -dr --prefix-addresses --show-raw-insn
 #name: ARM arm7t
 #as: -mcpu=arm7t -EL
 
diff --git a/gas/testsuite/gas/arm/armv1-bad.d b/gas/testsuite/gas/arm/armv1-bad.d
new file mode 100644
index 000000000000..f6f1454bfc3e
--- /dev/null
+++ b/gas/testsuite/gas/arm/armv1-bad.d
@@ -0,0 +1,3 @@
+#name: ARM v1 errors
+#as: -mcpu=arm7m
+#error-output: armv1-bad.l
diff --git a/gas/testsuite/gas/arm/armv1-bad.l b/gas/testsuite/gas/arm/armv1-bad.l
index 19a7e9a216df..423672c59b44 100644
--- a/gas/testsuite/gas/arm/armv1-bad.l
+++ b/gas/testsuite/gas/arm/armv1-bad.l
@@ -1,12 +1,9 @@
 [^:]*: Assembler messages:
 [^:]*:4: Error: invalid pseudo operation -- `str r0,=0x00ff0000'
 [^:]*:5: Error: bad expression -- `ldr r0,{r1}'
-[^:]*:6: Error: address offset too large -- `ldr r0,\[r1,#4096\]'
-[^:]*:7: Error: address offset too large -- `ldr r0,\[r1,#-4096\]'
-[^:]*:8: Error: invalid constant -- `mov r0,#0x1ff'
-[^:]*:9: Error: bad instruction `cmpl r0,r0'
-[^:]*:10: Error: selected processor does not support `strh r0,\[r1\]'
-[^:]*:11: Warning: writeback of base register is UNPREDICTABLE
-[^:]*:12: Warning: writeback of base register when in register list is UNPREDICTABLE
-[^:]*:13: Warning: writeback of base register is UNPREDICTABLE
-[^:]*:15: Warning: if writeback register is in list, it must be the lowest reg in the list
+[^:]*:6: Error: bad instruction `cmpl r0,r0'
+[^:]*:7: Error: selected processor does not support `strh r0,\[r1\]'
+[^:]*:8: Warning: writeback of base register is UNPREDICTABLE
+[^:]*:9: Warning: writeback of base register when in register list is UNPREDICTABLE
+[^:]*:10: Warning: writeback of base register is UNPREDICTABLE
+[^:]*:12: Warning: if writeback register is in list, it must be the lowest reg in the list
diff --git a/gas/testsuite/gas/arm/armv1-bad.s b/gas/testsuite/gas/arm/armv1-bad.s
index 751aefe17039..7e5f68392646 100644
--- a/gas/testsuite/gas/arm/armv1-bad.s
+++ b/gas/testsuite/gas/arm/armv1-bad.s
@@ -3,9 +3,6 @@
 entry:
 	str	r0, =0x00ff0000
 	ldr	r0, {r1}
-	ldr	r0, [r1, #4096]
-	ldr	r0, [r1, #-4096]
-	mov	r0, #0x1ff
 	cmpl	r0, r0
 	strh	r0, [r1]
 	ldmfa	r4!, {r8, r9}^
diff --git a/gas/testsuite/gas/arm/armv1.d b/gas/testsuite/gas/arm/armv1.d
index f3b2c6b6c93e..4e4c91376179 100644
--- a/gas/testsuite/gas/arm/armv1.d
+++ b/gas/testsuite/gas/arm/armv1.d
@@ -43,7 +43,7 @@ Disassembly of section .text:
 0+84 <[^>]*> e1b00000 ?	movs	r0, r0
 0+88 <[^>]*> e1e00000 ?	mvn	r0, r0
 0+8c <[^>]*> e1f00000 ?	mvns	r0, r0
-0+90 <[^>]*> ef000000 ?	swi	0x00000000
+0+90 <[^>]*> ef000000 ?	(swi|svc)	0x00000000
 0+94 <[^>]*> e5900000 ?	ldr	r0, \[r0\]
 0+98 <[^>]*> e5d00000 ?	ldrb	r0, \[r0\]
 0+9c <[^>]*> e4b10000 ?	ldrt	r0, \[r1\]
diff --git a/gas/testsuite/gas/arm/bignum1.d b/gas/testsuite/gas/arm/bignum1.d
new file mode 100644
index 000000000000..cef2036cfa3f
--- /dev/null
+++ b/gas/testsuite/gas/arm/bignum1.d
@@ -0,0 +1,12 @@
+# name: bignums
+# as:
+# objdump: --full-contents
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+Contents of section .data:
+ 0000 [08]0000000 000000[08]0 11111111 11111111  \.\.\.\.\.\.\.\.\.\.\.\.\.\.\.\.
+# Ignore .ARM.attributes section
+#...
diff --git a/gas/testsuite/gas/arm/bignum1.s b/gas/testsuite/gas/arm/bignum1.s
new file mode 100644
index 000000000000..2b9d736427e3
--- /dev/null
+++ b/gas/testsuite/gas/arm/bignum1.s
@@ -0,0 +1,3 @@
+	.data
+	.8byte	-9223372036854775808
+	.8byte	1229782938247303441
diff --git a/gas/testsuite/gas/arm/blx-local.d b/gas/testsuite/gas/arm/blx-local.d
new file mode 100644
index 000000000000..e187536b3630
--- /dev/null
+++ b/gas/testsuite/gas/arm/blx-local.d
@@ -0,0 +1,15 @@
+#name: Local BLX instructions
+#objdump: -dr --prefix-addresses --show-raw-insn
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#as:
+
+# Test assembler resolution of blx instructions.
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+0+00 <[^>]*> fa000000 	blx	00+8 <foo>
+0+04 <[^>]*> fbffffff 	blx	00+a <foo2>
+0+08 <[^>]*> 46c0      	nop			\(mov r8, r8\)
+0+0a <[^>]*> 46c0      	nop			\(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/blx-local.s b/gas/testsuite/gas/arm/blx-local.s
new file mode 100644
index 000000000000..c85a562d90f8
--- /dev/null
+++ b/gas/testsuite/gas/arm/blx-local.s
@@ -0,0 +1,16 @@
+        .text
+	.arch armv5t
+        .arm
+one:
+        blx     foo
+        blx     foo2
+
+        .thumb
+        .type foo, %function
+        .thumb_func
+foo:
+        nop
+        .type foo2, %function
+        .thumb_func
+foo2:
+        nop
diff --git a/gas/testsuite/gas/arm/copro.d b/gas/testsuite/gas/arm/copro.d
index 469c1eeb60d0..5f5dd110e99a 100644
--- a/gas/testsuite/gas/arm/copro.d
+++ b/gas/testsuite/gas/arm/copro.d
@@ -22,7 +22,7 @@ Disassembly of section .text:
 0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
 0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
 0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
-0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
+0+03c <[^>]*> be228519 	mcrlt	5, 1, r8, cr2, cr9, \{0\}
 0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
 0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
 0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
diff --git a/gas/testsuite/gas/arm/eabi_attr_1.d b/gas/testsuite/gas/arm/eabi_attr_1.d
new file mode 100644
index 000000000000..0e97addb4946
--- /dev/null
+++ b/gas/testsuite/gas/arm/eabi_attr_1.d
@@ -0,0 +1,13 @@
+# as: -meabi=4
+# readelf: -A
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM1136JF-S"
+  Tag_CPU_arch: v6
+  Tag_ARM_ISA_use: Yes
+  Tag_ABI_VFP_args: VFP registers
+  Tag_compatibility: flag = 3, vendor = GNU
+  Tag_unknown_128: 1234 \(0x4d2\)
+  Tag_unknown_129: "bar"
diff --git a/gas/testsuite/gas/arm/eabi_attr_1.s b/gas/testsuite/gas/arm/eabi_attr_1.s
new file mode 100644
index 000000000000..3375acdb0771
--- /dev/null
+++ b/gas/testsuite/gas/arm/eabi_attr_1.s
@@ -0,0 +1,9 @@
+.text
+.cpu arm1136jf-s
+foo:
+bx lr
+.eabi_attribute 32, 3, "GNU"
+.eabi_attribute 28, 1
+.eabi_attribute 128, 1234
+.eabi_attribute 129, "bar"
+
diff --git a/gas/testsuite/gas/arm/el_segundo.d b/gas/testsuite/gas/arm/el_segundo.d
index 835e7a11adad..064c51f41a9b 100644
--- a/gas/testsuite/gas/arm/el_segundo.d
+++ b/gas/testsuite/gas/arm/el_segundo.d
@@ -1,33 +1,34 @@
+# name: El Segundo instructions
+# objdump: -dr --prefix-addresses --show-raw-insn
 
-el_segundo.o:     file format elf32-littlearm
+.*: +file format .*arm.*
 
-Disassembly of section .text:
-
-00000000 <main>:
-   0:	c1003281 	smlabbgt	r0, r1, r2, r3
-   4:	e1003281 	smlabb	r0, r1, r2, r3
-   8:	e10032a1 	smlatb	r0, r1, r2, r3
-   c:	e10032c1 	smlabt	r0, r1, r2, r3
-  10:	e10032e1 	smlatt	r0, r1, r2, r3
-  14:	c1203281 	smlawbgt	r0, r1, r2, r3
-  18:	e1203281 	smlawb	r0, r1, r2, r3
-  1c:	e12032c1 	smlawt	r0, r1, r2, r3
-  20:	c1410382 	smlalbbgt	r0, r1, r2, r3
-  24:	e1410382 	smlalbb	r0, r1, r2, r3
-  28:	e14103a2 	smlaltb	r0, r1, r2, r3
-  2c:	e14103c2 	smlalbt	r0, r1, r2, r3
-  30:	e14103e2 	smlaltt	r0, r1, r2, r3
-  34:	c1600281 	smulbbgt	r0, r1, r2
-  38:	e1600281 	smulbb	r0, r1, r2
-  3c:	e16002a1 	smultb	r0, r1, r2
-  40:	e16002c1 	smulbt	r0, r1, r2
-  44:	e16002e1 	smultt	r0, r1, r2
-  48:	c12002a1 	smulwbgt	r0, r1, r2
-  4c:	e12002a1 	smulwb	r0, r1, r2
-  50:	e12002e1 	smulwt	r0, r1, r2
-  54:	c1020051 	qaddgt	r0, r1, r2
-  58:	e1020051 	qadd	r0, r1, r2
-  5c:	e1420051 	qdadd	r0, r1, r2
-  60:	e1220051 	qsub	r0, r1, r2
-  64:	e1620051 	qdsub	r0, r1, r2
-  68:	e1220051 	qsub	r0, r1, r2
+Disassembly of section \.text:
+0+00 <[^>]+> c1003281 	smlabbgt	r0, r1, r2, r3
+0+04 <[^>]+> e1003281 	smlabb	r0, r1, r2, r3
+0+08 <[^>]+> e10032a1 	smlatb	r0, r1, r2, r3
+0+0c <[^>]+> e10032c1 	smlabt	r0, r1, r2, r3
+0+10 <[^>]+> e10032e1 	smlatt	r0, r1, r2, r3
+0+14 <[^>]+> c1203281 	smlawbgt	r0, r1, r2, r3
+0+18 <[^>]+> e1203281 	smlawb	r0, r1, r2, r3
+0+1c <[^>]+> e12032c1 	smlawt	r0, r1, r2, r3
+0+20 <[^>]+> c1410382 	smlalbbgt	r0, r1, r2, r3
+0+24 <[^>]+> e1410382 	smlalbb	r0, r1, r2, r3
+0+28 <[^>]+> e14103a2 	smlaltb	r0, r1, r2, r3
+0+2c <[^>]+> e14103c2 	smlalbt	r0, r1, r2, r3
+0+30 <[^>]+> e14103e2 	smlaltt	r0, r1, r2, r3
+0+34 <[^>]+> c1600281 	smulbbgt	r0, r1, r2
+0+38 <[^>]+> e1600281 	smulbb	r0, r1, r2
+0+3c <[^>]+> e16002a1 	smultb	r0, r1, r2
+0+40 <[^>]+> e16002c1 	smulbt	r0, r1, r2
+0+44 <[^>]+> e16002e1 	smultt	r0, r1, r2
+0+48 <[^>]+> c12002a1 	smulwbgt	r0, r1, r2
+0+4c <[^>]+> e12002a1 	smulwb	r0, r1, r2
+0+50 <[^>]+> e12002e1 	smulwt	r0, r1, r2
+0+54 <[^>]+> c1020051 	qaddgt	r0, r1, r2
+0+58 <[^>]+> e1020051 	qadd	r0, r1, r2
+0+5c <[^>]+> e1420051 	qdadd	r0, r1, r2
+0+60 <[^>]+> e1220051 	qsub	r0, r1, r2
+0+64 <[^>]+> e1620051 	qdsub	r0, r1, r2
+0+68 <[^>]+> e1220051 	qsub	r0, r1, r2
+0+6c <[^>]+> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/el_segundo.s b/gas/testsuite/gas/arm/el_segundo.s
index 9f403a10d565..2111b5e718e2 100644
--- a/gas/testsuite/gas/arm/el_segundo.s
+++ b/gas/testsuite/gas/arm/el_segundo.s
@@ -1,23 +1,9 @@
 # el_segundo.s
 #
 # Tests that we generate the right code for v5e instructions.
-# This is not a functional test, although it can be linked.
-# (The section at the rear is non-Coyanosa stuff for comparison.)
-# To verify a compiler, do:
-#	<gcc build area>/gcc/as el_segundo.s -o _temp.o
-#	<gcc build area>/binutils/objdump -dr _temp.o >! _temp.d
-#	diff _temp.d el_segundo.d
-
-	.section	.rdata
-	.align	0
-.LC0:
-	.ascii	"some data\000"
-
 	.text
 	.global main
-#	.type main,function
 	.align	0
-
 main:
 	smlabbgt r0,r1,r2,r3
 	smlabb r0,r1,r2,r3
@@ -52,3 +38,6 @@ main:
 	qsub r0,r1,r2
 	qdsub r0,r1,r2
 	qsub r0,r1,r2
+
+	@ padding for a.out's sake
+	nop
diff --git a/gas/testsuite/gas/arm/float.d b/gas/testsuite/gas/arm/float.d
new file mode 100644
index 000000000000..c9754b20f6b9
--- /dev/null
+++ b/gas/testsuite/gas/arm/float.d
@@ -0,0 +1,131 @@
+# name: Core floating point instructions
+# as: -mcpu=arm7tdmi -mfpu=fpa
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> ee088101 ?	mvfe	f0, f1
+0+004 <[^>]+> 0e08b105 ?	mvfeqe	f3, f5
+0+008 <[^>]+> 0e00c189 ?	mvfeqd	f4, #1\.0
+0+00c <[^>]+> ee00c107 ?	mvfs	f4, f7
+0+010 <[^>]+> ee008121 ?	mvfsp	f0, f1
+0+014 <[^>]+> ee00b1c4 ?	mvfdm	f3, f4
+0+018 <[^>]+> ee08f167 ?	mvfez	f7, f7
+0+01c <[^>]+> ee09010a ?	adfe	f0, f1, #2\.0
+0+020 <[^>]+> 0e0a110e ?	adfeqe	f1, f2, #0\.5
+0+024 <[^>]+> ee043145 ?	adfsm	f3, f4, f5
+0+028 <[^>]+> ee20018a ?	sufd	f0, f0, #2\.0
+0+02c <[^>]+> ee22110f ?	sufs	f1, f2, #10\.0
+0+030 <[^>]+> 1e2c3165 ?	sufneez	f3, f4, f5
+0+034 <[^>]+> ee311108 ?	rsfs	f1, f1, #0\.0
+0+038 <[^>]+> ee3031ad ?	rsfdp	f3, f0, #5\.0
+0+03c <[^>]+> de367180 ?	rsfled	f7, f6, f0
+0+040 <[^>]+> ee100180 ?	mufd	f0, f0, f0
+0+044 <[^>]+> ee1a116b ?	mufez	f1, f2, #3\.0
+0+048 <[^>]+> ee10010c ?	mufs	f0, f0, #4\.0
+0+04c <[^>]+> ee400189 ?	dvfd	f0, f0, #1\.0
+0+050 <[^>]+> ee49016f ?	dvfez	f0, f1, #10\.0
+0+054 <[^>]+> 4e443145 ?	dvfmism	f3, f4, f5
+0+058 <[^>]+> ee59010f ?	rdfe	f0, f1, #10\.0
+0+05c <[^>]+> ee573109 ?	rdfs	f3, f7, #1\.0
+0+060 <[^>]+> 3e5441a3 ?	rdfccdp	f4, f4, f3
+0+064 <[^>]+> ee620183 ?	powd	f0, f2, f3
+0+068 <[^>]+> ee63110f ?	pows	f1, f3, #10\.0
+0+06c <[^>]+> 2e6f4169 ?	powcsez	f4, f7, #1\.0
+0+070 <[^>]+> ee767107 ?	rpws	f7, f6, f7
+0+074 <[^>]+> 0e710182 ?	rpweqd	f0, f1, f2
+0+078 <[^>]+> ee7a2143 ?	rpwem	f2, f2, f3
+0+07c <[^>]+> ee82118b ?	rmfd	f1, f2, #3\.0
+0+080 <[^>]+> 6e843104 ?	rmfvss	f3, f4, f4
+0+084 <[^>]+> ee8f4120 ?	rmfep	f4, f7, f0
+0+088 <[^>]+> ee910102 ?	fmls	f0, f1, f2
+0+08c <[^>]+> 0e931105 ?	fmleqs	f1, f3, f5
+0+090 <[^>]+> 5e964160 ?	fmlplsz	f4, f6, f0
+0+094 <[^>]+> eea3110f ?	fdvs	f1, f3, #10\.0
+0+098 <[^>]+> eea10122 ?	fdvsp	f0, f1, f2
+0+09c <[^>]+> 2ea44144 ?	fdvcssm	f4, f4, f4
+0+0a0 <[^>]+> eeb11109 ?	frds	f1, f1, #1\.0
+0+0a4 <[^>]+> ceb12100 ?	frdgts	f2, f1, f0
+0+0a8 <[^>]+> ceb44165 ?	frdgtsz	f4, f4, f5
+0+0ac <[^>]+> eec10182 ?	pold	f0, f1, f2
+0+0b0 <[^>]+> eec6416b ?	polsz	f4, f6, #3\.0
+0+0b4 <[^>]+> 0ece5107 ?	poleqe	f5, f6, f7
+0+0b8 <[^>]+> ee108101 ?	mnfs	f0, f1
+0+0bc <[^>]+> ee10818b ?	mnfd	f0, #3\.0
+0+0c0 <[^>]+> ee18816c ?	mnfez	f0, #4\.0
+0+0c4 <[^>]+> 0e188165 ?	mnfeqez	f0, f5
+0+0c8 <[^>]+> ee108124 ?	mnfsp	f0, f4
+0+0cc <[^>]+> ee1091c7 ?	mnfdm	f1, f7
+0+0d0 <[^>]+> ee208181 ?	absd	f0, f1
+0+0d4 <[^>]+> ee20912b ?	abssp	f1, #3\.0
+0+0d8 <[^>]+> 0e28c105 ?	abseqe	f4, f5
+0+0dc <[^>]+> ee309102 ?	rnds	f1, f2
+0+0e0 <[^>]+> ee30b184 ?	rndd	f3, f4
+0+0e4 <[^>]+> 0e38e16c ?	rndeqez	f6, #4\.0
+0+0e8 <[^>]+> ee40d105 ?	sqts	f5, f5
+0+0ec <[^>]+> ee40e1a6 ?	sqtdp	f6, f6
+0+0f0 <[^>]+> 5e48f166 ?	sqtplez	f7, f6
+0+0f4 <[^>]+> ee50810f ?	logs	f0, #10\.0
+0+0f8 <[^>]+> ee58810f ?	loge	f0, #10\.0
+0+0fc <[^>]+> 1e5081e1 ?	lognedz	f0, f1
+0+100 <[^>]+> ee689102 ?	lgne	f1, f2
+0+104 <[^>]+> ee6091e3 ?	lgndz	f1, f3
+0+108 <[^>]+> 7e60b104 ?	lgnvcs	f3, f4
+0+10c <[^>]+> ee709103 ?	exps	f1, f3
+0+110 <[^>]+> ee78b14f ?	expem	f3, #10\.0
+0+114 <[^>]+> 5e70e187 ?	exppld	f6, f7
+0+118 <[^>]+> ee808181 ?	sind	f0, f1
+0+11c <[^>]+> ee809142 ?	sinsm	f1, f2
+0+120 <[^>]+> ce88c10d ?	singte	f4, #5\.0
+0+124 <[^>]+> ee909183 ?	cosd	f1, f3
+0+128 <[^>]+> ee98c145 ?	cosem	f4, f5
+0+12c <[^>]+> 1e90e1a1 ?	cosnedp	f6, f1
+0+130 <[^>]+> eea89105 ?	tane	f1, f5
+0+134 <[^>]+> eea0c167 ?	tansz	f4, f7
+0+138 <[^>]+> aea091ec ?	tangedz	f1, #4\.0
+0+13c <[^>]+> eeb8c105 ?	asne	f4, f5
+0+140 <[^>]+> eeb0e12e ?	asnsp	f6, #0\.5
+0+144 <[^>]+> 4eb0d1e5 ?	asnmidz	f5, f5
+0+148 <[^>]+> eec0d106 ?	acss	f5, f6
+0+14c <[^>]+> eec0e180 ?	acsd	f6, f0
+0+150 <[^>]+> 2ec8914e ?	acscsem	f1, #0\.5
+0+154 <[^>]+> eed88105 ?	atne	f0, f5
+0+158 <[^>]+> eed0916d ?	atnsz	f1, #5\.0
+0+15c <[^>]+> bed0b182 ?	atnltd	f3, f2
+0+160 <[^>]+> eee8d104 ?	urde	f5, f4
+0+164 <[^>]+> eef8e105 ?	nrme	f6, f5
+0+168 <[^>]+> 5ef0f1e5 ?	nrmpldz	f7, f5
+0+16c <[^>]+> ee008130 ?	fltsp	f0, r8
+0+170 <[^>]+> ee090110 ?	flte	f1, r0
+0+174 <[^>]+> 0e0571f0 ?	flteqdz	f5, r7
+0+178 <[^>]+> ee100111 ?	fix	r0, f1
+0+17c <[^>]+> ee101177 ?	fixz	r1, f7
+0+180 <[^>]+> 2e105155 ?	fixcsm	r5, f5
+0+184 <[^>]+> ee400110 ?	wfc	r0
+0+188 <[^>]+> ee201110 ?	wfs	r1
+0+18c <[^>]+> 0e302110 ?	rfseq	r2
+0+190 <[^>]+> ee504110 ?	rfc	r4
+0+194 <[^>]+> ee90f119 ?	cmf	f0, #1\.0
+0+198 <[^>]+> ee91f112 ?	cmf	f1, f2
+0+19c <[^>]+> 0e90f111 ?	cmfeq	f0, f1
+0+1a0 <[^>]+> eeb0f11b ?	cnf	f0, #3\.0
+0+1a4 <[^>]+> eeb1f11e ?	cnf	f1, #0\.5
+0+1a8 <[^>]+> 6eb3f114 ?	cnfvs	f3, f4
+0+1ac <[^>]+> eed0f111 ?	cmfe	f0, f1
+0+1b0 <[^>]+> 0ed1f112 ?	cmfeeq	f1, f2
+0+1b4 <[^>]+> 0ed3f11d ?	cmfeeq	f3, #5\.0
+0+1b8 <[^>]+> eef1f113 ?	cnfe	f1, f3
+0+1bc <[^>]+> 0ef3f114 ?	cnfeeq	f3, f4
+0+1c0 <[^>]+> 0ef4f117 ?	cnfeeq	f4, f7
+0+1c4 <[^>]+> eef4f11d ?	cnfe	f4, #5\.0
+0+1c8 <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
+0+1cc <[^>]+> ed900200 ?	lfm	f0, 4, \[r0\]
+0+1d0 <[^>]+> ed911210 ?	lfm	f1, 4, \[r1, #64\]
+0+1d4 <[^>]+> edae22ff ?	sfm	f2, 4, \[lr, #1020\]!
+0+1d8 <[^>]+> 0c68f2ff ?	sfmeq	f7, 3, \[r8\], #-1020
+0+1dc <[^>]+> eddf6200 ?	lfm	f6, 2, \[pc\]
+0+1e0 <[^>]+> eca8f203 ?	sfm	f7, 1, \[r8\], #12
+0+1e4 <[^>]+> 0d16520c ?	lfmeq	f5, 4, \[r6, #-48\]
+0+1e8 <[^>]+> 1d42c209 ?	sfmne	f4, 3, \[r2, #-36\]
+0+1ec <[^>]+> 1d62c209 ?	sfmne	f4, 3, \[r2, #-36\]!
diff --git a/gas/testsuite/gas/arm/float.s b/gas/testsuite/gas/arm/float.s
index 48aee965cb2f..437d298ddd52 100644
--- a/gas/testsuite/gas/arm/float.s
+++ b/gas/testsuite/gas/arm/float.s
@@ -1,5 +1,6 @@
-.text
-.align 0
+	.text
+	.align 0
+l:
 	mvfe	f0, f1
 	mvfeqe	f3, f5
 	mvfeqd	f4, #1.0
diff --git a/gas/testsuite/gas/arm/fpa-mem.d b/gas/testsuite/gas/arm/fpa-mem.d
index bbe4cfa3dc8d..9b3a65670b54 100644
--- a/gas/testsuite/gas/arm/fpa-mem.d
+++ b/gas/testsuite/gas/arm/fpa-mem.d
@@ -30,5 +30,5 @@ Disassembly of section .text:
 0+4c <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
 0+50 <[^>]*> ed00020c ?	sfm	f0, 4, \[r0, #-48\]
 0+54 <[^>]*> ed800200 ?	sfm	f0, 4, \[r0\]
-0+58 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
-0+5c <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
+0+58 <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
+0+5c <[^>]*> 5d800100 ?	stfpls	f0, \[r0\]
diff --git a/gas/testsuite/gas/arm/fpa-mem.s b/gas/testsuite/gas/arm/fpa-mem.s
index dfc9b6564c43..bcb4ae3ae86a 100644
--- a/gas/testsuite/gas/arm/fpa-mem.s
+++ b/gas/testsuite/gas/arm/fpa-mem.s
@@ -25,7 +25,8 @@ F:
 	sfmfd	f0, 4, [r0]
 	sfmea	f0, 4, [r0]
 	
-	# Add two nop instructions to ensure that the
-	# output is 32-byte aligned as required for arm-aout.
-	nop
-	nop
+	# Test mnemonic that is ambiguous between infix and suffic
+	# condition codes
+	stfpls	f0, [r0]
+	.syntax unified
+	stfpls	f0, [r0]
diff --git a/gas/testsuite/gas/arm/immed.d b/gas/testsuite/gas/arm/immed.d
new file mode 100644
index 000000000000..62b7eb72e545
--- /dev/null
+++ b/gas/testsuite/gas/arm/immed.d
@@ -0,0 +1,16 @@
+# name: immediate expressions
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0000 <[^>]+> e3a00000 ?	mov	r0, #0	; 0x0
+0+0004 <[^>]+> e3e00003 ?	mvn	r0, #3	; 0x3
+0+0008 <[^>]+> e51f0010 ?	ldr	r0, \[pc, #-16\]	; 0+0 <[^>]+>
+0+000c <[^>]+> e51f0014 ?	ldr	r0, \[pc, #-20\]	; 0+0 <[^>]+>
+	\.\.\.
+0+1010 <[^>]+> e3a00008 ?	mov	r0, #8	; 0x8
+0+1014 <[^>]+> e59f00e4 ?	ldr	r0, \[pc, #228\]	; 0+1100 <[^>]+>
+0+1018 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+101c <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/immed.s b/gas/testsuite/gas/arm/immed.s
index 5d2092be18b6..400f628f3f35 100644
--- a/gas/testsuite/gas/arm/immed.s
+++ b/gas/testsuite/gas/arm/immed.s
@@ -9,3 +9,7 @@ bar:
 	.space 4096
 	mov	r0, #(. - bar - 8) & 0xff
 	ldr	r0, [pc, # (bar - . -8) & 0xff]
+
+	@ section padding for a.out's benefit
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/inst.d b/gas/testsuite/gas/arm/inst.d
index 6067fe97edee..fbf27b4ab8db 100644
--- a/gas/testsuite/gas/arm/inst.d
+++ b/gas/testsuite/gas/arm/inst.d
@@ -1,6 +1,8 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: ARM basic instructions
 #as: -mcpu=arm7m -EL
+# WinCE has its own version of this test.
+#skip: *-wince-*
 
 # Test the standard ARM instructions:
 
@@ -157,15 +159,15 @@ Disassembly of section .text:
 0+24c <[^>]*> e9020018 ?	stmdb	r2, {r3, r4}
 0+250 <[^>]*> e8830003 ?	stmia	r3, {r0, r1}
 0+254 <[^>]*> e9c40300 ?	stmib	r4, {r8, r9}\^
-0+258 <[^>]*> ef123456 ?	swi	0x00123456
-0+25c <[^>]*> 2f000033 ?	swics	0x00000033
-0+260 <[^>]*> ebfffffe ?	bl	0+260 <[^>]*>
+0+258 <[^>]*> ef123456 ?	(swi|svc)	0x00123456
+0+25c <[^>]*> 2f000033 ?	(swi|svc)cs	0x00000033
+0+260 <[^>]*> eb...... ?	bl	0[0123456789abcdef]+ <[^>]*>
 [		]*260:.*_wombat.*
-0+264 <[^>]*> 5bfffffe ?	blpl	0+264 <[^>]*>
-[		]*264:.*ARM.*hohum
-0+268 <[^>]*> eafffffe ?	b	0+268 <[^>]*>
+0+264 <[^>]*> 5b...... ?	blpl	0[0123456789abcdef]+ <[^>]*>
+[		]*264:.*ARM.*hohum.*
+0+268 <[^>]*> ea...... ?	b	0[0123456789abcdef]+ <[^>]*>
 [		]*268:.*_wibble.*
-0+26c <[^>]*> dafffffe ?	ble	0+26c <[^>]*>
+0+26c <[^>]*> da...... ?	ble	0[0123456789abcdef]+ <[^>]*>
 [		]*26c:.*testerfunc.*
 0+270 <[^>]*> e1a01102 ?	mov	r1, r2, lsl #2
 0+274 <[^>]*> e1a01002 ?	mov	r1, r2
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.d b/gas/testsuite/gas/arm/iwmmxt-bad.d
new file mode 100644
index 000000000000..6b44634c3332
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-bad.d
@@ -0,0 +1,3 @@
+#name: iWMMXt errors
+#as: -mcpu=iwmmxt
+#error-output: iwmmxt-bad.l
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.l b/gas/testsuite/gas/arm/iwmmxt-bad.l
index 66144aa8758a..65889380cf1b 100644
--- a/gas/testsuite/gas/arm/iwmmxt-bad.l
+++ b/gas/testsuite/gas/arm/iwmmxt-bad.l
@@ -1,9 +1,10 @@
 [^:]*: Assembler messages:
-[^:]*:1: Error: conditional execution not supported with control register
-[^:]*:2: Error: non-word size not supported with control register
-[^:]*:3: Error: non-word size not supported with control register
-[^:]*:4: Error: non-word size not supported with control register
-[^:]*:5: Error: conditional execution not supported with control register
-[^:]*:6: Error: non-word size not supported with control register
-[^:]*:7: Error: non-word size not supported with control register
-[^:]*:8: Error: non-word size not supported with control register
+[^:]*:1: Error: instruction cannot be conditional -- `wldrwgt wcgr0,\[r1\]'
+[^:]*:2: Error: iWMMXt data register expected -- `wldrb wcgr0,\[r1\]'
+[^:]*:3: Error: iWMMXt data register expected -- `wldrh wcgr0,\[r1\]'
+[^:]*:4: Error: iWMMXt data register expected -- `wldrd wcgr0,\[r1\]'
+[^:]*:5: Error: instruction cannot be conditional -- `wstrwgt wcgr0,\[r1\]'
+[^:]*:6: Error: iWMMXt data register expected -- `wstrb wcgr0,\[r1\]'
+[^:]*:7: Error: iWMMXt data register expected -- `wstrh wcgr0,\[r1\]'
+[^:]*:8: Error: iWMMXt data register expected -- `wstrd wcgr0,\[r1\]'
+[^:]*:9: Error: iWMMXt control register expected -- `tmcr wibble,r1'
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad.s b/gas/testsuite/gas/arm/iwmmxt-bad.s
index 0c30af10f53c..47d8d71f8656 100644
--- a/gas/testsuite/gas/arm/iwmmxt-bad.s
+++ b/gas/testsuite/gas/arm/iwmmxt-bad.s
@@ -6,3 +6,4 @@
 	wstrb	wcgr0,[r1]
 	wstrh	wcgr0,[r1]
 	wstrd	wcgr0,[r1]
+	tmcr	wibble,r1
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad2.d b/gas/testsuite/gas/arm/iwmmxt-bad2.d
new file mode 100644
index 000000000000..c8587a4cc08b
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-bad2.d
@@ -0,0 +1,3 @@
+#name: iWMMXt CoProcessor offset errors
+#as: -mcpu=iwmmxt
+#error-output: iwmmxt-bad2.l
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad2.l b/gas/testsuite/gas/arm/iwmmxt-bad2.l
new file mode 100644
index 000000000000..1a43ebcdfbcd
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-bad2.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: co-processor offset out of range
+[^:]*:2: Error: co-processor offset out of range
+[^:]*:3: Error: co-processor offset out of range
+[^:]*:4: Error: co-processor offset out of range
+[^:]*:5: Error: co-processor offset out of range
+[^:]*:6: Error: co-processor offset out of range
diff --git a/gas/testsuite/gas/arm/iwmmxt-bad2.s b/gas/testsuite/gas/arm/iwmmxt-bad2.s
new file mode 100644
index 000000000000..dc559a8927f6
--- /dev/null
+++ b/gas/testsuite/gas/arm/iwmmxt-bad2.s
@@ -0,0 +1,6 @@
+	wldrd   wr1, [r0, #3]
+        wstrd   wr1, [r0, #0x400]
+        wstrb   wr1, [r0, #0x100]
+        wstrh   wr1, [r0, #0x100]
+        wldrb   wr1, [r0, #-0x100]
+        wldrh   wr1, [r0, #-0x100]
diff --git a/gas/testsuite/gas/arm/iwmmxt.d b/gas/testsuite/gas/arm/iwmmxt.d
index 7225a6129f2a..494199d2bc45 100644
--- a/gas/testsuite/gas/arm/iwmmxt.d
+++ b/gas/testsuite/gas/arm/iwmmxt.d
@@ -46,7 +46,7 @@ Disassembly of section .text:
 0+98 <[^>]*> ee120184[ 	]+waddbus[ 	]+wr0, wr2, wr4
 0+9c <[^>]*> ee38618a[ 	]+waddbss[ 	]+wr6, wr8, wr10
 0+a0 <[^>]*> ee4ec18f[ 	]+waddh[ 	]+wr12, wr14, wr15
-0+a4 <[^>]*> fe5cd18b[ 	]+waddhusnv[ 	]+wr13, wr12, wr11
+0+a4 <[^>]*> de5cd18b[ 	]+waddhusle[ 	]+wr13, wr12, wr11
 0+a8 <[^>]*> 0e79a188[ 	]+waddhsseq[ 	]+wr10, wr9, wr8
 0+ac <[^>]*> 1e867185[ 	]+waddwne[ 	]+wr7, wr6, wr5
 0+b0 <[^>]*> ee934182[ 	]+waddwus[ 	]+wr4, wr3, wr2
@@ -74,7 +74,7 @@ Disassembly of section .text:
 0+108 <[^>]*> ed901024[ 	]+wldrb[ 	]+wr1, \[r0, #36\]
 0+10c <[^>]*> 0df12018[ 	]+wldrheq[ 	]+wr2, \[r1, #24\]!
 0+110 <[^>]*> 1cb23104[ 	]+wldrwne[ 	]+wr3, \[r2\], #16
-0+114 <[^>]*> 6dd34102[ 	]+wldrdvs[ 	]+wr4, \[r3, #8\]
+0+114 <[^>]*> 6d534153[ 	]+wldrdvs[ 	]+wr4, \[r3, #-332\]
 0+118 <[^>]*> fdb12105[ 	]+wldrw[ 	]+wcssf, \[r1, #20\]!
 0+11c <[^>]*> ee474109[ 	]+wmacu[ 	]+wr4, wr7, wr9
 0+120 <[^>]*> 2e6a810e[ 	]+wmacscs[ 	]+wr8, wr10, wr14
@@ -87,7 +87,7 @@ Disassembly of section .text:
 0+13c <[^>]*> 5e443165[ 	]+wmaxuhpl[ 	]+wr3, wr4, wr5
 0+140 <[^>]*> 4e643165[ 	]+wmaxshmi[ 	]+wr3, wr4, wr5
 0+144 <[^>]*> ae843165[ 	]+wmaxuwge[ 	]+wr3, wr4, wr5
-0+148 <[^>]*> fea43165[ 	]+wmaxswnv[ 	]+wr3, wr4, wr5
+0+148 <[^>]*> dea43165[ 	]+wmaxswle[ 	]+wr3, wr4, wr5
 0+14c <[^>]*> 3e1c416a[ 	]+wminubcc[ 	]+wr4, wr12, wr10
 0+150 <[^>]*> ee3c416a[ 	]+wminsb[ 	]+wr4, wr12, wr10
 0+154 <[^>]*> 7e5c416a[ 	]+wminuhvc[ 	]+wr4, wr12, wr10
@@ -115,7 +115,7 @@ Disassembly of section .text:
 0+1ac <[^>]*> ee00212a[ 	]+wsadb[ 	]+wr2, wr0, wr10
 0+1b0 <[^>]*> ee40212a[ 	]+wsadh[ 	]+wr2, wr0, wr10
 0+1b4 <[^>]*> ee10212a[ 	]+wsadbz[ 	]+wr2, wr0, wr10
-0+1b8 <[^>]*> fe50212a[ 	]+wsadhznv[ 	]+wr2, wr0, wr10
+0+1b8 <[^>]*> de50212a[ 	]+wsadhzle[ 	]+wr2, wr0, wr10
 0+1bc <[^>]*> 0ef941eb[ 	]+wshufheq[ 	]+wr4, wr9, #251
 0+1c0 <[^>]*> ee592044[ 	]+wsllh[ 	]+wr2, wr9, wr4
 0+1c4 <[^>]*> ee992044[ 	]+wsllw[ 	]+wr2, wr9, wr4
@@ -135,11 +135,11 @@ Disassembly of section .text:
 0+1fc <[^>]*> ee65114b[ 	]+wsrlhg[ 	]+wr1, wr5, wcgr3
 0+200 <[^>]*> 4ea51148[ 	]+wsrlwgmi[ 	]+wr1, wr5, wcgr0
 0+204 <[^>]*> eee51149[ 	]+wsrldg[ 	]+wr1, wr5, wcgr1
-0+208 <[^>]*> ed811004[ 	]+wstrb[ 	]+wr1, \[r1, #4\]
-0+20c <[^>]*> ede11004[ 	]+wstrh[ 	]+wr1, \[r1, #4\]!
+0+208 <[^>]*> ed8110ff[ 	]+wstrb[ 	]+wr1, \[r1, #255\]
+0+20c <[^>]*> ed6110ff[ 	]+wstrh[ 	]+wr1, \[r1, #-255\]!
 0+210 <[^>]*> eca11101[ 	]+wstrw[ 	]+wr1, \[r1\], #4
-0+214 <[^>]*> edc11101[ 	]+wstrd[ 	]+wr1, \[r1, #4\]
-0+218 <[^>]*> fca13101[ 	]+wstrw[ 	]+wcasf, \[r1\], #4
+0+214 <[^>]*> edc111ff[ 	]+wstrd[ 	]+wr1, \[r1, #1020\]
+0+218 <[^>]*> fca1314b[ 	]+wstrw[ 	]+wcasf, \[r1\], #300
 0+21c <[^>]*> 3e1311ae[ 	]+wsubbuscc[ 	]+wr1, wr3, wr14
 0+220 <[^>]*> ee5311ae[ 	]+wsubhus[ 	]+wr1, wr3, wr14
 0+224 <[^>]*> 3e9311ae[ 	]+wsubwuscc[ 	]+wr1, wr3, wr14
@@ -166,3 +166,6 @@ Disassembly of section .text:
 0+278 <[^>]*> 0e9540ea[ 	]+wunpckilweq[ 	]+wr4, wr5, wr10
 0+27c <[^>]*> 1e143005[ 	]+wxorne[ 	]+wr3, wr4, wr5
 0+280 <[^>]*> ae377007[ 	]+wandnge[ 	]+wr7, wr7, wr7
+0+284 <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
+0+288 <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
+0+28c <[^>]*> e1a00000[ 	]+nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/iwmmxt.s b/gas/testsuite/gas/arm/iwmmxt.s
index b3e7a8562e9f..0ebbad5cd3c7 100644
--- a/gas/testsuite/gas/arm/iwmmxt.s
+++ b/gas/testsuite/gas/arm/iwmmxt.s
@@ -54,7 +54,7 @@ iwmmxt:
 	waddBUS		wr0,  wr2,  wr4
 	waddbssal	wr6,  wr8,  wr10
 	waddH		wr12, wr14, wr15
-	WADDHUSNV	wr13, wr12, wr11
+	WADDHUSLE	wr13, wr12, wr11
 	WADDHSSeq	wr10, wr9,  wr8
 	WADDWne		wr7,  wr6, wr5
 	waddwus		wr4,  wr3, wr2
@@ -88,7 +88,7 @@ iwmmxt:
 	wldrb		wr1, [r0, #36]
 	wldrheq		wr2, [r1, #24]!
 	wldrwne		wr3, [r2], #16
-	wldrdvs		wr4, [r3, #8]
+	wldrdvs		wr4, [r3, #-332]
 	wldrw		wcssf, [r1, #20]!
 	
 	wmacu		wr4, wr7, wr9
@@ -104,7 +104,7 @@ iwmmxt:
 	wmaxuhpl	wr3, wr4, wr5
 	wmaxshmi	wr3, wr4, wr5
 	wmaxuwge	wr3, wr4, wr5
-	wmaxswnv	wr3, wr4, wr5
+	wmaxswle	wr3, wr4, wr5
 
 	wminubul	wr4, wr12, wr10
 	wminsb		wr4, wr12, wr10
@@ -139,7 +139,7 @@ iwmmxt:
 	wsadb		wr2, wr0, wr10
 	wsadhal		wr2, wr0, wr10
 	wsadbz		wr2, wr0, wr10
-	wsadhznv	wr2, wr0, wr10
+	wsadhzle	wr2, wr0, wr10
 
 	wshufheq	wr4, wr9, #251
 
@@ -164,11 +164,11 @@ iwmmxt:
 	wsrlwgmi	wr1, wr5, wcgr0
 	wsrldg		wr1, wr5, wcgr1
 
-	wstrb		wr1, [r1, #4]
-	wstrh		wr1, [r1, #4]!
+	wstrb		wr1, [r1, #0xFF]
+	wstrh		wr1, [r1, #-0xFF]!
 	wstrw		wr1, [r1], #4
-	wstrd		wr1, [r1, #4]
-	wstrw		wcasf, [r1], #4
+	wstrd		wr1, [r1, #0x3FC]
+	wstrw		wcasf, [r1], #300
 
 	wsubbusul	wr1, wr3, wr14
 	wsubhus		wr1, wr3, wr14
@@ -202,3 +202,8 @@ iwmmxt:
 	wxorne		wr3, wr4, wr5
 
 	wzeroge		wr7
+
+	@ a.out-required section size padding
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/le-fpconst.d b/gas/testsuite/gas/arm/le-fpconst.d
index 37a7338712ef..846da89f0293 100644
--- a/gas/testsuite/gas/arm/le-fpconst.d
+++ b/gas/testsuite/gas/arm/le-fpconst.d
@@ -1,6 +1,9 @@
 #objdump: -s --section=.text
 #as: -EL
 #name: arm little-endian fpconst
+# Not all arm targets are bi-endian, so only run this test on ones
+# we know that are.  FIXME We should probably also key off armeb/armel.
+#target: *-*-pe
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/macro1.d b/gas/testsuite/gas/arm/macro1.d
new file mode 100644
index 000000000000..2384594fc545
--- /dev/null
+++ b/gas/testsuite/gas/arm/macro1.d
@@ -0,0 +1,12 @@
+# name: Macro scrubbing
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+[^:]+: +file format .*arm.*
+
+Disassembly of section .text:
+
+0+0 <[^>]*> e8bd8030 ?	ldmia	sp!, {r4, r5, pc}
+0+4 <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
+0+8 <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
+0+c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/macro1.s b/gas/testsuite/gas/arm/macro1.s
new file mode 100644
index 000000000000..e2880e7b9228
--- /dev/null
+++ b/gas/testsuite/gas/arm/macro1.s
@@ -0,0 +1,12 @@
+	@ Test that macro expansions are properly scrubbed.
+	.macro popret regs
+	ldmia sp!, {\regs, pc}
+	.endm
+	.text
+l:
+	popret "r4, r5"
+
+	@ section padding for a.out's sake
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/mapping.d b/gas/testsuite/gas/arm/mapping.d
index 81022093407b..e6db1a987ff2 100644
--- a/gas/testsuite/gas/arm/mapping.d
+++ b/gas/testsuite/gas/arm/mapping.d
@@ -1,18 +1,22 @@
-#objdump: --syms
+#objdump: --syms --special-syms
 #name: ARM Mapping Symbols
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 
 # Test the generation of ARM ELF Mapping Symbols
 
 .*: +file format.*arm.*
 
 SYMBOL TABLE:
-0+00 l    d  .text	0+0 
-0+00 l    d  .data	0+0 
-0+00 l    d  .bss	0+0 
-0+00 l     F .text	0+0 \$a
+0+00 l    d  .text	0+0 (|.text)
+0+00 l    d  .data	0+0 (|.data)
+0+00 l    d  .bss	0+0 (|.bss)
+0+00 l       .text	0+0 \$a
 0+08 l       .text	0+0 \$t
-0+00 l     O .data	0+0 \$d
-0+00 l    d  foo	0+0 
+0+00 l       .data	0+0 \$d
+0+00 l    d  foo	0+0 (|foo)
 0+00 l       foo	0+0 \$t
+#Maybe section symbol for .ARM.attributes
+#...
 0+00 g       .text	0+0 mapping
-0+08 g       .text	0+0 thumb_mapping
+0+08 g     F .text	0+0 thumb_mapping
diff --git a/gas/testsuite/gas/arm/maverick.c b/gas/testsuite/gas/arm/maverick.c
index 5f55e86aff2f..e0eb25eccd31 100644
--- a/gas/testsuite/gas/arm/maverick.c
+++ b/gas/testsuite/gas/arm/maverick.c
@@ -13,7 +13,7 @@
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 /* Generator of tests for Maverick.
 
@@ -75,16 +75,16 @@ arm_cond (func_arg * arg, insn_data * data)
 
 /* The sign of an offset is actually used to determined whether the
    absolute value of the offset should be added or subtracted, so we
-   must adjust negative values so that they do not overflow: -256 is
+   must adjust negative values so that they do not overflow: -1024 is
    not valid, but -0 is distinct from +0.  */
 int
 off8s (func_arg * arg, insn_data * data)
 #define off8s { off8s }
 {
   int val;
-  char value[6];
+  char value[9];
 
-  /* Values less that -255 or between -3 and 0 are problematical.
+  /* Zero values are problematical.
      The assembler performs translations on the addressing modes
      for these values, meaning that we cannot just recreate the
      disassembler string in the LDST macro without knowing what
@@ -93,26 +93,23 @@ off8s (func_arg * arg, insn_data * data)
     {
       val  = get_bits (9s);
     }
-  while (val < -255 || (val > -4 && val < 1));
+  while (val == -1 || val == 0);
   
+  val <<= 2;
   if (val < 0)
     {
-      val = - val;
-      val &= ~3;
+      val = -4 - val;
       sprintf (value, ", #-%i", val);
       data->dis_out = strdup (value);
       sprintf (value, ", #-%i", val);
       data->as_in = strdup (value);
-      val >>= 2;
-      data->bits = val;
+      data->bits = val >> 2;
     }
   else
     {
-      val &= ~3;
       sprintf (value, ", #%i", val);
       data->as_in = data->dis_out = strdup (value);
-      val >>= 2;
-      data->bits = val | (1 << 23);
+      data->bits = (val >> 2) | (1 << 23);
     }
   
   return 0;
@@ -273,13 +270,20 @@ imm7 (func_arg *arg, insn_data *data)
   MCRC2 (mv ## insname, cpnum, 0, 1, opcode2, \
 	 armreg (12), mvreg (regDSPname, 16))
 
+/* Move between coprocessor registers. A two operand CDP insn.   */
+#define MCC2(insname, opcode1, opcode2, reg1spec, reg2spec) \
+  mv_insn (insname, , \
+	   ((14 << 24) | ((opcode1) << 20) | \
+	    (4 << 8) | ((opcode2) << 5)), \
+	   reg1spec, comma, reg2spec)
+
 /* Define a move from a DSP register to a DSP accumulator.  */
 #define MVDSPACC(insname, opcode2, regDSPname) \
-  MCRC2 (mv ## insname, 6, 0, 1, opcode2, acreg (0), mvreg (regDSPname, 16))
+  MCC2 (mv ## insname, 2, opcode2, acreg (12), mvreg (regDSPname, 16))
 
 /* Define a move from a DSP accumulator to a DSP register.  */
 #define MVACCDSP(insname, opcode2, regDSPname) \
-  MCRC2 (mv ## insname, 6, 0, 0, opcode2, mvreg (regDSPname, 0), acreg (16))
+  MCC2 (mv ## insname, 1, opcode2, mvreg (regDSPname, 12), acreg (16))
 
 /* Define move insns between a float DSP register and an ARM
    register.  */
@@ -355,13 +359,13 @@ MVd (dlr, rdl, 0);
 MVd (dhr, rdh, 1);
 MVdx (64lr, r64l, 0);
 MVdx (64hr, r64h, 1);
-MVfxa (al32, 32al, 0);
-MVfxa (am32, 32am, 1);
-MVfxa (ah32, 32ah, 2);
-MVfxa (a32, 32a, 3);
-MVdxa (a64, 64a, 4);
-MCRC2 (mvsc32, 4, 1, 0, 7, dspsc, mvreg ("dx", 12));
-MCRC2 (mv32sc, 4, 0, 1, 7, mvreg ("dx", 12), dspsc);
+MVfxa (al32, 32al, 2);
+MVfxa (am32, 32am, 3);
+MVfxa (ah32, 32ah, 4);
+MVfxa (a32, 32a, 5);
+MVdxa (a64, 64a, 6);
+MCC2 (mvsc32, 2, 7, dspsc, mvreg ("dx", 12));
+MCC2 (mv32sc, 1, 7, mvreg ("dx", 12), dspsc);
 CDP2 (cpys, , 4, 0, 0, "f", "f");
 CDP2 (cpyd, , 4, 0, 1, "d", "d");
 
diff --git a/gas/testsuite/gas/arm/maverick.d b/gas/testsuite/gas/arm/maverick.d
index 26e82dfdb09f..7c41457b1fb6 100644
--- a/gas/testsuite/gas/arm/maverick.d
+++ b/gas/testsuite/gas/arm/maverick.d
@@ -8,470 +8,470 @@
 
 Disassembly of section .text:
 # load_store:
-0*0 <load_store> 0d ?9d ?54 ?3f ? *	cfldrseq	mvf5, ?\[sp, #252\]
-0*4 <load_store\+0x4> 4d ?9b ?e4 ?12 ? *	cfldrsmi	mvf14, ?\[fp, #72\]
-0*8 <load_store\+0x8> 7d ?1c ?24 ?3c ? *	cfldrsvc	mvf2, ?\[ip, #-240\]
-0*c <load_store\+0xc> bd ?9a ?04 ?3f ? *	cfldrslt	mvf0, ?\[sl, #252\]
-0*10 <load_store\+0x10> cd ?9b ?a4 ?12 ? *	cfldrsgt	mvf10, ?\[fp, #72\]
-0*14 <load_store\+0x14> dd ?3c ?64 ?3c ? *	cfldrsle	mvf6, ?\[ip, #-240\]!
-0*18 <load_store\+0x18> 9d ?ba ?04 ?3f ? *	cfldrsls	mvf0, ?\[sl, #252\]!
-0*1c <load_store\+0x1c> 4d ?bb ?e4 ?12 ? *	cfldrsmi	mvf14, ?\[fp, #72\]!
-0*20 <load_store\+0x20> 7d ?3c ?24 ?3c ? *	cfldrsvc	mvf2, ?\[ip, #-240\]!
-0*24 <load_store\+0x24> bd ?ba ?04 ?3f ? *	cfldrslt	mvf0, ?\[sl, #252\]!
-0*28 <load_store\+0x28> cc ?bb ?a4 ?12 ? *	cfldrsgt	mvf10, ?\[fp\], #72
-0*2c <load_store\+0x2c> dc ?3c ?64 ?3c ? *	cfldrsle	mvf6, ?\[ip\], #-240
-0*30 <load_store\+0x30> 9c ?ba ?04 ?3f ? *	cfldrsls	mvf0, ?\[sl\], #252
-0*34 <load_store\+0x34> 4c ?bb ?e4 ?12 ? *	cfldrsmi	mvf14, ?\[fp\], #72
-0*38 <load_store\+0x38> 7c ?3c ?24 ?3c ? *	cfldrsvc	mvf2, ?\[ip\], #-240
-0*3c <load_store\+0x3c> bd ?da ?04 ?3f ? *	cfldrdlt	mvd0, ?\[sl, #252\]
-0*40 <load_store\+0x40> cd ?db ?a4 ?12 ? *	cfldrdgt	mvd10, ?\[fp, #72\]
-0*44 <load_store\+0x44> dd ?5c ?64 ?3c ? *	cfldrdle	mvd6, ?\[ip, #-240\]
-0*48 <load_store\+0x48> 9d ?da ?04 ?3f ? *	cfldrdls	mvd0, ?\[sl, #252\]
-0*4c <load_store\+0x4c> 4d ?db ?e4 ?12 ? *	cfldrdmi	mvd14, ?\[fp, #72\]
-0*50 <load_store\+0x50> 7d ?7c ?24 ?3c ? *	cfldrdvc	mvd2, ?\[ip, #-240\]!
-0*54 <load_store\+0x54> bd ?fa ?04 ?3f ? *	cfldrdlt	mvd0, ?\[sl, #252\]!
-0*58 <load_store\+0x58> cd ?fb ?a4 ?12 ? *	cfldrdgt	mvd10, ?\[fp, #72\]!
-0*5c <load_store\+0x5c> dd ?7c ?64 ?3c ? *	cfldrdle	mvd6, ?\[ip, #-240\]!
-0*60 <load_store\+0x60> 9d ?fa ?04 ?3f ? *	cfldrdls	mvd0, ?\[sl, #252\]!
-0*64 <load_store\+0x64> 4c ?fb ?e4 ?12 ? *	cfldrdmi	mvd14, ?\[fp\], #72
-0*68 <load_store\+0x68> 7c ?7c ?24 ?3c ? *	cfldrdvc	mvd2, ?\[ip\], #-240
-0*6c <load_store\+0x6c> bc ?fa ?04 ?3f ? *	cfldrdlt	mvd0, ?\[sl\], #252
-0*70 <load_store\+0x70> cc ?fb ?a4 ?12 ? *	cfldrdgt	mvd10, ?\[fp\], #72
-0*74 <load_store\+0x74> dc ?7c ?64 ?3c ? *	cfldrdle	mvd6, ?\[ip\], #-240
-0*78 <load_store\+0x78> 9d ?9a ?05 ?3f ? *	cfldr32ls	mvfx0, ?\[sl, #252\]
-0*7c <load_store\+0x7c> 4d ?9b ?e5 ?12 ? *	cfldr32mi	mvfx14, ?\[fp, #72\]
-0*80 <load_store\+0x80> 7d ?1c ?25 ?3c ? *	cfldr32vc	mvfx2, ?\[ip, #-240\]
-0*84 <load_store\+0x84> bd ?9a ?05 ?3f ? *	cfldr32lt	mvfx0, ?\[sl, #252\]
-0*88 <load_store\+0x88> cd ?9b ?a5 ?12 ? *	cfldr32gt	mvfx10, ?\[fp, #72\]
-0*8c <load_store\+0x8c> dd ?3c ?65 ?3c ? *	cfldr32le	mvfx6, ?\[ip, #-240\]!
-0*90 <load_store\+0x90> 9d ?ba ?05 ?3f ? *	cfldr32ls	mvfx0, ?\[sl, #252\]!
-0*94 <load_store\+0x94> 4d ?bb ?e5 ?12 ? *	cfldr32mi	mvfx14, ?\[fp, #72\]!
-0*98 <load_store\+0x98> 7d ?3c ?25 ?3c ? *	cfldr32vc	mvfx2, ?\[ip, #-240\]!
-0*9c <load_store\+0x9c> bd ?ba ?05 ?3f ? *	cfldr32lt	mvfx0, ?\[sl, #252\]!
-0*a0 <load_store\+0xa0> cc ?bb ?a5 ?12 ? *	cfldr32gt	mvfx10, ?\[fp\], #72
-0*a4 <load_store\+0xa4> dc ?3c ?65 ?3c ? *	cfldr32le	mvfx6, ?\[ip\], #-240
-0*a8 <load_store\+0xa8> 9c ?ba ?05 ?3f ? *	cfldr32ls	mvfx0, ?\[sl\], #252
-0*ac <load_store\+0xac> 4c ?bb ?e5 ?12 ? *	cfldr32mi	mvfx14, ?\[fp\], #72
-0*b0 <load_store\+0xb0> 7c ?3c ?25 ?3c ? *	cfldr32vc	mvfx2, ?\[ip\], #-240
-0*b4 <load_store\+0xb4> bd ?da ?05 ?3f ? *	cfldr64lt	mvdx0, ?\[sl, #252\]
-0*b8 <load_store\+0xb8> cd ?db ?a5 ?12 ? *	cfldr64gt	mvdx10, ?\[fp, #72\]
-0*bc <load_store\+0xbc> dd ?5c ?65 ?3c ? *	cfldr64le	mvdx6, ?\[ip, #-240\]
-0*c0 <load_store\+0xc0> 9d ?da ?05 ?3f ? *	cfldr64ls	mvdx0, ?\[sl, #252\]
-0*c4 <load_store\+0xc4> 4d ?db ?e5 ?12 ? *	cfldr64mi	mvdx14, ?\[fp, #72\]
-0*c8 <load_store\+0xc8> 7d ?7c ?25 ?3c ? *	cfldr64vc	mvdx2, ?\[ip, #-240\]!
-0*cc <load_store\+0xcc> bd ?fa ?05 ?3f ? *	cfldr64lt	mvdx0, ?\[sl, #252\]!
-0*d0 <load_store\+0xd0> cd ?fb ?a5 ?12 ? *	cfldr64gt	mvdx10, ?\[fp, #72\]!
-0*d4 <load_store\+0xd4> dd ?7c ?65 ?3c ? *	cfldr64le	mvdx6, ?\[ip, #-240\]!
-0*d8 <load_store\+0xd8> 9d ?fa ?05 ?3f ? *	cfldr64ls	mvdx0, ?\[sl, #252\]!
-0*dc <load_store\+0xdc> 4c ?fb ?e5 ?12 ? *	cfldr64mi	mvdx14, ?\[fp\], #72
-0*e0 <load_store\+0xe0> 7c ?7c ?25 ?3c ? *	cfldr64vc	mvdx2, ?\[ip\], #-240
-0*e4 <load_store\+0xe4> bc ?fa ?05 ?3f ? *	cfldr64lt	mvdx0, ?\[sl\], #252
-0*e8 <load_store\+0xe8> cc ?fb ?a5 ?12 ? *	cfldr64gt	mvdx10, ?\[fp\], #72
-0*ec <load_store\+0xec> dc ?7c ?65 ?3c ? *	cfldr64le	mvdx6, ?\[ip\], #-240
-0*f0 <load_store\+0xf0> 9d ?8a ?04 ?3f ? *	cfstrsls	mvf0, ?\[sl, #252\]
-0*f4 <load_store\+0xf4> 4d ?8b ?e4 ?12 ? *	cfstrsmi	mvf14, ?\[fp, #72\]
-0*f8 <load_store\+0xf8> 7d ?0c ?24 ?3c ? *	cfstrsvc	mvf2, ?\[ip, #-240\]
-0*fc <load_store\+0xfc> bd ?8a ?04 ?3f ? *	cfstrslt	mvf0, ?\[sl, #252\]
-0*100 <load_store\+0x100> cd ?8b ?a4 ?12 ? *	cfstrsgt	mvf10, ?\[fp, #72\]
-0*104 <load_store\+0x104> dd ?2c ?64 ?3c ? *	cfstrsle	mvf6, ?\[ip, #-240\]!
-0*108 <load_store\+0x108> 9d ?aa ?04 ?3f ? *	cfstrsls	mvf0, ?\[sl, #252\]!
-0*10c <load_store\+0x10c> 4d ?ab ?e4 ?12 ? *	cfstrsmi	mvf14, ?\[fp, #72\]!
-0*110 <load_store\+0x110> 7d ?2c ?24 ?3c ? *	cfstrsvc	mvf2, ?\[ip, #-240\]!
-0*114 <load_store\+0x114> bd ?aa ?04 ?3f ? *	cfstrslt	mvf0, ?\[sl, #252\]!
-0*118 <load_store\+0x118> cc ?ab ?a4 ?12 ? *	cfstrsgt	mvf10, ?\[fp\], #72
-0*11c <load_store\+0x11c> dc ?2c ?64 ?3c ? *	cfstrsle	mvf6, ?\[ip\], #-240
-0*120 <load_store\+0x120> 9c ?aa ?04 ?3f ? *	cfstrsls	mvf0, ?\[sl\], #252
-0*124 <load_store\+0x124> 4c ?ab ?e4 ?12 ? *	cfstrsmi	mvf14, ?\[fp\], #72
-0*128 <load_store\+0x128> 7c ?2c ?24 ?3c ? *	cfstrsvc	mvf2, ?\[ip\], #-240
-0*12c <load_store\+0x12c> bd ?ca ?04 ?3f ? *	cfstrdlt	mvd0, ?\[sl, #252\]
-0*130 <load_store\+0x130> cd ?cb ?a4 ?12 ? *	cfstrdgt	mvd10, ?\[fp, #72\]
-0*134 <load_store\+0x134> dd ?4c ?64 ?3c ? *	cfstrdle	mvd6, ?\[ip, #-240\]
-0*138 <load_store\+0x138> 9d ?ca ?04 ?3f ? *	cfstrdls	mvd0, ?\[sl, #252\]
-0*13c <load_store\+0x13c> 4d ?cb ?e4 ?12 ? *	cfstrdmi	mvd14, ?\[fp, #72\]
-0*140 <load_store\+0x140> 7d ?6c ?24 ?3c ? *	cfstrdvc	mvd2, ?\[ip, #-240\]!
-0*144 <load_store\+0x144> bd ?ea ?04 ?3f ? *	cfstrdlt	mvd0, ?\[sl, #252\]!
-0*148 <load_store\+0x148> cd ?eb ?a4 ?12 ? *	cfstrdgt	mvd10, ?\[fp, #72\]!
-0*14c <load_store\+0x14c> dd ?6c ?64 ?3c ? *	cfstrdle	mvd6, ?\[ip, #-240\]!
-0*150 <load_store\+0x150> 9d ?ea ?04 ?3f ? *	cfstrdls	mvd0, ?\[sl, #252\]!
-0*154 <load_store\+0x154> 4c ?eb ?e4 ?12 ? *	cfstrdmi	mvd14, ?\[fp\], #72
-0*158 <load_store\+0x158> 7c ?6c ?24 ?3c ? *	cfstrdvc	mvd2, ?\[ip\], #-240
-0*15c <load_store\+0x15c> bc ?ea ?04 ?3f ? *	cfstrdlt	mvd0, ?\[sl\], #252
-0*160 <load_store\+0x160> cc ?eb ?a4 ?12 ? *	cfstrdgt	mvd10, ?\[fp\], #72
-0*164 <load_store\+0x164> dc ?6c ?64 ?3c ? *	cfstrdle	mvd6, ?\[ip\], #-240
-0*168 <load_store\+0x168> 9d ?8a ?05 ?3f ? *	cfstr32ls	mvfx0, ?\[sl, #252\]
-0*16c <load_store\+0x16c> 4d ?8b ?e5 ?12 ? *	cfstr32mi	mvfx14, ?\[fp, #72\]
-0*170 <load_store\+0x170> 7d ?0c ?25 ?3c ? *	cfstr32vc	mvfx2, ?\[ip, #-240\]
-0*174 <load_store\+0x174> bd ?8a ?05 ?3f ? *	cfstr32lt	mvfx0, ?\[sl, #252\]
-0*178 <load_store\+0x178> cd ?8b ?a5 ?12 ? *	cfstr32gt	mvfx10, ?\[fp, #72\]
-0*17c <load_store\+0x17c> dd ?2c ?65 ?3c ? *	cfstr32le	mvfx6, ?\[ip, #-240\]!
-0*180 <load_store\+0x180> 9d ?aa ?05 ?3f ? *	cfstr32ls	mvfx0, ?\[sl, #252\]!
-0*184 <load_store\+0x184> 4d ?ab ?e5 ?12 ? *	cfstr32mi	mvfx14, ?\[fp, #72\]!
-0*188 <load_store\+0x188> 7d ?2c ?25 ?3c ? *	cfstr32vc	mvfx2, ?\[ip, #-240\]!
-0*18c <load_store\+0x18c> bd ?aa ?05 ?3f ? *	cfstr32lt	mvfx0, ?\[sl, #252\]!
-0*190 <load_store\+0x190> cc ?ab ?a5 ?12 ? *	cfstr32gt	mvfx10, ?\[fp\], #72
-0*194 <load_store\+0x194> dc ?2c ?65 ?3c ? *	cfstr32le	mvfx6, ?\[ip\], #-240
-0*198 <load_store\+0x198> 9c ?aa ?05 ?3f ? *	cfstr32ls	mvfx0, ?\[sl\], #252
-0*19c <load_store\+0x19c> 4c ?ab ?e5 ?12 ? *	cfstr32mi	mvfx14, ?\[fp\], #72
-0*1a0 <load_store\+0x1a0> 7c ?2c ?25 ?3c ? *	cfstr32vc	mvfx2, ?\[ip\], #-240
-0*1a4 <load_store\+0x1a4> bd ?ca ?05 ?3f ? *	cfstr64lt	mvdx0, ?\[sl, #252\]
-0*1a8 <load_store\+0x1a8> cd ?cb ?a5 ?12 ? *	cfstr64gt	mvdx10, ?\[fp, #72\]
-0*1ac <load_store\+0x1ac> dd ?4c ?65 ?3c ? *	cfstr64le	mvdx6, ?\[ip, #-240\]
-0*1b0 <load_store\+0x1b0> 9d ?ca ?05 ?3f ? *	cfstr64ls	mvdx0, ?\[sl, #252\]
-0*1b4 <load_store\+0x1b4> 4d ?cb ?e5 ?12 ? *	cfstr64mi	mvdx14, ?\[fp, #72\]
-0*1b8 <load_store\+0x1b8> 7d ?6c ?25 ?3c ? *	cfstr64vc	mvdx2, ?\[ip, #-240\]!
-0*1bc <load_store\+0x1bc> bd ?ea ?05 ?3f ? *	cfstr64lt	mvdx0, ?\[sl, #252\]!
-0*1c0 <load_store\+0x1c0> cd ?eb ?a5 ?12 ? *	cfstr64gt	mvdx10, ?\[fp, #72\]!
-0*1c4 <load_store\+0x1c4> dd ?6c ?65 ?3c ? *	cfstr64le	mvdx6, ?\[ip, #-240\]!
-0*1c8 <load_store\+0x1c8> 9d ?ea ?05 ?3f ? *	cfstr64ls	mvdx0, ?\[sl, #252\]!
-0*1cc <load_store\+0x1cc> 4c ?eb ?e5 ?12 ? *	cfstr64mi	mvdx14, ?\[fp\], #72
-0*1d0 <load_store\+0x1d0> 7c ?6c ?25 ?3c ? *	cfstr64vc	mvdx2, ?\[ip\], #-240
-0*1d4 <load_store\+0x1d4> bc ?ea ?05 ?3f ? *	cfstr64lt	mvdx0, ?\[sl\], #252
-0*1d8 <load_store\+0x1d8> cc ?eb ?a5 ?12 ? *	cfstr64gt	mvdx10, ?\[fp\], #72
-0*1dc <load_store\+0x1dc> dc ?6c ?65 ?3c ? *	cfstr64le	mvdx6, ?\[ip\], #-240
+0*0 <load_store> 0d ?9d ?54 ?ff ? *	cfldrseq	mvf5, ?\[sp, #1020\]
+0*4 <load_store\+0x4> 4d ?9b ?e4 ?49 ? *	cfldrsmi	mvf14, ?\[fp, #292\]
+0*8 <load_store\+0x8> 7d ?1c ?24 ?ef ? *	cfldrsvc	mvf2, ?\[ip, #-956\]
+0*c <load_store\+0xc> bd ?1a ?04 ?ff ? *	cfldrslt	mvf0, ?\[sl, #-1020\]
+0*10 <load_store\+0x10> 3d ?11 ?c4 ?27 ? *	cfldrscc	mvf12, ?\[r1, #-156\]
+0*14 <load_store\+0x14> ed ?b9 ?d4 ?68 ? *	cfldrs	mvf13, ?\[r9, #416\]!
+0*18 <load_store\+0x18> 2d ?30 ?94 ?ff ? *	cfldrscs	mvf9, ?\[r0, #-1020\]!
+0*1c <load_store\+0x1c> 9d ?31 ?44 ?27 ? *	cfldrsls	mvf4, ?\[r1, #-156\]!
+0*20 <load_store\+0x20> dd ?b9 ?74 ?68 ? *	cfldrsle	mvf7, ?\[r9, #416\]!
+0*24 <load_store\+0x24> 6d ?30 ?b4 ?ff ? *	cfldrsvs	mvf11, ?\[r0, #-1020\]!
+0*28 <load_store\+0x28> 3c ?31 ?c4 ?27 ? *	cfldrscc	mvf12, ?\[r1\], #-156
+0*2c <load_store\+0x2c> ec ?b9 ?d4 ?68 ? *	cfldrs	mvf13, ?\[r9\], #416
+0*30 <load_store\+0x30> 2c ?30 ?94 ?ff ? *	cfldrscs	mvf9, ?\[r0\], #-1020
+0*34 <load_store\+0x34> 9c ?31 ?44 ?27 ? *	cfldrsls	mvf4, ?\[r1\], #-156
+0*38 <load_store\+0x38> dc ?b9 ?74 ?68 ? *	cfldrsle	mvf7, ?\[r9\], #416
+0*3c <load_store\+0x3c> 6d ?50 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0, #-1020\]
+0*40 <load_store\+0x40> 3d ?51 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1, #-156\]
+0*44 <load_store\+0x44> ed ?d9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9, #416\]
+0*48 <load_store\+0x48> 2d ?50 ?94 ?ff ? *	cfldrdcs	mvd9, ?\[r0, #-1020\]
+0*4c <load_store\+0x4c> 9d ?51 ?44 ?27 ? *	cfldrdls	mvd4, ?\[r1, #-156\]
+0*50 <load_store\+0x50> dd ?f9 ?74 ?68 ? *	cfldrdle	mvd7, ?\[r9, #416\]!
+0*54 <load_store\+0x54> 6d ?70 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0, #-1020\]!
+0*58 <load_store\+0x58> 3d ?71 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1, #-156\]!
+0*5c <load_store\+0x5c> ed ?f9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9, #416\]!
+0*60 <load_store\+0x60> 2d ?70 ?94 ?ff ? *	cfldrdcs	mvd9, ?\[r0, #-1020\]!
+0*64 <load_store\+0x64> 9c ?71 ?44 ?27 ? *	cfldrdls	mvd4, ?\[r1\], #-156
+0*68 <load_store\+0x68> dc ?f9 ?74 ?68 ? *	cfldrdle	mvd7, ?\[r9\], #416
+0*6c <load_store\+0x6c> 6c ?70 ?b4 ?ff ? *	cfldrdvs	mvd11, ?\[r0\], #-1020
+0*70 <load_store\+0x70> 3c ?71 ?c4 ?27 ? *	cfldrdcc	mvd12, ?\[r1\], #-156
+0*74 <load_store\+0x74> ec ?f9 ?d4 ?68 ? *	cfldrd	mvd13, ?\[r9\], #416
+0*78 <load_store\+0x78> 2d ?10 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0, #-1020\]
+0*7c <load_store\+0x7c> 9d ?11 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1, #-156\]
+0*80 <load_store\+0x80> dd ?99 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9, #416\]
+0*84 <load_store\+0x84> 6d ?10 ?b5 ?ff ? *	cfldr32vs	mvfx11, ?\[r0, #-1020\]
+0*88 <load_store\+0x88> 3d ?11 ?c5 ?27 ? *	cfldr32cc	mvfx12, ?\[r1, #-156\]
+0*8c <load_store\+0x8c> ed ?b9 ?d5 ?68 ? *	cfldr32	mvfx13, ?\[r9, #416\]!
+0*90 <load_store\+0x90> 2d ?30 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0, #-1020\]!
+0*94 <load_store\+0x94> 9d ?31 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1, #-156\]!
+0*98 <load_store\+0x98> dd ?b9 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9, #416\]!
+0*9c <load_store\+0x9c> 6d ?30 ?b5 ?ff ? *	cfldr32vs	mvfx11, ?\[r0, #-1020\]!
+0*a0 <load_store\+0xa0> 3c ?31 ?c5 ?27 ? *	cfldr32cc	mvfx12, ?\[r1\], #-156
+0*a4 <load_store\+0xa4> ec ?b9 ?d5 ?68 ? *	cfldr32	mvfx13, ?\[r9\], #416
+0*a8 <load_store\+0xa8> 2c ?30 ?95 ?ff ? *	cfldr32cs	mvfx9, ?\[r0\], #-1020
+0*ac <load_store\+0xac> 9c ?31 ?45 ?27 ? *	cfldr32ls	mvfx4, ?\[r1\], #-156
+0*b0 <load_store\+0xb0> dc ?b9 ?75 ?68 ? *	cfldr32le	mvfx7, ?\[r9\], #416
+0*b4 <load_store\+0xb4> 6d ?50 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0, #-1020\]
+0*b8 <load_store\+0xb8> 3d ?51 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1, #-156\]
+0*bc <load_store\+0xbc> ed ?d9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9, #416\]
+0*c0 <load_store\+0xc0> 2d ?50 ?95 ?ff ? *	cfldr64cs	mvdx9, ?\[r0, #-1020\]
+0*c4 <load_store\+0xc4> 9d ?51 ?45 ?27 ? *	cfldr64ls	mvdx4, ?\[r1, #-156\]
+0*c8 <load_store\+0xc8> dd ?f9 ?75 ?68 ? *	cfldr64le	mvdx7, ?\[r9, #416\]!
+0*cc <load_store\+0xcc> 6d ?70 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0, #-1020\]!
+0*d0 <load_store\+0xd0> 3d ?71 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1, #-156\]!
+0*d4 <load_store\+0xd4> ed ?f9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9, #416\]!
+0*d8 <load_store\+0xd8> 2d ?70 ?95 ?ff ? *	cfldr64cs	mvdx9, ?\[r0, #-1020\]!
+0*dc <load_store\+0xdc> 9c ?71 ?45 ?27 ? *	cfldr64ls	mvdx4, ?\[r1\], #-156
+0*e0 <load_store\+0xe0> dc ?f9 ?75 ?68 ? *	cfldr64le	mvdx7, ?\[r9\], #416
+0*e4 <load_store\+0xe4> 6c ?70 ?b5 ?ff ? *	cfldr64vs	mvdx11, ?\[r0\], #-1020
+0*e8 <load_store\+0xe8> 3c ?71 ?c5 ?27 ? *	cfldr64cc	mvdx12, ?\[r1\], #-156
+0*ec <load_store\+0xec> ec ?f9 ?d5 ?68 ? *	cfldr64	mvdx13, ?\[r9\], #416
+0*f0 <load_store\+0xf0> 2d ?00 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0, #-1020\]
+0*f4 <load_store\+0xf4> 9d ?01 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1, #-156\]
+0*f8 <load_store\+0xf8> dd ?89 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9, #416\]
+0*fc <load_store\+0xfc> 6d ?00 ?b4 ?ff ? *	cfstrsvs	mvf11, ?\[r0, #-1020\]
+0*100 <load_store\+0x100> 3d ?01 ?c4 ?27 ? *	cfstrscc	mvf12, ?\[r1, #-156\]
+0*104 <load_store\+0x104> ed ?a9 ?d4 ?68 ? *	cfstrs	mvf13, ?\[r9, #416\]!
+0*108 <load_store\+0x108> 2d ?20 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0, #-1020\]!
+0*10c <load_store\+0x10c> 9d ?21 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1, #-156\]!
+0*110 <load_store\+0x110> dd ?a9 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9, #416\]!
+0*114 <load_store\+0x114> 6d ?20 ?b4 ?ff ? *	cfstrsvs	mvf11, ?\[r0, #-1020\]!
+0*118 <load_store\+0x118> 3c ?21 ?c4 ?27 ? *	cfstrscc	mvf12, ?\[r1\], #-156
+0*11c <load_store\+0x11c> ec ?a9 ?d4 ?68 ? *	cfstrs	mvf13, ?\[r9\], #416
+0*120 <load_store\+0x120> 2c ?20 ?94 ?ff ? *	cfstrscs	mvf9, ?\[r0\], #-1020
+0*124 <load_store\+0x124> 9c ?21 ?44 ?27 ? *	cfstrsls	mvf4, ?\[r1\], #-156
+0*128 <load_store\+0x128> dc ?a9 ?74 ?68 ? *	cfstrsle	mvf7, ?\[r9\], #416
+0*12c <load_store\+0x12c> 6d ?40 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0, #-1020\]
+0*130 <load_store\+0x130> 3d ?41 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1, #-156\]
+0*134 <load_store\+0x134> ed ?c9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9, #416\]
+0*138 <load_store\+0x138> 2d ?40 ?94 ?ff ? *	cfstrdcs	mvd9, ?\[r0, #-1020\]
+0*13c <load_store\+0x13c> 9d ?41 ?44 ?27 ? *	cfstrdls	mvd4, ?\[r1, #-156\]
+0*140 <load_store\+0x140> dd ?e9 ?74 ?68 ? *	cfstrdle	mvd7, ?\[r9, #416\]!
+0*144 <load_store\+0x144> 6d ?60 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0, #-1020\]!
+0*148 <load_store\+0x148> 3d ?61 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1, #-156\]!
+0*14c <load_store\+0x14c> ed ?e9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9, #416\]!
+0*150 <load_store\+0x150> 2d ?60 ?94 ?ff ? *	cfstrdcs	mvd9, ?\[r0, #-1020\]!
+0*154 <load_store\+0x154> 9c ?61 ?44 ?27 ? *	cfstrdls	mvd4, ?\[r1\], #-156
+0*158 <load_store\+0x158> dc ?e9 ?74 ?68 ? *	cfstrdle	mvd7, ?\[r9\], #416
+0*15c <load_store\+0x15c> 6c ?60 ?b4 ?ff ? *	cfstrdvs	mvd11, ?\[r0\], #-1020
+0*160 <load_store\+0x160> 3c ?61 ?c4 ?27 ? *	cfstrdcc	mvd12, ?\[r1\], #-156
+0*164 <load_store\+0x164> ec ?e9 ?d4 ?68 ? *	cfstrd	mvd13, ?\[r9\], #416
+0*168 <load_store\+0x168> 2d ?00 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0, #-1020\]
+0*16c <load_store\+0x16c> 9d ?01 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1, #-156\]
+0*170 <load_store\+0x170> dd ?89 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9, #416\]
+0*174 <load_store\+0x174> 6d ?00 ?b5 ?ff ? *	cfstr32vs	mvfx11, ?\[r0, #-1020\]
+0*178 <load_store\+0x178> 3d ?01 ?c5 ?27 ? *	cfstr32cc	mvfx12, ?\[r1, #-156\]
+0*17c <load_store\+0x17c> ed ?a9 ?d5 ?68 ? *	cfstr32	mvfx13, ?\[r9, #416\]!
+0*180 <load_store\+0x180> 2d ?20 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0, #-1020\]!
+0*184 <load_store\+0x184> 9d ?21 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1, #-156\]!
+0*188 <load_store\+0x188> dd ?a9 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9, #416\]!
+0*18c <load_store\+0x18c> 6d ?20 ?b5 ?ff ? *	cfstr32vs	mvfx11, ?\[r0, #-1020\]!
+0*190 <load_store\+0x190> 3c ?21 ?c5 ?27 ? *	cfstr32cc	mvfx12, ?\[r1\], #-156
+0*194 <load_store\+0x194> ec ?a9 ?d5 ?68 ? *	cfstr32	mvfx13, ?\[r9\], #416
+0*198 <load_store\+0x198> 2c ?20 ?95 ?ff ? *	cfstr32cs	mvfx9, ?\[r0\], #-1020
+0*19c <load_store\+0x19c> 9c ?21 ?45 ?27 ? *	cfstr32ls	mvfx4, ?\[r1\], #-156
+0*1a0 <load_store\+0x1a0> dc ?a9 ?75 ?68 ? *	cfstr32le	mvfx7, ?\[r9\], #416
+0*1a4 <load_store\+0x1a4> 6d ?40 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0, #-1020\]
+0*1a8 <load_store\+0x1a8> 3d ?41 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1, #-156\]
+0*1ac <load_store\+0x1ac> ed ?c9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9, #416\]
+0*1b0 <load_store\+0x1b0> 2d ?40 ?95 ?ff ? *	cfstr64cs	mvdx9, ?\[r0, #-1020\]
+0*1b4 <load_store\+0x1b4> 9d ?41 ?45 ?27 ? *	cfstr64ls	mvdx4, ?\[r1, #-156\]
+0*1b8 <load_store\+0x1b8> dd ?e9 ?75 ?68 ? *	cfstr64le	mvdx7, ?\[r9, #416\]!
+0*1bc <load_store\+0x1bc> 6d ?60 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0, #-1020\]!
+0*1c0 <load_store\+0x1c0> 3d ?61 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1, #-156\]!
+0*1c4 <load_store\+0x1c4> ed ?e9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9, #416\]!
+0*1c8 <load_store\+0x1c8> 2d ?60 ?95 ?ff ? *	cfstr64cs	mvdx9, ?\[r0, #-1020\]!
+0*1cc <load_store\+0x1cc> 9c ?61 ?45 ?27 ? *	cfstr64ls	mvdx4, ?\[r1\], #-156
+0*1d0 <load_store\+0x1d0> dc ?e9 ?75 ?68 ? *	cfstr64le	mvdx7, ?\[r9\], #416
+0*1d4 <load_store\+0x1d4> 6c ?60 ?b5 ?ff ? *	cfstr64vs	mvdx11, ?\[r0\], #-1020
+0*1d8 <load_store\+0x1d8> 3c ?61 ?c5 ?27 ? *	cfstr64cc	mvdx12, ?\[r1\], #-156
+0*1dc <load_store\+0x1dc> ec ?e9 ?d5 ?68 ? *	cfstr64	mvdx13, ?\[r9\], #416
 # move:
-0*1e0 <move> 9e ?00 ?a4 ?50 ? *	cfmvsrls	mvf0, ?sl
-0*1e4 <move\+0x4> ee ?0a ?44 ?50 ? *	cfmvsr	mvf10, ?r4
-0*1e8 <move\+0x8> 4e ?0e ?b4 ?50 ? *	cfmvsrmi	mvf14, ?fp
-0*1ec <move\+0xc> 8e ?0d ?54 ?50 ? *	cfmvsrhi	mvf13, ?r5
-0*1f0 <move\+0x10> 2e ?01 ?64 ?50 ? *	cfmvsrcs	mvf1, ?r6
-0*1f4 <move\+0x14> 6e ?10 ?34 ?50 ? *	cfmvrsvs	r3, ?mvf0
-0*1f8 <move\+0x18> 7e ?1e ?d4 ?50 ? *	cfmvrsvc	sp, ?mvf14
-0*1fc <move\+0x1c> 3e ?1a ?e4 ?50 ? *	cfmvrscc	lr, ?mvf10
-0*200 <move\+0x20> 1e ?1f ?84 ?50 ? *	cfmvrsne	r8, ?mvf15
-0*204 <move\+0x24> de ?1b ?f4 ?50 ? *	cfmvrsle	pc, ?mvf11
-0*208 <move\+0x28> 4e ?02 ?34 ?10 ? *	cfmvdlrmi	mvd2, ?r3
-0*20c <move\+0x2c> 0e ?05 ?d4 ?10 ? *	cfmvdlreq	mvd5, ?sp
-0*210 <move\+0x30> ae ?09 ?e4 ?10 ? *	cfmvdlrge	mvd9, ?lr
-0*214 <move\+0x34> ee ?03 ?84 ?10 ? *	cfmvdlr	mvd3, ?r8
-0*218 <move\+0x38> de ?07 ?f4 ?10 ? *	cfmvdlrle	mvd7, ?pc
-0*21c <move\+0x3c> 1e ?16 ?64 ?10 ? *	cfmvrdlne	r6, ?mvd6
-0*220 <move\+0x40> be ?17 ?04 ?10 ? *	cfmvrdllt	r0, ?mvd7
-0*224 <move\+0x44> 5e ?13 ?74 ?10 ? *	cfmvrdlpl	r7, ?mvd3
-0*228 <move\+0x48> ce ?11 ?14 ?10 ? *	cfmvrdlgt	r1, ?mvd1
-0*22c <move\+0x4c> 8e ?1d ?24 ?10 ? *	cfmvrdlhi	r2, ?mvd13
-0*230 <move\+0x50> 6e ?0b ?64 ?30 ? *	cfmvdhrvs	mvd11, ?r6
-0*234 <move\+0x54> 2e ?09 ?04 ?30 ? *	cfmvdhrcs	mvd9, ?r0
-0*238 <move\+0x58> 5e ?0f ?74 ?30 ? *	cfmvdhrpl	mvd15, ?r7
-0*23c <move\+0x5c> 9e ?04 ?14 ?30 ? *	cfmvdhrls	mvd4, ?r1
-0*240 <move\+0x60> 3e ?08 ?24 ?30 ? *	cfmvdhrcc	mvd8, ?r2
-0*244 <move\+0x64> 7e ?11 ?f4 ?30 ? *	cfmvrdhvc	pc, ?mvd1
-0*248 <move\+0x68> ce ?1b ?94 ?30 ? *	cfmvrdhgt	r9, ?mvd11
-0*24c <move\+0x6c> 0e ?15 ?a4 ?30 ? *	cfmvrdheq	sl, ?mvd5
-0*250 <move\+0x70> ee ?1c ?44 ?30 ? *	cfmvrdh	r4, ?mvd12
-0*254 <move\+0x74> ae ?18 ?b4 ?30 ? *	cfmvrdhge	fp, ?mvd8
-0*258 <move\+0x78> ee ?0d ?f5 ?10 ? *	cfmv64lr	mvdx13, ?pc
-0*25c <move\+0x7c> be ?04 ?95 ?10 ? *	cfmv64lrlt	mvdx4, ?r9
-0*260 <move\+0x80> 9e ?00 ?a5 ?10 ? *	cfmv64lrls	mvdx0, ?sl
-0*264 <move\+0x84> ee ?0a ?45 ?10 ? *	cfmv64lr	mvdx10, ?r4
-0*268 <move\+0x88> 4e ?0e ?b5 ?10 ? *	cfmv64lrmi	mvdx14, ?fp
-0*26c <move\+0x8c> 8e ?17 ?25 ?10 ? *	cfmvr64lhi	r2, ?mvdx7
-0*270 <move\+0x90> 2e ?1c ?c5 ?10 ? *	cfmvr64lcs	ip, ?mvdx12
-0*274 <move\+0x94> 6e ?10 ?35 ?10 ? *	cfmvr64lvs	r3, ?mvdx0
-0*278 <move\+0x98> 7e ?1e ?d5 ?10 ? *	cfmvr64lvc	sp, ?mvdx14
-0*27c <move\+0x9c> 3e ?1a ?e5 ?10 ? *	cfmvr64lcc	lr, ?mvdx10
-0*280 <move\+0xa0> 1e ?08 ?25 ?30 ? *	cfmv64hrne	mvdx8, ?r2
-0*284 <move\+0xa4> de ?06 ?c5 ?30 ? *	cfmv64hrle	mvdx6, ?ip
-0*288 <move\+0xa8> 4e ?02 ?35 ?30 ? *	cfmv64hrmi	mvdx2, ?r3
-0*28c <move\+0xac> 0e ?05 ?d5 ?30 ? *	cfmv64hreq	mvdx5, ?sp
-0*290 <move\+0xb0> ae ?09 ?e5 ?30 ? *	cfmv64hrge	mvdx9, ?lr
-0*294 <move\+0xb4> ee ?18 ?b5 ?30 ? *	cfmvr64h	fp, ?mvdx8
-0*298 <move\+0xb8> de ?12 ?55 ?30 ? *	cfmvr64hle	r5, ?mvdx2
-0*29c <move\+0xbc> 1e ?16 ?65 ?30 ? *	cfmvr64hne	r6, ?mvdx6
-0*2a0 <move\+0xc0> be ?17 ?05 ?30 ? *	cfmvr64hlt	r0, ?mvdx7
-0*2a4 <move\+0xc4> 5e ?13 ?75 ?30 ? *	cfmvr64hpl	r7, ?mvdx3
-0*2a8 <move\+0xc8> ce ?21 ?14 ?40 ? *	cfmval32gt	mvax1, ?mvfx1
-0*2ac <move\+0xcc> 8e ?2d ?34 ?40 ? *	cfmval32hi	mvax3, ?mvfx13
-0*2b0 <move\+0xd0> 6e ?24 ?34 ?40 ? *	cfmval32vs	mvax3, ?mvfx4
-0*2b4 <move\+0xd4> 2e ?20 ?14 ?40 ? *	cfmval32cs	mvax1, ?mvfx0
-0*2b8 <move\+0xd8> 5e ?2a ?34 ?40 ? *	cfmval32pl	mvax3, ?mvfx10
-0*2bc <move\+0xdc> 9e ?11 ?44 ?40 ? *	cfmv32alls	mvfx4, ?mvax1
-0*2c0 <move\+0xe0> 3e ?13 ?84 ?40 ? *	cfmv32alcc	mvfx8, ?mvax3
-0*2c4 <move\+0xe4> 7e ?13 ?24 ?40 ? *	cfmv32alvc	mvfx2, ?mvax3
-0*2c8 <move\+0xe8> ce ?11 ?64 ?40 ? *	cfmv32algt	mvfx6, ?mvax1
-0*2cc <move\+0xec> 0e ?13 ?74 ?40 ? *	cfmv32aleq	mvfx7, ?mvax3
-0*2d0 <move\+0xf0> ee ?2c ?24 ?60 ? *	cfmvam32	mvax2, ?mvfx12
-0*2d4 <move\+0xf4> ae ?28 ?34 ?60 ? *	cfmvam32ge	mvax3, ?mvfx8
-0*2d8 <move\+0xf8> ee ?26 ?24 ?60 ? *	cfmvam32	mvax2, ?mvfx6
-0*2dc <move\+0xfc> be ?22 ?24 ?60 ? *	cfmvam32lt	mvax2, ?mvfx2
-0*2e0 <move\+0x100> 9e ?25 ?04 ?60 ? *	cfmvam32ls	mvax0, ?mvfx5
-0*2e4 <move\+0x104> ee ?12 ?a4 ?60 ? *	cfmv32am	mvfx10, ?mvax2
-0*2e8 <move\+0x108> 4e ?13 ?e4 ?60 ? *	cfmv32ammi	mvfx14, ?mvax3
-0*2ec <move\+0x10c> 8e ?12 ?d4 ?60 ? *	cfmv32amhi	mvfx13, ?mvax2
-0*2f0 <move\+0x110> 2e ?12 ?14 ?60 ? *	cfmv32amcs	mvfx1, ?mvax2
-0*2f4 <move\+0x114> 6e ?10 ?b4 ?60 ? *	cfmv32amvs	mvfx11, ?mvax0
-0*2f8 <move\+0x118> 7e ?2e ?34 ?80 ? *	cfmvah32vc	mvax3, ?mvfx14
-0*2fc <move\+0x11c> 3e ?2a ?04 ?80 ? *	cfmvah32cc	mvax0, ?mvfx10
-0*300 <move\+0x120> 1e ?2f ?14 ?80 ? *	cfmvah32ne	mvax1, ?mvfx15
-0*304 <move\+0x124> de ?2b ?04 ?80 ? *	cfmvah32le	mvax0, ?mvfx11
-0*308 <move\+0x128> 4e ?29 ?04 ?80 ? *	cfmvah32mi	mvax0, ?mvfx9
-0*30c <move\+0x12c> 0e ?13 ?54 ?80 ? *	cfmv32aheq	mvfx5, ?mvax3
-0*310 <move\+0x130> ae ?10 ?94 ?80 ? *	cfmv32ahge	mvfx9, ?mvax0
-0*314 <move\+0x134> ee ?11 ?34 ?80 ? *	cfmv32ah	mvfx3, ?mvax1
-0*318 <move\+0x138> de ?10 ?74 ?80 ? *	cfmv32ahle	mvfx7, ?mvax0
-0*31c <move\+0x13c> 1e ?10 ?c4 ?80 ? *	cfmv32ahne	mvfx12, ?mvax0
-0*320 <move\+0x140> be ?27 ?04 ?a0 ? *	cfmva32lt	mvax0, ?mvfx7
-0*324 <move\+0x144> 5e ?23 ?24 ?a0 ? *	cfmva32pl	mvax2, ?mvfx3
-0*328 <move\+0x148> ce ?21 ?14 ?a0 ? *	cfmva32gt	mvax1, ?mvfx1
-0*32c <move\+0x14c> 8e ?2d ?34 ?a0 ? *	cfmva32hi	mvax3, ?mvfx13
-0*330 <move\+0x150> 6e ?24 ?34 ?a0 ? *	cfmva32vs	mvax3, ?mvfx4
-0*334 <move\+0x154> 2e ?10 ?94 ?a0 ? *	cfmv32acs	mvfx9, ?mvax0
-0*338 <move\+0x158> 5e ?12 ?f4 ?a0 ? *	cfmv32apl	mvfx15, ?mvax2
-0*33c <move\+0x15c> 9e ?11 ?44 ?a0 ? *	cfmv32als	mvfx4, ?mvax1
-0*340 <move\+0x160> 3e ?13 ?84 ?a0 ? *	cfmv32acc	mvfx8, ?mvax3
-0*344 <move\+0x164> 7e ?13 ?24 ?a0 ? *	cfmv32avc	mvfx2, ?mvax3
-0*348 <move\+0x168> ce ?2b ?04 ?c0 ? *	cfmva64gt	mvax0, ?mvdx11
-0*34c <move\+0x16c> 0e ?25 ?14 ?c0 ? *	cfmva64eq	mvax1, ?mvdx5
-0*350 <move\+0x170> ee ?2c ?24 ?c0 ? *	cfmva64	mvax2, ?mvdx12
-0*354 <move\+0x174> ae ?28 ?34 ?c0 ? *	cfmva64ge	mvax3, ?mvdx8
-0*358 <move\+0x178> ee ?26 ?24 ?c0 ? *	cfmva64	mvax2, ?mvdx6
-0*35c <move\+0x17c> be ?10 ?44 ?c0 ? *	cfmv64alt	mvdx4, ?mvax0
-0*360 <move\+0x180> 9e ?11 ?04 ?c0 ? *	cfmv64als	mvdx0, ?mvax1
-0*364 <move\+0x184> ee ?12 ?a4 ?c0 ? *	cfmv64a	mvdx10, ?mvax2
-0*368 <move\+0x188> 4e ?13 ?e4 ?c0 ? *	cfmv64ami	mvdx14, ?mvax3
-0*36c <move\+0x18c> 8e ?12 ?d4 ?c0 ? *	cfmv64ahi	mvdx13, ?mvax2
-0*370 <move\+0x190> 2e ?20 ?c4 ?e0 ? *	cfmvsc32cs	dspsc, ?mvdx12
-0*374 <move\+0x194> 6e ?20 ?04 ?e0 ? *	cfmvsc32vs	dspsc, ?mvdx0
-0*378 <move\+0x198> 7e ?20 ?e4 ?e0 ? *	cfmvsc32vc	dspsc, ?mvdx14
-0*37c <move\+0x19c> 3e ?20 ?a4 ?e0 ? *	cfmvsc32cc	dspsc, ?mvdx10
-0*380 <move\+0x1a0> 1e ?20 ?f4 ?e0 ? *	cfmvsc32ne	dspsc, ?mvdx15
-0*384 <move\+0x1a4> de ?10 ?64 ?e0 ? *	cfmv32scle	mvdx6, ?dspsc
-0*388 <move\+0x1a8> 4e ?10 ?24 ?e0 ? *	cfmv32scmi	mvdx2, ?dspsc
-0*38c <move\+0x1ac> 0e ?10 ?54 ?e0 ? *	cfmv32sceq	mvdx5, ?dspsc
-0*390 <move\+0x1b0> ae ?10 ?94 ?e0 ? *	cfmv32scge	mvdx9, ?dspsc
-0*394 <move\+0x1b4> ee ?10 ?34 ?e0 ? *	cfmv32sc	mvdx3, ?dspsc
-0*398 <move\+0x1b8> de ?02 ?74 ?00 ? *	cfcpysle	mvf7, ?mvf2
-0*39c <move\+0x1bc> 1e ?06 ?c4 ?00 ? *	cfcpysne	mvf12, ?mvf6
-0*3a0 <move\+0x1c0> be ?07 ?04 ?00 ? *	cfcpyslt	mvf0, ?mvf7
-0*3a4 <move\+0x1c4> 5e ?03 ?e4 ?00 ? *	cfcpyspl	mvf14, ?mvf3
-0*3a8 <move\+0x1c8> ce ?01 ?a4 ?00 ? *	cfcpysgt	mvf10, ?mvf1
-0*3ac <move\+0x1cc> 8e ?0d ?f4 ?20 ? *	cfcpydhi	mvd15, ?mvd13
-0*3b0 <move\+0x1d0> 6e ?04 ?b4 ?20 ? *	cfcpydvs	mvd11, ?mvd4
-0*3b4 <move\+0x1d4> 2e ?00 ?94 ?20 ? *	cfcpydcs	mvd9, ?mvd0
-0*3b8 <move\+0x1d8> 5e ?0a ?f4 ?20 ? *	cfcpydpl	mvd15, ?mvd10
-0*3bc <move\+0x1dc> 9e ?0e ?44 ?20 ? *	cfcpydls	mvd4, ?mvd14
+0*1e0 <move> 2e ?09 ?04 ?50 ? *	cfmvsrcs	mvf9, ?r0
+0*1e4 <move\+0x4> 5e ?0f ?74 ?50 ? *	cfmvsrpl	mvf15, ?r7
+0*1e8 <move\+0x8> 9e ?04 ?14 ?50 ? *	cfmvsrls	mvf4, ?r1
+0*1ec <move\+0xc> 3e ?08 ?24 ?50 ? *	cfmvsrcc	mvf8, ?r2
+0*1f0 <move\+0x10> 7e ?02 ?c4 ?50 ? *	cfmvsrvc	mvf2, ?ip
+0*1f4 <move\+0x14> ce ?1b ?94 ?50 ? *	cfmvrsgt	r9, ?mvf11
+0*1f8 <move\+0x18> 0e ?15 ?a4 ?50 ? *	cfmvrseq	sl, ?mvf5
+0*1fc <move\+0x1c> ee ?1c ?44 ?50 ? *	cfmvrs	r4, ?mvf12
+0*200 <move\+0x20> ae ?18 ?b4 ?50 ? *	cfmvrsge	fp, ?mvf8
+0*204 <move\+0x24> ee ?16 ?54 ?50 ? *	cfmvrs	r5, ?mvf6
+0*208 <move\+0x28> be ?04 ?94 ?10 ? *	cfmvdlrlt	mvd4, ?r9
+0*20c <move\+0x2c> 9e ?00 ?a4 ?10 ? *	cfmvdlrls	mvd0, ?sl
+0*210 <move\+0x30> ee ?0a ?44 ?10 ? *	cfmvdlr	mvd10, ?r4
+0*214 <move\+0x34> 4e ?0e ?b4 ?10 ? *	cfmvdlrmi	mvd14, ?fp
+0*218 <move\+0x38> 8e ?0d ?54 ?10 ? *	cfmvdlrhi	mvd13, ?r5
+0*21c <move\+0x3c> 2e ?1c ?c4 ?10 ? *	cfmvrdlcs	ip, ?mvd12
+0*220 <move\+0x40> 6e ?10 ?34 ?10 ? *	cfmvrdlvs	r3, ?mvd0
+0*224 <move\+0x44> 7e ?1e ?d4 ?10 ? *	cfmvrdlvc	sp, ?mvd14
+0*228 <move\+0x48> 3e ?1a ?e4 ?10 ? *	cfmvrdlcc	lr, ?mvd10
+0*22c <move\+0x4c> 1e ?1f ?84 ?10 ? *	cfmvrdlne	r8, ?mvd15
+0*230 <move\+0x50> de ?06 ?c4 ?30 ? *	cfmvdhrle	mvd6, ?ip
+0*234 <move\+0x54> 4e ?02 ?34 ?30 ? *	cfmvdhrmi	mvd2, ?r3
+0*238 <move\+0x58> 0e ?05 ?d4 ?30 ? *	cfmvdhreq	mvd5, ?sp
+0*23c <move\+0x5c> ae ?09 ?e4 ?30 ? *	cfmvdhrge	mvd9, ?lr
+0*240 <move\+0x60> ee ?03 ?84 ?30 ? *	cfmvdhr	mvd3, ?r8
+0*244 <move\+0x64> de ?12 ?54 ?30 ? *	cfmvrdhle	r5, ?mvd2
+0*248 <move\+0x68> 1e ?16 ?64 ?30 ? *	cfmvrdhne	r6, ?mvd6
+0*24c <move\+0x6c> be ?17 ?04 ?30 ? *	cfmvrdhlt	r0, ?mvd7
+0*250 <move\+0x70> 5e ?13 ?74 ?30 ? *	cfmvrdhpl	r7, ?mvd3
+0*254 <move\+0x74> ce ?11 ?14 ?30 ? *	cfmvrdhgt	r1, ?mvd1
+0*258 <move\+0x78> 8e ?0f ?55 ?10 ? *	cfmv64lrhi	mvdx15, ?r5
+0*25c <move\+0x7c> 6e ?0b ?65 ?10 ? *	cfmv64lrvs	mvdx11, ?r6
+0*260 <move\+0x80> 2e ?09 ?05 ?10 ? *	cfmv64lrcs	mvdx9, ?r0
+0*264 <move\+0x84> 5e ?0f ?75 ?10 ? *	cfmv64lrpl	mvdx15, ?r7
+0*268 <move\+0x88> 9e ?04 ?15 ?10 ? *	cfmv64lrls	mvdx4, ?r1
+0*26c <move\+0x8c> 3e ?1d ?85 ?10 ? *	cfmvr64lcc	r8, ?mvdx13
+0*270 <move\+0x90> 7e ?11 ?f5 ?10 ? *	cfmvr64lvc	pc, ?mvdx1
+0*274 <move\+0x94> ce ?1b ?95 ?10 ? *	cfmvr64lgt	r9, ?mvdx11
+0*278 <move\+0x98> 0e ?15 ?a5 ?10 ? *	cfmvr64leq	sl, ?mvdx5
+0*27c <move\+0x9c> ee ?1c ?45 ?10 ? *	cfmvr64l	r4, ?mvdx12
+0*280 <move\+0xa0> ae ?01 ?85 ?30 ? *	cfmv64hrge	mvdx1, ?r8
+0*284 <move\+0xa4> ee ?0d ?f5 ?30 ? *	cfmv64hr	mvdx13, ?pc
+0*288 <move\+0xa8> be ?04 ?95 ?30 ? *	cfmv64hrlt	mvdx4, ?r9
+0*28c <move\+0xac> 9e ?00 ?a5 ?30 ? *	cfmv64hrls	mvdx0, ?sl
+0*290 <move\+0xb0> ee ?0a ?45 ?30 ? *	cfmv64hr	mvdx10, ?r4
+0*294 <move\+0xb4> 4e ?13 ?15 ?30 ? *	cfmvr64hmi	r1, ?mvdx3
+0*298 <move\+0xb8> 8e ?17 ?25 ?30 ? *	cfmvr64hhi	r2, ?mvdx7
+0*29c <move\+0xbc> 2e ?1c ?c5 ?30 ? *	cfmvr64hcs	ip, ?mvdx12
+0*2a0 <move\+0xc0> 6e ?10 ?35 ?30 ? *	cfmvr64hvs	r3, ?mvdx0
+0*2a4 <move\+0xc4> 7e ?1e ?d5 ?30 ? *	cfmvr64hvc	sp, ?mvdx14
+0*2a8 <move\+0xc8> 3e ?2a ?04 ?40 ? *	cfmval32cc	mvax0, ?mvfx10
+0*2ac <move\+0xcc> 1e ?2f ?14 ?40 ? *	cfmval32ne	mvax1, ?mvfx15
+0*2b0 <move\+0xd0> de ?2b ?04 ?40 ? *	cfmval32le	mvax0, ?mvfx11
+0*2b4 <move\+0xd4> 4e ?29 ?04 ?40 ? *	cfmval32mi	mvax0, ?mvfx9
+0*2b8 <move\+0xd8> 0e ?2f ?14 ?40 ? *	cfmval32eq	mvax1, ?mvfx15
+0*2bc <move\+0xdc> ae ?10 ?94 ?40 ? *	cfmv32alge	mvfx9, ?mvax0
+0*2c0 <move\+0xe0> ee ?11 ?34 ?40 ? *	cfmv32al	mvfx3, ?mvax1
+0*2c4 <move\+0xe4> de ?10 ?74 ?40 ? *	cfmv32alle	mvfx7, ?mvax0
+0*2c8 <move\+0xe8> 1e ?10 ?c4 ?40 ? *	cfmv32alne	mvfx12, ?mvax0
+0*2cc <move\+0xec> be ?11 ?04 ?40 ? *	cfmv32allt	mvfx0, ?mvax1
+0*2d0 <move\+0xf0> 5e ?23 ?24 ?60 ? *	cfmvam32pl	mvax2, ?mvfx3
+0*2d4 <move\+0xf4> ce ?21 ?14 ?60 ? *	cfmvam32gt	mvax1, ?mvfx1
+0*2d8 <move\+0xf8> 8e ?2d ?34 ?60 ? *	cfmvam32hi	mvax3, ?mvfx13
+0*2dc <move\+0xfc> 6e ?24 ?34 ?60 ? *	cfmvam32vs	mvax3, ?mvfx4
+0*2e0 <move\+0x100> 2e ?20 ?14 ?60 ? *	cfmvam32cs	mvax1, ?mvfx0
+0*2e4 <move\+0x104> 5e ?12 ?f4 ?60 ? *	cfmv32ampl	mvfx15, ?mvax2
+0*2e8 <move\+0x108> 9e ?11 ?44 ?60 ? *	cfmv32amls	mvfx4, ?mvax1
+0*2ec <move\+0x10c> 3e ?13 ?84 ?60 ? *	cfmv32amcc	mvfx8, ?mvax3
+0*2f0 <move\+0x110> 7e ?13 ?24 ?60 ? *	cfmv32amvc	mvfx2, ?mvax3
+0*2f4 <move\+0x114> ce ?11 ?64 ?60 ? *	cfmv32amgt	mvfx6, ?mvax1
+0*2f8 <move\+0x118> 0e ?25 ?14 ?80 ? *	cfmvah32eq	mvax1, ?mvfx5
+0*2fc <move\+0x11c> ee ?2c ?24 ?80 ? *	cfmvah32	mvax2, ?mvfx12
+0*300 <move\+0x120> ae ?28 ?34 ?80 ? *	cfmvah32ge	mvax3, ?mvfx8
+0*304 <move\+0x124> ee ?26 ?24 ?80 ? *	cfmvah32	mvax2, ?mvfx6
+0*308 <move\+0x128> be ?22 ?24 ?80 ? *	cfmvah32lt	mvax2, ?mvfx2
+0*30c <move\+0x12c> 9e ?11 ?04 ?80 ? *	cfmv32ahls	mvfx0, ?mvax1
+0*310 <move\+0x130> ee ?12 ?a4 ?80 ? *	cfmv32ah	mvfx10, ?mvax2
+0*314 <move\+0x134> 4e ?13 ?e4 ?80 ? *	cfmv32ahmi	mvfx14, ?mvax3
+0*318 <move\+0x138> 8e ?12 ?d4 ?80 ? *	cfmv32ahhi	mvfx13, ?mvax2
+0*31c <move\+0x13c> 2e ?12 ?14 ?80 ? *	cfmv32ahcs	mvfx1, ?mvax2
+0*320 <move\+0x140> 6e ?20 ?14 ?a0 ? *	cfmva32vs	mvax1, ?mvfx0
+0*324 <move\+0x144> 7e ?2e ?34 ?a0 ? *	cfmva32vc	mvax3, ?mvfx14
+0*328 <move\+0x148> 3e ?2a ?04 ?a0 ? *	cfmva32cc	mvax0, ?mvfx10
+0*32c <move\+0x14c> 1e ?2f ?14 ?a0 ? *	cfmva32ne	mvax1, ?mvfx15
+0*330 <move\+0x150> de ?2b ?04 ?a0 ? *	cfmva32le	mvax0, ?mvfx11
+0*334 <move\+0x154> 4e ?11 ?24 ?a0 ? *	cfmv32ami	mvfx2, ?mvax1
+0*338 <move\+0x158> 0e ?13 ?54 ?a0 ? *	cfmv32aeq	mvfx5, ?mvax3
+0*33c <move\+0x15c> ae ?10 ?94 ?a0 ? *	cfmv32age	mvfx9, ?mvax0
+0*340 <move\+0x160> ee ?11 ?34 ?a0 ? *	cfmv32a	mvfx3, ?mvax1
+0*344 <move\+0x164> de ?10 ?74 ?a0 ? *	cfmv32ale	mvfx7, ?mvax0
+0*348 <move\+0x168> 1e ?26 ?24 ?c0 ? *	cfmva64ne	mvax2, ?mvdx6
+0*34c <move\+0x16c> be ?27 ?04 ?c0 ? *	cfmva64lt	mvax0, ?mvdx7
+0*350 <move\+0x170> 5e ?23 ?24 ?c0 ? *	cfmva64pl	mvax2, ?mvdx3
+0*354 <move\+0x174> ce ?21 ?14 ?c0 ? *	cfmva64gt	mvax1, ?mvdx1
+0*358 <move\+0x178> 8e ?2d ?34 ?c0 ? *	cfmva64hi	mvax3, ?mvdx13
+0*35c <move\+0x17c> 6e ?12 ?b4 ?c0 ? *	cfmv64avs	mvdx11, ?mvax2
+0*360 <move\+0x180> 2e ?10 ?94 ?c0 ? *	cfmv64acs	mvdx9, ?mvax0
+0*364 <move\+0x184> 5e ?12 ?f4 ?c0 ? *	cfmv64apl	mvdx15, ?mvax2
+0*368 <move\+0x188> 9e ?11 ?44 ?c0 ? *	cfmv64als	mvdx4, ?mvax1
+0*36c <move\+0x18c> 3e ?13 ?84 ?c0 ? *	cfmv64acc	mvdx8, ?mvax3
+0*370 <move\+0x190> 7e ?20 ?14 ?e0 ? *	cfmvsc32vc	dspsc, ?mvdx1
+0*374 <move\+0x194> ce ?20 ?b4 ?e0 ? *	cfmvsc32gt	dspsc, ?mvdx11
+0*378 <move\+0x198> 0e ?20 ?54 ?e0 ? *	cfmvsc32eq	dspsc, ?mvdx5
+0*37c <move\+0x19c> ee ?20 ?c4 ?e0 ? *	cfmvsc32	dspsc, ?mvdx12
+0*380 <move\+0x1a0> ae ?20 ?84 ?e0 ? *	cfmvsc32ge	dspsc, ?mvdx8
+0*384 <move\+0x1a4> ee ?10 ?d4 ?e0 ? *	cfmv32sc	mvdx13, ?dspsc
+0*388 <move\+0x1a8> be ?10 ?44 ?e0 ? *	cfmv32sclt	mvdx4, ?dspsc
+0*38c <move\+0x1ac> 9e ?10 ?04 ?e0 ? *	cfmv32scls	mvdx0, ?dspsc
+0*390 <move\+0x1b0> ee ?10 ?a4 ?e0 ? *	cfmv32sc	mvdx10, ?dspsc
+0*394 <move\+0x1b4> 4e ?10 ?e4 ?e0 ? *	cfmv32scmi	mvdx14, ?dspsc
+0*398 <move\+0x1b8> 8e ?07 ?d4 ?00 ? *	cfcpyshi	mvf13, ?mvf7
+0*39c <move\+0x1bc> 2e ?0c ?14 ?00 ? *	cfcpyscs	mvf1, ?mvf12
+0*3a0 <move\+0x1c0> 6e ?00 ?b4 ?00 ? *	cfcpysvs	mvf11, ?mvf0
+0*3a4 <move\+0x1c4> 7e ?0e ?54 ?00 ? *	cfcpysvc	mvf5, ?mvf14
+0*3a8 <move\+0x1c8> 3e ?0a ?c4 ?00 ? *	cfcpyscc	mvf12, ?mvf10
+0*3ac <move\+0x1cc> 1e ?0f ?84 ?20 ? *	cfcpydne	mvd8, ?mvd15
+0*3b0 <move\+0x1d0> de ?0b ?64 ?20 ? *	cfcpydle	mvd6, ?mvd11
+0*3b4 <move\+0x1d4> 4e ?09 ?24 ?20 ? *	cfcpydmi	mvd2, ?mvd9
+0*3b8 <move\+0x1d8> 0e ?0f ?54 ?20 ? *	cfcpydeq	mvd5, ?mvd15
+0*3bc <move\+0x1dc> ae ?04 ?94 ?20 ? *	cfcpydge	mvd9, ?mvd4
 # conv:
-0*3c0 <conv> 3e ?0d ?84 ?60 ? *	cfcvtsdcc	mvd8, ?mvf13
-0*3c4 <conv\+0x4> 7e ?01 ?24 ?60 ? *	cfcvtsdvc	mvd2, ?mvf1
-0*3c8 <conv\+0x8> ce ?0b ?64 ?60 ? *	cfcvtsdgt	mvd6, ?mvf11
-0*3cc <conv\+0xc> 0e ?05 ?74 ?60 ? *	cfcvtsdeq	mvd7, ?mvf5
-0*3d0 <conv\+0x10> ee ?0c ?34 ?60 ? *	cfcvtsd	mvd3, ?mvf12
-0*3d4 <conv\+0x14> ae ?08 ?14 ?40 ? *	cfcvtdsge	mvf1, ?mvd8
-0*3d8 <conv\+0x18> ee ?06 ?d4 ?40 ? *	cfcvtds	mvf13, ?mvd6
-0*3dc <conv\+0x1c> be ?02 ?44 ?40 ? *	cfcvtdslt	mvf4, ?mvd2
-0*3e0 <conv\+0x20> 9e ?05 ?04 ?40 ? *	cfcvtdsls	mvf0, ?mvd5
-0*3e4 <conv\+0x24> ee ?09 ?a4 ?40 ? *	cfcvtds	mvf10, ?mvd9
-0*3e8 <conv\+0x28> 4e ?03 ?e4 ?80 ? *	cfcvt32smi	mvf14, ?mvfx3
-0*3ec <conv\+0x2c> 8e ?07 ?d4 ?80 ? *	cfcvt32shi	mvf13, ?mvfx7
-0*3f0 <conv\+0x30> 2e ?0c ?14 ?80 ? *	cfcvt32scs	mvf1, ?mvfx12
-0*3f4 <conv\+0x34> 6e ?00 ?b4 ?80 ? *	cfcvt32svs	mvf11, ?mvfx0
-0*3f8 <conv\+0x38> 7e ?0e ?54 ?80 ? *	cfcvt32svc	mvf5, ?mvfx14
-0*3fc <conv\+0x3c> 3e ?0a ?c4 ?a0 ? *	cfcvt32dcc	mvd12, ?mvfx10
-0*400 <conv\+0x40> 1e ?0f ?84 ?a0 ? *	cfcvt32dne	mvd8, ?mvfx15
-0*404 <conv\+0x44> de ?0b ?64 ?a0 ? *	cfcvt32dle	mvd6, ?mvfx11
-0*408 <conv\+0x48> 4e ?09 ?24 ?a0 ? *	cfcvt32dmi	mvd2, ?mvfx9
-0*40c <conv\+0x4c> 0e ?0f ?54 ?a0 ? *	cfcvt32deq	mvd5, ?mvfx15
-0*410 <conv\+0x50> ae ?04 ?94 ?c0 ? *	cfcvt64sge	mvf9, ?mvdx4
-0*414 <conv\+0x54> ee ?08 ?34 ?c0 ? *	cfcvt64s	mvf3, ?mvdx8
-0*418 <conv\+0x58> de ?02 ?74 ?c0 ? *	cfcvt64sle	mvf7, ?mvdx2
-0*41c <conv\+0x5c> 1e ?06 ?c4 ?c0 ? *	cfcvt64sne	mvf12, ?mvdx6
-0*420 <conv\+0x60> be ?07 ?04 ?c0 ? *	cfcvt64slt	mvf0, ?mvdx7
-0*424 <conv\+0x64> 5e ?03 ?e4 ?e0 ? *	cfcvt64dpl	mvd14, ?mvdx3
-0*428 <conv\+0x68> ce ?01 ?a4 ?e0 ? *	cfcvt64dgt	mvd10, ?mvdx1
-0*42c <conv\+0x6c> 8e ?0d ?f4 ?e0 ? *	cfcvt64dhi	mvd15, ?mvdx13
-0*430 <conv\+0x70> 6e ?04 ?b4 ?e0 ? *	cfcvt64dvs	mvd11, ?mvdx4
-0*434 <conv\+0x74> 2e ?00 ?94 ?e0 ? *	cfcvt64dcs	mvd9, ?mvdx0
-0*438 <conv\+0x78> 5e ?1a ?f5 ?80 ? *	cfcvts32pl	mvfx15, ?mvf10
-0*43c <conv\+0x7c> 9e ?1e ?45 ?80 ? *	cfcvts32ls	mvfx4, ?mvf14
-0*440 <conv\+0x80> 3e ?1d ?85 ?80 ? *	cfcvts32cc	mvfx8, ?mvf13
-0*444 <conv\+0x84> 7e ?11 ?25 ?80 ? *	cfcvts32vc	mvfx2, ?mvf1
-0*448 <conv\+0x88> ce ?1b ?65 ?80 ? *	cfcvts32gt	mvfx6, ?mvf11
-0*44c <conv\+0x8c> 0e ?15 ?75 ?a0 ? *	cfcvtd32eq	mvfx7, ?mvd5
-0*450 <conv\+0x90> ee ?1c ?35 ?a0 ? *	cfcvtd32	mvfx3, ?mvd12
-0*454 <conv\+0x94> ae ?18 ?15 ?a0 ? *	cfcvtd32ge	mvfx1, ?mvd8
-0*458 <conv\+0x98> ee ?16 ?d5 ?a0 ? *	cfcvtd32	mvfx13, ?mvd6
-0*45c <conv\+0x9c> be ?12 ?45 ?a0 ? *	cfcvtd32lt	mvfx4, ?mvd2
-0*460 <conv\+0xa0> 9e ?15 ?05 ?c0 ? *	cftruncs32ls	mvfx0, ?mvf5
-0*464 <conv\+0xa4> ee ?19 ?a5 ?c0 ? *	cftruncs32	mvfx10, ?mvf9
-0*468 <conv\+0xa8> 4e ?13 ?e5 ?c0 ? *	cftruncs32mi	mvfx14, ?mvf3
-0*46c <conv\+0xac> 8e ?17 ?d5 ?c0 ? *	cftruncs32hi	mvfx13, ?mvf7
-0*470 <conv\+0xb0> 2e ?1c ?15 ?c0 ? *	cftruncs32cs	mvfx1, ?mvf12
-0*474 <conv\+0xb4> 6e ?10 ?b5 ?e0 ? *	cftruncd32vs	mvfx11, ?mvd0
-0*478 <conv\+0xb8> 7e ?1e ?55 ?e0 ? *	cftruncd32vc	mvfx5, ?mvd14
-0*47c <conv\+0xbc> 3e ?1a ?c5 ?e0 ? *	cftruncd32cc	mvfx12, ?mvd10
-0*480 <conv\+0xc0> 1e ?1f ?85 ?e0 ? *	cftruncd32ne	mvfx8, ?mvd15
-0*484 <conv\+0xc4> de ?1b ?65 ?e0 ? *	cftruncd32le	mvfx6, ?mvd11
+0*3c0 <conv> ee ?08 ?34 ?60 ? *	cfcvtsd	mvd3, ?mvf8
+0*3c4 <conv\+0x4> de ?02 ?74 ?60 ? *	cfcvtsdle	mvd7, ?mvf2
+0*3c8 <conv\+0x8> 1e ?06 ?c4 ?60 ? *	cfcvtsdne	mvd12, ?mvf6
+0*3cc <conv\+0xc> be ?07 ?04 ?60 ? *	cfcvtsdlt	mvd0, ?mvf7
+0*3d0 <conv\+0x10> 5e ?03 ?e4 ?60 ? *	cfcvtsdpl	mvd14, ?mvf3
+0*3d4 <conv\+0x14> ce ?01 ?a4 ?40 ? *	cfcvtdsgt	mvf10, ?mvd1
+0*3d8 <conv\+0x18> 8e ?0d ?f4 ?40 ? *	cfcvtdshi	mvf15, ?mvd13
+0*3dc <conv\+0x1c> 6e ?04 ?b4 ?40 ? *	cfcvtdsvs	mvf11, ?mvd4
+0*3e0 <conv\+0x20> 2e ?00 ?94 ?40 ? *	cfcvtdscs	mvf9, ?mvd0
+0*3e4 <conv\+0x24> 5e ?0a ?f4 ?40 ? *	cfcvtdspl	mvf15, ?mvd10
+0*3e8 <conv\+0x28> 9e ?0e ?44 ?80 ? *	cfcvt32sls	mvf4, ?mvfx14
+0*3ec <conv\+0x2c> 3e ?0d ?84 ?80 ? *	cfcvt32scc	mvf8, ?mvfx13
+0*3f0 <conv\+0x30> 7e ?01 ?24 ?80 ? *	cfcvt32svc	mvf2, ?mvfx1
+0*3f4 <conv\+0x34> ce ?0b ?64 ?80 ? *	cfcvt32sgt	mvf6, ?mvfx11
+0*3f8 <conv\+0x38> 0e ?05 ?74 ?80 ? *	cfcvt32seq	mvf7, ?mvfx5
+0*3fc <conv\+0x3c> ee ?0c ?34 ?a0 ? *	cfcvt32d	mvd3, ?mvfx12
+0*400 <conv\+0x40> ae ?08 ?14 ?a0 ? *	cfcvt32dge	mvd1, ?mvfx8
+0*404 <conv\+0x44> ee ?06 ?d4 ?a0 ? *	cfcvt32d	mvd13, ?mvfx6
+0*408 <conv\+0x48> be ?02 ?44 ?a0 ? *	cfcvt32dlt	mvd4, ?mvfx2
+0*40c <conv\+0x4c> 9e ?05 ?04 ?a0 ? *	cfcvt32dls	mvd0, ?mvfx5
+0*410 <conv\+0x50> ee ?09 ?a4 ?c0 ? *	cfcvt64s	mvf10, ?mvdx9
+0*414 <conv\+0x54> 4e ?03 ?e4 ?c0 ? *	cfcvt64smi	mvf14, ?mvdx3
+0*418 <conv\+0x58> 8e ?07 ?d4 ?c0 ? *	cfcvt64shi	mvf13, ?mvdx7
+0*41c <conv\+0x5c> 2e ?0c ?14 ?c0 ? *	cfcvt64scs	mvf1, ?mvdx12
+0*420 <conv\+0x60> 6e ?00 ?b4 ?c0 ? *	cfcvt64svs	mvf11, ?mvdx0
+0*424 <conv\+0x64> 7e ?0e ?54 ?e0 ? *	cfcvt64dvc	mvd5, ?mvdx14
+0*428 <conv\+0x68> 3e ?0a ?c4 ?e0 ? *	cfcvt64dcc	mvd12, ?mvdx10
+0*42c <conv\+0x6c> 1e ?0f ?84 ?e0 ? *	cfcvt64dne	mvd8, ?mvdx15
+0*430 <conv\+0x70> de ?0b ?64 ?e0 ? *	cfcvt64dle	mvd6, ?mvdx11
+0*434 <conv\+0x74> 4e ?09 ?24 ?e0 ? *	cfcvt64dmi	mvd2, ?mvdx9
+0*438 <conv\+0x78> 0e ?1f ?55 ?80 ? *	cfcvts32eq	mvfx5, ?mvf15
+0*43c <conv\+0x7c> ae ?14 ?95 ?80 ? *	cfcvts32ge	mvfx9, ?mvf4
+0*440 <conv\+0x80> ee ?18 ?35 ?80 ? *	cfcvts32	mvfx3, ?mvf8
+0*444 <conv\+0x84> de ?12 ?75 ?80 ? *	cfcvts32le	mvfx7, ?mvf2
+0*448 <conv\+0x88> 1e ?16 ?c5 ?80 ? *	cfcvts32ne	mvfx12, ?mvf6
+0*44c <conv\+0x8c> be ?17 ?05 ?a0 ? *	cfcvtd32lt	mvfx0, ?mvd7
+0*450 <conv\+0x90> 5e ?13 ?e5 ?a0 ? *	cfcvtd32pl	mvfx14, ?mvd3
+0*454 <conv\+0x94> ce ?11 ?a5 ?a0 ? *	cfcvtd32gt	mvfx10, ?mvd1
+0*458 <conv\+0x98> 8e ?1d ?f5 ?a0 ? *	cfcvtd32hi	mvfx15, ?mvd13
+0*45c <conv\+0x9c> 6e ?14 ?b5 ?a0 ? *	cfcvtd32vs	mvfx11, ?mvd4
+0*460 <conv\+0xa0> 2e ?10 ?95 ?c0 ? *	cftruncs32cs	mvfx9, ?mvf0
+0*464 <conv\+0xa4> 5e ?1a ?f5 ?c0 ? *	cftruncs32pl	mvfx15, ?mvf10
+0*468 <conv\+0xa8> 9e ?1e ?45 ?c0 ? *	cftruncs32ls	mvfx4, ?mvf14
+0*46c <conv\+0xac> 3e ?1d ?85 ?c0 ? *	cftruncs32cc	mvfx8, ?mvf13
+0*470 <conv\+0xb0> 7e ?11 ?25 ?c0 ? *	cftruncs32vc	mvfx2, ?mvf1
+0*474 <conv\+0xb4> ce ?1b ?65 ?e0 ? *	cftruncd32gt	mvfx6, ?mvd11
+0*478 <conv\+0xb8> 0e ?15 ?75 ?e0 ? *	cftruncd32eq	mvfx7, ?mvd5
+0*47c <conv\+0xbc> ee ?1c ?35 ?e0 ? *	cftruncd32	mvfx3, ?mvd12
+0*480 <conv\+0xc0> ae ?18 ?15 ?e0 ? *	cftruncd32ge	mvfx1, ?mvd8
+0*484 <conv\+0xc4> ee ?16 ?d5 ?e0 ? *	cftruncd32	mvfx13, ?mvd6
 # shift:
-0*488 <shift> 4e ?02 ?05 ?59 ? *	cfrshl32mi	mvfx2, ?mvfx9, ?r0
-0*48c <shift\+0x4> ee ?0a ?e5 ?59 ? *	cfrshl32	mvfx10, ?mvfx9, ?lr
-0*490 <shift\+0x8> 3e ?08 ?55 ?5d ? *	cfrshl32cc	mvfx8, ?mvfx13, ?r5
-0*494 <shift\+0xc> 1e ?0c ?35 ?56 ? *	cfrshl32ne	mvfx12, ?mvfx6, ?r3
-0*498 <shift\+0x10> 7e ?05 ?45 ?5e ? *	cfrshl32vc	mvfx5, ?mvfx14, ?r4
-0*49c <shift\+0x14> ae ?01 ?25 ?78 ? *	cfrshl64ge	mvdx1, ?mvdx8, ?r2
-0*4a0 <shift\+0x18> 6e ?0b ?95 ?74 ? *	cfrshl64vs	mvdx11, ?mvdx4, ?r9
-0*4a4 <shift\+0x1c> 0e ?05 ?75 ?7f ? *	cfrshl64eq	mvdx5, ?mvdx15, ?r7
-0*4a8 <shift\+0x20> 4e ?0e ?85 ?73 ? *	cfrshl64mi	mvdx14, ?mvdx3, ?r8
-0*4ac <shift\+0x24> 7e ?02 ?65 ?71 ? *	cfrshl64vc	mvdx2, ?mvdx1, ?r6
-0*4b0 <shift\+0x28> be ?07 ?05 ?80 ? *	cfsh32lt	mvfx0, ?mvfx7, ?#-64
-0*4b4 <shift\+0x2c> 3e ?0a ?c5 ?cc ? *	cfsh32cc	mvfx12, ?mvfx10, ?#-20
-0*4b8 <shift\+0x30> ee ?06 ?d5 ?48 ? *	cfsh32	mvfx13, ?mvfx6, ?#40
-0*4bc <shift\+0x34> 2e ?00 ?95 ?ef ? *	cfsh32cs	mvfx9, ?mvfx0, ?#-1
-0*4c0 <shift\+0x38> ae ?04 ?95 ?28 ? *	cfsh32ge	mvfx9, ?mvfx4, ?#24
-0*4c4 <shift\+0x3c> 8e ?27 ?d5 ?41 ? *	cfsh64hi	mvdx13, ?mvdx7, ?#33
-0*4c8 <shift\+0x40> ce ?2b ?65 ?00 ? *	cfsh64gt	mvdx6, ?mvdx11, ?#0
-0*4cc <shift\+0x44> 5e ?23 ?e5 ?40 ? *	cfsh64pl	mvdx14, ?mvdx3, ?#32
-0*4d0 <shift\+0x48> 1e ?2f ?85 ?c1 ? *	cfsh64ne	mvdx8, ?mvdx15, ?#-31
-0*4d4 <shift\+0x4c> be ?22 ?45 ?01 ? *	cfsh64lt	mvdx4, ?mvdx2, ?#1
+0*488 <shift> be ?04 ?35 ?52 ? *	cfrshl32lt	mvfx4, ?mvfx2, ?r3
+0*48c <shift\+0x4> 5e ?0f ?45 ?5a ? *	cfrshl32pl	mvfx15, ?mvfx10, ?r4
+0*490 <shift\+0x8> ee ?03 ?25 ?58 ? *	cfrshl32	mvfx3, ?mvfx8, ?r2
+0*494 <shift\+0xc> 2e ?01 ?95 ?5c ? *	cfrshl32cs	mvfx1, ?mvfx12, ?r9
+0*498 <shift\+0x10> 0e ?07 ?75 ?55 ? *	cfrshl32eq	mvfx7, ?mvfx5, ?r7
+0*49c <shift\+0x14> ce ?0a ?85 ?71 ? *	cfrshl64gt	mvdx10, ?mvdx1, ?r8
+0*4a0 <shift\+0x18> de ?06 ?65 ?7b ? *	cfrshl64le	mvdx6, ?mvdx11, ?r6
+0*4a4 <shift\+0x1c> 9e ?00 ?d5 ?75 ? *	cfrshl64ls	mvdx0, ?mvdx5, ?sp
+0*4a8 <shift\+0x20> 9e ?04 ?b5 ?7e ? *	cfrshl64ls	mvdx4, ?mvdx14, ?fp
+0*4ac <shift\+0x24> de ?07 ?c5 ?72 ? *	cfrshl64le	mvdx7, ?mvdx2, ?ip
+0*4b0 <shift\+0x28> 6e ?00 ?b5 ?ef ? *	cfsh32vs	mvfx11, ?mvfx0, ?#-1
+0*4b4 <shift\+0x2c> ee ?0c ?35 ?28 ? *	cfsh32	mvfx3, ?mvfx12, ?#24
+0*4b8 <shift\+0x30> 8e ?0d ?f5 ?41 ? *	cfsh32hi	mvfx15, ?mvfx13, ?#33
+0*4bc <shift\+0x34> 4e ?09 ?25 ?00 ? *	cfsh32mi	mvfx2, ?mvfx9, ?#0
+0*4c0 <shift\+0x38> ee ?09 ?a5 ?40 ? *	cfsh32	mvfx10, ?mvfx9, ?#32
+0*4c4 <shift\+0x3c> 3e ?2d ?85 ?c1 ? *	cfsh64cc	mvdx8, ?mvdx13, ?#-31
+0*4c8 <shift\+0x40> 1e ?26 ?c5 ?01 ? *	cfsh64ne	mvdx12, ?mvdx6, ?#1
+0*4cc <shift\+0x44> 7e ?2e ?55 ?c0 ? *	cfsh64vc	mvdx5, ?mvdx14, ?#-32
+0*4d0 <shift\+0x48> ae ?28 ?15 ?c5 ? *	cfsh64ge	mvdx1, ?mvdx8, ?#-27
+0*4d4 <shift\+0x4c> 6e ?24 ?b5 ?eb ? *	cfsh64vs	mvdx11, ?mvdx4, ?#-5
 # comp:
-0*4d8 <comp> 5e ?1a ?d4 ?99 ? *	cfcmpspl	sp, ?mvf10, ?mvf9
-0*4dc <comp\+0x4> ee ?18 ?b4 ?9d ? *	cfcmps	fp, ?mvf8, ?mvf13
-0*4e0 <comp\+0x8> 2e ?1c ?c4 ?96 ? *	cfcmpscs	ip, ?mvf12, ?mvf6
-0*4e4 <comp\+0xc> 0e ?15 ?a4 ?9e ? *	cfcmpseq	sl, ?mvf5, ?mvf14
-0*4e8 <comp\+0x10> ce ?11 ?14 ?98 ? *	cfcmpsgt	r1, ?mvf1, ?mvf8
-0*4ec <comp\+0x14> de ?1b ?f4 ?b4 ? *	cfcmpdle	pc, ?mvd11, ?mvd4
-0*4f0 <comp\+0x18> 9e ?15 ?04 ?bf ? *	cfcmpdls	r0, ?mvd5, ?mvd15
-0*4f4 <comp\+0x1c> 9e ?1e ?e4 ?b3 ? *	cfcmpdls	lr, ?mvd14, ?mvd3
-0*4f8 <comp\+0x20> de ?12 ?54 ?b1 ? *	cfcmpdle	r5, ?mvd2, ?mvd1
-0*4fc <comp\+0x24> 6e ?10 ?34 ?b7 ? *	cfcmpdvs	r3, ?mvd0, ?mvd7
-0*500 <comp\+0x28> ee ?1c ?45 ?9a ? *	cfcmp32	r4, ?mvfx12, ?mvfx10
-0*504 <comp\+0x2c> 8e ?1d ?25 ?96 ? *	cfcmp32hi	r2, ?mvfx13, ?mvfx6
-0*508 <comp\+0x30> 4e ?19 ?95 ?90 ? *	cfcmp32mi	r9, ?mvfx9, ?mvfx0
-0*50c <comp\+0x34> ee ?19 ?75 ?94 ? *	cfcmp32	r7, ?mvfx9, ?mvfx4
-0*510 <comp\+0x38> 3e ?1d ?85 ?97 ? *	cfcmp32cc	r8, ?mvfx13, ?mvfx7
-0*514 <comp\+0x3c> 1e ?16 ?65 ?bb ? *	cfcmp64ne	r6, ?mvdx6, ?mvdx11
-0*518 <comp\+0x40> 7e ?1e ?d5 ?b3 ? *	cfcmp64vc	sp, ?mvdx14, ?mvdx3
-0*51c <comp\+0x44> ae ?18 ?b5 ?bf ? *	cfcmp64ge	fp, ?mvdx8, ?mvdx15
-0*520 <comp\+0x48> 6e ?14 ?c5 ?b2 ? *	cfcmp64vs	ip, ?mvdx4, ?mvdx2
-0*524 <comp\+0x4c> 0e ?1f ?a5 ?ba ? *	cfcmp64eq	sl, ?mvdx15, ?mvdx10
+0*4d8 <comp> 0e ?1f ?a4 ?9a ? *	cfcmpseq	sl, ?mvf15, ?mvf10
+0*4dc <comp\+0x4> 4e ?13 ?14 ?98 ? *	cfcmpsmi	r1, ?mvf3, ?mvf8
+0*4e0 <comp\+0x8> 7e ?11 ?f4 ?9c ? *	cfcmpsvc	pc, ?mvf1, ?mvf12
+0*4e4 <comp\+0xc> be ?17 ?04 ?95 ? *	cfcmpslt	r0, ?mvf7, ?mvf5
+0*4e8 <comp\+0x10> 3e ?1a ?e4 ?91 ? *	cfcmpscc	lr, ?mvf10, ?mvf1
+0*4ec <comp\+0x14> ee ?16 ?54 ?bb ? *	cfcmpd	r5, ?mvd6, ?mvd11
+0*4f0 <comp\+0x18> 2e ?10 ?34 ?b5 ? *	cfcmpdcs	r3, ?mvd0, ?mvd5
+0*4f4 <comp\+0x1c> ae ?14 ?44 ?be ? *	cfcmpdge	r4, ?mvd4, ?mvd14
+0*4f8 <comp\+0x20> 8e ?17 ?24 ?b2 ? *	cfcmpdhi	r2, ?mvd7, ?mvd2
+0*4fc <comp\+0x24> ce ?1b ?94 ?b0 ? *	cfcmpdgt	r9, ?mvd11, ?mvd0
+0*500 <comp\+0x28> 5e ?13 ?75 ?9c ? *	cfcmp32pl	r7, ?mvfx3, ?mvfx12
+0*504 <comp\+0x2c> 1e ?1f ?85 ?9d ? *	cfcmp32ne	r8, ?mvfx15, ?mvfx13
+0*508 <comp\+0x30> be ?12 ?65 ?99 ? *	cfcmp32lt	r6, ?mvfx2, ?mvfx9
+0*50c <comp\+0x34> 5e ?1a ?d5 ?99 ? *	cfcmp32pl	sp, ?mvfx10, ?mvfx9
+0*510 <comp\+0x38> ee ?18 ?b5 ?9d ? *	cfcmp32	fp, ?mvfx8, ?mvfx13
+0*514 <comp\+0x3c> 2e ?1c ?c5 ?b6 ? *	cfcmp64cs	ip, ?mvdx12, ?mvdx6
+0*518 <comp\+0x40> 0e ?15 ?a5 ?be ? *	cfcmp64eq	sl, ?mvdx5, ?mvdx14
+0*51c <comp\+0x44> ce ?11 ?15 ?b8 ? *	cfcmp64gt	r1, ?mvdx1, ?mvdx8
+0*520 <comp\+0x48> de ?1b ?f5 ?b4 ? *	cfcmp64le	pc, ?mvdx11, ?mvdx4
+0*524 <comp\+0x4c> 9e ?15 ?05 ?bf ? *	cfcmp64ls	r0, ?mvdx5, ?mvdx15
 # fp_arith:
-0*528 <fp_arith> 4e ?33 ?e4 ?00 ? *	cfabssmi	mvf14, ?mvf3
-0*52c <fp_arith\+0x4> 8e ?37 ?d4 ?00 ? *	cfabsshi	mvf13, ?mvf7
-0*530 <fp_arith\+0x8> 2e ?3c ?14 ?00 ? *	cfabsscs	mvf1, ?mvf12
-0*534 <fp_arith\+0xc> 6e ?30 ?b4 ?00 ? *	cfabssvs	mvf11, ?mvf0
-0*538 <fp_arith\+0x10> 7e ?3e ?54 ?00 ? *	cfabssvc	mvf5, ?mvf14
-0*53c <fp_arith\+0x14> 3e ?3a ?c4 ?20 ? *	cfabsdcc	mvd12, ?mvd10
-0*540 <fp_arith\+0x18> 1e ?3f ?84 ?20 ? *	cfabsdne	mvd8, ?mvd15
-0*544 <fp_arith\+0x1c> de ?3b ?64 ?20 ? *	cfabsdle	mvd6, ?mvd11
-0*548 <fp_arith\+0x20> 4e ?39 ?24 ?20 ? *	cfabsdmi	mvd2, ?mvd9
-0*54c <fp_arith\+0x24> 0e ?3f ?54 ?20 ? *	cfabsdeq	mvd5, ?mvd15
-0*550 <fp_arith\+0x28> ae ?34 ?94 ?40 ? *	cfnegsge	mvf9, ?mvf4
-0*554 <fp_arith\+0x2c> ee ?38 ?34 ?40 ? *	cfnegs	mvf3, ?mvf8
-0*558 <fp_arith\+0x30> de ?32 ?74 ?40 ? *	cfnegsle	mvf7, ?mvf2
-0*55c <fp_arith\+0x34> 1e ?36 ?c4 ?40 ? *	cfnegsne	mvf12, ?mvf6
-0*560 <fp_arith\+0x38> be ?37 ?04 ?40 ? *	cfnegslt	mvf0, ?mvf7
-0*564 <fp_arith\+0x3c> 5e ?33 ?e4 ?60 ? *	cfnegdpl	mvd14, ?mvd3
-0*568 <fp_arith\+0x40> ce ?31 ?a4 ?60 ? *	cfnegdgt	mvd10, ?mvd1
-0*56c <fp_arith\+0x44> 8e ?3d ?f4 ?60 ? *	cfnegdhi	mvd15, ?mvd13
-0*570 <fp_arith\+0x48> 6e ?34 ?b4 ?60 ? *	cfnegdvs	mvd11, ?mvd4
-0*574 <fp_arith\+0x4c> 2e ?30 ?94 ?60 ? *	cfnegdcs	mvd9, ?mvd0
-0*578 <fp_arith\+0x50> 5e ?3a ?f4 ?89 ? *	cfaddspl	mvf15, ?mvf10, ?mvf9
-0*57c <fp_arith\+0x54> ee ?38 ?34 ?8d ? *	cfadds	mvf3, ?mvf8, ?mvf13
-0*580 <fp_arith\+0x58> 2e ?3c ?14 ?86 ? *	cfaddscs	mvf1, ?mvf12, ?mvf6
-0*584 <fp_arith\+0x5c> 0e ?35 ?74 ?8e ? *	cfaddseq	mvf7, ?mvf5, ?mvf14
-0*588 <fp_arith\+0x60> ce ?31 ?a4 ?88 ? *	cfaddsgt	mvf10, ?mvf1, ?mvf8
-0*58c <fp_arith\+0x64> de ?3b ?64 ?a4 ? *	cfadddle	mvd6, ?mvd11, ?mvd4
-0*590 <fp_arith\+0x68> 9e ?35 ?04 ?af ? *	cfadddls	mvd0, ?mvd5, ?mvd15
-0*594 <fp_arith\+0x6c> 9e ?3e ?44 ?a3 ? *	cfadddls	mvd4, ?mvd14, ?mvd3
-0*598 <fp_arith\+0x70> de ?32 ?74 ?a1 ? *	cfadddle	mvd7, ?mvd2, ?mvd1
-0*59c <fp_arith\+0x74> 6e ?30 ?b4 ?a7 ? *	cfadddvs	mvd11, ?mvd0, ?mvd7
-0*5a0 <fp_arith\+0x78> ee ?3c ?34 ?ca ? *	cfsubs	mvf3, ?mvf12, ?mvf10
-0*5a4 <fp_arith\+0x7c> 8e ?3d ?f4 ?c6 ? *	cfsubshi	mvf15, ?mvf13, ?mvf6
-0*5a8 <fp_arith\+0x80> 4e ?39 ?24 ?c0 ? *	cfsubsmi	mvf2, ?mvf9, ?mvf0
-0*5ac <fp_arith\+0x84> ee ?39 ?a4 ?c4 ? *	cfsubs	mvf10, ?mvf9, ?mvf4
-0*5b0 <fp_arith\+0x88> 3e ?3d ?84 ?c7 ? *	cfsubscc	mvf8, ?mvf13, ?mvf7
-0*5b4 <fp_arith\+0x8c> 1e ?36 ?c4 ?eb ? *	cfsubdne	mvd12, ?mvd6, ?mvd11
-0*5b8 <fp_arith\+0x90> 7e ?3e ?54 ?e3 ? *	cfsubdvc	mvd5, ?mvd14, ?mvd3
-0*5bc <fp_arith\+0x94> ae ?38 ?14 ?ef ? *	cfsubdge	mvd1, ?mvd8, ?mvd15
-0*5c0 <fp_arith\+0x98> 6e ?34 ?b4 ?e2 ? *	cfsubdvs	mvd11, ?mvd4, ?mvd2
-0*5c4 <fp_arith\+0x9c> 0e ?3f ?54 ?ea ? *	cfsubdeq	mvd5, ?mvd15, ?mvd10
-0*5c8 <fp_arith\+0xa0> 4e ?13 ?e4 ?08 ? *	cfmulsmi	mvf14, ?mvf3, ?mvf8
-0*5cc <fp_arith\+0xa4> 7e ?11 ?24 ?0c ? *	cfmulsvc	mvf2, ?mvf1, ?mvf12
-0*5d0 <fp_arith\+0xa8> be ?17 ?04 ?05 ? *	cfmulslt	mvf0, ?mvf7, ?mvf5
-0*5d4 <fp_arith\+0xac> 3e ?1a ?c4 ?01 ? *	cfmulscc	mvf12, ?mvf10, ?mvf1
-0*5d8 <fp_arith\+0xb0> ee ?16 ?d4 ?0b ? *	cfmuls	mvf13, ?mvf6, ?mvf11
-0*5dc <fp_arith\+0xb4> 2e ?10 ?94 ?25 ? *	cfmuldcs	mvd9, ?mvd0, ?mvd5
-0*5e0 <fp_arith\+0xb8> ae ?14 ?94 ?2e ? *	cfmuldge	mvd9, ?mvd4, ?mvd14
-0*5e4 <fp_arith\+0xbc> 8e ?17 ?d4 ?22 ? *	cfmuldhi	mvd13, ?mvd7, ?mvd2
-0*5e8 <fp_arith\+0xc0> ce ?1b ?64 ?20 ? *	cfmuldgt	mvd6, ?mvd11, ?mvd0
-0*5ec <fp_arith\+0xc4> 5e ?13 ?e4 ?2c ? *	cfmuldpl	mvd14, ?mvd3, ?mvd12
+0*528 <fp_arith> 9e ?3e ?44 ?00 ? *	cfabssls	mvf4, ?mvf14
+0*52c <fp_arith\+0x4> 3e ?3d ?84 ?00 ? *	cfabsscc	mvf8, ?mvf13
+0*530 <fp_arith\+0x8> 7e ?31 ?24 ?00 ? *	cfabssvc	mvf2, ?mvf1
+0*534 <fp_arith\+0xc> ce ?3b ?64 ?00 ? *	cfabssgt	mvf6, ?mvf11
+0*538 <fp_arith\+0x10> 0e ?35 ?74 ?00 ? *	cfabsseq	mvf7, ?mvf5
+0*53c <fp_arith\+0x14> ee ?3c ?34 ?20 ? *	cfabsd	mvd3, ?mvd12
+0*540 <fp_arith\+0x18> ae ?38 ?14 ?20 ? *	cfabsdge	mvd1, ?mvd8
+0*544 <fp_arith\+0x1c> ee ?36 ?d4 ?20 ? *	cfabsd	mvd13, ?mvd6
+0*548 <fp_arith\+0x20> be ?32 ?44 ?20 ? *	cfabsdlt	mvd4, ?mvd2
+0*54c <fp_arith\+0x24> 9e ?35 ?04 ?20 ? *	cfabsdls	mvd0, ?mvd5
+0*550 <fp_arith\+0x28> ee ?39 ?a4 ?40 ? *	cfnegs	mvf10, ?mvf9
+0*554 <fp_arith\+0x2c> 4e ?33 ?e4 ?40 ? *	cfnegsmi	mvf14, ?mvf3
+0*558 <fp_arith\+0x30> 8e ?37 ?d4 ?40 ? *	cfnegshi	mvf13, ?mvf7
+0*55c <fp_arith\+0x34> 2e ?3c ?14 ?40 ? *	cfnegscs	mvf1, ?mvf12
+0*560 <fp_arith\+0x38> 6e ?30 ?b4 ?40 ? *	cfnegsvs	mvf11, ?mvf0
+0*564 <fp_arith\+0x3c> 7e ?3e ?54 ?60 ? *	cfnegdvc	mvd5, ?mvd14
+0*568 <fp_arith\+0x40> 3e ?3a ?c4 ?60 ? *	cfnegdcc	mvd12, ?mvd10
+0*56c <fp_arith\+0x44> 1e ?3f ?84 ?60 ? *	cfnegdne	mvd8, ?mvd15
+0*570 <fp_arith\+0x48> de ?3b ?64 ?60 ? *	cfnegdle	mvd6, ?mvd11
+0*574 <fp_arith\+0x4c> 4e ?39 ?24 ?60 ? *	cfnegdmi	mvd2, ?mvd9
+0*578 <fp_arith\+0x50> 0e ?3f ?54 ?8a ? *	cfaddseq	mvf5, ?mvf15, ?mvf10
+0*57c <fp_arith\+0x54> 4e ?33 ?e4 ?88 ? *	cfaddsmi	mvf14, ?mvf3, ?mvf8
+0*580 <fp_arith\+0x58> 7e ?31 ?24 ?8c ? *	cfaddsvc	mvf2, ?mvf1, ?mvf12
+0*584 <fp_arith\+0x5c> be ?37 ?04 ?85 ? *	cfaddslt	mvf0, ?mvf7, ?mvf5
+0*588 <fp_arith\+0x60> 3e ?3a ?c4 ?81 ? *	cfaddscc	mvf12, ?mvf10, ?mvf1
+0*58c <fp_arith\+0x64> ee ?36 ?d4 ?ab ? *	cfaddd	mvd13, ?mvd6, ?mvd11
+0*590 <fp_arith\+0x68> 2e ?30 ?94 ?a5 ? *	cfadddcs	mvd9, ?mvd0, ?mvd5
+0*594 <fp_arith\+0x6c> ae ?34 ?94 ?ae ? *	cfadddge	mvd9, ?mvd4, ?mvd14
+0*598 <fp_arith\+0x70> 8e ?37 ?d4 ?a2 ? *	cfadddhi	mvd13, ?mvd7, ?mvd2
+0*59c <fp_arith\+0x74> ce ?3b ?64 ?a0 ? *	cfadddgt	mvd6, ?mvd11, ?mvd0
+0*5a0 <fp_arith\+0x78> 5e ?33 ?e4 ?cc ? *	cfsubspl	mvf14, ?mvf3, ?mvf12
+0*5a4 <fp_arith\+0x7c> 1e ?3f ?84 ?cd ? *	cfsubsne	mvf8, ?mvf15, ?mvf13
+0*5a8 <fp_arith\+0x80> be ?32 ?44 ?c9 ? *	cfsubslt	mvf4, ?mvf2, ?mvf9
+0*5ac <fp_arith\+0x84> 5e ?3a ?f4 ?c9 ? *	cfsubspl	mvf15, ?mvf10, ?mvf9
+0*5b0 <fp_arith\+0x88> ee ?38 ?34 ?cd ? *	cfsubs	mvf3, ?mvf8, ?mvf13
+0*5b4 <fp_arith\+0x8c> 2e ?3c ?14 ?e6 ? *	cfsubdcs	mvd1, ?mvd12, ?mvd6
+0*5b8 <fp_arith\+0x90> 0e ?35 ?74 ?ee ? *	cfsubdeq	mvd7, ?mvd5, ?mvd14
+0*5bc <fp_arith\+0x94> ce ?31 ?a4 ?e8 ? *	cfsubdgt	mvd10, ?mvd1, ?mvd8
+0*5c0 <fp_arith\+0x98> de ?3b ?64 ?e4 ? *	cfsubdle	mvd6, ?mvd11, ?mvd4
+0*5c4 <fp_arith\+0x9c> 9e ?35 ?04 ?ef ? *	cfsubdls	mvd0, ?mvd5, ?mvd15
+0*5c8 <fp_arith\+0xa0> 9e ?1e ?44 ?03 ? *	cfmulsls	mvf4, ?mvf14, ?mvf3
+0*5cc <fp_arith\+0xa4> de ?12 ?74 ?01 ? *	cfmulsle	mvf7, ?mvf2, ?mvf1
+0*5d0 <fp_arith\+0xa8> 6e ?10 ?b4 ?07 ? *	cfmulsvs	mvf11, ?mvf0, ?mvf7
+0*5d4 <fp_arith\+0xac> ee ?1c ?34 ?0a ? *	cfmuls	mvf3, ?mvf12, ?mvf10
+0*5d8 <fp_arith\+0xb0> 8e ?1d ?f4 ?06 ? *	cfmulshi	mvf15, ?mvf13, ?mvf6
+0*5dc <fp_arith\+0xb4> 4e ?19 ?24 ?20 ? *	cfmuldmi	mvd2, ?mvd9, ?mvd0
+0*5e0 <fp_arith\+0xb8> ee ?19 ?a4 ?24 ? *	cfmuld	mvd10, ?mvd9, ?mvd4
+0*5e4 <fp_arith\+0xbc> 3e ?1d ?84 ?27 ? *	cfmuldcc	mvd8, ?mvd13, ?mvd7
+0*5e8 <fp_arith\+0xc0> 1e ?16 ?c4 ?2b ? *	cfmuldne	mvd12, ?mvd6, ?mvd11
+0*5ec <fp_arith\+0xc4> 7e ?1e ?54 ?23 ? *	cfmuldvc	mvd5, ?mvd14, ?mvd3
 # int_arith:
-0*5f0 <int_arith> 1e ?3f ?85 ?00 ? *	cfabs32ne	mvfx8, ?mvfx15
-0*5f4 <int_arith\+0x4> de ?3b ?65 ?00 ? *	cfabs32le	mvfx6, ?mvfx11
-0*5f8 <int_arith\+0x8> 4e ?39 ?25 ?00 ? *	cfabs32mi	mvfx2, ?mvfx9
-0*5fc <int_arith\+0xc> 0e ?3f ?55 ?00 ? *	cfabs32eq	mvfx5, ?mvfx15
-0*600 <int_arith\+0x10> ae ?34 ?95 ?00 ? *	cfabs32ge	mvfx9, ?mvfx4
-0*604 <int_arith\+0x14> ee ?38 ?35 ?20 ? *	cfabs64	mvdx3, ?mvdx8
-0*608 <int_arith\+0x18> de ?32 ?75 ?20 ? *	cfabs64le	mvdx7, ?mvdx2
-0*60c <int_arith\+0x1c> 1e ?36 ?c5 ?20 ? *	cfabs64ne	mvdx12, ?mvdx6
-0*610 <int_arith\+0x20> be ?37 ?05 ?20 ? *	cfabs64lt	mvdx0, ?mvdx7
-0*614 <int_arith\+0x24> 5e ?33 ?e5 ?20 ? *	cfabs64pl	mvdx14, ?mvdx3
-0*618 <int_arith\+0x28> ce ?31 ?a5 ?40 ? *	cfneg32gt	mvfx10, ?mvfx1
-0*61c <int_arith\+0x2c> 8e ?3d ?f5 ?40 ? *	cfneg32hi	mvfx15, ?mvfx13
-0*620 <int_arith\+0x30> 6e ?34 ?b5 ?40 ? *	cfneg32vs	mvfx11, ?mvfx4
-0*624 <int_arith\+0x34> 2e ?30 ?95 ?40 ? *	cfneg32cs	mvfx9, ?mvfx0
-0*628 <int_arith\+0x38> 5e ?3a ?f5 ?40 ? *	cfneg32pl	mvfx15, ?mvfx10
-0*62c <int_arith\+0x3c> 9e ?3e ?45 ?60 ? *	cfneg64ls	mvdx4, ?mvdx14
-0*630 <int_arith\+0x40> 3e ?3d ?85 ?60 ? *	cfneg64cc	mvdx8, ?mvdx13
-0*634 <int_arith\+0x44> 7e ?31 ?25 ?60 ? *	cfneg64vc	mvdx2, ?mvdx1
-0*638 <int_arith\+0x48> ce ?3b ?65 ?60 ? *	cfneg64gt	mvdx6, ?mvdx11
-0*63c <int_arith\+0x4c> 0e ?35 ?75 ?60 ? *	cfneg64eq	mvdx7, ?mvdx5
-0*640 <int_arith\+0x50> ee ?3c ?35 ?8a ? *	cfadd32	mvfx3, ?mvfx12, ?mvfx10
-0*644 <int_arith\+0x54> 8e ?3d ?f5 ?86 ? *	cfadd32hi	mvfx15, ?mvfx13, ?mvfx6
-0*648 <int_arith\+0x58> 4e ?39 ?25 ?80 ? *	cfadd32mi	mvfx2, ?mvfx9, ?mvfx0
-0*64c <int_arith\+0x5c> ee ?39 ?a5 ?84 ? *	cfadd32	mvfx10, ?mvfx9, ?mvfx4
-0*650 <int_arith\+0x60> 3e ?3d ?85 ?87 ? *	cfadd32cc	mvfx8, ?mvfx13, ?mvfx7
-0*654 <int_arith\+0x64> 1e ?36 ?c5 ?ab ? *	cfadd64ne	mvdx12, ?mvdx6, ?mvdx11
-0*658 <int_arith\+0x68> 7e ?3e ?55 ?a3 ? *	cfadd64vc	mvdx5, ?mvdx14, ?mvdx3
-0*65c <int_arith\+0x6c> ae ?38 ?15 ?af ? *	cfadd64ge	mvdx1, ?mvdx8, ?mvdx15
-0*660 <int_arith\+0x70> 6e ?34 ?b5 ?a2 ? *	cfadd64vs	mvdx11, ?mvdx4, ?mvdx2
-0*664 <int_arith\+0x74> 0e ?3f ?55 ?aa ? *	cfadd64eq	mvdx5, ?mvdx15, ?mvdx10
-0*668 <int_arith\+0x78> 4e ?33 ?e5 ?c8 ? *	cfsub32mi	mvfx14, ?mvfx3, ?mvfx8
-0*66c <int_arith\+0x7c> 7e ?31 ?25 ?cc ? *	cfsub32vc	mvfx2, ?mvfx1, ?mvfx12
-0*670 <int_arith\+0x80> be ?37 ?05 ?c5 ? *	cfsub32lt	mvfx0, ?mvfx7, ?mvfx5
-0*674 <int_arith\+0x84> 3e ?3a ?c5 ?c1 ? *	cfsub32cc	mvfx12, ?mvfx10, ?mvfx1
-0*678 <int_arith\+0x88> ee ?36 ?d5 ?cb ? *	cfsub32	mvfx13, ?mvfx6, ?mvfx11
-0*67c <int_arith\+0x8c> 2e ?30 ?95 ?e5 ? *	cfsub64cs	mvdx9, ?mvdx0, ?mvdx5
-0*680 <int_arith\+0x90> ae ?34 ?95 ?ee ? *	cfsub64ge	mvdx9, ?mvdx4, ?mvdx14
-0*684 <int_arith\+0x94> 8e ?37 ?d5 ?e2 ? *	cfsub64hi	mvdx13, ?mvdx7, ?mvdx2
-0*688 <int_arith\+0x98> ce ?3b ?65 ?e0 ? *	cfsub64gt	mvdx6, ?mvdx11, ?mvdx0
-0*68c <int_arith\+0x9c> 5e ?33 ?e5 ?ec ? *	cfsub64pl	mvdx14, ?mvdx3, ?mvdx12
-0*690 <int_arith\+0xa0> 1e ?1f ?85 ?0d ? *	cfmul32ne	mvfx8, ?mvfx15, ?mvfx13
-0*694 <int_arith\+0xa4> be ?12 ?45 ?09 ? *	cfmul32lt	mvfx4, ?mvfx2, ?mvfx9
-0*698 <int_arith\+0xa8> 5e ?1a ?f5 ?09 ? *	cfmul32pl	mvfx15, ?mvfx10, ?mvfx9
-0*69c <int_arith\+0xac> ee ?18 ?35 ?0d ? *	cfmul32	mvfx3, ?mvfx8, ?mvfx13
-0*6a0 <int_arith\+0xb0> 2e ?1c ?15 ?06 ? *	cfmul32cs	mvfx1, ?mvfx12, ?mvfx6
-0*6a4 <int_arith\+0xb4> 0e ?15 ?75 ?2e ? *	cfmul64eq	mvdx7, ?mvdx5, ?mvdx14
-0*6a8 <int_arith\+0xb8> ce ?11 ?a5 ?28 ? *	cfmul64gt	mvdx10, ?mvdx1, ?mvdx8
-0*6ac <int_arith\+0xbc> de ?1b ?65 ?24 ? *	cfmul64le	mvdx6, ?mvdx11, ?mvdx4
-0*6b0 <int_arith\+0xc0> 9e ?15 ?05 ?2f ? *	cfmul64ls	mvdx0, ?mvdx5, ?mvdx15
-0*6b4 <int_arith\+0xc4> 9e ?1e ?45 ?23 ? *	cfmul64ls	mvdx4, ?mvdx14, ?mvdx3
-0*6b8 <int_arith\+0xc8> de ?12 ?75 ?41 ? *	cfmac32le	mvfx7, ?mvfx2, ?mvfx1
-0*6bc <int_arith\+0xcc> 6e ?10 ?b5 ?47 ? *	cfmac32vs	mvfx11, ?mvfx0, ?mvfx7
-0*6c0 <int_arith\+0xd0> ee ?1c ?35 ?4a ? *	cfmac32	mvfx3, ?mvfx12, ?mvfx10
-0*6c4 <int_arith\+0xd4> 8e ?1d ?f5 ?46 ? *	cfmac32hi	mvfx15, ?mvfx13, ?mvfx6
-0*6c8 <int_arith\+0xd8> 4e ?19 ?25 ?40 ? *	cfmac32mi	mvfx2, ?mvfx9, ?mvfx0
-0*6cc <int_arith\+0xdc> ee ?19 ?a5 ?64 ? *	cfmsc32	mvfx10, ?mvfx9, ?mvfx4
-0*6d0 <int_arith\+0xe0> 3e ?1d ?85 ?67 ? *	cfmsc32cc	mvfx8, ?mvfx13, ?mvfx7
-0*6d4 <int_arith\+0xe4> 1e ?16 ?c5 ?6b ? *	cfmsc32ne	mvfx12, ?mvfx6, ?mvfx11
-0*6d8 <int_arith\+0xe8> 7e ?1e ?55 ?63 ? *	cfmsc32vc	mvfx5, ?mvfx14, ?mvfx3
-0*6dc <int_arith\+0xec> ae ?18 ?15 ?6f ? *	cfmsc32ge	mvfx1, ?mvfx8, ?mvfx15
+0*5f0 <int_arith> ae ?38 ?15 ?00 ? *	cfabs32ge	mvfx1, ?mvfx8
+0*5f4 <int_arith\+0x4> ee ?36 ?d5 ?00 ? *	cfabs32	mvfx13, ?mvfx6
+0*5f8 <int_arith\+0x8> be ?32 ?45 ?00 ? *	cfabs32lt	mvfx4, ?mvfx2
+0*5fc <int_arith\+0xc> 9e ?35 ?05 ?00 ? *	cfabs32ls	mvfx0, ?mvfx5
+0*600 <int_arith\+0x10> ee ?39 ?a5 ?00 ? *	cfabs32	mvfx10, ?mvfx9
+0*604 <int_arith\+0x14> 4e ?33 ?e5 ?20 ? *	cfabs64mi	mvdx14, ?mvdx3
+0*608 <int_arith\+0x18> 8e ?37 ?d5 ?20 ? *	cfabs64hi	mvdx13, ?mvdx7
+0*60c <int_arith\+0x1c> 2e ?3c ?15 ?20 ? *	cfabs64cs	mvdx1, ?mvdx12
+0*610 <int_arith\+0x20> 6e ?30 ?b5 ?20 ? *	cfabs64vs	mvdx11, ?mvdx0
+0*614 <int_arith\+0x24> 7e ?3e ?55 ?20 ? *	cfabs64vc	mvdx5, ?mvdx14
+0*618 <int_arith\+0x28> 3e ?3a ?c5 ?40 ? *	cfneg32cc	mvfx12, ?mvfx10
+0*61c <int_arith\+0x2c> 1e ?3f ?85 ?40 ? *	cfneg32ne	mvfx8, ?mvfx15
+0*620 <int_arith\+0x30> de ?3b ?65 ?40 ? *	cfneg32le	mvfx6, ?mvfx11
+0*624 <int_arith\+0x34> 4e ?39 ?25 ?40 ? *	cfneg32mi	mvfx2, ?mvfx9
+0*628 <int_arith\+0x38> 0e ?3f ?55 ?40 ? *	cfneg32eq	mvfx5, ?mvfx15
+0*62c <int_arith\+0x3c> ae ?34 ?95 ?60 ? *	cfneg64ge	mvdx9, ?mvdx4
+0*630 <int_arith\+0x40> ee ?38 ?35 ?60 ? *	cfneg64	mvdx3, ?mvdx8
+0*634 <int_arith\+0x44> de ?32 ?75 ?60 ? *	cfneg64le	mvdx7, ?mvdx2
+0*638 <int_arith\+0x48> 1e ?36 ?c5 ?60 ? *	cfneg64ne	mvdx12, ?mvdx6
+0*63c <int_arith\+0x4c> be ?37 ?05 ?60 ? *	cfneg64lt	mvdx0, ?mvdx7
+0*640 <int_arith\+0x50> 5e ?33 ?e5 ?8c ? *	cfadd32pl	mvfx14, ?mvfx3, ?mvfx12
+0*644 <int_arith\+0x54> 1e ?3f ?85 ?8d ? *	cfadd32ne	mvfx8, ?mvfx15, ?mvfx13
+0*648 <int_arith\+0x58> be ?32 ?45 ?89 ? *	cfadd32lt	mvfx4, ?mvfx2, ?mvfx9
+0*64c <int_arith\+0x5c> 5e ?3a ?f5 ?89 ? *	cfadd32pl	mvfx15, ?mvfx10, ?mvfx9
+0*650 <int_arith\+0x60> ee ?38 ?35 ?8d ? *	cfadd32	mvfx3, ?mvfx8, ?mvfx13
+0*654 <int_arith\+0x64> 2e ?3c ?15 ?a6 ? *	cfadd64cs	mvdx1, ?mvdx12, ?mvdx6
+0*658 <int_arith\+0x68> 0e ?35 ?75 ?ae ? *	cfadd64eq	mvdx7, ?mvdx5, ?mvdx14
+0*65c <int_arith\+0x6c> ce ?31 ?a5 ?a8 ? *	cfadd64gt	mvdx10, ?mvdx1, ?mvdx8
+0*660 <int_arith\+0x70> de ?3b ?65 ?a4 ? *	cfadd64le	mvdx6, ?mvdx11, ?mvdx4
+0*664 <int_arith\+0x74> 9e ?35 ?05 ?af ? *	cfadd64ls	mvdx0, ?mvdx5, ?mvdx15
+0*668 <int_arith\+0x78> 9e ?3e ?45 ?c3 ? *	cfsub32ls	mvfx4, ?mvfx14, ?mvfx3
+0*66c <int_arith\+0x7c> de ?32 ?75 ?c1 ? *	cfsub32le	mvfx7, ?mvfx2, ?mvfx1
+0*670 <int_arith\+0x80> 6e ?30 ?b5 ?c7 ? *	cfsub32vs	mvfx11, ?mvfx0, ?mvfx7
+0*674 <int_arith\+0x84> ee ?3c ?35 ?ca ? *	cfsub32	mvfx3, ?mvfx12, ?mvfx10
+0*678 <int_arith\+0x88> 8e ?3d ?f5 ?c6 ? *	cfsub32hi	mvfx15, ?mvfx13, ?mvfx6
+0*67c <int_arith\+0x8c> 4e ?39 ?25 ?e0 ? *	cfsub64mi	mvdx2, ?mvdx9, ?mvdx0
+0*680 <int_arith\+0x90> ee ?39 ?a5 ?e4 ? *	cfsub64	mvdx10, ?mvdx9, ?mvdx4
+0*684 <int_arith\+0x94> 3e ?3d ?85 ?e7 ? *	cfsub64cc	mvdx8, ?mvdx13, ?mvdx7
+0*688 <int_arith\+0x98> 1e ?36 ?c5 ?eb ? *	cfsub64ne	mvdx12, ?mvdx6, ?mvdx11
+0*68c <int_arith\+0x9c> 7e ?3e ?55 ?e3 ? *	cfsub64vc	mvdx5, ?mvdx14, ?mvdx3
+0*690 <int_arith\+0xa0> ae ?18 ?15 ?0f ? *	cfmul32ge	mvfx1, ?mvfx8, ?mvfx15
+0*694 <int_arith\+0xa4> 6e ?14 ?b5 ?02 ? *	cfmul32vs	mvfx11, ?mvfx4, ?mvfx2
+0*698 <int_arith\+0xa8> 0e ?1f ?55 ?0a ? *	cfmul32eq	mvfx5, ?mvfx15, ?mvfx10
+0*69c <int_arith\+0xac> 4e ?13 ?e5 ?08 ? *	cfmul32mi	mvfx14, ?mvfx3, ?mvfx8
+0*6a0 <int_arith\+0xb0> 7e ?11 ?25 ?0c ? *	cfmul32vc	mvfx2, ?mvfx1, ?mvfx12
+0*6a4 <int_arith\+0xb4> be ?17 ?05 ?25 ? *	cfmul64lt	mvdx0, ?mvdx7, ?mvdx5
+0*6a8 <int_arith\+0xb8> 3e ?1a ?c5 ?21 ? *	cfmul64cc	mvdx12, ?mvdx10, ?mvdx1
+0*6ac <int_arith\+0xbc> ee ?16 ?d5 ?2b ? *	cfmul64	mvdx13, ?mvdx6, ?mvdx11
+0*6b0 <int_arith\+0xc0> 2e ?10 ?95 ?25 ? *	cfmul64cs	mvdx9, ?mvdx0, ?mvdx5
+0*6b4 <int_arith\+0xc4> ae ?14 ?95 ?2e ? *	cfmul64ge	mvdx9, ?mvdx4, ?mvdx14
+0*6b8 <int_arith\+0xc8> 8e ?17 ?d5 ?42 ? *	cfmac32hi	mvfx13, ?mvfx7, ?mvfx2
+0*6bc <int_arith\+0xcc> ce ?1b ?65 ?40 ? *	cfmac32gt	mvfx6, ?mvfx11, ?mvfx0
+0*6c0 <int_arith\+0xd0> 5e ?13 ?e5 ?4c ? *	cfmac32pl	mvfx14, ?mvfx3, ?mvfx12
+0*6c4 <int_arith\+0xd4> 1e ?1f ?85 ?4d ? *	cfmac32ne	mvfx8, ?mvfx15, ?mvfx13
+0*6c8 <int_arith\+0xd8> be ?12 ?45 ?49 ? *	cfmac32lt	mvfx4, ?mvfx2, ?mvfx9
+0*6cc <int_arith\+0xdc> 5e ?1a ?f5 ?69 ? *	cfmsc32pl	mvfx15, ?mvfx10, ?mvfx9
+0*6d0 <int_arith\+0xe0> ee ?18 ?35 ?6d ? *	cfmsc32	mvfx3, ?mvfx8, ?mvfx13
+0*6d4 <int_arith\+0xe4> 2e ?1c ?15 ?66 ? *	cfmsc32cs	mvfx1, ?mvfx12, ?mvfx6
+0*6d8 <int_arith\+0xe8> 0e ?15 ?75 ?6e ? *	cfmsc32eq	mvfx7, ?mvfx5, ?mvfx14
+0*6dc <int_arith\+0xec> ce ?11 ?a5 ?68 ? *	cfmsc32gt	mvfx10, ?mvfx1, ?mvfx8
 # acc_arith:
-0*6e0 <acc_arith> 6e ?02 ?46 ?69 ? *	cfmadd32vs	mvax3, ?mvfx4, ?mvfx2, ?mvfx9
-0*6e4 <acc_arith\+0x4> 0e ?0a ?f6 ?29 ? *	cfmadd32eq	mvax1, ?mvfx15, ?mvfx10, ?mvfx9
-0*6e8 <acc_arith\+0x8> 4e ?08 ?36 ?2d ? *	cfmadd32mi	mvax1, ?mvfx3, ?mvfx8, ?mvfx13
-0*6ec <acc_arith\+0xc> 7e ?0c ?16 ?06 ? *	cfmadd32vc	mvax0, ?mvfx1, ?mvfx12, ?mvfx6
-0*6f0 <acc_arith\+0x10> be ?05 ?76 ?0e ? *	cfmadd32lt	mvax0, ?mvfx7, ?mvfx5, ?mvfx14
-0*6f4 <acc_arith\+0x14> 3e ?11 ?a6 ?08 ? *	cfmsub32cc	mvax0, ?mvfx10, ?mvfx1, ?mvfx8
-0*6f8 <acc_arith\+0x18> ee ?1b ?66 ?44 ? *	cfmsub32	mvax2, ?mvfx6, ?mvfx11, ?mvfx4
-0*6fc <acc_arith\+0x1c> 2e ?15 ?06 ?2f ? *	cfmsub32cs	mvax1, ?mvfx0, ?mvfx5, ?mvfx15
-0*700 <acc_arith\+0x20> ae ?1e ?46 ?43 ? *	cfmsub32ge	mvax2, ?mvfx4, ?mvfx14, ?mvfx3
-0*704 <acc_arith\+0x24> 8e ?12 ?76 ?61 ? *	cfmsub32hi	mvax3, ?mvfx7, ?mvfx2, ?mvfx1
-0*708 <acc_arith\+0x28> ce ?20 ?16 ?07 ? *	cfmadda32gt	mvax0, ?mvax1, ?mvfx0, ?mvfx7
-0*70c <acc_arith\+0x2c> 5e ?2c ?26 ?4a ? *	cfmadda32pl	mvax2, ?mvax2, ?mvfx12, ?mvfx10
-0*710 <acc_arith\+0x30> 1e ?2d ?36 ?26 ? *	cfmadda32ne	mvax1, ?mvax3, ?mvfx13, ?mvfx6
-0*714 <acc_arith\+0x34> be ?29 ?06 ?40 ? *	cfmadda32lt	mvax2, ?mvax0, ?mvfx9, ?mvfx0
-0*718 <acc_arith\+0x38> 5e ?29 ?26 ?64 ? *	cfmadda32pl	mvax3, ?mvax2, ?mvfx9, ?mvfx4
-0*71c <acc_arith\+0x3c> ee ?3d ?16 ?67 ? *	cfmsuba32	mvax3, ?mvax1, ?mvfx13, ?mvfx7
-0*720 <acc_arith\+0x40> 2e ?36 ?26 ?6b ? *	cfmsuba32cs	mvax3, ?mvax2, ?mvfx6, ?mvfx11
-0*724 <acc_arith\+0x44> 0e ?3e ?36 ?23 ? *	cfmsuba32eq	mvax1, ?mvax3, ?mvfx14, ?mvfx3
-0*728 <acc_arith\+0x48> ce ?38 ?36 ?2f ? *	cfmsuba32gt	mvax1, ?mvax3, ?mvfx8, ?mvfx15
-0*72c <acc_arith\+0x4c> de ?34 ?36 ?02 ? *	cfmsuba32le	mvax0, ?mvax3, ?mvfx4, ?mvfx2
+0*6e0 <acc_arith> de ?04 ?b6 ?02 ? *	cfmadd32le	mvax0, ?mvfx11, ?mvfx4, ?mvfx2
+0*6e4 <acc_arith\+0x4> 9e ?0f ?56 ?0a ? *	cfmadd32ls	mvax0, ?mvfx5, ?mvfx15, ?mvfx10
+0*6e8 <acc_arith\+0x8> 9e ?03 ?e6 ?08 ? *	cfmadd32ls	mvax0, ?mvfx14, ?mvfx3, ?mvfx8
+0*6ec <acc_arith\+0xc> de ?01 ?26 ?4c ? *	cfmadd32le	mvax2, ?mvfx2, ?mvfx1, ?mvfx12
+0*6f0 <acc_arith\+0x10> 6e ?07 ?06 ?25 ? *	cfmadd32vs	mvax1, ?mvfx0, ?mvfx7, ?mvfx5
+0*6f4 <acc_arith\+0x14> ee ?1a ?c6 ?41 ? *	cfmsub32	mvax2, ?mvfx12, ?mvfx10, ?mvfx1
+0*6f8 <acc_arith\+0x18> 8e ?16 ?d6 ?6b ? *	cfmsub32hi	mvax3, ?mvfx13, ?mvfx6, ?mvfx11
+0*6fc <acc_arith\+0x1c> 4e ?10 ?96 ?05 ? *	cfmsub32mi	mvax0, ?mvfx9, ?mvfx0, ?mvfx5
+0*700 <acc_arith\+0x20> ee ?14 ?96 ?4e ? *	cfmsub32	mvax2, ?mvfx9, ?mvfx4, ?mvfx14
+0*704 <acc_arith\+0x24> 3e ?17 ?d6 ?22 ? *	cfmsub32cc	mvax1, ?mvfx13, ?mvfx7, ?mvfx2
+0*708 <acc_arith\+0x28> 1e ?2b ?06 ?40 ? *	cfmadda32ne	mvax2, ?mvax0, ?mvfx11, ?mvfx0
+0*70c <acc_arith\+0x2c> 7e ?23 ?26 ?6c ? *	cfmadda32vc	mvax3, ?mvax2, ?mvfx3, ?mvfx12
+0*710 <acc_arith\+0x30> ae ?2f ?16 ?6d ? *	cfmadda32ge	mvax3, ?mvax1, ?mvfx15, ?mvfx13
+0*714 <acc_arith\+0x34> 6e ?22 ?26 ?69 ? *	cfmadda32vs	mvax3, ?mvax2, ?mvfx2, ?mvfx9
+0*718 <acc_arith\+0x38> 0e ?2a ?36 ?29 ? *	cfmadda32eq	mvax1, ?mvax3, ?mvfx10, ?mvfx9
+0*71c <acc_arith\+0x3c> 4e ?38 ?36 ?2d ? *	cfmsuba32mi	mvax1, ?mvax3, ?mvfx8, ?mvfx13
+0*720 <acc_arith\+0x40> 7e ?3c ?36 ?06 ? *	cfmsuba32vc	mvax0, ?mvax3, ?mvfx12, ?mvfx6
+0*724 <acc_arith\+0x44> be ?35 ?16 ?0e ? *	cfmsuba32lt	mvax0, ?mvax1, ?mvfx5, ?mvfx14
+0*728 <acc_arith\+0x48> 3e ?31 ?16 ?08 ? *	cfmsuba32cc	mvax0, ?mvax1, ?mvfx1, ?mvfx8
+0*72c <acc_arith\+0x4c> ee ?3b ?06 ?44 ? *	cfmsuba32	mvax2, ?mvax0, ?mvfx11, ?mvfx4
diff --git a/gas/testsuite/gas/arm/maverick.s b/gas/testsuite/gas/arm/maverick.s
index c044348d8dd3..e32d36b6a9bf 100644
--- a/gas/testsuite/gas/arm/maverick.s
+++ b/gas/testsuite/gas/arm/maverick.s
@@ -1,470 +1,470 @@
 	.text
 	.align
 load_store:
-	cfldrseq	mvf5, [sp, #252]
-	cfldrsmi	mvf14, [r11, #72]
-	cfldrsvc	mvf2, [r12, #-240]
-	cfldrslt	mvf0, [sl, #252]
-	cfldrsgt	mvf10, [fp, #72]
-	cfldrsle	mvf6, [ip, #-240]!
-	cfldrsls	mvf0, [r10, #252]!
-	cfldrsmi	mvf14, [r11, #72]!
-	cfldrsvc	mvf2, [r12, #-240]!
-	cfldrslt	mvf0, [sl, #252]!
-	cfldrsgt	mvf10, [fp], #72
-	cfldrsle	mvf6, [ip], #-240
-	cfldrsls	mvf0, [r10], #252
-	cfldrsmi	mvf14, [r11], #72
-	cfldrsvc	mvf2, [r12], #-240
-	cfldrdlt	mvd0, [sl, #252]
-	cfldrdgt	mvd10, [fp, #72]
-	cfldrdle	mvd6, [ip, #-240]
-	cfldrdls	mvd0, [r10, #252]
-	cfldrdmi	mvd14, [r11, #72]
-	cfldrdvc	mvd2, [r12, #-240]!
-	cfldrdlt	mvd0, [sl, #252]!
-	cfldrdgt	mvd10, [fp, #72]!
-	cfldrdle	mvd6, [ip, #-240]!
-	cfldrdls	mvd0, [r10, #252]!
-	cfldrdmi	mvd14, [r11], #72
-	cfldrdvc	mvd2, [r12], #-240
-	cfldrdlt	mvd0, [sl], #252
-	cfldrdgt	mvd10, [fp], #72
-	cfldrdle	mvd6, [ip], #-240
-	cfldr32ls	mvfx0, [r10, #252]
-	cfldr32mi	mvfx14, [r11, #72]
-	cfldr32vc	mvfx2, [r12, #-240]
-	cfldr32lt	mvfx0, [sl, #252]
-	cfldr32gt	mvfx10, [fp, #72]
-	cfldr32le	mvfx6, [ip, #-240]!
-	cfldr32ls	mvfx0, [r10, #252]!
-	cfldr32mi	mvfx14, [r11, #72]!
-	cfldr32vc	mvfx2, [r12, #-240]!
-	cfldr32lt	mvfx0, [sl, #252]!
-	cfldr32gt	mvfx10, [fp], #72
-	cfldr32le	mvfx6, [ip], #-240
-	cfldr32ls	mvfx0, [r10], #252
-	cfldr32mi	mvfx14, [r11], #72
-	cfldr32vc	mvfx2, [r12], #-240
-	cfldr64lt	mvdx0, [sl, #252]
-	cfldr64gt	mvdx10, [fp, #72]
-	cfldr64le	mvdx6, [ip, #-240]
-	cfldr64ls	mvdx0, [r10, #252]
-	cfldr64mi	mvdx14, [r11, #72]
-	cfldr64vc	mvdx2, [r12, #-240]!
-	cfldr64lt	mvdx0, [sl, #252]!
-	cfldr64gt	mvdx10, [fp, #72]!
-	cfldr64le	mvdx6, [ip, #-240]!
-	cfldr64ls	mvdx0, [r10, #252]!
-	cfldr64mi	mvdx14, [r11], #72
-	cfldr64vc	mvdx2, [r12], #-240
-	cfldr64lt	mvdx0, [sl], #252
-	cfldr64gt	mvdx10, [fp], #72
-	cfldr64le	mvdx6, [ip], #-240
-	cfstrsls	mvf0, [r10, #252]
-	cfstrsmi	mvf14, [r11, #72]
-	cfstrsvc	mvf2, [r12, #-240]
-	cfstrslt	mvf0, [sl, #252]
-	cfstrsgt	mvf10, [fp, #72]
-	cfstrsle	mvf6, [ip, #-240]!
-	cfstrsls	mvf0, [r10, #252]!
-	cfstrsmi	mvf14, [r11, #72]!
-	cfstrsvc	mvf2, [r12, #-240]!
-	cfstrslt	mvf0, [sl, #252]!
-	cfstrsgt	mvf10, [fp], #72
-	cfstrsle	mvf6, [ip], #-240
-	cfstrsls	mvf0, [r10], #252
-	cfstrsmi	mvf14, [r11], #72
-	cfstrsvc	mvf2, [r12], #-240
-	cfstrdlt	mvd0, [sl, #252]
-	cfstrdgt	mvd10, [fp, #72]
-	cfstrdle	mvd6, [ip, #-240]
-	cfstrdls	mvd0, [r10, #252]
-	cfstrdmi	mvd14, [r11, #72]
-	cfstrdvc	mvd2, [r12, #-240]!
-	cfstrdlt	mvd0, [sl, #252]!
-	cfstrdgt	mvd10, [fp, #72]!
-	cfstrdle	mvd6, [ip, #-240]!
-	cfstrdls	mvd0, [r10, #252]!
-	cfstrdmi	mvd14, [r11], #72
-	cfstrdvc	mvd2, [r12], #-240
-	cfstrdlt	mvd0, [sl], #252
-	cfstrdgt	mvd10, [fp], #72
-	cfstrdle	mvd6, [ip], #-240
-	cfstr32ls	mvfx0, [r10, #252]
-	cfstr32mi	mvfx14, [r11, #72]
-	cfstr32vc	mvfx2, [r12, #-240]
-	cfstr32lt	mvfx0, [sl, #252]
-	cfstr32gt	mvfx10, [fp, #72]
-	cfstr32le	mvfx6, [ip, #-240]!
-	cfstr32ls	mvfx0, [r10, #252]!
-	cfstr32mi	mvfx14, [r11, #72]!
-	cfstr32vc	mvfx2, [r12, #-240]!
-	cfstr32lt	mvfx0, [sl, #252]!
-	cfstr32gt	mvfx10, [fp], #72
-	cfstr32le	mvfx6, [ip], #-240
-	cfstr32ls	mvfx0, [r10], #252
-	cfstr32mi	mvfx14, [r11], #72
-	cfstr32vc	mvfx2, [r12], #-240
-	cfstr64lt	mvdx0, [sl, #252]
-	cfstr64gt	mvdx10, [fp, #72]
-	cfstr64le	mvdx6, [ip, #-240]
-	cfstr64ls	mvdx0, [r10, #252]
-	cfstr64mi	mvdx14, [r11, #72]
-	cfstr64vc	mvdx2, [r12, #-240]!
-	cfstr64lt	mvdx0, [sl, #252]!
-	cfstr64gt	mvdx10, [fp, #72]!
-	cfstr64le	mvdx6, [ip, #-240]!
-	cfstr64ls	mvdx0, [r10, #252]!
-	cfstr64mi	mvdx14, [r11], #72
-	cfstr64vc	mvdx2, [r12], #-240
-	cfstr64lt	mvdx0, [sl], #252
-	cfstr64gt	mvdx10, [fp], #72
-	cfstr64le	mvdx6, [ip], #-240
+	cfldrseq	mvf5, [sp, #1020]
+	cfldrsmi	mvf14, [r11, #292]
+	cfldrsvc	mvf2, [r12, #-956]
+	cfldrslt	mvf0, [sl, #-1020]
+	cfldrscc	mvf12, [r1, #-156]
+	cfldrs	mvf13, [r9, #416]!
+	cfldrscs	mvf9, [r0, #-1020]!
+	cfldrsls	mvf4, [r1, #-156]!
+	cfldrsle	mvf7, [r9, #416]!
+	cfldrsvs	mvf11, [r0, #-1020]!
+	cfldrscc	mvf12, [r1], #-156
+	cfldrs	mvf13, [r9], #416
+	cfldrscs	mvf9, [r0], #-1020
+	cfldrsls	mvf4, [r1], #-156
+	cfldrsle	mvf7, [r9], #416
+	cfldrdvs	mvd11, [r0, #-1020]
+	cfldrdcc	mvd12, [r1, #-156]
+	cfldrd	mvd13, [r9, #416]
+	cfldrdcs	mvd9, [r0, #-1020]
+	cfldrdls	mvd4, [r1, #-156]
+	cfldrdle	mvd7, [r9, #416]!
+	cfldrdvs	mvd11, [r0, #-1020]!
+	cfldrdcc	mvd12, [r1, #-156]!
+	cfldrd	mvd13, [r9, #416]!
+	cfldrdcs	mvd9, [r0, #-1020]!
+	cfldrdls	mvd4, [r1], #-156
+	cfldrdle	mvd7, [r9], #416
+	cfldrdvs	mvd11, [r0], #-1020
+	cfldrdcc	mvd12, [r1], #-156
+	cfldrd	mvd13, [r9], #416
+	cfldr32cs	mvfx9, [r0, #-1020]
+	cfldr32ls	mvfx4, [r1, #-156]
+	cfldr32le	mvfx7, [r9, #416]
+	cfldr32vs	mvfx11, [r0, #-1020]
+	cfldr32cc	mvfx12, [r1, #-156]
+	cfldr32	mvfx13, [r9, #416]!
+	cfldr32cs	mvfx9, [r0, #-1020]!
+	cfldr32ls	mvfx4, [r1, #-156]!
+	cfldr32le	mvfx7, [r9, #416]!
+	cfldr32vs	mvfx11, [r0, #-1020]!
+	cfldr32cc	mvfx12, [r1], #-156
+	cfldr32	mvfx13, [r9], #416
+	cfldr32cs	mvfx9, [r0], #-1020
+	cfldr32ls	mvfx4, [r1], #-156
+	cfldr32le	mvfx7, [r9], #416
+	cfldr64vs	mvdx11, [r0, #-1020]
+	cfldr64cc	mvdx12, [r1, #-156]
+	cfldr64	mvdx13, [r9, #416]
+	cfldr64cs	mvdx9, [r0, #-1020]
+	cfldr64ls	mvdx4, [r1, #-156]
+	cfldr64le	mvdx7, [r9, #416]!
+	cfldr64vs	mvdx11, [r0, #-1020]!
+	cfldr64cc	mvdx12, [r1, #-156]!
+	cfldr64	mvdx13, [r9, #416]!
+	cfldr64cs	mvdx9, [r0, #-1020]!
+	cfldr64ls	mvdx4, [r1], #-156
+	cfldr64le	mvdx7, [r9], #416
+	cfldr64vs	mvdx11, [r0], #-1020
+	cfldr64cc	mvdx12, [r1], #-156
+	cfldr64	mvdx13, [r9], #416
+	cfstrscs	mvf9, [r0, #-1020]
+	cfstrsls	mvf4, [r1, #-156]
+	cfstrsle	mvf7, [r9, #416]
+	cfstrsvs	mvf11, [r0, #-1020]
+	cfstrscc	mvf12, [r1, #-156]
+	cfstrs	mvf13, [r9, #416]!
+	cfstrscs	mvf9, [r0, #-1020]!
+	cfstrsls	mvf4, [r1, #-156]!
+	cfstrsle	mvf7, [r9, #416]!
+	cfstrsvs	mvf11, [r0, #-1020]!
+	cfstrscc	mvf12, [r1], #-156
+	cfstrs	mvf13, [r9], #416
+	cfstrscs	mvf9, [r0], #-1020
+	cfstrsls	mvf4, [r1], #-156
+	cfstrsle	mvf7, [r9], #416
+	cfstrdvs	mvd11, [r0, #-1020]
+	cfstrdcc	mvd12, [r1, #-156]
+	cfstrd	mvd13, [r9, #416]
+	cfstrdcs	mvd9, [r0, #-1020]
+	cfstrdls	mvd4, [r1, #-156]
+	cfstrdle	mvd7, [r9, #416]!
+	cfstrdvs	mvd11, [r0, #-1020]!
+	cfstrdcc	mvd12, [r1, #-156]!
+	cfstrd	mvd13, [r9, #416]!
+	cfstrdcs	mvd9, [r0, #-1020]!
+	cfstrdls	mvd4, [r1], #-156
+	cfstrdle	mvd7, [r9], #416
+	cfstrdvs	mvd11, [r0], #-1020
+	cfstrdcc	mvd12, [r1], #-156
+	cfstrd	mvd13, [r9], #416
+	cfstr32cs	mvfx9, [r0, #-1020]
+	cfstr32ls	mvfx4, [r1, #-156]
+	cfstr32le	mvfx7, [r9, #416]
+	cfstr32vs	mvfx11, [r0, #-1020]
+	cfstr32cc	mvfx12, [r1, #-156]
+	cfstr32	mvfx13, [r9, #416]!
+	cfstr32cs	mvfx9, [r0, #-1020]!
+	cfstr32ls	mvfx4, [r1, #-156]!
+	cfstr32le	mvfx7, [r9, #416]!
+	cfstr32vs	mvfx11, [r0, #-1020]!
+	cfstr32cc	mvfx12, [r1], #-156
+	cfstr32	mvfx13, [r9], #416
+	cfstr32cs	mvfx9, [r0], #-1020
+	cfstr32ls	mvfx4, [r1], #-156
+	cfstr32le	mvfx7, [r9], #416
+	cfstr64vs	mvdx11, [r0, #-1020]
+	cfstr64cc	mvdx12, [r1, #-156]
+	cfstr64	mvdx13, [r9, #416]
+	cfstr64cs	mvdx9, [r0, #-1020]
+	cfstr64ls	mvdx4, [r1, #-156]
+	cfstr64le	mvdx7, [r9, #416]!
+	cfstr64vs	mvdx11, [r0, #-1020]!
+	cfstr64cc	mvdx12, [r1, #-156]!
+	cfstr64	mvdx13, [r9, #416]!
+	cfstr64cs	mvdx9, [r0, #-1020]!
+	cfstr64ls	mvdx4, [r1], #-156
+	cfstr64le	mvdx7, [r9], #416
+	cfstr64vs	mvdx11, [r0], #-1020
+	cfstr64cc	mvdx12, [r1], #-156
+	cfstr64	mvdx13, [r9], #416
 move:
-	cfmvsrls	mvf0, r10
-	cfmvsr	mvf10, r4
-	cfmvsrmi	mvf14, r11
-	cfmvsrhi	mvf13, r5
-	cfmvsrcs	mvf1, r6
-	cfmvrsvs	r3, mvf0
-	cfmvrsvc	r13, mvf14
-	cfmvrscc	r14, mvf10
-	cfmvrsne	r8, mvf15
-	cfmvrsle	r15, mvf11
-	cfmvdlrmi	mvd2, r3
-	cfmvdlreq	mvd5, sp
-	cfmvdlrge	mvd9, lr
-	cfmvdlral	mvd3, r8
-	cfmvdlrle	mvd7, pc
-	cfmvrdlne	r6, mvd6
-	cfmvrdllt	r0, mvd7
-	cfmvrdlpl	r7, mvd3
-	cfmvrdlgt	r1, mvd1
-	cfmvrdlhi	r2, mvd13
-	cfmvdhrvs	mvd11, r6
-	cfmvdhrcs	mvd9, r0
-	cfmvdhrpl	mvd15, r7
-	cfmvdhrls	mvd4, r1
-	cfmvdhrcc	mvd8, r2
-	cfmvrdhvc	pc, mvd1
-	cfmvrdhgt	r9, mvd11
-	cfmvrdheq	sl, mvd5
-	cfmvrdhal	r4, mvd12
-	cfmvrdhge	fp, mvd8
-	cfmv64lr	mvdx13, r15
-	cfmv64lrlt	mvdx4, r9
-	cfmv64lrls	mvdx0, r10
-	cfmv64lr	mvdx10, r4
-	cfmv64lrmi	mvdx14, r11
-	cfmvr64lhi	r2, mvdx7
-	cfmvr64lcs	r12, mvdx12
-	cfmvr64lvs	r3, mvdx0
-	cfmvr64lvc	r13, mvdx14
-	cfmvr64lcc	r14, mvdx10
-	cfmv64hrne	mvdx8, r2
-	cfmv64hrle	mvdx6, ip
-	cfmv64hrmi	mvdx2, r3
-	cfmv64hreq	mvdx5, sp
-	cfmv64hrge	mvdx9, lr
-	cfmvr64hal	r11, mvdx8
-	cfmvr64hle	r5, mvdx2
-	cfmvr64hne	r6, mvdx6
-	cfmvr64hlt	r0, mvdx7
-	cfmvr64hpl	r7, mvdx3
-	cfmval32gt	mvax1, mvfx1
-	cfmval32hi	mvax3, mvfx13
-	cfmval32vs	mvax3, mvfx4
-	cfmval32cs	mvax1, mvfx0
-	cfmval32pl	mvax3, mvfx10
-	cfmv32alls	mvfx4, mvax1
-	cfmv32alcc	mvfx8, mvax3
-	cfmv32alvc	mvfx2, mvax3
-	cfmv32algt	mvfx6, mvax1
-	cfmv32aleq	mvfx7, mvax3
-	cfmvam32al	mvax2, mvfx12
-	cfmvam32ge	mvax3, mvfx8
-	cfmvam32	mvax2, mvfx6
-	cfmvam32lt	mvax2, mvfx2
-	cfmvam32ls	mvax0, mvfx5
-	cfmv32am	mvfx10, mvax2
-	cfmv32ammi	mvfx14, mvax3
-	cfmv32amhi	mvfx13, mvax2
-	cfmv32amcs	mvfx1, mvax2
-	cfmv32amvs	mvfx11, mvax0
-	cfmvah32vc	mvax3, mvfx14
-	cfmvah32cc	mvax0, mvfx10
-	cfmvah32ne	mvax1, mvfx15
-	cfmvah32le	mvax0, mvfx11
-	cfmvah32mi	mvax0, mvfx9
-	cfmv32aheq	mvfx5, mvax3
-	cfmv32ahge	mvfx9, mvax0
-	cfmv32ahal	mvfx3, mvax1
-	cfmv32ahle	mvfx7, mvax0
-	cfmv32ahne	mvfx12, mvax0
-	cfmva32lt	mvax0, mvfx7
-	cfmva32pl	mvax2, mvfx3
-	cfmva32gt	mvax1, mvfx1
-	cfmva32hi	mvax3, mvfx13
-	cfmva32vs	mvax3, mvfx4
-	cfmv32acs	mvfx9, mvax0
-	cfmv32apl	mvfx15, mvax2
-	cfmv32als	mvfx4, mvax1
-	cfmv32acc	mvfx8, mvax3
-	cfmv32avc	mvfx2, mvax3
-	cfmva64gt	mvax0, mvdx11
-	cfmva64eq	mvax1, mvdx5
-	cfmva64al	mvax2, mvdx12
-	cfmva64ge	mvax3, mvdx8
-	cfmva64	mvax2, mvdx6
-	cfmv64alt	mvdx4, mvax0
-	cfmv64als	mvdx0, mvax1
-	cfmv64a	mvdx10, mvax2
-	cfmv64ami	mvdx14, mvax3
-	cfmv64ahi	mvdx13, mvax2
-	cfmvsc32cs	dspsc, mvdx12
-	cfmvsc32vs	dspsc, mvdx0
-	cfmvsc32vc	dspsc, mvdx14
-	cfmvsc32cc	dspsc, mvdx10
-	cfmvsc32ne	dspsc, mvdx15
-	cfmv32scle	mvdx6, dspsc
-	cfmv32scmi	mvdx2, dspsc
-	cfmv32sceq	mvdx5, dspsc
-	cfmv32scge	mvdx9, dspsc
-	cfmv32scal	mvdx3, dspsc
-	cfcpysle	mvf7, mvf2
-	cfcpysne	mvf12, mvf6
-	cfcpyslt	mvf0, mvf7
-	cfcpyspl	mvf14, mvf3
-	cfcpysgt	mvf10, mvf1
-	cfcpydhi	mvd15, mvd13
-	cfcpydvs	mvd11, mvd4
-	cfcpydcs	mvd9, mvd0
-	cfcpydpl	mvd15, mvd10
-	cfcpydls	mvd4, mvd14
+	cfmvsrcs	mvf9, r0
+	cfmvsrpl	mvf15, r7
+	cfmvsrls	mvf4, r1
+	cfmvsrcc	mvf8, r2
+	cfmvsrvc	mvf2, r12
+	cfmvrsgt	r9, mvf11
+	cfmvrseq	sl, mvf5
+	cfmvrsal	r4, mvf12
+	cfmvrsge	fp, mvf8
+	cfmvrs	r5, mvf6
+	cfmvdlrlt	mvd4, r9
+	cfmvdlrls	mvd0, r10
+	cfmvdlr	mvd10, r4
+	cfmvdlrmi	mvd14, r11
+	cfmvdlrhi	mvd13, r5
+	cfmvrdlcs	r12, mvd12
+	cfmvrdlvs	r3, mvd0
+	cfmvrdlvc	r13, mvd14
+	cfmvrdlcc	r14, mvd10
+	cfmvrdlne	r8, mvd15
+	cfmvdhrle	mvd6, ip
+	cfmvdhrmi	mvd2, r3
+	cfmvdhreq	mvd5, sp
+	cfmvdhrge	mvd9, lr
+	cfmvdhral	mvd3, r8
+	cfmvrdhle	r5, mvd2
+	cfmvrdhne	r6, mvd6
+	cfmvrdhlt	r0, mvd7
+	cfmvrdhpl	r7, mvd3
+	cfmvrdhgt	r1, mvd1
+	cfmv64lrhi	mvdx15, r5
+	cfmv64lrvs	mvdx11, r6
+	cfmv64lrcs	mvdx9, r0
+	cfmv64lrpl	mvdx15, r7
+	cfmv64lrls	mvdx4, r1
+	cfmvr64lcc	r8, mvdx13
+	cfmvr64lvc	pc, mvdx1
+	cfmvr64lgt	r9, mvdx11
+	cfmvr64leq	sl, mvdx5
+	cfmvr64lal	r4, mvdx12
+	cfmv64hrge	mvdx1, r8
+	cfmv64hr	mvdx13, r15
+	cfmv64hrlt	mvdx4, r9
+	cfmv64hrls	mvdx0, r10
+	cfmv64hr	mvdx10, r4
+	cfmvr64hmi	r1, mvdx3
+	cfmvr64hhi	r2, mvdx7
+	cfmvr64hcs	r12, mvdx12
+	cfmvr64hvs	r3, mvdx0
+	cfmvr64hvc	r13, mvdx14
+	cfmval32cc	mvax0, mvfx10
+	cfmval32ne	mvax1, mvfx15
+	cfmval32le	mvax0, mvfx11
+	cfmval32mi	mvax0, mvfx9
+	cfmval32eq	mvax1, mvfx15
+	cfmv32alge	mvfx9, mvax0
+	cfmv32alal	mvfx3, mvax1
+	cfmv32alle	mvfx7, mvax0
+	cfmv32alne	mvfx12, mvax0
+	cfmv32allt	mvfx0, mvax1
+	cfmvam32pl	mvax2, mvfx3
+	cfmvam32gt	mvax1, mvfx1
+	cfmvam32hi	mvax3, mvfx13
+	cfmvam32vs	mvax3, mvfx4
+	cfmvam32cs	mvax1, mvfx0
+	cfmv32ampl	mvfx15, mvax2
+	cfmv32amls	mvfx4, mvax1
+	cfmv32amcc	mvfx8, mvax3
+	cfmv32amvc	mvfx2, mvax3
+	cfmv32amgt	mvfx6, mvax1
+	cfmvah32eq	mvax1, mvfx5
+	cfmvah32al	mvax2, mvfx12
+	cfmvah32ge	mvax3, mvfx8
+	cfmvah32	mvax2, mvfx6
+	cfmvah32lt	mvax2, mvfx2
+	cfmv32ahls	mvfx0, mvax1
+	cfmv32ah	mvfx10, mvax2
+	cfmv32ahmi	mvfx14, mvax3
+	cfmv32ahhi	mvfx13, mvax2
+	cfmv32ahcs	mvfx1, mvax2
+	cfmva32vs	mvax1, mvfx0
+	cfmva32vc	mvax3, mvfx14
+	cfmva32cc	mvax0, mvfx10
+	cfmva32ne	mvax1, mvfx15
+	cfmva32le	mvax0, mvfx11
+	cfmv32ami	mvfx2, mvax1
+	cfmv32aeq	mvfx5, mvax3
+	cfmv32age	mvfx9, mvax0
+	cfmv32aal	mvfx3, mvax1
+	cfmv32ale	mvfx7, mvax0
+	cfmva64ne	mvax2, mvdx6
+	cfmva64lt	mvax0, mvdx7
+	cfmva64pl	mvax2, mvdx3
+	cfmva64gt	mvax1, mvdx1
+	cfmva64hi	mvax3, mvdx13
+	cfmv64avs	mvdx11, mvax2
+	cfmv64acs	mvdx9, mvax0
+	cfmv64apl	mvdx15, mvax2
+	cfmv64als	mvdx4, mvax1
+	cfmv64acc	mvdx8, mvax3
+	cfmvsc32vc	dspsc, mvdx1
+	cfmvsc32gt	dspsc, mvdx11
+	cfmvsc32eq	dspsc, mvdx5
+	cfmvsc32al	dspsc, mvdx12
+	cfmvsc32ge	dspsc, mvdx8
+	cfmv32sc	mvdx13, dspsc
+	cfmv32sclt	mvdx4, dspsc
+	cfmv32scls	mvdx0, dspsc
+	cfmv32sc	mvdx10, dspsc
+	cfmv32scmi	mvdx14, dspsc
+	cfcpyshi	mvf13, mvf7
+	cfcpyscs	mvf1, mvf12
+	cfcpysvs	mvf11, mvf0
+	cfcpysvc	mvf5, mvf14
+	cfcpyscc	mvf12, mvf10
+	cfcpydne	mvd8, mvd15
+	cfcpydle	mvd6, mvd11
+	cfcpydmi	mvd2, mvd9
+	cfcpydeq	mvd5, mvd15
+	cfcpydge	mvd9, mvd4
 conv:
-	cfcvtsdcc	mvd8, mvf13
-	cfcvtsdvc	mvd2, mvf1
-	cfcvtsdgt	mvd6, mvf11
-	cfcvtsdeq	mvd7, mvf5
-	cfcvtsdal	mvd3, mvf12
-	cfcvtdsge	mvf1, mvd8
-	cfcvtds	mvf13, mvd6
-	cfcvtdslt	mvf4, mvd2
-	cfcvtdsls	mvf0, mvd5
-	cfcvtds	mvf10, mvd9
-	cfcvt32smi	mvf14, mvfx3
-	cfcvt32shi	mvf13, mvfx7
-	cfcvt32scs	mvf1, mvfx12
-	cfcvt32svs	mvf11, mvfx0
-	cfcvt32svc	mvf5, mvfx14
-	cfcvt32dcc	mvd12, mvfx10
-	cfcvt32dne	mvd8, mvfx15
-	cfcvt32dle	mvd6, mvfx11
-	cfcvt32dmi	mvd2, mvfx9
-	cfcvt32deq	mvd5, mvfx15
-	cfcvt64sge	mvf9, mvdx4
-	cfcvt64sal	mvf3, mvdx8
-	cfcvt64sle	mvf7, mvdx2
-	cfcvt64sne	mvf12, mvdx6
-	cfcvt64slt	mvf0, mvdx7
-	cfcvt64dpl	mvd14, mvdx3
-	cfcvt64dgt	mvd10, mvdx1
-	cfcvt64dhi	mvd15, mvdx13
-	cfcvt64dvs	mvd11, mvdx4
-	cfcvt64dcs	mvd9, mvdx0
-	cfcvts32pl	mvfx15, mvf10
-	cfcvts32ls	mvfx4, mvf14
-	cfcvts32cc	mvfx8, mvf13
-	cfcvts32vc	mvfx2, mvf1
-	cfcvts32gt	mvfx6, mvf11
-	cfcvtd32eq	mvfx7, mvd5
-	cfcvtd32al	mvfx3, mvd12
-	cfcvtd32ge	mvfx1, mvd8
-	cfcvtd32	mvfx13, mvd6
-	cfcvtd32lt	mvfx4, mvd2
-	cftruncs32ls	mvfx0, mvf5
-	cftruncs32	mvfx10, mvf9
-	cftruncs32mi	mvfx14, mvf3
-	cftruncs32hi	mvfx13, mvf7
-	cftruncs32cs	mvfx1, mvf12
-	cftruncd32vs	mvfx11, mvd0
-	cftruncd32vc	mvfx5, mvd14
-	cftruncd32cc	mvfx12, mvd10
-	cftruncd32ne	mvfx8, mvd15
-	cftruncd32le	mvfx6, mvd11
+	cfcvtsdal	mvd3, mvf8
+	cfcvtsdle	mvd7, mvf2
+	cfcvtsdne	mvd12, mvf6
+	cfcvtsdlt	mvd0, mvf7
+	cfcvtsdpl	mvd14, mvf3
+	cfcvtdsgt	mvf10, mvd1
+	cfcvtdshi	mvf15, mvd13
+	cfcvtdsvs	mvf11, mvd4
+	cfcvtdscs	mvf9, mvd0
+	cfcvtdspl	mvf15, mvd10
+	cfcvt32sls	mvf4, mvfx14
+	cfcvt32scc	mvf8, mvfx13
+	cfcvt32svc	mvf2, mvfx1
+	cfcvt32sgt	mvf6, mvfx11
+	cfcvt32seq	mvf7, mvfx5
+	cfcvt32dal	mvd3, mvfx12
+	cfcvt32dge	mvd1, mvfx8
+	cfcvt32d	mvd13, mvfx6
+	cfcvt32dlt	mvd4, mvfx2
+	cfcvt32dls	mvd0, mvfx5
+	cfcvt64s	mvf10, mvdx9
+	cfcvt64smi	mvf14, mvdx3
+	cfcvt64shi	mvf13, mvdx7
+	cfcvt64scs	mvf1, mvdx12
+	cfcvt64svs	mvf11, mvdx0
+	cfcvt64dvc	mvd5, mvdx14
+	cfcvt64dcc	mvd12, mvdx10
+	cfcvt64dne	mvd8, mvdx15
+	cfcvt64dle	mvd6, mvdx11
+	cfcvt64dmi	mvd2, mvdx9
+	cfcvts32eq	mvfx5, mvf15
+	cfcvts32ge	mvfx9, mvf4
+	cfcvts32al	mvfx3, mvf8
+	cfcvts32le	mvfx7, mvf2
+	cfcvts32ne	mvfx12, mvf6
+	cfcvtd32lt	mvfx0, mvd7
+	cfcvtd32pl	mvfx14, mvd3
+	cfcvtd32gt	mvfx10, mvd1
+	cfcvtd32hi	mvfx15, mvd13
+	cfcvtd32vs	mvfx11, mvd4
+	cftruncs32cs	mvfx9, mvf0
+	cftruncs32pl	mvfx15, mvf10
+	cftruncs32ls	mvfx4, mvf14
+	cftruncs32cc	mvfx8, mvf13
+	cftruncs32vc	mvfx2, mvf1
+	cftruncd32gt	mvfx6, mvd11
+	cftruncd32eq	mvfx7, mvd5
+	cftruncd32al	mvfx3, mvd12
+	cftruncd32ge	mvfx1, mvd8
+	cftruncd32	mvfx13, mvd6
 shift:
-	cfrshl32mi	mvfx2, mvfx9, r0
-	cfrshl32	mvfx10, mvfx9, lr
-	cfrshl32cc	mvfx8, mvfx13, r5
-	cfrshl32ne	mvfx12, mvfx6, r3
-	cfrshl32vc	mvfx5, mvfx14, r4
-	cfrshl64ge	mvdx1, mvdx8, r2
-	cfrshl64vs	mvdx11, mvdx4, r9
-	cfrshl64eq	mvdx5, mvdx15, r7
-	cfrshl64mi	mvdx14, mvdx3, r8
-	cfrshl64vc	mvdx2, mvdx1, r6
-	cfsh32lt	mvfx0, mvfx7, #-64
-	cfsh32cc	mvfx12, mvfx10, #-20
-	cfsh32	mvfx13, mvfx6, #40
-	cfsh32cs	mvfx9, mvfx0, #-1
-	cfsh32ge	mvfx9, mvfx4, #24
-	cfsh64hi	mvdx13, mvdx7, #33
-	cfsh64gt	mvdx6, mvdx11, #0
-	cfsh64pl	mvdx14, mvdx3, #32
-	cfsh64ne	mvdx8, mvdx15, #-31
-	cfsh64lt	mvdx4, mvdx2, #1
+	cfrshl32lt	mvfx4, mvfx2, r3
+	cfrshl32pl	mvfx15, mvfx10, r4
+	cfrshl32al	mvfx3, mvfx8, r2
+	cfrshl32cs	mvfx1, mvfx12, r9
+	cfrshl32eq	mvfx7, mvfx5, r7
+	cfrshl64gt	mvdx10, mvdx1, r8
+	cfrshl64le	mvdx6, mvdx11, r6
+	cfrshl64ls	mvdx0, mvdx5, sp
+	cfrshl64ls	mvdx4, mvdx14, r11
+	cfrshl64le	mvdx7, mvdx2, r12
+	cfsh32vs	mvfx11, mvfx0, #-1
+	cfsh32al	mvfx3, mvfx12, #24
+	cfsh32hi	mvfx15, mvfx13, #33
+	cfsh32mi	mvfx2, mvfx9, #0
+	cfsh32	mvfx10, mvfx9, #32
+	cfsh64cc	mvdx8, mvdx13, #-31
+	cfsh64ne	mvdx12, mvdx6, #1
+	cfsh64vc	mvdx5, mvdx14, #-32
+	cfsh64ge	mvdx1, mvdx8, #-27
+	cfsh64vs	mvdx11, mvdx4, #-5
 comp:
-	cfcmpspl	sp, mvf10, mvf9
-	cfcmpsal	r11, mvf8, mvf13
-	cfcmpscs	r12, mvf12, mvf6
-	cfcmpseq	sl, mvf5, mvf14
-	cfcmpsgt	r1, mvf1, mvf8
-	cfcmpdle	r15, mvd11, mvd4
-	cfcmpdls	r0, mvd5, mvd15
-	cfcmpdls	lr, mvd14, mvd3
-	cfcmpdle	r5, mvd2, mvd1
-	cfcmpdvs	r3, mvd0, mvd7
-	cfcmp32al	r4, mvfx12, mvfx10
-	cfcmp32hi	r2, mvfx13, mvfx6
-	cfcmp32mi	r9, mvfx9, mvfx0
-	cfcmp32	r7, mvfx9, mvfx4
-	cfcmp32cc	r8, mvfx13, mvfx7
-	cfcmp64ne	r6, mvdx6, mvdx11
-	cfcmp64vc	r13, mvdx14, mvdx3
-	cfcmp64ge	fp, mvdx8, mvdx15
-	cfcmp64vs	ip, mvdx4, mvdx2
-	cfcmp64eq	r10, mvdx15, mvdx10
+	cfcmpseq	r10, mvf15, mvf10
+	cfcmpsmi	r1, mvf3, mvf8
+	cfcmpsvc	pc, mvf1, mvf12
+	cfcmpslt	r0, mvf7, mvf5
+	cfcmpscc	r14, mvf10, mvf1
+	cfcmpd	r5, mvd6, mvd11
+	cfcmpdcs	r3, mvd0, mvd5
+	cfcmpdge	r4, mvd4, mvd14
+	cfcmpdhi	r2, mvd7, mvd2
+	cfcmpdgt	r9, mvd11, mvd0
+	cfcmp32pl	r7, mvfx3, mvfx12
+	cfcmp32ne	r8, mvfx15, mvfx13
+	cfcmp32lt	r6, mvfx2, mvfx9
+	cfcmp32pl	sp, mvfx10, mvfx9
+	cfcmp32al	r11, mvfx8, mvfx13
+	cfcmp64cs	r12, mvdx12, mvdx6
+	cfcmp64eq	sl, mvdx5, mvdx14
+	cfcmp64gt	r1, mvdx1, mvdx8
+	cfcmp64le	r15, mvdx11, mvdx4
+	cfcmp64ls	r0, mvdx5, mvdx15
 fp_arith:
-	cfabssmi	mvf14, mvf3
-	cfabsshi	mvf13, mvf7
-	cfabsscs	mvf1, mvf12
-	cfabssvs	mvf11, mvf0
-	cfabssvc	mvf5, mvf14
-	cfabsdcc	mvd12, mvd10
-	cfabsdne	mvd8, mvd15
-	cfabsdle	mvd6, mvd11
-	cfabsdmi	mvd2, mvd9
-	cfabsdeq	mvd5, mvd15
-	cfnegsge	mvf9, mvf4
-	cfnegsal	mvf3, mvf8
-	cfnegsle	mvf7, mvf2
-	cfnegsne	mvf12, mvf6
-	cfnegslt	mvf0, mvf7
-	cfnegdpl	mvd14, mvd3
-	cfnegdgt	mvd10, mvd1
-	cfnegdhi	mvd15, mvd13
-	cfnegdvs	mvd11, mvd4
-	cfnegdcs	mvd9, mvd0
-	cfaddspl	mvf15, mvf10, mvf9
-	cfaddsal	mvf3, mvf8, mvf13
-	cfaddscs	mvf1, mvf12, mvf6
-	cfaddseq	mvf7, mvf5, mvf14
-	cfaddsgt	mvf10, mvf1, mvf8
-	cfadddle	mvd6, mvd11, mvd4
-	cfadddls	mvd0, mvd5, mvd15
-	cfadddls	mvd4, mvd14, mvd3
-	cfadddle	mvd7, mvd2, mvd1
-	cfadddvs	mvd11, mvd0, mvd7
-	cfsubsal	mvf3, mvf12, mvf10
-	cfsubshi	mvf15, mvf13, mvf6
-	cfsubsmi	mvf2, mvf9, mvf0
-	cfsubs	mvf10, mvf9, mvf4
-	cfsubscc	mvf8, mvf13, mvf7
-	cfsubdne	mvd12, mvd6, mvd11
-	cfsubdvc	mvd5, mvd14, mvd3
-	cfsubdge	mvd1, mvd8, mvd15
-	cfsubdvs	mvd11, mvd4, mvd2
-	cfsubdeq	mvd5, mvd15, mvd10
-	cfmulsmi	mvf14, mvf3, mvf8
-	cfmulsvc	mvf2, mvf1, mvf12
-	cfmulslt	mvf0, mvf7, mvf5
-	cfmulscc	mvf12, mvf10, mvf1
-	cfmuls	mvf13, mvf6, mvf11
-	cfmuldcs	mvd9, mvd0, mvd5
-	cfmuldge	mvd9, mvd4, mvd14
-	cfmuldhi	mvd13, mvd7, mvd2
-	cfmuldgt	mvd6, mvd11, mvd0
-	cfmuldpl	mvd14, mvd3, mvd12
+	cfabssls	mvf4, mvf14
+	cfabsscc	mvf8, mvf13
+	cfabssvc	mvf2, mvf1
+	cfabssgt	mvf6, mvf11
+	cfabsseq	mvf7, mvf5
+	cfabsdal	mvd3, mvd12
+	cfabsdge	mvd1, mvd8
+	cfabsd	mvd13, mvd6
+	cfabsdlt	mvd4, mvd2
+	cfabsdls	mvd0, mvd5
+	cfnegs	mvf10, mvf9
+	cfnegsmi	mvf14, mvf3
+	cfnegshi	mvf13, mvf7
+	cfnegscs	mvf1, mvf12
+	cfnegsvs	mvf11, mvf0
+	cfnegdvc	mvd5, mvd14
+	cfnegdcc	mvd12, mvd10
+	cfnegdne	mvd8, mvd15
+	cfnegdle	mvd6, mvd11
+	cfnegdmi	mvd2, mvd9
+	cfaddseq	mvf5, mvf15, mvf10
+	cfaddsmi	mvf14, mvf3, mvf8
+	cfaddsvc	mvf2, mvf1, mvf12
+	cfaddslt	mvf0, mvf7, mvf5
+	cfaddscc	mvf12, mvf10, mvf1
+	cfaddd	mvd13, mvd6, mvd11
+	cfadddcs	mvd9, mvd0, mvd5
+	cfadddge	mvd9, mvd4, mvd14
+	cfadddhi	mvd13, mvd7, mvd2
+	cfadddgt	mvd6, mvd11, mvd0
+	cfsubspl	mvf14, mvf3, mvf12
+	cfsubsne	mvf8, mvf15, mvf13
+	cfsubslt	mvf4, mvf2, mvf9
+	cfsubspl	mvf15, mvf10, mvf9
+	cfsubsal	mvf3, mvf8, mvf13
+	cfsubdcs	mvd1, mvd12, mvd6
+	cfsubdeq	mvd7, mvd5, mvd14
+	cfsubdgt	mvd10, mvd1, mvd8
+	cfsubdle	mvd6, mvd11, mvd4
+	cfsubdls	mvd0, mvd5, mvd15
+	cfmulsls	mvf4, mvf14, mvf3
+	cfmulsle	mvf7, mvf2, mvf1
+	cfmulsvs	mvf11, mvf0, mvf7
+	cfmulsal	mvf3, mvf12, mvf10
+	cfmulshi	mvf15, mvf13, mvf6
+	cfmuldmi	mvd2, mvd9, mvd0
+	cfmuld	mvd10, mvd9, mvd4
+	cfmuldcc	mvd8, mvd13, mvd7
+	cfmuldne	mvd12, mvd6, mvd11
+	cfmuldvc	mvd5, mvd14, mvd3
 int_arith:
-	cfabs32ne	mvfx8, mvfx15
-	cfabs32le	mvfx6, mvfx11
-	cfabs32mi	mvfx2, mvfx9
-	cfabs32eq	mvfx5, mvfx15
-	cfabs32ge	mvfx9, mvfx4
-	cfabs64al	mvdx3, mvdx8
-	cfabs64le	mvdx7, mvdx2
-	cfabs64ne	mvdx12, mvdx6
-	cfabs64lt	mvdx0, mvdx7
-	cfabs64pl	mvdx14, mvdx3
-	cfneg32gt	mvfx10, mvfx1
-	cfneg32hi	mvfx15, mvfx13
-	cfneg32vs	mvfx11, mvfx4
-	cfneg32cs	mvfx9, mvfx0
-	cfneg32pl	mvfx15, mvfx10
-	cfneg64ls	mvdx4, mvdx14
-	cfneg64cc	mvdx8, mvdx13
-	cfneg64vc	mvdx2, mvdx1
-	cfneg64gt	mvdx6, mvdx11
-	cfneg64eq	mvdx7, mvdx5
-	cfadd32al	mvfx3, mvfx12, mvfx10
-	cfadd32hi	mvfx15, mvfx13, mvfx6
-	cfadd32mi	mvfx2, mvfx9, mvfx0
-	cfadd32	mvfx10, mvfx9, mvfx4
-	cfadd32cc	mvfx8, mvfx13, mvfx7
-	cfadd64ne	mvdx12, mvdx6, mvdx11
-	cfadd64vc	mvdx5, mvdx14, mvdx3
-	cfadd64ge	mvdx1, mvdx8, mvdx15
-	cfadd64vs	mvdx11, mvdx4, mvdx2
-	cfadd64eq	mvdx5, mvdx15, mvdx10
-	cfsub32mi	mvfx14, mvfx3, mvfx8
-	cfsub32vc	mvfx2, mvfx1, mvfx12
-	cfsub32lt	mvfx0, mvfx7, mvfx5
-	cfsub32cc	mvfx12, mvfx10, mvfx1
-	cfsub32	mvfx13, mvfx6, mvfx11
-	cfsub64cs	mvdx9, mvdx0, mvdx5
-	cfsub64ge	mvdx9, mvdx4, mvdx14
-	cfsub64hi	mvdx13, mvdx7, mvdx2
-	cfsub64gt	mvdx6, mvdx11, mvdx0
-	cfsub64pl	mvdx14, mvdx3, mvdx12
-	cfmul32ne	mvfx8, mvfx15, mvfx13
-	cfmul32lt	mvfx4, mvfx2, mvfx9
-	cfmul32pl	mvfx15, mvfx10, mvfx9
-	cfmul32al	mvfx3, mvfx8, mvfx13
-	cfmul32cs	mvfx1, mvfx12, mvfx6
-	cfmul64eq	mvdx7, mvdx5, mvdx14
-	cfmul64gt	mvdx10, mvdx1, mvdx8
-	cfmul64le	mvdx6, mvdx11, mvdx4
-	cfmul64ls	mvdx0, mvdx5, mvdx15
-	cfmul64ls	mvdx4, mvdx14, mvdx3
-	cfmac32le	mvfx7, mvfx2, mvfx1
-	cfmac32vs	mvfx11, mvfx0, mvfx7
-	cfmac32al	mvfx3, mvfx12, mvfx10
-	cfmac32hi	mvfx15, mvfx13, mvfx6
-	cfmac32mi	mvfx2, mvfx9, mvfx0
-	cfmsc32	mvfx10, mvfx9, mvfx4
-	cfmsc32cc	mvfx8, mvfx13, mvfx7
-	cfmsc32ne	mvfx12, mvfx6, mvfx11
-	cfmsc32vc	mvfx5, mvfx14, mvfx3
-	cfmsc32ge	mvfx1, mvfx8, mvfx15
+	cfabs32ge	mvfx1, mvfx8
+	cfabs32	mvfx13, mvfx6
+	cfabs32lt	mvfx4, mvfx2
+	cfabs32ls	mvfx0, mvfx5
+	cfabs32	mvfx10, mvfx9
+	cfabs64mi	mvdx14, mvdx3
+	cfabs64hi	mvdx13, mvdx7
+	cfabs64cs	mvdx1, mvdx12
+	cfabs64vs	mvdx11, mvdx0
+	cfabs64vc	mvdx5, mvdx14
+	cfneg32cc	mvfx12, mvfx10
+	cfneg32ne	mvfx8, mvfx15
+	cfneg32le	mvfx6, mvfx11
+	cfneg32mi	mvfx2, mvfx9
+	cfneg32eq	mvfx5, mvfx15
+	cfneg64ge	mvdx9, mvdx4
+	cfneg64al	mvdx3, mvdx8
+	cfneg64le	mvdx7, mvdx2
+	cfneg64ne	mvdx12, mvdx6
+	cfneg64lt	mvdx0, mvdx7
+	cfadd32pl	mvfx14, mvfx3, mvfx12
+	cfadd32ne	mvfx8, mvfx15, mvfx13
+	cfadd32lt	mvfx4, mvfx2, mvfx9
+	cfadd32pl	mvfx15, mvfx10, mvfx9
+	cfadd32al	mvfx3, mvfx8, mvfx13
+	cfadd64cs	mvdx1, mvdx12, mvdx6
+	cfadd64eq	mvdx7, mvdx5, mvdx14
+	cfadd64gt	mvdx10, mvdx1, mvdx8
+	cfadd64le	mvdx6, mvdx11, mvdx4
+	cfadd64ls	mvdx0, mvdx5, mvdx15
+	cfsub32ls	mvfx4, mvfx14, mvfx3
+	cfsub32le	mvfx7, mvfx2, mvfx1
+	cfsub32vs	mvfx11, mvfx0, mvfx7
+	cfsub32al	mvfx3, mvfx12, mvfx10
+	cfsub32hi	mvfx15, mvfx13, mvfx6
+	cfsub64mi	mvdx2, mvdx9, mvdx0
+	cfsub64	mvdx10, mvdx9, mvdx4
+	cfsub64cc	mvdx8, mvdx13, mvdx7
+	cfsub64ne	mvdx12, mvdx6, mvdx11
+	cfsub64vc	mvdx5, mvdx14, mvdx3
+	cfmul32ge	mvfx1, mvfx8, mvfx15
+	cfmul32vs	mvfx11, mvfx4, mvfx2
+	cfmul32eq	mvfx5, mvfx15, mvfx10
+	cfmul32mi	mvfx14, mvfx3, mvfx8
+	cfmul32vc	mvfx2, mvfx1, mvfx12
+	cfmul64lt	mvdx0, mvdx7, mvdx5
+	cfmul64cc	mvdx12, mvdx10, mvdx1
+	cfmul64	mvdx13, mvdx6, mvdx11
+	cfmul64cs	mvdx9, mvdx0, mvdx5
+	cfmul64ge	mvdx9, mvdx4, mvdx14
+	cfmac32hi	mvfx13, mvfx7, mvfx2
+	cfmac32gt	mvfx6, mvfx11, mvfx0
+	cfmac32pl	mvfx14, mvfx3, mvfx12
+	cfmac32ne	mvfx8, mvfx15, mvfx13
+	cfmac32lt	mvfx4, mvfx2, mvfx9
+	cfmsc32pl	mvfx15, mvfx10, mvfx9
+	cfmsc32al	mvfx3, mvfx8, mvfx13
+	cfmsc32cs	mvfx1, mvfx12, mvfx6
+	cfmsc32eq	mvfx7, mvfx5, mvfx14
+	cfmsc32gt	mvfx10, mvfx1, mvfx8
 acc_arith:
-	cfmadd32vs	mvax3, mvfx4, mvfx2, mvfx9
-	cfmadd32eq	mvax1, mvfx15, mvfx10, mvfx9
-	cfmadd32mi	mvax1, mvfx3, mvfx8, mvfx13
-	cfmadd32vc	mvax0, mvfx1, mvfx12, mvfx6
-	cfmadd32lt	mvax0, mvfx7, mvfx5, mvfx14
-	cfmsub32cc	mvax0, mvfx10, mvfx1, mvfx8
-	cfmsub32	mvax2, mvfx6, mvfx11, mvfx4
-	cfmsub32cs	mvax1, mvfx0, mvfx5, mvfx15
-	cfmsub32ge	mvax2, mvfx4, mvfx14, mvfx3
-	cfmsub32hi	mvax3, mvfx7, mvfx2, mvfx1
-	cfmadda32gt	mvax0, mvax1, mvfx0, mvfx7
-	cfmadda32pl	mvax2, mvax2, mvfx12, mvfx10
-	cfmadda32ne	mvax1, mvax3, mvfx13, mvfx6
-	cfmadda32lt	mvax2, mvax0, mvfx9, mvfx0
-	cfmadda32pl	mvax3, mvax2, mvfx9, mvfx4
-	cfmsuba32al	mvax3, mvax1, mvfx13, mvfx7
-	cfmsuba32cs	mvax3, mvax2, mvfx6, mvfx11
-	cfmsuba32eq	mvax1, mvax3, mvfx14, mvfx3
-	cfmsuba32gt	mvax1, mvax3, mvfx8, mvfx15
-	cfmsuba32le	mvax0, mvax3, mvfx4, mvfx2
+	cfmadd32le	mvax0, mvfx11, mvfx4, mvfx2
+	cfmadd32ls	mvax0, mvfx5, mvfx15, mvfx10
+	cfmadd32ls	mvax0, mvfx14, mvfx3, mvfx8
+	cfmadd32le	mvax2, mvfx2, mvfx1, mvfx12
+	cfmadd32vs	mvax1, mvfx0, mvfx7, mvfx5
+	cfmsub32al	mvax2, mvfx12, mvfx10, mvfx1
+	cfmsub32hi	mvax3, mvfx13, mvfx6, mvfx11
+	cfmsub32mi	mvax0, mvfx9, mvfx0, mvfx5
+	cfmsub32	mvax2, mvfx9, mvfx4, mvfx14
+	cfmsub32cc	mvax1, mvfx13, mvfx7, mvfx2
+	cfmadda32ne	mvax2, mvax0, mvfx11, mvfx0
+	cfmadda32vc	mvax3, mvax2, mvfx3, mvfx12
+	cfmadda32ge	mvax3, mvax1, mvfx15, mvfx13
+	cfmadda32vs	mvax3, mvax2, mvfx2, mvfx9
+	cfmadda32eq	mvax1, mvax3, mvfx10, mvfx9
+	cfmsuba32mi	mvax1, mvax3, mvfx8, mvfx13
+	cfmsuba32vc	mvax0, mvax3, mvfx12, mvfx6
+	cfmsuba32lt	mvax0, mvax1, mvfx5, mvfx14
+	cfmsuba32cc	mvax0, mvax1, mvfx1, mvfx8
+	cfmsuba32	mvax2, mvax0, mvfx11, mvfx4
diff --git a/gas/testsuite/gas/arm/nomapping.d b/gas/testsuite/gas/arm/nomapping.d
new file mode 100644
index 000000000000..76f283345e11
--- /dev/null
+++ b/gas/testsuite/gas/arm/nomapping.d
@@ -0,0 +1,8 @@
+#nm: -n
+#name: ARM Mapping Symbols Ignored
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Check ARM ELF Mapping Symbols are ignored properly
+0+0 t sym1
+0+c t sym2
diff --git a/gas/testsuite/gas/arm/nomapping.s b/gas/testsuite/gas/arm/nomapping.s
new file mode 100644
index 000000000000..efe92ae57e1b
--- /dev/null
+++ b/gas/testsuite/gas/arm/nomapping.s
@@ -0,0 +1,19 @@
+	.text
+	.arm
+sym1:
+	nop
+	.thumb
+	nop
+	nop
+$a.foo:
+$t.foo:
+$d.foo:
+@ Obsolete mapping symbols generated by armcc.
+$m:
+$m.foo:
+$f:
+$f.foo:
+$p:
+$p.foo:
+	.word 0
+sym2:
diff --git a/gas/testsuite/gas/arm/offset.d b/gas/testsuite/gas/arm/offset.d
new file mode 100644
index 000000000000..f6957c074ed8
--- /dev/null
+++ b/gas/testsuite/gas/arm/offset.d
@@ -0,0 +1,11 @@
+# name: OFFSET_IMM regression
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0 <[^>]+> e51f0004 ?	ldr	r0, \[pc, #-4\]	; 0+4 <[^>]+>
+0+4 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+8 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+c <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/offset.s b/gas/testsuite/gas/arm/offset.s
index ba3ecbabe644..53d567def2d4 100644
--- a/gas/testsuite/gas/arm/offset.s
+++ b/gas/testsuite/gas/arm/offset.s
@@ -1,5 +1,14 @@
-@ test for OFFSET_IMM reloc against global symbols
+	@ test that an OFFSET_IMM reloc against a global symbol is
+	@ still resolved by the assembler, as long as the symbol is in
+	@ the same section as the reference
+	.text
+	.globl l
+	.globl foo
+l:
+	ldr r0, foo
+foo:
+	nop
 
-.globl foo
-foo: .word 0
-ldr r0, foo
+	@ pad section for a.out's benefit
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/pic.d b/gas/testsuite/gas/arm/pic.d
index 6c4a04330635..f5232a36992e 100644
--- a/gas/testsuite/gas/arm/pic.d
+++ b/gas/testsuite/gas/arm/pic.d
@@ -1,17 +1,24 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: PIC
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# VxWorks needs a special variant of this file.
+#skip: *-*-vxworks*
 
 # Test generation of PIC
 
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-00+0 <[^>]*> ebfffffe 	bl	00+0 <[^>]*>
-			0: R_ARM_PC24	foo
-00+4 <[^>]*> ebfffffe 	bl	00+4 <[^>]*>
+00+0 <[^>]*> eb...... 	bl	00+. <[^>]*>
+			0: R_ARM_(PC24|CALL)	foo.*
+00+4 <[^>]*> eb...... 	bl	0[0123456789abcdef]+ <[^>]*>
 			4: R_ARM_PLT32	foo
 	\.\.\.
 			8: R_ARM_ABS32	sym
 			c: R_ARM_GOT32	sym
-			10: R_ARM_GOTOFF	sym
+			10: R_ARM_GOTOFF32	sym
 			14: R_ARM_GOTPC	_GLOBAL_OFFSET_TABLE_
+			18: R_ARM_TARGET1	foo2
+			1c: R_ARM_SBREL32	foo3
+			20: R_ARM_TARGET2	foo4
diff --git a/gas/testsuite/gas/arm/pic.s b/gas/testsuite/gas/arm/pic.s
index f538908e9066..3c3c3293b6db 100644
--- a/gas/testsuite/gas/arm/pic.s
+++ b/gas/testsuite/gas/arm/pic.s
@@ -9,3 +9,6 @@
 	.word	sym(GOTOFF)
 1:
 	.word	_GLOBAL_OFFSET_TABLE_ - 1b
+	.word foo2(TARGET1)
+	.word foo3(SBREL)
+	.word foo4(TARGET2)
diff --git a/gas/testsuite/gas/arm/pic_vxworks.d b/gas/testsuite/gas/arm/pic_vxworks.d
new file mode 100644
index 000000000000..f7db8aa41afe
--- /dev/null
+++ b/gas/testsuite/gas/arm/pic_vxworks.d
@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: PIC
+#source: pic.s
+#not-skip: *-*-vxworks*
+
+# Test generation of PIC
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00+0 <[^>]*> eb000000 	bl	.*
+			0: R_ARM_PC24	foo\+0xfffffff8
+00+4 <[^>]*> eb000000 	bl	.*
+			4: R_ARM_PLT32	foo\+0xfffffff8
+	\.\.\.
+			8: R_ARM_ABS32	sym
+			c: R_ARM_GOT32	sym
+			10: R_ARM_GOTOFF32	sym
+			14: R_ARM_GOTPC	_GLOBAL_OFFSET_TABLE_
+			18: R_ARM_TARGET1	foo2
+			1c: R_ARM_SBREL32	foo3
+			20: R_ARM_TARGET2	foo4
diff --git a/gas/testsuite/gas/arm/r15-bad.d b/gas/testsuite/gas/arm/r15-bad.d
new file mode 100644
index 000000000000..ec7c3055942c
--- /dev/null
+++ b/gas/testsuite/gas/arm/r15-bad.d
@@ -0,0 +1,2 @@
+#name: Invalid use of r15 errors
+#error-output: r15-bad.l
diff --git a/gas/testsuite/gas/arm/r15-bad.l b/gas/testsuite/gas/arm/r15-bad.l
index b0c370fdc87b..a172e9e9ef39 100644
--- a/gas/testsuite/gas/arm/r15-bad.l
+++ b/gas/testsuite/gas/arm/r15-bad.l
@@ -1,6 +1,6 @@
 [^:]*: Assembler messages:
-[^:]*:5: Error: r15 not allowed here -- `mul r15,r1'
-[^:]*:6: Error: r15 not allowed here -- `mul r1,r15'
+[^:]*:5: Error: r15 not allowed here -- `mul r15,r1,r2'
+[^:]*:6: Error: r15 not allowed here -- `mul r1,r15,r2'
 [^:]*:7: Error: r15 not allowed here -- `mla r15,r2,r3,r4'
 [^:]*:8: Error: r15 not allowed here -- `mla r1,r15,r3,r4'
 [^:]*:9: Error: r15 not allowed here -- `mla r1,r2,r15,r4'
@@ -30,7 +30,7 @@
 [^:]*:33: Error: r15 not allowed here -- `umaal r1,r2,r3,r15'
 [^:]*:34: Error: r15 not allowed here -- `strex r15,r2,[[]r3[]]'
 [^:]*:35: Error: r15 not allowed here -- `strex r1,r15,[[]r3[]]'
-[^:]*:36: Error: r15 not allowed here -- `strex r1,r2,[[]r15[]]'
+[^:]*:36: Error: instruction does not accept this addressing mode -- `strex r1,r2,[[]r15[]]'
 [^:]*:37: Error: r15 not allowed here -- `ssat r15,#1,r2'
 [^:]*:38: Error: r15 not allowed here -- `ssat r1,#1,r15'
 [^:]*:39: Error: r15 not allowed here -- `ssat16 r15,#1,r2'
@@ -58,7 +58,7 @@
 [^:]*:61: Error: r15 not allowed here -- `pkhtb r1,r15,r3'
 [^:]*:62: Error: r15 not allowed here -- `pkhtb r1,r2,r15'
 [^:]*:63: Error: r15 not allowed here -- `ldrex r15,[[]r2[]]'
-[^:]*:64: Error: r15 not allowed here -- `ldrex r1,[[]r15[]]'
-[^:]*:65: Error: r15 not allowed in swap -- `swp r15,r2,[[]r3[]]'
-[^:]*:66: Error: r15 not allowed in swap -- `swp r1,r15,[[]r3[]]'
+[^:]*:64: Error: instruction does not accept this addressing mode -- `ldrex r1,[[]r15[]]'
+[^:]*:65: Error: r15 not allowed here -- `swp r15,r2,[[]r3[]]'
+[^:]*:66: Error: r15 not allowed here -- `swp r1,r15,[[]r3[]]'
 [^:]*:67: Error: r15 not allowed here -- `swp r1,r2,[[]r15[]]'
diff --git a/gas/testsuite/gas/arm/r15-bad.s b/gas/testsuite/gas/arm/r15-bad.s
index 5c91e727db98..59a6ea83dd76 100644
--- a/gas/testsuite/gas/arm/r15-bad.s
+++ b/gas/testsuite/gas/arm/r15-bad.s
@@ -2,8 +2,8 @@
 .align 0
 
 label:
-	mul r15, r1
-	mul r1, r15
+	mul r15, r1, r2
+	mul r1, r15, r2
 	mla r15, r2, r3, r4
 	mla r1, r15, r3, r4
 	mla r1, r2, r15, r4
diff --git a/gas/testsuite/gas/arm/reg-alias.d b/gas/testsuite/gas/arm/reg-alias.d
new file mode 100644
index 000000000000..d9b4be29acbf
--- /dev/null
+++ b/gas/testsuite/gas/arm/reg-alias.d
@@ -0,0 +1,10 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Case Sensitive Register Aliases
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+0 <.*> ee060f10 	mcr	15, 0, r0, cr6, cr0, \{0\}
+0+4 <.*> e1a00000 	nop			\(mov r0,r0\)
+0+8 <.*> e1a00000 	nop			\(mov r0,r0\)
+0+c <.*> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/reg-alias.s b/gas/testsuite/gas/arm/reg-alias.s
new file mode 100644
index 000000000000..5086b8b4ca10
--- /dev/null
+++ b/gas/testsuite/gas/arm/reg-alias.s
@@ -0,0 +1,14 @@
+	@ Test case-sensitive register aliases
+	.text
+	.global fred
+fred:
+	
+MMUPurgeTLBReg      .req c6
+MMUCP               .req p15
+	
+MCR     MMUCP, 0, a1, MMUPurgeTLBReg, c0, 0
+	@ The NOPs are here for ports like arm-aout which will pad
+	@ the .text section to a 16 byte boundary.
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/req.d b/gas/testsuite/gas/arm/req.d
new file mode 100644
index 000000000000..41707fffdd27
--- /dev/null
+++ b/gas/testsuite/gas/arm/req.d
@@ -0,0 +1,3 @@
+#name: .req errors
+#as: -mcpu=arm7m
+#error-output: req.l
diff --git a/gas/testsuite/gas/arm/req.l b/gas/testsuite/gas/arm/req.l
index 6dbf135766c0..165d1d81df3a 100644
--- a/gas/testsuite/gas/arm/req.l
+++ b/gas/testsuite/gas/arm/req.l
@@ -1,3 +1,3 @@
 [^:]*: Assembler messages:
-[^:]*:18: Error: register expected, not 'foo,foo,foo' -- `add foo,foo,foo'
-[^:]*:24: Error: register expected, not 'r0,r0,r0' -- `add r0,r0,r0'
+[^:]*:18: Error: ARM register expected -- `add foo,foo,foo'
+[^:]*:21: Warning: ignoring attempt to undefine built-in register 'r0'
diff --git a/gas/testsuite/gas/arm/req.s b/gas/testsuite/gas/arm/req.s
index 212308a6b424..341f66d1bf4b 100644
--- a/gas/testsuite/gas/arm/req.s
+++ b/gas/testsuite/gas/arm/req.s
@@ -2,7 +2,7 @@
 	.global test_dot_req_and_unreq
 test_dot_req_and_unreq:
 
-	#  Check that builtin register alias 'r0' works.
+	# Check that builtin register alias 'r0' works.
 	add r0, r0, r0
 
 	# Create an alias for r0.
@@ -17,9 +17,9 @@ test_dot_req_and_unreq:
 	# And make sure that it no longer works.
 	add foo, foo, foo
 
-	# Finally remove the builtin alias for r0.
+	# Attempt to remove the builtin alias for r0.
         .unreq r0
 
-	# And make sure that this no longer works.
+	# That is ignored, so this should still work.
 	add r0, r0, r0
 	
diff --git a/gas/testsuite/gas/arm/svc.d b/gas/testsuite/gas/arm/svc.d
new file mode 100644
index 000000000000..fdeb9302083b
--- /dev/null
+++ b/gas/testsuite/gas/arm/svc.d
@@ -0,0 +1,15 @@
+# name: SWI/SVC instructions
+# objdump: -dr --prefix-addresses --show-raw-insn
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> ef123456 	(swi|svc)	0x00123456
+0+004 <[^>]+> ef876543 	(swi|svc)	0x00876543
+0+008 <[^>]+> ef123456 	(swi|svc)	0x00123456
+0+00c <[^>]+> ef876543 	(swi|svc)	0x00876543
+0+010 <[^>]+> df5a      	(swi|svc)	90
+0+012 <[^>]+> dfa5      	(swi|svc)	165
+0+014 <[^>]+> df5a      	(swi|svc)	90
+0+016 <[^>]+> dfa5      	(swi|svc)	165
diff --git a/gas/testsuite/gas/arm/svc.s b/gas/testsuite/gas/arm/svc.s
new file mode 100644
index 000000000000..734bd75b1c1c
--- /dev/null
+++ b/gas/testsuite/gas/arm/svc.s
@@ -0,0 +1,15 @@
+	.text
+	.arch armv4t
+	.syntax unified
+foo:
+	swi 0x123456
+	swi 0x876543
+	svc 0x123456
+	svc 0x876543
+
+	.thumb
+bar:
+	swi 0x5a
+	swi 0xa5
+	svc 0x5a
+	svc 0xa5
diff --git a/gas/testsuite/gas/arm/t16-bad.d b/gas/testsuite/gas/arm/t16-bad.d
new file mode 100644
index 000000000000..b5603addc09f
--- /dev/null
+++ b/gas/testsuite/gas/arm/t16-bad.d
@@ -0,0 +1,3 @@
+#name: Valid ARM, invalid Thumb
+#as: -march=armv6k
+#error-output: t16-bad.l
diff --git a/gas/testsuite/gas/arm/t16-bad.l b/gas/testsuite/gas/arm/t16-bad.l
new file mode 100644
index 000000000000..7c322609ffe0
--- /dev/null
+++ b/gas/testsuite/gas/arm/t16-bad.l
@@ -0,0 +1,186 @@
+[^:]*: Assembler messages:
+[^:]*:36: Error: lo register required -- `tst r8,r0'
+[^:]*:36: Error: lo register required -- `tst r0,r8'
+[^:]*:36: Error: unshifted register required -- `tst r0,#12'
+[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl#2'
+[^:]*:36: Error: unshifted register required -- `tst r0,r1,lsl r3'
+[^:]*:37: Error: lo register required -- `cmn r8,r0'
+[^:]*:37: Error: lo register required -- `cmn r0,r8'
+[^:]*:37: Error: unshifted register required -- `cmn r0,#12'
+[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl#2'
+[^:]*:37: Error: unshifted register required -- `cmn r0,r1,lsl r3'
+[^:]*:38: Error: lo register required -- `mvn r8,r0'
+[^:]*:38: Error: lo register required -- `mvn r0,r8'
+[^:]*:38: Error: unshifted register required -- `mvn r0,#12'
+[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl#2'
+[^:]*:38: Error: unshifted register required -- `mvn r0,r1,lsl r3'
+[^:]*:39: Error: lo register required -- `neg r8,r0'
+[^:]*:39: Error: lo register required -- `neg r0,r8'
+[^:]*:40: Error: lo register required -- `rev r8,r0'
+[^:]*:40: Error: lo register required -- `rev r0,r8'
+[^:]*:41: Error: lo register required -- `rev16 r8,r0'
+[^:]*:41: Error: lo register required -- `rev16 r0,r8'
+[^:]*:42: Error: lo register required -- `revsh r8,r0'
+[^:]*:42: Error: lo register required -- `revsh r0,r8'
+[^:]*:43: Error: lo register required -- `sxtb r8,r0'
+[^:]*:43: Error: lo register required -- `sxtb r0,r8'
+[^:]*:43: Error: Thumb encoding does not support rotation -- `sxtb r0,r1,ror#8'
+[^:]*:44: Error: lo register required -- `sxth r8,r0'
+[^:]*:44: Error: lo register required -- `sxth r0,r8'
+[^:]*:44: Error: Thumb encoding does not support rotation -- `sxth r0,r1,ror#8'
+[^:]*:45: Error: lo register required -- `uxtb r8,r0'
+[^:]*:45: Error: lo register required -- `uxtb r0,r8'
+[^:]*:45: Error: Thumb encoding does not support rotation -- `uxtb r0,r1,ror#8'
+[^:]*:46: Error: lo register required -- `uxth r8,r0'
+[^:]*:46: Error: lo register required -- `uxth r0,r8'
+[^:]*:46: Error: Thumb encoding does not support rotation -- `uxth r0,r1,ror#8'
+[^:]*:48: Error: dest must overlap one source register -- `adc r1,r2,r3'
+[^:]*:48: Error: lo register required -- `adc r8,r0'
+[^:]*:48: Error: lo register required -- `adc r0,r8'
+[^:]*:48: Error: unshifted register required -- `adc r0,#12'
+[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl#2'
+[^:]*:48: Error: unshifted register required -- `adc r0,r1,lsl r3'
+[^:]*:49: Error: dest must overlap one source register -- `and r1,r2,r3'
+[^:]*:49: Error: lo register required -- `and r8,r0'
+[^:]*:49: Error: lo register required -- `and r0,r8'
+[^:]*:49: Error: unshifted register required -- `and r0,#12'
+[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl#2'
+[^:]*:49: Error: unshifted register required -- `and r0,r1,lsl r3'
+[^:]*:50: Error: dest and source1 must be the same register -- `bic r1,r2,r3'
+[^:]*:50: Error: lo register required -- `bic r8,r0'
+[^:]*:50: Error: lo register required -- `bic r0,r8'
+[^:]*:50: Error: unshifted register required -- `bic r0,#12'
+[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl#2'
+[^:]*:50: Error: unshifted register required -- `bic r0,r1,lsl r3'
+[^:]*:51: Error: dest must overlap one source register -- `eor r1,r2,r3'
+[^:]*:51: Error: lo register required -- `eor r8,r0'
+[^:]*:51: Error: lo register required -- `eor r0,r8'
+[^:]*:51: Error: unshifted register required -- `eor r0,#12'
+[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl#2'
+[^:]*:51: Error: unshifted register required -- `eor r0,r1,lsl r3'
+[^:]*:52: Error: dest must overlap one source register -- `orr r1,r2,r3'
+[^:]*:52: Error: lo register required -- `orr r8,r0'
+[^:]*:52: Error: lo register required -- `orr r0,r8'
+[^:]*:52: Error: unshifted register required -- `orr r0,#12'
+[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl#2'
+[^:]*:52: Error: unshifted register required -- `orr r0,r1,lsl r3'
+[^:]*:53: Error: dest and source1 must be the same register -- `sbc r1,r2,r3'
+[^:]*:53: Error: lo register required -- `sbc r8,r0'
+[^:]*:53: Error: lo register required -- `sbc r0,r8'
+[^:]*:53: Error: unshifted register required -- `sbc r0,#12'
+[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl#2'
+[^:]*:53: Error: unshifted register required -- `sbc r0,r1,lsl r3'
+[^:]*:54: Error: dest must overlap one source register -- `mul r1,r2,r3'
+[^:]*:54: Error: lo register required -- `mul r8,r0'
+[^:]*:54: Error: lo register required -- `mul r0,r8'
+[^:]*:62: Error: lo register required -- `asr r8,r0,#12'
+[^:]*:62: Error: lo register required -- `asr r0,r8,#12'
+[^:]*:62: Error: lo register required -- `asr r8,r0'
+[^:]*:62: Error: lo register required -- `asr r0,r8'
+[^:]*:63: Error: lo register required -- `lsl r8,r0,#12'
+[^:]*:63: Error: lo register required -- `lsl r0,r8,#12'
+[^:]*:63: Error: lo register required -- `lsl r8,r0'
+[^:]*:63: Error: lo register required -- `lsl r0,r8'
+[^:]*:64: Error: lo register required -- `lsr r8,r0,#12'
+[^:]*:64: Error: lo register required -- `lsr r0,r8,#12'
+[^:]*:64: Error: lo register required -- `lsr r8,r0'
+[^:]*:64: Error: lo register required -- `lsr r0,r8'
+[^:]*:65: Error: lo register required -- `ror r8,r0,#12'
+[^:]*:65: Error: lo register required -- `ror r0,r8,#12'
+[^:]*:65: Error: lo register required -- `ror r8,r0'
+[^:]*:65: Error: lo register required -- `ror r0,r8'
+[^:]*:66: Error: ror #imm not supported -- `ror r0,r1,#12'
+[^:]*:69: Error: unshifted register required -- `add r0,r1,lsl#2'
+[^:]*:70: Error: unshifted register required -- `add r0,r1,lsl r3'
+[^:]*:71: Error: lo register required -- `add r8,r0,#1'
+[^:]*:72: Error: lo register required -- `add r0,r8,#1'
+[^:]*:73: Error: lo register required -- `add r8,#10'
+[^:]*:74: Error: dest must overlap one source register -- `add r8,r1,r2'
+[^:]*:75: Error: dest must overlap one source register -- `add r1,r8,r2'
+[^:]*:76: Error: dest must overlap one source register -- `add r1,r2,r8'
+[^:]*:77: Error: lo register required -- `add r8,pc,#4'
+[^:]*:78: Error: lo register required -- `add r8,sp,#4'
+[^:]*:80: Error: lo register required -- `sub r8,r0'
+[^:]*:80: Error: lo register required -- `sub r0,r8'
+[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl#2'
+[^:]*:80: Error: unshifted register required -- `sub r0,r1,lsl r3'
+[^:]*:81: Error: lo register required -- `sub r8,r0,#1'
+[^:]*:82: Error: lo register required -- `sub r0,r8,#1'
+[^:]*:83: Error: lo register required -- `sub r8,#10'
+[^:]*:84: Error: lo register required -- `sub r8,r1,r2'
+[^:]*:85: Error: lo register required -- `sub r1,r8,r2'
+[^:]*:86: Error: lo register required -- `sub r1,r2,r8'
+[^:]*:90: Error: only lo regs allowed with immediate -- `cmp r8,#255'
+[^:]*:94: Error: only lo regs allowed with immediate -- `mov r8,#255'
+[^:]*:106: Error: lo register required -- `ldr r8,\[r0\]'
+[^:]*:106: Error: lo register required -- `ldr r0,\[r8\]'
+[^:]*:106: Error: lo register required -- `ldr r0,\[r0,r8\]'
+[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,#4\]!'
+[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],#4'
+[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,-r2\]'
+[^:]*:106: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1\],r2'
+[^:]*:107: Error: lo register required -- `ldrb r8,\[r0\]'
+[^:]*:107: Error: lo register required -- `ldrb r0,\[r8\]'
+[^:]*:107: Error: lo register required -- `ldrb r0,\[r0,r8\]'
+[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,#4\]!'
+[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],#4'
+[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1,-r2\]'
+[^:]*:107: Error: Thumb does not support this addressing mode -- `ldrb r0,\[r1\],r2'
+[^:]*:108: Error: lo register required -- `ldrh r8,\[r0\]'
+[^:]*:108: Error: lo register required -- `ldrh r0,\[r8\]'
+[^:]*:108: Error: lo register required -- `ldrh r0,\[r0,r8\]'
+[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,#4\]!'
+[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],#4'
+[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1,-r2\]'
+[^:]*:108: Error: Thumb does not support this addressing mode -- `ldrh r0,\[r1\],r2'
+[^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]'
+[^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]'
+[^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]'
+[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!'
+[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4'
+[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]'
+[^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2'
+[^:]*:110: Error: lo register required -- `ldrsh r8,\[r0\]'
+[^:]*:110: Error: lo register required -- `ldrsh r0,\[r8\]'
+[^:]*:110: Error: lo register required -- `ldrsh r0,\[r0,r8\]'
+[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,#4\]!'
+[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],#4'
+[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1,-r2\]'
+[^:]*:110: Error: Thumb does not support this addressing mode -- `ldrsh r0,\[r1\],r2'
+[^:]*:111: Error: lo register required -- `str r8,\[r0\]'
+[^:]*:111: Error: lo register required -- `str r0,\[r8\]'
+[^:]*:111: Error: lo register required -- `str r0,\[r0,r8\]'
+[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,#4\]!'
+[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],#4'
+[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1,-r2\]'
+[^:]*:111: Error: Thumb does not support this addressing mode -- `str r0,\[r1\],r2'
+[^:]*:112: Error: lo register required -- `strb r8,\[r0\]'
+[^:]*:112: Error: lo register required -- `strb r0,\[r8\]'
+[^:]*:112: Error: lo register required -- `strb r0,\[r0,r8\]'
+[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,#4\]!'
+[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],#4'
+[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1,-r2\]'
+[^:]*:112: Error: Thumb does not support this addressing mode -- `strb r0,\[r1\],r2'
+[^:]*:113: Error: lo register required -- `strh r8,\[r0\]'
+[^:]*:113: Error: lo register required -- `strh r0,\[r8\]'
+[^:]*:113: Error: lo register required -- `strh r0,\[r0,r8\]'
+[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,#4\]!'
+[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],#4'
+[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1,-r2\]'
+[^:]*:113: Error: Thumb does not support this addressing mode -- `strh r0,\[r1\],r2'
+[^:]*:115: Error: Thumb does not support this addressing mode -- `ldr r0,\[r1,r2,lsl#1\]'
+[^:]*:116: Error: Thumb does not support this addressing mode -- `str r0,\[r1,r2,lsl#1\]'
+[^:]*:119: Error: lo register required -- `ldmia r8!,{r1,r2}'
+[^:]*:120: Error: lo register required -- `ldmia r7!,{r8}'
+[^:]*:121: Warning: this instruction will write back the base register
+[^:]*:122: Warning: this instruction will not write back the base register
+[^:]*:124: Error: lo register required -- `stmia r8!,{r1,r2}'
+[^:]*:125: Error: lo register required -- `stmia r7!,{r8}'
+[^:]*:126: Warning: this instruction will write back the base register
+[^:]*:127: Warning: value stored for r7 is UNPREDICTABLE
+[^:]*:129: Error: invalid register list to push/pop instruction -- `push {r8,r9}'
+[^:]*:130: Error: invalid register list to push/pop instruction -- `pop {r8,r9}'
+[^:]*:133: Error: immediate value out of range -- `bkpt #257'
+[^:]*:134: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie ai,#5'
+[^:]*:135: Error: Thumb does not support the 2-argument form of this instruction -- `cpsid ai,#5'
+[^:]*:138: Error: Thumb does not support conditional execution
diff --git a/gas/testsuite/gas/arm/t16-bad.s b/gas/testsuite/gas/arm/t16-bad.s
new file mode 100644
index 000000000000..a80a81ff0586
--- /dev/null
+++ b/gas/testsuite/gas/arm/t16-bad.s
@@ -0,0 +1,138 @@
+	@ Things you can't do with 16-bit Thumb instructions, but you can
+	@ do with the equivalent ARM instruction.  Does not include errors
+	@ caught by fixup processing (e.g. out-of-range immediates).
+
+	.text
+	.code 16
+	.thumb_func
+l:
+	@ Arithmetic instruction templates
+	.macro	ar2 opc
+	\opc	r8,r0
+	\opc	r0,r8
+	.endm
+	.macro	ar2sh opc
+	ar2	\opc
+	\opc	r0,#12
+	\opc	r0,r1,lsl #2
+	\opc	r0,r1,lsl r3
+	.endm
+	.macro	ar2r opc
+	ar2	\opc
+	\opc	r0,r1,ror #8
+	.endm
+	.macro 	ar3 opc
+	\opc	r1,r2,r3
+	\opc	r8,r0
+	\opc	r0,r8
+	.endm
+	.macro ar3sh opc
+	ar3	\opc
+	\opc	r0,#12
+	\opc	r0,r1,lsl #2
+	\opc	r0,r1,lsl r3
+	.endm
+
+	ar2sh	tst
+	ar2sh	cmn
+	ar2sh	mvn
+	ar2	neg
+	ar2	rev
+	ar2	rev16
+	ar2	revsh
+	ar2r	sxtb
+	ar2r	sxth
+	ar2r	uxtb
+	ar2r	uxth
+
+	ar3sh	adc
+	ar3sh	and
+	ar3sh	bic
+	ar3sh	eor
+	ar3sh	orr
+	ar3sh	sbc
+	ar3	mul
+
+	@ Shift instruction template
+	.macro	shift opc
+	\opc	r8,r0,#12  @ form 1
+	\opc	r0,r8,#12
+	ar2	\opc	   @ form 2
+	.endm
+	shift	asr
+	shift	lsl
+	shift	lsr
+	shift	ror
+	ror	r0,r1,#12
+
+	@ add/sub/mov/cmp are idiosyncratic
+	add	r0,r1,lsl #2
+	add	r0,r1,lsl r3
+	add	r8,r0,#1	@ form 1
+	add	r0,r8,#1
+	add	r8,#10		@ form 2
+	add	r8,r1,r2	@ form 3
+	add	r1,r8,r2
+	add	r1,r2,r8
+	add	r8,pc,#4	@ form 5
+	add	r8,sp,#4	@ form 6
+
+	ar3sh	sub
+	sub	r8,r0,#1	@ form 1
+	sub	r0,r8,#1
+	sub	r8,#10		@ form 2
+	sub	r8,r1,r2	@ form 3
+	sub	r1,r8,r2
+	sub	r1,r2,r8
+
+	cmp	r0,r1,lsl #2
+	cmp	r0,r1,lsl r3
+	cmp	r8,#255
+
+	mov	r0,r1,lsl #2
+	mov	r0,r1,lsl r3
+	mov	r8,#255
+
+	@ Load/store template
+	.macro	ldst opc
+	\opc	r8,[r0]
+	\opc	r0,[r8]
+	\opc	r0,[r0,r8]
+	\opc	r0,[r1,#4]!
+	\opc	r0,[r1],#4
+	\opc	r0,[r1,-r2]
+	\opc	r0,[r1],r2
+	.endm
+	ldst	ldr
+	ldst	ldrb
+	ldst	ldrh
+	ldst	ldrsb
+	ldst	ldrsh
+	ldst	str
+	ldst	strb
+	ldst	strh
+
+	ldr	r0,[r1,r2,lsl #1]
+	str	r0,[r1,r2,lsl #1]
+	
+	@ Load/store multiple
+	ldmia	r8!,{r1,r2}
+	ldmia	r7!,{r8}
+	ldmia	r7,{r1,r2}
+	ldmia	r7!,{r1,r7}
+
+	stmia	r8!,{r1,r2}
+	stmia	r7!,{r8}
+	stmia	r7,{r1,r2}
+	stmia	r7!,{r1,r7}
+
+	push	{r8,r9}
+	pop	{r8,r9}
+
+	@ Miscellaneous
+	bkpt	#257
+	cpsie	ai,#5
+	cpsid	ai,#5
+
+	@ Conditional suffixes
+	addeq	r0,r1,r2
diff --git a/gas/testsuite/gas/arm/tcompat.d b/gas/testsuite/gas/arm/tcompat.d
new file mode 100644
index 000000000000..47e9d89d9f94
--- /dev/null
+++ b/gas/testsuite/gas/arm/tcompat.d
@@ -0,0 +1,50 @@
+#name: ARM Thumb-compat pseudos
+#objdump: -dr --prefix-addresses --show-raw-insn
+#as:
+
+# Test the ARM pseudo instructions that exist for Thumb source compatibility
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+0+00 <[^>]*> 91a00000 ?	movls	r0, r0
+0+04 <[^>]*> e1a09000 ?	mov	r9, r0
+0+08 <[^>]*> e1a00009 ?	mov	r0, r9
+0+0c <[^>]*> e1a0c00e ?	mov	ip, lr
+0+10 <[^>]*> 91b09019 ?	movlss	r9, r9, lsl r0
+0+14 <[^>]*> 91a00910 ?	movls	r0, r0, lsl r9
+0+18 <[^>]*> e1b00880 ?	movs	r0, r0, lsl #17
+0+1c <[^>]*> e1a00889 ?	mov	r0, r9, lsl #17
+0+20 <[^>]*> 91b09039 ?	movlss	r9, r9, lsr r0
+0+24 <[^>]*> 91a00930 ?	movls	r0, r0, lsr r9
+0+28 <[^>]*> e1b008a0 ?	movs	r0, r0, lsr #17
+0+2c <[^>]*> e1a008a9 ?	mov	r0, r9, lsr #17
+0+30 <[^>]*> 91b09059 ?	movlss	r9, r9, asr r0
+0+34 <[^>]*> 91a00950 ?	movls	r0, r0, asr r9
+0+38 <[^>]*> e1b008c0 ?	movs	r0, r0, asr #17
+0+3c <[^>]*> e1a008c9 ?	mov	r0, r9, asr #17
+0+40 <[^>]*> 91b09079 ?	movlss	r9, r9, ror r0
+0+44 <[^>]*> 91a00970 ?	movls	r0, r0, ror r9
+0+48 <[^>]*> e1b008e0 ?	movs	r0, r0, ror #17
+0+4c <[^>]*> e1a008e9 ?	mov	r0, r9, ror #17
+0+50 <[^>]*> e2690000 ?	rsb	r0, r9, #0	; 0x0
+0+54 <[^>]*> e2709000 ?	rsbs	r9, r0, #0	; 0x0
+0+58 <[^>]*> 92600000 ?	rsbls	r0, r0, #0	; 0x0
+0+5c <[^>]*> 92799000 ?	rsblss	r9, r9, #0	; 0x0
+0+60 <[^>]*> e92d000e ?	stmdb	sp!, {r1, r2, r3}
+0+64 <[^>]*> 992d8154 ?	stmlsdb	sp!, {r2, r4, r6, r8, pc}
+0+68 <[^>]*> e8bd000e ?	ldmia	sp!, {r1, r2, r3}
+0+6c <[^>]*> 98bd8154 ?	ldmlsia	sp!, {r2, r4, r6, r8, pc}
+0+70 <[^>]*> e0000001 ?	and	r0, r0, r1
+0+74 <[^>]*> e0200001 ?	eor	r0, r0, r1
+0+78 <[^>]*> e0400001 ?	sub	r0, r0, r1
+0+7c <[^>]*> e0600001 ?	rsb	r0, r0, r1
+0+80 <[^>]*> e0800001 ?	add	r0, r0, r1
+0+84 <[^>]*> e0a00001 ?	adc	r0, r0, r1
+0+88 <[^>]*> e0c00001 ?	sbc	r0, r0, r1
+0+8c <[^>]*> e0e00001 ?	rsc	r0, r0, r1
+0+90 <[^>]*> e1800001 ?	orr	r0, r0, r1
+0+94 <[^>]*> e1c00001 ?	bic	r0, r0, r1
+0+98 <[^>]*> e0000091 ?	mul	r0, r1, r0
+0+9c <[^>]*> e1a00000 ?	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/tcompat.s b/gas/testsuite/gas/arm/tcompat.s
new file mode 100644
index 000000000000..c0042e8f127b
--- /dev/null
+++ b/gas/testsuite/gas/arm/tcompat.s
@@ -0,0 +1,45 @@
+	@ ARM instructions defined for source compatibility with Thumb.
+	.macro	shift op opls ops oplss
+	\oplss	r9,r0
+	\opls	r0,r0,r9
+	\ops	r0,#17
+	\op	r0,r9,#17
+	.endm
+	.text
+	.global l
+l:
+	cpyls	r0,r0
+	cpy	r9,r0
+	cpy	r0,r9
+	cpy	ip,lr
+
+	shift	lsl lslls lsls lsllss
+	shift	lsr lsrls lsrs lsrlss
+	shift	asr asrls asrs asrlss
+	shift	ror rorls rors rorlss
+
+	neg	r0,r9
+	negs	r9,r0
+	negls	r0,r0
+	neglss	r9,r9
+
+	push	{r1,r2,r3}
+	pushls	{r2,r4,r6,r8,pc}
+	pop	{r1,r2,r3}
+	popls	{r2,r4,r6,r8,pc}
+
+	@ Two-argument forms of ARM arithmetic instructions.
+	and	r0,r1
+	eor	r0,r1
+	sub	r0,r1
+	rsb	r0,r1
+
+	add	r0,r1
+	adc	r0,r1
+	sbc	r0,r1
+	rsc	r0,r1
+
+	orr	r0,r1
+	bic	r0,r1
+	mul	r0,r1
+	nop
diff --git a/gas/testsuite/gas/arm/tcompat2.d b/gas/testsuite/gas/arm/tcompat2.d
new file mode 100644
index 000000000000..ba39db1fad1b
--- /dev/null
+++ b/gas/testsuite/gas/arm/tcompat2.d
@@ -0,0 +1,26 @@
+#name: Thumb ARM-compat pseudos
+#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
+#as:
+
+# Test the Thumb pseudo instructions that exist for ARM source compatibility
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+0+00 <[^>]*> 4148 *	adcs	r0, r1
+0+02 <[^>]*> 4148 *	adcs	r0, r1
+0+04 <[^>]*> 4008 *	ands	r0, r1
+0+06 <[^>]*> 4008 *	ands	r0, r1
+0+08 <[^>]*> 4048 *	eors	r0, r1
+0+0a <[^>]*> 4048 *	eors	r0, r1
+0+0c <[^>]*> 4348 *	muls	r0, r1
+0+0e <[^>]*> 4348 *	muls	r0, r1
+0+10 <[^>]*> 4308 *	orrs	r0, r1
+0+12 <[^>]*> 4308 *	orrs	r0, r1
+0+14 <[^>]*> 4388 *	bics	r0, r1
+0+16 <[^>]*> 4188 *	sbcs	r0, r1
+0+18 <[^>]*> 46c0 *	nop			\(mov r8, r8\)
+0+1a <[^>]*> 46c0 *	nop			\(mov r8, r8\)
+0+1c <[^>]*> 46c0 *	nop			\(mov r8, r8\)
+0+1e <[^>]*> 46c0 *	nop			\(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/tcompat2.s b/gas/testsuite/gas/arm/tcompat2.s
new file mode 100644
index 000000000000..b034ce2f6725
--- /dev/null
+++ b/gas/testsuite/gas/arm/tcompat2.s
@@ -0,0 +1,32 @@
+	@ Three-argument forms of Thumb arithmetic instructions.
+	@ Commutative instructions allow either the second or third
+	@ operand to equal the first.
+
+	.text
+	.global m
+	.thumb_func
+m:
+	adc	r0,r0,r1
+	adc	r0,r1,r0
+
+	and	r0,r0,r1
+	and	r0,r1,r0
+
+	eor	r0,r0,r1
+	eor	r0,r1,r0
+
+	mul	r0,r0,r1
+	mul	r0,r1,r0
+
+	orr	r0,r0,r1
+	orr	r0,r1,r0
+
+	bic	r0,r0,r1
+
+	sbc	r0,r0,r1
+
+	@ section padding for a.out's sake
+	nop
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
new file mode 100644
index 000000000000..d3f815a2986a
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -0,0 +1,164 @@
+# name: Thumb instructions
+# as: -mcpu=arm7t
+# objdump: -dr --prefix-addresses --show-raw-insn
+# The arm-aout and arm-pe ports do not support Thumb branch relocations.
+# not-target: *-*-*aout* *-*-pe
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> 00ca      	lsls	r2, r1, #3
+0+002 <[^>]+> 0fe3      	lsrs	r3, r4, #31
+0+004 <[^>]+> 1147      	asrs	r7, r0, #5
+0+006 <[^>]+> 0011      	lsls	r1, r2, #0
+0+008 <[^>]+> 0023      	lsls	r3, r4, #0
+0+00a <[^>]+> 002c      	lsls	r4, r5, #0
+0+00c <[^>]+> 083e      	lsrs	r6, r7, #32
+0+00e <[^>]+> 1008      	asrs	r0, r1, #32
+0+010 <[^>]+> 18d1      	adds	r1, r2, r3
+0+012 <[^>]+> 1ca2      	adds	r2, r4, #2
+0+014 <[^>]+> 1beb      	subs	r3, r5, r7
+0+016 <[^>]+> 1fe2      	subs	r2, r4, #7
+0+018 <[^>]+> 24ff      	movs	r4, #255
+0+01a <[^>]+> 2bfa      	cmp	r3, #250
+0+01c <[^>]+> 367b      	adds	r6, #123
+0+01e <[^>]+> 3d80      	subs	r5, #128
+0+020 <[^>]+> 402b      	ands	r3, r5
+0+022 <[^>]+> 4074      	eors	r4, r6
+0+024 <[^>]+> 4081      	lsls	r1, r0
+0+026 <[^>]+> 40da      	lsrs	r2, r3
+0+028 <[^>]+> 4134      	asrs	r4, r6
+0+02a <[^>]+> 417d      	adcs	r5, r7
+0+02c <[^>]+> 41a0      	sbcs	r0, r4
+0+02e <[^>]+> 41e1      	rors	r1, r4
+0+030 <[^>]+> 422a      	tst	r2, r5
+0+032 <[^>]+> 4249      	negs	r1, r1
+0+034 <[^>]+> 429a      	cmp	r2, r3
+0+036 <[^>]+> 42e1      	cmn	r1, r4
+0+038 <[^>]+> 4318      	orrs	r0, r3
+0+03a <[^>]+> 436c      	muls	r4, r5
+0+03c <[^>]+> 43bd      	bics	r5, r7
+0+03e <[^>]+> 43ed      	mvns	r5, r5
+0+040 <[^>]+> 4469      	add	r1, sp
+0+042 <[^>]+> 4494      	add	ip, r2
+0+044 <[^>]+> 44c9      	add	r9, r9
+0+046 <[^>]+> 4571      	cmp	r1, lr
+0+048 <[^>]+> 4580      	cmp	r8, r0
+0+04a <[^>]+> 45f4      	cmp	ip, lr
+0+04c <[^>]+> 4648      	mov	r0, r9
+0+04e <[^>]+> 46a1      	mov	r9, r4
+0+050 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+052 <[^>]+> 4738      	bx	r7
+0+054 <[^>]+> 4740      	bx	r8
+0+056 <[^>]+> 0000      	lsls	r0, r0, #0
+0+058 <[^>]+> 4778      	bx	pc
+0+05a <[^>]+> 4b20      	ldr	r3, \[pc, #128\]	\(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02      	ldr	r4, \[pc, #8\]	\(0+068 <[^>]+>\)
+0+05e <[^>]+> 5088      	str	r0, \[r1, r2\]
+0+060 <[^>]+> 5511      	strb	r1, \[r2, r4\]
+0+062 <[^>]+> 59f5      	ldr	r5, \[r6, r7\]
+0+064 <[^>]+> 5d62      	ldrb	r2, \[r4, r5\]
+	\.\.\.
+0+068 <[^>]+> 52d1      	strh	r1, \[r2, r3\]
+0+06a <[^>]+> 5a23      	ldrh	r3, \[r4, r0\]
+0+06c <[^>]+> 57f1      	ldrsb	r1, \[r6, r7\]
+0+06e <[^>]+> 5f42      	ldrsh	r2, \[r0, r5\]
+0+070 <[^>]+> 67db      	str	r3, \[r3, #124\]
+0+072 <[^>]+> 6fe1      	ldr	r1, \[r4, #124\]
+0+074 <[^>]+> 682d      	ldr	r5, \[r5, #0\]
+0+076 <[^>]+> 77e9      	strb	r1, \[r5, #31\]
+0+078 <[^>]+> 7161      	strb	r1, \[r4, #5\]
+0+07a <[^>]+> 7032      	strb	r2, \[r6, #0\]
+0+07c <[^>]+> 87ec      	strh	r4, \[r5, #62\]
+0+07e <[^>]+> 8885      	ldrh	r5, \[r0, #4\]
+0+080 <[^>]+> 8813      	ldrh	r3, \[r2, #0\]
+0+082 <[^>]+> 93ff      	str	r3, \[sp, #1020\]
+0+084 <[^>]+> 990b      	ldr	r1, \[sp, #44\]
+0+086 <[^>]+> 9a00      	ldr	r2, \[sp, #0\]
+0+088 <[^>]+> a7ff      	add	r7, pc, #1020	\(adr r7,0+488 <[^>]+>\)
+0+08a <[^>]+> ac80      	add	r4, sp, #512
+0+08c <[^>]+> b043      	add	sp, #268
+0+08e <[^>]+> b09a      	sub	sp, #104
+0+090 <[^>]+> b0c3      	sub	sp, #268
+0+092 <[^>]+> b01b      	add	sp, #108
+0+094 <[^>]+> b417      	push	{r0, r1, r2, r4}
+0+096 <[^>]+> b5f9      	push	{r0, r3, r4, r5, r6, r7, lr}
+0+098 <[^>]+> bc98      	pop	{r3, r4, r7}
+0+09a <[^>]+> bdff      	pop	{r0, r1, r2, r3, r4, r5, r6, r7, pc}
+0+09c <[^>]+> c3f3      	stmia	r3!, {r0, r1, r4, r5, r6, r7}
+0+09e <[^>]+> c8fe      	ldmia	r0!, {r1, r2, r3, r4, r5, r6, r7}
+0+0a0 <[^>]+> d0e2      	beq.n	0+068 <[^>]+>
+0+0a2 <[^>]+> d1e1      	bne.n	0+068 <[^>]+>
+0+0a4 <[^>]+> d2e0      	bcs.n	0+068 <[^>]+>
+0+0a6 <[^>]+> d3df      	bcc.n	0+068 <[^>]+>
+0+0a8 <[^>]+> d4de      	bmi.n	0+068 <[^>]+>
+0+0aa <[^>]+> d5dd      	bpl.n	0+068 <[^>]+>
+0+0ac <[^>]+> d6dc      	bvs.n	0+068 <[^>]+>
+0+0ae <[^>]+> d7db      	bvc.n	0+068 <[^>]+>
+0+0b0 <[^>]+> d8da      	bhi.n	0+068 <[^>]+>
+0+0b2 <[^>]+> d9d9      	bls.n	0+068 <[^>]+>
+0+0b4 <[^>]+> dad8      	bge.n	0+068 <[^>]+>
+0+0b6 <[^>]+> dcd7      	bgt.n	0+068 <[^>]+>
+0+0b8 <[^>]+> dbd6      	blt.n	0+068 <[^>]+>
+0+0ba <[^>]+> dcd5      	bgt.n	0+068 <[^>]+>
+0+0bc <[^>]+> ddd4      	ble.n	0+068 <[^>]+>
+0+0be <[^>]+> d8d3      	bhi.n	0+068 <[^>]+>
+0+0c0 <[^>]+> d3d2      	bcc.n	0+068 <[^>]+>
+0+0c2 <[^>]+> d3d1      	bcc.n	0+068 <[^>]+>
+0+0c4 <[^>]+> e7d0      	b.n	0+068 <[^>]+>
+0+0c6 <[^>]+> 00ac      	lsls	r4, r5, #2
+0+0c8 <[^>]+> 1c9a      	adds	r2, r3, #2
+0+0ca <[^>]+> b07f      	add	sp, #508
+0+0cc <[^>]+> b0ff      	sub	sp, #508
+0+0ce <[^>]+> a8ff      	add	r0, sp, #1020
+0+0d0 <[^>]+> a0ff      	add	r0, pc, #1020	\(adr r0,0+4d0 <[^>]+>\)
+0+0d2 <[^>]+> b01a      	add	sp, #104
+0+0d4 <[^>]+> b09a      	sub	sp, #104
+0+0d6 <[^>]+> a81a      	add	r0, sp, #104
+0+0d8 <[^>]+> a01a      	add	r0, pc, #104	\(adr r0,0+144 <[^>]+>\)
+0+0da <[^>]+> 3168      	adds	r1, #104
+0+0dc <[^>]+> 2668      	movs	r6, #104
+0+0de <[^>]+> 2f68      	cmp	r7, #104
+0+0e0 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+0e2 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+0e4 <[^>]+> eafffffe 	b	0+0e4 <[^>]+>
+0+0e8 <[^>]+> ea000011 	b	0+134 <[^>]+>
+0+0ec <[^>]+> ebfffffc 	bl	0+0e4 <[^>]+>
+0+0f0 <[^>]+> eb00000f 	bl	0+134 <[^>]+>
+0+0f4 <[^>]+> e12fff10 	bx	r0
+0+0f8 <[^>]+> ef123456 	(swi|svc)	0x00123456
+0+0fc <[^>]+> a004      	add	r0, pc, #16	\(adr r0,0+110 <[^>]+>\)
+0+0fe <[^>]+> e77f      	b.n	0+000 <[^>]+>
+0+100 <[^>]+> e018      	b.n	0+134 <[^>]+>
+0+102 <[^>]+> f7ff ff7d 	bl	0+000 <[^>]+>
+0+106 <[^>]+> f000 f815 	bl	0+134 <[^>]+>
+0+10a <[^>]+> 4700      	bx	r0
+0+10c <[^>]+> dfff      	(swi|svc)	255
+	\.\.\.
+0+110 <[^>]+> d010      	beq.n	0+134 <[^>]+>
+0+112 <[^>]+> d10f      	bne.n	0+134 <[^>]+>
+0+114 <[^>]+> d20e      	bcs.n	0+134 <[^>]+>
+0+116 <[^>]+> d30d      	bcc.n	0+134 <[^>]+>
+0+118 <[^>]+> d40c      	bmi.n	0+134 <[^>]+>
+0+11a <[^>]+> d50b      	bpl.n	0+134 <[^>]+>
+0+11c <[^>]+> d60a      	bvs.n	0+134 <[^>]+>
+0+11e <[^>]+> d709      	bvc.n	0+134 <[^>]+>
+0+120 <[^>]+> d808      	bhi.n	0+134 <[^>]+>
+0+122 <[^>]+> d907      	bls.n	0+134 <[^>]+>
+0+124 <[^>]+> da06      	bge.n	0+134 <[^>]+>
+0+126 <[^>]+> dc05      	bgt.n	0+134 <[^>]+>
+0+128 <[^>]+> db04      	blt.n	0+134 <[^>]+>
+0+12a <[^>]+> dc03      	bgt.n	0+134 <[^>]+>
+0+12c <[^>]+> dd02      	ble.n	0+134 <[^>]+>
+0+12e <[^>]+> d801      	bhi.n	0+134 <[^>]+>
+0+130 <[^>]+> d300      	bcc.n	0+134 <[^>]+>
+0+132 <[^>]+> d3ff      	bcc.n	0+134 <[^>]+>
+0+134 <[^>]+> f000 fc00 	bl	0+938 <[^>]+>
+	\.\.\.
+0+938 <[^>]+> f7ff fbfc 	bl	0+134 <[^>]+>
+0+93c <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+948 <[^>]+>\)
+0+944 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+946 <[^>]+> 46c0      	nop			\(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb.s b/gas/testsuite/gas/arm/thumb.s
index 422b088de856..d1e43394efa2 100644
--- a/gas/testsuite/gas/arm/thumb.s
+++ b/gas/testsuite/gas/arm/thumb.s
@@ -145,9 +145,9 @@ near:
 	.arm
 .localbar:
 	b	.localbar
-	b	.wombat
+	b	.back
 	bl	.localbar
-	bl	.wombat
+	bl	.back
 
 	bx	r0
 	swi	0x123456
@@ -159,36 +159,44 @@ morethumb:
 	adr	r0, forwardonly
 
 	b	.foo
-	b	.wombat
+	b	.back
 	bl	.foo
-	bl	.wombat
+	bl	.back
 
 	bx	r0
 
 	swi	0xff
 	.align	0
 forwardonly:
-	beq	.wombat
-	bne	.wombat
-	bcs	.wombat
-	bcc	.wombat
-	bmi	.wombat
-	bpl	.wombat
-	bvs	.wombat
-	bvc	.wombat
-	bhi	.wombat
-	bls	.wombat
-	bge	.wombat
-	bgt	.wombat
-	blt	.wombat
-	bgt	.wombat
-	ble	.wombat
-	bhi	.wombat
-	blo	.wombat
-	bul	.wombat
+	beq	.back
+	bne	.back
+	bcs	.back
+	bcc	.back
+	bmi	.back
+	bpl	.back
+	bvs	.back
+	bvc	.back
+	bhi	.back
+	bls	.back
+	bge	.back
+	bgt	.back
+	blt	.back
+	bgt	.back
+	ble	.back
+	bhi	.back
+	blo	.back
+	bul	.back
 
 .back:
 	bl	.local
 	.space	(1 << 11)	@ leave space to force long offsets
 .local:
 	bl	.back
+
+	ldr	r0, .target
+	ldr	r0, .target
+	ldr	r0, [pc, #4]
+	ldr	r0, [pc, #4]
+.target:
+	nop	@ pad for a.out
+	nop
diff --git a/gas/testsuite/gas/arm/thumb2_bcond.d b/gas/testsuite/gas/arm/thumb2_bcond.d
new file mode 100644
index 000000000000..8ab75320e1a3
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_bcond.d
@@ -0,0 +1,26 @@
+# as:
+# objdump: -dr --prefix-addresses --show-raw-insn
+# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> bf18      	it	ne
+0+002 <[^>]+> e7fd      	b(|ne).n	0+0 <[^>]+>
+0+004 <[^>]+> bf38      	it	cc
+0+006 <[^>]+> f7ff bffb 	b(|cc).w	0+0 <[^>]+>
+0+00a <[^>]+> bf28      	it	cs
+0+00c <[^>]+> f7ff fff8 	bl(|cs)	0+0 <[^>]+>
+0+010 <[^>]+> bfb8      	it	lt
+0+012 <[^>]+> 47a8      	blx(|lr)	r5
+0+014 <[^>]+> bf08      	it	eq
+0+016 <[^>]+> 4740      	bx(|eq)	r8
+0+018 <[^>]+> bfc8      	it	gt
+0+01a <[^>]+> e8d4 f001 	tbb(|gt)	\[r4, r1\]
+0+01e <[^>]+> bfb8      	it	lt
+0+020 <[^>]+> df00      	svc(|lt)	0
+0+022 <[^>]+> bfdc      	itt	le
+0+024 <[^>]+> be00      	bkpt	0x0000
+0+026 <[^>]+> bf00      	nop
+0+028 <[^>]+> bf00      	nop
+0+02a <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb2_bcond.s b/gas/testsuite/gas/arm/thumb2_bcond.s
new file mode 100644
index 000000000000..4a066f2438ae
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_bcond.s
@@ -0,0 +1,25 @@
+	.text
+	.arch armv7
+	.thumb
+	.syntax unified
+	.thumb_func
+thumb2_bcond:
+	it ne
+	bne thumb2_bcond
+	it cc
+	bcc.w thumb2_bcond
+	it cs
+	blcs thumb2_bcond
+	it lt
+	blxlt r5
+	it eq
+	bxeq r8
+	it gt
+	tbbgt [r4, r1]
+	it lt
+	svclt 0
+	itt le
+	bkpt #0
+	nople
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/thumb2_invert.d b/gas/testsuite/gas/arm/thumb2_invert.d
new file mode 100644
index 000000000000..3880e5bb5fc6
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_invert.d
@@ -0,0 +1,16 @@
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> f517 0f80 	cmn.w	r7, #4194304	; 0x400000
+0+004 <[^>]+> f5b8 0f80 	cmp.w	r8, #4194304	; 0x400000
+0+008 <[^>]+> f5a4 0980 	sub.w	r9, r4, #4194304	; 0x400000
+0+00c <[^>]+> f506 0380 	add.w	r3, r6, #4194304	; 0x400000
+0+010 <[^>]+> f160 4500 	sbc.w	r5, r0, #2147483648	; 0x80000000
+0+014 <[^>]+> f147 4400 	adc.w	r4, r7, #2147483648	; 0x80000000
+0+018 <[^>]+> f022 4600 	bic.w	r6, r2, #2147483648	; 0x80000000
+0+01c <[^>]+> f002 4800 	and.w	r8, r2, #2147483648	; 0x80000000
+0+020 <[^>]+> f06f 4300 	mvn.w	r3, #2147483648	; 0x80000000
+0+024 <[^>]+> f04f 4100 	mov.w	r1, #2147483648	; 0x80000000
diff --git a/gas/testsuite/gas/arm/thumb2_invert.s b/gas/testsuite/gas/arm/thumb2_invert.s
new file mode 100644
index 000000000000..38ebcdda4cbb
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_invert.s
@@ -0,0 +1,14 @@
+	.text
+	.thumb
+	.syntax unified
+thumb2_invert:
+	cmp	r7, #0xffc00000
+	cmn	r8, #0xffc00000
+	add	r9, r4, #0xffc00000
+	sub	r3, r6, #0xffc00000
+	adc	r5, r0, #0x7fffffff
+	sbc	r4, r7, #0x7fffffff
+	and	r6, r2, #0x7fffffff
+	bic	r8, r2, #0x7fffffff
+	mov	r3, 0x7fffffff
+	mvn	r1, 0x7fffffff
diff --git a/gas/testsuite/gas/arm/thumb2_it.d b/gas/testsuite/gas/arm/thumb2_it.d
new file mode 100644
index 000000000000..30a390bbb0a7
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it.d
@@ -0,0 +1,62 @@
+# name: Mixed 16 and 32-bit Thumb conditional instructions
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+# Many of these patterns use "(eq|s)". These should be changed to just "eq"
+# once the disassembler is fixed. Likewise for "(eq)?"
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> bf05      	ittet	eq
+0+002 <[^>]+> 1880      	add(eq|s)	r0, r0, r2
+0+004 <[^>]+> 4440      	add(eq)?	r0, r8
+0+006 <[^>]+> 1888      	add(ne|s)	r0, r1, r2
+0+008 <[^>]+> eb11 0002 	adds(eq)?.w	r0, r1, r2
+0+00c <[^>]+> 4410      	add	r0, r2
+0+00e <[^>]+> 4440      	add	r0, r8
+0+010 <[^>]+> 1880      	adds	r0, r0, r2
+0+012 <[^>]+> eb10 0008 	adds.w	r0, r0, r8
+0+016 <[^>]+> 1888      	adds	r0, r1, r2
+0+018 <[^>]+> bf0a      	itet	eq
+0+01a <[^>]+> 4310      	orr(eq|s)	r0, r2
+0+01c <[^>]+> ea40 0008 	orr(ne)?.w	r0, r0, r8
+0+020 <[^>]+> ea50 0002 	orrs(eq)?.w	r0, r0, r2
+0+024 <[^>]+> ea40 0002 	orr.w	r0, r0, r2
+0+028 <[^>]+> ea40 0008 	orr.w	r0, r0, r8
+0+02c <[^>]+> 4310      	orrs	r0, r2
+0+02e <[^>]+> bf01      	itttt	eq
+0+030 <[^>]+> 4090      	lsl(eq|s)	r0, r2
+0+032 <[^>]+> fa00 f008 	lsl(eq)?.w	r0, r0, r8
+0+036 <[^>]+> fa01 f002 	lsl(eq)?.w	r0, r1, r2
+0+03a <[^>]+> fa10 f002 	lsls(eq)?.w	r0, r0, r2
+0+03e <[^>]+> bf02      	ittt	eq
+0+040 <[^>]+> 0048      	lsl(eq|s)	r0, r1, #1
+0+042 <[^>]+> ea4f 0048 	mov(eq)?.w	r0, r8, lsl #1
+0+046 <[^>]+> ea5f 0040 	movs(eq)?.w	r0, r0, lsl #1
+0+04a <[^>]+> fa00 f002 	lsl.w	r0, r0, r2
+0+04e <[^>]+> 4090      	lsls	r0, r2
+0+050 <[^>]+> ea4f 0041 	mov.w	r0, r1, lsl #1
+0+054 <[^>]+> 0048      	lsls	r0, r1, #1
+0+056 <[^>]+> bf01      	itttt	eq
+0+058 <[^>]+> 4288      	cmp(eq)?	r0, r1
+0+05a <[^>]+> 4540      	cmp(eq)?	r0, r8
+0+05c <[^>]+> 4608      	mov(eq)?	r0, r1
+0+05e <[^>]+> ea5f 0001 	movs(eq)?.w	r0, r1
+0+062 <[^>]+> bf08      	it	eq
+0+064 <[^>]+> 4640      	mov(eq)?	r0, r8
+0+066 <[^>]+> 4608      	mov(eq)?	r0, r1
+0+068 <[^>]+> 1c08      	adds	r0, r1, #0
+0+06a <[^>]+> ea5f 0008 	movs.w	r0, r8
+0+06e <[^>]+> bf01      	itttt	eq
+0+070 <[^>]+> 43c8      	mvn(eq|s)	r0, r1
+0+072 <[^>]+> ea6f 0008 	mvn(eq)?.w	r0, r8
+0+076 <[^>]+> ea7f 0001 	mvns(eq)?.w	r0, r1
+0+07a <[^>]+> 42c8      	cmn(eq)?	r0, r1
+0+07c <[^>]+> ea6f 0001 	mvn.w	r0, r1
+0+080 <[^>]+> 43c8      	mvns	r0, r1
+0+082 <[^>]+> bf02      	ittt	eq
+0+084 <[^>]+> 4248      	neg(eq|s)	r0, r1
+0+086 <[^>]+> f1c8 0000 	rsb(eq)?	r0, r8, #0	; 0x0
+0+08a <[^>]+> f1d1 0000 	rsbs(eq)?	r0, r1, #0	; 0x0
+0+08e <[^>]+> f1c1 0000 	rsb	r0, r1, #0	; 0x0
+0+092 <[^>]+> 4248      	negs	r0, r1
diff --git a/gas/testsuite/gas/arm/thumb2_it.s b/gas/testsuite/gas/arm/thumb2_it.s
new file mode 100644
index 000000000000..c12abb6242f6
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it.s
@@ -0,0 +1,64 @@
+	.text
+	.thumb
+	.syntax unified
+	.thumb_func
+foo:
+	ittet eq
+	addeq r0, r0, r2
+	addeq r0, r0, r8
+	addne r0, r1, r2
+	addseq r0, r1, r2
+	add r0, r0, r2
+	add r0, r0, r8
+	adds r0, r0, r2
+	adds r0, r0, r8
+	adds r0, r1, r2
+
+	itet eq
+	orreq r0, r0, r2
+	orrne r0, r0, r8
+	orrseq r0, r0, r2
+	orr r0, r0, r2
+	orr r0, r0, r8
+	orrs r0, r0, r2
+
+	itttt eq
+	lsleq r0, r0, r2
+	lsleq r0, r0, r8
+	lsleq r0, r1, r2
+	lslseq r0, r0, r2
+	ittt eq
+	lsleq r0, r1, #1
+	lsleq r0, r8, #1
+	lslseq r0, r0, #1
+	lsl r0, r0, r2
+	lsls r0, r0, r2
+	lsl r0, r1, #1
+	lsls r0, r1, #1
+
+	itttt eq
+	cmpeq r0, r1
+	cmpeq r0, r8
+	moveq r0, r1
+	movseq r0, r1
+	it eq
+	moveq r0, r8
+	mov r0, r1
+	movs r0, r1
+	movs r0, r8
+
+	itttt eq
+	mvneq r0, r1
+	mvneq r0, r8
+	mvnseq r0, r1
+	cmneq r0, r1
+	mvn r0, r1
+	mvns r0, r1
+
+	ittt eq
+	negeq r0, r1
+	negeq r0, r8
+	negseq r0, r1
+	neg r0, r1
+	negs r0, r1
+
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.d b/gas/testsuite/gas/arm/thumb2_it_bad.d
new file mode 100644
index 000000000000..f905c9f5e73b
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.d
@@ -0,0 +1,4 @@
+#name: Invalid IT instructions
+#as:
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: thumb2_it_bad.l
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.l b/gas/testsuite/gas/arm/thumb2_it_bad.l
new file mode 100644
index 000000000000..e2e96cddb43a
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.l
@@ -0,0 +1,12 @@
+[^:]*: Assembler messages:
+[^:]*:8: Error: branch must be last instruction in IT block -- `beq foo'
+[^:]*:9: Error: branch must be last instruction in IT block -- `bleq foo'
+[^:]*:10: Error: branch must be last instruction in IT block -- `blxeq r0'
+[^:]*:11: Error: instruction not allowed in IT block -- `cbzeq r0,foo'
+[^:]*:13: Error: branch must be last instruction in IT block -- `bxeq r0'
+[^:]*:14: Error: branch must be last instruction in IT block -- `tbbeq \[r0,r1\]'
+[^:]*:15: Error: instruction not allowed in IT block -- `cpsieeq f'
+[^:]*:17: Error: instruction not allowed in IT block -- `cpseq #0x10'
+[^:]*:19: Error: instruction is always unconditional -- `bkpteq 0'
+[^:]*:20: Error: instruction not allowed in IT block -- `setendeq le'
+[^:]*:22: Error: instruction not allowed in IT block -- `iteq eq'
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad.s b/gas/testsuite/gas/arm/thumb2_it_bad.s
new file mode 100644
index 000000000000..6add4fb51710
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad.s
@@ -0,0 +1,24 @@
+	.text
+	.syntax unified
+	.arch armv7a
+	.thumb
+	.thumb_func
+thumb2_it_bad:
+	itttt	eq
+	beq	foo
+	bleq	foo
+	blxeq	r0
+	cbzeq	r0, foo
+	ittt	eq
+	bxeq	r0
+	tbbeq	[r0, r1]
+	cpsieeq	f
+	it	eq
+	cpseq	#0x10
+	itt	eq
+	bkpteq	0
+	setendeq	le
+	it	eq
+	iteq	eq
+	nop
+foo:
diff --git a/gas/testsuite/gas/arm/thumb2_pool.d b/gas/testsuite/gas/arm/thumb2_pool.d
new file mode 100644
index 000000000000..7bf0c605d5fd
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_pool.d
@@ -0,0 +1,15 @@
+# as: -march=armv6t2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> 4e04      	ldr	r6, \[pc, #16\]	\(00+14 <[^>]+>\)
+0+002 <[^>]+> 4904      	ldr	r1, \[pc, #16\]	\(00+14 <[^>]+>\)
+0+004 <[^>]+> f8df 600c 	ldr\.w	r6, \[pc, #12\]	; 00+14 <[^>]+>
+0+008 <[^>]+> f8df 9008 	ldr\.w	r9, \[pc, #8\]	; 00+14 <[^>]+>
+0+00c <[^>]+> bf00      	nop
+0+00e <[^>]+> f8df 5004 	ldr\.w	r5, \[pc, #4\]	; 00+14 <[^>]+>
+0+012 <[^>]+> 4900      	ldr	r1, \[pc, #0\]	\(00+14 <[^>]+>\)
+0+014 <[^>]+> (5678|1234) .*
+0+016 <[^>]+> (1234|5678) .*
diff --git a/gas/testsuite/gas/arm/thumb2_pool.s b/gas/testsuite/gas/arm/thumb2_pool.s
new file mode 100644
index 000000000000..844e77ec49f9
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_pool.s
@@ -0,0 +1,13 @@
+	.text
+	.thumb
+	.syntax unified
+	.thumb_func
+thumb2_ldr:
+	ldr	r6, =0x12345678
+	ldr.n	r1, =0x12345678
+	ldr.w	r6, =0x12345678
+	ldr	r9, =0x12345678
+	nop
+	ldr.w	r5, =0x12345678
+	ldr	r1, =0x12345678
+	.pool
diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d
new file mode 100644
index 000000000000..48cd1f21f806
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_relax.d
@@ -0,0 +1,155 @@
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> 7829      	ldrb	r1, \[r5, #0\]
+0+002 <[^>]+> f895 1023 	ldrb.w	r1, \[r5, #35\]
+0+006 <[^>]+> 7fe9      	ldrb	r1, \[r5, #31\]
+0+008 <[^>]+> f895 101f 	ldrb.w	r1, \[r5, #31\]
+0+00c <[^>]+> f815 1c1f 	ldrb.w	r1, \[r5, #-31\]
+0+010 <[^>]+> f815 1b1f 	ldrb.w	r1, \[r5\], #31
+0+014 <[^>]+> f815 1b1f 	ldrb.w	r1, \[r5\], #31
+0+018 <[^>]+> f815 1f1f 	ldrb.w	r1, \[r5, #31\]!
+0+01c <[^>]+> f815 1d1f 	ldrb.w	r1, \[r5, #-31\]!
+0+020 <[^>]+> 5d29      	ldrb	r1, \[r5, r4\]
+0+022 <[^>]+> f819 100c 	ldrb.w	r1, \[r9, ip\]
+0+026 <[^>]+> f89f 1014 	ldrb.w	r1, \[pc, #20\]	; 0+03c <[^>]+>
+0+02a <[^>]+> f89f 1010 	ldrb.w	r1, \[pc, #16\]	; 0+03c <[^>]+>
+0+02e <[^>]+> f89f 800c 	ldrb.w	r8, \[pc, #12\]	; 0+03c <[^>]+>
+0+032 <[^>]+> f89f 100a 	ldrb.w	r1, \[pc, #10\]	; 0+03e <[^>]+>
+0+036 <[^>]+> f81f 1038 	ldrb.w	r1, \[pc, #-56\]	; 0+000 <[^>]+>
+0+03a <[^>]+> 0000      	lsls	r0, r0, #0
+0+03c <[^>]+> bf00      	nop
+0+03e <[^>]+> f995 1000 	ldrsb.w	r1, \[r5\]
+0+042 <[^>]+> f995 1023 	ldrsb.w	r1, \[r5, #35\]
+0+046 <[^>]+> f995 101f 	ldrsb.w	r1, \[r5, #31\]
+0+04a <[^>]+> f995 101f 	ldrsb.w	r1, \[r5, #31\]
+0+04e <[^>]+> f915 1c1f 	ldrsb.w	r1, \[r5, #-31\]
+0+052 <[^>]+> f915 1b1f 	ldrsb.w	r1, \[r5\], #31
+0+056 <[^>]+> f915 1b1f 	ldrsb.w	r1, \[r5\], #31
+0+05a <[^>]+> f915 1f1f 	ldrsb.w	r1, \[r5, #31\]!
+0+05e <[^>]+> f915 1d1f 	ldrsb.w	r1, \[r5, #-31\]!
+0+062 <[^>]+> 5729      	ldrsb	r1, \[r5, r4\]
+0+064 <[^>]+> f919 100c 	ldrsb.w	r1, \[r9, ip\]
+0+068 <[^>]+> f99f 1010 	ldrsb.w	r1, \[pc, #16\]	; 0+07c <[^>]+>
+0+06c <[^>]+> f99f 100c 	ldrsb.w	r1, \[pc, #12\]	; 0+07c <[^>]+>
+0+070 <[^>]+> f99f 8008 	ldrsb.w	r8, \[pc, #8\]	; 0+07c <[^>]+>
+0+074 <[^>]+> f99f 1006 	ldrsb.w	r1, \[pc, #6\]	; 0+07e <[^>]+>
+0+078 <[^>]+> f91f 103e 	ldrsb.w	r1, \[pc, #-62\]	; 0+03e <[^>]+>
+0+07c <[^>]+> bf00      	nop
+0+07e <[^>]+> 8829      	ldrh	r1, \[r5, #0\]
+0+080 <[^>]+> f8b5 1042 	ldrh.w	r1, \[r5, #66\]
+0+084 <[^>]+> 8fe9      	ldrh	r1, \[r5, #62\]
+0+086 <[^>]+> f8b5 103e 	ldrh.w	r1, \[r5, #62\]
+0+08a <[^>]+> f835 1c3e 	ldrh.w	r1, \[r5, #-62\]
+0+08e <[^>]+> f835 1b3e 	ldrh.w	r1, \[r5\], #62
+0+092 <[^>]+> f835 1b3e 	ldrh.w	r1, \[r5\], #62
+0+096 <[^>]+> f835 1f3e 	ldrh.w	r1, \[r5, #62\]!
+0+09a <[^>]+> f835 1d3e 	ldrh.w	r1, \[r5, #-62\]!
+0+09e <[^>]+> 5b29      	ldrh	r1, \[r5, r4\]
+0+0a0 <[^>]+> f839 100c 	ldrh.w	r1, \[r9, ip\]
+0+0a4 <[^>]+> f8bf 1010 	ldrh.w	r1, \[pc, #16\]	; 0+0b8 <[^>]+>
+0+0a8 <[^>]+> f8bf 100c 	ldrh.w	r1, \[pc, #12\]	; 0+0b8 <[^>]+>
+0+0ac <[^>]+> f8bf 8008 	ldrh.w	r8, \[pc, #8\]	; 0+0b8 <[^>]+>
+0+0b0 <[^>]+> f8bf 1006 	ldrh.w	r1, \[pc, #6\]	; 0+0ba <[^>]+>
+0+0b4 <[^>]+> f83f 103a 	ldrh.w	r1, \[pc, #-58\]	; 0+07e <[^>]+>
+0+0b8 <[^>]+> bf00      	nop
+0+0ba <[^>]+> f9b5 1000 	ldrsh.w	r1, \[r5\]
+0+0be <[^>]+> f9b5 1042 	ldrsh.w	r1, \[r5, #66\]
+0+0c2 <[^>]+> f9b5 103e 	ldrsh.w	r1, \[r5, #62\]
+0+0c6 <[^>]+> f9b5 103e 	ldrsh.w	r1, \[r5, #62\]
+0+0ca <[^>]+> f935 1c3e 	ldrsh.w	r1, \[r5, #-62\]
+0+0ce <[^>]+> f935 1b3e 	ldrsh.w	r1, \[r5\], #62
+0+0d2 <[^>]+> f935 1b3e 	ldrsh.w	r1, \[r5\], #62
+0+0d6 <[^>]+> f935 1f3e 	ldrsh.w	r1, \[r5, #62\]!
+0+0da <[^>]+> f935 1d3e 	ldrsh.w	r1, \[r5, #-62\]!
+0+0de <[^>]+> 5f29      	ldrsh	r1, \[r5, r4\]
+0+0e0 <[^>]+> f939 100c 	ldrsh.w	r1, \[r9, ip\]
+0+0e4 <[^>]+> f9bf 1010 	ldrsh.w	r1, \[pc, #16\]	; 0+0f8 <[^>]+>
+0+0e8 <[^>]+> f9bf 100c 	ldrsh.w	r1, \[pc, #12\]	; 0+0f8 <[^>]+>
+0+0ec <[^>]+> f9bf 8008 	ldrsh.w	r8, \[pc, #8\]	; 0+0f8 <[^>]+>
+0+0f0 <[^>]+> f9bf 1006 	ldrsh.w	r1, \[pc, #6\]	; 0+0fa <[^>]+>
+0+0f4 <[^>]+> f93f 103e 	ldrsh.w	r1, \[pc, #-62\]	; 0+0ba <[^>]+>
+0+0f8 <[^>]+> bf00      	nop
+0+0fa <[^>]+> 6829      	ldr	r1, \[r5, #0\]
+0+0fc <[^>]+> f8d5 1080 	ldr.w	r1, \[r5, #128\]
+0+100 <[^>]+> 6fe9      	ldr	r1, \[r5, #124\]
+0+102 <[^>]+> f8d5 107c 	ldr.w	r1, \[r5, #124\]
+0+106 <[^>]+> f855 1c7c 	ldr.w	r1, \[r5, #-124\]
+0+10a <[^>]+> f855 1b7c 	ldr.w	r1, \[r5\], #124
+0+10e <[^>]+> f855 1b7c 	ldr.w	r1, \[r5\], #124
+0+112 <[^>]+> f855 1f7c 	ldr.w	r1, \[r5, #124\]!
+0+116 <[^>]+> f855 1d7c 	ldr.w	r1, \[r5, #-124\]!
+0+11a <[^>]+> 5929      	ldr	r1, \[r5, r4\]
+0+11c <[^>]+> f859 100c 	ldr.w	r1, \[r9, ip\]
+0+120 <[^>]+> 4904      	ldr	r1, \[pc, #16\]	\(0+134 <[^>]+>\)
+0+122 <[^>]+> f8df 1010 	ldr.w	r1, \[pc, #16\]	; 0+134 <[^>]+>
+0+126 <[^>]+> f8df 800c 	ldr.w	r8, \[pc, #12\]	; 0+134 <[^>]+>
+0+12a <[^>]+> f8df 100a 	ldr.w	r1, \[pc, #10\]	; 0+136 <[^>]+>
+0+12e <[^>]+> f85f 1036 	ldr.w	r1, \[pc, #-54\]	; 0+0fa <[^>]+>
+0+132 <[^>]+> 0000      	lsls	r0, r0, #0
+0+134 <[^>]+> bf00      	nop
+0+136 <[^>]+> 7029      	strb	r1, \[r5, #0\]
+0+138 <[^>]+> f885 1023 	strb.w	r1, \[r5, #35\]
+0+13c <[^>]+> 77e9      	strb	r1, \[r5, #31\]
+0+13e <[^>]+> f885 101f 	strb.w	r1, \[r5, #31\]
+0+142 <[^>]+> f805 1c1f 	strb.w	r1, \[r5, #-31\]
+0+146 <[^>]+> f805 1b1f 	strb.w	r1, \[r5\], #31
+0+14a <[^>]+> f805 1b1f 	strb.w	r1, \[r5\], #31
+0+14e <[^>]+> f805 1f1f 	strb.w	r1, \[r5, #31\]!
+0+152 <[^>]+> f805 1d1f 	strb.w	r1, \[r5, #-31\]!
+0+156 <[^>]+> 5529      	strb	r1, \[r5, r4\]
+0+158 <[^>]+> f809 100c 	strb.w	r1, \[r9, ip\]
+0+15c <[^>]+> f88f 1010 	strb.w	r1, \[pc, #16\]	; 0+170 <[^>]+>
+0+160 <[^>]+> f88f 100c 	strb.w	r1, \[pc, #12\]	; 0+170 <[^>]+>
+0+164 <[^>]+> f88f 8008 	strb.w	r8, \[pc, #8\]	; 0+170 <[^>]+>
+0+168 <[^>]+> f88f 1006 	strb.w	r1, \[pc, #6\]	; 0+172 <[^>]+>
+0+16c <[^>]+> f80f 103a 	strb.w	r1, \[pc, #-58\]	; 0+136 <[^>]+>
+0+170 <[^>]+> bf00      	nop
+0+172 <[^>]+> 8029      	strh	r1, \[r5, #0\]
+0+174 <[^>]+> f8a5 1042 	strh.w	r1, \[r5, #66\]
+0+178 <[^>]+> 87e9      	strh	r1, \[r5, #62\]
+0+17a <[^>]+> f8a5 103e 	strh.w	r1, \[r5, #62\]
+0+17e <[^>]+> f825 1c3e 	strh.w	r1, \[r5, #-62\]
+0+182 <[^>]+> f825 1b3e 	strh.w	r1, \[r5\], #62
+0+186 <[^>]+> f825 1b3e 	strh.w	r1, \[r5\], #62
+0+18a <[^>]+> f825 1f3e 	strh.w	r1, \[r5, #62\]!
+0+18e <[^>]+> f825 1d3e 	strh.w	r1, \[r5, #-62\]!
+0+192 <[^>]+> 5329      	strh	r1, \[r5, r4\]
+0+194 <[^>]+> f829 100c 	strh.w	r1, \[r9, ip\]
+0+198 <[^>]+> f8af 1010 	strh.w	r1, \[pc, #16\]	; 0+1ac <[^>]+>
+0+19c <[^>]+> f8af 100c 	strh.w	r1, \[pc, #12\]	; 0+1ac <[^>]+>
+0+1a0 <[^>]+> f8af 8008 	strh.w	r8, \[pc, #8\]	; 0+1ac <[^>]+>
+0+1a4 <[^>]+> f8af 1006 	strh.w	r1, \[pc, #6\]	; 0+1ae <[^>]+>
+0+1a8 <[^>]+> f82f 103a 	strh.w	r1, \[pc, #-58\]	; 0+172 <[^>]+>
+0+1ac <[^>]+> bf00      	nop
+0+1ae <[^>]+> 6029      	str	r1, \[r5, #0\]
+0+1b0 <[^>]+> f8c5 1080 	str.w	r1, \[r5, #128\]
+0+1b4 <[^>]+> 67e9      	str	r1, \[r5, #124\]
+0+1b6 <[^>]+> f8c5 107c 	str.w	r1, \[r5, #124\]
+0+1ba <[^>]+> f845 1c7c 	str.w	r1, \[r5, #-124\]
+0+1be <[^>]+> f845 1b7c 	str.w	r1, \[r5\], #124
+0+1c2 <[^>]+> f845 1b7c 	str.w	r1, \[r5\], #124
+0+1c6 <[^>]+> f845 1f7c 	str.w	r1, \[r5, #124\]!
+0+1ca <[^>]+> f845 1d7c 	str.w	r1, \[r5, #-124\]!
+0+1ce <[^>]+> 5129      	str	r1, \[r5, r4\]
+0+1d0 <[^>]+> f849 100c 	str.w	r1, \[r9, ip\]
+0+1d4 <[^>]+> f8cf 1010 	str.w	r1, \[pc, #16\]	; 0+1e8 <[^>]+>
+0+1d8 <[^>]+> f8cf 100c 	str.w	r1, \[pc, #12\]	; 0+1e8 <[^>]+>
+0+1dc <[^>]+> f8cf 8008 	str.w	r8, \[pc, #8\]	; 0+1e8 <[^>]+>
+0+1e0 <[^>]+> f8cf 1006 	str.w	r1, \[pc, #6\]	; 0+1ea <[^>]+>
+0+1e4 <[^>]+> f84f 103a 	str.w	r1, \[pc, #-58\]	; 0+1ae <[^>]+>
+0+1e8 <[^>]+> bf00      	nop
+0+1ea <[^>]+> a104      	add	r1, pc, #16	\(adr r1,0+1fc <[^>]+>\)
+0+1ec <[^>]+> f20f 010c 	addw	r1, pc, #12	; 0xc
+0+1f0 <[^>]+> f20f 0808 	addw	r8, pc, #8	; 0x8
+0+1f4 <[^>]+> f20f 0106 	addw	r1, pc, #6	; 0x6
+0+1f8 <[^>]+> f2af 0112 	subw	r1, pc, #18	; 0x12
+0+1fc <[^>]+> bf00      	nop
+0+1fe <[^>]+> bf00      	nop
+0+200 <[^>]+> f20f 0104 	addw	r1, pc, #4	; 0x4
+0+204 <[^>]+> f20f 0102 	addw	r1, pc, #2	; 0x2
+0+208 <[^>]+> bf00      	nop
+0+20a <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb2_relax.s b/gas/testsuite/gas/arm/thumb2_relax.s
new file mode 100644
index 000000000000..428e6ff55bab
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_relax.s
@@ -0,0 +1,62 @@
+	.text
+	.thumb
+	.syntax unified
+thumb2_relax:
+	.macro	ls op w=".w"
+1:
+	\op	r1, [r5]
+	\op	r1, [r5, #(far_\op + 4)]
+	\op	r1, [r5, #far_\op]
+	\op\w	r1, [r5, #far_\op]
+	\op	r1, [r5, #-far_\op]
+	\op	r1, [r5], #far_\op
+	\op	r1, [r5], #far_\op
+	\op	r1, [r5, #far_\op]!
+	\op	r1, [r5, #-far_\op]!
+	\op	r1, [r5, r4]
+	\op	r1, [r9, ip]
+	\op	r1, 1f
+	\op\w	r1, 1f
+	\op	r8, 1f
+	\op	r1, 2f
+	\op	r1, 1b
+	.align 2
+1:
+	nop
+2:
+	.endm
+.equ far_ldrb, 0x1f
+.equ far_ldrsb, 0x1f
+.equ far_ldrh, 0x3e
+.equ far_ldrsh, 0x3e
+.equ far_ldr, 0x7c
+.equ far_strb, 0x1f
+.equ far_strh, 0x3e
+.equ far_str, 0x7c
+	ls	ldrb
+	ls	ldrsb
+	ls	ldrh
+	ls	ldrsh
+	ls	ldr
+	ls	strb
+	ls	strh
+	ls	str
+	.purgem ls
+1:
+	adr	r1, 1f
+	adr.w	r1, 1f
+	adr	r8, 1f
+	adr	r1, 2f
+	adr	r1, 1b
+.align 2
+1:
+	nop
+2:
+	nop
+	@ Relaxation with conflicting alignment requirements.
+	adr	r1, 1f
+	adr	r1, 2f
+1:
+	nop
+2:
+	nop
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
new file mode 100644
index 000000000000..2977779aefdd
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -0,0 +1,956 @@
+# name: 32-bit Thumb instructions
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+# The arm-aout and arm-pe ports do not support Thumb branch relocations.
+# not-target: *-*-*aout* *-*-pe
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f041 0000 	orr\.w	r0, r1, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f041 00a5 	orr\.w	r0, r1, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f041 10a5 	orr\.w	r0, r1, #10813605	; 0xa500a5
+0[0-9a-f]+ <[^>]+> f041 20a5 	orr\.w	r0, r1, #2768282880	; 0xa500a500
+0[0-9a-f]+ <[^>]+> f041 30a5 	orr\.w	r0, r1, #2779096485	; 0xa5a5a5a5
+0[0-9a-f]+ <[^>]+> f041 4000 	orr\.w	r0, r1, #2147483648	; 0x80000000
+0[0-9a-f]+ <[^>]+> f041 4080 	orr\.w	r0, r1, #1073741824	; 0x40000000
+0[0-9a-f]+ <[^>]+> f041 4020 	orr\.w	r0, r1, #2684354560	; 0xa0000000
+0[0-9a-f]+ <[^>]+> f041 40a0 	orr\.w	r0, r1, #1342177280	; 0x50000000
+0[0-9a-f]+ <[^>]+> f041 5020 	orr\.w	r0, r1, #671088640	; 0x28000000
+0[0-9a-f]+ <[^>]+> f041 4014 	orr\.w	r0, r1, #2483027968	; 0x94000000
+0[0-9a-f]+ <[^>]+> f041 4094 	orr\.w	r0, r1, #1241513984	; 0x4a000000
+0[0-9a-f]+ <[^>]+> f041 4025 	orr\.w	r0, r1, #2768240640	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f041 40a5 	orr\.w	r0, r1, #1384120320	; 0x52800000
+0[0-9a-f]+ <[^>]+> f041 5025 	orr\.w	r0, r1, #692060160	; 0x29400000
+0[0-9a-f]+ <[^>]+> f041 50a5 	orr\.w	r0, r1, #346030080	; 0x14a00000
+0[0-9a-f]+ <[^>]+> f041 6025 	orr\.w	r0, r1, #173015040	; 0xa500000
+0[0-9a-f]+ <[^>]+> f041 60a5 	orr\.w	r0, r1, #86507520	; 0x5280000
+0[0-9a-f]+ <[^>]+> f041 7025 	orr\.w	r0, r1, #43253760	; 0x2940000
+0[0-9a-f]+ <[^>]+> f041 70a5 	orr\.w	r0, r1, #21626880	; 0x14a0000
+0[0-9a-f]+ <[^>]+> f441 0025 	orr\.w	r0, r1, #10813440	; 0xa50000
+0[0-9a-f]+ <[^>]+> f441 00a5 	orr\.w	r0, r1, #5406720	; 0x528000
+0[0-9a-f]+ <[^>]+> f441 1025 	orr\.w	r0, r1, #2703360	; 0x294000
+0[0-9a-f]+ <[^>]+> f441 10a5 	orr\.w	r0, r1, #1351680	; 0x14a000
+0[0-9a-f]+ <[^>]+> f441 2025 	orr\.w	r0, r1, #675840	; 0xa5000
+0[0-9a-f]+ <[^>]+> f441 20a5 	orr\.w	r0, r1, #337920	; 0x52800
+0[0-9a-f]+ <[^>]+> f441 3025 	orr\.w	r0, r1, #168960	; 0x29400
+0[0-9a-f]+ <[^>]+> f441 30a5 	orr\.w	r0, r1, #84480	; 0x14a00
+0[0-9a-f]+ <[^>]+> f441 4025 	orr\.w	r0, r1, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f441 40a5 	orr\.w	r0, r1, #21120	; 0x5280
+0[0-9a-f]+ <[^>]+> f441 5025 	orr\.w	r0, r1, #10560	; 0x2940
+0[0-9a-f]+ <[^>]+> f441 50a5 	orr\.w	r0, r1, #5280	; 0x14a0
+0[0-9a-f]+ <[^>]+> f441 6025 	orr\.w	r0, r1, #2640	; 0xa50
+0[0-9a-f]+ <[^>]+> f441 60a5 	orr\.w	r0, r1, #1320	; 0x528
+0[0-9a-f]+ <[^>]+> f441 7025 	orr\.w	r0, r1, #660	; 0x294
+0[0-9a-f]+ <[^>]+> f441 70a5 	orr\.w	r0, r1, #330	; 0x14a
+0[0-9a-f]+ <[^>]+> 3000      	adds	r0, #0
+0[0-9a-f]+ <[^>]+> 1c05      	adds	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 1c28      	adds	r0, r5, #0
+0[0-9a-f]+ <[^>]+> 1d50      	adds	r0, r2, #5
+0[0-9a-f]+ <[^>]+> 3081      	adds	r0, #129
+0[0-9a-f]+ <[^>]+> 3081      	adds	r0, #129
+0[0-9a-f]+ <[^>]+> 357e      	adds	r5, #126
+0[0-9a-f]+ <[^>]+> 1800      	adds	r0, r0, r0
+0[0-9a-f]+ <[^>]+> 1805      	adds	r5, r0, r0
+0[0-9a-f]+ <[^>]+> 1828      	adds	r0, r5, r0
+0[0-9a-f]+ <[^>]+> 1940      	adds	r0, r0, r5
+0[0-9a-f]+ <[^>]+> 18d1      	adds	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 4480      	add	r8, r0
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> eb00 0800 	add\.w	r8, r0, r0
+0[0-9a-f]+ <[^>]+> 4401      	add	r1, r0
+0[0-9a-f]+ <[^>]+> 4408      	add	r0, r1
+0[0-9a-f]+ <[^>]+> a000      	add	r0, pc, #0	\(adr r0,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a500      	add	r5, pc, #0	\(adr r5,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a081      	add	r0, pc, #516	\(adr r0,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a800      	add	r0, sp, #0
+0[0-9a-f]+ <[^>]+> ad00      	add	r5, sp, #0
+0[0-9a-f]+ <[^>]+> a881      	add	r0, sp, #516
+0[0-9a-f]+ <[^>]+> b000      	add	sp, #0
+0[0-9a-f]+ <[^>]+> b000      	add	sp, #0
+0[0-9a-f]+ <[^>]+> b041      	add	sp, #260
+0[0-9a-f]+ <[^>]+> f100 0000 	add\.w	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f110 0000 	adds\.w	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f100 0900 	add\.w	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f109 0000 	add\.w	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f100 0081 	add\.w	r0, r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f513 3580 	adds\.w	r5, r3, #65536	; 0x10000
+0[0-9a-f]+ <[^>]+> f10d 0001 	add\.w	r0, sp, #1	; 0x1
+0[0-9a-f]+ <[^>]+> f10d 0900 	add\.w	r9, sp, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f10d 0d04 	add\.w	sp, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> eb00 0000 	add\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb10 0000 	adds\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb00 0900 	add\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb09 0000 	add\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb00 0009 	add\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb09 080a 	add\.w	r8, r9, sl
+0[0-9a-f]+ <[^>]+> eb09 484a 	add\.w	r8, r9, sl, lsl #17
+0[0-9a-f]+ <[^>]+> eb08 081a 	add\.w	r8, r8, sl, lsr #32
+0[0-9a-f]+ <[^>]+> eb08 485a 	add\.w	r8, r8, sl, lsr #17
+0[0-9a-f]+ <[^>]+> eb09 082a 	add\.w	r8, r9, sl, asr #32
+0[0-9a-f]+ <[^>]+> eb09 486a 	add\.w	r8, r9, sl, asr #17
+0[0-9a-f]+ <[^>]+> eb09 083a 	add\.w	r8, r9, sl, rrx
+0[0-9a-f]+ <[^>]+> eb09 487a 	add\.w	r8, r9, sl, ror #17
+0[0-9a-f]+ <[^>]+> 3800      	subs	r0, #0
+0[0-9a-f]+ <[^>]+> 1e05      	subs	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 1e28      	subs	r0, r5, #0
+0[0-9a-f]+ <[^>]+> 1f50      	subs	r0, r2, #5
+0[0-9a-f]+ <[^>]+> 3881      	subs	r0, #129
+0[0-9a-f]+ <[^>]+> 3d08      	subs	r5, #8
+0[0-9a-f]+ <[^>]+> 1a00      	subs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> 1a05      	subs	r5, r0, r0
+0[0-9a-f]+ <[^>]+> 1a28      	subs	r0, r5, r0
+0[0-9a-f]+ <[^>]+> 1b40      	subs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> b0c1      	sub	sp, #260
+0[0-9a-f]+ <[^>]+> b0c1      	sub	sp, #260
+0[0-9a-f]+ <[^>]+> ebb8 0800 	subs\.w	r8, r8, r0
+0[0-9a-f]+ <[^>]+> ebb0 0008 	subs\.w	r0, r0, r8
+0[0-9a-f]+ <[^>]+> f5b0 7082 	subs\.w	r0, r0, #260	; 0x104
+0[0-9a-f]+ <[^>]+> f1b2 0104 	subs\.w	r1, r2, #4	; 0x4
+0[0-9a-f]+ <[^>]+> f5b3 3580 	subs\.w	r5, r3, #65536	; 0x10000
+0[0-9a-f]+ <[^>]+> f1ad 0104 	sub\.w	r1, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> f1ad 0900 	sub\.w	r9, sp, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1ad 0d04 	sub\.w	sp, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> 4140      	adcs	r0, r0
+0[0-9a-f]+ <[^>]+> 4145      	adcs	r5, r0
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> eb45 0000 	adc\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb41 0002 	adc\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> eb40 0900 	adc\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb49 0000 	adc\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb40 0009 	adc\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb50 0000 	adcs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb41 4062 	adc\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f141 0081 	adc\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4000      	ands	r0, r0
+0[0-9a-f]+ <[^>]+> 4005      	ands	r5, r0
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> ea05 0000 	and\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea01 0002 	and\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea00 0900 	and\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea09 0000 	and\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea00 0009 	and\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea10 0000 	ands\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea01 4062 	and\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f001 0081 	and\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4380      	bics	r0, r0
+0[0-9a-f]+ <[^>]+> 4385      	bics	r5, r0
+0[0-9a-f]+ <[^>]+> 43a8      	bics	r0, r5
+0[0-9a-f]+ <[^>]+> 43a8      	bics	r0, r5
+0[0-9a-f]+ <[^>]+> ea35 0000 	bics\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea25 0000 	bic\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea21 0002 	bic\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea20 0900 	bic\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea29 0000 	bic\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea20 0009 	bic\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea30 0000 	bics\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea21 4062 	bic\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f021 0081 	bic\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4040      	eors	r0, r0
+0[0-9a-f]+ <[^>]+> 4045      	eors	r5, r0
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> ea85 0000 	eor\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea81 0002 	eor\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea80 0900 	eor\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea89 0000 	eor\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea80 0009 	eor\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea90 0000 	eors\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea81 4062 	eor\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f081 0081 	eor\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4300      	orrs	r0, r0
+0[0-9a-f]+ <[^>]+> 4305      	orrs	r5, r0
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea45 0000 	orr\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea41 0002 	orr\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea40 0900 	orr\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea49 0000 	orr\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea40 0009 	orr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea50 0000 	orrs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea41 4062 	orr\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f041 0081 	orr\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ebd5 0500 	rsbs	r5, r5, r0
+0[0-9a-f]+ <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ebd5 0000 	rsbs	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ebc5 0000 	rsb	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ebc1 0002 	rsb	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ebc0 0900 	rsb	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ebc9 0000 	rsb	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ebc0 0009 	rsb	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ebc1 4062 	rsb	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f1c1 0081 	rsb	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4180      	sbcs	r0, r0
+0[0-9a-f]+ <[^>]+> 4185      	sbcs	r5, r0
+0[0-9a-f]+ <[^>]+> 41a8      	sbcs	r0, r5
+0[0-9a-f]+ <[^>]+> 41a8      	sbcs	r0, r5
+0[0-9a-f]+ <[^>]+> eb75 0000 	sbcs\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb65 0000 	sbc\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb61 0002 	sbc\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> eb60 0900 	sbc\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb69 0000 	sbc\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb60 0009 	sbc\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb70 0000 	sbcs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb61 4062 	sbc\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f161 0081 	sbc\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f36f 0000 	bfc	r0, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 5055 	bfc	r0, #21, #1
+0[0-9a-f]+ <[^>]+> f36f 0011 	bfc	r0, #0, #18
+0[0-9a-f]+ <[^>]+> f360 0000 	bfi	r0, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f360 0900 	bfi	r9, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f369 0000 	bfi	r0, r9, #0, #1
+0[0-9a-f]+ <[^>]+> f360 5055 	bfi	r0, r0, #21, #1
+0[0-9a-f]+ <[^>]+> f360 0011 	bfi	r0, r0, #0, #18
+0[0-9a-f]+ <[^>]+> f340 0000 	sbfx	r0, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f3c0 0900 	ubfx	r9, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f349 0000 	sbfx	r0, r9, #0, #1
+0[0-9a-f]+ <[^>]+> f3c0 5040 	ubfx	r0, r0, #21, #1
+0[0-9a-f]+ <[^>]+> f340 0011 	sbfx	r0, r0, #0, #18
+0[0-9a-f]+ <[^>]+> d0fe      	beq\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d02a      	beq\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d1fc      	bne\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d128      	bne\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2fa      	bcs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d226      	bcs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2f8      	bcs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d224      	bcs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f6      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d322      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f4      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d320      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f2      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d31e      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d4f0      	bmi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d41c      	bmi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d5ee      	bpl\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d51a      	bpl\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d6ec      	bvs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d618      	bvs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7ea      	bvc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d716      	bvc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e8      	bhi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d814      	bhi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e6      	bls\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d912      	bls\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7e4      	bvc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d710      	bvc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e2      	bhi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d80e      	bhi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e0      	bls\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d90c      	bls\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dade      	bge\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> da0a      	bge\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dbdc      	blt\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> db08      	blt\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dcda      	bgt\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> dc06      	bgt\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> ddd8      	ble\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> dd04      	ble\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d6      	b\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> e002      	b\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d4      	b\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> e000      	b\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0[0-9a-f]+ <[^>]+> f43f affe 	beq\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 8058 	beq\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f47f affa 	bne\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f040 8054 	bne\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff6 	bcs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 8050 	bcs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff2 	bcs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 804c 	bcs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afee 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8048 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afea 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8044 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afe6 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8040 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f53f afe2 	bmi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f100 803c 	bmi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f57f afde 	bpl\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f140 8038 	bpl\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5bf afda 	bvs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f180 8034 	bvs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afd6 	bvc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8030 	bvc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afd2 	bhi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 802c 	bhi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afce 	bls\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 8028 	bls\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afca 	bvc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8024 	bvc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afc6 	bhi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 8020 	bhi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afc2 	bls\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 801c 	bls\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f6bf afbe 	bge\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f280 8018 	bge\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f6ff afba 	blt\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f2c0 8014 	blt\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f73f afb6 	bgt\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f300 8010 	bgt\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f77f afb2 	ble\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f340 800c 	ble\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff bfae 	b\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 b808 	b\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff ffaa 	bl	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 f804 	bl	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff efa6 	blx	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 e800 	blx	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> 4748      	bx	r9
+0[0-9a-f]+ <[^>]+> 4780      	blx	r0
+0[0-9a-f]+ <[^>]+> 47c8      	blx	r9
+0[0-9a-f]+ <[^>]+> f3c0 8f00 	bxj	r0
+0[0-9a-f]+ <[^>]+> f3c9 8f00 	bxj	r9
+0[0-9a-f]+ <[^>]+> fab0 f080 	clz	r0, r0
+0[0-9a-f]+ <[^>]+> fab0 f980 	clz	r9, r0
+0[0-9a-f]+ <[^>]+> fab9 f089 	clz	r0, r9
+0[0-9a-f]+ <[^>]+> b661      	cpsie	f
+0[0-9a-f]+ <[^>]+> b672      	cpsid	i
+0[0-9a-f]+ <[^>]+> b664      	cpsie	a
+0[0-9a-f]+ <[^>]+> f3af 8620 	cpsid\.w	f
+0[0-9a-f]+ <[^>]+> f3af 8440 	cpsie\.w	i
+0[0-9a-f]+ <[^>]+> f3af 8680 	cpsid\.w	a
+0[0-9a-f]+ <[^>]+> f3af 8540 	cpsie	i, #0
+0[0-9a-f]+ <[^>]+> f3af 8751 	cpsid	i, #17
+0[0-9a-f]+ <[^>]+> f3af 8100 	cps	#0
+0[0-9a-f]+ <[^>]+> f3af 8111 	cps	#17
+0[0-9a-f]+ <[^>]+> 4600      	mov	r0, r0
+0[0-9a-f]+ <[^>]+> 4681      	mov	r9, r0
+0[0-9a-f]+ <[^>]+> 4648      	mov	r0, r9
+0[0-9a-f]+ <[^>]+> ea4f 0000 	mov\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea4f 0900 	mov\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea4f 0009 	mov\.w	r0, r9
+0[0-9a-f]+ <[^>]+> b910      	cbnz	r0, 0+432 <[^>]+>
+0[0-9a-f]+ <[^>]+> b105      	cbz	r5, 0+430 <[^>]+>
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf10      	yield
+0[0-9a-f]+ <[^>]+> bf20      	wfe
+0[0-9a-f]+ <[^>]+> bf30      	wfi
+0[0-9a-f]+ <[^>]+> bf40      	sev
+0[0-9a-f]+ <[^>]+> f3af 8000 	nop\.w
+0[0-9a-f]+ <[^>]+> f3af 8001 	yield\.w
+0[0-9a-f]+ <[^>]+> f3af 8002 	wfe\.w
+0[0-9a-f]+ <[^>]+> f3af 8003 	wfi\.w
+0[0-9a-f]+ <[^>]+> f3af 9004 	sev\.w
+0[0-9a-f]+ <[^>]+> bf90      	nop	\{9\}
+0[0-9a-f]+ <[^>]+> f3af 8081 	nop\.w	\{129\}
+0[0-9a-f]+ <[^>]+> bf08      	it	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf18      	it	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf28      	it	cs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf28      	it	cs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf48      	it	mi
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf58      	it	pl
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf68      	it	vs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf78      	it	vc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf88      	it	hi
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfa8      	it	ge
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfb8      	it	lt
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfc8      	it	gt
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfd8      	it	le
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfe8      	it	al
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0c      	ite	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf02      	ittt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0a      	itet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf06      	itte	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0e      	itee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf09      	itett	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf05      	ittet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf03      	ittte	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf07      	ittee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0b      	itete	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0d      	iteet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0f      	iteee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1c      	itt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf14      	ite	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1e      	ittt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf16      	itet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1a      	itte	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf12      	itee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1f      	itttt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf17      	itett	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1b      	ittet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1d      	ittte	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf19      	ittee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf15      	itete	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf13      	iteet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf11      	iteee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> f895 f000 	pld	\[r5\]
+0[0-9a-f]+ <[^>]+> f895 f330 	pld	\[r5, #816\]
+0[0-9a-f]+ <[^>]+> f815 fc30 	pld	\[r5, #-48\]
+0[0-9a-f]+ <[^>]+> f815 fb30 	pld	\[r5\], #48
+0[0-9a-f]+ <[^>]+> f815 f930 	pld	\[r5\], #-48
+0[0-9a-f]+ <[^>]+> f815 ff30 	pld	\[r5, #48\]!
+0[0-9a-f]+ <[^>]+> f815 fd30 	pld	\[r5, #-48\]!
+0[0-9a-f]+ <[^>]+> f815 f004 	pld	\[r5, r4\]
+0[0-9a-f]+ <[^>]+> f819 f00c 	pld	\[r9, ip\]
+0[0-9a-f]+ <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+5ba <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f f02a 	pld	\[pc, #-42\]	; 0+58e <[^>]+>
+0[0-9a-f]+ <[^>]+> e9d5 2300 	ldrd	r2, r3, \[r5\]
+0[0-9a-f]+ <[^>]+> e9d5 230c 	ldrd	r2, r3, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e955 230c 	ldrd	r2, r3, \[r5, #-48\]
+0[0-9a-f]+ <[^>]+> e9c5 2300 	strd	r2, r3, \[r5\]
+0[0-9a-f]+ <[^>]+> e9c5 230c 	strd	r2, r3, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e945 230c 	strd	r2, r3, \[r5, #-48\]
+0[0-9a-f]+ <[^>]+> f815 1e00 	ldrbt	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f815 1e30 	ldrbt	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f915 1e00 	ldrsbt	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f915 1e30 	ldrsbt	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f835 1e00 	ldrht	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f835 1e30 	ldrht	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f935 1e00 	ldrsht	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f935 1e30 	ldrsht	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f855 1e00 	ldrt	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f855 1e30 	ldrt	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e8d4 1f4f 	ldrexb	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e8d4 1f5f 	ldrexh	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e854 1f00 	ldrex	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e8d4 127f 	ldrexd	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2f41 	strexb	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2f51 	strexh	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e844 2100 	strex	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2371 	strexd	r1, r2, r3, \[r4\]
+0[0-9a-f]+ <[^>]+> e854 1f81 	ldrex	r1, \[r4, #516\]
+0[0-9a-f]+ <[^>]+> e844 2181 	strex	r1, r2, \[r4, #516\]
+0[0-9a-f]+ <[^>]+> c80e      	ldmia	r0!, \{r1, r2, r3\}
+0[0-9a-f]+ <[^>]+> ca07      	ldmia	r2!, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e892 0007 	ldmia\.w	r2, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e899 0007 	ldmia\.w	r9, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e890 0580 	ldmia\.w	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e8b0 0580 	ldmia\.w	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> c00e      	stmia	r0!, \{r1, r2, r3\}
+0[0-9a-f]+ <[^>]+> c20b      	stmia	r2!, \{r0, r1, r3\}
+0[0-9a-f]+ <[^>]+> e8a2 000b 	stmia\.w	r2!, \{r0, r1, r3\}
+0[0-9a-f]+ <[^>]+> e889 0007 	stmia\.w	r9, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e880 0580 	stmia\.w	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e8a0 0580 	stmia\.w	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e910 0580 	ldmdb	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e900 0580 	stmdb	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> fb00 0000 	mla	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0010 	mls	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0900 	mla	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb09 0000 	mla	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0009 	mla	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb00 9000 	mla	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> 4200      	tst	r0, r0
+0[0-9a-f]+ <[^>]+> 4200      	tst	r0, r0
+0[0-9a-f]+ <[^>]+> 4205      	tst	r5, r0
+0[0-9a-f]+ <[^>]+> 4228      	tst	r0, r5
+0[0-9a-f]+ <[^>]+> ea10 4f65 	tst\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea10 0f00 	tst\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea19 0f00 	tst\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea10 0f09 	tst\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f010 0f81 	tst\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f015 0f81 	tst\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea95 0f00 	teq	r5, r0
+0[0-9a-f]+ <[^>]+> ea90 0f05 	teq	r0, r5
+0[0-9a-f]+ <[^>]+> ea90 4f65 	teq	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea99 0f00 	teq	r9, r0
+0[0-9a-f]+ <[^>]+> ea90 0f09 	teq	r0, r9
+0[0-9a-f]+ <[^>]+> f090 0f81 	teq	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f095 0f81 	teq	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4280      	cmp	r0, r0
+0[0-9a-f]+ <[^>]+> 4280      	cmp	r0, r0
+0[0-9a-f]+ <[^>]+> 4285      	cmp	r5, r0
+0[0-9a-f]+ <[^>]+> 42a8      	cmp	r0, r5
+0[0-9a-f]+ <[^>]+> ebb0 4f65 	cmp\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ebb0 0f00 	cmp\.w	r0, r0
+0[0-9a-f]+ <[^>]+> 4581      	cmp	r9, r0
+0[0-9a-f]+ <[^>]+> ebb0 0f09 	cmp\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f1b0 0f81 	cmp\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f1b5 0f81 	cmp\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 42c0      	cmn	r0, r0
+0[0-9a-f]+ <[^>]+> 42c0      	cmn	r0, r0
+0[0-9a-f]+ <[^>]+> 42c5      	cmn	r5, r0
+0[0-9a-f]+ <[^>]+> 42e8      	cmn	r0, r5
+0[0-9a-f]+ <[^>]+> eb10 4f65 	cmn\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> eb10 0f00 	cmn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> eb19 0f00 	cmn\.w	r9, r0
+0[0-9a-f]+ <[^>]+> eb10 0f09 	cmn\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f110 0f81 	cmn\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f115 0f81 	cmn\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 1c00      	adds	r0, r0, #0
+0[0-9a-f]+ <[^>]+> 4600      	mov	r0, r0
+0[0-9a-f]+ <[^>]+> 1c05      	adds	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 4628      	mov	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4065 	mov\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 0000 	mov\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea5f 0900 	movs\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea5f 0009 	movs\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f04f 0081 	mov\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f04f 0581 	mov\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 43c0      	mvns	r0, r0
+0[0-9a-f]+ <[^>]+> ea6f 0000 	mvn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> 43c5      	mvns	r5, r0
+0[0-9a-f]+ <[^>]+> ea6f 0005 	mvn\.w	r0, r5
+0[0-9a-f]+ <[^>]+> ea6f 4065 	mvn\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea6f 0000 	mvn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea7f 0900 	mvns\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea7f 0009 	mvns\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f06f 0081 	mvn\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f06f 0581 	mvn\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f240 0000 	movw	r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f2c0 0000 	movt	r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f240 0900 	movw	r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f249 0000 	movw	r0, #36864	; 0x9000
+0[0-9a-f]+ <[^>]+> f640 0000 	movw	r0, #2048	; 0x800
+0[0-9a-f]+ <[^>]+> f240 5000 	movw	r0, #1280	; 0x500
+0[0-9a-f]+ <[^>]+> f240 0081 	movw	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f64f 70ff 	movw	r0, #65535	; 0xffff
+0[0-9a-f]+ <[^>]+> f3ef 8000 	mrs	r0, CPSR
+0[0-9a-f]+ <[^>]+> f3ff 8000 	mrs	r0, SPSR
+0[0-9a-f]+ <[^>]+> f3ef 8900 	mrs	r9, CPSR
+0[0-9a-f]+ <[^>]+> f3ff 8900 	mrs	r9, SPSR
+0[0-9a-f]+ <[^>]+> f380 8100 	msr	CPSR_c, r0
+0[0-9a-f]+ <[^>]+> f390 8100 	msr	SPSR_c, r0
+0[0-9a-f]+ <[^>]+> f389 8100 	msr	CPSR_c, r9
+0[0-9a-f]+ <[^>]+> f380 8200 	msr	CPSR_x, r0
+0[0-9a-f]+ <[^>]+> f380 8400 	msr	CPSR_s, r0
+0[0-9a-f]+ <[^>]+> f380 8800 	msr	CPSR_f, r0
+0[0-9a-f]+ <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb09 f000 	mul\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb00 f009 	mul\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 f909 	mul\.w	r9, r0, r9
+0[0-9a-f]+ <[^>]+> 4345      	muls	r5, r0
+0[0-9a-f]+ <[^>]+> 4345      	muls	r5, r0
+0[0-9a-f]+ <[^>]+> 4368      	muls	r0, r5
+0[0-9a-f]+ <[^>]+> fb80 0100 	smull	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fba0 0100 	umull	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0100 	smlal	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fbe0 0100 	umlal	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fb80 9000 	smull	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb80 0900 	smull	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb89 0100 	smull	r0, r1, r9, r0
+0[0-9a-f]+ <[^>]+> fb80 0109 	smull	r0, r1, r0, r9
+0[0-9a-f]+ <[^>]+> 4240      	negs	r0, r0
+0[0-9a-f]+ <[^>]+> 4268      	negs	r0, r5
+0[0-9a-f]+ <[^>]+> 4245      	negs	r5, r0
+0[0-9a-f]+ <[^>]+> f1d0 0000 	rsbs	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d0 0500 	rsbs	r5, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d5 0000 	rsbs	r0, r5, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1c9 0000 	rsb	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1c0 0900 	rsb	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d9 0000 	rsbs	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d0 0900 	rsbs	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> eac0 0000 	pkhbt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eac0 0900 	pkhbt	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eac9 0000 	pkhbt	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eac0 0009 	pkhbt	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eac0 5000 	pkhbt	r0, r0, r0, lsl #20
+0[0-9a-f]+ <[^>]+> eac0 00c0 	pkhbt	r0, r0, r0, lsl #3
+0[0-9a-f]+ <[^>]+> eac2 0103 	pkhbt	r1, r2, r3
+0[0-9a-f]+ <[^>]+> eac2 4163 	pkhtb	r1, r2, r3, asr #17
+0[0-9a-f]+ <[^>]+> b401      	push	\{r0\}
+0[0-9a-f]+ <[^>]+> bc01      	pop	\{r0\}
+0[0-9a-f]+ <[^>]+> b502      	push	\{r1, lr\}
+0[0-9a-f]+ <[^>]+> bd02      	pop	\{r1, pc\}
+0[0-9a-f]+ <[^>]+> e92d 1f00 	stmdb	sp!, \{r8, r9, sl, fp, ip\}
+0[0-9a-f]+ <[^>]+> e8bd 1f00 	ldmia\.w	sp!, \{r8, r9, sl, fp, ip\}
+0[0-9a-f]+ <[^>]+> fa92 f113 	qadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f113 	qadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f113 	qaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f113 	qsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f113 	qsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f113 	qsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f103 	sadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f103 	sadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f103 	saddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f103 	ssub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f103 	ssub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f103 	ssubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f123 	shadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f123 	shadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f123 	shaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f123 	shsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f123 	shsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f123 	shsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f143 	uadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f143 	uadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f143 	uaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f143 	usub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f143 	usub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f143 	usubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f163 	uhadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f163 	uhadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f163 	uhaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f163 	uhsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f163 	uhsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f163 	uhsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f153 	uqadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f153 	uqadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f153 	uqaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f153 	uqsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f153 	uqsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f153 	uqsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f183 	sel	r1, r2, r3
+0[0-9a-f]+ <[^>]+> ba00      	rev	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f080 	rev\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ba28      	rev	r0, r5
+0[0-9a-f]+ <[^>]+> ba05      	rev	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f089 	rev\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f980 	rev\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ba40      	rev16	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f090 	rev16\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ba68      	rev16	r0, r5
+0[0-9a-f]+ <[^>]+> ba45      	rev16	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f099 	rev16\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f990 	rev16\.w	r9, r0
+0[0-9a-f]+ <[^>]+> bac0      	revsh	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f0b0 	revsh\.w	r0, r0
+0[0-9a-f]+ <[^>]+> bae8      	revsh	r0, r5
+0[0-9a-f]+ <[^>]+> bac5      	revsh	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f0b9 	revsh\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f9b0 	revsh\.w	r9, r0
+0[0-9a-f]+ <[^>]+> fa90 f0a0 	rbit	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f0a0 	rbit	r0, r0
+0[0-9a-f]+ <[^>]+> fa95 f0a0 	rbit	r0, r5
+0[0-9a-f]+ <[^>]+> fa90 f5a0 	rbit	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f0a0 	rbit	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f9a0 	rbit	r9, r0
+0[0-9a-f]+ <[^>]+> 0440      	lsls	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 0380      	lsls	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 0445      	lsls	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 03a8      	lsls	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 4080      	lsls	r0, r0
+0[0-9a-f]+ <[^>]+> 40a8      	lsls	r0, r5
+0[0-9a-f]+ <[^>]+> 40a8      	lsls	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4949 	mov\.w	r9, r9, lsl #17
+0[0-9a-f]+ <[^>]+> ea4f 3989 	mov\.w	r9, r9, lsl #14
+0[0-9a-f]+ <[^>]+> ea5f 4049 	movs\.w	r0, r9, lsl #17
+0[0-9a-f]+ <[^>]+> ea4f 3980 	mov\.w	r9, r0, lsl #14
+0[0-9a-f]+ <[^>]+> fa00 f000 	lsl\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa09 f909 	lsl\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa19 f900 	lsls\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa00 f009 	lsl\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa00 f005 	lsl\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa11 f002 	lsls\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> 0c40      	lsrs	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 0b80      	lsrs	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 0c45      	lsrs	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 0ba8      	lsrs	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 40c0      	lsrs	r0, r0
+0[0-9a-f]+ <[^>]+> 40e8      	lsrs	r0, r5
+0[0-9a-f]+ <[^>]+> 40e8      	lsrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4959 	mov\.w	r9, r9, lsr #17
+0[0-9a-f]+ <[^>]+> ea4f 3999 	mov\.w	r9, r9, lsr #14
+0[0-9a-f]+ <[^>]+> ea5f 4059 	movs\.w	r0, r9, lsr #17
+0[0-9a-f]+ <[^>]+> ea4f 3990 	mov\.w	r9, r0, lsr #14
+0[0-9a-f]+ <[^>]+> fa20 f000 	lsr\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa29 f909 	lsr\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa39 f900 	lsrs\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa20 f009 	lsr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa20 f005 	lsr\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa31 f002 	lsrs\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> 1440      	asrs	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 1380      	asrs	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 1445      	asrs	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 13a8      	asrs	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 4100      	asrs	r0, r0
+0[0-9a-f]+ <[^>]+> 4128      	asrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4128      	asrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4969 	mov\.w	r9, r9, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 39a9 	mov\.w	r9, r9, asr #14
+0[0-9a-f]+ <[^>]+> ea5f 4069 	movs\.w	r0, r9, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 39a0 	mov\.w	r9, r0, asr #14
+0[0-9a-f]+ <[^>]+> fa40 f000 	asr\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa49 f909 	asr\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa59 f900 	asrs\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa40 f009 	asr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa40 f005 	asr\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa51 f002 	asrs\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea5f 4070 	movs\.w	r0, r0, ror #17
+0[0-9a-f]+ <[^>]+> ea5f 30b0 	movs\.w	r0, r0, ror #14
+0[0-9a-f]+ <[^>]+> ea5f 4570 	movs\.w	r5, r0, ror #17
+0[0-9a-f]+ <[^>]+> ea5f 30b5 	movs\.w	r0, r5, ror #14
+0[0-9a-f]+ <[^>]+> 41c0      	rors	r0, r0
+0[0-9a-f]+ <[^>]+> 41e8      	rors	r0, r5
+0[0-9a-f]+ <[^>]+> 41e8      	rors	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4979 	mov\.w	r9, r9, ror #17
+0[0-9a-f]+ <[^>]+> ea4f 39b9 	mov\.w	r9, r9, ror #14
+0[0-9a-f]+ <[^>]+> ea5f 4079 	movs\.w	r0, r9, ror #17
+0[0-9a-f]+ <[^>]+> ea4f 39b0 	mov\.w	r9, r0, ror #14
+0[0-9a-f]+ <[^>]+> fa60 f000 	ror\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa69 f909 	ror\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa79 f900 	rors\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa60 f009 	ror\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa60 f005 	ror\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa71 f002 	rors\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> f7f0 8000 	smc	#0	; 0x0
+0[0-9a-f]+ <[^>]+> f7fd 8bca 	smc	#43981	; 0xabcd
+0[0-9a-f]+ <[^>]+> fb10 0000 	smlabb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0900 	smlabb	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 0000 	smlabb	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0009 	smlabb	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 9000 	smlabb	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 0020 	smlatb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0010 	smlabt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0030 	smlatt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0000 	smlawb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0010 	smlawt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0000 	smlad	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0010 	smladx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0000 	smlsd	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0010 	smlsdx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0000 	smmla	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0010 	smmlar	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0000 	smmls	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0010 	smmlsr	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 0000 	usada8	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0080 	smlalbb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 9080 	smlalbb	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0980 	smlalbb	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fbc9 0080 	smlalbb	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fbc0 0089 	smlalbb	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fbc0 00a0 	smlaltb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0090 	smlalbt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00b0 	smlaltt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00c0 	smlald	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00d0 	smlaldx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00c0 	smlsld	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00d0 	smlsldx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbe0 0060 	umaal	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f000 	smulbb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f900 	smulbb	r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 f000 	smulbb	r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 f009 	smulbb	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 f020 	smultb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f010 	smulbt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f030 	smultt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f000 	smulwb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f010 	smulwt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f000 	smmul	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f010 	smmulr	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f000 	smuad	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f010 	smuadx	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f000 	smusd	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f010 	smusdx	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 f000 	usad8	r0, r0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0900 	ssat	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0011 	ssat	r0, #17, r0
+0[0-9a-f]+ <[^>]+> f309 0000 	ssat	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f300 7000 	ssat	r0, #0, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f320 00c0 	ssat	r0, #0, r0, asr #3
+0[0-9a-f]+ <[^>]+> f320 0000 	ssat16	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f320 0900 	ssat16	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f320 0009 	ssat16	r0, #9, r0
+0[0-9a-f]+ <[^>]+> f329 0000 	ssat16	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0900 	usat	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0011 	usat	r0, #17, r0
+0[0-9a-f]+ <[^>]+> f389 0000 	usat	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f380 7000 	usat	r0, #0, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f3a0 00c0 	usat	r0, #0, r0, asr #3
+0[0-9a-f]+ <[^>]+> f3a0 0000 	usat16	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0900 	usat16	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0009 	usat16	r0, #9, r0
+0[0-9a-f]+ <[^>]+> f3a9 0000 	usat16	r0, #0, r9
+0[0-9a-f]+ <[^>]+> b240      	sxtb	r0, r0
+0[0-9a-f]+ <[^>]+> b240      	sxtb	r0, r0
+0[0-9a-f]+ <[^>]+> b245      	sxtb	r5, r0
+0[0-9a-f]+ <[^>]+> b268      	sxtb	r0, r5
+0[0-9a-f]+ <[^>]+> fa4f f182 	sxtb\.w	r1, r2
+0[0-9a-f]+ <[^>]+> fa4f f192 	sxtb\.w	r1, r2, ror #8
+0[0-9a-f]+ <[^>]+> fa4f f1a2 	sxtb\.w	r1, r2, ror #16
+0[0-9a-f]+ <[^>]+> fa4f f1b2 	sxtb\.w	r1, r2, ror #24
+0[0-9a-f]+ <[^>]+> fa2f f182 	sxtb16	r1, r2
+0[0-9a-f]+ <[^>]+> fa2f f889 	sxtb16	r8, r9
+0[0-9a-f]+ <[^>]+> b211      	sxth	r1, r2
+0[0-9a-f]+ <[^>]+> fa0f f889 	sxth\.w	r8, r9
+0[0-9a-f]+ <[^>]+> b2d1      	uxtb	r1, r2
+0[0-9a-f]+ <[^>]+> fa5f f889 	uxtb\.w	r8, r9
+0[0-9a-f]+ <[^>]+> fa3f f182 	uxtb16	r1, r2
+0[0-9a-f]+ <[^>]+> fa3f f889 	uxtb16	r8, r9
+0[0-9a-f]+ <[^>]+> b291      	uxth	r1, r2
+0[0-9a-f]+ <[^>]+> fa1f f889 	uxth\.w	r8, r9
+0[0-9a-f]+ <[^>]+> fa40 f080 	sxtab	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f080 	sxtab	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f990 	sxtab	r9, r0, r0, ror #8
+0[0-9a-f]+ <[^>]+> fa49 f0a0 	sxtab	r0, r9, r0, ror #16
+0[0-9a-f]+ <[^>]+> fa40 f0b9 	sxtab	r0, r0, r9, ror #24
+0[0-9a-f]+ <[^>]+> fa22 f183 	sxtab16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa02 f183 	sxtah	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa52 f183 	uxtab	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa32 f183 	uxtab16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa12 f183 	uxtah	r1, r2, r3
+0[0-9a-f]+ <[^>]+> f89f 12aa 	ldrb\.w	r1, \[pc, #682\]	; 0+e02 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155 	ldrb\.w	r1, \[pc, #341\]	; 0+cb1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa 	ldrb\.w	r1, \[pc, #-682\]	; 0+8b6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155 	ldrb\.w	r1, \[pc, #-341\]	; 0+a0f <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa 	ldrsb\.w	r1, \[pc, #682\]	; 0+e12 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155 	ldrsb\.w	r1, \[pc, #341\]	; 0+cc1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa 	ldrsb\.w	r1, \[pc, #-682\]	; 0+8c6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155 	ldrsb\.w	r1, \[pc, #-341\]	; 0+a1f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa 	ldrh\.w	r1, \[pc, #682\]	; 0+e22 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155 	ldrh\.w	r1, \[pc, #341\]	; 0+cd1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa 	ldrh\.w	r1, \[pc, #-682\]	; 0+8d6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155 	ldrh\.w	r1, \[pc, #-341\]	; 0+a2f <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa 	ldrsh\.w	r1, \[pc, #682\]	; 0+e32 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155 	ldrsh\.w	r1, \[pc, #341\]	; 0+ce1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa 	ldrsh\.w	r1, \[pc, #-682\]	; 0+8e6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155 	ldrsh\.w	r1, \[pc, #-341\]	; 0+a3f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa 	ldr\.w	r1, \[pc, #682\]	; 0+e42 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+cf1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+8f6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+a4f <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 0900 	addw	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f60f 76ff 	addw	r6, pc, #4095	; 0xfff
+0[0-9a-f]+ <[^>]+> f6a9 2685 	subw	r6, r9, #2693	; 0xa85
+0[0-9a-f]+ <[^>]+> f2a9 567a 	subw	r6, r9, #1402	; 0x57a
+0[0-9a-f]+ <[^>]+> e8df f006 	tbb	\[pc, r6\]
+0[0-9a-f]+ <[^>]+> e8d0 f009 	tbb	\[r0, r9\]
+0[0-9a-f]+ <[^>]+> e8df f017 	tbh	\[pc, r7, lsl #1\]
+0[0-9a-f]+ <[^>]+> e8d0 f018 	tbh	\[r0, r8, lsl #1\]
+0[0-9a-f]+ <[^>]+> f84d 8d04 	str.w	r8, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f85d 8b04 	ldr.w	r8, \[sp\], #4
+0[0-9a-f]+ <[^>]+> e930 0580 	ldmdb	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e920 0580 	stmdb	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> c806      	ldmia	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> c006      	stmia	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> e890 0300 	ldmia.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> e880 0300 	stmia.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> c806      	ldmia	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> c006      	stmia	r0!, \{r1, r2\}
+0[0-9a-f]+ <[^>]+> e890 0300 	ldmia.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> e880 0300 	stmia.w	r0, \{r8, r9\}
+0[0-9a-f]+ <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
new file mode 100644
index 000000000000..b75a0850f384
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -0,0 +1,771 @@
+	.text
+	.thumb
+	.syntax unified
+
+encode_thumb32_immediate:
+	orr	r0, r1, #0x00000000
+	orr	r0, r1, #0x000000a5
+	orr	r0, r1, #0x00a500a5
+	orr	r0, r1, #0xa500a500
+	orr	r0, r1, #0xa5a5a5a5
+
+	orr	r0, r1, #0xa5 << 31
+	orr	r0, r1, #0xa5 << 30
+	orr	r0, r1, #0xa5 << 29
+	orr	r0, r1, #0xa5 << 28
+	orr	r0, r1, #0xa5 << 27
+	orr	r0, r1, #0xa5 << 26
+	orr	r0, r1, #0xa5 << 25
+	orr	r0, r1, #0xa5 << 24
+	orr	r0, r1, #0xa5 << 23
+	orr	r0, r1, #0xa5 << 22
+	orr	r0, r1, #0xa5 << 21
+	orr	r0, r1, #0xa5 << 20
+	orr	r0, r1, #0xa5 << 19
+	orr	r0, r1, #0xa5 << 18
+	orr	r0, r1, #0xa5 << 17
+	orr	r0, r1, #0xa5 << 16
+	orr	r0, r1, #0xa5 << 15
+	orr	r0, r1, #0xa5 << 14
+	orr	r0, r1, #0xa5 << 13
+	orr	r0, r1, #0xa5 << 12
+	orr	r0, r1, #0xa5 << 11
+	orr	r0, r1, #0xa5 << 10
+	orr	r0, r1, #0xa5 << 9
+	orr	r0, r1, #0xa5 << 8
+	orr	r0, r1, #0xa5 << 7
+	orr	r0, r1, #0xa5 << 6
+	orr	r0, r1, #0xa5 << 5
+	orr	r0, r1, #0xa5 << 4
+	orr	r0, r1, #0xa5 << 3
+	orr	r0, r1, #0xa5 << 2
+	orr	r0, r1, #0xa5 << 1
+
+add_sub:
+	@ Should be format 1, Some have equivalent format 2 encodings
+	adds	r0, r0, #0
+	adds	r5, r0, #0
+	adds	r0, r5, #0
+	adds	r0, r2, #5
+
+	adds	r0, #129	@ format 2
+	adds	r0, r0, #129
+	adds	r5, #126
+
+	adds	r0, r0, r0	@ format 3
+	adds	r5, r0, r0
+	adds	r0, r5, r0
+	adds	r0, r0, r5
+	adds	r1, r2, r3
+
+	add	r8, r0		@ format 4
+	add	r0, r8
+	add	r0, r8, r0
+	add	r0, r0, r8
+	add	r8, r0, r0	@ ... not this one
+
+	add	r1, r0
+	add	r0, r1
+
+	add	r0, pc, #0	@ format 5
+	add	r5, pc, #0
+	add	r0, pc, #516
+
+	add	r0, sp, #0	@ format 6
+	add	r5, sp, #0
+	add	r0, sp, #516
+
+	add	sp, #0		@ format 7
+	add	sp, sp, #0
+	add	sp, #260
+
+	add.w	r0, r0, #0	@ T32 format 1
+	adds.w	r0, r0, #0
+	add.w	r9, r0, #0
+	add.w	r0, r9, #0
+	add.w	r0, r0, #129
+	adds	r5, r3, #0x10000
+	add	r0, sp, #1
+	add	r9, sp, #0
+	add.w	sp, sp, #4
+
+	add.w	r0, r0, r0	@ T32 format 2
+	adds.w	r0, r0, r0
+	add.w	r9, r0, r0
+	add.w	r0, r9, r0
+	add.w	r0, r0, r9
+
+	add.w	r8, r9, r10
+	add.w	r8, r9, r10, lsl #17
+	add.w	r8, r8, r10, lsr #32
+	add.w	r8, r8, r10, lsr #17
+	add.w	r8, r9, r10, asr #32
+	add.w	r8, r9, r10, asr #17
+	add.w	r8, r9, r10, rrx
+	add.w	r8, r9, r10, ror #17
+
+	subs	r0, r0, #0	@ format 1
+	subs	r5, r0, #0
+	subs	r0, r5, #0
+	subs	r0, r2, #5
+
+	subs	r0, r0, #129
+	subs	r5, #8
+
+	subs	r0, r0, r0	@ format 3
+	subs	r5, r0, r0
+	subs	r0, r5, r0
+	subs	r0, r0, r5
+
+	sub	sp, #260	@ format 4
+	sub	sp, sp, #260
+
+	subs	r8, r0		@ T32 format 2
+	subs	r0, r8
+	subs	r0, #260	@ T32 format 1
+	subs.w	r1, r2, #4
+	subs	r5, r3, #0x10000
+	sub	r1, sp, #4
+	sub	r9, sp, #0
+	sub.w	sp, sp, #4
+
+arit3:
+	.macro arit3 op ops opw opsw
+	\ops	r0, r0
+	\ops	r5, r0
+	\ops	r0, r5
+	\ops	r0, r0, r5
+	\ops	r0, r5, r0
+	\op	r0, r5, r0
+	\op	r0, r1, r2
+	\op	r9, r0, r0
+	\op	r0, r9, r0
+	\op	r0, r0, r9
+	\opsw	r0, r0, r0
+	\opw	r0, r1, r2, asr #17
+	\opw	r0, r1, #129
+	.endm
+
+	arit3	adc adcs adc.w adcs.w
+	arit3	and ands and.w ands.w
+	arit3	bic bics bic.w bics.w
+	arit3	eor eors eor.w eors.w
+	arit3	orr orrs orr.w orrs.w
+	arit3	rsb rsbs rsb.w rsbs.w
+	arit3	sbc sbcs sbc.w sbcs.w
+
+	.purgem arit3
+
+bfc_bfi_bfx:
+	bfc	r0, #0, #1
+	bfc	r9, #0, #1
+	bfi	r9, #0, #0, #1
+	bfc	r0, #21, #1
+	bfc	r0, #0, #18
+
+	bfi	r0, r0, #0, #1
+	bfi	r9, r0, #0, #1
+	bfi	r0, r9, #0, #1
+	bfi	r0, r0, #21, #1
+	bfi	r0, r0, #0, #18
+
+	sbfx	r0, r0, #0, #1
+	ubfx	r9, r0, #0, #1
+	sbfx	r0, r9, #0, #1
+	ubfx	r0, r0, #21, #1
+	sbfx	r0, r0, #0, #18
+
+	.globl	branches
+branches:
+	.macro bra op
+	\op	1b
+	\op	1f
+	.endm
+1:
+	bra	beq.n
+	bra	bne.n
+	bra	bcs.n
+	bra	bhs.n
+	bra	bcc.n
+	bra	bul.n
+	bra	blo.n
+	bra	bmi.n
+	bra	bpl.n
+	bra	bvs.n
+	bra	bvc.n
+	bra	bhi.n
+	bra	bls.n
+	bra	bvc.n
+	bra	bhi.n
+	bra	bls.n
+	bra	bge.n
+	bra	blt.n
+	bra	bgt.n
+	bra	ble.n
+	bra	bal.n
+	bra	b.n
+	@ bl, blx have no short form.
+	.balign 4
+1:
+	bra	beq.w
+	bra	bne.w
+	bra	bcs.w
+	bra	bhs.w
+	bra	bcc.w
+	bra	bul.w
+	bra	blo.w
+	bra	bmi.w
+	bra	bpl.w
+	bra	bvs.w
+	bra	bvc.w
+	bra	bhi.w
+	bra	bls.w
+	bra	bvc.w
+	bra	bhi.w
+	bra	bls.w
+	bra	bge.w
+	bra	blt.w
+	bra	bgt.w
+	bra	ble.w
+	bra	b.w
+	bra	bl
+	bra	blx
+	.balign 4
+1:
+	bx	r9
+	blx	r0
+	blx	r9
+	bxj	r0
+	bxj	r9
+	.purgem bra
+
+clz:
+	clz	r0, r0
+	clz	r9, r0
+	clz	r0, r9
+
+cps:
+	cpsie	f
+	cpsid	i
+	cpsie	a
+	cpsid.w	f
+	cpsie.w	i
+	cpsid.w	a
+	cpsie	i, #0
+	cpsid	i, #17
+	cps	#0
+	cps	#17
+
+cpy:
+	cpy	r0, r0
+	cpy	r9, r0
+	cpy	r0, r9
+	cpy.w	r0, r0
+	cpy.w	r9, r0
+	cpy.w	r0, r9
+
+czb:
+	cbnz	r0, 2f
+	cbz	r5, 1f
+
+nop_hint:
+	nop
+1:	yield
+2:	wfe
+	wfi
+	sev
+
+	nop.w
+	yield.w
+	wfe.w
+	wfi.w
+	sev.w
+
+	nop {9}
+	nop {129}
+
+it:
+	.macro nop1 cond ncond a
+	.ifc \a,t
+	nop\cond
+	.else
+	nop\ncond
+	.endif
+	.endm
+	.macro it0 cond m=
+	it\m \cond
+	nop\cond
+	.endm
+	.macro it1 cond ncond a m=
+	it0 \cond \a\m
+	nop1 \cond \ncond \a
+	.endm
+	.macro it2 cond ncond a b m=
+	it1 \cond \ncond \a \b\m
+	nop1 \cond \ncond \b
+	.endm
+	.macro it3 cond ncond a b c
+	it2 \cond \ncond \a \b \c
+	nop1 \cond \ncond \c
+	.endm
+
+	it0	eq
+	it0	ne
+	it0	cs
+	it0	hs
+	it0	cc
+	it0	ul
+	it0	lo
+	it0	mi
+	it0	pl
+	it0	vs
+	it0	vc
+	it0	hi
+	it0	ge
+	it0	lt
+	it0	gt
+	it0	le
+	it0	al
+	it1 eq ne t
+	it1 eq ne e
+	it2 eq ne t t
+	it2 eq ne e t
+	it2 eq ne t e
+	it2 eq ne e e
+	it3 eq ne t t t
+	it3 eq ne e t t
+	it3 eq ne t e t
+	it3 eq ne t t e
+	it3 eq ne t e e
+	it3 eq ne e t e
+	it3 eq ne e e t
+	it3 eq ne e e e
+
+	it1 ne eq t
+	it1 ne eq e
+	it2 ne eq t t
+	it2 ne eq e t
+	it2 ne eq t e
+	it2 ne eq e e
+	it3 ne eq t t t
+	it3 ne eq e t t
+	it3 ne eq t e t
+	it3 ne eq t t e
+	it3 ne eq t e e
+	it3 ne eq e t e
+	it3 ne eq e e t
+	it3 ne eq e e e
+
+ldst:
+1:
+	pld	[r5]
+	pld	[r5, #0x330]
+	pld	[r5, #-0x30]
+	pld	[r5], #0x30
+	pld	[r5], #-0x30
+	pld	[r5, #0x30]!
+	pld	[r5, #-0x30]!
+	pld	[r5, r4]
+	pld	[r9, ip]
+	pld	1f
+	pld	1b
+1:
+
+	ldrd	r2, r3, [r5]
+	ldrd	r2, [r5, #0x30]
+	ldrd	r2, [r5, #-0x30]
+	strd	r2, r3, [r5]
+	strd	r2, [r5, #0x30]
+	strd	r2, [r5, #-0x30]
+
+	ldrbt	r1, [r5]
+	ldrbt	r1, [r5, #0x30]
+	ldrsbt	r1, [r5]
+	ldrsbt	r1, [r5, #0x30]
+	ldrht	r1, [r5]
+	ldrht	r1, [r5, #0x30]
+	ldrsht	r1, [r5]
+	ldrsht	r1, [r5, #0x30]
+	ldrt	r1, [r5]
+	ldrt	r1, [r5, #0x30]
+
+ldxstx:
+	ldrexb	r1, [r4]
+	ldrexh	r1, [r4]
+	ldrex	r1, [r4]
+	ldrexd	r1, r2, [r4]
+
+	strexb	r1, r2, [r4]
+	strexh	r1, r2, [r4]
+	strex	r1, r2, [r4]
+	strexd	r1, r2, r3, [r4]
+
+	ldrex	r1, [r4,#516]
+	strex	r1, r2, [r4,#516]
+
+ldmstm:
+	ldmia	r0!, {r1,r2,r3}
+	ldmia	r2, {r0,r1,r2}
+	ldmia.w	r2, {r0,r1,r2}
+	ldmia	r9, {r0,r1,r2}
+	ldmia	r0, {r7,r8,r10}
+	ldmia	r0!, {r7,r8,r10}
+	
+	stmia	r0!, {r1,r2,r3}
+	stmia	r2!, {r0,r1,r3}
+	stmia.w	r2!, {r0,r1,r3}
+	stmia	r9, {r0,r1,r2}
+	stmia	r0, {r7,r8,r10}
+	stmia	r0!, {r7,r8,r10}
+
+	ldmdb	r0, {r7,r8,r10}
+	stmdb	r0, {r7,r8,r10}
+
+mlas:
+	mla	r0, r0, r0, r0
+	mls	r0, r0, r0, r0
+	mla	r9, r0, r0, r0
+	mla	r0, r9, r0, r0
+	mla	r0, r0, r9, r0
+	mla	r0, r0, r0, r9
+
+tst_teq_cmp_cmn_mov_mvn:
+	.macro	mt op ops opw opsw
+	\ops	r0, r0
+	\op	r0, r0
+	\ops	r5, r0
+	\op	r0, r5
+	\op	r0, r5, asr #17
+	\opw	r0, r0
+	\ops	r9, r0
+	\opsw	r0, r9
+	\opw	r0, #129
+	\opw	r5, #129
+	.endm
+
+	mt	tst tsts tst.w tsts.w
+	mt	teq teqs teq.w teqs.w
+	mt	cmp cmps cmp.w cmps.w
+	mt	cmn cmns cmn.w cmns.w
+	mt	mov movs mov.w movs.w
+	mt	mvn mvns mvn.w mvns.w
+	.purgem mt
+
+mov16:
+	movw	r0, #0
+	movt	r0, #0
+	movw	r9, #0
+	movw	r0, #0x9000
+	movw	r0, #0x0800
+	movw	r0, #0x0500
+	movw	r0, #0x0081
+	movw	r0, #0xffff
+
+mrs_msr:
+	mrs	r0, CPSR
+	mrs	r0, SPSR
+	mrs	r9, CPSR_all
+	mrs	r9, SPSR_all
+
+	msr	CPSR_c, r0
+	msr	SPSR_c, r0
+	msr	CPSR_c, r9
+	msr	CPSR_x, r0
+	msr	CPSR_s, r0
+	msr	CPSR_f, r0
+
+mul:
+	mul	r0, r0, r0
+	mul	r0, r9, r0
+	mul	r0, r0, r9
+	mul	r0, r0
+	mul	r9, r0
+	muls	r5, r0
+	muls	r5, r0, r5
+	muls	r0, r5
+
+mull:
+	smull	r0, r1, r0, r0
+	umull	r0, r1, r0, r0
+	smlal	r0, r1, r0, r0
+	umlal	r0, r1, r0, r0
+	smull	r9, r0, r0, r0
+	smull	r0, r9, r0, r0
+	smull	r0, r1, r9, r0
+	smull	r0, r1, r0, r9
+
+neg:
+	negs	r0, r0
+	negs	r0, r5
+	negs	r5, r0
+	negs.w	r0, r0
+	negs.w	r5, r0
+	negs.w	r0, r5
+
+	neg	r0, r9
+	neg	r9, r0
+	negs	r0, r9
+	negs	r9, r0
+
+pkh:
+	pkhbt	r0, r0, r0
+	pkhbt	r9, r0, r0
+	pkhbt	r0, r9, r0
+	pkhbt	r0, r0, r9
+	pkhbt	r0, r0, r0, lsl #0x14
+	pkhbt	r0, r0, r0, lsl #3
+	pkhtb	r1, r2, r3
+	pkhtb	r1, r2, r3, asr #0x11
+
+push_pop:
+	push	{r0}
+	pop	{r0}
+	push	{r1,lr}
+	pop	{r1,pc}
+	push	{r8,r9,r10,r11,r12}
+	pop	{r8,r9,r10,r11,r12}
+
+qadd:
+	qadd16		r1, r2, r3
+	qadd8		r1, r2, r3
+	qaddsubx	r1, r2, r3
+	qsub16		r1, r2, r3
+	qsub8		r1, r2, r3
+	qsubaddx	r1, r2, r3
+	sadd16		r1, r2, r3
+	sadd8		r1, r2, r3
+	saddsubx	r1, r2, r3
+	ssub16		r1, r2, r3
+	ssub8		r1, r2, r3
+	ssubaddx	r1, r2, r3
+	shadd16		r1, r2, r3
+	shadd8		r1, r2, r3
+	shaddsubx	r1, r2, r3
+	shsub16		r1, r2, r3
+	shsub8		r1, r2, r3
+	shsubaddx	r1, r2, r3
+	uadd16		r1, r2, r3
+	uadd8		r1, r2, r3
+	uaddsubx	r1, r2, r3
+	usub16		r1, r2, r3
+	usub8		r1, r2, r3
+	usubaddx	r1, r2, r3
+	uhadd16		r1, r2, r3
+	uhadd8		r1, r2, r3
+	uhaddsubx	r1, r2, r3
+	uhsub16		r1, r2, r3
+	uhsub8		r1, r2, r3
+	uhsubaddx	r1, r2, r3
+	uqadd16		r1, r2, r3
+	uqadd8		r1, r2, r3
+	uqaddsubx	r1, r2, r3
+	uqsub16		r1, r2, r3
+	uqsub8		r1, r2, r3
+	uqsubaddx	r1, r2, r3
+	sel		r1, r2, r3
+
+rbit_rev:
+	.macro	rx op opw
+	\op	r0, r0
+	\opw	r0, r0
+	\op	r0, r5
+	\op	r5, r0
+	\op	r0, r9
+	\op	r9, r0
+	.endm
+
+	rx	rev rev.w
+	rx	rev16 rev16.w
+	rx	revsh revsh.w
+	rx	rbit rbit.w
+
+	.purgem rx
+
+shift:
+	.macro	sh op ops opw opsw
+	\ops	r0, #17		@ 16-bit format 1
+	\ops	r0, r0, #14
+	\ops	r5, r0, #17
+	\ops	r0, r5, #14
+	\ops	r0, r0		@ 16-bit format 2
+	\ops	r0, r5
+	\ops	r0, r0, r5
+	\op	r9, #17		@ 32-bit format 1
+	\op	r9, r9, #14
+	\ops	r0, r9, #17
+	\op	r9, r0, #14
+	\opw	r0, r0, r0	@ 32-bit format 2
+	\op	r9, r9
+	\ops	r9, r0
+	\op	r0, r9
+	\op	r0, r5
+	\ops	r0, r1, r2
+	.endm
+
+	sh	lsl lsls lsl.w lsls.w
+	sh	lsr lsrs lsr.w lsrs.w
+	sh	asr asrs asr.w asrs.w
+	sh	ror rors ror.w rors.w
+
+	.purgem sh
+
+smc:
+	smc	#0
+	smc	#0xabcd
+
+smla:
+	smlabb	r0, r0, r0, r0
+	smlabb	r9, r0, r0, r0
+	smlabb	r0, r9, r0, r0
+	smlabb	r0, r0, r9, r0
+	smlabb	r0, r0, r0, r9
+
+	smlatb	r0, r0, r0, r0
+	smlabt	r0, r0, r0, r0
+	smlatt	r0, r0, r0, r0
+	smlawb	r0, r0, r0, r0
+	smlawt	r0, r0, r0, r0
+	smlad	r0, r0, r0, r0
+	smladx	r0, r0, r0, r0
+	smlsd	r0, r0, r0, r0
+	smlsdx	r0, r0, r0, r0
+	smmla	r0, r0, r0, r0
+	smmlar	r0, r0, r0, r0
+	smmls	r0, r0, r0, r0
+	smmlsr	r0, r0, r0, r0
+	usada8	r0, r0, r0, r0
+
+smlal:
+	smlalbb	r0, r0, r0, r0
+	smlalbb	r9, r0, r0, r0
+	smlalbb	r0, r9, r0, r0
+	smlalbb	r0, r0, r9, r0
+	smlalbb	r0, r0, r0, r9
+
+	smlaltb	r0, r0, r0, r0
+	smlalbt	r0, r0, r0, r0
+	smlaltt	r0, r0, r0, r0
+	smlald	r0, r0, r0, r0
+	smlaldx	r0, r0, r0, r0
+	smlsld	r0, r0, r0, r0
+	smlsldx	r0, r0, r0, r0
+	umaal	r0, r0, r0, r0
+
+smul:
+	smulbb	r0, r0, r0
+	smulbb	r9, r0, r0
+	smulbb	r0, r9, r0
+	smulbb	r0, r0, r9
+
+	smultb	r0, r0, r0
+	smulbt	r0, r0, r0
+	smultt	r0, r0, r0
+	smulwb	r0, r0, r0
+	smulwt	r0, r0, r0
+	smmul	r0, r0, r0
+	smmulr	r0, r0, r0
+	smuad	r0, r0, r0
+	smuadx	r0, r0, r0
+	smusd	r0, r0, r0
+	smusdx	r0, r0, r0
+	usad8	r0, r0, r0
+
+sat:
+	ssat	r0, #1, r0
+	ssat	r0, #1, r0, lsl #0
+	ssat	r0, #1, r0, asr #0
+	ssat	r9, #1, r0
+	ssat	r0, #18, r0
+	ssat	r0, #1, r9
+	ssat	r0, #1, r0, lsl #0x1c
+	ssat	r0, #1, r0, asr #0x03
+
+	ssat16	r0, #1, r0
+	ssat16	r9, #1, r0
+	ssat16	r0, #10, r0
+	ssat16	r0, #1, r9
+
+	usat	r0, #0, r0
+	usat	r0, #0, r0, lsl #0
+	usat	r0, #0, r0, asr #0
+	usat	r9, #0, r0
+	usat	r0, #17, r0
+	usat	r0, #0, r9
+	usat	r0, #0, r0, lsl #0x1c
+	usat	r0, #0, r0, asr #0x03
+
+	usat16	r0, #0, r0
+	usat16	r9, #0, r0
+	usat16	r0, #9, r0
+	usat16	r0, #0, r9
+
+xt:
+	sxtb	r0, r0
+	sxtb	r0, r0, ror #0
+	sxtb	r5, r0
+	sxtb	r0, r5
+	sxtb.w	r1, r2
+	sxtb	r1, r2, ror #8
+	sxtb	r1, r2, ror #16
+	sxtb	r1, r2, ror #24
+
+	sxtb16	r1, r2
+	sxtb16	r8, r9
+	sxth	r1, r2
+	sxth	r8, r9
+	uxtb	r1, r2
+	uxtb	r8, r9
+	uxtb16	r1, r2
+	uxtb16	r8, r9
+	uxth	r1, r2
+	uxth	r8, r9
+
+xta:	
+	sxtab	r0, r0, r0
+	sxtab	r0, r0, r0, ror #0
+	sxtab	r9, r0, r0, ror #8
+	sxtab	r0, r9, r0, ror #16
+	sxtab	r0, r0, r9, ror #24
+
+	sxtab16	r1, r2, r3
+	sxtah	r1, r2, r3
+	uxtab	r1, r2, r3
+	uxtab16	r1, r2, r3
+	uxtah	r1, r2, r3
+
+	.macro	ldpcimm op
+	\op	r1, [pc, #0x2aa]
+	\op	r1, [pc, #0x155]
+	\op	r1, [pc, #-0x2aa]
+	\op	r1, [pc, #-0x155]
+	.endm
+	ldpcimm	ldrb
+	ldpcimm	ldrsb
+	ldpcimm	ldrh
+	ldpcimm	ldrsh
+	ldpcimm	ldr
+	addw r9, r0, #0
+	addw r6, pc, #0xfff
+	subw r6, r9, #0xa85
+	subw r6, r9, #0x57a
+	tbb [pc, r6]
+	tbb [r0, r9]
+	tbh [pc, r7, lsl #1]
+	tbh [r0, r8, lsl #1]
+
+	push	{r8}
+	pop	{r8}
+
+	ldmdb	r0!, {r7,r8,r10}
+	stmdb	r0!, {r7,r8,r10}
+
+	ldm	r0!, {r1, r2}
+	stm	r0!, {r1, r2}
+	ldm	r0, {r8, r9}
+	stm	r0, {r8, r9}
+	itttt eq
+	ldmeq	r0!, {r1, r2}
+	stmeq	r0!, {r1, r2}
+	ldmeq	r0, {r8, r9}
+	stmeq	r0, {r8, r9}
+	nop
diff --git a/gas/testsuite/gas/arm/thumbv6.d b/gas/testsuite/gas/arm/thumbv6.d
index b7c32904cbca..5dc821455dd8 100644
--- a/gas/testsuite/gas/arm/thumbv6.d
+++ b/gas/testsuite/gas/arm/thumbv6.d
@@ -7,12 +7,12 @@
 Disassembly of section .text:
 0+000 <[^>]*> b666 *	cpsie	ai
 0+002 <[^>]*> b675 *	cpsid	af
-0+004 <[^>]*> 4623 *	cpy	r3, r4
+0+004 <[^>]*> 4623 *	mov	r3, r4
 0+006 <[^>]*> ba3a *	rev	r2, r7
 0+008 <[^>]*> ba4d *	rev16	r5, r1
 0+00a <[^>]*> baf3 *	revsh	r3, r6
-0+00c <[^>]*> b658 *	setend	be	
-0+00e <[^>]*> b650 *	setend	le	
+0+00c <[^>]*> b658 *	setend	be
+0+00e <[^>]*> b650 *	setend	le
 0+010 <[^>]*> b208 *	sxth	r0, r1
 0+012 <[^>]*> b251 *	sxtb	r1, r2
 0+014 <[^>]*> b2a3 *	uxth	r3, r4
diff --git a/gas/testsuite/gas/arm/thumbv6k.d b/gas/testsuite/gas/arm/thumbv6k.d
new file mode 100644
index 000000000000..54a1d31ca638
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbv6k.d
@@ -0,0 +1,15 @@
+#name: THUMB V6K instructions
+#as: -march=armv6k -mthumb
+#objdump: -dr --prefix-addresses --show-raw-insn -M force-thumb
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> bf10 *	yield
+0+002 <[^>]*> bf20 *	wfe
+0+004 <[^>]*> bf30 *	wfi
+0+006 <[^>]*> bf40 *	sev
+0+008 <[^>]*> 46c0 *	nop[ \t]+\(mov r8, r8\)
+0+00a <[^>]*> 46c0 *	nop[ \t]+\(mov r8, r8\)
+0+00c <[^>]*> 46c0 *	nop[ \t]+\(mov r8, r8\)
+0+00e <[^>]*> 46c0 *	nop[ \t]+\(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumbv6k.s b/gas/testsuite/gas/arm/thumbv6k.s
new file mode 100644
index 000000000000..86198432396f
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumbv6k.s
@@ -0,0 +1,14 @@
+	.text
+	.align 0
+	.thumb
+label:
+	yield
+	wfe
+	wfi
+	sev
+	# arm-aout wants the segment padded to an 16-byte boundary;
+	# do this explicitly so it's consistent for all object formats.
+	nop
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/tls.d b/gas/testsuite/gas/arm/tls.d
new file mode 100644
index 000000000000..5b41109292cb
--- /dev/null
+++ b/gas/testsuite/gas/arm/tls.d
@@ -0,0 +1,25 @@
+#objdump: -dr
+#name: TLS
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# VxWorks needs a special variant of this file.
+#skip: *-*-vxworks*
+
+# Test generation of TLS relocations
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00+0 <main>:
+   0:	e1a00000 	nop			\(mov r0,r0\)
+   4:	e1a00000 	nop			\(mov r0,r0\)
+   8:	e1a0f00e 	mov	pc, lr
+   c:	00000000 	andeq	r0, r0, r0
+			c: R_ARM_TLS_GD32	a
+  10:	00000004 	andeq	r0, r0, r4
+			10: R_ARM_TLS_LDM32	b
+  14:	00000008 	andeq	r0, r0, r8
+			14: R_ARM_TLS_IE32	c
+  18:	00000000 	andeq	r0, r0, r0
+			18: R_ARM_TLS_LE32	d
diff --git a/gas/testsuite/gas/arm/tls.s b/gas/testsuite/gas/arm/tls.s
new file mode 100644
index 000000000000..48722a42b3a2
--- /dev/null
+++ b/gas/testsuite/gas/arm/tls.s
@@ -0,0 +1,14 @@
+	.text
+	.globl main
+	.type main, %function
+main:
+	nop
+.L2:
+	nop
+	mov	pc, lr
+
+.Lpool:
+	.word	a(tlsgd) + (. - .L2 - 8)
+	.word	b(tlsldm) + (. - .L2 - 8)
+	.word	c(gottpoff) + (. - .L2 - 8)
+	.word	d(tpoff)
diff --git a/gas/testsuite/gas/arm/tls_vxworks.d b/gas/testsuite/gas/arm/tls_vxworks.d
new file mode 100644
index 000000000000..ec80e652d297
--- /dev/null
+++ b/gas/testsuite/gas/arm/tls_vxworks.d
@@ -0,0 +1,30 @@
+#objdump: -dr
+#name: TLS
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# This is the VxWorks variant of this file.
+#source: tls.s
+#not-skip: *-*-vxworks*
+
+# Test generation of TLS relocations
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+
+00+0 <main>:
+   0:	e1a00000 	nop			\(mov r0,r0\)
+   4:	e1a00000 	nop			\(mov r0,r0\)
+   8:	e1a0f00e 	mov	pc, lr
+   c:	00000000 	andeq	r0, r0, r0
+			c: R_ARM_TLS_GD32	a
+# ??? The addend is appearing in both the RELA field and the
+# contents.  Shouldn't it be just one?  bfd_install_relocation
+# appears to write the addend into the contents unconditionally,
+# yet somehow this does not happen for the majority of relocations.
+  10:	00000004 	andeq	r0, r0, r4
+			10: R_ARM_TLS_LDM32	b\+0x4
+  14:	00000008 	andeq	r0, r0, r8
+			14: R_ARM_TLS_IE32	c\+0x8
+  18:	00000000 	andeq	r0, r0, r0
+			18: R_ARM_TLS_LE32	d
diff --git a/gas/testsuite/gas/arm/undefined.d b/gas/testsuite/gas/arm/undefined.d
new file mode 100644
index 000000000000..6a6149561cc3
--- /dev/null
+++ b/gas/testsuite/gas/arm/undefined.d
@@ -0,0 +1,4 @@
+#name: Undefined local label error
+# COFF and aout based ports use a different naming convention for local labels.
+#skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: undefined.l
diff --git a/gas/testsuite/gas/arm/undefined_coff.d b/gas/testsuite/gas/arm/undefined_coff.d
new file mode 100644
index 000000000000..ab0bbcdc6672
--- /dev/null
+++ b/gas/testsuite/gas/arm/undefined_coff.d
@@ -0,0 +1,4 @@
+#name: Undefined local label error
+# COFF and aout based ports use a different naming convention for local labels.
+#not-skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+#error-output: undefined_coff.l
diff --git a/gas/testsuite/gas/arm/undefined_coff.l b/gas/testsuite/gas/arm/undefined_coff.l
new file mode 100644
index 000000000000..1bd8dcfc9adc
--- /dev/null
+++ b/gas/testsuite/gas/arm/undefined_coff.l
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: undefined local label `Lval'
diff --git a/gas/testsuite/gas/arm/undefined_coff.s b/gas/testsuite/gas/arm/undefined_coff.s
new file mode 100644
index 000000000000..dd18dad28cb1
--- /dev/null
+++ b/gas/testsuite/gas/arm/undefined_coff.s
@@ -0,0 +1 @@
+	ldr	a1, Lval
diff --git a/gas/testsuite/gas/arm/unwind.d b/gas/testsuite/gas/arm/unwind.d
new file mode 100644
index 000000000000..cd4a7c7995c2
--- /dev/null
+++ b/gas/testsuite/gas/arm/unwind.d
@@ -0,0 +1,42 @@
+#objdump: -sr
+#name: Unwind table generation
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# VxWorks needs a special variant of this file.
+#skip: *-*-vxworks*
+
+.*:     file format.*
+
+RELOCATION RECORDS FOR \[.ARM.extab\]:
+OFFSET   TYPE              VALUE 
+0000000c R_ARM_PREL31      .text
+
+
+RELOCATION RECORDS FOR \[.ARM.exidx\]:
+OFFSET   TYPE              VALUE 
+00000000 R_ARM_PREL31      .text
+00000000 R_ARM_NONE        __aeabi_unwind_cpp_pr0
+00000008 R_ARM_PREL31      .text.*
+00000008 R_ARM_NONE        __aeabi_unwind_cpp_pr1
+0000000c R_ARM_PREL31      .ARM.extab
+00000010 R_ARM_PREL31      .text.*
+00000014 R_ARM_PREL31      .ARM.extab.*
+00000018 R_ARM_PREL31      .text.*
+0000001c R_ARM_PREL31      .ARM.extab.*
+00000020 R_ARM_PREL31      .text.*
+00000028 R_ARM_PREL31      .text.*
+
+
+Contents of section .text:
+ 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003)  .*
+ 0010 (04200520|20052004)                             .*
+Contents of section .ARM.extab:
+ 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000  .*
+ 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600)  .*
+ 0020 (b0b0c1c1|c1c1b0b0) 00000000                    .*
+Contents of section .ARM.exidx:
+ 0000 00000000 (b0b0a880 04000000|80a8b0b0 00000004) 00000000  .*
+ 0010 (08000000 0c000000 0c000000 1c000000|00000008 0000000c 0000000c 0000001c)  .*
+ 0020 (10000000 08849780 12000000 b00fb180|00000010 80978408 00000012 80b10fb0)  .*
+# Ignore .ARM.attributes section
+#...
diff --git a/gas/testsuite/gas/arm/unwind.s b/gas/testsuite/gas/arm/unwind.s
new file mode 100644
index 000000000000..7d0f126954f1
--- /dev/null
+++ b/gas/testsuite/gas/arm/unwind.s
@@ -0,0 +1,51 @@
+# Test generation of unwind tables
+	.text
+foo:	@ Simple function
+	.fnstart
+	.save {r4, lr}
+	mov r0, #0
+	.fnend
+foo1:	@ Typical frame pointer prologue
+	.fnstart
+	.movsp ip
+	@mov ip, sp
+	.pad #4
+	.save {fp, ip, lr}
+	@stmfd sp!, {fp, ip, lr, pc}
+	.setfp fp, ip, #4
+	@sub fp, ip, #4
+	mov r0, #1
+	.fnend
+foo2:	@ Custom personality routine
+	.fnstart
+	.save {r1, r4, r6, lr}
+	@stmfd {r1, r4, r6, lr}
+	mov r0, #2
+	.personality foo
+	.handlerdata
+	.word 42
+	.fnend
+foo3:	@ Saving iwmmxt registers
+	.fnstart
+	.save {wr11}
+	.save {wr10}
+	.save {wr10, wr11}
+	.save {wr0}
+	mov r0, #3
+	.fnend
+	.code 16
+foo4:	@ Thumb frame pointer
+	.fnstart
+	.save {r7, lr}
+	@push {r7, lr}
+	.setfp r7, sp
+	@mov r7, sp
+	.pad #8
+	@sub sp, sp, #8
+	mov r0, #4
+	.fnend
+foo5:	@ Save r0-r3 only.
+	.fnstart
+	.save {r0, r1, r2, r3}
+	mov r0, #5
+	.fnend
diff --git a/gas/testsuite/gas/arm/unwind_vxworks.d b/gas/testsuite/gas/arm/unwind_vxworks.d
new file mode 100644
index 000000000000..ccd16a65cc9a
--- /dev/null
+++ b/gas/testsuite/gas/arm/unwind_vxworks.d
@@ -0,0 +1,41 @@
+#objdump: -sr
+#name: Unwind table generation
+# This is the VxWorks variant of this file.
+#source: unwind.s
+#not-skip: *-*-vxworks*
+
+.*:     file format.*
+
+RELOCATION RECORDS FOR \[.ARM.extab\]:
+OFFSET   TYPE              VALUE 
+0000000c R_ARM_PREL31      .text
+
+
+RELOCATION RECORDS FOR \[.ARM.exidx\]:
+OFFSET   TYPE              VALUE 
+00000000 R_ARM_PREL31      .text
+00000000 R_ARM_NONE        __aeabi_unwind_cpp_pr0
+00000008 R_ARM_PREL31      .text.*\+0x00000004
+00000008 R_ARM_NONE        __aeabi_unwind_cpp_pr1
+0000000c R_ARM_PREL31      .ARM.extab
+00000010 R_ARM_PREL31      .text.*\+0x00000008
+00000014 R_ARM_PREL31      .ARM.extab.*\+0x0000000c
+00000018 R_ARM_PREL31      .text.*\+0x0000000c
+0000001c R_ARM_PREL31      .ARM.extab.*\+0x0000001c
+00000020 R_ARM_PREL31      .text.*\+0x00000010
+00000028 R_ARM_PREL31      .text.*\+0x00000012
+
+
+Contents of section .text:
+ 0000 (0000a0e3 0100a0e3 0200a0e3 0300a0e3|e3a00000 e3a00001 e3a00002 e3a00003)  .*
+ 0010 (04200520|20052004)                             .*
+Contents of section .ARM.extab:
+ 0000 (449b0181 b0b08086|81019b44 8680b0b0) 00000000 00000000  .*
+ 0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600)  .*
+ 0020 (b0b0c1c1|c1c1b0b0) 00000000                    .*
+Contents of section .ARM.exidx:
+ 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000  .*
+ 0010 00000000 00000000 00000000 00000000  .*
+ 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0)  .*
+# Ignore .ARM.attributes section
+#...
diff --git a/gas/testsuite/gas/arm/vfp-bad.d b/gas/testsuite/gas/arm/vfp-bad.d
new file mode 100644
index 000000000000..760c4d5c323a
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-bad.d
@@ -0,0 +1,3 @@
+#name: VFP errors
+#as: -mfpu=vfp
+#error-output: vfp-bad.l
diff --git a/gas/testsuite/gas/arm/vfp-bad.l b/gas/testsuite/gas/arm/vfp-bad.l
index 04bb04d4d7a9..7726e63180b1 100644
--- a/gas/testsuite/gas/arm/vfp-bad.l
+++ b/gas/testsuite/gas/arm/vfp-bad.l
@@ -1,9 +1,9 @@
 [^:]*: Assembler messages:
-[^:]*:4: Error: garbage following instruction -- `fstd d0,\[r0\],#8'
-[^:]*:5: Error: garbage following instruction -- `fstd d0,\[r0,#-8\]!'
-[^:]*:6: Error: garbage following instruction -- `fsts s0,\[r0\],#8'
-[^:]*:7: Error: garbage following instruction -- `fsts s0,\[r0,#-8\]!'
-[^:]*:8: Error: garbage following instruction -- `fldd d0,\[r0\],#8'
-[^:]*:9: Error: garbage following instruction -- `fldd d0,\[r0,#-8\]!'
-[^:]*:10: Error: garbage following instruction -- `flds s0,\[r0\],#8'
-[^:]*:11: Error: garbage following instruction -- `flds s0,\[r0,#-8\]!'
+[^:]*:4: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
+[^:]*:5: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
+[^:]*:6: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8'
+[^:]*:7: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!'
+[^:]*:8: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
+[^:]*:9: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
+[^:]*:10: Error: instruction does not support writeback -- `flds s0,\[r0\],#8'
+[^:]*:11: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'
diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.d b/gas/testsuite/gas/arm/vfp-bad_t2.d
new file mode 100644
index 000000000000..1ef83bab5df1
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-bad_t2.d
@@ -0,0 +1,3 @@
+#name: Thumb-2 VFP errors
+#as: -mfpu=vfp
+#error-output: vfp-bad_t2.l
diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.l b/gas/testsuite/gas/arm/vfp-bad_t2.l
new file mode 100644
index 000000000000..ecc0640b6cf1
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-bad_t2.l
@@ -0,0 +1,9 @@
+[^:]*: Assembler messages:
+[^:]*:7: Error: instruction does not support writeback -- `fstd d0,\[r0\],#8'
+[^:]*:8: Error: instruction does not support writeback -- `fstd d0,\[r0,#-8\]!'
+[^:]*:9: Error: instruction does not support writeback -- `fsts s0,\[r0\],#8'
+[^:]*:10: Error: instruction does not support writeback -- `fsts s0,\[r0,#-8\]!'
+[^:]*:11: Error: instruction does not support writeback -- `fldd d0,\[r0\],#8'
+[^:]*:12: Error: instruction does not support writeback -- `fldd d0,\[r0,#-8\]!'
+[^:]*:13: Error: instruction does not support writeback -- `flds s0,\[r0\],#8'
+[^:]*:14: Error: instruction does not support writeback -- `flds s0,\[r0,#-8\]!'
diff --git a/gas/testsuite/gas/arm/vfp-bad_t2.s b/gas/testsuite/gas/arm/vfp-bad_t2.s
new file mode 100644
index 000000000000..3b904b36dc27
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp-bad_t2.s
@@ -0,0 +1,14 @@
+        .global entry
+@ Same as vfp-bad.s, but for Thumb-2
+	.syntax unified
+	.thumb
+        .text
+entry:
+	fstd	d0, [r0], #8
+	fstd	d0, [r0, #-8]!
+	fsts	s0, [r0], #8
+	fsts	s0, [r0, #-8]!
+	fldd	d0, [r0], #8
+	fldd	d0, [r0, #-8]!
+	flds	s0, [r0], #8
+	flds	s0, [r0, #-8]!
diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d
new file mode 100644
index 000000000000..22c4fd6f01dc
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp1_t2.d
@@ -0,0 +1,205 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Thumb-2 VFP Double-precision instructions
+#as: -mfpu=vfp
+
+# Test the ARM VFP Double Precision instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eeb4 0bc0 	fcmped	d0, d0
+0+004 <[^>]*> eeb5 0bc0 	fcmpezd	d0
+0+008 <[^>]*> eeb4 0b40 	fcmpd	d0, d0
+0+00c <[^>]*> eeb5 0b40 	fcmpzd	d0
+0+010 <[^>]*> eeb0 0bc0 	fabsd	d0, d0
+0+014 <[^>]*> eeb0 0b40 	fcpyd	d0, d0
+0+018 <[^>]*> eeb1 0b40 	fnegd	d0, d0
+0+01c <[^>]*> eeb1 0bc0 	fsqrtd	d0, d0
+0+020 <[^>]*> ee30 0b00 	faddd	d0, d0, d0
+0+024 <[^>]*> ee80 0b00 	fdivd	d0, d0, d0
+0+028 <[^>]*> ee00 0b00 	fmacd	d0, d0, d0
+0+02c <[^>]*> ee10 0b00 	fmscd	d0, d0, d0
+0+030 <[^>]*> ee20 0b00 	fmuld	d0, d0, d0
+0+034 <[^>]*> ee00 0b40 	fnmacd	d0, d0, d0
+0+038 <[^>]*> ee10 0b40 	fnmscd	d0, d0, d0
+0+03c <[^>]*> ee20 0b40 	fnmuld	d0, d0, d0
+0+040 <[^>]*> ee30 0b40 	fsubd	d0, d0, d0
+0+044 <[^>]*> ed90 0b00 	fldd	d0, \[r0\]
+0+048 <[^>]*> ed80 0b00 	fstd	d0, \[r0\]
+0+04c <[^>]*> ec90 0b02 	fldmiad	r0, {d0}
+0+050 <[^>]*> ec90 0b02 	fldmiad	r0, {d0}
+0+054 <[^>]*> ecb0 0b02 	fldmiad	r0!, {d0}
+0+058 <[^>]*> ecb0 0b02 	fldmiad	r0!, {d0}
+0+05c <[^>]*> ed30 0b02 	fldmdbd	r0!, {d0}
+0+060 <[^>]*> ed30 0b02 	fldmdbd	r0!, {d0}
+0+064 <[^>]*> ec80 0b02 	fstmiad	r0, {d0}
+0+068 <[^>]*> ec80 0b02 	fstmiad	r0, {d0}
+0+06c <[^>]*> eca0 0b02 	fstmiad	r0!, {d0}
+0+070 <[^>]*> eca0 0b02 	fstmiad	r0!, {d0}
+0+074 <[^>]*> ed20 0b02 	fstmdbd	r0!, {d0}
+0+078 <[^>]*> ed20 0b02 	fstmdbd	r0!, {d0}
+0+07c <[^>]*> eeb8 0bc0 	fsitod	d0, s0
+0+080 <[^>]*> eeb8 0b40 	fuitod	d0, s0
+0+084 <[^>]*> eebd 0b40 	ftosid	s0, d0
+0+088 <[^>]*> eebd 0bc0 	ftosizd	s0, d0
+0+08c <[^>]*> eebc 0b40 	ftouid	s0, d0
+0+090 <[^>]*> eebc 0bc0 	ftouizd	s0, d0
+0+094 <[^>]*> eeb7 0ac0 	fcvtds	d0, s0
+0+098 <[^>]*> eeb7 0bc0 	fcvtsd	s0, d0
+0+09c <[^>]*> ee30 0b10 	fmrdh	r0, d0
+0+0a0 <[^>]*> ee10 0b10 	fmrdl	r0, d0
+0+0a4 <[^>]*> ee20 0b10 	fmdhr	d0, r0
+0+0a8 <[^>]*> ee00 0b10 	fmdlr	d0, r0
+0+0ac <[^>]*> eeb5 1b40 	fcmpzd	d1
+0+0b0 <[^>]*> eeb5 2b40 	fcmpzd	d2
+0+0b4 <[^>]*> eeb5 fb40 	fcmpzd	d15
+0+0b8 <[^>]*> eeb4 0b41 	fcmpd	d0, d1
+0+0bc <[^>]*> eeb4 0b42 	fcmpd	d0, d2
+0+0c0 <[^>]*> eeb4 0b4f 	fcmpd	d0, d15
+0+0c4 <[^>]*> eeb4 1b40 	fcmpd	d1, d0
+0+0c8 <[^>]*> eeb4 2b40 	fcmpd	d2, d0
+0+0cc <[^>]*> eeb4 fb40 	fcmpd	d15, d0
+0+0d0 <[^>]*> eeb4 5b4c 	fcmpd	d5, d12
+0+0d4 <[^>]*> eeb1 0b41 	fnegd	d0, d1
+0+0d8 <[^>]*> eeb1 0b42 	fnegd	d0, d2
+0+0dc <[^>]*> eeb1 0b4f 	fnegd	d0, d15
+0+0e0 <[^>]*> eeb1 1b40 	fnegd	d1, d0
+0+0e4 <[^>]*> eeb1 2b40 	fnegd	d2, d0
+0+0e8 <[^>]*> eeb1 fb40 	fnegd	d15, d0
+0+0ec <[^>]*> eeb1 cb45 	fnegd	d12, d5
+0+0f0 <[^>]*> ee30 0b01 	faddd	d0, d0, d1
+0+0f4 <[^>]*> ee30 0b02 	faddd	d0, d0, d2
+0+0f8 <[^>]*> ee30 0b0f 	faddd	d0, d0, d15
+0+0fc <[^>]*> ee31 0b00 	faddd	d0, d1, d0
+0+100 <[^>]*> ee32 0b00 	faddd	d0, d2, d0
+0+104 <[^>]*> ee3f 0b00 	faddd	d0, d15, d0
+0+108 <[^>]*> ee30 1b00 	faddd	d1, d0, d0
+0+10c <[^>]*> ee30 2b00 	faddd	d2, d0, d0
+0+110 <[^>]*> ee30 fb00 	faddd	d15, d0, d0
+0+114 <[^>]*> ee39 cb05 	faddd	d12, d9, d5
+0+118 <[^>]*> eeb7 0ae0 	fcvtds	d0, s1
+0+11c <[^>]*> eeb7 0ac1 	fcvtds	d0, s2
+0+120 <[^>]*> eeb7 0aef 	fcvtds	d0, s31
+0+124 <[^>]*> eeb7 1ac0 	fcvtds	d1, s0
+0+128 <[^>]*> eeb7 2ac0 	fcvtds	d2, s0
+0+12c <[^>]*> eeb7 fac0 	fcvtds	d15, s0
+0+130 <[^>]*> eef7 0bc0 	fcvtsd	s1, d0
+0+134 <[^>]*> eeb7 1bc0 	fcvtsd	s2, d0
+0+138 <[^>]*> eef7 fbc0 	fcvtsd	s31, d0
+0+13c <[^>]*> eeb7 0bc1 	fcvtsd	s0, d1
+0+140 <[^>]*> eeb7 0bc2 	fcvtsd	s0, d2
+0+144 <[^>]*> eeb7 0bcf 	fcvtsd	s0, d15
+0+148 <[^>]*> ee30 1b10 	fmrdh	r1, d0
+0+14c <[^>]*> ee30 eb10 	fmrdh	lr, d0
+0+150 <[^>]*> ee31 0b10 	fmrdh	r0, d1
+0+154 <[^>]*> ee32 0b10 	fmrdh	r0, d2
+0+158 <[^>]*> ee3f 0b10 	fmrdh	r0, d15
+0+15c <[^>]*> ee10 1b10 	fmrdl	r1, d0
+0+160 <[^>]*> ee10 eb10 	fmrdl	lr, d0
+0+164 <[^>]*> ee11 0b10 	fmrdl	r0, d1
+0+168 <[^>]*> ee12 0b10 	fmrdl	r0, d2
+0+16c <[^>]*> ee1f 0b10 	fmrdl	r0, d15
+0+170 <[^>]*> ee20 1b10 	fmdhr	d0, r1
+0+174 <[^>]*> ee20 eb10 	fmdhr	d0, lr
+0+178 <[^>]*> ee21 0b10 	fmdhr	d1, r0
+0+17c <[^>]*> ee22 0b10 	fmdhr	d2, r0
+0+180 <[^>]*> ee2f 0b10 	fmdhr	d15, r0
+0+184 <[^>]*> ee00 1b10 	fmdlr	d0, r1
+0+188 <[^>]*> ee00 eb10 	fmdlr	d0, lr
+0+18c <[^>]*> ee01 0b10 	fmdlr	d1, r0
+0+190 <[^>]*> ee02 0b10 	fmdlr	d2, r0
+0+194 <[^>]*> ee0f 0b10 	fmdlr	d15, r0
+0+198 <[^>]*> ed91 0b00 	fldd	d0, \[r1\]
+0+19c <[^>]*> ed9e 0b00 	fldd	d0, \[lr\]
+0+1a0 <[^>]*> ed90 0b00 	fldd	d0, \[r0\]
+0+1a4 <[^>]*> ed90 0bff 	fldd	d0, \[r0, #1020\]
+0+1a8 <[^>]*> ed10 0bff 	fldd	d0, \[r0, #-1020\]
+0+1ac <[^>]*> ed90 1b00 	fldd	d1, \[r0\]
+0+1b0 <[^>]*> ed90 2b00 	fldd	d2, \[r0\]
+0+1b4 <[^>]*> ed90 fb00 	fldd	d15, \[r0\]
+0+1b8 <[^>]*> ed8c cbc9 	fstd	d12, \[ip, #804\]
+0+1bc <[^>]*> ec90 1b02 	fldmiad	r0, {d1}
+0+1c0 <[^>]*> ec90 2b02 	fldmiad	r0, {d2}
+0+1c4 <[^>]*> ec90 fb02 	fldmiad	r0, {d15}
+0+1c8 <[^>]*> ec90 0b04 	fldmiad	r0, {d0-d1}
+0+1cc <[^>]*> ec90 0b06 	fldmiad	r0, {d0-d2}
+0+1d0 <[^>]*> ec90 0b20 	fldmiad	r0, {d0-d15}
+0+1d4 <[^>]*> ec90 1b1e 	fldmiad	r0, {d1-d15}
+0+1d8 <[^>]*> ec90 2b1c 	fldmiad	r0, {d2-d15}
+0+1dc <[^>]*> ec90 eb04 	fldmiad	r0, {d14-d15}
+0+1e0 <[^>]*> ec91 0b02 	fldmiad	r1, {d0}
+0+1e4 <[^>]*> ec9e 0b02 	fldmiad	lr, {d0}
+0+1e8 <[^>]*> eeb5 0b40 	fcmpzd	d0
+0+1ec <[^>]*> eeb5 1b40 	fcmpzd	d1
+0+1f0 <[^>]*> eeb5 2b40 	fcmpzd	d2
+0+1f4 <[^>]*> eeb5 3b40 	fcmpzd	d3
+0+1f8 <[^>]*> eeb5 4b40 	fcmpzd	d4
+0+1fc <[^>]*> eeb5 5b40 	fcmpzd	d5
+0+200 <[^>]*> eeb5 6b40 	fcmpzd	d6
+0+204 <[^>]*> eeb5 7b40 	fcmpzd	d7
+0+208 <[^>]*> eeb5 8b40 	fcmpzd	d8
+0+20c <[^>]*> eeb5 9b40 	fcmpzd	d9
+0+210 <[^>]*> eeb5 ab40 	fcmpzd	d10
+0+214 <[^>]*> eeb5 bb40 	fcmpzd	d11
+0+218 <[^>]*> eeb5 cb40 	fcmpzd	d12
+0+21c <[^>]*> eeb5 db40 	fcmpzd	d13
+0+220 <[^>]*> eeb5 eb40 	fcmpzd	d14
+0+224 <[^>]*> eeb5 fb40 	fcmpzd	d15
+# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
+0+228 <[^>]*> bf01      	itttt	eq
+0+22a <[^>]*> eeb4 1bcf 	fcmped(eq|)	d1, d15
+0+22e <[^>]*> eeb5 2bc0 	fcmpezd(eq|)	d2
+0+232 <[^>]*> eeb4 3b4e 	fcmpd(eq|)	d3, d14
+0+236 <[^>]*> eeb5 4b40 	fcmpzd(eq|)	d4
+0+23a <[^>]*> bf01      	itttt	eq
+0+23c <[^>]*> eeb0 5bcd 	fabsd(eq|)	d5, d13
+0+240 <[^>]*> eeb0 6b4c 	fcpyd(eq|)	d6, d12
+0+244 <[^>]*> eeb1 7b4b 	fnegd(eq|)	d7, d11
+0+248 <[^>]*> eeb1 8bca 	fsqrtd(eq|)	d8, d10
+0+24c <[^>]*> bf01      	itttt	eq
+0+24e <[^>]*> ee31 9b0f 	faddd(eq|)	d9, d1, d15
+0+252 <[^>]*> ee83 2b0e 	fdivd(eq|)	d2, d3, d14
+0+256 <[^>]*> ee0d 4b0c 	fmacd(eq|)	d4, d13, d12
+0+25a <[^>]*> ee16 5b0b 	fmscd(eq|)	d5, d6, d11
+0+25e <[^>]*> bf01      	itttt	eq
+0+260 <[^>]*> ee2a 7b09 	fmuld(eq|)	d7, d10, d9
+0+264 <[^>]*> ee09 8b4a 	fnmacd(eq|)	d8, d9, d10
+0+268 <[^>]*> ee16 7b4b 	fnmscd(eq|)	d7, d6, d11
+0+26c <[^>]*> ee24 5b4c 	fnmuld(eq|)	d5, d4, d12
+0+270 <[^>]*> bf02      	ittt	eq
+0+272 <[^>]*> ee3d 3b4e 	fsubd(eq|)	d3, d13, d14
+0+276 <[^>]*> ed95 2b00 	fldd(eq|)	d2, \[r5\]
+0+27a <[^>]*> ed8c 1b00 	fstd(eq|)	d1, \[ip\]
+0+27e <[^>]*> bf01      	itttt	eq
+0+280 <[^>]*> ec91 1b02 	fldmiad(eq|)	r1, {d1}
+0+284 <[^>]*> ec92 2b02 	fldmiad(eq|)	r2, {d2}
+0+288 <[^>]*> ecb3 3b02 	fldmiad(eq|)	r3!, {d3}
+0+28c <[^>]*> ecb4 4b02 	fldmiad(eq|)	r4!, {d4}
+0+290 <[^>]*> bf01      	itttt	eq
+0+292 <[^>]*> ed35 5b02 	fldmdbd(eq|)	r5!, {d5}
+0+296 <[^>]*> ed36 6b02 	fldmdbd(eq|)	r6!, {d6}
+0+29a <[^>]*> ec87 fb02 	fstmiad(eq|)	r7, {d15}
+0+29e <[^>]*> ec88 eb02 	fstmiad(eq|)	r8, {d14}
+0+2a2 <[^>]*> bf01      	itttt	eq
+0+2a4 <[^>]*> eca9 db02 	fstmiad(eq|)	r9!, {d13}
+0+2a8 <[^>]*> ecaa cb02 	fstmiad(eq|)	sl!, {d12}
+0+2ac <[^>]*> ed2b bb02 	fstmdbd(eq|)	fp!, {d11}
+0+2b0 <[^>]*> ed2c ab02 	fstmdbd(eq|)	ip!, {d10}
+0+2b4 <[^>]*> bf01      	itttt	eq
+0+2b6 <[^>]*> eeb8 fbe0 	fsitod(eq|)	d15, s1
+0+2ba <[^>]*> eeb8 1b6f 	fuitod(eq|)	d1, s31
+0+2be <[^>]*> eefd 0b4f 	ftosid(eq|)	s1, d15
+0+2c2 <[^>]*> eefd fbc2 	ftosizd(eq|)	s31, d2
+0+2c6 <[^>]*> bf01      	itttt	eq
+0+2c8 <[^>]*> eefc 7b42 	ftouid(eq|)	s15, d2
+0+2cc <[^>]*> eefc 5bc3 	ftouizd(eq|)	s11, d3
+0+2d0 <[^>]*> eeb7 1ac5 	fcvtds(eq|)	d1, s10
+0+2d4 <[^>]*> eef7 5bc1 	fcvtsd(eq|)	s11, d1
+0+2d8 <[^>]*> bf01      	itttt	eq
+0+2da <[^>]*> ee31 8b10 	fmrdh(eq|)	r8, d1
+0+2de <[^>]*> ee1f 7b10 	fmrdl(eq|)	r7, d15
+0+2e2 <[^>]*> ee21 fb10 	fmdhr(eq|)	d1, pc
+0+2e6 <[^>]*> ee0f 1b10 	fmdlr(eq|)	d15, r1
+0+2ea <[^>]*> bf00      	nop
+0+2ec <[^>]*> bf00      	nop
+0+2ee <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/vfp1_t2.s b/gas/testsuite/gas/arm/vfp1_t2.s
new file mode 100644
index 000000000000..dd596cb56913
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp1_t2.s
@@ -0,0 +1,298 @@
+@ VFP Instructions for D variants (Double precision)
+@ Same as vfp1.s, but for Thumb-2
+	.syntax unified
+	.thumb
+	.text
+	.global F
+F:
+	@ First we test the basic syntax and bit patterns of the opcodes.
+	@ Most of these tests deliberatly use d0/r0 to avoid setting
+	@ any more bits than necessary.
+
+	@ Comparison operations
+
+	fcmped	d0, d0
+	fcmpezd	d0
+	fcmpd	d0, d0
+	fcmpzd	d0
+
+	@ Monadic data operations
+
+	fabsd	d0, d0
+	fcpyd	d0, d0
+	fnegd	d0, d0
+	fsqrtd	d0, d0
+
+	@ Dyadic data operations
+
+	faddd	d0, d0, d0
+	fdivd	d0, d0, d0
+	fmacd	d0, d0, d0
+	fmscd	d0, d0, d0
+	fmuld	d0, d0, d0
+	fnmacd	d0, d0, d0
+	fnmscd	d0, d0, d0
+	fnmuld	d0, d0, d0
+	fsubd	d0, d0, d0
+
+	@ Load/store operations
+
+	fldd	d0, [r0]
+	fstd	d0, [r0]
+
+	@ Load/store multiple operations
+
+	fldmiad	r0, {d0}
+	fldmfdd	r0, {d0}
+	fldmiad	r0!, {d0}
+	fldmfdd	r0!, {d0}
+	fldmdbd	r0!, {d0}
+	fldmead	r0!, {d0}
+
+	fstmiad	r0, {d0}
+	fstmead	r0, {d0}
+	fstmiad	r0!, {d0}
+	fstmead	r0!, {d0}
+	fstmdbd	r0!, {d0}
+	fstmfdd	r0!, {d0}
+
+	@ Conversion operations
+
+	fsitod	d0, s0
+	fuitod	d0, s0
+
+	ftosid	s0, d0
+	ftosizd	s0, d0
+	ftouid	s0, d0
+	ftouizd	s0, d0
+
+	fcvtds	d0, s0
+	fcvtsd	s0, d0
+	
+	@ ARM from VFP operations
+
+	fmrdh	r0, d0
+	fmrdl	r0, d0
+
+	@ VFP From ARM operations
+
+	fmdhr	d0, r0
+	fmdlr	d0, r0
+
+	@ Now we test that the register fields are updated correctly for
+	@ each class of instruction.
+
+	@ Single register operations (compare-zero):
+
+	fcmpzd	d1
+	fcmpzd	d2
+	fcmpzd	d15
+
+	@ Two register comparison operations:
+
+	fcmpd	d0, d1
+	fcmpd	d0, d2
+	fcmpd	d0, d15
+	fcmpd	d1, d0
+	fcmpd	d2, d0
+	fcmpd	d15, d0
+	fcmpd	d5, d12
+
+	@ Two register data operations (monadic)
+
+	fnegd	d0, d1
+	fnegd	d0, d2
+	fnegd	d0, d15
+	fnegd	d1, d0
+	fnegd	d2, d0
+	fnegd	d15, d0
+	fnegd	d12, d5
+	
+	@ Three register data operations (dyadic)
+
+	faddd	d0, d0, d1
+	faddd	d0, d0, d2
+	faddd	d0, d0, d15
+	faddd	d0, d1, d0
+	faddd	d0, d2, d0
+	faddd	d0, d15, d0
+	faddd	d1, d0, d0
+	faddd	d2, d0, d0
+	faddd	d15, d0, d0
+	faddd	d12, d9, d5
+
+	@ Conversion operations
+
+	fcvtds	d0, s1
+	fcvtds	d0, s2
+	fcvtds	d0, s31
+	fcvtds	d1, s0
+	fcvtds	d2, s0
+	fcvtds	d15, s0
+	fcvtsd	s1, d0
+	fcvtsd	s2, d0
+	fcvtsd	s31, d0
+	fcvtsd	s0, d1
+	fcvtsd	s0, d2
+	fcvtsd	s0, d15
+
+	@ Move to VFP from ARM
+
+	fmrdh	r1, d0
+	fmrdh	r14, d0
+	fmrdh	r0, d1
+	fmrdh	r0, d2
+	fmrdh	r0, d15
+	fmrdl	r1, d0
+	fmrdl	r14, d0
+	fmrdl	r0, d1
+	fmrdl	r0, d2
+	fmrdl	r0, d15
+
+	@ Move to ARM from VFP
+
+	fmdhr	d0, r1
+	fmdhr	d0, r14
+	fmdhr	d1, r0
+	fmdhr	d2, r0
+	fmdhr	d15, r0
+	fmdlr	d0, r1
+	fmdlr	d0, r14
+	fmdlr	d1, r0
+	fmdlr	d2, r0
+	fmdlr	d15, r0
+
+	@ Load/store operations
+
+	fldd	d0, [r1]
+	fldd	d0, [r14]
+	fldd	d0, [r0, #0]
+	fldd	d0, [r0, #1020]
+	fldd	d0, [r0, #-1020]
+	fldd	d1, [r0]
+	fldd	d2, [r0]
+	fldd	d15, [r0]
+	fstd	d12, [r12, #804]
+
+	@ Load/store multiple operations
+
+	fldmiad	r0, {d1}
+	fldmiad	r0, {d2}
+	fldmiad	r0, {d15}
+	fldmiad	r0, {d0-d1}
+	fldmiad	r0, {d0-d2}
+	fldmiad	r0, {d0-d15}
+	fldmiad	r0, {d1-d15}
+	fldmiad	r0, {d2-d15}
+	fldmiad	r0, {d14-d15}
+	fldmiad	r1, {d0}
+	fldmiad	r14, {d0}
+
+	@ Check that we assemble all the register names correctly
+
+	fcmpzd	d0
+	fcmpzd	d1
+	fcmpzd	d2
+	fcmpzd	d3
+	fcmpzd	d4
+	fcmpzd	d5
+	fcmpzd	d6
+	fcmpzd	d7
+	fcmpzd	d8
+	fcmpzd	d9
+	fcmpzd	d10
+	fcmpzd	d11
+	fcmpzd	d12
+	fcmpzd	d13
+	fcmpzd	d14
+	fcmpzd	d15
+
+	@ Now we check the placement of the conditional execution substring.
+	@ On VFP this is always at the end of the instruction.
+	
+	@ Comparison operations
+
+	itttt eq
+	fcmpedeq	d1, d15
+	fcmpezdeq	d2
+	fcmpdeq	d3, d14
+	fcmpzdeq	d4
+
+	@ Monadic data operations
+
+	itttt eq
+	fabsdeq	d5, d13
+	fcpydeq	d6, d12
+	fnegdeq	d7, d11
+	fsqrtdeq	d8, d10
+
+	@ Dyadic data operations
+
+	itttt eq
+	fadddeq	d9, d1, d15
+	fdivdeq	d2, d3, d14
+	fmacdeq	d4, d13, d12
+	fmscdeq	d5, d6, d11
+	itttt eq
+	fmuldeq	d7, d10, d9
+	fnmacdeq	d8, d9, d10
+	fnmscdeq	d7, d6, d11
+	fnmuldeq	d5, d4, d12
+	ittt eq
+	fsubdeq	d3, d13, d14
+
+	@ Load/store operations
+
+	flddeq	d2, [r5]
+	fstdeq	d1, [r12]
+
+	@ Load/store multiple operations
+
+	itttt eq
+	fldmiadeq	r1, {d1}
+	fldmfddeq	r2, {d2}
+	fldmiadeq	r3!, {d3}
+	fldmfddeq	r4!, {d4}
+	itttt eq
+	fldmdbdeq	r5!, {d5}
+	fldmeadeq	r6!, {d6}
+
+	fstmiadeq	r7, {d15}
+	fstmeadeq	r8, {d14}
+	itttt eq
+	fstmiadeq	r9!, {d13}
+	fstmeadeq	r10!, {d12}
+	fstmdbdeq	r11!, {d11}
+	fstmfddeq	r12!, {d10}
+
+	@ Conversion operations
+
+	itttt eq
+	fsitodeq	d15, s1
+	fuitodeq	d1, s31
+
+	ftosideq	s1, d15
+	ftosizdeq	s31, d2
+	itttt eq
+	ftouideq	s15, d2
+	ftouizdeq	s11, d3
+
+	fcvtdseq	d1, s10
+	fcvtsdeq	s11, d1
+	
+	@ ARM from VFP operations
+
+	itttt eq
+	fmrdheq	r8, d1
+	fmrdleq	r7, d15
+
+	@ VFP From ARM operations
+
+	fmdhreq	d1, r15
+	fmdlreq	d15, r1
+
+	# Add three nop instructions to ensure that the
+	# output is 32-byte aligned as required for arm-aout.
+	nop
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/vfp1xD.d b/gas/testsuite/gas/arm/vfp1xD.d
index ac4e4f92747a..096b46c86e4c 100644
--- a/gas/testsuite/gas/arm/vfp1xD.d
+++ b/gas/testsuite/gas/arm/vfp1xD.d
@@ -82,16 +82,16 @@ Disassembly of section .text:
 0+120 <[^>]*> eeb11a40 	fnegs	s2, s0
 0+124 <[^>]*> eef1fa40 	fnegs	s31, s0
 0+128 <[^>]*> eeb16a6a 	fnegs	s12, s21
-0+12c <[^>]*> ee300a20 	fadds	s0, s0, s0
-0+130 <[^>]*> ee300a01 	fadds	s0, s0, s0
-0+134 <[^>]*> ee300a2f 	fadds	s0, s0, s0
+0+12c <[^>]*> ee300a20 	fadds	s0, s0, s1
+0+130 <[^>]*> ee300a01 	fadds	s0, s0, s2
+0+134 <[^>]*> ee300a2f 	fadds	s0, s0, s31
 0+138 <[^>]*> ee300a80 	fadds	s0, s1, s0
 0+13c <[^>]*> ee310a00 	fadds	s0, s2, s0
 0+140 <[^>]*> ee3f0a80 	fadds	s0, s31, s0
-0+144 <[^>]*> ee700a00 	fadds	s1, s0, s1
-0+148 <[^>]*> ee301a00 	fadds	s2, s0, s2
-0+14c <[^>]*> ee70fa00 	fadds	s31, s0, s31
-0+150 <[^>]*> ee3a6aa2 	fadds	s12, s21, s12
+0+144 <[^>]*> ee700a00 	fadds	s1, s0, s0
+0+148 <[^>]*> ee301a00 	fadds	s2, s0, s0
+0+14c <[^>]*> ee70fa00 	fadds	s31, s0, s0
+0+150 <[^>]*> ee3a6aa2 	fadds	s12, s21, s5
 0+154 <[^>]*> eeb80ae0 	fsitos	s0, s1
 0+158 <[^>]*> eeb80ac1 	fsitos	s0, s2
 0+15c <[^>]*> eeb80aef 	fsitos	s0, s31
@@ -194,7 +194,7 @@ Disassembly of section .text:
 0+2e0 <[^>]*> 0ef0fa69 	fcpyseq	s31, s19
 0+2e4 <[^>]*> 0eb1aa44 	fnegseq	s20, s8
 0+2e8 <[^>]*> 0ef12ae3 	fsqrtseq	s5, s7
-0+2ec <[^>]*> 0e323a82 	faddseq	s6, s5, s6
+0+2ec <[^>]*> 0e323a82 	faddseq	s6, s5, s4
 0+2f0 <[^>]*> 0ec11a20 	fdivseq	s3, s2, s1
 0+2f4 <[^>]*> 0e4ffa2e 	fmacseq	s31, s30, s29
 0+2f8 <[^>]*> 0e1dea8d 	fmscseq	s28, s27, s26
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
new file mode 100644
index 000000000000..327383d01c5b
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
@@ -0,0 +1,258 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Thumb-2 VFP Single-precision instructions
+#as: -mfpu=vfpxd
+
+# Test the ARM VFP Single Precision instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> eef1 fa10 	fmstat
+0+004 <[^>]*> eeb4 0ac0 	fcmpes	s0, s0
+0+008 <[^>]*> eeb5 0ac0 	fcmpezs	s0
+0+00c <[^>]*> eeb4 0a40 	fcmps	s0, s0
+0+010 <[^>]*> eeb5 0a40 	fcmpzs	s0
+0+014 <[^>]*> eeb0 0ac0 	fabss	s0, s0
+0+018 <[^>]*> eeb0 0a40 	fcpys	s0, s0
+0+01c <[^>]*> eeb1 0a40 	fnegs	s0, s0
+0+020 <[^>]*> eeb1 0ac0 	fsqrts	s0, s0
+0+024 <[^>]*> ee30 0a00 	fadds	s0, s0, s0
+0+028 <[^>]*> ee80 0a00 	fdivs	s0, s0, s0
+0+02c <[^>]*> ee00 0a00 	fmacs	s0, s0, s0
+0+030 <[^>]*> ee10 0a00 	fmscs	s0, s0, s0
+0+034 <[^>]*> ee20 0a00 	fmuls	s0, s0, s0
+0+038 <[^>]*> ee00 0a40 	fnmacs	s0, s0, s0
+0+03c <[^>]*> ee10 0a40 	fnmscs	s0, s0, s0
+0+040 <[^>]*> ee20 0a40 	fnmuls	s0, s0, s0
+0+044 <[^>]*> ee30 0a40 	fsubs	s0, s0, s0
+0+048 <[^>]*> ed90 0a00 	flds	s0, \[r0\]
+0+04c <[^>]*> ed80 0a00 	fsts	s0, \[r0\]
+0+050 <[^>]*> ec90 0a01 	fldmias	r0, {s0}
+0+054 <[^>]*> ec90 0a01 	fldmias	r0, {s0}
+0+058 <[^>]*> ecb0 0a01 	fldmias	r0!, {s0}
+0+05c <[^>]*> ecb0 0a01 	fldmias	r0!, {s0}
+0+060 <[^>]*> ed30 0a01 	fldmdbs	r0!, {s0}
+0+064 <[^>]*> ed30 0a01 	fldmdbs	r0!, {s0}
+0+068 <[^>]*> ec90 0b03 	fldmiax	r0, {d0}
+0+06c <[^>]*> ec90 0b03 	fldmiax	r0, {d0}
+0+070 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}
+0+074 <[^>]*> ecb0 0b03 	fldmiax	r0!, {d0}
+0+078 <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}
+0+07c <[^>]*> ed30 0b03 	fldmdbx	r0!, {d0}
+0+080 <[^>]*> ec80 0a01 	fstmias	r0, {s0}
+0+084 <[^>]*> ec80 0a01 	fstmias	r0, {s0}
+0+088 <[^>]*> eca0 0a01 	fstmias	r0!, {s0}
+0+08c <[^>]*> eca0 0a01 	fstmias	r0!, {s0}
+0+090 <[^>]*> ed20 0a01 	fstmdbs	r0!, {s0}
+0+094 <[^>]*> ed20 0a01 	fstmdbs	r0!, {s0}
+0+098 <[^>]*> ec80 0b03 	fstmiax	r0, {d0}
+0+09c <[^>]*> ec80 0b03 	fstmiax	r0, {d0}
+0+0a0 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}
+0+0a4 <[^>]*> eca0 0b03 	fstmiax	r0!, {d0}
+0+0a8 <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}
+0+0ac <[^>]*> ed20 0b03 	fstmdbx	r0!, {d0}
+0+0b0 <[^>]*> eeb8 0ac0 	fsitos	s0, s0
+0+0b4 <[^>]*> eeb8 0a40 	fuitos	s0, s0
+0+0b8 <[^>]*> eebd 0a40 	ftosis	s0, s0
+0+0bc <[^>]*> eebd 0ac0 	ftosizs	s0, s0
+0+0c0 <[^>]*> eebc 0a40 	ftouis	s0, s0
+0+0c4 <[^>]*> eebc 0ac0 	ftouizs	s0, s0
+0+0c8 <[^>]*> ee10 0a10 	fmrs	r0, s0
+0+0cc <[^>]*> eef0 0a10 	fmrx	r0, fpsid
+0+0d0 <[^>]*> eef1 0a10 	fmrx	r0, fpscr
+0+0d4 <[^>]*> eef8 0a10 	fmrx	r0, fpexc
+0+0d8 <[^>]*> ee00 0a10 	fmsr	s0, r0
+0+0dc <[^>]*> eee0 0a10 	fmxr	fpsid, r0
+0+0e0 <[^>]*> eee1 0a10 	fmxr	fpscr, r0
+0+0e4 <[^>]*> eee8 0a10 	fmxr	fpexc, r0
+0+0e8 <[^>]*> eef5 0a40 	fcmpzs	s1
+0+0ec <[^>]*> eeb5 1a40 	fcmpzs	s2
+0+0f0 <[^>]*> eef5 fa40 	fcmpzs	s31
+0+0f4 <[^>]*> eeb4 0a60 	fcmps	s0, s1
+0+0f8 <[^>]*> eeb4 0a41 	fcmps	s0, s2
+0+0fc <[^>]*> eeb4 0a6f 	fcmps	s0, s31
+0+100 <[^>]*> eef4 0a40 	fcmps	s1, s0
+0+104 <[^>]*> eeb4 1a40 	fcmps	s2, s0
+0+108 <[^>]*> eef4 fa40 	fcmps	s31, s0
+0+10c <[^>]*> eef4 aa46 	fcmps	s21, s12
+0+110 <[^>]*> eeb1 0a60 	fnegs	s0, s1
+0+114 <[^>]*> eeb1 0a41 	fnegs	s0, s2
+0+118 <[^>]*> eeb1 0a6f 	fnegs	s0, s31
+0+11c <[^>]*> eef1 0a40 	fnegs	s1, s0
+0+120 <[^>]*> eeb1 1a40 	fnegs	s2, s0
+0+124 <[^>]*> eef1 fa40 	fnegs	s31, s0
+0+128 <[^>]*> eeb1 6a6a 	fnegs	s12, s21
+0+12c <[^>]*> ee30 0a20 	fadds	s0, s0, s1
+0+130 <[^>]*> ee30 0a01 	fadds	s0, s0, s2
+0+134 <[^>]*> ee30 0a2f 	fadds	s0, s0, s31
+0+138 <[^>]*> ee30 0a80 	fadds	s0, s1, s0
+0+13c <[^>]*> ee31 0a00 	fadds	s0, s2, s0
+0+140 <[^>]*> ee3f 0a80 	fadds	s0, s31, s0
+0+144 <[^>]*> ee70 0a00 	fadds	s1, s0, s0
+0+148 <[^>]*> ee30 1a00 	fadds	s2, s0, s0
+0+14c <[^>]*> ee70 fa00 	fadds	s31, s0, s0
+0+150 <[^>]*> ee3a 6aa2 	fadds	s12, s21, s5
+0+154 <[^>]*> eeb8 0ae0 	fsitos	s0, s1
+0+158 <[^>]*> eeb8 0ac1 	fsitos	s0, s2
+0+15c <[^>]*> eeb8 0aef 	fsitos	s0, s31
+0+160 <[^>]*> eef8 0ac0 	fsitos	s1, s0
+0+164 <[^>]*> eeb8 1ac0 	fsitos	s2, s0
+0+168 <[^>]*> eef8 fac0 	fsitos	s31, s0
+0+16c <[^>]*> eebd 0a60 	ftosis	s0, s1
+0+170 <[^>]*> eebd 0a41 	ftosis	s0, s2
+0+174 <[^>]*> eebd 0a6f 	ftosis	s0, s31
+0+178 <[^>]*> eefd 0a40 	ftosis	s1, s0
+0+17c <[^>]*> eebd 1a40 	ftosis	s2, s0
+0+180 <[^>]*> eefd fa40 	ftosis	s31, s0
+0+184 <[^>]*> ee00 1a10 	fmsr	s0, r1
+0+188 <[^>]*> ee00 7a10 	fmsr	s0, r7
+0+18c <[^>]*> ee00 ea10 	fmsr	s0, lr
+0+190 <[^>]*> ee00 0a90 	fmsr	s1, r0
+0+194 <[^>]*> ee01 0a10 	fmsr	s2, r0
+0+198 <[^>]*> ee0f 0a90 	fmsr	s31, r0
+0+19c <[^>]*> ee0a 7a90 	fmsr	s21, r7
+0+1a0 <[^>]*> eee0 1a10 	fmxr	fpsid, r1
+0+1a4 <[^>]*> eee0 ea10 	fmxr	fpsid, lr
+0+1a8 <[^>]*> ee10 0a90 	fmrs	r0, s1
+0+1ac <[^>]*> ee11 0a10 	fmrs	r0, s2
+0+1b0 <[^>]*> ee1f 0a90 	fmrs	r0, s31
+0+1b4 <[^>]*> ee10 1a10 	fmrs	r1, s0
+0+1b8 <[^>]*> ee10 7a10 	fmrs	r7, s0
+0+1bc <[^>]*> ee10 ea10 	fmrs	lr, s0
+0+1c0 <[^>]*> ee15 9a90 	fmrs	r9, s11
+0+1c4 <[^>]*> eef0 1a10 	fmrx	r1, fpsid
+0+1c8 <[^>]*> eef0 ea10 	fmrx	lr, fpsid
+0+1cc <[^>]*> ed91 0a00 	flds	s0, \[r1\]
+0+1d0 <[^>]*> ed9e 0a00 	flds	s0, \[lr\]
+0+1d4 <[^>]*> ed90 0a00 	flds	s0, \[r0\]
+0+1d8 <[^>]*> ed90 0aff 	flds	s0, \[r0, #1020\]
+0+1dc <[^>]*> ed10 0aff 	flds	s0, \[r0, #-1020\]
+0+1e0 <[^>]*> edd0 0a00 	flds	s1, \[r0\]
+0+1e4 <[^>]*> ed90 1a00 	flds	s2, \[r0\]
+0+1e8 <[^>]*> edd0 fa00 	flds	s31, \[r0\]
+0+1ec <[^>]*> edcc aac9 	fsts	s21, \[ip, #804\]
+0+1f0 <[^>]*> ecd0 0a01 	fldmias	r0, {s1}
+0+1f4 <[^>]*> ec90 1a01 	fldmias	r0, {s2}
+0+1f8 <[^>]*> ecd0 fa01 	fldmias	r0, {s31}
+0+1fc <[^>]*> ec90 0a02 	fldmias	r0, {s0-s1}
+0+200 <[^>]*> ec90 0a03 	fldmias	r0, {s0-s2}
+0+204 <[^>]*> ec90 0a20 	fldmias	r0, {s0-s31}
+0+208 <[^>]*> ecd0 0a1f 	fldmias	r0, {s1-s31}
+0+20c <[^>]*> ec90 1a1e 	fldmias	r0, {s2-s31}
+0+210 <[^>]*> ec90 fa02 	fldmias	r0, {s30-s31}
+0+214 <[^>]*> ec91 0a01 	fldmias	r1, {s0}
+0+218 <[^>]*> ec9e 0a01 	fldmias	lr, {s0}
+0+21c <[^>]*> ec80 1b03 	fstmiax	r0, {d1}
+0+220 <[^>]*> ec80 2b03 	fstmiax	r0, {d2}
+0+224 <[^>]*> ec80 fb03 	fstmiax	r0, {d15}
+0+228 <[^>]*> ec80 0b05 	fstmiax	r0, {d0-d1}
+0+22c <[^>]*> ec80 0b07 	fstmiax	r0, {d0-d2}
+0+230 <[^>]*> ec80 0b21 	fstmiax	r0, {d0-d15}
+0+234 <[^>]*> ec80 1b1f 	fstmiax	r0, {d1-d15}
+0+238 <[^>]*> ec80 2b1d 	fstmiax	r0, {d2-d15}
+0+23c <[^>]*> ec80 eb05 	fstmiax	r0, {d14-d15}
+0+240 <[^>]*> ec81 0b03 	fstmiax	r1, {d0}
+0+244 <[^>]*> ec8e 0b03 	fstmiax	lr, {d0}
+0+248 <[^>]*> eeb5 0a40 	fcmpzs	s0
+0+24c <[^>]*> eef5 0a40 	fcmpzs	s1
+0+250 <[^>]*> eeb5 1a40 	fcmpzs	s2
+0+254 <[^>]*> eef5 1a40 	fcmpzs	s3
+0+258 <[^>]*> eeb5 2a40 	fcmpzs	s4
+0+25c <[^>]*> eef5 2a40 	fcmpzs	s5
+0+260 <[^>]*> eeb5 3a40 	fcmpzs	s6
+0+264 <[^>]*> eef5 3a40 	fcmpzs	s7
+0+268 <[^>]*> eeb5 4a40 	fcmpzs	s8
+0+26c <[^>]*> eef5 4a40 	fcmpzs	s9
+0+270 <[^>]*> eeb5 5a40 	fcmpzs	s10
+0+274 <[^>]*> eef5 5a40 	fcmpzs	s11
+0+278 <[^>]*> eeb5 6a40 	fcmpzs	s12
+0+27c <[^>]*> eef5 6a40 	fcmpzs	s13
+0+280 <[^>]*> eeb5 7a40 	fcmpzs	s14
+0+284 <[^>]*> eef5 7a40 	fcmpzs	s15
+0+288 <[^>]*> eeb5 8a40 	fcmpzs	s16
+0+28c <[^>]*> eef5 8a40 	fcmpzs	s17
+0+290 <[^>]*> eeb5 9a40 	fcmpzs	s18
+0+294 <[^>]*> eef5 9a40 	fcmpzs	s19
+0+298 <[^>]*> eeb5 aa40 	fcmpzs	s20
+0+29c <[^>]*> eef5 aa40 	fcmpzs	s21
+0+2a0 <[^>]*> eeb5 ba40 	fcmpzs	s22
+0+2a4 <[^>]*> eef5 ba40 	fcmpzs	s23
+0+2a8 <[^>]*> eeb5 ca40 	fcmpzs	s24
+0+2ac <[^>]*> eef5 ca40 	fcmpzs	s25
+0+2b0 <[^>]*> eeb5 da40 	fcmpzs	s26
+0+2b4 <[^>]*> eef5 da40 	fcmpzs	s27
+0+2b8 <[^>]*> eeb5 ea40 	fcmpzs	s28
+0+2bc <[^>]*> eef5 ea40 	fcmpzs	s29
+0+2c0 <[^>]*> eeb5 fa40 	fcmpzs	s30
+0+2c4 <[^>]*> eef5 fa40 	fcmpzs	s31
+# The "(eq|)" should be replaces by "eq" once the disassembler is fixed.
+0+2c8 <[^>]*> bf01      	itttt	eq
+0+2ca <[^>]*> eef1 fa10 	fmstat(eq|)
+0+2ce <[^>]*> eef4 1ae3 	fcmpes(eq|)	s3, s7
+0+2d2 <[^>]*> eef5 2ac0 	fcmpezs(eq|)	s5
+0+2d6 <[^>]*> eef4 0a41 	fcmps(eq|)	s1, s2
+0+2da <[^>]*> bf01      	itttt	eq
+0+2dc <[^>]*> eef5 0a40 	fcmpzs(eq|)	s1
+0+2e0 <[^>]*> eef0 0ae1 	fabss(eq|)	s1, s3
+0+2e4 <[^>]*> eef0 fa69 	fcpys(eq|)	s31, s19
+0+2e8 <[^>]*> eeb1 aa44 	fnegs(eq|)	s20, s8
+0+2ec <[^>]*> bf01      	itttt	eq
+0+2ee <[^>]*> eef1 2ae3 	fsqrts(eq|)	s5, s7
+0+2f2 <[^>]*> ee32 3a82 	fadds(eq|)	s6, s5, s4
+0+2f6 <[^>]*> eec1 1a20 	fdivs(eq|)	s3, s2, s1
+0+2fa <[^>]*> ee4f fa2e 	fmacs(eq|)	s31, s30, s29
+0+2fe <[^>]*> bf01      	itttt	eq
+0+300 <[^>]*> ee1d ea8d 	fmscs(eq|)	s28, s27, s26
+0+304 <[^>]*> ee6c ca2b 	fmuls(eq|)	s25, s24, s23
+0+308 <[^>]*> ee0a baca 	fnmacs(eq|)	s22, s21, s20
+0+30c <[^>]*> ee59 9a68 	fnmscs(eq|)	s19, s18, s17
+0+310 <[^>]*> bf01      	itttt	eq
+0+312 <[^>]*> ee27 8ac7 	fnmuls(eq|)	s16, s15, s14
+0+316 <[^>]*> ee76 6a65 	fsubs(eq|)	s13, s12, s11
+0+31a <[^>]*> ed98 5a00 	flds(eq|)	s10, \[r8\]
+0+31e <[^>]*> edc7 4a00 	fsts(eq|)	s9, \[r7\]
+0+322 <[^>]*> bf01      	itttt	eq
+0+324 <[^>]*> ec91 4a01 	fldmias(eq|)	r1, {s8}
+0+328 <[^>]*> ecd2 3a01 	fldmias(eq|)	r2, {s7}
+0+32c <[^>]*> ecb3 3a01 	fldmias(eq|)	r3!, {s6}
+0+330 <[^>]*> ecf4 2a01 	fldmias(eq|)	r4!, {s5}
+0+334 <[^>]*> bf01      	itttt	eq
+0+336 <[^>]*> ed35 2a01 	fldmdbs(eq|)	r5!, {s4}
+0+33a <[^>]*> ed76 1a01 	fldmdbs(eq|)	r6!, {s3}
+0+33e <[^>]*> ec97 1b03 	fldmiax(eq|)	r7, {d1}
+0+342 <[^>]*> ec98 2b03 	fldmiax(eq|)	r8, {d2}
+0+346 <[^>]*> bf01      	itttt	eq
+0+348 <[^>]*> ecb9 3b03 	fldmiax(eq|)	r9!, {d3}
+0+34c <[^>]*> ecba 4b03 	fldmiax(eq|)	sl!, {d4}
+0+350 <[^>]*> ed3b 5b03 	fldmdbx(eq|)	fp!, {d5}
+0+354 <[^>]*> ed3c 6b03 	fldmdbx(eq|)	ip!, {d6}
+0+358 <[^>]*> bf01      	itttt	eq
+0+35a <[^>]*> ec8d 1a01 	fstmias(eq|)	sp, {s2}
+0+35e <[^>]*> ecce 0a01 	fstmias(eq|)	lr, {s1}
+0+362 <[^>]*> ece1 fa01 	fstmias(eq|)	r1!, {s31}
+0+366 <[^>]*> eca2 fa01 	fstmias(eq|)	r2!, {s30}
+0+36a <[^>]*> bf01      	itttt	eq
+0+36c <[^>]*> ed63 ea01 	fstmdbs(eq|)	r3!, {s29}
+0+370 <[^>]*> ed24 ea01 	fstmdbs(eq|)	r4!, {s28}
+0+374 <[^>]*> ec85 7b03 	fstmiax(eq|)	r5, {d7}
+0+378 <[^>]*> ec86 8b03 	fstmiax(eq|)	r6, {d8}
+0+37c <[^>]*> bf01      	itttt	eq
+0+37e <[^>]*> eca7 9b03 	fstmiax(eq|)	r7!, {d9}
+0+382 <[^>]*> eca8 ab03 	fstmiax(eq|)	r8!, {d10}
+0+386 <[^>]*> ed29 bb03 	fstmdbx(eq|)	r9!, {d11}
+0+38a <[^>]*> ed2a cb03 	fstmdbx(eq|)	sl!, {d12}
+0+38e <[^>]*> bf01      	itttt	eq
+0+390 <[^>]*> eef8 dac3 	fsitos(eq|)	s27, s6
+0+394 <[^>]*> eefd ca62 	ftosis(eq|)	s25, s5
+0+398 <[^>]*> eefd bac2 	ftosizs(eq|)	s23, s4
+0+39c <[^>]*> eefc aa61 	ftouis(eq|)	s21, s3
+0+3a0 <[^>]*> bf01      	itttt	eq
+0+3a2 <[^>]*> eefc 9ac1 	ftouizs(eq|)	s19, s2
+0+3a6 <[^>]*> eef8 8a60 	fuitos(eq|)	s17, s1
+0+3aa <[^>]*> ee11 ba90 	fmrs(eq|)	fp, s3
+0+3ae <[^>]*> eef0 9a10 	fmrx(eq|)	r9, fpsid
+0+3b2 <[^>]*> bf04      	itt	eq
+0+3b4 <[^>]*> ee01 9a90 	fmsr(eq|)	s3, r9
+0+3b8 <[^>]*> eee0 8a10 	fmxr(eq|)	fpsid, r8
+0+3bc <[^>]*> bf00      	nop
+0+3be <[^>]*> bf00      	nop
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.s b/gas/testsuite/gas/arm/vfp1xD_t2.s
new file mode 100644
index 000000000000..f3087a37ee96
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.s
@@ -0,0 +1,359 @@
+@ VFP Instructions for v1xD variants (Single precision only)
+@ Same as vfp1xD.s, but for Thumb-2
+	.syntax unified
+	.thumb
+	.text
+	.global F
+F:
+	@ First we test the basic syntax and bit patterns of the opcodes.
+	@ Most of these tests deliberatly use s0/r0 to avoid setting
+	@ any more bits than necessary.
+
+	@ Comparison operations
+
+	fmstat
+
+	fcmpes	s0, s0
+	fcmpezs	s0
+	fcmps	s0, s0
+	fcmpzs	s0
+
+	@ Monadic data operations
+
+	fabss	s0, s0
+	fcpys	s0, s0
+	fnegs	s0, s0
+	fsqrts	s0, s0
+
+	@ Dyadic data operations
+
+	fadds	s0, s0, s0
+	fdivs	s0, s0, s0
+	fmacs	s0, s0, s0
+	fmscs	s0, s0, s0
+	fmuls	s0, s0, s0
+	fnmacs	s0, s0, s0
+	fnmscs	s0, s0, s0
+	fnmuls	s0, s0, s0
+	fsubs	s0, s0, s0
+
+	@ Load/store operations
+
+	flds	s0, [r0]
+	fsts	s0, [r0]
+
+	@ Load/store multiple operations
+
+	fldmias	r0, {s0}
+	fldmfds	r0, {s0}
+	fldmias	r0!, {s0}
+	fldmfds	r0!, {s0}
+	fldmdbs	r0!, {s0}
+	fldmeas	r0!, {s0}
+
+	fldmiax	r0, {d0}
+	fldmfdx	r0, {d0}
+	fldmiax	r0!, {d0}
+	fldmfdx	r0!, {d0}
+	fldmdbx	r0!, {d0}
+	fldmeax	r0!, {d0}
+
+	fstmias	r0, {s0}
+	fstmeas	r0, {s0}
+	fstmias	r0!, {s0}
+	fstmeas	r0!, {s0}
+	fstmdbs	r0!, {s0}
+	fstmfds	r0!, {s0}
+
+	fstmiax	r0, {d0}
+	fstmeax	r0, {d0}
+	fstmiax	r0!, {d0}
+	fstmeax	r0!, {d0}
+	fstmdbx	r0!, {d0}
+	fstmfdx	r0!, {d0}
+
+	@ Conversion operations
+
+	fsitos	s0, s0
+	fuitos	s0, s0
+
+	ftosis	s0, s0
+	ftosizs	s0, s0
+	ftouis	s0, s0
+	ftouizs	s0, s0
+
+	@ ARM from VFP operations
+
+	fmrs	r0, s0
+	fmrx	r0, fpsid
+	fmrx	r0, fpscr
+	fmrx	r0, fpexc
+
+	@ VFP From ARM operations
+
+	fmsr	s0, r0
+	fmxr	fpsid, r0
+	fmxr	fpscr, r0
+	fmxr	fpexc, r0
+
+	@ Now we test that the register fields are updated correctly for
+	@ each class of instruction.
+
+	@ Single register operations (compare-zero):
+
+	fcmpzs	s1
+	fcmpzs	s2
+	fcmpzs	s31
+
+	@ Two register comparison operations:
+
+	fcmps	s0, s1
+	fcmps	s0, s2
+	fcmps	s0, s31
+	fcmps	s1, s0
+	fcmps	s2, s0
+	fcmps	s31, s0
+	fcmps	s21, s12
+
+	@ Two register data operations (monadic)
+
+	fnegs	s0, s1
+	fnegs	s0, s2
+	fnegs	s0, s31
+	fnegs	s1, s0
+	fnegs	s2, s0
+	fnegs	s31, s0
+	fnegs	s12, s21
+	
+	@ Three register data operations (dyadic)
+
+	fadds	s0, s0, s1
+	fadds	s0, s0, s2
+	fadds	s0, s0, s31
+	fadds	s0, s1, s0
+	fadds	s0, s2, s0
+	fadds	s0, s31, s0
+	fadds	s1, s0, s0
+	fadds	s2, s0, s0
+	fadds	s31, s0, s0
+	fadds	s12, s21, s5
+
+	@ Conversion operations
+
+	fsitos	s0, s1
+	fsitos	s0, s2
+	fsitos	s0, s31
+	fsitos	s1, s0
+	fsitos	s2, s0
+	fsitos	s31, s0
+
+	ftosis	s0, s1
+	ftosis	s0, s2
+	ftosis	s0, s31
+	ftosis	s1, s0
+	ftosis	s2, s0
+	ftosis	s31, s0
+
+	@ Move to VFP from ARM
+
+	fmsr	s0, r1
+	fmsr	s0, r7
+	fmsr	s0, r14
+	fmsr	s1, r0
+	fmsr	s2, r0
+	fmsr	s31, r0
+	fmsr	s21, r7
+
+	fmxr	fpsid, r1
+	fmxr	fpsid, r14
+
+	@ Move to ARM from VFP
+
+	fmrs	r0, s1
+	fmrs	r0, s2
+	fmrs	r0, s31
+	fmrs	r1, s0
+	fmrs	r7, s0
+	fmrs	r14, s0
+	fmrs	r9, s11
+
+	fmrx	r1, fpsid
+	fmrx	r14, fpsid
+
+	@ Load/store operations
+
+	flds	s0, [r1]
+	flds	s0, [r14]
+	flds	s0, [r0, #0]
+	flds	s0, [r0, #1020]
+	flds	s0, [r0, #-1020]
+	flds	s1, [r0]
+	flds	s2, [r0]
+	flds	s31, [r0]
+	fsts	s21, [r12, #804]
+
+	@ Load/store multiple operations
+
+	fldmias	r0, {s1}
+	fldmias	r0, {s2}
+	fldmias	r0, {s31}
+	fldmias	r0, {s0-s1}
+	fldmias	r0, {s0-s2}
+	fldmias	r0, {s0-s31}
+	fldmias	r0, {s1-s31}
+	fldmias	r0, {s2-s31}
+	fldmias	r0, {s30-s31}
+	fldmias	r1, {s0}
+	fldmias	r14, {s0}
+
+	fstmiax	r0, {d1}
+	fstmiax	r0, {d2}
+	fstmiax	r0, {d15}
+	fstmiax	r0, {d0-d1}
+	fstmiax	r0, {d0-d2}
+	fstmiax	r0, {d0-d15}
+	fstmiax	r0, {d1-d15}
+	fstmiax	r0, {d2-d15}
+	fstmiax	r0, {d14-d15}
+	fstmiax	r1, {d0}
+	fstmiax	r14, {d0}
+
+	@ Check that we assemble all the register names correctly
+
+	fcmpzs	s0
+	fcmpzs	s1
+	fcmpzs	s2
+	fcmpzs	s3
+	fcmpzs	s4
+	fcmpzs	s5
+	fcmpzs	s6
+	fcmpzs	s7
+	fcmpzs	s8
+	fcmpzs	s9
+	fcmpzs	s10
+	fcmpzs	s11
+	fcmpzs	s12
+	fcmpzs	s13
+	fcmpzs	s14
+	fcmpzs	s15
+	fcmpzs	s16
+	fcmpzs	s17
+	fcmpzs	s18
+	fcmpzs	s19
+	fcmpzs	s20
+	fcmpzs	s21
+	fcmpzs	s22
+	fcmpzs	s23
+	fcmpzs	s24
+	fcmpzs	s25
+	fcmpzs	s26
+	fcmpzs	s27
+	fcmpzs	s28
+	fcmpzs	s29
+	fcmpzs	s30
+	fcmpzs	s31
+
+	@ Now we check the placement of the conditional execution substring.
+	@ On VFP this is always at the end of the instruction.
+	@ We use different register numbers here to check for correct
+	@ disassembly
+	
+	@ Comparison operations
+
+	itttt eq
+	fmstateq
+
+	fcmpeseq	s3, s7
+	fcmpezseq	s5
+	fcmpseq	s1, s2
+	itttt eq
+	fcmpzseq	s1
+
+	@ Monadic data operations
+
+	fabsseq	s1, s3
+	fcpyseq	s31, s19
+	fnegseq	s20, s8
+	itttt eq
+	fsqrtseq	s5, s7
+
+	@ Dyadic data operations
+
+	faddseq	s6, s5, s4
+	fdivseq	s3, s2, s1
+	fmacseq	s31, s30, s29
+	itttt eq
+	fmscseq	s28, s27, s26
+	fmulseq	s25, s24, s23
+	fnmacseq	s22, s21, s20
+	fnmscseq	s19, s18, s17
+	itttt eq
+	fnmulseq	s16, s15, s14
+	fsubseq	s13, s12, s11
+
+	@ Load/store operations
+
+	fldseq	s10, [r8]
+	fstseq	s9, [r7]
+
+	@ Load/store multiple operations
+
+	itttt eq
+	fldmiaseq	r1, {s8}
+	fldmfdseq	r2, {s7}
+	fldmiaseq	r3!, {s6}
+	fldmfdseq	r4!, {s5}
+	itttt eq
+	fldmdbseq	r5!, {s4}
+	fldmeaseq	r6!, {s3}
+
+	fldmiaxeq	r7, {d1}
+	fldmfdxeq	r8, {d2}
+	itttt eq
+	fldmiaxeq	r9!, {d3}
+	fldmfdxeq	r10!, {d4}
+	fldmdbxeq	r11!, {d5}
+	fldmeaxeq	r12!, {d6}
+
+	itttt eq
+	fstmiaseq	r13, {s2}
+	fstmeaseq	r14, {s1}
+	fstmiaseq	r1!, {s31}
+	fstmeaseq	r2!, {s30}
+	itttt eq
+	fstmdbseq	r3!, {s29}
+	fstmfdseq	r4!, {s28}
+
+	fstmiaxeq	r5, {d7}
+	fstmeaxeq	r6, {d8}
+	itttt eq
+	fstmiaxeq	r7!, {d9}
+	fstmeaxeq	r8!, {d10}
+	fstmdbxeq	r9!, {d11}
+	fstmfdxeq	r10!, {d12}
+
+	@ Conversion operations
+
+	itttt eq
+	fsitoseq	s27, s6
+	ftosiseq	s25, s5
+	ftosizseq	s23, s4
+	ftouiseq	s21, s3
+	itttt eq
+	ftouizseq	s19, s2
+	fuitoseq	s17, s1
+
+	@ ARM from VFP operations
+
+	fmrseq	r11, s3
+	fmrxeq	r9, fpsid
+
+	@ VFP From ARM operations
+
+	itt eq
+	fmsreq	s3, r9
+	fmxreq	fpsid, r8
+
+	@ 2 nops to pad to 16-byte boundary
+	nop
+	nop
diff --git a/gas/testsuite/gas/arm/vfp2_t2.d b/gas/testsuite/gas/arm/vfp2_t2.d
new file mode 100644
index 000000000000..bb988e5472e2
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp2_t2.d
@@ -0,0 +1,17 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: Thumb-2 VFP Additional instructions
+#as: -mfpu=vfp
+
+# Test the ARM VFP Double Precision instructions
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]*> ec4a 5b10 	fmdrr	d0, r5, sl
+0+004 <[^>]*> ec5a 5b10 	fmrrd	r5, sl, d0
+0+008 <[^>]*> ec4a 5a37 	fmsrr	r5, sl, {s15, s16}
+0+00c <[^>]*> ec5a 5a37 	fmrrs	r5, sl, {s15, s16}
+0+010 <[^>]*> ec45 ab1f 	fmdrr	d15, sl, r5
+0+014 <[^>]*> ec55 ab1f 	fmrrd	sl, r5, d15
+0+018 <[^>]*> ec45 aa38 	fmsrr	sl, r5, {s17, s18}
+0+01c <[^>]*> ec55 aa38 	fmrrs	sl, r5, {s17, s18}
diff --git a/gas/testsuite/gas/arm/vfp2_t2.s b/gas/testsuite/gas/arm/vfp2_t2.s
new file mode 100644
index 000000000000..ba5551b6b9b6
--- /dev/null
+++ b/gas/testsuite/gas/arm/vfp2_t2.s
@@ -0,0 +1,21 @@
+@ VFP2 Additional instructions
+@ Same as vfp2.s, but for Thumb-2
+	.syntax unified
+	.thumb
+	.text
+	.global F
+F:
+	@ First we test the basic syntax and bit patterns of the opcodes.
+	@ Use a combination of r5, r10, s15, s17, d0 and d15 to exercise
+	@ the full register bitpatterns
+
+	fmdrr d0, r5, r10
+	fmrrd r5, r10, d0
+	fmsrr {s15, s16}, r5, r10
+	fmrrs r5, r10, {s15, s16}
+
+	fmdrr d15, r10, r5
+	fmrrd r10, r5, d15
+	fmsrr {s17, s18}, r10, r5
+	fmrrs r10, r5, {s17, s18}
+
diff --git a/gas/testsuite/gas/arm/wince_arm7t.d b/gas/testsuite/gas/arm/wince_arm7t.d
deleted file mode 100644
index 9d9b87f0acb1..000000000000
--- a/gas/testsuite/gas/arm/wince_arm7t.d
+++ /dev/null
@@ -1,75 +0,0 @@
-#objdump: -Dr --prefix-addresses --show-raw-insn
-#name: ARM arm7t (WinCE version)
-#as: -mcpu=arm7t -EL
-#source: arm7t.s
-
-# This file is the same as arm7t.d except that the PC-relative
-# LDR[S]H instructions have not had a -8 bias inserted.
-
-
-# Test the halfword and signextend memory transfers:
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> e1d100b0 ?	ldrh	r0, \[r1\]
-0+04 <[^>]*> e1f100b0 ?	ldrh	r0, \[r1\]!
-0+08 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
-0+0c <[^>]*> e1b100b2 ?	ldrh	r0, \[r1, r2\]!
-0+10 <[^>]*> e1d100bc ?	ldrh	r0, \[r1, #12\]
-0+14 <[^>]*> e1f100bc ?	ldrh	r0, \[r1, #12\]!
-0+18 <[^>]*> e15100bc ?	ldrh	r0, \[r1, #-12\]
-0+1c <[^>]*> e09100b2 ?	ldrh	r0, \[r1\], r2
-0+20 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
-0+24 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+d8 <[^>]*>
-0+28 <[^>]*> e1df0abc ?	ldrh	r0, \[pc, #172\]	; 0+dc <[^>]*>
-0+2c <[^>]*> e1c100b0 ?	strh	r0, \[r1\]
-0+30 <[^>]*> e1e100b0 ?	strh	r0, \[r1\]!
-0+34 <[^>]*> e18100b2 ?	strh	r0, \[r1, r2\]
-0+38 <[^>]*> e1a100b2 ?	strh	r0, \[r1, r2\]!
-0+3c <[^>]*> e1c100bc ?	strh	r0, \[r1, #12\]
-0+40 <[^>]*> e1e100bc ?	strh	r0, \[r1, #12\]!
-0+44 <[^>]*> e14100bc ?	strh	r0, \[r1, #-12\]
-0+48 <[^>]*> e08100b2 ?	strh	r0, \[r1\], r2
-0+4c <[^>]*> e1cf08b8 ?	strh	r0, \[pc, #136\]	; 0+dc <[^>]*>
-0+50 <[^>]*> e1d100d0 ?	ldrsb	r0, \[r1\]
-0+54 <[^>]*> e1f100d0 ?	ldrsb	r0, \[r1\]!
-0+58 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
-0+5c <[^>]*> e1b100d2 ?	ldrsb	r0, \[r1, r2\]!
-0+60 <[^>]*> e1d100dc ?	ldrsb	r0, \[r1, #12\]
-0+64 <[^>]*> e1f100dc ?	ldrsb	r0, \[r1, #12\]!
-0+68 <[^>]*> e15100dc ?	ldrsb	r0, \[r1, #-12\]
-0+6c <[^>]*> e09100d2 ?	ldrsb	r0, \[r1\], r2
-0+70 <[^>]*> e3a000de ?	mov	r0, #222	; 0xde
-0+74 <[^>]*> e1df06d0 ?	ldrsb	r0, \[pc, #96\]	; 0+dc <[^>]*>
-0+78 <[^>]*> e1d100f0 ?	ldrsh	r0, \[r1\]
-0+7c <[^>]*> e1f100f0 ?	ldrsh	r0, \[r1\]!
-0+80 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
-0+84 <[^>]*> e1b100f2 ?	ldrsh	r0, \[r1, r2\]!
-0+88 <[^>]*> e1d100fc ?	ldrsh	r0, \[r1, #12\]
-0+8c <[^>]*> e1f100fc ?	ldrsh	r0, \[r1, #12\]!
-0+90 <[^>]*> e15100fc ?	ldrsh	r0, \[r1, #-12\]
-0+94 <[^>]*> e09100f2 ?	ldrsh	r0, \[r1\], r2
-0+98 <[^>]*> e3a00cff ?	mov	r0, #65280	; 0xff00
-0+9c <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+d8 <[^>]*>
-0+a0 <[^>]*> e1df03f4 ?	ldrsh	r0, \[pc, #52\]	; 0+dc <[^>]*>
-0+a4 <[^>]*> e19100b2 ?	ldrh	r0, \[r1, r2\]
-0+a8 <[^>]*> 119100b2 ?	ldrneh	r0, \[r1, r2\]
-0+ac <[^>]*> 819100b2 ?	ldrhih	r0, \[r1, r2\]
-0+b0 <[^>]*> b19100b2 ?	ldrlth	r0, \[r1, r2\]
-0+b4 <[^>]*> e19100f2 ?	ldrsh	r0, \[r1, r2\]
-0+b8 <[^>]*> 119100f2 ?	ldrnesh	r0, \[r1, r2\]
-0+bc <[^>]*> 819100f2 ?	ldrhish	r0, \[r1, r2\]
-0+c0 <[^>]*> b19100f2 ?	ldrltsh	r0, \[r1, r2\]
-0+c4 <[^>]*> e19100d2 ?	ldrsb	r0, \[r1, r2\]
-0+c8 <[^>]*> 119100d2 ?	ldrnesb	r0, \[r1, r2\]
-0+cc <[^>]*> 819100d2 ?	ldrhisb	r0, \[r1, r2\]
-0+d0 <[^>]*> b19100d2 ?	ldrltsb	r0, \[r1, r2\]
-0+d4 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+d8 <[^>]*>
-0+d8 <[^>]*> e15f00f4 ?	ldrsh	r0, \[pc, #-4\]	; 0+dc <[^>]*>
-0+dc <[^>]*> 00000000 ?	andeq	r0, r0, r0
-[		]*dc:.*fred
-0+e0 <[^>]*> 0000c0de ?	.*
-0+e4 <[^>]*> 0000dead ?	.*
-0+e8 <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
-0+ec <[^>]*> e1a00000 ?	nop[ 	]+\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_copro.d b/gas/testsuite/gas/arm/wince_copro.d
deleted file mode 100644
index 91097dd45155..000000000000
--- a/gas/testsuite/gas/arm/wince_copro.d
+++ /dev/null
@@ -1,45 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn --architecture=armv5te
-#name: ARM CoProcessor Instructions (WinCE version)
-#as: -march=armv5te -EL
-#source: copro.s
-
-# This file is the same as copro.d except that the PC-relative
-# LDC and STFS instructions have not had a -8 bias inserted.
-
-# Test the standard ARM co-processor instructions:
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+000 <[^>]*> ee421103 	dvfs	f1, f2, f3
-0+004 <[^>]*> 0e3414a5 	cfadddeq	mvd1, mvd4, mvd5
-0+008 <[^>]*> ed939500 	cfldr32	mvfx9, \[r3\]
-0+00c <[^>]*> edd1e108 	ldfp	f6, \[r1, #32\]
-0+010 <[^>]*> 4db200ff 	ldcmi	0, cr0, \[r2, #1020\]!
-0+014 <[^>]*> 5cf31710 	ldcpll	7, cr1, \[r3\], #64
-0+018 <[^>]*> ed1f8003 	ldc	0, cr8, \[pc, #-12\]
-0+01c <[^>]*> ed830500 	cfstr32	mvfx0, \[r3\]
-0+020 <[^>]*> edc0f302 	stcl	3, cr15, \[r0, #8\]
-0+024 <[^>]*> 0da2c419 	cfstrseq	mvf12, \[r2, #100\]!
-0+028 <[^>]*> 3ca4860c 	stccc	6, cr8, \[r4\], #48
-0+02c <[^>]*> ed0f7103 	stfs	f7, \[pc, #-12\]
-0+030 <[^>]*> ee715212 	mrc	2, 3, r5, cr1, cr2, \{0\}
-0+034 <[^>]*> aeb1f4f2 	mrcge	4, 5, pc, cr1, cr2, \{7\}
-0+038 <[^>]*> ee21f711 	mcr	7, 1, pc, cr1, cr1, \{0\}
-0+03c <[^>]*> be228519 	cfsh64lt	mvdx8, mvdx2, #9
-0+040 <[^>]*> ec907300 	ldc	3, cr7, \[r0\], \{0\}
-0+044 <[^>]*> ec816e01 	stc	14, cr6, \[r1\], \{1\}
-0+048 <[^>]*> fc925502 	ldc2	5, cr5, \[r2\], \{2\}
-0+04c <[^>]*> fc834603 	stc2	6, cr4, \[r3\], \{3\}
-0+050 <[^>]*> ecd43704 	ldcl	7, cr3, \[r4\], \{4\}
-0+054 <[^>]*> ecc52805 	stcl	8, cr2, \[r5\], \{5\}
-0+058 <[^>]*> fcd61906 	ldc2l	9, cr1, \[r6\], \{6\}
-0+05c <[^>]*> fcc70a07 	stc2l	10, cr0, \[r7\], \{7\}
-0+060 <[^>]*> ecd88bff 	ldcl	11, cr8, \[r8\], \{255\}
-0+064 <[^>]*> ecc99cfe 	stcl	12, cr9, \[r9\], \{254\}
-0+068 <[^>]*> ec507d04 	mrrc	13, 0, r7, r0, cr4
-0+06c <[^>]*> ec407e05 	mcrr	14, 0, r7, r0, cr5
-0+070 <[^>]*> ec507fff 	mrrc	15, 15, r7, r0, cr15
-0+074 <[^>]*> ec407efe 	mcrr	14, 15, r7, r0, cr14
-0+078 <[^>]*> e1a00000 	nop			\(mov r0,r0\)
-0+07c <[^>]*> e1a00000 	nop			\(mov r0,r0\)
diff --git a/gas/testsuite/gas/arm/wince_inst.d b/gas/testsuite/gas/arm/wince_inst.d
index 2543f0b8ed07..a9852e0394b8 100644
--- a/gas/testsuite/gas/arm/wince_inst.d
+++ b/gas/testsuite/gas/arm/wince_inst.d
@@ -2,6 +2,8 @@
 #name: ARM basic instructions (WinCE version)
 #as: -mcpu=arm7m -EL
 #source: inst.s
+# inst.d is used for non-WinCE targets.
+#not-skip: *-wince-*
 
 # This file is the same as inst.d except that the BL
 # instructions have not had a -8 bias inserted.
@@ -159,8 +161,8 @@ Disassembly of section .text:
 0+24c <[^>]*> e9020018 ?	stmdb	r2, {r3, r4}
 0+250 <[^>]*> e8830003 ?	stmia	r3, {r0, r1}
 0+254 <[^>]*> e9c40300 ?	stmib	r4, {r8, r9}\^
-0+258 <[^>]*> ef123456 ?	swi	0x00123456
-0+25c <[^>]*> 2f000033 ?	swics	0x00000033
+0+258 <[^>]*> ef123456 ?	(swi|svc)	0x00123456
+0+25c <[^>]*> 2f000033 ?	(swi|svc)cs	0x00000033
 0+260 <[^>]*> eb000000 ?	bl	0+268 <[^>]*>
 [		]*260:.*_wombat.*
 0+264 <[^>]*> 5b000000 ?	blpl	0+26c <[^>]*>
diff --git a/gas/testsuite/gas/arm/wince_ldconst.d b/gas/testsuite/gas/arm/wince_ldconst.d
deleted file mode 100644
index 131b4b5433f2..000000000000
--- a/gas/testsuite/gas/arm/wince_ldconst.d
+++ /dev/null
@@ -1,31 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: ARM ldr with immediate constant (WinCE version)
-#as: -mcpu=arm7m -EL
-#source: ldconst.s
-
-# This file is the same as ldconst.d except that the PC-
-# relative LDR instructions have not had a -8 bias inserted.
-
-.*: +file format .*arm.*
-
-Disassembly of section .text:
-0+00 <[^>]*> e3a00000 ?	mov	r0, #0	; 0x0
-0+04 <[^>]*> e3a004ff ?	mov	r0, #-16777216	; 0xff000000
-0+08 <[^>]*> e3e00000 ?	mvn	r0, #0	; 0x0
-0+0c <[^>]*> e51f000c ?	ldr	r0, \[pc, #-12\]	; 0+08 <[^>]*>
-0+10 <[^>]*> 0fff0000 ?	.*
-0+14 <[^>]*> e3a0e000 ?	mov	lr, #0	; 0x0
-0+18 <[^>]*> e3a0e8ff ?	mov	lr, #16711680	; 0xff0000
-0+1c <[^>]*> e3e0e8ff ?	mvn	lr, #16711680	; 0xff0000
-0+20 <[^>]*> e51fe00c ?	ldr	lr, \[pc, #-12\]	; 0+1c <[^>]*>
-0+24 <[^>]*> 00fff000 ?	.*
-0+28 <[^>]*> 03a00000 ?	moveq	r0, #0	; 0x0
-0+2c <[^>]*> 03a00cff ?	moveq	r0, #65280	; 0xff00
-0+30 <[^>]*> 03e00cff ?	mvneq	r0, #65280	; 0xff00
-0+34 <[^>]*> 051f000c ?	ldreq	r0, \[pc, #-12\]	; 0+30 <[^>]*>
-0+38 <[^>]*> 000fff00 ?	.*
-0+3c <[^>]*> 43a0b000 ?	movmi	fp, #0	; 0x0
-0+40 <[^>]*> 43a0b0ff ?	movmi	fp, #255	; 0xff
-0+44 <[^>]*> 43e0b0ff ?	mvnmi	fp, #255	; 0xff
-0+48 <[^>]*> 451fb00c ?	ldrmi	fp, \[pc, #-12\]	; 0+44 <[^>]*>
-0+4c <[^>]*> 0000fff0 ?	.*
diff --git a/gas/testsuite/gas/bfin/arithmetic.d b/gas/testsuite/gas/bfin/arithmetic.d
new file mode 100644
index 000000000000..a6c98f77aa13
--- /dev/null
+++ b/gas/testsuite/gas/bfin/arithmetic.d
@@ -0,0 +1,179 @@
+#objdump: -dr
+#name: arithmetic
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+00000000 <abs>:
+   0:	10 c4 [0-3][[:xdigit:]] 00 	A0= ABS A0;
+   4:	10 c4 [0-3][[:xdigit:]] 40 	A0= ABS A1;
+   8:	30 c4 [0-3][[:xdigit:]] 00 	A1= ABS A0;
+   c:	30 c4 [0-3][[:xdigit:]] 40 	A1= ABS A1;
+  10:	10 c4 [0-3][[:xdigit:]] c0 	A1= ABS A0,A0= ABS A0;
+  14:	07 c4 10 80 	R0= ABS R2;
+
+00000018 <add>:
+  18:	86 5b       	SP=SP\+P0;
+  1a:	96 5b       	SP=SP\+P2;
+  1c:	f9 5b       	FP=P1\+FP;
+  1e:	04 c4 3a 0e 	R7=R7\+R2 \(NS\);
+  22:	04 c4 30 2c 	R6=R6\+R0 \(S\);
+  26:	02 c4 10 a8 	R4.L=R2.H\+R0.L \(S\);
+  2a:	22 c4 09 aa 	R5.H=R1.H\+R1.L \(S\);
+  2e:	02 c4 35 0c 	R6.L=R6.L\+R5.L \(NS\);
+
+00000032 <add_sub_prescale_down>:
+  32:	05 c4 01 98 	R4.L=R0\+R1\(RND20\);
+  36:	25 c4 28 96 	R3.H=R5\+R0\(RND20\);
+  3a:	05 c4 3d d2 	R1.L=R7-R5\(RND20\);
+
+0000003e <add_sub_prescale_up>:
+  3e:	05 c4 01 04 	R2.L=R0\+R1\(RND12\);
+  42:	25 c4 3e 0e 	R7.H=R7\+R6\(RND12\);
+  46:	05 c4 1a 4a 	R5.L=R3-R2\(RND12\);
+  4a:	25 c4 0a 44 	R2.H=R1-R2\(RND12\);
+
+0000004e <add_immediate>:
+  4e:	05 66       	R5\+=-64;
+  50:	fa 65       	R2\+=0x3f;
+  52:	60 9f       	I0\+=2;
+  54:	63 9f       	I3\+=2;
+  56:	6a 9f       	I2\+=4;
+  58:	69 9f       	I1\+=4;
+  5a:	20 6c       	P0\+=0x4;
+  5c:	86 6c       	SP\+=0x10;
+  5e:	07 6f       	FP\+=-32;
+
+00000060 <divide_primitive>:
+  60:	6b 42       	DIVS\(R3,R5\);
+  62:	2b 42       	DIVQ\(R3,R5\);
+
+00000064 <expadj>:
+  64:	07 c6 25 0c 	R6.L=EXPADJ \(R5,R4.L\);
+  68:	07 c6 08 ca 	R5.L=EXPADJ \(R0.H,R1.L\);
+  6c:	07 c6 2b 48 	R4.L=EXPADJ \(R3,R5.L\) \(V\);
+
+00000070 <max>:
+  70:	07 c4 2a 0c 	R6=MAX\(R5,R2\);
+  74:	07 c4 0b 00 	R0=MAX\(R1,R3\);
+
+00000078 <min>:
+  78:	07 c4 13 4a 	R5=MIN\(R2,R3\);
+  7c:	07 c4 38 48 	R4=MIN\(R7,R0\);
+
+00000080 <modify_decrement>:
+  80:	0b c4 [0-3][[:xdigit:]] c0 	A0-=A1;
+  84:	0b c4 [0-3][[:xdigit:]] e0 	A0-=A1\(W32\);
+  88:	17 44       	FP-=P2;
+  8a:	06 44       	SP-=P0;
+  8c:	73 9e       	I3-=M0;
+  8e:	75 9e       	I1-=M1;
+
+00000090 <modify_increment>:
+  90:	0b c4 [0-3][[:xdigit:]] 80 	A0\+=A1;
+  94:	0b c4 [0-3][[:xdigit:]] a0 	A0\+=A1\(W32\);
+  98:	4e 45       	SP\+=P1\(BREV\);
+  9a:	7d 45       	P5\+=FP\(BREV\);
+  9c:	6a 9e       	I2\+=M2;
+  9e:	e0 9e       	I0\+=M0\(BREV\);
+  a0:	0b c4 [0-3][[:xdigit:]] 0e 	R7=\(A0\+=A1\);
+  a4:	0b c4 [0-3][[:xdigit:]] 4c 	R6.L=\(A0\+=A1\);
+  a8:	2b c4 [0-3][[:xdigit:]] 40 	R0.H=\(A0\+=A1\);
+
+000000ac <multiply16>:
+  ac:	00 c2 0a 24 	R0 = R1.H \* R2.L;
+  b0:	20 c2 68 26 	R1 = R5.H \* R0.H \(S2RND\);
+  b4:	80 c2 db 23 	R7 = R3.L \* R3.H \(FU\);
+  b8:	28 c3 15 27 	R4 = R2.H \* R5.H \(ISS2\);
+  bc:	08 c3 0b 20 	R0 = R1.L \* R3.L \(IS\);
+  c0:	08 c2 a8 25 	R6 = R5.H \* R0.L;
+  c4:	94 c3 be 40 	R2.H = R7.L \* R6.H \(M, IU\);
+  c8:	04 c2 e8 80 	R3.H = R5.H \* R0.L;
+  cc:	14 c2 09 40 	R0.H = R1.L \* R1.H \(M\);
+  d0:	1c c3 3e 80 	R1 = R7.H \* R6.L \(M, IS\);
+  d4:	0c c2 02 41 	R5 = R0.L \* R2.H;
+  d8:	1c c2 b0 c0 	R3 = R6.H \* R0.H \(M\);
+
+000000dc <multiply32>:
+  dc:	c4 40       	R4\*=R0;
+  de:	d7 40       	R7\*=R2;
+
+000000e0 <multiply_accumulate>:
+  e0:	63 c0 2f 02 	a0 = R5.L \* R7.H \(W32\);
+  e4:	03 c0 00 04 	a0 = R0.H \* R0.L;
+  e8:	83 c0 13 0a 	a0 \+= R2.L \* R3.H \(FU\);
+  ec:	03 c0 21 0c 	a0 \+= R4.H \* R1.L;
+  f0:	03 c1 3e 12 	a0 -= R7.L \* R6.H \(IS\);
+  f4:	03 c0 2a 16 	a0 -= R5.H \* R2.H;
+  f8:	10 c0 08 58 	a1 = R1.L \* R0.H \(M\);
+  fc:	00 c0 10 98 	a1 = R2.H \* R0.L;
+ 100:	70 c0 3e 98 	a1 = R7.H \* R6.L \(M, W32\);
+ 104:	81 c0 1a 18 	a1 \+= R3.L \* R2.L \(FU\);
+ 108:	01 c0 31 98 	a1 \+= R6.H \* R1.L;
+ 10c:	02 c1 03 58 	a1 -= R0.L \* R3.H \(IS\);
+ 110:	02 c0 17 58 	a1 -= R2.L \* R7.H;
+
+00000114 <multiply_accumulate_half>:
+ 114:	03 c0 f5 25 	R7.L = \(a0 = R6.H \* R5.L\);
+ 118:	c3 c0 0a 24 	R0.L = \(a0 = R1.H \* R2.L\) \(TFU\);
+ 11c:	03 c0 ac 28 	R2.L = \(a0 \+= R5.L \* R4.L\);
+ 120:	43 c0 fe 2e 	R3.L = \(a0 \+= R7.H \* R6.H\) \(T\);
+ 124:	03 c0 1a 36 	R0.L = \(a0 -= R3.H \* R2.H\);
+ 128:	63 c1 6c 30 	R1.L = \(a0 -= R5.L \* R4.L\) \(IH\);
+ 12c:	04 c0 48 58 	R1.H = \(a1 = R1.L \* R0.H\);
+ 130:	34 c1 83 98 	R2.H = \(a1 = R0.H \* R3.L\) \(M, ISS2\);
+ 134:	05 c0 bf 59 	R6.H = \(a1 \+= R7.L \* R7.H\);
+ 138:	25 c0 d3 19 	R7.H = \(a1 \+= R2.L \* R3.L\) \(S2RND\);
+ 13c:	06 c0 a2 d9 	R6.H = \(a1 -= R4.H \* R2.H\);
+ 140:	d6 c0 5f 99 	R5.H = \(a1 -= R3.H \* R7.L\) \(M, TFU\);
+
+00000144 <multiply_accumulate_data_reg>:
+ 144:	0b c0 0a 20 	R0 = \(a0 = R1.L \* R2.L\);
+ 148:	0b c1 8a 20 	R2 = \(a0 = R1.L \* R2.L\) \(IS\);
+ 14c:	0b c0 3e 2d 	R4 = \(a0 \+= R7.H \* R6.L\);
+ 150:	2b c0 ab 2b 	R6 = \(a0 \+= R5.L \* R3.H\) \(S2RND\);
+ 154:	0b c0 97 35 	R6 = \(a0 -= R2.H \* R7.L\);
+ 158:	8b c0 06 33 	R4 = \(a0 -= R0.L \* R6.H\) \(FU\);
+ 15c:	0c c0 81 99 	R7 = \(a1 = R0.H \* R1.L\);
+ 160:	9c c0 13 d9 	R5 = \(a1 = R2.H \* R3.H\) \(M, FU\);
+ 164:	0d c0 bd 18 	R3 = \(a1 \+= R7.L \* R5.L\);
+ 168:	2d c1 17 d8 	R1 = \(a1 \+= R2.H \* R7.H\) \(ISS2\);
+ 16c:	0e c0 80 58 	R3 = \(a1 -= R0.L \* R0.H\);
+ 170:	1e c1 17 59 	R5 = \(a1 -= R2.L \* R7.H\) \(M, IS\);
+
+00000174 <negate>:
+ 174:	85 43       	R5=-R0;
+ 176:	07 c4 10 ee 	R7=-R2\(S\);
+ 17a:	07 c4 10 ce 	R7=-R2\(NS\);
+ 17e:	0e c4 [0-3][[:xdigit:]] 00 	A0=-A0;
+ 182:	0e c4 [0-3][[:xdigit:]] 40 	A0=-A1;
+ 186:	2e c4 [0-3][[:xdigit:]] 00 	A1=-A0;
+ 18a:	2e c4 [0-3][[:xdigit:]] 40 	A1=-A1;
+ 18e:	0e c4 [0-3][[:xdigit:]] c0 	A1=-A1,A0=-A0;
+
+00000192 <round_half>:
+ 192:	0c c4 18 ca 	R5.L=R3\(RND\);
+ 196:	2c c4 00 cc 	R6.H=R0\(RND\);
+
+0000019a <saturate>:
+ 19a:	08 c4 [0-3][[:xdigit:]] 20 	A0=A0\(S\);
+ 19e:	08 c4 [0-3][[:xdigit:]] 60 	A1=A1\(S\);
+ 1a2:	08 c4 [0-3][[:xdigit:]] a0 	A1=A1\(S\),A0=A0\(S\);
+
+000001a6 <signbits>:
+ 1a6:	05 c6 00 0a 	R5.L=SIGNBITS R0;
+ 1aa:	05 c6 07 80 	R0.L=SIGNBITS R7.H;
+ 1ae:	06 c6 00 06 	R3.L=SIGNBITS A0;
+ 1b2:	06 c6 00 4e 	R7.L=SIGNBITS A1;
+
+000001b6 <subtract>:
+ 1b6:	43 53       	R5=R3-R0;
+ 1b8:	04 c4 38 6e 	R7=R7-R0 \(S\);
+ 1bc:	04 c4 11 46 	R3=R2-R1 \(NS\);
+ 1c0:	03 c4 37 ea 	R5.L=R6.H-R7.H \(S\);
+ 1c4:	23 c4 1b 40 	R0.H=R3.L-R3.H \(NS\);
+
+000001c8 <subtract_immediate>:
+ 1c8:	66 9f       	I2-=2;
+ 1ca:	6c 9f       	I0-=4;
diff --git a/gas/testsuite/gas/bfin/arithmetic.s b/gas/testsuite/gas/bfin/arithmetic.s
new file mode 100644
index 000000000000..6c6300ba61a0
--- /dev/null
+++ b/gas/testsuite/gas/bfin/arithmetic.s
@@ -0,0 +1,225 @@
+	.text
+	.global abs
+abs:
+	a0 = abs a0;
+	A0 = ABS A1;
+	A1 = Abs a0;
+	a1 = aBs A1;
+	A1 = abs a1, a0 = ABS A0;
+	r0 = abs r2;
+
+	.text
+	.global add
+add:
+	sp = sp + P0;
+	SP = SP + P2;
+	FP = p1 + fp;
+
+	R7 = r7 + r2 (NS);
+	r6 = r6 + r0 (s);
+	
+	r4.L = R2.h + r0.L (s);
+	r5.H = R1.H + R1.L (S);
+	r6.L = R6.L + r5.l (NS);
+
+	.text
+	.global add_sub_prescale_down
+add_sub_prescale_down:
+	r4.l = r0 + r1 (RND20);
+	R3.H = r5 + r0 (rnd20);
+	r1.L = r7 - R5 (rND20);
+
+	.text
+	.global add_sub_prescale_up
+add_sub_prescale_up:
+	r2.L = R0 + R1 (rnd12);
+	r7.H = r7 + r6 (RND12);
+	r5.l = r3 - R2 (rNd12);
+	r2.h = R1 - R2 (Rnd12);
+
+	.text
+	.global add_immediate
+add_immediate:
+	R5 += -64;
+	r2 += 63;
+	i0 += 2;
+	I3 += 2;
+	I2 += 4;
+	i1 += 4;
+	P0 += 4;
+	sp += 16;
+	FP += -32;
+
+	.text
+	.global divide_primitive
+divide_primitive:
+	divs (r3, r5);
+	divq (R3, R5);
+
+	.text
+	.global expadj
+expadj:
+	r6.L = EXPADJ (r5, r4.l);
+	R5.l = ExpAdj (r0.h, r1.l);
+	R4.L = expadj (R3, R5.L) (V);
+
+	.text
+	.global max
+max:
+	R6 = MAX (r5, R2);
+	r0 = max (r1, r3);
+
+	.text 
+	.global min
+min:
+	r5 = mIn (r2, R3);
+	R4 = Min (r7, R0);
+
+
+	.text
+	.global modify_decrement
+modify_decrement:
+	A0 -= A1;
+	a0 -= a1 (w32);
+	fp -= p2;
+	SP -= P0;
+	I3 -= M0;
+	i1 -= m1;
+
+	.text
+	.global modify_increment
+modify_increment:
+	a0 += a1;
+	A0 += A1 (w32);
+	Sp += P1 (Brev);
+	P5 += Fp (BREV);
+	i2 += M2;
+	I0 += m0 (brev);
+	r7 = ( a0 += a1);
+	r6.l = (A0 += a1);
+	R0.H = (a0 += A1);
+
+	.text
+	.global multiply16
+multiply16:
+	R0.l = r1.h * r2.l;
+	r1.L = r5.H * r0.H (s2rnd);
+	r7.l = r3.l * r3.H (FU);
+	r4 = r2.H * r5.H (iSS2);
+	r0 = r1.l * r3.l (is);
+	r6 = R5.H * r0.l;
+
+	r2.h = r7.l * r6.H (M, iu);
+	r3.H = r5.H * r0.L;
+	R0.H = r1.L * r1.H (M);
+	r1 = r7.H * r6.L (M, is);
+	R5 = r0.l * r2.h;
+	r3 = r6.H * r0.H (m);
+
+	.text
+	.global multiply32
+multiply32:
+	R4 *= r0;
+	r7 *= R2;
+
+	.text
+	.global multiply_accumulate
+multiply_accumulate:
+	a0 = r5.l * R7.H (w32);
+	a0 = r0.h * r0.l;
+	A0 += R2.L * r3.H (FU);
+	A0 += r4.h * r1.L;
+	a0 -= r7.l * r6.H (Is);
+	A0 -= R5.H * r2.H;
+
+	a1 = r1.L * r0.H (M);
+	A1 = r2.h * r0.L;
+	A1 = R7.H * R6.L (M, W32);
+	a1 += r3.l * r2.l (fu);
+	a1 += R6.H * r1.L;
+	A1 -= r0.L * R3.H (is);
+	a1 -= r2.l * r7.h;
+
+	.text
+	.global multiply_accumulate_half
+multiply_accumulate_half:
+	r7.l = (a0 = r6.H * r5.L);
+	r0.L = (A0 = r1.h * R2.l) (tfu);
+	R2.L = (a0 += r5.L * r4.L);
+	r3.l = (A0 += r7.H * r6.h) (T);
+	r0.l = (a0 -= r3.h * r2.h);
+	r1.l = (a0 -= r5.L * r4.L) (iH);
+
+	r1.H = (a1 = r1.l * R0.H);
+	r2.h = (A1 = r0.H * r3.L) (M, Iss2);
+	R6.H = (a1 += r7.l * r7.H);
+	r7.h = (a1 += R2.L * R3.L) (S2rnd);
+	r6.H = (A1 -= R4.h * r2.h);
+	r5.h = (a1 -= r3.H * r7.L) (M, tFu);
+
+	.text
+	.global multiply_accumulate_data_reg
+multiply_accumulate_data_reg:
+	R0 = (A0 = R1.L * R2.L);
+	R2 = (A0 = r1.l * r2.l) (is);
+	r4 = (a0 += r7.h * r6.L);
+	r6 = (A0 += R5.L * r3.h) (s2RND);
+	R6 = (a0 -= r2.h * r7.l);
+	r4 = (A0 -= R0.L * r6.H) (FU);
+
+	r7 = (a1 = r0.h * r1.l);
+	R5 = (A1 = r2.H * r3.H) (M, fu);
+	R3 = (A1 += r7.l * r5.l);
+	r1 = (a1 += r2.h * r7.h) (iss2);
+	r3 = (A1 -= r0.l * R0.H);
+	R5 = (a1 -= R2.l * R7.h) (m, is);
+
+	.text
+	.global negate
+negate:
+	R5 = - r0;
+	r7 = -R2(s);
+	R7 = -r2(Ns);
+	A0 = -A0;
+	a0 = -a1;
+	A1 = -A0;
+	a1 = -A1;
+	a1 = -a1, a0 = -a0;
+
+	.text
+	.global round_half
+round_half:
+	R5.L = r3 (rnd);
+	r6.H = r0 (RND);
+
+	.text
+	.global saturate
+saturate:
+	A0 = A0 (S);
+	a1 = a1 (s);
+	A1 = a1 (S), a0 = A0 (s);
+
+	.text
+	.global signbits
+signbits:
+	R5.l = signbits r0;
+	r0.L = SIGNbits r7.H;
+	r3.l = signBits A0;
+	r7.L = SIGNBITS a1;
+
+	.text
+	.global subtract
+subtract:
+	R5 = R3 - R0;
+	R7 = R7 - r0 (S);
+	r3 = r2 - r1 (ns);
+
+	r5.l = R6.H - R7.h (s);
+	r0.H = r3.l - r3.h (NS);
+
+	.text
+	.global subtract_immediate
+subtract_immediate:
+	I2 -= 2;
+	i0 -= 4;
+
diff --git a/gas/testsuite/gas/bfin/bfin.exp b/gas/testsuite/gas/bfin/bfin.exp
new file mode 100644
index 000000000000..51690a16fe05
--- /dev/null
+++ b/gas/testsuite/gas/bfin/bfin.exp
@@ -0,0 +1,48 @@
+# Blackfin assembler testsuite
+
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "bfin $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+if [istarget bfin*-*-*] {
+	run_dump_test "arithmetic"
+	run_dump_test "bit"
+	run_dump_test "bit2"
+	run_dump_test "cache"
+	run_dump_test "cache2"
+	run_dump_test "control_code"
+	run_dump_test "control_code2"
+	run_dump_test "event"
+	run_dump_test "event2"
+	run_list_test "expected_errors" ""
+	run_list_test "expected_move_errors" ""
+	run_dump_test "flow"
+	run_dump_test "flow2"
+	run_dump_test "load"
+	run_dump_test "logical"
+	run_dump_test "logical2"
+	run_dump_test "move"
+	run_dump_test "move2"
+	run_dump_test "parallel"
+	run_dump_test "parallel2"
+	run_dump_test "parallel3"
+	run_dump_test "parallel4"
+	run_dump_test "reloc"
+	run_dump_test "shift"
+	run_dump_test "shift2"
+	run_dump_test "stack"
+	run_dump_test "stack2"
+	run_dump_test "store"
+	run_dump_test "vector"
+	run_dump_test "vector2"
+	run_dump_test "video"
+	run_dump_test "video2"
+}
diff --git a/gas/testsuite/gas/bfin/bit.d b/gas/testsuite/gas/bfin/bit.d
new file mode 100644
index 000000000000..fa334c242241
--- /dev/null
+++ b/gas/testsuite/gas/bfin/bit.d
@@ -0,0 +1,42 @@
+#objdump: -dr
+#name: bit
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <bitclr>:
+   0:	fc 4c       	BITCLR \(R4,0x1f\);
+   2:	00 4c       	BITCLR \(R0,0x0\);
+
+00000004 <bitset>:
+   4:	f2 4a       	BITSET \(R2,0x1e\);
+   6:	eb 4a       	BITSET \(R3,0x1d\);
+
+00000008 <bittgl>:
+   8:	b7 4b       	BITTGL \(R7,0x16\);
+   a:	86 4b       	BITTGL \(R6,0x10\);
+
+0000000c <bittst>:
+   c:	f8 49       	CC = BITTST \(R0,0x1f\);
+   e:	01 49       	CC = BITTST \(R1,0x0\);
+  10:	7f 49       	CC = BITTST \(R7,0xf\);
+
+00000012 <deposit>:
+  12:	0a c6 13 8a 	R5=DEPOSIT\(R3,R2\);
+  16:	0a c6 37 c0 	R0=DEPOSIT\(R7,R6\)\(X\);
+
+0000001a <extract>:
+  1a:	0a c6 0a 08 	R4=EXTRACT\(R2,R1.L\) \(Z\);
+  1e:	0a c6 10 04 	R2=EXTRACT\(R0,R2.L\) \(Z\);
+  22:	0a c6 23 4e 	R7=EXTRACT\(R3,R4.L\)\(X\);
+  26:	0a c6 0e 4a 	R5=EXTRACT\(R6,R1.L\)\(X\);
+
+0000002a <bitmux>:
+  2a:	08 c6 08 00 	BITMUX \(R1,R0,A0 \)\(ASR\);
+  2e:	08 c6 13 00 	BITMUX \(R2,R3,A0 \)\(ASR\);
+  32:	08 c6 25 40 	BITMUX \(R4,R5,A0 \)\(ASL\);
+  36:	08 c6 3e 40 	BITMUX \(R7,R6,A0 \)\(ASL\);
+
+0000003a <ones>:
+  3a:	06 c6 00 ca 	R5.L=ONES R0;
+  3e:	06 c6 02 ce 	R7.L=ONES R2;
+	...
diff --git a/gas/testsuite/gas/bfin/bit.s b/gas/testsuite/gas/bfin/bit.s
new file mode 100644
index 000000000000..5bf501ab48e6
--- /dev/null
+++ b/gas/testsuite/gas/bfin/bit.s
@@ -0,0 +1,54 @@
+	.text
+	.global bitclr
+bitclr:
+	bitclr(r4, 31);
+	bitCLR (r0, 0);
+
+	.text
+	.global bitset
+bitset:
+	BITSET(R2, 30);
+	BiTsET (r3, 29);
+
+	.text
+	.global bittgl
+bittgl:
+	bitTGL(r7, 22);
+	BITtgl (r6, 16);
+
+	.text
+	.global bittst
+bittst:
+	cc = bittst (r0, 31);
+	CC = BITTST (r1, 0);
+	cC = BittST (r7, 15);
+
+	.text
+	.global deposit
+deposit:
+	R5 = Deposit (r3, r2);
+	r0 = DEPOSIT (r7, R6) (X);
+
+	.text
+	.global extract
+extract:
+	r4 = extract (r2, r1.L) (z);
+	R2 = EXTRACT (r0, r2.l) (Z);
+
+	r7 = ExtracT (r3, r4.L) (X);
+	r5 = ExtRACt (R6, R1.L) (x);
+
+	.text
+	.global bitmux
+bitmux:
+	BITMUX(R1, R0, A0) (ASR);
+	Bitmux (r2, R3, a0) (aSr);
+
+	bitmux (r4, r5, a0) (asl);
+	BiTMux (R7, r6, a0) (ASl);
+
+	.text
+	.global ones
+ones:
+	R5.l = ones r0;
+	r7.L = Ones R2;
diff --git a/gas/testsuite/gas/bfin/bit2.d b/gas/testsuite/gas/bfin/bit2.d
new file mode 100644
index 000000000000..77a4964f1e37
--- /dev/null
+++ b/gas/testsuite/gas/bfin/bit2.d
@@ -0,0 +1,70 @@
+#objdump: -dr
+#name: bit2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	07 4c       	BITCLR \(R7,0x0\);
+   2:	ff 4c       	BITCLR \(R7,0x1f\);
+   4:	7f 4c       	BITCLR \(R7,0xf\);
+   6:	01 4c       	BITCLR \(R1,0x0\);
+   8:	0a 4c       	BITCLR \(R2,0x1\);
+   a:	9b 4c       	BITCLR \(R3,0x13\);
+   c:	07 4a       	BITSET \(R7,0x0\);
+   e:	ff 4a       	BITSET \(R7,0x1f\);
+  10:	7f 4a       	BITSET \(R7,0xf\);
+  12:	01 4a       	BITSET \(R1,0x0\);
+  14:	0a 4a       	BITSET \(R2,0x1\);
+  16:	9b 4a       	BITSET \(R3,0x13\);
+  18:	07 4b       	BITTGL \(R7,0x0\);
+  1a:	ff 4b       	BITTGL \(R7,0x1f\);
+  1c:	7f 4b       	BITTGL \(R7,0xf\);
+  1e:	01 4b       	BITTGL \(R1,0x0\);
+  20:	0a 4b       	BITTGL \(R2,0x1\);
+  22:	9b 4b       	BITTGL \(R3,0x13\);
+  24:	07 49       	CC = BITTST \(R7,0x0\);
+  26:	ff 49       	CC = BITTST \(R7,0x1f\);
+  28:	7f 49       	CC = BITTST \(R7,0xf\);
+  2a:	01 49       	CC = BITTST \(R1,0x0\);
+  2c:	0a 49       	CC = BITTST \(R2,0x1\);
+  2e:	9b 49       	CC = BITTST \(R3,0x13\);
+  30:	07 48       	CC = ! BITTST \(R7,0x0\);
+  32:	ff 48       	CC = ! BITTST \(R7,0x1f\);
+  34:	7f 48       	CC = ! BITTST \(R7,0xf\);
+  36:	01 48       	CC = ! BITTST \(R1,0x0\);
+  38:	0a 48       	CC = ! BITTST \(R2,0x1\);
+  3a:	9b 48       	CC = ! BITTST \(R3,0x13\);
+  3c:	0a c6 08 8e 	R7=DEPOSIT\(R0,R1\);
+  40:	0a c6 0f 8e 	R7=DEPOSIT\(R7,R1\);
+  44:	0a c6 3f 8e 	R7=DEPOSIT\(R7,R7\);
+  48:	0a c6 08 82 	R1=DEPOSIT\(R0,R1\);
+  4c:	0a c6 0f 84 	R2=DEPOSIT\(R7,R1\);
+  50:	0a c6 3f 86 	R3=DEPOSIT\(R7,R7\);
+  54:	0a c6 08 ce 	R7=DEPOSIT\(R0,R1\)\(X\);
+  58:	0a c6 0f ce 	R7=DEPOSIT\(R7,R1\)\(X\);
+  5c:	0a c6 3f ce 	R7=DEPOSIT\(R7,R7\)\(X\);
+  60:	0a c6 08 c2 	R1=DEPOSIT\(R0,R1\)\(X\);
+  64:	0a c6 0f c4 	R2=DEPOSIT\(R7,R1\)\(X\);
+  68:	0a c6 3f c6 	R3=DEPOSIT\(R7,R7\)\(X\);
+  6c:	0a c6 08 0e 	R7=EXTRACT\(R0,R1.L\) \(Z\);
+  70:	0a c6 0f 0e 	R7=EXTRACT\(R7,R1.L\) \(Z\);
+  74:	0a c6 3f 0e 	R7=EXTRACT\(R7,R7.L\) \(Z\);
+  78:	0a c6 08 02 	R1=EXTRACT\(R0,R1.L\) \(Z\);
+  7c:	0a c6 0f 04 	R2=EXTRACT\(R7,R1.L\) \(Z\);
+  80:	0a c6 3f 06 	R3=EXTRACT\(R7,R7.L\) \(Z\);
+  84:	0a c6 08 4e 	R7=EXTRACT\(R0,R1.L\)\(X\);
+  88:	0a c6 0f 4e 	R7=EXTRACT\(R7,R1.L\)\(X\);
+  8c:	0a c6 3f 4e 	R7=EXTRACT\(R7,R7.L\)\(X\);
+  90:	0a c6 08 42 	R1=EXTRACT\(R0,R1.L\)\(X\);
+  94:	0a c6 0f 44 	R2=EXTRACT\(R7,R1.L\)\(X\);
+  98:	0a c6 3f 46 	R3=EXTRACT\(R7,R7.L\)\(X\);
+  9c:	08 c6 01 00 	BITMUX \(R0,R1,A0 \)\(ASR\);
+  a0:	08 c6 02 00 	BITMUX \(R0,R2,A0 \)\(ASR\);
+  a4:	08 c6 0b 00 	BITMUX \(R1,R3,A0 \)\(ASR\);
+  a8:	08 c6 01 40 	BITMUX \(R0,R1,A0 \)\(ASL\);
+  ac:	08 c6 0a 40 	BITMUX \(R1,R2,A0 \)\(ASL\);
+  b0:	06 c6 00 c0 	R0.L=ONES R0;
+  b4:	06 c6 01 c0 	R0.L=ONES R1;
+  b8:	06 c6 06 c2 	R1.L=ONES R6;
+  bc:	06 c6 07 c4 	R2.L=ONES R7;
diff --git a/gas/testsuite/gas/bfin/bit2.s b/gas/testsuite/gas/bfin/bit2.s
new file mode 100755
index 000000000000..1977ef7fe3c6
--- /dev/null
+++ b/gas/testsuite/gas/bfin/bit2.s
@@ -0,0 +1,98 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//8 BIT OPERATIONS

+//

+

+//BITCLR ( Dreg , uimm5 ) ; /* (a) */

+BITCLR ( R7 , 0 ) ;

+BITCLR ( R7 , 31 ) ;

+BITCLR ( R7 , 15 ) ;

+BITCLR ( R1 , 0 ) ;

+BITCLR ( R2 , 1 ) ;

+BITCLR ( R3 , 19 ) ;

+

+//BITSET ( Dreg , uimm5 ) ; /* (a) */

+BITSET ( R7 , 0 ) ;

+BITSET ( R7 , 31 ) ;

+BITSET ( R7 , 15 ) ;

+BITSET ( R1 , 0 ) ;

+BITSET ( R2 , 1 ) ;

+BITSET ( R3 , 19 ) ;

+

+//BITTGL ( Dreg , uimm5 ) ; /* (a) */

+BITTGL ( R7 , 0 ) ;

+BITTGL ( R7 , 31 ) ;

+BITTGL ( R7 , 15 ) ;

+BITTGL ( R1 , 0 ) ;

+BITTGL ( R2 , 1 ) ;

+BITTGL ( R3 , 19 ) ;

+

+//CC = BITTST ( Dreg , uimm5 ) ; /* set CC if bit = 1 (a)*/

+CC = BITTST ( R7 , 0 ) ;

+CC = BITTST ( R7 , 31 ) ;

+CC = BITTST ( R7 , 15 ) ;

+CC = BITTST ( R1 , 0 ) ;

+CC = BITTST ( R2 , 1 ) ;

+CC = BITTST ( R3 , 19 ) ;

+

+//CC = ! BITTST ( Dreg , uimm5 ) ; /* set CC if bit = 0 (a)*/

+CC = !BITTST ( R7 , 0 ) ;

+CC = !BITTST ( R7 , 31 ) ;

+CC = !BITTST ( R7 , 15 ) ;

+CC = !BITTST ( R1 , 0 ) ;

+CC = !BITTST ( R2 , 1 ) ;

+CC = !BITTST ( R3 , 19 ) ;

+

+//Dreg = DEPOSIT ( Dreg, Dreg ) ; /* no extension (b) */

+R7 = DEPOSIT(R0, R1);

+R7 = DEPOSIT(R7, R1);

+R7 = DEPOSIT(R7, R7);

+R1 = DEPOSIT(R0, R1);

+R2 = DEPOSIT(R7, R1);

+R3 = DEPOSIT(R7, R7);

+

+//Dreg = DEPOSIT ( Dreg, Dreg ) (X) ; /* sign-extended (b) */

+R7 = DEPOSIT(R0, R1)(X);

+R7 = DEPOSIT(R7, R1)(X);

+R7 = DEPOSIT(R7, R7)(X);

+R1 = DEPOSIT(R0, R1)(X);

+R2 = DEPOSIT(R7, R1)(X);

+R3 = DEPOSIT(R7, R7)(X);

+

+//Dreg = EXTRACT ( Dreg, Dreg_lo ) (Z) ; /* zero-extended (b)*/

+R7 = EXTRACT(R0, R1.L)(Z);

+R7 = EXTRACT(R7, R1.L)(Z);

+R7 = EXTRACT(R7, R7.L)(Z);

+R1 = EXTRACT(R0, R1.L)(Z);

+R2 = EXTRACT(R7, R1.L)(Z);

+R3 = EXTRACT(R7, R7.L)(Z);

+

+//Dreg = EXTRACT ( Dreg, Dreg_lo ) (X) ; /* sign-extended (b)*/

+R7 = EXTRACT(R0, R1.L)(X);

+R7 = EXTRACT(R7, R1.L)(X);

+R7 = EXTRACT(R7, R7.L)(X);

+R1 = EXTRACT(R0, R1.L)(X);

+R2 = EXTRACT(R7, R1.L)(X);

+R3 = EXTRACT(R7, R7.L)(X);

+

+//BITMUX ( Dreg , Dreg , A0 ) (ASR) ; /* shift right, LSB is shifted out (b) */

+BITMUX(R0, R1, A0)(ASR);

+BITMUX(R0, R2, A0)(ASR);

+BITMUX(R1, R3, A0)(ASR);

+//BITMUX(R0, R0, A0)(ASR);

+

+//BITMUX ( Dreg , Dreg , A0 ) (ASL) ; /* shift left, MSB is shifted out (b) */

+//BITMUX(R0, R0, A0)(ASL);

+BITMUX(R0, R1, A0)(ASL);

+BITMUX(R1, R2, A0)(ASL);

+

+//Dreg_lo = ONES Dreg ; /* (b) */

+R0.L = ONES R0;

+R0.L = ONES R1;

+R1.L = ONES R6;

+R2.L = ONES R7;

+

+

diff --git a/gas/testsuite/gas/bfin/cache.d b/gas/testsuite/gas/bfin/cache.d
new file mode 100644
index 000000000000..4d8d4b33e59d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/cache.d
@@ -0,0 +1,22 @@
+#objdump: -dr
+#name: cache
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <prefetch>:
+   0:	45 02       	PREFETCH\[P5\];
+   2:	67 02       	PREFETCH\[FP\+\+\];
+   4:	46 02       	PREFETCH\[SP\];
+
+00000006 <flush>:
+   6:	52 02       	FLUSH\[P2\];
+   8:	76 02       	FLUSH\[SP\+\+\];
+
+0000000a <flushinv>:
+   a:	6c 02       	FLUSHINV\[P4\+\+\];
+   c:	4f 02       	FLUSHINV\[FP\];
+
+0000000e <iflush>:
+   e:	5b 02       	IFLUSH\[P3\];
+  10:	7f 02       	IFLUSH\[FP\+\+\];
+	...
diff --git a/gas/testsuite/gas/bfin/cache.s b/gas/testsuite/gas/bfin/cache.s
new file mode 100644
index 000000000000..925d809652c7
--- /dev/null
+++ b/gas/testsuite/gas/bfin/cache.s
@@ -0,0 +1,24 @@
+	.text
+	.global prefetch
+prefetch:
+	prefetch[p5];
+	PreFetch [fp++];
+	PREFETCH [SP];
+
+	.text
+	.global flush
+flush:
+	flush[ p2 ];
+	FLUsH [SP++];
+
+	.text
+	.global flushinv
+flushinv:
+	flushinv[ P4 ++ ];
+	FLUshINv [ fp ];
+
+	.text
+	.global iflush
+iflush:
+	iflush[ p3 ];
+	iflush [ fp++ ];
diff --git a/gas/testsuite/gas/bfin/cache2.d b/gas/testsuite/gas/bfin/cache2.d
new file mode 100644
index 000000000000..a6dc7e8cc580
--- /dev/null
+++ b/gas/testsuite/gas/bfin/cache2.d
@@ -0,0 +1,70 @@
+#objdump: -dr
+#name: cache2
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	40 02       	PREFETCH\[P0\];
+   2:	41 02       	PREFETCH\[P1\];
+   4:	42 02       	PREFETCH\[P2\];
+   6:	43 02       	PREFETCH\[P3\];
+   8:	44 02       	PREFETCH\[P4\];
+   a:	45 02       	PREFETCH\[P5\];
+   c:	46 02       	PREFETCH\[SP\];
+   e:	47 02       	PREFETCH\[FP\];
+  10:	60 02       	PREFETCH\[P0\+\+\];
+  12:	61 02       	PREFETCH\[P1\+\+\];
+  14:	62 02       	PREFETCH\[P2\+\+\];
+  16:	63 02       	PREFETCH\[P3\+\+\];
+  18:	64 02       	PREFETCH\[P4\+\+\];
+  1a:	65 02       	PREFETCH\[P5\+\+\];
+  1c:	66 02       	PREFETCH\[SP\+\+\];
+  1e:	67 02       	PREFETCH\[FP\+\+\];
+  20:	50 02       	FLUSH\[P0\];
+  22:	51 02       	FLUSH\[P1\];
+  24:	52 02       	FLUSH\[P2\];
+  26:	53 02       	FLUSH\[P3\];
+  28:	54 02       	FLUSH\[P4\];
+  2a:	55 02       	FLUSH\[P5\];
+  2c:	56 02       	FLUSH\[SP\];
+  2e:	57 02       	FLUSH\[FP\];
+  30:	70 02       	FLUSH\[P0\+\+\];
+  32:	71 02       	FLUSH\[P1\+\+\];
+  34:	72 02       	FLUSH\[P2\+\+\];
+  36:	73 02       	FLUSH\[P3\+\+\];
+  38:	74 02       	FLUSH\[P4\+\+\];
+  3a:	75 02       	FLUSH\[P5\+\+\];
+  3c:	76 02       	FLUSH\[SP\+\+\];
+  3e:	77 02       	FLUSH\[FP\+\+\];
+  40:	48 02       	FLUSHINV\[P0\];
+  42:	49 02       	FLUSHINV\[P1\];
+  44:	4a 02       	FLUSHINV\[P2\];
+  46:	4b 02       	FLUSHINV\[P3\];
+  48:	4c 02       	FLUSHINV\[P4\];
+  4a:	4d 02       	FLUSHINV\[P5\];
+  4c:	4e 02       	FLUSHINV\[SP\];
+  4e:	4f 02       	FLUSHINV\[FP\];
+  50:	68 02       	FLUSHINV\[P0\+\+\];
+  52:	69 02       	FLUSHINV\[P1\+\+\];
+  54:	6a 02       	FLUSHINV\[P2\+\+\];
+  56:	6b 02       	FLUSHINV\[P3\+\+\];
+  58:	6c 02       	FLUSHINV\[P4\+\+\];
+  5a:	6d 02       	FLUSHINV\[P5\+\+\];
+  5c:	6e 02       	FLUSHINV\[SP\+\+\];
+  5e:	6f 02       	FLUSHINV\[FP\+\+\];
+  60:	58 02       	IFLUSH\[P0\];
+  62:	59 02       	IFLUSH\[P1\];
+  64:	5a 02       	IFLUSH\[P2\];
+  66:	5b 02       	IFLUSH\[P3\];
+  68:	5c 02       	IFLUSH\[P4\];
+  6a:	5d 02       	IFLUSH\[P5\];
+  6c:	5e 02       	IFLUSH\[SP\];
+  6e:	5f 02       	IFLUSH\[FP\];
+  70:	78 02       	IFLUSH\[P0\+\+\];
+  72:	79 02       	IFLUSH\[P1\+\+\];
+  74:	7a 02       	IFLUSH\[P2\+\+\];
+  76:	7b 02       	IFLUSH\[P3\+\+\];
+  78:	7c 02       	IFLUSH\[P4\+\+\];
+  7a:	7d 02       	IFLUSH\[P5\+\+\];
+  7c:	7e 02       	IFLUSH\[SP\+\+\];
+  7e:	7f 02       	IFLUSH\[FP\+\+\];
diff --git a/gas/testsuite/gas/bfin/cache2.s b/gas/testsuite/gas/bfin/cache2.s
new file mode 100755
index 000000000000..ed4aa266088e
--- /dev/null
+++ b/gas/testsuite/gas/bfin/cache2.s
@@ -0,0 +1,86 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//12 CACHE CONTROL

+//

+

+//PREFETCH [ Preg ] ; /* indexed (a) */

+PREFETCH [ P0 ] ;

+PREFETCH [ P1 ] ;

+PREFETCH [ P2 ] ;

+PREFETCH [ P3 ] ;

+PREFETCH [ P4 ] ;

+PREFETCH [ P5 ] ;

+PREFETCH [ SP ] ;

+PREFETCH [ FP ] ;

+

+//PREFETCH [ Preg ++ ] ; /* indexed, post increment (a) */

+PREFETCH [ P0++ ] ;

+PREFETCH [ P1++ ] ;

+PREFETCH [ P2++ ] ;

+PREFETCH [ P3++ ] ;

+PREFETCH [ P4++ ] ;

+PREFETCH [ P5++ ] ;

+PREFETCH [ SP++ ] ;

+PREFETCH [ FP++ ] ;

+

+//FLUSH [ Preg ] ; /* indexed (a) */

+FLUSH [ P0 ] ;

+FLUSH [ P1 ] ;

+FLUSH [ P2 ] ;

+FLUSH [ P3 ] ;

+FLUSH [ P4 ] ;

+FLUSH [ P5 ] ;

+FLUSH [ SP ] ;

+FLUSH [ FP ] ;

+//FLUSH [ Preg ++ ] ; /* indexed, post increment (a) */

+FLUSH [ P0++ ] ;

+FLUSH [ P1++ ] ;

+FLUSH [ P2++ ] ;

+FLUSH [ P3++ ] ;

+FLUSH [ P4++ ] ;

+FLUSH [ P5++ ] ;

+FLUSH [ SP++ ] ;

+FLUSH [ FP++ ] ;

+

+//FLUSHINV [ Preg ] ; /* indexed (a) */

+FLUSHINV [ P0 ] ;

+FLUSHINV [ P1 ] ;

+FLUSHINV [ P2 ] ;

+FLUSHINV [ P3 ] ;

+FLUSHINV [ P4 ] ;

+FLUSHINV [ P5 ] ;

+FLUSHINV [ SP ] ;

+FLUSHINV [ FP ] ;

+

+//FLUSHINV [ Preg ++ ] ; /* indexed, post increment (a) */

+FLUSHINV [ P0++ ] ;

+FLUSHINV [ P1++ ] ;

+FLUSHINV [ P2++ ] ;

+FLUSHINV [ P3++ ] ;

+FLUSHINV [ P4++ ] ;

+FLUSHINV [ P5++ ] ;

+FLUSHINV [ SP++ ] ;

+FLUSHINV [ FP++ ] ;

+

+//IFLUSH [ Preg ] ; /* indexed (a) */

+IFLUSH [ P0 ] ;

+IFLUSH [ P1 ] ;

+IFLUSH [ P2 ] ;

+IFLUSH [ P3 ] ;

+IFLUSH [ P4 ] ;

+IFLUSH [ P5 ] ;

+IFLUSH [ SP ] ;

+IFLUSH [ FP ] ;

+

+//IFLUSH [ Preg ++ ] ; /* indexed, post increment (a) */

+IFLUSH [ P0++ ] ;

+IFLUSH [ P1++ ] ;

+IFLUSH [ P2++ ] ;

+IFLUSH [ P3++ ] ;

+IFLUSH [ P4++ ] ;

+IFLUSH [ P5++ ] ;

+IFLUSH [ SP++ ] ;

+IFLUSH [ FP++ ] ;

diff --git a/gas/testsuite/gas/bfin/control_code.d b/gas/testsuite/gas/bfin/control_code.d
new file mode 100644
index 000000000000..71a4563cbf62
--- /dev/null
+++ b/gas/testsuite/gas/bfin/control_code.d
@@ -0,0 +1,62 @@
+#objdump: -dr
+#name: control_code
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <compare_data_register>:
+   0:	06 08       	CC=R6==R0;
+   2:	17 08       	CC=R7==R2;
+   4:	33 0c       	CC=R3==-2;
+   6:	88 08       	CC=R0<R1;
+   8:	a4 0c       	CC=R4<-4;
+   a:	2c 09       	CC=R4<=R5;
+   c:	1d 0d       	CC=R5<=0x3;
+   e:	be 09       	CC=R6<R7\(IU\);
+  10:	a7 0d       	CC=R7<0x4\(IU\);
+  12:	1d 0a       	CC=R5<=R3\(IU\);
+  14:	2a 0e       	CC=R2<=0x5\(IU\);
+
+00000016 <compare_pointer>:
+  16:	46 08       	CC=SP==P0;
+  18:	47 0c       	CC=FP==0x0;
+  1a:	f7 08       	CC=FP<SP;
+  1c:	a1 0c       	CC=R1<-4;
+  1e:	11 09       	CC=R1<=R2;
+  20:	1b 0d       	CC=R3<=0x3;
+  22:	b5 09       	CC=R5<R6\(IU\);
+  24:	bf 0d       	CC=R7<0x7\(IU\);
+  26:	08 0a       	CC=R0<=R1\(IU\);
+  28:	02 0e       	CC=R2<=0x0\(IU\);
+
+0000002a <compare_accumulator>:
+  2a:	80 0a       	CC=A0==A1;
+  2c:	00 0b       	CC=A0<A1;
+  2e:	80 0b       	CC=A0<=A1;
+
+00000030 <move_cc>:
+  30:	00 02       	R0=CC;
+  32:	ac 03       	AC0\|=CC;
+  34:	80 03       	AZ=CC;
+  36:	81 03       	AN=CC;
+  38:	cd 03       	AC1&=CC;
+  3a:	f8 03       	V\^=CC;
+  3c:	98 03       	V=CC;
+  3e:	b9 03       	VS\|=CC;
+  40:	90 03       	AV0=CC;
+  42:	d2 03       	AV1&=CC;
+  44:	93 03       	AV1S=CC;
+  46:	a6 03       	AQ\|=CC;
+  48:	0c 02       	CC=R4;
+  4a:	00 03       	CC = AZ;
+  4c:	21 03       	CC\|=AN;
+  4e:	4c 03       	CC&=AC0;
+  50:	6d 03       	CC\^=AC1;
+  52:	18 03       	CC = V;
+  54:	39 03       	CC\|=VS;
+  56:	50 03       	CC&=AV0;
+  58:	72 03       	CC\^=AV1;
+  5a:	13 03       	CC = AV1S;
+  5c:	26 03       	CC\|=AQ;
+
+0000005e <negate_cc>:
+  5e:	18 02       	CC=!CC;
diff --git a/gas/testsuite/gas/bfin/control_code.s b/gas/testsuite/gas/bfin/control_code.s
new file mode 100644
index 000000000000..ef492a3bef2a
--- /dev/null
+++ b/gas/testsuite/gas/bfin/control_code.s
@@ -0,0 +1,70 @@
+	.text
+	.global compare_data_register
+compare_data_register:
+	cc = r6 == r0;
+	Cc = R7 == r2;
+	CC = R3 == -2;
+	cc = r0 < r1;
+	cC = r4 < -4;
+	Cc = r4 <= R5;
+	cc = r5 <= 3;
+	cc = r6 < r7 (iu);
+	cc = R7 < 4 (iu);
+	CC = r5 <= R3 (Iu);
+	Cc = R2 <= 5 (iU);
+
+	.text
+	.global compare_pointer
+compare_pointer:
+	cc = sp == p0;
+	cC = FP == 0;
+	CC = FP < SP;
+	Cc = r1 < -4;
+	CC = R1 <= R2;
+	cc = r3 <= 3;
+	cC = r5 < R6 (iu);
+	Cc = R7 < 7 (Iu);
+	cC = r0 <= r1 (iU);
+	cc = r2 <= 0 (IU);
+
+	.global compare_accumulator
+	.text
+compare_accumulator:
+	CC = A0 == A1;
+	cc = A0 < a1;
+	cc = a0 <= a1;
+
+	.text
+	.global move_cc
+move_cc:
+	R0 = cc;
+	ac0 |= cc;
+	AZ = Cc;
+	an = Cc;
+	AC1 &= cC;
+	v ^= cc;
+	V = CC;
+	VS |= cC;
+	aV0 = cc;
+	Av1 &= CC;
+	AV1s = cc;
+	AQ |= cc;
+
+	CC = R4;
+	cc = AZ;
+	cc |= An;
+	CC &= Ac0;
+	Cc ^= aC1;
+	CC = V;
+	cC |= vS;
+	Cc &= AV0;
+	cc ^= av1;
+	cc = av1s;
+	cC |= aQ;
+
+
+	.text
+	.global negate_cc
+negate_cc:
+	cc = !cc;
+
diff --git a/gas/testsuite/gas/bfin/control_code2.d b/gas/testsuite/gas/bfin/control_code2.d
new file mode 100644
index 000000000000..15cfdab81a31
--- /dev/null
+++ b/gas/testsuite/gas/bfin/control_code2.d
@@ -0,0 +1,186 @@
+#objdump: -dr
+#name: control_code2
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	07 08       	CC=R7==R0;
+   2:	0e 08       	CC=R6==R1;
+   4:	38 08       	CC=R0==R7;
+   6:	27 0c       	CC=R7==-4;
+   8:	1f 0c       	CC=R7==0x3;
+   a:	20 0c       	CC=R0==-4;
+   c:	18 0c       	CC=R0==0x3;
+   e:	87 08       	CC=R7<R0;
+  10:	86 08       	CC=R6<R0;
+  12:	8f 08       	CC=R7<R1;
+  14:	b9 08       	CC=R1<R7;
+  16:	b0 08       	CC=R0<R6;
+  18:	a7 0c       	CC=R7<-4;
+  1a:	a6 0c       	CC=R6<-4;
+  1c:	9f 0c       	CC=R7<0x3;
+  1e:	99 0c       	CC=R1<0x3;
+  20:	07 09       	CC=R7<=R0;
+  22:	06 09       	CC=R6<=R0;
+  24:	0f 09       	CC=R7<=R1;
+  26:	39 09       	CC=R1<=R7;
+  28:	30 09       	CC=R0<=R6;
+  2a:	27 0d       	CC=R7<=-4;
+  2c:	26 0d       	CC=R6<=-4;
+  2e:	1f 0d       	CC=R7<=0x3;
+  30:	19 0d       	CC=R1<=0x3;
+  32:	87 09       	CC=R7<R0\(IU\);
+  34:	86 09       	CC=R6<R0\(IU\);
+  36:	8f 09       	CC=R7<R1\(IU\);
+  38:	b9 09       	CC=R1<R7\(IU\);
+  3a:	b0 09       	CC=R0<R6\(IU\);
+  3c:	87 0d       	CC=R7<0x0\(IU\);
+  3e:	86 0d       	CC=R6<0x0\(IU\);
+  40:	bf 0d       	CC=R7<0x7\(IU\);
+  42:	b9 0d       	CC=R1<0x7\(IU\);
+  44:	07 0a       	CC=R7<=R0\(IU\);
+  46:	06 0a       	CC=R6<=R0\(IU\);
+  48:	0f 0a       	CC=R7<=R1\(IU\);
+  4a:	39 0a       	CC=R1<=R7\(IU\);
+  4c:	30 0a       	CC=R0<=R6\(IU\);
+  4e:	07 0e       	CC=R7<=0x0\(IU\);
+  50:	06 0e       	CC=R6<=0x0\(IU\);
+  52:	3f 0e       	CC=R7<=0x7\(IU\);
+  54:	39 0e       	CC=R1<=0x7\(IU\);
+  56:	45 08       	CC=P5==P0;
+  58:	4d 08       	CC=P5==P1;
+  5a:	50 08       	CC=P0==P2;
+  5c:	6b 08       	CC=P3==P5;
+  5e:	65 0c       	CC=P5==-4;
+  60:	45 0c       	CC=P5==0x0;
+  62:	5d 0c       	CC=P5==0x3;
+  64:	62 0c       	CC=P2==-4;
+  66:	42 0c       	CC=P2==0x0;
+  68:	5a 0c       	CC=P2==0x3;
+  6a:	c5 08       	CC=P5<P0;
+  6c:	cd 08       	CC=P5<P1;
+  6e:	d0 08       	CC=P0<P2;
+  70:	eb 08       	CC=P3<P5;
+  72:	e5 0c       	CC=P5<-4;
+  74:	c5 0c       	CC=P5<0x0;
+  76:	dd 0c       	CC=P5<0x3;
+  78:	e2 0c       	CC=P2<-4;
+  7a:	c2 0c       	CC=P2<0x0;
+  7c:	da 0c       	CC=P2<0x3;
+  7e:	45 09       	CC=P5<=P0;
+  80:	4d 09       	CC=P5<=P1;
+  82:	50 09       	CC=P0<=P2;
+  84:	6b 09       	CC=P3<=P5;
+  86:	65 0d       	CC=P5<=-4;
+  88:	45 0d       	CC=P5<=0x0;
+  8a:	5d 0d       	CC=P5<=0x3;
+  8c:	62 0d       	CC=P2<=-4;
+  8e:	42 0d       	CC=P2<=0x0;
+  90:	5a 0d       	CC=P2<=0x3;
+  92:	c5 09       	CC=P5<P0\(IU\);
+  94:	cd 09       	CC=P5<P1\(IU\);
+  96:	d0 09       	CC=P0<P2\(IU\);
+  98:	eb 09       	CC=P3<P5\(IU\);
+  9a:	c5 0d       	CC=P5<0x0\(IU\);
+  9c:	fd 0d       	CC=P5<0x7\(IU\);
+  9e:	c2 0d       	CC=P2<0x0\(IU\);
+  a0:	fa 0d       	CC=P2<0x7\(IU\);
+  a2:	45 0a       	CC=P5<=P0\(IU\);
+  a4:	4d 0a       	CC=P5<=P1\(IU\);
+  a6:	50 0a       	CC=P0<=P2\(IU\);
+  a8:	6b 0a       	CC=P3<=P5\(IU\);
+  aa:	45 0e       	CC=P5<=0x0\(IU\);
+  ac:	7d 0e       	CC=P5<=0x7\(IU\);
+  ae:	42 0e       	CC=P2<=0x0\(IU\);
+  b0:	7a 0e       	CC=P2<=0x7\(IU\);
+  b2:	80 0a       	CC=A0==A1;
+  b4:	00 0b       	CC=A0<A1;
+  b6:	80 0b       	CC=A0<=A1;
+  b8:	07 02       	R7=CC;
+  ba:	00 02       	R0=CC;
+  bc:	80 03       	AZ=CC;
+  be:	81 03       	AN=CC;
+  c0:	8c 03       	AC0=CC;
+  c2:	8d 03       	AC1=CC;
+  c4:	99 03       	VS=CC;
+  c6:	90 03       	AV0=CC;
+  c8:	91 03       	AV0S=CC;
+  ca:	92 03       	AV1=CC;
+  cc:	93 03       	AV1S=CC;
+  ce:	86 03       	AQ=CC;
+  d0:	a0 03       	AZ\|=CC;
+  d2:	a1 03       	AN\|=CC;
+  d4:	ac 03       	AC0\|=CC;
+  d6:	ad 03       	AC1\|=CC;
+  d8:	b9 03       	VS\|=CC;
+  da:	b0 03       	AV0\|=CC;
+  dc:	b1 03       	AV0S\|=CC;
+  de:	b2 03       	AV1\|=CC;
+  e0:	b3 03       	AV1S\|=CC;
+  e2:	a6 03       	AQ\|=CC;
+  e4:	c0 03       	AZ&=CC;
+  e6:	c1 03       	AN&=CC;
+  e8:	cc 03       	AC0&=CC;
+  ea:	cd 03       	AC1&=CC;
+  ec:	d9 03       	VS&=CC;
+  ee:	d0 03       	AV0&=CC;
+  f0:	d1 03       	AV0S&=CC;
+  f2:	d2 03       	AV1&=CC;
+  f4:	d3 03       	AV1S&=CC;
+  f6:	c6 03       	AQ&=CC;
+  f8:	e0 03       	AZ\^=CC;
+  fa:	e1 03       	AN\^=CC;
+  fc:	ec 03       	AC0\^=CC;
+  fe:	ed 03       	AC1\^=CC;
+ 100:	f9 03       	VS\^=CC;
+ 102:	f0 03       	AV0\^=CC;
+ 104:	f1 03       	AV0S\^=CC;
+ 106:	f2 03       	AV1\^=CC;
+ 108:	f3 03       	AV1S\^=CC;
+ 10a:	e6 03       	AQ\^=CC;
+ 10c:	0f 02       	CC=R7;
+ 10e:	0e 02       	CC=R6;
+ 110:	09 02       	CC=R1;
+ 112:	08 02       	CC=R0;
+ 114:	00 03       	CC = AZ;
+ 116:	01 03       	CC = AN;
+ 118:	0c 03       	CC = AC0;
+ 11a:	0d 03       	CC = AC1;
+ 11c:	19 03       	CC = VS;
+ 11e:	10 03       	CC = AV0;
+ 120:	11 03       	CC = AV0S;
+ 122:	12 03       	CC = AV1;
+ 124:	13 03       	CC = AV1S;
+ 126:	06 03       	CC = AQ;
+ 128:	20 03       	CC\|=AZ;
+ 12a:	21 03       	CC\|=AN;
+ 12c:	2c 03       	CC\|=AC0;
+ 12e:	2d 03       	CC\|=AC1;
+ 130:	39 03       	CC\|=VS;
+ 132:	30 03       	CC\|=AV0;
+ 134:	31 03       	CC\|=AV0S;
+ 136:	32 03       	CC\|=AV1;
+ 138:	33 03       	CC\|=AV1S;
+ 13a:	26 03       	CC\|=AQ;
+ 13c:	40 03       	CC&=AZ;
+ 13e:	41 03       	CC&=AN;
+ 140:	4c 03       	CC&=AC0;
+ 142:	4d 03       	CC&=AC1;
+ 144:	59 03       	CC&=VS;
+ 146:	50 03       	CC&=AV0;
+ 148:	51 03       	CC&=AV0S;
+ 14a:	52 03       	CC&=AV1;
+ 14c:	53 03       	CC&=AV1S;
+ 14e:	46 03       	CC&=AQ;
+ 150:	60 03       	CC\^=AZ;
+ 152:	61 03       	CC\^=AN;
+ 154:	6c 03       	CC\^=AC0;
+ 156:	6d 03       	CC\^=AC1;
+ 158:	79 03       	CC\^=VS;
+ 15a:	70 03       	CC\^=AV0;
+ 15c:	71 03       	CC\^=AV0S;
+ 15e:	72 03       	CC\^=AV1;
+ 160:	73 03       	CC\^=AV1S;
+ 162:	66 03       	CC\^=AQ;
+ 164:	18 02       	CC=!CC;
+	...
diff --git a/gas/testsuite/gas/bfin/control_code2.s b/gas/testsuite/gas/bfin/control_code2.s
new file mode 100755
index 000000000000..4633bcc281da
--- /dev/null
+++ b/gas/testsuite/gas/bfin/control_code2.s
@@ -0,0 +1,257 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//6 CONTROL CODE BIT MANAGEMENT

+//

+

+//CC = Dreg == Dreg ; /* equal, register, signed (a) */

+CC = R7 == R0;

+CC = R6 == R1;

+CC = R0 == R7;

+

+//CC = Dreg == imm3 ; /* equal, immediate, signed (a) */

+CC = R7 == -4;

+CC = R7 == 3;

+CC = R0 == -4;

+CC = R0 == 3;

+

+//CC = Dreg < Dreg ; /* less than, register, signed (a) */

+CC = R7 < R0;

+CC = R6 < R0;

+CC = R7 < R1;

+CC = R1 < R7;

+CC = R0 < R6;

+

+//CC = Dreg < imm3 ; /* less than, immediate, signed (a) */

+CC = R7 < -4;

+CC = R6 < -4;

+CC = R7 < 3;

+CC = R1 < 3;

+

+//CC = Dreg <= Dreg ; /* less than or equal, register, signed (a) */

+CC = R7 <= R0;

+CC = R6 <= R0;

+CC = R7 <= R1;

+CC = R1 <= R7;

+CC = R0 <= R6;

+

+//CC = Dreg <= imm3 ; /* less than or equal, immediate, signed (a) */

+CC = R7 <= -4;

+CC = R6 <= -4;

+CC = R7 <= 3;

+CC = R1 <= 3;

+

+//CC = Dreg < Dreg (IU) ; /* less than, register, unsigned (a) */

+CC = R7 < R0(IU);

+CC = R6 < R0(IU);

+CC = R7 < R1(IU);

+CC = R1 < R7(IU);

+CC = R0 < R6(IU);

+

+//CC = Dreg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */

+CC = R7 < 0(IU);

+CC = R6 < 0(IU);

+CC = R7 < 7(IU);

+CC = R1 < 7(IU);

+//CC = Dreg <= Dreg (IU) ; /* less than or equal, register, unsigned (a) */

+CC = R7 <= R0(IU);

+CC = R6 <= R0(IU);

+CC = R7 <= R1(IU);

+CC = R1 <= R7(IU);

+CC = R0 <= R6(IU);

+

+

+//CC = Dreg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */

+CC = R7 <= 0(IU);

+CC = R6 <= 0(IU);

+CC = R7 <= 7(IU);

+CC = R1 <= 7(IU);

+

+//CC = Preg == Preg ; /* equal, register, signed (a) */

+CC = P5 == P0;

+CC = P5 == P1;

+CC = P0 == P2;

+CC = P3 == P5;

+

+//CC = Preg == imm3 ; /* equal, immediate, signed (a) */

+CC = P5 == -4;

+CC = P5 == 0;

+CC = P5 == 3;

+CC = P2 == -4;

+CC = P2 == 0;

+CC = P2 == 3;

+

+//CC = Preg < Preg ; /* less than, register, signed (a) */

+CC = P5 < P0;

+CC = P5 < P1;

+CC = P0 < P2;

+CC = P3 < P5;

+

+//CC = Preg < imm3 ; /* less than, immediate, signed (a) */

+CC = P5 < -4;

+CC = P5 < 0;

+CC = P5 < 3;

+CC = P2 < -4;

+CC = P2 < 0;

+CC = P2 < 3;

+

+

+//CC = Preg <= Preg ; /* less than or equal, register, signed (a) */

+CC = P5 <= P0;

+CC = P5 <= P1;

+CC = P0 <= P2;

+CC = P3 <= P5;

+

+//CC = Preg <= imm3 ; /* less than or equal, immediate, signed (a) */

+CC = P5 <= -4;

+CC = P5 <= 0;

+CC = P5 <= 3;

+CC = P2 <= -4;

+CC = P2 <= 0;

+CC = P2 <= 3;

+

+//CC = Preg < Preg (IU) ; /* less than, register, unsigned (a) */

+CC = P5 < P0(IU);

+CC = P5 < P1(IU);

+CC = P0 < P2(IU);

+CC = P3 < P5(IU);

+

+//CC = Preg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */

+CC = P5 < 0(IU);

+CC = P5 < 7(IU);

+CC = P2 < 0(IU);

+CC = P2 < 7(IU);

+

+//CC = Preg <= Preg (IU) ; /* less than or equal, register, unsigned (a) */

+CC = P5 <= P0(IU);

+CC = P5 <= P1(IU);

+CC = P0 <= P2(IU);

+CC = P3 <= P5(IU);

+

+//CC = Preg <= uimm3 (IU) ; /* less than or equal, immediate unsigned (a) */

+CC = P5 <= 0(IU);

+CC = P5 <= 7(IU);

+CC = P2 <= 0(IU);

+CC = P2 <= 7(IU);

+

+CC = A0 == A1 ; /* equal, signed (a) */

+CC = A0 < A1 ; /* less than, Accumulator, signed (a) */

+CC = A0 <= A1 ; /* less than or equal, Accumulator, signed (a) */

+

+//Dreg = CC ; /* CC into 32-bit data register, zero-extended (a) */

+R7 = CC;

+R0 = CC;

+

+//statbit = CC ; /* status bit equals CC (a) */

+AZ = CC;

+AN = CC;

+AC0= CC;

+AC1= CC;

+//V  = CC;

+VS = CC; 

+AV0= CC;

+AV0S= CC; 

+AV1 = CC; 

+AV1S= CC; 

+AQ  = CC;

+//statbit |= CC ; /* status bit equals status bit OR CC (a) */

+AZ |= CC;

+AN |= CC;

+AC0|= CC;

+AC1|= CC;

+//V  |= CC;

+VS |= CC; 

+AV0|= CC;

+AV0S|= CC; 

+AV1 |= CC; 

+AV1S|= CC; 

+AQ  |= CC;

+

+//statbit &= CC ; /* status bit equals status bit AND CC (a) */

+AZ &= CC;

+AN &= CC;

+AC0&= CC;

+AC1&= CC;

+//V  &= CC;

+VS &= CC; 

+AV0&= CC;

+AV0S&= CC; 

+AV1 &= CC; 

+AV1S&= CC; 

+AQ  &= CC;

+

+//statbit ^= CC ; /* status bit equals status bit XOR CC (a) */

+

+AZ ^= CC;

+AN ^= CC;

+AC0^= CC;

+AC1^= CC;

+//V  ^= CC;

+VS ^= CC; 

+AV0^= CC;

+AV0S^= CC; 

+AV1 ^= CC; 

+AV1S^= CC; 

+AQ  ^= CC;

+//CC = Dreg ; /* CC set if the register is non-zero (a) */

+CC = R7;

+CC = R6;

+CC = R1;

+CC = R0;

+

+

+//CC = statbit ; /* CC equals status bit (a) */

+CC = AZ;

+CC = AN;

+CC = AC0;

+CC = AC1;

+//CC = V;

+CC = VS; 

+CC = AV0;

+CC = AV0S; 

+CC = AV1; 

+CC = AV1S; 

+CC = AQ;

+

+//CC |= statbit ; /* CC equals CC OR status bit (a) */

+CC |= AZ;

+CC |= AN;

+CC |= AC0;

+CC |= AC1;

+//CC |= V;

+CC |= VS; 

+CC |= AV0;

+CC |= AV0S; 

+CC |= AV1; 

+CC |= AV1S; 

+CC |= AQ;

+

+//CC &= statbit ; /* CC equals CC AND status bit (a) */

+CC &= AZ;

+CC &= AN;

+CC &= AC0;

+CC &= AC1;

+//CC &= V;

+CC &= VS; 

+CC &= AV0;

+CC &= AV0S; 

+CC &= AV1; 

+CC &= AV1S; 

+CC &= AQ;

+

+//CC ^= statbit ; /* CC equals CC XOR status bit (a) */

+CC ^= AZ;

+CC ^= AN;

+CC ^= AC0;

+CC ^= AC1;

+//CC ^= V;

+CC ^= VS; 

+CC ^= AV0;

+CC ^= AV0S; 

+CC ^= AV1; 

+CC ^= AV1S; 

+CC ^= AQ;

+

+CC = ! CC ; /* (a) */

diff --git a/gas/testsuite/gas/bfin/event.d b/gas/testsuite/gas/bfin/event.d
new file mode 100644
index 000000000000..13c06796e02c
--- /dev/null
+++ b/gas/testsuite/gas/bfin/event.d
@@ -0,0 +1,42 @@
+#objdump: -dr
+#name: event
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <idle>:
+   0:	20 00       	IDLE;
+
+00000002 <csync>:
+   2:	23 00       	CSYNC;
+
+00000004 <ssync>:
+   4:	24 00       	SSYNC;
+
+00000006 <emuexcpt>:
+   6:	25 00       	EMUEXCPT;
+
+00000008 <cli>:
+   8:	37 00       	CLI  R7;
+   a:	30 00       	CLI  R0;
+
+0000000c <sti>:
+   c:	41 00       	STI  R1;
+   e:	42 00       	STI  R2;
+
+00000010 <raise>:
+  10:	9f 00       	RAISE  0xf;
+  12:	90 00       	RAISE  0x0;
+
+00000014 <excpt>:
+  14:	af 00       	EXCPT  0xf;
+  16:	a0 00       	EXCPT  0x0;
+
+00000018 <testset>:
+  18:	b5 00       	TESTSET  \(P5\);
+  1a:	b0 00       	TESTSET  \(P0\);
+
+0000001c <nop>:
+  1c:	00 00       	NOP;
+  1e:	03 c0 00 18 	mnop;
+	...
diff --git a/gas/testsuite/gas/bfin/event.s b/gas/testsuite/gas/bfin/event.s
new file mode 100644
index 000000000000..8e65523ecc99
--- /dev/null
+++ b/gas/testsuite/gas/bfin/event.s
@@ -0,0 +1,56 @@
+	.text
+	.global idle
+idle:
+	IDle;
+
+	.text
+	.global csync
+csync:
+	csync;
+
+	.text
+	.global ssync
+ssync:
+	SSYNC;
+
+	.text
+	.global emuexcpt
+emuexcpt:
+	EMuExCpt;
+
+	.text
+	.global cli
+cli:
+	cli r7;
+	CLI R0;
+
+	.text
+	.global sti
+sti:
+	STI r1;
+	stI r2;
+
+	.text
+	.global raise
+raise:
+	raise 15;
+	RAISE 0;
+
+	.text
+	.global excpt
+excpt:
+	excpt 15;
+	EXCPT 0;
+	
+	.text
+	.global testset
+testset:
+	testset(p5);
+	TESTset (P0);
+
+	.text
+	.global nop
+nop:
+	nop;
+	MNOP;
+
diff --git a/gas/testsuite/gas/bfin/event2.d b/gas/testsuite/gas/bfin/event2.d
new file mode 100644
index 000000000000..d3975ded8d4b
--- /dev/null
+++ b/gas/testsuite/gas/bfin/event2.d
@@ -0,0 +1,28 @@
+#objdump: -dr
+#name: event2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	20 00       	IDLE;
+   2:	23 00       	CSYNC;
+   4:	24 00       	SSYNC;
+   6:	25 00       	EMUEXCPT;
+   8:	30 00       	CLI  R0;
+   a:	31 00       	CLI  R1;
+   c:	32 00       	CLI  R2;
+   e:	40 00       	STI  R0;
+  10:	41 00       	STI  R1;
+  12:	42 00       	STI  R2;
+  14:	90 00       	RAISE  0x0;
+  16:	94 00       	RAISE  0x4;
+  18:	9f 00       	RAISE  0xf;
+  1a:	a0 00       	EXCPT  0x0;
+  1c:	a1 00       	EXCPT  0x1;
+  1e:	af 00       	EXCPT  0xf;
+  20:	b0 00       	TESTSET  \(P0\);
+  22:	b1 00       	TESTSET  \(P1\);
+  24:	b2 00       	TESTSET  \(P2\);
+  26:	00 00       	NOP;
+  28:	03 c0 00 18 	mnop;
diff --git a/gas/testsuite/gas/bfin/event2.s b/gas/testsuite/gas/bfin/event2.s
new file mode 100755
index 000000000000..c0a6fc365578
--- /dev/null
+++ b/gas/testsuite/gas/bfin/event2.s
@@ -0,0 +1,41 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//11 EXTERNAL EVENT MANAGEMENT

+//

+IDLE ; /* (a) */

+CSYNC ; /* (a) */

+SSYNC ; /* (a) */

+EMUEXCPT ; /* (a) */

+

+//CLI Dreg ; /* previous state of IMASK moved to Dreg (a) */

+CLI R0;

+CLI R1;

+CLI R2;

+

+//STI Dreg ; /* previous state of IMASK restored from Dreg (a) */

+STI R0;

+STI R1;

+STI R2;

+

+//RAISE uimm4 ; /* (a) */

+RAISE 0;

+RAISE 4;

+RAISE 15;

+

+//EXCPT uimm4 ; /* (a) */

+EXCPT 0;

+EXCPT 1;

+EXCPT 15;

+

+//TESTSET ( Preg ) ; /* (a) */

+TESTSET (P0);

+TESTSET (P1);

+TESTSET (P2);

+//TESTSET (SP);

+//TESTSET (FP);

+

+NOP ; /* (a) */

+MNOP ; /* (b) */

diff --git a/gas/testsuite/gas/bfin/expected_errors.l b/gas/testsuite/gas/bfin/expected_errors.l
new file mode 100644
index 000000000000..d20b3f7a3df7
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_errors.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:3: Error: Constant out of range.
+.*:4: Error: Constant out of range.
+.*:6: Error: Bad constant value.
+.*:7: Error: Bad constant value.
+.*:8: Error: Bad constant value.
+.*:9: Error: Bad constant value.
+.*:10: Error: Bad constant value.
+.*:11: Error: Bad constant value.
+.*:13: Error: Dregs expected. Input text was R3.L.
diff --git a/gas/testsuite/gas/bfin/expected_errors.s b/gas/testsuite/gas/bfin/expected_errors.s
new file mode 100644
index 000000000000..005570d89acf
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_errors.s
@@ -0,0 +1,13 @@
+	.text
+
+	p0.H = 0x12345678;
+	P0.l = 0x12345678;
+
+	CC = R3 < 4;
+	CC = R3 < 7;
+	CC = R3 < 8;
+	CC = R3 <= 4;
+	CC = R3 <= 7;
+	CC = R3 <= 8;
+
+	A1 -= M2.h * R3.L, A0 -= M2.l * R3.L;
diff --git a/gas/testsuite/gas/bfin/expected_move_errors.l b/gas/testsuite/gas/bfin/expected_move_errors.l
new file mode 100644
index 000000000000..9b8b1aa15bf5
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_move_errors.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:3: Error: Cannot move A1 to low half of register. Input text was A1.
+.*:4: Error: Cannot move A0 to high half of register. Input text was A0.
+.*:5: Error: Cannot move A1 to even register.
+.*:6: Error: Cannot move A0 to odd register.
diff --git a/gas/testsuite/gas/bfin/expected_move_errors.s b/gas/testsuite/gas/bfin/expected_move_errors.s
new file mode 100644
index 000000000000..d73525f935e0
--- /dev/null
+++ b/gas/testsuite/gas/bfin/expected_move_errors.s
@@ -0,0 +1,6 @@
+	.text
+
+	R0.L = A1;
+	R0.H = A0;
+	R0 = A1;
+	R1 = A0;
diff --git a/gas/testsuite/gas/bfin/flow.d b/gas/testsuite/gas/bfin/flow.d
new file mode 100644
index 000000000000..9c5c8252bfca
--- /dev/null
+++ b/gas/testsuite/gas/bfin/flow.d
@@ -0,0 +1,96 @@
+#objdump: -d
+#name: flow
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <jump>:
+   0:	55 00       	JUMP  \(P5\);
+   2:	83 00       	JUMP  \(PC\+P3\);
+   4:	00 20       	JUMP.S  4.*
+   6:	80 e2 00 00 	JUMP.L  ff000006.*
+   a:	7f e2 ff ff 	JUMP.L  1000008.*
+   e:	ff 27       	JUMP.S  100c.*
+  10:	7f e2 00 80 	JUMP.L  ff0010.*
+  14:	f6 2f       	JUMP.S  0 <jump>;
+
+00000016 <ccjump>:
+  16:	00 1a       	IF CC JUMP fffffc16.*
+  18:	ff 1d       	IF CC JUMP 416.*\(BP\);
+  1a:	00 16       	IF ! CC JUMP fffffc1a.*\(BP\);
+  1c:	89 10       	IF ! CC JUMP 12e.*
+  1e:	f1 1b       	IF CC JUMP 0 <jump>;
+  20:	f0 1f       	IF CC JUMP 0 <jump>\(BP\);
+  22:	ef 17       	IF ! CC JUMP 0 <jump>\(BP\);
+  24:	ee 13       	IF ! CC JUMP 0 <jump>;
+
+00000026 <call>:
+  26:	63 00       	CALL  \(P3\);
+  28:	72 00       	CALL  \(PC\+P2\);
+  2a:	80 e3 00 00 	CALL  ff00002a.*
+  2e:	7f e3 ff ff 	CALL  100002c.*
+  32:	ff e3 e7 ff 	CALL  0 <jump>;
+
+00000036 <return>:
+  36:	10 00       	RTS;
+  38:	11 00       	RTI;
+  3a:	12 00       	RTX;
+  3c:	13 00       	RTN;
+  3e:	14 00       	RTE;
+
+00000040 <loop_lc0>:
+  40:	82 e0 13 00 	LSETUP\(44 <first_loop__BEGIN>,66 <first_loop__END>\)LC0;
+
+00000044 <first_loop__BEGIN>:
+  44:	38 e4 7b fc 	R0=\[FP\+-3604\];
+  48:	49 60       	R1=0x9\(x\);
+  4a:	38 e4 7b fc 	R0=\[FP\+-3604\];
+  4e:	00 32       	P0=R0;
+  50:	42 44       	P2=P0<<2;
+  52:	ba 5a       	P2=P2\+FP;
+  54:	20 e1 50 fb 	R0=-1200 \(X\);
+  58:	08 32       	P1=R0;
+  5a:	8a 5a       	P2=P2\+P1;
+  5c:	00 60       	R0=0x0\(x\);
+  5e:	10 93       	\[P2\]=R0;
+  60:	38 e4 7b fc 	R0=\[FP\+-3604\];
+  64:	08 64       	R0\+=0x1;
+
+00000066 <first_loop__END>:
+  66:	38 e6 7b fc 	\[FP\+-3604\]=R0;
+  6a:	a2 e0 02 40 	LSETUP\(6e <second_loop__BEGIN>,6e <second_loop__BEGIN>\)LC0=P4;
+
+0000006e <second_loop__BEGIN>:
+  6e:	00 00       	NOP;
+  70:	e0 e0 00 10 	LSETUP\(70 <second_loop__BEGIN\+0x2>,70 <second_loop__BEGIN\+0x2>\)LC0=P1>>1;
+  74:	82 e0 ff 03 	LSETUP\(78 <second_loop__BEGIN\+0xa>,72 <second_loop__BEGIN\+0x4>\)LC0;
+  78:	af e0 00 52 	LSETUP\(76 <second_loop__BEGIN\+0x8>,fffffc78 <another_loop__END\+0xfffffbba>\)LC0=P5;
+  7c:	ef e0 02 00 	LSETUP\(7a <second_loop__BEGIN\+0xc>,80 <loop_lc1>\)LC0=P0>>1;
+
+00000080 <loop_lc1>:
+  80:	90 e0 00 00 	LSETUP\(80 <loop_lc1>,80 <loop_lc1>\)LC1;
+  84:	b0 e0 00 40 	LSETUP\(84 <loop_lc1\+0x4>,84 <loop_lc1\+0x4>\)LC1=P4;
+  88:	f8 e0 1b 10 	LSETUP\(78 <second_loop__BEGIN\+0xa>,be <another_loop__END>\)LC1=P1>>1;
+  8c:	92 e0 ff 03 	LSETUP\(90 <loop_lc1\+0x10>,8a <loop_lc1\+0xa>\)LC1;
+  90:	bf e0 00 52 	LSETUP\(8e <loop_lc1\+0xe>,fffffc90 <another_loop__END\+0xfffffbd2>\)LC1=P5;
+  94:	ff e0 02 00 	LSETUP\(92 <loop_lc1\+0x12>,98 <another_loop__BEGIN>\)LC1=P0>>1;
+
+00000098 <another_loop__BEGIN>:
+  98:	38 e4 7a fc 	R0=\[FP\+-3608\];
+  9c:	00 32       	P0=R0;
+  9e:	42 44       	P2=P0<<2;
+  a0:	ba 5a       	P2=P2\+FP;
+  a2:	20 e1 f0 f1 	R0=-3600 \(X\);
+  a6:	00 32       	P0=R0;
+  a8:	42 5a       	P1=P2\+P0;
+  aa:	38 e4 7a fc 	R0=\[FP\+-3608\];
+  ae:	00 32       	P0=R0;
+  b0:	42 44       	P2=P0<<2;
+  b2:	ba 5a       	P2=P2\+FP;
+  b4:	20 e1 50 fb 	R0=-1200 \(X\);
+  b8:	00 32       	P0=R0;
+  ba:	82 5a       	P2=P2\+P0;
+  bc:	10 91       	R0=\[P2\];
+
+000000be <another_loop__END>:
+  be:	08 93       	\[P1\]=R0;
diff --git a/gas/testsuite/gas/bfin/flow.s b/gas/testsuite/gas/bfin/flow.s
new file mode 100644
index 000000000000..b13016090d87
--- /dev/null
+++ b/gas/testsuite/gas/bfin/flow.s
@@ -0,0 +1,109 @@
+	 .data
+foodata:	.word 42
+	.text
+footext:
+	.text
+	.global jump
+jump:
+	jump(P5);
+	Jump (pc + p3);
+	jUMp (0);
+	JumP.l (-16777216);
+	jumP.L (0x00fffffe);
+	JUMP.s (4094);
+	JUMP.L (0X00FF0000);
+	jump (footext);
+
+	.text
+	.global ccjump
+ccjump:
+	if cc jump (-1024);
+	IF CC JUMP (1022) (BP);
+	if !cc jump (0xffffFc00) (Bp);
+	if !cc jumP (0x0112);
+	if cC JuMp (footext);
+	if CC jUmP (footext) (bp);
+	if !cc jump (FOOTEXT) (bP);
+	if !Cc JUMP (FooText);
+
+	.text
+	.global call
+call:
+	call (P3);
+	Call (PC+p2);
+	cALL (0xff000000);
+	CalL(0x00FFFFFe);
+	CAll call_test;
+
+
+	.text
+	.global return
+return:
+	rts;
+	rTi;
+	rtX;
+	Rtn;
+	RTE;
+
+	.text
+	
+	.text
+	.global loop_lc0
+loop_lc0:
+	loop first_loop lc0;
+	Loop_Begin first_loop;
+	R0 = [FP+-3604];
+	R1 = 9 (X);
+	R0 = [FP+-3604];
+	P0 = R0;
+	P2 = P0 << 2;
+	P2 = P2 + FP;
+	R0 = -1200 (X);
+	P1 = R0;
+	P2 = P2 + P1;
+	R0 = 0 (X);
+	[P2] = R0;
+	R0 = [FP+-3604];
+	R0 += 1;
+	[FP+-3604] = R0;
+	LOOP_END first_loop;
+
+	lOOP second_loop Lc0 = P4;
+	Loop_Begin second_loop;
+	NOP;
+	Loop_End second_loop;
+
+	LOOP third_loop lC0 = P1 >> 1;
+
+	Lsetup (4, 2046) Lc0;
+	LSETUP(30, 1024) LC0 = P5;
+	LSeTuP (30, 4) lc0 = p0 >> 1;
+
+
+	.global loop_lc1
+loop_lc1:
+	loop my_loop lc1;
+	lOOP other_loop Lc1 = P4;
+	LOOP another_loop lC1 = P1 >> 1;
+
+	Lsetup (4, 2046) Lc1;
+	LSETUP (30, 1024) LC1 = P5;
+	LSeTuP (30, 4) lc1 = p0 >> 1;
+	Loop_Begin another_loop;
+	R0 = [FP+-3608];
+	P0 = R0;
+	P2 = P0 << 2;
+	P2 = P2 + FP;
+	R0 = -3600 (X);
+	P0 = R0;
+	P1 = P2 + P0;
+	R0 = [FP+-3608];
+	P0 = R0;
+	P2 = P0 << 2;
+	P2 = P2 + FP;
+	R0 = -1200 (X);
+	P0 = R0;
+	P2 = P2 + P0;
+	R0 = [P2];
+	[P1] = R0;
+	LOOP_END another_loop;
diff --git a/gas/testsuite/gas/bfin/flow2.d b/gas/testsuite/gas/bfin/flow2.d
new file mode 100644
index 000000000000..1ffe7c3eae3d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/flow2.d
@@ -0,0 +1,114 @@
+#objdump: -d
+#name: flow2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <MY_LABEL1-0x2a>:
+   0:	50 00       	JUMP  \(P0\);
+   2:	51 00       	JUMP  \(P1\);
+   4:	52 00       	JUMP  \(P2\);
+   6:	53 00       	JUMP  \(P3\);
+   8:	54 00       	JUMP  \(P4\);
+   a:	55 00       	JUMP  \(P5\);
+   c:	56 00       	JUMP  \(SP\);
+   e:	57 00       	JUMP  \(FP\);
+  10:	80 00       	JUMP  \(PC\+P0\);
+  12:	81 00       	JUMP  \(PC\+P1\);
+  14:	82 00       	JUMP  \(PC\+P2\);
+  16:	83 00       	JUMP  \(PC\+P3\);
+  18:	84 00       	JUMP  \(PC\+P4\);
+  1a:	85 00       	JUMP  \(PC\+P5\);
+  1c:	86 00       	JUMP  \(PC\+SP\);
+  1e:	87 00       	JUMP  \(PC\+FP\);
+  20:	00 20       	JUMP.S  20 <MY_LABEL1-0xa>;
+  22:	69 22       	JUMP.S  4f4.*
+  24:	97 2d       	JUMP.S  fffffb52.*
+  26:	01 20       	JUMP.S  28 <MY_LABEL1-0x2>;
+  28:	ff 2f       	JUMP.S  26 <MY_LABEL1-0x4>;
+
+0000002a <MY_LABEL1>:
+  2a:	00 20       	JUMP.S  2a <MY_LABEL1>;
+  2c:	69 22       	JUMP.S  4fe.*
+  2e:	97 2d       	JUMP.S  fffffb5c.*
+  30:	01 20       	JUMP.S  32 <MY_LABEL1\+0x8>;
+  32:	ff 2f       	JUMP.S  30 <MY_LABEL1\+0x6>;
+  34:	c0 e2 00 00 	JUMP.L  ff800034.*
+  38:	3f e2 ff ff 	JUMP.L  800036.*
+  3c:	00 e2 00 00 	JUMP.L  3c <MY_LABEL1\+0x12>;
+  40:	00 e2 69 02 	JUMP.L  512.*
+  44:	ff e2 97 fd 	JUMP.L  fffffb72.*
+  48:	00 e2 01 00 	JUMP.L  4a <MY_LABEL1\+0x20>;
+  4c:	ff e2 ff ff 	JUMP.L  4a <MY_LABEL1\+0x20>;
+  50:	ed 2f       	JUMP.S  2a <MY_LABEL1>;
+  52:	d7 2f       	JUMP.S  0 .*
+  54:	d6 2f       	JUMP.S  0 .*
+  56:	d5 2f       	JUMP.S  0 .*
+  58:	04 1b       	IF CC JUMP fffffe60.*
+  5a:	5a 18       	IF CC JUMP 10e.*
+  5c:	00 18       	IF CC JUMP 5c <MY_LABEL1\+0x32>;
+  5e:	04 1f       	IF CC JUMP fffffe66.*\(BP\);
+  60:	5a 1c       	IF CC JUMP 114.*\(BP\);
+  62:	91 13       	IF ! CC JUMP ffffff84.*;
+  64:	90 10       	IF ! CC JUMP 184.*;
+  66:	91 17       	IF ! CC JUMP ffffff88.*\(BP\);
+  68:	90 14       	IF ! CC JUMP 188.*\(BP\);
+  6a:	e0 1b       	IF CC JUMP 2a <MY_LABEL1>;
+  6c:	ca 1b       	IF CC JUMP 0 <MY_LABEL1-0x2a>;
+  6e:	de 1f       	IF CC JUMP 2a <MY_LABEL1>\(BP\);
+  70:	c8 1f       	IF CC JUMP 0 <MY_LABEL1-0x2a>\(BP\);
+  72:	dc 13       	IF ! CC JUMP 2a <MY_LABEL1>;
+  74:	c6 13       	IF ! CC JUMP 0 <MY_LABEL1-0x2a>;
+  76:	da 17       	IF ! CC JUMP 2a <MY_LABEL1>\(BP\);
+  78:	c4 17       	IF ! CC JUMP 0 <MY_LABEL1-0x2a>\(BP\);
+  7a:	60 00       	CALL  \(P0\);
+  7c:	61 00       	CALL  \(P1\);
+  7e:	62 00       	CALL  \(P2\);
+  80:	63 00       	CALL  \(P3\);
+  82:	64 00       	CALL  \(P4\);
+  84:	65 00       	CALL  \(P5\);
+  86:	70 00       	CALL  \(PC\+P0\);
+  88:	71 00       	CALL  \(PC\+P1\);
+  8a:	72 00       	CALL  \(PC\+P2\);
+  8c:	73 00       	CALL  \(PC\+P3\);
+  8e:	74 00       	CALL  \(PC\+P4\);
+  90:	75 00       	CALL  \(PC\+P5\);
+  92:	09 e3 2b 1a 	CALL  1234e8.*;
+  96:	ff e3 97 fd 	CALL  fffffbc4.*;
+  9a:	ff e3 c8 ff 	CALL  2a <MY_LABEL1>;
+  9e:	ff e3 b1 ff 	CALL  0 <MY_LABEL1-0x2a>;
+  a2:	10 00       	RTS;
+  a4:	11 00       	RTI;
+  a6:	12 00       	RTX;
+  a8:	13 00       	RTN;
+  aa:	14 00       	RTE;
+  ac:	82 e0 02 00 	LSETUP\(b0 <MY_LABEL1\+0x86>,b0 <MY_LABEL1\+0x86>\)LC0;
+  b0:	84 e0 06 00 	LSETUP\(b8 <beg_poll_bit>,bc <end_poll_bit>\)LC0;
+  b4:	00 00       	NOP;
+	...
+
+000000b8 <beg_poll_bit>:
+  b8:	80 e1 01 00 	R0=1 <MY_LABEL1-0x29>\(Z\);
+
+000000bc <end_poll_bit>:
+  bc:	81 e1 02 00 	R1=2 <MY_LABEL1-0x28>\(Z\);
+  c0:	92 e0 03 00 	LSETUP\(c4 <end_poll_bit\+0x8>,c6 <end_poll_bit\+0xa>\)LC1;
+  c4:	93 e0 05 00 	LSETUP\(ca <FIR_filter>,ce <bottom_of_FIR_filter>\)LC1;
+	...
+
+000000ca <FIR_filter>:
+  ca:	80 e1 01 00 	R0=1 <MY_LABEL1-0x29>\(Z\);
+
+000000ce <bottom_of_FIR_filter>:
+  ce:	81 e1 02 00 	R1=2 <MY_LABEL1-0x28>\(Z\);
+  d2:	a2 e0 04 10 	LSETUP\(d6 <bottom_of_FIR_filter\+0x8>,da <bottom_of_FIR_filter\+0xc>\)LC0=P1;
+  d6:	e2 e0 04 10 	LSETUP\(da <bottom_of_FIR_filter\+0xc>,de <DoItSome__BEGIN>\)LC0=P1>>1;
+  da:	82 e0 03 00 	LSETUP\(de <DoItSome__BEGIN>,e0 <DoItSome__END>\)LC0;
+
+000000de <DoItSome__BEGIN>:
+  de:	08 60       	R0=0x1\(x\);
+
+000000e0 <DoItSome__END>:
+  e0:	11 60       	R1=0x2\(x\);
+  e2:	90 e0 00 00 	LSETUP\(e2 <DoItSome__END\+0x2>,e2 <DoItSome__END\+0x2>\)LC1;
+	...
diff --git a/gas/testsuite/gas/bfin/flow2.s b/gas/testsuite/gas/bfin/flow2.s
new file mode 100755
index 000000000000..7ae355100a00
--- /dev/null
+++ b/gas/testsuite/gas/bfin/flow2.s
@@ -0,0 +1,155 @@
+
+.EXTERN MY_LABEL2;
+.section .text;
+
+//
+//2 Program Flow Control
+//
+
+
+//JUMP ( Preg ) ; /* indirect to an absolute (not PC-relative)address (a) */
+//Preg: P5-0, SP, FP
+
+JUMP (P0);
+JUMP (P1);
+JUMP (P2);
+JUMP (P3);
+JUMP (P4);
+JUMP (P5);
+JUMP (SP);
+JUMP (FP);
+
+//JUMP ( PC + Preg ) ; /* PC-relative, indexed (a) */
+JUMP (PC+P0);
+JUMP (PC+P1);
+JUMP (PC+P2);
+JUMP (PC+P3);
+JUMP (PC+P4);
+JUMP (PC+P5);
+JUMP (PC+SP);
+JUMP (PC+FP);
+
+
+//JUMP pcrelm2 ; /* PC-relative, immediate (a) or (b) */
+
+JUMP 0X0;
+JUMP 1234;
+JUMP -1234;
+JUMP 2;
+JUMP -2;
+
+MY_LABEL1:
+//JUMP.S pcrel13m2 ; /* PC-relative, immediate, short (a) */
+JUMP.S 0X0;
+JUMP.S 1234;
+JUMP.S -1234;
+JUMP.S 2;
+JUMP.S -2;
+
+//JUMP.L pcrel25m2 ; /* PC-relative, immediate, long (b) */
+JUMP.L 0XFF800000;
+JUMP.L 0X007FFFFE;
+JUMP.L 0X0;
+JUMP.L 1234;
+JUMP.L -1234;
+JUMP.L 2;
+JUMP.L -2;
+
+//JUMP user_label ; /* user-defined absolute address label, */
+JUMP MY_LABEL1;
+JUMP MY_LABEL2;
+
+JUMP MY_LABEL1-2;
+JUMP MY_LABEL2-2;
+
+//IF CC JUMP pcrel11m2 ; /* branch if CC=1, branch predicted as not taken (a) */
+IF CC JUMP 0xFFFFFE08;
+IF CC JUMP 0x0B4;
+IF CC JUMP 0;
+
+//IF CC JUMP pcrel11m2 (bp) ; /* branch if CC=1, branch predicted as taken (a) */
+IF CC JUMP 0xFFFFFE08(bp);
+IF CC JUMP 0x0B4(bp);
+
+//IF !CC JUMP pcrel11m2 ; /* branch if CC=0, branch predicted as not taken (a) */
+IF !CC JUMP 0xFFFFFF22;
+IF !CC JUMP 0X120;
+
+//IF !CC JUMP pcrel11m2 (bp) ; /* branch if CC=0, branch predicted as taken (a) */
+IF !CC JUMP 0xFFFFFF22(bp);
+IF !CC JUMP 0X120(bp);
+
+//IF CC JUMP user_label ; /* user-defined absolute address label, resolved by the assembler/linker to the appropriate PC-relative instruction (a) */
+IF CC JUMP MY_LABEL1;
+IF CC JUMP MY_LABEL2;
+
+//IF CC JUMP user_label (bp) ; /* user-defined absolute address label, resolved by the assembler/linker to the appropriate PC-relative instruction (a) */
+IF CC JUMP MY_LABEL1(bp);
+IF CC JUMP MY_LABEL2(bp);
+
+//IF !CC JUMP user_label ; /* user-defined absolute address label, resolved by the assembler/linker to the appropriate PC-relative instruction (a) */
+IF !CC JUMP MY_LABEL1;
+IF !CC JUMP MY_LABEL2;
+
+//IF !CC JUMP user_label (bp) ; /* user-defined absolute address label, resolved by the assembler/linker to the appropriate PC-relative instruction (a) */
+IF !CC JUMP MY_LABEL1(bp);
+IF !CC JUMP MY_LABEL2(bp);
+
+//CALL ( Preg ) ; /* indirect to an absolute (not PC-relative) address (a) */
+CALL(P0);
+CALL(P1);
+CALL(P2);
+CALL(P3);
+CALL(P4);
+CALL(P5);
+
+
+//CALL ( PC + Preg ) ; /* PC-relative, indexed (a) */
+CALL(PC+P0);
+CALL(PC+P1);
+CALL(PC+P2);
+CALL(PC+P3);
+CALL(PC+P4);
+CALL(PC+P5);
+
+//CALL pcrel25m2 ; /* PC-relative, immediate (b) */
+CALL 0x123456 ;
+CALL -1234;
+
+//CALL user_label ; /* user-defined absolute address label,resolved by the assembler/linker to the appropriate PC-relative instruction (a) or (b) */
+CALL MY_LABEL1;
+CALL MY_LABEL2;
+
+RTS ; // Return from Subroutine (a)
+RTI ; // Return from Interrupt (a)
+RTX ; // Return from Exception (a)
+RTN ; // Return from NMI (a)
+RTE ; // Return from Emulation (a)
+
+lsetup ( 4, 4 ) lc0 ;
+
+lsetup ( beg_poll_bit, end_poll_bit ) lc0 ;
+NOP;NOP;
+beg_poll_bit: R0=1(Z);
+end_poll_bit: R1=2(Z);
+
+lsetup ( 4, 6 ) lc1 ;
+
+lsetup ( FIR_filter, bottom_of_FIR_filter ) lc1 ;
+NOP;
+FIR_filter: R0=1(Z);
+bottom_of_FIR_filter: R1=2(Z);
+
+lsetup ( 4, 8 ) lc0 = p1 ;
+
+lsetup ( 4, 8 ) lc0 = p1>>1 ;
+
+loop DoItSome LC0 ; /* define loop DoItSome with Loop Counter 0 */
+loop_begin DoItSome ; /* place before the first instruction in the loop */
+R0=1;
+R1=2;
+loop_end DoItSome ; /* place after the last instruction in the loop */
+
+loop DoItSomeMore LC1 ; /* define loop MyLoop with Loop Counter 1*/
+
+
diff --git a/gas/testsuite/gas/bfin/load.d b/gas/testsuite/gas/bfin/load.d
new file mode 100644
index 000000000000..58d97c2a82f4
--- /dev/null
+++ b/gas/testsuite/gas/bfin/load.d
@@ -0,0 +1,114 @@
+#objdump: -d
+#name: load
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <load_immediate>:
+   0:	17 e1 ff ff 	M3.L=ffff.*
+   4:	1a e1 fe ff 	B2.L=fffe.*
+   8:	0e e1 00 00 	SP.L=0.*
+   c:	0f e1 dc fe 	FP.L=fedc.*
+  10:	40 e1 02 00 	R0.H=0x2;
+  14:	4d e1 20 00 	P5.H=20.*
+  18:	52 e1 04 f2 	I2.H=f204.*
+  1c:	59 e1 40 00 	B1.H=40.*
+  20:	5c e1 ff ff 	L0.H=ffff.*
+  24:	45 e1 00 00 	R5.H=0x0;
+  28:	5a e1 00 00 	B2.H=0 <load_immediate>;
+  2c:	8f e1 20 ff 	FP=ff20.*
+  30:	9e e1 20 00 	L2=20.*
+  34:	85 e1 00 00 	R5=0 <load_immediate>\(Z\);
+  38:	08 c4 [0-3][[:xdigit:]] 00 	A0=0;
+  3c:	08 c4 [0-3][[:xdigit:]] 40 	A1=0;
+  40:	08 c4 [0-3][[:xdigit:]] 80 	A1=A0=0;
+  44:	02 62       	R2=-64\(x\);
+  46:	20 e1 7f 00 	R0=0x7f \(X\);
+  4a:	02 68       	P2=0x0;
+  4c:	06 6b       	SP=-32;
+  4e:	67 69       	FP=0x2c;
+  50:	3f e1 00 08 	L3=0x800 \(X\);
+  54:	36 e1 ff 7f 	M2=0x7fff \(X\);
+  58:	81 60       	R1=0x10\(x\);
+  5a:	3c e1 00 00 	L0=0x0 \(X\);
+  5e:	27 e1 eb 00 	R7=0xeb \(X\);
+
+00000062 <load_pointer_register>:
+  62:	7e 91       	SP=\[FP\];
+  64:	47 90       	FP=\[P0\+\+\];
+  66:	f1 90       	P1=\[SP--\];
+  68:	96 af       	SP=\[P2\+0x38\];
+  6a:	3b ac       	P3=\[FP\+0x0];
+  6c:	3c e5 ff 7f 	P4=\[FP\+0x1fffc\];
+  70:	3e e5 01 80 	SP=\[FP\+-131068\];
+  74:	26 ac       	SP=\[P4\+0x0\];
+  76:	0d b8       	P5=\[FP-128\];
+
+00000078 <load_data_register>:
+  78:	07 91       	R7=\[P0\];
+  7a:	2e 90       	R6=\[P5\+\+\];
+  7c:	a5 90       	R5=\[P4--\];
+  7e:	bc a2       	R4=\[FP\+0x28\];
+  80:	33 e4 ff 7f 	R3=\[SP\+0x1fffc\];
+  84:	32 a0       	R2=\[SP\+0x0\];
+  86:	39 e4 01 80 	R1=\[FP\+-131068\];
+  8a:	06 80       	R0=\[SP\+\+P0\];
+  8c:	05 b8       	R5=\[FP-128\];
+  8e:	02 9d       	R2=\[I0\];
+  90:	09 9c       	R1=\[I1\+\+\];
+  92:	93 9c       	R3=\[I2--\];
+  94:	9c 9d       	R4=\[I3\+\+M0\];
+
+00000096 <load_half_word_zero_extend>:
+  96:	37 95       	R7=W\[SP\] \(Z\);
+  98:	3e 94       	R6=W\[FP\+\+\] \(Z\);
+  9a:	85 94       	R5=W\[P0--\] \(Z\);
+  9c:	cc a7       	R4=W\[P1\+0x1e\] \(Z\);
+  9e:	73 e4 fe 7f 	R3=W\[SP\+0xfffc\] \(Z\);
+  a2:	7a e4 02 80 	R2=W\[FP\+-65532\] \(Z\);
+  a6:	28 86       	R0=W\[P0\+\+P5\] \(Z\);
+
+000000a8 <load_half_word_sign_extend>:
+  a8:	77 95       	R7=W\[SP\]\(X\);
+  aa:	7e 94       	R6=W\[FP\+\+\]\(X\);
+  ac:	c5 94       	R5=W\[P0--\]\(X\);
+  ae:	0d ab       	R5=W\[P1\+0x18\]\(X\);
+  b0:	73 e5 fe 7f 	R3=W\[SP\+0xfffc\]\(X\);
+  b4:	7f e5 02 80 	R7=W\[FP\+-65532\]\(X\);
+  b8:	51 8e       	R1=W\[P1\+\+P2\]\(X\);
+
+000000ba <load_high_data_register_half>:
+  ba:	40 9d       	R0.H=W\[I0\];
+  bc:	49 9c       	R1.H=W\[I1\+\+\];
+  be:	d2 9c       	R2.H=W\[I2--\];
+  c0:	f6 84       	R3.H=W\[SP\];
+  c2:	07 85       	R4.H=W\[FP\+\+P0\];
+
+000000c4 <load_low_data_register_half>:
+  c4:	3f 9d       	R7.L=W\[I3\];
+  c6:	36 9c       	R6.L=W\[I2\+\+\];
+  c8:	ad 9c       	R5.L=W\[I1--\];
+  ca:	00 83       	R4.L=W\[P0\];
+  cc:	da 82       	R3.L=W\[P2\+\+P3\];
+
+000000ce <load_byte_zero_extend>:
+  ce:	05 99       	R5=B\[P0\] \(Z\);
+  d0:	0c 98       	R4=B\[P1\+\+\] \(Z\);
+  d2:	90 98       	R0=B\[P2--\] \(Z\);
+  d4:	b3 e4 ff 7f 	R3=B\[SP\+0x7fff\] \(Z\);
+  d8:	b7 e4 01 80 	R7=B\[SP\+-32767\] \(Z\);
+
+000000dc <load_byte_sign_extend>:
+  dc:	45 99       	R5=B\[P0\]\(X\);
+  de:	4a 98       	R2=B\[P1\+\+\]\(X\);
+  e0:	fb 98       	R3=B\[FP--\]\(X\);
+  e2:	b7 e5 00 00 	R7=B\[SP\+0x0\]\(X\);
+  e6:	be e5 01 80 	R6=B\[FP\+-32767\]\(X\);
+
+000000ea <load_data1>:
+	...
+
+000000eb <load_data2>:
+  eb:	10 00       	IF ! CC JUMP eb <load_data2>;
+  ed:	00 00       	NOP;
+	...
diff --git a/gas/testsuite/gas/bfin/load.s b/gas/testsuite/gas/bfin/load.s
new file mode 100644
index 000000000000..07f4732a7e99
--- /dev/null
+++ b/gas/testsuite/gas/bfin/load.s
@@ -0,0 +1,131 @@
+	.extern f001
+	.extern F002
+	.text
+	.global load_immediate
+load_immediate:
+	/* Half-Word Load.  */
+	M3.l = 0xffff;
+	b2.l = 0xfffe;
+	Sp.l = 0;
+	FP.L = 0xfedc;
+	r0.h = 2;
+	p5.H = 32;
+	I2.h = 0xf204;
+	b1.H = 64;
+	l0.h = 0xffff;
+	R5.h = load_data1;
+	B2.H = F002;
+
+	/* Zero Extended.  */
+	fp = 0xff20 (Z);
+	l2 = 32 (z);
+	R5 = foo2 (Z);
+	A0 = 0;
+	A1 = 0;
+	a1 = a0 = 0;
+
+	/* Sign Extended.  */
+	r2 = -64 (x);
+	R0 = 0x7f (X);
+	P2 = 0 (x);
+	sp = -32 (x);
+	fp = 44 (X);
+	l3 = 0x800 (x);
+	m2 = 0x7fff (X);
+	R1 = 16 (X);
+	L0 = foo1;
+	r7 = load_data2;
+
+	.text
+	.global load_pointer_register
+load_pointer_register:
+	Sp = [ fp];
+	FP = [ p0++ ];
+	p1 = [sp--];
+	SP = [P2 +56];
+	p3 = [fp + 0];
+	P4 = [FP + 0x0001FFFC];
+	sp = [fp-0x0001fffc];
+	sp = [p4-0];
+	P5 = [FP-128];
+	
+
+	.text
+	.global load_data_register
+load_data_register:
+	R7 = [p0];
+	r6 = [p5++];
+	r5 = [P4 --];
+	R4 = [Fp + 40];
+	r3 = [sp+131068];
+	r2 = [sp-0];
+	r1 = [fp - 0x0001fffc];
+	R0 = [sp ++ p0];
+	R5 = [Fp-128];
+	r2 = [i0];
+	r1 = [I1++];
+	R3 = [I2--];
+	R4 = [i3 ++ M0];
+
+	.text
+	.global load_half_word_zero_extend
+load_half_word_zero_extend:
+	r7 = w [sp] (z);
+	R6 = W [FP ++] (Z);
+	R5 = W [P0 --] (z);
+	R4 = w [p1 + 30] (Z);
+	r3 = w [sp + 0xfffc] (z);
+	r2 = w [fp - 0xfffc] (Z);
+	R0 = W [ P0 ++ P5] (z);
+
+	.text
+	.global load_half_word_sign_extend
+load_half_word_sign_extend:
+	r7 = w [sp] (x);
+	R6 = W [FP ++] (X);
+	R5 = W [P0 --] (X);
+	r5 = w [p1 + 24] (x);
+	R3 = w [sp + 0xfffc] (X);
+	r7 = w [fp - 0xfffc] (x);
+	R1 = W [ P1 ++ P2] (X);
+	
+	.text
+	.global load_high_data_register_half
+load_high_data_register_half:
+	r0.h = w [i0];
+	R1.H = W [I1 ++];
+	R2.h = w [I2 --];
+	r3.H = W [sp];
+	R4.h = W [Fp ++ p0];
+
+	.text
+	.global load_low_data_register_half
+load_low_data_register_half:
+	r7.l = w [i3];
+	R6.L = W [I2++];
+	R5.l = w [i1 --];
+	r4.L = w [P0];
+	r3.l = W [p2 ++ p3];
+
+	.text
+	.global load_byte_zero_extend
+load_byte_zero_extend:
+	r5 = b [p0] (z);
+	R4 = B [P1++] (Z);
+	r0 = b [p2--] (z);
+	R3 = B [sp + 0x7fff] (Z);
+	r7 = b [SP - 32767] (z);
+
+	.text
+	.global load_byte_sign_extend
+load_byte_sign_extend:
+	r5 = b [ P0 ] (X);
+	r2 = B [ p1++ ] (x);
+	R3 = b [ FP--] (x);
+	r7 = B [ sp+0] (x);
+	r6 = b [fp-0x7fff] (X);
+
+	.global load_data
+load_data1:	.byte 0
+load_data2:	.word 16
+
diff --git a/gas/testsuite/gas/bfin/logical.d b/gas/testsuite/gas/bfin/logical.d
new file mode 100644
index 000000000000..d35f9fdce39c
--- /dev/null
+++ b/gas/testsuite/gas/bfin/logical.d
@@ -0,0 +1,39 @@
+#objdump: -dr
+#name: logical
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <and>:
+   0:	c8 55       	R7=R0&R1;
+   2:	9b 54       	R2=R3&R3;
+   4:	91 55       	R6=R1&R2;
+
+00000006 <not>:
+   6:	c8 43       	R0=~R1;
+   8:	d1 43       	R1=~R2;
+   a:	e3 43       	R3=~R4;
+   c:	ec 43       	R4=~R5;
+
+0000000e <or>:
+   e:	08 56       	R0=R0\|R1;
+  10:	a3 56       	R2=R3\|R4;
+  12:	7e 57       	R5=R6\|R7;
+
+00000014 <xor>:
+  14:	5d 59       	R5=R5\^R3;
+  16:	02 59       	R4=R2\^R0;
+  18:	01 58       	R0=R1\^R0;
+
+0000001a <bxor>:
+  1a:	0b c6 00 4e 	R7.L=CC=BXOR\(A0,R0\);
+  1e:	0b c6 08 4e 	R7.L=CC=BXOR\(A0,R1\);
+  22:	0c c6 00 4a 	R5.L=CC=BXOR\( A0,A1 ,CC \);
+  26:	0c c6 00 48 	R4.L=CC=BXOR\( A0,A1 ,CC \);
+
+0000002a <bxorshift>:
+  2a:	0b c6 38 06 	R3.L=CC=BXORSHIFT\(A0,R7\);
+  2e:	0b c6 10 04 	R2.L=CC=BXORSHIFT\(A0,R2\);
+  32:	0c c6 00 00 	A0=BXORSHIFT\(A0,A1 ,CC\);
+  36:	0c c6 00 00 	A0=BXORSHIFT\(A0,A1 ,CC\);
+	...
diff --git a/gas/testsuite/gas/bfin/logical.s b/gas/testsuite/gas/bfin/logical.s
new file mode 100644
index 000000000000..7a0a363fd990
--- /dev/null
+++ b/gas/testsuite/gas/bfin/logical.s
@@ -0,0 +1,51 @@
+	.text
+	.global and
+and:
+	r7 = r0 & r1;
+	R2 = R3 & R3;
+	r6 = r1 & R2;
+
+	.text
+	.global not
+not:
+	r0 = ~R1;
+	R1 = ~r2;
+	r3 = ~r4;
+	R4 = ~R5;
+
+	.text
+	.global or
+or:
+	r0 = r0 | r1;
+	r2 = R3 | R4;
+	R5 = r6 | R7;
+
+	.text
+	.global xor
+xor:
+	r5 = r5 ^ r3;
+	r4 = R2 ^ r0;
+	R0 = R1 ^ R0;
+
+
+	.text
+	.global bxor
+bxor:
+	R7.l = CC = bxor (a0, r0);
+	r7.l = cc = BXOR (A0, R1);
+
+	r5.L = Cc = BxoR (A0, A1, CC);
+	R4.L = cC = bXor (a0, a1, cc);
+
+	.text
+	.global bxorshift
+bxorshift:
+	r3.l = cc = bxorshift (a0, R7);
+	R2.l = cC = BxoRsHIft (A0, R2);
+
+	A0 = BXORSHIFT (A0, A1, CC);
+	a0 = BxorShift (a0, A1, Cc);
+
+
+
+	
diff --git a/gas/testsuite/gas/bfin/logical2.d b/gas/testsuite/gas/bfin/logical2.d
new file mode 100644
index 000000000000..0a7091143a92
--- /dev/null
+++ b/gas/testsuite/gas/bfin/logical2.d
@@ -0,0 +1,43 @@
+#objdump: -dr
+#name: logical2
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	ff 55       	R7=R7&R7;
+   2:	c7 55       	R7=R7&R0;
+   4:	cf 55       	R7=R7&R1;
+   6:	7f 54       	R1=R7&R7;
+   8:	87 54       	R2=R7&R0;
+   a:	cf 54       	R3=R7&R1;
+   c:	ff 43       	R7=~R7;
+   e:	c7 43       	R7=~R0;
+  10:	f8 43       	R0=~R7;
+  12:	d0 43       	R0=~R2;
+  14:	ff 57       	R7=R7\|R7;
+  16:	cf 57       	R7=R7\|R1;
+  18:	c7 57       	R7=R7\|R0;
+  1a:	7f 56       	R1=R7\|R7;
+  1c:	8f 56       	R2=R7\|R1;
+  1e:	c7 56       	R3=R7\|R0;
+  20:	ff 59       	R7=R7\^R7;
+  22:	cf 59       	R7=R7\^R1;
+  24:	c7 59       	R7=R7\^R0;
+  26:	7f 58       	R1=R7\^R7;
+  28:	8f 58       	R2=R7\^R1;
+  2a:	c7 58       	R3=R7\^R0;
+  2c:	0b c6 00 00 	R0.L=CC=BXORSHIFT\(A0,R0\);
+  30:	0b c6 08 00 	R0.L=CC=BXORSHIFT\(A0,R1\);
+  34:	0b c6 00 06 	R3.L=CC=BXORSHIFT\(A0,R0\);
+  38:	0b c6 08 06 	R3.L=CC=BXORSHIFT\(A0,R1\);
+  3c:	0b c6 00 40 	R0.L=CC=BXOR\(A0,R0\);
+  40:	0b c6 08 40 	R0.L=CC=BXOR\(A0,R1\);
+  44:	0b c6 00 46 	R3.L=CC=BXOR\(A0,R0\);
+  48:	0b c6 08 46 	R3.L=CC=BXOR\(A0,R1\);
+  4c:	0c c6 00 40 	R0.L=CC=BXOR\( A0,A1 ,CC \);
+  50:	0c c6 00 40 	R0.L=CC=BXOR\( A0,A1 ,CC \);
+  54:	0c c6 00 46 	R3.L=CC=BXOR\( A0,A1 ,CC \);
+  58:	0c c6 00 46 	R3.L=CC=BXOR\( A0,A1 ,CC \);
+  5c:	0c c6 00 00 	A0=BXORSHIFT\(A0,A1 ,CC\);
diff --git a/gas/testsuite/gas/bfin/logical2.s b/gas/testsuite/gas/bfin/logical2.s
new file mode 100755
index 000000000000..b26a765cfd59
--- /dev/null
+++ b/gas/testsuite/gas/bfin/logical2.s
@@ -0,0 +1,69 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//7 LOGICAL OPERATIONS

+//

+

+//Dreg = Dreg & Dreg ; /* (a) */

+

+R7 = R7 & R7;

+R7 = R7 & R0;

+r7 = R7 & R1;

+

+R1 = R7 & R7;

+R2 = R7 & R0;

+r3 = R7 & R1;

+

+//Dreg = ~ Dreg ; /* (a)*/

+

+R7 = ~R7;

+R7 = ~R0;

+R0 = ~R7;

+R0 = ~R2;

+

+//Dreg = Dreg | Dreg ; /* (a) */

+

+R7 = R7 | R7;

+R7 = R7 | R1;

+R7 = R7 | R0;

+

+R1 = R7 | R7;

+R2 = R7 | R1;

+R3 = R7 | R0;

+

+//Dreg = Dreg ^ Dreg ; /* (a) */

+

+R7 = R7 ^ R7;

+R7 = R7 ^ R1;

+R7 = R7 ^ R0;

+

+R1 = R7 ^ R7;

+R2 = R7 ^ R1;

+R3 = R7 ^ R0;

+

+//Dreg_lo = CC = BXORSHIFT ( A0, Dreg ) ; /* (b) */

+R0.L = CC = BXORSHIFT(A0, R0);

+R0.L = CC = BXORSHIFT(A0, R1);

+

+R3.L = CC = BXORSHIFT(A0, R0);

+R3.L = CC = BXORSHIFT(A0, R1);

+

+//Dreg_lo = CC = BXOR ( A0, Dreg ) ; /* (b) */

+R0.L = CC = BXOR(A0, R0);

+R0.L = CC = BXOR(A0, R1);

+

+R3.L = CC = BXOR(A0, R0);

+R3.L = CC = BXOR(A0, R1);

+

+//Dreg_lo = CC = BXOR ( A0, A1, CC ) ; /* (b) */

+R0.L = CC = BXOR(A0, A1, CC);

+R0.L = CC = BXOR(A0, A1, CC);

+

+R3.L = CC = BXOR(A0, A1, CC);

+R3.L = CC = BXOR(A0, A1, CC);

+

+A0 = BXORSHIFT ( A0, A1, CC ) ; /* (b) */

+

+

diff --git a/gas/testsuite/gas/bfin/move.d b/gas/testsuite/gas/bfin/move.d
new file mode 100644
index 000000000000..62bb5e11968d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/move.d
@@ -0,0 +1,82 @@
+#objdump: -dr
+#name: move
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <move_register>:
+   0:	38 31       	R7=A0.x;
+   2:	fb 32       	FP=B3;
+   4:	35 36       	L2=R5;
+   6:	b2 34       	M2=I2;
+   8:	d8 39       	A1.w=USP;
+   a:	06 31       	R0=ASTAT;
+   c:	c9 31       	R1=SEQSTAT;
+   e:	d2 31       	R2=SYSCFG;
+  10:	db 31       	R3=RETI;
+  12:	e4 31       	R4=RETX;
+  14:	ed 31       	R5=RETN;
+  16:	f6 31       	R6=RETE;
+  18:	3f 31       	R7=RETS;
+  1a:	a8 31       	R5=LC0;
+  1c:	a3 31       	R4=LC1;
+  1e:	99 31       	R3=LT0;
+  20:	94 31       	R2=LT1;
+  22:	8a 31       	R1=LB0;
+  24:	85 31       	R0=LB1;
+  26:	96 31       	R2=CYCLES;
+  28:	9f 31       	R3=CYCLES2;
+  2a:	cf 31       	R1=EMUDAT;
+  2c:	31 3d       	CYCLES=A0.w;
+  2e:	7f 38       	RETS=FP;
+  30:	e0 3d       	LT1=USP;
+  32:	72 38       	ASTAT=P2;
+  34:	08 c4 [0|3][0|f] c0 	A0=A1;
+  38:	08 c4 [0|3][0|f] e0 	A1=A0;
+  3c:	09 c4 00 20 	A0=R0;
+  40:	09 c4 08 a0 	A1=R1;
+  44:	8b c0 00 39 	R4 = A0 \(FU\);
+  48:	2f c1 00 19 	R5 = A1 \(ISS2\);
+  4c:	0b c0 80 39 	R6 = A0;
+  50:	0f c0 80 19 	R7 = A1;
+  54:	0f c0 80 39 	R7 = A1, R6 = A0;
+  58:	8f c0 00 38 	R1 = A1, R0 = A0 \(FU\);
+
+0000005c <move_conditional>:
+  5c:	6a 07       	IF CC R5 = P2;
+  5e:	b0 06       	IF ! CC SP = R0;
+
+00000060 <move_half_to_full_zero_extend>:
+  60:	fa 42       	R2=R7.L\(Z\);
+  62:	c8 42       	R0=R1.L\(Z\);
+
+00000064 <move_half_to_full_sign_extend>:
+  64:	8d 42       	R5=R1.L\(X\);
+  66:	93 42       	R3=R2.L\(X\);
+
+00000068 <move_register_half>:
+  68:	09 c4 28 40 	A0.x=R5.L;
+  6c:	09 c4 10 c0 	A1.x=R2.L;
+  70:	0a c4 [0|3][0|6] 00 	R0.L=A0.x;
+  74:	0a c4 [0|3][0|6] 4e 	R7.L=A1.x;
+  78:	09 c4 18 00 	A0.L=R3.L;
+  7c:	09 c4 20 80 	A1.L=R4.L;
+  80:	29 c4 30 00 	A0.H=R6.H;
+  84:	29 c4 28 80 	A1.H=R5.H;
+  88:	83 c1 00 38 	R0.L = A0 \(IU\);
+  8c:	27 c0 40 18 	R1.H = A1 \(S2RND\);
+  90:	07 c0 40 18 	R1.H = A1;
+  94:	67 c1 80 38 	R2.H = A1, R2.L = A0 \(IH\);
+  98:	07 c0 80 38 	R2.H = A1, R2.L = A0;
+  9c:	47 c0 00 38 	R0.H = A1, R0.L = A0 \(T\);
+  a0:	87 c0 00 38 	R0.H = A1, R0.L = A0 \(FU\);
+  a4:	07 c1 00 38 	R0.H = A1, R0.L = A0 \(IS\);
+  a8:	07 c0 00 38 	R0.H = A1, R0.L = A0;
+
+000000ac <move_byte_zero_extend>:
+  ac:	57 43       	R7=R2.B\(Z\);
+  ae:	48 43       	R0=R1.B\(Z\);
+
+000000b0 <move_byte_sign_extend>:
+  b0:	4e 43       	R6=R1.B\(Z\);
+  b2:	65 43       	R5=R4.B\(Z\);
diff --git a/gas/testsuite/gas/bfin/move.s b/gas/testsuite/gas/bfin/move.s
new file mode 100644
index 000000000000..253367159b34
--- /dev/null
+++ b/gas/testsuite/gas/bfin/move.s
@@ -0,0 +1,91 @@
+	.text
+	.global move_register
+move_register:
+	r7 = A0.X;
+	Fp = B3;
+	l2 = R5;
+	M2 = i2;
+	a1.w = usp;
+	r0 = astat;
+	r1 = sEQstat;
+	R2 = SYScfg;
+	R3 = reti;
+	R4 = RETX;
+	r5 = reTN;
+	r6 = rETe;
+	R7 = RETS;
+	R5 = lc0;
+	r4 = Lc1;
+	r3 = Lt0;
+	r2 = LT1;
+	r1 = Lb0;
+	r0 = LB1;
+	R2 = Cycles;
+	R3 = Cycles2;
+	r1 = emudat;
+	CYCLES = A0.W;
+	Rets = Fp;
+	Lt1 = USP;
+	ASTAT = P2; 
+	A0 = A1;
+	a1 = a0;
+	a0 = R0;
+	A1 = r1;
+
+	R4 = A0 (fu);
+	r5 = A1 (ISS2);
+	R6 = a0;
+	R7 = A1;
+	R6 = A0, R7 = a1;
+	r1 = a1, r0 = a0 (fu);
+
+	.text
+	.global move_conditional
+move_conditional:
+	if cc R5 = P2;
+	if !cc Sp = R0;
+	
+	.text
+	.global move_half_to_full_zero_extend
+move_half_to_full_zero_extend:
+	R2 = r7.L (Z);
+	r0 = R1.L (z);
+	
+	.text
+	.global move_half_to_full_sign_extend
+move_half_to_full_sign_extend:
+	R5 = R1.L (x);
+	r3 = r2.L (X);
+
+	.text
+	.global move_register_half
+move_register_half:
+	A0.X = r5.l;
+	a1.X = r2.L;
+	r0.l = a0.x;
+	R7.l = A1.X;
+	A0.L = r3.l;
+	a1.l = r4.l;
+	A0.h = r6.H;
+	A1.H = r5.h;
+	r0.l = A0 (iu);
+	R1.H = A1 (s2rnd);
+	r1.h = a1;
+	R2.l = A0, r2.H = A1 (IH);
+	R2.l = A0, r2.H = A1;
+	r0.H = A1, R0.L = a0 (t);
+	r0.H = A1, R0.L = a0 (fu);
+	r0.H = A1, R0.L = a0 (is);
+	r0.H = A1, R0.L = a0;
+
+	.text
+	.global move_byte_zero_extend
+move_byte_zero_extend:
+	R7 = r2.b (z);
+	r0 = R1.B (Z);
+
+	.text
+	.global move_byte_sign_extend
+move_byte_sign_extend:
+	r6 = r1.b (Z);
+	R5 = R4.B (z);
diff --git a/gas/testsuite/gas/bfin/move2.d b/gas/testsuite/gas/bfin/move2.d
new file mode 100644
index 000000000000..722f2e1b7eb9
--- /dev/null
+++ b/gas/testsuite/gas/bfin/move2.d
@@ -0,0 +1,371 @@
+#objdump: -dr
+#name: move2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 30       	R0=R0;
+   2:	09 30       	R1=R1;
+   4:	12 30       	R2=R2;
+   6:	1b 30       	R3=R3;
+   8:	24 30       	R4=R4;
+   a:	2d 30       	R5=R5;
+   c:	36 30       	R6=R6;
+   e:	3f 30       	R7=R7;
+  10:	40 32       	P0=P0;
+  12:	49 32       	P1=P1;
+  14:	52 32       	P2=P2;
+  16:	5b 32       	P3=P3;
+  18:	64 32       	P4=P4;
+  1a:	6d 32       	P5=P5;
+  1c:	76 32       	SP=SP;
+  1e:	7f 32       	FP=FP;
+  20:	00 39       	A0.x=A0.x;
+  22:	09 39       	A0.w=A0.w;
+  24:	12 39       	A1.x=A1.x;
+  26:	1b 39       	A1.w=A1.w;
+  28:	03 31       	R0=A1.w;
+  2a:	0a 31       	R1=A1.x;
+  2c:	11 31       	R2=A0.w;
+  2e:	18 31       	R3=A0.x;
+  30:	67 30       	R4=FP;
+  32:	6e 30       	R5=SP;
+  34:	75 30       	R6=P5;
+  36:	7c 30       	R7=P4;
+  38:	43 32       	P0=P3;
+  3a:	4a 32       	P1=P2;
+  3c:	51 32       	P2=P1;
+  3e:	58 32       	P3=P0;
+  40:	27 32       	P4=R7;
+  42:	2e 32       	P5=R6;
+  44:	35 32       	SP=R5;
+  46:	3c 32       	FP=R4;
+  48:	03 38       	A0.x=R3;
+  4a:	0a 38       	A0.w=R2;
+  4c:	11 38       	A1.x=R1;
+  4e:	18 38       	A1.w=R0;
+  50:	01 39       	A0.x=A0.w;
+  52:	03 39       	A0.x=A1.w;
+  54:	02 39       	A0.x=A1.x;
+  56:	13 39       	A1.x=A1.w;
+  58:	11 39       	A1.x=A0.w;
+  5a:	10 39       	A1.x=A0.x;
+  5c:	09 39       	A0.w=A0.w;
+  5e:	0b 39       	A0.w=A1.w;
+  60:	0a 39       	A0.w=A1.x;
+  62:	1b 39       	A1.w=A1.w;
+  64:	19 39       	A1.w=A0.w;
+  66:	18 39       	A1.w=A0.x;
+  68:	80 30       	R0=I0;
+  6a:	89 30       	R1=I1;
+  6c:	92 30       	R2=I2;
+  6e:	9b 30       	R3=I3;
+  70:	a4 30       	R4=M0;
+  72:	ad 30       	R5=M1;
+  74:	b6 30       	R6=M2;
+  76:	bf 30       	R7=M3;
+  78:	c0 30       	R0=B0;
+  7a:	c9 30       	R1=B1;
+  7c:	d2 30       	R2=B2;
+  7e:	db 30       	R3=B3;
+  80:	e4 30       	R4=L0;
+  82:	ed 30       	R5=L1;
+  84:	f6 30       	R6=L2;
+  86:	ff 30       	R7=L3;
+  88:	80 32       	P0=I0;
+  8a:	89 32       	P1=I1;
+  8c:	92 32       	P2=I2;
+  8e:	9b 32       	P3=I3;
+  90:	a4 32       	P4=M0;
+  92:	ad 32       	P5=M1;
+  94:	b6 32       	SP=M2;
+  96:	bf 32       	FP=M3;
+  98:	c0 32       	P0=B0;
+  9a:	c9 32       	P1=B1;
+  9c:	d2 32       	P2=B2;
+  9e:	db 32       	P3=B3;
+  a0:	e4 32       	P4=L0;
+  a2:	ed 32       	P5=L1;
+  a4:	f6 32       	SP=L2;
+  a6:	ff 32       	FP=L3;
+  a8:	80 38       	A0.x=I0;
+  aa:	89 38       	A0.w=I1;
+  ac:	92 38       	A1.x=I2;
+  ae:	9b 38       	A1.w=I3;
+  b0:	84 38       	A0.x=M0;
+  b2:	8d 38       	A0.w=M1;
+  b4:	96 38       	A1.x=M2;
+  b6:	9f 38       	A1.w=M3;
+  b8:	c0 38       	A0.x=B0;
+  ba:	c9 38       	A0.w=B1;
+  bc:	d2 38       	A1.x=B2;
+  be:	db 38       	A1.w=B3;
+  c0:	c4 38       	A0.x=L0;
+  c2:	cd 38       	A0.w=L1;
+  c4:	d6 38       	A1.x=L2;
+  c6:	df 38       	A1.w=L3;
+  c8:	00 34       	I0=R0;
+  ca:	48 34       	I1=P0;
+  cc:	56 34       	I2=SP;
+  ce:	5f 34       	I3=FP;
+  d0:	00 35       	I0=A0.x;
+  d2:	09 35       	I1=A0.w;
+  d4:	12 35       	I2=A1.x;
+  d6:	1b 35       	I3=A1.w;
+  d8:	20 34       	M0=R0;
+  da:	68 34       	M1=P0;
+  dc:	76 34       	M2=SP;
+  de:	7f 34       	M3=FP;
+  e0:	20 35       	M0=A0.x;
+  e2:	29 35       	M1=A0.w;
+  e4:	32 35       	M2=A1.x;
+  e6:	3b 35       	M3=A1.w;
+  e8:	00 36       	B0=R0;
+  ea:	48 36       	B1=P0;
+  ec:	56 36       	B2=SP;
+  ee:	5f 36       	B3=FP;
+  f0:	00 37       	B0=A0.x;
+  f2:	09 37       	B1=A0.w;
+  f4:	12 37       	B2=A1.x;
+  f6:	1b 37       	B3=A1.w;
+  f8:	20 36       	L0=R0;
+  fa:	68 36       	L1=P0;
+  fc:	76 36       	L2=SP;
+  fe:	7f 36       	L3=FP;
+ 100:	20 37       	L0=A0.x;
+ 102:	29 37       	L1=A0.w;
+ 104:	32 37       	L2=A1.x;
+ 106:	3b 37       	L3=A1.w;
+ 108:	81 34       	I0=I1;
+ 10a:	8c 34       	I1=M0;
+ 10c:	d1 34       	I2=B1;
+ 10e:	dc 34       	I3=L0;
+ 110:	a1 34       	M0=I1;
+ 112:	ac 34       	M1=M0;
+ 114:	f1 34       	M2=B1;
+ 116:	fc 34       	M3=L0;
+ 118:	81 36       	B0=I1;
+ 11a:	8c 36       	B1=M0;
+ 11c:	d1 36       	B2=B1;
+ 11e:	dc 36       	B3=L0;
+ 120:	a1 36       	L0=I1;
+ 122:	ac 36       	L1=M0;
+ 124:	f1 36       	L2=B1;
+ 126:	fc 36       	L3=L0;
+ 128:	c8 31       	R1=USP;
+ 12a:	d0 33       	P2=USP;
+ 12c:	f0 33       	SP=USP;
+ 12e:	f8 33       	FP=USP;
+ 130:	c0 39       	A0.x=USP;
+ 132:	d8 39       	A1.w=USP;
+ 134:	02 3e       	USP=R2;
+ 136:	44 3e       	USP=P4;
+ 138:	46 3e       	USP=SP;
+ 13a:	47 3e       	USP=FP;
+ 13c:	00 3f       	USP=A0.x;
+ 13e:	03 3f       	USP=A1.w;
+ 140:	06 31       	R0=ASTAT;
+ 142:	c9 31       	R1=SEQSTAT;
+ 144:	d2 31       	R2=SYSCFG;
+ 146:	db 31       	R3=RETI;
+ 148:	e4 31       	R4=RETX;
+ 14a:	ed 31       	R5=RETN;
+ 14c:	f6 31       	R6=RETE;
+ 14e:	3f 31       	R7=RETS;
+ 150:	80 31       	R0=LC0;
+ 152:	8b 31       	R1=LC1;
+ 154:	91 31       	R2=LT0;
+ 156:	9c 31       	R3=LT1;
+ 158:	a2 31       	R4=LB0;
+ 15a:	ad 31       	R5=LB1;
+ 15c:	b6 31       	R6=CYCLES;
+ 15e:	bf 31       	R7=CYCLES2;
+ 160:	30 38       	ASTAT=R0;
+ 162:	09 3e       	SEQSTAT=R1;
+ 164:	13 3e       	SYSCFG=R3;
+ 166:	1c 3e       	RETI=R4;
+ 168:	25 3e       	RETX=R5;
+ 16a:	2e 3e       	RETN=R6;
+ 16c:	37 3e       	RETE=R7;
+ 16e:	38 38       	RETS=R0;
+ 170:	01 3c       	LC0=R1;
+ 172:	1a 3c       	LC1=R2;
+ 174:	0b 3c       	LT0=R3;
+ 176:	24 3c       	LT1=R4;
+ 178:	15 3c       	LB0=R5;
+ 17a:	2e 3c       	LB1=R6;
+ 17c:	37 3c       	CYCLES=R7;
+ 17e:	38 3c       	CYCLES2=R0;
+ 180:	70 38       	ASTAT=P0;
+ 182:	49 3e       	SEQSTAT=P1;
+ 184:	53 3e       	SYSCFG=P3;
+ 186:	5c 3e       	RETI=P4;
+ 188:	65 3e       	RETX=P5;
+ 18a:	6e 3e       	RETN=SP;
+ 18c:	77 3e       	RETE=FP;
+ 18e:	78 38       	RETS=P0;
+ 190:	41 3c       	LC0=P1;
+ 192:	5a 3c       	LC1=P2;
+ 194:	4b 3c       	LT0=P3;
+ 196:	64 3c       	LT1=P4;
+ 198:	55 3c       	LB0=P5;
+ 19a:	6e 3c       	LB1=SP;
+ 19c:	76 3c       	CYCLES=SP;
+ 19e:	78 3c       	CYCLES2=P0;
+ 1a0:	08 c4 [0|3][0|f] c0 	A0=A1;
+ 1a4:	08 c4 [0|3][0|f] e0 	A1=A0;
+ 1a8:	09 c4 00 20 	A0=R0;
+ 1ac:	09 c4 08 20 	A0=R1;
+ 1b0:	09 c4 10 20 	A0=R2;
+ 1b4:	09 c4 00 a0 	A1=R0;
+ 1b8:	09 c4 08 a0 	A1=R1;
+ 1bc:	09 c4 10 a0 	A1=R2;
+ 1c0:	0b c0 00 38 	R0 = A0;
+ 1c4:	8b c0 80 38 	R2 = A0 \(FU\);
+ 1c8:	2b c1 00 39 	R4 = A0 \(ISS2\);
+ 1cc:	0f c0 00 18 	R1 = A1;
+ 1d0:	8f c0 80 18 	R3 = A1 \(FU\);
+ 1d4:	2f c1 00 19 	R5 = A1 \(ISS2\);
+ 1d8:	0f c0 00 38 	R1 = A1, R0 = A0;
+ 1dc:	8f c0 00 38 	R1 = A1, R0 = A0 \(FU\);
+ 1e0:	2f c1 80 39 	R7 = A1, R6 = A0 \(ISS2\);
+ 1e4:	0f c0 00 38 	R1 = A1, R0 = A0;
+ 1e8:	8f c0 80 38 	R3 = A1, R2 = A0 \(FU\);
+ 1ec:	2f c1 00 39 	R5 = A1, R4 = A0 \(ISS2\);
+ 1f0:	18 07       	IF CC R3 = R0;
+ 1f2:	10 07       	IF CC R2 = R0;
+ 1f4:	38 07       	IF CC R7 = R0;
+ 1f6:	52 07       	IF CC R2 = P2;
+ 1f8:	61 07       	IF CC R4 = P1;
+ 1fa:	40 07       	IF CC R0 = P0;
+ 1fc:	7c 07       	IF CC R7 = P4;
+ 1fe:	c2 07       	IF CC P0 = P2;
+ 200:	e5 07       	IF CC P4 = P5;
+ 202:	cb 07       	IF CC P1 = P3;
+ 204:	ec 07       	IF CC P5 = P4;
+ 206:	82 07       	IF CC P0 = R2;
+ 208:	a3 07       	IF CC P4 = R3;
+ 20a:	af 07       	IF CC P5 = R7;
+ 20c:	96 07       	IF CC P2 = R6;
+ 20e:	18 06       	IF ! CC R3 = R0;
+ 210:	10 06       	IF ! CC R2 = R0;
+ 212:	38 06       	IF ! CC R7 = R0;
+ 214:	52 06       	IF ! CC R2 = P2;
+ 216:	61 06       	IF ! CC R4 = P1;
+ 218:	40 06       	IF ! CC R0 = P0;
+ 21a:	7c 06       	IF ! CC R7 = P4;
+ 21c:	c2 06       	IF ! CC P0 = P2;
+ 21e:	e5 06       	IF ! CC P4 = P5;
+ 220:	cb 06       	IF ! CC P1 = P3;
+ 222:	ec 06       	IF ! CC P5 = P4;
+ 224:	82 06       	IF ! CC P0 = R2;
+ 226:	a3 06       	IF ! CC P4 = R3;
+ 228:	af 06       	IF ! CC P5 = R7;
+ 22a:	96 06       	IF ! CC P2 = R6;
+ 22c:	c0 42       	R0=R0.L\(Z\);
+ 22e:	ca 42       	R2=R1.L\(Z\);
+ 230:	d1 42       	R1=R2.L\(Z\);
+ 232:	f7 42       	R7=R6.L\(Z\);
+ 234:	80 42       	R0=R0.L\(X\);
+ 236:	8a 42       	R2=R1.L\(X\);
+ 238:	91 42       	R1=R2.L\(X\);
+ 23a:	b7 42       	R7=R6.L\(X\);
+ 23c:	c0 42       	R0=R0.L\(Z\);
+ 23e:	ca 42       	R2=R1.L\(Z\);
+ 240:	d1 42       	R1=R2.L\(Z\);
+ 242:	f7 42       	R7=R6.L\(Z\);
+ 244:	09 c4 00 40 	A0.x=R0.L;
+ 248:	09 c4 08 40 	A0.x=R1.L;
+ 24c:	09 c4 00 c0 	A1.x=R0.L;
+ 250:	09 c4 08 c0 	A1.x=R1.L;
+ 254:	0a c4 [0|3][0|6] 00 	R0.L=A0.x;
+ 258:	0a c4 [0|3][0|6] 02 	R1.L=A0.x;
+ 25c:	0a c4 [0|3][0|6] 0e 	R7.L=A0.x;
+ 260:	0a c4 [0|3][0|6] 40 	R0.L=A1.x;
+ 264:	0a c4 [0|3][0|6] 42 	R1.L=A1.x;
+ 268:	0a c4 [0|3][0|6] 4e 	R7.L=A1.x;
+ 26c:	09 c4 00 00 	A0.L=R0.L;
+ 270:	09 c4 08 00 	A0.L=R1.L;
+ 274:	09 c4 30 00 	A0.L=R6.L;
+ 278:	09 c4 00 80 	A1.L=R0.L;
+ 27c:	09 c4 08 80 	A1.L=R1.L;
+ 280:	09 c4 30 80 	A1.L=R6.L;
+ 284:	29 c4 00 00 	A0.H=R0.H;
+ 288:	29 c4 08 00 	A0.H=R1.H;
+ 28c:	29 c4 30 00 	A0.H=R6.H;
+ 290:	29 c4 00 80 	A1.H=R0.H;
+ 294:	29 c4 08 80 	A1.H=R1.H;
+ 298:	29 c4 30 80 	A1.H=R6.H;
+ 29c:	03 c0 00 38 	R0.L = A0;
+ 2a0:	03 c0 40 38 	R1.L = A0;
+ 2a4:	83 c0 00 38 	R0.L = A0 \(FU\);
+ 2a8:	83 c0 40 38 	R1.L = A0 \(FU\);
+ 2ac:	03 c1 00 38 	R0.L = A0 \(IS\);
+ 2b0:	03 c1 40 38 	R1.L = A0 \(IS\);
+ 2b4:	83 c1 00 38 	R0.L = A0 \(IU\);
+ 2b8:	83 c1 40 38 	R1.L = A0 \(IU\);
+ 2bc:	43 c0 00 38 	R0.L = A0 \(T\);
+ 2c0:	43 c0 40 38 	R1.L = A0 \(T\);
+ 2c4:	23 c0 00 38 	R0.L = A0 \(S2RND\);
+ 2c8:	23 c0 40 38 	R1.L = A0 \(S2RND\);
+ 2cc:	23 c1 00 38 	R0.L = A0 \(ISS2\);
+ 2d0:	23 c1 40 38 	R1.L = A0 \(ISS2\);
+ 2d4:	63 c1 00 38 	R0.L = A0 \(IH\);
+ 2d8:	63 c1 40 38 	R1.L = A0 \(IH\);
+ 2dc:	07 c0 00 18 	R0.H = A1;
+ 2e0:	07 c0 40 18 	R1.H = A1;
+ 2e4:	87 c0 00 18 	R0.H = A1 \(FU\);
+ 2e8:	87 c0 40 18 	R1.H = A1 \(FU\);
+ 2ec:	07 c1 00 18 	R0.H = A1 \(IS\);
+ 2f0:	07 c1 40 18 	R1.H = A1 \(IS\);
+ 2f4:	87 c1 00 18 	R0.H = A1 \(IU\);
+ 2f8:	87 c1 40 18 	R1.H = A1 \(IU\);
+ 2fc:	47 c0 00 18 	R0.H = A1 \(T\);
+ 300:	47 c0 40 18 	R1.H = A1 \(T\);
+ 304:	27 c0 00 18 	R0.H = A1 \(S2RND\);
+ 308:	27 c0 40 18 	R1.H = A1 \(S2RND\);
+ 30c:	27 c1 00 18 	R0.H = A1 \(ISS2\);
+ 310:	27 c1 40 18 	R1.H = A1 \(ISS2\);
+ 314:	67 c1 00 18 	R0.H = A1 \(IH\);
+ 318:	67 c1 40 18 	R1.H = A1 \(IH\);
+ 31c:	07 c0 00 38 	R0.H = A1, R0.L = A0;
+ 320:	07 c0 40 38 	R1.H = A1, R1.L = A0;
+ 324:	87 c0 00 38 	R0.H = A1, R0.L = A0 \(FU\);
+ 328:	87 c0 40 38 	R1.H = A1, R1.L = A0 \(FU\);
+ 32c:	07 c1 00 38 	R0.H = A1, R0.L = A0 \(IS\);
+ 330:	07 c1 40 38 	R1.H = A1, R1.L = A0 \(IS\);
+ 334:	87 c1 00 38 	R0.H = A1, R0.L = A0 \(IU\);
+ 338:	87 c1 40 38 	R1.H = A1, R1.L = A0 \(IU\);
+ 33c:	47 c0 00 38 	R0.H = A1, R0.L = A0 \(T\);
+ 340:	47 c0 40 38 	R1.H = A1, R1.L = A0 \(T\);
+ 344:	27 c0 00 38 	R0.H = A1, R0.L = A0 \(S2RND\);
+ 348:	27 c0 40 38 	R1.H = A1, R1.L = A0 \(S2RND\);
+ 34c:	27 c1 00 38 	R0.H = A1, R0.L = A0 \(ISS2\);
+ 350:	27 c1 40 38 	R1.H = A1, R1.L = A0 \(ISS2\);
+ 354:	67 c1 00 38 	R0.H = A1, R0.L = A0 \(IH\);
+ 358:	67 c1 40 38 	R1.H = A1, R1.L = A0 \(IH\);
+ 35c:	07 c0 00 38 	R0.H = A1, R0.L = A0;
+ 360:	07 c0 40 38 	R1.H = A1, R1.L = A0;
+ 364:	87 c0 00 38 	R0.H = A1, R0.L = A0 \(FU\);
+ 368:	87 c0 40 38 	R1.H = A1, R1.L = A0 \(FU\);
+ 36c:	07 c1 00 38 	R0.H = A1, R0.L = A0 \(IS\);
+ 370:	07 c1 40 38 	R1.H = A1, R1.L = A0 \(IS\);
+ 374:	87 c1 00 38 	R0.H = A1, R0.L = A0 \(IU\);
+ 378:	87 c1 40 38 	R1.H = A1, R1.L = A0 \(IU\);
+ 37c:	47 c0 00 38 	R0.H = A1, R0.L = A0 \(T\);
+ 380:	47 c0 40 38 	R1.H = A1, R1.L = A0 \(T\);
+ 384:	27 c0 00 38 	R0.H = A1, R0.L = A0 \(S2RND\);
+ 388:	27 c0 40 38 	R1.H = A1, R1.L = A0 \(S2RND\);
+ 38c:	27 c1 00 38 	R0.H = A1, R0.L = A0 \(ISS2\);
+ 390:	27 c1 40 38 	R1.H = A1, R1.L = A0 \(ISS2\);
+ 394:	67 c1 00 38 	R0.H = A1, R0.L = A0 \(IH\);
+ 398:	67 c1 40 38 	R1.H = A1, R1.L = A0 \(IH\);
+ 39c:	48 43       	R0=R1.B\(Z\);
+ 39e:	50 43       	R0=R2.B\(Z\);
+ 3a0:	4f 43       	R7=R1.B\(Z\);
+ 3a2:	57 43       	R7=R2.B\(Z\);
+ 3a4:	08 43       	R0=R1.B\(X\);
+ 3a6:	10 43       	R0=R2.B\(X\);
+ 3a8:	0f 43       	R7=R1.B\(X\);
+ 3aa:	17 43       	R7=R2.B\(X\);
diff --git a/gas/testsuite/gas/bfin/move2.s b/gas/testsuite/gas/bfin/move2.s
new file mode 100755
index 000000000000..1036900f3b68
--- /dev/null
+++ b/gas/testsuite/gas/bfin/move2.s
@@ -0,0 +1,530 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//4 MOVE

+//

+

+//genreg = genreg ; /* (a) */

+R0 = R0;

+R1 = R1;

+R2 = R2;

+R3 = R3;

+R4 = R4;

+R5 = R5;

+R6 = R6;

+R7 = R7;

+	   

+P0 = P0;

+P1 = P1;

+P2 = P2;

+P3 = P3;

+P4 = P4;

+P5 = P5;

+SP = SP;

+FP = FP;

+

+A0.X = A0.X;

+A0.W = A0.W;

+A1.X = A1.X;

+A1.W = A1.W;

+

+

+R0 = A1.W;

+R1 = A1.X;

+R2 = A0.W;

+R3 = A0.X;

+R4 = FP;

+R5 = SP;

+R6 = P5;

+R7 = P4;

+	   

+P0 = P3;

+P1 = P2;

+P2 = P1;

+P3 = P0;

+P4 = R7;

+P5 = R6;

+SP = R5;

+FP = R4;

+

+A0.X = R3;

+A0.W = R2;

+A1.X = R1;

+A1.W = R0;

+

+A0.X = A0.W;

+A0.X = A1.W;

+A0.X = A1.X;

+

+A1.X = A1.W;

+A1.X = A0.W;

+A1.X = A0.X;

+

+A0.W = A0.W;

+A0.W = A1.W;

+A0.W = A1.X;

+

+A1.W = A1.W;

+A1.W = A0.W;

+A1.W = A0.X;

+

+//genreg = dagreg ; /* (a) */

+R0 = I0;

+R1 = I1;

+R2 = I2;

+R3 = I3;

+R4 = M0;

+R5 = M1;

+R6 = M2;

+R7 = M3;

+	   

+R0 = B0;

+R1 = B1;

+R2 = B2;

+R3 = B3;

+R4 = L0;

+R5 = L1;

+R6 = L2;

+R7 = L3;

+

+P0 = I0;

+P1 = I1;

+P2 = I2;

+P3 = I3;

+P4 = M0;

+P5 = M1;

+SP = M2;

+FP = M3;

+	   

+P0 = B0;

+P1 = B1;

+P2 = B2;

+P3 = B3;

+P4 = L0;

+P5 = L1;

+SP = L2;

+FP = L3;

+

+

+A0.X = I0;

+A0.W = I1;

+A1.X = I2;

+A1.W = I3;

+

+A0.X = M0;

+A0.W = M1;

+A1.X = M2;

+A1.W = M3;

+

+A0.X = B0;

+A0.W = B1;

+A1.X = B2;

+A1.W = B3;

+

+A0.X = L0;

+A0.W = L1;

+A1.X = L2;

+A1.W = L3;

+

+//dagreg = genreg ; /* (a) */

+I0 = R0;

+I1 = P0;

+I2 = SP;

+I3 = FP;

+I0 = A0.X;

+I1 = A0.W;

+I2 = A1.X;

+I3 = A1.W;

+

+M0 = R0;

+M1 = P0;

+M2 = SP;

+M3 = FP;

+M0 = A0.X;

+M1 = A0.W;

+M2 = A1.X;

+M3 = A1.W;

+

+B0 = R0;

+B1 = P0;

+B2 = SP;

+B3 = FP;

+B0 = A0.X;

+B1 = A0.W;

+B2 = A1.X;

+B3 = A1.W;

+

+L0 = R0;

+L1 = P0;

+L2 = SP;

+L3 = FP;

+L0 = A0.X;

+L1 = A0.W;

+L2 = A1.X;

+L3 = A1.W;

+

+

+//dagreg = dagreg ; /* (a) */

+

+I0 = I1;

+I1 = M0;

+I2 = B1;

+I3 = L0;

+

+M0 = I1;

+M1 = M0;

+M2 = B1;

+M3 = L0;

+

+B0 = I1;

+B1 = M0;

+B2 = B1;

+B3 = L0;

+

+L0 = I1;

+L1 = M0;

+L2 = B1;

+L3 = L0;

+

+//genreg = USP ; /* (a)*/

+R1 = USP;

+P2 = USP;

+SP = USP;

+FP = USP;

+A0.X = USP;

+A1.W = USP;

+

+//USP = genreg ; /* (a)*/

+USP = R2;

+USP = P4;

+USP = SP;

+USP = FP;

+USP = A0.X;

+USP = A1.W;

+

+//Dreg = sysreg ; /* sysreg to 32-bit D-register (a) */

+R0 = ASTAT;

+R1 = SEQSTAT;

+R2 = SYSCFG;

+R3 = RETI;

+R4 = RETX;

+R5 = RETN;

+R6 = RETE;

+R7 = RETS;

+R0 = LC0;

+R1 = LC1;

+R2 = LT0;

+R3 = LT1;

+R4 = LB0;

+R5 = LB1;

+R6 = CYCLES;

+R7 = CYCLES2;

+//R0 = EMUDAT; 

+//sysreg = Dreg ; /* 32-bit D-register to sysreg (a) */

+ASTAT = R0;

+SEQSTAT = R1;

+SYSCFG = R3;

+RETI = R4;

+RETX =R5;

+RETN = R6;

+RETE = R7;

+RETS = R0;

+LC0 = R1;

+LC1 = R2;

+LT0 = R3;

+LT1 = R4;

+LB0 = R5;

+LB1 = R6;

+CYCLES = R7;

+CYCLES2 = R0;

+//EMUDAT = R1; 

+//sysreg = Preg ; /* 32-bit P-register to sysreg (a) */

+ASTAT = P0;

+SEQSTAT = P1;

+SYSCFG = P3;

+RETI = P4;

+RETX =P5;

+RETN = SP;

+RETE = FP;

+RETS = P0;

+LC0 = P1;

+LC1 = P2;

+LT0 = P3;

+LT1 = P4;

+LB0 = P5;

+LB1 = SP;

+CYCLES = SP;

+CYCLES2 = P0;

+//EMUDAT = P1; 

+

+

+//sysreg = USP ; /* (a) */

+//ASTAT = USP;

+//SEQSTAT = USP;

+//SYSCFG = USP;

+//RETI = USP;

+//RETX =USP;

+//RETN = USP;

+//RETE = USP;

+//RETS = USP;

+//LC0 = USP;

+//LC1 = USP;

+//LT0 = USP;

+//LT1 = USP;

+//LB0 = USP;

+//LB1 = USP;

+//CYCLES = USP;

+//CYCLES2 = USP;

+//EMUDAT = USP; 

+

+A0 = A1 ; /* move 40-bit Accumulator value (b) */

+

+A1 = A0 ; /* move 40-bit Accumulator value (b) */

+

+//A0 = Dreg ; /* 32-bit D-register to 40-bit A0, sign extended (b)*/

+A0 = R0;

+A0 = R1;

+A0 = R2;

+

+//A1 = Dreg ; /* 32-bit D-register to 40-bit A1, sign extended (b)*/

+

+A1 = R0;

+A1 = R1;

+A1 = R2;

+//Dreg_even = A0 (opt_mode) ; /* move 32-bit A0.W to even Dreg (b) */

+R0 = A0;

+R2 = A0(FU);

+R4 = A0(ISS2);

+

+//Dreg_odd = A1 (opt_mode) ; /* move 32-bit A1.W to odd Dreg (b) */

+R1 = A1;

+R3 = A1(FU);

+R5 = A1(ISS2);

+

+//Dreg_even = A0, Dreg_odd = A1 (opt_mode) ; /* move both Accumulators to a register pair (b) */

+R0 = A0, R1 = A1;

+R0 = A0, R1 = A1(FU);

+R6 = A0, R7 = A1(ISS2);

+

+

+//Dreg_odd = A1, Dreg_even = A0 (opt_mode) ; /* move both Accumulators to a register pair (b) */

+R1 = A1, R0 = A0;

+R3 = A1, R2 = A0(FU);

+R5 = A1, R4 = A0(ISS2);

+

+//IF CC DPreg = DPreg ; /* move if CC = 1 (a) */

+

+IF CC R3 = R0;

+IF CC R2 = R0;

+IF CC R7 = R0;

+

+IF CC R2 = P2;

+IF CC R4 = P1;

+IF CC R0 = P0;

+IF CC R7 = P4;

+

+IF CC P0 = P2;

+IF CC P4 = P5;

+IF CC P1 = P3;

+IF CC P5 = P4;

+

+IF CC P0 = R2;

+IF CC P4 = R3;

+IF CC P5 = R7;

+IF CC P2 = R6;

+

+//IF ! CC DPreg = DPreg ; /* move if CC = 0 (a) */

+IF !CC R3 = R0;

+IF !CC R2 = R0;

+IF !CC R7 = R0;

+

+IF !CC R2 = P2;

+IF !CC R4 = P1;

+IF !CC R0 = P0;

+IF !CC R7 = P4;

+

+IF !CC P0 = P2;

+IF !CC P4 = P5;

+IF !CC P1 = P3;

+IF !CC P5 = P4;

+

+IF !CC P0 = R2;

+IF !CC P4 = R3;

+IF !CC P5 = R7;

+IF !CC P2 = R6;

+

+//Dreg = Dreg_lo (Z) ; /* (a) */

+

+R0 = R0.L(Z);

+R2 = R1.L(Z);

+R1 = R2.L(Z);

+R7 = R6.L(Z);

+

+//Dreg = Dreg_lo (X) ; /* (a)*/

+R0 = R0.L(X);

+R2 = R1.L(X);

+R1 = R2.L(X);

+R7 = R6.L(X);

+

+R0 = R0.L;

+R2 = R1.L;

+R1 = R2.L;

+R7 = R6.L;

+

+//A0.X = Dreg_lo ; /* least significant 8 bits of Dreg into A0.X (b) */

+A0.X = R0.L;

+A0.X = R1.L;

+

+//A1.X = Dreg_lo ; /* least significant 8 bits of Dreg into A1.X (b) */

+A1.X = R0.L;

+A1.X = R1.L;

+

+//Dreg_lo = A0.X ; /* 8-bit A0.X, sign-extended, into least significant 16 bits of Dreg (b) */

+R0.L = A0.X;

+R1.L = A0.X;

+R7.L = A0.X;

+

+//Dreg_lo = A1.X ; /* 8-bit A1.X, sign-extended, into least significant 16 bits of Dreg (b) */

+R0.L = A1.X;

+R1.L = A1.X;

+R7.L = A1.X;

+

+//A0.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A0.W (b) */

+A0.L = R0.L;

+A0.L = R1.L;

+A0.L = R6.L;

+

+//A1.L = Dreg_lo ; /* least significant 16 bits of Dreg into least significant 16 bits of A1.W (b) */

+A1.L = R0.L;

+A1.L = R1.L;

+A1.L = R6.L;

+

+//A0.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A0.W (b) */

+A0.H = R0.H;

+A0.H = R1.H;

+A0.H = R6.H;

+//A1.H = Dreg_hi ; /* most significant 16 bits of Dreg into most significant 16 bits of A1.W (b) */

+A1.H = R0.H;

+A1.H = R1.H;

+A1.H = R6.H;

+

+//Dreg_lo = A0 (opt_mode) ; /* move A0 to lower half of Dreg (b) */

+R0.L = A0;

+R1.L = A0;

+

+R0.L = A0(FU);

+R1.L = A0(FU);

+

+R0.L = A0(IS);

+R1.L = A0(IS);

+

+R0.L = A0(IU);

+R1.L = A0(IU);

+

+R0.L = A0(T);

+R1.L = A0(T);

+

+R0.L = A0(S2RND);

+R1.L = A0(S2RND);

+

+R0.L = A0(ISS2);

+R1.L = A0(ISS2);

+

+R0.L = A0(IH);

+R1.L = A0(IH);

+

+//Dreg_hi = A1 (opt_mode) ; /* move A1 to upper half of Dreg (b) */

+R0.H = A1;

+R1.H = A1;

+

+R0.H = A1(FU);

+R1.H = A1(FU);

+

+R0.H = A1(IS);

+R1.H = A1(IS);

+

+R0.H = A1(IU);

+R1.H = A1(IU);

+

+R0.H = A1(T);

+R1.H = A1(T);

+

+R0.H = A1(S2RND);

+R1.H = A1(S2RND);

+

+R0.H = A1(ISS2);

+R1.H = A1(ISS2);

+

+R0.H = A1(IH);

+R1.H = A1(IH);

+

+

+//Dreg_lo = A0, Dreg_hi = A1 (opt_mode) ; /* move both values at once; must go to the lower and upper halves of the same Dreg (b)*/

+

+R0.L = A0, R0.H = A1; 

+R1.L = A0, R1.H = A1; 

+

+R0.L = A0, R0.H = A1(FU); 

+R1.L = A0, R1.H = A1(FU);

+ 

+R0.L = A0, R0.H = A1(IS); 

+R1.L = A0, R1.H = A1(IS);

+ 

+R0.L = A0, R0.H = A1(IU); 

+R1.L = A0, R1.H = A1(IU);

+ 

+R0.L = A0, R0.H = A1(T); 

+R1.L = A0, R1.H = A1(T);

+ 

+R0.L = A0, R0.H = A1(S2RND); 

+R1.L = A0, R1.H = A1(S2RND);

+ 

+R0.L = A0, R0.H = A1(ISS2); 

+R1.L = A0, R1.H = A1(ISS2);

+

+R0.L = A0, R0.H = A1(IH); 

+R1.L = A0, R1.H = A1(IH);

+ 

+//Dreg_hi = A1, Dreg_lo = AO (opt_mode) ; /* move both values at once; must go to the upper and lower halves of the same Dreg (b) */

+

+R0.H = A1,R0.L = A0;  

+R1.H = A1,R1.L = A0;  

+		            

+R0.H = A1,R0.L = A0 (FU); 

+R1.H = A1,R1.L = A0 (FU);

+		            

+R0.H = A1,R0.L = A0 (IS); 

+R1.H = A1,R1.L = A0 (IS);

+		            

+R0.H = A1,R0.L = A0 (IU); 

+R1.H = A1,R1.L = A0 (IU);

+		            

+R0.H = A1,R0.L = A0 (T); 

+R1.H = A1,R1.L = A0 (T);

+		            

+R0.H = A1,R0.L = A0 (S2RND); 

+R1.H = A1,R1.L = A0 (S2RND);

+		            

+R0.H = A1,R0.L = A0 (ISS2); 

+R1.H = A1,R1.L = A0 (ISS2);

+		            

+R0.H = A1,R0.L = A0 (IH); 

+R1.H = A1,R1.L = A0 (IH);

+		            

+//Dreg = Dreg_byte (Z) ; /* (a)*/

+

+R0 = R1.B(Z);

+R0 = R2.B(Z);

+

+R7 = R1.B(Z);

+R7 = R2.B(Z);

+

+//Dreg = Dreg_byte (X) ; /* (a) */

+R0 = R1.B(X);

+R0 = R2.B(X);

+

+R7 = R1.B(X);

+R7 = R2.B(X);

+

diff --git a/gas/testsuite/gas/bfin/parallel.d b/gas/testsuite/gas/bfin/parallel.d
new file mode 100644
index 000000000000..26aee7bfd8e6
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel.d
@@ -0,0 +1,226 @@
+#objdump: -d
+#name: parallel
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	0a ce 13 8a 	R5=DEPOSIT\(R3,R2\) \|\| I0\+=2 \|\| NOP;
+   4:	60 9f 00 00 
+   8:	0a ce 37 c0 	R0=DEPOSIT\(R7,R6\)\(X\) \|\| I1\+=4 \|\| NOP;
+   c:	69 9f 00 00 
+  10:	0a ce 0a 08 	R4=EXTRACT\(R2,R1.L\) \(Z\) \|\| I2-=M0 \|\| NOP;
+  14:	72 9e 00 00 
+  18:	0a ce 10 04 	R2=EXTRACT\(R0,R2.L\) \(Z\) \|\| I3\+=M1 \|\| NOP;
+  1c:	67 9e 00 00 
+  20:	0a ce 23 4e 	R7=EXTRACT\(R3,R4.L\)\(X\) \|\| I3\+=M1\(BREV\) \|\| NOP;
+  24:	e7 9e 00 00 
+  28:	0a ce 0e 4a 	R5=EXTRACT\(R6,R1.L\)\(X\) \|\| I0-=2 \|\| NOP;
+  2c:	64 9f 00 00 
+  30:	08 ce 08 00 	BITMUX \(R1,R0,A0 \)\(ASR\) \|\| I1-=4 \|\| NOP;
+  34:	6d 9f 00 00 
+  38:	08 ce 13 00 	BITMUX \(R2,R3,A0 \)\(ASR\) \|\| I0\+=2 \|\| NOP;
+  3c:	60 9f 00 00 
+  40:	08 ce 25 40 	BITMUX \(R4,R5,A0 \)\(ASL\) \|\| SP=\[P0\] \|\| NOP;
+  44:	46 91 00 00 
+  48:	08 ce 3e 40 	BITMUX \(R7,R6,A0 \)\(ASL\) \|\| FP=\[P1\+\+\] \|\| NOP;
+  4c:	4f 90 00 00 
+  50:	06 ce 00 ca 	R5.L=ONES R0 \|\| P0=\[FP--\] \|\| NOP;
+  54:	f8 90 00 00 
+  58:	06 ce 02 ce 	R7.L=ONES R2 \|\| P1=\[P5\+0x18\] \|\| NOP;
+  5c:	a9 ad 00 00 
+  60:	10 cc 00 00 	A0= ABS A0 \|\| P2=\[SP\+0x3c\] \|\| R0=\[I0\];
+  64:	f2 af 00 9d 
+  68:	10 cc 00 40 	A0= ABS A1 \|\| P3=\[FP-60\] \|\| R1=\[I1\+\+M0\];
+  6c:	1b b9 89 9d 
+  70:	30 cc 00 00 	A1= ABS A0 \|\| P4=\[FP-4\] \|\| R2=\[I1\+\+\];
+  74:	fc b9 0a 9c 
+  78:	30 cc 00 40 	A1= ABS A1 \|\| FP=\[SP\] \|\| R3=\[I2--\];
+  7c:	77 91 93 9c 
+  80:	10 cc 00 c0 	A1= ABS A0,A0= ABS A0 \|\| R4=\[P5\+0x38\] \|\| R0.H=W\[I0\];
+  84:	ac a3 40 9d 
+  88:	07 cc 10 80 	R0= ABS R2 \|\| B\[SP\]=R0 \|\| R1.H=W\[I1\+\+\];
+  8c:	30 9b 49 9c 
+  90:	02 cc 10 a8 	R4.L=R2.H\+R0.L \(S\) \|\| B\[FP\]=R0 \|\| R2.H=W\[I2--\];
+  94:	38 9b d2 9c 
+  98:	22 cc 09 aa 	R5.H=R1.H\+R1.L \(S\) \|\| B\[P0\]=R0 \|\| R3.L=W\[I3\];
+  9c:	00 9b 3b 9d 
+  a0:	02 cc 35 0c 	R6.L=R6.L\+R5.L \(NS\) \|\| B\[P1\]=R0 \|\| R4.L=W\[I3\+\+\];
+  a4:	08 9b 3c 9c 
+  a8:	05 cc 01 98 	R4.L=R0\+R1\(RND20\) \|\| B\[P2\]=R0 \|\| R5.L=W\[I2--\];
+  ac:	10 9b b5 9c 
+  b0:	25 cc 28 96 	R3.H=R5\+R0\(RND20\) \|\| R0=B\[P0\]\(X\) \|\| \[I0\]=R6;
+  b4:	40 99 06 9f 
+  b8:	05 cc 3d d2 	R1.L=R7-R5\(RND20\) \|\| R0=B\[P4\] \(Z\) \|\| \[I1\+\+\]=R7;
+  bc:	20 99 0f 9e 
+  c0:	05 cc 01 04 	R2.L=R0\+R1\(RND12\) \|\| R1=B\[SP\]\(X\) \|\| \[I2--\]=R7;
+  c4:	71 99 97 9e 
+  c8:	25 cc 3e 0e 	R7.H=R7\+R6\(RND12\) \|\| R1=B\[P0\]\(X\) \|\| \[I3\+\+M1\]=R6;
+  cc:	41 99 be 9f 
+  d0:	05 cc 1a 4a 	R5.L=R3-R2\(RND12\) \|\| R1=B\[P1\] \(Z\) \|\| W\[I3\]=R5.H;
+  d4:	09 99 5d 9f 
+  d8:	25 cc 0a 44 	R2.H=R1-R2\(RND12\) \|\| R1=B\[P2\] \(Z\) \|\| W\[I2\+\+\]=R4.H;
+  dc:	11 99 54 9e 
+  e0:	07 ce 25 0c 	R6.L=EXPADJ \(R5,R4.L\) \|\| R1=B\[P3\] \(Z\) \|\| W\[I1--\]=R3.H;
+  e4:	19 99 cb 9e 
+  e8:	07 ce 08 ca 	R5.L=EXPADJ \(R0.H,R1.L\) \|\| R1=B\[P4\] \(Z\) \|\| W\[I0\]=R2.L;
+  ec:	21 99 22 9f 
+  f0:	07 ce 2b 48 	R4.L=EXPADJ \(R3,R5.L\) \(V\) \|\| R1=B\[P5\] \(Z\) \|\| W\[I0\+\+\]=R1.L;
+  f4:	29 99 21 9e 
+  f8:	07 cc 2a 0c 	R6=MAX\(R5,R2\) \|\| R2=B\[P0\]\(X\) \|\| W\[I1--\]=R0.L;
+  fc:	42 99 a8 9e 
+ 100:	07 cc 0b 00 	R0=MAX\(R1,R3\) \|\| B\[P1\]=R2 \|\| NOP;
+ 104:	0a 9b 00 00 
+ 108:	07 cc 13 4a 	R5=MIN\(R2,R3\) \|\| B\[P2\]=R2 \|\| R0=\[I1\+\+\];
+ 10c:	12 9b 08 9c 
+ 110:	07 cc 38 48 	R4=MIN\(R7,R0\) \|\| B\[P3\]=R2 \|\| R1=\[I1\+\+\];
+ 114:	1a 9b 09 9c 
+ 118:	0b cc 00 c0 	A0-=A1 \|\| B\[P4\]=R2 \|\| R2=\[I1\+\+\];
+ 11c:	22 9b 0a 9c 
+ 120:	0b cc 00 e0 	A0-=A1\(W32\) \|\| B\[P5\]=R2 \|\| R3=\[I1\+\+\];
+ 124:	2a 9b 0b 9c 
+ 128:	0b cc 00 80 	A0\+=A1 \|\| B\[SP\]=R2 \|\| R4=\[I1\+\+\];
+ 12c:	32 9b 0c 9c 
+ 130:	0b cc 00 a0 	A0\+=A1\(W32\) \|\| B\[FP\]=R2 \|\| R5=\[I1\+\+\];
+ 134:	3a 9b 0d 9c 
+ 138:	0b cc 00 0e 	R7=\(A0\+=A1\) \|\| B\[SP\]=R3 \|\| R6=\[I1\+\+\];
+ 13c:	33 9b 0e 9c 
+ 140:	0b cc 00 4c 	R6.L=\(A0\+=A1\) \|\| B\[FP\]=R3 \|\| R7=\[I1\+\+\];
+ 144:	3b 9b 0f 9c 
+ 148:	2b cc 00 40 	R0.H=\(A0\+=A1\) \|\| B\[P0\]=R3 \|\| R7=\[I0\+\+\];
+ 14c:	03 9b 07 9c 
+ 150:	00 ca 0a 24 	R0 = R1.H \* R2.L \|\| B\[P1\]=R3 \|\| R1=\[I0\+\+\];
+ 154:	0b 9b 01 9c 
+ 158:	20 ca 68 26 	R1 = R5.H \* R0.H \(S2RND\) \|\| B\[P2\]=R3 \|\| R2=\[I0\+\+\];
+ 15c:	13 9b 02 9c 
+ 160:	80 ca db 23 	R7 = R3.L \* R3.H \(FU\) \|\| B\[P3\]=R3 \|\| R3=\[I0\+\+\];
+ 164:	1b 9b 03 9c 
+ 168:	28 cb 15 27 	R4 = R2.H \* R5.H \(ISS2\) \|\| B\[P4\]=R3 \|\| R0=\[I0\+\+\];
+ 16c:	23 9b 00 9c 
+ 170:	08 cb 0b 20 	R0 = R1.L \* R3.L \(IS\) \|\| B\[P5\]=R3 \|\| R5=\[I0\+\+\];
+ 174:	2b 9b 05 9c 
+ 178:	08 ca a8 25 	R6 = R5.H \* R0.L \|\| B\[FP\]=R4 \|\| R7=\[I0\+\+\];
+ 17c:	3c 9b 07 9c 
+ 180:	94 cb be 40 	R2.H = R7.L \* R6.H \(M, IU\) \|\| B\[SP\]=R4 \|\| R6=\[I0\+\+\];
+ 184:	34 9b 06 9c 
+ 188:	04 ca e8 80 	R3.H = R5.H \* R0.L \|\| R4=B\[P0\]\(X\) \|\| \[I0\+\+M0\]=R0;
+ 18c:	44 99 80 9f 
+ 190:	14 ca 09 40 	R0.H = R1.L \* R1.H \(M\) \|\| R4=B\[P1\]\(X\) \|\| \[I0\+\+M0\]=R1;
+ 194:	4c 99 81 9f 
+ 198:	1c cb 3e 80 	R1 = R7.H \* R6.L \(M, IS\) \|\| R4=B\[P2\]\(X\) \|\| \[I0\+\+M0\]=R2;
+ 19c:	54 99 82 9f 
+ 1a0:	0c ca 02 41 	R5 = R0.L \* R2.H \|\| R4=B\[P3\]\(X\) \|\| \[I0\+\+M0\]=R3;
+ 1a4:	5c 99 83 9f 
+ 1a8:	1c ca b0 c0 	R3 = R6.H \* R0.H \(M\) \|\| R4=B\[P4\] \(Z\) \|\| \[I0\+\+M0\]=R4;
+ 1ac:	24 99 84 9f 
+ 1b0:	63 c8 2f 02 	a0 = R5.L \* R7.H \(W32\) \|\| R4=B\[P5\] \(Z\) \|\| \[I0\+\+M0\]=R5;
+ 1b4:	2c 99 85 9f 
+ 1b8:	03 c8 00 04 	a0 = R0.H \* R0.L \|\| R5=B\[P0\]\(X\) \|\| \[I0\+\+M0\]=R6;
+ 1bc:	45 99 86 9f 
+ 1c0:	83 c8 13 0a 	a0 \+= R2.L \* R3.H \(FU\) \|\| R5=B\[P1\] \(Z\) \|\| \[I0\+\+M0\]=R7;
+ 1c4:	0d 99 87 9f 
+ 1c8:	03 c8 21 0c 	a0 \+= R4.H \* R1.L \|\| R5=B\[P2\] \(Z\) \|\| \[I1\+\+M1\]=R7;
+ 1cc:	15 99 af 9f 
+ 1d0:	03 c9 3e 12 	a0 -= R7.L \* R6.H \(IS\) \|\| R5=B\[P3\]\(X\) \|\| \[I1\+\+M1\]=R6;
+ 1d4:	5d 99 ae 9f 
+ 1d8:	03 c8 2a 16 	a0 -= R5.H \* R2.H \|\| R5=B\[P4\] \(Z\) \|\| \[I1\+\+M1\]=R5;
+ 1dc:	25 99 ad 9f 
+ 1e0:	10 c8 08 58 	a1 = R1.L \* R0.H \(M\) \|\| R5=B\[P5\]\(X\) \|\| \[I1\+\+M1\]=R4;
+ 1e4:	6d 99 ac 9f 
+ 1e8:	00 c8 10 98 	a1 = R2.H \* R0.L \|\| R5=B\[SP\] \(Z\) \|\| \[I1\+\+M1\]=R3;
+ 1ec:	35 99 ab 9f 
+ 1f0:	70 c8 3e 98 	a1 = R7.H \* R6.L \(M, W32\) \|\| R5=B\[FP\]\(X\) \|\| \[I1\+\+M1\]=R2;
+ 1f4:	7d 99 aa 9f 
+ 1f8:	81 c8 1a 18 	a1 \+= R3.L \* R2.L \(FU\) \|\| R0.L=W\[I0\] \|\| \[I1\+\+M1\]=R1;
+ 1fc:	20 9d a9 9f 
+ 200:	01 c8 31 98 	a1 \+= R6.H \* R1.L \|\| R1.L=W\[I0\] \|\| \[I1\+\+M1\]=R0;
+ 204:	21 9d a8 9f 
+ 208:	02 c9 03 58 	a1 -= R0.L \* R3.H \(IS\) \|\| R2.L=W\[I0\] \|\| \[I2\+\+M2\]=R0;
+ 20c:	22 9d d0 9f 
+ 210:	02 c8 17 58 	a1 -= R2.L \* R7.H \|\| R3.L=W\[I0\] \|\| \[I2\+\+M2\]=R1;
+ 214:	23 9d d1 9f 
+ 218:	03 c8 f5 25 	R7.L = \(a0 = R6.H \* R5.L\) \|\| R4.L=W\[I0\] \|\| \[I2\+\+M2\]=R2;
+ 21c:	24 9d d2 9f 
+ 220:	c3 c8 0a 24 	R0.L = \(a0 = R1.H \* R2.L\) \(TFU\) \|\| R5.L=W\[I0\] \|\| \[I2\+\+M2\]=R3;
+ 224:	25 9d d3 9f 
+ 228:	03 c8 ac 28 	R2.L = \(a0 \+= R5.L \* R4.L\) \|\| R6.L=W\[I0\] \|\| \[I2\+\+M2\]=R4;
+ 22c:	26 9d d4 9f 
+ 230:	43 c8 fe 2e 	R3.L = \(a0 \+= R7.H \* R6.H\) \(T\) \|\| R7.L=W\[I0\] \|\| \[I2\+\+M2\]=R5;
+ 234:	27 9d d5 9f 
+ 238:	03 c8 1a 36 	R0.L = \(a0 -= R3.H \* R2.H\) \|\| R7.L=W\[I1\+\+\] \|\| \[I2\+\+M2\]=R6;
+ 23c:	2f 9c d6 9f 
+ 240:	63 c9 6c 30 	R1.L = \(a0 -= R5.L \* R4.L\) \(IH\) \|\| R6.L=W\[I1\+\+\] \|\| \[I2\+\+M2\]=R7;
+ 244:	2e 9c d7 9f 
+ 248:	04 c8 48 58 	R1.H = \(a1 = R1.L \* R0.H\) \|\| R2.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R7;
+ 24c:	2a 9c ff 9f 
+ 250:	34 c9 83 98 	R2.H = \(a1 = R0.H \* R3.L\) \(M, ISS2\) \|\| R3.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R6;
+ 254:	2b 9c fe 9f 
+ 258:	05 c8 bf 59 	R6.H = \(a1 \+= R7.L \* R7.H\) \|\| R4.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R5;
+ 25c:	2c 9c fd 9f 
+ 260:	25 c8 d3 19 	R7.H = \(a1 \+= R2.L \* R3.L\) \(S2RND\) \|\| R5.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R4;
+ 264:	2d 9c fc 9f 
+ 268:	06 c8 a2 d9 	R6.H = \(a1 -= R4.H \* R2.H\) \|\| R6.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R3;
+ 26c:	2e 9c fb 9f 
+ 270:	d6 c8 5f 99 	R5.H = \(a1 -= R3.H \* R7.L\) \(M, TFU\) \|\| R7.L=W\[I1\+\+\] \|\| \[I3\+\+M3\]=R2;
+ 274:	2f 9c fa 9f 
+ 278:	0b c8 0a 20 	R0 = \(a0 = R1.L \* R2.L\) \|\| R1.L=W\[I2--\] \|\| \[I3\+\+M3\]=R1;
+ 27c:	b1 9c f9 9f 
+ 280:	0b c9 8a 20 	R2 = \(a0 = R1.L \* R2.L\) \(IS\) \|\| R1.L=W\[I2--\] \|\| \[I3\+\+M3\]=R0;
+ 284:	b1 9c f8 9f 
+ 288:	0b c8 3e 2d 	R4 = \(a0 \+= R7.H \* R6.L\) \|\| R2.L=W\[I2--\] \|\| R0.H=W\[I0\];
+ 28c:	b2 9c 40 9d 
+ 290:	2b c8 ab 2b 	R6 = \(a0 \+= R5.L \* R3.H\) \(S2RND\) \|\| R3.L=W\[I2--\] \|\| R1.H=W\[I1\];
+ 294:	b3 9c 49 9d 
+ 298:	0b c8 97 35 	R6 = \(a0 -= R2.H \* R7.L\) \|\| R4.L=W\[I2--\] \|\| R2.H=W\[I2\];
+ 29c:	b4 9c 52 9d 
+ 2a0:	8b c8 06 33 	R4 = \(a0 -= R0.L \* R6.H\) \(FU\) \|\| R5.L=W\[I2--\] \|\| R3.H=W\[I3\];
+ 2a4:	b5 9c 5b 9d 
+ 2a8:	0c c8 81 99 	R7 = \(a1 = R0.H \* R1.L\) \|\| R6.L=W\[I2--\] \|\| R4.H=W\[I3\];
+ 2ac:	b6 9c 5c 9d 
+ 2b0:	9c c8 13 d9 	R5 = \(a1 = R2.H \* R3.H\) \(M, FU\) \|\| R7.L=W\[I2--\] \|\| R4.H=W\[I2\];
+ 2b4:	b7 9c 54 9d 
+ 2b8:	0d c8 bd 18 	R3 = \(a1 \+= R7.L \* R5.L\) \|\| W\[P0\]=R0.L \|\| R6.H=W\[I1\];
+ 2bc:	00 8a 4e 9d 
+ 2c0:	2d c9 17 d8 	R1 = \(a1 \+= R2.H \* R7.H\) \(ISS2\) \|\| W\[P0\]=R1.L \|\| R7.H=W\[I0\];
+ 2c4:	40 8a 47 9d 
+ 2c8:	0e c8 80 58 	R3 = \(a1 -= R0.L \* R0.H\) \|\| W\[P0\]=R2.L \|\| R7.L=W\[I0\+\+\];
+ 2cc:	80 8a 27 9c 
+ 2d0:	1e c9 17 59 	R5 = \(a1 -= R2.L \* R7.H\) \(M, IS\) \|\| W\[P0\]=R3.L \|\| R6.L=W\[I1\+\+\];
+ 2d4:	c0 8a 2e 9c 
+ 2d8:	07 cc 10 ee 	R7=-R2\(S\) \|\| W\[P0\]=R4.L \|\| R5.L=W\[I2\+\+\];
+ 2dc:	00 8b 35 9c 
+ 2e0:	0e cc 00 00 	A0=-A0 \|\| W\[P0\]=R5.L \|\| R4.L=W\[I3\+\+\];
+ 2e4:	40 8b 3c 9c 
+ 2e8:	0e cc 00 40 	A0=-A1 \|\| W\[P0\]=R6.L \|\| R3.L=W\[I3--\];
+ 2ec:	80 8b bb 9c 
+ 2f0:	2e cc 00 00 	A1=-A0 \|\| W\[P0\]=R7.L \|\| R2.L=W\[I1\+\+\];
+ 2f4:	c0 8b 2a 9c 
+ 2f8:	2e cc 00 40 	A1=-A1 \|\| W\[P1\]=R0 \|\| R1.L=W\[I2--\];
+ 2fc:	08 97 b1 9c 
+ 300:	0e cc 00 c0 	A1=-A1,A0=-A0 \|\| W\[P1\]=R1 \|\| R0.L=W\[I1--\];
+ 304:	09 97 a8 9c 
+ 308:	0c cc 18 ca 	R5.L=R3\(RND\) \|\| W\[P1\]=R2 \|\| R0=\[I0\+\+M3\];
+ 30c:	0a 97 e0 9d 
+ 310:	2c cc 00 cc 	R6.H=R0\(RND\) \|\| W\[P1\]=R3 \|\| R1=\[I1\+\+M2\];
+ 314:	0b 97 c9 9d 
+ 318:	08 cc 00 20 	A0=A0\(S\) \|\| W\[P1\]=R4 \|\| R2=\[I2\+\+M1\];
+ 31c:	0c 97 b2 9d 
+ 320:	08 cc 00 60 	A1=A1\(S\) \|\| W\[P1\]=R5 \|\| R3=\[I3\+\+M0\];
+ 324:	0d 97 9b 9d 
+ 328:	08 cc 00 a0 	A1=A1\(S\),A0=A0\(S\) \|\| R6=W\[P1\] \(Z\) \|\| \[I0\]=R0;
+ 32c:	0e 95 00 9f 
+ 330:	05 ce 00 0a 	R5.L=SIGNBITS R0 \|\| R7=W\[P1\] \(Z\) \|\| \[I1\]=R0;
+ 334:	0f 95 08 9f 
+ 338:	05 ce 07 80 	R0.L=SIGNBITS R7.H \|\| R1=W\[P2\+\+\]\(X\) \|\| \[I2\]=R0;
+ 33c:	51 94 10 9f 
+ 340:	06 ce 00 06 	R3.L=SIGNBITS A0 \|\| R2=W\[P2\+\+\]\(X\) \|\| \[I3\]=R0;
+ 344:	52 94 18 9f 
+ 348:	06 ce 00 4e 	R7.L=SIGNBITS A1 \|\| R3=W\[P2\+\+\] \(Z\) \|\| \[I0\]=R1;
+ 34c:	13 94 01 9f 
+ 350:	03 cc 37 ea 	R5.L=R6.H-R7.H \(S\) \|\| R4=W\[P2\+\+\]\(X\) \|\| \[I1\]=R1;
+ 354:	54 94 09 9f 
+ 358:	23 cc 1b 40 	R0.H=R3.L-R3.H \(NS\) \|\| R5=W\[P2\+\+\]\(X\) \|\| \[I2\]=R2;
+ 35c:	55 94 12 9f 
+ 360:   07 cc 10 84     R2= ABS R2 || R1=\[I0\+\+\] || NOP;
+ 364:	01 9c 00 00 
+
diff --git a/gas/testsuite/gas/bfin/parallel.s b/gas/testsuite/gas/bfin/parallel.s
new file mode 100644
index 000000000000..d5b10dd2356d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel.s
@@ -0,0 +1,141 @@
+	.section .text;

+	R5 = Deposit (r3, r2) || I0 += 2;

+	r0 = DEPOSIT (r7, R6) (X) || I1 += 4;

+	r4 = extract (r2, r1.L) (z) || I2 -= M0;

+	R2 = EXTRACT (r0, r2.l) (Z) || i3 += m1;

+

+	r7 = ExtracT (r3, r4.L) (X) || I3 += M1 (breV);

+	r5 = ExtRACt (R6, R1.L) (x) || i0 -= 2;

+

+	BITMUX(R1, R0, A0) (ASR) || I1 -= 4;

+	Bitmux (r2, R3, a0) (aSr) || I0 += 2;

+

+	bitmux (r4, r5, a0) (asl) || Sp = [P0];

+	BiTMux (R7, r6, a0) (ASl) || FP = [P1++];

+

+	R5.l = ones r0 || P0 = [fp--];

+	r7.L = Ones R2 || p1 = [P5 + 24];

+

+	a0 = abs a0 || p2 = [Sp+60] || r0 = [i0];

+	A0 = ABS A1 || P3 = [FP-60] || R1 = [I1++M0];

+	A1 = Abs a0 || P4 = [fp-4] || r2 = [i1++];

+	a1 = aBs A1 || fp = [sp] || r3 = [I2--];

+	A1 = abs a1, a0 = ABS A0 || R4=[p5+56] || r0.h = w [I0];

+	r0 = abs r2 || B[sp] = r0 || R1.H = W[I1++];

+

+	r4.L = R2.h + r0.L (s) || b [fp] = r0 || r2.H = w [i2--];

+	r5.H = R1.H + R1.L (S) || b [p0] = r0 || R3.l = W[I3];

+	r6.L = R6.L + r5.l (NS) || b [p1] = r0 || r4.L =w [i3++];

+

+	r4.l = r0 + r1 (RND20) || b [p2] = r0 || R5.l = W [i2--];

+	R3.H = r5 + r0 (rnd20) || r0 = b [p0] (x) || [i0] = R6;

+	r1.L = r7 - R5 (rND20) || r0 = b [p4] (z) || [I1++] = R7;

+

+	r2.L = R0 + R1 (rnd12) || r1 = b [sp] (x) || [I2--]= r7;

+	r7.H = r7 + r6 (RND12) || r1 = b [p0] (x)|| [I3++m1]=r6;

+	r5.l = r3 - R2 (rNd12) || r1 = b [p1] (z) || W [ i3 ] = r5.h;

+	r2.h = R1 - R2 (Rnd12) || r1 = b [p2] (z) || w [I2++] = R4.H;

+

+

+	r6.L = EXPADJ (r5, r4.l) || r1 = b [p3] (z) || W[I1--]=r3.h;

+	R5.l = ExpAdj (r0.h, r1.l) || r1 = b [p4] (z) || w[i0]=r2.l;

+	R4.L = expadj (R3, R5.L) (V) || r1 = b [p5] (z) || W [I0++] = R1.L;

+

+	R6 = MAX (r5, R2) || r2 = b [p0] (x) || W[i1--]=R0.l;

+	r0 = max (r1, r3) || b [p1] = r2 || NoP;

+

+	r5 = mIn (r2, R3) || b [p2] = r2 || r0 = [i1++];

+	R4 = Min (r7, R0) || b [p3] = r2 || r1 = [i1++];

+

+

+	A0 -= A1 || b [p4] = r2 || r2 = [i1++];

+	a0 -= a1 (w32) || b [p5] = r2 || r3 = [i1++];

+

+	a0 += a1 || b [sp] = r2 || r4 = [i1++];

+	A0 += A1 (w32) || b [fp] = r2 || r5 = [i1++];

+	r7 = ( a0 += a1) || b [sp] = r3 || r6 = [i1++];

+	r6.l = (A0 += a1) || b [fp] = r3 || r7 = [i1++];

+	R0.H = (a0 += A1) || b [p0] = r3 || r7 = [i0++];

+

+

+	R0.l = r1.h * r2.l || b [p1] = r3 || r1 = [i0++];

+	r1.L = r5.H * r0.H (s2rnd) || b [p2] = r3 || r2 = [i0++];

+	r7.l = r3.l * r3.H (FU) || b [p3] = r3 || r3 = [i0++];

+	r4 = r2.H * r5.H (iSS2) || b [p4] = r3 || r0 = [i0++];

+	r0 = r1.l * r3.l (is) || b [p5] = r3 || r5 = [i0++];

+	r6 = R5.H * r0.l || b [fp] = r4 || r7 = [i0++];

+

+	r2.h = r7.l * r6.H (M, iu) || b [sp] = r4 || r6 = [i0++];

+	r3.H = r5.H * r0.L || r4 = b [p0] (x) ||  [I0++M0] = R0;

+	R0.H = r1.L * r1.H (M) || r4 = b [p1] (x) || [i0++M0] = R1;

+	r1 = r7.H * r6.L (M, is) || r4 = b [p2] (x) || [i0++M0] = R2;

+	R5 = r0.l * r2.h || r4 = b [p3] (x) || [i0++m0] = R3;

+	r3 = r6.H * r0.H (m) || r4 = b [p4] (z) || [i0++m0] = R4;

+

+	a0 = r5.l * R7.H (w32) || r4 = b [p5] (z) || [i0++m0] = R5;

+	a0 = r0.h * r0.l || r5 = b [p0] (x) || [i0++M0] =R6;

+	A0 += R2.L * r3.H (FU) || r5 = b [p1] (z) || [i0++M0]=R7;

+	A0 += r4.h * r1.L || r5 = b [p2] (z) || [I1++M1] = R7;

+	a0 -= r7.l * r6.H (Is) || r5 = b [p3] (x) || [i1++m1] = r6;

+	A0 -= R5.H * r2.H || r5 = b [p4] (z) || [i1++m1]=r5;

+

+	a1 = r1.L * r0.H (M) || r5 = b [p5] (x) || [i1++m1]=r4;

+	A1 = r2.h * r0.L || r5 = b [sp] (z)  || [i1++m1] = r3;

+	A1 = R7.H * R6.L (M, W32) || r5 = b [fp] (x)  || [i1++m1] =r2;

+

+	a1 += r3.l * r2.l (fu) || r0.l = w [i0]  || [i1++m1] = r1;

+	a1 += R6.H * r1.L || r1.l = w [i0]  || [i1++m1] = R0;

+	A1 -= r0.L * R3.H (is) || r2.l = w [i0]  || [i2++m2] = R0;

+	a1 -= r2.l * r7.h || r3.l = w [i0]  || [I2++M2] =R1;

+

+	r7.l = (a0 = r6.H * r5.L) || r4.l = w [i0]  || [i2++m2] = r2;

+	r0.L = (A0 = r1.h * R2.l) (tfu) || r5.l = w [i0]  || [I2++m2] = R3;

+	R2.L = (a0 += r5.L * r4.L) || r6.l = w [i0]  || [I2++m2] = R4;

+	r3.l = (A0 += r7.H * r6.h) (T) || r7.l = w [i0]  ||  [ i2 ++ m2] = R5;

+	r0.l = (a0 -= r3.h * r2.h) || r7.l = w [i1++]  || [i2++m2] = r6;

+	r1.l = (a0 -= r5.L * r4.L) (iH) || r6.l = w [i1++]  || [i2++m2] = R7;

+

+	r1.H = (a1 = r1.l * R0.H) || r2.l = w [i1++]  || [i3++m3] = R7;

+	r2.h = (A1 = r0.H * r3.L) (M, Iss2) || r3.l = w [i1++]  || [i3++m3] = r6;

+	R6.H = (a1 += r7.l * r7.H) || r4.l = w [i1++]  || [i3++m3] = R5;

+	r7.h = (a1 += R2.L * R3.L) (S2rnd) || r5.l = w [i1++]  ||  [i3++m3] = r4;

+	r6.H = (A1 -= R4.h * r2.h) || r6.l = w [i1++]  || [i3++m3] = r3;

+	r5.h = (a1 -= r3.H * r7.L) (M, tFu) || r7.l = w [i1++]  || [i3++m3] = r2;

+

+	R0 = (A0 = R1.L * R2.L) || R1.L = W [I2--]  || [i3++m3] = r1;

+	R2 = (A0 = r1.l * r2.l) (is) || R1.L = W [I2--]  || [i3++m3] = r0;

+	r4 = (a0 += r7.h * r6.L) || R2.L = W [I2--]  || r0.h = w[i0];

+	r6 = (A0 += R5.L * r3.h) (s2RND) || R3.L = W [I2--]  || R1.H = w[i1];

+	R6 = (a0 -= r2.h * r7.l) || R4.L = W [I2--]  || r2.h = w[i2];

+	r4 = (A0 -= R0.L * r6.H) (FU) || R5.L = W [I2--]  || r3.h = w[i3];

+

+	r7 = (a1 = r0.h * r1.l) || R6.L = W [I2--]  || r4.h = w[i3];

+	R5 = (A1 = r2.H * r3.H) (M, fu) || R7.L = W [I2--]  || r4.h = W[i2];

+	R3 = (A1 += r7.l * r5.l) || w [p0] = r0.L || r6.h = W[i1];

+	r1 = (a1 += r2.h * r7.h) (iss2) || w [p0] = r1.L || r7.h = w[i0];

+	r3 = (A1 -= r0.l * R0.H) || w [p0] = r2.L || r7.L = w[I0++];

+	R5 = (a1 -= R2.l * R7.h) (m, is) || w [p0] = r3.L || R6.L = W [i1++];

+

+	r7 = -R2(s) || w [p0] = r4.L || r5.l = w[i2++];

+	A0 = -A0 || w [p0] = r5.L || r4.l = w[i3++];

+	a0 = -a1 || w [p0] = r6.L || r3.L = w [i3--];

+	A1 = -A0 || w [p0] = r7.L || r2.l = W [i1++];

+	a1 = -A1 || w [p1] = r0 || r1.L = w [i2--];

+	a1 = -a1, a0 = -a0 || w [p1] = r1 || r0.l = w [i1--];

+

+	R5.L = r3 (rnd) || w [p1] = r2 || r0 = [i0++m3];

+	r6.H = r0 (RND) || w [p1] = r3 || r1 = [i1++m2];

+

+	A0 = A0 (S) || w [p1] = r4  || r2 = [i2++m1];

+	a1 = a1 (s) || w [p1] = r5  || r3 = [i3++m0];

+	A1 = a1 (S), a0 = A0 (s) || r6 = w [p1] (z) || [i0] = r0;

+

+	R5.l = signbits r0 || r7 = w [p1] (z) || [i1] = R0;

+	r0.L = SIGNbits r7.H || r1 = w [p2++](x) || [I2] = r0;

+	r3.l = signBits A0 || r2 = w [p2++] (x) || [I3] = R0;

+	r7.L = SIGNBITS a1 || r3 = w [p2++] (z) || [i0] = R1;

+

+	r5.l = R6.H - R7.h (s) || r4 = w [p2++] (x) || [i1] = r1;

+	r0.H = r3.l - r3.h (NS) || r5 = w [p2++] (x) || [i2] = r2;

+

+	R1 = [I0++] || R2 = ABS R2 || NOP;

diff --git a/gas/testsuite/gas/bfin/parallel2.d b/gas/testsuite/gas/bfin/parallel2.d
new file mode 100644
index 000000000000..cd508019ac49
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel2.d
@@ -0,0 +1,147 @@
+#objdump: -d
+#name: parallel2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	08 cc 00 c0 	A0=A1 \|\| P0=\[SP\+0x14\] \|\| NOP;
+   4:	70 ad 00 00 
+   8:	08 cc 00 e0 	A1=A0 \|\| P0=\[P5\+0x18\] \|\| NOP;
+   c:	a8 ad 00 00 
+  10:	09 cc 00 20 	A0=R0 \|\| P0=\[P4\+0x1c\] \|\| NOP;
+  14:	e0 ad 00 00 
+  18:	09 cc 08 a0 	A1=R1 \|\| P0=\[P3\+0x20\] \|\| NOP;
+  1c:	18 ae 00 00 
+  20:	8b c8 00 39 	R4 = A0 \(FU\) \|\| P0=\[P3\+0x24\] \|\| NOP;
+  24:	58 ae 00 00 
+  28:	2f c9 00 19 	R5 = A1 \(ISS2\) \|\| P0=\[P3\+0x28\] \|\| NOP;
+  2c:	98 ae 00 00 
+  30:	0b c8 80 39 	R6 = A0 \|\| P0=\[P4\+0x2c\] \|\| NOP;
+  34:	e0 ae 00 00 
+  38:	0f c8 80 19 	R7 = A1 \|\| P0=\[P4\+0x30\] \|\| NOP;
+  3c:	20 af 00 00 
+  40:	0f c8 80 39 	R7 = A1, R6 = A0 \|\| P0=\[P4\+0x34\] \|\| NOP;
+  44:	60 af 00 00 
+  48:	8f c8 00 38 	R1 = A1, R0 = A0 \(FU\) \|\| P0=\[P4\+0x38\] \|\| NOP;
+  4c:	a0 af 00 00 
+  50:	09 cc 28 40 	A0.x=R5.L \|\| P0=\[P4\+0x3c\] \|\| NOP;
+  54:	e0 af 00 00 
+  58:	09 cc 10 c0 	A1.x=R2.L \|\| R0=\[I0\+\+M0\] \|\| NOP;
+  5c:	80 9d 00 00 
+  60:	0a cc 00 00 	R0.L=A0.x \|\| R1=\[I0\+\+M1\] \|\| NOP;
+  64:	a1 9d 00 00 
+  68:	0a cc 00 4e 	R7.L=A1.x \|\| R0=\[I0\+\+M2\] \|\| NOP;
+  6c:	c0 9d 00 00 
+  70:	09 cc 18 00 	A0.L=R3.L \|\| R0=\[I0\+\+M3\] \|\| NOP;
+  74:	e0 9d 00 00 
+  78:	09 cc 20 80 	A1.L=R4.L \|\| R0=\[I1\+\+M3\] \|\| NOP;
+  7c:	e8 9d 00 00 
+  80:	29 cc 30 00 	A0.H=R6.H \|\| R0=\[I1\+\+M2\] \|\| NOP;
+  84:	c8 9d 00 00 
+  88:	29 cc 28 80 	A1.H=R5.H \|\| R0=\[I1\+\+M1\] \|\| NOP;
+  8c:	a8 9d 00 00 
+  90:	83 c9 00 38 	R0.L = A0 \(IU\) \|\| R4=\[I1\+\+M0\] \|\| NOP;
+  94:	8c 9d 00 00 
+  98:	27 c8 40 18 	R1.H = A1 \(S2RND\) \|\| R0=\[I2\+\+M0\] \|\| NOP;
+  9c:	90 9d 00 00 
+  a0:	07 c8 40 18 	R1.H = A1 \|\| R0=\[I2\+\+M1\] \|\| NOP;
+  a4:	b0 9d 00 00 
+  a8:	67 c9 80 38 	R2.H = A1, R2.L = A0 \(IH\) \|\| R0=\[I2\+\+M2\] \|\| NOP;
+  ac:	d0 9d 00 00 
+  b0:	07 c8 80 38 	R2.H = A1, R2.L = A0 \|\| R0=\[I2\+\+M3\] \|\| NOP;
+  b4:	f0 9d 00 00 
+  b8:	47 c8 00 38 	R0.H = A1, R0.L = A0 \(T\) \|\| R5=\[I3\+\+M0\] \|\| NOP;
+  bc:	9d 9d 00 00 
+  c0:	87 c8 00 38 	R0.H = A1, R0.L = A0 \(FU\) \|\| R5=\[I3\+\+M1\] \|\| NOP;
+  c4:	bd 9d 00 00 
+  c8:	07 c9 00 38 	R0.H = A1, R0.L = A0 \(IS\) \|\| R5=\[I3\+\+M2\] \|\| NOP;
+  cc:	dd 9d 00 00 
+  d0:	07 c8 00 38 	R0.H = A1, R0.L = A0 \|\| R5=\[I3\+\+M3\] \|\| NOP;
+  d4:	fd 9d 00 00 
+  d8:	83 ce 08 41 	A0=A0>>0x1f \|\| R0=\[FP-32\] \|\| NOP;
+  dc:	80 b9 00 00 
+  e0:	83 ce f8 00 	A0=A0<<0x1f \|\| R0=\[FP-28\] \|\| NOP;
+  e4:	90 b9 00 00 
+  e8:	83 ce 00 50 	A1=A1>>0x0 \|\| R0=\[FP-24\] \|\| NOP;
+  ec:	a0 b9 00 00 
+  f0:	83 ce 00 10 	A1=A1<<0x0 \|\| R0=\[FP-20\] \|\| NOP;
+  f4:	b0 b9 00 00 
+  f8:	82 ce fd 4e 	R7=R5<<0x1f\(S\) \|\| R0=\[FP-16\] \|\| NOP;
+  fc:	c0 b9 00 00 
+ 100:	82 ce 52 07 	R3=R2>>>0x16 \|\| R0=\[FP-12\] \|\| NOP;
+ 104:	d0 b9 00 00 
+ 108:	80 ce 7a 52 	R1.L = R2.H << 0xf \(S\) \|\| R0=\[FP-8\] \|\| NOP;
+ 10c:	e0 b9 00 00 
+ 110:	80 ce f2 2b 	R5.H = R2.L >>> 0x2 \|\| R0=\[FP-4\] \|\| NOP;
+ 114:	f0 b9 00 00 
+ 118:	00 ce 14 16 	R3.L= ASHIFT R4.H BY R2.L \|\| R0=\[FP-100\] \|\| NOP;
+ 11c:	70 b8 00 00 
+ 120:	00 ce 07 6e 	R7.H= ASHIFT R7.L BY R0.L\(S\) \|\| R0=\[FP-104\] \|\| NOP;
+ 124:	60 b8 00 00 
+ 128:	00 ce 07 6e 	R7.H= ASHIFT R7.L BY R0.L\(S\) \|\| R0=\[FP-108\] \|\| NOP;
+ 12c:	50 b8 00 00 
+ 130:	02 ce 15 0c 	R6= ASHIFT R5 BY R2.L \|\| R0=\[FP-112\] \|\| NOP;
+ 134:	40 b8 00 00 
+ 138:	02 ce 0c 40 	R0= ASHIFT R4 BY R1.L\(S\) \|\| R3=\[FP-116\] \|\| NOP;
+ 13c:	33 b8 00 00 
+ 140:	02 ce 1e 44 	R2= ASHIFT R6 BY R3.L\(S\) \|\| R0=\[FP-120\] \|\| NOP;
+ 144:	20 b8 00 00 
+ 148:	03 ce 08 00 	A0= ASHIFT A0 BY R1.L \|\| R0=\[FP-124\] \|\| NOP;
+ 14c:	10 b8 00 00 
+ 150:	03 ce 00 10 	A1= ASHIFT A1 BY R0.L \|\| R0=\[FP-128\] \|\| NOP;
+ 154:	00 b8 00 00 
+ 158:	80 ce 8a a3 	R1.H = R2.L >> 0xf \|\| R5=W\[P1--\] \(Z\) \|\| NOP;
+ 15c:	8d 94 00 00 
+ 160:	80 ce 00 8e 	R7.L = R0.L << 0x0 \|\| R5=W\[P2\] \(Z\) \|\| NOP;
+ 164:	15 95 00 00 
+ 168:	82 ce 0d 8b 	R5=R5>>0x1f \|\| R7=W\[P2\+\+\] \(Z\) \|\| NOP;
+ 16c:	17 94 00 00 
+ 170:	82 ce 60 80 	R0=R0<<0xc \|\| R5=W\[P2--\] \(Z\) \|\| NOP;
+ 174:	95 94 00 00 
+ 178:	83 ce f8 41 	A0=A0>>0x1 \|\| R5=W\[P2\+0x0\] \(Z\) \|\| NOP;
+ 17c:	15 a4 00 00 
+ 180:	83 ce 00 00 	A0=A0<<0x0 \|\| R5=W\[P2\+0x2\] \(Z\) \|\| NOP;
+ 184:	55 a4 00 00 
+ 188:	83 ce f8 10 	A1=A1<<0x1f \|\| R5=W\[P2\+0x4\] \(Z\) \|\| NOP;
+ 18c:	95 a4 00 00 
+ 190:	83 ce 80 51 	A1=A1>>0x10 \|\| R5=W\[P2\+0x1e\] \(Z\) \|\| NOP;
+ 194:	d5 a7 00 00 
+ 198:	00 ce 02 b2 	R1.H= LSHIFT R2.H BY R0.L \|\| R5=W\[P2\+0x18\] \(Z\) \|\| NOP;
+ 19c:	15 a7 00 00 
+ 1a0:	00 ce 08 90 	R0.L= LSHIFT R0.H BY R1.L \|\| R5=W\[P2\+0x16\] \(Z\) \|\| NOP;
+ 1a4:	d5 a6 00 00 
+ 1a8:	00 ce 16 8e 	R7.L= LSHIFT R6.L BY R2.L \|\| R5=W\[P2\+0x14\] \(Z\) \|\| NOP;
+ 1ac:	95 a6 00 00 
+ 1b0:	02 ce 1c 8a 	R5=SHIFT R4 BY R3.L \|\| R4=W\[P2\+0x12\] \(Z\) \|\| NOP;
+ 1b4:	54 a6 00 00 
+ 1b8:	03 ce 30 40 	A0= LSHIFT A0 BY R6.L \|\| R5=W\[P2\+0x10\] \(Z\) \|\| NOP;
+ 1bc:	15 a6 00 00 
+ 1c0:	03 ce 28 50 	A1= LSHIFT A1 BY R5.L \|\| R5=W\[P2\+0xe\] \(Z\) \|\| NOP;
+ 1c4:	d5 a5 00 00 
+ 1c8:	82 ce 07 cf 	R7= ROT R7 BY -32 \|\| R5=W\[P2\+0xc\] \(Z\) \|\| NOP;
+ 1cc:	95 a5 00 00 
+ 1d0:	82 ce 0f cd 	R6= ROT R7 BY -31 \|\| R5=W\[P2\+0xa\] \(Z\) \|\| NOP;
+ 1d4:	55 a5 00 00 
+ 1d8:	82 ce ff ca 	R5= ROT R7 BY 0x1f \|\| R6=W\[P2\+0x8\] \(Z\) \|\| NOP;
+ 1dc:	16 a5 00 00 
+ 1e0:	82 ce f7 c8 	R4= ROT R7 BY 0x1e \|\| R5=W\[P2\+0x6\] \(Z\) \|\| NOP;
+ 1e4:	d5 a4 00 00 
+ 1e8:	83 ce 00 80 	A0= ROT A0 BY 0x0 \|\| R5=W\[P3\] \(Z\) \|\| NOP;
+ 1ec:	1d 95 00 00 
+ 1f0:	83 ce 50 80 	A0= ROT A0 BY 0xa \|\| R5=W\[P3\+\+\] \(Z\) \|\| NOP;
+ 1f4:	1d 94 00 00 
+ 1f8:	83 ce 60 91 	A1= ROT A1 BY -20 \|\| R5=W\[P3--\] \(Z\) \|\| NOP;
+ 1fc:	9d 94 00 00 
+ 200:	83 ce 00 91 	A1= ROT A1 BY -32 \|\| R5=W\[P4\] \(Z\) \|\| NOP;
+ 204:	25 95 00 00 
+ 208:	02 ce 11 c0 	R0= ROT R1 BY R2.L \|\| R5=W\[P4\+\+\] \(Z\) \|\| NOP;
+ 20c:	25 94 00 00 
+ 210:	02 ce 1c c0 	R0= ROT R4 BY R3.L \|\| R5=W\[P4--\] \(Z\) \|\| NOP;
+ 214:	a5 94 00 00 
+ 218:	03 ce 38 80 	A0= ROT A0 BY R7.L \|\| R5=W\[P5\] \(Z\) \|\| NOP;
+ 21c:	2d 95 00 00 
+ 220:	03 ce 30 90 	A1= ROT A1 BY R6.L \|\| R5=W\[P5\+\+\] \(Z\) \|\| NOP;
+ 224:	2d 94 00 00 
+ 228:	03 c8 00 18 	mnop \|\| R5=W\[P5--\] \(Z\) \|\| NOP;
+ 22c:	ad 94 00 00 
diff --git a/gas/testsuite/gas/bfin/parallel2.s b/gas/testsuite/gas/bfin/parallel2.s
new file mode 100644
index 000000000000..064e98fbd724
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel2.s
@@ -0,0 +1,80 @@
+	.section .text;

+	A0 = A1 || P0 = [sp+20];

+	a1 = a0 || P0 = [p5+24];

+	a0 = R0 || P0 = [P4+28];

+	A1 = r1 || P0 = [P3+32];

+

+	R4 = A0 (fu) || P0 = [p3+36];

+	r5 = A1 (ISS2) || P0 = [P3+40];

+	R6 = a0 || P0 = [P4+44];

+	R7 = A1 || P0 = [P4+48];

+	R6 = A0, R7 = a1 || P0 = [P4+52];

+	r1 = a1, r0 = a0 (fu) || P0 = [P4+56];

+

+	A0.X = r5.l || p0 = [p4+60];

+	a1.X = r2.L || r0 = [i0 ++ m0];

+	r0.l = a0.x || r1 = [i0 ++ m1];

+	R7.l = A1.X || r0 = [i0 ++ m2];

+	A0.L = r3.l || r0 = [i0 ++ m3];

+	a1.l = r4.l || r0 = [i1 ++ m3];

+	A0.h = r6.H || r0 = [i1 ++ m2];

+	A1.H = r5.h || r0 = [i1 ++ m1];

+	r0.l = A0 (iu) || r4 = [i1 ++ m0];

+	R1.H = A1 (s2rnd) || r0 = [i2 ++ m0];

+	r1.h = a1 || r0 = [i2 ++ m1];

+	R2.l = A0, r2.H = A1 (IH) || r0 = [i2 ++ m2];

+	R2.l = A0, r2.H = A1 || r0 = [i2 ++ m3];

+	r0.H = A1, R0.L = a0 (t) || r5 = [i3 ++ m0];

+	r0.H = A1, R0.L = a0 (fu) || r5 = [i3 ++ m1];

+	r0.H = A1, R0.L = a0 (is) || r5 = [i3 ++ m2];

+	r0.H = A1, R0.L = a0 || r5 = [i3 ++ m3];

+

+	A0 = A0 >> 31 || r0 = [fp - 32];

+	a0 = a0 << 31 || r0 = [fp - 28];

+	a1 = a1 >> 0 || r0 = [fp - 24];

+	A1 = A1 << 0 || r0 = [fp - 20];

+	r7 = r5 << 31 (s) || r0 = [fp - 16];

+	R3 = r2 >>> 22 || r0 = [fp - 12];

+	r1.L = R2.H << 15 (S) || r0 = [fp - 8];

+	r5.h = r2.l >>> 2 || r0 = [fp - 4];

+

+	r3.l = Ashift  r4.h by r2.l || r0 = [fp - 100];

+	R7.H = ASHIFT R7.L by R0.L (S) || r0 = [fp - 104];

+	r7.h = ashift  r7.l by r0.l (s) || r0 = [fp - 108];

+	r6 = AShiFT R5 by R2.L || r0 = [fp - 112];

+	R0 = Ashift R4 by r1.l (s) || r3 = [fp - 116];

+	r2 = ashift r6 BY r3.L (S) || r0 = [fp - 120];

+	A0 = Ashift a0 by r1.l || r0 = [fp - 124];

+	a1 = ASHIFT a1 by r0.L || r0 = [fp - 128];

+

+	r1.H = r2.l >> 15 || R5 = W [P1--] (z);

+	r7.l = r0.L << 0 || R5 = W [P2] (z);

+	r5 = r5 >> 31 || R7 = W [P2++] (z);

+	r0 = r0 << 12 || R5 = W [P2--] (z);

+	A0 = A0 >> 1 || R5 = W [P2+0] (z);

+	A0 = A0 << 0 || R5 = W [P2+2] (z);

+	a1 = A1 << 31 || R5 = W [P2+4] (z);

+	a1 = a1 >> 16 || R5 = W [P2+30] (z);

+	

+	R1.H = LShift r2.h by r0.l || R5 = W [P2+24] (z);

+	r0.l = LSHIFT r0.h by r1.l || R5 = W [P2+22] (z);

+	r7.L = lshift r6.L BY r2.l || R5 = W [P2+20] (z);

+	r5 = LShIft R4 bY r3.L || R4 = W [P2+18] (z);

+	A0 = Lshift a0 By R6.L || R5 = W [P2+16] (z);

+	A1 = LsHIFt a1 by r5.l || R5 = W [P2+14] (z);

+

+	r7 = ROT r7 by -32 || R5 = W [P2+12] (z);

+	R6 = Rot r7 by -31 || R5 = W [P2+10] (z);

+	R5 = RoT R7 by 31 || R6 = W [P2+8] (z);

+	R4 = Rot r7 by 30 || R5 = W [P2+6] (z);

+	a0 = rot A0 by 0 || R5 = W [P3] (z);

+	A0 = ROT a0 BY 10 || R5 = W [P3++] (z);

+	A1 = ROT A1 by -20 || R5 = W [P3--] (z);

+	A1 = ROT a1 By -32 || R5 = W [P4] (z);

+

+	r0 = rot r1 by r2.L || R5 = W [P4++] (z);

+	R0 = Rot R4 BY R3.L || R5 = W [P4--] (z);

+	A0 = ROT A0 by r7.l || R5 = W [P5] (z);

+	A1 = rot a1 bY r6.l || R5 = W [P5++] (z);

+

+	NOp || R5 = W [P5--] (z);

diff --git a/gas/testsuite/gas/bfin/parallel3.d b/gas/testsuite/gas/bfin/parallel3.d
new file mode 100644
index 000000000000..afada020fec2
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel3.d
@@ -0,0 +1,159 @@
+#objdump: -d
+#name: parallel3
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	0c cc 0d 08 	R4.H=R4.L=SIGN\(R1.H\)\*R5.H\+SIGN\(R1.L\)\*R5.L\) \|\| \[P0\]=P0 \|\| NOP;
+   4:	40 93 00 00 
+   8:	09 ce 15 8e 	R7=VIT_MAX\(R5,R2\)\(ASL\) \|\| \[P0\+\+\]=P0 \|\| NOP;
+   c:	40 92 00 00 
+  10:	09 ce 30 c0 	R0=VIT_MAX\(R0,R6\)\(ASR\) \|\| \[P0--\]=P0 \|\| NOP;
+  14:	c0 92 00 00 
+  18:	09 ce 03 0a 	R5.L=VIT_MAX \(R3\) \(ASL\) \|\| \[P0\+0x4\]=P0 \|\| NOP;
+  1c:	40 bc 00 00 
+  20:	09 ce 02 44 	R2.L=VIT_MAX \(R2\) \(ASR\) \|\| \[P0\+0x8\]=P0 \|\| NOP;
+  24:	80 bc 00 00 
+  28:	06 cc 28 8a 	R5= ABS R5\(V\) \|\| \[P0\+0x3c\]=P0 \|\| NOP;
+  2c:	c0 bf 00 00 
+  30:	06 cc 00 84 	R2= ABS R0\(V\) \|\| \[P0\+0x38\]=P0 \|\| NOP;
+  34:	80 bf 00 00 
+  38:	00 cc 1a 0a 	R5=R3\+\|\+R2  \|\| \[P0\+0x34\]=P0 \|\| NOP;
+  3c:	40 bf 00 00 
+  40:	00 cc 1a 3a 	R5=R3\+\|\+R2 \(SCO\) \|\| \[P1\]=P0 \|\| NOP;
+  44:	48 93 00 00 
+  48:	00 cc 06 8e 	R7=R0-\|\+R6  \|\| \[P1\+\+\]=P0 \|\| NOP;
+  4c:	48 92 00 00 
+  50:	00 cc 0b a4 	R2=R1-\|\+R3 \(S\) \|\| \[P1--\]=P0 \|\| NOP;
+  54:	c8 92 00 00 
+  58:	00 cc 02 48 	R4=R0\+\|-R2  \|\| \[P1\+0x30\]=P0 \|\| NOP;
+  5c:	08 bf 00 00 
+  60:	00 cc 0a 5a 	R5=R1\+\|-R2 \(CO\) \|\| \[P1\+0x2c\]=P0 \|\| NOP;
+  64:	c8 be 00 00 
+  68:	00 cc 1c cc 	R6=R3-\|-R4  \|\| \[P1\+0x28\]=P0 \|\| NOP;
+  6c:	88 be 00 00 
+  70:	00 cc 2e de 	R7=R5-\|-R6 \(CO\) \|\| \[P2\]=P0 \|\| NOP;
+  74:	50 93 00 00 
+  78:	01 cc 63 bf 	R5=R4\+\|\+R3,R7=R4-\|-R3\(SCO,ASR\) \|\| \[P2\+\+\]=P0 \|\| NOP;
+  7c:	50 92 00 00 
+  80:	01 cc 1e c2 	R0=R3\+\|\+R6,R1=R3-\|-R6\(ASL\) \|\| \[P2--\]=P0 \|\| NOP;
+  84:	d0 92 00 00 
+  88:	21 cc ca 2d 	R7=R1\+\|-R2,R6=R1-\|\+R2\(S\) \|\| \[P2\+0x24\]=P0 \|\| NOP;
+  8c:	50 be 00 00 
+  90:	21 cc 53 0a 	R1=R2\+\|-R3,R5=R2-\|\+R3 \|\| \[P2\+0x20\]=P0 \|\| NOP;
+  94:	10 be 00 00 
+  98:	04 cc 41 8d 	R5=R0\+R1,R6=R0-R1 \(NS\) \|\| \[P3\]=P0 \|\| NOP;
+  9c:	58 93 00 00 
+  a0:	04 cc 39 a6 	R0=R7\+R1,R3=R7-R1 \(S\) \|\| \[P3\+\+\]=P0 \|\| NOP;
+  a4:	58 92 00 00 
+  a8:	11 cc c0 0b 	R7=A1\+A0,R5=A1-A0 \(NS\) \|\| \[P3--\]=P0 \|\| NOP;
+  ac:	d8 92 00 00 
+  b0:	11 cc c0 6c 	R3=A0\+A1,R6=A0-A1 \(S\) \|\| \[P3\+0x1c\]=P0 \|\| NOP;
+  b4:	d8 bd 00 00 
+  b8:	81 ce 8b 03 	R1=R3>>>0xf \(V\) \|\| \[P3\+0x18\]=P0 \|\| NOP;
+  bc:	98 bd 00 00 
+  c0:	81 ce e0 09 	R4=R0>>>0x4 \(V\) \|\| \[P4\]=P0 \|\| NOP;
+  c4:	60 93 00 00 
+  c8:	81 ce 00 4a 	R5=R0<<0x0 \(V, S\) \|\| \[P4\+\+\]=P0 \|\| NOP;
+  cc:	60 92 00 00 
+  d0:	81 ce 62 44 	R2=R2<<0xc \(V, S\) \|\| \[P4--\]=P0 \|\| NOP;
+  d4:	e0 92 00 00 
+  d8:	01 ce 15 0e 	R7= ASHIFT R5 BY R2.L\(V\) \|\| \[P4\+0x18\]=P0 \|\| NOP;
+  dc:	a0 bd 00 00 
+  e0:	01 ce 02 40 	R0= ASHIFT R2 BY R0.L\(V,S\) \|\| \[P4\+0x14\]=P0 \|\| NOP;
+  e4:	60 bd 00 00 
+  e8:	81 ce 8a 8b 	R5=R2 >> 0xf \(V\) \|\| \[P4\+0x10\]=P0 \|\| NOP;
+  ec:	20 bd 00 00 
+  f0:	81 ce 11 80 	R0=R1<<0x2 \(V\) \|\| \[P4\+0xc\]=P0 \|\| NOP;
+  f4:	e0 bc 00 00 
+  f8:	01 ce 11 88 	R4=SHIFT R1 BY R2.L\(V\) \|\| \[P5\]=P0 \|\| NOP;
+  fc:	68 93 00 00 
+ 100:	06 cc 01 0c 	R6=MAX\(R0,R1\)\(V\) \|\| \[P5\+\+\]=P0 \|\| NOP;
+ 104:	68 92 00 00 
+ 108:	06 cc 17 40 	R0=MIN\(R2,R7\)\(V\) \|\| \[P5--\]=P0 \|\| NOP;
+ 10c:	e8 92 00 00 
+ 110:	04 ca be 66 	R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H \|\| \[P5\+0x8\]=P0 \|\| NOP;
+ 114:	a8 bc 00 00 
+ 118:	04 ca 08 e1 	R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L \|\| \[P5\+0x4\]=P0 \|\| NOP;
+ 11c:	68 bc 00 00 
+ 120:	04 ca 1a a0 	R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L \|\| \[P5\]=P0 \|\| NOP;
+ 124:	68 93 00 00 
+ 128:	94 ca 5a e1 	R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\) \|\| \[SP\]=P0 \|\| NOP;
+ 12c:	70 93 00 00 
+ 130:	2c ca 27 e0 	R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\) \|\| \[SP\+\+\]=P0 \|\| NOP;
+ 134:	70 92 00 00 
+ 138:	0c ca 95 27 	R7 = R2.L \* R5.L, R6 = R2.H \* R5.H \|\| \[SP--\]=P0 \|\| NOP;
+ 13c:	f0 92 00 00 
+ 140:	24 cb 3e e0 	R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\) \|\| \[SP\+0x3c\]=P0 \|\| NOP;
+ 144:	f0 bf 00 00 
+ 148:	04 cb c1 e0 	R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\) \|\| \[FP\]=P0 \|\| NOP;
+ 14c:	78 93 00 00 
+ 150:	00 c8 13 46 	a1 = R2.L \* R3.H, a0 = R2.H \* R3.H \|\| \[FP\+\+\]=P0 \|\| NOP;
+ 154:	78 92 00 00 
+ 158:	01 c8 08 c0 	a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L \|\| \[FP--\]=P0 \|\| NOP;
+ 15c:	f8 92 00 00 
+ 160:	60 c8 2f c8 	a1 = R5.H \* R7.H, a0 \+= R5.L \* R7.L \(W32\) \|\| \[FP\+0x0\]=P0 \|\| NOP;
+ 164:	38 bc 00 00 
+ 168:	01 c9 01 c0 	a1 \+= R0.H \* R1.H, a0 = R0.L \* R1.L \(IS\) \|\| \[FP\+0x3c\]=P0 \|\| NOP;
+ 16c:	f8 bf 00 00 
+ 170:	90 c8 1c c8 	a1 = R3.H \* R4.H \(M\), a0 \+= R3.L \* R4.L \(FU\) \|\| \[P0\]=P1 \|\| NOP;
+ 174:	41 93 00 00 
+ 178:	01 c8 24 96 	a1 \+= R4.H \* R4.L, a0 -= R4.H \* R4.H \|\| \[P0\]=P2 \|\| NOP;
+ 17c:	42 93 00 00 
+ 180:	25 c9 3e e8 	R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[P0\]=P3 \|\| NOP;
+ 184:	43 93 00 00 
+ 188:	27 c8 81 28 	R2.H = A1, R2.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[P0\]=P4 \|\| NOP;
+ 18c:	44 93 00 00 
+ 190:	04 c8 d1 c9 	R7.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L \|\| \[P0\]=P5 \|\| NOP;
+ 194:	45 93 00 00 
+ 198:	04 c8 be 66 	R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\) \|\| \[P0\]=FP \|\| NOP;
+ 19c:	47 93 00 00 
+ 1a0:	05 c8 9a e1 	R6.H = \(a1 \+= R3.H \* R2.H\), R6.L = \(a0 = R3.L \* R2.L\) \|\| \[P0\]=SP \|\| NOP;
+ 1a4:	46 93 00 00 
+ 1a8:	05 c8 f5 a7 	R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\) \|\| \[P0\]=R1 \|\| NOP;
+ 1ac:	01 93 00 00 
+ 1b0:	14 c8 3c a8 	R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\) \|\| \[P0\+\+\]=R2 \|\| NOP;
+ 1b4:	02 92 00 00 
+ 1b8:	94 c8 5a e9 	R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\) \|\| \[P1--\]=R3 \|\| NOP;
+ 1bc:	8b 92 00 00 
+ 1c0:	05 c9 1a e0 	R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\) \|\| \[I0\]=R0 \|\| NOP;
+ 1c4:	00 9f 00 00 
+ 1c8:	1c c8 b7 d0 	R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L \|\| \[I0\+\+\]=R1 \|\| NOP;
+ 1cc:	01 9e 00 00 
+ 1d0:	1c c8 3c 2e 	R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\) \|\| \[I0--\]=R2 \|\| NOP;
+ 1d4:	82 9e 00 00 
+ 1d8:	2d c9 3e e8 	R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\) \|\| \[I1\]=R3 \|\| NOP;
+ 1dc:	0b 9f 00 00 
+ 1e0:	0d c8 37 e1 	R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\) \|\| \[I1\+\+\]=R3 \|\| NOP;
+ 1e4:	0b 9e 00 00 
+ 1e8:	0d c8 9d f1 	R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\) \|\| \[I1--\]=R3 \|\| NOP;
+ 1ec:	8b 9e 00 00 
+ 1f0:	0e c8 37 c9 	R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L \|\| \[I2\]=R0 \|\| NOP;
+ 1f4:	10 9f 00 00 
+ 1f8:	0c c8 b7 e0 	R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\) \|\| \[I2\+\+\]=R0 \|\| NOP;
+ 1fc:	10 9e 00 00 
+ 200:	9c c8 1f e9 	R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\) \|\| \[I2--\]=R0 \|\| NOP;
+ 204:	90 9e 00 00 
+ 208:	2f c8 81 28 	R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\) \|\| \[I3\]=R7 \|\| NOP;
+ 20c:	1f 9f 00 00 
+ 210:	0d c9 1a e0 	R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\) \|\| \[I3\+\+\]=R7 \|\| NOP;
+ 214:	1f 9e 00 00 
+ 218:	0f cc 08 c0 	R0=-R1\(V\) \|\| \[I3--\]=R6 \|\| NOP;
+ 21c:	9e 9e 00 00 
+ 220:	0f cc 10 ce 	R7=-R2\(V\) \|\| \[P0\+\+P1\]=R0 \|\| NOP;
+ 224:	08 88 00 00 
+ 228:	04 ce 08 8e 	R7=PACK\(R0.H,R1.L\) \|\| \[P0\+\+P1\]=R3 \|\| NOP;
+ 22c:	c8 88 00 00 
+ 230:	04 ce 31 cc 	R6=PACK\(R1.H,R6.H\) \|\| \[P0\+\+P2\]=R0 \|\| NOP;
+ 234:	10 88 00 00 
+ 238:	04 ce 12 4a 	R5=PACK\(R2.L,R2.H\) \|\| \[P0\+\+P3\]=R4 \|\| NOP;
+ 23c:	18 89 00 00 
+ 240:	0d cc 10 82 	\(R0,R1\) = SEARCH R2\(LT\) \|\| R2=\[P0\+0x4\] \|\| NOP;
+ 244:	42 a0 00 00 
+ 248:	0d cc 80 cf 	\(R6,R7\) = SEARCH R0\(LE\) \|\| R5=\[P0--\] \|\| NOP;
+ 24c:	85 90 00 00 
+ 250:	0d cc c8 0c 	\(R3,R6\) = SEARCH R1\(GT\) \|\| R0=\[P0\+0x14\] \|\| NOP;
+ 254:	40 a1 00 00 
+ 258:	0d cc 18 4b 	\(R4,R5\) = SEARCH R3\(GE\) \|\| R1=\[P0\+\+\] \|\| NOP;
+ 25c:	01 90 00 00 
diff --git a/gas/testsuite/gas/bfin/parallel3.s b/gas/testsuite/gas/bfin/parallel3.s
new file mode 100644
index 000000000000..538fad701ec0
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel3.s
@@ -0,0 +1,95 @@
+	.section .text;

+	r4.h = r4.l = Sign (R1.h) * R5.h + Sign(r1.L) * R5.L|| [p0] = P0;

+

+	R7 = Vit_Max (R5, r2) (ASL)|| [p0++] = P0;

+	r0 = VIT_MAX (r0, r6) (asr)|| [p0--] = P0;

+	r5.l = vit_max (R3) (asL)|| [p0+4] = P0;

+	r2.L = VIT_Max (r2) (Asr)|| [p0+8] = P0;

+

+	R5 = ABS R5 (V)|| [p0+60] = P0;

+	r2 = abs r0 (v)|| [p0+56] = P0;

+

+	R5 = r3 +|+ R2|| [p0+52] = P0;

+	r5 = r3 +|+ r2 (Sco)|| [p1] = P0;

+	r7 = R0 -|+ r6|| [p1++] = P0;

+	r2 = R1 -|+ R3 (S)|| [p1--] = P0;

+	R4 = R0 +|- R2|| [p1+48] = P0;

+	R5 = r1 +|- r2 (CO)|| [p1+44] = P0;

+	r6 = r3 -|- R4|| [p1+40] = P0;

+	r7 = R5 -|- R6 (co)|| [p2] = P0;

+

+	r5 = r4 +|+ r3, R7 = r4 -|- r3 (Sco, ASR)|| [p2++] = P0;

+	R0 = R3 +|+ r6, R1 = R3 -|- R6 (ASL)|| [p2--] = P0;

+	R7 = R1 +|- R2, R6 = R1 -|+ R2 (S)|| [p2+36] = P0;

+	r1 = r2 +|- r3, r5 = r2 -|+ r3|| [p2+32] = P0;

+

+	R5 = R0 + R1, R6 = R0 - R1|| [p3] = P0;

+	r0 = r7 + r1, r3 = r7 - r1 (s)|| [p3++] = P0;

+

+	r7 = A1 + A0, r5 = A1 - A0|| [p3--] = P0;

+	r3 = a0 + a1, r6 = a0 - a1 (s)|| [p3+28] = P0;

+

+	R1 = R3 >>> 15 (V)|| [p3+24] = P0;

+	r4 = r0 >>> 4 (v)|| [p4] = P0;

+	r5 = r0 << 0 (v,s)|| [p4++] = P0;

+	r2 = r2 << 12 (v, S)|| [p4--] = P0;

+

+	R7 = ASHIFT R5 BY R2.L (V)|| [p4+24] = P0;

+	r0 = Ashift r2 by r0.L (v, s)|| [p4+20] = P0;

+

+	R5 = r2 >> 15 (V)|| [p4+16] = P0;

+	r0 = R1 << 2 (v)|| [p4+12] = P0;

+

+	R4 = lshift r1 by r2.L (v)|| [p5] = P0;

+

+	R6 = MAX (R0, R1) (V)|| [p5++] = P0;

+	r0 = min (r2, r7) (v)|| [p5--] = P0;

+

+	r2.h = r7.l * r6.h, r2.l = r7.h * r6.h|| [p5+8] = P0;

+	R4.L = R1.L * R0.L, R4.H = R1.H * R0.H|| [p5+4] = P0;

+	R0.h = R3.H * r2.l, r0.l=r3.l * r2.l|| [p5] = P0;

+	r5.h = r3.h * r2.h (M), r5.l = r3.L * r2.L (fu)|| [sp] = P0;

+	R0 = r4.l * r7.l, r1 = r4.h * r7.h (s2rnd)|| [sp++] = P0;

+	R7 = R2.l * r5.l, r6 = r2.h * r5.h|| [sp--] = P0;

+	R0.L = R7.L * R6.L, R0.H = R7.H * R6.H (ISS2)|| [sp+60] = P0;

+	r3.h = r0.h * r1.h, r3.l = r0.l * r1.l (is)|| [fp] = P0;

+

+	a1 = r2.l * r3.h, a0 = r2.h * R3.H|| [fp++] = P0;

+	A0 = R1.l * R0.L, A1 += R1.h * R0.h|| [fp--] = P0;

+	A1 = R5.h * R7.H, A0 += r5.L * r7.l (w32)|| [fp+0] = P0;

+	a1 += r0.H * r1.H, A0 = R0.L * R1.l (is)|| [fp+60] = P0;

+	a1 = r3.h * r4.h (m), a0 += r3.l * R4.L (FU)|| [p0] = P1;

+	A1 += r4.H * R4.L, a0 -= r4.h * r4.h|| [p0] = P2;

+

+	r0.l = (a0 += R7.l * R6.L), R0.H = (A1 += R7.H * R6.H) (Iss2)|| [p0] = P3;

+	r2.H = A1, r2.l = (a0 += r0.L * r1.L) (s2rnd)|| [p0] = P4;

+	r7.h = (a1 = r2.h * r1.h), a0 += r2.l * r1.l|| [p0] = P5;

+	R2.H = (A1 = R7.L * R6.H), R2.L = (A0 = R7.H * R6.h)|| [p0] = fp;

+	r6.L = (A0 = R3.L * r2.L), R6.H = (A1 += R3.H * R2.H)|| [p0] = sp;

+	R7.h = (a1 += r6.h * r5.l), r7.l = (a0=r6.h * r5.h)|| [p0] = r1;

+	r0.h = (A1 = r7.h * R4.l) (M), R0.l = (a0 += r7.l * r4.l)|| [p0++] = r2;

+	R5.H = (a1 = r3.h * r2.h) (m), r5.l= (a0 += r3.l * r2.l) (fu)|| [p1--] = r3;

+	r0.h = (A1 += R3.h * R2.h), R0.L = ( A0 = R3.L * R2.L) (is)|| [i0] = r0;

+

+	R3 = (A1 = R6.H * R7.H) (M), A0 -= R6.L * R7.L|| [i0++] = r1;

+	r1 = (a1 = r7.l * r4.l) (m), r0 = (a0 += r7.h * r4.h)|| [i0--] = r2;

+	R0 = (a0 += r7.l * r6.l), r1 = (a1+= r7.h * r6.h) (ISS2)|| [i1] = r3;

+	r4 = (a0 = r6.l * r7.l), r5 = (a1 += r6.h * r7.h)|| [i1++] = r3;

+	R7 = (A1 += r3.h * r5.H), R6 = (A0 -= r3.l * r5.l)|| [i1--] = r3;

+	r5 = (a1 -= r6.h * r7.h), a0 += r6.l * r7.l|| [i2] = r0;

+	R3 = (A1 = r6.h * R7.h), R2 = (A0 = R6.l * r7.l)|| [i2++] = r0;

+	R5 = (A1 = r3.h * r7.h) (M), r4 = (A0 += R3.l * r7.l) (fu)|| [i2--] = R0;

+	R3 = a1, r2 = (a0 += r0.l *r1.l) (s2rnd)|| [i3] = R7;

+	r1 = (a1 += r3.h * r2.h), r0 = (a0 = r3.l * r2.l) (is)|| [i3++] = R7;

+

+	R0 = - R1 (V)|| [i3--] = R6;

+	r7 = - r2 (v)|| [p0++p1] = R0;

+

+	R7 = Pack (r0.h, r1.l)|| [p0++p1] = R3;

+	r6 = PACK (r1.H, r6.H)|| [p0++p2] = r0;

+	R5 = pack (R2.L, R2.H)|| [p0++p3] = r4;

+	

+	(R0, R1) = search R2 (lt)|| r2 = [p0+4];

+	(r6, r7) = Search r0 (LE)|| r5 = [p0--];

+	(r3, r6) = SEARCH r1 (Gt)|| r0 = [p0+20];

+	(r4, R5) = sEARch r3 (gE)|| r1 = [p0++];

diff --git a/gas/testsuite/gas/bfin/parallel4.d b/gas/testsuite/gas/bfin/parallel4.d
new file mode 100644
index 000000000000..5b5d85f4359d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel4.d
@@ -0,0 +1,67 @@
+#objdump: -d
+#name: parallel4
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	0d ce 15 0e 	R7=ALIGN8\(R5,R2\) \|\| \[I0\]=R0 \|\| NOP;
+   4:	00 9f 00 00 
+   8:	0d ce 08 4a 	R5=ALIGN16\(R0,R1\) \|\| \[I0\+\+\]=R0 \|\| NOP;
+   c:	00 9e 00 00 
+  10:	0d ce 05 84 	R2=ALIGN24\(R5,R0\) \|\| \[I0--\]=R0 \|\| NOP;
+  14:	80 9e 00 00 
+  18:	12 cc 00 c0 	DISALGNEXCPT \|\| \[I1\]=R0 \|\| NOP;
+  1c:	08 9f 00 00 
+  20:	17 cc 02 0a 	R5=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\) \|\| \[I1\+\+\]=R0 \|\| NOP;
+  24:	08 9e 00 00 
+  28:	37 cc 02 00 	R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\) \|\| \[I1--\]=R0 \|\| NOP;
+  2c:	88 9e 00 00 
+  30:	17 cc 02 22 	R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\) \|\| \[I2\]=R0 \|\| NOP;
+  34:	10 9f 00 00 
+  38:	37 cc 02 24 	R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\) \|\| \[I2\+\+\]=R0 \|\| NOP;
+  3c:	10 9e 00 00 
+  40:	0c cc 40 45 	R5=A1.L\+A1.H,R2=A0.L\+A0.H \|\| \[I2--\]=R0 \|\| NOP;
+  44:	90 9e 00 00 
+  48:	15 cc 82 06 	\(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\)  \|\| \[I3\]=R0 \|\| NOP;
+  4c:	18 9f 00 00 
+  50:	15 cc 82 21 	\(R6,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\) \|\| \[I3\+\+\]=R0 \|\| NOP;
+  54:	18 9e 00 00 
+  58:	14 cc 02 4e 	R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\) \|\| \[I3--\]=R0 \|\| NOP;
+  5c:	98 9e 00 00 
+  60:	14 cc 02 44 	R2=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\) \|\| \[P0\]=R0 \|\| NOP;
+  64:	00 93 00 00 
+  68:	14 cc 02 26 	R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\) \|\| \[P0\+\+\]=R0 \|\| NOP;
+  6c:	00 92 00 00 
+  70:	14 cc 02 6e 	R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\) \|\| \[P0--\]=R0 \|\| NOP;
+  74:	80 92 00 00 
+  78:	16 cc 02 00 	R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\) \|\| \[P1\]=R0 \|\| NOP;
+  7c:	08 93 00 00 
+  80:	36 cc 02 02 	R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\) \|\| \[P1\+\+\]=R0 \|\| NOP;
+  84:	08 92 00 00 
+  88:	16 cc 02 44 	R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\) \|\| \[P1--\]=R0 \|\| NOP;
+  8c:	88 92 00 00 
+  90:	36 cc 02 46 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\) \|\| \[P2\]=R0 \|\| NOP;
+  94:	10 93 00 00 
+  98:	16 cc 02 28 	R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\) \|\| \[P2\+\+\]=R0 \|\| NOP;
+  9c:	10 92 00 00 
+  a0:	36 cc 02 2a 	R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\) \|\| \[P2--\]=R0 \|\| NOP;
+  a4:	90 92 00 00 
+  a8:	16 cc 02 6c 	R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\) \|\| \[P3\]=R0 \|\| NOP;
+  ac:	18 93 00 00 
+  b0:	36 cc 02 6e 	R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\) \|\| \[P3\+\+\]=R0 \|\| NOP;
+  b4:	18 92 00 00 
+  b8:	18 cc 03 0a 	R5=BYTEPACK\(R0,R3\) \|\| \[P3--\]=R0 \|\| NOP;
+  bc:	98 92 00 00 
+  c0:	15 cc 82 45 	\(R6,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\)  \|\| \[P4\]=R0 \|\| NOP;
+  c4:	20 93 00 00 
+  c8:	15 cc 02 6a 	\(R0,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\) \|\| \[P4\+\+\]=R0 \|\| NOP;
+  cc:	20 92 00 00 
+  d0:	12 cc 02 00 	SAA\(R1:0x0,R3:0x2\)  \|\| \[P4--\]=R0 \|\| NOP;
+  d4:	a0 92 00 00 
+  d8:	12 cc 02 20 	SAA\(R1:0x0,R3:0x2\) \(R\) \|\| \[P5\]=R0 \|\| NOP;
+  dc:	28 93 00 00 
+  e0:	18 cc c0 45 	\(R7,R2\) = BYTEUNPACK R1:0x0  \|\| \[P5\+\+\]=R0 \|\| NOP;
+  e4:	28 92 00 00 
+  e8:	18 cc 90 69 	\(R6,R4\) = BYTEUNPACK R3:0x2 \(R\) \|\| \[P5--\]=R0 \|\| NOP;
+  ec:	a8 92 00 00 
diff --git a/gas/testsuite/gas/bfin/parallel4.s b/gas/testsuite/gas/bfin/parallel4.s
new file mode 100644
index 000000000000..899050d45dc1
--- /dev/null
+++ b/gas/testsuite/gas/bfin/parallel4.s
@@ -0,0 +1,43 @@
+	.section .text;

+	R7 = Align8 (r5, r2) || [i0] = r0;

+	R5 = ALIGN16 (R0, R1) || [i0++] = r0;

+	r2 = ALIGN24 (r5, r0) || [i0--] = r0;

+

+	DISAlgnExcpt || [i1] = r0;

+

+	R5 = Byteop3p (r1:0, r3:2) (lO) 

+		|| [i1++] = r0;

+	R0 = BYTEOP3P (R1:0, R3:2) (HI) || // comment test

+		[i1--] = r0;

+	R1 = byteop3p (r1:0, r3:2) (LO, r) || [i2] = r0;

+	r2 = ByteOp3P (r1:0, R3:2) (hi, R) || [i2++] = r0;

+

+	R5 = A1.l + A1.h, R2 = a0.l + a0.h || [i2--] = r0;

+

+	(r2, r3) = BYTEOP16P (R1:0, R3:2) || [i3] = r0;

+	(R6, R0) = byteop16p (r1:0, r3:2) (r) || [i3++] = r0;

+

+	R7 = BYTEOP1P (R1:0, R3:2) (t) || [i3--] = r0;

+	r2 = byteop1p (r1:0, r3:2) (t) || [p0] = r0;

+	R3 = ByteOp1P (r1:0, R3:2) (R) || [p0++] = r0;

+	r7 = byteOP1P (R1:0, r3:2) (T, r) || [p0--] = r0;

+

+	R0 = BYTEOP2P (R1:0, R3:2) (RNDL) || [p1] = r0;

+	r1 = byteop2p (r1:0, r3:2) (rndh) || [p1++] = r0;

+	R2 = Byteop2p (R1:0, R3:2) (tL) || [p1--] = r0;

+	R3 = Byteop2p (r1:0, r3:2) (TH) || [p2] = r0;

+	r4 = ByTEOP2P (r1:0, R3:2) (Rndl, R) || [p2++] = r0;

+	R5 = byTeOp2p (R1:0, r3:2) (rndH, r) || [p2--] = r0;

+	r6 = BYTEop2p (r1:0, r3:2) (tl, R) || [p3] = r0;

+	R7 = byteop2p (r1:0, R3:2) (TH, r) || [p3++] = r0;

+

+	R5 = BytePack (R0, R3) || [p3--] = r0;

+

+	(R6, R2) = ByteOp16M (r1:0, r3:2) || [p4] = r0;

+	(r0, r5) = byteop16m (R1:0, R3:2) (r) || [p4++] = r0;

+

+	saa (r1:0, r3:2) || [p4--] = r0;

+	SAA (R1:0, R3:2) (r) || [p5] = r0;

+

+	(R7, R2) = byteunpack R1:0 || [p5++] = r0;

+	(R6, R4) = BYTEUNPACK r3:2 (R) || [p5--] = r0;

diff --git a/gas/testsuite/gas/bfin/reloc.d b/gas/testsuite/gas/bfin/reloc.d
new file mode 100644
index 000000000000..c2e402d2c8e1
--- /dev/null
+++ b/gas/testsuite/gas/bfin/reloc.d
@@ -0,0 +1,20 @@
+#objdump: -r
+#name: reloc
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET   TYPE              VALUE 
+0*0004 R_pcrel24         _call_data1
+0*0008 R_rimm16          .data
+0*000a R_pcrel12_jump_s  .text\+0x00000018
+0*000e R_pcrel24         call_data1\+0x00000008
+0*0012 R_huimm16         .data\+0x00000002
+0*0016 R_luimm16         .data\+0x00000004
+0*001a R_huimm16         load_extern1
+
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET   TYPE              VALUE 
+0*0006 R_byte_data       load_extern1
+
+
diff --git a/gas/testsuite/gas/bfin/reloc.s b/gas/testsuite/gas/bfin/reloc.s
new file mode 100644
index 000000000000..51162d9c3083
--- /dev/null
+++ b/gas/testsuite/gas/bfin/reloc.s
@@ -0,0 +1,19 @@
+	.extern load_extern1;
+	.extern call_data1;
+	.data
+load_data1:	.word 4567;
+load_data2:	.word 8901;
+load_data3:	.word 1243;
+load_data4:	.byte load_extern1;
+	.text
+	jump exit;
+	call _call_data1;
+	r5 = load_data1;
+	jump exit-4;
+	call call_data1+8;
+	r5.H = load_data2;
+	r7.L = load_data3;
+	r1.h = load_extern1;
+
+exit:
+
diff --git a/gas/testsuite/gas/bfin/shift.d b/gas/testsuite/gas/bfin/shift.d
new file mode 100644
index 000000000000..b355f72d0687
--- /dev/null
+++ b/gas/testsuite/gas/bfin/shift.d
@@ -0,0 +1,75 @@
+#objdump: -dr
+#name: shift
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <add_with_shift>:
+   0:	88 45       	P0=\(P0\+P1\)<<1;
+   2:	ea 45       	P2=\(P2\+P5\)<<2;
+   4:	4f 41       	R7=\(R7\+R1\)<<2;
+   6:	03 41       	R3=\(R3\+R0\)<<1;
+
+00000008 <shift_with_add>:
+   8:	44 5f       	P5=P4\+\(P0<<2\);
+   a:	0a 5c       	P0=P2\+\(P1<<1\);
+
+0000000c <arithmetic_shift>:
+   c:	83 c6 08 41 	A0=A0>>0x1f;
+  10:	83 c6 f8 00 	A0=A0<<0x1f;
+  14:	83 c6 00 50 	A1=A1>>0x0;
+  18:	83 c6 00 10 	A1=A1<<0x0;
+  1c:	82 c6 fd 4e 	R7=R5<<0x1f\(S\);
+  20:	82 c6 52 07 	R3=R2>>>0x16;
+  24:	80 c6 7a 52 	R1.L = R2.H << 0xf \(S\);
+  28:	80 c6 f2 2b 	R5.H = R2.L >>> 0x2;
+  2c:	00 4f       	R0<<=0x0;
+  2e:	f9 4d       	R1>>>=0x1f;
+  30:	08 40       	R0>>>=R1;
+  32:	8a 40       	R2<<=R1;
+  34:	00 c6 14 16 	R3.L= ASHIFT R4.H BY R2.L;
+  38:	00 c6 07 6e 	R7.H= ASHIFT R7.L BY R0.L\(S\);
+  3c:	00 c6 07 6e 	R7.H= ASHIFT R7.L BY R0.L\(S\);
+  40:	02 c6 15 0c 	R6= ASHIFT R5 BY R2.L;
+  44:	02 c6 0c 40 	R0= ASHIFT R4 BY R1.L\(S\);
+  48:	02 c6 1e 44 	R2= ASHIFT R6 BY R3.L\(S\);
+  4c:	03 c6 08 00 	A0= ASHIFT A0 BY R1.L;
+  50:	03 c6 00 10 	A1= ASHIFT A1 BY R0.L;
+
+00000054 <logical_shift>:
+  54:	00 45       	P0=P0>>1;
+  56:	d1 44       	P1=P2>>2;
+  58:	c9 5a       	P3=P1<<1;
+  5a:	6c 44       	P4=P5<<2;
+  5c:	f8 4e       	R0>>=0x1f;
+  5e:	ff 4f       	R7<<=0x1f;
+  60:	80 c6 8a a3 	R1.H = R2.L >> 0xf;
+  64:	80 c6 00 8e 	R7.L = R0.L << 0x0;
+  68:	82 c6 0d 8b 	R5=R5>>0x1f;
+  6c:	82 c6 60 80 	R0=R0<<0xc;
+  70:	83 c6 f8 41 	A0=A0>>0x1;
+  74:	83 c6 00 00 	A0=A0<<0x0;
+  78:	83 c6 f8 10 	A1=A1<<0x1f;
+  7c:	83 c6 80 51 	A1=A1>>0x10;
+  80:	7d 40       	R5>>=R7;
+  82:	86 40       	R6<<=R0;
+  84:	00 c6 02 b2 	R1.H= LSHIFT R2.H BY R0.L;
+  88:	00 c6 08 90 	R0.L= LSHIFT R0.H BY R1.L;
+  8c:	00 c6 16 8e 	R7.L= LSHIFT R6.L BY R2.L;
+  90:	02 c6 1c 8a 	R5=SHIFT R4 BY R3.L;
+  94:	03 c6 30 40 	A0= LSHIFT A0 BY R6.L;
+  98:	03 c6 28 50 	A1= LSHIFT A1 BY R5.L;
+
+0000009c <rotate>:
+  9c:	82 c6 07 cf 	R7= ROT R7 BY -32;
+  a0:	82 c6 0f cd 	R6= ROT R7 BY -31;
+  a4:	82 c6 ff ca 	R5= ROT R7 BY 0x1f;
+  a8:	82 c6 f7 c8 	R4= ROT R7 BY 0x1e;
+  ac:	83 c6 00 80 	A0= ROT A0 BY 0x0;
+  b0:	83 c6 50 80 	A0= ROT A0 BY 0xa;
+  b4:	83 c6 60 91 	A1= ROT A1 BY -20;
+  b8:	83 c6 00 91 	A1= ROT A1 BY -32;
+  bc:	02 c6 11 c0 	R0= ROT R1 BY R2.L;
+  c0:	02 c6 1c c0 	R0= ROT R4 BY R3.L;
+  c4:	03 c6 38 80 	A0= ROT A0 BY R7.L;
+  c8:	03 c6 30 90 	A1= ROT A1 BY R6.L;
diff --git a/gas/testsuite/gas/bfin/shift.s b/gas/testsuite/gas/bfin/shift.s
new file mode 100644
index 000000000000..b146f7d4c06f
--- /dev/null
+++ b/gas/testsuite/gas/bfin/shift.s
@@ -0,0 +1,87 @@
+	.text
+	.global add_with_shift
+add_with_shift:
+	P0 = (P0 + p1) << 1;
+	P2 = (p2 + p5) << 2;
+	r7 = (R7 + r1) << 2;
+	r3 = (r3 + R0) << 1;
+
+	.text
+	.global shift_with_add
+shift_with_add:
+	P5 = p4 + (P0 << 2);
+	P0 = p2 + (p1 << 1);
+
+	.text
+	.global arithmetic_shift
+arithmetic_shift:
+	A0 = A0 >> 31;
+	a0 = a0 << 31;
+	a1 = a1 >> 0;
+	A1 = A1 << 0;
+	r7 = r5 << 31 (s);
+	R3 = r2 >>> 22;
+	r1.L = R2.H << 15 (S);
+	r5.h = r2.l >>> 2;
+	r0 <<= 0;
+	r1 >>>= 31;
+
+	r0 >>>= R1;
+	R2 <<= R1;
+	r3.l = Ashift  r4.h by r2.l;
+	R7.H = ASHIFT R7.L by R0.L (S);
+	r7.h = ashift  r7.l by r0.l (s);
+	r6 = AShiFT R5 by R2.L;
+	R0 = Ashift R4 by r1.l (s);
+	r2 = ashift r6 BY r3.L (S);
+	A0 = Ashift a0 by r1.l;
+	a1 = ASHIFT a1 by r0.L;
+
+
+	.text
+	.global logical_shift
+logical_shift:
+	p0 = p0 >> 1;
+	P1 = p2 >> 2;
+	P3 = P1 << 1;
+	p4 = p5 << 2;
+
+	r0 >>= 31;
+	R7 <<= 31;
+	r1.H = r2.l >> 15;
+	r7.l = r0.L << 0;
+	r5 = r5 >> 31;
+	r0 = r0 << 12;
+	A0 = A0 >> 1;
+	A0 = A0 << 0;
+	a1 = A1 << 31;
+	a1 = a1 >> 16;
+	
+	r5 >>= R7;
+	R6 <<= r0;
+	R1.H = LShift r2.h by r0.l;
+	r0.l = LSHIFT r0.h by r1.l;
+	r7.L = lshift r6.L BY r2.l;
+	r5 = LShIft R4 bY r3.L;
+	A0 = Lshift a0 By R6.L;
+	A1 = LsHIFt a1 by r5.l;
+
+	.text
+	.global rotate
+rotate:
+	r7 = ROT r7 by -32;
+	R6 = Rot r7 by -31;
+	R5 = RoT R7 by 31;
+	R4 = Rot r7 by 30;
+	a0 = rot A0 by 0;
+	A0 = ROT a0 BY 10;
+	A1 = ROT A1 by -20;
+	A1 = ROT a1 By -32;
+
+	r0 = rot r1 by r2.L;
+	R0 = Rot R4 BY R3.L;
+	A0 = ROT A0 by r7.l;
+	A1 = rot a1 bY r6.l;
+
+
+
diff --git a/gas/testsuite/gas/bfin/shift2.d b/gas/testsuite/gas/bfin/shift2.d
new file mode 100644
index 000000000000..75416b14268c
--- /dev/null
+++ b/gas/testsuite/gas/bfin/shift2.d
@@ -0,0 +1,222 @@
+#objdump: -dr
+#name: shift2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	80 45       	P0=\(P0\+P0\)<<1;
+   2:	88 45       	P0=\(P0\+P1\)<<1;
+   4:	82 45       	P2=\(P2\+P0\)<<1;
+   6:	91 45       	P1=\(P1\+P2\)<<1;
+   8:	c0 45       	P0=\(P0\+P0\)<<2;
+   a:	c8 45       	P0=\(P0\+P1\)<<2;
+   c:	c2 45       	P2=\(P2\+P0\)<<2;
+   e:	d1 45       	P1=\(P1\+P2\)<<2;
+  10:	00 41       	R0=\(R0\+R0\)<<1;
+  12:	08 41       	R0=\(R0\+R1\)<<1;
+  14:	02 41       	R2=\(R2\+R0\)<<1;
+  16:	11 41       	R1=\(R1\+R2\)<<1;
+  18:	40 41       	R0=\(R0\+R0\)<<2;
+  1a:	48 41       	R0=\(R0\+R1\)<<2;
+  1c:	42 41       	R2=\(R2\+R0\)<<2;
+  1e:	51 41       	R1=\(R1\+R2\)<<2;
+  20:	00 5c       	P0=P0\+\(P0<<1\);
+  22:	08 5c       	P0=P0\+\(P1<<1\);
+  24:	10 5c       	P0=P0\+\(P2<<1\);
+  26:	11 5c       	P0=P1\+\(P2<<1\);
+  28:	1a 5c       	P0=P2\+\(P3<<1\);
+  2a:	40 5c       	P1=P0\+\(P0<<1\);
+  2c:	48 5c       	P1=P0\+\(P1<<1\);
+  2e:	50 5c       	P1=P0\+\(P2<<1\);
+  30:	51 5c       	P1=P1\+\(P2<<1\);
+  32:	5a 5c       	P1=P2\+\(P3<<1\);
+  34:	00 5e       	P0=P0\+\(P0<<2\);
+  36:	08 5e       	P0=P0\+\(P1<<2\);
+  38:	10 5e       	P0=P0\+\(P2<<2\);
+  3a:	11 5e       	P0=P1\+\(P2<<2\);
+  3c:	1a 5e       	P0=P2\+\(P3<<2\);
+  3e:	40 5e       	P1=P0\+\(P0<<2\);
+  40:	48 5e       	P1=P0\+\(P1<<2\);
+  42:	50 5e       	P1=P0\+\(P2<<2\);
+  44:	51 5e       	P1=P1\+\(P2<<2\);
+  46:	5a 5e       	P1=P2\+\(P3<<2\);
+  48:	00 4d       	R0>>>=0x0;
+  4a:	f8 4d       	R0>>>=0x1f;
+  4c:	28 4d       	R0>>>=0x5;
+  4e:	05 4d       	R5>>>=0x0;
+  50:	fd 4d       	R5>>>=0x1f;
+  52:	2d 4d       	R5>>>=0x5;
+  54:	00 4f       	R0<<=0x0;
+  56:	f8 4f       	R0<<=0x1f;
+  58:	28 4f       	R0<<=0x5;
+  5a:	05 4f       	R5<<=0x0;
+  5c:	fd 4f       	R5<<=0x1f;
+  5e:	2d 4f       	R5<<=0x5;
+  60:	80 c6 00 00 	R0.L = R0.L >>> 0x0;
+  64:	80 c6 88 01 	R0.L = R0.L >>> 0xf;
+  68:	80 c6 00 10 	R0.L = R0.H >>> 0x0;
+  6c:	80 c6 88 11 	R0.L = R0.H >>> 0xf;
+  70:	80 c6 00 20 	R0.H = R0.L >>> 0x0;
+  74:	80 c6 88 21 	R0.H = R0.L >>> 0xf;
+  78:	80 c6 00 30 	R0.H = R0.H >>> 0x0;
+  7c:	80 c6 88 31 	R0.H = R0.H >>> 0xf;
+  80:	80 c6 01 00 	R0.L = R1.L >>> 0x0;
+  84:	80 c6 89 01 	R0.L = R1.L >>> 0xf;
+  88:	80 c6 01 10 	R0.L = R1.H >>> 0x0;
+  8c:	80 c6 89 11 	R0.L = R1.H >>> 0xf;
+  90:	80 c6 01 20 	R0.H = R1.L >>> 0x0;
+  94:	80 c6 89 21 	R0.H = R1.L >>> 0xf;
+  98:	80 c6 01 30 	R0.H = R1.H >>> 0x0;
+  9c:	80 c6 89 31 	R0.H = R1.H >>> 0xf;
+  a0:	80 c6 07 00 	R0.L = R7.L >>> 0x0;
+  a4:	80 c6 8e 03 	R1.L = R6.L >>> 0xf;
+  a8:	80 c6 05 14 	R2.L = R5.H >>> 0x0;
+  ac:	80 c6 8c 17 	R3.L = R4.H >>> 0xf;
+  b0:	80 c6 03 28 	R4.H = R3.L >>> 0x0;
+  b4:	80 c6 8a 2b 	R5.H = R2.L >>> 0xf;
+  b8:	80 c6 01 3c 	R6.H = R1.H >>> 0x0;
+  bc:	80 c6 88 3f 	R7.H = R0.H >>> 0xf;
+  c0:	80 c6 00 40 	R0.L = R0.L << 0x0 \(S\);
+  c4:	80 c6 78 40 	R0.L = R0.L << 0xf \(S\);
+  c8:	80 c6 00 50 	R0.L = R0.H << 0x0 \(S\);
+  cc:	80 c6 78 50 	R0.L = R0.H << 0xf \(S\);
+  d0:	80 c6 00 60 	R0.H = R0.L << 0x0 \(S\);
+  d4:	80 c6 78 60 	R0.H = R0.L << 0xf \(S\);
+  d8:	80 c6 00 70 	R0.H = R0.H << 0x0 \(S\);
+  dc:	80 c6 78 70 	R0.H = R0.H << 0xf \(S\);
+  e0:	80 c6 01 40 	R0.L = R1.L << 0x0 \(S\);
+  e4:	80 c6 79 40 	R0.L = R1.L << 0xf \(S\);
+  e8:	80 c6 01 50 	R0.L = R1.H << 0x0 \(S\);
+  ec:	80 c6 79 50 	R0.L = R1.H << 0xf \(S\);
+  f0:	80 c6 01 60 	R0.H = R1.L << 0x0 \(S\);
+  f4:	80 c6 79 60 	R0.H = R1.L << 0xf \(S\);
+  f8:	80 c6 01 70 	R0.H = R1.H << 0x0 \(S\);
+  fc:	80 c6 79 70 	R0.H = R1.H << 0xf \(S\);
+ 100:	80 c6 07 40 	R0.L = R7.L << 0x0 \(S\);
+ 104:	80 c6 7e 42 	R1.L = R6.L << 0xf \(S\);
+ 108:	80 c6 05 54 	R2.L = R5.H << 0x0 \(S\);
+ 10c:	80 c6 7c 56 	R3.L = R4.H << 0xf \(S\);
+ 110:	80 c6 03 68 	R4.H = R3.L << 0x0 \(S\);
+ 114:	80 c6 7a 6a 	R5.H = R2.L << 0xf \(S\);
+ 118:	80 c6 01 7c 	R6.H = R1.H << 0x0 \(S\);
+ 11c:	80 c6 78 7e 	R7.H = R0.H << 0xf \(S\);
+ 120:	82 c6 00 00 	R0=R0>>>0x0;
+ 124:	82 c6 08 01 	R0=R0>>>0x1f;
+ 128:	82 c6 01 00 	R0=R1>>>0x0;
+ 12c:	82 c6 09 01 	R0=R1>>>0x1f;
+ 130:	82 c6 00 0e 	R7=R0>>>0x0;
+ 134:	82 c6 09 0d 	R6=R1>>>0x1f;
+ 138:	82 c6 02 0a 	R5=R2>>>0x0;
+ 13c:	82 c6 0b 09 	R4=R3>>>0x1f;
+ 140:	82 c6 04 06 	R3=R4>>>0x0;
+ 144:	82 c6 0d 05 	R2=R5>>>0x1f;
+ 148:	82 c6 06 02 	R1=R6>>>0x0;
+ 14c:	82 c6 0f 01 	R0=R7>>>0x1f;
+ 150:	82 c6 00 40 	R0=R0<<0x0\(S\);
+ 154:	82 c6 f8 40 	R0=R0<<0x1f\(S\);
+ 158:	82 c6 01 40 	R0=R1<<0x0\(S\);
+ 15c:	82 c6 f9 40 	R0=R1<<0x1f\(S\);
+ 160:	82 c6 00 4e 	R7=R0<<0x0\(S\);
+ 164:	82 c6 f9 4c 	R6=R1<<0x1f\(S\);
+ 168:	82 c6 02 4a 	R5=R2<<0x0\(S\);
+ 16c:	82 c6 fb 48 	R4=R3<<0x1f\(S\);
+ 170:	82 c6 04 46 	R3=R4<<0x0\(S\);
+ 174:	82 c6 fd 44 	R2=R5<<0x1f\(S\);
+ 178:	82 c6 06 42 	R1=R6<<0x0\(S\);
+ 17c:	82 c6 ff 40 	R0=R7<<0x1f\(S\);
+ 180:	83 c6 00 00 	A0=A0<<0x0;
+ 184:	83 c6 88 01 	A0=A0>>>0xf;
+ 188:	83 c6 08 01 	A0=A0>>>0x1f;
+ 18c:	83 c6 00 00 	A0=A0<<0x0;
+ 190:	83 c6 78 00 	A0=A0<<0xf;
+ 194:	83 c6 f8 00 	A0=A0<<0x1f;
+ 198:	83 c6 00 10 	A1=A1<<0x0;
+ 19c:	83 c6 88 11 	A1=A1>>>0xf;
+ 1a0:	83 c6 08 11 	A1=A1>>>0x1f;
+ 1a4:	83 c6 00 10 	A1=A1<<0x0;
+ 1a8:	83 c6 78 10 	A1=A1<<0xf;
+ 1ac:	83 c6 f8 10 	A1=A1<<0x1f;
+ 1b0:	00 40       	R0>>>=R0;
+ 1b2:	08 40       	R0>>>=R1;
+ 1b4:	01 40       	R1>>>=R0;
+ 1b6:	39 40       	R1>>>=R7;
+ 1b8:	80 40       	R0<<=R0;
+ 1ba:	88 40       	R0<<=R1;
+ 1bc:	81 40       	R1<<=R0;
+ 1be:	b9 40       	R1<<=R7;
+ 1c0:	00 c6 38 16 	R3.L= ASHIFT R0.H BY R7.L;
+ 1c4:	00 c6 38 26 	R3.H= ASHIFT R0.L BY R7.L;
+ 1c8:	00 c6 38 36 	R3.H= ASHIFT R0.H BY R7.L;
+ 1cc:	00 c6 38 06 	R3.L= ASHIFT R0.L BY R7.L;
+ 1d0:	00 c6 38 56 	R3.L= ASHIFT R0.H BY R7.L\(S\);
+ 1d4:	00 c6 38 66 	R3.H= ASHIFT R0.L BY R7.L\(S\);
+ 1d8:	00 c6 38 76 	R3.H= ASHIFT R0.H BY R7.L\(S\);
+ 1dc:	00 c6 38 46 	R3.L= ASHIFT R0.L BY R7.L\(S\);
+ 1e0:	02 c6 3a 08 	R4= ASHIFT R2 BY R7.L;
+ 1e4:	02 c6 3a 48 	R4= ASHIFT R2 BY R7.L\(S\);
+ 1e8:	03 c6 38 00 	A0= ASHIFT A0 BY R7.L;
+ 1ec:	03 c6 38 10 	A1= ASHIFT A1 BY R7.L;
+ 1f0:	13 45       	P3=P2>>1;
+ 1f2:	db 44       	P3=P3>>2;
+ 1f4:	2d 5b       	P4=P5<<1;
+ 1f6:	48 44       	P0=P1<<2;
+ 1f8:	8b 4e       	R3>>=0x11;
+ 1fa:	8b 4f       	R3<<=0x11;
+ 1fc:	80 c6 e0 87 	R3.L = R0.L >> 0x4;
+ 200:	80 c6 e0 97 	R3.L = R0.H >> 0x4;
+ 204:	80 c6 60 a6 	R3.H = R0.L << 0xc;
+ 208:	80 c6 70 b6 	R3.H = R0.H << 0xe;
+ 20c:	82 c6 e6 87 	R3=R6>>0x4;
+ 210:	82 c6 26 86 	R3=R6<<0x4;
+ 214:	83 c6 c8 41 	A0=A0>>0x7;
+ 218:	83 c6 38 51 	A1=A1>>0x19;
+ 21c:	83 c6 38 00 	A0=A0<<0x7;
+ 220:	83 c6 70 10 	A1=A1<<0xe;
+ 224:	43 40       	R3>>=R0;
+ 226:	8b 40       	R3<<=R1;
+ 228:	00 c6 10 86 	R3.L= LSHIFT R0.L BY R2.L;
+ 22c:	00 c6 10 a6 	R3.H= LSHIFT R0.L BY R2.L;
+ 230:	03 c6 38 40 	A0= LSHIFT A0 BY R7.L;
+ 234:	03 c6 38 50 	A1= LSHIFT A1 BY R7.L;
+ 238:	82 c6 f9 c8 	R4= ROT R1 BY 0x1f;
+ 23c:	82 c6 01 c9 	R4= ROT R1 BY -32;
+ 240:	82 c6 29 c8 	R4= ROT R1 BY 0x5;
+ 244:	83 c6 b0 80 	A0= ROT A0 BY 0x16;
+ 248:	83 c6 00 81 	A0= ROT A0 BY -32;
+ 24c:	83 c6 f8 80 	A0= ROT A0 BY 0x1f;
+ 250:	83 c6 00 91 	A1= ROT A1 BY -32;
+ 254:	83 c6 f8 90 	A1= ROT A1 BY 0x1f;
+ 258:	83 c6 b0 90 	A1= ROT A1 BY 0x16;
+ 25c:	02 c6 11 c8 	R4= ROT R1 BY R2.L;
+ 260:	03 c6 18 80 	A0= ROT A0 BY R3.L;
+ 264:	03 c6 38 90 	A1= ROT A1 BY R7.L;
+ 268:	80 c6 01 80 	R0.L = R1.L << 0x0;
+ 26c:	80 c6 09 80 	R0.L = R1.L << 0x1;
+ 270:	80 c6 11 80 	R0.L = R1.L << 0x2;
+ 274:	80 c6 21 80 	R0.L = R1.L << 0x4;
+ 278:	80 c6 01 80 	R0.L = R1.L << 0x0;
+ 27c:	80 c6 f9 81 	R0.L = R1.L >> 0x1;
+ 280:	80 c6 f1 81 	R0.L = R1.L >> 0x2;
+ 284:	80 c6 e1 81 	R0.L = R1.L >> 0x4;
+ 288:	80 c6 f9 01 	R0.L = R1.L >>> 0x1;
+ 28c:	80 c6 f1 01 	R0.L = R1.L >>> 0x2;
+ 290:	80 c6 e1 01 	R0.L = R1.L >>> 0x4;
+ 294:	80 c6 01 90 	R0.L = R1.H << 0x0;
+ 298:	80 c6 09 90 	R0.L = R1.H << 0x1;
+ 29c:	80 c6 11 90 	R0.L = R1.H << 0x2;
+ 2a0:	80 c6 21 90 	R0.L = R1.H << 0x4;
+ 2a4:	80 c6 01 90 	R0.L = R1.H << 0x0;
+ 2a8:	80 c6 f9 91 	R0.L = R1.H >> 0x1;
+ 2ac:	80 c6 f1 91 	R0.L = R1.H >> 0x2;
+ 2b0:	80 c6 e1 91 	R0.L = R1.H >> 0x4;
+ 2b4:	80 c6 f9 11 	R0.L = R1.H >>> 0x1;
+ 2b8:	80 c6 f1 11 	R0.L = R1.H >>> 0x2;
+ 2bc:	80 c6 e1 11 	R0.L = R1.H >>> 0x4;
+ 2c0:	80 c6 01 50 	R0.L = R1.H << 0x0 \(S\);
+ 2c4:	80 c6 09 50 	R0.L = R1.H << 0x1 \(S\);
+ 2c8:	80 c6 11 50 	R0.L = R1.H << 0x2 \(S\);
+ 2cc:	80 c6 21 50 	R0.L = R1.H << 0x4 \(S\);
+ 2d0:	80 c6 f9 51 	R0.L = R1.H >>> 0x1 \(S\);
+ 2d4:	80 c6 f1 51 	R0.L = R1.H >>> 0x2 \(S\);
+ 2d8:	80 c6 e1 51 	R0.L = R1.H >>> 0x4 \(S\);
diff --git a/gas/testsuite/gas/bfin/shift2.s b/gas/testsuite/gas/bfin/shift2.s
new file mode 100755
index 000000000000..69377bcd101e
--- /dev/null
+++ b/gas/testsuite/gas/bfin/shift2.s
@@ -0,0 +1,290 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//9 SHIFT/ROTATE OPERATIONS

+//

+

+//Preg = ( Preg + Preg ) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */

+P0 = (P0+P0)<<1;

+P0 = (P0+P1)<<1;

+P2 = (P2+P0)<<1;

+P1 = (P1+P2)<<1;

+

+//P0 = (P2+P0)<<1;

+

+//Preg = ( Preg + Preg ) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */

+P0 = (P0+P0)<<2;

+P0 = (P0+P1)<<2;

+P2 = (P2+P0)<<2;

+P1 = (P1+P2)<<2;

+

+//P0 = (P2+P0)<<2;

+

+//Dreg = (Dreg + Dreg) << 1 ; /* dest_reg = (dest_reg + src_reg) x 2 (a) */

+R0 = (R0+R0)<<1;

+R0 = (R0+R1)<<1;

+R2 = (R2+R0)<<1;

+R1 = (R1+R2)<<1;

+

+//R0 = (R2+R0)<<1;

+

+

+//Dreg = (Dreg + Dreg) << 2 ; /* dest_reg = (dest_reg + src_reg) x 4 (a) */

+R0 = (R0+R0)<<2;

+R0 = (R0+R1)<<2;

+R2 = (R2+R0)<<2;

+R1 = (R1+R2)<<2;

+

+//R0 = (R2+R0)<<2;

+

+//Preg = Preg + ( Preg << 1 ) ; /* adder_pntr + (src_pntr x 2) (a) */

+P0 = P0 + (P0 << 1);

+P0 = P0 + (P1 << 1);

+P0 = P0 + (P2 << 1);

+P0 = P1 + (P2 << 1);

+P0 = P2 + (P3 << 1);

+P1 = P0 + (P0 << 1);

+P1 = P0 + (P1 << 1);

+P1 = P0 + (P2 << 1);

+P1 = P1 + (P2 << 1);

+P1 = P2 + (P3 << 1);

+

+//Preg = Preg + ( Preg << 2 ) ; /* adder_pntr + (src_pntr x 4) (a) */

+P0 = P0 + (P0 << 2);

+P0 = P0 + (P1 << 2);

+P0 = P0 + (P2 << 2);

+P0 = P1 + (P2 << 2);

+P0 = P2 + (P3 << 2);

+P1 = P0 + (P0 << 2);

+P1 = P0 + (P1 << 2);

+P1 = P0 + (P2 << 2);

+P1 = P1 + (P2 << 2);

+P1 = P2 + (P3 << 2);

+

+//Dreg >>>= uimm5 ; /* arithmetic right shift (a) */

+R0 >>>= 0;

+R0 >>>= 31;

+R0 >>>= 5;

+R5 >>>= 0;

+R5 >>>= 31;

+R5 >>>= 5;

+

+//Dreg <<= uimm5 ; /* logical left shift (a) */

+R0 <<= 0;

+R0 <<= 31;

+R0 <<= 5;

+R5 <<= 0;

+R5 <<= 31;

+R5 <<= 5;

+//Dreg_lo_hi = Dreg_lo_hi >>> uimm4 ; /* arithmetic right shift (b) */

+R0.L = R0.L >>> 0;

+R0.L = R0.L >>> 15;

+R0.L = R0.H >>> 0;

+R0.L = R0.H >>> 15;

+R0.H = R0.L >>> 0;

+R0.H = R0.L >>> 15;

+R0.H = R0.H >>> 0;

+R0.H = R0.H >>> 15;

+

+R0.L = R1.L >>> 0;

+R0.L = R1.L >>> 15;

+R0.L = R1.H >>> 0;

+R0.L = R1.H >>> 15;

+R0.H = R1.L >>> 0;

+R0.H = R1.L >>> 15;

+R0.H = R1.H >>> 0;

+R0.H = R1.H >>> 15;

+

+R0.L = R7.L >>> 0;

+R1.L = R6.L >>> 15;

+R2.L = R5.H >>> 0;

+R3.L = R4.H >>> 15;

+R4.H = R3.L >>> 0;

+R5.H = R2.L >>> 15;

+R6.H = R1.H >>> 0;

+R7.H = R0.H >>> 15;

+

+//Dreg_lo_hi = Dreg_lo_hi << uimm4 (S) ; /* arithmetic left shift (b) */

+R0.L = R0.L << 0(S);

+R0.L = R0.L << 15(S);

+R0.L = R0.H << 0(S);

+R0.L = R0.H << 15(S);

+R0.H = R0.L << 0(S);

+R0.H = R0.L << 15(S);

+R0.H = R0.H << 0(S);

+R0.H = R0.H << 15(S);

+

+R0.L = R1.L << 0(S);

+R0.L = R1.L << 15(S);

+R0.L = R1.H << 0(S);

+R0.L = R1.H << 15(S);

+R0.H = R1.L << 0(S);

+R0.H = R1.L << 15(S);

+R0.H = R1.H << 0(S);

+R0.H = R1.H << 15(S);

+

+R0.L = R7.L << 0(S);

+R1.L = R6.L << 15(S);

+R2.L = R5.H << 0(S);

+R3.L = R4.H << 15(S);

+R4.H = R3.L << 0(S);

+R5.H = R2.L << 15(S);

+R6.H = R1.H << 0(S);

+R7.H = R0.H << 15(S);

+//Dreg = Dreg >>> uimm5 ; /* arithmetic right shift (b) */

+R0 = R0 >>> 0;

+R0 = R0 >>> 31;

+R0 = R1 >>> 0;

+R0 = R1 >>> 31;

+R7 = R0 >>> 0;

+R6 = R1 >>> 31;

+R5 = R2 >>> 0;

+R4 = R3 >>> 31;

+R3 = R4 >>> 0;

+R2 = R5 >>> 31;

+R1 = R6 >>> 0;

+R0 = R7 >>> 31;

+

+//Dreg = Dreg << uimm5 (S) ; /* arithmetic left shift (b) */

+R0 = R0 << 0(S);

+R0 = R0 << 31(S);

+R0 = R1 << 0(S);

+R0 = R1 << 31(S);

+R7 = R0 << 0(S);

+R6 = R1 << 31(S);

+R5 = R2 << 0(S);

+R4 = R3 << 31(S);

+R3 = R4 << 0(S);

+R2 = R5 << 31(S);

+R1 = R6 << 0(S);

+R0 = R7 << 31(S);

+//A0 = A0 >>> uimm5 ; /* arithmetic right shift (b) */

+A0 = A0 >>> 0;

+A0 = A0 >>> 15;

+A0 = A0 >>> 31;

+

+//A0 = A0 << uimm5 ; /* logical left shift (b) */

+A0 = A0 << 0;

+A0 = A0 << 15;

+A0 = A0 << 31;

+

+//A1 = A1 >>> uimm5 ; /* arithmetic right shift (b) */

+A1 = A1 >>> 0;

+A1 = A1 >>> 15;

+A1 = A1 >>> 31;

+

+//A1 = A1 << uimm5 ; /* logical left shift (b) */

+A1 = A1 << 0;

+A1 = A1 << 15;

+A1 = A1 << 31;

+

+//Dreg >>>= Dreg ; /* arithmetic right shift (a) */

+R0 >>>= R0;

+R0 >>>= R1;

+R1 >>>= R0;

+R1 >>>= R7;

+

+//Dreg <<= Dreg ; /* logical left shift (a) */

+R0 <<= R0;

+R0 <<= R1;

+R1 <<= R0;

+R1 <<= R7;

+

+//Dreg_lo_hi = ASHIFT Dreg_lo_hi BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */

+r3.l = ashift r0.h by r7.l ; /* shift, half-word */

+r3.h = ashift r0.l by r7.l ;

+r3.h = ashift r0.h by r7.l ;

+r3.l = ashift r0.l by r7.l ;

+r3.l = ashift r0.h by r7.l(s) ; /* shift, half-word, saturated */

+r3.h = ashift r0.l by r7.l(s) ; /* shift, half-word, saturated */

+r3.h = ashift r0.h by r7.l(s) ;

+r3.l = ashift r0.l by r7.l (s) ;

+

+//Dreg = ASHIFT Dreg BY Dreg_lo (opt_sat) ; /* arithmetic right shift (b) */

+r4 = ashift r2 by r7.l ; /* shift, word */

+r4 = ashift r2 by r7.l (s) ; /* shift, word, saturated */

+

+//A0 = ASHIFT A0 BY Dreg_lo ; /* arithmetic right shift (b)*/

+A0 = ashift A0 by r7.l ; /* shift, Accumulator */

+

+//A1 = ASHIFT A1 BY Dreg_lo ; /* arithmetic right shift (b)*/

+A1 = ashift A1 by r7.l ; /* shift, Accumulator */

+

+p3 = p2 >> 1 ; /* pointer right shift by 1 */

+p3 = p3 >> 2 ; /* pointer right shift by 2 */

+p4 = p5 << 1 ; /* pointer left shift by 1 */

+p0 = p1 << 2 ; /* pointer left shift by 2 */

+r3 >>= 17 ; /* data right shift */

+r3 <<= 17 ; /* data left shift */

+r3.l = r0.l >> 4 ; /* data right shift, half-word register */

+r3.l = r0.h >> 4 ; /* same as above; half-word register combinations are arbitrary */

+r3.h = r0.l << 12 ; /* data left shift, half-word register */

+r3.h = r0.h << 14 ; /* same as above; half-word register combinations are arbitrary */

+

+r3 = r6 >> 4 ; /* right shift, 32-bit word */

+r3 = r6 << 4 ; /* left shift, 32-bit word */

+

+a0 = a0 >> 7 ; /* Accumulator right shift */

+a1 = a1 >> 25 ; /* Accumulator right shift */

+a0 = a0 << 7 ; /* Accumulator left shift */

+a1 = a1 << 14 ; /* Accumulator left shift */

+

+r3 >>= r0 ; /* data right shift */

+r3 <<= r1 ; /* data left shift */

+

+r3.l = lshift r0.l by r2.l ; /* shift direction controlled by sign of R2.L */

+r3.h = lshift r0.l by r2.l ;

+

+a0 = lshift a0 by r7.l ;

+a1 = lshift a1 by r7.l ;

+

+r4 = rot r1 by 31 ; /* rotate left */

+r4 = rot r1 by -32 ; /* rotate right */

+r4 = rot r1 by 5 ; /* rotate right */

+

+a0 = rot a0 by 22 ; /* rotate Accumulator left */

+a0 = rot a0 by -32 ; /* rotate Accumulator left */

+a0 = rot a0 by 31 ; /* rotate Accumulator left */

+

+a1 = rot a1 by -32 ; /* rotate Accumulator right */

+a1 = rot a1 by 31 ; /* rotate Accumulator right */

+a1 = rot a1 by 22 ; /* rotate Accumulator right */

+

+r4 = rot r1 by r2.l ;

+a0 = rot a0 by r3.l ;

+a1 = rot a1 by r7.l ;

+

+r0.l = r1.l << 0;

+r0.l = r1.l << 1;

+r0.l = r1.l << 2;

+r0.l = r1.l << 4;

+r0.l = r1.l >> 0;

+r0.l = r1.l >> 1;

+r0.l = r1.l >> 2;

+r0.l = r1.l >> 4;

+r0.l = r1.l >>> 1;

+r0.l = r1.l >>> 2;

+r0.l = r1.l >>> 4;

+

+r0.l = r1.h << 0;

+r0.l = r1.h << 1;

+r0.l = r1.h << 2;

+r0.l = r1.h << 4;

+r0.l = r1.h >> 0;

+r0.l = r1.h >> 1;

+r0.l = r1.h >> 2;

+r0.l = r1.h >> 4;

+r0.l = r1.h >>> 1;

+r0.l = r1.h >>> 2;

+r0.l = r1.h >>> 4;

+

+r0.l = r1.h << 0 (S);

+r0.l = r1.h << 1 (S);

+r0.l = r1.h << 2 (S);

+r0.l = r1.h << 4 (S);

+r0.l = r1.h >>> 1 (S);

+r0.l = r1.h >>> 2 (S);

+r0.l = r1.h >>> 4 (S);

+

diff --git a/gas/testsuite/gas/bfin/stack.d b/gas/testsuite/gas/bfin/stack.d
new file mode 100644
index 000000000000..fd06754801a2
--- /dev/null
+++ b/gas/testsuite/gas/bfin/stack.d
@@ -0,0 +1,42 @@
+#objdump: -dr
+#name: stack
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <push>:
+   0:	7a 01       	\[--SP\] = SYSCFG;
+   2:	70 01       	\[--SP\] = LC0;
+   4:	47 01       	\[--SP\] = R7;
+   6:	61 01       	\[--SP\] = A0.w;
+   8:	76 01       	\[--SP\] = CYCLES;
+   a:	5a 01       	\[--SP\] = B2;
+   c:	55 01       	\[--SP\] = M1;
+   e:	48 01       	\[--SP\] = P0;
+
+00000010 <push_multiple>:
+  10:	d0 05       	\[--SP\] = \(R7:2, P5:0\);
+  12:	70 05       	\[--SP\] = \(R7:6\);
+  14:	c2 04       	\[--SP\] = \(P5:2\);
+
+00000016 <pop>:
+  16:	38 01       	USP = \[SP\+\+\];
+  18:	3b 01       	RETI = \[SP\+\+\];
+  1a:	10 01       	I0 = \[SP\+\+\];
+  1c:	39 01       	SEQSTAT = \[SP\+\+\];
+  1e:	1e 01       	L2 = \[SP\+\+\];
+  20:	35 90       	R5=\[SP\+\+\];
+  22:	77 90       	FP=\[SP\+\+\];
+
+00000024 <pop_multiple>:
+  24:	a8 05       	\(R7:5, P5:0\) = \[SP\+\+\];
+  26:	30 05       	\(R7:6\) = \[SP\+\+\];
+  28:	84 04       	\(P5:4\) = \[SP\+\+\];
+
+0000002a <link>:
+  2a:	00 e8 02 00 	LINK 0x8;
+  2e:	00 e8 ff ff 	LINK 0x3fffc;
+  32:	00 e8 01 80 	LINK 0x20004;
+
+00000036 <unlink>:
+  36:	01 e8 00 00 	UNLINK;
+	...
diff --git a/gas/testsuite/gas/bfin/stack.s b/gas/testsuite/gas/bfin/stack.s
new file mode 100644
index 000000000000..9826beff1b0a
--- /dev/null
+++ b/gas/testsuite/gas/bfin/stack.s
@@ -0,0 +1,49 @@
+	.text
+	.global push
+push:
+	[--Sp] = syscfg;
+	[--SP] = Lc0;
+	[--sp] = R7;
+	[--sp] = A0.W;
+	[--sP] = Cycles;
+	[--Sp] = b2;
+	[--sp] = m1;
+	[--SP] = P0;
+
+	.text
+	.global push_multiple
+push_multiple:
+	[--sp] = (r7:2, p5:0);
+	[--SP] = (R7:6);
+	[--Sp] = (p5:2);
+
+	.text
+	.global pop
+pop:
+	usp = [ Sp++];
+	Reti = [sp++];
+	i0 = [sp++];
+	Seqstat = [sp++];
+	L2 = [sp++];
+	R5 = [SP ++ ];
+	Fp = [Sp ++];
+
+	.text
+	.global pop_multiple
+pop_multiple:
+	(R7:5, P5:0) = [sp++];
+	(r7:6) = [SP++];
+	(P5:4) = [Sp++];
+
+	.text
+	.global link
+link:
+	link 8;
+	link 0x3fffc;
+	link 0x20004;
+
+	.text
+	.global unlink
+unlink:
+	unlink;
+	
diff --git a/gas/testsuite/gas/bfin/stack2.d b/gas/testsuite/gas/bfin/stack2.d
new file mode 100644
index 000000000000..42a4b6d64067
--- /dev/null
+++ b/gas/testsuite/gas/bfin/stack2.d
@@ -0,0 +1,83 @@
+#objdump: -dr
+#name: stack2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	40 01       	\[--SP\] = R0;
+   2:	46 01       	\[--SP\] = R6;
+   4:	48 01       	\[--SP\] = P0;
+   6:	4c 01       	\[--SP\] = P4;
+   8:	50 01       	\[--SP\] = I0;
+   a:	51 01       	\[--SP\] = I1;
+   c:	54 01       	\[--SP\] = M0;
+   e:	55 01       	\[--SP\] = M1;
+  10:	5c 01       	\[--SP\] = L0;
+  12:	5d 01       	\[--SP\] = L1;
+  14:	58 01       	\[--SP\] = B0;
+  16:	59 01       	\[--SP\] = B1;
+  18:	60 01       	\[--SP\] = A0.x;
+  1a:	62 01       	\[--SP\] = A1.x;
+  1c:	61 01       	\[--SP\] = A0.w;
+  1e:	63 01       	\[--SP\] = A1.w;
+  20:	66 01       	\[--SP\] = ASTAT;
+  22:	67 01       	\[--SP\] = RETS;
+  24:	7b 01       	\[--SP\] = RETI;
+  26:	7c 01       	\[--SP\] = RETX;
+  28:	7d 01       	\[--SP\] = RETN;
+  2a:	7e 01       	\[--SP\] = RETE;
+  2c:	70 01       	\[--SP\] = LC0;
+  2e:	73 01       	\[--SP\] = LC1;
+  30:	71 01       	\[--SP\] = LT0;
+  32:	74 01       	\[--SP\] = LT1;
+  34:	72 01       	\[--SP\] = LB0;
+  36:	75 01       	\[--SP\] = LB1;
+  38:	76 01       	\[--SP\] = CYCLES;
+  3a:	77 01       	\[--SP\] = CYCLES2;
+  3c:	78 01       	\[--SP\] = USP;
+  3e:	79 01       	\[--SP\] = SEQSTAT;
+  40:	7a 01       	\[--SP\] = SYSCFG;
+  42:	c0 05       	\[--SP\] = \(R7:0, P5:0\);
+  44:	40 05       	\[--SP\] = \(R7:0\);
+  46:	c0 04       	\[--SP\] = \(P5:0\);
+  48:	30 90       	R0=\[SP\+\+\];
+  4a:	36 90       	R6=\[SP\+\+\];
+  4c:	70 90       	P0=\[SP\+\+\];
+  4e:	74 90       	P4=\[SP\+\+\];
+  50:	10 01       	I0 = \[SP\+\+\];
+  52:	11 01       	I1 = \[SP\+\+\];
+  54:	14 01       	M0 = \[SP\+\+\];
+  56:	15 01       	M1 = \[SP\+\+\];
+  58:	1c 01       	L0 = \[SP\+\+\];
+  5a:	1d 01       	L1 = \[SP\+\+\];
+  5c:	18 01       	B0 = \[SP\+\+\];
+  5e:	19 01       	B1 = \[SP\+\+\];
+  60:	20 01       	A0.x = \[SP\+\+\];
+  62:	22 01       	A1.x = \[SP\+\+\];
+  64:	21 01       	A0.w = \[SP\+\+\];
+  66:	23 01       	A1.w = \[SP\+\+\];
+  68:	26 01       	ASTAT = \[SP\+\+\];
+  6a:	27 01       	RETS = \[SP\+\+\];
+  6c:	3b 01       	RETI = \[SP\+\+\];
+  6e:	3c 01       	RETX = \[SP\+\+\];
+  70:	3d 01       	RETN = \[SP\+\+\];
+  72:	3e 01       	RETE = \[SP\+\+\];
+  74:	30 01       	LC0 = \[SP\+\+\];
+  76:	33 01       	LC1 = \[SP\+\+\];
+  78:	31 01       	LT0 = \[SP\+\+\];
+  7a:	34 01       	LT1 = \[SP\+\+\];
+  7c:	32 01       	LB0 = \[SP\+\+\];
+  7e:	35 01       	LB1 = \[SP\+\+\];
+  80:	36 01       	CYCLES = \[SP\+\+\];
+  82:	37 01       	CYCLES2 = \[SP\+\+\];
+  84:	38 01       	USP = \[SP\+\+\];
+  86:	39 01       	SEQSTAT = \[SP\+\+\];
+  88:	3a 01       	SYSCFG = \[SP\+\+\];
+  8a:	80 05       	\(R7:0, P5:0\) = \[SP\+\+\];
+  8c:	00 05       	\(R7:0\) = \[SP\+\+\];
+  8e:	80 04       	\(P5:0\) = \[SP\+\+\];
+  90:	00 e8 00 00 	LINK 0x0;
+  94:	00 e8 02 00 	LINK 0x8;
+  98:	00 e8 ff ff 	LINK 0x3fffc;
+  9c:	01 e8 00 00 	UNLINK;
diff --git a/gas/testsuite/gas/bfin/stack2.s b/gas/testsuite/gas/bfin/stack2.s
new file mode 100755
index 000000000000..5d7f2c233342
--- /dev/null
+++ b/gas/testsuite/gas/bfin/stack2.s
@@ -0,0 +1,125 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//5 STACK CONTROL

+//

+

+//[ -- SP ] = allreg ; /* predecrement SP (a) */

+

+[--SP ] =  R0;

+[--SP ] =  R6;

+

+[--SP ] =  P0;

+[--SP ] =  P4;

+

+[--SP ] =  I0;

+[--SP ] =  I1;

+

+[--SP ] =  M0;

+[--SP ] =  M1;

+

+[--SP ] =  L0;

+[--SP ] =  L1;

+

+[--SP ] =  B0;

+[--SP ] =  B1;

+

+[--SP ] =  A0.X;

+[--SP ] =  A1.X;

+

+[--SP ] =  A0.W;

+[--SP ] =  A1.W;

+

+[--SP ] =  ASTAT;

+[--SP ] =  RETS;

+[--SP ] =  RETI;

+[--SP ] =  RETX;

+[--SP ] =  RETN;

+[--SP ] =  RETE;

+[--SP ] =  LC0;

+[--SP ] =  LC1;

+[--SP ] =  LT0;

+[--SP ] =  LT1;

+[--SP ] =  LB0;

+[--SP ] =  LB1;

+[--SP ] =  CYCLES;

+[--SP ] =  CYCLES2;

+//[--SP ] =  EMUDAT;

+[--SP ] =  USP;

+[--SP ] =  SEQSTAT;

+[--SP ] =  SYSCFG;

+

+

+//[ -- SP ] = ( R7 : Dreglim , P5 : Preglim ) ; /* Dregs and indexed Pregs (a) */

+[--SP ] = ( R7:0, P5:0);

+

+

+//[ -- SP ] = ( R7 : Dreglim ) ; /* Dregs, only (a) */

+[--SP ] = ( R7:0);

+

+//[ -- SP ] = ( P5 : Preglim ) ; /* indexed Pregs, only (a) */

+[--SP ] = (P5:0);

+

+

+//mostreg = [ SP ++ ] ; /* post-increment SP; does not apply to Data Registers and Pointer Registers (a) */

+

+R0= [ SP ++ ] ;      

+R6= [ SP ++ ] ;      

+         

+P0= [ SP ++ ] ;      

+P4= [ SP ++ ] ;      

+         

+I0= [ SP ++ ] ;      

+I1= [ SP ++ ] ;      

+         

+M0= [ SP ++ ] ;      

+M1= [ SP ++ ] ;      

+         

+L0= [ SP ++ ] ;      

+L1= [ SP ++ ] ;      

+         

+B0= [ SP ++ ] ;      

+B1= [ SP ++ ] ;      

+         

+A0.X= [ SP ++ ] ;    

+A1.X= [ SP ++ ] ;    

+         

+A0.W= [ SP ++ ] ;    

+A1.W= [ SP ++ ] ;    

+         

+ASTAT= [ SP ++ ] ;   

+RETS= [ SP ++ ] ;    

+RETI= [ SP ++ ] ;    

+RETX= [ SP ++ ] ;    

+RETN= [ SP ++ ] ;    

+RETE= [ SP ++ ] ;    

+LC0= [ SP ++ ] ;     

+LC1= [ SP ++ ] ;     

+LT0= [ SP ++ ] ;     

+LT1= [ SP ++ ] ;     

+LB0= [ SP ++ ] ;     

+LB1= [ SP ++ ] ;     

+CYCLES= [ SP ++ ] ;  

+CYCLES2= [ SP ++ ] ; 

+//EMUDAT= [ SP ++ ] ;  

+USP= [ SP ++ ] ;     

+SEQSTAT= [ SP ++ ] ; 

+SYSCFG= [ SP ++ ] ;  

+

+//( R7 : Dreglim, P5 : Preglim ) = [ SP ++ ] ; /* Dregs and indexed Pregs (a) */

+( R7:0, P5:0) = [ SP++ ];

+

+//( R7 : Dreglim ) = [ SP ++ ] ; /* Dregs, only (a) */

+( R7:0) = [ SP++ ];

+

+//( P5 : Preglim ) = [ SP ++ ] ; /* indexed Pregs, only (a) */

+( P5:0) = [ SP++ ];

+

+//LINK uimm18m4 ; /* allocate a stack frame of specified size (b) */

+LINK 0X0;

+LINK 0X8;

+LINK 0x3FFFC;

+

+UNLINK ; /* de-allocate the stack frame (b)*/

diff --git a/gas/testsuite/gas/bfin/store.d b/gas/testsuite/gas/bfin/store.d
new file mode 100644
index 000000000000..0e553c17ca94
--- /dev/null
+++ b/gas/testsuite/gas/bfin/store.d
@@ -0,0 +1,55 @@
+#objdump: -dr
+#name: store
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <store_pointer_register>:
+   0:	78 93       	\[FP\]=P0;
+   2:	71 92       	\[SP\+\+\]=P1;
+   4:	fd 92       	\[FP--\]=P5;
+   6:	d6 bf       	\[P2\+0x3c\]=SP;
+   8:	28 e7 ff 7f 	\[P5\+0x1fffc\]=P0;
+   c:	3a bc       	\[FP\+0x0\]=P2;
+   e:	f9 bb       	\[FP-4\]=P1;
+  10:	08 ba       	\[FP-128\]=P0;
+
+00000012 <store_data_register>:
+  12:	10 93       	\[P2\]=R0;
+  14:	2a 92       	\[P5\+\+\]=R2;
+  16:	bf 92       	\[FP--\]=R7;
+  18:	b5 b3       	\[SP\+0x38\]=R5;
+  1a:	33 e6 fc 3b 	\[SP\+0xeff0\]=R3;
+  1e:	38 e6 01 c0 	\[FP\+-65532\]=R0;
+  22:	4f 88       	\[FP\+\+P1\]=R1;
+  24:	86 ba       	\[FP-96\]=R6;
+  26:	01 9f       	\[I0\]=R1;
+  28:	12 9e       	\[I2\+\+\]=R2;
+  2a:	9c 9e       	\[I3--\]=R4;
+  2c:	8f 9f       	\[I1\+\+M0\]=R7;
+
+0000002e <store_data_register_half>:
+  2e:	5c 9f       	W\[I3\]=R4.H;
+  30:	40 9e       	W\[I0\+\+\]=R0.H;
+  32:	d7 9e       	W\[I2--\]=R7.H;
+  34:	b6 8d       	W\[SP\]=R6.H;
+  36:	07 8d       	W\[FP\+\+P0\]=R4.H;
+
+00000038 <store_low_data_register_half>:
+  38:	20 9f       	W\[I0\]=R0.L;
+  3a:	2f 9e       	W\[I1\+\+\]=R7.L;
+  3c:	b1 9e       	W\[I2--\]=R1.L;
+  3e:	b6 8a       	W\[SP\]=R2.L;
+  40:	13 97       	W\[P2\]=R3;
+  42:	1d 96       	W\[P3\+\+\]=R5;
+  44:	bc 96       	W\[FP--\]=R4;
+  46:	cf b7       	W\[P1\+0x1e\]=R7;
+  48:	56 e6 ff 7f 	W\[P2\+0xfffe\]=R6;
+  4c:	79 e6 98 a1 	W\[FP\+-48336\]=R1;
+  50:	56 8b       	W\[SP\+\+P2\]=R5.L;
+
+00000052 <store_byte>:
+  52:	39 9b       	B\[FP\]=R1;
+  54:	00 9a       	B\[P0\+\+\]=R0;
+  56:	ba 9a       	B\[FP--\]=R2;
+  58:	97 e6 19 00 	B\[P2\+0x19\]=R7;
+  5c:	be e6 01 80 	B\[FP\+-32767\]=R6;
diff --git a/gas/testsuite/gas/bfin/store.s b/gas/testsuite/gas/bfin/store.s
new file mode 100644
index 000000000000..05abe8eb5a34
--- /dev/null
+++ b/gas/testsuite/gas/bfin/store.s
@@ -0,0 +1,61 @@
+	.text
+	.global store_pointer_register
+store_pointer_register:
+	[FP] = P0;
+	[Sp ++] = p1;
+	[fp --] = P5;
+	[p2 + 60] = Sp;
+	[P5 + 131068] = P0;
+	[Fp -0]= p2;
+	[fp -4] = P1;
+	[Fp - 128] = p0;
+
+	.text
+	.global store_data_register
+store_data_register:
+	[p2] = r0;
+	[P5 ++] = R2;
+	[fp--] = R7;
+	[SP + 56] = R5;
+	[sp+0xeff0]=R3;
+	[FP - 0xfffc] = R0;
+	[fp ++ P1] = r1;
+	[FP - 96] = r6;
+
+	[i0] = r1;
+	[I2++] = R2;
+	[i3--] = R4;	
+	[i1 ++ m0] = r7;
+
+	.text
+	.global store_data_register_half
+store_data_register_half:
+	w [ i3] = R4.h;
+	W[I0++] = r0.h;
+	W [ i2--] = r7.H;
+	w[Sp] = R6.h;
+	W [ Fp++P0] = r4.h;
+
+	.text
+	.global store_low_data_register_half
+store_low_data_register_half:
+	W [I0] = r0.l;
+	w [i1++] = r7.L;
+	W[I2--] = R1.l;
+	w [SP] = r2.l;
+	W[P2] = r3;
+	w [p3 ++ ] = R5;
+	W [fp--] = R4;
+	W [P1+30]=r7;
+	w[p2+0xfffe] = R6;
+	w [FP-0xbcd0] = r1;
+	W [sp ++ P2] = r5.L;
+
+	.text
+	.global store_byte
+store_byte:
+	b [Fp] = R1;
+	B[P0++] = r0;
+	B [fp --] = r2;
+	B [ p2 + 25] = R7;
+	b[FP - 0x7FFF] = r6;
diff --git a/gas/testsuite/gas/bfin/vector.d b/gas/testsuite/gas/bfin/vector.d
new file mode 100644
index 000000000000..fd8bd0a3d597
--- /dev/null
+++ b/gas/testsuite/gas/bfin/vector.d
@@ -0,0 +1,105 @@
+#objdump: -dr
+#name: vector
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <add_on_sign>:
+   0:	0c c4 0d 08 	R4.H=R4.L=SIGN\(R1.H\)\*R5.H\+SIGN\(R1.L\)\*R5.L\);
+
+00000004 <vit_max>:
+   4:	09 c6 15 8e 	R7=VIT_MAX\(R5,R2\)\(ASL\);
+   8:	09 c6 30 c0 	R0=VIT_MAX\(R0,R6\)\(ASR\);
+   c:	09 c6 03 0a 	R5.L=VIT_MAX \(R3\) \(ASL\);
+  10:	09 c6 02 44 	R2.L=VIT_MAX \(R2\) \(ASR\);
+
+00000014 <vector_abs>:
+  14:	06 c4 28 8a 	R5= ABS R5\(V\);
+  18:	06 c4 00 84 	R2= ABS R0\(V\);
+
+0000001c <vector_add_sub>:
+  1c:	00 c4 1a 0a 	R5=R3\+\|\+R2 ;
+  20:	00 c4 1a 3a 	R5=R3\+\|\+R2 \(SCO\);
+  24:	00 c4 06 8e 	R7=R0-\|\+R6 ;
+  28:	00 c4 0b a4 	R2=R1-\|\+R3 \(S\);
+  2c:	00 c4 02 48 	R4=R0\+\|-R2 ;
+  30:	00 c4 0a 5a 	R5=R1\+\|-R2 \(CO\);
+  34:	00 c4 1c cc 	R6=R3-\|-R4 ;
+  38:	00 c4 2e de 	R7=R5-\|-R6 \(CO\);
+  3c:	01 c4 63 bf 	R5=R4\+\|\+R3,R7=R4-\|-R3\(SCO,ASR\);
+  40:	01 c4 1e c2 	R0=R3\+\|\+R6,R1=R3-\|-R6\(ASL\);
+  44:	21 c4 ca 2d 	R7=R1\+\|-R2,R6=R1-\|\+R2\(S\);
+  48:	21 c4 53 0a 	R1=R2\+\|-R3,R5=R2-\|\+R3;
+  4c:	04 c4 41 8d 	R5=R0\+R1,R6=R0-R1 \(NS\);
+  50:	04 c4 39 a6 	R0=R7\+R1,R3=R7-R1 \(S\);
+  54:	11 c4 [c-f][[:xdigit:]] 0b 	R7=A1\+A0,R5=A1-A0 \(NS\);
+  58:	11 c4 [c-f][[:xdigit:]] 6c 	R3=A0\+A1,R6=A0-A1 \(S\);
+
+0000005c <vector_ashift>:
+  5c:	81 c6 8b 03 	R1=R3>>>0xf \(V\);
+  60:	81 c6 e0 09 	R4=R0>>>0x4 \(V\);
+  64:	81 c6 00 4a 	R5=R0<<0x0 \(V, S\);
+  68:	81 c6 62 44 	R2=R2<<0xc \(V, S\);
+  6c:	01 c6 15 0e 	R7= ASHIFT R5 BY R2.L\(V\);
+  70:	01 c6 02 40 	R0= ASHIFT R2 BY R0.L\(V,S\);
+
+00000074 <vector_lshift>:
+  74:	81 c6 8a 8b 	R5=R2 >> 0xf \(V\);
+  78:	81 c6 11 80 	R0=R1<<0x2 \(V\);
+  7c:	01 c6 11 88 	R4=SHIFT R1 BY R2.L\(V\);
+
+00000080 <vector_max>:
+  80:	06 c4 01 0c 	R6=MAX\(R0,R1\)\(V\);
+
+00000084 <vector_min>:
+  84:	06 c4 17 40 	R0=MIN\(R2,R7\)\(V\);
+
+00000088 <vector_mul>:
+  88:	04 c2 be 66 	R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H;
+  8c:	04 c2 08 e1 	R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L;
+  90:	04 c2 1a a0 	R0.H = R3.H \* R2.L, R0 = R3.L \* R2.L;
+  94:	94 c2 5a e1 	R5.H = R3.H \* R2.H \(M\), R5 = R3.L \* R2.L \(FU\);
+  98:	2c c2 27 e0 	R1 = R4.H \* R7.H, R0 = R4.L \* R7.L \(S2RND\);
+  9c:	0c c2 95 27 	R7 = R2.L \* R5.L, R6 = R2.H \* R5.H;
+  a0:	24 c3 3e e0 	R0.H = R7.H \* R6.H, R0 = R7.L \* R6.L \(ISS2\);
+  a4:	04 c3 c1 e0 	R3.H = R0.H \* R1.H, R3 = R0.L \* R1.L \(IS\);
+  a8:	00 c0 13 46 	a1 = R2.L \* R3.H, a0 = R2.H \* R3.H;
+  ac:	01 c0 08 c0 	a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L;
+  b0:	60 c0 2f c8 	a1 = R5.H \* R7.H, a0 \+= R5.L \* R7.L \(W32\);
+  b4:	01 c1 01 c0 	a1 \+= R0.H \* R1.H, a0 = R0.L \* R1.L \(IS\);
+  b8:	90 c0 1c c8 	a1 = R3.H \* R4.H \(M\), a0 \+= R3.L \* R4.L \(FU\);
+  bc:	01 c0 24 96 	a1 \+= R4.H \* R4.L, a0 -= R4.H \* R4.H;
+  c0:	25 c1 3e e8 	R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\);
+  c4:	27 c0 81 28 	R2.H = A1, R2.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\);
+  c8:	04 c0 d1 c9 	R7.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L;
+  cc:	04 c0 be 66 	R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\);
+  d0:	05 c0 9a e1 	R6.H = \(a1 \+= R3.H \* R2.H\), R6.L = \(a0 = R3.L \* R2.L\);
+  d4:	05 c0 f5 a7 	R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\);
+  d8:	14 c0 3c a8 	R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\);
+  dc:	94 c0 5a e9 	R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\);
+  e0:	05 c1 1a e0 	R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\);
+  e4:	1c c0 b7 d0 	R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L;
+  e8:	1c c0 3c 2e 	R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\);
+  ec:	2d c1 3e e8 	R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\);
+  f0:	0d c0 37 e1 	R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\);
+  f4:	0d c0 9d f1 	R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\);
+  f8:	0e c0 37 c9 	R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L;
+  fc:	0c c0 b7 e0 	R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\);
+ 100:	9c c0 1f e9 	R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\);
+ 104:	2f c0 81 28 	R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\);
+ 108:	0d c1 1a e0 	R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\);
+
+0000010c <vector_negate>:
+ 10c:	0f c4 08 c0 	R0=-R1\(V\);
+ 110:	0f c4 10 ce 	R7=-R2\(V\);
+
+00000114 <vector_pack>:
+ 114:	04 c6 08 8e 	R7=PACK\(R0.H,R1.L\);
+ 118:	04 c6 31 cc 	R6=PACK\(R1.H,R6.H\);
+ 11c:	04 c6 12 4a 	R5=PACK\(R2.L,R2.H\);
+
+00000120 <vector_search>:
+ 120:	0d c4 10 82 	\(R0,R1\) = SEARCH R2\(LT\);
+ 124:	0d c4 80 cf 	\(R6,R7\) = SEARCH R0\(LE\);
+ 128:	0d c4 c8 0c 	\(R3,R6\) = SEARCH R1\(GT\);
+ 12c:	0d c4 18 4b 	\(R4,R5\) = SEARCH R3\(GE\);
diff --git a/gas/testsuite/gas/bfin/vector.s b/gas/testsuite/gas/bfin/vector.s
new file mode 100644
index 000000000000..670869a69297
--- /dev/null
+++ b/gas/testsuite/gas/bfin/vector.s
@@ -0,0 +1,131 @@
+	.text
+	.global add_on_sign
+add_on_sign:
+	r4.h = r4.l = Sign (R1.h) * R5.h + Sign(r1.L) * R5.L;
+
+	.text
+	.global vit_max
+vit_max:
+	R7 = Vit_Max (R5, r2) (ASL);
+	r0 = VIT_MAX (r0, r6) (asr);
+	r5.l = vit_max (R3) (asL);
+	r2.L = VIT_Max (r2) (Asr);
+
+	.text
+	.global vector_abs
+vector_abs:
+	R5 = ABS R5 (V);
+	r2 = abs r0 (v);
+
+	.text
+	.global vector_add_sub
+vector_add_sub:
+	R5 = r3 +|+ R2;
+	r5 = r3 +|+ r2 (Sco);
+	r7 = R0 -|+ r6;
+	r2 = R1 -|+ R3 (S);
+	R4 = R0 +|- R2;
+	R5 = r1 +|- r2 (CO);
+	r6 = r3 -|- R4;
+	r7 = R5 -|- R6 (co);
+
+	r5 = r4 +|+ r3, R7 = r4 -|- r3 (Sco, ASR);
+	R0 = R3 +|+ r6, R1 = R3 -|- R6 (ASL);
+	R7 = R1 +|- R2, R6 = R1 -|+ R2 (S);
+	r1 = r2 +|- r3, r5 = r2 -|+ r3;
+
+	R5 = R0 + R1, R6 = R0 - R1;
+	r0 = r7 + r1, r3 = r7 - r1 (s);
+
+	r7 = A1 + A0, r5 = A1 - A0;
+	r3 = a0 + a1, r6 = a0 - a1 (s);
+
+	.text
+	.global vector_ashift
+vector_ashift:
+	R1 = R3 >>> 15 (V);
+	r4 = r0 >>> 4 (v);
+	r5 = r0 << 0 (v,s);
+	r2 = r2 << 12 (v, S);
+
+	R7 = ASHIFT R5 BY R2.L (V);
+	r0 = Ashift r2 by r0.L (v, s);
+
+	.text
+	.global vector_lshift
+vector_lshift:
+	R5 = r2 >> 15 (V);
+	r0 = R1 << 2 (v);
+
+	R4 = lshift r1 by r2.L (v);
+
+	.text
+	.global vector_max
+vector_max:
+	R6 = MAX (R0, R1) (V);
+
+	.text
+	.global vector_min
+vector_min:
+	r0 = min (r2, r7) (v);
+
+	.text
+	.global vector_mul
+vector_mul:
+	r2.h = r7.l * r6.h, r2.l = r7.h * r6.h;
+	R4.L = R1.L * R0.L, R4.H = R1.H * R0.H;
+	R0.h = R3.H * r2.l, r0.l=r3.l * r2.l;
+	r5.h = r3.h * r2.h (M), r5.l = r3.L * r2.L (fu);
+	R0 = r4.l * r7.l, r1 = r4.h * r7.h (s2rnd);
+	R7 = R2.l * r5.l, r6 = r2.h * r5.h;
+	R0.L = R7.L * R6.L, R0.H = R7.H * R6.H (ISS2);
+	r3.h = r0.h * r1.h, r3.l = r0.l * r1.l (is);
+
+	a1 = r2.l * r3.h, a0 = r2.h * R3.H;
+	A0 = R1.l * R0.L, A1 += R1.h * R0.h;
+	A1 = R5.h * R7.H, A0 += r5.L * r7.l (w32);
+	a1 += r0.H * r1.H, A0 = R0.L * R1.l (is);
+	a1 = r3.h * r4.h (m), a0 += r3.l * R4.L (FU);
+	A1 += r4.H * R4.L, a0 -= r4.h * r4.h;
+
+	r0.l = (a0 += R7.l * R6.L), R0.H = (A1 += R7.H * R6.H) (Iss2);
+	r2.H = A1, r2.l = (a0 += r0.L * r1.L) (s2rnd);
+	r7.h = (a1 = r2.h * r1.h), a0 += r2.l * r1.l;
+	R2.H = (A1 = R7.L * R6.H), R2.L = (A0 = R7.H * R6.h);
+	r6.L = (A0 = R3.L * r2.L), R6.H = (A1 += R3.H * R2.H);
+	R7.h = (a1 += r6.h * r5.l), r7.l = (a0=r6.h * r5.h);
+	r0.h = (A1 = r7.h * R4.l) (M), R0.l = (a0 += r7.l * r4.l);
+	R5.H = (a1 = r3.h * r2.h) (m), r5.l= (a0 += r3.l * r2.l) (fu);
+	r0.h = (A1 += R3.h * R2.h), R0.L = ( A0 = R3.L * R2.L) (is);
+
+	R3 = (A1 = R6.H * R7.H) (M), A0 -= R6.L * R7.L;
+	r1 = (a1 = r7.l * r4.l) (m), r0 = (a0 += r7.h * r4.h);
+	R0 = (a0 += r7.l * r6.l), r1 = (a1+= r7.h * r6.h) (ISS2);
+	r4 = (a0 = r6.l * r7.l), r5 = (a1 += r6.h * r7.h);
+	R7 = (A1 += r3.h * r5.H), R6 = (A0 -= r3.l * r5.l);
+	r5 = (a1 -= r6.h * r7.h), a0 += r6.l * r7.l;
+	R3 = (A1 = r6.h * R7.h), R2 = (A0 = R6.l * r7.l);
+	R5 = (A1 = r3.h * r7.h) (M), r4 = (A0 += R3.l * r7.l) (fu);
+	R3 = a1, r2 = (a0 += r0.l *r1.l) (s2rnd);
+	r1 = (a1 += r3.h * r2.h), r0 = (a0 = r3.l * r2.l) (is);
+
+	.text
+	.global vector_negate
+vector_negate:
+	R0 = - R1 (V);
+	r7 = - r2 (v);
+
+	.text
+	.global vector_pack
+vector_pack:
+	R7 = Pack (r0.h, r1.l);
+	r6 = PACK (r1.H, r6.H);
+	R5 = pack (R2.L, R2.H);
+	
+	.text
+	.global vector_search
+vector_search:
+	(R0, R1) = search R2 (lt);
+	(r6, r7) = Search r0 (LE);
+	(r3, r6) = SEARCH r1 (Gt);
+	(r4, R5) = sEARch r3 (gE);
diff --git a/gas/testsuite/gas/bfin/vector2.d b/gas/testsuite/gas/bfin/vector2.d
new file mode 100644
index 000000000000..57f3a91e2fa3
--- /dev/null
+++ b/gas/testsuite/gas/bfin/vector2.d
@@ -0,0 +1,471 @@
+#objdump: -dr
+#name: vector2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	0c c4 13 0e 	R7.H=R7.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\);
+   4:	0c c4 0a 00 	R0.H=R0.L=SIGN\(R1.H\)\*R2.H\+SIGN\(R1.L\)\*R2.L\);
+   8:	0c c4 25 06 	R3.H=R3.L=SIGN\(R4.H\)\*R5.H\+SIGN\(R4.L\)\*R5.L\);
+   c:	0c c4 38 0c 	R6.H=R6.L=SIGN\(R7.H\)\*R0.H\+SIGN\(R7.L\)\*R0.L\);
+  10:	0c c4 13 02 	R1.H=R1.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\);
+  14:	0c c4 2e 08 	R4.H=R4.L=SIGN\(R5.H\)\*R6.H\+SIGN\(R5.L\)\*R6.L\);
+  18:	0c c4 01 0e 	R7.H=R7.L=SIGN\(R0.H\)\*R1.H\+SIGN\(R0.L\)\*R1.L\);
+  1c:	0c c4 1c 04 	R2.H=R2.L=SIGN\(R3.H\)\*R4.H\+SIGN\(R3.L\)\*R4.L\);
+  20:	09 c6 13 8a 	R5=VIT_MAX\(R3,R2\)\(ASL\);
+  24:	09 c6 01 ce 	R7=VIT_MAX\(R1,R0\)\(ASR\);
+  28:	09 c6 11 80 	R0=VIT_MAX\(R1,R2\)\(ASL\);
+  2c:	09 c6 2c c6 	R3=VIT_MAX\(R4,R5\)\(ASR\);
+  30:	09 c6 07 8c 	R6=VIT_MAX\(R7,R0\)\(ASL\);
+  34:	09 c6 1a c2 	R1=VIT_MAX\(R2,R3\)\(ASR\);
+  38:	09 c6 35 88 	R4=VIT_MAX\(R5,R6\)\(ASL\);
+  3c:	09 c6 08 ce 	R7=VIT_MAX\(R0,R1\)\(ASR\);
+  40:	09 c6 23 84 	R2=VIT_MAX\(R3,R4\)\(ASL\);
+  44:	09 c6 3e ca 	R5=VIT_MAX\(R6,R7\)\(ASR\);
+  48:	09 c6 01 06 	R3.L=VIT_MAX \(R1\) \(ASL\);
+  4c:	09 c6 01 46 	R3.L=VIT_MAX \(R1\) \(ASR\);
+  50:	09 c6 01 00 	R0.L=VIT_MAX \(R1\) \(ASL\);
+  54:	09 c6 03 44 	R2.L=VIT_MAX \(R3\) \(ASR\);
+  58:	09 c6 05 08 	R4.L=VIT_MAX \(R5\) \(ASL\);
+  5c:	09 c6 07 4c 	R6.L=VIT_MAX \(R7\) \(ASR\);
+  60:	09 c6 02 02 	R1.L=VIT_MAX \(R2\) \(ASL\);
+  64:	09 c6 04 46 	R3.L=VIT_MAX \(R4\) \(ASR\);
+  68:	09 c6 06 0a 	R5.L=VIT_MAX \(R6\) \(ASL\);
+  6c:	09 c6 00 4e 	R7.L=VIT_MAX \(R0\) \(ASR\);
+  70:	06 c4 08 86 	R3= ABS R1\(V\);
+  74:	06 c4 00 80 	R0= ABS R0\(V\);
+  78:	06 c4 08 80 	R0= ABS R1\(V\);
+  7c:	06 c4 18 84 	R2= ABS R3\(V\);
+  80:	06 c4 28 88 	R4= ABS R5\(V\);
+  84:	06 c4 38 8c 	R6= ABS R7\(V\);
+  88:	06 c4 00 82 	R1= ABS R0\(V\);
+  8c:	06 c4 10 86 	R3= ABS R2\(V\);
+  90:	06 c4 20 8a 	R5= ABS R4\(V\);
+  94:	06 c4 30 8e 	R7= ABS R6\(V\);
+  98:	00 c4 1c 0a 	R5=R3\+\|\+R4 ;
+  9c:	00 c4 0a 00 	R0=R1\+\|\+R2 ;
+  a0:	00 c4 25 06 	R3=R4\+\|\+R5 ;
+  a4:	00 c4 38 0c 	R6=R7\+\|\+R0 ;
+  a8:	00 c4 13 02 	R1=R2\+\|\+R3 ;
+  ac:	00 c4 1d 08 	R4=R3\+\|\+R5 ;
+  b0:	00 c4 1f 0c 	R6=R3\+\|\+R7 ;
+  b4:	00 c4 0a 20 	R0=R1\+\|\+R2 \(S\);
+  b8:	00 c4 25 26 	R3=R4\+\|\+R5 \(S\);
+  bc:	00 c4 38 2c 	R6=R7\+\|\+R0 \(S\);
+  c0:	00 c4 13 22 	R1=R2\+\|\+R3 \(S\);
+  c4:	00 c4 1d 28 	R4=R3\+\|\+R5 \(S\);
+  c8:	00 c4 1f 2c 	R6=R3\+\|\+R7 \(S\);
+  cc:	00 c4 0a 10 	R0=R1\+\|\+R2 \(CO\);
+  d0:	00 c4 25 16 	R3=R4\+\|\+R5 \(CO\);
+  d4:	00 c4 38 1c 	R6=R7\+\|\+R0 \(CO\);
+  d8:	00 c4 13 12 	R1=R2\+\|\+R3 \(CO\);
+  dc:	00 c4 1d 18 	R4=R3\+\|\+R5 \(CO\);
+  e0:	00 c4 1f 1c 	R6=R3\+\|\+R7 \(CO\);
+  e4:	00 c4 0a 30 	R0=R1\+\|\+R2 \(SCO\);
+  e8:	00 c4 25 36 	R3=R4\+\|\+R5 \(SCO\);
+  ec:	00 c4 38 3c 	R6=R7\+\|\+R0 \(SCO\);
+  f0:	00 c4 13 32 	R1=R2\+\|\+R3 \(SCO\);
+  f4:	00 c4 1d 38 	R4=R3\+\|\+R5 \(SCO\);
+  f8:	00 c4 1f 3c 	R6=R3\+\|\+R7 \(SCO\);
+  fc:	00 c4 01 ac 	R6=R0-\|\+R1 \(S\);
+ 100:	00 c4 0a 80 	R0=R1-\|\+R2 ;
+ 104:	00 c4 25 86 	R3=R4-\|\+R5 ;
+ 108:	00 c4 38 8c 	R6=R7-\|\+R0 ;
+ 10c:	00 c4 13 82 	R1=R2-\|\+R3 ;
+ 110:	00 c4 1d 88 	R4=R3-\|\+R5 ;
+ 114:	00 c4 1f 8c 	R6=R3-\|\+R7 ;
+ 118:	00 c4 0a a0 	R0=R1-\|\+R2 \(S\);
+ 11c:	00 c4 25 a6 	R3=R4-\|\+R5 \(S\);
+ 120:	00 c4 38 ac 	R6=R7-\|\+R0 \(S\);
+ 124:	00 c4 13 a2 	R1=R2-\|\+R3 \(S\);
+ 128:	00 c4 1d a8 	R4=R3-\|\+R5 \(S\);
+ 12c:	00 c4 1f ac 	R6=R3-\|\+R7 \(S\);
+ 130:	00 c4 0a 90 	R0=R1-\|\+R2 \(CO\);
+ 134:	00 c4 25 96 	R3=R4-\|\+R5 \(CO\);
+ 138:	00 c4 38 9c 	R6=R7-\|\+R0 \(CO\);
+ 13c:	00 c4 13 92 	R1=R2-\|\+R3 \(CO\);
+ 140:	00 c4 1d 98 	R4=R3-\|\+R5 \(CO\);
+ 144:	00 c4 1f 9c 	R6=R3-\|\+R7 \(CO\);
+ 148:	00 c4 0a b0 	R0=R1-\|\+R2 \(SCO\);
+ 14c:	00 c4 25 b6 	R3=R4-\|\+R5 \(SCO\);
+ 150:	00 c4 38 bc 	R6=R7-\|\+R0 \(SCO\);
+ 154:	00 c4 13 b2 	R1=R2-\|\+R3 \(SCO\);
+ 158:	00 c4 1d b8 	R4=R3-\|\+R5 \(SCO\);
+ 15c:	00 c4 1f bc 	R6=R3-\|\+R7 \(SCO\);
+ 160:	00 c4 11 50 	R0=R2\+\|-R1 \(CO\);
+ 164:	00 c4 0a 40 	R0=R1\+\|-R2 ;
+ 168:	00 c4 25 46 	R3=R4\+\|-R5 ;
+ 16c:	00 c4 38 4c 	R6=R7\+\|-R0 ;
+ 170:	00 c4 13 42 	R1=R2\+\|-R3 ;
+ 174:	00 c4 1d 48 	R4=R3\+\|-R5 ;
+ 178:	00 c4 1f 4c 	R6=R3\+\|-R7 ;
+ 17c:	00 c4 0a 60 	R0=R1\+\|-R2 \(S\);
+ 180:	00 c4 25 66 	R3=R4\+\|-R5 \(S\);
+ 184:	00 c4 38 6c 	R6=R7\+\|-R0 \(S\);
+ 188:	00 c4 13 62 	R1=R2\+\|-R3 \(S\);
+ 18c:	00 c4 1d 68 	R4=R3\+\|-R5 \(S\);
+ 190:	00 c4 1f 6c 	R6=R3\+\|-R7 \(S\);
+ 194:	00 c4 0a 50 	R0=R1\+\|-R2 \(CO\);
+ 198:	00 c4 25 56 	R3=R4\+\|-R5 \(CO\);
+ 19c:	00 c4 38 5c 	R6=R7\+\|-R0 \(CO\);
+ 1a0:	00 c4 13 52 	R1=R2\+\|-R3 \(CO\);
+ 1a4:	00 c4 1d 58 	R4=R3\+\|-R5 \(CO\);
+ 1a8:	00 c4 1f 5c 	R6=R3\+\|-R7 \(CO\);
+ 1ac:	00 c4 0a 70 	R0=R1\+\|-R2 \(SCO\);
+ 1b0:	00 c4 25 76 	R3=R4\+\|-R5 \(SCO\);
+ 1b4:	00 c4 38 7c 	R6=R7\+\|-R0 \(SCO\);
+ 1b8:	00 c4 13 72 	R1=R2\+\|-R3 \(SCO\);
+ 1bc:	00 c4 1d 78 	R4=R3\+\|-R5 \(SCO\);
+ 1c0:	00 c4 1f 7c 	R6=R3\+\|-R7 \(SCO\);
+ 1c4:	00 c4 1e fe 	R7=R3-\|-R6 \(SCO\);
+ 1c8:	00 c4 0a c0 	R0=R1-\|-R2 ;
+ 1cc:	00 c4 25 c6 	R3=R4-\|-R5 ;
+ 1d0:	00 c4 38 cc 	R6=R7-\|-R0 ;
+ 1d4:	00 c4 13 c2 	R1=R2-\|-R3 ;
+ 1d8:	00 c4 1d c8 	R4=R3-\|-R5 ;
+ 1dc:	00 c4 1f cc 	R6=R3-\|-R7 ;
+ 1e0:	00 c4 0a e0 	R0=R1-\|-R2 \(S\);
+ 1e4:	00 c4 25 e6 	R3=R4-\|-R5 \(S\);
+ 1e8:	00 c4 38 ec 	R6=R7-\|-R0 \(S\);
+ 1ec:	00 c4 13 e2 	R1=R2-\|-R3 \(S\);
+ 1f0:	00 c4 1d e8 	R4=R3-\|-R5 \(S\);
+ 1f4:	00 c4 1f ec 	R6=R3-\|-R7 \(S\);
+ 1f8:	00 c4 0a d0 	R0=R1-\|-R2 \(CO\);
+ 1fc:	00 c4 25 d6 	R3=R4-\|-R5 \(CO\);
+ 200:	00 c4 38 dc 	R6=R7-\|-R0 \(CO\);
+ 204:	00 c4 13 d2 	R1=R2-\|-R3 \(CO\);
+ 208:	00 c4 1d d8 	R4=R3-\|-R5 \(CO\);
+ 20c:	00 c4 1f dc 	R6=R3-\|-R7 \(CO\);
+ 210:	00 c4 0a f0 	R0=R1-\|-R2 \(SCO\);
+ 214:	00 c4 25 f6 	R3=R4-\|-R5 \(SCO\);
+ 218:	00 c4 38 fc 	R6=R7-\|-R0 \(SCO\);
+ 21c:	00 c4 13 f2 	R1=R2-\|-R3 \(SCO\);
+ 220:	00 c4 1d f8 	R4=R3-\|-R5 \(SCO\);
+ 224:	00 c4 1f fc 	R6=R3-\|-R7 \(SCO\);
+ 228:	01 c4 5c 0f 	R5=R3\+\|\+R4,R7=R3-\|-R4;
+ 22c:	01 c4 0a 0e 	R0=R1\+\|\+R2,R7=R1-\|-R2;
+ 230:	01 c4 e5 0c 	R3=R4\+\|\+R5,R6=R4-\|-R5;
+ 234:	01 c4 b8 0b 	R6=R7\+\|\+R0,R5=R7-\|-R0;
+ 238:	01 c4 53 08 	R1=R2\+\|\+R3,R4=R2-\|-R3;
+ 23c:	01 c4 1d 07 	R4=R3\+\|\+R5,R3=R3-\|-R5;
+ 240:	01 c4 9f 05 	R6=R3\+\|\+R7,R2=R3-\|-R7;
+ 244:	01 c4 0a 2e 	R0=R1\+\|\+R2,R7=R1-\|-R2\(S\);
+ 248:	01 c4 e5 2c 	R3=R4\+\|\+R5,R6=R4-\|-R5\(S\);
+ 24c:	01 c4 b8 2b 	R6=R7\+\|\+R0,R5=R7-\|-R0\(S\);
+ 250:	01 c4 53 28 	R1=R2\+\|\+R3,R4=R2-\|-R3\(S\);
+ 254:	01 c4 1d 27 	R4=R3\+\|\+R5,R3=R3-\|-R5\(S\);
+ 258:	01 c4 9f 25 	R6=R3\+\|\+R7,R2=R3-\|-R7\(S\);
+ 25c:	01 c4 0a 1e 	R0=R1\+\|\+R2,R7=R1-\|-R2\(CO\);
+ 260:	01 c4 e5 1c 	R3=R4\+\|\+R5,R6=R4-\|-R5\(CO\);
+ 264:	01 c4 b8 1b 	R6=R7\+\|\+R0,R5=R7-\|-R0\(CO\);
+ 268:	01 c4 53 18 	R1=R2\+\|\+R3,R4=R2-\|-R3\(CO\);
+ 26c:	01 c4 1d 17 	R4=R3\+\|\+R5,R3=R3-\|-R5\(CO\);
+ 270:	01 c4 9f 15 	R6=R3\+\|\+R7,R2=R3-\|-R7\(CO\);
+ 274:	01 c4 0a 3e 	R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO\);
+ 278:	01 c4 e5 3c 	R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO\);
+ 27c:	01 c4 b8 3b 	R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO\);
+ 280:	01 c4 53 38 	R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO\);
+ 284:	01 c4 1d 37 	R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO\);
+ 288:	01 c4 9f 35 	R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO\);
+ 28c:	01 c4 0a 8e 	R0=R1\+\|\+R2,R7=R1-\|-R2\(ASR\);
+ 290:	01 c4 e5 8c 	R3=R4\+\|\+R5,R6=R4-\|-R5\(ASR\);
+ 294:	01 c4 b8 8b 	R6=R7\+\|\+R0,R5=R7-\|-R0\(ASR\);
+ 298:	01 c4 53 88 	R1=R2\+\|\+R3,R4=R2-\|-R3\(ASR\);
+ 29c:	01 c4 1d 87 	R4=R3\+\|\+R5,R3=R3-\|-R5\(ASR\);
+ 2a0:	01 c4 9f 85 	R6=R3\+\|\+R7,R2=R3-\|-R7\(ASR\);
+ 2a4:	01 c4 0a ce 	R0=R1\+\|\+R2,R7=R1-\|-R2\(ASL\);
+ 2a8:	01 c4 e5 cc 	R3=R4\+\|\+R5,R6=R4-\|-R5\(ASL\);
+ 2ac:	01 c4 b8 cb 	R6=R7\+\|\+R0,R5=R7-\|-R0\(ASL\);
+ 2b0:	01 c4 53 c8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(ASL\);
+ 2b4:	01 c4 1d c7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(ASL\);
+ 2b8:	01 c4 9f c5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(ASL\);
+ 2bc:	01 c4 0a ae 	R0=R1\+\|\+R2,R7=R1-\|-R2\(S,ASR\);
+ 2c0:	01 c4 e5 ac 	R3=R4\+\|\+R5,R6=R4-\|-R5\(S,ASR\);
+ 2c4:	01 c4 b8 ab 	R6=R7\+\|\+R0,R5=R7-\|-R0\(S,ASR\);
+ 2c8:	01 c4 53 a8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(S,ASR\);
+ 2cc:	01 c4 1d a7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(S,ASR\);
+ 2d0:	01 c4 9f a5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(S,ASR\);
+ 2d4:	01 c4 0a 9e 	R0=R1\+\|\+R2,R7=R1-\|-R2\(CO,ASR\);
+ 2d8:	01 c4 e5 9c 	R3=R4\+\|\+R5,R6=R4-\|-R5\(CO,ASR\);
+ 2dc:	01 c4 b8 9b 	R6=R7\+\|\+R0,R5=R7-\|-R0\(CO,ASR\);
+ 2e0:	01 c4 53 98 	R1=R2\+\|\+R3,R4=R2-\|-R3\(CO,ASR\);
+ 2e4:	01 c4 1d 97 	R4=R3\+\|\+R5,R3=R3-\|-R5\(CO,ASR\);
+ 2e8:	01 c4 9f 95 	R6=R3\+\|\+R7,R2=R3-\|-R7\(CO,ASR\);
+ 2ec:	01 c4 0a be 	R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO,ASR\);
+ 2f0:	01 c4 e5 bc 	R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO,ASR\);
+ 2f4:	01 c4 b8 bb 	R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO,ASR\);
+ 2f8:	01 c4 53 b8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO,ASR\);
+ 2fc:	01 c4 1d b7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO,ASR\);
+ 300:	01 c4 9f b5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO,ASR\);
+ 304:	01 c4 0a ee 	R0=R1\+\|\+R2,R7=R1-\|-R2\(S,ASL\);
+ 308:	01 c4 e5 ec 	R3=R4\+\|\+R5,R6=R4-\|-R5\(S,ASL\);
+ 30c:	01 c4 b8 eb 	R6=R7\+\|\+R0,R5=R7-\|-R0\(S,ASL\);
+ 310:	01 c4 53 e8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(S,ASL\);
+ 314:	01 c4 1d e7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(S,ASL\);
+ 318:	01 c4 9f e5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(S,ASL\);
+ 31c:	01 c4 0a de 	R0=R1\+\|\+R2,R7=R1-\|-R2\(CO,ASL\);
+ 320:	01 c4 e5 dc 	R3=R4\+\|\+R5,R6=R4-\|-R5\(CO,ASL\);
+ 324:	01 c4 b8 db 	R6=R7\+\|\+R0,R5=R7-\|-R0\(CO,ASL\);
+ 328:	01 c4 53 d8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(CO,ASL\);
+ 32c:	01 c4 1d d7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(CO,ASL\);
+ 330:	01 c4 9f d5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(CO,ASL\);
+ 334:	01 c4 0a fe 	R0=R1\+\|\+R2,R7=R1-\|-R2\(SCO,ASL\);
+ 338:	01 c4 e5 fc 	R3=R4\+\|\+R5,R6=R4-\|-R5\(SCO,ASL\);
+ 33c:	01 c4 b8 fb 	R6=R7\+\|\+R0,R5=R7-\|-R0\(SCO,ASL\);
+ 340:	01 c4 53 f8 	R1=R2\+\|\+R3,R4=R2-\|-R3\(SCO,ASL\);
+ 344:	01 c4 1d f7 	R4=R3\+\|\+R5,R3=R3-\|-R5\(SCO,ASL\);
+ 348:	01 c4 9f f5 	R6=R3\+\|\+R7,R2=R3-\|-R7\(SCO,ASL\);
+ 34c:	21 c4 5c 0f 	R5=R3\+\|-R4,R7=R3-\|\+R4;
+ 350:	21 c4 0a 0e 	R0=R1\+\|-R2,R7=R1-\|\+R2;
+ 354:	21 c4 e5 0c 	R3=R4\+\|-R5,R6=R4-\|\+R5;
+ 358:	21 c4 b8 0b 	R6=R7\+\|-R0,R5=R7-\|\+R0;
+ 35c:	21 c4 53 08 	R1=R2\+\|-R3,R4=R2-\|\+R3;
+ 360:	21 c4 1d 07 	R4=R3\+\|-R5,R3=R3-\|\+R5;
+ 364:	21 c4 9f 05 	R6=R3\+\|-R7,R2=R3-\|\+R7;
+ 368:	21 c4 0a 2e 	R0=R1\+\|-R2,R7=R1-\|\+R2\(S\);
+ 36c:	21 c4 e5 2c 	R3=R4\+\|-R5,R6=R4-\|\+R5\(S\);
+ 370:	21 c4 b8 2b 	R6=R7\+\|-R0,R5=R7-\|\+R0\(S\);
+ 374:	21 c4 53 28 	R1=R2\+\|-R3,R4=R2-\|\+R3\(S\);
+ 378:	21 c4 1d 27 	R4=R3\+\|-R5,R3=R3-\|\+R5\(S\);
+ 37c:	21 c4 9f 25 	R6=R3\+\|-R7,R2=R3-\|\+R7\(S\);
+ 380:	21 c4 0a 1e 	R0=R1\+\|-R2,R7=R1-\|\+R2\(CO\);
+ 384:	21 c4 e5 1c 	R3=R4\+\|-R5,R6=R4-\|\+R5\(CO\);
+ 388:	21 c4 b8 1b 	R6=R7\+\|-R0,R5=R7-\|\+R0\(CO\);
+ 38c:	21 c4 53 18 	R1=R2\+\|-R3,R4=R2-\|\+R3\(CO\);
+ 390:	21 c4 1d 17 	R4=R3\+\|-R5,R3=R3-\|\+R5\(CO\);
+ 394:	21 c4 9f 15 	R6=R3\+\|-R7,R2=R3-\|\+R7\(CO\);
+ 398:	21 c4 0a 3e 	R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO\);
+ 39c:	21 c4 e5 3c 	R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO\);
+ 3a0:	21 c4 b8 3b 	R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO\);
+ 3a4:	21 c4 53 38 	R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO\);
+ 3a8:	21 c4 1d 37 	R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO\);
+ 3ac:	21 c4 9f 35 	R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO\);
+ 3b0:	21 c4 0a 8e 	R0=R1\+\|-R2,R7=R1-\|\+R2\(ASR\);
+ 3b4:	21 c4 e5 8c 	R3=R4\+\|-R5,R6=R4-\|\+R5\(ASR\);
+ 3b8:	21 c4 b8 8b 	R6=R7\+\|-R0,R5=R7-\|\+R0\(ASR\);
+ 3bc:	21 c4 53 88 	R1=R2\+\|-R3,R4=R2-\|\+R3\(ASR\);
+ 3c0:	21 c4 1d 87 	R4=R3\+\|-R5,R3=R3-\|\+R5\(ASR\);
+ 3c4:	21 c4 9f 85 	R6=R3\+\|-R7,R2=R3-\|\+R7\(ASR\);
+ 3c8:	21 c4 0a ce 	R0=R1\+\|-R2,R7=R1-\|\+R2\(ASL\);
+ 3cc:	21 c4 e5 cc 	R3=R4\+\|-R5,R6=R4-\|\+R5\(ASL\);
+ 3d0:	21 c4 b8 cb 	R6=R7\+\|-R0,R5=R7-\|\+R0\(ASL\);
+ 3d4:	21 c4 53 c8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(ASL\);
+ 3d8:	21 c4 1d c7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(ASL\);
+ 3dc:	21 c4 9f c5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(ASL\);
+ 3e0:	21 c4 0a ae 	R0=R1\+\|-R2,R7=R1-\|\+R2\(S,ASR\);
+ 3e4:	21 c4 e5 ac 	R3=R4\+\|-R5,R6=R4-\|\+R5\(S,ASR\);
+ 3e8:	21 c4 b8 ab 	R6=R7\+\|-R0,R5=R7-\|\+R0\(S,ASR\);
+ 3ec:	21 c4 53 a8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(S,ASR\);
+ 3f0:	21 c4 1d a7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(S,ASR\);
+ 3f4:	21 c4 9f a5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(S,ASR\);
+ 3f8:	21 c4 0a 9e 	R0=R1\+\|-R2,R7=R1-\|\+R2\(CO,ASR\);
+ 3fc:	21 c4 e5 9c 	R3=R4\+\|-R5,R6=R4-\|\+R5\(CO,ASR\);
+ 400:	21 c4 b8 9b 	R6=R7\+\|-R0,R5=R7-\|\+R0\(CO,ASR\);
+ 404:	21 c4 53 98 	R1=R2\+\|-R3,R4=R2-\|\+R3\(CO,ASR\);
+ 408:	21 c4 1d 97 	R4=R3\+\|-R5,R3=R3-\|\+R5\(CO,ASR\);
+ 40c:	21 c4 9f 95 	R6=R3\+\|-R7,R2=R3-\|\+R7\(CO,ASR\);
+ 410:	21 c4 0a be 	R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO,ASR\);
+ 414:	21 c4 e5 bc 	R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO,ASR\);
+ 418:	21 c4 b8 bb 	R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO,ASR\);
+ 41c:	21 c4 53 b8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO,ASR\);
+ 420:	21 c4 1d b7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO,ASR\);
+ 424:	21 c4 9f b5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO,ASR\);
+ 428:	21 c4 0a ee 	R0=R1\+\|-R2,R7=R1-\|\+R2\(S,ASL\);
+ 42c:	21 c4 e5 ec 	R3=R4\+\|-R5,R6=R4-\|\+R5\(S,ASL\);
+ 430:	21 c4 b8 eb 	R6=R7\+\|-R0,R5=R7-\|\+R0\(S,ASL\);
+ 434:	21 c4 53 e8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(S,ASL\);
+ 438:	21 c4 1d e7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(S,ASL\);
+ 43c:	21 c4 9f e5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(S,ASL\);
+ 440:	21 c4 0a de 	R0=R1\+\|-R2,R7=R1-\|\+R2\(CO,ASL\);
+ 444:	21 c4 e5 dc 	R3=R4\+\|-R5,R6=R4-\|\+R5\(CO,ASL\);
+ 448:	21 c4 b8 db 	R6=R7\+\|-R0,R5=R7-\|\+R0\(CO,ASL\);
+ 44c:	21 c4 53 d8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(CO,ASL\);
+ 450:	21 c4 1d d7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(CO,ASL\);
+ 454:	21 c4 9f d5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(CO,ASL\);
+ 458:	21 c4 0a fe 	R0=R1\+\|-R2,R7=R1-\|\+R2\(SCO,ASL\);
+ 45c:	21 c4 e5 fc 	R3=R4\+\|-R5,R6=R4-\|\+R5\(SCO,ASL\);
+ 460:	21 c4 b8 fb 	R6=R7\+\|-R0,R5=R7-\|\+R0\(SCO,ASL\);
+ 464:	21 c4 53 f8 	R1=R2\+\|-R3,R4=R2-\|\+R3\(SCO,ASL\);
+ 468:	21 c4 1d f7 	R4=R3\+\|-R5,R3=R3-\|\+R5\(SCO,ASL\);
+ 46c:	21 c4 9f f5 	R6=R3\+\|-R7,R2=R3-\|\+R7\(SCO,ASL\);
+ 470:	04 c4 81 86 	R2=R0\+R1,R3=R0-R1 \(NS\);
+ 474:	04 c4 c1 81 	R7=R0\+R1,R0=R0-R1 \(NS\);
+ 478:	04 c4 8a 83 	R6=R1\+R2,R1=R1-R2 \(NS\);
+ 47c:	04 c4 53 85 	R5=R2\+R3,R2=R2-R3 \(NS\);
+ 480:	04 c4 1c 87 	R4=R3\+R4,R3=R3-R4 \(NS\);
+ 484:	04 c4 e5 88 	R3=R4\+R5,R4=R4-R5 \(NS\);
+ 488:	04 c4 ae 8a 	R2=R5\+R6,R5=R5-R6 \(NS\);
+ 48c:	04 c4 77 8c 	R1=R6\+R7,R6=R6-R7 \(NS\);
+ 490:	04 c4 38 8e 	R0=R7\+R0,R7=R7-R0 \(NS\);
+ 494:	04 c4 81 a6 	R2=R0\+R1,R3=R0-R1 \(S\);
+ 498:	04 c4 c1 a1 	R7=R0\+R1,R0=R0-R1 \(S\);
+ 49c:	04 c4 8a a3 	R6=R1\+R2,R1=R1-R2 \(S\);
+ 4a0:	04 c4 53 a5 	R5=R2\+R3,R2=R2-R3 \(S\);
+ 4a4:	04 c4 1c a7 	R4=R3\+R4,R3=R3-R4 \(S\);
+ 4a8:	04 c4 e5 a8 	R3=R4\+R5,R4=R4-R5 \(S\);
+ 4ac:	04 c4 ae aa 	R2=R5\+R6,R5=R5-R6 \(S\);
+ 4b0:	04 c4 77 ac 	R1=R6\+R7,R6=R6-R7 \(S\);
+ 4b4:	04 c4 38 ae 	R0=R7\+R0,R7=R7-R0 \(S\);
+ 4b8:	11 c4 [0-3][[:xdigit:]] 02 	R0=A1\+A0,R1=A1-A0 \(NS\);
+ 4bc:	11 c4 [8|9|a|b][[:xdigit:]] 06 	R2=A1\+A0,R3=A1-A0 \(NS\);
+ 4c0:	11 c4 [0-3][[:xdigit:]] 0b 	R4=A1\+A0,R5=A1-A0 \(NS\);
+ 4c4:	11 c4 [8|9|a|b][[:xdigit:]] 0f 	R6=A1\+A0,R7=A1-A0 \(NS\);
+ 4c8:	11 c4 [4-7][[:xdigit:]] 00 	R1=A1\+A0,R0=A1-A0 \(NS\);
+ 4cc:	11 c4 [c-f][[:xdigit:]] 04 	R3=A1\+A0,R2=A1-A0 \(NS\);
+ 4d0:	11 c4 [4-7][[:xdigit:]] 09 	R5=A1\+A0,R4=A1-A0 \(NS\);
+ 4d4:	11 c4 [0-3][[:xdigit:]] 22 	R0=A1\+A0,R1=A1-A0 \(S\);
+ 4d8:	11 c4 [8|9|a|b][[:xdigit:]] 26 	R2=A1\+A0,R3=A1-A0 \(S\);
+ 4dc:	11 c4 [0-3][[:xdigit:]] 2b 	R4=A1\+A0,R5=A1-A0 \(S\);
+ 4e0:	11 c4 [8|9|a|b][[:xdigit:]] 2f 	R6=A1\+A0,R7=A1-A0 \(S\);
+ 4e4:	11 c4 [4-7][[:xdigit:]] 20 	R1=A1\+A0,R0=A1-A0 \(S\);
+ 4e8:	11 c4 [c-f][[:xdigit:]] 24 	R3=A1\+A0,R2=A1-A0 \(S\);
+ 4ec:	11 c4 [4-7][[:xdigit:]] 29 	R5=A1\+A0,R4=A1-A0 \(S\);
+ 4f0:	11 c4 [0-3][[:xdigit:]] 6d 	R4=A0\+A1,R6=A0-A1 \(S\);
+ 4f4:	11 c4 [0-3][[:xdigit:]] 42 	R0=A0\+A1,R1=A0-A1 \(NS\);
+ 4f8:	11 c4 [8|9|a|b][[:xdigit:]] 46 	R2=A0\+A1,R3=A0-A1 \(NS\);
+ 4fc:	11 c4 [0-3][[:xdigit:]] 4b 	R4=A0\+A1,R5=A0-A1 \(NS\);
+ 500:	11 c4 [8|9|a|b][[:xdigit:]] 4f 	R6=A0\+A1,R7=A0-A1 \(NS\);
+ 504:	11 c4 [4-7][[:xdigit:]] 40 	R1=A0\+A1,R0=A0-A1 \(NS\);
+ 508:	11 c4 [c-f][[:xdigit:]] 44 	R3=A0\+A1,R2=A0-A1 \(NS\);
+ 50c:	11 c4 [4-7][[:xdigit:]] 49 	R5=A0\+A1,R4=A0-A1 \(NS\);
+ 510:	11 c4 [0-3][[:xdigit:]] 62 	R0=A0\+A1,R1=A0-A1 \(S\);
+ 514:	11 c4 [8|9|a|b][[:xdigit:]] 66 	R2=A0\+A1,R3=A0-A1 \(S\);
+ 518:	11 c4 [0-3][[:xdigit:]] 6b 	R4=A0\+A1,R5=A0-A1 \(S\);
+ 51c:	11 c4 [8|9|a|b][[:xdigit:]] 6f 	R6=A0\+A1,R7=A0-A1 \(S\);
+ 520:	11 c4 [4-7][[:xdigit:]] 60 	R1=A0\+A1,R0=A0-A1 \(S\);
+ 524:	11 c4 [c-f][[:xdigit:]] 64 	R3=A0\+A1,R2=A0-A1 \(S\);
+ 528:	11 c4 [4-7][[:xdigit:]] 69 	R5=A0\+A1,R4=A0-A1 \(S\);
+ 52c:	81 c6 d8 01 	R0=R0>>>0x5 \(V\);
+ 530:	81 c6 d9 01 	R0=R1>>>0x5 \(V\);
+ 534:	81 c6 db 05 	R2=R3>>>0x5 \(V\);
+ 538:	81 c6 dd 09 	R4=R5>>>0x5 \(V\);
+ 53c:	81 c6 df 0d 	R6=R7>>>0x5 \(V\);
+ 540:	81 c6 d8 03 	R1=R0>>>0x5 \(V\);
+ 544:	81 c6 da 07 	R3=R2>>>0x5 \(V\);
+ 548:	81 c6 dc 0b 	R5=R4>>>0x5 \(V\);
+ 54c:	81 c6 de 0f 	R7=R6>>>0x5 \(V\);
+ 550:	81 c6 29 40 	R0=R1<<0x5 \(V, S\);
+ 554:	81 c6 2b 44 	R2=R3<<0x5 \(V, S\);
+ 558:	81 c6 2d 48 	R4=R5<<0x5 \(V, S\);
+ 55c:	81 c6 2f 4c 	R6=R7<<0x5 \(V, S\);
+ 560:	81 c6 28 42 	R1=R0<<0x5 \(V, S\);
+ 564:	81 c6 2a 46 	R3=R2<<0x5 \(V, S\);
+ 568:	81 c6 2c 4a 	R5=R4<<0x5 \(V, S\);
+ 56c:	81 c6 2e 4e 	R7=R6<<0x5 \(V, S\);
+ 570:	01 c6 2f 04 	R2= ASHIFT R7 BY R5.L\(V\);
+ 574:	01 c6 11 00 	R0= ASHIFT R1 BY R2.L\(V\);
+ 578:	01 c6 2c 06 	R3= ASHIFT R4 BY R5.L\(V\);
+ 57c:	01 c6 07 0c 	R6= ASHIFT R7 BY R0.L\(V\);
+ 580:	01 c6 1a 02 	R1= ASHIFT R2 BY R3.L\(V\);
+ 584:	01 c6 35 08 	R4= ASHIFT R5 BY R6.L\(V\);
+ 588:	01 c6 08 0e 	R7= ASHIFT R0 BY R1.L\(V\);
+ 58c:	01 c6 23 04 	R2= ASHIFT R3 BY R4.L\(V\);
+ 590:	01 c6 3e 0a 	R5= ASHIFT R6 BY R7.L\(V\);
+ 594:	01 c6 11 40 	R0= ASHIFT R1 BY R2.L\(V,S\);
+ 598:	01 c6 2c 46 	R3= ASHIFT R4 BY R5.L\(V,S\);
+ 59c:	01 c6 07 4c 	R6= ASHIFT R7 BY R0.L\(V,S\);
+ 5a0:	01 c6 1a 42 	R1= ASHIFT R2 BY R3.L\(V,S\);
+ 5a4:	01 c6 35 48 	R4= ASHIFT R5 BY R6.L\(V,S\);
+ 5a8:	01 c6 08 4e 	R7= ASHIFT R0 BY R1.L\(V,S\);
+ 5ac:	01 c6 23 44 	R2= ASHIFT R3 BY R4.L\(V,S\);
+ 5b0:	01 c6 3e 4a 	R5= ASHIFT R6 BY R7.L\(V,S\);
+ 5b4:	81 c6 d9 81 	R0=R1 >> 0x5 \(V\);
+ 5b8:	81 c6 db 85 	R2=R3 >> 0x5 \(V\);
+ 5bc:	81 c6 dd 89 	R4=R5 >> 0x5 \(V\);
+ 5c0:	81 c6 df 8d 	R6=R7 >> 0x5 \(V\);
+ 5c4:	81 c6 d8 83 	R1=R0 >> 0x5 \(V\);
+ 5c8:	81 c6 da 87 	R3=R2 >> 0x5 \(V\);
+ 5cc:	81 c6 dc 8b 	R5=R4 >> 0x5 \(V\);
+ 5d0:	81 c6 de 8f 	R7=R6 >> 0x5 \(V\);
+ 5d4:	81 c6 29 80 	R0=R1<<0x5 \(V\);
+ 5d8:	81 c6 2b 84 	R2=R3<<0x5 \(V\);
+ 5dc:	81 c6 2d 88 	R4=R5<<0x5 \(V\);
+ 5e0:	81 c6 2f 8c 	R6=R7<<0x5 \(V\);
+ 5e4:	81 c6 28 82 	R1=R0<<0x5 \(V\);
+ 5e8:	81 c6 2a 86 	R3=R2<<0x5 \(V\);
+ 5ec:	81 c6 2c 8a 	R5=R4<<0x5 \(V\);
+ 5f0:	81 c6 2e 8e 	R7=R6<<0x5 \(V\);
+ 5f4:	01 c6 11 80 	R0=SHIFT R1 BY R2.L\(V\);
+ 5f8:	01 c6 2c 86 	R3=SHIFT R4 BY R5.L\(V\);
+ 5fc:	01 c6 07 8c 	R6=SHIFT R7 BY R0.L\(V\);
+ 600:	01 c6 1a 82 	R1=SHIFT R2 BY R3.L\(V\);
+ 604:	01 c6 35 88 	R4=SHIFT R5 BY R6.L\(V\);
+ 608:	01 c6 08 8e 	R7=SHIFT R0 BY R1.L\(V\);
+ 60c:	01 c6 23 84 	R2=SHIFT R3 BY R4.L\(V\);
+ 610:	01 c6 3e 8a 	R5=SHIFT R6 BY R7.L\(V\);
+ 614:	06 c4 08 0e 	R7=MAX\(R1,R0\)\(V\);
+ 618:	06 c4 0a 00 	R0=MAX\(R1,R2\)\(V\);
+ 61c:	06 c4 25 06 	R3=MAX\(R4,R5\)\(V\);
+ 620:	06 c4 38 0c 	R6=MAX\(R7,R0\)\(V\);
+ 624:	06 c4 13 02 	R1=MAX\(R2,R3\)\(V\);
+ 628:	06 c4 2e 08 	R4=MAX\(R5,R6\)\(V\);
+ 62c:	06 c4 01 0e 	R7=MAX\(R0,R1\)\(V\);
+ 630:	06 c4 1c 04 	R2=MAX\(R3,R4\)\(V\);
+ 634:	06 c4 37 0a 	R5=MAX\(R6,R7\)\(V\);
+ 638:	06 c4 0a 40 	R0=MIN\(R1,R2\)\(V\);
+ 63c:	06 c4 25 46 	R3=MIN\(R4,R5\)\(V\);
+ 640:	06 c4 38 4c 	R6=MIN\(R7,R0\)\(V\);
+ 644:	06 c4 13 42 	R1=MIN\(R2,R3\)\(V\);
+ 648:	06 c4 2e 48 	R4=MIN\(R5,R6\)\(V\);
+ 64c:	06 c4 01 4e 	R7=MIN\(R0,R1\)\(V\);
+ 650:	06 c4 1c 44 	R2=MIN\(R3,R4\)\(V\);
+ 654:	06 c4 37 4a 	R5=MIN\(R6,R7\)\(V\);
+ 658:	04 c2 be 66 	R2.H = R7.L \* R6.H, R2 = R7.H \* R6.H;
+ 65c:	04 c2 08 e1 	R4.H = R1.H \* R0.H, R4 = R1.L \* R0.L;
+ 660:	14 c2 1a a0 	R0.H = R3.H \* R2.L \(M\), R0 = R3.L \* R2.L;
+ 664:	00 c0 13 46 	a1 = R2.L \* R3.H, a0 = R2.H \* R3.H;
+ 668:	01 c0 08 c0 	a1 \+= R1.H \* R0.H, a0 = R1.L \* R0.L;
+ 66c:	01 c0 1b 96 	a1 \+= R3.H \* R3.L, a0 -= R3.H \* R3.H;
+ 670:	10 c0 1a 88 	a1 = R3.H \* R2.L \(M\), a0 \+= R3.L \* R2.L;
+ 674:	90 c0 3c c8 	a1 = R7.H \* R4.H \(M\), a0 \+= R7.L \* R4.L \(FU\);
+ 678:	01 c1 1a c0 	a1 \+= R3.H \* R2.H, a0 = R3.L \* R2.L \(IS\);
+ 67c:	60 c0 37 c8 	a1 = R6.H \* R7.H, a0 \+= R6.L \* R7.L \(W32\);
+ 680:	04 c0 be 66 	R2.H = \(a1 = R7.L \* R6.H\), R2.L = \(a0 = R7.H \* R6.H\);
+ 684:	05 c0 08 e1 	R4.H = \(a1 \+= R1.H \* R0.H\), R4.L = \(a0 = R1.L \* R0.L\);
+ 688:	05 c0 f5 a7 	R7.H = \(a1 \+= R6.H \* R5.L\), R7.L = \(a0 = R6.H \* R5.H\);
+ 68c:	14 c0 3c a8 	R0.H = \(a1 = R7.H \* R4.L\) \(M\), R0.L = \(a0 \+= R7.L \* R4.L\);
+ 690:	94 c0 5a e9 	R5.H = \(a1 = R3.H \* R2.H\) \(M\), R5.L = \(a0 \+= R3.L \* R2.L\) \(FU\);
+ 694:	05 c1 1a e0 	R0.H = \(a1 \+= R3.H \* R2.H\), R0.L = \(a0 = R3.L \* R2.L\) \(IS\);
+ 698:	04 c0 51 c9 	R5.H = \(a1 = R2.H \* R1.H\), a0 \+= R2.L \* R1.L;
+ 69c:	14 c0 d1 c0 	R3.H = \(a1 = R2.H \* R1.H\) \(M\), a0 = R2.L \* R1.L;
+ 6a0:	27 c0 c1 28 	R3.H = A1, R3.L = \(a0 \+= R0.L \* R1.L\) \(S2RND\);
+ 6a4:	25 c1 3e e8 	R0.H = \(a1 \+= R7.H \* R6.H\), R0.L = \(a0 \+= R7.L \* R6.L\) \(ISS2\);
+ 6a8:	0c c0 b7 e0 	R3 = \(a1 = R6.H \* R7.H\), R2 = \(a0 = R6.L \* R7.L\);
+ 6ac:	0d c0 37 e1 	R5 = \(a1 \+= R6.H \* R7.H\), R4 = \(a0 = R6.L \* R7.L\);
+ 6b0:	0d c0 9d f1 	R7 = \(a1 \+= R3.H \* R5.H\), R6 = \(a0 -= R3.L \* R5.L\);
+ 6b4:	1c c0 3c 2e 	R1 = \(a1 = R7.L \* R4.L\) \(M\), R0 = \(a0 \+= R7.H \* R4.H\);
+ 6b8:	9c c0 1f e9 	R5 = \(a1 = R3.H \* R7.H\) \(M\), R4 = \(a0 \+= R3.L \* R7.L\) \(FU\);
+ 6bc:	0d c1 1a e0 	R1 = \(a1 \+= R3.H \* R2.H\), R0 = \(a0 = R3.L \* R2.L\) \(IS\);
+ 6c0:	0e c0 37 c9 	R5 = \(a1 -= R6.H \* R7.H\), a0 \+= R6.L \* R7.L;
+ 6c4:	1c c0 b7 d0 	R3 = \(a1 = R6.H \* R7.H\) \(M\), a0 -= R6.L \* R7.L;
+ 6c8:	2f c0 81 28 	R3 = A1, R2 = \(a0 \+= R0.L \* R1.L\) \(S2RND\);
+ 6cc:	2d c1 3e e8 	R1 = \(a1 \+= R7.H \* R6.H\), R0 = \(a0 \+= R7.L \* R6.L\) \(ISS2\);
+ 6d0:	0f c4 18 ca 	R5=-R3\(V\);
+ 6d4:	04 c6 2c 06 	R3=PACK\(R4.L,R5.L\);
+ 6d8:	04 c6 26 42 	R1=PACK\(R6.L,R4.H\);
+ 6dc:	04 c6 22 80 	R0=PACK\(R2.H,R4.L\);
+ 6e0:	04 c6 17 ca 	R5=PACK\(R7.H,R2.H\);
+ 6e4:	0d cc 50 c0 	\(R1,R0\) = SEARCH R2\(LE\) \|\| R2=\[P0\+\+\] \|\| NOP;
+ 6e8:	02 90 00 00 
+ 6ec:	0d c4 50 c0 	\(R1,R0\) = SEARCH R2\(LE\);
+ 6f0:	12 cc 02 00 	SAA\(R1:0x0,R3:0x2\)  \|\| R0=\[I0\+\+\] \|\| R2=\[I1\+\+\];
+ 6f4:	00 9c 0a 9c 
+ 6f8:	12 cc 02 20 	SAA\(R1:0x0,R3:0x2\) \(R\) \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\];
+ 6fc:	01 9c 0b 9c 
+ 700:	03 c8 00 18 	mnop \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\];
+ 704:	01 9c 0b 9c 
+ 708:	0c cc 13 0e 	R7.H=R7.L=SIGN\(R2.H\)\*R3.H\+SIGN\(R2.L\)\*R3.L\) \|\| I0\+=M3 \|\| R0=\[I0\];
+ 70c:	6c 9e 00 9d 
+ 710:	01 cc 94 88 	R2=R2\+\|\+R4,R4=R2-\|-R4\(ASR\) \|\| I0\+=M0\(BREV\) \|\| R1=\[I0\];
+ 714:	e0 9e 01 9d 
+ 718:	00 c8 11 06 	a1 = R2.L \* R1.L, a0 = R2.H \* R1.H \|\| R2.H=W\[I2\+\+\] \|\| \[I3\+\+\]=R3;
+ 71c:	52 9c 1b 9e 
+ 720:	01 c8 02 48 	a1 \+= R0.L \* R2.H, a0 \+= R0.L \* R2.L \|\| R2.L=W\[I2\+\+\] \|\| R0=\[I1--\];
+ 724:	32 9c 88 9c 
+ 728:	05 c8 c1 68 	R3.H = \(a1 \+= R0.L \* R1.H\), R3.L = \(a0 \+= R0.L \* R1.L\) \|\| R0=\[P0\+\+\] \|\| R1=\[I0\];
+ 72c:	00 90 01 9d 
+ 730:	04 ce 01 c2 	R1=PACK\(R1.H,R0.H\) \|\| \[I0\+\+\]=R0 \|\| R2.L=W\[I2\+\+\];
+ 734:	00 9e 32 9c 
+ 738:	8b c8 9a 2f 	R6 = \(a0 \+= R3.H \* R2.H\) \(FU\) \|\| I2-=M0 \|\| NOP;
+ 73c:	72 9e 00 00 
diff --git a/gas/testsuite/gas/bfin/vector2.s b/gas/testsuite/gas/bfin/vector2.s
new file mode 100755
index 000000000000..30cca43c1ebe
--- /dev/null
+++ b/gas/testsuite/gas/bfin/vector2.s
@@ -0,0 +1,668 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//14 VECTOR OPERATIONS

+//

+

+//Dreg_hi = Dreg_lo = SIGN ( Dreg_hi ) * Dreg_hi + SIGN ( Dreg_lo ) * Dreg_lo ; /* (b) */

+

+r7.h=r7.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;

+r0.h=r0.l=sign(r1.h)*r2.h+sign(r1.l)*r2.l ;

+r3.h=r3.l=sign(r4.h)*r5.h+sign(r4.l)*r5.l ;

+r6.h=r6.l=sign(r7.h)*r0.h+sign(r7.l)*r0.l ;

+r1.h=r1.l=sign(r2.h)*r3.h+sign(r2.l)*r3.l ;

+r4.h=r4.l=sign(r5.h)*r6.h+sign(r5.l)*r6.l ;

+r7.h=r7.l=sign(r0.h)*r1.h+sign(r0.l)*r1.l ;

+r2.h=r2.l=sign(r3.h)*r4.h+sign(r3.l)*r4.l ;

+

+//Dual 16-Bit Operation

+//Dreg = VIT_MAX ( Dreg , Dreg ) (ASL) ; /* shift history bits left (b) */

+//Dreg = VIT_MAX ( Dreg , Dreg ) (ASR) ; /* shift history bits right (b) */

+//Single 16-Bit Operation

+//Dreg_lo = VIT_MAX ( Dreg ) (ASL) ; /* shift history bits left (b) */

+//Dreg_lo = VIT_MAX ( Dreg ) (ASR) ; /* shift history bits right (b) */

+r5 = vit_max(r3, r2)(asl) ; /* shift left, dual operation */

+r7 = vit_max (r1, r0) (asr) ; /* shift right, dual operation */

+

+r0 = vit_max(r1, r2)(asl) ; /* shift left, dual operation */

+r3 = vit_max (r4, r5) (asr) ; /* shift right, dual operation */

+r6 = vit_max(r7, r0)(asl) ; /* shift left, dual operation */

+r1 = vit_max (r2, r3) (asr) ; /* shift right, dual operation */

+r4 = vit_max(r5, r6)(asl) ; /* shift left, dual operation */

+r7 = vit_max (r0, r1) (asr) ; /* shift right, dual operation */

+r2 = vit_max(r3, r4)(asl) ; /* shift left, dual operation */

+r5 = vit_max (r6, r7) (asr) ; /* shift right, dual operation */

+

+

+r3.l = vit_max (r1)(asl) ; /* shift left, single operation */

+r3.l = vit_max (r1)(asr) ; /* shift right, single operation */

+

+r0.l = vit_max (r1)(asl) ; /* shift left, single operation */

+r2.l = vit_max (r3)(asr) ; /* shift right, single operation */

+r4.l = vit_max (r5)(asl) ; /* shift left, single operation */

+r6.l = vit_max (r7)(asr) ; /* shift right, single operation */

+r1.l = vit_max (r2)(asl) ; /* shift left, single operation */

+r3.l = vit_max (r4)(asr) ; /* shift right, single operation */

+r5.l = vit_max (r6)(asl) ; /* shift left, single operation */

+r7.l = vit_max (r0)(asr) ; /* shift right, single operation */

+

+//Dreg = ABS Dreg (V) ; /* (b) */

+r3 = abs r1 (v) ;

+

+r0 = abs r0 (v) ;

+r0 = abs r1 (v) ;

+r2 = abs r3 (v) ;

+r4 = abs r5 (v) ;

+r6 = abs r7 (v) ;

+r1 = abs r0 (v) ;

+r3 = abs r2 (v) ;

+r5 = abs r4 (v) ;

+r7 = abs r6 (v) ;

+

+//Dual 16-Bit Operations

+//Dreg = Dreg +|+ Dreg (opt_mode_0) ; /* add | add (b) */

+r5=r3 +|+ r4 ; /* dual 16-bit operations, add|add */

+

+r0=r1 +|+ r2 ;

+r3=r4 +|+ r5 ;

+r6=r7 +|+ r0 ;

+r1=r2 +|+ r3 ;

+r4=r3 +|+ r5 ;

+r6=r3 +|+ r7 ;

+

+r0=r1 +|+ r2 (S);

+r3=r4 +|+ r5 (S);

+r6=r7 +|+ r0 (S);

+r1=r2 +|+ r3 (S);

+r4=r3 +|+ r5 (S);

+r6=r3 +|+ r7 (S);

+

+r0=r1 +|+ r2 (CO);

+r3=r4 +|+ r5 (CO);

+r6=r7 +|+ r0 (CO) ;

+r1=r2 +|+ r3 (CO);

+r4=r3 +|+ r5 (CO);

+r6=r3 +|+ r7 (CO);

+

+r0=r1 +|+ r2 (SCO);

+r3=r4 +|+ r5 (SCO);

+r6=r7 +|+ r0 (SCO);

+r1=r2 +|+ r3 (SCO);

+r4=r3 +|+ r5 (SCO);

+r6=r3 +|+ r7 (SCO);

+

+//Dreg = Dreg –|+ Dreg (opt_mode_0) ; /* subtract | add (b) */

+r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */

+

+r0=r1 -|+ r2 ;

+r3=r4 -|+ r5 ;

+r6=r7 -|+ r0 ;

+r1=r2 -|+ r3 ;

+r4=r3 -|+ r5 ;

+r6=r3 -|+ r7 ;

+

+r0=r1 -|+ r2 (S);

+r3=r4 -|+ r5 (S);

+r6=r7 -|+ r0 (S);

+r1=r2 -|+ r3 (S);

+r4=r3 -|+ r5 (S);

+r6=r3 -|+ r7 (S);

+

+r0=r1 -|+ r2 (CO);

+r3=r4 -|+ r5 (CO);

+r6=r7 -|+ r0 (CO) ;

+r1=r2 -|+ r3 (CO);

+r4=r3 -|+ r5 (CO);

+r6=r3 -|+ r7 (CO);

+

+r0=r1 -|+ r2 (SCO);

+r3=r4 -|+ r5 (SCO);

+r6=r7 -|+ r0 (SCO);

+r1=r2 -|+ r3 (SCO);

+r4=r3 -|+ r5 (SCO);

+r6=r3 -|+ r7 (SCO);

+

+

+//Dreg = Dreg +|– Dreg (opt_mode_0) ; /* add | subtract (b) */

+r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */

+

+r0=r1 +|- r2 ;

+r3=r4 +|- r5 ;

+r6=r7 +|- r0 ;

+r1=r2 +|- r3 ;

+r4=r3 +|- r5 ;

+r6=r3 +|- r7 ;

+

+r0=r1 +|- r2 (S);

+r3=r4 +|- r5 (S);

+r6=r7 +|- r0 (S);

+r1=r2 +|- r3 (S);

+r4=r3 +|- r5 (S);

+r6=r3 +|- r7 (S);

+

+r0=r1 +|- r2 (CO);

+r3=r4 +|- r5 (CO);

+r6=r7 +|- r0 (CO) ;

+r1=r2 +|- r3 (CO);

+r4=r3 +|- r5 (CO);

+r6=r3 +|- r7 (CO);

+

+r0=r1 +|- r2 (SCO);

+r3=r4 +|- r5 (SCO);

+r6=r7 +|- r0 (SCO);

+r1=r2 +|- r3 (SCO);

+r4=r3 +|- r5 (SCO);

+r6=r3 +|- r7 (SCO);

+

+//Dreg = Dreg –|– Dreg (opt_mode_0) ; /* subtract | subtract (b) */

+r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */

+

+r0=r1 -|- r2 ;

+r3=r4 -|- r5 ;

+r6=r7 -|- r0 ;

+r1=r2 -|- r3 ;

+r4=r3 -|- r5 ;

+r6=r3 -|- r7 ;

+

+r0=r1 -|- r2 (S);

+r3=r4 -|- r5 (S);

+r6=r7 -|- r0 (S);

+r1=r2 -|- r3 (S);

+r4=r3 -|- r5 (S);

+r6=r3 -|- r7 (S);

+

+r0=r1 -|- r2 (CO);

+r3=r4 -|- r5 (CO);

+r6=r7 -|- r0 (CO) ;

+r1=r2 -|- r3 (CO);

+r4=r3 -|- r5 (CO);

+r6=r3 -|- r7 (CO);

+

+r0=r1 -|- r2 (SCO);

+r3=r4 -|- r5 (SCO);

+r6=r7 -|- r0 (SCO);

+r1=r2 -|- r3 (SCO);

+r4=r3 -|- r5 (SCO);

+r6=r3 -|- r7 (SCO);

+

+//Quad 16-Bit Operations

+//Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */

+r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */

+

+r0=r1 +|+ r2, r7=r1 -|- r2;

+r3=r4 +|+ r5, r6=r4 -|- r5;

+r6=r7 +|+ r0, r5=r7 -|- r0;

+r1=r2 +|+ r3, r4=r2 -|- r3;

+r4=r3 +|+ r5, r3=r3 -|- r5;

+r6=r3 +|+ r7, r2=r3 -|- r7;

+                         

+r0=r1 +|+ r2, r7=r1 -|- r2(S);

+r3=r4 +|+ r5, r6=r4 -|- r5(S);

+r6=r7 +|+ r0, r5=r7 -|- r0(S);

+r1=r2 +|+ r3, r4=r2 -|- r3(S);

+r4=r3 +|+ r5, r3=r3 -|- r5(S);

+r6=r3 +|+ r7, r2=r3 -|- r7(S);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(CO);

+r3=r4 +|+ r5, r6=r4 -|- r5(CO);

+r6=r7 +|+ r0, r5=r7 -|- r0(CO);

+r1=r2 +|+ r3, r4=r2 -|- r3(CO);

+r4=r3 +|+ r5, r3=r3 -|- r5(CO);

+r6=r3 +|+ r7, r2=r3 -|- r7(CO);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(SCO);

+r3=r4 +|+ r5, r6=r4 -|- r5(SCO);

+r6=r7 +|+ r0, r5=r7 -|- r0(SCO);

+r1=r2 +|+ r3, r4=r2 -|- r3(SCO);

+r4=r3 +|+ r5, r3=r3 -|- r5(SCO);

+r6=r3 +|+ r7, r2=r3 -|- r7(SCO);

+                         

+r0=r1 +|+ r2, r7=r1 -|- r2(ASR);

+r3=r4 +|+ r5, r6=r4 -|- r5(ASR);

+r6=r7 +|+ r0, r5=r7 -|- r0(ASR);

+r1=r2 +|+ r3, r4=r2 -|- r3(ASR);

+r4=r3 +|+ r5, r3=r3 -|- r5(ASR);

+r6=r3 +|+ r7, r2=r3 -|- r7(ASR);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(ASL);

+r3=r4 +|+ r5, r6=r4 -|- r5(ASL);

+r6=r7 +|+ r0, r5=r7 -|- r0(ASL);

+r1=r2 +|+ r3, r4=r2 -|- r3(ASL);

+r4=r3 +|+ r5, r3=r3 -|- r5(ASL);

+r6=r3 +|+ r7, r2=r3 -|- r7(ASL);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(S,ASR);

+r3=r4 +|+ r5, r6=r4 -|- r5(S,ASR);

+r6=r7 +|+ r0, r5=r7 -|- r0(S,ASR);

+r1=r2 +|+ r3, r4=r2 -|- r3(S,ASR);

+r4=r3 +|+ r5, r3=r3 -|- r5(S,ASR);

+r6=r3 +|+ r7, r2=r3 -|- r7(S,ASR);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASR);

+r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASR);

+r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASR);

+r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASR);

+r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASR);

+r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASR);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASR);

+r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASR);

+r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASR);

+r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASR);

+r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASR);

+r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASR);

+

+r0=r1 +|+ r2, r7=r1 -|- r2(S,ASL);

+r3=r4 +|+ r5, r6=r4 -|- r5(S,ASL);

+r6=r7 +|+ r0, r5=r7 -|- r0(S,ASL);

+r1=r2 +|+ r3, r4=r2 -|- r3(S,ASL);

+r4=r3 +|+ r5, r3=r3 -|- r5(S,ASL);

+r6=r3 +|+ r7, r2=r3 -|- r7(S,ASL);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(CO,ASL);

+r3=r4 +|+ r5, r6=r4 -|- r5(CO,ASL);

+r6=r7 +|+ r0, r5=r7 -|- r0(CO,ASL);

+r1=r2 +|+ r3, r4=r2 -|- r3(CO,ASL);

+r4=r3 +|+ r5, r3=r3 -|- r5(CO,ASL);

+r6=r3 +|+ r7, r2=r3 -|- r7(CO,ASL);

+                         

+

+r0=r1 +|+ r2, r7=r1 -|- r2(SCO,ASL);

+r3=r4 +|+ r5, r6=r4 -|- r5(SCO,ASL);

+r6=r7 +|+ r0, r5=r7 -|- r0(SCO,ASL);

+r1=r2 +|+ r3, r4=r2 -|- r3(SCO,ASL);

+r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL);

+r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL);

+

+

+//Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */

+r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */

+

+r0=r1 +|- r2, r7=r1 -|+ r2;

+r3=r4 +|- r5, r6=r4 -|+ r5;

+r6=r7 +|- r0, r5=r7 -|+ r0;

+r1=r2 +|- r3, r4=r2 -|+ r3;

+r4=r3 +|- r5, r3=r3 -|+ r5;

+r6=r3 +|- r7, r2=r3 -|+ r7;

+                         

+r0=r1 +|- r2, r7=r1 -|+ r2(S);

+r3=r4 +|- r5, r6=r4 -|+ r5(S);

+r6=r7 +|- r0, r5=r7 -|+ r0(S);

+r1=r2 +|- r3, r4=r2 -|+ r3(S);

+r4=r3 +|- r5, r3=r3 -|+ r5(S);

+r6=r3 +|- r7, r2=r3 -|+ r7(S);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(CO);

+r3=r4 +|- r5, r6=r4 -|+ r5(CO);

+r6=r7 +|- r0, r5=r7 -|+ r0(CO);

+r1=r2 +|- r3, r4=r2 -|+ r3(CO);

+r4=r3 +|- r5, r3=r3 -|+ r5(CO);

+r6=r3 +|- r7, r2=r3 -|+ r7(CO);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(SCO);

+r3=r4 +|- r5, r6=r4 -|+ r5(SCO);

+r6=r7 +|- r0, r5=r7 -|+ r0(SCO);

+r1=r2 +|- r3, r4=r2 -|+ r3(SCO);

+r4=r3 +|- r5, r3=r3 -|+ r5(SCO);

+r6=r3 +|- r7, r2=r3 -|+ r7(SCO);

+                         

+r0=r1 +|- r2, r7=r1 -|+ r2(ASR);

+r3=r4 +|- r5, r6=r4 -|+ r5(ASR);

+r6=r7 +|- r0, r5=r7 -|+ r0(ASR);

+r1=r2 +|- r3, r4=r2 -|+ r3(ASR);

+r4=r3 +|- r5, r3=r3 -|+ r5(ASR);

+r6=r3 +|- r7, r2=r3 -|+ r7(ASR);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(ASL);

+r3=r4 +|- r5, r6=r4 -|+ r5(ASL);

+r6=r7 +|- r0, r5=r7 -|+ r0(ASL);

+r1=r2 +|- r3, r4=r2 -|+ r3(ASL);

+r4=r3 +|- r5, r3=r3 -|+ r5(ASL);

+r6=r3 +|- r7, r2=r3 -|+ r7(ASL);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(S,ASR);

+r3=r4 +|- r5, r6=r4 -|+ r5(S,ASR);

+r6=r7 +|- r0, r5=r7 -|+ r0(S,ASR);

+r1=r2 +|- r3, r4=r2 -|+ r3(S,ASR);

+r4=r3 +|- r5, r3=r3 -|+ r5(S,ASR);

+r6=r3 +|- r7, r2=r3 -|+ r7(S,ASR);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASR);

+r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASR);

+r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASR);

+r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASR);

+r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASR);

+r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASR);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASR);

+r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASR);

+r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASR);

+r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASR);

+r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASR);

+r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASR);

+

+r0=r1 +|- r2, r7=r1 -|+ r2(S,ASL);

+r3=r4 +|- r5, r6=r4 -|+ r5(S,ASL);

+r6=r7 +|- r0, r5=r7 -|+ r0(S,ASL);

+r1=r2 +|- r3, r4=r2 -|+ r3(S,ASL);

+r4=r3 +|- r5, r3=r3 -|+ r5(S,ASL);

+r6=r3 +|- r7, r2=r3 -|+ r7(S,ASL);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(CO,ASL);

+r3=r4 +|- r5, r6=r4 -|+ r5(CO,ASL);

+r6=r7 +|- r0, r5=r7 -|+ r0(CO,ASL);

+r1=r2 +|- r3, r4=r2 -|+ r3(CO,ASL);

+r4=r3 +|- r5, r3=r3 -|+ r5(CO,ASL);

+r6=r3 +|- r7, r2=r3 -|+ r7(CO,ASL);

+                         

+

+r0=r1 +|- r2, r7=r1 -|+ r2(SCO,ASL);

+r3=r4 +|- r5, r6=r4 -|+ r5(SCO,ASL);

+r6=r7 +|- r0, r5=r7 -|+ r0(SCO,ASL);

+r1=r2 +|- r3, r4=r2 -|+ r3(SCO,ASL);

+r4=r3 +|- r5, r3=r3 -|+ r5(SCO,ASL);

+r6=r3 +|- r7, r2=r3 -|+ r7(SCO,ASL);

+

+

+

+//Dual 32-Bit Operations

+//Dreg = Dreg + Dreg, Dreg = Dreg - Dreg (opt_mode_1) ; /* add, subtract; the set of source registers must be the same for each operation (b) */

+r2=r0+r1, r3=r0-r1 ; /* 32-bit operations */

+

+r7=r0+r1, r0=r0-r1 ; /* 32-bit operations */

+r6=r1+r2, r1=r1-r2 ; /* 32-bit operations */

+r5=r2+r3, r2=r2-r3 ; /* 32-bit operations */

+r4=r3+r4, r3=r3-r4 ; /* 32-bit operations */

+r3=r4+r5, r4=r4-r5 ; /* 32-bit operations */

+r2=r5+r6, r5=r5-r6 ; /* 32-bit operations */

+r1=r6+r7, r6=r6-r7 ; /* 32-bit operations */

+r0=r7+r0, r7=r7-r0 ; /* 32-bit operations */

+

+r2=r0+r1, r3=r0-r1(s) ; /* dual 32-bit operations with saturation */

+r7=r0+r1, r0=r0-r1 (s); /* 32-bit operations */

+r6=r1+r2, r1=r1-r2 (s); /* 32-bit operations */

+r5=r2+r3, r2=r2-r3 (s); /* 32-bit operations */

+r4=r3+r4, r3=r3-r4(s) ; /* 32-bit operations */

+r3=r4+r5, r4=r4-r5 (s); /* 32-bit operations */

+r2=r5+r6, r5=r5-r6 (s); /* 32-bit operations */

+r1=r6+r7, r6=r6-r7 (s); /* 32-bit operations */

+r0=r7+r0, r7=r7-r0 (s); /* 32-bit operations */

+

+

+

+//Dual 40-Bit Accumulator Operations

+//Dreg = A1 + A0, Dreg = A1 - A0 (opt_mode_1) ; /* add, subtract Accumulators; subtract A0 from A1 (b) */

+r0=a1+a0, r1=a1-a0 ;

+r2=a1+a0, r3=a1-a0 ;

+r4=a1+a0, r5=a1-a0 ;

+r6=a1+a0, r7=a1-a0 ;

+r1=a1+a0, r0=a1-a0 ;

+r3=a1+a0, r2=a1-a0 ;

+r5=a1+a0, r4=a1-a0 ;

+

+r0=a1+a0, r1=a1-a0 (s);

+r2=a1+a0, r3=a1-a0 (s);

+r4=a1+a0, r5=a1-a0 (s);

+r6=a1+a0, r7=a1-a0 (s);

+r1=a1+a0, r0=a1-a0 (s);

+r3=a1+a0, r2=a1-a0 (s);

+r5=a1+a0, r4=a1-a0 (s);

+

+//Dreg = A0 + A1, Dreg = A0 - A1 (opt_mode_1) ; /* add, subtract Accumulators; subtract A1 from A0 (b) */

+r4=a0+a1, r6=a0-a1(s);

+

+r0=a0+a1, r1=a0-a1 ;

+r2=a0+a1, r3=a0-a1 ;

+r4=a0+a1, r5=a0-a1 ;

+r6=a0+a1, r7=a0-a1 ;

+r1=a0+a1, r0=a0-a1 ;

+r3=a0+a1, r2=a0-a1 ;

+r5=a0+a1, r4=a0-a1 ;

+

+r0=a0+a1, r1=a0-a1 (s);

+r2=a0+a1, r3=a0-a1 (s);

+r4=a0+a1, r5=a0-a1 (s);

+r6=a0+a1, r7=a0-a1 (s);

+r1=a0+a1, r0=a0-a1 (s);

+r3=a0+a1, r2=a0-a1 (s);

+r5=a0+a1, r4=a0-a1 (s);

+

+//Constant Shift Magnitude

+//Dreg = Dreg >>> uimm4 (V) ; /* arithmetic shift right, immediate (b) */

+R0 = R0 >>> 5(V);

+

+R0 = R1 >>> 5(V);

+R2 = R3 >>> 5(V);

+R4 = R5 >>> 5(V);

+R6 = R7 >>> 5(V);

+R1 = R0 >>> 5(V);

+R3 = R2 >>> 5(V);

+R5 = R4 >>> 5(V);

+R7 = R6 >>> 5(V);

+

+

+//Dreg = Dreg << uimm4 (V,S) ; /* arithmetic shift left, immediate with saturation (b) */

+

+R0 = R1 << 5(V,S);

+R2 = R3 << 5(V,S);

+R4 = R5 << 5(V,S);

+R6 = R7 << 5(V,S);

+R1 = R0 << 5(V,S);

+R3 = R2 << 5(V,S);

+R5 = R4 << 5(V,S);

+R7 = R6 << 5(V,S);

+

+//Registered Shift Magnitude

+//Dreg = ASHIFT Dreg BY Dreg_lo (V) ; /* arithmetic shift (b) */

+r2=ashift r7 by r5.l (v) ;

+

+R0 = ASHIFT R1 BY R2.L (V);

+R3 = ASHIFT R4 BY R5.L (V);

+R6 = ASHIFT R7 BY R0.L (V);

+R1 = ASHIFT R2 BY R3.L (V);

+R4 = ASHIFT R5 BY R6.L (V);

+R7 = ASHIFT R0 BY R1.L (V);

+R2 = ASHIFT R3 BY R4.L (V);

+R5 = ASHIFT R6 BY R7.L (V);

+

+

+//Dreg = ASHIFT Dreg BY Dreg_lo (V, S) ; /* arithmetic shift with saturation (b) */

+R0 = ASHIFT R1 BY R2.L (V,S);

+R3 = ASHIFT R4 BY R5.L (V,S);

+R6 = ASHIFT R7 BY R0.L (V,S);

+R1 = ASHIFT R2 BY R3.L (V,S);

+R4 = ASHIFT R5 BY R6.L (V,S);

+R7 = ASHIFT R0 BY R1.L (V,S);

+R2 = ASHIFT R3 BY R4.L (V,S);

+R5 = ASHIFT R6 BY R7.L (V,S);

+

+//Constant Shift Magnitude

+//Dreg = Dreg >> uimm4 (V) ; /* logical shift right, immediate (b) */

+R0 = R1 >> 5(V);

+R2 = R3 >> 5(V);

+R4 = R5 >> 5(V);

+R6 = R7 >> 5(V);

+R1 = R0 >> 5(V);

+R3 = R2 >> 5(V);

+R5 = R4 >> 5(V);

+R7 = R6 >> 5(V);

+

+//Dreg = Dreg << uimm4 (V) ; /* logical shift left, immediate (b) */

+R0 = R1 << 5(V);

+R2 = R3 << 5(V);

+R4 = R5 << 5(V);

+R6 = R7 << 5(V);

+R1 = R0 << 5(V);

+R3 = R2 << 5(V);

+R5 = R4 << 5(V);

+R7 = R6 << 5(V);

+

+

+//Registered Shift Magnitude

+//Dreg = LSHIFT Dreg BY Dreg_lo (V) ; /* logical shift (b) */

+

+R0 = LSHIFT R1 BY R2.L (V);

+R3 = LSHIFT R4 BY R5.L (V);

+R6 = LSHIFT R7 BY R0.L (V);

+R1 = LSHIFT R2 BY R3.L (V);

+R4 = LSHIFT R5 BY R6.L (V);

+R7 = LSHIFT R0 BY R1.L (V);

+R2 = LSHIFT R3 BY R4.L (V);

+R5 = LSHIFT R6 BY R7.L (V);

+

+//Dreg = MAX ( Dreg , Dreg ) (V) ; /* dual 16-bit operations (b) */

+r7 = max (r1, r0) (v) ;

+

+R0 = MAX (R1, R2) (V);

+R3 = MAX (R4, R5) (V);

+R6 = MAX (R7, R0) (V);

+R1 = MAX (R2, R3) (V);

+R4 = MAX (R5, R6) (V);

+R7 = MAX (R0, R1) (V);

+R2 = MAX (R3, R4) (V);

+R5 = MAX (R6, R7) (V);

+

+//Dreg = MIN ( Dreg , Dreg ) (V) ; /* dual 16-bit operation (b) */

+R0 = MIN (R1, R2) (V);

+R3 = MIN (R4, R5) (V);

+R6 = MIN (R7, R0) (V);

+R1 = MIN (R2, R3) (V);

+R4 = MIN (R5, R6) (V);

+R7 = MIN (R0, R1) (V);

+R2 = MIN (R3, R4) (V);

+R5 = MIN (R6, R7) (V);

+

+r2.h=r7.l*r6.h, r2.l=r7.h*r6.h ;

+/* simultaneous MAC0 and MAC1 execution, 16-bit results. Both

+results are signed fractions. */

+r4.l=r1.l*r0.l, r4.h=r1.h*r0.h ;

+/* same as above. MAC order is arbitrary. */

+r0.h=r3.h*r2.l (m), r0.l=r3.l*r2.l ;

+

+a1=r2.l*r3.h, a0=r2.h*r3.h ;

+/* both multiply signed fractions into separate Accumulators */

+a0=r1.l*r0.l, a1+=r1.h*r0.h ;

+/* same as above, but sum result into A1. MAC order is arbitrary.

+*/

+a1+=r3.h*r3.l, a0-=r3.h*r3.h ;

+/* sum product into A1, subtract product from A0 */

+a1=r3.h*r2.l (m), a0+=r3.l*r2.l ;

+/* MAC1 multiplies a signed fraction in r3.h by an unsigned fraction

+in r2.l. MAC0 multiplies two signed fractions. */

+a1=r7.h*r4.h (m), a0+=r7.l*r4.l (fu) ;

+/* MAC1 multiplies signed fraction by unsigned fraction. MAC0

+multiplies and accumulates two unsigned fractions. */

+a1+=r3.h*r2.h, a0=r3.l*r2.l (is) ;

+/* both MACs perform signed integer multiplication */

+a1=r6.h*r7.h, a0+=r6.l*r7.l (w32) ;

+/* both MACs multiply signed fractions, sign extended, and saturate

+both Accumulators at bit 31 */

+r2.h=(a1=r7.l*r6.h), r2.l=(a0=r7.h*r6.h) ; /* simultaneous MAC0

+and MAC1 execution, both are signed fractions, both products load

+into the Accumulators,MAC1 into half-word registers. */

+r4.l=(a0=r1.l*r0.l), r4.h=(a1+=r1.h*r0.h) ; /* same as above,

+but sum result into A1. ; MAC order is arbitrary. */

+r7.h=(a1+=r6.h*r5.l), r7.l=(a0=r6.h*r5.h) ; /* sum into A1,

+subtract into A0 */

+r0.h=(a1=r7.h*r4.l) (m), r0.l=(a0+=r7.l*r4.l) ; /* MAC1 multiplies

+a signed fraction by an unsigned fraction. MAC0 multiplies

+two signed fractions. */

+r5.h=(a1=r3.h*r2.h) (m), r5.l=(a0+=r3.l*r2.l) (fu) ; /* MAC1

+multiplies signed fraction by unsigned fraction. MAC0 multiplies

+two unsigned fractions. */

+r0.h=(a1+=r3.h*r2.h), r0.l=(a0=r3.l*r2.l) (is) ; /* both MACs

+perform signed integer multiplication. */

+r5.h=(a1=r2.h*r1.h), a0+=r2.l*r1.l ; /* both MACs multiply

+signed fractions. MAC0 does not copy the accum result. */

+r3.h=(a1=r2.h*r1.h) (m), a0=r2.l*r1.l ; /* MAC1 multiplies

+signed fraction by unsigned fraction and uses all 40 bits of A1.

+MAC0 multiplies two signed fractions. */

+r3.h=a1, r3.l=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 copies Accumulator

+to register half. MAC0 multiplies signed fractions. Both

+scale the result and round on the way to the destination register.

+*/

+r0.l=(a0+=r7.l*r6.l), r0.h=(a1+=r7.h*r6.h) (iss2) ; /* both

+MACs process signed integer the way to the destination half-registers.

+*/

+r3=(a1=r6.h*r7.h), r2=(a0=r6.l*r7.l) ; /* simultaneous MAC0 and

+MAC1 execution, both are signed fractions, both products load

+into the Accumulators */

+r4=(a0=r6.l*r7.l), r5=(a1+=r6.h*r7.h) ; /* same as above, but

+sum result into A1. MAC order is arbitrary. */

+r7=(a1+=r3.h*r5.h), r6=(a0-=r3.l*r5.l) ; /* sum into A1, subtract

+into A0 */

+r1=(a1=r7.l*r4.l) (m), r0=(a0+=r7.h*r4.h) ; /* MAC1 multiplies

+a signed fraction by an unsigned fraction. MAC0 multiplies two

+signed fractions. */

+r5=(a1=r3.h*r7.h) (m), r4=(a0+=r3.l*r7.l) (fu) ; /* MAC1 multiplies

+signed fraction by unsigned fraction. MAC0 multiplies two

+unsigned fractions. */

+r1=(a1+=r3.h*r2.h), r0=(a0=r3.l*r2.l) (is) ; /* both MACs perform

+signed integer multiplication */

+r5=(a1-=r6.h*r7.h), a0+=r6.l*r7.l ; /* both MACs multiply

+signed fractions. MAC0 does not copy the accum result */

+r3=(a1=r6.h*r7.h) (m), a0-=r6.l*r7.l ; /* MAC1 multiplies

+signed fraction by unsigned fraction and uses all 40 bits of A1.

+MAC0 multiplies two signed fractions. */

+r3=a1, r2=(a0+=r0.l*r1.l) (s2rnd) ; /* MAC1 moves Accumulator

+to register. MAC0 multiplies signed fractions. Both scale the

+result and round on the way to the destination register. */

+r0=(a0+=r7.l*r6.l), r1=(a1+=r7.h*r6.h) (iss2) ; /* both MACs

+process signed integer operands and scale the result on the way

+to the destination registers. */

+

+r5 =-r3 (v) ; /* R5.H becomes the negative of R3.H and R5.L

+becomes the negative of R3.L If r3 = 0x0004 7FFF the result is r5

+= 0xFFFC 8001 */

+

+r3=pack(r4.l, r5.l) ; /* pack low / low half-words */

+r1=pack(r6.l, r4.h) ; /* pack low / high half-words */

+r0=pack(r2.h, r4.l) ; /* pack high / low half-words */

+r5=pack(r7.h, r2.h) ; /* pack high / high half-words */

+

+(r1,r0) = SEARCH R2 (LE) || R2=[P0++];

+/* search for the last minimum in all but the

+last element of the array */

+(r1,r0) = SEARCH R2 (LE);

+

+saa (r1:0, r3:2) || r0=[i0++] || r2=[i1++] ;

+saa (r1:0, r3:2)(r) || r1=[i0++] || r3=[i1++] ;

+mnop || r1 = [i0++] || r3 = [i1++] ;

+r7.h=r7.l=sign(r2.h)*r3.h + sign(r2.l)*r3.l || i0+=m3 || r0=[i0]

+;

+

+/* Add/subtract two vector values while incrementing an Ireg and

+loading a data register. */

+R2 = R2 +|+ R4, R4 = R2 -|- R4 (ASR) || I0 += M0 (BREV) || R1 = [I0] ;

+/* Multiply and accumulate to Accumulator while loading a data

+register and storing a data register using an Ireg pointer. */

+A1=R2.L*R1.L, A0=R2.H*R1.H || R2.H=W[I2++] || [I3++]=R3 ;

+/* Multiply and accumulate while loading two data registers. One

+load uses an Ireg pointer. */

+A1+=R0.L*R2.H,A0+=R0.L*R2.L || R2.L=W[I2++] || R0=[I1--] ;

+R3.H=(A1+=R0.L*R1.H), R3.L=(A0+=R0.L*R1.L) || R0=[P0++] || R1=[I0] ;

+/* Pack two vector values while storing a data register using an

+Ireg pointer and loading another data register. */

+R1=PACK(R1.H,R0.H) || [I0++]=R0 || R2.L=W[I2++] ;

+

+/* Multiply-Accumulate to a Data register while incrementing an

+Ireg. */

+r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 ;

+/* which the assembler expands into:

+r6=(a0+=r3.h*r2.h)(fu) || i2-=m0 || nop ; */

diff --git a/gas/testsuite/gas/bfin/video.d b/gas/testsuite/gas/bfin/video.d
new file mode 100644
index 000000000000..7f911d1c11ef
--- /dev/null
+++ b/gas/testsuite/gas/bfin/video.d
@@ -0,0 +1,56 @@
+#objdump: -dr
+#name: video
+.*: +file format .*
+Disassembly of section .text:
+
+00000000 <align>:
+   0:	0d c6 15 0e 	R7=ALIGN8\(R5,R2\);
+   4:	0d c6 08 4a 	R5=ALIGN16\(R0,R1\);
+   8:	0d c6 05 84 	R2=ALIGN24\(R5,R0\);
+
+0000000c <disalgnexcpt>:
+   c:	12 c4 00 c0 	DISALGNEXCPT;
+
+00000010 <byteop3p>:
+  10:	17 c4 02 0a 	R5=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\);
+  14:	37 c4 02 00 	R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\);
+  18:	17 c4 02 22 	R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\);
+  1c:	37 c4 02 24 	R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\);
+
+00000020 <dual16>:
+  20:	0c c4 [4-7][[:xdigit:]] 45 	R5=A1.L\+A1.H,R2=A0.L\+A0.H;
+
+00000024 <byteop16p>:
+  24:	15 c4 82 06 	\(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) ;
+  28:	15 c4 82 21 	\(R6,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\);
+
+0000002c <byteop1p>:
+  2c:	14 c4 02 0e 	R7=BYTEOP1P\(R1:0x0,R3:0x2\);
+  30:	14 c4 02 44 	R2=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\);
+  34:	14 c4 02 26 	R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\);
+  38:	14 c4 02 6e 	R7=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\);
+
+0000003c <byteop2p>:
+  3c:	16 c4 02 00 	R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\);
+  40:	36 c4 02 02 	R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\);
+  44:	16 c4 02 44 	R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\);
+  48:	36 c4 02 46 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\);
+  4c:	16 c4 02 28 	R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\);
+  50:	36 c4 02 2a 	R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\);
+  54:	16 c4 02 6c 	R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\);
+  58:	36 c4 02 6e 	R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\);
+
+0000005c <bytepack>:
+  5c:	18 c4 03 0a 	R5=BYTEPACK\(R0,R3\);
+
+00000060 <byteop16m>:
+  60:	15 c4 82 45 	\(R6,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) ;
+  64:	15 c4 02 6a 	\(R0,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\);
+
+00000068 <saa>:
+  68:	12 c4 02 00 	SAA\(R1:0x0,R3:0x2\) ;
+  6c:	12 c4 02 20 	SAA\(R1:0x0,R3:0x2\) \(R\);
+
+00000070 <byteunpack>:
+  70:	18 c4 c0 45 	\(R7,R2\) = BYTEUNPACK R1:0x0 ;
+  74:	18 c4 90 69 	\(R6,R4\) = BYTEUNPACK R3:0x2 \(R\);
diff --git a/gas/testsuite/gas/bfin/video.s b/gas/testsuite/gas/bfin/video.s
new file mode 100644
index 000000000000..b53eb6c231e7
--- /dev/null
+++ b/gas/testsuite/gas/bfin/video.s
@@ -0,0 +1,74 @@
+	.text
+	.global align
+align:
+	R7 = Align8 (r5, r2);
+	R5 = ALIGN16 (R0, R1);
+	r2 = ALIGN24 (r5, r0);
+
+	.global disalgnexcpt
+disalgnexcpt:
+	DISAlgnExcpt;
+
+	.text
+	.global byteop3p
+byteop3p:
+	R5 = Byteop3p (r1:0, r3:2) (lO);
+	R0 = BYTEOP3P (R1:0, R3:2) (HI);
+	R1 = byteop3p (r1:0, r3:2) (LO, r);
+	r2 = ByteOp3P (r1:0, R3:2) (hi, R);
+
+	.text
+	.global dual16
+dual16:
+	R5 = A1.l + A1.h, R2 = a0.l + a0.h;
+
+	.text
+	.global byteop16p
+byteop16p:
+	(r2, r3) = BYTEOP16P (R1:0, R3:2);
+	(R6, R0) = byteop16p (r1:0, r3:2) (r);
+
+	.text
+	.global byteop1p
+byteop1p:
+	R7 = BYTEOP1P (R1:0, R3:2);
+	r2 = byteop1p (r1:0, r3:2) (t);
+	R3 = ByteOp1P (r1:0, R3:2) (R);
+	r7 = byteOP1P (R1:0, r3:2) (T, r);
+
+	.text
+	.global byteop2p
+byteop2p:
+	R0 = BYTEOP2P (R1:0, R3:2) (RNDL);
+	r1 = byteop2p (r1:0, r3:2) (rndh);
+	R2 = Byteop2p (R1:0, R3:2) (tL);
+	R3 = Byteop2p (r1:0, r3:2) (TH);
+	r4 = ByTEOP2P (r1:0, R3:2) (Rndl, R);
+	R5 = byTeOp2p (R1:0, r3:2) (rndH, r);
+	r6 = BYTEop2p (r1:0, r3:2) (tl, R);
+	R7 = byteop2p (r1:0, R3:2) (TH, r);
+
+	.text
+	.global bytepack
+bytepack:
+	R5 = BytePack (R0, R3);
+
+	.text
+	.global byteop16m
+byteop16m:
+	(R6, R2) = ByteOp16M (r1:0, r3:2);
+	(r0, r5) = byteop16m (R1:0, R3:2) (r);
+
+	.text
+	.global saa
+saa:
+	saa(r1:0, r3:2);
+	SAA (R1:0, R3:2) (r);
+
+	.text
+	.global byteunpack
+byteunpack:
+	(R7, R2) = byteunpack R1:0;
+	(R6, R4) = BYTEUNPACK r3:2 (R);
+
+
diff --git a/gas/testsuite/gas/bfin/video2.d b/gas/testsuite/gas/bfin/video2.d
new file mode 100644
index 000000000000..90be24b3b5f3
--- /dev/null
+++ b/gas/testsuite/gas/bfin/video2.d
@@ -0,0 +1,148 @@
+#objdump: -dr
+#name: video2
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	0d c6 00 00 	R0=ALIGN8\(R0,R0\);
+   4:	0d c6 08 00 	R0=ALIGN8\(R0,R1\);
+   8:	0d c6 01 00 	R0=ALIGN8\(R1,R0\);
+   c:	0d c6 09 00 	R0=ALIGN8\(R1,R1\);
+  10:	0d c6 11 00 	R0=ALIGN8\(R1,R2\);
+  14:	0d c6 2c 06 	R3=ALIGN8\(R4,R5\);
+  18:	0d c6 07 0c 	R6=ALIGN8\(R7,R0\);
+  1c:	0d c6 1a 02 	R1=ALIGN8\(R2,R3\);
+  20:	0d c6 35 08 	R4=ALIGN8\(R5,R6\);
+  24:	0d c6 08 0e 	R7=ALIGN8\(R0,R1\);
+  28:	0d c6 23 04 	R2=ALIGN8\(R3,R4\);
+  2c:	0d c6 3e 0a 	R5=ALIGN8\(R6,R7\);
+  30:	0d c6 00 40 	R0=ALIGN16\(R0,R0\);
+  34:	0d c6 08 40 	R0=ALIGN16\(R0,R1\);
+  38:	0d c6 01 40 	R0=ALIGN16\(R1,R0\);
+  3c:	0d c6 09 40 	R0=ALIGN16\(R1,R1\);
+  40:	0d c6 11 40 	R0=ALIGN16\(R1,R2\);
+  44:	0d c6 2c 46 	R3=ALIGN16\(R4,R5\);
+  48:	0d c6 07 4c 	R6=ALIGN16\(R7,R0\);
+  4c:	0d c6 1a 42 	R1=ALIGN16\(R2,R3\);
+  50:	0d c6 35 48 	R4=ALIGN16\(R5,R6\);
+  54:	0d c6 08 4e 	R7=ALIGN16\(R0,R1\);
+  58:	0d c6 23 44 	R2=ALIGN16\(R3,R4\);
+  5c:	0d c6 3e 4a 	R5=ALIGN16\(R6,R7\);
+  60:	0d c6 00 80 	R0=ALIGN24\(R0,R0\);
+  64:	0d c6 08 80 	R0=ALIGN24\(R0,R1\);
+  68:	0d c6 01 80 	R0=ALIGN24\(R1,R0\);
+  6c:	0d c6 09 80 	R0=ALIGN24\(R1,R1\);
+  70:	0d c6 11 80 	R0=ALIGN24\(R1,R2\);
+  74:	0d c6 2c 86 	R3=ALIGN24\(R4,R5\);
+  78:	0d c6 07 8c 	R6=ALIGN24\(R7,R0\);
+  7c:	0d c6 1a 82 	R1=ALIGN24\(R2,R3\);
+  80:	0d c6 35 88 	R4=ALIGN24\(R5,R6\);
+  84:	0d c6 08 8e 	R7=ALIGN24\(R0,R1\);
+  88:	0d c6 23 84 	R2=ALIGN24\(R3,R4\);
+  8c:	0d c6 3e 8a 	R5=ALIGN24\(R6,R7\);
+  90:	12 c4 00 c0 	DISALGNEXCPT;
+  94:	17 c4 02 00 	R0=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO\);
+  98:	37 c4 02 02 	R1=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI\);
+  9c:	17 c4 02 24 	R2=BYTEOP3P\(R1:0x0,R3:0x2\)\(LO, R\);
+  a0:	37 c4 02 26 	R3=BYTEOP3P\(R1:0x0,R3:0x2\)\(HI, R\);
+  a4:	17 c4 10 08 	R4=BYTEOP3P\(R3:0x2,R1:0x0\)\(LO\);
+  a8:	37 c4 10 0a 	R5=BYTEOP3P\(R3:0x2,R1:0x0\)\(HI\);
+  ac:	17 c4 10 2c 	R6=BYTEOP3P\(R3:0x2,R1:0x0\)\(LO, R\);
+  b0:	37 c4 10 2e 	R7=BYTEOP3P\(R3:0x2,R1:0x0\)\(HI, R\);
+  b4:	0c c4 [0-3][[:xdigit:]] 40 	R0=A1.L\+A1.H,R0=A0.L\+A0.H;
+  b8:	0c c4 [0-3][[:xdigit:]] 42 	R0=A1.L\+A1.H,R1=A0.L\+A0.H;
+  bc:	0c c4 [8|9|a|b][[:xdigit:]] 46 	R2=A1.L\+A1.H,R3=A0.L\+A0.H;
+  c0:	0c c4 [0-3][[:xdigit:]] 4b 	R4=A1.L\+A1.H,R5=A0.L\+A0.H;
+  c4:	0c c4 [8|9|a|b][[:xdigit:]] 4f 	R6=A1.L\+A1.H,R7=A0.L\+A0.H;
+  c8:	15 c4 d0 01 	\(R7,R0\)=BYTEOP16P\(R3:0x2,R1:0x0\) ;
+  cc:	15 c4 50 04 	\(R1,R2\)=BYTEOP16P\(R3:0x2,R1:0x0\) ;
+  d0:	15 c4 10 02 	\(R0,R1\)=BYTEOP16P\(R3:0x2,R1:0x0\) ;
+  d4:	15 c4 90 06 	\(R2,R3\)=BYTEOP16P\(R3:0x2,R1:0x0\) ;
+  d8:	15 c4 c2 01 	\(R7,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) ;
+  dc:	15 c4 42 04 	\(R1,R2\)=BYTEOP16P\(R1:0x0,R3:0x2\) ;
+  e0:	15 c4 02 02 	\(R0,R1\)=BYTEOP16P\(R1:0x0,R3:0x2\) ;
+  e4:	15 c4 82 06 	\(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) ;
+  e8:	15 c4 d0 21 	\(R7,R0\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\);
+  ec:	15 c4 50 24 	\(R1,R2\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\);
+  f0:	15 c4 10 22 	\(R0,R1\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\);
+  f4:	15 c4 90 26 	\(R2,R3\)=BYTEOP16P\(R3:0x2,R1:0x0\) \(R\);
+  f8:	15 c4 c2 21 	\(R7,R0\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\);
+  fc:	15 c4 42 24 	\(R1,R2\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\);
+ 100:	15 c4 02 22 	\(R0,R1\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\);
+ 104:	15 c4 82 26 	\(R2,R3\)=BYTEOP16P\(R1:0x0,R3:0x2\) \(R\);
+ 108:	14 c4 02 06 	R3=BYTEOP1P\(R1:0x0,R3:0x2\);
+ 10c:	14 c4 02 26 	R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(R\);
+ 110:	14 c4 02 46 	R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(T\);
+ 114:	14 c4 02 66 	R3=BYTEOP1P\(R1:0x0,R3:0x2\)\(T, R\);
+ 118:	14 c4 10 00 	R0=BYTEOP1P\(R3:0x2,R1:0x0\);
+ 11c:	14 c4 10 22 	R1=BYTEOP1P\(R3:0x2,R1:0x0\)\(R\);
+ 120:	14 c4 10 44 	R2=BYTEOP1P\(R3:0x2,R1:0x0\)\(T\);
+ 124:	14 c4 10 66 	R3=BYTEOP1P\(R3:0x2,R1:0x0\)\(T, R\);
+ 128:	16 c4 02 06 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\);
+ 12c:	36 c4 02 06 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\);
+ 130:	16 c4 02 46 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\);
+ 134:	36 c4 02 46 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\);
+ 138:	16 c4 02 26 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\);
+ 13c:	36 c4 02 26 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\);
+ 140:	16 c4 02 66 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\);
+ 144:	36 c4 02 66 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\);
+ 148:	16 c4 02 00 	R0=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL\);
+ 14c:	36 c4 02 02 	R1=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH\);
+ 150:	16 c4 02 44 	R2=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL\);
+ 154:	36 c4 02 46 	R3=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH\);
+ 158:	16 c4 02 28 	R4=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDL, R\);
+ 15c:	36 c4 02 2a 	R5=BYTEOP2P\(R1:0x0,R3:0x2\)\(RNDH, R\);
+ 160:	16 c4 02 6c 	R6=BYTEOP2P\(R1:0x0,R3:0x2\)\(TL, R\);
+ 164:	36 c4 02 6e 	R7=BYTEOP2P\(R1:0x0,R3:0x2\)\(TH, R\);
+ 168:	16 c4 12 00 	R0=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDL\);
+ 16c:	36 c4 12 02 	R1=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDH\);
+ 170:	16 c4 12 44 	R2=BYTEOP2P\(R3:0x2,R3:0x2\)\(TL\);
+ 174:	36 c4 12 46 	R3=BYTEOP2P\(R3:0x2,R3:0x2\)\(TH\);
+ 178:	16 c4 12 28 	R4=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDL, R\);
+ 17c:	36 c4 12 2a 	R5=BYTEOP2P\(R3:0x2,R3:0x2\)\(RNDH, R\);
+ 180:	16 c4 12 6c 	R6=BYTEOP2P\(R3:0x2,R3:0x2\)\(TL, R\);
+ 184:	36 c4 12 6e 	R7=BYTEOP2P\(R3:0x2,R3:0x2\)\(TH, R\);
+ 188:	18 c4 00 00 	R0=BYTEPACK\(R0,R0\);
+ 18c:	18 c4 13 02 	R1=BYTEPACK\(R2,R3\);
+ 190:	18 c4 2e 08 	R4=BYTEPACK\(R5,R6\);
+ 194:	18 c4 01 0e 	R7=BYTEPACK\(R0,R1\);
+ 198:	18 c4 1c 04 	R2=BYTEPACK\(R3,R4\);
+ 19c:	18 c4 37 0a 	R5=BYTEPACK\(R6,R7\);
+ 1a0:	15 c4 50 44 	\(R1,R2\)=BYTEOP16M\(R3:0x2,R1:0x0\) ;
+ 1a4:	15 c4 50 64 	\(R1,R2\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\);
+ 1a8:	15 c4 10 42 	\(R0,R1\)=BYTEOP16M\(R3:0x2,R1:0x0\) ;
+ 1ac:	15 c4 90 66 	\(R2,R3\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\);
+ 1b0:	15 c4 d0 4a 	\(R3,R5\)=BYTEOP16M\(R3:0x2,R1:0x0\) ;
+ 1b4:	15 c4 90 6f 	\(R6,R7\)=BYTEOP16M\(R3:0x2,R1:0x0\) \(R\);
+ 1b8:	15 c4 40 44 	\(R1,R2\)=BYTEOP16M\(R1:0x0,R1:0x0\) ;
+ 1bc:	15 c4 40 64 	\(R1,R2\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\);
+ 1c0:	15 c4 00 42 	\(R0,R1\)=BYTEOP16M\(R1:0x0,R1:0x0\) ;
+ 1c4:	15 c4 80 66 	\(R2,R3\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\);
+ 1c8:	15 c4 c0 4a 	\(R3,R5\)=BYTEOP16M\(R1:0x0,R1:0x0\) ;
+ 1cc:	15 c4 80 6f 	\(R6,R7\)=BYTEOP16M\(R1:0x0,R1:0x0\) \(R\);
+ 1d0:	15 c4 42 44 	\(R1,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) ;
+ 1d4:	15 c4 42 64 	\(R1,R2\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\);
+ 1d8:	15 c4 02 42 	\(R0,R1\)=BYTEOP16M\(R1:0x0,R3:0x2\) ;
+ 1dc:	15 c4 82 66 	\(R2,R3\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\);
+ 1e0:	15 c4 c2 4a 	\(R3,R5\)=BYTEOP16M\(R1:0x0,R3:0x2\) ;
+ 1e4:	15 c4 82 6f 	\(R6,R7\)=BYTEOP16M\(R1:0x0,R3:0x2\) \(R\);
+ 1e8:	15 c4 52 44 	\(R1,R2\)=BYTEOP16M\(R3:0x2,R3:0x2\) ;
+ 1ec:	15 c4 52 64 	\(R1,R2\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\);
+ 1f0:	15 c4 12 42 	\(R0,R1\)=BYTEOP16M\(R3:0x2,R3:0x2\) ;
+ 1f4:	15 c4 92 66 	\(R2,R3\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\);
+ 1f8:	15 c4 d2 4a 	\(R3,R5\)=BYTEOP16M\(R3:0x2,R3:0x2\) ;
+ 1fc:	15 c4 92 6f 	\(R6,R7\)=BYTEOP16M\(R3:0x2,R3:0x2\) \(R\);
+ 200:	12 cc 02 00 	SAA\(R1:0x0,R3:0x2\)  \|\| R0=\[I0\+\+\] \|\| R2=\[I1\+\+\];
+ 204:	00 9c 0a 9c 
+ 208:	12 cc 02 20 	SAA\(R1:0x0,R3:0x2\) \(R\) \|\| R1=\[I0\+\+\] \|\| R3=\[I1\+\+\];
+ 20c:	01 9c 0b 9c 
+ 210:	12 c4 02 00 	SAA\(R1:0x0,R3:0x2\) ;
+ 214:	18 c4 80 4b 	\(R6,R5\) = BYTEUNPACK R1:0x0 ;
+ 218:	18 c4 80 6b 	\(R6,R5\) = BYTEUNPACK R1:0x0 \(R\);
+ 21c:	18 c4 90 4b 	\(R6,R5\) = BYTEUNPACK R3:0x2 ;
+ 220:	18 c4 90 6b 	\(R6,R5\) = BYTEUNPACK R3:0x2 \(R\);
+ 224:	18 c4 00 42 	\(R0,R1\) = BYTEUNPACK R1:0x0 ;
+ 228:	18 c4 80 66 	\(R2,R3\) = BYTEUNPACK R1:0x0 \(R\);
+ 22c:	18 c4 10 4b 	\(R4,R5\) = BYTEUNPACK R3:0x2 ;
+ 230:	18 c4 90 6f 	\(R6,R7\) = BYTEUNPACK R3:0x2 \(R\);
diff --git a/gas/testsuite/gas/bfin/video2.s b/gas/testsuite/gas/bfin/video2.s
new file mode 100755
index 000000000000..16b0ff11730d
--- /dev/null
+++ b/gas/testsuite/gas/bfin/video2.s
@@ -0,0 +1,220 @@
+

+.EXTERN MY_LABEL2;

+.section .text;

+

+//

+//13 VIDEO PIXEL OPERATIONS

+//

+

+//Dreg = ALIGN8 ( Dreg, Dreg ) ; /* overlay 1 byte (b) */

+R0 = ALIGN8(R0, R0);

+R0 = ALIGN8(R0, R1);

+R0 = ALIGN8(R1, R0);

+R0 = ALIGN8(R1, R1);

+R0 = ALIGN8(R1, R2);

+R3 = ALIGN8(R4, R5);

+R6 = ALIGN8(R7, R0);

+R1 = ALIGN8(R2, R3);

+R4 = ALIGN8(R5, R6);

+R7 = ALIGN8(R0, R1);

+R2 = ALIGN8(R3, R4);

+R5 = ALIGN8(R6, R7);

+

+//Dreg = ALIGN16 ( Dreg, Dreg ) ; /* overlay 2 bytes (b) */

+R0 = ALIGN16(R0, R0);

+R0 = ALIGN16(R0, R1);

+R0 = ALIGN16(R1, R0);

+R0 = ALIGN16(R1, R1);

+R0 = ALIGN16(R1, R2);

+R3 = ALIGN16(R4, R5);

+R6 = ALIGN16(R7, R0);

+R1 = ALIGN16(R2, R3);

+R4 = ALIGN16(R5, R6);

+R7 = ALIGN16(R0, R1);

+R2 = ALIGN16(R3, R4);

+R5 = ALIGN16(R6, R7);

+

+//Dreg = ALIGN24 ( Dreg, Dreg ) ; /* overlay 3 bytes (b) */

+R0 = ALIGN24(R0, R0);

+R0 = ALIGN24(R0, R1);

+R0 = ALIGN24(R1, R0);

+R0 = ALIGN24(R1, R1);

+R0 = ALIGN24(R1, R2);

+R3 = ALIGN24(R4, R5);

+R6 = ALIGN24(R7, R0);

+R1 = ALIGN24(R2, R3);

+R4 = ALIGN24(R5, R6);

+R7 = ALIGN24(R0, R1);

+R2 = ALIGN24(R3, R4);

+R5 = ALIGN24(R6, R7);

+

+DISALGNEXCPT ; /* (b) */

+

+/* forward byte order operands */

+//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO) ; /* sum into low bytes (b) */

+//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI) ; /* sum into high bytes (b) */

+/* reverse byte order operands */

+//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (LO, R) ; /* sum into low bytes (b) */

+//Dreg = BYTEOP3P (Dreg_pair, Dreg_pair) (HI, R) ; /* sum into high bytes (b) */

+

+r0 = byteop3p (r1:0, r3:2) (lo) ;

+r1 = byteop3p (r1:0, r3:2) (hi) ;

+r2 = byteop3p (r1:0, r3:2) (lo, r) ;

+r3 = byteop3p (r1:0, r3:2) (hi, r) ;

+r4 = byteop3p (r3:2, r1:0) (lo) ;

+r5 = byteop3p (r3:2, r1:0) (hi) ;

+r6 = byteop3p (r3:2, r1:0) (lo, r) ;

+r7 = byteop3p (r3:2, r1:0) (hi, r) ;

+

+//Dreg = A1.L + A1.H, Dreg = A0.L + A0.H ; /* (b) */

+

+R0 = A1.L + A1.H, R0= A0.L + A0.H ;

+R0 = A1.L + A1.H, R1= A0.L + A0.H ;

+R2 = A1.L + A1.H, R3= A0.L + A0.H ;

+R4 = A1.L + A1.H, R5= A0.L + A0.H ;

+R6 = A1.L + A1.H, R7= A0.L + A0.H ;

+

+/* forward byte order operands */

+//( Dreg, Dreg ) = BYTEOP16P ( Dreg_pair, Dreg_pair ) ; /* (b) */

+(r7,r0) = BYTEOP16P ( r3:2,r1:0 ) ;

+(r1,r2) = byteop16p (r3:2,r1:0) ;

+(r0,r1) = BYTEOP16P ( r3:2,r1:0 ) ;

+(r2,r3) = byteop16p (r3:2,r1:0) ;

+(r7,r0) = BYTEOP16P (r1:0, r3:2) ;

+(r1,r2) = byteop16p (r1:0,r3:2) ;

+(r0,r1) = BYTEOP16P (r1:0, r3:2) ;

+(r2,r3) = byteop16p (r1:0,r3:2) ;

+

+/* reverse byte order operands */

+//( Dreg, Dreg ) = BYTEOP16P ( Dreg_pair, Dreg_pair ) (R); /* (b) */

+(r7,r0) = BYTEOP16P ( r3:2,r1:0 )(r) ;

+(r1,r2) = byteop16p (r3:2,r1:0)(r) ;

+(r0,r1) = BYTEOP16P ( r3:2,r1:0 )(r) ;

+(r2,r3) = byteop16p (r3:2,r1:0)(r) ;

+(r7,r0) = BYTEOP16P (r1:0, r3:2)(r) ;

+(r1,r2) = byteop16p (r1:0,r3:2)(r) ;

+(r0,r1) = BYTEOP16P (r1:0, r3:2)(r) ;

+(r2,r3) = byteop16p (r1:0,r3:2)(r) ;

+

+/* forward byte order operands */

+//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) ; /* (b) */

+//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T) ; /* truncated (b)*/

+/* reverse byte order operands */

+//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (R) ; /* (b) */

+//Dreg = BYTEOP1P (Dreg_pair, Dreg_pair) (T, R) ; /* truncated (b) */				                

+

+r3 = byteop1p (r1:0, r3:2) ;

+r3 = byteop1p (r1:0, r3:2) (r) ;

+r3 = byteop1p (r1:0, r3:2) (t) ;

+r3 = byteop1p (r1:0, r3:2) (t,r) ;

+

+r0 = byteop1p (r3:2,r1:0);

+r1 = byteop1p (r3:2,r1:0)(r) ;

+r2 = byteop1p (r3:2,r1:0)(t) ;

+r3 = byteop1p (r3:2,r1:0)(t,r) ;

+

+/* forward byte order operands */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL) ;

+/* round into low bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDH) ;

+/* round into high bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL) ;

+/* truncate into low bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH) ;

+/* truncate into high bytes (b) */

+/* reverse byte order operands */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDL, R) ;

+/* round into low bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (RNDH, R) ;

+/* round into high bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TL, R) ;

+/* truncate into low bytes (b) */

+//Dreg = BYTEOP2P (Dreg_pair, Dreg_pair) (TH, R) ;

+/* truncate into high bytes (b) */

+

+r3 = byteop2p (r1:0, r3:2) (rndl) ;

+r3 = byteop2p (r1:0, r3:2) (rndh) ;

+r3 = byteop2p (r1:0, r3:2) (tl) ;

+r3 = byteop2p (r1:0, r3:2) (th) ;

+r3 = byteop2p (r1:0, r3:2) (rndl, r) ;

+r3 = byteop2p (r1:0, r3:2) (rndh, r) ;

+r3 = byteop2p (r1:0, r3:2) (tl, r) ;

+r3 = byteop2p (r1:0, r3:2) (th, r) ;

+

+r0 = byteop2p (r1:0, r3:2) (rndl) ;

+r1 = byteop2p (r1:0, r3:2) (rndh) ;

+r2 = byteop2p (r1:0, r3:2) (tl) ;

+r3 = byteop2p (r1:0, r3:2) (th) ;

+r4 = byteop2p (r1:0, r3:2) (rndl, r) ;

+r5 = byteop2p (r1:0, r3:2) (rndh, r) ;

+r6 = byteop2p (r1:0, r3:2) (tl, r) ;

+r7 = byteop2p (r1:0, r3:2) (th, r) ;

+

+r0 = byteop2p (r3:2, r3:2) (rndl) ;

+r1 = byteop2p (r3:2, r3:2) (rndh) ;

+r2 = byteop2p (r3:2, r3:2) (tl) ;

+r3 = byteop2p (r3:2, r3:2) (th) ;

+r4 = byteop2p (r3:2, r3:2) (rndl, r) ;

+r5 = byteop2p (r3:2, r3:2) (rndh, r) ;

+r6 = byteop2p (r3:2, r3:2) (tl, r) ;

+r7 = byteop2p (r3:2, r3:2) (th, r) ;

+

+//Dreg = BYTEPACK ( Dreg, Dreg ) ; /* (b) */

+r0 = bytepack (r0,r0) ;

+r1 = bytepack (r2,r3) ;

+r4 = bytepack (r5,r6) ;

+r7 = bytepack (r0,r1) ;

+r2 = bytepack (r3,r4) ;

+r5 = bytepack (r6,r7) ;

+

+/* forward byte order operands */

+//(Dreg, Dreg) = BYTEOP16M (Dreg_pair, Dreg_pair) ; /* (b */)

+/* reverse byte order operands */

+//(Dreg, Dreg) = BYTEOP16M (Dreg-pair, Dreg-pair) (R) ; /* (b) */

+

+(r1,r2)= byteop16m (r3:2,r1:0) ;

+(r1,r2)= byteop16m (r3:2,r1:0) (r) ;

+(r0,r1)= byteop16m (r3:2,r1:0) ;

+(r2,r3)= byteop16m (r3:2,r1:0) (r) ;

+(r3,r5)= byteop16m (r3:2,r1:0) ;

+(r6,r7)= byteop16m (r3:2,r1:0) (r) ;

+

+(r1,r2)= byteop16m (r1:0,r1:0) ;

+(r1,r2)= byteop16m (r1:0,r1:0) (r) ;

+(r0,r1)= byteop16m (r1:0,r1:0) ;

+(r2,r3)= byteop16m (r1:0,r1:0) (r) ;

+(r3,r5)= byteop16m (r1:0,r1:0) ;

+(r6,r7)= byteop16m (r1:0,r1:0) (r) ;

+

+(r1,r2)= byteop16m (r1:0,r3:2) ;

+(r1,r2)= byteop16m (r1:0,r3:2) (r) ;

+(r0,r1)= byteop16m (r1:0,r3:2) ;

+(r2,r3)= byteop16m (r1:0,r3:2) (r) ;

+(r3,r5)= byteop16m (r1:0,r3:2) ;

+(r6,r7)= byteop16m (r1:0,r3:2) (r) ;

+

+(r1,r2)= byteop16m (r3:2,r3:2) ;

+(r1,r2)= byteop16m (r3:2,r3:2) (r) ;

+(r0,r1)= byteop16m (r3:2,r3:2) ;

+(r2,r3)= byteop16m (r3:2,r3:2) (r) ;

+(r3,r5)= byteop16m (r3:2,r3:2) ;

+(r6,r7)= byteop16m (r3:2,r3:2) (r) ;

+

+//SAA (Dreg_pair, Dreg_pair) ; /* forward byte order operands (b) */

+//SAA (Dreg_pair, Dreg_pair) (R) ; /* reverse byte order operands (b) */

+

+saa(r1:0, r3:2) || r0 = [i0++] || r2 = [i1++] ; /* parallel fill instructions */

+saa (r1:0, r3:2) (R) || r1 = [i0++] || r3 = [i1++] ; /* reverse, parallel fill instructions */

+saa (r1:0, r3:2) ; /* last SAA in a loop, no more fill required */

+

+//( Dreg , Dreg ) = BYTEUNPACK Dreg_pair ; /* (b) */

+//( Dreg , Dreg ) = BYTEUNPACK Dreg_pair (R) ; /* reverse source order (b) */

+

+(r6,r5) = byteunpack r1:0 ; /* non-reversing sources */

+(r6,r5) = byteunpack r1:0 (R) ; /* reversing sources case */

+(r6,r5) = byteunpack r3:2 ; /* non-reversing sources */

+(r6,r5) = byteunpack r3:2 (R) ; /* reversing sources case */

+(r0,r1) = byteunpack r1:0 ; /* non-reversing sources */

+(r2,r3) = byteunpack r1:0 (R) ; /* reversing sources case */

+(r4,r5) = byteunpack r3:2 ; /* non-reversing sources */

+(r6,r7) = byteunpack r3:2 (R) ; /* reversing sources case */

diff --git a/gas/testsuite/gas/cfi/cfi-alpha-1.d b/gas/testsuite/gas/cfi/cfi-alpha-1.d
index 9568d3b9c283..4b3a34095b1c 100644
--- a/gas/testsuite/gas/cfi/cfi-alpha-1.d
+++ b/gas/testsuite/gas/cfi/cfi-alpha-1.d
@@ -13,8 +13,8 @@ The section .eh_frame contains:
   DW_CFA_def_cfa_reg: r30
   DW_CFA_nop
 
-00000014 00000020 00000018 FDE cie=00000000 pc=0000001c..00000050
-  DW_CFA_advance_loc: 24 to 00000034
+00000014 00000020 00000018 FDE cie=00000000 pc=00000000..00000034
+  DW_CFA_advance_loc: 24 to 00000018
   DW_CFA_def_cfa: r15 ofs 32
   DW_CFA_offset: r26 at cfa-32
   DW_CFA_offset: r9 at cfa-24
diff --git a/gas/testsuite/gas/cfi/cfi-alpha-3.d b/gas/testsuite/gas/cfi/cfi-alpha-3.d
index f3ad084235be..f7bb8f0a6428 100644
--- a/gas/testsuite/gas/cfi/cfi-alpha-3.d
+++ b/gas/testsuite/gas/cfi/cfi-alpha-3.d
@@ -13,20 +13,20 @@ The section .eh_frame contains:
   DW_CFA_def_cfa_reg: r30
   DW_CFA_nop
 
-00000014 00000028 00000018 FDE cie=00000000 pc=0000001c..0000005c
-  DW_CFA_advance_loc: 4 to 00000020
+00000014 00000028 00000018 FDE cie=00000000 pc=00000000..00000040
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_def_cfa_offset: 32
-  DW_CFA_advance_loc: 4 to 00000024
+  DW_CFA_advance_loc: 4 to 00000008
   DW_CFA_offset: r26 at cfa-32
-  DW_CFA_advance_loc: 4 to 00000028
+  DW_CFA_advance_loc: 4 to 0000000c
   DW_CFA_offset: r9 at cfa-24
-  DW_CFA_advance_loc: 4 to 0000002c
+  DW_CFA_advance_loc: 4 to 00000010
   DW_CFA_offset: r15 at cfa-16
-  DW_CFA_advance_loc: 4 to 00000030
+  DW_CFA_advance_loc: 4 to 00000014
   DW_CFA_offset: r34 at cfa-8
-  DW_CFA_advance_loc: 4 to 00000034
+  DW_CFA_advance_loc: 4 to 00000018
   DW_CFA_def_cfa_reg: r15
-  DW_CFA_advance_loc: 36 to 00000058
+  DW_CFA_advance_loc: 36 to 0000003c
   DW_CFA_def_cfa: r30 ofs 0
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-arm-1.d b/gas/testsuite/gas/cfi/cfi-arm-1.d
new file mode 100644
index 000000000000..8474e20bbeee
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-arm-1.d
@@ -0,0 +1,27 @@
+#readelf: -wf
+#name: CFI on ARM
+
+The section .eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 2
+  Data alignment factor: -4
+  Return address column: 14
+  Augmentation data:     1b
+
+  DW_CFA_def_cfa: r13 ofs 0
+
+00000014 00000020 00000018 FDE cie=00000000 pc=00000000..00000018
+  DW_CFA_advance_loc: 4 to 00000004
+  DW_CFA_def_cfa: r12 ofs 0
+  DW_CFA_advance_loc: 4 to 00000008
+  DW_CFA_def_cfa: r13 ofs 16
+  DW_CFA_advance_loc: 4 to 0000000c
+  DW_CFA_def_cfa_offset: 32
+  DW_CFA_offset: r11 at cfa-32
+  DW_CFA_offset: r14 at cfa-24
+  DW_CFA_advance_loc: 4 to 00000010
+  DW_CFA_def_cfa: r11 ofs 16
+
diff --git a/gas/testsuite/gas/cfi/cfi-arm-1.s b/gas/testsuite/gas/cfi/cfi-arm-1.s
new file mode 100644
index 000000000000..8c9d9176bf5a
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-arm-1.s
@@ -0,0 +1,23 @@
+#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o
+
+	.file   "a.c"
+	.text
+	.align 2
+	.global foo
+	.type   foo, %function
+foo:
+	.cfi_startproc
+	mov	ip, sp
+	.cfi_def_cfa ip, 0
+	stmfd	sp!, {r0, r1, r2, r3}
+	.cfi_def_cfa sp, 16
+	stmfd	sp!, {fp, ip, lr, pc}
+	.cfi_adjust_cfa_offset 16
+	.cfi_rel_offset r11, 0
+	.cfi_rel_offset lr, 8
+	sub	fp, ip, #20
+	.cfi_def_cfa fp, 16
+	nop
+	ldmea	fp, {fp, sp, pc}
+	.cfi_endproc
+	.size   foo, .-foo
diff --git a/gas/testsuite/gas/cfi/cfi-common-1.d b/gas/testsuite/gas/cfi/cfi-common-1.d
index 332c4774c0c5..9f5d9932a7d9 100644
--- a/gas/testsuite/gas/cfi/cfi-common-1.d
+++ b/gas/testsuite/gas/cfi/cfi-common-1.d
@@ -8,7 +8,7 @@ The section .eh_frame contains:
   Code alignment factor: .*
   Data alignment factor: .*
   Return address column: .*
-  Augmentation data:     1b
+  Augmentation data:     [01]b
 
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-common-2.d b/gas/testsuite/gas/cfi/cfi-common-2.d
index a1f1d068541a..a54e542cbc38 100644
--- a/gas/testsuite/gas/cfi/cfi-common-2.d
+++ b/gas/testsuite/gas/cfi/cfi-common-2.d
@@ -8,7 +8,7 @@ The section .eh_frame contains:
   Code alignment factor: .*
   Data alignment factor: .*
   Return address column: .*
-  Augmentation data:     1b
+  Augmentation data:     [01]b
 #...
 00000014 000000[12][c0] 00000018 FDE cie=00000000 pc=.*
   DW_CFA_advance_loc: 4 to .*
diff --git a/gas/testsuite/gas/cfi/cfi-common-3.d b/gas/testsuite/gas/cfi/cfi-common-3.d
index 82a4193280ff..70055aa0b8cb 100644
--- a/gas/testsuite/gas/cfi/cfi-common-3.d
+++ b/gas/testsuite/gas/cfi/cfi-common-3.d
@@ -8,7 +8,7 @@ The section .eh_frame contains:
   Code alignment factor: .*
   Data alignment factor: .*
   Return address column: .*
-  Augmentation data:     1b
+  Augmentation data:     [01]b
 #...
 00000014 00000010 00000018 FDE cie=00000000 pc=.*
   DW_CFA_advance_loc: 4 to .*
diff --git a/gas/testsuite/gas/cfi/cfi-common-4.d b/gas/testsuite/gas/cfi/cfi-common-4.d
new file mode 100644
index 000000000000..9d6527023b49
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-4.d
@@ -0,0 +1,20 @@
+#readelf: -wf
+#name: CFI common 4
+The section .eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     [01]b
+#...
+00000014 00000010 00000018 FDE cie=00000000 pc=.*
+  DW_CFA_remember_state
+  DW_CFA_restore_state
+#...
+00000028 0000001[04] 0000002c FDE cie=00000000 pc=.*
+  DW_CFA_remember_state
+  DW_CFA_restore_state
+#pass
diff --git a/gas/testsuite/gas/cfi/cfi-common-4.s b/gas/testsuite/gas/cfi/cfi-common-4.s
new file mode 100644
index 000000000000..1851529e123b
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-common-4.s
@@ -0,0 +1,9 @@
+	.cfi_startproc simple
+	.cfi_remember_state
+	.cfi_restore_state
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_remember_state
+	.cfi_restore_state
+	.cfi_endproc
diff --git a/gas/testsuite/gas/cfi/cfi-i386.d b/gas/testsuite/gas/cfi/cfi-i386.d
index 471f5e1514be..ff7478031cc9 100644
--- a/gas/testsuite/gas/cfi/cfi-i386.d
+++ b/gas/testsuite/gas/cfi/cfi-i386.d
@@ -15,33 +15,33 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
-00000018 00000014 0000001c FDE cie=00000000 pc=00000020..00000032
-  DW_CFA_advance_loc: 6 to 00000026
+00000018 00000014 0000001c FDE cie=00000000 pc=00000000..00000012
+  DW_CFA_advance_loc: 6 to 00000006
   DW_CFA_def_cfa_offset: 4664
-  DW_CFA_advance_loc: 11 to 00000031
+  DW_CFA_advance_loc: 11 to 00000011
   DW_CFA_def_cfa_offset: 4
 
-00000030 00000018 00000034 FDE cie=00000000 pc=0000004a..00000057
-  DW_CFA_advance_loc: 1 to 0000004b
+00000030 00000018 00000034 FDE cie=00000000 pc=00000012..0000001f
+  DW_CFA_advance_loc: 1 to 00000013
   DW_CFA_def_cfa_offset: 8
   DW_CFA_offset: r5 at cfa-8
-  DW_CFA_advance_loc: 2 to 0000004d
+  DW_CFA_advance_loc: 2 to 00000015
   DW_CFA_def_cfa_reg: r5
-  DW_CFA_advance_loc: 9 to 00000056
+  DW_CFA_advance_loc: 9 to 0000001e
   DW_CFA_def_cfa_reg: r4
 
-0000004c 00000014 00000050 FDE cie=00000000 pc=00000073..00000083
-  DW_CFA_advance_loc: 2 to 00000075
+0000004c 00000014 00000050 FDE cie=00000000 pc=0000001f..0000002f
+  DW_CFA_advance_loc: 2 to 00000021
   DW_CFA_def_cfa_reg: r3
-  DW_CFA_advance_loc: 13 to 00000082
+  DW_CFA_advance_loc: 13 to 0000002e
   DW_CFA_def_cfa: r4 ofs 4
 
-00000064 00000010 00000068 FDE cie=00000000 pc=0000009b..000000a1
+00000064 00000010 00000068 FDE cie=00000000 pc=0000002f..00000035
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
 
-00000078 00000010 0000007c FDE cie=00000000 pc=000000b5..000000c4
+00000078 00000010 0000007c FDE cie=00000000 pc=00000035..00000044
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-m68k.d b/gas/testsuite/gas/cfi/cfi-m68k.d
index ff239f31731d..7aeb542e4bf4 100644
--- a/gas/testsuite/gas/cfi/cfi-m68k.d
+++ b/gas/testsuite/gas/cfi/cfi-m68k.d
@@ -15,22 +15,22 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
-00000018 00000014 0000001c FDE cie=00000000 pc=00000020..0000002c
-  DW_CFA_advance_loc: 4 to 00000024
+00000018 00000014 0000001c FDE cie=00000000 pc=00000000..0000000c
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_def_cfa_offset: 4664
-  DW_CFA_advance_loc: 6 to 0000002a
+  DW_CFA_advance_loc: 6 to 0000000a
   DW_CFA_def_cfa_offset: 4
 
-00000030 00000018 00000034 FDE cie=00000000 pc=00000038..00000044
-  DW_CFA_advance_loc: 4 to 0000003c
+00000030 00000018 00000034 FDE cie=00000000 pc=0000000c..00000018
+  DW_CFA_advance_loc: 4 to 00000010
   DW_CFA_def_cfa_offset: 8
   DW_CFA_offset: r14 at cfa-8
   DW_CFA_def_cfa_reg: r14
-  DW_CFA_advance_loc: 6 to 00000042
+  DW_CFA_advance_loc: 6 to 00000016
   DW_CFA_def_cfa_reg: r15
   DW_CFA_nop
 
-0000004c 00000010 00000050 FDE cie=00000000 pc=00000054..00000058
+0000004c 00000010 00000050 FDE cie=00000000 pc=00000018..0000001c
 
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-mips-1.d b/gas/testsuite/gas/cfi/cfi-mips-1.d
new file mode 100644
index 000000000000..7a8d8e8b29a7
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-mips-1.d
@@ -0,0 +1,27 @@
+#readelf: -wf
+#name: CFI on mips, 1
+The section .eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: -4
+  Return address column: 31
+  Augmentation data:     0b
+
+  DW_CFA_def_cfa_reg: r29
+  DW_CFA_def_cfa: r29 ofs 0
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00000000..0000002c
+  DW_CFA_advance_loc: 4 to 00000004
+  DW_CFA_def_cfa_offset: 8
+  DW_CFA_advance_loc: 4 to 00000008
+  DW_CFA_offset: r30 at cfa-8
+  DW_CFA_advance_loc: 4 to 0000000c
+  DW_CFA_def_cfa: r30 ofs 8
+  DW_CFA_advance_loc: 24 to 00000024
+  DW_CFA_def_cfa: r29 ofs 0
+  DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-mips-1.s b/gas/testsuite/gas/cfi/cfi-mips-1.s
new file mode 100644
index 000000000000..cf7d5e2fc816
--- /dev/null
+++ b/gas/testsuite/gas/cfi/cfi-mips-1.s
@@ -0,0 +1,39 @@
+	.file	1 "foo.c"
+	.section .mdebug.abi64
+	.previous
+	.text
+	.align	2
+	.globl	foo
+	.ent	foo
+	.cfi_startproc
+foo:
+	.frame	$fp,8,$31		# vars= 8, regs= 1/0, args= 0, gp= 0
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+
+	.cfi_def_cfa $sp, 0
+	addiu	$sp,$sp,-8
+	.cfi_adjust_cfa_offset 8
+	sw	$fp,0($sp)
+	.cfi_offset $30, -8
+	move	$fp,$sp
+	.cfi_def_cfa $fp, 8
+
+	nop
+	nop
+	nop
+	
+	move	$sp,$fp
+	lw	$fp,0($sp)
+	addiu	$sp,$sp,8
+	.cfi_def_cfa $sp, 0
+	j	$31
+	nop
+	.set	macro
+	.set	reorder
+	.end	foo
+	.cfi_endproc
+	.size   foo, .-foo
+	.ident	"GCC: (GNU) 4.0.0 20041226 (experimental)"
diff --git a/gas/testsuite/gas/cfi/cfi-ppc-1.d b/gas/testsuite/gas/cfi/cfi-ppc-1.d
index 28cb64c413c7..cb1f55e1c62f 100644
--- a/gas/testsuite/gas/cfi/cfi-ppc-1.d
+++ b/gas/testsuite/gas/cfi/cfi-ppc-1.d
@@ -14,16 +14,16 @@ The section .eh_frame contains:
 
   DW_CFA_def_cfa: r1 ofs 0
 
-00000014 00000020 00000018 FDE cie=00000000 pc=0000001c..0000008c
-  DW_CFA_advance_loc: 4 to 00000020
+00000014 00000020 00000018 FDE cie=00000000 pc=00000000..00000070
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_def_cfa_offset: 48
-  DW_CFA_advance_loc: 16 to 00000030
+  DW_CFA_advance_loc: 16 to 00000014
   DW_CFA_offset: r27 at cfa-20
   DW_CFA_offset: r26 at cfa-24
   DW_CFA_offset_extended_sf: r65 at cfa\+4
-  DW_CFA_advance_loc: 8 to 00000038
+  DW_CFA_advance_loc: 8 to 0000001c
   DW_CFA_offset: r28 at cfa-16
-  DW_CFA_advance_loc: 8 to 00000040
+  DW_CFA_advance_loc: 8 to 00000024
   DW_CFA_offset: r29 at cfa-12
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-s390-1.d b/gas/testsuite/gas/cfi/cfi-s390-1.d
index aa8dfe1a17a5..5cf36945f34f 100644
--- a/gas/testsuite/gas/cfi/cfi-s390-1.d
+++ b/gas/testsuite/gas/cfi/cfi-s390-1.d
@@ -14,8 +14,8 @@ The section .eh_frame contains:
 
   DW_CFA_def_cfa: r15 ofs 96
 
-00000014 00000024 00000018 FDE cie=00000000 pc=0000001c..0000006a
-  DW_CFA_advance_loc: 4 to 00000020
+00000014 00000024 00000018 FDE cie=00000000 pc=00000000..0000004e
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_offset: r15 at cfa-36
   DW_CFA_offset: r14 at cfa-40
   DW_CFA_offset: r13 at cfa-44
@@ -24,7 +24,7 @@ The section .eh_frame contains:
   DW_CFA_offset: r10 at cfa-56
   DW_CFA_offset: r9 at cfa-60
   DW_CFA_offset: r8 at cfa-64
-  DW_CFA_advance_loc: 22 to 00000036
+  DW_CFA_advance_loc: 22 to 0000001a
   DW_CFA_def_cfa_offset: 192
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-s390x-1.d b/gas/testsuite/gas/cfi/cfi-s390x-1.d
index ad67addc2abf..c515f38daa8e 100644
--- a/gas/testsuite/gas/cfi/cfi-s390x-1.d
+++ b/gas/testsuite/gas/cfi/cfi-s390x-1.d
@@ -17,8 +17,8 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
-00000018 00000024 0000001c FDE cie=00000000 pc=00000020..00000090
-  DW_CFA_advance_loc: 6 to 00000026
+00000018 00000024 0000001c FDE cie=00000000 pc=00000000..00000070
+  DW_CFA_advance_loc: 6 to 00000006
   DW_CFA_offset: r15 at cfa-40
   DW_CFA_offset: r14 at cfa-48
   DW_CFA_offset: r13 at cfa-56
@@ -27,7 +27,7 @@ The section .eh_frame contains:
   DW_CFA_offset: r10 at cfa-80
   DW_CFA_offset: r9 at cfa-88
   DW_CFA_offset: r8 at cfa-96
-  DW_CFA_advance_loc: 8 to 0000002e
+  DW_CFA_advance_loc: 8 to 0000000e
   DW_CFA_def_cfa_offset: 320
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-sh-1.d b/gas/testsuite/gas/cfi/cfi-sh-1.d
index fac748460b2f..bfbfcfad091c 100644
--- a/gas/testsuite/gas/cfi/cfi-sh-1.d
+++ b/gas/testsuite/gas/cfi/cfi-sh-1.d
@@ -12,16 +12,16 @@ The section .eh_frame contains:
 
   DW_CFA_def_cfa: r15 ofs 0
 
-00000014 00000020 00000018 FDE cie=00000000 pc=0000001c..00000048
-  DW_CFA_advance_loc: 2 to 0000001e
+00000014 00000020 00000018 FDE cie=00000000 pc=00000000..0000002c
+  DW_CFA_advance_loc: 2 to 00000002
   DW_CFA_def_cfa_offset: 4
-  DW_CFA_advance_loc: 2 to 00000020
+  DW_CFA_advance_loc: 2 to 00000004
   DW_CFA_def_cfa_offset: 8
   DW_CFA_offset: r15 at cfa-4
   DW_CFA_offset: r17 at cfa-8
-  DW_CFA_advance_loc: 6 to 00000026
+  DW_CFA_advance_loc: 6 to 0000000a
   DW_CFA_def_cfa_reg: r14
-  DW_CFA_advance_loc: 2 to 00000028
+  DW_CFA_advance_loc: 2 to 0000000c
   DW_CFA_def_cfa_offset: 40
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi-sparc-1.d b/gas/testsuite/gas/cfi/cfi-sparc-1.d
index ac927ac3ca72..c9d855a3dd64 100644
--- a/gas/testsuite/gas/cfi/cfi-sparc-1.d
+++ b/gas/testsuite/gas/cfi/cfi-sparc-1.d
@@ -14,8 +14,8 @@ The section .eh_frame contains:
 
   DW_CFA_def_cfa: r14 ofs 0
 
-00000014 00000014 00000018 FDE cie=00000000 pc=0000001c..00000040
-  DW_CFA_advance_loc: 4 to 00000020
+00000014 00000014 00000018 FDE cie=00000000 pc=00000000..00000024
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_def_cfa_reg: r30
   DW_CFA_GNU_window_save
   DW_CFA_register: r15 in r31
diff --git a/gas/testsuite/gas/cfi/cfi-sparc64-1.d b/gas/testsuite/gas/cfi/cfi-sparc64-1.d
index 10d3ea9a4f52..6206e391b595 100644
--- a/gas/testsuite/gas/cfi/cfi-sparc64-1.d
+++ b/gas/testsuite/gas/cfi/cfi-sparc64-1.d
@@ -17,8 +17,8 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
-00000018 00000014 0000001c FDE cie=00000000 pc=00000020..00000050
-  DW_CFA_advance_loc: 4 to 00000024
+00000018 00000014 0000001c FDE cie=00000000 pc=00000000..00000030
+  DW_CFA_advance_loc: 4 to 00000004
   DW_CFA_def_cfa_reg: r30
   DW_CFA_GNU_window_save
   DW_CFA_register: r15 in r31
diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d
index 2b19641ed2a8..f34643545028 100644
--- a/gas/testsuite/gas/cfi/cfi-x86_64.d
+++ b/gas/testsuite/gas/cfi/cfi-x86_64.d
@@ -15,37 +15,37 @@ The section .eh_frame contains:
   DW_CFA_nop
   DW_CFA_nop
 
-00000018 00000014 0000001c FDE cie=00000000 pc=00000020..00000034
-  DW_CFA_advance_loc: 7 to 00000027
+00000018 00000014 0000001c FDE cie=00000000 pc=00000000..00000014
+  DW_CFA_advance_loc: 7 to 00000007
   DW_CFA_def_cfa_offset: 4668
-  DW_CFA_advance_loc: 12 to 00000033
+  DW_CFA_advance_loc: 12 to 00000013
   DW_CFA_def_cfa_offset: 8
 
-00000030 0000001c 00000034 FDE cie=00000000 pc=00000038..00000047
-  DW_CFA_advance_loc: 1 to 00000039
+00000030 0000001c 00000034 FDE cie=00000000 pc=00000014..00000022
+  DW_CFA_advance_loc: 1 to 00000015
   DW_CFA_def_cfa_offset: 16
   DW_CFA_offset: r6 at cfa-16
-  DW_CFA_advance_loc: 3 to 0000003c
+  DW_CFA_advance_loc: 3 to 00000018
   DW_CFA_def_cfa_reg: r6
-  DW_CFA_advance_loc: 10 to 00000046
+  DW_CFA_advance_loc: 9 to 00000021
   DW_CFA_def_cfa: r7 ofs 8
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
 
-00000050 00000014 00000054 FDE cie=00000000 pc=00000058..0000006b
-  DW_CFA_advance_loc: 3 to 0000005b
+00000050 00000014 00000054 FDE cie=00000000 pc=00000022..00000035
+  DW_CFA_advance_loc: 3 to 00000025
   DW_CFA_def_cfa_reg: r12
-  DW_CFA_advance_loc: 15 to 0000006a
+  DW_CFA_advance_loc: 15 to 00000034
   DW_CFA_def_cfa_reg: r7
   DW_CFA_nop
 
-00000068 00000010 0000006c FDE cie=00000000 pc=00000070..00000076
+00000068 00000010 0000006c FDE cie=00000000 pc=00000035..0000003b
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
 
-0000007c 00000010 00000080 FDE cie=00000000 pc=00000084..00000096
+0000007c 00000010 00000080 FDE cie=00000000 pc=0000003b..0000004d
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp
index f32a04746074..eeb551098291 100644
--- a/gas/testsuite/gas/cfi/cfi.exp
+++ b/gas/testsuite/gas/cfi/cfi.exp
@@ -56,6 +56,11 @@ if [istarget "x86_64-*"] then {
 	run_dump_test "cfi-sh-1"
     }
 
+} elseif { [istarget "arm*-*"] || [istarget "xscale*-*"] } then {
+    run_dump_test "cfi-arm-1"
+
+} elseif { [istarget "mips*-*"] } then {
+    run_dump_test "cfi-mips-1"
 } else {
     return
 }
@@ -64,3 +69,4 @@ run_list_test "cfi-diag-1" ""
 run_dump_test "cfi-common-1"
 run_dump_test "cfi-common-2"
 run_dump_test "cfi-common-3"
+run_dump_test "cfi-common-4"
diff --git a/gas/testsuite/gas/cris/abs32-1.s b/gas/testsuite/gas/cris/abs32-1.s
new file mode 100644
index 000000000000..07c22b3361ed
--- /dev/null
+++ b/gas/testsuite/gas/cris/abs32-1.s
@@ -0,0 +1,31 @@
+ .text
+  nop
+locsym1:
+  .global locsym2
+locsym2:
+  nop
+  jump locsym1
+  jump locsym2
+  jump locsym3
+  jump locsym4
+  jump extsym
+  jsr locsym1
+  jsr locsym2
+  jsr locsym3
+  jsr locsym4
+  jsr extsym
+  jsrc locsym1
+  .dword 0
+  jsrc locsym2
+  .dword 0
+  jsrc locsym3
+  .dword 0
+  jsrc locsym4
+  .dword 0
+  jsrc extsym
+  .dword 0
+  nop
+  .global locsym3
+locsym3:
+locsym4:
+  nop
diff --git a/gas/testsuite/gas/cris/arch-err-1.s b/gas/testsuite/gas/cris/arch-err-1.s
new file mode 100644
index 000000000000..f2d5c53ff1e5
--- /dev/null
+++ b/gas/testsuite/gas/cris/arch-err-1.s
@@ -0,0 +1,4 @@
+; Test mismatch of --march=ARCH1 and .arch ARCH2.
+; { dg-do assemble }
+ .arch something ; { dg-error "unknown operand to .arch" }
+
diff --git a/gas/testsuite/gas/cris/arch-err-2.s b/gas/testsuite/gas/cris/arch-err-2.s
new file mode 100644
index 000000000000..d8b2dae5fe2b
--- /dev/null
+++ b/gas/testsuite/gas/cris/arch-err-2.s
@@ -0,0 +1,5 @@
+; Test mismatch of --march=ARCH1 and .arch ARCH2.
+; { dg-do assemble }
+; { dg-options "--march=v0_v10" }
+ .arch v32 ; { dg-error ".arch <arch> requires a matching --march=" }
+
diff --git a/gas/testsuite/gas/cris/arch-err-3.s b/gas/testsuite/gas/cris/arch-err-3.s
new file mode 100644
index 000000000000..153f316114c2
--- /dev/null
+++ b/gas/testsuite/gas/cris/arch-err-3.s
@@ -0,0 +1,5 @@
+; Test mismatch of --march=ARCH1 and .arch ARCH2.
+; { dg-do assemble }
+; { dg-options "--march=common_v10_v32" }
+ .arch v32 ; { dg-error ".arch <arch> requires a matching --march=" }
+
diff --git a/gas/testsuite/gas/cris/arch-err-4.s b/gas/testsuite/gas/cris/arch-err-4.s
new file mode 100644
index 000000000000..a13828e41959
--- /dev/null
+++ b/gas/testsuite/gas/cris/arch-err-4.s
@@ -0,0 +1,5 @@
+; Test mismatch of --march=ARCH1 and .arch ARCH2.
+; { dg-do assemble }
+; { dg-options "--march=v10" }
+ .arch common_v10_v32 ; { dg-error ".arch <arch> requires a matching --march=" }
+
diff --git a/gas/testsuite/gas/cris/arch-err-5.s b/gas/testsuite/gas/cris/arch-err-5.s
new file mode 100644
index 000000000000..800521f0fa16
--- /dev/null
+++ b/gas/testsuite/gas/cris/arch-err-5.s
@@ -0,0 +1,5 @@
+; Test mismatch of --march=ARCH1 and .arch ARCH2.
+; { dg-do assemble }
+; { dg-options "--march=v10" }
+ .arch v0_v10 ; { dg-error ".arch <arch> requires a matching --march=" }
+
diff --git a/gas/testsuite/gas/cris/bound-err-1.s b/gas/testsuite/gas/cris/bound-err-1.s
new file mode 100644
index 000000000000..3d3f9c486fae
--- /dev/null
+++ b/gas/testsuite/gas/cris/bound-err-1.s
@@ -0,0 +1,9 @@
+; { dg-do assemble { target cris-*-* } }
+; { dg-options "--march=v32" }
+x:
+ ; Memory operand for bound didn't make it to v32.  Check that
+ ; it's flagged as an error.
+ bound.b [r3],r7	; { dg-error "operands" }
+ bound.w [r8+],r1	; { dg-error "operands" }
+ bound.d [r11],r3	; { dg-error "operands" }
+ nop ; For alignment purposes.
diff --git a/gas/testsuite/gas/cris/brokw-3.d b/gas/testsuite/gas/cris/brokw-3.d
index bbf04832f59e..139e3a5d191b 100644
--- a/gas/testsuite/gas/cris/brokw-3.d
+++ b/gas/testsuite/gas/cris/brokw-3.d
@@ -1,4 +1,5 @@
 #objdump: -dr
+#as: --underscore
 #name: brokw-3
 
 .*:     file format .*-cris
diff --git a/gas/testsuite/gas/cris/brokw-3b.s b/gas/testsuite/gas/cris/brokw-3b.s
new file mode 100644
index 000000000000..d067d04c394a
--- /dev/null
+++ b/gas/testsuite/gas/cris/brokw-3b.s
@@ -0,0 +1,115 @@
+; Tests the broken-word function with a real switch table.  CRISv32 version.
+
+start:	moveq 0,r0
+
+	subs.b 87,r0
+	bound.b 41,r0
+	lapc sym2,acr
+	addi r0.w,acr
+	adds.w [acr],acr
+	jump acr
+	nop
+sym2:
+	.word	sym1 - .
+	.word	sym3 - .
+	.word	sym4 - .
+	.word	sym5 - .
+	.word	sym6 - .
+	.word	sym7 - .
+	.word	sym8 - .
+	.word	sym9 - .
+	.word	sym10 - .
+	.word	sym11 - .
+	.word	sym12 - .
+	.word	sym13 - .
+	.word	sym14 - .
+	.word	sym15 - .
+	.word	sym16 - .
+	.word	sym17 - .
+	.word	sym18 - .
+	.word	sym19 - .
+	.word	sym20 - .
+	.word	sym21 - .
+	.word	sym22 - .
+	.word	sym23 - .
+	.word	sym24 - .
+	.word	sym25 - .
+	.word	sym26 - .
+	.word	sym27 - .
+	.word	sym28 - .
+	.word	sym29 - .
+	.word	sym30 - .
+	.word	sym31 - .
+	.word	sym32 - .
+	.word	sym33 - .
+	.word	sym34 - .
+	.word	sym35 - .
+	.word	sym36 - .
+	.word	sym37 - .
+	.word	sym38 - .
+	.word	sym39 - .
+	.word	sym40 - .
+	.word	sym41 - .
+	.word	sym42 - .
+	.word	sym43 - .
+
+	.space	16, 0
+
+	moveq 1,r0
+; Medium-range branch around secondary jump table inserted here :
+;	ba	next_label
+;	nop
+;	.skip	2,0
+; Secondary jump table inserted here :
+;	ba	sym1
+;	nop
+;	ba	sym3
+;	nop
+;	...
+next_label:
+	moveq 2,r0
+
+	.space	32768, 0
+
+sym1:	moveq -3,r0
+sym3: moveq 3,r0
+sym4: moveq 4,r0
+sym5: moveq 5,r0
+sym6: moveq 6,r0
+sym7: moveq 7,r0
+sym8: moveq 8,r0
+sym9: moveq 9,r0
+sym10: moveq 10,r0
+sym11: moveq 11,r0
+sym12: moveq 12,r0
+sym13: moveq 13,r0
+sym14: moveq 14,r0
+sym15: moveq 15,r0
+sym16: moveq 16,r0
+sym17: moveq 17,r0
+sym18: moveq 18,r0
+sym19: moveq 19,r0
+sym20: moveq 20,r0
+sym21: moveq 21,r0
+sym22: moveq 22,r0
+sym23: moveq 23,r0
+sym24: moveq 24,r0
+sym25: moveq 25,r0
+sym26: moveq 26,r0
+sym27: moveq 27,r0
+sym28: moveq 28,r0
+sym29: moveq 29,r0
+sym30: moveq 30,r0
+sym31: moveq 31,r0
+sym32: moveq -32,r0
+sym33: moveq -31,r0
+sym34: moveq -30,r0
+sym35: moveq -29,r0
+sym36: moveq -28,r0
+sym37: moveq -27,r0
+sym38: moveq -26,r0
+sym39: moveq -25,r0
+sym40: moveq -24,r0
+sym41: moveq -23,r0
+sym42: moveq -22,r0
+sym43: moveq -21,r0
diff --git a/gas/testsuite/gas/cris/cris.exp b/gas/testsuite/gas/cris/cris.exp
index 5977fefc32b5..33fb72017eed 100644
--- a/gas/testsuite/gas/cris/cris.exp
+++ b/gas/testsuite/gas/cris/cris.exp
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # hp@axis.com
diff --git a/gas/testsuite/gas/cris/march-err-1.s b/gas/testsuite/gas/cris/march-err-1.s
new file mode 100644
index 000000000000..b646f10a7900
--- /dev/null
+++ b/gas/testsuite/gas/cris/march-err-1.s
@@ -0,0 +1,5 @@
+; Test unsupported ARCH in -march=ARCH.
+; { dg-do assemble }
+; { dg-options "--march=whatever" }
+; { dg-error ".* invalid <arch> in --march=<arch>: whatever" "" { target cris-*-* } 0 }
+ nop
diff --git a/gas/testsuite/gas/cris/march-err-2.s b/gas/testsuite/gas/cris/march-err-2.s
new file mode 100644
index 000000000000..f27f09ed5ff1
--- /dev/null
+++ b/gas/testsuite/gas/cris/march-err-2.s
@@ -0,0 +1,6 @@
+; Test unsupported ARCH in -march=ARCH, where there's an option
+; which is a proper substring.
+; { dg-do assemble }
+; { dg-options "--march=v10_v32" }
+; { dg-error ".* invalid <arch> in --march=<arch>: v10_v32" "" { target cris-*-* } 0 }
+ nop
diff --git a/gas/testsuite/gas/cris/mulbug-err-1.s b/gas/testsuite/gas/cris/mulbug-err-1.s
index fbd830398c69..b8a0d9ca0ac8 100644
--- a/gas/testsuite/gas/cris/mulbug-err-1.s
+++ b/gas/testsuite/gas/cris/mulbug-err-1.s
@@ -2,6 +2,7 @@
 ; a hardware bug.
 
 ;  { dg-do assemble { target cris-*-* } }
+;  { dg-options "--em=criself" }
 
  ; First, .text isn't dword-aligned by default.
  .text
diff --git a/gas/testsuite/gas/cris/operand-err-1.s b/gas/testsuite/gas/cris/operand-err-1.s
index e042cc3a7717..cd806f97ce63 100644
--- a/gas/testsuite/gas/cris/operand-err-1.s
+++ b/gas/testsuite/gas/cris/operand-err-1.s
@@ -12,16 +12,21 @@ start:
  test.d [r3],r4 ; { dg-error "(Illegal|Invalid) operands" }
  move.d [r3],r4,r5 ; { dg-error "(Illegal|Invalid) operands" }
 
-; These two *might* be useful in extreme cases, so maybe the following
-; should not be considered an error in the first place.
- test.d whatever ; { dg-error "(Illegal|Invalid) operands" "" { xfail *-*-* } }
- test.d 42 ; { dg-error "(Illegal|Invalid) operands" "" { xfail *-*-* } }
+; These two could be seen useful in extreme cases, but those
+; would be shadowed by not flagging erroneous use of
+; e.g. "test.d $r3" for CRISv32.  If you really need it, use
+; e.g. "test.d [$pc+] @ .dword whatever".
+ test.d whatever ; { dg-error "(Illegal|Invalid) operands" "" }
+ test.d 42 ; { dg-error "(Illegal|Invalid) operands" "" }
 
  clear.d whatever ; { dg-error "(Illegal|Invalid) operands" }
  clear.d 42 ; { dg-error "(Illegal|Invalid) operands" }
  addi r5,r3 ; { dg-error "(Illegal|Invalid) operands" }
- ba [external_symbol] ; Not an error, just obscure and generally useless.
- ba [r3] ; Not an error, just obscure and generally useless.
+
+; These two are valid instructions, though not recognized by
+; the assembler since they're obscure and generally useless.
+ ba [external_symbol] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
+ ba [r3] ; { dg-error "(Illegal|Invalid) operands|(B|b)ad expression" }
  lsl r3,r5 ; { dg-error "(Illegal|Invalid) operands" }
  xor.d r5,r6 ; { dg-error "(Illegal|Invalid) operands" }
 
diff --git a/gas/testsuite/gas/cris/push-err-1.s b/gas/testsuite/gas/cris/push-err-1.s
new file mode 100644
index 000000000000..acf1b6f31ff3
--- /dev/null
+++ b/gas/testsuite/gas/cris/push-err-1.s
@@ -0,0 +1,8 @@
+; { dg-do assemble { target cris-*-* } }
+; { dg-options "--march=v32" }
+x:
+ ; There are no "push" or "pop" synonyms for v32.
+ push $r10	; { dg-error "Unknown" }
+ push $srp	; { dg-error "Unknown" }
+ pop $r8	; { dg-error "Unknown" }
+ pop $mof	; { dg-error "Unknown" }
diff --git a/gas/testsuite/gas/cris/push-err-2.s b/gas/testsuite/gas/cris/push-err-2.s
new file mode 100644
index 000000000000..7717ee745bbf
--- /dev/null
+++ b/gas/testsuite/gas/cris/push-err-2.s
@@ -0,0 +1,9 @@
+; { dg-do assemble { target cris-*-* } }
+; { dg-options "--march=common_v10_v32" }
+x:
+; There are no "push" or "pop" synonyms for the compatible
+; subset of v10 and v32.
+ push $r10	; { dg-error "Unknown" }
+ push $srp	; { dg-error "Unknown" }
+ pop $r8	; { dg-error "Unknown" }
+ pop $mof	; { dg-error "Unknown" }
diff --git a/gas/testsuite/gas/cris/pushpopv32.s b/gas/testsuite/gas/cris/pushpopv32.s
new file mode 100644
index 000000000000..a41d80b5a925
--- /dev/null
+++ b/gas/testsuite/gas/cris/pushpopv32.s
@@ -0,0 +1,11 @@
+; Check that push and pop builtin "macros" aren't recognized for
+; v32.
+ .text
+start:
+ subq 4,sp
+ move.d r10,[sp]
+ subq 4,sp
+ move srp,[sp]
+ move.d [sp+],r10
+ move [sp+],srp
+end:
diff --git a/gas/testsuite/gas/cris/range-err-1.s b/gas/testsuite/gas/cris/range-err-1.s
index 69e3a3222be7..ecced2671074 100644
--- a/gas/testsuite/gas/cris/range-err-1.s
+++ b/gas/testsuite/gas/cris/range-err-1.s
@@ -61,9 +61,9 @@ start:
  add.w 2781868,r13 ; { dg-error "Immediate value not in 16 bit range: 2781868" }
  add.w -2701867,r13 ; { dg-error "Immediate value not in 16 bit range: -2701867" }
 
- add.w 0x9ec0ceac,r13 ; { dg-error "Immediate value not in 16 bit range: -1631531348" }
+ add.w 0x9ec0ceac,r13 ; { dg-error "Immediate value not in 16 bit range: (2663435948|-1631531348)" }
  add.w -0x7ec0cead,r13 ; { dg-error "Immediate value not in 16 bit range: -2126565037" }
 
- add.w const_int_m32,r13 ; { dg-error "Immediate value not in 16 bit range: 781758389" }
+ add.w const_int_m32,r13 ; { dg-error "Immediate value not in 16 bit range: (-3513208907|781758389)" }
  add.w const_int_32,r13 ; { dg-error "Immediate value not in 16 bit range: 462701867" }
  add.w -(three2767+2),r5 ; { dg-error "Immediate value not in 16 bit range: -32769" }
diff --git a/gas/testsuite/gas/cris/rd-abs32-1.d b/gas/testsuite/gas/cris/rd-abs32-1.d
new file mode 100644
index 000000000000..aee95ff5c337
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-abs32-1.d
@@ -0,0 +1,61 @@
+#source: abs32-1.s
+#as: --em=criself
+#objdump: -dr
+
+# Check that jump-type instructions to absolute addresses
+# assemble and disassemble correctly.
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+
+00000000 <locsym2-0x2>:
+   0:	0f05                	nop 
+
+00000002 <locsym2>:
+   2:	0f05                	nop 
+   4:	3f0d 0200 0000      	jump 2 <locsym2>
+			6: R_CRIS_32	\.text\+0x2
+   a:	3f0d 0000 0000      	jump 0 <locsym2-0x2>
+			c: R_CRIS_32	locsym2
+  10:	3f0d 0000 0000      	jump 0 <locsym2-0x2>
+			12: R_CRIS_32	locsym3
+  16:	3f0d 7400 0000      	jump 74 <locsym3>
+			18: R_CRIS_32	\.text\+0x74
+  1c:	3f0d 0000 0000      	jump 0 <locsym2-0x2>
+			1e: R_CRIS_32	extsym
+  22:	3fbd 0200 0000      	jsr 2 <locsym2>
+			24: R_CRIS_32	\.text\+0x2
+  28:	3fbd 0000 0000      	jsr 0 <locsym2-0x2>
+			2a: R_CRIS_32	locsym2
+  2e:	3fbd 0000 0000      	jsr 0 <locsym2-0x2>
+			30: R_CRIS_32	locsym3
+  34:	3fbd 7400 0000      	jsr 74 <locsym3>
+			36: R_CRIS_32	\.text\+0x74
+  3a:	3fbd 0000 0000      	jsr 0 <locsym2-0x2>
+			3c: R_CRIS_32	extsym
+  40:	3f3d 0200 0000      	jsrc 2 <locsym2>
+			42: R_CRIS_32	\.text\+0x2
+  46:	0000                	bcc \.\+2
+  48:	0000                	bcc \.\+2
+  4a:	3f3d 0000 0000      	jsrc 0 <locsym2-0x2>
+			4c: R_CRIS_32	locsym2
+  50:	0000                	bcc \.\+2
+  52:	0000                	bcc \.\+2
+  54:	3f3d 0000 0000      	jsrc 0 <locsym2-0x2>
+			56: R_CRIS_32	locsym3
+  5a:	0000                	bcc \.\+2
+  5c:	0000                	bcc \.\+2
+  5e:	3f3d 7400 0000      	jsrc 74 <locsym3>
+			60: R_CRIS_32	\.text\+0x74
+  64:	0000                	bcc \.\+2
+  66:	0000                	bcc \.\+2
+  68:	3f3d 0000 0000      	jsrc 0 <locsym2-0x2>
+			6a: R_CRIS_32	extsym
+  6e:	0000                	bcc \.\+2
+  70:	0000                	bcc \.\+2
+  72:	0f05                	nop 
+
+00000074 <locsym3>:
+  74:	0f05                	nop 
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-abs32-2.d b/gas/testsuite/gas/cris/rd-abs32-2.d
new file mode 100644
index 000000000000..20fc30205aef
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-abs32-2.d
@@ -0,0 +1,62 @@
+#source: abs32-1.s
+#as: --em=criself --march=v32
+#objdump: -dr
+
+# Check that jump-type instructions to absolute addresses
+# assemble and disassemble correctly for v32 given "old-style"
+# mnemonics.
+
+.*:     file format elf32.*-cris
+
+Disassembly of section \.text:
+
+00000000 <locsym2-0x2>:
+   0:	b005                	nop 
+
+00000002 <locsym2>:
+   2:	b005                	nop 
+   4:	bf0d 0000 0000      	jump 0 <locsym2-0x2>
+			6: R_CRIS_32	\.text\+0x2
+   a:	bf0d 0000 0000      	jump 0 <locsym2-0x2>
+			c: R_CRIS_32	locsym2
+  10:	bf0d 0000 0000      	jump 0 <locsym2-0x2>
+			12: R_CRIS_32	locsym3
+  16:	bf0d 0000 0000      	jump 0 <locsym2-0x2>
+			18: R_CRIS_32	\.text\+0x74
+  1c:	bf0d 0000 0000      	jump 0 <locsym2-0x2>
+			1e: R_CRIS_32	extsym
+  22:	bfbd 0000 0000      	jsr 0 <locsym2-0x2>
+			24: R_CRIS_32	\.text\+0x2
+  28:	bfbd 0000 0000      	jsr 0 <locsym2-0x2>
+			2a: R_CRIS_32	locsym2
+  2e:	bfbd 0000 0000      	jsr 0 <locsym2-0x2>
+			30: R_CRIS_32	locsym3
+  34:	bfbd 0000 0000      	jsr 0 <locsym2-0x2>
+			36: R_CRIS_32	\.text\+0x74
+  3a:	bfbd 0000 0000      	jsr 0 <locsym2-0x2>
+			3c: R_CRIS_32	extsym
+  40:	3fbf 0000 0000      	jsrc 0 <locsym2-0x2>
+			42: R_CRIS_32	\.text\+0x2
+  46:	0000                	bcc \.
+  48:	0000                	bcc \.
+  4a:	3fbf 0000 0000      	jsrc 0 <locsym2-0x2>
+			4c: R_CRIS_32	locsym2
+  50:	0000                	bcc \.
+  52:	0000                	bcc \.
+  54:	3fbf 0000 0000      	jsrc 0 <locsym2-0x2>
+			56: R_CRIS_32	locsym3
+  5a:	0000                	bcc \.
+  5c:	0000                	bcc \.
+  5e:	3fbf 0000 0000      	jsrc 0 <locsym2-0x2>
+			60: R_CRIS_32	\.text\+0x74
+  64:	0000                	bcc \.
+  66:	0000                	bcc \.
+  68:	3fbf 0000 0000      	jsrc 0 <locsym2-0x2>
+			6a: R_CRIS_32	extsym
+  6e:	0000                	bcc \.
+  70:	0000                	bcc \.
+  72:	b005                	nop 
+
+00000074 <locsym3>:
+  74:	b005                	nop 
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-arch-1.d b/gas/testsuite/gas/cris/rd-arch-1.d
new file mode 100644
index 000000000000..12c6c6ee7a56
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-arch-1.d
@@ -0,0 +1,7 @@
+#source: arch-err-2.s
+#as: --march=v32 --underscore --em=criself
+#objdump: -p
+
+#...
+private flags = 3: \[symbols have a _ prefix\] \[v32\]
+#pass
diff --git a/gas/testsuite/gas/cris/rd-arch-2.d b/gas/testsuite/gas/cris/rd-arch-2.d
new file mode 100644
index 000000000000..69e5b6fb5418
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-arch-2.d
@@ -0,0 +1,7 @@
+#source: arch-err-4.s
+#as: --underscore --march=common_v10_v32 --em=criself
+#objdump: -p
+
+#...
+private flags = 5: \[symbols have a _ prefix\] \[v10 and v32\]
+#pass
diff --git a/gas/testsuite/gas/cris/rd-arch-3.d b/gas/testsuite/gas/cris/rd-arch-3.d
new file mode 100644
index 000000000000..022c1f01cc11
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-arch-3.d
@@ -0,0 +1,7 @@
+#source: arch-err-5.s
+#as: --march=v0_v10 --underscore --em=criself
+#objdump: -p
+
+#...
+private flags = 1: \[symbols have a _ prefix\]
+#pass
diff --git a/gas/testsuite/gas/cris/rd-bcnst-pic.d b/gas/testsuite/gas/cris/rd-bcnst-pic.d
new file mode 100644
index 000000000000..365a6a4c7237
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bcnst-pic.d
@@ -0,0 +1,28 @@
+#objdump: -dr
+#as: --pic --underscore --em=criself
+#source: rd-bcnst.s
+
+# Catches an error in the relaxation machinery and checks that there's no
+# confusion between section offset and absolute address.
+
+.*:     file format elf32.*-cris
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+[ 	]+0:[ 	]+0ae0[ 	]+ba 0xc
+[ 	]+2:[ 	]+0f05[ 	]+nop 
+[ 	]+4:[ 	]+6ffd 0000 0000 3f0e[ 	]+move \[pc=pc\+0x0\],p0
+[ 	]+6:[ 	]+R_CRIS_32_PCREL[ 	]+\*ABS\*\+0xbadb00
+[ 	]+c:[ 	]+f770[ 	]+bmi 0x4
+[ 	]+e:[ 	]+0ae0[ 	]+ba 0x1a
+[ 	]+10:[ 	]+0f05[ 	]+nop 
+[ 	]+12:[ 	]+6ffd 0000 0000 3f0e[ 	]+move \[pc=pc\+0x0\],p0
+[ 	]+14:[ 	]+R_CRIS_32_PCREL[ 	]+\*ABS\*\+0xb00
+[ 	]+1a:[ 	]+f770[ 	]+bmi 0x12
+[ 	]+1c:[ 	]+0ae0[ 	]+ba 0x28
+[ 	]+1e:[ 	]+0f05[ 	]+nop 
+[ 	]+20:[ 	]+6ffd 0000 0000 3f0e[ 	]+move \[pc=pc\+0x0\],p0
+[ 	]+22:[ 	]+R_CRIS_32_PCREL[ 	]+\*ABS\*\+0x42
+[ 	]+28:[ 	]+f770[ 	]+bmi 0x20
+[ 	]+2a:[ 	]+0000[ 	]+bcc \.\+2
diff --git a/gas/testsuite/gas/cris/rd-bcnst.d b/gas/testsuite/gas/cris/rd-bcnst.d
index f21066657b40..80e9716dd5c0 100644
--- a/gas/testsuite/gas/cris/rd-bcnst.d
+++ b/gas/testsuite/gas/cris/rd-bcnst.d
@@ -8,15 +8,15 @@
 Disassembly of section \.text:
 
 0+ <\.text>:
-[ 	]+0:[ 	]+08e0[ 	]+ba 0xa
+[ 	]+0:[ 	]+08e0[ 	]+ba (0xa|a <.*)
 [ 	]+2:[ 	]+0f05[ 	]+nop 
-[ 	]+4:[ 	]+3f0d 00db ba00[ 	]+jump 0xbadb00
-[ 	]+a:[ 	]+f970[ 	]+bmi 0x4
-[ 	]+c:[ 	]+08e0[ 	]+ba 0x16
+[ 	]+4:[ 	]+3f0d 00db ba00[ 	]+jump (0xbadb00|badb00 <.*)
+[ 	]+a:[ 	]+f970[ 	]+bmi (0x4|4 <.*)
+[ 	]+c:[ 	]+08e0[ 	]+ba (0x16|16 <.*)
 [ 	]+e:[ 	]+0f05[ 	]+nop 
-[ 	]+10:[ 	]+3f0d 000b 0000[ 	]+jump 0xb00
-[ 	]+16:[ 	]+f970[ 	]+bmi 0x10
-[ 	]+18:[ 	]+08e0[ 	]+ba 0x22
+[ 	]+10:[ 	]+3f0d 000b 0000[ 	]+jump (0xb00|b00 <.*)
+[ 	]+16:[ 	]+f970[ 	]+bmi (0x10|10 <.*)
+[ 	]+18:[ 	]+08e0[ 	]+ba (0x22|22 <.*)
 [ 	]+1a:[ 	]+0f05[ 	]+nop 
-[ 	]+1c:[ 	]+3f0d 4200 0000[ 	]+jump 0x42
-[ 	]+22:[ 	]+f970[ 	]+bmi 0x1c
+[ 	]+1c:[ 	]+3f0d 4200 0000[ 	]+jump (0x42|42 <.*)
+[ 	]+22:[ 	]+f970[ 	]+bmi (0x1c|1c <.*)
diff --git a/gas/testsuite/gas/cris/rd-bkw1b.d b/gas/testsuite/gas/cris/rd-bkw1b.d
new file mode 100644
index 000000000000..19e9d71b299a
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bkw1b.d
@@ -0,0 +1,23 @@
+#as: --underscore --em=criself --march=v32
+#source: brokw-1.s
+#objdump: -dr
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+0+ <sym2>:
+[	 ]+0:[	 ]+4002[ 	]+moveq[ ]+0,r0
+[	 ]+2:[	 ]+0c00[ 	]+.*
+[	 ]+4:[	 ]+4102[ 	]+moveq[ ]+1,r0
+[	 ]+6:[	 ]+0ee0[ 	]+ba[ ]+14 <next_label>
+[	 ]+8:[	 ]+b005[ 	]+nop[ ]*
+[	 ]+a:[	 ]+b005[ 	]+nop[ ]*
+[	 ]+c:[	 ]+bf0e 0880 0000[ 	]+ba[ ]+8014 <sym1>
+[	 ]+12:[	 ]+b005[ 	]+nop[ ]*
+0+14 <next_label>:
+[	 ]+14:[	 ]+4202[ 	]+moveq[ ]+2,r0
+[ 	]+\.\.\.
+0+8014 <sym1>:
+[	 ]+8014:[	 ]+4302[ 	]+moveq[ ]+3,r0
+[ 	]+\.\.\.
+
diff --git a/gas/testsuite/gas/cris/rd-bkw2b.d b/gas/testsuite/gas/cris/rd-bkw2b.d
new file mode 100644
index 000000000000..1d268b3a44c0
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bkw2b.d
@@ -0,0 +1,27 @@
+#as: --underscore --em=criself --march=v32
+#source: brokw-2.s
+#objdump: -dr
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+0+ <sym2>:
+[	 ]+0:[	 ]+4002[ 	]+moveq[ ]+0,r0
+[	 ]+2:[	 ]+1600[ 	]+.*
+[	 ]+4:[	 ]+0e00[ 	]+.*
+[	 ]+6:[	 ]+4102[ 	]+moveq[ ]+1,r0
+[	 ]+8:[	 ]+16e0[ 	]+ba[ ]+1e <next_label>
+[	 ]+a:[	 ]+b005[ 	]+nop[ ]*
+[	 ]+c:[	 ]+b005[ 	]+nop[ ]*
+[	 ]+e:[	 ]+bf0e 1280 0000[ 	]+ba[ ]+8020 <sym3>
+[	 ]+14:[	 ]+b005[ 	]+nop[ ]*
+[	 ]+16:[	 ]+bf0e 0880 0000[ 	]+ba[ ]+801e <sym1>
+[	 ]+1c:[	 ]+b005[ 	]+nop[ ]*
+0+1e <next_label>:
+[	 ]+1e:[	 ]+4202[ 	]+moveq[ ]+2,r0
+[ 	]+\.\.\.
+0+801e <sym1>:
+[	 ]+801e:[	 ]+4302[ 	]+moveq[ ]+3,r0
+0+8020 <sym3>:
+[	 ]+8020:[	 ]+4402[ 	]+moveq[ ]+4,r0
+[ 	]+\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-bkw3b.d b/gas/testsuite/gas/cris/rd-bkw3b.d
new file mode 100644
index 000000000000..4a7cca9bb2e2
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bkw3b.d
@@ -0,0 +1,282 @@
+#as: --underscore --em=criself --march=v32
+#source: brokw-3b.s
+#objdump: -dr
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+
+00000000 <start>:
+       0:	4002                	moveq 0,r0
+       2:	af0c 5700           	subs\.b 87,r0
+       6:	cf0d 2900           	bound\.b 0x29,r0
+       a:	75f9                	lapcq 14 <sym2>,acr
+       c:	1f05                	addi r0\.w,acr
+       e:	3ff8                	adds\.w \[acr\],acr
+      10:	bf09                	jump acr
+      12:	b005                	nop 
+
+00000014 <sym2>:
+      14:	b401 .*
+      16:	aa01 .*
+      18:	a001 .*
+      1a:	9601 .*
+      1c:	8c01 .*
+      1e:	8201 .*
+      20:	7801 .*
+      22:	6e01 .*
+      24:	6401 .*
+      26:	5a01 .*
+      28:	5001 .*
+      2a:	4601 .*
+      2c:	3c01 .*
+      2e:	3201 .*
+      30:	2801 .*
+      32:	1e01 .*
+      34:	1401 .*
+      36:	0a01 .*
+      38:	0001 .*
+      3a:	f600 .*
+      3c:	ec00 .*
+      3e:	e200 .*
+      40:	d800 .*
+      42:	ce00 .*
+      44:	c400 .*
+      46:	ba00 .*
+      48:	b000 .*
+      4a:	a600 .*
+      4c:	9c00 .*
+      4e:	9200 .*
+      50:	8800 .*
+      52:	7e00 .*
+      54:	7400 .*
+      56:	6a00 .*
+      58:	6000 .*
+      5a:	5600 .*
+      5c:	4c00 .*
+      5e:	4200 .*
+      60:	3800 .*
+      62:	2e00 .*
+      64:	2400 .*
+      66:	1a00 .*
+      68:	0000 .*
+	\.\.\.
+      76:	0000 .*
+      78:	4102                	moveq 1,r0
+      7a:	ffed 5601           	ba 1d0 <next_label>
+      7e:	b005                	nop 
+      80:	bf0e a481 0000      	ba 8224 <sym43>
+      86:	b005                	nop 
+      88:	bf0e 9a81 0000      	ba 8222 <sym42>
+      8e:	b005                	nop 
+      90:	bf0e 9081 0000      	ba 8220 <sym41>
+      96:	b005                	nop 
+      98:	bf0e 8681 0000      	ba 821e <sym40>
+      9e:	b005                	nop 
+      a0:	bf0e 7c81 0000      	ba 821c <sym39>
+      a6:	b005                	nop 
+      a8:	bf0e 7281 0000      	ba 821a <sym38>
+      ae:	b005                	nop 
+      b0:	bf0e 6881 0000      	ba 8218 <sym37>
+      b6:	b005                	nop 
+      b8:	bf0e 5e81 0000      	ba 8216 <sym36>
+      be:	b005                	nop 
+      c0:	bf0e 5481 0000      	ba 8214 <sym35>
+      c6:	b005                	nop 
+      c8:	bf0e 4a81 0000      	ba 8212 <sym34>
+      ce:	b005                	nop 
+      d0:	bf0e 4081 0000      	ba 8210 <sym33>
+      d6:	b005                	nop 
+      d8:	bf0e 3681 0000      	ba 820e <sym32>
+      de:	b005                	nop 
+      e0:	bf0e 2c81 0000      	ba 820c <sym31>
+      e6:	b005                	nop 
+      e8:	bf0e 2281 0000      	ba 820a <sym30>
+      ee:	b005                	nop 
+      f0:	bf0e 1881 0000      	ba 8208 <sym29>
+      f6:	b005                	nop 
+      f8:	bf0e 0e81 0000      	ba 8206 <sym28>
+      fe:	b005                	nop 
+     100:	bf0e 0481 0000      	ba 8204 <sym27>
+     106:	b005                	nop 
+     108:	bf0e fa80 0000      	ba 8202 <sym26>
+     10e:	b005                	nop 
+     110:	bf0e f080 0000      	ba 8200 <sym25>
+     116:	b005                	nop 
+     118:	bf0e e680 0000      	ba 81fe <sym24>
+     11e:	b005                	nop 
+     120:	bf0e dc80 0000      	ba 81fc <sym23>
+     126:	b005                	nop 
+     128:	bf0e d280 0000      	ba 81fa <sym22>
+     12e:	b005                	nop 
+     130:	bf0e c880 0000      	ba 81f8 <sym21>
+     136:	b005                	nop 
+     138:	bf0e be80 0000      	ba 81f6 <sym20>
+     13e:	b005                	nop 
+     140:	bf0e b480 0000      	ba 81f4 <sym19>
+     146:	b005                	nop 
+     148:	bf0e aa80 0000      	ba 81f2 <sym18>
+     14e:	b005                	nop 
+     150:	bf0e a080 0000      	ba 81f0 <sym17>
+     156:	b005                	nop 
+     158:	bf0e 9680 0000      	ba 81ee <sym16>
+     15e:	b005                	nop 
+     160:	bf0e 8c80 0000      	ba 81ec <sym15>
+     166:	b005                	nop 
+     168:	bf0e 8280 0000      	ba 81ea <sym14>
+     16e:	b005                	nop 
+     170:	bf0e 7880 0000      	ba 81e8 <sym13>
+     176:	b005                	nop 
+     178:	bf0e 6e80 0000      	ba 81e6 <sym12>
+     17e:	b005                	nop 
+     180:	bf0e 6480 0000      	ba 81e4 <sym11>
+     186:	b005                	nop 
+     188:	bf0e 5a80 0000      	ba 81e2 <sym10>
+     18e:	b005                	nop 
+     190:	bf0e 5080 0000      	ba 81e0 <sym9>
+     196:	b005                	nop 
+     198:	bf0e 4680 0000      	ba 81de <sym8>
+     19e:	b005                	nop 
+     1a0:	bf0e 3c80 0000      	ba 81dc <sym7>
+     1a6:	b005                	nop 
+     1a8:	bf0e 3280 0000      	ba 81da <sym6>
+     1ae:	b005                	nop 
+     1b0:	bf0e 2880 0000      	ba 81d8 <sym5>
+     1b6:	b005                	nop 
+     1b8:	bf0e 1e80 0000      	ba 81d6 <sym4>
+     1be:	b005                	nop 
+     1c0:	bf0e 1480 0000      	ba 81d4 <sym3>
+     1c6:	b005                	nop 
+     1c8:	bf0e 0a80 0000      	ba 81d2 <sym1>
+     1ce:	b005                	nop 
+
+000001d0 <next_label>:
+     1d0:	4202                	moveq 2,r0
+	\.\.\.
+
+000081d2 <sym1>:
+    81d2:	7d02                	moveq -3,r0
+
+000081d4 <sym3>:
+    81d4:	4302                	moveq 3,r0
+
+000081d6 <sym4>:
+    81d6:	4402                	moveq 4,r0
+
+000081d8 <sym5>:
+    81d8:	4502                	moveq 5,r0
+
+000081da <sym6>:
+    81da:	4602                	moveq 6,r0
+
+000081dc <sym7>:
+    81dc:	4702                	moveq 7,r0
+
+000081de <sym8>:
+    81de:	4802                	moveq 8,r0
+
+000081e0 <sym9>:
+    81e0:	4902                	moveq 9,r0
+
+000081e2 <sym10>:
+    81e2:	4a02                	moveq 10,r0
+
+000081e4 <sym11>:
+    81e4:	4b02                	moveq 11,r0
+
+000081e6 <sym12>:
+    81e6:	4c02                	moveq 12,r0
+
+000081e8 <sym13>:
+    81e8:	4d02                	moveq 13,r0
+
+000081ea <sym14>:
+    81ea:	4e02                	moveq 14,r0
+
+000081ec <sym15>:
+    81ec:	4f02                	moveq 15,r0
+
+000081ee <sym16>:
+    81ee:	5002                	moveq 16,r0
+
+000081f0 <sym17>:
+    81f0:	5102                	moveq 17,r0
+
+000081f2 <sym18>:
+    81f2:	5202                	moveq 18,r0
+
+000081f4 <sym19>:
+    81f4:	5302                	moveq 19,r0
+
+000081f6 <sym20>:
+    81f6:	5402                	moveq 20,r0
+
+000081f8 <sym21>:
+    81f8:	5502                	moveq 21,r0
+
+000081fa <sym22>:
+    81fa:	5602                	moveq 22,r0
+
+000081fc <sym23>:
+    81fc:	5702                	moveq 23,r0
+
+000081fe <sym24>:
+    81fe:	5802                	moveq 24,r0
+
+00008200 <sym25>:
+    8200:	5902                	moveq 25,r0
+
+00008202 <sym26>:
+    8202:	5a02                	moveq 26,r0
+
+00008204 <sym27>:
+    8204:	5b02                	moveq 27,r0
+
+00008206 <sym28>:
+    8206:	5c02                	moveq 28,r0
+
+00008208 <sym29>:
+    8208:	5d02                	moveq 29,r0
+
+0000820a <sym30>:
+    820a:	5e02                	moveq 30,r0
+
+0000820c <sym31>:
+    820c:	5f02                	moveq 31,r0
+
+0000820e <sym32>:
+    820e:	6002                	moveq -32,r0
+
+00008210 <sym33>:
+    8210:	6102                	moveq -31,r0
+
+00008212 <sym34>:
+    8212:	6202                	moveq -30,r0
+
+00008214 <sym35>:
+    8214:	6302                	moveq -29,r0
+
+00008216 <sym36>:
+    8216:	6402                	moveq -28,r0
+
+00008218 <sym37>:
+    8218:	6502                	moveq -27,r0
+
+0000821a <sym38>:
+    821a:	6602                	moveq -26,r0
+
+0000821c <sym39>:
+    821c:	6702                	moveq -25,r0
+
+0000821e <sym40>:
+    821e:	6802                	moveq -24,r0
+
+00008220 <sym41>:
+    8220:	6902                	moveq -23,r0
+
+00008222 <sym42>:
+    8222:	6a02                	moveq -22,r0
+
+00008224 <sym43>:
+    8224:	6b02                	moveq -21,r0
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-bound1.d b/gas/testsuite/gas/cris/rd-bound1.d
new file mode 100644
index 000000000000..40bfd34b8c36
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bound1.d
@@ -0,0 +1,11 @@
+#as: --underscore --em=criself
+#objdump: -dr
+.*:     file format elf32-us-cris
+Disassembly of section \.text:
+0+ <x>:
+[ 	]+0:[ 	]+c375[ 	]+bound\.b r3,r7
+[ 	]+2:[ 	]+d815[ 	]+bound\.w r8,r1
+[ 	]+4:[ 	]+eb35[ 	]+bound\.d r11,r3
+[ 	]+6:[ 	]+cf2d 4200[ 	]+bound\.b 0x42,r2
+[ 	]+a:[ 	]+df0d 6810[ 	]+bound\.w 0x1068,r0
+[ 	]+e:[ 	]+ef5d 6a16 4000[ 	]+bound\.d 40166a <x\+0x40166a>,r5
diff --git a/gas/testsuite/gas/cris/rd-bound1.s b/gas/testsuite/gas/cris/rd-bound1.s
new file mode 100644
index 000000000000..f004276c143b
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bound1.s
@@ -0,0 +1,8 @@
+; Some simple bound operands, but no memory operands.
+x:
+ bound.b r3,r7
+ bound.w r8,r1
+ bound.d r11,r3
+ bound.b 0x42,r2
+ bound.w 4200,r0
+ bound.d 4200042,r5
diff --git a/gas/testsuite/gas/cris/rd-bound2.d b/gas/testsuite/gas/cris/rd-bound2.d
new file mode 100644
index 000000000000..e0aec151f7c9
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bound2.d
@@ -0,0 +1,15 @@
+#as: --underscore --em=criself --march=v32
+#source: rd-bound1.s
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <x>:
+[ 	]+0:[ 	]+c375[ 	]+bound\.b r3,r7
+[ 	]+2:[ 	]+d815[ 	]+bound\.w r8,r1
+[ 	]+4:[ 	]+eb35[ 	]+bound\.d r11,r3
+[ 	]+6:[ 	]+cf2d 4200[ 	]+bound\.b 0x42,r2
+[ 	]+a:[ 	]+df0d 6810[ 	]+bound\.w 0x1068,r0
+[ 	]+e:[ 	]+ef5d 6a16 4000[ 	]+bound.d 40166a <x\+0x40166a>,r5
diff --git a/gas/testsuite/gas/cris/rd-bound3.d b/gas/testsuite/gas/cris/rd-bound3.d
new file mode 100644
index 000000000000..874c29016e8c
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bound3.d
@@ -0,0 +1,14 @@
+#as: --underscore --em=criself --march=v10
+#source: bound-err-1.s
+#objdump: -dr
+
+# A bound insn with a memory operand is an error for v32, but is
+# valid for v10.  Check.
+
+.*:     file format elf32-us-cris
+Disassembly of section \.text:
+0+ <x>:
+[ 	]+0:[ 	]+c379[ 	]+bound\.b \[r3\],r7
+[ 	]+2:[ 	]+d81d[ 	]+bound\.w \[r8\+\],r1
+[ 	]+4:[ 	]+eb39[ 	]+bound\.d \[r11\],r3
+[ 	]+6:[ 	]+0f05[ 	]+nop 
diff --git a/gas/testsuite/gas/cris/rd-bound4.d b/gas/testsuite/gas/cris/rd-bound4.d
new file mode 100644
index 000000000000..1b0670ab2681
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-bound4.d
@@ -0,0 +1,18 @@
+#as: --underscore --em=criself --march=common_v10_v32
+#source: rd-bound1.s
+#objdump: -dr
+
+# Bound with register and immediate are part of the common
+# v10+v32 subset.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <x>:
+[ 	]+0:[ 	]+c375[ 	]+bound\.b r3,r7
+[ 	]+2:[ 	]+d815[ 	]+bound\.w r8,r1
+[ 	]+4:[ 	]+eb35[ 	]+bound\.d r11,r3
+[ 	]+6:[ 	]+cf2d 4200[ 	]+bound\.b 0x42,r2
+[ 	]+a:[ 	]+df0d 6810[ 	]+bound\.w 0x1068,r0
+[ 	]+e:[ 	]+ef5d 6a16 4000[ 	]+bound.d 40166a <x\+0x40166a>,r5
diff --git a/gas/testsuite/gas/cris/rd-branch-pic.d b/gas/testsuite/gas/cris/rd-branch-pic.d
new file mode 100644
index 000000000000..4c6b59abc790
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-branch-pic.d
@@ -0,0 +1,450 @@
+#objdump: -dr
+#as: --pic --underscore --em=criself
+#source: branch.s
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+0+ <start_original>:
+[	 ]+0:[	 ]+0f05[ 	]+nop[ ]*
+0+2 <startm32>:
+[	 ]+2:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+7e6a <startm16>:
+[	 ]+7e6a:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+7f2e <start>:
+[	 ]+7f2e:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+7f30:[	 ]+fde0[ 	]+ba[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f32:[	 ]+fb00[ 	]+bcc[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f34:[	 ]+f910[ 	]+bcs[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f36:[	 ]+f730[ 	]+beq[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f38:[	 ]+f5f0[ 	]+bwf[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f3a:[	 ]+f3f0[ 	]+bwf[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f3c:[	 ]+f1f0[ 	]+bwf[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f3e:[	 ]+efa0[ 	]+bge[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f40:[	 ]+edc0[ 	]+bgt[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f42:[	 ]+eb90[ 	]+bhi[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f44:[	 ]+e900[ 	]+bcc[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f46:[	 ]+e7d0[ 	]+ble[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f48:[	 ]+e510[ 	]+bcs[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f4a:[	 ]+e380[ 	]+bls[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f4c:[	 ]+e1b0[ 	]+blt[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f4e:[	 ]+df70[ 	]+bmi[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f50:[	 ]+dd20[ 	]+bne[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f52:[	 ]+db60[ 	]+bpl[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f54:[	 ]+d940[ 	]+bvc[ ]+(0x7f2e|7f2e <start>)
+[	 ]+7f56:[	 ]+d750[ 	]+bvs[ ]+(0x7f2e|7f2e <start>)
+0+7f58 <start2>:
+[	 ]+7f58:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+7f5a:[	 ]+0fe0[ 	]+ba[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f5c:[	 ]+0d00[ 	]+bcc[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f5e:[	 ]+0b10[ 	]+bcs[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f60:[	 ]+0930[ 	]+beq[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f62:[	 ]+07f0[ 	]+bwf[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f64:[	 ]+05f0[ 	]+bwf[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f66:[	 ]+03f0[ 	]+bwf[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f68:[	 ]+01a0[ 	]+bge[ ]+(0x7e6a|7e6a <startm16>)
+[	 ]+7f6a:[	 ]+ffcd fcfe[ 	]+bgt (0x7e6a|7e6a <startm16>)
+[	 ]+7f6e:[	 ]+ff9d f8fe[ 	]+bhi (0x7e6a|7e6a <startm16>)
+[	 ]+7f72:[	 ]+ff0d f4fe[ 	]+bhs (0x7e6a|7e6a <startm16>)
+[	 ]+7f76:[	 ]+ffdd f0fe[ 	]+ble (0x7e6a|7e6a <startm16>)
+[	 ]+7f7a:[	 ]+ff1d ecfe[ 	]+blo (0x7e6a|7e6a <startm16>)
+[	 ]+7f7e:[	 ]+ff8d e8fe[ 	]+bls (0x7e6a|7e6a <startm16>)
+[	 ]+7f82:[	 ]+ffbd e4fe[ 	]+blt (0x7e6a|7e6a <startm16>)
+[	 ]+7f86:[	 ]+ff7d e0fe[ 	]+bmi (0x7e6a|7e6a <startm16>)
+[	 ]+7f8a:[	 ]+ff2d dcfe[ 	]+bne (0x7e6a|7e6a <startm16>)
+[	 ]+7f8e:[	 ]+ff6d d8fe[ 	]+bpl (0x7e6a|7e6a <startm16>)
+[	 ]+7f92:[	 ]+ff4d d4fe[ 	]+bvc (0x7e6a|7e6a <startm16>)
+[	 ]+7f96:[	 ]+ff5d d0fe[ 	]+bvs (0x7e6a|7e6a <startm16>)
+0+7f9a <start3>:
+[	 ]+7f9a:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+7f9c:[	 ]+ffed cafe[ 	]+ba (0x7e6a|7e6a <startm16>)
+[	 ]+7fa0:[	 ]+ff0d c6fe[ 	]+bhs (0x7e6a|7e6a <startm16>)
+[	 ]+7fa4:[	 ]+ff1d c2fe[ 	]+blo (0x7e6a|7e6a <startm16>)
+[	 ]+7fa8:[	 ]+ff3d befe[ 	]+beq (0x7e6a|7e6a <startm16>)
+[	 ]+7fac:[	 ]+fffd bafe[ 	]+bwf (0x7e6a|7e6a <startm16>)
+[	 ]+7fb0:[	 ]+fffd b6fe[ 	]+bwf (0x7e6a|7e6a <startm16>)
+[	 ]+7fb4:[	 ]+fffd b2fe[ 	]+bwf (0x7e6a|7e6a <startm16>)
+[	 ]+7fb8:[	 ]+ffad aefe[ 	]+bge (0x7e6a|7e6a <startm16>)
+[	 ]+7fbc:[	 ]+ffcd aafe[ 	]+bgt (0x7e6a|7e6a <startm16>)
+[	 ]+7fc0:[	 ]+ff9d a6fe[ 	]+bhi (0x7e6a|7e6a <startm16>)
+[	 ]+7fc4:[	 ]+ff0d a2fe[ 	]+bhs (0x7e6a|7e6a <startm16>)
+[	 ]+7fc8:[	 ]+ffdd 9efe[ 	]+ble (0x7e6a|7e6a <startm16>)
+[	 ]+7fcc:[	 ]+ff1d 9afe[ 	]+blo (0x7e6a|7e6a <startm16>)
+[	 ]+7fd0:[	 ]+ff8d 96fe[ 	]+bls (0x7e6a|7e6a <startm16>)
+[	 ]+7fd4:[	 ]+ffbd 92fe[ 	]+blt (0x7e6a|7e6a <startm16>)
+[	 ]+7fd8:[	 ]+ff7d 8efe[ 	]+bmi (0x7e6a|7e6a <startm16>)
+[	 ]+7fdc:[	 ]+ff2d 8afe[ 	]+bne (0x7e6a|7e6a <startm16>)
+[	 ]+7fe0:[	 ]+ff6d 86fe[ 	]+bpl (0x7e6a|7e6a <startm16>)
+[	 ]+7fe4:[	 ]+ff4d 82fe[ 	]+bvc (0x7e6a|7e6a <startm16>)
+[	 ]+7fe8:[	 ]+ff5d 7efe[ 	]+bvs (0x7e6a|7e6a <startm16>)
+0+7fec <start4>:
+[	 ]+7fec:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+7fee:[	 ]+ffed 1080[ 	]+ba (0x2|2 <startm32>)
+[	 ]+7ff2:[	 ]+ff0d 0c80[ 	]+bhs (0x2|2 <startm32>)
+[	 ]+7ff6:[	 ]+ff1d 0880[ 	]+blo (0x2|2 <startm32>)
+[	 ]+7ffa:[	 ]+ff3d 0480[ 	]+beq (0x2|2 <startm32>)
+[	 ]+7ffe:[	 ]+fffd 0080[ 	]+bwf (0x2|2 <startm32>)
+[ 	]+8002:[ 	]+0ae0[ 	]+ba 800e <start4\+0x22>
+[ 	]+8004:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8006:[ 	]+6ffd f67f ffff 3f0e[ 	]+move \[pc=pc\+ffff7ff6 <endp32\+0xfffe7c28>\],p0
+[ 	]+800e:[ 	]+f7f0[ 	]+bwf 8006 <start4\+0x1a>
+[ 	]+8010:[ 	]+0ae0[ 	]+ba 801c <start4\+0x30>
+[ 	]+8012:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8014:[ 	]+6ffd e87f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fe8 <endp32\+0xfffe7c1a>\],p0
+[ 	]+801c:[ 	]+f7f0[ 	]+bwf 8014 <start4\+0x28>
+[ 	]+801e:[ 	]+0ae0[ 	]+ba 802a <start4\+0x3e>
+[ 	]+8020:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8022:[ 	]+6ffd da7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fda <endp32\+0xfffe7c0c>\],p0
+[ 	]+802a:[ 	]+f7a0[ 	]+bge 8022 <start4\+0x36>
+[ 	]+802c:[ 	]+0ae0[ 	]+ba 8038 <start4\+0x4c>
+[ 	]+802e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8030:[ 	]+6ffd cc7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fcc <endp32\+0xfffe7bfe>\],p0
+[ 	]+8038:[ 	]+f7c0[ 	]+bgt 8030 <start4\+0x44>
+[ 	]+803a:[ 	]+0ae0[ 	]+ba 8046 <start4\+0x5a>
+[ 	]+803c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+803e:[ 	]+6ffd be7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fbe <endp32\+0xfffe7bf0>\],p0
+[ 	]+8046:[ 	]+f790[ 	]+bhi 803e <start4\+0x52>
+[ 	]+8048:[ 	]+0ae0[ 	]+ba 8054 <start4\+0x68>
+[ 	]+804a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+804c:[ 	]+6ffd b07f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fb0 <endp32\+0xfffe7be2>\],p0
+[ 	]+8054:[ 	]+f700[ 	]+bcc 804c <start4\+0x60>
+[ 	]+8056:[ 	]+0ae0[ 	]+ba 8062 <start4\+0x76>
+[ 	]+8058:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+805a:[ 	]+6ffd a27f ffff 3f0e[ 	]+move \[pc=pc\+ffff7fa2 <endp32\+0xfffe7bd4>\],p0
+[ 	]+8062:[ 	]+f7d0[ 	]+ble 805a <start4\+0x6e>
+[ 	]+8064:[ 	]+0ae0[ 	]+ba 8070 <start4\+0x84>
+[ 	]+8066:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8068:[ 	]+6ffd 947f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f94 <endp32\+0xfffe7bc6>\],p0
+[ 	]+8070:[ 	]+f710[ 	]+bcs 8068 <start4\+0x7c>
+[ 	]+8072:[ 	]+0ae0[ 	]+ba 807e <start4\+0x92>
+[ 	]+8074:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8076:[ 	]+6ffd 867f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f86 <endp32\+0xfffe7bb8>\],p0
+[ 	]+807e:[ 	]+f780[ 	]+bls 8076 <start4\+0x8a>
+[ 	]+8080:[ 	]+0ae0[ 	]+ba 808c <start4\+0xa0>
+[ 	]+8082:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8084:[ 	]+6ffd 787f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f78 <endp32\+0xfffe7baa>\],p0
+[ 	]+808c:[ 	]+f7b0[ 	]+blt 8084 <start4\+0x98>
+[ 	]+808e:[ 	]+0ae0[ 	]+ba 809a <start4\+0xae>
+[ 	]+8090:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8092:[ 	]+6ffd 6a7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f6a <endp32\+0xfffe7b9c>\],p0
+[ 	]+809a:[ 	]+f770[ 	]+bmi 8092 <start4\+0xa6>
+[ 	]+809c:[ 	]+0ae0[ 	]+ba 80a8 <start4\+0xbc>
+[ 	]+809e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80a0:[ 	]+6ffd 5c7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f5c <endp32\+0xfffe7b8e>\],p0
+[ 	]+80a8:[ 	]+f720[ 	]+bne 80a0 <start4\+0xb4>
+[ 	]+80aa:[ 	]+0ae0[ 	]+ba 80b6 <start4\+0xca>
+[ 	]+80ac:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80ae:[ 	]+6ffd 4e7f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f4e <endp32\+0xfffe7b80>\],p0
+[ 	]+80b6:[ 	]+f760[ 	]+bpl 80ae <start4\+0xc2>
+[ 	]+80b8:[ 	]+0ae0[ 	]+ba 80c4 <start4\+0xd8>
+[ 	]+80ba:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80bc:[ 	]+6ffd 407f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f40 <endp32\+0xfffe7b72>\],p0
+[ 	]+80c4:[ 	]+f740[ 	]+bvc 80bc <start4\+0xd0>
+[ 	]+80c6:[ 	]+0ae0[ 	]+ba 80d2 <start4\+0xe6>
+[ 	]+80c8:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80ca:[ 	]+6ffd 327f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f32 <endp32\+0xfffe7b64>\],p0
+[ 	]+80d2:[ 	]+f750[ 	]+bvs 80ca <start4\+0xde>
+0+80d4 <start5>:
+[ 	]+80d4:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80d6:[ 	]+0ae0[ 	]+ba 80e2 <start5\+0xe>
+[ 	]+80d8:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80da:[ 	]+6ffd 227f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f22 <endp32\+0xfffe7b54>\],p0
+[ 	]+80e2:[ 	]+f7e0[ 	]+ba 80da <start5\+0x6>
+[ 	]+80e4:[ 	]+0ae0[ 	]+ba 80f0 <start5\+0x1c>
+[ 	]+80e6:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80e8:[ 	]+6ffd 147f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f14 <endp32\+0xfffe7b46>\],p0
+[ 	]+80f0:[ 	]+f700[ 	]+bcc 80e8 <start5\+0x14>
+[ 	]+80f2:[ 	]+0ae0[ 	]+ba 80fe <start5\+0x2a>
+[ 	]+80f4:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+80f6:[ 	]+6ffd 067f ffff 3f0e[ 	]+move \[pc=pc\+ffff7f06 <endp32\+0xfffe7b38>\],p0
+[ 	]+80fe:[ 	]+f710[ 	]+bcs 80f6 <start5\+0x22>
+[ 	]+8100:[ 	]+0ae0[ 	]+ba 810c <start5\+0x38>
+[ 	]+8102:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8104:[ 	]+6ffd f87e ffff 3f0e[ 	]+move \[pc=pc\+ffff7ef8 <endp32\+0xfffe7b2a>\],p0
+[ 	]+810c:[ 	]+f730[ 	]+beq 8104 <start5\+0x30>
+[ 	]+810e:[ 	]+0ae0[ 	]+ba 811a <start5\+0x46>
+[ 	]+8110:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8112:[ 	]+6ffd ea7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7eea <endp32\+0xfffe7b1c>\],p0
+[ 	]+811a:[ 	]+f7f0[ 	]+bwf 8112 <start5\+0x3e>
+[ 	]+811c:[ 	]+0ae0[ 	]+ba 8128 <start5\+0x54>
+[ 	]+811e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8120:[ 	]+6ffd dc7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7edc <endp32\+0xfffe7b0e>\],p0
+[ 	]+8128:[ 	]+f7f0[ 	]+bwf 8120 <start5\+0x4c>
+[ 	]+812a:[ 	]+0ae0[ 	]+ba 8136 <start5\+0x62>
+[ 	]+812c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+812e:[ 	]+6ffd ce7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7ece <endp32\+0xfffe7b00>\],p0
+[ 	]+8136:[ 	]+f7f0[ 	]+bwf 812e <start5\+0x5a>
+[ 	]+8138:[ 	]+0ae0[ 	]+ba 8144 <start5\+0x70>
+[ 	]+813a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+813c:[ 	]+6ffd c07e ffff 3f0e[ 	]+move \[pc=pc\+ffff7ec0 <endp32\+0xfffe7af2>\],p0
+[ 	]+8144:[ 	]+f7a0[ 	]+bge 813c <start5\+0x68>
+[ 	]+8146:[ 	]+0ae0[ 	]+ba 8152 <start5\+0x7e>
+[ 	]+8148:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+814a:[ 	]+6ffd b27e ffff 3f0e[ 	]+move \[pc=pc\+ffff7eb2 <endp32\+0xfffe7ae4>\],p0
+[ 	]+8152:[ 	]+f7c0[ 	]+bgt 814a <start5\+0x76>
+[ 	]+8154:[ 	]+0ae0[ 	]+ba 8160 <start5\+0x8c>
+[ 	]+8156:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8158:[ 	]+6ffd a47e ffff 3f0e[ 	]+move \[pc=pc\+ffff7ea4 <endp32\+0xfffe7ad6>\],p0
+[ 	]+8160:[ 	]+f790[ 	]+bhi 8158 <start5\+0x84>
+[ 	]+8162:[ 	]+0ae0[ 	]+ba 816e <start5\+0x9a>
+[ 	]+8164:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8166:[ 	]+6ffd 967e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e96 <endp32\+0xfffe7ac8>\],p0
+[ 	]+816e:[ 	]+f700[ 	]+bcc 8166 <start5\+0x92>
+[ 	]+8170:[ 	]+0ae0[ 	]+ba 817c <start5\+0xa8>
+[ 	]+8172:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8174:[ 	]+6ffd 887e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e88 <endp32\+0xfffe7aba>\],p0
+[ 	]+817c:[ 	]+f7d0[ 	]+ble 8174 <start5\+0xa0>
+[ 	]+817e:[ 	]+0ae0[ 	]+ba 818a <start5\+0xb6>
+[ 	]+8180:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8182:[ 	]+6ffd 7a7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e7a <endp32\+0xfffe7aac>\],p0
+[ 	]+818a:[ 	]+f710[ 	]+bcs 8182 <start5\+0xae>
+[ 	]+818c:[ 	]+0ae0[ 	]+ba 8198 <start5\+0xc4>
+[ 	]+818e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8190:[ 	]+6ffd 6c7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e6c <endp32\+0xfffe7a9e>\],p0
+[ 	]+8198:[ 	]+f780[ 	]+bls 8190 <start5\+0xbc>
+[ 	]+819a:[ 	]+0ae0[ 	]+ba 81a6 <start5\+0xd2>
+[ 	]+819c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+819e:[ 	]+6ffd 5e7e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e5e <endp32\+0xfffe7a90>\],p0
+[ 	]+81a6:[ 	]+f7b0[ 	]+blt 819e <start5\+0xca>
+[ 	]+81a8:[ 	]+0ae0[ 	]+ba 81b4 <start5\+0xe0>
+[ 	]+81aa:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81ac:[ 	]+6ffd 507e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e50 <endp32\+0xfffe7a82>\],p0
+[ 	]+81b4:[ 	]+f770[ 	]+bmi 81ac <start5\+0xd8>
+[ 	]+81b6:[ 	]+0ae0[ 	]+ba 81c2 <start5\+0xee>
+[ 	]+81b8:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81ba:[ 	]+6ffd 427e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e42 <endp32\+0xfffe7a74>\],p0
+[ 	]+81c2:[ 	]+f720[ 	]+bne 81ba <start5\+0xe6>
+[ 	]+81c4:[ 	]+0ae0[ 	]+ba 81d0 <start5\+0xfc>
+[ 	]+81c6:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81c8:[ 	]+6ffd 347e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e34 <endp32\+0xfffe7a66>\],p0
+[ 	]+81d0:[ 	]+f760[ 	]+bpl 81c8 <start5\+0xf4>
+[ 	]+81d2:[ 	]+0ae0[ 	]+ba 81de <start5\+0x10a>
+[ 	]+81d4:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81d6:[ 	]+6ffd 267e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e26 <endp32\+0xfffe7a58>\],p0
+[ 	]+81de:[ 	]+f740[ 	]+bvc 81d6 <start5\+0x102>
+[ 	]+81e0:[ 	]+0ae0[ 	]+ba 81ec <start5\+0x118>
+[ 	]+81e2:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81e4:[ 	]+6ffd 187e ffff 3f0e[ 	]+move \[pc=pc\+ffff7e18 <endp32\+0xfffe7a4a>\],p0
+[ 	]+81ec:[ 	]+f750[ 	]+bvs 81e4 <start5\+0x110>
+0+81ee <start6>:
+[ 	]+81ee:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81f0:[ 	]+0ae0[ 	]+ba 81fc <start6\+0xe>
+[ 	]+81f2:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+81f4:[ 	]+6ffd d481 0000 3f0e[ 	]+move \[pc=pc\+81d4 <start5\+0x100>\],p0
+[ 	]+81fc:[ 	]+f7e0[ 	]+ba 81f4 <start6\+0x6>
+[ 	]+81fe:[ 	]+0ae0[ 	]+ba 820a <start6\+0x1c>
+[ 	]+8200:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8202:[ 	]+6ffd c681 0000 3f0e[ 	]+move \[pc=pc\+81c6 <start5\+0xf2>\],p0
+[ 	]+820a:[ 	]+f700[ 	]+bcc 8202 <start6\+0x14>
+[ 	]+820c:[ 	]+0ae0[ 	]+ba 8218 <start6\+0x2a>
+[ 	]+820e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8210:[ 	]+6ffd b881 0000 3f0e[ 	]+move \[pc=pc\+81b8 <start5\+0xe4>\],p0
+[ 	]+8218:[ 	]+f710[ 	]+bcs 8210 <start6\+0x22>
+[ 	]+821a:[ 	]+0ae0[ 	]+ba 8226 <start6\+0x38>
+[ 	]+821c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+821e:[ 	]+6ffd aa81 0000 3f0e[ 	]+move \[pc=pc\+81aa <start5\+0xd6>\],p0
+[ 	]+8226:[ 	]+f730[ 	]+beq 821e <start6\+0x30>
+[ 	]+8228:[ 	]+0ae0[ 	]+ba 8234 <start6\+0x46>
+[ 	]+822a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+822c:[ 	]+6ffd 9c81 0000 3f0e[ 	]+move \[pc=pc\+819c <start5\+0xc8>\],p0
+[ 	]+8234:[ 	]+f7f0[ 	]+bwf 822c <start6\+0x3e>
+[ 	]+8236:[ 	]+0ae0[ 	]+ba 8242 <start6\+0x54>
+[ 	]+8238:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+823a:[ 	]+6ffd 8e81 0000 3f0e[ 	]+move \[pc=pc\+818e <start5\+0xba>\],p0
+[ 	]+8242:[ 	]+f7f0[ 	]+bwf 823a <start6\+0x4c>
+[ 	]+8244:[ 	]+0ae0[ 	]+ba 8250 <start6\+0x62>
+[ 	]+8246:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8248:[ 	]+6ffd 8081 0000 3f0e[ 	]+move \[pc=pc\+8180 <start5\+0xac>\],p0
+[ 	]+8250:[ 	]+f7f0[ 	]+bwf 8248 <start6\+0x5a>
+[ 	]+8252:[ 	]+0ae0[ 	]+ba 825e <start6\+0x70>
+[ 	]+8254:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8256:[ 	]+6ffd 7281 0000 3f0e[ 	]+move \[pc=pc\+8172 <start5\+0x9e>\],p0
+[ 	]+825e:[ 	]+f7a0[ 	]+bge 8256 <start6\+0x68>
+[ 	]+8260:[ 	]+0ae0[ 	]+ba 826c <start6\+0x7e>
+[ 	]+8262:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8264:[ 	]+6ffd 6481 0000 3f0e[ 	]+move \[pc=pc\+8164 <start5\+0x90>\],p0
+[ 	]+826c:[ 	]+f7c0[ 	]+bgt 8264 <start6\+0x76>
+[ 	]+826e:[ 	]+0ae0[ 	]+ba 827a <start6\+0x8c>
+[ 	]+8270:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8272:[ 	]+6ffd 5681 0000 3f0e[ 	]+move \[pc=pc\+8156 <start5\+0x82>\],p0
+[ 	]+827a:[ 	]+f790[ 	]+bhi 8272 <start6\+0x84>
+[ 	]+827c:[ 	]+0ae0[ 	]+ba 8288 <start6\+0x9a>
+[ 	]+827e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8280:[ 	]+6ffd 4881 0000 3f0e[ 	]+move \[pc=pc\+8148 <start5\+0x74>\],p0
+[ 	]+8288:[ 	]+f700[ 	]+bcc 8280 <start6\+0x92>
+[ 	]+828a:[ 	]+0ae0[ 	]+ba 8296 <start6\+0xa8>
+[ 	]+828c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+828e:[ 	]+6ffd 3a81 0000 3f0e[ 	]+move \[pc=pc\+813a <start5\+0x66>\],p0
+[ 	]+8296:[ 	]+f7d0[ 	]+ble 828e <start6\+0xa0>
+[ 	]+8298:[ 	]+0ae0[ 	]+ba 82a4 <start6\+0xb6>
+[ 	]+829a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+829c:[ 	]+6ffd 2c81 0000 3f0e[ 	]+move \[pc=pc\+812c <start5\+0x58>\],p0
+[ 	]+82a4:[ 	]+f710[ 	]+bcs 829c <start6\+0xae>
+[ 	]+82a6:[ 	]+0ae0[ 	]+ba 82b2 <start6\+0xc4>
+[ 	]+82a8:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82aa:[ 	]+6ffd 1e81 0000 3f0e[ 	]+move \[pc=pc\+811e <start5\+0x4a>\],p0
+[ 	]+82b2:[ 	]+f780[ 	]+bls 82aa <start6\+0xbc>
+[ 	]+82b4:[ 	]+0ae0[ 	]+ba 82c0 <start6\+0xd2>
+[ 	]+82b6:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82b8:[ 	]+6ffd 1081 0000 3f0e[ 	]+move \[pc=pc\+8110 <start5\+0x3c>\],p0
+[ 	]+82c0:[ 	]+f7b0[ 	]+blt 82b8 <start6\+0xca>
+[ 	]+82c2:[ 	]+0ae0[ 	]+ba 82ce <start6\+0xe0>
+[ 	]+82c4:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82c6:[ 	]+6ffd 0281 0000 3f0e[ 	]+move \[pc=pc\+8102 <start5\+0x2e>\],p0
+[ 	]+82ce:[ 	]+f770[ 	]+bmi 82c6 <start6\+0xd8>
+[ 	]+82d0:[ 	]+0ae0[ 	]+ba 82dc <start6\+0xee>
+[ 	]+82d2:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82d4:[ 	]+6ffd f480 0000 3f0e[ 	]+move \[pc=pc\+80f4 <start5\+0x20>\],p0
+[ 	]+82dc:[ 	]+f720[ 	]+bne 82d4 <start6\+0xe6>
+[ 	]+82de:[ 	]+0ae0[ 	]+ba 82ea <start6\+0xfc>
+[ 	]+82e0:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82e2:[ 	]+6ffd e680 0000 3f0e[ 	]+move \[pc=pc\+80e6 <start5\+0x12>\],p0
+[ 	]+82ea:[ 	]+f760[ 	]+bpl 82e2 <start6\+0xf4>
+[ 	]+82ec:[ 	]+0ae0[ 	]+ba 82f8 <start6\+0x10a>
+[ 	]+82ee:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82f0:[ 	]+6ffd d880 0000 3f0e[ 	]+move \[pc=pc\+80d8 <start5\+0x4>\],p0
+[ 	]+82f8:[ 	]+f740[ 	]+bvc 82f0 <start6\+0x102>
+[ 	]+82fa:[ 	]+0ae0[ 	]+ba 8306 <start6\+0x118>
+[ 	]+82fc:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+82fe:[ 	]+6ffd ca80 0000 3f0e[ 	]+move \[pc=pc\+80ca <start4\+0xde>\],p0
+[ 	]+8306:[ 	]+f750[ 	]+bvs 82fe <start6\+0x110>
+0+8308 <start7>:
+[ 	]+8308:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+830a:[ 	]+0ae0[ 	]+ba 8316 <start7\+0xe>
+[ 	]+830c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+830e:[ 	]+6ffd ba80 0000 3f0e[ 	]+move \[pc=pc\+80ba <start4\+0xce>\],p0
+[ 	]+8316:[ 	]+f7e0[ 	]+ba 830e <start7\+0x6>
+[ 	]+8318:[ 	]+0ae0[ 	]+ba 8324 <start7\+0x1c>
+[ 	]+831a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+831c:[ 	]+6ffd ac80 0000 3f0e[ 	]+move \[pc=pc\+80ac <start4\+0xc0>\],p0
+[ 	]+8324:[ 	]+f700[ 	]+bcc 831c <start7\+0x14>
+[ 	]+8326:[ 	]+0ae0[ 	]+ba 8332 <start7\+0x2a>
+[ 	]+8328:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+832a:[ 	]+6ffd 9e80 0000 3f0e[ 	]+move \[pc=pc\+809e <start4\+0xb2>\],p0
+[ 	]+8332:[ 	]+f710[ 	]+bcs 832a <start7\+0x22>
+[ 	]+8334:[ 	]+0ae0[ 	]+ba 8340 <start7\+0x38>
+[ 	]+8336:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8338:[ 	]+6ffd 9080 0000 3f0e[ 	]+move \[pc=pc\+8090 <start4\+0xa4>\],p0
+[ 	]+8340:[ 	]+f730[ 	]+beq 8338 <start7\+0x30>
+[ 	]+8342:[ 	]+0ae0[ 	]+ba 834e <start7\+0x46>
+[ 	]+8344:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8346:[ 	]+6ffd 8280 0000 3f0e[ 	]+move \[pc=pc\+8082 <start4\+0x96>\],p0
+[ 	]+834e:[ 	]+f7f0[ 	]+bwf 8346 <start7\+0x3e>
+[ 	]+8350:[ 	]+0ae0[ 	]+ba 835c <start7\+0x54>
+[ 	]+8352:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8354:[ 	]+6ffd 7480 0000 3f0e[ 	]+move \[pc=pc\+8074 <start4\+0x88>\],p0
+[ 	]+835c:[ 	]+f7f0[ 	]+bwf 8354 <start7\+0x4c>
+[ 	]+835e:[ 	]+0ae0[ 	]+ba 836a <start7\+0x62>
+[ 	]+8360:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8362:[ 	]+6ffd 6680 0000 3f0e[ 	]+move \[pc=pc\+8066 <start4\+0x7a>\],p0
+[ 	]+836a:[ 	]+f7f0[ 	]+bwf 8362 <start7\+0x5a>
+[ 	]+836c:[ 	]+0ae0[ 	]+ba 8378 <start7\+0x70>
+[ 	]+836e:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+8370:[ 	]+6ffd 5880 0000 3f0e[ 	]+move \[pc=pc\+8058 <start4\+0x6c>\],p0
+[ 	]+8378:[ 	]+f7a0[ 	]+bge 8370 <start7\+0x68>
+[ 	]+837a:[ 	]+0ae0[ 	]+ba 8386 <start7\+0x7e>
+[ 	]+837c:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+837e:[ 	]+6ffd 4a80 0000 3f0e[ 	]+move \[pc=pc\+804a <start4\+0x5e>\],p0
+[ 	]+8386:[ 	]+f7c0[ 	]+bgt 837e <start7\+0x76>
+[ 	]+8388:[ 	]+0ae0[ 	]+ba 8394 <start7\+0x8c>
+[ 	]+838a:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+838c:[ 	]+6ffd 3c80 0000 3f0e[ 	]+move \[pc=pc\+803c <start4\+0x50>\],p0
+[ 	]+8394:[ 	]+f790[ 	]+bhi 838c <start7\+0x84>
+[ 	]+8396:[ 	]+0ae0[ 	]+ba 83a2 <start7\+0x9a>
+[ 	]+8398:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+839a:[ 	]+6ffd 2e80 0000 3f0e[ 	]+move \[pc=pc\+802e <start4\+0x42>\],p0
+[ 	]+83a2:[ 	]+f700[ 	]+bcc 839a <start7\+0x92>
+[ 	]+83a4:[ 	]+0ae0[ 	]+ba 83b0 <start7\+0xa8>
+[ 	]+83a6:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+83a8:[ 	]+6ffd 2080 0000 3f0e[ 	]+move \[pc=pc\+8020 <start4\+0x34>\],p0
+[ 	]+83b0:[ 	]+f7d0[ 	]+ble 83a8 <start7\+0xa0>
+[ 	]+83b2:[ 	]+0ae0[ 	]+ba 83be <start7\+0xb6>
+[ 	]+83b4:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+83b6:[ 	]+6ffd 1280 0000 3f0e[ 	]+move \[pc=pc\+8012 <start4\+0x26>\],p0
+[ 	]+83be:[ 	]+f710[ 	]+bcs 83b6 <start7\+0xae>
+[ 	]+83c0:[ 	]+0ae0[ 	]+ba 83cc <start7\+0xc4>
+[ 	]+83c2:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+83c4:[ 	]+6ffd 0480 0000 3f0e[ 	]+move \[pc=pc\+8004 <start4\+0x18>\],p0
+[ 	]+83cc:[ 	]+f780[ 	]+bls 83c4 <start7\+0xbc>
+[ 	]+83ce:[ 	]+ffbd fc7f[ 	]+blt 103ce <endp32>
+[ 	]+83d2:[ 	]+ff7d f87f[ 	]+bmi 103ce <endp32>
+[ 	]+83d6:[ 	]+ff2d f47f[ 	]+bne 103ce <endp32>
+[ 	]+83da:[ 	]+ff6d f07f[ 	]+bpl 103ce <endp32>
+[ 	]+83de:[ 	]+ff4d ec7f[ 	]+bvc 103ce <endp32>
+[ 	]+83e2:[ 	]+ff5d e87f[ 	]+bvs 103ce <endp32>
+0+83e6 <start8>:
+[ 	]+83e6:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+83e8:[ 	]+ffed 7a01[ 	]+ba 8566 <endp16>
+[ 	]+83ec:[ 	]+ff0d 7601[ 	]+bhs 8566 <endp16>
+[ 	]+83f0:[ 	]+ff1d 7201[ 	]+blo 8566 <endp16>
+[ 	]+83f4:[ 	]+ff3d 6e01[ 	]+beq 8566 <endp16>
+[ 	]+83f8:[ 	]+fffd 6a01[ 	]+bwf 8566 <endp16>
+[ 	]+83fc:[ 	]+fffd 6601[ 	]+bwf 8566 <endp16>
+[ 	]+8400:[ 	]+fffd 6201[ 	]+bwf 8566 <endp16>
+[ 	]+8404:[ 	]+ffad 5e01[ 	]+bge 8566 <endp16>
+[ 	]+8408:[ 	]+ffcd 5a01[ 	]+bgt 8566 <endp16>
+[ 	]+840c:[ 	]+ff9d 5601[ 	]+bhi 8566 <endp16>
+[ 	]+8410:[ 	]+ff0d 5201[ 	]+bhs 8566 <endp16>
+[ 	]+8414:[ 	]+ffdd 4e01[ 	]+ble 8566 <endp16>
+[ 	]+8418:[ 	]+ff1d 4a01[ 	]+blo 8566 <endp16>
+[ 	]+841c:[ 	]+ff8d 4601[ 	]+bls 8566 <endp16>
+[ 	]+8420:[ 	]+ffbd 4201[ 	]+blt 8566 <endp16>
+[ 	]+8424:[ 	]+ff7d 3e01[ 	]+bmi 8566 <endp16>
+[ 	]+8428:[ 	]+ff2d 3a01[ 	]+bne 8566 <endp16>
+[ 	]+842c:[ 	]+ff6d 3601[ 	]+bpl 8566 <endp16>
+[ 	]+8430:[ 	]+ff4d 3201[ 	]+bvc 8566 <endp16>
+[ 	]+8434:[ 	]+ff5d 2e01[ 	]+bvs 8566 <endp16>
+0+8438 <start9>:
+[ 	]+8438:[ 	]+0f05[ 	]+nop[ 	]*
+[ 	]+843a:[ 	]+ffed 2801[ 	]+ba 8566 <endp16>
+[ 	]+843e:[ 	]+ff0d 2401[ 	]+bhs 8566 <endp16>
+[ 	]+8442:[ 	]+ff1d 2001[ 	]+blo 8566 <endp16>
+[ 	]+8446:[ 	]+ff3d 1c01[ 	]+beq 8566 <endp16>
+[ 	]+844a:[ 	]+fffd 1801[ 	]+bwf 8566 <endp16>
+[ 	]+844e:[ 	]+fffd 1401[ 	]+bwf 8566 <endp16>
+[ 	]+8452:[ 	]+fffd 1001[ 	]+bwf 8566 <endp16>
+[ 	]+8456:[ 	]+ffad 0c01[ 	]+bge 8566 <endp16>
+[ 	]+845a:[ 	]+ffcd 0801[ 	]+bgt 8566 <endp16>
+[ 	]+845e:[ 	]+ff9d 0401[ 	]+bhi 8566 <endp16>
+[ 	]+8462:[ 	]+ff0d 0001[ 	]+bhs 8566 <endp16>
+[ 	]+8466:[ 	]+fed0[ 	]+ble 8566 <endp16>
+[ 	]+8468:[ 	]+fc10[ 	]+bcs 8566 <endp16>
+[ 	]+846a:[ 	]+fa80[ 	]+bls 8566 <endp16>
+[ 	]+846c:[ 	]+f8b0[ 	]+blt 8566 <endp16>
+[ 	]+846e:[ 	]+f670[ 	]+bmi 8566 <endp16>
+[ 	]+8470:[ 	]+f420[ 	]+bne 8566 <endp16>
+[ 	]+8472:[ 	]+f260[ 	]+bpl 8566 <endp16>
+[ 	]+8474:[ 	]+f040[ 	]+bvc 8566 <endp16>
+[ 	]+8476:[ 	]+ee50[ 	]+bvs 8566 <endp16>
+0+8478 <start10>:
+[ 	]+8478:[ 	]+28e0[ 	]+ba 84a2 <end>
+[ 	]+847a:[ 	]+2600[ 	]+bcc 84a2 <end>
+[ 	]+847c:[ 	]+2410[ 	]+bcs 84a2 <end>
+[ 	]+847e:[ 	]+2230[ 	]+beq 84a2 <end>
+[ 	]+8480:[ 	]+20f0[ 	]+bwf 84a2 <end>
+[ 	]+8482:[ 	]+1ef0[ 	]+bwf 84a2 <end>
+[ 	]+8484:[ 	]+1cf0[ 	]+bwf 84a2 <end>
+[ 	]+8486:[ 	]+1aa0[ 	]+bge 84a2 <end>
+[ 	]+8488:[ 	]+18c0[ 	]+bgt 84a2 <end>
+[ 	]+848a:[ 	]+1690[ 	]+bhi 84a2 <end>
+[ 	]+848c:[ 	]+1400[ 	]+bcc 84a2 <end>
+[ 	]+848e:[ 	]+12d0[ 	]+ble 84a2 <end>
+[ 	]+8490:[ 	]+1010[ 	]+bcs 84a2 <end>
+[ 	]+8492:[ 	]+0e80[ 	]+bls 84a2 <end>
+[ 	]+8494:[ 	]+0cb0[ 	]+blt 84a2 <end>
+[ 	]+8496:[ 	]+0a70[ 	]+bmi 84a2 <end>
+[ 	]+8498:[ 	]+0820[ 	]+bne 84a2 <end>
+[ 	]+849a:[ 	]+0660[ 	]+bpl 84a2 <end>
+[ 	]+849c:[ 	]+0440[ 	]+bvc 84a2 <end>
+[ 	]+849e:[ 	]+0250[ 	]+bvs 84a2 <end>
+[ 	]+84a0:[ 	]+0f05[ 	]+nop[ ]*
+0+84a2 <end>:
+[	 ]+84a2:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+8566 <endp16>:
+[	 ]+8566:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+103ce <endp32>:
+[	 ]+103ce:[	 ]+0f05[ 	]+nop[ ]*
diff --git a/gas/testsuite/gas/cris/rd-break32.d b/gas/testsuite/gas/cris/rd-break32.d
new file mode 100644
index 000000000000..ba7c518e057b
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-break32.d
@@ -0,0 +1,28 @@
+#as: --march=v32 --em=criself
+#source: break.s
+#objdump: -dr
+
+.*:[ 	]+file format .*-cris
+
+Disassembly of section \.text:
+0+ <start>:
+[	 ]+0:[	 ]+32e9[ 	]+break[ ]+2
+[	 ]+2:[	 ]+30e9[ 	]+break[ ]+0
+[	 ]+4:[	 ]+31e9[ 	]+break[ ]+1
+[	 ]+6:[	 ]+32e9[ 	]+break[ ]+2
+[	 ]+8:[	 ]+33e9[ 	]+break[ ]+3
+[	 ]+a:[	 ]+34e9[ 	]+break[ ]+4
+[	 ]+c:[	 ]+35e9[ 	]+break[ ]+5
+[	 ]+e:[	 ]+36e9[ 	]+break[ ]+6
+[	 ]+10:[	 ]+37e9[ 	]+break[ ]+7
+[	 ]+12:[	 ]+38e9[ 	]+break[ ]+8
+[	 ]+14:[	 ]+39e9[ 	]+break[ ]+9
+[	 ]+16:[	 ]+3ae9[ 	]+break[ ]+10
+[	 ]+18:[	 ]+3be9[ 	]+break[ ]+11
+[	 ]+1a:[	 ]+3ce9[ 	]+break[ ]+12
+[	 ]+1c:[	 ]+3de9[ 	]+break[ ]+13
+[	 ]+1e:[	 ]+3ee9[ 	]+break[ ]+14
+[	 ]+20:[	 ]+3fe9[ 	]+break[ ]+15
+
+0+22 <end>:
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-brokw-pic-1.d b/gas/testsuite/gas/cris/rd-brokw-pic-1.d
new file mode 100644
index 000000000000..502796817bfb
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-brokw-pic-1.d
@@ -0,0 +1,21 @@
+#objdump: -dr
+#as: --pic
+#source: brokw-1.s
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+0+ <sym2>:
+[	 ]+0:[	 ]+4002[ 	]+moveq[ ]+0,\$?r0
+[	 ]+2:[	 ]+0c00[ 	]+bcc[ ]+(0x10|10 <sym2\+0x10>)
+[	 ]+4:[	 ]+4102[ 	]+moveq[ ]+1,\$?r0
+[	 ]+6:[	 ]+0ce0[ 	]+ba[ ]+(0x14|14 <next_label>)
+[	 ]+8:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+a:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+c:[	 ]+6ffd 0280 0000 3f0e[ 	]+move \[\$?pc=\$?pc\+8002 <next_label\+0x7fee>\],\$?p0
+0+14 <next_label>:
+[	 ]+14:[	 ]+4202[ 	]+moveq[ ]+2,\$?r0
+^[ 	]+\.\.\.
+0+8014 <sym1>:
+[	 ]+8014:[	 ]+4302[ 	]+moveq[ ]+3,\$?r0
+^[ 	]+\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-brokw-pic-2.d b/gas/testsuite/gas/cris/rd-brokw-pic-2.d
new file mode 100644
index 000000000000..30ca1f5b83dd
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-brokw-pic-2.d
@@ -0,0 +1,24 @@
+#objdump: -dr
+#as: --pic
+#source: brokw-2.s
+
+.*:     file format .*-cris
+Disassembly of section \.text:
+0+ <sym2>:
+[	 ]+0:[	 ]+4002[ 	]+moveq[ ]+0,\$?r0
+[	 ]+2:[	 ]+1600[ 	]+bcc[ ]+(0x1a|1a <sym2\+0x1a>)
+[	 ]+4:[	 ]+0e00[ 	]+bcc[ ]+(0x14|14 <sym2\+0x14>)
+[	 ]+6:[	 ]+4102[ 	]+moveq[ ]+1,\$?r0
+[	 ]+8:[	 ]+14e0[ 	]+ba[ ]+(0x1e|1e <next_label>)
+[	 ]+a:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+c:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+e:[	 ]+6ffd 0c80 0000 3f0e[ 	]+move \[\$?pc=\$?pc\+800c <next_label\+0x7fee>\],\$?p0
+[	 ]+16:[	 ]+6ffd 0280 0000 3f0e[ 	]+move \[\$?pc=\$?pc\+8002 <next_label\+0x7fe4>\],\$?p0
+0+1e <next_label>:
+[	 ]+1e:[	 ]+4202[ 	]+moveq[ ]+2,\$?r0
+^[ 	]+\.\.\.
+0+801e <sym1>:
+[	 ]+801e:[	 ]+4302[ 	]+moveq[ ]+3,\$?r0
+0+8020 <sym3>:
+[	 ]+8020:[	 ]+4402[ 	]+moveq[ ]+4,\$?r0
+^[ 	]+\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-brokw-pic-3.d b/gas/testsuite/gas/cris/rd-brokw-pic-3.d
new file mode 100644
index 000000000000..bf3170cb25f0
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-brokw-pic-3.d
@@ -0,0 +1,187 @@
+#objdump: -dr
+#as: --underscore --pic --em=criself
+#source: brokw-3.s
+
+.*:     file format .*-cris
+Disassembly of section \.text:
+0+ <start>:
+[	 ]+0:[	 ]+4002[ 	]+moveq[ ]+0,\$?r0
+[	 ]+2:[	 ]+af0c 5700[ 	]+subs\.b 87,\$?r0
+[	 ]+6:[	 ]+cf0d 2900[ 	]+bound\.b 0x29,\$?r0
+[	 ]+a:[	 ]+5f05 3ff8[ 	]+adds\.w \[\$?pc\+\$?r0\.w\],\$?pc
+0+e <sym2>:
+[ 	]+e:[ 	]+b401[ 	]+case 87: -> 1c2 <sym2\+0x1b4>
+[ 	]+10:[ 	]+ac01[ 	]+case 88: -> 1ba <sym2\+0x1ac>
+[ 	]+12:[ 	]+a401[ 	]+case 89: -> 1b2 <sym2\+0x1a4>
+[ 	]+14:[ 	]+9c01[ 	]+case 90: -> 1aa <sym2\+0x19c>
+[ 	]+16:[ 	]+9401[ 	]+case 91: -> 1a2 <sym2\+0x194>
+[ 	]+18:[ 	]+8c01[ 	]+case 92: -> 19a <sym2\+0x18c>
+[ 	]+1a:[ 	]+8401[ 	]+case 93: -> 192 <sym2\+0x184>
+[ 	]+1c:[ 	]+7c01[ 	]+case 94: -> 18a <sym2\+0x17c>
+[ 	]+1e:[ 	]+7401[ 	]+case 95: -> 182 <sym2\+0x174>
+[ 	]+20:[ 	]+6c01[ 	]+case 96: -> 17a <sym2\+0x16c>
+[ 	]+22:[ 	]+6401[ 	]+case 97: -> 172 <sym2\+0x164>
+[ 	]+24:[ 	]+5c01[ 	]+case 98: -> 16a <sym2\+0x15c>
+[ 	]+26:[ 	]+5401[ 	]+case 99: -> 162 <sym2\+0x154>
+[ 	]+28:[ 	]+4c01[ 	]+case 100: -> 15a <sym2\+0x14c>
+[ 	]+2a:[ 	]+4401[ 	]+case 101: -> 152 <sym2\+0x144>
+[ 	]+2c:[ 	]+3c01[ 	]+case 102: -> 14a <sym2\+0x13c>
+[ 	]+2e:[ 	]+3401[ 	]+case 103: -> 142 <sym2\+0x134>
+[ 	]+30:[ 	]+2c01[ 	]+case 104: -> 13a <sym2\+0x12c>
+[ 	]+32:[ 	]+2401[ 	]+case 105: -> 132 <sym2\+0x124>
+[ 	]+34:[ 	]+1c01[ 	]+case 106: -> 12a <sym2\+0x11c>
+[ 	]+36:[ 	]+1401[ 	]+case 107: -> 122 <sym2\+0x114>
+[ 	]+38:[ 	]+0c01[ 	]+case 108: -> 11a <sym2\+0x10c>
+[ 	]+3a:[ 	]+0401[ 	]+case 109: -> 112 <sym2\+0x104>
+[ 	]+3c:[ 	]+fc00[ 	]+case 110: -> 10a <sym2\+0xfc>
+[ 	]+3e:[ 	]+f400[ 	]+case 111: -> 102 <sym2\+0xf4>
+[ 	]+40:[ 	]+ec00[ 	]+case 112: -> fa <sym2\+0xec>
+[ 	]+42:[ 	]+e400[ 	]+case 113: -> f2 <sym2\+0xe4>
+[ 	]+44:[ 	]+dc00[ 	]+case 114: -> ea <sym2\+0xdc>
+[ 	]+46:[ 	]+d400[ 	]+case 115: -> e2 <sym2\+0xd4>
+[ 	]+48:[ 	]+cc00[ 	]+case 116: -> da <sym2\+0xcc>
+[ 	]+4a:[ 	]+c400[ 	]+case 117: -> d2 <sym2\+0xc4>
+[ 	]+4c:[ 	]+bc00[ 	]+case 118: -> ca <sym2\+0xbc>
+[ 	]+4e:[ 	]+b400[ 	]+case 119: -> c2 <sym2\+0xb4>
+[ 	]+50:[ 	]+ac00[ 	]+case 120: -> ba <sym2\+0xac>
+[ 	]+52:[ 	]+a400[ 	]+case 121: -> b2 <sym2\+0xa4>
+[ 	]+54:[ 	]+9c00[ 	]+case 122: -> aa <sym2\+0x9c>
+[ 	]+56:[ 	]+9400[ 	]+case 123: -> a2 <sym2\+0x94>
+[ 	]+58:[ 	]+8c00[ 	]+case 124: -> 9a <sym2\+0x8c>
+[ 	]+5a:[ 	]+8400[ 	]+case 125: -> 92 <sym2\+0x84>
+[ 	]+5c:[ 	]+7c00[ 	]+case 126: -> 8a <sym2\+0x7c>
+[ 	]+5e:[ 	]+7400[ 	]+case 127: -> 82 <sym2\+0x74>
+[ 	]+60:[ 	]+6c00[ 	]+case 128/default: -> 7a <sym2\+0x6c>
+^[ 	]+\.\.\.
+[	 ]+72:[	 ]+4102[ 	]+moveq[ ]+1,\$?r0
+[	 ]+74:[	 ]+ffed 5201[ 	]+ba 1ca <next_label>
+[	 ]+78:[	 ]+0f05[ 	]+nop[ ]*
+[ 	]+7a:[ 	]+6ffd 9e81 0000 3f0e[ 	]+move \[pc=pc\+819e <next_label\+0x7fd4>\],p0
+[ 	]+82:[ 	]+6ffd 9481 0000 3f0e[ 	]+move \[pc=pc\+8194 <next_label\+0x7fca>\],p0
+[ 	]+8a:[ 	]+6ffd 8a81 0000 3f0e[ 	]+move \[pc=pc\+818a <next_label\+0x7fc0>\],p0
+[ 	]+92:[ 	]+6ffd 8081 0000 3f0e[ 	]+move \[pc=pc\+8180 <next_label\+0x7fb6>\],p0
+[ 	]+9a:[ 	]+6ffd 7681 0000 3f0e[ 	]+move \[pc=pc\+8176 <next_label\+0x7fac>\],p0
+[ 	]+a2:[ 	]+6ffd 6c81 0000 3f0e[ 	]+move \[pc=pc\+816c <next_label\+0x7fa2>\],p0
+[ 	]+aa:[ 	]+6ffd 6281 0000 3f0e[ 	]+move \[pc=pc\+8162 <next_label\+0x7f98>\],p0
+[ 	]+b2:[ 	]+6ffd 5881 0000 3f0e[ 	]+move \[pc=pc\+8158 <next_label\+0x7f8e>\],p0
+[ 	]+ba:[ 	]+6ffd 4e81 0000 3f0e[ 	]+move \[pc=pc\+814e <next_label\+0x7f84>\],p0
+[ 	]+c2:[ 	]+6ffd 4481 0000 3f0e[ 	]+move \[pc=pc\+8144 <next_label\+0x7f7a>\],p0
+[ 	]+ca:[ 	]+6ffd 3a81 0000 3f0e[ 	]+move \[pc=pc\+813a <next_label\+0x7f70>\],p0
+[ 	]+d2:[ 	]+6ffd 3081 0000 3f0e[ 	]+move \[pc=pc\+8130 <next_label\+0x7f66>\],p0
+[ 	]+da:[ 	]+6ffd 2681 0000 3f0e[ 	]+move \[pc=pc\+8126 <next_label\+0x7f5c>\],p0
+[ 	]+e2:[ 	]+6ffd 1c81 0000 3f0e[ 	]+move \[pc=pc\+811c <next_label\+0x7f52>\],p0
+[ 	]+ea:[ 	]+6ffd 1281 0000 3f0e[ 	]+move \[pc=pc\+8112 <next_label\+0x7f48>\],p0
+[ 	]+f2:[ 	]+6ffd 0881 0000 3f0e[ 	]+move \[pc=pc\+8108 <next_label\+0x7f3e>\],p0
+[ 	]+fa:[ 	]+6ffd fe80 0000 3f0e[ 	]+move \[pc=pc\+80fe <next_label\+0x7f34>\],p0
+[ 	]+102:[ 	]+6ffd f480 0000 3f0e[ 	]+move \[pc=pc\+80f4 <next_label\+0x7f2a>\],p0
+[ 	]+10a:[ 	]+6ffd ea80 0000 3f0e[ 	]+move \[pc=pc\+80ea <next_label\+0x7f20>\],p0
+[ 	]+112:[ 	]+6ffd e080 0000 3f0e[ 	]+move \[pc=pc\+80e0 <next_label\+0x7f16>\],p0
+[ 	]+11a:[ 	]+6ffd d680 0000 3f0e[ 	]+move \[pc=pc\+80d6 <next_label\+0x7f0c>\],p0
+[ 	]+122:[ 	]+6ffd cc80 0000 3f0e[ 	]+move \[pc=pc\+80cc <next_label\+0x7f02>\],p0
+[ 	]+12a:[ 	]+6ffd c280 0000 3f0e[ 	]+move \[pc=pc\+80c2 <next_label\+0x7ef8>\],p0
+[ 	]+132:[ 	]+6ffd b880 0000 3f0e[ 	]+move \[pc=pc\+80b8 <next_label\+0x7eee>\],p0
+[ 	]+13a:[ 	]+6ffd ae80 0000 3f0e[ 	]+move \[pc=pc\+80ae <next_label\+0x7ee4>\],p0
+[ 	]+142:[ 	]+6ffd a480 0000 3f0e[ 	]+move \[pc=pc\+80a4 <next_label\+0x7eda>\],p0
+[ 	]+14a:[ 	]+6ffd 9a80 0000 3f0e[ 	]+move \[pc=pc\+809a <next_label\+0x7ed0>\],p0
+[ 	]+152:[ 	]+6ffd 9080 0000 3f0e[ 	]+move \[pc=pc\+8090 <next_label\+0x7ec6>\],p0
+[ 	]+15a:[ 	]+6ffd 8680 0000 3f0e[ 	]+move \[pc=pc\+8086 <next_label\+0x7ebc>\],p0
+[ 	]+162:[ 	]+6ffd 7c80 0000 3f0e[ 	]+move \[pc=pc\+807c <next_label\+0x7eb2>\],p0
+[ 	]+16a:[ 	]+6ffd 7280 0000 3f0e[ 	]+move \[pc=pc\+8072 <next_label\+0x7ea8>\],p0
+[ 	]+172:[ 	]+6ffd 6880 0000 3f0e[ 	]+move \[pc=pc\+8068 <next_label\+0x7e9e>\],p0
+[ 	]+17a:[ 	]+6ffd 5e80 0000 3f0e[ 	]+move \[pc=pc\+805e <next_label\+0x7e94>\],p0
+[ 	]+182:[ 	]+6ffd 5480 0000 3f0e[ 	]+move \[pc=pc\+8054 <next_label\+0x7e8a>\],p0
+[ 	]+18a:[ 	]+6ffd 4a80 0000 3f0e[ 	]+move \[pc=pc\+804a <next_label\+0x7e80>\],p0
+[ 	]+192:[ 	]+6ffd 4080 0000 3f0e[ 	]+move \[pc=pc\+8040 <next_label\+0x7e76>\],p0
+[ 	]+19a:[ 	]+6ffd 3680 0000 3f0e[ 	]+move \[pc=pc\+8036 <next_label\+0x7e6c>\],p0
+[ 	]+1a2:[ 	]+6ffd 2c80 0000 3f0e[ 	]+move \[pc=pc\+802c <next_label\+0x7e62>\],p0
+[ 	]+1aa:[ 	]+6ffd 2280 0000 3f0e[ 	]+move \[pc=pc\+8022 <next_label\+0x7e58>\],p0
+[ 	]+1b2:[ 	]+6ffd 1880 0000 3f0e[ 	]+move \[pc=pc\+8018 <next_label\+0x7e4e>\],p0
+[ 	]+1ba:[ 	]+6ffd 0e80 0000 3f0e[ 	]+move \[pc=pc\+800e <next_label\+0x7e44>\],p0
+[ 	]+1c2:[ 	]+6ffd 0480 0000 3f0e[ 	]+move \[pc=pc\+8004 <next_label\+0x7e3a>\],p0
+0+1ca <next_label>:
+[	 ]+1ca:[	 ]+4202[ 	]+moveq[ ]+2,\$?r0
+^[ 	]+\.\.\.
+0+81cc <sym1>:
+[ 	]+81cc:[ 	]+7d02[ 	]+moveq -3,\$?r0
+0+81ce <sym3>:
+[ 	]+81ce:[ 	]+4302[ 	]+moveq 3,\$?r0
+0+81d0 <sym4>:
+[ 	]+81d0:[ 	]+4402[ 	]+moveq 4,\$?r0
+0+81d2 <sym5>:
+[ 	]+81d2:[ 	]+4502[ 	]+moveq 5,\$?r0
+0+81d4 <sym6>:
+[ 	]+81d4:[ 	]+4602[ 	]+moveq 6,\$?r0
+0+81d6 <sym7>:
+[ 	]+81d6:[ 	]+4702[ 	]+moveq 7,\$?r0
+0+81d8 <sym8>:
+[ 	]+81d8:[ 	]+4802[ 	]+moveq 8,\$?r0
+0+81da <sym9>:
+[ 	]+81da:[ 	]+4902[ 	]+moveq 9,\$?r0
+0+81dc <sym10>:
+[ 	]+81dc:[ 	]+4a02[ 	]+moveq 10,\$?r0
+0+81de <sym11>:
+[ 	]+81de:[ 	]+4b02[ 	]+moveq 11,\$?r0
+0+81e0 <sym12>:
+[ 	]+81e0:[ 	]+4c02[ 	]+moveq 12,\$?r0
+0+81e2 <sym13>:
+[ 	]+81e2:[ 	]+4d02[ 	]+moveq 13,\$?r0
+0+81e4 <sym14>:
+[ 	]+81e4:[ 	]+4e02[ 	]+moveq 14,\$?r0
+0+81e6 <sym15>:
+[ 	]+81e6:[ 	]+4f02[ 	]+moveq 15,\$?r0
+0+81e8 <sym16>:
+[ 	]+81e8:[ 	]+5002[ 	]+moveq 16,\$?r0
+0+81ea <sym17>:
+[ 	]+81ea:[ 	]+5102[ 	]+moveq 17,\$?r0
+0+81ec <sym18>:
+[ 	]+81ec:[ 	]+5202[ 	]+moveq 18,\$?r0
+0+81ee <sym19>:
+[ 	]+81ee:[ 	]+5302[ 	]+moveq 19,\$?r0
+0+81f0 <sym20>:
+[ 	]+81f0:[ 	]+5402[ 	]+moveq 20,\$?r0
+0+81f2 <sym21>:
+[ 	]+81f2:[ 	]+5502[ 	]+moveq 21,\$?r0
+0+81f4 <sym22>:
+[ 	]+81f4:[ 	]+5602[ 	]+moveq 22,\$?r0
+0+81f6 <sym23>:
+[ 	]+81f6:[ 	]+5702[ 	]+moveq 23,\$?r0
+0+81f8 <sym24>:
+[ 	]+81f8:[ 	]+5802[ 	]+moveq 24,\$?r0
+0+81fa <sym25>:
+[ 	]+81fa:[ 	]+5902[ 	]+moveq 25,\$?r0
+0+81fc <sym26>:
+[ 	]+81fc:[ 	]+5a02[ 	]+moveq 26,\$?r0
+0+81fe <sym27>:
+[ 	]+81fe:[ 	]+5b02[ 	]+moveq 27,\$?r0
+0+8200 <sym28>:
+[ 	]+8200:[ 	]+5c02[ 	]+moveq 28,\$?r0
+0+8202 <sym29>:
+[ 	]+8202:[ 	]+5d02[ 	]+moveq 29,\$?r0
+0+8204 <sym30>:
+[ 	]+8204:[ 	]+5e02[ 	]+moveq 30,\$?r0
+0+8206 <sym31>:
+[ 	]+8206:[ 	]+5f02[ 	]+moveq 31,\$?r0
+0+8208 <sym32>:
+[ 	]+8208:[ 	]+6002[ 	]+moveq -32,\$?r0
+0+820a <sym33>:
+[ 	]+820a:[ 	]+6102[ 	]+moveq -31,\$?r0
+0+820c <sym34>:
+[ 	]+820c:[ 	]+6202[ 	]+moveq -30,\$?r0
+0+820e <sym35>:
+[ 	]+820e:[ 	]+6302[ 	]+moveq -29,\$?r0
+0+8210 <sym36>:
+[ 	]+8210:[ 	]+6402[ 	]+moveq -28,\$?r0
+0+8212 <sym37>:
+[ 	]+8212:[ 	]+6502[ 	]+moveq -27,\$?r0
+0+8214 <sym38>:
+[ 	]+8214:[ 	]+6602[ 	]+moveq -26,\$?r0
+0+8216 <sym39>:
+[ 	]+8216:[ 	]+6702[ 	]+moveq -25,\$?r0
+0+8218 <sym40>:
+[ 	]+8218:[ 	]+6802[ 	]+moveq -24,\$?r0
+0+821a <sym41>:
+[ 	]+821a:[ 	]+6902[ 	]+moveq -23,\$?r0
+0+821c <sym42>:
+[ 	]+821c:[ 	]+6a02[ 	]+moveq -22,\$?r0
+0+821e <sym43>:
+[ 	]+821e:[ 	]+6b02[ 	]+moveq -21,\$?r0
diff --git a/gas/testsuite/gas/cris/rd-dw2-1.d b/gas/testsuite/gas/cris/rd-dw2-1.d
index fa9da0c02f8c..3b0dc61d5499 100644
--- a/gas/testsuite/gas/cris/rd-dw2-1.d
+++ b/gas/testsuite/gas/cris/rd-dw2-1.d
@@ -1,52 +1,21 @@
 #readelf: -wl
 #source: addi.s
 #as: --em=criself --gdwarf2
-
 # A most simple instruction sequence.
-
-Dump of debug contents of section \.debug_line:
-
-  Length:                      .*
-  DWARF Version:               2
-  Prologue Length:             .*
-  Minimum Instruction Length:  2
-  Initial value of 'is_stmt':  1
-  Line Base:                   -5
-  Line Range:                  14
-  Opcode Base:                 10
-  \(Pointer size:               4\)
-
- Opcodes:
-  Opcode 1 has 0 args
-  Opcode 2 has 1 args
-  Opcode 3 has 1 args
-  Opcode 4 has 1 args
-  Opcode 5 has 1 args
-  Opcode 6 has 0 args
-  Opcode 7 has 0 args
-  Opcode 8 has 0 args
-  Opcode 9 has 1 args
-
- The Directory Table:
-  .*/gas/testsuite/gas/cris
-
- The File Name Table:
-  Entry	Dir	Time	Size	Name
-  1	1	0	0	addi\.s
-
+#...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 9: advance Address by 0 to 0x0 and Line by 4 to 5
-  Special opcode 20: advance Address by 2 to 0x2 and Line by 1 to 6
-  Special opcode 20: advance Address by 2 to 0x4 and Line by 1 to 7
-  Special opcode 20: advance Address by 2 to 0x6 and Line by 1 to 8
-  Special opcode 20: advance Address by 2 to 0x8 and Line by 1 to 9
-  Special opcode 20: advance Address by 2 to 0xa and Line by 1 to 10
-  Special opcode 20: advance Address by 2 to 0xc and Line by 1 to 11
-  Special opcode 20: advance Address by 2 to 0xe and Line by 1 to 12
-  Special opcode 20: advance Address by 2 to 0x10 and Line by 1 to 13
-  Special opcode 20: advance Address by 2 to 0x12 and Line by 1 to 14
-  Special opcode 20: advance Address by 2 to 0x14 and Line by 1 to 15
-  Special opcode 20: advance Address by 2 to 0x16 and Line by 1 to 16
-  Advance PC by 2 to 18
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 4 to 5
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 6
+  Special opcode .*: advance Address by 2 to 0x4 and Line by 1 to 7
+  Special opcode .*: advance Address by 2 to 0x6 and Line by 1 to 8
+  Special opcode .*: advance Address by 2 to 0x8 and Line by 1 to 9
+  Special opcode .*: advance Address by 2 to 0xa and Line by 1 to 10
+  Special opcode .*: advance Address by 2 to 0xc and Line by 1 to 11
+  Special opcode .*: advance Address by 2 to 0xe and Line by 1 to 12
+  Special opcode .*: advance Address by 2 to 0x10 and Line by 1 to 13
+  Special opcode .*: advance Address by 2 to 0x12 and Line by 1 to 14
+  Special opcode .*: advance Address by 2 to 0x14 and Line by 1 to 15
+  Special opcode .*: advance Address by 2 to 0x16 and Line by 1 to 16
+  Advance PC by 2 to 0x18
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-10.d b/gas/testsuite/gas/cris/rd-dw2-10.d
index 2513a4b9dc90..f9b196f9b9aa 100644
--- a/gas/testsuite/gas/cris/rd-dw2-10.d
+++ b/gas/testsuite/gas/cris/rd-dw2-10.d
@@ -6,6 +6,6 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 11: advance Address by 0 to 0x0 and Line by 6 to 7
-  Advance PC by 4 to 4
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 6 to 7
+  Advance PC by 4 to 0x4
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-11.d b/gas/testsuite/gas/cris/rd-dw2-11.d
index da5aedbbf858..ea88664d7bfd 100644
--- a/gas/testsuite/gas/cris/rd-dw2-11.d
+++ b/gas/testsuite/gas/cris/rd-dw2-11.d
@@ -6,41 +6,41 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 9: advance Address by 0 to 0x0 and Line by 4 to 5
-  Special opcode 20: advance Address by 2 to 0x2 and Line by 1 to 6
-  Advance PC by 126 to 80
-  Special opcode 7: advance Address by 0 to 0x80 and Line by 2 to 8
-  Special opcode 20: advance Address by 2 to 0x82 and Line by 1 to 9
-  Advance PC by 226 to 164
-  Special opcode 11: advance Address by 0 to 0x164 and Line by 6 to 15
-  Special opcode 34: advance Address by 4 to 0x168 and Line by 1 to 16
-  Advance PC by 126 to 1e6
-  Special opcode 7: advance Address by 0 to 0x1e6 and Line by 2 to 18
-  Special opcode 34: advance Address by 4 to 0x1ea and Line by 1 to 19
-  Advance PC by 1126 to 650
-  Special opcode 11: advance Address by 0 to 0x650 and Line by 6 to 25
-  Special opcode 34: advance Address by 4 to 0x654 and Line by 1 to 26
-  Advance PC by 126 to 6d2
-  Special opcode 7: advance Address by 0 to 0x6d2 and Line by 2 to 28
-  Special opcode 90: advance Address by 12 to 0x6de and Line by 1 to 29
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 4 to 5
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 6
+  Advance PC by 126 to 0x80
+  Special opcode .*: advance Address by 0 to 0x80 and Line by 2 to 8
+  Special opcode .*: advance Address by 2 to 0x82 and Line by 1 to 9
+  Advance PC by 226 to 0x164
+  Special opcode .*: advance Address by 0 to 0x164 and Line by 6 to 15
+  Special opcode .*: advance Address by 4 to 0x168 and Line by 1 to 16
+  Advance PC by 126 to 0x1e6
+  Special opcode .*: advance Address by 0 to 0x1e6 and Line by 2 to 18
+  Special opcode .*: advance Address by 4 to 0x1ea and Line by 1 to 19
+  Advance PC by 1126 to 0x650
+  Special opcode .*: advance Address by 0 to 0x650 and Line by 6 to 25
+  Special opcode .*: advance Address by 4 to 0x654 and Line by 1 to 26
+  Advance PC by 126 to 0x6d2
+  Special opcode .*: advance Address by 0 to 0x6d2 and Line by 2 to 28
+  Special opcode .*: advance Address by 12 to 0x6de and Line by 1 to 29
   Advance Line by 11 to 40
-  Advance PC by 33250 to 88c0
+  Advance PC by 33250 to 0x88c0
   Copy
-  Special opcode 20: advance Address by 2 to 0x88c2 and Line by 1 to 41
-  Advance PC by 128 to 8942
-  Special opcode 7: advance Address by 0 to 0x8942 and Line by 2 to 43
-  Special opcode 20: advance Address by 2 to 0x8944 and Line by 1 to 44
-  Advance PC by 248 to 8a3c
-  Special opcode 11: advance Address by 0 to 0x8a3c and Line by 6 to 50
-  Special opcode 34: advance Address by 4 to 0x8a40 and Line by 1 to 51
-  Advance PC by 128 to 8ac0
-  Special opcode 7: advance Address by 0 to 0x8ac0 and Line by 2 to 53
-  Special opcode 34: advance Address by 4 to 0x8ac4 and Line by 1 to 54
-  Advance PC by 252 to 8bc0
-  Special opcode 11: advance Address by 0 to 0x8bc0 and Line by 6 to 60
-  Special opcode 34: advance Address by 4 to 0x8bc4 and Line by 1 to 61
-  Advance PC by 128 to 8c44
-  Special opcode 7: advance Address by 0 to 0x8c44 and Line by 2 to 63
-  Special opcode 34: advance Address by 4 to 0x8c48 and Line by 1 to 64
-  Advance PC by 124 to 8cc4
+  Special opcode .*: advance Address by 2 to 0x88c2 and Line by 1 to 41
+  Advance PC by 128 to 0x8942
+  Special opcode .*: advance Address by 0 to 0x8942 and Line by 2 to 43
+  Special opcode .*: advance Address by 2 to 0x8944 and Line by 1 to 44
+  Advance PC by 248 to 0x8a3c
+  Special opcode .*: advance Address by 0 to 0x8a3c and Line by 6 to 50
+  Special opcode .*: advance Address by 4 to 0x8a40 and Line by 1 to 51
+  Advance PC by 128 to 0x8ac0
+  Special opcode .*: advance Address by 0 to 0x8ac0 and Line by 2 to 53
+  Special opcode .*: advance Address by 4 to 0x8ac4 and Line by 1 to 54
+  Advance PC by 252 to 0x8bc0
+  Special opcode .*: advance Address by 0 to 0x8bc0 and Line by 6 to 60
+  Special opcode .*: advance Address by 4 to 0x8bc4 and Line by 1 to 61
+  Advance PC by 128 to 0x8c44
+  Special opcode .*: advance Address by 0 to 0x8c44 and Line by 2 to 63
+  Special opcode .*: advance Address by 4 to 0x8c48 and Line by 1 to 64
+  Advance PC by 124 to 0x8cc4
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-12.d b/gas/testsuite/gas/cris/rd-dw2-12.d
index c53d1d980e20..1b9dca579822 100644
--- a/gas/testsuite/gas/cris/rd-dw2-12.d
+++ b/gas/testsuite/gas/cris/rd-dw2-12.d
@@ -6,88 +6,88 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 9: advance Address by 0 to 0x0 and Line by 4 to 5
-  Special opcode 34: advance Address by 4 to 0x4 and Line by 1 to 6
-  Special opcode 34: advance Address by 4 to 0x8 and Line by 1 to 7
-  Special opcode 35: advance Address by 4 to 0xc and Line by 2 to 9
-  Special opcode 34: advance Address by 4 to 0x10 and Line by 1 to 10
-  Special opcode 34: advance Address by 4 to 0x14 and Line by 1 to 11
-  Special opcode 35: advance Address by 4 to 0x18 and Line by 2 to 13
-  Special opcode 34: advance Address by 4 to 0x1c and Line by 1 to 14
-  Special opcode 34: advance Address by 4 to 0x20 and Line by 1 to 15
-  Special opcode 35: advance Address by 4 to 0x24 and Line by 2 to 17
-  Special opcode 34: advance Address by 4 to 0x28 and Line by 1 to 18
-  Special opcode 35: advance Address by 4 to 0x2c and Line by 2 to 20
-  Special opcode 34: advance Address by 4 to 0x30 and Line by 1 to 21
-  Special opcode 34: advance Address by 4 to 0x34 and Line by 1 to 22
-  Special opcode 35: advance Address by 4 to 0x38 and Line by 2 to 24
-  Special opcode 34: advance Address by 4 to 0x3c and Line by 1 to 25
-  Special opcode 35: advance Address by 4 to 0x40 and Line by 2 to 27
-  Special opcode 34: advance Address by 4 to 0x44 and Line by 1 to 28
-  Special opcode 35: advance Address by 4 to 0x48 and Line by 2 to 30
-  Special opcode 34: advance Address by 4 to 0x4c and Line by 1 to 31
-  Special opcode 34: advance Address by 4 to 0x50 and Line by 1 to 32
-  Special opcode 35: advance Address by 4 to 0x54 and Line by 2 to 34
-  Special opcode 34: advance Address by 4 to 0x58 and Line by 1 to 35
-  Special opcode 34: advance Address by 4 to 0x5c and Line by 1 to 36
-  Special opcode 35: advance Address by 4 to 0x60 and Line by 2 to 38
-  Special opcode 34: advance Address by 4 to 0x64 and Line by 1 to 39
-  Special opcode 34: advance Address by 4 to 0x68 and Line by 1 to 40
-  Special opcode 35: advance Address by 4 to 0x6c and Line by 2 to 42
-  Special opcode 34: advance Address by 4 to 0x70 and Line by 1 to 43
-  Special opcode 34: advance Address by 4 to 0x74 and Line by 1 to 44
-  Special opcode 35: advance Address by 4 to 0x78 and Line by 2 to 46
-  Special opcode 34: advance Address by 4 to 0x7c and Line by 1 to 47
-  Special opcode 34: advance Address by 4 to 0x80 and Line by 1 to 48
-  Special opcode 35: advance Address by 4 to 0x84 and Line by 2 to 50
-  Special opcode 34: advance Address by 4 to 0x88 and Line by 1 to 51
-  Special opcode 34: advance Address by 4 to 0x8c and Line by 1 to 52
-  Special opcode 35: advance Address by 4 to 0x90 and Line by 2 to 54
-  Special opcode 34: advance Address by 4 to 0x94 and Line by 1 to 55
-  Special opcode 34: advance Address by 4 to 0x98 and Line by 1 to 56
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 4 to 5
+  Special opcode .*: advance Address by 4 to 0x4 and Line by 1 to 6
+  Special opcode .*: advance Address by 4 to 0x8 and Line by 1 to 7
+  Special opcode .*: advance Address by 4 to 0xc and Line by 2 to 9
+  Special opcode .*: advance Address by 4 to 0x10 and Line by 1 to 10
+  Special opcode .*: advance Address by 4 to 0x14 and Line by 1 to 11
+  Special opcode .*: advance Address by 4 to 0x18 and Line by 2 to 13
+  Special opcode .*: advance Address by 4 to 0x1c and Line by 1 to 14
+  Special opcode .*: advance Address by 4 to 0x20 and Line by 1 to 15
+  Special opcode .*: advance Address by 4 to 0x24 and Line by 2 to 17
+  Special opcode .*: advance Address by 4 to 0x28 and Line by 1 to 18
+  Special opcode .*: advance Address by 4 to 0x2c and Line by 2 to 20
+  Special opcode .*: advance Address by 4 to 0x30 and Line by 1 to 21
+  Special opcode .*: advance Address by 4 to 0x34 and Line by 1 to 22
+  Special opcode .*: advance Address by 4 to 0x38 and Line by 2 to 24
+  Special opcode .*: advance Address by 4 to 0x3c and Line by 1 to 25
+  Special opcode .*: advance Address by 4 to 0x40 and Line by 2 to 27
+  Special opcode .*: advance Address by 4 to 0x44 and Line by 1 to 28
+  Special opcode .*: advance Address by 4 to 0x48 and Line by 2 to 30
+  Special opcode .*: advance Address by 4 to 0x4c and Line by 1 to 31
+  Special opcode .*: advance Address by 4 to 0x50 and Line by 1 to 32
+  Special opcode .*: advance Address by 4 to 0x54 and Line by 2 to 34
+  Special opcode .*: advance Address by 4 to 0x58 and Line by 1 to 35
+  Special opcode .*: advance Address by 4 to 0x5c and Line by 1 to 36
+  Special opcode .*: advance Address by 4 to 0x60 and Line by 2 to 38
+  Special opcode .*: advance Address by 4 to 0x64 and Line by 1 to 39
+  Special opcode .*: advance Address by 4 to 0x68 and Line by 1 to 40
+  Special opcode .*: advance Address by 4 to 0x6c and Line by 2 to 42
+  Special opcode .*: advance Address by 4 to 0x70 and Line by 1 to 43
+  Special opcode .*: advance Address by 4 to 0x74 and Line by 1 to 44
+  Special opcode .*: advance Address by 4 to 0x78 and Line by 2 to 46
+  Special opcode .*: advance Address by 4 to 0x7c and Line by 1 to 47
+  Special opcode .*: advance Address by 4 to 0x80 and Line by 1 to 48
+  Special opcode .*: advance Address by 4 to 0x84 and Line by 2 to 50
+  Special opcode .*: advance Address by 4 to 0x88 and Line by 1 to 51
+  Special opcode .*: advance Address by 4 to 0x8c and Line by 1 to 52
+  Special opcode .*: advance Address by 4 to 0x90 and Line by 2 to 54
+  Special opcode .*: advance Address by 4 to 0x94 and Line by 1 to 55
+  Special opcode .*: advance Address by 4 to 0x98 and Line by 1 to 56
   Advance Line by 9 to 65
-  Special opcode 33: advance Address by 4 to 0x9c and Line by 0 to 65
-  Special opcode 34: advance Address by 4 to 0xa0 and Line by 1 to 66
-  Special opcode 34: advance Address by 4 to 0xa4 and Line by 1 to 67
-  Special opcode 35: advance Address by 4 to 0xa8 and Line by 2 to 69
-  Special opcode 34: advance Address by 4 to 0xac and Line by 1 to 70
-  Special opcode 34: advance Address by 4 to 0xb0 and Line by 1 to 71
-  Special opcode 35: advance Address by 4 to 0xb4 and Line by 2 to 73
-  Special opcode 34: advance Address by 4 to 0xb8 and Line by 1 to 74
-  Special opcode 34: advance Address by 4 to 0xbc and Line by 1 to 75
-  Special opcode 35: advance Address by 4 to 0xc0 and Line by 2 to 77
-  Special opcode 34: advance Address by 4 to 0xc4 and Line by 1 to 78
-  Special opcode 34: advance Address by 4 to 0xc8 and Line by 1 to 79
-  Special opcode 35: advance Address by 4 to 0xcc and Line by 2 to 81
-  Special opcode 34: advance Address by 4 to 0xd0 and Line by 1 to 82
-  Special opcode 34: advance Address by 4 to 0xd4 and Line by 1 to 83
-  Special opcode 35: advance Address by 4 to 0xd8 and Line by 2 to 85
-  Special opcode 34: advance Address by 4 to 0xdc and Line by 1 to 86
-  Special opcode 34: advance Address by 4 to 0xe0 and Line by 1 to 87
-  Special opcode 35: advance Address by 4 to 0xe4 and Line by 2 to 89
-  Special opcode 34: advance Address by 4 to 0xe8 and Line by 1 to 90
-  Special opcode 34: advance Address by 4 to 0xec and Line by 1 to 91
-  Special opcode 35: advance Address by 4 to 0xf0 and Line by 2 to 93
-  Special opcode 34: advance Address by 4 to 0xf4 and Line by 1 to 94
-  Special opcode 34: advance Address by 4 to 0xf8 and Line by 1 to 95
-  Special opcode 35: advance Address by 4 to 0xfc and Line by 2 to 97
-  Special opcode 34: advance Address by 4 to 0x100 and Line by 1 to 98
-  Special opcode 34: advance Address by 4 to 0x104 and Line by 1 to 99
-  Special opcode 35: advance Address by 4 to 0x108 and Line by 2 to 101
-  Special opcode 34: advance Address by 4 to 0x10c and Line by 1 to 102
-  Special opcode 34: advance Address by 4 to 0x110 and Line by 1 to 103
-  Special opcode 35: advance Address by 4 to 0x114 and Line by 2 to 105
-  Special opcode 34: advance Address by 4 to 0x118 and Line by 1 to 106
-  Special opcode 34: advance Address by 4 to 0x11c and Line by 1 to 107
-  Special opcode 35: advance Address by 4 to 0x120 and Line by 2 to 109
-  Special opcode 34: advance Address by 4 to 0x124 and Line by 1 to 110
-  Special opcode 34: advance Address by 4 to 0x128 and Line by 1 to 111
-  Special opcode 35: advance Address by 4 to 0x12c and Line by 2 to 113
-  Special opcode 34: advance Address by 4 to 0x130 and Line by 1 to 114
-  Special opcode 34: advance Address by 4 to 0x134 and Line by 1 to 115
-  Special opcode 35: advance Address by 4 to 0x138 and Line by 2 to 117
-  Special opcode 34: advance Address by 4 to 0x13c and Line by 1 to 118
-  Special opcode 20: advance Address by 2 to 0x13e and Line by 1 to 119
-  Special opcode 20: advance Address by 2 to 0x140 and Line by 1 to 120
-  Advance PC by 4 to 144
+  Special opcode .*: advance Address by 4 to 0x9c and Line by 0 to 65
+  Special opcode .*: advance Address by 4 to 0xa0 and Line by 1 to 66
+  Special opcode .*: advance Address by 4 to 0xa4 and Line by 1 to 67
+  Special opcode .*: advance Address by 4 to 0xa8 and Line by 2 to 69
+  Special opcode .*: advance Address by 4 to 0xac and Line by 1 to 70
+  Special opcode .*: advance Address by 4 to 0xb0 and Line by 1 to 71
+  Special opcode .*: advance Address by 4 to 0xb4 and Line by 2 to 73
+  Special opcode .*: advance Address by 4 to 0xb8 and Line by 1 to 74
+  Special opcode .*: advance Address by 4 to 0xbc and Line by 1 to 75
+  Special opcode .*: advance Address by 4 to 0xc0 and Line by 2 to 77
+  Special opcode .*: advance Address by 4 to 0xc4 and Line by 1 to 78
+  Special opcode .*: advance Address by 4 to 0xc8 and Line by 1 to 79
+  Special opcode .*: advance Address by 4 to 0xcc and Line by 2 to 81
+  Special opcode .*: advance Address by 4 to 0xd0 and Line by 1 to 82
+  Special opcode .*: advance Address by 4 to 0xd4 and Line by 1 to 83
+  Special opcode .*: advance Address by 4 to 0xd8 and Line by 2 to 85
+  Special opcode .*: advance Address by 4 to 0xdc and Line by 1 to 86
+  Special opcode .*: advance Address by 4 to 0xe0 and Line by 1 to 87
+  Special opcode .*: advance Address by 4 to 0xe4 and Line by 2 to 89
+  Special opcode .*: advance Address by 4 to 0xe8 and Line by 1 to 90
+  Special opcode .*: advance Address by 4 to 0xec and Line by 1 to 91
+  Special opcode .*: advance Address by 4 to 0xf0 and Line by 2 to 93
+  Special opcode .*: advance Address by 4 to 0xf4 and Line by 1 to 94
+  Special opcode .*: advance Address by 4 to 0xf8 and Line by 1 to 95
+  Special opcode .*: advance Address by 4 to 0xfc and Line by 2 to 97
+  Special opcode .*: advance Address by 4 to 0x100 and Line by 1 to 98
+  Special opcode .*: advance Address by 4 to 0x104 and Line by 1 to 99
+  Special opcode .*: advance Address by 4 to 0x108 and Line by 2 to 101
+  Special opcode .*: advance Address by 4 to 0x10c and Line by 1 to 102
+  Special opcode .*: advance Address by 4 to 0x110 and Line by 1 to 103
+  Special opcode .*: advance Address by 4 to 0x114 and Line by 2 to 105
+  Special opcode .*: advance Address by 4 to 0x118 and Line by 1 to 106
+  Special opcode .*: advance Address by 4 to 0x11c and Line by 1 to 107
+  Special opcode .*: advance Address by 4 to 0x120 and Line by 2 to 109
+  Special opcode .*: advance Address by 4 to 0x124 and Line by 1 to 110
+  Special opcode .*: advance Address by 4 to 0x128 and Line by 1 to 111
+  Special opcode .*: advance Address by 4 to 0x12c and Line by 2 to 113
+  Special opcode .*: advance Address by 4 to 0x130 and Line by 1 to 114
+  Special opcode .*: advance Address by 4 to 0x134 and Line by 1 to 115
+  Special opcode .*: advance Address by 4 to 0x138 and Line by 2 to 117
+  Special opcode .*: advance Address by 4 to 0x13c and Line by 1 to 118
+  Special opcode .*: advance Address by 2 to 0x13e and Line by 1 to 119
+  Special opcode .*: advance Address by 2 to 0x140 and Line by 1 to 120
+  Advance PC by 4 to 0x144
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-13.d b/gas/testsuite/gas/cris/rd-dw2-13.d
index fa20f1fd57eb..7c985e438986 100644
--- a/gas/testsuite/gas/cris/rd-dw2-13.d
+++ b/gas/testsuite/gas/cris/rd-dw2-13.d
@@ -6,29 +6,29 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 10: advance Address by 0 to 0x0 and Line by 5 to 6
-  Special opcode 48: advance Address by 6 to 0x6 and Line by 1 to 7
-  Special opcode 62: advance Address by 8 to 0xe and Line by 1 to 8
-  Special opcode 48: advance Address by 6 to 0x14 and Line by 1 to 9
-  Special opcode 48: advance Address by 6 to 0x1a and Line by 1 to 10
-  Special opcode 48: advance Address by 6 to 0x20 and Line by 1 to 11
-  Special opcode 62: advance Address by 8 to 0x28 and Line by 1 to 12
-  Special opcode 48: advance Address by 6 to 0x2e and Line by 1 to 13
-  Special opcode 36: advance Address by 4 to 0x32 and Line by 3 to 16
-  Special opcode 62: advance Address by 8 to 0x3a and Line by 1 to 17
-  Special opcode 48: advance Address by 6 to 0x40 and Line by 1 to 18
-  Special opcode 48: advance Address by 6 to 0x46 and Line by 1 to 19
-  Special opcode 62: advance Address by 8 to 0x4e and Line by 1 to 20
-  Special opcode 62: advance Address by 8 to 0x56 and Line by 1 to 21
-  Special opcode 62: advance Address by 8 to 0x5e and Line by 1 to 22
-  Special opcode 62: advance Address by 8 to 0x66 and Line by 1 to 23
-  Special opcode 62: advance Address by 8 to 0x6e and Line by 1 to 24
-  Special opcode 62: advance Address by 8 to 0x76 and Line by 1 to 25
-  Special opcode 48: advance Address by 6 to 0x7c and Line by 1 to 26
-  Special opcode 48: advance Address by 6 to 0x82 and Line by 1 to 27
-  Special opcode 48: advance Address by 6 to 0x88 and Line by 1 to 28
-  Special opcode 48: advance Address by 6 to 0x8e and Line by 1 to 29
-  Special opcode 48: advance Address by 6 to 0x94 and Line by 1 to 30
-  Special opcode 48: advance Address by 6 to 0x9a and Line by 1 to 31
-  Advance PC by 8 to a2
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 5 to 6
+  Special opcode .*: advance Address by 6 to 0x6 and Line by 1 to 7
+  Special opcode .*: advance Address by 8 to 0xe and Line by 1 to 8
+  Special opcode .*: advance Address by 6 to 0x14 and Line by 1 to 9
+  Special opcode .*: advance Address by 6 to 0x1a and Line by 1 to 10
+  Special opcode .*: advance Address by 6 to 0x20 and Line by 1 to 11
+  Special opcode .*: advance Address by 8 to 0x28 and Line by 1 to 12
+  Special opcode .*: advance Address by 6 to 0x2e and Line by 1 to 13
+  Special opcode .*: advance Address by 4 to 0x32 and Line by 3 to 16
+  Special opcode .*: advance Address by 8 to 0x3a and Line by 1 to 17
+  Special opcode .*: advance Address by 6 to 0x40 and Line by 1 to 18
+  Special opcode .*: advance Address by 6 to 0x46 and Line by 1 to 19
+  Special opcode .*: advance Address by 8 to 0x4e and Line by 1 to 20
+  Special opcode .*: advance Address by 8 to 0x56 and Line by 1 to 21
+  Special opcode .*: advance Address by 8 to 0x5e and Line by 1 to 22
+  Special opcode .*: advance Address by 8 to 0x66 and Line by 1 to 23
+  Special opcode .*: advance Address by 8 to 0x6e and Line by 1 to 24
+  Special opcode .*: advance Address by 8 to 0x76 and Line by 1 to 25
+  Special opcode .*: advance Address by 6 to 0x7c and Line by 1 to 26
+  Special opcode .*: advance Address by 6 to 0x82 and Line by 1 to 27
+  Special opcode .*: advance Address by 6 to 0x88 and Line by 1 to 28
+  Special opcode .*: advance Address by 6 to 0x8e and Line by 1 to 29
+  Special opcode .*: advance Address by 6 to 0x94 and Line by 1 to 30
+  Special opcode .*: advance Address by 6 to 0x9a and Line by 1 to 31
+  Advance PC by 8 to 0xa2
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-14.d b/gas/testsuite/gas/cris/rd-dw2-14.d
index fd76906e7ccc..297d83cefcbd 100644
--- a/gas/testsuite/gas/cris/rd-dw2-14.d
+++ b/gas/testsuite/gas/cris/rd-dw2-14.d
@@ -6,25 +6,25 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 13: advance Address by 0 to 0x0 and Line by 8 to 9
-  Special opcode 20: advance Address by 2 to 0x2 and Line by 1 to 10
-  Special opcode 34: advance Address by 4 to 0x6 and Line by 1 to 11
-  Special opcode 34: advance Address by 4 to 0xa and Line by 1 to 12
-  Special opcode 62: advance Address by 8 to 0x12 and Line by 1 to 13
-  Special opcode 62: advance Address by 8 to 0x1a and Line by 1 to 14
-  Special opcode 20: advance Address by 2 to 0x1c and Line by 1 to 15
-  Special opcode 34: advance Address by 4 to 0x20 and Line by 1 to 16
-  Special opcode 34: advance Address by 4 to 0x24 and Line by 1 to 17
-  Special opcode 62: advance Address by 8 to 0x2c and Line by 1 to 18
-  Special opcode 62: advance Address by 8 to 0x34 and Line by 1 to 19
-  Special opcode 20: advance Address by 2 to 0x36 and Line by 1 to 20
-  Special opcode 20: advance Address by 2 to 0x38 and Line by 1 to 21
-  Special opcode 20: advance Address by 2 to 0x3a and Line by 1 to 22
-  Special opcode 20: advance Address by 2 to 0x3c and Line by 1 to 23
-  Special opcode 20: advance Address by 2 to 0x3e and Line by 1 to 24
-  Special opcode 20: advance Address by 2 to 0x40 and Line by 1 to 25
-  Special opcode 20: advance Address by 2 to 0x42 and Line by 1 to 26
-  Special opcode 20: advance Address by 2 to 0x44 and Line by 1 to 27
-  Special opcode 20: advance Address by 2 to 0x46 and Line by 1 to 28
-  Advance PC by 2 to 48
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 8 to 9
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 10
+  Special opcode .*: advance Address by 4 to 0x6 and Line by 1 to 11
+  Special opcode .*: advance Address by 4 to 0xa and Line by 1 to 12
+  Special opcode .*: advance Address by 8 to 0x12 and Line by 1 to 13
+  Special opcode .*: advance Address by 8 to 0x1a and Line by 1 to 14
+  Special opcode .*: advance Address by 2 to 0x1c and Line by 1 to 15
+  Special opcode .*: advance Address by 4 to 0x20 and Line by 1 to 16
+  Special opcode .*: advance Address by 4 to 0x24 and Line by 1 to 17
+  Special opcode .*: advance Address by 8 to 0x2c and Line by 1 to 18
+  Special opcode .*: advance Address by 8 to 0x34 and Line by 1 to 19
+  Special opcode .*: advance Address by 2 to 0x36 and Line by 1 to 20
+  Special opcode .*: advance Address by 2 to 0x38 and Line by 1 to 21
+  Special opcode .*: advance Address by 2 to 0x3a and Line by 1 to 22
+  Special opcode .*: advance Address by 2 to 0x3c and Line by 1 to 23
+  Special opcode .*: advance Address by 2 to 0x3e and Line by 1 to 24
+  Special opcode .*: advance Address by 2 to 0x40 and Line by 1 to 25
+  Special opcode .*: advance Address by 2 to 0x42 and Line by 1 to 26
+  Special opcode .*: advance Address by 2 to 0x44 and Line by 1 to 27
+  Special opcode .*: advance Address by 2 to 0x46 and Line by 1 to 28
+  Advance PC by 2 to 0x48
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-15.d b/gas/testsuite/gas/cris/rd-dw2-15.d
index 589fdf679819..bbb828949e0c 100644
--- a/gas/testsuite/gas/cris/rd-dw2-15.d
+++ b/gas/testsuite/gas/cris/rd-dw2-15.d
@@ -6,157 +6,157 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 13: advance Address by 0 to 0x0 and Line by 8 to 9
-  Special opcode 20: advance Address by 2 to 0x2 and Line by 1 to 10
-  Special opcode 21: advance Address by 2 to 0x4 and Line by 2 to 12
-  Special opcode 20: advance Address by 2 to 0x6 and Line by 1 to 13
-  Special opcode 21: advance Address by 2 to 0x8 and Line by 2 to 15
-  Special opcode 20: advance Address by 2 to 0xa and Line by 1 to 16
-  Special opcode 21: advance Address by 2 to 0xc and Line by 2 to 18
-  Special opcode 20: advance Address by 2 to 0xe and Line by 1 to 19
-  Special opcode 21: advance Address by 2 to 0x10 and Line by 2 to 21
-  Special opcode 20: advance Address by 2 to 0x12 and Line by 1 to 22
-  Special opcode 21: advance Address by 2 to 0x14 and Line by 2 to 24
-  Special opcode 20: advance Address by 2 to 0x16 and Line by 1 to 25
-  Special opcode 21: advance Address by 2 to 0x18 and Line by 2 to 27
-  Special opcode 20: advance Address by 2 to 0x1a and Line by 1 to 28
-  Special opcode 21: advance Address by 2 to 0x1c and Line by 2 to 30
-  Special opcode 20: advance Address by 2 to 0x1e and Line by 1 to 31
-  Special opcode 25: advance Address by 2 to 0x20 and Line by 6 to 37
-  Special opcode 34: advance Address by 4 to 0x24 and Line by 1 to 38
-  Special opcode 21: advance Address by 2 to 0x26 and Line by 2 to 40
-  Special opcode 34: advance Address by 4 to 0x2a and Line by 1 to 41
-  Special opcode 21: advance Address by 2 to 0x2c and Line by 2 to 43
-  Special opcode 34: advance Address by 4 to 0x30 and Line by 1 to 44
-  Special opcode 21: advance Address by 2 to 0x32 and Line by 2 to 46
-  Special opcode 34: advance Address by 4 to 0x36 and Line by 1 to 47
-  Special opcode 21: advance Address by 2 to 0x38 and Line by 2 to 49
-  Special opcode 34: advance Address by 4 to 0x3c and Line by 1 to 50
-  Special opcode 21: advance Address by 2 to 0x3e and Line by 2 to 52
-  Special opcode 34: advance Address by 4 to 0x42 and Line by 1 to 53
-  Special opcode 21: advance Address by 2 to 0x44 and Line by 2 to 55
-  Special opcode 34: advance Address by 4 to 0x48 and Line by 1 to 56
-  Special opcode 21: advance Address by 2 to 0x4a and Line by 2 to 58
-  Special opcode 34: advance Address by 4 to 0x4e and Line by 1 to 59
-  Special opcode 21: advance Address by 2 to 0x50 and Line by 2 to 61
-  Special opcode 34: advance Address by 4 to 0x54 and Line by 1 to 62
-  Special opcode 21: advance Address by 2 to 0x56 and Line by 2 to 64
-  Special opcode 34: advance Address by 4 to 0x5a and Line by 1 to 65
-  Special opcode 21: advance Address by 2 to 0x5c and Line by 2 to 67
-  Special opcode 34: advance Address by 4 to 0x60 and Line by 1 to 68
-  Special opcode 21: advance Address by 2 to 0x62 and Line by 2 to 70
-  Special opcode 34: advance Address by 4 to 0x66 and Line by 1 to 71
-  Special opcode 21: advance Address by 2 to 0x68 and Line by 2 to 73
-  Special opcode 34: advance Address by 4 to 0x6c and Line by 1 to 74
-  Special opcode 21: advance Address by 2 to 0x6e and Line by 2 to 76
-  Special opcode 34: advance Address by 4 to 0x72 and Line by 1 to 77
-  Special opcode 21: advance Address by 2 to 0x74 and Line by 2 to 79
-  Special opcode 48: advance Address by 6 to 0x7a and Line by 1 to 80
-  Special opcode 21: advance Address by 2 to 0x7c and Line by 2 to 82
-  Special opcode 48: advance Address by 6 to 0x82 and Line by 1 to 83
-  Special opcode 21: advance Address by 2 to 0x84 and Line by 2 to 85
-  Special opcode 48: advance Address by 6 to 0x8a and Line by 1 to 86
-  Special opcode 21: advance Address by 2 to 0x8c and Line by 2 to 88
-  Special opcode 48: advance Address by 6 to 0x92 and Line by 1 to 89
-  Special opcode 21: advance Address by 2 to 0x94 and Line by 2 to 91
-  Special opcode 48: advance Address by 6 to 0x9a and Line by 1 to 92
-  Special opcode 21: advance Address by 2 to 0x9c and Line by 2 to 94
-  Special opcode 48: advance Address by 6 to 0xa2 and Line by 1 to 95
-  Special opcode 21: advance Address by 2 to 0xa4 and Line by 2 to 97
-  Special opcode 48: advance Address by 6 to 0xaa and Line by 1 to 98
-  Special opcode 21: advance Address by 2 to 0xac and Line by 2 to 100
-  Special opcode 48: advance Address by 6 to 0xb2 and Line by 1 to 101
-  Special opcode 21: advance Address by 2 to 0xb4 and Line by 2 to 103
-  Special opcode 48: advance Address by 6 to 0xba and Line by 1 to 104
-  Special opcode 21: advance Address by 2 to 0xbc and Line by 2 to 106
-  Special opcode 48: advance Address by 6 to 0xc2 and Line by 1 to 107
-  Special opcode 21: advance Address by 2 to 0xc4 and Line by 2 to 109
-  Special opcode 48: advance Address by 6 to 0xca and Line by 1 to 110
-  Special opcode 21: advance Address by 2 to 0xcc and Line by 2 to 112
-  Special opcode 48: advance Address by 6 to 0xd2 and Line by 1 to 113
-  Special opcode 21: advance Address by 2 to 0xd4 and Line by 2 to 115
-  Special opcode 48: advance Address by 6 to 0xda and Line by 1 to 116
-  Special opcode 21: advance Address by 2 to 0xdc and Line by 2 to 118
-  Special opcode 48: advance Address by 6 to 0xe2 and Line by 1 to 119
-  Special opcode 21: advance Address by 2 to 0xe4 and Line by 2 to 121
-  Special opcode 48: advance Address by 6 to 0xea and Line by 1 to 122
-  Special opcode 21: advance Address by 2 to 0xec and Line by 2 to 124
-  Special opcode 48: advance Address by 6 to 0xf2 and Line by 1 to 125
-  Special opcode 21: advance Address by 2 to 0xf4 and Line by 2 to 127
-  Special opcode 20: advance Address by 2 to 0xf6 and Line by 1 to 128
-  Special opcode 21: advance Address by 2 to 0xf8 and Line by 2 to 130
-  Special opcode 20: advance Address by 2 to 0xfa and Line by 1 to 131
-  Special opcode 21: advance Address by 2 to 0xfc and Line by 2 to 133
-  Special opcode 20: advance Address by 2 to 0xfe and Line by 1 to 134
-  Special opcode 21: advance Address by 2 to 0x100 and Line by 2 to 136
-  Special opcode 20: advance Address by 2 to 0x102 and Line by 1 to 137
-  Special opcode 21: advance Address by 2 to 0x104 and Line by 2 to 139
-  Special opcode 20: advance Address by 2 to 0x106 and Line by 1 to 140
-  Special opcode 21: advance Address by 2 to 0x108 and Line by 2 to 142
-  Special opcode 20: advance Address by 2 to 0x10a and Line by 1 to 143
-  Special opcode 21: advance Address by 2 to 0x10c and Line by 2 to 145
-  Special opcode 20: advance Address by 2 to 0x10e and Line by 1 to 146
-  Special opcode 21: advance Address by 2 to 0x110 and Line by 2 to 148
-  Special opcode 20: advance Address by 2 to 0x112 and Line by 1 to 149
-  Special opcode 21: advance Address by 2 to 0x114 and Line by 2 to 151
-  Special opcode 20: advance Address by 2 to 0x116 and Line by 1 to 152
-  Special opcode 25: advance Address by 2 to 0x118 and Line by 6 to 158
-  Special opcode 20: advance Address by 2 to 0x11a and Line by 1 to 159
-  Special opcode 21: advance Address by 2 to 0x11c and Line by 2 to 161
-  Special opcode 20: advance Address by 2 to 0x11e and Line by 1 to 162
-  Special opcode 21: advance Address by 2 to 0x120 and Line by 2 to 164
-  Special opcode 20: advance Address by 2 to 0x122 and Line by 1 to 165
-  Special opcode 21: advance Address by 2 to 0x124 and Line by 2 to 167
-  Special opcode 20: advance Address by 2 to 0x126 and Line by 1 to 168
-  Special opcode 21: advance Address by 2 to 0x128 and Line by 2 to 170
-  Special opcode 20: advance Address by 2 to 0x12a and Line by 1 to 171
-  Special opcode 21: advance Address by 2 to 0x12c and Line by 2 to 173
-  Special opcode 20: advance Address by 2 to 0x12e and Line by 1 to 174
-  Special opcode 21: advance Address by 2 to 0x130 and Line by 2 to 176
-  Special opcode 20: advance Address by 2 to 0x132 and Line by 1 to 177
-  Special opcode 21: advance Address by 2 to 0x134 and Line by 2 to 179
-  Special opcode 20: advance Address by 2 to 0x136 and Line by 1 to 180
-  Special opcode 21: advance Address by 2 to 0x138 and Line by 2 to 182
-  Special opcode 20: advance Address by 2 to 0x13a and Line by 1 to 183
-  Special opcode 24: advance Address by 2 to 0x13c and Line by 5 to 188
-  Special opcode 48: advance Address by 6 to 0x142 and Line by 1 to 189
-  Special opcode 21: advance Address by 2 to 0x144 and Line by 2 to 191
-  Special opcode 48: advance Address by 6 to 0x14a and Line by 1 to 192
-  Special opcode 21: advance Address by 2 to 0x14c and Line by 2 to 194
-  Special opcode 48: advance Address by 6 to 0x152 and Line by 1 to 195
-  Special opcode 21: advance Address by 2 to 0x154 and Line by 2 to 197
-  Special opcode 48: advance Address by 6 to 0x15a and Line by 1 to 198
-  Special opcode 21: advance Address by 2 to 0x15c and Line by 2 to 200
-  Special opcode 48: advance Address by 6 to 0x162 and Line by 1 to 201
-  Special opcode 21: advance Address by 2 to 0x164 and Line by 2 to 203
-  Special opcode 48: advance Address by 6 to 0x16a and Line by 1 to 204
-  Special opcode 21: advance Address by 2 to 0x16c and Line by 2 to 206
-  Special opcode 48: advance Address by 6 to 0x172 and Line by 1 to 207
-  Special opcode 21: advance Address by 2 to 0x174 and Line by 2 to 209
-  Special opcode 48: advance Address by 6 to 0x17a and Line by 1 to 210
-  Special opcode 21: advance Address by 2 to 0x17c and Line by 2 to 212
-  Special opcode 48: advance Address by 6 to 0x182 and Line by 1 to 213
-  Special opcode 21: advance Address by 2 to 0x184 and Line by 2 to 215
-  Special opcode 48: advance Address by 6 to 0x18a and Line by 1 to 216
-  Special opcode 21: advance Address by 2 to 0x18c and Line by 2 to 218
-  Special opcode 48: advance Address by 6 to 0x192 and Line by 1 to 219
-  Special opcode 21: advance Address by 2 to 0x194 and Line by 2 to 221
-  Special opcode 48: advance Address by 6 to 0x19a and Line by 1 to 222
-  Special opcode 21: advance Address by 2 to 0x19c and Line by 2 to 224
-  Special opcode 48: advance Address by 6 to 0x1a2 and Line by 1 to 225
-  Special opcode 21: advance Address by 2 to 0x1a4 and Line by 2 to 227
-  Special opcode 48: advance Address by 6 to 0x1aa and Line by 1 to 228
-  Special opcode 21: advance Address by 2 to 0x1ac and Line by 2 to 230
-  Special opcode 48: advance Address by 6 to 0x1b2 and Line by 1 to 231
-  Special opcode 21: advance Address by 2 to 0x1b4 and Line by 2 to 233
-  Special opcode 48: advance Address by 6 to 0x1ba and Line by 1 to 234
-  Special opcode 21: advance Address by 2 to 0x1bc and Line by 2 to 236
-  Special opcode 20: advance Address by 2 to 0x1be and Line by 1 to 237
-  Special opcode 21: advance Address by 2 to 0x1c0 and Line by 2 to 239
-  Special opcode 20: advance Address by 2 to 0x1c2 and Line by 1 to 240
-  Special opcode 21: advance Address by 2 to 0x1c4 and Line by 2 to 242
-  Special opcode 20: advance Address by 2 to 0x1c6 and Line by 1 to 243
-  Special opcode 21: advance Address by 2 to 0x1c8 and Line by 2 to 245
-  Special opcode 20: advance Address by 2 to 0x1ca and Line by 1 to 246
-  Advance PC by 2 to 1cc
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 8 to 9
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 10
+  Special opcode .*: advance Address by 2 to 0x4 and Line by 2 to 12
+  Special opcode .*: advance Address by 2 to 0x6 and Line by 1 to 13
+  Special opcode .*: advance Address by 2 to 0x8 and Line by 2 to 15
+  Special opcode .*: advance Address by 2 to 0xa and Line by 1 to 16
+  Special opcode .*: advance Address by 2 to 0xc and Line by 2 to 18
+  Special opcode .*: advance Address by 2 to 0xe and Line by 1 to 19
+  Special opcode .*: advance Address by 2 to 0x10 and Line by 2 to 21
+  Special opcode .*: advance Address by 2 to 0x12 and Line by 1 to 22
+  Special opcode .*: advance Address by 2 to 0x14 and Line by 2 to 24
+  Special opcode .*: advance Address by 2 to 0x16 and Line by 1 to 25
+  Special opcode .*: advance Address by 2 to 0x18 and Line by 2 to 27
+  Special opcode .*: advance Address by 2 to 0x1a and Line by 1 to 28
+  Special opcode .*: advance Address by 2 to 0x1c and Line by 2 to 30
+  Special opcode .*: advance Address by 2 to 0x1e and Line by 1 to 31
+  Special opcode .*: advance Address by 2 to 0x20 and Line by 6 to 37
+  Special opcode .*: advance Address by 4 to 0x24 and Line by 1 to 38
+  Special opcode .*: advance Address by 2 to 0x26 and Line by 2 to 40
+  Special opcode .*: advance Address by 4 to 0x2a and Line by 1 to 41
+  Special opcode .*: advance Address by 2 to 0x2c and Line by 2 to 43
+  Special opcode .*: advance Address by 4 to 0x30 and Line by 1 to 44
+  Special opcode .*: advance Address by 2 to 0x32 and Line by 2 to 46
+  Special opcode .*: advance Address by 4 to 0x36 and Line by 1 to 47
+  Special opcode .*: advance Address by 2 to 0x38 and Line by 2 to 49
+  Special opcode .*: advance Address by 4 to 0x3c and Line by 1 to 50
+  Special opcode .*: advance Address by 2 to 0x3e and Line by 2 to 52
+  Special opcode .*: advance Address by 4 to 0x42 and Line by 1 to 53
+  Special opcode .*: advance Address by 2 to 0x44 and Line by 2 to 55
+  Special opcode .*: advance Address by 4 to 0x48 and Line by 1 to 56
+  Special opcode .*: advance Address by 2 to 0x4a and Line by 2 to 58
+  Special opcode .*: advance Address by 4 to 0x4e and Line by 1 to 59
+  Special opcode .*: advance Address by 2 to 0x50 and Line by 2 to 61
+  Special opcode .*: advance Address by 4 to 0x54 and Line by 1 to 62
+  Special opcode .*: advance Address by 2 to 0x56 and Line by 2 to 64
+  Special opcode .*: advance Address by 4 to 0x5a and Line by 1 to 65
+  Special opcode .*: advance Address by 2 to 0x5c and Line by 2 to 67
+  Special opcode .*: advance Address by 4 to 0x60 and Line by 1 to 68
+  Special opcode .*: advance Address by 2 to 0x62 and Line by 2 to 70
+  Special opcode .*: advance Address by 4 to 0x66 and Line by 1 to 71
+  Special opcode .*: advance Address by 2 to 0x68 and Line by 2 to 73
+  Special opcode .*: advance Address by 4 to 0x6c and Line by 1 to 74
+  Special opcode .*: advance Address by 2 to 0x6e and Line by 2 to 76
+  Special opcode .*: advance Address by 4 to 0x72 and Line by 1 to 77
+  Special opcode .*: advance Address by 2 to 0x74 and Line by 2 to 79
+  Special opcode .*: advance Address by 6 to 0x7a and Line by 1 to 80
+  Special opcode .*: advance Address by 2 to 0x7c and Line by 2 to 82
+  Special opcode .*: advance Address by 6 to 0x82 and Line by 1 to 83
+  Special opcode .*: advance Address by 2 to 0x84 and Line by 2 to 85
+  Special opcode .*: advance Address by 6 to 0x8a and Line by 1 to 86
+  Special opcode .*: advance Address by 2 to 0x8c and Line by 2 to 88
+  Special opcode .*: advance Address by 6 to 0x92 and Line by 1 to 89
+  Special opcode .*: advance Address by 2 to 0x94 and Line by 2 to 91
+  Special opcode .*: advance Address by 6 to 0x9a and Line by 1 to 92
+  Special opcode .*: advance Address by 2 to 0x9c and Line by 2 to 94
+  Special opcode .*: advance Address by 6 to 0xa2 and Line by 1 to 95
+  Special opcode .*: advance Address by 2 to 0xa4 and Line by 2 to 97
+  Special opcode .*: advance Address by 6 to 0xaa and Line by 1 to 98
+  Special opcode .*: advance Address by 2 to 0xac and Line by 2 to 100
+  Special opcode .*: advance Address by 6 to 0xb2 and Line by 1 to 101
+  Special opcode .*: advance Address by 2 to 0xb4 and Line by 2 to 103
+  Special opcode .*: advance Address by 6 to 0xba and Line by 1 to 104
+  Special opcode .*: advance Address by 2 to 0xbc and Line by 2 to 106
+  Special opcode .*: advance Address by 6 to 0xc2 and Line by 1 to 107
+  Special opcode .*: advance Address by 2 to 0xc4 and Line by 2 to 109
+  Special opcode .*: advance Address by 6 to 0xca and Line by 1 to 110
+  Special opcode .*: advance Address by 2 to 0xcc and Line by 2 to 112
+  Special opcode .*: advance Address by 6 to 0xd2 and Line by 1 to 113
+  Special opcode .*: advance Address by 2 to 0xd4 and Line by 2 to 115
+  Special opcode .*: advance Address by 6 to 0xda and Line by 1 to 116
+  Special opcode .*: advance Address by 2 to 0xdc and Line by 2 to 118
+  Special opcode .*: advance Address by 6 to 0xe2 and Line by 1 to 119
+  Special opcode .*: advance Address by 2 to 0xe4 and Line by 2 to 121
+  Special opcode .*: advance Address by 6 to 0xea and Line by 1 to 122
+  Special opcode .*: advance Address by 2 to 0xec and Line by 2 to 124
+  Special opcode .*: advance Address by 6 to 0xf2 and Line by 1 to 125
+  Special opcode .*: advance Address by 2 to 0xf4 and Line by 2 to 127
+  Special opcode .*: advance Address by 2 to 0xf6 and Line by 1 to 128
+  Special opcode .*: advance Address by 2 to 0xf8 and Line by 2 to 130
+  Special opcode .*: advance Address by 2 to 0xfa and Line by 1 to 131
+  Special opcode .*: advance Address by 2 to 0xfc and Line by 2 to 133
+  Special opcode .*: advance Address by 2 to 0xfe and Line by 1 to 134
+  Special opcode .*: advance Address by 2 to 0x100 and Line by 2 to 136
+  Special opcode .*: advance Address by 2 to 0x102 and Line by 1 to 137
+  Special opcode .*: advance Address by 2 to 0x104 and Line by 2 to 139
+  Special opcode .*: advance Address by 2 to 0x106 and Line by 1 to 140
+  Special opcode .*: advance Address by 2 to 0x108 and Line by 2 to 142
+  Special opcode .*: advance Address by 2 to 0x10a and Line by 1 to 143
+  Special opcode .*: advance Address by 2 to 0x10c and Line by 2 to 145
+  Special opcode .*: advance Address by 2 to 0x10e and Line by 1 to 146
+  Special opcode .*: advance Address by 2 to 0x110 and Line by 2 to 148
+  Special opcode .*: advance Address by 2 to 0x112 and Line by 1 to 149
+  Special opcode .*: advance Address by 2 to 0x114 and Line by 2 to 151
+  Special opcode .*: advance Address by 2 to 0x116 and Line by 1 to 152
+  Special opcode .*: advance Address by 2 to 0x118 and Line by 6 to 158
+  Special opcode .*: advance Address by 2 to 0x11a and Line by 1 to 159
+  Special opcode .*: advance Address by 2 to 0x11c and Line by 2 to 161
+  Special opcode .*: advance Address by 2 to 0x11e and Line by 1 to 162
+  Special opcode .*: advance Address by 2 to 0x120 and Line by 2 to 164
+  Special opcode .*: advance Address by 2 to 0x122 and Line by 1 to 165
+  Special opcode .*: advance Address by 2 to 0x124 and Line by 2 to 167
+  Special opcode .*: advance Address by 2 to 0x126 and Line by 1 to 168
+  Special opcode .*: advance Address by 2 to 0x128 and Line by 2 to 170
+  Special opcode .*: advance Address by 2 to 0x12a and Line by 1 to 171
+  Special opcode .*: advance Address by 2 to 0x12c and Line by 2 to 173
+  Special opcode .*: advance Address by 2 to 0x12e and Line by 1 to 174
+  Special opcode .*: advance Address by 2 to 0x130 and Line by 2 to 176
+  Special opcode .*: advance Address by 2 to 0x132 and Line by 1 to 177
+  Special opcode .*: advance Address by 2 to 0x134 and Line by 2 to 179
+  Special opcode .*: advance Address by 2 to 0x136 and Line by 1 to 180
+  Special opcode .*: advance Address by 2 to 0x138 and Line by 2 to 182
+  Special opcode .*: advance Address by 2 to 0x13a and Line by 1 to 183
+  Special opcode .*: advance Address by 2 to 0x13c and Line by 5 to 188
+  Special opcode .*: advance Address by 6 to 0x142 and Line by 1 to 189
+  Special opcode .*: advance Address by 2 to 0x144 and Line by 2 to 191
+  Special opcode .*: advance Address by 6 to 0x14a and Line by 1 to 192
+  Special opcode .*: advance Address by 2 to 0x14c and Line by 2 to 194
+  Special opcode .*: advance Address by 6 to 0x152 and Line by 1 to 195
+  Special opcode .*: advance Address by 2 to 0x154 and Line by 2 to 197
+  Special opcode .*: advance Address by 6 to 0x15a and Line by 1 to 198
+  Special opcode .*: advance Address by 2 to 0x15c and Line by 2 to 200
+  Special opcode .*: advance Address by 6 to 0x162 and Line by 1 to 201
+  Special opcode .*: advance Address by 2 to 0x164 and Line by 2 to 203
+  Special opcode .*: advance Address by 6 to 0x16a and Line by 1 to 204
+  Special opcode .*: advance Address by 2 to 0x16c and Line by 2 to 206
+  Special opcode .*: advance Address by 6 to 0x172 and Line by 1 to 207
+  Special opcode .*: advance Address by 2 to 0x174 and Line by 2 to 209
+  Special opcode .*: advance Address by 6 to 0x17a and Line by 1 to 210
+  Special opcode .*: advance Address by 2 to 0x17c and Line by 2 to 212
+  Special opcode .*: advance Address by 6 to 0x182 and Line by 1 to 213
+  Special opcode .*: advance Address by 2 to 0x184 and Line by 2 to 215
+  Special opcode .*: advance Address by 6 to 0x18a and Line by 1 to 216
+  Special opcode .*: advance Address by 2 to 0x18c and Line by 2 to 218
+  Special opcode .*: advance Address by 6 to 0x192 and Line by 1 to 219
+  Special opcode .*: advance Address by 2 to 0x194 and Line by 2 to 221
+  Special opcode .*: advance Address by 6 to 0x19a and Line by 1 to 222
+  Special opcode .*: advance Address by 2 to 0x19c and Line by 2 to 224
+  Special opcode .*: advance Address by 6 to 0x1a2 and Line by 1 to 225
+  Special opcode .*: advance Address by 2 to 0x1a4 and Line by 2 to 227
+  Special opcode .*: advance Address by 6 to 0x1aa and Line by 1 to 228
+  Special opcode .*: advance Address by 2 to 0x1ac and Line by 2 to 230
+  Special opcode .*: advance Address by 6 to 0x1b2 and Line by 1 to 231
+  Special opcode .*: advance Address by 2 to 0x1b4 and Line by 2 to 233
+  Special opcode .*: advance Address by 6 to 0x1ba and Line by 1 to 234
+  Special opcode .*: advance Address by 2 to 0x1bc and Line by 2 to 236
+  Special opcode .*: advance Address by 2 to 0x1be and Line by 1 to 237
+  Special opcode .*: advance Address by 2 to 0x1c0 and Line by 2 to 239
+  Special opcode .*: advance Address by 2 to 0x1c2 and Line by 1 to 240
+  Special opcode .*: advance Address by 2 to 0x1c4 and Line by 2 to 242
+  Special opcode .*: advance Address by 2 to 0x1c6 and Line by 1 to 243
+  Special opcode .*: advance Address by 2 to 0x1c8 and Line by 2 to 245
+  Special opcode .*: advance Address by 2 to 0x1ca and Line by 1 to 246
+  Advance PC by 2 to 0x1cc
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-2.d b/gas/testsuite/gas/cris/rd-dw2-2.d
index 66a75beb342f..7d58ab561337 100644
--- a/gas/testsuite/gas/cris/rd-dw2-2.d
+++ b/gas/testsuite/gas/cris/rd-dw2-2.d
@@ -8,28 +8,28 @@
   Extended opcode 2: set Address to 0x5005a
   Advance Line by 36 to 37
   Copy
-  Special opcode 34: advance Address by 4 to 0x5005e and Line by 1 to 38
-  Special opcode 34: advance Address by 4 to 0x50062 and Line by 1 to 39
-  Special opcode 34: advance Address by 4 to 0x50066 and Line by 1 to 40
-  Special opcode 35: advance Address by 4 to 0x5006a and Line by 2 to 42
-  Special opcode 34: advance Address by 4 to 0x5006e and Line by 1 to 43
-  Special opcode 34: advance Address by 4 to 0x50072 and Line by 1 to 44
-  Special opcode 34: advance Address by 4 to 0x50076 and Line by 1 to 45
-  Special opcode 35: advance Address by 4 to 0x5007a and Line by 2 to 47
-  Special opcode 34: advance Address by 4 to 0x5007e and Line by 1 to 48
-  Special opcode 34: advance Address by 4 to 0x50082 and Line by 1 to 49
-  Special opcode 34: advance Address by 4 to 0x50086 and Line by 1 to 50
-  Special opcode 35: advance Address by 4 to 0x5008a and Line by 2 to 52
-  Special opcode 48: advance Address by 6 to 0x50090 and Line by 1 to 53
-  Special opcode 48: advance Address by 6 to 0x50096 and Line by 1 to 54
-  Special opcode 48: advance Address by 6 to 0x5009c and Line by 1 to 55
-  Special opcode 49: advance Address by 6 to 0x500a2 and Line by 2 to 57
-  Special opcode 48: advance Address by 6 to 0x500a8 and Line by 1 to 58
-  Special opcode 48: advance Address by 6 to 0x500ae and Line by 1 to 59
-  Special opcode 48: advance Address by 6 to 0x500b4 and Line by 1 to 60
-  Special opcode 49: advance Address by 6 to 0x500ba and Line by 2 to 62
-  Special opcode 48: advance Address by 6 to 0x500c0 and Line by 1 to 63
-  Special opcode 48: advance Address by 6 to 0x500c6 and Line by 1 to 64
-  Special opcode 48: advance Address by 6 to 0x500cc and Line by 1 to 65
-  Advance PC by 327776 to a012c
+  Special opcode .*: advance Address by 4 to 0x5005e and Line by 1 to 38
+  Special opcode .*: advance Address by 4 to 0x50062 and Line by 1 to 39
+  Special opcode .*: advance Address by 4 to 0x50066 and Line by 1 to 40
+  Special opcode .*: advance Address by 4 to 0x5006a and Line by 2 to 42
+  Special opcode .*: advance Address by 4 to 0x5006e and Line by 1 to 43
+  Special opcode .*: advance Address by 4 to 0x50072 and Line by 1 to 44
+  Special opcode .*: advance Address by 4 to 0x50076 and Line by 1 to 45
+  Special opcode .*: advance Address by 4 to 0x5007a and Line by 2 to 47
+  Special opcode .*: advance Address by 4 to 0x5007e and Line by 1 to 48
+  Special opcode .*: advance Address by 4 to 0x50082 and Line by 1 to 49
+  Special opcode .*: advance Address by 4 to 0x50086 and Line by 1 to 50
+  Special opcode .*: advance Address by 4 to 0x5008a and Line by 2 to 52
+  Special opcode .*: advance Address by 6 to 0x50090 and Line by 1 to 53
+  Special opcode .*: advance Address by 6 to 0x50096 and Line by 1 to 54
+  Special opcode .*: advance Address by 6 to 0x5009c and Line by 1 to 55
+  Special opcode .*: advance Address by 6 to 0x500a2 and Line by 2 to 57
+  Special opcode .*: advance Address by 6 to 0x500a8 and Line by 1 to 58
+  Special opcode .*: advance Address by 6 to 0x500ae and Line by 1 to 59
+  Special opcode .*: advance Address by 6 to 0x500b4 and Line by 1 to 60
+  Special opcode .*: advance Address by 6 to 0x500ba and Line by 2 to 62
+  Special opcode .*: advance Address by 6 to 0x500c0 and Line by 1 to 63
+  Special opcode .*: advance Address by 6 to 0x500c6 and Line by 1 to 64
+  Special opcode .*: advance Address by 6 to 0x500cc and Line by 1 to 65
+  Advance PC by 327776 to 0xa012c
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-3.d b/gas/testsuite/gas/cris/rd-dw2-3.d
index 8be9391bbe1c..272fbf1e748f 100644
--- a/gas/testsuite/gas/cris/rd-dw2-3.d
+++ b/gas/testsuite/gas/cris/rd-dw2-3.d
@@ -6,7 +6,7 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 12: advance Address by 0 to 0x0 and Line by 7 to 8
-  Special opcode 90: advance Address by 12 to 0xc and Line by 1 to 9
-  Advance PC by 2 to e
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 7 to 8
+  Special opcode .*: advance Address by 12 to 0xc and Line by 1 to 9
+  Advance PC by 2 to 0xe
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-4.d b/gas/testsuite/gas/cris/rd-dw2-4.d
index cfd8a439ecde..9a3fbd38f11b 100644
--- a/gas/testsuite/gas/cris/rd-dw2-4.d
+++ b/gas/testsuite/gas/cris/rd-dw2-4.d
@@ -6,8 +6,8 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 12: advance Address by 0 to 0x0 and Line by 7 to 8
-  Advance PC by 32780 to 800c
-  Special opcode 8: advance Address by 0 to 0x800c and Line by 3 to 11
-  Advance PC by 2 to 800e
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 7 to 8
+  Advance PC by 32780 to 0x800c
+  Special opcode .*: advance Address by 0 to 0x800c and Line by 3 to 11
+  Advance PC by 2 to 0x800e
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-5.d b/gas/testsuite/gas/cris/rd-dw2-5.d
index 9758d8273e39..be35ca903054 100644
--- a/gas/testsuite/gas/cris/rd-dw2-5.d
+++ b/gas/testsuite/gas/cris/rd-dw2-5.d
@@ -6,9 +6,9 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 12: advance Address by 0 to 0x0 and Line by 7 to 8
-  Advance PC by 32770 to 8002
-  Special opcode 7: advance Address by 0 to 0x8002 and Line by 2 to 10
-  Special opcode 90: advance Address by 12 to 0x800e and Line by 1 to 11
-  Advance PC by 2 to 8010
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 7 to 8
+  Advance PC by 32770 to 0x8002
+  Special opcode .*: advance Address by 0 to 0x8002 and Line by 2 to 10
+  Special opcode .*: advance Address by 12 to 0x800e and Line by 1 to 11
+  Advance PC by 2 to 0x8010
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-6.d b/gas/testsuite/gas/cris/rd-dw2-6.d
index 799689702fc2..658e5110682d 100644
--- a/gas/testsuite/gas/cris/rd-dw2-6.d
+++ b/gas/testsuite/gas/cris/rd-dw2-6.d
@@ -6,225 +6,225 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 12: advance Address by 0 to 0x0 and Line by 7 to 8
-  Special opcode 21: advance Address by 2 to 0x2 and Line by 2 to 10
-  Advance PC by 32360 to 7e6a
-  Special opcode 8: advance Address by 0 to 0x7e6a and Line by 3 to 13
-  Advance PC by 196 to 7f2e
-  Special opcode 11: advance Address by 0 to 0x7f2e and Line by 6 to 19
-  Special opcode 20: advance Address by 2 to 0x7f30 and Line by 1 to 20
-  Special opcode 20: advance Address by 2 to 0x7f32 and Line by 1 to 21
-  Special opcode 20: advance Address by 2 to 0x7f34 and Line by 1 to 22
-  Special opcode 20: advance Address by 2 to 0x7f36 and Line by 1 to 23
-  Special opcode 20: advance Address by 2 to 0x7f38 and Line by 1 to 24
-  Special opcode 20: advance Address by 2 to 0x7f3a and Line by 1 to 25
-  Special opcode 20: advance Address by 2 to 0x7f3c and Line by 1 to 26
-  Special opcode 20: advance Address by 2 to 0x7f3e and Line by 1 to 27
-  Special opcode 20: advance Address by 2 to 0x7f40 and Line by 1 to 28
-  Special opcode 20: advance Address by 2 to 0x7f42 and Line by 1 to 29
-  Special opcode 20: advance Address by 2 to 0x7f44 and Line by 1 to 30
-  Special opcode 20: advance Address by 2 to 0x7f46 and Line by 1 to 31
-  Special opcode 20: advance Address by 2 to 0x7f48 and Line by 1 to 32
-  Special opcode 20: advance Address by 2 to 0x7f4a and Line by 1 to 33
-  Special opcode 20: advance Address by 2 to 0x7f4c and Line by 1 to 34
-  Special opcode 20: advance Address by 2 to 0x7f4e and Line by 1 to 35
-  Special opcode 20: advance Address by 2 to 0x7f50 and Line by 1 to 36
-  Special opcode 20: advance Address by 2 to 0x7f52 and Line by 1 to 37
-  Special opcode 20: advance Address by 2 to 0x7f54 and Line by 1 to 38
-  Special opcode 20: advance Address by 2 to 0x7f56 and Line by 1 to 39
-  Special opcode 21: advance Address by 2 to 0x7f58 and Line by 2 to 41
-  Special opcode 20: advance Address by 2 to 0x7f5a and Line by 1 to 42
-  Special opcode 20: advance Address by 2 to 0x7f5c and Line by 1 to 43
-  Special opcode 20: advance Address by 2 to 0x7f5e and Line by 1 to 44
-  Special opcode 20: advance Address by 2 to 0x7f60 and Line by 1 to 45
-  Special opcode 20: advance Address by 2 to 0x7f62 and Line by 1 to 46
-  Special opcode 20: advance Address by 2 to 0x7f64 and Line by 1 to 47
-  Special opcode 20: advance Address by 2 to 0x7f66 and Line by 1 to 48
-  Special opcode 20: advance Address by 2 to 0x7f68 and Line by 1 to 49
-  Special opcode 20: advance Address by 2 to 0x7f6a and Line by 1 to 50
-  Special opcode 34: advance Address by 4 to 0x7f6e and Line by 1 to 51
-  Special opcode 34: advance Address by 4 to 0x7f72 and Line by 1 to 52
-  Special opcode 34: advance Address by 4 to 0x7f76 and Line by 1 to 53
-  Special opcode 34: advance Address by 4 to 0x7f7a and Line by 1 to 54
-  Special opcode 34: advance Address by 4 to 0x7f7e and Line by 1 to 55
-  Special opcode 34: advance Address by 4 to 0x7f82 and Line by 1 to 56
-  Special opcode 34: advance Address by 4 to 0x7f86 and Line by 1 to 57
-  Special opcode 34: advance Address by 4 to 0x7f8a and Line by 1 to 58
-  Special opcode 34: advance Address by 4 to 0x7f8e and Line by 1 to 59
-  Special opcode 34: advance Address by 4 to 0x7f92 and Line by 1 to 60
-  Special opcode 34: advance Address by 4 to 0x7f96 and Line by 1 to 61
-  Special opcode 37: advance Address by 4 to 0x7f9a and Line by 4 to 65
-  Special opcode 20: advance Address by 2 to 0x7f9c and Line by 1 to 66
-  Special opcode 34: advance Address by 4 to 0x7fa0 and Line by 1 to 67
-  Special opcode 34: advance Address by 4 to 0x7fa4 and Line by 1 to 68
-  Special opcode 34: advance Address by 4 to 0x7fa8 and Line by 1 to 69
-  Special opcode 34: advance Address by 4 to 0x7fac and Line by 1 to 70
-  Special opcode 34: advance Address by 4 to 0x7fb0 and Line by 1 to 71
-  Special opcode 34: advance Address by 4 to 0x7fb4 and Line by 1 to 72
-  Special opcode 34: advance Address by 4 to 0x7fb8 and Line by 1 to 73
-  Special opcode 34: advance Address by 4 to 0x7fbc and Line by 1 to 74
-  Special opcode 34: advance Address by 4 to 0x7fc0 and Line by 1 to 75
-  Special opcode 34: advance Address by 4 to 0x7fc4 and Line by 1 to 76
-  Special opcode 34: advance Address by 4 to 0x7fc8 and Line by 1 to 77
-  Special opcode 34: advance Address by 4 to 0x7fcc and Line by 1 to 78
-  Special opcode 34: advance Address by 4 to 0x7fd0 and Line by 1 to 79
-  Special opcode 34: advance Address by 4 to 0x7fd4 and Line by 1 to 80
-  Special opcode 34: advance Address by 4 to 0x7fd8 and Line by 1 to 81
-  Special opcode 34: advance Address by 4 to 0x7fdc and Line by 1 to 82
-  Special opcode 34: advance Address by 4 to 0x7fe0 and Line by 1 to 83
-  Special opcode 34: advance Address by 4 to 0x7fe4 and Line by 1 to 84
-  Special opcode 34: advance Address by 4 to 0x7fe8 and Line by 1 to 85
-  Special opcode 39: advance Address by 4 to 0x7fec and Line by 6 to 91
-  Special opcode 20: advance Address by 2 to 0x7fee and Line by 1 to 92
-  Special opcode 34: advance Address by 4 to 0x7ff2 and Line by 1 to 93
-  Special opcode 34: advance Address by 4 to 0x7ff6 and Line by 1 to 94
-  Special opcode 34: advance Address by 4 to 0x7ffa and Line by 1 to 95
-  Special opcode 34: advance Address by 4 to 0x7ffe and Line by 1 to 96
-  Special opcode 34: advance Address by 4 to 0x8002 and Line by 1 to 97
-  Special opcode 90: advance Address by 12 to 0x800e and Line by 1 to 98
-  Special opcode 90: advance Address by 12 to 0x801a and Line by 1 to 99
-  Special opcode 90: advance Address by 12 to 0x8026 and Line by 1 to 100
-  Special opcode 90: advance Address by 12 to 0x8032 and Line by 1 to 101
-  Special opcode 90: advance Address by 12 to 0x803e and Line by 1 to 102
-  Special opcode 90: advance Address by 12 to 0x804a and Line by 1 to 103
-  Special opcode 90: advance Address by 12 to 0x8056 and Line by 1 to 104
-  Special opcode 90: advance Address by 12 to 0x8062 and Line by 1 to 105
-  Special opcode 90: advance Address by 12 to 0x806e and Line by 1 to 106
-  Special opcode 90: advance Address by 12 to 0x807a and Line by 1 to 107
-  Special opcode 90: advance Address by 12 to 0x8086 and Line by 1 to 108
-  Special opcode 90: advance Address by 12 to 0x8092 and Line by 1 to 109
-  Special opcode 90: advance Address by 12 to 0x809e and Line by 1 to 110
-  Special opcode 90: advance Address by 12 to 0x80aa and Line by 1 to 111
-  Special opcode 94: advance Address by 12 to 0x80b6 and Line by 5 to 116
-  Special opcode 20: advance Address by 2 to 0x80b8 and Line by 1 to 117
-  Special opcode 90: advance Address by 12 to 0x80c4 and Line by 1 to 118
-  Special opcode 90: advance Address by 12 to 0x80d0 and Line by 1 to 119
-  Special opcode 90: advance Address by 12 to 0x80dc and Line by 1 to 120
-  Special opcode 90: advance Address by 12 to 0x80e8 and Line by 1 to 121
-  Special opcode 90: advance Address by 12 to 0x80f4 and Line by 1 to 122
-  Special opcode 90: advance Address by 12 to 0x8100 and Line by 1 to 123
-  Special opcode 90: advance Address by 12 to 0x810c and Line by 1 to 124
-  Special opcode 90: advance Address by 12 to 0x8118 and Line by 1 to 125
-  Special opcode 90: advance Address by 12 to 0x8124 and Line by 1 to 126
-  Special opcode 90: advance Address by 12 to 0x8130 and Line by 1 to 127
-  Special opcode 90: advance Address by 12 to 0x813c and Line by 1 to 128
-  Special opcode 90: advance Address by 12 to 0x8148 and Line by 1 to 129
-  Special opcode 90: advance Address by 12 to 0x8154 and Line by 1 to 130
-  Special opcode 90: advance Address by 12 to 0x8160 and Line by 1 to 131
-  Special opcode 90: advance Address by 12 to 0x816c and Line by 1 to 132
-  Special opcode 90: advance Address by 12 to 0x8178 and Line by 1 to 133
-  Special opcode 90: advance Address by 12 to 0x8184 and Line by 1 to 134
-  Special opcode 90: advance Address by 12 to 0x8190 and Line by 1 to 135
-  Special opcode 90: advance Address by 12 to 0x819c and Line by 1 to 136
-  Special opcode 95: advance Address by 12 to 0x81a8 and Line by 6 to 142
-  Special opcode 20: advance Address by 2 to 0x81aa and Line by 1 to 143
-  Special opcode 90: advance Address by 12 to 0x81b6 and Line by 1 to 144
-  Special opcode 90: advance Address by 12 to 0x81c2 and Line by 1 to 145
-  Special opcode 90: advance Address by 12 to 0x81ce and Line by 1 to 146
-  Special opcode 90: advance Address by 12 to 0x81da and Line by 1 to 147
-  Special opcode 90: advance Address by 12 to 0x81e6 and Line by 1 to 148
-  Special opcode 90: advance Address by 12 to 0x81f2 and Line by 1 to 149
-  Special opcode 90: advance Address by 12 to 0x81fe and Line by 1 to 150
-  Special opcode 90: advance Address by 12 to 0x820a and Line by 1 to 151
-  Special opcode 90: advance Address by 12 to 0x8216 and Line by 1 to 152
-  Special opcode 90: advance Address by 12 to 0x8222 and Line by 1 to 153
-  Special opcode 90: advance Address by 12 to 0x822e and Line by 1 to 154
-  Special opcode 90: advance Address by 12 to 0x823a and Line by 1 to 155
-  Special opcode 90: advance Address by 12 to 0x8246 and Line by 1 to 156
-  Special opcode 90: advance Address by 12 to 0x8252 and Line by 1 to 157
-  Special opcode 90: advance Address by 12 to 0x825e and Line by 1 to 158
-  Special opcode 90: advance Address by 12 to 0x826a and Line by 1 to 159
-  Special opcode 90: advance Address by 12 to 0x8276 and Line by 1 to 160
-  Special opcode 90: advance Address by 12 to 0x8282 and Line by 1 to 161
-  Special opcode 90: advance Address by 12 to 0x828e and Line by 1 to 162
-  Special opcode 94: advance Address by 12 to 0x829a and Line by 5 to 167
-  Special opcode 20: advance Address by 2 to 0x829c and Line by 1 to 168
-  Special opcode 90: advance Address by 12 to 0x82a8 and Line by 1 to 169
-  Special opcode 90: advance Address by 12 to 0x82b4 and Line by 1 to 170
-  Special opcode 90: advance Address by 12 to 0x82c0 and Line by 1 to 171
-  Special opcode 90: advance Address by 12 to 0x82cc and Line by 1 to 172
-  Special opcode 90: advance Address by 12 to 0x82d8 and Line by 1 to 173
-  Special opcode 90: advance Address by 12 to 0x82e4 and Line by 1 to 174
-  Special opcode 90: advance Address by 12 to 0x82f0 and Line by 1 to 175
-  Special opcode 90: advance Address by 12 to 0x82fc and Line by 1 to 176
-  Special opcode 90: advance Address by 12 to 0x8308 and Line by 1 to 177
-  Special opcode 90: advance Address by 12 to 0x8314 and Line by 1 to 178
-  Special opcode 90: advance Address by 12 to 0x8320 and Line by 1 to 179
-  Special opcode 90: advance Address by 12 to 0x832c and Line by 1 to 180
-  Special opcode 90: advance Address by 12 to 0x8338 and Line by 1 to 181
-  Special opcode 90: advance Address by 12 to 0x8344 and Line by 1 to 182
-  Special opcode 34: advance Address by 4 to 0x8348 and Line by 1 to 183
-  Special opcode 34: advance Address by 4 to 0x834c and Line by 1 to 184
-  Special opcode 34: advance Address by 4 to 0x8350 and Line by 1 to 185
-  Special opcode 34: advance Address by 4 to 0x8354 and Line by 1 to 186
-  Special opcode 34: advance Address by 4 to 0x8358 and Line by 1 to 187
-  Special opcode 38: advance Address by 4 to 0x835c and Line by 5 to 192
-  Special opcode 20: advance Address by 2 to 0x835e and Line by 1 to 193
-  Special opcode 34: advance Address by 4 to 0x8362 and Line by 1 to 194
-  Special opcode 34: advance Address by 4 to 0x8366 and Line by 1 to 195
-  Special opcode 34: advance Address by 4 to 0x836a and Line by 1 to 196
-  Special opcode 34: advance Address by 4 to 0x836e and Line by 1 to 197
-  Special opcode 34: advance Address by 4 to 0x8372 and Line by 1 to 198
-  Special opcode 34: advance Address by 4 to 0x8376 and Line by 1 to 199
-  Special opcode 34: advance Address by 4 to 0x837a and Line by 1 to 200
-  Special opcode 34: advance Address by 4 to 0x837e and Line by 1 to 201
-  Special opcode 34: advance Address by 4 to 0x8382 and Line by 1 to 202
-  Special opcode 34: advance Address by 4 to 0x8386 and Line by 1 to 203
-  Special opcode 34: advance Address by 4 to 0x838a and Line by 1 to 204
-  Special opcode 34: advance Address by 4 to 0x838e and Line by 1 to 205
-  Special opcode 34: advance Address by 4 to 0x8392 and Line by 1 to 206
-  Special opcode 34: advance Address by 4 to 0x8396 and Line by 1 to 207
-  Special opcode 34: advance Address by 4 to 0x839a and Line by 1 to 208
-  Special opcode 34: advance Address by 4 to 0x839e and Line by 1 to 209
-  Special opcode 34: advance Address by 4 to 0x83a2 and Line by 1 to 210
-  Special opcode 34: advance Address by 4 to 0x83a6 and Line by 1 to 211
-  Special opcode 34: advance Address by 4 to 0x83aa and Line by 1 to 212
-  Special opcode 38: advance Address by 4 to 0x83ae and Line by 5 to 217
-  Special opcode 20: advance Address by 2 to 0x83b0 and Line by 1 to 218
-  Special opcode 34: advance Address by 4 to 0x83b4 and Line by 1 to 219
-  Special opcode 34: advance Address by 4 to 0x83b8 and Line by 1 to 220
-  Special opcode 34: advance Address by 4 to 0x83bc and Line by 1 to 221
-  Special opcode 34: advance Address by 4 to 0x83c0 and Line by 1 to 222
-  Special opcode 34: advance Address by 4 to 0x83c4 and Line by 1 to 223
-  Special opcode 34: advance Address by 4 to 0x83c8 and Line by 1 to 224
-  Special opcode 34: advance Address by 4 to 0x83cc and Line by 1 to 225
-  Special opcode 34: advance Address by 4 to 0x83d0 and Line by 1 to 226
-  Special opcode 34: advance Address by 4 to 0x83d4 and Line by 1 to 227
-  Special opcode 34: advance Address by 4 to 0x83d8 and Line by 1 to 228
-  Special opcode 34: advance Address by 4 to 0x83dc and Line by 1 to 229
-  Special opcode 20: advance Address by 2 to 0x83de and Line by 1 to 230
-  Special opcode 20: advance Address by 2 to 0x83e0 and Line by 1 to 231
-  Special opcode 20: advance Address by 2 to 0x83e2 and Line by 1 to 232
-  Special opcode 20: advance Address by 2 to 0x83e4 and Line by 1 to 233
-  Special opcode 20: advance Address by 2 to 0x83e6 and Line by 1 to 234
-  Special opcode 20: advance Address by 2 to 0x83e8 and Line by 1 to 235
-  Special opcode 20: advance Address by 2 to 0x83ea and Line by 1 to 236
-  Special opcode 20: advance Address by 2 to 0x83ec and Line by 1 to 237
-  Special opcode 24: advance Address by 2 to 0x83ee and Line by 5 to 242
-  Special opcode 20: advance Address by 2 to 0x83f0 and Line by 1 to 243
-  Special opcode 20: advance Address by 2 to 0x83f2 and Line by 1 to 244
-  Special opcode 20: advance Address by 2 to 0x83f4 and Line by 1 to 245
-  Special opcode 20: advance Address by 2 to 0x83f6 and Line by 1 to 246
-  Special opcode 20: advance Address by 2 to 0x83f8 and Line by 1 to 247
-  Special opcode 20: advance Address by 2 to 0x83fa and Line by 1 to 248
-  Special opcode 20: advance Address by 2 to 0x83fc and Line by 1 to 249
-  Special opcode 20: advance Address by 2 to 0x83fe and Line by 1 to 250
-  Special opcode 20: advance Address by 2 to 0x8400 and Line by 1 to 251
-  Special opcode 20: advance Address by 2 to 0x8402 and Line by 1 to 252
-  Special opcode 20: advance Address by 2 to 0x8404 and Line by 1 to 253
-  Special opcode 20: advance Address by 2 to 0x8406 and Line by 1 to 254
-  Special opcode 20: advance Address by 2 to 0x8408 and Line by 1 to 255
-  Special opcode 20: advance Address by 2 to 0x840a and Line by 1 to 256
-  Special opcode 20: advance Address by 2 to 0x840c and Line by 1 to 257
-  Special opcode 20: advance Address by 2 to 0x840e and Line by 1 to 258
-  Special opcode 20: advance Address by 2 to 0x8410 and Line by 1 to 259
-  Special opcode 20: advance Address by 2 to 0x8412 and Line by 1 to 260
-  Special opcode 20: advance Address by 2 to 0x8414 and Line by 1 to 261
-  Special opcode 20: advance Address by 2 to 0x8416 and Line by 1 to 262
-  Special opcode 21: advance Address by 2 to 0x8418 and Line by 2 to 264
-  Advance PC by 196 to 84dc
-  Special opcode 8: advance Address by 0 to 0x84dc and Line by 3 to 267
-  Advance PC by 32360 to 10344
-  Special opcode 8: advance Address by 0 to 0x10344 and Line by 3 to 270
-  Advance PC by 2 to 10346
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 7 to 8
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 2 to 10
+  Advance PC by 32360 to 0x7e6a
+  Special opcode .*: advance Address by 0 to 0x7e6a and Line by 3 to 13
+  Advance PC by 196 to 0x7f2e
+  Special opcode .*: advance Address by 0 to 0x7f2e and Line by 6 to 19
+  Special opcode .*: advance Address by 2 to 0x7f30 and Line by 1 to 20
+  Special opcode .*: advance Address by 2 to 0x7f32 and Line by 1 to 21
+  Special opcode .*: advance Address by 2 to 0x7f34 and Line by 1 to 22
+  Special opcode .*: advance Address by 2 to 0x7f36 and Line by 1 to 23
+  Special opcode .*: advance Address by 2 to 0x7f38 and Line by 1 to 24
+  Special opcode .*: advance Address by 2 to 0x7f3a and Line by 1 to 25
+  Special opcode .*: advance Address by 2 to 0x7f3c and Line by 1 to 26
+  Special opcode .*: advance Address by 2 to 0x7f3e and Line by 1 to 27
+  Special opcode .*: advance Address by 2 to 0x7f40 and Line by 1 to 28
+  Special opcode .*: advance Address by 2 to 0x7f42 and Line by 1 to 29
+  Special opcode .*: advance Address by 2 to 0x7f44 and Line by 1 to 30
+  Special opcode .*: advance Address by 2 to 0x7f46 and Line by 1 to 31
+  Special opcode .*: advance Address by 2 to 0x7f48 and Line by 1 to 32
+  Special opcode .*: advance Address by 2 to 0x7f4a and Line by 1 to 33
+  Special opcode .*: advance Address by 2 to 0x7f4c and Line by 1 to 34
+  Special opcode .*: advance Address by 2 to 0x7f4e and Line by 1 to 35
+  Special opcode .*: advance Address by 2 to 0x7f50 and Line by 1 to 36
+  Special opcode .*: advance Address by 2 to 0x7f52 and Line by 1 to 37
+  Special opcode .*: advance Address by 2 to 0x7f54 and Line by 1 to 38
+  Special opcode .*: advance Address by 2 to 0x7f56 and Line by 1 to 39
+  Special opcode .*: advance Address by 2 to 0x7f58 and Line by 2 to 41
+  Special opcode .*: advance Address by 2 to 0x7f5a and Line by 1 to 42
+  Special opcode .*: advance Address by 2 to 0x7f5c and Line by 1 to 43
+  Special opcode .*: advance Address by 2 to 0x7f5e and Line by 1 to 44
+  Special opcode .*: advance Address by 2 to 0x7f60 and Line by 1 to 45
+  Special opcode .*: advance Address by 2 to 0x7f62 and Line by 1 to 46
+  Special opcode .*: advance Address by 2 to 0x7f64 and Line by 1 to 47
+  Special opcode .*: advance Address by 2 to 0x7f66 and Line by 1 to 48
+  Special opcode .*: advance Address by 2 to 0x7f68 and Line by 1 to 49
+  Special opcode .*: advance Address by 2 to 0x7f6a and Line by 1 to 50
+  Special opcode .*: advance Address by 4 to 0x7f6e and Line by 1 to 51
+  Special opcode .*: advance Address by 4 to 0x7f72 and Line by 1 to 52
+  Special opcode .*: advance Address by 4 to 0x7f76 and Line by 1 to 53
+  Special opcode .*: advance Address by 4 to 0x7f7a and Line by 1 to 54
+  Special opcode .*: advance Address by 4 to 0x7f7e and Line by 1 to 55
+  Special opcode .*: advance Address by 4 to 0x7f82 and Line by 1 to 56
+  Special opcode .*: advance Address by 4 to 0x7f86 and Line by 1 to 57
+  Special opcode .*: advance Address by 4 to 0x7f8a and Line by 1 to 58
+  Special opcode .*: advance Address by 4 to 0x7f8e and Line by 1 to 59
+  Special opcode .*: advance Address by 4 to 0x7f92 and Line by 1 to 60
+  Special opcode .*: advance Address by 4 to 0x7f96 and Line by 1 to 61
+  Special opcode .*: advance Address by 4 to 0x7f9a and Line by 4 to 65
+  Special opcode .*: advance Address by 2 to 0x7f9c and Line by 1 to 66
+  Special opcode .*: advance Address by 4 to 0x7fa0 and Line by 1 to 67
+  Special opcode .*: advance Address by 4 to 0x7fa4 and Line by 1 to 68
+  Special opcode .*: advance Address by 4 to 0x7fa8 and Line by 1 to 69
+  Special opcode .*: advance Address by 4 to 0x7fac and Line by 1 to 70
+  Special opcode .*: advance Address by 4 to 0x7fb0 and Line by 1 to 71
+  Special opcode .*: advance Address by 4 to 0x7fb4 and Line by 1 to 72
+  Special opcode .*: advance Address by 4 to 0x7fb8 and Line by 1 to 73
+  Special opcode .*: advance Address by 4 to 0x7fbc and Line by 1 to 74
+  Special opcode .*: advance Address by 4 to 0x7fc0 and Line by 1 to 75
+  Special opcode .*: advance Address by 4 to 0x7fc4 and Line by 1 to 76
+  Special opcode .*: advance Address by 4 to 0x7fc8 and Line by 1 to 77
+  Special opcode .*: advance Address by 4 to 0x7fcc and Line by 1 to 78
+  Special opcode .*: advance Address by 4 to 0x7fd0 and Line by 1 to 79
+  Special opcode .*: advance Address by 4 to 0x7fd4 and Line by 1 to 80
+  Special opcode .*: advance Address by 4 to 0x7fd8 and Line by 1 to 81
+  Special opcode .*: advance Address by 4 to 0x7fdc and Line by 1 to 82
+  Special opcode .*: advance Address by 4 to 0x7fe0 and Line by 1 to 83
+  Special opcode .*: advance Address by 4 to 0x7fe4 and Line by 1 to 84
+  Special opcode .*: advance Address by 4 to 0x7fe8 and Line by 1 to 85
+  Special opcode .*: advance Address by 4 to 0x7fec and Line by 6 to 91
+  Special opcode .*: advance Address by 2 to 0x7fee and Line by 1 to 92
+  Special opcode .*: advance Address by 4 to 0x7ff2 and Line by 1 to 93
+  Special opcode .*: advance Address by 4 to 0x7ff6 and Line by 1 to 94
+  Special opcode .*: advance Address by 4 to 0x7ffa and Line by 1 to 95
+  Special opcode .*: advance Address by 4 to 0x7ffe and Line by 1 to 96
+  Special opcode .*: advance Address by 4 to 0x8002 and Line by 1 to 97
+  Special opcode .*: advance Address by 12 to 0x800e and Line by 1 to 98
+  Special opcode .*: advance Address by 12 to 0x801a and Line by 1 to 99
+  Special opcode .*: advance Address by 12 to 0x8026 and Line by 1 to 100
+  Special opcode .*: advance Address by 12 to 0x8032 and Line by 1 to 101
+  Special opcode .*: advance Address by 12 to 0x803e and Line by 1 to 102
+  Special opcode .*: advance Address by 12 to 0x804a and Line by 1 to 103
+  Special opcode .*: advance Address by 12 to 0x8056 and Line by 1 to 104
+  Special opcode .*: advance Address by 12 to 0x8062 and Line by 1 to 105
+  Special opcode .*: advance Address by 12 to 0x806e and Line by 1 to 106
+  Special opcode .*: advance Address by 12 to 0x807a and Line by 1 to 107
+  Special opcode .*: advance Address by 12 to 0x8086 and Line by 1 to 108
+  Special opcode .*: advance Address by 12 to 0x8092 and Line by 1 to 109
+  Special opcode .*: advance Address by 12 to 0x809e and Line by 1 to 110
+  Special opcode .*: advance Address by 12 to 0x80aa and Line by 1 to 111
+  Special opcode .*: advance Address by 12 to 0x80b6 and Line by 5 to 116
+  Special opcode .*: advance Address by 2 to 0x80b8 and Line by 1 to 117
+  Special opcode .*: advance Address by 12 to 0x80c4 and Line by 1 to 118
+  Special opcode .*: advance Address by 12 to 0x80d0 and Line by 1 to 119
+  Special opcode .*: advance Address by 12 to 0x80dc and Line by 1 to 120
+  Special opcode .*: advance Address by 12 to 0x80e8 and Line by 1 to 121
+  Special opcode .*: advance Address by 12 to 0x80f4 and Line by 1 to 122
+  Special opcode .*: advance Address by 12 to 0x8100 and Line by 1 to 123
+  Special opcode .*: advance Address by 12 to 0x810c and Line by 1 to 124
+  Special opcode .*: advance Address by 12 to 0x8118 and Line by 1 to 125
+  Special opcode .*: advance Address by 12 to 0x8124 and Line by 1 to 126
+  Special opcode .*: advance Address by 12 to 0x8130 and Line by 1 to 127
+  Special opcode .*: advance Address by 12 to 0x813c and Line by 1 to 128
+  Special opcode .*: advance Address by 12 to 0x8148 and Line by 1 to 129
+  Special opcode .*: advance Address by 12 to 0x8154 and Line by 1 to 130
+  Special opcode .*: advance Address by 12 to 0x8160 and Line by 1 to 131
+  Special opcode .*: advance Address by 12 to 0x816c and Line by 1 to 132
+  Special opcode .*: advance Address by 12 to 0x8178 and Line by 1 to 133
+  Special opcode .*: advance Address by 12 to 0x8184 and Line by 1 to 134
+  Special opcode .*: advance Address by 12 to 0x8190 and Line by 1 to 135
+  Special opcode .*: advance Address by 12 to 0x819c and Line by 1 to 136
+  Special opcode .*: advance Address by 12 to 0x81a8 and Line by 6 to 142
+  Special opcode .*: advance Address by 2 to 0x81aa and Line by 1 to 143
+  Special opcode .*: advance Address by 12 to 0x81b6 and Line by 1 to 144
+  Special opcode .*: advance Address by 12 to 0x81c2 and Line by 1 to 145
+  Special opcode .*: advance Address by 12 to 0x81ce and Line by 1 to 146
+  Special opcode .*: advance Address by 12 to 0x81da and Line by 1 to 147
+  Special opcode .*: advance Address by 12 to 0x81e6 and Line by 1 to 148
+  Special opcode .*: advance Address by 12 to 0x81f2 and Line by 1 to 149
+  Special opcode .*: advance Address by 12 to 0x81fe and Line by 1 to 150
+  Special opcode .*: advance Address by 12 to 0x820a and Line by 1 to 151
+  Special opcode .*: advance Address by 12 to 0x8216 and Line by 1 to 152
+  Special opcode .*: advance Address by 12 to 0x8222 and Line by 1 to 153
+  Special opcode .*: advance Address by 12 to 0x822e and Line by 1 to 154
+  Special opcode .*: advance Address by 12 to 0x823a and Line by 1 to 155
+  Special opcode .*: advance Address by 12 to 0x8246 and Line by 1 to 156
+  Special opcode .*: advance Address by 12 to 0x8252 and Line by 1 to 157
+  Special opcode .*: advance Address by 12 to 0x825e and Line by 1 to 158
+  Special opcode .*: advance Address by 12 to 0x826a and Line by 1 to 159
+  Special opcode .*: advance Address by 12 to 0x8276 and Line by 1 to 160
+  Special opcode .*: advance Address by 12 to 0x8282 and Line by 1 to 161
+  Special opcode .*: advance Address by 12 to 0x828e and Line by 1 to 162
+  Special opcode .*: advance Address by 12 to 0x829a and Line by 5 to 167
+  Special opcode .*: advance Address by 2 to 0x829c and Line by 1 to 168
+  Special opcode .*: advance Address by 12 to 0x82a8 and Line by 1 to 169
+  Special opcode .*: advance Address by 12 to 0x82b4 and Line by 1 to 170
+  Special opcode .*: advance Address by 12 to 0x82c0 and Line by 1 to 171
+  Special opcode .*: advance Address by 12 to 0x82cc and Line by 1 to 172
+  Special opcode .*: advance Address by 12 to 0x82d8 and Line by 1 to 173
+  Special opcode .*: advance Address by 12 to 0x82e4 and Line by 1 to 174
+  Special opcode .*: advance Address by 12 to 0x82f0 and Line by 1 to 175
+  Special opcode .*: advance Address by 12 to 0x82fc and Line by 1 to 176
+  Special opcode .*: advance Address by 12 to 0x8308 and Line by 1 to 177
+  Special opcode .*: advance Address by 12 to 0x8314 and Line by 1 to 178
+  Special opcode .*: advance Address by 12 to 0x8320 and Line by 1 to 179
+  Special opcode .*: advance Address by 12 to 0x832c and Line by 1 to 180
+  Special opcode .*: advance Address by 12 to 0x8338 and Line by 1 to 181
+  Special opcode .*: advance Address by 12 to 0x8344 and Line by 1 to 182
+  Special opcode .*: advance Address by 4 to 0x8348 and Line by 1 to 183
+  Special opcode .*: advance Address by 4 to 0x834c and Line by 1 to 184
+  Special opcode .*: advance Address by 4 to 0x8350 and Line by 1 to 185
+  Special opcode .*: advance Address by 4 to 0x8354 and Line by 1 to 186
+  Special opcode .*: advance Address by 4 to 0x8358 and Line by 1 to 187
+  Special opcode .*: advance Address by 4 to 0x835c and Line by 5 to 192
+  Special opcode .*: advance Address by 2 to 0x835e and Line by 1 to 193
+  Special opcode .*: advance Address by 4 to 0x8362 and Line by 1 to 194
+  Special opcode .*: advance Address by 4 to 0x8366 and Line by 1 to 195
+  Special opcode .*: advance Address by 4 to 0x836a and Line by 1 to 196
+  Special opcode .*: advance Address by 4 to 0x836e and Line by 1 to 197
+  Special opcode .*: advance Address by 4 to 0x8372 and Line by 1 to 198
+  Special opcode .*: advance Address by 4 to 0x8376 and Line by 1 to 199
+  Special opcode .*: advance Address by 4 to 0x837a and Line by 1 to 200
+  Special opcode .*: advance Address by 4 to 0x837e and Line by 1 to 201
+  Special opcode .*: advance Address by 4 to 0x8382 and Line by 1 to 202
+  Special opcode .*: advance Address by 4 to 0x8386 and Line by 1 to 203
+  Special opcode .*: advance Address by 4 to 0x838a and Line by 1 to 204
+  Special opcode .*: advance Address by 4 to 0x838e and Line by 1 to 205
+  Special opcode .*: advance Address by 4 to 0x8392 and Line by 1 to 206
+  Special opcode .*: advance Address by 4 to 0x8396 and Line by 1 to 207
+  Special opcode .*: advance Address by 4 to 0x839a and Line by 1 to 208
+  Special opcode .*: advance Address by 4 to 0x839e and Line by 1 to 209
+  Special opcode .*: advance Address by 4 to 0x83a2 and Line by 1 to 210
+  Special opcode .*: advance Address by 4 to 0x83a6 and Line by 1 to 211
+  Special opcode .*: advance Address by 4 to 0x83aa and Line by 1 to 212
+  Special opcode .*: advance Address by 4 to 0x83ae and Line by 5 to 217
+  Special opcode .*: advance Address by 2 to 0x83b0 and Line by 1 to 218
+  Special opcode .*: advance Address by 4 to 0x83b4 and Line by 1 to 219
+  Special opcode .*: advance Address by 4 to 0x83b8 and Line by 1 to 220
+  Special opcode .*: advance Address by 4 to 0x83bc and Line by 1 to 221
+  Special opcode .*: advance Address by 4 to 0x83c0 and Line by 1 to 222
+  Special opcode .*: advance Address by 4 to 0x83c4 and Line by 1 to 223
+  Special opcode .*: advance Address by 4 to 0x83c8 and Line by 1 to 224
+  Special opcode .*: advance Address by 4 to 0x83cc and Line by 1 to 225
+  Special opcode .*: advance Address by 4 to 0x83d0 and Line by 1 to 226
+  Special opcode .*: advance Address by 4 to 0x83d4 and Line by 1 to 227
+  Special opcode .*: advance Address by 4 to 0x83d8 and Line by 1 to 228
+  Special opcode .*: advance Address by 4 to 0x83dc and Line by 1 to 229
+  Special opcode .*: advance Address by 2 to 0x83de and Line by 1 to 230
+  Special opcode .*: advance Address by 2 to 0x83e0 and Line by 1 to 231
+  Special opcode .*: advance Address by 2 to 0x83e2 and Line by 1 to 232
+  Special opcode .*: advance Address by 2 to 0x83e4 and Line by 1 to 233
+  Special opcode .*: advance Address by 2 to 0x83e6 and Line by 1 to 234
+  Special opcode .*: advance Address by 2 to 0x83e8 and Line by 1 to 235
+  Special opcode .*: advance Address by 2 to 0x83ea and Line by 1 to 236
+  Special opcode .*: advance Address by 2 to 0x83ec and Line by 1 to 237
+  Special opcode .*: advance Address by 2 to 0x83ee and Line by 5 to 242
+  Special opcode .*: advance Address by 2 to 0x83f0 and Line by 1 to 243
+  Special opcode .*: advance Address by 2 to 0x83f2 and Line by 1 to 244
+  Special opcode .*: advance Address by 2 to 0x83f4 and Line by 1 to 245
+  Special opcode .*: advance Address by 2 to 0x83f6 and Line by 1 to 246
+  Special opcode .*: advance Address by 2 to 0x83f8 and Line by 1 to 247
+  Special opcode .*: advance Address by 2 to 0x83fa and Line by 1 to 248
+  Special opcode .*: advance Address by 2 to 0x83fc and Line by 1 to 249
+  Special opcode .*: advance Address by 2 to 0x83fe and Line by 1 to 250
+  Special opcode .*: advance Address by 2 to 0x8400 and Line by 1 to 251
+  Special opcode .*: advance Address by 2 to 0x8402 and Line by 1 to 252
+  Special opcode .*: advance Address by 2 to 0x8404 and Line by 1 to 253
+  Special opcode .*: advance Address by 2 to 0x8406 and Line by 1 to 254
+  Special opcode .*: advance Address by 2 to 0x8408 and Line by 1 to 255
+  Special opcode .*: advance Address by 2 to 0x840a and Line by 1 to 256
+  Special opcode .*: advance Address by 2 to 0x840c and Line by 1 to 257
+  Special opcode .*: advance Address by 2 to 0x840e and Line by 1 to 258
+  Special opcode .*: advance Address by 2 to 0x8410 and Line by 1 to 259
+  Special opcode .*: advance Address by 2 to 0x8412 and Line by 1 to 260
+  Special opcode .*: advance Address by 2 to 0x8414 and Line by 1 to 261
+  Special opcode .*: advance Address by 2 to 0x8416 and Line by 1 to 262
+  Special opcode .*: advance Address by 2 to 0x8418 and Line by 2 to 264
+  Advance PC by 196 to 0x84dc
+  Special opcode .*: advance Address by 0 to 0x84dc and Line by 3 to 267
+  Advance PC by 32360 to 0x10344
+  Special opcode .*: advance Address by 0 to 0x10344 and Line by 3 to 270
+  Advance PC by 2 to 0x10346
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-7.d b/gas/testsuite/gas/cris/rd-dw2-7.d
index 14765aaf930b..ad99a3f6a813 100644
--- a/gas/testsuite/gas/cris/rd-dw2-7.d
+++ b/gas/testsuite/gas/cris/rd-dw2-7.d
@@ -6,10 +6,10 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 7: advance Address by 0 to 0x0 and Line by 2 to 3
-  Special opcode 37: advance Address by 4 to 0x4 and Line by 4 to 7
-  Special opcode 111: advance Address by 14 to 0x12 and Line by 8 to 15
-  Advance PC by 32768 to 8012
-  Special opcode 9: advance Address by 0 to 0x8012 and Line by 4 to 19
-  Advance PC by 2 to 8014
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 2 to 3
+  Special opcode .*: advance Address by 4 to 0x4 and Line by 4 to 7
+  Special opcode .*: advance Address by 14 to 0x12 and Line by 8 to 15
+  Advance PC by 32768 to 0x8012
+  Special opcode .*: advance Address by 0 to 0x8012 and Line by 4 to 19
+  Advance PC by 2 to 0x8014
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-8.d b/gas/testsuite/gas/cris/rd-dw2-8.d
index a9e1c85dfe42..d141412641fb 100644
--- a/gas/testsuite/gas/cris/rd-dw2-8.d
+++ b/gas/testsuite/gas/cris/rd-dw2-8.d
@@ -6,12 +6,12 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 7: advance Address by 0 to 0x0 and Line by 2 to 3
-  Special opcode 52: advance Address by 6 to 0x6 and Line by 5 to 8
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 2 to 3
+  Special opcode .*: advance Address by 6 to 0x6 and Line by 5 to 8
   Advance Line by 9 to 17
-  Special opcode 145: advance Address by 20 to 0x1a and Line by 0 to 17
-  Advance PC by 32768 to 801a
-  Special opcode 9: advance Address by 0 to 0x801a and Line by 4 to 21
-  Special opcode 20: advance Address by 2 to 0x801c and Line by 1 to 22
-  Advance PC by 2 to 801e
+  Special opcode .*: advance Address by 20 to 0x1a and Line by 0 to 17
+  Advance PC by 32768 to 0x801a
+  Special opcode .*: advance Address by 0 to 0x801a and Line by 4 to 21
+  Special opcode .*: advance Address by 2 to 0x801c and Line by 1 to 22
+  Advance PC by 2 to 0x801e
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-dw2-9.d b/gas/testsuite/gas/cris/rd-dw2-9.d
index 53ec1e0773c3..0290ad2a4a5d 100644
--- a/gas/testsuite/gas/cris/rd-dw2-9.d
+++ b/gas/testsuite/gas/cris/rd-dw2-9.d
@@ -6,58 +6,58 @@
 #...
  Line Number Statements:
   Extended opcode 2: set Address to 0x0
-  Special opcode 8: advance Address by 0 to 0x0 and Line by 3 to 4
-  Special opcode 23: advance Address by 2 to 0x2 and Line by 4 to 8
-  Special opcode 34: advance Address by 4 to 0x6 and Line by 1 to 9
-  Special opcode 34: advance Address by 4 to 0xa and Line by 1 to 10
+  Special opcode .*: advance Address by 0 to 0x0 and Line by 3 to 4
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 4 to 8
+  Special opcode .*: advance Address by 4 to 0x6 and Line by 1 to 9
+  Special opcode .*: advance Address by 4 to 0xa and Line by 1 to 10
   Advance Line by 47 to 57
-  Advance PC by 104 to 72
+  Advance PC by 104 to 0x72
   Copy
   Advance Line by 10 to 67
-  Advance PC by 260 to 176
+  Advance PC by 260 to 0x176
   Copy
-  Advance PC by 32770 to 8178
-  Special opcode 9: advance Address by 0 to 0x8178 and Line by 4 to 71
-  Special opcode 20: advance Address by 2 to 0x817a and Line by 1 to 72
-  Special opcode 20: advance Address by 2 to 0x817c and Line by 1 to 73
-  Special opcode 20: advance Address by 2 to 0x817e and Line by 1 to 74
-  Special opcode 20: advance Address by 2 to 0x8180 and Line by 1 to 75
-  Special opcode 20: advance Address by 2 to 0x8182 and Line by 1 to 76
-  Special opcode 20: advance Address by 2 to 0x8184 and Line by 1 to 77
-  Special opcode 20: advance Address by 2 to 0x8186 and Line by 1 to 78
-  Special opcode 20: advance Address by 2 to 0x8188 and Line by 1 to 79
-  Special opcode 20: advance Address by 2 to 0x818a and Line by 1 to 80
-  Special opcode 20: advance Address by 2 to 0x818c and Line by 1 to 81
-  Special opcode 20: advance Address by 2 to 0x818e and Line by 1 to 82
-  Special opcode 20: advance Address by 2 to 0x8190 and Line by 1 to 83
-  Special opcode 20: advance Address by 2 to 0x8192 and Line by 1 to 84
-  Special opcode 20: advance Address by 2 to 0x8194 and Line by 1 to 85
-  Special opcode 20: advance Address by 2 to 0x8196 and Line by 1 to 86
-  Special opcode 20: advance Address by 2 to 0x8198 and Line by 1 to 87
-  Special opcode 20: advance Address by 2 to 0x819a and Line by 1 to 88
-  Special opcode 20: advance Address by 2 to 0x819c and Line by 1 to 89
-  Special opcode 20: advance Address by 2 to 0x819e and Line by 1 to 90
-  Special opcode 20: advance Address by 2 to 0x81a0 and Line by 1 to 91
-  Special opcode 20: advance Address by 2 to 0x81a2 and Line by 1 to 92
-  Special opcode 20: advance Address by 2 to 0x81a4 and Line by 1 to 93
-  Special opcode 20: advance Address by 2 to 0x81a6 and Line by 1 to 94
-  Special opcode 20: advance Address by 2 to 0x81a8 and Line by 1 to 95
-  Special opcode 20: advance Address by 2 to 0x81aa and Line by 1 to 96
-  Special opcode 20: advance Address by 2 to 0x81ac and Line by 1 to 97
-  Special opcode 20: advance Address by 2 to 0x81ae and Line by 1 to 98
-  Special opcode 20: advance Address by 2 to 0x81b0 and Line by 1 to 99
-  Special opcode 20: advance Address by 2 to 0x81b2 and Line by 1 to 100
-  Special opcode 20: advance Address by 2 to 0x81b4 and Line by 1 to 101
-  Special opcode 20: advance Address by 2 to 0x81b6 and Line by 1 to 102
-  Special opcode 20: advance Address by 2 to 0x81b8 and Line by 1 to 103
-  Special opcode 20: advance Address by 2 to 0x81ba and Line by 1 to 104
-  Special opcode 20: advance Address by 2 to 0x81bc and Line by 1 to 105
-  Special opcode 20: advance Address by 2 to 0x81be and Line by 1 to 106
-  Special opcode 20: advance Address by 2 to 0x81c0 and Line by 1 to 107
-  Special opcode 20: advance Address by 2 to 0x81c2 and Line by 1 to 108
-  Special opcode 20: advance Address by 2 to 0x81c4 and Line by 1 to 109
-  Special opcode 20: advance Address by 2 to 0x81c6 and Line by 1 to 110
-  Special opcode 20: advance Address by 2 to 0x81c8 and Line by 1 to 111
-  Special opcode 20: advance Address by 2 to 0x81ca and Line by 1 to 112
-  Advance PC by 2 to 81cc
+  Advance PC by 32770 to 0x8178
+  Special opcode .*: advance Address by 0 to 0x8178 and Line by 4 to 71
+  Special opcode .*: advance Address by 2 to 0x817a and Line by 1 to 72
+  Special opcode .*: advance Address by 2 to 0x817c and Line by 1 to 73
+  Special opcode .*: advance Address by 2 to 0x817e and Line by 1 to 74
+  Special opcode .*: advance Address by 2 to 0x8180 and Line by 1 to 75
+  Special opcode .*: advance Address by 2 to 0x8182 and Line by 1 to 76
+  Special opcode .*: advance Address by 2 to 0x8184 and Line by 1 to 77
+  Special opcode .*: advance Address by 2 to 0x8186 and Line by 1 to 78
+  Special opcode .*: advance Address by 2 to 0x8188 and Line by 1 to 79
+  Special opcode .*: advance Address by 2 to 0x818a and Line by 1 to 80
+  Special opcode .*: advance Address by 2 to 0x818c and Line by 1 to 81
+  Special opcode .*: advance Address by 2 to 0x818e and Line by 1 to 82
+  Special opcode .*: advance Address by 2 to 0x8190 and Line by 1 to 83
+  Special opcode .*: advance Address by 2 to 0x8192 and Line by 1 to 84
+  Special opcode .*: advance Address by 2 to 0x8194 and Line by 1 to 85
+  Special opcode .*: advance Address by 2 to 0x8196 and Line by 1 to 86
+  Special opcode .*: advance Address by 2 to 0x8198 and Line by 1 to 87
+  Special opcode .*: advance Address by 2 to 0x819a and Line by 1 to 88
+  Special opcode .*: advance Address by 2 to 0x819c and Line by 1 to 89
+  Special opcode .*: advance Address by 2 to 0x819e and Line by 1 to 90
+  Special opcode .*: advance Address by 2 to 0x81a0 and Line by 1 to 91
+  Special opcode .*: advance Address by 2 to 0x81a2 and Line by 1 to 92
+  Special opcode .*: advance Address by 2 to 0x81a4 and Line by 1 to 93
+  Special opcode .*: advance Address by 2 to 0x81a6 and Line by 1 to 94
+  Special opcode .*: advance Address by 2 to 0x81a8 and Line by 1 to 95
+  Special opcode .*: advance Address by 2 to 0x81aa and Line by 1 to 96
+  Special opcode .*: advance Address by 2 to 0x81ac and Line by 1 to 97
+  Special opcode .*: advance Address by 2 to 0x81ae and Line by 1 to 98
+  Special opcode .*: advance Address by 2 to 0x81b0 and Line by 1 to 99
+  Special opcode .*: advance Address by 2 to 0x81b2 and Line by 1 to 100
+  Special opcode .*: advance Address by 2 to 0x81b4 and Line by 1 to 101
+  Special opcode .*: advance Address by 2 to 0x81b6 and Line by 1 to 102
+  Special opcode .*: advance Address by 2 to 0x81b8 and Line by 1 to 103
+  Special opcode .*: advance Address by 2 to 0x81ba and Line by 1 to 104
+  Special opcode .*: advance Address by 2 to 0x81bc and Line by 1 to 105
+  Special opcode .*: advance Address by 2 to 0x81be and Line by 1 to 106
+  Special opcode .*: advance Address by 2 to 0x81c0 and Line by 1 to 107
+  Special opcode .*: advance Address by 2 to 0x81c2 and Line by 1 to 108
+  Special opcode .*: advance Address by 2 to 0x81c4 and Line by 1 to 109
+  Special opcode .*: advance Address by 2 to 0x81c6 and Line by 1 to 110
+  Special opcode .*: advance Address by 2 to 0x81c8 and Line by 1 to 111
+  Special opcode .*: advance Address by 2 to 0x81ca and Line by 1 to 112
+  Advance PC by 2 to 0x81cc
   Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/cris/rd-fragtest-pic.d b/gas/testsuite/gas/cris/rd-fragtest-pic.d
new file mode 100644
index 000000000000..0e4c2f16a392
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-fragtest-pic.d
@@ -0,0 +1,66 @@
+#objdump: -dr
+#as: --pic
+#source: fragtest.s
+
+.*:     file format .*-cris
+Disassembly of section \.text:
+0+ <l1-(0x)?100>:
+[	 ]+0:[	 ]+fee0[ 	]+ba[ ]+(0x[0]?100|100 <l1>)
+[ 	]+2:[		]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+80:[	 ]+e2e0[ 	]+ba[ ]+(0x[0]?164|164 <l2>)
+^[ 	]+82:[		]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+0+100 <l1>:
+^[ 	]+\.\.\.
+0+164 <l2>:
+[	 ]+164:[	 ]+ffed 0001[ 	]+ba (0x[0]?268|268 <l3>)
+[ 	]+168:[		]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+1e6:[	 ]+ffed 6604[ 	]+ba (0x[0]?650|650 <l4>)
+[ 	]+1ea:[		]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+0+268 <l3>:
+^[ 	]+\.\.\.
+0+650 <l4>:
+[	 ]+650:[	 ]+ffed 0a01[ 	]+ba (0x[0]?75e|75e <l5>)
+[ 	]+654:[	]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+6d2:[	 ]+0ae0[ 	]+ba[ ]+(0x[0]?6de|[0]?6de <l4\+0x8e>)
+[	 ]+6d4:[	 ]+0f05[ 	]+nop[ ]*
+[	 ]+6d6:[	 ]+6ffd 6a81 0000 3f0e[ 	]+move \[\$?pc=\$?pc\+816a <l5\+0x7a0c>\],\$?p0
+[	 ]+6de:[	 ]+f7e0[ 	]+ba[ ]+(0x[0]?6d6|6d6 <l4\+0x86>)
+[ 	]+6e0:[		]+0f05[	 ]+nop[ ]*
+^[ 	]+\.\.\.
+0+75e <l5>:
+^[ 	]+\.\.\.
+0+8846 <l6>:
+^[ 	]+\.\.\.
+[	 ]+88c2:[	 ]+fee0[ 	]+ba[ ]+(0x89c2|89c2 <l8>)
+[	 ]+88c4:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+8942:[	 ]+0000[ 	]+bcc[ ]+.*
+[	 ]+8944:[	 ]+01e0[ 	]+ba[ ]+(0x8846|8846 <l6>)
+[	 ]+8946:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+89c2 <l8>:
+^[ 	]+\.\.\.
+[	 ]+8a3e:[	 ]+ffed 0201[ 	]+ba (0x8b44|8b44 <l10>)
+[	 ]+8a42:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+8ac0:[	 ]+0000[ 	]+bcc[ ]+.*
+[	 ]+8ac2:[	 ]+ffed fcfe[ 	]+ba (0x89c2|89c2 <l8>)
+[	 ]+8ac6:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+8b44 <l10>:
+^[ 	]+\.\.\.
+[	 ]+8bc0:[	 ]+0000[ 	]+bcc[ ]+.*
+[	 ]+8bc2:[	 ]+ffed 0001[ 	]+ba (0x8cc6|8cc6 <l12>)
+[	 ]+8bc6:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+[	 ]+8c44:[	 ]+0000[ 	]+bcc[ ]+.*
+[	 ]+8c46:[	 ]+ffed fafe[ 	]+ba (0x8b44|8b44 <l10>)
+[	 ]+8c4a:[	 ]+0f05[ 	]+nop[ ]*
+^[ 	]+\.\.\.
+0+8cc6 <l12>:
+^[ 	]+\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-pcplus.d b/gas/testsuite/gas/cris/rd-pcplus.d
new file mode 100644
index 000000000000..7cbd2aed1971
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-pcplus.d
@@ -0,0 +1,16 @@
+#as: --em=criself --march=v10 --underscore
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+[ 	]+0:[ 	]+4715 3fbe[ 	]+move \[pc=r7\+r1\.b\],srp
+[ 	]+4:[ 	]+6ffd 0000 0100 3f0e[ 	]+move \[pc=pc\+10000 <a\+0x10000>\],p0
+[ 	]+c:[ 	]+4385 6f5e[ 	]+move\.d \[pc=r3\+r8\.b\],r5
+[ 	]+10:[ 	]+6ffd 0000 0100 6fbe[ 	]+move\.d \[pc=pc\+10000 <a\+0x10000>\],r11
+[ 	]+18:[ 	]+6f5d 0000 0a00 3f1e[ 	]+move \[pc=r5\+a0000 <a\+0xa0000>\],vr
+[ 	]+20:[ 	]+5f7d 8f02 6fde[ 	]+move\.d \[pc=r7\+655\],r13
+[ 	]+26:[ 	]+4161 6fae[ 	]+move\.d \[pc=r6\+65\],r10
+[ 	]+2a:[ 	]+0f05[ 	]+nop 
diff --git a/gas/testsuite/gas/cris/rd-pcplus.s b/gas/testsuite/gas/cris/rd-pcplus.s
new file mode 100644
index 000000000000..b4a266128859
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-pcplus.s
@@ -0,0 +1,10 @@
+ .text
+a:
+ move [$pc=$r7+$r1.b],$srp
+ move [$pc=$pc+65536],$p0
+ move.d [$pc=$r3+$r8.b],$r5
+ move.d [$pc=$pc+65536],$r11
+ move [$pc=$r5+655360],$p1
+ move.d [$pc=$r7+655],$r13
+ move.d [$pc=$r6+65],$r10
+ nop
diff --git a/gas/testsuite/gas/cris/rd-pcrel2.d b/gas/testsuite/gas/cris/rd-pcrel2.d
index 8dac5ca4b011..2b401e7a0f12 100644
--- a/gas/testsuite/gas/cris/rd-pcrel2.d
+++ b/gas/testsuite/gas/cris/rd-pcrel2.d
@@ -1,4 +1,5 @@
 #objdump: -dr
+#as: --em=criself
 
 .*:     file format .*-cris
 
diff --git a/gas/testsuite/gas/cris/rd-pic-2.d b/gas/testsuite/gas/cris/rd-pic-2.d
new file mode 100644
index 000000000000..ce75451cd116
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-pic-2.d
@@ -0,0 +1,19 @@
+#objdump: -dr
+#as: --underscore --em=criself --pic
+
+# Check that 16-bit PIC relocs aren't overflowing.
+# PR gas/1049.
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+0+ <a>:
+       0:	7f9c 0000           	movs\.w 0,r9
+			2: R_CRIS_16_GOT	y
+       4:	7f9c 0000           	movs\.w 0,r9
+			6: R_CRIS_16_GOTPLT	z
+	\.\.\.
+0+10008 <y>:
+   10008:	0f05                	nop 
+0+1000a <z>:
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-pic-2.s b/gas/testsuite/gas/cris/rd-pic-2.s
new file mode 100644
index 000000000000..949fa18b0c30
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-pic-2.s
@@ -0,0 +1,11 @@
+; GAS mustn't error on the larger-than-16-bit offsets here.
+
+	.global y
+	.global z
+a:
+	movs.w y:GOT16,$r9
+	movs.w z:GOTPLT16,$r9
+	.space 65536,0
+y:
+	nop
+z:
diff --git a/gas/testsuite/gas/cris/rd-ppv1032.d b/gas/testsuite/gas/cris/rd-ppv1032.d
new file mode 100644
index 000000000000..4f64ce1938f7
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-ppv1032.d
@@ -0,0 +1,14 @@
+#source: pushpopv32.s
+#as: --underscore --march=common_v10_v32 --em=criself
+#objdump: -dr
+
+.*:[ 	]+file format .*-cris
+
+Disassembly of section \.text:
+0+ <start>:
+[ 	]+0:[ 	]+84e2[ 	]+subq 4,sp
+[ 	]+2:[ 	]+eeab[ 	]+move\.d r10,\[sp\]
+[ 	]+4:[ 	]+84e2[ 	]+subq 4,sp
+[ 	]+6:[ 	]+7eba[ 	]+move srp,\[sp\]
+[ 	]+8:[ 	]+6eae[ 	]+move\.d \[sp\+\],r10
+[ 	]+a:[ 	]+3ebe[ 	]+move \[sp\+\],srp
diff --git a/gas/testsuite/gas/cris/rd-ppv32.d b/gas/testsuite/gas/cris/rd-ppv32.d
new file mode 100644
index 000000000000..52355ffe228f
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-ppv32.d
@@ -0,0 +1,14 @@
+#source: pushpopv32.s
+#as: --underscore --march=v32 --em=criself
+#objdump: -dr
+
+.*:[ 	]+file format .*-cris
+
+Disassembly of section \.text:
+0+ <start>:
+[ 	]+0:[ 	]+84e2[ 	]+subq 4,sp
+[ 	]+2:[ 	]+eeab[ 	]+move\.d r10,\[sp\]
+[ 	]+4:[ 	]+84e2[ 	]+subq 4,sp
+[ 	]+6:[ 	]+7eba[ 	]+move srp,\[sp\]
+[ 	]+8:[ 	]+6eae[ 	]+move\.d \[sp\+\],r10
+[ 	]+a:[ 	]+3ebe[ 	]+move \[sp\+\],srp
diff --git a/gas/testsuite/gas/cris/rd-spr-1.d b/gas/testsuite/gas/cris/rd-spr-1.d
new file mode 100644
index 000000000000..a7f28c70f568
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-spr-1.d
@@ -0,0 +1,42 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Check support for support function register names.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+   0:	7a0f                	move s0,r10
+   2:	791f                	move s1,r9
+   4:	781f                	move s1,r8
+   6:	772f                	move s2,r7
+   8:	762f                	move s2,r6
+   a:	753f                	move s3,r5
+   c:	743f                	move s3,r4
+   e:	734f                	move s4,r3
+  10:	724f                	move s4,r2
+  12:	718f                	move s8,r1
+  14:	709f                	move s9,r0
+  16:	7f8f                	move s8,acr
+  18:	7e9f                	move s9,sp
+  1a:	7daf                	move s10,r13
+  1c:	7bff                	move s15,r11
+
+0000001e <b>:
+  1e:	790b                	move r9,s0
+  20:	7a1b                	move r10,s1
+  22:	771b                	move r7,s1
+  24:	782b                	move r8,s2
+  26:	752b                	move r5,s2
+  28:	763b                	move r6,s3
+  2a:	733b                	move r3,s3
+  2c:	744b                	move r4,s4
+  2e:	714b                	move r1,s4
+  30:	708b                	move r0,s8
+  32:	7f9b                	move acr,s9
+  34:	728b                	move r2,s8
+  36:	7d9b                	move r13,s9
+  38:	7bab                	move r11,s10
+  3a:	7efb                	move sp,s15
diff --git a/gas/testsuite/gas/cris/rd-spr-1.s b/gas/testsuite/gas/cris/rd-spr-1.s
new file mode 100644
index 000000000000..3758d39f902b
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-spr-1.s
@@ -0,0 +1,32 @@
+a:
+ move s0,r10
+ move s1,r9
+ move s1,r8
+ move s2,r7
+ move s2,r6
+ move s3,r5
+ move s3,r4
+ move s4,r3
+ move s4,r2
+ move s8,r1
+ move s9,r0
+ move s8,r15
+ move s9,r14
+ move s10,r13
+ move s15,r11
+b:
+ move r9,s0
+ move r10,s1
+ move r7,s1
+ move r8,s2
+ move r5,s2
+ move r6,s3
+ move r3,s3
+ move r4,s4
+ move r1,s4
+ move r0,s8
+ move r15,s9
+ move r2,s8
+ move r13,s9
+ move r11,s10
+ move r14,s15
diff --git a/gas/testsuite/gas/cris/rd-usp-1.d b/gas/testsuite/gas/cris/rd-usp-1.d
new file mode 100644
index 000000000000..7e1a5db58805
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-usp-1.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+#as: --underscore --march=v10
+#source: v32-err-8.s
+
+# Check that USP gets the right number for V10.
+
+.*:     file format .*-cris
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+   0:	3af6                	move r10,usp
+   2:	3ffe b0ab 0f00      	move (0xfabb0|fabb0 <.*>),usp
+   8:	75fa                	move usp,\[r5\]
+   a:	3cfa                	move \[r12\],usp
diff --git a/gas/testsuite/gas/cris/rd-usp-1b.d b/gas/testsuite/gas/cris/rd-usp-1b.d
new file mode 100644
index 000000000000..40a92fe05412
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-usp-1b.d
@@ -0,0 +1,15 @@
+#objdump: -dr
+#as: --underscore --march=v32 --em=criself
+#source: v32-err-8.s
+
+# Check that USP gets the right number for V32.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	3ae6                	move r10,usp
+   2:	3fee b0ab 0f00      	move 0xfabb0,usp
+   8:	75ea                	move usp,\[r5\]
+   a:	3cea                	move \[r12\],usp
diff --git a/gas/testsuite/gas/cris/rd-v10_32o-1.d b/gas/testsuite/gas/cris/rd-v10_32o-1.d
new file mode 100644
index 000000000000..d9f43531a6b7
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v10_32o-1.d
@@ -0,0 +1,9 @@
+#source: break.s
+#as: --underscore --em=criself --march=common_v10_v32
+#objdump: -p
+
+# Check that different command-line options result in different
+# machine-type stamps on the object files.
+
+.*:     file format elf32-us-cris
+private flags = 5: \[symbols have a _ prefix\] \[v10 and v32\]
diff --git a/gas/testsuite/gas/cris/rd-v10_32o-2.d b/gas/testsuite/gas/cris/rd-v10_32o-2.d
new file mode 100644
index 000000000000..73c240f13b02
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v10_32o-2.d
@@ -0,0 +1,53 @@
+#as: --underscore --em=criself --march=common_v10_v32
+#objdump: -dr
+
+# Check that branch offsets are computed as for v32.  The
+# compiler is supposed to generate four nop-type insns after
+# every label to make sure the offset-by-2 or 4 doesn't matter.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+       0:	ffed ff7f           	ba .*
+       4:	0000                	bcc \.\+2
+	\.\.\.
+
+00007fff <b1>:
+    7fff:	ffed 0201           	ba .*
+    8003:	fee0                	ba .*
+    8005:	0000                	bcc \.\+2
+	\.\.\.
+
+00008101 <b2>:
+	\.\.\.
+    8201:	01e0                	ba .*
+    8203:	ffed fefe           	ba .*
+
+00008207 <b3>:
+	\.\.\.
+   10203:	ffed 0480           	ba .*
+
+00010207 <b4>:
+   10207:	b005                	setf 
+
+00010209 <aa>:
+   10209:	ff3d ff7f           	beq .*
+   1020d:	0000                	bcc \.\+2
+	\.\.\.
+
+00018208 <bb1>:
+   18208:	ff3d 0201           	beq .*
+   1820c:	fe30                	beq .*
+   1820e:	0000                	bcc \.\+2
+	\.\.\.
+
+0001830a <bb2>:
+	\.\.\.
+   1840a:	0130                	beq .*
+   1840c:	ff3d fefe           	beq .*
+
+00018410 <bb3>:
+	\.\.\.
+   2040c:	ff3d 0480           	beq .*
diff --git a/gas/testsuite/gas/cris/rd-v10_32o-2.s b/gas/testsuite/gas/cris/rd-v10_32o-2.s
new file mode 100644
index 000000000000..a912ae6efddc
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v10_32o-2.s
@@ -0,0 +1,31 @@
+a:
+ ba b1
+ .space 32767-4
+b1:
+ ba b2
+ ba b2
+ .space 127*2-2
+b2:
+ .space 128*2
+ ba b2
+ ba b2
+b3:
+ .space 32764
+ ba b3
+b4:
+ setf
+aa:
+ beq bb1
+ .space 32767-4
+bb1:
+ beq bb2
+ beq bb2
+ .space 127*2-2
+bb2:
+ .space 128*2
+ beq bb2
+ beq bb2
+bb3:
+ .space 32764
+ beq bb3
+bb4:
diff --git a/gas/testsuite/gas/cris/rd-v32-b1.d b/gas/testsuite/gas/cris/rd-v32-b1.d
new file mode 100644
index 000000000000..52823994de89
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b1.d
@@ -0,0 +1,31 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+       0:	bf0e 0580 0000      	ba 8005 <b1>
+       6:	ffed ff7f           	ba 8005 <b1>
+       a:	0000                	bcc \.
+	\.\.\.
+
+00008005 <b1>:
+    8005:	ffed 0201           	ba 8107 <b2>
+    8009:	fee0                	ba 8107 <b2>
+    800b:	0000                	bcc \.
+	\.\.\.
+
+00008107 <b2>:
+	\.\.\.
+    8207:	01e0                	ba 8107 <b2>
+    8209:	ffed fefe           	ba 8107 <b2>
+
+0000820d <b3>:
+	\.\.\.
+   1020d:	ffed 0080           	ba 820d <b3>
+   10211:	bf0e fc7f ffff      	ba 820d <b3>
+
+00010217 <b4>:
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-v32-b1.s b/gas/testsuite/gas/cris/rd-v32-b1.s
new file mode 100644
index 000000000000..e3a8ba82df86
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b1.s
@@ -0,0 +1,17 @@
+a:
+ ba b1
+ ba b1
+ .space 32767-4
+b1:
+ ba b2
+ ba b2
+ .space 127*2-2
+b2:
+ .space 128*2
+ ba b2
+ ba b2
+b3:
+ .space 32768
+ ba b3
+ ba b3
+b4:
diff --git a/gas/testsuite/gas/cris/rd-v32-b2.d b/gas/testsuite/gas/cris/rd-v32-b2.d
new file mode 100644
index 000000000000..9439b9e8591e
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b2.d
@@ -0,0 +1,39 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+       0:	0ce0                	ba c <a\+0xc>
+       2:	b005                	nop 
+       4:	bf0e 0980 0000      	ba 800d <b1>
+       a:	b005                	nop 
+       c:	f930                	beq 4 <a\+0x4>
+       e:	ff2d ff7f           	bne 800d <b1>
+      12:	0000                	bcc \.
+	\.\.\.
+
+0000800d <b1>:
+    800d:	ff0d 0201           	bhs 810f <b2>
+    8011:	fe90                	bhi 810f <b2>
+    8013:	0000                	bcc \.
+	\.\.\.
+
+0000810f <b2>:
+	\.\.\.
+    820f:	0110                	bcs 810f <b2>
+    8211:	ff1d fefe           	blo 810f <b2>
+
+00008215 <b3>:
+	\.\.\.
+   10215:	ff8d 0080           	bls 8215 <b3>
+   10219:	0ce0                	ba 10225 <b3\+0x8010>
+   1021b:	b005                	nop 
+   1021d:	bf0e f87f ffff      	ba 8215 <b3>
+   10223:	b005                	nop 
+   10225:	f9f0                	bsb 1021d <b3\+0x8008>
+
+00010227 <b4>:
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-v32-b2.s b/gas/testsuite/gas/cris/rd-v32-b2.s
new file mode 100644
index 000000000000..65b137ae6935
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b2.s
@@ -0,0 +1,20 @@
+a:
+ beq b1
+ bne b1
+ .space 32767-4
+b1:
+ bhs b2
+ bhi b2
+ .space 127*2-2
+b2:
+ .space 128*2
+ bcs b2
+ blo b2
+b3:
+ .space 32768
+ bls b3
+ bsb b3
+b4:
+
+
+  
\ No newline at end of file
diff --git a/gas/testsuite/gas/cris/rd-v32-b3.d b/gas/testsuite/gas/cris/rd-v32-b3.d
new file mode 100644
index 000000000000..fee75df97c64
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b3.d
@@ -0,0 +1,27 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Check expansion of "ba" into dword operands for different segment.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a-0x2>:
+   0:	7fa2                	moveq -1,r10
+
+00000002 <a>:
+   2:	bf0e 0000 0000      	ba 2 <a>
+			4: R_CRIS_32_PCREL	\.text\.2\+0x8
+   8:	4152                	moveq 1,r5
+	\.\.\.
+Disassembly of section \.text\.2:
+
+00000000 <b-0x2>:
+   0:	4822                	moveq 8,r2
+
+00000002 <b>:
+   2:	4232                	moveq 2,r3
+   4:	bf0e 0000 0000      	ba 4 <b\+0x2>
+			6: R_CRIS_32_PCREL	\.text\+0x8
+   a:	4472                	moveq 4,r7
diff --git a/gas/testsuite/gas/cris/rd-v32-b3.s b/gas/testsuite/gas/cris/rd-v32-b3.s
new file mode 100644
index 000000000000..14aa0b54f04a
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-b3.s
@@ -0,0 +1,11 @@
+ moveq -1,r10
+a:
+ ba b
+ moveq 1,r5
+
+ .section .text.2,"ax"
+ moveq 8,r2
+b:
+ moveq 2,r3
+ ba a
+ moveq 4,r7
diff --git a/gas/testsuite/gas/cris/rd-v32-f1.d b/gas/testsuite/gas/cris/rd-v32-f1.d
new file mode 100644
index 000000000000..d97c38e3b62c
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-f1.d
@@ -0,0 +1,26 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Test that v32 flags are properly recognized and emitted at disassembly.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <x>:
+   0:	b105                	setf c
+   2:	f105                	clearf c
+   4:	f205                	clearf v
+   6:	b205                	setf v
+   8:	b405                	setf z
+   a:	f405                	clearf z
+   c:	f805                	clearf n
+   e:	b805                	setf n
+  10:	b015                	ax 
+  12:	f015                	clearf x
+  14:	b025                	ei 
+  16:	f025                	di 
+  18:	f045                	clearf u
+  1a:	b045                	setf u
+  1c:	b085                	setf p
+  1e:	f085                	clearf p
diff --git a/gas/testsuite/gas/cris/rd-v32-f1.s b/gas/testsuite/gas/cris/rd-v32-f1.s
new file mode 100644
index 000000000000..dc5c6cf868de
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-f1.s
@@ -0,0 +1,18 @@
+; Test that v32 flags are properly recognized.
+x:
+ setf c
+ clearf C
+ clearf v
+ setf V
+ setf z
+ clearf Z
+ clearf n
+ setf N
+ setf x
+ clearf X
+ setf i
+ clearf I
+ clearf u
+ setf U
+ setf p
+ clearf P
diff --git a/gas/testsuite/gas/cris/rd-v32-i1.d b/gas/testsuite/gas/cris/rd-v32-i1.d
new file mode 100644
index 000000000000..def1e49900f8
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-i1.d
@@ -0,0 +1,19 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Test that addc recognizes constant operands.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <x>:
+   0:	afad ffff ffff      	addc 0xffffffff,r10
+   6:	affd 4000 0000      	addc 40 <x\+0x40>,acr
+   c:	af5d 0100 0000      	addc 1 <x\+0x1>,r5
+  12:	af7d 0000 0000      	addc 0 <x>,r7
+			14: R_CRIS_32	extsym\+0x140
+  18:	af0d 0000 0000      	addc 0 <x>,r0
+  1e:	af4d e782 3101      	addc 13182e7 <x\+0x13182e7>,r4
+  24:	affd 0f00 0000      	addc f <x\+0xf>,acr
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-v32-i1.s b/gas/testsuite/gas/cris/rd-v32-i1.s
new file mode 100644
index 000000000000..008393b46716
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-i1.s
@@ -0,0 +1,10 @@
+; Test that addc recognizes constant operands; [pc+]
+x:
+ addc -1,r10
+ addc 0x40,acr
+ addc 1,r5
+ addc extsym+320,r7
+ addc 0,r0
+ addc [pc+],r4
+ .dword 20021991
+ addc 15,acr
diff --git a/gas/testsuite/gas/cris/rd-v32-l1.d b/gas/testsuite/gas/cris/rd-v32-l1.d
new file mode 100644
index 000000000000..231f0e7ac5e3
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l1.d
@@ -0,0 +1,14 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <a>:
+   0:	7f5d 0000 0000      	lapc 0 <a>,r5
+			2: R_CRIS_32_PCREL	\*ABS\*\+0x7
+   6:	7f6d faff ffff      	lapc 0 <a>,r6
+   c:	7f7d 0000 0000      	lapc c <a\+0xc>,r7
+			e: R_CRIS_32_PCREL	\*ABS\*\+0xa
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-v32-l1.s b/gas/testsuite/gas/cris/rd-v32-l1.s
new file mode 100644
index 000000000000..db3a325860e5
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l1.s
@@ -0,0 +1,4 @@
+a:
+ lapc 1,r5
+ lapc.d a,r6
+ lapc.d 4,r7
diff --git a/gas/testsuite/gas/cris/rd-v32-l3.d b/gas/testsuite/gas/cris/rd-v32-l3.d
new file mode 100644
index 000000000000..59a8174419b4
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l3.d
@@ -0,0 +1,14 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <x>:
+   0:	7259                	lapcq 4 <y>,r5
+   2:	b005                	nop 
+
+0+4 <y>:
+   4:	bfbe fcff ffff      	bsr 0 <x>
+   a:	b005                	nop 
diff --git a/gas/testsuite/gas/cris/rd-v32-l3.s b/gas/testsuite/gas/cris/rd-v32-l3.s
new file mode 100644
index 000000000000..e96a85c04804
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l3.s
@@ -0,0 +1,7 @@
+ .arch v32
+x:
+ lapcq y,r5
+ nop
+y:
+ bsr x
+ nop
diff --git a/gas/testsuite/gas/cris/rd-v32-l4.d b/gas/testsuite/gas/cris/rd-v32-l4.d
new file mode 100644
index 000000000000..4afd3fb9a93a
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l4.d
@@ -0,0 +1,61 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Test that lapc shrinks to lapcq and that offsets are emitted correctly.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <a>:
+   0:	70a9                	lapcq 0 <a>,r10
+   2:	71b9                	lapcq 4 <x>,r11
+
+0+4 <x>:
+   4:	72c9                	lapcq 8 <xx>,r12
+   6:	b005                	nop 
+
+0+8 <xx>:
+   8:	73d9                	lapcq e <xxx>,r13
+   a:	b005                	nop 
+   c:	b005                	nop 
+
+0+e <xxx>:
+   e:	b005                	nop 
+
+0+10 <a00>:
+  10:	b005                	nop 
+  12:	7f9d feff ffff      	lapc 10 <a00>,r9
+
+0+18 <a0>:
+  18:	7089                	lapcq 18 <a0>,r8
+  1a:	7179                	lapcq 1c <x0>,r7
+
+0+1c <x0>:
+  1c:	7269                	lapcq 20 <xx0>,r6
+  1e:	b005                	nop 
+
+0+20 <xx0>:
+  20:	b005                	nop 
+
+0+22 <a11>:
+  22:	b005                	nop 
+  24:	7fad feff ffff      	lapc 22 <a11>,r10
+
+0+2a <a1>:
+  2a:	7fad 0000 0000      	lapc 2a <a1>,r10
+  30:	7fbd 0600 0000      	lapc 36 <x1>,r11
+
+0+36 <x1>:
+  36:	7fcd 0800 0000      	lapc 3e <xx1>,r12
+  3c:	b005                	nop 
+
+0+3e <xx1>:
+  3e:	7fdd 0a00 0000      	lapc 48 <xxx1>,r13
+  44:	b005                	nop 
+  46:	b005                	nop 
+
+0+48 <xxx1>:
+  48:	b005                	nop 
+  4a:	7f39                	lapcq 68 <y>,r3
+	\.\.\.
diff --git a/gas/testsuite/gas/cris/rd-v32-l4.s b/gas/testsuite/gas/cris/rd-v32-l4.s
new file mode 100644
index 000000000000..beab427a5772
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32-l4.s
@@ -0,0 +1,42 @@
+a:
+ lapcq a,$r10
+ lapcq x,$r11
+x:
+ lapcq xx,$r12
+ nop
+xx:
+ lapcq xxx,$r13
+ nop
+ nop
+xxx:
+ nop
+a00:
+ nop
+ lapc a00,$r9
+a0:
+ lapc a0,$r8
+ lapc x0,$r7
+x0:
+ lapc xx0,$r6
+ nop
+xx0:
+ nop
+a11:
+ nop
+ lapc.d a11,$r10
+a1:
+ lapc.d a1,$r10
+ lapc.d x1,$r11
+x1:
+ lapc.d xx1,$r12
+ nop
+xx1:
+ lapc.d xxx1,$r13
+ nop
+ nop
+xxx1:
+ nop
+ lapc y,$r3
+ .space 28,0
+y:
+
diff --git a/gas/testsuite/gas/cris/rd-v32o-1.d b/gas/testsuite/gas/cris/rd-v32o-1.d
new file mode 100644
index 000000000000..24bfcda11700
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32o-1.d
@@ -0,0 +1,9 @@
+#source: abs32-1.s
+#as: --underscore --em=criself --march=v32
+#objdump: -p
+
+# Check that different command-line options result in different
+# machine-type stamps on the object files.
+
+.*:     file format elf32-us-cris
+private flags = 3: \[symbols have a _ prefix\] \[v32\]
diff --git a/gas/testsuite/gas/cris/rd-v32s-1.d b/gas/testsuite/gas/cris/rd-v32s-1.d
new file mode 100644
index 000000000000..b4f85be8c4d5
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-1.d
@@ -0,0 +1,148 @@
+#source: v32-err-1.s
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+# Check that v32 insns that are expected to give syntax errors
+# for non-v32 are recognized and resulting in correct code and
+# disassembly.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+00000000 <here>:
+   0:	6f3a                	move\.d \[acr\],r3
+   2:	65fe                	move\.d \[r5\+\],acr
+   4:	6f76                	move\.d acr,r7
+   6:	68f6                	move\.d r8,acr
+   8:	3fb6                	move acr,srp
+   a:	7005                	addc r0,r0
+   c:	7ff5                	addc acr,acr
+   e:	7615                	addc r6,r1
+  10:	a319                	addc \[r3\],r1
+  12:	a009                	addc \[r0\],r0
+  14:	aff9                	addc \[acr\],acr
+  16:	af19                	addc \[acr\],r1
+  18:	a31d                	addc \[r3\+\],r1
+  1a:	5285                	addi r8\.w,r2,acr
+  1c:	4005                	addi r0\.b,r0,acr
+  1e:	6ff5                	addi acr\.d,acr,acr
+  20:	6379                	addo\.d \[r3\],r7,acr
+  22:	6d7d                	addo\.d \[r13\+\],r7,acr
+  24:	63f9                	addo\.d \[r3\],acr,acr
+  26:	4009                	addo\.b \[r0\],r0,acr
+  28:	6ff9                	addo\.d \[acr\],acr,acr
+  2a:	4ffd ffff           	addo\.b 0xffff,acr,acr
+  2e:	5ffd ffff           	addo\.w 0xffff,acr,acr
+  32:	6ffd ffff ffff      	addo\.d 0xffffffff,acr,acr
+  38:	4f3d 0000           	addo\.b 0x0,r3,acr
+			3a: R_CRIS_16	extsym1
+  3c:	5f3d 0000           	addo\.w 0x0,r3,acr
+			3e: R_CRIS_16	extsym2
+  40:	6f3d 0000 0000      	addo\.d 0 <here>,r3,acr
+			42: R_CRIS_32	extsym3
+  46:	4ffd 7f00           	addo\.b 0x7f,acr,acr
+  4a:	5ffd ff7f           	addo\.w 0x7fff,acr,acr
+  4e:	6ffd ffff ff00      	addo\.d ffffff <here\+0xffffff>,acr,acr
+  54:	4ffd 80ff           	addo\.b 0xff80,acr,acr
+  58:	5ffd 0080           	addo\.w 0x8000,acr,acr
+  5c:	6ffd ffff ffff      	addo\.d 0xffffffff,acr,acr
+  62:	7009                	lapcq 62 <here\+0x62>,r0
+  64:	7f49                	lapcq 82 <here\+0x82>,r4
+  66:	7ff9                	lapcq 84 <here\+0x84>,acr
+  68:	7ffd 0000 0000      	lapc 68 <here\+0x68>,acr
+			6a: R_CRIS_32_PCREL	extsym4\+0x6
+  6e:	7f4d 0000 0000      	lapc 6e <here\+0x6e>,r4
+			70: R_CRIS_32_PCREL	extsym5\+0x6
+  74:	7f4d 8cff ffff      	lapc 0 <here>,r4
+  7a:	fff1                	addoq -1,acr,acr
+  7c:	0001                	addoq 0,r0,acr
+  7e:	7f41                	addoq 127,r4,acr
+  80:	0041                	addoq 0,r4,acr
+			80: R_CRIS_8	extsym6
+  82:	bfbe 0000 0000      	bsr 82 <here\+0x82>
+			84: R_CRIS_32_PCREL	\*ABS\*\+0x5
+  88:	bf0e 0000 0000      	ba 88 <here\+0x88>
+			8a: R_CRIS_32_PCREL	extsym7\+0x6
+  8e:	bfae 72ff ffff      	bas 0 <here>,erp
+  94:	ffbe 0000 0000      	bsrc 94 <here\+0x94>
+			96: R_CRIS_32_PCREL	\*ABS\*\+0x5
+  9a:	0000                	bcc \.
+  9c:	0000                	bcc \.
+  9e:	ff0e 0000 0000      	basc 9e <here\+0x9e>,bz
+			a0: R_CRIS_32_PCREL	extsym8\+0x6
+  a4:	0000                	bcc \.
+  a6:	0000                	bcc \.
+  a8:	ffae 58ff ffff      	basc 0 <here>,erp
+  ae:	0000                	bcc \.
+  b0:	0000                	bcc \.
+  b2:	00f0                	bsb b2 <here\+0xb2>
+  b4:	b005                	nop 
+  b6:	4bf0                	bsb 0 <here>
+  b8:	b005                	nop 
+  ba:	bfbe 0000 0000      	bsr ba <here\+0xba>
+			bc: R_CRIS_32_PCREL	extsym9\+0x6
+  c0:	bfbe 40ff ffff      	bsr 0 <here>
+  c6:	ffbe 0000 0000      	bsrc c6 <here\+0xc6>
+			c8: R_CRIS_32_PCREL	\*ABS\*\+0x5
+  cc:	0000                	bcc \.
+  ce:	0000                	bcc \.
+  d0:	ffbe 0000 0000      	bsrc d0 <here\+0xd0>
+			d2: R_CRIS_32_PCREL	extsym10\+0x6
+  d6:	0000                	bcc \.
+  d8:	0000                	bcc \.
+  da:	ffbe 26ff ffff      	bsrc 0 <here>
+  e0:	0000                	bcc \.
+  e2:	0000                	bcc \.
+  e4:	b00a                	fidxd \[r0\]
+  e6:	bf0a                	fidxd \[acr\]
+  e8:	300d                	fidxi \[r0\]
+  ea:	3f0d                	fidxi \[acr\]
+  ec:	b01a                	ftagd \[r0\]
+  ee:	bf1a                	ftagd \[acr\]
+  f0:	301d                	ftagi \[r0\]
+  f2:	3f1d                	ftagi \[acr\]
+  f4:	b009                	jump r0
+  f6:	bfe9                	jas acr,usp
+  f8:	bf0d 0000 0000      	jump 0 <here>
+			fa: R_CRIS_32	extsym9
+  fe:	bfbd 0000 0000      	jsr 0 <here>
+			100: R_CRIS_32	\.text
+ 104:	300b                	jasc r0,bz
+ 106:	0000                	bcc \.
+ 108:	0000                	bcc \.
+ 10a:	3feb                	jasc acr,usp
+ 10c:	0000                	bcc \.
+ 10e:	0000                	bcc \.
+ 110:	3fbf ffff ffff      	jsrc ffffffff <here\+0xffffffff>
+ 116:	0000                	bcc \.
+ 118:	0000                	bcc \.
+ 11a:	3f0f 0000 0000      	jasc 0 <here>,bz
+			11c: R_CRIS_32	extsym11
+ 120:	0000                	bcc \.
+ 122:	0000                	bcc \.
+ 124:	3faf 0000 0000      	jasc 0 <here>,erp
+			126: R_CRIS_32	\.text
+ 12a:	0000                	bcc \.
+ 12c:	0000                	bcc \.
+ 12e:	f0b9                	ret 
+ 130:	f009                	jump bz
+ 132:	f007                	mcp bz,r0
+ 134:	ff77                	mcp mof,acr
+ 136:	f2b7                	mcp srp,r2
+ 138:	700f                	move s0,r0
+ 13a:	7fff                	move s15,acr
+ 13c:	735f                	move s5,r3
+ 13e:	700b                	move r0,s0
+ 140:	7ffb                	move acr,s15
+ 142:	74ab                	move r4,s10
+ 144:	3029                	rfe 
+ 146:	3049                	rfg 
+ 148:	f0a9                	rete 
+ 14a:	f0c9                	retn 
+ 14c:	30f5                	ssb r0
+ 14e:	3ff5                	ssb acr
+ 150:	3af5                	ssb r10
+ 152:	3039                	sfe 
+ 154:	30f9                	halt 
+ 156:	3059                	rfn 
diff --git a/gas/testsuite/gas/cris/rd-v32s-2.d b/gas/testsuite/gas/cris/rd-v32s-2.d
new file mode 100644
index 000000000000..446cadc29155
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-2.d
@@ -0,0 +1,16 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <here>:
+[ 	]+0:[ 	]+3f1e fafc fdfe[ 	]+move fefdfcfa <here\+0xfefdfcfa>,vr
+[ 	]+6:[ 	]+3f2e 11ba 0ff0[ 	]+move f00fba11 <here\+0xf00fba11>,pid
+[ 	]+c:[ 	]+3f3e 0000 0000[ 	]+move 0 <here>,srs
+[ 	]+e:[ 	]+R_CRIS_32	extsym
+[ 	]+12:[ 	]+3f4e 0000 0000[ 	]+move 0 <here>,wz
+[ 	]+14:[ 	]+R_CRIS_32	extsym2
+[ 	]+18:[ 	]+3f5e e903 0000[ 	]+move 3e9 <here\+0x3e9>,exs
+[ 	]+1e:[ 	]+3f6e 6500 0000[ 	]+move 65 <here\+0x65>,eda
diff --git a/gas/testsuite/gas/cris/rd-v32s-2.s b/gas/testsuite/gas/cris/rd-v32s-2.s
new file mode 100644
index 000000000000..8aee3a9b3cf3
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-2.s
@@ -0,0 +1,11 @@
+; Check that byte- and word-size special registers on CRISv32
+; take 32-bit immediate operands, as opposed to pre-v32 CRIS.
+
+ .text
+here:
+ move 0xfefdfcfa,$vr
+ move 0xf00fba11,$pid
+ move extsym,$srs
+ move extsym2,$wz
+ move 1001,$exs
+ move 101,$eda
diff --git a/gas/testsuite/gas/cris/rd-v32s-3.d b/gas/testsuite/gas/cris/rd-v32s-3.d
new file mode 100644
index 000000000000..27d75aa6dc54
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-3.d
@@ -0,0 +1,14 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <here>:
+[ 	]+0:[ 	]+3316[ 	]+move r3,vr
+[ 	]+2:[ 	]+3526[ 	]+move r5,pid
+[ 	]+4:[ 	]+3636[ 	]+move r6,srs
+[ 	]+6:[ 	]+3746[ 	]+move r7,wz
+[ 	]+8:[ 	]+3856[ 	]+move r8,exs
+[ 	]+a:[ 	]+3966[ 	]+move r9,eda
diff --git a/gas/testsuite/gas/cris/rd-v32s-3.s b/gas/testsuite/gas/cris/rd-v32s-3.s
new file mode 100644
index 000000000000..cd6022ad8048
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-3.s
@@ -0,0 +1,10 @@
+; Check correct disassembly of special registers.
+
+ .text
+here:
+ move $r3,$vr
+ move $r5,$pid
+ move $r6,$srs
+ move $r7,$wz
+ move $r8,$exs
+ move $r9,$eda
diff --git a/gas/testsuite/gas/cris/rd-v32s-4.d b/gas/testsuite/gas/cris/rd-v32s-4.d
new file mode 100644
index 000000000000..516dcc8a1c52
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-4.d
@@ -0,0 +1,88 @@
+#as: --underscore --em=criself --march=v32
+#objdump: -dr
+
+.*:     file format elf32-us-cris
+
+Disassembly of section .text:
+
+0+ <here>:
+[ 	]+0:[ 	]+3306[ 	]+move r3,bz
+[ 	]+2:[ 	]+3516[ 	]+move r5,vr
+[ 	]+4:[ 	]+3626[ 	]+move r6,pid
+[ 	]+6:[ 	]+3736[ 	]+move r7,srs
+[ 	]+8:[ 	]+3846[ 	]+move r8,wz
+[ 	]+a:[ 	]+3956[ 	]+move r9,exs
+[ 	]+c:[ 	]+3566[ 	]+move r5,eda
+[ 	]+e:[ 	]+3676[ 	]+move r6,mof
+[ 	]+10:[ 	]+3786[ 	]+move r7,dz
+[ 	]+12:[ 	]+3296[ 	]+move r2,ebp
+[ 	]+14:[ 	]+34a6[ 	]+move r4,erp
+[ 	]+16:[ 	]+30b6[ 	]+move r0,srp
+[ 	]+18:[ 	]+36c6[ 	]+move r6,nrp
+[ 	]+1a:[ 	]+3ad6[ 	]+move r10,ccs
+[ 	]+1c:[ 	]+3ce6[ 	]+move r12,usp
+[ 	]+1e:[ 	]+3df6[ 	]+move r13,spc
+[ 	]+20:[ 	]+7306[ 	]+clear\.b r3
+[ 	]+22:[ 	]+7516[ 	]+move vr,r5
+[ 	]+24:[ 	]+7626[ 	]+move pid,r6
+[ 	]+26:[ 	]+7736[ 	]+move srs,r7
+[ 	]+28:[ 	]+7846[ 	]+clear\.w r8
+[ 	]+2a:[ 	]+7956[ 	]+move exs,r9
+[ 	]+2c:[ 	]+7566[ 	]+move eda,r5
+[ 	]+2e:[ 	]+7676[ 	]+move mof,r6
+[ 	]+30:[ 	]+7786[ 	]+clear\.d r7
+[ 	]+32:[ 	]+7296[ 	]+move ebp,r2
+[ 	]+34:[ 	]+74a6[ 	]+move erp,r4
+[ 	]+36:[ 	]+70b6[ 	]+move srp,r0
+[ 	]+38:[ 	]+76c6[ 	]+move nrp,r6
+[ 	]+3a:[ 	]+7ad6[ 	]+move ccs,r10
+[ 	]+3c:[ 	]+7ce6[ 	]+move usp,r12
+[ 	]+3e:[ 	]+7df6[ 	]+move spc,r13
+[ 	]+40:[ 	]+3f0e 0300 0000[ 	]+move 3 <here\+0x3>,bz
+[ 	]+46:[ 	]+3f1e 0500 0000[ 	]+move 5 <here\+0x5>,vr
+[ 	]+4c:[ 	]+3f2e 0600 0000[ 	]+move 6 <here\+0x6>,pid
+[ 	]+52:[ 	]+3f3e 0700 0000[ 	]+move 7 <here\+0x7>,srs
+[ 	]+58:[ 	]+3f4e 0800 0000[ 	]+move 8 <here\+0x8>,wz
+[ 	]+5e:[ 	]+3f5e 0900 0000[ 	]+move 9 <here\+0x9>,exs
+[ 	]+64:[ 	]+3f6e 0a00 0000[ 	]+move a <here\+0xa>,eda
+[ 	]+6a:[ 	]+3f7e 6500 0000[ 	]+move 65 <here\+0x65>,mof
+[ 	]+70:[ 	]+3f8e 7800 0000[ 	]+move 78 <here\+0x78>,dz
+[ 	]+76:[ 	]+3f9e 0d00 0000[ 	]+move d <here\+0xd>,ebp
+[ 	]+7c:[ 	]+3fae 0400 0000[ 	]+move 4 <here\+0x4>,erp
+[ 	]+82:[ 	]+3fbe 0000 0000[ 	]+move 0 <here>,srp
+[ 	]+88:[ 	]+3fce 0600 0000[ 	]+move 6 <here\+0x6>,nrp
+[ 	]+8e:[ 	]+3fde 0a00 0000[ 	]+move a <here\+0xa>,ccs
+[ 	]+94:[ 	]+3fee 0c00 0000[ 	]+move c <here\+0xc>,usp
+[ 	]+9a:[ 	]+3ffe 0d00 0000[ 	]+move d <here\+0xd>,spc
+[ 	]+a0:[ 	]+730a[ 	]+clear\.b \[r3\]
+[ 	]+a2:[ 	]+751a[ 	]+move vr,\[r5\]
+[ 	]+a4:[ 	]+762a[ 	]+move pid,\[r6\]
+[ 	]+a6:[ 	]+773a[ 	]+move srs,\[r7\]
+[ 	]+a8:[ 	]+784a[ 	]+clear\.w \[r8\]
+[ 	]+aa:[ 	]+795a[ 	]+move exs,\[r9\]
+[ 	]+ac:[ 	]+756a[ 	]+move eda,\[r5\]
+[ 	]+ae:[ 	]+767a[ 	]+move mof,\[r6\]
+[ 	]+b0:[ 	]+778a[ 	]+clear\.d \[r7\]
+[ 	]+b2:[ 	]+729a[ 	]+move ebp,\[r2\]
+[ 	]+b4:[ 	]+74aa[ 	]+move erp,\[r4\]
+[ 	]+b6:[ 	]+70ba[ 	]+move srp,\[r0\]
+[ 	]+b8:[ 	]+76ca[ 	]+move nrp,\[r6\]
+[ 	]+ba:[ 	]+7ada[ 	]+move ccs,\[r10\]
+[ 	]+bc:[ 	]+7cea[ 	]+move usp,\[r12\]
+[ 	]+be:[ 	]+7dfa[ 	]+move spc,\[r13\]
+[ 	]+c0:[ 	]+330a[ 	]+move \[r3\],bz
+[ 	]+c2:[ 	]+351a[ 	]+move \[r5\],vr
+[ 	]+c4:[ 	]+362a[ 	]+move \[r6\],pid
+[ 	]+c6:[ 	]+373a[ 	]+move \[r7\],srs
+[ 	]+c8:[ 	]+384a[ 	]+move \[r8\],wz
+[ 	]+ca:[ 	]+395a[ 	]+move \[r9\],exs
+[ 	]+cc:[ 	]+356a[ 	]+move \[r5\],eda
+[ 	]+ce:[ 	]+367a[ 	]+move \[r6\],mof
+[ 	]+d0:[ 	]+378a[ 	]+move \[r7\],dz
+[ 	]+d2:[ 	]+329a[ 	]+move \[r2\],ebp
+[ 	]+d4:[ 	]+34aa[ 	]+move \[r4\],erp
+[ 	]+d6:[ 	]+30ba[ 	]+move \[r0\],srp
+[ 	]+d8:[ 	]+36ca[ 	]+move \[r6\],nrp
+[ 	]+da:[ 	]+3ada[ 	]+move \[r10\],ccs
+[ 	]+dc:[ 	]+3cea[ 	]+move \[r12\],usp
+[ 	]+de:[ 	]+3dfa[ 	]+move \[r13\],spc
diff --git a/gas/testsuite/gas/cris/rd-v32s-4.s b/gas/testsuite/gas/cris/rd-v32s-4.s
new file mode 100644
index 000000000000..4b3c46d865eb
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-v32s-4.s
@@ -0,0 +1,88 @@
+; Check special registers specified as pN.
+
+ .text
+here:
+ move $r3,$p0
+ move $r5,$p1
+ move $r6,$p2
+ move $r7,$p3
+ move $r8,$p4
+ move $r9,$p5
+ move $r5,$p6
+ move $r6,$p7
+ move $r7,$p8
+ move $r2,$p9
+ move $r4,$p10
+ move $r0,$p11
+ move $r6,$p12
+ move $r10,$p13
+ move $r12,$p14
+ move $r13,$p15
+
+ move $p0,$r3
+ move $p1,$r5
+ move $p2,$r6
+ move $p3,$r7
+ move $p4,$r8
+ move $p5,$r9
+ move $p6,$r5
+ move $p7,$r6
+ move $p8,$r7
+ move $p9,$r2
+ move $p10,$r4
+ move $p11,$r0
+ move $p12,$r6
+ move $p13,$r10
+ move $p14,$r12
+ move $p15,$r13
+
+ move 3,$p0
+ move 5,$p1
+ move 6,$p2
+ move 7,$p3
+ move 8,$p4
+ move 9,$p5
+ move 10,$p6
+ move 101,$p7
+ move 120,$p8
+ move 13,$p9
+ move 4,$p10
+ move 0,$p11
+ move 6,$p12
+ move 10,$p13
+ move 12,$p14
+ move 13,$p15
+
+ move $p0,[$r3]
+ move $p1,[$r5]
+ move $p2,[$r6]
+ move $p3,[$r7]
+ move $p4,[$r8]
+ move $p5,[$r9]
+ move $p6,[$r5]
+ move $p7,[$r6]
+ move $p8,[$r7]
+ move $p9,[$r2]
+ move $p10,[$r4]
+ move $p11,[$r0]
+ move $p12,[$r6]
+ move $p13,[$r10]
+ move $p14,[$r12]
+ move $p15,[$r13]
+
+ move [$r3],$p0
+ move [$r5],$p1
+ move [$r6],$p2
+ move [$r7],$p3
+ move [$r8],$p4
+ move [$r9],$p5
+ move [$r5],$p6
+ move [$r6],$p7
+ move [$r7],$p8
+ move [$r2],$p9
+ move [$r4],$p10
+ move [$r0],$p11
+ move [$r6],$p12
+ move [$r10],$p13
+ move [$r12],$p14
+ move [$r13],$p15
diff --git a/gas/testsuite/gas/cris/rd-vao-1.d b/gas/testsuite/gas/cris/rd-vao-1.d
new file mode 100644
index 000000000000..14b68bdd0ca8
--- /dev/null
+++ b/gas/testsuite/gas/cris/rd-vao-1.d
@@ -0,0 +1,11 @@
+#source: abs32-1.s
+#as: --underscore --em=criself --march=v0_v10
+#objdump: -p
+
+# Check that different command-line options result in different
+# machine-type stamps on the object files.  The source file
+# isn't important, as long the code assembles for the machine we
+# specify.
+
+.*:     file format elf32-us-cris
+private flags = 1: \[symbols have a _ prefix\]
diff --git a/gas/testsuite/gas/cris/v32-err-1.s b/gas/testsuite/gas/cris/v32-err-1.s
new file mode 100644
index 000000000000..220caf40bec0
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-1.s
@@ -0,0 +1,117 @@
+; { dg-do assemble }
+; { dg-options "--march=v0_v10" }
+
+; Check that valid v32-specific mnemonics and operands are not
+; recognized for v10.  (Also used elsewhere to check that valid
+; v32-specific insns and operands are recognized at assembly and
+; disassembly for v32.)
+
+ .text
+here:
+ move.d [$acr],$r3		; No error - $acr treated as a symbol.
+ move.d [$r5+],$acr		; { dg-error "(Illegal|Invalid) operands" }
+ move.d $acr,$r7		; No error - $acr treated as a symbol.
+ move.d $r8,$acr		; { dg-error "(Illegal|Invalid) operands" }
+ move $acr,$srp			; No error - $acr treated as a symbol.
+ addc $r0,$r0			; { dg-error "Unknown opcode" }
+ addc $acr,$acr			; { dg-error "Unknown opcode" }
+ addc $r6,$r1			; { dg-error "Unknown opcode" }
+ addc [$r3],$r1			; { dg-error "Unknown opcode" }
+ addc [$r0],$r0			; { dg-error "Unknown opcode" }
+ addc [$acr],$acr		; { dg-error "Unknown opcode" }
+ addc [$acr],$r1		; { dg-error "Unknown opcode" }
+ addc [$r3+],$r1		; { dg-error "Unknown opcode" }
+ addi $r8.w,$r2,$acr		; { dg-error "(Illegal|Invalid) operands" }
+ addi $r0.b,$r0,$acr		; { dg-error "(Illegal|Invalid) operands" }
+ addi $acr.d,$acr,$acr		; { dg-error "(Illegal|Invalid) operands" }
+ addo.d [$r3],$r7,$acr		; { dg-error "Unknown opcode" }
+ addo.d [$r13+],$r7,$acr	; { dg-error "Unknown opcode" }
+ addo.d [$r3],$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.b [$r0],$r0,$acr		; { dg-error "Unknown opcode" }
+ addo.d [$acr],$acr,$acr	; { dg-error "Unknown opcode" }
+ addo.b -1,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.w -1,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.d -1,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.b extsym1,$r3,$acr	; { dg-error "Unknown opcode" }
+ addo.w extsym2,$r3,$acr	; { dg-error "Unknown opcode" }
+ addo.d extsym3,$r3,$acr	; { dg-error "Unknown opcode" }
+ addo.b 127,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.w 32767,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.d 0xffffff,$acr,$acr	; { dg-error "Unknown opcode" }
+ addo.b -128,$acr,$acr		; { dg-error "Unknown opcode" }
+ addo.w -32768,$acr,$acr	; { dg-error "Unknown opcode" }
+ addo.d 0xffffffff,$acr,$acr	; { dg-error "Unknown opcode" }
+ lapc .,$r0			; { dg-error "Unknown opcode" }
+ lapc .+30,$r4			; { dg-error "Unknown opcode" }
+ lapc .+30,$acr			; { dg-error "Unknown opcode" }
+ lapc extsym4,$acr		; { dg-error "Unknown opcode" }
+ lapc extsym5,$r4		; { dg-error "Unknown opcode" }
+ lapc here,$r4			; { dg-error "Unknown opcode" }
+ addoq -1,$acr,$acr		; { dg-error "Unknown opcode" }
+ addoq 0,$r0,$acr		; { dg-error "Unknown opcode" }
+ addoq 127,$r4,$acr		; { dg-error "Unknown opcode" }
+ addoq extsym6,$r4,$acr		; { dg-error "Unknown opcode" }
+ bas 0xffffffff,$srp		; { dg-error "Unknown opcode" }
+ bas extsym7,$bz		; { dg-error "Unknown opcode" }
+ bas here,$erp			; { dg-error "Unknown opcode" }
+ basc 0xffffffff,$srp		; { dg-error "Unknown opcode" }
+ .dword 0
+ basc extsym8,$bz		; { dg-error "Unknown opcode" }
+ .dword 0
+ basc here,$erp			; { dg-error "Unknown opcode" }
+ .dword 0
+ bsb .				; { dg-error "Unknown opcode" }
+ nop
+ bsb here			; { dg-error "Unknown opcode" }
+ nop
+ bsr extsym9			; { dg-error "Unknown opcode" }
+ bsr here			; { dg-error "Unknown opcode" }
+ bsrc 0xffffffff		; { dg-error "Unknown opcode" }
+ .dword 0
+ bsrc extsym10			; { dg-error "Unknown opcode" }
+ .dword 0
+ bsrc here			; { dg-error "Unknown opcode" }
+ .dword 0
+ fidxd [$r0]			; { dg-error "Unknown opcode" }
+ fidxd [$acr]			; { dg-error "Unknown opcode" }
+ fidxi [$r0]			; { dg-error "Unknown opcode" }
+ fidxi [$acr]			; { dg-error "Unknown opcode" }
+ ftagd [$r0]			; { dg-error "Unknown opcode" }
+ ftagd [$acr]			; { dg-error "Unknown opcode" }
+ ftagi [$r0]			; { dg-error "Unknown opcode" }
+ ftagi [$acr]			; { dg-error "Unknown opcode" }
+ jas $r0,$bz			; { dg-error "Unknown opcode" }
+ jas $acr,$usp			; { dg-error "Unknown opcode" }
+ jas extsym9,$bz		; { dg-error "Unknown opcode" }
+ jas here,$srp			; { dg-error "Unknown opcode" }
+ jasc $r0,$bz			; { dg-error "Unknown opcode" }
+ .dword 0
+ jasc $acr,$usp			; { dg-error "Unknown opcode" }
+ .dword 0
+ jasc 0xffffffff,$srp		; { dg-error "Unknown opcode" }
+ .dword 0
+ jasc extsym11,$bz		; { dg-error "Unknown opcode" }
+ .dword 0
+ jasc here,$erp			; { dg-error "Unknown opcode" }
+ .dword 0
+ jump $srp			; No error - $srp treated as a symbol.
+ jump $bz			; No error - $bz treated as a symbol.
+ mcp $p0,$r0			; { dg-error "Unknown opcode" }
+ mcp $mof,$acr			; { dg-error "Unknown opcode" }
+ mcp $srp,$r2			; { dg-error "Unknown opcode" }
+ move $s0,$r0			; { dg-error "(Illegal|Invalid) operands" }
+ move $s15,$acr			; { dg-error "(Illegal|Invalid) operands" }
+ move $s5,$r3			; { dg-error "(Illegal|Invalid) operands" }
+ move $r0,$s0			; { dg-error "(Illegal|Invalid) operands" }
+ move $acr,$s15			; { dg-error "(Illegal|Invalid) operands" }
+ move $r4,$s10			; { dg-error "(Illegal|Invalid) operands" }
+ rfe				; { dg-error "Unknown opcode" }
+ rfg				; { dg-error "Unknown opcode" }
+ rete				; { dg-error "Unknown opcode" }
+ retn				; { dg-error "Unknown opcode" }
+ ssb $r0			; { dg-error "Unknown opcode" }
+ ssb $acr			; { dg-error "Unknown opcode" }
+ ssb $r10			; { dg-error "Unknown opcode" }
+ sfe				; { dg-error "Unknown opcode" }
+ halt				; { dg-error "Unknown opcode" }
+ rfn				; { dg-error "Unknown opcode" }
diff --git a/gas/testsuite/gas/cris/v32-err-10.s b/gas/testsuite/gas/cris/v32-err-10.s
new file mode 100644
index 000000000000..dda3c69a1548
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-10.s
@@ -0,0 +1,19 @@
+; { dg-do assemble }
+; { dg-options "--march=v32" }
+
+; Check that explicit contants out-of-range for addo are
+; identified.  We don't check addoq here, since that range check
+; is done at a later stage which isn't entered if there were
+; errors.
+
+ .text
+here:
+ addo.b 133,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addo.b 128,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addo.b -129,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addo.b 127,$r0,$acr
+ addo.b -128,$r0,$acr
+ addo.w 32768,$r0,$acr			; { dg-error "not in 16 bit signed range" }
+ addo.w -32769,$r0,$acr			; { dg-error "not in 16 bit signed range" }
+ addo.w 32767,$r0,$acr
+ addo.w -32768,$r0,$acr
diff --git a/gas/testsuite/gas/cris/v32-err-11.s b/gas/testsuite/gas/cris/v32-err-11.s
new file mode 100644
index 000000000000..70fe8e8403f4
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-11.s
@@ -0,0 +1,13 @@
+; { dg-do assemble }
+; { dg-options "--march=v32" }
+
+; Check that explicit contants out-of-range for addoq are
+; identified.  See also v32-err-10.s.
+
+ .text
+here:
+ addoq 133,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addoq 128,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addoq -129,$r0,$acr			; { dg-error "not in 8 bit signed range" }
+ addoq 127,$r0,$acr
+ addoq -128,$r0,$acr
diff --git a/gas/testsuite/gas/cris/v32-err-2.s b/gas/testsuite/gas/cris/v32-err-2.s
new file mode 100644
index 000000000000..0a5a3767f3ed
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-2.s
@@ -0,0 +1,14 @@
+; { dg-do assemble }
+; { dg-options " --underscore --march=common_v10_v32 --em=criself" }
+; { dg-error ".word offset handling is not implemented" "err for broken .word" { target cris-*-* } 0 }
+
+; Tests that broken words don't crash, just give a message when
+; in compatibility mode.
+
+sym2:	moveq 0,r0
+	.word	sym1 - sym2
+	moveq 1,r0
+	moveq 2,r0
+	.space	32766, 0
+sym1:	moveq 3,r0
+
diff --git a/gas/testsuite/gas/cris/v32-err-3.s b/gas/testsuite/gas/cris/v32-err-3.s
new file mode 100644
index 000000000000..4c2d1ec98464
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-3.s
@@ -0,0 +1,10 @@
+; Error for flags not applicable to current arch.
+; #1: Error for pre-v32 flags for v32.
+; { dg-do assemble }
+; { dg-options " --underscore --march=v32" }
+
+y:
+ clearf d	; { dg-error "(Illegal|Invalid) operands" }
+ setf D		; { dg-error "(Illegal|Invalid) operands" }
+ setf m		; { dg-error "(Illegal|Invalid) operands" }
+ clearf M	; { dg-error "(Illegal|Invalid) operands" }
diff --git a/gas/testsuite/gas/cris/v32-err-4.s b/gas/testsuite/gas/cris/v32-err-4.s
new file mode 100644
index 000000000000..547e15944440
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-4.s
@@ -0,0 +1,18 @@
+; Error for flags not applicable to current arch.
+; #2: Error for v32 flags for pre-v32.
+; { dg-do assemble }
+; { dg-options "--march=v0_v10" }
+
+y:
+ clearf p	; { dg-error "(Illegal|Invalid) operands" }
+ setf P		; { dg-error "(Illegal|Invalid) operands" }
+ setf u		; { dg-error "(Illegal|Invalid) operands" }
+ clearf U	; { dg-error "(Illegal|Invalid) operands" }
+ clearf d
+ setf D
+ clearf e
+ setf E
+ clearf b
+ setf B
+ setf m
+ clearf M
diff --git a/gas/testsuite/gas/cris/v32-err-5.s b/gas/testsuite/gas/cris/v32-err-5.s
new file mode 100644
index 000000000000..bf1f832ab8e2
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-5.s
@@ -0,0 +1,24 @@
+; Error for flags not applicable to current arch.
+; #3: Error for non-common flags for v10+v32.
+; { dg-do assemble }
+; { dg-options "--march=common_v10_v32" }
+
+y:
+ clearf p	; { dg-error "(Illegal|Invalid) operands" }
+ setf P		; { dg-error "(Illegal|Invalid) operands" }
+ setf u		; { dg-error "(Illegal|Invalid) operands" }
+ clearf U	; { dg-error "(Illegal|Invalid) operands" }
+ clearf d	; { dg-error "(Illegal|Invalid) operands" }
+ setf D		; { dg-error "(Illegal|Invalid) operands" }
+ setf z
+ setf X
+ clearf c
+ clearf V
+ setf n
+ clearf i
+ clearf e	; { dg-error "(Illegal|Invalid) operands" }
+ setf E		; { dg-error "(Illegal|Invalid) operands" }
+ clearf b	; { dg-error "(Illegal|Invalid) operands" }
+ setf B		; { dg-error "(Illegal|Invalid) operands" }
+ setf m		; { dg-error "(Illegal|Invalid) operands" }
+ clearf M	; { dg-error "(Illegal|Invalid) operands" }
diff --git a/gas/testsuite/gas/cris/v32-err-6.s b/gas/testsuite/gas/cris/v32-err-6.s
new file mode 100644
index 000000000000..21b147256c58
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-6.s
@@ -0,0 +1,18 @@
+; Error for flags not applicable to current arch.
+; #4: Error for v32 and pre-v10 flags for v10.
+; { dg-do assemble }
+; { dg-options "--march=v10" }
+
+y:
+ clearf p	; { dg-error "(Illegal|Invalid) operands" }
+ setf P		; { dg-error "(Illegal|Invalid) operands" }
+ setf u		; { dg-error "(Illegal|Invalid) operands" }
+ clearf U	; { dg-error "(Illegal|Invalid) operands" }
+ clearf d	; { dg-error "(Illegal|Invalid) operands" }
+ setf D		; { dg-error "(Illegal|Invalid) operands" }
+ clearf e	; { dg-error "(Illegal|Invalid) operands" }
+ setf E		; { dg-error "(Illegal|Invalid) operands" }
+ clearf b
+ setf B
+ setf m
+ clearf M
diff --git a/gas/testsuite/gas/cris/v32-err-7.s b/gas/testsuite/gas/cris/v32-err-7.s
new file mode 100644
index 000000000000..72b65033cdc6
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-7.s
@@ -0,0 +1,10 @@
+; Error for lapcq out-of-range.
+; { dg-do assemble }
+; { dg-options "--march=v32 --em=criself" }
+
+a:
+ nop
+ lapcq a,$r10	; { dg-error "not in 4.bit unsigned range" }
+ lapcq x,$r11	; { dg-error "not in 4.bit unsigned range" }
+ .space 30
+x:
diff --git a/gas/testsuite/gas/cris/v32-err-8.s b/gas/testsuite/gas/cris/v32-err-8.s
new file mode 100644
index 000000000000..105173ba3ce3
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-8.s
@@ -0,0 +1,9 @@
+; { dg-do assemble }
+; { dg-options "--march=common_v10_v32" }
+
+; USP does not have the same register number in v10 as in v32.
+
+ move $r10,$usp			; { dg-error "(Illegal|Invalid) operands" }
+ move 0xfabb0,$usp		; { dg-error "(Illegal|Invalid) operands" }
+ move $usp,[$r5]		; { dg-error "(Illegal|Invalid) operands" }
+ move [$r12],$usp		; { dg-error "(Illegal|Invalid) operands" }
diff --git a/gas/testsuite/gas/cris/v32-err-9.s b/gas/testsuite/gas/cris/v32-err-9.s
new file mode 100644
index 000000000000..dadea75e3961
--- /dev/null
+++ b/gas/testsuite/gas/cris/v32-err-9.s
@@ -0,0 +1,8 @@
+; { dg-do assemble }
+; { dg-options "--march=v32" }
+
+; "Test.m R" doesn't exist.
+
+ test.d $r10			; { dg-error "(Illegal|Invalid) operands" }
+ test.w $r0			; { dg-error "(Illegal|Invalid) operands" }
+ test.b $acr			; { dg-error "(Illegal|Invalid) operands" }
diff --git a/gas/testsuite/gas/crx/allinsn.exp b/gas/testsuite/gas/crx/allinsn.exp
new file mode 100644
index 000000000000..f3f8ae80a58e
--- /dev/null
+++ b/gas/testsuite/gas/crx/allinsn.exp
@@ -0,0 +1,27 @@
+#
+# Driver for CRX assembler testsuite
+#
+
+proc run_list_test { name opts } {
+  global srcdir subdir
+  set testname "CRX $name"
+  set file $srcdir/$subdir/$name
+  gas_run ${name}.s $opts ">&dump.out"
+  if {[regexp_diff "dump.out" "${file}.l"] } {
+    fail $testname
+    verbose "output is [file_contents "dump.out"]" 2
+    return
+  }
+  pass $testname
+}
+
+if ![istarget crx-*-*] {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach test $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $test]
+    run_dump_test [file rootname $test]
+}
diff --git a/gas/testsuite/gas/crx/arith_insn.d b/gas/testsuite/gas/crx/arith_insn.d
new file mode 100644
index 000000000000..6017f3f4172b
--- /dev/null
+++ b/gas/testsuite/gas/crx/arith_insn.d
@@ -0,0 +1,192 @@
+#as:
+#objdump: -dr
+#name: arith_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <addub>:
+   0:	01 00       	addub	\$0x0, r1
+   2:	e2 00 05 00 	addub	\$0x5, r2
+   6:	34 40       	addub	r3, r4
+
+00000008 <addb>:
+   8:	15 01       	addb	\$0x1, r5
+   a:	e6 01 06 00 	addb	\$0x6, r6
+   e:	78 41       	addb	r7, r8
+
+00000010 <addcb>:
+  10:	29 02       	addcb	\$0x2, r9
+  12:	ea 02 09 00 	addcb	\$0x9, r10
+  16:	bc 42       	addcb	r11, r12
+
+00000018 <andb>:
+  18:	3d 03       	andb	\$0x3, r13
+  1a:	9e 03       	andb	\$0x10, r14
+  1c:	fe 43       	andb	r15, r14
+
+0000001e <cmpb>:
+  1e:	4f 04       	cmpb	\$0x4, r15
+  20:	e1 04 11 00 	cmpb	\$0x11, r1
+  24:	23 44       	cmpb	r2, r3
+
+00000026 <movb>:
+  26:	54 05       	movb	\$0xfffffffc, r4
+  28:	e5 05 36 02 	movb	\$0x236, r5
+  2c:	67 45       	movb	r6, r7
+
+0000002e <orb>:
+  2e:	68 06       	orb	\$0xffffffff, r8
+  30:	e9 06 80 69 	orb	\$0x6980, r9
+  34:	ab 46       	orb	r10, r11
+
+00000036 <subb>:
+  36:	7c 07       	subb	\$0x7, r12
+  38:	ed 07 ff 7f 	subb	\$0x7fff, r13
+  3c:	ef 47       	subb	r14, r15
+
+0000003e <subcb>:
+  3e:	8e 08       	subcb	\$0x8, r14
+  40:	ef 08 aa ff 	subcb	\$0xffaa, r15
+  44:	12 48       	subcb	r1, r2
+
+00000046 <xorb>:
+  46:	e3 09 16 00 	xorb	\$0x16, r3
+  4a:	e4 09 02 90 	xorb	\$0x9002, r4
+  4e:	56 49       	xorb	r5, r6
+
+00000050 <mulb>:
+  50:	e7 0a 32 00 	mulb	\$0x32, r7
+  54:	e8 0a fa 0e 	mulb	\$0xefa, r8
+  58:	9a 4a       	mulb	r9, r10
+
+0000005a <adduw>:
+  5a:	ab 10       	adduw	\$0x20, r11
+  5c:	ec 10 ff 7f 	adduw	\$0x7fff, r12
+  60:	de 50       	adduw	r13, r14
+
+00000062 <addw>:
+  62:	ef 11 12 00 	addw	\$0x12, r15
+  66:	ee 11 01 80 	addw	\$0x8001, r14
+  6a:	f1 51       	addw	r15, r1
+
+0000006c <addcw>:
+  6c:	e2 12 48 00 	addcw	\$0x48, r2
+  70:	e3 12 1b 00 	addcw	\$0x1b, r3
+  74:	45 52       	addcw	r4, r5
+
+00000076 <andw>:
+  76:	06 13       	andw	\$0x0, r6
+  78:	e7 13 e5 ff 	andw	\$0xffe5, r7
+  7c:	89 53       	andw	r8, r9
+
+0000007e <cmpw>:
+  7e:	1a 14       	cmpw	\$0x1, r10
+  80:	eb 14 11 00 	cmpw	\$0x11, r11
+  84:	cd 54       	cmpw	r12, r13
+
+00000086 <movw>:
+  86:	2e 15       	movw	\$0x2, r14
+  88:	ef 15 00 0e 	movw	\$0xe00, r15
+  8c:	ef 55       	movw	r14, r15
+
+0000008e <orw>:
+  8e:	31 16       	orw	\$0x3, r1
+  90:	e2 16 fe ff 	orw	\$0xfffe, r2
+  94:	34 56       	orw	r3, r4
+
+00000096 <subw>:
+  96:	45 17       	subw	\$0x4, r5
+  98:	e6 17 12 00 	subw	\$0x12, r6
+  9c:	78 57       	subw	r7, r8
+
+0000009e <subcw>:
+  9e:	59 18       	subcw	\$0xfffffffc, r9
+  a0:	ea 18 f7 ff 	subcw	\$0xfff7, r10
+  a4:	bc 58       	subcw	r11, r12
+
+000000a6 <xorw>:
+  a6:	6d 19       	xorw	\$0xffffffff, r13
+  a8:	ee 19 21 00 	xorw	\$0x21, r14
+  ac:	fe 59       	xorw	r15, r14
+
+000000ae <mulw>:
+  ae:	7f 1a       	mulw	\$0x7, r15
+  b0:	e1 1a 17 00 	mulw	\$0x17, r1
+  b4:	23 5a       	mulw	r2, r3
+
+000000b6 <addud>:
+  b6:	01 20       	addud	\$0x0, r1
+  b8:	e2 20 05 00 	addud	\$0x5, r2
+  bc:	f2 20 05 00 	addud	\$0x55555, r2
+  c0:	55 55 
+  c2:	34 60       	addud	r3, r4
+
+000000c4 <addd>:
+  c4:	15 21       	addd	\$0x1, r5
+  c6:	e6 21 06 00 	addd	\$0x6, r6
+  ca:	f6 21 ff 7f 	addd	\$0x7fffffff, r6
+  ce:	ff ff 
+  d0:	78 61       	addd	r7, r8
+
+000000d2 <addcd>:
+  d2:	29 22       	addcd	\$0x2, r9
+  d4:	ea 22 09 00 	addcd	\$0x9, r10
+  d8:	fa 22 00 80 	addcd	\$0x80000001, r10
+  dc:	01 00 
+  de:	bc 62       	addcd	r11, r12
+
+000000e0 <andd>:
+  e0:	3d 23       	andd	\$0x3, r13
+  e2:	9e 23       	andd	\$0x10, r14
+  e4:	6e 23       	andd	\$0xffffffff, r14
+  e6:	fe 63       	andd	r15, r14
+
+000000e8 <cmpd>:
+  e8:	4f 24       	cmpd	\$0x4, r15
+  ea:	e1 24 11 00 	cmpd	\$0x11, r1
+  ee:	f1 24 00 f0 	cmpd	\$0xf0000001, r1
+  f2:	01 00 
+  f4:	23 64       	cmpd	r2, r3
+
+000000f6 <movd>:
+  f6:	54 25       	movd	\$0xfffffffc, r4
+  f8:	e5 25 36 02 	movd	\$0x236, r5
+  fc:	f5 25 00 80 	movd	\$0x80000000, r5
+ 100:	00 00 
+ 102:	67 65       	movd	r6, r7
+
+00000104 <ord>:
+ 104:	68 26       	ord	\$0xffffffff, r8
+ 106:	e9 26 80 69 	ord	\$0x6980, r9
+ 10a:	f9 26 01 00 	ord	\$0x10000, r9
+ 10e:	00 00 
+ 110:	ab 66       	ord	r10, r11
+
+00000112 <subd>:
+ 112:	7c 27       	subd	\$0x7, r12
+ 114:	ed 27 ff 7f 	subd	\$0x7fff, r13
+ 118:	fd 27 ff ff 	subd	\$0xffff0000, r13
+ 11c:	00 00 
+ 11e:	ef 67       	subd	r14, r15
+
+00000120 <subcd>:
+ 120:	8e 28       	subcd	\$0x8, r14
+ 122:	ef 28 aa ff 	subcd	\$0xffaa, r15
+ 126:	6f 28       	subcd	\$0xffffffff, r15
+ 128:	12 68       	subcd	r1, r2
+
+0000012a <xord>:
+ 12a:	e3 29 16 00 	xord	\$0x16, r3
+ 12e:	e4 29 02 90 	xord	\$0x9002, r4
+ 132:	f4 29 ff 7f 	xord	\$0x7fffffff, r4
+ 136:	ff ff 
+ 138:	56 69       	xord	r5, r6
+
+0000013a <muld>:
+ 13a:	e7 2a 32 00 	muld	\$0x32, r7
+ 13e:	e8 2a fa 0e 	muld	\$0xefa, r8
+ 142:	f8 2a 00 80 	muld	\$0x80000001, r8
+ 146:	01 00 
+ 148:	9a 6a       	muld	r9, r10
diff --git a/gas/testsuite/gas/crx/arith_insn.s b/gas/testsuite/gas/crx/arith_insn.s
new file mode 100644
index 000000000000..f0c6045c44a7
--- /dev/null
+++ b/gas/testsuite/gas/crx/arith_insn.s
@@ -0,0 +1,214 @@
+# Arithmetic instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global addub
+addub:
+addub $0x0 , r1
+addub $0x5 , r2
+addub r3 , r4
+
+	.global addb
+addb:
+addb $0x1 , r5
+addb $0x6 , r6
+addb r7 , r8
+
+	.global addcb
+addcb:
+addcb $2 , r9
+addcb $0x9 , r10
+addcb r11 , r12
+
+	.global andb
+andb:
+andb $0x3 , r13
+andb $0x10 , r14
+andb r15 , ra
+
+	.global cmpb
+cmpb:
+cmpb $0x4 , sp
+cmpb $0x11 , r1
+cmpb r2 , r3
+
+	.global movb
+movb:
+movb $-4 , r4
+movb $0x236 , r5
+movb r6 , r7
+
+	.global orb
+orb:
+orb $-0x1 , r8
+orb $0x6980 , r9
+orb r10 , r11
+
+	.global subb
+subb:
+subb $07 , r12
+subb $0x7fff , r13
+subb r14 , r15
+
+	.global subcb
+subcb:
+subcb $010 , ra
+subcb $-0x56 , sp
+subcb r1 , r2
+
+	.global xorb
+xorb:
+xorb $0x16 , r3
+xorb $-0x6ffe , r4
+xorb r5 , r6
+
+	.global mulb
+mulb:
+mulb $0x32 , r7
+mulb $0xefa , r8
+mulb r9 , r10
+
+	.global adduw
+adduw:
+adduw $0x20 , r11
+adduw $32767 , r12
+adduw r13 , r14
+
+	.global addw
+addw:
+addw $0x12 , r15
+addw $-32767 , ra
+addw sp , r1
+
+	.global addcw
+addcw:
+addcw $0x48 , r2
+addcw $27 , r3
+addcw r4 , r5
+
+	.global andw
+andw:
+andw $0 , r6
+andw $-27 , r7
+andw r8 , r9
+
+	.global cmpw
+cmpw:
+cmpw $1 , r10
+cmpw $0x11 , r11
+cmpw r12 , r13
+
+	.global movw
+movw:
+movw $0x2 , r14
+movw $07000 , r15
+movw ra , sp
+
+	.global orw
+orw:
+orw $0x3 , r1
+orw $-2 , r2
+orw r3 , r4
+
+	.global subw
+subw:
+subw $04 , r5
+subw $022 , r6
+subw r7 , r8
+
+	.global subcw
+subcw:
+subcw $-0x4 , r9
+subcw $-9 , r10
+subcw r11 , r12
+
+	.global xorw
+xorw:
+xorw $-1 , r13
+xorw $0x21 , r14
+xorw r15 , ra
+
+	.global mulw
+mulw:
+mulw $0x7 , sp
+mulw $027 , r1
+mulw r2 , r3
+
+	.global addud
+addud:
+addud $0x0 , r1
+addud $0x5 , r2
+addud $0x55555 , r2
+addud r3 , r4
+
+	.global addd
+addd:
+addd $0x1 , r5
+addd $0x6 , r6
+addd $0x7fffffff , r6
+addd r7 , r8
+
+	.global addcd
+addcd:
+addcd $2 , r9
+addcd $0x9 , r10
+addcd $-0x7fffffff , r10
+addcd r11 , r12
+
+	.global andd
+andd:
+andd $0x3 , r13
+andd $0x10 , r14
+andd $0xffffffff , r14
+andd r15 , ra
+
+	.global cmpd
+cmpd:
+cmpd $0x4 , sp
+cmpd $0x11 , r1
+cmpd $0xf0000001 , r1
+cmpd r2 , r3
+
+	.global movd
+movd:
+movd $-4 , r4
+movd $0x236 , r5
+movd $-0x80000000 , r5
+movd r6 , r7
+
+	.global ord
+ord:
+ord $-0x1 , r8
+ord $0x6980 , r9
+ord $0x10000 , r9
+ord r10 , r11
+
+	.global subd
+subd:
+subd $07 , r12
+subd $0x7fff , r13
+subd $-0x10000 , r13
+subd r14 , r15
+
+	.global subcd
+subcd:
+subcd $010 , ra
+subcd $-0x56 , sp
+subcd $4294967295 , sp
+subcd r1 , r2
+
+	.global xord
+xord:
+xord $0x16 , r3
+xord $-0x6ffe , r4
+xord $017777777777 , r4
+xord r5 , r6
+
+	.global muld
+muld:
+muld $0x32 , r7
+muld $0xefa , r8
+muld $-017777777777 , r8
+muld r9 , r10
diff --git a/gas/testsuite/gas/crx/beq_insn.d b/gas/testsuite/gas/crx/beq_insn.d
new file mode 100644
index 000000000000..dc4ebc8892e4
--- /dev/null
+++ b/gas/testsuite/gas/crx/beq_insn.d
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dr
+#name: beq_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <beq0b>:
+   0:	aa b0       	beq0b	r10, 0x16 [-_<>+0-9a-z]*
+
+00000002 <bne0b>:
+   2:	fb b1       	bne0b	r11, 0x20 [-_<>+0-9a-z]*
+
+00000004 <beq0w>:
+   4:	0c b2       	beq0w	r12, 0x2 [-_<>+0-9a-z]*
+
+00000006 <bne0w>:
+   6:	fd b3       	bne0w	r13, 0x20 [-_<>+0-9a-z]*
+
+00000008 <beq0d>:
+   8:	fe b4       	beq0d	r14, 0x20 [-_<>+0-9a-z]*
+
+0000000a <bne0d>:
+   a:	7f b5       	bne0d	r15, 0x10 [-_<>+0-9a-z]*
diff --git a/gas/testsuite/gas/crx/beq_insn.s b/gas/testsuite/gas/crx/beq_insn.s
new file mode 100644
index 000000000000..2f5d5ade017f
--- /dev/null
+++ b/gas/testsuite/gas/crx/beq_insn.s
@@ -0,0 +1,32 @@
+# 'Branch if Equal to 0' instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global beq0b
+beq0b:
+beq0b r10 , *+22
+
+	.global bne0b
+bne0b:
+bne0b r11 , *+0x20
+
+	.global beq0w
+beq0w:
+beq0w r12 , *+2
+
+	.global bne0w
+bne0w:
+bne0w r13 , *+040
+
+	.global beq0d
+beq0d:
+beq0d ra , *+32
+
+	.global bne0d
+bne0d:
+bne0d sp , *+16
+
+
+
diff --git a/gas/testsuite/gas/crx/bit_insn.d b/gas/testsuite/gas/crx/bit_insn.d
new file mode 100644
index 000000000000..6f75a82d056c
--- /dev/null
+++ b/gas/testsuite/gas/crx/bit_insn.d
@@ -0,0 +1,145 @@
+#as:
+#objdump: -dr
+#name: bit_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <cbitb>:
+   0:	06 39 00 00 	cbitb	\$0x6, 0x450 [-_<>+0-9a-z]*
+   4:	50 04 
+   6:	06 38 50 04 	cbitb	\$0x6, 0xffff0450 [-_<>+0-9a-z]*
+   a:	07 39 04 00 	cbitb	\$0x7, 0x41287 [-_<>+0-9a-z]*
+   e:	87 12 
+  10:	03 3a 09 50 	cbitb	\$0x3, 0x9\(r5\)
+  14:	0f fe       	cbitb	\$0x0, \(r15\)
+  16:	02 3b ff 10 	cbitb	\$0x2, 0xffffe1\(r1\)
+  1a:	e1 ff 
+  1c:	04 3d 00 ef 	cbitb	\$0x4, 0xfa\(r14,r15,1\)
+  20:	fa 00 
+  22:	07 3d ff f7 	cbitb	\$0x7, 0x3ffeb3\(r15,r7,8\)
+  26:	b3 fe 
+
+00000028 <cbitw>:
+  28:	2f 39 00 00 	cbitw	\$0xf, 0x23 [-_<>+0-9a-z]*
+  2c:	23 00 
+  2e:	26 38 23 00 	cbitw	\$0x6, 0xffff0023 [-_<>+0-9a-z]*
+  32:	21 39 0f 00 	cbitw	\$0x1, 0xff287 [-_<>+0-9a-z]*
+  36:	87 f2 
+  38:	2f 3a 01 50 	cbitw	\$0xf, 0x1\(r5\)
+  3c:	0e bd       	cbitw	\$0x0, \(r14\)
+  3e:	25 3b ff 10 	cbitw	\$0x5, 0xffffe1\(r1\)
+  42:	e1 ff 
+  44:	28 3d 40 ef 	cbitw	\$0x8, 0xaf\(r14,r15,2\)
+  48:	af 00 
+  4a:	27 3d bf 13 	cbitw	\$0x7, 0x3fff38\(r1,r3,4\)
+  4e:	38 ff 
+
+00000050 <cbitd>:
+  50:	66 39 00 00 	cbitd	\$0x6, 0xff [-_<>+0-9a-z]*
+  54:	ff 00 
+  56:	66 38 ff 0f 	cbitd	\$0x6, 0xffff0fff [-_<>+0-9a-z]*
+  5a:	7a 39 01 00 	cbitd	\$0x1a, 0x10000 [-_<>+0-9a-z]*
+  5e:	00 00 
+  60:	7f 3a 07 90 	cbitd	\$0x1f, 0x7\(r9\)
+  64:	02 f7       	cbitd	\$0x10, \(r2\)
+  66:	7a 3b ff 20 	cbitd	\$0x1a, 0xffffe1\(r2\)
+  6a:	e1 ff 
+  6c:	7e 3c 0a 3f 	cbitd	\$0x1e, 0xa\(r3,r15,1\)
+  70:	67 3d ff 45 	cbitd	\$0x7, 0x3ffb80\(r4,r5,8\)
+  74:	80 fb 
+  76:	08 30 68 38 	cbitd	r6, r8
+  7a:	08 30 e4 f7 	cbitd	\$0x1e, r4
+
+0000007e <sbitb>:
+  7e:	0e 39 00 00 	sbitb	\$0x6, 0x450 [-_<>+0-9a-z]*
+  82:	50 04 
+  84:	0e 38 50 04 	sbitb	\$0x6, 0xffff0450 [-_<>+0-9a-z]*
+  88:	0f 39 04 00 	sbitb	\$0x7, 0x41287 [-_<>+0-9a-z]*
+  8c:	87 12 
+  8e:	0b 3a 09 50 	sbitb	\$0x3, 0x9\(r5\)
+  92:	8f fe       	sbitb	\$0x0, \(r15\)
+  94:	0a 3b ff 10 	sbitb	\$0x2, 0xffffe1\(r1\)
+  98:	e1 ff 
+  9a:	0c 3d 00 ef 	sbitb	\$0x4, 0xfa\(r14,r15,1\)
+  9e:	fa 00 
+  a0:	0f 3d ff f7 	sbitb	\$0x7, 0x3ffeb3\(r15,r7,8\)
+  a4:	b3 fe 
+
+000000a6 <sbitw>:
+  a6:	3f 39 00 00 	sbitw	\$0xf, 0x23 [-_<>+0-9a-z]*
+  aa:	23 00 
+  ac:	36 38 23 00 	sbitw	\$0x6, 0xffff0023 [-_<>+0-9a-z]*
+  b0:	31 39 0f 00 	sbitw	\$0x1, 0xff287 [-_<>+0-9a-z]*
+  b4:	87 f2 
+  b6:	3f 3a 01 50 	sbitw	\$0xf, 0x1\(r5\)
+  ba:	0e be       	sbitw	\$0x0, \(r14\)
+  bc:	35 3b ff 10 	sbitw	\$0x5, 0xffffe1\(r1\)
+  c0:	e1 ff 
+  c2:	38 3d 40 ef 	sbitw	\$0x8, 0xaf\(r14,r15,2\)
+  c6:	af 00 
+  c8:	37 3d bf 13 	sbitw	\$0x7, 0x3fff38\(r1,r3,4\)
+  cc:	38 ff 
+
+000000ce <sbitd>:
+  ce:	86 39 00 00 	sbitd	\$0x6, 0xff [-_<>+0-9a-z]*
+  d2:	ff 00 
+  d4:	86 38 ff 0f 	sbitd	\$0x6, 0xffff0fff [-_<>+0-9a-z]*
+  d8:	9a 39 01 00 	sbitd	\$0x1a, 0x10000 [-_<>+0-9a-z]*
+  dc:	00 00 
+  de:	9f 3a 07 90 	sbitd	\$0x1f, 0x7\(r9\)
+  e2:	02 f9       	sbitd	\$0x10, \(r2\)
+  e4:	9a 3b ff 20 	sbitd	\$0x1a, 0xffffe1\(r2\)
+  e8:	e1 ff 
+  ea:	9e 3c 0a 3f 	sbitd	\$0x1e, 0xa\(r3,r15,1\)
+  ee:	87 3d ff 45 	sbitd	\$0x7, 0x3ffb80\(r4,r5,8\)
+  f2:	80 fb 
+  f4:	08 30 68 39 	sbitd	r6, r8
+  f8:	08 30 e4 f9 	sbitd	\$0x1e, r4
+
+000000fc <tbitb>:
+  fc:	16 39 00 00 	tbitb	\$0x6, 0x450 [-_<>+0-9a-z]*
+ 100:	50 04 
+ 102:	16 38 50 04 	tbitb	\$0x6, 0xffff0450 [-_<>+0-9a-z]*
+ 106:	17 39 04 00 	tbitb	\$0x7, 0x41287 [-_<>+0-9a-z]*
+ 10a:	87 12 
+ 10c:	13 3a 09 50 	tbitb	\$0x3, 0x9\(r5\)
+ 110:	0f ff       	tbitb	\$0x0, \(r15\)
+ 112:	12 3b ff 10 	tbitb	\$0x2, 0xffffe1\(r1\)
+ 116:	e1 ff 
+ 118:	14 3d 00 ef 	tbitb	\$0x4, 0xfa\(r14,r15,1\)
+ 11c:	fa 00 
+ 11e:	17 3d ff f7 	tbitb	\$0x7, 0x3ffeb3\(r15,r7,8\)
+ 122:	b3 fe 
+
+00000124 <tbitw>:
+ 124:	4f 39 00 00 	tbitw	\$0xf, 0x23 [-_<>+0-9a-z]*
+ 128:	23 00 
+ 12a:	46 38 23 00 	tbitw	\$0x6, 0xffff0023 [-_<>+0-9a-z]*
+ 12e:	41 39 0f 00 	tbitw	\$0x1, 0xff287 [-_<>+0-9a-z]*
+ 132:	87 f2 
+ 134:	4f 3a 01 50 	tbitw	\$0xf, 0x1\(r5\)
+ 138:	0e bf       	tbitw	\$0x0, \(r14\)
+ 13a:	45 3b ff 10 	tbitw	\$0x5, 0xffffe1\(r1\)
+ 13e:	e1 ff 
+ 140:	48 3d 40 ef 	tbitw	\$0x8, 0xaf\(r14,r15,2\)
+ 144:	af 00 
+ 146:	47 3d bf 13 	tbitw	\$0x7, 0x3fff38\(r1,r3,4\)
+ 14a:	38 ff 
+
+0000014c <tbitd>:
+ 14c:	a6 39 00 00 	tbitd	\$0x6, 0xff [-_<>+0-9a-z]*
+ 150:	ff 00 
+ 152:	a6 38 ff 0f 	tbitd	\$0x6, 0xffff0fff [-_<>+0-9a-z]*
+ 156:	ba 39 01 00 	tbitd	\$0x1a, 0x10000 [-_<>+0-9a-z]*
+ 15a:	00 00 
+ 15c:	bf 3a 07 90 	tbitd	\$0x1f, 0x7\(r9\)
+ 160:	02 fb       	tbitd	\$0x10, \(r2\)
+ 162:	ba 3b ff 20 	tbitd	\$0x1a, 0xffffe1\(r2\)
+ 166:	e1 ff 
+ 168:	be 3c 0a 3f 	tbitd	\$0x1e, 0xa\(r3,r15,1\)
+ 16c:	a7 3d ff 45 	tbitd	\$0x7, 0x3ffb80\(r4,r5,8\)
+ 170:	80 fb 
+ 172:	08 30 68 3a 	tbitd	r6, r8
+ 176:	08 30 e4 fb 	tbitd	\$0x1e, r4
diff --git a/gas/testsuite/gas/crx/bit_insn.s b/gas/testsuite/gas/crx/bit_insn.s
new file mode 100644
index 000000000000..25b39217cef3
--- /dev/null
+++ b/gas/testsuite/gas/crx/bit_insn.s
@@ -0,0 +1,113 @@
+# Bit instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+# cbit instructions.
+	.global cbitb
+cbitb:
+cbitb $6, 0x450
+cbitb $0x6, 0xffff0450
+cbitb $7, 0x41287
+cbitb $3, 9(r5)
+cbitb $0, (sp)
+cbitb $2, 0xffffe1(r1)
+cbitb $4, 0xfa(ra,sp,1)
+cbitb $0x7, -333(r15,r7,8)
+
+	.global cbitw
+cbitw:
+cbitw $0xf, 0x23
+cbitw $0x6, 0xffff0023
+cbitw $01, 0xff287
+cbitw $15, 1(r5)
+cbitw $0, (r14)
+cbitw $5, 0xffffe1(r1)
+cbitw $8, 0xaf(ra,sp,2)
+cbitw $0x7, -200(r1,r3,4)
+
+	.global cbitd
+cbitd:
+cbitd $6, 0xff
+cbitd $0x6, 0xffff0fff
+cbitd $0x1a, 0x10000
+cbitd $31, 7(r9)
+cbitd $020, (r2)
+cbitd $26, 0xffffe1(r2)
+cbitd $30, 0xa(r3,sp,1)
+cbitd $0x7, -0x480(r4,r5,8)
+cbitd r6, r8
+cbitd $30, r4
+
+# sbit instructions.
+	.global sbitb
+sbitb:
+sbitb $6, 0x450
+sbitb $0x6, 0xffff0450
+sbitb $7, 0x41287
+sbitb $3, 9(r5)
+sbitb $0, (sp)
+sbitb $2, 0xffffe1(r1)
+sbitb $4, 0xfa(ra,sp,1)
+sbitb $0x7, -333(r15,r7,8)
+
+	.global sbitw
+sbitw:
+sbitw $0xf, 0x23
+sbitw $0x6, 0xffff0023
+sbitw $01, 0xff287
+sbitw $15, 1(r5)
+sbitw $0, (r14)
+sbitw $5, 0xffffe1(r1)
+sbitw $8, 0xaf(ra,sp,2)
+sbitw $0x7, -200(r1,r3,4)
+
+	.global sbitd
+sbitd:
+sbitd $6, 0xff
+sbitd $0x6, 0xffff0fff
+sbitd $0x1a, 0x10000
+sbitd $31, 7(r9)
+sbitd $020, (r2)
+sbitd $26, 0xffffe1(r2)
+sbitd $30, 0xa(r3,sp,1)
+sbitd $0x7, -0x480(r4,r5,8)
+sbitd r6, r8
+sbitd $30, r4
+
+# tbit instructions.
+	.global tbitb
+tbitb:
+tbitb $6, 0x450
+tbitb $0x6, 0xffff0450
+tbitb $7, 0x41287
+tbitb $3, 9(r5)
+tbitb $0, (sp)
+tbitb $2, 0xffffe1(r1)
+tbitb $4, 0xfa(ra,sp,1)
+tbitb $0x7, -333(r15,r7,8)
+
+	.global tbitw
+tbitw:
+tbitw $0xf, 0x23
+tbitw $0x6, 0xffff0023
+tbitw $01, 0xff287
+tbitw $15, 1(r5)
+tbitw $0, (r14)
+tbitw $5, 0xffffe1(r1)
+tbitw $8, 0xaf(ra,sp,2)
+tbitw $0x7, -200(r1,r3,4)
+
+	.global tbitd
+tbitd:
+tbitd $6, 0xff
+tbitd $0x6, 0xffff0fff
+tbitd $0x1a, 0x10000
+tbitd $31, 7(r9)
+tbitd $020, (r2)
+tbitd $26, 0xffffe1(r2)
+tbitd $30, 0xa(r3,sp,1)
+tbitd $0x7, -0x480(r4,r5,8)
+tbitd r6, r8
+tbitd $30, r4
diff --git a/gas/testsuite/gas/crx/br_insn.d b/gas/testsuite/gas/crx/br_insn.d
new file mode 100644
index 000000000000..e79229988f49
--- /dev/null
+++ b/gas/testsuite/gas/crx/br_insn.d
@@ -0,0 +1,123 @@
+#as:
+#objdump: -dr
+#name: br_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <beq>:
+   0:	08 70       	beq	0x[0-9a-f]* [-_<>+0-9a-z]*
+   2:	7e 70 fd 07 	beq	0x[0-9a-f]* [-_<>+0-9a-z]*
+   6:	7f 70 04 00 	beq	0x[0-9a-f]* [-_<>+0-9a-z]*
+   a:	29 55 
+
+0000000c <bne>:
+   c:	fc 71       	bne	0x[0-9a-f]* [-_<>+0-9a-z]*
+   e:	7e 71 a3 07 	bne	0x[0-9a-f]* [-_<>+0-9a-z]*
+  12:	7f 71 f8 ff 	bne	0x[0-9a-f]* [-_<>+0-9a-z]*
+  16:	f7 43 
+
+00000018 <bcs>:
+  18:	7d 72       	bcs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  1a:	7e 72 c6 ec 	bcs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  1e:	7f 72 04 00 	bcs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  22:	29 48 
+
+00000024 <bcc>:
+  24:	83 73       	bcc	0x[0-9a-f]* [-_<>+0-9a-z]*
+  26:	7e 73 ff 7f 	bcc	0x[0-9a-f]* [-_<>+0-9a-z]*
+  2a:	ff 73       	bcc	0x[0-9a-f]* [-_<>+0-9a-z]*
+
+0000002c <bhi>:
+  2c:	7e 74 7f 00 	bhi	0x[0-9a-f]* [-_<>+0-9a-z]*
+  30:	7e 74 01 80 	bhi	0x[0-9a-f]* [-_<>+0-9a-z]*
+  34:	01 74       	bhi	0x[0-9a-f]* [-_<>+0-9a-z]*
+
+00000036 <bls>:
+  36:	ff 75       	bls	0x[0-9a-f]* [-_<>+0-9a-z]*
+  38:	7e 75 00 80 	bls	0x[0-9a-f]* [-_<>+0-9a-z]*
+  3c:	7f 75 00 00 	bls	0x[0-9a-f]* [-_<>+0-9a-z]*
+  40:	00 80 
+
+00000042 <bgt>:
+  42:	18 76       	bgt	0x[0-9a-f]* [-_<>+0-9a-z]*
+  44:	7e 76 ff 07 	bgt	0x[0-9a-f]* [-_<>+0-9a-z]*
+  48:	7f 76 ff ff 	bgt	0x[0-9a-f]* [-_<>+0-9a-z]*
+  4c:	ff 7f 
+
+0000004e <ble>:
+  4e:	e0 77       	ble	0x[0-9a-f]* [-_<>+0-9a-z]*
+  50:	7e 77 7f ff 	ble	0x[0-9a-f]* [-_<>+0-9a-z]*
+  54:	7f 77 07 00 	ble	0x[0-9a-f]* [-_<>+0-9a-z]*
+  58:	f9 7f 
+
+0000005a <bfs>:
+  5a:	01 78       	bfs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  5c:	7e 78 ff 7f 	bfs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  60:	7f 78 00 00 	bfs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  64:	00 80 
+
+00000066 <bfc>:
+  66:	7e 79 7f 00 	bfc	0x[0-9a-f]* [-_<>+0-9a-z]*
+  6a:	7e 79 ff 7f 	bfc	0x[0-9a-f]* [-_<>+0-9a-z]*
+  6e:	7f 79 04 00 	bfc	0x[0-9a-f]* [-_<>+0-9a-z]*
+  72:	00 00 
+
+00000074 <blo>:
+  74:	81 7a       	blo	0x[0-9a-f]* [-_<>+0-9a-z]*
+  76:	7e 7a 01 80 	blo	0x[0-9a-f]* [-_<>+0-9a-z]*
+  7a:	ff 7a       	blo	0x[0-9a-f]* [-_<>+0-9a-z]*
+
+0000007c <bhs>:
+  7c:	80 7b       	bhs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  7e:	7e 7b 00 88 	bhs	0x[0-9a-f]* [-_<>+0-9a-z]*
+  82:	7e 7b f9 07 	bhs	0x[0-9a-f]* [-_<>+0-9a-z]*
+
+00000086 <blt>:
+  86:	11 7c       	blt	0x[0-9a-f]* [-_<>+0-9a-z]*
+  88:	7e 7c 69 02 	blt	0x[0-9a-f]* [-_<>+0-9a-z]*
+  8c:	ff 7c       	blt	0x[0-9a-f]* [-_<>+0-9a-z]*
+
+0000008e <bge>:
+  8e:	1a 7d       	bge	0x[0-9a-f]* [-_<>+0-9a-z]*
+  90:	7e 7d e6 f6 	bge	0x[0-9a-f]* [-_<>+0-9a-z]*
+  94:	7f 7d 08 00 	bge	0x[0-9a-f]* [-_<>+0-9a-z]*
+  98:	01 00 
+
+0000009a <br>:
+  9a:	0e 7e       	br	0x[0-9a-f]* [-_<>+0-9a-z]*
+  9c:	7e 7e 4e 01 	br	0x[0-9a-f]* [-_<>+0-9a-z]*
+  a0:	7f 7e f7 ff 	br	0x[0-9a-f]* [-_<>+0-9a-z]*
+  a4:	ff ff 
+
+000000a6 <dbnzb>:
+  a6:	40 30 0e 00 	dbnzb	r0, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  aa:	41 30 97 53 	dbnzb	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+
+000000ae <dbnzw>:
+  ae:	52 30 cc 0c 	dbnzw	r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  b2:	53 31 31 00 	dbnzw	r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  b6:	d8 ff 
+
+000000b8 <dbnzd>:
+  b8:	6e 30 f9 07 	dbnzd	r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  bc:	6f 31 97 00 	dbnzd	r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  c0:	fa ff 
+
+000000c2 <bal>:
+  c2:	71 30 01 00 	bal	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  c6:	71 30 ff ff 	bal	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  ca:	71 30 e7 55 	bal	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  ce:	70 30 59 fa 	bal	r0, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  d2:	71 31 05 00 	bal	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  d6:	6f 5e 
+  d8:	71 31 fa ff 	bal	r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  dc:	91 a1 
+
+000000de <jal>:
+  de:	8e ff       	jal	r14
+  e0:	08 30 1f 37 	jal	r1, r15
+
+000000e4 <jalid>:
+  e4:	08 30 ce 33 	jalid	r12, r14
diff --git a/gas/testsuite/gas/crx/br_insn.s b/gas/testsuite/gas/crx/br_insn.s
new file mode 100644
index 000000000000..10b8a66b4485
--- /dev/null
+++ b/gas/testsuite/gas/crx/br_insn.s
@@ -0,0 +1,132 @@
+# Branch instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+# conditional branch instructions.
+	.global beq
+beq:
+beq *+16
+beq *+4090
+beq *+567890
+
+	.global bne
+bne:
+bne *-8
+bne *+0xf46
+bne *-0xf7812
+
+	.global bcs
+bcs:
+bcs *+250
+bcs *-0x2674
+bcs *+0x89052
+
+	.global bcc
+bcc:
+bcc *-250
+bcc *+0xfffe
+bcc *+0xfffffffe
+
+	.global bhi
+bhi:
+bhi *+254
+bhi *-0xfffe
+bhi *-0xfffffffe
+
+	.global bls
+bls:
+bls *-2
+bls *-0x10000
+bls *+0x10000
+
+	.global bgt
+bgt:
+bgt *+060
+bgt *+0xffe
+bgt *-0x10002
+
+	.global ble
+ble:
+ble *-0100 
+ble *-258
+ble *+0xefff2
+
+	.global bfs
+bfs:
+bfs *+0x2 
+bfs *+0177776
+bfs *+0200000 
+
+	.global bfc
+bfc:
+bfc *+0xfe
+bfc *+65534
+bfc *+0x80000
+
+	.global blo
+blo:
+blo *-0xfe
+blo *-65534
+blo *+4294967294
+
+	.global bhs
+bhs:
+bhs *-0x100
+bhs *-0xf000
+bhs *+0xff2
+
+	.global blt
+blt:
+blt *+34
+blt *+1234
+blt *+037777777776
+
+	.global bge
+bge:
+bge *+0x34
+bge *-0x1234
+bge *+1048578
+
+	.global br
+br:
+br *+034
+br *+01234
+br *-04000002
+
+# Decrement and Branch instructions.
+	.global dbnzb
+dbnzb:
+dbnzb r0, *+034
+dbnzb r1, *+01234568
+
+	.global dbnzw
+dbnzw:
+dbnzw r2, *+6552
+dbnzw r3, *+6553520
+
+	.global dbnzd
+dbnzd:
+dbnzd ra, *+0xff2
+dbnzd sp, *+0x12ffff4
+
+# Branch/Jump and link instructions.
+
+	.global bal
+bal:
+bal r1, 0x2
+bal r1, -0x2
+bal r1, 0xabce
+bal r0, -0xb4e
+bal r1, 0xabcde
+bal r1, -0xabcde
+
+	.global jal
+jal:
+jal ra
+jal r1, sp
+
+	.global jalid
+jalid:
+jalid r12, r14
diff --git a/gas/testsuite/gas/crx/cmov_insn.d b/gas/testsuite/gas/crx/cmov_insn.d
new file mode 100644
index 000000000000..b99fec2f4d17
--- /dev/null
+++ b/gas/testsuite/gas/crx/cmov_insn.d
@@ -0,0 +1,49 @@
+#as:
+#objdump: -dr
+#name: cmov_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <cmoveqd>:
+   0:	08 30 01 70 	cmoveqd	r0, r1
+
+00000004 <cmovned>:
+   4:	08 30 23 71 	cmovned	r2, r3
+
+00000008 <cmovcsd>:
+   8:	08 30 45 72 	cmovcsd	r4, r5
+
+0000000c <cmovccd>:
+   c:	08 30 67 73 	cmovccd	r6, r7
+
+00000010 <cmovhid>:
+  10:	08 30 89 74 	cmovhid	r8, r9
+
+00000014 <cmovlsd>:
+  14:	08 30 ab 75 	cmovlsd	r10, r11
+
+00000018 <cmovgtd>:
+  18:	08 30 cd 76 	cmovgtd	r12, r13
+
+0000001c <cmovled>:
+  1c:	08 30 ef 77 	cmovled	r14, r15
+
+00000020 <cmovfsd>:
+  20:	08 30 fe 78 	cmovfsd	r15, r14
+
+00000024 <cmovfcd>:
+  24:	08 30 fe 79 	cmovfcd	r15, r14
+
+00000028 <cmovlod>:
+  28:	08 30 f0 7a 	cmovlod	r15, r0
+
+0000002c <cmovhsd>:
+  2c:	08 30 23 7b 	cmovhsd	r2, r3
+
+00000030 <cmovltd>:
+  30:	08 30 75 7c 	cmovltd	r7, r5
+
+00000034 <cmovged>:
+  34:	08 30 34 7d 	cmovged	r3, r4
diff --git a/gas/testsuite/gas/crx/cmov_insn.s b/gas/testsuite/gas/crx/cmov_insn.s
new file mode 100644
index 000000000000..31bc2585a8ff
--- /dev/null
+++ b/gas/testsuite/gas/crx/cmov_insn.s
@@ -0,0 +1,61 @@
+# Conditional move instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global cmoveqd
+cmoveqd:
+cmoveqd r0 , r1
+
+	.global cmovned
+cmovned:
+cmovned r2 , r3
+
+	.global cmovcsd
+cmovcsd:
+cmovcsd r4 , r5
+
+	.global cmovccd
+cmovccd:
+cmovccd r6 , r7
+
+	.global cmovhid
+cmovhid:
+cmovhid r8 , r9
+
+	.global cmovlsd
+cmovlsd:
+cmovlsd r10 , r11
+
+	.global cmovgtd
+cmovgtd:
+cmovgtd r12 , r13
+
+	.global cmovled
+cmovled:
+cmovled r14 , sp
+
+	.global cmovfsd
+cmovfsd:
+cmovfsd r15 , ra
+
+	.global cmovfcd
+cmovfcd:
+cmovfcd sp , ra
+
+	.global cmovlod
+cmovlod:
+cmovlod r15 , r0
+
+	.global cmovhsd
+cmovhsd:
+cmovhsd r2 , r3
+
+	.global cmovltd
+cmovltd:
+cmovltd r7 , r5
+
+	.global cmovged
+cmovged:
+cmovged r3 , r4
diff --git a/gas/testsuite/gas/crx/cmpbr_insn.d b/gas/testsuite/gas/crx/cmpbr_insn.d
new file mode 100644
index 000000000000..c244f77e625d
--- /dev/null
+++ b/gas/testsuite/gas/crx/cmpbr_insn.d
@@ -0,0 +1,250 @@
+#as:
+#objdump: -dr
+#name: cmpbr_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <cmpbeqb>:
+   0:	81 30 2b 20 	cmpbeqb	r1, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+   4:	83 31 00 40 	cmpbeqb	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+   8:	a4 21 
+   a:	c0 30 1b 50 	cmpbeqb	\$0x0, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+   e:	c1 31 1a 60 	cmpbeqb	\$0x1, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  12:	3c 2b 
+
+00000014 <cmpbneb>:
+  14:	87 30 7d 81 	cmpbneb	r7, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  18:	89 31 00 a1 	cmpbneb	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  1c:	00 78 
+  1e:	c2 30 01 b1 	cmpbneb	\$0x2, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  22:	c3 31 7f c1 	cmpbneb	\$0x3, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  26:	ff ff 
+
+00000028 <cmpbhib>:
+  28:	8d 31 00 e4 	cmpbhib	r13, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  2c:	80 00 
+  2e:	8f 31 00 e4 	cmpbhib	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  32:	81 00 
+  34:	c4 30 ff f4 	cmpbhib	\$0x4, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  38:	c5 31 ff 14 	cmpbhib	\$0xfffffffc, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  3c:	7e ff 
+
+0000003e <cmpblsb>:
+  3e:	82 30 3c 35 	cmpblsb	r2, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  42:	84 31 00 55 	cmpblsb	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  46:	80 00 
+  48:	c6 30 84 65 	cmpblsb	\$0xffffffff, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  4c:	c7 31 ff 75 	cmpblsb	\$0x7, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  50:	7f ff 
+
+00000052 <cmpbgtb>:
+  52:	88 30 83 96 	cmpbgtb	r8, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  56:	8a 31 00 b6 	cmpbgtb	r10, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  5a:	e0 07 
+  5c:	c8 30 7f c6 	cmpbgtb	\$0x8, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  60:	c9 31 7f d6 	cmpbgtb	\$0x10, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  64:	f9 ff 
+
+00000066 <cmpbleb>:
+  66:	8e 30 81 f7 	cmpbleb	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  6a:	8e 31 ff f7 	cmpbleb	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  6e:	00 ff 
+  70:	c9 30 1b 17 	cmpbleb	\$0x10, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  74:	c9 31 80 27 	cmpbleb	\$0x10, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  78:	7f 00 
+
+0000007a <cmpblob>:
+  7a:	83 30 e4 4a 	cmpblob	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  7e:	85 31 80 6a 	cmpblob	r5, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  82:	01 00 
+  84:	ca 30 12 7a 	cmpblob	\$0x20, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  88:	ca 31 7f 8a 	cmpblob	\$0x20, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  8c:	ff ff 
+
+0000008e <cmpbhsb>:
+  8e:	89 30 78 ab 	cmpbhsb	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  92:	8b 31 00 cb 	cmpbhsb	r11, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  96:	81 00 
+  98:	ca 30 81 db 	cmpbhsb	\$0x20, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  9c:	cb 31 00 eb 	cmpbhsb	\$0x14, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  a0:	00 08 
+
+000000a2 <cmpbltb>:
+  a2:	8f 30 08 ec 	cmpbltb	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  a6:	8f 31 00 1c 	cmpbltb	r15, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  aa:	31 02 
+  ac:	cc 30 f8 2c 	cmpbltb	\$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  b0:	cc 31 c0 3c 	cmpbltb	\$0xc, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  b4:	00 00 
+
+000000b6 <cmpbgeb>:
+  b6:	84 30 00 5d 	cmpbgeb	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  ba:	86 31 20 7d 	cmpbgeb	r6, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  be:	00 00 
+  c0:	cd 30 00 8d 	cmpbgeb	\$0x30, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  c4:	cd 31 f8 9d 	cmpbgeb	\$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  c8:	00 00 
+
+000000ca <cmpbeqw>:
+  ca:	91 30 2b 20 	cmpbeqw	r1, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  ce:	93 31 00 40 	cmpbeqw	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  d2:	a4 21 
+  d4:	d0 30 1b 50 	cmpbeqw	\$0x0, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  d8:	d1 31 1a 60 	cmpbeqw	\$0x1, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  dc:	3c 2b 
+
+000000de <cmpbnew>:
+  de:	97 30 7d 81 	cmpbnew	r7, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  e2:	99 31 00 a1 	cmpbnew	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  e6:	00 78 
+  e8:	d2 30 01 b1 	cmpbnew	\$0x2, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  ec:	d3 31 7f c1 	cmpbnew	\$0x3, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  f0:	ff ff 
+
+000000f2 <cmpbhiw>:
+  f2:	9d 31 00 e4 	cmpbhiw	r13, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  f6:	80 00 
+  f8:	9f 31 00 e4 	cmpbhiw	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  fc:	81 00 
+  fe:	d4 30 ff f4 	cmpbhiw	\$0x4, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 102:	d5 31 ff 14 	cmpbhiw	\$0xfffffffc, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 106:	7e ff 
+
+00000108 <cmpblsw>:
+ 108:	92 30 3c 35 	cmpblsw	r2, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 10c:	94 31 00 55 	cmpblsw	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 110:	80 00 
+ 112:	d6 30 84 65 	cmpblsw	\$0xffffffff, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 116:	d7 31 ff 75 	cmpblsw	\$0x7, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 11a:	7f ff 
+
+0000011c <cmpbgtw>:
+ 11c:	98 30 83 96 	cmpbgtw	r8, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 120:	9a 31 00 b6 	cmpbgtw	r10, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 124:	e0 07 
+ 126:	d8 30 7f c6 	cmpbgtw	\$0x8, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 12a:	d9 31 7f d6 	cmpbgtw	\$0x10, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 12e:	f9 ff 
+
+00000130 <cmpblew>:
+ 130:	9e 30 81 f7 	cmpblew	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 134:	9e 31 ff f7 	cmpblew	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 138:	00 ff 
+ 13a:	d9 30 1b 17 	cmpblew	\$0x10, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 13e:	d9 31 80 27 	cmpblew	\$0x10, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 142:	7f 00 
+
+00000144 <cmpblow>:
+ 144:	93 30 e4 4a 	cmpblow	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 148:	95 31 80 6a 	cmpblow	r5, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 14c:	01 00 
+ 14e:	da 30 12 7a 	cmpblow	\$0x20, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 152:	da 31 7f 8a 	cmpblow	\$0x20, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 156:	ff ff 
+
+00000158 <cmpbhsw>:
+ 158:	99 30 78 ab 	cmpbhsw	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 15c:	9b 31 00 cb 	cmpbhsw	r11, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 160:	81 00 
+ 162:	da 30 81 db 	cmpbhsw	\$0x20, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 166:	db 31 00 eb 	cmpbhsw	\$0x14, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 16a:	00 08 
+
+0000016c <cmpbltw>:
+ 16c:	9f 30 08 ec 	cmpbltw	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 170:	9f 31 00 1c 	cmpbltw	r15, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 174:	31 02 
+ 176:	dc 30 f8 2c 	cmpbltw	\$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 17a:	dc 31 c0 3c 	cmpbltw	\$0xc, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 17e:	00 00 
+
+00000180 <cmpbgew>:
+ 180:	94 30 00 5d 	cmpbgew	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 184:	96 31 20 7d 	cmpbgew	r6, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 188:	00 00 
+ 18a:	dd 30 00 8d 	cmpbgew	\$0x30, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 18e:	dd 31 f8 9d 	cmpbgew	\$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 192:	00 00 
+
+00000194 <cmpbeqd>:
+ 194:	a1 30 2b 20 	cmpbeqd	r1, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 198:	a3 31 00 40 	cmpbeqd	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 19c:	a4 21 
+ 19e:	e0 30 1b 50 	cmpbeqd	\$0x0, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1a2:	e1 31 1a 60 	cmpbeqd	\$0x1, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1a6:	3c 2b 
+
+000001a8 <cmpbned>:
+ 1a8:	a7 30 7d 81 	cmpbned	r7, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1ac:	a9 31 00 a1 	cmpbned	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1b0:	00 78 
+ 1b2:	e2 30 01 b1 	cmpbned	\$0x2, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1b6:	e3 31 7f c1 	cmpbned	\$0x3, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1ba:	ff ff 
+
+000001bc <cmpbhid>:
+ 1bc:	ad 31 00 e4 	cmpbhid	r13, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1c0:	80 00 
+ 1c2:	af 31 00 e4 	cmpbhid	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1c6:	81 00 
+ 1c8:	e4 30 ff f4 	cmpbhid	\$0x4, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1cc:	e5 31 ff 14 	cmpbhid	\$0xfffffffc, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1d0:	7e ff 
+
+000001d2 <cmpblsd>:
+ 1d2:	a2 30 3c 35 	cmpblsd	r2, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1d6:	a4 31 00 55 	cmpblsd	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1da:	80 00 
+ 1dc:	e6 30 84 65 	cmpblsd	\$0xffffffff, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1e0:	e7 31 ff 75 	cmpblsd	\$0x7, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1e4:	7f ff 
+
+000001e6 <cmpbgtd>:
+ 1e6:	a8 30 83 96 	cmpbgtd	r8, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1ea:	aa 31 00 b6 	cmpbgtd	r10, r11, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1ee:	e0 07 
+ 1f0:	e8 30 7f c6 	cmpbgtd	\$0x8, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1f4:	e9 31 7f d6 	cmpbgtd	\$0x10, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1f8:	f9 ff 
+
+000001fa <cmpbled>:
+ 1fa:	ae 30 81 f7 	cmpbled	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 1fe:	ae 31 ff f7 	cmpbled	r14, r15, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 202:	00 ff 
+ 204:	e9 30 1b 17 	cmpbled	\$0x10, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 208:	e9 31 80 27 	cmpbled	\$0x10, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 20c:	7f 00 
+
+0000020e <cmpblod>:
+ 20e:	a3 30 e4 4a 	cmpblod	r3, r4, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 212:	a5 31 80 6a 	cmpblod	r5, r6, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 216:	01 00 
+ 218:	ea 30 12 7a 	cmpblod	\$0x20, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 21c:	ea 31 7f 8a 	cmpblod	\$0x20, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 220:	ff ff 
+
+00000222 <cmpbhsd>:
+ 222:	a9 30 78 ab 	cmpbhsd	r9, r10, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 226:	ab 31 00 cb 	cmpbhsd	r11, r12, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 22a:	81 00 
+ 22c:	ea 30 81 db 	cmpbhsd	\$0x20, r13, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 230:	eb 31 00 eb 	cmpbhsd	\$0x14, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 234:	00 08 
+
+00000236 <cmpbltd>:
+ 236:	af 30 08 ec 	cmpbltd	r15, r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 23a:	af 31 00 1c 	cmpbltd	r15, r1, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 23e:	31 02 
+ 240:	ec 30 f8 2c 	cmpbltd	\$0xc, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 244:	ec 31 c0 3c 	cmpbltd	\$0xc, r3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 248:	00 00 
+
+0000024a <cmpbged>:
+ 24a:	a4 30 00 5d 	cmpbged	r4, r5, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 24e:	a6 31 20 7d 	cmpbged	r6, r7, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 252:	00 00 
+ 254:	ed 30 00 8d 	cmpbged	\$0x30, r8, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 258:	ed 31 f8 9d 	cmpbged	\$0x30, r9, 0x[0-9a-f]* [-_<>+0-9a-z]*
+ 25c:	00 00 
diff --git a/gas/testsuite/gas/crx/cmpbr_insn.s b/gas/testsuite/gas/crx/cmpbr_insn.s
new file mode 100644
index 000000000000..9406afa248f1
--- /dev/null
+++ b/gas/testsuite/gas/crx/cmpbr_insn.s
@@ -0,0 +1,217 @@
+# 'Compare & Branch' instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global cmpbeqb
+cmpbeqb:
+cmpbeqb r1, r2, 0x56
+cmpbeqb r3, r4, 0x4348
+cmpbeqb $0, r5, 0x36
+cmpbeqb $1, r6, 0x345678
+
+	.global cmpbneb
+cmpbneb:
+cmpbneb r7, r8, 250
+cmpbneb r9, r10, 0xf000
+cmpbneb $2, r11, 0x2
+cmpbneb $3, r12, 0xfffffe
+
+	.global cmpbhib
+cmpbhib:
+cmpbhib r13, r14, 0400
+cmpbhib r15, ra, 258
+cmpbhib $4, sp, -0x2
+cmpbhib $-4, r1, -260
+
+	.global cmpblsb
+cmpblsb:
+cmpblsb r2, r3, 0x78
+cmpblsb r4, r5, 0x100
+cmpblsb $-1, r6, -0370
+cmpblsb $7, r7, -0x102
+
+	.global cmpbgtb
+cmpbgtb:
+cmpbgtb r8, r9, -250
+cmpbgtb r10, r11, 07700
+cmpbgtb $8, r12, 0xfe
+cmpbgtb $16, r13, 0xfffff2
+
+	.global cmpbleb
+cmpbleb:
+cmpbleb r14, r15, -0xfe
+cmpbleb ra, sp, -01000
+cmpbleb $0x10, r1, 066
+cmpbleb $020, r2, -0xffff02
+
+	.global cmpblob
+cmpblob:
+cmpblob r3, r4, -070
+cmpblob r5, r6, -0xfffffe
+cmpblob $32, r7, +0x24
+cmpblob $0x20, r8, 16777214
+
+	.global cmpbhsb
+cmpbhsb:
+cmpbhsb r9, r10, 0xf0
+cmpbhsb r11, r12, 0402
+cmpbhsb $040, r13, -254
+cmpbhsb $20, r14, 0x1000
+
+	.global cmpbltb
+cmpbltb:
+cmpbltb r15, ra, 0x10
+cmpbltb sp, r1, 1122
+cmpbltb $12, r2, -020
+cmpbltb $0xc, r3, -0x800000
+
+	.global cmpbgeb
+cmpbgeb:
+cmpbgeb r4, r5, 0x0
+cmpbgeb r6, r7, 0x400000
+cmpbgeb $48, r8, 0
+cmpbgeb $060, r9, -0x100000
+
+
+	.global cmpbeqw
+cmpbeqw:
+cmpbeqw r1, r2, 0x56
+cmpbeqw r3, r4, 0x4348
+cmpbeqw $0, r5, 0x36
+cmpbeqw $1, r6, 0x345678
+
+	.global cmpbnew
+cmpbnew:
+cmpbnew r7, r8, 250
+cmpbnew r9, r10, 0xf000
+cmpbnew $2, r11, 0x2
+cmpbnew $3, r12, 0xfffffe
+
+	.global cmpbhiw
+cmpbhiw:
+cmpbhiw r13, r14, 0400
+cmpbhiw r15, ra, 258
+cmpbhiw $4, sp, -0x2
+cmpbhiw $-4, r1, -260
+
+	.global cmpblsw
+cmpblsw:
+cmpblsw r2, r3, 0x78
+cmpblsw r4, r5, 0x100
+cmpblsw $-1, r6, -0370
+cmpblsw $7, r7, -0x102
+
+	.global cmpbgtw
+cmpbgtw:
+cmpbgtw r8, r9, -250
+cmpbgtw r10, r11, 07700
+cmpbgtw $8, r12, 0xfe
+cmpbgtw $16, r13, 0xfffff2
+
+	.global cmpblew
+cmpblew:
+cmpblew r14, r15, -0xfe
+cmpblew ra, sp, -01000
+cmpblew $0x10, r1, 066
+cmpblew $020, r2, -0xffff02
+
+	.global cmpblow
+cmpblow:
+cmpblow r3, r4, -070
+cmpblow r5, r6, -0xfffffe
+cmpblow $32, r7, +0x24
+cmpblow $0x20, r8, 16777214
+
+	.global cmpbhsw
+cmpbhsw:
+cmpbhsw r9, r10, 0xf0
+cmpbhsw r11, r12, 0402
+cmpbhsw $040, r13, -254
+cmpbhsw $20, r14, 0x1000
+
+	.global cmpbltw
+cmpbltw:
+cmpbltw r15, ra, 0x10
+cmpbltw sp, r1, 1122
+cmpbltw $12, r2, -020
+cmpbltw $0xc, r3, -0x800000
+
+	.global cmpbgew
+cmpbgew:
+cmpbgew r4, r5, 0x0
+cmpbgew r6, r7, 0x400000
+cmpbgew $48, r8, 0
+cmpbgew $060, r9, -0x100000
+
+
+	.global cmpbeqd
+cmpbeqd:
+cmpbeqd r1, r2, 0x56
+cmpbeqd r3, r4, 0x4348
+cmpbeqd $0, r5, 0x36
+cmpbeqd $1, r6, 0x345678
+
+	.global cmpbned
+cmpbned:
+cmpbned r7, r8, 250
+cmpbned r9, r10, 0xf000
+cmpbned $2, r11, 0x2
+cmpbned $3, r12, 0xfffffe
+
+	.global cmpbhid
+cmpbhid:
+cmpbhid r13, r14, 0400
+cmpbhid r15, ra, 258
+cmpbhid $4, sp, -0x2
+cmpbhid $-4, r1, -260
+
+	.global cmpblsd
+cmpblsd:
+cmpblsd r2, r3, 0x78
+cmpblsd r4, r5, 0x100
+cmpblsd $-1, r6, -0370
+cmpblsd $7, r7, -0x102
+
+	.global cmpbgtd
+cmpbgtd:
+cmpbgtd r8, r9, -250
+cmpbgtd r10, r11, 07700
+cmpbgtd $8, r12, 0xfe
+cmpbgtd $16, r13, 0xfffff2
+
+	.global cmpbled
+cmpbled:
+cmpbled r14, r15, -0xfe
+cmpbled ra, sp, -01000
+cmpbled $0x10, r1, 066
+cmpbled $020, r2, -0xffff02
+
+	.global cmpblod
+cmpblod:
+cmpblod r3, r4, -070
+cmpblod r5, r6, -0xfffffe
+cmpblod $32, r7, +0x24
+cmpblod $0x20, r8, 16777214
+
+	.global cmpbhsd
+cmpbhsd:
+cmpbhsd r9, r10, 0xf0
+cmpbhsd r11, r12, 0402
+cmpbhsd $040, r13, -254
+cmpbhsd $20, r14, 0x1000
+
+	.global cmpbltd
+cmpbltd:
+cmpbltd r15, ra, 0x10
+cmpbltd sp, r1, 1122
+cmpbltd $12, r2, -020
+cmpbltd $0xc, r3, -0x800000
+
+	.global cmpbged
+cmpbged:
+cmpbged r4, r5, 0x0
+cmpbged r6, r7, 0x400000
+cmpbged $48, r8, 0
+cmpbged $060, r9, -0x100000
diff --git a/gas/testsuite/gas/crx/cop_insn.d b/gas/testsuite/gas/crx/cop_insn.d
new file mode 100644
index 000000000000..322089c0e2bd
--- /dev/null
+++ b/gas/testsuite/gas/crx/cop_insn.d
@@ -0,0 +1,72 @@
+#as:
+#objdump: -dr
+#name: cop_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <cpi>:
+   0:	12 30 34 12 	cpi	\$0x2, \$0x1234
+   4:	13 31 65 87 	cpi	\$0x3, \$0x4321, \$0x8765
+   8:	21 43 
+
+0000000a <mtcr>:
+   a:	1f 30 1e 30 	mtcr	\$0xf, r1, c14
+
+0000000e <mfcr>:
+   e:	13 30 72 31 	mfcr	\$0x3, c7, r2
+
+00000012 <mtcsr>:
+  12:	12 30 51 32 	mtcsr	\$0x2, r5, cs1
+
+00000016 <mfcsr>:
+  16:	11 30 ce 33 	mfcsr	\$0x1, cs12, r14
+
+0000001a <ldcr>:
+  1a:	11 30 38 34 	ldcr	\$0x1, r3, c8
+
+0000001e <stcr>:
+  1e:	12 30 4b 35 	stcr	\$0x2, c11, r4
+
+00000022 <ldcsr>:
+  22:	14 30 6c 36 	ldcsr	\$0x4, r6, cs12
+
+00000026 <stcsr>:
+  26:	17 30 da 37 	stcsr	\$0x7, cs10, r13
+
+0000002a <loadmcr>:
+  2a:	13 31 01 30 	loadmcr	\$0x3, r1, {c0,c12,c13}
+  2e:	2c 00 
+
+00000030 <stormcr>:
+  30:	1f 31 1e 30 	stormcr	\$0xf, r14, {c1,c2,c3,c4,c12,c13}
+  34:	90 06 
+
+00000036 <loadmcsr>:
+  36:	1c 31 28 30 	loadmcsr	\$0xc, r8, {cs3,cs5,cs12,cs13}
+  3a:	80 0f 
+
+0000003c <stormcsr>:
+  3c:	19 31 39 30 	stormcsr	\$0x9, r9, {cs0,cs3,cs4,cs5,cs12,cs13}
+  40:	90 04 
+
+00000042 <bcop>:
+  42:	13 30 48 77 	bcop	\$0x7, \$0x3, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  46:	1c 31 fa 76 	bcop	\$0x6, \$0xc, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  4a:	01 19 
+
+0000004c <cpdop>:
+  4c:	13 30 45 b2 	cpdop	\$0x3, \$0x2, r4, r5
+  50:	17 31 12 ba 	cpdop	\$0x7, \$0xa, r1, r2, \$0xba12
+  54:	34 12 
+
+00000056 <mtpr>:
+  56:	09 30 10 00 	mtpr	r0, hi
+
+0000005a <mfpr>:
+  5a:	0a 30 05 11 	mfpr	lo, r5
+  5e:	0a 30 0a 90 	mfpr	uhi, r10
+
+00000062 <cinv>:
+  62:	10 30 0f 00 	cinv	\[b,d,i,u\]
diff --git a/gas/testsuite/gas/crx/cop_insn.s b/gas/testsuite/gas/crx/cop_insn.s
new file mode 100644
index 000000000000..d91260bc13d8
--- /dev/null
+++ b/gas/testsuite/gas/crx/cop_insn.s
@@ -0,0 +1,82 @@
+# Co-Processor instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global cpi
+cpi:
+cpi $0x2, $0x1234
+cpi $3, $0x8765, $0x4321
+
+	.global mtcr
+mtcr:
+mtcr $0xf, r1, c14
+
+	.global mfcr
+mfcr:
+mfcr $3, c7, r2
+
+	.global mtcsr
+mtcsr:
+mtcsr $0x2, r5, cs1
+
+	.global mfcsr
+mfcsr:
+mfcsr $01, cs12, ra
+
+	.global ldcr
+ldcr:
+ldcr $1, r3, c8
+
+	.global stcr
+stcr:
+stcr $2, c11, r4
+
+	.global ldcsr
+ldcsr:
+ldcsr $4, r6, cs12
+
+	.global stcsr
+stcsr:
+stcsr $7, cs10, r13
+
+	.global loadmcr
+loadmcr:
+loadmcr $3, r1, {c2,c3,c5}
+
+	.global stormcr
+stormcr:
+stormcr $15, ra, {c10,c9,c7,c4}
+
+	.global loadmcsr
+loadmcsr:
+loadmcsr $12, r8, {cs7, cs8, cs9, cs10, cs11}
+
+	.global stormcsr
+stormcsr:
+stormcsr $9, r9, {cs10,cs7,cs4}
+
+	.global bcop
+bcop:
+bcop $7, $3, 0x90
+bcop $6, $12, -0xbcdfe
+
+	.global cpdop
+cpdop:
+cpdop $3, $2, r4, r5
+cpdop $7, $10, r1, r2, $0x1234
+
+	.global mtpr
+mtpr:
+mtpr r0 , hi
+
+	.global mfpr
+mfpr:
+mfpr lo , r5
+mfpr uhi , r10
+
+	.global cinv
+cinv:
+cinv [i,d,u,b]
+
diff --git a/gas/testsuite/gas/crx/gas-segfault.d b/gas/testsuite/gas/crx/gas-segfault.d
new file mode 100644
index 000000000000..9cf772632af3
--- /dev/null
+++ b/gas/testsuite/gas/crx/gas-segfault.d
@@ -0,0 +1,17 @@
+#as:
+#objdump: -dr
+#name: GAS segmentation fault
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc>:
+   0:	ee ba       	jump	r14
+	...
+
+00000004 <_main>:
+   4:	6f 34 00 40 	push	r15, {r14}
+   8:	7e 30 00 00 	bal	r14, 0x8 <_main\+0x4>
+			8: R_CRX_REL16	__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc
+   c:	6f 32 00 40 	popret	r15, {r14}
diff --git a/gas/testsuite/gas/crx/gas-segfault.s b/gas/testsuite/gas/crx/gas-segfault.s
new file mode 100644
index 000000000000..7156665df988
--- /dev/null
+++ b/gas/testsuite/gas/crx/gas-segfault.s
@@ -0,0 +1,20 @@
+	# PR 1063
+	# This source file used to make GAS crash with a seg fault
+        .section        .text
+        .align  4
+        .globl __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc
+        .type  __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc,@function
+__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc:
+        jump    ra
+
+        .size  __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc,.-__Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc
+        .align  4
+        .globl  _main
+        .type   _main, @function
+_main:
+        push    sp, { ra }
+        bal     ra, __Z1flllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllc
+        popret  sp, { ra }
+        .size   _main, .-_main
+
+
diff --git a/gas/testsuite/gas/crx/jscond_insn.d b/gas/testsuite/gas/crx/jscond_insn.d
new file mode 100644
index 000000000000..f45b53584587
--- /dev/null
+++ b/gas/testsuite/gas/crx/jscond_insn.d
@@ -0,0 +1,94 @@
+#as:
+#objdump: -dr
+#name: jscond_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <jeq>:
+   0:	01 ba       	jeq	r1
+
+00000002 <jne>:
+   2:	12 ba       	jne	r2
+
+00000004 <jcs>:
+   4:	23 ba       	jcs	r3
+
+00000006 <jcc>:
+   6:	34 ba       	jcc	r4
+
+00000008 <jhi>:
+   8:	45 ba       	jhi	r5
+
+0000000a <jls>:
+   a:	56 ba       	jls	r6
+
+0000000c <jgt>:
+   c:	67 ba       	jgt	r7
+
+0000000e <jle>:
+   e:	78 ba       	jle	r8
+
+00000010 <jfs>:
+  10:	89 ba       	jfs	r9
+
+00000012 <jfc>:
+  12:	9a ba       	jfc	r10
+
+00000014 <jlo>:
+  14:	ab ba       	jlo	r11
+
+00000016 <jhs>:
+  16:	bc ba       	jhs	r12
+
+00000018 <jlt>:
+  18:	cd ba       	jlt	r13
+
+0000001a <jge>:
+  1a:	de ba       	jge	r14
+
+0000001c <jump>:
+  1c:	ef ba       	jump	r15
+
+0000001e <seq>:
+  1e:	01 bb       	seq	r1
+
+00000020 <sne>:
+  20:	12 bb       	sne	r2
+
+00000022 <scs>:
+  22:	23 bb       	scs	r3
+
+00000024 <scc>:
+  24:	34 bb       	scc	r4
+
+00000026 <shi>:
+  26:	45 bb       	shi	r5
+
+00000028 <sls>:
+  28:	56 bb       	sls	r6
+
+0000002a <sgt>:
+  2a:	67 bb       	sgt	r7
+
+0000002c <sle>:
+  2c:	78 bb       	sle	r8
+
+0000002e <sfs>:
+  2e:	89 bb       	sfs	r9
+
+00000030 <sfc>:
+  30:	9a bb       	sfc	r10
+
+00000032 <slo>:
+  32:	ab bb       	slo	r11
+
+00000034 <shs>:
+  34:	bc bb       	shs	r12
+
+00000036 <slt>:
+  36:	cd bb       	slt	r13
+
+00000038 <sge>:
+  38:	de bb       	sge	r14
diff --git a/gas/testsuite/gas/crx/jscond_insn.s b/gas/testsuite/gas/crx/jscond_insn.s
new file mode 100644
index 000000000000..f0659f1e7b3f
--- /dev/null
+++ b/gas/testsuite/gas/crx/jscond_insn.s
@@ -0,0 +1,121 @@
+# JCond/SCond instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global jeq
+jeq:
+jeq r1
+
+	.global jne
+jne:
+jne r2
+
+	.global jcs
+jcs:
+jcs r3
+
+	.global jcc
+jcc:
+jcc r4
+
+	.global jhi
+jhi:
+jhi r5
+
+	.global jls
+jls:
+jls r6
+
+	.global jgt
+jgt:
+jgt r7
+
+	.global jle
+jle:
+jle r8
+
+	.global jfs
+jfs:
+jfs r9
+
+	.global jfc
+jfc:
+jfc r10
+
+	.global jlo
+jlo:
+jlo r11
+
+	.global jhs
+jhs:
+jhs r12
+
+	.global jlt
+jlt:
+jlt r13
+
+	.global jge
+jge:
+jge ra
+
+	.global jump
+jump:
+jump sp
+
+	.global seq
+seq:
+seq r1
+
+	.global sne
+sne:
+sne r2
+
+	.global scs
+scs:
+scs r3
+
+	.global scc
+scc:
+scc r4
+
+	.global shi
+shi:
+shi r5
+
+	.global sls
+sls:
+sls r6
+
+	.global sgt
+sgt:
+sgt r7
+
+	.global sle
+sle:
+sle r8
+
+	.global sfs
+sfs:
+sfs r9
+
+	.global sfc
+sfc:
+sfc r10
+
+	.global slo
+slo:
+slo r11
+
+	.global shs
+shs:
+shs r12
+
+	.global slt
+slt:
+slt r13
+
+	.global sge
+sge:
+sge ra
diff --git a/gas/testsuite/gas/crx/list_insn.d b/gas/testsuite/gas/crx/list_insn.d
new file mode 100644
index 000000000000..b9b23fbc6d96
--- /dev/null
+++ b/gas/testsuite/gas/crx/list_insn.d
@@ -0,0 +1,39 @@
+#as:
+#objdump: -dr
+#name: list_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <push>:
+   0:	6e 34 18 00 	push	r14, {r3,r4}
+   4:	b2 ff       	push	r2
+
+00000006 <pushx>:
+   6:	7f 34 ff 00 	pushx	r15, {r0,r1,r2,r3,r4,r5,r6,r7}
+   a:	76 34 00 00 	pushx	r6, {lo,hi}
+
+0000000e <pop>:
+   e:	40 32 00 04 	loadm	r0, {r10}
+  12:	c2 ff       	pop	r2
+
+00000014 <popx>:
+  14:	7f 32 fb 00 	popx	r15, {r0,r1,r3,r4,r5,r6,r7}
+  18:	77 32 00 00 	popx	r7, {lo,hi}
+
+0000001c <popret>:
+  1c:	6d 32 02 40 	popret	r13, {r1,r14}
+  20:	de ff       	popret	r14
+
+00000022 <loadm>:
+  22:	40 32 42 00 	loadm	r0, {r1,r6}
+
+00000026 <loadma>:
+  26:	5d 32 14 10 	loadma	r13, {u2,u4,u12}
+
+0000002a <storm>:
+  2a:	4f 34 00 40 	storm	r15, {r14}
+
+0000002e <storma>:
+  2e:	53 34 05 00 	storma	r3, {u0,u2}
diff --git a/gas/testsuite/gas/crx/list_insn.s b/gas/testsuite/gas/crx/list_insn.s
new file mode 100644
index 000000000000..1b54aab47828
--- /dev/null
+++ b/gas/testsuite/gas/crx/list_insn.s
@@ -0,0 +1,47 @@
+# Instructions including a register list (opcode is represented as a mask).
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global push
+push:
+push ra, {r3, r4}
+push r2
+
+	.global pushx
+pushx:
+pushx sp, {r0, r1, r2, r3, r4, r5, r6, r7}
+pushx r6, {hi, lo}
+
+	.global pop
+pop:
+pop r0, {r10}
+pop r2
+
+	.global popx
+popx:
+popx sp, {r0, r1, r3, r4, r5, r6, r7}
+popx r7, {lo, hi}
+
+	.global popret
+popret:
+popret r13, {ra, r1}
+popret ra
+
+	.global loadm
+loadm:
+loadm r0, {r1, r6}
+
+	.global loadma
+loadma:
+loadma r13, {u12, u4, u2}
+
+	.global storm
+storm:
+storm r15, {ra}
+
+	.global storma
+storma:
+storma r3, {u0, u2}
+
diff --git a/gas/testsuite/gas/crx/load_stor_insn.d b/gas/testsuite/gas/crx/load_stor_insn.d
new file mode 100644
index 000000000000..fadf28780aa2
--- /dev/null
+++ b/gas/testsuite/gas/crx/load_stor_insn.d
@@ -0,0 +1,143 @@
+#as:
+#objdump: -dr
+#name: load_stor_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <loadb>:
+   0:	01 33 00 00 	loadb	0x632 [-_<>+0-9a-z]*, r1
+   4:	32 06 
+   6:	02 33 08 00 	loadb	0x87632 [-_<>+0-9a-z]*, r2
+   a:	32 76 
+   c:	03 32 34 12 	loadb	0xffff1234 [-_<>+0-9a-z]*, r3
+  10:	95 84       	loadb	0x9\(r5\), r4
+  12:	0f 86       	loadb	0x0\(r15\), r6
+  14:	e6 87 56 04 	loadb	0x456\(r6\), r7
+  18:	e8 8a aa fb 	loadb	0xfbaa\(r8\), r10
+  1c:	fd 8c 04 00 	loadb	0x45678\(r13\), r12
+  20:	78 56 
+  22:	f9 8f a9 fb 	loadb	0xfba9876e\(r9\), r15
+  26:	6e 87 
+  28:	8e 32 09 f0 	loadb	0x9\(r15\)\+, r14
+  2c:	82 32 de df 	loadb	0xfde\(r13\)\+, r2
+  30:	cd 33 40 9c 	loadb	0x45\(r9,r12,2\), r13
+  34:	45 00 
+  36:	ce 33 3f f7 	loadb	0x3ffd6f\(r15,r7,1\), r14
+  3a:	6f fd 
+
+0000003c <loadw>:
+  3c:	11 33 00 00 	loadw	0x19a [-_<>+0-9a-z]*, r1
+  40:	9a 01 
+  42:	12 33 01 00 	loadw	0x15650 [-_<>+0-9a-z]*, r2
+  46:	50 56 
+  48:	13 32 06 00 	loadw	0xffff0006 [-_<>+0-9a-z]*, r3
+  4c:	1f 94       	loadw	0x2\(r15\), r4
+  4e:	0f 96       	loadw	0x0\(r15\), r6
+  50:	e6 97 2e 01 	loadw	0x12e\(r6\), r7
+  54:	e8 9a 01 f8 	loadw	0xf801\(r8\), r10
+  58:	fd 9c 06 00 	loadw	0x6f855\(r13\), r12
+  5c:	55 f8 
+  5e:	f9 9f 00 ff 	loadw	0xff000000\(r9\), r15
+  62:	00 00 
+  64:	9e 32 08 20 	loadw	0x8\(r2\)\+, r14
+  68:	92 32 cc df 	loadw	0xfcc\(r13\)\+, r2
+  6c:	dd 33 80 9c 	loadw	0x25\(r9,r12,4\), r13
+  70:	25 00 
+  72:	de 33 ff f7 	loadw	0x3f99a9\(r15,r7,8\), r14
+  76:	a9 99 
+
+00000078 <loadd>:
+  78:	21 33 00 00 	loadd	0xfff1 [-_<>+0-9a-z]*, r1
+  7c:	f1 ff 
+  7e:	22 33 ef ff 	loadd	0xffefffef [-_<>+0-9a-z]*, r2
+  82:	ef ff 
+  84:	23 32 34 12 	loadd	0xffff1234 [-_<>+0-9a-z]*, r3
+  88:	e0 a4 0a 00 	loadd	0xa\(r0\), r4
+  8c:	0f a6       	loadd	0x0\(r15\), r6
+  8e:	e6 a7 00 01 	loadd	0x100\(r6\), r7
+  92:	e8 aa 00 ff 	loadd	0xff00\(r8\), r10
+  96:	fd ac 01 00 	loadd	0x12000\(r13\), r12
+  9a:	00 20 
+  9c:	f9 af ce ff 	loadd	0xffce0000\(r9\), r15
+  a0:	00 00 
+  a2:	ae 32 07 f0 	loadd	0x7\(r15\)\+, r14
+  a6:	a2 32 ce ef 	loadd	0xfce\(r14\)\+, r2
+  aa:	ed 33 40 9c 	loadd	0x2d\(r9,r12,2\), r13
+  ae:	2d 00 
+  b0:	ee 33 3f f7 	loadd	0x3ffe51\(r15,r7,1\), r14
+  b4:	51 fe 
+
+000000b6 <storb>:
+  b6:	01 35 00 00 	storb	r1, 0x632 [-_<>+0-9a-z]*
+  ba:	32 06 
+  bc:	02 35 08 00 	storb	r2, 0x87632 [-_<>+0-9a-z]*
+  c0:	32 76 
+  c2:	03 34 34 12 	storb	r3, 0xffff1234 [-_<>+0-9a-z]*
+  c6:	95 c4       	storb	r4, 0x9\(r5\)
+  c8:	0f c6       	storb	r6, 0x0\(r15\)
+  ca:	e6 c7 56 04 	storb	r7, 0x456\(r6\)
+  ce:	e8 ca aa fb 	storb	r10, 0xfbaa\(r8\)
+  d2:	fd cc 04 00 	storb	r12, 0x45678\(r13\)
+  d6:	78 56 
+  d8:	f9 cf a9 fb 	storb	r15, 0xfba9876e\(r9\)
+  dc:	6e 87 
+  de:	8e 34 09 f0 	storb	r14, 0x9\(r15\)\+
+  e2:	82 34 de df 	storb	r2, 0xfde\(r13\)\+
+  e6:	cd 35 40 9c 	storb	r13, 0x45\(r9,r12,2\)
+  ea:	45 00 
+  ec:	ce 35 3f f7 	storb	r14, 0x3ffd6f\(r15,r7,1\)
+  f0:	6f fd 
+  f2:	45 36 09 40 	storb	\$0x5, 0x9\(r4\)
+  f6:	4f 37 ff 3f 	storb	\$0xf, 0xffff013\(r3\)
+  fa:	13 f0 
+
+000000fc <storw>:
+  fc:	11 35 00 00 	storw	r1, 0x19a [-_<>+0-9a-z]*
+ 100:	9a 01 
+ 102:	12 35 01 00 	storw	r2, 0x15650 [-_<>+0-9a-z]*
+ 106:	50 56 
+ 108:	13 34 06 00 	storw	r3, 0xffff0006 [-_<>+0-9a-z]*
+ 10c:	1f d4       	storw	r4, 0x2\(r15\)
+ 10e:	0f d6       	storw	r6, 0x0\(r15\)
+ 110:	e6 d7 2e 01 	storw	r7, 0x12e\(r6\)
+ 114:	e8 da 01 f8 	storw	r10, 0xf801\(r8\)
+ 118:	fd dc 06 00 	storw	r12, 0x6f855\(r13\)
+ 11c:	55 f8 
+ 11e:	f9 df 00 ff 	storw	r15, 0xff000000\(r9\)
+ 122:	00 00 
+ 124:	9e 34 08 20 	storw	r14, 0x8\(r2\)\+
+ 128:	92 34 cc df 	storw	r2, 0xfcc\(r13\)\+
+ 12c:	dd 35 80 9c 	storw	r13, 0x25\(r9,r12,4\)
+ 130:	25 00 
+ 132:	de 35 ff f7 	storw	r14, 0x3f99a9\(r15,r7,8\)
+ 136:	a9 99 
+ 138:	11 37 00 00 	storw	\$0x1, 0x632 [-_<>+0-9a-z]*
+ 13c:	32 06 
+ 13e:	17 37 08 00 	storw	\$0x7, 0x87632 [-_<>+0-9a-z]*
+ 142:	32 76 
+
+00000144 <stord>:
+ 144:	21 35 00 00 	stord	r1, 0xfff1 [-_<>+0-9a-z]*
+ 148:	f1 ff 
+ 14a:	22 35 ef ff 	stord	r2, 0xffefffef [-_<>+0-9a-z]*
+ 14e:	ef ff 
+ 150:	23 34 01 00 	stord	r3, 0xffff0001 [-_<>+0-9a-z]*
+ 154:	e0 e4 0a 00 	stord	r4, 0xa\(r0\)
+ 158:	0f e6       	stord	r6, 0x0\(r15\)
+ 15a:	e6 e7 00 01 	stord	r7, 0x100\(r6\)
+ 15e:	e8 ea 00 ff 	stord	r10, 0xff00\(r8\)
+ 162:	fd ec 01 00 	stord	r12, 0x12000\(r13\)
+ 166:	00 20 
+ 168:	f9 ef ce ff 	stord	r15, 0xffce0000\(r9\)
+ 16c:	00 00 
+ 16e:	ae 34 07 f0 	stord	r14, 0x7\(r15\)\+
+ 172:	a2 34 ce ef 	stord	r2, 0xfce\(r14\)\+
+ 176:	ed 35 40 9c 	stord	r13, 0x2d\(r9,r12,2\)
+ 17a:	2d 00 
+ 17c:	ee 35 3f f7 	stord	r14, 0x3ffe51\(r15,r7,1\)
+ 180:	51 fe 
+ 182:	af 36 05 a0 	stord	\$0xf, 0x5\(r10\)\+
+ 186:	a0 36 e4 bf 	stord	\$0x0, 0xfe4\(r11\)\+
+
diff --git a/gas/testsuite/gas/crx/load_stor_insn.s b/gas/testsuite/gas/crx/load_stor_insn.s
new file mode 100644
index 000000000000..4c9fd41d24b9
--- /dev/null
+++ b/gas/testsuite/gas/crx/load_stor_insn.s
@@ -0,0 +1,110 @@
+# Load/Store instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+# Load instructions (memory to register).
+	.global loadb
+loadb:
+loadb 0x632, r1
+loadb 0x87632, r2
+loadb 0xffff1234, r3
+loadb 9(r5), r4
+loadb 0(sp), r6
+loadb 0x456(r6), r7
+loadb -0x456(r8), r10
+loadb 0x45678(r13), r12
+loadb -0x4567892(r9), sp
+loadb 0x9(sp)+, ra
+loadb -34(r13)+, r2
+loadb 0x45(r9,r12,2), r13
+loadb -657(r15,r7,1), r14
+
+	.global loadw
+loadw:
+loadw 0632, r1
+loadw 87632, r2
+loadw 0xffff0006, r3
+loadw 2(r15), r4
+loadw 0(sp), r6
+loadw 0456(r6), r7
+loadw -0x7ff(r8), r10
+loadw 456789(r13), r12
+loadw -16777216(r9), sp
+loadw 010(r2)+, ra
+loadw -0x34(r13)+, r2
+loadw 045(r9,r12,4), r13
+loadw -0x6657(r15,r7,8), r14
+
+	.global loadd
+loadd:
+loadd 0xfff1, r1
+loadd 0xffefffef, r2
+loadd 0xffff1234, r3
+loadd 10(r0), r4
+loadd 0(sp), r6
+loadd 0x100(r6), r7
+loadd -0x100(r8), r10
+loadd 0220000(r13), r12
+loadd -014400000(r9), sp
+loadd 07(sp)+, ra
+loadd -50(ra)+, r2
+loadd 45(r9,r12,2), r13
+loadd -0657(r15,r7,1), r14
+
+# Store instructions (register/immediate to memory).
+	.global storb
+storb:
+storb r1, 0x632
+storb r2, 0x87632
+storb r3, 0xffff1234
+storb r4, 9(r5)
+storb r6, 0(sp)
+storb r7, 0x456(r6)
+storb r10, -0x456(r8)
+storb r12, 0x45678(r13)
+storb sp, -0x4567892(r9)
+storb ra, 0x9(sp)+
+storb r2, -34(r13)+
+storb r13, 0x45(r9,r12,2)
+storb r14, -657(r15,r7,1)
+storb $5, 9(r4)
+storb $15, -0xfed(r3)
+
+	.global storw
+storw:
+storw r1, 0632
+storw r2, 87632
+storw r3, 0xffff0006
+storw r4, 2(r15)
+storw r6, 0(sp)
+storw r7, 0456(r6)
+storw r10, -0x7ff(r8)
+storw r12, 456789(r13)
+storw sp, -16777216(r9)
+storw ra, 010(r2)+
+storw r2, -0x34(r13)+
+storw r13, 045(r9,r12,4)
+storw r14, -0x6657(r15,r7,8)
+storw $01, 0x632
+storw $0x7, 0x87632
+
+	.global stord
+stord:
+stord r1, 0xfff1
+stord r2, 0xffefffef
+stord r3, 0xffff0001
+stord r4, 10(r0)
+stord r6, 0(sp)
+stord r7, 0x100(r6)
+stord r10, -0x100(r8)
+stord r12, 0220000(r13)
+stord sp, -014400000(r9)
+stord ra, 07(sp)+
+stord r2, -50(ra)+
+stord r13, 45(r9,r12,2)
+stord r14, -0657(r15,r7,1)
+stord $0xf, 05(r10)+
+stord $0x0, -034(r11)+
+
diff --git a/gas/testsuite/gas/crx/misc_insn.d b/gas/testsuite/gas/crx/misc_insn.d
new file mode 100644
index 000000000000..ea4c7c45ea30
--- /dev/null
+++ b/gas/testsuite/gas/crx/misc_insn.d
@@ -0,0 +1,233 @@
+#as:
+#objdump: -dr
+#name: misc_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <macsb>:
+   0:	08 30 01 40 	macsb	r0, r1
+
+00000004 <macub>:
+   4:	08 30 23 41 	macub	r2, r3
+
+00000008 <macqb>:
+   8:	08 30 45 42 	macqb	r4, r5
+
+0000000c <macsw>:
+   c:	08 30 67 50 	macsw	r6, r7
+
+00000010 <macuw>:
+  10:	08 30 89 51 	macuw	r8, r9
+
+00000014 <macqw>:
+  14:	08 30 ab 52 	macqw	r10, r11
+
+00000018 <macsd>:
+  18:	08 30 cd 60 	macsd	r12, r13
+
+0000001c <macud>:
+  1c:	08 30 ef 61 	macud	r14, r15
+
+00000020 <macqd>:
+  20:	08 30 ef 62 	macqd	r14, r15
+
+00000024 <mullsd>:
+  24:	08 30 02 65 	mullsd	r0, r2
+
+00000028 <mullud>:
+  28:	08 30 13 66 	mullud	r1, r3
+
+0000002c <mulsbw>:
+  2c:	08 30 46 3b 	mulsbw	r4, r6
+
+00000030 <mulubw>:
+  30:	08 30 57 3c 	mulubw	r5, r7
+
+00000034 <mulswd>:
+  34:	08 30 8a 3d 	mulswd	r8, r10
+
+00000038 <muluwd>:
+  38:	08 30 9b 3e 	muluwd	r9, r11
+
+0000003c <sextbw>:
+  3c:	08 30 ce 30 	sextbw	r12, r14
+
+00000040 <sextbd>:
+  40:	08 30 df 31 	sextbd	r13, r15
+
+00000044 <sextwd>:
+  44:	08 30 ef 32 	sextwd	r14, r15
+
+00000048 <zextbw>:
+  48:	08 30 50 34 	zextbw	r5, r0
+
+0000004c <zextbd>:
+  4c:	08 30 a6 35 	zextbd	r10, r6
+
+00000050 <zextwd>:
+  50:	08 30 7f 36 	zextwd	r7, r15
+
+00000054 <getrfid>:
+  54:	9e ff       	getrfid	r14
+
+00000056 <setrfid>:
+  56:	af ff       	setrfid	r15
+
+00000058 <bswap>:
+  58:	08 30 e2 3f 	bswap	r14, r2
+
+0000005c <maxsb>:
+  5c:	08 30 83 80 	maxsb	r8, r3
+
+00000060 <minsb>:
+  60:	08 30 fe 81 	minsb	r15, r14
+
+00000064 <maxub>:
+  64:	08 30 dc 82 	maxub	r13, r12
+
+00000068 <minub>:
+  68:	08 30 ba 83 	minub	r11, r10
+
+0000006c <absb>:
+  6c:	08 30 98 84 	absb	r9, r8
+
+00000070 <negb>:
+  70:	08 30 76 85 	negb	r7, r6
+
+00000074 <cntl0b>:
+  74:	08 30 54 86 	cntl0b	r5, r4
+
+00000078 <cntl1b>:
+  78:	08 30 32 87 	cntl1b	r3, r2
+
+0000007c <popcntb>:
+  7c:	08 30 10 88 	popcntb	r1, r0
+
+00000080 <rotlb>:
+  80:	08 30 b4 89 	rotlb	r11, r4
+
+00000084 <rotrb>:
+  84:	08 30 72 8a 	rotrb	r7, r2
+
+00000088 <mulqb>:
+  88:	08 30 ee 8b 	mulqb	r14, r14
+
+0000008c <addqb>:
+  8c:	08 30 ff 8c 	addqb	r15, r15
+
+00000090 <subqb>:
+  90:	08 30 0a 8d 	subqb	r0, r10
+
+00000094 <cntlsb>:
+  94:	08 30 2c 8e 	cntlsb	r2, r12
+
+00000098 <maxsw>:
+  98:	08 30 83 90 	maxsw	r8, r3
+
+0000009c <minsw>:
+  9c:	08 30 fe 91 	minsw	r15, r14
+
+000000a0 <maxuw>:
+  a0:	08 30 dc 92 	maxuw	r13, r12
+
+000000a4 <minuw>:
+  a4:	08 30 ba 93 	minuw	r11, r10
+
+000000a8 <absw>:
+  a8:	08 30 98 94 	absw	r9, r8
+
+000000ac <negw>:
+  ac:	08 30 76 95 	negw	r7, r6
+
+000000b0 <cntl0w>:
+  b0:	08 30 54 96 	cntl0w	r5, r4
+
+000000b4 <cntl1w>:
+  b4:	08 30 32 97 	cntl1w	r3, r2
+
+000000b8 <popcntw>:
+  b8:	08 30 10 98 	popcntw	r1, r0
+
+000000bc <rotlw>:
+  bc:	08 30 b4 99 	rotlw	r11, r4
+
+000000c0 <rotrw>:
+  c0:	08 30 72 9a 	rotrw	r7, r2
+
+000000c4 <mulqw>:
+  c4:	08 30 ee 9b 	mulqw	r14, r14
+
+000000c8 <addqw>:
+  c8:	08 30 ff 9c 	addqw	r15, r15
+
+000000cc <subqw>:
+  cc:	08 30 0a 9d 	subqw	r0, r10
+
+000000d0 <cntlsw>:
+  d0:	08 30 2c 9e 	cntlsw	r2, r12
+
+000000d4 <maxsd>:
+  d4:	08 30 83 a0 	maxsd	r8, r3
+
+000000d8 <minsd>:
+  d8:	08 30 fe a1 	minsd	r15, r14
+
+000000dc <maxud>:
+  dc:	08 30 dc a2 	maxud	r13, r12
+
+000000e0 <minud>:
+  e0:	08 30 ba a3 	minud	r11, r10
+
+000000e4 <absd>:
+  e4:	08 30 98 a4 	absd	r9, r8
+
+000000e8 <negd>:
+  e8:	08 30 76 a5 	negd	r7, r6
+
+000000ec <cntl0d>:
+  ec:	08 30 54 a6 	cntl0d	r5, r4
+
+000000f0 <cntl1d>:
+  f0:	08 30 32 a7 	cntl1d	r3, r2
+
+000000f4 <popcntd>:
+  f4:	08 30 10 a8 	popcntd	r1, r0
+
+000000f8 <rotld>:
+  f8:	08 30 b4 a9 	rotld	r11, r4
+
+000000fc <rotrd>:
+  fc:	08 30 72 aa 	rotrd	r7, r2
+
+00000100 <mulqd>:
+ 100:	08 30 ee ab 	mulqd	r14, r14
+
+00000104 <addqd>:
+ 104:	08 30 ff ac 	addqd	r15, r15
+
+00000108 <subqd>:
+ 108:	08 30 0a ad 	subqd	r0, r10
+
+0000010c <cntlsd>:
+ 10c:	08 30 2c ae 	cntlsd	r2, r12
+
+00000110 <excp>:
+ 110:	f8 ff       	excp	bpt
+ 112:	f5 ff       	excp	svc
+
+00000114 <ram>:
+ 114:	61 3e ec 21 	ram	\$0x18, \$0x9, \$0x1, r14, r12
+
+00000118 <rim>:
+ 118:	fd 3e 21 ee 	rim	\$0x1f, \$0xf, \$0xe, r2, r1
+
+0000011c <rotb>:
+ 11c:	f1 fd       	rotb	\$0x7, r1
+
+0000011e <rotw>:
+ 11e:	d3 b9       	rotw	\$0xd, r3
+
+00000120 <rotd>:
+ 120:	08 30 b2 f1 	rotd	\$0x1b, r2
diff --git a/gas/testsuite/gas/crx/misc_insn.s b/gas/testsuite/gas/crx/misc_insn.s
new file mode 100644
index 000000000000..2330d4cd2b9f
--- /dev/null
+++ b/gas/testsuite/gas/crx/misc_insn.s
@@ -0,0 +1,312 @@
+# Miscellaneous instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+# Multiply instructions.
+	.global macsb
+macsb:
+macsb r0 , r1
+
+	.global macub
+macub:
+macub r2 , r3
+
+	.global macqb
+macqb:
+macqb r4 , r5
+
+	.global macsw
+macsw:
+macsw r6 , r7
+
+	.global macuw
+macuw:
+macuw r8 , r9
+
+	.global macqw
+macqw:
+macqw r10 , r11
+
+	.global macsd
+macsd:
+macsd r12 , r13
+
+	.global macud
+macud:
+macud r14 , r15
+
+	.global macqd
+macqd:
+macqd ra , sp
+
+	.global mullsd
+mullsd:
+mullsd r0 , r2
+
+	.global mullud
+mullud:
+mullud r1 , r3
+
+	.global mulsbw
+mulsbw:
+mulsbw r4 , r6
+
+	.global mulubw
+mulubw:
+mulubw r5 , r7
+
+	.global mulswd
+mulswd:
+mulswd r8 , r10
+
+	.global muluwd
+muluwd:
+muluwd r9 , r11
+
+# Signextend instructions.
+	.global sextbw
+sextbw:
+sextbw r12 , ra
+
+	.global sextbd
+sextbd:
+sextbd r13 , sp
+
+	.global sextwd
+sextwd:
+sextwd r14 , r15
+
+	.global zextbw
+zextbw:
+zextbw r5 , r0
+
+	.global zextbd
+zextbd:
+zextbd r10 , r6
+
+	.global zextwd
+zextwd:
+zextwd r7 , r15
+
+# Misc. instructions.
+
+	.global getrfid
+getrfid:
+getrfid r14
+
+	.global setrfid
+setrfid:
+setrfid sp
+
+	.global bswap
+bswap:
+bswap r14 , r2
+
+	.global maxsb
+maxsb:
+maxsb r8 , r3
+
+	.global minsb
+minsb:
+minsb r15 , r14
+
+	.global maxub
+maxub:
+maxub r13 , r12
+
+	.global minub
+minub:
+minub r11 , r10
+
+	.global absb
+absb:
+absb r9 , r8
+
+	.global negb
+negb:
+negb r7 , r6
+
+	.global cntl0b
+cntl0b:
+cntl0b r5 , r4
+
+	.global cntl1b
+cntl1b:
+cntl1b r3 , r2
+
+	.global popcntb
+popcntb:
+popcntb r1 , r0
+
+	.global rotlb
+rotlb:
+rotlb r11 , r4
+
+	.global rotrb
+rotrb:
+rotrb r7 , r2
+
+	.global mulqb
+mulqb:
+mulqb r14 , ra
+
+	.global addqb
+addqb:
+addqb r15 , sp
+
+	.global subqb
+subqb:
+subqb r0 , r10
+
+	.global cntlsb
+cntlsb:
+cntlsb r2 , r12
+
+	.global maxsw
+maxsw:
+maxsw r8 , r3
+
+	.global minsw
+minsw:
+minsw r15 , r14
+
+	.global maxuw
+maxuw:
+maxuw r13 , r12
+
+	.global minuw
+minuw:
+minuw r11 , r10
+
+	.global absw
+absw:
+absw r9 , r8
+
+	.global negw
+negw:
+negw r7 , r6
+
+	.global cntl0w
+cntl0w:
+cntl0w r5 , r4
+
+	.global cntl1w
+cntl1w:
+cntl1w r3 , r2
+
+	.global popcntw
+popcntw:
+popcntw r1 , r0
+
+	.global rotlw
+rotlw:
+rotlw r11 , r4
+
+	.global rotrw
+rotrw:
+rotrw r7 , r2
+
+	.global mulqw
+mulqw:
+mulqw r14 , ra
+
+	.global addqw
+addqw:
+addqw r15 , sp
+
+	.global subqw
+subqw:
+subqw r0 , r10
+
+	.global cntlsw
+cntlsw:
+cntlsw r2 , r12
+
+	.global maxsd
+maxsd:
+maxsd r8 , r3
+
+	.global minsd
+minsd:
+minsd r15 , r14
+
+	.global maxud
+maxud:
+maxud r13 , r12
+
+	.global minud
+minud:
+minud r11 , r10
+
+	.global absd
+absd:
+absd r9 , r8
+
+	.global negd
+negd:
+negd r7 , r6
+
+	.global cntl0d
+cntl0d:
+cntl0d r5 , r4
+
+	.global cntl1d
+cntl1d:
+cntl1d r3 , r2
+
+	.global popcntd
+popcntd:
+popcntd r1 , r0
+
+	.global rotld
+rotld:
+rotld r11 , r4
+
+	.global rotrd
+rotrd:
+rotrd r7 , r2
+
+	.global mulqd
+mulqd:
+mulqd r14 , ra
+
+	.global addqd
+addqd:
+addqd r15 , sp
+
+	.global subqd
+subqd:
+subqd r0 , r10
+
+	.global cntlsd
+cntlsd:
+cntlsd r2 , r12
+
+	.global excp
+excp:
+excp BPT
+excp svc
+
+	.global ram
+ram:
+ram $24, $9, $1, ra, r12
+
+	.global rim
+rim:
+rim $0x1f, $0xf, $0xe, r2, r1
+
+	.global rotb
+rotb:
+rotb $7, r1
+
+	.global rotw
+rotw:
+rotw $13, r3
+
+	.global rotd
+rotd:
+rotd $27, r2
+
+
diff --git a/gas/testsuite/gas/crx/no_op_insn.d b/gas/testsuite/gas/crx/no_op_insn.d
new file mode 100644
index 000000000000..7e8a549782b8
--- /dev/null
+++ b/gas/testsuite/gas/crx/no_op_insn.d
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dr
+#name: no_op_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <nop>:
+   0:	02 30       	nop
+
+00000002 <retx>:
+   2:	03 30       	retx
+
+00000004 <di>:
+   4:	04 30       	di
+
+00000006 <ei>:
+   6:	05 30       	ei
+
+00000008 <wait>:
+   8:	06 30       	wait
+
+0000000a <eiwait>:
+   a:	07 30       	eiwait
diff --git a/gas/testsuite/gas/crx/no_op_insn.s b/gas/testsuite/gas/crx/no_op_insn.s
new file mode 100644
index 000000000000..8090c929ee7f
--- /dev/null
+++ b/gas/testsuite/gas/crx/no_op_insn.s
@@ -0,0 +1,29 @@
+# Instruction with no operands.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global nop
+nop:
+nop
+
+	.global retx
+retx:
+retx
+
+	.global di
+di:
+di
+
+	.global ei
+ei:
+ei
+
+	.global wait
+wait:
+wait
+
+	.global eiwait
+eiwait:
+eiwait
diff --git a/gas/testsuite/gas/crx/shift_insn.d b/gas/testsuite/gas/crx/shift_insn.d
new file mode 100644
index 000000000000..484932fd5412
--- /dev/null
+++ b/gas/testsuite/gas/crx/shift_insn.d
@@ -0,0 +1,43 @@
+#as:
+#objdump: -dr
+#name: shift_insn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <sllb>:
+   0:	71 fc       	sllb	\$0x7, r1
+   2:	23 4d       	sllb	r2, r3
+
+00000004 <srlb>:
+   4:	d4 fc       	srlb	\$0x5, r4
+   6:	56 4e       	srlb	r5, r6
+
+00000008 <srab>:
+   8:	47 fd       	srab	\$0x4, r7
+   a:	89 4f       	srab	r8, r9
+
+0000000c <sllw>:
+   c:	fa b6       	sllw	\$0xf, r10
+   e:	bc 5d       	sllw	r11, r12
+
+00000010 <srlw>:
+  10:	ed b7       	srlw	\$0xe, r13
+  12:	ef 5e       	srlw	r14, r15
+
+00000014 <sraw>:
+  14:	de b8       	sraw	\$0xd, r14
+  16:	f1 5f       	sraw	r15, r1
+
+00000018 <slld>:
+  18:	f2 f1       	slld	\$0x1f, r2
+  1a:	34 6d       	slld	r3, r4
+
+0000001c <srld>:
+  1c:	f5 f3       	srld	\$0x1f, r5
+  1e:	67 6e       	srld	r6, r7
+
+00000020 <srad>:
+  20:	28 f5       	srad	\$0x12, r8
+  22:	9a 6f       	srad	r9, r10
diff --git a/gas/testsuite/gas/crx/shift_insn.s b/gas/testsuite/gas/crx/shift_insn.s
new file mode 100644
index 000000000000..63503d1a84ff
--- /dev/null
+++ b/gas/testsuite/gas/crx/shift_insn.s
@@ -0,0 +1,51 @@
+# Shift instructions.
+ .data
+foodata: .word 42
+	 .text
+footext:
+
+	.global sllb
+sllb:
+sllb $7 , r1
+sllb r2 , r3
+
+	.global srlb
+srlb:
+srlb $0x5 , r4
+srlb r5 , r6
+
+	.global srab
+srab:
+srab $04 , r7
+srab r8 , r9
+
+	.global sllw
+sllw:
+sllw $15 , r10
+sllw r11 , r12
+
+	.global srlw
+srlw:
+srlw $0xe , r13
+srlw r14 , r15
+
+	.global sraw
+sraw:
+sraw $015 , ra
+sraw sp , r1
+
+	.global slld
+slld:
+slld $31 , r2
+slld r3 , r4
+
+	.global srld
+srld:
+srld $0x1f , r5
+srld r6 , r7
+
+	.global srad
+srad:
+srad $022 , r8
+srad r9 , r10
+
diff --git a/gas/testsuite/gas/d10v/instruction_packing-005.d b/gas/testsuite/gas/d10v/instruction_packing-005.d
index 71ed975fc9dd..0129b7140aa2 100644
--- a/gas/testsuite/gas/d10v/instruction_packing-005.d
+++ b/gas/testsuite/gas/d10v/instruction_packing-005.d
@@ -25,5 +25,5 @@ Disassembly of section .text:
 Disassembly of section .data:
 
 00000000 <in_data>:
-   0:	Address 0x0 is out of bounds.
+   0:	Address 0x0+ is out of bounds.
 
diff --git a/gas/testsuite/gas/d10v/instruction_packing-008.d b/gas/testsuite/gas/d10v/instruction_packing-008.d
index 22db4809d2e8..1845950fdb7b 100644
--- a/gas/testsuite/gas/d10v/instruction_packing-008.d
+++ b/gas/testsuite/gas/d10v/instruction_packing-008.d
@@ -12,3 +12,4 @@ Disassembly of section .text:
    8:	60 22 c0 67 	ldi.s	r2, 0x2	->	ldi.s	r3, 0x3
    c:	e0 40 40 00 	ldi.l	r4, 0x4000
   10:	60 55 cc 1a 	ldi.s	r5, 0x5	->	jmp	r13
+#pass
diff --git a/gas/testsuite/gas/d10v/instruction_packing-009.d b/gas/testsuite/gas/d10v/instruction_packing-009.d
index 327ea3e5da43..b81df4f1b9e0 100644
--- a/gas/testsuite/gas/d10v/instruction_packing-009.d
+++ b/gas/testsuite/gas/d10v/instruction_packing-009.d
@@ -14,3 +14,4 @@ Disassembly of section .text:
   10:	e0 40 40 00 	ldi.l	r4, 0x4000
   14:	20 55 de 00 	ldi.s	r5, 0x5	||	nop	
   18:	26 0d 5e 00 	jmp	r13	||	nop	
+#pass
diff --git a/gas/testsuite/gas/d10v/instruction_packing-010.d b/gas/testsuite/gas/d10v/instruction_packing-010.d
index aba360e607f8..227540191e38 100644
--- a/gas/testsuite/gas/d10v/instruction_packing-010.d
+++ b/gas/testsuite/gas/d10v/instruction_packing-010.d
@@ -12,3 +12,4 @@ Disassembly of section .text:
    8:	60 22 c0 67 	ldi.s	r2, 0x2	->	ldi.s	r3, 0x3
    c:	e0 40 40 00 	ldi.l	r4, 0x4000
   10:	60 55 cc 1a 	ldi.s	r5, 0x5	->	jmp	r13
+#pass
diff --git a/gas/testsuite/gas/d10v/warning-001.d b/gas/testsuite/gas/d10v/warning-001.d
index 5ef473c36e2e..1f120426edf8 100644
--- a/gas/testsuite/gas/d10v/warning-001.d
+++ b/gas/testsuite/gas/d10v/warning-001.d
@@ -1,2 +1,2 @@
 #source: warning-001.s
-#error : cr6 is a reserved control register
+#warning : cr6 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-002.d b/gas/testsuite/gas/d10v/warning-002.d
index c331e6915159..c62eae69b6e7 100644
--- a/gas/testsuite/gas/d10v/warning-002.d
+++ b/gas/testsuite/gas/d10v/warning-002.d
@@ -1,2 +1,2 @@
 #source: warning-002.s
-#error : cr6 is a reserved control register
+#warning : cr6 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-003.d b/gas/testsuite/gas/d10v/warning-003.d
index 4282e13b0de3..e155d561b1d0 100644
--- a/gas/testsuite/gas/d10v/warning-003.d
+++ b/gas/testsuite/gas/d10v/warning-003.d
@@ -1,2 +1,2 @@
 #source: warning-003.s
-#error : cr12 is a reserved control register
+#warning : cr12 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-004.d b/gas/testsuite/gas/d10v/warning-004.d
index 193a843277e7..46f8e2eb8a1d 100644
--- a/gas/testsuite/gas/d10v/warning-004.d
+++ b/gas/testsuite/gas/d10v/warning-004.d
@@ -1,2 +1,2 @@
 #source: warning-004.s
-#error : cr12 is a reserved control register
+#warning : cr12 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-005.d b/gas/testsuite/gas/d10v/warning-005.d
index 77592712a2cd..4fcae03d9acb 100644
--- a/gas/testsuite/gas/d10v/warning-005.d
+++ b/gas/testsuite/gas/d10v/warning-005.d
@@ -1,2 +1,2 @@
 #source: warning-005.s
-#error : Warning: cr13 is a reserved control register
+#warning : Warning: cr13 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-006.d b/gas/testsuite/gas/d10v/warning-006.d
index 50656fb797ca..e398fd97b644 100644
--- a/gas/testsuite/gas/d10v/warning-006.d
+++ b/gas/testsuite/gas/d10v/warning-006.d
@@ -1,2 +1,2 @@
 #source: warning-006.s
-#error : cr13 is a reserved control register
+#warning : cr13 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-007.d b/gas/testsuite/gas/d10v/warning-007.d
index 1ab4879dd235..b5b92e88b59b 100644
--- a/gas/testsuite/gas/d10v/warning-007.d
+++ b/gas/testsuite/gas/d10v/warning-007.d
@@ -1,2 +1,2 @@
 #source: warning-007.s
-#error : Warning: cr13 is a reserved control register
+#warning : Warning: cr13 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-008.d b/gas/testsuite/gas/d10v/warning-008.d
index 30211ab29778..911934b95800 100644
--- a/gas/testsuite/gas/d10v/warning-008.d
+++ b/gas/testsuite/gas/d10v/warning-008.d
@@ -1,2 +1,2 @@
 #source: warning-008.s
-#error : cr15 is a reserved control register
+#warning : cr15 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-009.d b/gas/testsuite/gas/d10v/warning-009.d
index 695fc77b9caf..b11666ca6b36 100644
--- a/gas/testsuite/gas/d10v/warning-009.d
+++ b/gas/testsuite/gas/d10v/warning-009.d
@@ -1,2 +1,2 @@
 #source: warning-009.s
-#error : cr15 is a reserved control register
+#warning : cr15 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-010.d b/gas/testsuite/gas/d10v/warning-010.d
index 44e1e30e515d..d5825c671e47 100644
--- a/gas/testsuite/gas/d10v/warning-010.d
+++ b/gas/testsuite/gas/d10v/warning-010.d
@@ -1,2 +1,2 @@
 #source: warning-010.s
-#error : cr4 is a reserved control register
+#warning : cr4 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-011.d b/gas/testsuite/gas/d10v/warning-011.d
index 12a3c04bcd19..cf1a54b59a07 100644
--- a/gas/testsuite/gas/d10v/warning-011.d
+++ b/gas/testsuite/gas/d10v/warning-011.d
@@ -1,2 +1,2 @@
 #source: warning-011.s
-#error : cr4 is a reserved control register
+#warning : cr4 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-012.d b/gas/testsuite/gas/d10v/warning-012.d
index 2e4dcbb8feb5..8a17f47a0226 100644
--- a/gas/testsuite/gas/d10v/warning-012.d
+++ b/gas/testsuite/gas/d10v/warning-012.d
@@ -1,2 +1,2 @@
 #source: warning-012.s
-#error : cr5 is a reserved control register
+#warning : cr5 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-013.d b/gas/testsuite/gas/d10v/warning-013.d
index 86754289f436..6da2bb3d6032 100644
--- a/gas/testsuite/gas/d10v/warning-013.d
+++ b/gas/testsuite/gas/d10v/warning-013.d
@@ -1,2 +1,2 @@
 #source: warning-013.s
-#error : cr5 is a reserved control register
+#warning : cr5 is a reserved control register
diff --git a/gas/testsuite/gas/d10v/warning-015.d b/gas/testsuite/gas/d10v/warning-015.d
index ff4a97ca994b..6725d012b71f 100644
--- a/gas/testsuite/gas/d10v/warning-015.d
+++ b/gas/testsuite/gas/d10v/warning-015.d
@@ -1,2 +1,2 @@
 #source: instruction_packing-002.s
-#error : Warning: resource conflict \(C flag\)
+#warning : Warning: resource conflict \(C flag\)
diff --git a/gas/testsuite/gas/d10v/warning-016.d b/gas/testsuite/gas/d10v/warning-016.d
index f833369cc327..cd19f0fb5b1e 100644
--- a/gas/testsuite/gas/d10v/warning-016.d
+++ b/gas/testsuite/gas/d10v/warning-016.d
@@ -1,2 +1,2 @@
 #source: warning-016.s
-#error : Warning: resource conflict \(F flag\)
+#warning : Warning: resource conflict \(F flag\)
diff --git a/gas/testsuite/gas/d10v/warning-017.d b/gas/testsuite/gas/d10v/warning-017.d
index a8aed683c213..34134cc97198 100644
--- a/gas/testsuite/gas/d10v/warning-017.d
+++ b/gas/testsuite/gas/d10v/warning-017.d
@@ -1,2 +1,2 @@
 #source: warning-017.s
-#error : Warning: resource conflict \(C flag\)
+#warning : Warning: resource conflict \(C flag\)
diff --git a/gas/testsuite/gas/d10v/warning-018.d b/gas/testsuite/gas/d10v/warning-018.d
index 40b1106182ee..5c5e7108cae5 100644
--- a/gas/testsuite/gas/d10v/warning-018.d
+++ b/gas/testsuite/gas/d10v/warning-018.d
@@ -1,2 +1,2 @@
 #source: warning-018.s
-#error : Warning: resource conflict \(C flag\)
+#warning : Warning: resource conflict \(C flag\)
diff --git a/gas/testsuite/gas/d10v/warning-019.d b/gas/testsuite/gas/d10v/warning-019.d
index 638875188774..cf05c54e89d6 100644
--- a/gas/testsuite/gas/d10v/warning-019.d
+++ b/gas/testsuite/gas/d10v/warning-019.d
@@ -1,2 +1,2 @@
 #source: warning-019.s
-#error : Warning: resource conflict \(R0\)
+#warning : Warning: resource conflict \(R0\)
diff --git a/gas/testsuite/gas/d30v/serial.l b/gas/testsuite/gas/d30v/serial.l
index f7a5a670766f..84b475d3c063 100644
--- a/gas/testsuite/gas/d30v/serial.l
+++ b/gas/testsuite/gas/d30v/serial.l
@@ -11,12 +11,9 @@ GAS LISTING .*
    3              	# In the following examples, the right-subinstructions
    4              	# will never be executed.  GAS should detect this.
    5              		
-   6 \?\?\?\? 000000F0 		trap r21 -> add r2, r0, r0 ; right instruction will never be executed.
+   6 \?\?\?\? ........ 		trap r21 -> add r2, r0, r0 ; right instruction will never be executed.
 \*\*\*\*  Error:Unable to mix instructions as specified
-   6      000000F0 
-   6      000000F0 
-   6      00000090 
-   6      001500F0 
+   6      ........ 
    7 \?\?\?\? 08002000 		dbt     -> add r2, r0, r0               ; ditto
 \*\*\*\*  Error:Unable to mix instructions as specified
    7      00F00000 
diff --git a/gas/testsuite/gas/d30v/serial2.l b/gas/testsuite/gas/d30v/serial2.l
index 2de04dc2dbb2..3dc2652dacf0 100644
--- a/gas/testsuite/gas/d30v/serial2.l
+++ b/gas/testsuite/gas/d30v/serial2.l
@@ -26,12 +26,9 @@ GAS LISTING .*
    2              		
    3              		.text
    4              		
-   5 \?\?\?\? 000000F0 		bra -3 -> add r3,r0,0	; Invalid
+   5 \?\?\?\? ........ 		bra -3 -> add r3,r0,0	; Invalid
 \*\*\*\*  Error:Unable to mix instructions as specified
-   5      000000F0 
-   5      000000F0 
-   5      0000000B 
-   5      FFFF00F0 
+   5      ........ 
    6 \?\?\?\? 08083000 		bsr -3 -> add r3,r0,0	; Invalid
 \*\*\*\*  Error:Unable to mix instructions as specified
    6      00F00000 
@@ -79,13 +76,13 @@ GAS LISTING .*
 \*\*\*\*  Error:Unable to mix instructions as specified
   17      00F00000 
   17      000BFFFF 
-GAS LISTING .*
-
-
   17      00F00000 
   18 \?\?\?\? 10080001 		bra/tx -3 -> bra 10     ;      Valid
 \*\*\*\*  Error:Unable to mix instructions as specified
   18      00F00000 
+GAS LISTING .*
+
+
   18      100BFFFF 
   18      00F00000 
   19 \?\?\?\? 00080001 		bra/tx -3 -> bra/fx 10  ;      Valid
diff --git a/gas/testsuite/gas/d30v/serial2O.l b/gas/testsuite/gas/d30v/serial2O.l
index d9eb05cb1a92..dc5b9c785741 100644
--- a/gas/testsuite/gas/d30v/serial2O.l
+++ b/gas/testsuite/gas/d30v/serial2O.l
@@ -16,12 +16,9 @@ GAS LISTING .*
    2              		
    3              		.text
    4              		
-   5 \?\?\?\? 000000F0 		bra -3 -> add r3,r0,0	; Invalid
+   5 \?\?\?\? ........ 		bra -3 -> add r3,r0,0	; Invalid
 \*\*\*\*  Error:Unable to mix instructions as specified
-   5      000000F0 
-   5      000000F0 
-   5      0000000B 
-   5      FFFF00F0 
+   5      ........ 
    6 \?\?\?\? 08083000 		bsr -3 -> add r3,r0,0	; Invalid
 \*\*\*\*  Error:Unable to mix instructions as specified
    6      00F00000 
@@ -69,12 +66,12 @@ GAS LISTING .*
 \*\*\*\*  Error:Unable to mix instructions as specified
   21      00F00000 
   22 \?\?\?\? 00080001 		bsr -3 -> bra/tx 10     ;      Invalid
-GAS LISTING .*
-
-
 \*\*\*\*  Error:Unable to mix instructions as specified
   22      00F00000 
   22      002BFFFF 
+GAS LISTING .*
+
+
   22      00F00000 
   23 \?\?\?\? 10080001 		bsr/tx -3 -> bra 10     ;      Valid
   23      00F00000 
diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp
index f4274822ac60..43265d0d2fae 100644
--- a/gas/testsuite/gas/elf/elf.exp
+++ b/gas/testsuite/gas/elf/elf.exp
@@ -2,7 +2,7 @@
 # elf tests
 #
 
-proc run_list_test { name suffix opts readelf_pipe } {
+proc run_list_test { name suffix opts readelf_opts readelf_pipe } {
     global READELF
     global srcdir subdir
     set testname "elf $name list"
@@ -14,8 +14,8 @@ proc run_list_test { name suffix opts readelf_pipe } {
 	verbose "output is [file_contents "dump.out"]" 2
 	return
     }
-    send_log "$READELF -s dump.o > dump.out\n"
-    catch "exec $READELF -s dump.o $readelf_pipe > dump.out\n" comp_output
+    send_log "$READELF $readelf_opts dump.o $readelf_pipe > dump.out\n"
+    catch "exec $READELF $readelf_opts dump.o $readelf_pipe > dump.out\n" comp_output
     if ![string match "" $comp_output] then {
 	send_log "$comp_output\n"
 	fail $testname
@@ -31,10 +31,13 @@ proc run_list_test { name suffix opts readelf_pipe } {
 }
 
 # We're testing bits in obj-elf -- don't run on anything else.
-if { ([istarget "*-*-elf*"]		
+if { ([istarget "*-*-*elf*"]		
       || [istarget "*-*-linux*"]
+      || [istarget "m6811-*"]
+      || [istarget "m6812-*"]
       || [istarget "sparc*-*-solaris*"]
-      || [istarget "mips*-*-irix6*"])
+      || [istarget "mips*-*-irix6*"]
+      || [istarget "arm*-*-eabi"])
      && ![istarget *-*-linux*aout*]
      && ![istarget *-*-linux*coff*]
      && ![istarget *-*-linux*oldld*]
@@ -47,11 +50,34 @@ if { ([istarget "*-*-elf*"]
     if {[istarget m32r*-*-*]} then {
 	set target_machine -m32r
     }
+    if { ([istarget "*arm*-*-*"]
+	  || [istarget "xscale*-*-*"])
+	&& ([istarget "*-*-*eabi"]
+	    || [istarget "*-*-symbianelf"])} then {
+	set target_machine -armeabi
+    }
     run_dump_test "ehopt0"
+    run_dump_test "group0a" 
+    run_dump_test "group0b" 
+    run_dump_test "group1a" 
+    run_dump_test "group1b" 
+    case $target_triplet in {
+	{ alpha*-*-* } { }
+	{ hppa*-*-* } { }
+	{ iq2000*-*-* } { }
+	{ mips*-*-* } { }
+	{ *c54x*-*-* } { }
+	default {
+	    run_dump_test redef
+	}
+    }
     run_dump_test "section0" 
     run_dump_test "section1" 
-    run_list_test "section2" "$target_machine" "-al" ""
+    run_list_test "section2" "$target_machine" "-al" "-s" ""
     run_dump_test "section3" 
+    run_dump_test "section4"
+    run_list_test "section5" "" "-al" "-SW" "| grep \" \\\\.test\\\[0-9\\\]\""
+    run_dump_test "struct" 
     run_dump_test "symver" 
-    run_list_test "type" "" "" "| grep \"1 \\\[FONT\\\]\""
+    run_list_test "type" "" "" "-s" "| grep \"1 \\\[FONT\\\]\""
 }
diff --git a/gas/testsuite/gas/elf/group0.s b/gas/testsuite/gas/elf/group0.s
new file mode 100644
index 000000000000..4707c69e5310
--- /dev/null
+++ b/gas/testsuite/gas/elf/group0.s
@@ -0,0 +1,4 @@
+	.section       .foo,"axG",%progbits,.foo_group,comdat
+	.byte	1
+	.section       .bar,"aG",%progbits,.foo_group,comdat
+	.byte	1
diff --git a/gas/testsuite/gas/elf/group0a.d b/gas/testsuite/gas/elf/group0a.d
new file mode 100644
index 000000000000..8aedc0caa4f9
--- /dev/null
+++ b/gas/testsuite/gas/elf/group0a.d
@@ -0,0 +1,10 @@
+#readelf: -SW
+#name: group section
+#source: group0.s
+
+#...
+[ 	]*\[.*\][ 	]+\.foo_group[ 	]+GROUP.*
+#...
+[ 	]*\[.*\][ 	]+\.foo[ 	]+PROGBITS.*[ 	]+AXG[ 	]+.*
+[ 	]*\[.*\][ 	]+\.bar[ 	]+PROGBITS.*[ 	]+AG[ 	]+.*
+#pass
diff --git a/gas/testsuite/gas/elf/group0b.d b/gas/testsuite/gas/elf/group0b.d
new file mode 100644
index 000000000000..803b8ec797b6
--- /dev/null
+++ b/gas/testsuite/gas/elf/group0b.d
@@ -0,0 +1,10 @@
+#readelf: -g
+#name: group section
+#source: group0.s
+
+#...
+COMDAT group section \[    1\] `.foo_group' \[.foo_group\] contains 2 sections:
+[ 	]+\[Index\][ 	]+Name
+[ 	]+\[.*\][ 	]+.foo
+[ 	]+\[.*\][ 	]+.bar
+#pass
diff --git a/gas/testsuite/gas/elf/group1.s b/gas/testsuite/gas/elf/group1.s
new file mode 100644
index 000000000000..f02f15069298
--- /dev/null
+++ b/gas/testsuite/gas/elf/group1.s
@@ -0,0 +1,2 @@
+	.section       .text,"axG",%progbits,.foo_group,comdat
+	.byte	1
diff --git a/gas/testsuite/gas/elf/group1a.d b/gas/testsuite/gas/elf/group1a.d
new file mode 100644
index 000000000000..a5b329875748
--- /dev/null
+++ b/gas/testsuite/gas/elf/group1a.d
@@ -0,0 +1,11 @@
+#readelf: -SW
+#name: group section with multiple sections of same name
+#source: group1.s
+
+#...
+[ 	]*\[.*\][ 	]+\.foo_group[ 	]+GROUP.*
+#...
+[ 	]*\[.*\][ 	]+\.text[ 	]+PROGBITS.*[ 	]+AX[ 	]+.*
+#...
+[ 	]*\[.*\][ 	]+\.text[ 	]+PROGBITS.*[ 	]+AXG[ 	]+.*
+#pass
diff --git a/gas/testsuite/gas/elf/group1b.d b/gas/testsuite/gas/elf/group1b.d
new file mode 100644
index 000000000000..704752ba6a36
--- /dev/null
+++ b/gas/testsuite/gas/elf/group1b.d
@@ -0,0 +1,9 @@
+#readelf: -g
+#name: group section with multiple sections of same name
+#source: group1.s
+
+#...
+COMDAT group section \[    1\] `.foo_group' \[.foo_group\] contains 1 sections:
+[ 	]+\[Index\][ 	]+Name
+[ 	]+\[.*\][ 	]+.text
+#pass
diff --git a/gas/testsuite/gas/elf/redef.d b/gas/testsuite/gas/elf/redef.d
new file mode 100644
index 000000000000..6e5daeabc36b
--- /dev/null
+++ b/gas/testsuite/gas/elf/redef.d
@@ -0,0 +1,13 @@
+#objdump: -t
+#name: .equ redefinitions (ELF)
+
+.*: .*
+
+SYMBOL TABLE:
+#...
+0+[ 	]+l[ 	].*[ 	]here
+#...
+0*2+[ 	]+l[ 	]+\*ABS\*[ 	].*[ 	]sym
+#...
+0+[ 	]+\*UND\*[ 	].*[ 	]xtrn
+#...
diff --git a/gas/testsuite/gas/elf/redef.s b/gas/testsuite/gas/elf/redef.s
new file mode 100644
index 000000000000..3e975e137280
--- /dev/null
+++ b/gas/testsuite/gas/elf/redef.s
@@ -0,0 +1,10 @@
+ .data
+here:
+ .set sym, here
+ .long sym
+ .set sym, 0x11111111
+ .long sym
+ .set sym, xtrn
+ .long sym
+ .set sym, 0x22222222
+ .long sym
diff --git a/gas/testsuite/gas/elf/section0.d b/gas/testsuite/gas/elf/section0.d
index 286327cad6d3..6978d0a23d19 100644
--- a/gas/testsuite/gas/elf/section0.d
+++ b/gas/testsuite/gas/elf/section0.d
@@ -13,3 +13,5 @@ Contents of section B:
  0+000 02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02.*
 Contents of section C:
  0+000 03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03.*
+# Arm includes a .ARM.attributes section here
+#...
diff --git a/gas/testsuite/gas/elf/section1.d b/gas/testsuite/gas/elf/section1.d
index 4084752a907e..c6b7fd482766 100644
--- a/gas/testsuite/gas/elf/section1.d
+++ b/gas/testsuite/gas/elf/section1.d
@@ -13,3 +13,5 @@ Contents of section B:
  0+000 02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02 ?02.*
 Contents of section C:
  0+000 03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03 ?03.*
+# Arm includes a .ARM.attributes section here
+#...
diff --git a/gas/testsuite/gas/elf/section2.e-armeabi b/gas/testsuite/gas/elf/section2.e-armeabi
new file mode 100644
index 000000000000..84463b1f8b2b
--- /dev/null
+++ b/gas/testsuite/gas/elf/section2.e-armeabi
@@ -0,0 +1,9 @@
+
+Symbol table '.symtab' contains 6 entries:
+   Num:    Value[ 	]* Size Type    Bind   Vis      Ndx Name
+     0: 0+0     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+0     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+0     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+0     0 SECTION LOCAL  DEFAULT    3 
+     4: 0+0     0 SECTION LOCAL  DEFAULT    4 
+     5: 0+0     0 SECTION LOCAL  DEFAULT    5 
diff --git a/gas/testsuite/gas/elf/section4.d b/gas/testsuite/gas/elf/section4.d
new file mode 100644
index 000000000000..5cda69ba7351
--- /dev/null
+++ b/gas/testsuite/gas/elf/section4.d
@@ -0,0 +1,12 @@
+#readelf: --sections
+#name: label arithmetic with multiple same-name sections
+
+#...
+[ 	]*\[.*\][ 	]+foo[ 	]+GROUP.*
+#...
+[ 	]*\[.*\][ 	]+\.text[ 	]+PROGBITS.*
+#...
+[ 	]*\[.*\][ 	]+\.data[ 	]+PROGBITS.*
+#...
+[ 	]*\[.*\][ 	]+\.text[ 	]+PROGBITS.*
+#pass
diff --git a/gas/testsuite/gas/elf/section4.s b/gas/testsuite/gas/elf/section4.s
new file mode 100644
index 000000000000..682ccb6b7f5f
--- /dev/null
+++ b/gas/testsuite/gas/elf/section4.s
@@ -0,0 +1,11 @@
+	.text
+.L1:
+        .align 4
+.L2:
+.L3:
+        .section        .data,"",%progbits
+        .long		.L3 - .L1
+        .section        .text,"axG",%progbits,foo,comdat
+	.word		0
+	
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/elf/section5.e b/gas/testsuite/gas/elf/section5.e
new file mode 100644
index 000000000000..916a9ed8ccbd
--- /dev/null
+++ b/gas/testsuite/gas/elf/section5.e
@@ -0,0 +1,5 @@
+.* \.test0[ 	]+PROGBITS[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[ 	]+[0-9]+.*
+.* \.test1[ 	]+PROGBITS[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[ 	]+[0-9]+.*
+.* \.test2[ 	]+PROGBITS[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[ 	]+[0-9]+.*
+.* \.test3[ 	]+PROGBITS[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+WA[ 	]+[0-9]+.*
+.* \.test4[ 	]+NOBITS[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+[0-9a-fA-F]+[ 	]+WA[ 	]+[0-9]+.*
diff --git a/gas/testsuite/gas/elf/section5.l b/gas/testsuite/gas/elf/section5.l
new file mode 100644
index 000000000000..ed547583d733
--- /dev/null
+++ b/gas/testsuite/gas/elf/section5.l
@@ -0,0 +1,37 @@
+.*: Assembler messages:
+.*:7: Warning: .*
+.*:7: Warning: .*
+.*:10: Warning: .*
+.*:13: Warning: .*
+.*:16: Warning: .*
+.*:18: Warning: .*
+.*:20: Warning: .*
+.*:22: Warning: .*
+.*:24: Warning: .*
+.*GAS.*
+
+
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test0[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test1,[ 	]*"",[ 	]*%progbits[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test2[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test3,[ 	]*"aw"[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test4,[ 	]*"aw",[ 	]*%nobits[ 	]*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test1,[ 	]*"aw",[ 	]*%nobits[ 	]*
+[ 	]+[0-9]+[ 	]+.*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test2,[ 	]*"w"[ 	]*
+[ 	]+[0-9]+[ 	]+.*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test3,[ 	]*"aw",[ 	]*%progbits[ 	]*
+[ 	]+[0-9]+[ 	]+.*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.test4,[ 	]*"aw"[ 	]*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.data,[ 	]*"a"[ 	]*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.bss,[ 	]*"a"[ 	]*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.data,[ 	]*"aw",[ 	]*%nobits[ 	]*
+[ 	]+[0-9]+[ 	]*
+[ 	]+[0-9]+[ 	]+.section[ 	]+.bss,[ 	]*"aw",[ 	]*%progbits[ 	]*
diff --git a/gas/testsuite/gas/elf/section5.s b/gas/testsuite/gas/elf/section5.s
new file mode 100644
index 000000000000..3a133cd0a27a
--- /dev/null
+++ b/gas/testsuite/gas/elf/section5.s
@@ -0,0 +1,24 @@
+	.section	.test0
+	.section	.test1, "", %progbits
+	.section	.test2
+	.section	.test3, "aw"
+	.section	.test4, "aw", %nobits
+
+	.section	.test1, "aw", %nobits
+test1:	.long	test1
+
+	.section	.test2, "w"
+test2:	.long	test2
+
+	.section	.test3, "aw", %progbits
+test3:	.long	test3
+
+	.section	.test4, "aw"
+
+	.section	.data, "a"
+
+	.section	.bss, "a"
+
+	.section	.data, "aw", %nobits
+
+	.section	.bss, "aw", %progbits
diff --git a/gas/testsuite/gas/elf/struct.d b/gas/testsuite/gas/elf/struct.d
new file mode 100644
index 000000000000..420c6e501115
--- /dev/null
+++ b/gas/testsuite/gas/elf/struct.d
@@ -0,0 +1,10 @@
+#nm: --extern-only
+#name: ELF struct
+
+# Test the .struct pseudo-op.
+
+0+0 D l1
+0+4 D l2
+0+2 A w1
+0+4 A w2
+0+6 A w3
diff --git a/gas/testsuite/gas/elf/struct.s b/gas/testsuite/gas/elf/struct.s
new file mode 100644
index 000000000000..abbd3f0ff570
--- /dev/null
+++ b/gas/testsuite/gas/elf/struct.s
@@ -0,0 +1,9 @@
+	.globl	w1, w2, w3, l1, l2
+	.data
+l1:	.long	0
+	.struct 2
+w1:	.short	0
+w2:	.short	0
+w3:	.short	0
+	.previous
+l2:	.long	0
diff --git a/gas/testsuite/gas/frv/allinsn.d b/gas/testsuite/gas/frv/allinsn.d
index 5ff96af8d62b..7b96806721b6 100644
--- a/gas/testsuite/gas/frv/allinsn.d
+++ b/gas/testsuite/gas/frv/allinsn.d
@@ -514,22 +514,22 @@ Disassembly of section .text:
  2a0:	80 0c 19 41 	stc cpr0,@\(sp,sp\)
 
 000002a4 <rstb>:
- 2a4:	82 0c 18 01 	rstb sp,@\(sp,sp\)
+ 2a4:	80 88 00 00 	nop
 
 000002a8 <rsth>:
- 2a8:	82 0c 18 41 	rsth sp,@\(sp,sp\)
+ 2a8:	80 88 00 00 	nop
 
 000002ac <rst>:
- 2ac:	82 0c 18 81 	rst sp,@\(sp,sp\)
+ 2ac:	80 88 00 00 	nop
 
 000002b0 <rstbf>:
- 2b0:	80 0c 1a 01 	rstbf fr0,@\(sp,sp\)
+ 2b0:	80 88 00 00 	nop
 
 000002b4 <rsthf>:
- 2b4:	80 0c 1a 41 	rsthf fr0,@\(sp,sp\)
+ 2b4:	80 88 00 00 	nop
 
 000002b8 <rstf>:
- 2b8:	80 0c 1a 81 	rstf fr0,@\(sp,sp\)
+ 2b8:	80 88 00 00 	nop
 
 000002bc <std>:
  2bc:	84 0c 10 c1 	std fp,@\(sp,sp\)
@@ -541,10 +541,10 @@ Disassembly of section .text:
  2c4:	80 0c 19 81 	stdc cpr0,@\(sp,sp\)
 
 000002c8 <rstd>:
- 2c8:	84 0c 18 c1 	rstd fp,@\(sp,sp\)
+ 2c8:	80 88 00 00 	nop
 
 000002cc <rstdf>:
- 2cc:	80 0c 1a c1 	rstdf fr0,@\(sp,sp\)
+ 2cc:	80 88 00 00 	nop
 
 000002d0 <stq>:
  2d0:	82 0c 11 01 	stq sp,@\(sp,sp\)
@@ -556,10 +556,10 @@ Disassembly of section .text:
  2d8:	80 0c 19 c1 	stqc cpr0,@\(sp,sp\)
 
 000002dc <rstq>:
- 2dc:	82 0c 19 01 	rstq sp,@\(sp,sp\)
+ 2dc:	80 88 00 00 	nop
 
 000002e0 <rstqf>:
- 2e0:	80 0c 1b 01 	rstqf fr0,@\(sp,sp\)
+ 2e0:	80 88 00 00 	nop
 
 000002e4 <stbu>:
  2e4:	82 0c 14 01 	stbu sp,@\(sp,sp\)
diff --git a/gas/testsuite/gas/frv/allinsn.exp b/gas/testsuite/gas/frv/allinsn.exp
index a9fc9654416b..ed29d20893b3 100644
--- a/gas/testsuite/gas/frv/allinsn.exp
+++ b/gas/testsuite/gas/frv/allinsn.exp
@@ -1,8 +1,32 @@
 # FRV assembler testsuite.
 
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "$name error test ($opts)"
+    gas_run $name.s $opts >&dump.out
+    if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} {
+	fail $testname
+	verbose "output is [file_contents dump.out]" 2
+	return
+    }
+    pass $testname
+}
+
 if [istarget frv*-*-*] {
     run_dump_test "allinsn"
 
     run_dump_test "fdpic"
     run_dump_test "reloc1"
+    run_dump_test "fr405-insn"
+    run_list_test "fr405-insn" "-mcpu=fr400"
+    run_list_test "fr405-insn" "-mcpu=fr500"
+
+    run_dump_test "fr450-spr"
+    run_dump_test "fr450-insn"
+    run_list_test "fr450-insn" "-mcpu=fr405"
+    run_list_test "fr450-insn" "-mcpu=fr400"
+    run_list_test "fr450-insn" "-mcpu=fr500"
+    run_list_test "fr450-media-issue" "-mcpu=fr450"
+
+    run_dump_test "fr550-pack1"
 }
diff --git a/gas/testsuite/gas/frv/allinsn.s b/gas/testsuite/gas/frv/allinsn.s
index 66aed2bbb29a..2657f03127fd 100644
--- a/gas/testsuite/gas/frv/allinsn.s
+++ b/gas/testsuite/gas/frv/allinsn.s
@@ -681,27 +681,27 @@ stc:
 	.text
 	.global rstb
 rstb:
-	rstb sp,@(sp,sp)
+	nop
 	.text
 	.global rsth
 rsth:
-	rsth sp,@(sp,sp)
+	nop
 	.text
 	.global rst
 rst:
-	rst sp,@(sp,sp)
+	nop
 	.text
 	.global rstbf
 rstbf:
-	rstbf fr0,@(sp,sp)
+	nop
 	.text
 	.global rsthf
 rsthf:
-	rsthf fr0,@(sp,sp)
+	nop
 	.text
 	.global rstf
 rstf:
-	rstf fr0,@(sp,sp)
+	nop
 	.text
 	.global std
 std:
@@ -717,11 +717,11 @@ stdc:
 	.text
 	.global rstd
 rstd:
-	rstd fp,@(sp,sp)
+	nop
 	.text
 	.global rstdf
 rstdf:
-	rstdf fr0,@(sp,sp)
+	nop
 	.text
 	.global stq
 stq:
@@ -737,11 +737,11 @@ stqc:
 	.text
 	.global rstq
 rstq:
-	rstq sp,@(sp,sp)
+	nop
 	.text
 	.global rstqf
 rstqf:
-	rstqf fr0,@(sp,sp)
+	nop
 	.text
 	.global stbu
 stbu:
diff --git a/gas/testsuite/gas/frv/fr405-insn.d b/gas/testsuite/gas/frv/fr405-insn.d
new file mode 100644
index 000000000000..044f71e95550
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.d
@@ -0,0 +1,15 @@
+#as: -mcpu=fr405
+#objdump: -dr
+
+.*:     file format elf32-frv(|fdpic)
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+.*:	81 18 41 45 	smu gr4,gr5
+.*:	81 18 41 85 	smass gr4,gr5
+.*:	81 18 41 c5 	smsss gr4,gr5
+.*:	8d 18 40 85 	slass gr4,gr5,gr6
+.*:	8b 18 01 04 	scutss gr4,gr5
+.*:	8d 18 40 05 	addss gr4,gr5,gr6
+.*:	8d 18 40 45 	subss gr4,gr5,gr6
diff --git a/gas/testsuite/gas/frv/fr405-insn.l b/gas/testsuite/gas/frv/fr405-insn.l
new file mode 100644
index 000000000000..8c84f80ece9b
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+.*:6: Error: Instruction not supported by this architecture
+.*:7: Error: Instruction not supported by this architecture
diff --git a/gas/testsuite/gas/frv/fr405-insn.s b/gas/testsuite/gas/frv/fr405-insn.s
new file mode 100644
index 000000000000..acd5ea26c056
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr405-insn.s
@@ -0,0 +1,7 @@
+	smu	gr4,gr5
+	smass	gr4,gr5
+	smsss	gr4,gr5
+	slass	gr4,gr5,gr6
+	scutss	gr4,gr5
+	addss	gr4,gr5,gr6
+	subss	gr4,gr5,gr6
diff --git a/gas/testsuite/gas/frv/fr450-insn.d b/gas/testsuite/gas/frv/fr450-insn.d
new file mode 100644
index 000000000000..a510f84be2ed
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.d
@@ -0,0 +1,41 @@
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*:     file format elf32-frv(|fdpic)
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+#
+.*:	80 0d f8 00 	lrai gr31,gr0,0x0,0x0,0x0
+.*:	be 0c 08 00 	lrai gr0,gr31,0x0,0x0,0x0
+.*:	80 0c 08 20 	lrai gr0,gr0,0x1,0x0,0x0
+.*:	80 0c 08 10 	lrai gr0,gr0,0x0,0x1,0x0
+.*:	80 0c 08 08 	lrai gr0,gr0,0x0,0x0,0x1
+#
+.*:	80 0d f8 40 	lrad gr31,gr0,0x0,0x0,0x0
+.*:	be 0c 08 40 	lrad gr0,gr31,0x0,0x0,0x0
+.*:	80 0c 08 60 	lrad gr0,gr0,0x1,0x0,0x0
+.*:	80 0c 08 50 	lrad gr0,gr0,0x0,0x1,0x0
+.*:	80 0c 08 48 	lrad gr0,gr0,0x0,0x0,0x1
+#
+.*:	80 0d f9 00 	tlbpr gr31,gr0,0x0,0x0
+.*:	80 0c 09 1f 	tlbpr gr0,gr31,0x0,0x0
+.*:	9c 0c 09 00 	tlbpr gr0,gr0,0x7,0x0
+.*:	82 0c 09 00 	tlbpr gr0,gr0,0x0,0x1
+#
+.*:	81 e1 e4 00 	mqlclrhs fr30,fr0,fr0
+.*:	81 e0 04 1e 	mqlclrhs fr0,fr30,fr0
+.*:	bd e0 04 00 	mqlclrhs fr0,fr0,fr30
+#
+.*:	81 e1 e5 00 	mqlmths fr30,fr0,fr0
+.*:	81 e0 05 1e 	mqlmths fr0,fr30,fr0
+.*:	bd e0 05 00 	mqlmths fr0,fr0,fr30
+#
+.*:	81 e1 e4 40 	mqsllhi fr30,0x0,fr0
+.*:	81 e0 04 7f 	mqsllhi fr0,0x3f,fr0
+.*:	bd e0 04 40 	mqsllhi fr0,0x0,fr30
+#
+.*:	81 e1 e4 c0 	mqsrahi fr30,0x0,fr0
+.*:	81 e0 04 ff 	mqsrahi fr0,0x3f,fr0
+.*:	bd e0 04 c0 	mqsrahi fr0,0x0,fr30
diff --git a/gas/testsuite/gas/frv/fr450-insn.l b/gas/testsuite/gas/frv/fr450-insn.l
new file mode 100644
index 000000000000..106a8f7041e2
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.l
@@ -0,0 +1,33 @@
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+#
+.*:7: Error: Instruction not supported by this architecture
+.*:8: Error: Instruction not supported by this architecture
+.*:9: Error: Instruction not supported by this architecture
+.*:10: Error: Instruction not supported by this architecture
+.*:11: Error: Instruction not supported by this architecture
+#
+.*:13: Error: Instruction not supported by this architecture
+.*:14: Error: Instruction not supported by this architecture
+.*:15: Error: Instruction not supported by this architecture
+.*:16: Error: Instruction not supported by this architecture
+#
+.*:18: Error: Instruction not supported by this architecture
+.*:19: Error: Instruction not supported by this architecture
+.*:20: Error: Instruction not supported by this architecture
+#
+.*:22: Error: Instruction not supported by this architecture
+.*:23: Error: Instruction not supported by this architecture
+.*:24: Error: Instruction not supported by this architecture
+#
+.*:26: Error: Instruction not supported by this architecture
+.*:27: Error: Instruction not supported by this architecture
+.*:28: Error: Instruction not supported by this architecture
+#
+.*:30: Error: Instruction not supported by this architecture
+.*:31: Error: Instruction not supported by this architecture
+.*:32: Error: Instruction not supported by this architecture
diff --git a/gas/testsuite/gas/frv/fr450-insn.s b/gas/testsuite/gas/frv/fr450-insn.s
new file mode 100644
index 000000000000..7224c30ca803
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-insn.s
@@ -0,0 +1,32 @@
+	lrai	gr31,gr0,#0,#0,#0
+	lrai	gr0,gr31,#0,#0,#0
+	lrai	gr0,gr0,#1,#0,#0
+	lrai	gr0,gr0,#0,#1,#0
+	lrai	gr0,gr0,#0,#0,#1
+
+	lrad	gr31,gr0,#0,#0,#0
+	lrad	gr0,gr31,#0,#0,#0
+	lrad	gr0,gr0,#1,#0,#0
+	lrad	gr0,gr0,#0,#1,#0
+	lrad	gr0,gr0,#0,#0,#1
+
+	tlbpr	gr31,gr0,#0,#0
+	tlbpr	gr0,gr31,#0,#0
+	tlbpr	gr0,gr0,#7,#0
+	tlbpr	gr0,gr0,#0,#1
+
+	mqlclrhs fr30,fr0,fr0
+	mqlclrhs fr0,fr30,fr0
+	mqlclrhs fr0,fr0,fr30
+
+	mqlmths	fr30,fr0,fr0
+	mqlmths	fr0,fr30,fr0
+	mqlmths	fr0,fr0,fr30
+
+	mqsllhi	fr30,#0,fr0
+	mqsllhi	fr0,#63,fr0
+	mqsllhi	fr0,#0,fr30
+
+	mqsrahi	fr30,#0,fr0
+	mqsrahi	fr0,#63,fr0
+	mqsrahi	fr0,#0,fr30
diff --git a/gas/testsuite/gas/frv/fr450-media-issue.l b/gas/testsuite/gas/frv/fr450-media-issue.l
new file mode 100644
index 000000000000..679702191bcb
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-media-issue.l
@@ -0,0 +1,31 @@
+.*: Assembler messages:
+.*:5: Error: VLIW packing constraint violation
+.*:9: Error: VLIW packing constraint violation
+.*:13: Error: VLIW packing constraint violation
+#
+.*:17: Error: VLIW packing constraint violation
+.*:19: Error: VLIW packing constraint violation
+.*:21: Error: VLIW packing constraint violation
+.*:23: Error: VLIW packing constraint violation
+.*:25: Error: VLIW packing constraint violation
+.*:27: Error: VLIW packing constraint violation
+#
+.*:33: Error: VLIW packing constraint violation
+.*:37: Error: VLIW packing constraint violation
+.*:41: Error: VLIW packing constraint violation
+#
+.*:45: Error: VLIW packing constraint violation
+.*:47: Error: VLIW packing constraint violation
+.*:49: Error: VLIW packing constraint violation
+.*:51: Error: VLIW packing constraint violation
+#
+.*:61: Error: VLIW packing constraint violation
+.*:65: Error: VLIW packing constraint violation
+.*:69: Error: VLIW packing constraint violation
+#
+.*:73: Error: VLIW packing constraint violation
+.*:75: Error: VLIW packing constraint violation
+.*:77: Error: VLIW packing constraint violation
+.*:79: Error: VLIW packing constraint violation
+.*:81: Error: VLIW packing constraint violation
+.*:83: Error: VLIW packing constraint violation
diff --git a/gas/testsuite/gas/frv/fr450-media-issue.s b/gas/testsuite/gas/frv/fr450-media-issue.s
new file mode 100644
index 000000000000..e73fc98aa55c
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-media-issue.s
@@ -0,0 +1,83 @@
+	; M-1 first
+	mand.p     fr0,fr1,fr2	; M1
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mand.p     fr0,fr1,fr2	; M1
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mand.p     fr0,fr1,fr2	; M1
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mand.p     fr0,fr1,fr2	; M1
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-2 first
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mcuti      acc8,#2,fr8	; M5 -- error
+	mqaddhss.p fr0,fr2,fr2	; M2
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-3 first
+	mwtacc.p   fr0,acc0	; M3
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mwtacc.p   fr0,acc0	; M3
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mwtacc.p   fr0,acc0	; M3
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mwtacc.p   fr0,acc0	; M3
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-4 first
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mqcpxrs.p  fr0,fr2,acc0	; M4
+	mdcutssi   acc8,#2,fr8	; M6 -- ok
+
+	; M-5 first
+	mrdacc.p   acc0,fr0	; M5
+	mpackh     fr4,fr5,fr6  ; M1 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mrdacc.p   acc0,fr0	; M5
+	mmulhu     fr4,fr6,acc8 ; M3 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mrdacc.p   acc0,fr0	; M5
+	mcuti      acc8,#2,fr8	; M5 -- ok
+	mrdacc.p   acc0,fr0	; M5
+	mdcutssi   acc8,#2,fr8	; M6 -- error
+
+	; M-6 first
+	mdcutssi.p acc0,#3,fr0	; M6
+	mpackh     fr4,fr5,fr6  ; M1 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mcpli      fr4,#1,fr6	; M2 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mmulhu     fr4,fr6,acc8 ; M3 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mqmulhu    fr4,fr6,acc8 ; M4 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mcuti      acc8,#2,fr8	; M5 -- error
+	mdcutssi.p acc0,#3,fr0	; M6
+	mdcutssi   acc8,#2,fr8	; M6 -- error
diff --git a/gas/testsuite/gas/frv/fr450-spr.d b/gas/testsuite/gas/frv/fr450-spr.d
new file mode 100644
index 000000000000..85b1f092c942
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-spr.d
@@ -0,0 +1,107 @@
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <\.text>:
+.*:	80 0c 01 84 	movgs gr4,psr
+.*:	80 0c 11 84 	movgs gr4,pcsr
+.*:	80 0c 21 84 	movgs gr4,bpcsr
+.*:	80 0c 31 84 	movgs gr4,tbr
+.*:	80 0c 41 84 	movgs gr4,bpsr
+.*:	80 0d 01 84 	movgs gr4,hsr0
+.*:	88 0c 01 84 	movgs gr4,ccr
+.*:	88 0c 71 84 	movgs gr4,cccr
+.*:	88 0d 01 84 	movgs gr4,lr
+.*:	88 0d 11 84 	movgs gr4,lcr
+.*:	88 0d 81 84 	movgs gr4,iacc0h
+.*:	88 0d 91 84 	movgs gr4,iacc0l
+.*:	88 0e 01 84 	movgs gr4,isr
+.*:	90 0c 01 84 	movgs gr4,epcr0
+.*:	92 0c 01 84 	movgs gr4,esr0
+.*:	92 0c e1 84 	movgs gr4,esr14
+.*:	92 0c f1 84 	movgs gr4,esr15
+.*:	94 0e 11 84 	movgs gr4,esfr1
+.*:	9a 0c 01 84 	movgs gr4,scr0
+.*:	9a 0c 11 84 	movgs gr4,scr1
+.*:	9a 0c 21 84 	movgs gr4,scr2
+.*:	9a 0c 31 84 	movgs gr4,scr3
+.*:	a8 0c 01 84 	movgs gr4,msr0
+.*:	a8 0c 11 84 	movgs gr4,msr1
+.*:	b0 0c 01 84 	movgs gr4,ear0
+.*:	b0 0c f1 84 	movgs gr4,ear15
+.*:	b4 0c 01 84 	movgs gr4,iamlr0
+.*:	b4 0c 11 84 	movgs gr4,iamlr1
+.*:	b4 0c 21 84 	movgs gr4,iamlr2
+.*:	b4 0c 31 84 	movgs gr4,iamlr3
+.*:	b4 0c 41 84 	movgs gr4,iamlr4
+.*:	b4 0c 51 84 	movgs gr4,iamlr5
+.*:	b4 0c 61 84 	movgs gr4,iamlr6
+.*:	b4 0c 71 84 	movgs gr4,iamlr7
+.*:	b6 0c 01 84 	movgs gr4,iampr0
+.*:	b6 0c 11 84 	movgs gr4,iampr1
+.*:	b6 0c 21 84 	movgs gr4,iampr2
+.*:	b6 0c 31 84 	movgs gr4,iampr3
+.*:	b6 0c 41 84 	movgs gr4,iampr4
+.*:	b6 0c 51 84 	movgs gr4,iampr5
+.*:	b6 0c 61 84 	movgs gr4,iampr6
+.*:	b6 0c 71 84 	movgs gr4,iampr7
+.*:	b8 0c 01 84 	movgs gr4,damlr0
+.*:	b8 0c 11 84 	movgs gr4,damlr1
+.*:	b8 0c 21 84 	movgs gr4,damlr2
+.*:	b8 0c 31 84 	movgs gr4,damlr3
+.*:	b8 0c 41 84 	movgs gr4,damlr4
+.*:	b8 0c 51 84 	movgs gr4,damlr5
+.*:	b8 0c 61 84 	movgs gr4,damlr6
+.*:	b8 0c 71 84 	movgs gr4,damlr7
+.*:	b8 0c 81 84 	movgs gr4,damlr8
+.*:	b8 0c 91 84 	movgs gr4,damlr9
+.*:	b8 0c a1 84 	movgs gr4,damlr10
+.*:	b8 0c b1 84 	movgs gr4,damlr11
+.*:	ba 0c 01 84 	movgs gr4,dampr0
+.*:	ba 0c 11 84 	movgs gr4,dampr1
+.*:	ba 0c 21 84 	movgs gr4,dampr2
+.*:	ba 0c 31 84 	movgs gr4,dampr3
+.*:	ba 0c 41 84 	movgs gr4,dampr4
+.*:	ba 0c 51 84 	movgs gr4,dampr5
+.*:	ba 0c 61 84 	movgs gr4,dampr6
+.*:	ba 0c 71 84 	movgs gr4,dampr7
+.*:	ba 0c 81 84 	movgs gr4,dampr8
+.*:	ba 0c 91 84 	movgs gr4,dampr9
+.*:	ba 0c a1 84 	movgs gr4,dampr10
+.*:	ba 0c b1 84 	movgs gr4,dampr11
+.*:	bc 0c 01 84 	movgs gr4,amcr
+.*:	bc 0c 51 84 	movgs gr4,iamvr1
+.*:	bc 0c 71 84 	movgs gr4,damvr1
+.*:	bc 0d 01 84 	movgs gr4,cxnr
+.*:	bc 0d 11 84 	movgs gr4,ttbr
+.*:	bc 0d 21 84 	movgs gr4,tplr
+.*:	bc 0d 31 84 	movgs gr4,tppr
+.*:	bc 0d 41 84 	movgs gr4,tpxr
+.*:	bc 0e 01 84 	movgs gr4,timerh
+.*:	bc 0e 11 84 	movgs gr4,timerl
+.*:	bc 0e 21 84 	movgs gr4,timerd
+.*:	c0 0c 01 84 	movgs gr4,dcr
+.*:	c0 0c 11 84 	movgs gr4,brr
+.*:	c0 0c 21 84 	movgs gr4,nmar
+.*:	c0 0c 31 84 	movgs gr4,btbr
+.*:	c0 0c 41 84 	movgs gr4,ibar0
+.*:	c0 0c 51 84 	movgs gr4,ibar1
+.*:	c0 0c 61 84 	movgs gr4,ibar2
+.*:	c0 0c 71 84 	movgs gr4,ibar3
+.*:	c0 0c 81 84 	movgs gr4,dbar0
+.*:	c0 0c 91 84 	movgs gr4,dbar1
+.*:	c0 0c a1 84 	movgs gr4,dbar2
+.*:	c0 0c b1 84 	movgs gr4,dbar3
+.*:	c0 0c c1 84 	movgs gr4,dbdr00
+.*:	c0 0c d1 84 	movgs gr4,dbdr01
+.*:	c0 0c e1 84 	movgs gr4,dbdr02
+.*:	c0 0c f1 84 	movgs gr4,dbdr03
+.*:	c0 0d 01 84 	movgs gr4,dbdr10
+.*:	c0 0d 11 84 	movgs gr4,dbdr11
+.*:	c0 0d c1 84 	movgs gr4,dbmr00
+.*:	c0 0d d1 84 	movgs gr4,dbmr01
+.*:	c0 0e 01 84 	movgs gr4,dbmr10
+.*:	c0 0e 11 84 	movgs gr4,dbmr11
diff --git a/gas/testsuite/gas/frv/fr450-spr.s b/gas/testsuite/gas/frv/fr450-spr.s
new file mode 100644
index 000000000000..2be3ba65070d
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr450-spr.s
@@ -0,0 +1,99 @@
+	movgs	gr4, psr	; 0x000 00000
+	movgs	gr4, pcsr	; 0x001 00001
+	movgs	gr4, bpcsr	; 0x002 00002
+	movgs	gr4, tbr	; 0x003 00003
+	movgs	gr4, bpsr	; 0x004 00004
+	movgs	gr4, hsr0	; 0x010 00020
+	movgs	gr4, ccr	; 0x100 00400
+	movgs	gr4, cccr	; 0x107 00407
+	movgs	gr4, lr		; 0x110 00420
+	movgs	gr4, lcr	; 0x111 00421
+	movgs	gr4, iacc0h	; 0x118 00430
+	movgs	gr4, iacc0l	; 0x119 00431
+	movgs	gr4, isr	; 0x120 00440
+	movgs	gr4, epcr0	; 0x200 01000
+	movgs	gr4, esr0	; 0x240 01100
+	movgs	gr4, esr14	; 0x24e 01116
+	movgs	gr4, esr15	; 0x24f 01117
+	movgs	gr4, esfr1	; 0x2a1 01241
+	movgs	gr4, scr0	; 0x340 01500
+	movgs	gr4, scr1	; 0x341 01501
+	movgs	gr4, scr2	; 0x342 01502
+	movgs	gr4, scr3	; 0x343 01503
+	movgs	gr4, msr0	; 0x500 02400
+	movgs	gr4, msr1	; 0x501 02401
+	movgs	gr4, ear0	; 0x600 03000
+	movgs	gr4, ear15	; 0x60f 03017
+	movgs	gr4, iamlr0	; 0x680 03200
+	movgs	gr4, iamlr1	; 0x681 03201
+	movgs	gr4, iamlr2	; 0x682 03202
+	movgs	gr4, iamlr3	; 0x683 03203
+	movgs	gr4, iamlr4	; 0x684 03204
+	movgs	gr4, iamlr5	; 0x685 03205
+	movgs	gr4, iamlr6	; 0x686 03206
+	movgs	gr4, iamlr7	; 0x687 03207
+	movgs	gr4, iampr0	; 0x6c0 03300
+	movgs	gr4, iampr1	; 0x6c1 03301
+	movgs	gr4, iampr2	; 0x6c2 03302
+	movgs	gr4, iampr3	; 0x6c3 03303
+	movgs	gr4, iampr4	; 0x6c4 03304
+	movgs	gr4, iampr5	; 0x6c5 03305
+	movgs	gr4, iampr6	; 0x6c6 03306
+	movgs	gr4, iampr7	; 0x6c7 03307
+	movgs	gr4, damlr0	; 0x700 03400
+	movgs	gr4, damlr1	; 0x701 03401
+	movgs	gr4, damlr2	; 0x702 03402
+	movgs	gr4, damlr3	; 0x703 03403
+	movgs	gr4, damlr4	; 0x704 03404
+	movgs	gr4, damlr5	; 0x705 03405
+	movgs	gr4, damlr6	; 0x706 03406
+	movgs	gr4, damlr7	; 0x707 03407
+	movgs	gr4, damlr8	; 0x708 03410
+	movgs	gr4, damlr9	; 0x709 03411
+	movgs	gr4, damlr10	; 0x70a 03412
+	movgs	gr4, damlr11	; 0x70b 03413
+	movgs	gr4, dampr0	; 0x740 03500
+	movgs	gr4, dampr1	; 0x741 03501
+	movgs	gr4, dampr2	; 0x742 03502
+	movgs	gr4, dampr3	; 0x743 03503
+	movgs	gr4, dampr4	; 0x744 03504
+	movgs	gr4, dampr5	; 0x745 03505
+	movgs	gr4, dampr6	; 0x746 03506
+	movgs	gr4, dampr7	; 0x747 03507
+	movgs	gr4, dampr8	; 0x748 03510
+	movgs	gr4, dampr9	; 0x749 03511
+	movgs	gr4, dampr10	; 0x74a 03512
+	movgs	gr4, dampr11	; 0x74b 03513
+	movgs	gr4, amcr	; 0x780 03600
+	movgs	gr4, iamvr1	; 0x785 03605
+	movgs	gr4, damvr1	; 0x787 03607
+	movgs	gr4, cxnr	; 0x790 03620
+	movgs	gr4, ttbr	; 0x791 03621
+	movgs	gr4, tplr	; 0x792 03622
+	movgs	gr4, tppr	; 0x793 03623
+	movgs	gr4, tpxr	; 0x794 03624
+	movgs	gr4, timerh	; 0x7a0 03640
+	movgs	gr4, timerl	; 0x7a1 03641
+	movgs	gr4, timerd	; 0x7a2 03642
+	movgs	gr4, dcr	; 0x800 04000
+	movgs	gr4, brr	; 0x801 04001
+	movgs	gr4, nmar	; 0x802 04002
+	movgs	gr4, btbr	; 0x803 04003
+	movgs	gr4, ibar0	; 0x804 04004
+	movgs	gr4, ibar1	; 0x805 04005
+	movgs	gr4, ibar2	; 0x806 04006
+	movgs	gr4, ibar3	; 0x807 04007
+	movgs	gr4, dbar0	; 0x808 04010
+	movgs	gr4, dbar1	; 0x809 04011
+	movgs	gr4, dbar2	; 0x80A 04012
+	movgs	gr4, dbar3	; 0x80B 04013
+	movgs	gr4, dbdr00	; 0x80C 04014
+	movgs	gr4, dbdr01	; 0x80D 04015
+	movgs	gr4, dbdr02	; 0x80E 04016
+	movgs	gr4, dbdr03	; 0x80F 04017
+	movgs	gr4, dbdr10	; 0x810 04020
+	movgs	gr4, dbdr11	; 0x811 04021
+	movgs	gr4, dbmr00	; 0x81C 04034
+	movgs	gr4, dbmr01	; 0x81D 04035
+	movgs	gr4, dbmr10	; 0x820 04040
+	movgs	gr4, dbmr11	; 0x821 04041
diff --git a/gas/testsuite/gas/frv/fr550-pack1.d b/gas/testsuite/gas/frv/fr550-pack1.d
new file mode 100644
index 000000000000..c577bfcfb5e0
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr550-pack1.d
@@ -0,0 +1,12 @@
+#as: -mcpu=fr550
+#objdump: -dr
+
+.*:     file format elf32-frv(|fdpic)
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+.*:	09 b0 00 00 	cfmovs\.p fr0,fr4,cc0,0x0
+.*:	0b b0 00 01 	cfmovs\.p fr1,fr5,cc0,0x0
+.*:	0d b0 00 02 	cfmovs\.p fr2,fr6,cc0,0x0
+.*:	8f b0 00 03 	cfmovs fr3,fr7,cc0,0x0
diff --git a/gas/testsuite/gas/frv/fr550-pack1.s b/gas/testsuite/gas/frv/fr550-pack1.s
new file mode 100644
index 000000000000..aa3f36077df7
--- /dev/null
+++ b/gas/testsuite/gas/frv/fr550-pack1.s
@@ -0,0 +1,4 @@
+	cfmovs.p	fr0,fr4,cc0,0
+	cfmovs.p	fr1,fr5,cc0,0
+	cfmovs.p	fr2,fr6,cc0,0
+	cfmovs		fr3,fr7,cc0,0
diff --git a/gas/testsuite/gas/h8300/addsubrxcheck.s b/gas/testsuite/gas/h8300/addsubrxcheck.s
new file mode 100644
index 000000000000..8ad191222c11
--- /dev/null
+++ b/gas/testsuite/gas/h8300/addsubrxcheck.s
@@ -0,0 +1,16 @@
+	.section .text
+	.global _main
+_main:
+	mov.w	r6,@-r7
+	mov.w	r7,r6
+	subs	#2,r7
+	mov.w	@(-2,r6),r2
+	subs	#2,r2
+	mov.w	r2,@(-2,r6)
+	sub.w	r2,r2
+	mov.w	r2,r0
+	adds	#2,r7
+	mov.w	@r7+,r6
+	rts
+	.size	_main, .-_main
+	.end
diff --git a/gas/testsuite/gas/h8300/ffxx1-coff.d b/gas/testsuite/gas/h8300/ffxx1-coff.d
index 93455d521750..18aa05bd30ec 100644
--- a/gas/testsuite/gas/h8300/ffxx1-coff.d
+++ b/gas/testsuite/gas/h8300/ffxx1-coff.d
@@ -8,16 +8,16 @@
 Disassembly of section .text:
 	...
 			0: 16	main
-0+0400 <main> f8 7f             mov.b	#0x7f,r0l
-0+0402 <main[+](0x|)2> 28 bb             mov.b	@0xbb:8,r0l
-0+0404 <main[+](0x|)4> 6a 88 ff b9       mov.b	r0l,@0xffb9:16
-0+0408 <main[+](0x|)8> f8 01             mov.b	#0x1,r0l
-0+040a <loop> 6a 88 ff bb       mov.b	r0l,@0xffbb:16
-0+040e <delay> 79 01 00 00       mov.w	#0x0,r1
-0+0412 <deloop> 0b 01             adds	#0x1,er1
-0+0414 <deloop[+](0x|)2> 46 00             bne	.0 \(416\)
+0+0400 <main>.*mov.b	#0x7f,r0l
+0+0402 <.*>.*mov.b	@0xbb:8,r0l
+0+0404 <.*>.*mov.b	r0l,@0xffb9:16
+0+0408 <.*>.*mov.b	#0x1,r0l
+0+040a <loop>.*mov.b	r0l,@0xffbb:16
+0+040e <delay>.*mov.w	#0x0,r1
+0+0412 <deloop>.*adds	#1,r1
+0+0414 <.*>.*bne	.0 \(0x416\)
 			415: DISP8	deloop[+]0xffffffff
-0+0416 <deloop[+](0x|)4> 12 88             rotl	r0l
-0+0418 <deloop[+](0x|)6> 40 00             bra	.0 \(41a\)
+0+0416 <.*>.*rotl.b	r0l
+0+0418 <.*>.*bra	.0 \(0x41a\)
 			419: DISP8	loop[+]0xffffffff
 	...
diff --git a/gas/testsuite/gas/h8300/ffxx1-coff.s b/gas/testsuite/gas/h8300/ffxx1-coff.s
index 53fc84160d40..b44a19f27cf6 100644
--- a/gas/testsuite/gas/h8300/ffxx1-coff.s
+++ b/gas/testsuite/gas/h8300/ffxx1-coff.s
@@ -13,7 +13,7 @@ main:   mov.b   #0x7f,r0l       ;port 6 ddr = 7F
 	mov.b   #seed,r0l       ;start with 0000001
 loop:   mov.b   r0l,@p6dr:16    ;output to port 6 
 delay:  mov.w   #0x0000,r1
-deloop: adds.w  #1,r1
+deloop: adds    #1,r1
 	bne     deloop:8        ;not = 0
 	rotl    r0l
         bra     loop:8
diff --git a/gas/testsuite/gas/h8300/ffxx1-elf.d b/gas/testsuite/gas/h8300/ffxx1-elf.d
index efbf308e3d46..89e7224dcfee 100644
--- a/gas/testsuite/gas/h8300/ffxx1-elf.d
+++ b/gas/testsuite/gas/h8300/ffxx1-elf.d
@@ -8,16 +8,16 @@
 Disassembly of section .text:
 	...
 			0: R_H8_DIR16	main
-0+0400 <main> f8 7f             mov.b	#0x7f,r0l
-0+0402 <main[+](0x|)2> 28 bb             mov.b	@0xbb:8,r0l
-0+0404 <main[+](0x|)4> 6a 88 ff b9       mov.b	r0l,@0xffb9:16
-0+0408 <main[+](0x|)8> f8 01             mov.b	#0x1,r0l
-0+040a <loop> 6a 88 ff bb       mov.b	r0l,@0xffbb:16
-0+040e <delay> 79 01 00 00       mov.w	#0x0,r1
-0+0412 <deloop> 0b 01             adds	#0x1,er1
-0+0414 <deloop[+](0x|)2> 46 00             bne	.0 \(416\)
+0+0400 <main>.*mov.b	#0x7f,r0l
+0+0402 <.*>.*mov.b	@0xbb:8,r0l
+0+0404 <.*>.*mov.b	r0l,@0xffb9:16
+0+0408 <.*>.*mov.b	#0x1,r0l
+0+040a <loop>.*mov.b	r0l,@0xffbb:16
+0+040e <delay>.*mov.w	#0x0,r1
+0+0412 <deloop>.*adds	#1,r1
+0+0414 <.*>.*bne	.0 \(0x416\)
 			415: R_H8_PCREL8	deloop
-0+0416 <deloop[+](0x|)4> 12 88             rotl	r0l
-0+0418 <deloop[+](0x|)6> 40 00             bra	.0 \(41a\)
+0+0416 <.*>.*rotl.b	r0l
+0+0418 <.*>.*bra	.0 \(0x41a\)
 			419: R_H8_PCREL8	loop
 	...
diff --git a/gas/testsuite/gas/h8300/ffxx1-elf.s b/gas/testsuite/gas/h8300/ffxx1-elf.s
index 53fc84160d40..b44a19f27cf6 100644
--- a/gas/testsuite/gas/h8300/ffxx1-elf.s
+++ b/gas/testsuite/gas/h8300/ffxx1-elf.s
@@ -13,7 +13,7 @@ main:   mov.b   #0x7f,r0l       ;port 6 ddr = 7F
 	mov.b   #seed,r0l       ;start with 0000001
 loop:   mov.b   r0l,@p6dr:16    ;output to port 6 
 delay:  mov.w   #0x0000,r1
-deloop: adds.w  #1,r1
+deloop: adds    #1,r1
 	bne     deloop:8        ;not = 0
 	rotl    r0l
         bra     loop:8
diff --git a/gas/testsuite/gas/h8300/h8300.exp b/gas/testsuite/gas/h8300/h8300.exp
index a13c16aa3478..104a88251350 100644
--- a/gas/testsuite/gas/h8300/h8300.exp
+++ b/gas/testsuite/gas/h8300/h8300.exp
@@ -2114,6 +2114,67 @@ proc do_h8300h_mov32bug {} {
     if [expr $x == 1] then { pass $testname } else { fail $testname }
 }
 
+proc do_h8300hn_addressgen {} {
+    set testname "symaddgen.s: h8300hn symbol address generation"
+    set x 0
+
+    gas_start "symaddgen.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ .* 01006DF6\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 0D76\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 790207D0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 6B82F020\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 79022710\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 6B820000\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 01006D76\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 5470\[^\n\]*\n"       { set x [expr $x+1] }
+            
+	    eof					{ break }
+	}
+    }
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 8] then { pass $testname } else { fail $testname }
+}
+
+proc do_h8300_addsubrxcheck {} {
+    set testname "addsubrxcheck.s: h8300 check rx generation for adds subs instructions"
+    set x 0
+
+    gas_start "addsubrxcheck.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ .* 6DF6\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 0D76\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 1B87\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 6F62FFFE\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 1B82\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 6FE2FFFE\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 1922\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 0D20\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 0B87\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 6D76\[^\n\]*\n"       { set x [expr $x+1] }
+	    -re " +\[0-9\]+ .* 5470\[^\n\]*\n"       { set x [expr $x+1] }
+
+	    eof					{ break }
+	}
+    }
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 11] then { pass $testname } else { fail $testname }
+}
+
 if [istarget h8300*-*-*] then {
     # Test the basic h8300 instruction parser
     do_h8300_add_sub
@@ -2131,6 +2192,9 @@ if [istarget h8300*-*-*] then {
     do_h8300_movw
     do_h8300_pushpop
     do_h8300_rotate_shift
+    do_h8300hn_addressgen
+
+    do_h8300_addsubrxcheck
 
     # Now test the h8300h instruction parser
     do_h8300h_add_sub
diff --git a/gas/testsuite/gas/h8300/h8sx_disp2.d b/gas/testsuite/gas/h8300/h8sx_disp2.d
index a3c712cb35a7..77aaba31727f 100644
--- a/gas/testsuite/gas/h8300/h8sx_disp2.d
+++ b/gas/testsuite/gas/h8300/h8sx_disp2.d
@@ -5,42 +5,42 @@
 Disassembly of section \.text:
 
 0+00 <\.text>:
- .*:	01 75 68 08 *	01 75 68 08 80 02 add.b	#0x2,@\(0x1:2,r0\)
- .*:	80 02 *
- .*:	01 76 68 08 *	01 76 68 08 80 02 add.b	#0x2,@\(0x2:2,r0\)
- .*:	80 02 *
- .*:	01 77 68 08 *	01 77 68 08 80 02 add.b	#0x2,@\(0x3:2,r0\)
- .*:	80 02 *
- .*:	01 74 6e 08 *	01 74 6e 08 00 04 80 02 add.b	#0x2,@\(0x4:16,r0\)
- .*:	00 04 80 02 *
- .*:	78 04 6a 28 *	78 04 6a 28 00 00 00 00 80 02 add.b	#0x2,@\(0x0:32,r0\)
- .*:	00 00 00 00 *
- .*:	80 02 *
- .*:	01 5e c0 10 *	01 5e c0 10 00 01 00 02 add.w	#0x2,@\(0x1:16,r0\)
- .*:	00 01 00 02 *
- .*:	01 5e 10 10 *	01 5e 10 10 00 02 add.w	#0x2,@\(0x2:2,r0\)
- .*:	00 02 *
- .*:	01 5e 20 10 *	01 5e 20 10 00 02 add.w	#0x2,@\(0x4:2,r0\)
- .*:	00 02 *
- .*:	01 5e 30 10 *	01 5e 30 10 00 02 add.w	#0x2,@\(0x6:2,r0\)
- .*:	00 02 *
- .*:	01 5e c0 10 *	01 5e c0 10 00 08 00 02 add.w	#0x2,@\(0x8:16,r0\)
- .*:	00 08 00 02 *
- .*:	01 5e c8 10 *	01 5e c8 10 00 00 00 00 00 02 add.w	#0x2,@\(0x0:32,r0\)
- .*:	00 00 00 00 *
- .*:	00 02 *
- .*:	01 0e c0 10 *	01 0e c0 10 00 01 00 02 add.l	#0x2,@\(0x1:16,r0\)
- .*:	00 01 00 02 *
- .*:	01 0e c0 10 *	01 0e c0 10 00 02 00 02 add.l	#0x2,@\(0x2:16,r0\)
- .*:	00 02 00 02 *
- .*:	01 0e 10 10 *	01 0e 10 10 00 02 add.l	#0x2,@\(0x4:2,r0\)
- .*:	00 02 *
- .*:	01 0e 20 10 *	01 0e 20 10 00 02 add.l	#0x2,@\(0x8:2,r0\)
- .*:	00 02 *
- .*:	01 0e 30 10 *	01 0e 30 10 00 02 add.l	#0x2,@\(0xc:2,r0\)
- .*:	00 02 *
- .*:	01 0e c0 10 *	01 0e c0 10 00 10 00 02 add.l	#0x2,@\(0x10:16,r0\)
- .*:	00 10 00 02 *
- .*:	01 0e c8 10 *	01 0e c8 10 00 00 00 00 00 02 add.l	#0x2,@\(0x0:32,r0\)
- .*:	00 00 00 00 *
- .*:	00 02 *
+ .*:	01 75 68 08.*add.b	#0x2,@\(0x1:2,er0\)
+ .*:	80 02 
+ .*:	01 76 68 08.*add.b	#0x2,@\(0x2:2,er0\)
+ .*:	80 02 
+ .*:	01 77 68 08.*add.b	#0x2,@\(0x3:2,er0\)
+ .*:	80 02 
+ .*:	01 74 6e 08.*add.b	#0x2,@\(0x4:16,er0\)
+ .*:	00 04 80 02 
+ .*:	78 04 6a 28.*add.b	#0x2,@\(0x0:32,er0\)
+ .*:	00 00 00 00 
+ .*:	80 02 
+ .*:	01 5e c0 10.*add.w	#0x2,@\(0x1:16,er0\)
+ .*:	00 01 00 02 
+ .*:	01 5e 10 10.*add.w	#0x2,@\(0x2:2,er0\)
+ .*:	00 02 
+ .*:	01 5e 20 10.*add.w	#0x2,@\(0x4:2,er0\)
+ .*:	00 02 
+ .*:	01 5e 30 10.*add.w	#0x2,@\(0x6:2,er0\)
+ .*:	00 02 
+ .*:	01 5e c0 10.*add.w	#0x2,@\(0x8:16,er0\)
+ .*:	00 08 00 02 
+ .*:	01 5e c8 10.*add.w	#0x2,@\(0x0:32,er0\)
+ .*:	00 00 00 00 
+ .*:	00 02 
+ .*:	01 0e c0 10.*add.l	#0x2,@\(0x1:16,er0\)
+ .*:	00 01 00 02 
+ .*:	01 0e c0 10.*add.l	#0x2,@\(0x2:16,er0\)
+ .*:	00 02 00 02 
+ .*:	01 0e 10 10.*add.l	#0x2,@\(0x4:2,er0\)
+ .*:	00 02 
+ .*:	01 0e 20 10.*add.l	#0x2,@\(0x8:2,er0\)
+ .*:	00 02 
+ .*:	01 0e 30 10.*add.l	#0x2,@\(0xc:2,er0\)
+ .*:	00 02 
+ .*:	01 0e c0 10.*add.l	#0x2,@\(0x10:16,er0\)
+ .*:	00 10 00 02 
+ .*:	01 0e c8 10.*add.l	#0x2,@\(0x0:32,er0\)
+ .*:	00 00 00 00 
+ .*:	00 02 
diff --git a/gas/testsuite/gas/h8300/h8sx_mov_imm.d b/gas/testsuite/gas/h8300/h8sx_mov_imm.d
index 15a5ff9e5f0e..968e3c770900 100644
--- a/gas/testsuite/gas/h8300/h8sx_mov_imm.d
+++ b/gas/testsuite/gas/h8300/h8sx_mov_imm.d
@@ -5,303 +5,303 @@
 Disassembly of section \.text:
 
 .* <.*>:
-.*:	fa 00 *	fa 00 * mov.b	#0x0,r2l
+.*:	fa 00 *	mov.b	#0x0,r2l
 			.*: R_H8_DIR8	foo
-.*:	fa 00 *	fa 00 * mov.b	#0x0,r2l
+.*:	fa 00 *	mov.b	#0x0,r2l
 			.*: R_H8_DIR8	.L1
-.*:	fa 00 *	fa 00 * mov.b	#0x0,r2l
+.*:	fa 00 *	mov.b	#0x0,r2l
 			.*: R_H8_DIR8	bar
-.*:	01 7d 02 00 *	01 7d 02 00 * mov.b	#0x0,@r2
+.*:	01 7d 02 00[ 	]*mov.b	#0x0,@er2
 			.*: R_H8_DIR8	foo
-.*:	01 7d 02 00 *	01 7d 02 00 * mov.b	#0x0,@r2
+.*:	01 7d 02 00[ 	]*mov.b	#0x0,@er2
 			.*: R_H8_DIR8	.L1
-.*:	01 7d 02 00 *	01 7d 02 00 * mov.b	#0x0,@r2
+.*:	01 7d 02 00[ 	]*mov.b	#0x0,@er2
 			.*: R_H8_DIR8	bar
-.*:	01 7d b2 00 *	01 7d b2 00 * mov.b	#0x0,@-r2
+.*:	01 7d b2 00[ 	]*mov.b	#0x0,@-er2
 			.*: R_H8_DIR8	foo
-.*:	01 7d 82 00 *	01 7d 82 00 * mov.b	#0x0,@r2\+
+.*:	01 7d 82 00[ 	]*mov.b	#0x0,@er2\+
 			.*: R_H8_DIR8	.L1
-.*:	01 7d a2 00 *	01 7d a2 00 * mov.b	#0x0,@r2-
+.*:	01 7d a2 00[ 	]*mov.b	#0x0,@er2-
 			.*: R_H8_DIR8	bar
-.*:	01 7d 22 00 *	01 7d 22 00 * mov.b	#0x0,@\(0x2:2,r2\)
+.*:	01 7d 22 00[ 	]*mov.b	#0x0,@\(0x2:2,er2\)
 			.*: R_H8_DIR8	foo
-.*:	01 7d 22 00 *	01 7d 22 00 * mov.b	#0x0,@\(0x2:2,r2\)
+.*:	01 7d 22 00[ 	]*mov.b	#0x0,@\(0x2:2,er2\)
 			.*: R_H8_DIR8	.L1
-.*:	01 7d 22 00 *	01 7d 22 00 * mov.b	#0x0,@\(0x2:2,r2\)
+.*:	01 7d 22 00[ 	]*mov.b	#0x0,@\(0x2:2,er2\)
 			.*: R_H8_DIR8	bar
-.*:	01 7d c2 00 *	01 7d c2 00 00 10 * mov.b	#0x0,@\(0x10:16,r2\)
+.*:	01 7d c2 00[ 	]*mov.b	#0x0,@\(0x10:16,er2\)
 .*:	00 10 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d c2 00 *	01 7d c2 00 00 10 * mov.b	#0x0,@\(0x10:16,r2\)
+.*:	01 7d c2 00[ 	]*mov.b	#0x0,@\(0x10:16,er2\)
 .*:	00 10 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d c2 00 *	01 7d c2 00 00 10 * mov.b	#0x0,@\(0x10:16,r2\)
+.*:	01 7d c2 00[ 	]*mov.b	#0x0,@\(0x10:16,er2\)
 .*:	00 10 *
 			.*: R_H8_DIR8	bar
-.*:	01 7d d2 00 *	01 7d d2 00 00 10 * mov.b	#0x0,@\(0x10:16,r2l.b\)
+.*:	01 7d d2 00[ 	]*mov.b	#0x0,@\(0x10:16,r2l.b\)
 .*:	00 10 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d e2 00 *	01 7d e2 00 00 10 * mov.b	#0x0,@\(0x10:16,r2.w\)
+.*:	01 7d e2 00[ 	]*mov.b	#0x0,@\(0x10:16,r2.w\)
 .*:	00 10 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d f2 00 *	01 7d f2 00 00 10 * mov.b	#0x0,@\(0x10:16,er2.l\)
+.*:	01 7d f2 00[ 	]*mov.b	#0x0,@\(0x10:16,er2.l\)
 .*:	00 10 *
 			.*: R_H8_DIR8	bar
-.*:	01 7d ca 00 *	01 7d ca 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,r2\)
+.*:	01 7d ca 00[ 	]*mov.b	#0x0,@\(0x12345:32,er2\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d ca 00 *	01 7d ca 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,r2\)
+.*:	01 7d ca 00[ 	]*mov.b	#0x0,@\(0x12345:32,er2\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d ca 00 *	01 7d ca 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,r2\)
+.*:	01 7d ca 00[ 	]*mov.b	#0x0,@\(0x12345:32,er2\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	bar
-.*:	01 7d da 00 *	01 7d da 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,r2l.b\)
+.*:	01 7d da 00[ 	]*mov.b	#0x0,@\(0x12345:32,r2l.b\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d ea 00 *	01 7d ea 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,r2.w\)
+.*:	01 7d ea 00[ 	]*mov.b	#0x0,@\(0x12345:32,r2.w\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d fa 00 *	01 7d fa 00 00 01 23 45 * mov.b	#0x0,@\(0x12345:32,er2.l\)
+.*:	01 7d fa 00[ 	]*mov.b	#0x0,@\(0x12345:32,er2.l\)
 .*:	00 01 23 45 *
 			.*: R_H8_DIR8	bar
-.*:	01 7d 40 00 *	01 7d 40 00 80 00 * mov.b	#0x0,@0x8000:16
+.*:	01 7d 40 00[ 	]*mov.b	#0x0,@0x8000:16
 .*:	80 00 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d 40 00 *	01 7d 40 00 80 00 * mov.b	#0x0,@0x8000:16
+.*:	01 7d 40 00[ 	]*mov.b	#0x0,@0x8000:16
 .*:	80 00 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d 40 00 *	01 7d 40 00 80 00 * mov.b	#0x0,@0x8000:16
+.*:	01 7d 40 00[ 	]*mov.b	#0x0,@0x8000:16
 .*:	80 00 *
 			.*: R_H8_DIR8	bar
-.*:	01 7d 48 00 *	01 7d 48 00 00 01 80 00 * mov.b	#0x0,@0x18000:32
+.*:	01 7d 48 00[ 	]*mov.b	#0x0,@0x18000:32
 .*:	00 01 80 00 *
 			.*: R_H8_DIR8	foo
-.*:	01 7d 48 00 *	01 7d 48 00 00 01 80 00 * mov.b	#0x0,@0x18000:32
+.*:	01 7d 48 00[ 	]*mov.b	#0x0,@0x18000:32
 .*:	00 01 80 00 *
 			.*: R_H8_DIR8	.L1
-.*:	01 7d 48 00 *	01 7d 48 00 00 01 80 00 * mov.b	#0x0,@0x18000:32
+.*:	01 7d 48 00[ 	]*mov.b	#0x0,@0x18000:32
 .*:	00 01 80 00 *
 			.*: R_H8_DIR8	bar
-.*:	79 02 00 00 *	79 02 00 00 * mov.w	#0x0,r2
+.*:	79 02 00 00[ 	]*mov.w	#0x0,r2
 			.*: R_H8_DIR16	foo
-.*:	79 02 00 00 *	79 02 00 00 * mov.w	#0x0,r2
+.*:	79 02 00 00[ 	]*mov.w	#0x0,r2
 			.*: R_H8_DIR16	.L1
-.*:	79 02 00 00 *	79 02 00 00 * mov.w	#0x0,r2
+.*:	79 02 00 00[ 	]*mov.w	#0x0,r2
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 02 00 * mov.w	#0x0,@r2
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@er2
 .*:	02 00 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 02 00 * mov.w	#0x0,@r2
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@er2
 .*:	02 00 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 02 00 * mov.w	#0x0,@r2
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@er2
 .*:	02 00 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 b2 00 * mov.w	#0x0,@-r2
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@-er2
 .*:	b2 00 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 82 00 * mov.w	#0x0,@r2\+
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@er2\+
 .*:	82 00 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 a2 00 * mov.w	#0x0,@r2-
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@er2-
 .*:	a2 00 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 22 00 * mov.w	#0x0,@\(0x4:2,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x4:2,er2\)
 .*:	22 00 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 22 00 * mov.w	#0x0,@\(0x4:2,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x4:2,er2\)
 .*:	22 00 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 22 00 * mov.w	#0x0,@\(0x4:2,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x4:2,er2\)
 .*:	22 00 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 c2 00 00 10 * mov.w	#0x0,@\(0x10:16,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,er2\)
 .*:	c2 00 00 10 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 c2 00 00 10 * mov.w	#0x0,@\(0x10:16,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,er2\)
 .*:	c2 00 00 10 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 c2 00 00 10 * mov.w	#0x0,@\(0x10:16,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,er2\)
 .*:	c2 00 00 10 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 d2 00 00 10 * mov.w	#0x0,@\(0x10:16,r2l.b\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,r2l.b\)
 .*:	d2 00 00 10 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 e2 00 00 10 * mov.w	#0x0,@\(0x10:16,r2.w\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,r2.w\)
 .*:	e2 00 00 10 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 f2 00 00 10 * mov.w	#0x0,@\(0x10:16,er2.l\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x10:16,er2.l\)
 .*:	f2 00 00 10 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 ca 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,er2\)
 .*:	ca 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 ca 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,er2\)
 .*:	ca 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 ca 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,r2\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,er2\)
 .*:	ca 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 da 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,r2l.b\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,r2l.b\)
 .*:	da 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 ea 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,r2.w\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,r2.w\)
 .*:	ea 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 fa 00 00 01 23 45 * mov.w	#0x0,@\(0x12345:32,er2.l\)
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@\(0x12345:32,er2.l\)
 .*:	fa 00 00 01 *
 .*:	23 45 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 40 00 80 00 * mov.w	#0x0,@0x8000:16
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x8000:16
 .*:	40 00 80 00 *
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 40 00 80 00 * mov.w	#0x0,@0x8000:16
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x8000:16
 .*:	40 00 80 00 *
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 40 00 80 00 * mov.w	#0x0,@0x8000:16
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x8000:16
 .*:	40 00 80 00 *
 			.*: R_H8_DIR16	bar
-.*:	79 74 00 00 *	79 74 00 00 48 00 00 01 80 00 * mov.w	#0x0,@0x18000:32
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x18000:32
 .*:	48 00 00 01 *
-.*:	80 00 *
+.*:	80 00 
 			.*: R_H8_DIR16	foo
-.*:	79 74 00 00 *	79 74 00 00 48 00 00 01 80 00 * mov.w	#0x0,@0x18000:32
-.*:	48 00 00 01 *
-.*:	80 00 *
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x18000:32
+.*:	48 00 00 01 
+.*:	80 00 
 			.*: R_H8_DIR16	.L1
-.*:	79 74 00 00 *	79 74 00 00 48 00 00 01 80 00 * mov.w	#0x0,@0x18000:32
-.*:	48 00 00 01 *
-.*:	80 00 *
+.*:	79 74 00 00[ 	]*mov.w	#0x0,@0x18000:32
+.*:	48 00 00 01 
+.*:	80 00 
 			.*: R_H8_DIR16	bar
 
 .* <.*>:
-.*:	7a 02 00 00 *	7a 02 00 00 00 00 * mov.l	#0x0,er2
-.*:	00 00 *
+.*:	7a 02 00 00[ 	]*mov.l	#0x0,er2
+.*:	00 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 02 00 00 *	7a 02 00 00 00 00 * mov.l	#0x0,er2
-.*:	00 00 *
+.*:	7a 02 00 00[ 	]*mov.l	#0x0,er2
+.*:	00 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 02 00 00 *	7a 02 00 00 00 00 * mov.l	#0x0,er2
-.*:	00 00 *
+.*:	7a 02 00 00[ 	]*mov.l	#0x0,er2
+.*:	00 00 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 02 00 * mov.l	#0x0,@r2
-.*:	00 00 02 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@er2
+.*:	00 00 02 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 02 00 * mov.l	#0x0,@r2
-.*:	00 00 02 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@er2
+.*:	00 00 02 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 02 00 * mov.l	#0x0,@r2
-.*:	00 00 02 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@er2
+.*:	00 00 02 00 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 b2 00 * mov.l	#0x0,@-r2
-.*:	00 00 b2 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@-er2
+.*:	00 00 b2 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 82 00 * mov.l	#0x0,@r2\+
-.*:	00 00 82 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@er2\+
+.*:	00 00 82 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 a2 00 * mov.l	#0x0,@r2-
-.*:	00 00 a2 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@er2-
+.*:	00 00 a2 00 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 22 00 * mov.l	#0x0,@\(0x8:2,r2\)
-.*:	00 00 22 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x8:2,er2\)
+.*:	00 00 22 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 22 00 * mov.l	#0x0,@\(0x8:2,r2\)
-.*:	00 00 22 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x8:2,er2\)
+.*:	00 00 22 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 22 00 * mov.l	#0x0,@\(0x8:2,r2\)
-.*:	00 00 22 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x8:2,er2\)
+.*:	00 00 22 00 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 c2 00 00 10 * mov.l	#0x0,@\(0x10:16,r2\)
-.*:	00 00 c2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,er2\)
+.*:	00 00 c2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 c2 00 00 10 * mov.l	#0x0,@\(0x10:16,r2\)
-.*:	00 00 c2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,er2\)
+.*:	00 00 c2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 c2 00 00 10 * mov.l	#0x0,@\(0x10:16,r2\)
-.*:	00 00 c2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,er2\)
+.*:	00 00 c2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 d2 00 00 10 * mov.l	#0x0,@\(0x10:16,r2l.b\)
-.*:	00 00 d2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,r2l.b\)
+.*:	00 00 d2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 e2 00 00 10 * mov.l	#0x0,@\(0x10:16,r2.w\)
-.*:	00 00 e2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,r2.w\)
+.*:	00 00 e2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 f2 00 00 10 * mov.l	#0x0,@\(0x10:16,er2.l\)
-.*:	00 00 f2 00 *
-.*:	00 10 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x10:16,er2.l\)
+.*:	00 00 f2 00 
+.*:	00 10 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 ca 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,r2\)
-.*:	00 00 ca 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,er2\)
+.*:	00 00 ca 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 ca 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,r2\)
-.*:	00 00 ca 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,er2\)
+.*:	00 00 ca 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 ca 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,r2\)
-.*:	00 00 ca 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,er2\)
+.*:	00 00 ca 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 da 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,r2l.b\)
-.*:	00 00 da 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,r2l.b\)
+.*:	00 00 da 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 ea 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,r2.w\)
-.*:	00 00 ea 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,r2.w\)
+.*:	00 00 ea 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 fa 00 00 01 23 45 * mov.l	#0x0,@\(0x12345:32,er2.l\)
-.*:	00 00 fa 00 *
-.*:	00 01 23 45 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@\(0x12345:32,er2.l\)
+.*:	00 00 fa 00 
+.*:	00 01 23 45 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 40 00 80 00 * mov.l	#0x0,@0x8000:16
-.*:	00 00 40 00 *
-.*:	80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x8000:16
+.*:	00 00 40 00 
+.*:	80 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 40 00 80 00 * mov.l	#0x0,@0x8000:16
-.*:	00 00 40 00 *
-.*:	80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x8000:16
+.*:	00 00 40 00 
+.*:	80 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 40 00 80 00 * mov.l	#0x0,@0x8000:16
-.*:	00 00 40 00 *
-.*:	80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x8000:16
+.*:	00 00 40 00 
+.*:	80 00 
 			.*: R_H8_DIR32	bar
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 48 00 00 01 80 00 * mov.l	#0x0,@0x18000:32
-.*:	00 00 48 00 *
-.*:	00 01 80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x18000:32
+.*:	00 00 48 00 
+.*:	00 01 80 00 
 			.*: R_H8_DIR32	foo
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 48 00 00 01 80 00 * mov.l	#0x0,@0x18000:32
-.*:	00 00 48 00 *
-.*:	00 01 80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x18000:32
+.*:	00 00 48 00 
+.*:	00 01 80 00 
 			.*: R_H8_DIR32	.L1
-.*:	7a 74 00 00 *	7a 74 00 00 00 00 48 00 00 01 80 00 * mov.l	#0x0,@0x18000:32
-.*:	00 00 48 00 *
-.*:	00 01 80 00 *
+.*:	7a 74 00 00[ 	]*mov.l	#0x0,@0x18000:32
+.*:	00 00 48 00 
+.*:	00 01 80 00 
 			.*: R_H8_DIR32	bar
-.*:	79 74 ff ff *	79 74 ff ff 00 00 * mov.w	#0xffff,@r0
-.*:	00 00 *
-.*:	01 5d 00 00 *	01 5d 00 00 * mov.w	#0x0,@r0
-.*:	01 5d 00 01 *	01 5d 00 01 * mov.w	#0x1,@r0
-.*:	01 5d 00 ff *	01 5d 00 ff * mov.w	#0xff,@r0
-.*:	79 74 01 00 *	79 74 01 00 00 00 * mov.w	#0x100,@r0
-.*:	00 00 *
-.*:	7a 74 ff ff *	7a 74 ff ff ff ff 00 00 * mov.l	#0xffffffff,@r0
-.*:	ff ff 00 00 *
-.*:	01 0d 00 00 *	01 0d 00 00 * mov.l	#0x0,@r0
-.*:	01 0d 00 01 *	01 0d 00 01 * mov.l	#0x1,@r0
-.*:	01 0d 00 ff *	01 0d 00 ff * mov.l	#0xff,@r0
-.*:	7a 7c 01 00 *	7a 7c 01 00 00 00 * mov.l	#0x100,@r0
-.*:	00 00 *
+.*:	79 74 ff ff[ 	]*mov.w	#0xffff,@er0
+.*:	00 00 
+.*:	01 5d 00 00[ 	]*mov.w	#0x0,@er0
+.*:	01 5d 00 01[ 	]*mov.w	#0x1,@er0
+.*:	01 5d 00 ff[ 	]*mov.w	#0xff,@er0
+.*:	79 74 01 00[ 	]*mov.w	#0x100,@er0
+.*:	00 00 
+.*:	7a 74 ff ff[ 	]*mov.l	#0xffffffff,@er0
+.*:	ff ff 00 00 
+.*:	01 0d 00 00[ 	]*mov.l	#0x0,@er0
+.*:	01 0d 00 01[ 	]*mov.l	#0x1,@er0
+.*:	01 0d 00 ff[ 	]*mov.l	#0xff,@er0
+.*:	7a 7c 01 00[ 	]*mov.l	#0x100,@er0
+.*:	00 00 
 .* <.*>:
 	\.\.\.
diff --git a/gas/testsuite/gas/h8300/h8sx_rtsl.d b/gas/testsuite/gas/h8300/h8sx_rtsl.d
index 648faf93d5d6..32750585ee42 100644
--- a/gas/testsuite/gas/h8300/h8sx_rtsl.d
+++ b/gas/testsuite/gas/h8300/h8sx_rtsl.d
@@ -5,10 +5,10 @@
 Disassembly of section \.text:
 
 0+00 <\.text>:
- *0:	54 00 *	54 00 * rts/l	er0
- *2:	54 01 *	54 01 * rts/l	er1
- *4:	54 03 *	54 03 * rts/l	er3
- *6:	54 05 *	54 05 * rts/l	er5
- *8:	54 16 *	54 16 * rts/l	er5-er6
- *a:	54 25 *	54 25 * rts/l	er3-er5
- *c:	54 34 *	54 34 * rts/l	er1-er4
+ *0:	54 00 *	rts/l	er0
+ *2:	54 01 *	rts/l	er1
+ *4:	54 03 *	rts/l	er3
+ *6:	54 05 *	rts/l	er5
+ *8:	54 16 *	rts/l	er5-er6
+ *a:	54 25 *	rts/l	er3-er5
+ *c:	54 34 *	rts/l	er1-er4
diff --git a/gas/testsuite/gas/h8300/symaddgen.s b/gas/testsuite/gas/h8300/symaddgen.s
new file mode 100644
index 000000000000..7aef522b8209
--- /dev/null
+++ b/gas/testsuite/gas/h8300/symaddgen.s
@@ -0,0 +1,13 @@
+	.h8300hn
+	.text
+foo:
+	mov.l er6,@-er7
+	mov.w r7,r6
+	mov.w #2000,r2
+	mov.w r2,@-4064:16
+	mov.w #10000,r2
+	mov.w r2,@_var2
+	mov.l @er7+,er6
+	rts
+	.comm _var2,2,2
+	.end
diff --git a/gas/testsuite/gas/h8300/t03_add.exp b/gas/testsuite/gas/h8300/t03_add.exp
index 635daab5162b..fea902f37433 100644
--- a/gas/testsuite/gas/h8300/t03_add.exp
+++ b/gas/testsuite/gas/h8300/t03_add.exp
@@ -2940,7 +2940,7 @@ proc do_t03_add_test {} {
         default	{ fail "$testname: add.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 960 1f44 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/h8300/t04_sub.exp b/gas/testsuite/gas/h8300/t04_sub.exp
index a5d134c40bea..4ec2608a7536 100644
--- a/gas/testsuite/gas/h8300/t04_sub.exp
+++ b/gas/testsuite/gas/h8300/t04_sub.exp
@@ -2939,7 +2939,7 @@ proc do_t04_sub_test {} {
         default	{ fail "$testname: sub.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 959 1f42 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/h8300/t05_cmp.exp b/gas/testsuite/gas/h8300/t05_cmp.exp
index 502cc3031873..26343b7a10be 100644
--- a/gas/testsuite/gas/h8300/t05_cmp.exp
+++ b/gas/testsuite/gas/h8300/t05_cmp.exp
@@ -2800,7 +2800,7 @@ proc do_t05_cmp_test {} {
         default	{ fail "$testname: cmp.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 903 1e00 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/h8300/t08_or.exp b/gas/testsuite/gas/h8300/t08_or.exp
index 617b0263b529..ff50cdc10db1 100644
--- a/gas/testsuite/gas/h8300/t08_or.exp
+++ b/gas/testsuite/gas/h8300/t08_or.exp
@@ -2921,7 +2921,7 @@ proc do_t08_or_test {} {
         default	{ fail "$testname: or.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 954 1f30 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/h8300/t09_xor.exp b/gas/testsuite/gas/h8300/t09_xor.exp
index 21d38a67a670..dd579b567317 100644
--- a/gas/testsuite/gas/h8300/t09_xor.exp
+++ b/gas/testsuite/gas/h8300/t09_xor.exp
@@ -2921,7 +2921,7 @@ proc do_t09_xor_test {} {
         default	{ fail "$testname: xor.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 954 1f30 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/h8300/t10_and.exp b/gas/testsuite/gas/h8300/t10_and.exp
index d4bf5dbe05bc..80625029c8d1 100644
--- a/gas/testsuite/gas/h8300/t10_and.exp
+++ b/gas/testsuite/gas/h8300/t10_and.exp
@@ -2921,7 +2921,7 @@ proc do_t10_and_test {} {
         default	{ fail "$testname: and.l @0x1234:16, ... ($x)" }
     }
     # FIXME return early, expect bombs out on the next group.
-    return;
+    return
     set x 0
     expect {
 	-re ".* 954 1f30 01046B2C" { set x [expr $x+1]; exp_continue; }
diff --git a/gas/testsuite/gas/hppa/basic/basic.exp b/gas/testsuite/gas/hppa/basic/basic.exp
index 67f89d5c96de..5ad43b385935 100644
--- a/gas/testsuite/gas/hppa/basic/basic.exp
+++ b/gas/testsuite/gas/hppa/basic/basic.exp
@@ -1,4 +1,5 @@
-# Copyright (C) 1993, 1996, 1997 Free Software Foundation, Inc.
+# Copyright (C) 1993, 1996, 1997, 1999, 2002
+# Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +13,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -2880,12 +2881,10 @@ proc do_system {} {
 	    -re "^ +\[0-9\]+ 0048 04A41346\[^\n]*\n"	{ set x [expr $x+1] }
 	    -re "^ +\[0-9\]+ 004c 04A41366\[^\n]*\n"	{ set x [expr $x+1] }
 	    -re "^ +\[0-9\]+ 0050 04A41306\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0054 04A41326\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0058 04A41306\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 005c 04A41040\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0060 04A42040\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0064 04A41000\[^\n]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0068 04A42000\[^\n]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0054 04A41040\[^\n]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0058 04A42040\[^\n]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 005c 04A41000\[^\n]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0060 04A42000\[^\n]*\n"	{ set x [expr $x+1] }
 	    -re "\[^\n\]*\n"				{ }
 	    timeout				{ perror "timeout\n"; break }
 	    eof					{ break }
@@ -2897,7 +2896,7 @@ proc do_system {} {
     gas_finish
 
     # Did we find what we were looking for?  If not, flunk it.
-    if [expr $x==27] then { pass $testname } else { fail $testname }
+    if [expr $x==25] then { pass $testname } else { fail $testname }
 }
 
 proc do_system2 {} {
diff --git a/gas/testsuite/gas/hppa/basic/fp_comp.s b/gas/testsuite/gas/hppa/basic/fp_comp.s
index 298e2d66c129..82e3bbd432e8 100644
--- a/gas/testsuite/gas/hppa/basic/fp_comp.s
+++ b/gas/testsuite/gas/hppa/basic/fp_comp.s
@@ -1,3 +1,4 @@
+	.level 1.1
 	.code
 	.align 4
 ; Basic immediate instruction tests.  
diff --git a/gas/testsuite/gas/hppa/basic/special.s b/gas/testsuite/gas/hppa/basic/special.s
index e61ce9aa13f8..7ac1e2eb506a 100644
--- a/gas/testsuite/gas/hppa/basic/special.s
+++ b/gas/testsuite/gas/hppa/basic/special.s
@@ -1,3 +1,4 @@
+	.level 1.1
 	.code
 	.align 4
 	gfw %r4(%sr0,%r5)
diff --git a/gas/testsuite/gas/hppa/basic/system.s b/gas/testsuite/gas/hppa/basic/system.s
index b9846b9e191f..857ea498020a 100644
--- a/gas/testsuite/gas/hppa/basic/system.s
+++ b/gas/testsuite/gas/hppa/basic/system.s
@@ -1,3 +1,4 @@
+	.level 1.1
 	.code
 	.align 4
 ; Basic immediate instruction tests.  
@@ -27,8 +28,6 @@
 	
 	lpa %r4(%sr0,%r5),%r6
 	lpa,m %r4(%sr0,%r5),%r6
-	lha %r4(%sr0,%r5),%r6
-	lha,m %r4(%sr0,%r5),%r6
 	lci %r4(%sr0,%r5),%r6
 
 	idtlba %r4,(%sr0,%r5)
diff --git a/gas/testsuite/gas/hppa/parse/block1.s b/gas/testsuite/gas/hppa/parse/block1.s
index 4f12ab58952d..a3ddafe3c5b4 100644
--- a/gas/testsuite/gas/hppa/parse/block1.s
+++ b/gas/testsuite/gas/hppa/parse/block1.s
@@ -4,7 +4,7 @@
 foo:
 	.block
 bar:
-	.block 0x7fffffff
+	.block 0x3fffffff
 com:
 
 
diff --git a/gas/testsuite/gas/hppa/parse/parse.exp b/gas/testsuite/gas/hppa/parse/parse.exp
index 463c48f15914..ad7bccc2a59b 100644
--- a/gas/testsuite/gas/hppa/parse/parse.exp
+++ b/gas/testsuite/gas/hppa/parse/parse.exp
@@ -1,4 +1,5 @@
-# Copyright (C) 1993, 1996, 1997 Free Software Foundation, Inc.
+# Copyright (C) 1993, 1996, 1997, 1999, 2000, 2001, 2002, 2003
+# Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +13,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
diff --git a/gas/testsuite/gas/hppa/reloc/reloc.exp b/gas/testsuite/gas/hppa/reloc/reloc.exp
index bbcb435482c9..c1b9fa9aa14e 100644
--- a/gas/testsuite/gas/hppa/reloc/reloc.exp
+++ b/gas/testsuite/gas/hppa/reloc/reloc.exp
@@ -1,4 +1,4 @@
-# Copyright 1993, 1996, 1997, 2002 Free Software Foundation, Inc.
+# Copyright 1993, 1996, 1997, 2002, 2004 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -68,7 +68,7 @@ proc do_relocation_reduction_tests {} {
 
     if {[istarget hppa*64*-*-*]
         || [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
-      return;
+      return
     }
 
     if [gas_test_old "reduce.s" "" "Relocation reductions (part1)"] then {
@@ -245,7 +245,7 @@ proc do_selector_scope_test {} {
     set x 0
 
     if [istarget hppa*64*-*-*] then {
-      return;
+      return
     }
 
     if [gas_test_old "selectorbug.s" "" "Test scope of field selector (part 1)"] {
@@ -348,7 +348,7 @@ proc do_exit_relocation_test {} {
     if {[istarget hppa*64*-*-*]
 	|| [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
 	gas_test_old "exitbug.s" "" "Test for bogus R_EXIT relocation (part 1)"
-	return;
+	return
     }
 
     if [gas_test_old "exitbug.s" "" "Test for bogus R_EXIT relocation (part 1)"] {
@@ -381,7 +381,7 @@ proc do_cross_space_fixup_test_1 {} {
     # ELF doesn't really handle extra sections too well...
     if {[istarget hppa*64*-*-*]
 	|| [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
-	return;
+	return
     }
 
     if [gas_test_old "fixupbug.s" "" "Test cross space jump/call fixup bug (part 1)"] {
@@ -415,7 +415,7 @@ proc do_cross_space_fixup_test_2 {} {
     # ELF doesn't really handle extra sections too well...
     if {[istarget hppa*64*-*-*]
 	|| [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
-	return;
+	return
     }
 
     gas_start "fixupbug.s" "-al"
@@ -545,7 +545,7 @@ proc do_function_reloc_bug {} {
 	# Make sure we didn't put anything in the instruction itself!
 	while 1 {
 	    expect {
-	        -re "^0+cc\[^\n\]*ldil 0,r20\[^\n\]*\n" 
+	        -re "^0+cc\[^\n\]*ldil L%0,r20\[^\n\]*\n" 
 		    { set x [expr $x+1] }
 	        -re "^0+d0\[^\n\]*ldo 0\[\(\]+r20\[\)\]+,r19\[^\n\]*\n" 
 		    { set x [expr $x+1] }
@@ -600,7 +600,7 @@ proc do_pic_relocation_test {} {
     # ELF doesn't really handle extra sections too well...
     if {[istarget hppa*64*-*-*]
 	|| [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
-	return;
+	return
     }
 
     gas_start "picreloc.s" "-al"
@@ -629,16 +629,16 @@ proc do_apply_test {} {
     # ELF doesn't really handle extra sections too well...
     if {[istarget hppa*64*-*-*]
 	|| [istarget hppa*-*-*elf*] || [istarget hppa*-*-linux*]} then {
-	return;
+	return
     }
 
     gas_start "applybug.s" "-al"
 
     while 1 {
 	expect {
-	    -re "^ +\[0-9\]+ 0000 00000000\[^\n\]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0004 00000000\[^\n\]*\n"	{ set x [expr $x+1] }
-	    -re "^ +\[0-9\]+ 0008 00000000\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0000 00000044\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0004 00000058\[^\n\]*\n"	{ set x [expr $x+1] }
+	    -re "^ +\[0-9\]+ 0008 0000006C\[^\n\]*\n"	{ set x [expr $x+1] }
 	    -re "\[^\n\]*\n"				{ }
 	    timeout				{ perror "timeout\n"; break }
 	    eof					{ break }
diff --git a/gas/testsuite/gas/hppa/unsorted/unsorted.exp b/gas/testsuite/gas/hppa/unsorted/unsorted.exp
index a63ebe763485..5f09e99281d8 100644
--- a/gas/testsuite/gas/hppa/unsorted/unsorted.exp
+++ b/gas/testsuite/gas/hppa/unsorted/unsorted.exp
@@ -1,4 +1,5 @@
-# Copyright (C) 1993, 1997 Free Software Foundation, Inc.
+# Copyright (C) 1993, 1997, 1999, 2000, 2002, 2004
+# Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +13,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -197,7 +198,7 @@ proc do_import_test {} {
 proc do_common_test {} {
     # linux has a different .comm syntax
     if [istarget hppa*-*-linux*] then {
-	return;
+	return
     }
 
     set testname "common.s: Test for bug in .comm handling (part2)"
diff --git a/gas/testsuite/gas/i386/bss.d b/gas/testsuite/gas/i386/bss.d
new file mode 100644
index 000000000000..ba7493032c8e
--- /dev/null
+++ b/gas/testsuite/gas/i386/bss.d
@@ -0,0 +1,7 @@
+#objdump: -s
+#name: i386 .bss
+
+.*: +file format .*
+
+Contents of section \.other:
+ 0000 0102 .*
diff --git a/gas/testsuite/gas/i386/bss.s b/gas/testsuite/gas/i386/bss.s
new file mode 100644
index 000000000000..f3f1326662e9
--- /dev/null
+++ b/gas/testsuite/gas/i386/bss.s
@@ -0,0 +1,7 @@
+ .data
+ .section .other, "a", @progbits
+ .byte 1
+ .bss
+ .skip 1
+ .previous
+ .byte 2
diff --git a/gas/testsuite/gas/i386/cr-err.l b/gas/testsuite/gas/i386/cr-err.l
new file mode 100644
index 000000000000..4aa1358ac10c
--- /dev/null
+++ b/gas/testsuite/gas/i386/cr-err.l
@@ -0,0 +1,29 @@
+.*: Assembler messages:
+.*:[0-9]+: Error: .\(%cr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%cr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%cr8\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%cr15\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%db0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%db7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%dr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%dr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%tr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(%tr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(cr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(cr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(cr8\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(cr15\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(db0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(db7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(dr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(dr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(tr0\). is not a valid base/index expression
+.*:[0-9]+: Error: .\(tr7\). is not a valid base/index expression
+.*:[0-9]+: Error: .\[cr0\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[cr7\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[cr8\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[cr15\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[dr0\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[dr7\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[tr0\]. is not a valid base/index expression
+.*:[0-9]+: Error: .\[tr7\]. is not a valid base/index expression
diff --git a/gas/testsuite/gas/i386/cr-err.s b/gas/testsuite/gas/i386/cr-err.s
new file mode 100644
index 000000000000..5c45c32aa340
--- /dev/null
+++ b/gas/testsuite/gas/i386/cr-err.s
@@ -0,0 +1,35 @@
+.text
+
+_start:
+	movl	(%cr0), %eax
+	movl	%eax, (%cr7)
+	movl	(%cr8), %eax
+	movl	%eax, (%cr15)
+	movl	(%db0), %eax
+	movl	%eax, (%db7)
+	movl	(%dr0), %eax
+	movl	%eax, (%dr7)
+	movl	(%tr0), %eax
+	movl	%eax, (%tr7)
+
+.att_syntax noprefix
+	movl	(cr0), eax
+	movl	eax, (cr7)
+	movl	(cr8), eax
+	movl	eax, (cr15)
+	movl	(db0), eax
+	movl	eax, (db7)
+	movl	(dr0), eax
+	movl	eax, (dr7)
+	movl	(tr0), eax
+	movl	eax, (tr7)
+
+.intel_syntax noprefix
+	mov	eax, [cr0]
+	mov	[cr7], eax
+	mov	eax, [cr8]
+	mov	[cr15], eax
+	mov	eax, [dr0]
+	mov	[dr7], eax
+	mov	eax, [tr0]
+	mov	[tr7], eax
diff --git a/gas/testsuite/gas/i386/crx.d b/gas/testsuite/gas/i386/crx.d
new file mode 100644
index 000000000000..11e007a9aa13
--- /dev/null
+++ b/gas/testsuite/gas/i386/crx.d
@@ -0,0 +1,20 @@
+#objdump: -dw
+#name: i386 cr8+
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[0-9a-f]+:	f0 0f 20 c0[ 	]+movl?[ 	]+?%cr8,%eax
+[ 	]*[0-9a-f]+:	f0 0f 20 c7[ 	]+movl?[ 	]+?%cr8,%edi
+[ 	]*[0-9a-f]+:	f0 0f 22 c0[ 	]+movl?[ 	]+?%eax,%cr8
+[ 	]*[0-9a-f]+:	f0 0f 22 c7[ 	]+movl?[ 	]+?%edi,%cr8
+[ 	]*[0-9a-f]+:	f0 0f 20 c0[ 	]+movl?[ 	]+?%cr8,%eax
+[ 	]*[0-9a-f]+:	f0 0f 20 c7[ 	]+movl?[ 	]+?%cr8,%edi
+[ 	]*[0-9a-f]+:	f0 0f 22 c0[ 	]+movl?[ 	]+?%eax,%cr8
+[ 	]*[0-9a-f]+:	f0 0f 22 c7[ 	]+movl?[ 	]+?%edi,%cr8
+[ 	]*[0-9a-f]+:	f0 0f 20 c0[ 	]+movl?[ 	]+?%cr8,%eax
+[ 	]*[0-9a-f]+:	f0 0f 20 c7[ 	]+movl?[ 	]+?%cr8,%edi
+[ 	]*[0-9a-f]+:	f0 0f 22 c0[ 	]+movl?[ 	]+?%eax,%cr8
+[ 	]*[0-9a-f]+:	f0 0f 22 c7[ 	]+movl?[ 	]+?%edi,%cr8
diff --git a/gas/testsuite/gas/i386/crx.s b/gas/testsuite/gas/i386/crx.s
new file mode 100644
index 000000000000..e0a78fd12c77
--- /dev/null
+++ b/gas/testsuite/gas/i386/crx.s
@@ -0,0 +1,18 @@
+.text
+_start:
+	movl	%cr8, %eax
+	movl	%cr8, %edi
+	movl	%eax, %cr8
+	movl	%edi, %cr8
+
+.att_syntax noprefix
+	movl	cr8, eax
+	movl	cr8, edi
+	movl	eax, cr8
+	movl	edi, cr8
+
+.intel_syntax noprefix
+	mov	eax, cr8
+	mov	edi, cr8
+	mov	cr8, eax
+	mov	cr8, edi
diff --git a/gas/testsuite/gas/i386/divide.d b/gas/testsuite/gas/i386/divide.d
index be54254be4a7..108742646508 100644
--- a/gas/testsuite/gas/i386/divide.d
+++ b/gas/testsuite/gas/i386/divide.d
@@ -1,3 +1,4 @@
+#as: --divide
 #objdump: -s
 #name: i386 divide
 
diff --git a/gas/testsuite/gas/i386/divide.s b/gas/testsuite/gas/i386/divide.s
index 6a22dedae58b..17433db78864 100644
--- a/gas/testsuite/gas/i386/divide.s
+++ b/gas/testsuite/gas/i386/divide.s
@@ -1,4 +1,6 @@
 start:
  .long 1,2,3,a,b
- a=(.-start)/4-1
+/ This comment should still be allowed with --divide,
+/ but the divide must remain a divide in the next line
+a=(.-start)/4-1 # comment
 b=(.-start)/4
diff --git a/gas/testsuite/gas/i386/equ.d b/gas/testsuite/gas/i386/equ.d
new file mode 100644
index 000000000000..f023abf5650c
--- /dev/null
+++ b/gas/testsuite/gas/i386/equ.d
@@ -0,0 +1,26 @@
+#objdump: -drw
+#name: i386 equates
+#stderr: equ.e
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_start>:
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+\$0xffffffff,%eax
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+0xffffffff,%eax
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+\$0x0,%eax[ 	0-9a-f]+:[ 	a-zA-Z0-9_]+xtrn
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+0x0,%eax[ 	0-9a-f]+:[ 	a-zA-Z0-9_]+xtrn
+[ 0-9a-f]+:[ 	0-9a-f]+test[ 	]+%ecx,%ecx
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+%fs:\(%ecx,%ecx,4\),%ecx
+[ 0-9a-f]+:[ 	0-9a-f]+fadd[ 	]+%st\(1\),%st
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+\$0xfffffffe,%eax
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+0xfffffffe,%eax
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+\$0x0,%eax[ 	0-9a-f]+:[ 	a-zA-Z0-9_]+xtrn
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+0x0,%eax[ 	0-9a-f]+:[ 	a-zA-Z0-9_]+xtrn
+[ 0-9a-f]+:[ 	0-9a-f]+test[ 	]+%edx,%edx
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+%gs:\(%edx,%edx,8\),%edx
+[ 0-9a-f]+:[ 	0-9a-f]+mov[ 	]+%gs:\(%edx,%edx,8\),%edx
+[ 0-9a-f]+:[ 	0-9a-f]+fadd[ 	]+%st\(1\),%st
+[ 0-9a-f]+:[ 	0-9a-f]+fadd[ 	]+%st\(7\),%st
+#pass
diff --git a/gas/testsuite/gas/i386/equ.e b/gas/testsuite/gas/i386/equ.e
new file mode 100644
index 000000000000..8a485d1ee946
--- /dev/null
+++ b/gas/testsuite/gas/i386/equ.e
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:30: Warning: Treating .* as memory reference
diff --git a/gas/testsuite/gas/i386/equ.s b/gas/testsuite/gas/i386/equ.s
new file mode 100644
index 000000000000..1b7a796ad043
--- /dev/null
+++ b/gas/testsuite/gas/i386/equ.s
@@ -0,0 +1,51 @@
+ .text
+_start:
+
+ .att_syntax prefix
+ .equ r, -1
+ .equ s, -1
+	movl	$r, %eax
+	movl	(r), %eax
+ .equ r, xtrn
+	movl	$r, %eax
+	movl	r, %eax
+ .equ r, %ecx
+ .equ s, %fs
+	testl	r, r
+	movl	s:(r,r,4), r
+ .equ x, %st(1)
+	fadd	x
+
+ .if r <> %ecx
+ .err
+ .endif
+ .if r == s
+ .err
+ .endif
+
+ .intel_syntax noprefix
+ .equ r, -2
+ .equ s, -2
+	mov	eax, r
+	mov	eax, [r]
+ .equ r, xtrn
+	mov	eax, offset r
+	mov	eax, [r]
+ .equ r, edx
+ .equ s, gs
+	test	r, r
+	mov	r, s:[r+r*8]
+	mov	r, s:[8*r+r]
+	fadd	x
+ .equ x, st(7)
+	fadd	x
+
+ .if s <> gs
+ .err
+ .endif
+ .if s == x
+ .err
+ .endif
+
+ .equ r, -3
+ .equ s, -3
diff --git a/gas/testsuite/gas/i386/general.l b/gas/testsuite/gas/i386/general.l
index 51bbdf79963c..f0ddfc7d3d87 100644
--- a/gas/testsuite/gas/i386/general.l
+++ b/gas/testsuite/gas/i386/general.l
@@ -285,6 +285,10 @@
  212 021d 67668984 248C0000 		movl	%eax,140\(%esp\)
  212      00
  213                       	
- 214                       		# Force a good alignment.
- 215 0226 00000000 00000000 		.p2align	4,0
- 215      0000
+ 214                       	.code32
+ 215                       	# Make sure that we won't remove movzb by accident.
+ 216 0226 660FB6F8          		movzb	%al,%di
+ 217 022a 0FB6C8            		movzb	%al,%ecx
+ 218                       	
+ 219                       		# Force a good alignment.
+ 220 022d 000000            		.p2align	4,0
diff --git a/gas/testsuite/gas/i386/general.s b/gas/testsuite/gas/i386/general.s
index 3d0403d4f77b..385b47899084 100644
--- a/gas/testsuite/gas/i386/general.s
+++ b/gas/testsuite/gas/i386/general.s
@@ -211,5 +211,10 @@
 	leal	-1760(%ebp),%ebx
 	movl	%eax,140(%esp)
 
+.code32
+# Make sure that we won't remove movzb by accident.
+	movzb	%al,%di
+	movzb	%al,%ecx
+
 	# Force a good alignment.
 	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 3ccb7e2e2bae..a12bc91fb210 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -20,7 +20,7 @@ proc gas_64_check { } {
     global srcdir
 
     catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
-    return [regexp "targets:.*x86-64" $nm_help];
+    return [regexp "targets:.*x86-64" $nm_help]
 }
 
 proc gas_32_check { } {
@@ -29,10 +29,9 @@ proc gas_32_check { } {
     global srcdir
 
     catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
-    return [regexp "targets:.*i386" $nm_help];
+    return [regexp "targets:.*i386" $nm_help]
 }
 
-
 if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]  then {
 
     global ASFLAGS
@@ -42,50 +41,73 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_list_test "float" "-al"
     run_list_test "general" "-al --listing-lhs-width=2"
     run_list_test "inval" "-al"
+    run_list_test "segment" "-al"
+    run_list_test "inval-seg" "-al"
     run_list_test "modrm" "-al --listing-lhs-width=2"
     run_dump_test "naked"
     run_dump_test "opcode"
     run_dump_test "intel"
     run_dump_test "intel16"
+    run_list_test "intelbad" ""
+    run_dump_test "intelok"
     run_dump_test "prefix"
     run_dump_test "amd"
     run_dump_test "katmai"
     run_dump_test "jump"
     run_dump_test "ssemmx2"
     run_dump_test "sse2"
-    run_dump_test "absrel"
-    run_dump_test "pcrel"
     run_dump_test "sub"
     run_dump_test "prescott"
+    run_dump_test "sib"
+    run_dump_test "vmx"
+    run_dump_test "suffix"
+    run_dump_test "immed32"
+    run_dump_test "equ"
     run_dump_test "divide"
     run_dump_test "padlock"
-
-    # PIC is only supported on ELF targets.
-    if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] )
-	 && ![istarget *-*-linux*aout*]
-	 && ![istarget *-*-linux*oldld*] } then {
-	run_dump_test "intelpic"
-    }
+    run_dump_test "crx"
+    run_list_test "cr-err" ""
+    run_dump_test "svme"
+    run_dump_test "merom"
+    run_dump_test "rep"
+    run_dump_test "rep-suffix"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
-    if {[istarget "*-*-elf*"] || [istarget "*-*-linux*"] || [istarget "*-*-coff*"]} then {
+    if {[is_elf_format] || [istarget "*-*-coff*"]} then {
 	run_dump_test "reloc"
 	run_dump_test "jump16"
 	run_list_test "white" "-al --listing-lhs-width=3"
+
+	# These tests should in theory work for PE targets as well,
+	# but the relocs we currently produce are slightly different
+	# from those produced for ELF/COFF based toolchains.
+	# So for now we ignore PE targets.
+	run_dump_test "pcrel"
+	run_dump_test "absrel"
     }
 
-    # Do they only work for ELF?
-    if { ([istarget "*-*-elf*"]		
-	  || [istarget "*-*-linux*"]
-	 && ![istarget *-*-linux*aout*]
-	 && ![istarget *-*-linux*oldld*])
-    } then {
+    # ELF specific tests
+    if [is_elf_format] then {
+	# PIC is only supported on ELF targets.
+	run_dump_test "intelpic"
+
 	run_dump_test "relax"
 	run_dump_test "gotpc"
 	run_dump_test "tlsd"
 	run_dump_test "tlspic"
 	run_dump_test "tlsnopic"
+	run_dump_test "bss"
+	run_dump_test "reloc32"
+	run_list_test "reloc32" "--defsym _bad_=1"
+	run_dump_test "mixed-mode-reloc32"
+    }
+
+    # This is a PE specific test.
+    if { [istarget "*-*-cygwin*"] || [istarget "*-*-pe"]
+	 || [istarget "*-*-mingw*"]
+    } then {
+	run_dump_test "secrel"
     }
 
     set ASFLAGS "$old_ASFLAGS"
@@ -98,8 +120,58 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     set ASFLAGS "$ASFLAGS --64"
 
     run_dump_test "x86_64"
+    run_dump_test "x86-64-addr32"
     run_dump_test "x86-64-opcode"
+    run_dump_test "x86-64-pcrel"
+    run_dump_test "x86-64-rip"
+    run_dump_test "x86-64-stack"
+    run_dump_test "x86-64-stack-intel"
+    run_dump_test "x86-64-stack-suffix"
     run_list_test "x86-64-inval" "-al"
+    run_list_test "x86-64-segment" "-al"
+    run_list_test "x86-64-inval-seg" "-al"
+    run_dump_test "x86-64-branch"
+    run_dump_test "svme64"
+    run_dump_test "x86-64-vmx"
+    run_dump_test "immed64"
+    run_dump_test "x86-64-prescott"
+    run_dump_test "x86-64-crx"
+    run_dump_test "x86-64-crx-suffix"
+    run_dump_test "x86-64-drx"
+    run_dump_test "x86-64-drx-suffix"
+    run_dump_test "x86-64-merom"
+    run_dump_test "x86-64-rep"
+    run_dump_test "x86-64-rep-suffix"
+
+    if { ![istarget "*-*-aix*"]
+      && ![istarget "*-*-beos*"]
+      && ![istarget "*-*-*bsd*"]
+      && ![istarget "*-*-chaos*"]
+      && ![istarget "*-*-kaos*"]
+      && ![istarget "*-*-lynx*"]
+      && ![istarget "*-*-moss*"]
+      && ![istarget "*-*-nto-qnx*"]
+      && ![istarget "*-*-rtems*"]
+      && ![istarget "*-*-sco*"]
+      && ![istarget "*-*-solaris*"]
+      && ![istarget "*-*-sysv*"] } then {
+	run_dump_test "rex"
+    }
+
+    # For ELF targets verify that @unwind works.
+    if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"]
+	  || [istarget "*-*-solaris2.*"])
+	 && ![istarget *-*-linux*aout*]
+	 && ![istarget *-*-linux*oldld*] } then {
+	run_dump_test "x86-64-unwind"
+    }
+
+    # ELF specific tests
+    if [is_elf_format] then {
+	run_dump_test "reloc64"
+	run_list_test "reloc64" "--defsym _bad_=1"
+	run_dump_test "mixed-mode-reloc64"
+    }
 
     set ASFLAGS "$old_ASFLAGS"
 }
diff --git a/gas/testsuite/gas/i386/immed32.d b/gas/testsuite/gas/i386/immed32.d
new file mode 100644
index 000000000000..3d308a833b4a
--- /dev/null
+++ b/gas/testsuite/gas/i386/immed32.d
@@ -0,0 +1,50 @@
+#objdump: -dw
+#name: i386 immed
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+000 <_start>:
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 50 04[ 	]+calll? +\*0x4\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 90 08 00 00 00[ 	]+calll? +\*0x8\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 90 00 00 00 00[ 	]+calll? +\*0x0\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 57 04[ 	]+(addr16 )?calll? +\*4\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 08 00[ 	]+(addr16 )?calll? +\*8\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 97 00 00[ 	]+(addr16 )?calll? +\*0\(%bx\)
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 04[ 	]+movb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 08[ 	]+movb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 00[ 	]+movb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 04 00[ 	]+movw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 08 00[ 	]+movw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 00 00[ 	]+movw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 04 00 00 00[ 	]+movl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 08 00 00 00[ 	]+movl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 00 00 00 00[ 	]+movl? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+04 04[ 	]+addb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+04 08[ 	]+addb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+04 00[ 	]+addb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 83 c0 04[ 	]+addw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 05 08 00[ 	]+addw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 05 00 00[ 	]+addw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+83 c0 04[ 	]+addl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+05 08 00 00 00[ 	]+addl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+05 00 00 00 00[ 	]+addl? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 04[ 	]+shlb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 08[ 	]+shlb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 00[ 	]+shlb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 04[ 	]+shlw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 08[ 	]+shlw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 00[ 	]+shlw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 04[ 	]+shll? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 08[ 	]+shll? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 00[ 	]+shll? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 04[ 	]+inb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 08[ 	]+inb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 00[ 	]+inb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 04[ 	]+inw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 08[ 	]+inw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 00[ 	]+inw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 04[ 	]+inl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 08[ 	]+inl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 00[ 	]+inl? +\$0x0,%eax
diff --git a/gas/testsuite/gas/i386/immed32.s b/gas/testsuite/gas/i386/immed32.s
new file mode 100644
index 000000000000..a0b058f0fe1b
--- /dev/null
+++ b/gas/testsuite/gas/i386/immed32.s
@@ -0,0 +1,47 @@
+	.equiv early, 4
+
+_start:
+	calll	*early(%eax)
+	calll	*late(%eax)
+	calll	*xtrn(%eax)
+	calll	*early(%bx)
+	calll	*late(%bx)
+	calll	*xtrn(%bx)
+	movb	$early, %al
+	movb	$late, %al
+	movb	$xtrn, %al
+	movw	$early, %ax
+	movw	$late, %ax
+	movw	$xtrn, %ax
+	movl	$early, %eax
+	movl	$late, %eax
+	movl	$xtrn, %eax
+	addb	$early, %al
+	addb	$late, %al
+	addb	$xtrn, %al
+	addw	$early, %ax
+	addw	$late, %ax
+	addw	$xtrn, %ax
+	addl	$early, %eax
+	addl	$late, %eax
+	addl	$xtrn, %eax
+	shlb	$early, %al
+	shlb	$late, %al
+	shlb	$xtrn, %al
+	shlw	$early, %ax
+	shlw	$late, %ax
+	shlw	$xtrn, %ax
+	shll	$early, %eax
+	shll	$late, %eax
+	shll	$xtrn, %eax
+	inb	$early, %al
+	inb	$late, %al
+	inb	$xtrn, %al
+	inw	$early, %ax
+	inw	$late, %ax
+	inw	$xtrn, %ax
+	inl	$early, %eax
+	inl	$late, %eax
+	inl	$xtrn, %eax
+
+	.equiv late, 8
diff --git a/gas/testsuite/gas/i386/immed64.d b/gas/testsuite/gas/i386/immed64.d
new file mode 100644
index 000000000000..c2ab3248b7d6
--- /dev/null
+++ b/gas/testsuite/gas/i386/immed64.d
@@ -0,0 +1,59 @@
+#objdump: -dw
+#name: x86-64 immed
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+000 <_start>:
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 50 04[ 	]+callq? +\*0x4\(%rax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 90 08 00 00 00[ 	]+callq? +\*0x8\(%rax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+ff 90 00 00 00 00[ 	]+callq? +\*0x0\(%rax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 50 04[ 	]+(addr32 )?callq? +\*0x4\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 90 08 00 00 00[ 	]+(addr32 )?callq? +\*0x8\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+67 ff 90 00 00 00 00[ 	]+(addr32 )?callq? +\*0x0\(%eax\)
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 04[ 	]+movb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 08[ 	]+movb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+b0 00[ 	]+movb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 04 00[ 	]+movw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 08 00[ 	]+movw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 b8 00 00[ 	]+movw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 04 00 00 00[ 	]+movl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 08 00 00 00[ 	]+movl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+b8 00 00 00 00[ 	]+movl? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 b8 04 00 00 00 00 00 00 00[ 	]+movq? +\$0x4,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 b8 08 00 00 00 00 00 00 00[ 	]+movq? +\$0x8,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 b8 00 00 00 00 00 00 00 00[ 	]+movq? +\$0x0,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+04 04[ 	]+addb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+04 08[ 	]+addb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+04 00[ 	]+addb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 83 c0 04[ 	]+addw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 05 08 00[ 	]+addw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 05 00 00[ 	]+addw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+83 c0 04[ 	]+addl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+05 08 00 00 00[ 	]+addl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+05 00 00 00 00[ 	]+addl? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 83 c0 04[ 	]+addq? +\$0x4,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 05 08 00 00 00[ 	]+addq? +\$0x8,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 05 00 00 00 00[ 	]+addq? +\$0x0,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 04[ 	]+shlb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 08[ 	]+shlb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+c0 e0 00[ 	]+shlb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 04[ 	]+shlw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 08[ 	]+shlw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 c1 e0 00[ 	]+shlw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 04[ 	]+shll? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 08[ 	]+shll? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+c1 e0 00[ 	]+shll? +\$0x0,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 c1 e0 04[ 	]+shlq? +\$0x4,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 c1 e0 08[ 	]+shlq? +\$0x8,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+48 c1 e0 00[ 	]+shlq? +\$0x0,%rax
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 04[ 	]+inb? +\$0x4,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 08[ 	]+inb? +\$0x8,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+e4 00[ 	]+inb? +\$0x0,%al
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 04[ 	]+inw? +\$0x4,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 08[ 	]+inw? +\$0x8,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+66 e5 00[ 	]+inw? +\$0x0,%ax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 04[ 	]+inl? +\$0x4,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 08[ 	]+inl? +\$0x8,%eax
+[ 	]*[0-9a-fA-F]+:[ 	]+e5 00[ 	]+inl? +\$0x0,%eax
diff --git a/gas/testsuite/gas/i386/immed64.s b/gas/testsuite/gas/i386/immed64.s
new file mode 100644
index 000000000000..4e68701e1fa9
--- /dev/null
+++ b/gas/testsuite/gas/i386/immed64.s
@@ -0,0 +1,56 @@
+	.equiv early, 4
+
+_start:
+	callq	*early(%rax)
+	callq	*late(%rax)
+	callq	*xtrn(%rax)
+	callq	*early(%eax)
+	callq	*late(%eax)
+	callq	*xtrn(%eax)
+	movb	$early, %al
+	movb	$late, %al
+	movb	$xtrn, %al
+	movw	$early, %ax
+	movw	$late, %ax
+	movw	$xtrn, %ax
+	movl	$early, %eax
+	movl	$late, %eax
+	movl	$xtrn, %eax
+	movabsq	$early, %rax
+	movabsq	$late, %rax
+	movabsq	$xtrn, %rax
+	addb	$early, %al
+	addb	$late, %al
+	addb	$xtrn, %al
+	addw	$early, %ax
+	addw	$late, %ax
+	addw	$xtrn, %ax
+	addl	$early, %eax
+	addl	$late, %eax
+	addl	$xtrn, %eax
+	addq	$early, %rax
+	addq	$late, %rax
+	addq	$xtrn, %rax
+	shlb	$early, %al
+	shlb	$late, %al
+	shlb	$xtrn, %al
+	shlw	$early, %ax
+	shlw	$late, %ax
+	shlw	$xtrn, %ax
+	shll	$early, %eax
+	shll	$late, %eax
+	shll	$xtrn, %eax
+	shlq	$early, %rax
+	shlq	$late, %rax
+	shlq	$xtrn, %rax
+	inb	$early, %al
+	inb	$late, %al
+	inb	$xtrn, %al
+	inw	$early, %ax
+	inw	$late, %ax
+	inw	$xtrn, %ax
+	inl	$early, %eax
+	inl	$late, %eax
+	inl	$xtrn, %eax
+
+	.equiv late, 8
diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 7365dbaf1a28..02b1a0a197f5 100644
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -1,6 +1,7 @@
 #as: -J
 #objdump: -dw
 #name: i386 intel
+#stderr: intel.e
 
 .*: +file format .*
 
@@ -137,9 +138,9 @@ Disassembly of section .text:
  1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,0x90909090\(%eax\)
  1a9:	8a 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dl
  1af:	8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%edx
- 1b5:	8c 90 90 90 90 90 [ 	]*movl   %ss,0x90909090\(%eax\)
+ 1b5:	8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
  1bb:	8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%edx
- 1c1:	8e 90 90 90 90 90 [ 	]*movl   0x90909090\(%eax\),%ss
+ 1c1:	8e 90 90 90 90 90 [ 	]*movw   0x90909090\(%eax\),%ss
  1c7:	8f 80 90 90 90 90 [ 	]*popl   0x90909090\(%eax\)
  1cd:	90 [ 	]*nop    
  1ce:	91 [ 	]*xchg   %eax,%ecx
@@ -480,144 +481,152 @@ Disassembly of section .text:
  7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
  7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
  7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	66 8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 7da:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e1:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
- 7e8:	66 91 [ 	]*xchg   %ax,%cx
- 7ea:	66 92 [ 	]*xchg   %ax,%dx
- 7ec:	66 93 [ 	]*xchg   %ax,%bx
- 7ee:	66 94 [ 	]*xchg   %ax,%sp
- 7f0:	66 95 [ 	]*xchg   %ax,%bp
- 7f2:	66 96 [ 	]*xchg   %ax,%si
- 7f4:	66 97 [ 	]*xchg   %ax,%di
- 7f6:	66 98 [ 	]*cbtw   
- 7f8:	66 99 [ 	]*cwtd   
- 7fa:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
- 800:	66 9c [ 	]*pushfw 
- 802:	66 9d [ 	]*popfw  
- 804:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
- 80a:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
- 810:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- 812:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
- 814:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
- 818:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
- 81a:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
- 81c:	66 af [ 	]*scas   %es:\(%edi\),%ax
- 81e:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
- 822:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
- 826:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
- 82a:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
- 82e:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
- 832:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
- 836:	66 be 90 90 [ 	]*mov    \$0x9090,%si
- 83a:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83e:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
- 846:	66 c2 90 90 [ 	]*retw   \$0x9090
- 84a:	66 c3 [ 	]*retw   
- 84c:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 853:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 85a:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
- 863:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
- 868:	66 c9 [ 	]*leavew 
- 86a:	66 ca 90 90 [ 	]*lretw  \$0x9090
- 86e:	66 cb [ 	]*lretw  
- 870:	66 cf [ 	]*iretw  
- 872:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 879:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
- 880:	66 e5 90 [ 	]*in     \$0x90,%ax
- 883:	66 e7 90 [ 	]*out    %ax,\$0x90
- 886:	66 e8 8f 90 [ 	]*callw  (0x)?9919.*
- 88a:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
- 890:	66 ed [ 	]*in     \(%dx\),%ax
- 892:	66 ef [ 	]*out    %ax,\(%dx\)
- 894:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89b:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a2:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8aa:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b2:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8ba:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c2:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8ca:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d2:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8da:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e2:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8ea:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f2:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8fa:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 902:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 90a:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 912:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 91a:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 922:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 92a:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
- 932:	66 0f a0 [ 	]*pushw  %fs
- 935:	66 0f a1 [ 	]*popw   %fs
- 938:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 940:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 949:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
- 951:	66 0f a8 [ 	]*pushw  %gs
- 954:	66 0f a9 [ 	]*popw   %gs
- 957:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95f:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 968:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 970:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 978:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 980:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 988:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 990:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 998:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 9a0:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a8:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9b0:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b8:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9c0:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c8:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,0x90909090\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7e7:	66 91 [ 	]*xchg   %ax,%cx
+ 7e9:	66 92 [ 	]*xchg   %ax,%dx
+ 7eb:	66 93 [ 	]*xchg   %ax,%bx
+ 7ed:	66 94 [ 	]*xchg   %ax,%sp
+ 7ef:	66 95 [ 	]*xchg   %ax,%bp
+ 7f1:	66 96 [ 	]*xchg   %ax,%si
+ 7f3:	66 97 [ 	]*xchg   %ax,%di
+ 7f5:	66 98 [ 	]*cbtw   
+ 7f7:	66 99 [ 	]*cwtd   
+ 7f9:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
+ 7ff:	66 9c [ 	]*pushfw 
+ 801:	66 9d [ 	]*popfw  
+ 803:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
+ 809:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
+ 80f:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ 811:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
+ 813:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
+ 817:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
+ 819:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
+ 81b:	66 af [ 	]*scas   %es:\(%edi\),%ax
+ 81d:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
+ 821:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
+ 825:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
+ 829:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
+ 82d:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
+ 831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
+ 835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
+ 839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 845:	66 c2 90 90 [ 	]*retw   \$0x9090
+ 849:	66 c3 [ 	]*retw   
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
+ 867:	66 c9 [ 	]*leavew 
+ 869:	66 ca 90 90 [ 	]*lretw  \$0x9090
+ 86d:	66 cb [ 	]*lretw  
+ 86f:	66 cf [ 	]*iretw  
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 87f:	66 e5 90 [ 	]*in     \$0x90,%ax
+ 882:	66 e7 90 [ 	]*out    %ax,\$0x90
+ 885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
+ 889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
+ 88f:	66 ed [ 	]*in     \(%dx\),%ax
+ 891:	66 ef [ 	]*out    %ax,\(%dx\)
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 931:	66 0f a0 [ 	]*pushw  %fs
+ 934:	66 0f a1 [ 	]*popw   %fs
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 950:	66 0f a8 [ 	]*pushw  %gs
+ 953:	66 0f a9 [ 	]*popw   %gs
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
 
-0+9d0 <gs_foo>:
- 9d0:	c3 [ 	]*ret    
+0+9cf <gs_foo>:
+ 9cf:	c3 [ 	]*ret    
 
-0+9d1 <short_foo>:
- 9d1:	c3 [ 	]*ret    
+0+9d0 <short_foo>:
+ 9d0:	c3 [ 	]*ret    
 
-0+9d2 <bar>:
- 9d2:	e8 f9 ff ff ff [ 	]*call   9d0 <gs_foo>
- 9d7:	e8 f5 ff ff ff [ 	]*call   9d1 <short_foo>
- 9dc:	dd 1c d0 [ 	]*fstpl  \(%eax,%edx,8\)
- 9df:	b9 00 00 00 00 [ 	]*mov    \$0x0,%ecx
- 9e4:	88 04 16 [ 	]*mov    %al,\(%esi,%edx,1\)
- 9e7:	88 04 32 [ 	]*mov    %al,\(%edx,%esi,1\)
- 9ea:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
- 9ed:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
- 9f0:	eb 0c [ 	]*jmp    9fe <rot5>
- 9f2:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
- 9f3:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
- 9fb:	83 e0 f8 [ 	]*and    \$0xfffffff8,%eax
+0+9d1 <bar>:
+ 9d1:	e8 f9 ff ff ff [ 	]*call   9cf <gs_foo>
+ 9d6:	e8 f5 ff ff ff [ 	]*call   9d0 <short_foo>
+ 9db:	dd 1c d0 [ 	]*fstpl  \(%eax,%edx,8\)
+ 9de:	b9 00 00 00 00 [ 	]*mov    \$0x0,%ecx
+ 9e3:	88 04 16 [ 	]*mov    %al,\(%esi,%edx,1\)
+ 9e6:	88 04 32 [ 	]*mov    %al,\(%edx,%esi,1\)
+ 9e9:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
+ 9ec:	88 04 56 [ 	]*mov    %al,\(%esi,%edx,2\)
+ 9ef:	eb 0c [ 	]*jmp    9fd <rot5>
+ 9f1:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
+ 9f2:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 9fa:	83 e0 f8 [ 	]*and    \$0xfffffff8,%eax
 
-0+9fe <rot5>:
- 9fe:	8b 44 ce 04 [ 	]*mov    0x4\(%esi,%ecx,8\),%eax
- a02:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
- a03:	0c 90 [ 	]*or     \$0x90,%al
- a05:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
- a0a:	0e [ 	]*push   %cs
- a0b:	8b 04 5d 00 00 00 00 [ 	]*mov    0x0\(,%ebx,2\),%eax
- a12:	10 14 85 90 90 90 90 [ 	]*adc    %dl,0x90909090\(,%eax,4\)
- a19:	2f [ 	]*das    
- a1a:	ea 90 90 90 90 90 90 [ 	]*ljmp   \$0x9090,\$0x90909090
- a21:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- a23:	70 90 [ 	]*jo     9b5 <foo\+0x9b5>
- a25:	75 fe [ 	]*jne    a25 <rot5\+0x27>
- a27:	0f 6f 35 28 00 00 00 [ 	]*movq   0x28,%mm6
- a2e:	03 3c c3 [ 	]*add    \(%ebx,%eax,8\),%edi
- a31:	0f 6e 44 c3 04 [ 	]*movd   0x4\(%ebx,%eax,8\),%mm0
- a36:	03 bc cb 00 80 00 00 [ 	]*add    0x8000\(%ebx,%ecx,8\),%edi
- a3d:	0f 6e 8c cb 04 80 00 00 [ 	]*movd   0x8004\(%ebx,%ecx,8\),%mm1
- a45:	0f 6e 94 c3 04 00 01 00 [ 	]*movd   0x10004\(%ebx,%eax,8\),%mm2
- a4d:	03 bc c3 00 00 01 00 [ 	]*add    0x10000\(%ebx,%eax,8\),%edi
- a54:	66 8b 04 43 [ 	]*mov    \(%ebx,%eax,2\),%ax
- a58:	66 8b 8c 4b 00 20 00 00 [ 	]*mov    0x2000\(%ebx,%ecx,2\),%cx
- a60:	66 8b 84 43 00 40 00 00 [ 	]*mov    0x4000\(%ebx,%eax,2\),%ax
- a68:	ff e0 [ 	]*jmp    \*%eax
- a6a:	ff 20 [ 	]*jmp    \*\(%eax\)
- a6c:	ff 25 d2 09 00 00 [ 	]*jmp    \*0x9d2
- a72:	e9 5b ff ff ff [ 	]*jmp    9d2 <bar>
+0+9fd <rot5>:
+ 9fd:	8b 44 ce 04 [ 	]*mov    0x4\(%esi,%ecx,8\),%eax
+ a01:	6c [ 	]*insb   \(%dx\),%es:\(%edi\)
+ a02:	0c 90 [ 	]*or     \$0x90,%al
+ a04:	0d 90 90 90 90 [ 	]*or     \$0x90909090,%eax
+ a09:	0e [ 	]*push   %cs
+ a0a:	8b 04 5d 00 00 00 00 [ 	]*mov    0x0\(,%ebx,2\),%eax
+ a11:	10 14 85 90 90 90 90 [ 	]*adc    %dl,0x90909090\(,%eax,4\)
+ a18:	2f [ 	]*das    
+ a19:	ea 90 90 90 90 90 90 [ 	]*ljmp   \$0x9090,\$0x90909090
+ a20:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ a22:	70 90 [ 	]*jo     9b4 <foo\+0x9b4>
+ a24:	75 fe [ 	]*jne    a24 <rot5\+0x27>
+ a26:	0f 6f 35 28 00 00 00 [ 	]*movq   0x28,%mm6
+ a2d:	03 3c c3 [ 	]*add    \(%ebx,%eax,8\),%edi
+ a30:	0f 6e 44 c3 04 [ 	]*movd   0x4\(%ebx,%eax,8\),%mm0
+ a35:	03 bc cb 00 80 00 00 [ 	]*add    0x8000\(%ebx,%ecx,8\),%edi
+ a3c:	0f 6e 8c cb 04 80 00 00 [ 	]*movd   0x8004\(%ebx,%ecx,8\),%mm1
+ a44:	0f 6e 94 c3 04 00 01 00 [ 	]*movd   0x10004\(%ebx,%eax,8\),%mm2
+ a4c:	03 bc c3 00 00 01 00 [ 	]*add    0x10000\(%ebx,%eax,8\),%edi
+ a53:	66 8b 04 43 [ 	]*mov    \(%ebx,%eax,2\),%ax
+ a57:	66 8b 8c 4b 00 20 00 00 [ 	]*mov    0x2000\(%ebx,%ecx,2\),%cx
+ a5f:	66 8b 84 43 00 40 00 00 [ 	]*mov    0x4000\(%ebx,%eax,2\),%ax
+ a67:	ff e0 [ 	]*jmp    \*%eax
+ a69:	ff 20 [ 	]*jmp    \*\(%eax\)
+ a6b:	ff 25 d1 09 00 00 [ 	]*jmp    \*0x9d1
+ a71:	e9 5b ff ff ff [ 	]*jmp    9d1 <bar>
+ a76:	b8 12 00 00 00 [ 	]*mov    \$0x12,%eax
+ a7b:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
+ a80:	25 ff ff fb ff [ 	]*and    \$0xfffbffff,%eax
+ a85:	b0 11 [ 	]*mov    \$0x11,%al
+ a87:	b0 11 [ 	]*mov    \$0x11,%al
+ a89:	b3 47 [ 	]*mov    \$0x47,%bl
+ a8b:	b3 47 [ 	]*mov    \$0x47,%bl
+ a8d:	00 00 .*
 [ 	]*...
diff --git a/gas/testsuite/gas/i386/intel.e b/gas/testsuite/gas/i386/intel.e
new file mode 100644
index 000000000000..9a38e093217d
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel.e
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:154: Warning: Treating .\[0x90909090\]. as memory reference
+.*:155: Warning: Treating .\[0x90909090\]. as memory reference
+.*:156: Warning: Treating .\[0x90909090\]. as memory reference
+.*:157: Warning: Treating .\[0x90909090\]. as memory reference
+.*:492: Warning: Treating .\[0x90909090\]. as memory reference
+.*:493: Warning: Treating .\[0x90909090\]. as memory reference
diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 2a4afb27cbb4..464f4b6d411b 100644
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -520,7 +520,7 @@ foo:
  rcl    word ptr 0x90909090[eax], cl
  in     ax, 0x90
  out    0x90, ax
- call   word ptr .+3+0x9090
+ callw  .+3+0x9090
  jmpw   0x9090,0x9090
  in     ax, dx
  out    dx, ax
@@ -577,7 +577,7 @@ bar:
  call	gs_foo
  call	short_foo
  fstp   QWORD PTR [eax+edx*8]
- mov	ecx, OFFSET FLAT:ss
+ mov	ecx, OFFSET FLAT:xyz
  mov	BYTE PTR [esi+edx], al
  mov	BYTE PTR [edx+esi], al
  mov	BYTE PTR [edx*2+esi], al
@@ -615,4 +615,14 @@ rot5:
  jmp	[eax]
  jmp	[bar]
  jmp	bar
+
+	# Check arithmetic operators
+	mov	%eax,(( 17 ) + 1) 
+	and	%eax,~(1 << ( 18 )) 
+	and	%eax,0xFFFBFFFF
+	mov	%al, (( 0x4711  ) & 0xff) 
+	mov	%al, 0x11
+	mov	%bl, ((( 0x4711  ) >> 8) & 0xff) 
+	mov	%bl, 0x47
+	
  .p2align 4,0
diff --git a/gas/testsuite/gas/i386/intel16.d b/gas/testsuite/gas/i386/intel16.d
index fc74ad0bdaae..495fe14f211b 100644
--- a/gas/testsuite/gas/i386/intel16.d
+++ b/gas/testsuite/gas/i386/intel16.d
@@ -1,5 +1,6 @@
 #objdump: -dw -mi8086
 #name: i386 intel16
+#stderr: intel16.e
 
 .*: +file format .*
 
@@ -12,4 +13,12 @@ Disassembly of section .text:
   11:	66 0f b7 06 00 00 [ 	]*movzwl 0,%eax
   17:	66 0f b6 06 00 00 [ 	]*movzbl 0,%eax
   1d:	0f b6 06 00 00 [ 	]*movzbw 0,%ax
+  22:	8d 00 [ 	]*lea    \(%bx,%si\),%ax
+  24:	8d 02 [ 	]*lea    \(%bp,%si\),%ax
+  26:	8d 01 [ 	]*lea    \(%bx,%di\),%ax
+  28:	8d 03 [ 	]*lea    \(%bp,%di\),%ax
+  2a:	8d 00 [ 	]*lea    \(%bx,%si\),%ax
+  2c:	8d 02 [ 	]*lea    \(%bp,%si\),%ax
+  2e:	8d 01 [ 	]*lea    \(%bx,%di\),%ax
+  30:	8d 03 [ 	]*lea    \(%bp,%di\),%ax
 	...
diff --git a/gas/testsuite/gas/i386/intel16.e b/gas/testsuite/gas/i386/intel16.e
new file mode 100644
index 000000000000..62da8a775ebd
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel16.e
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*:5: Warning: Treating .word ptr \[0\]. as memory reference
+.*:6: Warning: Treating .byte ptr \[0\]. as memory reference
+.*:7: Warning: Treating .byte ptr \[0\]. as memory reference
+.*:8: Warning: Treating .word ptr \[0\]. as memory reference
+.*:9: Warning: Treating .byte ptr \[0\]. as memory reference
+.*:10: Warning: Treating .byte ptr \[0\]. as memory reference
diff --git a/gas/testsuite/gas/i386/intel16.s b/gas/testsuite/gas/i386/intel16.s
index bf78ad86211b..e27b017310d3 100644
--- a/gas/testsuite/gas/i386/intel16.s
+++ b/gas/testsuite/gas/i386/intel16.s
@@ -8,4 +8,14 @@
  movzx	eax,word ptr [0]
  movzx	eax,byte ptr [0]
  movzx	ax,byte ptr [0]
+
+ lea	ax, [si+bx]
+ lea	ax, [si+bp]
+ lea	ax, [di+bx]
+ lea	ax, [di+bp]
+ lea	ax, [si][bx]
+ lea	ax, [si][bp]
+ lea	ax, [di][bx]
+ lea	ax, [di][bp]
+
  .p2align 4,0
diff --git a/gas/testsuite/gas/i386/intelbad.l b/gas/testsuite/gas/i386/intelbad.l
new file mode 100644
index 000000000000..198420a0d810
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelbad.l
@@ -0,0 +1,129 @@
+.*: Assembler messages:
+.*:4: (Warning|Error): .*
+.*:5: Error: .*
+.*:6: Error: .*
+.*:7: Error: .*
+.*:10: Error: .*
+.*:13: Error: .*
+.*:15: Error: .*
+.*:18: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:40: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:56: (Warning|Error): .*
+.*:57: Error: .*
+.*:58: Error: .*
+.*:59: Error: .*
+.*:60: Error: .*
+.*:61: Error: .*
+.*:62: Error: .*
+.*:67: Error: .*
+.*:73: Error: .*
+.*:74: Error: .*
+.*:75: Error: .*
+.*:77: Error: .*
+.*:78: Error: .*
+.*:89: Error: .*
+.*:90: Error: .*
+.*:91: Error: .*
+.*:94: Error: .*
+.*:95: Error: .*
+.*:96: Error: .*
+.*:97: Error: .*
+.*:98: Error: .*
+.*:99: Error: .*
+.*:100: Error: .*
+.*:101: Error: .*
+.*:102: Error: .*
+.*:103: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:106: Error: .*
+.*:107: Error: .*
+.*:108: Error: .*
+.*:109: Error: .*
+.*:110: Error: .*
+.*:111: Error: .*
+.*:112: Error: .*
+.*:113: Error: .*
+.*:114: Error: .*
+.*:115: Error: .*
+.*:117: Error: .*
+.*:118: Error: .*
+.*:119: Error: .*
+.*:120: Error: .*
+.*:121: Error: .*
+.*:122: Error: .*
+.*:124: Error: .*
+.*:125: Error: .*
+.*:126: Error: .*
+.*:127: Error: .*
+.*:128: Error: .*
+.*:129: Error: .*
+.*:131: Error: .*
+.*:132: Error: .*
+.*:133: Error: .*
+.*:134: Error: .*
+.*:135: Error: .*
+.*:136: Error: .*
+.*:138: Error: .*
+.*:139: Error: .*
+.*:140: Error: .*
+.*:141: Error: .*
+.*:142: Error: .*
+.*:143: Error: .*
+.*:144: Error: .*
+.*:145: Error: .*
+.*:147: Error: .*
+.*:148: Error: .*
+.*:149: Error: .*
+.*:150: Error: .*
+.*:151: Error: .*
+#...
+.*:152: Error: .*
+#...
+.*:153: Error: .*
+.*:154: Error: .*
+.*:155: Error: .*
+.*:156: Error: .*
+.*:158: Error: .*
+.*:159: Error: .*
+.*:160: Error: .*
+.*:161: Warning: .*
+.*:162: Warning: .*
+.*:164: Error: .*
+.*:165: Warning: .*
+.*:165: Error: .*
diff --git a/gas/testsuite/gas/i386/intelbad.s b/gas/testsuite/gas/i386/intelbad.s
new file mode 100644
index 000000000000..f3bb96dcfb33
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelbad.s
@@ -0,0 +1,165 @@
+	.intel_syntax noprefix
+	.text
+start:
+	add	eax, byte ptr [eax]
+	add	eax, qword ptr [eax]
+	add	[eax], 1
+	add	qword ptr [eax], 1
+	addpd	xmm0, dword ptr [eax]
+	addpd	xmm0, qword ptr [eax]
+	addpd	xmm0, tbyte ptr [eax]
+	addps	xmm0, dword ptr [eax]
+	addps	xmm0, qword ptr [eax]
+	addps	xmm0, tbyte ptr [eax]
+	addsd	xmm0, dword ptr [eax]
+	addsd	xmm0, tbyte ptr [eax]
+	addsd	xmm0, xmmword ptr [eax]
+	addss	xmm0, qword ptr [eax]
+	addss	xmm0, tbyte ptr [eax]
+	addss	xmm0, xmmword ptr [eax]
+	call	byte ptr [eax]
+	call	qword ptr [eax]
+	call	tbyte ptr [eax]
+	call	xword ptr [eax]
+	cmps	[esi], es:[edi]
+	cmps	dword ptr [esi], word ptr es:[edi]
+	cmpxchg8b dword ptr [eax]
+	fadd	[eax]
+	fadd	word ptr [eax]
+	fadd	tbyte ptr [eax]
+	fbld	byte ptr [eax]
+	fbld	word ptr [eax]
+	fbstp	dword ptr [eax]
+	fbstp	qword ptr [eax]
+	fiadd	[eax]
+	fiadd	byte ptr [eax]
+	fild	[eax]
+	fild	byte ptr [eax]
+	fild	tbyte ptr [eax]
+	fist	[eax]
+	fist	byte ptr [eax]
+	fist	qword ptr [eax]
+	fistp	[eax]
+	fistp	byte ptr [eax]
+	fisttp	[eax]
+	fisttp	byte ptr [eax]
+	fld	[eax]
+	fld	word ptr [eax]
+	fldcw	dword ptr [eax]
+	fst	[eax]
+	fst	word ptr [eax]
+	fst	tbyte ptr [eax]
+	fstp	[eax]
+	fstp	word ptr [eax]
+	ins	es:[edi], dx
+	lds	ax, word ptr [eax]
+	lds	eax, dword ptr [eax]
+	lods	[esi]
+	movs	es:[edi], [esi]
+	movs	dword ptr es:[edi], word ptr [esi]
+	movsx	eax, [eax]
+	movsx	eax, dword ptr [eax]
+	outs	dx, [esi]
+	paddb	mm0, dword ptr [eax]
+	paddb	mm0, xmmword ptr [eax]
+	paddb	xmm0, dword ptr [eax]
+	paddb	xmm0, qword ptr [eax]
+	pinsrw	mm0, byte ptr [eax], 3
+	pinsrw	mm0, dword ptr [eax], 3
+	pinsrw	mm0, qword ptr [eax], 3
+	pinsrw	xmm0, dword ptr [eax], 7
+	pinsrw	xmm0, qword ptr [eax], 7
+	pinsrw	xmm0, xmmword ptr [eax], 7
+	push	byte ptr [eax]
+	push	qword ptr [eax]
+	scas	es:[edi]
+#XXX?	shl	eax
+	stos	es:[edi]
+	xlat	word ptr [ebx]
+#XXX?	xlatb	[ebx]
+
+	# expressions
+#XXX?	push	~ 1
+#XXX?	push	1 % 1
+#XXX?	push	1 << 1
+#XXX?	push	1 >> 1
+#XXX?	push	1 & 1
+#XXX?	push	1 ^ 1
+#XXX?	push	1 | 1
+	push	1 1
+	push	1 +
+	push	1 * * 1
+
+	# memory references
+	mov	eax, [ecx*3]
+	mov	eax, [3*ecx]
+	mov	eax, [-1*ecx + 1]
+	mov	eax, [esp + esp]
+	mov	eax, [eax - 1*ecx + 1]
+	mov	eax, [(eax-1) * (eax-1)]
+	mov	eax, [eax-1 xor eax-1]
+	mov	eax, [(eax-1) xor (eax-1)]
+	mov	eax, [not eax + 1]
+	mov	eax, [ecx*2 + edx*4]
+	mov	eax, [2*ecx + 4*edx]
+	mov	eax, [eax]1[ecx]		# ugly diag
+	mov	eax, [eax][ecx]1		# ugly diag
+	mov	eax, eax[ecx]			# ugly diag
+	mov	eax, es[ecx]
+	mov	eax, cr0[ecx]
+	mov	eax, [eax]ecx
+	mov	eax, [eax]+ecx
+	mov	eax, [eax]+ecx*2
+	mov	eax, [eax]+2*ecx
+	mov	eax, [[eax]ecx]
+	mov	eax, eax:[ecx]
+
+	mov	eax, [ss]
+	mov	eax, [st]
+	mov	eax, [mm0]
+	mov	eax, [xmm0]
+	mov	eax, [cr0]
+	mov	eax, [dr7]
+
+	mov	eax, [ss+edx]
+	mov	eax, [st+edx]
+	mov	eax, [mm0+edx]
+	mov	eax, [xmm0+edx]
+	mov	eax, [cr0+edx]
+	mov	eax, [dr7+edx]
+
+	mov	eax, [edx+ss]
+	mov	eax, [edx+st]
+	mov	eax, [edx+cr0]
+	mov	eax, [edx+dr7]
+	mov	eax, [edx+mm0]
+	mov	eax, [edx+xmm0]
+
+	lea	eax, [bx+si*1]
+	lea	eax, [bp+si*2]
+	lea	eax, [bx+di*4]
+	lea	eax, [bp+di*8]
+	lea	eax, [bx+1*si]
+	lea	eax, [bp+2*si]
+	lea	eax, [bx+4*di]
+	lea	eax, [bp+8*di]
+
+	mov	eax, [ah]
+	mov	eax, [ax]
+	mov	eax, [eax+bx]
+	mov	eax, offset [1*eax]
+	mov	eax, offset 1*eax
+	mov	eax, offset x[eax]		# ugly diag
+	mov	eax, offset [x][eax]		# ugly diag
+	mov	eax, flat x
+	mov	eax, flat [x]
+	mov	eax, es:eax
+
+	mov	eax, offset [eax]
+	mov	eax, offset eax
+	mov	eax, offset offset eax
+	mov	eax, es:ss:[eax]
+	mov	eax, es:[eax]+ss:[eax]
+
+	mov	eax, 3:5
+	call	3:[5]
diff --git a/gas/testsuite/gas/i386/intelok.d b/gas/testsuite/gas/i386/intelok.d
new file mode 100644
index 000000000000..8e7fdbf75447
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelok.d
@@ -0,0 +1,176 @@
+#as: -J --divide
+#objdump: -dwMintel
+#name: i386 intel-ok
+#stderr: intelok.e
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <start>:
+[ 	]*[0-9a-f]+:[ 	]+02 00[ 	]+add[ 	]+al,(BYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	02 00[ 	]+add[ 	]+al,(BYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 03 00[ 	]+add[ 	]+ax,(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 03 00[ 	]+add[ 	]+ax,(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	03 00[ 	]+add[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	03 00[ 	]+add[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	80 00 01[ 	]+add[ 	]+BYTE PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	83 00 01[ 	]+add[ 	]+DWORD PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	66 83 00 01[ 	]+add[ 	]+WORD PTR \[eax\],0x1
+[ 	]*[0-9a-f]+:	66 0f 58 00[ 	]+addpd[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 0f 58 00[ 	]+addpd[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f 58 00[ 	]+addps[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f 58 00[ 	]+addps[ 	]+xmm0,XMMWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f2 0f 58 00[ 	]+addsd[ 	]+xmm0,QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f2 0f 58 00[ 	]+addsd[ 	]+xmm0,QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f3 0f 58 00[ 	]+addss[ 	]+xmm0,DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	f3 0f 58 00[ 	]+addss[ 	]+xmm0,DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 ff 10[ 	]+call[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	ff 10[ 	]+call[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	ff 18[ 	]+call[ 	]+FWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	a6[ 	]+cmps[ 	]+(BYTE PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	a7[ 	]+cmps[ 	]+(DWORD PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	66 a7[ 	]+cmps[ 	]+(WORD PTR )(ds:)?\[esi\],(\1)?es:\[edi\]
+[ 	]*[0-9a-f]+:	0f c7 08[ 	]+cmpxchg8b[ 	]+(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	d8 00[ 	]+fadd[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dc 00[ 	]+fadd[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 20[ 	]+fbld[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	df 20[ 	]+fbld[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	df 30[ 	]+fbstp[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	df 30[ 	]+fbstp[ 	]+(TBYTE PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	da 00[ 	]+fiadd[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	de 00[ 	]+fiadd[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 00[ 	]+fild[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 28[ 	]+fild[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 00[ 	]+fild[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 10[ 	]+fist[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 10[ 	]+fist[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 18[ 	]+fistp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 38[ 	]+fistp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 18[ 	]+fistp[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 08[ 	]+fisttp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 08[ 	]+fisttp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	df 08[ 	]+fisttp[ 	]+WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 00[ 	]+fld[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 00[ 	]+fld[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 28[ 	]+fld[ 	]+TBYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 28[ 	]+fldcw[ 	]+(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	d9 28[ 	]+fldcw[ 	]+(WORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	d9 20[ 	]+fldenvd?[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	d9 20[ 	]+fldenvd?[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	66 d9 20[ 	]+fldenvw[ 	]+\[eax\]
+[ 	]*[0-9a-f]+:	d9 10[ 	]+fst[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 10[ 	]+fst[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d9 18[ 	]+fstp[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	dd 18[ 	]+fstp[ 	]+QWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	db 38[ 	]+fstp[ 	]+TBYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	66 c5 00[ 	]+lds[ 	]+ax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	c5 00[ 	]+lds[ 	]+eax,(FWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 c5 00[ 	]+lds[ 	]+ax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	c5 00[ 	]+lds[ 	]+eax,(FWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	8d 00[ 	]+lea[ 	]+eax,\[eax\]
+[ 	]*[0-9a-f]+:	0f 01 10[ 	]+lgdtd?[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	0f 01 10[ 	]+lgdtd?[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f 01 10[ 	]+lgdtw[ 	]+(PWORD PTR)?\[eax\]
+[ 	]*[0-9a-f]+:	a4[ 	]+movs[ 	]+(BYTE PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	a5[ 	]+movs[ 	]+(DWORD PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	66 a5[ 	]+movs[ 	]+(WORD PTR )es:\[edi\],(\1)?(ds:)?\[esi\]
+[ 	]*[0-9a-f]+:	0f be 00[ 	]+movsx[ 	]+eax,BYTE PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f bf 00[ 	]+movsx[ 	]+eax,WORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	0f fc 00[ 	]+paddb[ 	]+mm0,(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	0f fc 00[ 	]+paddb[ 	]+mm0,(QWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f fc 00[ 	]+paddb[ 	]+xmm0,(XMMWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	66 0f fc 00[ 	]+paddb[ 	]+xmm0,(XMMWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	0f c4 00 03[ 	]+pinsrw[ 	]+mm0,(WORD PTR )?\[eax\],0x3
+[ 	]*[0-9a-f]+:	66 0f c4 00 07[ 	]+pinsrw[ 	]+xmm0,(WORD PTR )?\[eax\],0x7
+[ 	]*[0-9a-f]+:	ff 30[ 	]+push[ 	]+DWORD PTR \[eax\]
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	d7[ 	]+xlat(b|[ 	]+(BYTE PTR )?(ds:)?\[ebx\])
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+4\]
+[ 	]*[0-9a-f]+:	8b 40 04[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+4\]
+[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+6\]
+[ 	]*[0-9a-f]+:	8b 40 06[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+6\]
+[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+12\]
+[ 	]*[0-9a-f]+:	8b 40 0c[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+12\]
+[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+18\]
+[ 	]*[0-9a-f]+:	8b 40 12[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+18\]
+[ 	]*[0-9a-f]+:	8b 04 85 02 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
+[ 	]*[0-9a-f]+:	8b 04 85 02 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*4\+(0x)?2\]
+[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\]
+[ 	]*[0-9a-f]+:	8b 04 45 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\*2\]
+[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\]
+[ 	]*[0-9a-f]+:	8b 04 8d 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[ecx\*4\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 fb[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\-5\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 0f[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+15\]
+[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+16\]
+[ 	]*[0-9a-f]+:	8b 40 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+16\]
+[ 	]*[0-9a-f]+:	8b 44 08 10[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+16\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 44 08 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\+1\]
+[ 	]*[0-9a-f]+:	8b 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8b 04 08[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\]
+[ 	]*[0-9a-f]+:	8b 04 08[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+ecx\]
+[ 	]*[0-9a-f]+:	26 8b 00[ 	]+mov[ 	]+eax,(DWORD PTR )?es:\[eax\]
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a ff[ 	]+push[ 	]+0xffffffff
+[ 	]*[0-9a-f]+:	6a fe[ 	]+push[ 	]+0xfffffffe
+[ 	]*[0-9a-f]+:	6a 02[ 	]+push[ 	]+0x2
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 04[ 	]+push[ 	]+0x4
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 08[ 	]+push[ 	]+0x8
+[ 	]*[0-9a-f]+:	6a 01[ 	]+push[ 	]+0x1
+[ 	]*[0-9a-f]+:	6a 02[ 	]+push[ 	]+0x2
+[ 	]*[0-9a-f]+:	6a 03[ 	]+push[ 	]+0x3
+[ 	]*[0-9a-f]+:	6a 0d[ 	]+push[ 	]+0xd
+[ 	]*[0-9a-f]+:	6a 04[ 	]+push[ 	]+0x4
+[ 	]*[0-9a-f]+:	6a fc[ 	]+push[ 	]+0xfffffffc
+[ 	]*[0-9a-f]+:	6a fb[ 	]+push[ 	]+0xfffffffb
+[ 	]*[0-9a-f]+:	6a fb[ 	]+push[ 	]+0xfffffffb
+[ 	]*[0-9a-f]+:	6a 03[ 	]+push[ 	]+0x3
+[ 	]*[0-9a-f]+:	6a 04[ 	]+push[ 	]+0x4
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	b8 00 00 00 00[ 	]+mov[ 	]+eax,0x0
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1]
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8b 80 01 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+(0x)?1\]
+[ 	]*[0-9a-f]+:	8b 80 00 00 00 00[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\]
+[ 	]*[0-9a-f]+:	8b 40 01[ 	]+mov[ 	]+eax,(DWORD PTR )?\[eax\+1\]
+[ 	]*[0-9a-f]+:	a1 01 00 00 00[ 	]+mov[ 	]+eax,ds:0x1
+[ 	]*[0-9a-f]+:	a1 ff ff ff ff[ 	]+mov[ 	]+eax,ds:0xffffffff
+[ 	]*[0-9a-f]+:	26 a1 02 00 00 00[ 	]+mov[ 	]+eax,es:0x2
+#...
+[ 	]*[0-9a-f]+:	b8 03 00 00 00[ 	]+mov[ 	]+eax,0x3
+[ 	]*[0-9a-f]+:	a1 04 00 00 00[ 	]+mov[ 	]+eax,ds:0x4
+[ 	]*[0-9a-f]+:	a1 05 00 00 00[ 	]+mov[ 	]+eax,ds:0x5
+[ 	]*[0-9a-f]+:	36 a1 06 00 00 00[ 	]+mov[ 	]+eax,ss:0x6
+[ 	]*[0-9a-f]+:	36 a1 07 00 00 00[ 	]+mov[ 	]+eax,ss:0x7
+[ 	]*[0-9a-f]+:	a1 08 00 00 00[ 	]+mov[ 	]+eax,ds:0x8
+[ 	]*[0-9a-f]+:	9a 05 00 00 00 03 00[ 	]+l?call[ 	]+0x3[,:]0x5
+[ 	]*[0-9a-f]+:	ea 03 00 00 00 05 00[ 	]+l?jmp[ 	]+0x5[,:]0x3
+[ 	]*[0-9a-f]+:	ff 15 00 00 00 00[ 	]+call[ 	]+(DWORD PTR )?(ds:)?0x0
+[ 	]*[0-9a-f]+:	66 ff 25 00 00 00 00[ 	]+jmp[ 	]+(WORD PTR )?(ds:)?0x0
+#pass
diff --git a/gas/testsuite/gas/i386/intelok.e b/gas/testsuite/gas/i386/intelok.e
new file mode 100644
index 000000000000..8403bf218e82
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelok.e
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:170: Warning: .* taken to mean just .*
+.*:177: Warning: Treating .* as memory reference
+.*:178: Warning: .* taken to mean just .*
+.*:178: Warning: Treating .* as memory reference
+.*:181: Warning: Treating .* as memory reference
+.*:182: Warning: Treating .* as memory reference
+.*:185: Warning: Treating .* as memory reference
diff --git a/gas/testsuite/gas/i386/intelok.s b/gas/testsuite/gas/i386/intelok.s
new file mode 100644
index 000000000000..c46a17874856
--- /dev/null
+++ b/gas/testsuite/gas/i386/intelok.s
@@ -0,0 +1,194 @@
+	.intel_syntax noprefix
+	.equiv byte, 1
+	.equiv word, 2
+	.equiv dword, 4
+	.equiv fword, 6
+	.equiv qword, 8
+	.equiv tbyte, 10
+	.equiv oword, 16
+	.equiv xmmword, 16
+	.text
+start:
+
+	# operand sizes
+
+	add	al, [eax]
+	add	al, byte ptr [eax]
+	add	ax, [eax]
+	add	ax, word ptr [eax]
+	add	eax, [eax]
+	add	eax, dword ptr [eax]
+	add	byte ptr [eax], 1
+	add	dword ptr [eax], 1
+	add	word ptr [eax], 1
+	addpd	xmm0, [eax]
+	addpd	xmm0, xmmword ptr [eax]
+	addps	xmm0, [eax]
+	addps	xmm0, xmmword ptr [eax]
+	addsd	xmm0, [eax]
+	addsd	xmm0, qword ptr [eax]
+	addss	xmm0, [eax]
+	addss	xmm0, dword ptr [eax]
+	call	word ptr [eax]
+	call	dword ptr [eax]
+	call	fword ptr [eax]
+	cmps	[esi], byte ptr es:[edi]
+	cmps	dword ptr [esi], es:[edi]
+	cmps	word ptr [esi], word ptr es:[edi]
+	cmpxchg8b qword ptr [eax]
+	fadd	dword ptr [eax]
+	fadd	qword ptr [eax]
+	fbld	[eax]
+	fbld	tbyte ptr [eax]
+	fbstp	[eax]
+	fbstp	tbyte ptr [eax]
+	fiadd	dword ptr [eax]
+	fiadd	word ptr [eax]
+	fild	dword ptr [eax]
+	fild	qword ptr [eax]
+	fild	word ptr [eax]
+	fist	dword ptr [eax]
+	fist	word ptr [eax]
+	fistp	dword ptr [eax]
+	fistp	qword ptr [eax]
+	fistp	word ptr [eax]
+	fisttp	dword ptr [eax]
+	fisttp	qword ptr [eax]
+	fisttp	word ptr [eax]
+	fld	dword ptr [eax]
+	fld	qword ptr [eax]
+	fld	tbyte ptr [eax]
+	fldcw	[eax]
+	fldcw	word ptr [eax]
+	fldenv	[eax]
+	fldenvd	[eax]
+	fldenvw	[eax]
+	fst	dword ptr [eax]
+	fst	qword ptr [eax]
+	fstp	dword ptr [eax]
+	fstp	qword ptr [eax]
+	fstp	tbyte ptr [eax]
+	lds	ax, [eax]
+	lds	eax, [eax]
+	lds	ax, dword ptr [eax]
+	lds	eax, fword ptr [eax]
+	lea	eax, [eax]
+	lea	eax, byte ptr [eax]
+	lea	eax, dword ptr [eax]
+	lea	eax, fword ptr [eax]
+	lea	eax, qword ptr [eax]
+	lea	eax, tbyte ptr [eax]
+	lea	eax, word ptr [eax]
+	lea	eax, xmmword ptr [eax]
+	lgdt	[eax]
+	lgdtd	[eax]
+	lgdtw	[eax]
+	movs	es:[edi], byte ptr [esi]
+	movs	dword ptr es:[edi], [esi]
+	movs	word ptr es:[edi], word ptr [esi]
+	movsx	eax, byte ptr [eax]
+	movsx	eax, word ptr [eax]
+	paddb	mm0, [eax]
+	paddb	mm0, qword ptr [eax]
+	paddb	xmm0, [eax]
+	paddb	xmm0, xmmword ptr [eax]
+	pinsrw	mm0, word ptr [eax], 3
+	pinsrw	xmm0, word ptr [eax], 7
+	push	dword ptr [eax]
+	xlat	[ebx]
+	xlat	byte ptr [ebx]
+	xlatb
+
+	# memory operands
+
+	mov	eax, dword ptr [byte+eax]
+	mov	eax, dword ptr byte[eax]
+	mov	eax, [dword+eax]
+	mov	eax, dword[eax]
+	mov	eax, [fword+eax]
+	mov	eax, fword[eax]
+	mov	eax, [qword+eax+dword]
+	mov	eax, qword[eax+dword]
+	mov	eax, [tbyte+eax+dword*2]
+	mov	eax, tbyte[eax+dword*2]
+	mov	eax, [word+eax*dword]
+	mov	eax, word[eax*dword]
+
+	mov	eax, [eax*+2]
+	mov	eax, [+2*eax]
+	mov	eax, [ecx*dword]
+	mov	eax, [dword*ecx]
+	mov	eax, 1[eax]
+	mov	eax, [eax]+1
+	mov	eax, [eax - 5 + ecx]
+	mov	eax, [eax + 5 and 3 + ecx]
+	mov	eax, [eax + 5*3 + ecx]
+	mov	eax, [oword][eax]
+	mov	eax, [eax][oword]
+	mov	eax, xmmword[eax][ecx]
+	mov	eax, [eax]+1[ecx]
+	mov	eax, [eax][ecx]+1
+	mov	eax, [1][eax][ecx]
+	mov	eax, [eax][1][ecx]
+	mov	eax, [eax][ecx][1]
+	mov	eax, [[eax]]
+	mov	eax, [eax[ecx]]
+	mov	eax, [[eax][ecx]]
+	mov	eax, es:[eax]
+
+	# expressions
+
+	push	+ 1
+	push	- 1
+	push	not 1
+	push	1 + 1
+	push	2 - 1
+	push	2 * 2
+	push	3 / 2
+	push	3 mod 2
+	push	4 shl 1
+	push	5 shr 2
+	push	6 and 3
+	push	7 xor 4
+	push	8 or 5
+
+	push	+dword
+	push	-dword
+	push	not dword
+	push	not +dword
+	push	not -dword
+	push	not not dword
+
+	# offset expressions
+
+	mov	eax, offset x
+	mov	eax, offset flat:x
+	mov	eax, flat:x
+	mov	eax, offset [x]
+	mov	eax, offset flat:[x]
+	mov	eax, flat:[x]
+	mov	eax, [offset x]
+	mov	eax, [eax + offset x]
+	mov	eax, [eax + offset 1]
+	mov	eax, [offset x + eax]
+	mov	eax, offset x+1[eax]
+	mov	eax, [eax] + offset x
+	mov	eax, [eax] + offset 1
+	mov	eax, offset x + [1]
+	mov	eax, [offset x] - [1]
+	mov	eax, offset x + es:[2]
+	mov	eax, offset x + offset es:[3]
+	mov	eax, [4] + offset x
+	mov	eax, [5] + [offset x]
+	mov	eax, ss:[6] + offset x
+	mov	eax, ss:[7] + [offset x]
+	mov	eax, dword ptr [8]
+
+	# other operands
+	call	3:5
+	jmp	5:3
+	call	dword ptr xtrn
+	jmp	word ptr xtrn
+
+	# Force a good alignment.
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/inval-seg.l b/gas/testsuite/gas/i386/inval-seg.l
new file mode 100644
index 000000000000..efe190e9998f
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-seg.l
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:3: Error: .*
+.*:4: Error: .*
+GAS LISTING .*
+
+
+   1 [ 	]*	.text
+   2 [ 	]*# All the following should be illegal
+   3 [ 	]*	movl	%ds,\(%eax\)
+   4 [ 	]*	movl	\(%eax\),%ds
diff --git a/gas/testsuite/gas/i386/inval-seg.s b/gas/testsuite/gas/i386/inval-seg.s
new file mode 100644
index 000000000000..4cc222145e8a
--- /dev/null
+++ b/gas/testsuite/gas/i386/inval-seg.s
@@ -0,0 +1,4 @@
+	.text
+# All the following should be illegal
+	movl	%ds,(%eax)
+	movl	(%eax),%ds
diff --git a/gas/testsuite/gas/i386/merom.d b/gas/testsuite/gas/i386/merom.d
new file mode 100644
index 000000000000..a09721c85eca
--- /dev/null
+++ b/gas/testsuite/gas/i386/merom.d
@@ -0,0 +1,73 @@
+#objdump: -dw
+#name: i386 merom
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 38 01 01[ 	]+phaddw \(%ecx\),%mm0
+   4:	0f 38 01 c1[ 	]+phaddw %mm1,%mm0
+   8:	66 0f 38 01 01[ 	]+phaddw \(%ecx\),%xmm0
+   d:	66 0f 38 01 c1[ 	]+phaddw %xmm1,%xmm0
+  12:	0f 38 02 01[ 	]+phaddd \(%ecx\),%mm0
+  16:	0f 38 02 c1[ 	]+phaddd %mm1,%mm0
+  1a:	66 0f 38 02 01[ 	]+phaddd \(%ecx\),%xmm0
+  1f:	66 0f 38 02 c1[ 	]+phaddd %xmm1,%xmm0
+  24:	0f 38 03 01[ 	]+phaddsw \(%ecx\),%mm0
+  28:	0f 38 03 c1[ 	]+phaddsw %mm1,%mm0
+  2c:	66 0f 38 03 01[ 	]+phaddsw \(%ecx\),%xmm0
+  31:	66 0f 38 03 c1[ 	]+phaddsw %xmm1,%xmm0
+  36:	0f 38 05 01[ 	]+phsubw \(%ecx\),%mm0
+  3a:	0f 38 05 c1[ 	]+phsubw %mm1,%mm0
+  3e:	66 0f 38 05 01[ 	]+phsubw \(%ecx\),%xmm0
+  43:	66 0f 38 05 c1[ 	]+phsubw %xmm1,%xmm0
+  48:	0f 38 06 01[ 	]+phsubd \(%ecx\),%mm0
+  4c:	0f 38 06 c1[ 	]+phsubd %mm1,%mm0
+  50:	66 0f 38 06 01[ 	]+phsubd \(%ecx\),%xmm0
+  55:	66 0f 38 06 c1[ 	]+phsubd %xmm1,%xmm0
+  5a:	0f 38 07 01[ 	]+phsubsw \(%ecx\),%mm0
+  5e:	0f 38 07 c1[ 	]+phsubsw %mm1,%mm0
+  62:	66 0f 38 07 01[ 	]+phsubsw \(%ecx\),%xmm0
+  67:	66 0f 38 07 c1[ 	]+phsubsw %xmm1,%xmm0
+  6c:	0f 38 04 01[ 	]+pmaddubsw \(%ecx\),%mm0
+  70:	0f 38 04 c1[ 	]+pmaddubsw %mm1,%mm0
+  74:	66 0f 38 04 01[ 	]+pmaddubsw \(%ecx\),%xmm0
+  79:	66 0f 38 04 c1[ 	]+pmaddubsw %xmm1,%xmm0
+  7e:	0f 38 0b 01[ 	]+pmulhrsw \(%ecx\),%mm0
+  82:	0f 38 0b c1[ 	]+pmulhrsw %mm1,%mm0
+  86:	66 0f 38 0b 01[ 	]+pmulhrsw \(%ecx\),%xmm0
+  8b:	66 0f 38 0b c1[ 	]+pmulhrsw %xmm1,%xmm0
+  90:	0f 38 00 01[ 	]+pshufb \(%ecx\),%mm0
+  94:	0f 38 00 c1[ 	]+pshufb %mm1,%mm0
+  98:	66 0f 38 00 01[ 	]+pshufb \(%ecx\),%xmm0
+  9d:	66 0f 38 00 c1[ 	]+pshufb %xmm1,%xmm0
+  a2:	0f 38 08 01[ 	]+psignb \(%ecx\),%mm0
+  a6:	0f 38 08 c1[ 	]+psignb %mm1,%mm0
+  aa:	66 0f 38 08 01[ 	]+psignb \(%ecx\),%xmm0
+  af:	66 0f 38 08 c1[ 	]+psignb %xmm1,%xmm0
+  b4:	0f 38 09 01[ 	]+psignw \(%ecx\),%mm0
+  b8:	0f 38 09 c1[ 	]+psignw %mm1,%mm0
+  bc:	66 0f 38 09 01[ 	]+psignw \(%ecx\),%xmm0
+  c1:	66 0f 38 09 c1[ 	]+psignw %xmm1,%xmm0
+  c6:	0f 38 0a 01[ 	]+psignd \(%ecx\),%mm0
+  ca:	0f 38 0a c1[ 	]+psignd %mm1,%mm0
+  ce:	66 0f 38 0a 01[ 	]+psignd \(%ecx\),%xmm0
+  d3:	66 0f 38 0a c1[ 	]+psignd %xmm1,%xmm0
+  d8:	0f 3a 0f 01 02[ 	]+palignr \$0x2,\(%ecx\),%mm0
+  dd:	0f 3a 0f c1 02[ 	]+palignr \$0x2,%mm1,%mm0
+  e2:	66 0f 3a 0f 01 02[ 	]+palignr \$0x2,\(%ecx\),%xmm0
+  e8:	66 0f 3a 0f c1 02[ 	]+palignr \$0x2,%xmm1,%xmm0
+  ee:	0f 38 1c 01[ 	]+pabsb  \(%ecx\),%mm0
+  f2:	0f 38 1c c1[ 	]+pabsb  %mm1,%mm0
+  f6:	66 0f 38 1c 01[ 	]+pabsb  \(%ecx\),%xmm0
+  fb:	66 0f 38 1c c1[ 	]+pabsb  %xmm1,%xmm0
+ 100:	0f 38 1d 01[ 	]+pabsw  \(%ecx\),%mm0
+ 104:	0f 38 1d c1[ 	]+pabsw  %mm1,%mm0
+ 108:	66 0f 38 1d 01[ 	]+pabsw  \(%ecx\),%xmm0
+ 10d:	66 0f 38 1d c1[ 	]+pabsw  %xmm1,%xmm0
+ 112:	0f 38 1e 01[ 	]+pabsd  \(%ecx\),%mm0
+ 116:	0f 38 1e c1[ 	]+pabsd  %mm1,%mm0
+ 11a:	66 0f 38 1e 01[ 	]+pabsd  \(%ecx\),%xmm0
+ 11f:	66 0f 38 1e c1[ 	]+pabsd  %xmm1,%xmm0
+	...
diff --git a/gas/testsuite/gas/i386/merom.s b/gas/testsuite/gas/i386/merom.s
new file mode 100644
index 000000000000..154d2f8ddb33
--- /dev/null
+++ b/gas/testsuite/gas/i386/merom.s
@@ -0,0 +1,70 @@
+#Merom New Instructions
+
+	.text
+foo:
+	phaddw		(%ecx),%mm0
+	phaddw		%mm1,%mm0
+	phaddw		(%ecx),%xmm0
+	phaddw		%xmm1,%xmm0
+	phaddd		(%ecx),%mm0
+	phaddd		%mm1,%mm0
+	phaddd		(%ecx),%xmm0
+	phaddd		%xmm1,%xmm0
+	phaddsw		(%ecx),%mm0
+	phaddsw		%mm1,%mm0
+	phaddsw		(%ecx),%xmm0
+	phaddsw		%xmm1,%xmm0
+	phsubw		(%ecx),%mm0
+	phsubw		%mm1,%mm0
+	phsubw		(%ecx),%xmm0
+	phsubw		%xmm1,%xmm0
+	phsubd		(%ecx),%mm0
+	phsubd		%mm1,%mm0
+	phsubd		(%ecx),%xmm0
+	phsubd		%xmm1,%xmm0
+	phsubsw		(%ecx),%mm0
+	phsubsw		%mm1,%mm0
+	phsubsw		(%ecx),%xmm0
+	phsubsw		%xmm1,%xmm0
+	pmaddubsw	(%ecx),%mm0
+	pmaddubsw	%mm1,%mm0
+	pmaddubsw	(%ecx),%xmm0
+	pmaddubsw	%xmm1,%xmm0
+	pmulhrsw	(%ecx),%mm0
+	pmulhrsw	%mm1,%mm0
+	pmulhrsw	(%ecx),%xmm0
+	pmulhrsw	%xmm1,%xmm0
+	pshufb		(%ecx),%mm0
+	pshufb		%mm1,%mm0
+	pshufb		(%ecx),%xmm0
+	pshufb		%xmm1,%xmm0
+	psignb		(%ecx),%mm0
+	psignb		%mm1,%mm0
+	psignb		(%ecx),%xmm0
+	psignb		%xmm1,%xmm0
+	psignw		(%ecx),%mm0
+	psignw		%mm1,%mm0
+	psignw		(%ecx),%xmm0
+	psignw		%xmm1,%xmm0
+	psignd		(%ecx),%mm0
+	psignd		%mm1,%mm0
+	psignd		(%ecx),%xmm0
+	psignd		%xmm1,%xmm0
+	palignr		$0x2,(%ecx),%mm0
+	palignr		$0x2,%mm1,%mm0
+	palignr		$0x2,(%ecx),%xmm0
+	palignr		$0x2,%xmm1,%xmm0
+	pabsb		(%ecx),%mm0
+	pabsb		%mm1,%mm0
+	pabsb		(%ecx),%xmm0
+	pabsb		%xmm1,%xmm0
+	pabsw		(%ecx),%mm0
+	pabsw		%mm1,%mm0
+	pabsw		(%ecx),%xmm0
+	pabsw		%xmm1,%xmm0
+	pabsd		(%ecx),%mm0
+	pabsd		%mm1,%mm0
+	pabsd		(%ecx),%xmm0
+	pabsd		%xmm1,%xmm0
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/mixed-mode-reloc.s b/gas/testsuite/gas/i386/mixed-mode-reloc.s
new file mode 100644
index 000000000000..3cc286197f7a
--- /dev/null
+++ b/gas/testsuite/gas/i386/mixed-mode-reloc.s
@@ -0,0 +1,16 @@
+ .text
+
+ .code16
+_start16:
+	movl	xtrn@got(%ebx), %eax
+	calll	xtrn@plt
+
+ .code32
+_start32:
+	movl	xtrn@got(%ebx), %eax
+	calll	xtrn@plt
+
+ .code64
+_start64:
+	movq	xtrn@got(%rbx), %rax
+	callq	xtrn@plt
diff --git a/gas/testsuite/gas/i386/mixed-mode-reloc32.d b/gas/testsuite/gas/i386/mixed-mode-reloc32.d
new file mode 100644
index 000000000000..6bc52f7959ae
--- /dev/null
+++ b/gas/testsuite/gas/i386/mixed-mode-reloc32.d
@@ -0,0 +1,14 @@
+#objdump: -r
+#source: mixed-mode-reloc.s
+#name: x86 mixed mode relocs (32-bit object)
+
+.*: +file format .*i386.*
+
+RELOCATION RECORDS FOR \[.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE[ 	]*
+[0-9a-f]+[ 	]+R_386_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_386_PLT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_386_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_386_PLT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_386_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_386_PLT32[ 	]+xtrn[ 	]*
diff --git a/gas/testsuite/gas/i386/mixed-mode-reloc64.d b/gas/testsuite/gas/i386/mixed-mode-reloc64.d
new file mode 100644
index 000000000000..dc50e43576b3
--- /dev/null
+++ b/gas/testsuite/gas/i386/mixed-mode-reloc64.d
@@ -0,0 +1,14 @@
+#objdump: -r
+#source: mixed-mode-reloc.s
+#name: x86 mixed mode relocs (64-bit object)
+
+.*: +file format .*x86-64.*
+
+RELOCATION RECORDS FOR \[.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_PLT32[ 	]+xtrn\+0xf+c[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_PLT32[ 	]+xtrn\+0xf+c[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_GOT32[ 	]+xtrn[ 	]*
+[0-9a-f]+[ 	]+R_X86_64_PLT32[ 	]+xtrn\+0xf+c[ 	]*
diff --git a/gas/testsuite/gas/i386/naked.d b/gas/testsuite/gas/i386/naked.d
index 206e3002b15f..66214d58addf 100644
--- a/gas/testsuite/gas/i386/naked.d
+++ b/gas/testsuite/gas/i386/naked.d
@@ -11,11 +11,11 @@ Disassembly of section .text:
    a:	b2 20 [ 	]*mov    \$0x20,%dl
    c:	bb 00 00 00 00 [ 	]*mov    \$0x0,%ebx	d: (R_386_)?(dir)?32	.text
   11:	d9 c9 [ 	]*fxch   %st\(1\)
-  13:	36 8c a4 81 d2 04 00 00 [ 	]*movl   %fs,%ss:0x4d2\(%ecx,%eax,4\)
-  1b:	8c 2c ed 00 00 00 00 [ 	]*movl   %gs,0x0\(,%ebp,8\)
+  13:	36 8c a4 81 d2 04 00 00 [ 	]*movw   %fs,%ss:0x4d2\(%ecx,%eax,4\)
+  1b:	8c 2c ed 00 00 00 00 [ 	]*movw   %gs,0x0\(,%ebp,8\)
   22:	26 88 25 00 00 00 00 [ 	]*mov    %ah,%es:0x0
   29:	2e 8b 74 14 80 [ 	]*mov    %cs:0xffffff80\(%esp,%edx,1\),%esi
-  2e:	f3 65 a5 [ 	]*repz movsl %gs:\(%esi\),%es:\(%edi\)
+  2e:	f3 65 a5 [ 	]*rep movsl %gs:\(%esi\),%es:\(%edi\)
   31:	ec [ 	]*in     \(%dx\),%al
   32:	66 ef [ 	]*out    %ax,\(%dx\)
   34:	67 d2 14 [ 	]*addr16 rclb %cl,\(%si\)
diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index dac75a81fa86..808ddc5371a4 100644
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -1,6 +1,6 @@
 #as: -J
 #objdump: -dw
-#name: i386 opcode
+#name: i386 intel
 
 .*: +file format .*
 
@@ -137,9 +137,9 @@ Disassembly of section .text:
  1a3:	89 90 90 90 90 90 [ 	]*mov    %edx,0x90909090\(%eax\)
  1a9:	8a 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dl
  1af:	8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%edx
- 1b5:	8c 90 90 90 90 90 [ 	]*movl   %ss,0x90909090\(%eax\)
+ 1b5:	8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
  1bb:	8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%edx
- 1c1:	8e 90 90 90 90 90 [ 	]*movl   0x90909090\(%eax\),%ss
+ 1c1:	8e 90 90 90 90 90 [ 	]*movw   0x90909090\(%eax\),%ss
  1c7:	8f 80 90 90 90 90 [ 	]*popl   0x90909090\(%eax\)
  1cd:	90 [ 	]*nop    
  1ce:	91 [ 	]*xchg   %eax,%ecx
@@ -480,95 +480,96 @@ Disassembly of section .text:
  7be:	66 87 90 90 90 90 90 [ 	]*xchg   %dx,0x90909090\(%eax\)
  7c5:	66 89 90 90 90 90 90 [ 	]*mov    %dx,0x90909090\(%eax\)
  7cc:	66 8b 90 90 90 90 90 [ 	]*mov    0x90909090\(%eax\),%dx
- 7d3:	66 8c 90 90 90 90 90 [ 	]*movw   %ss,0x90909090\(%eax\)
- 7da:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
- 7e1:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
- 7e8:	66 91 [ 	]*xchg   %ax,%cx
- 7ea:	66 92 [ 	]*xchg   %ax,%dx
- 7ec:	66 93 [ 	]*xchg   %ax,%bx
- 7ee:	66 94 [ 	]*xchg   %ax,%sp
- 7f0:	66 95 [ 	]*xchg   %ax,%bp
- 7f2:	66 96 [ 	]*xchg   %ax,%si
- 7f4:	66 97 [ 	]*xchg   %ax,%di
- 7f6:	66 98 [ 	]*cbtw   
- 7f8:	66 99 [ 	]*cwtd   
- 7fa:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
- 800:	66 9c [ 	]*pushfw 
- 802:	66 9d [ 	]*popfw  
- 804:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
- 80a:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
- 810:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
- 812:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
- 814:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
- 818:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
- 81a:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
- 81c:	66 af [ 	]*scas   %es:\(%edi\),%ax
- 81e:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
- 822:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
- 826:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
- 82a:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
- 82e:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
- 832:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
- 836:	66 be 90 90 [ 	]*mov    \$0x9090,%si
- 83a:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
- 83e:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
- 846:	66 c2 90 90 [ 	]*retw   \$0x9090
- 84a:	66 c3 [ 	]*retw   
- 84c:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
- 853:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
- 85a:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
- 863:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
- 868:	66 c9 [ 	]*leavew 
- 86a:	66 ca 90 90 [ 	]*lretw  \$0x9090
- 86e:	66 cb [ 	]*lretw  
- 870:	66 cf [ 	]*iretw  
- 872:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
- 879:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
- 880:	66 e5 90 [ 	]*in     \$0x90,%ax
- 883:	66 e7 90 [ 	]*out    %ax,\$0x90
- 886:	66 e8 8f 90 [ 	]*callw  (0x)?9919.*
- 88a:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
- 890:	66 ed [ 	]*in     \(%dx\),%ax
- 892:	66 ef [ 	]*out    %ax,\(%dx\)
- 894:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
- 89b:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
- 8a2:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
- 8aa:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
- 8b2:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
- 8ba:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
- 8c2:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
- 8ca:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
- 8d2:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
- 8da:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
- 8e2:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
- 8ea:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
- 8f2:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
- 8fa:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
- 902:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
- 90a:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
- 912:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
- 91a:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
- 922:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
- 92a:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
- 932:	66 0f a0 [ 	]*pushw  %fs
- 935:	66 0f a1 [ 	]*popw   %fs
- 938:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
- 940:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
- 949:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
- 951:	66 0f a8 [ 	]*pushw  %gs
- 954:	66 0f a9 [ 	]*popw   %gs
- 957:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
- 95f:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
- 968:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
- 970:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
- 978:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
- 980:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
- 988:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
- 990:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
- 998:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
- 9a0:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
- 9a8:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
- 9b0:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
- 9b8:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
- 9c0:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
- 9c8:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+ 7d3:	8c 90 90 90 90 90 [ 	]*mov[w ]   %ss,0x90909090\(%eax\)
+ 7d9:	66 8d 90 90 90 90 90 [ 	]*lea    0x90909090\(%eax\),%dx
+ 7e0:	66 8f 80 90 90 90 90 [ 	]*popw   0x90909090\(%eax\)
+ 7e7:	66 91 [ 	]*xchg   %ax,%cx
+ 7e9:	66 92 [ 	]*xchg   %ax,%dx
+ 7eb:	66 93 [ 	]*xchg   %ax,%bx
+ 7ed:	66 94 [ 	]*xchg   %ax,%sp
+ 7ef:	66 95 [ 	]*xchg   %ax,%bp
+ 7f1:	66 96 [ 	]*xchg   %ax,%si
+ 7f3:	66 97 [ 	]*xchg   %ax,%di
+ 7f5:	66 98 [ 	]*cbtw   
+ 7f7:	66 99 [ 	]*cwtd   
+ 7f9:	66 9a 90 90 90 90 [ 	]*lcallw \$0x9090,\$0x9090
+ 7ff:	66 9c [ 	]*pushfw 
+ 801:	66 9d [ 	]*popfw  
+ 803:	66 a1 90 90 90 90 [ 	]*mov    0x90909090,%ax
+ 809:	66 a3 90 90 90 90 [ 	]*mov    %ax,0x90909090
+ 80f:	66 a5 [ 	]*movsw  %ds:\(%esi\),%es:\(%edi\)
+ 811:	66 a7 [ 	]*cmpsw  %es:\(%edi\),%ds:\(%esi\)
+ 813:	66 a9 90 90 [ 	]*test   \$0x9090,%ax
+ 817:	66 ab [ 	]*stos   %ax,%es:\(%edi\)
+ 819:	66 ad [ 	]*lods   %ds:\(%esi\),%ax
+ 81b:	66 af [ 	]*scas   %es:\(%edi\),%ax
+ 81d:	66 b8 90 90 [ 	]*mov    \$0x9090,%ax
+ 821:	66 b9 90 90 [ 	]*mov    \$0x9090,%cx
+ 825:	66 ba 90 90 [ 	]*mov    \$0x9090,%dx
+ 829:	66 bb 90 90 [ 	]*mov    \$0x9090,%bx
+ 82d:	66 bc 90 90 [ 	]*mov    \$0x9090,%sp
+ 831:	66 bd 90 90 [ 	]*mov    \$0x9090,%bp
+ 835:	66 be 90 90 [ 	]*mov    \$0x9090,%si
+ 839:	66 bf 90 90 [ 	]*mov    \$0x9090,%di
+ 83d:	66 c1 90 90 90 90 90 90 [ 	]*rclw   \$0x90,0x90909090\(%eax\)
+ 845:	66 c2 90 90 [ 	]*retw   \$0x9090
+ 849:	66 c3 [ 	]*retw   
+ 84b:	66 c4 90 90 90 90 90 [ 	]*les    0x90909090\(%eax\),%dx
+ 852:	66 c5 90 90 90 90 90 [ 	]*lds    0x90909090\(%eax\),%dx
+ 859:	66 c7 80 90 90 90 90 90 90 [ 	]*movw   \$0x9090,0x90909090\(%eax\)
+ 862:	66 c8 90 90 90 [ 	]*enterw \$0x9090,\$0x90
+ 867:	66 c9 [ 	]*leavew 
+ 869:	66 ca 90 90 [ 	]*lretw  \$0x9090
+ 86d:	66 cb [ 	]*lretw  
+ 86f:	66 cf [ 	]*iretw  
+ 871:	66 d1 90 90 90 90 90 [ 	]*rclw   0x90909090\(%eax\)
+ 878:	66 d3 90 90 90 90 90 [ 	]*rclw   %cl,0x90909090\(%eax\)
+ 87f:	66 e5 90 [ 	]*in     \$0x90,%ax
+ 882:	66 e7 90 [ 	]*out    %ax,\$0x90
+ 885:	66 e8 8f 90 [ 	]*callw  (0x)?9918.*
+ 889:	66 ea 90 90 90 90 [ 	]*ljmpw  \$0x9090,\$0x9090
+ 88f:	66 ed [ 	]*in     \(%dx\),%ax
+ 891:	66 ef [ 	]*out    %ax,\(%dx\)
+ 893:	66 f7 90 90 90 90 90 [ 	]*notw   0x90909090\(%eax\)
+ 89a:	66 ff 90 90 90 90 90 [ 	]*callw  \*0x90909090\(%eax\)
+ 8a1:	66 0f 02 90 90 90 90 90 [ 	]*lar    0x90909090\(%eax\),%dx
+ 8a9:	66 0f 03 90 90 90 90 90 [ 	]*lsl    0x90909090\(%eax\),%dx
+ 8b1:	66 0f 40 90 90 90 90 90 [ 	]*cmovo  0x90909090\(%eax\),%dx
+ 8b9:	66 0f 41 90 90 90 90 90 [ 	]*cmovno 0x90909090\(%eax\),%dx
+ 8c1:	66 0f 42 90 90 90 90 90 [ 	]*cmovb  0x90909090\(%eax\),%dx
+ 8c9:	66 0f 43 90 90 90 90 90 [ 	]*cmovae 0x90909090\(%eax\),%dx
+ 8d1:	66 0f 44 90 90 90 90 90 [ 	]*cmove  0x90909090\(%eax\),%dx
+ 8d9:	66 0f 45 90 90 90 90 90 [ 	]*cmovne 0x90909090\(%eax\),%dx
+ 8e1:	66 0f 46 90 90 90 90 90 [ 	]*cmovbe 0x90909090\(%eax\),%dx
+ 8e9:	66 0f 47 90 90 90 90 90 [ 	]*cmova  0x90909090\(%eax\),%dx
+ 8f1:	66 0f 48 90 90 90 90 90 [ 	]*cmovs  0x90909090\(%eax\),%dx
+ 8f9:	66 0f 49 90 90 90 90 90 [ 	]*cmovns 0x90909090\(%eax\),%dx
+ 901:	66 0f 4a 90 90 90 90 90 [ 	]*cmovp  0x90909090\(%eax\),%dx
+ 909:	66 0f 4b 90 90 90 90 90 [ 	]*cmovnp 0x90909090\(%eax\),%dx
+ 911:	66 0f 4c 90 90 90 90 90 [ 	]*cmovl  0x90909090\(%eax\),%dx
+ 919:	66 0f 4d 90 90 90 90 90 [ 	]*cmovge 0x90909090\(%eax\),%dx
+ 921:	66 0f 4e 90 90 90 90 90 [ 	]*cmovle 0x90909090\(%eax\),%dx
+ 929:	66 0f 4f 90 90 90 90 90 [ 	]*cmovg  0x90909090\(%eax\),%dx
+ 931:	66 0f a0 [ 	]*pushw  %fs
+ 934:	66 0f a1 [ 	]*popw   %fs
+ 937:	66 0f a3 90 90 90 90 90 [ 	]*bt     %dx,0x90909090\(%eax\)
+ 93f:	66 0f a4 90 90 90 90 90 90 [ 	]*shld   \$0x90,%dx,0x90909090\(%eax\)
+ 948:	66 0f a5 90 90 90 90 90 [ 	]*shld   %cl,%dx,0x90909090\(%eax\)
+ 950:	66 0f a8 [ 	]*pushw  %gs
+ 953:	66 0f a9 [ 	]*popw   %gs
+ 956:	66 0f ab 90 90 90 90 90 [ 	]*bts    %dx,0x90909090\(%eax\)
+ 95e:	66 0f ac 90 90 90 90 90 90 [ 	]*shrd   \$0x90,%dx,0x90909090\(%eax\)
+ 967:	66 0f ad 90 90 90 90 90 [ 	]*shrd   %cl,%dx,0x90909090\(%eax\)
+ 96f:	66 0f af 90 90 90 90 90 [ 	]*imul   0x90909090\(%eax\),%dx
+ 977:	66 0f b1 90 90 90 90 90 [ 	]*cmpxchg %dx,0x90909090\(%eax\)
+ 97f:	66 0f b2 90 90 90 90 90 [ 	]*lss    0x90909090\(%eax\),%dx
+ 987:	66 0f b3 90 90 90 90 90 [ 	]*btr    %dx,0x90909090\(%eax\)
+ 98f:	66 0f b4 90 90 90 90 90 [ 	]*lfs    0x90909090\(%eax\),%dx
+ 997:	66 0f b5 90 90 90 90 90 [ 	]*lgs    0x90909090\(%eax\),%dx
+ 99f:	66 0f b6 90 90 90 90 90 [ 	]*movzbw 0x90909090\(%eax\),%dx
+ 9a7:	66 0f bb 90 90 90 90 90 [ 	]*btc    %dx,0x90909090\(%eax\)
+ 9af:	66 0f bc 90 90 90 90 90 [ 	]*bsf    0x90909090\(%eax\),%dx
+ 9b7:	66 0f bd 90 90 90 90 90 [ 	]*bsr    0x90909090\(%eax\),%dx
+ 9bf:	66 0f be 90 90 90 90 90 [ 	]*movsbw 0x90909090\(%eax\),%dx
+ 9c7:	66 0f c1 90 90 90 90 90 [ 	]*xadd   %dx,0x90909090\(%eax\)
+	\.\.\.
diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 39c5967b266c..8d7cd050f165 100644
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -130,9 +130,9 @@ foo:
  mov    %edx,0x90909090(%eax)
  mov    0x90909090(%eax),%dl
  mov    0x90909090(%eax),%edx
- movl   %ss,0x90909090(%eax)
+ movw   %ss,0x90909090(%eax)
  lea    0x90909090(%eax),%edx
- movl   0x90909090(%eax),%ss
+ movw   0x90909090(%eax),%ss
  popl   0x90909090(%eax)
  xchg   %eax,%eax
  xchg   %eax,%ecx
@@ -565,3 +565,6 @@ foo:
  bsr    0x90909090(%eax),%dx
  movsbw 0x90909090(%eax),%dx
  xadd   %dx,0x90909090(%eax)
+
+# Force a good alignment.
+ .p2align 4,0
diff --git a/gas/testsuite/gas/i386/padlock.d b/gas/testsuite/gas/i386/padlock.d
index a85f1049d014..886ee124695b 100644
--- a/gas/testsuite/gas/i386/padlock.d
+++ b/gas/testsuite/gas/i386/padlock.d
@@ -5,23 +5,23 @@
 
 Disassembly of section .text:
 
-00000000 <foo>:
-   0:[	 ]*0f a7 c0 [	 ]*xstorerng 
-   3:[	 ]*f3 0f a7 c0 [	 ]*repz xstorerng 
-   7:[	 ]*f3 0f a7 c8 [	 ]*repz xcryptecb 
-   b:[	 ]*f3 0f a7 c8 [	 ]*repz xcryptecb 
-   f:[	 ]*f3 0f a7 d0 [	 ]*repz xcryptcbc 
-  13:[	 ]*f3 0f a7 d0 [	 ]*repz xcryptcbc 
-  17:[	 ]*f3 0f a7 e0 [	 ]*repz xcryptcfb 
-  1b:[	 ]*f3 0f a7 e0 [	 ]*repz xcryptcfb 
-  1f:[	 ]*f3 0f a7 e8 [	 ]*repz xcryptofb 
-  23:[	 ]*f3 0f a7 e8 [	 ]*repz xcryptofb 
-  27:[	 ]*0f a7 c0 [	 ]*xstorerng 
-  2a:[	 ]*f3 0f a7 c0 [	 ]*repz xstorerng 
+0+000 <foo>:
+   0:[	 ]*0f a7 c0 [	 ]*xstore-rng 
+   3:[	 ]*f3 0f a7 c0 [	 ]*repz xstore-rng 
+   7:[	 ]*f3 0f a7 c8 [	 ]*repz xcrypt-ecb 
+   b:[	 ]*f3 0f a7 c8 [	 ]*repz xcrypt-ecb 
+   f:[	 ]*f3 0f a7 d0 [	 ]*repz xcrypt-cbc 
+  13:[	 ]*f3 0f a7 d0 [	 ]*repz xcrypt-cbc 
+  17:[	 ]*f3 0f a7 e0 [	 ]*repz xcrypt-cfb 
+  1b:[	 ]*f3 0f a7 e0 [	 ]*repz xcrypt-cfb 
+  1f:[	 ]*f3 0f a7 e8 [	 ]*repz xcrypt-ofb 
+  23:[	 ]*f3 0f a7 e8 [	 ]*repz xcrypt-ofb 
+  27:[	 ]*0f a7 c0 [	 ]*xstore-rng 
+  2a:[	 ]*f3 0f a7 c0 [	 ]*repz xstore-rng 
   2e:[	 ]*f3 0f a6 c0 [	 ]*repz montmul 
   32:[	 ]*f3 0f a6 c0 [	 ]*repz montmul 
   36:[	 ]*f3 0f a6 c8 [	 ]*repz xsha1 
   3a:[	 ]*f3 0f a6 c8 [	 ]*repz xsha1 
   3e:[	 ]*f3 0f a6 d0 [	 ]*repz xsha256 
   42:[	 ]*f3 0f a6 d0 [	 ]*repz xsha256 
-[ 	]*\.\.\.
+#pass
diff --git a/gas/testsuite/gas/i386/prefix.d b/gas/testsuite/gas/i386/prefix.d
index 054b658a3cf8..229a2a766a30 100644
--- a/gas/testsuite/gas/i386/prefix.d
+++ b/gas/testsuite/gas/i386/prefix.d
@@ -12,4 +12,4 @@ Disassembly of section .text:
    b:	9b df e0 [ 	]*fstsw  %ax
    e:	9b 67 df e0 [ 	]*addr16 fstsw %ax
   12:	f3 67 66 36 a7 [ 	]*repz addr16 cmpsw %es:\(%di\),%ss:\(%si\)
-	...
+#pass
diff --git a/gas/testsuite/gas/i386/prescott.d b/gas/testsuite/gas/i386/prescott.d
index 78609a7db218..1e66065433ac 100644
--- a/gas/testsuite/gas/i386/prescott.d
+++ b/gas/testsuite/gas/i386/prescott.d
@@ -13,25 +13,25 @@ Disassembly of section .text:
   10:	df 88 90 90 90 90 [ 	]*fisttp 0x90909090\(%eax\)
   16:	db 88 90 90 90 90 [ 	]*fisttpl 0x90909090\(%eax\)
   1c:	dd 88 90 90 90 90 [ 	]*fisttpll 0x90909090\(%eax\)
-  22:	dd 88 90 90 90 90 [ 	]*fisttpll 0x90909090\(%eax\)
-  28:	dd 88 90 90 90 90 [ 	]*fisttpll 0x90909090\(%eax\)
-  2e:	66 0f 7c 65 00 [ 	]*haddpd 0x0\(%ebp\),%xmm4
-  33:	66 0f 7c ee [ 	]*haddpd %xmm6,%xmm5
-  37:	f2 0f 7c 37 [ 	]*haddps \(%edi\),%xmm6
-  3b:	f2 0f 7c f8 [ 	]*haddps %xmm0,%xmm7
-  3f:	66 0f 7d c1 [ 	]*hsubpd %xmm1,%xmm0
-  43:	66 0f 7d 0a [ 	]*hsubpd \(%edx\),%xmm1
-  47:	f2 0f 7d d2 [ 	]*hsubps %xmm2,%xmm2
-  4b:	f2 0f 7d 1c 24 [ 	]*hsubps \(%esp\),%xmm3
-  50:	f2 0f f0 2e [ 	]*lddqu  \(%esi\),%xmm5
-  54:	0f 01 c8 [ 	]*monitor %eax,%ecx,%edx 
-  57:	0f 01 c8 [ 	]*monitor %eax,%ecx,%edx 
-  5a:	f2 0f 12 f7 [ 	]*movddup %xmm7,%xmm6
-  5e:	f2 0f 12 38 [ 	]*movddup \(%eax\),%xmm7
-  62:	f3 0f 16 01 [ 	]*movshdup \(%ecx\),%xmm0
-  66:	f3 0f 16 ca [ 	]*movshdup %xmm2,%xmm1
-  6a:	f3 0f 12 13 [ 	]*movsldup \(%ebx\),%xmm2
-  6e:	f3 0f 12 dc [ 	]*movsldup %xmm4,%xmm3
-  72:	0f 01 c9 [ 	]*mwait   %eax,%ecx 
-  75:	0f 01 c9 [ 	]*mwait   %eax,%ecx 
+  22:	66 0f 7c 65 00 [ 	]*haddpd 0x0\(%ebp\),%xmm4
+  27:	66 0f 7c ee [ 	]*haddpd %xmm6,%xmm5
+  2b:	f2 0f 7c 37 [ 	]*haddps \(%edi\),%xmm6
+  2f:	f2 0f 7c f8 [ 	]*haddps %xmm0,%xmm7
+  33:	66 0f 7d c1 [ 	]*hsubpd %xmm1,%xmm0
+  37:	66 0f 7d 0a [ 	]*hsubpd \(%edx\),%xmm1
+  3b:	f2 0f 7d d2 [ 	]*hsubps %xmm2,%xmm2
+  3f:	f2 0f 7d 1c 24 [ 	]*hsubps \(%esp\),%xmm3
+  44:	f2 0f f0 2e [ 	]*lddqu  \(%esi\),%xmm5
+  48:	0f 01 c8 [ 	]*monitor %eax,%ecx,%edx
+  4b:	0f 01 c8 [ 	]*monitor %eax,%ecx,%edx
+  4e:	f2 0f 12 f7 [ 	]*movddup %xmm7,%xmm6
+  52:	f2 0f 12 38 [ 	]*movddup \(%eax\),%xmm7
+  56:	f3 0f 16 01 [ 	]*movshdup \(%ecx\),%xmm0
+  5a:	f3 0f 16 ca [ 	]*movshdup %xmm2,%xmm1
+  5e:	f3 0f 12 13 [ 	]*movsldup \(%ebx\),%xmm2
+  62:	f3 0f 12 dc [ 	]*movsldup %xmm4,%xmm3
+  66:	0f 01 c9 [ 	]*mwait  %eax,%ecx
+  69:	0f 01 c9 [ 	]*mwait  %eax,%ecx
+  6c:	67 0f 01 c8 [ 	]*monitor %ax,%ecx,%edx
+  70:	67 0f 01 c8 [ 	]*monitor %ax,%ecx,%edx
 	...
diff --git a/gas/testsuite/gas/i386/prescott.s b/gas/testsuite/gas/i386/prescott.s
index 8a3651daddd4..95dacf772935 100644
--- a/gas/testsuite/gas/i386/prescott.s
+++ b/gas/testsuite/gas/i386/prescott.s
@@ -8,8 +8,6 @@ foo:
 	addsubps	%xmm4,%xmm3
 	fisttp		0x90909090(%eax)
 	fisttpl		0x90909090(%eax)
-	fisttpd		0x90909090(%eax)
-	fisttpq		0x90909090(%eax)
 	fisttpll	0x90909090(%eax)
 	haddpd		0x0(%ebp),%xmm4
 	haddpd		%xmm6,%xmm5
@@ -31,4 +29,7 @@ foo:
 	mwait
 	mwait		%eax,%ecx
 
+	monitor		%ax,%ecx,%edx
+	addr16 monitor
+
 	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/reloc32.d b/gas/testsuite/gas/i386/reloc32.d
new file mode 100644
index 000000000000..b2cd29c5142c
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc32.d
@@ -0,0 +1,67 @@
+#objdump: -Drw
+#name: i386 relocs
+
+.*: +file format .*i386.*
+
+Disassembly of section \.text:
+#...
+.*[ 	]+R_386_32[ 	]+xtrn
+.*[ 	]+R_386_16[ 	]+xtrn
+.*[ 	]+R_386_8[ 	]+xtrn
+.*[ 	]+R_386_32[ 	]+xtrn
+.*[ 	]+R_386_16[ 	]+xtrn
+.*[ 	]+R_386_PC32[ 	]+xtrn
+.*[ 	]+R_386_PC16[ 	]+xtrn
+.*[ 	]+R_386_PC8[ 	]+xtrn
+.*[ 	]+R_386_PC32[ 	]+xtrn
+.*[ 	]+R_386_PC16[ 	]+xtrn
+.*[ 	]+R_386_PC32[ 	]+xtrn
+.*[ 	]+R_386_PC8[ 	]+xtrn
+.*[ 	]+R_386_GOT32[ 	]+xtrn
+.*[ 	]+R_386_GOT32[ 	]+xtrn
+.*[ 	]+R_386_GOTOFF[ 	]+xtrn
+.*[ 	]+R_386_GOTOFF[ 	]+xtrn
+.*[ 	]+R_386_GOTPC[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_386_GOTPC[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_386_PLT32[ 	]+xtrn
+.*[ 	]+R_386_PLT32[ 	]+xtrn
+.*[ 	]+R_386_PLT32[ 	]+xtrn
+.*[ 	]+R_386_TLS_GD[ 	]+xtrn
+.*[ 	]+R_386_TLS_GD[ 	]+xtrn
+.*[ 	]+R_386_TLS_GOTIE[ 	]+xtrn
+.*[ 	]+R_386_TLS_GOTIE[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDM[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDM[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDO_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDO_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE_32[ 	]+xtrn
+Disassembly of section \.data:
+#...
+.*[ 	]+R_386_32[ 	]+xtrn
+.*[ 	]+R_386_PC32[ 	]+xtrn
+.*[ 	]+R_386_GOT32[ 	]+xtrn
+.*[ 	]+R_386_GOTOFF[ 	]+xtrn
+.*[ 	]+R_386_GOTPC[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_386_GOTPC[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_386_PLT32[ 	]+xtrn
+#...
+.*[ 	]+R_386_TLS_GD[ 	]+xtrn
+#...
+.*[ 	]+R_386_TLS_GOTIE[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE[ 	]+xtrn
+.*[ 	]+R_386_TLS_IE_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDM[ 	]+xtrn
+.*[ 	]+R_386_TLS_LDO_32[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE[ 	]+xtrn
+.*[ 	]+R_386_TLS_LE_32[ 	]+xtrn
+.*[ 	]+R_386_16[ 	]+xtrn
+.*[ 	]+R_386_PC16[ 	]+xtrn
+.*[ 	]+R_386_8[ 	]+xtrn
+.*[ 	]+R_386_PC8[ 	]+xtrn
diff --git a/gas/testsuite/gas/i386/reloc32.l b/gas/testsuite/gas/i386/reloc32.l
new file mode 100644
index 000000000000..74e80df6109a
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc32.l
@@ -0,0 +1,67 @@
+.*: Assembler messages:
+.*:30: Error: .*
+.*:31: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:40: Error: .*
+.*:41: Error: .*
+.*:51: Error: .*
+.*:52: Error: .*
+.*:54: Error: .*
+.*:56: Error: .*
+.*:59: Error: .*
+.*:60: Error: .*
+.*:62: Error: .*
+.*:63: Error: .*
+.*:66: Error: .*
+.*:67: Error: .*
+.*:69: Error: .*
+.*:70: Error: .*
+.*:73: Error: .*
+.*:74: Error: .*
+.*:76: Error: .*
+.*:77: Error: .*
+.*:80: Error: .*
+.*:81: Error: .*
+.*:83: Error: .*
+.*:84: Error: .*
+.*:87: Error: .*
+.*:88: Error: .*
+.*:90: Error: .*
+.*:91: Error: .*
+.*:94: Error: .*
+.*:95: Error: .*
+.*:97: Error: .*
+.*:98: Error: .*
+.*:101: Error: .*
+.*:102: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:108: Error: .*
+.*:109: Error: .*
+.*:111: Error: .*
+.*:112: Error: .*
+.*:133: Error: .*
+.*:134: Error: .*
+.*:137: Error: .*
+.*:138: Error: .*
+.*:139: Error: .*
+.*:140: Error: .*
+.*:141: Error: .*
+.*:142: Error: .*
+.*:143: Error: .*
+.*:144: Error: .*
+.*:145: Error: .*
+.*:149: Error: .*
+.*:150: Error: .*
+.*:153: Error: .*
+.*:154: Error: .*
+.*:155: Error: .*
+.*:156: Error: .*
+.*:157: Error: .*
+.*:158: Error: .*
+.*:159: Error: .*
+.*:160: Error: .*
+.*:161: Error: .*
diff --git a/gas/testsuite/gas/i386/reloc32.s b/gas/testsuite/gas/i386/reloc32.s
new file mode 100644
index 000000000000..1a893ffdb093
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc32.s
@@ -0,0 +1,161 @@
+ .macro bad args:vararg
+  .ifdef _bad_
+	\args
+  .endif
+ .endm
+
+ .macro ill args:vararg
+  # This is used to mark entries that aren't handled consistently,
+  # and thus shouldn't currently be checked for.
+  #	\args
+ .endm
+
+ .text
+_start:
+	mov	$xtrn, %eax
+	mov	$xtrn, %ax
+	mov	$xtrn, %al
+	mov	xtrn(%ebx), %eax
+	mov	xtrn(%bx), %eax
+
+	mov	$(xtrn - .), %eax
+	mov	$(xtrn - .), %ax
+	mov	$(xtrn - .), %al
+	mov	xtrn - .(%ebx), %eax
+	mov	xtrn - .(%bx), %eax
+	call	xtrn
+	jecxz	xtrn
+
+	mov	$xtrn@got, %eax
+bad	mov	$xtrn@got, %ax
+bad	mov	$xtrn@got, %al
+	mov	xtrn@got(%ebx), %eax
+bad	mov	xtrn@got(%bx), %eax
+bad	call	xtrn@got
+
+	mov	$xtrn@gotoff, %eax
+bad	mov	$xtrn@gotoff, %ax
+bad	mov	$xtrn@gotoff, %al
+	mov	xtrn@gotoff(%ebx), %eax
+bad	mov	xtrn@gotoff(%bx), %eax
+bad	call	xtrn@gotoff
+
+	add	$_GLOBAL_OFFSET_TABLE_, %eax
+ill	add	$_GLOBAL_OFFSET_TABLE_, %ax
+ill	add	$_GLOBAL_OFFSET_TABLE_, %al
+	add	$(_GLOBAL_OFFSET_TABLE_ - .), %eax
+ill	add	$(_GLOBAL_OFFSET_TABLE_ - .), %ax
+ill	add	$(_GLOBAL_OFFSET_TABLE_ - .), %al
+
+	mov	$xtrn@plt, %eax
+bad	mov	$xtrn@plt, %ax
+bad	mov	$xtrn@plt, %al
+	mov	xtrn@plt(%ebx), %eax
+bad	mov	xtrn@plt(%bx), %eax
+	call	xtrn@plt
+bad	jecxz	xtrn@plt
+
+	mov	$xtrn@tlsgd, %eax
+bad	mov	$xtrn@tlsgd, %ax
+bad	mov	$xtrn@tlsgd, %al
+	mov	xtrn@tlsgd(%ebx), %eax
+bad	mov	xtrn@tlsgd(%bx), %eax
+bad	call	xtrn@tlsgd
+
+	mov	$xtrn@gotntpoff, %eax
+bad	mov	$xtrn@gotntpoff, %ax
+bad	mov	$xtrn@gotntpoff, %al
+	mov	xtrn@gotntpoff(%ebx), %eax
+bad	mov	xtrn@gotntpoff(%bx), %eax
+bad	call	xtrn@gotntpoff
+
+	mov	$xtrn@indntpoff, %eax
+bad	mov	$xtrn@indntpoff, %ax
+bad	mov	$xtrn@indntpoff, %al
+	mov	xtrn@indntpoff(%ebx), %eax
+bad	mov	xtrn@indntpoff(%bx), %eax
+bad	call	xtrn@indntpoff
+
+	mov	$xtrn@gottpoff, %eax
+bad	mov	$xtrn@gottpoff, %ax
+bad	mov	$xtrn@gottpoff, %al
+	mov	xtrn@gottpoff(%ebx), %eax
+bad	mov	xtrn@gottpoff(%bx), %eax
+bad	call	xtrn@gottpoff
+
+	mov	$xtrn@tlsldm, %eax
+bad	mov	$xtrn@tlsldm, %ax
+bad	mov	$xtrn@tlsldm, %al
+	mov	xtrn@tlsldm(%ebx), %eax
+bad	mov	xtrn@tlsldm(%bx), %eax
+bad	call	xtrn@tlsldm
+
+	mov	$xtrn@dtpoff, %eax
+bad	mov	$xtrn@dtpoff, %ax
+bad	mov	$xtrn@dtpoff, %al
+	mov	xtrn@dtpoff(%ebx), %eax
+bad	mov	xtrn@dtpoff(%bx), %eax
+bad	call	xtrn@dtpoff
+
+	mov	$xtrn@ntpoff, %eax
+bad	mov	$xtrn@ntpoff, %ax
+bad	mov	$xtrn@ntpoff, %al
+	mov	xtrn@ntpoff(%ebx), %eax
+bad	mov	xtrn@ntpoff(%bx), %eax
+bad	call	xtrn@ntpoff
+
+	mov	$xtrn@tpoff, %eax
+bad	mov	$xtrn@tpoff, %ax
+bad	mov	$xtrn@tpoff, %al
+	mov	xtrn@tpoff(%ebx), %eax
+bad	mov	xtrn@tpoff(%bx), %eax
+bad	call	xtrn@tpoff
+
+ .data
+	.long	xtrn
+	.long	xtrn - .
+	.long	xtrn@got
+	.long	xtrn@gotoff
+	.long	_GLOBAL_OFFSET_TABLE_
+	.long	_GLOBAL_OFFSET_TABLE_ - .
+	.long	xtrn@plt
+	.long	xtrn@tlsgd
+	.long	xtrn@gotntpoff
+	.long	xtrn@indntpoff
+	.long	xtrn@gottpoff
+	.long	xtrn@tlsldm
+	.long	xtrn@dtpoff
+	.long	xtrn@ntpoff
+	.long	xtrn@tpoff
+	
+	.word	xtrn
+	.word	xtrn - .
+bad	.word	xtrn@got
+bad	.word	xtrn@gotoff
+ill	.word	_GLOBAL_OFFSET_TABLE_
+ill	.word	_GLOBAL_OFFSET_TABLE_ - .
+bad	.word	xtrn@plt
+bad	.word	xtrn@tlsgd
+bad	.word	xtrn@gotntpoff
+bad	.word	xtrn@indntpoff
+bad	.word	xtrn@gottpoff
+bad	.word	xtrn@tlsldm
+bad	.word	xtrn@dtpoff
+bad	.word	xtrn@ntpoff
+bad	.word	xtrn@tpoff
+
+	.byte	xtrn
+	.byte	xtrn - .
+bad	.byte	xtrn@got
+bad	.byte	xtrn@gotoff
+ill	.byte	_GLOBAL_OFFSET_TABLE_
+ill	.byte	_GLOBAL_OFFSET_TABLE_ - .
+bad	.byte	xtrn@plt
+bad	.byte	xtrn@tlsgd
+bad	.byte	xtrn@gotntpoff
+bad	.byte	xtrn@indntpoff
+bad	.byte	xtrn@gottpoff
+bad	.byte	xtrn@tlsldm
+bad	.byte	xtrn@dtpoff
+bad	.byte	xtrn@ntpoff
+bad	.byte	xtrn@tpoff
diff --git a/gas/testsuite/gas/i386/reloc64.d b/gas/testsuite/gas/i386/reloc64.d
new file mode 100644
index 000000000000..11dfdb4fedd2
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc64.d
@@ -0,0 +1,86 @@
+#objdump: -Drw
+#name: x86-64 relocs
+
+.*: +file format .*x86-64.*
+
+Disassembly of section \.text:
+#...
+.*[ 	]+R_X86_64_64[ 	]+xtrn
+.*[ 	]+R_X86_64_32S[ 	]+xtrn
+.*[ 	]+R_X86_64_32[ 	]+xtrn
+.*[ 	]+R_X86_64_16[ 	]+xtrn
+.*[ 	]+R_X86_64_8[ 	]+xtrn
+.*[ 	]+R_X86_64_32S[ 	]+xtrn
+.*[ 	]+R_X86_64_32[ 	]+xtrn
+.*[ 	]+R_X86_64_PC64[ 	]+xtrn\+0x0*2
+.*[ 	]+R_X86_64_PC32[ 	]+xtrn\+0x0*2
+.*[ 	]+R_X86_64_PC16[ 	]+xtrn\+0x0*2
+.*[ 	]+R_X86_64_PC8[ 	]+xtrn\+0x0*1
+.*[ 	]+R_X86_64_PC32[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_PC32[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_PC8[ 	]+xtrn\+0xf+f
+.*[ 	]+R_X86_64_GOT64[ 	]+xtrn
+.*[ 	]+R_X86_64_GOT32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOT32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_\+0x0*2
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_\+0xf+c
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_\+0x0*2
+.*[ 	]+R_X86_64_PLT32[ 	]+xtrn
+.*[ 	]+R_X86_64_PLT32[ 	]+xtrn
+.*[ 	]+R_X86_64_PLT32[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_TLSGD[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSGD[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSGD[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_GOTTPOFF[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTTPOFF[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTTPOFF[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_TLSLD[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSLD[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSLD[ 	]+xtrn\+0xf+c
+.*[ 	]+R_X86_64_DTPOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_DTPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_DTPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
+Disassembly of section \.data:
+#...
+.*[ 	]+R_X86_64_64[ 	]+xtrn
+.*[ 	]+R_X86_64_PC64[ 	]+xtrn
+.*[ 	]+R_X86_64_GOT64[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL64[ 	]+xtrn
+.*[ 	]+R_X86_64_DTPOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF64[ 	]+xtrn
+.*[ 	]+R_X86_64_32[ 	]+xtrn
+.*[ 	]+R_X86_64_PC32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOT32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_X86_64_PLT32[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSGD[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTTPOFF[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSLD[ 	]+xtrn
+.*[ 	]+R_X86_64_DTPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_32S[ 	]+xtrn
+.*[ 	]+R_X86_64_PC32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOT32[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPCREL[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_X86_64_GOTPC32[ 	]+_GLOBAL_OFFSET_TABLE_
+.*[ 	]+R_X86_64_PLT32[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSGD[ 	]+xtrn
+.*[ 	]+R_X86_64_GOTTPOFF[ 	]+xtrn
+.*[ 	]+R_X86_64_TLSLD[ 	]+xtrn
+.*[ 	]+R_X86_64_DTPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_TPOFF32[ 	]+xtrn
+.*[ 	]+R_X86_64_16[ 	]+xtrn
+.*[ 	]+R_X86_64_PC16[ 	]+xtrn
+.*[ 	]+R_X86_64_8[ 	]+xtrn
+.*[ 	]+R_X86_64_PC8[ 	]+xtrn
diff --git a/gas/testsuite/gas/i386/reloc64.l b/gas/testsuite/gas/i386/reloc64.l
new file mode 100644
index 000000000000..87a5c772c328
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc64.l
@@ -0,0 +1,75 @@
+.*: Assembler messages:
+.*:29: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:39: Error: .*
+.*:40: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:51: Error: .*
+.*:53: Error: .*
+.*:54: Error: .*
+.*:55: Error: .*
+.*:57: Error: .*
+.*:66: Error: .*
+.*:73: Error: .*
+.*:75: Error: .*
+.*:76: Error: .*
+.*:77: Error: .*
+.*:79: Error: .*
+.*:81: Error: .*
+.*:83: Error: .*
+.*:85: Error: .*
+.*:86: Error: .*
+.*:87: Error: .*
+.*:89: Error: .*
+.*:92: Error: .*
+.*:94: Error: .*
+.*:95: Error: .*
+.*:96: Error: .*
+.*:98: Error: .*
+.*:101: Error: .*
+.*:103: Error: .*
+.*:104: Error: .*
+.*:105: Error: .*
+.*:107: Error: .*
+.*:112: Error: .*
+.*:113: Error: .*
+.*:114: Error: .*
+.*:116: Error: .*
+.*:117: Error: .*
+.*:121: Error: .*
+.*:122: Error: .*
+.*:123: Error: .*
+.*:125: Error: .*
+.*:126: Error: .*
+.*:136: Error: .*
+.*:137: Error: .*
+.*:138: Error: .*
+.*:139: Error: .*
+.*:146: Error: .*
+.*:160: Error: .*
+.*:173: Error: .*
+.*:174: Error: .*
+.*:175: Error: .*
+.*:178: Error: .*
+.*:179: Error: .*
+.*:180: Error: .*
+.*:181: Error: .*
+.*:182: Error: .*
+.*:183: Error: .*
+.*:187: Error: .*
+.*:188: Error: .*
+.*:189: Error: .*
+.*:192: Error: .*
+.*:193: Error: .*
+.*:194: Error: .*
+.*:195: Error: .*
+.*:196: Error: .*
+.*:197: Error: .*
diff --git a/gas/testsuite/gas/i386/reloc64.s b/gas/testsuite/gas/i386/reloc64.s
new file mode 100644
index 000000000000..47ebfa8dc0ad
--- /dev/null
+++ b/gas/testsuite/gas/i386/reloc64.s
@@ -0,0 +1,197 @@
+ .macro bad args:vararg
+  .ifdef _bad_
+	\args
+  .endif
+ .endm
+
+ .macro ill args:vararg
+  # This is used to mark entries that aren't handled consistently,
+  # and thus shouldn't currently be checked for.
+  #	\args
+ .endm
+
+ .text
+_start:
+	movabs	$xtrn, %rax
+	add	$xtrn, %rax
+	mov	$xtrn, %eax
+	mov	$xtrn, %ax
+	mov	$xtrn, %al
+	mov	xtrn(%rbx), %eax
+	mov	xtrn(%ebx), %eax
+
+	movabs	$(xtrn - .), %rax
+	add	$(xtrn - .), %rax
+ill	mov	$(xtrn - .), %eax
+	mov	$(xtrn - .), %ax
+	mov	$(xtrn - .), %al
+	mov	xtrn(%rip), %eax
+bad	mov	xtrn(%eip), %eax
+	call	xtrn
+	jrcxz	xtrn
+
+	movabs	$xtrn@got, %rax
+	add	$xtrn@got, %rax
+bad	mov	$xtrn@got, %eax
+bad	mov	$xtrn@got, %ax
+bad	mov	$xtrn@got, %al
+	mov	xtrn@got(%rbx), %eax
+bad	mov	xtrn@got(%ebx), %eax
+bad	call	xtrn@got
+
+	movabs	$xtrn@gotoff, %rax
+bad	add	$xtrn@gotoff, %rax
+bad	mov	$xtrn@gotoff, %eax
+bad	mov	$xtrn@gotoff, %ax
+bad	mov	$xtrn@gotoff, %al
+bad	mov	xtrn@gotoff(%rbx), %eax
+bad	mov	xtrn@gotoff(%ebx), %eax
+bad	call	xtrn@gotoff
+
+bad	movabs	$xtrn@gotpcrel, %rax
+	add	$xtrn@gotpcrel, %rax
+bad	mov	$xtrn@gotpcrel, %eax
+bad	mov	$xtrn@gotpcrel, %ax
+bad	mov	$xtrn@gotpcrel, %al
+	mov	xtrn@gotpcrel(%rbx), %eax
+bad	mov	xtrn@gotpcrel(%ebx), %eax
+	call	xtrn@gotpcrel
+
+ill	movabs	$_GLOBAL_OFFSET_TABLE_, %rax
+	add	$_GLOBAL_OFFSET_TABLE_, %rax
+ill	add	$_GLOBAL_OFFSET_TABLE_, %eax
+ill	add	$_GLOBAL_OFFSET_TABLE_, %ax
+ill	add	$_GLOBAL_OFFSET_TABLE_, %al
+	lea	_GLOBAL_OFFSET_TABLE_(%rip), %rax #???
+bad	lea	_GLOBAL_OFFSET_TABLE_(%eip), %rax
+ill	movabs	$(_GLOBAL_OFFSET_TABLE_ - .), %rax
+	add	$(_GLOBAL_OFFSET_TABLE_ - .), %rax
+ill	add	$(_GLOBAL_OFFSET_TABLE_ - .), %eax
+ill	add	$(_GLOBAL_OFFSET_TABLE_ - .), %ax
+ill	add	$(_GLOBAL_OFFSET_TABLE_ - .), %al
+
+bad	movabs	$xtrn@plt, %rax
+	add	$xtrn@plt, %rax
+bad	mov	$xtrn@plt, %eax
+bad	mov	$xtrn@plt, %ax
+bad	mov	$xtrn@plt, %al
+	mov	xtrn@plt(%rbx), %eax
+bad	mov	xtrn@plt(%ebx), %eax
+	call	xtrn@plt
+bad	jrcxz	xtrn@plt
+
+bad	movabs	$xtrn@tlsgd, %rax
+	add	$xtrn@tlsgd, %rax
+bad	mov	$xtrn@tlsgd, %eax
+bad	mov	$xtrn@tlsgd, %ax
+bad	mov	$xtrn@tlsgd, %al
+	mov	xtrn@tlsgd(%rbx), %eax
+bad	mov	xtrn@tlsgd(%ebx), %eax
+	call	xtrn@tlsgd
+
+bad	movabs	$xtrn@gottpoff, %rax
+	add	$xtrn@gottpoff, %rax
+bad	mov	$xtrn@gottpoff, %eax
+bad	mov	$xtrn@gottpoff, %ax
+bad	mov	$xtrn@gottpoff, %al
+	mov	xtrn@gottpoff(%rbx), %eax
+bad	mov	xtrn@gottpoff(%ebx), %eax
+	call	xtrn@gottpoff
+
+bad	movabs	$xtrn@tlsld, %rax
+	add	$xtrn@tlsld, %rax
+bad	mov	$xtrn@tlsld, %eax
+bad	mov	$xtrn@tlsld, %ax
+bad	mov	$xtrn@tlsld, %al
+	mov	xtrn@tlsld(%rbx), %eax
+bad	mov	xtrn@tlsld(%ebx), %eax
+	call	xtrn@tlsld
+
+	movabs	$xtrn@dtpoff, %rax
+	add	$xtrn@dtpoff, %rax
+bad	mov	$xtrn@dtpoff, %eax
+bad	mov	$xtrn@dtpoff, %ax
+bad	mov	$xtrn@dtpoff, %al
+	mov	xtrn@dtpoff(%rbx), %eax
+bad	mov	xtrn@dtpoff(%ebx), %eax
+bad	call	xtrn@dtpoff
+
+	movabs	$xtrn@tpoff, %rax
+	add	$xtrn@tpoff, %rax
+bad	mov	$xtrn@tpoff, %eax
+bad	mov	$xtrn@tpoff, %ax
+bad	mov	$xtrn@tpoff, %al
+	mov	xtrn@tpoff(%rbx), %eax
+bad	mov	xtrn@tpoff(%ebx), %eax
+bad	call	xtrn@tpoff
+
+ .data
+	.quad	xtrn
+	.quad	xtrn - .
+	.quad	xtrn@got
+	.quad	xtrn@gotoff
+	.quad	xtrn@gotpcrel
+ill	.quad	_GLOBAL_OFFSET_TABLE_
+ill	.quad	_GLOBAL_OFFSET_TABLE_ - .
+bad	.quad	xtrn@plt
+bad	.quad	xtrn@tlsgd
+bad	.quad	xtrn@gottpoff
+bad	.quad	xtrn@tlsld
+	.quad	xtrn@dtpoff
+	.quad	xtrn@tpoff
+	
+	.long	xtrn
+	.long	xtrn - .
+	.long	xtrn@got
+bad	.long	xtrn@gotoff
+	.long	xtrn@gotpcrel
+	.long	_GLOBAL_OFFSET_TABLE_
+	.long	_GLOBAL_OFFSET_TABLE_ - .
+	.long	xtrn@plt
+	.long	xtrn@tlsgd
+	.long	xtrn@gottpoff
+	.long	xtrn@tlsld
+	.long	xtrn@dtpoff
+	.long	xtrn@tpoff
+	
+	.slong	xtrn
+	.slong	xtrn - .
+	.slong	xtrn@got
+bad	.slong	xtrn@gotoff
+	.slong	xtrn@gotpcrel
+	.slong	_GLOBAL_OFFSET_TABLE_
+	.slong	_GLOBAL_OFFSET_TABLE_ - .
+	.slong	xtrn@plt
+	.slong	xtrn@tlsgd
+	.slong	xtrn@gottpoff
+	.slong	xtrn@tlsld
+	.slong	xtrn@dtpoff
+	.slong	xtrn@tpoff
+	
+	.word	xtrn
+	.word	xtrn - .
+bad	.word	xtrn@got
+bad	.word	xtrn@gotoff
+bad	.word	xtrn@gotpcrel
+ill	.word	_GLOBAL_OFFSET_TABLE_
+ill	.word	_GLOBAL_OFFSET_TABLE_ - .
+bad	.word	xtrn@plt
+bad	.word	xtrn@tlsgd
+bad	.word	xtrn@gottpoff
+bad	.word	xtrn@tlsld
+bad	.word	xtrn@dtpoff
+bad	.word	xtrn@tpoff
+
+	.byte	xtrn
+	.byte	xtrn - .
+bad	.byte	xtrn@got
+bad	.byte	xtrn@gotoff
+bad	.byte	xtrn@gotpcrel
+ill	.byte	_GLOBAL_OFFSET_TABLE_
+ill	.byte	_GLOBAL_OFFSET_TABLE_ - .
+bad	.byte	xtrn@plt
+bad	.byte	xtrn@tlsgd
+bad	.byte	xtrn@gottpoff
+bad	.byte	xtrn@tlsld
+bad	.byte	xtrn@dtpoff
+bad	.byte	xtrn@tpoff
diff --git a/gas/testsuite/gas/i386/rep-suffix.d b/gas/testsuite/gas/i386/rep-suffix.d
new file mode 100644
index 000000000000..9eaaf3dd5d98
--- /dev/null
+++ b/gas/testsuite/gas/i386/rep-suffix.d
@@ -0,0 +1,15 @@
+#objdump: -dwMsuffix
+#name: i386 rep prefix (with suffixes)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_start>:
+   0:	f3 ac[ 	]+rep lodsb %ds:\(%esi\),%al
+   2:	f3 aa[ 	]+rep stosb %al,%es:\(%edi\)
+   4:	f3 66 ad[ 	]+rep lodsw %ds:\(%esi\),%ax
+   7:	f3 66 ab[ 	]+rep stosw %ax,%es:\(%edi\)
+   a:	f3 ad[ 	]+rep lodsl %ds:\(%esi\),%eax
+   c:	f3 ab[ 	]+rep stosl %eax,%es:\(%edi\)
+#pass
diff --git a/gas/testsuite/gas/i386/rep-suffix.s b/gas/testsuite/gas/i386/rep-suffix.s
new file mode 100644
index 000000000000..be54877bf5aa
--- /dev/null
+++ b/gas/testsuite/gas/i386/rep-suffix.s
@@ -0,0 +1,9 @@
+# Disassembling with -Msuffix.
+	.text
+_start:
+	rep lodsb
+	rep stosb
+	rep lodsw
+	rep stosw
+	rep lodsl
+	rep stosl
diff --git a/gas/testsuite/gas/i386/rep.d b/gas/testsuite/gas/i386/rep.d
new file mode 100644
index 000000000000..f43cc5feb6cf
--- /dev/null
+++ b/gas/testsuite/gas/i386/rep.d
@@ -0,0 +1,51 @@
+#objdump: -dw
+#name: i386 rep prefix
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+   0:	f3 6c[ 	]+rep insb \(%dx\),%es:\(%edi\)
+   2:	f3 6e[ 	]+rep outsb %ds:\(%esi\),\(%dx\)
+   4:	f3 a4[ 	]+rep movsb %ds:\(%esi\),%es:\(%edi\)
+   6:	f3 ac[ 	]+rep lods %ds:\(%esi\),%al
+   8:	f3 aa[ 	]+rep stos %al,%es:\(%edi\)
+   a:	f3 a6[ 	]+repz cmpsb %es:\(%edi\),%ds:\(%esi\)
+   c:	f3 ae[ 	]+repz scas %es:\(%edi\),%al
+   e:	f3 66 6d[ 	]+rep insw \(%dx\),%es:\(%edi\)
+  11:	f3 66 6f[ 	]+rep outsw %ds:\(%esi\),\(%dx\)
+  14:	f3 66 a5[ 	]+rep movsw %ds:\(%esi\),%es:\(%edi\)
+  17:	f3 66 ad[ 	]+rep lods %ds:\(%esi\),%ax
+  1a:	f3 66 ab[ 	]+rep stos %ax,%es:\(%edi\)
+  1d:	f3 66 a7[ 	]+repz cmpsw %es:\(%edi\),%ds:\(%esi\)
+  20:	f3 66 af[ 	]+repz scas %es:\(%edi\),%ax
+  23:	f3 6d[ 	]+rep insl \(%dx\),%es:\(%edi\)
+  25:	f3 6f[ 	]+rep outsl %ds:\(%esi\),\(%dx\)
+  27:	f3 a5[ 	]+rep movsl %ds:\(%esi\),%es:\(%edi\)
+  29:	f3 ad[ 	]+rep lods %ds:\(%esi\),%eax
+  2b:	f3 ab[ 	]+rep stos %eax,%es:\(%edi\)
+  2d:	f3 a7[ 	]+repz cmpsl %es:\(%edi\),%ds:\(%esi\)
+  2f:	f3 af[ 	]+repz scas %es:\(%edi\),%eax
+  31:	f3 67 6c[ 	]+rep addr16 insb \(%dx\),%es:\(%di\)
+  34:	f3 67 6e[ 	]+rep addr16 outsb %ds:\(%si\),\(%dx\)
+  37:	f3 67 a4[ 	]+rep addr16 movsb %ds:\(%si\),%es:\(%di\)
+  3a:	f3 67 ac[ 	]+rep addr16 lods %ds:\(%si\),%al
+  3d:	f3 67 aa[ 	]+rep addr16 stos %al,%es:\(%di\)
+  40:	f3 67 a6[ 	]+repz addr16 cmpsb %es:\(%di\),%ds:\(%si\)
+  43:	f3 67 ae[ 	]+repz addr16 scas %es:\(%di\),%al
+  46:	f3 67 66 6d[ 	]+rep addr16 insw \(%dx\),%es:\(%di\)
+  4a:	f3 67 66 6f[ 	]+rep addr16 outsw %ds:\(%si\),\(%dx\)
+  4e:	f3 67 66 a5[ 	]+rep addr16 movsw %ds:\(%si\),%es:\(%di\)
+  52:	f3 67 66 ad[ 	]+rep addr16 lods %ds:\(%si\),%ax
+  56:	f3 67 66 ab[ 	]+rep addr16 stos %ax,%es:\(%di\)
+  5a:	f3 67 66 a7[ 	]+repz addr16 cmpsw %es:\(%di\),%ds:\(%si\)
+  5e:	f3 67 66 af[ 	]+repz addr16 scas %es:\(%di\),%ax
+  62:	f3 67 6d[ 	]+rep addr16 insl \(%dx\),%es:\(%di\)
+  65:	f3 67 6f[ 	]+rep addr16 outsl %ds:\(%si\),\(%dx\)
+  68:	f3 67 a5[ 	]+rep addr16 movsl %ds:\(%si\),%es:\(%di\)
+  6b:	f3 67 ad[ 	]+rep addr16 lods %ds:\(%si\),%eax
+  6e:	f3 67 ab[ 	]+rep addr16 stos %eax,%es:\(%di\)
+  71:	f3 67 a7[ 	]+repz addr16 cmpsl %es:\(%di\),%ds:\(%si\)
+  74:	f3 67 af[ 	]+repz addr16 scas %es:\(%di\),%eax
+	...
diff --git a/gas/testsuite/gas/i386/rep.s b/gas/testsuite/gas/i386/rep.s
new file mode 100644
index 000000000000..cbda8b3dcd10
--- /dev/null
+++ b/gas/testsuite/gas/i386/rep.s
@@ -0,0 +1,52 @@
+ 	.text
+
+_start:
+	rep insb
+	rep outsb
+	rep movsb
+	rep lodsb
+	rep stosb
+	repz cmpsb
+	repz scasb
+
+	rep insw
+	rep outsw
+	rep movsw
+	rep lodsw
+	rep stosw
+	repz cmpsw
+	repz scasw
+
+	rep insl
+	rep outsl
+	rep movsl
+	rep lodsl
+	rep stosl
+	repz cmpsl
+	repz scasl
+
+	addr16 rep insb
+	addr16 rep outsb
+	addr16 rep movsb
+	addr16 rep lodsb
+	addr16 rep stosb
+	addr16 repz cmpsb
+	addr16 repz scasb
+
+	addr16 rep insw
+	addr16 rep outsw
+	addr16 rep movsw
+	addr16 rep lodsw
+	addr16 rep stosw
+	addr16 repz cmpsw
+	addr16 repz scasw
+
+	addr16 rep insl
+	addr16 rep outsl
+	addr16 rep movsl
+	addr16 rep lodsl
+	addr16 rep stosl
+	addr16 repz cmpsl
+	addr16 repz scasl
+
+	.p2align        4,0
diff --git a/gas/testsuite/gas/i386/rex.d b/gas/testsuite/gas/i386/rex.d
new file mode 100644
index 000000000000..dab6b12580d1
--- /dev/null
+++ b/gas/testsuite/gas/i386/rex.d
@@ -0,0 +1,17 @@
+#objdump: -dw
+#name: x86-64 manual rex prefix use
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[	 ]*[0-9a-f]+:[	 ]+40 0f ae 00[	 ]+rex fxsavel?[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+48 0f ae 00[	 ]+(rex64 )?fxsaveq?[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+41 0f ae 00[	 ]+fxsavel?[	 ]+\(%r8\)
+[	 ]*[0-9a-f]+:[	 ]+49 0f ae 00[	 ]+(rex64Z? )?fxsaveq?[	 ]+\(%r8\)
+[	 ]*[0-9a-f]+:[	 ]+42 0f ae 04 05 00 00 00 00[	 ]+fxsavel?[	 ]+(0x0)?\(,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+4a 0f ae 04 05 00 00 00 00[	 ]+(rex64Y? )?fxsaveq?[	 ]+(0x0)?\(,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+43 0f ae 04 00[	 ]+fxsavel?[	 ]+\(%r8,%r8(,1)?\)
+[	 ]*[0-9a-f]+:[	 ]+4b 0f ae 04 00[	 ]+(rex64(YZ)? )?fxsaveq?[	 ]+\(%r8,%r8(,1)?\)
+#pass
diff --git a/gas/testsuite/gas/i386/rex.s b/gas/testsuite/gas/i386/rex.s
new file mode 100644
index 000000000000..a142312a2c6b
--- /dev/null
+++ b/gas/testsuite/gas/i386/rex.s
@@ -0,0 +1,11 @@
+ .text
+
+_start:
+	rex/fxsave (%rax)
+	rex64/fxsave (%rax)
+	rex/fxsave (%r8)
+	rex64/fxsave (%r8)
+	rex/fxsave (,%r8)
+	rex64/fxsave (,%r8)
+	rex/fxsave (%r8,%r8)
+	rex64/fxsave (%r8,%r8)
diff --git a/gas/testsuite/gas/i386/secrel.d b/gas/testsuite/gas/i386/secrel.d
new file mode 100644
index 000000000000..6a3b915fd77d
--- /dev/null
+++ b/gas/testsuite/gas/i386/secrel.d
@@ -0,0 +1,43 @@
+#objdump: -rs

+#name: i386 secrel reloc

+

+.*: +file format pe-i386

+

+RELOCATION RECORDS FOR \[\.data\]:

+OFFSET   TYPE              VALUE 

+00000024 secrel32          \.text

+00000029 secrel32          \.text

+0000002e secrel32          \.text

+00000033 secrel32          \.text

+00000044 secrel32          \.data

+00000049 secrel32          \.data

+0000004e secrel32          \.data

+00000053 secrel32          \.data

+00000064 secrel32          \.rdata

+00000069 secrel32          \.rdata

+0000006e secrel32          \.rdata

+00000073 secrel32          \.rdata

+00000084 secrel32          ext24

+00000089 secrel32          ext2d

+0000008e secrel32          ext36

+00000093 secrel32          ext3f

+

+

+Contents of section \.text:

+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+Contents of section \.data:

+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ 0020 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ 0030 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ 0040 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ 0050 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ 0060 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ 0070 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ 0080 3e3e3e3e 00000000 11000000 00110000  >>>>............

+ 0090 00001100 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+Contents of section \.rdata:

+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ 0020 3e3e3e3e 00000000 00000000 00000000  >>>>............

diff --git a/gas/testsuite/gas/i386/secrel.s b/gas/testsuite/gas/i386/secrel.s
new file mode 100644
index 000000000000..c16299016b68
--- /dev/null
+++ b/gas/testsuite/gas/i386/secrel.s
@@ -0,0 +1,79 @@
+.text

+

+	.ascii ">>>>"

+pre04:	.ascii "<<<<"

+	.ascii ">>>>>"

+pre0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+pre16:	.ascii "<<"

+	.ascii ">>>>>>>"

+pre1f:	.ascii "<"

+

+.data

+

+	.ascii ">>>>"

+sam04:	.ascii "<<<<"

+	.ascii ">>>>>"

+sam0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+sam16:	.ascii "<<"

+	.ascii ">>>>>>>"

+sam1f:	.ascii "<"

+

+	.ascii ">>>>"

+	.secrel32 pre04

+	.byte 0x11

+	.secrel32 pre0d

+	.byte 0x11

+	.secrel32 pre16

+	.byte 0x11

+	.secrel32 pre1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 sam04

+	.byte 0x11

+	.secrel32 sam0d

+	.byte 0x11

+	.secrel32 sam16

+	.byte 0x11

+	.secrel32 sam1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 nex04

+	.byte 0x11

+	.secrel32 nex0d

+	.byte 0x11

+	.secrel32 nex16

+	.byte 0x11

+	.secrel32 nex1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 ext24

+	.byte 0x11

+	.secrel32 ext2d

+	.byte 0x11

+	.secrel32 ext36

+	.byte 0x11

+	.secrel32 ext3f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+.section .rdata

+

+	.ascii ">>>>"

+nex04:	.ascii "<<<<"

+	.ascii ">>>>>"

+nex0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+nex16:	.ascii "<<"

+	.ascii ">>>>>>>"

+nex1f:	.ascii "<"

+	.ascii ">>>>"

+

+	.p2align 4,0

diff --git a/gas/testsuite/gas/i386/segment.l b/gas/testsuite/gas/i386/segment.l
new file mode 100644
index 000000000000..59c081e30599
--- /dev/null
+++ b/gas/testsuite/gas/i386/segment.l
@@ -0,0 +1,10 @@
+   1              	.psize 0
+   2              	.text
+   3              	# test segment reg insns with memory operand
+   4 0000 8C18     		movw	%ds,\(%eax\)
+   5 0002 8C18     		mov	%ds,\(%eax\)
+   6 0004 8E18     		movw	\(%eax\),%ds
+   7 0006 8E18     		mov	\(%eax\),%ds
+   8              		# Force a good alignment.
+   9 0008 00000000 		.p2align	4,0
+   9      00000000 
diff --git a/gas/testsuite/gas/i386/segment.s b/gas/testsuite/gas/i386/segment.s
new file mode 100644
index 000000000000..6c2850ccc706
--- /dev/null
+++ b/gas/testsuite/gas/i386/segment.s
@@ -0,0 +1,9 @@
+.psize 0
+.text
+# test segment reg insns with memory operand
+	movw	%ds,(%eax)
+	mov	%ds,(%eax)
+	movw	(%eax),%ds
+	mov	(%eax),%ds
+	# Force a good alignment.
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/sib.d b/gas/testsuite/gas/i386/sib.d
new file mode 100644
index 000000000000..2a5dbb6c9c9a
--- /dev/null
+++ b/gas/testsuite/gas/i386/sib.d
@@ -0,0 +1,15 @@
+#objdump: -dw
+#name: i386 SIB
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	8b 04 23 [ 	]*mov [ 	]*\(%ebx\),%eax
+   3:	8b 04 63 [ 	]*mov [ 	]*\(%ebx\),%eax
+   6:	8b 04 a3 [ 	]*mov [ 	]*\(%ebx\),%eax
+   9:	8b 04 e3 [ 	]*mov [ 	]*\(%ebx\),%eax
+   c:	90 [ 	]*nop [ 	]*
+   d:	90 [ 	]*nop [ 	]*
+	...
diff --git a/gas/testsuite/gas/i386/sib.s b/gas/testsuite/gas/i386/sib.s
new file mode 100644
index 000000000000..25d88b75a6da
--- /dev/null
+++ b/gas/testsuite/gas/i386/sib.s
@@ -0,0 +1,11 @@
+#Test the special case of the index bits, 0x4, in SIB.
+
+	.text
+foo:
+	.byte	0x8B, 0x04, 0x23	# effect is: movl (%ebx), %eax
+	.byte	0x8B, 0x04, 0x63	# effect is: movl (%ebx), %eax	
+	.byte	0x8B, 0x04, 0xA3	# effect is: movl (%ebx), %eax
+	.byte	0x8B, 0x04, 0xE3	# effect is: movl (%ebx), %eax
+	nop
+	nop
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/sub.d b/gas/testsuite/gas/i386/sub.d
index d4ac3f774ddb..fd5e5fa594cb 100644
--- a/gas/testsuite/gas/i386/sub.d
+++ b/gas/testsuite/gas/i386/sub.d
@@ -7,4 +7,4 @@ Disassembly of section .text:
 
 0+000 <foo>:
    0:	66 be (0|1)(0|2|4) 00[ 	]+mov[ 	]+\$0x(1)?(0|2|4),%si[ 	]+2:[ 	]+(R_386_PC|DISP)16[ 	]+.data(\+0xfffffff0)?
-.*
+#pass
diff --git a/gas/testsuite/gas/i386/suffix.d b/gas/testsuite/gas/i386/suffix.d
new file mode 100644
index 000000000000..fa57bb7e2653
--- /dev/null
+++ b/gas/testsuite/gas/i386/suffix.d
@@ -0,0 +1,15 @@
+#objdump: -dw -Msuffix
+#name: i386 suffix
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 01 c8 [ 	]*monitor %eax,%ecx,%edx
+   3:	0f 01 c9 [ 	]*mwait  %eax,%ecx
+   6:	0f 01 c1 [ 	]*vmcall 
+   9:	0f 01 c2 [ 	]*vmlaunch 
+   c:	0f 01 c3 [ 	]*vmresume 
+   f:	0f 01 c4 [ 	]*vmxoff 
+	...
diff --git a/gas/testsuite/gas/i386/suffix.s b/gas/testsuite/gas/i386/suffix.s
new file mode 100644
index 000000000000..2ce1c3dcd809
--- /dev/null
+++ b/gas/testsuite/gas/i386/suffix.s
@@ -0,0 +1,13 @@
+# Disassembling with -Msuffix.
+
+	.text
+foo:
+	monitor
+	mwait
+
+	vmcall
+	vmlaunch
+	vmresume
+	vmxoff
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/svme.d b/gas/testsuite/gas/i386/svme.d
new file mode 100644
index 000000000000..d7682a470652
--- /dev/null
+++ b/gas/testsuite/gas/i386/svme.d
@@ -0,0 +1,29 @@
+#objdump: -dw
+#name: 32-bit SVME
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <common>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 dd[	 ]+clgi[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 dc[	 ]+stgi[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d9[	 ]+vmmcall[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <att32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <intel32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+#pass
diff --git a/gas/testsuite/gas/i386/svme.s b/gas/testsuite/gas/i386/svme.s
new file mode 100644
index 000000000000..1b7f2347cf14
--- /dev/null
+++ b/gas/testsuite/gas/i386/svme.s
@@ -0,0 +1,36 @@
+	.text
+common:
+	clgi
+	invlpga
+	skinit
+	stgi
+	vmload
+	vmmcall
+	vmrun
+	vmsave
+
+.macro do_args arg1, arg2
+	invlpga	\arg1, \arg2
+	vmload	\arg1
+	vmrun	\arg1
+	vmsave	\arg1
+.endm
+
+.ifdef __amd64__
+att64:
+	do_args	(%rax), %ecx
+.endif
+att32:
+	skinit	(%eax)
+	do_args	(%eax), %ecx
+
+.intel_syntax noprefix
+.ifdef __amd64__
+intel64:
+	do_args	[rax], ecx
+.endif
+intel32:
+	skinit	[eax]
+	do_args	[eax], ecx
+
+	.p2align 4,0
diff --git a/gas/testsuite/gas/i386/svme64.d b/gas/testsuite/gas/i386/svme64.d
new file mode 100644
index 000000000000..876d4396340d
--- /dev/null
+++ b/gas/testsuite/gas/i386/svme64.d
@@ -0,0 +1,41 @@
+#as: --defsym __amd64__=1
+#objdump: -dw
+#name: 64-bit SVME
+#source: svme.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <common>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 dd[	 ]+clgi[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 dc[	 ]+stgi[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d9[	 ]+vmmcall[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <att64>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <att32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 df[	 ]+(addr32 )?invlpga[	 ]*\(%eax\),[	 ]*%ecx
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 da[	 ]+(addr32 )?vmload[	 ]*\(%eax\)
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 d8[	 ]+(addr32 )?vmrun[	 ]*\(%eax\)
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 db[	 ]+(addr32 )?vmsave[	 ]*\(%eax\)
+[0-9a-f]+ <intel64>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 df[	 ]+invlpga[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 da[	 ]+vmload[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 d8[	 ]+vmrun[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 db[	 ]+vmsave[	 ]*
+[0-9a-f]+ <intel32>:
+[	 ]*[0-9a-f]+:[	 ]+0f 01 de[	 ]+skinit[	 ]*
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 df[	 ]+(addr32 )?invlpga[	 ]*\(%eax\),[	 ]*%ecx
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 da[	 ]+(addr32 )?vmload[	 ]*\(%eax\)
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 d8[	 ]+(addr32 )?vmrun[	 ]*\(%eax\)
+[	 ]*[0-9a-f]+:[	 ]+67 0f 01 db[	 ]+(addr32 )?vmsave[	 ]*\(%eax\)
+#pass
diff --git a/gas/testsuite/gas/i386/tlsd.d b/gas/testsuite/gas/i386/tlsd.d
index 62efaa34507d..bbf6fd49cfa9 100644
--- a/gas/testsuite/gas/i386/tlsd.d
+++ b/gas/testsuite/gas/i386/tlsd.d
@@ -22,10 +22,10 @@ Disassembly of section .text:
 [ 	]+1f: R_386_TLS_LDM	bar
   23:	e8 fc ff ff ff [ 	]*call   24 <fn\+0x24>
 [ 	]+24: R_386_PLT32	___tls_get_addr
-  28:	8d 7f 00 [ 	]*lea    0x0\(%edi\),%edi
+  28:	83 c7 00 [ 	]*add    \$0x0,%edi
   2b:	8d 90 00 00 00 00 [ 	]*lea    0x0\(%eax\),%edx
 [ 	]+2d: R_386_TLS_LDO_32	bar
-  31:	8d 76 00 [ 	]*lea    0x0\(%esi\),%esi
+  31:	83 c6 00 [ 	]*add    \$0x0,%esi
   34:	8d 88 00 00 00 00 [ 	]*lea    0x0\(%eax\),%ecx
 [ 	]+36: R_386_TLS_LDO_32	baz
   3a:	8b 5d fc [ 	]*mov    0xfffffffc\(%ebp\),%ebx
diff --git a/gas/testsuite/gas/i386/tlsd.s b/gas/testsuite/gas/i386/tlsd.s
index 9ce01ec708d8..f5c2c50e0dd3 100644
--- a/gas/testsuite/gas/i386/tlsd.s
+++ b/gas/testsuite/gas/i386/tlsd.s
@@ -26,13 +26,13 @@ fn:
 	call	___tls_get_addr@PLT
 
 	/* Just show that there can be arbitrary instructions here  */
-	leal	0(%edi, 1), %edi
+	addl	$0, %edi
 
 	leal	bar@DTPOFF(%eax), %edx
 	/* %edx now contains &bar  */
 
 	/* Again, arbitrary instructions  */
-	leal	0(%esi, 1), %esi
+	addl	$0, %esi
 
 	leal	baz@DTPOFF(%eax), %ecx
 	/* %ecx now contains &baz  */
diff --git a/gas/testsuite/gas/i386/tlspic.d b/gas/testsuite/gas/i386/tlspic.d
index fbe83a47c4a4..bd5dbb7bace9 100644
--- a/gas/testsuite/gas/i386/tlspic.d
+++ b/gas/testsuite/gas/i386/tlspic.d
@@ -1,5 +1,5 @@
 #objdump: -dr
-#name: i386 non-pic tls
+#name: i386 pic tls
 
 .*: +file format .*
 
@@ -15,12 +15,12 @@ Disassembly of section .text:
    b:	81 c3 03 00 00 00 [ 	]*add    \$0x3,%ebx
 [ 	]+d: R_386_GOTPC	_GLOBAL_OFFSET_TABLE_
   11:	65 a1 00 00 00 00 [ 	]*mov    %gs:0x0,%eax
-  17:	8d 76 00 [ 	]*lea    0x0\(%esi\),%esi
+  17:	83 c6 00 [ 	]*add    \$0x0,%esi
   1a:	2b 83 00 00 00 00 [ 	]*sub    0x0\(%ebx\),%eax
 [ 	]+1c: R_386_TLS_IE_32	foo
   20:	8b 83 00 00 00 00 [ 	]*mov    0x0\(%ebx\),%eax
 [ 	]+22: R_386_TLS_GOTIE	foo
-  26:	8d 76 00 [ 	]*lea    0x0\(%esi\),%esi
+  26:	83 c6 00 [ 	]*add    \$0x0,%esi
   29:	65 8b 00 [ 	]*mov    %gs:\(%eax\),%eax
   2c:	65 8b 0d 00 00 00 00 [ 	]*mov    %gs:0x0,%ecx
   33:	03 8b 00 00 00 00 [ 	]*add    0x0\(%ebx\),%ecx
diff --git a/gas/testsuite/gas/i386/tlspic.s b/gas/testsuite/gas/i386/tlspic.s
index c9b97574ab55..bd63fd47b0fa 100644
--- a/gas/testsuite/gas/i386/tlspic.s
+++ b/gas/testsuite/gas/i386/tlspic.s
@@ -17,7 +17,7 @@ fn:
 	movl	%gs:0, %eax
 
 	/* Arbitrary instructions in between.  */
-	leal	0(%esi, 1), %esi
+	addl	$0, %esi
 
 	subl	foo@GOTTPOFF(%ebx), %eax
 	/* %eax now contains &foo  */
@@ -26,7 +26,7 @@ fn:
 	movl	foo@GOTNTPOFF(%ebx), %eax
 
 	/* Arbitrary instructions in between.  */
-	leal	0(%esi, 1), %esi
+	addl	$0, %esi
 
 	movl	%gs:(%eax), %eax
 	/* %eax now contains foo  */
diff --git a/gas/testsuite/gas/i386/vmx.d b/gas/testsuite/gas/i386/vmx.d
new file mode 100644
index 000000000000..334702d9c295
--- /dev/null
+++ b/gas/testsuite/gas/i386/vmx.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: i386 VMX
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 01 c1 [ 	]*vmcall 
+   3:	0f 01 c2 [ 	]*vmlaunch 
+   6:	0f 01 c3 [ 	]*vmresume 
+   9:	0f 01 c4 [ 	]*vmxoff 
+   c:	66 0f c7 30 [ 	]*vmclear \(%eax\)
+  10:	0f c7 30 [ 	]*vmptrld \(%eax\)
+  13:	0f c7 38 [ 	]*vmptrst \(%eax\)
+  16:	f3 0f c7 30 [ 	]*vmxon  \(%eax\)
+  1a:	0f 78 c3 [ 	]*vmread %eax,%ebx
+  1d:	0f 78 c3 [ 	]*vmread %eax,%ebx
+  20:	0f 78 03 [ 	]*vmread %eax,\(%ebx\)
+  23:	0f 78 03 [ 	]*vmread %eax,\(%ebx\)
+  26:	0f 79 d8 [ 	]*vmwrite %eax,%ebx
+  29:	0f 79 d8 [ 	]*vmwrite %eax,%ebx
+  2c:	0f 79 18 [ 	]*vmwrite \(%eax\),%ebx
+  2f:	0f 79 18 [ 	]*vmwrite \(%eax\),%ebx
+	...
diff --git a/gas/testsuite/gas/i386/vmx.s b/gas/testsuite/gas/i386/vmx.s
new file mode 100644
index 000000000000..9f52b3fdeade
--- /dev/null
+++ b/gas/testsuite/gas/i386/vmx.s
@@ -0,0 +1,21 @@
+# VMX Instructions
+
+	.text
+foo:
+	vmcall
+	vmlaunch
+	vmresume
+	vmxoff
+	vmclear (%eax)
+	vmptrld (%eax)
+	vmptrst (%eax)
+	vmxon (%eax)
+	vmread %eax,%ebx
+	vmreadl %eax,%ebx
+	vmread %eax,(%ebx)
+	vmreadl %eax,(%ebx)
+	vmwrite %eax,%ebx
+	vmwritel %eax,%ebx
+	vmwrite (%eax),%ebx
+	vmwritel (%eax),%ebx
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-addr32.d b/gas/testsuite/gas/i386/x86-64-addr32.d
new file mode 100644
index 000000000000..c892fb1ba1d5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-addr32.d
@@ -0,0 +1,13 @@
+#as: -J
+#objdump: -drw
+#name: x86-64 32-bit addressing
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+67 48 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0\(%[re]ax\),%rax.*
+[	 ]*8:[	 ]+67 49 8d 80 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0\(%r8d?\),%rax.*
+[	 ]*10:[	 ]+67 48 8d 05 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0\(%[re]ip\),%rax.*
+[	 ]*18:[	 ]+67 48 8d 04 25 00 00 00 00[	 ]+addr32[	 ]+lea[ 	]+0x0,%rax.*
diff --git a/gas/testsuite/gas/i386/x86-64-addr32.s b/gas/testsuite/gas/i386/x86-64-addr32.s
new file mode 100644
index 000000000000..d18cbb91bcfc
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-addr32.s
@@ -0,0 +1,5 @@
+.text
+	lea		symbol(%eax), %rax
+	lea		symbol(%r8d), %rax
+	addr32 lea	symbol(%rip), %rax
+	addr32 lea	symbol, %rax
diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
new file mode 100644
index 000000000000..7ddd6fe17778
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -0,0 +1,13 @@
+#as: -J
+#objdump: -drw
+#name: x86-64 indirect branch
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+ff d0[	 ]+callq[	 ]+\*%rax
+[	 ]*2:[	 ]+ff d0[	 ]+callq[	 ]+\*%rax
+[	 ]*4:[	 ]+ff e0[	 ]+jmpq[	 ]+\*%rax
+[	 ]*6:[	 ]+ff e0[	 ]+jmpq[	 ]+\*%rax
diff --git a/gas/testsuite/gas/i386/x86-64-branch.s b/gas/testsuite/gas/i386/x86-64-branch.s
new file mode 100644
index 000000000000..865c4759012a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch.s
@@ -0,0 +1,5 @@
+.text
+	callq	*%rax
+	call	*%rax
+	jmpq	*%rax
+	jmp	*%rax
diff --git a/gas/testsuite/gas/i386/x86-64-crx-suffix.d b/gas/testsuite/gas/i386/x86-64-crx-suffix.d
new file mode 100644
index 000000000000..1dc3584219ed
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crx-suffix.d
@@ -0,0 +1,21 @@
+#objdump: -dwMsuffix
+#name: x86-64 control register related opcodes (with suffixes)
+#source: x86-64-crx.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq[ 	]+?%rdi,%cr8
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq[ 	]+?%rdi,%cr8
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq[ 	]+?%rdi,%cr8
diff --git a/gas/testsuite/gas/i386/x86-64-crx.d b/gas/testsuite/gas/i386/x86-64-crx.d
new file mode 100644
index 000000000000..8c1333f53693
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crx.d
@@ -0,0 +1,21 @@
+#objdump: -dw
+#name: x86-64 control register related opcodes
+#source: x86-64-crx.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq?[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq?[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq?[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq?[ 	]+?%rdi,%cr8
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq?[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq?[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq?[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq?[ 	]+?%rdi,%cr8
+[ 	]*[0-9a-f]+:	44 0f 20 c0[ 	]+movq?[ 	]+?%cr8,%rax
+[ 	]*[0-9a-f]+:	44 0f 20 c7[ 	]+movq?[ 	]+?%cr8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 22 c0[ 	]+movq?[ 	]+?%rax,%cr8
+[ 	]*[0-9a-f]+:	44 0f 22 c7[ 	]+movq?[ 	]+?%rdi,%cr8
diff --git a/gas/testsuite/gas/i386/x86-64-crx.s b/gas/testsuite/gas/i386/x86-64-crx.s
new file mode 100644
index 000000000000..bc288c3623b8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-crx.s
@@ -0,0 +1,18 @@
+.text
+_start:
+	movq	%cr8, %rax
+	movq	%cr8, %rdi
+	movq	%rax, %cr8
+	movq	%rdi, %cr8
+
+.att_syntax noprefix
+	movq	cr8, rax
+	movq	cr8, rdi
+	movq	rax, cr8
+	movq	rdi, cr8
+
+.intel_syntax noprefix
+	mov	rax, cr8
+	mov	rdi, cr8
+	mov	cr8, rax
+	mov	cr8, rdi
diff --git a/gas/testsuite/gas/i386/x86-64-drx-suffix.d b/gas/testsuite/gas/i386/x86-64-drx-suffix.d
new file mode 100644
index 000000000000..1f76b8b163b8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-drx-suffix.d
@@ -0,0 +1,21 @@
+#objdump: -dwMsuffix
+#name: x86-64 debug register related opcodes (with suffixes)
+#source: x86-64-drx.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq[ 	]+?%rdi,%db8
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq[ 	]+?%rdi,%db8
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq[ 	]+?%rdi,%db8
diff --git a/gas/testsuite/gas/i386/x86-64-drx.d b/gas/testsuite/gas/i386/x86-64-drx.d
new file mode 100644
index 000000000000..879ce50a5ef8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-drx.d
@@ -0,0 +1,20 @@
+#objdump: -dw
+#name: x86-64 debug register related opcodes
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq?[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq?[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq?[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq?[ 	]+?%rdi,%db8
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq?[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq?[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq?[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq?[ 	]+?%rdi,%db8
+[ 	]*[0-9a-f]+:	44 0f 21 c0[ 	]+movq?[ 	]+?%db8,%rax
+[ 	]*[0-9a-f]+:	44 0f 21 c7[ 	]+movq?[ 	]+?%db8,%rdi
+[ 	]*[0-9a-f]+:	44 0f 23 c0[ 	]+movq?[ 	]+?%rax,%db8
+[ 	]*[0-9a-f]+:	44 0f 23 c7[ 	]+movq?[ 	]+?%rdi,%db8
diff --git a/gas/testsuite/gas/i386/x86-64-drx.s b/gas/testsuite/gas/i386/x86-64-drx.s
new file mode 100644
index 000000000000..16801d189311
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-drx.s
@@ -0,0 +1,18 @@
+.text
+_start:
+	movq	%dr8, %rax
+	movq	%dr8, %rdi
+	movq	%rax, %dr8
+	movq	%rdi, %dr8
+
+.att_syntax noprefix
+	movq	dr8, rax
+	movq	dr8, rdi
+	movq	rax, dr8
+	movq	rdi, dr8
+
+.intel_syntax noprefix
+	mov	rax, dr8
+	mov	rdi, dr8
+	mov	dr8, rax
+	mov	dr8, rdi
diff --git a/gas/testsuite/gas/i386/x86-64-inval-seg.l b/gas/testsuite/gas/i386/x86-64-inval-seg.l
new file mode 100644
index 000000000000..adef5d41d444
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-seg.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*:3: Error: .*
+.*:4: Error: .*
+.*:5: Error: .*
+.*:6: Error: .*
+GAS LISTING .*
+
+
+   1 [ 	]*	.text
+   2 [ 	]*# All the following should be illegal
+   3 [ 	]*	movq	%ds,\(%rax\)
+   4 [ 	]*	movl	%ds,\(%rax\)
+   5 [ 	]*	movq	\(%rax\),%ds
+   6 [ 	]*	movl	\(%rax\),%ds
diff --git a/gas/testsuite/gas/i386/x86-64-inval-seg.s b/gas/testsuite/gas/i386/x86-64-inval-seg.s
new file mode 100644
index 000000000000..bb547422364a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-inval-seg.s
@@ -0,0 +1,6 @@
+	.text
+# All the following should be illegal
+	movq	%ds,(%rax)
+	movl	%ds,(%rax)
+	movq	(%rax),%ds
+	movl	(%rax),%ds
diff --git a/gas/testsuite/gas/i386/x86-64-inval.l b/gas/testsuite/gas/i386/x86-64-inval.l
index 05416d7c02e5..aa080cba46a6 100644
--- a/gas/testsuite/gas/i386/x86-64-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-inval.l
@@ -11,20 +11,94 @@
 .*:12: Error: .*
 .*:13: Error: .*
 .*:14: Error: .*
+.*:15: Error: .*
+.*:16: Error: .*
+.*:17: Error: .*
+.*:18: Error: .*
+.*:19: Error: .*
+.*:20: Error: .*
+.*:21: Error: .*
+.*:22: Error: .*
+.*:23: Error: .*
+.*:24: Error: .*
+.*:25: Error: .*
+.*:26: Error: .*
+.*:27: Error: .*
+.*:28: Error: .*
+.*:29: Error: .*
+.*:30: Error: .*
+.*:31: Error: .*
+.*:32: Error: .*
+.*:33: Error: .*
+.*:34: Error: .*
+.*:35: Error: .*
+.*:36: Error: .*
+.*:37: Error: .*
+.*:38: Error: .*
+.*:39: Error: .*
+.*:40: Error: .*
+.*:41: Error: .*
+.*:42: Error: .*
+.*:43: Error: .*
+.*:44: Error: .*
+.*:45: Error: .*
+.*:46: Error: .*
+.*:47: Error: .*
+.*:48: Error: .*
+.*:49: Error: .*
+.*:50: Error: .*
+.*:51: Error: .*
 GAS LISTING .*
 
 
-   1 [ 	]*	.text
+   1 [ 	]*.text
    2 [ 	]*# All the following should be illegal for x86-64
-   3 [ 	]*calll \*%eax	# 32-bit data size not allowed
-   4 [ 	]*calll \*\(%ax\)	# 32-bit data size not allowed
-   5 [ 	]*calll \*\(%eax\)	# 32-bit data size not allowed
-   6 [ 	]*calll \*\(%r8\)	# 32-bit data size not allowed
-   7 [ 	]*calll \*\(%rax\)	# 32-bit data size not allowed
-   8 [ 	]*callq \*\(%ax\)	# 32-bit data size not allowed
-   9 [ 	]*callw \*\(%ax\)	# no 16-bit addressing
-  10 [ 	]*foo:[ 	]*jcxz foo	# No prefix exists to select CX as a counter
-  11 [ 	]*popl %eax	# can\'t have 32-bit stack operands
-  12 [ 	]*pushl %eax	# can\'t have 32-bit stack operands
-  13 [ 	]*pushfl		# can\'t have 32-bit stack operands
-  14 [ 	]*popfl		# can\'t have 32-bit stack operands
+   3 [ 	]*aaa		# illegal
+   4 [ 	]*aad		# illegal
+   5 [ 	]*aam		# illegal
+   6 [ 	]*aas		# illegal
+   7 [ 	]*arpl %ax,%ax	# illegal
+   8 [ 	]*bound %eax,\(%rax\) # illegal
+   9 [ 	]*calll \*%eax	# 32-bit data size not allowed
+  10 [ 	]*calll \*\(%ax\)	# 32-bit data size not allowed
+  11 [ 	]*calll \*\(%eax\)	# 32-bit data size not allowed
+  12 [ 	]*calll \*\(%r8\)	# 32-bit data size not allowed
+  13 [ 	]*calll \*\(%rax\)	# 32-bit data size not allowed
+  14 [ 	]*callq \*\(%ax\)	# 32-bit data size not allowed
+  15 [ 	]*callw \*\(%ax\)	# no 16-bit addressing
+  16 [ 	]*daa		# illegal
+  17 [ 	]*das		# illegal
+  18 [ 	]*enterl \$0,\$0	# can't have 32-bit stack operands
+  19 [ 	]*into		# illegal
+  20 [ 	]*foo:[ 	]*jcxz foo	# No prefix exists to select CX as a counter
+  21 [ 	]*jmpl \*%eax	# 32-bit data size not allowed
+  22 [ 	]*jmpl \*\(%rax\)	# 32-bit data size not allowed
+  23 [ 	]*lcalll \$0,\$0	# illegal
+  24 [ 	]*lcallq \$0,\$0	# illegal
+  25 [ 	]*ldsl %eax,\(%rax\) # illegal
+  26 [ 	]*ldsq %rax,\(%rax\) # illegal
+  27 [ 	]*lesl %eax,\(%rax\) # illegal
+  28 [ 	]*lesq %rax,\(%rax\) # illegal
+  29 [ 	]*ljmpl \$0,\$0	# illegal
+  30 [ 	]*ljmpq \$0,\$0	# illegal
+  31 [ 	]*ljmpq \*\(%rax\)	# 64-bit data size not allowed
+  32 [ 	]*loopw foo	# No prefix exists to select CX as a counter
+  33 [ 	]*loopew foo	# No prefix exists to select CX as a counter
+  34 [ 	]*loopnew foo	# No prefix exists to select CX as a counter
+  35 [ 	]*loopnzw foo	# No prefix exists to select CX as a counter
+  36 [ 	]*loopzw foo	# No prefix exists to select CX as a counter
+  37 [ 	]*leavel		# can't have 32-bit stack operands
+  38 [ 	]*pop %ds		# illegal
+  39 [ 	]*pop %es		# illegal
+  40 [ 	]*pop %ss		# illegal
+  41 [ 	]*popa		# illegal
+  42 [ 	]*popl %eax	# can't have 32-bit stack operands
+  43 [ 	]*push %cs	# illegal
+  44 [ 	]*push %ds	# illegal
+  45 [ 	]*push %es	# illegal
+  46 [ 	]*push %ss	# illegal
+  47 [ 	]*pusha		# illegal
+  48 [ 	]*pushl %eax	# can't have 32-bit stack operands
+  49 [ 	]*pushfl		# can't have 32-bit stack operands
+  50 [ 	]*popfl		# can't have 32-bit stack operands
+  51 [ 	]*retl		# can't have 32-bit stack operands
diff --git a/gas/testsuite/gas/i386/x86-64-inval.s b/gas/testsuite/gas/i386/x86-64-inval.s
index be532d52a130..b069a282e5c5 100644
--- a/gas/testsuite/gas/i386/x86-64-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-inval.s
@@ -1,5 +1,11 @@
 	.text
 # All the following should be illegal for x86-64
+        aaa		# illegal
+        aad		# illegal
+        aam		# illegal
+        aas		# illegal
+        arpl %ax,%ax	# illegal
+        bound %eax,(%rax) # illegal
 	calll *%eax	# 32-bit data size not allowed
         calll *(%ax)	# 32-bit data size not allowed
         calll *(%eax)	# 32-bit data size not allowed
@@ -7,8 +13,39 @@
         calll *(%rax)	# 32-bit data size not allowed
         callq *(%ax)	# 32-bit data size not allowed
         callw *(%ax)	# no 16-bit addressing
+        daa		# illegal
+        das		# illegal
+        enterl $0,$0	# can't have 32-bit stack operands
+        into		# illegal
 foo:	jcxz foo	# No prefix exists to select CX as a counter
+	jmpl *%eax	# 32-bit data size not allowed
+        jmpl *(%rax)	# 32-bit data size not allowed
+        lcalll $0,$0	# illegal
+        lcallq $0,$0	# illegal
+        ldsl %eax,(%rax) # illegal
+        ldsq %rax,(%rax) # illegal
+        lesl %eax,(%rax) # illegal
+        lesq %rax,(%rax) # illegal
+        ljmpl $0,$0	# illegal
+        ljmpq $0,$0	# illegal
+        ljmpq *(%rax)	# 64-bit data size not allowed
+	loopw foo	# No prefix exists to select CX as a counter
+	loopew foo	# No prefix exists to select CX as a counter
+	loopnew foo	# No prefix exists to select CX as a counter
+	loopnzw foo	# No prefix exists to select CX as a counter
+	loopzw foo	# No prefix exists to select CX as a counter
+        leavel		# can't have 32-bit stack operands
+        pop %ds		# illegal
+        pop %es		# illegal
+        pop %ss		# illegal
+        popa		# illegal
         popl %eax	# can't have 32-bit stack operands
+        push %cs	# illegal
+        push %ds	# illegal
+        push %es	# illegal
+        push %ss	# illegal
+        pusha		# illegal
         pushl %eax	# can't have 32-bit stack operands
         pushfl		# can't have 32-bit stack operands
 	popfl		# can't have 32-bit stack operands
+	retl		# can't have 32-bit stack operands
diff --git a/gas/testsuite/gas/i386/x86-64-merom.d b/gas/testsuite/gas/i386/x86-64-merom.d
new file mode 100644
index 000000000000..f15a6e466abc
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-merom.d
@@ -0,0 +1,73 @@
+#objdump: -dw
+#name: x86-64 merom
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 38 01 01[ 	]+phaddw \(%rcx\),%mm0
+   4:	0f 38 01 c1[ 	]+phaddw %mm1,%mm0
+   8:	66 0f 38 01 01[ 	]+phaddw \(%rcx\),%xmm0
+   d:	66 0f 38 01 c1[ 	]+phaddw %xmm1,%xmm0
+  12:	0f 38 02 01[ 	]+phaddd \(%rcx\),%mm0
+  16:	0f 38 02 c1[ 	]+phaddd %mm1,%mm0
+  1a:	66 0f 38 02 01[ 	]+phaddd \(%rcx\),%xmm0
+  1f:	66 0f 38 02 c1[ 	]+phaddd %xmm1,%xmm0
+  24:	0f 38 03 01[ 	]+phaddsw \(%rcx\),%mm0
+  28:	0f 38 03 c1[ 	]+phaddsw %mm1,%mm0
+  2c:	66 0f 38 03 01[ 	]+phaddsw \(%rcx\),%xmm0
+  31:	66 0f 38 03 c1[ 	]+phaddsw %xmm1,%xmm0
+  36:	0f 38 05 01[ 	]+phsubw \(%rcx\),%mm0
+  3a:	0f 38 05 c1[ 	]+phsubw %mm1,%mm0
+  3e:	66 0f 38 05 01[ 	]+phsubw \(%rcx\),%xmm0
+  43:	66 0f 38 05 c1[ 	]+phsubw %xmm1,%xmm0
+  48:	0f 38 06 01[ 	]+phsubd \(%rcx\),%mm0
+  4c:	0f 38 06 c1[ 	]+phsubd %mm1,%mm0
+  50:	66 0f 38 06 01[ 	]+phsubd \(%rcx\),%xmm0
+  55:	66 0f 38 06 c1[ 	]+phsubd %xmm1,%xmm0
+  5a:	0f 38 07 01[ 	]+phsubsw \(%rcx\),%mm0
+  5e:	0f 38 07 c1[ 	]+phsubsw %mm1,%mm0
+  62:	66 0f 38 07 01[ 	]+phsubsw \(%rcx\),%xmm0
+  67:	66 0f 38 07 c1[ 	]+phsubsw %xmm1,%xmm0
+  6c:	0f 38 04 01[ 	]+pmaddubsw \(%rcx\),%mm0
+  70:	0f 38 04 c1[ 	]+pmaddubsw %mm1,%mm0
+  74:	66 0f 38 04 01[ 	]+pmaddubsw \(%rcx\),%xmm0
+  79:	66 0f 38 04 c1[ 	]+pmaddubsw %xmm1,%xmm0
+  7e:	0f 38 0b 01[ 	]+pmulhrsw \(%rcx\),%mm0
+  82:	0f 38 0b c1[ 	]+pmulhrsw %mm1,%mm0
+  86:	66 0f 38 0b 01[ 	]+pmulhrsw \(%rcx\),%xmm0
+  8b:	66 0f 38 0b c1[ 	]+pmulhrsw %xmm1,%xmm0
+  90:	0f 38 00 01[ 	]+pshufb \(%rcx\),%mm0
+  94:	0f 38 00 c1[ 	]+pshufb %mm1,%mm0
+  98:	66 0f 38 00 01[ 	]+pshufb \(%rcx\),%xmm0
+  9d:	66 0f 38 00 c1[ 	]+pshufb %xmm1,%xmm0
+  a2:	0f 38 08 01[ 	]+psignb \(%rcx\),%mm0
+  a6:	0f 38 08 c1[ 	]+psignb %mm1,%mm0
+  aa:	66 0f 38 08 01[ 	]+psignb \(%rcx\),%xmm0
+  af:	66 0f 38 08 c1[ 	]+psignb %xmm1,%xmm0
+  b4:	0f 38 09 01[ 	]+psignw \(%rcx\),%mm0
+  b8:	0f 38 09 c1[ 	]+psignw %mm1,%mm0
+  bc:	66 0f 38 09 01[ 	]+psignw \(%rcx\),%xmm0
+  c1:	66 0f 38 09 c1[ 	]+psignw %xmm1,%xmm0
+  c6:	0f 38 0a 01[ 	]+psignd \(%rcx\),%mm0
+  ca:	0f 38 0a c1[ 	]+psignd %mm1,%mm0
+  ce:	66 0f 38 0a 01[ 	]+psignd \(%rcx\),%xmm0
+  d3:	66 0f 38 0a c1[ 	]+psignd %xmm1,%xmm0
+  d8:	0f 3a 0f 01 02[ 	]+palignr \$0x2,\(%rcx\),%mm0
+  dd:	0f 3a 0f c1 02[ 	]+palignr \$0x2,%mm1,%mm0
+  e2:	66 0f 3a 0f 01 02[ 	]+palignr \$0x2,\(%rcx\),%xmm0
+  e8:	66 0f 3a 0f c1 02[ 	]+palignr \$0x2,%xmm1,%xmm0
+  ee:	0f 38 1c 01[ 	]+pabsb  \(%rcx\),%mm0
+  f2:	0f 38 1c c1[ 	]+pabsb  %mm1,%mm0
+  f6:	66 0f 38 1c 01[ 	]+pabsb  \(%rcx\),%xmm0
+  fb:	66 0f 38 1c c1[ 	]+pabsb  %xmm1,%xmm0
+ 100:	0f 38 1d 01[ 	]+pabsw  \(%rcx\),%mm0
+ 104:	0f 38 1d c1[ 	]+pabsw  %mm1,%mm0
+ 108:	66 0f 38 1d 01[ 	]+pabsw  \(%rcx\),%xmm0
+ 10d:	66 0f 38 1d c1[ 	]+pabsw  %xmm1,%xmm0
+ 112:	0f 38 1e 01[ 	]+pabsd  \(%rcx\),%mm0
+ 116:	0f 38 1e c1[ 	]+pabsd  %mm1,%mm0
+ 11a:	66 0f 38 1e 01[ 	]+pabsd  \(%rcx\),%xmm0
+ 11f:	66 0f 38 1e c1[ 	]+pabsd  %xmm1,%xmm0
+	...
diff --git a/gas/testsuite/gas/i386/x86-64-merom.s b/gas/testsuite/gas/i386/x86-64-merom.s
new file mode 100644
index 000000000000..a70654db3e13
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-merom.s
@@ -0,0 +1,70 @@
+#Merom New Instructions
+
+	.text
+foo:
+	phaddw		(%rcx),%mm0
+	phaddw		%mm1,%mm0
+	phaddw		(%rcx),%xmm0
+	phaddw		%xmm1,%xmm0
+	phaddd		(%rcx),%mm0
+	phaddd		%mm1,%mm0
+	phaddd		(%rcx),%xmm0
+	phaddd		%xmm1,%xmm0
+	phaddsw		(%rcx),%mm0
+	phaddsw		%mm1,%mm0
+	phaddsw		(%rcx),%xmm0
+	phaddsw		%xmm1,%xmm0
+	phsubw		(%rcx),%mm0
+	phsubw		%mm1,%mm0
+	phsubw		(%rcx),%xmm0
+	phsubw		%xmm1,%xmm0
+	phsubd		(%rcx),%mm0
+	phsubd		%mm1,%mm0
+	phsubd		(%rcx),%xmm0
+	phsubd		%xmm1,%xmm0
+	phsubsw		(%rcx),%mm0
+	phsubsw		%mm1,%mm0
+	phsubsw		(%rcx),%xmm0
+	phsubsw		%xmm1,%xmm0
+	pmaddubsw	(%rcx),%mm0
+	pmaddubsw	%mm1,%mm0
+	pmaddubsw	(%rcx),%xmm0
+	pmaddubsw	%xmm1,%xmm0
+	pmulhrsw	(%rcx),%mm0
+	pmulhrsw	%mm1,%mm0
+	pmulhrsw	(%rcx),%xmm0
+	pmulhrsw	%xmm1,%xmm0
+	pshufb		(%rcx),%mm0
+	pshufb		%mm1,%mm0
+	pshufb		(%rcx),%xmm0
+	pshufb		%xmm1,%xmm0
+	psignb		(%rcx),%mm0
+	psignb		%mm1,%mm0
+	psignb		(%rcx),%xmm0
+	psignb		%xmm1,%xmm0
+	psignw		(%rcx),%mm0
+	psignw		%mm1,%mm0
+	psignw		(%rcx),%xmm0
+	psignw		%xmm1,%xmm0
+	psignd		(%rcx),%mm0
+	psignd		%mm1,%mm0
+	psignd		(%rcx),%xmm0
+	psignd		%xmm1,%xmm0
+	palignr		$0x2,(%rcx),%mm0
+	palignr		$0x2,%mm1,%mm0
+	palignr		$0x2,(%rcx),%xmm0
+	palignr		$0x2,%xmm1,%xmm0
+	pabsb		(%rcx),%mm0
+	pabsb		%mm1,%mm0
+	pabsb		(%rcx),%xmm0
+	pabsb		%xmm1,%xmm0
+	pabsw		(%rcx),%mm0
+	pabsw		%mm1,%mm0
+	pabsw		(%rcx),%xmm0
+	pabsw		%xmm1,%xmm0
+	pabsd		(%rcx),%mm0
+	pabsd		%mm1,%mm0
+	pabsd		(%rcx),%xmm0
+	pabsd		%xmm1,%xmm0
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index 58155e2defee..13d58be1bdb8 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -7,269 +7,265 @@
 Disassembly of section .text:
 
 0+000 <.text>:
-[	 ]*0:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
-[	 ]*3:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
-[	 ]*5:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
-[	 ]*8:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
-[	 ]*a:[	 ]+cb[	 ]+lret[	 ]*(#.*)*
-[	 ]*b:[	 ]+c3[	 ]+retq[	 ]*(#.*)*
-[	 ]*c:[	 ]+cf[	 ]+iret[	 ]*(#.*)*
-[	 ]*d:[	 ]+66 cf[	 ]+iretw[	 ]*(#.*)*
-[	 ]*f:[	 ]+48 cf[	 ]+iretq[	 ]*(#.*)*
-[	 ]*11:[	 ]+66 41 8c 08[	 ]+movw[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
-[	 ]*15:[	 ]+66 8c 08[	 ]+movw[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
-[	 ]*18:[	 ]+66 41 8c 10[	 ]+movw[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
-[	 ]*1c:[	 ]+66 8c 10[	 ]+movw[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
-[	 ]*1f:[	 ]+66 41 8c 20[	 ]+movw[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
-[	 ]*23:[	 ]+66 8c 20[	 ]+movw[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
-[	 ]*26:[	 ]+41 8c 08[	 ]+movl[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
-[	 ]*29:[	 ]+8c 08[	 ]+movl[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
-[	 ]*2b:[	 ]+41 8c 10[	 ]+movl[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
-[	 ]*2e:[	 ]+8c 10[	 ]+movl[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
-[	 ]*30:[	 ]+41 8c 20[	 ]+movl[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
-[	 ]*33:[	 ]+8c 20[	 ]+movl[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
-[	 ]*35:[	 ]+41 8e 10[	 ]+movl[	 ]+\(%r8\),%ss[	 ]*(#.*)*
-[	 ]*38:[	 ]+8e 10[	 ]+movl[	 ]+\(%rax\),%ss[	 ]*(#.*)*
-[	 ]*3a:[	 ]+41 8e 20[	 ]+movl[	 ]+\(%r8\),%fs[	 ]*(#.*)*
-[	 ]*3d:[	 ]+8e 20[	 ]+movl[	 ]+\(%rax\),%fs[	 ]*(#.*)*
-[	 ]*3f:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*43:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*46:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*4c:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*51:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*58:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*5e:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*62:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*65:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*6b:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*70:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*76:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
-[	 ]*7a:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
-[	 ]*7d:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
-[	 ]*83:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
-[	 ]*88:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*8f:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*95:[	 ]+49 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
-[	 ]*9c:[	 ]+48 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
-[	 ]*a3:[	 ]+41 0f c3 00[	 ]+movnti[	 ]+%eax,\(%r8\)[	 ]*(#.*)*
-[	 ]*a7:[	 ]+0f c3 00[	 ]+movnti[	 ]+%eax,\(%rax\)[	 ]*(#.*)*
-[	 ]*aa:[	 ]+49 0f c3 00[	 ]+movnti[	 ]+%rax,\(%r8\)[	 ]*(#.*)*
-[	 ]*ae:[	 ]+48 0f c3 00[	 ]+movnti[	 ]+%rax,\(%rax\)[	 ]*(#.*)*
-[	 ]*b2:[	 ]+4d 0f c3 00[	 ]+movnti[	 ]+%r8,\(%r8\)[	 ]*(#.*)*
-[	 ]*b6:[	 ]+4c 0f c3 00[	 ]+movnti[	 ]+%r8,\(%rax\)[	 ]*(#.*)*
-[	 ]*ba:[	 ]+41 f6 38[	 ]+idivb[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*bd:[	 ]+f6 38[	 ]+idivb[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*bf:[	 ]+66 41 f7 38[	 ]+idivw[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*c3:[	 ]+66 f7 38[	 ]+idivw[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*c6:[	 ]+41 f7 38[	 ]+idivl[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*c9:[	 ]+f7 38[	 ]+idivl[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*cb:[	 ]+49 f7 38[	 ]+idivq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*ce:[	 ]+48 f7 38[	 ]+idivq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*d1:[	 ]+41 f6 28[	 ]+imulb[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*d4:[	 ]+f6 28[	 ]+imulb[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*d6:[	 ]+66 41 f7 28[	 ]+imulw[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*da:[	 ]+66 f7 28[	 ]+imulw[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*dd:[	 ]+41 f7 28[	 ]+imull[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*e0:[	 ]+f7 28[	 ]+imull[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*e2:[	 ]+49 f7 28[	 ]+imulq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*e5:[	 ]+48 f7 28[	 ]+imulq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*e8:[	 ]+66 41 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*ed:[	 ]+66 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*f1:[	 ]+66 45 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*f6:[	 ]+66 44 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*fb:[	 ]+66 45 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*100:[	 ]+66 44 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*105:[	 ]+66 41 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*10a:[	 ]+66 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*10e:[	 ]+66 0f 58 c0[	 ]+addpd[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
-[	 ]*112:[	 ]+66 45 0f 58 ff[	 ]+addpd[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
-[	 ]*117:[	 ]+66 45 0f 58 c7[	 ]+addpd[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
-[	 ]*11c:[	 ]+f2 49 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*121:[	 ]+f2 48 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*126:[	 ]+f2 4d 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*12b:[	 ]+f2 4c 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*130:[	 ]+f2 48 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*135:[	 ]+f2 4d 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*13a:[	 ]+f2 49 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*13f:[	 ]+f2 4d 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*144:[	 ]+f2 49 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*149:[	 ]+f2 4c 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*14e:[	 ]+f2 48 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*153:[	 ]+f2 4c 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*158:[	 ]+f2 49 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*15d:[	 ]+f2 48 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*162:[	 ]+f2 4d 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*167:[	 ]+f2 4c 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*16c:[	 ]+f2 48 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*171:[	 ]+f2 4d 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*176:[	 ]+f2 49 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*17b:[	 ]+f2 4d 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*180:[	 ]+f2 49 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*185:[	 ]+f2 4c 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*18a:[	 ]+f2 48 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*18f:[	 ]+f2 4c 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*194:[	 ]+f3 49 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*199:[	 ]+f3 48 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*19e:[	 ]+f3 4d 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*1a3:[	 ]+f3 4c 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*1a8:[	 ]+f3 48 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*1ad:[	 ]+f3 4d 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*1b2:[	 ]+f3 49 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*1b7:[	 ]+f3 4d 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*1bc:[	 ]+f3 49 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*1c1:[	 ]+f3 4c 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*1c6:[	 ]+f3 48 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*1cb:[	 ]+f3 4c 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*1d0:[	 ]+f3 49 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
-[	 ]*1d5:[	 ]+f3 48 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
-[	 ]*1da:[	 ]+f3 4d 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
-[	 ]*1df:[	 ]+f3 4c 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
-[	 ]*1e4:[	 ]+f3 48 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*1e9:[	 ]+f3 4d 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
-[	 ]*1ee:[	 ]+f3 49 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
-[	 ]*1f3:[	 ]+f3 4d 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
-[	 ]*1f8:[	 ]+f3 49 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
-[	 ]*1fd:[	 ]+f3 4c 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*202:[	 ]+f3 48 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
-[	 ]*207:[	 ]+f3 4c 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*20c:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*211:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*215:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*21a:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*21f:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*224:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*229:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*22e:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*232:[	 ]+f3 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*236:[	 ]+f3 44 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*23b:[	 ]+f3 44 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*240:[	 ]+f3 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*244:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*249:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*24d:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*252:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*257:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*25c:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*261:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*266:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*26a:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*26f:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*273:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*278:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*27d:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*282:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*287:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*28c:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*290:[	 ]+f2 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*294:[	 ]+f2 44 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*299:[	 ]+f2 44 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*29e:[	 ]+f2 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*2a2:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*2a7:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*2ab:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*2b0:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*2b5:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*2ba:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*2bf:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*2c4:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*2c8:[	 ]+66 41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*2cd:[	 ]+66 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*2d1:[	 ]+66 45 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*2d6:[	 ]+66 44 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*2db:[	 ]+66 45 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*2e0:[	 ]+66 44 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*2e5:[	 ]+66 41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*2ea:[	 ]+66 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*2ee:[	 ]+66 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm0[	 ]*(#.*)*
-[	 ]*2f2:[	 ]+66 44 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm15[	 ]*(#.*)*
-[	 ]*2f7:[	 ]+66 44 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm8[	 ]*(#.*)*
-[	 ]*2fc:[	 ]+66 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm7[	 ]*(#.*)*
-[	 ]*300:[	 ]+66 41 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*305:[	 ]+66 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*309:[	 ]+66 45 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
-[	 ]*30e:[	 ]+66 44 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
-[	 ]*313:[	 ]+66 45 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
-[	 ]*318:[	 ]+66 44 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
-[	 ]*31d:[	 ]+66 41 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*322:[	 ]+66 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*326:[	 ]+66 0f 7e c0[	 ]+movd[	 ]+%xmm0,%eax[	 ]*(#.*)*
-[	 ]*32a:[	 ]+66 44 0f 7e f8[	 ]+movd[	 ]+%xmm15,%eax[	 ]*(#.*)*
-[	 ]*32f:[	 ]+66 44 0f 7e c0[	 ]+movd[	 ]+%xmm8,%eax[	 ]*(#.*)*
-[	 ]*334:[	 ]+66 0f 7e f8[	 ]+movd[	 ]+%xmm7,%eax[	 ]*(#.*)*
-[	 ]*338:[	 ]+66 48 0f 6e c0[	 ]+movd[	 ]+%rax,%xmm0[	 ]*(#.*)*
-[	 ]*33d:[	 ]+66 49 0f 6e c0[	 ]+movd[	 ]+%r8,%xmm0[	 ]*(#.*)*
-[	 ]*342:[	 ]+66 4d 0f 6e f8[	 ]+movd[	 ]+%r8,%xmm15[	 ]*(#.*)*
-[	 ]*347:[	 ]+66 48 0f 7e c0[	 ]+movd[	 ]+%xmm0,%rax[	 ]*(#.*)*
-[	 ]*34c:[	 ]+66 49 0f 7e c0[	 ]+movd[	 ]+%xmm0,%r8[	 ]*(#.*)*
-[	 ]*351:[	 ]+66 49 0f 7e f8[	 ]+movd[	 ]+%xmm7,%r8[	 ]*(#.*)*
-[	 ]*356:[	 ]+f3 41 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
-[	 ]*35b:[	 ]+f3 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
-[	 ]*35f:[	 ]+f3 45 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
-[	 ]*364:[	 ]+f3 44 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
-[	 ]*369:[	 ]+f3 45 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
-[	 ]*36e:[	 ]+f3 44 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
-[	 ]*373:[	 ]+f3 41 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
-[	 ]*378:[	 ]+f3 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
-[	 ]*37c:[	 ]+f3 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
-[	 ]*380:[	 ]+f3 45 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
-[	 ]*385:[	 ]+f3 45 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
-[	 ]*38a:[	 ]+f3 41 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm7[	 ]*(#.*)*
-[	 ]*38f:[	 ]+f3 41 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm0[	 ]*(#.*)*
-[	 ]*394:[	 ]+f3 45 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm15[	 ]*(#.*)*
-[	 ]*399:[	 ]+f3 45 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm8[	 ]*(#.*)*
-[	 ]*39e:[	 ]+f3 41 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm7[	 ]*(#.*)*
-[	 ]*3a3:[	 ]+f3 41 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm0[	 ]*(#.*)*
-[	 ]*3a8:[	 ]+f3 44 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm15[	 ]*(#.*)*
-[	 ]*3ad:[	 ]+f3 44 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm8[	 ]*(#.*)*
-[	 ]*3b2:[	 ]+f3 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm7[	 ]*(#.*)*
-[	 ]*3b6:[	 ]+f3 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm0[	 ]*(#.*)*
-[	 ]*3ba:[	 ]+f3 44 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm15[	 ]*(#.*)*
-[	 ]*3bf:[	 ]+f3 44 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm8[	 ]*(#.*)*
-[	 ]*3c4:[	 ]+f3 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm7[	 ]*(#.*)*
-[	 ]*3c8:[	 ]+66 41 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*3cd:[	 ]+66 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*3d1:[	 ]+66 45 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
-[	 ]*3d6:[	 ]+66 44 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
-[	 ]*3db:[	 ]+66 45 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
-[	 ]*3e0:[	 ]+66 44 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
-[	 ]*3e5:[	 ]+66 41 0f d6 38[	 ]+movq[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*3ea:[	 ]+41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
-[	 ]*3ee:[	 ]+0f 6e 00[	 ]+movd[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
-[	 ]*3f1:[	 ]+41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
-[	 ]*3f5:[	 ]+0f 6e 38[	 ]+movd[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
-[	 ]*3f8:[	 ]+0f 6e c0[	 ]+movd[	 ]+%eax,%mm0[	 ]*(#.*)*
-[	 ]*3fb:[	 ]+0f 6e f8[	 ]+movd[	 ]+%eax,%mm7[	 ]*(#.*)*
-[	 ]*3fe:[	 ]+41 0f 7e 00[	 ]+movd[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*402:[	 ]+0f 7e 00[	 ]+movd[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*405:[	 ]+41 0f 7e 38[	 ]+movd[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*409:[	 ]+0f 7e 38[	 ]+movd[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*40c:[	 ]+0f 7e c0[	 ]+movd[	 ]+%mm0,%eax[	 ]*(#.*)*
-[	 ]*40f:[	 ]+0f 7e f8[	 ]+movd[	 ]+%mm7,%eax[	 ]*(#.*)*
-[	 ]*412:[	 ]+41 0f 6f 00[	 ]+movq[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
-[	 ]*416:[	 ]+0f 6f 00[	 ]+movq[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
-[	 ]*419:[	 ]+41 0f 6f 38[	 ]+movq[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
-[	 ]*41d:[	 ]+0f 6f 38[	 ]+movq[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
-[	 ]*420:[	 ]+41 0f 7f 00[	 ]+movq[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
-[	 ]*424:[	 ]+0f 7f 00[	 ]+movq[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
-[	 ]*427:[	 ]+41 0f 7f 38[	 ]+movq[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
-[	 ]*42b:[	 ]+0f 7f 38[	 ]+movq[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
-[	 ]*42e:[	 ]+41 8f 00[	 ]+popq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*431:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*433:[	 ]+9d[	 ]+popfq[	 ]*(#.*)*
-[	 ]*434:[	 ]+41 ff 30[	 ]+pushq[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*437:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*439:[	 ]+9c[	 ]+pushfq[	 ]*(#.*)*
-[	 ]*43a:[	 ]+0f 77[	 ]+emms[	 ]*(#.*)*
-[	 ]*43c:[	 ]+0f 0e[	 ]+femms[	 ]*(#.*)*
-[	 ]*43e:[	 ]+0f 08[	 ]+invd[	 ]*(#.*)*
-[	 ]*440:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*444:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*447:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*44b:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*44e:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
-[	 ]*452:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
-[	 ]*455:[	 ]+0f 00 c0[	 ]+sldt[	 ]+%eax[	 ]*(#.*)*
-[	 ]*458:[	 ]+e6 00[	 ]+out[	 ]+%al,\$0[x0]*[	 ]*(#.*)*
-[	 ]*45a:[	 ]+66 e7 00[	 ]+out[	 ]+%ax,\$0[x0]*[	 ]*(#.*)*
-[	 ]*45d:[	 ]+e7 00[	 ]+out[	 ]+%eax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 10[	 ]+callq[	 ]+\*\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+cb[	 ]+lret[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c3[	 ]+retq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+cf[	 ]+iret[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 cf[	 ]+iretw[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 cf[	 ]+iretq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 08[	 ]+movw?[	 ]+%cs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 08[	 ]+movw?[	 ]+%cs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 10[	 ]+movw?[	 ]+%ss,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 10[	 ]+movw?[	 ]+%ss,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8c 20[	 ]+movw?[	 ]+%fs,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8c 20[	 ]+movw?[	 ]+%fs,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8e 10[	 ]+movw?[	 ]+\(%r8\),%ss[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8e 10[	 ]+movw?[	 ]+\(%rax\),%ss[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8e 20[	 ]+movw?[	 ]+\(%r8\),%fs[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8e 20[	 ]+movw?[	 ]+\(%rax\),%fs[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c6 00 00[	 ]+movb[	 ]+\$0[x0]*,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 c7 00 00 70[	 ]+movw[	 ]+\$0x7000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+c7 00 00 00 00 70[	 ]+movl[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 c7 00 00 00 00 70[	 ]+movq[	 ]+\$0x70000000,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f c3 00[	 ]+movnti[	 ]+%eax,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f c3 00[	 ]+movnti[	 ]+%eax,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 0f c3 00[	 ]+movnti[	 ]+%rax,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 0f c3 00[	 ]+movnti[	 ]+%rax,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+4d 0f c3 00[	 ]+movnti[	 ]+%r8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+4c 0f c3 00[	 ]+movnti[	 ]+%r8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f6 38[	 ]+idivb[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f6 38[	 ]+idivb[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 f7 38[	 ]+idivw[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 f7 38[	 ]+idivw[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f7 38[	 ]+idivl[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f7 38[	 ]+idivl[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 f7 38[	 ]+idivq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 f7 38[	 ]+idivq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f6 28[	 ]+imulb[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f6 28[	 ]+imulb[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 f7 28[	 ]+imulw[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 f7 28[	 ]+imulw[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 f7 28[	 ]+imull[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f7 28[	 ]+imull[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+49 f7 28[	 ]+imulq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+48 f7 28[	 ]+imulq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 00[	 ]+addpd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 58 00[	 ]+addpd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 58 38[	 ]+addpd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 38[	 ]+addpd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 58 c0[	 ]+addpd[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 ff[	 ]+addpd[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 58 c7[	 ]+addpd[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d 00[	 ]+cvtsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2d c7[	 ]+cvtsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2d c0[	 ]+cvtsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c 00[	 ]+cvttsd2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4d 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 49 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 48 0f 2c c7[	 ]+cvttsd2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 4c 0f 2c c0[	 ]+cvttsd2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d 00[	 ]+cvtss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2d c7[	 ]+cvtss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2d c0[	 ]+cvtss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%r8\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c 00[	 ]+cvttss2siq[	 ]+\(%rax\),%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm15,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4d 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 49 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm8,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 48 0f 2c c7[	 ]+cvttss2siq[	 ]+%xmm7,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 4c 0f 2c c0[	 ]+cvttss2siq[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a c0[	 ]+cvtsi2ss[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a f8[	 ]+cvtsi2ss[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 2a 00[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 2a 38[	 ]+cvtsi2ss[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a c0[	 ]+cvtsi2sd[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a f8[	 ]+cvtsi2sd[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 45 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 44 0f 2a 00[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 41 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f2 0f 2a 38[	 ]+cvtsi2sd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e 00[	 ]+movd[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e 38[	 ]+movd[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 6e c0[	 ]+movd[	 ]+%eax,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 6e f8[	 ]+movd[	 ]+%eax,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e 00[	 ]+movd[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e 38[	 ]+movd[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e 00[	 ]+movd[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e 38[	 ]+movd[	 ]+%xmm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e c0[	 ]+movd[	 ]+%xmm0,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e f8[	 ]+movd[	 ]+%xmm15,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f 7e c0[	 ]+movd[	 ]+%xmm8,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f 7e f8[	 ]+movd[	 ]+%xmm7,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 48 0f 6e c0[	 ]+movd[	 ]+%rax,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 6e c0[	 ]+movd[	 ]+%r8,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 4d 0f 6e f8[	 ]+movd[	 ]+%r8,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 48 0f 7e c0[	 ]+movd[	 ]+%xmm0,%rax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 7e c0[	 ]+movd[	 ]+%xmm0,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 49 0f 7e f8[	 ]+movd[	 ]+%xmm7,%r8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e 00[	 ]+movq[	 ]+\(%r8\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e 00[	 ]+movq[	 ]+\(%rax\),%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e 38[	 ]+movq[	 ]+\(%r8\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e 38[	 ]+movq[	 ]+\(%rax\),%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e ff[	 ]+movq[	 ]+%xmm15,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e c7[	 ]+movq[	 ]+%xmm15,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 45 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e f8[	 ]+movq[	 ]+%xmm8,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 41 0f 7e c0[	 ]+movq[	 ]+%xmm8,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e ff[	 ]+movq[	 ]+%xmm7,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e c7[	 ]+movq[	 ]+%xmm7,%xmm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm15[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 44 0f 7e c0[	 ]+movq[	 ]+%xmm0,%xmm8[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+f3 0f 7e f8[	 ]+movq[	 ]+%xmm0,%xmm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 0f d6 00[	 ]+movq[	 ]+%xmm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f d6 38[	 ]+movq[	 ]+%xmm15,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 45 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 44 0f d6 00[	 ]+movq[	 ]+%xmm8,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 41 0f d6 38[	 ]+movq[	 ]+%xmm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6e 00[	 ]+movd[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e 00[	 ]+movd[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6e 38[	 ]+movd[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e 38[	 ]+movd[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e c0[	 ]+movd[	 ]+%eax,%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6e f8[	 ]+movd[	 ]+%eax,%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7e 00[	 ]+movd[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e 00[	 ]+movd[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7e 38[	 ]+movd[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e 38[	 ]+movd[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e c0[	 ]+movd[	 ]+%mm0,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7e f8[	 ]+movd[	 ]+%mm7,%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6f 00[	 ]+movq[	 ]+\(%r8\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6f 00[	 ]+movq[	 ]+\(%rax\),%mm0[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 6f 38[	 ]+movq[	 ]+\(%r8\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 6f 38[	 ]+movq[	 ]+\(%rax\),%mm7[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7f 00[	 ]+movq[	 ]+%mm0,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7f 00[	 ]+movq[	 ]+%mm0,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 7f 38[	 ]+movq[	 ]+%mm7,\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 7f 38[	 ]+movq[	 ]+%mm7,\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 8f 00[	 ]+popq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+9d[	 ]+popfq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 ff 30[	 ]+pushq[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+9c[	 ]+pushfq[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 77[	 ]+emms[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 0e[	 ]+femms[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 08[	 ]+invd[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+41 0f 01 38[	 ]+invlpg[	 ]+\(%r8\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 01 38[	 ]+invlpg[	 ]+\(%rax\)[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+0f 00 c0[	 ]+sldt[	 ]+%eax[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+e6 00[	 ]+out[	 ]+%al,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+66 e7 00[	 ]+out[	 ]+%ax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+e7 00[	 ]+out[	 ]+%eax,\$0[x0]*[	 ]*(#.*)*
+[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
+[	 ]*[0-9a-f]+:[	 ]+00 00[	 ]+.*
 [	 *]...
diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index 839a2c3b6327..8b132b390468 100644
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -20,22 +20,16 @@
 	# CMP
 
 	# MOV
-	MOVw %cs,(%r8)		      # 66  --  -- 41   8C 08				 ; REX to access upper reg. O16 for 16-bit operand size
-	MOVw %cs,(%rax)		      # 66  --  -- --   8C 08				 ; O16 for 16-bit operand size
-	MOVw %ss,(%r8)		      # 66  --  -- 41   8C 10				 ; REX to access upper reg. O16 for 16-bit operand size
-	MOVw %ss,(%rax)		      # 66  --  -- --   8C 10				 ; O16 for 16-bit operand size
-	MOVw %fs,(%r8)		      # 66  --  -- 41   8C 20				 ; REX to access upper reg. O16 for 16-bit operand size
-	MOVw %fs,(%rax)		      # 66  --  -- --   8C 20				 ; O16 for 16-bit operand size
-	MOVl %cs,(%r8)		      # --  --  -- 41   8C 08				 ; REX to access upper reg.
-	MOVl %cs,(%rax)		      # --  --  -- --   8C 08
-	MOVl %ss,(%r8)		      # --  --  -- 41   8C 10				 ; REX to access upper reg.
-	MOVl %ss,(%rax)		      # --  --  -- --   8C 10
-	MOVl %fs,(%r8)		      # --  --  -- 41   8C 20				 ; REX to access upper reg.
-	MOVl %fs,(%rax)		      # --  --  -- --   8C 20
-	MOVl (%r8),%ss		      # --  --  -- 41   8E 10				 ; REX to access upper reg.
-	MOVl (%rax),%ss		      # --  --  -- --   8E 10
-	MOVl (%r8),%fs		      # --  --  -- 41   8E 20				 ; REX to access upper reg.
-	MOVl (%rax),%fs		      # --  --  -- --   8E 20
+	MOVw %cs,(%r8)		      # --  --  -- 41   8C 08				 ; REX to access upper reg.
+	MOVw %cs,(%rax)		      # --  --  -- --   8C 08
+	MOVw %ss,(%r8)		      # --  --  -- 41   8C 10				 ; REX to access upper reg.
+	MOVw %ss,(%rax)		      # --  --  -- --   8C 10
+	MOVw %fs,(%r8)		      # --  --  -- 41   8C 20				 ; REX to access upper reg.
+	MOVw %fs,(%rax)		      # --  --  -- --   8C 20
+	MOVw (%r8),%ss		      # --  --  -- 41   8E 10				 ; REX to access upper reg.
+	MOVw (%rax),%ss		      # --  --  -- --   8E 10
+	MOVw (%r8),%fs		      # --  --  -- 41   8E 20				 ; REX to access upper reg.
+	MOVw (%rax),%fs		      # --  --  -- --   8E 20
 	MOVb $0,(%r8)		      # --  --  -- 41   C6 00 00			 ; REX to access upper reg.
 	MOVb $0,(%rax)		      # --  --  -- --   C6 00 00
 	MOVw $0x7000,(%r8)	      # 66  --  -- 41   C7 00 00 70			 ; REX to access upper reg. O16 for 16-bit operand size
diff --git a/gas/testsuite/gas/i386/x86-64-pcrel.d b/gas/testsuite/gas/i386/x86-64-pcrel.d
new file mode 100644
index 000000000000..3be86c7c3405
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-pcrel.d
@@ -0,0 +1,19 @@
+#objdump: -drw
+#name: x86-64 pcrel
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+000 <_start>:
+[	 ]*[0-9a-f]+:[	 ]+b0 00[	 ]+movb?[	 ]+\$(0x)?0,%al[	 ]*[0-9a-f]+:[	 ]+R_X86_64_PC8[	 ]+xtrn\+(0x)?1
+[	 ]*[0-9a-f]+:[	 ]+66 b8 00 00[	 ]+movw?[	 ]+\$(0x)?0,%ax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_PC16[	 ]+xtrn\+(0x)?2
+[	 ]*[0-9a-f]+:[	 ]+b8( 00){4}[	 ]+movl?[	 ]+\$(0x)?0,%eax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_PC32[	 ]+xtrn\+(0x)?1
+[	 ]*[0-9a-f]+:[	 ]+48 c7 c0( 00){4}[	 ]+movq?[	 ]+\$(0x)?0,%rax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_PC32[	 ]+xtrn\+(0x)?3
+[	 ]*[0-9a-f]+:[	 ]+48 b8( 00){8}[	 ]+mov(abs)?q?[	 ]+\$(0x)?0,%rax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_PC64[	 ]+xtrn\+(0x)?2
+[	 ]*[0-9a-f]+:[	 ]+b0 00[	 ]+movb?[	 ]+\$(0x)?0,%al[	 ]*[0-9a-f]+:[	 ]+R_X86_64_8[	 ]+xtrn
+[	 ]*[0-9a-f]+:[	 ]+66 b8 00 00[	 ]+movw?[	 ]+\$(0x)?0,%ax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_16[	 ]+xtrn
+[	 ]*[0-9a-f]+:[	 ]+b8( 00){4}[	 ]+movl?[	 ]+\$(0x)?0,%eax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_32[	 ]+xtrn
+[	 ]*[0-9a-f]+:[	 ]+48 c7 c0( 00){4}[	 ]+movq?[	 ]+\$(0x)?0,%rax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_32S[	 ]+xtrn
+[	 ]*[0-9a-f]+:[	 ]+48 b8( 00){8}[	 ]+mov(abs)?q?[	 ]+\$(0x)?0,%rax[	 ]*[0-9a-f]+:[	 ]+R_X86_64_64[	 ]+xtrn
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-pcrel.s b/gas/testsuite/gas/i386/x86-64-pcrel.s
new file mode 100644
index 000000000000..d4dcd9e1ba2e
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-pcrel.s
@@ -0,0 +1,15 @@
+	.text
+_start:
+	movb	$(xtrn - .), %al
+	movw	$(xtrn - .), %ax
+	movl	$(xtrn - .), %eax
+	movq	$(xtrn - .), %rax
+	movabsq	$(xtrn - .), %rax
+
+	movb	$xtrn, %al
+	movw	$xtrn, %ax
+	movl	$xtrn, %eax
+	movq	$xtrn, %rax
+	movabsq	$xtrn, %rax
+
+	.p2align 4,0
diff --git a/gas/testsuite/gas/i386/x86-64-prescott.d b/gas/testsuite/gas/i386/x86-64-prescott.d
new file mode 100644
index 000000000000..43a2d2802027
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prescott.d
@@ -0,0 +1,37 @@
+#objdump: -dw
+#name: x86-64 prescott
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	66 0f d0 01 [ 	]*addsubpd \(%rcx\),%xmm0
+   4:	66 0f d0 ca [ 	]*addsubpd %xmm2,%xmm1
+   8:	f2 0f d0 13 [ 	]*addsubps \(%rbx\),%xmm2
+   c:	f2 0f d0 dc [ 	]*addsubps %xmm4,%xmm3
+  10:	df 88 90 90 90 90 [ 	]*fisttp 0xffffffff90909090\(%rax\)
+  16:	db 88 90 90 90 90 [ 	]*fisttpl 0xffffffff90909090\(%rax\)
+  1c:	dd 88 90 90 90 90 [ 	]*fisttpll 0xffffffff90909090\(%rax\)
+  22:	66 0f 7c 65 00 [ 	]*haddpd 0x0\(%rbp\),%xmm4
+  27:	66 0f 7c ee [ 	]*haddpd %xmm6,%xmm5
+  2b:	f2 0f 7c 37 [ 	]*haddps \(%rdi\),%xmm6
+  2f:	f2 0f 7c f8 [ 	]*haddps %xmm0,%xmm7
+  33:	66 0f 7d c1 [ 	]*hsubpd %xmm1,%xmm0
+  37:	66 0f 7d 0a [ 	]*hsubpd \(%rdx\),%xmm1
+  3b:	f2 0f 7d d2 [ 	]*hsubps %xmm2,%xmm2
+  3f:	f2 0f 7d 1c 24 [ 	]*hsubps \(%rsp\),%xmm3
+  44:	f2 0f f0 2e [ 	]*lddqu  \(%rsi\),%xmm5
+  48:	0f 01 c8 [ 	]*monitor %rax,%rcx,%rdx
+  4b:	0f 01 c8 [ 	]*monitor %rax,%rcx,%rdx
+  4e:	f2 0f 12 f7 [ 	]*movddup %xmm7,%xmm6
+  52:	f2 0f 12 38 [ 	]*movddup \(%rax\),%xmm7
+  56:	f3 0f 16 01 [ 	]*movshdup \(%rcx\),%xmm0
+  5a:	f3 0f 16 ca [ 	]*movshdup %xmm2,%xmm1
+  5e:	f3 0f 12 13 [ 	]*movsldup \(%rbx\),%xmm2
+  62:	f3 0f 12 dc [ 	]*movsldup %xmm4,%xmm3
+  66:	0f 01 c9 [ 	]*mwait  %rax,%rcx
+  69:	0f 01 c9 [ 	]*mwait  %rax,%rcx
+  6c:	67 0f 01 c8 [ 	]*monitor %eax,%rcx,%rdx
+  70:	67 0f 01 c8 [ 	]*monitor %eax,%rcx,%rdx
+	...
diff --git a/gas/testsuite/gas/i386/x86-64-prescott.s b/gas/testsuite/gas/i386/x86-64-prescott.s
new file mode 100644
index 000000000000..0f03683c2ab8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prescott.s
@@ -0,0 +1,35 @@
+#Prescott New Instructions
+
+	.text
+foo:
+	addsubpd	(%rcx),%xmm0
+	addsubpd	%xmm2,%xmm1
+	addsubps	(%rbx),%xmm2
+	addsubps	%xmm4,%xmm3
+	fisttp		0x90909090(%rax)
+	fisttpl		0x90909090(%rax)
+	fisttpll	0x90909090(%rax)
+	haddpd		0x0(%rbp),%xmm4
+	haddpd		%xmm6,%xmm5
+	haddps		(%rdi),%xmm6
+	haddps		%xmm0,%xmm7
+	hsubpd		%xmm1,%xmm0
+	hsubpd		(%rdx),%xmm1
+	hsubps		%xmm2,%xmm2
+	hsubps		(%rsp,1),%xmm3
+	lddqu		(%rsi),%xmm5
+	monitor
+	monitor		%rax,%rcx,%rdx
+	movddup		%xmm7,%xmm6
+	movddup		(%rax),%xmm7
+	movshdup	(%rcx),%xmm0
+	movshdup	%xmm2,%xmm1
+	movsldup	(%rbx),%xmm2
+	movsldup	%xmm4,%xmm3
+	mwait
+	mwait		%rax,%rcx
+
+	monitor		%eax,%rcx,%rdx
+	addr32 monitor
+
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-rep-suffix.d b/gas/testsuite/gas/i386/x86-64-rep-suffix.d
new file mode 100644
index 000000000000..a85b4a941779
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rep-suffix.d
@@ -0,0 +1,17 @@
+#objdump: -dwMsuffix
+#name: x86-64 rep prefix (with suffixes)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <_start>:
+   0:	f3 ac[ 	]+rep lodsb %ds:\(%rsi\),%al
+   2:	f3 aa[ 	]+rep stosb %al,%es:\(%rdi\)
+   4:	f3 66 ad[ 	]+rep lodsw %ds:\(%rsi\),%ax
+   7:	f3 66 ab[ 	]+rep stosw %ax,%es:\(%rdi\)
+   a:	f3 ad[ 	]+rep lodsl %ds:\(%rsi\),%eax
+   c:	f3 ab[ 	]+rep stosl %eax,%es:\(%rdi\)
+   e:	f3 48 ad[ 	]+rep lodsq %ds:\(%rsi\),%rax
+  11:	f3 48 ab[ 	]+rep stosq %rax,%es:\(%rdi\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rep-suffix.s b/gas/testsuite/gas/i386/x86-64-rep-suffix.s
new file mode 100644
index 000000000000..de748cf774e6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rep-suffix.s
@@ -0,0 +1,11 @@
+# Disassembling with -Msuffix.
+	.text
+_start:
+	rep lodsb
+	rep stosb
+	rep lodsw
+	rep stosw
+	rep lodsl
+	rep stosl
+	rep lodsq
+	rep stosq
diff --git a/gas/testsuite/gas/i386/x86-64-rep.d b/gas/testsuite/gas/i386/x86-64-rep.d
new file mode 100644
index 000000000000..631b7113d8e7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rep.d
@@ -0,0 +1,61 @@
+#objdump: -dw
+#name: x86-64 rep prefix
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <_start>:
+   0:	f3 6c[ 	]+rep insb \(%dx\),%es:\(%rdi\)
+   2:	f3 6e[ 	]+rep outsb %ds:\(%rsi\),\(%dx\)
+   4:	f3 a4[ 	]+rep movsb %ds:\(%rsi\),%es:\(%rdi\)
+   6:	f3 ac[ 	]+rep lods %ds:\(%rsi\),%al
+   8:	f3 aa[ 	]+rep stos %al,%es:\(%rdi\)
+   a:	f3 a6[ 	]+repz cmpsb %es:\(%rdi\),%ds:\(%rsi\)
+   c:	f3 ae[ 	]+repz scas %es:\(%rdi\),%al
+   e:	f3 66 6d[ 	]+rep insw \(%dx\),%es:\(%rdi\)
+  11:	f3 66 6f[ 	]+rep outsw %ds:\(%rsi\),\(%dx\)
+  14:	f3 66 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+  17:	f3 66 ad[ 	]+rep lods %ds:\(%rsi\),%ax
+  1a:	f3 66 ab[ 	]+rep stos %ax,%es:\(%rdi\)
+  1d:	f3 66 a7[ 	]+repz cmpsw %es:\(%rdi\),%ds:\(%rsi\)
+  20:	f3 66 af[ 	]+repz scas %es:\(%rdi\),%ax
+  23:	f3 6d[ 	]+rep insl \(%dx\),%es:\(%rdi\)
+  25:	f3 6f[ 	]+rep outsl %ds:\(%rsi\),\(%dx\)
+  27:	f3 a5[ 	]+rep movsl %ds:\(%rsi\),%es:\(%rdi\)
+  29:	f3 ad[ 	]+rep lods %ds:\(%rsi\),%eax
+  2b:	f3 ab[ 	]+rep stos %eax,%es:\(%rdi\)
+  2d:	f3 a7[ 	]+repz cmpsl %es:\(%rdi\),%ds:\(%rsi\)
+  2f:	f3 af[ 	]+repz scas %es:\(%rdi\),%eax
+  31:	f3 48 a5[ 	]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+  34:	f3 48 ad[ 	]+rep lods %ds:\(%rsi\),%rax
+  37:	f3 48 ab[ 	]+rep stos %rax,%es:\(%rdi\)
+  3a:	f3 48 a7[ 	]+repz cmpsq %es:\(%rdi\),%ds:\(%rsi\)
+  3d:	f3 48 af[ 	]+repz scas %es:\(%rdi\),%rax
+  40:	f3 67 6c[ 	]+rep addr32 insb \(%dx\),%es:\(%edi\)
+  43:	f3 67 6e[ 	]+rep addr32 outsb %ds:\(%esi\),\(%dx\)
+  46:	f3 67 a4[ 	]+rep addr32 movsb %ds:\(%esi\),%es:\(%edi\)
+  49:	f3 67 ac[ 	]+rep addr32 lods %ds:\(%esi\),%al
+  4c:	f3 67 aa[ 	]+rep addr32 stos %al,%es:\(%edi\)
+  4f:	f3 67 a6[ 	]+repz addr32 cmpsb %es:\(%edi\),%ds:\(%esi\)
+  52:	f3 67 ae[ 	]+repz addr32 scas %es:\(%edi\),%al
+  55:	f3 67 66 6d[ 	]+rep addr32 insw \(%dx\),%es:\(%edi\)
+  59:	f3 67 66 6f[ 	]+rep addr32 outsw %ds:\(%esi\),\(%dx\)
+  5d:	f3 67 66 a5[ 	]+rep addr32 movsw %ds:\(%esi\),%es:\(%edi\)
+  61:	f3 67 66 ad[ 	]+rep addr32 lods %ds:\(%esi\),%ax
+  65:	f3 67 66 ab[ 	]+rep addr32 stos %ax,%es:\(%edi\)
+  69:	f3 67 66 a7[ 	]+repz addr32 cmpsw %es:\(%edi\),%ds:\(%esi\)
+  6d:	f3 67 66 af[ 	]+repz addr32 scas %es:\(%edi\),%ax
+  71:	f3 67 6d[ 	]+rep addr32 insl \(%dx\),%es:\(%edi\)
+  74:	f3 67 6f[ 	]+rep addr32 outsl %ds:\(%esi\),\(%dx\)
+  77:	f3 67 a5[ 	]+rep addr32 movsl %ds:\(%esi\),%es:\(%edi\)
+  7a:	f3 67 ad[ 	]+rep addr32 lods %ds:\(%esi\),%eax
+  7d:	f3 67 ab[ 	]+rep addr32 stos %eax,%es:\(%edi\)
+  80:	f3 67 a7[ 	]+repz addr32 cmpsl %es:\(%edi\),%ds:\(%esi\)
+  83:	f3 67 af[ 	]+repz addr32 scas %es:\(%edi\),%eax
+  86:	f3 67 48 a5[ 	]+rep addr32 movsq %ds:\(%esi\),%es:\(%edi\)
+  8a:	f3 67 48 ad[ 	]+rep addr32 lods %ds:\(%esi\),%rax
+  8e:	f3 67 48 ab[ 	]+rep addr32 stos %rax,%es:\(%edi\)
+  92:	f3 67 48 a7[ 	]+repz addr32 cmpsq %es:\(%edi\),%ds:\(%esi\)
+  96:	f3 67 48 af[ 	]+repz addr32 scas %es:\(%edi\),%rax
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-rep.s b/gas/testsuite/gas/i386/x86-64-rep.s
new file mode 100644
index 000000000000..c4c8b3456902
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rep.s
@@ -0,0 +1,62 @@
+ 	.text
+
+_start:
+	rep insb
+	rep outsb
+	rep movsb
+	rep lodsb
+	rep stosb
+	repz cmpsb
+	repz scasb
+
+	rep insw
+	rep outsw
+	rep movsw
+	rep lodsw
+	rep stosw
+	repz cmpsw
+	repz scasw
+
+	rep insl
+	rep outsl
+	rep movsl
+	rep lodsl
+	rep stosl
+	repz cmpsl
+	repz scasl
+
+	rep movsq
+	rep lodsq
+	rep stosq
+	repz cmpsq
+	repz scasq
+
+	addr32 rep insb
+	addr32 rep outsb
+	addr32 rep movsb
+	addr32 rep lodsb
+	addr32 rep stosb
+	addr32 repz cmpsb
+	addr32 repz scasb
+
+	addr32 rep insw
+	addr32 rep outsw
+	addr32 rep movsw
+	addr32 rep lodsw
+	addr32 rep stosw
+	addr32 repz cmpsw
+	addr32 repz scasw
+
+	addr32 rep insl
+	addr32 rep outsl
+	addr32 rep movsl
+	addr32 rep lodsl
+	addr32 rep stosl
+	addr32 repz cmpsl
+	addr32 repz scasl
+
+	addr32 rep movsq
+	addr32 rep lodsq
+	addr32 rep stosq
+	addr32 repz cmpsq
+	addr32 repz scasq
diff --git a/gas/testsuite/gas/i386/x86-64-rip.d b/gas/testsuite/gas/i386/x86-64-rip.d
new file mode 100644
index 000000000000..1b1d6c8a31c5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rip.d
@@ -0,0 +1,13 @@
+#as: -J
+#objdump: -drw
+#name: x86-64 rip addressing
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[	 ]*0:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*6:[	 ]+8d 05 11 11 11 11[	 ]+lea[	 ]+286331153\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*c:[	 ]+8d 05 01 00 00 00[	 ]+lea[	 ]+1\(%rip\),%eax[ 	]*(#.*)?
+[	 ]*12:[	 ]+8d 05 00 00 00 00[	 ]+lea[	 ]+0\(%rip\),%eax[ 	]*(#.*)?
diff --git a/gas/testsuite/gas/i386/x86-64-rip.s b/gas/testsuite/gas/i386/x86-64-rip.s
new file mode 100644
index 000000000000..c6ac1954b219
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-rip.s
@@ -0,0 +1,5 @@
+.text
+	leal	symbol(%rip), %eax
+	leal	0x11111111(%rip), %eax
+	leal	1(%rip), %eax
+	leal	(%rip), %eax
diff --git a/gas/testsuite/gas/i386/x86-64-segment.l b/gas/testsuite/gas/i386/x86-64-segment.l
new file mode 100644
index 000000000000..4056fde869e7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-segment.l
@@ -0,0 +1,12 @@
+   1              	.psize 0
+   2              	.text
+   3              	# test segment reg insns with memory operand
+   4 0000 8C18     		movw	%ds,\(%rax\)
+   5 0002 8C18     		mov	%ds,\(%rax\)
+   6 0004 8E18     		movw	\(%rax\),%ds
+   7 0006 8E18     		mov	\(%rax\),%ds
+   8              	# test segment reg insns with REX
+   9 0008 488CD8   		movq	%ds,%rax
+  10 000b 488ED8   		movq	%rax,%ds
+  11              		# Force a good alignment.
+  12 000e 0000     		.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-segment.s b/gas/testsuite/gas/i386/x86-64-segment.s
new file mode 100644
index 000000000000..16fcd7619060
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-segment.s
@@ -0,0 +1,12 @@
+.psize 0
+.text
+# test segment reg insns with memory operand
+	movw	%ds,(%rax)
+	mov	%ds,(%rax)
+	movw	(%rax),%ds
+	mov	(%rax),%ds
+# test segment reg insns with REX
+	movq	%ds,%rax
+	movq	%rax,%ds
+	# Force a good alignment.
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86-64-stack-intel.d b/gas/testsuite/gas/i386/x86-64-stack-intel.d
new file mode 100644
index 000000000000..0dfab4d3fbe8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-stack-intel.d
@@ -0,0 +1,40 @@
+#objdump: -dwMintel
+#name: x86-64 stack-related opcodes (Intel mode)
+#source: x86-64-stack.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[	 ]*[0-9a-f]+:[	 ]+50[	 ]+push[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 50[	 ]+push[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 50[	 ]+push[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+58[	 ]+pop[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 58[	 ]+pop[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 58[	 ]+pop[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+8f c0[	 ]+pop[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 8f c0[	 ]+pop[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f c0[	 ]+pop[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+8f 00[	 ]+pop[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 8f 00[	 ]+pop[	 ]+WORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f 00[	 ]+pop[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+ff d0[	 ]+call[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff d0[	 ]+call[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff d0[	 ]+call[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+call[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 ff 10[	 ]+call[	 ]+WORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 10[	 ]+call[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+ff e0[	 ]+jmp[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff e0[	 ]+jmp[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff e0[	 ]+jmp[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+ff 20[	 ]+jmp[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 ff 20[	 ]+jmp[	 ]+WORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 20[	 ]+jmp[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+ff f0[	 ]+push[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff f0[	 ]+push[	 ]+ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff f0[	 ]+push[	 ]+rax
+[	 ]*[0-9a-f]+:[	 ]+ff 30[	 ]+push[	 ]+QWORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 ff 30[	 ]+push[	 ]+WORD PTR \[rax\]
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 30[	 ]+push[	 ]+QWORD PTR \[rax\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/x86-64-stack-suffix.d
new file mode 100644
index 000000000000..c5d789d8a71d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-stack-suffix.d
@@ -0,0 +1,40 @@
+#objdump: -dwMsuffix
+#name: x86-64 stack-related opcodes (with suffixes)
+#source: x86-64-stack.s
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[	 ]*[0-9a-f]+:[	 ]+50[	 ]+pushq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 50[	 ]+pushw[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 50[	 ]+pushq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+58[	 ]+popq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 58[	 ]+popw[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 58[	 ]+popq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+8f c0[	 ]+popq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 8f c0[	 ]+popw[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f c0[	 ]+popq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 8f 00[	 ]+popw[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f 00[	 ]+popq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff d0[	 ]+callq[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff d0[	 ]+callw[	 ]+\*%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff d0[	 ]+callq[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 10[	 ]+callw[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 10[	 ]+callq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff e0[	 ]+jmpq[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff e0[	 ]+jmpw[	 ]+\*%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff e0[	 ]+jmpq[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 20[	 ]+jmpq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 20[	 ]+jmpw[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 20[	 ]+jmpq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff f0[	 ]+pushq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff f0[	 ]+pushw[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff f0[	 ]+pushq[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 30[	 ]+pushw[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 30[	 ]+pushq[	 ]+\(%rax\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-stack.d b/gas/testsuite/gas/i386/x86-64-stack.d
new file mode 100644
index 000000000000..fa010a981a12
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-stack.d
@@ -0,0 +1,39 @@
+#objdump: -dw
+#name: x86-64 stack-related opcodes
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+[	 ]*[0-9a-f]+:[	 ]+50[	 ]+pushq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 50[	 ]+pushw?[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 50[	 ]+pushq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+58[	 ]+popq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 58[	 ]+popw?[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 58[	 ]+popq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+8f c0[	 ]+popq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 8f c0[	 ]+popw?[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f c0[	 ]+popq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+8f 00[	 ]+popq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 8f 00[	 ]+popw[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 8f 00[	 ]+popq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff d0[	 ]+callq?[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff d0[	 ]+callw?[	 ]+\*%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff d0[	 ]+callq?[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 10[	 ]+callq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 10[	 ]+callw[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 10[	 ]+callq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff e0[	 ]+jmpq?[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff e0[	 ]+jmpw?[	 ]+\*%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff e0[	 ]+jmpq?[	 ]+\*%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 20[	 ]+jmpq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 20[	 ]+jmpw[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 20[	 ]+jmpq[	 ]+\*\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+ff f0[	 ]+pushq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+66 ff f0[	 ]+pushw?[	 ]+%ax
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff f0[	 ]+pushq?[	 ]+%rax
+[	 ]*[0-9a-f]+:[	 ]+ff 30[	 ]+pushq[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 ff 30[	 ]+pushw[	 ]+\(%rax\)
+[	 ]*[0-9a-f]+:[	 ]+66 48 ff 30[	 ]+pushq[	 ]+\(%rax\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-stack.s b/gas/testsuite/gas/i386/x86-64-stack.s
new file mode 100644
index 000000000000..e0fc046bbc14
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-stack.s
@@ -0,0 +1,23 @@
+ .macro try bytes:vararg
+  .byte \bytes
+  .byte 0x66, \bytes
+  .byte 0x66, 0x48, \bytes
+ .endm
+
+ .text
+
+_start:
+	try	0x50
+	try	0x58
+
+	try	0x8f, 0xc0
+	try	0x8f, 0x00
+
+	try	0xff, 0xd0
+	try	0xff, 0x10
+
+	try	0xff, 0xe0
+	try	0xff, 0x20
+
+	try	0xff, 0xf0
+	try	0xff, 0x30
diff --git a/gas/testsuite/gas/i386/x86-64-unwind.d b/gas/testsuite/gas/i386/x86-64-unwind.d
new file mode 100644
index 000000000000..6ce528afd2f4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-unwind.d
@@ -0,0 +1,28 @@
+#readelf: -S
+#name: x86-64 unwind
+
+There are 8 section headers, starting at offset 0x80:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0000000000000000  00000000
+       0000000000000000  0000000000000000           0     0     0
+  \[ 1\] \.text             PROGBITS         0000000000000000  00000040
+       0000000000000000  0000000000000000  AX       0     0     4
+  \[ 2\] \.data             PROGBITS         0000000000000000  00000040
+       0000000000000000  0000000000000000  WA       0     0     4
+  \[ 3\] \.bss              NOBITS           0000000000000000  00000040
+       0000000000000000  0000000000000000  WA       0     0     4
+  \[ 4\] \.eh_frame         X86_64_UNWIND    0000000000000000  00000040
+       0000000000000008  0000000000000000   A       0     0     1
+  \[ 5\] \.shstrtab         STRTAB           0000000000000000  00000048
+       0000000000000036  0000000000000000           0     0     1
+  \[ 6\] \.symtab           SYMTAB           0000000000000000  00000280
+       0000000000000078  0000000000000018           7     5     8
+  \[ 7\] \.strtab           STRTAB           0000000000000000  000002f8
+       0000000000000001  0000000000000000           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
diff --git a/gas/testsuite/gas/i386/x86-64-unwind.s b/gas/testsuite/gas/i386/x86-64-unwind.s
new file mode 100644
index 000000000000..da6f0f5b70d9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-unwind.s
@@ -0,0 +1,8 @@
+# First create .eh_frame with the right type.
+.section	.eh_frame,"a",@unwind
+.long 0
+
+# Verify that switching back into .eh_frame does not change
+# its type.
+.section .eh_frame
+.long 1
diff --git a/gas/testsuite/gas/i386/x86-64-vmx.d b/gas/testsuite/gas/i386/x86-64-vmx.d
new file mode 100644
index 000000000000..201dc059652c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vmx.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: 64bit VMX
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <foo>:
+   0:	0f 01 c1 [ 	]*vmcall 
+   3:	0f 01 c2 [ 	]*vmlaunch 
+   6:	0f 01 c3 [ 	]*vmresume 
+   9:	0f 01 c4 [ 	]*vmxoff 
+   c:	66 0f c7 30 [ 	]*vmclear \(%rax\)
+  10:	0f c7 30 [ 	]*vmptrld \(%rax\)
+  13:	0f c7 38 [ 	]*vmptrst \(%rax\)
+  16:	f3 0f c7 30 [ 	]*vmxon  \(%rax\)
+  1a:	0f 78 c3 [ 	]*vmread %rax,%rbx
+  1d:	0f 78 c3 [ 	]*vmread %rax,%rbx
+  20:	0f 78 03 [ 	]*vmread %rax,\(%rbx\)
+  23:	0f 78 03 [ 	]*vmread %rax,\(%rbx\)
+  26:	0f 79 d8 [ 	]*vmwrite %rax,%rbx
+  29:	0f 79 d8 [ 	]*vmwrite %rax,%rbx
+  2c:	0f 79 18 [ 	]*vmwrite \(%rax\),%rbx
+  2f:	0f 79 18 [ 	]*vmwrite \(%rax\),%rbx
+	...
diff --git a/gas/testsuite/gas/i386/x86-64-vmx.s b/gas/testsuite/gas/i386/x86-64-vmx.s
new file mode 100644
index 000000000000..7c4018167e41
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-vmx.s
@@ -0,0 +1,21 @@
+# VMX Instructions
+
+	.text
+foo:
+	vmcall
+	vmlaunch
+	vmresume
+	vmxoff
+	vmclear (%rax)
+	vmptrld (%rax)
+	vmptrst (%rax)
+	vmxon (%rax)
+	vmread %rax,%rbx
+	vmreadq %rax,%rbx
+	vmread %rax,(%rbx)
+	vmreadq %rax,(%rbx)
+	vmwrite %rax,%rbx
+	vmwriteq %rax,%rbx
+	vmwrite (%rax),%rbx
+	vmwriteq (%rax),%rbx
+	.p2align	4,0
diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d
index 1af2278728d4..60452a512735 100644
--- a/gas/testsuite/gas/i386/x86_64.d
+++ b/gas/testsuite/gas/i386/x86_64.d
@@ -1,6 +1,7 @@
 #as: -J
 #objdump: -dw
 #name: i386 x86_64
+#stderr: x86_64.e
 .*: +file format .*
 
 Disassembly of section .text:
@@ -36,9 +37,9 @@ Disassembly of section .text:
 [ 	]+56:	41 0f 20 c0[ 	]+mov[ 	]+%cr0,%r8
 [ 	]+5a:	44 0f 20 c0[ 	]+mov[ 	]+%cr8,%rax
 [ 	]+5e:	44 0f 22 c0[ 	]+mov[ 	]+%rax,%cr8
-[ 	]+62:	f3 48 a5[ 	]+repz movsq %ds:\(%rsi\),%es:\(%rdi\)
-[ 	]+65:	f3 66 a5[ 	]+repz movsw %ds:\(%esi\),%es:\(%edi\)
-[ 	]+68:	f3 48 a5[ 	]+repz movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]+62:	f3 48 a5[ 	]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]+65:	f3 66 a5[ 	]+rep movsw %ds:\(%rsi\),%es:\(%rdi\)
+[ 	]+68:	f3 48 a5[ 	]+rep movsq %ds:\(%rsi\),%es:\(%rdi\)
 [ 	]+6b:	b0 11[ 	]+mov[ 	]+\$0x11,%al
 [ 	]+6d:	b4 11[ 	]+mov[ 	]+\$0x11,%ah
 [ 	]+6f:	40 b4 11[ 	]+mov[ 	]+\$0x11,%spl
@@ -117,10 +118,42 @@ Disassembly of section .text:
  1d7:	66 b8 00 00[ 	]+mov[ 	]+\$0x0,%ax
  1db:	b8 00 00 00 00[ 	]+mov[ 	]+\$0x0,%eax
  1e0:	48 c7 c0 00 00 00 00 	mov[ 	]+\$0x0,%rax
- 1e7:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 1ee:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 1f5:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
- 1fe:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
- 205:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
- 20b:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
-	...
+ 1e7:	a1 00 00 00 00 00 00 00 00 	mov[ 	]+0x0,%eax
+ 1f0:	8b 04 25 00 00 00 00 	mov[ 	]+0x0,%eax
+ 1f7:	8b 80 00 00 00 00[ 	]+mov[ 	]+0x0\(%rax\),%eax
+ 1fd:	8b 05 00 00 00 00[ 	]+mov[ 	]+0\(%rip\),%eax.*
+
+0+203 <foo>:
+ 203:	a0 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%al
+ 20c:	66 a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%ax
+ 216:	a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%eax
+ 21f:	48 a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%rax
+ 229:	a2 11 22 33 44 55 66 77 88 	mov[ 	]+%al,0x8877665544332211
+ 232:	66 a3 11 22 33 44 55 66 77 88 	mov[ 	]+%ax,0x8877665544332211
+ 23c:	a3 11 22 33 44 55 66 77 88 	mov[ 	]+%eax,0x8877665544332211
+ 245:	48 a3 11 22 33 44 55 66 77 88 	mov[ 	]+%rax,0x8877665544332211
+ 24f:	a0 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%al
+ 258:	66 a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%ax
+ 262:	a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%eax
+ 26b:	48 a1 11 22 33 44 55 66 77 88 	mov[ 	]+0x8877665544332211,%rax
+ 275:	a2 11 22 33 44 55 66 77 88 	mov[ 	]+%al,0x8877665544332211
+ 27e:	66 a3 11 22 33 44 55 66 77 88 	mov[ 	]+%ax,0x8877665544332211
+ 288:	a3 11 22 33 44 55 66 77 88 	mov[ 	]+%eax,0x8877665544332211
+ 291:	48 a3 11 22 33 44 55 66 77 88 	mov[ 	]+%rax,0x8877665544332211
+ 29b:	8a 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%al
+ 2a2:	66 8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%ax
+ 2aa:	8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%eax
+ 2b1:	48 8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%rax
+ 2b9:	88 04 25 11 22 33 ff 	mov[ 	]+%al,0xffffffffff332211
+ 2c0:	66 89 04 25 11 22 33 ff 	mov[ 	]+%ax,0xffffffffff332211
+ 2c8:	89 04 25 11 22 33 ff 	mov[ 	]+%eax,0xffffffffff332211
+ 2cf:	48 89 04 25 11 22 33 ff 	mov[ 	]+%rax,0xffffffffff332211
+ 2d7:	8a 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%al
+ 2de:	66 8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%ax
+ 2e6:	8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%eax
+ 2ed:	48 8b 04 25 11 22 33 ff 	mov[ 	]+0xffffffffff332211,%rax
+ 2f5:	88 04 25 11 22 33 ff 	mov[ 	]+%al,0xffffffffff332211
+ 2fc:	66 89 04 25 11 22 33 ff 	mov[ 	]+%ax,0xffffffffff332211
+ 304:	89 04 25 11 22 33 ff 	mov[ 	]+%eax,0xffffffffff332211
+ 30b:	48 89 04 25 11 22 33 ff 	mov[ 	]+%rax,0xffffffffff332211
+#pass
diff --git a/gas/testsuite/gas/i386/x86_64.e b/gas/testsuite/gas/i386/x86_64.e
new file mode 100644
index 000000000000..e11e90358fd9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86_64.e
@@ -0,0 +1,9 @@
+.*.s: Assembler messages:
+.*:51: Warning: Treating .\[0x22222222\]. as memory reference
+.*:89: Warning: Treating .DWORD PTR \[0x22222222\]. as memory reference
+.*:91: Warning: Treating .\[0x8877665544332211\]. as memory reference
+.*:92: Warning: Treating .\[0x8877665544332211\]. as memory reference
+.*:93: Warning: Treating .\[0x8877665544332211\]. as memory reference
+.*:94: Warning: Treating .\[0x8877665544332211\]. as memory reference
+.*:95: Warning: Treating .\[0x8877665544332211\]. as memory reference
+.*:96: Warning: Treating .\[0x8877665544332211\]. as memory reference
diff --git a/gas/testsuite/gas/i386/x86_64.s b/gas/testsuite/gas/i386/x86_64.s
index d65054eb768c..3e5532ab297b 100644
--- a/gas/testsuite/gas/i386/x86_64.s
+++ b/gas/testsuite/gas/i386/x86_64.s
@@ -127,14 +127,14 @@ mov symbol(%rip), %eax
 .intel_syntax noprefix
 
 #immediates - various sizes:
-mov al, flat symbol
-mov ax, flat symbol
-mov eax, flat symbol
-mov rax, flat symbol
+mov al, flat:symbol
+mov ax, flat:symbol
+mov eax, flat:symbol
+mov rax, flat:symbol
 
-#parts
-mov eax, high part symbol
-mov eax, low part symbol
+#parts aren't supported by the parser, yet (and not at all for symbol refs)
+#mov eax, high part symbol
+#mov eax, low part symbol
 
 #addressing modes
 
@@ -150,5 +150,43 @@ mov eax, [rax+symbol]
 #RIP relative
 mov eax, [rip+symbol]
 
+foo:
+.att_syntax
+#absolute 64bit addressing
+mov 0x8877665544332211,%al
+mov 0x8877665544332211,%ax
+mov 0x8877665544332211,%eax
+mov 0x8877665544332211,%rax
+mov %al,0x8877665544332211
+mov %ax,0x8877665544332211
+mov %eax,0x8877665544332211
+mov %rax,0x8877665544332211
+movb 0x8877665544332211,%al
+movw 0x8877665544332211,%ax
+movl 0x8877665544332211,%eax
+movq 0x8877665544332211,%rax
+movb %al,0x8877665544332211
+movw %ax,0x8877665544332211
+movl %eax,0x8877665544332211
+movq %rax,0x8877665544332211
+
+#absolute signed 32bit addressing
+mov 0xffffffffff332211,%al
+mov 0xffffffffff332211,%ax
+mov 0xffffffffff332211,%eax
+mov 0xffffffffff332211,%rax
+mov %al,0xffffffffff332211
+mov %ax,0xffffffffff332211
+mov %eax,0xffffffffff332211
+mov %rax,0xffffffffff332211
+movb 0xffffffffff332211,%al
+movw 0xffffffffff332211,%ax
+movl 0xffffffffff332211,%eax
+movq 0xffffffffff332211,%rax
+movb %al,0xffffffffff332211
+movw %ax,0xffffffffff332211
+movl %eax,0xffffffffff332211
+movq %rax,0xffffffffff332211
+
 # Get a good alignment.
  .p2align	4,0
diff --git a/gas/testsuite/gas/i860/dir-intel03-err.l b/gas/testsuite/gas/i860/dir-intel03-err.l
index 480e1aea5831..b8261282bf79 100644
--- a/gas/testsuite/gas/i860/dir-intel03-err.l
+++ b/gas/testsuite/gas/i860/dir-intel03-err.l
@@ -1,5 +1,5 @@
 .*: Assembler messages:
 .*:8: Error: Directive .atmp available only with -mintel-syntax option
-.*:8: Warning: rest of line ignored; first ignored character is `r'
+.*:8: Error: junk at end of line, first unrecognized character is `r'
 .*:10: Error: Directive .dual available only with -mintel-syntax option
 .*:13: Error: Directive .enddual available only with -mintel-syntax option
diff --git a/gas/testsuite/gas/ia64/alloc.l b/gas/testsuite/gas/ia64/alloc.l
new file mode 100644
index 000000000000..42a866a18301
--- /dev/null
+++ b/gas/testsuite/gas/ia64/alloc.l
@@ -0,0 +1,11 @@
+# Currently in the error messages the operand numbers for the constants
+# aren't correct, which is why the patterns only check for ranges.
+.*: Assembler messages:
+.*:7: Error: Operand [345] of .alloc. should be .*
+.*:8: Error: Operand [345] of .alloc. should be .*
+.*:9: Error: Operand [345] of .alloc. should be .*
+.*:10: Error: Operand [56] of .alloc. should be .*
+.*:11: Error: Operand [234] of .alloc. should be .*
+.*:12: Error: Operand [234] of .alloc. should be .*
+.*:13: Error: Operand [234] of .alloc. should be .*
+.*:14: Error: Operand [45] of .alloc. should be .*
diff --git a/gas/testsuite/gas/ia64/alloc.s b/gas/testsuite/gas/ia64/alloc.s
new file mode 100644
index 000000000000..0fcdb848b352
--- /dev/null
+++ b/gas/testsuite/gas/ia64/alloc.s
@@ -0,0 +1,14 @@
+// Make sure error messages on 'alloc' don't needlessly refer to operand 1
+// (which gets parsed late) when only one of the other operands is wrong.
+
+	.text
+
+alloc:
+	alloc		r2 = ar.pfs, x, 0, 0, 0
+	alloc		r2 = ar.pfs, 0, x, 0, 0
+	alloc		r2 = ar.pfs, 0, 0, x, 0
+	alloc		r2 = ar.pfs, 0, 0, 0, x
+	alloc		r3 = x, 0, 0, 0
+	alloc		r3 = 0, x, 0, 0
+	alloc		r3 = 0, 0, x, 0
+	alloc		r3 = 0, 0, 0, x
diff --git a/gas/testsuite/gas/ia64/bundling.d b/gas/testsuite/gas/ia64/bundling.d
new file mode 100644
index 000000000000..2ddece1f03f4
--- /dev/null
+++ b/gas/testsuite/gas/ia64/bundling.d
@@ -0,0 +1,14 @@
+# objdump: -d
+# name: ia64 explicit bundling
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MII]       nop\.m 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.i 0x0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i r31=ar\.lc;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[..B]       nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+br\.ret\.sptk\.few b0;;
diff --git a/gas/testsuite/gas/ia64/bundling.s b/gas/testsuite/gas/ia64/bundling.s
new file mode 100644
index 000000000000..23a987d47f03
--- /dev/null
+++ b/gas/testsuite/gas/ia64/bundling.s
@@ -0,0 +1,15 @@
+.explicit
+.proc	_start
+_start:
+	.prologue
+{.mii
+	nop.m	0
+	;;
+	.save		ar.lc, r31
+	mov		r31 = ar.lc
+}	;;
+	.body
+{.mfb
+	br.ret.sptk	rp
+}	;;
+.endp	_start
diff --git a/gas/testsuite/gas/ia64/dv-imply.d b/gas/testsuite/gas/ia64/dv-imply.d
index affc8d4ed398..30ae379672f0 100644
--- a/gas/testsuite/gas/ia64/dv-imply.d
+++ b/gas/testsuite/gas/ia64/dv-imply.d
@@ -1,4 +1,4 @@
-# as: -xexplicit
+# as: -xexplicit -mtune=itanium1
 # objdump: -d
 # name ia64 dv-mutex
 
@@ -7,39 +7,39 @@
 Disassembly of section \.text:
 
 0+000 <L-0xc0>:
-   0:	3c 20 08 00 00 21 	\[MFB\] \(p01\) mov r4=2
+   0:	3c 20 08 00 00 24 	\[MFB\] \(p01\) mov r4=2
    6:	00 00 00 02 00 01 	            nop\.f 0x0
    c:	c0 00 00 40       	      \(p02\) br\.cond\.sptk\.few c0 <L>
-  10:	1d 20 1c 00 00 21 	\[MFB\]       mov r4=7
+  10:	1d 20 1c 00 00 24 	\[MFB\]       mov r4=7
   16:	00 00 00 02 00 00 	            nop\.f 0x0
   1c:	00 00 20 00       	            rfi;;
-  20:	1c 20 08 00 00 21 	\[MFB\]       mov r4=2
+  20:	1c 20 08 00 00 24 	\[MFB\]       mov r4=2
   26:	00 00 00 02 00 01 	            nop\.f 0x0
   2c:	a0 00 00 40       	      \(p02\) br\.cond\.sptk\.few c0 <L>
-  30:	3d 20 1c 00 00 21 	\[MFB\] \(p01\) mov r4=7
+  30:	3d 20 1c 00 00 24 	\[MFB\] \(p01\) mov r4=7
   36:	00 00 00 02 00 00 	            nop\.f 0x0
   3c:	00 00 20 00       	            rfi;;
   40:	6a 08 06 04 02 78 	\[MMI\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2;;
-  46:	40 10 00 00 42 00 	      \(p01\) mov r4=2
+  46:	40 10 00 00 48 00 	      \(p01\) mov r4=2
   4c:	00 00 04 00       	            nop\.i 0x0
   50:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   56:	00 00 00 02 80 01 	            nop\.f 0x0
   5c:	70 00 00 40       	      \(p03\) br\.cond\.sptk\.few c0 <L>
-  60:	1d 20 1c 00 00 21 	\[MFB\]       mov r4=7
+  60:	1d 20 1c 00 00 24 	\[MFB\]       mov r4=7
   66:	00 00 00 02 00 00 	            nop\.f 0x0
   6c:	00 00 20 00       	            rfi;;
   70:	62 08 06 04 02 38 	\[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2
   76:	30 28 18 88 e8 80 	            cmp\.eq\.or p3,p4=r5,r6;;
-  7c:	20 00 00 84       	      \(p01\) mov r4=2
+  7c:	20 00 00 90       	      \(p01\) mov r4=2
   80:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   86:	00 00 00 02 80 01 	            nop\.f 0x0
   8c:	40 00 00 40       	      \(p03\) br\.cond\.sptk\.few c0 <L>
-  90:	1d 20 1c 00 00 21 	\[MFB\]       mov r4=7
+  90:	1d 20 1c 00 00 24 	\[MFB\]       mov r4=7
   96:	00 00 00 02 00 00 	            nop\.f 0x0
   9c:	00 00 20 00       	            rfi;;
   a0:	10 08 16 0c 42 70 	\[MIB\]       cmp\.ne\.and p1,p2=r5,r6
-  a6:	40 10 00 00 c2 01 	      \(p01\) mov r4=2
+  a6:	40 10 00 00 c8 01 	      \(p01\) mov r4=2
   ac:	20 00 00 40       	      \(p03\) br\.cond\.sptk\.few c0 <L>
-  b0:	1d 20 1c 00 00 21 	\[MFB\]       mov r4=7
+  b0:	1d 20 1c 00 00 24 	\[MFB\]       mov r4=7
   b6:	00 00 00 02 00 00 	            nop\.f 0x0
   bc:	00 00 20 00       	            rfi;;
diff --git a/gas/testsuite/gas/ia64/dv-mutex.d b/gas/testsuite/gas/ia64/dv-mutex.d
index 2926ab2cbc33..66ea0fd03d8b 100644
--- a/gas/testsuite/gas/ia64/dv-mutex.d
+++ b/gas/testsuite/gas/ia64/dv-mutex.d
@@ -1,4 +1,4 @@
-# as: -xexplicit
+# as: -xexplicit -mtune=itanium1
 # objdump: -d
 # name ia64 dv-mutex
 
@@ -7,33 +7,33 @@
 Disassembly of section \.text:
 
 0+000 <start>:
-   0:	20 20 08 00 00 a1 	\[MII\] \(p01\) mov r4=2
-   6:	40 28 00 00 c2 81 	      \(p02\) mov r4=5
-   c:	70 00 00 84       	      \(p03\) mov r4=7
+   0:	20 20 08 00 00 a4 	\[MII\] \(p01\) mov r4=2
+   6:	40 28 00 00 c8 81 	      \(p02\) mov r4=5
+   c:	70 00 00 90       	      \(p03\) mov r4=7
   10:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   16:	00 00 00 02 00 00 	            nop\.f 0x0
   1c:	00 00 20 00       	            rfi;;
   20:	0a 08 04 04 02 78 	\[MMI\]       cmp\.eq p1,p2=r1,r2;;
-  26:	40 10 00 00 42 81 	      \(p01\) mov r4=2
-  2c:	40 00 00 84       	      \(p02\) mov r4=4
+  26:	40 10 00 00 48 81 	      \(p01\) mov r4=2
+  2c:	40 00 00 90       	      \(p02\) mov r4=4
   30:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   36:	00 00 00 02 00 00 	            nop\.f 0x0
   3c:	00 00 20 00       	            rfi;;
   40:	6a 08 06 04 02 78 	\[MMI\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2;;
-  46:	40 10 00 00 42 81 	      \(p01\) mov r4=2
-  4c:	40 00 00 84       	      \(p02\) mov r4=4
+  46:	40 10 00 00 48 81 	      \(p01\) mov r4=2
+  4c:	40 00 00 90       	      \(p02\) mov r4=4
   50:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   56:	00 00 00 02 00 00 	            nop\.f 0x0
   5c:	00 00 20 00       	            rfi;;
   60:	0a 08 04 04 02 78 	\[MMI\]       cmp\.eq p1,p2=r1,r2;;
-  66:	40 10 00 00 42 81 	      \(p01\) mov r4=2
-  6c:	40 00 00 84       	      \(p02\) mov r4=4
+  66:	40 10 00 00 48 81 	      \(p01\) mov r4=2
+  6c:	40 00 00 90       	      \(p02\) mov r4=4
   70:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   76:	00 00 00 02 00 00 	            nop\.f 0x0
   7c:	00 00 20 00       	            rfi;;
   80:	6a 08 04 04 02 78 	\[MMI\] \(p03\) cmp\.eq p1,p2=r1,r2;;
-  86:	40 10 00 00 42 81 	      \(p01\) mov r4=2
-  8c:	40 00 00 84       	      \(p02\) mov r4=4
+  86:	40 10 00 00 48 81 	      \(p01\) mov r4=2
+  8c:	40 00 00 90       	      \(p02\) mov r4=4
   90:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   96:	00 00 00 02 00 00 	            nop\.f 0x0
   9c:	00 00 20 00       	            rfi;;
diff --git a/gas/testsuite/gas/ia64/dv-raw-err.l b/gas/testsuite/gas/ia64/dv-raw-err.l
index 3623d0c53208..b73a2144eeb9 100644
--- a/gas/testsuite/gas/ia64/dv-raw-err.l
+++ b/gas/testsuite/gas/ia64/dv-raw-err.l
@@ -51,7 +51,7 @@
 .*:98: Warning: This is the location of the conflicting usage
 .*:104: Warning: Use of 'ld8\.fill' .* RAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
 .*:103: Warning: This is the location of the conflicting usage
-.*:111: Warning: Use of 'mov' .* RAW dependency 'BR%, % in 0 - 7' \(impliedf\)
+.*:111: Warning: Use of 'mov' .* RAW dependency 'BR%, % in 0 - 7' \(impliedf\), specific resource number is 0
 .*:110: Warning: This is the location of the conflicting usage
 .*:116: Warning: Use of 'fadd' .* RAW dependency 'CFM' \(impliedf\)
 .*:115: Warning: This is the location of the conflicting usage
@@ -277,3 +277,19 @@
 .*:569: Warning: This is the location of the conflicting usage
 .*:573: Warning: Use of 'br.cond.sptk' may violate RAW dependency 'PR%, % in 16 - 62' \(impliedf\), specific resource number is 25
 .*:572: Warning: This is the location of the conflicting usage
+.*:581: Warning: Use of 'adds' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:580: Warning: This is the location of the conflicting usage
+.*:584: Warning: Use of 'adds' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:583: Warning: This is the location of the conflicting usage
+.*:587: Warning: Use of 'add' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:586: Warning: This is the location of the conflicting usage
+.*:590: Warning: Use of 'ld8' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:589: Warning: This is the location of the conflicting usage
+.*:590: Warning: Use of 'ld8' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:589: Warning: This is the location of the conflicting usage
+.*:593: Warning: Use of 'ldfd' .* RAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:592: Warning: This is the location of the conflicting usage
+.*:593: Warning: Use of 'ldfd' .* WAW dependency 'GR%, % in 1 - 127' \(impliedf\), specific resource number is 6
+.*:592: Warning: This is the location of the conflicting usage
+.*:601: Warning: Use of 'ld8' .* RAW dependency 'PSR\.vm' \(implied\)
+.*:600: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-raw-err.s b/gas/testsuite/gas/ia64/dv-raw-err.s
index 44fb89c485c7..cf9f75e42952 100644
--- a/gas/testsuite/gas/ia64/dv-raw-err.s
+++ b/gas/testsuite/gas/ia64/dv-raw-err.s
@@ -6,8 +6,8 @@
 .text
 	.explicit
 // AR[BSP]
-	mov	ar.bspstore = r1
-	mov	r0 = ar.bsp
+	mov	ar.bspstore = r0
+	mov	r1 = ar.bsp
 	;;
 
 // AR[BSPSTORE]	
@@ -108,12 +108,12 @@
 
 // BR%
 	mov	b0 = r0
-	mov	r0 = b0
+	mov	r2 = b0
 	;;
 	
 // CFM	
 	br.wtop.sptk	L
-	fadd	f0 = f1, f32	// read from rotating register region
+	fadd	f2 = f1, f32	// read from rotating register region
 	;;
 	
 // CR[CMCV]
@@ -276,7 +276,7 @@
 	;;
 
 // GR%
-	ld8.c.clr	r0 = [r1]	// no DV here
+	ld8.c.clr	r1 = [r1]	// no DV here
 	mov		r2 = r0		
 	;;
 	mov		r3 = r4
@@ -357,7 +357,7 @@
 	
 // PR63
 	br.wtop.sptk	L
-(p63)	add	r0 = r1, r2
+(p63)	add	r3 = r1, r2
 	;;
 	fcmp.eq p62, p63 = f2, f3
 (p63)	add	r3 = r4, r5	
@@ -368,17 +368,17 @@
 
 // PSR.ac
 	rum	(1<<3)
-	ld8	r0 = [r1]
+	ld8	r2 = [r1]
 	;;
 
 // PSR.be
 	rum	(1<<1)
-	ld8	r0 = [r1]
+	ld8	r2 = [r1]
 	;;
 	
 // PSR.bn
 	bsw.0
-	mov	r0 = r15	// no DV here, since gr < 16
+	mov	r1 = r15	// no DV here, since gr < 16
 	;;
 	bsw.1			// GAS automatically emits a stop after bsw.n
 	mov	r1 = r16	// so this conflict is avoided               
@@ -439,24 +439,24 @@
 	
 // PSR.di
 	rsm	(1<<22)
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 
 // PSR.dt
 	rsm	(1<<17)
-	ld8	r0 = [r1]
+	ld8	r1 = [r1]
 	;;
 	
 // PSR.ed (rfi is the only writer)
 // PSR.i
 	ssm	(1<<14)
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 	
 // PSR.ia (no DV semantics)
 // PSR.ic
 	ssm	(1<<13)
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 	srlz.d
 	rsm	(1<<13)
@@ -479,17 +479,17 @@
 // PSR.mc (rfi is the only writer)
 // PSR.mfh
 	mov	f32 = f33
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 
 // PSR.mfl
 	mov	f2 = f3
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 
 // PSR.pk
 	rsm	(1<<15)
-	ld8	r0 = [r1]
+	ld8	r1 = [r1]
 	;;
 	rsm	(1<<15)
 	mov	r2 = psr
@@ -497,7 +497,7 @@
 
 // PSR.pp
 	rsm	(1<<21)
-	mov	r0 = psr
+	mov	r1 = psr
 	;;
 
 // PSR.ri (no DV semantics)
@@ -509,7 +509,7 @@
 
 // PSR.si
 	rsm	(1<<23)
-	mov	r0 = ar.itc
+	mov	r1 = ar.itc
 	;;
 	ssm	(1<<23)
 	mov	r1 = ar.ec	// no DV here
@@ -517,13 +517,13 @@
 
 // PSR.sp
 	ssm	(1<<20)
-	mov	r0 = pmd[r1]
+	mov	r1 = pmd[r1]
 	;;
 	ssm	(1<<20)
 	rum	0xff
 	;;
 	ssm	(1<<20)
-	mov	r0 = rr[r1]
+	mov	r1 = rr[r1]
 	;;
 
 // PSR.ss (rfi is the only writer)
@@ -534,7 +534,7 @@
 
 // PSR.up
 	rsm	(1<<2)
-	mov	r0 = psr.um
+	mov	r1 = psr.um
 	;;
 	srlz.d
 
@@ -576,4 +576,27 @@
 (p27)	br.cond.sptk	b1	// no DV here
 	;;
 	
-L:	
+// postinc
+	st8	[r6] = r8, 16
+	add	r7 = 8, r6	// impliedf
+	;;
+	ldfd	f14 = [r6], 16
+	add	r7 = 8, r6	// impliedf
+	;;
+	stfd	[r6] = f14, 16
+	add	r7 = r8, r6
+	;;
+	add	r6 = 8, r7
+	ld8	r8 = [r6], 16	// impliedf, WAW
+	;;
+	add	r6 = 8, r7
+	ldfd	f14 = [r6], 16	// impliedf, WAW
+	;;
+
+L:
+	br.ret.sptk     rp
+
+// PSR.vm. New in SDM 2.2
+	vmsw.0
+	ld8	r2 = [r1]
+	;;
diff --git a/gas/testsuite/gas/ia64/dv-safe.d b/gas/testsuite/gas/ia64/dv-safe.d
index 8a8f3006abc9..c1da4a4c3089 100644
--- a/gas/testsuite/gas/ia64/dv-safe.d
+++ b/gas/testsuite/gas/ia64/dv-safe.d
@@ -1,4 +1,4 @@
-# as: -xexplicit
+# as: -xexplicit -mtune=itanium1
 # objdump: -d
 # name ia64 dv-safe
 
@@ -13,8 +13,8 @@ Disassembly of section \.text:
   10:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
   16:	00 00 00 02 80 21 	            nop\.f 0x0
   1c:	30 00 00 50       	      \(p03\) br\.call\.sptk\.few b1=40 <L>
-  20:	20 20 08 00 00 a1 	\[MII\] \(p01\) mov r4=2
-  26:	40 28 00 00 c2 a1 	      \(p02\) mov r4=5
+  20:	20 20 08 00 00 a4 	\[MII\] \(p01\) mov r4=2
+  26:	40 28 00 00 c8 a1 	      \(p02\) mov r4=5
   2c:	00 30 00 84       	      \(p03\) mov r5=r6
   30:	9d 28 00 0e 00 21 	\[MFB\] \(p04\) mov r5=r7
   36:	00 00 00 02 00 00 	            nop\.f 0x0
diff --git a/gas/testsuite/gas/ia64/dv-srlz.d b/gas/testsuite/gas/ia64/dv-srlz.d
index 4bd14afaa336..bf9caa48e6f6 100644
--- a/gas/testsuite/gas/ia64/dv-srlz.d
+++ b/gas/testsuite/gas/ia64/dv-srlz.d
@@ -1,4 +1,4 @@
-# as: -xauto
+# as: -xauto -mtune=itanium1
 # objdump: -d
 # name ia64 dv-srlz
 
@@ -10,7 +10,7 @@ Disassembly of section \.text:
    0:	0a 00 00 02 34 04 	\[MMI\]       ptc\.e r1;;
    6:	00 00 00 60 00 00 	            srlz\.d
    c:	00 00 04 00       	            nop\.i 0x0
-  10:	1d 00 00 00 18 10 	\[MFB\]       ld8 r0=\[r0\]
+  10:	1d 08 00 04 18 10 	\[MFB\]       ld8 r1=\[r2\]
   16:	00 00 00 02 00 00 	            nop\.f 0x0
   1c:	00 00 20 00       	            rfi;;
   20:	0b 00 00 02 34 04 	\[MMI\]       ptc\.e r1;;
diff --git a/gas/testsuite/gas/ia64/dv-waw-err.l b/gas/testsuite/gas/ia64/dv-waw-err.l
index 6c9225b497e7..c641cb383820 100644
--- a/gas/testsuite/gas/ia64/dv-waw-err.l
+++ b/gas/testsuite/gas/ia64/dv-waw-err.l
@@ -81,7 +81,7 @@
 .*:108: Warning: This is the location of the conflicting usage
 .*:114: Warning: Use of 'st8\.spill' .* WAW dependency 'AR\[UNAT\]{%}, % in 0 - 63' \(impliedf\)
 .*:113: Warning: This is the location of the conflicting usage
-.*:119: Warning: Use of 'mov\.m' .* WAW dependency 'AR%, % in 48 - 63, 112-127' \(impliedf\), specific resource number is 48
+.*:119: Warning: Use of 'mov(\.[im])?' .* WAW dependency 'AR%, % in 48 - 63, 112-127' \(impliedf\), specific resource number is 48
 .*:118: Warning: This is the location of the conflicting usage
 .*:124: Warning: Use of 'mov' .* WAW dependency 'BR%, % in 0 - 7' \(impliedf\), specific resource number is 1
 .*:123: Warning: This is the location of the conflicting usage
diff --git a/gas/testsuite/gas/ia64/dv-waw-err.s b/gas/testsuite/gas/ia64/dv-waw-err.s
index acb698391a93..37a8b0fde466 100644
--- a/gas/testsuite/gas/ia64/dv-waw-err.s
+++ b/gas/testsuite/gas/ia64/dv-waw-err.s
@@ -186,8 +186,8 @@
 	;;
 
 // CR[IRR%] (and others)
-	mov	r0 = cr.ivr
-	mov	r1 = cr.ivr
+	mov	r2 = cr.ivr
+	mov	r3 = cr.ivr
 	;;
 	
 // CR[ISR]
@@ -441,13 +441,13 @@
 // PSR.mc (rfi is the only writer)
 // PSR.mfh
 	mov	f32 = f33
-	mov	r0 = psr
+	mov	r10 = psr
 	;;
 	ssm	(1<<5)
 	ssm	(1<<5)
 	;;
 	ssm	(1<<5)
-	mov	psr.um = r0
+	mov	psr.um = r10
 	;;
 	rum	(1<<5)
 	rum	(1<<5)
@@ -458,13 +458,13 @@
 
 // PSR.mfl
 	mov	f2 = f3
-	mov	r0 = psr
+	mov	r10 = psr
 	;;
 	ssm	(1<<4)
 	ssm	(1<<4)
 	;;
 	ssm	(1<<4)
-	mov	psr.um = r0
+	mov	psr.um = r10
 	;;
 	rum	(1<<4)
 	rum	(1<<4)
diff --git a/gas/testsuite/gas/ia64/forward.d b/gas/testsuite/gas/ia64/forward.d
new file mode 100644
index 000000000000..66aecde6a954
--- /dev/null
+++ b/gas/testsuite/gas/ia64/forward.d
@@ -0,0 +1,15 @@
+# as: -xexplicit
+# objdump: -d
+# name ia64 forward references
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MIB\][[:space:]]+alloc r31=ar.pfs,12,6,8
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+[[:space:]]+dep.z r2=1,5,7
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\(p0?6\)[[:space:]]+br.cond.sptk.few 0+ <_start>;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MIB\][[:space:]]+alloc r31=ar.pfs,0,0,0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+[[:space:]]+dep.z r3=-1,1,1
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\(p0?7\)[[:space:]]+br(\.cond)?\.sptk(\.few)? [[:xdigit:]]+0 <.*>;;
diff --git a/gas/testsuite/gas/ia64/forward.s b/gas/testsuite/gas/ia64/forward.s
new file mode 100644
index 000000000000..fc2590b778c9
--- /dev/null
+++ b/gas/testsuite/gas/ia64/forward.s
@@ -0,0 +1,27 @@
+two == 2*one
+one = 1
+three == 3*one
+four = 4*one
+
+RA == rA
+rA = r2
+
+PA == pA
+pA = p6
+
+ .text
+_start:
+	alloc	r31 = one + 1, two + 2, three + 3, four + 4
+	dep.z	RA = one, two + 3, three + 4
+(PA)	br.sptk	_start
+	;;
+
+one = -1
+rA = r3
+pA = p7
+
+.L1:
+	alloc	r31 = one + 1, two + 2, three + 3, four - 4
+	dep.z	RA = one, two + 3, three + 4
+(PA)	br.sptk	.L1
+	;;
diff --git a/gas/testsuite/gas/ia64/global.d b/gas/testsuite/gas/ia64/global.d
index 47ac65f0560b..30783583be0e 100644
--- a/gas/testsuite/gas/ia64/global.d
+++ b/gas/testsuite/gas/ia64/global.d
@@ -1,4 +1,4 @@
-#readelf: --sym
+#readelf: --syms
 #name: ia64 global label
 
 Symbol table '.symtab' contains 5 entries:
diff --git a/gas/testsuite/gas/ia64/group-1.d b/gas/testsuite/gas/ia64/group-1.d
new file mode 100644
index 000000000000..fe2334767c7c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/group-1.d
@@ -0,0 +1,34 @@
+#readelf: -Sg
+#name: ia64 group
+
+There are 9 section headers, starting at offset 0x98:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0000000000000000  00000000
+       0000000000000000  0000000000000000           0     0     0
+  \[ 1\] \._foo             GROUP            0000000000000000  00000040
+       0000000000000008  0000000000000004           7     6     4
+  \[ 2\] \.text             PROGBITS         0000000000000000  00000050
+       0000000000000000  0000000000000000  AX       0     0     16
+  \[ 3\] \.data             PROGBITS         0000000000000000  00000050
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 4\] \.bss              NOBITS           0000000000000000  00000050
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 5\] \.text             PROGBITS         0000000000000000  00000050
+       0000000000000010  0000000000000000 AXG       0     0     16
+  \[ 6\] \.shstrtab         STRTAB           0000000000000000  00000060
+       0000000000000032  0000000000000000           0     0     1
+  \[ 7\] \.symtab           SYMTAB           0000000000000000  000002d8
+       00000000000000a8  0000000000000018           8     7     8
+  \[ 8\] \.strtab           STRTAB           0000000000000000  00000380
+       0000000000000006  0000000000000000           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+COMDAT group section \[    1\] `\._foo' \[\._foo\] contains 1 sections:
+   \[Index\]    Name
+   \[    5\]   \.text
diff --git a/gas/testsuite/gas/ia64/group-1.s b/gas/testsuite/gas/ia64/group-1.s
new file mode 100644
index 000000000000..ed7f64f93156
--- /dev/null
+++ b/gas/testsuite/gas/ia64/group-1.s
@@ -0,0 +1,10 @@
+	.section	.text,"axG",@progbits,._foo,comdat
+	.proc _foo#
+_foo:
+	(p6) br.cond.dptk .L37
+.L48:
+.L70:
+.L37:
+.L77:
+.L74:
+	.endp _foo#
diff --git a/gas/testsuite/gas/ia64/group-2.d b/gas/testsuite/gas/ia64/group-2.d
new file mode 100644
index 000000000000..1c938952f0ce
--- /dev/null
+++ b/gas/testsuite/gas/ia64/group-2.d
@@ -0,0 +1,43 @@
+#readelf: -Sg
+#as: -x
+#name: ia64 unwind group
+
+There are 12 section headers, starting at offset 0x100:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0000000000000000  00000000
+       0000000000000000  0000000000000000           0     0     0
+  \[ 1\] \.group            GROUP            0000000000000000  00000040
+       0000000000000010  0000000000000004          10     5     4
+  \[ 2\] \.text             PROGBITS         0000000000000000  00000050
+       0000000000000000  0000000000000000  AX       0     0     16
+  \[ 3\] \.data             PROGBITS         0000000000000000  00000050
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 4\] \.bss              NOBITS           0000000000000000  00000050
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 5\] \.gnu\.linkonce\.t\.f PROGBITS         0000000000000000  00000050
+       0000000000000000  0000000000000000 AXG       0     0     16
+  \[ 6\] \.gnu\.linkonce\.ia6 PROGBITS         0000000000000000  00000050
+       0000000000000010  0000000000000000  AG       0     0     8
+  \[ 7\] \.gnu\.linkonce\.ia6 IA_64_UNWIND     0000000000000000  00000060
+       0000000000000018  0000000000000000 ALG       5     5     8
+  \[ 8\] \.rela\.gnu\.linkonc RELA             0000000000000000  000004e0
+       0000000000000048  0000000000000018          10     7     8
+  \[ 9\] \.shstrtab         STRTAB           0000000000000000  00000078
+       0000000000000081  0000000000000000           0     0     1
+  \[10\] \.symtab           SYMTAB           0000000000000000  00000400
+       00000000000000d8  0000000000000018          11     9     8
+  \[11\] \.strtab           STRTAB           0000000000000000  000004d8
+       0000000000000005  0000000000000000           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+COMDAT group section \[    1\] `\.group' \[foo\] contains 3 sections:
+   \[Index\]    Name
+   \[    5\]   \.gnu\.linkonce\.t\.foo
+   \[    6\]   \.gnu\.linkonce\.ia64unwi\.foo
+   \[    7\]   \.gnu\.linkonce\.ia64unw\.foo
diff --git a/gas/testsuite/gas/ia64/group-2.s b/gas/testsuite/gas/ia64/group-2.s
new file mode 100644
index 000000000000..6b6b9fc0edff
--- /dev/null
+++ b/gas/testsuite/gas/ia64/group-2.s
@@ -0,0 +1,6 @@
+	.section	.gnu.linkonce.t.foo,"axG",@progbits,foo,comdat
+	.proc foo#
+foo:
+	.prologue 12, r33
+	;;
+	.endp foo#
diff --git a/gas/testsuite/gas/ia64/hint.b-err.l b/gas/testsuite/gas/ia64/hint.b-err.l
new file mode 100644
index 000000000000..86d8b5e52bd7
--- /dev/null
+++ b/gas/testsuite/gas/ia64/hint.b-err.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:1: Error: hint.b shouldn't be used
+.*:2: Error: hint.b shouldn't be used
diff --git a/gas/testsuite/gas/ia64/hint.b-err.s b/gas/testsuite/gas/ia64/hint.b-err.s
new file mode 100644
index 000000000000..75f7a6522fb7
--- /dev/null
+++ b/gas/testsuite/gas/ia64/hint.b-err.s
@@ -0,0 +1,2 @@
+	hint.b	@pause
+	hint.b	0x1ffff
diff --git a/gas/testsuite/gas/ia64/hint.b-warn.l b/gas/testsuite/gas/ia64/hint.b-warn.l
new file mode 100644
index 000000000000..1c5f0be537c3
--- /dev/null
+++ b/gas/testsuite/gas/ia64/hint.b-warn.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:1: Warning: hint.b may be treated as nop
+.*:2: Warning: hint.b may be treated as nop
diff --git a/gas/testsuite/gas/ia64/hint.b-warn.s b/gas/testsuite/gas/ia64/hint.b-warn.s
new file mode 100644
index 000000000000..75f7a6522fb7
--- /dev/null
+++ b/gas/testsuite/gas/ia64/hint.b-warn.s
@@ -0,0 +1,2 @@
+	hint.b	@pause
+	hint.b	0x1ffff
diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp
index 9990d27a5e98..f68c107f528b 100644
--- a/gas/testsuite/gas/ia64/ia64.exp
+++ b/gas/testsuite/gas/ia64/ia64.exp
@@ -24,6 +24,11 @@ if [istarget "ia64-*"] then {
     run_dump_test "opc-i"
     run_dump_test "opc-m"
     run_dump_test "opc-x"
+    run_dump_test "pseudo"
+    run_dump_test "nop_x"
+    run_dump_test "mov-ar"
+    run_list_test "operands" ""
+    run_list_test "reg-err" ""
 
     run_list_test "dv-raw-err" ""
     run_list_test "dv-waw-err" ""
@@ -33,15 +38,31 @@ if [istarget "ia64-*"] then {
     run_dump_test "dv-branch"
     run_dump_test "dv-imply"
     run_dump_test "dv-mutex"
+    gas_test "pred-rel.s" "" "" ".pred.rel alternative forms"
     run_dump_test "dv-safe"
     run_dump_test "dv-srlz"
+    run_list_test "regval" ""
     run_dump_test "tls"
     run_dump_test "ldxmov-1"
     run_list_test "ldxmov-2" ""
     run_dump_test "ltoff22x-1"
-    
+    run_dump_test "ltoff22x-2"
+    run_dump_test "ltoff22x-3"
+    run_dump_test "ltoff22x-4"
+    run_dump_test "ltoff22x-5"
+
+    run_dump_test "nostkreg"
+    run_list_test "invalid-ar" ""
+
+    run_dump_test "nostkreg"
+    run_list_test "invalid-ar" ""
+
     run_dump_test "dependency-1"
 
+    run_dump_test "reloc"
+    run_list_test "reloc-bad" ""
+    run_dump_test "pcrel"
+
     run_dump_test "real"
     run_dump_test "align"
     run_dump_test "order"
@@ -50,9 +71,35 @@ if [istarget "ia64-*"] then {
 	run_dump_test "secname-ilp32"
 	run_dump_test "unwind-ilp32"
 	run_dump_test "alias-ilp32"
+	run_dump_test "xdata-ilp32"
+	run_dump_test "reloc-uw-ilp32"
     } else {
 	run_dump_test "secname"
 	run_dump_test "unwind"
 	run_dump_test "alias"
+	run_dump_test "xdata"
+	run_dump_test "reloc-uw"
+	run_dump_test "group-1"
+	run_dump_test "group-2"
     }
+
+    run_list_test "alloc" ""
+    run_dump_test "bundling"
+    run_dump_test "forward"
+    run_list_test "index" ""
+    run_list_test "label" ""
+    run_list_test "last" ""
+    run_list_test "no-fit" ""
+    run_list_test "pound" "-al"
+    run_list_test "proc" "-munwind-check=error"
+    run_list_test "radix" ""
+    run_list_test "rotX" ""
+    run_list_test "slot2" ""
+    run_dump_test "strange"
+    run_list_test "unwind-bad" ""
+    run_list_test "unwind-err" "-munwind-check=error"
+    run_dump_test "unwind-ok"
+    run_dump_test "operand-or"
+    run_list_test "hint.b-err" ""
+    run_list_test "hint.b-warn" "-mhint.b=warning"
 }
diff --git a/gas/testsuite/gas/ia64/index.l b/gas/testsuite/gas/ia64/index.l
new file mode 100644
index 000000000000..41af9fdec2f1
--- /dev/null
+++ b/gas/testsuite/gas/ia64/index.l
@@ -0,0 +1,42 @@
+.*: Assembler messages:
+.*.s:6: Error: [Ii]ndex must be a general register
+.*.s:7: Error: [Ii]ndex must be a general register
+.*.s:8: Error: [Ii]ndex must be a general register
+.*.s:9: Error: [Ii]ndex must be a general register
+.*.s:13: Error: [Ii]ndirect register index must be a general register
+.*.s:14: Error: [Ii]ndirect register index must be a general register
+.*.s:15: Error: [Ii]ndirect register index must be a general register
+.*.s:16: Error: [Ii]ndirect register index must be a general register
+.*.s:20: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:21: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:22: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:23: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:24: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:25: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:27: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:28: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:29: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:30: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:31: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:32: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:37: Error: [Rr]otating register index must be a non-negative constant
+.*.s:39: Error: [Ii]ndex out of range 0\.\.[[:digit:]]+
+.*.s:40: Error: [Rr]otating register index must be a non-negative constant
+.*.s:41: Error: [Rr]otating register index must be a non-negative constant
+.*.s:42: Error: [Rr]otating register index must be a non-negative constant
+.*.s:44: Error: [Ii]ndirect register index must be a general register
+.*.s:45: Error: [Ii]ndirect register index must be a general register
+.*.s:46: Error: [Ii]ndirect register index must be a general register
+.*.s:47: Error: [Ii]ndirect register index must be a general register
+.*.s:51: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:52: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:53: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:54: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:55: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:56: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:58: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:59: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:60: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:61: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:62: Error: [Ii]ndex can only be applied to rotating or indirect registers
+.*.s:63: Error: [Ii]ndex can only be applied to rotating or indirect registers
diff --git a/gas/testsuite/gas/ia64/index.s b/gas/testsuite/gas/ia64/index.s
new file mode 100644
index 000000000000..0a5d9f1ad1e6
--- /dev/null
+++ b/gas/testsuite/gas/ia64/index.s
@@ -0,0 +1,63 @@
+z == zero
+zero == r0
+
+.text
+_start:
+	ld8	r2 = [ar.lc]
+	ld8	r3 = [1]
+	ld8	r4 = [-1]
+	ld8	r5 = [xyz]
+	ld8	r6 = [zero]
+	ld8	r7 = [z]
+
+	mov	r2 = cpuid[ar.lc]
+	mov	r3 = cpuid[1]
+	mov	r4 = cpuid[-1]
+	mov	r5 = cpuid[xyz]
+	mov	r6 = cpuid[zero]
+	mov	r7 = cpuid[z]
+
+	mov	r2 = b0[ar.lc]
+	mov	r3 = b0[1]
+	mov	r4 = b0[-1]
+	mov	r5 = b0[xyz]
+	mov	r6 = b0[zero]
+	mov	r7 = b0[z]
+
+	mov	r2 = xyz[ar.lc]
+	mov	r3 = xyz[1]
+	mov	r4 = xyz[-1]
+	mov	r5 = xyz[xyz]
+	mov	r6 = xyz[zero]
+	mov	r7 = xyz[z]
+
+.regstk 0, 8, 0, 8
+.rotr reg[8]
+
+	mov	r2 = reg[ar.lc]
+	mov	r3 = reg[1]
+	mov	r4 = reg[-1]
+	mov	r5 = reg[xyz]
+	mov	r6 = reg[zero]
+	mov	r7 = reg[z]
+
+	mov	r2 = cpuid[ar.lc]
+	mov	r3 = cpuid[1]
+	mov	r4 = cpuid[-1]
+	mov	r5 = cpuid[xyz]
+	mov	r6 = cpuid[zero]
+	mov	r7 = cpuid[z]
+
+	mov	r2 = b0[ar.lc]
+	mov	r3 = b0[1]
+	mov	r4 = b0[-1]
+	mov	r5 = b0[xyz]
+	mov	r6 = b0[zero]
+	mov	r7 = b0[z]
+
+	mov	r2 = xyz[ar.lc]
+	mov	r3 = xyz[1]
+	mov	r4 = xyz[-1]
+	mov	r5 = xyz[xyz]
+	mov	r6 = xyz[zero]
+	mov	r7 = xyz[z]
diff --git a/gas/testsuite/gas/ia64/invalid-ar.l b/gas/testsuite/gas/ia64/invalid-ar.l
new file mode 100644
index 000000000000..2507e2ba90a0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/invalid-ar.l
@@ -0,0 +1,124 @@
+.*: Assembler messages:
+.*:2: Error: AR 0 can only be accessed by M-unit
+.*:3: Error: AR 1 can only be accessed by M-unit
+.*:4: Error: AR 2 can only be accessed by M-unit
+.*:5: Error: AR 3 can only be accessed by M-unit
+.*:6: Error: AR 4 can only be accessed by M-unit
+.*:7: Error: AR 5 can only be accessed by M-unit
+.*:8: Error: AR 6 can only be accessed by M-unit
+.*:9: Error: AR 7 can only be accessed by M-unit
+.*:10: Error: AR 8 can only be accessed by M-unit
+.*:11: Error: AR 9 can only be accessed by M-unit
+.*:12: Error: AR 10 can only be accessed by M-unit
+.*:13: Error: AR 11 can only be accessed by M-unit
+.*:14: Error: AR 12 can only be accessed by M-unit
+.*:15: Error: AR 13 can only be accessed by M-unit
+.*:16: Error: AR 14 can only be accessed by M-unit
+.*:17: Error: AR 15 can only be accessed by M-unit
+.*:18: Error: AR 16 can only be accessed by M-unit
+.*:19: Error: AR 17 can only be accessed by M-unit
+.*:20: Error: AR 18 can only be accessed by M-unit
+.*:21: Error: AR 19 can only be accessed by M-unit
+.*:22: Error: AR 20 can only be accessed by M-unit
+.*:23: Error: AR 21 can only be accessed by M-unit
+.*:24: Error: AR 22 can only be accessed by M-unit
+.*:25: Error: AR 23 can only be accessed by M-unit
+.*:26: Error: AR 24 can only be accessed by M-unit
+.*:27: Error: AR 25 can only be accessed by M-unit
+.*:28: Error: AR 26 can only be accessed by M-unit
+.*:29: Error: AR 27 can only be accessed by M-unit
+.*:30: Error: AR 28 can only be accessed by M-unit
+.*:31: Error: AR 29 can only be accessed by M-unit
+.*:32: Error: AR 30 can only be accessed by M-unit
+.*:33: Error: AR 31 can only be accessed by M-unit
+.*:34: Error: AR 32 can only be accessed by M-unit
+.*:35: Error: AR 33 can only be accessed by M-unit
+.*:36: Error: AR 34 can only be accessed by M-unit
+.*:37: Error: AR 35 can only be accessed by M-unit
+.*:38: Error: AR 36 can only be accessed by M-unit
+.*:39: Error: AR 37 can only be accessed by M-unit
+.*:40: Error: AR 38 can only be accessed by M-unit
+.*:41: Error: AR 39 can only be accessed by M-unit
+.*:42: Error: AR 40 can only be accessed by M-unit
+.*:43: Error: AR 41 can only be accessed by M-unit
+.*:44: Error: AR 42 can only be accessed by M-unit
+.*:45: Error: AR 43 can only be accessed by M-unit
+.*:46: Error: AR 44 can only be accessed by M-unit
+.*:47: Error: AR 45 can only be accessed by M-unit
+.*:48: Error: AR 46 can only be accessed by M-unit
+.*:49: Error: AR 47 can only be accessed by M-unit
+.*:54: Error: AR 64 can only be accessed by I-unit
+.*:55: Error: AR 65 can only be accessed by I-unit
+.*:56: Error: AR 66 can only be accessed by I-unit
+.*:57: Error: AR 67 can only be accessed by I-unit
+.*:58: Error: AR 68 can only be accessed by I-unit
+.*:59: Error: AR 69 can only be accessed by I-unit
+.*:60: Error: AR 70 can only be accessed by I-unit
+.*:61: Error: AR 71 can only be accessed by I-unit
+.*:62: Error: AR 72 can only be accessed by I-unit
+.*:63: Error: AR 73 can only be accessed by I-unit
+.*:64: Error: AR 74 can only be accessed by I-unit
+.*:65: Error: AR 75 can only be accessed by I-unit
+.*:66: Error: AR 76 can only be accessed by I-unit
+.*:67: Error: AR 77 can only be accessed by I-unit
+.*:68: Error: AR 78 can only be accessed by I-unit
+.*:69: Error: AR 79 can only be accessed by I-unit
+.*:70: Error: AR 80 can only be accessed by I-unit
+.*:71: Error: AR 81 can only be accessed by I-unit
+.*:72: Error: AR 82 can only be accessed by I-unit
+.*:73: Error: AR 83 can only be accessed by I-unit
+.*:74: Error: AR 84 can only be accessed by I-unit
+.*:75: Error: AR 85 can only be accessed by I-unit
+.*:76: Error: AR 86 can only be accessed by I-unit
+.*:77: Error: AR 87 can only be accessed by I-unit
+.*:78: Error: AR 88 can only be accessed by I-unit
+.*:79: Error: AR 89 can only be accessed by I-unit
+.*:80: Error: AR 90 can only be accessed by I-unit
+.*:81: Error: AR 91 can only be accessed by I-unit
+.*:82: Error: AR 92 can only be accessed by I-unit
+.*:83: Error: AR 93 can only be accessed by I-unit
+.*:84: Error: AR 94 can only be accessed by I-unit
+.*:85: Error: AR 95 can only be accessed by I-unit
+.*:86: Error: AR 96 can only be accessed by I-unit
+.*:87: Error: AR 97 can only be accessed by I-unit
+.*:88: Error: AR 98 can only be accessed by I-unit
+.*:89: Error: AR 99 can only be accessed by I-unit
+.*:90: Error: AR 100 can only be accessed by I-unit
+.*:91: Error: AR 101 can only be accessed by I-unit
+.*:92: Error: AR 102 can only be accessed by I-unit
+.*:93: Error: AR 103 can only be accessed by I-unit
+.*:94: Error: AR 104 can only be accessed by I-unit
+.*:95: Error: AR 105 can only be accessed by I-unit
+.*:96: Error: AR 106 can only be accessed by I-unit
+.*:97: Error: AR 107 can only be accessed by I-unit
+.*:98: Error: AR 108 can only be accessed by I-unit
+.*:99: Error: AR 109 can only be accessed by I-unit
+.*:100: Error: AR 110 can only be accessed by I-unit
+.*:101: Error: AR 111 can only be accessed by I-unit
+.*:106: Error: AR 0 can only be accessed by M-unit
+.*:107: Error: AR 1 can only be accessed by M-unit
+.*:108: Error: AR 2 can only be accessed by M-unit
+.*:109: Error: AR 3 can only be accessed by M-unit
+.*:110: Error: AR 4 can only be accessed by M-unit
+.*:111: Error: AR 5 can only be accessed by M-unit
+.*:112: Error: AR 6 can only be accessed by M-unit
+.*:113: Error: AR 7 can only be accessed by M-unit
+.*:114: Error: AR 16 can only be accessed by M-unit
+.*:115: Error: AR 17 can only be accessed by M-unit
+.*:116: Error: AR 18 can only be accessed by M-unit
+.*:117: Error: AR 19 can only be accessed by M-unit
+.*:118: Error: AR 21 can only be accessed by M-unit
+.*:119: Error: AR 24 can only be accessed by M-unit
+.*:120: Error: AR 25 can only be accessed by M-unit
+.*:121: Error: AR 26 can only be accessed by M-unit
+.*:122: Error: AR 27 can only be accessed by M-unit
+.*:123: Error: AR 28 can only be accessed by M-unit
+.*:124: Error: AR 29 can only be accessed by M-unit
+.*:125: Error: AR 30 can only be accessed by M-unit
+.*:126: Error: AR 32 can only be accessed by M-unit
+.*:127: Error: AR 36 can only be accessed by M-unit
+.*:128: Error: AR 40 can only be accessed by M-unit
+.*:129: Error: AR 44 can only be accessed by M-unit
+.*:132: Error: AR 64 can only be accessed by I-unit
+.*:133: Error: AR 65 can only be accessed by I-unit
+.*:134: Error: AR 66 can only be accessed by I-unit
diff --git a/gas/testsuite/gas/ia64/invalid-ar.s b/gas/testsuite/gas/ia64/invalid-ar.s
new file mode 100644
index 000000000000..79c264164aa6
--- /dev/null
+++ b/gas/testsuite/gas/ia64/invalid-ar.s
@@ -0,0 +1,134 @@
+// AR 0 to AR 47 can be accessed only by M unit.
+	mov.i r1 = ar0
+	mov.i r1 = ar1
+	mov.i r1 = ar2
+	mov.i r1 = ar3
+	mov.i r1 = ar4
+	mov.i r1 = ar5
+	mov.i r1 = ar6
+	mov.i r1 = ar7
+	mov.i r1 = ar8
+	mov.i r1 = ar9
+	mov.i r1 = ar10
+	mov.i r1 = ar11
+	mov.i r1 = ar12
+	mov.i r1 = ar13
+	mov.i r1 = ar14
+	mov.i r1 = ar15
+	mov.i r1 = ar16
+	mov.i r1 = ar17
+	mov.i r1 = ar18
+	mov.i r1 = ar19
+	mov.i r1 = ar20
+	mov.i r1 = ar21
+	mov.i r1 = ar22
+	mov.i r1 = ar23
+	mov.i r1 = ar24
+	mov.i r1 = ar25
+	mov.i r1 = ar26
+	mov.i r1 = ar27
+	mov.i r1 = ar28
+	mov.i r1 = ar29
+	mov.i r1 = ar30
+	mov.i r1 = ar31
+	mov.i r1 = ar32
+	mov.i r1 = ar33
+	mov.i r1 = ar34
+	mov.i r1 = ar35
+	mov.i r1 = ar36
+	mov.i r1 = ar37
+	mov.i r1 = ar38
+	mov.i r1 = ar39
+	mov.i r1 = ar40
+	mov.i r1 = ar41
+	mov.i r1 = ar42
+	mov.i r1 = ar43
+	mov.i r1 = ar44
+	mov.i r1 = ar45
+	mov.i r1 = ar46
+	mov.i r1 = ar47
+
+// AR 48 to 63 can be accessed by I or M units.
+
+// AR 64 to AR 111 can be accessed only by I unit.
+	mov.m r1 = ar64
+	mov.m r1 = ar65
+	mov.m r1 = ar66
+	mov.m r1 = ar67
+	mov.m r1 = ar68
+	mov.m r1 = ar69
+	mov.m r1 = ar70
+	mov.m r1 = ar71
+	mov.m r1 = ar72
+	mov.m r1 = ar73
+	mov.m r1 = ar74
+	mov.m r1 = ar75
+	mov.m r1 = ar76
+	mov.m r1 = ar77
+	mov.m r1 = ar78
+	mov.m r1 = ar79
+	mov.m r1 = ar80
+	mov.m r1 = ar81
+	mov.m r1 = ar82
+	mov.m r1 = ar83
+	mov.m r1 = ar84
+	mov.m r1 = ar85
+	mov.m r1 = ar86
+	mov.m r1 = ar87
+	mov.m r1 = ar88
+	mov.m r1 = ar89
+	mov.m r1 = ar90
+	mov.m r1 = ar91
+	mov.m r1 = ar92
+	mov.m r1 = ar93
+	mov.m r1 = ar94
+	mov.m r1 = ar95
+	mov.m r1 = ar96
+	mov.m r1 = ar97
+	mov.m r1 = ar98
+	mov.m r1 = ar99
+	mov.m r1 = ar100
+	mov.m r1 = ar101
+	mov.m r1 = ar102
+	mov.m r1 = ar103
+	mov.m r1 = ar104
+	mov.m r1 = ar105
+	mov.m r1 = ar106
+	mov.m r1 = ar107
+	mov.m r1 = ar108
+	mov.m r1 = ar109
+	mov.m r1 = ar110
+	mov.m r1 = ar111
+
+// AR 112 to 127 can be accessed by I or M units.
+
+// AR K0 to AR ITC can be accessed only by M unit.
+	mov.i r1 = ar.k0
+	mov.i r1 = ar.k1
+	mov.i r1 = ar.k2
+	mov.i r1 = ar.k3
+	mov.i r1 = ar.k4
+	mov.i r1 = ar.k5
+	mov.i r1 = ar.k6
+	mov.i r1 = ar.k7
+	mov.i r1 = ar.rsc
+	mov.i r1 = ar.bsp
+	mov.i r1 = ar.bspstore
+	mov.i r1 = ar.rnat
+	mov.i r1 = ar.fcr
+	mov.i r1 = ar.eflag
+	mov.i r1 = ar.csd
+	mov.i r1 = ar.ssd
+	mov.i r1 = ar.cflg
+	mov.i r1 = ar.fsr
+	mov.i r1 = ar.fir
+	mov.i r1 = ar.fdr
+	mov.i r1 = ar.ccv
+	mov.i r1 = ar.unat
+	mov.i r1 = ar.fpsr
+	mov.i r1 = ar.itc
+
+// AR PFS, LC and EC can be accessed only by I unit.
+	mov.m r1 = ar.pfs
+	mov.m r1 = ar.lc
+	mov.m r1 = ar.ec
diff --git a/gas/testsuite/gas/ia64/label.l b/gas/testsuite/gas/ia64/label.l
new file mode 100644
index 000000000000..89eba5926e7c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/label.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:12: Error: Label must be first in a bundle
+.*:19: Error: Label must be first in a bundle
diff --git a/gas/testsuite/gas/ia64/label.s b/gas/testsuite/gas/ia64/label.s
new file mode 100644
index 000000000000..dbe5c38ec95c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/label.s
@@ -0,0 +1,26 @@
+.explicit
+start:
+{.mii
+label0:
+	nop	0
+	nop	0
+	nop	0
+}
+{.mii
+	nop	0
+label1:
+	nop	0
+	nop	0
+}
+{.mii
+	nop	0
+	nop	0
+label2:
+	nop	0
+}
+{.mii
+	nop	0
+	nop	0
+	nop	0
+label3:
+}
diff --git a/gas/testsuite/gas/ia64/last.l b/gas/testsuite/gas/ia64/last.l
new file mode 100644
index 000000000000..946b4d2e080f
--- /dev/null
+++ b/gas/testsuite/gas/ia64/last.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: .* must be last in instruction group
+.*:10: Error: .* must be last in instruction group
diff --git a/gas/testsuite/gas/ia64/last.s b/gas/testsuite/gas/ia64/last.s
new file mode 100644
index 000000000000..d7b0de0b00a9
--- /dev/null
+++ b/gas/testsuite/gas/ia64/last.s
@@ -0,0 +1,12 @@
+.explicit
+_start:
+{.mib
+	itc.d	r0
+}	;;
+{.mib
+	cover
+}	;;
+{.mbb
+	cover
+	nop	0
+}	;;
diff --git a/gas/testsuite/gas/ia64/ldxmov-1.d b/gas/testsuite/gas/ia64/ldxmov-1.d
index 93dd2dfe30b7..0676d10cdd82 100644
--- a/gas/testsuite/gas/ia64/ldxmov-1.d
+++ b/gas/testsuite/gas/ia64/ldxmov-1.d
@@ -1,3 +1,4 @@
+#as: -mtune=itanium1
 #objdump: -dr
 #name: ia64 ldxmov-1
 
diff --git a/gas/testsuite/gas/ia64/ltoff22x-2.d b/gas/testsuite/gas/ia64/ltoff22x-2.d
new file mode 100644
index 000000000000..8a2dbda120db
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-2.d
@@ -0,0 +1,11 @@
+# objdump: -r
+# name: ia64 ltoff22x-2
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE 
+0+000 LTOFF22X          foo
+0+010 LDXMOV            foo
+
+
diff --git a/gas/testsuite/gas/ia64/ltoff22x-2.s b/gas/testsuite/gas/ia64/ltoff22x-2.s
new file mode 100644
index 000000000000..cbd27f2819c6
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-2.s
@@ -0,0 +1,13 @@
+	.global foo#
+	foo# = bar#
+	.global bar#
+	.data
+bar:
+	data4 0
+	.text
+	addl	r3 = @ltoffx(foo#), gp
+	nop.i	0
+	nop.i	0
+	ld8.mov r3 = [r3], foo#
+	nop.i	0
+	nop.i	0
diff --git a/gas/testsuite/gas/ia64/ltoff22x-3.d b/gas/testsuite/gas/ia64/ltoff22x-3.d
new file mode 100644
index 000000000000..724cc59d23b4
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-3.d
@@ -0,0 +1,11 @@
+# objdump: -r
+# name: ia64 ltoff22x-3
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE 
+0+000 LTOFF22X          foo
+0+010 LDXMOV            foo
+
+
diff --git a/gas/testsuite/gas/ia64/ltoff22x-3.s b/gas/testsuite/gas/ia64/ltoff22x-3.s
new file mode 100644
index 000000000000..f0ebd10258e1
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-3.s
@@ -0,0 +1,13 @@
+	.global bar#
+	.data
+bar:
+	data4 0
+	.global foo#
+	foo# = bar#
+	.text
+	addl	r3 = @ltoffx(foo#), gp
+	nop.i	0
+	nop.i	0
+	ld8.mov r3 = [r3], foo#
+	nop.i	0
+	nop.i	0
diff --git a/gas/testsuite/gas/ia64/ltoff22x-4.d b/gas/testsuite/gas/ia64/ltoff22x-4.d
new file mode 100644
index 000000000000..feedbae63cbe
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-4.d
@@ -0,0 +1,11 @@
+# objdump: -r
+# name: ia64 ltoff22x-4
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE 
+0+000 LTOFF22X          foo
+0+010 LDXMOV            foo
+
+
diff --git a/gas/testsuite/gas/ia64/ltoff22x-4.s b/gas/testsuite/gas/ia64/ltoff22x-4.s
new file mode 100644
index 000000000000..fa43f34682d7
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-4.s
@@ -0,0 +1,13 @@
+	.text
+	addl	r3 = @ltoffx(foo#), gp
+	nop.i	0
+	nop.i	0
+	ld8.mov r3 = [r3], foo#
+	nop.i	0
+	nop.i	0
+	.global foo#
+	foo# = bar#
+	.global bar#
+	.data
+bar:
+	data4 0
diff --git a/gas/testsuite/gas/ia64/ltoff22x-5.d b/gas/testsuite/gas/ia64/ltoff22x-5.d
new file mode 100644
index 000000000000..e6081b45ce2d
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-5.d
@@ -0,0 +1,11 @@
+# objdump: -r
+# name: ia64 ltoff22x-5
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE 
+0+000 LTOFF22X          foo
+0+010 LDXMOV            foo
+
+
diff --git a/gas/testsuite/gas/ia64/ltoff22x-5.s b/gas/testsuite/gas/ia64/ltoff22x-5.s
new file mode 100644
index 000000000000..a6c5137b96f7
--- /dev/null
+++ b/gas/testsuite/gas/ia64/ltoff22x-5.s
@@ -0,0 +1,13 @@
+	.text
+	addl	r3 = @ltoffx(foo#), gp
+	nop.i	0
+	nop.i	0
+	ld8.mov r3 = [r3], foo#
+	nop.i	0
+	nop.i	0
+	.global bar#
+	.data
+bar:
+	data4 0
+	.global foo#
+	foo# = bar#
diff --git a/gas/testsuite/gas/ia64/mov-ar.d b/gas/testsuite/gas/ia64/mov-ar.d
new file mode 100644
index 000000000000..ec7cb61548bb
--- /dev/null
+++ b/gas/testsuite/gas/ia64/mov-ar.d
@@ -0,0 +1,26 @@
+# objdump: -d
+# name: ia64 app reg moves
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar.k0=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar127=r0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar47=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar112=r0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar48=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar111=r0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar63=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar.pfs=r0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar112=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar63=r0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MFI\][[:space:]]+mov\.m ar127=r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop\.f 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+mov\.i ar48=r0;;
diff --git a/gas/testsuite/gas/ia64/mov-ar.s b/gas/testsuite/gas/ia64/mov-ar.s
new file mode 100644
index 000000000000..79780d940bcf
--- /dev/null
+++ b/gas/testsuite/gas/ia64/mov-ar.s
@@ -0,0 +1,21 @@
+.explicit
+_start:
+{.mfi
+	mov	ar0 = r0
+	mov	ar127 = r0
+} ;; {.mfi
+	mov	ar47 = r0
+	mov	ar112 = r0
+} ;; {.mfi
+	mov	ar48 = r0
+	mov	ar111 = r0
+} ;; {.mfi
+	mov	ar63 = r0
+	mov	ar64 = r0
+} ;; {.mfi
+	mov	ar112 = r0
+	mov	ar63 = r0
+} ;; {.mfi
+	mov	ar127 = r0
+	mov	ar48 = r0
+} ;;
diff --git a/gas/testsuite/gas/ia64/no-fit.l b/gas/testsuite/gas/ia64/no-fit.l
new file mode 100644
index 000000000000..1dec89c8673f
--- /dev/null
+++ b/gas/testsuite/gas/ia64/no-fit.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:5: Error: .nop\.i.[[:space:]]+[^23]*[[:space:]]+MFB[[:space:]]+.*
+.*:8: Error: .nop\.f.[[:space:]]+[^23]*[[:space:]]+MLX[[:space:]]+.*
+.*:12: Error: .nop\.i.[[:space:]]+.*[[:space:]]+2[[:space:]]+.*[[:space:]]+3[[:space:]]+.*[[:space:]]+MFB[[:space:]]+.*
+.*:17: Error: .nop\.i.[[:space:]]+[^2]*[[:space:]]+3[[:space:]]+.*[[:space:]]+MFB[[:space:]]+.*
+.*:21: Error: .nop\.f.[[:space:]]+.*[[:space:]]+X[[:space:]]+.*[[:space:]]+MLX[[:space:]]+.*
+.*:27: Error: .nop.[[:space:]]+[^23M]*
+.*:32: Error: .nop.[[:space:]]+[^23M]*
diff --git a/gas/testsuite/gas/ia64/no-fit.s b/gas/testsuite/gas/ia64/no-fit.s
new file mode 100644
index 000000000000..dc992a5ef8e2
--- /dev/null
+++ b/gas/testsuite/gas/ia64/no-fit.s
@@ -0,0 +1,33 @@
+.explicit
+.text
+_start:
+{.mfb
+	nop.i	0
+}
+{.mlx
+	nop.f	0
+}
+{.mfb
+	nop.m	0
+	nop.i	0
+}
+{.mfb
+	nop.m	0
+	nop.f	0
+	nop.i	0
+}
+{.mlx
+	nop.m	0
+	nop.f	0
+}
+{.mfb
+	nop	0
+	nop	0
+	nop	0
+	nop	0
+}
+{.mlx
+	nop	0
+	nop	0
+	nop	0
+}
diff --git a/gas/testsuite/gas/ia64/nop_x.d b/gas/testsuite/gas/ia64/nop_x.d
new file mode 100644
index 000000000000..add141488571
--- /dev/null
+++ b/gas/testsuite/gas/ia64/nop_x.d
@@ -0,0 +1,11 @@
+# objdump: -d
+# name: ia64 nop.x pseudo
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+\[MLX][[:space:]]+nop.m 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+nop.x 0x0;;
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+
diff --git a/gas/testsuite/gas/ia64/nop_x.s b/gas/testsuite/gas/ia64/nop_x.s
new file mode 100644
index 000000000000..61265b39fd7c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/nop_x.s
@@ -0,0 +1,6 @@
+.explicit
+_start:
+{.mlx
+	nop	0
+	nop	0
+} ;;
diff --git a/gas/testsuite/gas/ia64/nostkreg.d b/gas/testsuite/gas/ia64/nostkreg.d
new file mode 100644
index 000000000000..e1eee70b5971
--- /dev/null
+++ b/gas/testsuite/gas/ia64/nostkreg.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+#name: ia64 not stacked registers
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+000 <_start>:
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+\[M[IM]I\][[:space:]]+mov[[:space:]]+r5=0
+[[:space:]]+0:[[:space:]]+IMM22[[:space:]]+in00
+[[:space:]]+1:[[:space:]]+IMM22[[:space:]]+loc96
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r6=0
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r7=r32
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+\[M[IM]B\][[:space:]]+mov[[:space:]]+r8=r34
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+mov[[:space:]]+r9=r36
+[[:space:]]*[[:xdigit:]]+:[[:space:][:xdigit:]]+br\.ret\.sptk\.few[[:space:]]+(b0|rp);;
diff --git a/gas/testsuite/gas/ia64/nostkreg.s b/gas/testsuite/gas/ia64/nostkreg.s
new file mode 100644
index 000000000000..ecdba2bd0cce
--- /dev/null
+++ b/gas/testsuite/gas/ia64/nostkreg.s
@@ -0,0 +1,9 @@
+_start:
+	mov		r5 = in00
+	mov		r6 = loc96
+	.regstk 2, 6, 2, 8
+	.rotr in0I[2], loc1L[2], out2O[2]
+	mov		r7 = in0I[0]
+	mov		r8 = loc1L[0]
+	mov		r9 = out2O[0]
+	br.ret.sptk	rp
diff --git a/gas/testsuite/gas/ia64/opc-a.d b/gas/testsuite/gas/ia64/opc-a.d
index 44d7daf5324e..ed599bd266de 100644
--- a/gas/testsuite/gas/ia64/opc-a.d
+++ b/gas/testsuite/gas/ia64/opc-a.d
@@ -1,3 +1,4 @@
+# as: -xnone
 # objdump: -d
 # name: ia64 opc-a
 
diff --git a/gas/testsuite/gas/ia64/opc-b.d b/gas/testsuite/gas/ia64/opc-b.d
index 9dd987411532..4e483f8d2b4c 100644
--- a/gas/testsuite/gas/ia64/opc-b.d
+++ b/gas/testsuite/gas/ia64/opc-b.d
@@ -1,3 +1,4 @@
+#as: -xnone -mhint.b=ok -mtune=itanium1
 #objdump: -d
 #name: ia64 opc-b
 
@@ -1015,6 +1016,6 @@ Disassembly of section .text:
     2bf0:	16 f8 ff 0f 00 00 	\[BBB\]       break\.b 0x1ffff
     2bf6:	00 00 00 02 10 e0 	            hint\.b 0x0
     2bfc:	ff 3f 04 20       	            hint\.b 0x1ffff
-    2c00:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
-    2c06:	00 00 00 02 00 e0 	            nop\.f 0x0
-    2c0c:	ff 3f 00 20       	            nop\.b 0x1ffff;;
+    2c00:	17 f8 ff 0f 00 08 	\[BBB\]       nop\.b 0x1ffff
+    2c06:	00 00 00 30 00 00 	            vmsw.0
+    2c0c:	00 00 64 00       	            vmsw.1;;
diff --git a/gas/testsuite/gas/ia64/opc-b.s b/gas/testsuite/gas/ia64/opc-b.s
index e6881845dcba..565ab5474abf 100644
--- a/gas/testsuite/gas/ia64/opc-b.s
+++ b/gas/testsuite/gas/ia64/opc-b.s
@@ -831,3 +831,7 @@
 	hint.b	@pause
 	hint.b	0x1ffff
 	nop.b	0x1ffff
+
+	# instructions added by SDM2.2:
+	vmsw.0
+	vmsw.1
diff --git a/gas/testsuite/gas/ia64/opc-f.d b/gas/testsuite/gas/ia64/opc-f.d
index 4b39b9bf1f74..0dfa8811cd11 100644
--- a/gas/testsuite/gas/ia64/opc-f.d
+++ b/gas/testsuite/gas/ia64/opc-f.d
@@ -1,3 +1,4 @@
+# as: -xnone -mtune=itanium1
 # objdump: -d --disassemble-zeroes
 # name: ia64 opc-f
 
diff --git a/gas/testsuite/gas/ia64/opc-i.d b/gas/testsuite/gas/ia64/opc-i.d
index 3b99593072f4..175e07aac05d 100644
--- a/gas/testsuite/gas/ia64/opc-i.d
+++ b/gas/testsuite/gas/ia64/opc-i.d
@@ -1,3 +1,4 @@
+# as: -xnone -mtune=itanium1
 # objdump: -d
 # name: ia64 opc-i
 
@@ -258,6 +259,54 @@ Disassembly of section \.text:
  ab0:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
  ab6:	01 00 00 03 80 03 	      \(p07\) hint\.i 0x0
  abc:	00 00 06 00       	      \(p07\) hint\.i 0x0
- ac0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
- ac6:	00 00 00 02 80 e3 	            nop\.f 0x0
- acc:	ff ff 07 08       	      \(p07\) hint\.i 0x1fffff;;
+ ac0:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ ac6:	f1 ff ff 03 04 40 	      \(p07\) hint\.i 0x1fffff
+ acc:	f0 04 0c 50       	            tf\.z p2,p3=39
+ ad0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ ad6:	20 7c 02 06 28 40 	            tf\.z\.unc p2,p3=39
+ adc:	f0 04 0c 58       	            tf\.z\.and p2,p3=39
+ ae0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ ae6:	20 78 02 86 28 40 	            tf\.z\.or p2,p3=39
+ aec:	f0 04 0c 59       	            tf\.z\.or\.andcm p2,p3=39
+ af0:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ af6:	30 7c 02 84 28 60 	            tf\.nz\.or p3,p2=39
+ afc:	f8 04 08 58       	            tf\.nz\.and p3,p2=39
+ b00:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ b06:	30 7c 02 84 2c 60 	            tf\.nz\.or\.andcm p3,p2=39
+ b0c:	f0 04 08 50       	            tf\.z p3,p2=39
+ b10:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ b16:	30 7c 02 04 28 40 	            tf\.z\.unc p3,p2=39
+ b1c:	f8 04 0c 58       	            tf\.nz\.and p2,p3=39
+ b20:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ b26:	20 7c 02 86 28 40 	            tf\.nz\.or p2,p3=39
+ b2c:	f8 04 0c 59       	            tf\.nz\.or\.andcm p2,p3=39
+ b30:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ b36:	30 78 02 84 28 60 	            tf\.z\.or p3,p2=39
+ b3c:	f0 04 08 58       	            tf\.z\.and p3,p2=39
+ b40:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0
+ b46:	30 78 02 84 ac 43 	            tf\.z\.or\.andcm p3,p2=39
+ b4c:	f0 04 0c 50       	      \(p07\) tf\.z p2,p3=39
+ b50:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ b56:	21 7c 02 06 a8 43 	      \(p07\) tf\.z\.unc p2,p3=39
+ b5c:	f0 04 0c 58       	      \(p07\) tf\.z\.and p2,p3=39
+ b60:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ b66:	21 78 02 86 a8 43 	      \(p07\) tf\.z\.or p2,p3=39
+ b6c:	f0 04 0c 59       	      \(p07\) tf\.z\.or\.andcm p2,p3=39
+ b70:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ b76:	31 7c 02 84 a8 63 	      \(p07\) tf\.nz\.or p3,p2=39
+ b7c:	f8 04 08 58       	      \(p07\) tf\.nz\.and p3,p2=39
+ b80:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ b86:	31 7c 02 84 ac 63 	      \(p07\) tf\.nz\.or\.andcm p3,p2=39
+ b8c:	f0 04 08 50       	      \(p07\) tf\.z p3,p2=39
+ b90:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ b96:	31 7c 02 04 a8 43 	      \(p07\) tf\.z\.unc p3,p2=39
+ b9c:	f8 04 0c 58       	      \(p07\) tf\.nz\.and p2,p3=39
+ ba0:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ ba6:	21 7c 02 86 a8 43 	      \(p07\) tf\.nz\.or p2,p3=39
+ bac:	f8 04 0c 59       	      \(p07\) tf\.nz\.or\.andcm p2,p3=39
+ bb0:	00 00 00 00 01 c0 	\[MII\]       nop\.m 0x0
+ bb6:	31 78 02 84 a8 63 	      \(p07\) tf\.z\.or p3,p2=39
+ bbc:	f0 04 08 58       	      \(p07\) tf\.z\.and p3,p2=39
+ bc0:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
+ bc6:	00 00 00 02 80 63 	            nop\.f 0x0
+ bcc:	f0 04 08 59       	      \(p07\) tf\.z\.or\.andcm p3,p2=39;;
diff --git a/gas/testsuite/gas/ia64/opc-i.s b/gas/testsuite/gas/ia64/opc-i.s
index 09b820e92bd1..77ca9646f46a 100644
--- a/gas/testsuite/gas/ia64/opc-i.s
+++ b/gas/testsuite/gas/ia64/opc-i.s
@@ -220,3 +220,39 @@ _start:
  (p7)	hint.i 0
  (p7)	hint.i @pause
  (p7)	hint.i 0x1fffff
+
+	# instructions added by SDM2.2:
+
+	tf.z p2, p3 = 39
+	tf.z.unc p2, p3 = 39
+	tf.z.and p2, p3 = 39
+	tf.z.or p2, p3 = 39
+	tf.z.or.andcm p2, p3 = 39
+	tf.z.orcm p2, p3 = 39
+	tf.z.andcm p2, p3 = 39
+	tf.z.and.orcm p2, p3 = 39
+	tf.nz p2, p3 = 39
+	tf.nz.unc p2, p3 = 39
+	tf.nz.and p2, p3 = 39
+	tf.nz.or p2, p3 = 39
+	tf.nz.or.andcm p2, p3 = 39
+	tf.nz.orcm p2, p3 = 39
+	tf.nz.andcm p2, p3 = 39
+	tf.nz.and.orcm p2, p3 = 39
+
+(p7)	tf.z p2, p3 = 39
+(p7)	tf.z.unc p2, p3 = 39
+(p7)	tf.z.and p2, p3 = 39
+(p7)	tf.z.or p2, p3 = 39
+(p7)	tf.z.or.andcm p2, p3 = 39
+(p7)	tf.z.orcm p2, p3 = 39
+(p7)	tf.z.andcm p2, p3 = 39
+(p7)	tf.z.and.orcm p2, p3 = 39
+(p7)	tf.nz p2, p3 = 39
+(p7)	tf.nz.unc p2, p3 = 39
+(p7)	tf.nz.and p2, p3 = 39
+(p7)	tf.nz.or p2, p3 = 39
+(p7)	tf.nz.or.andcm p2, p3 = 39
+(p7)	tf.nz.orcm p2, p3 = 39
+(p7)	tf.nz.andcm p2, p3 = 39
+(p7)	tf.nz.and.orcm p2, p3 = 39
diff --git a/gas/testsuite/gas/ia64/opc-m.d b/gas/testsuite/gas/ia64/opc-m.d
index ea5ddac0a607..7ec2a4274ce8 100644
--- a/gas/testsuite/gas/ia64/opc-m.d
+++ b/gas/testsuite/gas/ia64/opc-m.d
@@ -1,3 +1,4 @@
+# as: -xnone -mtune=itanium1
 # objdump: -d
 # name: ia64 opc-m
 
diff --git a/gas/testsuite/gas/ia64/opc-x.d b/gas/testsuite/gas/ia64/opc-x.d
index 77010e8d5eb2..dc645587806d 100644
--- a/gas/testsuite/gas/ia64/opc-x.d
+++ b/gas/testsuite/gas/ia64/opc-x.d
@@ -1,3 +1,4 @@
+#as: -xnone
 #objdump: -d
 #name: ia64 opc-x
 
diff --git a/gas/testsuite/gas/ia64/operand-or.d b/gas/testsuite/gas/ia64/operand-or.d
new file mode 100644
index 000000000000..a40087a853ac
--- /dev/null
+++ b/gas/testsuite/gas/ia64/operand-or.d
@@ -0,0 +1,30 @@
+# as: -xnone -mtune=itanium1
+# objdump: -d --disassemble-zeroes
+# name: ia64 operand-or
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+000 <_start>:
+   0:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+   6:	30 20 80 09 28 00 	            fclass\.m p3,p4=f4,0x180
+   c:	00 00 00 20       	            nop\.b 0x0
+  10:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  16:	30 20 c0 09 28 00 	            fclass\.m p3,p4=f4,0x1c0
+  1c:	00 00 00 20       	            nop\.b 0x0
+  20:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  26:	30 20 c0 89 28 00 	            fclass\.m p3,p4=f4,0x1c1
+  2c:	00 00 00 20       	            nop\.b 0x0
+  30:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  36:	30 20 c0 89 29 00 	            fclass\.m p3,p4=f4,0x1c3
+  3c:	00 00 00 20       	            nop\.b 0x0
+  40:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  46:	30 20 c8 89 29 00 	            fclass\.m p3,p4=f4,0x1cb
+  4c:	00 00 00 20       	            nop\.b 0x0
+  50:	1c 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  56:	30 20 d8 89 29 00 	            fclass\.m p3,p4=f4,0x1db
+  5c:	00 00 00 20       	            nop\.b 0x0
+  60:	1d 00 00 00 01 00 	\[MFB\]       nop\.m 0x0
+  66:	30 20 f8 89 29 00 	            fclass\.m p3,p4=f4,0x1fb
+  6c:	00 00 00 20       	            nop\.b 0x0;;
diff --git a/gas/testsuite/gas/ia64/operand-or.s b/gas/testsuite/gas/ia64/operand-or.s
new file mode 100644
index 000000000000..a48a9162a4d4
--- /dev/null
+++ b/gas/testsuite/gas/ia64/operand-or.s
@@ -0,0 +1,11 @@
+.text
+	.type _start,@function
+_start:
+
+	fclass.m p3, p4 = f4, @nat|@qnan
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan|@pos
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan|@pos|@neg
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan|@pos|@neg|@unorm
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan|@pos|@neg|@unorm|@norm
+	fclass.m p3, p4 = f4, @nat|@qnan|@snan|@pos|@neg|@unorm|@norm|@inf
diff --git a/gas/testsuite/gas/ia64/operands.l b/gas/testsuite/gas/ia64/operands.l
new file mode 100644
index 000000000000..440c78b5260c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/operands.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:3: Error: .* output .*
+.*:4: Error: .* input .*
+.*:5: Error: .* 1 .*
+.*:6: Error: .* 2 .*
diff --git a/gas/testsuite/gas/ia64/operands.s b/gas/testsuite/gas/ia64/operands.s
new file mode 100644
index 000000000000..08f4ec15b6f5
--- /dev/null
+++ b/gas/testsuite/gas/ia64/operands.s
@@ -0,0 +1,6 @@
+	.text
+_start:
+	zxt1	r1, r2 = r3
+	zxt2	r4 = r5, r6
+	zxt4	p1 = r8
+	sxt1	r7 = 0
diff --git a/gas/testsuite/gas/ia64/pcrel.d b/gas/testsuite/gas/ia64/pcrel.d
new file mode 100644
index 000000000000..674060d8bf30
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pcrel.d
@@ -0,0 +1,63 @@
+#as: -mtune=itanium1
+#objdump: -rs
+#name: ia64 pcrel
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.mov\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0+10[[:space:]]+PCREL22[[:space:]]+esym
+0+20[[:space:]]+PCREL22[[:space:]]+esym\+0x0+20
+0+30[[:space:]]+PCREL22[[:space:]]+esym
+0+40[[:space:]]+PCREL22[[:space:]]+esym\+0xf+e0
+
+RELOCATION RECORDS FOR \[\.movl\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0+12[[:space:]]+PCREL64I[[:space:]]+esym
+0+22[[:space:]]+PCREL64I[[:space:]]+esym\+0x0+20
+0+32[[:space:]]+PCREL64I[[:space:]]+esym
+0+42[[:space:]]+PCREL64I[[:space:]]+esym\+0xf+e0
+
+RELOCATION RECORDS FOR \[\.data8\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0+10[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
+0+20[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0x0+20
+0+30[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
+0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0xf+e0
+
+RELOCATION RECORDS FOR \[\.data4\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0+10[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
+0+20[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0x0+20
+0+30[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
+0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0xf+e0
+
+
+Contents of section \.mov:
+ 0+00 1d108001 00240000 00020000 00000020  .*
+ 0+10 1d100000 00240000 00020000 00000020  .*
+ 0+20 1d100000 00240000 00020000 00000020  .*
+ 0+30 1d100000 00240000 00020000 00000020  .*
+ 0+40 1d100000 00240000 00020000 00000020  .*
+ 0+50 1d100000 00240000 00020000 00000020  .*
+Contents of section \.movl:
+ 0+00 05000000 01000000 00000040 00060060  .*
+ 0+10 05000000 01000000 00000040 00000060  .*
+ 0+20 05000000 01000000 00000040 00000060  .*
+ 0+30 05000000 01000000 00000040 00000060  .*
+ 0+40 05000000 01000000 00000040 00000060  .*
+ 0+50 05000000 01000000 00000040 00000060  .*
+Contents of section \.data8:
+ 0+00 [06]0000000 000000[06]0 00000000 00000000  .*
+ 0+10 00000000 00000000 00000000 00000000  .*
+ 0+20 00000000 00000000 00000000 00000000  .*
+ 0+30 00000000 00000000 00000000 00000000  .*
+ 0+40 00000000 00000000 00000000 00000000  .*
+ 0+50 00000000 00000000 00000000 00000000  .*
+Contents of section \.data4:
+ 0+00 [06]00000[06]0 00000000 00000000 00000000  .*
+ 0+10 00000000 00000000 00000000 00000000  .*
+ 0+20 00000000 00000000 00000000 00000000  .*
+ 0+30 00000000 00000000 00000000 00000000  .*
+ 0+40 00000000 00000000 00000000 00000000  .*
+ 0+50 00000000 00000000 00000000 00000000  .*
diff --git a/gas/testsuite/gas/ia64/pcrel.s b/gas/testsuite/gas/ia64/pcrel.s
new file mode 100644
index 000000000000..d63130a7d93b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pcrel.s
@@ -0,0 +1,87 @@
+.explicit
+.global esym
+
+.altmacro
+
+.macro begin n, attr
+ .section .&n, attr, @progbits
+ .align 16
+_&n:
+.endm
+.macro end n
+ .align 16
+_e&n:
+.endm
+
+.macro m1 op, opnd1
+ .align 16
+	op		opnd1 _e&op - _&op
+.endm
+.macro m2 op, opnd1
+ .align 16
+	op		opnd1 @pcrel(esym)
+.endm
+.macro m3 op, opnd1
+ .align 16
+	op		opnd1 esym - _&op
+.endm
+.macro m4 op, opnd1
+ .align 16
+	op		opnd1 esym - .
+.endm
+.macro m5 op, opnd1
+ .align 16
+	op		opnd1 esym - _e&op
+.endm
+.macro m6 op, opnd1
+ .align 16
+	op		opnd1 0
+.endm
+
+begin	mov, "ax"
+	m1	mov, r2 =
+	;;
+	m2	mov, r2 =
+	;;
+	m3	mov, r2 =
+	;;
+	m4	mov, r2 =
+	;;
+	m5	mov, r2 =
+	;;
+	m6	mov, r2 =
+	;;
+end mov
+
+begin	movl, "ax"
+	m1	movl, r2 =
+	;;
+	m2	movl, r2 =
+	;;
+	m3	movl, r2 =
+	;;
+	m4	movl, r2 =
+	;;
+	m5	movl, r2 =
+	;;
+	m6	movl, r2 =
+	;;
+end movl
+
+begin data8, "a"
+	m1	data8
+	m2	data8
+	m3	data8
+	m4	data8
+	m5	data8
+	m6	data8
+end data8
+
+begin data4, "a"
+	m1	data4
+	m2	data4
+	m3	data4
+	m4	data4
+	m5	data4
+	m6	data4
+end data4
diff --git a/gas/testsuite/gas/ia64/pound.l b/gas/testsuite/gas/ia64/pound.l
new file mode 100644
index 000000000000..71f2a4fa253b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pound.l
@@ -0,0 +1,58 @@
+.*: Assembler messages:
+.*:35: Warning: .* WAW .*
+#...
+.*:41: Error: symbol .esym. .* .efunction.
+.*:43: Error: section .\.extra. .* .esection.
+GAS LISTING .*
+#...
+[[:space:]]*[[:digit:]]+[[:space:]]+\.explicit
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+\.global esym#
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+\.section \.extra#, "a", @progbits
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+\.text
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+	break		0
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+[[:xdigit:]]+[[:space:]]+\.proc psym
+#...
+[[:space:]]*[[:digit:]]+[[:space:]]+psym:
+[[:space:]]*[[:digit:]]+[[:space:]]+	mov\.ret\.sptk	b7 = r0, tag#
+[[:space:]]*[[:digit:]]+[[:space:]]+	mov		r8 = 0
+[[:space:]]*[[:digit:]]+[[:space:]]+\[tag:\]	br\.ret\.sptk	rp
+[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+[[:xdigit:]]+[[:space:]]+\.endp psym
+#...
+[[:space:]]*[[:digit:]]+[[:space:]]+
+[[:space:]]*[[:digit:]]+[[:space:]]+\.proc esym#
+[[:space:]]*[[:digit:]]+[[:space:]]+\.entry entry#
+[[:space:]]*[[:digit:]]+[[:space:]]+esym:
+[[:space:]]*[[:digit:]]+[[:space:]]+\.unwentry
+[[:space:]]*[[:digit:]]+[[:space:]]+\.personality psym#
+[[:space:]]*[[:digit:]]+[[:space:]]+\.regstk 0, 8, 0, 8
+[[:space:]]*[[:digit:]]+[[:space:]]+\.rotp p#\[2\], p1#\[4\]
+[[:space:]]*[[:digit:]]+[[:space:]]+\.rotr r#\[2\], r1#\[4\]
+[[:space:]]*[[:digit:]]+[[:space:]]+\.reg\.val r#\[1\], 0
+[[:space:]]*[[:digit:]]+[[:space:]]+\.reg\.val r1#\[3\], 0
+[[:space:]]*[[:digit:]]+[[:space:]]+\(p1#\[1\]\) cmp\.eq	p\[0\] = r\[1\], r1#\[1\]
+[[:space:]]*[[:digit:]]+[[:space:]]+\(p1#\[3\]\) cmp\.eq	p#\[1\] = r#\[1\], r1#\[3\]
+[[:space:]]*[[:digit:]]+[[:space:]]+\.pred\.rel "mutex", p#\[0\], p\[1\]
+[[:space:]]*[[:digit:]]+[[:space:]]+	nop		0
+[[:space:]]*[[:digit:]]+[[:space:]]+	;;
+[[:space:]]*[[:digit:]]+[[:space:]]+entry:
+[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+61828446[[:space:]]+\(p\[0\]\)	mov		r8 = 1
+[[:space:]]*[[:digit:]]+[[:space:]]+00781509[[:space:]]*
+[[:space:]]*[[:digit:]]+[[:space:]]+95007000[[:space:]]*
+[[:space:]]*[[:digit:]]+[[:space:]]+00000400[[:space:]]*
+[[:space:]]*[[:digit:]]+[[:space:]]+\(p#\[1\]\)	mov		r8 = 0
+[[:space:]]*[[:digit:]]+[[:space:]]+	br\.ret\.sptk	rp
+[[:space:]]*[[:digit:]]+[[:space:]]+\.xdata4 \.extra#, -1
+[[:space:]]*[[:digit:]]+[[:space:]]+\?*[[:space:]]+11420400+[[:space:]]+\.endp esym#
+[[:space:]]*[[:digit:]]+[[:space:]]+00648400[[:space:]]*
+[[:space:]]*[[:digit:]]+[[:space:]]+00004880[[:space:]]*
+[[:space:]]*[[:digit:]]+[[:space:]]+00008400[[:space:]]*
+#...
+[[:space:]]*[[:digit:]]+[[:space:]]+\.alias esym#, "efunction"
+[[:space:]]*[[:digit:]]+[[:space:]]+\.alias esym, "efunc"
+[[:space:]]*[[:digit:]]+[[:space:]]+\.secalias \.extra#, "esection"
+[[:space:]]*[[:digit:]]+[[:space:]]+\.secalias \.extra, "esec"
diff --git a/gas/testsuite/gas/ia64/pound.s b/gas/testsuite/gas/ia64/pound.s
new file mode 100644
index 000000000000..f54c072f5b67
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pound.s
@@ -0,0 +1,43 @@
+.explicit
+
+.global esym#
+
+.section .extra#, "a", @progbits
+
+.text
+
+	break		0
+
+.proc psym
+psym:
+	mov.ret.sptk	b7 = r0, tag#
+	mov		r8 = 0
+[tag:]	br.ret.sptk	rp
+.endp psym
+
+.proc esym#
+.entry entry#
+esym:
+.unwentry
+.personality psym#
+.regstk 0, 8, 0, 8
+.rotp p#[2], p1#[4]
+.rotr r#[2], r1#[4]
+.reg.val r#[1], 0
+.reg.val r1#[3], 0
+(p1#[1]) cmp.eq	p[0] = r[1], r1#[1]
+(p1#[3]) cmp.eq	p#[1] = r#[1], r1#[3]
+.pred.rel "mutex", p#[0], p[1]
+	nop		0
+	;;
+entry:
+(p[0])	mov		r8 = 1
+(p#[1])	mov		r8 = 0
+	br.ret.sptk	rp
+.xdata4 .extra#, -1
+.endp esym#
+
+.alias esym#, "efunction"
+.alias esym, "efunc"
+.secalias .extra#, "esection"
+.secalias .extra, "esec"
diff --git a/gas/testsuite/gas/ia64/pred-rel.s b/gas/testsuite/gas/ia64/pred-rel.s
new file mode 100644
index 000000000000..1316921a6b8c
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pred-rel.s
@@ -0,0 +1,21 @@
+// Make sure all forms of .pred.rel are accepted
+_start:
+	.pred.rel "mutex", p1, p2
+	.pred.rel "imply", p2, p3
+	.pred.rel "clear", p1, p2, p3
+
+	.pred.rel "mutex" p1, p2
+	.pred.rel "imply" p2, p3
+	.pred.rel "clear" p1, p2, p3
+
+	.pred.rel.mutex p1, p2
+	.pred.rel.imply p2, p3
+	.pred.rel.clear p1, p2, p3
+
+	.pred.rel @mutex, p1, p2
+	.pred.rel @imply, p2, p3
+	.pred.rel @clear, p1, p2, p3
+
+	.pred.rel @mutex p1, p2
+	.pred.rel @imply p2, p3
+	.pred.rel @clear p1, p2, p3
diff --git a/gas/testsuite/gas/ia64/proc.l b/gas/testsuite/gas/ia64/proc.l
new file mode 100644
index 000000000000..60843c1f00b9
--- /dev/null
+++ b/gas/testsuite/gas/ia64/proc.l
@@ -0,0 +1,6 @@
+.*: Assembler messages:
+.*:4: Error: .* already defined.*
+.*:7: Error: .* not defined.*
+.*:7: Warning: .* not specified.*
+.*:12: Error: Empty argument of .proc
+.*:13: Error: Empty argument of .endp
diff --git a/gas/testsuite/gas/ia64/proc.s b/gas/testsuite/gas/ia64/proc.s
new file mode 100644
index 000000000000..9225a0a01b59
--- /dev/null
+++ b/gas/testsuite/gas/ia64/proc.s
@@ -0,0 +1,13 @@
+func1::
+	br.ret.sptk rp
+
+.proc	func, func1, func2
+func::
+	br.ret.sptk rp
+.endp	func, func1, func2
+
+func2::
+	br.ret.sptk rp
+
+.proc
+.endp
diff --git a/gas/testsuite/gas/ia64/pseudo.d b/gas/testsuite/gas/ia64/pseudo.d
new file mode 100644
index 000000000000..3dd850594744
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pseudo.d
@@ -0,0 +1,29 @@
+# as: -xnone -mtune=itanium1
+# objdump: -d
+# name: ia64 pseudo-ops
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+alloc r8=ar\.pfs,0,0,0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp\.eq p6,p0=r0,r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp\.eq p7,p0=0,r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp4\.eq p8,p0=r0,r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp4\.eq p9,p0=0,r0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmp8xchg16\.acq r9=\[r0\],r0,ar\.csd,ar\.ccv
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+cmpxchg4\.acq r10=\[r0\],r0,ar\.ccv
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+fclass\.m p10,p0=f0,0x1
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+fcmp\.eq\.s0 p11,p0=f0,f0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+ld16 r11,ar\.csd=\[r0\]
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+nop\.. 0x0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+mov pr=r0,0xfffffffffffffffe
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+st16 \[r0\]=r0,ar\.csd
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tbit\.z p0,p12=r0,0
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tnat\.z p0,p13=r0(;;)?
+#...
+[[:space:]]*[[:xdigit:]]*:[[:space:][:xdigit:]]+(\[[[:upper:]]+\])?[[:space:]]+tf\.z p3,p2=33(;;)?
diff --git a/gas/testsuite/gas/ia64/pseudo.s b/gas/testsuite/gas/ia64/pseudo.s
new file mode 100644
index 000000000000..06326c172ebe
--- /dev/null
+++ b/gas/testsuite/gas/ia64/pseudo.s
@@ -0,0 +1,19 @@
+_start:
+	alloc		r8 = 0, 0, 0, 0
+	cmp.eq		p6 = r0, r0
+	cmp.eq		p7 = 0, r0
+	cmp4.eq		p8 = r0, r0
+	cmp4.eq		p9 = 0, r0
+	cmp8xchg16.acq	r9 = [r0], r0
+	cmpxchg4.acq	r10 = [r0], r0
+	fclass.m	p10 = f0, @pos
+	fcmp.eq		p11 = f0, f0
+	ld16		r11 = [r0]
+	mov		pr = r0
+	st16		[r0] = r0
+	tbit.nz		p12 = r0, 0
+	tnat.nz		p13 = r0
+
+	# instructions added by SDM2.2:
+
+	tf.nz p2, p3 = 33
diff --git a/gas/testsuite/gas/ia64/radix.l b/gas/testsuite/gas/ia64/radix.l
new file mode 100644
index 000000000000..92d9e7cda14f
--- /dev/null
+++ b/gas/testsuite/gas/ia64/radix.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*:1: Error: Radix .a. .*invalid
+.*:4: Error: Radix .cc. .*invalid
+.*:5: Error: Radix .Z. .*invalid
diff --git a/gas/testsuite/gas/ia64/radix.s b/gas/testsuite/gas/ia64/radix.s
new file mode 100644
index 000000000000..75dcf7bc8684
--- /dev/null
+++ b/gas/testsuite/gas/ia64/radix.s
@@ -0,0 +1,5 @@
+	.radix a
+	.radix c
+	.radix C#
+	.radix cc
+	.radix Z
diff --git a/gas/testsuite/gas/ia64/reg-err.l b/gas/testsuite/gas/ia64/reg-err.l
new file mode 100644
index 000000000000..bd4dbc401d3e
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reg-err.l
@@ -0,0 +1,14 @@
+.*: Assembler messages:
+.*:3: (Error|Warning): Invalid use of `r0' as output operand
+.*:4: (Error|Warning): Invalid use of `r0' as base update address operand
+.*:5: (Error|Warning): Invalid duplicate use of `r1'
+.*:6: (Error|Warning): Invalid use of `r0' as base update address operand
+.*:7: (Error|Warning): Invalid duplicate use of `p1'
+.*:8: (Error|Warning): Invalid use of `f0' as output operand
+.*:9: (Error|Warning): Invalid use of `f1' as output operand
+.*:10: (Error|Warning): Invalid use of `f0' as output operand
+.*:11: (Error|Warning): Invalid use of `f1' as output operand
+.*:12: (Error|Warning): Invalid use of `f0' as output operand
+.*:12: (Error|Warning): Invalid use of `f1' as output operand
+.*:13: (Error|Warning): Invalid simultaneous use of `f2' and `f4'
+.*:14: (Error|Warning): Dangerous simultaneous use of `f31' and `f32'
diff --git a/gas/testsuite/gas/ia64/reg-err.s b/gas/testsuite/gas/ia64/reg-err.s
new file mode 100644
index 000000000000..88124d365e77
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reg-err.s
@@ -0,0 +1,14 @@
+	.text
+_start:
+	mov	r0 = r0
+	ld1	r1 = [r0], 1
+	ld1	r1 = [r1], 1
+	st1	[r0] = r0, 1
+	cmp.eq	p1, p1 = 0, r0
+	mov	f0 = f0
+	mov	f1 = f1
+	ldfs	f0 = [r0]
+	ldfs	f1 = [r0]
+	ldfps	f0, f1 = [r0]
+	ldfps	f2, f4 = [r0]
+	ldfps	f31, f32 = [r0]
diff --git a/gas/testsuite/gas/ia64/regs.d b/gas/testsuite/gas/ia64/regs.d
index 20655b114814..1dbd13787a35 100644
--- a/gas/testsuite/gas/ia64/regs.d
+++ b/gas/testsuite/gas/ia64/regs.d
@@ -1,3 +1,4 @@
+#as: -xnone
 #objdump: -d
 #name: ia64 regs
 
@@ -1264,8 +1265,8 @@ Disassembly of section \.text:
     1a26:	00 00 00 02 00 00 	            nop\.i 0x0
     1a2c:	00 00 04 00       	            nop\.i 0x0;;
     1a30:	01 08 00 00 00 21 	\[MII\]       mov r1=r0
-    1a36:	c0 00 00 00 42 00 	            mov r12=r0
-    1a3c:	00 00 04 00       	            nop\.i 0x0;;
+    1a36:	c0 00 00 00 42 a0 	            mov r12=r0
+    1a3c:	01 00 00 84       	            mov r13=r0;;
     1a40:	0d 00 00 00 01 00 	\[MFI\]       nop\.m 0x0
     1a46:	20 00 00 20 00 00 	            mov f2=f0
     1a4c:	00 00 04 00       	            nop\.i 0x0;;
@@ -2041,53 +2042,53 @@ Disassembly of section \.text:
     2a56:	00 00 00 02 00 20 	            nop\.m 0x0
     2a5c:	00 10 ca 00       	            mov\.i r1=ar\.ec;;
     2a60:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2a66:	00 00 00 02 00 20 	            nop\.m 0x0
-    2a6c:	00 80 cb 00       	            mov\.i r1=ar112;;
+    2a66:	10 00 c0 45 08 00 	            mov\.m r1=ar112
+    2a6c:	00 00 04 00       	            nop\.i 0x0;;
     2a70:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2a76:	00 00 00 02 00 20 	            nop\.m 0x0
-    2a7c:	00 88 cb 00       	            mov\.i r1=ar113;;
+    2a76:	10 00 c4 45 08 00 	            mov\.m r1=ar113
+    2a7c:	00 00 04 00       	            nop\.i 0x0;;
     2a80:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2a86:	00 00 00 02 00 20 	            nop\.m 0x0
-    2a8c:	00 90 cb 00       	            mov\.i r1=ar114;;
+    2a86:	10 00 c8 45 08 00 	            mov\.m r1=ar114
+    2a8c:	00 00 04 00       	            nop\.i 0x0;;
     2a90:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2a96:	00 00 00 02 00 20 	            nop\.m 0x0
-    2a9c:	00 98 cb 00       	            mov\.i r1=ar115;;
+    2a96:	10 00 cc 45 08 00 	            mov\.m r1=ar115
+    2a9c:	00 00 04 00       	            nop\.i 0x0;;
     2aa0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2aa6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2aac:	00 a0 cb 00       	            mov\.i r1=ar116;;
+    2aa6:	10 00 d0 45 08 00 	            mov\.m r1=ar116
+    2aac:	00 00 04 00       	            nop\.i 0x0;;
     2ab0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2ab6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2abc:	00 a8 cb 00       	            mov\.i r1=ar117;;
+    2ab6:	10 00 d4 45 08 00 	            mov\.m r1=ar117
+    2abc:	00 00 04 00       	            nop\.i 0x0;;
     2ac0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2ac6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2acc:	00 b0 cb 00       	            mov\.i r1=ar118;;
+    2ac6:	10 00 d8 45 08 00 	            mov\.m r1=ar118
+    2acc:	00 00 04 00       	            nop\.i 0x0;;
     2ad0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2ad6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2adc:	00 b8 cb 00       	            mov\.i r1=ar119;;
+    2ad6:	10 00 dc 45 08 00 	            mov\.m r1=ar119
+    2adc:	00 00 04 00       	            nop\.i 0x0;;
     2ae0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2ae6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2aec:	00 c0 cb 00       	            mov\.i r1=ar120;;
+    2ae6:	10 00 e0 45 08 00 	            mov\.m r1=ar120
+    2aec:	00 00 04 00       	            nop\.i 0x0;;
     2af0:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2af6:	00 00 00 02 00 20 	            nop\.m 0x0
-    2afc:	00 c8 cb 00       	            mov\.i r1=ar121;;
+    2af6:	10 00 e4 45 08 00 	            mov\.m r1=ar121
+    2afc:	00 00 04 00       	            nop\.i 0x0;;
     2b00:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b06:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b0c:	00 d0 cb 00       	            mov\.i r1=ar122;;
+    2b06:	10 00 e8 45 08 00 	            mov\.m r1=ar122
+    2b0c:	00 00 04 00       	            nop\.i 0x0;;
     2b10:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b16:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b1c:	00 d8 cb 00       	            mov\.i r1=ar123;;
+    2b16:	10 00 ec 45 08 00 	            mov\.m r1=ar123
+    2b1c:	00 00 04 00       	            nop\.i 0x0;;
     2b20:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b26:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b2c:	00 e0 cb 00       	            mov\.i r1=ar124;;
+    2b26:	10 00 f0 45 08 00 	            mov\.m r1=ar124
+    2b2c:	00 00 04 00       	            nop\.i 0x0;;
     2b30:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b36:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b3c:	00 e8 cb 00       	            mov\.i r1=ar125;;
+    2b36:	10 00 f4 45 08 00 	            mov\.m r1=ar125
+    2b3c:	00 00 04 00       	            nop\.i 0x0;;
     2b40:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b46:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b4c:	00 f0 cb 00       	            mov\.i r1=ar126;;
+    2b46:	10 00 f8 45 08 00 	            mov\.m r1=ar126
+    2b4c:	00 00 04 00       	            nop\.i 0x0;;
     2b50:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
-    2b56:	00 00 00 02 00 20 	            nop\.m 0x0
-    2b5c:	00 f8 cb 00       	            mov\.i r1=ar127;;
+    2b56:	10 00 fc 45 08 00 	            mov\.m r1=ar127
+    2b5c:	00 00 04 00       	            nop\.i 0x0;;
     2b60:	09 00 00 00 01 00 	\[MMI\]       nop\.m 0x0
     2b66:	10 00 00 44 08 00 	            mov\.m r1=ar\.k0
     2b6c:	00 00 04 00       	            nop\.i 0x0;;
diff --git a/gas/testsuite/gas/ia64/regs.pl b/gas/testsuite/gas/ia64/regs.pl
index ca51cc036d17..1c7df5c390fc 100644
--- a/gas/testsuite/gas/ia64/regs.pl
+++ b/gas/testsuite/gas/ia64/regs.pl
@@ -38,7 +38,7 @@ print "\n";
 print "\t{ .mii;\n";
 print "\tmov gp = r0\n";
 print "\tmov sp = r0\n";
-print "\tnop.i 0;; }\n\n";
+print "\tmov tp = r0;; }\n\n";
 
 print "// Floating point registers\n";
 for ($i = 2; $i < 128; ++$i) {
diff --git a/gas/testsuite/gas/ia64/regs.s b/gas/testsuite/gas/ia64/regs.s
index 06226a55f746..8e77b0e81c28 100644
--- a/gas/testsuite/gas/ia64/regs.s
+++ b/gas/testsuite/gas/ia64/regs.s
@@ -437,7 +437,7 @@ _start:
 	{ .mii;
 	mov gp = r0
 	mov sp = r0
-	nop.i 0;; }
+	mov tp = r0;; }
 
 // Floating point registers
 	{ .mfi; mov f2 = f0 ;; }
diff --git a/gas/testsuite/gas/ia64/regval.l b/gas/testsuite/gas/ia64/regval.l
new file mode 100644
index 000000000000..b12a266227fc
--- /dev/null
+++ b/gas/testsuite/gas/ia64/regval.l
@@ -0,0 +1,17 @@
+.*: Assembler messages:
+.*:11: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specific resource number is 0
+.*:11: Warning: Only the first path encountering the conflict is reported
+.*:10: Warning: This is the location of the conflicting usage
+#...
+.*:25: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specific resource number is 0
+.*:25: Warning: Only the first path encountering the conflict is reported
+.*:24: Warning: This is the location of the conflicting usage
+#...
+.*:32: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\)
+.*:32: Warning: Only the first path encountering the conflict is reported
+.*:31: Warning: This is the location of the conflicting usage
+#...
+.*:46: Warning: Use of 'mov' .* WAW dependency 'RR#' \(impliedf\), specific resource number is 0
+.*:46: Warning: Only the first path encountering the conflict is reported
+.*:45: Warning: This is the location of the conflicting usage
+#pass
diff --git a/gas/testsuite/gas/ia64/regval.s b/gas/testsuite/gas/ia64/regval.s
new file mode 100644
index 000000000000..3fb033017de0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/regval.s
@@ -0,0 +1,48 @@
+.explicit
+rr1:
+	.reg.val r1, 0xE000000000000000
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr2:
+	.reg.val r1, 0
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr3:
+	movl		r1 = 0xE000000000000000
+	;;
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr4:
+	mov		r1 = 0
+	;;
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr5:
+	movl		r1 = xyz+0xE000000000000000
+	;;
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr6:
+	dep.z		r1 = 1, 61, 3
+	;;
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
+rr7:
+	dep.z		r1 = -1, 0, 61
+	;;
+	mov		rr[r0] = r0
+	mov		rr[r1] = r0
+	br.ret.sptk	rp
+	;;
diff --git a/gas/testsuite/gas/ia64/reloc-bad.l b/gas/testsuite/gas/ia64/reloc-bad.l
new file mode 100644
index 000000000000..5a2df9a73bb4
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc-bad.l
@@ -0,0 +1,43 @@
+.*: Assembler messages:
+.*:[[:digit:]]+: (Error|Warning): .* GPREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF64[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* PLTOFF14 .*
+.*:[[:digit:]]+: (Error|Warning): .* PLTOFF32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* FPTR14 .*
+.*:[[:digit:]]+: (Error|Warning): .* FPTR22 .*
+.*:[[:digit:]]+: (Error|Warning): .* PCREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_FPTR14 .*
+.*:[[:digit:]]+: (Error|Warning): .* SEGREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* SEGREL22 .*
+.*:[[:digit:]]+: (Error|Warning): .* SEGREL64I .*
+.*:[[:digit:]]+: (Error|Warning): .* SECREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* SECREL22 .*
+.*:[[:digit:]]+: (Error|Warning): .* SECREL64I .*
+.*:[[:digit:]]+: (Error|Warning): .* LTV14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTV22 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTV64I .*
+.*:[[:digit:]]+: (Error|Warning): .* IPLT14 .*
+.*:[[:digit:]]+: (Error|Warning): .* IPLT22 .*
+.*:[[:digit:]]+: (Error|Warning): .* IPLT64I .*
+.*:[[:digit:]]+: (Error|Warning): .* IPLT32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* IPLT64[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF14X .*
+.*:[[:digit:]]+: (Error|Warning): .* TPREL32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64I .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* DTPMOD14 .*
+.*:[[:digit:]]+: (Error|Warning): .* DTPMOD22 .*
+.*:[[:digit:]]+: (Error|Warning): .* DTPMOD64I .*
+.*:[[:digit:]]+: (Error|Warning): .* DTPMOD32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPMOD14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPMOD64I .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_TPREL64[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL14 .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL64I .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL32[LM]SB .*
+.*:[[:digit:]]+: (Error|Warning): .* LTOFF_DTPREL64[LM]SB .*
diff --git a/gas/testsuite/gas/ia64/reloc-bad.s b/gas/testsuite/gas/ia64/reloc-bad.s
new file mode 100644
index 000000000000..488a0d986379
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc-bad.s
@@ -0,0 +1,62 @@
+	.psr abi64
+	.global esym
+	.section .rodata, "a", @progbits
+	.text
+_start:
+	adds		r1 = @gprel(esym), r0
+
+	adds		r1 = @ltoff(esym), r0
+	.xdata4 .rodata, @ltoff(esym)
+	.xdata8 .rodata, @ltoff(esym)
+
+	adds		r1 = @pltoff(esym), r0
+	.xdata4 .rodata, @pltoff(esym)
+
+	adds		r1 = @fptr(esym), r0
+	mov		r2 = @fptr(esym)
+
+	adds		r1 = @pcrel(esym), r0
+
+	adds		r1 = @ltoff(@fptr(esym)), r0
+
+	adds		r1 = @segrel(esym), r0
+	mov		r2 = @segrel(esym)
+	movl		r3 = @segrel(esym)
+
+	adds		r1 = @secrel(esym), r0
+	mov		r2 = @secrel(esym)
+	movl		r3 = @secrel(esym)
+
+	adds		r1 = @ltv(esym), r0
+	mov		r2 = @ltv(esym)
+	movl		r3 = @ltv(esym)
+
+	adds		r1 = @iplt(esym), r0
+	mov		r2 = @iplt(esym)
+	movl		r3 = @iplt(esym)
+	.xdata4 .rodata, @iplt(esym)
+	.xdata8 .rodata, @iplt(esym)
+
+	adds		r1 = @ltoffx(esym), r0
+
+	.xdata4 .rodata, @tprel(esym)
+
+	adds		r1 = @ltoff(@tprel(esym)), r0
+	movl		r3 = @ltoff(@tprel(esym))
+	.xdata4 .rodata, @ltoff(@tprel(esym))
+	.xdata8 .rodata, @ltoff(@tprel(esym))
+
+	adds		r1 = @dtpmod(esym), r0
+	mov		r2 = @dtpmod(esym)
+	movl		r3 = @dtpmod(esym)
+	.xdata4 .rodata, @dtpmod(esym)
+
+	adds		r1 = @ltoff(@dtpmod(esym)), r0
+	movl		r3 = @ltoff(@dtpmod(esym))
+	.xdata4 .rodata, @ltoff(@tprel(esym))
+	.xdata8 .rodata, @ltoff(@tprel(esym))
+
+	adds		r1 = @ltoff(@dtprel(esym)), r0
+	movl		r3 = @ltoff(@dtprel(esym))
+	.xdata4 .rodata, @ltoff(@dtprel(esym))
+	.xdata8 .rodata, @ltoff(@dtprel(esym))
diff --git a/gas/testsuite/gas/ia64/reloc-uw-ilp32.d b/gas/testsuite/gas/ia64/reloc-uw-ilp32.d
new file mode 100644
index 000000000000..b59eb40fd7bd
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc-uw-ilp32.d
@@ -0,0 +1,15 @@
+#objdump: -r
+#name: ia64 unwind relocations (ilp32)
+#as: -milp32
+#source: reloc-uw.s
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.IA_64\.unwind\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0*00 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*04 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*08 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c])?
+0*0c SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*10 SEGREL32[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*14 SEGREL32[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[048c])?
diff --git a/gas/testsuite/gas/ia64/reloc-uw.d b/gas/testsuite/gas/ia64/reloc-uw.d
new file mode 100644
index 000000000000..e7af6f1b88b5
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc-uw.d
@@ -0,0 +1,13 @@
+# objdump: -r
+# name: ia64 unwind relocations
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.IA_64\.unwind\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+0*00 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*08 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*10 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])?
+0*18 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*20 SEGREL64[ML]SB[[:space:]]+\.text(\+0x[[:xdigit:]]*0)?
+0*28 SEGREL64[ML]SB[[:space:]]+\.IA_64\.unwind_info(\+0x[[:xdigit:]]*[08])?
diff --git a/gas/testsuite/gas/ia64/reloc-uw.s b/gas/testsuite/gas/ia64/reloc-uw.s
new file mode 100644
index 000000000000..1cda453f5227
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc-uw.s
@@ -0,0 +1,13 @@
+	.text
+
+	.macro uw, type
+	.proc	uw\type
+	.\type	uw\type
+uw\type:
+	.unwentry
+	br.ret.sptk rp
+	.endp	uw\type
+	.endm
+
+	uw global
+	uw weak
diff --git a/gas/testsuite/gas/ia64/reloc.d b/gas/testsuite/gas/ia64/reloc.d
new file mode 100644
index 000000000000..467282dfe92e
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc.d
@@ -0,0 +1,64 @@
+#objdump: -r
+#name: ia64 relocations
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+[[:xdigit:]]+[012][[:space:]]+IMM14[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+IMM22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+IMM64[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+GPREL22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+GPREL64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PLTOFF22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PLTOFF64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+FPTR64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL60B[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL21B[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL21M[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL21F[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF_FPTR22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF_FPTR64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+PCREL64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF22X[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LDXMOV[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+TPREL14[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+TPREL22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+TPREL64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF_TPREL22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF_DTPMOD22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+DTPREL14[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+DTPREL22[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+DTPREL64I[[:space:]]+esym
+[[:xdigit:]]+[012][[:space:]]+LTOFF_DTPREL22[[:space:]]+esym
+
+RELOCATION RECORDS FOR \[\.rodata\.4\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+[[:xdigit:]]+[048cC][[:space:]]+DIR32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+GPREL32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+FPTR32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+PCREL32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+LTOFF_FPTR32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+SEGREL32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+SECREL32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+LTV32[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[048cC][[:space:]]+DTPREL32[LM]SB[[:space:]]+esym
+
+RELOCATION RECORDS FOR \[\.rodata\.8\]:
+OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
+[[:xdigit:]]+[08][[:space:]]+DIR64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+GPREL64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+PLTOFF64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+FPTR64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+PCREL64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+LTOFF_FPTR64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+SEGREL64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+SECREL64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+LTV64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+IPLT[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+TPREL64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+DTPMOD64[LM]SB[[:space:]]+esym
+[[:xdigit:]]+[08][[:space:]]+DTPREL64[LM]SB[[:space:]]+esym
diff --git a/gas/testsuite/gas/ia64/reloc.s b/gas/testsuite/gas/ia64/reloc.s
new file mode 100644
index 000000000000..e5caa7c6d2f3
--- /dev/null
+++ b/gas/testsuite/gas/ia64/reloc.s
@@ -0,0 +1,82 @@
+	.global esym
+	.section .rodata.4, "a", @progbits
+	.section .rodata.8, "a", @progbits
+	.text
+_start:
+	adds		r1 = esym, r0
+	mov		r2 = esym
+	movl		r3 = esym
+	.xdata4 .rodata.4, esym
+	.xdata8 .rodata.8, esym
+
+	mov		r2 = @gprel(esym)
+	movl		r3 = @gprel(esym)
+	.xdata4 .rodata.4, @gprel(esym)
+	.xdata8 .rodata.8, @gprel(esym)
+
+	mov		r2 = @ltoff(esym)
+	movl		r3 = @ltoff(esym)
+
+	mov		r2 = @pltoff(esym)
+	movl		r3 = @pltoff(esym)
+	.xdata8 .rodata.8, @pltoff(esym)
+
+	movl		r3 = @fptr(esym)
+	.xdata4 .rodata.4, @fptr(esym)
+	.xdata8 .rodata.8, @fptr(esym)
+
+	brl.call.sptk	b1 = esym
+	br.call.sptk	b2 = esym
+	chk.s		r0, esym
+	fchkf		esym
+	.xdata4 .rodata.4, @pcrel(esym)
+	.xdata8 .rodata.8, @pcrel(esym)
+
+	mov		r2 = @ltoff(@fptr(esym))
+	movl		r3 = @ltoff(@fptr(esym))
+	.xdata4 .rodata.4, @ltoff(@fptr(esym))
+	.xdata8 .rodata.8, @ltoff(@fptr(esym))
+
+	.xdata4 .rodata.4, @segrel(esym)
+	.xdata8 .rodata.8, @segrel(esym)
+
+	.xdata4 .rodata.4, @secrel(esym)
+	.xdata8 .rodata.8, @secrel(esym)
+
+	// REL32 only in executables
+	// REL64 only in executables
+
+	.xdata4 .rodata.4, @ltv(esym)
+	.xdata8 .rodata.8, @ltv(esym)
+
+//todo PCREL21BI
+	mov		r2 = @pcrel(esym)
+	movl		r3 = @pcrel(esym)
+
+	.xdata16 .rodata.8, @iplt(esym)
+
+	// COPY only in executables
+
+//todo	movl		r3 = -esym
+
+	mov		r2 = @ltoffx(esym)
+	ld8.mov		r3 = [r2], esym
+
+	adds		r1 = @tprel(esym), r0
+	mov		r2 = @tprel(esym)
+	movl		r3 = @tprel(esym)
+	.xdata8 .rodata.8, @tprel(esym)
+
+	mov		r2 = @ltoff(@tprel(esym))
+
+	.xdata8 .rodata.8, @dtpmod(esym)
+
+	mov		r2 = @ltoff(@dtpmod(esym))
+
+	adds		r1 = @dtprel(esym), r0
+	mov		r2 = @dtprel(esym)
+	movl		r3 = @dtprel(esym)
+	.xdata4 .rodata.4, @dtprel(esym)
+	.xdata8 .rodata.8, @dtprel(esym)
+
+	mov		r2 = @ltoff(@dtprel(esym))
diff --git a/gas/testsuite/gas/ia64/rotX.l b/gas/testsuite/gas/ia64/rotX.l
new file mode 100644
index 000000000000..1159774575c4
--- /dev/null
+++ b/gas/testsuite/gas/ia64/rotX.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*.s:[[:digit:]]+: Error: [Nn]umber of elements must be positive
+.*.s:[[:digit:]]+: Error: [Nn]umber of elements must be positive
+.*.s:[[:digit:]]+: Error: [Bb]ad or irreducible absolute expression
+#pass
diff --git a/gas/testsuite/gas/ia64/rotX.s b/gas/testsuite/gas/ia64/rotX.s
new file mode 100644
index 000000000000..48320f6d070d
--- /dev/null
+++ b/gas/testsuite/gas/ia64/rotX.s
@@ -0,0 +1,4 @@
+.regstk 0, 8, 0, 8
+.rotr a[8], b[-8]
+.rotp c[8], d[0]
+.rotf e[8], f[x]
diff --git a/gas/testsuite/gas/ia64/slot2.l b/gas/testsuite/gas/ia64/slot2.l
new file mode 100644
index 000000000000..f52299a1363a
--- /dev/null
+++ b/gas/testsuite/gas/ia64/slot2.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:11: Error: .* must be last in bundle
+.*:16: Error: .* must be last in bundle
diff --git a/gas/testsuite/gas/ia64/slot2.s b/gas/testsuite/gas/ia64/slot2.s
new file mode 100644
index 000000000000..030db8e06957
--- /dev/null
+++ b/gas/testsuite/gas/ia64/slot2.s
@@ -0,0 +1,18 @@
+.explicit
+_start:
+{.mib
+	br.cloop.sptk	start
+}	;;
+{.mib
+	nop		0
+	br.cloop.sptk	start
+}	;;
+{.mbb
+	br.cloop.sptk	start
+	nop		0
+}	;;
+{.mbb
+	nop		0
+	br.cloop.sptk	start
+	nop		0
+}	;;
diff --git a/gas/testsuite/gas/ia64/strange.d b/gas/testsuite/gas/ia64/strange.d
new file mode 100644
index 000000000000..287d073762df
--- /dev/null
+++ b/gas/testsuite/gas/ia64/strange.d
@@ -0,0 +1,19 @@
+#objdump: -s
+#name: ia64 strange
+
+.*: +file format .*
+
+Contents of section .text:
+ 0000 0c000000 01001000 00020000 00000400  .*
+ 0010 04000000 01000000 00000020 00000400  .*
+ 0020 0c000000 01002000 00020000 00000400  .*
+ 0030 04000000 01000000 00000040 00000400  .*
+ 0040 1c000000 01003000 00020000 00000020  .*
+ 0050 04000000 01000000 00000080 00000400  .*
+ 0060 04000000 01000000 000000a0 00000400  .*
+ 0070 04000000 01000000 000000c0 00000400  .*
+ 0080 04000000 01000000 000000e0 00000400  .*
+ 0090 0e000000 01000000 00020000 01000400  .*
+ 00a0 1d000000 01009000 00020080 00008400  .*
+Contents of section .data:
+ 0000 ffffff                               .*
diff --git a/gas/testsuite/gas/ia64/strange.s b/gas/testsuite/gas/ia64/strange.s
new file mode 100644
index 000000000000..9a19b0461287
--- /dev/null
+++ b/gas/testsuite/gas/ia64/strange.s
@@ -0,0 +1,18 @@
+.explicit
+.text
+_start:
+{.mfi
+	nop.f		1 } nop.x 1
+{.mfi
+	nop.f		2
+}	nop.x		2
+{.mfb
+	nop.f		3
+.xdata1 .data, -1 } .xdata1 .data, -1
+	nop.x		4 { nop.x 5
+} {	nop.x		6 }
+	nop.x		7 {.mmf
+	nop.f		8
+} .xdata1 .data, -1 { .mfb
+	nop.f		9
+	br.ret.sptk	rp }
diff --git a/gas/testsuite/gas/ia64/tls.d b/gas/testsuite/gas/ia64/tls.d
index 57e07678e74b..3f03b25291b6 100644
--- a/gas/testsuite/gas/ia64/tls.d
+++ b/gas/testsuite/gas/ia64/tls.d
@@ -1,3 +1,4 @@
+#as: -xnone -mtune=itanium1
 #objdump: -dr
 #name: ia64 tls
 
diff --git a/gas/testsuite/gas/ia64/unwind-bad.l b/gas/testsuite/gas/ia64/unwind-bad.l
new file mode 100644
index 000000000000..7009fab54afd
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-bad.l
@@ -0,0 +1,51 @@
+.*: Assembler messages:
+.*:8: Error: First operand to \.save\.g must be a positive 4-bit constant
+.*:10: Error: First operand to \.save\.g must be a positive 4-bit constant
+.*:12: Error: First operand to \.save\.g must be a positive 4-bit constant
+.*:16: Warning: Previous .save incomplete
+#FIXME .*:18: Error: Register r4 was already saved
+.*:20: Error: Operand to \.save\.f must be a positive 20-bit constant
+.*:22: Error: Operand to \.save\.f must be a positive 20-bit constant
+.*:24: Error: Operand to \.save\.f must be a positive 20-bit constant
+.*:28: Warning: Previous .save incomplete
+#FIXME .*:30: Error: Register f2 was already saved
+.*:32: Error: First operand to \.save\.b must be a positive 5-bit constant
+.*:34: Error: First operand to \.save\.b must be a positive 5-bit constant
+.*:36: Error: First operand to \.save\.b must be a positive 5-bit constant
+.*:40: Warning: Previous .save incomplete
+#FIXME .*:42: Error: Register b1 was already saved
+.*:44: Error: Operand 2 to \.spillreg must be a writable register
+.*:46: Error: Operand 1 to \.spillreg must be a preserved register
+.*:48: Error: Operand 1 to \.spillreg must be a preserved register
+.*:50: Error: Operand 1 to \.spillreg must be a preserved register
+.*:52: Error: Operand 2 to \.spillreg must be a writable register
+.*:54: Error: Operand 2 to \.spillreg must be a writable register
+.*:56: Error: Operand 1 to \.spillreg must be a preserved register
+#FIXME .*:58: Error: Floating point register cannot be spilled to general register
+#FIXME .*:60: Error: Floating point register cannot be spilled to branch register
+.*:62: Warning: Pointless use of p0 as first operand to \.spillreg\.p
+.*:64: Error: Operand 3 to \.spillreg.p must be a writable register
+.*:66: Error: Operand 3 to \.spillreg.p must be a writable register
+.*:68: Warning: Pointless use of p0 as first operand to \.restorereg\.p
+.*:78: Error: Operands to \.save\.gf may not be both zero
+.*:80: Error: First operand to \.save\.gf must be a non-negative 4-bit constant
+.*:82: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant
+.*:84: Error: First operand to \.save\.gf must be a non-negative 4-bit constant
+.*:86: Error: Second operand to \.save\.gf must be a non-negative 20-bit constant
+.*:90: Warning: Previous .save incomplete
+#FIXME .*:92: Error: Register r4 was already saved
+#FIXME .*:94: Error: Register f2 was already saved
+.*:98: Error: Epilogue count of 2 exceeds number of nested prologues \(1\)
+.*:100: Error: Missing \.label_state 2
+.*:108: Error: First operand to \.save\.g must be a positive 4-bit constant
+#FIXME .*:110: Error: Second operand to \.save\.g must be a writable general registers
+.*:112: Error: Second operand to \.save\.g must be the first of 2 general registers
+.*:115: Error: First operand to \.save\.b must be a positive 5-bit constant
+#FIXME .*:117: Error: Second operand to \.save\.b must be a writable general registers
+.*:119: Error: Second operand to \.save\.b must be the first of 2 general registers
+.*:128: Error: First operand to \.prologue must be a positive 4-bit constant
+.*:134: Warning: Pointless use of zero first operand to \.prologue
+.*:140: Error: First operand to \.prologue must be a positive 4-bit constant
+#FIXME .*:141: Error: Operand to \.vframe must be a writable general registers
+#FIXME .*:147: Error: Second operand to \.prologue must be a writable general registers
+.*:153: Error: Second operand to \.prologue must be the first of 2 general registers
diff --git a/gas/testsuite/gas/ia64/unwind-bad.s b/gas/testsuite/gas/ia64/unwind-bad.s
new file mode 100644
index 000000000000..9a4b7beab509
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-bad.s
@@ -0,0 +1,155 @@
+.text
+
+.proc full1
+full1:
+
+.prologue
+.spill 0
+.save.g 0
+	nop		0
+.save.g 0x10
+	nop		0
+.save.g -1
+	nop		0
+.save.g 0x3
+	nop		0
+.save.g 0x4
+	nop		0
+.save.g 0x1
+	nop		0
+.save.f 0
+	nop		0
+.save.f 0x100000
+	nop		0
+.save.f -1
+	nop		0
+.save.f 0x3
+	nop		0
+.save.f 0x4
+	nop		0
+.save.f 0x1
+	nop		0
+.save.b 0
+	nop		0
+.save.b 0x20
+	nop		0
+.save.b -1
+	nop		0
+.save.b 0x3
+	nop		0
+.save.b 0x4
+	nop		0
+.save.b 0x1
+	nop		0
+.spillreg r4, r0
+	nop		0
+.spillreg r3, r2
+	nop		0
+.spillreg r8, r9
+	nop		0
+.spillreg b6, r10
+	nop		0
+.spillreg f2, f0
+	nop		0
+.spillreg f3, f1
+	nop		0
+.spillreg f6, f7
+	nop		0
+.spillreg f4, r11
+	nop		0
+.spillreg f5, b0
+	nop		0
+.spillreg.p p0, r4, r3
+	nop		0
+.spillreg.p p1, r4, r0
+	nop		0
+.spillreg.p p1, f16, f0
+	nop		0
+.restorereg.p p0, r4
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp full1
+
+.proc full2
+full2:
+.prologue
+.spill 0
+.save.gf 0, 0
+	nop		0
+.save.gf 0x10, 0
+	nop		0
+.save.gf 0, 0x100000
+	nop		0
+.save.gf ~0, 0
+	nop		0
+.save.gf 0, ~0
+	nop		0
+.save.gf 1, 1
+	nop		0
+.save.gf 2, 0
+	nop		0
+.save.gf 1, 0
+	nop		0
+.save.gf 0, 1
+	nop		0
+.body
+.label_state 1
+.restore sp, 1
+	nop.x		0
+.copy_state 2
+	br.ret.sptk	rp
+.endp full2
+
+.proc full3
+full3:
+.prologue
+.spill 0
+.save.g 0x10, r16
+	nop		0
+.save.g 0x01, r0
+	nop		0
+.save.g 0x06, r127
+	nop		0
+	nop		0
+.save.b 0x20, r16
+	nop		0
+.save.b 0x01, r0
+	nop		0
+.save.b 0x18, r127
+	nop		0
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp full3
+
+.proc simple1
+simple1:
+.prologue 0x10, r2
+	br.ret.sptk	rp
+.endp simple1
+
+.proc simple2
+simple2:
+.prologue 0, r2
+	br.ret.sptk	rp
+.endp simple2
+
+.proc simple3
+simple3:
+.prologue -1, r2
+.vframe r0
+	br.ret.sptk	rp
+.endp simple3
+
+.proc simple4
+simple4:
+.prologue 0x1, r0
+	br.ret.sptk	rp
+.endp simple4
+
+.proc simple5
+simple5:
+.prologue 0xc, r127
+	br.ret.sptk	rp
+.endp simple5
diff --git a/gas/testsuite/gas/ia64/unwind-err.l b/gas/testsuite/gas/ia64/unwind-err.l
new file mode 100644
index 000000000000..71cca18d592f
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-err.l
@@ -0,0 +1,35 @@
+.*: Assembler messages:
+.*:1: Error: .endp outside of procedure
+.*:2: Error: .personality outside of procedure
+.*:3: Error: .unwentry outside of procedure
+.*:4: Error: .unwabi outside of procedure
+.*:5: Error: .handlerdata outside of procedure
+.*:6: Error: .prologue outside of procedure
+.*:7: Error: .body outside of procedure
+.*:8: Error: .spillreg outside of procedure
+.*:9: Error: .spillreg.p outside of procedure
+.*:10: Error: .spillsp outside of procedure
+.*:11: Error: .spillsp.p outside of procedure
+.*:12: Error: .spillpsp outside of procedure
+.*:13: Error: .spillpsp.p outside of procedure
+.*:14: Error: .restorereg outside of procedure
+.*:15: Error: .restorereg.p outside of procedure
+.*:24: Error: .label_state outside of body region
+.*:25: Error: .copy_state outside of body region
+.*:26: Error: .fframe outside of prologue
+.*:27: Error: .vframe outside of prologue
+.*:28: Error: .vframesp outside of prologue
+.*:29: Error: .spill outside of prologue
+.*:30: Error: .restore outside of body region
+.*:31: Error: .save outside of prologue
+.*:32: Error: .savesp outside of prologue
+.*:33: Error: .savepsp outside of prologue
+.*:34: Error: .save.g outside of prologue
+.*:35: Error: .save.gf outside of prologue
+.*:36: Error: .save.f outside of prologue
+.*:37: Error: .save.b outside of prologue
+.*:38: Error: .altrp outside of prologue
+.*:43: Error: .prologue within prologue
+.*:51: Error: .body outside of procedure
+.*:58: Warning: Initial .prologue.*
+.*:65: Warning: Initial .body.*
diff --git a/gas/testsuite/gas/ia64/unwind-err.s b/gas/testsuite/gas/ia64/unwind-err.s
new file mode 100644
index 000000000000..81b25974644b
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-err.s
@@ -0,0 +1,67 @@
+.endp	xyz
+.personality personality
+.unwentry
+.unwabi @svr4, 0
+.handlerdata
+.prologue
+.body
+.spillreg r4, r8
+.spillreg.p p1, r4, r8
+.spillsp r5, 0
+.spillsp.p p2, r5, 0
+.spillpsp r6, 0
+.spillpsp.p p2, r6, 0
+.restorereg r4
+.restorereg.p p1, r4
+
+.proc	personality
+personality:
+.endp	personality
+
+.proc	start
+start:
+
+.label_state 1
+.copy_state 1
+.fframe 0
+.vframe r0
+.vframesp 0
+.spill 0
+.restore sp
+.save rp, r0
+.savesp pr, 0
+.savepsp ar.fpsr, 0
+.save.g 2
+.save.gf 2,2
+.save.f 2
+.save.b 2
+.altrp b7
+.body
+
+
+	.prologue
+	.prologue
+	.save		ar.lc, r31
+	mov		r31 = ar.lc
+	.body
+	.body
+	br.ret.sptk	rp
+.personality personality
+.handlerdata
+.body
+
+.endp	start
+
+.proc	late_prologue
+late_prologue:
+	nop	0
+	.prologue
+	nop	0
+.endp	late_prologue
+
+.proc	late_body
+late_body:
+	nop	0
+	.body
+	nop	0
+.endp	late_body
diff --git a/gas/testsuite/gas/ia64/unwind-ok.d b/gas/testsuite/gas/ia64/unwind-ok.d
new file mode 100644
index 000000000000..e60c7cc94b87
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-ok.d
@@ -0,0 +1,224 @@
+#readelf: -u
+#name: ia64 unwind descriptors
+
+Unwind section '\.IA_64\.unwind' at offset 0x[[:xdigit:]]+ contains 8 entries:
+
+<full1>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x3 \( ?ehandler uhandler\), len=[[:digit:]]+ bytes
+[[:space:]]*R1:prologue\(rlen=8\)
+[[:space:]]*P6:fr_mem\(frmask=\[f2,f5\]\)
+[[:space:]]*P6:gr_mem\(grmask=\[r4,r7\]\)
+[[:space:]]*P1:br_mem\(brmask=\[b1,b5\]\)
+[[:space:]]*P4:spill_mask\(imask=\[rfb,rfb,--\]\)
+[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\)
+[[:space:]]*P3:rp_br\(reg=b7\)
+[[:space:]]*P10:unwabi\(abi=@svr4,context=0x00\)
+[[:space:]]*R1:body\(rlen=25\)
+[[:space:]]*X2:spill_reg\(t=0,reg=r4,treg=r2\)
+[[:space:]]*X4:spill_reg_p\(qp=p1,t=1,reg=r7,treg=r31\)
+[[:space:]]*X1:spill_sprel\(reg=b1,t=2,spoff=0x8\)
+[[:space:]]*X3:spill_sprel_p\(qp=p2,t=3,reg=b5,spoff=0x10\)
+[[:space:]]*X1:spill_psprel\(reg=f2,t=4,pspoff=0x10-0x28\)
+[[:space:]]*X3:spill_psprel_p\(qp=p4,t=5,reg=f5,pspoff=0x10-0x30\)
+[[:space:]]*X2:restore\(t=6,reg=f16\)
+[[:space:]]*X4:restore_p\(qp=p8,t=7,reg=f31\)
+[[:space:]]*X2:spill_reg\(t=8,reg=ar\.bsp,treg=r16\)
+[[:space:]]*X2:spill_reg\(t=9,reg=ar\.bspstore,treg=r17\)
+[[:space:]]*X2:spill_reg\(t=10,reg=ar\.fpsr,treg=r18\)
+[[:space:]]*X2:spill_reg\(t=11,reg=ar\.lc,treg=r19\)
+[[:space:]]*X2:spill_reg\(t=12,reg=ar\.pfs,treg=r20\)
+[[:space:]]*X2:spill_reg\(t=13,reg=ar\.rnat,treg=r21\)
+[[:space:]]*X2:spill_reg\(t=14,reg=ar\.unat,treg=r22\)
+[[:space:]]*X2:spill_reg\(t=15,reg=psp,treg=r23\)
+[[:space:]]*X2:spill_reg\(t=16,reg=pr,treg=r24\)
+[[:space:]]*X2:spill_reg\(t=17,reg=rp,treg=r25\)
+[[:space:]]*X2:spill_reg\(t=18,reg=@priunat,treg=r26\)
+[[:space:]]*B1:label_state\(label=1\)
+[[:space:]]*B2:epilogue\(t=4,ecount=0\)
+[[:space:]]*B1:copy_state\(label=1\)
+#...
+<full2>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R2:prologue_gr\(mask=\[rp,psp,pr\],grsave=r8,rlen=14\)
+[[:space:]]*P5:frgr_mem\(grmask=\[r4,r7\],frmask=\[f2,f31\]\)
+[[:space:]]*P4:spill_mask\(imask=\[frb,bfr,---,---,--\]\)
+[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\)
+[[:space:]]*P2:br_gr\(brmask=\[b1,b5\],gr=r32\)
+[[:space:]]*X2:spill_reg\(t=6,reg=f31,treg=f31\)
+[[:space:]]*X4:spill_reg_p\(qp=p63,t=7,reg=f16,treg=f0\)
+[[:space:]]*X1:spill_sprel\(reg=f5,t=8,spoff=0x20\)
+[[:space:]]*X3:spill_sprel_p\(qp=p31,t=9,reg=f2,spoff=0x18\)
+[[:space:]]*X1:spill_psprel\(reg=b5,t=10,pspoff=0x10-0x20\)
+[[:space:]]*X3:spill_psprel_p\(qp=p15,t=11,reg=b1,pspoff=0x10-0x18\)
+[[:space:]]*X2:restore\(t=12,reg=r7\)
+[[:space:]]*X4:restore_p\(qp=p7,t=13,reg=r4\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=0\)
+[[:space:]]*R1:prologue\(rlen=0\)
+[[:space:]]*R1:body\(rlen=7\)
+[[:space:]]*B4:label_state\(label=32\)
+[[:space:]]*B3:epilogue\(t=4,ecount=32\)
+[[:space:]]*B4:copy_state\(label=32\)
+#...
+<full3>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R3:prologue\(rlen=33\)
+[[:space:]]*P4:spill_mask\(imask=\[rrb,brr,bb-,---,---,---,---,---,---,---,---\]\)
+[[:space:]]*P7:spill_base\(pspoff=0x10-0x10\)
+[[:space:]]*P9:gr_gr\(grmask=\[r4,r5\],r32\)
+[[:space:]]*P2:br_gr\(brmask=\[b1,b2\],gr=r34\)
+[[:space:]]*P9:gr_gr\(grmask=\[r6,r7\],r124\)
+[[:space:]]*P2:br_gr\(brmask=\[b4,b5\],gr=r126\)
+[[:space:]]*R3:body\(rlen=33\)
+#...
+<fframe>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R1:prologue\(rlen=1\)
+[[:space:]]*P7:mem_stack_f\(t=0,size=0\)
+[[:space:]]*R1:body\(rlen=2\)
+#...
+<vframe>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R1:prologue\(rlen=11\)
+[[:space:]]*P7:mem_stack_v\(t=0\)
+[[:space:]]*P3:psp_gr\(reg=r16\)
+[[:space:]]*P8:bsp_when\(t=1\)
+[[:space:]]*P3:bsp_gr\(reg=r17\)
+[[:space:]]*P8:bspstore_when\(t=2\)
+[[:space:]]*P3:bspstore_gr\(reg=r18\)
+[[:space:]]*P7:fpsr_when\(t=3\)
+[[:space:]]*P3:fpsr_gr\(reg=r19\)
+[[:space:]]*P7:lc_when\(t=4\)
+[[:space:]]*P3:lc_gr\(reg=r20\)
+[[:space:]]*P7:pfs_when\(t=5\)
+[[:space:]]*P3:pfs_gr\(reg=r21\)
+[[:space:]]*P8:rnat_when\(t=6\)
+[[:space:]]*P3:rnat_gr\(reg=r22\)
+[[:space:]]*P7:unat_when\(t=7\)
+[[:space:]]*P3:unat_gr\(reg=r23\)
+[[:space:]]*P7:pr_when\(t=8\)
+[[:space:]]*P3:pr_gr\(reg=r24\)
+[[:space:]]*P8:priunat_when_gr\(t=9\)
+[[:space:]]*P3:priunat_gr\(reg=r25\)
+[[:space:]]*P7:rp_when\(t=10\)
+[[:space:]]*P3:rp_gr\(reg=r26\)
+[[:space:]]*R1:body\(rlen=1\)
+#...
+<vframesp>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R1:prologue\(rlen=11\)
+[[:space:]]*P7:mem_stack_v\(t=0\)
+[[:space:]]*P7:psp_sprel\(spoff=0x0\)
+[[:space:]]*P8:bsp_when\(t=1\)
+[[:space:]]*P8:bsp_sprel\(spoff=0x8\)
+[[:space:]]*P8:bspstore_when\(t=2\)
+[[:space:]]*P8:bspstore_sprel\(spoff=0x10\)
+[[:space:]]*P7:fpsr_when\(t=3\)
+[[:space:]]*P8:fpsr_sprel\(spoff=0x18\)
+[[:space:]]*P7:lc_when\(t=4\)
+[[:space:]]*P8:lc_sprel\(spoff=0x20\)
+[[:space:]]*P7:pfs_when\(t=5\)
+[[:space:]]*P8:pfs_sprel\(spoff=0x28\)
+[[:space:]]*P8:rnat_when\(t=6\)
+[[:space:]]*P8:rnat_sprel\(spoff=0x30\)
+[[:space:]]*P7:unat_when\(t=7\)
+[[:space:]]*P8:unat_sprel\(spoff=0x38\)
+[[:space:]]*P7:pr_when\(t=8\)
+[[:space:]]*P8:pr_sprel\(spoff=0x40\)
+[[:space:]]*P8:priunat_when_mem\(t=9\)
+[[:space:]]*P8:priunat_sprel\(spoff=0x48\)
+[[:space:]]*P7:rp_when\(t=10\)
+[[:space:]]*P8:rp_sprel\(spoff=0x50\)
+[[:space:]]*R1:body\(rlen=1\)
+#...
+<psp>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+[[:space:]]*R1:prologue\(rlen=11\)
+[[:space:]]*P7:mem_stack_v\(t=0\)
+[[:space:]]*P7:psp_sprel\(spoff=0x0\)
+[[:space:]]*P8:bsp_when\(t=1\)
+[[:space:]]*P8:bsp_psprel\(pspoff=0x10-0x18\)
+[[:space:]]*P8:bspstore_when\(t=2\)
+[[:space:]]*P8:bspstore_psprel\(pspoff=0x10-0x20\)
+[[:space:]]*P7:fpsr_when\(t=3\)
+[[:space:]]*P7:fpsr_psprel\(pspoff=0x10-0x28\)
+[[:space:]]*P7:lc_when\(t=4\)
+[[:space:]]*P7:lc_psprel\(pspoff=0x10-0x30\)
+[[:space:]]*P7:pfs_when\(t=5\)
+[[:space:]]*P7:pfs_psprel\(pspoff=0x10-0x38\)
+[[:space:]]*P8:rnat_when\(t=6\)
+[[:space:]]*P8:rnat_psprel\(pspoff=0x10-0x40\)
+[[:space:]]*P7:unat_when\(t=7\)
+[[:space:]]*P7:unat_psprel\(pspoff=0x10-0x48\)
+[[:space:]]*P7:pr_when\(t=8\)
+[[:space:]]*P7:pr_psprel\(pspoff=0x10-0x50\)
+[[:space:]]*P8:priunat_when_mem\(t=9\)
+[[:space:]]*P8:priunat_psprel\(pspoff=0x10-0x58\)
+[[:space:]]*P7:rp_when\(t=10\)
+[[:space:]]*P7:rp_psprel\(pspoff=0x10-0x60\)
+[[:space:]]*R1:body\(rlen=1\)
+#...
+<simple>: \[0x[[:xdigit:]]*0-0x[[:xdigit:]]*0\], info at \+0x[[:xdigit:]]*[08]
+[[:space:]]*v[[:digit:]]+, flags=0x0( \(\))?, len=[[:digit:]]+ bytes
+#pass
diff --git a/gas/testsuite/gas/ia64/unwind-ok.s b/gas/testsuite/gas/ia64/unwind-ok.s
new file mode 100644
index 000000000000..f2cc0cfffdad
--- /dev/null
+++ b/gas/testsuite/gas/ia64/unwind-ok.s
@@ -0,0 +1,272 @@
+.text
+.proc personality
+personality:
+	br.ret.sptk	rp
+.endp personality
+
+.proc full1
+full1:
+
+.prologue
+.spill 0
+.save.g 0x1
+	nop		0
+.save.f 0x1
+	nop		0
+.save.b 0x01
+	nop		0
+.save.g 0x8
+	nop		0
+.save.f 0x8
+	nop		0
+.save.b 0x10
+	nop		0
+.altrp b7
+	nop		0
+.unwabi @svr4, 0
+	nop		0
+
+.body
+.spillreg r4, r2
+	nop		0
+.spillreg.p p1, r7, r127
+	nop		0
+.spillsp b1, 0x08
+	nop		0
+.spillsp.p p2, b5, 0x10
+	nop		0
+.spillpsp f2, 0x18
+	nop		0
+.spillpsp.p p4, f5, 0x20
+	nop		0
+.restorereg f16
+	nop		0
+.restorereg.p p8, f31
+	nop		0
+
+.spillreg ar.bsp, r16
+	nop		0
+.spillreg ar.bspstore, r17
+	nop		0
+.spillreg ar.fpsr, r18
+	nop		0
+.spillreg ar.lc, r19
+	nop		0
+.spillreg ar.pfs, r20
+	nop		0
+.spillreg ar.rnat, r21
+	nop		0
+.spillreg ar.unat, r22
+	nop		0
+.spillreg psp, r23
+	nop		0
+.spillreg pr, r24
+	nop		0
+.spillreg rp, r25
+	nop		0
+.spillreg @priunat, r26
+	nop		0
+
+.label_state 1
+	nop		0
+.restore sp
+	nop.x		0
+.copy_state 1
+	br.ret.sptk	rp
+
+.personality personality
+.handlerdata
+	data4		-1
+	data4		0
+
+.endp full1
+
+.proc full2
+full2:
+
+.prologue 0xb, r8
+.spill 0
+.save.gf 0x1, 0x00001
+	nop		0
+	nop		0
+.save.b 0x11, r32
+	nop		0
+	nop		0
+.save.gf 0x8, 0x80000
+	nop		0
+	nop		0
+.spillreg f31, f127
+	nop		0
+.spillreg.p p63, f16, f32
+	nop		0
+.spillsp f5, 0x20
+	nop		0
+.spillsp.p p31, f2, 0x18
+	nop		0
+.spillpsp b5, 0x10
+	nop		0
+.spillpsp.p p15, b1, 0x08
+	nop		0
+.restorereg r7
+	nop		0
+.restorereg.p p7, r4
+	nop		0
+
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
+
+.body
+.label_state 32
+	nop		0
+.restore sp, 32
+	nop.x		0
+.copy_state 32
+	br.ret.sptk	rp
+.endp full2
+
+.proc full3
+full3:
+
+.prologue
+.spill 0
+.save.g 0x3, r32
+	nop		0
+	nop		0
+.save.b 0x03, r34
+	nop		0
+	nop		0
+.save.g 0xc, r124
+	nop		0
+	nop		0
+.save.b 0x18, r126
+	nop		0
+	nop		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+.body
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	nop.x		0
+	br.ret.sptk	rp
+.endp full3
+
+.proc fframe
+fframe:
+.prologue
+.fframe 0
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp fframe
+
+.proc vframe
+vframe:
+.prologue
+.vframe r16
+	nop		0
+.save ar.bsp, r17
+	nop		0
+.save ar.bspstore, r18
+	nop		0
+.save ar.fpsr, r19
+	nop		0
+.save ar.lc, r20
+	nop		0
+.save ar.pfs, r21
+	nop		0
+.save ar.rnat, r22
+	nop		0
+.save ar.unat, r23
+	nop		0
+.save pr, r24
+	nop		0
+.save @priunat, r25
+	nop		0
+.save rp, r26
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp vframe
+
+.proc vframesp
+vframesp:
+.prologue
+.vframesp 0
+	nop		0
+.savesp ar.bsp, 0x08
+	nop		0
+.savesp ar.bspstore, 0x10
+	nop		0
+.savesp ar.fpsr, 0x18
+	nop		0
+.savesp ar.lc, 0x20
+	nop		0
+.savesp ar.pfs, 0x28
+	nop		0
+.savesp ar.rnat, 0x30
+	nop		0
+.savesp ar.unat, 0x38
+	nop		0
+.savesp pr, 0x40
+	nop		0
+.savesp @priunat, 0x48
+	nop		0
+.savesp rp, 0x50
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp vframesp
+
+.proc psp
+psp:
+.prologue
+.vframesp 0
+	nop		0
+.savepsp ar.bsp, 0x08
+	nop		0
+.savepsp ar.bspstore, 0x10
+	nop		0
+.savepsp ar.fpsr, 0x18
+	nop		0
+.savepsp ar.lc, 0x20
+	nop		0
+.savepsp ar.pfs, 0x28
+	nop		0
+.savepsp ar.rnat, 0x30
+	nop		0
+.savepsp ar.unat, 0x38
+	nop		0
+.savepsp pr, 0x40
+	nop		0
+.savepsp @priunat, 0x48
+	nop		0
+.savepsp rp, 0x50
+	nop		0
+.body
+	br.ret.sptk	rp
+.endp psp
+
+.proc simple
+simple:
+.unwentry
+	br.ret.sptk	rp
+.endp simple
diff --git a/gas/testsuite/gas/ia64/xdata-ilp32.d b/gas/testsuite/gas/ia64/xdata-ilp32.d
new file mode 100644
index 000000000000..3958c71c1bf8
--- /dev/null
+++ b/gas/testsuite/gas/ia64/xdata-ilp32.d
@@ -0,0 +1,29 @@
+#readelf: -S
+#name: ia64 xdata (ilp32)
+#as: -milp32
+#source: xdata.s
+
+There are 19 section headers, starting at offset 0x[[:xdigit:]]+:
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] .text             PROGBITS        00000000 [[:xdigit:]]+ 000000 00  AX  0   0 16
+  \[ 2\] .data             PROGBITS        00000000 [[:xdigit:]]+ 000000 00  WA  0   0  1
+  \[ 3\] .bss              NOBITS          00000000 [[:xdigit:]]+ 000000 00  WA  0   0  1
+  \[ 4\] \.xdata1           PROGBITS        00000000 [[:xdigit:]]+ 000001 00   A  0   0  1
+  \[ 5\] \.xdata2           PROGBITS        00000000 [[:xdigit:]]+ 000004 00   A  0   0  2
+  \[ 6\] ,xdata3           PROGBITS        00000000 [[:xdigit:]]+ 000008 00   A  0   0  4
+  \[ 7\] \.xdata,4          PROGBITS        00000000 [[:xdigit:]]+ 000010 00   A  0   0  8
+  \[ 8\] "\.xdata5"         PROGBITS        00000000 [[:xdigit:]]+ 000020 00   A  0   0 16
+  \[ 9\] \.rela"\.xdata5"    RELA            00000000 [[:xdigit:]]+ 000018 0c     17   8  4
+  \[10\] \.xreal\\1          PROGBITS        00000000 [[:xdigit:]]+ 000008 00   A  0   0  4
+  \[11\] \.xreal\+2          PROGBITS        00000000 [[:xdigit:]]+ 000010 00   A  0   0  8
+  \[12\] \.xreal\(3\)         PROGBITS        00000000 [[:xdigit:]]+ 000014 00   A  0   0 16
+  \[13\] \.xreal\[4\]         PROGBITS        00000000 [[:xdigit:]]+ 000020 00   A  0   0 16
+  \[14\] \.xstr<1>          PROGBITS        00000000 [[:xdigit:]]+ 000003 00   A  0   0  1
+  \[15\] \.xstr\{2\}          PROGBITS        00000000 [[:xdigit:]]+ 000004 00   A  0   0  1
+  \[16\] .shstrtab         STRTAB          00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00      0   0  1
+  \[17\] .symtab           SYMTAB          00000000 [[:xdigit:]]+ [[:xdigit:]]+ 10     18  15  4
+  \[18\] .strtab           STRTAB          00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00      0   0  1
+#pass
diff --git a/gas/testsuite/gas/ia64/xdata.d b/gas/testsuite/gas/ia64/xdata.d
new file mode 100644
index 000000000000..e56d24e35e55
--- /dev/null
+++ b/gas/testsuite/gas/ia64/xdata.d
@@ -0,0 +1,47 @@
+#readelf: -S
+#name: ia64 xdata
+
+There are 19 section headers, starting at offset 0x[[:xdigit:]]+:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0000000000000000  [[:xdigit:]]+
+       0000000000000000  0000000000000000           0     0     0
+  \[ 1\] \.text             PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000000  0000000000000000  AX       0     0     16
+  \[ 2\] \.data             PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 3\] \.bss              NOBITS           0000000000000000  [[:xdigit:]]+
+       0000000000000000  0000000000000000  WA       0     0     1
+  \[ 4\] \.xdata1           PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000001  0000000000000000   A       0     0     1
+  \[ 5\] \.xdata2           PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000004  0000000000000000   A       0     0     2
+  \[ 6\] ,xdata3           PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000008  0000000000000000   A       0     0     4
+  \[ 7\] \.xdata,4          PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000010  0000000000000000   A       0     0     8
+  \[ 8\] "\.xdata5"         PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000020  0000000000000000   A       0     0     16
+  \[ 9\] \.rela"\.xdata5"    RELA             0000000000000000  [[:xdigit:]]+
+       0000000000000030  0000000000000018          17     8     8
+  \[10\] \.xreal\\1          PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000008  0000000000000000   A       0     0     4
+  \[11\] \.xreal\+2          PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000010  0000000000000000   A       0     0     8
+  \[12\] \.xreal\(3\)         PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000014  0000000000000000   A       0     0     16
+  \[13\] \.xreal\[4\]         PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000020  0000000000000000   A       0     0     16
+  \[14\] \.xstr<1>          PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000003  0000000000000000   A       0     0     1
+  \[15\] \.xstr\{2\}          PROGBITS         0000000000000000  [[:xdigit:]]+
+       0000000000000004  0000000000000000   A       0     0     1
+  \[16\] \.shstrtab         STRTAB           0000000000000000  [[:xdigit:]]+
+       [[:xdigit:]]+  0000000000000000           0     0     1
+  \[17\] \.symtab           SYMTAB           0000000000000000  [[:xdigit:]]+
+       [[:xdigit:]]+  0000000000000018          18    15     8
+  \[18\] \.strtab           STRTAB           0000000000000000  [[:xdigit:]]+
+       [[:xdigit:]]+  0000000000000000           0     0     1
+#pass
diff --git a/gas/testsuite/gas/ia64/xdata.s b/gas/testsuite/gas/ia64/xdata.s
new file mode 100644
index 000000000000..6929405f4fc0
--- /dev/null
+++ b/gas/testsuite/gas/ia64/xdata.s
@@ -0,0 +1,45 @@
+// Note that most of the section names used here aren't legal as operands
+// to either .section or .xdata/.xreal/.xstring (quoted strings aren't in
+// general), but since generic code accepts them for .section we also test
+// this here for our target specific directives. This could be viewed as a
+// shortcut of a pair of .section/.secalias for each of them.
+
+.section .xdata1, "a", @progbits
+.section ".xdata2", "a", @progbits
+.section ",xdata3", "a", @progbits
+.section ".xdata,4", "a", @progbits
+.section "\".xdata5\"", "a", @progbits
+
+.section ".xreal\\1", "a", @progbits
+.section ".xreal+2", "a", @progbits
+.section ".xreal(3)", "a", @progbits
+.section ".xreal[4]", "a", @progbits
+
+.section ".xstr<1>", "a", @progbits
+.section ".xstr{2}", "a", @progbits
+
+.text
+
+.xdata1 .xdata1, 1
+.xdata2 ".xdata2", 2
+.xdata4 ",xdata3", 3
+.xdata8 ".xdata,4", 4
+.xdata16 "\".xdata5\"", @iplt(_start)
+
+.xdata2.ua ".xdata2", 2
+.xdata4.ua ",xdata3", 3
+.xdata8.ua ".xdata,4", 4
+.xdata16.ua "\".xdata5\"", @iplt(_start)
+
+.xreal4 ".xreal\\1", 1
+.xreal8 ".xreal+2", 2
+.xreal10 ".xreal(3)", 3
+.xreal16 ".xreal[4]", 4
+
+.xreal4.ua ".xreal\\1", 1
+.xreal8.ua ".xreal+2", 2
+.xreal10.ua ".xreal(3)", 3
+.xreal16.ua ".xreal[4]", 4
+
+.xstring ".xstr<1>", "abc"
+.xstringz ".xstr{2}", "xyz"
diff --git a/gas/testsuite/gas/ieee-fp/x930509a.exp b/gas/testsuite/gas/ieee-fp/x930509a.exp
index 933725d18f0b..d1325ecd6765 100644
--- a/gas/testsuite/gas/ieee-fp/x930509a.exp
+++ b/gas/testsuite/gas/ieee-fp/x930509a.exp
@@ -21,7 +21,7 @@ proc dotest {} {
     # float encoding is tested in c54x-specific tests.
     # No floating point support in assembly code for CRIS.
     setup_xfail "arc*-*-*" "cris-*-*" "*c30*-*-*" "*c54x*-*-*" "*c80*-*-*"
-    setup_xfail "vax*-*-*"
+    setup_xfail "vax*-*-*" "crisv32-*-*"
 
     if !$x then { fail "$testname (listing didn't match)" }
 }
diff --git a/gas/testsuite/gas/iq2000/allinsn.exp b/gas/testsuite/gas/iq2000/allinsn.exp
index 20354e012614..b53235f2114d 100644
--- a/gas/testsuite/gas/iq2000/allinsn.exp
+++ b/gas/testsuite/gas/iq2000/allinsn.exp
@@ -2,5 +2,4 @@
 
 if [istarget iq2000*-*-*] {
     run_dump_test "allinsn"
-    run_dump_test "q10allinsn"
 }
diff --git a/gas/testsuite/gas/iq2000/q10allinsn.d b/gas/testsuite/gas/iq2000/q10allinsn.d
deleted file mode 100644
index 6e9903a8d49e..000000000000
--- a/gas/testsuite/gas/iq2000/q10allinsn.d
+++ /dev/null
@@ -1,492 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10allinsn
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <add>:
-   0:	03 be 00 20 	add r0,r29,r30
-
-00000004 <addi>:
-   4:	20 00 ff fc 	addi r0,r0,0xfffc
-
-00000008 <addiu>:
-   8:	24 00 00 04 	addiu r0,r0,0x4
-
-0000000c <addu>:
-   c:	03 be 00 21 	addu r0,r29,r30
-
-00000010 <ado16>:
-  10:	03 be 00 29 	ado16 r0,r29,r30
-
-00000014 <and>:
-  14:	03 be 00 24 	and r0,r29,r30
-
-00000018 <andi>:
-  18:	30 00 de ad 	andi r0,r0,0xdead
-
-0000001c <andoi>:
-  1c:	b0 00 00 00 	andoi r0,r0,0x0
-
-00000020 <andoui>:
-  20:	bc 00 00 00 	andoui r0,r0,0x0
-
-00000024 <mrgb>:
-  24:	03 a0 00 2d 	mrgb r0,r29,r0,0x0
-
-00000028 <nor>:
-  28:	03 be 00 27 	nor r0,r29,r30
-
-0000002c <or>:
-  2c:	03 be 00 25 	or r0,r29,r30
-  30:	03 be 08 25 	or r1,r29,r30
-
-00000034 <ori>:
-  34:	34 00 ff ff 	ori r0,r0,0xffff
-
-00000038 <orui>:
-  38:	3c 20 00 00 	orui r0,r1,0x0
-
-0000003c <ram>:
-  3c:	9c 00 00 00 	ram r0,r0,0x0,0x0,0x0
-
-00000040 <sll>:
-  40:	00 00 00 00 	nop
-  44:	00 02 08 00 	sll r1,r2,0x0
-
-00000048 <sllv>:
-  48:	03 dd 00 04 	sllv r0,r29,r30
-
-0000004c <slmv>:
-  4c:	00 00 00 01 	slmv r0,r0,r0,0x0
-
-00000050 <slt>:
-  50:	03 be 00 2a 	slt r0,r29,r30
-
-00000054 <slti>:
-  54:	28 00 00 00 	slti r0,r0,0x0
-
-00000058 <sltiu>:
-  58:	2c 00 00 00 	sltiu r0,r0,0x0
-
-0000005c <sltu>:
-  5c:	03 be 00 2b 	sltu r0,r29,r30
-
-00000060 <sra>:
-  60:	00 00 00 03 	sra r0,r0,0x0
-
-00000064 <srav>:
-  64:	03 dd 00 07 	srav r0,r29,r30
-
-00000068 <srl>:
-  68:	00 00 00 02 	srl r0,r0,0x0
-
-0000006c <srlv>:
-  6c:	03 dd 00 06 	srlv r0,r29,r30
-
-00000070 <srmv>:
-  70:	00 00 00 05 	srmv r0,r0,r0,0x0
-
-00000074 <sub>:
-  74:	03 be 00 22 	sub r0,r29,r30
-
-00000078 <subu>:
-  78:	03 be 00 23 	subu r0,r29,r30
-
-0000007c <xor>:
-  7c:	00 00 00 26 	xor r0,r0,r0
-
-00000080 <xori>:
-  80:	38 00 00 00 	xori r0,r0,0x0
-
-00000084 <bbi>:
-  84:	70 00 ff ff 	bbi r0\(0x0\),84 <bbi>
-
-00000088 <bbil>:
-  88:	f0 00 ff fe 	bbil r0\(0x0\),84 <bbi>
-
-0000008c <bbinl>:
-  8c:	f8 00 ff fd 	bbinl r0\(0x0\),84 <bbi>
-
-00000090 <bbin>:
-  90:	78 00 ff fc 	bbin r0\(0x0\),84 <bbi>
-
-00000094 <bbv>:
-  94:	74 00 ff fb 	bbv r0,r0,84 <bbi>
-
-00000098 <bbvl>:
-  98:	f4 00 ff fa 	bbvl r0,r0,84 <bbi>
-
-0000009c <bbvn>:
-  9c:	7c 00 ff f9 	bbvn r0,r0,84 <bbi>
-
-000000a0 <bbvnl>:
-  a0:	fc 00 ff f8 	bbvnl r0,r0,84 <bbi>
-
-000000a4 <beq>:
-  a4:	10 00 ff f7 	beq r0,r0,84 <bbi>
-
-000000a8 <beql>:
-  a8:	50 00 ff f6 	beql r0,r0,84 <bbi>
-
-000000ac <bgez>:
-  ac:	04 01 ff f5 	bgez r0,84 <bbi>
-
-000000b0 <bgezal>:
-  b0:	04 11 ff f4 	bgezal r0,84 <bbi>
-
-000000b4 <bgezall>:
-  b4:	04 13 ff f3 	bgezall r0,84 <bbi>
-
-000000b8 <bgezl>:
-  b8:	04 03 ff f2 	bgezl r0,84 <bbi>
-
-000000bc <bgtz>:
-  bc:	04 05 ff f1 	bgtz r0,84 <bbi>
-
-000000c0 <bgtzal>:
-  c0:	04 15 ff f0 	bgtzal r0,84 <bbi>
-
-000000c4 <bgtzall>:
-  c4:	04 17 ff ef 	bgtzall r0,84 <bbi>
-
-000000c8 <bgtzl>:
-  c8:	04 07 ff ee 	bgtzl r0,84 <bbi>
-
-000000cc <blez>:
-  cc:	04 04 ff ed 	blez r0,84 <bbi>
-
-000000d0 <blezal>:
-  d0:	04 14 ff ec 	blezal r0,84 <bbi>
-
-000000d4 <blezall>:
-  d4:	04 16 ff eb 	blezall r0,84 <bbi>
-
-000000d8 <blezl>:
-  d8:	04 06 ff ea 	blezl r0,84 <bbi>
-
-000000dc <bltz>:
-  dc:	04 00 ff e9 	bltz r0,84 <bbi>
-
-000000e0 <bltzl>:
-  e0:	04 02 ff e8 	bltzl r0,84 <bbi>
-
-000000e4 <bltzal>:
-  e4:	04 10 ff e7 	bltzal r0,84 <bbi>
-
-000000e8 <bltzall>:
-  e8:	04 12 ff e6 	bltzall r0,84 <bbi>
-
-000000ec <bmb>:
-  ec:	18 00 ff e5 	bmb r0,r0,84 <bbi>
-
-000000f0 <bmb0>:
-  f0:	60 00 ff e4 	bmb0 r0,r0,84 <bbi>
-
-000000f4 <bmb1>:
-  f4:	64 00 ff e3 	bmb1 r0,r0,84 <bbi>
-
-000000f8 <bmb2>:
-  f8:	68 00 ff e2 	bmb2 r0,r0,84 <bbi>
-
-000000fc <bmb3>:
-  fc:	6c 00 ff e1 	bmb3 r0,r0,84 <bbi>
-
-00000100 <bmbl>:
- 100:	58 00 ff e0 	bmbl r0,r0,84 <bbi>
-
-00000104 <bne>:
- 104:	14 00 ff df 	bne r0,r0,84 <bbi>
-
-00000108 <bnel>:
- 108:	54 00 ff de 	bnel r0,r0,84 <bbi>
-
-0000010c <break>:
- 10c:	00 00 00 0d 	break
-
-00000110 <bri>:
- 110:	04 08 ff dc 	bri r0,84 <bbi>
-
-00000114 <brv>:
- 114:	04 09 ff db 	brv r0,84 <bbi>
-
-00000118 <chkhdr>:
- 118:	4c 00 00 26 	chkhdr r0,r0
-
-0000011c <j>:
- 11c:	08 00 00 00 	j 0 <add>
-			11c: R_IQ2000_OFFSET_16	.text\+0x124
-
-00000120 <jal>:
- 120:	0c 00 00 00 	jal r0,0 <add>
-			120: R_IQ2000_OFFSET_16	.text\+0x124
-
-00000124 <jalr>:
- 124:	00 00 00 09 	jalr r0,r0
-
-00000128 <jr>:
- 128:	00 00 00 08 	jr r0
-
-0000012c <lb>:
- 12c:	80 00 10 24 	lb r0,0x1024\(r0\)
-
-00000130 <lbu>:
- 130:	90 00 10 24 	lbu r0,0x1024\(r0\)
-
-00000134 <lh>:
- 134:	84 00 10 24 	lh r0,0x1024\(r0\)
-
-00000138 <lhu>:
- 138:	94 00 10 24 	lhu r0,0x1024\(r0\)
-
-0000013c <lui>:
- 13c:	3c 00 ff ff 	lui r0,0xffff
- 140:	3c 1d 00 00 	lui r29,0x0
-			140: R_IQ2000_HI16	foodata
- 144:	37 bd 00 00 	ori r29,r29,0x0
-			144: R_IQ2000_LO16	foodata
-
-00000148 <la>:
- 148:	3c 0b 00 00 	lui r11,0x0
-			148: R_IQ2000_HI16	foodata
- 14c:	35 6b 00 00 	ori r11,r11,0x0
-			14c: R_IQ2000_LO16	foodata
-
-00000150 <lw>:
- 150:	8c 00 10 24 	lw r0,0x1024\(r0\)
-
-00000154 <sb>:
- 154:	a0 00 10 24 	sb r0,0x1024\(r0\)
-
-00000158 <sh>:
- 158:	a4 00 10 24 	sh r0,0x1024\(r0\)
-
-0000015c <sw>:
- 15c:	ac 00 10 24 	sw r0,0x1024\(r0\)
-
-00000160 <swrd>:
- 160:	4c 1e e8 04 	swrd r29,r30
-
-00000164 <swrdl>:
- 164:	4c 1e e8 05 	swrdl r29,r30
-
-00000168 <swwr>:
- 168:	4f be 00 06 	swwr r0,r29,r30
-
-0000016c <swwru>:
- 16c:	4f be 00 07 	swwru r0,r29,r30
-
-00000170 <rba>:
- 170:	4f be 00 08 	rba r0,r29,r30
-
-00000174 <rbal>:
- 174:	4f be 00 09 	rbal r0,r29,r30
-
-00000178 <rbar>:
- 178:	4f be 00 0a 	rbar r0,r29,r30
-
-0000017c <dwrd>:
- 17c:	4c 1e e0 0c 	dwrd r28,r30
-
-00000180 <dwrdl>:
- 180:	4c 1e e0 0d 	dwrdl r28,r30
-
-00000184 <wba>:
- 184:	4f be 00 10 	wba r0,r29,r30
-
-00000188 <wbau>:
- 188:	4f be 00 11 	wbau r0,r29,r30
-
-0000018c <wbac>:
- 18c:	4f be 00 12 	wbac r0,r29,r30
-
-00000190 <crc32>:
- 190:	4f be 00 14 	crc32 r0,r29,r30
-
-00000194 <crc32b>:
- 194:	4f be 00 15 	crc32b r0,r29,r30
-
-00000198 <cfc>:
- 198:	4c 1e e8 00 	cfc r29,r30
-
-0000019c <lock>:
- 19c:	4c 1c e8 01 	lock r29,r28
-
-000001a0 <ctc>:
- 1a0:	4f be 00 02 	ctc r29,r30
-
-000001a4 <unlk>:
- 1a4:	4c 1e e8 03 	unlk r29,r30
-
-000001a8 <mcid>:
- 1a8:	4c 1d 00 20 	mcid r0,r29
-
-000001ac <dba>:
- 1ac:	4c 00 f0 22 	dba r30
-
-000001b0 <dbd>:
- 1b0:	4c 1e 00 21 	dbd r0,r0,r30
-
-000001b4 <dpwt>:
- 1b4:	4f c0 00 23 	dpwt r0,r30
-
-000001b8 <avail>:
- 1b8:	4c 00 f8 24 	avail r31
-
-000001bc <free>:
- 1bc:	4f c0 00 25 	free r0,r30
-
-000001c0 <tstod>:
- 1c0:	4f c0 00 27 	tstod r0,r30
-
-000001c4 <yield>:
- 1c4:	00 00 00 0e 	yield
-
-000001c8 <pkrla>:
- 1c8:	4f be 00 28 	pkrla r0,r29,r30
-
-000001cc <pkrlac>:
- 1cc:	4f be 00 2b 	pkrlac r0,r29,r30
-
-000001d0 <pkrlau>:
- 1d0:	4f be 00 29 	pkrlau r0,r29,r30
-
-000001d4 <pkrlah>:
- 1d4:	4f be 00 2a 	pkrlah r0,r29,r30
-
-000001d8 <cmphdr>:
- 1d8:	4c 00 f8 2c 	cmphdr r31
-
-000001dc <cam36>:
- 1dc:	4c 1e ec 09 	cam36 r29,r30,0x1,0x1
-
-000001e0 <cam72>:
- 1e0:	4c 1e 04 52 	cam72 r0,r30,0x2,0x2
-
-000001e4 <cam144>:
- 1e4:	4c 1d 04 9b 	cam144 r0,r29,0x3,0x3
-
-000001e8 <cam288>:
- 1e8:	4c 1d 04 a4 	cam144 r0,r29,0x4,0x4
-
-000001ec <cm32and>:
- 1ec:	4f be 00 ab 	cm32and r0,r29,r30
-
-000001f0 <cm32andn>:
- 1f0:	4f be 00 a3 	cm32andn r0,r29,r30
-
-000001f4 <cm32or>:
- 1f4:	4f be 00 aa 	cm32or r0,r29,r30
-
-000001f8 <cm32ra>:
- 1f8:	4f be 00 b0 	cm32ra r0,r29,r30
-
-000001fc <cm32rd>:
- 1fc:	4c 1e e8 a1 	cm32rd r29,r30
-
-00000200 <cm32ri>:
- 200:	4c 1d 00 a4 	cm32ri r0,r29
-
-00000204 <cm32rs>:
- 204:	4f be 00 a0 	cm32rs r0,r29,r30
-
-00000208 <cm32sa>:
- 208:	4f be 00 b8 	cm32sa r0,r29,r30
-
-0000020c <cm32sd>:
- 20c:	4c 1d 00 a9 	cm32sd r0,r29
-
-00000210 <cm32si>:
- 210:	4c 1d 00 ac 	cm32si r0,r29
-
-00000214 <cm32ss>:
- 214:	4f be 00 a8 	cm32ss r0,r29,r30
-
-00000218 <cm32xor>:
- 218:	4f be 00 a2 	cm32xor r0,r29,r30
-
-0000021c <cm64clr>:
- 21c:	4c 1c 00 85 	cm64clr r0,r28
-
-00000220 <cm64ra>:
- 220:	4f 9e 00 90 	cm64ra r0,r28,r30
-
-00000224 <cm64rd>:
- 224:	4c 1c 00 81 	cm64rd r0,r28
-
-00000228 <cm64ri>:
- 228:	4c 1c 00 84 	cm64ri r0,r28
-
-0000022c <cm64ria2>:
- 22c:	4f 9e 00 94 	cm64ria2 r0,r28,r30
-
-00000230 <cm64rs>:
- 230:	4f 9e 00 80 	cm64rs r0,r28,r30
-
-00000234 <cm64sa>:
- 234:	4f 9e 00 98 	cm64sa r0,r28,r30
-
-00000238 <cm64sd>:
- 238:	4c 1c 00 89 	cm64sd r0,r28
-
-0000023c <cm64si>:
- 23c:	4c 1c 00 8c 	cm64si r0,r28
-
-00000240 <cm64sia2>:
- 240:	4f 9e 00 9c 	cm64sia2 r0,r28,r30
-
-00000244 <cm64ss>:
- 244:	4f be 00 88 	cm64ss r0,r29,r30
-
-00000248 <cm128ria2>:
- 248:	4f be 00 95 	cm128ria2 r0,r29,r30
-
-0000024c <cm128ria3>:
- 24c:	4f be 00 90 	cm64ra r0,r29,r30
-
-00000250 <cm128ria4>:
- 250:	4f be 00 b7 	cm128ria4 r0,r29,r30,0x7
-
-00000254 <cm128sia2>:
- 254:	4f be 00 9d 	cm128sia2 r0,r29,r30
-
-00000258 <cm128sia3>:
- 258:	4f be 00 98 	cm64sa r0,r29,r30
-
-0000025c <cm128sia4>:
- 25c:	4f be 00 bf 	cm128sia4 r0,r29,r30,0x7
-
-00000260 <cm128vsa>:
- 260:	4f be 00 a6 	cm128vsa r0,r29,r30
-
-00000264 <pkrli>:
- 264:	4b fd 08 3f 	pkrli r1,r31,r29,0x3f
-
-00000268 <pkrlic>:
- 268:	4b fd 0b 3f 	pkrlic r1,r31,r29,0x3f
-
-0000026c <pkrlih>:
- 26c:	4b fd 0a 3f 	pkrlih r1,r31,r29,0x3f
-
-00000270 <pkrliu>:
- 270:	4b fd 09 3f 	pkrliu r1,r31,r29,0x3f
-
-00000274 <rbi>:
- 274:	4f bc 12 20 	rbi r2,r29,r28,0x20
-
-00000278 <rbil>:
- 278:	4f bc 13 20 	rbil r2,r29,r28,0x20
-
-0000027c <rbir>:
- 27c:	4f bc 11 20 	rbir r2,r29,r28,0x20
-
-00000280 <wbi>:
- 280:	4c 22 06 20 	wbi r0,r1,r2,0x20
-
-00000284 <wbic>:
- 284:	4c 22 05 20 	wbic r0,r1,r2,0x20
-
-00000288 <wbiu>:
- 288:	4c 22 07 20 	wbiu r0,r1,r2,0x20
diff --git a/gas/testsuite/gas/iq2000/q10allinsn.s b/gas/testsuite/gas/iq2000/q10allinsn.s
deleted file mode 100644
index bb5d0f6887ee..000000000000
--- a/gas/testsuite/gas/iq2000/q10allinsn.s
+++ /dev/null
@@ -1,641 +0,0 @@
-	.globl foodata	
-	.data
-	.align  2
-foodata: 
-	.word 42		
-	.text
-	.global add
-add:
-	add %0,%29,%30
-	.text
-	.global addi
-addi:
-	addi %0,%0,-4
-	.text
-	.global addiu
-addiu:
-	addiu %0,%0,4		
-	.text
-	.global addu
-addu:
-	addu %0,%29,%30
-	.text
-	.global ado16
-ado16:
-	ado16 %0,%29,%30
-	.text
-	.global and
-and:
-	and %0,%29,%30
-	.text
-	.global andi
-andi:
-	andi %0,%0,0xdead
-	.text
-	.global andoi
-andoi:
-	andoi %0,%0,0
-	.text
-	.global andoui
-andoui:
-	andoui %0,%0,0
-	.text
-	.global mrgb
-mrgb:
-	mrgb %0,%29,%0,0
-	.text
-	.global nor
-nor:
-	nor %0,%29,%30
-	.text
-	.global or
-or:
-	or %0,%29,%30
-	or %1,%29,%30
-	.text
-	.global ori
-ori:
-	ori %0,%0,-1
-	.text
-	.global orui
-orui:
-	orui %0,%1,0
-	.text
-	.global ram
-ram:
-	ram %0,%0,0,0,0
-	.text
-	.global sll
-sll:
-	sll %0,%0,0
-	sll %1,%2,0
-	.text
-	.global sllv
-sllv:
-	sllv %0,%29,%30
-	.text
-	.global slmv
-slmv:
-	slmv %0,%0,%0,0
-	.text
-	.global slt
-slt:
-	slt %0,%29,%30
-	.text
-	.global slti
-slti:
-	slti %0,%0,0
-	.text
-	.global sltiu
-sltiu:
-	sltiu %0,%0,0
-	.text
-	.global sltu
-sltu:
-	sltu %0,%29,%30
-	.text
-	.global sra
-sra:
-	sra %0,%0,0
-	.text
-	.global srav
-srav:
-	srav %0,%29,%30
-	.text
-	.global srl
-srl:
-	srl %0,%0,0
-	.text
-	.global srlv
-srlv:
-	srlv %0,%29,%30
-	.text
-	.global srmv
-srmv:
-	srmv %0,%0,%0,0
-	.text
-	.global sub
-sub:
-	sub %0,%29,%30
-	.text
-	.global subu
-subu:
-	subu %0,%29,%30
-	.text
-	.global xor
-xor:
-	xor %0,%0,%0
-	.global xori
-xori:
-	xori %0,%0,0
-footext:
-	.text
-	.global bbi
-bbi:
-	bbi %0(0),footext
-	.text
-	.global bbil
-bbil:	
-	bbil %0(0),footext
-	.text
-	.global bbinl
-bbinl:	
-	bbinl %0(0),footext
-	.text
-	.global bbin
-bbin:
-	bbin %0(0),footext
-	.text
-	.global bbv
-bbv:
-	bbv %0,%0,footext
-	.text
-	.global bbvl
-bbvl:	
-	bbvl %0,%0,footext
-	.text
-	.global bbvn
-bbvn:
-	bbvn %0,%0,footext
-	.text
-	.global bbvnl
-bbvnl:
-	bbvnl %0,%0,footext
-	.text
-	.global beq
-beq:
-	beq %0,%0,footext
-	.text
-	.global beql
-beql:
-	beql %0,%0,footext
-	.text
-	.global bgez
-bgez:
-	bgez %0,footext
-	.text
-	.global bgezal
-bgezal:
-	bgezal %0,footext
-	.text
-	.global bgezall
-bgezall:
-	bgezall %0,footext
-	.text
-	.global bgezl
-bgezl:
-	bgezl %0,footext
-	.text
-	.global bgtz
-bgtz:
-	bgtz %0,footext
-	.text
-	.global bgtzal
-bgtzal:
-	bgtzal %0,footext
-	.text
-	.global bgtzall
-bgtzall:
-	bgtzall %0,footext
-	.text
-	.global bgtzl
-bgtzl:
-	bgtzl %0,footext
-	.text
-	.global blez
-blez:
-	blez %0,footext
-	.text
-	.global blezal
-blezal:
-	blezal %0,footext
-	.text
-	.global blezall
-blezall:
-	blezall %0,footext
-	.text
-	.global blezl
-blezl:
-	blezl %0,footext
-	.text
-	.global bltz
-bltz:
-	bltz %0,footext
-	.text
-	.global bltzl
-bltzl:
-	bltzl %0,footext
-	.text
-	.global bltzal
-bltzal:
-	bltzal %0,footext
-	.text
-	.global bltzall
-bltzall:
-	bltzall %0,footext
-	.text
-	.global bmb
-bmb:
-	bmb %0,%0,footext
-	.text
-	.global bmb0
-bmb0:
-	bmb0 %0,%0,footext
-	.text
-	.global bmb1
-bmb1:
-	bmb1 %0,%0,footext
-	.text
-	.global bmb2
-bmb2:
-	bmb2 %0,%0,footext
-	.text
-	.global bmb3
-bmb3:
-	bmb3 %0,%0,footext
-	.text
-	.global bmbl
-bmbl:
-	bmbl %0,%0,footext
-	.text
-	.global bne
-bne:
-	bne %0,%0,footext
-	.text
-	.global bnel
-bnel:
-	bnel %0,%0,footext
-	.text
-	.global break
-break:
-	break
-	.text
-	.global bri
-bri:
-	bri %0,footext
-	.text
-	.global brv
-brv:
-	brv %0,footext
-	.text
-	.global chkhdr
-chkhdr:
-	chkhdr %0,%0
-	.text
-	.global j
-j:
-	j bartext
-	.text
-	.global jal
-jal:
-	jal %0,bartext
-bartext:
-	.text
-	.global jalr
-jalr:
-	jalr %0,%0
-	.text
-	.global jr
-jr:
-	jr %0
-	.text
-	.global lb
-lb:
-	lb %0,0x1024(%0)
-	.text
-	.global lbu
-lbu:
-	lbu %0,0x1024(%0)
-	.text
-	.global lh
-lh:
-	lh %0,0x1024(%0)
-	.text
-	.global lhu
-lhu:
-	lhu %0,0x1024(%0)
-	.text
-	.global lui
-lui:
-	lui %0,-1
-	lui %29,%hi(foodata)
-	ori %29,%29,%lo(foodata)
-	.text
-	.global la
-la:
-	la %11,foodata
-	.global lw
-lw:
-	lw %0,0x1024(%0)
-	.text
-	.global sb
-sb:
-	sb %0,0x1024(%0)
-	.text
-	.global sh
-sh:
-	sh %0,0x1024(%0)
-	.text
-	.global sw
-sw:
-	sw %0,0x1024(%0)
-	.text
-	.global swrd
-swrd:	
-	swrd %29,%30
-	.text
-	.global swrdl
-swrdl:		
-	swrdl %29,%30
-	.text
-	.global swwr
-swwr:		
-	swwr %0,%29,%30
-	.text
-	.global swwru
-swwru:		
-	swwru %0,%29,%30
-	.text
-	.global rba
-rba:		
-	rba %0,%29,%30
-	.text
-	.global rbal
-rbal:	
-	rbal %0,%29,%30
-	.text
-	.global rbar
-rbar:	
-	rbar %0,%29,%30
-	.text
-	.global dwrd
-dwrd:	
-	dwrd %28,%30
-	.text
-	.global dwrdl
-dwrdl:	
-	dwrdl %28,%30
-	.text
-	.global wba
-wba:						
-	wba %0,%29,%30
-	.text
-	.global wbau
-wbau:		
-	wbau %0,%29,%30
-	.text
-	.global wbac
-wbac:		
-	wbac %0,%29,%30
-	.text
-	.global crc32
-crc32:
-	crc32 %0,%29,%30
-	.text
-	.global crc32b
-crc32b:
-	crc32b %0,%29,%30
-	.text
-	.global cfc
-cfc:	
-	cfc %29,%30
-	.text
-	.global lock
-lock:	
-	lock %29,%28
-	.text
-	.global ctc
-ctc:					
-	ctc %29,%30
-	.text
-	.global unlk
-unlk:		
-	unlk %29,%30
-	.text
-	.global mcid
-mcid:		
-	mcid %0,%29
-	.text
-	.global dba
-dba:
-	dba %30
-	.text
-	.global dbd
-dbd:	
-	dbd %0,%30
-	.text
-	.global dpwt
-dpwt:			
-	dpwt %0,%30
-	.text
-	.global avail
-avail:
-	avail %31
-	.text
-	.global free
-free:	
-	free %0,%30
-	.text
-	.global tstod
-tstod:	
-	tstod %0,%30
-	.global yield
-yield:	
-	yield
-	.text
-	.global pkrla
-pkrla:	
-	pkrla %0,%29,%30
-	.text
-	.global pkrlac
-pkrlac:	
-	pkrlac %0,%29,%30
-	.text
-	.global pkrlau
-pkrlau:	
-	pkrlau %0,%29,%30
-	.text
-	.global pkrlah
-pkrlah:	
-	pkrlah %0,%29,%30
-	.text
-	.global cmphdr
-cmphdr:						
-	cmphdr %31
-	.text
-	.global cam36
-cam36:	
-	cam36 %29,%30,1,1
-	.text
-	.global cam72
-cam72:	
-	cam72 %0,%30,2,2
-	.text
-	.global cam144
-cam144:	
-	cam144 %0,%29,3,3
-	.text
-	.global cam288
-cam288:	
-	cam144 %0,%29,4,4
-	.text
-	.global cm32and
-cm32and:
-	cm32and %0,%29,%30
-	.text
-	.global cm32andn
-cm32andn:
-	cm32andn %0,%29,%30
-	.text
-	.global cm32or
-cm32or:
-	cm32or %0,%29,%30
-	.text
-	.global cm32ra
-cm32ra:
-	cm32ra %0,%29,%30
-	.text
-	.global cm32rd
-cm32rd:
-	cm32rd %29,%30
-	.text
-	.global cm32ri
-cm32ri:	
-	cm32ri %0,%29
-	.text
-	.global cm32rs
-cm32rs:
-	cm32rs %0,%29,%30
-	.text
-	.global cm32sa
-cm32sa:
-	cm32sa %0,%29,%30
-	.text
-	.global cm32sd
-cm32sd:
-	cm32sd %0,%29
-	.text
-	.global cm32si
-cm32si:
-	cm32si %0,%29
-	.text
-	.global cm32ss
-cm32ss:
-	cm32ss %0,%29,%30
-	.text
-	.global cm32xor
-cm32xor:
-	cm32xor %0,%29,%30
-	.text
-	.global cm64clr
-cm64clr:
-	cm64clr %0,%28
-	.text
-	.global cm64ra
-cm64ra:
-	cm64ra %0,%28,%30
-	.text
-	.global cm64rd
-cm64rd:
-	cm64rd %0,%28
-	.text
-	.global cm64ri
-cm64ri:
-	cm64ri %0,%28
-	.text
-	.global cm64ria2
-cm64ria2:
-	cm64ria2 %0,%28,%30
-	.text
-	.global cm64rs
-cm64rs:
-	cm64rs %0,%28,%30
-	.text
-	.global cm64sa
-cm64sa:
-	cm64sa %0,%28,%30
-	.text
-	.global cm64sd
-cm64sd:
-	cm64sd %0,%28
-	.text
-	.global cm64si
-cm64si:
-	cm64si %0,%28
-	.text
-	.global cm64sia2
-cm64sia2:
-	cm64sia2 %0,%28,%30
-	.text
-	.global cm64ss
-cm64ss:
-	cm64ss %0,%29,%30
-	.text
-	.global cm128ria2
-cm128ria2:
-	cm128ria2 %0,%29,%30
-	.text
-	.global cm128ria30
-cm128ria3:
-	cm128ria3 %0,%29,%30,0
-	.text
-	.global cm128ria4
-cm128ria4:
-	cm128ria4 %0,%29,%30,7
-	.text
-	.global cm128sia2
-cm128sia2:
-	cm128sia2 %0,%29,%30
-	.text
-	.global cm128sia3
-cm128sia3:
-	cm128sia3 %0,%29,%30,0
-	.text
-	.global cm128sia4
-cm128sia4:
-	cm128sia4 %0,%29,%30,7
-	.text
-	.global cm128vsa
-cm128vsa:
-	cm128vsa %0,%29,%30
-	.text
-	.global pkrli
-pkrli:	
-	pkrli %1,%31,%29,63
-	.text
-	.global pkrlic
-pkrlic:	
-	pkrlic %1,%31,%29,63
-	.text
-	.global pkrlih
-pkrlih:	
-	pkrlih %1,%31,%29,63
-	.text
-	.global pkrliu
-pkrliu:	
-	pkrliu %1,%31,%29,63
-	.text
-	.global rbi
-rbi:		
-	rbi %2,%29,%28,32
-	.text
-	.global rbil
-rbil:		
-	rbil %2,%29,%28,32
-	.text
-	.global rbir
-rbir:		
-	rbir %2,%29,%28,32
-	.text
-	.global wbi
-wbi:		
-	wbi %0,%1,%2,32
-	.text
-	.global wbic
-wbic:		
-	wbic %0,%1,%2,32
-	.text
-	.global wbiu
-wbiu:		
-	wbiu %0,%1,%2,32
-			
diff --git a/gas/testsuite/gas/iq2000/q10hazard3.s b/gas/testsuite/gas/iq2000/q10hazard3.s
deleted file mode 100644
index c4170a075a7b..000000000000
--- a/gas/testsuite/gas/iq2000/q10hazard3.s
+++ /dev/null
@@ -1,14 +0,0 @@
-# This test case includes a single case of a load hazard, whereby an
-# instruction references a register which is the target of a load.
-# The assembler must warn about this!
-
-.data
-foodata:
-	.word 42
-
-.text
-	lw %31, foodata(%1)
-	jal %31,footext
-
-footext:
-	nop
diff --git a/gas/testsuite/gas/iq2000/q10hazard4.s b/gas/testsuite/gas/iq2000/q10hazard4.s
deleted file mode 100644
index fc9f9a65e695..000000000000
--- a/gas/testsuite/gas/iq2000/q10hazard4.s
+++ /dev/null
@@ -1,11 +0,0 @@
-# This test case includes a single case of a load hazard, whereby an
-# instruction references a register which is the target of a load.
-# The assembler must warn about this!
-
-.data
-foodata:
-	.word 42
-
-.text
-	lw %10, foodata(%12)
-	add %3, %10, %9
diff --git a/gas/testsuite/gas/iq2000/q10hazard5.s b/gas/testsuite/gas/iq2000/q10hazard5.s
deleted file mode 100644
index 6ec51f5a8055..000000000000
--- a/gas/testsuite/gas/iq2000/q10hazard5.s
+++ /dev/null
@@ -1,11 +0,0 @@
-# This test case includes a single case of a load hazard, whereby an
-# instruction references a register which is the target of a load.
-# The assembler must warn about this!
-
-.data
-foodata:
-	.word 42
-
-.text
-	lw %1, foodata(%4)
-	add %8, %1, %9
diff --git a/gas/testsuite/gas/iq2000/q10load-hazards.exp b/gas/testsuite/gas/iq2000/q10load-hazards.exp
deleted file mode 100644
index e49bcf9020b4..000000000000
--- a/gas/testsuite/gas/iq2000/q10load-hazards.exp
+++ /dev/null
@@ -1,62 +0,0 @@
-# Test for warnings when producing load hazards (instructions that
-# reference the target of load one stage further down the pipeline.
-
-# Run GAS and check that it emits the desired warning for the test case.
-# Arguments:
-#   file -- name of the test case to assemble.
-#   testname -- a string describing the test.
-#   warnpattern -- a regular expression, suitable for use by the Tcl
-#     regexp command, to decide if the warning string was emitted by
-#     the assembler to stderr.
-
-proc iq2000_warning_test { file testname {warnpattern ""} } {
-    global comp_output
-
-    gas_run $file "-m10" ">/dev/null"
-    verbose "output was $comp_output" 2
-
-    if {$warnpattern == ""} {
-	if {$comp_output == ""} { pass $testname } else { fail $testname }
-	return
-    }
-
-    if {[regexp "Warning: $warnpattern" $comp_output]} {
-	pass $testname
-    } else {
-	fail $testname
-    }
-}
-
-if [istarget iq2000*-*-*] {
-    foreach file [glob -nocomplain -- $srcdir/$subdir/q10hazard*.s] {
-	set file [file tail $file]
-	switch -- $file {
-	    "q10hazard0.s" {
-		set warnpattern "operand references R10 of previous load"
-	    }
-	    "q10hazard1.s" {
-		set warnpattern "operand references R1 of previous load"
-	    }
-	    "q10hazard2.s" {
-		set warnpattern "operand references R2 of previous load"
-	    }
-	    "q10hazard3.s" {
-		set warnpattern "operand references R31 of previous load"
-	    }
-	    "q10hazard4.s" {
-		set warnpattern "operand references R10 of previous load"
-	    }
-	    "q10hazard5.s" {
-		set warnpattern "operand references R1 of previous load"
-	    }
-	    default {
-		error "no expected result specified for $file"
-		return
-	    }
-	}
-	iq2000_warning_test $file "assembler emits load hazard warning for $file" $warnpattern
-    }
-
-    set testname "assembler emits no warnings when there are no load hazards"
-    iq2000_warning_test q10nohazard.s $testname
-}
diff --git a/gas/testsuite/gas/iq2000/q10nohazard.s b/gas/testsuite/gas/iq2000/q10nohazard.s
deleted file mode 100644
index 02fc136d7e02..000000000000
--- a/gas/testsuite/gas/iq2000/q10nohazard.s
+++ /dev/null
@@ -1,20 +0,0 @@
-# This test case includes a number of cases where there is no load
-# hazard between a load and the instruction which follows it in
-# the pipeline.
-
-.data
-.text
-	lw %0, 0x40(%0)
-	add %1, %2, %3
-	lh %0, 0x80(%0)
-	add %1, %2, %3
-	lb %0, 0x80(%0)
-	add %1, %2, %3
-	lw %0, 0x80(%0)
-	nop
-	add %0, %0, %0
-	lw %0, 0x80(%3)
-	nop
-	lw %0, 0x80(%3)
-	add %2, %3, %4
-	
diff --git a/gas/testsuite/gas/iq2000/q10noyield.s b/gas/testsuite/gas/iq2000/q10noyield.s
deleted file mode 100644
index 7c8cdaf9df22..000000000000
--- a/gas/testsuite/gas/iq2000/q10noyield.s
+++ /dev/null
@@ -1,14 +0,0 @@
-# This test case includes a number of cases where a yield instruction
-# (e.g. SLEEP) does NOT appear in the branch delay slot.
-
-.text
-test1:	beq %0, %0, test2
-	# nop in the branch delay slot.
-	nop
-test2:	cfc %0, %0
-	nop
-test3:	cfc %0, %0
-	beq %0, %0, test4
-	nop
-test4:	sub %1,%2,%3
-
diff --git a/gas/testsuite/gas/iq2000/q10test0.d b/gas/testsuite/gas/iq2000/q10test0.d
deleted file mode 100644
index a0e77c7ec7c6..000000000000
--- a/gas/testsuite/gas/iq2000/q10test0.d
+++ /dev/null
@@ -1,361 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test0
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 2d 	mrgb r1,r1,r1,0x0
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 01 08 00 	ram r1,r1,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 00 	rbi r1,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 00 	rbir r1,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 00 	rbil r1,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 00 	wbi r1,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 00 	wbic r1,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 00 	wbiu r1,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2b 	pkrlac r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 2a 	pkrlah r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	4c 21 08 29 	pkrlau r1,r1,r1
- 30c:	00 00 00 00 	nop
- 310:	48 21 08 00 	pkrli r1,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 0b 00 	pkrlic r1,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	48 21 0a 00 	pkrlih r1,r1,r1,0x0
- 324:	00 00 00 00 	nop
- 328:	48 21 09 00 	pkrliu r1,r1,r1,0x0
- 32c:	00 00 00 00 	nop
- 330:	4c 01 08 01 	lock r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 01 08 03 	unlk r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 21 08 06 	swwr r1,r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 21 08 07 	swwru r1,r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 01 08 04 	swrd r1,r1
- 354:	00 00 00 00 	nop
- 358:	4c 01 08 05 	swrdl r1,r1
- 35c:	00 00 00 00 	nop
- 360:	4c 02 10 0c 	dwrd r2,r2
- 364:	00 00 00 00 	nop
- 368:	4c 02 10 0d 	dwrdl r2,r2
- 36c:	00 00 00 00 	nop
- 370:	4c 01 0c 00 	cam36 r1,r1,0x0,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 01 0c 40 	cam72 r1,r1,0x0,0x0
- 37c:	00 00 00 00 	nop
- 380:	4c 01 0c 80 	cam144 r1,r1,0x0,0x0
- 384:	00 00 00 00 	nop
- 388:	4c 01 0c c0 	cam288 r1,r1,0x0,0x0
- 38c:	00 00 00 00 	nop
- 390:	4c 21 08 ab 	cm32and r1,r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 21 08 a3 	cm32andn r1,r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 21 08 aa 	cm32or r1,r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 21 08 b0 	cm32ra r1,r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 01 08 a1 	cm32rd r1,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 01 08 a4 	cm32ri r1,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 21 08 a0 	cm32rs r1,r1,r1
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 21 08 b8 	cm32sa r1,r1,r1
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 01 08 a9 	cm32sd r1,r1
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 01 08 ac 	cm32si r1,r1
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 21 08 a8 	cm32ss r1,r1,r1
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 21 08 a2 	cm32xor r1,r1,r1
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 02 10 85 	cm64clr r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 42 10 90 	cm64ra r2,r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 02 10 81 	cm64rd r2,r2
- 404:	00 00 00 00 	nop
- 408:	4c 02 10 84 	cm64ri r2,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 42 10 94 	cm64ria2 r2,r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 10 80 	cm64rs r2,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 42 10 98 	cm64sa r2,r2,r2
- 424:	00 00 00 00 	nop
- 428:	4c 02 10 89 	cm64sd r2,r2
- 42c:	00 00 00 00 	nop
- 430:	4c 02 10 8c 	cm64si r2,r2
- 434:	00 00 00 00 	nop
- 438:	4c 42 10 9c 	cm64sia2 r2,r2,r2
- 43c:	00 00 00 00 	nop
- 440:	4c 42 10 88 	cm64ss r2,r2,r2
- 444:	00 00 00 00 	nop
- 448:	4c 42 10 95 	cm128ria2 r2,r2,r2
- 44c:	00 00 00 00 	nop
- 450:	4c 42 10 90 	cm64ra r2,r2,r2
- 454:	00 00 00 00 	nop
- 458:	4c 42 10 91 	cm128ria3 r2,r2,r2,0x1
- 45c:	00 00 00 00 	nop
- 460:	4c 42 10 92 	cm128ria3 r2,r2,r2,0x2
- 464:	00 00 00 00 	nop
- 468:	4c 42 10 93 	cm128ria3 r2,r2,r2,0x3
- 46c:	00 00 00 00 	nop
- 470:	4c 42 10 b0 	cm32ra r2,r2,r2
- 474:	00 00 00 00 	nop
- 478:	4c 42 10 b1 	cm128ria4 r2,r2,r2,0x1
- 47c:	00 00 00 00 	nop
- 480:	4c 42 10 b2 	cm128ria4 r2,r2,r2,0x2
- 484:	00 00 00 00 	nop
- 488:	4c 42 10 b3 	cm128ria4 r2,r2,r2,0x3
- 48c:	00 00 00 00 	nop
- 490:	4c 42 10 b4 	cm128ria4 r2,r2,r2,0x4
- 494:	00 00 00 00 	nop
- 498:	4c 42 10 b5 	cm128ria4 r2,r2,r2,0x5
- 49c:	00 00 00 00 	nop
- 4a0:	4c 42 10 b6 	cm128ria4 r2,r2,r2,0x6
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 42 10 b7 	cm128ria4 r2,r2,r2,0x7
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 42 10 9d 	cm128sia2 r2,r2,r2
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 42 10 98 	cm64sa r2,r2,r2
- 4bc:	00 00 00 00 	nop
- 4c0:	4c 42 10 99 	cm128sia3 r2,r2,r2,0x1
- 4c4:	00 00 00 00 	nop
- 4c8:	4c 42 10 9a 	cm128sia3 r2,r2,r2,0x2
- 4cc:	00 00 00 00 	nop
- 4d0:	4c 42 10 9b 	cm128sia3 r2,r2,r2,0x3
- 4d4:	00 00 00 00 	nop
- 4d8:	4c 21 08 b8 	cm32sa r1,r1,r1
- 4dc:	00 00 00 00 	nop
- 4e0:	4c 21 08 b9 	cm128sia4 r1,r1,r1,0x1
- 4e4:	00 00 00 00 	nop
- 4e8:	4c 21 08 ba 	cm128sia4 r1,r1,r1,0x2
- 4ec:	00 00 00 00 	nop
- 4f0:	4c 21 08 bb 	cm128sia4 r1,r1,r1,0x3
- 4f4:	00 00 00 00 	nop
- 4f8:	4c 21 08 bc 	cm128sia4 r1,r1,r1,0x4
- 4fc:	00 00 00 00 	nop
- 500:	4c 21 08 bd 	cm128sia4 r1,r1,r1,0x5
- 504:	00 00 00 00 	nop
- 508:	4c 21 08 be 	cm128sia4 r1,r1,r1,0x6
- 50c:	00 00 00 00 	nop
- 510:	4c 21 08 bf 	cm128sia4 r1,r1,r1,0x7
- 514:	00 00 00 00 	nop
- 518:	4c 21 08 a6 	cm128vsa r1,r1,r1
- 51c:	00 00 00 00 	nop
- 520:	4c 21 08 14 	crc32 r1,r1,r1
- 524:	00 00 00 00 	nop
- 528:	4c 21 08 15 	crc32b r1,r1,r1
- 52c:	00 00 00 00 	nop
- 530:	4c 20 08 26 	chkhdr r1,r1
- 534:	00 00 00 00 	nop
- 538:	4c 00 08 24 	avail r1
- 53c:	00 00 00 00 	nop
- 540:	4c 20 08 25 	free r1,r1
- 544:	00 00 00 00 	nop
- 548:	00 00 00 0e 	yield
- 54c:	00 00 00 00 	nop
- 550:	4c 20 08 27 	tstod r1,r1
- 554:	00 00 00 00 	nop
- 558:	4c 00 08 2c 	cmphdr r1
- 55c:	00 00 00 00 	nop
- 560:	4c 01 08 20 	mcid r1,r1
- 564:	00 00 00 00 	nop
- 568:	4c 00 08 22 	dba r1
- 56c:	00 00 00 00 	nop
- 570:	4c 01 08 21 	dbd r1,r0,r1
- 574:	00 00 00 00 	nop
- 578:	4c 20 08 23 	dpwt r1,r1
- 57c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test0.s b/gas/testsuite/gas/iq2000/q10test0.s
deleted file mode 100644
index 60ba744f10e7..000000000000
--- a/gas/testsuite/gas/iq2000/q10test0.s
+++ /dev/null
@@ -1,354 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%1,%1,0

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,0,0

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,0

-	 NOP	

-	 RBIR	%1,%1,%1,0

-	 NOP	

-	 RBIL	%1,%1,%1,0

-	 NOP	

-	 WBI	%1,%1,%1,0

-	 NOP	

-	 WBIC	%1,%1,%1,0

-	 NOP	

-	 WBIU	%1,%1,%1,0

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAC %1,%1,%1

-	 NOP

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,0

-	 NOP	

-	 PKRLIC	%1,%1,%1,0

-	 NOP	

-	 PKRLIH	%1,%1,%1,0

-	 NOP	

-	 PKRLIU	%1,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 DWRD	%2,%2

-	 NOP	

-	 DWRDL	%2,%2

-	 NOP	

-	 CAM36	%1,%1,0,0

-	 NOP

-	 CAM72	%1,%1,0,0

-	 NOP	

-	 CAM144	%1,%1,0,0

-	 NOP	

-	 CAM288	%1,%1,0,0

-	 NOP	

-	 CM32AND	%1,%1,%1

-	 NOP	

-	 CM32ANDN	%1,%1,%1

-	 NOP	

-	 CM32OR	%1,%1,%1

-	 NOP	

-	 CM32RA	%1,%1,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%1,%1

-	 NOP	

-	 CM32SA	%1,%1,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%1,%1

-	 NOP	

-	 CM32XOR	%1,%1,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%2,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%2,%2

-	 NOP	

-	 CM64RS	%2,%2,%2

-	 NOP	

-	 CM64SA	%2,%2,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%2,%2

-	 NOP	

-	 CM64SS	%2,%2,%2

-	 NOP	

-	 CM128RIA2	%2,%2,%2

-	 NOP	

-	 CM128RIA3	%2,%2,%2,0

-	 NOP	

-	 CM128RIA3	%2,%2,%2,1

-	 NOP	

-	 CM128RIA3	%2,%2,%2,2

-	 NOP	

-	 CM128RIA3	%2,%2,%2,3

-	 NOP	

-	 CM128RIA4	%2,%2,%2,0

-	 NOP	

-	 CM128RIA4	%2,%2,%2,1

-	 NOP	

-	 CM128RIA4	%2,%2,%2,2

-	 NOP	

-	 CM128RIA4	%2,%2,%2,3

-	 NOP	

-	 CM128RIA4	%2,%2,%2,4

-	 NOP	

-	 CM128RIA4	%2,%2,%2,5

-	 NOP	

-	 CM128RIA4	%2,%2,%2,6

-	 NOP	

-	 CM128RIA4	%2,%2,%2,7

-	 NOP	

-	 CM128SIA2	%2,%2,%2

-	 NOP	

-	 CM128SIA3	%2,%2,%2,0

-	 NOP	

-	 CM128SIA3	%2,%2,%2,1

-	 NOP	

-	 CM128SIA3	%2,%2,%2,2

-	 NOP	

-	 CM128SIA3	%2,%2,%2,3

-	 NOP	

-	 CM128SIA4	%1,%1,%1,0

-	 NOP	

-	 CM128SIA4	%1,%1,%1,1

-	 NOP	

-	 CM128SIA4	%1,%1,%1,2

-	 NOP	

-	 CM128SIA4	%1,%1,%1,3

-	 NOP	

-	 CM128SIA4	%1,%1,%1,4

-	 NOP	

-	 CM128SIA4	%1,%1,%1,5

-	 NOP	

-	 CM128SIA4	%1,%1,%1,6

-	 NOP	

-	 CM128SIA4	%1,%1,%1,7

-	 NOP	

-	 CM128VSA	%1,%1,%1

-	 NOP	

-	 CRC32	%1,%1,%1

-	 NOP	

-	 CRC32B	%1,%1,%1

-	 NOP	

-	 CHKHDR	%1,%1

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 YIELD

-	 NOP	

-	 TSTOD	%1,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%1

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP

diff --git a/gas/testsuite/gas/iq2000/q10test1.d b/gas/testsuite/gas/iq2000/q10test1.d
deleted file mode 100644
index 97f5cd7014f0..000000000000
--- a/gas/testsuite/gas/iq2000/q10test1.d
+++ /dev/null
@@ -1,317 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test1
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	03 e1 08 20 	add r1,r31,r1
-   4:	00 00 00 00 	nop
-   8:	23 e1 00 00 	addi r1,r31,0x0
-   c:	00 00 00 00 	nop
-  10:	27 e1 00 00 	addiu r1,r31,0x0
-  14:	00 00 00 00 	nop
-  18:	03 e1 08 21 	addu r1,r31,r1
-  1c:	00 00 00 00 	nop
-  20:	03 e1 08 29 	ado16 r1,r31,r1
-  24:	00 00 00 00 	nop
-  28:	03 e1 08 24 	and r1,r31,r1
-  2c:	00 00 00 00 	nop
-  30:	33 e1 00 00 	andi r1,r31,0x0
-  34:	00 00 00 00 	nop
-  38:	b3 e1 00 00 	andoi r1,r31,0x0
-  3c:	00 00 00 00 	nop
-  40:	bf e1 00 00 	andoui r1,r31,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	03 e1 08 2d 	mrgb r1,r31,r1,0x0
-  54:	00 00 00 00 	nop
-  58:	03 e1 08 27 	nor r1,r31,r1
-  5c:	00 00 00 00 	nop
-  60:	03 e1 08 25 	or r1,r31,r1
-  64:	00 00 00 00 	nop
-  68:	37 e1 00 00 	ori r1,r31,0x0
-  6c:	00 00 00 00 	nop
-  70:	3f e1 00 00 	orui r1,r31,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	03 e1 08 04 	sllv r1,r1,r31
-  84:	00 00 00 00 	nop
-  88:	03 e1 08 2a 	slt r1,r31,r1
-  8c:	00 00 00 00 	nop
-  90:	2b e1 00 00 	slti r1,r31,0x0
-  94:	00 00 00 00 	nop
-  98:	2f e1 00 00 	sltiu r1,r31,0x0
-  9c:	00 00 00 00 	nop
-  a0:	03 e1 08 2b 	sltu r1,r31,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	03 e1 08 07 	srav r1,r1,r31
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	03 e1 08 06 	srlv r1,r1,r31
-  c4:	00 00 00 00 	nop
-  c8:	03 e1 08 22 	sub r1,r31,r1
-  cc:	00 00 00 00 	nop
-  d0:	03 e1 08 23 	subu r1,r31,r1
-  d4:	00 00 00 00 	nop
-  d8:	03 e1 08 26 	xor r1,r31,r1
-  dc:	00 00 00 00 	nop
-  e0:	3b e1 00 00 	xori r1,r31,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 3f 08 05 	srmv r1,r31,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 3f 08 01 	slmv r1,r31,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 01 08 00 	ram r1,r1,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	73 e0 ff bd 	bbi r31\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	7b e0 ff bb 	bbin r31\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	77 e1 ff b9 	bbv r31,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7f e1 ff b7 	bbvn r31,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f3 e0 ff b5 	bbil r31\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	fb e0 ff b3 	bbinl r31\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f7 e1 ff b1 	bbvl r31,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	ff e1 ff af 	bbvnl r31,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	13 e1 ff ad 	beq r31,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	53 e1 ff ab 	beql r31,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	07 e1 ff a9 	bgez r31,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	07 f5 ff a7 	bgtzal r31,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	07 f1 ff a5 	bgezal r31,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	07 f7 ff a3 	bgtzall r31,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	07 f3 ff a1 	bgezall r31,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	07 e3 ff 9f 	bgezl r31,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	07 e7 ff 9d 	bgtzl r31,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	07 e5 ff 9b 	bgtz r31,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	07 e4 ff 99 	blez r31,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	07 f4 ff 97 	blezal r31,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	07 e0 ff 95 	bltz r31,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	07 f0 ff 93 	bltzal r31,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	07 e6 ff 91 	blezl r31,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	07 e2 ff 8f 	bltzl r31,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	07 f6 ff 8d 	blezall r31,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	07 f2 ff 8b 	bltzall r31,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	1b e1 ff 89 	bmb r31,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	5b e1 ff 87 	bmbl r31,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	63 e1 ff 85 	bmb0 r31,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	67 e1 ff 83 	bmb1 r31,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	6b e1 ff 81 	bmb2 r31,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6f e1 ff 7f 	bmb3 r31,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	17 e1 ff 7d 	bne r31,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	57 e1 ff 7b 	bnel r31,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 1f 00 00 	jal 0 <_start>
- 224:	00 00 00 00 	nop
- 228:	03 e0 08 09 	jalr r1,r31
- 22c:	00 00 00 00 	nop
- 230:	03 e0 00 08 	jr r31
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4f e1 00 02 	ctc r31,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8f e1 00 00 	lw r1,0x0\(r31\)
- 254:	00 00 00 00 	nop
- 258:	87 e1 00 00 	lh r1,0x0\(r31\)
- 25c:	00 00 00 00 	nop
- 260:	83 e1 00 00 	lb r1,0x0\(r31\)
- 264:	00 00 00 00 	nop
- 268:	97 e1 00 00 	lhu r1,0x0\(r31\)
- 26c:	00 00 00 00 	nop
- 270:	93 e1 00 00 	lbu r1,0x0\(r31\)
- 274:	00 00 00 00 	nop
- 278:	a3 e1 00 00 	sb r1,0x0\(r31\)
- 27c:	00 00 00 00 	nop
- 280:	a7 e1 00 00 	sh r1,0x0\(r31\)
- 284:	00 00 00 00 	nop
- 288:	af e1 00 00 	sw r1,0x0\(r31\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 f8 08 	rba r31,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 f8 0a 	rbar r31,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 f8 09 	rbal r31,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 f8 10 	wba r31,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 f8 12 	wbac r31,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 f8 11 	wbau r31,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 fa 00 	rbi r31,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 f9 00 	rbir r31,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 fb 00 	rbil r31,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 fe 00 	wbi r31,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 fd 00 	wbic r31,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 ff 00 	wbiu r31,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 f8 28 	pkrla r31,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 f8 2a 	pkrlah r31,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 f8 29 	pkrlau r31,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 f8 00 	pkrli r31,r1,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	48 21 fa 00 	pkrlih r31,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 f9 00 	pkrliu r31,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 f8 06 	swwr r31,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 f8 07 	swwru r31,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 02 10 0c 	dwrd r2,r2
- 354:	00 00 00 00 	nop
- 358:	4c 02 10 0d 	dwrdl r2,r2
- 35c:	00 00 00 00 	nop
- 360:	4c 1f 0c 08 	cam36 r1,r31,0x1,0x0
- 364:	00 00 00 00 	nop
- 368:	4c 1f 0c 41 	cam72 r1,r31,0x1,0x0
- 36c:	00 00 00 00 	nop
- 370:	4c 1f 0c 81 	cam144 r1,r31,0x1,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 1f 0c c1 	cam288 r1,r31,0x1,0x0
- 37c:	00 00 00 00 	nop
- 380:	4f e1 08 ab 	cm32and r1,r31,r1
- 384:	00 00 00 00 	nop
- 388:	4f e1 08 a3 	cm32andn r1,r31,r1
- 38c:	00 00 00 00 	nop
- 390:	4f e1 08 aa 	cm32or r1,r31,r1
- 394:	00 00 00 00 	nop
- 398:	4f e1 08 b0 	cm32ra r1,r31,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 01 08 a1 	cm32rd r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 01 08 a4 	cm32ri r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4f e1 08 a0 	cm32rs r1,r31,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4f e1 08 b8 	cm32sa r1,r31,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 01 08 a9 	cm32sd r1,r1
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 01 08 ac 	cm32si r1,r1
- 3cc:	00 00 00 00 	nop
- 3d0:	4f e1 08 a8 	cm32ss r1,r31,r1
- 3d4:	00 00 00 00 	nop
- 3d8:	4f e1 08 a2 	cm32xor r1,r31,r1
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 02 10 85 	cm64clr r2,r2
- 3e4:	00 00 00 00 	nop
- 3e8:	4f e2 10 90 	cm64ra r2,r31,r2
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 02 10 81 	cm64rd r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 02 10 84 	cm64ri r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4f e2 10 94 	cm64ria2 r2,r31,r2
- 404:	00 00 00 00 	nop
- 408:	4f e2 10 80 	cm64rs r2,r31,r2
- 40c:	00 00 00 00 	nop
- 410:	4f e2 10 98 	cm64sa r2,r31,r2
- 414:	00 00 00 00 	nop
- 418:	4c 02 10 89 	cm64sd r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 02 10 8c 	cm64si r2,r2
- 424:	00 00 00 00 	nop
- 428:	4f e2 10 9c 	cm64sia2 r2,r31,r2
- 42c:	00 00 00 00 	nop
- 430:	4f e2 10 88 	cm64ss r2,r31,r2
- 434:	00 00 00 00 	nop
- 438:	4f e2 10 95 	cm128ria2 r2,r31,r2
- 43c:	00 00 00 00 	nop
- 440:	4f e2 10 90 	cm64ra r2,r31,r2
- 444:	00 00 00 00 	nop
- 448:	4f e2 10 b1 	cm128ria4 r2,r31,r2,0x1
- 44c:	00 00 00 00 	nop
- 450:	4f e2 10 9d 	cm128sia2 r2,r31,r2
- 454:	00 00 00 00 	nop
- 458:	4f e2 10 98 	cm64sa r2,r31,r2
- 45c:	00 00 00 00 	nop
- 460:	4f e1 08 b8 	cm32sa r1,r31,r1
- 464:	00 00 00 00 	nop
- 468:	4f e1 08 a6 	cm128vsa r1,r31,r1
- 46c:	00 00 00 00 	nop
- 470:	4f e1 08 14 	crc32 r1,r31,r1
- 474:	00 00 00 00 	nop
- 478:	4f e1 08 15 	crc32b r1,r31,r1
- 47c:	00 00 00 00 	nop
- 480:	4c 20 08 26 	chkhdr r1,r1
- 484:	00 00 00 00 	nop
- 488:	4c 00 08 24 	avail r1
- 48c:	00 00 00 00 	nop
- 490:	4c 20 08 25 	free r1,r1
- 494:	00 00 00 00 	nop
- 498:	4f e0 08 27 	tstod r1,r31
- 49c:	00 00 00 00 	nop
- 4a0:	00 00 00 0e 	yield
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 00 08 2c 	cmphdr r1
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 01 08 20 	mcid r1,r1
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 00 f8 22 	dba r31
- 4bc:	00 00 00 00 	nop
- 4c0:	4c 01 08 21 	dbd r1,r0,r1
- 4c4:	00 00 00 00 	nop
- 4c8:	4c 20 08 23 	dpwt r1,r1
- 4cc:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test1.s b/gas/testsuite/gas/iq2000/q10test1.s
deleted file mode 100644
index 750523008101..000000000000
--- a/gas/testsuite/gas/iq2000/q10test1.s
+++ /dev/null
@@ -1,310 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%31,%1

-	 NOP	

-	 ADDI	%1,%31,0

-	 NOP	

-	 ADDIU	%1,%31,0

-	 NOP	

-	 ADDU	%1,%31,%1

-	 NOP	

-	 ADO16	%1,%31,%1

-	 NOP	

-	 AND	%1,%31,%1

-	 NOP	

-	 ANDI	%1,%31,0

-	 NOP	

-	 ANDOI	%1,%31,0

-	 NOP	

-	 ANDOUI	%1,%31,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%31,%1,0

-	 NOP	

-	 NOR	%1,%31,%1

-	 NOP	

-	 OR	%1,%31,%1

-	 NOP	

-	 ORI	%1,%31,0

-	 NOP	

-	 ORUI	%1,%31,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%31

-	 NOP	

-	 SLT	%1,%31,%1

-	 NOP	

-	 SLTI	%1,%31,0

-	 NOP	

-	 SLTIU	%1,%31,0

-	 NOP	

-	 SLTU	%1,%31,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%31

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%31

-	 NOP	

-	 SUB	%1,%31,%1

-	 NOP	

-	 SUBU	%1,%31,%1

-	 NOP	

-	 XOR	%1,%31,%1

-	 NOP	

-	 XORI	%1,%31,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%31,%1,0

-	 NOP	

-	 SLMV	%1,%31,%1,0

-	 NOP	

-	 RAM	%1,%1,0,0,0

-	 NOP	

-	 BBI	%31(0),_start

-	 NOP	

-	 BBIN	%31(0),_start

-	 NOP	

-	 BBV	%31,%1,_start

-	 NOP	

-	 BBVN	%31,%1,_start

-	 NOP	

-	 BBIL	%31(0),_start

-	 NOP	

-	 BBINL	%31(0),_start

-	 NOP	

-	 BBVL	%31,%1,_start

-	 NOP	

-	 BBVNL	%31,%1,_start

-	 NOP	

-	 BEQ	%31,%1,_start

-	 NOP	

-	 BEQL	%31,%1,_start

-	 NOP	

-	 BGEZ	%31,_start

-	 NOP	

-	 BGTZAL	%31,_start

-	 NOP	

-	 BGEZAL	%31,_start

-	 NOP	

-	 BGTZALL	%31,_start

-	 NOP	

-	 BGEZALL	%31,_start

-	 NOP	

-	 BGEZL	%31,_start

-	 NOP	

-	 BGTZL	%31,_start

-	 NOP	

-	 BGTZ	%31,_start

-	 NOP	

-	 BLEZ	%31,_start

-	 NOP	

-	 BLEZAL	%31,_start

-	 NOP	

-	 BLTZ	%31,_start

-	 NOP	

-	 BLTZAL	%31,_start

-	 NOP	

-	 BLEZL	%31,_start

-	 NOP	

-	 BLTZL	%31,_start

-	 NOP	

-	 BLEZALL	%31,_start

-	 NOP	

-	 BLTZALL	%31,_start

-	 NOP	

-	 BMB	%31,%1,_start

-	 NOP	

-	 BMBL	%31,%1,_start

-	 NOP	

-	 BMB0	%31,%1,_start

-	 NOP	

-	 BMB1	%31,%1,_start

-	 NOP	

-	 BMB2	%31,%1,_start

-	 NOP	

-	 BMB3	%31,%1,_start

-	 NOP	

-	 BNE	%31,%1,_start

-	 NOP	

-	 BNEL	%31,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%31,0

-	 NOP	

-	 JALR	%1,%31

-	 NOP	

-	 JR	%31

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%31,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%31)

-	 NOP	

-	 LH	%1,0(%31)

-	 NOP	

-	 LB	%1,0(%31)

-	 NOP	

-	 LHU	%1,0(%31)

-	 NOP	

-	 LBU	%1,0(%31)

-	 NOP	

-	 SB	%1,0(%31)

-	 NOP	

-	 SH	%1,0(%31)

-	 NOP	

-	 SW	%1,0(%31)

-	 NOP	

-	 RBA	%31,%1,%1

-	 NOP	

-	 RBAR	%31,%1,%1

-	 NOP	

-	 RBAL	%31,%1,%1

-	 NOP	

-	 WBA	%31,%1,%1

-	 NOP	

-	 WBAC	%31,%1,%1

-	 NOP	

-	 WBAU	%31,%1,%1

-	 NOP	

-	 RBI	%31,%1,%1,0

-	 NOP	

-	 RBIR	%31,%1,%1,0

-	 NOP	

-	 RBIL	%31,%1,%1,0

-	 NOP	

-	 WBI	%31,%1,%1,0

-	 NOP	

-	 WBIC	%31,%1,%1,0

-	 NOP	

-	 WBIU	%31,%1,%1,0

-	 NOP	

-	 PKRLA	%31,%1,%1

-	 NOP	

-	 PKRLAH	%31,%1,%1

-	 NOP	

-	 PKRLAU	%31,%1,%1

-	 NOP	

-	 PKRLI	%31,%1,%1,0

-	 NOP	

-	 PKRLIH	%31,%1,%1,0

-	 NOP	

-	 PKRLIU	%31,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%31,%1,%1

-	 NOP	

-	 SWWRU	%31,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 DWRD	%2,%2

-	 NOP	

-	 DWRDL	%2,%2

-	 NOP	

-	 CAM36	%1,%31,1,0

-	 NOP	

-	 CAM72	%1,%31,1,0

-	 NOP	

-	 CAM144	%1,%31,1,0

-	 NOP	

-	 CAM288	%1,%31,1,0

-	 NOP	

-	 CM32AND	%1,%31,%1

-	 NOP	

-	 CM32ANDN	%1,%31,%1

-	 NOP	

-	 CM32OR	%1,%31,%1

-	 NOP	

-	 CM32RA	%1,%31,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%31,%1

-	 NOP	

-	 CM32SA	%1,%31,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%31,%1

-	 NOP	

-	 CM32XOR	%1,%31,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%31,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%31,%2

-	 NOP	

-	 CM64RS	%2,%31,%2

-	 NOP	

-	 CM64SA	%2,%31,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%31,%2

-	 NOP	

-	 CM64SS	%2,%31,%2

-	 NOP	

-	 CM128RIA2	%2,%31,%2

-	 NOP	

-	 CM128RIA3	%2,%31,%2,0

-	 NOP	

-	 CM128RIA4	%2,%31,%2,1

-	 NOP	

-	 CM128SIA2	%2,%31,%2

-	 NOP	

-	 CM128SIA3	%2,%31,%2,0

-	 NOP	

-	 CM128SIA4	%1,%31,%1,0

-	 NOP	

-	 CM128VSA	%1,%31,%1

-	 NOP	

-	 CRC32	%1,%31,%1

-	 NOP	

-	 CRC32B	%1,%31,%1

-	 NOP	

-	 CHKHDR	%1,%1

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 TSTOD	%1,%31

-	 NOP	

-	 YIELD

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%31

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test10.d b/gas/testsuite/gas/iq2000/q10test10.d
deleted file mode 100644
index 422e0b74bc09..000000000000
--- a/gas/testsuite/gas/iq2000/q10test10.d
+++ /dev/null
@@ -1,301 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test10
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 0f ed 	mrgb r1,r1,r1,0x1f
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 21 08 01 	ram r1,r1,0x0,0x1,0x1
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a ff 	rbi r1,r1,r1,0xff
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 ff 	rbir r1,r1,r1,0xff
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b ff 	rbil r1,r1,r1,0xff
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e ff 	wbi r1,r1,r1,0xff
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d ff 	wbic r1,r1,r1,0xff
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f ff 	wbiu r1,r1,r1,0xff
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2a 	pkrlah r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 29 	pkrlau r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 08 ff 	pkrli r1,r1,r1,0xff
- 30c:	00 00 00 00 	nop
- 310:	48 21 0a ff 	pkrlih r1,r1,r1,0xff
- 314:	00 00 00 00 	nop
- 318:	48 21 09 ff 	pkrliu r1,r1,r1,0xff
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 08 06 	swwr r1,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 08 07 	swwru r1,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 01 0c 07 	cam36 r1,r1,0x0,0x7
- 354:	00 00 00 00 	nop
- 358:	4c 01 0c 78 	cam72 r1,r1,0x0,0x7
- 35c:	00 00 00 00 	nop
- 360:	4c 01 0c b8 	cam144 r1,r1,0x0,0x7
- 364:	00 00 00 00 	nop
- 368:	4c 01 0c f8 	cam288 r1,r1,0x0,0x7
- 36c:	00 00 00 00 	nop
- 370:	4c 21 08 ab 	cm32and r1,r1,r1
- 374:	00 00 00 00 	nop
- 378:	4c 21 08 a3 	cm32andn r1,r1,r1
- 37c:	00 00 00 00 	nop
- 380:	4c 21 08 aa 	cm32or r1,r1,r1
- 384:	00 00 00 00 	nop
- 388:	4c 21 08 b0 	cm32ra r1,r1,r1
- 38c:	00 00 00 00 	nop
- 390:	4c 01 08 a1 	cm32rd r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 01 08 a4 	cm32ri r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 21 08 a0 	cm32rs r1,r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 21 08 b8 	cm32sa r1,r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 01 08 a9 	cm32sd r1,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 01 08 ac 	cm32si r1,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 21 08 a8 	cm32ss r1,r1,r1
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 21 08 a2 	cm32xor r1,r1,r1
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 02 10 85 	cm64clr r2,r2
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 42 10 90 	cm64ra r2,r2,r2
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 02 10 81 	cm64rd r2,r2
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 02 10 84 	cm64ri r2,r2
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 42 10 94 	cm64ria2 r2,r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 42 10 80 	cm64rs r2,r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 42 10 98 	cm64sa r2,r2,r2
- 404:	00 00 00 00 	nop
- 408:	4c 02 10 89 	cm64sd r2,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 02 10 8c 	cm64si r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 10 9c 	cm64sia2 r2,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 42 10 88 	cm64ss r2,r2,r2
- 424:	00 00 00 00 	nop
- 428:	4c 42 10 95 	cm128ria2 r2,r2,r2
- 42c:	00 00 00 00 	nop
- 430:	4c 21 08 14 	crc32 r1,r1,r1
- 434:	00 00 00 00 	nop
- 438:	4c 21 08 15 	crc32b r1,r1,r1
- 43c:	00 00 00 00 	nop
- 440:	4c 20 08 26 	chkhdr r1,r1
- 444:	00 00 00 00 	nop
- 448:	4c 00 08 24 	avail r1
- 44c:	00 00 00 00 	nop
- 450:	4c 20 08 25 	free r1,r1
- 454:	00 00 00 00 	nop
- 458:	4c 20 08 27 	tstod r1,r1
- 45c:	00 00 00 00 	nop
- 460:	00 00 00 0e 	yield
- 464:	00 00 00 00 	nop
- 468:	4c 00 08 2c 	cmphdr r1
- 46c:	00 00 00 00 	nop
- 470:	4c 01 08 20 	mcid r1,r1
- 474:	00 00 00 00 	nop
- 478:	4c 00 08 22 	dba r1
- 47c:	00 00 00 00 	nop
- 480:	4c 01 08 21 	dbd r1,r0,r1
- 484:	00 00 00 00 	nop
- 488:	4c 20 08 23 	dpwt r1,r1
- 48c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test10.s b/gas/testsuite/gas/iq2000/q10test10.s
deleted file mode 100644
index 1ecf11013d57..000000000000
--- a/gas/testsuite/gas/iq2000/q10test10.s
+++ /dev/null
@@ -1,294 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%1,%1,31

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,1,1

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,255

-	 NOP	

-	 RBIR	%1,%1,%1,255

-	 NOP	

-	 RBIL	%1,%1,%1,255

-	 NOP	

-	 WBI	%1,%1,%1,255

-	 NOP	

-	 WBIC	%1,%1,%1,255

-	 NOP	

-	 WBIU	%1,%1,%1,255

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,255

-	 NOP	

-	 PKRLIH	%1,%1,%1,255

-	 NOP	

-	 PKRLIU	%1,%1,%1,255

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 CAM36	%1,%1,0,7

-	 NOP	

-	 CAM72	%1,%1,0,7

-	 NOP	

-	 CAM144	%1,%1,0,7

-	 NOP	

-	 CAM288	%1,%1,0,7

-	 NOP	

-	 CM32AND	%1,%1,%1

-	 NOP	

-	 CM32ANDN	%1,%1,%1

-	 NOP	

-	 CM32OR	%1,%1,%1

-	 NOP	

-	 CM32RA	%1,%1,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%1,%1

-	 NOP	

-	 CM32SA	%1,%1,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%1,%1

-	 NOP	

-	 CM32XOR	%1,%1,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%2,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%2,%2

-	 NOP	

-	 CM64RS	%2,%2,%2

-	 NOP	

-	 CM64SA	%2,%2,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%2,%2

-	 NOP	

-	 CM64SS	%2,%2,%2

-	 NOP	

-	 CM128RIA2	%2,%2,%2

-	 NOP	

-	 CRC32	%1,%1,%1

-	 NOP	

-	 CRC32B	%1,%1,%1

-	 NOP	

-	 CHKHDR	%1,%1

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 TSTOD	%1,%1

-	 NOP	

-	 YIELD

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%1

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test11.d b/gas/testsuite/gas/iq2000/q10test11.d
deleted file mode 100644
index a01fedc73817..000000000000
--- a/gas/testsuite/gas/iq2000/q10test11.d
+++ /dev/null
@@ -1,225 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test11
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 6d 	mrgb r1,r1,r1,0x1
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9d e1 08 01 	ram r1,r1,0x0,0x1,0xf
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 00 	rbi r1,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 00 	rbir r1,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 00 	rbil r1,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 00 	wbi r1,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 00 	wbic r1,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 00 	wbiu r1,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2b 	pkrlac r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 2a 	pkrlah r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	4c 21 08 29 	pkrlau r1,r1,r1
- 30c:	00 00 00 00 	nop
- 310:	48 21 08 00 	pkrli r1,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 0b 00 	pkrlic r1,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	48 21 0a 00 	pkrlih r1,r1,r1,0x0
- 324:	00 00 00 00 	nop
- 328:	48 21 09 00 	pkrliu r1,r1,r1,0x0
- 32c:	00 00 00 00 	nop
- 330:	4c 01 08 01 	lock r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 01 08 03 	unlk r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 21 08 06 	swwr r1,r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 21 08 07 	swwru r1,r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 01 08 04 	swrd r1,r1
- 354:	00 00 00 00 	nop
- 358:	4c 01 08 05 	swrdl r1,r1
- 35c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test11.s b/gas/testsuite/gas/iq2000/q10test11.s
deleted file mode 100644
index 08ee8d5573e6..000000000000
--- a/gas/testsuite/gas/iq2000/q10test11.s
+++ /dev/null
@@ -1,218 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%1,%1,1

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,1,15

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,0

-	 NOP	

-	 RBIR	%1,%1,%1,0

-	 NOP	

-	 RBIL	%1,%1,%1,0

-	 NOP	

-	 WBI	%1,%1,%1,0

-	 NOP	

-	 WBIC	%1,%1,%1,0

-	 NOP	

-	 WBIU	%1,%1,%1,0

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAC	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,0

-	 NOP	

-	 PKRLIC	%1,%1,%1,0

-	 NOP	

-	 PKRLIH	%1,%1,%1,0

-	 NOP	

-	 PKRLIU	%1,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test12.d b/gas/testsuite/gas/iq2000/q10test12.d
deleted file mode 100644
index c2612056781b..000000000000
--- a/gas/testsuite/gas/iq2000/q10test12.d
+++ /dev/null
@@ -1,221 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test12
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 6d 	mrgb r1,r1,r1,0x1
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 21 08 0f 	ram r1,r1,0x0,0xf,0x1
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 00 	rbi r1,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 00 	rbir r1,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 00 	rbil r1,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 00 	wbi r1,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 00 	wbic r1,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 00 	wbiu r1,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2a 	pkrlah r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 29 	pkrlau r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 08 00 	pkrli r1,r1,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	48 21 0a 00 	pkrlih r1,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 09 00 	pkrliu r1,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 08 06 	swwr r1,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 08 07 	swwru r1,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test12.s b/gas/testsuite/gas/iq2000/q10test12.s
deleted file mode 100644
index e207ec3d93e6..000000000000
--- a/gas/testsuite/gas/iq2000/q10test12.s
+++ /dev/null
@@ -1,214 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%1,%1,1

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,15,1

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,0

-	 NOP	

-	 RBIR	%1,%1,%1,0

-	 NOP	

-	 RBIL	%1,%1,%1,0

-	 NOP	

-	 WBI	%1,%1,%1,0

-	 NOP	

-	 WBIC	%1,%1,%1,0

-	 NOP	

-	 WBIU	%1,%1,%1,0

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,0

-	 NOP	

-	 PKRLIH	%1,%1,%1,0

-	 NOP	

-	 PKRLIU	%1,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test2.d b/gas/testsuite/gas/iq2000/q10test2.d
deleted file mode 100644
index 944232a10b02..000000000000
--- a/gas/testsuite/gas/iq2000/q10test2.d
+++ /dev/null
@@ -1,319 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test2
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 f8 20 	add r31,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 f8 21 	addu r31,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 f8 29 	ado16 r31,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 f8 24 	and r31,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 f8 2d 	mrgb r31,r1,r1,0x0
-  54:	00 00 00 00 	nop
-  58:	00 21 f8 27 	nor r31,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 f8 25 	or r31,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 f8 00 	sll r31,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 f8 04 	sllv r31,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 f8 2a 	slt r31,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 f8 2b 	sltu r31,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 f8 03 	sra r31,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 f8 07 	srav r31,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 f8 02 	srl r31,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 f8 06 	srlv r31,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 f8 22 	sub r31,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 f8 23 	subu r31,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 f8 26 	xor r31,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 f8 05 	srmv r31,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 f8 01 	slmv r31,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 01 f8 00 	ram r31,r1,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 f8 09 	jalr r31,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 f8 00 	cfc r31,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 3f 08 08 	rba r1,r1,r31
- 294:	00 00 00 00 	nop
- 298:	4c 3f 08 0a 	rbar r1,r1,r31
- 29c:	00 00 00 00 	nop
- 2a0:	4c 3f 08 09 	rbal r1,r1,r31
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 3f 08 10 	wba r1,r1,r31
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 3f 08 12 	wbac r1,r1,r31
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 3f 08 11 	wbau r1,r1,r31
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 3f 0a 00 	rbi r1,r1,r31,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 3f 09 00 	rbir r1,r1,r31,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 3f 0b 00 	rbil r1,r1,r31,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 3f 0e 00 	wbi r1,r1,r31,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 3f 0d 00 	wbic r1,r1,r31,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 3f 0f 00 	wbiu r1,r1,r31,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 3f 08 28 	pkrla r1,r1,r31
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 3f 08 2b 	pkrlac r1,r1,r31
- 2fc:	00 00 00 00 	nop
- 300:	4c 3f 08 2a 	pkrlah r1,r1,r31
- 304:	00 00 00 00 	nop
- 308:	4c 3f 08 29 	pkrlau r1,r1,r31
- 30c:	00 00 00 00 	nop
- 310:	48 3f 08 00 	pkrli r1,r1,r31,0x0
- 314:	00 00 00 00 	nop
- 318:	48 3f 0b 00 	pkrlic r1,r1,r31,0x0
- 31c:	00 00 00 00 	nop
- 320:	48 3f 0a 00 	pkrlih r1,r1,r31,0x0
- 324:	00 00 00 00 	nop
- 328:	48 3f 09 00 	pkrliu r1,r1,r31,0x0
- 32c:	00 00 00 00 	nop
- 330:	4c 1f 08 01 	lock r1,r31
- 334:	00 00 00 00 	nop
- 338:	4c 1f 08 03 	unlk r1,r31
- 33c:	00 00 00 00 	nop
- 340:	4c 3f 08 06 	swwr r1,r1,r31
- 344:	00 00 00 00 	nop
- 348:	4c 3f 08 07 	swwru r1,r1,r31
- 34c:	00 00 00 00 	nop
- 350:	4c 01 f8 04 	swrd r31,r1
- 354:	00 00 00 00 	nop
- 358:	4c 01 f8 05 	swrdl r31,r1
- 35c:	00 00 00 00 	nop
- 360:	4c 02 f0 0c 	dwrd r30,r2
- 364:	00 00 00 00 	nop
- 368:	4c 02 f0 0d 	dwrdl r30,r2
- 36c:	00 00 00 00 	nop
- 370:	4c 01 fc 10 	cam36 r31,r1,0x2,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 01 fc 42 	cam72 r31,r1,0x2,0x0
- 37c:	00 00 00 00 	nop
- 380:	4c 01 fc 82 	cam144 r31,r1,0x2,0x0
- 384:	00 00 00 00 	nop
- 388:	4c 01 fc c2 	cam288 r31,r1,0x2,0x0
- 38c:	00 00 00 00 	nop
- 390:	4c 21 f8 ab 	cm32and r31,r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 21 f8 a3 	cm32andn r31,r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 21 f8 aa 	cm32or r31,r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 21 f8 b0 	cm32ra r31,r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 01 f8 a1 	cm32rd r31,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 01 f8 a4 	cm32ri r31,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 21 f8 a0 	cm32rs r31,r1,r1
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 21 f8 b8 	cm32sa r31,r1,r1
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 01 f8 a9 	cm32sd r31,r1
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 01 f8 ac 	cm32si r31,r1
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 21 f8 a8 	cm32ss r31,r1,r1
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 21 f8 a2 	cm32xor r31,r1,r1
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 02 f0 85 	cm64clr r30,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 42 f0 90 	cm64ra r30,r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 02 f0 81 	cm64rd r30,r2
- 404:	00 00 00 00 	nop
- 408:	4c 02 f0 84 	cm64ri r30,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 42 f0 94 	cm64ria2 r30,r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 f0 80 	cm64rs r30,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 42 f0 98 	cm64sa r30,r2,r2
- 424:	00 00 00 00 	nop
- 428:	4c 02 f0 89 	cm64sd r30,r2
- 42c:	00 00 00 00 	nop
- 430:	4c 02 f0 8c 	cm64si r30,r2
- 434:	00 00 00 00 	nop
- 438:	4c 42 f0 9c 	cm64sia2 r30,r2,r2
- 43c:	00 00 00 00 	nop
- 440:	4c 42 f0 88 	cm64ss r30,r2,r2
- 444:	00 00 00 00 	nop
- 448:	4c 42 f0 95 	cm128ria2 r30,r2,r2
- 44c:	00 00 00 00 	nop
- 450:	4c 42 f0 92 	cm128ria3 r30,r2,r2,0x2
- 454:	00 00 00 00 	nop
- 458:	4c 42 f0 b2 	cm128ria4 r30,r2,r2,0x2
- 45c:	00 00 00 00 	nop
- 460:	4c 42 f0 9d 	cm128sia2 r30,r2,r2
- 464:	00 00 00 00 	nop
- 468:	4c 42 f0 9a 	cm128sia3 r30,r2,r2,0x2
- 46c:	00 00 00 00 	nop
- 470:	4c 21 f8 ba 	cm128sia4 r31,r1,r1,0x2
- 474:	00 00 00 00 	nop
- 478:	4c 21 f8 a6 	cm128vsa r31,r1,r1
- 47c:	00 00 00 00 	nop
- 480:	4c 21 f8 14 	crc32 r31,r1,r1
- 484:	00 00 00 00 	nop
- 488:	4c 21 f8 15 	crc32b r31,r1,r1
- 48c:	00 00 00 00 	nop
- 490:	4c 20 f8 26 	chkhdr r31,r1
- 494:	00 00 00 00 	nop
- 498:	4c 00 f8 24 	avail r31
- 49c:	00 00 00 00 	nop
- 4a0:	4c 20 f8 25 	free r31,r1
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 20 f8 27 	tstod r31,r1
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 00 f8 2c 	cmphdr r31
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 01 f8 20 	mcid r31,r1
- 4bc:	00 00 00 00 	nop
- 4c0:	4c 00 f8 22 	dba r31
- 4c4:	00 00 00 00 	nop
- 4c8:	4c 1f 08 21 	dbd r1,r0,r31
- 4cc:	00 00 00 00 	nop
- 4d0:	4f e0 08 23 	dpwt r1,r31
- 4d4:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test2.s b/gas/testsuite/gas/iq2000/q10test2.s
deleted file mode 100644
index 72a83113d9b5..000000000000
--- a/gas/testsuite/gas/iq2000/q10test2.s
+++ /dev/null
@@ -1,312 +0,0 @@
-.global _start

-_start:

-	 ADD	%31,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%31,%1,%1

-	 NOP	

-	 ADO16	%31,%1,%1

-	 NOP	

-	 AND	%31,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%31,%1,%1,0

-	 NOP	

-	 NOR	%31,%1,%1

-	 NOP	

-	 OR	%31,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%31,%1,0

-	 NOP	

-	 SLLV	%31,%1,%1

-	 NOP	

-	 SLT	%31,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%31,%1,%1

-	 NOP	

-	 SRA	%31,%1,0

-	 NOP	

-	 SRAV	%31,%1,%1

-	 NOP	

-	 SRL	%31,%1,0

-	 NOP	

-	 SRLV	%31,%1,%1

-	 NOP	

-	 SUB	%31,%1,%1

-	 NOP	

-	 SUBU	%31,%1,%1

-	 NOP	

-	 XOR	%31,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%31,%1,%1,0

-	 NOP	

-	 SLMV	%31,%1,%1,0

-	 NOP	

-	 RAM	%31,%1,0,0,0

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%31,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%31,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%31

-	 NOP	

-	 RBAR	%1,%1,%31

-	 NOP	

-	 RBAL	%1,%1,%31

-	 NOP	

-	 WBA	%1,%1,%31

-	 NOP	

-	 WBAC	%1,%1,%31

-	 NOP	

-	 WBAU	%1,%1,%31

-	 NOP	

-	 RBI	%1,%1,%31,0

-	 NOP	

-	 RBIR	%1,%1,%31,0

-	 NOP	

-	 RBIL	%1,%1,%31,0

-	 NOP	

-	 WBI	%1,%1,%31,0

-	 NOP	

-	 WBIC	%1,%1,%31,0

-	 NOP	

-	 WBIU	%1,%1,%31,0

-	 NOP	

-	 PKRLA	%1,%1,%31

-	 NOP	

-	 PKRLAC	%1,%1,%31

-	 NOP	

-	 PKRLAH	%1,%1,%31

-	 NOP	

-	 PKRLAU	%1,%1,%31

-	 NOP	

-	 PKRLI	%1,%1,%31,0

-	 NOP	

-	 PKRLIC	%1,%1,%31,0

-	 NOP	

-	 PKRLIH	%1,%1,%31,0

-	 NOP	

-	 PKRLIU	%1,%1,%31,0

-	 NOP	

-	 LOCK	%1,%31

-	 NOP	

-	 UNLK	%1,%31

-	 NOP	

-	 SWWR	%1,%1,%31

-	 NOP	

-	 SWWRU	%1,%1,%31

-	 NOP	

-	 SWRD	%31,%1

-	 NOP	

-	 SWRDL	%31,%1

-	 NOP	

-	 DWRD	%30,%2

-	 NOP	

-	 DWRDL	%30,%2

-	 NOP	

-	 CAM36	%31,%1,2,0

-	 NOP	

-	 CAM72	%31,%1,2,0

-	 NOP	

-	 CAM144	%31,%1,2,0

-	 NOP	

-	 CAM288	%31,%1,2,0

-	 NOP	

-	 CM32AND	%31,%1,%1

-	 NOP	

-	 CM32ANDN	%31,%1,%1

-	 NOP	

-	 CM32OR	%31,%1,%1

-	 NOP	

-	 CM32RA	%31,%1,%1

-	 NOP	

-	 CM32RD	%31,%1

-	 NOP	

-	 CM32RI	%31,%1

-	 NOP	

-	 CM32RS	%31,%1,%1

-	 NOP	

-	 CM32SA	%31,%1,%1

-	 NOP	

-	 CM32SD	%31,%1

-	 NOP	

-	 CM32SI	%31,%1

-	 NOP	

-	 CM32SS	%31,%1,%1

-	 NOP	

-	 CM32XOR	%31,%1,%1

-	 NOP	

-	 CM64CLR	%30,%2

-	 NOP	

-	 CM64RA	%30,%2,%2

-	 NOP	

-	 CM64RD	%30,%2

-	 NOP	

-	 CM64RI	%30,%2

-	 NOP	

-	 CM64RIA2	%30,%2,%2

-	 NOP	

-	 CM64RS	%30,%2,%2

-	 NOP	

-	 CM64SA	%30,%2,%2

-	 NOP	

-	 CM64SD	%30,%2

-	 NOP	

-	 CM64SI	%30,%2

-	 NOP	

-	 CM64SIA2	%30,%2,%2

-	 NOP	

-	 CM64SS	%30,%2,%2

-	 NOP	

-	 CM128RIA2	%30,%2,%2

-	 NOP	

-	 CM128RIA3	%30,%2,%2,2

-	 NOP	

-	 CM128RIA4	%30,%2,%2,2

-	 NOP	

-	 CM128SIA2	%30,%2,%2

-	 NOP	

-	 CM128SIA3	%30,%2,%2,2

-	 NOP	

-	 CM128SIA4	%31,%1,%1,2

-	 NOP	

-	 CM128VSA	%31,%1,%1

-	 NOP	

-	 CRC32	%31,%1,%1

-	 NOP	

-	 CRC32B	%31,%1,%1

-	 NOP	

-	 CHKHDR	%31,%1

-	 NOP	

-	 AVAIL	%31

-	 NOP	

-	 FREE	%31,%1

-	 NOP	

-	 TSTOD	%31,%1

-	 NOP	

-	 CMPHDR	%31

-	 NOP	

-	 MCID	%31,%1

-	 NOP	

-	 DBA	%31

-	 NOP	

-	 DBD	%1,%31

-	 NOP	

-	 DPWT	%1,%31

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test3.d b/gas/testsuite/gas/iq2000/q10test3.d
deleted file mode 100644
index a32acdd6ddbc..000000000000
--- a/gas/testsuite/gas/iq2000/q10test3.d
+++ /dev/null
@@ -1,313 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test3
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 3f 08 20 	add r1,r1,r31
-   4:	00 00 00 00 	nop
-   8:	20 3f 00 00 	addi r31,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 3f 00 00 	addiu r31,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 3f 08 21 	addu r1,r1,r31
-  1c:	00 00 00 00 	nop
-  20:	00 3f 08 29 	ado16 r1,r1,r31
-  24:	00 00 00 00 	nop
-  28:	00 3f 08 24 	and r1,r1,r31
-  2c:	00 00 00 00 	nop
-  30:	30 3f 00 00 	andi r31,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 3f 00 00 	andoi r31,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 3f 00 00 	andoui r31,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 1f 00 00 	lui r31,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 3f 08 2d 	mrgb r1,r1,r31,0x0
-  54:	00 00 00 00 	nop
-  58:	00 3f 08 27 	nor r1,r1,r31
-  5c:	00 00 00 00 	nop
-  60:	00 3f 08 25 	or r1,r1,r31
-  64:	00 00 00 00 	nop
-  68:	34 3f 00 00 	ori r31,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 3f 00 00 	orui r31,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 1f 08 00 	sll r1,r31,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 3f 08 04 	sllv r1,r31,r1
-  84:	00 00 00 00 	nop
-  88:	00 3f 08 2a 	slt r1,r1,r31
-  8c:	00 00 00 00 	nop
-  90:	28 3f 00 00 	slti r31,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 3f 00 00 	sltiu r31,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 3f 08 2b 	sltu r1,r1,r31
-  a4:	00 00 00 00 	nop
-  a8:	00 1f 08 03 	sra r1,r31,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 3f 08 07 	srav r1,r31,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 1f 08 02 	srl r1,r31,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 3f 08 06 	srlv r1,r31,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 3f 08 22 	sub r1,r1,r31
-  cc:	00 00 00 00 	nop
-  d0:	00 3f 08 23 	subu r1,r1,r31
-  d4:	00 00 00 00 	nop
-  d8:	00 3f 08 26 	xor r1,r1,r31
-  dc:	00 00 00 00 	nop
-  e0:	38 3f 00 00 	xori r31,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	03 e1 08 05 	srmv r1,r1,r31,0x0
-  f4:	00 00 00 00 	nop
-  f8:	03 e1 08 01 	slmv r1,r1,r31,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 1f 08 00 	ram r1,r31,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 3f ff b9 	bbv r1,r31,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 3f ff b7 	bbvn r1,r31,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 3f ff b1 	bbvl r1,r31,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 3f ff af 	bbvnl r1,r31,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 3f ff ad 	beq r1,r31,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 3f ff ab 	beql r1,r31,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 3f ff 89 	bmb r1,r31,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 3f ff 87 	bmbl r1,r31,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 3f ff 85 	bmb0 r1,r31,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 3f ff 83 	bmb1 r1,r31,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 3f ff 81 	bmb2 r1,r31,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 3f ff 7f 	bmb3 r1,r31,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 3f ff 7d 	bne r1,r31,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 3f ff 7b 	bnel r1,r31,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 3f 00 02 	ctc r1,r31
- 244:	00 00 00 00 	nop
- 248:	4c 1f 08 00 	cfc r1,r31
- 24c:	00 00 00 00 	nop
- 250:	8c 3f 00 00 	lw r31,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 3f 00 00 	lh r31,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 3f 00 00 	lb r31,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 3f 00 00 	lhu r31,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 3f 00 00 	lbu r31,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 3f 00 00 	sb r31,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 3f 00 00 	sh r31,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 3f 00 00 	sw r31,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4f e1 08 08 	rba r1,r31,r1
- 294:	00 00 00 00 	nop
- 298:	4f e1 08 0a 	rbar r1,r31,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4f e1 08 09 	rbal r1,r31,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4f e1 08 10 	wba r1,r31,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4f e1 08 12 	wbac r1,r31,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4f e1 08 11 	wbau r1,r31,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4f e1 0a 00 	rbi r1,r31,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4f e1 09 00 	rbir r1,r31,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4f e1 0b 00 	rbil r1,r31,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4f e1 0e 00 	wbi r1,r31,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4f e1 0d 00 	wbic r1,r31,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4f e1 0f 00 	wbiu r1,r31,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4f e1 08 28 	pkrla r1,r31,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4f e1 08 2a 	pkrlah r1,r31,r1
- 2fc:	00 00 00 00 	nop
- 300:	4f e1 08 29 	pkrlau r1,r31,r1
- 304:	00 00 00 00 	nop
- 308:	4b e1 08 00 	pkrli r1,r31,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	4b e1 0a 00 	pkrlih r1,r31,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	4b e1 09 00 	pkrliu r1,r31,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 f8 01 	lock r31,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 f8 03 	unlk r31,r1
- 32c:	00 00 00 00 	nop
- 330:	4f e1 08 06 	swwr r1,r31,r1
- 334:	00 00 00 00 	nop
- 338:	4f e1 08 07 	swwru r1,r31,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 1f 08 04 	swrd r1,r31
- 344:	00 00 00 00 	nop
- 348:	4c 1f 08 05 	swrdl r1,r31
- 34c:	00 00 00 00 	nop
- 350:	4c 1e 10 0c 	dwrd r2,r30
- 354:	00 00 00 00 	nop
- 358:	4c 1e 10 0d 	dwrdl r2,r30
- 35c:	00 00 00 00 	nop
- 360:	4c 1f 0c 18 	cam36 r1,r31,0x3,0x0
- 364:	00 00 00 00 	nop
- 368:	4c 1f 0c 43 	cam72 r1,r31,0x3,0x0
- 36c:	00 00 00 00 	nop
- 370:	4c 1f 0c 83 	cam144 r1,r31,0x3,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 1f 0c c3 	cam288 r1,r31,0x3,0x0
- 37c:	00 00 00 00 	nop
- 380:	4c 3f 08 ab 	cm32and r1,r1,r31
- 384:	00 00 00 00 	nop
- 388:	4c 3f 08 a3 	cm32andn r1,r1,r31
- 38c:	00 00 00 00 	nop
- 390:	4c 3f 08 aa 	cm32or r1,r1,r31
- 394:	00 00 00 00 	nop
- 398:	4c 3f 08 b0 	cm32ra r1,r1,r31
- 39c:	00 00 00 00 	nop
- 3a0:	4c 1f 08 a1 	cm32rd r1,r31
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 1f 08 a4 	cm32ri r1,r31
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 3f 08 a0 	cm32rs r1,r1,r31
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 3f 08 b8 	cm32sa r1,r1,r31
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 1f 08 a9 	cm32sd r1,r31
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 1f 08 ac 	cm32si r1,r31
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 3f 08 a8 	cm32ss r1,r1,r31
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 3f 08 a2 	cm32xor r1,r1,r31
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 1e 10 85 	cm64clr r2,r30
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 5e 10 90 	cm64ra r2,r2,r30
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 1e 10 81 	cm64rd r2,r30
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 1e 10 84 	cm64ri r2,r30
- 3fc:	00 00 00 00 	nop
- 400:	4c 5e 10 94 	cm64ria2 r2,r2,r30
- 404:	00 00 00 00 	nop
- 408:	4c 5e 10 80 	cm64rs r2,r2,r30
- 40c:	00 00 00 00 	nop
- 410:	4c 5e 10 98 	cm64sa r2,r2,r30
- 414:	00 00 00 00 	nop
- 418:	4c 1e 10 89 	cm64sd r2,r30
- 41c:	00 00 00 00 	nop
- 420:	4c 1e 10 8c 	cm64si r2,r30
- 424:	00 00 00 00 	nop
- 428:	4c 5e 10 9c 	cm64sia2 r2,r2,r30
- 42c:	00 00 00 00 	nop
- 430:	4c 5e 10 88 	cm64ss r2,r2,r30
- 434:	00 00 00 00 	nop
- 438:	4c 5e 10 95 	cm128ria2 r2,r2,r30
- 43c:	00 00 00 00 	nop
- 440:	4c 5e 10 93 	cm128ria3 r2,r2,r30,0x3
- 444:	00 00 00 00 	nop
- 448:	4c 5e 10 b3 	cm128ria4 r2,r2,r30,0x3
- 44c:	00 00 00 00 	nop
- 450:	4c 5e 10 9d 	cm128sia2 r2,r2,r30
- 454:	00 00 00 00 	nop
- 458:	4c 5e 10 9b 	cm128sia3 r2,r2,r30,0x3
- 45c:	00 00 00 00 	nop
- 460:	4c 3f 08 bb 	cm128sia4 r1,r1,r31,0x3
- 464:	00 00 00 00 	nop
- 468:	4c 3f 08 a6 	cm128vsa r1,r1,r31
- 46c:	00 00 00 00 	nop
- 470:	4c 3f 08 14 	crc32 r1,r1,r31
- 474:	00 00 00 00 	nop
- 478:	4c 3f 08 15 	crc32b r1,r1,r31
- 47c:	00 00 00 00 	nop
- 480:	4f e0 08 26 	chkhdr r1,r31
- 484:	00 00 00 00 	nop
- 488:	4c 00 08 24 	avail r1
- 48c:	00 00 00 00 	nop
- 490:	4c 20 f8 25 	free r31,r1
- 494:	00 00 00 00 	nop
- 498:	4c 00 08 2c 	cmphdr r1
- 49c:	00 00 00 00 	nop
- 4a0:	4c 1f 08 20 	mcid r1,r31
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 00 f8 22 	dba r31
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 01 f8 21 	dbd r31,r0,r1
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 20 f8 23 	dpwt r31,r1
- 4bc:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test3.s b/gas/testsuite/gas/iq2000/q10test3.s
deleted file mode 100644
index c5f0f3267c07..000000000000
--- a/gas/testsuite/gas/iq2000/q10test3.s
+++ /dev/null
@@ -1,306 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%31

-	 NOP	

-	 ADDI	%31,%1,0

-	 NOP	

-	 ADDIU	%31,%1,0

-	 NOP	

-	 ADDU	%1,%1,%31

-	 NOP	

-	 ADO16	%1,%1,%31

-	 NOP	

-	 AND	%1,%1,%31

-	 NOP	

-	 ANDI	%31,%1,0

-	 NOP	

-	 ANDOI	%31,%1,0

-	 NOP	

-	 ANDOUI	%31,%1,0

-	 NOP	

-	 LUI	%31,0

-	 NOP	

-	 MRGB	%1,%1,%31,0

-	 NOP	

-	 NOR	%1,%1,%31

-	 NOP	

-	 OR	%1,%1,%31

-	 NOP	

-	 ORI	%31,%1,0

-	 NOP	

-	 ORUI	%31,%1,0

-	 NOP	

-	 SLL	%1,%31,0

-	 NOP	

-	 SLLV	%1,%31,%1

-	 NOP	

-	 SLT	%1,%1,%31

-	 NOP	

-	 SLTI	%31,%1,0

-	 NOP	

-	 SLTIU	%31,%1,0

-	 NOP	

-	 SLTU	%1,%1,%31

-	 NOP	

-	 SRA	%1,%31,0

-	 NOP	

-	 SRAV	%1,%31,%1

-	 NOP	

-	 SRL	%1,%31,0

-	 NOP	

-	 SRLV	%1,%31,%1

-	 NOP	

-	 SUB	%1,%1,%31

-	 NOP	

-	 SUBU	%1,%1,%31

-	 NOP	

-	 XOR	%1,%1,%31

-	 NOP	

-	 XORI	%31,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%31,0

-	 NOP	

-	 SLMV	%1,%1,%31,0

-	 NOP	

-	 RAM	%1,%31,0,0,0

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%31,_start

-	 NOP	

-	 BBVN	%1,%31,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%31,_start

-	 NOP	

-	 BBVNL	%1,%31,_start

-	 NOP	

-	 BEQ	%1,%31,_start

-	 NOP	

-	 BEQL	%1,%31,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%31,_start

-	 NOP	

-	 BMBL	%1,%31,_start

-	 NOP	

-	 BMB0	%1,%31,_start

-	 NOP	

-	 BMB1	%1,%31,_start

-	 NOP	

-	 BMB2	%1,%31,_start

-	 NOP	

-	 BMB3	%1,%31,_start

-	 NOP	

-	 BNE	%1,%31,_start

-	 NOP	

-	 BNEL	%1,%31,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%31

-	 NOP	

-	 CFC	%1,%31

-	 NOP	

-	 LW	%31,0(%1)

-	 NOP	

-	 LH	%31,0(%1)

-	 NOP	

-	 LB	%31,0(%1)

-	 NOP	

-	 LHU	%31,0(%1)

-	 NOP	

-	 LBU	%31,0(%1)

-	 NOP	

-	 SB	%31,0(%1)

-	 NOP	

-	 SH	%31,0(%1)

-	 NOP	

-	 SW	%31,0(%1)

-	 NOP	

-	 RBA	%1,%31,%1

-	 NOP	

-	 RBAR	%1,%31,%1

-	 NOP	

-	 RBAL	%1,%31,%1

-	 NOP	

-	 WBA	%1,%31,%1

-	 NOP	

-	 WBAC	%1,%31,%1

-	 NOP	

-	 WBAU	%1,%31,%1

-	 NOP	

-	 RBI	%1,%31,%1,0

-	 NOP	

-	 RBIR	%1,%31,%1,0

-	 NOP	

-	 RBIL	%1,%31,%1,0

-	 NOP	

-	 WBI	%1,%31,%1,0

-	 NOP	

-	 WBIC	%1,%31,%1,0

-	 NOP	

-	 WBIU	%1,%31,%1,0

-	 NOP	

-	 PKRLA	%1,%31,%1

-	 NOP	

-	 PKRLAH	%1,%31,%1

-	 NOP	

-	 PKRLAU	%1,%31,%1

-	 NOP	

-	 PKRLI	%1,%31,%1,0

-	 NOP	

-	 PKRLIH	%1,%31,%1,0

-	 NOP	

-	 PKRLIU	%1,%31,%1,0

-	 NOP	

-	 LOCK	%31,%1

-	 NOP	

-	 UNLK	%31,%1

-	 NOP	

-	 SWWR	%1,%31,%1

-	 NOP	

-	 SWWRU	%1,%31,%1

-	 NOP	

-	 SWRD	%1,%31

-	 NOP	

-	 SWRDL	%1,%31

-	 NOP	

-	 DWRD	%2,%30

-	 NOP	

-	 DWRDL	%2,%30

-	 NOP	

-	 CAM36	%1,%31,3,0

-	 NOP	

-	 CAM72	%1,%31,3,0

-	 NOP	

-	 CAM144	%1,%31,3,0

-	 NOP	

-	 CAM288	%1,%31,3,0

-	 NOP	

-	 CM32AND	%1,%1,%31

-	 NOP	

-	 CM32ANDN	%1,%1,%31

-	 NOP	

-	 CM32OR	%1,%1,%31

-	 NOP	

-	 CM32RA	%1,%1,%31

-	 NOP	

-	 CM32RD	%1,%31

-	 NOP	

-	 CM32RI	%1,%31

-	 NOP	

-	 CM32RS	%1,%1,%31

-	 NOP	

-	 CM32SA	%1,%1,%31

-	 NOP	

-	 CM32SD	%1,%31

-	 NOP	

-	 CM32SI	%1,%31

-	 NOP	

-	 CM32SS	%1,%1,%31

-	 NOP	

-	 CM32XOR	%1,%1,%31

-	 NOP	

-	 CM64CLR	%2,%30

-	 NOP	

-	 CM64RA	%2,%2,%30

-	 NOP	

-	 CM64RD	%2,%30

-	 NOP	

-	 CM64RI	%2,%30

-	 NOP	

-	 CM64RIA2	%2,%2,%30

-	 NOP	

-	 CM64RS	%2,%2,%30

-	 NOP	

-	 CM64SA	%2,%2,%30

-	 NOP	

-	 CM64SD	%2,%30

-	 NOP	

-	 CM64SI	%2,%30

-	 NOP	

-	 CM64SIA2	%2,%2,%30

-	 NOP	

-	 CM64SS	%2,%2,%30

-	 NOP	

-	 CM128RIA2	%2,%2,%30

-	 NOP	

-	 CM128RIA3	%2,%2,%30,3

-	 NOP	

-	 CM128RIA4	%2,%2,%30,3

-	 NOP	

-	 CM128SIA2	%2,%2,%30

-	 NOP	

-	 CM128SIA3	%2,%2,%30,3

-	 NOP	

-	 CM128SIA4	%1,%1,%31,3

-	 NOP	

-	 CM128VSA	%1,%1,%31

-	 NOP	

-	 CRC32	%1,%1,%31

-	 NOP	

-	 CRC32B	%1,%1,%31

-	 NOP	

-	 CHKHDR	%1,%31

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%31,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%31

-	 NOP	

-	 DBA	%31

-	 NOP	

-	 DBD	%31,%1

-	 NOP	

-	 DPWT	%31,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test4.d b/gas/testsuite/gas/iq2000/q10test4.d
deleted file mode 100644
index 3b3a77fe3d82..000000000000
--- a/gas/testsuite/gas/iq2000/q10test4.d
+++ /dev/null
@@ -1,315 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test4
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	03 df 08 20 	add r1,r30,r31
-   4:	00 00 00 00 	nop
-   8:	23 df 00 00 	addi r31,r30,0x0
-   c:	00 00 00 00 	nop
-  10:	27 df 00 00 	addiu r31,r30,0x0
-  14:	00 00 00 00 	nop
-  18:	03 df 08 21 	addu r1,r30,r31
-  1c:	00 00 00 00 	nop
-  20:	03 df 08 29 	ado16 r1,r30,r31
-  24:	00 00 00 00 	nop
-  28:	03 df 08 24 	and r1,r30,r31
-  2c:	00 00 00 00 	nop
-  30:	33 df 00 00 	andi r31,r30,0x0
-  34:	00 00 00 00 	nop
-  38:	b3 df 00 00 	andoi r31,r30,0x0
-  3c:	00 00 00 00 	nop
-  40:	bf df 00 00 	andoui r31,r30,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 1f 00 00 	lui r31,0x0
-  4c:	00 00 00 00 	nop
-  50:	03 df 08 2d 	mrgb r1,r30,r31,0x0
-  54:	00 00 00 00 	nop
-  58:	03 df 08 27 	nor r1,r30,r31
-  5c:	00 00 00 00 	nop
-  60:	03 df 08 25 	or r1,r30,r31
-  64:	00 00 00 00 	nop
-  68:	37 df 00 00 	ori r31,r30,0x0
-  6c:	00 00 00 00 	nop
-  70:	3f df 00 00 	orui r31,r30,0x0
-  74:	00 00 00 00 	nop
-  78:	00 1f 08 00 	sll r1,r31,0x0
-  7c:	00 00 00 00 	nop
-  80:	03 df 08 04 	sllv r1,r31,r30
-  84:	00 00 00 00 	nop
-  88:	03 df 08 2a 	slt r1,r30,r31
-  8c:	00 00 00 00 	nop
-  90:	2b df 00 00 	slti r31,r30,0x0
-  94:	00 00 00 00 	nop
-  98:	2f df 00 00 	sltiu r31,r30,0x0
-  9c:	00 00 00 00 	nop
-  a0:	03 df 08 2b 	sltu r1,r30,r31
-  a4:	00 00 00 00 	nop
-  a8:	00 1f 08 03 	sra r1,r31,0x0
-  ac:	00 00 00 00 	nop
-  b0:	03 df 08 07 	srav r1,r31,r30
-  b4:	00 00 00 00 	nop
-  b8:	00 1f 08 02 	srl r1,r31,0x0
-  bc:	00 00 00 00 	nop
-  c0:	03 df 08 06 	srlv r1,r31,r30
-  c4:	00 00 00 00 	nop
-  c8:	03 df 08 22 	sub r1,r30,r31
-  cc:	00 00 00 00 	nop
-  d0:	03 df 08 23 	subu r1,r30,r31
-  d4:	00 00 00 00 	nop
-  d8:	03 df 08 26 	xor r1,r30,r31
-  dc:	00 00 00 00 	nop
-  e0:	3b df 00 00 	xori r31,r30,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	03 fe 08 05 	srmv r1,r30,r31,0x0
-  f4:	00 00 00 00 	nop
-  f8:	03 fe 08 01 	slmv r1,r30,r31,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 1f 08 00 	ram r1,r31,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	73 c0 ff bd 	bbi r30\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	7b c0 ff bb 	bbin r30\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	77 df ff b9 	bbv r30,r31,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7f df ff b7 	bbvn r30,r31,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f3 c0 ff b5 	bbil r30\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	fb c0 ff b3 	bbinl r30\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f7 df ff b1 	bbvl r30,r31,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	ff df ff af 	bbvnl r30,r31,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	13 df ff ad 	beq r30,r31,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	53 df ff ab 	beql r30,r31,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	07 c1 ff a9 	bgez r30,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	07 d5 ff a7 	bgtzal r30,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	07 d1 ff a5 	bgezal r30,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	07 d7 ff a3 	bgtzall r30,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	07 d3 ff a1 	bgezall r30,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	07 c3 ff 9f 	bgezl r30,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	07 c7 ff 9d 	bgtzl r30,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	07 c5 ff 9b 	bgtz r30,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	07 c4 ff 99 	blez r30,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	07 d4 ff 97 	blezal r30,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	07 c0 ff 95 	bltz r30,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	07 d0 ff 93 	bltzal r30,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	07 c6 ff 91 	blezl r30,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	07 c2 ff 8f 	bltzl r30,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	07 d6 ff 8d 	blezall r30,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	07 d2 ff 8b 	bltzall r30,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	1b df ff 89 	bmb r30,r31,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	5b df ff 87 	bmbl r30,r31,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	63 df ff 85 	bmb0 r30,r31,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	67 df ff 83 	bmb1 r30,r31,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	6b df ff 81 	bmb2 r30,r31,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6f df ff 7f 	bmb3 r30,r31,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	17 df ff 7d 	bne r30,r31,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	57 df ff 7b 	bnel r30,r31,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 1e 00 00 	jal r30,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	03 c0 08 09 	jalr r1,r30
- 22c:	00 00 00 00 	nop
- 230:	03 c0 00 08 	jr r30
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4f df 00 02 	ctc r30,r31
- 244:	00 00 00 00 	nop
- 248:	4c 1f 08 00 	cfc r1,r31
- 24c:	00 00 00 00 	nop
- 250:	8f df 00 00 	lw r31,0x0\(r30\)
- 254:	00 00 00 00 	nop
- 258:	87 df 00 00 	lh r31,0x0\(r30\)
- 25c:	00 00 00 00 	nop
- 260:	83 df 00 00 	lb r31,0x0\(r30\)
- 264:	00 00 00 00 	nop
- 268:	97 df 00 00 	lhu r31,0x0\(r30\)
- 26c:	00 00 00 00 	nop
- 270:	93 df 00 00 	lbu r31,0x0\(r30\)
- 274:	00 00 00 00 	nop
- 278:	a3 df 00 00 	sb r31,0x0\(r30\)
- 27c:	00 00 00 00 	nop
- 280:	a7 df 00 00 	sh r31,0x0\(r30\)
- 284:	00 00 00 00 	nop
- 288:	af df 00 00 	sw r31,0x0\(r30\)
- 28c:	00 00 00 00 	nop
- 290:	4f e1 f0 08 	rba r30,r31,r1
- 294:	00 00 00 00 	nop
- 298:	4f e1 f0 0a 	rbar r30,r31,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4f e1 f0 09 	rbal r30,r31,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4f e1 f0 10 	wba r30,r31,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4f e1 f0 12 	wbac r30,r31,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4f e1 f0 11 	wbau r30,r31,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4f e1 f2 00 	rbi r30,r31,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4f e1 f1 00 	rbir r30,r31,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4f e1 f3 00 	rbil r30,r31,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4f e1 f6 00 	wbi r30,r31,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4f e1 f5 00 	wbic r30,r31,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4f e1 f7 00 	wbiu r30,r31,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4f e1 f0 28 	pkrla r30,r31,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4f e1 f0 2a 	pkrlah r30,r31,r1
- 2fc:	00 00 00 00 	nop
- 300:	4f e1 f0 29 	pkrlau r30,r31,r1
- 304:	00 00 00 00 	nop
- 308:	4b e1 f0 00 	pkrli r30,r31,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	4b e1 f2 00 	pkrlih r30,r31,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	4b e1 f1 00 	pkrliu r30,r31,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 f8 01 	lock r31,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 f8 03 	unlk r31,r1
- 32c:	00 00 00 00 	nop
- 330:	4f e1 f0 06 	swwr r30,r31,r1
- 334:	00 00 00 00 	nop
- 338:	4f e1 f0 07 	swwru r30,r31,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 1f 08 04 	swrd r1,r31
- 344:	00 00 00 00 	nop
- 348:	4c 1f 08 05 	swrdl r1,r31
- 34c:	00 00 00 00 	nop
- 350:	4c 1e 10 0c 	dwrd r2,r30
- 354:	00 00 00 00 	nop
- 358:	4c 1e 10 0d 	dwrdl r2,r30
- 35c:	00 00 00 00 	nop
- 360:	4c 1e 0c 20 	cam36 r1,r30,0x4,0x0
- 364:	00 00 00 00 	nop
- 368:	4c 1e 0c 44 	cam72 r1,r30,0x4,0x0
- 36c:	00 00 00 00 	nop
- 370:	4c 1e 0c 84 	cam144 r1,r30,0x4,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 1e 0c c4 	cam288 r1,r30,0x4,0x0
- 37c:	00 00 00 00 	nop
- 380:	4f df 08 ab 	cm32and r1,r30,r31
- 384:	00 00 00 00 	nop
- 388:	4f df 08 a3 	cm32andn r1,r30,r31
- 38c:	00 00 00 00 	nop
- 390:	4f df 08 aa 	cm32or r1,r30,r31
- 394:	00 00 00 00 	nop
- 398:	4f df 08 b0 	cm32ra r1,r30,r31
- 39c:	00 00 00 00 	nop
- 3a0:	4c 1f 08 a1 	cm32rd r1,r31
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 1f 08 a4 	cm32ri r1,r31
- 3ac:	00 00 00 00 	nop
- 3b0:	4f df 08 a0 	cm32rs r1,r30,r31
- 3b4:	00 00 00 00 	nop
- 3b8:	4f df 08 b8 	cm32sa r1,r30,r31
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 1f 08 a9 	cm32sd r1,r31
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 1f 08 ac 	cm32si r1,r31
- 3cc:	00 00 00 00 	nop
- 3d0:	4f df 08 a8 	cm32ss r1,r30,r31
- 3d4:	00 00 00 00 	nop
- 3d8:	4f df 08 a2 	cm32xor r1,r30,r31
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 1e 10 85 	cm64clr r2,r30
- 3e4:	00 00 00 00 	nop
- 3e8:	4f de 10 90 	cm64ra r2,r30,r30
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 1e 10 81 	cm64rd r2,r30
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 1e 10 84 	cm64ri r2,r30
- 3fc:	00 00 00 00 	nop
- 400:	4f de 10 94 	cm64ria2 r2,r30,r30
- 404:	00 00 00 00 	nop
- 408:	4f de 10 80 	cm64rs r2,r30,r30
- 40c:	00 00 00 00 	nop
- 410:	4f de 10 98 	cm64sa r2,r30,r30
- 414:	00 00 00 00 	nop
- 418:	4c 1e 10 89 	cm64sd r2,r30
- 41c:	00 00 00 00 	nop
- 420:	4c 1e 10 8c 	cm64si r2,r30
- 424:	00 00 00 00 	nop
- 428:	4f de 10 9c 	cm64sia2 r2,r30,r30
- 42c:	00 00 00 00 	nop
- 430:	4f de 10 88 	cm64ss r2,r30,r30
- 434:	00 00 00 00 	nop
- 438:	4f de 10 95 	cm128ria2 r2,r30,r30
- 43c:	00 00 00 00 	nop
- 440:	4f de 10 93 	cm128ria3 r2,r30,r30,0x3
- 444:	00 00 00 00 	nop
- 448:	4f de 10 b4 	cm128ria4 r2,r30,r30,0x4
- 44c:	00 00 00 00 	nop
- 450:	4f de 10 9d 	cm128sia2 r2,r30,r30
- 454:	00 00 00 00 	nop
- 458:	4f de 10 9b 	cm128sia3 r2,r30,r30,0x3
- 45c:	00 00 00 00 	nop
- 460:	4f df 08 bc 	cm128sia4 r1,r30,r31,0x4
- 464:	00 00 00 00 	nop
- 468:	4f df 08 a6 	cm128vsa r1,r30,r31
- 46c:	00 00 00 00 	nop
- 470:	4f df 08 14 	crc32 r1,r30,r31
- 474:	00 00 00 00 	nop
- 478:	4f df 08 15 	crc32b r1,r30,r31
- 47c:	00 00 00 00 	nop
- 480:	4f e0 08 26 	chkhdr r1,r31
- 484:	00 00 00 00 	nop
- 488:	4c 00 08 24 	avail r1
- 48c:	00 00 00 00 	nop
- 490:	4c 20 f8 25 	free r31,r1
- 494:	00 00 00 00 	nop
- 498:	4c 20 f8 27 	tstod r31,r1
- 49c:	00 00 00 00 	nop
- 4a0:	4c 00 08 2c 	cmphdr r1
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 1f 08 20 	mcid r1,r31
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 00 f0 22 	dba r30
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 01 f8 21 	dbd r31,r0,r1
- 4bc:	00 00 00 00 	nop
- 4c0:	4c 20 f8 23 	dpwt r31,r1
- 4c4:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test4.s b/gas/testsuite/gas/iq2000/q10test4.s
deleted file mode 100644
index 3ef2ef9cd318..000000000000
--- a/gas/testsuite/gas/iq2000/q10test4.s
+++ /dev/null
@@ -1,308 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%30,%31

-	 NOP	

-	 ADDI	%31,%30,0

-	 NOP	

-	 ADDIU	%31,%30,0

-	 NOP	

-	 ADDU	%1,%30,%31

-	 NOP	

-	 ADO16	%1,%30,%31

-	 NOP	

-	 AND	%1,%30,%31

-	 NOP	

-	 ANDI	%31,%30,0

-	 NOP	

-	 ANDOI	%31,%30,0

-	 NOP	

-	 ANDOUI	%31,%30,0

-	 NOP	

-	 LUI	%31,0

-	 NOP	

-	 MRGB	%1,%30,%31,0

-	 NOP	

-	 NOR	%1,%30,%31

-	 NOP	

-	 OR	%1,%30,%31

-	 NOP	

-	 ORI	%31,%30,0

-	 NOP	

-	 ORUI	%31,%30,0

-	 NOP	

-	 SLL	%1,%31,0

-	 NOP	

-	 SLLV	%1,%31,%30

-	 NOP	

-	 SLT	%1,%30,%31

-	 NOP	

-	 SLTI	%31,%30,0

-	 NOP	

-	 SLTIU	%31,%30,0

-	 NOP	

-	 SLTU	%1,%30,%31

-	 NOP	

-	 SRA	%1,%31,0

-	 NOP	

-	 SRAV	%1,%31,%30

-	 NOP	

-	 SRL	%1,%31,0

-	 NOP	

-	 SRLV	%1,%31,%30

-	 NOP	

-	 SUB	%1,%30,%31

-	 NOP	

-	 SUBU	%1,%30,%31

-	 NOP	

-	 XOR	%1,%30,%31

-	 NOP	

-	 XORI	%31,%30,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%30,%31,0

-	 NOP	

-	 SLMV	%1,%30,%31,0

-	 NOP	

-	 RAM	%1,%31,0,0,0

-	 NOP	

-	 BBI	%30(0),_start

-	 NOP	

-	 BBIN	%30(0),_start

-	 NOP	

-	 BBV	%30,%31,_start

-	 NOP	

-	 BBVN	%30,%31,_start

-	 NOP	

-	 BBIL	%30(0),_start

-	 NOP	

-	 BBINL	%30(0),_start

-	 NOP	

-	 BBVL	%30,%31,_start

-	 NOP	

-	 BBVNL	%30,%31,_start

-	 NOP	

-	 BEQ	%30,%31,_start

-	 NOP	

-	 BEQL	%30,%31,_start

-	 NOP	

-	 BGEZ	%30,_start

-	 NOP	

-	 BGTZAL	%30,_start

-	 NOP	

-	 BGEZAL	%30,_start

-	 NOP	

-	 BGTZALL	%30,_start

-	 NOP	

-	 BGEZALL	%30,_start

-	 NOP	

-	 BGEZL	%30,_start

-	 NOP	

-	 BGTZL	%30,_start

-	 NOP	

-	 BGTZ	%30,_start

-	 NOP	

-	 BLEZ	%30,_start

-	 NOP	

-	 BLEZAL	%30,_start

-	 NOP	

-	 BLTZ	%30,_start

-	 NOP	

-	 BLTZAL	%30,_start

-	 NOP	

-	 BLEZL	%30,_start

-	 NOP	

-	 BLTZL	%30,_start

-	 NOP	

-	 BLEZALL	%30,_start

-	 NOP	

-	 BLTZALL	%30,_start

-	 NOP	

-	 BMB	%30,%31,_start

-	 NOP	

-	 BMBL	%30,%31,_start

-	 NOP	

-	 BMB0	%30,%31,_start

-	 NOP	

-	 BMB1	%30,%31,_start

-	 NOP	

-	 BMB2	%30,%31,_start

-	 NOP	

-	 BMB3	%30,%31,_start

-	 NOP	

-	 BNE	%30,%31,_start

-	 NOP	

-	 BNEL	%30,%31,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%30,0

-	 NOP	

-	 JALR	%1,%30

-	 NOP	

-	 JR	%30

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%30,%31

-	 NOP	

-	 CFC	%1,%31

-	 NOP	

-	 LW	%31,0(%30)

-	 NOP	

-	 LH	%31,0(%30)

-	 NOP	

-	 LB	%31,0(%30)

-	 NOP	

-	 LHU	%31,0(%30)

-	 NOP	

-	 LBU	%31,0(%30)

-	 NOP	

-	 SB	%31,0(%30)

-	 NOP	

-	 SH	%31,0(%30)

-	 NOP	

-	 SW	%31,0(%30)

-	 NOP	

-	 RBA	%30,%31,%1

-	 NOP	

-	 RBAR	%30,%31,%1

-	 NOP	

-	 RBAL	%30,%31,%1

-	 NOP	

-	 WBA	%30,%31,%1

-	 NOP	

-	 WBAC	%30,%31,%1

-	 NOP	

-	 WBAU	%30,%31,%1

-	 NOP	

-	 RBI	%30,%31,%1,0

-	 NOP	

-	 RBIR	%30,%31,%1,0

-	 NOP	

-	 RBIL	%30,%31,%1,0

-	 NOP	

-	 WBI	%30,%31,%1,0

-	 NOP	

-	 WBIC	%30,%31,%1,0

-	 NOP	

-	 WBIU	%30,%31,%1,0

-	 NOP	

-	 PKRLA	%30,%31,%1

-	 NOP	

-	 PKRLAH	%30,%31,%1

-	 NOP	

-	 PKRLAU	%30,%31,%1

-	 NOP	

-	 PKRLI	%30,%31,%1,0

-	 NOP	

-	 PKRLIH	%30,%31,%1,0

-	 NOP	

-	 PKRLIU	%30,%31,%1,0

-	 NOP	

-	 LOCK	%31,%1

-	 NOP	

-	 UNLK	%31,%1

-	 NOP	

-	 SWWR	%30,%31,%1

-	 NOP	

-	 SWWRU	%30,%31,%1

-	 NOP	

-	 SWRD	%1,%31

-	 NOP	

-	 SWRDL	%1,%31

-	 NOP	

-	 DWRD	%2,%30

-	 NOP	

-	 DWRDL	%2,%30

-	 NOP	

-	 CAM36	%1,%30,4,0

-	 NOP	

-	 CAM72	%1,%30,4,0

-	 NOP	

-	 CAM144	%1,%30,4,0

-	 NOP	

-	 CAM288	%1,%30,4,0

-	 NOP	

-	 CM32AND	%1,%30,%31

-	 NOP	

-	 CM32ANDN	%1,%30,%31

-	 NOP	

-	 CM32OR	%1,%30,%31

-	 NOP	

-	 CM32RA	%1,%30,%31

-	 NOP	

-	 CM32RD	%1,%31

-	 NOP	

-	 CM32RI	%1,%31

-	 NOP	

-	 CM32RS	%1,%30,%31

-	 NOP	

-	 CM32SA	%1,%30,%31

-	 NOP	

-	 CM32SD	%1,%31

-	 NOP	

-	 CM32SI	%1,%31

-	 NOP	

-	 CM32SS	%1,%30,%31

-	 NOP	

-	 CM32XOR	%1,%30,%31

-	 NOP	

-	 CM64CLR	%2,%30

-	 NOP	

-	 CM64RA	%2,%30,%30

-	 NOP	

-	 CM64RD	%2,%30

-	 NOP	

-	 CM64RI	%2,%30

-	 NOP	

-	 CM64RIA2	%2,%30,%30

-	 NOP	

-	 CM64RS	%2,%30,%30

-	 NOP	

-	 CM64SA	%2,%30,%30

-	 NOP	

-	 CM64SD	%2,%30

-	 NOP	

-	 CM64SI	%2,%30

-	 NOP	

-	 CM64SIA2	%2,%30,%30

-	 NOP	

-	 CM64SS	%2,%30,%30

-	 NOP	

-	 CM128RIA2	%2,%30,%30

-	 NOP	

-	 CM128RIA3	%2,%30,%30,3

-	 NOP	

-	 CM128RIA4	%2,%30,%30,4

-	 NOP	

-	 CM128SIA2	%2,%30,%30

-	 NOP	

-	 CM128SIA3	%2,%30,%30,3

-	 NOP	

-	 CM128SIA4	%1,%30,%31,4

-	 NOP	

-	 CM128VSA	%1,%30,%31

-	 NOP	

-	 CRC32	%1,%30,%31

-	 NOP	

-	 CRC32B	%1,%30,%31

-	 NOP	

-	 CHKHDR	%1,%31

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%31,%1

-	 NOP	

-	 TSTOD	%31,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%31

-	 NOP	

-	 DBA	%30

-	 NOP	

-	 DBD	%31,%1

-	 NOP	

-	 DPWT	%31,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test5.d b/gas/testsuite/gas/iq2000/q10test5.d
deleted file mode 100644
index 4485a977e1bd..000000000000
--- a/gas/testsuite/gas/iq2000/q10test5.d
+++ /dev/null
@@ -1,315 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test5
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	03 df f0 20 	add r30,r30,r31
-   4:	00 00 00 00 	nop
-   8:	23 df 00 00 	addi r31,r30,0x0
-   c:	00 00 00 00 	nop
-  10:	27 df 00 00 	addiu r31,r30,0x0
-  14:	00 00 00 00 	nop
-  18:	03 df f0 21 	addu r30,r30,r31
-  1c:	00 00 00 00 	nop
-  20:	03 df f0 29 	ado16 r30,r30,r31
-  24:	00 00 00 00 	nop
-  28:	03 df f0 24 	and r30,r30,r31
-  2c:	00 00 00 00 	nop
-  30:	33 df 00 00 	andi r31,r30,0x0
-  34:	00 00 00 00 	nop
-  38:	b3 df 00 00 	andoi r31,r30,0x0
-  3c:	00 00 00 00 	nop
-  40:	bf df 00 00 	andoui r31,r30,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 1f 00 00 	lui r31,0x0
-  4c:	00 00 00 00 	nop
-  50:	03 df f0 2d 	mrgb r30,r30,r31,0x0
-  54:	00 00 00 00 	nop
-  58:	03 df f0 27 	nor r30,r30,r31
-  5c:	00 00 00 00 	nop
-  60:	03 df f0 25 	or r30,r30,r31
-  64:	00 00 00 00 	nop
-  68:	37 df 00 00 	ori r31,r30,0x0
-  6c:	00 00 00 00 	nop
-  70:	3f df 00 00 	orui r31,r30,0x0
-  74:	00 00 00 00 	nop
-  78:	00 1f f0 00 	sll r30,r31,0x0
-  7c:	00 00 00 00 	nop
-  80:	03 df f0 04 	sllv r30,r31,r30
-  84:	00 00 00 00 	nop
-  88:	03 df f0 2a 	slt r30,r30,r31
-  8c:	00 00 00 00 	nop
-  90:	2b df 00 00 	slti r31,r30,0x0
-  94:	00 00 00 00 	nop
-  98:	2f df 00 00 	sltiu r31,r30,0x0
-  9c:	00 00 00 00 	nop
-  a0:	03 df f0 2b 	sltu r30,r30,r31
-  a4:	00 00 00 00 	nop
-  a8:	00 1f f0 03 	sra r30,r31,0x0
-  ac:	00 00 00 00 	nop
-  b0:	03 df f0 07 	srav r30,r31,r30
-  b4:	00 00 00 00 	nop
-  b8:	00 1f f0 02 	srl r30,r31,0x0
-  bc:	00 00 00 00 	nop
-  c0:	03 df f0 06 	srlv r30,r31,r30
-  c4:	00 00 00 00 	nop
-  c8:	03 df f0 22 	sub r30,r30,r31
-  cc:	00 00 00 00 	nop
-  d0:	03 df f0 23 	subu r30,r30,r31
-  d4:	00 00 00 00 	nop
-  d8:	03 df f0 26 	xor r30,r30,r31
-  dc:	00 00 00 00 	nop
-  e0:	3b df 00 00 	xori r31,r30,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	03 fe f0 05 	srmv r30,r30,r31,0x0
-  f4:	00 00 00 00 	nop
-  f8:	03 fe f0 01 	slmv r30,r30,r31,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 1f f0 00 	ram r30,r31,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	73 c0 ff bd 	bbi r30\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	7b c0 ff bb 	bbin r30\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	77 df ff b9 	bbv r30,r31,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7f df ff b7 	bbvn r30,r31,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f3 c0 ff b5 	bbil r30\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	fb c0 ff b3 	bbinl r30\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f7 df ff b1 	bbvl r30,r31,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	ff df ff af 	bbvnl r30,r31,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	13 df ff ad 	beq r30,r31,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	53 df ff ab 	beql r30,r31,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	07 c1 ff a9 	bgez r30,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	07 d5 ff a7 	bgtzal r30,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	07 d1 ff a5 	bgezal r30,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	07 d7 ff a3 	bgtzall r30,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	07 d3 ff a1 	bgezall r30,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	07 c3 ff 9f 	bgezl r30,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	07 c7 ff 9d 	bgtzl r30,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	07 c5 ff 9b 	bgtz r30,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	07 c4 ff 99 	blez r30,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	07 d4 ff 97 	blezal r30,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	07 c0 ff 95 	bltz r30,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	07 d0 ff 93 	bltzal r30,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	07 c6 ff 91 	blezl r30,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	07 c2 ff 8f 	bltzl r30,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	07 d6 ff 8d 	blezall r30,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	07 d2 ff 8b 	bltzall r30,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	1b df ff 89 	bmb r30,r31,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	5b df ff 87 	bmbl r30,r31,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	63 df ff 85 	bmb0 r30,r31,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	67 df ff 83 	bmb1 r30,r31,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	6b df ff 81 	bmb2 r30,r31,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6f df ff 7f 	bmb3 r30,r31,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	17 df ff 7d 	bne r30,r31,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	57 df ff 7b 	bnel r30,r31,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 1e 00 00 	jal r30,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	03 c0 f0 09 	jalr r30,r30
- 22c:	00 00 00 00 	nop
- 230:	03 c0 00 08 	jr r30
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4f df 00 02 	ctc r30,r31
- 244:	00 00 00 00 	nop
- 248:	4c 1f f0 00 	cfc r30,r31
- 24c:	00 00 00 00 	nop
- 250:	8f df 00 00 	lw r31,0x0\(r30\)
- 254:	00 00 00 00 	nop
- 258:	87 df 00 00 	lh r31,0x0\(r30\)
- 25c:	00 00 00 00 	nop
- 260:	83 df 00 00 	lb r31,0x0\(r30\)
- 264:	00 00 00 00 	nop
- 268:	97 df 00 00 	lhu r31,0x0\(r30\)
- 26c:	00 00 00 00 	nop
- 270:	93 df 00 00 	lbu r31,0x0\(r30\)
- 274:	00 00 00 00 	nop
- 278:	a3 df 00 00 	sb r31,0x0\(r30\)
- 27c:	00 00 00 00 	nop
- 280:	a7 df 00 00 	sh r31,0x0\(r30\)
- 284:	00 00 00 00 	nop
- 288:	af df 00 00 	sw r31,0x0\(r30\)
- 28c:	00 00 00 00 	nop
- 290:	4f fe f0 08 	rba r30,r31,r30
- 294:	00 00 00 00 	nop
- 298:	4f fe f0 0a 	rbar r30,r31,r30
- 29c:	00 00 00 00 	nop
- 2a0:	4f fe f0 09 	rbal r30,r31,r30
- 2a4:	00 00 00 00 	nop
- 2a8:	4f fe f0 10 	wba r30,r31,r30
- 2ac:	00 00 00 00 	nop
- 2b0:	4f fe f0 12 	wbac r30,r31,r30
- 2b4:	00 00 00 00 	nop
- 2b8:	4f fe f0 11 	wbau r30,r31,r30
- 2bc:	00 00 00 00 	nop
- 2c0:	4f fe f2 00 	rbi r30,r31,r30,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4f fe f1 00 	rbir r30,r31,r30,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4f fe f3 00 	rbil r30,r31,r30,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4f fe f6 00 	wbi r30,r31,r30,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4f fe f5 00 	wbic r30,r31,r30,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4f fe f7 00 	wbiu r30,r31,r30,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4f fe f0 28 	pkrla r30,r31,r30
- 2f4:	00 00 00 00 	nop
- 2f8:	4f fe f0 2a 	pkrlah r30,r31,r30
- 2fc:	00 00 00 00 	nop
- 300:	4f fe f0 29 	pkrlau r30,r31,r30
- 304:	00 00 00 00 	nop
- 308:	4b fe f0 00 	pkrli r30,r31,r30,0x0
- 30c:	00 00 00 00 	nop
- 310:	4b fe f2 00 	pkrlih r30,r31,r30,0x0
- 314:	00 00 00 00 	nop
- 318:	4b fe f1 00 	pkrliu r30,r31,r30,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 1e f8 01 	lock r31,r30
- 324:	00 00 00 00 	nop
- 328:	4c 1e f8 03 	unlk r31,r30
- 32c:	00 00 00 00 	nop
- 330:	4f fe f0 06 	swwr r30,r31,r30
- 334:	00 00 00 00 	nop
- 338:	4f fe f0 07 	swwru r30,r31,r30
- 33c:	00 00 00 00 	nop
- 340:	4c 1f f0 04 	swrd r30,r31
- 344:	00 00 00 00 	nop
- 348:	4c 1f f0 05 	swrdl r30,r31
- 34c:	00 00 00 00 	nop
- 350:	4c 1e f0 0c 	dwrd r30,r30
- 354:	00 00 00 00 	nop
- 358:	4c 1e f0 0d 	dwrdl r30,r30
- 35c:	00 00 00 00 	nop
- 360:	4c 1f f4 28 	cam36 r30,r31,0x5,0x0
- 364:	00 00 00 00 	nop
- 368:	4c 1f f4 45 	cam72 r30,r31,0x5,0x0
- 36c:	00 00 00 00 	nop
- 370:	4c 1f f4 85 	cam144 r30,r31,0x5,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 1f f4 c5 	cam288 r30,r31,0x5,0x0
- 37c:	00 00 00 00 	nop
- 380:	4f df f0 ab 	cm32and r30,r30,r31
- 384:	00 00 00 00 	nop
- 388:	4f df f0 a3 	cm32andn r30,r30,r31
- 38c:	00 00 00 00 	nop
- 390:	4f df f0 aa 	cm32or r30,r30,r31
- 394:	00 00 00 00 	nop
- 398:	4f df f0 b0 	cm32ra r30,r30,r31
- 39c:	00 00 00 00 	nop
- 3a0:	4c 1f f0 a1 	cm32rd r30,r31
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 1f f0 a4 	cm32ri r30,r31
- 3ac:	00 00 00 00 	nop
- 3b0:	4f df f0 a0 	cm32rs r30,r30,r31
- 3b4:	00 00 00 00 	nop
- 3b8:	4f df f0 b8 	cm32sa r30,r30,r31
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 1f f0 a9 	cm32sd r30,r31
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 1f f0 ac 	cm32si r30,r31
- 3cc:	00 00 00 00 	nop
- 3d0:	4f df f0 a8 	cm32ss r30,r30,r31
- 3d4:	00 00 00 00 	nop
- 3d8:	4f df f0 a2 	cm32xor r30,r30,r31
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 1e f0 85 	cm64clr r30,r30
- 3e4:	00 00 00 00 	nop
- 3e8:	4f de f0 90 	cm64ra r30,r30,r30
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 1e f0 81 	cm64rd r30,r30
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 1e f0 84 	cm64ri r30,r30
- 3fc:	00 00 00 00 	nop
- 400:	4f de f0 94 	cm64ria2 r30,r30,r30
- 404:	00 00 00 00 	nop
- 408:	4f de f0 80 	cm64rs r30,r30,r30
- 40c:	00 00 00 00 	nop
- 410:	4f de f0 98 	cm64sa r30,r30,r30
- 414:	00 00 00 00 	nop
- 418:	4c 1e f0 89 	cm64sd r30,r30
- 41c:	00 00 00 00 	nop
- 420:	4c 1e f0 8c 	cm64si r30,r30
- 424:	00 00 00 00 	nop
- 428:	4f de f0 9c 	cm64sia2 r30,r30,r30
- 42c:	00 00 00 00 	nop
- 430:	4f de f0 88 	cm64ss r30,r30,r30
- 434:	00 00 00 00 	nop
- 438:	4f de f0 95 	cm128ria2 r30,r30,r30
- 43c:	00 00 00 00 	nop
- 440:	4f de f0 93 	cm128ria3 r30,r30,r30,0x3
- 444:	00 00 00 00 	nop
- 448:	4f de f0 b5 	cm128ria4 r30,r30,r30,0x5
- 44c:	00 00 00 00 	nop
- 450:	4f de f0 9d 	cm128sia2 r30,r30,r30
- 454:	00 00 00 00 	nop
- 458:	4f de f0 9b 	cm128sia3 r30,r30,r30,0x3
- 45c:	00 00 00 00 	nop
- 460:	4f df f0 bd 	cm128sia4 r30,r30,r31,0x5
- 464:	00 00 00 00 	nop
- 468:	4f df f0 a6 	cm128vsa r30,r30,r31
- 46c:	00 00 00 00 	nop
- 470:	4f df f0 14 	crc32 r30,r30,r31
- 474:	00 00 00 00 	nop
- 478:	4f df f0 15 	crc32b r30,r30,r31
- 47c:	00 00 00 00 	nop
- 480:	4f e0 f0 26 	chkhdr r30,r31
- 484:	00 00 00 00 	nop
- 488:	4c 00 f0 24 	avail r30
- 48c:	00 00 00 00 	nop
- 490:	4f c0 f8 25 	free r31,r30
- 494:	00 00 00 00 	nop
- 498:	4f c0 f8 27 	tstod r31,r30
- 49c:	00 00 00 00 	nop
- 4a0:	4c 00 f0 2c 	cmphdr r30
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 1f f0 20 	mcid r30,r31
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 00 f0 22 	dba r30
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 1e f8 21 	dbd r31,r0,r30
- 4bc:	00 00 00 00 	nop
- 4c0:	4f c0 f8 23 	dpwt r31,r30
- 4c4:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test5.s b/gas/testsuite/gas/iq2000/q10test5.s
deleted file mode 100644
index ab80fac90da3..000000000000
--- a/gas/testsuite/gas/iq2000/q10test5.s
+++ /dev/null
@@ -1,308 +0,0 @@
-.global _start

-_start:

-	 ADD	%30,%30,%31

-	 NOP	

-	 ADDI	%31,%30,0

-	 NOP	

-	 ADDIU	%31,%30,0

-	 NOP	

-	 ADDU	%30,%30,%31

-	 NOP	

-	 ADO16	%30,%30,%31

-	 NOP	

-	 AND	%30,%30,%31

-	 NOP	

-	 ANDI	%31,%30,0

-	 NOP	

-	 ANDOI	%31,%30,0

-	 NOP	

-	 ANDOUI	%31,%30,0

-	 NOP	

-	 LUI	%31,0

-	 NOP	

-	 MRGB	%30,%30,%31,0

-	 NOP	

-	 NOR	%30,%30,%31

-	 NOP	

-	 OR	%30,%30,%31

-	 NOP	

-	 ORI	%31,%30,0

-	 NOP	

-	 ORUI	%31,%30,0

-	 NOP	

-	 SLL	%30,%31,0

-	 NOP	

-	 SLLV	%30,%31,%30

-	 NOP	

-	 SLT	%30,%30,%31

-	 NOP	

-	 SLTI	%31,%30,0

-	 NOP	

-	 SLTIU	%31,%30,0

-	 NOP	

-	 SLTU	%30,%30,%31

-	 NOP	

-	 SRA	%30,%31,0

-	 NOP	

-	 SRAV	%30,%31,%30

-	 NOP	

-	 SRL	%30,%31,0

-	 NOP	

-	 SRLV	%30,%31,%30

-	 NOP	

-	 SUB	%30,%30,%31

-	 NOP	

-	 SUBU	%30,%30,%31

-	 NOP	

-	 XOR	%30,%30,%31

-	 NOP	

-	 XORI	%31,%30,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%30,%30,%31,0

-	 NOP	

-	 SLMV	%30,%30,%31,0

-	 NOP	

-	 RAM	%30,%31,0,0,0

-	 NOP	

-	 BBI	%30(0),_start

-	 NOP	

-	 BBIN	%30(0),_start

-	 NOP	

-	 BBV	%30,%31,_start

-	 NOP	

-	 BBVN	%30,%31,_start

-	 NOP	

-	 BBIL	%30(0),_start

-	 NOP	

-	 BBINL	%30(0),_start

-	 NOP	

-	 BBVL	%30,%31,_start

-	 NOP	

-	 BBVNL	%30,%31,_start

-	 NOP	

-	 BEQ	%30,%31,_start

-	 NOP	

-	 BEQL	%30,%31,_start

-	 NOP	

-	 BGEZ	%30,_start

-	 NOP	

-	 BGTZAL	%30,_start

-	 NOP	

-	 BGEZAL	%30,_start

-	 NOP	

-	 BGTZALL	%30,_start

-	 NOP	

-	 BGEZALL	%30,_start

-	 NOP	

-	 BGEZL	%30,_start

-	 NOP	

-	 BGTZL	%30,_start

-	 NOP	

-	 BGTZ	%30,_start

-	 NOP	

-	 BLEZ	%30,_start

-	 NOP	

-	 BLEZAL	%30,_start

-	 NOP	

-	 BLTZ	%30,_start

-	 NOP	

-	 BLTZAL	%30,_start

-	 NOP	

-	 BLEZL	%30,_start

-	 NOP	

-	 BLTZL	%30,_start

-	 NOP	

-	 BLEZALL	%30,_start

-	 NOP	

-	 BLTZALL	%30,_start

-	 NOP	

-	 BMB	%30,%31,_start

-	 NOP	

-	 BMBL	%30,%31,_start

-	 NOP	

-	 BMB0	%30,%31,_start

-	 NOP	

-	 BMB1	%30,%31,_start

-	 NOP	

-	 BMB2	%30,%31,_start

-	 NOP	

-	 BMB3	%30,%31,_start

-	 NOP	

-	 BNE	%30,%31,_start

-	 NOP	

-	 BNEL	%30,%31,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%30,0

-	 NOP	

-	 JALR	%30,%30

-	 NOP	

-	 JR	%30

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%30,%31

-	 NOP	

-	 CFC	%30,%31

-	 NOP	

-	 LW	%31,0(%30)

-	 NOP	

-	 LH	%31,0(%30)

-	 NOP	

-	 LB	%31,0(%30)

-	 NOP	

-	 LHU	%31,0(%30)

-	 NOP	

-	 LBU	%31,0(%30)

-	 NOP	

-	 SB	%31,0(%30)

-	 NOP	

-	 SH	%31,0(%30)

-	 NOP	

-	 SW	%31,0(%30)

-	 NOP	

-	 RBA	%30,%31,%30

-	 NOP	

-	 RBAR	%30,%31,%30

-	 NOP	

-	 RBAL	%30,%31,%30

-	 NOP	

-	 WBA	%30,%31,%30

-	 NOP	

-	 WBAC	%30,%31,%30

-	 NOP	

-	 WBAU	%30,%31,%30

-	 NOP	

-	 RBI	%30,%31,%30,0

-	 NOP	

-	 RBIR	%30,%31,%30,0

-	 NOP	

-	 RBIL	%30,%31,%30,0

-	 NOP	

-	 WBI	%30,%31,%30,0

-	 NOP	

-	 WBIC	%30,%31,%30,0

-	 NOP	

-	 WBIU	%30,%31,%30,0

-	 NOP	

-	 PKRLA	%30,%31,%30

-	 NOP	

-	 PKRLAH	%30,%31,%30

-	 NOP	

-	 PKRLAU	%30,%31,%30

-	 NOP	

-	 PKRLI	%30,%31,%30,0

-	 NOP	

-	 PKRLIH	%30,%31,%30,0

-	 NOP	

-	 PKRLIU	%30,%31,%30,0

-	 NOP	

-	 LOCK	%31,%30

-	 NOP	

-	 UNLK	%31,%30

-	 NOP	

-	 SWWR	%30,%31,%30

-	 NOP	

-	 SWWRU	%30,%31,%30

-	 NOP	

-	 SWRD	%30,%31

-	 NOP	

-	 SWRDL	%30,%31

-	 NOP	

-	 DWRD	%30,%30

-	 NOP	

-	 DWRDL	%30,%30

-	 NOP	

-	 CAM36	%30,%31,5,0

-	 NOP	

-	 CAM72	%30,%31,5,0

-	 NOP	

-	 CAM144	%30,%31,5,0

-	 NOP	

-	 CAM288	%30,%31,5,0

-	 NOP	

-	 CM32AND	%30,%30,%31

-	 NOP	

-	 CM32ANDN	%30,%30,%31

-	 NOP	

-	 CM32OR	%30,%30,%31

-	 NOP	

-	 CM32RA	%30,%30,%31

-	 NOP	

-	 CM32RD	%30,%31

-	 NOP	

-	 CM32RI	%30,%31

-	 NOP	

-	 CM32RS	%30,%30,%31

-	 NOP	

-	 CM32SA	%30,%30,%31

-	 NOP	

-	 CM32SD	%30,%31

-	 NOP	

-	 CM32SI	%30,%31

-	 NOP	

-	 CM32SS	%30,%30,%31

-	 NOP	

-	 CM32XOR	%30,%30,%31

-	 NOP	

-	 CM64CLR	%30,%30

-	 NOP	

-	 CM64RA	%30,%30,%30

-	 NOP	

-	 CM64RD	%30,%30

-	 NOP	

-	 CM64RI	%30,%30

-	 NOP	

-	 CM64RIA2	%30,%30,%30

-	 NOP	

-	 CM64RS	%30,%30,%30

-	 NOP	

-	 CM64SA	%30,%30,%30

-	 NOP	

-	 CM64SD	%30,%30

-	 NOP	

-	 CM64SI	%30,%30

-	 NOP	

-	 CM64SIA2	%30,%30,%30

-	 NOP	

-	 CM64SS	%30,%30,%30

-	 NOP	

-	 CM128RIA2	%30,%30,%30

-	 NOP	

-	 CM128RIA3	%30,%30,%30,3

-	 NOP	

-	 CM128RIA4	%30,%30,%30,5

-	 NOP	

-	 CM128SIA2	%30,%30,%30

-	 NOP	

-	 CM128SIA3	%30,%30,%30,3

-	 NOP	

-	 CM128SIA4	%30,%30,%31,5

-	 NOP	

-	 CM128VSA	%30,%30,%31

-	 NOP	

-	 CRC32	%30,%30,%31

-	 NOP	

-	 CRC32B	%30,%30,%31

-	 NOP	

-	 CHKHDR	%30,%31

-	 NOP	

-	 AVAIL	%30

-	 NOP	

-	 FREE	%31,%30

-	 NOP	

-	 TSTOD	%31,%30

-	 NOP	

-	 CMPHDR	%30

-	 NOP	

-	 MCID	%30,%31

-	 NOP	

-	 DBA	%30

-	 NOP	

-	 DBD	%31,%30

-	 NOP	

-	 DPWT	%31,%30

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test6.d b/gas/testsuite/gas/iq2000/q10test6.d
deleted file mode 100644
index c7e0adf0e63e..000000000000
--- a/gas/testsuite/gas/iq2000/q10test6.d
+++ /dev/null
@@ -1,315 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test6
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	03 de f0 20 	add r30,r30,r30
-   4:	00 00 00 00 	nop
-   8:	23 de 00 00 	addi r30,r30,0x0
-   c:	00 00 00 00 	nop
-  10:	27 de 00 00 	addiu r30,r30,0x0
-  14:	00 00 00 00 	nop
-  18:	03 de f0 21 	addu r30,r30,r30
-  1c:	00 00 00 00 	nop
-  20:	03 de f0 29 	ado16 r30,r30,r30
-  24:	00 00 00 00 	nop
-  28:	03 de f0 24 	and r30,r30,r30
-  2c:	00 00 00 00 	nop
-  30:	33 de 00 00 	andi r30,r30,0x0
-  34:	00 00 00 00 	nop
-  38:	b3 de 00 00 	andoi r30,r30,0x0
-  3c:	00 00 00 00 	nop
-  40:	bf de 00 00 	andoui r30,r30,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 1e 00 00 	lui r30,0x0
-  4c:	00 00 00 00 	nop
-  50:	03 de f0 2d 	mrgb r30,r30,r30,0x0
-  54:	00 00 00 00 	nop
-  58:	03 de f0 27 	nor r30,r30,r30
-  5c:	00 00 00 00 	nop
-  60:	03 de f0 25 	or r30,r30,r30
-  64:	00 00 00 00 	nop
-  68:	37 de 00 00 	ori r30,r30,0x0
-  6c:	00 00 00 00 	nop
-  70:	3f de 00 00 	orui r30,r30,0x0
-  74:	00 00 00 00 	nop
-  78:	00 1e f0 00 	sll r30,r30,0x0
-  7c:	00 00 00 00 	nop
-  80:	03 de f0 04 	sllv r30,r30,r30
-  84:	00 00 00 00 	nop
-  88:	03 de f0 2a 	slt r30,r30,r30
-  8c:	00 00 00 00 	nop
-  90:	2b de 00 00 	slti r30,r30,0x0
-  94:	00 00 00 00 	nop
-  98:	2f de 00 00 	sltiu r30,r30,0x0
-  9c:	00 00 00 00 	nop
-  a0:	03 de f0 2b 	sltu r30,r30,r30
-  a4:	00 00 00 00 	nop
-  a8:	00 1e f0 03 	sra r30,r30,0x0
-  ac:	00 00 00 00 	nop
-  b0:	03 de f0 07 	srav r30,r30,r30
-  b4:	00 00 00 00 	nop
-  b8:	00 1e f0 02 	srl r30,r30,0x0
-  bc:	00 00 00 00 	nop
-  c0:	03 de f0 06 	srlv r30,r30,r30
-  c4:	00 00 00 00 	nop
-  c8:	03 de f0 22 	sub r30,r30,r30
-  cc:	00 00 00 00 	nop
-  d0:	03 de f0 23 	subu r30,r30,r30
-  d4:	00 00 00 00 	nop
-  d8:	03 de f0 26 	xor r30,r30,r30
-  dc:	00 00 00 00 	nop
-  e0:	3b de 00 00 	xori r30,r30,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	03 de f0 05 	srmv r30,r30,r30,0x0
-  f4:	00 00 00 00 	nop
-  f8:	03 de f0 01 	slmv r30,r30,r30,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 1e f0 00 	ram r30,r30,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	73 c0 ff bd 	bbi r30\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	7b c0 ff bb 	bbin r30\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	77 de ff b9 	bbv r30,r30,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7f de ff b7 	bbvn r30,r30,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f3 c0 ff b5 	bbil r30\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	fb c0 ff b3 	bbinl r30\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f7 de ff b1 	bbvl r30,r30,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	ff de ff af 	bbvnl r30,r30,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	13 de ff ad 	beq r30,r30,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	53 de ff ab 	beql r30,r30,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	07 c1 ff a9 	bgez r30,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	07 d5 ff a7 	bgtzal r30,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	07 d1 ff a5 	bgezal r30,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	07 d7 ff a3 	bgtzall r30,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	07 d3 ff a1 	bgezall r30,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	07 c3 ff 9f 	bgezl r30,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	07 c7 ff 9d 	bgtzl r30,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	07 c5 ff 9b 	bgtz r30,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	07 c4 ff 99 	blez r30,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	07 d4 ff 97 	blezal r30,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	07 c0 ff 95 	bltz r30,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	07 d0 ff 93 	bltzal r30,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	07 c6 ff 91 	blezl r30,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	07 c2 ff 8f 	bltzl r30,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	07 d6 ff 8d 	blezall r30,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	07 d2 ff 8b 	bltzall r30,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	1b de ff 89 	bmb r30,r30,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	5b de ff 87 	bmbl r30,r30,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	63 de ff 85 	bmb0 r30,r30,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	67 de ff 83 	bmb1 r30,r30,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	6b de ff 81 	bmb2 r30,r30,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6f de ff 7f 	bmb3 r30,r30,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	17 de ff 7d 	bne r30,r30,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	57 de ff 7b 	bnel r30,r30,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 1e 00 00 	jal r30,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	03 c0 f0 09 	jalr r30,r30
- 22c:	00 00 00 00 	nop
- 230:	03 c0 00 08 	jr r30
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4f de 00 02 	ctc r30,r30
- 244:	00 00 00 00 	nop
- 248:	4c 1e f0 00 	cfc r30,r30
- 24c:	00 00 00 00 	nop
- 250:	8f de 00 00 	lw r30,0x0\(r30\)
- 254:	00 00 00 00 	nop
- 258:	87 de 00 00 	lh r30,0x0\(r30\)
- 25c:	00 00 00 00 	nop
- 260:	83 de 00 00 	lb r30,0x0\(r30\)
- 264:	00 00 00 00 	nop
- 268:	97 de 00 00 	lhu r30,0x0\(r30\)
- 26c:	00 00 00 00 	nop
- 270:	93 de 00 00 	lbu r30,0x0\(r30\)
- 274:	00 00 00 00 	nop
- 278:	a3 de 00 00 	sb r30,0x0\(r30\)
- 27c:	00 00 00 00 	nop
- 280:	a7 de 00 00 	sh r30,0x0\(r30\)
- 284:	00 00 00 00 	nop
- 288:	af de 00 00 	sw r30,0x0\(r30\)
- 28c:	00 00 00 00 	nop
- 290:	4f de f0 08 	rba r30,r30,r30
- 294:	00 00 00 00 	nop
- 298:	4f de f0 0a 	rbar r30,r30,r30
- 29c:	00 00 00 00 	nop
- 2a0:	4f de f0 09 	rbal r30,r30,r30
- 2a4:	00 00 00 00 	nop
- 2a8:	4f de f0 10 	wba r30,r30,r30
- 2ac:	00 00 00 00 	nop
- 2b0:	4f de f0 12 	wbac r30,r30,r30
- 2b4:	00 00 00 00 	nop
- 2b8:	4f de f0 11 	wbau r30,r30,r30
- 2bc:	00 00 00 00 	nop
- 2c0:	4f de f2 00 	rbi r30,r30,r30,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4f de f1 00 	rbir r30,r30,r30,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4f de f3 00 	rbil r30,r30,r30,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4f de f6 00 	wbi r30,r30,r30,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4f de f5 00 	wbic r30,r30,r30,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4f de f7 00 	wbiu r30,r30,r30,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4f de f0 28 	pkrla r30,r30,r30
- 2f4:	00 00 00 00 	nop
- 2f8:	4f de f0 2a 	pkrlah r30,r30,r30
- 2fc:	00 00 00 00 	nop
- 300:	4f de f0 29 	pkrlau r30,r30,r30
- 304:	00 00 00 00 	nop
- 308:	4b de f0 00 	pkrli r30,r30,r30,0x0
- 30c:	00 00 00 00 	nop
- 310:	4b de f2 00 	pkrlih r30,r30,r30,0x0
- 314:	00 00 00 00 	nop
- 318:	4b de f1 00 	pkrliu r30,r30,r30,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 1e f0 01 	lock r30,r30
- 324:	00 00 00 00 	nop
- 328:	4c 1e f0 03 	unlk r30,r30
- 32c:	00 00 00 00 	nop
- 330:	4f de f0 06 	swwr r30,r30,r30
- 334:	00 00 00 00 	nop
- 338:	4f de f0 07 	swwru r30,r30,r30
- 33c:	00 00 00 00 	nop
- 340:	4c 1e f0 04 	swrd r30,r30
- 344:	00 00 00 00 	nop
- 348:	4c 1e f0 05 	swrdl r30,r30
- 34c:	00 00 00 00 	nop
- 350:	4c 1e f0 0c 	dwrd r30,r30
- 354:	00 00 00 00 	nop
- 358:	4c 1e f0 0d 	dwrdl r30,r30
- 35c:	00 00 00 00 	nop
- 360:	4c 1e f4 30 	cam36 r30,r30,0x6,0x0
- 364:	00 00 00 00 	nop
- 368:	4c 1e f4 46 	cam72 r30,r30,0x6,0x0
- 36c:	00 00 00 00 	nop
- 370:	4c 1e f4 86 	cam144 r30,r30,0x6,0x0
- 374:	00 00 00 00 	nop
- 378:	4c 1e f4 c6 	cam288 r30,r30,0x6,0x0
- 37c:	00 00 00 00 	nop
- 380:	4f de f0 ab 	cm32and r30,r30,r30
- 384:	00 00 00 00 	nop
- 388:	4f de f0 a3 	cm32andn r30,r30,r30
- 38c:	00 00 00 00 	nop
- 390:	4f de f0 aa 	cm32or r30,r30,r30
- 394:	00 00 00 00 	nop
- 398:	4f de f0 b0 	cm32ra r30,r30,r30
- 39c:	00 00 00 00 	nop
- 3a0:	4c 1e f0 a1 	cm32rd r30,r30
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 1e f0 a4 	cm32ri r30,r30
- 3ac:	00 00 00 00 	nop
- 3b0:	4f de f0 a0 	cm32rs r30,r30,r30
- 3b4:	00 00 00 00 	nop
- 3b8:	4f de f0 b8 	cm32sa r30,r30,r30
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 1e f0 a9 	cm32sd r30,r30
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 1e f0 ac 	cm32si r30,r30
- 3cc:	00 00 00 00 	nop
- 3d0:	4f de f0 a8 	cm32ss r30,r30,r30
- 3d4:	00 00 00 00 	nop
- 3d8:	4f de f0 a2 	cm32xor r30,r30,r30
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 1e f0 85 	cm64clr r30,r30
- 3e4:	00 00 00 00 	nop
- 3e8:	4f de f0 90 	cm64ra r30,r30,r30
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 1e f0 81 	cm64rd r30,r30
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 1e f0 84 	cm64ri r30,r30
- 3fc:	00 00 00 00 	nop
- 400:	4f de f0 94 	cm64ria2 r30,r30,r30
- 404:	00 00 00 00 	nop
- 408:	4f de f0 80 	cm64rs r30,r30,r30
- 40c:	00 00 00 00 	nop
- 410:	4f de f0 98 	cm64sa r30,r30,r30
- 414:	00 00 00 00 	nop
- 418:	4c 1e f0 89 	cm64sd r30,r30
- 41c:	00 00 00 00 	nop
- 420:	4c 1e f0 8c 	cm64si r30,r30
- 424:	00 00 00 00 	nop
- 428:	4f de f0 9c 	cm64sia2 r30,r30,r30
- 42c:	00 00 00 00 	nop
- 430:	4f de f0 88 	cm64ss r30,r30,r30
- 434:	00 00 00 00 	nop
- 438:	4f de f0 95 	cm128ria2 r30,r30,r30
- 43c:	00 00 00 00 	nop
- 440:	4f de f0 93 	cm128ria3 r30,r30,r30,0x3
- 444:	00 00 00 00 	nop
- 448:	4f de f0 b6 	cm128ria4 r30,r30,r30,0x6
- 44c:	00 00 00 00 	nop
- 450:	4f de f0 9d 	cm128sia2 r30,r30,r30
- 454:	00 00 00 00 	nop
- 458:	4f de f0 9b 	cm128sia3 r30,r30,r30,0x3
- 45c:	00 00 00 00 	nop
- 460:	4f de f0 be 	cm128sia4 r30,r30,r30,0x6
- 464:	00 00 00 00 	nop
- 468:	4f de f0 a6 	cm128vsa r30,r30,r30
- 46c:	00 00 00 00 	nop
- 470:	4f de f0 14 	crc32 r30,r30,r30
- 474:	00 00 00 00 	nop
- 478:	4f de f0 15 	crc32b r30,r30,r30
- 47c:	00 00 00 00 	nop
- 480:	4f c0 f0 26 	chkhdr r30,r30
- 484:	00 00 00 00 	nop
- 488:	4c 00 f0 24 	avail r30
- 48c:	00 00 00 00 	nop
- 490:	4f c0 f0 25 	free r30,r30
- 494:	00 00 00 00 	nop
- 498:	4f c0 f0 27 	tstod r30,r30
- 49c:	00 00 00 00 	nop
- 4a0:	4c 00 f0 2c 	cmphdr r30
- 4a4:	00 00 00 00 	nop
- 4a8:	4c 1e f0 20 	mcid r30,r30
- 4ac:	00 00 00 00 	nop
- 4b0:	4c 00 f0 22 	dba r30
- 4b4:	00 00 00 00 	nop
- 4b8:	4c 1e f0 21 	dbd r30,r0,r30
- 4bc:	00 00 00 00 	nop
- 4c0:	4f c0 f0 23 	dpwt r30,r30
- 4c4:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test6.s b/gas/testsuite/gas/iq2000/q10test6.s
deleted file mode 100644
index c6f58acc104d..000000000000
--- a/gas/testsuite/gas/iq2000/q10test6.s
+++ /dev/null
@@ -1,308 +0,0 @@
-.global _start

-_start:

-	 ADD	%30,%30,%30

-	 NOP	

-	 ADDI	%30,%30,0

-	 NOP	

-	 ADDIU	%30,%30,0

-	 NOP	

-	 ADDU	%30,%30,%30

-	 NOP	

-	 ADO16	%30,%30,%30

-	 NOP	

-	 AND	%30,%30,%30

-	 NOP	

-	 ANDI	%30,%30,0

-	 NOP	

-	 ANDOI	%30,%30,0

-	 NOP	

-	 ANDOUI	%30,%30,0

-	 NOP	

-	 LUI	%30,0

-	 NOP	

-	 MRGB	%30,%30,%30,0

-	 NOP	

-	 NOR	%30,%30,%30

-	 NOP	

-	 OR	%30,%30,%30

-	 NOP	

-	 ORI	%30,%30,0

-	 NOP	

-	 ORUI	%30,%30,0

-	 NOP	

-	 SLL	%30,%30,0

-	 NOP	

-	 SLLV	%30,%30,%30

-	 NOP	

-	 SLT	%30,%30,%30

-	 NOP	

-	 SLTI	%30,%30,0

-	 NOP	

-	 SLTIU	%30,%30,0

-	 NOP	

-	 SLTU	%30,%30,%30

-	 NOP	

-	 SRA	%30,%30,0

-	 NOP	

-	 SRAV	%30,%30,%30

-	 NOP	

-	 SRL	%30,%30,0

-	 NOP	

-	 SRLV	%30,%30,%30

-	 NOP	

-	 SUB	%30,%30,%30

-	 NOP	

-	 SUBU	%30,%30,%30

-	 NOP	

-	 XOR	%30,%30,%30

-	 NOP	

-	 XORI	%30,%30,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%30,%30,%30,0

-	 NOP	

-	 SLMV	%30,%30,%30,0

-	 NOP	

-	 RAM	%30,%30,0,0,0

-	 NOP	

-	 BBI	%30(0),_start

-	 NOP	

-	 BBIN	%30(0),_start

-	 NOP	

-	 BBV	%30,%30,_start

-	 NOP	

-	 BBVN	%30,%30,_start

-	 NOP	

-	 BBIL	%30(0),_start

-	 NOP	

-	 BBINL	%30(0),_start

-	 NOP	

-	 BBVL	%30,%30,_start

-	 NOP	

-	 BBVNL	%30,%30,_start

-	 NOP	

-	 BEQ	%30,%30,_start

-	 NOP	

-	 BEQL	%30,%30,_start

-	 NOP	

-	 BGEZ	%30,_start

-	 NOP	

-	 BGTZAL	%30,_start

-	 NOP	

-	 BGEZAL	%30,_start

-	 NOP	

-	 BGTZALL	%30,_start

-	 NOP	

-	 BGEZALL	%30,_start

-	 NOP	

-	 BGEZL	%30,_start

-	 NOP	

-	 BGTZL	%30,_start

-	 NOP	

-	 BGTZ	%30,_start

-	 NOP	

-	 BLEZ	%30,_start

-	 NOP	

-	 BLEZAL	%30,_start

-	 NOP	

-	 BLTZ	%30,_start

-	 NOP	

-	 BLTZAL	%30,_start

-	 NOP	

-	 BLEZL	%30,_start

-	 NOP	

-	 BLTZL	%30,_start

-	 NOP	

-	 BLEZALL	%30,_start

-	 NOP	

-	 BLTZALL	%30,_start

-	 NOP	

-	 BMB	%30,%30,_start

-	 NOP	

-	 BMBL	%30,%30,_start

-	 NOP	

-	 BMB0	%30,%30,_start

-	 NOP	

-	 BMB1	%30,%30,_start

-	 NOP	

-	 BMB2	%30,%30,_start

-	 NOP	

-	 BMB3	%30,%30,_start

-	 NOP	

-	 BNE	%30,%30,_start

-	 NOP	

-	 BNEL	%30,%30,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%30,0

-	 NOP	

-	 JALR	%30,%30

-	 NOP	

-	 JR	%30

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%30,%30

-	 NOP	

-	 CFC	%30,%30

-	 NOP	

-	 LW	%30,0(%30)

-	 NOP	

-	 LH	%30,0(%30)

-	 NOP	

-	 LB	%30,0(%30)

-	 NOP	

-	 LHU	%30,0(%30)

-	 NOP	

-	 LBU	%30,0(%30)

-	 NOP	

-	 SB	%30,0(%30)

-	 NOP	

-	 SH	%30,0(%30)

-	 NOP	

-	 SW	%30,0(%30)

-	 NOP	

-	 RBA	%30,%30,%30

-	 NOP	

-	 RBAR	%30,%30,%30

-	 NOP	

-	 RBAL	%30,%30,%30

-	 NOP	

-	 WBA	%30,%30,%30

-	 NOP	

-	 WBAC	%30,%30,%30

-	 NOP	

-	 WBAU	%30,%30,%30

-	 NOP	

-	 RBI	%30,%30,%30,0

-	 NOP	

-	 RBIR	%30,%30,%30,0

-	 NOP	

-	 RBIL	%30,%30,%30,0

-	 NOP	

-	 WBI	%30,%30,%30,0

-	 NOP	

-	 WBIC	%30,%30,%30,0

-	 NOP	

-	 WBIU	%30,%30,%30,0

-	 NOP	

-	 PKRLA	%30,%30,%30

-	 NOP	

-	 PKRLAH	%30,%30,%30

-	 NOP	

-	 PKRLAU	%30,%30,%30

-	 NOP	

-	 PKRLI	%30,%30,%30,0

-	 NOP	

-	 PKRLIH	%30,%30,%30,0

-	 NOP	

-	 PKRLIU	%30,%30,%30,0

-	 NOP	

-	 LOCK	%30,%30

-	 NOP	

-	 UNLK	%30,%30

-	 NOP	

-	 SWWR	%30,%30,%30

-	 NOP	

-	 SWWRU	%30,%30,%30

-	 NOP	

-	 SWRD	%30,%30

-	 NOP	

-	 SWRDL	%30,%30

-	 NOP	

-	 DWRD	%30,%30

-	 NOP	

-	 DWRDL	%30,%30

-	 NOP	

-	 CAM36	%30,%30,6,0

-	 NOP	

-	 CAM72	%30,%30,6,0

-	 NOP	

-	 CAM144	%30,%30,6,0

-	 NOP	

-	 CAM288	%30,%30,6,0

-	 NOP	

-	 CM32AND	%30,%30,%30

-	 NOP	

-	 CM32ANDN	%30,%30,%30

-	 NOP	

-	 CM32OR	%30,%30,%30

-	 NOP	

-	 CM32RA	%30,%30,%30

-	 NOP	

-	 CM32RD	%30,%30

-	 NOP	

-	 CM32RI	%30,%30

-	 NOP	

-	 CM32RS	%30,%30,%30

-	 NOP	

-	 CM32SA	%30,%30,%30

-	 NOP	

-	 CM32SD	%30,%30

-	 NOP	

-	 CM32SI	%30,%30

-	 NOP	

-	 CM32SS	%30,%30,%30

-	 NOP	

-	 CM32XOR	%30,%30,%30

-	 NOP	

-	 CM64CLR	%30,%30

-	 NOP	

-	 CM64RA	%30,%30,%30

-	 NOP	

-	 CM64RD	%30,%30

-	 NOP	

-	 CM64RI	%30,%30

-	 NOP	

-	 CM64RIA2	%30,%30,%30

-	 NOP	

-	 CM64RS	%30,%30,%30

-	 NOP	

-	 CM64SA	%30,%30,%30

-	 NOP	

-	 CM64SD	%30,%30

-	 NOP	

-	 CM64SI	%30,%30

-	 NOP	

-	 CM64SIA2	%30,%30,%30

-	 NOP	

-	 CM64SS	%30,%30,%30

-	 NOP	

-	 CM128RIA2	%30,%30,%30

-	 NOP	

-	 CM128RIA3	%30,%30,%30,3

-	 NOP	

-	 CM128RIA4	%30,%30,%30,6

-	 NOP	

-	 CM128SIA2	%30,%30,%30

-	 NOP	

-	 CM128SIA3	%30,%30,%30,3

-	 NOP	

-	 CM128SIA4	%30,%30,%30,6

-	 NOP	

-	 CM128VSA	%30,%30,%30

-	 NOP	

-	 CRC32	%30,%30,%30

-	 NOP	

-	 CRC32B	%30,%30,%30

-	 NOP	

-	 CHKHDR	%30,%30

-	 NOP	

-	 AVAIL	%30

-	 NOP	

-	 FREE	%30,%30

-	 NOP	

-	 TSTOD	%30,%30

-	 NOP	

-	 CMPHDR	%30

-	 NOP	

-	 MCID	%30,%30

-	 NOP	

-	 DBA	%30

-	 NOP	

-	 DBD	%30,%30

-	 NOP	

-	 DPWT	%30,%30

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test7.d b/gas/testsuite/gas/iq2000/q10test7.d
deleted file mode 100644
index 2bf380ca7e1b..000000000000
--- a/gas/testsuite/gas/iq2000/q10test7.d
+++ /dev/null
@@ -1,301 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test7
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 08 	addi r1,r1,0x8
-   c:	00 00 00 00 	nop
-  10:	24 21 00 08 	addiu r1,r1,0x8
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 08 	andi r1,r1,0x8
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 08 	andoi r1,r1,0x8
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 08 	andoui r1,r1,0x8
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 08 	lui r1,0x8
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 2d 	mrgb r1,r1,r1,0x0
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 08 	ori r1,r1,0x8
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 08 	orui r1,r1,0x8
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 08 	slti r1,r1,0x8
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 08 	sltiu r1,r1,0x8
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 08 	xori r1,r1,0x8
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 01 08 00 	ram r1,r1,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	70 21 00 02 	bbi r1\(0x1\),114 <_start\+0x114>
- 10c:	00 00 00 00 	nop
- 110:	78 21 00 02 	bbin r1\(0x1\),11c <_start\+0x11c>
- 114:	00 00 00 00 	nop
- 118:	74 21 00 02 	bbv r1,r1,124 <_start\+0x124>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 00 02 	bbvn r1,r1,12c <_start\+0x12c>
- 124:	00 00 00 00 	nop
- 128:	f0 21 00 02 	bbil r1\(0x1\),134 <_start\+0x134>
- 12c:	00 00 00 00 	nop
- 130:	f8 21 00 02 	bbinl r1\(0x1\),13c <_start\+0x13c>
- 134:	00 00 00 00 	nop
- 138:	f4 21 00 02 	bbvl r1,r1,144 <_start\+0x144>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 00 02 	bbvnl r1,r1,14c <_start\+0x14c>
- 144:	00 00 00 00 	nop
- 148:	10 21 00 02 	beq r1,r1,154 <_start\+0x154>
- 14c:	00 00 00 00 	nop
- 150:	50 21 00 02 	beql r1,r1,15c <_start\+0x15c>
- 154:	00 00 00 00 	nop
- 158:	04 21 00 02 	bgez r1,164 <_start\+0x164>
- 15c:	00 00 00 00 	nop
- 160:	04 35 00 02 	bgtzal r1,16c <_start\+0x16c>
- 164:	00 00 00 00 	nop
- 168:	04 31 00 02 	bgezal r1,174 <_start\+0x174>
- 16c:	00 00 00 00 	nop
- 170:	04 37 00 02 	bgtzall r1,17c <_start\+0x17c>
- 174:	00 00 00 00 	nop
- 178:	04 33 00 02 	bgezall r1,184 <_start\+0x184>
- 17c:	00 00 00 00 	nop
- 180:	04 23 00 02 	bgezl r1,18c <_start\+0x18c>
- 184:	00 00 00 00 	nop
- 188:	04 27 00 02 	bgtzl r1,194 <_start\+0x194>
- 18c:	00 00 00 00 	nop
- 190:	04 25 00 02 	bgtz r1,19c <_start\+0x19c>
- 194:	00 00 00 00 	nop
- 198:	04 24 00 02 	blez r1,1a4 <_start\+0x1a4>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 00 02 	blezal r1,1ac <_start\+0x1ac>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 00 02 	bltz r1,1b4 <_start\+0x1b4>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 00 02 	bltzal r1,1bc <_start\+0x1bc>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 00 02 	blezl r1,1c4 <_start\+0x1c4>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 00 02 	bltzl r1,1cc <_start\+0x1cc>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 00 02 	blezall r1,1d4 <_start\+0x1d4>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 00 02 	bltzall r1,1dc <_start\+0x1dc>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 00 02 	bmb r1,r1,1e4 <_start\+0x1e4>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 00 02 	bmbl r1,r1,1ec <_start\+0x1ec>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 00 02 	bmb0 r1,r1,1f4 <_start\+0x1f4>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 00 02 	bmb1 r1,r1,1fc <_start\+0x1fc>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 00 02 	bmb2 r1,r1,204 <_start\+0x204>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 00 02 	bmb3 r1,r1,20c <_start\+0x20c>
- 204:	00 00 00 00 	nop
- 208:	14 21 00 02 	bne r1,r1,214 <_start\+0x214>
- 20c:	00 00 00 00 	nop
- 210:	54 21 00 02 	bnel r1,r1,21c <_start\+0x21c>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 02 	j 8 <_start\+0x8>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 02 	jal r1,8 <_start\+0x8>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 08 	lw r1,0x8\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 08 	lh r1,0x8\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 08 	lb r1,0x8\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 08 	lhu r1,0x8\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 08 	lbu r1,0x8\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 08 	sb r1,0x8\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 08 	sh r1,0x8\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 08 	sw r1,0x8\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 00 	rbi r1,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 00 	rbir r1,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 00 	rbil r1,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 00 	wbi r1,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 00 	wbic r1,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 00 	wbiu r1,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2a 	pkrlah r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 29 	pkrlau r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 08 00 	pkrli r1,r1,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	48 21 0a 00 	pkrlih r1,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 09 00 	pkrliu r1,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 08 06 	swwr r1,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 08 07 	swwru r1,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 02 10 0c 	dwrd r2,r2
- 354:	00 00 00 00 	nop
- 358:	4c 02 10 0d 	dwrdl r2,r2
- 35c:	00 00 00 00 	nop
- 360:	4c 21 08 ab 	cm32and r1,r1,r1
- 364:	00 00 00 00 	nop
- 368:	4c 21 08 a3 	cm32andn r1,r1,r1
- 36c:	00 00 00 00 	nop
- 370:	4c 21 08 aa 	cm32or r1,r1,r1
- 374:	00 00 00 00 	nop
- 378:	4c 21 08 b0 	cm32ra r1,r1,r1
- 37c:	00 00 00 00 	nop
- 380:	4c 01 08 a1 	cm32rd r1,r1
- 384:	00 00 00 00 	nop
- 388:	4c 01 08 a4 	cm32ri r1,r1
- 38c:	00 00 00 00 	nop
- 390:	4c 21 08 a0 	cm32rs r1,r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 21 08 b8 	cm32sa r1,r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 01 08 a9 	cm32sd r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 01 08 ac 	cm32si r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 21 08 a8 	cm32ss r1,r1,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 21 08 a2 	cm32xor r1,r1,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 02 10 85 	cm64clr r2,r2
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 42 10 90 	cm64ra r2,r2,r2
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 02 10 81 	cm64rd r2,r2
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 02 10 84 	cm64ri r2,r2
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 42 10 94 	cm64ria2 r2,r2,r2
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 42 10 80 	cm64rs r2,r2,r2
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 42 10 98 	cm64sa r2,r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 02 10 89 	cm64sd r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 02 10 8c 	cm64si r2,r2
- 404:	00 00 00 00 	nop
- 408:	4c 42 10 9c 	cm64sia2 r2,r2,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 42 10 88 	cm64ss r2,r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 10 95 	cm128ria2 r2,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 42 10 b7 	cm128ria4 r2,r2,r2,0x7
- 424:	00 00 00 00 	nop
- 428:	4c 42 10 9d 	cm128sia2 r2,r2,r2
- 42c:	00 00 00 00 	nop
- 430:	4c 21 08 bf 	cm128sia4 r1,r1,r1,0x7
- 434:	00 00 00 00 	nop
- 438:	4c 21 08 a6 	cm128vsa r1,r1,r1
- 43c:	00 00 00 00 	nop
- 440:	4c 21 08 14 	crc32 r1,r1,r1
- 444:	00 00 00 00 	nop
- 448:	4c 21 08 15 	crc32b r1,r1,r1
- 44c:	00 00 00 00 	nop
- 450:	4c 20 08 26 	chkhdr r1,r1
- 454:	00 00 00 00 	nop
- 458:	4c 00 08 24 	avail r1
- 45c:	00 00 00 00 	nop
- 460:	4c 20 08 25 	free r1,r1
- 464:	00 00 00 00 	nop
- 468:	4c 00 08 2c 	cmphdr r1
- 46c:	00 00 00 00 	nop
- 470:	4c 01 08 20 	mcid r1,r1
- 474:	00 00 00 00 	nop
- 478:	4c 00 08 22 	dba r1
- 47c:	00 00 00 00 	nop
- 480:	4c 01 08 21 	dbd r1,r0,r1
- 484:	00 00 00 00 	nop
- 488:	4c 20 08 23 	dpwt r1,r1
- 48c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test7.s b/gas/testsuite/gas/iq2000/q10test7.s
deleted file mode 100644
index 12b1c99535a5..000000000000
--- a/gas/testsuite/gas/iq2000/q10test7.s
+++ /dev/null
@@ -1,294 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,8

-	 NOP	

-	 ADDIU	%1,%1,8

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,8

-	 NOP	

-	 ANDOI	%1,%1,8

-	 NOP	

-	 ANDOUI	%1,%1,8

-	 NOP	

-	 LUI	%1,8

-	 NOP	

-	 MRGB	%1,%1,%1,0

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,8

-	 NOP	

-	 ORUI	%1,%1,8

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,8

-	 NOP	

-	 SLTIU	%1,%1,8

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,8

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,0,0

-	 NOP	

-	 BBI	%1(1),8

-	 NOP	

-	 BBIN	%1(1),8

-	 NOP	

-	 BBV	%1,%1,8

-	 NOP	

-	 BBVN	%1,%1,8

-	 NOP	

-	 BBIL	%1(1),8

-	 NOP	

-	 BBINL	%1(1),8

-	 NOP	

-	 BBVL	%1,%1,8

-	 NOP	

-	 BBVNL	%1,%1,8

-	 NOP	

-	 BEQ	%1,%1,8

-	 NOP	

-	 BEQL	%1,%1,8

-	 NOP	

-	 BGEZ	%1,8

-	 NOP	

-	 BGTZAL	%1,8

-	 NOP	

-	 BGEZAL	%1,8

-	 NOP	

-	 BGTZALL	%1,8

-	 NOP	

-	 BGEZALL	%1,8

-	 NOP	

-	 BGEZL	%1,8

-	 NOP	

-	 BGTZL	%1,8

-	 NOP	

-	 BGTZ	%1,8

-	 NOP	

-	 BLEZ	%1,8

-	 NOP	

-	 BLEZAL	%1,8

-	 NOP	

-	 BLTZ	%1,8

-	 NOP	

-	 BLTZAL	%1,8

-	 NOP	

-	 BLEZL	%1,8

-	 NOP	

-	 BLTZL	%1,8

-	 NOP	

-	 BLEZALL	%1,8

-	 NOP	

-	 BLTZALL	%1,8

-	 NOP	

-	 BMB	%1,%1,8

-	 NOP	

-	 BMBL	%1,%1,8

-	 NOP	

-	 BMB0	%1,%1,8

-	 NOP	

-	 BMB1	%1,%1,8

-	 NOP	

-	 BMB2	%1,%1,8

-	 NOP	

-	 BMB3	%1,%1,8

-	 NOP	

-	 BNE	%1,%1,8

-	 NOP	

-	 BNEL	%1,%1,8

-	 NOP	

-	 J	8

-	 NOP	

-	 JAL	%1,8

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,8(%1)

-	 NOP	

-	 LH	%1,8(%1)

-	 NOP	

-	 LB	%1,8(%1)

-	 NOP	

-	 LHU	%1,8(%1)

-	 NOP	

-	 LBU	%1,8(%1)

-	 NOP	

-	 SB	%1,8(%1)

-	 NOP	

-	 SH	%1,8(%1)

-	 NOP	

-	 SW	%1,8(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,0

-	 NOP	

-	 RBIR	%1,%1,%1,0

-	 NOP	

-	 RBIL	%1,%1,%1,0

-	 NOP	

-	 WBI	%1,%1,%1,0

-	 NOP	

-	 WBIC	%1,%1,%1,0

-	 NOP	

-	 WBIU	%1,%1,%1,0

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,0

-	 NOP	

-	 PKRLIH	%1,%1,%1,0

-	 NOP	

-	 PKRLIU	%1,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 DWRD	%2,%2

-	 NOP	

-	 DWRDL	%2,%2

-	 NOP	

-	 CM32AND	%1,%1,%1

-	 NOP	

-	 CM32ANDN	%1,%1,%1

-	 NOP	

-	 CM32OR	%1,%1,%1

-	 NOP	

-	 CM32RA	%1,%1,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%1,%1

-	 NOP	

-	 CM32SA	%1,%1,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%1,%1

-	 NOP	

-	 CM32XOR	%1,%1,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%2,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%2,%2

-	 NOP	

-	 CM64RS	%2,%2,%2

-	 NOP	

-	 CM64SA	%2,%2,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%2,%2

-	 NOP	

-	 CM64SS	%2,%2,%2

-	 NOP	

-	 CM128RIA2	%2,%2,%2

-	 NOP	

-	 CM128RIA4	%2,%2,%2,7

-	 NOP	

-	 CM128SIA2	%2,%2,%2

-	 NOP	

-	 CM128SIA4	%1,%1,%1,7

-	 NOP	

-	 CM128VSA	%1,%1,%1

-	 NOP	

-	 CRC32	%1,%1,%1

-	 NOP	

-	 CRC32B	%1,%1,%1

-	 NOP	

-	 CHKHDR	%1,%1

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%1

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test8.d b/gas/testsuite/gas/iq2000/q10test8.d
deleted file mode 100644
index 9b18dde51d53..000000000000
--- a/gas/testsuite/gas/iq2000/q10test8.d
+++ /dev/null
@@ -1,327 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test8
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 ff f8 	addi r1,r1,0xfff8
-   c:	00 00 00 00 	nop
-  10:	24 21 ff f8 	addiu r1,r1,0xfff8
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 ff f8 	andi r1,r1,0xfff8
-  34:	00 00 00 00 	nop
-  38:	b0 21 ff f8 	andoi r1,r1,0xfff8
-  3c:	00 00 00 00 	nop
-  40:	bc 21 ff f8 	andoui r1,r1,0xfff8
-  44:	00 00 00 00 	nop
-  48:	3c 01 ff f8 	lui r1,0xfff8
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 2d 	mrgb r1,r1,r1,0x0
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 ff f8 	ori r1,r1,0xfff8
-  6c:	00 00 00 00 	nop
-  70:	3c 21 ff f8 	orui r1,r1,0xfff8
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 ff f8 	slti r1,r1,0xfff8
-  94:	00 00 00 00 	nop
-  98:	2c 21 ff f8 	sltiu r1,r1,0xfff8
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 ff f8 	xori r1,r1,0xfff8
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 01 08 00 	ram r1,r1,0x0,0x0,0x0
- 104:	00 00 00 00 	nop
- 108:	70 3f 00 00 	bbi r1\(0x1f\),10c <_start\+0x10c>
-			108: R_IQ2000_PC16	_startxfff8
- 10c:	00 00 00 00 	nop
- 110:	78 3f 00 00 	bbin r1\(0x1f\),114 <_start\+0x114>
-			110: R_IQ2000_PC16	_startxfff8
- 114:	00 00 00 00 	nop
- 118:	74 21 00 00 	bbv r1,r1,11c <_start\+0x11c>
-			118: R_IQ2000_PC16	_startxfff8
- 11c:	00 00 00 00 	nop
- 120:	7c 21 00 00 	bbvn r1,r1,124 <_start\+0x124>
-			120: R_IQ2000_PC16	_startxfff8
- 124:	00 00 00 00 	nop
- 128:	f0 3f 00 00 	bbil r1\(0x1f\),12c <_start\+0x12c>
-			128: R_IQ2000_PC16	_startxfff8
- 12c:	00 00 00 00 	nop
- 130:	f8 3f 00 00 	bbinl r1\(0x1f\),134 <_start\+0x134>
-			130: R_IQ2000_PC16	_startxfff8
- 134:	00 00 00 00 	nop
- 138:	f4 21 00 00 	bbvl r1,r1,13c <_start\+0x13c>
-			138: R_IQ2000_PC16	_startxfff8
- 13c:	00 00 00 00 	nop
- 140:	fc 21 00 00 	bbvnl r1,r1,144 <_start\+0x144>
-			140: R_IQ2000_PC16	_startxfff8
- 144:	00 00 00 00 	nop
- 148:	10 21 00 00 	beq r1,r1,14c <_start\+0x14c>
-			148: R_IQ2000_PC16	_startxfff8
- 14c:	00 00 00 00 	nop
- 150:	50 21 00 00 	beql r1,r1,154 <_start\+0x154>
-			150: R_IQ2000_PC16	_startxfff8
- 154:	00 00 00 00 	nop
- 158:	04 21 00 00 	bgez r1,15c <_start\+0x15c>
-			158: R_IQ2000_PC16	_startxfff8
- 15c:	00 00 00 00 	nop
- 160:	04 35 00 00 	bgtzal r1,164 <_start\+0x164>
-			160: R_IQ2000_PC16	_startxfff8
- 164:	00 00 00 00 	nop
- 168:	04 31 00 00 	bgezal r1,16c <_start\+0x16c>
-			168: R_IQ2000_PC16	_startxfff8
- 16c:	00 00 00 00 	nop
- 170:	04 37 00 00 	bgtzall r1,174 <_start\+0x174>
-			170: R_IQ2000_PC16	_startxfff8
- 174:	00 00 00 00 	nop
- 178:	04 33 00 00 	bgezall r1,17c <_start\+0x17c>
-			178: R_IQ2000_PC16	_startxfff8
- 17c:	00 00 00 00 	nop
- 180:	04 23 00 00 	bgezl r1,184 <_start\+0x184>
-			180: R_IQ2000_PC16	_startxfff8
- 184:	00 00 00 00 	nop
- 188:	04 27 00 00 	bgtzl r1,18c <_start\+0x18c>
-			188: R_IQ2000_PC16	_startxfff8
- 18c:	00 00 00 00 	nop
- 190:	04 25 00 00 	bgtz r1,194 <_start\+0x194>
-			190: R_IQ2000_PC16	_startxfff8
- 194:	00 00 00 00 	nop
- 198:	04 24 00 00 	blez r1,19c <_start\+0x19c>
-			198: R_IQ2000_PC16	_startxfff8
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 00 00 	blezal r1,1a4 <_start\+0x1a4>
-			1a0: R_IQ2000_PC16	_startxfff8
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 00 00 	bltz r1,1ac <_start\+0x1ac>
-			1a8: R_IQ2000_PC16	_startxfff8
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 00 00 	bltzal r1,1b4 <_start\+0x1b4>
-			1b0: R_IQ2000_PC16	_startxfff8
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 00 00 	blezl r1,1bc <_start\+0x1bc>
-			1b8: R_IQ2000_PC16	_startxfff8
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 00 00 	bltzl r1,1c4 <_start\+0x1c4>
-			1c0: R_IQ2000_PC16	_startxfff8
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 00 00 	blezall r1,1cc <_start\+0x1cc>
-			1c8: R_IQ2000_PC16	_startxfff8
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 00 00 	bltzall r1,1d4 <_start\+0x1d4>
-			1d0: R_IQ2000_PC16	_startxfff8
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 00 00 	bmb r1,r1,1dc <_start\+0x1dc>
-			1d8: R_IQ2000_PC16	_startxfff8
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 00 00 	bmbl r1,r1,1e4 <_start\+0x1e4>
-			1e0: R_IQ2000_PC16	_startxfff8
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 00 00 	bmb0 r1,r1,1ec <_start\+0x1ec>
-			1e8: R_IQ2000_PC16	_startxfff8
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 00 00 	bmb1 r1,r1,1f4 <_start\+0x1f4>
-			1f0: R_IQ2000_PC16	_startxfff8
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 00 00 	bmb2 r1,r1,1fc <_start\+0x1fc>
-			1f8: R_IQ2000_PC16	_startxfff8
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 00 00 	bmb3 r1,r1,204 <_start\+0x204>
-			200: R_IQ2000_PC16	_startxfff8
- 204:	00 00 00 00 	nop
- 208:	14 21 00 00 	bne r1,r1,20c <_start\+0x20c>
-			208: R_IQ2000_PC16	_startxfff8
- 20c:	00 00 00 00 	nop
- 210:	54 21 00 00 	bnel r1,r1,214 <_start\+0x214>
-			210: R_IQ2000_PC16	_startxfff8
- 214:	00 00 00 00 	nop
- 218:	08 00 3f fe 	j fff8 <_start\+0xfff8>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 3f fe 	jal r1,fff8 <_start\+0xfff8>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 ff f8 	lw r1,0xfff8\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 ff f8 	lh r1,0xfff8\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 ff f8 	lb r1,0xfff8\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 ff f8 	lhu r1,0xfff8\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 ff f8 	lbu r1,0xfff8\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 ff f8 	sb r1,0xfff8\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 ff f8 	sh r1,0xfff8\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 ff f8 	sw r1,0xfff8\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 00 	rbi r1,r1,r1,0x0
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 00 	rbir r1,r1,r1,0x0
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 00 	rbil r1,r1,r1,0x0
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 00 	wbi r1,r1,r1,0x0
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 00 	wbic r1,r1,r1,0x0
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 00 	wbiu r1,r1,r1,0x0
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2a 	pkrlah r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 29 	pkrlau r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 08 00 	pkrli r1,r1,r1,0x0
- 30c:	00 00 00 00 	nop
- 310:	48 21 0a 00 	pkrlih r1,r1,r1,0x0
- 314:	00 00 00 00 	nop
- 318:	48 21 09 00 	pkrliu r1,r1,r1,0x0
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 08 06 	swwr r1,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 08 07 	swwru r1,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 02 10 0c 	dwrd r2,r2
- 354:	00 00 00 00 	nop
- 358:	4c 02 10 0d 	dwrdl r2,r2
- 35c:	00 00 00 00 	nop
- 360:	4c 21 08 ab 	cm32and r1,r1,r1
- 364:	00 00 00 00 	nop
- 368:	4c 21 08 a3 	cm32andn r1,r1,r1
- 36c:	00 00 00 00 	nop
- 370:	4c 21 08 aa 	cm32or r1,r1,r1
- 374:	00 00 00 00 	nop
- 378:	4c 21 08 b0 	cm32ra r1,r1,r1
- 37c:	00 00 00 00 	nop
- 380:	4c 01 08 a1 	cm32rd r1,r1
- 384:	00 00 00 00 	nop
- 388:	4c 01 08 a4 	cm32ri r1,r1
- 38c:	00 00 00 00 	nop
- 390:	4c 21 08 a0 	cm32rs r1,r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 21 08 b8 	cm32sa r1,r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 01 08 a9 	cm32sd r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 01 08 ac 	cm32si r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 21 08 a8 	cm32ss r1,r1,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 21 08 a2 	cm32xor r1,r1,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 02 10 85 	cm64clr r2,r2
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 42 10 90 	cm64ra r2,r2,r2
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 02 10 81 	cm64rd r2,r2
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 02 10 84 	cm64ri r2,r2
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 42 10 94 	cm64ria2 r2,r2,r2
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 42 10 80 	cm64rs r2,r2,r2
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 42 10 98 	cm64sa r2,r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 02 10 89 	cm64sd r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 02 10 8c 	cm64si r2,r2
- 404:	00 00 00 00 	nop
- 408:	4c 42 10 9c 	cm64sia2 r2,r2,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 42 10 88 	cm64ss r2,r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 10 95 	cm128ria2 r2,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 21 08 14 	crc32 r1,r1,r1
- 424:	00 00 00 00 	nop
- 428:	4c 21 08 15 	crc32b r1,r1,r1
- 42c:	00 00 00 00 	nop
- 430:	4c 20 08 26 	chkhdr r1,r1
- 434:	00 00 00 00 	nop
- 438:	4c 00 08 24 	avail r1
- 43c:	00 00 00 00 	nop
- 440:	4c 20 08 25 	free r1,r1
- 444:	00 00 00 00 	nop
- 448:	4c 00 08 2c 	cmphdr r1
- 44c:	00 00 00 00 	nop
- 450:	4c 01 08 20 	mcid r1,r1
- 454:	00 00 00 00 	nop
- 458:	4c 00 08 22 	dba r1
- 45c:	00 00 00 00 	nop
- 460:	4c 01 08 21 	dbd r1,r0,r1
- 464:	00 00 00 00 	nop
- 468:	4c 20 08 23 	dpwt r1,r1
- 46c:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test8.s b/gas/testsuite/gas/iq2000/q10test8.s
deleted file mode 100644
index 9484f3111d37..000000000000
--- a/gas/testsuite/gas/iq2000/q10test8.s
+++ /dev/null
@@ -1,286 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0xfff8

-	 NOP	

-	 ADDIU	%1,%1,0xfff8

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0xfff8

-	 NOP	

-	 ANDOI	%1,%1,0xfff8

-	 NOP	

-	 ANDOUI	%1,%1,0xfff8

-	 NOP	

-	 LUI	%1,0xfff8

-	 NOP	

-	 MRGB	%1,%1,%1,0

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0xfff8

-	 NOP	

-	 ORUI	%1,%1,0xfff8

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0xfff8

-	 NOP	

-	 SLTIU	%1,%1,0xfff8

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0xfff8

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,0,0

-	 NOP	

-	 BBI	%1(31),_startxfff8

-	 NOP	

-	 BBIN	%1(31),_startxfff8

-	 NOP	

-	 BBV	%1,%1,_startxfff8

-	 NOP	

-	 BBVN	%1,%1,_startxfff8

-	 NOP	

-	 BBIL	%1(31),_startxfff8

-	 NOP	

-	 BBINL	%1(31),_startxfff8

-	 NOP	

-	 BBVL	%1,%1,_startxfff8

-	 NOP	

-	 BBVNL	%1,%1,_startxfff8

-	 NOP	

-	 BEQ	%1,%1,_startxfff8

-	 NOP	

-	 BEQL	%1,%1,_startxfff8

-	 NOP	

-	 BGEZ	%1,_startxfff8

-	 NOP	

-	 BGTZAL	%1,_startxfff8

-	 NOP	

-	 BGEZAL	%1,_startxfff8

-	 NOP	

-	 BGTZALL	%1,_startxfff8

-	 NOP	

-	 BGEZALL	%1,_startxfff8

-	 NOP	

-	 BGEZL	%1,_startxfff8

-	 NOP	

-	 BGTZL	%1,_startxfff8

-	 NOP	

-	 BGTZ	%1,_startxfff8

-	 NOP	

-	 BLEZ	%1,_startxfff8

-	 NOP	

-	 BLEZAL	%1,_startxfff8

-	 NOP	

-	 BLTZ	%1,_startxfff8

-	 NOP	

-	 BLTZAL	%1,_startxfff8

-	 NOP	

-	 BLEZL	%1,_startxfff8

-	 NOP	

-	 BLTZL	%1,_startxfff8

-	 NOP	

-	 BLEZALL	%1,_startxfff8

-	 NOP	

-	 BLTZALL	%1,_startxfff8

-	 NOP	

-	 BMB	%1,%1,_startxfff8

-	 NOP	

-	 BMBL	%1,%1,_startxfff8

-	 NOP	

-	 BMB0	%1,%1,_startxfff8

-	 NOP	

-	 BMB1	%1,%1,_startxfff8

-	 NOP	

-	 BMB2	%1,%1,_startxfff8

-	 NOP	

-	 BMB3	%1,%1,_startxfff8

-	 NOP	

-	 BNE	%1,%1,_startxfff8

-	 NOP	

-	 BNEL	%1,%1,_startxfff8

-	 NOP	

-	 J	0xfff8

-	 NOP	

-	 JAL	%1,0xfff8

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0xfff8(%1)

-	 NOP	

-	 LH	%1,0xfff8(%1)

-	 NOP	

-	 LB	%1,0xfff8(%1)

-	 NOP	

-	 LHU	%1,0xfff8(%1)

-	 NOP	

-	 LBU	%1,0xfff8(%1)

-	 NOP	

-	 SB	%1,0xfff8(%1)

-	 NOP	

-	 SH	%1,0xfff8(%1)

-	 NOP	

-	 SW	%1,0xfff8(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,0

-	 NOP	

-	 RBIR	%1,%1,%1,0

-	 NOP	

-	 RBIL	%1,%1,%1,0

-	 NOP	

-	 WBI	%1,%1,%1,0

-	 NOP	

-	 WBIC	%1,%1,%1,0

-	 NOP	

-	 WBIU	%1,%1,%1,0

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,0

-	 NOP	

-	 PKRLIH	%1,%1,%1,0

-	 NOP	

-	 PKRLIU	%1,%1,%1,0

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 DWRD	%2,%2

-	 NOP	

-	 DWRDL	%2,%2

-	 NOP	

-	 CM32AND	%1,%1,%1

-	 NOP	

-	 CM32ANDN	%1,%1,%1

-	 NOP	

-	 CM32OR	%1,%1,%1

-	 NOP	

-	 CM32RA	%1,%1,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%1,%1

-	 NOP	

-	 CM32SA	%1,%1,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%1,%1

-	 NOP	

-	 CM32XOR	%1,%1,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%2,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%2,%2

-	 NOP	

-	 CM64RS	%2,%2,%2

-	 NOP	

-	 CM64SA	%2,%2,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%2,%2

-	 NOP	

-	 CM64SS	%2,%2,%2

-	 NOP	

-	 CM128RIA2	%2,%2,%2

-	 NOP	

-	 CRC32	%1,%1,%1

-	 NOP	

-	 CRC32B	%1,%1,%1

-	 NOP	

-	 CHKHDR	%1,%1

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%1

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10test9.d b/gas/testsuite/gas/iq2000/q10test9.d
deleted file mode 100644
index 9a1f295a1428..000000000000
--- a/gas/testsuite/gas/iq2000/q10test9.d
+++ /dev/null
@@ -1,291 +0,0 @@
-#as: -m10
-#objdump: -drz
-#name: q10test9
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <_start>:
-   0:	00 21 08 20 	add r1,r1,r1
-   4:	00 00 00 00 	nop
-   8:	20 21 00 00 	addi r1,r1,0x0
-   c:	00 00 00 00 	nop
-  10:	24 21 00 00 	addiu r1,r1,0x0
-  14:	00 00 00 00 	nop
-  18:	00 21 08 21 	addu r1,r1,r1
-  1c:	00 00 00 00 	nop
-  20:	00 21 08 29 	ado16 r1,r1,r1
-  24:	00 00 00 00 	nop
-  28:	00 21 08 24 	and r1,r1,r1
-  2c:	00 00 00 00 	nop
-  30:	30 21 00 00 	andi r1,r1,0x0
-  34:	00 00 00 00 	nop
-  38:	b0 21 00 00 	andoi r1,r1,0x0
-  3c:	00 00 00 00 	nop
-  40:	bc 21 00 00 	andoui r1,r1,0x0
-  44:	00 00 00 00 	nop
-  48:	3c 01 00 00 	lui r1,0x0
-  4c:	00 00 00 00 	nop
-  50:	00 21 08 6d 	mrgb r1,r1,r1,0x1
-  54:	00 00 00 00 	nop
-  58:	00 21 08 27 	nor r1,r1,r1
-  5c:	00 00 00 00 	nop
-  60:	00 21 08 25 	or r1,r1,r1
-  64:	00 00 00 00 	nop
-  68:	34 21 00 00 	ori r1,r1,0x0
-  6c:	00 00 00 00 	nop
-  70:	3c 21 00 00 	orui r1,r1,0x0
-  74:	00 00 00 00 	nop
-  78:	00 01 08 00 	sll r1,r1,0x0
-  7c:	00 00 00 00 	nop
-  80:	00 21 08 04 	sllv r1,r1,r1
-  84:	00 00 00 00 	nop
-  88:	00 21 08 2a 	slt r1,r1,r1
-  8c:	00 00 00 00 	nop
-  90:	28 21 00 00 	slti r1,r1,0x0
-  94:	00 00 00 00 	nop
-  98:	2c 21 00 00 	sltiu r1,r1,0x0
-  9c:	00 00 00 00 	nop
-  a0:	00 21 08 2b 	sltu r1,r1,r1
-  a4:	00 00 00 00 	nop
-  a8:	00 01 08 03 	sra r1,r1,0x0
-  ac:	00 00 00 00 	nop
-  b0:	00 21 08 07 	srav r1,r1,r1
-  b4:	00 00 00 00 	nop
-  b8:	00 01 08 02 	srl r1,r1,0x0
-  bc:	00 00 00 00 	nop
-  c0:	00 21 08 06 	srlv r1,r1,r1
-  c4:	00 00 00 00 	nop
-  c8:	00 21 08 22 	sub r1,r1,r1
-  cc:	00 00 00 00 	nop
-  d0:	00 21 08 23 	subu r1,r1,r1
-  d4:	00 00 00 00 	nop
-  d8:	00 21 08 26 	xor r1,r1,r1
-  dc:	00 00 00 00 	nop
-  e0:	38 21 00 00 	xori r1,r1,0x0
-  e4:	00 00 00 00 	nop
-  e8:	00 00 00 00 	nop
-  ec:	00 00 00 00 	nop
-  f0:	00 21 08 05 	srmv r1,r1,r1,0x0
-  f4:	00 00 00 00 	nop
-  f8:	00 21 08 01 	slmv r1,r1,r1,0x0
-  fc:	00 00 00 00 	nop
- 100:	9c 21 08 01 	ram r1,r1,0x0,0x1,0x1
- 104:	00 00 00 00 	nop
- 108:	70 20 ff bd 	bbi r1\(0x0\),0 <_start>
- 10c:	00 00 00 00 	nop
- 110:	78 20 ff bb 	bbin r1\(0x0\),0 <_start>
- 114:	00 00 00 00 	nop
- 118:	74 21 ff b9 	bbv r1,r1,0 <_start>
- 11c:	00 00 00 00 	nop
- 120:	7c 21 ff b7 	bbvn r1,r1,0 <_start>
- 124:	00 00 00 00 	nop
- 128:	f0 20 ff b5 	bbil r1\(0x0\),0 <_start>
- 12c:	00 00 00 00 	nop
- 130:	f8 20 ff b3 	bbinl r1\(0x0\),0 <_start>
- 134:	00 00 00 00 	nop
- 138:	f4 21 ff b1 	bbvl r1,r1,0 <_start>
- 13c:	00 00 00 00 	nop
- 140:	fc 21 ff af 	bbvnl r1,r1,0 <_start>
- 144:	00 00 00 00 	nop
- 148:	10 21 ff ad 	beq r1,r1,0 <_start>
- 14c:	00 00 00 00 	nop
- 150:	50 21 ff ab 	beql r1,r1,0 <_start>
- 154:	00 00 00 00 	nop
- 158:	04 21 ff a9 	bgez r1,0 <_start>
- 15c:	00 00 00 00 	nop
- 160:	04 35 ff a7 	bgtzal r1,0 <_start>
- 164:	00 00 00 00 	nop
- 168:	04 31 ff a5 	bgezal r1,0 <_start>
- 16c:	00 00 00 00 	nop
- 170:	04 37 ff a3 	bgtzall r1,0 <_start>
- 174:	00 00 00 00 	nop
- 178:	04 33 ff a1 	bgezall r1,0 <_start>
- 17c:	00 00 00 00 	nop
- 180:	04 23 ff 9f 	bgezl r1,0 <_start>
- 184:	00 00 00 00 	nop
- 188:	04 27 ff 9d 	bgtzl r1,0 <_start>
- 18c:	00 00 00 00 	nop
- 190:	04 25 ff 9b 	bgtz r1,0 <_start>
- 194:	00 00 00 00 	nop
- 198:	04 24 ff 99 	blez r1,0 <_start>
- 19c:	00 00 00 00 	nop
- 1a0:	04 34 ff 97 	blezal r1,0 <_start>
- 1a4:	00 00 00 00 	nop
- 1a8:	04 20 ff 95 	bltz r1,0 <_start>
- 1ac:	00 00 00 00 	nop
- 1b0:	04 30 ff 93 	bltzal r1,0 <_start>
- 1b4:	00 00 00 00 	nop
- 1b8:	04 26 ff 91 	blezl r1,0 <_start>
- 1bc:	00 00 00 00 	nop
- 1c0:	04 22 ff 8f 	bltzl r1,0 <_start>
- 1c4:	00 00 00 00 	nop
- 1c8:	04 36 ff 8d 	blezall r1,0 <_start>
- 1cc:	00 00 00 00 	nop
- 1d0:	04 32 ff 8b 	bltzall r1,0 <_start>
- 1d4:	00 00 00 00 	nop
- 1d8:	18 21 ff 89 	bmb r1,r1,0 <_start>
- 1dc:	00 00 00 00 	nop
- 1e0:	58 21 ff 87 	bmbl r1,r1,0 <_start>
- 1e4:	00 00 00 00 	nop
- 1e8:	60 21 ff 85 	bmb0 r1,r1,0 <_start>
- 1ec:	00 00 00 00 	nop
- 1f0:	64 21 ff 83 	bmb1 r1,r1,0 <_start>
- 1f4:	00 00 00 00 	nop
- 1f8:	68 21 ff 81 	bmb2 r1,r1,0 <_start>
- 1fc:	00 00 00 00 	nop
- 200:	6c 21 ff 7f 	bmb3 r1,r1,0 <_start>
- 204:	00 00 00 00 	nop
- 208:	14 21 ff 7d 	bne r1,r1,0 <_start>
- 20c:	00 00 00 00 	nop
- 210:	54 21 ff 7b 	bnel r1,r1,0 <_start>
- 214:	00 00 00 00 	nop
- 218:	08 00 00 00 	j 0 <_start>
- 21c:	00 00 00 00 	nop
- 220:	0c 01 00 00 	jal r1,0 <_start>
- 224:	00 00 00 00 	nop
- 228:	00 20 08 09 	jalr r1,r1
- 22c:	00 00 00 00 	nop
- 230:	00 20 00 08 	jr r1
- 234:	00 00 00 00 	nop
- 238:	00 00 00 0d 	break
- 23c:	00 00 00 00 	nop
- 240:	4c 21 00 02 	ctc r1,r1
- 244:	00 00 00 00 	nop
- 248:	4c 01 08 00 	cfc r1,r1
- 24c:	00 00 00 00 	nop
- 250:	8c 21 00 00 	lw r1,0x0\(r1\)
- 254:	00 00 00 00 	nop
- 258:	84 21 00 00 	lh r1,0x0\(r1\)
- 25c:	00 00 00 00 	nop
- 260:	80 21 00 00 	lb r1,0x0\(r1\)
- 264:	00 00 00 00 	nop
- 268:	94 21 00 00 	lhu r1,0x0\(r1\)
- 26c:	00 00 00 00 	nop
- 270:	90 21 00 00 	lbu r1,0x0\(r1\)
- 274:	00 00 00 00 	nop
- 278:	a0 21 00 00 	sb r1,0x0\(r1\)
- 27c:	00 00 00 00 	nop
- 280:	a4 21 00 00 	sh r1,0x0\(r1\)
- 284:	00 00 00 00 	nop
- 288:	ac 21 00 00 	sw r1,0x0\(r1\)
- 28c:	00 00 00 00 	nop
- 290:	4c 21 08 08 	rba r1,r1,r1
- 294:	00 00 00 00 	nop
- 298:	4c 21 08 0a 	rbar r1,r1,r1
- 29c:	00 00 00 00 	nop
- 2a0:	4c 21 08 09 	rbal r1,r1,r1
- 2a4:	00 00 00 00 	nop
- 2a8:	4c 21 08 10 	wba r1,r1,r1
- 2ac:	00 00 00 00 	nop
- 2b0:	4c 21 08 12 	wbac r1,r1,r1
- 2b4:	00 00 00 00 	nop
- 2b8:	4c 21 08 11 	wbau r1,r1,r1
- 2bc:	00 00 00 00 	nop
- 2c0:	4c 21 0a 08 	rbi r1,r1,r1,0x8
- 2c4:	00 00 00 00 	nop
- 2c8:	4c 21 09 08 	rbir r1,r1,r1,0x8
- 2cc:	00 00 00 00 	nop
- 2d0:	4c 21 0b 08 	rbil r1,r1,r1,0x8
- 2d4:	00 00 00 00 	nop
- 2d8:	4c 21 0e 08 	wbi r1,r1,r1,0x8
- 2dc:	00 00 00 00 	nop
- 2e0:	4c 21 0d 08 	wbic r1,r1,r1,0x8
- 2e4:	00 00 00 00 	nop
- 2e8:	4c 21 0f 08 	wbiu r1,r1,r1,0x8
- 2ec:	00 00 00 00 	nop
- 2f0:	4c 21 08 28 	pkrla r1,r1,r1
- 2f4:	00 00 00 00 	nop
- 2f8:	4c 21 08 2a 	pkrlah r1,r1,r1
- 2fc:	00 00 00 00 	nop
- 300:	4c 21 08 29 	pkrlau r1,r1,r1
- 304:	00 00 00 00 	nop
- 308:	48 21 08 08 	pkrli r1,r1,r1,0x8
- 30c:	00 00 00 00 	nop
- 310:	48 21 0a 08 	pkrlih r1,r1,r1,0x8
- 314:	00 00 00 00 	nop
- 318:	48 21 09 08 	pkrliu r1,r1,r1,0x8
- 31c:	00 00 00 00 	nop
- 320:	4c 01 08 01 	lock r1,r1
- 324:	00 00 00 00 	nop
- 328:	4c 01 08 03 	unlk r1,r1
- 32c:	00 00 00 00 	nop
- 330:	4c 21 08 06 	swwr r1,r1,r1
- 334:	00 00 00 00 	nop
- 338:	4c 21 08 07 	swwru r1,r1,r1
- 33c:	00 00 00 00 	nop
- 340:	4c 01 08 04 	swrd r1,r1
- 344:	00 00 00 00 	nop
- 348:	4c 01 08 05 	swrdl r1,r1
- 34c:	00 00 00 00 	nop
- 350:	4c 02 10 0c 	dwrd r2,r2
- 354:	00 00 00 00 	nop
- 358:	4c 02 10 0d 	dwrdl r2,r2
- 35c:	00 00 00 00 	nop
- 360:	4c 21 08 ab 	cm32and r1,r1,r1
- 364:	00 00 00 00 	nop
- 368:	4c 21 08 a3 	cm32andn r1,r1,r1
- 36c:	00 00 00 00 	nop
- 370:	4c 21 08 aa 	cm32or r1,r1,r1
- 374:	00 00 00 00 	nop
- 378:	4c 21 08 b0 	cm32ra r1,r1,r1
- 37c:	00 00 00 00 	nop
- 380:	4c 01 08 a1 	cm32rd r1,r1
- 384:	00 00 00 00 	nop
- 388:	4c 01 08 a4 	cm32ri r1,r1
- 38c:	00 00 00 00 	nop
- 390:	4c 21 08 a0 	cm32rs r1,r1,r1
- 394:	00 00 00 00 	nop
- 398:	4c 21 08 b8 	cm32sa r1,r1,r1
- 39c:	00 00 00 00 	nop
- 3a0:	4c 01 08 a9 	cm32sd r1,r1
- 3a4:	00 00 00 00 	nop
- 3a8:	4c 01 08 ac 	cm32si r1,r1
- 3ac:	00 00 00 00 	nop
- 3b0:	4c 21 08 a8 	cm32ss r1,r1,r1
- 3b4:	00 00 00 00 	nop
- 3b8:	4c 21 08 a2 	cm32xor r1,r1,r1
- 3bc:	00 00 00 00 	nop
- 3c0:	4c 02 10 85 	cm64clr r2,r2
- 3c4:	00 00 00 00 	nop
- 3c8:	4c 42 10 90 	cm64ra r2,r2,r2
- 3cc:	00 00 00 00 	nop
- 3d0:	4c 02 10 81 	cm64rd r2,r2
- 3d4:	00 00 00 00 	nop
- 3d8:	4c 02 10 84 	cm64ri r2,r2
- 3dc:	00 00 00 00 	nop
- 3e0:	4c 42 10 94 	cm64ria2 r2,r2,r2
- 3e4:	00 00 00 00 	nop
- 3e8:	4c 42 10 80 	cm64rs r2,r2,r2
- 3ec:	00 00 00 00 	nop
- 3f0:	4c 42 10 98 	cm64sa r2,r2,r2
- 3f4:	00 00 00 00 	nop
- 3f8:	4c 02 10 89 	cm64sd r2,r2
- 3fc:	00 00 00 00 	nop
- 400:	4c 02 10 8c 	cm64si r2,r2
- 404:	00 00 00 00 	nop
- 408:	4c 42 10 9c 	cm64sia2 r2,r2,r2
- 40c:	00 00 00 00 	nop
- 410:	4c 42 10 88 	cm64ss r2,r2,r2
- 414:	00 00 00 00 	nop
- 418:	4c 42 10 14 	crc32 r2,r2,r2
- 41c:	00 00 00 00 	nop
- 420:	4c 42 10 15 	crc32b r2,r2,r2
- 424:	00 00 00 00 	nop
- 428:	4c 40 10 26 	chkhdr r2,r2
- 42c:	00 00 00 00 	nop
- 430:	4c 00 08 24 	avail r1
- 434:	00 00 00 00 	nop
- 438:	4c 20 08 25 	free r1,r1
- 43c:	00 00 00 00 	nop
- 440:	4c 00 08 2c 	cmphdr r1
- 444:	00 00 00 00 	nop
- 448:	4c 01 08 20 	mcid r1,r1
- 44c:	00 00 00 00 	nop
- 450:	4c 00 08 22 	dba r1
- 454:	00 00 00 00 	nop
- 458:	4c 01 08 21 	dbd r1,r0,r1
- 45c:	00 00 00 00 	nop
- 460:	4c 20 08 23 	dpwt r1,r1
- 464:	00 00 00 00 	nop
diff --git a/gas/testsuite/gas/iq2000/q10test9.s b/gas/testsuite/gas/iq2000/q10test9.s
deleted file mode 100644
index 0481743aa7ab..000000000000
--- a/gas/testsuite/gas/iq2000/q10test9.s
+++ /dev/null
@@ -1,284 +0,0 @@
-.global _start

-_start:

-	 ADD	%1,%1,%1

-	 NOP	

-	 ADDI	%1,%1,0

-	 NOP	

-	 ADDIU	%1,%1,0

-	 NOP	

-	 ADDU	%1,%1,%1

-	 NOP	

-	 ADO16	%1,%1,%1

-	 NOP	

-	 AND	%1,%1,%1

-	 NOP	

-	 ANDI	%1,%1,0

-	 NOP	

-	 ANDOI	%1,%1,0

-	 NOP	

-	 ANDOUI	%1,%1,0

-	 NOP	

-	 LUI	%1,0

-	 NOP	

-	 MRGB	%1,%1,%1,1

-	 NOP	

-	 NOR	%1,%1,%1

-	 NOP	

-	 OR	%1,%1,%1

-	 NOP	

-	 ORI	%1,%1,0

-	 NOP	

-	 ORUI	%1,%1,0

-	 NOP	

-	 SLL	%1,%1,0

-	 NOP	

-	 SLLV	%1,%1,%1

-	 NOP	

-	 SLT	%1,%1,%1

-	 NOP	

-	 SLTI	%1,%1,0

-	 NOP	

-	 SLTIU	%1,%1,0

-	 NOP	

-	 SLTU	%1,%1,%1

-	 NOP	

-	 SRA	%1,%1,0

-	 NOP	

-	 SRAV	%1,%1,%1

-	 NOP	

-	 SRL	%1,%1,0

-	 NOP	

-	 SRLV	%1,%1,%1

-	 NOP	

-	 SUB	%1,%1,%1

-	 NOP	

-	 SUBU	%1,%1,%1

-	 NOP	

-	 XOR	%1,%1,%1

-	 NOP	

-	 XORI	%1,%1,0

-	 NOP	

-	 NOP	

-	 NOP	

-	 SRMV	%1,%1,%1,0

-	 NOP	

-	 SLMV	%1,%1,%1,0

-	 NOP	

-	 RAM	%1,%1,0,1,1

-	 NOP	

-	 BBI	%1(0),_start

-	 NOP	

-	 BBIN	%1(0),_start

-	 NOP	

-	 BBV	%1,%1,_start

-	 NOP	

-	 BBVN	%1,%1,_start

-	 NOP	

-	 BBIL	%1(0),_start

-	 NOP	

-	 BBINL	%1(0),_start

-	 NOP	

-	 BBVL	%1,%1,_start

-	 NOP	

-	 BBVNL	%1,%1,_start

-	 NOP	

-	 BEQ	%1,%1,_start

-	 NOP	

-	 BEQL	%1,%1,_start

-	 NOP	

-	 BGEZ	%1,_start

-	 NOP	

-	 BGTZAL	%1,_start

-	 NOP	

-	 BGEZAL	%1,_start

-	 NOP	

-	 BGTZALL	%1,_start

-	 NOP	

-	 BGEZALL	%1,_start

-	 NOP	

-	 BGEZL	%1,_start

-	 NOP	

-	 BGTZL	%1,_start

-	 NOP	

-	 BGTZ	%1,_start

-	 NOP	

-	 BLEZ	%1,_start

-	 NOP	

-	 BLEZAL	%1,_start

-	 NOP	

-	 BLTZ	%1,_start

-	 NOP	

-	 BLTZAL	%1,_start

-	 NOP	

-	 BLEZL	%1,_start

-	 NOP	

-	 BLTZL	%1,_start

-	 NOP	

-	 BLEZALL	%1,_start

-	 NOP	

-	 BLTZALL	%1,_start

-	 NOP	

-	 BMB	%1,%1,_start

-	 NOP	

-	 BMBL	%1,%1,_start

-	 NOP	

-	 BMB0	%1,%1,_start

-	 NOP	

-	 BMB1	%1,%1,_start

-	 NOP	

-	 BMB2	%1,%1,_start

-	 NOP	

-	 BMB3	%1,%1,_start

-	 NOP	

-	 BNE	%1,%1,_start

-	 NOP	

-	 BNEL	%1,%1,_start

-	 NOP	

-	 J	0

-	 NOP	

-	 JAL	%1,0

-	 NOP	

-	 JALR	%1,%1

-	 NOP	

-	 JR	%1

-	 NOP	

-	 BREAK	

-	 NOP	

-	 CTC	%1,%1

-	 NOP	

-	 CFC	%1,%1

-	 NOP	

-	 LW	%1,0(%1)

-	 NOP	

-	 LH	%1,0(%1)

-	 NOP	

-	 LB	%1,0(%1)

-	 NOP	

-	 LHU	%1,0(%1)

-	 NOP	

-	 LBU	%1,0(%1)

-	 NOP	

-	 SB	%1,0(%1)

-	 NOP	

-	 SH	%1,0(%1)

-	 NOP	

-	 SW	%1,0(%1)

-	 NOP	

-	 RBA	%1,%1,%1

-	 NOP	

-	 RBAR	%1,%1,%1

-	 NOP	

-	 RBAL	%1,%1,%1

-	 NOP	

-	 WBA	%1,%1,%1

-	 NOP	

-	 WBAC	%1,%1,%1

-	 NOP	

-	 WBAU	%1,%1,%1

-	 NOP	

-	 RBI	%1,%1,%1,8

-	 NOP	

-	 RBIR	%1,%1,%1,8

-	 NOP	

-	 RBIL	%1,%1,%1,8

-	 NOP	

-	 WBI	%1,%1,%1,8

-	 NOP	

-	 WBIC	%1,%1,%1,8

-	 NOP	

-	 WBIU	%1,%1,%1,8

-	 NOP	

-	 PKRLA	%1,%1,%1

-	 NOP	

-	 PKRLAH	%1,%1,%1

-	 NOP	

-	 PKRLAU	%1,%1,%1

-	 NOP	

-	 PKRLI	%1,%1,%1,8

-	 NOP	

-	 PKRLIH	%1,%1,%1,8

-	 NOP	

-	 PKRLIU	%1,%1,%1,8

-	 NOP	

-	 LOCK	%1,%1

-	 NOP	

-	 UNLK	%1,%1

-	 NOP	

-	 SWWR	%1,%1,%1

-	 NOP	

-	 SWWRU	%1,%1,%1

-	 NOP	

-	 SWRD	%1,%1

-	 NOP	

-	 SWRDL	%1,%1

-	 NOP	

-	 DWRD	%2,%2

-	 NOP	

-	 DWRDL	%2,%2

-	 NOP	

-	 CM32AND	%1,%1,%1

-	 NOP	

-	 CM32ANDN	%1,%1,%1

-	 NOP	

-	 CM32OR	%1,%1,%1

-	 NOP	

-	 CM32RA	%1,%1,%1

-	 NOP	

-	 CM32RD	%1,%1

-	 NOP	

-	 CM32RI	%1,%1

-	 NOP	

-	 CM32RS	%1,%1,%1

-	 NOP	

-	 CM32SA	%1,%1,%1

-	 NOP	

-	 CM32SD	%1,%1

-	 NOP	

-	 CM32SI	%1,%1

-	 NOP	

-	 CM32SS	%1,%1,%1

-	 NOP	

-	 CM32XOR	%1,%1,%1

-	 NOP	

-	 CM64CLR	%2,%2

-	 NOP	

-	 CM64RA	%2,%2,%2

-	 NOP	

-	 CM64RD	%2,%2

-	 NOP	

-	 CM64RI	%2,%2

-	 NOP	

-	 CM64RIA2	%2,%2,%2

-	 NOP	

-	 CM64RS	%2,%2,%2

-	 NOP	

-	 CM64SA	%2,%2,%2

-	 NOP	

-	 CM64SD	%2,%2

-	 NOP	

-	 CM64SI	%2,%2

-	 NOP	

-	 CM64SIA2	%2,%2,%2

-	 NOP	

-	 CM64SS	%2,%2,%2

-	 NOP	

-	 CRC32	%2,%2,%2

-	 NOP	

-	 CRC32B	%2,%2,%2

-	 NOP	

-	 CHKHDR	%2,%2

-	 NOP	

-	 AVAIL	%1

-	 NOP	

-	 FREE	%1,%1

-	 NOP	

-	 CMPHDR	%1

-	 NOP	

-	 MCID	%1,%1

-	 NOP	

-	 DBA	%1

-	 NOP	

-	 DBD	%1,%1

-	 NOP	

-	 DPWT	%1,%1

-	 NOP	

diff --git a/gas/testsuite/gas/iq2000/q10yield.exp b/gas/testsuite/gas/iq2000/q10yield.exp
deleted file mode 100644
index 9e9d9dcf4728..000000000000
--- a/gas/testsuite/gas/iq2000/q10yield.exp
+++ /dev/null
@@ -1,39 +0,0 @@
-# Test for warnings when placing yield instructions into IQ2000's
-# branch delay slot.  Written by Ben Elliston (bje@redhat.com)
-
-# Run GAS and check that it emits the desired warning for the test case.
-# Arguments:
-#   file -- name of the test case to assemble.
-#   testname -- a string describing the test.
-#   warnpattern -- a regular expression, suitable for use by the Tcl
-#     regexp command, to decide if the warning string was emitted by
-#     the assembler to stderr.
-
-proc iq2000_warning_test { file testname {warnpattern ""} } {
-    global comp_output
-
-    gas_run $file "-m10" ">/dev/null"
-    verbose "output was $comp_output" 2
-
-    if {$warnpattern == ""} {
-	if {$comp_output == ""} { pass $testname } else { fail $testname }
-	return
-    }
-
-    if {[regexp "Warning: $warnpattern" $comp_output]} {
-	pass $testname
-    } else {
-	fail $testname
-    }
-}
-
-if [istarget iq2000*-*-*] {
-    foreach file [glob -nocomplain -- $srcdir/$subdir/q10yield*.s] {
-	set file [file tail $file]
-	iq2000_warning_test $file \
-		"assembler emits yield instruction in delay slot warning for $file" \
-		"instruction \[a-zA-Z0-9\]+ may not follow a branch/jump"
-    }
-    set testname "assembler emits no warnings for non-yield instruction in delay slot"
-    iq2000_warning_test q10noyield.s $testname
-}
diff --git a/gas/testsuite/gas/iq2000/test.exp b/gas/testsuite/gas/iq2000/test.exp
deleted file mode 100644
index 3f1553c4b27c..000000000000
--- a/gas/testsuite/gas/iq2000/test.exp
+++ /dev/null
@@ -1,17 +0,0 @@
-# IQ2000 assembler testsuite.
-
-if [istarget iq2000*-*-*] {
-    run_dump_test "q10test0"
-    run_dump_test "q10test1"
-    run_dump_test "q10test2"
-    run_dump_test "q10test3"
-    run_dump_test "q10test4"
-    run_dump_test "q10test5"
-    run_dump_test "q10test6"
-    run_dump_test "q10test7"
-    run_dump_test "q10test8"
-    run_dump_test "q10test9"
-    run_dump_test "q10test10"
-    run_dump_test "q10test11"
-    run_dump_test "q10test12"
-}
diff --git a/gas/testsuite/gas/lns/lns-common-1.d b/gas/testsuite/gas/lns/lns-common-1.d
new file mode 100644
index 000000000000..69de6388c067
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns-common-1.d
@@ -0,0 +1,26 @@
+#readelf: -wl
+#name: lns-common-1
+Dump of debug contents of section \.debug_line:
+#...
+  Initial value of 'is_stmt':  1
+#...
+ Line Number Statements:
+  Extended opcode 2: set Address to .*
+  Copy
+  Set column to 3
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 2
+  Set prologue_end to true
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 3
+  Set column to 0
+  Set epilogue_begin to true
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 4
+  Set ISA to 1
+  Set basic block
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 5
+  Set is_stmt to 0
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 6
+  Set is_stmt to 1
+  Special opcode .*: advance Address by .* to .* and Line by 1 to 7
+  Advance PC by .* to .*
+  Extended opcode 1: End of Sequence
+#...
diff --git a/gas/testsuite/gas/lns/lns-common-1.s b/gas/testsuite/gas/lns/lns-common-1.s
new file mode 100644
index 000000000000..f1d590b457bb
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns-common-1.s
@@ -0,0 +1,15 @@
+	.file 1 "foo.c"
+	.loc 1 1
+	nop
+	.loc 1 2 3
+	nop
+	.loc 1 3 prologue_end
+	nop
+	.loc 1 4 0 epilogue_begin
+	nop
+	.loc 1 5 isa 1 basic_block
+	nop
+	.loc 1 6 is_stmt 0
+	nop
+	.loc 1 7 is_stmt 1
+	nop
diff --git a/gas/testsuite/gas/lns/lns-diag-1.l b/gas/testsuite/gas/lns/lns-diag-1.l
new file mode 100644
index 000000000000..53f993605de5
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns-diag-1.l
@@ -0,0 +1,15 @@
+.*: Assembler messages:
+.*:2: Error: file number less than one
+.*:3: Error: missing string
+.*:4: Error: file number 1 already allocated
+.*:8: Error: unassigned file number 3
+.*:9: Error: junk at end of line, first unrecognized character is `1'
+.*:12: Error: junk at end of line, first unrecognized character is `0'
+.*:18: Error: is_stmt value not 0 or 1
+.*:19: Error: bad or irreducible absolute expression
+.*:23: Error: isa number less than zero
+.*:26: Error: bad or irreducible absolute expression
+.*:26: Error: file number less than one
+.*:27: Error: bad or irreducible absolute expression
+.*:28: Error: unknown .loc sub-directive `frobnitz'
+.*:29: Error: unknown .loc sub-directive `frobnitz'
diff --git a/gas/testsuite/gas/lns/lns-diag-1.s b/gas/testsuite/gas/lns/lns-diag-1.s
new file mode 100644
index 000000000000..7a0aa409189e
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns-diag-1.s
@@ -0,0 +1,29 @@
+	.file 1 "foo.c"
+	.file 0 "bar.c"
+	.file 2 baz.c
+	.file 1 "bar.c"
+
+	.loc 1 1
+	.loc 1 2 3
+	.loc 3 1
+	.loc 1 1 1 1
+
+	.loc 1 1 basic_block
+	.loc 1 1 basic_block 0
+	.loc 1 1 prologue_end
+	.loc 1 1 epilogue_begin
+
+	.loc 1 1 1 is_stmt 0
+	.loc 1 1 1 is_stmt 1
+	.loc 1 1 1 is_stmt 2
+	.loc 1 1 1 is_stmt foo
+
+	.loc 1 1 isa 1
+	.loc 1 1 isa 2
+	.loc 1 1 isa -1
+	.loc 1 1 isa 0
+
+	.loc frobnitz
+	.loc 1 frobnitz
+	.loc 1 1 frobnitz
+	.loc 1 1 1 frobnitz
diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp
new file mode 100644
index 000000000000..1bc95990e3ea
--- /dev/null
+++ b/gas/testsuite/gas/lns/lns.exp
@@ -0,0 +1,27 @@
+# ??? This probably shouldn't be replicated here...
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "lns $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+        fail $testname
+        verbose "output is [file_contents "dump.out"]" 2
+        return
+    }
+    pass $testname
+}
+
+if ![is_elf_format] then {
+    return
+}
+
+run_list_test "lns-diag-1" ""
+
+# ??? Won't work on targets that don't have a bare "nop" insn.
+# Perhaps we could arrange for an include file or something that
+# defined a macro...
+if { ![istarget ia64*-*-*] && ![istarget i370-*-*] && ![istarget i960-*-*]
+     && ![istarget or32-*-*] && ![istarget s390*-*-*] } {
+  run_dump_test "lns-common-1"
+}
diff --git a/gas/testsuite/gas/m32r/error.exp b/gas/testsuite/gas/m32r/error.exp
index 17807c12beee..11c15d580e6a 100644
--- a/gas/testsuite/gas/m32r/error.exp
+++ b/gas/testsuite/gas/m32r/error.exp
@@ -10,6 +10,7 @@ if [istarget m32r-*-*] {
     dg-runtest "$srcdir/$subdir/interfere.s" "" ""
     dg-runtest "$srcdir/$subdir/outofrange.s" "" ""
     dg-runtest "$srcdir/$subdir/parallel.s" "" ""
+    dg-runtest "$srcdir/$subdir/rel32-err.s" "" ""
 
     dg-finish
 
diff --git a/gas/testsuite/gas/m32r/m32r.exp b/gas/testsuite/gas/m32r/m32r.exp
index 0ac272b13585..32e376d30cae 100644
--- a/gas/testsuite/gas/m32r/m32r.exp
+++ b/gas/testsuite/gas/m32r/m32r.exp
@@ -6,4 +6,6 @@ if [istarget m32r*-*-*] {
     run_dump_test "uppercase"
     run_dump_test "fslot"
     run_dump_test "signed-relocs"
+    run_dump_test "seth"
+    run_dump_test "rela-1"
 }
diff --git a/gas/testsuite/gas/m32r/m32r2.exp b/gas/testsuite/gas/m32r/m32r2.exp
index 03a160aa589e..f5f7415d9ed2 100644
--- a/gas/testsuite/gas/m32r/m32r2.exp
+++ b/gas/testsuite/gas/m32r/m32r2.exp
@@ -2,4 +2,5 @@
 
 if [istarget m32r*-*-*] {
     run_dump_test "m32r2"
+    run_dump_test "parallel-2"
 }
diff --git a/gas/testsuite/gas/m32r/parallel-2.d b/gas/testsuite/gas/m32r/parallel-2.d
new file mode 100644
index 000000000000..5638c33f02e1
--- /dev/null
+++ b/gas/testsuite/gas/m32r/parallel-2.d
@@ -0,0 +1,10 @@
+#as: -m32r2 -O
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <test>:
+   0:	04 a5 24 46 	add r4,r5 -> st r4,@r6
+   4:	7c ff c6 04 	bc 0 <test> \|\| addi r6,[#]4
diff --git a/gas/testsuite/gas/m32r/parallel-2.s b/gas/testsuite/gas/m32r/parallel-2.s
new file mode 100644
index 000000000000..7ea40c2e0518
--- /dev/null
+++ b/gas/testsuite/gas/m32r/parallel-2.s
@@ -0,0 +1,7 @@
+	.text
+test:
+        add r4,r5
+        st r4,@(r6)
+        addi r6,#4
+        .debugsym .LM568
+        bc.s test
diff --git a/gas/testsuite/gas/m32r/pic.exp b/gas/testsuite/gas/m32r/pic.exp
index 391a780aba61..1b61441e3ed1 100644
--- a/gas/testsuite/gas/m32r/pic.exp
+++ b/gas/testsuite/gas/m32r/pic.exp
@@ -2,4 +2,5 @@
 
 if [istarget m32r*-*-*] {
     run_dump_test "pic"
+    run_dump_test "pic2"
 }
diff --git a/gas/testsuite/gas/m32r/pic2.d b/gas/testsuite/gas/m32r/pic2.d
new file mode 100644
index 000000000000..5159ad3f0f48
--- /dev/null
+++ b/gas/testsuite/gas/m32r/pic2.d
@@ -0,0 +1,58 @@
+#objdump: -dr
+#name: pic2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <pic_gotpc>:
+   0:	7e 01 f0 00 	bl 4 <pic_gotpc\+0x4> \|\| nop
+   4:	ec 00 00 00 	ld24 r12,0 <pic_gotpc>
+			4: R_M32R_GOTPC24	_GLOBAL_OFFSET_TABLE_
+   8:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+000c <pic_gotpc_slo>:
+   c:	7e 01 f0 00 	bl 10 <pic_gotpc_slo\+0x4> \|\| nop
+  10:	dc c0 00 00 	seth r12,[#]0x0
+			10: R_M32R_GOTPC_HI_SLO	_GLOBAL_OFFSET_TABLE_
+  14:	8c ac 00 00 	add3 r12,r12,[#]0
+			14: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+  18:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+001c <pic_gotpc_ulo>:
+  1c:	7e 01 f0 00 	bl 20 <pic_gotpc_ulo\+0x4> \|\| nop
+  20:	dc c0 00 00 	seth r12,[#]0x0
+			20: R_M32R_GOTPC_HI_ULO	_GLOBAL_OFFSET_TABLE_
+  24:	8c ec 00 00 	or3 r12,r12,[#]0x0
+			24: R_M32R_GOTPC_LO	_GLOBAL_OFFSET_TABLE_\+0x4
+  28:	0c ae f0 00 	add r12,lr \|\| nop
+
+0+002c <pic_got>:
+  2c:	e0 00 00 00 	ld24 r0,0 <pic_gotpc>
+			2c: R_M32R_GOTOFF	sym
+
+0+0030 <pic_got16>:
+  30:	dc c0 00 00 	seth r12,[#]0x0
+			30: R_M32R_GOT16_HI_SLO	sym2
+  34:	8c ac 00 00 	add3 r12,r12,[#]0
+			34: R_M32R_GOT16_LO	sym2
+  38:	dc c0 00 00 	seth r12,[#]0x0
+			38: R_M32R_GOTOFF_HI_ULO	sym2
+  3c:	8c ec 00 00 	or3 r12,r12,[#]0x0
+			3c: R_M32R_GOT16_LO	sym2
+
+0+0040 <pic_plt>:
+  40:	fe 00 00 00 	bl 40 <pic_plt>
+			40: R_M32R_26_PLTREL	func
+
+0+0044 <gotoff>:
+  44:	e0 00 00 00 	ld24 r0,0 <pic_gotpc>
+			44: R_M32R_GOTOFF	.text\+0x44
+  48:	d0 c0 00 00 	seth r0,[#]0x0
+			48: R_M32R_GOTOFF_HI_SLO	.text\+0x44
+  4c:	80 a0 00 00 	add3 r0,r0,[#]0
+			4c: R_M32R_GOTOFF_LO	.text\+0x44
+  50:	d0 c0 00 00 	seth r0,[#]0x0
+			50: R_M32R_GOTOFF_HI_ULO	.text\+0x44
+  54:	80 e0 00 00 	or3 r0,r0,[#]0x0
+			54: R_M32R_GOTOFF_LO	.text\+0x44
diff --git a/gas/testsuite/gas/m32r/pic2.s b/gas/testsuite/gas/m32r/pic2.s
new file mode 100644
index 000000000000..0f3d28585c3f
--- /dev/null
+++ b/gas/testsuite/gas/m32r/pic2.s
@@ -0,0 +1,55 @@
+	.section .text
+# R_M32R_GOTPC24
+pic_gotpc:
+	bl.s .+4
+        ld24 r12,#_GLOBAL_OFFSET_TABLE_
+	add r12,lr
+
+# R_M32R_GOTPC_HI_ULO
+# R_M32R_GOTPC_HI_SLO
+# R_M32R_GOTPC_LO
+pic_gotpc_slo:
+	bl.s .+4
+        seth r12,#shigh(_GLOBAL_OFFSET_TABLE_)
+        add3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+	add r12,lr
+
+pic_gotpc_ulo:
+	bl.s .+4
+        seth r12,#high(_GLOBAL_OFFSET_TABLE_)
+        or3 r12,r12,#low(_GLOBAL_OFFSET_TABLE_+4)
+	add r12,lr
+
+# R_M32R_GOT24
+pic_got:
+	.global sym
+	ld24 r0,#sym@GOTOFF
+
+# R_M32R_GOT16_HI_ULO
+# R_M32R_GOT16_HI_SLO
+# R_M32R_GOT16_LO
+pic_got16:
+	.global sym2
+        seth r12,#shigh(sym2@GOT)
+        add3 r12,r12,#low(sym2@GOT)
+        seth r12,#high(sym2@GOTOFF)
+        or3 r12,r12,#low(sym2@GOT)
+
+# R_M32R_26_PLTREL
+pic_plt:
+	.global func
+	bl func@PLT
+
+# R_M32R_GOTOFF
+gotoff:
+	ld24 r0,#gotoff@GOTOFF
+
+# R_M32R_GOTOFF_HI_ULO
+# R_M32R_GOTOFF_HI_SLO
+# R_M32R_GOTOFF_LO
+        seth r0,#shigh(gotoff@GOTOFF)
+        add3 r0,r0,#low(gotoff@GOTOFF)
+        seth r0,#high(gotoff@GOTOFF)
+        or3 r0,r0,#low(gotoff@GOTOFF)
+
+	.end
diff --git a/gas/testsuite/gas/m32r/rel32-err.s b/gas/testsuite/gas/m32r/rel32-err.s
new file mode 100644
index 000000000000..fe8784e7acec
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32-err.s
@@ -0,0 +1,10 @@
+
+; { dg-do assemble { target m32r-*-* } }
+
+	.text
+	nop
+	nop
+bar:
+	.section .text2
+	.2byte bar - .  ; { dg-error "can't export reloc type 11" } 
+	.byte bar - .  ; { dg-error "can\'t export reloc type 7" } 
diff --git a/gas/testsuite/gas/m32r/rel32-pic.d b/gas/testsuite/gas/m32r/rel32-pic.d
new file mode 100644
index 000000000000..9a27fe9058d4
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32-pic.d
@@ -0,0 +1,13 @@
+#as: -KPIC
+#objdump: -r
+#name: rel32-pic
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[.text2\]:
+OFFSET   TYPE              VALUE 
+00000000 R_M32R_REL32      .text\+0x00000004
+00000008 R_M32R_REL32      .text\+0x00000008
+0000000c R_M32R_REL32      .text
+
+
diff --git a/gas/testsuite/gas/m32r/rel32-pic.s b/gas/testsuite/gas/m32r/rel32-pic.s
new file mode 100644
index 000000000000..488c3ea2c4c9
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32-pic.s
@@ -0,0 +1,12 @@
+	.text
+	nop
+	nop
+bar:
+	.section .text2
+	.4byte bar - .
+label:
+	nop
+	nop
+	.4byte bar - label
+	.4byte bar - label2
+label2:
diff --git a/gas/testsuite/gas/m32r/rel32.d b/gas/testsuite/gas/m32r/rel32.d
new file mode 100644
index 000000000000..abfe1363e6cc
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -r
+#name: rel32
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR \[.text2\]:
+OFFSET   TYPE              VALUE 
+00000000 R_M32R_REL32      .text\+0x00000004
+00000008 R_M32R_REL32      .text\+0x00000008
+0000000c R_M32R_REL32      .text
+
+
diff --git a/gas/testsuite/gas/m32r/rel32.exp b/gas/testsuite/gas/m32r/rel32.exp
new file mode 100644
index 000000000000..1866217e1438
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32.exp
@@ -0,0 +1,6 @@
+# M32R R_M32R_REL32 testcases
+
+if [istarget m32r*-*-*] {
+    run_dump_test "rel32"
+    run_dump_test "rel32-pic"
+}
diff --git a/gas/testsuite/gas/m32r/rel32.s b/gas/testsuite/gas/m32r/rel32.s
new file mode 100644
index 000000000000..488c3ea2c4c9
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rel32.s
@@ -0,0 +1,12 @@
+	.text
+	nop
+	nop
+bar:
+	.section .text2
+	.4byte bar - .
+label:
+	nop
+	nop
+	.4byte bar - label
+	.4byte bar - label2
+label2:
diff --git a/gas/testsuite/gas/m32r/rela-1.d b/gas/testsuite/gas/m32r/rela-1.d
new file mode 100644
index 000000000000..9b2dcce936c0
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rela-1.d
@@ -0,0 +1,24 @@
+#as:
+#objdump: -dr
+#name: rela-1
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+0000 <.text>:
+   0:	fe 00 00 00 	bl 0 <.text>
+			0: R_M32R_26_PCREL_RELA	.text2\+0x8
+   4:	fe 00 00 00 	bl 4 <.text\+0x4>
+			4: R_M32R_26_PCREL_RELA	.text2\+0x8
+   8:	7e 00 f0 00 	bl 8 <.text\+0x8> \|\| nop
+			8: R_M32R_10_PCREL_RELA	.text2\+0x8
+   c:	b0 90 00 00 	bnez r0,c <.text\+0xc>
+			c: R_M32R_18_PCREL_RELA	.text2\+0x8
+  10:	10 80 7e 00 	mv r0,r0 -> bl 10 <.text\+0x10>
+			12: R_M32R_10_PCREL_RELA	.text2\+0x8
+Disassembly of section .text2:
+
+0+0000 <label-0x8>:
+   0:	70 00 70 00 	nop -> nop
+   4:	70 00 70 00 	nop -> nop
diff --git a/gas/testsuite/gas/m32r/rela-1.s b/gas/testsuite/gas/m32r/rela-1.s
new file mode 100644
index 000000000000..4759a2c23769
--- /dev/null
+++ b/gas/testsuite/gas/m32r/rela-1.s
@@ -0,0 +1,18 @@
+
+	.section .text
+	bl	label
+	bl.l	label
+	bl.s	label
+	bnez	r0,label
+	mv	r0,r0
+	bl.s	label
+
+	.section .text2, "ax" 
+	nop
+	nop
+	nop
+	nop
+label:
+	.end
+
+
diff --git a/gas/testsuite/gas/m32r/relax-1.d b/gas/testsuite/gas/m32r/relax-1.d
index 64f906ce8823..36570d1962d3 100644
--- a/gas/testsuite/gas/m32r/relax-1.d
+++ b/gas/testsuite/gas/m32r/relax-1.d
@@ -14,5 +14,5 @@ Disassembly of section .text:
 Disassembly of section .branch:
 
 0* <branch>:
- *0:	ff 00 00 01 	bra 4 <Work>
-[ 	]*0: R_M32R_26_PCREL_RELA	.text
+ *0:	ff 00 00 00 	bra 0 <branch>
+[ 	]*0: R_M32R_26_PCREL_RELA	.text\+0x4
diff --git a/gas/testsuite/gas/m32r/seth.d b/gas/testsuite/gas/m32r/seth.d
new file mode 100644
index 000000000000..fd792e557996
--- /dev/null
+++ b/gas/testsuite/gas/m32r/seth.d
@@ -0,0 +1,8 @@
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+000 <.text>:
+   0:	d0 c0 00 00 	seth r0,[#]0x0
diff --git a/gas/testsuite/gas/m32r/seth.s b/gas/testsuite/gas/m32r/seth.s
new file mode 100644
index 000000000000..32160a3759d8
--- /dev/null
+++ b/gas/testsuite/gas/m32r/seth.s
@@ -0,0 +1,3 @@
+	.text
+	seth	r0, #shigh(0xffff8000)
+	.end
diff --git a/gas/testsuite/gas/m68hc11/m68hc11.exp b/gas/testsuite/gas/m68hc11/m68hc11.exp
index 2bfa8803aab5..89ad226dded7 100644
--- a/gas/testsuite/gas/m68hc11/m68hc11.exp
+++ b/gas/testsuite/gas/m68hc11/m68hc11.exp
@@ -43,7 +43,7 @@ proc gas_m68hc11_message { kind options line expect } {
     regsub -all "\n" "$line: $expect" " " title
 
     # Make a file containing the instructions to assemble.
-    set fd [open "$srcdir/$subdir/tst-m68hc1x.s" "w"];
+    set fd [open "$srcdir/$subdir/tst-m68hc1x.s" "w"]
     puts -nonewline $fd "$line"
     close $fd
 
@@ -153,15 +153,12 @@ gas_m68hc11_error "-m68hc12" "movb 2,x,bar,pc\nbar=300\n" \
 gas_m68hc11_error "-m68hc12" "movb bar,pc,2,x\nbar=300\n" \
     "Offset out of 5-bit range for movw/movb insn: 300"
 
-setup_xfail m6811-*-*
-setup_xfail m6812-*-*
-
 # ------------------
 # Specific commands
 gas_m68hc11_warning "" ".mode \"bar\"\n" "Invalid mode: .bar."
 gas_m68hc11_error "" ".relax 23\n" "bad .relax format"
 gas_m68hc11_error "" ".relax bar-23\n" "bad .relax format"
-gas_m68hc11_warning "" ".far bar bar\n" "rest of line ignored"
+gas_m68hc11_error "" ".far bar bar\n" "junk at end of line"
 
 
 run_dump_test insns
diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp
index d28f9f66a2dc..9516b1ab1dfc 100644
--- a/gas/testsuite/gas/m68k/all.exp
+++ b/gas/testsuite/gas/m68k/all.exp
@@ -35,6 +35,11 @@ if [istarget m68*-*-*] then {
     run_dump_test link
     run_dump_test fmoveml
     run_dump_test mcf-mov3q
+    run_dump_test mode5
+    run_dump_test mcf-mac
+    run_dump_test mcf-emac
+    run_dump_test mcf-fpu
+    run_dump_test arch-cpu-1
 
     set testname "68000 operands"
     gas_run "operands.s" "-m68000" "2>err.out"
diff --git a/gas/testsuite/gas/m68k/arch-cpu-1.d b/gas/testsuite/gas/m68k/arch-cpu-1.d
new file mode 100644
index 000000000000..421010d08392
--- /dev/null
+++ b/gas/testsuite/gas/m68k/arch-cpu-1.d
@@ -0,0 +1,11 @@
+#name: arch-cpu-1
+#objdump: -dp
+
+
+.*:     file format elf32-m68k
+private flags = 21: \[isa A\] \[nodiv\] \[emac\]
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	a241 0280      	macw %d1l,%a1u,<<,%acc0
diff --git a/gas/testsuite/gas/m68k/arch-cpu-1.s b/gas/testsuite/gas/m68k/arch-cpu-1.s
new file mode 100644
index 000000000000..48d621bd69b6
--- /dev/null
+++ b/gas/testsuite/gas/m68k/arch-cpu-1.s
@@ -0,0 +1,4 @@
+	.arch  isaa,no-div,emac
+	.cpu 5329
+
+	mac.w   %d1l,%a1u,<<,%acc0
diff --git a/gas/testsuite/gas/m68k/mcf-emac.d b/gas/testsuite/gas/m68k/mcf-emac.d
new file mode 100644
index 000000000000..4651d48fd75e
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-emac.d
@@ -0,0 +1,6654 @@
+#name: mcf-emac
+#objdump: -d --architecture=m68k:cfv4e
+#as: -mcfv4e
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+       0:	a241 0280      	macw %d1l,%a1u,<<,%acc0
+       4:	a2d0 d281      	macw %d1l,%a5u,<<,%a0@,%a1,%acc0
+       8:	a490 b2a5      	macw %d5l,%a3u,<<,%a0@&,%d2,%acc0
+       c:	a13c 00bc 614e 	movel #12345678,%acc0
+      12:	a301           	movel %d1,%acc1
+      14:	a33c 00bc 614e 	movel #12345678,%acc1
+      1a:	a53c 00bc 614e 	movel #12345678,%acc2
+      20:	a309           	movel %a1,%acc1
+      22:	a73c 00bc 614e 	movel #12345678,%acc3
+      28:	a8c3 0640      	macw %d3u,%a4l,>>,%acc1
+      2c:	acc5 0040      	macw %d5u,%a6l,%acc1
+      30:	a602 0800      	macl %d2,%d3,%acc0
+      34:	a682 0800      	macl %d2,%d3,%acc1
+      38:	a602 0810      	macl %d2,%d3,%acc2
+      3c:	a682 0810      	macl %d2,%d3,%acc3
+      40:	a1c1           	movclrl %acc0,%d1
+      42:	a3ca           	movclrl %acc1,%a2
+      44:	a5c3           	movclrl %acc2,%d3
+      46:	a7cd           	movclrl %acc3,%a5
+      48:	a381           	movel %acc1,%d1
+      4a:	a78b           	movel %acc3,%a3
+      4c:	a185           	movel %acc0,%d5
+      4e:	a38f           	movel %acc1,%sp
+      50:	a110           	movel %acc0,%acc0
+      52:	a310           	movel %acc0,%acc1
+      54:	a510           	movel %acc0,%acc2
+      56:	a710           	movel %acc0,%acc3
+      58:	a111           	movel %acc1,%acc0
+      5a:	a311           	movel %acc1,%acc1
+      5c:	a511           	movel %acc1,%acc2
+      5e:	a711           	movel %acc1,%acc3
+      60:	a112           	movel %acc2,%acc0
+      62:	a312           	movel %acc2,%acc1
+      64:	a512           	movel %acc2,%acc2
+      66:	a712           	movel %acc2,%acc3
+      68:	a113           	movel %acc3,%acc0
+      6a:	a313           	movel %acc3,%acc1
+      6c:	a513           	movel %acc3,%acc2
+      6e:	a713           	movel %acc3,%acc3
+      70:	ab88           	movel %accext01,%a0
+      72:	af8f           	movel %accext23,%sp
+      74:	a180           	movel %acc0,%d0
+      76:	a389           	movel %acc1,%a1
+      78:	a582           	movel %acc2,%d2
+      7a:	a78b           	movel %acc3,%a3
+      7c:	a4c9 0080      	macw %a1l,%a2u,%acc1
+      80:	a449 0090      	macw %a1l,%a2u,%acc2
+      84:	a4c9 0280      	macw %a1l,%a2u,<<,%acc1
+      88:	a449 0290      	macw %a1l,%a2u,<<,%acc2
+      8c:	a4c9 0680      	macw %a1l,%a2u,>>,%acc1
+      90:	a449 0690      	macw %a1l,%a2u,>>,%acc2
+      94:	a4c9 0280      	macw %a1l,%a2u,<<,%acc1
+      98:	a449 0290      	macw %a1l,%a2u,<<,%acc2
+      9c:	a4c9 0680      	macw %a1l,%a2u,>>,%acc1
+      a0:	a449 0690      	macw %a1l,%a2u,>>,%acc2
+      a4:	a689 0000      	macw %a1l,%d3l,%acc1
+      a8:	a609 0010      	macw %a1l,%d3l,%acc2
+      ac:	a689 0200      	macw %a1l,%d3l,<<,%acc1
+      b0:	a609 0210      	macw %a1l,%d3l,<<,%acc2
+      b4:	a689 0600      	macw %a1l,%d3l,>>,%acc1
+      b8:	a609 0610      	macw %a1l,%d3l,>>,%acc2
+      bc:	a689 0200      	macw %a1l,%d3l,<<,%acc1
+      c0:	a609 0210      	macw %a1l,%d3l,<<,%acc2
+      c4:	a689 0600      	macw %a1l,%d3l,>>,%acc1
+      c8:	a609 0610      	macw %a1l,%d3l,>>,%acc2
+      cc:	aec9 0080      	macw %a1l,%a7u,%acc1
+      d0:	ae49 0090      	macw %a1l,%a7u,%acc2
+      d4:	aec9 0280      	macw %a1l,%a7u,<<,%acc1
+      d8:	ae49 0290      	macw %a1l,%a7u,<<,%acc2
+      dc:	aec9 0680      	macw %a1l,%a7u,>>,%acc1
+      e0:	ae49 0690      	macw %a1l,%a7u,>>,%acc2
+      e4:	aec9 0280      	macw %a1l,%a7u,<<,%acc1
+      e8:	ae49 0290      	macw %a1l,%a7u,<<,%acc2
+      ec:	aec9 0680      	macw %a1l,%a7u,>>,%acc1
+      f0:	ae49 0690      	macw %a1l,%a7u,>>,%acc2
+      f4:	a289 0000      	macw %a1l,%d1l,%acc1
+      f8:	a209 0010      	macw %a1l,%d1l,%acc2
+      fc:	a289 0200      	macw %a1l,%d1l,<<,%acc1
+     100:	a209 0210      	macw %a1l,%d1l,<<,%acc2
+     104:	a289 0600      	macw %a1l,%d1l,>>,%acc1
+     108:	a209 0610      	macw %a1l,%d1l,>>,%acc2
+     10c:	a289 0200      	macw %a1l,%d1l,<<,%acc1
+     110:	a209 0210      	macw %a1l,%d1l,<<,%acc2
+     114:	a289 0600      	macw %a1l,%d1l,>>,%acc1
+     118:	a209 0610      	macw %a1l,%d1l,>>,%acc2
+     11c:	a4c2 00c0      	macw %d2u,%a2u,%acc1
+     120:	a442 00d0      	macw %d2u,%a2u,%acc2
+     124:	a4c2 02c0      	macw %d2u,%a2u,<<,%acc1
+     128:	a442 02d0      	macw %d2u,%a2u,<<,%acc2
+     12c:	a4c2 06c0      	macw %d2u,%a2u,>>,%acc1
+     130:	a442 06d0      	macw %d2u,%a2u,>>,%acc2
+     134:	a4c2 02c0      	macw %d2u,%a2u,<<,%acc1
+     138:	a442 02d0      	macw %d2u,%a2u,<<,%acc2
+     13c:	a4c2 06c0      	macw %d2u,%a2u,>>,%acc1
+     140:	a442 06d0      	macw %d2u,%a2u,>>,%acc2
+     144:	a682 0040      	macw %d2u,%d3l,%acc1
+     148:	a602 0050      	macw %d2u,%d3l,%acc2
+     14c:	a682 0240      	macw %d2u,%d3l,<<,%acc1
+     150:	a602 0250      	macw %d2u,%d3l,<<,%acc2
+     154:	a682 0640      	macw %d2u,%d3l,>>,%acc1
+     158:	a602 0650      	macw %d2u,%d3l,>>,%acc2
+     15c:	a682 0240      	macw %d2u,%d3l,<<,%acc1
+     160:	a602 0250      	macw %d2u,%d3l,<<,%acc2
+     164:	a682 0640      	macw %d2u,%d3l,>>,%acc1
+     168:	a602 0650      	macw %d2u,%d3l,>>,%acc2
+     16c:	aec2 00c0      	macw %d2u,%a7u,%acc1
+     170:	ae42 00d0      	macw %d2u,%a7u,%acc2
+     174:	aec2 02c0      	macw %d2u,%a7u,<<,%acc1
+     178:	ae42 02d0      	macw %d2u,%a7u,<<,%acc2
+     17c:	aec2 06c0      	macw %d2u,%a7u,>>,%acc1
+     180:	ae42 06d0      	macw %d2u,%a7u,>>,%acc2
+     184:	aec2 02c0      	macw %d2u,%a7u,<<,%acc1
+     188:	ae42 02d0      	macw %d2u,%a7u,<<,%acc2
+     18c:	aec2 06c0      	macw %d2u,%a7u,>>,%acc1
+     190:	ae42 06d0      	macw %d2u,%a7u,>>,%acc2
+     194:	a282 0040      	macw %d2u,%d1l,%acc1
+     198:	a202 0050      	macw %d2u,%d1l,%acc2
+     19c:	a282 0240      	macw %d2u,%d1l,<<,%acc1
+     1a0:	a202 0250      	macw %d2u,%d1l,<<,%acc2
+     1a4:	a282 0640      	macw %d2u,%d1l,>>,%acc1
+     1a8:	a202 0650      	macw %d2u,%d1l,>>,%acc2
+     1ac:	a282 0240      	macw %d2u,%d1l,<<,%acc1
+     1b0:	a202 0250      	macw %d2u,%d1l,<<,%acc2
+     1b4:	a282 0640      	macw %d2u,%d1l,>>,%acc1
+     1b8:	a202 0650      	macw %d2u,%d1l,>>,%acc2
+     1bc:	a4cd 0080      	macw %a5l,%a2u,%acc1
+     1c0:	a44d 0090      	macw %a5l,%a2u,%acc2
+     1c4:	a4cd 0280      	macw %a5l,%a2u,<<,%acc1
+     1c8:	a44d 0290      	macw %a5l,%a2u,<<,%acc2
+     1cc:	a4cd 0680      	macw %a5l,%a2u,>>,%acc1
+     1d0:	a44d 0690      	macw %a5l,%a2u,>>,%acc2
+     1d4:	a4cd 0280      	macw %a5l,%a2u,<<,%acc1
+     1d8:	a44d 0290      	macw %a5l,%a2u,<<,%acc2
+     1dc:	a4cd 0680      	macw %a5l,%a2u,>>,%acc1
+     1e0:	a44d 0690      	macw %a5l,%a2u,>>,%acc2
+     1e4:	a68d 0000      	macw %a5l,%d3l,%acc1
+     1e8:	a60d 0010      	macw %a5l,%d3l,%acc2
+     1ec:	a68d 0200      	macw %a5l,%d3l,<<,%acc1
+     1f0:	a60d 0210      	macw %a5l,%d3l,<<,%acc2
+     1f4:	a68d 0600      	macw %a5l,%d3l,>>,%acc1
+     1f8:	a60d 0610      	macw %a5l,%d3l,>>,%acc2
+     1fc:	a68d 0200      	macw %a5l,%d3l,<<,%acc1
+     200:	a60d 0210      	macw %a5l,%d3l,<<,%acc2
+     204:	a68d 0600      	macw %a5l,%d3l,>>,%acc1
+     208:	a60d 0610      	macw %a5l,%d3l,>>,%acc2
+     20c:	aecd 0080      	macw %a5l,%a7u,%acc1
+     210:	ae4d 0090      	macw %a5l,%a7u,%acc2
+     214:	aecd 0280      	macw %a5l,%a7u,<<,%acc1
+     218:	ae4d 0290      	macw %a5l,%a7u,<<,%acc2
+     21c:	aecd 0680      	macw %a5l,%a7u,>>,%acc1
+     220:	ae4d 0690      	macw %a5l,%a7u,>>,%acc2
+     224:	aecd 0280      	macw %a5l,%a7u,<<,%acc1
+     228:	ae4d 0290      	macw %a5l,%a7u,<<,%acc2
+     22c:	aecd 0680      	macw %a5l,%a7u,>>,%acc1
+     230:	ae4d 0690      	macw %a5l,%a7u,>>,%acc2
+     234:	a28d 0000      	macw %a5l,%d1l,%acc1
+     238:	a20d 0010      	macw %a5l,%d1l,%acc2
+     23c:	a28d 0200      	macw %a5l,%d1l,<<,%acc1
+     240:	a20d 0210      	macw %a5l,%d1l,<<,%acc2
+     244:	a28d 0600      	macw %a5l,%d1l,>>,%acc1
+     248:	a20d 0610      	macw %a5l,%d1l,>>,%acc2
+     24c:	a28d 0200      	macw %a5l,%d1l,<<,%acc1
+     250:	a20d 0210      	macw %a5l,%d1l,<<,%acc2
+     254:	a28d 0600      	macw %a5l,%d1l,>>,%acc1
+     258:	a20d 0610      	macw %a5l,%d1l,>>,%acc2
+     25c:	a4c6 00c0      	macw %d6u,%a2u,%acc1
+     260:	a446 00d0      	macw %d6u,%a2u,%acc2
+     264:	a4c6 02c0      	macw %d6u,%a2u,<<,%acc1
+     268:	a446 02d0      	macw %d6u,%a2u,<<,%acc2
+     26c:	a4c6 06c0      	macw %d6u,%a2u,>>,%acc1
+     270:	a446 06d0      	macw %d6u,%a2u,>>,%acc2
+     274:	a4c6 02c0      	macw %d6u,%a2u,<<,%acc1
+     278:	a446 02d0      	macw %d6u,%a2u,<<,%acc2
+     27c:	a4c6 06c0      	macw %d6u,%a2u,>>,%acc1
+     280:	a446 06d0      	macw %d6u,%a2u,>>,%acc2
+     284:	a686 0040      	macw %d6u,%d3l,%acc1
+     288:	a606 0050      	macw %d6u,%d3l,%acc2
+     28c:	a686 0240      	macw %d6u,%d3l,<<,%acc1
+     290:	a606 0250      	macw %d6u,%d3l,<<,%acc2
+     294:	a686 0640      	macw %d6u,%d3l,>>,%acc1
+     298:	a606 0650      	macw %d6u,%d3l,>>,%acc2
+     29c:	a686 0240      	macw %d6u,%d3l,<<,%acc1
+     2a0:	a606 0250      	macw %d6u,%d3l,<<,%acc2
+     2a4:	a686 0640      	macw %d6u,%d3l,>>,%acc1
+     2a8:	a606 0650      	macw %d6u,%d3l,>>,%acc2
+     2ac:	aec6 00c0      	macw %d6u,%a7u,%acc1
+     2b0:	ae46 00d0      	macw %d6u,%a7u,%acc2
+     2b4:	aec6 02c0      	macw %d6u,%a7u,<<,%acc1
+     2b8:	ae46 02d0      	macw %d6u,%a7u,<<,%acc2
+     2bc:	aec6 06c0      	macw %d6u,%a7u,>>,%acc1
+     2c0:	ae46 06d0      	macw %d6u,%a7u,>>,%acc2
+     2c4:	aec6 02c0      	macw %d6u,%a7u,<<,%acc1
+     2c8:	ae46 02d0      	macw %d6u,%a7u,<<,%acc2
+     2cc:	aec6 06c0      	macw %d6u,%a7u,>>,%acc1
+     2d0:	ae46 06d0      	macw %d6u,%a7u,>>,%acc2
+     2d4:	a286 0040      	macw %d6u,%d1l,%acc1
+     2d8:	a206 0050      	macw %d6u,%d1l,%acc2
+     2dc:	a286 0240      	macw %d6u,%d1l,<<,%acc1
+     2e0:	a206 0250      	macw %d6u,%d1l,<<,%acc2
+     2e4:	a286 0640      	macw %d6u,%d1l,>>,%acc1
+     2e8:	a206 0650      	macw %d6u,%d1l,>>,%acc2
+     2ec:	a286 0240      	macw %d6u,%d1l,<<,%acc1
+     2f0:	a206 0250      	macw %d6u,%d1l,<<,%acc2
+     2f4:	a286 0640      	macw %d6u,%d1l,>>,%acc1
+     2f8:	a206 0650      	macw %d6u,%d1l,>>,%acc2
+     2fc:	a213 a089      	macw %a1l,%a2u,%a3@,%d1,%acc1
+     300:	a293 a099      	macw %a1l,%a2u,%a3@,%d1,%acc2
+     304:	a653 a089      	macw %a1l,%a2u,%a3@,%a3,%acc1
+     308:	a6d3 a099      	macw %a1l,%a2u,%a3@,%a3,%acc2
+     30c:	a413 a089      	macw %a1l,%a2u,%a3@,%d2,%acc1
+     310:	a493 a099      	macw %a1l,%a2u,%a3@,%d2,%acc2
+     314:	ae53 a089      	macw %a1l,%a2u,%a3@,%sp,%acc1
+     318:	aed3 a099      	macw %a1l,%a2u,%a3@,%sp,%acc2
+     31c:	a213 a0a9      	macw %a1l,%a2u,%a3@&,%d1,%acc1
+     320:	a293 a0b9      	macw %a1l,%a2u,%a3@&,%d1,%acc2
+     324:	a653 a0a9      	macw %a1l,%a2u,%a3@&,%a3,%acc1
+     328:	a6d3 a0b9      	macw %a1l,%a2u,%a3@&,%a3,%acc2
+     32c:	a413 a0a9      	macw %a1l,%a2u,%a3@&,%d2,%acc1
+     330:	a493 a0b9      	macw %a1l,%a2u,%a3@&,%d2,%acc2
+     334:	ae53 a0a9      	macw %a1l,%a2u,%a3@&,%sp,%acc1
+     338:	aed3 a0b9      	macw %a1l,%a2u,%a3@&,%sp,%acc2
+     33c:	a21a a089      	macw %a1l,%a2u,%a2@\+,%d1,%acc1
+     340:	a29a a099      	macw %a1l,%a2u,%a2@\+,%d1,%acc2
+     344:	a65a a089      	macw %a1l,%a2u,%a2@\+,%a3,%acc1
+     348:	a6da a099      	macw %a1l,%a2u,%a2@\+,%a3,%acc2
+     34c:	a41a a089      	macw %a1l,%a2u,%a2@\+,%d2,%acc1
+     350:	a49a a099      	macw %a1l,%a2u,%a2@\+,%d2,%acc2
+     354:	ae5a a089      	macw %a1l,%a2u,%a2@\+,%sp,%acc1
+     358:	aeda a099      	macw %a1l,%a2u,%a2@\+,%sp,%acc2
+     35c:	a21a a0a9      	macw %a1l,%a2u,%a2@\+&,%d1,%acc1
+     360:	a29a a0b9      	macw %a1l,%a2u,%a2@\+&,%d1,%acc2
+     364:	a65a a0a9      	macw %a1l,%a2u,%a2@\+&,%a3,%acc1
+     368:	a6da a0b9      	macw %a1l,%a2u,%a2@\+&,%a3,%acc2
+     36c:	a41a a0a9      	macw %a1l,%a2u,%a2@\+&,%d2,%acc1
+     370:	a49a a0b9      	macw %a1l,%a2u,%a2@\+&,%d2,%acc2
+     374:	ae5a a0a9      	macw %a1l,%a2u,%a2@\+&,%sp,%acc1
+     378:	aeda a0b9      	macw %a1l,%a2u,%a2@\+&,%sp,%acc2
+     37c:	a22e a089 000a 	macw %a1l,%a2u,%fp@\(10\),%d1,%acc1
+     382:	a2ae a099 000a 	macw %a1l,%a2u,%fp@\(10\),%d1,%acc2
+     388:	a66e a089 000a 	macw %a1l,%a2u,%fp@\(10\),%a3,%acc1
+     38e:	a6ee a099 000a 	macw %a1l,%a2u,%fp@\(10\),%a3,%acc2
+     394:	a42e a089 000a 	macw %a1l,%a2u,%fp@\(10\),%d2,%acc1
+     39a:	a4ae a099 000a 	macw %a1l,%a2u,%fp@\(10\),%d2,%acc2
+     3a0:	ae6e a089 000a 	macw %a1l,%a2u,%fp@\(10\),%sp,%acc1
+     3a6:	aeee a099 000a 	macw %a1l,%a2u,%fp@\(10\),%sp,%acc2
+     3ac:	a22e a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d1,%acc1
+     3b2:	a2ae a0b9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d1,%acc2
+     3b8:	a66e a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%a3,%acc1
+     3be:	a6ee a0b9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%a3,%acc2
+     3c4:	a42e a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d2,%acc1
+     3ca:	a4ae a0b9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d2,%acc2
+     3d0:	ae6e a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%sp,%acc1
+     3d6:	aeee a0b9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%sp,%acc2
+     3dc:	a221 a089      	macw %a1l,%a2u,%a1@-,%d1,%acc1
+     3e0:	a2a1 a099      	macw %a1l,%a2u,%a1@-,%d1,%acc2
+     3e4:	a661 a089      	macw %a1l,%a2u,%a1@-,%a3,%acc1
+     3e8:	a6e1 a099      	macw %a1l,%a2u,%a1@-,%a3,%acc2
+     3ec:	a421 a089      	macw %a1l,%a2u,%a1@-,%d2,%acc1
+     3f0:	a4a1 a099      	macw %a1l,%a2u,%a1@-,%d2,%acc2
+     3f4:	ae61 a089      	macw %a1l,%a2u,%a1@-,%sp,%acc1
+     3f8:	aee1 a099      	macw %a1l,%a2u,%a1@-,%sp,%acc2
+     3fc:	a221 a0a9      	macw %a1l,%a2u,%a1@-&,%d1,%acc1
+     400:	a2a1 a0b9      	macw %a1l,%a2u,%a1@-&,%d1,%acc2
+     404:	a661 a0a9      	macw %a1l,%a2u,%a1@-&,%a3,%acc1
+     408:	a6e1 a0b9      	macw %a1l,%a2u,%a1@-&,%a3,%acc2
+     40c:	a421 a0a9      	macw %a1l,%a2u,%a1@-&,%d2,%acc1
+     410:	a4a1 a0b9      	macw %a1l,%a2u,%a1@-&,%d2,%acc2
+     414:	ae61 a0a9      	macw %a1l,%a2u,%a1@-&,%sp,%acc1
+     418:	aee1 a0b9      	macw %a1l,%a2u,%a1@-&,%sp,%acc2
+     41c:	a213 a289      	macw %a1l,%a2u,<<,%a3@,%d1,%acc1
+     420:	a293 a299      	macw %a1l,%a2u,<<,%a3@,%d1,%acc2
+     424:	a653 a289      	macw %a1l,%a2u,<<,%a3@,%a3,%acc1
+     428:	a6d3 a299      	macw %a1l,%a2u,<<,%a3@,%a3,%acc2
+     42c:	a413 a289      	macw %a1l,%a2u,<<,%a3@,%d2,%acc1
+     430:	a493 a299      	macw %a1l,%a2u,<<,%a3@,%d2,%acc2
+     434:	ae53 a289      	macw %a1l,%a2u,<<,%a3@,%sp,%acc1
+     438:	aed3 a299      	macw %a1l,%a2u,<<,%a3@,%sp,%acc2
+     43c:	a213 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d1,%acc1
+     440:	a293 a2b9      	macw %a1l,%a2u,<<,%a3@&,%d1,%acc2
+     444:	a653 a2a9      	macw %a1l,%a2u,<<,%a3@&,%a3,%acc1
+     448:	a6d3 a2b9      	macw %a1l,%a2u,<<,%a3@&,%a3,%acc2
+     44c:	a413 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d2,%acc1
+     450:	a493 a2b9      	macw %a1l,%a2u,<<,%a3@&,%d2,%acc2
+     454:	ae53 a2a9      	macw %a1l,%a2u,<<,%a3@&,%sp,%acc1
+     458:	aed3 a2b9      	macw %a1l,%a2u,<<,%a3@&,%sp,%acc2
+     45c:	a21a a289      	macw %a1l,%a2u,<<,%a2@\+,%d1,%acc1
+     460:	a29a a299      	macw %a1l,%a2u,<<,%a2@\+,%d1,%acc2
+     464:	a65a a289      	macw %a1l,%a2u,<<,%a2@\+,%a3,%acc1
+     468:	a6da a299      	macw %a1l,%a2u,<<,%a2@\+,%a3,%acc2
+     46c:	a41a a289      	macw %a1l,%a2u,<<,%a2@\+,%d2,%acc1
+     470:	a49a a299      	macw %a1l,%a2u,<<,%a2@\+,%d2,%acc2
+     474:	ae5a a289      	macw %a1l,%a2u,<<,%a2@\+,%sp,%acc1
+     478:	aeda a299      	macw %a1l,%a2u,<<,%a2@\+,%sp,%acc2
+     47c:	a21a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d1,%acc1
+     480:	a29a a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%d1,%acc2
+     484:	a65a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%a3,%acc1
+     488:	a6da a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%a3,%acc2
+     48c:	a41a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d2,%acc1
+     490:	a49a a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%d2,%acc2
+     494:	ae5a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%sp,%acc1
+     498:	aeda a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%sp,%acc2
+     49c:	a22e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1,%acc1
+     4a2:	a2ae a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1,%acc2
+     4a8:	a66e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3,%acc1
+     4ae:	a6ee a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3,%acc2
+     4b4:	a42e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2,%acc1
+     4ba:	a4ae a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2,%acc2
+     4c0:	ae6e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp,%acc1
+     4c6:	aeee a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp,%acc2
+     4cc:	a22e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+     4d2:	a2ae a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+     4d8:	a66e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+     4de:	a6ee a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+     4e4:	a42e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+     4ea:	a4ae a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+     4f0:	ae6e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+     4f6:	aeee a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+     4fc:	a221 a289      	macw %a1l,%a2u,<<,%a1@-,%d1,%acc1
+     500:	a2a1 a299      	macw %a1l,%a2u,<<,%a1@-,%d1,%acc2
+     504:	a661 a289      	macw %a1l,%a2u,<<,%a1@-,%a3,%acc1
+     508:	a6e1 a299      	macw %a1l,%a2u,<<,%a1@-,%a3,%acc2
+     50c:	a421 a289      	macw %a1l,%a2u,<<,%a1@-,%d2,%acc1
+     510:	a4a1 a299      	macw %a1l,%a2u,<<,%a1@-,%d2,%acc2
+     514:	ae61 a289      	macw %a1l,%a2u,<<,%a1@-,%sp,%acc1
+     518:	aee1 a299      	macw %a1l,%a2u,<<,%a1@-,%sp,%acc2
+     51c:	a221 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d1,%acc1
+     520:	a2a1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%d1,%acc2
+     524:	a661 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%a3,%acc1
+     528:	a6e1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%a3,%acc2
+     52c:	a421 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d2,%acc1
+     530:	a4a1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%d2,%acc2
+     534:	ae61 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%sp,%acc1
+     538:	aee1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%sp,%acc2
+     53c:	a213 a689      	macw %a1l,%a2u,>>,%a3@,%d1,%acc1
+     540:	a293 a699      	macw %a1l,%a2u,>>,%a3@,%d1,%acc2
+     544:	a653 a689      	macw %a1l,%a2u,>>,%a3@,%a3,%acc1
+     548:	a6d3 a699      	macw %a1l,%a2u,>>,%a3@,%a3,%acc2
+     54c:	a413 a689      	macw %a1l,%a2u,>>,%a3@,%d2,%acc1
+     550:	a493 a699      	macw %a1l,%a2u,>>,%a3@,%d2,%acc2
+     554:	ae53 a689      	macw %a1l,%a2u,>>,%a3@,%sp,%acc1
+     558:	aed3 a699      	macw %a1l,%a2u,>>,%a3@,%sp,%acc2
+     55c:	a213 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d1,%acc1
+     560:	a293 a6b9      	macw %a1l,%a2u,>>,%a3@&,%d1,%acc2
+     564:	a653 a6a9      	macw %a1l,%a2u,>>,%a3@&,%a3,%acc1
+     568:	a6d3 a6b9      	macw %a1l,%a2u,>>,%a3@&,%a3,%acc2
+     56c:	a413 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d2,%acc1
+     570:	a493 a6b9      	macw %a1l,%a2u,>>,%a3@&,%d2,%acc2
+     574:	ae53 a6a9      	macw %a1l,%a2u,>>,%a3@&,%sp,%acc1
+     578:	aed3 a6b9      	macw %a1l,%a2u,>>,%a3@&,%sp,%acc2
+     57c:	a21a a689      	macw %a1l,%a2u,>>,%a2@\+,%d1,%acc1
+     580:	a29a a699      	macw %a1l,%a2u,>>,%a2@\+,%d1,%acc2
+     584:	a65a a689      	macw %a1l,%a2u,>>,%a2@\+,%a3,%acc1
+     588:	a6da a699      	macw %a1l,%a2u,>>,%a2@\+,%a3,%acc2
+     58c:	a41a a689      	macw %a1l,%a2u,>>,%a2@\+,%d2,%acc1
+     590:	a49a a699      	macw %a1l,%a2u,>>,%a2@\+,%d2,%acc2
+     594:	ae5a a689      	macw %a1l,%a2u,>>,%a2@\+,%sp,%acc1
+     598:	aeda a699      	macw %a1l,%a2u,>>,%a2@\+,%sp,%acc2
+     59c:	a21a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d1,%acc1
+     5a0:	a29a a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%d1,%acc2
+     5a4:	a65a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%a3,%acc1
+     5a8:	a6da a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%a3,%acc2
+     5ac:	a41a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d2,%acc1
+     5b0:	a49a a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%d2,%acc2
+     5b4:	ae5a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%sp,%acc1
+     5b8:	aeda a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%sp,%acc2
+     5bc:	a22e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1,%acc1
+     5c2:	a2ae a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1,%acc2
+     5c8:	a66e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3,%acc1
+     5ce:	a6ee a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3,%acc2
+     5d4:	a42e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2,%acc1
+     5da:	a4ae a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2,%acc2
+     5e0:	ae6e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp,%acc1
+     5e6:	aeee a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp,%acc2
+     5ec:	a22e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+     5f2:	a2ae a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+     5f8:	a66e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+     5fe:	a6ee a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+     604:	a42e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+     60a:	a4ae a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+     610:	ae6e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+     616:	aeee a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+     61c:	a221 a689      	macw %a1l,%a2u,>>,%a1@-,%d1,%acc1
+     620:	a2a1 a699      	macw %a1l,%a2u,>>,%a1@-,%d1,%acc2
+     624:	a661 a689      	macw %a1l,%a2u,>>,%a1@-,%a3,%acc1
+     628:	a6e1 a699      	macw %a1l,%a2u,>>,%a1@-,%a3,%acc2
+     62c:	a421 a689      	macw %a1l,%a2u,>>,%a1@-,%d2,%acc1
+     630:	a4a1 a699      	macw %a1l,%a2u,>>,%a1@-,%d2,%acc2
+     634:	ae61 a689      	macw %a1l,%a2u,>>,%a1@-,%sp,%acc1
+     638:	aee1 a699      	macw %a1l,%a2u,>>,%a1@-,%sp,%acc2
+     63c:	a221 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d1,%acc1
+     640:	a2a1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%d1,%acc2
+     644:	a661 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%a3,%acc1
+     648:	a6e1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%a3,%acc2
+     64c:	a421 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d2,%acc1
+     650:	a4a1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%d2,%acc2
+     654:	ae61 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%sp,%acc1
+     658:	aee1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%sp,%acc2
+     65c:	a213 a289      	macw %a1l,%a2u,<<,%a3@,%d1,%acc1
+     660:	a293 a299      	macw %a1l,%a2u,<<,%a3@,%d1,%acc2
+     664:	a653 a289      	macw %a1l,%a2u,<<,%a3@,%a3,%acc1
+     668:	a6d3 a299      	macw %a1l,%a2u,<<,%a3@,%a3,%acc2
+     66c:	a413 a289      	macw %a1l,%a2u,<<,%a3@,%d2,%acc1
+     670:	a493 a299      	macw %a1l,%a2u,<<,%a3@,%d2,%acc2
+     674:	ae53 a289      	macw %a1l,%a2u,<<,%a3@,%sp,%acc1
+     678:	aed3 a299      	macw %a1l,%a2u,<<,%a3@,%sp,%acc2
+     67c:	a213 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d1,%acc1
+     680:	a293 a2b9      	macw %a1l,%a2u,<<,%a3@&,%d1,%acc2
+     684:	a653 a2a9      	macw %a1l,%a2u,<<,%a3@&,%a3,%acc1
+     688:	a6d3 a2b9      	macw %a1l,%a2u,<<,%a3@&,%a3,%acc2
+     68c:	a413 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d2,%acc1
+     690:	a493 a2b9      	macw %a1l,%a2u,<<,%a3@&,%d2,%acc2
+     694:	ae53 a2a9      	macw %a1l,%a2u,<<,%a3@&,%sp,%acc1
+     698:	aed3 a2b9      	macw %a1l,%a2u,<<,%a3@&,%sp,%acc2
+     69c:	a21a a289      	macw %a1l,%a2u,<<,%a2@\+,%d1,%acc1
+     6a0:	a29a a299      	macw %a1l,%a2u,<<,%a2@\+,%d1,%acc2
+     6a4:	a65a a289      	macw %a1l,%a2u,<<,%a2@\+,%a3,%acc1
+     6a8:	a6da a299      	macw %a1l,%a2u,<<,%a2@\+,%a3,%acc2
+     6ac:	a41a a289      	macw %a1l,%a2u,<<,%a2@\+,%d2,%acc1
+     6b0:	a49a a299      	macw %a1l,%a2u,<<,%a2@\+,%d2,%acc2
+     6b4:	ae5a a289      	macw %a1l,%a2u,<<,%a2@\+,%sp,%acc1
+     6b8:	aeda a299      	macw %a1l,%a2u,<<,%a2@\+,%sp,%acc2
+     6bc:	a21a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d1,%acc1
+     6c0:	a29a a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%d1,%acc2
+     6c4:	a65a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%a3,%acc1
+     6c8:	a6da a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%a3,%acc2
+     6cc:	a41a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d2,%acc1
+     6d0:	a49a a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%d2,%acc2
+     6d4:	ae5a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%sp,%acc1
+     6d8:	aeda a2b9      	macw %a1l,%a2u,<<,%a2@\+&,%sp,%acc2
+     6dc:	a22e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1,%acc1
+     6e2:	a2ae a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1,%acc2
+     6e8:	a66e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3,%acc1
+     6ee:	a6ee a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3,%acc2
+     6f4:	a42e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2,%acc1
+     6fa:	a4ae a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2,%acc2
+     700:	ae6e a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp,%acc1
+     706:	aeee a299 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp,%acc2
+     70c:	a22e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+     712:	a2ae a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+     718:	a66e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+     71e:	a6ee a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+     724:	a42e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+     72a:	a4ae a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+     730:	ae6e a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+     736:	aeee a2b9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+     73c:	a221 a289      	macw %a1l,%a2u,<<,%a1@-,%d1,%acc1
+     740:	a2a1 a299      	macw %a1l,%a2u,<<,%a1@-,%d1,%acc2
+     744:	a661 a289      	macw %a1l,%a2u,<<,%a1@-,%a3,%acc1
+     748:	a6e1 a299      	macw %a1l,%a2u,<<,%a1@-,%a3,%acc2
+     74c:	a421 a289      	macw %a1l,%a2u,<<,%a1@-,%d2,%acc1
+     750:	a4a1 a299      	macw %a1l,%a2u,<<,%a1@-,%d2,%acc2
+     754:	ae61 a289      	macw %a1l,%a2u,<<,%a1@-,%sp,%acc1
+     758:	aee1 a299      	macw %a1l,%a2u,<<,%a1@-,%sp,%acc2
+     75c:	a221 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d1,%acc1
+     760:	a2a1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%d1,%acc2
+     764:	a661 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%a3,%acc1
+     768:	a6e1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%a3,%acc2
+     76c:	a421 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d2,%acc1
+     770:	a4a1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%d2,%acc2
+     774:	ae61 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%sp,%acc1
+     778:	aee1 a2b9      	macw %a1l,%a2u,<<,%a1@-&,%sp,%acc2
+     77c:	a213 a689      	macw %a1l,%a2u,>>,%a3@,%d1,%acc1
+     780:	a293 a699      	macw %a1l,%a2u,>>,%a3@,%d1,%acc2
+     784:	a653 a689      	macw %a1l,%a2u,>>,%a3@,%a3,%acc1
+     788:	a6d3 a699      	macw %a1l,%a2u,>>,%a3@,%a3,%acc2
+     78c:	a413 a689      	macw %a1l,%a2u,>>,%a3@,%d2,%acc1
+     790:	a493 a699      	macw %a1l,%a2u,>>,%a3@,%d2,%acc2
+     794:	ae53 a689      	macw %a1l,%a2u,>>,%a3@,%sp,%acc1
+     798:	aed3 a699      	macw %a1l,%a2u,>>,%a3@,%sp,%acc2
+     79c:	a213 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d1,%acc1
+     7a0:	a293 a6b9      	macw %a1l,%a2u,>>,%a3@&,%d1,%acc2
+     7a4:	a653 a6a9      	macw %a1l,%a2u,>>,%a3@&,%a3,%acc1
+     7a8:	a6d3 a6b9      	macw %a1l,%a2u,>>,%a3@&,%a3,%acc2
+     7ac:	a413 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d2,%acc1
+     7b0:	a493 a6b9      	macw %a1l,%a2u,>>,%a3@&,%d2,%acc2
+     7b4:	ae53 a6a9      	macw %a1l,%a2u,>>,%a3@&,%sp,%acc1
+     7b8:	aed3 a6b9      	macw %a1l,%a2u,>>,%a3@&,%sp,%acc2
+     7bc:	a21a a689      	macw %a1l,%a2u,>>,%a2@\+,%d1,%acc1
+     7c0:	a29a a699      	macw %a1l,%a2u,>>,%a2@\+,%d1,%acc2
+     7c4:	a65a a689      	macw %a1l,%a2u,>>,%a2@\+,%a3,%acc1
+     7c8:	a6da a699      	macw %a1l,%a2u,>>,%a2@\+,%a3,%acc2
+     7cc:	a41a a689      	macw %a1l,%a2u,>>,%a2@\+,%d2,%acc1
+     7d0:	a49a a699      	macw %a1l,%a2u,>>,%a2@\+,%d2,%acc2
+     7d4:	ae5a a689      	macw %a1l,%a2u,>>,%a2@\+,%sp,%acc1
+     7d8:	aeda a699      	macw %a1l,%a2u,>>,%a2@\+,%sp,%acc2
+     7dc:	a21a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d1,%acc1
+     7e0:	a29a a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%d1,%acc2
+     7e4:	a65a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%a3,%acc1
+     7e8:	a6da a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%a3,%acc2
+     7ec:	a41a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d2,%acc1
+     7f0:	a49a a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%d2,%acc2
+     7f4:	ae5a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%sp,%acc1
+     7f8:	aeda a6b9      	macw %a1l,%a2u,>>,%a2@\+&,%sp,%acc2
+     7fc:	a22e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1,%acc1
+     802:	a2ae a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1,%acc2
+     808:	a66e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3,%acc1
+     80e:	a6ee a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3,%acc2
+     814:	a42e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2,%acc1
+     81a:	a4ae a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2,%acc2
+     820:	ae6e a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp,%acc1
+     826:	aeee a699 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp,%acc2
+     82c:	a22e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+     832:	a2ae a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+     838:	a66e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+     83e:	a6ee a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+     844:	a42e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+     84a:	a4ae a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+     850:	ae6e a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+     856:	aeee a6b9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+     85c:	a221 a689      	macw %a1l,%a2u,>>,%a1@-,%d1,%acc1
+     860:	a2a1 a699      	macw %a1l,%a2u,>>,%a1@-,%d1,%acc2
+     864:	a661 a689      	macw %a1l,%a2u,>>,%a1@-,%a3,%acc1
+     868:	a6e1 a699      	macw %a1l,%a2u,>>,%a1@-,%a3,%acc2
+     86c:	a421 a689      	macw %a1l,%a2u,>>,%a1@-,%d2,%acc1
+     870:	a4a1 a699      	macw %a1l,%a2u,>>,%a1@-,%d2,%acc2
+     874:	ae61 a689      	macw %a1l,%a2u,>>,%a1@-,%sp,%acc1
+     878:	aee1 a699      	macw %a1l,%a2u,>>,%a1@-,%sp,%acc2
+     87c:	a221 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d1,%acc1
+     880:	a2a1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%d1,%acc2
+     884:	a661 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%a3,%acc1
+     888:	a6e1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%a3,%acc2
+     88c:	a421 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d2,%acc1
+     890:	a4a1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%d2,%acc2
+     894:	ae61 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%sp,%acc1
+     898:	aee1 a6b9      	macw %a1l,%a2u,>>,%a1@-&,%sp,%acc2
+     89c:	a213 3009      	macw %a1l,%d3l,%a3@,%d1,%acc1
+     8a0:	a293 3019      	macw %a1l,%d3l,%a3@,%d1,%acc2
+     8a4:	a653 3009      	macw %a1l,%d3l,%a3@,%a3,%acc1
+     8a8:	a6d3 3019      	macw %a1l,%d3l,%a3@,%a3,%acc2
+     8ac:	a413 3009      	macw %a1l,%d3l,%a3@,%d2,%acc1
+     8b0:	a493 3019      	macw %a1l,%d3l,%a3@,%d2,%acc2
+     8b4:	ae53 3009      	macw %a1l,%d3l,%a3@,%sp,%acc1
+     8b8:	aed3 3019      	macw %a1l,%d3l,%a3@,%sp,%acc2
+     8bc:	a213 3029      	macw %a1l,%d3l,%a3@&,%d1,%acc1
+     8c0:	a293 3039      	macw %a1l,%d3l,%a3@&,%d1,%acc2
+     8c4:	a653 3029      	macw %a1l,%d3l,%a3@&,%a3,%acc1
+     8c8:	a6d3 3039      	macw %a1l,%d3l,%a3@&,%a3,%acc2
+     8cc:	a413 3029      	macw %a1l,%d3l,%a3@&,%d2,%acc1
+     8d0:	a493 3039      	macw %a1l,%d3l,%a3@&,%d2,%acc2
+     8d4:	ae53 3029      	macw %a1l,%d3l,%a3@&,%sp,%acc1
+     8d8:	aed3 3039      	macw %a1l,%d3l,%a3@&,%sp,%acc2
+     8dc:	a21a 3009      	macw %a1l,%d3l,%a2@\+,%d1,%acc1
+     8e0:	a29a 3019      	macw %a1l,%d3l,%a2@\+,%d1,%acc2
+     8e4:	a65a 3009      	macw %a1l,%d3l,%a2@\+,%a3,%acc1
+     8e8:	a6da 3019      	macw %a1l,%d3l,%a2@\+,%a3,%acc2
+     8ec:	a41a 3009      	macw %a1l,%d3l,%a2@\+,%d2,%acc1
+     8f0:	a49a 3019      	macw %a1l,%d3l,%a2@\+,%d2,%acc2
+     8f4:	ae5a 3009      	macw %a1l,%d3l,%a2@\+,%sp,%acc1
+     8f8:	aeda 3019      	macw %a1l,%d3l,%a2@\+,%sp,%acc2
+     8fc:	a21a 3029      	macw %a1l,%d3l,%a2@\+&,%d1,%acc1
+     900:	a29a 3039      	macw %a1l,%d3l,%a2@\+&,%d1,%acc2
+     904:	a65a 3029      	macw %a1l,%d3l,%a2@\+&,%a3,%acc1
+     908:	a6da 3039      	macw %a1l,%d3l,%a2@\+&,%a3,%acc2
+     90c:	a41a 3029      	macw %a1l,%d3l,%a2@\+&,%d2,%acc1
+     910:	a49a 3039      	macw %a1l,%d3l,%a2@\+&,%d2,%acc2
+     914:	ae5a 3029      	macw %a1l,%d3l,%a2@\+&,%sp,%acc1
+     918:	aeda 3039      	macw %a1l,%d3l,%a2@\+&,%sp,%acc2
+     91c:	a22e 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%d1,%acc1
+     922:	a2ae 3019 000a 	macw %a1l,%d3l,%fp@\(10\),%d1,%acc2
+     928:	a66e 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%a3,%acc1
+     92e:	a6ee 3019 000a 	macw %a1l,%d3l,%fp@\(10\),%a3,%acc2
+     934:	a42e 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%d2,%acc1
+     93a:	a4ae 3019 000a 	macw %a1l,%d3l,%fp@\(10\),%d2,%acc2
+     940:	ae6e 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%sp,%acc1
+     946:	aeee 3019 000a 	macw %a1l,%d3l,%fp@\(10\),%sp,%acc2
+     94c:	a22e 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d1,%acc1
+     952:	a2ae 3039 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d1,%acc2
+     958:	a66e 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%a3,%acc1
+     95e:	a6ee 3039 000a 	macw %a1l,%d3l,%fp@\(10\)&,%a3,%acc2
+     964:	a42e 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d2,%acc1
+     96a:	a4ae 3039 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d2,%acc2
+     970:	ae6e 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%sp,%acc1
+     976:	aeee 3039 000a 	macw %a1l,%d3l,%fp@\(10\)&,%sp,%acc2
+     97c:	a221 3009      	macw %a1l,%d3l,%a1@-,%d1,%acc1
+     980:	a2a1 3019      	macw %a1l,%d3l,%a1@-,%d1,%acc2
+     984:	a661 3009      	macw %a1l,%d3l,%a1@-,%a3,%acc1
+     988:	a6e1 3019      	macw %a1l,%d3l,%a1@-,%a3,%acc2
+     98c:	a421 3009      	macw %a1l,%d3l,%a1@-,%d2,%acc1
+     990:	a4a1 3019      	macw %a1l,%d3l,%a1@-,%d2,%acc2
+     994:	ae61 3009      	macw %a1l,%d3l,%a1@-,%sp,%acc1
+     998:	aee1 3019      	macw %a1l,%d3l,%a1@-,%sp,%acc2
+     99c:	a221 3029      	macw %a1l,%d3l,%a1@-&,%d1,%acc1
+     9a0:	a2a1 3039      	macw %a1l,%d3l,%a1@-&,%d1,%acc2
+     9a4:	a661 3029      	macw %a1l,%d3l,%a1@-&,%a3,%acc1
+     9a8:	a6e1 3039      	macw %a1l,%d3l,%a1@-&,%a3,%acc2
+     9ac:	a421 3029      	macw %a1l,%d3l,%a1@-&,%d2,%acc1
+     9b0:	a4a1 3039      	macw %a1l,%d3l,%a1@-&,%d2,%acc2
+     9b4:	ae61 3029      	macw %a1l,%d3l,%a1@-&,%sp,%acc1
+     9b8:	aee1 3039      	macw %a1l,%d3l,%a1@-&,%sp,%acc2
+     9bc:	a213 3209      	macw %a1l,%d3l,<<,%a3@,%d1,%acc1
+     9c0:	a293 3219      	macw %a1l,%d3l,<<,%a3@,%d1,%acc2
+     9c4:	a653 3209      	macw %a1l,%d3l,<<,%a3@,%a3,%acc1
+     9c8:	a6d3 3219      	macw %a1l,%d3l,<<,%a3@,%a3,%acc2
+     9cc:	a413 3209      	macw %a1l,%d3l,<<,%a3@,%d2,%acc1
+     9d0:	a493 3219      	macw %a1l,%d3l,<<,%a3@,%d2,%acc2
+     9d4:	ae53 3209      	macw %a1l,%d3l,<<,%a3@,%sp,%acc1
+     9d8:	aed3 3219      	macw %a1l,%d3l,<<,%a3@,%sp,%acc2
+     9dc:	a213 3229      	macw %a1l,%d3l,<<,%a3@&,%d1,%acc1
+     9e0:	a293 3239      	macw %a1l,%d3l,<<,%a3@&,%d1,%acc2
+     9e4:	a653 3229      	macw %a1l,%d3l,<<,%a3@&,%a3,%acc1
+     9e8:	a6d3 3239      	macw %a1l,%d3l,<<,%a3@&,%a3,%acc2
+     9ec:	a413 3229      	macw %a1l,%d3l,<<,%a3@&,%d2,%acc1
+     9f0:	a493 3239      	macw %a1l,%d3l,<<,%a3@&,%d2,%acc2
+     9f4:	ae53 3229      	macw %a1l,%d3l,<<,%a3@&,%sp,%acc1
+     9f8:	aed3 3239      	macw %a1l,%d3l,<<,%a3@&,%sp,%acc2
+     9fc:	a21a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d1,%acc1
+     a00:	a29a 3219      	macw %a1l,%d3l,<<,%a2@\+,%d1,%acc2
+     a04:	a65a 3209      	macw %a1l,%d3l,<<,%a2@\+,%a3,%acc1
+     a08:	a6da 3219      	macw %a1l,%d3l,<<,%a2@\+,%a3,%acc2
+     a0c:	a41a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d2,%acc1
+     a10:	a49a 3219      	macw %a1l,%d3l,<<,%a2@\+,%d2,%acc2
+     a14:	ae5a 3209      	macw %a1l,%d3l,<<,%a2@\+,%sp,%acc1
+     a18:	aeda 3219      	macw %a1l,%d3l,<<,%a2@\+,%sp,%acc2
+     a1c:	a21a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d1,%acc1
+     a20:	a29a 3239      	macw %a1l,%d3l,<<,%a2@\+&,%d1,%acc2
+     a24:	a65a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%a3,%acc1
+     a28:	a6da 3239      	macw %a1l,%d3l,<<,%a2@\+&,%a3,%acc2
+     a2c:	a41a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d2,%acc1
+     a30:	a49a 3239      	macw %a1l,%d3l,<<,%a2@\+&,%d2,%acc2
+     a34:	ae5a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%sp,%acc1
+     a38:	aeda 3239      	macw %a1l,%d3l,<<,%a2@\+&,%sp,%acc2
+     a3c:	a22e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1,%acc1
+     a42:	a2ae 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1,%acc2
+     a48:	a66e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3,%acc1
+     a4e:	a6ee 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3,%acc2
+     a54:	a42e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2,%acc1
+     a5a:	a4ae 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2,%acc2
+     a60:	ae6e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp,%acc1
+     a66:	aeee 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp,%acc2
+     a6c:	a22e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+     a72:	a2ae 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+     a78:	a66e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+     a7e:	a6ee 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+     a84:	a42e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+     a8a:	a4ae 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+     a90:	ae6e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+     a96:	aeee 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+     a9c:	a221 3209      	macw %a1l,%d3l,<<,%a1@-,%d1,%acc1
+     aa0:	a2a1 3219      	macw %a1l,%d3l,<<,%a1@-,%d1,%acc2
+     aa4:	a661 3209      	macw %a1l,%d3l,<<,%a1@-,%a3,%acc1
+     aa8:	a6e1 3219      	macw %a1l,%d3l,<<,%a1@-,%a3,%acc2
+     aac:	a421 3209      	macw %a1l,%d3l,<<,%a1@-,%d2,%acc1
+     ab0:	a4a1 3219      	macw %a1l,%d3l,<<,%a1@-,%d2,%acc2
+     ab4:	ae61 3209      	macw %a1l,%d3l,<<,%a1@-,%sp,%acc1
+     ab8:	aee1 3219      	macw %a1l,%d3l,<<,%a1@-,%sp,%acc2
+     abc:	a221 3229      	macw %a1l,%d3l,<<,%a1@-&,%d1,%acc1
+     ac0:	a2a1 3239      	macw %a1l,%d3l,<<,%a1@-&,%d1,%acc2
+     ac4:	a661 3229      	macw %a1l,%d3l,<<,%a1@-&,%a3,%acc1
+     ac8:	a6e1 3239      	macw %a1l,%d3l,<<,%a1@-&,%a3,%acc2
+     acc:	a421 3229      	macw %a1l,%d3l,<<,%a1@-&,%d2,%acc1
+     ad0:	a4a1 3239      	macw %a1l,%d3l,<<,%a1@-&,%d2,%acc2
+     ad4:	ae61 3229      	macw %a1l,%d3l,<<,%a1@-&,%sp,%acc1
+     ad8:	aee1 3239      	macw %a1l,%d3l,<<,%a1@-&,%sp,%acc2
+     adc:	a213 3609      	macw %a1l,%d3l,>>,%a3@,%d1,%acc1
+     ae0:	a293 3619      	macw %a1l,%d3l,>>,%a3@,%d1,%acc2
+     ae4:	a653 3609      	macw %a1l,%d3l,>>,%a3@,%a3,%acc1
+     ae8:	a6d3 3619      	macw %a1l,%d3l,>>,%a3@,%a3,%acc2
+     aec:	a413 3609      	macw %a1l,%d3l,>>,%a3@,%d2,%acc1
+     af0:	a493 3619      	macw %a1l,%d3l,>>,%a3@,%d2,%acc2
+     af4:	ae53 3609      	macw %a1l,%d3l,>>,%a3@,%sp,%acc1
+     af8:	aed3 3619      	macw %a1l,%d3l,>>,%a3@,%sp,%acc2
+     afc:	a213 3629      	macw %a1l,%d3l,>>,%a3@&,%d1,%acc1
+     b00:	a293 3639      	macw %a1l,%d3l,>>,%a3@&,%d1,%acc2
+     b04:	a653 3629      	macw %a1l,%d3l,>>,%a3@&,%a3,%acc1
+     b08:	a6d3 3639      	macw %a1l,%d3l,>>,%a3@&,%a3,%acc2
+     b0c:	a413 3629      	macw %a1l,%d3l,>>,%a3@&,%d2,%acc1
+     b10:	a493 3639      	macw %a1l,%d3l,>>,%a3@&,%d2,%acc2
+     b14:	ae53 3629      	macw %a1l,%d3l,>>,%a3@&,%sp,%acc1
+     b18:	aed3 3639      	macw %a1l,%d3l,>>,%a3@&,%sp,%acc2
+     b1c:	a21a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d1,%acc1
+     b20:	a29a 3619      	macw %a1l,%d3l,>>,%a2@\+,%d1,%acc2
+     b24:	a65a 3609      	macw %a1l,%d3l,>>,%a2@\+,%a3,%acc1
+     b28:	a6da 3619      	macw %a1l,%d3l,>>,%a2@\+,%a3,%acc2
+     b2c:	a41a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d2,%acc1
+     b30:	a49a 3619      	macw %a1l,%d3l,>>,%a2@\+,%d2,%acc2
+     b34:	ae5a 3609      	macw %a1l,%d3l,>>,%a2@\+,%sp,%acc1
+     b38:	aeda 3619      	macw %a1l,%d3l,>>,%a2@\+,%sp,%acc2
+     b3c:	a21a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d1,%acc1
+     b40:	a29a 3639      	macw %a1l,%d3l,>>,%a2@\+&,%d1,%acc2
+     b44:	a65a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%a3,%acc1
+     b48:	a6da 3639      	macw %a1l,%d3l,>>,%a2@\+&,%a3,%acc2
+     b4c:	a41a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d2,%acc1
+     b50:	a49a 3639      	macw %a1l,%d3l,>>,%a2@\+&,%d2,%acc2
+     b54:	ae5a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%sp,%acc1
+     b58:	aeda 3639      	macw %a1l,%d3l,>>,%a2@\+&,%sp,%acc2
+     b5c:	a22e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1,%acc1
+     b62:	a2ae 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1,%acc2
+     b68:	a66e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3,%acc1
+     b6e:	a6ee 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3,%acc2
+     b74:	a42e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2,%acc1
+     b7a:	a4ae 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2,%acc2
+     b80:	ae6e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp,%acc1
+     b86:	aeee 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp,%acc2
+     b8c:	a22e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+     b92:	a2ae 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+     b98:	a66e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+     b9e:	a6ee 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+     ba4:	a42e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+     baa:	a4ae 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+     bb0:	ae6e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+     bb6:	aeee 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+     bbc:	a221 3609      	macw %a1l,%d3l,>>,%a1@-,%d1,%acc1
+     bc0:	a2a1 3619      	macw %a1l,%d3l,>>,%a1@-,%d1,%acc2
+     bc4:	a661 3609      	macw %a1l,%d3l,>>,%a1@-,%a3,%acc1
+     bc8:	a6e1 3619      	macw %a1l,%d3l,>>,%a1@-,%a3,%acc2
+     bcc:	a421 3609      	macw %a1l,%d3l,>>,%a1@-,%d2,%acc1
+     bd0:	a4a1 3619      	macw %a1l,%d3l,>>,%a1@-,%d2,%acc2
+     bd4:	ae61 3609      	macw %a1l,%d3l,>>,%a1@-,%sp,%acc1
+     bd8:	aee1 3619      	macw %a1l,%d3l,>>,%a1@-,%sp,%acc2
+     bdc:	a221 3629      	macw %a1l,%d3l,>>,%a1@-&,%d1,%acc1
+     be0:	a2a1 3639      	macw %a1l,%d3l,>>,%a1@-&,%d1,%acc2
+     be4:	a661 3629      	macw %a1l,%d3l,>>,%a1@-&,%a3,%acc1
+     be8:	a6e1 3639      	macw %a1l,%d3l,>>,%a1@-&,%a3,%acc2
+     bec:	a421 3629      	macw %a1l,%d3l,>>,%a1@-&,%d2,%acc1
+     bf0:	a4a1 3639      	macw %a1l,%d3l,>>,%a1@-&,%d2,%acc2
+     bf4:	ae61 3629      	macw %a1l,%d3l,>>,%a1@-&,%sp,%acc1
+     bf8:	aee1 3639      	macw %a1l,%d3l,>>,%a1@-&,%sp,%acc2
+     bfc:	a213 3209      	macw %a1l,%d3l,<<,%a3@,%d1,%acc1
+     c00:	a293 3219      	macw %a1l,%d3l,<<,%a3@,%d1,%acc2
+     c04:	a653 3209      	macw %a1l,%d3l,<<,%a3@,%a3,%acc1
+     c08:	a6d3 3219      	macw %a1l,%d3l,<<,%a3@,%a3,%acc2
+     c0c:	a413 3209      	macw %a1l,%d3l,<<,%a3@,%d2,%acc1
+     c10:	a493 3219      	macw %a1l,%d3l,<<,%a3@,%d2,%acc2
+     c14:	ae53 3209      	macw %a1l,%d3l,<<,%a3@,%sp,%acc1
+     c18:	aed3 3219      	macw %a1l,%d3l,<<,%a3@,%sp,%acc2
+     c1c:	a213 3229      	macw %a1l,%d3l,<<,%a3@&,%d1,%acc1
+     c20:	a293 3239      	macw %a1l,%d3l,<<,%a3@&,%d1,%acc2
+     c24:	a653 3229      	macw %a1l,%d3l,<<,%a3@&,%a3,%acc1
+     c28:	a6d3 3239      	macw %a1l,%d3l,<<,%a3@&,%a3,%acc2
+     c2c:	a413 3229      	macw %a1l,%d3l,<<,%a3@&,%d2,%acc1
+     c30:	a493 3239      	macw %a1l,%d3l,<<,%a3@&,%d2,%acc2
+     c34:	ae53 3229      	macw %a1l,%d3l,<<,%a3@&,%sp,%acc1
+     c38:	aed3 3239      	macw %a1l,%d3l,<<,%a3@&,%sp,%acc2
+     c3c:	a21a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d1,%acc1
+     c40:	a29a 3219      	macw %a1l,%d3l,<<,%a2@\+,%d1,%acc2
+     c44:	a65a 3209      	macw %a1l,%d3l,<<,%a2@\+,%a3,%acc1
+     c48:	a6da 3219      	macw %a1l,%d3l,<<,%a2@\+,%a3,%acc2
+     c4c:	a41a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d2,%acc1
+     c50:	a49a 3219      	macw %a1l,%d3l,<<,%a2@\+,%d2,%acc2
+     c54:	ae5a 3209      	macw %a1l,%d3l,<<,%a2@\+,%sp,%acc1
+     c58:	aeda 3219      	macw %a1l,%d3l,<<,%a2@\+,%sp,%acc2
+     c5c:	a21a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d1,%acc1
+     c60:	a29a 3239      	macw %a1l,%d3l,<<,%a2@\+&,%d1,%acc2
+     c64:	a65a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%a3,%acc1
+     c68:	a6da 3239      	macw %a1l,%d3l,<<,%a2@\+&,%a3,%acc2
+     c6c:	a41a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d2,%acc1
+     c70:	a49a 3239      	macw %a1l,%d3l,<<,%a2@\+&,%d2,%acc2
+     c74:	ae5a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%sp,%acc1
+     c78:	aeda 3239      	macw %a1l,%d3l,<<,%a2@\+&,%sp,%acc2
+     c7c:	a22e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1,%acc1
+     c82:	a2ae 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1,%acc2
+     c88:	a66e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3,%acc1
+     c8e:	a6ee 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3,%acc2
+     c94:	a42e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2,%acc1
+     c9a:	a4ae 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2,%acc2
+     ca0:	ae6e 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp,%acc1
+     ca6:	aeee 3219 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp,%acc2
+     cac:	a22e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+     cb2:	a2ae 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+     cb8:	a66e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+     cbe:	a6ee 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+     cc4:	a42e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+     cca:	a4ae 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+     cd0:	ae6e 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+     cd6:	aeee 3239 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+     cdc:	a221 3209      	macw %a1l,%d3l,<<,%a1@-,%d1,%acc1
+     ce0:	a2a1 3219      	macw %a1l,%d3l,<<,%a1@-,%d1,%acc2
+     ce4:	a661 3209      	macw %a1l,%d3l,<<,%a1@-,%a3,%acc1
+     ce8:	a6e1 3219      	macw %a1l,%d3l,<<,%a1@-,%a3,%acc2
+     cec:	a421 3209      	macw %a1l,%d3l,<<,%a1@-,%d2,%acc1
+     cf0:	a4a1 3219      	macw %a1l,%d3l,<<,%a1@-,%d2,%acc2
+     cf4:	ae61 3209      	macw %a1l,%d3l,<<,%a1@-,%sp,%acc1
+     cf8:	aee1 3219      	macw %a1l,%d3l,<<,%a1@-,%sp,%acc2
+     cfc:	a221 3229      	macw %a1l,%d3l,<<,%a1@-&,%d1,%acc1
+     d00:	a2a1 3239      	macw %a1l,%d3l,<<,%a1@-&,%d1,%acc2
+     d04:	a661 3229      	macw %a1l,%d3l,<<,%a1@-&,%a3,%acc1
+     d08:	a6e1 3239      	macw %a1l,%d3l,<<,%a1@-&,%a3,%acc2
+     d0c:	a421 3229      	macw %a1l,%d3l,<<,%a1@-&,%d2,%acc1
+     d10:	a4a1 3239      	macw %a1l,%d3l,<<,%a1@-&,%d2,%acc2
+     d14:	ae61 3229      	macw %a1l,%d3l,<<,%a1@-&,%sp,%acc1
+     d18:	aee1 3239      	macw %a1l,%d3l,<<,%a1@-&,%sp,%acc2
+     d1c:	a213 3609      	macw %a1l,%d3l,>>,%a3@,%d1,%acc1
+     d20:	a293 3619      	macw %a1l,%d3l,>>,%a3@,%d1,%acc2
+     d24:	a653 3609      	macw %a1l,%d3l,>>,%a3@,%a3,%acc1
+     d28:	a6d3 3619      	macw %a1l,%d3l,>>,%a3@,%a3,%acc2
+     d2c:	a413 3609      	macw %a1l,%d3l,>>,%a3@,%d2,%acc1
+     d30:	a493 3619      	macw %a1l,%d3l,>>,%a3@,%d2,%acc2
+     d34:	ae53 3609      	macw %a1l,%d3l,>>,%a3@,%sp,%acc1
+     d38:	aed3 3619      	macw %a1l,%d3l,>>,%a3@,%sp,%acc2
+     d3c:	a213 3629      	macw %a1l,%d3l,>>,%a3@&,%d1,%acc1
+     d40:	a293 3639      	macw %a1l,%d3l,>>,%a3@&,%d1,%acc2
+     d44:	a653 3629      	macw %a1l,%d3l,>>,%a3@&,%a3,%acc1
+     d48:	a6d3 3639      	macw %a1l,%d3l,>>,%a3@&,%a3,%acc2
+     d4c:	a413 3629      	macw %a1l,%d3l,>>,%a3@&,%d2,%acc1
+     d50:	a493 3639      	macw %a1l,%d3l,>>,%a3@&,%d2,%acc2
+     d54:	ae53 3629      	macw %a1l,%d3l,>>,%a3@&,%sp,%acc1
+     d58:	aed3 3639      	macw %a1l,%d3l,>>,%a3@&,%sp,%acc2
+     d5c:	a21a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d1,%acc1
+     d60:	a29a 3619      	macw %a1l,%d3l,>>,%a2@\+,%d1,%acc2
+     d64:	a65a 3609      	macw %a1l,%d3l,>>,%a2@\+,%a3,%acc1
+     d68:	a6da 3619      	macw %a1l,%d3l,>>,%a2@\+,%a3,%acc2
+     d6c:	a41a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d2,%acc1
+     d70:	a49a 3619      	macw %a1l,%d3l,>>,%a2@\+,%d2,%acc2
+     d74:	ae5a 3609      	macw %a1l,%d3l,>>,%a2@\+,%sp,%acc1
+     d78:	aeda 3619      	macw %a1l,%d3l,>>,%a2@\+,%sp,%acc2
+     d7c:	a21a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d1,%acc1
+     d80:	a29a 3639      	macw %a1l,%d3l,>>,%a2@\+&,%d1,%acc2
+     d84:	a65a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%a3,%acc1
+     d88:	a6da 3639      	macw %a1l,%d3l,>>,%a2@\+&,%a3,%acc2
+     d8c:	a41a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d2,%acc1
+     d90:	a49a 3639      	macw %a1l,%d3l,>>,%a2@\+&,%d2,%acc2
+     d94:	ae5a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%sp,%acc1
+     d98:	aeda 3639      	macw %a1l,%d3l,>>,%a2@\+&,%sp,%acc2
+     d9c:	a22e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1,%acc1
+     da2:	a2ae 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1,%acc2
+     da8:	a66e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3,%acc1
+     dae:	a6ee 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3,%acc2
+     db4:	a42e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2,%acc1
+     dba:	a4ae 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2,%acc2
+     dc0:	ae6e 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp,%acc1
+     dc6:	aeee 3619 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp,%acc2
+     dcc:	a22e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+     dd2:	a2ae 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+     dd8:	a66e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+     dde:	a6ee 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+     de4:	a42e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+     dea:	a4ae 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+     df0:	ae6e 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+     df6:	aeee 3639 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+     dfc:	a221 3609      	macw %a1l,%d3l,>>,%a1@-,%d1,%acc1
+     e00:	a2a1 3619      	macw %a1l,%d3l,>>,%a1@-,%d1,%acc2
+     e04:	a661 3609      	macw %a1l,%d3l,>>,%a1@-,%a3,%acc1
+     e08:	a6e1 3619      	macw %a1l,%d3l,>>,%a1@-,%a3,%acc2
+     e0c:	a421 3609      	macw %a1l,%d3l,>>,%a1@-,%d2,%acc1
+     e10:	a4a1 3619      	macw %a1l,%d3l,>>,%a1@-,%d2,%acc2
+     e14:	ae61 3609      	macw %a1l,%d3l,>>,%a1@-,%sp,%acc1
+     e18:	aee1 3619      	macw %a1l,%d3l,>>,%a1@-,%sp,%acc2
+     e1c:	a221 3629      	macw %a1l,%d3l,>>,%a1@-&,%d1,%acc1
+     e20:	a2a1 3639      	macw %a1l,%d3l,>>,%a1@-&,%d1,%acc2
+     e24:	a661 3629      	macw %a1l,%d3l,>>,%a1@-&,%a3,%acc1
+     e28:	a6e1 3639      	macw %a1l,%d3l,>>,%a1@-&,%a3,%acc2
+     e2c:	a421 3629      	macw %a1l,%d3l,>>,%a1@-&,%d2,%acc1
+     e30:	a4a1 3639      	macw %a1l,%d3l,>>,%a1@-&,%d2,%acc2
+     e34:	ae61 3629      	macw %a1l,%d3l,>>,%a1@-&,%sp,%acc1
+     e38:	aee1 3639      	macw %a1l,%d3l,>>,%a1@-&,%sp,%acc2
+     e3c:	a213 f089      	macw %a1l,%a7u,%a3@,%d1,%acc1
+     e40:	a293 f099      	macw %a1l,%a7u,%a3@,%d1,%acc2
+     e44:	a653 f089      	macw %a1l,%a7u,%a3@,%a3,%acc1
+     e48:	a6d3 f099      	macw %a1l,%a7u,%a3@,%a3,%acc2
+     e4c:	a413 f089      	macw %a1l,%a7u,%a3@,%d2,%acc1
+     e50:	a493 f099      	macw %a1l,%a7u,%a3@,%d2,%acc2
+     e54:	ae53 f089      	macw %a1l,%a7u,%a3@,%sp,%acc1
+     e58:	aed3 f099      	macw %a1l,%a7u,%a3@,%sp,%acc2
+     e5c:	a213 f0a9      	macw %a1l,%a7u,%a3@&,%d1,%acc1
+     e60:	a293 f0b9      	macw %a1l,%a7u,%a3@&,%d1,%acc2
+     e64:	a653 f0a9      	macw %a1l,%a7u,%a3@&,%a3,%acc1
+     e68:	a6d3 f0b9      	macw %a1l,%a7u,%a3@&,%a3,%acc2
+     e6c:	a413 f0a9      	macw %a1l,%a7u,%a3@&,%d2,%acc1
+     e70:	a493 f0b9      	macw %a1l,%a7u,%a3@&,%d2,%acc2
+     e74:	ae53 f0a9      	macw %a1l,%a7u,%a3@&,%sp,%acc1
+     e78:	aed3 f0b9      	macw %a1l,%a7u,%a3@&,%sp,%acc2
+     e7c:	a21a f089      	macw %a1l,%a7u,%a2@\+,%d1,%acc1
+     e80:	a29a f099      	macw %a1l,%a7u,%a2@\+,%d1,%acc2
+     e84:	a65a f089      	macw %a1l,%a7u,%a2@\+,%a3,%acc1
+     e88:	a6da f099      	macw %a1l,%a7u,%a2@\+,%a3,%acc2
+     e8c:	a41a f089      	macw %a1l,%a7u,%a2@\+,%d2,%acc1
+     e90:	a49a f099      	macw %a1l,%a7u,%a2@\+,%d2,%acc2
+     e94:	ae5a f089      	macw %a1l,%a7u,%a2@\+,%sp,%acc1
+     e98:	aeda f099      	macw %a1l,%a7u,%a2@\+,%sp,%acc2
+     e9c:	a21a f0a9      	macw %a1l,%a7u,%a2@\+&,%d1,%acc1
+     ea0:	a29a f0b9      	macw %a1l,%a7u,%a2@\+&,%d1,%acc2
+     ea4:	a65a f0a9      	macw %a1l,%a7u,%a2@\+&,%a3,%acc1
+     ea8:	a6da f0b9      	macw %a1l,%a7u,%a2@\+&,%a3,%acc2
+     eac:	a41a f0a9      	macw %a1l,%a7u,%a2@\+&,%d2,%acc1
+     eb0:	a49a f0b9      	macw %a1l,%a7u,%a2@\+&,%d2,%acc2
+     eb4:	ae5a f0a9      	macw %a1l,%a7u,%a2@\+&,%sp,%acc1
+     eb8:	aeda f0b9      	macw %a1l,%a7u,%a2@\+&,%sp,%acc2
+     ebc:	a22e f089 000a 	macw %a1l,%a7u,%fp@\(10\),%d1,%acc1
+     ec2:	a2ae f099 000a 	macw %a1l,%a7u,%fp@\(10\),%d1,%acc2
+     ec8:	a66e f089 000a 	macw %a1l,%a7u,%fp@\(10\),%a3,%acc1
+     ece:	a6ee f099 000a 	macw %a1l,%a7u,%fp@\(10\),%a3,%acc2
+     ed4:	a42e f089 000a 	macw %a1l,%a7u,%fp@\(10\),%d2,%acc1
+     eda:	a4ae f099 000a 	macw %a1l,%a7u,%fp@\(10\),%d2,%acc2
+     ee0:	ae6e f089 000a 	macw %a1l,%a7u,%fp@\(10\),%sp,%acc1
+     ee6:	aeee f099 000a 	macw %a1l,%a7u,%fp@\(10\),%sp,%acc2
+     eec:	a22e f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d1,%acc1
+     ef2:	a2ae f0b9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d1,%acc2
+     ef8:	a66e f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%a3,%acc1
+     efe:	a6ee f0b9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%a3,%acc2
+     f04:	a42e f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d2,%acc1
+     f0a:	a4ae f0b9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d2,%acc2
+     f10:	ae6e f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%sp,%acc1
+     f16:	aeee f0b9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%sp,%acc2
+     f1c:	a221 f089      	macw %a1l,%a7u,%a1@-,%d1,%acc1
+     f20:	a2a1 f099      	macw %a1l,%a7u,%a1@-,%d1,%acc2
+     f24:	a661 f089      	macw %a1l,%a7u,%a1@-,%a3,%acc1
+     f28:	a6e1 f099      	macw %a1l,%a7u,%a1@-,%a3,%acc2
+     f2c:	a421 f089      	macw %a1l,%a7u,%a1@-,%d2,%acc1
+     f30:	a4a1 f099      	macw %a1l,%a7u,%a1@-,%d2,%acc2
+     f34:	ae61 f089      	macw %a1l,%a7u,%a1@-,%sp,%acc1
+     f38:	aee1 f099      	macw %a1l,%a7u,%a1@-,%sp,%acc2
+     f3c:	a221 f0a9      	macw %a1l,%a7u,%a1@-&,%d1,%acc1
+     f40:	a2a1 f0b9      	macw %a1l,%a7u,%a1@-&,%d1,%acc2
+     f44:	a661 f0a9      	macw %a1l,%a7u,%a1@-&,%a3,%acc1
+     f48:	a6e1 f0b9      	macw %a1l,%a7u,%a1@-&,%a3,%acc2
+     f4c:	a421 f0a9      	macw %a1l,%a7u,%a1@-&,%d2,%acc1
+     f50:	a4a1 f0b9      	macw %a1l,%a7u,%a1@-&,%d2,%acc2
+     f54:	ae61 f0a9      	macw %a1l,%a7u,%a1@-&,%sp,%acc1
+     f58:	aee1 f0b9      	macw %a1l,%a7u,%a1@-&,%sp,%acc2
+     f5c:	a213 f289      	macw %a1l,%a7u,<<,%a3@,%d1,%acc1
+     f60:	a293 f299      	macw %a1l,%a7u,<<,%a3@,%d1,%acc2
+     f64:	a653 f289      	macw %a1l,%a7u,<<,%a3@,%a3,%acc1
+     f68:	a6d3 f299      	macw %a1l,%a7u,<<,%a3@,%a3,%acc2
+     f6c:	a413 f289      	macw %a1l,%a7u,<<,%a3@,%d2,%acc1
+     f70:	a493 f299      	macw %a1l,%a7u,<<,%a3@,%d2,%acc2
+     f74:	ae53 f289      	macw %a1l,%a7u,<<,%a3@,%sp,%acc1
+     f78:	aed3 f299      	macw %a1l,%a7u,<<,%a3@,%sp,%acc2
+     f7c:	a213 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d1,%acc1
+     f80:	a293 f2b9      	macw %a1l,%a7u,<<,%a3@&,%d1,%acc2
+     f84:	a653 f2a9      	macw %a1l,%a7u,<<,%a3@&,%a3,%acc1
+     f88:	a6d3 f2b9      	macw %a1l,%a7u,<<,%a3@&,%a3,%acc2
+     f8c:	a413 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d2,%acc1
+     f90:	a493 f2b9      	macw %a1l,%a7u,<<,%a3@&,%d2,%acc2
+     f94:	ae53 f2a9      	macw %a1l,%a7u,<<,%a3@&,%sp,%acc1
+     f98:	aed3 f2b9      	macw %a1l,%a7u,<<,%a3@&,%sp,%acc2
+     f9c:	a21a f289      	macw %a1l,%a7u,<<,%a2@\+,%d1,%acc1
+     fa0:	a29a f299      	macw %a1l,%a7u,<<,%a2@\+,%d1,%acc2
+     fa4:	a65a f289      	macw %a1l,%a7u,<<,%a2@\+,%a3,%acc1
+     fa8:	a6da f299      	macw %a1l,%a7u,<<,%a2@\+,%a3,%acc2
+     fac:	a41a f289      	macw %a1l,%a7u,<<,%a2@\+,%d2,%acc1
+     fb0:	a49a f299      	macw %a1l,%a7u,<<,%a2@\+,%d2,%acc2
+     fb4:	ae5a f289      	macw %a1l,%a7u,<<,%a2@\+,%sp,%acc1
+     fb8:	aeda f299      	macw %a1l,%a7u,<<,%a2@\+,%sp,%acc2
+     fbc:	a21a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d1,%acc1
+     fc0:	a29a f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%d1,%acc2
+     fc4:	a65a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%a3,%acc1
+     fc8:	a6da f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%a3,%acc2
+     fcc:	a41a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d2,%acc1
+     fd0:	a49a f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%d2,%acc2
+     fd4:	ae5a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%sp,%acc1
+     fd8:	aeda f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%sp,%acc2
+     fdc:	a22e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1,%acc1
+     fe2:	a2ae f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1,%acc2
+     fe8:	a66e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3,%acc1
+     fee:	a6ee f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3,%acc2
+     ff4:	a42e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2,%acc1
+     ffa:	a4ae f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2,%acc2
+    1000:	ae6e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp,%acc1
+    1006:	aeee f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp,%acc2
+    100c:	a22e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    1012:	a2ae f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    1018:	a66e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    101e:	a6ee f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    1024:	a42e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    102a:	a4ae f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    1030:	ae6e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    1036:	aeee f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    103c:	a221 f289      	macw %a1l,%a7u,<<,%a1@-,%d1,%acc1
+    1040:	a2a1 f299      	macw %a1l,%a7u,<<,%a1@-,%d1,%acc2
+    1044:	a661 f289      	macw %a1l,%a7u,<<,%a1@-,%a3,%acc1
+    1048:	a6e1 f299      	macw %a1l,%a7u,<<,%a1@-,%a3,%acc2
+    104c:	a421 f289      	macw %a1l,%a7u,<<,%a1@-,%d2,%acc1
+    1050:	a4a1 f299      	macw %a1l,%a7u,<<,%a1@-,%d2,%acc2
+    1054:	ae61 f289      	macw %a1l,%a7u,<<,%a1@-,%sp,%acc1
+    1058:	aee1 f299      	macw %a1l,%a7u,<<,%a1@-,%sp,%acc2
+    105c:	a221 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d1,%acc1
+    1060:	a2a1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%d1,%acc2
+    1064:	a661 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%a3,%acc1
+    1068:	a6e1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%a3,%acc2
+    106c:	a421 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d2,%acc1
+    1070:	a4a1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%d2,%acc2
+    1074:	ae61 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%sp,%acc1
+    1078:	aee1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%sp,%acc2
+    107c:	a213 f689      	macw %a1l,%a7u,>>,%a3@,%d1,%acc1
+    1080:	a293 f699      	macw %a1l,%a7u,>>,%a3@,%d1,%acc2
+    1084:	a653 f689      	macw %a1l,%a7u,>>,%a3@,%a3,%acc1
+    1088:	a6d3 f699      	macw %a1l,%a7u,>>,%a3@,%a3,%acc2
+    108c:	a413 f689      	macw %a1l,%a7u,>>,%a3@,%d2,%acc1
+    1090:	a493 f699      	macw %a1l,%a7u,>>,%a3@,%d2,%acc2
+    1094:	ae53 f689      	macw %a1l,%a7u,>>,%a3@,%sp,%acc1
+    1098:	aed3 f699      	macw %a1l,%a7u,>>,%a3@,%sp,%acc2
+    109c:	a213 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d1,%acc1
+    10a0:	a293 f6b9      	macw %a1l,%a7u,>>,%a3@&,%d1,%acc2
+    10a4:	a653 f6a9      	macw %a1l,%a7u,>>,%a3@&,%a3,%acc1
+    10a8:	a6d3 f6b9      	macw %a1l,%a7u,>>,%a3@&,%a3,%acc2
+    10ac:	a413 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d2,%acc1
+    10b0:	a493 f6b9      	macw %a1l,%a7u,>>,%a3@&,%d2,%acc2
+    10b4:	ae53 f6a9      	macw %a1l,%a7u,>>,%a3@&,%sp,%acc1
+    10b8:	aed3 f6b9      	macw %a1l,%a7u,>>,%a3@&,%sp,%acc2
+    10bc:	a21a f689      	macw %a1l,%a7u,>>,%a2@\+,%d1,%acc1
+    10c0:	a29a f699      	macw %a1l,%a7u,>>,%a2@\+,%d1,%acc2
+    10c4:	a65a f689      	macw %a1l,%a7u,>>,%a2@\+,%a3,%acc1
+    10c8:	a6da f699      	macw %a1l,%a7u,>>,%a2@\+,%a3,%acc2
+    10cc:	a41a f689      	macw %a1l,%a7u,>>,%a2@\+,%d2,%acc1
+    10d0:	a49a f699      	macw %a1l,%a7u,>>,%a2@\+,%d2,%acc2
+    10d4:	ae5a f689      	macw %a1l,%a7u,>>,%a2@\+,%sp,%acc1
+    10d8:	aeda f699      	macw %a1l,%a7u,>>,%a2@\+,%sp,%acc2
+    10dc:	a21a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d1,%acc1
+    10e0:	a29a f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%d1,%acc2
+    10e4:	a65a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%a3,%acc1
+    10e8:	a6da f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%a3,%acc2
+    10ec:	a41a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d2,%acc1
+    10f0:	a49a f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%d2,%acc2
+    10f4:	ae5a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%sp,%acc1
+    10f8:	aeda f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%sp,%acc2
+    10fc:	a22e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1,%acc1
+    1102:	a2ae f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1,%acc2
+    1108:	a66e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3,%acc1
+    110e:	a6ee f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3,%acc2
+    1114:	a42e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2,%acc1
+    111a:	a4ae f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2,%acc2
+    1120:	ae6e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp,%acc1
+    1126:	aeee f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp,%acc2
+    112c:	a22e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    1132:	a2ae f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    1138:	a66e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    113e:	a6ee f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    1144:	a42e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    114a:	a4ae f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    1150:	ae6e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    1156:	aeee f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    115c:	a221 f689      	macw %a1l,%a7u,>>,%a1@-,%d1,%acc1
+    1160:	a2a1 f699      	macw %a1l,%a7u,>>,%a1@-,%d1,%acc2
+    1164:	a661 f689      	macw %a1l,%a7u,>>,%a1@-,%a3,%acc1
+    1168:	a6e1 f699      	macw %a1l,%a7u,>>,%a1@-,%a3,%acc2
+    116c:	a421 f689      	macw %a1l,%a7u,>>,%a1@-,%d2,%acc1
+    1170:	a4a1 f699      	macw %a1l,%a7u,>>,%a1@-,%d2,%acc2
+    1174:	ae61 f689      	macw %a1l,%a7u,>>,%a1@-,%sp,%acc1
+    1178:	aee1 f699      	macw %a1l,%a7u,>>,%a1@-,%sp,%acc2
+    117c:	a221 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d1,%acc1
+    1180:	a2a1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%d1,%acc2
+    1184:	a661 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%a3,%acc1
+    1188:	a6e1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%a3,%acc2
+    118c:	a421 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d2,%acc1
+    1190:	a4a1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%d2,%acc2
+    1194:	ae61 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%sp,%acc1
+    1198:	aee1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%sp,%acc2
+    119c:	a213 f289      	macw %a1l,%a7u,<<,%a3@,%d1,%acc1
+    11a0:	a293 f299      	macw %a1l,%a7u,<<,%a3@,%d1,%acc2
+    11a4:	a653 f289      	macw %a1l,%a7u,<<,%a3@,%a3,%acc1
+    11a8:	a6d3 f299      	macw %a1l,%a7u,<<,%a3@,%a3,%acc2
+    11ac:	a413 f289      	macw %a1l,%a7u,<<,%a3@,%d2,%acc1
+    11b0:	a493 f299      	macw %a1l,%a7u,<<,%a3@,%d2,%acc2
+    11b4:	ae53 f289      	macw %a1l,%a7u,<<,%a3@,%sp,%acc1
+    11b8:	aed3 f299      	macw %a1l,%a7u,<<,%a3@,%sp,%acc2
+    11bc:	a213 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d1,%acc1
+    11c0:	a293 f2b9      	macw %a1l,%a7u,<<,%a3@&,%d1,%acc2
+    11c4:	a653 f2a9      	macw %a1l,%a7u,<<,%a3@&,%a3,%acc1
+    11c8:	a6d3 f2b9      	macw %a1l,%a7u,<<,%a3@&,%a3,%acc2
+    11cc:	a413 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d2,%acc1
+    11d0:	a493 f2b9      	macw %a1l,%a7u,<<,%a3@&,%d2,%acc2
+    11d4:	ae53 f2a9      	macw %a1l,%a7u,<<,%a3@&,%sp,%acc1
+    11d8:	aed3 f2b9      	macw %a1l,%a7u,<<,%a3@&,%sp,%acc2
+    11dc:	a21a f289      	macw %a1l,%a7u,<<,%a2@\+,%d1,%acc1
+    11e0:	a29a f299      	macw %a1l,%a7u,<<,%a2@\+,%d1,%acc2
+    11e4:	a65a f289      	macw %a1l,%a7u,<<,%a2@\+,%a3,%acc1
+    11e8:	a6da f299      	macw %a1l,%a7u,<<,%a2@\+,%a3,%acc2
+    11ec:	a41a f289      	macw %a1l,%a7u,<<,%a2@\+,%d2,%acc1
+    11f0:	a49a f299      	macw %a1l,%a7u,<<,%a2@\+,%d2,%acc2
+    11f4:	ae5a f289      	macw %a1l,%a7u,<<,%a2@\+,%sp,%acc1
+    11f8:	aeda f299      	macw %a1l,%a7u,<<,%a2@\+,%sp,%acc2
+    11fc:	a21a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d1,%acc1
+    1200:	a29a f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%d1,%acc2
+    1204:	a65a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%a3,%acc1
+    1208:	a6da f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%a3,%acc2
+    120c:	a41a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d2,%acc1
+    1210:	a49a f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%d2,%acc2
+    1214:	ae5a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%sp,%acc1
+    1218:	aeda f2b9      	macw %a1l,%a7u,<<,%a2@\+&,%sp,%acc2
+    121c:	a22e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1,%acc1
+    1222:	a2ae f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1,%acc2
+    1228:	a66e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3,%acc1
+    122e:	a6ee f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3,%acc2
+    1234:	a42e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2,%acc1
+    123a:	a4ae f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2,%acc2
+    1240:	ae6e f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp,%acc1
+    1246:	aeee f299 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp,%acc2
+    124c:	a22e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    1252:	a2ae f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    1258:	a66e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    125e:	a6ee f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    1264:	a42e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    126a:	a4ae f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    1270:	ae6e f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    1276:	aeee f2b9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    127c:	a221 f289      	macw %a1l,%a7u,<<,%a1@-,%d1,%acc1
+    1280:	a2a1 f299      	macw %a1l,%a7u,<<,%a1@-,%d1,%acc2
+    1284:	a661 f289      	macw %a1l,%a7u,<<,%a1@-,%a3,%acc1
+    1288:	a6e1 f299      	macw %a1l,%a7u,<<,%a1@-,%a3,%acc2
+    128c:	a421 f289      	macw %a1l,%a7u,<<,%a1@-,%d2,%acc1
+    1290:	a4a1 f299      	macw %a1l,%a7u,<<,%a1@-,%d2,%acc2
+    1294:	ae61 f289      	macw %a1l,%a7u,<<,%a1@-,%sp,%acc1
+    1298:	aee1 f299      	macw %a1l,%a7u,<<,%a1@-,%sp,%acc2
+    129c:	a221 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d1,%acc1
+    12a0:	a2a1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%d1,%acc2
+    12a4:	a661 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%a3,%acc1
+    12a8:	a6e1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%a3,%acc2
+    12ac:	a421 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d2,%acc1
+    12b0:	a4a1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%d2,%acc2
+    12b4:	ae61 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%sp,%acc1
+    12b8:	aee1 f2b9      	macw %a1l,%a7u,<<,%a1@-&,%sp,%acc2
+    12bc:	a213 f689      	macw %a1l,%a7u,>>,%a3@,%d1,%acc1
+    12c0:	a293 f699      	macw %a1l,%a7u,>>,%a3@,%d1,%acc2
+    12c4:	a653 f689      	macw %a1l,%a7u,>>,%a3@,%a3,%acc1
+    12c8:	a6d3 f699      	macw %a1l,%a7u,>>,%a3@,%a3,%acc2
+    12cc:	a413 f689      	macw %a1l,%a7u,>>,%a3@,%d2,%acc1
+    12d0:	a493 f699      	macw %a1l,%a7u,>>,%a3@,%d2,%acc2
+    12d4:	ae53 f689      	macw %a1l,%a7u,>>,%a3@,%sp,%acc1
+    12d8:	aed3 f699      	macw %a1l,%a7u,>>,%a3@,%sp,%acc2
+    12dc:	a213 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d1,%acc1
+    12e0:	a293 f6b9      	macw %a1l,%a7u,>>,%a3@&,%d1,%acc2
+    12e4:	a653 f6a9      	macw %a1l,%a7u,>>,%a3@&,%a3,%acc1
+    12e8:	a6d3 f6b9      	macw %a1l,%a7u,>>,%a3@&,%a3,%acc2
+    12ec:	a413 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d2,%acc1
+    12f0:	a493 f6b9      	macw %a1l,%a7u,>>,%a3@&,%d2,%acc2
+    12f4:	ae53 f6a9      	macw %a1l,%a7u,>>,%a3@&,%sp,%acc1
+    12f8:	aed3 f6b9      	macw %a1l,%a7u,>>,%a3@&,%sp,%acc2
+    12fc:	a21a f689      	macw %a1l,%a7u,>>,%a2@\+,%d1,%acc1
+    1300:	a29a f699      	macw %a1l,%a7u,>>,%a2@\+,%d1,%acc2
+    1304:	a65a f689      	macw %a1l,%a7u,>>,%a2@\+,%a3,%acc1
+    1308:	a6da f699      	macw %a1l,%a7u,>>,%a2@\+,%a3,%acc2
+    130c:	a41a f689      	macw %a1l,%a7u,>>,%a2@\+,%d2,%acc1
+    1310:	a49a f699      	macw %a1l,%a7u,>>,%a2@\+,%d2,%acc2
+    1314:	ae5a f689      	macw %a1l,%a7u,>>,%a2@\+,%sp,%acc1
+    1318:	aeda f699      	macw %a1l,%a7u,>>,%a2@\+,%sp,%acc2
+    131c:	a21a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d1,%acc1
+    1320:	a29a f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%d1,%acc2
+    1324:	a65a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%a3,%acc1
+    1328:	a6da f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%a3,%acc2
+    132c:	a41a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d2,%acc1
+    1330:	a49a f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%d2,%acc2
+    1334:	ae5a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%sp,%acc1
+    1338:	aeda f6b9      	macw %a1l,%a7u,>>,%a2@\+&,%sp,%acc2
+    133c:	a22e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1,%acc1
+    1342:	a2ae f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1,%acc2
+    1348:	a66e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3,%acc1
+    134e:	a6ee f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3,%acc2
+    1354:	a42e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2,%acc1
+    135a:	a4ae f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2,%acc2
+    1360:	ae6e f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp,%acc1
+    1366:	aeee f699 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp,%acc2
+    136c:	a22e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    1372:	a2ae f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    1378:	a66e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    137e:	a6ee f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    1384:	a42e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    138a:	a4ae f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    1390:	ae6e f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    1396:	aeee f6b9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    139c:	a221 f689      	macw %a1l,%a7u,>>,%a1@-,%d1,%acc1
+    13a0:	a2a1 f699      	macw %a1l,%a7u,>>,%a1@-,%d1,%acc2
+    13a4:	a661 f689      	macw %a1l,%a7u,>>,%a1@-,%a3,%acc1
+    13a8:	a6e1 f699      	macw %a1l,%a7u,>>,%a1@-,%a3,%acc2
+    13ac:	a421 f689      	macw %a1l,%a7u,>>,%a1@-,%d2,%acc1
+    13b0:	a4a1 f699      	macw %a1l,%a7u,>>,%a1@-,%d2,%acc2
+    13b4:	ae61 f689      	macw %a1l,%a7u,>>,%a1@-,%sp,%acc1
+    13b8:	aee1 f699      	macw %a1l,%a7u,>>,%a1@-,%sp,%acc2
+    13bc:	a221 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d1,%acc1
+    13c0:	a2a1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%d1,%acc2
+    13c4:	a661 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%a3,%acc1
+    13c8:	a6e1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%a3,%acc2
+    13cc:	a421 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d2,%acc1
+    13d0:	a4a1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%d2,%acc2
+    13d4:	ae61 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%sp,%acc1
+    13d8:	aee1 f6b9      	macw %a1l,%a7u,>>,%a1@-&,%sp,%acc2
+    13dc:	a213 1009      	macw %a1l,%d1l,%a3@,%d1,%acc1
+    13e0:	a293 1019      	macw %a1l,%d1l,%a3@,%d1,%acc2
+    13e4:	a653 1009      	macw %a1l,%d1l,%a3@,%a3,%acc1
+    13e8:	a6d3 1019      	macw %a1l,%d1l,%a3@,%a3,%acc2
+    13ec:	a413 1009      	macw %a1l,%d1l,%a3@,%d2,%acc1
+    13f0:	a493 1019      	macw %a1l,%d1l,%a3@,%d2,%acc2
+    13f4:	ae53 1009      	macw %a1l,%d1l,%a3@,%sp,%acc1
+    13f8:	aed3 1019      	macw %a1l,%d1l,%a3@,%sp,%acc2
+    13fc:	a213 1029      	macw %a1l,%d1l,%a3@&,%d1,%acc1
+    1400:	a293 1039      	macw %a1l,%d1l,%a3@&,%d1,%acc2
+    1404:	a653 1029      	macw %a1l,%d1l,%a3@&,%a3,%acc1
+    1408:	a6d3 1039      	macw %a1l,%d1l,%a3@&,%a3,%acc2
+    140c:	a413 1029      	macw %a1l,%d1l,%a3@&,%d2,%acc1
+    1410:	a493 1039      	macw %a1l,%d1l,%a3@&,%d2,%acc2
+    1414:	ae53 1029      	macw %a1l,%d1l,%a3@&,%sp,%acc1
+    1418:	aed3 1039      	macw %a1l,%d1l,%a3@&,%sp,%acc2
+    141c:	a21a 1009      	macw %a1l,%d1l,%a2@\+,%d1,%acc1
+    1420:	a29a 1019      	macw %a1l,%d1l,%a2@\+,%d1,%acc2
+    1424:	a65a 1009      	macw %a1l,%d1l,%a2@\+,%a3,%acc1
+    1428:	a6da 1019      	macw %a1l,%d1l,%a2@\+,%a3,%acc2
+    142c:	a41a 1009      	macw %a1l,%d1l,%a2@\+,%d2,%acc1
+    1430:	a49a 1019      	macw %a1l,%d1l,%a2@\+,%d2,%acc2
+    1434:	ae5a 1009      	macw %a1l,%d1l,%a2@\+,%sp,%acc1
+    1438:	aeda 1019      	macw %a1l,%d1l,%a2@\+,%sp,%acc2
+    143c:	a21a 1029      	macw %a1l,%d1l,%a2@\+&,%d1,%acc1
+    1440:	a29a 1039      	macw %a1l,%d1l,%a2@\+&,%d1,%acc2
+    1444:	a65a 1029      	macw %a1l,%d1l,%a2@\+&,%a3,%acc1
+    1448:	a6da 1039      	macw %a1l,%d1l,%a2@\+&,%a3,%acc2
+    144c:	a41a 1029      	macw %a1l,%d1l,%a2@\+&,%d2,%acc1
+    1450:	a49a 1039      	macw %a1l,%d1l,%a2@\+&,%d2,%acc2
+    1454:	ae5a 1029      	macw %a1l,%d1l,%a2@\+&,%sp,%acc1
+    1458:	aeda 1039      	macw %a1l,%d1l,%a2@\+&,%sp,%acc2
+    145c:	a22e 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%d1,%acc1
+    1462:	a2ae 1019 000a 	macw %a1l,%d1l,%fp@\(10\),%d1,%acc2
+    1468:	a66e 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%a3,%acc1
+    146e:	a6ee 1019 000a 	macw %a1l,%d1l,%fp@\(10\),%a3,%acc2
+    1474:	a42e 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%d2,%acc1
+    147a:	a4ae 1019 000a 	macw %a1l,%d1l,%fp@\(10\),%d2,%acc2
+    1480:	ae6e 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%sp,%acc1
+    1486:	aeee 1019 000a 	macw %a1l,%d1l,%fp@\(10\),%sp,%acc2
+    148c:	a22e 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d1,%acc1
+    1492:	a2ae 1039 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d1,%acc2
+    1498:	a66e 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%a3,%acc1
+    149e:	a6ee 1039 000a 	macw %a1l,%d1l,%fp@\(10\)&,%a3,%acc2
+    14a4:	a42e 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d2,%acc1
+    14aa:	a4ae 1039 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d2,%acc2
+    14b0:	ae6e 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%sp,%acc1
+    14b6:	aeee 1039 000a 	macw %a1l,%d1l,%fp@\(10\)&,%sp,%acc2
+    14bc:	a221 1009      	macw %a1l,%d1l,%a1@-,%d1,%acc1
+    14c0:	a2a1 1019      	macw %a1l,%d1l,%a1@-,%d1,%acc2
+    14c4:	a661 1009      	macw %a1l,%d1l,%a1@-,%a3,%acc1
+    14c8:	a6e1 1019      	macw %a1l,%d1l,%a1@-,%a3,%acc2
+    14cc:	a421 1009      	macw %a1l,%d1l,%a1@-,%d2,%acc1
+    14d0:	a4a1 1019      	macw %a1l,%d1l,%a1@-,%d2,%acc2
+    14d4:	ae61 1009      	macw %a1l,%d1l,%a1@-,%sp,%acc1
+    14d8:	aee1 1019      	macw %a1l,%d1l,%a1@-,%sp,%acc2
+    14dc:	a221 1029      	macw %a1l,%d1l,%a1@-&,%d1,%acc1
+    14e0:	a2a1 1039      	macw %a1l,%d1l,%a1@-&,%d1,%acc2
+    14e4:	a661 1029      	macw %a1l,%d1l,%a1@-&,%a3,%acc1
+    14e8:	a6e1 1039      	macw %a1l,%d1l,%a1@-&,%a3,%acc2
+    14ec:	a421 1029      	macw %a1l,%d1l,%a1@-&,%d2,%acc1
+    14f0:	a4a1 1039      	macw %a1l,%d1l,%a1@-&,%d2,%acc2
+    14f4:	ae61 1029      	macw %a1l,%d1l,%a1@-&,%sp,%acc1
+    14f8:	aee1 1039      	macw %a1l,%d1l,%a1@-&,%sp,%acc2
+    14fc:	a213 1209      	macw %a1l,%d1l,<<,%a3@,%d1,%acc1
+    1500:	a293 1219      	macw %a1l,%d1l,<<,%a3@,%d1,%acc2
+    1504:	a653 1209      	macw %a1l,%d1l,<<,%a3@,%a3,%acc1
+    1508:	a6d3 1219      	macw %a1l,%d1l,<<,%a3@,%a3,%acc2
+    150c:	a413 1209      	macw %a1l,%d1l,<<,%a3@,%d2,%acc1
+    1510:	a493 1219      	macw %a1l,%d1l,<<,%a3@,%d2,%acc2
+    1514:	ae53 1209      	macw %a1l,%d1l,<<,%a3@,%sp,%acc1
+    1518:	aed3 1219      	macw %a1l,%d1l,<<,%a3@,%sp,%acc2
+    151c:	a213 1229      	macw %a1l,%d1l,<<,%a3@&,%d1,%acc1
+    1520:	a293 1239      	macw %a1l,%d1l,<<,%a3@&,%d1,%acc2
+    1524:	a653 1229      	macw %a1l,%d1l,<<,%a3@&,%a3,%acc1
+    1528:	a6d3 1239      	macw %a1l,%d1l,<<,%a3@&,%a3,%acc2
+    152c:	a413 1229      	macw %a1l,%d1l,<<,%a3@&,%d2,%acc1
+    1530:	a493 1239      	macw %a1l,%d1l,<<,%a3@&,%d2,%acc2
+    1534:	ae53 1229      	macw %a1l,%d1l,<<,%a3@&,%sp,%acc1
+    1538:	aed3 1239      	macw %a1l,%d1l,<<,%a3@&,%sp,%acc2
+    153c:	a21a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d1,%acc1
+    1540:	a29a 1219      	macw %a1l,%d1l,<<,%a2@\+,%d1,%acc2
+    1544:	a65a 1209      	macw %a1l,%d1l,<<,%a2@\+,%a3,%acc1
+    1548:	a6da 1219      	macw %a1l,%d1l,<<,%a2@\+,%a3,%acc2
+    154c:	a41a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d2,%acc1
+    1550:	a49a 1219      	macw %a1l,%d1l,<<,%a2@\+,%d2,%acc2
+    1554:	ae5a 1209      	macw %a1l,%d1l,<<,%a2@\+,%sp,%acc1
+    1558:	aeda 1219      	macw %a1l,%d1l,<<,%a2@\+,%sp,%acc2
+    155c:	a21a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d1,%acc1
+    1560:	a29a 1239      	macw %a1l,%d1l,<<,%a2@\+&,%d1,%acc2
+    1564:	a65a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%a3,%acc1
+    1568:	a6da 1239      	macw %a1l,%d1l,<<,%a2@\+&,%a3,%acc2
+    156c:	a41a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d2,%acc1
+    1570:	a49a 1239      	macw %a1l,%d1l,<<,%a2@\+&,%d2,%acc2
+    1574:	ae5a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%sp,%acc1
+    1578:	aeda 1239      	macw %a1l,%d1l,<<,%a2@\+&,%sp,%acc2
+    157c:	a22e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1,%acc1
+    1582:	a2ae 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1,%acc2
+    1588:	a66e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3,%acc1
+    158e:	a6ee 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3,%acc2
+    1594:	a42e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2,%acc1
+    159a:	a4ae 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2,%acc2
+    15a0:	ae6e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp,%acc1
+    15a6:	aeee 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp,%acc2
+    15ac:	a22e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    15b2:	a2ae 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    15b8:	a66e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    15be:	a6ee 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    15c4:	a42e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    15ca:	a4ae 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    15d0:	ae6e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    15d6:	aeee 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    15dc:	a221 1209      	macw %a1l,%d1l,<<,%a1@-,%d1,%acc1
+    15e0:	a2a1 1219      	macw %a1l,%d1l,<<,%a1@-,%d1,%acc2
+    15e4:	a661 1209      	macw %a1l,%d1l,<<,%a1@-,%a3,%acc1
+    15e8:	a6e1 1219      	macw %a1l,%d1l,<<,%a1@-,%a3,%acc2
+    15ec:	a421 1209      	macw %a1l,%d1l,<<,%a1@-,%d2,%acc1
+    15f0:	a4a1 1219      	macw %a1l,%d1l,<<,%a1@-,%d2,%acc2
+    15f4:	ae61 1209      	macw %a1l,%d1l,<<,%a1@-,%sp,%acc1
+    15f8:	aee1 1219      	macw %a1l,%d1l,<<,%a1@-,%sp,%acc2
+    15fc:	a221 1229      	macw %a1l,%d1l,<<,%a1@-&,%d1,%acc1
+    1600:	a2a1 1239      	macw %a1l,%d1l,<<,%a1@-&,%d1,%acc2
+    1604:	a661 1229      	macw %a1l,%d1l,<<,%a1@-&,%a3,%acc1
+    1608:	a6e1 1239      	macw %a1l,%d1l,<<,%a1@-&,%a3,%acc2
+    160c:	a421 1229      	macw %a1l,%d1l,<<,%a1@-&,%d2,%acc1
+    1610:	a4a1 1239      	macw %a1l,%d1l,<<,%a1@-&,%d2,%acc2
+    1614:	ae61 1229      	macw %a1l,%d1l,<<,%a1@-&,%sp,%acc1
+    1618:	aee1 1239      	macw %a1l,%d1l,<<,%a1@-&,%sp,%acc2
+    161c:	a213 1609      	macw %a1l,%d1l,>>,%a3@,%d1,%acc1
+    1620:	a293 1619      	macw %a1l,%d1l,>>,%a3@,%d1,%acc2
+    1624:	a653 1609      	macw %a1l,%d1l,>>,%a3@,%a3,%acc1
+    1628:	a6d3 1619      	macw %a1l,%d1l,>>,%a3@,%a3,%acc2
+    162c:	a413 1609      	macw %a1l,%d1l,>>,%a3@,%d2,%acc1
+    1630:	a493 1619      	macw %a1l,%d1l,>>,%a3@,%d2,%acc2
+    1634:	ae53 1609      	macw %a1l,%d1l,>>,%a3@,%sp,%acc1
+    1638:	aed3 1619      	macw %a1l,%d1l,>>,%a3@,%sp,%acc2
+    163c:	a213 1629      	macw %a1l,%d1l,>>,%a3@&,%d1,%acc1
+    1640:	a293 1639      	macw %a1l,%d1l,>>,%a3@&,%d1,%acc2
+    1644:	a653 1629      	macw %a1l,%d1l,>>,%a3@&,%a3,%acc1
+    1648:	a6d3 1639      	macw %a1l,%d1l,>>,%a3@&,%a3,%acc2
+    164c:	a413 1629      	macw %a1l,%d1l,>>,%a3@&,%d2,%acc1
+    1650:	a493 1639      	macw %a1l,%d1l,>>,%a3@&,%d2,%acc2
+    1654:	ae53 1629      	macw %a1l,%d1l,>>,%a3@&,%sp,%acc1
+    1658:	aed3 1639      	macw %a1l,%d1l,>>,%a3@&,%sp,%acc2
+    165c:	a21a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d1,%acc1
+    1660:	a29a 1619      	macw %a1l,%d1l,>>,%a2@\+,%d1,%acc2
+    1664:	a65a 1609      	macw %a1l,%d1l,>>,%a2@\+,%a3,%acc1
+    1668:	a6da 1619      	macw %a1l,%d1l,>>,%a2@\+,%a3,%acc2
+    166c:	a41a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d2,%acc1
+    1670:	a49a 1619      	macw %a1l,%d1l,>>,%a2@\+,%d2,%acc2
+    1674:	ae5a 1609      	macw %a1l,%d1l,>>,%a2@\+,%sp,%acc1
+    1678:	aeda 1619      	macw %a1l,%d1l,>>,%a2@\+,%sp,%acc2
+    167c:	a21a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d1,%acc1
+    1680:	a29a 1639      	macw %a1l,%d1l,>>,%a2@\+&,%d1,%acc2
+    1684:	a65a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%a3,%acc1
+    1688:	a6da 1639      	macw %a1l,%d1l,>>,%a2@\+&,%a3,%acc2
+    168c:	a41a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d2,%acc1
+    1690:	a49a 1639      	macw %a1l,%d1l,>>,%a2@\+&,%d2,%acc2
+    1694:	ae5a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%sp,%acc1
+    1698:	aeda 1639      	macw %a1l,%d1l,>>,%a2@\+&,%sp,%acc2
+    169c:	a22e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1,%acc1
+    16a2:	a2ae 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1,%acc2
+    16a8:	a66e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3,%acc1
+    16ae:	a6ee 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3,%acc2
+    16b4:	a42e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2,%acc1
+    16ba:	a4ae 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2,%acc2
+    16c0:	ae6e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp,%acc1
+    16c6:	aeee 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp,%acc2
+    16cc:	a22e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    16d2:	a2ae 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    16d8:	a66e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    16de:	a6ee 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    16e4:	a42e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    16ea:	a4ae 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    16f0:	ae6e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    16f6:	aeee 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    16fc:	a221 1609      	macw %a1l,%d1l,>>,%a1@-,%d1,%acc1
+    1700:	a2a1 1619      	macw %a1l,%d1l,>>,%a1@-,%d1,%acc2
+    1704:	a661 1609      	macw %a1l,%d1l,>>,%a1@-,%a3,%acc1
+    1708:	a6e1 1619      	macw %a1l,%d1l,>>,%a1@-,%a3,%acc2
+    170c:	a421 1609      	macw %a1l,%d1l,>>,%a1@-,%d2,%acc1
+    1710:	a4a1 1619      	macw %a1l,%d1l,>>,%a1@-,%d2,%acc2
+    1714:	ae61 1609      	macw %a1l,%d1l,>>,%a1@-,%sp,%acc1
+    1718:	aee1 1619      	macw %a1l,%d1l,>>,%a1@-,%sp,%acc2
+    171c:	a221 1629      	macw %a1l,%d1l,>>,%a1@-&,%d1,%acc1
+    1720:	a2a1 1639      	macw %a1l,%d1l,>>,%a1@-&,%d1,%acc2
+    1724:	a661 1629      	macw %a1l,%d1l,>>,%a1@-&,%a3,%acc1
+    1728:	a6e1 1639      	macw %a1l,%d1l,>>,%a1@-&,%a3,%acc2
+    172c:	a421 1629      	macw %a1l,%d1l,>>,%a1@-&,%d2,%acc1
+    1730:	a4a1 1639      	macw %a1l,%d1l,>>,%a1@-&,%d2,%acc2
+    1734:	ae61 1629      	macw %a1l,%d1l,>>,%a1@-&,%sp,%acc1
+    1738:	aee1 1639      	macw %a1l,%d1l,>>,%a1@-&,%sp,%acc2
+    173c:	a213 1209      	macw %a1l,%d1l,<<,%a3@,%d1,%acc1
+    1740:	a293 1219      	macw %a1l,%d1l,<<,%a3@,%d1,%acc2
+    1744:	a653 1209      	macw %a1l,%d1l,<<,%a3@,%a3,%acc1
+    1748:	a6d3 1219      	macw %a1l,%d1l,<<,%a3@,%a3,%acc2
+    174c:	a413 1209      	macw %a1l,%d1l,<<,%a3@,%d2,%acc1
+    1750:	a493 1219      	macw %a1l,%d1l,<<,%a3@,%d2,%acc2
+    1754:	ae53 1209      	macw %a1l,%d1l,<<,%a3@,%sp,%acc1
+    1758:	aed3 1219      	macw %a1l,%d1l,<<,%a3@,%sp,%acc2
+    175c:	a213 1229      	macw %a1l,%d1l,<<,%a3@&,%d1,%acc1
+    1760:	a293 1239      	macw %a1l,%d1l,<<,%a3@&,%d1,%acc2
+    1764:	a653 1229      	macw %a1l,%d1l,<<,%a3@&,%a3,%acc1
+    1768:	a6d3 1239      	macw %a1l,%d1l,<<,%a3@&,%a3,%acc2
+    176c:	a413 1229      	macw %a1l,%d1l,<<,%a3@&,%d2,%acc1
+    1770:	a493 1239      	macw %a1l,%d1l,<<,%a3@&,%d2,%acc2
+    1774:	ae53 1229      	macw %a1l,%d1l,<<,%a3@&,%sp,%acc1
+    1778:	aed3 1239      	macw %a1l,%d1l,<<,%a3@&,%sp,%acc2
+    177c:	a21a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d1,%acc1
+    1780:	a29a 1219      	macw %a1l,%d1l,<<,%a2@\+,%d1,%acc2
+    1784:	a65a 1209      	macw %a1l,%d1l,<<,%a2@\+,%a3,%acc1
+    1788:	a6da 1219      	macw %a1l,%d1l,<<,%a2@\+,%a3,%acc2
+    178c:	a41a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d2,%acc1
+    1790:	a49a 1219      	macw %a1l,%d1l,<<,%a2@\+,%d2,%acc2
+    1794:	ae5a 1209      	macw %a1l,%d1l,<<,%a2@\+,%sp,%acc1
+    1798:	aeda 1219      	macw %a1l,%d1l,<<,%a2@\+,%sp,%acc2
+    179c:	a21a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d1,%acc1
+    17a0:	a29a 1239      	macw %a1l,%d1l,<<,%a2@\+&,%d1,%acc2
+    17a4:	a65a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%a3,%acc1
+    17a8:	a6da 1239      	macw %a1l,%d1l,<<,%a2@\+&,%a3,%acc2
+    17ac:	a41a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d2,%acc1
+    17b0:	a49a 1239      	macw %a1l,%d1l,<<,%a2@\+&,%d2,%acc2
+    17b4:	ae5a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%sp,%acc1
+    17b8:	aeda 1239      	macw %a1l,%d1l,<<,%a2@\+&,%sp,%acc2
+    17bc:	a22e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1,%acc1
+    17c2:	a2ae 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1,%acc2
+    17c8:	a66e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3,%acc1
+    17ce:	a6ee 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3,%acc2
+    17d4:	a42e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2,%acc1
+    17da:	a4ae 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2,%acc2
+    17e0:	ae6e 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp,%acc1
+    17e6:	aeee 1219 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp,%acc2
+    17ec:	a22e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    17f2:	a2ae 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    17f8:	a66e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    17fe:	a6ee 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    1804:	a42e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    180a:	a4ae 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    1810:	ae6e 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    1816:	aeee 1239 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    181c:	a221 1209      	macw %a1l,%d1l,<<,%a1@-,%d1,%acc1
+    1820:	a2a1 1219      	macw %a1l,%d1l,<<,%a1@-,%d1,%acc2
+    1824:	a661 1209      	macw %a1l,%d1l,<<,%a1@-,%a3,%acc1
+    1828:	a6e1 1219      	macw %a1l,%d1l,<<,%a1@-,%a3,%acc2
+    182c:	a421 1209      	macw %a1l,%d1l,<<,%a1@-,%d2,%acc1
+    1830:	a4a1 1219      	macw %a1l,%d1l,<<,%a1@-,%d2,%acc2
+    1834:	ae61 1209      	macw %a1l,%d1l,<<,%a1@-,%sp,%acc1
+    1838:	aee1 1219      	macw %a1l,%d1l,<<,%a1@-,%sp,%acc2
+    183c:	a221 1229      	macw %a1l,%d1l,<<,%a1@-&,%d1,%acc1
+    1840:	a2a1 1239      	macw %a1l,%d1l,<<,%a1@-&,%d1,%acc2
+    1844:	a661 1229      	macw %a1l,%d1l,<<,%a1@-&,%a3,%acc1
+    1848:	a6e1 1239      	macw %a1l,%d1l,<<,%a1@-&,%a3,%acc2
+    184c:	a421 1229      	macw %a1l,%d1l,<<,%a1@-&,%d2,%acc1
+    1850:	a4a1 1239      	macw %a1l,%d1l,<<,%a1@-&,%d2,%acc2
+    1854:	ae61 1229      	macw %a1l,%d1l,<<,%a1@-&,%sp,%acc1
+    1858:	aee1 1239      	macw %a1l,%d1l,<<,%a1@-&,%sp,%acc2
+    185c:	a213 1609      	macw %a1l,%d1l,>>,%a3@,%d1,%acc1
+    1860:	a293 1619      	macw %a1l,%d1l,>>,%a3@,%d1,%acc2
+    1864:	a653 1609      	macw %a1l,%d1l,>>,%a3@,%a3,%acc1
+    1868:	a6d3 1619      	macw %a1l,%d1l,>>,%a3@,%a3,%acc2
+    186c:	a413 1609      	macw %a1l,%d1l,>>,%a3@,%d2,%acc1
+    1870:	a493 1619      	macw %a1l,%d1l,>>,%a3@,%d2,%acc2
+    1874:	ae53 1609      	macw %a1l,%d1l,>>,%a3@,%sp,%acc1
+    1878:	aed3 1619      	macw %a1l,%d1l,>>,%a3@,%sp,%acc2
+    187c:	a213 1629      	macw %a1l,%d1l,>>,%a3@&,%d1,%acc1
+    1880:	a293 1639      	macw %a1l,%d1l,>>,%a3@&,%d1,%acc2
+    1884:	a653 1629      	macw %a1l,%d1l,>>,%a3@&,%a3,%acc1
+    1888:	a6d3 1639      	macw %a1l,%d1l,>>,%a3@&,%a3,%acc2
+    188c:	a413 1629      	macw %a1l,%d1l,>>,%a3@&,%d2,%acc1
+    1890:	a493 1639      	macw %a1l,%d1l,>>,%a3@&,%d2,%acc2
+    1894:	ae53 1629      	macw %a1l,%d1l,>>,%a3@&,%sp,%acc1
+    1898:	aed3 1639      	macw %a1l,%d1l,>>,%a3@&,%sp,%acc2
+    189c:	a21a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d1,%acc1
+    18a0:	a29a 1619      	macw %a1l,%d1l,>>,%a2@\+,%d1,%acc2
+    18a4:	a65a 1609      	macw %a1l,%d1l,>>,%a2@\+,%a3,%acc1
+    18a8:	a6da 1619      	macw %a1l,%d1l,>>,%a2@\+,%a3,%acc2
+    18ac:	a41a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d2,%acc1
+    18b0:	a49a 1619      	macw %a1l,%d1l,>>,%a2@\+,%d2,%acc2
+    18b4:	ae5a 1609      	macw %a1l,%d1l,>>,%a2@\+,%sp,%acc1
+    18b8:	aeda 1619      	macw %a1l,%d1l,>>,%a2@\+,%sp,%acc2
+    18bc:	a21a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d1,%acc1
+    18c0:	a29a 1639      	macw %a1l,%d1l,>>,%a2@\+&,%d1,%acc2
+    18c4:	a65a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%a3,%acc1
+    18c8:	a6da 1639      	macw %a1l,%d1l,>>,%a2@\+&,%a3,%acc2
+    18cc:	a41a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d2,%acc1
+    18d0:	a49a 1639      	macw %a1l,%d1l,>>,%a2@\+&,%d2,%acc2
+    18d4:	ae5a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%sp,%acc1
+    18d8:	aeda 1639      	macw %a1l,%d1l,>>,%a2@\+&,%sp,%acc2
+    18dc:	a22e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1,%acc1
+    18e2:	a2ae 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1,%acc2
+    18e8:	a66e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3,%acc1
+    18ee:	a6ee 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3,%acc2
+    18f4:	a42e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2,%acc1
+    18fa:	a4ae 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2,%acc2
+    1900:	ae6e 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp,%acc1
+    1906:	aeee 1619 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp,%acc2
+    190c:	a22e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    1912:	a2ae 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    1918:	a66e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    191e:	a6ee 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    1924:	a42e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    192a:	a4ae 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    1930:	ae6e 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    1936:	aeee 1639 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    193c:	a221 1609      	macw %a1l,%d1l,>>,%a1@-,%d1,%acc1
+    1940:	a2a1 1619      	macw %a1l,%d1l,>>,%a1@-,%d1,%acc2
+    1944:	a661 1609      	macw %a1l,%d1l,>>,%a1@-,%a3,%acc1
+    1948:	a6e1 1619      	macw %a1l,%d1l,>>,%a1@-,%a3,%acc2
+    194c:	a421 1609      	macw %a1l,%d1l,>>,%a1@-,%d2,%acc1
+    1950:	a4a1 1619      	macw %a1l,%d1l,>>,%a1@-,%d2,%acc2
+    1954:	ae61 1609      	macw %a1l,%d1l,>>,%a1@-,%sp,%acc1
+    1958:	aee1 1619      	macw %a1l,%d1l,>>,%a1@-,%sp,%acc2
+    195c:	a221 1629      	macw %a1l,%d1l,>>,%a1@-&,%d1,%acc1
+    1960:	a2a1 1639      	macw %a1l,%d1l,>>,%a1@-&,%d1,%acc2
+    1964:	a661 1629      	macw %a1l,%d1l,>>,%a1@-&,%a3,%acc1
+    1968:	a6e1 1639      	macw %a1l,%d1l,>>,%a1@-&,%a3,%acc2
+    196c:	a421 1629      	macw %a1l,%d1l,>>,%a1@-&,%d2,%acc1
+    1970:	a4a1 1639      	macw %a1l,%d1l,>>,%a1@-&,%d2,%acc2
+    1974:	ae61 1629      	macw %a1l,%d1l,>>,%a1@-&,%sp,%acc1
+    1978:	aee1 1639      	macw %a1l,%d1l,>>,%a1@-&,%sp,%acc2
+    197c:	a213 a0c2      	macw %d2u,%a2u,%a3@,%d1,%acc1
+    1980:	a293 a0d2      	macw %d2u,%a2u,%a3@,%d1,%acc2
+    1984:	a653 a0c2      	macw %d2u,%a2u,%a3@,%a3,%acc1
+    1988:	a6d3 a0d2      	macw %d2u,%a2u,%a3@,%a3,%acc2
+    198c:	a413 a0c2      	macw %d2u,%a2u,%a3@,%d2,%acc1
+    1990:	a493 a0d2      	macw %d2u,%a2u,%a3@,%d2,%acc2
+    1994:	ae53 a0c2      	macw %d2u,%a2u,%a3@,%sp,%acc1
+    1998:	aed3 a0d2      	macw %d2u,%a2u,%a3@,%sp,%acc2
+    199c:	a213 a0e2      	macw %d2u,%a2u,%a3@&,%d1,%acc1
+    19a0:	a293 a0f2      	macw %d2u,%a2u,%a3@&,%d1,%acc2
+    19a4:	a653 a0e2      	macw %d2u,%a2u,%a3@&,%a3,%acc1
+    19a8:	a6d3 a0f2      	macw %d2u,%a2u,%a3@&,%a3,%acc2
+    19ac:	a413 a0e2      	macw %d2u,%a2u,%a3@&,%d2,%acc1
+    19b0:	a493 a0f2      	macw %d2u,%a2u,%a3@&,%d2,%acc2
+    19b4:	ae53 a0e2      	macw %d2u,%a2u,%a3@&,%sp,%acc1
+    19b8:	aed3 a0f2      	macw %d2u,%a2u,%a3@&,%sp,%acc2
+    19bc:	a21a a0c2      	macw %d2u,%a2u,%a2@\+,%d1,%acc1
+    19c0:	a29a a0d2      	macw %d2u,%a2u,%a2@\+,%d1,%acc2
+    19c4:	a65a a0c2      	macw %d2u,%a2u,%a2@\+,%a3,%acc1
+    19c8:	a6da a0d2      	macw %d2u,%a2u,%a2@\+,%a3,%acc2
+    19cc:	a41a a0c2      	macw %d2u,%a2u,%a2@\+,%d2,%acc1
+    19d0:	a49a a0d2      	macw %d2u,%a2u,%a2@\+,%d2,%acc2
+    19d4:	ae5a a0c2      	macw %d2u,%a2u,%a2@\+,%sp,%acc1
+    19d8:	aeda a0d2      	macw %d2u,%a2u,%a2@\+,%sp,%acc2
+    19dc:	a21a a0e2      	macw %d2u,%a2u,%a2@\+&,%d1,%acc1
+    19e0:	a29a a0f2      	macw %d2u,%a2u,%a2@\+&,%d1,%acc2
+    19e4:	a65a a0e2      	macw %d2u,%a2u,%a2@\+&,%a3,%acc1
+    19e8:	a6da a0f2      	macw %d2u,%a2u,%a2@\+&,%a3,%acc2
+    19ec:	a41a a0e2      	macw %d2u,%a2u,%a2@\+&,%d2,%acc1
+    19f0:	a49a a0f2      	macw %d2u,%a2u,%a2@\+&,%d2,%acc2
+    19f4:	ae5a a0e2      	macw %d2u,%a2u,%a2@\+&,%sp,%acc1
+    19f8:	aeda a0f2      	macw %d2u,%a2u,%a2@\+&,%sp,%acc2
+    19fc:	a22e a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%d1,%acc1
+    1a02:	a2ae a0d2 000a 	macw %d2u,%a2u,%fp@\(10\),%d1,%acc2
+    1a08:	a66e a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%a3,%acc1
+    1a0e:	a6ee a0d2 000a 	macw %d2u,%a2u,%fp@\(10\),%a3,%acc2
+    1a14:	a42e a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%d2,%acc1
+    1a1a:	a4ae a0d2 000a 	macw %d2u,%a2u,%fp@\(10\),%d2,%acc2
+    1a20:	ae6e a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%sp,%acc1
+    1a26:	aeee a0d2 000a 	macw %d2u,%a2u,%fp@\(10\),%sp,%acc2
+    1a2c:	a22e a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d1,%acc1
+    1a32:	a2ae a0f2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d1,%acc2
+    1a38:	a66e a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%a3,%acc1
+    1a3e:	a6ee a0f2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%a3,%acc2
+    1a44:	a42e a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d2,%acc1
+    1a4a:	a4ae a0f2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d2,%acc2
+    1a50:	ae6e a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%sp,%acc1
+    1a56:	aeee a0f2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%sp,%acc2
+    1a5c:	a221 a0c2      	macw %d2u,%a2u,%a1@-,%d1,%acc1
+    1a60:	a2a1 a0d2      	macw %d2u,%a2u,%a1@-,%d1,%acc2
+    1a64:	a661 a0c2      	macw %d2u,%a2u,%a1@-,%a3,%acc1
+    1a68:	a6e1 a0d2      	macw %d2u,%a2u,%a1@-,%a3,%acc2
+    1a6c:	a421 a0c2      	macw %d2u,%a2u,%a1@-,%d2,%acc1
+    1a70:	a4a1 a0d2      	macw %d2u,%a2u,%a1@-,%d2,%acc2
+    1a74:	ae61 a0c2      	macw %d2u,%a2u,%a1@-,%sp,%acc1
+    1a78:	aee1 a0d2      	macw %d2u,%a2u,%a1@-,%sp,%acc2
+    1a7c:	a221 a0e2      	macw %d2u,%a2u,%a1@-&,%d1,%acc1
+    1a80:	a2a1 a0f2      	macw %d2u,%a2u,%a1@-&,%d1,%acc2
+    1a84:	a661 a0e2      	macw %d2u,%a2u,%a1@-&,%a3,%acc1
+    1a88:	a6e1 a0f2      	macw %d2u,%a2u,%a1@-&,%a3,%acc2
+    1a8c:	a421 a0e2      	macw %d2u,%a2u,%a1@-&,%d2,%acc1
+    1a90:	a4a1 a0f2      	macw %d2u,%a2u,%a1@-&,%d2,%acc2
+    1a94:	ae61 a0e2      	macw %d2u,%a2u,%a1@-&,%sp,%acc1
+    1a98:	aee1 a0f2      	macw %d2u,%a2u,%a1@-&,%sp,%acc2
+    1a9c:	a213 a2c2      	macw %d2u,%a2u,<<,%a3@,%d1,%acc1
+    1aa0:	a293 a2d2      	macw %d2u,%a2u,<<,%a3@,%d1,%acc2
+    1aa4:	a653 a2c2      	macw %d2u,%a2u,<<,%a3@,%a3,%acc1
+    1aa8:	a6d3 a2d2      	macw %d2u,%a2u,<<,%a3@,%a3,%acc2
+    1aac:	a413 a2c2      	macw %d2u,%a2u,<<,%a3@,%d2,%acc1
+    1ab0:	a493 a2d2      	macw %d2u,%a2u,<<,%a3@,%d2,%acc2
+    1ab4:	ae53 a2c2      	macw %d2u,%a2u,<<,%a3@,%sp,%acc1
+    1ab8:	aed3 a2d2      	macw %d2u,%a2u,<<,%a3@,%sp,%acc2
+    1abc:	a213 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d1,%acc1
+    1ac0:	a293 a2f2      	macw %d2u,%a2u,<<,%a3@&,%d1,%acc2
+    1ac4:	a653 a2e2      	macw %d2u,%a2u,<<,%a3@&,%a3,%acc1
+    1ac8:	a6d3 a2f2      	macw %d2u,%a2u,<<,%a3@&,%a3,%acc2
+    1acc:	a413 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d2,%acc1
+    1ad0:	a493 a2f2      	macw %d2u,%a2u,<<,%a3@&,%d2,%acc2
+    1ad4:	ae53 a2e2      	macw %d2u,%a2u,<<,%a3@&,%sp,%acc1
+    1ad8:	aed3 a2f2      	macw %d2u,%a2u,<<,%a3@&,%sp,%acc2
+    1adc:	a21a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d1,%acc1
+    1ae0:	a29a a2d2      	macw %d2u,%a2u,<<,%a2@\+,%d1,%acc2
+    1ae4:	a65a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%a3,%acc1
+    1ae8:	a6da a2d2      	macw %d2u,%a2u,<<,%a2@\+,%a3,%acc2
+    1aec:	a41a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d2,%acc1
+    1af0:	a49a a2d2      	macw %d2u,%a2u,<<,%a2@\+,%d2,%acc2
+    1af4:	ae5a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%sp,%acc1
+    1af8:	aeda a2d2      	macw %d2u,%a2u,<<,%a2@\+,%sp,%acc2
+    1afc:	a21a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d1,%acc1
+    1b00:	a29a a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%d1,%acc2
+    1b04:	a65a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%a3,%acc1
+    1b08:	a6da a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%a3,%acc2
+    1b0c:	a41a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d2,%acc1
+    1b10:	a49a a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%d2,%acc2
+    1b14:	ae5a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%sp,%acc1
+    1b18:	aeda a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%sp,%acc2
+    1b1c:	a22e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1,%acc1
+    1b22:	a2ae a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1,%acc2
+    1b28:	a66e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3,%acc1
+    1b2e:	a6ee a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3,%acc2
+    1b34:	a42e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2,%acc1
+    1b3a:	a4ae a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2,%acc2
+    1b40:	ae6e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp,%acc1
+    1b46:	aeee a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp,%acc2
+    1b4c:	a22e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    1b52:	a2ae a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    1b58:	a66e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    1b5e:	a6ee a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    1b64:	a42e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    1b6a:	a4ae a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    1b70:	ae6e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    1b76:	aeee a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    1b7c:	a221 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d1,%acc1
+    1b80:	a2a1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%d1,%acc2
+    1b84:	a661 a2c2      	macw %d2u,%a2u,<<,%a1@-,%a3,%acc1
+    1b88:	a6e1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%a3,%acc2
+    1b8c:	a421 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d2,%acc1
+    1b90:	a4a1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%d2,%acc2
+    1b94:	ae61 a2c2      	macw %d2u,%a2u,<<,%a1@-,%sp,%acc1
+    1b98:	aee1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%sp,%acc2
+    1b9c:	a221 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d1,%acc1
+    1ba0:	a2a1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%d1,%acc2
+    1ba4:	a661 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%a3,%acc1
+    1ba8:	a6e1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%a3,%acc2
+    1bac:	a421 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d2,%acc1
+    1bb0:	a4a1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%d2,%acc2
+    1bb4:	ae61 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%sp,%acc1
+    1bb8:	aee1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%sp,%acc2
+    1bbc:	a213 a6c2      	macw %d2u,%a2u,>>,%a3@,%d1,%acc1
+    1bc0:	a293 a6d2      	macw %d2u,%a2u,>>,%a3@,%d1,%acc2
+    1bc4:	a653 a6c2      	macw %d2u,%a2u,>>,%a3@,%a3,%acc1
+    1bc8:	a6d3 a6d2      	macw %d2u,%a2u,>>,%a3@,%a3,%acc2
+    1bcc:	a413 a6c2      	macw %d2u,%a2u,>>,%a3@,%d2,%acc1
+    1bd0:	a493 a6d2      	macw %d2u,%a2u,>>,%a3@,%d2,%acc2
+    1bd4:	ae53 a6c2      	macw %d2u,%a2u,>>,%a3@,%sp,%acc1
+    1bd8:	aed3 a6d2      	macw %d2u,%a2u,>>,%a3@,%sp,%acc2
+    1bdc:	a213 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d1,%acc1
+    1be0:	a293 a6f2      	macw %d2u,%a2u,>>,%a3@&,%d1,%acc2
+    1be4:	a653 a6e2      	macw %d2u,%a2u,>>,%a3@&,%a3,%acc1
+    1be8:	a6d3 a6f2      	macw %d2u,%a2u,>>,%a3@&,%a3,%acc2
+    1bec:	a413 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d2,%acc1
+    1bf0:	a493 a6f2      	macw %d2u,%a2u,>>,%a3@&,%d2,%acc2
+    1bf4:	ae53 a6e2      	macw %d2u,%a2u,>>,%a3@&,%sp,%acc1
+    1bf8:	aed3 a6f2      	macw %d2u,%a2u,>>,%a3@&,%sp,%acc2
+    1bfc:	a21a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d1,%acc1
+    1c00:	a29a a6d2      	macw %d2u,%a2u,>>,%a2@\+,%d1,%acc2
+    1c04:	a65a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%a3,%acc1
+    1c08:	a6da a6d2      	macw %d2u,%a2u,>>,%a2@\+,%a3,%acc2
+    1c0c:	a41a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d2,%acc1
+    1c10:	a49a a6d2      	macw %d2u,%a2u,>>,%a2@\+,%d2,%acc2
+    1c14:	ae5a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%sp,%acc1
+    1c18:	aeda a6d2      	macw %d2u,%a2u,>>,%a2@\+,%sp,%acc2
+    1c1c:	a21a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d1,%acc1
+    1c20:	a29a a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%d1,%acc2
+    1c24:	a65a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%a3,%acc1
+    1c28:	a6da a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%a3,%acc2
+    1c2c:	a41a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d2,%acc1
+    1c30:	a49a a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%d2,%acc2
+    1c34:	ae5a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%sp,%acc1
+    1c38:	aeda a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%sp,%acc2
+    1c3c:	a22e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1,%acc1
+    1c42:	a2ae a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1,%acc2
+    1c48:	a66e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3,%acc1
+    1c4e:	a6ee a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3,%acc2
+    1c54:	a42e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2,%acc1
+    1c5a:	a4ae a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2,%acc2
+    1c60:	ae6e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp,%acc1
+    1c66:	aeee a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp,%acc2
+    1c6c:	a22e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    1c72:	a2ae a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    1c78:	a66e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    1c7e:	a6ee a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    1c84:	a42e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    1c8a:	a4ae a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    1c90:	ae6e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    1c96:	aeee a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    1c9c:	a221 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d1,%acc1
+    1ca0:	a2a1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%d1,%acc2
+    1ca4:	a661 a6c2      	macw %d2u,%a2u,>>,%a1@-,%a3,%acc1
+    1ca8:	a6e1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%a3,%acc2
+    1cac:	a421 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d2,%acc1
+    1cb0:	a4a1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%d2,%acc2
+    1cb4:	ae61 a6c2      	macw %d2u,%a2u,>>,%a1@-,%sp,%acc1
+    1cb8:	aee1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%sp,%acc2
+    1cbc:	a221 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d1,%acc1
+    1cc0:	a2a1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%d1,%acc2
+    1cc4:	a661 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%a3,%acc1
+    1cc8:	a6e1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%a3,%acc2
+    1ccc:	a421 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d2,%acc1
+    1cd0:	a4a1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%d2,%acc2
+    1cd4:	ae61 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%sp,%acc1
+    1cd8:	aee1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%sp,%acc2
+    1cdc:	a213 a2c2      	macw %d2u,%a2u,<<,%a3@,%d1,%acc1
+    1ce0:	a293 a2d2      	macw %d2u,%a2u,<<,%a3@,%d1,%acc2
+    1ce4:	a653 a2c2      	macw %d2u,%a2u,<<,%a3@,%a3,%acc1
+    1ce8:	a6d3 a2d2      	macw %d2u,%a2u,<<,%a3@,%a3,%acc2
+    1cec:	a413 a2c2      	macw %d2u,%a2u,<<,%a3@,%d2,%acc1
+    1cf0:	a493 a2d2      	macw %d2u,%a2u,<<,%a3@,%d2,%acc2
+    1cf4:	ae53 a2c2      	macw %d2u,%a2u,<<,%a3@,%sp,%acc1
+    1cf8:	aed3 a2d2      	macw %d2u,%a2u,<<,%a3@,%sp,%acc2
+    1cfc:	a213 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d1,%acc1
+    1d00:	a293 a2f2      	macw %d2u,%a2u,<<,%a3@&,%d1,%acc2
+    1d04:	a653 a2e2      	macw %d2u,%a2u,<<,%a3@&,%a3,%acc1
+    1d08:	a6d3 a2f2      	macw %d2u,%a2u,<<,%a3@&,%a3,%acc2
+    1d0c:	a413 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d2,%acc1
+    1d10:	a493 a2f2      	macw %d2u,%a2u,<<,%a3@&,%d2,%acc2
+    1d14:	ae53 a2e2      	macw %d2u,%a2u,<<,%a3@&,%sp,%acc1
+    1d18:	aed3 a2f2      	macw %d2u,%a2u,<<,%a3@&,%sp,%acc2
+    1d1c:	a21a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d1,%acc1
+    1d20:	a29a a2d2      	macw %d2u,%a2u,<<,%a2@\+,%d1,%acc2
+    1d24:	a65a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%a3,%acc1
+    1d28:	a6da a2d2      	macw %d2u,%a2u,<<,%a2@\+,%a3,%acc2
+    1d2c:	a41a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d2,%acc1
+    1d30:	a49a a2d2      	macw %d2u,%a2u,<<,%a2@\+,%d2,%acc2
+    1d34:	ae5a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%sp,%acc1
+    1d38:	aeda a2d2      	macw %d2u,%a2u,<<,%a2@\+,%sp,%acc2
+    1d3c:	a21a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d1,%acc1
+    1d40:	a29a a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%d1,%acc2
+    1d44:	a65a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%a3,%acc1
+    1d48:	a6da a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%a3,%acc2
+    1d4c:	a41a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d2,%acc1
+    1d50:	a49a a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%d2,%acc2
+    1d54:	ae5a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%sp,%acc1
+    1d58:	aeda a2f2      	macw %d2u,%a2u,<<,%a2@\+&,%sp,%acc2
+    1d5c:	a22e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1,%acc1
+    1d62:	a2ae a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1,%acc2
+    1d68:	a66e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3,%acc1
+    1d6e:	a6ee a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3,%acc2
+    1d74:	a42e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2,%acc1
+    1d7a:	a4ae a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2,%acc2
+    1d80:	ae6e a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp,%acc1
+    1d86:	aeee a2d2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp,%acc2
+    1d8c:	a22e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    1d92:	a2ae a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    1d98:	a66e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    1d9e:	a6ee a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    1da4:	a42e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    1daa:	a4ae a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    1db0:	ae6e a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    1db6:	aeee a2f2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    1dbc:	a221 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d1,%acc1
+    1dc0:	a2a1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%d1,%acc2
+    1dc4:	a661 a2c2      	macw %d2u,%a2u,<<,%a1@-,%a3,%acc1
+    1dc8:	a6e1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%a3,%acc2
+    1dcc:	a421 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d2,%acc1
+    1dd0:	a4a1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%d2,%acc2
+    1dd4:	ae61 a2c2      	macw %d2u,%a2u,<<,%a1@-,%sp,%acc1
+    1dd8:	aee1 a2d2      	macw %d2u,%a2u,<<,%a1@-,%sp,%acc2
+    1ddc:	a221 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d1,%acc1
+    1de0:	a2a1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%d1,%acc2
+    1de4:	a661 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%a3,%acc1
+    1de8:	a6e1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%a3,%acc2
+    1dec:	a421 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d2,%acc1
+    1df0:	a4a1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%d2,%acc2
+    1df4:	ae61 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%sp,%acc1
+    1df8:	aee1 a2f2      	macw %d2u,%a2u,<<,%a1@-&,%sp,%acc2
+    1dfc:	a213 a6c2      	macw %d2u,%a2u,>>,%a3@,%d1,%acc1
+    1e00:	a293 a6d2      	macw %d2u,%a2u,>>,%a3@,%d1,%acc2
+    1e04:	a653 a6c2      	macw %d2u,%a2u,>>,%a3@,%a3,%acc1
+    1e08:	a6d3 a6d2      	macw %d2u,%a2u,>>,%a3@,%a3,%acc2
+    1e0c:	a413 a6c2      	macw %d2u,%a2u,>>,%a3@,%d2,%acc1
+    1e10:	a493 a6d2      	macw %d2u,%a2u,>>,%a3@,%d2,%acc2
+    1e14:	ae53 a6c2      	macw %d2u,%a2u,>>,%a3@,%sp,%acc1
+    1e18:	aed3 a6d2      	macw %d2u,%a2u,>>,%a3@,%sp,%acc2
+    1e1c:	a213 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d1,%acc1
+    1e20:	a293 a6f2      	macw %d2u,%a2u,>>,%a3@&,%d1,%acc2
+    1e24:	a653 a6e2      	macw %d2u,%a2u,>>,%a3@&,%a3,%acc1
+    1e28:	a6d3 a6f2      	macw %d2u,%a2u,>>,%a3@&,%a3,%acc2
+    1e2c:	a413 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d2,%acc1
+    1e30:	a493 a6f2      	macw %d2u,%a2u,>>,%a3@&,%d2,%acc2
+    1e34:	ae53 a6e2      	macw %d2u,%a2u,>>,%a3@&,%sp,%acc1
+    1e38:	aed3 a6f2      	macw %d2u,%a2u,>>,%a3@&,%sp,%acc2
+    1e3c:	a21a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d1,%acc1
+    1e40:	a29a a6d2      	macw %d2u,%a2u,>>,%a2@\+,%d1,%acc2
+    1e44:	a65a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%a3,%acc1
+    1e48:	a6da a6d2      	macw %d2u,%a2u,>>,%a2@\+,%a3,%acc2
+    1e4c:	a41a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d2,%acc1
+    1e50:	a49a a6d2      	macw %d2u,%a2u,>>,%a2@\+,%d2,%acc2
+    1e54:	ae5a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%sp,%acc1
+    1e58:	aeda a6d2      	macw %d2u,%a2u,>>,%a2@\+,%sp,%acc2
+    1e5c:	a21a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d1,%acc1
+    1e60:	a29a a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%d1,%acc2
+    1e64:	a65a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%a3,%acc1
+    1e68:	a6da a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%a3,%acc2
+    1e6c:	a41a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d2,%acc1
+    1e70:	a49a a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%d2,%acc2
+    1e74:	ae5a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%sp,%acc1
+    1e78:	aeda a6f2      	macw %d2u,%a2u,>>,%a2@\+&,%sp,%acc2
+    1e7c:	a22e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1,%acc1
+    1e82:	a2ae a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1,%acc2
+    1e88:	a66e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3,%acc1
+    1e8e:	a6ee a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3,%acc2
+    1e94:	a42e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2,%acc1
+    1e9a:	a4ae a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2,%acc2
+    1ea0:	ae6e a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp,%acc1
+    1ea6:	aeee a6d2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp,%acc2
+    1eac:	a22e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    1eb2:	a2ae a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    1eb8:	a66e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    1ebe:	a6ee a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    1ec4:	a42e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    1eca:	a4ae a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    1ed0:	ae6e a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    1ed6:	aeee a6f2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    1edc:	a221 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d1,%acc1
+    1ee0:	a2a1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%d1,%acc2
+    1ee4:	a661 a6c2      	macw %d2u,%a2u,>>,%a1@-,%a3,%acc1
+    1ee8:	a6e1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%a3,%acc2
+    1eec:	a421 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d2,%acc1
+    1ef0:	a4a1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%d2,%acc2
+    1ef4:	ae61 a6c2      	macw %d2u,%a2u,>>,%a1@-,%sp,%acc1
+    1ef8:	aee1 a6d2      	macw %d2u,%a2u,>>,%a1@-,%sp,%acc2
+    1efc:	a221 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d1,%acc1
+    1f00:	a2a1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%d1,%acc2
+    1f04:	a661 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%a3,%acc1
+    1f08:	a6e1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%a3,%acc2
+    1f0c:	a421 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d2,%acc1
+    1f10:	a4a1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%d2,%acc2
+    1f14:	ae61 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%sp,%acc1
+    1f18:	aee1 a6f2      	macw %d2u,%a2u,>>,%a1@-&,%sp,%acc2
+    1f1c:	a213 3042      	macw %d2u,%d3l,%a3@,%d1,%acc1
+    1f20:	a293 3052      	macw %d2u,%d3l,%a3@,%d1,%acc2
+    1f24:	a653 3042      	macw %d2u,%d3l,%a3@,%a3,%acc1
+    1f28:	a6d3 3052      	macw %d2u,%d3l,%a3@,%a3,%acc2
+    1f2c:	a413 3042      	macw %d2u,%d3l,%a3@,%d2,%acc1
+    1f30:	a493 3052      	macw %d2u,%d3l,%a3@,%d2,%acc2
+    1f34:	ae53 3042      	macw %d2u,%d3l,%a3@,%sp,%acc1
+    1f38:	aed3 3052      	macw %d2u,%d3l,%a3@,%sp,%acc2
+    1f3c:	a213 3062      	macw %d2u,%d3l,%a3@&,%d1,%acc1
+    1f40:	a293 3072      	macw %d2u,%d3l,%a3@&,%d1,%acc2
+    1f44:	a653 3062      	macw %d2u,%d3l,%a3@&,%a3,%acc1
+    1f48:	a6d3 3072      	macw %d2u,%d3l,%a3@&,%a3,%acc2
+    1f4c:	a413 3062      	macw %d2u,%d3l,%a3@&,%d2,%acc1
+    1f50:	a493 3072      	macw %d2u,%d3l,%a3@&,%d2,%acc2
+    1f54:	ae53 3062      	macw %d2u,%d3l,%a3@&,%sp,%acc1
+    1f58:	aed3 3072      	macw %d2u,%d3l,%a3@&,%sp,%acc2
+    1f5c:	a21a 3042      	macw %d2u,%d3l,%a2@\+,%d1,%acc1
+    1f60:	a29a 3052      	macw %d2u,%d3l,%a2@\+,%d1,%acc2
+    1f64:	a65a 3042      	macw %d2u,%d3l,%a2@\+,%a3,%acc1
+    1f68:	a6da 3052      	macw %d2u,%d3l,%a2@\+,%a3,%acc2
+    1f6c:	a41a 3042      	macw %d2u,%d3l,%a2@\+,%d2,%acc1
+    1f70:	a49a 3052      	macw %d2u,%d3l,%a2@\+,%d2,%acc2
+    1f74:	ae5a 3042      	macw %d2u,%d3l,%a2@\+,%sp,%acc1
+    1f78:	aeda 3052      	macw %d2u,%d3l,%a2@\+,%sp,%acc2
+    1f7c:	a21a 3062      	macw %d2u,%d3l,%a2@\+&,%d1,%acc1
+    1f80:	a29a 3072      	macw %d2u,%d3l,%a2@\+&,%d1,%acc2
+    1f84:	a65a 3062      	macw %d2u,%d3l,%a2@\+&,%a3,%acc1
+    1f88:	a6da 3072      	macw %d2u,%d3l,%a2@\+&,%a3,%acc2
+    1f8c:	a41a 3062      	macw %d2u,%d3l,%a2@\+&,%d2,%acc1
+    1f90:	a49a 3072      	macw %d2u,%d3l,%a2@\+&,%d2,%acc2
+    1f94:	ae5a 3062      	macw %d2u,%d3l,%a2@\+&,%sp,%acc1
+    1f98:	aeda 3072      	macw %d2u,%d3l,%a2@\+&,%sp,%acc2
+    1f9c:	a22e 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%d1,%acc1
+    1fa2:	a2ae 3052 000a 	macw %d2u,%d3l,%fp@\(10\),%d1,%acc2
+    1fa8:	a66e 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%a3,%acc1
+    1fae:	a6ee 3052 000a 	macw %d2u,%d3l,%fp@\(10\),%a3,%acc2
+    1fb4:	a42e 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%d2,%acc1
+    1fba:	a4ae 3052 000a 	macw %d2u,%d3l,%fp@\(10\),%d2,%acc2
+    1fc0:	ae6e 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%sp,%acc1
+    1fc6:	aeee 3052 000a 	macw %d2u,%d3l,%fp@\(10\),%sp,%acc2
+    1fcc:	a22e 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d1,%acc1
+    1fd2:	a2ae 3072 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d1,%acc2
+    1fd8:	a66e 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%a3,%acc1
+    1fde:	a6ee 3072 000a 	macw %d2u,%d3l,%fp@\(10\)&,%a3,%acc2
+    1fe4:	a42e 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d2,%acc1
+    1fea:	a4ae 3072 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d2,%acc2
+    1ff0:	ae6e 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%sp,%acc1
+    1ff6:	aeee 3072 000a 	macw %d2u,%d3l,%fp@\(10\)&,%sp,%acc2
+    1ffc:	a221 3042      	macw %d2u,%d3l,%a1@-,%d1,%acc1
+    2000:	a2a1 3052      	macw %d2u,%d3l,%a1@-,%d1,%acc2
+    2004:	a661 3042      	macw %d2u,%d3l,%a1@-,%a3,%acc1
+    2008:	a6e1 3052      	macw %d2u,%d3l,%a1@-,%a3,%acc2
+    200c:	a421 3042      	macw %d2u,%d3l,%a1@-,%d2,%acc1
+    2010:	a4a1 3052      	macw %d2u,%d3l,%a1@-,%d2,%acc2
+    2014:	ae61 3042      	macw %d2u,%d3l,%a1@-,%sp,%acc1
+    2018:	aee1 3052      	macw %d2u,%d3l,%a1@-,%sp,%acc2
+    201c:	a221 3062      	macw %d2u,%d3l,%a1@-&,%d1,%acc1
+    2020:	a2a1 3072      	macw %d2u,%d3l,%a1@-&,%d1,%acc2
+    2024:	a661 3062      	macw %d2u,%d3l,%a1@-&,%a3,%acc1
+    2028:	a6e1 3072      	macw %d2u,%d3l,%a1@-&,%a3,%acc2
+    202c:	a421 3062      	macw %d2u,%d3l,%a1@-&,%d2,%acc1
+    2030:	a4a1 3072      	macw %d2u,%d3l,%a1@-&,%d2,%acc2
+    2034:	ae61 3062      	macw %d2u,%d3l,%a1@-&,%sp,%acc1
+    2038:	aee1 3072      	macw %d2u,%d3l,%a1@-&,%sp,%acc2
+    203c:	a213 3242      	macw %d2u,%d3l,<<,%a3@,%d1,%acc1
+    2040:	a293 3252      	macw %d2u,%d3l,<<,%a3@,%d1,%acc2
+    2044:	a653 3242      	macw %d2u,%d3l,<<,%a3@,%a3,%acc1
+    2048:	a6d3 3252      	macw %d2u,%d3l,<<,%a3@,%a3,%acc2
+    204c:	a413 3242      	macw %d2u,%d3l,<<,%a3@,%d2,%acc1
+    2050:	a493 3252      	macw %d2u,%d3l,<<,%a3@,%d2,%acc2
+    2054:	ae53 3242      	macw %d2u,%d3l,<<,%a3@,%sp,%acc1
+    2058:	aed3 3252      	macw %d2u,%d3l,<<,%a3@,%sp,%acc2
+    205c:	a213 3262      	macw %d2u,%d3l,<<,%a3@&,%d1,%acc1
+    2060:	a293 3272      	macw %d2u,%d3l,<<,%a3@&,%d1,%acc2
+    2064:	a653 3262      	macw %d2u,%d3l,<<,%a3@&,%a3,%acc1
+    2068:	a6d3 3272      	macw %d2u,%d3l,<<,%a3@&,%a3,%acc2
+    206c:	a413 3262      	macw %d2u,%d3l,<<,%a3@&,%d2,%acc1
+    2070:	a493 3272      	macw %d2u,%d3l,<<,%a3@&,%d2,%acc2
+    2074:	ae53 3262      	macw %d2u,%d3l,<<,%a3@&,%sp,%acc1
+    2078:	aed3 3272      	macw %d2u,%d3l,<<,%a3@&,%sp,%acc2
+    207c:	a21a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d1,%acc1
+    2080:	a29a 3252      	macw %d2u,%d3l,<<,%a2@\+,%d1,%acc2
+    2084:	a65a 3242      	macw %d2u,%d3l,<<,%a2@\+,%a3,%acc1
+    2088:	a6da 3252      	macw %d2u,%d3l,<<,%a2@\+,%a3,%acc2
+    208c:	a41a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d2,%acc1
+    2090:	a49a 3252      	macw %d2u,%d3l,<<,%a2@\+,%d2,%acc2
+    2094:	ae5a 3242      	macw %d2u,%d3l,<<,%a2@\+,%sp,%acc1
+    2098:	aeda 3252      	macw %d2u,%d3l,<<,%a2@\+,%sp,%acc2
+    209c:	a21a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d1,%acc1
+    20a0:	a29a 3272      	macw %d2u,%d3l,<<,%a2@\+&,%d1,%acc2
+    20a4:	a65a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%a3,%acc1
+    20a8:	a6da 3272      	macw %d2u,%d3l,<<,%a2@\+&,%a3,%acc2
+    20ac:	a41a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d2,%acc1
+    20b0:	a49a 3272      	macw %d2u,%d3l,<<,%a2@\+&,%d2,%acc2
+    20b4:	ae5a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%sp,%acc1
+    20b8:	aeda 3272      	macw %d2u,%d3l,<<,%a2@\+&,%sp,%acc2
+    20bc:	a22e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1,%acc1
+    20c2:	a2ae 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1,%acc2
+    20c8:	a66e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3,%acc1
+    20ce:	a6ee 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3,%acc2
+    20d4:	a42e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2,%acc1
+    20da:	a4ae 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2,%acc2
+    20e0:	ae6e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp,%acc1
+    20e6:	aeee 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp,%acc2
+    20ec:	a22e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    20f2:	a2ae 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    20f8:	a66e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    20fe:	a6ee 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    2104:	a42e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    210a:	a4ae 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    2110:	ae6e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    2116:	aeee 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    211c:	a221 3242      	macw %d2u,%d3l,<<,%a1@-,%d1,%acc1
+    2120:	a2a1 3252      	macw %d2u,%d3l,<<,%a1@-,%d1,%acc2
+    2124:	a661 3242      	macw %d2u,%d3l,<<,%a1@-,%a3,%acc1
+    2128:	a6e1 3252      	macw %d2u,%d3l,<<,%a1@-,%a3,%acc2
+    212c:	a421 3242      	macw %d2u,%d3l,<<,%a1@-,%d2,%acc1
+    2130:	a4a1 3252      	macw %d2u,%d3l,<<,%a1@-,%d2,%acc2
+    2134:	ae61 3242      	macw %d2u,%d3l,<<,%a1@-,%sp,%acc1
+    2138:	aee1 3252      	macw %d2u,%d3l,<<,%a1@-,%sp,%acc2
+    213c:	a221 3262      	macw %d2u,%d3l,<<,%a1@-&,%d1,%acc1
+    2140:	a2a1 3272      	macw %d2u,%d3l,<<,%a1@-&,%d1,%acc2
+    2144:	a661 3262      	macw %d2u,%d3l,<<,%a1@-&,%a3,%acc1
+    2148:	a6e1 3272      	macw %d2u,%d3l,<<,%a1@-&,%a3,%acc2
+    214c:	a421 3262      	macw %d2u,%d3l,<<,%a1@-&,%d2,%acc1
+    2150:	a4a1 3272      	macw %d2u,%d3l,<<,%a1@-&,%d2,%acc2
+    2154:	ae61 3262      	macw %d2u,%d3l,<<,%a1@-&,%sp,%acc1
+    2158:	aee1 3272      	macw %d2u,%d3l,<<,%a1@-&,%sp,%acc2
+    215c:	a213 3642      	macw %d2u,%d3l,>>,%a3@,%d1,%acc1
+    2160:	a293 3652      	macw %d2u,%d3l,>>,%a3@,%d1,%acc2
+    2164:	a653 3642      	macw %d2u,%d3l,>>,%a3@,%a3,%acc1
+    2168:	a6d3 3652      	macw %d2u,%d3l,>>,%a3@,%a3,%acc2
+    216c:	a413 3642      	macw %d2u,%d3l,>>,%a3@,%d2,%acc1
+    2170:	a493 3652      	macw %d2u,%d3l,>>,%a3@,%d2,%acc2
+    2174:	ae53 3642      	macw %d2u,%d3l,>>,%a3@,%sp,%acc1
+    2178:	aed3 3652      	macw %d2u,%d3l,>>,%a3@,%sp,%acc2
+    217c:	a213 3662      	macw %d2u,%d3l,>>,%a3@&,%d1,%acc1
+    2180:	a293 3672      	macw %d2u,%d3l,>>,%a3@&,%d1,%acc2
+    2184:	a653 3662      	macw %d2u,%d3l,>>,%a3@&,%a3,%acc1
+    2188:	a6d3 3672      	macw %d2u,%d3l,>>,%a3@&,%a3,%acc2
+    218c:	a413 3662      	macw %d2u,%d3l,>>,%a3@&,%d2,%acc1
+    2190:	a493 3672      	macw %d2u,%d3l,>>,%a3@&,%d2,%acc2
+    2194:	ae53 3662      	macw %d2u,%d3l,>>,%a3@&,%sp,%acc1
+    2198:	aed3 3672      	macw %d2u,%d3l,>>,%a3@&,%sp,%acc2
+    219c:	a21a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d1,%acc1
+    21a0:	a29a 3652      	macw %d2u,%d3l,>>,%a2@\+,%d1,%acc2
+    21a4:	a65a 3642      	macw %d2u,%d3l,>>,%a2@\+,%a3,%acc1
+    21a8:	a6da 3652      	macw %d2u,%d3l,>>,%a2@\+,%a3,%acc2
+    21ac:	a41a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d2,%acc1
+    21b0:	a49a 3652      	macw %d2u,%d3l,>>,%a2@\+,%d2,%acc2
+    21b4:	ae5a 3642      	macw %d2u,%d3l,>>,%a2@\+,%sp,%acc1
+    21b8:	aeda 3652      	macw %d2u,%d3l,>>,%a2@\+,%sp,%acc2
+    21bc:	a21a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d1,%acc1
+    21c0:	a29a 3672      	macw %d2u,%d3l,>>,%a2@\+&,%d1,%acc2
+    21c4:	a65a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%a3,%acc1
+    21c8:	a6da 3672      	macw %d2u,%d3l,>>,%a2@\+&,%a3,%acc2
+    21cc:	a41a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d2,%acc1
+    21d0:	a49a 3672      	macw %d2u,%d3l,>>,%a2@\+&,%d2,%acc2
+    21d4:	ae5a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%sp,%acc1
+    21d8:	aeda 3672      	macw %d2u,%d3l,>>,%a2@\+&,%sp,%acc2
+    21dc:	a22e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1,%acc1
+    21e2:	a2ae 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1,%acc2
+    21e8:	a66e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3,%acc1
+    21ee:	a6ee 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3,%acc2
+    21f4:	a42e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2,%acc1
+    21fa:	a4ae 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2,%acc2
+    2200:	ae6e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp,%acc1
+    2206:	aeee 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp,%acc2
+    220c:	a22e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    2212:	a2ae 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    2218:	a66e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    221e:	a6ee 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    2224:	a42e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    222a:	a4ae 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    2230:	ae6e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    2236:	aeee 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    223c:	a221 3642      	macw %d2u,%d3l,>>,%a1@-,%d1,%acc1
+    2240:	a2a1 3652      	macw %d2u,%d3l,>>,%a1@-,%d1,%acc2
+    2244:	a661 3642      	macw %d2u,%d3l,>>,%a1@-,%a3,%acc1
+    2248:	a6e1 3652      	macw %d2u,%d3l,>>,%a1@-,%a3,%acc2
+    224c:	a421 3642      	macw %d2u,%d3l,>>,%a1@-,%d2,%acc1
+    2250:	a4a1 3652      	macw %d2u,%d3l,>>,%a1@-,%d2,%acc2
+    2254:	ae61 3642      	macw %d2u,%d3l,>>,%a1@-,%sp,%acc1
+    2258:	aee1 3652      	macw %d2u,%d3l,>>,%a1@-,%sp,%acc2
+    225c:	a221 3662      	macw %d2u,%d3l,>>,%a1@-&,%d1,%acc1
+    2260:	a2a1 3672      	macw %d2u,%d3l,>>,%a1@-&,%d1,%acc2
+    2264:	a661 3662      	macw %d2u,%d3l,>>,%a1@-&,%a3,%acc1
+    2268:	a6e1 3672      	macw %d2u,%d3l,>>,%a1@-&,%a3,%acc2
+    226c:	a421 3662      	macw %d2u,%d3l,>>,%a1@-&,%d2,%acc1
+    2270:	a4a1 3672      	macw %d2u,%d3l,>>,%a1@-&,%d2,%acc2
+    2274:	ae61 3662      	macw %d2u,%d3l,>>,%a1@-&,%sp,%acc1
+    2278:	aee1 3672      	macw %d2u,%d3l,>>,%a1@-&,%sp,%acc2
+    227c:	a213 3242      	macw %d2u,%d3l,<<,%a3@,%d1,%acc1
+    2280:	a293 3252      	macw %d2u,%d3l,<<,%a3@,%d1,%acc2
+    2284:	a653 3242      	macw %d2u,%d3l,<<,%a3@,%a3,%acc1
+    2288:	a6d3 3252      	macw %d2u,%d3l,<<,%a3@,%a3,%acc2
+    228c:	a413 3242      	macw %d2u,%d3l,<<,%a3@,%d2,%acc1
+    2290:	a493 3252      	macw %d2u,%d3l,<<,%a3@,%d2,%acc2
+    2294:	ae53 3242      	macw %d2u,%d3l,<<,%a3@,%sp,%acc1
+    2298:	aed3 3252      	macw %d2u,%d3l,<<,%a3@,%sp,%acc2
+    229c:	a213 3262      	macw %d2u,%d3l,<<,%a3@&,%d1,%acc1
+    22a0:	a293 3272      	macw %d2u,%d3l,<<,%a3@&,%d1,%acc2
+    22a4:	a653 3262      	macw %d2u,%d3l,<<,%a3@&,%a3,%acc1
+    22a8:	a6d3 3272      	macw %d2u,%d3l,<<,%a3@&,%a3,%acc2
+    22ac:	a413 3262      	macw %d2u,%d3l,<<,%a3@&,%d2,%acc1
+    22b0:	a493 3272      	macw %d2u,%d3l,<<,%a3@&,%d2,%acc2
+    22b4:	ae53 3262      	macw %d2u,%d3l,<<,%a3@&,%sp,%acc1
+    22b8:	aed3 3272      	macw %d2u,%d3l,<<,%a3@&,%sp,%acc2
+    22bc:	a21a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d1,%acc1
+    22c0:	a29a 3252      	macw %d2u,%d3l,<<,%a2@\+,%d1,%acc2
+    22c4:	a65a 3242      	macw %d2u,%d3l,<<,%a2@\+,%a3,%acc1
+    22c8:	a6da 3252      	macw %d2u,%d3l,<<,%a2@\+,%a3,%acc2
+    22cc:	a41a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d2,%acc1
+    22d0:	a49a 3252      	macw %d2u,%d3l,<<,%a2@\+,%d2,%acc2
+    22d4:	ae5a 3242      	macw %d2u,%d3l,<<,%a2@\+,%sp,%acc1
+    22d8:	aeda 3252      	macw %d2u,%d3l,<<,%a2@\+,%sp,%acc2
+    22dc:	a21a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d1,%acc1
+    22e0:	a29a 3272      	macw %d2u,%d3l,<<,%a2@\+&,%d1,%acc2
+    22e4:	a65a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%a3,%acc1
+    22e8:	a6da 3272      	macw %d2u,%d3l,<<,%a2@\+&,%a3,%acc2
+    22ec:	a41a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d2,%acc1
+    22f0:	a49a 3272      	macw %d2u,%d3l,<<,%a2@\+&,%d2,%acc2
+    22f4:	ae5a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%sp,%acc1
+    22f8:	aeda 3272      	macw %d2u,%d3l,<<,%a2@\+&,%sp,%acc2
+    22fc:	a22e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1,%acc1
+    2302:	a2ae 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1,%acc2
+    2308:	a66e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3,%acc1
+    230e:	a6ee 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3,%acc2
+    2314:	a42e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2,%acc1
+    231a:	a4ae 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2,%acc2
+    2320:	ae6e 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp,%acc1
+    2326:	aeee 3252 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp,%acc2
+    232c:	a22e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    2332:	a2ae 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    2338:	a66e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    233e:	a6ee 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    2344:	a42e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    234a:	a4ae 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    2350:	ae6e 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    2356:	aeee 3272 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    235c:	a221 3242      	macw %d2u,%d3l,<<,%a1@-,%d1,%acc1
+    2360:	a2a1 3252      	macw %d2u,%d3l,<<,%a1@-,%d1,%acc2
+    2364:	a661 3242      	macw %d2u,%d3l,<<,%a1@-,%a3,%acc1
+    2368:	a6e1 3252      	macw %d2u,%d3l,<<,%a1@-,%a3,%acc2
+    236c:	a421 3242      	macw %d2u,%d3l,<<,%a1@-,%d2,%acc1
+    2370:	a4a1 3252      	macw %d2u,%d3l,<<,%a1@-,%d2,%acc2
+    2374:	ae61 3242      	macw %d2u,%d3l,<<,%a1@-,%sp,%acc1
+    2378:	aee1 3252      	macw %d2u,%d3l,<<,%a1@-,%sp,%acc2
+    237c:	a221 3262      	macw %d2u,%d3l,<<,%a1@-&,%d1,%acc1
+    2380:	a2a1 3272      	macw %d2u,%d3l,<<,%a1@-&,%d1,%acc2
+    2384:	a661 3262      	macw %d2u,%d3l,<<,%a1@-&,%a3,%acc1
+    2388:	a6e1 3272      	macw %d2u,%d3l,<<,%a1@-&,%a3,%acc2
+    238c:	a421 3262      	macw %d2u,%d3l,<<,%a1@-&,%d2,%acc1
+    2390:	a4a1 3272      	macw %d2u,%d3l,<<,%a1@-&,%d2,%acc2
+    2394:	ae61 3262      	macw %d2u,%d3l,<<,%a1@-&,%sp,%acc1
+    2398:	aee1 3272      	macw %d2u,%d3l,<<,%a1@-&,%sp,%acc2
+    239c:	a213 3642      	macw %d2u,%d3l,>>,%a3@,%d1,%acc1
+    23a0:	a293 3652      	macw %d2u,%d3l,>>,%a3@,%d1,%acc2
+    23a4:	a653 3642      	macw %d2u,%d3l,>>,%a3@,%a3,%acc1
+    23a8:	a6d3 3652      	macw %d2u,%d3l,>>,%a3@,%a3,%acc2
+    23ac:	a413 3642      	macw %d2u,%d3l,>>,%a3@,%d2,%acc1
+    23b0:	a493 3652      	macw %d2u,%d3l,>>,%a3@,%d2,%acc2
+    23b4:	ae53 3642      	macw %d2u,%d3l,>>,%a3@,%sp,%acc1
+    23b8:	aed3 3652      	macw %d2u,%d3l,>>,%a3@,%sp,%acc2
+    23bc:	a213 3662      	macw %d2u,%d3l,>>,%a3@&,%d1,%acc1
+    23c0:	a293 3672      	macw %d2u,%d3l,>>,%a3@&,%d1,%acc2
+    23c4:	a653 3662      	macw %d2u,%d3l,>>,%a3@&,%a3,%acc1
+    23c8:	a6d3 3672      	macw %d2u,%d3l,>>,%a3@&,%a3,%acc2
+    23cc:	a413 3662      	macw %d2u,%d3l,>>,%a3@&,%d2,%acc1
+    23d0:	a493 3672      	macw %d2u,%d3l,>>,%a3@&,%d2,%acc2
+    23d4:	ae53 3662      	macw %d2u,%d3l,>>,%a3@&,%sp,%acc1
+    23d8:	aed3 3672      	macw %d2u,%d3l,>>,%a3@&,%sp,%acc2
+    23dc:	a21a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d1,%acc1
+    23e0:	a29a 3652      	macw %d2u,%d3l,>>,%a2@\+,%d1,%acc2
+    23e4:	a65a 3642      	macw %d2u,%d3l,>>,%a2@\+,%a3,%acc1
+    23e8:	a6da 3652      	macw %d2u,%d3l,>>,%a2@\+,%a3,%acc2
+    23ec:	a41a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d2,%acc1
+    23f0:	a49a 3652      	macw %d2u,%d3l,>>,%a2@\+,%d2,%acc2
+    23f4:	ae5a 3642      	macw %d2u,%d3l,>>,%a2@\+,%sp,%acc1
+    23f8:	aeda 3652      	macw %d2u,%d3l,>>,%a2@\+,%sp,%acc2
+    23fc:	a21a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d1,%acc1
+    2400:	a29a 3672      	macw %d2u,%d3l,>>,%a2@\+&,%d1,%acc2
+    2404:	a65a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%a3,%acc1
+    2408:	a6da 3672      	macw %d2u,%d3l,>>,%a2@\+&,%a3,%acc2
+    240c:	a41a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d2,%acc1
+    2410:	a49a 3672      	macw %d2u,%d3l,>>,%a2@\+&,%d2,%acc2
+    2414:	ae5a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%sp,%acc1
+    2418:	aeda 3672      	macw %d2u,%d3l,>>,%a2@\+&,%sp,%acc2
+    241c:	a22e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1,%acc1
+    2422:	a2ae 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1,%acc2
+    2428:	a66e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3,%acc1
+    242e:	a6ee 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3,%acc2
+    2434:	a42e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2,%acc1
+    243a:	a4ae 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2,%acc2
+    2440:	ae6e 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp,%acc1
+    2446:	aeee 3652 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp,%acc2
+    244c:	a22e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    2452:	a2ae 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    2458:	a66e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    245e:	a6ee 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    2464:	a42e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    246a:	a4ae 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    2470:	ae6e 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    2476:	aeee 3672 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    247c:	a221 3642      	macw %d2u,%d3l,>>,%a1@-,%d1,%acc1
+    2480:	a2a1 3652      	macw %d2u,%d3l,>>,%a1@-,%d1,%acc2
+    2484:	a661 3642      	macw %d2u,%d3l,>>,%a1@-,%a3,%acc1
+    2488:	a6e1 3652      	macw %d2u,%d3l,>>,%a1@-,%a3,%acc2
+    248c:	a421 3642      	macw %d2u,%d3l,>>,%a1@-,%d2,%acc1
+    2490:	a4a1 3652      	macw %d2u,%d3l,>>,%a1@-,%d2,%acc2
+    2494:	ae61 3642      	macw %d2u,%d3l,>>,%a1@-,%sp,%acc1
+    2498:	aee1 3652      	macw %d2u,%d3l,>>,%a1@-,%sp,%acc2
+    249c:	a221 3662      	macw %d2u,%d3l,>>,%a1@-&,%d1,%acc1
+    24a0:	a2a1 3672      	macw %d2u,%d3l,>>,%a1@-&,%d1,%acc2
+    24a4:	a661 3662      	macw %d2u,%d3l,>>,%a1@-&,%a3,%acc1
+    24a8:	a6e1 3672      	macw %d2u,%d3l,>>,%a1@-&,%a3,%acc2
+    24ac:	a421 3662      	macw %d2u,%d3l,>>,%a1@-&,%d2,%acc1
+    24b0:	a4a1 3672      	macw %d2u,%d3l,>>,%a1@-&,%d2,%acc2
+    24b4:	ae61 3662      	macw %d2u,%d3l,>>,%a1@-&,%sp,%acc1
+    24b8:	aee1 3672      	macw %d2u,%d3l,>>,%a1@-&,%sp,%acc2
+    24bc:	a213 f0c2      	macw %d2u,%a7u,%a3@,%d1,%acc1
+    24c0:	a293 f0d2      	macw %d2u,%a7u,%a3@,%d1,%acc2
+    24c4:	a653 f0c2      	macw %d2u,%a7u,%a3@,%a3,%acc1
+    24c8:	a6d3 f0d2      	macw %d2u,%a7u,%a3@,%a3,%acc2
+    24cc:	a413 f0c2      	macw %d2u,%a7u,%a3@,%d2,%acc1
+    24d0:	a493 f0d2      	macw %d2u,%a7u,%a3@,%d2,%acc2
+    24d4:	ae53 f0c2      	macw %d2u,%a7u,%a3@,%sp,%acc1
+    24d8:	aed3 f0d2      	macw %d2u,%a7u,%a3@,%sp,%acc2
+    24dc:	a213 f0e2      	macw %d2u,%a7u,%a3@&,%d1,%acc1
+    24e0:	a293 f0f2      	macw %d2u,%a7u,%a3@&,%d1,%acc2
+    24e4:	a653 f0e2      	macw %d2u,%a7u,%a3@&,%a3,%acc1
+    24e8:	a6d3 f0f2      	macw %d2u,%a7u,%a3@&,%a3,%acc2
+    24ec:	a413 f0e2      	macw %d2u,%a7u,%a3@&,%d2,%acc1
+    24f0:	a493 f0f2      	macw %d2u,%a7u,%a3@&,%d2,%acc2
+    24f4:	ae53 f0e2      	macw %d2u,%a7u,%a3@&,%sp,%acc1
+    24f8:	aed3 f0f2      	macw %d2u,%a7u,%a3@&,%sp,%acc2
+    24fc:	a21a f0c2      	macw %d2u,%a7u,%a2@\+,%d1,%acc1
+    2500:	a29a f0d2      	macw %d2u,%a7u,%a2@\+,%d1,%acc2
+    2504:	a65a f0c2      	macw %d2u,%a7u,%a2@\+,%a3,%acc1
+    2508:	a6da f0d2      	macw %d2u,%a7u,%a2@\+,%a3,%acc2
+    250c:	a41a f0c2      	macw %d2u,%a7u,%a2@\+,%d2,%acc1
+    2510:	a49a f0d2      	macw %d2u,%a7u,%a2@\+,%d2,%acc2
+    2514:	ae5a f0c2      	macw %d2u,%a7u,%a2@\+,%sp,%acc1
+    2518:	aeda f0d2      	macw %d2u,%a7u,%a2@\+,%sp,%acc2
+    251c:	a21a f0e2      	macw %d2u,%a7u,%a2@\+&,%d1,%acc1
+    2520:	a29a f0f2      	macw %d2u,%a7u,%a2@\+&,%d1,%acc2
+    2524:	a65a f0e2      	macw %d2u,%a7u,%a2@\+&,%a3,%acc1
+    2528:	a6da f0f2      	macw %d2u,%a7u,%a2@\+&,%a3,%acc2
+    252c:	a41a f0e2      	macw %d2u,%a7u,%a2@\+&,%d2,%acc1
+    2530:	a49a f0f2      	macw %d2u,%a7u,%a2@\+&,%d2,%acc2
+    2534:	ae5a f0e2      	macw %d2u,%a7u,%a2@\+&,%sp,%acc1
+    2538:	aeda f0f2      	macw %d2u,%a7u,%a2@\+&,%sp,%acc2
+    253c:	a22e f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%d1,%acc1
+    2542:	a2ae f0d2 000a 	macw %d2u,%a7u,%fp@\(10\),%d1,%acc2
+    2548:	a66e f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%a3,%acc1
+    254e:	a6ee f0d2 000a 	macw %d2u,%a7u,%fp@\(10\),%a3,%acc2
+    2554:	a42e f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%d2,%acc1
+    255a:	a4ae f0d2 000a 	macw %d2u,%a7u,%fp@\(10\),%d2,%acc2
+    2560:	ae6e f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%sp,%acc1
+    2566:	aeee f0d2 000a 	macw %d2u,%a7u,%fp@\(10\),%sp,%acc2
+    256c:	a22e f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d1,%acc1
+    2572:	a2ae f0f2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d1,%acc2
+    2578:	a66e f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%a3,%acc1
+    257e:	a6ee f0f2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%a3,%acc2
+    2584:	a42e f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d2,%acc1
+    258a:	a4ae f0f2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d2,%acc2
+    2590:	ae6e f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%sp,%acc1
+    2596:	aeee f0f2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%sp,%acc2
+    259c:	a221 f0c2      	macw %d2u,%a7u,%a1@-,%d1,%acc1
+    25a0:	a2a1 f0d2      	macw %d2u,%a7u,%a1@-,%d1,%acc2
+    25a4:	a661 f0c2      	macw %d2u,%a7u,%a1@-,%a3,%acc1
+    25a8:	a6e1 f0d2      	macw %d2u,%a7u,%a1@-,%a3,%acc2
+    25ac:	a421 f0c2      	macw %d2u,%a7u,%a1@-,%d2,%acc1
+    25b0:	a4a1 f0d2      	macw %d2u,%a7u,%a1@-,%d2,%acc2
+    25b4:	ae61 f0c2      	macw %d2u,%a7u,%a1@-,%sp,%acc1
+    25b8:	aee1 f0d2      	macw %d2u,%a7u,%a1@-,%sp,%acc2
+    25bc:	a221 f0e2      	macw %d2u,%a7u,%a1@-&,%d1,%acc1
+    25c0:	a2a1 f0f2      	macw %d2u,%a7u,%a1@-&,%d1,%acc2
+    25c4:	a661 f0e2      	macw %d2u,%a7u,%a1@-&,%a3,%acc1
+    25c8:	a6e1 f0f2      	macw %d2u,%a7u,%a1@-&,%a3,%acc2
+    25cc:	a421 f0e2      	macw %d2u,%a7u,%a1@-&,%d2,%acc1
+    25d0:	a4a1 f0f2      	macw %d2u,%a7u,%a1@-&,%d2,%acc2
+    25d4:	ae61 f0e2      	macw %d2u,%a7u,%a1@-&,%sp,%acc1
+    25d8:	aee1 f0f2      	macw %d2u,%a7u,%a1@-&,%sp,%acc2
+    25dc:	a213 f2c2      	macw %d2u,%a7u,<<,%a3@,%d1,%acc1
+    25e0:	a293 f2d2      	macw %d2u,%a7u,<<,%a3@,%d1,%acc2
+    25e4:	a653 f2c2      	macw %d2u,%a7u,<<,%a3@,%a3,%acc1
+    25e8:	a6d3 f2d2      	macw %d2u,%a7u,<<,%a3@,%a3,%acc2
+    25ec:	a413 f2c2      	macw %d2u,%a7u,<<,%a3@,%d2,%acc1
+    25f0:	a493 f2d2      	macw %d2u,%a7u,<<,%a3@,%d2,%acc2
+    25f4:	ae53 f2c2      	macw %d2u,%a7u,<<,%a3@,%sp,%acc1
+    25f8:	aed3 f2d2      	macw %d2u,%a7u,<<,%a3@,%sp,%acc2
+    25fc:	a213 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d1,%acc1
+    2600:	a293 f2f2      	macw %d2u,%a7u,<<,%a3@&,%d1,%acc2
+    2604:	a653 f2e2      	macw %d2u,%a7u,<<,%a3@&,%a3,%acc1
+    2608:	a6d3 f2f2      	macw %d2u,%a7u,<<,%a3@&,%a3,%acc2
+    260c:	a413 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d2,%acc1
+    2610:	a493 f2f2      	macw %d2u,%a7u,<<,%a3@&,%d2,%acc2
+    2614:	ae53 f2e2      	macw %d2u,%a7u,<<,%a3@&,%sp,%acc1
+    2618:	aed3 f2f2      	macw %d2u,%a7u,<<,%a3@&,%sp,%acc2
+    261c:	a21a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d1,%acc1
+    2620:	a29a f2d2      	macw %d2u,%a7u,<<,%a2@\+,%d1,%acc2
+    2624:	a65a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%a3,%acc1
+    2628:	a6da f2d2      	macw %d2u,%a7u,<<,%a2@\+,%a3,%acc2
+    262c:	a41a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d2,%acc1
+    2630:	a49a f2d2      	macw %d2u,%a7u,<<,%a2@\+,%d2,%acc2
+    2634:	ae5a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%sp,%acc1
+    2638:	aeda f2d2      	macw %d2u,%a7u,<<,%a2@\+,%sp,%acc2
+    263c:	a21a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d1,%acc1
+    2640:	a29a f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%d1,%acc2
+    2644:	a65a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%a3,%acc1
+    2648:	a6da f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%a3,%acc2
+    264c:	a41a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d2,%acc1
+    2650:	a49a f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%d2,%acc2
+    2654:	ae5a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%sp,%acc1
+    2658:	aeda f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%sp,%acc2
+    265c:	a22e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1,%acc1
+    2662:	a2ae f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1,%acc2
+    2668:	a66e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3,%acc1
+    266e:	a6ee f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3,%acc2
+    2674:	a42e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2,%acc1
+    267a:	a4ae f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2,%acc2
+    2680:	ae6e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp,%acc1
+    2686:	aeee f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp,%acc2
+    268c:	a22e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    2692:	a2ae f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    2698:	a66e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    269e:	a6ee f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    26a4:	a42e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    26aa:	a4ae f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    26b0:	ae6e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    26b6:	aeee f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    26bc:	a221 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d1,%acc1
+    26c0:	a2a1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%d1,%acc2
+    26c4:	a661 f2c2      	macw %d2u,%a7u,<<,%a1@-,%a3,%acc1
+    26c8:	a6e1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%a3,%acc2
+    26cc:	a421 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d2,%acc1
+    26d0:	a4a1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%d2,%acc2
+    26d4:	ae61 f2c2      	macw %d2u,%a7u,<<,%a1@-,%sp,%acc1
+    26d8:	aee1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%sp,%acc2
+    26dc:	a221 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d1,%acc1
+    26e0:	a2a1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%d1,%acc2
+    26e4:	a661 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%a3,%acc1
+    26e8:	a6e1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%a3,%acc2
+    26ec:	a421 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d2,%acc1
+    26f0:	a4a1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%d2,%acc2
+    26f4:	ae61 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%sp,%acc1
+    26f8:	aee1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%sp,%acc2
+    26fc:	a213 f6c2      	macw %d2u,%a7u,>>,%a3@,%d1,%acc1
+    2700:	a293 f6d2      	macw %d2u,%a7u,>>,%a3@,%d1,%acc2
+    2704:	a653 f6c2      	macw %d2u,%a7u,>>,%a3@,%a3,%acc1
+    2708:	a6d3 f6d2      	macw %d2u,%a7u,>>,%a3@,%a3,%acc2
+    270c:	a413 f6c2      	macw %d2u,%a7u,>>,%a3@,%d2,%acc1
+    2710:	a493 f6d2      	macw %d2u,%a7u,>>,%a3@,%d2,%acc2
+    2714:	ae53 f6c2      	macw %d2u,%a7u,>>,%a3@,%sp,%acc1
+    2718:	aed3 f6d2      	macw %d2u,%a7u,>>,%a3@,%sp,%acc2
+    271c:	a213 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d1,%acc1
+    2720:	a293 f6f2      	macw %d2u,%a7u,>>,%a3@&,%d1,%acc2
+    2724:	a653 f6e2      	macw %d2u,%a7u,>>,%a3@&,%a3,%acc1
+    2728:	a6d3 f6f2      	macw %d2u,%a7u,>>,%a3@&,%a3,%acc2
+    272c:	a413 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d2,%acc1
+    2730:	a493 f6f2      	macw %d2u,%a7u,>>,%a3@&,%d2,%acc2
+    2734:	ae53 f6e2      	macw %d2u,%a7u,>>,%a3@&,%sp,%acc1
+    2738:	aed3 f6f2      	macw %d2u,%a7u,>>,%a3@&,%sp,%acc2
+    273c:	a21a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d1,%acc1
+    2740:	a29a f6d2      	macw %d2u,%a7u,>>,%a2@\+,%d1,%acc2
+    2744:	a65a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%a3,%acc1
+    2748:	a6da f6d2      	macw %d2u,%a7u,>>,%a2@\+,%a3,%acc2
+    274c:	a41a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d2,%acc1
+    2750:	a49a f6d2      	macw %d2u,%a7u,>>,%a2@\+,%d2,%acc2
+    2754:	ae5a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%sp,%acc1
+    2758:	aeda f6d2      	macw %d2u,%a7u,>>,%a2@\+,%sp,%acc2
+    275c:	a21a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d1,%acc1
+    2760:	a29a f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%d1,%acc2
+    2764:	a65a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%a3,%acc1
+    2768:	a6da f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%a3,%acc2
+    276c:	a41a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d2,%acc1
+    2770:	a49a f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%d2,%acc2
+    2774:	ae5a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%sp,%acc1
+    2778:	aeda f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%sp,%acc2
+    277c:	a22e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1,%acc1
+    2782:	a2ae f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1,%acc2
+    2788:	a66e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3,%acc1
+    278e:	a6ee f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3,%acc2
+    2794:	a42e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2,%acc1
+    279a:	a4ae f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2,%acc2
+    27a0:	ae6e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp,%acc1
+    27a6:	aeee f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp,%acc2
+    27ac:	a22e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    27b2:	a2ae f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    27b8:	a66e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    27be:	a6ee f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    27c4:	a42e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    27ca:	a4ae f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    27d0:	ae6e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    27d6:	aeee f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    27dc:	a221 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d1,%acc1
+    27e0:	a2a1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%d1,%acc2
+    27e4:	a661 f6c2      	macw %d2u,%a7u,>>,%a1@-,%a3,%acc1
+    27e8:	a6e1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%a3,%acc2
+    27ec:	a421 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d2,%acc1
+    27f0:	a4a1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%d2,%acc2
+    27f4:	ae61 f6c2      	macw %d2u,%a7u,>>,%a1@-,%sp,%acc1
+    27f8:	aee1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%sp,%acc2
+    27fc:	a221 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d1,%acc1
+    2800:	a2a1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%d1,%acc2
+    2804:	a661 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%a3,%acc1
+    2808:	a6e1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%a3,%acc2
+    280c:	a421 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d2,%acc1
+    2810:	a4a1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%d2,%acc2
+    2814:	ae61 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%sp,%acc1
+    2818:	aee1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%sp,%acc2
+    281c:	a213 f2c2      	macw %d2u,%a7u,<<,%a3@,%d1,%acc1
+    2820:	a293 f2d2      	macw %d2u,%a7u,<<,%a3@,%d1,%acc2
+    2824:	a653 f2c2      	macw %d2u,%a7u,<<,%a3@,%a3,%acc1
+    2828:	a6d3 f2d2      	macw %d2u,%a7u,<<,%a3@,%a3,%acc2
+    282c:	a413 f2c2      	macw %d2u,%a7u,<<,%a3@,%d2,%acc1
+    2830:	a493 f2d2      	macw %d2u,%a7u,<<,%a3@,%d2,%acc2
+    2834:	ae53 f2c2      	macw %d2u,%a7u,<<,%a3@,%sp,%acc1
+    2838:	aed3 f2d2      	macw %d2u,%a7u,<<,%a3@,%sp,%acc2
+    283c:	a213 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d1,%acc1
+    2840:	a293 f2f2      	macw %d2u,%a7u,<<,%a3@&,%d1,%acc2
+    2844:	a653 f2e2      	macw %d2u,%a7u,<<,%a3@&,%a3,%acc1
+    2848:	a6d3 f2f2      	macw %d2u,%a7u,<<,%a3@&,%a3,%acc2
+    284c:	a413 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d2,%acc1
+    2850:	a493 f2f2      	macw %d2u,%a7u,<<,%a3@&,%d2,%acc2
+    2854:	ae53 f2e2      	macw %d2u,%a7u,<<,%a3@&,%sp,%acc1
+    2858:	aed3 f2f2      	macw %d2u,%a7u,<<,%a3@&,%sp,%acc2
+    285c:	a21a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d1,%acc1
+    2860:	a29a f2d2      	macw %d2u,%a7u,<<,%a2@\+,%d1,%acc2
+    2864:	a65a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%a3,%acc1
+    2868:	a6da f2d2      	macw %d2u,%a7u,<<,%a2@\+,%a3,%acc2
+    286c:	a41a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d2,%acc1
+    2870:	a49a f2d2      	macw %d2u,%a7u,<<,%a2@\+,%d2,%acc2
+    2874:	ae5a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%sp,%acc1
+    2878:	aeda f2d2      	macw %d2u,%a7u,<<,%a2@\+,%sp,%acc2
+    287c:	a21a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d1,%acc1
+    2880:	a29a f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%d1,%acc2
+    2884:	a65a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%a3,%acc1
+    2888:	a6da f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%a3,%acc2
+    288c:	a41a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d2,%acc1
+    2890:	a49a f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%d2,%acc2
+    2894:	ae5a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%sp,%acc1
+    2898:	aeda f2f2      	macw %d2u,%a7u,<<,%a2@\+&,%sp,%acc2
+    289c:	a22e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1,%acc1
+    28a2:	a2ae f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1,%acc2
+    28a8:	a66e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3,%acc1
+    28ae:	a6ee f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3,%acc2
+    28b4:	a42e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2,%acc1
+    28ba:	a4ae f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2,%acc2
+    28c0:	ae6e f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp,%acc1
+    28c6:	aeee f2d2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp,%acc2
+    28cc:	a22e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    28d2:	a2ae f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    28d8:	a66e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    28de:	a6ee f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    28e4:	a42e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    28ea:	a4ae f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    28f0:	ae6e f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    28f6:	aeee f2f2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    28fc:	a221 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d1,%acc1
+    2900:	a2a1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%d1,%acc2
+    2904:	a661 f2c2      	macw %d2u,%a7u,<<,%a1@-,%a3,%acc1
+    2908:	a6e1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%a3,%acc2
+    290c:	a421 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d2,%acc1
+    2910:	a4a1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%d2,%acc2
+    2914:	ae61 f2c2      	macw %d2u,%a7u,<<,%a1@-,%sp,%acc1
+    2918:	aee1 f2d2      	macw %d2u,%a7u,<<,%a1@-,%sp,%acc2
+    291c:	a221 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d1,%acc1
+    2920:	a2a1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%d1,%acc2
+    2924:	a661 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%a3,%acc1
+    2928:	a6e1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%a3,%acc2
+    292c:	a421 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d2,%acc1
+    2930:	a4a1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%d2,%acc2
+    2934:	ae61 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%sp,%acc1
+    2938:	aee1 f2f2      	macw %d2u,%a7u,<<,%a1@-&,%sp,%acc2
+    293c:	a213 f6c2      	macw %d2u,%a7u,>>,%a3@,%d1,%acc1
+    2940:	a293 f6d2      	macw %d2u,%a7u,>>,%a3@,%d1,%acc2
+    2944:	a653 f6c2      	macw %d2u,%a7u,>>,%a3@,%a3,%acc1
+    2948:	a6d3 f6d2      	macw %d2u,%a7u,>>,%a3@,%a3,%acc2
+    294c:	a413 f6c2      	macw %d2u,%a7u,>>,%a3@,%d2,%acc1
+    2950:	a493 f6d2      	macw %d2u,%a7u,>>,%a3@,%d2,%acc2
+    2954:	ae53 f6c2      	macw %d2u,%a7u,>>,%a3@,%sp,%acc1
+    2958:	aed3 f6d2      	macw %d2u,%a7u,>>,%a3@,%sp,%acc2
+    295c:	a213 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d1,%acc1
+    2960:	a293 f6f2      	macw %d2u,%a7u,>>,%a3@&,%d1,%acc2
+    2964:	a653 f6e2      	macw %d2u,%a7u,>>,%a3@&,%a3,%acc1
+    2968:	a6d3 f6f2      	macw %d2u,%a7u,>>,%a3@&,%a3,%acc2
+    296c:	a413 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d2,%acc1
+    2970:	a493 f6f2      	macw %d2u,%a7u,>>,%a3@&,%d2,%acc2
+    2974:	ae53 f6e2      	macw %d2u,%a7u,>>,%a3@&,%sp,%acc1
+    2978:	aed3 f6f2      	macw %d2u,%a7u,>>,%a3@&,%sp,%acc2
+    297c:	a21a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d1,%acc1
+    2980:	a29a f6d2      	macw %d2u,%a7u,>>,%a2@\+,%d1,%acc2
+    2984:	a65a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%a3,%acc1
+    2988:	a6da f6d2      	macw %d2u,%a7u,>>,%a2@\+,%a3,%acc2
+    298c:	a41a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d2,%acc1
+    2990:	a49a f6d2      	macw %d2u,%a7u,>>,%a2@\+,%d2,%acc2
+    2994:	ae5a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%sp,%acc1
+    2998:	aeda f6d2      	macw %d2u,%a7u,>>,%a2@\+,%sp,%acc2
+    299c:	a21a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d1,%acc1
+    29a0:	a29a f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%d1,%acc2
+    29a4:	a65a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%a3,%acc1
+    29a8:	a6da f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%a3,%acc2
+    29ac:	a41a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d2,%acc1
+    29b0:	a49a f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%d2,%acc2
+    29b4:	ae5a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%sp,%acc1
+    29b8:	aeda f6f2      	macw %d2u,%a7u,>>,%a2@\+&,%sp,%acc2
+    29bc:	a22e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1,%acc1
+    29c2:	a2ae f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1,%acc2
+    29c8:	a66e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3,%acc1
+    29ce:	a6ee f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3,%acc2
+    29d4:	a42e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2,%acc1
+    29da:	a4ae f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2,%acc2
+    29e0:	ae6e f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp,%acc1
+    29e6:	aeee f6d2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp,%acc2
+    29ec:	a22e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    29f2:	a2ae f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    29f8:	a66e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    29fe:	a6ee f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    2a04:	a42e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    2a0a:	a4ae f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    2a10:	ae6e f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    2a16:	aeee f6f2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    2a1c:	a221 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d1,%acc1
+    2a20:	a2a1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%d1,%acc2
+    2a24:	a661 f6c2      	macw %d2u,%a7u,>>,%a1@-,%a3,%acc1
+    2a28:	a6e1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%a3,%acc2
+    2a2c:	a421 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d2,%acc1
+    2a30:	a4a1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%d2,%acc2
+    2a34:	ae61 f6c2      	macw %d2u,%a7u,>>,%a1@-,%sp,%acc1
+    2a38:	aee1 f6d2      	macw %d2u,%a7u,>>,%a1@-,%sp,%acc2
+    2a3c:	a221 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d1,%acc1
+    2a40:	a2a1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%d1,%acc2
+    2a44:	a661 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%a3,%acc1
+    2a48:	a6e1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%a3,%acc2
+    2a4c:	a421 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d2,%acc1
+    2a50:	a4a1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%d2,%acc2
+    2a54:	ae61 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%sp,%acc1
+    2a58:	aee1 f6f2      	macw %d2u,%a7u,>>,%a1@-&,%sp,%acc2
+    2a5c:	a213 1042      	macw %d2u,%d1l,%a3@,%d1,%acc1
+    2a60:	a293 1052      	macw %d2u,%d1l,%a3@,%d1,%acc2
+    2a64:	a653 1042      	macw %d2u,%d1l,%a3@,%a3,%acc1
+    2a68:	a6d3 1052      	macw %d2u,%d1l,%a3@,%a3,%acc2
+    2a6c:	a413 1042      	macw %d2u,%d1l,%a3@,%d2,%acc1
+    2a70:	a493 1052      	macw %d2u,%d1l,%a3@,%d2,%acc2
+    2a74:	ae53 1042      	macw %d2u,%d1l,%a3@,%sp,%acc1
+    2a78:	aed3 1052      	macw %d2u,%d1l,%a3@,%sp,%acc2
+    2a7c:	a213 1062      	macw %d2u,%d1l,%a3@&,%d1,%acc1
+    2a80:	a293 1072      	macw %d2u,%d1l,%a3@&,%d1,%acc2
+    2a84:	a653 1062      	macw %d2u,%d1l,%a3@&,%a3,%acc1
+    2a88:	a6d3 1072      	macw %d2u,%d1l,%a3@&,%a3,%acc2
+    2a8c:	a413 1062      	macw %d2u,%d1l,%a3@&,%d2,%acc1
+    2a90:	a493 1072      	macw %d2u,%d1l,%a3@&,%d2,%acc2
+    2a94:	ae53 1062      	macw %d2u,%d1l,%a3@&,%sp,%acc1
+    2a98:	aed3 1072      	macw %d2u,%d1l,%a3@&,%sp,%acc2
+    2a9c:	a21a 1042      	macw %d2u,%d1l,%a2@\+,%d1,%acc1
+    2aa0:	a29a 1052      	macw %d2u,%d1l,%a2@\+,%d1,%acc2
+    2aa4:	a65a 1042      	macw %d2u,%d1l,%a2@\+,%a3,%acc1
+    2aa8:	a6da 1052      	macw %d2u,%d1l,%a2@\+,%a3,%acc2
+    2aac:	a41a 1042      	macw %d2u,%d1l,%a2@\+,%d2,%acc1
+    2ab0:	a49a 1052      	macw %d2u,%d1l,%a2@\+,%d2,%acc2
+    2ab4:	ae5a 1042      	macw %d2u,%d1l,%a2@\+,%sp,%acc1
+    2ab8:	aeda 1052      	macw %d2u,%d1l,%a2@\+,%sp,%acc2
+    2abc:	a21a 1062      	macw %d2u,%d1l,%a2@\+&,%d1,%acc1
+    2ac0:	a29a 1072      	macw %d2u,%d1l,%a2@\+&,%d1,%acc2
+    2ac4:	a65a 1062      	macw %d2u,%d1l,%a2@\+&,%a3,%acc1
+    2ac8:	a6da 1072      	macw %d2u,%d1l,%a2@\+&,%a3,%acc2
+    2acc:	a41a 1062      	macw %d2u,%d1l,%a2@\+&,%d2,%acc1
+    2ad0:	a49a 1072      	macw %d2u,%d1l,%a2@\+&,%d2,%acc2
+    2ad4:	ae5a 1062      	macw %d2u,%d1l,%a2@\+&,%sp,%acc1
+    2ad8:	aeda 1072      	macw %d2u,%d1l,%a2@\+&,%sp,%acc2
+    2adc:	a22e 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%d1,%acc1
+    2ae2:	a2ae 1052 000a 	macw %d2u,%d1l,%fp@\(10\),%d1,%acc2
+    2ae8:	a66e 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%a3,%acc1
+    2aee:	a6ee 1052 000a 	macw %d2u,%d1l,%fp@\(10\),%a3,%acc2
+    2af4:	a42e 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%d2,%acc1
+    2afa:	a4ae 1052 000a 	macw %d2u,%d1l,%fp@\(10\),%d2,%acc2
+    2b00:	ae6e 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%sp,%acc1
+    2b06:	aeee 1052 000a 	macw %d2u,%d1l,%fp@\(10\),%sp,%acc2
+    2b0c:	a22e 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d1,%acc1
+    2b12:	a2ae 1072 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d1,%acc2
+    2b18:	a66e 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%a3,%acc1
+    2b1e:	a6ee 1072 000a 	macw %d2u,%d1l,%fp@\(10\)&,%a3,%acc2
+    2b24:	a42e 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d2,%acc1
+    2b2a:	a4ae 1072 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d2,%acc2
+    2b30:	ae6e 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%sp,%acc1
+    2b36:	aeee 1072 000a 	macw %d2u,%d1l,%fp@\(10\)&,%sp,%acc2
+    2b3c:	a221 1042      	macw %d2u,%d1l,%a1@-,%d1,%acc1
+    2b40:	a2a1 1052      	macw %d2u,%d1l,%a1@-,%d1,%acc2
+    2b44:	a661 1042      	macw %d2u,%d1l,%a1@-,%a3,%acc1
+    2b48:	a6e1 1052      	macw %d2u,%d1l,%a1@-,%a3,%acc2
+    2b4c:	a421 1042      	macw %d2u,%d1l,%a1@-,%d2,%acc1
+    2b50:	a4a1 1052      	macw %d2u,%d1l,%a1@-,%d2,%acc2
+    2b54:	ae61 1042      	macw %d2u,%d1l,%a1@-,%sp,%acc1
+    2b58:	aee1 1052      	macw %d2u,%d1l,%a1@-,%sp,%acc2
+    2b5c:	a221 1062      	macw %d2u,%d1l,%a1@-&,%d1,%acc1
+    2b60:	a2a1 1072      	macw %d2u,%d1l,%a1@-&,%d1,%acc2
+    2b64:	a661 1062      	macw %d2u,%d1l,%a1@-&,%a3,%acc1
+    2b68:	a6e1 1072      	macw %d2u,%d1l,%a1@-&,%a3,%acc2
+    2b6c:	a421 1062      	macw %d2u,%d1l,%a1@-&,%d2,%acc1
+    2b70:	a4a1 1072      	macw %d2u,%d1l,%a1@-&,%d2,%acc2
+    2b74:	ae61 1062      	macw %d2u,%d1l,%a1@-&,%sp,%acc1
+    2b78:	aee1 1072      	macw %d2u,%d1l,%a1@-&,%sp,%acc2
+    2b7c:	a213 1242      	macw %d2u,%d1l,<<,%a3@,%d1,%acc1
+    2b80:	a293 1252      	macw %d2u,%d1l,<<,%a3@,%d1,%acc2
+    2b84:	a653 1242      	macw %d2u,%d1l,<<,%a3@,%a3,%acc1
+    2b88:	a6d3 1252      	macw %d2u,%d1l,<<,%a3@,%a3,%acc2
+    2b8c:	a413 1242      	macw %d2u,%d1l,<<,%a3@,%d2,%acc1
+    2b90:	a493 1252      	macw %d2u,%d1l,<<,%a3@,%d2,%acc2
+    2b94:	ae53 1242      	macw %d2u,%d1l,<<,%a3@,%sp,%acc1
+    2b98:	aed3 1252      	macw %d2u,%d1l,<<,%a3@,%sp,%acc2
+    2b9c:	a213 1262      	macw %d2u,%d1l,<<,%a3@&,%d1,%acc1
+    2ba0:	a293 1272      	macw %d2u,%d1l,<<,%a3@&,%d1,%acc2
+    2ba4:	a653 1262      	macw %d2u,%d1l,<<,%a3@&,%a3,%acc1
+    2ba8:	a6d3 1272      	macw %d2u,%d1l,<<,%a3@&,%a3,%acc2
+    2bac:	a413 1262      	macw %d2u,%d1l,<<,%a3@&,%d2,%acc1
+    2bb0:	a493 1272      	macw %d2u,%d1l,<<,%a3@&,%d2,%acc2
+    2bb4:	ae53 1262      	macw %d2u,%d1l,<<,%a3@&,%sp,%acc1
+    2bb8:	aed3 1272      	macw %d2u,%d1l,<<,%a3@&,%sp,%acc2
+    2bbc:	a21a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d1,%acc1
+    2bc0:	a29a 1252      	macw %d2u,%d1l,<<,%a2@\+,%d1,%acc2
+    2bc4:	a65a 1242      	macw %d2u,%d1l,<<,%a2@\+,%a3,%acc1
+    2bc8:	a6da 1252      	macw %d2u,%d1l,<<,%a2@\+,%a3,%acc2
+    2bcc:	a41a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d2,%acc1
+    2bd0:	a49a 1252      	macw %d2u,%d1l,<<,%a2@\+,%d2,%acc2
+    2bd4:	ae5a 1242      	macw %d2u,%d1l,<<,%a2@\+,%sp,%acc1
+    2bd8:	aeda 1252      	macw %d2u,%d1l,<<,%a2@\+,%sp,%acc2
+    2bdc:	a21a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d1,%acc1
+    2be0:	a29a 1272      	macw %d2u,%d1l,<<,%a2@\+&,%d1,%acc2
+    2be4:	a65a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%a3,%acc1
+    2be8:	a6da 1272      	macw %d2u,%d1l,<<,%a2@\+&,%a3,%acc2
+    2bec:	a41a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d2,%acc1
+    2bf0:	a49a 1272      	macw %d2u,%d1l,<<,%a2@\+&,%d2,%acc2
+    2bf4:	ae5a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%sp,%acc1
+    2bf8:	aeda 1272      	macw %d2u,%d1l,<<,%a2@\+&,%sp,%acc2
+    2bfc:	a22e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1,%acc1
+    2c02:	a2ae 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1,%acc2
+    2c08:	a66e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3,%acc1
+    2c0e:	a6ee 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3,%acc2
+    2c14:	a42e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2,%acc1
+    2c1a:	a4ae 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2,%acc2
+    2c20:	ae6e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp,%acc1
+    2c26:	aeee 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp,%acc2
+    2c2c:	a22e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    2c32:	a2ae 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    2c38:	a66e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    2c3e:	a6ee 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    2c44:	a42e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    2c4a:	a4ae 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    2c50:	ae6e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    2c56:	aeee 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    2c5c:	a221 1242      	macw %d2u,%d1l,<<,%a1@-,%d1,%acc1
+    2c60:	a2a1 1252      	macw %d2u,%d1l,<<,%a1@-,%d1,%acc2
+    2c64:	a661 1242      	macw %d2u,%d1l,<<,%a1@-,%a3,%acc1
+    2c68:	a6e1 1252      	macw %d2u,%d1l,<<,%a1@-,%a3,%acc2
+    2c6c:	a421 1242      	macw %d2u,%d1l,<<,%a1@-,%d2,%acc1
+    2c70:	a4a1 1252      	macw %d2u,%d1l,<<,%a1@-,%d2,%acc2
+    2c74:	ae61 1242      	macw %d2u,%d1l,<<,%a1@-,%sp,%acc1
+    2c78:	aee1 1252      	macw %d2u,%d1l,<<,%a1@-,%sp,%acc2
+    2c7c:	a221 1262      	macw %d2u,%d1l,<<,%a1@-&,%d1,%acc1
+    2c80:	a2a1 1272      	macw %d2u,%d1l,<<,%a1@-&,%d1,%acc2
+    2c84:	a661 1262      	macw %d2u,%d1l,<<,%a1@-&,%a3,%acc1
+    2c88:	a6e1 1272      	macw %d2u,%d1l,<<,%a1@-&,%a3,%acc2
+    2c8c:	a421 1262      	macw %d2u,%d1l,<<,%a1@-&,%d2,%acc1
+    2c90:	a4a1 1272      	macw %d2u,%d1l,<<,%a1@-&,%d2,%acc2
+    2c94:	ae61 1262      	macw %d2u,%d1l,<<,%a1@-&,%sp,%acc1
+    2c98:	aee1 1272      	macw %d2u,%d1l,<<,%a1@-&,%sp,%acc2
+    2c9c:	a213 1642      	macw %d2u,%d1l,>>,%a3@,%d1,%acc1
+    2ca0:	a293 1652      	macw %d2u,%d1l,>>,%a3@,%d1,%acc2
+    2ca4:	a653 1642      	macw %d2u,%d1l,>>,%a3@,%a3,%acc1
+    2ca8:	a6d3 1652      	macw %d2u,%d1l,>>,%a3@,%a3,%acc2
+    2cac:	a413 1642      	macw %d2u,%d1l,>>,%a3@,%d2,%acc1
+    2cb0:	a493 1652      	macw %d2u,%d1l,>>,%a3@,%d2,%acc2
+    2cb4:	ae53 1642      	macw %d2u,%d1l,>>,%a3@,%sp,%acc1
+    2cb8:	aed3 1652      	macw %d2u,%d1l,>>,%a3@,%sp,%acc2
+    2cbc:	a213 1662      	macw %d2u,%d1l,>>,%a3@&,%d1,%acc1
+    2cc0:	a293 1672      	macw %d2u,%d1l,>>,%a3@&,%d1,%acc2
+    2cc4:	a653 1662      	macw %d2u,%d1l,>>,%a3@&,%a3,%acc1
+    2cc8:	a6d3 1672      	macw %d2u,%d1l,>>,%a3@&,%a3,%acc2
+    2ccc:	a413 1662      	macw %d2u,%d1l,>>,%a3@&,%d2,%acc1
+    2cd0:	a493 1672      	macw %d2u,%d1l,>>,%a3@&,%d2,%acc2
+    2cd4:	ae53 1662      	macw %d2u,%d1l,>>,%a3@&,%sp,%acc1
+    2cd8:	aed3 1672      	macw %d2u,%d1l,>>,%a3@&,%sp,%acc2
+    2cdc:	a21a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d1,%acc1
+    2ce0:	a29a 1652      	macw %d2u,%d1l,>>,%a2@\+,%d1,%acc2
+    2ce4:	a65a 1642      	macw %d2u,%d1l,>>,%a2@\+,%a3,%acc1
+    2ce8:	a6da 1652      	macw %d2u,%d1l,>>,%a2@\+,%a3,%acc2
+    2cec:	a41a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d2,%acc1
+    2cf0:	a49a 1652      	macw %d2u,%d1l,>>,%a2@\+,%d2,%acc2
+    2cf4:	ae5a 1642      	macw %d2u,%d1l,>>,%a2@\+,%sp,%acc1
+    2cf8:	aeda 1652      	macw %d2u,%d1l,>>,%a2@\+,%sp,%acc2
+    2cfc:	a21a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d1,%acc1
+    2d00:	a29a 1672      	macw %d2u,%d1l,>>,%a2@\+&,%d1,%acc2
+    2d04:	a65a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%a3,%acc1
+    2d08:	a6da 1672      	macw %d2u,%d1l,>>,%a2@\+&,%a3,%acc2
+    2d0c:	a41a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d2,%acc1
+    2d10:	a49a 1672      	macw %d2u,%d1l,>>,%a2@\+&,%d2,%acc2
+    2d14:	ae5a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%sp,%acc1
+    2d18:	aeda 1672      	macw %d2u,%d1l,>>,%a2@\+&,%sp,%acc2
+    2d1c:	a22e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1,%acc1
+    2d22:	a2ae 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1,%acc2
+    2d28:	a66e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3,%acc1
+    2d2e:	a6ee 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3,%acc2
+    2d34:	a42e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2,%acc1
+    2d3a:	a4ae 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2,%acc2
+    2d40:	ae6e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp,%acc1
+    2d46:	aeee 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp,%acc2
+    2d4c:	a22e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    2d52:	a2ae 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    2d58:	a66e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    2d5e:	a6ee 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    2d64:	a42e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    2d6a:	a4ae 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    2d70:	ae6e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    2d76:	aeee 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    2d7c:	a221 1642      	macw %d2u,%d1l,>>,%a1@-,%d1,%acc1
+    2d80:	a2a1 1652      	macw %d2u,%d1l,>>,%a1@-,%d1,%acc2
+    2d84:	a661 1642      	macw %d2u,%d1l,>>,%a1@-,%a3,%acc1
+    2d88:	a6e1 1652      	macw %d2u,%d1l,>>,%a1@-,%a3,%acc2
+    2d8c:	a421 1642      	macw %d2u,%d1l,>>,%a1@-,%d2,%acc1
+    2d90:	a4a1 1652      	macw %d2u,%d1l,>>,%a1@-,%d2,%acc2
+    2d94:	ae61 1642      	macw %d2u,%d1l,>>,%a1@-,%sp,%acc1
+    2d98:	aee1 1652      	macw %d2u,%d1l,>>,%a1@-,%sp,%acc2
+    2d9c:	a221 1662      	macw %d2u,%d1l,>>,%a1@-&,%d1,%acc1
+    2da0:	a2a1 1672      	macw %d2u,%d1l,>>,%a1@-&,%d1,%acc2
+    2da4:	a661 1662      	macw %d2u,%d1l,>>,%a1@-&,%a3,%acc1
+    2da8:	a6e1 1672      	macw %d2u,%d1l,>>,%a1@-&,%a3,%acc2
+    2dac:	a421 1662      	macw %d2u,%d1l,>>,%a1@-&,%d2,%acc1
+    2db0:	a4a1 1672      	macw %d2u,%d1l,>>,%a1@-&,%d2,%acc2
+    2db4:	ae61 1662      	macw %d2u,%d1l,>>,%a1@-&,%sp,%acc1
+    2db8:	aee1 1672      	macw %d2u,%d1l,>>,%a1@-&,%sp,%acc2
+    2dbc:	a213 1242      	macw %d2u,%d1l,<<,%a3@,%d1,%acc1
+    2dc0:	a293 1252      	macw %d2u,%d1l,<<,%a3@,%d1,%acc2
+    2dc4:	a653 1242      	macw %d2u,%d1l,<<,%a3@,%a3,%acc1
+    2dc8:	a6d3 1252      	macw %d2u,%d1l,<<,%a3@,%a3,%acc2
+    2dcc:	a413 1242      	macw %d2u,%d1l,<<,%a3@,%d2,%acc1
+    2dd0:	a493 1252      	macw %d2u,%d1l,<<,%a3@,%d2,%acc2
+    2dd4:	ae53 1242      	macw %d2u,%d1l,<<,%a3@,%sp,%acc1
+    2dd8:	aed3 1252      	macw %d2u,%d1l,<<,%a3@,%sp,%acc2
+    2ddc:	a213 1262      	macw %d2u,%d1l,<<,%a3@&,%d1,%acc1
+    2de0:	a293 1272      	macw %d2u,%d1l,<<,%a3@&,%d1,%acc2
+    2de4:	a653 1262      	macw %d2u,%d1l,<<,%a3@&,%a3,%acc1
+    2de8:	a6d3 1272      	macw %d2u,%d1l,<<,%a3@&,%a3,%acc2
+    2dec:	a413 1262      	macw %d2u,%d1l,<<,%a3@&,%d2,%acc1
+    2df0:	a493 1272      	macw %d2u,%d1l,<<,%a3@&,%d2,%acc2
+    2df4:	ae53 1262      	macw %d2u,%d1l,<<,%a3@&,%sp,%acc1
+    2df8:	aed3 1272      	macw %d2u,%d1l,<<,%a3@&,%sp,%acc2
+    2dfc:	a21a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d1,%acc1
+    2e00:	a29a 1252      	macw %d2u,%d1l,<<,%a2@\+,%d1,%acc2
+    2e04:	a65a 1242      	macw %d2u,%d1l,<<,%a2@\+,%a3,%acc1
+    2e08:	a6da 1252      	macw %d2u,%d1l,<<,%a2@\+,%a3,%acc2
+    2e0c:	a41a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d2,%acc1
+    2e10:	a49a 1252      	macw %d2u,%d1l,<<,%a2@\+,%d2,%acc2
+    2e14:	ae5a 1242      	macw %d2u,%d1l,<<,%a2@\+,%sp,%acc1
+    2e18:	aeda 1252      	macw %d2u,%d1l,<<,%a2@\+,%sp,%acc2
+    2e1c:	a21a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d1,%acc1
+    2e20:	a29a 1272      	macw %d2u,%d1l,<<,%a2@\+&,%d1,%acc2
+    2e24:	a65a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%a3,%acc1
+    2e28:	a6da 1272      	macw %d2u,%d1l,<<,%a2@\+&,%a3,%acc2
+    2e2c:	a41a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d2,%acc1
+    2e30:	a49a 1272      	macw %d2u,%d1l,<<,%a2@\+&,%d2,%acc2
+    2e34:	ae5a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%sp,%acc1
+    2e38:	aeda 1272      	macw %d2u,%d1l,<<,%a2@\+&,%sp,%acc2
+    2e3c:	a22e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1,%acc1
+    2e42:	a2ae 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1,%acc2
+    2e48:	a66e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3,%acc1
+    2e4e:	a6ee 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3,%acc2
+    2e54:	a42e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2,%acc1
+    2e5a:	a4ae 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2,%acc2
+    2e60:	ae6e 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp,%acc1
+    2e66:	aeee 1252 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp,%acc2
+    2e6c:	a22e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    2e72:	a2ae 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    2e78:	a66e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    2e7e:	a6ee 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    2e84:	a42e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    2e8a:	a4ae 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    2e90:	ae6e 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    2e96:	aeee 1272 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    2e9c:	a221 1242      	macw %d2u,%d1l,<<,%a1@-,%d1,%acc1
+    2ea0:	a2a1 1252      	macw %d2u,%d1l,<<,%a1@-,%d1,%acc2
+    2ea4:	a661 1242      	macw %d2u,%d1l,<<,%a1@-,%a3,%acc1
+    2ea8:	a6e1 1252      	macw %d2u,%d1l,<<,%a1@-,%a3,%acc2
+    2eac:	a421 1242      	macw %d2u,%d1l,<<,%a1@-,%d2,%acc1
+    2eb0:	a4a1 1252      	macw %d2u,%d1l,<<,%a1@-,%d2,%acc2
+    2eb4:	ae61 1242      	macw %d2u,%d1l,<<,%a1@-,%sp,%acc1
+    2eb8:	aee1 1252      	macw %d2u,%d1l,<<,%a1@-,%sp,%acc2
+    2ebc:	a221 1262      	macw %d2u,%d1l,<<,%a1@-&,%d1,%acc1
+    2ec0:	a2a1 1272      	macw %d2u,%d1l,<<,%a1@-&,%d1,%acc2
+    2ec4:	a661 1262      	macw %d2u,%d1l,<<,%a1@-&,%a3,%acc1
+    2ec8:	a6e1 1272      	macw %d2u,%d1l,<<,%a1@-&,%a3,%acc2
+    2ecc:	a421 1262      	macw %d2u,%d1l,<<,%a1@-&,%d2,%acc1
+    2ed0:	a4a1 1272      	macw %d2u,%d1l,<<,%a1@-&,%d2,%acc2
+    2ed4:	ae61 1262      	macw %d2u,%d1l,<<,%a1@-&,%sp,%acc1
+    2ed8:	aee1 1272      	macw %d2u,%d1l,<<,%a1@-&,%sp,%acc2
+    2edc:	a213 1642      	macw %d2u,%d1l,>>,%a3@,%d1,%acc1
+    2ee0:	a293 1652      	macw %d2u,%d1l,>>,%a3@,%d1,%acc2
+    2ee4:	a653 1642      	macw %d2u,%d1l,>>,%a3@,%a3,%acc1
+    2ee8:	a6d3 1652      	macw %d2u,%d1l,>>,%a3@,%a3,%acc2
+    2eec:	a413 1642      	macw %d2u,%d1l,>>,%a3@,%d2,%acc1
+    2ef0:	a493 1652      	macw %d2u,%d1l,>>,%a3@,%d2,%acc2
+    2ef4:	ae53 1642      	macw %d2u,%d1l,>>,%a3@,%sp,%acc1
+    2ef8:	aed3 1652      	macw %d2u,%d1l,>>,%a3@,%sp,%acc2
+    2efc:	a213 1662      	macw %d2u,%d1l,>>,%a3@&,%d1,%acc1
+    2f00:	a293 1672      	macw %d2u,%d1l,>>,%a3@&,%d1,%acc2
+    2f04:	a653 1662      	macw %d2u,%d1l,>>,%a3@&,%a3,%acc1
+    2f08:	a6d3 1672      	macw %d2u,%d1l,>>,%a3@&,%a3,%acc2
+    2f0c:	a413 1662      	macw %d2u,%d1l,>>,%a3@&,%d2,%acc1
+    2f10:	a493 1672      	macw %d2u,%d1l,>>,%a3@&,%d2,%acc2
+    2f14:	ae53 1662      	macw %d2u,%d1l,>>,%a3@&,%sp,%acc1
+    2f18:	aed3 1672      	macw %d2u,%d1l,>>,%a3@&,%sp,%acc2
+    2f1c:	a21a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d1,%acc1
+    2f20:	a29a 1652      	macw %d2u,%d1l,>>,%a2@\+,%d1,%acc2
+    2f24:	a65a 1642      	macw %d2u,%d1l,>>,%a2@\+,%a3,%acc1
+    2f28:	a6da 1652      	macw %d2u,%d1l,>>,%a2@\+,%a3,%acc2
+    2f2c:	a41a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d2,%acc1
+    2f30:	a49a 1652      	macw %d2u,%d1l,>>,%a2@\+,%d2,%acc2
+    2f34:	ae5a 1642      	macw %d2u,%d1l,>>,%a2@\+,%sp,%acc1
+    2f38:	aeda 1652      	macw %d2u,%d1l,>>,%a2@\+,%sp,%acc2
+    2f3c:	a21a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d1,%acc1
+    2f40:	a29a 1672      	macw %d2u,%d1l,>>,%a2@\+&,%d1,%acc2
+    2f44:	a65a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%a3,%acc1
+    2f48:	a6da 1672      	macw %d2u,%d1l,>>,%a2@\+&,%a3,%acc2
+    2f4c:	a41a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d2,%acc1
+    2f50:	a49a 1672      	macw %d2u,%d1l,>>,%a2@\+&,%d2,%acc2
+    2f54:	ae5a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%sp,%acc1
+    2f58:	aeda 1672      	macw %d2u,%d1l,>>,%a2@\+&,%sp,%acc2
+    2f5c:	a22e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1,%acc1
+    2f62:	a2ae 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1,%acc2
+    2f68:	a66e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3,%acc1
+    2f6e:	a6ee 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3,%acc2
+    2f74:	a42e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2,%acc1
+    2f7a:	a4ae 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2,%acc2
+    2f80:	ae6e 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp,%acc1
+    2f86:	aeee 1652 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp,%acc2
+    2f8c:	a22e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    2f92:	a2ae 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    2f98:	a66e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    2f9e:	a6ee 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    2fa4:	a42e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    2faa:	a4ae 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    2fb0:	ae6e 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    2fb6:	aeee 1672 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    2fbc:	a221 1642      	macw %d2u,%d1l,>>,%a1@-,%d1,%acc1
+    2fc0:	a2a1 1652      	macw %d2u,%d1l,>>,%a1@-,%d1,%acc2
+    2fc4:	a661 1642      	macw %d2u,%d1l,>>,%a1@-,%a3,%acc1
+    2fc8:	a6e1 1652      	macw %d2u,%d1l,>>,%a1@-,%a3,%acc2
+    2fcc:	a421 1642      	macw %d2u,%d1l,>>,%a1@-,%d2,%acc1
+    2fd0:	a4a1 1652      	macw %d2u,%d1l,>>,%a1@-,%d2,%acc2
+    2fd4:	ae61 1642      	macw %d2u,%d1l,>>,%a1@-,%sp,%acc1
+    2fd8:	aee1 1652      	macw %d2u,%d1l,>>,%a1@-,%sp,%acc2
+    2fdc:	a221 1662      	macw %d2u,%d1l,>>,%a1@-&,%d1,%acc1
+    2fe0:	a2a1 1672      	macw %d2u,%d1l,>>,%a1@-&,%d1,%acc2
+    2fe4:	a661 1662      	macw %d2u,%d1l,>>,%a1@-&,%a3,%acc1
+    2fe8:	a6e1 1672      	macw %d2u,%d1l,>>,%a1@-&,%a3,%acc2
+    2fec:	a421 1662      	macw %d2u,%d1l,>>,%a1@-&,%d2,%acc1
+    2ff0:	a4a1 1672      	macw %d2u,%d1l,>>,%a1@-&,%d2,%acc2
+    2ff4:	ae61 1662      	macw %d2u,%d1l,>>,%a1@-&,%sp,%acc1
+    2ff8:	aee1 1672      	macw %d2u,%d1l,>>,%a1@-&,%sp,%acc2
+    2ffc:	a213 a08d      	macw %a5l,%a2u,%a3@,%d1,%acc1
+    3000:	a293 a09d      	macw %a5l,%a2u,%a3@,%d1,%acc2
+    3004:	a653 a08d      	macw %a5l,%a2u,%a3@,%a3,%acc1
+    3008:	a6d3 a09d      	macw %a5l,%a2u,%a3@,%a3,%acc2
+    300c:	a413 a08d      	macw %a5l,%a2u,%a3@,%d2,%acc1
+    3010:	a493 a09d      	macw %a5l,%a2u,%a3@,%d2,%acc2
+    3014:	ae53 a08d      	macw %a5l,%a2u,%a3@,%sp,%acc1
+    3018:	aed3 a09d      	macw %a5l,%a2u,%a3@,%sp,%acc2
+    301c:	a213 a0ad      	macw %a5l,%a2u,%a3@&,%d1,%acc1
+    3020:	a293 a0bd      	macw %a5l,%a2u,%a3@&,%d1,%acc2
+    3024:	a653 a0ad      	macw %a5l,%a2u,%a3@&,%a3,%acc1
+    3028:	a6d3 a0bd      	macw %a5l,%a2u,%a3@&,%a3,%acc2
+    302c:	a413 a0ad      	macw %a5l,%a2u,%a3@&,%d2,%acc1
+    3030:	a493 a0bd      	macw %a5l,%a2u,%a3@&,%d2,%acc2
+    3034:	ae53 a0ad      	macw %a5l,%a2u,%a3@&,%sp,%acc1
+    3038:	aed3 a0bd      	macw %a5l,%a2u,%a3@&,%sp,%acc2
+    303c:	a21a a08d      	macw %a5l,%a2u,%a2@\+,%d1,%acc1
+    3040:	a29a a09d      	macw %a5l,%a2u,%a2@\+,%d1,%acc2
+    3044:	a65a a08d      	macw %a5l,%a2u,%a2@\+,%a3,%acc1
+    3048:	a6da a09d      	macw %a5l,%a2u,%a2@\+,%a3,%acc2
+    304c:	a41a a08d      	macw %a5l,%a2u,%a2@\+,%d2,%acc1
+    3050:	a49a a09d      	macw %a5l,%a2u,%a2@\+,%d2,%acc2
+    3054:	ae5a a08d      	macw %a5l,%a2u,%a2@\+,%sp,%acc1
+    3058:	aeda a09d      	macw %a5l,%a2u,%a2@\+,%sp,%acc2
+    305c:	a21a a0ad      	macw %a5l,%a2u,%a2@\+&,%d1,%acc1
+    3060:	a29a a0bd      	macw %a5l,%a2u,%a2@\+&,%d1,%acc2
+    3064:	a65a a0ad      	macw %a5l,%a2u,%a2@\+&,%a3,%acc1
+    3068:	a6da a0bd      	macw %a5l,%a2u,%a2@\+&,%a3,%acc2
+    306c:	a41a a0ad      	macw %a5l,%a2u,%a2@\+&,%d2,%acc1
+    3070:	a49a a0bd      	macw %a5l,%a2u,%a2@\+&,%d2,%acc2
+    3074:	ae5a a0ad      	macw %a5l,%a2u,%a2@\+&,%sp,%acc1
+    3078:	aeda a0bd      	macw %a5l,%a2u,%a2@\+&,%sp,%acc2
+    307c:	a22e a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%d1,%acc1
+    3082:	a2ae a09d 000a 	macw %a5l,%a2u,%fp@\(10\),%d1,%acc2
+    3088:	a66e a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%a3,%acc1
+    308e:	a6ee a09d 000a 	macw %a5l,%a2u,%fp@\(10\),%a3,%acc2
+    3094:	a42e a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%d2,%acc1
+    309a:	a4ae a09d 000a 	macw %a5l,%a2u,%fp@\(10\),%d2,%acc2
+    30a0:	ae6e a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%sp,%acc1
+    30a6:	aeee a09d 000a 	macw %a5l,%a2u,%fp@\(10\),%sp,%acc2
+    30ac:	a22e a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d1,%acc1
+    30b2:	a2ae a0bd 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d1,%acc2
+    30b8:	a66e a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%a3,%acc1
+    30be:	a6ee a0bd 000a 	macw %a5l,%a2u,%fp@\(10\)&,%a3,%acc2
+    30c4:	a42e a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d2,%acc1
+    30ca:	a4ae a0bd 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d2,%acc2
+    30d0:	ae6e a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%sp,%acc1
+    30d6:	aeee a0bd 000a 	macw %a5l,%a2u,%fp@\(10\)&,%sp,%acc2
+    30dc:	a221 a08d      	macw %a5l,%a2u,%a1@-,%d1,%acc1
+    30e0:	a2a1 a09d      	macw %a5l,%a2u,%a1@-,%d1,%acc2
+    30e4:	a661 a08d      	macw %a5l,%a2u,%a1@-,%a3,%acc1
+    30e8:	a6e1 a09d      	macw %a5l,%a2u,%a1@-,%a3,%acc2
+    30ec:	a421 a08d      	macw %a5l,%a2u,%a1@-,%d2,%acc1
+    30f0:	a4a1 a09d      	macw %a5l,%a2u,%a1@-,%d2,%acc2
+    30f4:	ae61 a08d      	macw %a5l,%a2u,%a1@-,%sp,%acc1
+    30f8:	aee1 a09d      	macw %a5l,%a2u,%a1@-,%sp,%acc2
+    30fc:	a221 a0ad      	macw %a5l,%a2u,%a1@-&,%d1,%acc1
+    3100:	a2a1 a0bd      	macw %a5l,%a2u,%a1@-&,%d1,%acc2
+    3104:	a661 a0ad      	macw %a5l,%a2u,%a1@-&,%a3,%acc1
+    3108:	a6e1 a0bd      	macw %a5l,%a2u,%a1@-&,%a3,%acc2
+    310c:	a421 a0ad      	macw %a5l,%a2u,%a1@-&,%d2,%acc1
+    3110:	a4a1 a0bd      	macw %a5l,%a2u,%a1@-&,%d2,%acc2
+    3114:	ae61 a0ad      	macw %a5l,%a2u,%a1@-&,%sp,%acc1
+    3118:	aee1 a0bd      	macw %a5l,%a2u,%a1@-&,%sp,%acc2
+    311c:	a213 a28d      	macw %a5l,%a2u,<<,%a3@,%d1,%acc1
+    3120:	a293 a29d      	macw %a5l,%a2u,<<,%a3@,%d1,%acc2
+    3124:	a653 a28d      	macw %a5l,%a2u,<<,%a3@,%a3,%acc1
+    3128:	a6d3 a29d      	macw %a5l,%a2u,<<,%a3@,%a3,%acc2
+    312c:	a413 a28d      	macw %a5l,%a2u,<<,%a3@,%d2,%acc1
+    3130:	a493 a29d      	macw %a5l,%a2u,<<,%a3@,%d2,%acc2
+    3134:	ae53 a28d      	macw %a5l,%a2u,<<,%a3@,%sp,%acc1
+    3138:	aed3 a29d      	macw %a5l,%a2u,<<,%a3@,%sp,%acc2
+    313c:	a213 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d1,%acc1
+    3140:	a293 a2bd      	macw %a5l,%a2u,<<,%a3@&,%d1,%acc2
+    3144:	a653 a2ad      	macw %a5l,%a2u,<<,%a3@&,%a3,%acc1
+    3148:	a6d3 a2bd      	macw %a5l,%a2u,<<,%a3@&,%a3,%acc2
+    314c:	a413 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d2,%acc1
+    3150:	a493 a2bd      	macw %a5l,%a2u,<<,%a3@&,%d2,%acc2
+    3154:	ae53 a2ad      	macw %a5l,%a2u,<<,%a3@&,%sp,%acc1
+    3158:	aed3 a2bd      	macw %a5l,%a2u,<<,%a3@&,%sp,%acc2
+    315c:	a21a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d1,%acc1
+    3160:	a29a a29d      	macw %a5l,%a2u,<<,%a2@\+,%d1,%acc2
+    3164:	a65a a28d      	macw %a5l,%a2u,<<,%a2@\+,%a3,%acc1
+    3168:	a6da a29d      	macw %a5l,%a2u,<<,%a2@\+,%a3,%acc2
+    316c:	a41a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d2,%acc1
+    3170:	a49a a29d      	macw %a5l,%a2u,<<,%a2@\+,%d2,%acc2
+    3174:	ae5a a28d      	macw %a5l,%a2u,<<,%a2@\+,%sp,%acc1
+    3178:	aeda a29d      	macw %a5l,%a2u,<<,%a2@\+,%sp,%acc2
+    317c:	a21a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d1,%acc1
+    3180:	a29a a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%d1,%acc2
+    3184:	a65a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%a3,%acc1
+    3188:	a6da a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%a3,%acc2
+    318c:	a41a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d2,%acc1
+    3190:	a49a a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%d2,%acc2
+    3194:	ae5a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%sp,%acc1
+    3198:	aeda a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%sp,%acc2
+    319c:	a22e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1,%acc1
+    31a2:	a2ae a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1,%acc2
+    31a8:	a66e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3,%acc1
+    31ae:	a6ee a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3,%acc2
+    31b4:	a42e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2,%acc1
+    31ba:	a4ae a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2,%acc2
+    31c0:	ae6e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp,%acc1
+    31c6:	aeee a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp,%acc2
+    31cc:	a22e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    31d2:	a2ae a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    31d8:	a66e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    31de:	a6ee a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    31e4:	a42e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    31ea:	a4ae a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    31f0:	ae6e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    31f6:	aeee a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    31fc:	a221 a28d      	macw %a5l,%a2u,<<,%a1@-,%d1,%acc1
+    3200:	a2a1 a29d      	macw %a5l,%a2u,<<,%a1@-,%d1,%acc2
+    3204:	a661 a28d      	macw %a5l,%a2u,<<,%a1@-,%a3,%acc1
+    3208:	a6e1 a29d      	macw %a5l,%a2u,<<,%a1@-,%a3,%acc2
+    320c:	a421 a28d      	macw %a5l,%a2u,<<,%a1@-,%d2,%acc1
+    3210:	a4a1 a29d      	macw %a5l,%a2u,<<,%a1@-,%d2,%acc2
+    3214:	ae61 a28d      	macw %a5l,%a2u,<<,%a1@-,%sp,%acc1
+    3218:	aee1 a29d      	macw %a5l,%a2u,<<,%a1@-,%sp,%acc2
+    321c:	a221 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d1,%acc1
+    3220:	a2a1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%d1,%acc2
+    3224:	a661 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%a3,%acc1
+    3228:	a6e1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%a3,%acc2
+    322c:	a421 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d2,%acc1
+    3230:	a4a1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%d2,%acc2
+    3234:	ae61 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%sp,%acc1
+    3238:	aee1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%sp,%acc2
+    323c:	a213 a68d      	macw %a5l,%a2u,>>,%a3@,%d1,%acc1
+    3240:	a293 a69d      	macw %a5l,%a2u,>>,%a3@,%d1,%acc2
+    3244:	a653 a68d      	macw %a5l,%a2u,>>,%a3@,%a3,%acc1
+    3248:	a6d3 a69d      	macw %a5l,%a2u,>>,%a3@,%a3,%acc2
+    324c:	a413 a68d      	macw %a5l,%a2u,>>,%a3@,%d2,%acc1
+    3250:	a493 a69d      	macw %a5l,%a2u,>>,%a3@,%d2,%acc2
+    3254:	ae53 a68d      	macw %a5l,%a2u,>>,%a3@,%sp,%acc1
+    3258:	aed3 a69d      	macw %a5l,%a2u,>>,%a3@,%sp,%acc2
+    325c:	a213 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d1,%acc1
+    3260:	a293 a6bd      	macw %a5l,%a2u,>>,%a3@&,%d1,%acc2
+    3264:	a653 a6ad      	macw %a5l,%a2u,>>,%a3@&,%a3,%acc1
+    3268:	a6d3 a6bd      	macw %a5l,%a2u,>>,%a3@&,%a3,%acc2
+    326c:	a413 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d2,%acc1
+    3270:	a493 a6bd      	macw %a5l,%a2u,>>,%a3@&,%d2,%acc2
+    3274:	ae53 a6ad      	macw %a5l,%a2u,>>,%a3@&,%sp,%acc1
+    3278:	aed3 a6bd      	macw %a5l,%a2u,>>,%a3@&,%sp,%acc2
+    327c:	a21a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d1,%acc1
+    3280:	a29a a69d      	macw %a5l,%a2u,>>,%a2@\+,%d1,%acc2
+    3284:	a65a a68d      	macw %a5l,%a2u,>>,%a2@\+,%a3,%acc1
+    3288:	a6da a69d      	macw %a5l,%a2u,>>,%a2@\+,%a3,%acc2
+    328c:	a41a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d2,%acc1
+    3290:	a49a a69d      	macw %a5l,%a2u,>>,%a2@\+,%d2,%acc2
+    3294:	ae5a a68d      	macw %a5l,%a2u,>>,%a2@\+,%sp,%acc1
+    3298:	aeda a69d      	macw %a5l,%a2u,>>,%a2@\+,%sp,%acc2
+    329c:	a21a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d1,%acc1
+    32a0:	a29a a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%d1,%acc2
+    32a4:	a65a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%a3,%acc1
+    32a8:	a6da a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%a3,%acc2
+    32ac:	a41a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d2,%acc1
+    32b0:	a49a a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%d2,%acc2
+    32b4:	ae5a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%sp,%acc1
+    32b8:	aeda a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%sp,%acc2
+    32bc:	a22e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1,%acc1
+    32c2:	a2ae a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1,%acc2
+    32c8:	a66e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3,%acc1
+    32ce:	a6ee a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3,%acc2
+    32d4:	a42e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2,%acc1
+    32da:	a4ae a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2,%acc2
+    32e0:	ae6e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp,%acc1
+    32e6:	aeee a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp,%acc2
+    32ec:	a22e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    32f2:	a2ae a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    32f8:	a66e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    32fe:	a6ee a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    3304:	a42e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    330a:	a4ae a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    3310:	ae6e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    3316:	aeee a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    331c:	a221 a68d      	macw %a5l,%a2u,>>,%a1@-,%d1,%acc1
+    3320:	a2a1 a69d      	macw %a5l,%a2u,>>,%a1@-,%d1,%acc2
+    3324:	a661 a68d      	macw %a5l,%a2u,>>,%a1@-,%a3,%acc1
+    3328:	a6e1 a69d      	macw %a5l,%a2u,>>,%a1@-,%a3,%acc2
+    332c:	a421 a68d      	macw %a5l,%a2u,>>,%a1@-,%d2,%acc1
+    3330:	a4a1 a69d      	macw %a5l,%a2u,>>,%a1@-,%d2,%acc2
+    3334:	ae61 a68d      	macw %a5l,%a2u,>>,%a1@-,%sp,%acc1
+    3338:	aee1 a69d      	macw %a5l,%a2u,>>,%a1@-,%sp,%acc2
+    333c:	a221 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d1,%acc1
+    3340:	a2a1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%d1,%acc2
+    3344:	a661 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%a3,%acc1
+    3348:	a6e1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%a3,%acc2
+    334c:	a421 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d2,%acc1
+    3350:	a4a1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%d2,%acc2
+    3354:	ae61 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%sp,%acc1
+    3358:	aee1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%sp,%acc2
+    335c:	a213 a28d      	macw %a5l,%a2u,<<,%a3@,%d1,%acc1
+    3360:	a293 a29d      	macw %a5l,%a2u,<<,%a3@,%d1,%acc2
+    3364:	a653 a28d      	macw %a5l,%a2u,<<,%a3@,%a3,%acc1
+    3368:	a6d3 a29d      	macw %a5l,%a2u,<<,%a3@,%a3,%acc2
+    336c:	a413 a28d      	macw %a5l,%a2u,<<,%a3@,%d2,%acc1
+    3370:	a493 a29d      	macw %a5l,%a2u,<<,%a3@,%d2,%acc2
+    3374:	ae53 a28d      	macw %a5l,%a2u,<<,%a3@,%sp,%acc1
+    3378:	aed3 a29d      	macw %a5l,%a2u,<<,%a3@,%sp,%acc2
+    337c:	a213 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d1,%acc1
+    3380:	a293 a2bd      	macw %a5l,%a2u,<<,%a3@&,%d1,%acc2
+    3384:	a653 a2ad      	macw %a5l,%a2u,<<,%a3@&,%a3,%acc1
+    3388:	a6d3 a2bd      	macw %a5l,%a2u,<<,%a3@&,%a3,%acc2
+    338c:	a413 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d2,%acc1
+    3390:	a493 a2bd      	macw %a5l,%a2u,<<,%a3@&,%d2,%acc2
+    3394:	ae53 a2ad      	macw %a5l,%a2u,<<,%a3@&,%sp,%acc1
+    3398:	aed3 a2bd      	macw %a5l,%a2u,<<,%a3@&,%sp,%acc2
+    339c:	a21a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d1,%acc1
+    33a0:	a29a a29d      	macw %a5l,%a2u,<<,%a2@\+,%d1,%acc2
+    33a4:	a65a a28d      	macw %a5l,%a2u,<<,%a2@\+,%a3,%acc1
+    33a8:	a6da a29d      	macw %a5l,%a2u,<<,%a2@\+,%a3,%acc2
+    33ac:	a41a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d2,%acc1
+    33b0:	a49a a29d      	macw %a5l,%a2u,<<,%a2@\+,%d2,%acc2
+    33b4:	ae5a a28d      	macw %a5l,%a2u,<<,%a2@\+,%sp,%acc1
+    33b8:	aeda a29d      	macw %a5l,%a2u,<<,%a2@\+,%sp,%acc2
+    33bc:	a21a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d1,%acc1
+    33c0:	a29a a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%d1,%acc2
+    33c4:	a65a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%a3,%acc1
+    33c8:	a6da a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%a3,%acc2
+    33cc:	a41a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d2,%acc1
+    33d0:	a49a a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%d2,%acc2
+    33d4:	ae5a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%sp,%acc1
+    33d8:	aeda a2bd      	macw %a5l,%a2u,<<,%a2@\+&,%sp,%acc2
+    33dc:	a22e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1,%acc1
+    33e2:	a2ae a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1,%acc2
+    33e8:	a66e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3,%acc1
+    33ee:	a6ee a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3,%acc2
+    33f4:	a42e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2,%acc1
+    33fa:	a4ae a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2,%acc2
+    3400:	ae6e a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp,%acc1
+    3406:	aeee a29d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp,%acc2
+    340c:	a22e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    3412:	a2ae a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    3418:	a66e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    341e:	a6ee a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    3424:	a42e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    342a:	a4ae a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    3430:	ae6e a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    3436:	aeee a2bd 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    343c:	a221 a28d      	macw %a5l,%a2u,<<,%a1@-,%d1,%acc1
+    3440:	a2a1 a29d      	macw %a5l,%a2u,<<,%a1@-,%d1,%acc2
+    3444:	a661 a28d      	macw %a5l,%a2u,<<,%a1@-,%a3,%acc1
+    3448:	a6e1 a29d      	macw %a5l,%a2u,<<,%a1@-,%a3,%acc2
+    344c:	a421 a28d      	macw %a5l,%a2u,<<,%a1@-,%d2,%acc1
+    3450:	a4a1 a29d      	macw %a5l,%a2u,<<,%a1@-,%d2,%acc2
+    3454:	ae61 a28d      	macw %a5l,%a2u,<<,%a1@-,%sp,%acc1
+    3458:	aee1 a29d      	macw %a5l,%a2u,<<,%a1@-,%sp,%acc2
+    345c:	a221 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d1,%acc1
+    3460:	a2a1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%d1,%acc2
+    3464:	a661 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%a3,%acc1
+    3468:	a6e1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%a3,%acc2
+    346c:	a421 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d2,%acc1
+    3470:	a4a1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%d2,%acc2
+    3474:	ae61 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%sp,%acc1
+    3478:	aee1 a2bd      	macw %a5l,%a2u,<<,%a1@-&,%sp,%acc2
+    347c:	a213 a68d      	macw %a5l,%a2u,>>,%a3@,%d1,%acc1
+    3480:	a293 a69d      	macw %a5l,%a2u,>>,%a3@,%d1,%acc2
+    3484:	a653 a68d      	macw %a5l,%a2u,>>,%a3@,%a3,%acc1
+    3488:	a6d3 a69d      	macw %a5l,%a2u,>>,%a3@,%a3,%acc2
+    348c:	a413 a68d      	macw %a5l,%a2u,>>,%a3@,%d2,%acc1
+    3490:	a493 a69d      	macw %a5l,%a2u,>>,%a3@,%d2,%acc2
+    3494:	ae53 a68d      	macw %a5l,%a2u,>>,%a3@,%sp,%acc1
+    3498:	aed3 a69d      	macw %a5l,%a2u,>>,%a3@,%sp,%acc2
+    349c:	a213 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d1,%acc1
+    34a0:	a293 a6bd      	macw %a5l,%a2u,>>,%a3@&,%d1,%acc2
+    34a4:	a653 a6ad      	macw %a5l,%a2u,>>,%a3@&,%a3,%acc1
+    34a8:	a6d3 a6bd      	macw %a5l,%a2u,>>,%a3@&,%a3,%acc2
+    34ac:	a413 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d2,%acc1
+    34b0:	a493 a6bd      	macw %a5l,%a2u,>>,%a3@&,%d2,%acc2
+    34b4:	ae53 a6ad      	macw %a5l,%a2u,>>,%a3@&,%sp,%acc1
+    34b8:	aed3 a6bd      	macw %a5l,%a2u,>>,%a3@&,%sp,%acc2
+    34bc:	a21a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d1,%acc1
+    34c0:	a29a a69d      	macw %a5l,%a2u,>>,%a2@\+,%d1,%acc2
+    34c4:	a65a a68d      	macw %a5l,%a2u,>>,%a2@\+,%a3,%acc1
+    34c8:	a6da a69d      	macw %a5l,%a2u,>>,%a2@\+,%a3,%acc2
+    34cc:	a41a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d2,%acc1
+    34d0:	a49a a69d      	macw %a5l,%a2u,>>,%a2@\+,%d2,%acc2
+    34d4:	ae5a a68d      	macw %a5l,%a2u,>>,%a2@\+,%sp,%acc1
+    34d8:	aeda a69d      	macw %a5l,%a2u,>>,%a2@\+,%sp,%acc2
+    34dc:	a21a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d1,%acc1
+    34e0:	a29a a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%d1,%acc2
+    34e4:	a65a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%a3,%acc1
+    34e8:	a6da a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%a3,%acc2
+    34ec:	a41a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d2,%acc1
+    34f0:	a49a a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%d2,%acc2
+    34f4:	ae5a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%sp,%acc1
+    34f8:	aeda a6bd      	macw %a5l,%a2u,>>,%a2@\+&,%sp,%acc2
+    34fc:	a22e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1,%acc1
+    3502:	a2ae a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1,%acc2
+    3508:	a66e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3,%acc1
+    350e:	a6ee a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3,%acc2
+    3514:	a42e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2,%acc1
+    351a:	a4ae a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2,%acc2
+    3520:	ae6e a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp,%acc1
+    3526:	aeee a69d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp,%acc2
+    352c:	a22e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    3532:	a2ae a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    3538:	a66e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    353e:	a6ee a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    3544:	a42e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    354a:	a4ae a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    3550:	ae6e a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    3556:	aeee a6bd 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    355c:	a221 a68d      	macw %a5l,%a2u,>>,%a1@-,%d1,%acc1
+    3560:	a2a1 a69d      	macw %a5l,%a2u,>>,%a1@-,%d1,%acc2
+    3564:	a661 a68d      	macw %a5l,%a2u,>>,%a1@-,%a3,%acc1
+    3568:	a6e1 a69d      	macw %a5l,%a2u,>>,%a1@-,%a3,%acc2
+    356c:	a421 a68d      	macw %a5l,%a2u,>>,%a1@-,%d2,%acc1
+    3570:	a4a1 a69d      	macw %a5l,%a2u,>>,%a1@-,%d2,%acc2
+    3574:	ae61 a68d      	macw %a5l,%a2u,>>,%a1@-,%sp,%acc1
+    3578:	aee1 a69d      	macw %a5l,%a2u,>>,%a1@-,%sp,%acc2
+    357c:	a221 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d1,%acc1
+    3580:	a2a1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%d1,%acc2
+    3584:	a661 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%a3,%acc1
+    3588:	a6e1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%a3,%acc2
+    358c:	a421 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d2,%acc1
+    3590:	a4a1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%d2,%acc2
+    3594:	ae61 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%sp,%acc1
+    3598:	aee1 a6bd      	macw %a5l,%a2u,>>,%a1@-&,%sp,%acc2
+    359c:	a213 300d      	macw %a5l,%d3l,%a3@,%d1,%acc1
+    35a0:	a293 301d      	macw %a5l,%d3l,%a3@,%d1,%acc2
+    35a4:	a653 300d      	macw %a5l,%d3l,%a3@,%a3,%acc1
+    35a8:	a6d3 301d      	macw %a5l,%d3l,%a3@,%a3,%acc2
+    35ac:	a413 300d      	macw %a5l,%d3l,%a3@,%d2,%acc1
+    35b0:	a493 301d      	macw %a5l,%d3l,%a3@,%d2,%acc2
+    35b4:	ae53 300d      	macw %a5l,%d3l,%a3@,%sp,%acc1
+    35b8:	aed3 301d      	macw %a5l,%d3l,%a3@,%sp,%acc2
+    35bc:	a213 302d      	macw %a5l,%d3l,%a3@&,%d1,%acc1
+    35c0:	a293 303d      	macw %a5l,%d3l,%a3@&,%d1,%acc2
+    35c4:	a653 302d      	macw %a5l,%d3l,%a3@&,%a3,%acc1
+    35c8:	a6d3 303d      	macw %a5l,%d3l,%a3@&,%a3,%acc2
+    35cc:	a413 302d      	macw %a5l,%d3l,%a3@&,%d2,%acc1
+    35d0:	a493 303d      	macw %a5l,%d3l,%a3@&,%d2,%acc2
+    35d4:	ae53 302d      	macw %a5l,%d3l,%a3@&,%sp,%acc1
+    35d8:	aed3 303d      	macw %a5l,%d3l,%a3@&,%sp,%acc2
+    35dc:	a21a 300d      	macw %a5l,%d3l,%a2@\+,%d1,%acc1
+    35e0:	a29a 301d      	macw %a5l,%d3l,%a2@\+,%d1,%acc2
+    35e4:	a65a 300d      	macw %a5l,%d3l,%a2@\+,%a3,%acc1
+    35e8:	a6da 301d      	macw %a5l,%d3l,%a2@\+,%a3,%acc2
+    35ec:	a41a 300d      	macw %a5l,%d3l,%a2@\+,%d2,%acc1
+    35f0:	a49a 301d      	macw %a5l,%d3l,%a2@\+,%d2,%acc2
+    35f4:	ae5a 300d      	macw %a5l,%d3l,%a2@\+,%sp,%acc1
+    35f8:	aeda 301d      	macw %a5l,%d3l,%a2@\+,%sp,%acc2
+    35fc:	a21a 302d      	macw %a5l,%d3l,%a2@\+&,%d1,%acc1
+    3600:	a29a 303d      	macw %a5l,%d3l,%a2@\+&,%d1,%acc2
+    3604:	a65a 302d      	macw %a5l,%d3l,%a2@\+&,%a3,%acc1
+    3608:	a6da 303d      	macw %a5l,%d3l,%a2@\+&,%a3,%acc2
+    360c:	a41a 302d      	macw %a5l,%d3l,%a2@\+&,%d2,%acc1
+    3610:	a49a 303d      	macw %a5l,%d3l,%a2@\+&,%d2,%acc2
+    3614:	ae5a 302d      	macw %a5l,%d3l,%a2@\+&,%sp,%acc1
+    3618:	aeda 303d      	macw %a5l,%d3l,%a2@\+&,%sp,%acc2
+    361c:	a22e 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%d1,%acc1
+    3622:	a2ae 301d 000a 	macw %a5l,%d3l,%fp@\(10\),%d1,%acc2
+    3628:	a66e 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%a3,%acc1
+    362e:	a6ee 301d 000a 	macw %a5l,%d3l,%fp@\(10\),%a3,%acc2
+    3634:	a42e 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%d2,%acc1
+    363a:	a4ae 301d 000a 	macw %a5l,%d3l,%fp@\(10\),%d2,%acc2
+    3640:	ae6e 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%sp,%acc1
+    3646:	aeee 301d 000a 	macw %a5l,%d3l,%fp@\(10\),%sp,%acc2
+    364c:	a22e 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d1,%acc1
+    3652:	a2ae 303d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d1,%acc2
+    3658:	a66e 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%a3,%acc1
+    365e:	a6ee 303d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%a3,%acc2
+    3664:	a42e 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d2,%acc1
+    366a:	a4ae 303d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d2,%acc2
+    3670:	ae6e 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%sp,%acc1
+    3676:	aeee 303d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%sp,%acc2
+    367c:	a221 300d      	macw %a5l,%d3l,%a1@-,%d1,%acc1
+    3680:	a2a1 301d      	macw %a5l,%d3l,%a1@-,%d1,%acc2
+    3684:	a661 300d      	macw %a5l,%d3l,%a1@-,%a3,%acc1
+    3688:	a6e1 301d      	macw %a5l,%d3l,%a1@-,%a3,%acc2
+    368c:	a421 300d      	macw %a5l,%d3l,%a1@-,%d2,%acc1
+    3690:	a4a1 301d      	macw %a5l,%d3l,%a1@-,%d2,%acc2
+    3694:	ae61 300d      	macw %a5l,%d3l,%a1@-,%sp,%acc1
+    3698:	aee1 301d      	macw %a5l,%d3l,%a1@-,%sp,%acc2
+    369c:	a221 302d      	macw %a5l,%d3l,%a1@-&,%d1,%acc1
+    36a0:	a2a1 303d      	macw %a5l,%d3l,%a1@-&,%d1,%acc2
+    36a4:	a661 302d      	macw %a5l,%d3l,%a1@-&,%a3,%acc1
+    36a8:	a6e1 303d      	macw %a5l,%d3l,%a1@-&,%a3,%acc2
+    36ac:	a421 302d      	macw %a5l,%d3l,%a1@-&,%d2,%acc1
+    36b0:	a4a1 303d      	macw %a5l,%d3l,%a1@-&,%d2,%acc2
+    36b4:	ae61 302d      	macw %a5l,%d3l,%a1@-&,%sp,%acc1
+    36b8:	aee1 303d      	macw %a5l,%d3l,%a1@-&,%sp,%acc2
+    36bc:	a213 320d      	macw %a5l,%d3l,<<,%a3@,%d1,%acc1
+    36c0:	a293 321d      	macw %a5l,%d3l,<<,%a3@,%d1,%acc2
+    36c4:	a653 320d      	macw %a5l,%d3l,<<,%a3@,%a3,%acc1
+    36c8:	a6d3 321d      	macw %a5l,%d3l,<<,%a3@,%a3,%acc2
+    36cc:	a413 320d      	macw %a5l,%d3l,<<,%a3@,%d2,%acc1
+    36d0:	a493 321d      	macw %a5l,%d3l,<<,%a3@,%d2,%acc2
+    36d4:	ae53 320d      	macw %a5l,%d3l,<<,%a3@,%sp,%acc1
+    36d8:	aed3 321d      	macw %a5l,%d3l,<<,%a3@,%sp,%acc2
+    36dc:	a213 322d      	macw %a5l,%d3l,<<,%a3@&,%d1,%acc1
+    36e0:	a293 323d      	macw %a5l,%d3l,<<,%a3@&,%d1,%acc2
+    36e4:	a653 322d      	macw %a5l,%d3l,<<,%a3@&,%a3,%acc1
+    36e8:	a6d3 323d      	macw %a5l,%d3l,<<,%a3@&,%a3,%acc2
+    36ec:	a413 322d      	macw %a5l,%d3l,<<,%a3@&,%d2,%acc1
+    36f0:	a493 323d      	macw %a5l,%d3l,<<,%a3@&,%d2,%acc2
+    36f4:	ae53 322d      	macw %a5l,%d3l,<<,%a3@&,%sp,%acc1
+    36f8:	aed3 323d      	macw %a5l,%d3l,<<,%a3@&,%sp,%acc2
+    36fc:	a21a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d1,%acc1
+    3700:	a29a 321d      	macw %a5l,%d3l,<<,%a2@\+,%d1,%acc2
+    3704:	a65a 320d      	macw %a5l,%d3l,<<,%a2@\+,%a3,%acc1
+    3708:	a6da 321d      	macw %a5l,%d3l,<<,%a2@\+,%a3,%acc2
+    370c:	a41a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d2,%acc1
+    3710:	a49a 321d      	macw %a5l,%d3l,<<,%a2@\+,%d2,%acc2
+    3714:	ae5a 320d      	macw %a5l,%d3l,<<,%a2@\+,%sp,%acc1
+    3718:	aeda 321d      	macw %a5l,%d3l,<<,%a2@\+,%sp,%acc2
+    371c:	a21a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d1,%acc1
+    3720:	a29a 323d      	macw %a5l,%d3l,<<,%a2@\+&,%d1,%acc2
+    3724:	a65a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%a3,%acc1
+    3728:	a6da 323d      	macw %a5l,%d3l,<<,%a2@\+&,%a3,%acc2
+    372c:	a41a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d2,%acc1
+    3730:	a49a 323d      	macw %a5l,%d3l,<<,%a2@\+&,%d2,%acc2
+    3734:	ae5a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%sp,%acc1
+    3738:	aeda 323d      	macw %a5l,%d3l,<<,%a2@\+&,%sp,%acc2
+    373c:	a22e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1,%acc1
+    3742:	a2ae 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1,%acc2
+    3748:	a66e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3,%acc1
+    374e:	a6ee 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3,%acc2
+    3754:	a42e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2,%acc1
+    375a:	a4ae 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2,%acc2
+    3760:	ae6e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp,%acc1
+    3766:	aeee 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp,%acc2
+    376c:	a22e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    3772:	a2ae 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    3778:	a66e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    377e:	a6ee 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    3784:	a42e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    378a:	a4ae 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    3790:	ae6e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    3796:	aeee 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    379c:	a221 320d      	macw %a5l,%d3l,<<,%a1@-,%d1,%acc1
+    37a0:	a2a1 321d      	macw %a5l,%d3l,<<,%a1@-,%d1,%acc2
+    37a4:	a661 320d      	macw %a5l,%d3l,<<,%a1@-,%a3,%acc1
+    37a8:	a6e1 321d      	macw %a5l,%d3l,<<,%a1@-,%a3,%acc2
+    37ac:	a421 320d      	macw %a5l,%d3l,<<,%a1@-,%d2,%acc1
+    37b0:	a4a1 321d      	macw %a5l,%d3l,<<,%a1@-,%d2,%acc2
+    37b4:	ae61 320d      	macw %a5l,%d3l,<<,%a1@-,%sp,%acc1
+    37b8:	aee1 321d      	macw %a5l,%d3l,<<,%a1@-,%sp,%acc2
+    37bc:	a221 322d      	macw %a5l,%d3l,<<,%a1@-&,%d1,%acc1
+    37c0:	a2a1 323d      	macw %a5l,%d3l,<<,%a1@-&,%d1,%acc2
+    37c4:	a661 322d      	macw %a5l,%d3l,<<,%a1@-&,%a3,%acc1
+    37c8:	a6e1 323d      	macw %a5l,%d3l,<<,%a1@-&,%a3,%acc2
+    37cc:	a421 322d      	macw %a5l,%d3l,<<,%a1@-&,%d2,%acc1
+    37d0:	a4a1 323d      	macw %a5l,%d3l,<<,%a1@-&,%d2,%acc2
+    37d4:	ae61 322d      	macw %a5l,%d3l,<<,%a1@-&,%sp,%acc1
+    37d8:	aee1 323d      	macw %a5l,%d3l,<<,%a1@-&,%sp,%acc2
+    37dc:	a213 360d      	macw %a5l,%d3l,>>,%a3@,%d1,%acc1
+    37e0:	a293 361d      	macw %a5l,%d3l,>>,%a3@,%d1,%acc2
+    37e4:	a653 360d      	macw %a5l,%d3l,>>,%a3@,%a3,%acc1
+    37e8:	a6d3 361d      	macw %a5l,%d3l,>>,%a3@,%a3,%acc2
+    37ec:	a413 360d      	macw %a5l,%d3l,>>,%a3@,%d2,%acc1
+    37f0:	a493 361d      	macw %a5l,%d3l,>>,%a3@,%d2,%acc2
+    37f4:	ae53 360d      	macw %a5l,%d3l,>>,%a3@,%sp,%acc1
+    37f8:	aed3 361d      	macw %a5l,%d3l,>>,%a3@,%sp,%acc2
+    37fc:	a213 362d      	macw %a5l,%d3l,>>,%a3@&,%d1,%acc1
+    3800:	a293 363d      	macw %a5l,%d3l,>>,%a3@&,%d1,%acc2
+    3804:	a653 362d      	macw %a5l,%d3l,>>,%a3@&,%a3,%acc1
+    3808:	a6d3 363d      	macw %a5l,%d3l,>>,%a3@&,%a3,%acc2
+    380c:	a413 362d      	macw %a5l,%d3l,>>,%a3@&,%d2,%acc1
+    3810:	a493 363d      	macw %a5l,%d3l,>>,%a3@&,%d2,%acc2
+    3814:	ae53 362d      	macw %a5l,%d3l,>>,%a3@&,%sp,%acc1
+    3818:	aed3 363d      	macw %a5l,%d3l,>>,%a3@&,%sp,%acc2
+    381c:	a21a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d1,%acc1
+    3820:	a29a 361d      	macw %a5l,%d3l,>>,%a2@\+,%d1,%acc2
+    3824:	a65a 360d      	macw %a5l,%d3l,>>,%a2@\+,%a3,%acc1
+    3828:	a6da 361d      	macw %a5l,%d3l,>>,%a2@\+,%a3,%acc2
+    382c:	a41a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d2,%acc1
+    3830:	a49a 361d      	macw %a5l,%d3l,>>,%a2@\+,%d2,%acc2
+    3834:	ae5a 360d      	macw %a5l,%d3l,>>,%a2@\+,%sp,%acc1
+    3838:	aeda 361d      	macw %a5l,%d3l,>>,%a2@\+,%sp,%acc2
+    383c:	a21a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d1,%acc1
+    3840:	a29a 363d      	macw %a5l,%d3l,>>,%a2@\+&,%d1,%acc2
+    3844:	a65a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%a3,%acc1
+    3848:	a6da 363d      	macw %a5l,%d3l,>>,%a2@\+&,%a3,%acc2
+    384c:	a41a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d2,%acc1
+    3850:	a49a 363d      	macw %a5l,%d3l,>>,%a2@\+&,%d2,%acc2
+    3854:	ae5a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%sp,%acc1
+    3858:	aeda 363d      	macw %a5l,%d3l,>>,%a2@\+&,%sp,%acc2
+    385c:	a22e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1,%acc1
+    3862:	a2ae 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1,%acc2
+    3868:	a66e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3,%acc1
+    386e:	a6ee 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3,%acc2
+    3874:	a42e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2,%acc1
+    387a:	a4ae 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2,%acc2
+    3880:	ae6e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp,%acc1
+    3886:	aeee 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp,%acc2
+    388c:	a22e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    3892:	a2ae 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    3898:	a66e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    389e:	a6ee 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    38a4:	a42e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    38aa:	a4ae 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    38b0:	ae6e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    38b6:	aeee 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    38bc:	a221 360d      	macw %a5l,%d3l,>>,%a1@-,%d1,%acc1
+    38c0:	a2a1 361d      	macw %a5l,%d3l,>>,%a1@-,%d1,%acc2
+    38c4:	a661 360d      	macw %a5l,%d3l,>>,%a1@-,%a3,%acc1
+    38c8:	a6e1 361d      	macw %a5l,%d3l,>>,%a1@-,%a3,%acc2
+    38cc:	a421 360d      	macw %a5l,%d3l,>>,%a1@-,%d2,%acc1
+    38d0:	a4a1 361d      	macw %a5l,%d3l,>>,%a1@-,%d2,%acc2
+    38d4:	ae61 360d      	macw %a5l,%d3l,>>,%a1@-,%sp,%acc1
+    38d8:	aee1 361d      	macw %a5l,%d3l,>>,%a1@-,%sp,%acc2
+    38dc:	a221 362d      	macw %a5l,%d3l,>>,%a1@-&,%d1,%acc1
+    38e0:	a2a1 363d      	macw %a5l,%d3l,>>,%a1@-&,%d1,%acc2
+    38e4:	a661 362d      	macw %a5l,%d3l,>>,%a1@-&,%a3,%acc1
+    38e8:	a6e1 363d      	macw %a5l,%d3l,>>,%a1@-&,%a3,%acc2
+    38ec:	a421 362d      	macw %a5l,%d3l,>>,%a1@-&,%d2,%acc1
+    38f0:	a4a1 363d      	macw %a5l,%d3l,>>,%a1@-&,%d2,%acc2
+    38f4:	ae61 362d      	macw %a5l,%d3l,>>,%a1@-&,%sp,%acc1
+    38f8:	aee1 363d      	macw %a5l,%d3l,>>,%a1@-&,%sp,%acc2
+    38fc:	a213 320d      	macw %a5l,%d3l,<<,%a3@,%d1,%acc1
+    3900:	a293 321d      	macw %a5l,%d3l,<<,%a3@,%d1,%acc2
+    3904:	a653 320d      	macw %a5l,%d3l,<<,%a3@,%a3,%acc1
+    3908:	a6d3 321d      	macw %a5l,%d3l,<<,%a3@,%a3,%acc2
+    390c:	a413 320d      	macw %a5l,%d3l,<<,%a3@,%d2,%acc1
+    3910:	a493 321d      	macw %a5l,%d3l,<<,%a3@,%d2,%acc2
+    3914:	ae53 320d      	macw %a5l,%d3l,<<,%a3@,%sp,%acc1
+    3918:	aed3 321d      	macw %a5l,%d3l,<<,%a3@,%sp,%acc2
+    391c:	a213 322d      	macw %a5l,%d3l,<<,%a3@&,%d1,%acc1
+    3920:	a293 323d      	macw %a5l,%d3l,<<,%a3@&,%d1,%acc2
+    3924:	a653 322d      	macw %a5l,%d3l,<<,%a3@&,%a3,%acc1
+    3928:	a6d3 323d      	macw %a5l,%d3l,<<,%a3@&,%a3,%acc2
+    392c:	a413 322d      	macw %a5l,%d3l,<<,%a3@&,%d2,%acc1
+    3930:	a493 323d      	macw %a5l,%d3l,<<,%a3@&,%d2,%acc2
+    3934:	ae53 322d      	macw %a5l,%d3l,<<,%a3@&,%sp,%acc1
+    3938:	aed3 323d      	macw %a5l,%d3l,<<,%a3@&,%sp,%acc2
+    393c:	a21a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d1,%acc1
+    3940:	a29a 321d      	macw %a5l,%d3l,<<,%a2@\+,%d1,%acc2
+    3944:	a65a 320d      	macw %a5l,%d3l,<<,%a2@\+,%a3,%acc1
+    3948:	a6da 321d      	macw %a5l,%d3l,<<,%a2@\+,%a3,%acc2
+    394c:	a41a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d2,%acc1
+    3950:	a49a 321d      	macw %a5l,%d3l,<<,%a2@\+,%d2,%acc2
+    3954:	ae5a 320d      	macw %a5l,%d3l,<<,%a2@\+,%sp,%acc1
+    3958:	aeda 321d      	macw %a5l,%d3l,<<,%a2@\+,%sp,%acc2
+    395c:	a21a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d1,%acc1
+    3960:	a29a 323d      	macw %a5l,%d3l,<<,%a2@\+&,%d1,%acc2
+    3964:	a65a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%a3,%acc1
+    3968:	a6da 323d      	macw %a5l,%d3l,<<,%a2@\+&,%a3,%acc2
+    396c:	a41a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d2,%acc1
+    3970:	a49a 323d      	macw %a5l,%d3l,<<,%a2@\+&,%d2,%acc2
+    3974:	ae5a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%sp,%acc1
+    3978:	aeda 323d      	macw %a5l,%d3l,<<,%a2@\+&,%sp,%acc2
+    397c:	a22e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1,%acc1
+    3982:	a2ae 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1,%acc2
+    3988:	a66e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3,%acc1
+    398e:	a6ee 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3,%acc2
+    3994:	a42e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2,%acc1
+    399a:	a4ae 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2,%acc2
+    39a0:	ae6e 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp,%acc1
+    39a6:	aeee 321d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp,%acc2
+    39ac:	a22e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    39b2:	a2ae 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    39b8:	a66e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    39be:	a6ee 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    39c4:	a42e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    39ca:	a4ae 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    39d0:	ae6e 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    39d6:	aeee 323d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    39dc:	a221 320d      	macw %a5l,%d3l,<<,%a1@-,%d1,%acc1
+    39e0:	a2a1 321d      	macw %a5l,%d3l,<<,%a1@-,%d1,%acc2
+    39e4:	a661 320d      	macw %a5l,%d3l,<<,%a1@-,%a3,%acc1
+    39e8:	a6e1 321d      	macw %a5l,%d3l,<<,%a1@-,%a3,%acc2
+    39ec:	a421 320d      	macw %a5l,%d3l,<<,%a1@-,%d2,%acc1
+    39f0:	a4a1 321d      	macw %a5l,%d3l,<<,%a1@-,%d2,%acc2
+    39f4:	ae61 320d      	macw %a5l,%d3l,<<,%a1@-,%sp,%acc1
+    39f8:	aee1 321d      	macw %a5l,%d3l,<<,%a1@-,%sp,%acc2
+    39fc:	a221 322d      	macw %a5l,%d3l,<<,%a1@-&,%d1,%acc1
+    3a00:	a2a1 323d      	macw %a5l,%d3l,<<,%a1@-&,%d1,%acc2
+    3a04:	a661 322d      	macw %a5l,%d3l,<<,%a1@-&,%a3,%acc1
+    3a08:	a6e1 323d      	macw %a5l,%d3l,<<,%a1@-&,%a3,%acc2
+    3a0c:	a421 322d      	macw %a5l,%d3l,<<,%a1@-&,%d2,%acc1
+    3a10:	a4a1 323d      	macw %a5l,%d3l,<<,%a1@-&,%d2,%acc2
+    3a14:	ae61 322d      	macw %a5l,%d3l,<<,%a1@-&,%sp,%acc1
+    3a18:	aee1 323d      	macw %a5l,%d3l,<<,%a1@-&,%sp,%acc2
+    3a1c:	a213 360d      	macw %a5l,%d3l,>>,%a3@,%d1,%acc1
+    3a20:	a293 361d      	macw %a5l,%d3l,>>,%a3@,%d1,%acc2
+    3a24:	a653 360d      	macw %a5l,%d3l,>>,%a3@,%a3,%acc1
+    3a28:	a6d3 361d      	macw %a5l,%d3l,>>,%a3@,%a3,%acc2
+    3a2c:	a413 360d      	macw %a5l,%d3l,>>,%a3@,%d2,%acc1
+    3a30:	a493 361d      	macw %a5l,%d3l,>>,%a3@,%d2,%acc2
+    3a34:	ae53 360d      	macw %a5l,%d3l,>>,%a3@,%sp,%acc1
+    3a38:	aed3 361d      	macw %a5l,%d3l,>>,%a3@,%sp,%acc2
+    3a3c:	a213 362d      	macw %a5l,%d3l,>>,%a3@&,%d1,%acc1
+    3a40:	a293 363d      	macw %a5l,%d3l,>>,%a3@&,%d1,%acc2
+    3a44:	a653 362d      	macw %a5l,%d3l,>>,%a3@&,%a3,%acc1
+    3a48:	a6d3 363d      	macw %a5l,%d3l,>>,%a3@&,%a3,%acc2
+    3a4c:	a413 362d      	macw %a5l,%d3l,>>,%a3@&,%d2,%acc1
+    3a50:	a493 363d      	macw %a5l,%d3l,>>,%a3@&,%d2,%acc2
+    3a54:	ae53 362d      	macw %a5l,%d3l,>>,%a3@&,%sp,%acc1
+    3a58:	aed3 363d      	macw %a5l,%d3l,>>,%a3@&,%sp,%acc2
+    3a5c:	a21a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d1,%acc1
+    3a60:	a29a 361d      	macw %a5l,%d3l,>>,%a2@\+,%d1,%acc2
+    3a64:	a65a 360d      	macw %a5l,%d3l,>>,%a2@\+,%a3,%acc1
+    3a68:	a6da 361d      	macw %a5l,%d3l,>>,%a2@\+,%a3,%acc2
+    3a6c:	a41a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d2,%acc1
+    3a70:	a49a 361d      	macw %a5l,%d3l,>>,%a2@\+,%d2,%acc2
+    3a74:	ae5a 360d      	macw %a5l,%d3l,>>,%a2@\+,%sp,%acc1
+    3a78:	aeda 361d      	macw %a5l,%d3l,>>,%a2@\+,%sp,%acc2
+    3a7c:	a21a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d1,%acc1
+    3a80:	a29a 363d      	macw %a5l,%d3l,>>,%a2@\+&,%d1,%acc2
+    3a84:	a65a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%a3,%acc1
+    3a88:	a6da 363d      	macw %a5l,%d3l,>>,%a2@\+&,%a3,%acc2
+    3a8c:	a41a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d2,%acc1
+    3a90:	a49a 363d      	macw %a5l,%d3l,>>,%a2@\+&,%d2,%acc2
+    3a94:	ae5a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%sp,%acc1
+    3a98:	aeda 363d      	macw %a5l,%d3l,>>,%a2@\+&,%sp,%acc2
+    3a9c:	a22e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1,%acc1
+    3aa2:	a2ae 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1,%acc2
+    3aa8:	a66e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3,%acc1
+    3aae:	a6ee 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3,%acc2
+    3ab4:	a42e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2,%acc1
+    3aba:	a4ae 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2,%acc2
+    3ac0:	ae6e 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp,%acc1
+    3ac6:	aeee 361d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp,%acc2
+    3acc:	a22e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    3ad2:	a2ae 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    3ad8:	a66e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    3ade:	a6ee 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    3ae4:	a42e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    3aea:	a4ae 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    3af0:	ae6e 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    3af6:	aeee 363d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    3afc:	a221 360d      	macw %a5l,%d3l,>>,%a1@-,%d1,%acc1
+    3b00:	a2a1 361d      	macw %a5l,%d3l,>>,%a1@-,%d1,%acc2
+    3b04:	a661 360d      	macw %a5l,%d3l,>>,%a1@-,%a3,%acc1
+    3b08:	a6e1 361d      	macw %a5l,%d3l,>>,%a1@-,%a3,%acc2
+    3b0c:	a421 360d      	macw %a5l,%d3l,>>,%a1@-,%d2,%acc1
+    3b10:	a4a1 361d      	macw %a5l,%d3l,>>,%a1@-,%d2,%acc2
+    3b14:	ae61 360d      	macw %a5l,%d3l,>>,%a1@-,%sp,%acc1
+    3b18:	aee1 361d      	macw %a5l,%d3l,>>,%a1@-,%sp,%acc2
+    3b1c:	a221 362d      	macw %a5l,%d3l,>>,%a1@-&,%d1,%acc1
+    3b20:	a2a1 363d      	macw %a5l,%d3l,>>,%a1@-&,%d1,%acc2
+    3b24:	a661 362d      	macw %a5l,%d3l,>>,%a1@-&,%a3,%acc1
+    3b28:	a6e1 363d      	macw %a5l,%d3l,>>,%a1@-&,%a3,%acc2
+    3b2c:	a421 362d      	macw %a5l,%d3l,>>,%a1@-&,%d2,%acc1
+    3b30:	a4a1 363d      	macw %a5l,%d3l,>>,%a1@-&,%d2,%acc2
+    3b34:	ae61 362d      	macw %a5l,%d3l,>>,%a1@-&,%sp,%acc1
+    3b38:	aee1 363d      	macw %a5l,%d3l,>>,%a1@-&,%sp,%acc2
+    3b3c:	a213 f08d      	macw %a5l,%a7u,%a3@,%d1,%acc1
+    3b40:	a293 f09d      	macw %a5l,%a7u,%a3@,%d1,%acc2
+    3b44:	a653 f08d      	macw %a5l,%a7u,%a3@,%a3,%acc1
+    3b48:	a6d3 f09d      	macw %a5l,%a7u,%a3@,%a3,%acc2
+    3b4c:	a413 f08d      	macw %a5l,%a7u,%a3@,%d2,%acc1
+    3b50:	a493 f09d      	macw %a5l,%a7u,%a3@,%d2,%acc2
+    3b54:	ae53 f08d      	macw %a5l,%a7u,%a3@,%sp,%acc1
+    3b58:	aed3 f09d      	macw %a5l,%a7u,%a3@,%sp,%acc2
+    3b5c:	a213 f0ad      	macw %a5l,%a7u,%a3@&,%d1,%acc1
+    3b60:	a293 f0bd      	macw %a5l,%a7u,%a3@&,%d1,%acc2
+    3b64:	a653 f0ad      	macw %a5l,%a7u,%a3@&,%a3,%acc1
+    3b68:	a6d3 f0bd      	macw %a5l,%a7u,%a3@&,%a3,%acc2
+    3b6c:	a413 f0ad      	macw %a5l,%a7u,%a3@&,%d2,%acc1
+    3b70:	a493 f0bd      	macw %a5l,%a7u,%a3@&,%d2,%acc2
+    3b74:	ae53 f0ad      	macw %a5l,%a7u,%a3@&,%sp,%acc1
+    3b78:	aed3 f0bd      	macw %a5l,%a7u,%a3@&,%sp,%acc2
+    3b7c:	a21a f08d      	macw %a5l,%a7u,%a2@\+,%d1,%acc1
+    3b80:	a29a f09d      	macw %a5l,%a7u,%a2@\+,%d1,%acc2
+    3b84:	a65a f08d      	macw %a5l,%a7u,%a2@\+,%a3,%acc1
+    3b88:	a6da f09d      	macw %a5l,%a7u,%a2@\+,%a3,%acc2
+    3b8c:	a41a f08d      	macw %a5l,%a7u,%a2@\+,%d2,%acc1
+    3b90:	a49a f09d      	macw %a5l,%a7u,%a2@\+,%d2,%acc2
+    3b94:	ae5a f08d      	macw %a5l,%a7u,%a2@\+,%sp,%acc1
+    3b98:	aeda f09d      	macw %a5l,%a7u,%a2@\+,%sp,%acc2
+    3b9c:	a21a f0ad      	macw %a5l,%a7u,%a2@\+&,%d1,%acc1
+    3ba0:	a29a f0bd      	macw %a5l,%a7u,%a2@\+&,%d1,%acc2
+    3ba4:	a65a f0ad      	macw %a5l,%a7u,%a2@\+&,%a3,%acc1
+    3ba8:	a6da f0bd      	macw %a5l,%a7u,%a2@\+&,%a3,%acc2
+    3bac:	a41a f0ad      	macw %a5l,%a7u,%a2@\+&,%d2,%acc1
+    3bb0:	a49a f0bd      	macw %a5l,%a7u,%a2@\+&,%d2,%acc2
+    3bb4:	ae5a f0ad      	macw %a5l,%a7u,%a2@\+&,%sp,%acc1
+    3bb8:	aeda f0bd      	macw %a5l,%a7u,%a2@\+&,%sp,%acc2
+    3bbc:	a22e f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%d1,%acc1
+    3bc2:	a2ae f09d 000a 	macw %a5l,%a7u,%fp@\(10\),%d1,%acc2
+    3bc8:	a66e f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%a3,%acc1
+    3bce:	a6ee f09d 000a 	macw %a5l,%a7u,%fp@\(10\),%a3,%acc2
+    3bd4:	a42e f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%d2,%acc1
+    3bda:	a4ae f09d 000a 	macw %a5l,%a7u,%fp@\(10\),%d2,%acc2
+    3be0:	ae6e f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%sp,%acc1
+    3be6:	aeee f09d 000a 	macw %a5l,%a7u,%fp@\(10\),%sp,%acc2
+    3bec:	a22e f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d1,%acc1
+    3bf2:	a2ae f0bd 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d1,%acc2
+    3bf8:	a66e f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%a3,%acc1
+    3bfe:	a6ee f0bd 000a 	macw %a5l,%a7u,%fp@\(10\)&,%a3,%acc2
+    3c04:	a42e f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d2,%acc1
+    3c0a:	a4ae f0bd 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d2,%acc2
+    3c10:	ae6e f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%sp,%acc1
+    3c16:	aeee f0bd 000a 	macw %a5l,%a7u,%fp@\(10\)&,%sp,%acc2
+    3c1c:	a221 f08d      	macw %a5l,%a7u,%a1@-,%d1,%acc1
+    3c20:	a2a1 f09d      	macw %a5l,%a7u,%a1@-,%d1,%acc2
+    3c24:	a661 f08d      	macw %a5l,%a7u,%a1@-,%a3,%acc1
+    3c28:	a6e1 f09d      	macw %a5l,%a7u,%a1@-,%a3,%acc2
+    3c2c:	a421 f08d      	macw %a5l,%a7u,%a1@-,%d2,%acc1
+    3c30:	a4a1 f09d      	macw %a5l,%a7u,%a1@-,%d2,%acc2
+    3c34:	ae61 f08d      	macw %a5l,%a7u,%a1@-,%sp,%acc1
+    3c38:	aee1 f09d      	macw %a5l,%a7u,%a1@-,%sp,%acc2
+    3c3c:	a221 f0ad      	macw %a5l,%a7u,%a1@-&,%d1,%acc1
+    3c40:	a2a1 f0bd      	macw %a5l,%a7u,%a1@-&,%d1,%acc2
+    3c44:	a661 f0ad      	macw %a5l,%a7u,%a1@-&,%a3,%acc1
+    3c48:	a6e1 f0bd      	macw %a5l,%a7u,%a1@-&,%a3,%acc2
+    3c4c:	a421 f0ad      	macw %a5l,%a7u,%a1@-&,%d2,%acc1
+    3c50:	a4a1 f0bd      	macw %a5l,%a7u,%a1@-&,%d2,%acc2
+    3c54:	ae61 f0ad      	macw %a5l,%a7u,%a1@-&,%sp,%acc1
+    3c58:	aee1 f0bd      	macw %a5l,%a7u,%a1@-&,%sp,%acc2
+    3c5c:	a213 f28d      	macw %a5l,%a7u,<<,%a3@,%d1,%acc1
+    3c60:	a293 f29d      	macw %a5l,%a7u,<<,%a3@,%d1,%acc2
+    3c64:	a653 f28d      	macw %a5l,%a7u,<<,%a3@,%a3,%acc1
+    3c68:	a6d3 f29d      	macw %a5l,%a7u,<<,%a3@,%a3,%acc2
+    3c6c:	a413 f28d      	macw %a5l,%a7u,<<,%a3@,%d2,%acc1
+    3c70:	a493 f29d      	macw %a5l,%a7u,<<,%a3@,%d2,%acc2
+    3c74:	ae53 f28d      	macw %a5l,%a7u,<<,%a3@,%sp,%acc1
+    3c78:	aed3 f29d      	macw %a5l,%a7u,<<,%a3@,%sp,%acc2
+    3c7c:	a213 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d1,%acc1
+    3c80:	a293 f2bd      	macw %a5l,%a7u,<<,%a3@&,%d1,%acc2
+    3c84:	a653 f2ad      	macw %a5l,%a7u,<<,%a3@&,%a3,%acc1
+    3c88:	a6d3 f2bd      	macw %a5l,%a7u,<<,%a3@&,%a3,%acc2
+    3c8c:	a413 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d2,%acc1
+    3c90:	a493 f2bd      	macw %a5l,%a7u,<<,%a3@&,%d2,%acc2
+    3c94:	ae53 f2ad      	macw %a5l,%a7u,<<,%a3@&,%sp,%acc1
+    3c98:	aed3 f2bd      	macw %a5l,%a7u,<<,%a3@&,%sp,%acc2
+    3c9c:	a21a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d1,%acc1
+    3ca0:	a29a f29d      	macw %a5l,%a7u,<<,%a2@\+,%d1,%acc2
+    3ca4:	a65a f28d      	macw %a5l,%a7u,<<,%a2@\+,%a3,%acc1
+    3ca8:	a6da f29d      	macw %a5l,%a7u,<<,%a2@\+,%a3,%acc2
+    3cac:	a41a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d2,%acc1
+    3cb0:	a49a f29d      	macw %a5l,%a7u,<<,%a2@\+,%d2,%acc2
+    3cb4:	ae5a f28d      	macw %a5l,%a7u,<<,%a2@\+,%sp,%acc1
+    3cb8:	aeda f29d      	macw %a5l,%a7u,<<,%a2@\+,%sp,%acc2
+    3cbc:	a21a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d1,%acc1
+    3cc0:	a29a f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%d1,%acc2
+    3cc4:	a65a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%a3,%acc1
+    3cc8:	a6da f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%a3,%acc2
+    3ccc:	a41a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d2,%acc1
+    3cd0:	a49a f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%d2,%acc2
+    3cd4:	ae5a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%sp,%acc1
+    3cd8:	aeda f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%sp,%acc2
+    3cdc:	a22e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1,%acc1
+    3ce2:	a2ae f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1,%acc2
+    3ce8:	a66e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3,%acc1
+    3cee:	a6ee f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3,%acc2
+    3cf4:	a42e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2,%acc1
+    3cfa:	a4ae f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2,%acc2
+    3d00:	ae6e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp,%acc1
+    3d06:	aeee f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp,%acc2
+    3d0c:	a22e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    3d12:	a2ae f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    3d18:	a66e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    3d1e:	a6ee f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    3d24:	a42e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    3d2a:	a4ae f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    3d30:	ae6e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    3d36:	aeee f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    3d3c:	a221 f28d      	macw %a5l,%a7u,<<,%a1@-,%d1,%acc1
+    3d40:	a2a1 f29d      	macw %a5l,%a7u,<<,%a1@-,%d1,%acc2
+    3d44:	a661 f28d      	macw %a5l,%a7u,<<,%a1@-,%a3,%acc1
+    3d48:	a6e1 f29d      	macw %a5l,%a7u,<<,%a1@-,%a3,%acc2
+    3d4c:	a421 f28d      	macw %a5l,%a7u,<<,%a1@-,%d2,%acc1
+    3d50:	a4a1 f29d      	macw %a5l,%a7u,<<,%a1@-,%d2,%acc2
+    3d54:	ae61 f28d      	macw %a5l,%a7u,<<,%a1@-,%sp,%acc1
+    3d58:	aee1 f29d      	macw %a5l,%a7u,<<,%a1@-,%sp,%acc2
+    3d5c:	a221 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d1,%acc1
+    3d60:	a2a1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%d1,%acc2
+    3d64:	a661 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%a3,%acc1
+    3d68:	a6e1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%a3,%acc2
+    3d6c:	a421 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d2,%acc1
+    3d70:	a4a1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%d2,%acc2
+    3d74:	ae61 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%sp,%acc1
+    3d78:	aee1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%sp,%acc2
+    3d7c:	a213 f68d      	macw %a5l,%a7u,>>,%a3@,%d1,%acc1
+    3d80:	a293 f69d      	macw %a5l,%a7u,>>,%a3@,%d1,%acc2
+    3d84:	a653 f68d      	macw %a5l,%a7u,>>,%a3@,%a3,%acc1
+    3d88:	a6d3 f69d      	macw %a5l,%a7u,>>,%a3@,%a3,%acc2
+    3d8c:	a413 f68d      	macw %a5l,%a7u,>>,%a3@,%d2,%acc1
+    3d90:	a493 f69d      	macw %a5l,%a7u,>>,%a3@,%d2,%acc2
+    3d94:	ae53 f68d      	macw %a5l,%a7u,>>,%a3@,%sp,%acc1
+    3d98:	aed3 f69d      	macw %a5l,%a7u,>>,%a3@,%sp,%acc2
+    3d9c:	a213 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d1,%acc1
+    3da0:	a293 f6bd      	macw %a5l,%a7u,>>,%a3@&,%d1,%acc2
+    3da4:	a653 f6ad      	macw %a5l,%a7u,>>,%a3@&,%a3,%acc1
+    3da8:	a6d3 f6bd      	macw %a5l,%a7u,>>,%a3@&,%a3,%acc2
+    3dac:	a413 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d2,%acc1
+    3db0:	a493 f6bd      	macw %a5l,%a7u,>>,%a3@&,%d2,%acc2
+    3db4:	ae53 f6ad      	macw %a5l,%a7u,>>,%a3@&,%sp,%acc1
+    3db8:	aed3 f6bd      	macw %a5l,%a7u,>>,%a3@&,%sp,%acc2
+    3dbc:	a21a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d1,%acc1
+    3dc0:	a29a f69d      	macw %a5l,%a7u,>>,%a2@\+,%d1,%acc2
+    3dc4:	a65a f68d      	macw %a5l,%a7u,>>,%a2@\+,%a3,%acc1
+    3dc8:	a6da f69d      	macw %a5l,%a7u,>>,%a2@\+,%a3,%acc2
+    3dcc:	a41a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d2,%acc1
+    3dd0:	a49a f69d      	macw %a5l,%a7u,>>,%a2@\+,%d2,%acc2
+    3dd4:	ae5a f68d      	macw %a5l,%a7u,>>,%a2@\+,%sp,%acc1
+    3dd8:	aeda f69d      	macw %a5l,%a7u,>>,%a2@\+,%sp,%acc2
+    3ddc:	a21a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d1,%acc1
+    3de0:	a29a f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%d1,%acc2
+    3de4:	a65a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%a3,%acc1
+    3de8:	a6da f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%a3,%acc2
+    3dec:	a41a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d2,%acc1
+    3df0:	a49a f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%d2,%acc2
+    3df4:	ae5a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%sp,%acc1
+    3df8:	aeda f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%sp,%acc2
+    3dfc:	a22e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1,%acc1
+    3e02:	a2ae f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1,%acc2
+    3e08:	a66e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3,%acc1
+    3e0e:	a6ee f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3,%acc2
+    3e14:	a42e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2,%acc1
+    3e1a:	a4ae f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2,%acc2
+    3e20:	ae6e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp,%acc1
+    3e26:	aeee f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp,%acc2
+    3e2c:	a22e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    3e32:	a2ae f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    3e38:	a66e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    3e3e:	a6ee f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    3e44:	a42e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    3e4a:	a4ae f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    3e50:	ae6e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    3e56:	aeee f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    3e5c:	a221 f68d      	macw %a5l,%a7u,>>,%a1@-,%d1,%acc1
+    3e60:	a2a1 f69d      	macw %a5l,%a7u,>>,%a1@-,%d1,%acc2
+    3e64:	a661 f68d      	macw %a5l,%a7u,>>,%a1@-,%a3,%acc1
+    3e68:	a6e1 f69d      	macw %a5l,%a7u,>>,%a1@-,%a3,%acc2
+    3e6c:	a421 f68d      	macw %a5l,%a7u,>>,%a1@-,%d2,%acc1
+    3e70:	a4a1 f69d      	macw %a5l,%a7u,>>,%a1@-,%d2,%acc2
+    3e74:	ae61 f68d      	macw %a5l,%a7u,>>,%a1@-,%sp,%acc1
+    3e78:	aee1 f69d      	macw %a5l,%a7u,>>,%a1@-,%sp,%acc2
+    3e7c:	a221 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d1,%acc1
+    3e80:	a2a1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%d1,%acc2
+    3e84:	a661 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%a3,%acc1
+    3e88:	a6e1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%a3,%acc2
+    3e8c:	a421 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d2,%acc1
+    3e90:	a4a1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%d2,%acc2
+    3e94:	ae61 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%sp,%acc1
+    3e98:	aee1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%sp,%acc2
+    3e9c:	a213 f28d      	macw %a5l,%a7u,<<,%a3@,%d1,%acc1
+    3ea0:	a293 f29d      	macw %a5l,%a7u,<<,%a3@,%d1,%acc2
+    3ea4:	a653 f28d      	macw %a5l,%a7u,<<,%a3@,%a3,%acc1
+    3ea8:	a6d3 f29d      	macw %a5l,%a7u,<<,%a3@,%a3,%acc2
+    3eac:	a413 f28d      	macw %a5l,%a7u,<<,%a3@,%d2,%acc1
+    3eb0:	a493 f29d      	macw %a5l,%a7u,<<,%a3@,%d2,%acc2
+    3eb4:	ae53 f28d      	macw %a5l,%a7u,<<,%a3@,%sp,%acc1
+    3eb8:	aed3 f29d      	macw %a5l,%a7u,<<,%a3@,%sp,%acc2
+    3ebc:	a213 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d1,%acc1
+    3ec0:	a293 f2bd      	macw %a5l,%a7u,<<,%a3@&,%d1,%acc2
+    3ec4:	a653 f2ad      	macw %a5l,%a7u,<<,%a3@&,%a3,%acc1
+    3ec8:	a6d3 f2bd      	macw %a5l,%a7u,<<,%a3@&,%a3,%acc2
+    3ecc:	a413 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d2,%acc1
+    3ed0:	a493 f2bd      	macw %a5l,%a7u,<<,%a3@&,%d2,%acc2
+    3ed4:	ae53 f2ad      	macw %a5l,%a7u,<<,%a3@&,%sp,%acc1
+    3ed8:	aed3 f2bd      	macw %a5l,%a7u,<<,%a3@&,%sp,%acc2
+    3edc:	a21a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d1,%acc1
+    3ee0:	a29a f29d      	macw %a5l,%a7u,<<,%a2@\+,%d1,%acc2
+    3ee4:	a65a f28d      	macw %a5l,%a7u,<<,%a2@\+,%a3,%acc1
+    3ee8:	a6da f29d      	macw %a5l,%a7u,<<,%a2@\+,%a3,%acc2
+    3eec:	a41a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d2,%acc1
+    3ef0:	a49a f29d      	macw %a5l,%a7u,<<,%a2@\+,%d2,%acc2
+    3ef4:	ae5a f28d      	macw %a5l,%a7u,<<,%a2@\+,%sp,%acc1
+    3ef8:	aeda f29d      	macw %a5l,%a7u,<<,%a2@\+,%sp,%acc2
+    3efc:	a21a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d1,%acc1
+    3f00:	a29a f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%d1,%acc2
+    3f04:	a65a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%a3,%acc1
+    3f08:	a6da f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%a3,%acc2
+    3f0c:	a41a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d2,%acc1
+    3f10:	a49a f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%d2,%acc2
+    3f14:	ae5a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%sp,%acc1
+    3f18:	aeda f2bd      	macw %a5l,%a7u,<<,%a2@\+&,%sp,%acc2
+    3f1c:	a22e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1,%acc1
+    3f22:	a2ae f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1,%acc2
+    3f28:	a66e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3,%acc1
+    3f2e:	a6ee f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3,%acc2
+    3f34:	a42e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2,%acc1
+    3f3a:	a4ae f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2,%acc2
+    3f40:	ae6e f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp,%acc1
+    3f46:	aeee f29d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp,%acc2
+    3f4c:	a22e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    3f52:	a2ae f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    3f58:	a66e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    3f5e:	a6ee f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    3f64:	a42e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    3f6a:	a4ae f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    3f70:	ae6e f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    3f76:	aeee f2bd 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    3f7c:	a221 f28d      	macw %a5l,%a7u,<<,%a1@-,%d1,%acc1
+    3f80:	a2a1 f29d      	macw %a5l,%a7u,<<,%a1@-,%d1,%acc2
+    3f84:	a661 f28d      	macw %a5l,%a7u,<<,%a1@-,%a3,%acc1
+    3f88:	a6e1 f29d      	macw %a5l,%a7u,<<,%a1@-,%a3,%acc2
+    3f8c:	a421 f28d      	macw %a5l,%a7u,<<,%a1@-,%d2,%acc1
+    3f90:	a4a1 f29d      	macw %a5l,%a7u,<<,%a1@-,%d2,%acc2
+    3f94:	ae61 f28d      	macw %a5l,%a7u,<<,%a1@-,%sp,%acc1
+    3f98:	aee1 f29d      	macw %a5l,%a7u,<<,%a1@-,%sp,%acc2
+    3f9c:	a221 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d1,%acc1
+    3fa0:	a2a1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%d1,%acc2
+    3fa4:	a661 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%a3,%acc1
+    3fa8:	a6e1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%a3,%acc2
+    3fac:	a421 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d2,%acc1
+    3fb0:	a4a1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%d2,%acc2
+    3fb4:	ae61 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%sp,%acc1
+    3fb8:	aee1 f2bd      	macw %a5l,%a7u,<<,%a1@-&,%sp,%acc2
+    3fbc:	a213 f68d      	macw %a5l,%a7u,>>,%a3@,%d1,%acc1
+    3fc0:	a293 f69d      	macw %a5l,%a7u,>>,%a3@,%d1,%acc2
+    3fc4:	a653 f68d      	macw %a5l,%a7u,>>,%a3@,%a3,%acc1
+    3fc8:	a6d3 f69d      	macw %a5l,%a7u,>>,%a3@,%a3,%acc2
+    3fcc:	a413 f68d      	macw %a5l,%a7u,>>,%a3@,%d2,%acc1
+    3fd0:	a493 f69d      	macw %a5l,%a7u,>>,%a3@,%d2,%acc2
+    3fd4:	ae53 f68d      	macw %a5l,%a7u,>>,%a3@,%sp,%acc1
+    3fd8:	aed3 f69d      	macw %a5l,%a7u,>>,%a3@,%sp,%acc2
+    3fdc:	a213 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d1,%acc1
+    3fe0:	a293 f6bd      	macw %a5l,%a7u,>>,%a3@&,%d1,%acc2
+    3fe4:	a653 f6ad      	macw %a5l,%a7u,>>,%a3@&,%a3,%acc1
+    3fe8:	a6d3 f6bd      	macw %a5l,%a7u,>>,%a3@&,%a3,%acc2
+    3fec:	a413 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d2,%acc1
+    3ff0:	a493 f6bd      	macw %a5l,%a7u,>>,%a3@&,%d2,%acc2
+    3ff4:	ae53 f6ad      	macw %a5l,%a7u,>>,%a3@&,%sp,%acc1
+    3ff8:	aed3 f6bd      	macw %a5l,%a7u,>>,%a3@&,%sp,%acc2
+    3ffc:	a21a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d1,%acc1
+    4000:	a29a f69d      	macw %a5l,%a7u,>>,%a2@\+,%d1,%acc2
+    4004:	a65a f68d      	macw %a5l,%a7u,>>,%a2@\+,%a3,%acc1
+    4008:	a6da f69d      	macw %a5l,%a7u,>>,%a2@\+,%a3,%acc2
+    400c:	a41a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d2,%acc1
+    4010:	a49a f69d      	macw %a5l,%a7u,>>,%a2@\+,%d2,%acc2
+    4014:	ae5a f68d      	macw %a5l,%a7u,>>,%a2@\+,%sp,%acc1
+    4018:	aeda f69d      	macw %a5l,%a7u,>>,%a2@\+,%sp,%acc2
+    401c:	a21a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d1,%acc1
+    4020:	a29a f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%d1,%acc2
+    4024:	a65a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%a3,%acc1
+    4028:	a6da f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%a3,%acc2
+    402c:	a41a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d2,%acc1
+    4030:	a49a f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%d2,%acc2
+    4034:	ae5a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%sp,%acc1
+    4038:	aeda f6bd      	macw %a5l,%a7u,>>,%a2@\+&,%sp,%acc2
+    403c:	a22e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1,%acc1
+    4042:	a2ae f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1,%acc2
+    4048:	a66e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3,%acc1
+    404e:	a6ee f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3,%acc2
+    4054:	a42e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2,%acc1
+    405a:	a4ae f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2,%acc2
+    4060:	ae6e f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp,%acc1
+    4066:	aeee f69d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp,%acc2
+    406c:	a22e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    4072:	a2ae f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    4078:	a66e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    407e:	a6ee f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    4084:	a42e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    408a:	a4ae f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    4090:	ae6e f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    4096:	aeee f6bd 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    409c:	a221 f68d      	macw %a5l,%a7u,>>,%a1@-,%d1,%acc1
+    40a0:	a2a1 f69d      	macw %a5l,%a7u,>>,%a1@-,%d1,%acc2
+    40a4:	a661 f68d      	macw %a5l,%a7u,>>,%a1@-,%a3,%acc1
+    40a8:	a6e1 f69d      	macw %a5l,%a7u,>>,%a1@-,%a3,%acc2
+    40ac:	a421 f68d      	macw %a5l,%a7u,>>,%a1@-,%d2,%acc1
+    40b0:	a4a1 f69d      	macw %a5l,%a7u,>>,%a1@-,%d2,%acc2
+    40b4:	ae61 f68d      	macw %a5l,%a7u,>>,%a1@-,%sp,%acc1
+    40b8:	aee1 f69d      	macw %a5l,%a7u,>>,%a1@-,%sp,%acc2
+    40bc:	a221 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d1,%acc1
+    40c0:	a2a1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%d1,%acc2
+    40c4:	a661 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%a3,%acc1
+    40c8:	a6e1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%a3,%acc2
+    40cc:	a421 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d2,%acc1
+    40d0:	a4a1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%d2,%acc2
+    40d4:	ae61 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%sp,%acc1
+    40d8:	aee1 f6bd      	macw %a5l,%a7u,>>,%a1@-&,%sp,%acc2
+    40dc:	a213 100d      	macw %a5l,%d1l,%a3@,%d1,%acc1
+    40e0:	a293 101d      	macw %a5l,%d1l,%a3@,%d1,%acc2
+    40e4:	a653 100d      	macw %a5l,%d1l,%a3@,%a3,%acc1
+    40e8:	a6d3 101d      	macw %a5l,%d1l,%a3@,%a3,%acc2
+    40ec:	a413 100d      	macw %a5l,%d1l,%a3@,%d2,%acc1
+    40f0:	a493 101d      	macw %a5l,%d1l,%a3@,%d2,%acc2
+    40f4:	ae53 100d      	macw %a5l,%d1l,%a3@,%sp,%acc1
+    40f8:	aed3 101d      	macw %a5l,%d1l,%a3@,%sp,%acc2
+    40fc:	a213 102d      	macw %a5l,%d1l,%a3@&,%d1,%acc1
+    4100:	a293 103d      	macw %a5l,%d1l,%a3@&,%d1,%acc2
+    4104:	a653 102d      	macw %a5l,%d1l,%a3@&,%a3,%acc1
+    4108:	a6d3 103d      	macw %a5l,%d1l,%a3@&,%a3,%acc2
+    410c:	a413 102d      	macw %a5l,%d1l,%a3@&,%d2,%acc1
+    4110:	a493 103d      	macw %a5l,%d1l,%a3@&,%d2,%acc2
+    4114:	ae53 102d      	macw %a5l,%d1l,%a3@&,%sp,%acc1
+    4118:	aed3 103d      	macw %a5l,%d1l,%a3@&,%sp,%acc2
+    411c:	a21a 100d      	macw %a5l,%d1l,%a2@\+,%d1,%acc1
+    4120:	a29a 101d      	macw %a5l,%d1l,%a2@\+,%d1,%acc2
+    4124:	a65a 100d      	macw %a5l,%d1l,%a2@\+,%a3,%acc1
+    4128:	a6da 101d      	macw %a5l,%d1l,%a2@\+,%a3,%acc2
+    412c:	a41a 100d      	macw %a5l,%d1l,%a2@\+,%d2,%acc1
+    4130:	a49a 101d      	macw %a5l,%d1l,%a2@\+,%d2,%acc2
+    4134:	ae5a 100d      	macw %a5l,%d1l,%a2@\+,%sp,%acc1
+    4138:	aeda 101d      	macw %a5l,%d1l,%a2@\+,%sp,%acc2
+    413c:	a21a 102d      	macw %a5l,%d1l,%a2@\+&,%d1,%acc1
+    4140:	a29a 103d      	macw %a5l,%d1l,%a2@\+&,%d1,%acc2
+    4144:	a65a 102d      	macw %a5l,%d1l,%a2@\+&,%a3,%acc1
+    4148:	a6da 103d      	macw %a5l,%d1l,%a2@\+&,%a3,%acc2
+    414c:	a41a 102d      	macw %a5l,%d1l,%a2@\+&,%d2,%acc1
+    4150:	a49a 103d      	macw %a5l,%d1l,%a2@\+&,%d2,%acc2
+    4154:	ae5a 102d      	macw %a5l,%d1l,%a2@\+&,%sp,%acc1
+    4158:	aeda 103d      	macw %a5l,%d1l,%a2@\+&,%sp,%acc2
+    415c:	a22e 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%d1,%acc1
+    4162:	a2ae 101d 000a 	macw %a5l,%d1l,%fp@\(10\),%d1,%acc2
+    4168:	a66e 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%a3,%acc1
+    416e:	a6ee 101d 000a 	macw %a5l,%d1l,%fp@\(10\),%a3,%acc2
+    4174:	a42e 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%d2,%acc1
+    417a:	a4ae 101d 000a 	macw %a5l,%d1l,%fp@\(10\),%d2,%acc2
+    4180:	ae6e 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%sp,%acc1
+    4186:	aeee 101d 000a 	macw %a5l,%d1l,%fp@\(10\),%sp,%acc2
+    418c:	a22e 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d1,%acc1
+    4192:	a2ae 103d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d1,%acc2
+    4198:	a66e 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%a3,%acc1
+    419e:	a6ee 103d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%a3,%acc2
+    41a4:	a42e 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d2,%acc1
+    41aa:	a4ae 103d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d2,%acc2
+    41b0:	ae6e 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%sp,%acc1
+    41b6:	aeee 103d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%sp,%acc2
+    41bc:	a221 100d      	macw %a5l,%d1l,%a1@-,%d1,%acc1
+    41c0:	a2a1 101d      	macw %a5l,%d1l,%a1@-,%d1,%acc2
+    41c4:	a661 100d      	macw %a5l,%d1l,%a1@-,%a3,%acc1
+    41c8:	a6e1 101d      	macw %a5l,%d1l,%a1@-,%a3,%acc2
+    41cc:	a421 100d      	macw %a5l,%d1l,%a1@-,%d2,%acc1
+    41d0:	a4a1 101d      	macw %a5l,%d1l,%a1@-,%d2,%acc2
+    41d4:	ae61 100d      	macw %a5l,%d1l,%a1@-,%sp,%acc1
+    41d8:	aee1 101d      	macw %a5l,%d1l,%a1@-,%sp,%acc2
+    41dc:	a221 102d      	macw %a5l,%d1l,%a1@-&,%d1,%acc1
+    41e0:	a2a1 103d      	macw %a5l,%d1l,%a1@-&,%d1,%acc2
+    41e4:	a661 102d      	macw %a5l,%d1l,%a1@-&,%a3,%acc1
+    41e8:	a6e1 103d      	macw %a5l,%d1l,%a1@-&,%a3,%acc2
+    41ec:	a421 102d      	macw %a5l,%d1l,%a1@-&,%d2,%acc1
+    41f0:	a4a1 103d      	macw %a5l,%d1l,%a1@-&,%d2,%acc2
+    41f4:	ae61 102d      	macw %a5l,%d1l,%a1@-&,%sp,%acc1
+    41f8:	aee1 103d      	macw %a5l,%d1l,%a1@-&,%sp,%acc2
+    41fc:	a213 120d      	macw %a5l,%d1l,<<,%a3@,%d1,%acc1
+    4200:	a293 121d      	macw %a5l,%d1l,<<,%a3@,%d1,%acc2
+    4204:	a653 120d      	macw %a5l,%d1l,<<,%a3@,%a3,%acc1
+    4208:	a6d3 121d      	macw %a5l,%d1l,<<,%a3@,%a3,%acc2
+    420c:	a413 120d      	macw %a5l,%d1l,<<,%a3@,%d2,%acc1
+    4210:	a493 121d      	macw %a5l,%d1l,<<,%a3@,%d2,%acc2
+    4214:	ae53 120d      	macw %a5l,%d1l,<<,%a3@,%sp,%acc1
+    4218:	aed3 121d      	macw %a5l,%d1l,<<,%a3@,%sp,%acc2
+    421c:	a213 122d      	macw %a5l,%d1l,<<,%a3@&,%d1,%acc1
+    4220:	a293 123d      	macw %a5l,%d1l,<<,%a3@&,%d1,%acc2
+    4224:	a653 122d      	macw %a5l,%d1l,<<,%a3@&,%a3,%acc1
+    4228:	a6d3 123d      	macw %a5l,%d1l,<<,%a3@&,%a3,%acc2
+    422c:	a413 122d      	macw %a5l,%d1l,<<,%a3@&,%d2,%acc1
+    4230:	a493 123d      	macw %a5l,%d1l,<<,%a3@&,%d2,%acc2
+    4234:	ae53 122d      	macw %a5l,%d1l,<<,%a3@&,%sp,%acc1
+    4238:	aed3 123d      	macw %a5l,%d1l,<<,%a3@&,%sp,%acc2
+    423c:	a21a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d1,%acc1
+    4240:	a29a 121d      	macw %a5l,%d1l,<<,%a2@\+,%d1,%acc2
+    4244:	a65a 120d      	macw %a5l,%d1l,<<,%a2@\+,%a3,%acc1
+    4248:	a6da 121d      	macw %a5l,%d1l,<<,%a2@\+,%a3,%acc2
+    424c:	a41a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d2,%acc1
+    4250:	a49a 121d      	macw %a5l,%d1l,<<,%a2@\+,%d2,%acc2
+    4254:	ae5a 120d      	macw %a5l,%d1l,<<,%a2@\+,%sp,%acc1
+    4258:	aeda 121d      	macw %a5l,%d1l,<<,%a2@\+,%sp,%acc2
+    425c:	a21a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d1,%acc1
+    4260:	a29a 123d      	macw %a5l,%d1l,<<,%a2@\+&,%d1,%acc2
+    4264:	a65a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%a3,%acc1
+    4268:	a6da 123d      	macw %a5l,%d1l,<<,%a2@\+&,%a3,%acc2
+    426c:	a41a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d2,%acc1
+    4270:	a49a 123d      	macw %a5l,%d1l,<<,%a2@\+&,%d2,%acc2
+    4274:	ae5a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%sp,%acc1
+    4278:	aeda 123d      	macw %a5l,%d1l,<<,%a2@\+&,%sp,%acc2
+    427c:	a22e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1,%acc1
+    4282:	a2ae 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1,%acc2
+    4288:	a66e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3,%acc1
+    428e:	a6ee 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3,%acc2
+    4294:	a42e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2,%acc1
+    429a:	a4ae 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2,%acc2
+    42a0:	ae6e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp,%acc1
+    42a6:	aeee 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp,%acc2
+    42ac:	a22e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    42b2:	a2ae 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    42b8:	a66e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    42be:	a6ee 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    42c4:	a42e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    42ca:	a4ae 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    42d0:	ae6e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    42d6:	aeee 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    42dc:	a221 120d      	macw %a5l,%d1l,<<,%a1@-,%d1,%acc1
+    42e0:	a2a1 121d      	macw %a5l,%d1l,<<,%a1@-,%d1,%acc2
+    42e4:	a661 120d      	macw %a5l,%d1l,<<,%a1@-,%a3,%acc1
+    42e8:	a6e1 121d      	macw %a5l,%d1l,<<,%a1@-,%a3,%acc2
+    42ec:	a421 120d      	macw %a5l,%d1l,<<,%a1@-,%d2,%acc1
+    42f0:	a4a1 121d      	macw %a5l,%d1l,<<,%a1@-,%d2,%acc2
+    42f4:	ae61 120d      	macw %a5l,%d1l,<<,%a1@-,%sp,%acc1
+    42f8:	aee1 121d      	macw %a5l,%d1l,<<,%a1@-,%sp,%acc2
+    42fc:	a221 122d      	macw %a5l,%d1l,<<,%a1@-&,%d1,%acc1
+    4300:	a2a1 123d      	macw %a5l,%d1l,<<,%a1@-&,%d1,%acc2
+    4304:	a661 122d      	macw %a5l,%d1l,<<,%a1@-&,%a3,%acc1
+    4308:	a6e1 123d      	macw %a5l,%d1l,<<,%a1@-&,%a3,%acc2
+    430c:	a421 122d      	macw %a5l,%d1l,<<,%a1@-&,%d2,%acc1
+    4310:	a4a1 123d      	macw %a5l,%d1l,<<,%a1@-&,%d2,%acc2
+    4314:	ae61 122d      	macw %a5l,%d1l,<<,%a1@-&,%sp,%acc1
+    4318:	aee1 123d      	macw %a5l,%d1l,<<,%a1@-&,%sp,%acc2
+    431c:	a213 160d      	macw %a5l,%d1l,>>,%a3@,%d1,%acc1
+    4320:	a293 161d      	macw %a5l,%d1l,>>,%a3@,%d1,%acc2
+    4324:	a653 160d      	macw %a5l,%d1l,>>,%a3@,%a3,%acc1
+    4328:	a6d3 161d      	macw %a5l,%d1l,>>,%a3@,%a3,%acc2
+    432c:	a413 160d      	macw %a5l,%d1l,>>,%a3@,%d2,%acc1
+    4330:	a493 161d      	macw %a5l,%d1l,>>,%a3@,%d2,%acc2
+    4334:	ae53 160d      	macw %a5l,%d1l,>>,%a3@,%sp,%acc1
+    4338:	aed3 161d      	macw %a5l,%d1l,>>,%a3@,%sp,%acc2
+    433c:	a213 162d      	macw %a5l,%d1l,>>,%a3@&,%d1,%acc1
+    4340:	a293 163d      	macw %a5l,%d1l,>>,%a3@&,%d1,%acc2
+    4344:	a653 162d      	macw %a5l,%d1l,>>,%a3@&,%a3,%acc1
+    4348:	a6d3 163d      	macw %a5l,%d1l,>>,%a3@&,%a3,%acc2
+    434c:	a413 162d      	macw %a5l,%d1l,>>,%a3@&,%d2,%acc1
+    4350:	a493 163d      	macw %a5l,%d1l,>>,%a3@&,%d2,%acc2
+    4354:	ae53 162d      	macw %a5l,%d1l,>>,%a3@&,%sp,%acc1
+    4358:	aed3 163d      	macw %a5l,%d1l,>>,%a3@&,%sp,%acc2
+    435c:	a21a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d1,%acc1
+    4360:	a29a 161d      	macw %a5l,%d1l,>>,%a2@\+,%d1,%acc2
+    4364:	a65a 160d      	macw %a5l,%d1l,>>,%a2@\+,%a3,%acc1
+    4368:	a6da 161d      	macw %a5l,%d1l,>>,%a2@\+,%a3,%acc2
+    436c:	a41a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d2,%acc1
+    4370:	a49a 161d      	macw %a5l,%d1l,>>,%a2@\+,%d2,%acc2
+    4374:	ae5a 160d      	macw %a5l,%d1l,>>,%a2@\+,%sp,%acc1
+    4378:	aeda 161d      	macw %a5l,%d1l,>>,%a2@\+,%sp,%acc2
+    437c:	a21a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d1,%acc1
+    4380:	a29a 163d      	macw %a5l,%d1l,>>,%a2@\+&,%d1,%acc2
+    4384:	a65a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%a3,%acc1
+    4388:	a6da 163d      	macw %a5l,%d1l,>>,%a2@\+&,%a3,%acc2
+    438c:	a41a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d2,%acc1
+    4390:	a49a 163d      	macw %a5l,%d1l,>>,%a2@\+&,%d2,%acc2
+    4394:	ae5a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%sp,%acc1
+    4398:	aeda 163d      	macw %a5l,%d1l,>>,%a2@\+&,%sp,%acc2
+    439c:	a22e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1,%acc1
+    43a2:	a2ae 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1,%acc2
+    43a8:	a66e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3,%acc1
+    43ae:	a6ee 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3,%acc2
+    43b4:	a42e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2,%acc1
+    43ba:	a4ae 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2,%acc2
+    43c0:	ae6e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp,%acc1
+    43c6:	aeee 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp,%acc2
+    43cc:	a22e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    43d2:	a2ae 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    43d8:	a66e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    43de:	a6ee 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    43e4:	a42e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    43ea:	a4ae 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    43f0:	ae6e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    43f6:	aeee 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    43fc:	a221 160d      	macw %a5l,%d1l,>>,%a1@-,%d1,%acc1
+    4400:	a2a1 161d      	macw %a5l,%d1l,>>,%a1@-,%d1,%acc2
+    4404:	a661 160d      	macw %a5l,%d1l,>>,%a1@-,%a3,%acc1
+    4408:	a6e1 161d      	macw %a5l,%d1l,>>,%a1@-,%a3,%acc2
+    440c:	a421 160d      	macw %a5l,%d1l,>>,%a1@-,%d2,%acc1
+    4410:	a4a1 161d      	macw %a5l,%d1l,>>,%a1@-,%d2,%acc2
+    4414:	ae61 160d      	macw %a5l,%d1l,>>,%a1@-,%sp,%acc1
+    4418:	aee1 161d      	macw %a5l,%d1l,>>,%a1@-,%sp,%acc2
+    441c:	a221 162d      	macw %a5l,%d1l,>>,%a1@-&,%d1,%acc1
+    4420:	a2a1 163d      	macw %a5l,%d1l,>>,%a1@-&,%d1,%acc2
+    4424:	a661 162d      	macw %a5l,%d1l,>>,%a1@-&,%a3,%acc1
+    4428:	a6e1 163d      	macw %a5l,%d1l,>>,%a1@-&,%a3,%acc2
+    442c:	a421 162d      	macw %a5l,%d1l,>>,%a1@-&,%d2,%acc1
+    4430:	a4a1 163d      	macw %a5l,%d1l,>>,%a1@-&,%d2,%acc2
+    4434:	ae61 162d      	macw %a5l,%d1l,>>,%a1@-&,%sp,%acc1
+    4438:	aee1 163d      	macw %a5l,%d1l,>>,%a1@-&,%sp,%acc2
+    443c:	a213 120d      	macw %a5l,%d1l,<<,%a3@,%d1,%acc1
+    4440:	a293 121d      	macw %a5l,%d1l,<<,%a3@,%d1,%acc2
+    4444:	a653 120d      	macw %a5l,%d1l,<<,%a3@,%a3,%acc1
+    4448:	a6d3 121d      	macw %a5l,%d1l,<<,%a3@,%a3,%acc2
+    444c:	a413 120d      	macw %a5l,%d1l,<<,%a3@,%d2,%acc1
+    4450:	a493 121d      	macw %a5l,%d1l,<<,%a3@,%d2,%acc2
+    4454:	ae53 120d      	macw %a5l,%d1l,<<,%a3@,%sp,%acc1
+    4458:	aed3 121d      	macw %a5l,%d1l,<<,%a3@,%sp,%acc2
+    445c:	a213 122d      	macw %a5l,%d1l,<<,%a3@&,%d1,%acc1
+    4460:	a293 123d      	macw %a5l,%d1l,<<,%a3@&,%d1,%acc2
+    4464:	a653 122d      	macw %a5l,%d1l,<<,%a3@&,%a3,%acc1
+    4468:	a6d3 123d      	macw %a5l,%d1l,<<,%a3@&,%a3,%acc2
+    446c:	a413 122d      	macw %a5l,%d1l,<<,%a3@&,%d2,%acc1
+    4470:	a493 123d      	macw %a5l,%d1l,<<,%a3@&,%d2,%acc2
+    4474:	ae53 122d      	macw %a5l,%d1l,<<,%a3@&,%sp,%acc1
+    4478:	aed3 123d      	macw %a5l,%d1l,<<,%a3@&,%sp,%acc2
+    447c:	a21a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d1,%acc1
+    4480:	a29a 121d      	macw %a5l,%d1l,<<,%a2@\+,%d1,%acc2
+    4484:	a65a 120d      	macw %a5l,%d1l,<<,%a2@\+,%a3,%acc1
+    4488:	a6da 121d      	macw %a5l,%d1l,<<,%a2@\+,%a3,%acc2
+    448c:	a41a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d2,%acc1
+    4490:	a49a 121d      	macw %a5l,%d1l,<<,%a2@\+,%d2,%acc2
+    4494:	ae5a 120d      	macw %a5l,%d1l,<<,%a2@\+,%sp,%acc1
+    4498:	aeda 121d      	macw %a5l,%d1l,<<,%a2@\+,%sp,%acc2
+    449c:	a21a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d1,%acc1
+    44a0:	a29a 123d      	macw %a5l,%d1l,<<,%a2@\+&,%d1,%acc2
+    44a4:	a65a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%a3,%acc1
+    44a8:	a6da 123d      	macw %a5l,%d1l,<<,%a2@\+&,%a3,%acc2
+    44ac:	a41a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d2,%acc1
+    44b0:	a49a 123d      	macw %a5l,%d1l,<<,%a2@\+&,%d2,%acc2
+    44b4:	ae5a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%sp,%acc1
+    44b8:	aeda 123d      	macw %a5l,%d1l,<<,%a2@\+&,%sp,%acc2
+    44bc:	a22e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1,%acc1
+    44c2:	a2ae 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1,%acc2
+    44c8:	a66e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3,%acc1
+    44ce:	a6ee 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3,%acc2
+    44d4:	a42e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2,%acc1
+    44da:	a4ae 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2,%acc2
+    44e0:	ae6e 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp,%acc1
+    44e6:	aeee 121d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp,%acc2
+    44ec:	a22e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    44f2:	a2ae 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    44f8:	a66e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    44fe:	a6ee 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    4504:	a42e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    450a:	a4ae 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    4510:	ae6e 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    4516:	aeee 123d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    451c:	a221 120d      	macw %a5l,%d1l,<<,%a1@-,%d1,%acc1
+    4520:	a2a1 121d      	macw %a5l,%d1l,<<,%a1@-,%d1,%acc2
+    4524:	a661 120d      	macw %a5l,%d1l,<<,%a1@-,%a3,%acc1
+    4528:	a6e1 121d      	macw %a5l,%d1l,<<,%a1@-,%a3,%acc2
+    452c:	a421 120d      	macw %a5l,%d1l,<<,%a1@-,%d2,%acc1
+    4530:	a4a1 121d      	macw %a5l,%d1l,<<,%a1@-,%d2,%acc2
+    4534:	ae61 120d      	macw %a5l,%d1l,<<,%a1@-,%sp,%acc1
+    4538:	aee1 121d      	macw %a5l,%d1l,<<,%a1@-,%sp,%acc2
+    453c:	a221 122d      	macw %a5l,%d1l,<<,%a1@-&,%d1,%acc1
+    4540:	a2a1 123d      	macw %a5l,%d1l,<<,%a1@-&,%d1,%acc2
+    4544:	a661 122d      	macw %a5l,%d1l,<<,%a1@-&,%a3,%acc1
+    4548:	a6e1 123d      	macw %a5l,%d1l,<<,%a1@-&,%a3,%acc2
+    454c:	a421 122d      	macw %a5l,%d1l,<<,%a1@-&,%d2,%acc1
+    4550:	a4a1 123d      	macw %a5l,%d1l,<<,%a1@-&,%d2,%acc2
+    4554:	ae61 122d      	macw %a5l,%d1l,<<,%a1@-&,%sp,%acc1
+    4558:	aee1 123d      	macw %a5l,%d1l,<<,%a1@-&,%sp,%acc2
+    455c:	a213 160d      	macw %a5l,%d1l,>>,%a3@,%d1,%acc1
+    4560:	a293 161d      	macw %a5l,%d1l,>>,%a3@,%d1,%acc2
+    4564:	a653 160d      	macw %a5l,%d1l,>>,%a3@,%a3,%acc1
+    4568:	a6d3 161d      	macw %a5l,%d1l,>>,%a3@,%a3,%acc2
+    456c:	a413 160d      	macw %a5l,%d1l,>>,%a3@,%d2,%acc1
+    4570:	a493 161d      	macw %a5l,%d1l,>>,%a3@,%d2,%acc2
+    4574:	ae53 160d      	macw %a5l,%d1l,>>,%a3@,%sp,%acc1
+    4578:	aed3 161d      	macw %a5l,%d1l,>>,%a3@,%sp,%acc2
+    457c:	a213 162d      	macw %a5l,%d1l,>>,%a3@&,%d1,%acc1
+    4580:	a293 163d      	macw %a5l,%d1l,>>,%a3@&,%d1,%acc2
+    4584:	a653 162d      	macw %a5l,%d1l,>>,%a3@&,%a3,%acc1
+    4588:	a6d3 163d      	macw %a5l,%d1l,>>,%a3@&,%a3,%acc2
+    458c:	a413 162d      	macw %a5l,%d1l,>>,%a3@&,%d2,%acc1
+    4590:	a493 163d      	macw %a5l,%d1l,>>,%a3@&,%d2,%acc2
+    4594:	ae53 162d      	macw %a5l,%d1l,>>,%a3@&,%sp,%acc1
+    4598:	aed3 163d      	macw %a5l,%d1l,>>,%a3@&,%sp,%acc2
+    459c:	a21a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d1,%acc1
+    45a0:	a29a 161d      	macw %a5l,%d1l,>>,%a2@\+,%d1,%acc2
+    45a4:	a65a 160d      	macw %a5l,%d1l,>>,%a2@\+,%a3,%acc1
+    45a8:	a6da 161d      	macw %a5l,%d1l,>>,%a2@\+,%a3,%acc2
+    45ac:	a41a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d2,%acc1
+    45b0:	a49a 161d      	macw %a5l,%d1l,>>,%a2@\+,%d2,%acc2
+    45b4:	ae5a 160d      	macw %a5l,%d1l,>>,%a2@\+,%sp,%acc1
+    45b8:	aeda 161d      	macw %a5l,%d1l,>>,%a2@\+,%sp,%acc2
+    45bc:	a21a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d1,%acc1
+    45c0:	a29a 163d      	macw %a5l,%d1l,>>,%a2@\+&,%d1,%acc2
+    45c4:	a65a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%a3,%acc1
+    45c8:	a6da 163d      	macw %a5l,%d1l,>>,%a2@\+&,%a3,%acc2
+    45cc:	a41a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d2,%acc1
+    45d0:	a49a 163d      	macw %a5l,%d1l,>>,%a2@\+&,%d2,%acc2
+    45d4:	ae5a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%sp,%acc1
+    45d8:	aeda 163d      	macw %a5l,%d1l,>>,%a2@\+&,%sp,%acc2
+    45dc:	a22e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1,%acc1
+    45e2:	a2ae 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1,%acc2
+    45e8:	a66e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3,%acc1
+    45ee:	a6ee 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3,%acc2
+    45f4:	a42e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2,%acc1
+    45fa:	a4ae 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2,%acc2
+    4600:	ae6e 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp,%acc1
+    4606:	aeee 161d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp,%acc2
+    460c:	a22e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    4612:	a2ae 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    4618:	a66e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    461e:	a6ee 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    4624:	a42e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    462a:	a4ae 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    4630:	ae6e 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    4636:	aeee 163d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    463c:	a221 160d      	macw %a5l,%d1l,>>,%a1@-,%d1,%acc1
+    4640:	a2a1 161d      	macw %a5l,%d1l,>>,%a1@-,%d1,%acc2
+    4644:	a661 160d      	macw %a5l,%d1l,>>,%a1@-,%a3,%acc1
+    4648:	a6e1 161d      	macw %a5l,%d1l,>>,%a1@-,%a3,%acc2
+    464c:	a421 160d      	macw %a5l,%d1l,>>,%a1@-,%d2,%acc1
+    4650:	a4a1 161d      	macw %a5l,%d1l,>>,%a1@-,%d2,%acc2
+    4654:	ae61 160d      	macw %a5l,%d1l,>>,%a1@-,%sp,%acc1
+    4658:	aee1 161d      	macw %a5l,%d1l,>>,%a1@-,%sp,%acc2
+    465c:	a221 162d      	macw %a5l,%d1l,>>,%a1@-&,%d1,%acc1
+    4660:	a2a1 163d      	macw %a5l,%d1l,>>,%a1@-&,%d1,%acc2
+    4664:	a661 162d      	macw %a5l,%d1l,>>,%a1@-&,%a3,%acc1
+    4668:	a6e1 163d      	macw %a5l,%d1l,>>,%a1@-&,%a3,%acc2
+    466c:	a421 162d      	macw %a5l,%d1l,>>,%a1@-&,%d2,%acc1
+    4670:	a4a1 163d      	macw %a5l,%d1l,>>,%a1@-&,%d2,%acc2
+    4674:	ae61 162d      	macw %a5l,%d1l,>>,%a1@-&,%sp,%acc1
+    4678:	aee1 163d      	macw %a5l,%d1l,>>,%a1@-&,%sp,%acc2
+    467c:	a213 a0c6      	macw %d6u,%a2u,%a3@,%d1,%acc1
+    4680:	a293 a0d6      	macw %d6u,%a2u,%a3@,%d1,%acc2
+    4684:	a653 a0c6      	macw %d6u,%a2u,%a3@,%a3,%acc1
+    4688:	a6d3 a0d6      	macw %d6u,%a2u,%a3@,%a3,%acc2
+    468c:	a413 a0c6      	macw %d6u,%a2u,%a3@,%d2,%acc1
+    4690:	a493 a0d6      	macw %d6u,%a2u,%a3@,%d2,%acc2
+    4694:	ae53 a0c6      	macw %d6u,%a2u,%a3@,%sp,%acc1
+    4698:	aed3 a0d6      	macw %d6u,%a2u,%a3@,%sp,%acc2
+    469c:	a213 a0e6      	macw %d6u,%a2u,%a3@&,%d1,%acc1
+    46a0:	a293 a0f6      	macw %d6u,%a2u,%a3@&,%d1,%acc2
+    46a4:	a653 a0e6      	macw %d6u,%a2u,%a3@&,%a3,%acc1
+    46a8:	a6d3 a0f6      	macw %d6u,%a2u,%a3@&,%a3,%acc2
+    46ac:	a413 a0e6      	macw %d6u,%a2u,%a3@&,%d2,%acc1
+    46b0:	a493 a0f6      	macw %d6u,%a2u,%a3@&,%d2,%acc2
+    46b4:	ae53 a0e6      	macw %d6u,%a2u,%a3@&,%sp,%acc1
+    46b8:	aed3 a0f6      	macw %d6u,%a2u,%a3@&,%sp,%acc2
+    46bc:	a21a a0c6      	macw %d6u,%a2u,%a2@\+,%d1,%acc1
+    46c0:	a29a a0d6      	macw %d6u,%a2u,%a2@\+,%d1,%acc2
+    46c4:	a65a a0c6      	macw %d6u,%a2u,%a2@\+,%a3,%acc1
+    46c8:	a6da a0d6      	macw %d6u,%a2u,%a2@\+,%a3,%acc2
+    46cc:	a41a a0c6      	macw %d6u,%a2u,%a2@\+,%d2,%acc1
+    46d0:	a49a a0d6      	macw %d6u,%a2u,%a2@\+,%d2,%acc2
+    46d4:	ae5a a0c6      	macw %d6u,%a2u,%a2@\+,%sp,%acc1
+    46d8:	aeda a0d6      	macw %d6u,%a2u,%a2@\+,%sp,%acc2
+    46dc:	a21a a0e6      	macw %d6u,%a2u,%a2@\+&,%d1,%acc1
+    46e0:	a29a a0f6      	macw %d6u,%a2u,%a2@\+&,%d1,%acc2
+    46e4:	a65a a0e6      	macw %d6u,%a2u,%a2@\+&,%a3,%acc1
+    46e8:	a6da a0f6      	macw %d6u,%a2u,%a2@\+&,%a3,%acc2
+    46ec:	a41a a0e6      	macw %d6u,%a2u,%a2@\+&,%d2,%acc1
+    46f0:	a49a a0f6      	macw %d6u,%a2u,%a2@\+&,%d2,%acc2
+    46f4:	ae5a a0e6      	macw %d6u,%a2u,%a2@\+&,%sp,%acc1
+    46f8:	aeda a0f6      	macw %d6u,%a2u,%a2@\+&,%sp,%acc2
+    46fc:	a22e a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%d1,%acc1
+    4702:	a2ae a0d6 000a 	macw %d6u,%a2u,%fp@\(10\),%d1,%acc2
+    4708:	a66e a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%a3,%acc1
+    470e:	a6ee a0d6 000a 	macw %d6u,%a2u,%fp@\(10\),%a3,%acc2
+    4714:	a42e a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%d2,%acc1
+    471a:	a4ae a0d6 000a 	macw %d6u,%a2u,%fp@\(10\),%d2,%acc2
+    4720:	ae6e a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%sp,%acc1
+    4726:	aeee a0d6 000a 	macw %d6u,%a2u,%fp@\(10\),%sp,%acc2
+    472c:	a22e a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d1,%acc1
+    4732:	a2ae a0f6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d1,%acc2
+    4738:	a66e a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%a3,%acc1
+    473e:	a6ee a0f6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%a3,%acc2
+    4744:	a42e a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d2,%acc1
+    474a:	a4ae a0f6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d2,%acc2
+    4750:	ae6e a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%sp,%acc1
+    4756:	aeee a0f6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%sp,%acc2
+    475c:	a221 a0c6      	macw %d6u,%a2u,%a1@-,%d1,%acc1
+    4760:	a2a1 a0d6      	macw %d6u,%a2u,%a1@-,%d1,%acc2
+    4764:	a661 a0c6      	macw %d6u,%a2u,%a1@-,%a3,%acc1
+    4768:	a6e1 a0d6      	macw %d6u,%a2u,%a1@-,%a3,%acc2
+    476c:	a421 a0c6      	macw %d6u,%a2u,%a1@-,%d2,%acc1
+    4770:	a4a1 a0d6      	macw %d6u,%a2u,%a1@-,%d2,%acc2
+    4774:	ae61 a0c6      	macw %d6u,%a2u,%a1@-,%sp,%acc1
+    4778:	aee1 a0d6      	macw %d6u,%a2u,%a1@-,%sp,%acc2
+    477c:	a221 a0e6      	macw %d6u,%a2u,%a1@-&,%d1,%acc1
+    4780:	a2a1 a0f6      	macw %d6u,%a2u,%a1@-&,%d1,%acc2
+    4784:	a661 a0e6      	macw %d6u,%a2u,%a1@-&,%a3,%acc1
+    4788:	a6e1 a0f6      	macw %d6u,%a2u,%a1@-&,%a3,%acc2
+    478c:	a421 a0e6      	macw %d6u,%a2u,%a1@-&,%d2,%acc1
+    4790:	a4a1 a0f6      	macw %d6u,%a2u,%a1@-&,%d2,%acc2
+    4794:	ae61 a0e6      	macw %d6u,%a2u,%a1@-&,%sp,%acc1
+    4798:	aee1 a0f6      	macw %d6u,%a2u,%a1@-&,%sp,%acc2
+    479c:	a213 a2c6      	macw %d6u,%a2u,<<,%a3@,%d1,%acc1
+    47a0:	a293 a2d6      	macw %d6u,%a2u,<<,%a3@,%d1,%acc2
+    47a4:	a653 a2c6      	macw %d6u,%a2u,<<,%a3@,%a3,%acc1
+    47a8:	a6d3 a2d6      	macw %d6u,%a2u,<<,%a3@,%a3,%acc2
+    47ac:	a413 a2c6      	macw %d6u,%a2u,<<,%a3@,%d2,%acc1
+    47b0:	a493 a2d6      	macw %d6u,%a2u,<<,%a3@,%d2,%acc2
+    47b4:	ae53 a2c6      	macw %d6u,%a2u,<<,%a3@,%sp,%acc1
+    47b8:	aed3 a2d6      	macw %d6u,%a2u,<<,%a3@,%sp,%acc2
+    47bc:	a213 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d1,%acc1
+    47c0:	a293 a2f6      	macw %d6u,%a2u,<<,%a3@&,%d1,%acc2
+    47c4:	a653 a2e6      	macw %d6u,%a2u,<<,%a3@&,%a3,%acc1
+    47c8:	a6d3 a2f6      	macw %d6u,%a2u,<<,%a3@&,%a3,%acc2
+    47cc:	a413 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d2,%acc1
+    47d0:	a493 a2f6      	macw %d6u,%a2u,<<,%a3@&,%d2,%acc2
+    47d4:	ae53 a2e6      	macw %d6u,%a2u,<<,%a3@&,%sp,%acc1
+    47d8:	aed3 a2f6      	macw %d6u,%a2u,<<,%a3@&,%sp,%acc2
+    47dc:	a21a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d1,%acc1
+    47e0:	a29a a2d6      	macw %d6u,%a2u,<<,%a2@\+,%d1,%acc2
+    47e4:	a65a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%a3,%acc1
+    47e8:	a6da a2d6      	macw %d6u,%a2u,<<,%a2@\+,%a3,%acc2
+    47ec:	a41a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d2,%acc1
+    47f0:	a49a a2d6      	macw %d6u,%a2u,<<,%a2@\+,%d2,%acc2
+    47f4:	ae5a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%sp,%acc1
+    47f8:	aeda a2d6      	macw %d6u,%a2u,<<,%a2@\+,%sp,%acc2
+    47fc:	a21a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d1,%acc1
+    4800:	a29a a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%d1,%acc2
+    4804:	a65a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%a3,%acc1
+    4808:	a6da a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%a3,%acc2
+    480c:	a41a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d2,%acc1
+    4810:	a49a a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%d2,%acc2
+    4814:	ae5a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%sp,%acc1
+    4818:	aeda a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%sp,%acc2
+    481c:	a22e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1,%acc1
+    4822:	a2ae a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1,%acc2
+    4828:	a66e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3,%acc1
+    482e:	a6ee a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3,%acc2
+    4834:	a42e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2,%acc1
+    483a:	a4ae a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2,%acc2
+    4840:	ae6e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp,%acc1
+    4846:	aeee a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp,%acc2
+    484c:	a22e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    4852:	a2ae a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    4858:	a66e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    485e:	a6ee a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    4864:	a42e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    486a:	a4ae a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    4870:	ae6e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    4876:	aeee a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    487c:	a221 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d1,%acc1
+    4880:	a2a1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%d1,%acc2
+    4884:	a661 a2c6      	macw %d6u,%a2u,<<,%a1@-,%a3,%acc1
+    4888:	a6e1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%a3,%acc2
+    488c:	a421 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d2,%acc1
+    4890:	a4a1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%d2,%acc2
+    4894:	ae61 a2c6      	macw %d6u,%a2u,<<,%a1@-,%sp,%acc1
+    4898:	aee1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%sp,%acc2
+    489c:	a221 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d1,%acc1
+    48a0:	a2a1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%d1,%acc2
+    48a4:	a661 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%a3,%acc1
+    48a8:	a6e1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%a3,%acc2
+    48ac:	a421 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d2,%acc1
+    48b0:	a4a1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%d2,%acc2
+    48b4:	ae61 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%sp,%acc1
+    48b8:	aee1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%sp,%acc2
+    48bc:	a213 a6c6      	macw %d6u,%a2u,>>,%a3@,%d1,%acc1
+    48c0:	a293 a6d6      	macw %d6u,%a2u,>>,%a3@,%d1,%acc2
+    48c4:	a653 a6c6      	macw %d6u,%a2u,>>,%a3@,%a3,%acc1
+    48c8:	a6d3 a6d6      	macw %d6u,%a2u,>>,%a3@,%a3,%acc2
+    48cc:	a413 a6c6      	macw %d6u,%a2u,>>,%a3@,%d2,%acc1
+    48d0:	a493 a6d6      	macw %d6u,%a2u,>>,%a3@,%d2,%acc2
+    48d4:	ae53 a6c6      	macw %d6u,%a2u,>>,%a3@,%sp,%acc1
+    48d8:	aed3 a6d6      	macw %d6u,%a2u,>>,%a3@,%sp,%acc2
+    48dc:	a213 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d1,%acc1
+    48e0:	a293 a6f6      	macw %d6u,%a2u,>>,%a3@&,%d1,%acc2
+    48e4:	a653 a6e6      	macw %d6u,%a2u,>>,%a3@&,%a3,%acc1
+    48e8:	a6d3 a6f6      	macw %d6u,%a2u,>>,%a3@&,%a3,%acc2
+    48ec:	a413 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d2,%acc1
+    48f0:	a493 a6f6      	macw %d6u,%a2u,>>,%a3@&,%d2,%acc2
+    48f4:	ae53 a6e6      	macw %d6u,%a2u,>>,%a3@&,%sp,%acc1
+    48f8:	aed3 a6f6      	macw %d6u,%a2u,>>,%a3@&,%sp,%acc2
+    48fc:	a21a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d1,%acc1
+    4900:	a29a a6d6      	macw %d6u,%a2u,>>,%a2@\+,%d1,%acc2
+    4904:	a65a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%a3,%acc1
+    4908:	a6da a6d6      	macw %d6u,%a2u,>>,%a2@\+,%a3,%acc2
+    490c:	a41a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d2,%acc1
+    4910:	a49a a6d6      	macw %d6u,%a2u,>>,%a2@\+,%d2,%acc2
+    4914:	ae5a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%sp,%acc1
+    4918:	aeda a6d6      	macw %d6u,%a2u,>>,%a2@\+,%sp,%acc2
+    491c:	a21a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d1,%acc1
+    4920:	a29a a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%d1,%acc2
+    4924:	a65a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%a3,%acc1
+    4928:	a6da a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%a3,%acc2
+    492c:	a41a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d2,%acc1
+    4930:	a49a a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%d2,%acc2
+    4934:	ae5a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%sp,%acc1
+    4938:	aeda a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%sp,%acc2
+    493c:	a22e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1,%acc1
+    4942:	a2ae a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1,%acc2
+    4948:	a66e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3,%acc1
+    494e:	a6ee a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3,%acc2
+    4954:	a42e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2,%acc1
+    495a:	a4ae a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2,%acc2
+    4960:	ae6e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp,%acc1
+    4966:	aeee a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp,%acc2
+    496c:	a22e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    4972:	a2ae a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    4978:	a66e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    497e:	a6ee a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    4984:	a42e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    498a:	a4ae a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    4990:	ae6e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    4996:	aeee a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    499c:	a221 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d1,%acc1
+    49a0:	a2a1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%d1,%acc2
+    49a4:	a661 a6c6      	macw %d6u,%a2u,>>,%a1@-,%a3,%acc1
+    49a8:	a6e1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%a3,%acc2
+    49ac:	a421 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d2,%acc1
+    49b0:	a4a1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%d2,%acc2
+    49b4:	ae61 a6c6      	macw %d6u,%a2u,>>,%a1@-,%sp,%acc1
+    49b8:	aee1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%sp,%acc2
+    49bc:	a221 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d1,%acc1
+    49c0:	a2a1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%d1,%acc2
+    49c4:	a661 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%a3,%acc1
+    49c8:	a6e1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%a3,%acc2
+    49cc:	a421 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d2,%acc1
+    49d0:	a4a1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%d2,%acc2
+    49d4:	ae61 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%sp,%acc1
+    49d8:	aee1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%sp,%acc2
+    49dc:	a213 a2c6      	macw %d6u,%a2u,<<,%a3@,%d1,%acc1
+    49e0:	a293 a2d6      	macw %d6u,%a2u,<<,%a3@,%d1,%acc2
+    49e4:	a653 a2c6      	macw %d6u,%a2u,<<,%a3@,%a3,%acc1
+    49e8:	a6d3 a2d6      	macw %d6u,%a2u,<<,%a3@,%a3,%acc2
+    49ec:	a413 a2c6      	macw %d6u,%a2u,<<,%a3@,%d2,%acc1
+    49f0:	a493 a2d6      	macw %d6u,%a2u,<<,%a3@,%d2,%acc2
+    49f4:	ae53 a2c6      	macw %d6u,%a2u,<<,%a3@,%sp,%acc1
+    49f8:	aed3 a2d6      	macw %d6u,%a2u,<<,%a3@,%sp,%acc2
+    49fc:	a213 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d1,%acc1
+    4a00:	a293 a2f6      	macw %d6u,%a2u,<<,%a3@&,%d1,%acc2
+    4a04:	a653 a2e6      	macw %d6u,%a2u,<<,%a3@&,%a3,%acc1
+    4a08:	a6d3 a2f6      	macw %d6u,%a2u,<<,%a3@&,%a3,%acc2
+    4a0c:	a413 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d2,%acc1
+    4a10:	a493 a2f6      	macw %d6u,%a2u,<<,%a3@&,%d2,%acc2
+    4a14:	ae53 a2e6      	macw %d6u,%a2u,<<,%a3@&,%sp,%acc1
+    4a18:	aed3 a2f6      	macw %d6u,%a2u,<<,%a3@&,%sp,%acc2
+    4a1c:	a21a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d1,%acc1
+    4a20:	a29a a2d6      	macw %d6u,%a2u,<<,%a2@\+,%d1,%acc2
+    4a24:	a65a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%a3,%acc1
+    4a28:	a6da a2d6      	macw %d6u,%a2u,<<,%a2@\+,%a3,%acc2
+    4a2c:	a41a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d2,%acc1
+    4a30:	a49a a2d6      	macw %d6u,%a2u,<<,%a2@\+,%d2,%acc2
+    4a34:	ae5a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%sp,%acc1
+    4a38:	aeda a2d6      	macw %d6u,%a2u,<<,%a2@\+,%sp,%acc2
+    4a3c:	a21a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d1,%acc1
+    4a40:	a29a a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%d1,%acc2
+    4a44:	a65a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%a3,%acc1
+    4a48:	a6da a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%a3,%acc2
+    4a4c:	a41a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d2,%acc1
+    4a50:	a49a a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%d2,%acc2
+    4a54:	ae5a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%sp,%acc1
+    4a58:	aeda a2f6      	macw %d6u,%a2u,<<,%a2@\+&,%sp,%acc2
+    4a5c:	a22e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1,%acc1
+    4a62:	a2ae a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1,%acc2
+    4a68:	a66e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3,%acc1
+    4a6e:	a6ee a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3,%acc2
+    4a74:	a42e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2,%acc1
+    4a7a:	a4ae a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2,%acc2
+    4a80:	ae6e a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp,%acc1
+    4a86:	aeee a2d6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp,%acc2
+    4a8c:	a22e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1,%acc1
+    4a92:	a2ae a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1,%acc2
+    4a98:	a66e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3,%acc1
+    4a9e:	a6ee a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3,%acc2
+    4aa4:	a42e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2,%acc1
+    4aaa:	a4ae a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2,%acc2
+    4ab0:	ae6e a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp,%acc1
+    4ab6:	aeee a2f6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp,%acc2
+    4abc:	a221 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d1,%acc1
+    4ac0:	a2a1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%d1,%acc2
+    4ac4:	a661 a2c6      	macw %d6u,%a2u,<<,%a1@-,%a3,%acc1
+    4ac8:	a6e1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%a3,%acc2
+    4acc:	a421 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d2,%acc1
+    4ad0:	a4a1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%d2,%acc2
+    4ad4:	ae61 a2c6      	macw %d6u,%a2u,<<,%a1@-,%sp,%acc1
+    4ad8:	aee1 a2d6      	macw %d6u,%a2u,<<,%a1@-,%sp,%acc2
+    4adc:	a221 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d1,%acc1
+    4ae0:	a2a1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%d1,%acc2
+    4ae4:	a661 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%a3,%acc1
+    4ae8:	a6e1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%a3,%acc2
+    4aec:	a421 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d2,%acc1
+    4af0:	a4a1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%d2,%acc2
+    4af4:	ae61 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%sp,%acc1
+    4af8:	aee1 a2f6      	macw %d6u,%a2u,<<,%a1@-&,%sp,%acc2
+    4afc:	a213 a6c6      	macw %d6u,%a2u,>>,%a3@,%d1,%acc1
+    4b00:	a293 a6d6      	macw %d6u,%a2u,>>,%a3@,%d1,%acc2
+    4b04:	a653 a6c6      	macw %d6u,%a2u,>>,%a3@,%a3,%acc1
+    4b08:	a6d3 a6d6      	macw %d6u,%a2u,>>,%a3@,%a3,%acc2
+    4b0c:	a413 a6c6      	macw %d6u,%a2u,>>,%a3@,%d2,%acc1
+    4b10:	a493 a6d6      	macw %d6u,%a2u,>>,%a3@,%d2,%acc2
+    4b14:	ae53 a6c6      	macw %d6u,%a2u,>>,%a3@,%sp,%acc1
+    4b18:	aed3 a6d6      	macw %d6u,%a2u,>>,%a3@,%sp,%acc2
+    4b1c:	a213 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d1,%acc1
+    4b20:	a293 a6f6      	macw %d6u,%a2u,>>,%a3@&,%d1,%acc2
+    4b24:	a653 a6e6      	macw %d6u,%a2u,>>,%a3@&,%a3,%acc1
+    4b28:	a6d3 a6f6      	macw %d6u,%a2u,>>,%a3@&,%a3,%acc2
+    4b2c:	a413 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d2,%acc1
+    4b30:	a493 a6f6      	macw %d6u,%a2u,>>,%a3@&,%d2,%acc2
+    4b34:	ae53 a6e6      	macw %d6u,%a2u,>>,%a3@&,%sp,%acc1
+    4b38:	aed3 a6f6      	macw %d6u,%a2u,>>,%a3@&,%sp,%acc2
+    4b3c:	a21a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d1,%acc1
+    4b40:	a29a a6d6      	macw %d6u,%a2u,>>,%a2@\+,%d1,%acc2
+    4b44:	a65a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%a3,%acc1
+    4b48:	a6da a6d6      	macw %d6u,%a2u,>>,%a2@\+,%a3,%acc2
+    4b4c:	a41a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d2,%acc1
+    4b50:	a49a a6d6      	macw %d6u,%a2u,>>,%a2@\+,%d2,%acc2
+    4b54:	ae5a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%sp,%acc1
+    4b58:	aeda a6d6      	macw %d6u,%a2u,>>,%a2@\+,%sp,%acc2
+    4b5c:	a21a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d1,%acc1
+    4b60:	a29a a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%d1,%acc2
+    4b64:	a65a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%a3,%acc1
+    4b68:	a6da a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%a3,%acc2
+    4b6c:	a41a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d2,%acc1
+    4b70:	a49a a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%d2,%acc2
+    4b74:	ae5a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%sp,%acc1
+    4b78:	aeda a6f6      	macw %d6u,%a2u,>>,%a2@\+&,%sp,%acc2
+    4b7c:	a22e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1,%acc1
+    4b82:	a2ae a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1,%acc2
+    4b88:	a66e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3,%acc1
+    4b8e:	a6ee a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3,%acc2
+    4b94:	a42e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2,%acc1
+    4b9a:	a4ae a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2,%acc2
+    4ba0:	ae6e a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp,%acc1
+    4ba6:	aeee a6d6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp,%acc2
+    4bac:	a22e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1,%acc1
+    4bb2:	a2ae a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1,%acc2
+    4bb8:	a66e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3,%acc1
+    4bbe:	a6ee a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3,%acc2
+    4bc4:	a42e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2,%acc1
+    4bca:	a4ae a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2,%acc2
+    4bd0:	ae6e a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp,%acc1
+    4bd6:	aeee a6f6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp,%acc2
+    4bdc:	a221 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d1,%acc1
+    4be0:	a2a1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%d1,%acc2
+    4be4:	a661 a6c6      	macw %d6u,%a2u,>>,%a1@-,%a3,%acc1
+    4be8:	a6e1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%a3,%acc2
+    4bec:	a421 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d2,%acc1
+    4bf0:	a4a1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%d2,%acc2
+    4bf4:	ae61 a6c6      	macw %d6u,%a2u,>>,%a1@-,%sp,%acc1
+    4bf8:	aee1 a6d6      	macw %d6u,%a2u,>>,%a1@-,%sp,%acc2
+    4bfc:	a221 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d1,%acc1
+    4c00:	a2a1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%d1,%acc2
+    4c04:	a661 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%a3,%acc1
+    4c08:	a6e1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%a3,%acc2
+    4c0c:	a421 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d2,%acc1
+    4c10:	a4a1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%d2,%acc2
+    4c14:	ae61 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%sp,%acc1
+    4c18:	aee1 a6f6      	macw %d6u,%a2u,>>,%a1@-&,%sp,%acc2
+    4c1c:	a213 3046      	macw %d6u,%d3l,%a3@,%d1,%acc1
+    4c20:	a293 3056      	macw %d6u,%d3l,%a3@,%d1,%acc2
+    4c24:	a653 3046      	macw %d6u,%d3l,%a3@,%a3,%acc1
+    4c28:	a6d3 3056      	macw %d6u,%d3l,%a3@,%a3,%acc2
+    4c2c:	a413 3046      	macw %d6u,%d3l,%a3@,%d2,%acc1
+    4c30:	a493 3056      	macw %d6u,%d3l,%a3@,%d2,%acc2
+    4c34:	ae53 3046      	macw %d6u,%d3l,%a3@,%sp,%acc1
+    4c38:	aed3 3056      	macw %d6u,%d3l,%a3@,%sp,%acc2
+    4c3c:	a213 3066      	macw %d6u,%d3l,%a3@&,%d1,%acc1
+    4c40:	a293 3076      	macw %d6u,%d3l,%a3@&,%d1,%acc2
+    4c44:	a653 3066      	macw %d6u,%d3l,%a3@&,%a3,%acc1
+    4c48:	a6d3 3076      	macw %d6u,%d3l,%a3@&,%a3,%acc2
+    4c4c:	a413 3066      	macw %d6u,%d3l,%a3@&,%d2,%acc1
+    4c50:	a493 3076      	macw %d6u,%d3l,%a3@&,%d2,%acc2
+    4c54:	ae53 3066      	macw %d6u,%d3l,%a3@&,%sp,%acc1
+    4c58:	aed3 3076      	macw %d6u,%d3l,%a3@&,%sp,%acc2
+    4c5c:	a21a 3046      	macw %d6u,%d3l,%a2@\+,%d1,%acc1
+    4c60:	a29a 3056      	macw %d6u,%d3l,%a2@\+,%d1,%acc2
+    4c64:	a65a 3046      	macw %d6u,%d3l,%a2@\+,%a3,%acc1
+    4c68:	a6da 3056      	macw %d6u,%d3l,%a2@\+,%a3,%acc2
+    4c6c:	a41a 3046      	macw %d6u,%d3l,%a2@\+,%d2,%acc1
+    4c70:	a49a 3056      	macw %d6u,%d3l,%a2@\+,%d2,%acc2
+    4c74:	ae5a 3046      	macw %d6u,%d3l,%a2@\+,%sp,%acc1
+    4c78:	aeda 3056      	macw %d6u,%d3l,%a2@\+,%sp,%acc2
+    4c7c:	a21a 3066      	macw %d6u,%d3l,%a2@\+&,%d1,%acc1
+    4c80:	a29a 3076      	macw %d6u,%d3l,%a2@\+&,%d1,%acc2
+    4c84:	a65a 3066      	macw %d6u,%d3l,%a2@\+&,%a3,%acc1
+    4c88:	a6da 3076      	macw %d6u,%d3l,%a2@\+&,%a3,%acc2
+    4c8c:	a41a 3066      	macw %d6u,%d3l,%a2@\+&,%d2,%acc1
+    4c90:	a49a 3076      	macw %d6u,%d3l,%a2@\+&,%d2,%acc2
+    4c94:	ae5a 3066      	macw %d6u,%d3l,%a2@\+&,%sp,%acc1
+    4c98:	aeda 3076      	macw %d6u,%d3l,%a2@\+&,%sp,%acc2
+    4c9c:	a22e 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%d1,%acc1
+    4ca2:	a2ae 3056 000a 	macw %d6u,%d3l,%fp@\(10\),%d1,%acc2
+    4ca8:	a66e 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%a3,%acc1
+    4cae:	a6ee 3056 000a 	macw %d6u,%d3l,%fp@\(10\),%a3,%acc2
+    4cb4:	a42e 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%d2,%acc1
+    4cba:	a4ae 3056 000a 	macw %d6u,%d3l,%fp@\(10\),%d2,%acc2
+    4cc0:	ae6e 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%sp,%acc1
+    4cc6:	aeee 3056 000a 	macw %d6u,%d3l,%fp@\(10\),%sp,%acc2
+    4ccc:	a22e 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d1,%acc1
+    4cd2:	a2ae 3076 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d1,%acc2
+    4cd8:	a66e 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%a3,%acc1
+    4cde:	a6ee 3076 000a 	macw %d6u,%d3l,%fp@\(10\)&,%a3,%acc2
+    4ce4:	a42e 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d2,%acc1
+    4cea:	a4ae 3076 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d2,%acc2
+    4cf0:	ae6e 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%sp,%acc1
+    4cf6:	aeee 3076 000a 	macw %d6u,%d3l,%fp@\(10\)&,%sp,%acc2
+    4cfc:	a221 3046      	macw %d6u,%d3l,%a1@-,%d1,%acc1
+    4d00:	a2a1 3056      	macw %d6u,%d3l,%a1@-,%d1,%acc2
+    4d04:	a661 3046      	macw %d6u,%d3l,%a1@-,%a3,%acc1
+    4d08:	a6e1 3056      	macw %d6u,%d3l,%a1@-,%a3,%acc2
+    4d0c:	a421 3046      	macw %d6u,%d3l,%a1@-,%d2,%acc1
+    4d10:	a4a1 3056      	macw %d6u,%d3l,%a1@-,%d2,%acc2
+    4d14:	ae61 3046      	macw %d6u,%d3l,%a1@-,%sp,%acc1
+    4d18:	aee1 3056      	macw %d6u,%d3l,%a1@-,%sp,%acc2
+    4d1c:	a221 3066      	macw %d6u,%d3l,%a1@-&,%d1,%acc1
+    4d20:	a2a1 3076      	macw %d6u,%d3l,%a1@-&,%d1,%acc2
+    4d24:	a661 3066      	macw %d6u,%d3l,%a1@-&,%a3,%acc1
+    4d28:	a6e1 3076      	macw %d6u,%d3l,%a1@-&,%a3,%acc2
+    4d2c:	a421 3066      	macw %d6u,%d3l,%a1@-&,%d2,%acc1
+    4d30:	a4a1 3076      	macw %d6u,%d3l,%a1@-&,%d2,%acc2
+    4d34:	ae61 3066      	macw %d6u,%d3l,%a1@-&,%sp,%acc1
+    4d38:	aee1 3076      	macw %d6u,%d3l,%a1@-&,%sp,%acc2
+    4d3c:	a213 3246      	macw %d6u,%d3l,<<,%a3@,%d1,%acc1
+    4d40:	a293 3256      	macw %d6u,%d3l,<<,%a3@,%d1,%acc2
+    4d44:	a653 3246      	macw %d6u,%d3l,<<,%a3@,%a3,%acc1
+    4d48:	a6d3 3256      	macw %d6u,%d3l,<<,%a3@,%a3,%acc2
+    4d4c:	a413 3246      	macw %d6u,%d3l,<<,%a3@,%d2,%acc1
+    4d50:	a493 3256      	macw %d6u,%d3l,<<,%a3@,%d2,%acc2
+    4d54:	ae53 3246      	macw %d6u,%d3l,<<,%a3@,%sp,%acc1
+    4d58:	aed3 3256      	macw %d6u,%d3l,<<,%a3@,%sp,%acc2
+    4d5c:	a213 3266      	macw %d6u,%d3l,<<,%a3@&,%d1,%acc1
+    4d60:	a293 3276      	macw %d6u,%d3l,<<,%a3@&,%d1,%acc2
+    4d64:	a653 3266      	macw %d6u,%d3l,<<,%a3@&,%a3,%acc1
+    4d68:	a6d3 3276      	macw %d6u,%d3l,<<,%a3@&,%a3,%acc2
+    4d6c:	a413 3266      	macw %d6u,%d3l,<<,%a3@&,%d2,%acc1
+    4d70:	a493 3276      	macw %d6u,%d3l,<<,%a3@&,%d2,%acc2
+    4d74:	ae53 3266      	macw %d6u,%d3l,<<,%a3@&,%sp,%acc1
+    4d78:	aed3 3276      	macw %d6u,%d3l,<<,%a3@&,%sp,%acc2
+    4d7c:	a21a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d1,%acc1
+    4d80:	a29a 3256      	macw %d6u,%d3l,<<,%a2@\+,%d1,%acc2
+    4d84:	a65a 3246      	macw %d6u,%d3l,<<,%a2@\+,%a3,%acc1
+    4d88:	a6da 3256      	macw %d6u,%d3l,<<,%a2@\+,%a3,%acc2
+    4d8c:	a41a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d2,%acc1
+    4d90:	a49a 3256      	macw %d6u,%d3l,<<,%a2@\+,%d2,%acc2
+    4d94:	ae5a 3246      	macw %d6u,%d3l,<<,%a2@\+,%sp,%acc1
+    4d98:	aeda 3256      	macw %d6u,%d3l,<<,%a2@\+,%sp,%acc2
+    4d9c:	a21a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d1,%acc1
+    4da0:	a29a 3276      	macw %d6u,%d3l,<<,%a2@\+&,%d1,%acc2
+    4da4:	a65a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%a3,%acc1
+    4da8:	a6da 3276      	macw %d6u,%d3l,<<,%a2@\+&,%a3,%acc2
+    4dac:	a41a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d2,%acc1
+    4db0:	a49a 3276      	macw %d6u,%d3l,<<,%a2@\+&,%d2,%acc2
+    4db4:	ae5a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%sp,%acc1
+    4db8:	aeda 3276      	macw %d6u,%d3l,<<,%a2@\+&,%sp,%acc2
+    4dbc:	a22e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1,%acc1
+    4dc2:	a2ae 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1,%acc2
+    4dc8:	a66e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3,%acc1
+    4dce:	a6ee 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3,%acc2
+    4dd4:	a42e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2,%acc1
+    4dda:	a4ae 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2,%acc2
+    4de0:	ae6e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp,%acc1
+    4de6:	aeee 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp,%acc2
+    4dec:	a22e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    4df2:	a2ae 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    4df8:	a66e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    4dfe:	a6ee 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    4e04:	a42e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    4e0a:	a4ae 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    4e10:	ae6e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    4e16:	aeee 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    4e1c:	a221 3246      	macw %d6u,%d3l,<<,%a1@-,%d1,%acc1
+    4e20:	a2a1 3256      	macw %d6u,%d3l,<<,%a1@-,%d1,%acc2
+    4e24:	a661 3246      	macw %d6u,%d3l,<<,%a1@-,%a3,%acc1
+    4e28:	a6e1 3256      	macw %d6u,%d3l,<<,%a1@-,%a3,%acc2
+    4e2c:	a421 3246      	macw %d6u,%d3l,<<,%a1@-,%d2,%acc1
+    4e30:	a4a1 3256      	macw %d6u,%d3l,<<,%a1@-,%d2,%acc2
+    4e34:	ae61 3246      	macw %d6u,%d3l,<<,%a1@-,%sp,%acc1
+    4e38:	aee1 3256      	macw %d6u,%d3l,<<,%a1@-,%sp,%acc2
+    4e3c:	a221 3266      	macw %d6u,%d3l,<<,%a1@-&,%d1,%acc1
+    4e40:	a2a1 3276      	macw %d6u,%d3l,<<,%a1@-&,%d1,%acc2
+    4e44:	a661 3266      	macw %d6u,%d3l,<<,%a1@-&,%a3,%acc1
+    4e48:	a6e1 3276      	macw %d6u,%d3l,<<,%a1@-&,%a3,%acc2
+    4e4c:	a421 3266      	macw %d6u,%d3l,<<,%a1@-&,%d2,%acc1
+    4e50:	a4a1 3276      	macw %d6u,%d3l,<<,%a1@-&,%d2,%acc2
+    4e54:	ae61 3266      	macw %d6u,%d3l,<<,%a1@-&,%sp,%acc1
+    4e58:	aee1 3276      	macw %d6u,%d3l,<<,%a1@-&,%sp,%acc2
+    4e5c:	a213 3646      	macw %d6u,%d3l,>>,%a3@,%d1,%acc1
+    4e60:	a293 3656      	macw %d6u,%d3l,>>,%a3@,%d1,%acc2
+    4e64:	a653 3646      	macw %d6u,%d3l,>>,%a3@,%a3,%acc1
+    4e68:	a6d3 3656      	macw %d6u,%d3l,>>,%a3@,%a3,%acc2
+    4e6c:	a413 3646      	macw %d6u,%d3l,>>,%a3@,%d2,%acc1
+    4e70:	a493 3656      	macw %d6u,%d3l,>>,%a3@,%d2,%acc2
+    4e74:	ae53 3646      	macw %d6u,%d3l,>>,%a3@,%sp,%acc1
+    4e78:	aed3 3656      	macw %d6u,%d3l,>>,%a3@,%sp,%acc2
+    4e7c:	a213 3666      	macw %d6u,%d3l,>>,%a3@&,%d1,%acc1
+    4e80:	a293 3676      	macw %d6u,%d3l,>>,%a3@&,%d1,%acc2
+    4e84:	a653 3666      	macw %d6u,%d3l,>>,%a3@&,%a3,%acc1
+    4e88:	a6d3 3676      	macw %d6u,%d3l,>>,%a3@&,%a3,%acc2
+    4e8c:	a413 3666      	macw %d6u,%d3l,>>,%a3@&,%d2,%acc1
+    4e90:	a493 3676      	macw %d6u,%d3l,>>,%a3@&,%d2,%acc2
+    4e94:	ae53 3666      	macw %d6u,%d3l,>>,%a3@&,%sp,%acc1
+    4e98:	aed3 3676      	macw %d6u,%d3l,>>,%a3@&,%sp,%acc2
+    4e9c:	a21a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d1,%acc1
+    4ea0:	a29a 3656      	macw %d6u,%d3l,>>,%a2@\+,%d1,%acc2
+    4ea4:	a65a 3646      	macw %d6u,%d3l,>>,%a2@\+,%a3,%acc1
+    4ea8:	a6da 3656      	macw %d6u,%d3l,>>,%a2@\+,%a3,%acc2
+    4eac:	a41a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d2,%acc1
+    4eb0:	a49a 3656      	macw %d6u,%d3l,>>,%a2@\+,%d2,%acc2
+    4eb4:	ae5a 3646      	macw %d6u,%d3l,>>,%a2@\+,%sp,%acc1
+    4eb8:	aeda 3656      	macw %d6u,%d3l,>>,%a2@\+,%sp,%acc2
+    4ebc:	a21a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d1,%acc1
+    4ec0:	a29a 3676      	macw %d6u,%d3l,>>,%a2@\+&,%d1,%acc2
+    4ec4:	a65a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%a3,%acc1
+    4ec8:	a6da 3676      	macw %d6u,%d3l,>>,%a2@\+&,%a3,%acc2
+    4ecc:	a41a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d2,%acc1
+    4ed0:	a49a 3676      	macw %d6u,%d3l,>>,%a2@\+&,%d2,%acc2
+    4ed4:	ae5a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%sp,%acc1
+    4ed8:	aeda 3676      	macw %d6u,%d3l,>>,%a2@\+&,%sp,%acc2
+    4edc:	a22e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1,%acc1
+    4ee2:	a2ae 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1,%acc2
+    4ee8:	a66e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3,%acc1
+    4eee:	a6ee 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3,%acc2
+    4ef4:	a42e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2,%acc1
+    4efa:	a4ae 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2,%acc2
+    4f00:	ae6e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp,%acc1
+    4f06:	aeee 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp,%acc2
+    4f0c:	a22e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    4f12:	a2ae 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    4f18:	a66e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    4f1e:	a6ee 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    4f24:	a42e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    4f2a:	a4ae 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    4f30:	ae6e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    4f36:	aeee 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    4f3c:	a221 3646      	macw %d6u,%d3l,>>,%a1@-,%d1,%acc1
+    4f40:	a2a1 3656      	macw %d6u,%d3l,>>,%a1@-,%d1,%acc2
+    4f44:	a661 3646      	macw %d6u,%d3l,>>,%a1@-,%a3,%acc1
+    4f48:	a6e1 3656      	macw %d6u,%d3l,>>,%a1@-,%a3,%acc2
+    4f4c:	a421 3646      	macw %d6u,%d3l,>>,%a1@-,%d2,%acc1
+    4f50:	a4a1 3656      	macw %d6u,%d3l,>>,%a1@-,%d2,%acc2
+    4f54:	ae61 3646      	macw %d6u,%d3l,>>,%a1@-,%sp,%acc1
+    4f58:	aee1 3656      	macw %d6u,%d3l,>>,%a1@-,%sp,%acc2
+    4f5c:	a221 3666      	macw %d6u,%d3l,>>,%a1@-&,%d1,%acc1
+    4f60:	a2a1 3676      	macw %d6u,%d3l,>>,%a1@-&,%d1,%acc2
+    4f64:	a661 3666      	macw %d6u,%d3l,>>,%a1@-&,%a3,%acc1
+    4f68:	a6e1 3676      	macw %d6u,%d3l,>>,%a1@-&,%a3,%acc2
+    4f6c:	a421 3666      	macw %d6u,%d3l,>>,%a1@-&,%d2,%acc1
+    4f70:	a4a1 3676      	macw %d6u,%d3l,>>,%a1@-&,%d2,%acc2
+    4f74:	ae61 3666      	macw %d6u,%d3l,>>,%a1@-&,%sp,%acc1
+    4f78:	aee1 3676      	macw %d6u,%d3l,>>,%a1@-&,%sp,%acc2
+    4f7c:	a213 3246      	macw %d6u,%d3l,<<,%a3@,%d1,%acc1
+    4f80:	a293 3256      	macw %d6u,%d3l,<<,%a3@,%d1,%acc2
+    4f84:	a653 3246      	macw %d6u,%d3l,<<,%a3@,%a3,%acc1
+    4f88:	a6d3 3256      	macw %d6u,%d3l,<<,%a3@,%a3,%acc2
+    4f8c:	a413 3246      	macw %d6u,%d3l,<<,%a3@,%d2,%acc1
+    4f90:	a493 3256      	macw %d6u,%d3l,<<,%a3@,%d2,%acc2
+    4f94:	ae53 3246      	macw %d6u,%d3l,<<,%a3@,%sp,%acc1
+    4f98:	aed3 3256      	macw %d6u,%d3l,<<,%a3@,%sp,%acc2
+    4f9c:	a213 3266      	macw %d6u,%d3l,<<,%a3@&,%d1,%acc1
+    4fa0:	a293 3276      	macw %d6u,%d3l,<<,%a3@&,%d1,%acc2
+    4fa4:	a653 3266      	macw %d6u,%d3l,<<,%a3@&,%a3,%acc1
+    4fa8:	a6d3 3276      	macw %d6u,%d3l,<<,%a3@&,%a3,%acc2
+    4fac:	a413 3266      	macw %d6u,%d3l,<<,%a3@&,%d2,%acc1
+    4fb0:	a493 3276      	macw %d6u,%d3l,<<,%a3@&,%d2,%acc2
+    4fb4:	ae53 3266      	macw %d6u,%d3l,<<,%a3@&,%sp,%acc1
+    4fb8:	aed3 3276      	macw %d6u,%d3l,<<,%a3@&,%sp,%acc2
+    4fbc:	a21a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d1,%acc1
+    4fc0:	a29a 3256      	macw %d6u,%d3l,<<,%a2@\+,%d1,%acc2
+    4fc4:	a65a 3246      	macw %d6u,%d3l,<<,%a2@\+,%a3,%acc1
+    4fc8:	a6da 3256      	macw %d6u,%d3l,<<,%a2@\+,%a3,%acc2
+    4fcc:	a41a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d2,%acc1
+    4fd0:	a49a 3256      	macw %d6u,%d3l,<<,%a2@\+,%d2,%acc2
+    4fd4:	ae5a 3246      	macw %d6u,%d3l,<<,%a2@\+,%sp,%acc1
+    4fd8:	aeda 3256      	macw %d6u,%d3l,<<,%a2@\+,%sp,%acc2
+    4fdc:	a21a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d1,%acc1
+    4fe0:	a29a 3276      	macw %d6u,%d3l,<<,%a2@\+&,%d1,%acc2
+    4fe4:	a65a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%a3,%acc1
+    4fe8:	a6da 3276      	macw %d6u,%d3l,<<,%a2@\+&,%a3,%acc2
+    4fec:	a41a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d2,%acc1
+    4ff0:	a49a 3276      	macw %d6u,%d3l,<<,%a2@\+&,%d2,%acc2
+    4ff4:	ae5a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%sp,%acc1
+    4ff8:	aeda 3276      	macw %d6u,%d3l,<<,%a2@\+&,%sp,%acc2
+    4ffc:	a22e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1,%acc1
+    5002:	a2ae 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1,%acc2
+    5008:	a66e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3,%acc1
+    500e:	a6ee 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3,%acc2
+    5014:	a42e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2,%acc1
+    501a:	a4ae 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2,%acc2
+    5020:	ae6e 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp,%acc1
+    5026:	aeee 3256 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp,%acc2
+    502c:	a22e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1,%acc1
+    5032:	a2ae 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1,%acc2
+    5038:	a66e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3,%acc1
+    503e:	a6ee 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3,%acc2
+    5044:	a42e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2,%acc1
+    504a:	a4ae 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2,%acc2
+    5050:	ae6e 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp,%acc1
+    5056:	aeee 3276 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp,%acc2
+    505c:	a221 3246      	macw %d6u,%d3l,<<,%a1@-,%d1,%acc1
+    5060:	a2a1 3256      	macw %d6u,%d3l,<<,%a1@-,%d1,%acc2
+    5064:	a661 3246      	macw %d6u,%d3l,<<,%a1@-,%a3,%acc1
+    5068:	a6e1 3256      	macw %d6u,%d3l,<<,%a1@-,%a3,%acc2
+    506c:	a421 3246      	macw %d6u,%d3l,<<,%a1@-,%d2,%acc1
+    5070:	a4a1 3256      	macw %d6u,%d3l,<<,%a1@-,%d2,%acc2
+    5074:	ae61 3246      	macw %d6u,%d3l,<<,%a1@-,%sp,%acc1
+    5078:	aee1 3256      	macw %d6u,%d3l,<<,%a1@-,%sp,%acc2
+    507c:	a221 3266      	macw %d6u,%d3l,<<,%a1@-&,%d1,%acc1
+    5080:	a2a1 3276      	macw %d6u,%d3l,<<,%a1@-&,%d1,%acc2
+    5084:	a661 3266      	macw %d6u,%d3l,<<,%a1@-&,%a3,%acc1
+    5088:	a6e1 3276      	macw %d6u,%d3l,<<,%a1@-&,%a3,%acc2
+    508c:	a421 3266      	macw %d6u,%d3l,<<,%a1@-&,%d2,%acc1
+    5090:	a4a1 3276      	macw %d6u,%d3l,<<,%a1@-&,%d2,%acc2
+    5094:	ae61 3266      	macw %d6u,%d3l,<<,%a1@-&,%sp,%acc1
+    5098:	aee1 3276      	macw %d6u,%d3l,<<,%a1@-&,%sp,%acc2
+    509c:	a213 3646      	macw %d6u,%d3l,>>,%a3@,%d1,%acc1
+    50a0:	a293 3656      	macw %d6u,%d3l,>>,%a3@,%d1,%acc2
+    50a4:	a653 3646      	macw %d6u,%d3l,>>,%a3@,%a3,%acc1
+    50a8:	a6d3 3656      	macw %d6u,%d3l,>>,%a3@,%a3,%acc2
+    50ac:	a413 3646      	macw %d6u,%d3l,>>,%a3@,%d2,%acc1
+    50b0:	a493 3656      	macw %d6u,%d3l,>>,%a3@,%d2,%acc2
+    50b4:	ae53 3646      	macw %d6u,%d3l,>>,%a3@,%sp,%acc1
+    50b8:	aed3 3656      	macw %d6u,%d3l,>>,%a3@,%sp,%acc2
+    50bc:	a213 3666      	macw %d6u,%d3l,>>,%a3@&,%d1,%acc1
+    50c0:	a293 3676      	macw %d6u,%d3l,>>,%a3@&,%d1,%acc2
+    50c4:	a653 3666      	macw %d6u,%d3l,>>,%a3@&,%a3,%acc1
+    50c8:	a6d3 3676      	macw %d6u,%d3l,>>,%a3@&,%a3,%acc2
+    50cc:	a413 3666      	macw %d6u,%d3l,>>,%a3@&,%d2,%acc1
+    50d0:	a493 3676      	macw %d6u,%d3l,>>,%a3@&,%d2,%acc2
+    50d4:	ae53 3666      	macw %d6u,%d3l,>>,%a3@&,%sp,%acc1
+    50d8:	aed3 3676      	macw %d6u,%d3l,>>,%a3@&,%sp,%acc2
+    50dc:	a21a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d1,%acc1
+    50e0:	a29a 3656      	macw %d6u,%d3l,>>,%a2@\+,%d1,%acc2
+    50e4:	a65a 3646      	macw %d6u,%d3l,>>,%a2@\+,%a3,%acc1
+    50e8:	a6da 3656      	macw %d6u,%d3l,>>,%a2@\+,%a3,%acc2
+    50ec:	a41a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d2,%acc1
+    50f0:	a49a 3656      	macw %d6u,%d3l,>>,%a2@\+,%d2,%acc2
+    50f4:	ae5a 3646      	macw %d6u,%d3l,>>,%a2@\+,%sp,%acc1
+    50f8:	aeda 3656      	macw %d6u,%d3l,>>,%a2@\+,%sp,%acc2
+    50fc:	a21a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d1,%acc1
+    5100:	a29a 3676      	macw %d6u,%d3l,>>,%a2@\+&,%d1,%acc2
+    5104:	a65a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%a3,%acc1
+    5108:	a6da 3676      	macw %d6u,%d3l,>>,%a2@\+&,%a3,%acc2
+    510c:	a41a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d2,%acc1
+    5110:	a49a 3676      	macw %d6u,%d3l,>>,%a2@\+&,%d2,%acc2
+    5114:	ae5a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%sp,%acc1
+    5118:	aeda 3676      	macw %d6u,%d3l,>>,%a2@\+&,%sp,%acc2
+    511c:	a22e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1,%acc1
+    5122:	a2ae 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1,%acc2
+    5128:	a66e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3,%acc1
+    512e:	a6ee 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3,%acc2
+    5134:	a42e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2,%acc1
+    513a:	a4ae 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2,%acc2
+    5140:	ae6e 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp,%acc1
+    5146:	aeee 3656 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp,%acc2
+    514c:	a22e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1,%acc1
+    5152:	a2ae 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1,%acc2
+    5158:	a66e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3,%acc1
+    515e:	a6ee 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3,%acc2
+    5164:	a42e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2,%acc1
+    516a:	a4ae 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2,%acc2
+    5170:	ae6e 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp,%acc1
+    5176:	aeee 3676 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp,%acc2
+    517c:	a221 3646      	macw %d6u,%d3l,>>,%a1@-,%d1,%acc1
+    5180:	a2a1 3656      	macw %d6u,%d3l,>>,%a1@-,%d1,%acc2
+    5184:	a661 3646      	macw %d6u,%d3l,>>,%a1@-,%a3,%acc1
+    5188:	a6e1 3656      	macw %d6u,%d3l,>>,%a1@-,%a3,%acc2
+    518c:	a421 3646      	macw %d6u,%d3l,>>,%a1@-,%d2,%acc1
+    5190:	a4a1 3656      	macw %d6u,%d3l,>>,%a1@-,%d2,%acc2
+    5194:	ae61 3646      	macw %d6u,%d3l,>>,%a1@-,%sp,%acc1
+    5198:	aee1 3656      	macw %d6u,%d3l,>>,%a1@-,%sp,%acc2
+    519c:	a221 3666      	macw %d6u,%d3l,>>,%a1@-&,%d1,%acc1
+    51a0:	a2a1 3676      	macw %d6u,%d3l,>>,%a1@-&,%d1,%acc2
+    51a4:	a661 3666      	macw %d6u,%d3l,>>,%a1@-&,%a3,%acc1
+    51a8:	a6e1 3676      	macw %d6u,%d3l,>>,%a1@-&,%a3,%acc2
+    51ac:	a421 3666      	macw %d6u,%d3l,>>,%a1@-&,%d2,%acc1
+    51b0:	a4a1 3676      	macw %d6u,%d3l,>>,%a1@-&,%d2,%acc2
+    51b4:	ae61 3666      	macw %d6u,%d3l,>>,%a1@-&,%sp,%acc1
+    51b8:	aee1 3676      	macw %d6u,%d3l,>>,%a1@-&,%sp,%acc2
+    51bc:	a213 f0c6      	macw %d6u,%a7u,%a3@,%d1,%acc1
+    51c0:	a293 f0d6      	macw %d6u,%a7u,%a3@,%d1,%acc2
+    51c4:	a653 f0c6      	macw %d6u,%a7u,%a3@,%a3,%acc1
+    51c8:	a6d3 f0d6      	macw %d6u,%a7u,%a3@,%a3,%acc2
+    51cc:	a413 f0c6      	macw %d6u,%a7u,%a3@,%d2,%acc1
+    51d0:	a493 f0d6      	macw %d6u,%a7u,%a3@,%d2,%acc2
+    51d4:	ae53 f0c6      	macw %d6u,%a7u,%a3@,%sp,%acc1
+    51d8:	aed3 f0d6      	macw %d6u,%a7u,%a3@,%sp,%acc2
+    51dc:	a213 f0e6      	macw %d6u,%a7u,%a3@&,%d1,%acc1
+    51e0:	a293 f0f6      	macw %d6u,%a7u,%a3@&,%d1,%acc2
+    51e4:	a653 f0e6      	macw %d6u,%a7u,%a3@&,%a3,%acc1
+    51e8:	a6d3 f0f6      	macw %d6u,%a7u,%a3@&,%a3,%acc2
+    51ec:	a413 f0e6      	macw %d6u,%a7u,%a3@&,%d2,%acc1
+    51f0:	a493 f0f6      	macw %d6u,%a7u,%a3@&,%d2,%acc2
+    51f4:	ae53 f0e6      	macw %d6u,%a7u,%a3@&,%sp,%acc1
+    51f8:	aed3 f0f6      	macw %d6u,%a7u,%a3@&,%sp,%acc2
+    51fc:	a21a f0c6      	macw %d6u,%a7u,%a2@\+,%d1,%acc1
+    5200:	a29a f0d6      	macw %d6u,%a7u,%a2@\+,%d1,%acc2
+    5204:	a65a f0c6      	macw %d6u,%a7u,%a2@\+,%a3,%acc1
+    5208:	a6da f0d6      	macw %d6u,%a7u,%a2@\+,%a3,%acc2
+    520c:	a41a f0c6      	macw %d6u,%a7u,%a2@\+,%d2,%acc1
+    5210:	a49a f0d6      	macw %d6u,%a7u,%a2@\+,%d2,%acc2
+    5214:	ae5a f0c6      	macw %d6u,%a7u,%a2@\+,%sp,%acc1
+    5218:	aeda f0d6      	macw %d6u,%a7u,%a2@\+,%sp,%acc2
+    521c:	a21a f0e6      	macw %d6u,%a7u,%a2@\+&,%d1,%acc1
+    5220:	a29a f0f6      	macw %d6u,%a7u,%a2@\+&,%d1,%acc2
+    5224:	a65a f0e6      	macw %d6u,%a7u,%a2@\+&,%a3,%acc1
+    5228:	a6da f0f6      	macw %d6u,%a7u,%a2@\+&,%a3,%acc2
+    522c:	a41a f0e6      	macw %d6u,%a7u,%a2@\+&,%d2,%acc1
+    5230:	a49a f0f6      	macw %d6u,%a7u,%a2@\+&,%d2,%acc2
+    5234:	ae5a f0e6      	macw %d6u,%a7u,%a2@\+&,%sp,%acc1
+    5238:	aeda f0f6      	macw %d6u,%a7u,%a2@\+&,%sp,%acc2
+    523c:	a22e f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%d1,%acc1
+    5242:	a2ae f0d6 000a 	macw %d6u,%a7u,%fp@\(10\),%d1,%acc2
+    5248:	a66e f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%a3,%acc1
+    524e:	a6ee f0d6 000a 	macw %d6u,%a7u,%fp@\(10\),%a3,%acc2
+    5254:	a42e f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%d2,%acc1
+    525a:	a4ae f0d6 000a 	macw %d6u,%a7u,%fp@\(10\),%d2,%acc2
+    5260:	ae6e f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%sp,%acc1
+    5266:	aeee f0d6 000a 	macw %d6u,%a7u,%fp@\(10\),%sp,%acc2
+    526c:	a22e f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d1,%acc1
+    5272:	a2ae f0f6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d1,%acc2
+    5278:	a66e f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%a3,%acc1
+    527e:	a6ee f0f6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%a3,%acc2
+    5284:	a42e f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d2,%acc1
+    528a:	a4ae f0f6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d2,%acc2
+    5290:	ae6e f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%sp,%acc1
+    5296:	aeee f0f6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%sp,%acc2
+    529c:	a221 f0c6      	macw %d6u,%a7u,%a1@-,%d1,%acc1
+    52a0:	a2a1 f0d6      	macw %d6u,%a7u,%a1@-,%d1,%acc2
+    52a4:	a661 f0c6      	macw %d6u,%a7u,%a1@-,%a3,%acc1
+    52a8:	a6e1 f0d6      	macw %d6u,%a7u,%a1@-,%a3,%acc2
+    52ac:	a421 f0c6      	macw %d6u,%a7u,%a1@-,%d2,%acc1
+    52b0:	a4a1 f0d6      	macw %d6u,%a7u,%a1@-,%d2,%acc2
+    52b4:	ae61 f0c6      	macw %d6u,%a7u,%a1@-,%sp,%acc1
+    52b8:	aee1 f0d6      	macw %d6u,%a7u,%a1@-,%sp,%acc2
+    52bc:	a221 f0e6      	macw %d6u,%a7u,%a1@-&,%d1,%acc1
+    52c0:	a2a1 f0f6      	macw %d6u,%a7u,%a1@-&,%d1,%acc2
+    52c4:	a661 f0e6      	macw %d6u,%a7u,%a1@-&,%a3,%acc1
+    52c8:	a6e1 f0f6      	macw %d6u,%a7u,%a1@-&,%a3,%acc2
+    52cc:	a421 f0e6      	macw %d6u,%a7u,%a1@-&,%d2,%acc1
+    52d0:	a4a1 f0f6      	macw %d6u,%a7u,%a1@-&,%d2,%acc2
+    52d4:	ae61 f0e6      	macw %d6u,%a7u,%a1@-&,%sp,%acc1
+    52d8:	aee1 f0f6      	macw %d6u,%a7u,%a1@-&,%sp,%acc2
+    52dc:	a213 f2c6      	macw %d6u,%a7u,<<,%a3@,%d1,%acc1
+    52e0:	a293 f2d6      	macw %d6u,%a7u,<<,%a3@,%d1,%acc2
+    52e4:	a653 f2c6      	macw %d6u,%a7u,<<,%a3@,%a3,%acc1
+    52e8:	a6d3 f2d6      	macw %d6u,%a7u,<<,%a3@,%a3,%acc2
+    52ec:	a413 f2c6      	macw %d6u,%a7u,<<,%a3@,%d2,%acc1
+    52f0:	a493 f2d6      	macw %d6u,%a7u,<<,%a3@,%d2,%acc2
+    52f4:	ae53 f2c6      	macw %d6u,%a7u,<<,%a3@,%sp,%acc1
+    52f8:	aed3 f2d6      	macw %d6u,%a7u,<<,%a3@,%sp,%acc2
+    52fc:	a213 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d1,%acc1
+    5300:	a293 f2f6      	macw %d6u,%a7u,<<,%a3@&,%d1,%acc2
+    5304:	a653 f2e6      	macw %d6u,%a7u,<<,%a3@&,%a3,%acc1
+    5308:	a6d3 f2f6      	macw %d6u,%a7u,<<,%a3@&,%a3,%acc2
+    530c:	a413 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d2,%acc1
+    5310:	a493 f2f6      	macw %d6u,%a7u,<<,%a3@&,%d2,%acc2
+    5314:	ae53 f2e6      	macw %d6u,%a7u,<<,%a3@&,%sp,%acc1
+    5318:	aed3 f2f6      	macw %d6u,%a7u,<<,%a3@&,%sp,%acc2
+    531c:	a21a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d1,%acc1
+    5320:	a29a f2d6      	macw %d6u,%a7u,<<,%a2@\+,%d1,%acc2
+    5324:	a65a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%a3,%acc1
+    5328:	a6da f2d6      	macw %d6u,%a7u,<<,%a2@\+,%a3,%acc2
+    532c:	a41a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d2,%acc1
+    5330:	a49a f2d6      	macw %d6u,%a7u,<<,%a2@\+,%d2,%acc2
+    5334:	ae5a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%sp,%acc1
+    5338:	aeda f2d6      	macw %d6u,%a7u,<<,%a2@\+,%sp,%acc2
+    533c:	a21a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d1,%acc1
+    5340:	a29a f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%d1,%acc2
+    5344:	a65a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%a3,%acc1
+    5348:	a6da f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%a3,%acc2
+    534c:	a41a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d2,%acc1
+    5350:	a49a f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%d2,%acc2
+    5354:	ae5a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%sp,%acc1
+    5358:	aeda f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%sp,%acc2
+    535c:	a22e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1,%acc1
+    5362:	a2ae f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1,%acc2
+    5368:	a66e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3,%acc1
+    536e:	a6ee f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3,%acc2
+    5374:	a42e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2,%acc1
+    537a:	a4ae f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2,%acc2
+    5380:	ae6e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp,%acc1
+    5386:	aeee f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp,%acc2
+    538c:	a22e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    5392:	a2ae f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    5398:	a66e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    539e:	a6ee f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    53a4:	a42e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    53aa:	a4ae f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    53b0:	ae6e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    53b6:	aeee f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    53bc:	a221 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d1,%acc1
+    53c0:	a2a1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%d1,%acc2
+    53c4:	a661 f2c6      	macw %d6u,%a7u,<<,%a1@-,%a3,%acc1
+    53c8:	a6e1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%a3,%acc2
+    53cc:	a421 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d2,%acc1
+    53d0:	a4a1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%d2,%acc2
+    53d4:	ae61 f2c6      	macw %d6u,%a7u,<<,%a1@-,%sp,%acc1
+    53d8:	aee1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%sp,%acc2
+    53dc:	a221 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d1,%acc1
+    53e0:	a2a1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%d1,%acc2
+    53e4:	a661 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%a3,%acc1
+    53e8:	a6e1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%a3,%acc2
+    53ec:	a421 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d2,%acc1
+    53f0:	a4a1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%d2,%acc2
+    53f4:	ae61 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%sp,%acc1
+    53f8:	aee1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%sp,%acc2
+    53fc:	a213 f6c6      	macw %d6u,%a7u,>>,%a3@,%d1,%acc1
+    5400:	a293 f6d6      	macw %d6u,%a7u,>>,%a3@,%d1,%acc2
+    5404:	a653 f6c6      	macw %d6u,%a7u,>>,%a3@,%a3,%acc1
+    5408:	a6d3 f6d6      	macw %d6u,%a7u,>>,%a3@,%a3,%acc2
+    540c:	a413 f6c6      	macw %d6u,%a7u,>>,%a3@,%d2,%acc1
+    5410:	a493 f6d6      	macw %d6u,%a7u,>>,%a3@,%d2,%acc2
+    5414:	ae53 f6c6      	macw %d6u,%a7u,>>,%a3@,%sp,%acc1
+    5418:	aed3 f6d6      	macw %d6u,%a7u,>>,%a3@,%sp,%acc2
+    541c:	a213 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d1,%acc1
+    5420:	a293 f6f6      	macw %d6u,%a7u,>>,%a3@&,%d1,%acc2
+    5424:	a653 f6e6      	macw %d6u,%a7u,>>,%a3@&,%a3,%acc1
+    5428:	a6d3 f6f6      	macw %d6u,%a7u,>>,%a3@&,%a3,%acc2
+    542c:	a413 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d2,%acc1
+    5430:	a493 f6f6      	macw %d6u,%a7u,>>,%a3@&,%d2,%acc2
+    5434:	ae53 f6e6      	macw %d6u,%a7u,>>,%a3@&,%sp,%acc1
+    5438:	aed3 f6f6      	macw %d6u,%a7u,>>,%a3@&,%sp,%acc2
+    543c:	a21a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d1,%acc1
+    5440:	a29a f6d6      	macw %d6u,%a7u,>>,%a2@\+,%d1,%acc2
+    5444:	a65a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%a3,%acc1
+    5448:	a6da f6d6      	macw %d6u,%a7u,>>,%a2@\+,%a3,%acc2
+    544c:	a41a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d2,%acc1
+    5450:	a49a f6d6      	macw %d6u,%a7u,>>,%a2@\+,%d2,%acc2
+    5454:	ae5a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%sp,%acc1
+    5458:	aeda f6d6      	macw %d6u,%a7u,>>,%a2@\+,%sp,%acc2
+    545c:	a21a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d1,%acc1
+    5460:	a29a f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%d1,%acc2
+    5464:	a65a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%a3,%acc1
+    5468:	a6da f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%a3,%acc2
+    546c:	a41a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d2,%acc1
+    5470:	a49a f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%d2,%acc2
+    5474:	ae5a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%sp,%acc1
+    5478:	aeda f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%sp,%acc2
+    547c:	a22e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1,%acc1
+    5482:	a2ae f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1,%acc2
+    5488:	a66e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3,%acc1
+    548e:	a6ee f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3,%acc2
+    5494:	a42e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2,%acc1
+    549a:	a4ae f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2,%acc2
+    54a0:	ae6e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp,%acc1
+    54a6:	aeee f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp,%acc2
+    54ac:	a22e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    54b2:	a2ae f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    54b8:	a66e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    54be:	a6ee f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    54c4:	a42e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    54ca:	a4ae f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    54d0:	ae6e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    54d6:	aeee f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    54dc:	a221 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d1,%acc1
+    54e0:	a2a1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%d1,%acc2
+    54e4:	a661 f6c6      	macw %d6u,%a7u,>>,%a1@-,%a3,%acc1
+    54e8:	a6e1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%a3,%acc2
+    54ec:	a421 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d2,%acc1
+    54f0:	a4a1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%d2,%acc2
+    54f4:	ae61 f6c6      	macw %d6u,%a7u,>>,%a1@-,%sp,%acc1
+    54f8:	aee1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%sp,%acc2
+    54fc:	a221 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d1,%acc1
+    5500:	a2a1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%d1,%acc2
+    5504:	a661 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%a3,%acc1
+    5508:	a6e1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%a3,%acc2
+    550c:	a421 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d2,%acc1
+    5510:	a4a1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%d2,%acc2
+    5514:	ae61 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%sp,%acc1
+    5518:	aee1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%sp,%acc2
+    551c:	a213 f2c6      	macw %d6u,%a7u,<<,%a3@,%d1,%acc1
+    5520:	a293 f2d6      	macw %d6u,%a7u,<<,%a3@,%d1,%acc2
+    5524:	a653 f2c6      	macw %d6u,%a7u,<<,%a3@,%a3,%acc1
+    5528:	a6d3 f2d6      	macw %d6u,%a7u,<<,%a3@,%a3,%acc2
+    552c:	a413 f2c6      	macw %d6u,%a7u,<<,%a3@,%d2,%acc1
+    5530:	a493 f2d6      	macw %d6u,%a7u,<<,%a3@,%d2,%acc2
+    5534:	ae53 f2c6      	macw %d6u,%a7u,<<,%a3@,%sp,%acc1
+    5538:	aed3 f2d6      	macw %d6u,%a7u,<<,%a3@,%sp,%acc2
+    553c:	a213 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d1,%acc1
+    5540:	a293 f2f6      	macw %d6u,%a7u,<<,%a3@&,%d1,%acc2
+    5544:	a653 f2e6      	macw %d6u,%a7u,<<,%a3@&,%a3,%acc1
+    5548:	a6d3 f2f6      	macw %d6u,%a7u,<<,%a3@&,%a3,%acc2
+    554c:	a413 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d2,%acc1
+    5550:	a493 f2f6      	macw %d6u,%a7u,<<,%a3@&,%d2,%acc2
+    5554:	ae53 f2e6      	macw %d6u,%a7u,<<,%a3@&,%sp,%acc1
+    5558:	aed3 f2f6      	macw %d6u,%a7u,<<,%a3@&,%sp,%acc2
+    555c:	a21a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d1,%acc1
+    5560:	a29a f2d6      	macw %d6u,%a7u,<<,%a2@\+,%d1,%acc2
+    5564:	a65a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%a3,%acc1
+    5568:	a6da f2d6      	macw %d6u,%a7u,<<,%a2@\+,%a3,%acc2
+    556c:	a41a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d2,%acc1
+    5570:	a49a f2d6      	macw %d6u,%a7u,<<,%a2@\+,%d2,%acc2
+    5574:	ae5a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%sp,%acc1
+    5578:	aeda f2d6      	macw %d6u,%a7u,<<,%a2@\+,%sp,%acc2
+    557c:	a21a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d1,%acc1
+    5580:	a29a f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%d1,%acc2
+    5584:	a65a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%a3,%acc1
+    5588:	a6da f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%a3,%acc2
+    558c:	a41a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d2,%acc1
+    5590:	a49a f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%d2,%acc2
+    5594:	ae5a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%sp,%acc1
+    5598:	aeda f2f6      	macw %d6u,%a7u,<<,%a2@\+&,%sp,%acc2
+    559c:	a22e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1,%acc1
+    55a2:	a2ae f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1,%acc2
+    55a8:	a66e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3,%acc1
+    55ae:	a6ee f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3,%acc2
+    55b4:	a42e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2,%acc1
+    55ba:	a4ae f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2,%acc2
+    55c0:	ae6e f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp,%acc1
+    55c6:	aeee f2d6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp,%acc2
+    55cc:	a22e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1,%acc1
+    55d2:	a2ae f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1,%acc2
+    55d8:	a66e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3,%acc1
+    55de:	a6ee f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3,%acc2
+    55e4:	a42e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2,%acc1
+    55ea:	a4ae f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2,%acc2
+    55f0:	ae6e f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp,%acc1
+    55f6:	aeee f2f6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp,%acc2
+    55fc:	a221 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d1,%acc1
+    5600:	a2a1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%d1,%acc2
+    5604:	a661 f2c6      	macw %d6u,%a7u,<<,%a1@-,%a3,%acc1
+    5608:	a6e1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%a3,%acc2
+    560c:	a421 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d2,%acc1
+    5610:	a4a1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%d2,%acc2
+    5614:	ae61 f2c6      	macw %d6u,%a7u,<<,%a1@-,%sp,%acc1
+    5618:	aee1 f2d6      	macw %d6u,%a7u,<<,%a1@-,%sp,%acc2
+    561c:	a221 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d1,%acc1
+    5620:	a2a1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%d1,%acc2
+    5624:	a661 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%a3,%acc1
+    5628:	a6e1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%a3,%acc2
+    562c:	a421 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d2,%acc1
+    5630:	a4a1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%d2,%acc2
+    5634:	ae61 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%sp,%acc1
+    5638:	aee1 f2f6      	macw %d6u,%a7u,<<,%a1@-&,%sp,%acc2
+    563c:	a213 f6c6      	macw %d6u,%a7u,>>,%a3@,%d1,%acc1
+    5640:	a293 f6d6      	macw %d6u,%a7u,>>,%a3@,%d1,%acc2
+    5644:	a653 f6c6      	macw %d6u,%a7u,>>,%a3@,%a3,%acc1
+    5648:	a6d3 f6d6      	macw %d6u,%a7u,>>,%a3@,%a3,%acc2
+    564c:	a413 f6c6      	macw %d6u,%a7u,>>,%a3@,%d2,%acc1
+    5650:	a493 f6d6      	macw %d6u,%a7u,>>,%a3@,%d2,%acc2
+    5654:	ae53 f6c6      	macw %d6u,%a7u,>>,%a3@,%sp,%acc1
+    5658:	aed3 f6d6      	macw %d6u,%a7u,>>,%a3@,%sp,%acc2
+    565c:	a213 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d1,%acc1
+    5660:	a293 f6f6      	macw %d6u,%a7u,>>,%a3@&,%d1,%acc2
+    5664:	a653 f6e6      	macw %d6u,%a7u,>>,%a3@&,%a3,%acc1
+    5668:	a6d3 f6f6      	macw %d6u,%a7u,>>,%a3@&,%a3,%acc2
+    566c:	a413 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d2,%acc1
+    5670:	a493 f6f6      	macw %d6u,%a7u,>>,%a3@&,%d2,%acc2
+    5674:	ae53 f6e6      	macw %d6u,%a7u,>>,%a3@&,%sp,%acc1
+    5678:	aed3 f6f6      	macw %d6u,%a7u,>>,%a3@&,%sp,%acc2
+    567c:	a21a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d1,%acc1
+    5680:	a29a f6d6      	macw %d6u,%a7u,>>,%a2@\+,%d1,%acc2
+    5684:	a65a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%a3,%acc1
+    5688:	a6da f6d6      	macw %d6u,%a7u,>>,%a2@\+,%a3,%acc2
+    568c:	a41a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d2,%acc1
+    5690:	a49a f6d6      	macw %d6u,%a7u,>>,%a2@\+,%d2,%acc2
+    5694:	ae5a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%sp,%acc1
+    5698:	aeda f6d6      	macw %d6u,%a7u,>>,%a2@\+,%sp,%acc2
+    569c:	a21a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d1,%acc1
+    56a0:	a29a f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%d1,%acc2
+    56a4:	a65a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%a3,%acc1
+    56a8:	a6da f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%a3,%acc2
+    56ac:	a41a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d2,%acc1
+    56b0:	a49a f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%d2,%acc2
+    56b4:	ae5a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%sp,%acc1
+    56b8:	aeda f6f6      	macw %d6u,%a7u,>>,%a2@\+&,%sp,%acc2
+    56bc:	a22e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1,%acc1
+    56c2:	a2ae f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1,%acc2
+    56c8:	a66e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3,%acc1
+    56ce:	a6ee f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3,%acc2
+    56d4:	a42e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2,%acc1
+    56da:	a4ae f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2,%acc2
+    56e0:	ae6e f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp,%acc1
+    56e6:	aeee f6d6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp,%acc2
+    56ec:	a22e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1,%acc1
+    56f2:	a2ae f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1,%acc2
+    56f8:	a66e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3,%acc1
+    56fe:	a6ee f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3,%acc2
+    5704:	a42e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2,%acc1
+    570a:	a4ae f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2,%acc2
+    5710:	ae6e f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp,%acc1
+    5716:	aeee f6f6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp,%acc2
+    571c:	a221 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d1,%acc1
+    5720:	a2a1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%d1,%acc2
+    5724:	a661 f6c6      	macw %d6u,%a7u,>>,%a1@-,%a3,%acc1
+    5728:	a6e1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%a3,%acc2
+    572c:	a421 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d2,%acc1
+    5730:	a4a1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%d2,%acc2
+    5734:	ae61 f6c6      	macw %d6u,%a7u,>>,%a1@-,%sp,%acc1
+    5738:	aee1 f6d6      	macw %d6u,%a7u,>>,%a1@-,%sp,%acc2
+    573c:	a221 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d1,%acc1
+    5740:	a2a1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%d1,%acc2
+    5744:	a661 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%a3,%acc1
+    5748:	a6e1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%a3,%acc2
+    574c:	a421 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d2,%acc1
+    5750:	a4a1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%d2,%acc2
+    5754:	ae61 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%sp,%acc1
+    5758:	aee1 f6f6      	macw %d6u,%a7u,>>,%a1@-&,%sp,%acc2
+    575c:	a213 1046      	macw %d6u,%d1l,%a3@,%d1,%acc1
+    5760:	a293 1056      	macw %d6u,%d1l,%a3@,%d1,%acc2
+    5764:	a653 1046      	macw %d6u,%d1l,%a3@,%a3,%acc1
+    5768:	a6d3 1056      	macw %d6u,%d1l,%a3@,%a3,%acc2
+    576c:	a413 1046      	macw %d6u,%d1l,%a3@,%d2,%acc1
+    5770:	a493 1056      	macw %d6u,%d1l,%a3@,%d2,%acc2
+    5774:	ae53 1046      	macw %d6u,%d1l,%a3@,%sp,%acc1
+    5778:	aed3 1056      	macw %d6u,%d1l,%a3@,%sp,%acc2
+    577c:	a213 1066      	macw %d6u,%d1l,%a3@&,%d1,%acc1
+    5780:	a293 1076      	macw %d6u,%d1l,%a3@&,%d1,%acc2
+    5784:	a653 1066      	macw %d6u,%d1l,%a3@&,%a3,%acc1
+    5788:	a6d3 1076      	macw %d6u,%d1l,%a3@&,%a3,%acc2
+    578c:	a413 1066      	macw %d6u,%d1l,%a3@&,%d2,%acc1
+    5790:	a493 1076      	macw %d6u,%d1l,%a3@&,%d2,%acc2
+    5794:	ae53 1066      	macw %d6u,%d1l,%a3@&,%sp,%acc1
+    5798:	aed3 1076      	macw %d6u,%d1l,%a3@&,%sp,%acc2
+    579c:	a21a 1046      	macw %d6u,%d1l,%a2@\+,%d1,%acc1
+    57a0:	a29a 1056      	macw %d6u,%d1l,%a2@\+,%d1,%acc2
+    57a4:	a65a 1046      	macw %d6u,%d1l,%a2@\+,%a3,%acc1
+    57a8:	a6da 1056      	macw %d6u,%d1l,%a2@\+,%a3,%acc2
+    57ac:	a41a 1046      	macw %d6u,%d1l,%a2@\+,%d2,%acc1
+    57b0:	a49a 1056      	macw %d6u,%d1l,%a2@\+,%d2,%acc2
+    57b4:	ae5a 1046      	macw %d6u,%d1l,%a2@\+,%sp,%acc1
+    57b8:	aeda 1056      	macw %d6u,%d1l,%a2@\+,%sp,%acc2
+    57bc:	a21a 1066      	macw %d6u,%d1l,%a2@\+&,%d1,%acc1
+    57c0:	a29a 1076      	macw %d6u,%d1l,%a2@\+&,%d1,%acc2
+    57c4:	a65a 1066      	macw %d6u,%d1l,%a2@\+&,%a3,%acc1
+    57c8:	a6da 1076      	macw %d6u,%d1l,%a2@\+&,%a3,%acc2
+    57cc:	a41a 1066      	macw %d6u,%d1l,%a2@\+&,%d2,%acc1
+    57d0:	a49a 1076      	macw %d6u,%d1l,%a2@\+&,%d2,%acc2
+    57d4:	ae5a 1066      	macw %d6u,%d1l,%a2@\+&,%sp,%acc1
+    57d8:	aeda 1076      	macw %d6u,%d1l,%a2@\+&,%sp,%acc2
+    57dc:	a22e 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%d1,%acc1
+    57e2:	a2ae 1056 000a 	macw %d6u,%d1l,%fp@\(10\),%d1,%acc2
+    57e8:	a66e 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%a3,%acc1
+    57ee:	a6ee 1056 000a 	macw %d6u,%d1l,%fp@\(10\),%a3,%acc2
+    57f4:	a42e 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%d2,%acc1
+    57fa:	a4ae 1056 000a 	macw %d6u,%d1l,%fp@\(10\),%d2,%acc2
+    5800:	ae6e 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%sp,%acc1
+    5806:	aeee 1056 000a 	macw %d6u,%d1l,%fp@\(10\),%sp,%acc2
+    580c:	a22e 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d1,%acc1
+    5812:	a2ae 1076 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d1,%acc2
+    5818:	a66e 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%a3,%acc1
+    581e:	a6ee 1076 000a 	macw %d6u,%d1l,%fp@\(10\)&,%a3,%acc2
+    5824:	a42e 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d2,%acc1
+    582a:	a4ae 1076 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d2,%acc2
+    5830:	ae6e 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%sp,%acc1
+    5836:	aeee 1076 000a 	macw %d6u,%d1l,%fp@\(10\)&,%sp,%acc2
+    583c:	a221 1046      	macw %d6u,%d1l,%a1@-,%d1,%acc1
+    5840:	a2a1 1056      	macw %d6u,%d1l,%a1@-,%d1,%acc2
+    5844:	a661 1046      	macw %d6u,%d1l,%a1@-,%a3,%acc1
+    5848:	a6e1 1056      	macw %d6u,%d1l,%a1@-,%a3,%acc2
+    584c:	a421 1046      	macw %d6u,%d1l,%a1@-,%d2,%acc1
+    5850:	a4a1 1056      	macw %d6u,%d1l,%a1@-,%d2,%acc2
+    5854:	ae61 1046      	macw %d6u,%d1l,%a1@-,%sp,%acc1
+    5858:	aee1 1056      	macw %d6u,%d1l,%a1@-,%sp,%acc2
+    585c:	a221 1066      	macw %d6u,%d1l,%a1@-&,%d1,%acc1
+    5860:	a2a1 1076      	macw %d6u,%d1l,%a1@-&,%d1,%acc2
+    5864:	a661 1066      	macw %d6u,%d1l,%a1@-&,%a3,%acc1
+    5868:	a6e1 1076      	macw %d6u,%d1l,%a1@-&,%a3,%acc2
+    586c:	a421 1066      	macw %d6u,%d1l,%a1@-&,%d2,%acc1
+    5870:	a4a1 1076      	macw %d6u,%d1l,%a1@-&,%d2,%acc2
+    5874:	ae61 1066      	macw %d6u,%d1l,%a1@-&,%sp,%acc1
+    5878:	aee1 1076      	macw %d6u,%d1l,%a1@-&,%sp,%acc2
+    587c:	a213 1246      	macw %d6u,%d1l,<<,%a3@,%d1,%acc1
+    5880:	a293 1256      	macw %d6u,%d1l,<<,%a3@,%d1,%acc2
+    5884:	a653 1246      	macw %d6u,%d1l,<<,%a3@,%a3,%acc1
+    5888:	a6d3 1256      	macw %d6u,%d1l,<<,%a3@,%a3,%acc2
+    588c:	a413 1246      	macw %d6u,%d1l,<<,%a3@,%d2,%acc1
+    5890:	a493 1256      	macw %d6u,%d1l,<<,%a3@,%d2,%acc2
+    5894:	ae53 1246      	macw %d6u,%d1l,<<,%a3@,%sp,%acc1
+    5898:	aed3 1256      	macw %d6u,%d1l,<<,%a3@,%sp,%acc2
+    589c:	a213 1266      	macw %d6u,%d1l,<<,%a3@&,%d1,%acc1
+    58a0:	a293 1276      	macw %d6u,%d1l,<<,%a3@&,%d1,%acc2
+    58a4:	a653 1266      	macw %d6u,%d1l,<<,%a3@&,%a3,%acc1
+    58a8:	a6d3 1276      	macw %d6u,%d1l,<<,%a3@&,%a3,%acc2
+    58ac:	a413 1266      	macw %d6u,%d1l,<<,%a3@&,%d2,%acc1
+    58b0:	a493 1276      	macw %d6u,%d1l,<<,%a3@&,%d2,%acc2
+    58b4:	ae53 1266      	macw %d6u,%d1l,<<,%a3@&,%sp,%acc1
+    58b8:	aed3 1276      	macw %d6u,%d1l,<<,%a3@&,%sp,%acc2
+    58bc:	a21a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d1,%acc1
+    58c0:	a29a 1256      	macw %d6u,%d1l,<<,%a2@\+,%d1,%acc2
+    58c4:	a65a 1246      	macw %d6u,%d1l,<<,%a2@\+,%a3,%acc1
+    58c8:	a6da 1256      	macw %d6u,%d1l,<<,%a2@\+,%a3,%acc2
+    58cc:	a41a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d2,%acc1
+    58d0:	a49a 1256      	macw %d6u,%d1l,<<,%a2@\+,%d2,%acc2
+    58d4:	ae5a 1246      	macw %d6u,%d1l,<<,%a2@\+,%sp,%acc1
+    58d8:	aeda 1256      	macw %d6u,%d1l,<<,%a2@\+,%sp,%acc2
+    58dc:	a21a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d1,%acc1
+    58e0:	a29a 1276      	macw %d6u,%d1l,<<,%a2@\+&,%d1,%acc2
+    58e4:	a65a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%a3,%acc1
+    58e8:	a6da 1276      	macw %d6u,%d1l,<<,%a2@\+&,%a3,%acc2
+    58ec:	a41a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d2,%acc1
+    58f0:	a49a 1276      	macw %d6u,%d1l,<<,%a2@\+&,%d2,%acc2
+    58f4:	ae5a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%sp,%acc1
+    58f8:	aeda 1276      	macw %d6u,%d1l,<<,%a2@\+&,%sp,%acc2
+    58fc:	a22e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1,%acc1
+    5902:	a2ae 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1,%acc2
+    5908:	a66e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3,%acc1
+    590e:	a6ee 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3,%acc2
+    5914:	a42e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2,%acc1
+    591a:	a4ae 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2,%acc2
+    5920:	ae6e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp,%acc1
+    5926:	aeee 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp,%acc2
+    592c:	a22e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    5932:	a2ae 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    5938:	a66e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    593e:	a6ee 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    5944:	a42e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    594a:	a4ae 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    5950:	ae6e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    5956:	aeee 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    595c:	a221 1246      	macw %d6u,%d1l,<<,%a1@-,%d1,%acc1
+    5960:	a2a1 1256      	macw %d6u,%d1l,<<,%a1@-,%d1,%acc2
+    5964:	a661 1246      	macw %d6u,%d1l,<<,%a1@-,%a3,%acc1
+    5968:	a6e1 1256      	macw %d6u,%d1l,<<,%a1@-,%a3,%acc2
+    596c:	a421 1246      	macw %d6u,%d1l,<<,%a1@-,%d2,%acc1
+    5970:	a4a1 1256      	macw %d6u,%d1l,<<,%a1@-,%d2,%acc2
+    5974:	ae61 1246      	macw %d6u,%d1l,<<,%a1@-,%sp,%acc1
+    5978:	aee1 1256      	macw %d6u,%d1l,<<,%a1@-,%sp,%acc2
+    597c:	a221 1266      	macw %d6u,%d1l,<<,%a1@-&,%d1,%acc1
+    5980:	a2a1 1276      	macw %d6u,%d1l,<<,%a1@-&,%d1,%acc2
+    5984:	a661 1266      	macw %d6u,%d1l,<<,%a1@-&,%a3,%acc1
+    5988:	a6e1 1276      	macw %d6u,%d1l,<<,%a1@-&,%a3,%acc2
+    598c:	a421 1266      	macw %d6u,%d1l,<<,%a1@-&,%d2,%acc1
+    5990:	a4a1 1276      	macw %d6u,%d1l,<<,%a1@-&,%d2,%acc2
+    5994:	ae61 1266      	macw %d6u,%d1l,<<,%a1@-&,%sp,%acc1
+    5998:	aee1 1276      	macw %d6u,%d1l,<<,%a1@-&,%sp,%acc2
+    599c:	a213 1646      	macw %d6u,%d1l,>>,%a3@,%d1,%acc1
+    59a0:	a293 1656      	macw %d6u,%d1l,>>,%a3@,%d1,%acc2
+    59a4:	a653 1646      	macw %d6u,%d1l,>>,%a3@,%a3,%acc1
+    59a8:	a6d3 1656      	macw %d6u,%d1l,>>,%a3@,%a3,%acc2
+    59ac:	a413 1646      	macw %d6u,%d1l,>>,%a3@,%d2,%acc1
+    59b0:	a493 1656      	macw %d6u,%d1l,>>,%a3@,%d2,%acc2
+    59b4:	ae53 1646      	macw %d6u,%d1l,>>,%a3@,%sp,%acc1
+    59b8:	aed3 1656      	macw %d6u,%d1l,>>,%a3@,%sp,%acc2
+    59bc:	a213 1666      	macw %d6u,%d1l,>>,%a3@&,%d1,%acc1
+    59c0:	a293 1676      	macw %d6u,%d1l,>>,%a3@&,%d1,%acc2
+    59c4:	a653 1666      	macw %d6u,%d1l,>>,%a3@&,%a3,%acc1
+    59c8:	a6d3 1676      	macw %d6u,%d1l,>>,%a3@&,%a3,%acc2
+    59cc:	a413 1666      	macw %d6u,%d1l,>>,%a3@&,%d2,%acc1
+    59d0:	a493 1676      	macw %d6u,%d1l,>>,%a3@&,%d2,%acc2
+    59d4:	ae53 1666      	macw %d6u,%d1l,>>,%a3@&,%sp,%acc1
+    59d8:	aed3 1676      	macw %d6u,%d1l,>>,%a3@&,%sp,%acc2
+    59dc:	a21a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d1,%acc1
+    59e0:	a29a 1656      	macw %d6u,%d1l,>>,%a2@\+,%d1,%acc2
+    59e4:	a65a 1646      	macw %d6u,%d1l,>>,%a2@\+,%a3,%acc1
+    59e8:	a6da 1656      	macw %d6u,%d1l,>>,%a2@\+,%a3,%acc2
+    59ec:	a41a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d2,%acc1
+    59f0:	a49a 1656      	macw %d6u,%d1l,>>,%a2@\+,%d2,%acc2
+    59f4:	ae5a 1646      	macw %d6u,%d1l,>>,%a2@\+,%sp,%acc1
+    59f8:	aeda 1656      	macw %d6u,%d1l,>>,%a2@\+,%sp,%acc2
+    59fc:	a21a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d1,%acc1
+    5a00:	a29a 1676      	macw %d6u,%d1l,>>,%a2@\+&,%d1,%acc2
+    5a04:	a65a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%a3,%acc1
+    5a08:	a6da 1676      	macw %d6u,%d1l,>>,%a2@\+&,%a3,%acc2
+    5a0c:	a41a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d2,%acc1
+    5a10:	a49a 1676      	macw %d6u,%d1l,>>,%a2@\+&,%d2,%acc2
+    5a14:	ae5a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%sp,%acc1
+    5a18:	aeda 1676      	macw %d6u,%d1l,>>,%a2@\+&,%sp,%acc2
+    5a1c:	a22e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1,%acc1
+    5a22:	a2ae 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1,%acc2
+    5a28:	a66e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3,%acc1
+    5a2e:	a6ee 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3,%acc2
+    5a34:	a42e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2,%acc1
+    5a3a:	a4ae 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2,%acc2
+    5a40:	ae6e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp,%acc1
+    5a46:	aeee 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp,%acc2
+    5a4c:	a22e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    5a52:	a2ae 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    5a58:	a66e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    5a5e:	a6ee 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    5a64:	a42e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    5a6a:	a4ae 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    5a70:	ae6e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    5a76:	aeee 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    5a7c:	a221 1646      	macw %d6u,%d1l,>>,%a1@-,%d1,%acc1
+    5a80:	a2a1 1656      	macw %d6u,%d1l,>>,%a1@-,%d1,%acc2
+    5a84:	a661 1646      	macw %d6u,%d1l,>>,%a1@-,%a3,%acc1
+    5a88:	a6e1 1656      	macw %d6u,%d1l,>>,%a1@-,%a3,%acc2
+    5a8c:	a421 1646      	macw %d6u,%d1l,>>,%a1@-,%d2,%acc1
+    5a90:	a4a1 1656      	macw %d6u,%d1l,>>,%a1@-,%d2,%acc2
+    5a94:	ae61 1646      	macw %d6u,%d1l,>>,%a1@-,%sp,%acc1
+    5a98:	aee1 1656      	macw %d6u,%d1l,>>,%a1@-,%sp,%acc2
+    5a9c:	a221 1666      	macw %d6u,%d1l,>>,%a1@-&,%d1,%acc1
+    5aa0:	a2a1 1676      	macw %d6u,%d1l,>>,%a1@-&,%d1,%acc2
+    5aa4:	a661 1666      	macw %d6u,%d1l,>>,%a1@-&,%a3,%acc1
+    5aa8:	a6e1 1676      	macw %d6u,%d1l,>>,%a1@-&,%a3,%acc2
+    5aac:	a421 1666      	macw %d6u,%d1l,>>,%a1@-&,%d2,%acc1
+    5ab0:	a4a1 1676      	macw %d6u,%d1l,>>,%a1@-&,%d2,%acc2
+    5ab4:	ae61 1666      	macw %d6u,%d1l,>>,%a1@-&,%sp,%acc1
+    5ab8:	aee1 1676      	macw %d6u,%d1l,>>,%a1@-&,%sp,%acc2
+    5abc:	a213 1246      	macw %d6u,%d1l,<<,%a3@,%d1,%acc1
+    5ac0:	a293 1256      	macw %d6u,%d1l,<<,%a3@,%d1,%acc2
+    5ac4:	a653 1246      	macw %d6u,%d1l,<<,%a3@,%a3,%acc1
+    5ac8:	a6d3 1256      	macw %d6u,%d1l,<<,%a3@,%a3,%acc2
+    5acc:	a413 1246      	macw %d6u,%d1l,<<,%a3@,%d2,%acc1
+    5ad0:	a493 1256      	macw %d6u,%d1l,<<,%a3@,%d2,%acc2
+    5ad4:	ae53 1246      	macw %d6u,%d1l,<<,%a3@,%sp,%acc1
+    5ad8:	aed3 1256      	macw %d6u,%d1l,<<,%a3@,%sp,%acc2
+    5adc:	a213 1266      	macw %d6u,%d1l,<<,%a3@&,%d1,%acc1
+    5ae0:	a293 1276      	macw %d6u,%d1l,<<,%a3@&,%d1,%acc2
+    5ae4:	a653 1266      	macw %d6u,%d1l,<<,%a3@&,%a3,%acc1
+    5ae8:	a6d3 1276      	macw %d6u,%d1l,<<,%a3@&,%a3,%acc2
+    5aec:	a413 1266      	macw %d6u,%d1l,<<,%a3@&,%d2,%acc1
+    5af0:	a493 1276      	macw %d6u,%d1l,<<,%a3@&,%d2,%acc2
+    5af4:	ae53 1266      	macw %d6u,%d1l,<<,%a3@&,%sp,%acc1
+    5af8:	aed3 1276      	macw %d6u,%d1l,<<,%a3@&,%sp,%acc2
+    5afc:	a21a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d1,%acc1
+    5b00:	a29a 1256      	macw %d6u,%d1l,<<,%a2@\+,%d1,%acc2
+    5b04:	a65a 1246      	macw %d6u,%d1l,<<,%a2@\+,%a3,%acc1
+    5b08:	a6da 1256      	macw %d6u,%d1l,<<,%a2@\+,%a3,%acc2
+    5b0c:	a41a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d2,%acc1
+    5b10:	a49a 1256      	macw %d6u,%d1l,<<,%a2@\+,%d2,%acc2
+    5b14:	ae5a 1246      	macw %d6u,%d1l,<<,%a2@\+,%sp,%acc1
+    5b18:	aeda 1256      	macw %d6u,%d1l,<<,%a2@\+,%sp,%acc2
+    5b1c:	a21a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d1,%acc1
+    5b20:	a29a 1276      	macw %d6u,%d1l,<<,%a2@\+&,%d1,%acc2
+    5b24:	a65a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%a3,%acc1
+    5b28:	a6da 1276      	macw %d6u,%d1l,<<,%a2@\+&,%a3,%acc2
+    5b2c:	a41a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d2,%acc1
+    5b30:	a49a 1276      	macw %d6u,%d1l,<<,%a2@\+&,%d2,%acc2
+    5b34:	ae5a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%sp,%acc1
+    5b38:	aeda 1276      	macw %d6u,%d1l,<<,%a2@\+&,%sp,%acc2
+    5b3c:	a22e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1,%acc1
+    5b42:	a2ae 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1,%acc2
+    5b48:	a66e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3,%acc1
+    5b4e:	a6ee 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3,%acc2
+    5b54:	a42e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2,%acc1
+    5b5a:	a4ae 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2,%acc2
+    5b60:	ae6e 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp,%acc1
+    5b66:	aeee 1256 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp,%acc2
+    5b6c:	a22e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1,%acc1
+    5b72:	a2ae 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1,%acc2
+    5b78:	a66e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3,%acc1
+    5b7e:	a6ee 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3,%acc2
+    5b84:	a42e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2,%acc1
+    5b8a:	a4ae 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2,%acc2
+    5b90:	ae6e 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp,%acc1
+    5b96:	aeee 1276 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp,%acc2
+    5b9c:	a221 1246      	macw %d6u,%d1l,<<,%a1@-,%d1,%acc1
+    5ba0:	a2a1 1256      	macw %d6u,%d1l,<<,%a1@-,%d1,%acc2
+    5ba4:	a661 1246      	macw %d6u,%d1l,<<,%a1@-,%a3,%acc1
+    5ba8:	a6e1 1256      	macw %d6u,%d1l,<<,%a1@-,%a3,%acc2
+    5bac:	a421 1246      	macw %d6u,%d1l,<<,%a1@-,%d2,%acc1
+    5bb0:	a4a1 1256      	macw %d6u,%d1l,<<,%a1@-,%d2,%acc2
+    5bb4:	ae61 1246      	macw %d6u,%d1l,<<,%a1@-,%sp,%acc1
+    5bb8:	aee1 1256      	macw %d6u,%d1l,<<,%a1@-,%sp,%acc2
+    5bbc:	a221 1266      	macw %d6u,%d1l,<<,%a1@-&,%d1,%acc1
+    5bc0:	a2a1 1276      	macw %d6u,%d1l,<<,%a1@-&,%d1,%acc2
+    5bc4:	a661 1266      	macw %d6u,%d1l,<<,%a1@-&,%a3,%acc1
+    5bc8:	a6e1 1276      	macw %d6u,%d1l,<<,%a1@-&,%a3,%acc2
+    5bcc:	a421 1266      	macw %d6u,%d1l,<<,%a1@-&,%d2,%acc1
+    5bd0:	a4a1 1276      	macw %d6u,%d1l,<<,%a1@-&,%d2,%acc2
+    5bd4:	ae61 1266      	macw %d6u,%d1l,<<,%a1@-&,%sp,%acc1
+    5bd8:	aee1 1276      	macw %d6u,%d1l,<<,%a1@-&,%sp,%acc2
+    5bdc:	a213 1646      	macw %d6u,%d1l,>>,%a3@,%d1,%acc1
+    5be0:	a293 1656      	macw %d6u,%d1l,>>,%a3@,%d1,%acc2
+    5be4:	a653 1646      	macw %d6u,%d1l,>>,%a3@,%a3,%acc1
+    5be8:	a6d3 1656      	macw %d6u,%d1l,>>,%a3@,%a3,%acc2
+    5bec:	a413 1646      	macw %d6u,%d1l,>>,%a3@,%d2,%acc1
+    5bf0:	a493 1656      	macw %d6u,%d1l,>>,%a3@,%d2,%acc2
+    5bf4:	ae53 1646      	macw %d6u,%d1l,>>,%a3@,%sp,%acc1
+    5bf8:	aed3 1656      	macw %d6u,%d1l,>>,%a3@,%sp,%acc2
+    5bfc:	a213 1666      	macw %d6u,%d1l,>>,%a3@&,%d1,%acc1
+    5c00:	a293 1676      	macw %d6u,%d1l,>>,%a3@&,%d1,%acc2
+    5c04:	a653 1666      	macw %d6u,%d1l,>>,%a3@&,%a3,%acc1
+    5c08:	a6d3 1676      	macw %d6u,%d1l,>>,%a3@&,%a3,%acc2
+    5c0c:	a413 1666      	macw %d6u,%d1l,>>,%a3@&,%d2,%acc1
+    5c10:	a493 1676      	macw %d6u,%d1l,>>,%a3@&,%d2,%acc2
+    5c14:	ae53 1666      	macw %d6u,%d1l,>>,%a3@&,%sp,%acc1
+    5c18:	aed3 1676      	macw %d6u,%d1l,>>,%a3@&,%sp,%acc2
+    5c1c:	a21a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d1,%acc1
+    5c20:	a29a 1656      	macw %d6u,%d1l,>>,%a2@\+,%d1,%acc2
+    5c24:	a65a 1646      	macw %d6u,%d1l,>>,%a2@\+,%a3,%acc1
+    5c28:	a6da 1656      	macw %d6u,%d1l,>>,%a2@\+,%a3,%acc2
+    5c2c:	a41a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d2,%acc1
+    5c30:	a49a 1656      	macw %d6u,%d1l,>>,%a2@\+,%d2,%acc2
+    5c34:	ae5a 1646      	macw %d6u,%d1l,>>,%a2@\+,%sp,%acc1
+    5c38:	aeda 1656      	macw %d6u,%d1l,>>,%a2@\+,%sp,%acc2
+    5c3c:	a21a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d1,%acc1
+    5c40:	a29a 1676      	macw %d6u,%d1l,>>,%a2@\+&,%d1,%acc2
+    5c44:	a65a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%a3,%acc1
+    5c48:	a6da 1676      	macw %d6u,%d1l,>>,%a2@\+&,%a3,%acc2
+    5c4c:	a41a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d2,%acc1
+    5c50:	a49a 1676      	macw %d6u,%d1l,>>,%a2@\+&,%d2,%acc2
+    5c54:	ae5a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%sp,%acc1
+    5c58:	aeda 1676      	macw %d6u,%d1l,>>,%a2@\+&,%sp,%acc2
+    5c5c:	a22e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1,%acc1
+    5c62:	a2ae 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1,%acc2
+    5c68:	a66e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3,%acc1
+    5c6e:	a6ee 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3,%acc2
+    5c74:	a42e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2,%acc1
+    5c7a:	a4ae 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2,%acc2
+    5c80:	ae6e 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp,%acc1
+    5c86:	aeee 1656 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp,%acc2
+    5c8c:	a22e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1,%acc1
+    5c92:	a2ae 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1,%acc2
+    5c98:	a66e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3,%acc1
+    5c9e:	a6ee 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3,%acc2
+    5ca4:	a42e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2,%acc1
+    5caa:	a4ae 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2,%acc2
+    5cb0:	ae6e 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp,%acc1
+    5cb6:	aeee 1676 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp,%acc2
+    5cbc:	a221 1646      	macw %d6u,%d1l,>>,%a1@-,%d1,%acc1
+    5cc0:	a2a1 1656      	macw %d6u,%d1l,>>,%a1@-,%d1,%acc2
+    5cc4:	a661 1646      	macw %d6u,%d1l,>>,%a1@-,%a3,%acc1
+    5cc8:	a6e1 1656      	macw %d6u,%d1l,>>,%a1@-,%a3,%acc2
+    5ccc:	a421 1646      	macw %d6u,%d1l,>>,%a1@-,%d2,%acc1
+    5cd0:	a4a1 1656      	macw %d6u,%d1l,>>,%a1@-,%d2,%acc2
+    5cd4:	ae61 1646      	macw %d6u,%d1l,>>,%a1@-,%sp,%acc1
+    5cd8:	aee1 1656      	macw %d6u,%d1l,>>,%a1@-,%sp,%acc2
+    5cdc:	a221 1666      	macw %d6u,%d1l,>>,%a1@-&,%d1,%acc1
+    5ce0:	a2a1 1676      	macw %d6u,%d1l,>>,%a1@-&,%d1,%acc2
+    5ce4:	a661 1666      	macw %d6u,%d1l,>>,%a1@-&,%a3,%acc1
+    5ce8:	a6e1 1676      	macw %d6u,%d1l,>>,%a1@-&,%a3,%acc2
+    5cec:	a421 1666      	macw %d6u,%d1l,>>,%a1@-&,%d2,%acc1
+    5cf0:	a4a1 1676      	macw %d6u,%d1l,>>,%a1@-&,%d2,%acc2
+    5cf4:	ae61 1666      	macw %d6u,%d1l,>>,%a1@-&,%sp,%acc1
+    5cf8:	aee1 1676      	macw %d6u,%d1l,>>,%a1@-&,%sp,%acc2
+    5cfc:	a6c9 0800      	macl %a1,%a3,%acc1
+    5d00:	a649 0810      	macl %a1,%a3,%acc2
+    5d04:	a6c9 0a00      	macl %a1,%a3,<<,%acc1
+    5d08:	a649 0a10      	macl %a1,%a3,<<,%acc2
+    5d0c:	a6c9 0e00      	macl %a1,%a3,>>,%acc1
+    5d10:	a649 0e10      	macl %a1,%a3,>>,%acc2
+    5d14:	a6c9 0a00      	macl %a1,%a3,<<,%acc1
+    5d18:	a649 0a10      	macl %a1,%a3,<<,%acc2
+    5d1c:	a6c9 0e00      	macl %a1,%a3,>>,%acc1
+    5d20:	a649 0e10      	macl %a1,%a3,>>,%acc2
+    5d24:	a889 0800      	macl %a1,%d4,%acc1
+    5d28:	a809 0810      	macl %a1,%d4,%acc2
+    5d2c:	a889 0a00      	macl %a1,%d4,<<,%acc1
+    5d30:	a809 0a10      	macl %a1,%d4,<<,%acc2
+    5d34:	a889 0e00      	macl %a1,%d4,>>,%acc1
+    5d38:	a809 0e10      	macl %a1,%d4,>>,%acc2
+    5d3c:	a889 0a00      	macl %a1,%d4,<<,%acc1
+    5d40:	a809 0a10      	macl %a1,%d4,<<,%acc2
+    5d44:	a889 0e00      	macl %a1,%d4,>>,%acc1
+    5d48:	a809 0e10      	macl %a1,%d4,>>,%acc2
+    5d4c:	a6c6 0800      	macl %d6,%a3,%acc1
+    5d50:	a646 0810      	macl %d6,%a3,%acc2
+    5d54:	a6c6 0a00      	macl %d6,%a3,<<,%acc1
+    5d58:	a646 0a10      	macl %d6,%a3,<<,%acc2
+    5d5c:	a6c6 0e00      	macl %d6,%a3,>>,%acc1
+    5d60:	a646 0e10      	macl %d6,%a3,>>,%acc2
+    5d64:	a6c6 0a00      	macl %d6,%a3,<<,%acc1
+    5d68:	a646 0a10      	macl %d6,%a3,<<,%acc2
+    5d6c:	a6c6 0e00      	macl %d6,%a3,>>,%acc1
+    5d70:	a646 0e10      	macl %d6,%a3,>>,%acc2
+    5d74:	a886 0800      	macl %d6,%d4,%acc1
+    5d78:	a806 0810      	macl %d6,%d4,%acc2
+    5d7c:	a886 0a00      	macl %d6,%d4,<<,%acc1
+    5d80:	a806 0a10      	macl %d6,%d4,<<,%acc2
+    5d84:	a886 0e00      	macl %d6,%d4,>>,%acc1
+    5d88:	a806 0e10      	macl %d6,%d4,>>,%acc2
+    5d8c:	a886 0a00      	macl %d6,%d4,<<,%acc1
+    5d90:	a806 0a10      	macl %d6,%d4,<<,%acc2
+    5d94:	a886 0e00      	macl %d6,%d4,>>,%acc1
+    5d98:	a806 0e10      	macl %d6,%d4,>>,%acc2
+    5d9c:	a213 b809      	macl %a1,%a3,%a3@,%d1,%acc1
+    5da0:	a293 b819      	macl %a1,%a3,%a3@,%d1,%acc2
+    5da4:	a653 b809      	macl %a1,%a3,%a3@,%a3,%acc1
+    5da8:	a6d3 b819      	macl %a1,%a3,%a3@,%a3,%acc2
+    5dac:	a413 b809      	macl %a1,%a3,%a3@,%d2,%acc1
+    5db0:	a493 b819      	macl %a1,%a3,%a3@,%d2,%acc2
+    5db4:	ae53 b809      	macl %a1,%a3,%a3@,%sp,%acc1
+    5db8:	aed3 b819      	macl %a1,%a3,%a3@,%sp,%acc2
+    5dbc:	a213 b829      	macl %a1,%a3,%a3@&,%d1,%acc1
+    5dc0:	a293 b839      	macl %a1,%a3,%a3@&,%d1,%acc2
+    5dc4:	a653 b829      	macl %a1,%a3,%a3@&,%a3,%acc1
+    5dc8:	a6d3 b839      	macl %a1,%a3,%a3@&,%a3,%acc2
+    5dcc:	a413 b829      	macl %a1,%a3,%a3@&,%d2,%acc1
+    5dd0:	a493 b839      	macl %a1,%a3,%a3@&,%d2,%acc2
+    5dd4:	ae53 b829      	macl %a1,%a3,%a3@&,%sp,%acc1
+    5dd8:	aed3 b839      	macl %a1,%a3,%a3@&,%sp,%acc2
+    5ddc:	a21a b809      	macl %a1,%a3,%a2@\+,%d1,%acc1
+    5de0:	a29a b819      	macl %a1,%a3,%a2@\+,%d1,%acc2
+    5de4:	a65a b809      	macl %a1,%a3,%a2@\+,%a3,%acc1
+    5de8:	a6da b819      	macl %a1,%a3,%a2@\+,%a3,%acc2
+    5dec:	a41a b809      	macl %a1,%a3,%a2@\+,%d2,%acc1
+    5df0:	a49a b819      	macl %a1,%a3,%a2@\+,%d2,%acc2
+    5df4:	ae5a b809      	macl %a1,%a3,%a2@\+,%sp,%acc1
+    5df8:	aeda b819      	macl %a1,%a3,%a2@\+,%sp,%acc2
+    5dfc:	a21a b829      	macl %a1,%a3,%a2@\+&,%d1,%acc1
+    5e00:	a29a b839      	macl %a1,%a3,%a2@\+&,%d1,%acc2
+    5e04:	a65a b829      	macl %a1,%a3,%a2@\+&,%a3,%acc1
+    5e08:	a6da b839      	macl %a1,%a3,%a2@\+&,%a3,%acc2
+    5e0c:	a41a b829      	macl %a1,%a3,%a2@\+&,%d2,%acc1
+    5e10:	a49a b839      	macl %a1,%a3,%a2@\+&,%d2,%acc2
+    5e14:	ae5a b829      	macl %a1,%a3,%a2@\+&,%sp,%acc1
+    5e18:	aeda b839      	macl %a1,%a3,%a2@\+&,%sp,%acc2
+    5e1c:	a22e b809 000a 	macl %a1,%a3,%fp@\(10\),%d1,%acc1
+    5e22:	a2ae b819 000a 	macl %a1,%a3,%fp@\(10\),%d1,%acc2
+    5e28:	a66e b809 000a 	macl %a1,%a3,%fp@\(10\),%a3,%acc1
+    5e2e:	a6ee b819 000a 	macl %a1,%a3,%fp@\(10\),%a3,%acc2
+    5e34:	a42e b809 000a 	macl %a1,%a3,%fp@\(10\),%d2,%acc1
+    5e3a:	a4ae b819 000a 	macl %a1,%a3,%fp@\(10\),%d2,%acc2
+    5e40:	ae6e b809 000a 	macl %a1,%a3,%fp@\(10\),%sp,%acc1
+    5e46:	aeee b819 000a 	macl %a1,%a3,%fp@\(10\),%sp,%acc2
+    5e4c:	a22e b829 000a 	macl %a1,%a3,%fp@\(10\)&,%d1,%acc1
+    5e52:	a2ae b839 000a 	macl %a1,%a3,%fp@\(10\)&,%d1,%acc2
+    5e58:	a66e b829 000a 	macl %a1,%a3,%fp@\(10\)&,%a3,%acc1
+    5e5e:	a6ee b839 000a 	macl %a1,%a3,%fp@\(10\)&,%a3,%acc2
+    5e64:	a42e b829 000a 	macl %a1,%a3,%fp@\(10\)&,%d2,%acc1
+    5e6a:	a4ae b839 000a 	macl %a1,%a3,%fp@\(10\)&,%d2,%acc2
+    5e70:	ae6e b829 000a 	macl %a1,%a3,%fp@\(10\)&,%sp,%acc1
+    5e76:	aeee b839 000a 	macl %a1,%a3,%fp@\(10\)&,%sp,%acc2
+    5e7c:	a221 b809      	macl %a1,%a3,%a1@-,%d1,%acc1
+    5e80:	a2a1 b819      	macl %a1,%a3,%a1@-,%d1,%acc2
+    5e84:	a661 b809      	macl %a1,%a3,%a1@-,%a3,%acc1
+    5e88:	a6e1 b819      	macl %a1,%a3,%a1@-,%a3,%acc2
+    5e8c:	a421 b809      	macl %a1,%a3,%a1@-,%d2,%acc1
+    5e90:	a4a1 b819      	macl %a1,%a3,%a1@-,%d2,%acc2
+    5e94:	ae61 b809      	macl %a1,%a3,%a1@-,%sp,%acc1
+    5e98:	aee1 b819      	macl %a1,%a3,%a1@-,%sp,%acc2
+    5e9c:	a221 b829      	macl %a1,%a3,%a1@-&,%d1,%acc1
+    5ea0:	a2a1 b839      	macl %a1,%a3,%a1@-&,%d1,%acc2
+    5ea4:	a661 b829      	macl %a1,%a3,%a1@-&,%a3,%acc1
+    5ea8:	a6e1 b839      	macl %a1,%a3,%a1@-&,%a3,%acc2
+    5eac:	a421 b829      	macl %a1,%a3,%a1@-&,%d2,%acc1
+    5eb0:	a4a1 b839      	macl %a1,%a3,%a1@-&,%d2,%acc2
+    5eb4:	ae61 b829      	macl %a1,%a3,%a1@-&,%sp,%acc1
+    5eb8:	aee1 b839      	macl %a1,%a3,%a1@-&,%sp,%acc2
+    5ebc:	a213 ba09      	macl %a1,%a3,<<,%a3@,%d1,%acc1
+    5ec0:	a293 ba19      	macl %a1,%a3,<<,%a3@,%d1,%acc2
+    5ec4:	a653 ba09      	macl %a1,%a3,<<,%a3@,%a3,%acc1
+    5ec8:	a6d3 ba19      	macl %a1,%a3,<<,%a3@,%a3,%acc2
+    5ecc:	a413 ba09      	macl %a1,%a3,<<,%a3@,%d2,%acc1
+    5ed0:	a493 ba19      	macl %a1,%a3,<<,%a3@,%d2,%acc2
+    5ed4:	ae53 ba09      	macl %a1,%a3,<<,%a3@,%sp,%acc1
+    5ed8:	aed3 ba19      	macl %a1,%a3,<<,%a3@,%sp,%acc2
+    5edc:	a213 ba29      	macl %a1,%a3,<<,%a3@&,%d1,%acc1
+    5ee0:	a293 ba39      	macl %a1,%a3,<<,%a3@&,%d1,%acc2
+    5ee4:	a653 ba29      	macl %a1,%a3,<<,%a3@&,%a3,%acc1
+    5ee8:	a6d3 ba39      	macl %a1,%a3,<<,%a3@&,%a3,%acc2
+    5eec:	a413 ba29      	macl %a1,%a3,<<,%a3@&,%d2,%acc1
+    5ef0:	a493 ba39      	macl %a1,%a3,<<,%a3@&,%d2,%acc2
+    5ef4:	ae53 ba29      	macl %a1,%a3,<<,%a3@&,%sp,%acc1
+    5ef8:	aed3 ba39      	macl %a1,%a3,<<,%a3@&,%sp,%acc2
+    5efc:	a21a ba09      	macl %a1,%a3,<<,%a2@\+,%d1,%acc1
+    5f00:	a29a ba19      	macl %a1,%a3,<<,%a2@\+,%d1,%acc2
+    5f04:	a65a ba09      	macl %a1,%a3,<<,%a2@\+,%a3,%acc1
+    5f08:	a6da ba19      	macl %a1,%a3,<<,%a2@\+,%a3,%acc2
+    5f0c:	a41a ba09      	macl %a1,%a3,<<,%a2@\+,%d2,%acc1
+    5f10:	a49a ba19      	macl %a1,%a3,<<,%a2@\+,%d2,%acc2
+    5f14:	ae5a ba09      	macl %a1,%a3,<<,%a2@\+,%sp,%acc1
+    5f18:	aeda ba19      	macl %a1,%a3,<<,%a2@\+,%sp,%acc2
+    5f1c:	a21a ba29      	macl %a1,%a3,<<,%a2@\+&,%d1,%acc1
+    5f20:	a29a ba39      	macl %a1,%a3,<<,%a2@\+&,%d1,%acc2
+    5f24:	a65a ba29      	macl %a1,%a3,<<,%a2@\+&,%a3,%acc1
+    5f28:	a6da ba39      	macl %a1,%a3,<<,%a2@\+&,%a3,%acc2
+    5f2c:	a41a ba29      	macl %a1,%a3,<<,%a2@\+&,%d2,%acc1
+    5f30:	a49a ba39      	macl %a1,%a3,<<,%a2@\+&,%d2,%acc2
+    5f34:	ae5a ba29      	macl %a1,%a3,<<,%a2@\+&,%sp,%acc1
+    5f38:	aeda ba39      	macl %a1,%a3,<<,%a2@\+&,%sp,%acc2
+    5f3c:	a22e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1,%acc1
+    5f42:	a2ae ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1,%acc2
+    5f48:	a66e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3,%acc1
+    5f4e:	a6ee ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3,%acc2
+    5f54:	a42e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2,%acc1
+    5f5a:	a4ae ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2,%acc2
+    5f60:	ae6e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp,%acc1
+    5f66:	aeee ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp,%acc2
+    5f6c:	a22e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1,%acc1
+    5f72:	a2ae ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1,%acc2
+    5f78:	a66e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3,%acc1
+    5f7e:	a6ee ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3,%acc2
+    5f84:	a42e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2,%acc1
+    5f8a:	a4ae ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2,%acc2
+    5f90:	ae6e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp,%acc1
+    5f96:	aeee ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp,%acc2
+    5f9c:	a221 ba09      	macl %a1,%a3,<<,%a1@-,%d1,%acc1
+    5fa0:	a2a1 ba19      	macl %a1,%a3,<<,%a1@-,%d1,%acc2
+    5fa4:	a661 ba09      	macl %a1,%a3,<<,%a1@-,%a3,%acc1
+    5fa8:	a6e1 ba19      	macl %a1,%a3,<<,%a1@-,%a3,%acc2
+    5fac:	a421 ba09      	macl %a1,%a3,<<,%a1@-,%d2,%acc1
+    5fb0:	a4a1 ba19      	macl %a1,%a3,<<,%a1@-,%d2,%acc2
+    5fb4:	ae61 ba09      	macl %a1,%a3,<<,%a1@-,%sp,%acc1
+    5fb8:	aee1 ba19      	macl %a1,%a3,<<,%a1@-,%sp,%acc2
+    5fbc:	a221 ba29      	macl %a1,%a3,<<,%a1@-&,%d1,%acc1
+    5fc0:	a2a1 ba39      	macl %a1,%a3,<<,%a1@-&,%d1,%acc2
+    5fc4:	a661 ba29      	macl %a1,%a3,<<,%a1@-&,%a3,%acc1
+    5fc8:	a6e1 ba39      	macl %a1,%a3,<<,%a1@-&,%a3,%acc2
+    5fcc:	a421 ba29      	macl %a1,%a3,<<,%a1@-&,%d2,%acc1
+    5fd0:	a4a1 ba39      	macl %a1,%a3,<<,%a1@-&,%d2,%acc2
+    5fd4:	ae61 ba29      	macl %a1,%a3,<<,%a1@-&,%sp,%acc1
+    5fd8:	aee1 ba39      	macl %a1,%a3,<<,%a1@-&,%sp,%acc2
+    5fdc:	a213 be09      	macl %a1,%a3,>>,%a3@,%d1,%acc1
+    5fe0:	a293 be19      	macl %a1,%a3,>>,%a3@,%d1,%acc2
+    5fe4:	a653 be09      	macl %a1,%a3,>>,%a3@,%a3,%acc1
+    5fe8:	a6d3 be19      	macl %a1,%a3,>>,%a3@,%a3,%acc2
+    5fec:	a413 be09      	macl %a1,%a3,>>,%a3@,%d2,%acc1
+    5ff0:	a493 be19      	macl %a1,%a3,>>,%a3@,%d2,%acc2
+    5ff4:	ae53 be09      	macl %a1,%a3,>>,%a3@,%sp,%acc1
+    5ff8:	aed3 be19      	macl %a1,%a3,>>,%a3@,%sp,%acc2
+    5ffc:	a213 be29      	macl %a1,%a3,>>,%a3@&,%d1,%acc1
+    6000:	a293 be39      	macl %a1,%a3,>>,%a3@&,%d1,%acc2
+    6004:	a653 be29      	macl %a1,%a3,>>,%a3@&,%a3,%acc1
+    6008:	a6d3 be39      	macl %a1,%a3,>>,%a3@&,%a3,%acc2
+    600c:	a413 be29      	macl %a1,%a3,>>,%a3@&,%d2,%acc1
+    6010:	a493 be39      	macl %a1,%a3,>>,%a3@&,%d2,%acc2
+    6014:	ae53 be29      	macl %a1,%a3,>>,%a3@&,%sp,%acc1
+    6018:	aed3 be39      	macl %a1,%a3,>>,%a3@&,%sp,%acc2
+    601c:	a21a be09      	macl %a1,%a3,>>,%a2@\+,%d1,%acc1
+    6020:	a29a be19      	macl %a1,%a3,>>,%a2@\+,%d1,%acc2
+    6024:	a65a be09      	macl %a1,%a3,>>,%a2@\+,%a3,%acc1
+    6028:	a6da be19      	macl %a1,%a3,>>,%a2@\+,%a3,%acc2
+    602c:	a41a be09      	macl %a1,%a3,>>,%a2@\+,%d2,%acc1
+    6030:	a49a be19      	macl %a1,%a3,>>,%a2@\+,%d2,%acc2
+    6034:	ae5a be09      	macl %a1,%a3,>>,%a2@\+,%sp,%acc1
+    6038:	aeda be19      	macl %a1,%a3,>>,%a2@\+,%sp,%acc2
+    603c:	a21a be29      	macl %a1,%a3,>>,%a2@\+&,%d1,%acc1
+    6040:	a29a be39      	macl %a1,%a3,>>,%a2@\+&,%d1,%acc2
+    6044:	a65a be29      	macl %a1,%a3,>>,%a2@\+&,%a3,%acc1
+    6048:	a6da be39      	macl %a1,%a3,>>,%a2@\+&,%a3,%acc2
+    604c:	a41a be29      	macl %a1,%a3,>>,%a2@\+&,%d2,%acc1
+    6050:	a49a be39      	macl %a1,%a3,>>,%a2@\+&,%d2,%acc2
+    6054:	ae5a be29      	macl %a1,%a3,>>,%a2@\+&,%sp,%acc1
+    6058:	aeda be39      	macl %a1,%a3,>>,%a2@\+&,%sp,%acc2
+    605c:	a22e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1,%acc1
+    6062:	a2ae be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1,%acc2
+    6068:	a66e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3,%acc1
+    606e:	a6ee be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3,%acc2
+    6074:	a42e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2,%acc1
+    607a:	a4ae be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2,%acc2
+    6080:	ae6e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp,%acc1
+    6086:	aeee be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp,%acc2
+    608c:	a22e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1,%acc1
+    6092:	a2ae be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1,%acc2
+    6098:	a66e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3,%acc1
+    609e:	a6ee be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3,%acc2
+    60a4:	a42e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2,%acc1
+    60aa:	a4ae be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2,%acc2
+    60b0:	ae6e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp,%acc1
+    60b6:	aeee be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp,%acc2
+    60bc:	a221 be09      	macl %a1,%a3,>>,%a1@-,%d1,%acc1
+    60c0:	a2a1 be19      	macl %a1,%a3,>>,%a1@-,%d1,%acc2
+    60c4:	a661 be09      	macl %a1,%a3,>>,%a1@-,%a3,%acc1
+    60c8:	a6e1 be19      	macl %a1,%a3,>>,%a1@-,%a3,%acc2
+    60cc:	a421 be09      	macl %a1,%a3,>>,%a1@-,%d2,%acc1
+    60d0:	a4a1 be19      	macl %a1,%a3,>>,%a1@-,%d2,%acc2
+    60d4:	ae61 be09      	macl %a1,%a3,>>,%a1@-,%sp,%acc1
+    60d8:	aee1 be19      	macl %a1,%a3,>>,%a1@-,%sp,%acc2
+    60dc:	a221 be29      	macl %a1,%a3,>>,%a1@-&,%d1,%acc1
+    60e0:	a2a1 be39      	macl %a1,%a3,>>,%a1@-&,%d1,%acc2
+    60e4:	a661 be29      	macl %a1,%a3,>>,%a1@-&,%a3,%acc1
+    60e8:	a6e1 be39      	macl %a1,%a3,>>,%a1@-&,%a3,%acc2
+    60ec:	a421 be29      	macl %a1,%a3,>>,%a1@-&,%d2,%acc1
+    60f0:	a4a1 be39      	macl %a1,%a3,>>,%a1@-&,%d2,%acc2
+    60f4:	ae61 be29      	macl %a1,%a3,>>,%a1@-&,%sp,%acc1
+    60f8:	aee1 be39      	macl %a1,%a3,>>,%a1@-&,%sp,%acc2
+    60fc:	a213 ba09      	macl %a1,%a3,<<,%a3@,%d1,%acc1
+    6100:	a293 ba19      	macl %a1,%a3,<<,%a3@,%d1,%acc2
+    6104:	a653 ba09      	macl %a1,%a3,<<,%a3@,%a3,%acc1
+    6108:	a6d3 ba19      	macl %a1,%a3,<<,%a3@,%a3,%acc2
+    610c:	a413 ba09      	macl %a1,%a3,<<,%a3@,%d2,%acc1
+    6110:	a493 ba19      	macl %a1,%a3,<<,%a3@,%d2,%acc2
+    6114:	ae53 ba09      	macl %a1,%a3,<<,%a3@,%sp,%acc1
+    6118:	aed3 ba19      	macl %a1,%a3,<<,%a3@,%sp,%acc2
+    611c:	a213 ba29      	macl %a1,%a3,<<,%a3@&,%d1,%acc1
+    6120:	a293 ba39      	macl %a1,%a3,<<,%a3@&,%d1,%acc2
+    6124:	a653 ba29      	macl %a1,%a3,<<,%a3@&,%a3,%acc1
+    6128:	a6d3 ba39      	macl %a1,%a3,<<,%a3@&,%a3,%acc2
+    612c:	a413 ba29      	macl %a1,%a3,<<,%a3@&,%d2,%acc1
+    6130:	a493 ba39      	macl %a1,%a3,<<,%a3@&,%d2,%acc2
+    6134:	ae53 ba29      	macl %a1,%a3,<<,%a3@&,%sp,%acc1
+    6138:	aed3 ba39      	macl %a1,%a3,<<,%a3@&,%sp,%acc2
+    613c:	a21a ba09      	macl %a1,%a3,<<,%a2@\+,%d1,%acc1
+    6140:	a29a ba19      	macl %a1,%a3,<<,%a2@\+,%d1,%acc2
+    6144:	a65a ba09      	macl %a1,%a3,<<,%a2@\+,%a3,%acc1
+    6148:	a6da ba19      	macl %a1,%a3,<<,%a2@\+,%a3,%acc2
+    614c:	a41a ba09      	macl %a1,%a3,<<,%a2@\+,%d2,%acc1
+    6150:	a49a ba19      	macl %a1,%a3,<<,%a2@\+,%d2,%acc2
+    6154:	ae5a ba09      	macl %a1,%a3,<<,%a2@\+,%sp,%acc1
+    6158:	aeda ba19      	macl %a1,%a3,<<,%a2@\+,%sp,%acc2
+    615c:	a21a ba29      	macl %a1,%a3,<<,%a2@\+&,%d1,%acc1
+    6160:	a29a ba39      	macl %a1,%a3,<<,%a2@\+&,%d1,%acc2
+    6164:	a65a ba29      	macl %a1,%a3,<<,%a2@\+&,%a3,%acc1
+    6168:	a6da ba39      	macl %a1,%a3,<<,%a2@\+&,%a3,%acc2
+    616c:	a41a ba29      	macl %a1,%a3,<<,%a2@\+&,%d2,%acc1
+    6170:	a49a ba39      	macl %a1,%a3,<<,%a2@\+&,%d2,%acc2
+    6174:	ae5a ba29      	macl %a1,%a3,<<,%a2@\+&,%sp,%acc1
+    6178:	aeda ba39      	macl %a1,%a3,<<,%a2@\+&,%sp,%acc2
+    617c:	a22e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1,%acc1
+    6182:	a2ae ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1,%acc2
+    6188:	a66e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3,%acc1
+    618e:	a6ee ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3,%acc2
+    6194:	a42e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2,%acc1
+    619a:	a4ae ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2,%acc2
+    61a0:	ae6e ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp,%acc1
+    61a6:	aeee ba19 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp,%acc2
+    61ac:	a22e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1,%acc1
+    61b2:	a2ae ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1,%acc2
+    61b8:	a66e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3,%acc1
+    61be:	a6ee ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3,%acc2
+    61c4:	a42e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2,%acc1
+    61ca:	a4ae ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2,%acc2
+    61d0:	ae6e ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp,%acc1
+    61d6:	aeee ba39 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp,%acc2
+    61dc:	a221 ba09      	macl %a1,%a3,<<,%a1@-,%d1,%acc1
+    61e0:	a2a1 ba19      	macl %a1,%a3,<<,%a1@-,%d1,%acc2
+    61e4:	a661 ba09      	macl %a1,%a3,<<,%a1@-,%a3,%acc1
+    61e8:	a6e1 ba19      	macl %a1,%a3,<<,%a1@-,%a3,%acc2
+    61ec:	a421 ba09      	macl %a1,%a3,<<,%a1@-,%d2,%acc1
+    61f0:	a4a1 ba19      	macl %a1,%a3,<<,%a1@-,%d2,%acc2
+    61f4:	ae61 ba09      	macl %a1,%a3,<<,%a1@-,%sp,%acc1
+    61f8:	aee1 ba19      	macl %a1,%a3,<<,%a1@-,%sp,%acc2
+    61fc:	a221 ba29      	macl %a1,%a3,<<,%a1@-&,%d1,%acc1
+    6200:	a2a1 ba39      	macl %a1,%a3,<<,%a1@-&,%d1,%acc2
+    6204:	a661 ba29      	macl %a1,%a3,<<,%a1@-&,%a3,%acc1
+    6208:	a6e1 ba39      	macl %a1,%a3,<<,%a1@-&,%a3,%acc2
+    620c:	a421 ba29      	macl %a1,%a3,<<,%a1@-&,%d2,%acc1
+    6210:	a4a1 ba39      	macl %a1,%a3,<<,%a1@-&,%d2,%acc2
+    6214:	ae61 ba29      	macl %a1,%a3,<<,%a1@-&,%sp,%acc1
+    6218:	aee1 ba39      	macl %a1,%a3,<<,%a1@-&,%sp,%acc2
+    621c:	a213 be09      	macl %a1,%a3,>>,%a3@,%d1,%acc1
+    6220:	a293 be19      	macl %a1,%a3,>>,%a3@,%d1,%acc2
+    6224:	a653 be09      	macl %a1,%a3,>>,%a3@,%a3,%acc1
+    6228:	a6d3 be19      	macl %a1,%a3,>>,%a3@,%a3,%acc2
+    622c:	a413 be09      	macl %a1,%a3,>>,%a3@,%d2,%acc1
+    6230:	a493 be19      	macl %a1,%a3,>>,%a3@,%d2,%acc2
+    6234:	ae53 be09      	macl %a1,%a3,>>,%a3@,%sp,%acc1
+    6238:	aed3 be19      	macl %a1,%a3,>>,%a3@,%sp,%acc2
+    623c:	a213 be29      	macl %a1,%a3,>>,%a3@&,%d1,%acc1
+    6240:	a293 be39      	macl %a1,%a3,>>,%a3@&,%d1,%acc2
+    6244:	a653 be29      	macl %a1,%a3,>>,%a3@&,%a3,%acc1
+    6248:	a6d3 be39      	macl %a1,%a3,>>,%a3@&,%a3,%acc2
+    624c:	a413 be29      	macl %a1,%a3,>>,%a3@&,%d2,%acc1
+    6250:	a493 be39      	macl %a1,%a3,>>,%a3@&,%d2,%acc2
+    6254:	ae53 be29      	macl %a1,%a3,>>,%a3@&,%sp,%acc1
+    6258:	aed3 be39      	macl %a1,%a3,>>,%a3@&,%sp,%acc2
+    625c:	a21a be09      	macl %a1,%a3,>>,%a2@\+,%d1,%acc1
+    6260:	a29a be19      	macl %a1,%a3,>>,%a2@\+,%d1,%acc2
+    6264:	a65a be09      	macl %a1,%a3,>>,%a2@\+,%a3,%acc1
+    6268:	a6da be19      	macl %a1,%a3,>>,%a2@\+,%a3,%acc2
+    626c:	a41a be09      	macl %a1,%a3,>>,%a2@\+,%d2,%acc1
+    6270:	a49a be19      	macl %a1,%a3,>>,%a2@\+,%d2,%acc2
+    6274:	ae5a be09      	macl %a1,%a3,>>,%a2@\+,%sp,%acc1
+    6278:	aeda be19      	macl %a1,%a3,>>,%a2@\+,%sp,%acc2
+    627c:	a21a be29      	macl %a1,%a3,>>,%a2@\+&,%d1,%acc1
+    6280:	a29a be39      	macl %a1,%a3,>>,%a2@\+&,%d1,%acc2
+    6284:	a65a be29      	macl %a1,%a3,>>,%a2@\+&,%a3,%acc1
+    6288:	a6da be39      	macl %a1,%a3,>>,%a2@\+&,%a3,%acc2
+    628c:	a41a be29      	macl %a1,%a3,>>,%a2@\+&,%d2,%acc1
+    6290:	a49a be39      	macl %a1,%a3,>>,%a2@\+&,%d2,%acc2
+    6294:	ae5a be29      	macl %a1,%a3,>>,%a2@\+&,%sp,%acc1
+    6298:	aeda be39      	macl %a1,%a3,>>,%a2@\+&,%sp,%acc2
+    629c:	a22e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1,%acc1
+    62a2:	a2ae be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1,%acc2
+    62a8:	a66e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3,%acc1
+    62ae:	a6ee be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3,%acc2
+    62b4:	a42e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2,%acc1
+    62ba:	a4ae be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2,%acc2
+    62c0:	ae6e be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp,%acc1
+    62c6:	aeee be19 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp,%acc2
+    62cc:	a22e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1,%acc1
+    62d2:	a2ae be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1,%acc2
+    62d8:	a66e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3,%acc1
+    62de:	a6ee be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3,%acc2
+    62e4:	a42e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2,%acc1
+    62ea:	a4ae be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2,%acc2
+    62f0:	ae6e be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp,%acc1
+    62f6:	aeee be39 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp,%acc2
+    62fc:	a221 be09      	macl %a1,%a3,>>,%a1@-,%d1,%acc1
+    6300:	a2a1 be19      	macl %a1,%a3,>>,%a1@-,%d1,%acc2
+    6304:	a661 be09      	macl %a1,%a3,>>,%a1@-,%a3,%acc1
+    6308:	a6e1 be19      	macl %a1,%a3,>>,%a1@-,%a3,%acc2
+    630c:	a421 be09      	macl %a1,%a3,>>,%a1@-,%d2,%acc1
+    6310:	a4a1 be19      	macl %a1,%a3,>>,%a1@-,%d2,%acc2
+    6314:	ae61 be09      	macl %a1,%a3,>>,%a1@-,%sp,%acc1
+    6318:	aee1 be19      	macl %a1,%a3,>>,%a1@-,%sp,%acc2
+    631c:	a221 be29      	macl %a1,%a3,>>,%a1@-&,%d1,%acc1
+    6320:	a2a1 be39      	macl %a1,%a3,>>,%a1@-&,%d1,%acc2
+    6324:	a661 be29      	macl %a1,%a3,>>,%a1@-&,%a3,%acc1
+    6328:	a6e1 be39      	macl %a1,%a3,>>,%a1@-&,%a3,%acc2
+    632c:	a421 be29      	macl %a1,%a3,>>,%a1@-&,%d2,%acc1
+    6330:	a4a1 be39      	macl %a1,%a3,>>,%a1@-&,%d2,%acc2
+    6334:	ae61 be29      	macl %a1,%a3,>>,%a1@-&,%sp,%acc1
+    6338:	aee1 be39      	macl %a1,%a3,>>,%a1@-&,%sp,%acc2
+    633c:	a213 4809      	macl %a1,%d4,%a3@,%d1,%acc1
+    6340:	a293 4819      	macl %a1,%d4,%a3@,%d1,%acc2
+    6344:	a653 4809      	macl %a1,%d4,%a3@,%a3,%acc1
+    6348:	a6d3 4819      	macl %a1,%d4,%a3@,%a3,%acc2
+    634c:	a413 4809      	macl %a1,%d4,%a3@,%d2,%acc1
+    6350:	a493 4819      	macl %a1,%d4,%a3@,%d2,%acc2
+    6354:	ae53 4809      	macl %a1,%d4,%a3@,%sp,%acc1
+    6358:	aed3 4819      	macl %a1,%d4,%a3@,%sp,%acc2
+    635c:	a213 4829      	macl %a1,%d4,%a3@&,%d1,%acc1
+    6360:	a293 4839      	macl %a1,%d4,%a3@&,%d1,%acc2
+    6364:	a653 4829      	macl %a1,%d4,%a3@&,%a3,%acc1
+    6368:	a6d3 4839      	macl %a1,%d4,%a3@&,%a3,%acc2
+    636c:	a413 4829      	macl %a1,%d4,%a3@&,%d2,%acc1
+    6370:	a493 4839      	macl %a1,%d4,%a3@&,%d2,%acc2
+    6374:	ae53 4829      	macl %a1,%d4,%a3@&,%sp,%acc1
+    6378:	aed3 4839      	macl %a1,%d4,%a3@&,%sp,%acc2
+    637c:	a21a 4809      	macl %a1,%d4,%a2@\+,%d1,%acc1
+    6380:	a29a 4819      	macl %a1,%d4,%a2@\+,%d1,%acc2
+    6384:	a65a 4809      	macl %a1,%d4,%a2@\+,%a3,%acc1
+    6388:	a6da 4819      	macl %a1,%d4,%a2@\+,%a3,%acc2
+    638c:	a41a 4809      	macl %a1,%d4,%a2@\+,%d2,%acc1
+    6390:	a49a 4819      	macl %a1,%d4,%a2@\+,%d2,%acc2
+    6394:	ae5a 4809      	macl %a1,%d4,%a2@\+,%sp,%acc1
+    6398:	aeda 4819      	macl %a1,%d4,%a2@\+,%sp,%acc2
+    639c:	a21a 4829      	macl %a1,%d4,%a2@\+&,%d1,%acc1
+    63a0:	a29a 4839      	macl %a1,%d4,%a2@\+&,%d1,%acc2
+    63a4:	a65a 4829      	macl %a1,%d4,%a2@\+&,%a3,%acc1
+    63a8:	a6da 4839      	macl %a1,%d4,%a2@\+&,%a3,%acc2
+    63ac:	a41a 4829      	macl %a1,%d4,%a2@\+&,%d2,%acc1
+    63b0:	a49a 4839      	macl %a1,%d4,%a2@\+&,%d2,%acc2
+    63b4:	ae5a 4829      	macl %a1,%d4,%a2@\+&,%sp,%acc1
+    63b8:	aeda 4839      	macl %a1,%d4,%a2@\+&,%sp,%acc2
+    63bc:	a22e 4809 000a 	macl %a1,%d4,%fp@\(10\),%d1,%acc1
+    63c2:	a2ae 4819 000a 	macl %a1,%d4,%fp@\(10\),%d1,%acc2
+    63c8:	a66e 4809 000a 	macl %a1,%d4,%fp@\(10\),%a3,%acc1
+    63ce:	a6ee 4819 000a 	macl %a1,%d4,%fp@\(10\),%a3,%acc2
+    63d4:	a42e 4809 000a 	macl %a1,%d4,%fp@\(10\),%d2,%acc1
+    63da:	a4ae 4819 000a 	macl %a1,%d4,%fp@\(10\),%d2,%acc2
+    63e0:	ae6e 4809 000a 	macl %a1,%d4,%fp@\(10\),%sp,%acc1
+    63e6:	aeee 4819 000a 	macl %a1,%d4,%fp@\(10\),%sp,%acc2
+    63ec:	a22e 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%d1,%acc1
+    63f2:	a2ae 4839 000a 	macl %a1,%d4,%fp@\(10\)&,%d1,%acc2
+    63f8:	a66e 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%a3,%acc1
+    63fe:	a6ee 4839 000a 	macl %a1,%d4,%fp@\(10\)&,%a3,%acc2
+    6404:	a42e 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%d2,%acc1
+    640a:	a4ae 4839 000a 	macl %a1,%d4,%fp@\(10\)&,%d2,%acc2
+    6410:	ae6e 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%sp,%acc1
+    6416:	aeee 4839 000a 	macl %a1,%d4,%fp@\(10\)&,%sp,%acc2
+    641c:	a221 4809      	macl %a1,%d4,%a1@-,%d1,%acc1
+    6420:	a2a1 4819      	macl %a1,%d4,%a1@-,%d1,%acc2
+    6424:	a661 4809      	macl %a1,%d4,%a1@-,%a3,%acc1
+    6428:	a6e1 4819      	macl %a1,%d4,%a1@-,%a3,%acc2
+    642c:	a421 4809      	macl %a1,%d4,%a1@-,%d2,%acc1
+    6430:	a4a1 4819      	macl %a1,%d4,%a1@-,%d2,%acc2
+    6434:	ae61 4809      	macl %a1,%d4,%a1@-,%sp,%acc1
+    6438:	aee1 4819      	macl %a1,%d4,%a1@-,%sp,%acc2
+    643c:	a221 4829      	macl %a1,%d4,%a1@-&,%d1,%acc1
+    6440:	a2a1 4839      	macl %a1,%d4,%a1@-&,%d1,%acc2
+    6444:	a661 4829      	macl %a1,%d4,%a1@-&,%a3,%acc1
+    6448:	a6e1 4839      	macl %a1,%d4,%a1@-&,%a3,%acc2
+    644c:	a421 4829      	macl %a1,%d4,%a1@-&,%d2,%acc1
+    6450:	a4a1 4839      	macl %a1,%d4,%a1@-&,%d2,%acc2
+    6454:	ae61 4829      	macl %a1,%d4,%a1@-&,%sp,%acc1
+    6458:	aee1 4839      	macl %a1,%d4,%a1@-&,%sp,%acc2
+    645c:	a213 4a09      	macl %a1,%d4,<<,%a3@,%d1,%acc1
+    6460:	a293 4a19      	macl %a1,%d4,<<,%a3@,%d1,%acc2
+    6464:	a653 4a09      	macl %a1,%d4,<<,%a3@,%a3,%acc1
+    6468:	a6d3 4a19      	macl %a1,%d4,<<,%a3@,%a3,%acc2
+    646c:	a413 4a09      	macl %a1,%d4,<<,%a3@,%d2,%acc1
+    6470:	a493 4a19      	macl %a1,%d4,<<,%a3@,%d2,%acc2
+    6474:	ae53 4a09      	macl %a1,%d4,<<,%a3@,%sp,%acc1
+    6478:	aed3 4a19      	macl %a1,%d4,<<,%a3@,%sp,%acc2
+    647c:	a213 4a29      	macl %a1,%d4,<<,%a3@&,%d1,%acc1
+    6480:	a293 4a39      	macl %a1,%d4,<<,%a3@&,%d1,%acc2
+    6484:	a653 4a29      	macl %a1,%d4,<<,%a3@&,%a3,%acc1
+    6488:	a6d3 4a39      	macl %a1,%d4,<<,%a3@&,%a3,%acc2
+    648c:	a413 4a29      	macl %a1,%d4,<<,%a3@&,%d2,%acc1
+    6490:	a493 4a39      	macl %a1,%d4,<<,%a3@&,%d2,%acc2
+    6494:	ae53 4a29      	macl %a1,%d4,<<,%a3@&,%sp,%acc1
+    6498:	aed3 4a39      	macl %a1,%d4,<<,%a3@&,%sp,%acc2
+    649c:	a21a 4a09      	macl %a1,%d4,<<,%a2@\+,%d1,%acc1
+    64a0:	a29a 4a19      	macl %a1,%d4,<<,%a2@\+,%d1,%acc2
+    64a4:	a65a 4a09      	macl %a1,%d4,<<,%a2@\+,%a3,%acc1
+    64a8:	a6da 4a19      	macl %a1,%d4,<<,%a2@\+,%a3,%acc2
+    64ac:	a41a 4a09      	macl %a1,%d4,<<,%a2@\+,%d2,%acc1
+    64b0:	a49a 4a19      	macl %a1,%d4,<<,%a2@\+,%d2,%acc2
+    64b4:	ae5a 4a09      	macl %a1,%d4,<<,%a2@\+,%sp,%acc1
+    64b8:	aeda 4a19      	macl %a1,%d4,<<,%a2@\+,%sp,%acc2
+    64bc:	a21a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d1,%acc1
+    64c0:	a29a 4a39      	macl %a1,%d4,<<,%a2@\+&,%d1,%acc2
+    64c4:	a65a 4a29      	macl %a1,%d4,<<,%a2@\+&,%a3,%acc1
+    64c8:	a6da 4a39      	macl %a1,%d4,<<,%a2@\+&,%a3,%acc2
+    64cc:	a41a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d2,%acc1
+    64d0:	a49a 4a39      	macl %a1,%d4,<<,%a2@\+&,%d2,%acc2
+    64d4:	ae5a 4a29      	macl %a1,%d4,<<,%a2@\+&,%sp,%acc1
+    64d8:	aeda 4a39      	macl %a1,%d4,<<,%a2@\+&,%sp,%acc2
+    64dc:	a22e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1,%acc1
+    64e2:	a2ae 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1,%acc2
+    64e8:	a66e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3,%acc1
+    64ee:	a6ee 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3,%acc2
+    64f4:	a42e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2,%acc1
+    64fa:	a4ae 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2,%acc2
+    6500:	ae6e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp,%acc1
+    6506:	aeee 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp,%acc2
+    650c:	a22e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1,%acc1
+    6512:	a2ae 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1,%acc2
+    6518:	a66e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3,%acc1
+    651e:	a6ee 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3,%acc2
+    6524:	a42e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2,%acc1
+    652a:	a4ae 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2,%acc2
+    6530:	ae6e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp,%acc1
+    6536:	aeee 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp,%acc2
+    653c:	a221 4a09      	macl %a1,%d4,<<,%a1@-,%d1,%acc1
+    6540:	a2a1 4a19      	macl %a1,%d4,<<,%a1@-,%d1,%acc2
+    6544:	a661 4a09      	macl %a1,%d4,<<,%a1@-,%a3,%acc1
+    6548:	a6e1 4a19      	macl %a1,%d4,<<,%a1@-,%a3,%acc2
+    654c:	a421 4a09      	macl %a1,%d4,<<,%a1@-,%d2,%acc1
+    6550:	a4a1 4a19      	macl %a1,%d4,<<,%a1@-,%d2,%acc2
+    6554:	ae61 4a09      	macl %a1,%d4,<<,%a1@-,%sp,%acc1
+    6558:	aee1 4a19      	macl %a1,%d4,<<,%a1@-,%sp,%acc2
+    655c:	a221 4a29      	macl %a1,%d4,<<,%a1@-&,%d1,%acc1
+    6560:	a2a1 4a39      	macl %a1,%d4,<<,%a1@-&,%d1,%acc2
+    6564:	a661 4a29      	macl %a1,%d4,<<,%a1@-&,%a3,%acc1
+    6568:	a6e1 4a39      	macl %a1,%d4,<<,%a1@-&,%a3,%acc2
+    656c:	a421 4a29      	macl %a1,%d4,<<,%a1@-&,%d2,%acc1
+    6570:	a4a1 4a39      	macl %a1,%d4,<<,%a1@-&,%d2,%acc2
+    6574:	ae61 4a29      	macl %a1,%d4,<<,%a1@-&,%sp,%acc1
+    6578:	aee1 4a39      	macl %a1,%d4,<<,%a1@-&,%sp,%acc2
+    657c:	a213 4e09      	macl %a1,%d4,>>,%a3@,%d1,%acc1
+    6580:	a293 4e19      	macl %a1,%d4,>>,%a3@,%d1,%acc2
+    6584:	a653 4e09      	macl %a1,%d4,>>,%a3@,%a3,%acc1
+    6588:	a6d3 4e19      	macl %a1,%d4,>>,%a3@,%a3,%acc2
+    658c:	a413 4e09      	macl %a1,%d4,>>,%a3@,%d2,%acc1
+    6590:	a493 4e19      	macl %a1,%d4,>>,%a3@,%d2,%acc2
+    6594:	ae53 4e09      	macl %a1,%d4,>>,%a3@,%sp,%acc1
+    6598:	aed3 4e19      	macl %a1,%d4,>>,%a3@,%sp,%acc2
+    659c:	a213 4e29      	macl %a1,%d4,>>,%a3@&,%d1,%acc1
+    65a0:	a293 4e39      	macl %a1,%d4,>>,%a3@&,%d1,%acc2
+    65a4:	a653 4e29      	macl %a1,%d4,>>,%a3@&,%a3,%acc1
+    65a8:	a6d3 4e39      	macl %a1,%d4,>>,%a3@&,%a3,%acc2
+    65ac:	a413 4e29      	macl %a1,%d4,>>,%a3@&,%d2,%acc1
+    65b0:	a493 4e39      	macl %a1,%d4,>>,%a3@&,%d2,%acc2
+    65b4:	ae53 4e29      	macl %a1,%d4,>>,%a3@&,%sp,%acc1
+    65b8:	aed3 4e39      	macl %a1,%d4,>>,%a3@&,%sp,%acc2
+    65bc:	a21a 4e09      	macl %a1,%d4,>>,%a2@\+,%d1,%acc1
+    65c0:	a29a 4e19      	macl %a1,%d4,>>,%a2@\+,%d1,%acc2
+    65c4:	a65a 4e09      	macl %a1,%d4,>>,%a2@\+,%a3,%acc1
+    65c8:	a6da 4e19      	macl %a1,%d4,>>,%a2@\+,%a3,%acc2
+    65cc:	a41a 4e09      	macl %a1,%d4,>>,%a2@\+,%d2,%acc1
+    65d0:	a49a 4e19      	macl %a1,%d4,>>,%a2@\+,%d2,%acc2
+    65d4:	ae5a 4e09      	macl %a1,%d4,>>,%a2@\+,%sp,%acc1
+    65d8:	aeda 4e19      	macl %a1,%d4,>>,%a2@\+,%sp,%acc2
+    65dc:	a21a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d1,%acc1
+    65e0:	a29a 4e39      	macl %a1,%d4,>>,%a2@\+&,%d1,%acc2
+    65e4:	a65a 4e29      	macl %a1,%d4,>>,%a2@\+&,%a3,%acc1
+    65e8:	a6da 4e39      	macl %a1,%d4,>>,%a2@\+&,%a3,%acc2
+    65ec:	a41a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d2,%acc1
+    65f0:	a49a 4e39      	macl %a1,%d4,>>,%a2@\+&,%d2,%acc2
+    65f4:	ae5a 4e29      	macl %a1,%d4,>>,%a2@\+&,%sp,%acc1
+    65f8:	aeda 4e39      	macl %a1,%d4,>>,%a2@\+&,%sp,%acc2
+    65fc:	a22e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1,%acc1
+    6602:	a2ae 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1,%acc2
+    6608:	a66e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3,%acc1
+    660e:	a6ee 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3,%acc2
+    6614:	a42e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2,%acc1
+    661a:	a4ae 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2,%acc2
+    6620:	ae6e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp,%acc1
+    6626:	aeee 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp,%acc2
+    662c:	a22e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1,%acc1
+    6632:	a2ae 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1,%acc2
+    6638:	a66e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3,%acc1
+    663e:	a6ee 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3,%acc2
+    6644:	a42e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2,%acc1
+    664a:	a4ae 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2,%acc2
+    6650:	ae6e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp,%acc1
+    6656:	aeee 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp,%acc2
+    665c:	a221 4e09      	macl %a1,%d4,>>,%a1@-,%d1,%acc1
+    6660:	a2a1 4e19      	macl %a1,%d4,>>,%a1@-,%d1,%acc2
+    6664:	a661 4e09      	macl %a1,%d4,>>,%a1@-,%a3,%acc1
+    6668:	a6e1 4e19      	macl %a1,%d4,>>,%a1@-,%a3,%acc2
+    666c:	a421 4e09      	macl %a1,%d4,>>,%a1@-,%d2,%acc1
+    6670:	a4a1 4e19      	macl %a1,%d4,>>,%a1@-,%d2,%acc2
+    6674:	ae61 4e09      	macl %a1,%d4,>>,%a1@-,%sp,%acc1
+    6678:	aee1 4e19      	macl %a1,%d4,>>,%a1@-,%sp,%acc2
+    667c:	a221 4e29      	macl %a1,%d4,>>,%a1@-&,%d1,%acc1
+    6680:	a2a1 4e39      	macl %a1,%d4,>>,%a1@-&,%d1,%acc2
+    6684:	a661 4e29      	macl %a1,%d4,>>,%a1@-&,%a3,%acc1
+    6688:	a6e1 4e39      	macl %a1,%d4,>>,%a1@-&,%a3,%acc2
+    668c:	a421 4e29      	macl %a1,%d4,>>,%a1@-&,%d2,%acc1
+    6690:	a4a1 4e39      	macl %a1,%d4,>>,%a1@-&,%d2,%acc2
+    6694:	ae61 4e29      	macl %a1,%d4,>>,%a1@-&,%sp,%acc1
+    6698:	aee1 4e39      	macl %a1,%d4,>>,%a1@-&,%sp,%acc2
+    669c:	a213 4a09      	macl %a1,%d4,<<,%a3@,%d1,%acc1
+    66a0:	a293 4a19      	macl %a1,%d4,<<,%a3@,%d1,%acc2
+    66a4:	a653 4a09      	macl %a1,%d4,<<,%a3@,%a3,%acc1
+    66a8:	a6d3 4a19      	macl %a1,%d4,<<,%a3@,%a3,%acc2
+    66ac:	a413 4a09      	macl %a1,%d4,<<,%a3@,%d2,%acc1
+    66b0:	a493 4a19      	macl %a1,%d4,<<,%a3@,%d2,%acc2
+    66b4:	ae53 4a09      	macl %a1,%d4,<<,%a3@,%sp,%acc1
+    66b8:	aed3 4a19      	macl %a1,%d4,<<,%a3@,%sp,%acc2
+    66bc:	a213 4a29      	macl %a1,%d4,<<,%a3@&,%d1,%acc1
+    66c0:	a293 4a39      	macl %a1,%d4,<<,%a3@&,%d1,%acc2
+    66c4:	a653 4a29      	macl %a1,%d4,<<,%a3@&,%a3,%acc1
+    66c8:	a6d3 4a39      	macl %a1,%d4,<<,%a3@&,%a3,%acc2
+    66cc:	a413 4a29      	macl %a1,%d4,<<,%a3@&,%d2,%acc1
+    66d0:	a493 4a39      	macl %a1,%d4,<<,%a3@&,%d2,%acc2
+    66d4:	ae53 4a29      	macl %a1,%d4,<<,%a3@&,%sp,%acc1
+    66d8:	aed3 4a39      	macl %a1,%d4,<<,%a3@&,%sp,%acc2
+    66dc:	a21a 4a09      	macl %a1,%d4,<<,%a2@\+,%d1,%acc1
+    66e0:	a29a 4a19      	macl %a1,%d4,<<,%a2@\+,%d1,%acc2
+    66e4:	a65a 4a09      	macl %a1,%d4,<<,%a2@\+,%a3,%acc1
+    66e8:	a6da 4a19      	macl %a1,%d4,<<,%a2@\+,%a3,%acc2
+    66ec:	a41a 4a09      	macl %a1,%d4,<<,%a2@\+,%d2,%acc1
+    66f0:	a49a 4a19      	macl %a1,%d4,<<,%a2@\+,%d2,%acc2
+    66f4:	ae5a 4a09      	macl %a1,%d4,<<,%a2@\+,%sp,%acc1
+    66f8:	aeda 4a19      	macl %a1,%d4,<<,%a2@\+,%sp,%acc2
+    66fc:	a21a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d1,%acc1
+    6700:	a29a 4a39      	macl %a1,%d4,<<,%a2@\+&,%d1,%acc2
+    6704:	a65a 4a29      	macl %a1,%d4,<<,%a2@\+&,%a3,%acc1
+    6708:	a6da 4a39      	macl %a1,%d4,<<,%a2@\+&,%a3,%acc2
+    670c:	a41a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d2,%acc1
+    6710:	a49a 4a39      	macl %a1,%d4,<<,%a2@\+&,%d2,%acc2
+    6714:	ae5a 4a29      	macl %a1,%d4,<<,%a2@\+&,%sp,%acc1
+    6718:	aeda 4a39      	macl %a1,%d4,<<,%a2@\+&,%sp,%acc2
+    671c:	a22e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1,%acc1
+    6722:	a2ae 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1,%acc2
+    6728:	a66e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3,%acc1
+    672e:	a6ee 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3,%acc2
+    6734:	a42e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2,%acc1
+    673a:	a4ae 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2,%acc2
+    6740:	ae6e 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp,%acc1
+    6746:	aeee 4a19 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp,%acc2
+    674c:	a22e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1,%acc1
+    6752:	a2ae 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1,%acc2
+    6758:	a66e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3,%acc1
+    675e:	a6ee 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3,%acc2
+    6764:	a42e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2,%acc1
+    676a:	a4ae 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2,%acc2
+    6770:	ae6e 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp,%acc1
+    6776:	aeee 4a39 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp,%acc2
+    677c:	a221 4a09      	macl %a1,%d4,<<,%a1@-,%d1,%acc1
+    6780:	a2a1 4a19      	macl %a1,%d4,<<,%a1@-,%d1,%acc2
+    6784:	a661 4a09      	macl %a1,%d4,<<,%a1@-,%a3,%acc1
+    6788:	a6e1 4a19      	macl %a1,%d4,<<,%a1@-,%a3,%acc2
+    678c:	a421 4a09      	macl %a1,%d4,<<,%a1@-,%d2,%acc1
+    6790:	a4a1 4a19      	macl %a1,%d4,<<,%a1@-,%d2,%acc2
+    6794:	ae61 4a09      	macl %a1,%d4,<<,%a1@-,%sp,%acc1
+    6798:	aee1 4a19      	macl %a1,%d4,<<,%a1@-,%sp,%acc2
+    679c:	a221 4a29      	macl %a1,%d4,<<,%a1@-&,%d1,%acc1
+    67a0:	a2a1 4a39      	macl %a1,%d4,<<,%a1@-&,%d1,%acc2
+    67a4:	a661 4a29      	macl %a1,%d4,<<,%a1@-&,%a3,%acc1
+    67a8:	a6e1 4a39      	macl %a1,%d4,<<,%a1@-&,%a3,%acc2
+    67ac:	a421 4a29      	macl %a1,%d4,<<,%a1@-&,%d2,%acc1
+    67b0:	a4a1 4a39      	macl %a1,%d4,<<,%a1@-&,%d2,%acc2
+    67b4:	ae61 4a29      	macl %a1,%d4,<<,%a1@-&,%sp,%acc1
+    67b8:	aee1 4a39      	macl %a1,%d4,<<,%a1@-&,%sp,%acc2
+    67bc:	a213 4e09      	macl %a1,%d4,>>,%a3@,%d1,%acc1
+    67c0:	a293 4e19      	macl %a1,%d4,>>,%a3@,%d1,%acc2
+    67c4:	a653 4e09      	macl %a1,%d4,>>,%a3@,%a3,%acc1
+    67c8:	a6d3 4e19      	macl %a1,%d4,>>,%a3@,%a3,%acc2
+    67cc:	a413 4e09      	macl %a1,%d4,>>,%a3@,%d2,%acc1
+    67d0:	a493 4e19      	macl %a1,%d4,>>,%a3@,%d2,%acc2
+    67d4:	ae53 4e09      	macl %a1,%d4,>>,%a3@,%sp,%acc1
+    67d8:	aed3 4e19      	macl %a1,%d4,>>,%a3@,%sp,%acc2
+    67dc:	a213 4e29      	macl %a1,%d4,>>,%a3@&,%d1,%acc1
+    67e0:	a293 4e39      	macl %a1,%d4,>>,%a3@&,%d1,%acc2
+    67e4:	a653 4e29      	macl %a1,%d4,>>,%a3@&,%a3,%acc1
+    67e8:	a6d3 4e39      	macl %a1,%d4,>>,%a3@&,%a3,%acc2
+    67ec:	a413 4e29      	macl %a1,%d4,>>,%a3@&,%d2,%acc1
+    67f0:	a493 4e39      	macl %a1,%d4,>>,%a3@&,%d2,%acc2
+    67f4:	ae53 4e29      	macl %a1,%d4,>>,%a3@&,%sp,%acc1
+    67f8:	aed3 4e39      	macl %a1,%d4,>>,%a3@&,%sp,%acc2
+    67fc:	a21a 4e09      	macl %a1,%d4,>>,%a2@\+,%d1,%acc1
+    6800:	a29a 4e19      	macl %a1,%d4,>>,%a2@\+,%d1,%acc2
+    6804:	a65a 4e09      	macl %a1,%d4,>>,%a2@\+,%a3,%acc1
+    6808:	a6da 4e19      	macl %a1,%d4,>>,%a2@\+,%a3,%acc2
+    680c:	a41a 4e09      	macl %a1,%d4,>>,%a2@\+,%d2,%acc1
+    6810:	a49a 4e19      	macl %a1,%d4,>>,%a2@\+,%d2,%acc2
+    6814:	ae5a 4e09      	macl %a1,%d4,>>,%a2@\+,%sp,%acc1
+    6818:	aeda 4e19      	macl %a1,%d4,>>,%a2@\+,%sp,%acc2
+    681c:	a21a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d1,%acc1
+    6820:	a29a 4e39      	macl %a1,%d4,>>,%a2@\+&,%d1,%acc2
+    6824:	a65a 4e29      	macl %a1,%d4,>>,%a2@\+&,%a3,%acc1
+    6828:	a6da 4e39      	macl %a1,%d4,>>,%a2@\+&,%a3,%acc2
+    682c:	a41a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d2,%acc1
+    6830:	a49a 4e39      	macl %a1,%d4,>>,%a2@\+&,%d2,%acc2
+    6834:	ae5a 4e29      	macl %a1,%d4,>>,%a2@\+&,%sp,%acc1
+    6838:	aeda 4e39      	macl %a1,%d4,>>,%a2@\+&,%sp,%acc2
+    683c:	a22e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1,%acc1
+    6842:	a2ae 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1,%acc2
+    6848:	a66e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3,%acc1
+    684e:	a6ee 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3,%acc2
+    6854:	a42e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2,%acc1
+    685a:	a4ae 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2,%acc2
+    6860:	ae6e 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp,%acc1
+    6866:	aeee 4e19 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp,%acc2
+    686c:	a22e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1,%acc1
+    6872:	a2ae 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1,%acc2
+    6878:	a66e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3,%acc1
+    687e:	a6ee 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3,%acc2
+    6884:	a42e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2,%acc1
+    688a:	a4ae 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2,%acc2
+    6890:	ae6e 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp,%acc1
+    6896:	aeee 4e39 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp,%acc2
+    689c:	a221 4e09      	macl %a1,%d4,>>,%a1@-,%d1,%acc1
+    68a0:	a2a1 4e19      	macl %a1,%d4,>>,%a1@-,%d1,%acc2
+    68a4:	a661 4e09      	macl %a1,%d4,>>,%a1@-,%a3,%acc1
+    68a8:	a6e1 4e19      	macl %a1,%d4,>>,%a1@-,%a3,%acc2
+    68ac:	a421 4e09      	macl %a1,%d4,>>,%a1@-,%d2,%acc1
+    68b0:	a4a1 4e19      	macl %a1,%d4,>>,%a1@-,%d2,%acc2
+    68b4:	ae61 4e09      	macl %a1,%d4,>>,%a1@-,%sp,%acc1
+    68b8:	aee1 4e19      	macl %a1,%d4,>>,%a1@-,%sp,%acc2
+    68bc:	a221 4e29      	macl %a1,%d4,>>,%a1@-&,%d1,%acc1
+    68c0:	a2a1 4e39      	macl %a1,%d4,>>,%a1@-&,%d1,%acc2
+    68c4:	a661 4e29      	macl %a1,%d4,>>,%a1@-&,%a3,%acc1
+    68c8:	a6e1 4e39      	macl %a1,%d4,>>,%a1@-&,%a3,%acc2
+    68cc:	a421 4e29      	macl %a1,%d4,>>,%a1@-&,%d2,%acc1
+    68d0:	a4a1 4e39      	macl %a1,%d4,>>,%a1@-&,%d2,%acc2
+    68d4:	ae61 4e29      	macl %a1,%d4,>>,%a1@-&,%sp,%acc1
+    68d8:	aee1 4e39      	macl %a1,%d4,>>,%a1@-&,%sp,%acc2
+    68dc:	a213 b806      	macl %d6,%a3,%a3@,%d1,%acc1
+    68e0:	a293 b816      	macl %d6,%a3,%a3@,%d1,%acc2
+    68e4:	a653 b806      	macl %d6,%a3,%a3@,%a3,%acc1
+    68e8:	a6d3 b816      	macl %d6,%a3,%a3@,%a3,%acc2
+    68ec:	a413 b806      	macl %d6,%a3,%a3@,%d2,%acc1
+    68f0:	a493 b816      	macl %d6,%a3,%a3@,%d2,%acc2
+    68f4:	ae53 b806      	macl %d6,%a3,%a3@,%sp,%acc1
+    68f8:	aed3 b816      	macl %d6,%a3,%a3@,%sp,%acc2
+    68fc:	a213 b826      	macl %d6,%a3,%a3@&,%d1,%acc1
+    6900:	a293 b836      	macl %d6,%a3,%a3@&,%d1,%acc2
+    6904:	a653 b826      	macl %d6,%a3,%a3@&,%a3,%acc1
+    6908:	a6d3 b836      	macl %d6,%a3,%a3@&,%a3,%acc2
+    690c:	a413 b826      	macl %d6,%a3,%a3@&,%d2,%acc1
+    6910:	a493 b836      	macl %d6,%a3,%a3@&,%d2,%acc2
+    6914:	ae53 b826      	macl %d6,%a3,%a3@&,%sp,%acc1
+    6918:	aed3 b836      	macl %d6,%a3,%a3@&,%sp,%acc2
+    691c:	a21a b806      	macl %d6,%a3,%a2@\+,%d1,%acc1
+    6920:	a29a b816      	macl %d6,%a3,%a2@\+,%d1,%acc2
+    6924:	a65a b806      	macl %d6,%a3,%a2@\+,%a3,%acc1
+    6928:	a6da b816      	macl %d6,%a3,%a2@\+,%a3,%acc2
+    692c:	a41a b806      	macl %d6,%a3,%a2@\+,%d2,%acc1
+    6930:	a49a b816      	macl %d6,%a3,%a2@\+,%d2,%acc2
+    6934:	ae5a b806      	macl %d6,%a3,%a2@\+,%sp,%acc1
+    6938:	aeda b816      	macl %d6,%a3,%a2@\+,%sp,%acc2
+    693c:	a21a b826      	macl %d6,%a3,%a2@\+&,%d1,%acc1
+    6940:	a29a b836      	macl %d6,%a3,%a2@\+&,%d1,%acc2
+    6944:	a65a b826      	macl %d6,%a3,%a2@\+&,%a3,%acc1
+    6948:	a6da b836      	macl %d6,%a3,%a2@\+&,%a3,%acc2
+    694c:	a41a b826      	macl %d6,%a3,%a2@\+&,%d2,%acc1
+    6950:	a49a b836      	macl %d6,%a3,%a2@\+&,%d2,%acc2
+    6954:	ae5a b826      	macl %d6,%a3,%a2@\+&,%sp,%acc1
+    6958:	aeda b836      	macl %d6,%a3,%a2@\+&,%sp,%acc2
+    695c:	a22e b806 000a 	macl %d6,%a3,%fp@\(10\),%d1,%acc1
+    6962:	a2ae b816 000a 	macl %d6,%a3,%fp@\(10\),%d1,%acc2
+    6968:	a66e b806 000a 	macl %d6,%a3,%fp@\(10\),%a3,%acc1
+    696e:	a6ee b816 000a 	macl %d6,%a3,%fp@\(10\),%a3,%acc2
+    6974:	a42e b806 000a 	macl %d6,%a3,%fp@\(10\),%d2,%acc1
+    697a:	a4ae b816 000a 	macl %d6,%a3,%fp@\(10\),%d2,%acc2
+    6980:	ae6e b806 000a 	macl %d6,%a3,%fp@\(10\),%sp,%acc1
+    6986:	aeee b816 000a 	macl %d6,%a3,%fp@\(10\),%sp,%acc2
+    698c:	a22e b826 000a 	macl %d6,%a3,%fp@\(10\)&,%d1,%acc1
+    6992:	a2ae b836 000a 	macl %d6,%a3,%fp@\(10\)&,%d1,%acc2
+    6998:	a66e b826 000a 	macl %d6,%a3,%fp@\(10\)&,%a3,%acc1
+    699e:	a6ee b836 000a 	macl %d6,%a3,%fp@\(10\)&,%a3,%acc2
+    69a4:	a42e b826 000a 	macl %d6,%a3,%fp@\(10\)&,%d2,%acc1
+    69aa:	a4ae b836 000a 	macl %d6,%a3,%fp@\(10\)&,%d2,%acc2
+    69b0:	ae6e b826 000a 	macl %d6,%a3,%fp@\(10\)&,%sp,%acc1
+    69b6:	aeee b836 000a 	macl %d6,%a3,%fp@\(10\)&,%sp,%acc2
+    69bc:	a221 b806      	macl %d6,%a3,%a1@-,%d1,%acc1
+    69c0:	a2a1 b816      	macl %d6,%a3,%a1@-,%d1,%acc2
+    69c4:	a661 b806      	macl %d6,%a3,%a1@-,%a3,%acc1
+    69c8:	a6e1 b816      	macl %d6,%a3,%a1@-,%a3,%acc2
+    69cc:	a421 b806      	macl %d6,%a3,%a1@-,%d2,%acc1
+    69d0:	a4a1 b816      	macl %d6,%a3,%a1@-,%d2,%acc2
+    69d4:	ae61 b806      	macl %d6,%a3,%a1@-,%sp,%acc1
+    69d8:	aee1 b816      	macl %d6,%a3,%a1@-,%sp,%acc2
+    69dc:	a221 b826      	macl %d6,%a3,%a1@-&,%d1,%acc1
+    69e0:	a2a1 b836      	macl %d6,%a3,%a1@-&,%d1,%acc2
+    69e4:	a661 b826      	macl %d6,%a3,%a1@-&,%a3,%acc1
+    69e8:	a6e1 b836      	macl %d6,%a3,%a1@-&,%a3,%acc2
+    69ec:	a421 b826      	macl %d6,%a3,%a1@-&,%d2,%acc1
+    69f0:	a4a1 b836      	macl %d6,%a3,%a1@-&,%d2,%acc2
+    69f4:	ae61 b826      	macl %d6,%a3,%a1@-&,%sp,%acc1
+    69f8:	aee1 b836      	macl %d6,%a3,%a1@-&,%sp,%acc2
+    69fc:	a213 ba06      	macl %d6,%a3,<<,%a3@,%d1,%acc1
+    6a00:	a293 ba16      	macl %d6,%a3,<<,%a3@,%d1,%acc2
+    6a04:	a653 ba06      	macl %d6,%a3,<<,%a3@,%a3,%acc1
+    6a08:	a6d3 ba16      	macl %d6,%a3,<<,%a3@,%a3,%acc2
+    6a0c:	a413 ba06      	macl %d6,%a3,<<,%a3@,%d2,%acc1
+    6a10:	a493 ba16      	macl %d6,%a3,<<,%a3@,%d2,%acc2
+    6a14:	ae53 ba06      	macl %d6,%a3,<<,%a3@,%sp,%acc1
+    6a18:	aed3 ba16      	macl %d6,%a3,<<,%a3@,%sp,%acc2
+    6a1c:	a213 ba26      	macl %d6,%a3,<<,%a3@&,%d1,%acc1
+    6a20:	a293 ba36      	macl %d6,%a3,<<,%a3@&,%d1,%acc2
+    6a24:	a653 ba26      	macl %d6,%a3,<<,%a3@&,%a3,%acc1
+    6a28:	a6d3 ba36      	macl %d6,%a3,<<,%a3@&,%a3,%acc2
+    6a2c:	a413 ba26      	macl %d6,%a3,<<,%a3@&,%d2,%acc1
+    6a30:	a493 ba36      	macl %d6,%a3,<<,%a3@&,%d2,%acc2
+    6a34:	ae53 ba26      	macl %d6,%a3,<<,%a3@&,%sp,%acc1
+    6a38:	aed3 ba36      	macl %d6,%a3,<<,%a3@&,%sp,%acc2
+    6a3c:	a21a ba06      	macl %d6,%a3,<<,%a2@\+,%d1,%acc1
+    6a40:	a29a ba16      	macl %d6,%a3,<<,%a2@\+,%d1,%acc2
+    6a44:	a65a ba06      	macl %d6,%a3,<<,%a2@\+,%a3,%acc1
+    6a48:	a6da ba16      	macl %d6,%a3,<<,%a2@\+,%a3,%acc2
+    6a4c:	a41a ba06      	macl %d6,%a3,<<,%a2@\+,%d2,%acc1
+    6a50:	a49a ba16      	macl %d6,%a3,<<,%a2@\+,%d2,%acc2
+    6a54:	ae5a ba06      	macl %d6,%a3,<<,%a2@\+,%sp,%acc1
+    6a58:	aeda ba16      	macl %d6,%a3,<<,%a2@\+,%sp,%acc2
+    6a5c:	a21a ba26      	macl %d6,%a3,<<,%a2@\+&,%d1,%acc1
+    6a60:	a29a ba36      	macl %d6,%a3,<<,%a2@\+&,%d1,%acc2
+    6a64:	a65a ba26      	macl %d6,%a3,<<,%a2@\+&,%a3,%acc1
+    6a68:	a6da ba36      	macl %d6,%a3,<<,%a2@\+&,%a3,%acc2
+    6a6c:	a41a ba26      	macl %d6,%a3,<<,%a2@\+&,%d2,%acc1
+    6a70:	a49a ba36      	macl %d6,%a3,<<,%a2@\+&,%d2,%acc2
+    6a74:	ae5a ba26      	macl %d6,%a3,<<,%a2@\+&,%sp,%acc1
+    6a78:	aeda ba36      	macl %d6,%a3,<<,%a2@\+&,%sp,%acc2
+    6a7c:	a22e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1,%acc1
+    6a82:	a2ae ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1,%acc2
+    6a88:	a66e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3,%acc1
+    6a8e:	a6ee ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3,%acc2
+    6a94:	a42e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2,%acc1
+    6a9a:	a4ae ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2,%acc2
+    6aa0:	ae6e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp,%acc1
+    6aa6:	aeee ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp,%acc2
+    6aac:	a22e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1,%acc1
+    6ab2:	a2ae ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1,%acc2
+    6ab8:	a66e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3,%acc1
+    6abe:	a6ee ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3,%acc2
+    6ac4:	a42e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2,%acc1
+    6aca:	a4ae ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2,%acc2
+    6ad0:	ae6e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp,%acc1
+    6ad6:	aeee ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp,%acc2
+    6adc:	a221 ba06      	macl %d6,%a3,<<,%a1@-,%d1,%acc1
+    6ae0:	a2a1 ba16      	macl %d6,%a3,<<,%a1@-,%d1,%acc2
+    6ae4:	a661 ba06      	macl %d6,%a3,<<,%a1@-,%a3,%acc1
+    6ae8:	a6e1 ba16      	macl %d6,%a3,<<,%a1@-,%a3,%acc2
+    6aec:	a421 ba06      	macl %d6,%a3,<<,%a1@-,%d2,%acc1
+    6af0:	a4a1 ba16      	macl %d6,%a3,<<,%a1@-,%d2,%acc2
+    6af4:	ae61 ba06      	macl %d6,%a3,<<,%a1@-,%sp,%acc1
+    6af8:	aee1 ba16      	macl %d6,%a3,<<,%a1@-,%sp,%acc2
+    6afc:	a221 ba26      	macl %d6,%a3,<<,%a1@-&,%d1,%acc1
+    6b00:	a2a1 ba36      	macl %d6,%a3,<<,%a1@-&,%d1,%acc2
+    6b04:	a661 ba26      	macl %d6,%a3,<<,%a1@-&,%a3,%acc1
+    6b08:	a6e1 ba36      	macl %d6,%a3,<<,%a1@-&,%a3,%acc2
+    6b0c:	a421 ba26      	macl %d6,%a3,<<,%a1@-&,%d2,%acc1
+    6b10:	a4a1 ba36      	macl %d6,%a3,<<,%a1@-&,%d2,%acc2
+    6b14:	ae61 ba26      	macl %d6,%a3,<<,%a1@-&,%sp,%acc1
+    6b18:	aee1 ba36      	macl %d6,%a3,<<,%a1@-&,%sp,%acc2
+    6b1c:	a213 be06      	macl %d6,%a3,>>,%a3@,%d1,%acc1
+    6b20:	a293 be16      	macl %d6,%a3,>>,%a3@,%d1,%acc2
+    6b24:	a653 be06      	macl %d6,%a3,>>,%a3@,%a3,%acc1
+    6b28:	a6d3 be16      	macl %d6,%a3,>>,%a3@,%a3,%acc2
+    6b2c:	a413 be06      	macl %d6,%a3,>>,%a3@,%d2,%acc1
+    6b30:	a493 be16      	macl %d6,%a3,>>,%a3@,%d2,%acc2
+    6b34:	ae53 be06      	macl %d6,%a3,>>,%a3@,%sp,%acc1
+    6b38:	aed3 be16      	macl %d6,%a3,>>,%a3@,%sp,%acc2
+    6b3c:	a213 be26      	macl %d6,%a3,>>,%a3@&,%d1,%acc1
+    6b40:	a293 be36      	macl %d6,%a3,>>,%a3@&,%d1,%acc2
+    6b44:	a653 be26      	macl %d6,%a3,>>,%a3@&,%a3,%acc1
+    6b48:	a6d3 be36      	macl %d6,%a3,>>,%a3@&,%a3,%acc2
+    6b4c:	a413 be26      	macl %d6,%a3,>>,%a3@&,%d2,%acc1
+    6b50:	a493 be36      	macl %d6,%a3,>>,%a3@&,%d2,%acc2
+    6b54:	ae53 be26      	macl %d6,%a3,>>,%a3@&,%sp,%acc1
+    6b58:	aed3 be36      	macl %d6,%a3,>>,%a3@&,%sp,%acc2
+    6b5c:	a21a be06      	macl %d6,%a3,>>,%a2@\+,%d1,%acc1
+    6b60:	a29a be16      	macl %d6,%a3,>>,%a2@\+,%d1,%acc2
+    6b64:	a65a be06      	macl %d6,%a3,>>,%a2@\+,%a3,%acc1
+    6b68:	a6da be16      	macl %d6,%a3,>>,%a2@\+,%a3,%acc2
+    6b6c:	a41a be06      	macl %d6,%a3,>>,%a2@\+,%d2,%acc1
+    6b70:	a49a be16      	macl %d6,%a3,>>,%a2@\+,%d2,%acc2
+    6b74:	ae5a be06      	macl %d6,%a3,>>,%a2@\+,%sp,%acc1
+    6b78:	aeda be16      	macl %d6,%a3,>>,%a2@\+,%sp,%acc2
+    6b7c:	a21a be26      	macl %d6,%a3,>>,%a2@\+&,%d1,%acc1
+    6b80:	a29a be36      	macl %d6,%a3,>>,%a2@\+&,%d1,%acc2
+    6b84:	a65a be26      	macl %d6,%a3,>>,%a2@\+&,%a3,%acc1
+    6b88:	a6da be36      	macl %d6,%a3,>>,%a2@\+&,%a3,%acc2
+    6b8c:	a41a be26      	macl %d6,%a3,>>,%a2@\+&,%d2,%acc1
+    6b90:	a49a be36      	macl %d6,%a3,>>,%a2@\+&,%d2,%acc2
+    6b94:	ae5a be26      	macl %d6,%a3,>>,%a2@\+&,%sp,%acc1
+    6b98:	aeda be36      	macl %d6,%a3,>>,%a2@\+&,%sp,%acc2
+    6b9c:	a22e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1,%acc1
+    6ba2:	a2ae be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1,%acc2
+    6ba8:	a66e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3,%acc1
+    6bae:	a6ee be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3,%acc2
+    6bb4:	a42e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2,%acc1
+    6bba:	a4ae be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2,%acc2
+    6bc0:	ae6e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp,%acc1
+    6bc6:	aeee be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp,%acc2
+    6bcc:	a22e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1,%acc1
+    6bd2:	a2ae be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1,%acc2
+    6bd8:	a66e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3,%acc1
+    6bde:	a6ee be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3,%acc2
+    6be4:	a42e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2,%acc1
+    6bea:	a4ae be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2,%acc2
+    6bf0:	ae6e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp,%acc1
+    6bf6:	aeee be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp,%acc2
+    6bfc:	a221 be06      	macl %d6,%a3,>>,%a1@-,%d1,%acc1
+    6c00:	a2a1 be16      	macl %d6,%a3,>>,%a1@-,%d1,%acc2
+    6c04:	a661 be06      	macl %d6,%a3,>>,%a1@-,%a3,%acc1
+    6c08:	a6e1 be16      	macl %d6,%a3,>>,%a1@-,%a3,%acc2
+    6c0c:	a421 be06      	macl %d6,%a3,>>,%a1@-,%d2,%acc1
+    6c10:	a4a1 be16      	macl %d6,%a3,>>,%a1@-,%d2,%acc2
+    6c14:	ae61 be06      	macl %d6,%a3,>>,%a1@-,%sp,%acc1
+    6c18:	aee1 be16      	macl %d6,%a3,>>,%a1@-,%sp,%acc2
+    6c1c:	a221 be26      	macl %d6,%a3,>>,%a1@-&,%d1,%acc1
+    6c20:	a2a1 be36      	macl %d6,%a3,>>,%a1@-&,%d1,%acc2
+    6c24:	a661 be26      	macl %d6,%a3,>>,%a1@-&,%a3,%acc1
+    6c28:	a6e1 be36      	macl %d6,%a3,>>,%a1@-&,%a3,%acc2
+    6c2c:	a421 be26      	macl %d6,%a3,>>,%a1@-&,%d2,%acc1
+    6c30:	a4a1 be36      	macl %d6,%a3,>>,%a1@-&,%d2,%acc2
+    6c34:	ae61 be26      	macl %d6,%a3,>>,%a1@-&,%sp,%acc1
+    6c38:	aee1 be36      	macl %d6,%a3,>>,%a1@-&,%sp,%acc2
+    6c3c:	a213 ba06      	macl %d6,%a3,<<,%a3@,%d1,%acc1
+    6c40:	a293 ba16      	macl %d6,%a3,<<,%a3@,%d1,%acc2
+    6c44:	a653 ba06      	macl %d6,%a3,<<,%a3@,%a3,%acc1
+    6c48:	a6d3 ba16      	macl %d6,%a3,<<,%a3@,%a3,%acc2
+    6c4c:	a413 ba06      	macl %d6,%a3,<<,%a3@,%d2,%acc1
+    6c50:	a493 ba16      	macl %d6,%a3,<<,%a3@,%d2,%acc2
+    6c54:	ae53 ba06      	macl %d6,%a3,<<,%a3@,%sp,%acc1
+    6c58:	aed3 ba16      	macl %d6,%a3,<<,%a3@,%sp,%acc2
+    6c5c:	a213 ba26      	macl %d6,%a3,<<,%a3@&,%d1,%acc1
+    6c60:	a293 ba36      	macl %d6,%a3,<<,%a3@&,%d1,%acc2
+    6c64:	a653 ba26      	macl %d6,%a3,<<,%a3@&,%a3,%acc1
+    6c68:	a6d3 ba36      	macl %d6,%a3,<<,%a3@&,%a3,%acc2
+    6c6c:	a413 ba26      	macl %d6,%a3,<<,%a3@&,%d2,%acc1
+    6c70:	a493 ba36      	macl %d6,%a3,<<,%a3@&,%d2,%acc2
+    6c74:	ae53 ba26      	macl %d6,%a3,<<,%a3@&,%sp,%acc1
+    6c78:	aed3 ba36      	macl %d6,%a3,<<,%a3@&,%sp,%acc2
+    6c7c:	a21a ba06      	macl %d6,%a3,<<,%a2@\+,%d1,%acc1
+    6c80:	a29a ba16      	macl %d6,%a3,<<,%a2@\+,%d1,%acc2
+    6c84:	a65a ba06      	macl %d6,%a3,<<,%a2@\+,%a3,%acc1
+    6c88:	a6da ba16      	macl %d6,%a3,<<,%a2@\+,%a3,%acc2
+    6c8c:	a41a ba06      	macl %d6,%a3,<<,%a2@\+,%d2,%acc1
+    6c90:	a49a ba16      	macl %d6,%a3,<<,%a2@\+,%d2,%acc2
+    6c94:	ae5a ba06      	macl %d6,%a3,<<,%a2@\+,%sp,%acc1
+    6c98:	aeda ba16      	macl %d6,%a3,<<,%a2@\+,%sp,%acc2
+    6c9c:	a21a ba26      	macl %d6,%a3,<<,%a2@\+&,%d1,%acc1
+    6ca0:	a29a ba36      	macl %d6,%a3,<<,%a2@\+&,%d1,%acc2
+    6ca4:	a65a ba26      	macl %d6,%a3,<<,%a2@\+&,%a3,%acc1
+    6ca8:	a6da ba36      	macl %d6,%a3,<<,%a2@\+&,%a3,%acc2
+    6cac:	a41a ba26      	macl %d6,%a3,<<,%a2@\+&,%d2,%acc1
+    6cb0:	a49a ba36      	macl %d6,%a3,<<,%a2@\+&,%d2,%acc2
+    6cb4:	ae5a ba26      	macl %d6,%a3,<<,%a2@\+&,%sp,%acc1
+    6cb8:	aeda ba36      	macl %d6,%a3,<<,%a2@\+&,%sp,%acc2
+    6cbc:	a22e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1,%acc1
+    6cc2:	a2ae ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1,%acc2
+    6cc8:	a66e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3,%acc1
+    6cce:	a6ee ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3,%acc2
+    6cd4:	a42e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2,%acc1
+    6cda:	a4ae ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2,%acc2
+    6ce0:	ae6e ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp,%acc1
+    6ce6:	aeee ba16 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp,%acc2
+    6cec:	a22e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1,%acc1
+    6cf2:	a2ae ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1,%acc2
+    6cf8:	a66e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3,%acc1
+    6cfe:	a6ee ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3,%acc2
+    6d04:	a42e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2,%acc1
+    6d0a:	a4ae ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2,%acc2
+    6d10:	ae6e ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp,%acc1
+    6d16:	aeee ba36 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp,%acc2
+    6d1c:	a221 ba06      	macl %d6,%a3,<<,%a1@-,%d1,%acc1
+    6d20:	a2a1 ba16      	macl %d6,%a3,<<,%a1@-,%d1,%acc2
+    6d24:	a661 ba06      	macl %d6,%a3,<<,%a1@-,%a3,%acc1
+    6d28:	a6e1 ba16      	macl %d6,%a3,<<,%a1@-,%a3,%acc2
+    6d2c:	a421 ba06      	macl %d6,%a3,<<,%a1@-,%d2,%acc1
+    6d30:	a4a1 ba16      	macl %d6,%a3,<<,%a1@-,%d2,%acc2
+    6d34:	ae61 ba06      	macl %d6,%a3,<<,%a1@-,%sp,%acc1
+    6d38:	aee1 ba16      	macl %d6,%a3,<<,%a1@-,%sp,%acc2
+    6d3c:	a221 ba26      	macl %d6,%a3,<<,%a1@-&,%d1,%acc1
+    6d40:	a2a1 ba36      	macl %d6,%a3,<<,%a1@-&,%d1,%acc2
+    6d44:	a661 ba26      	macl %d6,%a3,<<,%a1@-&,%a3,%acc1
+    6d48:	a6e1 ba36      	macl %d6,%a3,<<,%a1@-&,%a3,%acc2
+    6d4c:	a421 ba26      	macl %d6,%a3,<<,%a1@-&,%d2,%acc1
+    6d50:	a4a1 ba36      	macl %d6,%a3,<<,%a1@-&,%d2,%acc2
+    6d54:	ae61 ba26      	macl %d6,%a3,<<,%a1@-&,%sp,%acc1
+    6d58:	aee1 ba36      	macl %d6,%a3,<<,%a1@-&,%sp,%acc2
+    6d5c:	a213 be06      	macl %d6,%a3,>>,%a3@,%d1,%acc1
+    6d60:	a293 be16      	macl %d6,%a3,>>,%a3@,%d1,%acc2
+    6d64:	a653 be06      	macl %d6,%a3,>>,%a3@,%a3,%acc1
+    6d68:	a6d3 be16      	macl %d6,%a3,>>,%a3@,%a3,%acc2
+    6d6c:	a413 be06      	macl %d6,%a3,>>,%a3@,%d2,%acc1
+    6d70:	a493 be16      	macl %d6,%a3,>>,%a3@,%d2,%acc2
+    6d74:	ae53 be06      	macl %d6,%a3,>>,%a3@,%sp,%acc1
+    6d78:	aed3 be16      	macl %d6,%a3,>>,%a3@,%sp,%acc2
+    6d7c:	a213 be26      	macl %d6,%a3,>>,%a3@&,%d1,%acc1
+    6d80:	a293 be36      	macl %d6,%a3,>>,%a3@&,%d1,%acc2
+    6d84:	a653 be26      	macl %d6,%a3,>>,%a3@&,%a3,%acc1
+    6d88:	a6d3 be36      	macl %d6,%a3,>>,%a3@&,%a3,%acc2
+    6d8c:	a413 be26      	macl %d6,%a3,>>,%a3@&,%d2,%acc1
+    6d90:	a493 be36      	macl %d6,%a3,>>,%a3@&,%d2,%acc2
+    6d94:	ae53 be26      	macl %d6,%a3,>>,%a3@&,%sp,%acc1
+    6d98:	aed3 be36      	macl %d6,%a3,>>,%a3@&,%sp,%acc2
+    6d9c:	a21a be06      	macl %d6,%a3,>>,%a2@\+,%d1,%acc1
+    6da0:	a29a be16      	macl %d6,%a3,>>,%a2@\+,%d1,%acc2
+    6da4:	a65a be06      	macl %d6,%a3,>>,%a2@\+,%a3,%acc1
+    6da8:	a6da be16      	macl %d6,%a3,>>,%a2@\+,%a3,%acc2
+    6dac:	a41a be06      	macl %d6,%a3,>>,%a2@\+,%d2,%acc1
+    6db0:	a49a be16      	macl %d6,%a3,>>,%a2@\+,%d2,%acc2
+    6db4:	ae5a be06      	macl %d6,%a3,>>,%a2@\+,%sp,%acc1
+    6db8:	aeda be16      	macl %d6,%a3,>>,%a2@\+,%sp,%acc2
+    6dbc:	a21a be26      	macl %d6,%a3,>>,%a2@\+&,%d1,%acc1
+    6dc0:	a29a be36      	macl %d6,%a3,>>,%a2@\+&,%d1,%acc2
+    6dc4:	a65a be26      	macl %d6,%a3,>>,%a2@\+&,%a3,%acc1
+    6dc8:	a6da be36      	macl %d6,%a3,>>,%a2@\+&,%a3,%acc2
+    6dcc:	a41a be26      	macl %d6,%a3,>>,%a2@\+&,%d2,%acc1
+    6dd0:	a49a be36      	macl %d6,%a3,>>,%a2@\+&,%d2,%acc2
+    6dd4:	ae5a be26      	macl %d6,%a3,>>,%a2@\+&,%sp,%acc1
+    6dd8:	aeda be36      	macl %d6,%a3,>>,%a2@\+&,%sp,%acc2
+    6ddc:	a22e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1,%acc1
+    6de2:	a2ae be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1,%acc2
+    6de8:	a66e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3,%acc1
+    6dee:	a6ee be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3,%acc2
+    6df4:	a42e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2,%acc1
+    6dfa:	a4ae be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2,%acc2
+    6e00:	ae6e be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp,%acc1
+    6e06:	aeee be16 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp,%acc2
+    6e0c:	a22e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1,%acc1
+    6e12:	a2ae be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1,%acc2
+    6e18:	a66e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3,%acc1
+    6e1e:	a6ee be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3,%acc2
+    6e24:	a42e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2,%acc1
+    6e2a:	a4ae be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2,%acc2
+    6e30:	ae6e be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp,%acc1
+    6e36:	aeee be36 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp,%acc2
+    6e3c:	a221 be06      	macl %d6,%a3,>>,%a1@-,%d1,%acc1
+    6e40:	a2a1 be16      	macl %d6,%a3,>>,%a1@-,%d1,%acc2
+    6e44:	a661 be06      	macl %d6,%a3,>>,%a1@-,%a3,%acc1
+    6e48:	a6e1 be16      	macl %d6,%a3,>>,%a1@-,%a3,%acc2
+    6e4c:	a421 be06      	macl %d6,%a3,>>,%a1@-,%d2,%acc1
+    6e50:	a4a1 be16      	macl %d6,%a3,>>,%a1@-,%d2,%acc2
+    6e54:	ae61 be06      	macl %d6,%a3,>>,%a1@-,%sp,%acc1
+    6e58:	aee1 be16      	macl %d6,%a3,>>,%a1@-,%sp,%acc2
+    6e5c:	a221 be26      	macl %d6,%a3,>>,%a1@-&,%d1,%acc1
+    6e60:	a2a1 be36      	macl %d6,%a3,>>,%a1@-&,%d1,%acc2
+    6e64:	a661 be26      	macl %d6,%a3,>>,%a1@-&,%a3,%acc1
+    6e68:	a6e1 be36      	macl %d6,%a3,>>,%a1@-&,%a3,%acc2
+    6e6c:	a421 be26      	macl %d6,%a3,>>,%a1@-&,%d2,%acc1
+    6e70:	a4a1 be36      	macl %d6,%a3,>>,%a1@-&,%d2,%acc2
+    6e74:	ae61 be26      	macl %d6,%a3,>>,%a1@-&,%sp,%acc1
+    6e78:	aee1 be36      	macl %d6,%a3,>>,%a1@-&,%sp,%acc2
+    6e7c:	a213 4806      	macl %d6,%d4,%a3@,%d1,%acc1
+    6e80:	a293 4816      	macl %d6,%d4,%a3@,%d1,%acc2
+    6e84:	a653 4806      	macl %d6,%d4,%a3@,%a3,%acc1
+    6e88:	a6d3 4816      	macl %d6,%d4,%a3@,%a3,%acc2
+    6e8c:	a413 4806      	macl %d6,%d4,%a3@,%d2,%acc1
+    6e90:	a493 4816      	macl %d6,%d4,%a3@,%d2,%acc2
+    6e94:	ae53 4806      	macl %d6,%d4,%a3@,%sp,%acc1
+    6e98:	aed3 4816      	macl %d6,%d4,%a3@,%sp,%acc2
+    6e9c:	a213 4826      	macl %d6,%d4,%a3@&,%d1,%acc1
+    6ea0:	a293 4836      	macl %d6,%d4,%a3@&,%d1,%acc2
+    6ea4:	a653 4826      	macl %d6,%d4,%a3@&,%a3,%acc1
+    6ea8:	a6d3 4836      	macl %d6,%d4,%a3@&,%a3,%acc2
+    6eac:	a413 4826      	macl %d6,%d4,%a3@&,%d2,%acc1
+    6eb0:	a493 4836      	macl %d6,%d4,%a3@&,%d2,%acc2
+    6eb4:	ae53 4826      	macl %d6,%d4,%a3@&,%sp,%acc1
+    6eb8:	aed3 4836      	macl %d6,%d4,%a3@&,%sp,%acc2
+    6ebc:	a21a 4806      	macl %d6,%d4,%a2@\+,%d1,%acc1
+    6ec0:	a29a 4816      	macl %d6,%d4,%a2@\+,%d1,%acc2
+    6ec4:	a65a 4806      	macl %d6,%d4,%a2@\+,%a3,%acc1
+    6ec8:	a6da 4816      	macl %d6,%d4,%a2@\+,%a3,%acc2
+    6ecc:	a41a 4806      	macl %d6,%d4,%a2@\+,%d2,%acc1
+    6ed0:	a49a 4816      	macl %d6,%d4,%a2@\+,%d2,%acc2
+    6ed4:	ae5a 4806      	macl %d6,%d4,%a2@\+,%sp,%acc1
+    6ed8:	aeda 4816      	macl %d6,%d4,%a2@\+,%sp,%acc2
+    6edc:	a21a 4826      	macl %d6,%d4,%a2@\+&,%d1,%acc1
+    6ee0:	a29a 4836      	macl %d6,%d4,%a2@\+&,%d1,%acc2
+    6ee4:	a65a 4826      	macl %d6,%d4,%a2@\+&,%a3,%acc1
+    6ee8:	a6da 4836      	macl %d6,%d4,%a2@\+&,%a3,%acc2
+    6eec:	a41a 4826      	macl %d6,%d4,%a2@\+&,%d2,%acc1
+    6ef0:	a49a 4836      	macl %d6,%d4,%a2@\+&,%d2,%acc2
+    6ef4:	ae5a 4826      	macl %d6,%d4,%a2@\+&,%sp,%acc1
+    6ef8:	aeda 4836      	macl %d6,%d4,%a2@\+&,%sp,%acc2
+    6efc:	a22e 4806 000a 	macl %d6,%d4,%fp@\(10\),%d1,%acc1
+    6f02:	a2ae 4816 000a 	macl %d6,%d4,%fp@\(10\),%d1,%acc2
+    6f08:	a66e 4806 000a 	macl %d6,%d4,%fp@\(10\),%a3,%acc1
+    6f0e:	a6ee 4816 000a 	macl %d6,%d4,%fp@\(10\),%a3,%acc2
+    6f14:	a42e 4806 000a 	macl %d6,%d4,%fp@\(10\),%d2,%acc1
+    6f1a:	a4ae 4816 000a 	macl %d6,%d4,%fp@\(10\),%d2,%acc2
+    6f20:	ae6e 4806 000a 	macl %d6,%d4,%fp@\(10\),%sp,%acc1
+    6f26:	aeee 4816 000a 	macl %d6,%d4,%fp@\(10\),%sp,%acc2
+    6f2c:	a22e 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%d1,%acc1
+    6f32:	a2ae 4836 000a 	macl %d6,%d4,%fp@\(10\)&,%d1,%acc2
+    6f38:	a66e 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%a3,%acc1
+    6f3e:	a6ee 4836 000a 	macl %d6,%d4,%fp@\(10\)&,%a3,%acc2
+    6f44:	a42e 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%d2,%acc1
+    6f4a:	a4ae 4836 000a 	macl %d6,%d4,%fp@\(10\)&,%d2,%acc2
+    6f50:	ae6e 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%sp,%acc1
+    6f56:	aeee 4836 000a 	macl %d6,%d4,%fp@\(10\)&,%sp,%acc2
+    6f5c:	a221 4806      	macl %d6,%d4,%a1@-,%d1,%acc1
+    6f60:	a2a1 4816      	macl %d6,%d4,%a1@-,%d1,%acc2
+    6f64:	a661 4806      	macl %d6,%d4,%a1@-,%a3,%acc1
+    6f68:	a6e1 4816      	macl %d6,%d4,%a1@-,%a3,%acc2
+    6f6c:	a421 4806      	macl %d6,%d4,%a1@-,%d2,%acc1
+    6f70:	a4a1 4816      	macl %d6,%d4,%a1@-,%d2,%acc2
+    6f74:	ae61 4806      	macl %d6,%d4,%a1@-,%sp,%acc1
+    6f78:	aee1 4816      	macl %d6,%d4,%a1@-,%sp,%acc2
+    6f7c:	a221 4826      	macl %d6,%d4,%a1@-&,%d1,%acc1
+    6f80:	a2a1 4836      	macl %d6,%d4,%a1@-&,%d1,%acc2
+    6f84:	a661 4826      	macl %d6,%d4,%a1@-&,%a3,%acc1
+    6f88:	a6e1 4836      	macl %d6,%d4,%a1@-&,%a3,%acc2
+    6f8c:	a421 4826      	macl %d6,%d4,%a1@-&,%d2,%acc1
+    6f90:	a4a1 4836      	macl %d6,%d4,%a1@-&,%d2,%acc2
+    6f94:	ae61 4826      	macl %d6,%d4,%a1@-&,%sp,%acc1
+    6f98:	aee1 4836      	macl %d6,%d4,%a1@-&,%sp,%acc2
+    6f9c:	a213 4a06      	macl %d6,%d4,<<,%a3@,%d1,%acc1
+    6fa0:	a293 4a16      	macl %d6,%d4,<<,%a3@,%d1,%acc2
+    6fa4:	a653 4a06      	macl %d6,%d4,<<,%a3@,%a3,%acc1
+    6fa8:	a6d3 4a16      	macl %d6,%d4,<<,%a3@,%a3,%acc2
+    6fac:	a413 4a06      	macl %d6,%d4,<<,%a3@,%d2,%acc1
+    6fb0:	a493 4a16      	macl %d6,%d4,<<,%a3@,%d2,%acc2
+    6fb4:	ae53 4a06      	macl %d6,%d4,<<,%a3@,%sp,%acc1
+    6fb8:	aed3 4a16      	macl %d6,%d4,<<,%a3@,%sp,%acc2
+    6fbc:	a213 4a26      	macl %d6,%d4,<<,%a3@&,%d1,%acc1
+    6fc0:	a293 4a36      	macl %d6,%d4,<<,%a3@&,%d1,%acc2
+    6fc4:	a653 4a26      	macl %d6,%d4,<<,%a3@&,%a3,%acc1
+    6fc8:	a6d3 4a36      	macl %d6,%d4,<<,%a3@&,%a3,%acc2
+    6fcc:	a413 4a26      	macl %d6,%d4,<<,%a3@&,%d2,%acc1
+    6fd0:	a493 4a36      	macl %d6,%d4,<<,%a3@&,%d2,%acc2
+    6fd4:	ae53 4a26      	macl %d6,%d4,<<,%a3@&,%sp,%acc1
+    6fd8:	aed3 4a36      	macl %d6,%d4,<<,%a3@&,%sp,%acc2
+    6fdc:	a21a 4a06      	macl %d6,%d4,<<,%a2@\+,%d1,%acc1
+    6fe0:	a29a 4a16      	macl %d6,%d4,<<,%a2@\+,%d1,%acc2
+    6fe4:	a65a 4a06      	macl %d6,%d4,<<,%a2@\+,%a3,%acc1
+    6fe8:	a6da 4a16      	macl %d6,%d4,<<,%a2@\+,%a3,%acc2
+    6fec:	a41a 4a06      	macl %d6,%d4,<<,%a2@\+,%d2,%acc1
+    6ff0:	a49a 4a16      	macl %d6,%d4,<<,%a2@\+,%d2,%acc2
+    6ff4:	ae5a 4a06      	macl %d6,%d4,<<,%a2@\+,%sp,%acc1
+    6ff8:	aeda 4a16      	macl %d6,%d4,<<,%a2@\+,%sp,%acc2
+    6ffc:	a21a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d1,%acc1
+    7000:	a29a 4a36      	macl %d6,%d4,<<,%a2@\+&,%d1,%acc2
+    7004:	a65a 4a26      	macl %d6,%d4,<<,%a2@\+&,%a3,%acc1
+    7008:	a6da 4a36      	macl %d6,%d4,<<,%a2@\+&,%a3,%acc2
+    700c:	a41a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d2,%acc1
+    7010:	a49a 4a36      	macl %d6,%d4,<<,%a2@\+&,%d2,%acc2
+    7014:	ae5a 4a26      	macl %d6,%d4,<<,%a2@\+&,%sp,%acc1
+    7018:	aeda 4a36      	macl %d6,%d4,<<,%a2@\+&,%sp,%acc2
+    701c:	a22e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1,%acc1
+    7022:	a2ae 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1,%acc2
+    7028:	a66e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3,%acc1
+    702e:	a6ee 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3,%acc2
+    7034:	a42e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2,%acc1
+    703a:	a4ae 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2,%acc2
+    7040:	ae6e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp,%acc1
+    7046:	aeee 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp,%acc2
+    704c:	a22e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1,%acc1
+    7052:	a2ae 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1,%acc2
+    7058:	a66e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3,%acc1
+    705e:	a6ee 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3,%acc2
+    7064:	a42e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2,%acc1
+    706a:	a4ae 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2,%acc2
+    7070:	ae6e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp,%acc1
+    7076:	aeee 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp,%acc2
+    707c:	a221 4a06      	macl %d6,%d4,<<,%a1@-,%d1,%acc1
+    7080:	a2a1 4a16      	macl %d6,%d4,<<,%a1@-,%d1,%acc2
+    7084:	a661 4a06      	macl %d6,%d4,<<,%a1@-,%a3,%acc1
+    7088:	a6e1 4a16      	macl %d6,%d4,<<,%a1@-,%a3,%acc2
+    708c:	a421 4a06      	macl %d6,%d4,<<,%a1@-,%d2,%acc1
+    7090:	a4a1 4a16      	macl %d6,%d4,<<,%a1@-,%d2,%acc2
+    7094:	ae61 4a06      	macl %d6,%d4,<<,%a1@-,%sp,%acc1
+    7098:	aee1 4a16      	macl %d6,%d4,<<,%a1@-,%sp,%acc2
+    709c:	a221 4a26      	macl %d6,%d4,<<,%a1@-&,%d1,%acc1
+    70a0:	a2a1 4a36      	macl %d6,%d4,<<,%a1@-&,%d1,%acc2
+    70a4:	a661 4a26      	macl %d6,%d4,<<,%a1@-&,%a3,%acc1
+    70a8:	a6e1 4a36      	macl %d6,%d4,<<,%a1@-&,%a3,%acc2
+    70ac:	a421 4a26      	macl %d6,%d4,<<,%a1@-&,%d2,%acc1
+    70b0:	a4a1 4a36      	macl %d6,%d4,<<,%a1@-&,%d2,%acc2
+    70b4:	ae61 4a26      	macl %d6,%d4,<<,%a1@-&,%sp,%acc1
+    70b8:	aee1 4a36      	macl %d6,%d4,<<,%a1@-&,%sp,%acc2
+    70bc:	a213 4e06      	macl %d6,%d4,>>,%a3@,%d1,%acc1
+    70c0:	a293 4e16      	macl %d6,%d4,>>,%a3@,%d1,%acc2
+    70c4:	a653 4e06      	macl %d6,%d4,>>,%a3@,%a3,%acc1
+    70c8:	a6d3 4e16      	macl %d6,%d4,>>,%a3@,%a3,%acc2
+    70cc:	a413 4e06      	macl %d6,%d4,>>,%a3@,%d2,%acc1
+    70d0:	a493 4e16      	macl %d6,%d4,>>,%a3@,%d2,%acc2
+    70d4:	ae53 4e06      	macl %d6,%d4,>>,%a3@,%sp,%acc1
+    70d8:	aed3 4e16      	macl %d6,%d4,>>,%a3@,%sp,%acc2
+    70dc:	a213 4e26      	macl %d6,%d4,>>,%a3@&,%d1,%acc1
+    70e0:	a293 4e36      	macl %d6,%d4,>>,%a3@&,%d1,%acc2
+    70e4:	a653 4e26      	macl %d6,%d4,>>,%a3@&,%a3,%acc1
+    70e8:	a6d3 4e36      	macl %d6,%d4,>>,%a3@&,%a3,%acc2
+    70ec:	a413 4e26      	macl %d6,%d4,>>,%a3@&,%d2,%acc1
+    70f0:	a493 4e36      	macl %d6,%d4,>>,%a3@&,%d2,%acc2
+    70f4:	ae53 4e26      	macl %d6,%d4,>>,%a3@&,%sp,%acc1
+    70f8:	aed3 4e36      	macl %d6,%d4,>>,%a3@&,%sp,%acc2
+    70fc:	a21a 4e06      	macl %d6,%d4,>>,%a2@\+,%d1,%acc1
+    7100:	a29a 4e16      	macl %d6,%d4,>>,%a2@\+,%d1,%acc2
+    7104:	a65a 4e06      	macl %d6,%d4,>>,%a2@\+,%a3,%acc1
+    7108:	a6da 4e16      	macl %d6,%d4,>>,%a2@\+,%a3,%acc2
+    710c:	a41a 4e06      	macl %d6,%d4,>>,%a2@\+,%d2,%acc1
+    7110:	a49a 4e16      	macl %d6,%d4,>>,%a2@\+,%d2,%acc2
+    7114:	ae5a 4e06      	macl %d6,%d4,>>,%a2@\+,%sp,%acc1
+    7118:	aeda 4e16      	macl %d6,%d4,>>,%a2@\+,%sp,%acc2
+    711c:	a21a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d1,%acc1
+    7120:	a29a 4e36      	macl %d6,%d4,>>,%a2@\+&,%d1,%acc2
+    7124:	a65a 4e26      	macl %d6,%d4,>>,%a2@\+&,%a3,%acc1
+    7128:	a6da 4e36      	macl %d6,%d4,>>,%a2@\+&,%a3,%acc2
+    712c:	a41a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d2,%acc1
+    7130:	a49a 4e36      	macl %d6,%d4,>>,%a2@\+&,%d2,%acc2
+    7134:	ae5a 4e26      	macl %d6,%d4,>>,%a2@\+&,%sp,%acc1
+    7138:	aeda 4e36      	macl %d6,%d4,>>,%a2@\+&,%sp,%acc2
+    713c:	a22e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1,%acc1
+    7142:	a2ae 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1,%acc2
+    7148:	a66e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3,%acc1
+    714e:	a6ee 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3,%acc2
+    7154:	a42e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2,%acc1
+    715a:	a4ae 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2,%acc2
+    7160:	ae6e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp,%acc1
+    7166:	aeee 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp,%acc2
+    716c:	a22e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1,%acc1
+    7172:	a2ae 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1,%acc2
+    7178:	a66e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3,%acc1
+    717e:	a6ee 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3,%acc2
+    7184:	a42e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2,%acc1
+    718a:	a4ae 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2,%acc2
+    7190:	ae6e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp,%acc1
+    7196:	aeee 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp,%acc2
+    719c:	a221 4e06      	macl %d6,%d4,>>,%a1@-,%d1,%acc1
+    71a0:	a2a1 4e16      	macl %d6,%d4,>>,%a1@-,%d1,%acc2
+    71a4:	a661 4e06      	macl %d6,%d4,>>,%a1@-,%a3,%acc1
+    71a8:	a6e1 4e16      	macl %d6,%d4,>>,%a1@-,%a3,%acc2
+    71ac:	a421 4e06      	macl %d6,%d4,>>,%a1@-,%d2,%acc1
+    71b0:	a4a1 4e16      	macl %d6,%d4,>>,%a1@-,%d2,%acc2
+    71b4:	ae61 4e06      	macl %d6,%d4,>>,%a1@-,%sp,%acc1
+    71b8:	aee1 4e16      	macl %d6,%d4,>>,%a1@-,%sp,%acc2
+    71bc:	a221 4e26      	macl %d6,%d4,>>,%a1@-&,%d1,%acc1
+    71c0:	a2a1 4e36      	macl %d6,%d4,>>,%a1@-&,%d1,%acc2
+    71c4:	a661 4e26      	macl %d6,%d4,>>,%a1@-&,%a3,%acc1
+    71c8:	a6e1 4e36      	macl %d6,%d4,>>,%a1@-&,%a3,%acc2
+    71cc:	a421 4e26      	macl %d6,%d4,>>,%a1@-&,%d2,%acc1
+    71d0:	a4a1 4e36      	macl %d6,%d4,>>,%a1@-&,%d2,%acc2
+    71d4:	ae61 4e26      	macl %d6,%d4,>>,%a1@-&,%sp,%acc1
+    71d8:	aee1 4e36      	macl %d6,%d4,>>,%a1@-&,%sp,%acc2
+    71dc:	a213 4a06      	macl %d6,%d4,<<,%a3@,%d1,%acc1
+    71e0:	a293 4a16      	macl %d6,%d4,<<,%a3@,%d1,%acc2
+    71e4:	a653 4a06      	macl %d6,%d4,<<,%a3@,%a3,%acc1
+    71e8:	a6d3 4a16      	macl %d6,%d4,<<,%a3@,%a3,%acc2
+    71ec:	a413 4a06      	macl %d6,%d4,<<,%a3@,%d2,%acc1
+    71f0:	a493 4a16      	macl %d6,%d4,<<,%a3@,%d2,%acc2
+    71f4:	ae53 4a06      	macl %d6,%d4,<<,%a3@,%sp,%acc1
+    71f8:	aed3 4a16      	macl %d6,%d4,<<,%a3@,%sp,%acc2
+    71fc:	a213 4a26      	macl %d6,%d4,<<,%a3@&,%d1,%acc1
+    7200:	a293 4a36      	macl %d6,%d4,<<,%a3@&,%d1,%acc2
+    7204:	a653 4a26      	macl %d6,%d4,<<,%a3@&,%a3,%acc1
+    7208:	a6d3 4a36      	macl %d6,%d4,<<,%a3@&,%a3,%acc2
+    720c:	a413 4a26      	macl %d6,%d4,<<,%a3@&,%d2,%acc1
+    7210:	a493 4a36      	macl %d6,%d4,<<,%a3@&,%d2,%acc2
+    7214:	ae53 4a26      	macl %d6,%d4,<<,%a3@&,%sp,%acc1
+    7218:	aed3 4a36      	macl %d6,%d4,<<,%a3@&,%sp,%acc2
+    721c:	a21a 4a06      	macl %d6,%d4,<<,%a2@\+,%d1,%acc1
+    7220:	a29a 4a16      	macl %d6,%d4,<<,%a2@\+,%d1,%acc2
+    7224:	a65a 4a06      	macl %d6,%d4,<<,%a2@\+,%a3,%acc1
+    7228:	a6da 4a16      	macl %d6,%d4,<<,%a2@\+,%a3,%acc2
+    722c:	a41a 4a06      	macl %d6,%d4,<<,%a2@\+,%d2,%acc1
+    7230:	a49a 4a16      	macl %d6,%d4,<<,%a2@\+,%d2,%acc2
+    7234:	ae5a 4a06      	macl %d6,%d4,<<,%a2@\+,%sp,%acc1
+    7238:	aeda 4a16      	macl %d6,%d4,<<,%a2@\+,%sp,%acc2
+    723c:	a21a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d1,%acc1
+    7240:	a29a 4a36      	macl %d6,%d4,<<,%a2@\+&,%d1,%acc2
+    7244:	a65a 4a26      	macl %d6,%d4,<<,%a2@\+&,%a3,%acc1
+    7248:	a6da 4a36      	macl %d6,%d4,<<,%a2@\+&,%a3,%acc2
+    724c:	a41a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d2,%acc1
+    7250:	a49a 4a36      	macl %d6,%d4,<<,%a2@\+&,%d2,%acc2
+    7254:	ae5a 4a26      	macl %d6,%d4,<<,%a2@\+&,%sp,%acc1
+    7258:	aeda 4a36      	macl %d6,%d4,<<,%a2@\+&,%sp,%acc2
+    725c:	a22e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1,%acc1
+    7262:	a2ae 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1,%acc2
+    7268:	a66e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3,%acc1
+    726e:	a6ee 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3,%acc2
+    7274:	a42e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2,%acc1
+    727a:	a4ae 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2,%acc2
+    7280:	ae6e 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp,%acc1
+    7286:	aeee 4a16 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp,%acc2
+    728c:	a22e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1,%acc1
+    7292:	a2ae 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1,%acc2
+    7298:	a66e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3,%acc1
+    729e:	a6ee 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3,%acc2
+    72a4:	a42e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2,%acc1
+    72aa:	a4ae 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2,%acc2
+    72b0:	ae6e 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp,%acc1
+    72b6:	aeee 4a36 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp,%acc2
+    72bc:	a221 4a06      	macl %d6,%d4,<<,%a1@-,%d1,%acc1
+    72c0:	a2a1 4a16      	macl %d6,%d4,<<,%a1@-,%d1,%acc2
+    72c4:	a661 4a06      	macl %d6,%d4,<<,%a1@-,%a3,%acc1
+    72c8:	a6e1 4a16      	macl %d6,%d4,<<,%a1@-,%a3,%acc2
+    72cc:	a421 4a06      	macl %d6,%d4,<<,%a1@-,%d2,%acc1
+    72d0:	a4a1 4a16      	macl %d6,%d4,<<,%a1@-,%d2,%acc2
+    72d4:	ae61 4a06      	macl %d6,%d4,<<,%a1@-,%sp,%acc1
+    72d8:	aee1 4a16      	macl %d6,%d4,<<,%a1@-,%sp,%acc2
+    72dc:	a221 4a26      	macl %d6,%d4,<<,%a1@-&,%d1,%acc1
+    72e0:	a2a1 4a36      	macl %d6,%d4,<<,%a1@-&,%d1,%acc2
+    72e4:	a661 4a26      	macl %d6,%d4,<<,%a1@-&,%a3,%acc1
+    72e8:	a6e1 4a36      	macl %d6,%d4,<<,%a1@-&,%a3,%acc2
+    72ec:	a421 4a26      	macl %d6,%d4,<<,%a1@-&,%d2,%acc1
+    72f0:	a4a1 4a36      	macl %d6,%d4,<<,%a1@-&,%d2,%acc2
+    72f4:	ae61 4a26      	macl %d6,%d4,<<,%a1@-&,%sp,%acc1
+    72f8:	aee1 4a36      	macl %d6,%d4,<<,%a1@-&,%sp,%acc2
+    72fc:	a213 4e06      	macl %d6,%d4,>>,%a3@,%d1,%acc1
+    7300:	a293 4e16      	macl %d6,%d4,>>,%a3@,%d1,%acc2
+    7304:	a653 4e06      	macl %d6,%d4,>>,%a3@,%a3,%acc1
+    7308:	a6d3 4e16      	macl %d6,%d4,>>,%a3@,%a3,%acc2
+    730c:	a413 4e06      	macl %d6,%d4,>>,%a3@,%d2,%acc1
+    7310:	a493 4e16      	macl %d6,%d4,>>,%a3@,%d2,%acc2
+    7314:	ae53 4e06      	macl %d6,%d4,>>,%a3@,%sp,%acc1
+    7318:	aed3 4e16      	macl %d6,%d4,>>,%a3@,%sp,%acc2
+    731c:	a213 4e26      	macl %d6,%d4,>>,%a3@&,%d1,%acc1
+    7320:	a293 4e36      	macl %d6,%d4,>>,%a3@&,%d1,%acc2
+    7324:	a653 4e26      	macl %d6,%d4,>>,%a3@&,%a3,%acc1
+    7328:	a6d3 4e36      	macl %d6,%d4,>>,%a3@&,%a3,%acc2
+    732c:	a413 4e26      	macl %d6,%d4,>>,%a3@&,%d2,%acc1
+    7330:	a493 4e36      	macl %d6,%d4,>>,%a3@&,%d2,%acc2
+    7334:	ae53 4e26      	macl %d6,%d4,>>,%a3@&,%sp,%acc1
+    7338:	aed3 4e36      	macl %d6,%d4,>>,%a3@&,%sp,%acc2
+    733c:	a21a 4e06      	macl %d6,%d4,>>,%a2@\+,%d1,%acc1
+    7340:	a29a 4e16      	macl %d6,%d4,>>,%a2@\+,%d1,%acc2
+    7344:	a65a 4e06      	macl %d6,%d4,>>,%a2@\+,%a3,%acc1
+    7348:	a6da 4e16      	macl %d6,%d4,>>,%a2@\+,%a3,%acc2
+    734c:	a41a 4e06      	macl %d6,%d4,>>,%a2@\+,%d2,%acc1
+    7350:	a49a 4e16      	macl %d6,%d4,>>,%a2@\+,%d2,%acc2
+    7354:	ae5a 4e06      	macl %d6,%d4,>>,%a2@\+,%sp,%acc1
+    7358:	aeda 4e16      	macl %d6,%d4,>>,%a2@\+,%sp,%acc2
+    735c:	a21a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d1,%acc1
+    7360:	a29a 4e36      	macl %d6,%d4,>>,%a2@\+&,%d1,%acc2
+    7364:	a65a 4e26      	macl %d6,%d4,>>,%a2@\+&,%a3,%acc1
+    7368:	a6da 4e36      	macl %d6,%d4,>>,%a2@\+&,%a3,%acc2
+    736c:	a41a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d2,%acc1
+    7370:	a49a 4e36      	macl %d6,%d4,>>,%a2@\+&,%d2,%acc2
+    7374:	ae5a 4e26      	macl %d6,%d4,>>,%a2@\+&,%sp,%acc1
+    7378:	aeda 4e36      	macl %d6,%d4,>>,%a2@\+&,%sp,%acc2
+    737c:	a22e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1,%acc1
+    7382:	a2ae 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1,%acc2
+    7388:	a66e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3,%acc1
+    738e:	a6ee 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3,%acc2
+    7394:	a42e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2,%acc1
+    739a:	a4ae 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2,%acc2
+    73a0:	ae6e 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp,%acc1
+    73a6:	aeee 4e16 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp,%acc2
+    73ac:	a22e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1,%acc1
+    73b2:	a2ae 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1,%acc2
+    73b8:	a66e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3,%acc1
+    73be:	a6ee 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3,%acc2
+    73c4:	a42e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2,%acc1
+    73ca:	a4ae 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2,%acc2
+    73d0:	ae6e 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp,%acc1
+    73d6:	aeee 4e36 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp,%acc2
+    73dc:	a221 4e06      	macl %d6,%d4,>>,%a1@-,%d1,%acc1
+    73e0:	a2a1 4e16      	macl %d6,%d4,>>,%a1@-,%d1,%acc2
+    73e4:	a661 4e06      	macl %d6,%d4,>>,%a1@-,%a3,%acc1
+    73e8:	a6e1 4e16      	macl %d6,%d4,>>,%a1@-,%a3,%acc2
+    73ec:	a421 4e06      	macl %d6,%d4,>>,%a1@-,%d2,%acc1
+    73f0:	a4a1 4e16      	macl %d6,%d4,>>,%a1@-,%d2,%acc2
+    73f4:	ae61 4e06      	macl %d6,%d4,>>,%a1@-,%sp,%acc1
+    73f8:	aee1 4e16      	macl %d6,%d4,>>,%a1@-,%sp,%acc2
+    73fc:	a221 4e26      	macl %d6,%d4,>>,%a1@-&,%d1,%acc1
+    7400:	a2a1 4e36      	macl %d6,%d4,>>,%a1@-&,%d1,%acc2
+    7404:	a661 4e26      	macl %d6,%d4,>>,%a1@-&,%a3,%acc1
+    7408:	a6e1 4e36      	macl %d6,%d4,>>,%a1@-&,%a3,%acc2
+    740c:	a421 4e26      	macl %d6,%d4,>>,%a1@-&,%d2,%acc1
+    7410:	a4a1 4e36      	macl %d6,%d4,>>,%a1@-&,%d2,%acc2
+    7414:	ae61 4e26      	macl %d6,%d4,>>,%a1@-&,%sp,%acc1
+    7418:	aee1 4e36      	macl %d6,%d4,>>,%a1@-&,%sp,%acc2
diff --git a/gas/testsuite/gas/m68k/mcf-emac.s b/gas/testsuite/gas/m68k/mcf-emac.s
new file mode 100644
index 000000000000..348191f65269
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-emac.s
@@ -0,0 +1,6660 @@
+	.text
+	mac.w   %d1l,%a1u,<<,%acc0             | 
+	mac.w   %d1l,%a5u,<<,(%a0),%a1,%acc0
+	mac.w   %d5l,%a3u,<<,(%a0)&,%d2,%acc0
+
+	move.l      #12345678,%acc0
+	move.l	%d1,%acc1
+	move.l      #12345678,%acc1
+	move.l      #12345678,%acc2
+	move.l	%a1,%acc1
+	move.l      #12345678,%acc3
+
+	mac.w   %d3u,%a4l,>>,%acc1
+	mac.w   %d5u,%a6l,%acc1
+
+	mac.l       %d2,%d3,%acc0
+	mac.l       %d2,%d3,%acc1
+	mac.l       %d2,%d3,%acc2
+	mac.l       %d2,%d3,%acc3
+
+	movclr.l  %acc0,%d1
+	movclr.l  %acc1,%a2
+	movclr.l  %acc2,%d3
+	movclr.l  %acc3,%a5
+
+	move.l %acc1,%d1
+	move.l %acc3,%a3
+	move.l %acc0,%d5
+	move.l %acc1,%a7
+
+	move.l %acc0,%acc0
+	move.l %acc0,%acc1
+	move.l %acc0,%acc2
+	move.l %acc0,%acc3
+	move.l %acc1,%acc0
+	move.l %acc1,%acc1
+	move.l %acc1,%acc2
+	move.l %acc1,%acc3
+	move.l %acc2,%acc0
+	move.l %acc2,%acc1
+	move.l %acc2,%acc2
+	move.l %acc2,%acc3
+	move.l %acc3,%acc0
+	move.l %acc3,%acc1
+	move.l %acc3,%acc2
+	move.l %acc3,%acc3
+
+	move.l %accext01,%a0
+	move.l %accext23,%a7
+
+	move.l %acc0,%d0
+	move.l %acc1,%a1
+	move.l %acc2,%d2
+	move.l %acc3,%a3
+
+	| Automated mac insns for testing
+	
+	mac.w %a1l,%a2u,%acc1
+	mac.w %a1l,%a2u,%acc2
+	mac.w %a1l,%a2u,<<,%acc1
+	mac.w %a1l,%a2u,<<,%acc2
+	mac.w %a1l,%a2u,>>,%acc1
+	mac.w %a1l,%a2u,>>,%acc2
+	mac.w %a1l,%a2u,#1,%acc1
+	mac.w %a1l,%a2u,#1,%acc2
+	mac.w %a1l,%a2u,#-1,%acc1
+	mac.w %a1l,%a2u,#-1,%acc2
+	mac.w %a1l,%d3l,%acc1
+	mac.w %a1l,%d3l,%acc2
+	mac.w %a1l,%d3l,<<,%acc1
+	mac.w %a1l,%d3l,<<,%acc2
+	mac.w %a1l,%d3l,>>,%acc1
+	mac.w %a1l,%d3l,>>,%acc2
+	mac.w %a1l,%d3l,#1,%acc1
+	mac.w %a1l,%d3l,#1,%acc2
+	mac.w %a1l,%d3l,#-1,%acc1
+	mac.w %a1l,%d3l,#-1,%acc2
+	mac.w %a1l,%a7u,%acc1
+	mac.w %a1l,%a7u,%acc2
+	mac.w %a1l,%a7u,<<,%acc1
+	mac.w %a1l,%a7u,<<,%acc2
+	mac.w %a1l,%a7u,>>,%acc1
+	mac.w %a1l,%a7u,>>,%acc2
+	mac.w %a1l,%a7u,#1,%acc1
+	mac.w %a1l,%a7u,#1,%acc2
+	mac.w %a1l,%a7u,#-1,%acc1
+	mac.w %a1l,%a7u,#-1,%acc2
+	mac.w %a1l,%d1l,%acc1
+	mac.w %a1l,%d1l,%acc2
+	mac.w %a1l,%d1l,<<,%acc1
+	mac.w %a1l,%d1l,<<,%acc2
+	mac.w %a1l,%d1l,>>,%acc1
+	mac.w %a1l,%d1l,>>,%acc2
+	mac.w %a1l,%d1l,#1,%acc1
+	mac.w %a1l,%d1l,#1,%acc2
+	mac.w %a1l,%d1l,#-1,%acc1
+	mac.w %a1l,%d1l,#-1,%acc2
+	mac.w %d2u,%a2u,%acc1
+	mac.w %d2u,%a2u,%acc2
+	mac.w %d2u,%a2u,<<,%acc1
+	mac.w %d2u,%a2u,<<,%acc2
+	mac.w %d2u,%a2u,>>,%acc1
+	mac.w %d2u,%a2u,>>,%acc2
+	mac.w %d2u,%a2u,#1,%acc1
+	mac.w %d2u,%a2u,#1,%acc2
+	mac.w %d2u,%a2u,#-1,%acc1
+	mac.w %d2u,%a2u,#-1,%acc2
+	mac.w %d2u,%d3l,%acc1
+	mac.w %d2u,%d3l,%acc2
+	mac.w %d2u,%d3l,<<,%acc1
+	mac.w %d2u,%d3l,<<,%acc2
+	mac.w %d2u,%d3l,>>,%acc1
+	mac.w %d2u,%d3l,>>,%acc2
+	mac.w %d2u,%d3l,#1,%acc1
+	mac.w %d2u,%d3l,#1,%acc2
+	mac.w %d2u,%d3l,#-1,%acc1
+	mac.w %d2u,%d3l,#-1,%acc2
+	mac.w %d2u,%a7u,%acc1
+	mac.w %d2u,%a7u,%acc2
+	mac.w %d2u,%a7u,<<,%acc1
+	mac.w %d2u,%a7u,<<,%acc2
+	mac.w %d2u,%a7u,>>,%acc1
+	mac.w %d2u,%a7u,>>,%acc2
+	mac.w %d2u,%a7u,#1,%acc1
+	mac.w %d2u,%a7u,#1,%acc2
+	mac.w %d2u,%a7u,#-1,%acc1
+	mac.w %d2u,%a7u,#-1,%acc2
+	mac.w %d2u,%d1l,%acc1
+	mac.w %d2u,%d1l,%acc2
+	mac.w %d2u,%d1l,<<,%acc1
+	mac.w %d2u,%d1l,<<,%acc2
+	mac.w %d2u,%d1l,>>,%acc1
+	mac.w %d2u,%d1l,>>,%acc2
+	mac.w %d2u,%d1l,#1,%acc1
+	mac.w %d2u,%d1l,#1,%acc2
+	mac.w %d2u,%d1l,#-1,%acc1
+	mac.w %d2u,%d1l,#-1,%acc2
+	mac.w %a5l,%a2u,%acc1
+	mac.w %a5l,%a2u,%acc2
+	mac.w %a5l,%a2u,<<,%acc1
+	mac.w %a5l,%a2u,<<,%acc2
+	mac.w %a5l,%a2u,>>,%acc1
+	mac.w %a5l,%a2u,>>,%acc2
+	mac.w %a5l,%a2u,#1,%acc1
+	mac.w %a5l,%a2u,#1,%acc2
+	mac.w %a5l,%a2u,#-1,%acc1
+	mac.w %a5l,%a2u,#-1,%acc2
+	mac.w %a5l,%d3l,%acc1
+	mac.w %a5l,%d3l,%acc2
+	mac.w %a5l,%d3l,<<,%acc1
+	mac.w %a5l,%d3l,<<,%acc2
+	mac.w %a5l,%d3l,>>,%acc1
+	mac.w %a5l,%d3l,>>,%acc2
+	mac.w %a5l,%d3l,#1,%acc1
+	mac.w %a5l,%d3l,#1,%acc2
+	mac.w %a5l,%d3l,#-1,%acc1
+	mac.w %a5l,%d3l,#-1,%acc2
+	mac.w %a5l,%a7u,%acc1
+	mac.w %a5l,%a7u,%acc2
+	mac.w %a5l,%a7u,<<,%acc1
+	mac.w %a5l,%a7u,<<,%acc2
+	mac.w %a5l,%a7u,>>,%acc1
+	mac.w %a5l,%a7u,>>,%acc2
+	mac.w %a5l,%a7u,#1,%acc1
+	mac.w %a5l,%a7u,#1,%acc2
+	mac.w %a5l,%a7u,#-1,%acc1
+	mac.w %a5l,%a7u,#-1,%acc2
+	mac.w %a5l,%d1l,%acc1
+	mac.w %a5l,%d1l,%acc2
+	mac.w %a5l,%d1l,<<,%acc1
+	mac.w %a5l,%d1l,<<,%acc2
+	mac.w %a5l,%d1l,>>,%acc1
+	mac.w %a5l,%d1l,>>,%acc2
+	mac.w %a5l,%d1l,#1,%acc1
+	mac.w %a5l,%d1l,#1,%acc2
+	mac.w %a5l,%d1l,#-1,%acc1
+	mac.w %a5l,%d1l,#-1,%acc2
+	mac.w %d6u,%a2u,%acc1
+	mac.w %d6u,%a2u,%acc2
+	mac.w %d6u,%a2u,<<,%acc1
+	mac.w %d6u,%a2u,<<,%acc2
+	mac.w %d6u,%a2u,>>,%acc1
+	mac.w %d6u,%a2u,>>,%acc2
+	mac.w %d6u,%a2u,#1,%acc1
+	mac.w %d6u,%a2u,#1,%acc2
+	mac.w %d6u,%a2u,#-1,%acc1
+	mac.w %d6u,%a2u,#-1,%acc2
+	mac.w %d6u,%d3l,%acc1
+	mac.w %d6u,%d3l,%acc2
+	mac.w %d6u,%d3l,<<,%acc1
+	mac.w %d6u,%d3l,<<,%acc2
+	mac.w %d6u,%d3l,>>,%acc1
+	mac.w %d6u,%d3l,>>,%acc2
+	mac.w %d6u,%d3l,#1,%acc1
+	mac.w %d6u,%d3l,#1,%acc2
+	mac.w %d6u,%d3l,#-1,%acc1
+	mac.w %d6u,%d3l,#-1,%acc2
+	mac.w %d6u,%a7u,%acc1
+	mac.w %d6u,%a7u,%acc2
+	mac.w %d6u,%a7u,<<,%acc1
+	mac.w %d6u,%a7u,<<,%acc2
+	mac.w %d6u,%a7u,>>,%acc1
+	mac.w %d6u,%a7u,>>,%acc2
+	mac.w %d6u,%a7u,#1,%acc1
+	mac.w %d6u,%a7u,#1,%acc2
+	mac.w %d6u,%a7u,#-1,%acc1
+	mac.w %d6u,%a7u,#-1,%acc2
+	mac.w %d6u,%d1l,%acc1
+	mac.w %d6u,%d1l,%acc2
+	mac.w %d6u,%d1l,<<,%acc1
+	mac.w %d6u,%d1l,<<,%acc2
+	mac.w %d6u,%d1l,>>,%acc1
+	mac.w %d6u,%d1l,>>,%acc2
+	mac.w %d6u,%d1l,#1,%acc1
+	mac.w %d6u,%d1l,#1,%acc2
+	mac.w %d6u,%d1l,#-1,%acc1
+	mac.w %d6u,%d1l,#-1,%acc2
+
+	mac.w %a1l,%a2u,(%a3),%d1,%acc1
+	mac.w %a1l,%a2u,(%a3),%d1,%acc2
+	mac.w %a1l,%a2u,(%a3),%a3,%acc1
+	mac.w %a1l,%a2u,(%a3),%a3,%acc2
+	mac.w %a1l,%a2u,(%a3),%d2,%acc1
+	mac.w %a1l,%a2u,(%a3),%d2,%acc2
+	mac.w %a1l,%a2u,(%a3),%a7,%acc1
+	mac.w %a1l,%a2u,(%a3),%a7,%acc2
+	mac.w %a1l,%a2u,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a2u,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a2u,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a2u,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a2u,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a2u,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a2u,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a2u,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a2u,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a2u,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a2u,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a2u,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a2u,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a2u,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a2u,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a2u,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a2u,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a2u,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a2u,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a2u,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a2u,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a2u,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a2u,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a2u,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a2u,10(%a6),%d1,%acc1
+	mac.w %a1l,%a2u,10(%a6),%d1,%acc2
+	mac.w %a1l,%a2u,10(%a6),%a3,%acc1
+	mac.w %a1l,%a2u,10(%a6),%a3,%acc2
+	mac.w %a1l,%a2u,10(%a6),%d2,%acc1
+	mac.w %a1l,%a2u,10(%a6),%d2,%acc2
+	mac.w %a1l,%a2u,10(%a6),%a7,%acc1
+	mac.w %a1l,%a2u,10(%a6),%a7,%acc2
+	mac.w %a1l,%a2u,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a2u,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a2u,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a2u,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a2u,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a2u,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a2u,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a2u,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a2u,-(%a1),%d1,%acc1
+	mac.w %a1l,%a2u,-(%a1),%d1,%acc2
+	mac.w %a1l,%a2u,-(%a1),%a3,%acc1
+	mac.w %a1l,%a2u,-(%a1),%a3,%acc2
+	mac.w %a1l,%a2u,-(%a1),%d2,%acc1
+	mac.w %a1l,%a2u,-(%a1),%d2,%acc2
+	mac.w %a1l,%a2u,-(%a1),%a7,%acc1
+	mac.w %a1l,%a2u,-(%a1),%a7,%acc2
+	mac.w %a1l,%a2u,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a2u,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a2u,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a2u,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a2u,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a2u,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a2u,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a2u,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a2u,<<,(%a3),%d1,%acc1
+	mac.w %a1l,%a2u,<<,(%a3),%d1,%acc2
+	mac.w %a1l,%a2u,<<,(%a3),%a3,%acc1
+	mac.w %a1l,%a2u,<<,(%a3),%a3,%acc2
+	mac.w %a1l,%a2u,<<,(%a3),%d2,%acc1
+	mac.w %a1l,%a2u,<<,(%a3),%d2,%acc2
+	mac.w %a1l,%a2u,<<,(%a3),%a7,%acc1
+	mac.w %a1l,%a2u,<<,(%a3),%a7,%acc2
+	mac.w %a1l,%a2u,<<,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a2u,<<,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a2u,<<,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a2u,<<,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a2u,<<,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a2u,<<,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a2u,<<,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a2u,<<,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6),%d1,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6),%d1,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6),%a3,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6),%a3,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6),%d2,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6),%d2,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6),%a7,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6),%a7,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1),%d1,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1),%d1,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1),%a3,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1),%a3,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1),%d2,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1),%d2,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1),%a7,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1),%a7,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a2u,>>,(%a3),%d1,%acc1
+	mac.w %a1l,%a2u,>>,(%a3),%d1,%acc2
+	mac.w %a1l,%a2u,>>,(%a3),%a3,%acc1
+	mac.w %a1l,%a2u,>>,(%a3),%a3,%acc2
+	mac.w %a1l,%a2u,>>,(%a3),%d2,%acc1
+	mac.w %a1l,%a2u,>>,(%a3),%d2,%acc2
+	mac.w %a1l,%a2u,>>,(%a3),%a7,%acc1
+	mac.w %a1l,%a2u,>>,(%a3),%a7,%acc2
+	mac.w %a1l,%a2u,>>,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a2u,>>,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a2u,>>,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a2u,>>,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a2u,>>,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a2u,>>,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a2u,>>,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a2u,>>,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6),%d1,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6),%d1,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6),%a3,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6),%a3,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6),%d2,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6),%d2,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6),%a7,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6),%a7,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1),%d1,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1),%d1,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1),%a3,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1),%a3,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1),%d2,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1),%d2,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1),%a7,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1),%a7,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a2u,#1,(%a3),%d1,%acc1
+	mac.w %a1l,%a2u,#1,(%a3),%d1,%acc2
+	mac.w %a1l,%a2u,#1,(%a3),%a3,%acc1
+	mac.w %a1l,%a2u,#1,(%a3),%a3,%acc2
+	mac.w %a1l,%a2u,#1,(%a3),%d2,%acc1
+	mac.w %a1l,%a2u,#1,(%a3),%d2,%acc2
+	mac.w %a1l,%a2u,#1,(%a3),%a7,%acc1
+	mac.w %a1l,%a2u,#1,(%a3),%a7,%acc2
+	mac.w %a1l,%a2u,#1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a2u,#1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a2u,#1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a2u,#1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a2u,#1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a2u,#1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a2u,#1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a2u,#1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6),%d1,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6),%d1,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6),%a3,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6),%a3,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6),%d2,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6),%d2,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6),%a7,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6),%a7,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1),%d1,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1),%d1,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1),%a3,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1),%a3,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1),%d2,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1),%d2,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1),%a7,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1),%a7,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3),%d1,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3),%d1,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3),%a3,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3),%a3,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3),%d2,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3),%d2,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3),%a7,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3),%a7,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6),%d1,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6),%d1,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6),%a3,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6),%a3,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6),%d2,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6),%d2,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6),%a7,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6),%a7,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1),%d1,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1),%d1,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1),%a3,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1),%a3,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1),%d2,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1),%d2,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1),%a7,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1),%a7,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d3l,(%a3),%d1,%acc1
+	mac.w %a1l,%d3l,(%a3),%d1,%acc2
+	mac.w %a1l,%d3l,(%a3),%a3,%acc1
+	mac.w %a1l,%d3l,(%a3),%a3,%acc2
+	mac.w %a1l,%d3l,(%a3),%d2,%acc1
+	mac.w %a1l,%d3l,(%a3),%d2,%acc2
+	mac.w %a1l,%d3l,(%a3),%a7,%acc1
+	mac.w %a1l,%d3l,(%a3),%a7,%acc2
+	mac.w %a1l,%d3l,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d3l,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d3l,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d3l,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d3l,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d3l,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d3l,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d3l,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d3l,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d3l,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d3l,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d3l,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d3l,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d3l,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d3l,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d3l,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d3l,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d3l,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d3l,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d3l,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d3l,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d3l,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d3l,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d3l,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d3l,10(%a6),%d1,%acc1
+	mac.w %a1l,%d3l,10(%a6),%d1,%acc2
+	mac.w %a1l,%d3l,10(%a6),%a3,%acc1
+	mac.w %a1l,%d3l,10(%a6),%a3,%acc2
+	mac.w %a1l,%d3l,10(%a6),%d2,%acc1
+	mac.w %a1l,%d3l,10(%a6),%d2,%acc2
+	mac.w %a1l,%d3l,10(%a6),%a7,%acc1
+	mac.w %a1l,%d3l,10(%a6),%a7,%acc2
+	mac.w %a1l,%d3l,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d3l,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d3l,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d3l,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d3l,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d3l,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d3l,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d3l,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d3l,-(%a1),%d1,%acc1
+	mac.w %a1l,%d3l,-(%a1),%d1,%acc2
+	mac.w %a1l,%d3l,-(%a1),%a3,%acc1
+	mac.w %a1l,%d3l,-(%a1),%a3,%acc2
+	mac.w %a1l,%d3l,-(%a1),%d2,%acc1
+	mac.w %a1l,%d3l,-(%a1),%d2,%acc2
+	mac.w %a1l,%d3l,-(%a1),%a7,%acc1
+	mac.w %a1l,%d3l,-(%a1),%a7,%acc2
+	mac.w %a1l,%d3l,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d3l,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d3l,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d3l,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d3l,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d3l,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d3l,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d3l,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d3l,<<,(%a3),%d1,%acc1
+	mac.w %a1l,%d3l,<<,(%a3),%d1,%acc2
+	mac.w %a1l,%d3l,<<,(%a3),%a3,%acc1
+	mac.w %a1l,%d3l,<<,(%a3),%a3,%acc2
+	mac.w %a1l,%d3l,<<,(%a3),%d2,%acc1
+	mac.w %a1l,%d3l,<<,(%a3),%d2,%acc2
+	mac.w %a1l,%d3l,<<,(%a3),%a7,%acc1
+	mac.w %a1l,%d3l,<<,(%a3),%a7,%acc2
+	mac.w %a1l,%d3l,<<,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d3l,<<,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d3l,<<,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d3l,<<,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d3l,<<,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d3l,<<,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d3l,<<,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d3l,<<,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6),%d1,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6),%d1,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6),%a3,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6),%a3,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6),%d2,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6),%d2,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6),%a7,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6),%a7,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1),%d1,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1),%d1,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1),%a3,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1),%a3,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1),%d2,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1),%d2,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1),%a7,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1),%a7,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d3l,>>,(%a3),%d1,%acc1
+	mac.w %a1l,%d3l,>>,(%a3),%d1,%acc2
+	mac.w %a1l,%d3l,>>,(%a3),%a3,%acc1
+	mac.w %a1l,%d3l,>>,(%a3),%a3,%acc2
+	mac.w %a1l,%d3l,>>,(%a3),%d2,%acc1
+	mac.w %a1l,%d3l,>>,(%a3),%d2,%acc2
+	mac.w %a1l,%d3l,>>,(%a3),%a7,%acc1
+	mac.w %a1l,%d3l,>>,(%a3),%a7,%acc2
+	mac.w %a1l,%d3l,>>,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d3l,>>,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d3l,>>,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d3l,>>,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d3l,>>,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d3l,>>,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d3l,>>,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d3l,>>,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6),%d1,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6),%d1,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6),%a3,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6),%a3,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6),%d2,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6),%d2,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6),%a7,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6),%a7,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1),%d1,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1),%d1,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1),%a3,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1),%a3,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1),%d2,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1),%d2,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1),%a7,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1),%a7,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d3l,#1,(%a3),%d1,%acc1
+	mac.w %a1l,%d3l,#1,(%a3),%d1,%acc2
+	mac.w %a1l,%d3l,#1,(%a3),%a3,%acc1
+	mac.w %a1l,%d3l,#1,(%a3),%a3,%acc2
+	mac.w %a1l,%d3l,#1,(%a3),%d2,%acc1
+	mac.w %a1l,%d3l,#1,(%a3),%d2,%acc2
+	mac.w %a1l,%d3l,#1,(%a3),%a7,%acc1
+	mac.w %a1l,%d3l,#1,(%a3),%a7,%acc2
+	mac.w %a1l,%d3l,#1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d3l,#1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d3l,#1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d3l,#1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d3l,#1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d3l,#1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d3l,#1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d3l,#1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6),%d1,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6),%d1,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6),%a3,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6),%a3,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6),%d2,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6),%d2,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6),%a7,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6),%a7,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1),%d1,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1),%d1,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1),%a3,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1),%a3,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1),%d2,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1),%d2,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1),%a7,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1),%a7,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3),%d1,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3),%d1,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3),%a3,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3),%a3,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3),%d2,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3),%d2,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3),%a7,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3),%a7,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6),%d1,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6),%d1,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6),%a3,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6),%a3,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6),%d2,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6),%d2,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6),%a7,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6),%a7,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1),%d1,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1),%d1,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1),%a3,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1),%a3,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1),%d2,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1),%d2,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1),%a7,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1),%a7,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a7u,(%a3),%d1,%acc1
+	mac.w %a1l,%a7u,(%a3),%d1,%acc2
+	mac.w %a1l,%a7u,(%a3),%a3,%acc1
+	mac.w %a1l,%a7u,(%a3),%a3,%acc2
+	mac.w %a1l,%a7u,(%a3),%d2,%acc1
+	mac.w %a1l,%a7u,(%a3),%d2,%acc2
+	mac.w %a1l,%a7u,(%a3),%a7,%acc1
+	mac.w %a1l,%a7u,(%a3),%a7,%acc2
+	mac.w %a1l,%a7u,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a7u,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a7u,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a7u,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a7u,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a7u,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a7u,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a7u,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a7u,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a7u,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a7u,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a7u,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a7u,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a7u,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a7u,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a7u,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a7u,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a7u,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a7u,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a7u,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a7u,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a7u,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a7u,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a7u,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a7u,10(%a6),%d1,%acc1
+	mac.w %a1l,%a7u,10(%a6),%d1,%acc2
+	mac.w %a1l,%a7u,10(%a6),%a3,%acc1
+	mac.w %a1l,%a7u,10(%a6),%a3,%acc2
+	mac.w %a1l,%a7u,10(%a6),%d2,%acc1
+	mac.w %a1l,%a7u,10(%a6),%d2,%acc2
+	mac.w %a1l,%a7u,10(%a6),%a7,%acc1
+	mac.w %a1l,%a7u,10(%a6),%a7,%acc2
+	mac.w %a1l,%a7u,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a7u,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a7u,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a7u,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a7u,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a7u,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a7u,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a7u,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a7u,-(%a1),%d1,%acc1
+	mac.w %a1l,%a7u,-(%a1),%d1,%acc2
+	mac.w %a1l,%a7u,-(%a1),%a3,%acc1
+	mac.w %a1l,%a7u,-(%a1),%a3,%acc2
+	mac.w %a1l,%a7u,-(%a1),%d2,%acc1
+	mac.w %a1l,%a7u,-(%a1),%d2,%acc2
+	mac.w %a1l,%a7u,-(%a1),%a7,%acc1
+	mac.w %a1l,%a7u,-(%a1),%a7,%acc2
+	mac.w %a1l,%a7u,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a7u,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a7u,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a7u,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a7u,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a7u,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a7u,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a7u,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a7u,<<,(%a3),%d1,%acc1
+	mac.w %a1l,%a7u,<<,(%a3),%d1,%acc2
+	mac.w %a1l,%a7u,<<,(%a3),%a3,%acc1
+	mac.w %a1l,%a7u,<<,(%a3),%a3,%acc2
+	mac.w %a1l,%a7u,<<,(%a3),%d2,%acc1
+	mac.w %a1l,%a7u,<<,(%a3),%d2,%acc2
+	mac.w %a1l,%a7u,<<,(%a3),%a7,%acc1
+	mac.w %a1l,%a7u,<<,(%a3),%a7,%acc2
+	mac.w %a1l,%a7u,<<,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a7u,<<,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a7u,<<,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a7u,<<,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a7u,<<,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a7u,<<,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a7u,<<,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a7u,<<,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6),%d1,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6),%d1,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6),%a3,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6),%a3,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6),%d2,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6),%d2,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6),%a7,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6),%a7,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1),%d1,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1),%d1,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1),%a3,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1),%a3,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1),%d2,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1),%d2,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1),%a7,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1),%a7,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a7u,>>,(%a3),%d1,%acc1
+	mac.w %a1l,%a7u,>>,(%a3),%d1,%acc2
+	mac.w %a1l,%a7u,>>,(%a3),%a3,%acc1
+	mac.w %a1l,%a7u,>>,(%a3),%a3,%acc2
+	mac.w %a1l,%a7u,>>,(%a3),%d2,%acc1
+	mac.w %a1l,%a7u,>>,(%a3),%d2,%acc2
+	mac.w %a1l,%a7u,>>,(%a3),%a7,%acc1
+	mac.w %a1l,%a7u,>>,(%a3),%a7,%acc2
+	mac.w %a1l,%a7u,>>,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a7u,>>,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a7u,>>,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a7u,>>,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a7u,>>,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a7u,>>,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a7u,>>,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a7u,>>,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6),%d1,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6),%d1,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6),%a3,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6),%a3,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6),%d2,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6),%d2,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6),%a7,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6),%a7,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1),%d1,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1),%d1,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1),%a3,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1),%a3,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1),%d2,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1),%d2,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1),%a7,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1),%a7,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a7u,#1,(%a3),%d1,%acc1
+	mac.w %a1l,%a7u,#1,(%a3),%d1,%acc2
+	mac.w %a1l,%a7u,#1,(%a3),%a3,%acc1
+	mac.w %a1l,%a7u,#1,(%a3),%a3,%acc2
+	mac.w %a1l,%a7u,#1,(%a3),%d2,%acc1
+	mac.w %a1l,%a7u,#1,(%a3),%d2,%acc2
+	mac.w %a1l,%a7u,#1,(%a3),%a7,%acc1
+	mac.w %a1l,%a7u,#1,(%a3),%a7,%acc2
+	mac.w %a1l,%a7u,#1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a7u,#1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a7u,#1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a7u,#1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a7u,#1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a7u,#1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a7u,#1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a7u,#1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6),%d1,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6),%d1,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6),%a3,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6),%a3,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6),%d2,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6),%d2,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6),%a7,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6),%a7,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1),%d1,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1),%d1,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1),%a3,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1),%a3,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1),%d2,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1),%d2,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1),%a7,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1),%a7,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3),%d1,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3),%d1,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3),%a3,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3),%a3,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3),%d2,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3),%d2,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3),%a7,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3),%a7,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6),%d1,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6),%d1,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6),%a3,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6),%a3,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6),%d2,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6),%d2,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6),%a7,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6),%a7,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1),%d1,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1),%d1,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1),%a3,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1),%a3,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1),%d2,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1),%d2,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1),%a7,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1),%a7,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d1l,(%a3),%d1,%acc1
+	mac.w %a1l,%d1l,(%a3),%d1,%acc2
+	mac.w %a1l,%d1l,(%a3),%a3,%acc1
+	mac.w %a1l,%d1l,(%a3),%a3,%acc2
+	mac.w %a1l,%d1l,(%a3),%d2,%acc1
+	mac.w %a1l,%d1l,(%a3),%d2,%acc2
+	mac.w %a1l,%d1l,(%a3),%a7,%acc1
+	mac.w %a1l,%d1l,(%a3),%a7,%acc2
+	mac.w %a1l,%d1l,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d1l,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d1l,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d1l,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d1l,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d1l,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d1l,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d1l,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d1l,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d1l,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d1l,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d1l,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d1l,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d1l,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d1l,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d1l,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d1l,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d1l,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d1l,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d1l,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d1l,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d1l,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d1l,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d1l,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d1l,10(%a6),%d1,%acc1
+	mac.w %a1l,%d1l,10(%a6),%d1,%acc2
+	mac.w %a1l,%d1l,10(%a6),%a3,%acc1
+	mac.w %a1l,%d1l,10(%a6),%a3,%acc2
+	mac.w %a1l,%d1l,10(%a6),%d2,%acc1
+	mac.w %a1l,%d1l,10(%a6),%d2,%acc2
+	mac.w %a1l,%d1l,10(%a6),%a7,%acc1
+	mac.w %a1l,%d1l,10(%a6),%a7,%acc2
+	mac.w %a1l,%d1l,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d1l,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d1l,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d1l,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d1l,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d1l,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d1l,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d1l,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d1l,-(%a1),%d1,%acc1
+	mac.w %a1l,%d1l,-(%a1),%d1,%acc2
+	mac.w %a1l,%d1l,-(%a1),%a3,%acc1
+	mac.w %a1l,%d1l,-(%a1),%a3,%acc2
+	mac.w %a1l,%d1l,-(%a1),%d2,%acc1
+	mac.w %a1l,%d1l,-(%a1),%d2,%acc2
+	mac.w %a1l,%d1l,-(%a1),%a7,%acc1
+	mac.w %a1l,%d1l,-(%a1),%a7,%acc2
+	mac.w %a1l,%d1l,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d1l,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d1l,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d1l,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d1l,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d1l,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d1l,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d1l,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d1l,<<,(%a3),%d1,%acc1
+	mac.w %a1l,%d1l,<<,(%a3),%d1,%acc2
+	mac.w %a1l,%d1l,<<,(%a3),%a3,%acc1
+	mac.w %a1l,%d1l,<<,(%a3),%a3,%acc2
+	mac.w %a1l,%d1l,<<,(%a3),%d2,%acc1
+	mac.w %a1l,%d1l,<<,(%a3),%d2,%acc2
+	mac.w %a1l,%d1l,<<,(%a3),%a7,%acc1
+	mac.w %a1l,%d1l,<<,(%a3),%a7,%acc2
+	mac.w %a1l,%d1l,<<,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d1l,<<,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d1l,<<,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d1l,<<,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d1l,<<,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d1l,<<,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d1l,<<,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d1l,<<,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6),%d1,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6),%d1,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6),%a3,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6),%a3,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6),%d2,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6),%d2,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6),%a7,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6),%a7,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1),%d1,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1),%d1,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1),%a3,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1),%a3,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1),%d2,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1),%d2,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1),%a7,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1),%a7,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d1l,>>,(%a3),%d1,%acc1
+	mac.w %a1l,%d1l,>>,(%a3),%d1,%acc2
+	mac.w %a1l,%d1l,>>,(%a3),%a3,%acc1
+	mac.w %a1l,%d1l,>>,(%a3),%a3,%acc2
+	mac.w %a1l,%d1l,>>,(%a3),%d2,%acc1
+	mac.w %a1l,%d1l,>>,(%a3),%d2,%acc2
+	mac.w %a1l,%d1l,>>,(%a3),%a7,%acc1
+	mac.w %a1l,%d1l,>>,(%a3),%a7,%acc2
+	mac.w %a1l,%d1l,>>,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d1l,>>,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d1l,>>,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d1l,>>,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d1l,>>,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d1l,>>,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d1l,>>,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d1l,>>,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6),%d1,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6),%d1,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6),%a3,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6),%a3,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6),%d2,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6),%d2,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6),%a7,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6),%a7,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1),%d1,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1),%d1,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1),%a3,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1),%a3,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1),%d2,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1),%d2,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1),%a7,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1),%a7,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d1l,#1,(%a3),%d1,%acc1
+	mac.w %a1l,%d1l,#1,(%a3),%d1,%acc2
+	mac.w %a1l,%d1l,#1,(%a3),%a3,%acc1
+	mac.w %a1l,%d1l,#1,(%a3),%a3,%acc2
+	mac.w %a1l,%d1l,#1,(%a3),%d2,%acc1
+	mac.w %a1l,%d1l,#1,(%a3),%d2,%acc2
+	mac.w %a1l,%d1l,#1,(%a3),%a7,%acc1
+	mac.w %a1l,%d1l,#1,(%a3),%a7,%acc2
+	mac.w %a1l,%d1l,#1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d1l,#1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d1l,#1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d1l,#1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d1l,#1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d1l,#1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d1l,#1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d1l,#1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6),%d1,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6),%d1,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6),%a3,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6),%a3,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6),%d2,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6),%d2,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6),%a7,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6),%a7,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1),%d1,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1),%d1,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1),%a3,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1),%a3,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1),%d2,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1),%d2,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1),%a7,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1),%a7,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a7,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3),%d1,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3),%d1,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3),%a3,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3),%a3,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3),%d2,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3),%d2,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3),%a7,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3),%a7,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d1,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d1,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a3,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a3,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d2,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d2,%acc2
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a7,%acc1
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a7,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d1,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d1,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a3,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a3,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d2,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d2,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a7,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a7,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6),%d1,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6),%d1,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6),%a3,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6),%a3,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6),%d2,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6),%d2,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6),%a7,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6),%a7,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1),%d1,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1),%d1,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1),%a3,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1),%a3,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1),%d2,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1),%d2,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1),%a7,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1),%a7,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a2u,(%a3),%d1,%acc1
+	mac.w %d2u,%a2u,(%a3),%d1,%acc2
+	mac.w %d2u,%a2u,(%a3),%a3,%acc1
+	mac.w %d2u,%a2u,(%a3),%a3,%acc2
+	mac.w %d2u,%a2u,(%a3),%d2,%acc1
+	mac.w %d2u,%a2u,(%a3),%d2,%acc2
+	mac.w %d2u,%a2u,(%a3),%a7,%acc1
+	mac.w %d2u,%a2u,(%a3),%a7,%acc2
+	mac.w %d2u,%a2u,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a2u,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a2u,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a2u,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a2u,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a2u,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a2u,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a2u,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a2u,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a2u,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a2u,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a2u,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a2u,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a2u,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a2u,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a2u,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a2u,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a2u,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a2u,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a2u,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a2u,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a2u,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a2u,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a2u,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a2u,10(%a6),%d1,%acc1
+	mac.w %d2u,%a2u,10(%a6),%d1,%acc2
+	mac.w %d2u,%a2u,10(%a6),%a3,%acc1
+	mac.w %d2u,%a2u,10(%a6),%a3,%acc2
+	mac.w %d2u,%a2u,10(%a6),%d2,%acc1
+	mac.w %d2u,%a2u,10(%a6),%d2,%acc2
+	mac.w %d2u,%a2u,10(%a6),%a7,%acc1
+	mac.w %d2u,%a2u,10(%a6),%a7,%acc2
+	mac.w %d2u,%a2u,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a2u,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a2u,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a2u,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a2u,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a2u,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a2u,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a2u,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a2u,-(%a1),%d1,%acc1
+	mac.w %d2u,%a2u,-(%a1),%d1,%acc2
+	mac.w %d2u,%a2u,-(%a1),%a3,%acc1
+	mac.w %d2u,%a2u,-(%a1),%a3,%acc2
+	mac.w %d2u,%a2u,-(%a1),%d2,%acc1
+	mac.w %d2u,%a2u,-(%a1),%d2,%acc2
+	mac.w %d2u,%a2u,-(%a1),%a7,%acc1
+	mac.w %d2u,%a2u,-(%a1),%a7,%acc2
+	mac.w %d2u,%a2u,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a2u,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a2u,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a2u,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a2u,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a2u,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a2u,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a2u,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a2u,<<,(%a3),%d1,%acc1
+	mac.w %d2u,%a2u,<<,(%a3),%d1,%acc2
+	mac.w %d2u,%a2u,<<,(%a3),%a3,%acc1
+	mac.w %d2u,%a2u,<<,(%a3),%a3,%acc2
+	mac.w %d2u,%a2u,<<,(%a3),%d2,%acc1
+	mac.w %d2u,%a2u,<<,(%a3),%d2,%acc2
+	mac.w %d2u,%a2u,<<,(%a3),%a7,%acc1
+	mac.w %d2u,%a2u,<<,(%a3),%a7,%acc2
+	mac.w %d2u,%a2u,<<,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a2u,<<,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a2u,<<,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a2u,<<,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a2u,<<,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a2u,<<,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a2u,<<,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a2u,<<,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6),%d1,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6),%d1,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6),%a3,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6),%a3,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6),%d2,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6),%d2,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6),%a7,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6),%a7,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1),%d1,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1),%d1,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1),%a3,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1),%a3,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1),%d2,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1),%d2,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1),%a7,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1),%a7,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a2u,>>,(%a3),%d1,%acc1
+	mac.w %d2u,%a2u,>>,(%a3),%d1,%acc2
+	mac.w %d2u,%a2u,>>,(%a3),%a3,%acc1
+	mac.w %d2u,%a2u,>>,(%a3),%a3,%acc2
+	mac.w %d2u,%a2u,>>,(%a3),%d2,%acc1
+	mac.w %d2u,%a2u,>>,(%a3),%d2,%acc2
+	mac.w %d2u,%a2u,>>,(%a3),%a7,%acc1
+	mac.w %d2u,%a2u,>>,(%a3),%a7,%acc2
+	mac.w %d2u,%a2u,>>,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a2u,>>,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a2u,>>,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a2u,>>,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a2u,>>,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a2u,>>,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a2u,>>,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a2u,>>,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6),%d1,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6),%d1,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6),%a3,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6),%a3,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6),%d2,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6),%d2,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6),%a7,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6),%a7,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1),%d1,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1),%d1,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1),%a3,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1),%a3,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1),%d2,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1),%d2,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1),%a7,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1),%a7,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a2u,#1,(%a3),%d1,%acc1
+	mac.w %d2u,%a2u,#1,(%a3),%d1,%acc2
+	mac.w %d2u,%a2u,#1,(%a3),%a3,%acc1
+	mac.w %d2u,%a2u,#1,(%a3),%a3,%acc2
+	mac.w %d2u,%a2u,#1,(%a3),%d2,%acc1
+	mac.w %d2u,%a2u,#1,(%a3),%d2,%acc2
+	mac.w %d2u,%a2u,#1,(%a3),%a7,%acc1
+	mac.w %d2u,%a2u,#1,(%a3),%a7,%acc2
+	mac.w %d2u,%a2u,#1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a2u,#1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a2u,#1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a2u,#1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a2u,#1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a2u,#1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a2u,#1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a2u,#1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6),%d1,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6),%d1,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6),%a3,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6),%a3,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6),%d2,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6),%d2,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6),%a7,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6),%a7,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1),%d1,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1),%d1,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1),%a3,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1),%a3,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1),%d2,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1),%d2,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1),%a7,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1),%a7,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3),%d1,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3),%d1,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3),%a3,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3),%a3,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3),%d2,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3),%d2,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3),%a7,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3),%a7,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6),%d1,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6),%d1,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6),%a3,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6),%a3,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6),%d2,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6),%d2,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6),%a7,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6),%a7,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1),%d1,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1),%d1,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1),%a3,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1),%a3,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1),%d2,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1),%d2,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1),%a7,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1),%a7,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d3l,(%a3),%d1,%acc1
+	mac.w %d2u,%d3l,(%a3),%d1,%acc2
+	mac.w %d2u,%d3l,(%a3),%a3,%acc1
+	mac.w %d2u,%d3l,(%a3),%a3,%acc2
+	mac.w %d2u,%d3l,(%a3),%d2,%acc1
+	mac.w %d2u,%d3l,(%a3),%d2,%acc2
+	mac.w %d2u,%d3l,(%a3),%a7,%acc1
+	mac.w %d2u,%d3l,(%a3),%a7,%acc2
+	mac.w %d2u,%d3l,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d3l,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d3l,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d3l,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d3l,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d3l,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d3l,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d3l,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d3l,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d3l,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d3l,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d3l,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d3l,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d3l,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d3l,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d3l,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d3l,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d3l,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d3l,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d3l,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d3l,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d3l,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d3l,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d3l,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d3l,10(%a6),%d1,%acc1
+	mac.w %d2u,%d3l,10(%a6),%d1,%acc2
+	mac.w %d2u,%d3l,10(%a6),%a3,%acc1
+	mac.w %d2u,%d3l,10(%a6),%a3,%acc2
+	mac.w %d2u,%d3l,10(%a6),%d2,%acc1
+	mac.w %d2u,%d3l,10(%a6),%d2,%acc2
+	mac.w %d2u,%d3l,10(%a6),%a7,%acc1
+	mac.w %d2u,%d3l,10(%a6),%a7,%acc2
+	mac.w %d2u,%d3l,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d3l,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d3l,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d3l,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d3l,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d3l,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d3l,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d3l,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d3l,-(%a1),%d1,%acc1
+	mac.w %d2u,%d3l,-(%a1),%d1,%acc2
+	mac.w %d2u,%d3l,-(%a1),%a3,%acc1
+	mac.w %d2u,%d3l,-(%a1),%a3,%acc2
+	mac.w %d2u,%d3l,-(%a1),%d2,%acc1
+	mac.w %d2u,%d3l,-(%a1),%d2,%acc2
+	mac.w %d2u,%d3l,-(%a1),%a7,%acc1
+	mac.w %d2u,%d3l,-(%a1),%a7,%acc2
+	mac.w %d2u,%d3l,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d3l,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d3l,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d3l,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d3l,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d3l,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d3l,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d3l,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d3l,<<,(%a3),%d1,%acc1
+	mac.w %d2u,%d3l,<<,(%a3),%d1,%acc2
+	mac.w %d2u,%d3l,<<,(%a3),%a3,%acc1
+	mac.w %d2u,%d3l,<<,(%a3),%a3,%acc2
+	mac.w %d2u,%d3l,<<,(%a3),%d2,%acc1
+	mac.w %d2u,%d3l,<<,(%a3),%d2,%acc2
+	mac.w %d2u,%d3l,<<,(%a3),%a7,%acc1
+	mac.w %d2u,%d3l,<<,(%a3),%a7,%acc2
+	mac.w %d2u,%d3l,<<,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d3l,<<,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d3l,<<,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d3l,<<,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d3l,<<,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d3l,<<,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d3l,<<,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d3l,<<,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6),%d1,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6),%d1,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6),%a3,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6),%a3,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6),%d2,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6),%d2,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6),%a7,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6),%a7,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1),%d1,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1),%d1,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1),%a3,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1),%a3,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1),%d2,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1),%d2,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1),%a7,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1),%a7,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d3l,>>,(%a3),%d1,%acc1
+	mac.w %d2u,%d3l,>>,(%a3),%d1,%acc2
+	mac.w %d2u,%d3l,>>,(%a3),%a3,%acc1
+	mac.w %d2u,%d3l,>>,(%a3),%a3,%acc2
+	mac.w %d2u,%d3l,>>,(%a3),%d2,%acc1
+	mac.w %d2u,%d3l,>>,(%a3),%d2,%acc2
+	mac.w %d2u,%d3l,>>,(%a3),%a7,%acc1
+	mac.w %d2u,%d3l,>>,(%a3),%a7,%acc2
+	mac.w %d2u,%d3l,>>,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d3l,>>,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d3l,>>,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d3l,>>,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d3l,>>,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d3l,>>,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d3l,>>,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d3l,>>,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6),%d1,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6),%d1,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6),%a3,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6),%a3,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6),%d2,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6),%d2,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6),%a7,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6),%a7,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1),%d1,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1),%d1,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1),%a3,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1),%a3,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1),%d2,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1),%d2,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1),%a7,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1),%a7,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d3l,#1,(%a3),%d1,%acc1
+	mac.w %d2u,%d3l,#1,(%a3),%d1,%acc2
+	mac.w %d2u,%d3l,#1,(%a3),%a3,%acc1
+	mac.w %d2u,%d3l,#1,(%a3),%a3,%acc2
+	mac.w %d2u,%d3l,#1,(%a3),%d2,%acc1
+	mac.w %d2u,%d3l,#1,(%a3),%d2,%acc2
+	mac.w %d2u,%d3l,#1,(%a3),%a7,%acc1
+	mac.w %d2u,%d3l,#1,(%a3),%a7,%acc2
+	mac.w %d2u,%d3l,#1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d3l,#1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d3l,#1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d3l,#1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d3l,#1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d3l,#1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d3l,#1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d3l,#1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6),%d1,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6),%d1,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6),%a3,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6),%a3,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6),%d2,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6),%d2,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6),%a7,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6),%a7,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1),%d1,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1),%d1,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1),%a3,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1),%a3,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1),%d2,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1),%d2,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1),%a7,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1),%a7,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3),%d1,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3),%d1,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3),%a3,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3),%a3,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3),%d2,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3),%d2,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3),%a7,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3),%a7,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6),%d1,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6),%d1,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6),%a3,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6),%a3,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6),%d2,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6),%d2,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6),%a7,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6),%a7,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1),%d1,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1),%d1,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1),%a3,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1),%a3,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1),%d2,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1),%d2,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1),%a7,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1),%a7,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a7u,(%a3),%d1,%acc1
+	mac.w %d2u,%a7u,(%a3),%d1,%acc2
+	mac.w %d2u,%a7u,(%a3),%a3,%acc1
+	mac.w %d2u,%a7u,(%a3),%a3,%acc2
+	mac.w %d2u,%a7u,(%a3),%d2,%acc1
+	mac.w %d2u,%a7u,(%a3),%d2,%acc2
+	mac.w %d2u,%a7u,(%a3),%a7,%acc1
+	mac.w %d2u,%a7u,(%a3),%a7,%acc2
+	mac.w %d2u,%a7u,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a7u,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a7u,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a7u,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a7u,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a7u,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a7u,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a7u,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a7u,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a7u,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a7u,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a7u,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a7u,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a7u,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a7u,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a7u,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a7u,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a7u,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a7u,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a7u,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a7u,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a7u,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a7u,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a7u,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a7u,10(%a6),%d1,%acc1
+	mac.w %d2u,%a7u,10(%a6),%d1,%acc2
+	mac.w %d2u,%a7u,10(%a6),%a3,%acc1
+	mac.w %d2u,%a7u,10(%a6),%a3,%acc2
+	mac.w %d2u,%a7u,10(%a6),%d2,%acc1
+	mac.w %d2u,%a7u,10(%a6),%d2,%acc2
+	mac.w %d2u,%a7u,10(%a6),%a7,%acc1
+	mac.w %d2u,%a7u,10(%a6),%a7,%acc2
+	mac.w %d2u,%a7u,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a7u,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a7u,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a7u,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a7u,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a7u,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a7u,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a7u,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a7u,-(%a1),%d1,%acc1
+	mac.w %d2u,%a7u,-(%a1),%d1,%acc2
+	mac.w %d2u,%a7u,-(%a1),%a3,%acc1
+	mac.w %d2u,%a7u,-(%a1),%a3,%acc2
+	mac.w %d2u,%a7u,-(%a1),%d2,%acc1
+	mac.w %d2u,%a7u,-(%a1),%d2,%acc2
+	mac.w %d2u,%a7u,-(%a1),%a7,%acc1
+	mac.w %d2u,%a7u,-(%a1),%a7,%acc2
+	mac.w %d2u,%a7u,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a7u,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a7u,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a7u,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a7u,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a7u,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a7u,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a7u,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a7u,<<,(%a3),%d1,%acc1
+	mac.w %d2u,%a7u,<<,(%a3),%d1,%acc2
+	mac.w %d2u,%a7u,<<,(%a3),%a3,%acc1
+	mac.w %d2u,%a7u,<<,(%a3),%a3,%acc2
+	mac.w %d2u,%a7u,<<,(%a3),%d2,%acc1
+	mac.w %d2u,%a7u,<<,(%a3),%d2,%acc2
+	mac.w %d2u,%a7u,<<,(%a3),%a7,%acc1
+	mac.w %d2u,%a7u,<<,(%a3),%a7,%acc2
+	mac.w %d2u,%a7u,<<,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a7u,<<,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a7u,<<,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a7u,<<,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a7u,<<,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a7u,<<,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a7u,<<,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a7u,<<,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6),%d1,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6),%d1,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6),%a3,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6),%a3,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6),%d2,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6),%d2,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6),%a7,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6),%a7,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1),%d1,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1),%d1,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1),%a3,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1),%a3,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1),%d2,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1),%d2,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1),%a7,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1),%a7,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a7u,>>,(%a3),%d1,%acc1
+	mac.w %d2u,%a7u,>>,(%a3),%d1,%acc2
+	mac.w %d2u,%a7u,>>,(%a3),%a3,%acc1
+	mac.w %d2u,%a7u,>>,(%a3),%a3,%acc2
+	mac.w %d2u,%a7u,>>,(%a3),%d2,%acc1
+	mac.w %d2u,%a7u,>>,(%a3),%d2,%acc2
+	mac.w %d2u,%a7u,>>,(%a3),%a7,%acc1
+	mac.w %d2u,%a7u,>>,(%a3),%a7,%acc2
+	mac.w %d2u,%a7u,>>,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a7u,>>,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a7u,>>,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a7u,>>,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a7u,>>,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a7u,>>,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a7u,>>,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a7u,>>,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6),%d1,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6),%d1,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6),%a3,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6),%a3,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6),%d2,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6),%d2,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6),%a7,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6),%a7,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1),%d1,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1),%d1,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1),%a3,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1),%a3,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1),%d2,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1),%d2,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1),%a7,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1),%a7,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a7u,#1,(%a3),%d1,%acc1
+	mac.w %d2u,%a7u,#1,(%a3),%d1,%acc2
+	mac.w %d2u,%a7u,#1,(%a3),%a3,%acc1
+	mac.w %d2u,%a7u,#1,(%a3),%a3,%acc2
+	mac.w %d2u,%a7u,#1,(%a3),%d2,%acc1
+	mac.w %d2u,%a7u,#1,(%a3),%d2,%acc2
+	mac.w %d2u,%a7u,#1,(%a3),%a7,%acc1
+	mac.w %d2u,%a7u,#1,(%a3),%a7,%acc2
+	mac.w %d2u,%a7u,#1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a7u,#1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a7u,#1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a7u,#1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a7u,#1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a7u,#1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a7u,#1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a7u,#1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6),%d1,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6),%d1,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6),%a3,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6),%a3,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6),%d2,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6),%d2,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6),%a7,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6),%a7,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1),%d1,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1),%d1,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1),%a3,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1),%a3,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1),%d2,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1),%d2,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1),%a7,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1),%a7,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3),%d1,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3),%d1,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3),%a3,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3),%a3,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3),%d2,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3),%d2,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3),%a7,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3),%a7,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6),%d1,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6),%d1,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6),%a3,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6),%a3,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6),%d2,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6),%d2,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6),%a7,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6),%a7,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1),%d1,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1),%d1,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1),%a3,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1),%a3,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1),%d2,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1),%d2,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1),%a7,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1),%a7,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d1l,(%a3),%d1,%acc1
+	mac.w %d2u,%d1l,(%a3),%d1,%acc2
+	mac.w %d2u,%d1l,(%a3),%a3,%acc1
+	mac.w %d2u,%d1l,(%a3),%a3,%acc2
+	mac.w %d2u,%d1l,(%a3),%d2,%acc1
+	mac.w %d2u,%d1l,(%a3),%d2,%acc2
+	mac.w %d2u,%d1l,(%a3),%a7,%acc1
+	mac.w %d2u,%d1l,(%a3),%a7,%acc2
+	mac.w %d2u,%d1l,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d1l,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d1l,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d1l,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d1l,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d1l,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d1l,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d1l,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d1l,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d1l,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d1l,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d1l,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d1l,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d1l,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d1l,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d1l,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d1l,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d1l,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d1l,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d1l,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d1l,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d1l,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d1l,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d1l,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d1l,10(%a6),%d1,%acc1
+	mac.w %d2u,%d1l,10(%a6),%d1,%acc2
+	mac.w %d2u,%d1l,10(%a6),%a3,%acc1
+	mac.w %d2u,%d1l,10(%a6),%a3,%acc2
+	mac.w %d2u,%d1l,10(%a6),%d2,%acc1
+	mac.w %d2u,%d1l,10(%a6),%d2,%acc2
+	mac.w %d2u,%d1l,10(%a6),%a7,%acc1
+	mac.w %d2u,%d1l,10(%a6),%a7,%acc2
+	mac.w %d2u,%d1l,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d1l,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d1l,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d1l,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d1l,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d1l,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d1l,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d1l,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d1l,-(%a1),%d1,%acc1
+	mac.w %d2u,%d1l,-(%a1),%d1,%acc2
+	mac.w %d2u,%d1l,-(%a1),%a3,%acc1
+	mac.w %d2u,%d1l,-(%a1),%a3,%acc2
+	mac.w %d2u,%d1l,-(%a1),%d2,%acc1
+	mac.w %d2u,%d1l,-(%a1),%d2,%acc2
+	mac.w %d2u,%d1l,-(%a1),%a7,%acc1
+	mac.w %d2u,%d1l,-(%a1),%a7,%acc2
+	mac.w %d2u,%d1l,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d1l,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d1l,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d1l,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d1l,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d1l,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d1l,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d1l,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d1l,<<,(%a3),%d1,%acc1
+	mac.w %d2u,%d1l,<<,(%a3),%d1,%acc2
+	mac.w %d2u,%d1l,<<,(%a3),%a3,%acc1
+	mac.w %d2u,%d1l,<<,(%a3),%a3,%acc2
+	mac.w %d2u,%d1l,<<,(%a3),%d2,%acc1
+	mac.w %d2u,%d1l,<<,(%a3),%d2,%acc2
+	mac.w %d2u,%d1l,<<,(%a3),%a7,%acc1
+	mac.w %d2u,%d1l,<<,(%a3),%a7,%acc2
+	mac.w %d2u,%d1l,<<,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d1l,<<,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d1l,<<,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d1l,<<,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d1l,<<,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d1l,<<,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d1l,<<,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d1l,<<,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6),%d1,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6),%d1,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6),%a3,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6),%a3,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6),%d2,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6),%d2,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6),%a7,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6),%a7,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1),%d1,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1),%d1,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1),%a3,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1),%a3,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1),%d2,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1),%d2,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1),%a7,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1),%a7,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d1l,>>,(%a3),%d1,%acc1
+	mac.w %d2u,%d1l,>>,(%a3),%d1,%acc2
+	mac.w %d2u,%d1l,>>,(%a3),%a3,%acc1
+	mac.w %d2u,%d1l,>>,(%a3),%a3,%acc2
+	mac.w %d2u,%d1l,>>,(%a3),%d2,%acc1
+	mac.w %d2u,%d1l,>>,(%a3),%d2,%acc2
+	mac.w %d2u,%d1l,>>,(%a3),%a7,%acc1
+	mac.w %d2u,%d1l,>>,(%a3),%a7,%acc2
+	mac.w %d2u,%d1l,>>,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d1l,>>,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d1l,>>,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d1l,>>,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d1l,>>,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d1l,>>,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d1l,>>,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d1l,>>,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6),%d1,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6),%d1,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6),%a3,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6),%a3,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6),%d2,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6),%d2,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6),%a7,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6),%a7,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1),%d1,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1),%d1,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1),%a3,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1),%a3,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1),%d2,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1),%d2,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1),%a7,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1),%a7,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d1l,#1,(%a3),%d1,%acc1
+	mac.w %d2u,%d1l,#1,(%a3),%d1,%acc2
+	mac.w %d2u,%d1l,#1,(%a3),%a3,%acc1
+	mac.w %d2u,%d1l,#1,(%a3),%a3,%acc2
+	mac.w %d2u,%d1l,#1,(%a3),%d2,%acc1
+	mac.w %d2u,%d1l,#1,(%a3),%d2,%acc2
+	mac.w %d2u,%d1l,#1,(%a3),%a7,%acc1
+	mac.w %d2u,%d1l,#1,(%a3),%a7,%acc2
+	mac.w %d2u,%d1l,#1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d1l,#1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d1l,#1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d1l,#1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d1l,#1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d1l,#1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d1l,#1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d1l,#1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6),%d1,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6),%d1,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6),%a3,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6),%a3,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6),%d2,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6),%d2,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6),%a7,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6),%a7,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1),%d1,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1),%d1,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1),%a3,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1),%a3,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1),%d2,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1),%d2,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1),%a7,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1),%a7,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a7,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3),%d1,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3),%d1,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3),%a3,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3),%a3,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3),%d2,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3),%d2,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3),%a7,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3),%a7,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d1,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d1,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a3,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a3,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d2,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d2,%acc2
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a7,%acc1
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a7,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d1,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d1,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a3,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a3,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d2,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d2,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a7,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a7,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6),%d1,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6),%d1,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6),%a3,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6),%a3,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6),%d2,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6),%d2,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6),%a7,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6),%a7,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1),%d1,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1),%d1,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1),%a3,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1),%a3,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1),%d2,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1),%d2,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1),%a7,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1),%a7,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a2u,(%a3),%d1,%acc1
+	mac.w %a5l,%a2u,(%a3),%d1,%acc2
+	mac.w %a5l,%a2u,(%a3),%a3,%acc1
+	mac.w %a5l,%a2u,(%a3),%a3,%acc2
+	mac.w %a5l,%a2u,(%a3),%d2,%acc1
+	mac.w %a5l,%a2u,(%a3),%d2,%acc2
+	mac.w %a5l,%a2u,(%a3),%a7,%acc1
+	mac.w %a5l,%a2u,(%a3),%a7,%acc2
+	mac.w %a5l,%a2u,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a2u,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a2u,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a2u,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a2u,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a2u,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a2u,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a2u,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a2u,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a2u,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a2u,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a2u,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a2u,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a2u,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a2u,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a2u,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a2u,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a2u,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a2u,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a2u,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a2u,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a2u,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a2u,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a2u,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a2u,10(%a6),%d1,%acc1
+	mac.w %a5l,%a2u,10(%a6),%d1,%acc2
+	mac.w %a5l,%a2u,10(%a6),%a3,%acc1
+	mac.w %a5l,%a2u,10(%a6),%a3,%acc2
+	mac.w %a5l,%a2u,10(%a6),%d2,%acc1
+	mac.w %a5l,%a2u,10(%a6),%d2,%acc2
+	mac.w %a5l,%a2u,10(%a6),%a7,%acc1
+	mac.w %a5l,%a2u,10(%a6),%a7,%acc2
+	mac.w %a5l,%a2u,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a2u,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a2u,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a2u,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a2u,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a2u,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a2u,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a2u,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a2u,-(%a1),%d1,%acc1
+	mac.w %a5l,%a2u,-(%a1),%d1,%acc2
+	mac.w %a5l,%a2u,-(%a1),%a3,%acc1
+	mac.w %a5l,%a2u,-(%a1),%a3,%acc2
+	mac.w %a5l,%a2u,-(%a1),%d2,%acc1
+	mac.w %a5l,%a2u,-(%a1),%d2,%acc2
+	mac.w %a5l,%a2u,-(%a1),%a7,%acc1
+	mac.w %a5l,%a2u,-(%a1),%a7,%acc2
+	mac.w %a5l,%a2u,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a2u,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a2u,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a2u,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a2u,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a2u,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a2u,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a2u,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a2u,<<,(%a3),%d1,%acc1
+	mac.w %a5l,%a2u,<<,(%a3),%d1,%acc2
+	mac.w %a5l,%a2u,<<,(%a3),%a3,%acc1
+	mac.w %a5l,%a2u,<<,(%a3),%a3,%acc2
+	mac.w %a5l,%a2u,<<,(%a3),%d2,%acc1
+	mac.w %a5l,%a2u,<<,(%a3),%d2,%acc2
+	mac.w %a5l,%a2u,<<,(%a3),%a7,%acc1
+	mac.w %a5l,%a2u,<<,(%a3),%a7,%acc2
+	mac.w %a5l,%a2u,<<,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a2u,<<,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a2u,<<,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a2u,<<,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a2u,<<,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a2u,<<,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a2u,<<,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a2u,<<,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6),%d1,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6),%d1,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6),%a3,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6),%a3,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6),%d2,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6),%d2,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6),%a7,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6),%a7,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1),%d1,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1),%d1,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1),%a3,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1),%a3,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1),%d2,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1),%d2,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1),%a7,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1),%a7,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a2u,>>,(%a3),%d1,%acc1
+	mac.w %a5l,%a2u,>>,(%a3),%d1,%acc2
+	mac.w %a5l,%a2u,>>,(%a3),%a3,%acc1
+	mac.w %a5l,%a2u,>>,(%a3),%a3,%acc2
+	mac.w %a5l,%a2u,>>,(%a3),%d2,%acc1
+	mac.w %a5l,%a2u,>>,(%a3),%d2,%acc2
+	mac.w %a5l,%a2u,>>,(%a3),%a7,%acc1
+	mac.w %a5l,%a2u,>>,(%a3),%a7,%acc2
+	mac.w %a5l,%a2u,>>,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a2u,>>,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a2u,>>,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a2u,>>,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a2u,>>,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a2u,>>,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a2u,>>,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a2u,>>,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6),%d1,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6),%d1,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6),%a3,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6),%a3,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6),%d2,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6),%d2,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6),%a7,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6),%a7,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1),%d1,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1),%d1,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1),%a3,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1),%a3,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1),%d2,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1),%d2,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1),%a7,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1),%a7,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a2u,#1,(%a3),%d1,%acc1
+	mac.w %a5l,%a2u,#1,(%a3),%d1,%acc2
+	mac.w %a5l,%a2u,#1,(%a3),%a3,%acc1
+	mac.w %a5l,%a2u,#1,(%a3),%a3,%acc2
+	mac.w %a5l,%a2u,#1,(%a3),%d2,%acc1
+	mac.w %a5l,%a2u,#1,(%a3),%d2,%acc2
+	mac.w %a5l,%a2u,#1,(%a3),%a7,%acc1
+	mac.w %a5l,%a2u,#1,(%a3),%a7,%acc2
+	mac.w %a5l,%a2u,#1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a2u,#1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a2u,#1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a2u,#1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a2u,#1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a2u,#1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a2u,#1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a2u,#1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6),%d1,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6),%d1,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6),%a3,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6),%a3,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6),%d2,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6),%d2,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6),%a7,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6),%a7,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1),%d1,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1),%d1,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1),%a3,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1),%a3,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1),%d2,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1),%d2,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1),%a7,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1),%a7,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3),%d1,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3),%d1,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3),%a3,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3),%a3,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3),%d2,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3),%d2,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3),%a7,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3),%a7,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6),%d1,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6),%d1,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6),%a3,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6),%a3,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6),%d2,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6),%d2,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6),%a7,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6),%a7,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1),%d1,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1),%d1,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1),%a3,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1),%a3,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1),%d2,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1),%d2,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1),%a7,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1),%a7,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d3l,(%a3),%d1,%acc1
+	mac.w %a5l,%d3l,(%a3),%d1,%acc2
+	mac.w %a5l,%d3l,(%a3),%a3,%acc1
+	mac.w %a5l,%d3l,(%a3),%a3,%acc2
+	mac.w %a5l,%d3l,(%a3),%d2,%acc1
+	mac.w %a5l,%d3l,(%a3),%d2,%acc2
+	mac.w %a5l,%d3l,(%a3),%a7,%acc1
+	mac.w %a5l,%d3l,(%a3),%a7,%acc2
+	mac.w %a5l,%d3l,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d3l,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d3l,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d3l,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d3l,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d3l,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d3l,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d3l,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d3l,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d3l,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d3l,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d3l,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d3l,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d3l,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d3l,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d3l,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d3l,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d3l,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d3l,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d3l,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d3l,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d3l,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d3l,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d3l,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d3l,10(%a6),%d1,%acc1
+	mac.w %a5l,%d3l,10(%a6),%d1,%acc2
+	mac.w %a5l,%d3l,10(%a6),%a3,%acc1
+	mac.w %a5l,%d3l,10(%a6),%a3,%acc2
+	mac.w %a5l,%d3l,10(%a6),%d2,%acc1
+	mac.w %a5l,%d3l,10(%a6),%d2,%acc2
+	mac.w %a5l,%d3l,10(%a6),%a7,%acc1
+	mac.w %a5l,%d3l,10(%a6),%a7,%acc2
+	mac.w %a5l,%d3l,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d3l,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d3l,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d3l,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d3l,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d3l,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d3l,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d3l,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d3l,-(%a1),%d1,%acc1
+	mac.w %a5l,%d3l,-(%a1),%d1,%acc2
+	mac.w %a5l,%d3l,-(%a1),%a3,%acc1
+	mac.w %a5l,%d3l,-(%a1),%a3,%acc2
+	mac.w %a5l,%d3l,-(%a1),%d2,%acc1
+	mac.w %a5l,%d3l,-(%a1),%d2,%acc2
+	mac.w %a5l,%d3l,-(%a1),%a7,%acc1
+	mac.w %a5l,%d3l,-(%a1),%a7,%acc2
+	mac.w %a5l,%d3l,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d3l,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d3l,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d3l,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d3l,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d3l,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d3l,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d3l,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d3l,<<,(%a3),%d1,%acc1
+	mac.w %a5l,%d3l,<<,(%a3),%d1,%acc2
+	mac.w %a5l,%d3l,<<,(%a3),%a3,%acc1
+	mac.w %a5l,%d3l,<<,(%a3),%a3,%acc2
+	mac.w %a5l,%d3l,<<,(%a3),%d2,%acc1
+	mac.w %a5l,%d3l,<<,(%a3),%d2,%acc2
+	mac.w %a5l,%d3l,<<,(%a3),%a7,%acc1
+	mac.w %a5l,%d3l,<<,(%a3),%a7,%acc2
+	mac.w %a5l,%d3l,<<,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d3l,<<,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d3l,<<,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d3l,<<,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d3l,<<,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d3l,<<,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d3l,<<,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d3l,<<,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6),%d1,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6),%d1,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6),%a3,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6),%a3,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6),%d2,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6),%d2,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6),%a7,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6),%a7,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1),%d1,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1),%d1,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1),%a3,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1),%a3,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1),%d2,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1),%d2,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1),%a7,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1),%a7,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d3l,>>,(%a3),%d1,%acc1
+	mac.w %a5l,%d3l,>>,(%a3),%d1,%acc2
+	mac.w %a5l,%d3l,>>,(%a3),%a3,%acc1
+	mac.w %a5l,%d3l,>>,(%a3),%a3,%acc2
+	mac.w %a5l,%d3l,>>,(%a3),%d2,%acc1
+	mac.w %a5l,%d3l,>>,(%a3),%d2,%acc2
+	mac.w %a5l,%d3l,>>,(%a3),%a7,%acc1
+	mac.w %a5l,%d3l,>>,(%a3),%a7,%acc2
+	mac.w %a5l,%d3l,>>,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d3l,>>,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d3l,>>,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d3l,>>,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d3l,>>,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d3l,>>,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d3l,>>,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d3l,>>,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6),%d1,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6),%d1,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6),%a3,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6),%a3,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6),%d2,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6),%d2,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6),%a7,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6),%a7,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1),%d1,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1),%d1,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1),%a3,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1),%a3,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1),%d2,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1),%d2,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1),%a7,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1),%a7,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d3l,#1,(%a3),%d1,%acc1
+	mac.w %a5l,%d3l,#1,(%a3),%d1,%acc2
+	mac.w %a5l,%d3l,#1,(%a3),%a3,%acc1
+	mac.w %a5l,%d3l,#1,(%a3),%a3,%acc2
+	mac.w %a5l,%d3l,#1,(%a3),%d2,%acc1
+	mac.w %a5l,%d3l,#1,(%a3),%d2,%acc2
+	mac.w %a5l,%d3l,#1,(%a3),%a7,%acc1
+	mac.w %a5l,%d3l,#1,(%a3),%a7,%acc2
+	mac.w %a5l,%d3l,#1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d3l,#1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d3l,#1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d3l,#1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d3l,#1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d3l,#1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d3l,#1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d3l,#1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6),%d1,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6),%d1,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6),%a3,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6),%a3,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6),%d2,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6),%d2,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6),%a7,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6),%a7,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1),%d1,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1),%d1,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1),%a3,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1),%a3,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1),%d2,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1),%d2,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1),%a7,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1),%a7,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3),%d1,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3),%d1,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3),%a3,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3),%a3,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3),%d2,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3),%d2,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3),%a7,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3),%a7,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6),%d1,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6),%d1,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6),%a3,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6),%a3,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6),%d2,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6),%d2,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6),%a7,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6),%a7,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1),%d1,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1),%d1,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1),%a3,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1),%a3,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1),%d2,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1),%d2,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1),%a7,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1),%a7,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a7u,(%a3),%d1,%acc1
+	mac.w %a5l,%a7u,(%a3),%d1,%acc2
+	mac.w %a5l,%a7u,(%a3),%a3,%acc1
+	mac.w %a5l,%a7u,(%a3),%a3,%acc2
+	mac.w %a5l,%a7u,(%a3),%d2,%acc1
+	mac.w %a5l,%a7u,(%a3),%d2,%acc2
+	mac.w %a5l,%a7u,(%a3),%a7,%acc1
+	mac.w %a5l,%a7u,(%a3),%a7,%acc2
+	mac.w %a5l,%a7u,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a7u,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a7u,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a7u,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a7u,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a7u,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a7u,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a7u,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a7u,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a7u,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a7u,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a7u,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a7u,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a7u,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a7u,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a7u,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a7u,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a7u,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a7u,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a7u,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a7u,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a7u,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a7u,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a7u,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a7u,10(%a6),%d1,%acc1
+	mac.w %a5l,%a7u,10(%a6),%d1,%acc2
+	mac.w %a5l,%a7u,10(%a6),%a3,%acc1
+	mac.w %a5l,%a7u,10(%a6),%a3,%acc2
+	mac.w %a5l,%a7u,10(%a6),%d2,%acc1
+	mac.w %a5l,%a7u,10(%a6),%d2,%acc2
+	mac.w %a5l,%a7u,10(%a6),%a7,%acc1
+	mac.w %a5l,%a7u,10(%a6),%a7,%acc2
+	mac.w %a5l,%a7u,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a7u,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a7u,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a7u,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a7u,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a7u,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a7u,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a7u,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a7u,-(%a1),%d1,%acc1
+	mac.w %a5l,%a7u,-(%a1),%d1,%acc2
+	mac.w %a5l,%a7u,-(%a1),%a3,%acc1
+	mac.w %a5l,%a7u,-(%a1),%a3,%acc2
+	mac.w %a5l,%a7u,-(%a1),%d2,%acc1
+	mac.w %a5l,%a7u,-(%a1),%d2,%acc2
+	mac.w %a5l,%a7u,-(%a1),%a7,%acc1
+	mac.w %a5l,%a7u,-(%a1),%a7,%acc2
+	mac.w %a5l,%a7u,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a7u,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a7u,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a7u,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a7u,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a7u,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a7u,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a7u,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a7u,<<,(%a3),%d1,%acc1
+	mac.w %a5l,%a7u,<<,(%a3),%d1,%acc2
+	mac.w %a5l,%a7u,<<,(%a3),%a3,%acc1
+	mac.w %a5l,%a7u,<<,(%a3),%a3,%acc2
+	mac.w %a5l,%a7u,<<,(%a3),%d2,%acc1
+	mac.w %a5l,%a7u,<<,(%a3),%d2,%acc2
+	mac.w %a5l,%a7u,<<,(%a3),%a7,%acc1
+	mac.w %a5l,%a7u,<<,(%a3),%a7,%acc2
+	mac.w %a5l,%a7u,<<,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a7u,<<,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a7u,<<,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a7u,<<,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a7u,<<,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a7u,<<,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a7u,<<,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a7u,<<,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6),%d1,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6),%d1,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6),%a3,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6),%a3,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6),%d2,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6),%d2,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6),%a7,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6),%a7,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1),%d1,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1),%d1,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1),%a3,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1),%a3,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1),%d2,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1),%d2,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1),%a7,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1),%a7,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a7u,>>,(%a3),%d1,%acc1
+	mac.w %a5l,%a7u,>>,(%a3),%d1,%acc2
+	mac.w %a5l,%a7u,>>,(%a3),%a3,%acc1
+	mac.w %a5l,%a7u,>>,(%a3),%a3,%acc2
+	mac.w %a5l,%a7u,>>,(%a3),%d2,%acc1
+	mac.w %a5l,%a7u,>>,(%a3),%d2,%acc2
+	mac.w %a5l,%a7u,>>,(%a3),%a7,%acc1
+	mac.w %a5l,%a7u,>>,(%a3),%a7,%acc2
+	mac.w %a5l,%a7u,>>,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a7u,>>,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a7u,>>,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a7u,>>,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a7u,>>,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a7u,>>,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a7u,>>,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a7u,>>,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6),%d1,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6),%d1,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6),%a3,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6),%a3,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6),%d2,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6),%d2,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6),%a7,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6),%a7,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1),%d1,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1),%d1,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1),%a3,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1),%a3,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1),%d2,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1),%d2,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1),%a7,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1),%a7,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a7u,#1,(%a3),%d1,%acc1
+	mac.w %a5l,%a7u,#1,(%a3),%d1,%acc2
+	mac.w %a5l,%a7u,#1,(%a3),%a3,%acc1
+	mac.w %a5l,%a7u,#1,(%a3),%a3,%acc2
+	mac.w %a5l,%a7u,#1,(%a3),%d2,%acc1
+	mac.w %a5l,%a7u,#1,(%a3),%d2,%acc2
+	mac.w %a5l,%a7u,#1,(%a3),%a7,%acc1
+	mac.w %a5l,%a7u,#1,(%a3),%a7,%acc2
+	mac.w %a5l,%a7u,#1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a7u,#1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a7u,#1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a7u,#1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a7u,#1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a7u,#1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a7u,#1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a7u,#1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6),%d1,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6),%d1,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6),%a3,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6),%a3,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6),%d2,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6),%d2,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6),%a7,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6),%a7,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1),%d1,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1),%d1,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1),%a3,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1),%a3,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1),%d2,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1),%d2,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1),%a7,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1),%a7,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3),%d1,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3),%d1,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3),%a3,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3),%a3,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3),%d2,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3),%d2,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3),%a7,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3),%a7,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6),%d1,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6),%d1,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6),%a3,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6),%a3,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6),%d2,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6),%d2,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6),%a7,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6),%a7,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1),%d1,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1),%d1,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1),%a3,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1),%a3,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1),%d2,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1),%d2,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1),%a7,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1),%a7,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d1l,(%a3),%d1,%acc1
+	mac.w %a5l,%d1l,(%a3),%d1,%acc2
+	mac.w %a5l,%d1l,(%a3),%a3,%acc1
+	mac.w %a5l,%d1l,(%a3),%a3,%acc2
+	mac.w %a5l,%d1l,(%a3),%d2,%acc1
+	mac.w %a5l,%d1l,(%a3),%d2,%acc2
+	mac.w %a5l,%d1l,(%a3),%a7,%acc1
+	mac.w %a5l,%d1l,(%a3),%a7,%acc2
+	mac.w %a5l,%d1l,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d1l,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d1l,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d1l,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d1l,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d1l,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d1l,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d1l,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d1l,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d1l,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d1l,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d1l,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d1l,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d1l,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d1l,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d1l,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d1l,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d1l,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d1l,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d1l,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d1l,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d1l,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d1l,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d1l,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d1l,10(%a6),%d1,%acc1
+	mac.w %a5l,%d1l,10(%a6),%d1,%acc2
+	mac.w %a5l,%d1l,10(%a6),%a3,%acc1
+	mac.w %a5l,%d1l,10(%a6),%a3,%acc2
+	mac.w %a5l,%d1l,10(%a6),%d2,%acc1
+	mac.w %a5l,%d1l,10(%a6),%d2,%acc2
+	mac.w %a5l,%d1l,10(%a6),%a7,%acc1
+	mac.w %a5l,%d1l,10(%a6),%a7,%acc2
+	mac.w %a5l,%d1l,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d1l,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d1l,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d1l,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d1l,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d1l,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d1l,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d1l,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d1l,-(%a1),%d1,%acc1
+	mac.w %a5l,%d1l,-(%a1),%d1,%acc2
+	mac.w %a5l,%d1l,-(%a1),%a3,%acc1
+	mac.w %a5l,%d1l,-(%a1),%a3,%acc2
+	mac.w %a5l,%d1l,-(%a1),%d2,%acc1
+	mac.w %a5l,%d1l,-(%a1),%d2,%acc2
+	mac.w %a5l,%d1l,-(%a1),%a7,%acc1
+	mac.w %a5l,%d1l,-(%a1),%a7,%acc2
+	mac.w %a5l,%d1l,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d1l,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d1l,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d1l,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d1l,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d1l,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d1l,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d1l,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d1l,<<,(%a3),%d1,%acc1
+	mac.w %a5l,%d1l,<<,(%a3),%d1,%acc2
+	mac.w %a5l,%d1l,<<,(%a3),%a3,%acc1
+	mac.w %a5l,%d1l,<<,(%a3),%a3,%acc2
+	mac.w %a5l,%d1l,<<,(%a3),%d2,%acc1
+	mac.w %a5l,%d1l,<<,(%a3),%d2,%acc2
+	mac.w %a5l,%d1l,<<,(%a3),%a7,%acc1
+	mac.w %a5l,%d1l,<<,(%a3),%a7,%acc2
+	mac.w %a5l,%d1l,<<,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d1l,<<,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d1l,<<,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d1l,<<,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d1l,<<,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d1l,<<,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d1l,<<,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d1l,<<,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6),%d1,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6),%d1,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6),%a3,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6),%a3,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6),%d2,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6),%d2,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6),%a7,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6),%a7,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1),%d1,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1),%d1,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1),%a3,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1),%a3,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1),%d2,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1),%d2,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1),%a7,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1),%a7,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d1l,>>,(%a3),%d1,%acc1
+	mac.w %a5l,%d1l,>>,(%a3),%d1,%acc2
+	mac.w %a5l,%d1l,>>,(%a3),%a3,%acc1
+	mac.w %a5l,%d1l,>>,(%a3),%a3,%acc2
+	mac.w %a5l,%d1l,>>,(%a3),%d2,%acc1
+	mac.w %a5l,%d1l,>>,(%a3),%d2,%acc2
+	mac.w %a5l,%d1l,>>,(%a3),%a7,%acc1
+	mac.w %a5l,%d1l,>>,(%a3),%a7,%acc2
+	mac.w %a5l,%d1l,>>,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d1l,>>,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d1l,>>,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d1l,>>,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d1l,>>,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d1l,>>,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d1l,>>,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d1l,>>,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6),%d1,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6),%d1,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6),%a3,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6),%a3,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6),%d2,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6),%d2,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6),%a7,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6),%a7,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1),%d1,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1),%d1,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1),%a3,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1),%a3,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1),%d2,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1),%d2,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1),%a7,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1),%a7,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d1l,#1,(%a3),%d1,%acc1
+	mac.w %a5l,%d1l,#1,(%a3),%d1,%acc2
+	mac.w %a5l,%d1l,#1,(%a3),%a3,%acc1
+	mac.w %a5l,%d1l,#1,(%a3),%a3,%acc2
+	mac.w %a5l,%d1l,#1,(%a3),%d2,%acc1
+	mac.w %a5l,%d1l,#1,(%a3),%d2,%acc2
+	mac.w %a5l,%d1l,#1,(%a3),%a7,%acc1
+	mac.w %a5l,%d1l,#1,(%a3),%a7,%acc2
+	mac.w %a5l,%d1l,#1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d1l,#1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d1l,#1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d1l,#1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d1l,#1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d1l,#1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d1l,#1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d1l,#1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6),%d1,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6),%d1,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6),%a3,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6),%a3,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6),%d2,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6),%d2,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6),%a7,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6),%a7,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1),%d1,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1),%d1,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1),%a3,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1),%a3,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1),%d2,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1),%d2,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1),%a7,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1),%a7,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a7,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3),%d1,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3),%d1,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3),%a3,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3),%a3,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3),%d2,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3),%d2,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3),%a7,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3),%a7,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d1,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d1,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a3,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a3,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d2,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d2,%acc2
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a7,%acc1
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a7,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d1,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d1,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a3,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a3,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d2,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d2,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a7,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a7,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6),%d1,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6),%d1,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6),%a3,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6),%a3,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6),%d2,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6),%d2,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6),%a7,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6),%a7,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1),%d1,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1),%d1,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1),%a3,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1),%a3,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1),%d2,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1),%d2,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1),%a7,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1),%a7,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a2u,(%a3),%d1,%acc1
+	mac.w %d6u,%a2u,(%a3),%d1,%acc2
+	mac.w %d6u,%a2u,(%a3),%a3,%acc1
+	mac.w %d6u,%a2u,(%a3),%a3,%acc2
+	mac.w %d6u,%a2u,(%a3),%d2,%acc1
+	mac.w %d6u,%a2u,(%a3),%d2,%acc2
+	mac.w %d6u,%a2u,(%a3),%a7,%acc1
+	mac.w %d6u,%a2u,(%a3),%a7,%acc2
+	mac.w %d6u,%a2u,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a2u,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a2u,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a2u,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a2u,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a2u,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a2u,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a2u,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a2u,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a2u,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a2u,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a2u,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a2u,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a2u,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a2u,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a2u,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a2u,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a2u,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a2u,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a2u,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a2u,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a2u,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a2u,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a2u,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a2u,10(%a6),%d1,%acc1
+	mac.w %d6u,%a2u,10(%a6),%d1,%acc2
+	mac.w %d6u,%a2u,10(%a6),%a3,%acc1
+	mac.w %d6u,%a2u,10(%a6),%a3,%acc2
+	mac.w %d6u,%a2u,10(%a6),%d2,%acc1
+	mac.w %d6u,%a2u,10(%a6),%d2,%acc2
+	mac.w %d6u,%a2u,10(%a6),%a7,%acc1
+	mac.w %d6u,%a2u,10(%a6),%a7,%acc2
+	mac.w %d6u,%a2u,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a2u,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a2u,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a2u,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a2u,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a2u,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a2u,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a2u,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a2u,-(%a1),%d1,%acc1
+	mac.w %d6u,%a2u,-(%a1),%d1,%acc2
+	mac.w %d6u,%a2u,-(%a1),%a3,%acc1
+	mac.w %d6u,%a2u,-(%a1),%a3,%acc2
+	mac.w %d6u,%a2u,-(%a1),%d2,%acc1
+	mac.w %d6u,%a2u,-(%a1),%d2,%acc2
+	mac.w %d6u,%a2u,-(%a1),%a7,%acc1
+	mac.w %d6u,%a2u,-(%a1),%a7,%acc2
+	mac.w %d6u,%a2u,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a2u,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a2u,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a2u,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a2u,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a2u,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a2u,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a2u,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a2u,<<,(%a3),%d1,%acc1
+	mac.w %d6u,%a2u,<<,(%a3),%d1,%acc2
+	mac.w %d6u,%a2u,<<,(%a3),%a3,%acc1
+	mac.w %d6u,%a2u,<<,(%a3),%a3,%acc2
+	mac.w %d6u,%a2u,<<,(%a3),%d2,%acc1
+	mac.w %d6u,%a2u,<<,(%a3),%d2,%acc2
+	mac.w %d6u,%a2u,<<,(%a3),%a7,%acc1
+	mac.w %d6u,%a2u,<<,(%a3),%a7,%acc2
+	mac.w %d6u,%a2u,<<,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a2u,<<,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a2u,<<,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a2u,<<,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a2u,<<,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a2u,<<,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a2u,<<,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a2u,<<,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6),%d1,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6),%d1,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6),%a3,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6),%a3,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6),%d2,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6),%d2,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6),%a7,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6),%a7,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1),%d1,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1),%d1,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1),%a3,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1),%a3,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1),%d2,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1),%d2,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1),%a7,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1),%a7,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a2u,>>,(%a3),%d1,%acc1
+	mac.w %d6u,%a2u,>>,(%a3),%d1,%acc2
+	mac.w %d6u,%a2u,>>,(%a3),%a3,%acc1
+	mac.w %d6u,%a2u,>>,(%a3),%a3,%acc2
+	mac.w %d6u,%a2u,>>,(%a3),%d2,%acc1
+	mac.w %d6u,%a2u,>>,(%a3),%d2,%acc2
+	mac.w %d6u,%a2u,>>,(%a3),%a7,%acc1
+	mac.w %d6u,%a2u,>>,(%a3),%a7,%acc2
+	mac.w %d6u,%a2u,>>,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a2u,>>,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a2u,>>,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a2u,>>,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a2u,>>,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a2u,>>,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a2u,>>,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a2u,>>,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6),%d1,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6),%d1,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6),%a3,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6),%a3,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6),%d2,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6),%d2,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6),%a7,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6),%a7,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1),%d1,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1),%d1,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1),%a3,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1),%a3,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1),%d2,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1),%d2,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1),%a7,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1),%a7,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a2u,#1,(%a3),%d1,%acc1
+	mac.w %d6u,%a2u,#1,(%a3),%d1,%acc2
+	mac.w %d6u,%a2u,#1,(%a3),%a3,%acc1
+	mac.w %d6u,%a2u,#1,(%a3),%a3,%acc2
+	mac.w %d6u,%a2u,#1,(%a3),%d2,%acc1
+	mac.w %d6u,%a2u,#1,(%a3),%d2,%acc2
+	mac.w %d6u,%a2u,#1,(%a3),%a7,%acc1
+	mac.w %d6u,%a2u,#1,(%a3),%a7,%acc2
+	mac.w %d6u,%a2u,#1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a2u,#1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a2u,#1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a2u,#1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a2u,#1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a2u,#1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a2u,#1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a2u,#1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6),%d1,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6),%d1,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6),%a3,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6),%a3,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6),%d2,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6),%d2,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6),%a7,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6),%a7,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1),%d1,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1),%d1,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1),%a3,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1),%a3,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1),%d2,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1),%d2,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1),%a7,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1),%a7,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3),%d1,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3),%d1,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3),%a3,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3),%a3,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3),%d2,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3),%d2,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3),%a7,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3),%a7,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6),%d1,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6),%d1,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6),%a3,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6),%a3,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6),%d2,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6),%d2,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6),%a7,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6),%a7,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1),%d1,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1),%d1,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1),%a3,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1),%a3,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1),%d2,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1),%d2,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1),%a7,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1),%a7,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d3l,(%a3),%d1,%acc1
+	mac.w %d6u,%d3l,(%a3),%d1,%acc2
+	mac.w %d6u,%d3l,(%a3),%a3,%acc1
+	mac.w %d6u,%d3l,(%a3),%a3,%acc2
+	mac.w %d6u,%d3l,(%a3),%d2,%acc1
+	mac.w %d6u,%d3l,(%a3),%d2,%acc2
+	mac.w %d6u,%d3l,(%a3),%a7,%acc1
+	mac.w %d6u,%d3l,(%a3),%a7,%acc2
+	mac.w %d6u,%d3l,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d3l,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d3l,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d3l,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d3l,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d3l,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d3l,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d3l,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d3l,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d3l,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d3l,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d3l,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d3l,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d3l,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d3l,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d3l,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d3l,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d3l,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d3l,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d3l,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d3l,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d3l,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d3l,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d3l,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d3l,10(%a6),%d1,%acc1
+	mac.w %d6u,%d3l,10(%a6),%d1,%acc2
+	mac.w %d6u,%d3l,10(%a6),%a3,%acc1
+	mac.w %d6u,%d3l,10(%a6),%a3,%acc2
+	mac.w %d6u,%d3l,10(%a6),%d2,%acc1
+	mac.w %d6u,%d3l,10(%a6),%d2,%acc2
+	mac.w %d6u,%d3l,10(%a6),%a7,%acc1
+	mac.w %d6u,%d3l,10(%a6),%a7,%acc2
+	mac.w %d6u,%d3l,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d3l,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d3l,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d3l,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d3l,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d3l,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d3l,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d3l,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d3l,-(%a1),%d1,%acc1
+	mac.w %d6u,%d3l,-(%a1),%d1,%acc2
+	mac.w %d6u,%d3l,-(%a1),%a3,%acc1
+	mac.w %d6u,%d3l,-(%a1),%a3,%acc2
+	mac.w %d6u,%d3l,-(%a1),%d2,%acc1
+	mac.w %d6u,%d3l,-(%a1),%d2,%acc2
+	mac.w %d6u,%d3l,-(%a1),%a7,%acc1
+	mac.w %d6u,%d3l,-(%a1),%a7,%acc2
+	mac.w %d6u,%d3l,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d3l,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d3l,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d3l,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d3l,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d3l,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d3l,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d3l,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d3l,<<,(%a3),%d1,%acc1
+	mac.w %d6u,%d3l,<<,(%a3),%d1,%acc2
+	mac.w %d6u,%d3l,<<,(%a3),%a3,%acc1
+	mac.w %d6u,%d3l,<<,(%a3),%a3,%acc2
+	mac.w %d6u,%d3l,<<,(%a3),%d2,%acc1
+	mac.w %d6u,%d3l,<<,(%a3),%d2,%acc2
+	mac.w %d6u,%d3l,<<,(%a3),%a7,%acc1
+	mac.w %d6u,%d3l,<<,(%a3),%a7,%acc2
+	mac.w %d6u,%d3l,<<,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d3l,<<,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d3l,<<,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d3l,<<,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d3l,<<,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d3l,<<,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d3l,<<,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d3l,<<,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6),%d1,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6),%d1,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6),%a3,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6),%a3,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6),%d2,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6),%d2,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6),%a7,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6),%a7,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1),%d1,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1),%d1,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1),%a3,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1),%a3,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1),%d2,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1),%d2,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1),%a7,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1),%a7,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d3l,>>,(%a3),%d1,%acc1
+	mac.w %d6u,%d3l,>>,(%a3),%d1,%acc2
+	mac.w %d6u,%d3l,>>,(%a3),%a3,%acc1
+	mac.w %d6u,%d3l,>>,(%a3),%a3,%acc2
+	mac.w %d6u,%d3l,>>,(%a3),%d2,%acc1
+	mac.w %d6u,%d3l,>>,(%a3),%d2,%acc2
+	mac.w %d6u,%d3l,>>,(%a3),%a7,%acc1
+	mac.w %d6u,%d3l,>>,(%a3),%a7,%acc2
+	mac.w %d6u,%d3l,>>,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d3l,>>,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d3l,>>,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d3l,>>,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d3l,>>,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d3l,>>,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d3l,>>,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d3l,>>,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6),%d1,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6),%d1,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6),%a3,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6),%a3,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6),%d2,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6),%d2,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6),%a7,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6),%a7,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1),%d1,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1),%d1,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1),%a3,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1),%a3,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1),%d2,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1),%d2,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1),%a7,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1),%a7,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d3l,#1,(%a3),%d1,%acc1
+	mac.w %d6u,%d3l,#1,(%a3),%d1,%acc2
+	mac.w %d6u,%d3l,#1,(%a3),%a3,%acc1
+	mac.w %d6u,%d3l,#1,(%a3),%a3,%acc2
+	mac.w %d6u,%d3l,#1,(%a3),%d2,%acc1
+	mac.w %d6u,%d3l,#1,(%a3),%d2,%acc2
+	mac.w %d6u,%d3l,#1,(%a3),%a7,%acc1
+	mac.w %d6u,%d3l,#1,(%a3),%a7,%acc2
+	mac.w %d6u,%d3l,#1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d3l,#1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d3l,#1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d3l,#1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d3l,#1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d3l,#1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d3l,#1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d3l,#1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6),%d1,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6),%d1,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6),%a3,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6),%a3,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6),%d2,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6),%d2,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6),%a7,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6),%a7,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1),%d1,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1),%d1,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1),%a3,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1),%a3,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1),%d2,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1),%d2,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1),%a7,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1),%a7,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3),%d1,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3),%d1,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3),%a3,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3),%a3,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3),%d2,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3),%d2,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3),%a7,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3),%a7,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6),%d1,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6),%d1,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6),%a3,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6),%a3,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6),%d2,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6),%d2,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6),%a7,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6),%a7,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1),%d1,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1),%d1,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1),%a3,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1),%a3,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1),%d2,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1),%d2,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1),%a7,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1),%a7,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a7u,(%a3),%d1,%acc1
+	mac.w %d6u,%a7u,(%a3),%d1,%acc2
+	mac.w %d6u,%a7u,(%a3),%a3,%acc1
+	mac.w %d6u,%a7u,(%a3),%a3,%acc2
+	mac.w %d6u,%a7u,(%a3),%d2,%acc1
+	mac.w %d6u,%a7u,(%a3),%d2,%acc2
+	mac.w %d6u,%a7u,(%a3),%a7,%acc1
+	mac.w %d6u,%a7u,(%a3),%a7,%acc2
+	mac.w %d6u,%a7u,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a7u,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a7u,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a7u,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a7u,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a7u,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a7u,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a7u,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a7u,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a7u,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a7u,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a7u,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a7u,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a7u,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a7u,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a7u,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a7u,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a7u,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a7u,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a7u,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a7u,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a7u,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a7u,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a7u,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a7u,10(%a6),%d1,%acc1
+	mac.w %d6u,%a7u,10(%a6),%d1,%acc2
+	mac.w %d6u,%a7u,10(%a6),%a3,%acc1
+	mac.w %d6u,%a7u,10(%a6),%a3,%acc2
+	mac.w %d6u,%a7u,10(%a6),%d2,%acc1
+	mac.w %d6u,%a7u,10(%a6),%d2,%acc2
+	mac.w %d6u,%a7u,10(%a6),%a7,%acc1
+	mac.w %d6u,%a7u,10(%a6),%a7,%acc2
+	mac.w %d6u,%a7u,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a7u,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a7u,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a7u,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a7u,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a7u,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a7u,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a7u,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a7u,-(%a1),%d1,%acc1
+	mac.w %d6u,%a7u,-(%a1),%d1,%acc2
+	mac.w %d6u,%a7u,-(%a1),%a3,%acc1
+	mac.w %d6u,%a7u,-(%a1),%a3,%acc2
+	mac.w %d6u,%a7u,-(%a1),%d2,%acc1
+	mac.w %d6u,%a7u,-(%a1),%d2,%acc2
+	mac.w %d6u,%a7u,-(%a1),%a7,%acc1
+	mac.w %d6u,%a7u,-(%a1),%a7,%acc2
+	mac.w %d6u,%a7u,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a7u,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a7u,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a7u,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a7u,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a7u,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a7u,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a7u,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a7u,<<,(%a3),%d1,%acc1
+	mac.w %d6u,%a7u,<<,(%a3),%d1,%acc2
+	mac.w %d6u,%a7u,<<,(%a3),%a3,%acc1
+	mac.w %d6u,%a7u,<<,(%a3),%a3,%acc2
+	mac.w %d6u,%a7u,<<,(%a3),%d2,%acc1
+	mac.w %d6u,%a7u,<<,(%a3),%d2,%acc2
+	mac.w %d6u,%a7u,<<,(%a3),%a7,%acc1
+	mac.w %d6u,%a7u,<<,(%a3),%a7,%acc2
+	mac.w %d6u,%a7u,<<,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a7u,<<,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a7u,<<,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a7u,<<,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a7u,<<,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a7u,<<,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a7u,<<,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a7u,<<,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6),%d1,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6),%d1,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6),%a3,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6),%a3,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6),%d2,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6),%d2,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6),%a7,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6),%a7,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1),%d1,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1),%d1,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1),%a3,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1),%a3,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1),%d2,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1),%d2,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1),%a7,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1),%a7,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a7u,>>,(%a3),%d1,%acc1
+	mac.w %d6u,%a7u,>>,(%a3),%d1,%acc2
+	mac.w %d6u,%a7u,>>,(%a3),%a3,%acc1
+	mac.w %d6u,%a7u,>>,(%a3),%a3,%acc2
+	mac.w %d6u,%a7u,>>,(%a3),%d2,%acc1
+	mac.w %d6u,%a7u,>>,(%a3),%d2,%acc2
+	mac.w %d6u,%a7u,>>,(%a3),%a7,%acc1
+	mac.w %d6u,%a7u,>>,(%a3),%a7,%acc2
+	mac.w %d6u,%a7u,>>,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a7u,>>,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a7u,>>,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a7u,>>,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a7u,>>,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a7u,>>,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a7u,>>,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a7u,>>,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6),%d1,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6),%d1,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6),%a3,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6),%a3,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6),%d2,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6),%d2,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6),%a7,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6),%a7,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1),%d1,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1),%d1,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1),%a3,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1),%a3,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1),%d2,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1),%d2,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1),%a7,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1),%a7,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a7u,#1,(%a3),%d1,%acc1
+	mac.w %d6u,%a7u,#1,(%a3),%d1,%acc2
+	mac.w %d6u,%a7u,#1,(%a3),%a3,%acc1
+	mac.w %d6u,%a7u,#1,(%a3),%a3,%acc2
+	mac.w %d6u,%a7u,#1,(%a3),%d2,%acc1
+	mac.w %d6u,%a7u,#1,(%a3),%d2,%acc2
+	mac.w %d6u,%a7u,#1,(%a3),%a7,%acc1
+	mac.w %d6u,%a7u,#1,(%a3),%a7,%acc2
+	mac.w %d6u,%a7u,#1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a7u,#1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a7u,#1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a7u,#1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a7u,#1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a7u,#1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a7u,#1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a7u,#1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6),%d1,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6),%d1,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6),%a3,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6),%a3,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6),%d2,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6),%d2,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6),%a7,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6),%a7,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1),%d1,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1),%d1,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1),%a3,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1),%a3,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1),%d2,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1),%d2,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1),%a7,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1),%a7,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3),%d1,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3),%d1,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3),%a3,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3),%a3,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3),%d2,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3),%d2,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3),%a7,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3),%a7,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6),%d1,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6),%d1,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6),%a3,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6),%a3,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6),%d2,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6),%d2,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6),%a7,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6),%a7,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1),%d1,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1),%d1,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1),%a3,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1),%a3,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1),%d2,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1),%d2,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1),%a7,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1),%a7,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d1l,(%a3),%d1,%acc1
+	mac.w %d6u,%d1l,(%a3),%d1,%acc2
+	mac.w %d6u,%d1l,(%a3),%a3,%acc1
+	mac.w %d6u,%d1l,(%a3),%a3,%acc2
+	mac.w %d6u,%d1l,(%a3),%d2,%acc1
+	mac.w %d6u,%d1l,(%a3),%d2,%acc2
+	mac.w %d6u,%d1l,(%a3),%a7,%acc1
+	mac.w %d6u,%d1l,(%a3),%a7,%acc2
+	mac.w %d6u,%d1l,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d1l,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d1l,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d1l,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d1l,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d1l,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d1l,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d1l,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d1l,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d1l,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d1l,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d1l,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d1l,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d1l,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d1l,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d1l,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d1l,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d1l,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d1l,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d1l,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d1l,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d1l,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d1l,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d1l,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d1l,10(%a6),%d1,%acc1
+	mac.w %d6u,%d1l,10(%a6),%d1,%acc2
+	mac.w %d6u,%d1l,10(%a6),%a3,%acc1
+	mac.w %d6u,%d1l,10(%a6),%a3,%acc2
+	mac.w %d6u,%d1l,10(%a6),%d2,%acc1
+	mac.w %d6u,%d1l,10(%a6),%d2,%acc2
+	mac.w %d6u,%d1l,10(%a6),%a7,%acc1
+	mac.w %d6u,%d1l,10(%a6),%a7,%acc2
+	mac.w %d6u,%d1l,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d1l,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d1l,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d1l,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d1l,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d1l,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d1l,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d1l,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d1l,-(%a1),%d1,%acc1
+	mac.w %d6u,%d1l,-(%a1),%d1,%acc2
+	mac.w %d6u,%d1l,-(%a1),%a3,%acc1
+	mac.w %d6u,%d1l,-(%a1),%a3,%acc2
+	mac.w %d6u,%d1l,-(%a1),%d2,%acc1
+	mac.w %d6u,%d1l,-(%a1),%d2,%acc2
+	mac.w %d6u,%d1l,-(%a1),%a7,%acc1
+	mac.w %d6u,%d1l,-(%a1),%a7,%acc2
+	mac.w %d6u,%d1l,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d1l,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d1l,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d1l,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d1l,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d1l,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d1l,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d1l,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d1l,<<,(%a3),%d1,%acc1
+	mac.w %d6u,%d1l,<<,(%a3),%d1,%acc2
+	mac.w %d6u,%d1l,<<,(%a3),%a3,%acc1
+	mac.w %d6u,%d1l,<<,(%a3),%a3,%acc2
+	mac.w %d6u,%d1l,<<,(%a3),%d2,%acc1
+	mac.w %d6u,%d1l,<<,(%a3),%d2,%acc2
+	mac.w %d6u,%d1l,<<,(%a3),%a7,%acc1
+	mac.w %d6u,%d1l,<<,(%a3),%a7,%acc2
+	mac.w %d6u,%d1l,<<,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d1l,<<,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d1l,<<,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d1l,<<,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d1l,<<,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d1l,<<,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d1l,<<,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d1l,<<,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6),%d1,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6),%d1,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6),%a3,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6),%a3,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6),%d2,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6),%d2,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6),%a7,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6),%a7,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1),%d1,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1),%d1,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1),%a3,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1),%a3,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1),%d2,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1),%d2,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1),%a7,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1),%a7,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d1l,>>,(%a3),%d1,%acc1
+	mac.w %d6u,%d1l,>>,(%a3),%d1,%acc2
+	mac.w %d6u,%d1l,>>,(%a3),%a3,%acc1
+	mac.w %d6u,%d1l,>>,(%a3),%a3,%acc2
+	mac.w %d6u,%d1l,>>,(%a3),%d2,%acc1
+	mac.w %d6u,%d1l,>>,(%a3),%d2,%acc2
+	mac.w %d6u,%d1l,>>,(%a3),%a7,%acc1
+	mac.w %d6u,%d1l,>>,(%a3),%a7,%acc2
+	mac.w %d6u,%d1l,>>,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d1l,>>,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d1l,>>,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d1l,>>,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d1l,>>,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d1l,>>,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d1l,>>,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d1l,>>,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6),%d1,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6),%d1,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6),%a3,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6),%a3,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6),%d2,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6),%d2,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6),%a7,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6),%a7,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1),%d1,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1),%d1,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1),%a3,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1),%a3,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1),%d2,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1),%d2,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1),%a7,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1),%a7,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d1l,#1,(%a3),%d1,%acc1
+	mac.w %d6u,%d1l,#1,(%a3),%d1,%acc2
+	mac.w %d6u,%d1l,#1,(%a3),%a3,%acc1
+	mac.w %d6u,%d1l,#1,(%a3),%a3,%acc2
+	mac.w %d6u,%d1l,#1,(%a3),%d2,%acc1
+	mac.w %d6u,%d1l,#1,(%a3),%d2,%acc2
+	mac.w %d6u,%d1l,#1,(%a3),%a7,%acc1
+	mac.w %d6u,%d1l,#1,(%a3),%a7,%acc2
+	mac.w %d6u,%d1l,#1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d1l,#1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d1l,#1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d1l,#1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d1l,#1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d1l,#1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d1l,#1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d1l,#1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6),%d1,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6),%d1,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6),%a3,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6),%a3,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6),%d2,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6),%d2,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6),%a7,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6),%a7,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1),%d1,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1),%d1,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1),%a3,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1),%a3,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1),%d2,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1),%d2,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1),%a7,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1),%a7,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a7,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3),%d1,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3),%d1,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3),%a3,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3),%a3,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3),%d2,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3),%d2,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3),%a7,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3),%a7,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d1,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d1,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a3,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a3,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d2,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d2,%acc2
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a7,%acc1
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a7,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d1,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d1,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a3,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a3,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d2,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d2,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a7,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a7,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d1,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d1,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a3,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a3,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d2,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d2,%acc2
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a7,%acc1
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a7,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6),%d1,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6),%d1,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6),%a3,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6),%a3,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6),%d2,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6),%d2,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6),%a7,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6),%a7,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d1,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d1,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a3,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a3,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d2,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d2,%acc2
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a7,%acc1
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a7,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1),%d1,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1),%d1,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1),%a3,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1),%a3,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1),%d2,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1),%d2,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1),%a7,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1),%a7,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d1,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d1,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a3,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a3,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d2,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d2,%acc2
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a7,%acc1
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a7,%acc2
+
+	mac.l %a1,%a3,%acc1
+	mac.l %a1,%a3,%acc2
+	mac.l %a1,%a3,<<,%acc1
+	mac.l %a1,%a3,<<,%acc2
+	mac.l %a1,%a3,>>,%acc1
+	mac.l %a1,%a3,>>,%acc2
+	mac.l %a1,%a3,#1,%acc1
+	mac.l %a1,%a3,#1,%acc2
+	mac.l %a1,%a3,#-1,%acc1
+	mac.l %a1,%a3,#-1,%acc2
+	mac.l %a1,%d4,%acc1
+	mac.l %a1,%d4,%acc2
+	mac.l %a1,%d4,<<,%acc1
+	mac.l %a1,%d4,<<,%acc2
+	mac.l %a1,%d4,>>,%acc1
+	mac.l %a1,%d4,>>,%acc2
+	mac.l %a1,%d4,#1,%acc1
+	mac.l %a1,%d4,#1,%acc2
+	mac.l %a1,%d4,#-1,%acc1
+	mac.l %a1,%d4,#-1,%acc2
+	mac.l %d6,%a3,%acc1
+	mac.l %d6,%a3,%acc2
+	mac.l %d6,%a3,<<,%acc1
+	mac.l %d6,%a3,<<,%acc2
+	mac.l %d6,%a3,>>,%acc1
+	mac.l %d6,%a3,>>,%acc2
+	mac.l %d6,%a3,#1,%acc1
+	mac.l %d6,%a3,#1,%acc2
+	mac.l %d6,%a3,#-1,%acc1
+	mac.l %d6,%a3,#-1,%acc2
+	mac.l %d6,%d4,%acc1
+	mac.l %d6,%d4,%acc2
+	mac.l %d6,%d4,<<,%acc1
+	mac.l %d6,%d4,<<,%acc2
+	mac.l %d6,%d4,>>,%acc1
+	mac.l %d6,%d4,>>,%acc2
+	mac.l %d6,%d4,#1,%acc1
+	mac.l %d6,%d4,#1,%acc2
+	mac.l %d6,%d4,#-1,%acc1
+	mac.l %d6,%d4,#-1,%acc2
+
+	mac.l %a1,%a3,(%a3),%d1,%acc1
+	mac.l %a1,%a3,(%a3),%d1,%acc2
+	mac.l %a1,%a3,(%a3),%a3,%acc1
+	mac.l %a1,%a3,(%a3),%a3,%acc2
+	mac.l %a1,%a3,(%a3),%d2,%acc1
+	mac.l %a1,%a3,(%a3),%d2,%acc2
+	mac.l %a1,%a3,(%a3),%a7,%acc1
+	mac.l %a1,%a3,(%a3),%a7,%acc2
+	mac.l %a1,%a3,(%a3)&,%d1,%acc1
+	mac.l %a1,%a3,(%a3)&,%d1,%acc2
+	mac.l %a1,%a3,(%a3)&,%a3,%acc1
+	mac.l %a1,%a3,(%a3)&,%a3,%acc2
+	mac.l %a1,%a3,(%a3)&,%d2,%acc1
+	mac.l %a1,%a3,(%a3)&,%d2,%acc2
+	mac.l %a1,%a3,(%a3)&,%a7,%acc1
+	mac.l %a1,%a3,(%a3)&,%a7,%acc2
+	mac.l %a1,%a3,(%a2)+,%d1,%acc1
+	mac.l %a1,%a3,(%a2)+,%d1,%acc2
+	mac.l %a1,%a3,(%a2)+,%a3,%acc1
+	mac.l %a1,%a3,(%a2)+,%a3,%acc2
+	mac.l %a1,%a3,(%a2)+,%d2,%acc1
+	mac.l %a1,%a3,(%a2)+,%d2,%acc2
+	mac.l %a1,%a3,(%a2)+,%a7,%acc1
+	mac.l %a1,%a3,(%a2)+,%a7,%acc2
+	mac.l %a1,%a3,(%a2)+&,%d1,%acc1
+	mac.l %a1,%a3,(%a2)+&,%d1,%acc2
+	mac.l %a1,%a3,(%a2)+&,%a3,%acc1
+	mac.l %a1,%a3,(%a2)+&,%a3,%acc2
+	mac.l %a1,%a3,(%a2)+&,%d2,%acc1
+	mac.l %a1,%a3,(%a2)+&,%d2,%acc2
+	mac.l %a1,%a3,(%a2)+&,%a7,%acc1
+	mac.l %a1,%a3,(%a2)+&,%a7,%acc2
+	mac.l %a1,%a3,10(%a6),%d1,%acc1
+	mac.l %a1,%a3,10(%a6),%d1,%acc2
+	mac.l %a1,%a3,10(%a6),%a3,%acc1
+	mac.l %a1,%a3,10(%a6),%a3,%acc2
+	mac.l %a1,%a3,10(%a6),%d2,%acc1
+	mac.l %a1,%a3,10(%a6),%d2,%acc2
+	mac.l %a1,%a3,10(%a6),%a7,%acc1
+	mac.l %a1,%a3,10(%a6),%a7,%acc2
+	mac.l %a1,%a3,10(%a6)&,%d1,%acc1
+	mac.l %a1,%a3,10(%a6)&,%d1,%acc2
+	mac.l %a1,%a3,10(%a6)&,%a3,%acc1
+	mac.l %a1,%a3,10(%a6)&,%a3,%acc2
+	mac.l %a1,%a3,10(%a6)&,%d2,%acc1
+	mac.l %a1,%a3,10(%a6)&,%d2,%acc2
+	mac.l %a1,%a3,10(%a6)&,%a7,%acc1
+	mac.l %a1,%a3,10(%a6)&,%a7,%acc2
+	mac.l %a1,%a3,-(%a1),%d1,%acc1
+	mac.l %a1,%a3,-(%a1),%d1,%acc2
+	mac.l %a1,%a3,-(%a1),%a3,%acc1
+	mac.l %a1,%a3,-(%a1),%a3,%acc2
+	mac.l %a1,%a3,-(%a1),%d2,%acc1
+	mac.l %a1,%a3,-(%a1),%d2,%acc2
+	mac.l %a1,%a3,-(%a1),%a7,%acc1
+	mac.l %a1,%a3,-(%a1),%a7,%acc2
+	mac.l %a1,%a3,-(%a1)&,%d1,%acc1
+	mac.l %a1,%a3,-(%a1)&,%d1,%acc2
+	mac.l %a1,%a3,-(%a1)&,%a3,%acc1
+	mac.l %a1,%a3,-(%a1)&,%a3,%acc2
+	mac.l %a1,%a3,-(%a1)&,%d2,%acc1
+	mac.l %a1,%a3,-(%a1)&,%d2,%acc2
+	mac.l %a1,%a3,-(%a1)&,%a7,%acc1
+	mac.l %a1,%a3,-(%a1)&,%a7,%acc2
+	mac.l %a1,%a3,<<,(%a3),%d1,%acc1
+	mac.l %a1,%a3,<<,(%a3),%d1,%acc2
+	mac.l %a1,%a3,<<,(%a3),%a3,%acc1
+	mac.l %a1,%a3,<<,(%a3),%a3,%acc2
+	mac.l %a1,%a3,<<,(%a3),%d2,%acc1
+	mac.l %a1,%a3,<<,(%a3),%d2,%acc2
+	mac.l %a1,%a3,<<,(%a3),%a7,%acc1
+	mac.l %a1,%a3,<<,(%a3),%a7,%acc2
+	mac.l %a1,%a3,<<,(%a3)&,%d1,%acc1
+	mac.l %a1,%a3,<<,(%a3)&,%d1,%acc2
+	mac.l %a1,%a3,<<,(%a3)&,%a3,%acc1
+	mac.l %a1,%a3,<<,(%a3)&,%a3,%acc2
+	mac.l %a1,%a3,<<,(%a3)&,%d2,%acc1
+	mac.l %a1,%a3,<<,(%a3)&,%d2,%acc2
+	mac.l %a1,%a3,<<,(%a3)&,%a7,%acc1
+	mac.l %a1,%a3,<<,(%a3)&,%a7,%acc2
+	mac.l %a1,%a3,<<,(%a2)+,%d1,%acc1
+	mac.l %a1,%a3,<<,(%a2)+,%d1,%acc2
+	mac.l %a1,%a3,<<,(%a2)+,%a3,%acc1
+	mac.l %a1,%a3,<<,(%a2)+,%a3,%acc2
+	mac.l %a1,%a3,<<,(%a2)+,%d2,%acc1
+	mac.l %a1,%a3,<<,(%a2)+,%d2,%acc2
+	mac.l %a1,%a3,<<,(%a2)+,%a7,%acc1
+	mac.l %a1,%a3,<<,(%a2)+,%a7,%acc2
+	mac.l %a1,%a3,<<,(%a2)+&,%d1,%acc1
+	mac.l %a1,%a3,<<,(%a2)+&,%d1,%acc2
+	mac.l %a1,%a3,<<,(%a2)+&,%a3,%acc1
+	mac.l %a1,%a3,<<,(%a2)+&,%a3,%acc2
+	mac.l %a1,%a3,<<,(%a2)+&,%d2,%acc1
+	mac.l %a1,%a3,<<,(%a2)+&,%d2,%acc2
+	mac.l %a1,%a3,<<,(%a2)+&,%a7,%acc1
+	mac.l %a1,%a3,<<,(%a2)+&,%a7,%acc2
+	mac.l %a1,%a3,<<,10(%a6),%d1,%acc1
+	mac.l %a1,%a3,<<,10(%a6),%d1,%acc2
+	mac.l %a1,%a3,<<,10(%a6),%a3,%acc1
+	mac.l %a1,%a3,<<,10(%a6),%a3,%acc2
+	mac.l %a1,%a3,<<,10(%a6),%d2,%acc1
+	mac.l %a1,%a3,<<,10(%a6),%d2,%acc2
+	mac.l %a1,%a3,<<,10(%a6),%a7,%acc1
+	mac.l %a1,%a3,<<,10(%a6),%a7,%acc2
+	mac.l %a1,%a3,<<,10(%a6)&,%d1,%acc1
+	mac.l %a1,%a3,<<,10(%a6)&,%d1,%acc2
+	mac.l %a1,%a3,<<,10(%a6)&,%a3,%acc1
+	mac.l %a1,%a3,<<,10(%a6)&,%a3,%acc2
+	mac.l %a1,%a3,<<,10(%a6)&,%d2,%acc1
+	mac.l %a1,%a3,<<,10(%a6)&,%d2,%acc2
+	mac.l %a1,%a3,<<,10(%a6)&,%a7,%acc1
+	mac.l %a1,%a3,<<,10(%a6)&,%a7,%acc2
+	mac.l %a1,%a3,<<,-(%a1),%d1,%acc1
+	mac.l %a1,%a3,<<,-(%a1),%d1,%acc2
+	mac.l %a1,%a3,<<,-(%a1),%a3,%acc1
+	mac.l %a1,%a3,<<,-(%a1),%a3,%acc2
+	mac.l %a1,%a3,<<,-(%a1),%d2,%acc1
+	mac.l %a1,%a3,<<,-(%a1),%d2,%acc2
+	mac.l %a1,%a3,<<,-(%a1),%a7,%acc1
+	mac.l %a1,%a3,<<,-(%a1),%a7,%acc2
+	mac.l %a1,%a3,<<,-(%a1)&,%d1,%acc1
+	mac.l %a1,%a3,<<,-(%a1)&,%d1,%acc2
+	mac.l %a1,%a3,<<,-(%a1)&,%a3,%acc1
+	mac.l %a1,%a3,<<,-(%a1)&,%a3,%acc2
+	mac.l %a1,%a3,<<,-(%a1)&,%d2,%acc1
+	mac.l %a1,%a3,<<,-(%a1)&,%d2,%acc2
+	mac.l %a1,%a3,<<,-(%a1)&,%a7,%acc1
+	mac.l %a1,%a3,<<,-(%a1)&,%a7,%acc2
+	mac.l %a1,%a3,>>,(%a3),%d1,%acc1
+	mac.l %a1,%a3,>>,(%a3),%d1,%acc2
+	mac.l %a1,%a3,>>,(%a3),%a3,%acc1
+	mac.l %a1,%a3,>>,(%a3),%a3,%acc2
+	mac.l %a1,%a3,>>,(%a3),%d2,%acc1
+	mac.l %a1,%a3,>>,(%a3),%d2,%acc2
+	mac.l %a1,%a3,>>,(%a3),%a7,%acc1
+	mac.l %a1,%a3,>>,(%a3),%a7,%acc2
+	mac.l %a1,%a3,>>,(%a3)&,%d1,%acc1
+	mac.l %a1,%a3,>>,(%a3)&,%d1,%acc2
+	mac.l %a1,%a3,>>,(%a3)&,%a3,%acc1
+	mac.l %a1,%a3,>>,(%a3)&,%a3,%acc2
+	mac.l %a1,%a3,>>,(%a3)&,%d2,%acc1
+	mac.l %a1,%a3,>>,(%a3)&,%d2,%acc2
+	mac.l %a1,%a3,>>,(%a3)&,%a7,%acc1
+	mac.l %a1,%a3,>>,(%a3)&,%a7,%acc2
+	mac.l %a1,%a3,>>,(%a2)+,%d1,%acc1
+	mac.l %a1,%a3,>>,(%a2)+,%d1,%acc2
+	mac.l %a1,%a3,>>,(%a2)+,%a3,%acc1
+	mac.l %a1,%a3,>>,(%a2)+,%a3,%acc2
+	mac.l %a1,%a3,>>,(%a2)+,%d2,%acc1
+	mac.l %a1,%a3,>>,(%a2)+,%d2,%acc2
+	mac.l %a1,%a3,>>,(%a2)+,%a7,%acc1
+	mac.l %a1,%a3,>>,(%a2)+,%a7,%acc2
+	mac.l %a1,%a3,>>,(%a2)+&,%d1,%acc1
+	mac.l %a1,%a3,>>,(%a2)+&,%d1,%acc2
+	mac.l %a1,%a3,>>,(%a2)+&,%a3,%acc1
+	mac.l %a1,%a3,>>,(%a2)+&,%a3,%acc2
+	mac.l %a1,%a3,>>,(%a2)+&,%d2,%acc1
+	mac.l %a1,%a3,>>,(%a2)+&,%d2,%acc2
+	mac.l %a1,%a3,>>,(%a2)+&,%a7,%acc1
+	mac.l %a1,%a3,>>,(%a2)+&,%a7,%acc2
+	mac.l %a1,%a3,>>,10(%a6),%d1,%acc1
+	mac.l %a1,%a3,>>,10(%a6),%d1,%acc2
+	mac.l %a1,%a3,>>,10(%a6),%a3,%acc1
+	mac.l %a1,%a3,>>,10(%a6),%a3,%acc2
+	mac.l %a1,%a3,>>,10(%a6),%d2,%acc1
+	mac.l %a1,%a3,>>,10(%a6),%d2,%acc2
+	mac.l %a1,%a3,>>,10(%a6),%a7,%acc1
+	mac.l %a1,%a3,>>,10(%a6),%a7,%acc2
+	mac.l %a1,%a3,>>,10(%a6)&,%d1,%acc1
+	mac.l %a1,%a3,>>,10(%a6)&,%d1,%acc2
+	mac.l %a1,%a3,>>,10(%a6)&,%a3,%acc1
+	mac.l %a1,%a3,>>,10(%a6)&,%a3,%acc2
+	mac.l %a1,%a3,>>,10(%a6)&,%d2,%acc1
+	mac.l %a1,%a3,>>,10(%a6)&,%d2,%acc2
+	mac.l %a1,%a3,>>,10(%a6)&,%a7,%acc1
+	mac.l %a1,%a3,>>,10(%a6)&,%a7,%acc2
+	mac.l %a1,%a3,>>,-(%a1),%d1,%acc1
+	mac.l %a1,%a3,>>,-(%a1),%d1,%acc2
+	mac.l %a1,%a3,>>,-(%a1),%a3,%acc1
+	mac.l %a1,%a3,>>,-(%a1),%a3,%acc2
+	mac.l %a1,%a3,>>,-(%a1),%d2,%acc1
+	mac.l %a1,%a3,>>,-(%a1),%d2,%acc2
+	mac.l %a1,%a3,>>,-(%a1),%a7,%acc1
+	mac.l %a1,%a3,>>,-(%a1),%a7,%acc2
+	mac.l %a1,%a3,>>,-(%a1)&,%d1,%acc1
+	mac.l %a1,%a3,>>,-(%a1)&,%d1,%acc2
+	mac.l %a1,%a3,>>,-(%a1)&,%a3,%acc1
+	mac.l %a1,%a3,>>,-(%a1)&,%a3,%acc2
+	mac.l %a1,%a3,>>,-(%a1)&,%d2,%acc1
+	mac.l %a1,%a3,>>,-(%a1)&,%d2,%acc2
+	mac.l %a1,%a3,>>,-(%a1)&,%a7,%acc1
+	mac.l %a1,%a3,>>,-(%a1)&,%a7,%acc2
+	mac.l %a1,%a3,#1,(%a3),%d1,%acc1
+	mac.l %a1,%a3,#1,(%a3),%d1,%acc2
+	mac.l %a1,%a3,#1,(%a3),%a3,%acc1
+	mac.l %a1,%a3,#1,(%a3),%a3,%acc2
+	mac.l %a1,%a3,#1,(%a3),%d2,%acc1
+	mac.l %a1,%a3,#1,(%a3),%d2,%acc2
+	mac.l %a1,%a3,#1,(%a3),%a7,%acc1
+	mac.l %a1,%a3,#1,(%a3),%a7,%acc2
+	mac.l %a1,%a3,#1,(%a3)&,%d1,%acc1
+	mac.l %a1,%a3,#1,(%a3)&,%d1,%acc2
+	mac.l %a1,%a3,#1,(%a3)&,%a3,%acc1
+	mac.l %a1,%a3,#1,(%a3)&,%a3,%acc2
+	mac.l %a1,%a3,#1,(%a3)&,%d2,%acc1
+	mac.l %a1,%a3,#1,(%a3)&,%d2,%acc2
+	mac.l %a1,%a3,#1,(%a3)&,%a7,%acc1
+	mac.l %a1,%a3,#1,(%a3)&,%a7,%acc2
+	mac.l %a1,%a3,#1,(%a2)+,%d1,%acc1
+	mac.l %a1,%a3,#1,(%a2)+,%d1,%acc2
+	mac.l %a1,%a3,#1,(%a2)+,%a3,%acc1
+	mac.l %a1,%a3,#1,(%a2)+,%a3,%acc2
+	mac.l %a1,%a3,#1,(%a2)+,%d2,%acc1
+	mac.l %a1,%a3,#1,(%a2)+,%d2,%acc2
+	mac.l %a1,%a3,#1,(%a2)+,%a7,%acc1
+	mac.l %a1,%a3,#1,(%a2)+,%a7,%acc2
+	mac.l %a1,%a3,#1,(%a2)+&,%d1,%acc1
+	mac.l %a1,%a3,#1,(%a2)+&,%d1,%acc2
+	mac.l %a1,%a3,#1,(%a2)+&,%a3,%acc1
+	mac.l %a1,%a3,#1,(%a2)+&,%a3,%acc2
+	mac.l %a1,%a3,#1,(%a2)+&,%d2,%acc1
+	mac.l %a1,%a3,#1,(%a2)+&,%d2,%acc2
+	mac.l %a1,%a3,#1,(%a2)+&,%a7,%acc1
+	mac.l %a1,%a3,#1,(%a2)+&,%a7,%acc2
+	mac.l %a1,%a3,#1,10(%a6),%d1,%acc1
+	mac.l %a1,%a3,#1,10(%a6),%d1,%acc2
+	mac.l %a1,%a3,#1,10(%a6),%a3,%acc1
+	mac.l %a1,%a3,#1,10(%a6),%a3,%acc2
+	mac.l %a1,%a3,#1,10(%a6),%d2,%acc1
+	mac.l %a1,%a3,#1,10(%a6),%d2,%acc2
+	mac.l %a1,%a3,#1,10(%a6),%a7,%acc1
+	mac.l %a1,%a3,#1,10(%a6),%a7,%acc2
+	mac.l %a1,%a3,#1,10(%a6)&,%d1,%acc1
+	mac.l %a1,%a3,#1,10(%a6)&,%d1,%acc2
+	mac.l %a1,%a3,#1,10(%a6)&,%a3,%acc1
+	mac.l %a1,%a3,#1,10(%a6)&,%a3,%acc2
+	mac.l %a1,%a3,#1,10(%a6)&,%d2,%acc1
+	mac.l %a1,%a3,#1,10(%a6)&,%d2,%acc2
+	mac.l %a1,%a3,#1,10(%a6)&,%a7,%acc1
+	mac.l %a1,%a3,#1,10(%a6)&,%a7,%acc2
+	mac.l %a1,%a3,#1,-(%a1),%d1,%acc1
+	mac.l %a1,%a3,#1,-(%a1),%d1,%acc2
+	mac.l %a1,%a3,#1,-(%a1),%a3,%acc1
+	mac.l %a1,%a3,#1,-(%a1),%a3,%acc2
+	mac.l %a1,%a3,#1,-(%a1),%d2,%acc1
+	mac.l %a1,%a3,#1,-(%a1),%d2,%acc2
+	mac.l %a1,%a3,#1,-(%a1),%a7,%acc1
+	mac.l %a1,%a3,#1,-(%a1),%a7,%acc2
+	mac.l %a1,%a3,#1,-(%a1)&,%d1,%acc1
+	mac.l %a1,%a3,#1,-(%a1)&,%d1,%acc2
+	mac.l %a1,%a3,#1,-(%a1)&,%a3,%acc1
+	mac.l %a1,%a3,#1,-(%a1)&,%a3,%acc2
+	mac.l %a1,%a3,#1,-(%a1)&,%d2,%acc1
+	mac.l %a1,%a3,#1,-(%a1)&,%d2,%acc2
+	mac.l %a1,%a3,#1,-(%a1)&,%a7,%acc1
+	mac.l %a1,%a3,#1,-(%a1)&,%a7,%acc2
+	mac.l %a1,%a3,#-1,(%a3),%d1,%acc1
+	mac.l %a1,%a3,#-1,(%a3),%d1,%acc2
+	mac.l %a1,%a3,#-1,(%a3),%a3,%acc1
+	mac.l %a1,%a3,#-1,(%a3),%a3,%acc2
+	mac.l %a1,%a3,#-1,(%a3),%d2,%acc1
+	mac.l %a1,%a3,#-1,(%a3),%d2,%acc2
+	mac.l %a1,%a3,#-1,(%a3),%a7,%acc1
+	mac.l %a1,%a3,#-1,(%a3),%a7,%acc2
+	mac.l %a1,%a3,#-1,(%a3)&,%d1,%acc1
+	mac.l %a1,%a3,#-1,(%a3)&,%d1,%acc2
+	mac.l %a1,%a3,#-1,(%a3)&,%a3,%acc1
+	mac.l %a1,%a3,#-1,(%a3)&,%a3,%acc2
+	mac.l %a1,%a3,#-1,(%a3)&,%d2,%acc1
+	mac.l %a1,%a3,#-1,(%a3)&,%d2,%acc2
+	mac.l %a1,%a3,#-1,(%a3)&,%a7,%acc1
+	mac.l %a1,%a3,#-1,(%a3)&,%a7,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+,%d1,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+,%d1,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+,%a3,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+,%a3,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+,%d2,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+,%d2,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+,%a7,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+,%a7,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+&,%d1,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+&,%d1,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+&,%a3,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+&,%a3,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+&,%d2,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+&,%d2,%acc2
+	mac.l %a1,%a3,#-1,(%a2)+&,%a7,%acc1
+	mac.l %a1,%a3,#-1,(%a2)+&,%a7,%acc2
+	mac.l %a1,%a3,#-1,10(%a6),%d1,%acc1
+	mac.l %a1,%a3,#-1,10(%a6),%d1,%acc2
+	mac.l %a1,%a3,#-1,10(%a6),%a3,%acc1
+	mac.l %a1,%a3,#-1,10(%a6),%a3,%acc2
+	mac.l %a1,%a3,#-1,10(%a6),%d2,%acc1
+	mac.l %a1,%a3,#-1,10(%a6),%d2,%acc2
+	mac.l %a1,%a3,#-1,10(%a6),%a7,%acc1
+	mac.l %a1,%a3,#-1,10(%a6),%a7,%acc2
+	mac.l %a1,%a3,#-1,10(%a6)&,%d1,%acc1
+	mac.l %a1,%a3,#-1,10(%a6)&,%d1,%acc2
+	mac.l %a1,%a3,#-1,10(%a6)&,%a3,%acc1
+	mac.l %a1,%a3,#-1,10(%a6)&,%a3,%acc2
+	mac.l %a1,%a3,#-1,10(%a6)&,%d2,%acc1
+	mac.l %a1,%a3,#-1,10(%a6)&,%d2,%acc2
+	mac.l %a1,%a3,#-1,10(%a6)&,%a7,%acc1
+	mac.l %a1,%a3,#-1,10(%a6)&,%a7,%acc2
+	mac.l %a1,%a3,#-1,-(%a1),%d1,%acc1
+	mac.l %a1,%a3,#-1,-(%a1),%d1,%acc2
+	mac.l %a1,%a3,#-1,-(%a1),%a3,%acc1
+	mac.l %a1,%a3,#-1,-(%a1),%a3,%acc2
+	mac.l %a1,%a3,#-1,-(%a1),%d2,%acc1
+	mac.l %a1,%a3,#-1,-(%a1),%d2,%acc2
+	mac.l %a1,%a3,#-1,-(%a1),%a7,%acc1
+	mac.l %a1,%a3,#-1,-(%a1),%a7,%acc2
+	mac.l %a1,%a3,#-1,-(%a1)&,%d1,%acc1
+	mac.l %a1,%a3,#-1,-(%a1)&,%d1,%acc2
+	mac.l %a1,%a3,#-1,-(%a1)&,%a3,%acc1
+	mac.l %a1,%a3,#-1,-(%a1)&,%a3,%acc2
+	mac.l %a1,%a3,#-1,-(%a1)&,%d2,%acc1
+	mac.l %a1,%a3,#-1,-(%a1)&,%d2,%acc2
+	mac.l %a1,%a3,#-1,-(%a1)&,%a7,%acc1
+	mac.l %a1,%a3,#-1,-(%a1)&,%a7,%acc2
+	mac.l %a1,%d4,(%a3),%d1,%acc1
+	mac.l %a1,%d4,(%a3),%d1,%acc2
+	mac.l %a1,%d4,(%a3),%a3,%acc1
+	mac.l %a1,%d4,(%a3),%a3,%acc2
+	mac.l %a1,%d4,(%a3),%d2,%acc1
+	mac.l %a1,%d4,(%a3),%d2,%acc2
+	mac.l %a1,%d4,(%a3),%a7,%acc1
+	mac.l %a1,%d4,(%a3),%a7,%acc2
+	mac.l %a1,%d4,(%a3)&,%d1,%acc1
+	mac.l %a1,%d4,(%a3)&,%d1,%acc2
+	mac.l %a1,%d4,(%a3)&,%a3,%acc1
+	mac.l %a1,%d4,(%a3)&,%a3,%acc2
+	mac.l %a1,%d4,(%a3)&,%d2,%acc1
+	mac.l %a1,%d4,(%a3)&,%d2,%acc2
+	mac.l %a1,%d4,(%a3)&,%a7,%acc1
+	mac.l %a1,%d4,(%a3)&,%a7,%acc2
+	mac.l %a1,%d4,(%a2)+,%d1,%acc1
+	mac.l %a1,%d4,(%a2)+,%d1,%acc2
+	mac.l %a1,%d4,(%a2)+,%a3,%acc1
+	mac.l %a1,%d4,(%a2)+,%a3,%acc2
+	mac.l %a1,%d4,(%a2)+,%d2,%acc1
+	mac.l %a1,%d4,(%a2)+,%d2,%acc2
+	mac.l %a1,%d4,(%a2)+,%a7,%acc1
+	mac.l %a1,%d4,(%a2)+,%a7,%acc2
+	mac.l %a1,%d4,(%a2)+&,%d1,%acc1
+	mac.l %a1,%d4,(%a2)+&,%d1,%acc2
+	mac.l %a1,%d4,(%a2)+&,%a3,%acc1
+	mac.l %a1,%d4,(%a2)+&,%a3,%acc2
+	mac.l %a1,%d4,(%a2)+&,%d2,%acc1
+	mac.l %a1,%d4,(%a2)+&,%d2,%acc2
+	mac.l %a1,%d4,(%a2)+&,%a7,%acc1
+	mac.l %a1,%d4,(%a2)+&,%a7,%acc2
+	mac.l %a1,%d4,10(%a6),%d1,%acc1
+	mac.l %a1,%d4,10(%a6),%d1,%acc2
+	mac.l %a1,%d4,10(%a6),%a3,%acc1
+	mac.l %a1,%d4,10(%a6),%a3,%acc2
+	mac.l %a1,%d4,10(%a6),%d2,%acc1
+	mac.l %a1,%d4,10(%a6),%d2,%acc2
+	mac.l %a1,%d4,10(%a6),%a7,%acc1
+	mac.l %a1,%d4,10(%a6),%a7,%acc2
+	mac.l %a1,%d4,10(%a6)&,%d1,%acc1
+	mac.l %a1,%d4,10(%a6)&,%d1,%acc2
+	mac.l %a1,%d4,10(%a6)&,%a3,%acc1
+	mac.l %a1,%d4,10(%a6)&,%a3,%acc2
+	mac.l %a1,%d4,10(%a6)&,%d2,%acc1
+	mac.l %a1,%d4,10(%a6)&,%d2,%acc2
+	mac.l %a1,%d4,10(%a6)&,%a7,%acc1
+	mac.l %a1,%d4,10(%a6)&,%a7,%acc2
+	mac.l %a1,%d4,-(%a1),%d1,%acc1
+	mac.l %a1,%d4,-(%a1),%d1,%acc2
+	mac.l %a1,%d4,-(%a1),%a3,%acc1
+	mac.l %a1,%d4,-(%a1),%a3,%acc2
+	mac.l %a1,%d4,-(%a1),%d2,%acc1
+	mac.l %a1,%d4,-(%a1),%d2,%acc2
+	mac.l %a1,%d4,-(%a1),%a7,%acc1
+	mac.l %a1,%d4,-(%a1),%a7,%acc2
+	mac.l %a1,%d4,-(%a1)&,%d1,%acc1
+	mac.l %a1,%d4,-(%a1)&,%d1,%acc2
+	mac.l %a1,%d4,-(%a1)&,%a3,%acc1
+	mac.l %a1,%d4,-(%a1)&,%a3,%acc2
+	mac.l %a1,%d4,-(%a1)&,%d2,%acc1
+	mac.l %a1,%d4,-(%a1)&,%d2,%acc2
+	mac.l %a1,%d4,-(%a1)&,%a7,%acc1
+	mac.l %a1,%d4,-(%a1)&,%a7,%acc2
+	mac.l %a1,%d4,<<,(%a3),%d1,%acc1
+	mac.l %a1,%d4,<<,(%a3),%d1,%acc2
+	mac.l %a1,%d4,<<,(%a3),%a3,%acc1
+	mac.l %a1,%d4,<<,(%a3),%a3,%acc2
+	mac.l %a1,%d4,<<,(%a3),%d2,%acc1
+	mac.l %a1,%d4,<<,(%a3),%d2,%acc2
+	mac.l %a1,%d4,<<,(%a3),%a7,%acc1
+	mac.l %a1,%d4,<<,(%a3),%a7,%acc2
+	mac.l %a1,%d4,<<,(%a3)&,%d1,%acc1
+	mac.l %a1,%d4,<<,(%a3)&,%d1,%acc2
+	mac.l %a1,%d4,<<,(%a3)&,%a3,%acc1
+	mac.l %a1,%d4,<<,(%a3)&,%a3,%acc2
+	mac.l %a1,%d4,<<,(%a3)&,%d2,%acc1
+	mac.l %a1,%d4,<<,(%a3)&,%d2,%acc2
+	mac.l %a1,%d4,<<,(%a3)&,%a7,%acc1
+	mac.l %a1,%d4,<<,(%a3)&,%a7,%acc2
+	mac.l %a1,%d4,<<,(%a2)+,%d1,%acc1
+	mac.l %a1,%d4,<<,(%a2)+,%d1,%acc2
+	mac.l %a1,%d4,<<,(%a2)+,%a3,%acc1
+	mac.l %a1,%d4,<<,(%a2)+,%a3,%acc2
+	mac.l %a1,%d4,<<,(%a2)+,%d2,%acc1
+	mac.l %a1,%d4,<<,(%a2)+,%d2,%acc2
+	mac.l %a1,%d4,<<,(%a2)+,%a7,%acc1
+	mac.l %a1,%d4,<<,(%a2)+,%a7,%acc2
+	mac.l %a1,%d4,<<,(%a2)+&,%d1,%acc1
+	mac.l %a1,%d4,<<,(%a2)+&,%d1,%acc2
+	mac.l %a1,%d4,<<,(%a2)+&,%a3,%acc1
+	mac.l %a1,%d4,<<,(%a2)+&,%a3,%acc2
+	mac.l %a1,%d4,<<,(%a2)+&,%d2,%acc1
+	mac.l %a1,%d4,<<,(%a2)+&,%d2,%acc2
+	mac.l %a1,%d4,<<,(%a2)+&,%a7,%acc1
+	mac.l %a1,%d4,<<,(%a2)+&,%a7,%acc2
+	mac.l %a1,%d4,<<,10(%a6),%d1,%acc1
+	mac.l %a1,%d4,<<,10(%a6),%d1,%acc2
+	mac.l %a1,%d4,<<,10(%a6),%a3,%acc1
+	mac.l %a1,%d4,<<,10(%a6),%a3,%acc2
+	mac.l %a1,%d4,<<,10(%a6),%d2,%acc1
+	mac.l %a1,%d4,<<,10(%a6),%d2,%acc2
+	mac.l %a1,%d4,<<,10(%a6),%a7,%acc1
+	mac.l %a1,%d4,<<,10(%a6),%a7,%acc2
+	mac.l %a1,%d4,<<,10(%a6)&,%d1,%acc1
+	mac.l %a1,%d4,<<,10(%a6)&,%d1,%acc2
+	mac.l %a1,%d4,<<,10(%a6)&,%a3,%acc1
+	mac.l %a1,%d4,<<,10(%a6)&,%a3,%acc2
+	mac.l %a1,%d4,<<,10(%a6)&,%d2,%acc1
+	mac.l %a1,%d4,<<,10(%a6)&,%d2,%acc2
+	mac.l %a1,%d4,<<,10(%a6)&,%a7,%acc1
+	mac.l %a1,%d4,<<,10(%a6)&,%a7,%acc2
+	mac.l %a1,%d4,<<,-(%a1),%d1,%acc1
+	mac.l %a1,%d4,<<,-(%a1),%d1,%acc2
+	mac.l %a1,%d4,<<,-(%a1),%a3,%acc1
+	mac.l %a1,%d4,<<,-(%a1),%a3,%acc2
+	mac.l %a1,%d4,<<,-(%a1),%d2,%acc1
+	mac.l %a1,%d4,<<,-(%a1),%d2,%acc2
+	mac.l %a1,%d4,<<,-(%a1),%a7,%acc1
+	mac.l %a1,%d4,<<,-(%a1),%a7,%acc2
+	mac.l %a1,%d4,<<,-(%a1)&,%d1,%acc1
+	mac.l %a1,%d4,<<,-(%a1)&,%d1,%acc2
+	mac.l %a1,%d4,<<,-(%a1)&,%a3,%acc1
+	mac.l %a1,%d4,<<,-(%a1)&,%a3,%acc2
+	mac.l %a1,%d4,<<,-(%a1)&,%d2,%acc1
+	mac.l %a1,%d4,<<,-(%a1)&,%d2,%acc2
+	mac.l %a1,%d4,<<,-(%a1)&,%a7,%acc1
+	mac.l %a1,%d4,<<,-(%a1)&,%a7,%acc2
+	mac.l %a1,%d4,>>,(%a3),%d1,%acc1
+	mac.l %a1,%d4,>>,(%a3),%d1,%acc2
+	mac.l %a1,%d4,>>,(%a3),%a3,%acc1
+	mac.l %a1,%d4,>>,(%a3),%a3,%acc2
+	mac.l %a1,%d4,>>,(%a3),%d2,%acc1
+	mac.l %a1,%d4,>>,(%a3),%d2,%acc2
+	mac.l %a1,%d4,>>,(%a3),%a7,%acc1
+	mac.l %a1,%d4,>>,(%a3),%a7,%acc2
+	mac.l %a1,%d4,>>,(%a3)&,%d1,%acc1
+	mac.l %a1,%d4,>>,(%a3)&,%d1,%acc2
+	mac.l %a1,%d4,>>,(%a3)&,%a3,%acc1
+	mac.l %a1,%d4,>>,(%a3)&,%a3,%acc2
+	mac.l %a1,%d4,>>,(%a3)&,%d2,%acc1
+	mac.l %a1,%d4,>>,(%a3)&,%d2,%acc2
+	mac.l %a1,%d4,>>,(%a3)&,%a7,%acc1
+	mac.l %a1,%d4,>>,(%a3)&,%a7,%acc2
+	mac.l %a1,%d4,>>,(%a2)+,%d1,%acc1
+	mac.l %a1,%d4,>>,(%a2)+,%d1,%acc2
+	mac.l %a1,%d4,>>,(%a2)+,%a3,%acc1
+	mac.l %a1,%d4,>>,(%a2)+,%a3,%acc2
+	mac.l %a1,%d4,>>,(%a2)+,%d2,%acc1
+	mac.l %a1,%d4,>>,(%a2)+,%d2,%acc2
+	mac.l %a1,%d4,>>,(%a2)+,%a7,%acc1
+	mac.l %a1,%d4,>>,(%a2)+,%a7,%acc2
+	mac.l %a1,%d4,>>,(%a2)+&,%d1,%acc1
+	mac.l %a1,%d4,>>,(%a2)+&,%d1,%acc2
+	mac.l %a1,%d4,>>,(%a2)+&,%a3,%acc1
+	mac.l %a1,%d4,>>,(%a2)+&,%a3,%acc2
+	mac.l %a1,%d4,>>,(%a2)+&,%d2,%acc1
+	mac.l %a1,%d4,>>,(%a2)+&,%d2,%acc2
+	mac.l %a1,%d4,>>,(%a2)+&,%a7,%acc1
+	mac.l %a1,%d4,>>,(%a2)+&,%a7,%acc2
+	mac.l %a1,%d4,>>,10(%a6),%d1,%acc1
+	mac.l %a1,%d4,>>,10(%a6),%d1,%acc2
+	mac.l %a1,%d4,>>,10(%a6),%a3,%acc1
+	mac.l %a1,%d4,>>,10(%a6),%a3,%acc2
+	mac.l %a1,%d4,>>,10(%a6),%d2,%acc1
+	mac.l %a1,%d4,>>,10(%a6),%d2,%acc2
+	mac.l %a1,%d4,>>,10(%a6),%a7,%acc1
+	mac.l %a1,%d4,>>,10(%a6),%a7,%acc2
+	mac.l %a1,%d4,>>,10(%a6)&,%d1,%acc1
+	mac.l %a1,%d4,>>,10(%a6)&,%d1,%acc2
+	mac.l %a1,%d4,>>,10(%a6)&,%a3,%acc1
+	mac.l %a1,%d4,>>,10(%a6)&,%a3,%acc2
+	mac.l %a1,%d4,>>,10(%a6)&,%d2,%acc1
+	mac.l %a1,%d4,>>,10(%a6)&,%d2,%acc2
+	mac.l %a1,%d4,>>,10(%a6)&,%a7,%acc1
+	mac.l %a1,%d4,>>,10(%a6)&,%a7,%acc2
+	mac.l %a1,%d4,>>,-(%a1),%d1,%acc1
+	mac.l %a1,%d4,>>,-(%a1),%d1,%acc2
+	mac.l %a1,%d4,>>,-(%a1),%a3,%acc1
+	mac.l %a1,%d4,>>,-(%a1),%a3,%acc2
+	mac.l %a1,%d4,>>,-(%a1),%d2,%acc1
+	mac.l %a1,%d4,>>,-(%a1),%d2,%acc2
+	mac.l %a1,%d4,>>,-(%a1),%a7,%acc1
+	mac.l %a1,%d4,>>,-(%a1),%a7,%acc2
+	mac.l %a1,%d4,>>,-(%a1)&,%d1,%acc1
+	mac.l %a1,%d4,>>,-(%a1)&,%d1,%acc2
+	mac.l %a1,%d4,>>,-(%a1)&,%a3,%acc1
+	mac.l %a1,%d4,>>,-(%a1)&,%a3,%acc2
+	mac.l %a1,%d4,>>,-(%a1)&,%d2,%acc1
+	mac.l %a1,%d4,>>,-(%a1)&,%d2,%acc2
+	mac.l %a1,%d4,>>,-(%a1)&,%a7,%acc1
+	mac.l %a1,%d4,>>,-(%a1)&,%a7,%acc2
+	mac.l %a1,%d4,#1,(%a3),%d1,%acc1
+	mac.l %a1,%d4,#1,(%a3),%d1,%acc2
+	mac.l %a1,%d4,#1,(%a3),%a3,%acc1
+	mac.l %a1,%d4,#1,(%a3),%a3,%acc2
+	mac.l %a1,%d4,#1,(%a3),%d2,%acc1
+	mac.l %a1,%d4,#1,(%a3),%d2,%acc2
+	mac.l %a1,%d4,#1,(%a3),%a7,%acc1
+	mac.l %a1,%d4,#1,(%a3),%a7,%acc2
+	mac.l %a1,%d4,#1,(%a3)&,%d1,%acc1
+	mac.l %a1,%d4,#1,(%a3)&,%d1,%acc2
+	mac.l %a1,%d4,#1,(%a3)&,%a3,%acc1
+	mac.l %a1,%d4,#1,(%a3)&,%a3,%acc2
+	mac.l %a1,%d4,#1,(%a3)&,%d2,%acc1
+	mac.l %a1,%d4,#1,(%a3)&,%d2,%acc2
+	mac.l %a1,%d4,#1,(%a3)&,%a7,%acc1
+	mac.l %a1,%d4,#1,(%a3)&,%a7,%acc2
+	mac.l %a1,%d4,#1,(%a2)+,%d1,%acc1
+	mac.l %a1,%d4,#1,(%a2)+,%d1,%acc2
+	mac.l %a1,%d4,#1,(%a2)+,%a3,%acc1
+	mac.l %a1,%d4,#1,(%a2)+,%a3,%acc2
+	mac.l %a1,%d4,#1,(%a2)+,%d2,%acc1
+	mac.l %a1,%d4,#1,(%a2)+,%d2,%acc2
+	mac.l %a1,%d4,#1,(%a2)+,%a7,%acc1
+	mac.l %a1,%d4,#1,(%a2)+,%a7,%acc2
+	mac.l %a1,%d4,#1,(%a2)+&,%d1,%acc1
+	mac.l %a1,%d4,#1,(%a2)+&,%d1,%acc2
+	mac.l %a1,%d4,#1,(%a2)+&,%a3,%acc1
+	mac.l %a1,%d4,#1,(%a2)+&,%a3,%acc2
+	mac.l %a1,%d4,#1,(%a2)+&,%d2,%acc1
+	mac.l %a1,%d4,#1,(%a2)+&,%d2,%acc2
+	mac.l %a1,%d4,#1,(%a2)+&,%a7,%acc1
+	mac.l %a1,%d4,#1,(%a2)+&,%a7,%acc2
+	mac.l %a1,%d4,#1,10(%a6),%d1,%acc1
+	mac.l %a1,%d4,#1,10(%a6),%d1,%acc2
+	mac.l %a1,%d4,#1,10(%a6),%a3,%acc1
+	mac.l %a1,%d4,#1,10(%a6),%a3,%acc2
+	mac.l %a1,%d4,#1,10(%a6),%d2,%acc1
+	mac.l %a1,%d4,#1,10(%a6),%d2,%acc2
+	mac.l %a1,%d4,#1,10(%a6),%a7,%acc1
+	mac.l %a1,%d4,#1,10(%a6),%a7,%acc2
+	mac.l %a1,%d4,#1,10(%a6)&,%d1,%acc1
+	mac.l %a1,%d4,#1,10(%a6)&,%d1,%acc2
+	mac.l %a1,%d4,#1,10(%a6)&,%a3,%acc1
+	mac.l %a1,%d4,#1,10(%a6)&,%a3,%acc2
+	mac.l %a1,%d4,#1,10(%a6)&,%d2,%acc1
+	mac.l %a1,%d4,#1,10(%a6)&,%d2,%acc2
+	mac.l %a1,%d4,#1,10(%a6)&,%a7,%acc1
+	mac.l %a1,%d4,#1,10(%a6)&,%a7,%acc2
+	mac.l %a1,%d4,#1,-(%a1),%d1,%acc1
+	mac.l %a1,%d4,#1,-(%a1),%d1,%acc2
+	mac.l %a1,%d4,#1,-(%a1),%a3,%acc1
+	mac.l %a1,%d4,#1,-(%a1),%a3,%acc2
+	mac.l %a1,%d4,#1,-(%a1),%d2,%acc1
+	mac.l %a1,%d4,#1,-(%a1),%d2,%acc2
+	mac.l %a1,%d4,#1,-(%a1),%a7,%acc1
+	mac.l %a1,%d4,#1,-(%a1),%a7,%acc2
+	mac.l %a1,%d4,#1,-(%a1)&,%d1,%acc1
+	mac.l %a1,%d4,#1,-(%a1)&,%d1,%acc2
+	mac.l %a1,%d4,#1,-(%a1)&,%a3,%acc1
+	mac.l %a1,%d4,#1,-(%a1)&,%a3,%acc2
+	mac.l %a1,%d4,#1,-(%a1)&,%d2,%acc1
+	mac.l %a1,%d4,#1,-(%a1)&,%d2,%acc2
+	mac.l %a1,%d4,#1,-(%a1)&,%a7,%acc1
+	mac.l %a1,%d4,#1,-(%a1)&,%a7,%acc2
+	mac.l %a1,%d4,#-1,(%a3),%d1,%acc1
+	mac.l %a1,%d4,#-1,(%a3),%d1,%acc2
+	mac.l %a1,%d4,#-1,(%a3),%a3,%acc1
+	mac.l %a1,%d4,#-1,(%a3),%a3,%acc2
+	mac.l %a1,%d4,#-1,(%a3),%d2,%acc1
+	mac.l %a1,%d4,#-1,(%a3),%d2,%acc2
+	mac.l %a1,%d4,#-1,(%a3),%a7,%acc1
+	mac.l %a1,%d4,#-1,(%a3),%a7,%acc2
+	mac.l %a1,%d4,#-1,(%a3)&,%d1,%acc1
+	mac.l %a1,%d4,#-1,(%a3)&,%d1,%acc2
+	mac.l %a1,%d4,#-1,(%a3)&,%a3,%acc1
+	mac.l %a1,%d4,#-1,(%a3)&,%a3,%acc2
+	mac.l %a1,%d4,#-1,(%a3)&,%d2,%acc1
+	mac.l %a1,%d4,#-1,(%a3)&,%d2,%acc2
+	mac.l %a1,%d4,#-1,(%a3)&,%a7,%acc1
+	mac.l %a1,%d4,#-1,(%a3)&,%a7,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+,%d1,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+,%d1,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+,%a3,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+,%a3,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+,%d2,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+,%d2,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+,%a7,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+,%a7,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+&,%d1,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+&,%d1,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+&,%a3,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+&,%a3,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+&,%d2,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+&,%d2,%acc2
+	mac.l %a1,%d4,#-1,(%a2)+&,%a7,%acc1
+	mac.l %a1,%d4,#-1,(%a2)+&,%a7,%acc2
+	mac.l %a1,%d4,#-1,10(%a6),%d1,%acc1
+	mac.l %a1,%d4,#-1,10(%a6),%d1,%acc2
+	mac.l %a1,%d4,#-1,10(%a6),%a3,%acc1
+	mac.l %a1,%d4,#-1,10(%a6),%a3,%acc2
+	mac.l %a1,%d4,#-1,10(%a6),%d2,%acc1
+	mac.l %a1,%d4,#-1,10(%a6),%d2,%acc2
+	mac.l %a1,%d4,#-1,10(%a6),%a7,%acc1
+	mac.l %a1,%d4,#-1,10(%a6),%a7,%acc2
+	mac.l %a1,%d4,#-1,10(%a6)&,%d1,%acc1
+	mac.l %a1,%d4,#-1,10(%a6)&,%d1,%acc2
+	mac.l %a1,%d4,#-1,10(%a6)&,%a3,%acc1
+	mac.l %a1,%d4,#-1,10(%a6)&,%a3,%acc2
+	mac.l %a1,%d4,#-1,10(%a6)&,%d2,%acc1
+	mac.l %a1,%d4,#-1,10(%a6)&,%d2,%acc2
+	mac.l %a1,%d4,#-1,10(%a6)&,%a7,%acc1
+	mac.l %a1,%d4,#-1,10(%a6)&,%a7,%acc2
+	mac.l %a1,%d4,#-1,-(%a1),%d1,%acc1
+	mac.l %a1,%d4,#-1,-(%a1),%d1,%acc2
+	mac.l %a1,%d4,#-1,-(%a1),%a3,%acc1
+	mac.l %a1,%d4,#-1,-(%a1),%a3,%acc2
+	mac.l %a1,%d4,#-1,-(%a1),%d2,%acc1
+	mac.l %a1,%d4,#-1,-(%a1),%d2,%acc2
+	mac.l %a1,%d4,#-1,-(%a1),%a7,%acc1
+	mac.l %a1,%d4,#-1,-(%a1),%a7,%acc2
+	mac.l %a1,%d4,#-1,-(%a1)&,%d1,%acc1
+	mac.l %a1,%d4,#-1,-(%a1)&,%d1,%acc2
+	mac.l %a1,%d4,#-1,-(%a1)&,%a3,%acc1
+	mac.l %a1,%d4,#-1,-(%a1)&,%a3,%acc2
+	mac.l %a1,%d4,#-1,-(%a1)&,%d2,%acc1
+	mac.l %a1,%d4,#-1,-(%a1)&,%d2,%acc2
+	mac.l %a1,%d4,#-1,-(%a1)&,%a7,%acc1
+	mac.l %a1,%d4,#-1,-(%a1)&,%a7,%acc2
+	mac.l %d6,%a3,(%a3),%d1,%acc1
+	mac.l %d6,%a3,(%a3),%d1,%acc2
+	mac.l %d6,%a3,(%a3),%a3,%acc1
+	mac.l %d6,%a3,(%a3),%a3,%acc2
+	mac.l %d6,%a3,(%a3),%d2,%acc1
+	mac.l %d6,%a3,(%a3),%d2,%acc2
+	mac.l %d6,%a3,(%a3),%a7,%acc1
+	mac.l %d6,%a3,(%a3),%a7,%acc2
+	mac.l %d6,%a3,(%a3)&,%d1,%acc1
+	mac.l %d6,%a3,(%a3)&,%d1,%acc2
+	mac.l %d6,%a3,(%a3)&,%a3,%acc1
+	mac.l %d6,%a3,(%a3)&,%a3,%acc2
+	mac.l %d6,%a3,(%a3)&,%d2,%acc1
+	mac.l %d6,%a3,(%a3)&,%d2,%acc2
+	mac.l %d6,%a3,(%a3)&,%a7,%acc1
+	mac.l %d6,%a3,(%a3)&,%a7,%acc2
+	mac.l %d6,%a3,(%a2)+,%d1,%acc1
+	mac.l %d6,%a3,(%a2)+,%d1,%acc2
+	mac.l %d6,%a3,(%a2)+,%a3,%acc1
+	mac.l %d6,%a3,(%a2)+,%a3,%acc2
+	mac.l %d6,%a3,(%a2)+,%d2,%acc1
+	mac.l %d6,%a3,(%a2)+,%d2,%acc2
+	mac.l %d6,%a3,(%a2)+,%a7,%acc1
+	mac.l %d6,%a3,(%a2)+,%a7,%acc2
+	mac.l %d6,%a3,(%a2)+&,%d1,%acc1
+	mac.l %d6,%a3,(%a2)+&,%d1,%acc2
+	mac.l %d6,%a3,(%a2)+&,%a3,%acc1
+	mac.l %d6,%a3,(%a2)+&,%a3,%acc2
+	mac.l %d6,%a3,(%a2)+&,%d2,%acc1
+	mac.l %d6,%a3,(%a2)+&,%d2,%acc2
+	mac.l %d6,%a3,(%a2)+&,%a7,%acc1
+	mac.l %d6,%a3,(%a2)+&,%a7,%acc2
+	mac.l %d6,%a3,10(%a6),%d1,%acc1
+	mac.l %d6,%a3,10(%a6),%d1,%acc2
+	mac.l %d6,%a3,10(%a6),%a3,%acc1
+	mac.l %d6,%a3,10(%a6),%a3,%acc2
+	mac.l %d6,%a3,10(%a6),%d2,%acc1
+	mac.l %d6,%a3,10(%a6),%d2,%acc2
+	mac.l %d6,%a3,10(%a6),%a7,%acc1
+	mac.l %d6,%a3,10(%a6),%a7,%acc2
+	mac.l %d6,%a3,10(%a6)&,%d1,%acc1
+	mac.l %d6,%a3,10(%a6)&,%d1,%acc2
+	mac.l %d6,%a3,10(%a6)&,%a3,%acc1
+	mac.l %d6,%a3,10(%a6)&,%a3,%acc2
+	mac.l %d6,%a3,10(%a6)&,%d2,%acc1
+	mac.l %d6,%a3,10(%a6)&,%d2,%acc2
+	mac.l %d6,%a3,10(%a6)&,%a7,%acc1
+	mac.l %d6,%a3,10(%a6)&,%a7,%acc2
+	mac.l %d6,%a3,-(%a1),%d1,%acc1
+	mac.l %d6,%a3,-(%a1),%d1,%acc2
+	mac.l %d6,%a3,-(%a1),%a3,%acc1
+	mac.l %d6,%a3,-(%a1),%a3,%acc2
+	mac.l %d6,%a3,-(%a1),%d2,%acc1
+	mac.l %d6,%a3,-(%a1),%d2,%acc2
+	mac.l %d6,%a3,-(%a1),%a7,%acc1
+	mac.l %d6,%a3,-(%a1),%a7,%acc2
+	mac.l %d6,%a3,-(%a1)&,%d1,%acc1
+	mac.l %d6,%a3,-(%a1)&,%d1,%acc2
+	mac.l %d6,%a3,-(%a1)&,%a3,%acc1
+	mac.l %d6,%a3,-(%a1)&,%a3,%acc2
+	mac.l %d6,%a3,-(%a1)&,%d2,%acc1
+	mac.l %d6,%a3,-(%a1)&,%d2,%acc2
+	mac.l %d6,%a3,-(%a1)&,%a7,%acc1
+	mac.l %d6,%a3,-(%a1)&,%a7,%acc2
+	mac.l %d6,%a3,<<,(%a3),%d1,%acc1
+	mac.l %d6,%a3,<<,(%a3),%d1,%acc2
+	mac.l %d6,%a3,<<,(%a3),%a3,%acc1
+	mac.l %d6,%a3,<<,(%a3),%a3,%acc2
+	mac.l %d6,%a3,<<,(%a3),%d2,%acc1
+	mac.l %d6,%a3,<<,(%a3),%d2,%acc2
+	mac.l %d6,%a3,<<,(%a3),%a7,%acc1
+	mac.l %d6,%a3,<<,(%a3),%a7,%acc2
+	mac.l %d6,%a3,<<,(%a3)&,%d1,%acc1
+	mac.l %d6,%a3,<<,(%a3)&,%d1,%acc2
+	mac.l %d6,%a3,<<,(%a3)&,%a3,%acc1
+	mac.l %d6,%a3,<<,(%a3)&,%a3,%acc2
+	mac.l %d6,%a3,<<,(%a3)&,%d2,%acc1
+	mac.l %d6,%a3,<<,(%a3)&,%d2,%acc2
+	mac.l %d6,%a3,<<,(%a3)&,%a7,%acc1
+	mac.l %d6,%a3,<<,(%a3)&,%a7,%acc2
+	mac.l %d6,%a3,<<,(%a2)+,%d1,%acc1
+	mac.l %d6,%a3,<<,(%a2)+,%d1,%acc2
+	mac.l %d6,%a3,<<,(%a2)+,%a3,%acc1
+	mac.l %d6,%a3,<<,(%a2)+,%a3,%acc2
+	mac.l %d6,%a3,<<,(%a2)+,%d2,%acc1
+	mac.l %d6,%a3,<<,(%a2)+,%d2,%acc2
+	mac.l %d6,%a3,<<,(%a2)+,%a7,%acc1
+	mac.l %d6,%a3,<<,(%a2)+,%a7,%acc2
+	mac.l %d6,%a3,<<,(%a2)+&,%d1,%acc1
+	mac.l %d6,%a3,<<,(%a2)+&,%d1,%acc2
+	mac.l %d6,%a3,<<,(%a2)+&,%a3,%acc1
+	mac.l %d6,%a3,<<,(%a2)+&,%a3,%acc2
+	mac.l %d6,%a3,<<,(%a2)+&,%d2,%acc1
+	mac.l %d6,%a3,<<,(%a2)+&,%d2,%acc2
+	mac.l %d6,%a3,<<,(%a2)+&,%a7,%acc1
+	mac.l %d6,%a3,<<,(%a2)+&,%a7,%acc2
+	mac.l %d6,%a3,<<,10(%a6),%d1,%acc1
+	mac.l %d6,%a3,<<,10(%a6),%d1,%acc2
+	mac.l %d6,%a3,<<,10(%a6),%a3,%acc1
+	mac.l %d6,%a3,<<,10(%a6),%a3,%acc2
+	mac.l %d6,%a3,<<,10(%a6),%d2,%acc1
+	mac.l %d6,%a3,<<,10(%a6),%d2,%acc2
+	mac.l %d6,%a3,<<,10(%a6),%a7,%acc1
+	mac.l %d6,%a3,<<,10(%a6),%a7,%acc2
+	mac.l %d6,%a3,<<,10(%a6)&,%d1,%acc1
+	mac.l %d6,%a3,<<,10(%a6)&,%d1,%acc2
+	mac.l %d6,%a3,<<,10(%a6)&,%a3,%acc1
+	mac.l %d6,%a3,<<,10(%a6)&,%a3,%acc2
+	mac.l %d6,%a3,<<,10(%a6)&,%d2,%acc1
+	mac.l %d6,%a3,<<,10(%a6)&,%d2,%acc2
+	mac.l %d6,%a3,<<,10(%a6)&,%a7,%acc1
+	mac.l %d6,%a3,<<,10(%a6)&,%a7,%acc2
+	mac.l %d6,%a3,<<,-(%a1),%d1,%acc1
+	mac.l %d6,%a3,<<,-(%a1),%d1,%acc2
+	mac.l %d6,%a3,<<,-(%a1),%a3,%acc1
+	mac.l %d6,%a3,<<,-(%a1),%a3,%acc2
+	mac.l %d6,%a3,<<,-(%a1),%d2,%acc1
+	mac.l %d6,%a3,<<,-(%a1),%d2,%acc2
+	mac.l %d6,%a3,<<,-(%a1),%a7,%acc1
+	mac.l %d6,%a3,<<,-(%a1),%a7,%acc2
+	mac.l %d6,%a3,<<,-(%a1)&,%d1,%acc1
+	mac.l %d6,%a3,<<,-(%a1)&,%d1,%acc2
+	mac.l %d6,%a3,<<,-(%a1)&,%a3,%acc1
+	mac.l %d6,%a3,<<,-(%a1)&,%a3,%acc2
+	mac.l %d6,%a3,<<,-(%a1)&,%d2,%acc1
+	mac.l %d6,%a3,<<,-(%a1)&,%d2,%acc2
+	mac.l %d6,%a3,<<,-(%a1)&,%a7,%acc1
+	mac.l %d6,%a3,<<,-(%a1)&,%a7,%acc2
+	mac.l %d6,%a3,>>,(%a3),%d1,%acc1
+	mac.l %d6,%a3,>>,(%a3),%d1,%acc2
+	mac.l %d6,%a3,>>,(%a3),%a3,%acc1
+	mac.l %d6,%a3,>>,(%a3),%a3,%acc2
+	mac.l %d6,%a3,>>,(%a3),%d2,%acc1
+	mac.l %d6,%a3,>>,(%a3),%d2,%acc2
+	mac.l %d6,%a3,>>,(%a3),%a7,%acc1
+	mac.l %d6,%a3,>>,(%a3),%a7,%acc2
+	mac.l %d6,%a3,>>,(%a3)&,%d1,%acc1
+	mac.l %d6,%a3,>>,(%a3)&,%d1,%acc2
+	mac.l %d6,%a3,>>,(%a3)&,%a3,%acc1
+	mac.l %d6,%a3,>>,(%a3)&,%a3,%acc2
+	mac.l %d6,%a3,>>,(%a3)&,%d2,%acc1
+	mac.l %d6,%a3,>>,(%a3)&,%d2,%acc2
+	mac.l %d6,%a3,>>,(%a3)&,%a7,%acc1
+	mac.l %d6,%a3,>>,(%a3)&,%a7,%acc2
+	mac.l %d6,%a3,>>,(%a2)+,%d1,%acc1
+	mac.l %d6,%a3,>>,(%a2)+,%d1,%acc2
+	mac.l %d6,%a3,>>,(%a2)+,%a3,%acc1
+	mac.l %d6,%a3,>>,(%a2)+,%a3,%acc2
+	mac.l %d6,%a3,>>,(%a2)+,%d2,%acc1
+	mac.l %d6,%a3,>>,(%a2)+,%d2,%acc2
+	mac.l %d6,%a3,>>,(%a2)+,%a7,%acc1
+	mac.l %d6,%a3,>>,(%a2)+,%a7,%acc2
+	mac.l %d6,%a3,>>,(%a2)+&,%d1,%acc1
+	mac.l %d6,%a3,>>,(%a2)+&,%d1,%acc2
+	mac.l %d6,%a3,>>,(%a2)+&,%a3,%acc1
+	mac.l %d6,%a3,>>,(%a2)+&,%a3,%acc2
+	mac.l %d6,%a3,>>,(%a2)+&,%d2,%acc1
+	mac.l %d6,%a3,>>,(%a2)+&,%d2,%acc2
+	mac.l %d6,%a3,>>,(%a2)+&,%a7,%acc1
+	mac.l %d6,%a3,>>,(%a2)+&,%a7,%acc2
+	mac.l %d6,%a3,>>,10(%a6),%d1,%acc1
+	mac.l %d6,%a3,>>,10(%a6),%d1,%acc2
+	mac.l %d6,%a3,>>,10(%a6),%a3,%acc1
+	mac.l %d6,%a3,>>,10(%a6),%a3,%acc2
+	mac.l %d6,%a3,>>,10(%a6),%d2,%acc1
+	mac.l %d6,%a3,>>,10(%a6),%d2,%acc2
+	mac.l %d6,%a3,>>,10(%a6),%a7,%acc1
+	mac.l %d6,%a3,>>,10(%a6),%a7,%acc2
+	mac.l %d6,%a3,>>,10(%a6)&,%d1,%acc1
+	mac.l %d6,%a3,>>,10(%a6)&,%d1,%acc2
+	mac.l %d6,%a3,>>,10(%a6)&,%a3,%acc1
+	mac.l %d6,%a3,>>,10(%a6)&,%a3,%acc2
+	mac.l %d6,%a3,>>,10(%a6)&,%d2,%acc1
+	mac.l %d6,%a3,>>,10(%a6)&,%d2,%acc2
+	mac.l %d6,%a3,>>,10(%a6)&,%a7,%acc1
+	mac.l %d6,%a3,>>,10(%a6)&,%a7,%acc2
+	mac.l %d6,%a3,>>,-(%a1),%d1,%acc1
+	mac.l %d6,%a3,>>,-(%a1),%d1,%acc2
+	mac.l %d6,%a3,>>,-(%a1),%a3,%acc1
+	mac.l %d6,%a3,>>,-(%a1),%a3,%acc2
+	mac.l %d6,%a3,>>,-(%a1),%d2,%acc1
+	mac.l %d6,%a3,>>,-(%a1),%d2,%acc2
+	mac.l %d6,%a3,>>,-(%a1),%a7,%acc1
+	mac.l %d6,%a3,>>,-(%a1),%a7,%acc2
+	mac.l %d6,%a3,>>,-(%a1)&,%d1,%acc1
+	mac.l %d6,%a3,>>,-(%a1)&,%d1,%acc2
+	mac.l %d6,%a3,>>,-(%a1)&,%a3,%acc1
+	mac.l %d6,%a3,>>,-(%a1)&,%a3,%acc2
+	mac.l %d6,%a3,>>,-(%a1)&,%d2,%acc1
+	mac.l %d6,%a3,>>,-(%a1)&,%d2,%acc2
+	mac.l %d6,%a3,>>,-(%a1)&,%a7,%acc1
+	mac.l %d6,%a3,>>,-(%a1)&,%a7,%acc2
+	mac.l %d6,%a3,#1,(%a3),%d1,%acc1
+	mac.l %d6,%a3,#1,(%a3),%d1,%acc2
+	mac.l %d6,%a3,#1,(%a3),%a3,%acc1
+	mac.l %d6,%a3,#1,(%a3),%a3,%acc2
+	mac.l %d6,%a3,#1,(%a3),%d2,%acc1
+	mac.l %d6,%a3,#1,(%a3),%d2,%acc2
+	mac.l %d6,%a3,#1,(%a3),%a7,%acc1
+	mac.l %d6,%a3,#1,(%a3),%a7,%acc2
+	mac.l %d6,%a3,#1,(%a3)&,%d1,%acc1
+	mac.l %d6,%a3,#1,(%a3)&,%d1,%acc2
+	mac.l %d6,%a3,#1,(%a3)&,%a3,%acc1
+	mac.l %d6,%a3,#1,(%a3)&,%a3,%acc2
+	mac.l %d6,%a3,#1,(%a3)&,%d2,%acc1
+	mac.l %d6,%a3,#1,(%a3)&,%d2,%acc2
+	mac.l %d6,%a3,#1,(%a3)&,%a7,%acc1
+	mac.l %d6,%a3,#1,(%a3)&,%a7,%acc2
+	mac.l %d6,%a3,#1,(%a2)+,%d1,%acc1
+	mac.l %d6,%a3,#1,(%a2)+,%d1,%acc2
+	mac.l %d6,%a3,#1,(%a2)+,%a3,%acc1
+	mac.l %d6,%a3,#1,(%a2)+,%a3,%acc2
+	mac.l %d6,%a3,#1,(%a2)+,%d2,%acc1
+	mac.l %d6,%a3,#1,(%a2)+,%d2,%acc2
+	mac.l %d6,%a3,#1,(%a2)+,%a7,%acc1
+	mac.l %d6,%a3,#1,(%a2)+,%a7,%acc2
+	mac.l %d6,%a3,#1,(%a2)+&,%d1,%acc1
+	mac.l %d6,%a3,#1,(%a2)+&,%d1,%acc2
+	mac.l %d6,%a3,#1,(%a2)+&,%a3,%acc1
+	mac.l %d6,%a3,#1,(%a2)+&,%a3,%acc2
+	mac.l %d6,%a3,#1,(%a2)+&,%d2,%acc1
+	mac.l %d6,%a3,#1,(%a2)+&,%d2,%acc2
+	mac.l %d6,%a3,#1,(%a2)+&,%a7,%acc1
+	mac.l %d6,%a3,#1,(%a2)+&,%a7,%acc2
+	mac.l %d6,%a3,#1,10(%a6),%d1,%acc1
+	mac.l %d6,%a3,#1,10(%a6),%d1,%acc2
+	mac.l %d6,%a3,#1,10(%a6),%a3,%acc1
+	mac.l %d6,%a3,#1,10(%a6),%a3,%acc2
+	mac.l %d6,%a3,#1,10(%a6),%d2,%acc1
+	mac.l %d6,%a3,#1,10(%a6),%d2,%acc2
+	mac.l %d6,%a3,#1,10(%a6),%a7,%acc1
+	mac.l %d6,%a3,#1,10(%a6),%a7,%acc2
+	mac.l %d6,%a3,#1,10(%a6)&,%d1,%acc1
+	mac.l %d6,%a3,#1,10(%a6)&,%d1,%acc2
+	mac.l %d6,%a3,#1,10(%a6)&,%a3,%acc1
+	mac.l %d6,%a3,#1,10(%a6)&,%a3,%acc2
+	mac.l %d6,%a3,#1,10(%a6)&,%d2,%acc1
+	mac.l %d6,%a3,#1,10(%a6)&,%d2,%acc2
+	mac.l %d6,%a3,#1,10(%a6)&,%a7,%acc1
+	mac.l %d6,%a3,#1,10(%a6)&,%a7,%acc2
+	mac.l %d6,%a3,#1,-(%a1),%d1,%acc1
+	mac.l %d6,%a3,#1,-(%a1),%d1,%acc2
+	mac.l %d6,%a3,#1,-(%a1),%a3,%acc1
+	mac.l %d6,%a3,#1,-(%a1),%a3,%acc2
+	mac.l %d6,%a3,#1,-(%a1),%d2,%acc1
+	mac.l %d6,%a3,#1,-(%a1),%d2,%acc2
+	mac.l %d6,%a3,#1,-(%a1),%a7,%acc1
+	mac.l %d6,%a3,#1,-(%a1),%a7,%acc2
+	mac.l %d6,%a3,#1,-(%a1)&,%d1,%acc1
+	mac.l %d6,%a3,#1,-(%a1)&,%d1,%acc2
+	mac.l %d6,%a3,#1,-(%a1)&,%a3,%acc1
+	mac.l %d6,%a3,#1,-(%a1)&,%a3,%acc2
+	mac.l %d6,%a3,#1,-(%a1)&,%d2,%acc1
+	mac.l %d6,%a3,#1,-(%a1)&,%d2,%acc2
+	mac.l %d6,%a3,#1,-(%a1)&,%a7,%acc1
+	mac.l %d6,%a3,#1,-(%a1)&,%a7,%acc2
+	mac.l %d6,%a3,#-1,(%a3),%d1,%acc1
+	mac.l %d6,%a3,#-1,(%a3),%d1,%acc2
+	mac.l %d6,%a3,#-1,(%a3),%a3,%acc1
+	mac.l %d6,%a3,#-1,(%a3),%a3,%acc2
+	mac.l %d6,%a3,#-1,(%a3),%d2,%acc1
+	mac.l %d6,%a3,#-1,(%a3),%d2,%acc2
+	mac.l %d6,%a3,#-1,(%a3),%a7,%acc1
+	mac.l %d6,%a3,#-1,(%a3),%a7,%acc2
+	mac.l %d6,%a3,#-1,(%a3)&,%d1,%acc1
+	mac.l %d6,%a3,#-1,(%a3)&,%d1,%acc2
+	mac.l %d6,%a3,#-1,(%a3)&,%a3,%acc1
+	mac.l %d6,%a3,#-1,(%a3)&,%a3,%acc2
+	mac.l %d6,%a3,#-1,(%a3)&,%d2,%acc1
+	mac.l %d6,%a3,#-1,(%a3)&,%d2,%acc2
+	mac.l %d6,%a3,#-1,(%a3)&,%a7,%acc1
+	mac.l %d6,%a3,#-1,(%a3)&,%a7,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+,%d1,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+,%d1,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+,%a3,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+,%a3,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+,%d2,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+,%d2,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+,%a7,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+,%a7,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+&,%d1,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+&,%d1,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+&,%a3,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+&,%a3,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+&,%d2,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+&,%d2,%acc2
+	mac.l %d6,%a3,#-1,(%a2)+&,%a7,%acc1
+	mac.l %d6,%a3,#-1,(%a2)+&,%a7,%acc2
+	mac.l %d6,%a3,#-1,10(%a6),%d1,%acc1
+	mac.l %d6,%a3,#-1,10(%a6),%d1,%acc2
+	mac.l %d6,%a3,#-1,10(%a6),%a3,%acc1
+	mac.l %d6,%a3,#-1,10(%a6),%a3,%acc2
+	mac.l %d6,%a3,#-1,10(%a6),%d2,%acc1
+	mac.l %d6,%a3,#-1,10(%a6),%d2,%acc2
+	mac.l %d6,%a3,#-1,10(%a6),%a7,%acc1
+	mac.l %d6,%a3,#-1,10(%a6),%a7,%acc2
+	mac.l %d6,%a3,#-1,10(%a6)&,%d1,%acc1
+	mac.l %d6,%a3,#-1,10(%a6)&,%d1,%acc2
+	mac.l %d6,%a3,#-1,10(%a6)&,%a3,%acc1
+	mac.l %d6,%a3,#-1,10(%a6)&,%a3,%acc2
+	mac.l %d6,%a3,#-1,10(%a6)&,%d2,%acc1
+	mac.l %d6,%a3,#-1,10(%a6)&,%d2,%acc2
+	mac.l %d6,%a3,#-1,10(%a6)&,%a7,%acc1
+	mac.l %d6,%a3,#-1,10(%a6)&,%a7,%acc2
+	mac.l %d6,%a3,#-1,-(%a1),%d1,%acc1
+	mac.l %d6,%a3,#-1,-(%a1),%d1,%acc2
+	mac.l %d6,%a3,#-1,-(%a1),%a3,%acc1
+	mac.l %d6,%a3,#-1,-(%a1),%a3,%acc2
+	mac.l %d6,%a3,#-1,-(%a1),%d2,%acc1
+	mac.l %d6,%a3,#-1,-(%a1),%d2,%acc2
+	mac.l %d6,%a3,#-1,-(%a1),%a7,%acc1
+	mac.l %d6,%a3,#-1,-(%a1),%a7,%acc2
+	mac.l %d6,%a3,#-1,-(%a1)&,%d1,%acc1
+	mac.l %d6,%a3,#-1,-(%a1)&,%d1,%acc2
+	mac.l %d6,%a3,#-1,-(%a1)&,%a3,%acc1
+	mac.l %d6,%a3,#-1,-(%a1)&,%a3,%acc2
+	mac.l %d6,%a3,#-1,-(%a1)&,%d2,%acc1
+	mac.l %d6,%a3,#-1,-(%a1)&,%d2,%acc2
+	mac.l %d6,%a3,#-1,-(%a1)&,%a7,%acc1
+	mac.l %d6,%a3,#-1,-(%a1)&,%a7,%acc2
+	mac.l %d6,%d4,(%a3),%d1,%acc1
+	mac.l %d6,%d4,(%a3),%d1,%acc2
+	mac.l %d6,%d4,(%a3),%a3,%acc1
+	mac.l %d6,%d4,(%a3),%a3,%acc2
+	mac.l %d6,%d4,(%a3),%d2,%acc1
+	mac.l %d6,%d4,(%a3),%d2,%acc2
+	mac.l %d6,%d4,(%a3),%a7,%acc1
+	mac.l %d6,%d4,(%a3),%a7,%acc2
+	mac.l %d6,%d4,(%a3)&,%d1,%acc1
+	mac.l %d6,%d4,(%a3)&,%d1,%acc2
+	mac.l %d6,%d4,(%a3)&,%a3,%acc1
+	mac.l %d6,%d4,(%a3)&,%a3,%acc2
+	mac.l %d6,%d4,(%a3)&,%d2,%acc1
+	mac.l %d6,%d4,(%a3)&,%d2,%acc2
+	mac.l %d6,%d4,(%a3)&,%a7,%acc1
+	mac.l %d6,%d4,(%a3)&,%a7,%acc2
+	mac.l %d6,%d4,(%a2)+,%d1,%acc1
+	mac.l %d6,%d4,(%a2)+,%d1,%acc2
+	mac.l %d6,%d4,(%a2)+,%a3,%acc1
+	mac.l %d6,%d4,(%a2)+,%a3,%acc2
+	mac.l %d6,%d4,(%a2)+,%d2,%acc1
+	mac.l %d6,%d4,(%a2)+,%d2,%acc2
+	mac.l %d6,%d4,(%a2)+,%a7,%acc1
+	mac.l %d6,%d4,(%a2)+,%a7,%acc2
+	mac.l %d6,%d4,(%a2)+&,%d1,%acc1
+	mac.l %d6,%d4,(%a2)+&,%d1,%acc2
+	mac.l %d6,%d4,(%a2)+&,%a3,%acc1
+	mac.l %d6,%d4,(%a2)+&,%a3,%acc2
+	mac.l %d6,%d4,(%a2)+&,%d2,%acc1
+	mac.l %d6,%d4,(%a2)+&,%d2,%acc2
+	mac.l %d6,%d4,(%a2)+&,%a7,%acc1
+	mac.l %d6,%d4,(%a2)+&,%a7,%acc2
+	mac.l %d6,%d4,10(%a6),%d1,%acc1
+	mac.l %d6,%d4,10(%a6),%d1,%acc2
+	mac.l %d6,%d4,10(%a6),%a3,%acc1
+	mac.l %d6,%d4,10(%a6),%a3,%acc2
+	mac.l %d6,%d4,10(%a6),%d2,%acc1
+	mac.l %d6,%d4,10(%a6),%d2,%acc2
+	mac.l %d6,%d4,10(%a6),%a7,%acc1
+	mac.l %d6,%d4,10(%a6),%a7,%acc2
+	mac.l %d6,%d4,10(%a6)&,%d1,%acc1
+	mac.l %d6,%d4,10(%a6)&,%d1,%acc2
+	mac.l %d6,%d4,10(%a6)&,%a3,%acc1
+	mac.l %d6,%d4,10(%a6)&,%a3,%acc2
+	mac.l %d6,%d4,10(%a6)&,%d2,%acc1
+	mac.l %d6,%d4,10(%a6)&,%d2,%acc2
+	mac.l %d6,%d4,10(%a6)&,%a7,%acc1
+	mac.l %d6,%d4,10(%a6)&,%a7,%acc2
+	mac.l %d6,%d4,-(%a1),%d1,%acc1
+	mac.l %d6,%d4,-(%a1),%d1,%acc2
+	mac.l %d6,%d4,-(%a1),%a3,%acc1
+	mac.l %d6,%d4,-(%a1),%a3,%acc2
+	mac.l %d6,%d4,-(%a1),%d2,%acc1
+	mac.l %d6,%d4,-(%a1),%d2,%acc2
+	mac.l %d6,%d4,-(%a1),%a7,%acc1
+	mac.l %d6,%d4,-(%a1),%a7,%acc2
+	mac.l %d6,%d4,-(%a1)&,%d1,%acc1
+	mac.l %d6,%d4,-(%a1)&,%d1,%acc2
+	mac.l %d6,%d4,-(%a1)&,%a3,%acc1
+	mac.l %d6,%d4,-(%a1)&,%a3,%acc2
+	mac.l %d6,%d4,-(%a1)&,%d2,%acc1
+	mac.l %d6,%d4,-(%a1)&,%d2,%acc2
+	mac.l %d6,%d4,-(%a1)&,%a7,%acc1
+	mac.l %d6,%d4,-(%a1)&,%a7,%acc2
+	mac.l %d6,%d4,<<,(%a3),%d1,%acc1
+	mac.l %d6,%d4,<<,(%a3),%d1,%acc2
+	mac.l %d6,%d4,<<,(%a3),%a3,%acc1
+	mac.l %d6,%d4,<<,(%a3),%a3,%acc2
+	mac.l %d6,%d4,<<,(%a3),%d2,%acc1
+	mac.l %d6,%d4,<<,(%a3),%d2,%acc2
+	mac.l %d6,%d4,<<,(%a3),%a7,%acc1
+	mac.l %d6,%d4,<<,(%a3),%a7,%acc2
+	mac.l %d6,%d4,<<,(%a3)&,%d1,%acc1
+	mac.l %d6,%d4,<<,(%a3)&,%d1,%acc2
+	mac.l %d6,%d4,<<,(%a3)&,%a3,%acc1
+	mac.l %d6,%d4,<<,(%a3)&,%a3,%acc2
+	mac.l %d6,%d4,<<,(%a3)&,%d2,%acc1
+	mac.l %d6,%d4,<<,(%a3)&,%d2,%acc2
+	mac.l %d6,%d4,<<,(%a3)&,%a7,%acc1
+	mac.l %d6,%d4,<<,(%a3)&,%a7,%acc2
+	mac.l %d6,%d4,<<,(%a2)+,%d1,%acc1
+	mac.l %d6,%d4,<<,(%a2)+,%d1,%acc2
+	mac.l %d6,%d4,<<,(%a2)+,%a3,%acc1
+	mac.l %d6,%d4,<<,(%a2)+,%a3,%acc2
+	mac.l %d6,%d4,<<,(%a2)+,%d2,%acc1
+	mac.l %d6,%d4,<<,(%a2)+,%d2,%acc2
+	mac.l %d6,%d4,<<,(%a2)+,%a7,%acc1
+	mac.l %d6,%d4,<<,(%a2)+,%a7,%acc2
+	mac.l %d6,%d4,<<,(%a2)+&,%d1,%acc1
+	mac.l %d6,%d4,<<,(%a2)+&,%d1,%acc2
+	mac.l %d6,%d4,<<,(%a2)+&,%a3,%acc1
+	mac.l %d6,%d4,<<,(%a2)+&,%a3,%acc2
+	mac.l %d6,%d4,<<,(%a2)+&,%d2,%acc1
+	mac.l %d6,%d4,<<,(%a2)+&,%d2,%acc2
+	mac.l %d6,%d4,<<,(%a2)+&,%a7,%acc1
+	mac.l %d6,%d4,<<,(%a2)+&,%a7,%acc2
+	mac.l %d6,%d4,<<,10(%a6),%d1,%acc1
+	mac.l %d6,%d4,<<,10(%a6),%d1,%acc2
+	mac.l %d6,%d4,<<,10(%a6),%a3,%acc1
+	mac.l %d6,%d4,<<,10(%a6),%a3,%acc2
+	mac.l %d6,%d4,<<,10(%a6),%d2,%acc1
+	mac.l %d6,%d4,<<,10(%a6),%d2,%acc2
+	mac.l %d6,%d4,<<,10(%a6),%a7,%acc1
+	mac.l %d6,%d4,<<,10(%a6),%a7,%acc2
+	mac.l %d6,%d4,<<,10(%a6)&,%d1,%acc1
+	mac.l %d6,%d4,<<,10(%a6)&,%d1,%acc2
+	mac.l %d6,%d4,<<,10(%a6)&,%a3,%acc1
+	mac.l %d6,%d4,<<,10(%a6)&,%a3,%acc2
+	mac.l %d6,%d4,<<,10(%a6)&,%d2,%acc1
+	mac.l %d6,%d4,<<,10(%a6)&,%d2,%acc2
+	mac.l %d6,%d4,<<,10(%a6)&,%a7,%acc1
+	mac.l %d6,%d4,<<,10(%a6)&,%a7,%acc2
+	mac.l %d6,%d4,<<,-(%a1),%d1,%acc1
+	mac.l %d6,%d4,<<,-(%a1),%d1,%acc2
+	mac.l %d6,%d4,<<,-(%a1),%a3,%acc1
+	mac.l %d6,%d4,<<,-(%a1),%a3,%acc2
+	mac.l %d6,%d4,<<,-(%a1),%d2,%acc1
+	mac.l %d6,%d4,<<,-(%a1),%d2,%acc2
+	mac.l %d6,%d4,<<,-(%a1),%a7,%acc1
+	mac.l %d6,%d4,<<,-(%a1),%a7,%acc2
+	mac.l %d6,%d4,<<,-(%a1)&,%d1,%acc1
+	mac.l %d6,%d4,<<,-(%a1)&,%d1,%acc2
+	mac.l %d6,%d4,<<,-(%a1)&,%a3,%acc1
+	mac.l %d6,%d4,<<,-(%a1)&,%a3,%acc2
+	mac.l %d6,%d4,<<,-(%a1)&,%d2,%acc1
+	mac.l %d6,%d4,<<,-(%a1)&,%d2,%acc2
+	mac.l %d6,%d4,<<,-(%a1)&,%a7,%acc1
+	mac.l %d6,%d4,<<,-(%a1)&,%a7,%acc2
+	mac.l %d6,%d4,>>,(%a3),%d1,%acc1
+	mac.l %d6,%d4,>>,(%a3),%d1,%acc2
+	mac.l %d6,%d4,>>,(%a3),%a3,%acc1
+	mac.l %d6,%d4,>>,(%a3),%a3,%acc2
+	mac.l %d6,%d4,>>,(%a3),%d2,%acc1
+	mac.l %d6,%d4,>>,(%a3),%d2,%acc2
+	mac.l %d6,%d4,>>,(%a3),%a7,%acc1
+	mac.l %d6,%d4,>>,(%a3),%a7,%acc2
+	mac.l %d6,%d4,>>,(%a3)&,%d1,%acc1
+	mac.l %d6,%d4,>>,(%a3)&,%d1,%acc2
+	mac.l %d6,%d4,>>,(%a3)&,%a3,%acc1
+	mac.l %d6,%d4,>>,(%a3)&,%a3,%acc2
+	mac.l %d6,%d4,>>,(%a3)&,%d2,%acc1
+	mac.l %d6,%d4,>>,(%a3)&,%d2,%acc2
+	mac.l %d6,%d4,>>,(%a3)&,%a7,%acc1
+	mac.l %d6,%d4,>>,(%a3)&,%a7,%acc2
+	mac.l %d6,%d4,>>,(%a2)+,%d1,%acc1
+	mac.l %d6,%d4,>>,(%a2)+,%d1,%acc2
+	mac.l %d6,%d4,>>,(%a2)+,%a3,%acc1
+	mac.l %d6,%d4,>>,(%a2)+,%a3,%acc2
+	mac.l %d6,%d4,>>,(%a2)+,%d2,%acc1
+	mac.l %d6,%d4,>>,(%a2)+,%d2,%acc2
+	mac.l %d6,%d4,>>,(%a2)+,%a7,%acc1
+	mac.l %d6,%d4,>>,(%a2)+,%a7,%acc2
+	mac.l %d6,%d4,>>,(%a2)+&,%d1,%acc1
+	mac.l %d6,%d4,>>,(%a2)+&,%d1,%acc2
+	mac.l %d6,%d4,>>,(%a2)+&,%a3,%acc1
+	mac.l %d6,%d4,>>,(%a2)+&,%a3,%acc2
+	mac.l %d6,%d4,>>,(%a2)+&,%d2,%acc1
+	mac.l %d6,%d4,>>,(%a2)+&,%d2,%acc2
+	mac.l %d6,%d4,>>,(%a2)+&,%a7,%acc1
+	mac.l %d6,%d4,>>,(%a2)+&,%a7,%acc2
+	mac.l %d6,%d4,>>,10(%a6),%d1,%acc1
+	mac.l %d6,%d4,>>,10(%a6),%d1,%acc2
+	mac.l %d6,%d4,>>,10(%a6),%a3,%acc1
+	mac.l %d6,%d4,>>,10(%a6),%a3,%acc2
+	mac.l %d6,%d4,>>,10(%a6),%d2,%acc1
+	mac.l %d6,%d4,>>,10(%a6),%d2,%acc2
+	mac.l %d6,%d4,>>,10(%a6),%a7,%acc1
+	mac.l %d6,%d4,>>,10(%a6),%a7,%acc2
+	mac.l %d6,%d4,>>,10(%a6)&,%d1,%acc1
+	mac.l %d6,%d4,>>,10(%a6)&,%d1,%acc2
+	mac.l %d6,%d4,>>,10(%a6)&,%a3,%acc1
+	mac.l %d6,%d4,>>,10(%a6)&,%a3,%acc2
+	mac.l %d6,%d4,>>,10(%a6)&,%d2,%acc1
+	mac.l %d6,%d4,>>,10(%a6)&,%d2,%acc2
+	mac.l %d6,%d4,>>,10(%a6)&,%a7,%acc1
+	mac.l %d6,%d4,>>,10(%a6)&,%a7,%acc2
+	mac.l %d6,%d4,>>,-(%a1),%d1,%acc1
+	mac.l %d6,%d4,>>,-(%a1),%d1,%acc2
+	mac.l %d6,%d4,>>,-(%a1),%a3,%acc1
+	mac.l %d6,%d4,>>,-(%a1),%a3,%acc2
+	mac.l %d6,%d4,>>,-(%a1),%d2,%acc1
+	mac.l %d6,%d4,>>,-(%a1),%d2,%acc2
+	mac.l %d6,%d4,>>,-(%a1),%a7,%acc1
+	mac.l %d6,%d4,>>,-(%a1),%a7,%acc2
+	mac.l %d6,%d4,>>,-(%a1)&,%d1,%acc1
+	mac.l %d6,%d4,>>,-(%a1)&,%d1,%acc2
+	mac.l %d6,%d4,>>,-(%a1)&,%a3,%acc1
+	mac.l %d6,%d4,>>,-(%a1)&,%a3,%acc2
+	mac.l %d6,%d4,>>,-(%a1)&,%d2,%acc1
+	mac.l %d6,%d4,>>,-(%a1)&,%d2,%acc2
+	mac.l %d6,%d4,>>,-(%a1)&,%a7,%acc1
+	mac.l %d6,%d4,>>,-(%a1)&,%a7,%acc2
+	mac.l %d6,%d4,#1,(%a3),%d1,%acc1
+	mac.l %d6,%d4,#1,(%a3),%d1,%acc2
+	mac.l %d6,%d4,#1,(%a3),%a3,%acc1
+	mac.l %d6,%d4,#1,(%a3),%a3,%acc2
+	mac.l %d6,%d4,#1,(%a3),%d2,%acc1
+	mac.l %d6,%d4,#1,(%a3),%d2,%acc2
+	mac.l %d6,%d4,#1,(%a3),%a7,%acc1
+	mac.l %d6,%d4,#1,(%a3),%a7,%acc2
+	mac.l %d6,%d4,#1,(%a3)&,%d1,%acc1
+	mac.l %d6,%d4,#1,(%a3)&,%d1,%acc2
+	mac.l %d6,%d4,#1,(%a3)&,%a3,%acc1
+	mac.l %d6,%d4,#1,(%a3)&,%a3,%acc2
+	mac.l %d6,%d4,#1,(%a3)&,%d2,%acc1
+	mac.l %d6,%d4,#1,(%a3)&,%d2,%acc2
+	mac.l %d6,%d4,#1,(%a3)&,%a7,%acc1
+	mac.l %d6,%d4,#1,(%a3)&,%a7,%acc2
+	mac.l %d6,%d4,#1,(%a2)+,%d1,%acc1
+	mac.l %d6,%d4,#1,(%a2)+,%d1,%acc2
+	mac.l %d6,%d4,#1,(%a2)+,%a3,%acc1
+	mac.l %d6,%d4,#1,(%a2)+,%a3,%acc2
+	mac.l %d6,%d4,#1,(%a2)+,%d2,%acc1
+	mac.l %d6,%d4,#1,(%a2)+,%d2,%acc2
+	mac.l %d6,%d4,#1,(%a2)+,%a7,%acc1
+	mac.l %d6,%d4,#1,(%a2)+,%a7,%acc2
+	mac.l %d6,%d4,#1,(%a2)+&,%d1,%acc1
+	mac.l %d6,%d4,#1,(%a2)+&,%d1,%acc2
+	mac.l %d6,%d4,#1,(%a2)+&,%a3,%acc1
+	mac.l %d6,%d4,#1,(%a2)+&,%a3,%acc2
+	mac.l %d6,%d4,#1,(%a2)+&,%d2,%acc1
+	mac.l %d6,%d4,#1,(%a2)+&,%d2,%acc2
+	mac.l %d6,%d4,#1,(%a2)+&,%a7,%acc1
+	mac.l %d6,%d4,#1,(%a2)+&,%a7,%acc2
+	mac.l %d6,%d4,#1,10(%a6),%d1,%acc1
+	mac.l %d6,%d4,#1,10(%a6),%d1,%acc2
+	mac.l %d6,%d4,#1,10(%a6),%a3,%acc1
+	mac.l %d6,%d4,#1,10(%a6),%a3,%acc2
+	mac.l %d6,%d4,#1,10(%a6),%d2,%acc1
+	mac.l %d6,%d4,#1,10(%a6),%d2,%acc2
+	mac.l %d6,%d4,#1,10(%a6),%a7,%acc1
+	mac.l %d6,%d4,#1,10(%a6),%a7,%acc2
+	mac.l %d6,%d4,#1,10(%a6)&,%d1,%acc1
+	mac.l %d6,%d4,#1,10(%a6)&,%d1,%acc2
+	mac.l %d6,%d4,#1,10(%a6)&,%a3,%acc1
+	mac.l %d6,%d4,#1,10(%a6)&,%a3,%acc2
+	mac.l %d6,%d4,#1,10(%a6)&,%d2,%acc1
+	mac.l %d6,%d4,#1,10(%a6)&,%d2,%acc2
+	mac.l %d6,%d4,#1,10(%a6)&,%a7,%acc1
+	mac.l %d6,%d4,#1,10(%a6)&,%a7,%acc2
+	mac.l %d6,%d4,#1,-(%a1),%d1,%acc1
+	mac.l %d6,%d4,#1,-(%a1),%d1,%acc2
+	mac.l %d6,%d4,#1,-(%a1),%a3,%acc1
+	mac.l %d6,%d4,#1,-(%a1),%a3,%acc2
+	mac.l %d6,%d4,#1,-(%a1),%d2,%acc1
+	mac.l %d6,%d4,#1,-(%a1),%d2,%acc2
+	mac.l %d6,%d4,#1,-(%a1),%a7,%acc1
+	mac.l %d6,%d4,#1,-(%a1),%a7,%acc2
+	mac.l %d6,%d4,#1,-(%a1)&,%d1,%acc1
+	mac.l %d6,%d4,#1,-(%a1)&,%d1,%acc2
+	mac.l %d6,%d4,#1,-(%a1)&,%a3,%acc1
+	mac.l %d6,%d4,#1,-(%a1)&,%a3,%acc2
+	mac.l %d6,%d4,#1,-(%a1)&,%d2,%acc1
+	mac.l %d6,%d4,#1,-(%a1)&,%d2,%acc2
+	mac.l %d6,%d4,#1,-(%a1)&,%a7,%acc1
+	mac.l %d6,%d4,#1,-(%a1)&,%a7,%acc2
+	mac.l %d6,%d4,#-1,(%a3),%d1,%acc1
+	mac.l %d6,%d4,#-1,(%a3),%d1,%acc2
+	mac.l %d6,%d4,#-1,(%a3),%a3,%acc1
+	mac.l %d6,%d4,#-1,(%a3),%a3,%acc2
+	mac.l %d6,%d4,#-1,(%a3),%d2,%acc1
+	mac.l %d6,%d4,#-1,(%a3),%d2,%acc2
+	mac.l %d6,%d4,#-1,(%a3),%a7,%acc1
+	mac.l %d6,%d4,#-1,(%a3),%a7,%acc2
+	mac.l %d6,%d4,#-1,(%a3)&,%d1,%acc1
+	mac.l %d6,%d4,#-1,(%a3)&,%d1,%acc2
+	mac.l %d6,%d4,#-1,(%a3)&,%a3,%acc1
+	mac.l %d6,%d4,#-1,(%a3)&,%a3,%acc2
+	mac.l %d6,%d4,#-1,(%a3)&,%d2,%acc1
+	mac.l %d6,%d4,#-1,(%a3)&,%d2,%acc2
+	mac.l %d6,%d4,#-1,(%a3)&,%a7,%acc1
+	mac.l %d6,%d4,#-1,(%a3)&,%a7,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+,%d1,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+,%d1,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+,%a3,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+,%a3,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+,%d2,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+,%d2,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+,%a7,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+,%a7,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+&,%d1,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+&,%d1,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+&,%a3,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+&,%a3,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+&,%d2,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+&,%d2,%acc2
+	mac.l %d6,%d4,#-1,(%a2)+&,%a7,%acc1
+	mac.l %d6,%d4,#-1,(%a2)+&,%a7,%acc2
+	mac.l %d6,%d4,#-1,10(%a6),%d1,%acc1
+	mac.l %d6,%d4,#-1,10(%a6),%d1,%acc2
+	mac.l %d6,%d4,#-1,10(%a6),%a3,%acc1
+	mac.l %d6,%d4,#-1,10(%a6),%a3,%acc2
+	mac.l %d6,%d4,#-1,10(%a6),%d2,%acc1
+	mac.l %d6,%d4,#-1,10(%a6),%d2,%acc2
+	mac.l %d6,%d4,#-1,10(%a6),%a7,%acc1
+	mac.l %d6,%d4,#-1,10(%a6),%a7,%acc2
+	mac.l %d6,%d4,#-1,10(%a6)&,%d1,%acc1
+	mac.l %d6,%d4,#-1,10(%a6)&,%d1,%acc2
+	mac.l %d6,%d4,#-1,10(%a6)&,%a3,%acc1
+	mac.l %d6,%d4,#-1,10(%a6)&,%a3,%acc2
+	mac.l %d6,%d4,#-1,10(%a6)&,%d2,%acc1
+	mac.l %d6,%d4,#-1,10(%a6)&,%d2,%acc2
+	mac.l %d6,%d4,#-1,10(%a6)&,%a7,%acc1
+	mac.l %d6,%d4,#-1,10(%a6)&,%a7,%acc2
+	mac.l %d6,%d4,#-1,-(%a1),%d1,%acc1
+	mac.l %d6,%d4,#-1,-(%a1),%d1,%acc2
+	mac.l %d6,%d4,#-1,-(%a1),%a3,%acc1
+	mac.l %d6,%d4,#-1,-(%a1),%a3,%acc2
+	mac.l %d6,%d4,#-1,-(%a1),%d2,%acc1
+	mac.l %d6,%d4,#-1,-(%a1),%d2,%acc2
+	mac.l %d6,%d4,#-1,-(%a1),%a7,%acc1
+	mac.l %d6,%d4,#-1,-(%a1),%a7,%acc2
+	mac.l %d6,%d4,#-1,-(%a1)&,%d1,%acc1
+	mac.l %d6,%d4,#-1,-(%a1)&,%d1,%acc2
+	mac.l %d6,%d4,#-1,-(%a1)&,%a3,%acc1
+	mac.l %d6,%d4,#-1,-(%a1)&,%a3,%acc2
+	mac.l %d6,%d4,#-1,-(%a1)&,%d2,%acc1
+	mac.l %d6,%d4,#-1,-(%a1)&,%d2,%acc2
+	mac.l %d6,%d4,#-1,-(%a1)&,%a7,%acc1
+	mac.l %d6,%d4,#-1,-(%a1)&,%a7,%acc2
diff --git a/gas/testsuite/gas/m68k/mcf-fpu.d b/gas/testsuite/gas/m68k/mcf-fpu.d
new file mode 100644
index 000000000000..5167b08dff0d
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-fpu.d
@@ -0,0 +1,178 @@
+#objdump: -d --architecture=m68k:cfv4e
+#as: -mcfv4e
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 0-9a-f]+:	f200 0004      	fsqrtd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4004 0008 	fsqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4404 0008 	fsqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5004 0008 	fsqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5404 0008 	fsqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5804 0008 	fsqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0041      	fssqrtd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4041 0008 	fssqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4441 0008 	fssqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5041 0008 	fssqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5441 0008 	fssqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5841 0008 	fssqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0045      	fdsqrtd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4045 0008 	fdsqrtl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4445 0008 	fdsqrts %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5045 0008 	fdsqrtw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5445 0008 	fdsqrtd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5845 0008 	fdsqrtb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0018      	fabsd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4018 0008 	fabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4418 0008 	fabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5018 0008 	fabsw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5418 0008 	fabsd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5818 0008 	fabsb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0058      	fsabsd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4058 0008 	fsabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4458 0008 	fsabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5058 0008 	fsabsw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5458 0008 	fsabsd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5858 0008 	fsabsb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 005c      	fdabsd %fp0,%fp0
+[ 0-9a-f]+:	f22e 405c 0008 	fdabsl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 445c 0008 	fdabss %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 505c 0008 	fdabsw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 545c 0008 	fdabsd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 585c 0008 	fdabsb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 001a      	fnegd %fp0,%fp0
+[ 0-9a-f]+:	f22e 401a 0008 	fnegl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 441a 0008 	fnegs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 501a 0008 	fnegw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 541a 0008 	fnegd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 581a 0008 	fnegb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 005a      	fsnegd %fp0,%fp0
+[ 0-9a-f]+:	f22e 405a 0008 	fsnegl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 445a 0008 	fsnegs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 505a 0008 	fsnegw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 545a 0008 	fsnegd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 585a 0008 	fsnegb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 005e      	fdnegd %fp0,%fp0
+[ 0-9a-f]+:	f22e 405e 0008 	fdnegl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 445e 0008 	fdnegs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 505e 0008 	fdnegw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 545e 0008 	fdnegd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 585e 0008 	fdnegb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0020      	fdivd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4020 0008 	fdivl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4420 0008 	fdivs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5020 0008 	fdivw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5420 0008 	fdivd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5820 0008 	fdivb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0060      	fsdivd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4060 0008 	fsdivl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4460 0008 	fsdivs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5060 0008 	fsdivw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5460 0008 	fsdivd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5860 0008 	fsdivb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0064      	fddivd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4064 0008 	fddivl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4464 0008 	fddivs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5064 0008 	fddivw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5464 0008 	fddivd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5864 0008 	fddivb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0022      	faddd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4022 0008 	faddl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4422 0008 	fadds %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5022 0008 	faddw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5422 0008 	faddd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5822 0008 	faddb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0062      	fsaddd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4062 0008 	fsaddl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4462 0008 	fsadds %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5062 0008 	fsaddw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5462 0008 	fsaddd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5862 0008 	fsaddb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0066      	fdaddd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4066 0008 	fdaddl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4466 0008 	fdadds %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5066 0008 	fdaddw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5466 0008 	fdaddd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5866 0008 	fdaddb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0023      	fmuld %fp0,%fp0
+[ 0-9a-f]+:	f22e 4023 0008 	fmull %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4423 0008 	fmuls %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5023 0008 	fmulw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5423 0008 	fmuld %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5823 0008 	fmulb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0063      	fsmuld %fp0,%fp0
+[ 0-9a-f]+:	f22e 4063 0008 	fsmull %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4463 0008 	fsmuls %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5063 0008 	fsmulw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5463 0008 	fsmuld %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5863 0008 	fsmulb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0067      	fdmuld %fp0,%fp0
+[ 0-9a-f]+:	f22e 4067 0008 	fdmull %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4467 0008 	fdmuls %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5067 0008 	fdmulw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5467 0008 	fdmuld %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5867 0008 	fdmulb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0028      	fsubd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4028 0008 	fsubl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4428 0008 	fsubs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5028 0008 	fsubw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5428 0008 	fsubd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5828 0008 	fsubb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0068      	fssubd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4068 0008 	fssubl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4468 0008 	fssubs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5068 0008 	fssubw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5468 0008 	fssubd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5868 0008 	fssubb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 006c      	fdsubd %fp0,%fp0
+[ 0-9a-f]+:	f22e 406c 0008 	fdsubl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 446c 0008 	fdsubs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 506c 0008 	fdsubw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 546c 0008 	fdsubd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 586c 0008 	fdsubb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0000      	fmoved %fp0,%fp0
+[ 0-9a-f]+:	f22e 4000 0008 	fmovel %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4400 0008 	fmoves %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5000 0008 	fmovew %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5400 0008 	fmoved %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5800 0008 	fmoveb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0040      	fsmoved %fp0,%fp0
+[ 0-9a-f]+:	f22e 4040 0008 	fsmovel %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4440 0008 	fsmoves %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5040 0008 	fsmovew %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5440 0008 	fsmoved %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5840 0008 	fsmoveb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0044      	fdmoved %fp0,%fp0
+[ 0-9a-f]+:	f22e 4044 0008 	fdmovel %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4444 0008 	fdmoves %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5044 0008 	fdmovew %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5444 0008 	fdmoved %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5844 0008 	fdmoveb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0001      	fintd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4001 0008 	fintl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4401 0008 	fints %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5001 0008 	fintw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5401 0008 	fintd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5801 0008 	fintb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0003      	fintrzd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4003 0008 	fintrzl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4403 0008 	fintrzs %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5003 0008 	fintrzw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5403 0008 	fintrzd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5803 0008 	fintrzb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f200 0038      	fcmpd %fp0,%fp0
+[ 0-9a-f]+:	f22e 4038 0008 	fcmpl %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 4438 0008 	fcmps %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5038 0008 	fcmpw %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5438 0008 	fcmpd %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e 5838 0008 	fcmpb %fp@\(8\),%fp0
+[ 0-9a-f]+:	f22e f0f2 0008 	fmovemd %fp0-%fp3/%fp6,%fp@\(8\)
+[ 0-9a-f]+:	f22e d02c 0008 	fmovemd %fp@\(8\),%fp2/%fp4-%fp5
+[ 0-9a-f]+:	f22e f027 0008 	fmovemd %fp2/%fp5-%fp7,%fp@\(8\)
+[ 0-9a-f]+:	f22e d0e1 0008 	fmovemd %fp@\(8\),%fp0-%fp2/%fp7
+[ 0-9a-f]+:	f22e f0f2 0008 	fmovemd %fp0-%fp3/%fp6,%fp@\(8\)
+[ 0-9a-f]+:	f22e d02c 0008 	fmovemd %fp@\(8\),%fp2/%fp4-%fp5
+[ 0-9a-f]+:	f22e f027 0008 	fmovemd %fp2/%fp5-%fp7,%fp@\(8\)
+[ 0-9a-f]+:	f22e d0e1 0008 	fmovemd %fp@\(8\),%fp0-%fp2/%fp7
diff --git a/gas/testsuite/gas/m68k/mcf-fpu.s b/gas/testsuite/gas/m68k/mcf-fpu.s
new file mode 100644
index 000000000000..99231a74e31f
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-fpu.s
@@ -0,0 +1,173 @@
+
+	.text
+
+	fsqrtd	%fp0,%fp0
+	fsqrtl	%fp@(8),%fp0
+	fsqrts	%fp@(8),%fp0
+	fsqrtw	%fp@(8),%fp0
+	fsqrtd	%fp@(8),%fp0
+	fsqrtb	%fp@(8),%fp0
+	fssqrtd	%fp0,%fp0
+	fssqrtl	%fp@(8),%fp0
+	fssqrts	%fp@(8),%fp0
+	fssqrtw	%fp@(8),%fp0
+	fssqrtd	%fp@(8),%fp0
+	fssqrtb	%fp@(8),%fp0
+	fdsqrtd	%fp0,%fp0
+	fdsqrtl	%fp@(8),%fp0
+	fdsqrts	%fp@(8),%fp0
+	fdsqrtw	%fp@(8),%fp0
+	fdsqrtd	%fp@(8),%fp0
+	fdsqrtb	%fp@(8),%fp0
+	fabsd	%fp0,%fp0
+	fabsl	%fp@(8),%fp0
+	fabss	%fp@(8),%fp0
+	fabsw	%fp@(8),%fp0
+	fabsd	%fp@(8),%fp0
+	fabsb	%fp@(8),%fp0
+	fsabsd	%fp0,%fp0
+	fsabsl	%fp@(8),%fp0
+	fsabss	%fp@(8),%fp0
+	fsabsw	%fp@(8),%fp0
+	fsabsd	%fp@(8),%fp0
+	fsabsb	%fp@(8),%fp0
+	fdabsd	%fp0,%fp0
+	fdabsl	%fp@(8),%fp0
+	fdabss	%fp@(8),%fp0
+	fdabsw	%fp@(8),%fp0
+	fdabsd	%fp@(8),%fp0
+	fdabsb	%fp@(8),%fp0
+	fnegd	%fp0,%fp0
+	fnegl	%fp@(8),%fp0
+	fnegs	%fp@(8),%fp0
+	fnegw	%fp@(8),%fp0
+	fnegd	%fp@(8),%fp0
+	fnegb	%fp@(8),%fp0
+	fsnegd	%fp0,%fp0
+	fsnegl	%fp@(8),%fp0
+	fsnegs	%fp@(8),%fp0
+	fsnegw	%fp@(8),%fp0
+	fsnegd	%fp@(8),%fp0
+	fsnegb	%fp@(8),%fp0
+	fdnegd	%fp0,%fp0
+	fdnegl	%fp@(8),%fp0
+	fdnegs	%fp@(8),%fp0
+	fdnegw	%fp@(8),%fp0
+	fdnegd	%fp@(8),%fp0
+	fdnegb	%fp@(8),%fp0
+	fdivd	%fp0,%fp0
+	fdivl	%fp@(8),%fp0
+	fdivs	%fp@(8),%fp0
+	fdivw	%fp@(8),%fp0
+	fdivd	%fp@(8),%fp0
+	fdivb	%fp@(8),%fp0
+	fsdivd	%fp0,%fp0
+	fsdivl	%fp@(8),%fp0
+	fsdivs	%fp@(8),%fp0
+	fsdivw	%fp@(8),%fp0
+	fsdivd	%fp@(8),%fp0
+	fsdivb	%fp@(8),%fp0
+	fddivd	%fp0,%fp0
+	fddivl	%fp@(8),%fp0
+	fddivs	%fp@(8),%fp0
+	fddivw	%fp@(8),%fp0
+	fddivd	%fp@(8),%fp0
+	fddivb	%fp@(8),%fp0
+	faddd	%fp0,%fp0
+	faddl	%fp@(8),%fp0
+	fadds	%fp@(8),%fp0
+	faddw	%fp@(8),%fp0
+	faddd	%fp@(8),%fp0
+	faddb	%fp@(8),%fp0
+	fsaddd	%fp0,%fp0
+	fsaddl	%fp@(8),%fp0
+	fsadds	%fp@(8),%fp0
+	fsaddw	%fp@(8),%fp0
+	fsaddd	%fp@(8),%fp0
+	fsaddb	%fp@(8),%fp0
+	fdaddd	%fp0,%fp0
+	fdaddl	%fp@(8),%fp0
+	fdadds	%fp@(8),%fp0
+	fdaddw	%fp@(8),%fp0
+	fdaddd	%fp@(8),%fp0
+	fdaddb	%fp@(8),%fp0
+	fmuld	%fp0,%fp0
+	fmull	%fp@(8),%fp0
+	fmuls	%fp@(8),%fp0
+	fmulw	%fp@(8),%fp0
+	fmuld	%fp@(8),%fp0
+	fmulb	%fp@(8),%fp0
+	fsmuld	%fp0,%fp0
+	fsmull	%fp@(8),%fp0
+	fsmuls	%fp@(8),%fp0
+	fsmulw	%fp@(8),%fp0
+	fsmuld	%fp@(8),%fp0
+	fsmulb	%fp@(8),%fp0
+	fdmuld	%fp0,%fp0
+	fdmull	%fp@(8),%fp0
+	fdmuls	%fp@(8),%fp0
+	fdmulw	%fp@(8),%fp0
+	fdmuld	%fp@(8),%fp0
+	fdmulb	%fp@(8),%fp0
+	fsubd	%fp0,%fp0
+	fsubl	%fp@(8),%fp0
+	fsubs	%fp@(8),%fp0
+	fsubw	%fp@(8),%fp0
+	fsubd	%fp@(8),%fp0
+	fsubb	%fp@(8),%fp0
+	fssubd	%fp0,%fp0
+	fssubl	%fp@(8),%fp0
+	fssubs	%fp@(8),%fp0
+	fssubw	%fp@(8),%fp0
+	fssubd	%fp@(8),%fp0
+	fssubb	%fp@(8),%fp0
+	fdsubd	%fp0,%fp0
+	fdsubl	%fp@(8),%fp0
+	fdsubs	%fp@(8),%fp0
+	fdsubw	%fp@(8),%fp0
+	fdsubd	%fp@(8),%fp0
+	fdsubb	%fp@(8),%fp0
+	fmoved	%fp0,%fp0
+	fmovel	%fp@(8),%fp0
+	fmoves	%fp@(8),%fp0
+	fmovew	%fp@(8),%fp0
+	fmoved	%fp@(8),%fp0
+	fmoveb	%fp@(8),%fp0
+	fsmoved	%fp0,%fp0
+	fsmovel	%fp@(8),%fp0
+	fsmoves	%fp@(8),%fp0
+	fsmovew	%fp@(8),%fp0
+	fsmoved	%fp@(8),%fp0
+	fsmoveb	%fp@(8),%fp0
+	fdmoved	%fp0,%fp0
+	fdmovel	%fp@(8),%fp0
+	fdmoves	%fp@(8),%fp0
+	fdmovew	%fp@(8),%fp0
+	fdmoved	%fp@(8),%fp0
+	fdmoveb	%fp@(8),%fp0
+	fintd	%fp0,%fp0
+	fintl	%fp@(8),%fp0
+	fints	%fp@(8),%fp0
+	fintw	%fp@(8),%fp0
+	fintd	%fp@(8),%fp0
+	fintb	%fp@(8),%fp0
+	fintrzd	%fp0,%fp0
+	fintrzl	%fp@(8),%fp0
+	fintrzs	%fp@(8),%fp0
+	fintrzw	%fp@(8),%fp0
+	fintrzd	%fp@(8),%fp0
+	fintrzb	%fp@(8),%fp0
+	fcmpd	%fp0,%fp0
+	fcmpl	%fp@(8),%fp0
+	fcmps	%fp@(8),%fp0
+	fcmpw	%fp@(8),%fp0
+	fcmpd	%fp@(8),%fp0
+	fcmpb	%fp@(8),%fp0
+	fmovemd	%fp0-%fp3/%fp6,%fp@(8)
+	fmovemd	%fp@(8),%fp5/%fp4/%fp2
+	fmovemd	#0x27,%fp@(8)
+	fmovemd	%fp@(8),#0xe1
+	fmovem	%fp0-%fp3/%fp6,%fp@(8)
+	fmovem	%fp@(8),%fp5/%fp4/%fp2
+	fmovem	#0x27,%fp@(8)
+	fmovem	%fp@(8),#0xe1
diff --git a/gas/testsuite/gas/m68k/mcf-mac.d b/gas/testsuite/gas/m68k/mcf-mac.d
new file mode 100644
index 000000000000..10dd7749ee2f
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-mac.d
@@ -0,0 +1,3325 @@
+#name: mcf-mac
+#objdump: -d --architecture=m68k:5407
+#as: -m5407
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+       0:	a182           	movel %acc,%d2
+       2:	a189           	movel %acc,%a1
+       4:	a989           	movel %macsr,%a1
+       6:	a982           	movel %macsr,%d2
+       8:	ad89           	movel %mask,%a1
+       a:	ad82           	movel %mask,%d2
+       c:	a9c0           	movel %macsr,%ccr
+       e:	a13c 1234 5678 	movel #305419896,%acc
+      14:	a101           	movel %d1,%acc
+      16:	a10a           	movel %a2,%acc
+      18:	a93c 1234 5678 	movel #305419896,%macsr
+      1e:	a901           	movel %d1,%macsr
+      20:	a90a           	movel %a2,%macsr
+      22:	ad3c 1234 5678 	movel #305419896,%mask
+      28:	ad01           	movel %d1,%mask
+      2a:	ad0a           	movel %a2,%mask
+      2c:	a449 0080      	macw %a1l,%a2u
+      30:	a449 0280      	macw %a1l,%a2u,<<
+      34:	a449 0680      	macw %a1l,%a2u,>>
+      38:	a449 0280      	macw %a1l,%a2u,<<
+      3c:	a449 0680      	macw %a1l,%a2u,>>
+      40:	a609 0000      	macw %a1l,%d3l
+      44:	a609 0200      	macw %a1l,%d3l,<<
+      48:	a609 0600      	macw %a1l,%d3l,>>
+      4c:	a609 0200      	macw %a1l,%d3l,<<
+      50:	a609 0600      	macw %a1l,%d3l,>>
+      54:	ae49 0080      	macw %a1l,%a7u
+      58:	ae49 0280      	macw %a1l,%a7u,<<
+      5c:	ae49 0680      	macw %a1l,%a7u,>>
+      60:	ae49 0280      	macw %a1l,%a7u,<<
+      64:	ae49 0680      	macw %a1l,%a7u,>>
+      68:	a209 0000      	macw %a1l,%d1l
+      6c:	a209 0200      	macw %a1l,%d1l,<<
+      70:	a209 0600      	macw %a1l,%d1l,>>
+      74:	a209 0200      	macw %a1l,%d1l,<<
+      78:	a209 0600      	macw %a1l,%d1l,>>
+      7c:	a442 00c0      	macw %d2u,%a2u
+      80:	a442 02c0      	macw %d2u,%a2u,<<
+      84:	a442 06c0      	macw %d2u,%a2u,>>
+      88:	a442 02c0      	macw %d2u,%a2u,<<
+      8c:	a442 06c0      	macw %d2u,%a2u,>>
+      90:	a602 0040      	macw %d2u,%d3l
+      94:	a602 0240      	macw %d2u,%d3l,<<
+      98:	a602 0640      	macw %d2u,%d3l,>>
+      9c:	a602 0240      	macw %d2u,%d3l,<<
+      a0:	a602 0640      	macw %d2u,%d3l,>>
+      a4:	ae42 00c0      	macw %d2u,%a7u
+      a8:	ae42 02c0      	macw %d2u,%a7u,<<
+      ac:	ae42 06c0      	macw %d2u,%a7u,>>
+      b0:	ae42 02c0      	macw %d2u,%a7u,<<
+      b4:	ae42 06c0      	macw %d2u,%a7u,>>
+      b8:	a202 0040      	macw %d2u,%d1l
+      bc:	a202 0240      	macw %d2u,%d1l,<<
+      c0:	a202 0640      	macw %d2u,%d1l,>>
+      c4:	a202 0240      	macw %d2u,%d1l,<<
+      c8:	a202 0640      	macw %d2u,%d1l,>>
+      cc:	a44d 0080      	macw %a5l,%a2u
+      d0:	a44d 0280      	macw %a5l,%a2u,<<
+      d4:	a44d 0680      	macw %a5l,%a2u,>>
+      d8:	a44d 0280      	macw %a5l,%a2u,<<
+      dc:	a44d 0680      	macw %a5l,%a2u,>>
+      e0:	a60d 0000      	macw %a5l,%d3l
+      e4:	a60d 0200      	macw %a5l,%d3l,<<
+      e8:	a60d 0600      	macw %a5l,%d3l,>>
+      ec:	a60d 0200      	macw %a5l,%d3l,<<
+      f0:	a60d 0600      	macw %a5l,%d3l,>>
+      f4:	ae4d 0080      	macw %a5l,%a7u
+      f8:	ae4d 0280      	macw %a5l,%a7u,<<
+      fc:	ae4d 0680      	macw %a5l,%a7u,>>
+     100:	ae4d 0280      	macw %a5l,%a7u,<<
+     104:	ae4d 0680      	macw %a5l,%a7u,>>
+     108:	a20d 0000      	macw %a5l,%d1l
+     10c:	a20d 0200      	macw %a5l,%d1l,<<
+     110:	a20d 0600      	macw %a5l,%d1l,>>
+     114:	a20d 0200      	macw %a5l,%d1l,<<
+     118:	a20d 0600      	macw %a5l,%d1l,>>
+     11c:	a446 00c0      	macw %d6u,%a2u
+     120:	a446 02c0      	macw %d6u,%a2u,<<
+     124:	a446 06c0      	macw %d6u,%a2u,>>
+     128:	a446 02c0      	macw %d6u,%a2u,<<
+     12c:	a446 06c0      	macw %d6u,%a2u,>>
+     130:	a606 0040      	macw %d6u,%d3l
+     134:	a606 0240      	macw %d6u,%d3l,<<
+     138:	a606 0640      	macw %d6u,%d3l,>>
+     13c:	a606 0240      	macw %d6u,%d3l,<<
+     140:	a606 0640      	macw %d6u,%d3l,>>
+     144:	ae46 00c0      	macw %d6u,%a7u
+     148:	ae46 02c0      	macw %d6u,%a7u,<<
+     14c:	ae46 06c0      	macw %d6u,%a7u,>>
+     150:	ae46 02c0      	macw %d6u,%a7u,<<
+     154:	ae46 06c0      	macw %d6u,%a7u,>>
+     158:	a206 0040      	macw %d6u,%d1l
+     15c:	a206 0240      	macw %d6u,%d1l,<<
+     160:	a206 0640      	macw %d6u,%d1l,>>
+     164:	a206 0240      	macw %d6u,%d1l,<<
+     168:	a206 0640      	macw %d6u,%d1l,>>
+     16c:	a293 a089      	macw %a1l,%a2u,%a3@,%d1
+     170:	a6d3 a089      	macw %a1l,%a2u,%a3@,%a3
+     174:	a493 a089      	macw %a1l,%a2u,%a3@,%d2
+     178:	aed3 a089      	macw %a1l,%a2u,%a3@,%sp
+     17c:	a293 a0a9      	macw %a1l,%a2u,%a3@&,%d1
+     180:	a6d3 a0a9      	macw %a1l,%a2u,%a3@&,%a3
+     184:	a493 a0a9      	macw %a1l,%a2u,%a3@&,%d2
+     188:	aed3 a0a9      	macw %a1l,%a2u,%a3@&,%sp
+     18c:	a29a a089      	macw %a1l,%a2u,%a2@\+,%d1
+     190:	a6da a089      	macw %a1l,%a2u,%a2@\+,%a3
+     194:	a49a a089      	macw %a1l,%a2u,%a2@\+,%d2
+     198:	aeda a089      	macw %a1l,%a2u,%a2@\+,%sp
+     19c:	a29a a0a9      	macw %a1l,%a2u,%a2@\+&,%d1
+     1a0:	a6da a0a9      	macw %a1l,%a2u,%a2@\+&,%a3
+     1a4:	a49a a0a9      	macw %a1l,%a2u,%a2@\+&,%d2
+     1a8:	aeda a0a9      	macw %a1l,%a2u,%a2@\+&,%sp
+     1ac:	a2ae a089 000a 	macw %a1l,%a2u,%fp@\(10\),%d1
+     1b2:	a6ee a089 000a 	macw %a1l,%a2u,%fp@\(10\),%a3
+     1b8:	a4ae a089 000a 	macw %a1l,%a2u,%fp@\(10\),%d2
+     1be:	aeee a089 000a 	macw %a1l,%a2u,%fp@\(10\),%sp
+     1c4:	a2ae a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d1
+     1ca:	a6ee a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%a3
+     1d0:	a4ae a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%d2
+     1d6:	aeee a0a9 000a 	macw %a1l,%a2u,%fp@\(10\)&,%sp
+     1dc:	a2a1 a089      	macw %a1l,%a2u,%a1@-,%d1
+     1e0:	a6e1 a089      	macw %a1l,%a2u,%a1@-,%a3
+     1e4:	a4a1 a089      	macw %a1l,%a2u,%a1@-,%d2
+     1e8:	aee1 a089      	macw %a1l,%a2u,%a1@-,%sp
+     1ec:	a2a1 a0a9      	macw %a1l,%a2u,%a1@-&,%d1
+     1f0:	a6e1 a0a9      	macw %a1l,%a2u,%a1@-&,%a3
+     1f4:	a4a1 a0a9      	macw %a1l,%a2u,%a1@-&,%d2
+     1f8:	aee1 a0a9      	macw %a1l,%a2u,%a1@-&,%sp
+     1fc:	a293 a289      	macw %a1l,%a2u,<<,%a3@,%d1
+     200:	a6d3 a289      	macw %a1l,%a2u,<<,%a3@,%a3
+     204:	a493 a289      	macw %a1l,%a2u,<<,%a3@,%d2
+     208:	aed3 a289      	macw %a1l,%a2u,<<,%a3@,%sp
+     20c:	a293 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d1
+     210:	a6d3 a2a9      	macw %a1l,%a2u,<<,%a3@&,%a3
+     214:	a493 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d2
+     218:	aed3 a2a9      	macw %a1l,%a2u,<<,%a3@&,%sp
+     21c:	a29a a289      	macw %a1l,%a2u,<<,%a2@\+,%d1
+     220:	a6da a289      	macw %a1l,%a2u,<<,%a2@\+,%a3
+     224:	a49a a289      	macw %a1l,%a2u,<<,%a2@\+,%d2
+     228:	aeda a289      	macw %a1l,%a2u,<<,%a2@\+,%sp
+     22c:	a29a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d1
+     230:	a6da a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%a3
+     234:	a49a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d2
+     238:	aeda a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%sp
+     23c:	a2ae a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1
+     242:	a6ee a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3
+     248:	a4ae a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2
+     24e:	aeee a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp
+     254:	a2ae a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1
+     25a:	a6ee a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3
+     260:	a4ae a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2
+     266:	aeee a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp
+     26c:	a2a1 a289      	macw %a1l,%a2u,<<,%a1@-,%d1
+     270:	a6e1 a289      	macw %a1l,%a2u,<<,%a1@-,%a3
+     274:	a4a1 a289      	macw %a1l,%a2u,<<,%a1@-,%d2
+     278:	aee1 a289      	macw %a1l,%a2u,<<,%a1@-,%sp
+     27c:	a2a1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d1
+     280:	a6e1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%a3
+     284:	a4a1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d2
+     288:	aee1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%sp
+     28c:	a293 a689      	macw %a1l,%a2u,>>,%a3@,%d1
+     290:	a6d3 a689      	macw %a1l,%a2u,>>,%a3@,%a3
+     294:	a493 a689      	macw %a1l,%a2u,>>,%a3@,%d2
+     298:	aed3 a689      	macw %a1l,%a2u,>>,%a3@,%sp
+     29c:	a293 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d1
+     2a0:	a6d3 a6a9      	macw %a1l,%a2u,>>,%a3@&,%a3
+     2a4:	a493 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d2
+     2a8:	aed3 a6a9      	macw %a1l,%a2u,>>,%a3@&,%sp
+     2ac:	a29a a689      	macw %a1l,%a2u,>>,%a2@\+,%d1
+     2b0:	a6da a689      	macw %a1l,%a2u,>>,%a2@\+,%a3
+     2b4:	a49a a689      	macw %a1l,%a2u,>>,%a2@\+,%d2
+     2b8:	aeda a689      	macw %a1l,%a2u,>>,%a2@\+,%sp
+     2bc:	a29a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d1
+     2c0:	a6da a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%a3
+     2c4:	a49a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d2
+     2c8:	aeda a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%sp
+     2cc:	a2ae a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1
+     2d2:	a6ee a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3
+     2d8:	a4ae a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2
+     2de:	aeee a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp
+     2e4:	a2ae a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1
+     2ea:	a6ee a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3
+     2f0:	a4ae a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2
+     2f6:	aeee a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp
+     2fc:	a2a1 a689      	macw %a1l,%a2u,>>,%a1@-,%d1
+     300:	a6e1 a689      	macw %a1l,%a2u,>>,%a1@-,%a3
+     304:	a4a1 a689      	macw %a1l,%a2u,>>,%a1@-,%d2
+     308:	aee1 a689      	macw %a1l,%a2u,>>,%a1@-,%sp
+     30c:	a2a1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d1
+     310:	a6e1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%a3
+     314:	a4a1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d2
+     318:	aee1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%sp
+     31c:	a293 a289      	macw %a1l,%a2u,<<,%a3@,%d1
+     320:	a6d3 a289      	macw %a1l,%a2u,<<,%a3@,%a3
+     324:	a493 a289      	macw %a1l,%a2u,<<,%a3@,%d2
+     328:	aed3 a289      	macw %a1l,%a2u,<<,%a3@,%sp
+     32c:	a293 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d1
+     330:	a6d3 a2a9      	macw %a1l,%a2u,<<,%a3@&,%a3
+     334:	a493 a2a9      	macw %a1l,%a2u,<<,%a3@&,%d2
+     338:	aed3 a2a9      	macw %a1l,%a2u,<<,%a3@&,%sp
+     33c:	a29a a289      	macw %a1l,%a2u,<<,%a2@\+,%d1
+     340:	a6da a289      	macw %a1l,%a2u,<<,%a2@\+,%a3
+     344:	a49a a289      	macw %a1l,%a2u,<<,%a2@\+,%d2
+     348:	aeda a289      	macw %a1l,%a2u,<<,%a2@\+,%sp
+     34c:	a29a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d1
+     350:	a6da a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%a3
+     354:	a49a a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%d2
+     358:	aeda a2a9      	macw %a1l,%a2u,<<,%a2@\+&,%sp
+     35c:	a2ae a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d1
+     362:	a6ee a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%a3
+     368:	a4ae a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%d2
+     36e:	aeee a289 000a 	macw %a1l,%a2u,<<,%fp@\(10\),%sp
+     374:	a2ae a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d1
+     37a:	a6ee a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%a3
+     380:	a4ae a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%d2
+     386:	aeee a2a9 000a 	macw %a1l,%a2u,<<,%fp@\(10\)&,%sp
+     38c:	a2a1 a289      	macw %a1l,%a2u,<<,%a1@-,%d1
+     390:	a6e1 a289      	macw %a1l,%a2u,<<,%a1@-,%a3
+     394:	a4a1 a289      	macw %a1l,%a2u,<<,%a1@-,%d2
+     398:	aee1 a289      	macw %a1l,%a2u,<<,%a1@-,%sp
+     39c:	a2a1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d1
+     3a0:	a6e1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%a3
+     3a4:	a4a1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%d2
+     3a8:	aee1 a2a9      	macw %a1l,%a2u,<<,%a1@-&,%sp
+     3ac:	a293 a689      	macw %a1l,%a2u,>>,%a3@,%d1
+     3b0:	a6d3 a689      	macw %a1l,%a2u,>>,%a3@,%a3
+     3b4:	a493 a689      	macw %a1l,%a2u,>>,%a3@,%d2
+     3b8:	aed3 a689      	macw %a1l,%a2u,>>,%a3@,%sp
+     3bc:	a293 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d1
+     3c0:	a6d3 a6a9      	macw %a1l,%a2u,>>,%a3@&,%a3
+     3c4:	a493 a6a9      	macw %a1l,%a2u,>>,%a3@&,%d2
+     3c8:	aed3 a6a9      	macw %a1l,%a2u,>>,%a3@&,%sp
+     3cc:	a29a a689      	macw %a1l,%a2u,>>,%a2@\+,%d1
+     3d0:	a6da a689      	macw %a1l,%a2u,>>,%a2@\+,%a3
+     3d4:	a49a a689      	macw %a1l,%a2u,>>,%a2@\+,%d2
+     3d8:	aeda a689      	macw %a1l,%a2u,>>,%a2@\+,%sp
+     3dc:	a29a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d1
+     3e0:	a6da a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%a3
+     3e4:	a49a a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%d2
+     3e8:	aeda a6a9      	macw %a1l,%a2u,>>,%a2@\+&,%sp
+     3ec:	a2ae a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d1
+     3f2:	a6ee a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%a3
+     3f8:	a4ae a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%d2
+     3fe:	aeee a689 000a 	macw %a1l,%a2u,>>,%fp@\(10\),%sp
+     404:	a2ae a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d1
+     40a:	a6ee a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%a3
+     410:	a4ae a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%d2
+     416:	aeee a6a9 000a 	macw %a1l,%a2u,>>,%fp@\(10\)&,%sp
+     41c:	a2a1 a689      	macw %a1l,%a2u,>>,%a1@-,%d1
+     420:	a6e1 a689      	macw %a1l,%a2u,>>,%a1@-,%a3
+     424:	a4a1 a689      	macw %a1l,%a2u,>>,%a1@-,%d2
+     428:	aee1 a689      	macw %a1l,%a2u,>>,%a1@-,%sp
+     42c:	a2a1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d1
+     430:	a6e1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%a3
+     434:	a4a1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%d2
+     438:	aee1 a6a9      	macw %a1l,%a2u,>>,%a1@-&,%sp
+     43c:	a293 3009      	macw %a1l,%d3l,%a3@,%d1
+     440:	a6d3 3009      	macw %a1l,%d3l,%a3@,%a3
+     444:	a493 3009      	macw %a1l,%d3l,%a3@,%d2
+     448:	aed3 3009      	macw %a1l,%d3l,%a3@,%sp
+     44c:	a293 3029      	macw %a1l,%d3l,%a3@&,%d1
+     450:	a6d3 3029      	macw %a1l,%d3l,%a3@&,%a3
+     454:	a493 3029      	macw %a1l,%d3l,%a3@&,%d2
+     458:	aed3 3029      	macw %a1l,%d3l,%a3@&,%sp
+     45c:	a29a 3009      	macw %a1l,%d3l,%a2@\+,%d1
+     460:	a6da 3009      	macw %a1l,%d3l,%a2@\+,%a3
+     464:	a49a 3009      	macw %a1l,%d3l,%a2@\+,%d2
+     468:	aeda 3009      	macw %a1l,%d3l,%a2@\+,%sp
+     46c:	a29a 3029      	macw %a1l,%d3l,%a2@\+&,%d1
+     470:	a6da 3029      	macw %a1l,%d3l,%a2@\+&,%a3
+     474:	a49a 3029      	macw %a1l,%d3l,%a2@\+&,%d2
+     478:	aeda 3029      	macw %a1l,%d3l,%a2@\+&,%sp
+     47c:	a2ae 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%d1
+     482:	a6ee 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%a3
+     488:	a4ae 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%d2
+     48e:	aeee 3009 000a 	macw %a1l,%d3l,%fp@\(10\),%sp
+     494:	a2ae 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d1
+     49a:	a6ee 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%a3
+     4a0:	a4ae 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%d2
+     4a6:	aeee 3029 000a 	macw %a1l,%d3l,%fp@\(10\)&,%sp
+     4ac:	a2a1 3009      	macw %a1l,%d3l,%a1@-,%d1
+     4b0:	a6e1 3009      	macw %a1l,%d3l,%a1@-,%a3
+     4b4:	a4a1 3009      	macw %a1l,%d3l,%a1@-,%d2
+     4b8:	aee1 3009      	macw %a1l,%d3l,%a1@-,%sp
+     4bc:	a2a1 3029      	macw %a1l,%d3l,%a1@-&,%d1
+     4c0:	a6e1 3029      	macw %a1l,%d3l,%a1@-&,%a3
+     4c4:	a4a1 3029      	macw %a1l,%d3l,%a1@-&,%d2
+     4c8:	aee1 3029      	macw %a1l,%d3l,%a1@-&,%sp
+     4cc:	a293 3209      	macw %a1l,%d3l,<<,%a3@,%d1
+     4d0:	a6d3 3209      	macw %a1l,%d3l,<<,%a3@,%a3
+     4d4:	a493 3209      	macw %a1l,%d3l,<<,%a3@,%d2
+     4d8:	aed3 3209      	macw %a1l,%d3l,<<,%a3@,%sp
+     4dc:	a293 3229      	macw %a1l,%d3l,<<,%a3@&,%d1
+     4e0:	a6d3 3229      	macw %a1l,%d3l,<<,%a3@&,%a3
+     4e4:	a493 3229      	macw %a1l,%d3l,<<,%a3@&,%d2
+     4e8:	aed3 3229      	macw %a1l,%d3l,<<,%a3@&,%sp
+     4ec:	a29a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d1
+     4f0:	a6da 3209      	macw %a1l,%d3l,<<,%a2@\+,%a3
+     4f4:	a49a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d2
+     4f8:	aeda 3209      	macw %a1l,%d3l,<<,%a2@\+,%sp
+     4fc:	a29a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d1
+     500:	a6da 3229      	macw %a1l,%d3l,<<,%a2@\+&,%a3
+     504:	a49a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d2
+     508:	aeda 3229      	macw %a1l,%d3l,<<,%a2@\+&,%sp
+     50c:	a2ae 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1
+     512:	a6ee 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3
+     518:	a4ae 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2
+     51e:	aeee 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp
+     524:	a2ae 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1
+     52a:	a6ee 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3
+     530:	a4ae 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2
+     536:	aeee 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp
+     53c:	a2a1 3209      	macw %a1l,%d3l,<<,%a1@-,%d1
+     540:	a6e1 3209      	macw %a1l,%d3l,<<,%a1@-,%a3
+     544:	a4a1 3209      	macw %a1l,%d3l,<<,%a1@-,%d2
+     548:	aee1 3209      	macw %a1l,%d3l,<<,%a1@-,%sp
+     54c:	a2a1 3229      	macw %a1l,%d3l,<<,%a1@-&,%d1
+     550:	a6e1 3229      	macw %a1l,%d3l,<<,%a1@-&,%a3
+     554:	a4a1 3229      	macw %a1l,%d3l,<<,%a1@-&,%d2
+     558:	aee1 3229      	macw %a1l,%d3l,<<,%a1@-&,%sp
+     55c:	a293 3609      	macw %a1l,%d3l,>>,%a3@,%d1
+     560:	a6d3 3609      	macw %a1l,%d3l,>>,%a3@,%a3
+     564:	a493 3609      	macw %a1l,%d3l,>>,%a3@,%d2
+     568:	aed3 3609      	macw %a1l,%d3l,>>,%a3@,%sp
+     56c:	a293 3629      	macw %a1l,%d3l,>>,%a3@&,%d1
+     570:	a6d3 3629      	macw %a1l,%d3l,>>,%a3@&,%a3
+     574:	a493 3629      	macw %a1l,%d3l,>>,%a3@&,%d2
+     578:	aed3 3629      	macw %a1l,%d3l,>>,%a3@&,%sp
+     57c:	a29a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d1
+     580:	a6da 3609      	macw %a1l,%d3l,>>,%a2@\+,%a3
+     584:	a49a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d2
+     588:	aeda 3609      	macw %a1l,%d3l,>>,%a2@\+,%sp
+     58c:	a29a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d1
+     590:	a6da 3629      	macw %a1l,%d3l,>>,%a2@\+&,%a3
+     594:	a49a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d2
+     598:	aeda 3629      	macw %a1l,%d3l,>>,%a2@\+&,%sp
+     59c:	a2ae 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1
+     5a2:	a6ee 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3
+     5a8:	a4ae 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2
+     5ae:	aeee 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp
+     5b4:	a2ae 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1
+     5ba:	a6ee 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3
+     5c0:	a4ae 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2
+     5c6:	aeee 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp
+     5cc:	a2a1 3609      	macw %a1l,%d3l,>>,%a1@-,%d1
+     5d0:	a6e1 3609      	macw %a1l,%d3l,>>,%a1@-,%a3
+     5d4:	a4a1 3609      	macw %a1l,%d3l,>>,%a1@-,%d2
+     5d8:	aee1 3609      	macw %a1l,%d3l,>>,%a1@-,%sp
+     5dc:	a2a1 3629      	macw %a1l,%d3l,>>,%a1@-&,%d1
+     5e0:	a6e1 3629      	macw %a1l,%d3l,>>,%a1@-&,%a3
+     5e4:	a4a1 3629      	macw %a1l,%d3l,>>,%a1@-&,%d2
+     5e8:	aee1 3629      	macw %a1l,%d3l,>>,%a1@-&,%sp
+     5ec:	a293 3209      	macw %a1l,%d3l,<<,%a3@,%d1
+     5f0:	a6d3 3209      	macw %a1l,%d3l,<<,%a3@,%a3
+     5f4:	a493 3209      	macw %a1l,%d3l,<<,%a3@,%d2
+     5f8:	aed3 3209      	macw %a1l,%d3l,<<,%a3@,%sp
+     5fc:	a293 3229      	macw %a1l,%d3l,<<,%a3@&,%d1
+     600:	a6d3 3229      	macw %a1l,%d3l,<<,%a3@&,%a3
+     604:	a493 3229      	macw %a1l,%d3l,<<,%a3@&,%d2
+     608:	aed3 3229      	macw %a1l,%d3l,<<,%a3@&,%sp
+     60c:	a29a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d1
+     610:	a6da 3209      	macw %a1l,%d3l,<<,%a2@\+,%a3
+     614:	a49a 3209      	macw %a1l,%d3l,<<,%a2@\+,%d2
+     618:	aeda 3209      	macw %a1l,%d3l,<<,%a2@\+,%sp
+     61c:	a29a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d1
+     620:	a6da 3229      	macw %a1l,%d3l,<<,%a2@\+&,%a3
+     624:	a49a 3229      	macw %a1l,%d3l,<<,%a2@\+&,%d2
+     628:	aeda 3229      	macw %a1l,%d3l,<<,%a2@\+&,%sp
+     62c:	a2ae 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d1
+     632:	a6ee 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%a3
+     638:	a4ae 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%d2
+     63e:	aeee 3209 000a 	macw %a1l,%d3l,<<,%fp@\(10\),%sp
+     644:	a2ae 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d1
+     64a:	a6ee 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%a3
+     650:	a4ae 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%d2
+     656:	aeee 3229 000a 	macw %a1l,%d3l,<<,%fp@\(10\)&,%sp
+     65c:	a2a1 3209      	macw %a1l,%d3l,<<,%a1@-,%d1
+     660:	a6e1 3209      	macw %a1l,%d3l,<<,%a1@-,%a3
+     664:	a4a1 3209      	macw %a1l,%d3l,<<,%a1@-,%d2
+     668:	aee1 3209      	macw %a1l,%d3l,<<,%a1@-,%sp
+     66c:	a2a1 3229      	macw %a1l,%d3l,<<,%a1@-&,%d1
+     670:	a6e1 3229      	macw %a1l,%d3l,<<,%a1@-&,%a3
+     674:	a4a1 3229      	macw %a1l,%d3l,<<,%a1@-&,%d2
+     678:	aee1 3229      	macw %a1l,%d3l,<<,%a1@-&,%sp
+     67c:	a293 3609      	macw %a1l,%d3l,>>,%a3@,%d1
+     680:	a6d3 3609      	macw %a1l,%d3l,>>,%a3@,%a3
+     684:	a493 3609      	macw %a1l,%d3l,>>,%a3@,%d2
+     688:	aed3 3609      	macw %a1l,%d3l,>>,%a3@,%sp
+     68c:	a293 3629      	macw %a1l,%d3l,>>,%a3@&,%d1
+     690:	a6d3 3629      	macw %a1l,%d3l,>>,%a3@&,%a3
+     694:	a493 3629      	macw %a1l,%d3l,>>,%a3@&,%d2
+     698:	aed3 3629      	macw %a1l,%d3l,>>,%a3@&,%sp
+     69c:	a29a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d1
+     6a0:	a6da 3609      	macw %a1l,%d3l,>>,%a2@\+,%a3
+     6a4:	a49a 3609      	macw %a1l,%d3l,>>,%a2@\+,%d2
+     6a8:	aeda 3609      	macw %a1l,%d3l,>>,%a2@\+,%sp
+     6ac:	a29a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d1
+     6b0:	a6da 3629      	macw %a1l,%d3l,>>,%a2@\+&,%a3
+     6b4:	a49a 3629      	macw %a1l,%d3l,>>,%a2@\+&,%d2
+     6b8:	aeda 3629      	macw %a1l,%d3l,>>,%a2@\+&,%sp
+     6bc:	a2ae 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d1
+     6c2:	a6ee 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%a3
+     6c8:	a4ae 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%d2
+     6ce:	aeee 3609 000a 	macw %a1l,%d3l,>>,%fp@\(10\),%sp
+     6d4:	a2ae 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d1
+     6da:	a6ee 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%a3
+     6e0:	a4ae 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%d2
+     6e6:	aeee 3629 000a 	macw %a1l,%d3l,>>,%fp@\(10\)&,%sp
+     6ec:	a2a1 3609      	macw %a1l,%d3l,>>,%a1@-,%d1
+     6f0:	a6e1 3609      	macw %a1l,%d3l,>>,%a1@-,%a3
+     6f4:	a4a1 3609      	macw %a1l,%d3l,>>,%a1@-,%d2
+     6f8:	aee1 3609      	macw %a1l,%d3l,>>,%a1@-,%sp
+     6fc:	a2a1 3629      	macw %a1l,%d3l,>>,%a1@-&,%d1
+     700:	a6e1 3629      	macw %a1l,%d3l,>>,%a1@-&,%a3
+     704:	a4a1 3629      	macw %a1l,%d3l,>>,%a1@-&,%d2
+     708:	aee1 3629      	macw %a1l,%d3l,>>,%a1@-&,%sp
+     70c:	a293 f089      	macw %a1l,%a7u,%a3@,%d1
+     710:	a6d3 f089      	macw %a1l,%a7u,%a3@,%a3
+     714:	a493 f089      	macw %a1l,%a7u,%a3@,%d2
+     718:	aed3 f089      	macw %a1l,%a7u,%a3@,%sp
+     71c:	a293 f0a9      	macw %a1l,%a7u,%a3@&,%d1
+     720:	a6d3 f0a9      	macw %a1l,%a7u,%a3@&,%a3
+     724:	a493 f0a9      	macw %a1l,%a7u,%a3@&,%d2
+     728:	aed3 f0a9      	macw %a1l,%a7u,%a3@&,%sp
+     72c:	a29a f089      	macw %a1l,%a7u,%a2@\+,%d1
+     730:	a6da f089      	macw %a1l,%a7u,%a2@\+,%a3
+     734:	a49a f089      	macw %a1l,%a7u,%a2@\+,%d2
+     738:	aeda f089      	macw %a1l,%a7u,%a2@\+,%sp
+     73c:	a29a f0a9      	macw %a1l,%a7u,%a2@\+&,%d1
+     740:	a6da f0a9      	macw %a1l,%a7u,%a2@\+&,%a3
+     744:	a49a f0a9      	macw %a1l,%a7u,%a2@\+&,%d2
+     748:	aeda f0a9      	macw %a1l,%a7u,%a2@\+&,%sp
+     74c:	a2ae f089 000a 	macw %a1l,%a7u,%fp@\(10\),%d1
+     752:	a6ee f089 000a 	macw %a1l,%a7u,%fp@\(10\),%a3
+     758:	a4ae f089 000a 	macw %a1l,%a7u,%fp@\(10\),%d2
+     75e:	aeee f089 000a 	macw %a1l,%a7u,%fp@\(10\),%sp
+     764:	a2ae f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d1
+     76a:	a6ee f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%a3
+     770:	a4ae f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%d2
+     776:	aeee f0a9 000a 	macw %a1l,%a7u,%fp@\(10\)&,%sp
+     77c:	a2a1 f089      	macw %a1l,%a7u,%a1@-,%d1
+     780:	a6e1 f089      	macw %a1l,%a7u,%a1@-,%a3
+     784:	a4a1 f089      	macw %a1l,%a7u,%a1@-,%d2
+     788:	aee1 f089      	macw %a1l,%a7u,%a1@-,%sp
+     78c:	a2a1 f0a9      	macw %a1l,%a7u,%a1@-&,%d1
+     790:	a6e1 f0a9      	macw %a1l,%a7u,%a1@-&,%a3
+     794:	a4a1 f0a9      	macw %a1l,%a7u,%a1@-&,%d2
+     798:	aee1 f0a9      	macw %a1l,%a7u,%a1@-&,%sp
+     79c:	a293 f289      	macw %a1l,%a7u,<<,%a3@,%d1
+     7a0:	a6d3 f289      	macw %a1l,%a7u,<<,%a3@,%a3
+     7a4:	a493 f289      	macw %a1l,%a7u,<<,%a3@,%d2
+     7a8:	aed3 f289      	macw %a1l,%a7u,<<,%a3@,%sp
+     7ac:	a293 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d1
+     7b0:	a6d3 f2a9      	macw %a1l,%a7u,<<,%a3@&,%a3
+     7b4:	a493 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d2
+     7b8:	aed3 f2a9      	macw %a1l,%a7u,<<,%a3@&,%sp
+     7bc:	a29a f289      	macw %a1l,%a7u,<<,%a2@\+,%d1
+     7c0:	a6da f289      	macw %a1l,%a7u,<<,%a2@\+,%a3
+     7c4:	a49a f289      	macw %a1l,%a7u,<<,%a2@\+,%d2
+     7c8:	aeda f289      	macw %a1l,%a7u,<<,%a2@\+,%sp
+     7cc:	a29a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d1
+     7d0:	a6da f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%a3
+     7d4:	a49a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d2
+     7d8:	aeda f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%sp
+     7dc:	a2ae f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1
+     7e2:	a6ee f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3
+     7e8:	a4ae f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2
+     7ee:	aeee f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp
+     7f4:	a2ae f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1
+     7fa:	a6ee f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3
+     800:	a4ae f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2
+     806:	aeee f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp
+     80c:	a2a1 f289      	macw %a1l,%a7u,<<,%a1@-,%d1
+     810:	a6e1 f289      	macw %a1l,%a7u,<<,%a1@-,%a3
+     814:	a4a1 f289      	macw %a1l,%a7u,<<,%a1@-,%d2
+     818:	aee1 f289      	macw %a1l,%a7u,<<,%a1@-,%sp
+     81c:	a2a1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d1
+     820:	a6e1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%a3
+     824:	a4a1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d2
+     828:	aee1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%sp
+     82c:	a293 f689      	macw %a1l,%a7u,>>,%a3@,%d1
+     830:	a6d3 f689      	macw %a1l,%a7u,>>,%a3@,%a3
+     834:	a493 f689      	macw %a1l,%a7u,>>,%a3@,%d2
+     838:	aed3 f689      	macw %a1l,%a7u,>>,%a3@,%sp
+     83c:	a293 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d1
+     840:	a6d3 f6a9      	macw %a1l,%a7u,>>,%a3@&,%a3
+     844:	a493 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d2
+     848:	aed3 f6a9      	macw %a1l,%a7u,>>,%a3@&,%sp
+     84c:	a29a f689      	macw %a1l,%a7u,>>,%a2@\+,%d1
+     850:	a6da f689      	macw %a1l,%a7u,>>,%a2@\+,%a3
+     854:	a49a f689      	macw %a1l,%a7u,>>,%a2@\+,%d2
+     858:	aeda f689      	macw %a1l,%a7u,>>,%a2@\+,%sp
+     85c:	a29a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d1
+     860:	a6da f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%a3
+     864:	a49a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d2
+     868:	aeda f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%sp
+     86c:	a2ae f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1
+     872:	a6ee f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3
+     878:	a4ae f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2
+     87e:	aeee f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp
+     884:	a2ae f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1
+     88a:	a6ee f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3
+     890:	a4ae f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2
+     896:	aeee f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp
+     89c:	a2a1 f689      	macw %a1l,%a7u,>>,%a1@-,%d1
+     8a0:	a6e1 f689      	macw %a1l,%a7u,>>,%a1@-,%a3
+     8a4:	a4a1 f689      	macw %a1l,%a7u,>>,%a1@-,%d2
+     8a8:	aee1 f689      	macw %a1l,%a7u,>>,%a1@-,%sp
+     8ac:	a2a1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d1
+     8b0:	a6e1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%a3
+     8b4:	a4a1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d2
+     8b8:	aee1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%sp
+     8bc:	a293 f289      	macw %a1l,%a7u,<<,%a3@,%d1
+     8c0:	a6d3 f289      	macw %a1l,%a7u,<<,%a3@,%a3
+     8c4:	a493 f289      	macw %a1l,%a7u,<<,%a3@,%d2
+     8c8:	aed3 f289      	macw %a1l,%a7u,<<,%a3@,%sp
+     8cc:	a293 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d1
+     8d0:	a6d3 f2a9      	macw %a1l,%a7u,<<,%a3@&,%a3
+     8d4:	a493 f2a9      	macw %a1l,%a7u,<<,%a3@&,%d2
+     8d8:	aed3 f2a9      	macw %a1l,%a7u,<<,%a3@&,%sp
+     8dc:	a29a f289      	macw %a1l,%a7u,<<,%a2@\+,%d1
+     8e0:	a6da f289      	macw %a1l,%a7u,<<,%a2@\+,%a3
+     8e4:	a49a f289      	macw %a1l,%a7u,<<,%a2@\+,%d2
+     8e8:	aeda f289      	macw %a1l,%a7u,<<,%a2@\+,%sp
+     8ec:	a29a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d1
+     8f0:	a6da f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%a3
+     8f4:	a49a f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%d2
+     8f8:	aeda f2a9      	macw %a1l,%a7u,<<,%a2@\+&,%sp
+     8fc:	a2ae f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d1
+     902:	a6ee f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%a3
+     908:	a4ae f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%d2
+     90e:	aeee f289 000a 	macw %a1l,%a7u,<<,%fp@\(10\),%sp
+     914:	a2ae f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d1
+     91a:	a6ee f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%a3
+     920:	a4ae f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%d2
+     926:	aeee f2a9 000a 	macw %a1l,%a7u,<<,%fp@\(10\)&,%sp
+     92c:	a2a1 f289      	macw %a1l,%a7u,<<,%a1@-,%d1
+     930:	a6e1 f289      	macw %a1l,%a7u,<<,%a1@-,%a3
+     934:	a4a1 f289      	macw %a1l,%a7u,<<,%a1@-,%d2
+     938:	aee1 f289      	macw %a1l,%a7u,<<,%a1@-,%sp
+     93c:	a2a1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d1
+     940:	a6e1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%a3
+     944:	a4a1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%d2
+     948:	aee1 f2a9      	macw %a1l,%a7u,<<,%a1@-&,%sp
+     94c:	a293 f689      	macw %a1l,%a7u,>>,%a3@,%d1
+     950:	a6d3 f689      	macw %a1l,%a7u,>>,%a3@,%a3
+     954:	a493 f689      	macw %a1l,%a7u,>>,%a3@,%d2
+     958:	aed3 f689      	macw %a1l,%a7u,>>,%a3@,%sp
+     95c:	a293 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d1
+     960:	a6d3 f6a9      	macw %a1l,%a7u,>>,%a3@&,%a3
+     964:	a493 f6a9      	macw %a1l,%a7u,>>,%a3@&,%d2
+     968:	aed3 f6a9      	macw %a1l,%a7u,>>,%a3@&,%sp
+     96c:	a29a f689      	macw %a1l,%a7u,>>,%a2@\+,%d1
+     970:	a6da f689      	macw %a1l,%a7u,>>,%a2@\+,%a3
+     974:	a49a f689      	macw %a1l,%a7u,>>,%a2@\+,%d2
+     978:	aeda f689      	macw %a1l,%a7u,>>,%a2@\+,%sp
+     97c:	a29a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d1
+     980:	a6da f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%a3
+     984:	a49a f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%d2
+     988:	aeda f6a9      	macw %a1l,%a7u,>>,%a2@\+&,%sp
+     98c:	a2ae f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d1
+     992:	a6ee f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%a3
+     998:	a4ae f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%d2
+     99e:	aeee f689 000a 	macw %a1l,%a7u,>>,%fp@\(10\),%sp
+     9a4:	a2ae f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d1
+     9aa:	a6ee f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%a3
+     9b0:	a4ae f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%d2
+     9b6:	aeee f6a9 000a 	macw %a1l,%a7u,>>,%fp@\(10\)&,%sp
+     9bc:	a2a1 f689      	macw %a1l,%a7u,>>,%a1@-,%d1
+     9c0:	a6e1 f689      	macw %a1l,%a7u,>>,%a1@-,%a3
+     9c4:	a4a1 f689      	macw %a1l,%a7u,>>,%a1@-,%d2
+     9c8:	aee1 f689      	macw %a1l,%a7u,>>,%a1@-,%sp
+     9cc:	a2a1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d1
+     9d0:	a6e1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%a3
+     9d4:	a4a1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%d2
+     9d8:	aee1 f6a9      	macw %a1l,%a7u,>>,%a1@-&,%sp
+     9dc:	a293 1009      	macw %a1l,%d1l,%a3@,%d1
+     9e0:	a6d3 1009      	macw %a1l,%d1l,%a3@,%a3
+     9e4:	a493 1009      	macw %a1l,%d1l,%a3@,%d2
+     9e8:	aed3 1009      	macw %a1l,%d1l,%a3@,%sp
+     9ec:	a293 1029      	macw %a1l,%d1l,%a3@&,%d1
+     9f0:	a6d3 1029      	macw %a1l,%d1l,%a3@&,%a3
+     9f4:	a493 1029      	macw %a1l,%d1l,%a3@&,%d2
+     9f8:	aed3 1029      	macw %a1l,%d1l,%a3@&,%sp
+     9fc:	a29a 1009      	macw %a1l,%d1l,%a2@\+,%d1
+     a00:	a6da 1009      	macw %a1l,%d1l,%a2@\+,%a3
+     a04:	a49a 1009      	macw %a1l,%d1l,%a2@\+,%d2
+     a08:	aeda 1009      	macw %a1l,%d1l,%a2@\+,%sp
+     a0c:	a29a 1029      	macw %a1l,%d1l,%a2@\+&,%d1
+     a10:	a6da 1029      	macw %a1l,%d1l,%a2@\+&,%a3
+     a14:	a49a 1029      	macw %a1l,%d1l,%a2@\+&,%d2
+     a18:	aeda 1029      	macw %a1l,%d1l,%a2@\+&,%sp
+     a1c:	a2ae 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%d1
+     a22:	a6ee 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%a3
+     a28:	a4ae 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%d2
+     a2e:	aeee 1009 000a 	macw %a1l,%d1l,%fp@\(10\),%sp
+     a34:	a2ae 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d1
+     a3a:	a6ee 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%a3
+     a40:	a4ae 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%d2
+     a46:	aeee 1029 000a 	macw %a1l,%d1l,%fp@\(10\)&,%sp
+     a4c:	a2a1 1009      	macw %a1l,%d1l,%a1@-,%d1
+     a50:	a6e1 1009      	macw %a1l,%d1l,%a1@-,%a3
+     a54:	a4a1 1009      	macw %a1l,%d1l,%a1@-,%d2
+     a58:	aee1 1009      	macw %a1l,%d1l,%a1@-,%sp
+     a5c:	a2a1 1029      	macw %a1l,%d1l,%a1@-&,%d1
+     a60:	a6e1 1029      	macw %a1l,%d1l,%a1@-&,%a3
+     a64:	a4a1 1029      	macw %a1l,%d1l,%a1@-&,%d2
+     a68:	aee1 1029      	macw %a1l,%d1l,%a1@-&,%sp
+     a6c:	a293 1209      	macw %a1l,%d1l,<<,%a3@,%d1
+     a70:	a6d3 1209      	macw %a1l,%d1l,<<,%a3@,%a3
+     a74:	a493 1209      	macw %a1l,%d1l,<<,%a3@,%d2
+     a78:	aed3 1209      	macw %a1l,%d1l,<<,%a3@,%sp
+     a7c:	a293 1229      	macw %a1l,%d1l,<<,%a3@&,%d1
+     a80:	a6d3 1229      	macw %a1l,%d1l,<<,%a3@&,%a3
+     a84:	a493 1229      	macw %a1l,%d1l,<<,%a3@&,%d2
+     a88:	aed3 1229      	macw %a1l,%d1l,<<,%a3@&,%sp
+     a8c:	a29a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d1
+     a90:	a6da 1209      	macw %a1l,%d1l,<<,%a2@\+,%a3
+     a94:	a49a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d2
+     a98:	aeda 1209      	macw %a1l,%d1l,<<,%a2@\+,%sp
+     a9c:	a29a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d1
+     aa0:	a6da 1229      	macw %a1l,%d1l,<<,%a2@\+&,%a3
+     aa4:	a49a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d2
+     aa8:	aeda 1229      	macw %a1l,%d1l,<<,%a2@\+&,%sp
+     aac:	a2ae 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1
+     ab2:	a6ee 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3
+     ab8:	a4ae 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2
+     abe:	aeee 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp
+     ac4:	a2ae 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1
+     aca:	a6ee 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3
+     ad0:	a4ae 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2
+     ad6:	aeee 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp
+     adc:	a2a1 1209      	macw %a1l,%d1l,<<,%a1@-,%d1
+     ae0:	a6e1 1209      	macw %a1l,%d1l,<<,%a1@-,%a3
+     ae4:	a4a1 1209      	macw %a1l,%d1l,<<,%a1@-,%d2
+     ae8:	aee1 1209      	macw %a1l,%d1l,<<,%a1@-,%sp
+     aec:	a2a1 1229      	macw %a1l,%d1l,<<,%a1@-&,%d1
+     af0:	a6e1 1229      	macw %a1l,%d1l,<<,%a1@-&,%a3
+     af4:	a4a1 1229      	macw %a1l,%d1l,<<,%a1@-&,%d2
+     af8:	aee1 1229      	macw %a1l,%d1l,<<,%a1@-&,%sp
+     afc:	a293 1609      	macw %a1l,%d1l,>>,%a3@,%d1
+     b00:	a6d3 1609      	macw %a1l,%d1l,>>,%a3@,%a3
+     b04:	a493 1609      	macw %a1l,%d1l,>>,%a3@,%d2
+     b08:	aed3 1609      	macw %a1l,%d1l,>>,%a3@,%sp
+     b0c:	a293 1629      	macw %a1l,%d1l,>>,%a3@&,%d1
+     b10:	a6d3 1629      	macw %a1l,%d1l,>>,%a3@&,%a3
+     b14:	a493 1629      	macw %a1l,%d1l,>>,%a3@&,%d2
+     b18:	aed3 1629      	macw %a1l,%d1l,>>,%a3@&,%sp
+     b1c:	a29a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d1
+     b20:	a6da 1609      	macw %a1l,%d1l,>>,%a2@\+,%a3
+     b24:	a49a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d2
+     b28:	aeda 1609      	macw %a1l,%d1l,>>,%a2@\+,%sp
+     b2c:	a29a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d1
+     b30:	a6da 1629      	macw %a1l,%d1l,>>,%a2@\+&,%a3
+     b34:	a49a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d2
+     b38:	aeda 1629      	macw %a1l,%d1l,>>,%a2@\+&,%sp
+     b3c:	a2ae 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1
+     b42:	a6ee 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3
+     b48:	a4ae 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2
+     b4e:	aeee 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp
+     b54:	a2ae 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1
+     b5a:	a6ee 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3
+     b60:	a4ae 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2
+     b66:	aeee 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp
+     b6c:	a2a1 1609      	macw %a1l,%d1l,>>,%a1@-,%d1
+     b70:	a6e1 1609      	macw %a1l,%d1l,>>,%a1@-,%a3
+     b74:	a4a1 1609      	macw %a1l,%d1l,>>,%a1@-,%d2
+     b78:	aee1 1609      	macw %a1l,%d1l,>>,%a1@-,%sp
+     b7c:	a2a1 1629      	macw %a1l,%d1l,>>,%a1@-&,%d1
+     b80:	a6e1 1629      	macw %a1l,%d1l,>>,%a1@-&,%a3
+     b84:	a4a1 1629      	macw %a1l,%d1l,>>,%a1@-&,%d2
+     b88:	aee1 1629      	macw %a1l,%d1l,>>,%a1@-&,%sp
+     b8c:	a293 1209      	macw %a1l,%d1l,<<,%a3@,%d1
+     b90:	a6d3 1209      	macw %a1l,%d1l,<<,%a3@,%a3
+     b94:	a493 1209      	macw %a1l,%d1l,<<,%a3@,%d2
+     b98:	aed3 1209      	macw %a1l,%d1l,<<,%a3@,%sp
+     b9c:	a293 1229      	macw %a1l,%d1l,<<,%a3@&,%d1
+     ba0:	a6d3 1229      	macw %a1l,%d1l,<<,%a3@&,%a3
+     ba4:	a493 1229      	macw %a1l,%d1l,<<,%a3@&,%d2
+     ba8:	aed3 1229      	macw %a1l,%d1l,<<,%a3@&,%sp
+     bac:	a29a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d1
+     bb0:	a6da 1209      	macw %a1l,%d1l,<<,%a2@\+,%a3
+     bb4:	a49a 1209      	macw %a1l,%d1l,<<,%a2@\+,%d2
+     bb8:	aeda 1209      	macw %a1l,%d1l,<<,%a2@\+,%sp
+     bbc:	a29a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d1
+     bc0:	a6da 1229      	macw %a1l,%d1l,<<,%a2@\+&,%a3
+     bc4:	a49a 1229      	macw %a1l,%d1l,<<,%a2@\+&,%d2
+     bc8:	aeda 1229      	macw %a1l,%d1l,<<,%a2@\+&,%sp
+     bcc:	a2ae 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d1
+     bd2:	a6ee 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%a3
+     bd8:	a4ae 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%d2
+     bde:	aeee 1209 000a 	macw %a1l,%d1l,<<,%fp@\(10\),%sp
+     be4:	a2ae 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d1
+     bea:	a6ee 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%a3
+     bf0:	a4ae 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%d2
+     bf6:	aeee 1229 000a 	macw %a1l,%d1l,<<,%fp@\(10\)&,%sp
+     bfc:	a2a1 1209      	macw %a1l,%d1l,<<,%a1@-,%d1
+     c00:	a6e1 1209      	macw %a1l,%d1l,<<,%a1@-,%a3
+     c04:	a4a1 1209      	macw %a1l,%d1l,<<,%a1@-,%d2
+     c08:	aee1 1209      	macw %a1l,%d1l,<<,%a1@-,%sp
+     c0c:	a2a1 1229      	macw %a1l,%d1l,<<,%a1@-&,%d1
+     c10:	a6e1 1229      	macw %a1l,%d1l,<<,%a1@-&,%a3
+     c14:	a4a1 1229      	macw %a1l,%d1l,<<,%a1@-&,%d2
+     c18:	aee1 1229      	macw %a1l,%d1l,<<,%a1@-&,%sp
+     c1c:	a293 1609      	macw %a1l,%d1l,>>,%a3@,%d1
+     c20:	a6d3 1609      	macw %a1l,%d1l,>>,%a3@,%a3
+     c24:	a493 1609      	macw %a1l,%d1l,>>,%a3@,%d2
+     c28:	aed3 1609      	macw %a1l,%d1l,>>,%a3@,%sp
+     c2c:	a293 1629      	macw %a1l,%d1l,>>,%a3@&,%d1
+     c30:	a6d3 1629      	macw %a1l,%d1l,>>,%a3@&,%a3
+     c34:	a493 1629      	macw %a1l,%d1l,>>,%a3@&,%d2
+     c38:	aed3 1629      	macw %a1l,%d1l,>>,%a3@&,%sp
+     c3c:	a29a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d1
+     c40:	a6da 1609      	macw %a1l,%d1l,>>,%a2@\+,%a3
+     c44:	a49a 1609      	macw %a1l,%d1l,>>,%a2@\+,%d2
+     c48:	aeda 1609      	macw %a1l,%d1l,>>,%a2@\+,%sp
+     c4c:	a29a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d1
+     c50:	a6da 1629      	macw %a1l,%d1l,>>,%a2@\+&,%a3
+     c54:	a49a 1629      	macw %a1l,%d1l,>>,%a2@\+&,%d2
+     c58:	aeda 1629      	macw %a1l,%d1l,>>,%a2@\+&,%sp
+     c5c:	a2ae 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d1
+     c62:	a6ee 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%a3
+     c68:	a4ae 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%d2
+     c6e:	aeee 1609 000a 	macw %a1l,%d1l,>>,%fp@\(10\),%sp
+     c74:	a2ae 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d1
+     c7a:	a6ee 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%a3
+     c80:	a4ae 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%d2
+     c86:	aeee 1629 000a 	macw %a1l,%d1l,>>,%fp@\(10\)&,%sp
+     c8c:	a2a1 1609      	macw %a1l,%d1l,>>,%a1@-,%d1
+     c90:	a6e1 1609      	macw %a1l,%d1l,>>,%a1@-,%a3
+     c94:	a4a1 1609      	macw %a1l,%d1l,>>,%a1@-,%d2
+     c98:	aee1 1609      	macw %a1l,%d1l,>>,%a1@-,%sp
+     c9c:	a2a1 1629      	macw %a1l,%d1l,>>,%a1@-&,%d1
+     ca0:	a6e1 1629      	macw %a1l,%d1l,>>,%a1@-&,%a3
+     ca4:	a4a1 1629      	macw %a1l,%d1l,>>,%a1@-&,%d2
+     ca8:	aee1 1629      	macw %a1l,%d1l,>>,%a1@-&,%sp
+     cac:	a293 a0c2      	macw %d2u,%a2u,%a3@,%d1
+     cb0:	a6d3 a0c2      	macw %d2u,%a2u,%a3@,%a3
+     cb4:	a493 a0c2      	macw %d2u,%a2u,%a3@,%d2
+     cb8:	aed3 a0c2      	macw %d2u,%a2u,%a3@,%sp
+     cbc:	a293 a0e2      	macw %d2u,%a2u,%a3@&,%d1
+     cc0:	a6d3 a0e2      	macw %d2u,%a2u,%a3@&,%a3
+     cc4:	a493 a0e2      	macw %d2u,%a2u,%a3@&,%d2
+     cc8:	aed3 a0e2      	macw %d2u,%a2u,%a3@&,%sp
+     ccc:	a29a a0c2      	macw %d2u,%a2u,%a2@\+,%d1
+     cd0:	a6da a0c2      	macw %d2u,%a2u,%a2@\+,%a3
+     cd4:	a49a a0c2      	macw %d2u,%a2u,%a2@\+,%d2
+     cd8:	aeda a0c2      	macw %d2u,%a2u,%a2@\+,%sp
+     cdc:	a29a a0e2      	macw %d2u,%a2u,%a2@\+&,%d1
+     ce0:	a6da a0e2      	macw %d2u,%a2u,%a2@\+&,%a3
+     ce4:	a49a a0e2      	macw %d2u,%a2u,%a2@\+&,%d2
+     ce8:	aeda a0e2      	macw %d2u,%a2u,%a2@\+&,%sp
+     cec:	a2ae a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%d1
+     cf2:	a6ee a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%a3
+     cf8:	a4ae a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%d2
+     cfe:	aeee a0c2 000a 	macw %d2u,%a2u,%fp@\(10\),%sp
+     d04:	a2ae a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d1
+     d0a:	a6ee a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%a3
+     d10:	a4ae a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%d2
+     d16:	aeee a0e2 000a 	macw %d2u,%a2u,%fp@\(10\)&,%sp
+     d1c:	a2a1 a0c2      	macw %d2u,%a2u,%a1@-,%d1
+     d20:	a6e1 a0c2      	macw %d2u,%a2u,%a1@-,%a3
+     d24:	a4a1 a0c2      	macw %d2u,%a2u,%a1@-,%d2
+     d28:	aee1 a0c2      	macw %d2u,%a2u,%a1@-,%sp
+     d2c:	a2a1 a0e2      	macw %d2u,%a2u,%a1@-&,%d1
+     d30:	a6e1 a0e2      	macw %d2u,%a2u,%a1@-&,%a3
+     d34:	a4a1 a0e2      	macw %d2u,%a2u,%a1@-&,%d2
+     d38:	aee1 a0e2      	macw %d2u,%a2u,%a1@-&,%sp
+     d3c:	a293 a2c2      	macw %d2u,%a2u,<<,%a3@,%d1
+     d40:	a6d3 a2c2      	macw %d2u,%a2u,<<,%a3@,%a3
+     d44:	a493 a2c2      	macw %d2u,%a2u,<<,%a3@,%d2
+     d48:	aed3 a2c2      	macw %d2u,%a2u,<<,%a3@,%sp
+     d4c:	a293 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d1
+     d50:	a6d3 a2e2      	macw %d2u,%a2u,<<,%a3@&,%a3
+     d54:	a493 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d2
+     d58:	aed3 a2e2      	macw %d2u,%a2u,<<,%a3@&,%sp
+     d5c:	a29a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d1
+     d60:	a6da a2c2      	macw %d2u,%a2u,<<,%a2@\+,%a3
+     d64:	a49a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d2
+     d68:	aeda a2c2      	macw %d2u,%a2u,<<,%a2@\+,%sp
+     d6c:	a29a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d1
+     d70:	a6da a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%a3
+     d74:	a49a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d2
+     d78:	aeda a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%sp
+     d7c:	a2ae a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1
+     d82:	a6ee a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3
+     d88:	a4ae a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2
+     d8e:	aeee a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp
+     d94:	a2ae a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1
+     d9a:	a6ee a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3
+     da0:	a4ae a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2
+     da6:	aeee a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp
+     dac:	a2a1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d1
+     db0:	a6e1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%a3
+     db4:	a4a1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d2
+     db8:	aee1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%sp
+     dbc:	a2a1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d1
+     dc0:	a6e1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%a3
+     dc4:	a4a1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d2
+     dc8:	aee1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%sp
+     dcc:	a293 a6c2      	macw %d2u,%a2u,>>,%a3@,%d1
+     dd0:	a6d3 a6c2      	macw %d2u,%a2u,>>,%a3@,%a3
+     dd4:	a493 a6c2      	macw %d2u,%a2u,>>,%a3@,%d2
+     dd8:	aed3 a6c2      	macw %d2u,%a2u,>>,%a3@,%sp
+     ddc:	a293 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d1
+     de0:	a6d3 a6e2      	macw %d2u,%a2u,>>,%a3@&,%a3
+     de4:	a493 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d2
+     de8:	aed3 a6e2      	macw %d2u,%a2u,>>,%a3@&,%sp
+     dec:	a29a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d1
+     df0:	a6da a6c2      	macw %d2u,%a2u,>>,%a2@\+,%a3
+     df4:	a49a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d2
+     df8:	aeda a6c2      	macw %d2u,%a2u,>>,%a2@\+,%sp
+     dfc:	a29a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d1
+     e00:	a6da a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%a3
+     e04:	a49a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d2
+     e08:	aeda a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%sp
+     e0c:	a2ae a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1
+     e12:	a6ee a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3
+     e18:	a4ae a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2
+     e1e:	aeee a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp
+     e24:	a2ae a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1
+     e2a:	a6ee a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3
+     e30:	a4ae a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2
+     e36:	aeee a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp
+     e3c:	a2a1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d1
+     e40:	a6e1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%a3
+     e44:	a4a1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d2
+     e48:	aee1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%sp
+     e4c:	a2a1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d1
+     e50:	a6e1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%a3
+     e54:	a4a1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d2
+     e58:	aee1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%sp
+     e5c:	a293 a2c2      	macw %d2u,%a2u,<<,%a3@,%d1
+     e60:	a6d3 a2c2      	macw %d2u,%a2u,<<,%a3@,%a3
+     e64:	a493 a2c2      	macw %d2u,%a2u,<<,%a3@,%d2
+     e68:	aed3 a2c2      	macw %d2u,%a2u,<<,%a3@,%sp
+     e6c:	a293 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d1
+     e70:	a6d3 a2e2      	macw %d2u,%a2u,<<,%a3@&,%a3
+     e74:	a493 a2e2      	macw %d2u,%a2u,<<,%a3@&,%d2
+     e78:	aed3 a2e2      	macw %d2u,%a2u,<<,%a3@&,%sp
+     e7c:	a29a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d1
+     e80:	a6da a2c2      	macw %d2u,%a2u,<<,%a2@\+,%a3
+     e84:	a49a a2c2      	macw %d2u,%a2u,<<,%a2@\+,%d2
+     e88:	aeda a2c2      	macw %d2u,%a2u,<<,%a2@\+,%sp
+     e8c:	a29a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d1
+     e90:	a6da a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%a3
+     e94:	a49a a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%d2
+     e98:	aeda a2e2      	macw %d2u,%a2u,<<,%a2@\+&,%sp
+     e9c:	a2ae a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d1
+     ea2:	a6ee a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%a3
+     ea8:	a4ae a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%d2
+     eae:	aeee a2c2 000a 	macw %d2u,%a2u,<<,%fp@\(10\),%sp
+     eb4:	a2ae a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d1
+     eba:	a6ee a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%a3
+     ec0:	a4ae a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%d2
+     ec6:	aeee a2e2 000a 	macw %d2u,%a2u,<<,%fp@\(10\)&,%sp
+     ecc:	a2a1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d1
+     ed0:	a6e1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%a3
+     ed4:	a4a1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%d2
+     ed8:	aee1 a2c2      	macw %d2u,%a2u,<<,%a1@-,%sp
+     edc:	a2a1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d1
+     ee0:	a6e1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%a3
+     ee4:	a4a1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%d2
+     ee8:	aee1 a2e2      	macw %d2u,%a2u,<<,%a1@-&,%sp
+     eec:	a293 a6c2      	macw %d2u,%a2u,>>,%a3@,%d1
+     ef0:	a6d3 a6c2      	macw %d2u,%a2u,>>,%a3@,%a3
+     ef4:	a493 a6c2      	macw %d2u,%a2u,>>,%a3@,%d2
+     ef8:	aed3 a6c2      	macw %d2u,%a2u,>>,%a3@,%sp
+     efc:	a293 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d1
+     f00:	a6d3 a6e2      	macw %d2u,%a2u,>>,%a3@&,%a3
+     f04:	a493 a6e2      	macw %d2u,%a2u,>>,%a3@&,%d2
+     f08:	aed3 a6e2      	macw %d2u,%a2u,>>,%a3@&,%sp
+     f0c:	a29a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d1
+     f10:	a6da a6c2      	macw %d2u,%a2u,>>,%a2@\+,%a3
+     f14:	a49a a6c2      	macw %d2u,%a2u,>>,%a2@\+,%d2
+     f18:	aeda a6c2      	macw %d2u,%a2u,>>,%a2@\+,%sp
+     f1c:	a29a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d1
+     f20:	a6da a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%a3
+     f24:	a49a a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%d2
+     f28:	aeda a6e2      	macw %d2u,%a2u,>>,%a2@\+&,%sp
+     f2c:	a2ae a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d1
+     f32:	a6ee a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%a3
+     f38:	a4ae a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%d2
+     f3e:	aeee a6c2 000a 	macw %d2u,%a2u,>>,%fp@\(10\),%sp
+     f44:	a2ae a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d1
+     f4a:	a6ee a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%a3
+     f50:	a4ae a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%d2
+     f56:	aeee a6e2 000a 	macw %d2u,%a2u,>>,%fp@\(10\)&,%sp
+     f5c:	a2a1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d1
+     f60:	a6e1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%a3
+     f64:	a4a1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%d2
+     f68:	aee1 a6c2      	macw %d2u,%a2u,>>,%a1@-,%sp
+     f6c:	a2a1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d1
+     f70:	a6e1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%a3
+     f74:	a4a1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%d2
+     f78:	aee1 a6e2      	macw %d2u,%a2u,>>,%a1@-&,%sp
+     f7c:	a293 3042      	macw %d2u,%d3l,%a3@,%d1
+     f80:	a6d3 3042      	macw %d2u,%d3l,%a3@,%a3
+     f84:	a493 3042      	macw %d2u,%d3l,%a3@,%d2
+     f88:	aed3 3042      	macw %d2u,%d3l,%a3@,%sp
+     f8c:	a293 3062      	macw %d2u,%d3l,%a3@&,%d1
+     f90:	a6d3 3062      	macw %d2u,%d3l,%a3@&,%a3
+     f94:	a493 3062      	macw %d2u,%d3l,%a3@&,%d2
+     f98:	aed3 3062      	macw %d2u,%d3l,%a3@&,%sp
+     f9c:	a29a 3042      	macw %d2u,%d3l,%a2@\+,%d1
+     fa0:	a6da 3042      	macw %d2u,%d3l,%a2@\+,%a3
+     fa4:	a49a 3042      	macw %d2u,%d3l,%a2@\+,%d2
+     fa8:	aeda 3042      	macw %d2u,%d3l,%a2@\+,%sp
+     fac:	a29a 3062      	macw %d2u,%d3l,%a2@\+&,%d1
+     fb0:	a6da 3062      	macw %d2u,%d3l,%a2@\+&,%a3
+     fb4:	a49a 3062      	macw %d2u,%d3l,%a2@\+&,%d2
+     fb8:	aeda 3062      	macw %d2u,%d3l,%a2@\+&,%sp
+     fbc:	a2ae 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%d1
+     fc2:	a6ee 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%a3
+     fc8:	a4ae 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%d2
+     fce:	aeee 3042 000a 	macw %d2u,%d3l,%fp@\(10\),%sp
+     fd4:	a2ae 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d1
+     fda:	a6ee 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%a3
+     fe0:	a4ae 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%d2
+     fe6:	aeee 3062 000a 	macw %d2u,%d3l,%fp@\(10\)&,%sp
+     fec:	a2a1 3042      	macw %d2u,%d3l,%a1@-,%d1
+     ff0:	a6e1 3042      	macw %d2u,%d3l,%a1@-,%a3
+     ff4:	a4a1 3042      	macw %d2u,%d3l,%a1@-,%d2
+     ff8:	aee1 3042      	macw %d2u,%d3l,%a1@-,%sp
+     ffc:	a2a1 3062      	macw %d2u,%d3l,%a1@-&,%d1
+    1000:	a6e1 3062      	macw %d2u,%d3l,%a1@-&,%a3
+    1004:	a4a1 3062      	macw %d2u,%d3l,%a1@-&,%d2
+    1008:	aee1 3062      	macw %d2u,%d3l,%a1@-&,%sp
+    100c:	a293 3242      	macw %d2u,%d3l,<<,%a3@,%d1
+    1010:	a6d3 3242      	macw %d2u,%d3l,<<,%a3@,%a3
+    1014:	a493 3242      	macw %d2u,%d3l,<<,%a3@,%d2
+    1018:	aed3 3242      	macw %d2u,%d3l,<<,%a3@,%sp
+    101c:	a293 3262      	macw %d2u,%d3l,<<,%a3@&,%d1
+    1020:	a6d3 3262      	macw %d2u,%d3l,<<,%a3@&,%a3
+    1024:	a493 3262      	macw %d2u,%d3l,<<,%a3@&,%d2
+    1028:	aed3 3262      	macw %d2u,%d3l,<<,%a3@&,%sp
+    102c:	a29a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d1
+    1030:	a6da 3242      	macw %d2u,%d3l,<<,%a2@\+,%a3
+    1034:	a49a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d2
+    1038:	aeda 3242      	macw %d2u,%d3l,<<,%a2@\+,%sp
+    103c:	a29a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d1
+    1040:	a6da 3262      	macw %d2u,%d3l,<<,%a2@\+&,%a3
+    1044:	a49a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d2
+    1048:	aeda 3262      	macw %d2u,%d3l,<<,%a2@\+&,%sp
+    104c:	a2ae 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1
+    1052:	a6ee 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3
+    1058:	a4ae 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2
+    105e:	aeee 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp
+    1064:	a2ae 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1
+    106a:	a6ee 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3
+    1070:	a4ae 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2
+    1076:	aeee 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp
+    107c:	a2a1 3242      	macw %d2u,%d3l,<<,%a1@-,%d1
+    1080:	a6e1 3242      	macw %d2u,%d3l,<<,%a1@-,%a3
+    1084:	a4a1 3242      	macw %d2u,%d3l,<<,%a1@-,%d2
+    1088:	aee1 3242      	macw %d2u,%d3l,<<,%a1@-,%sp
+    108c:	a2a1 3262      	macw %d2u,%d3l,<<,%a1@-&,%d1
+    1090:	a6e1 3262      	macw %d2u,%d3l,<<,%a1@-&,%a3
+    1094:	a4a1 3262      	macw %d2u,%d3l,<<,%a1@-&,%d2
+    1098:	aee1 3262      	macw %d2u,%d3l,<<,%a1@-&,%sp
+    109c:	a293 3642      	macw %d2u,%d3l,>>,%a3@,%d1
+    10a0:	a6d3 3642      	macw %d2u,%d3l,>>,%a3@,%a3
+    10a4:	a493 3642      	macw %d2u,%d3l,>>,%a3@,%d2
+    10a8:	aed3 3642      	macw %d2u,%d3l,>>,%a3@,%sp
+    10ac:	a293 3662      	macw %d2u,%d3l,>>,%a3@&,%d1
+    10b0:	a6d3 3662      	macw %d2u,%d3l,>>,%a3@&,%a3
+    10b4:	a493 3662      	macw %d2u,%d3l,>>,%a3@&,%d2
+    10b8:	aed3 3662      	macw %d2u,%d3l,>>,%a3@&,%sp
+    10bc:	a29a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d1
+    10c0:	a6da 3642      	macw %d2u,%d3l,>>,%a2@\+,%a3
+    10c4:	a49a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d2
+    10c8:	aeda 3642      	macw %d2u,%d3l,>>,%a2@\+,%sp
+    10cc:	a29a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d1
+    10d0:	a6da 3662      	macw %d2u,%d3l,>>,%a2@\+&,%a3
+    10d4:	a49a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d2
+    10d8:	aeda 3662      	macw %d2u,%d3l,>>,%a2@\+&,%sp
+    10dc:	a2ae 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1
+    10e2:	a6ee 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3
+    10e8:	a4ae 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2
+    10ee:	aeee 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp
+    10f4:	a2ae 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1
+    10fa:	a6ee 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3
+    1100:	a4ae 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2
+    1106:	aeee 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp
+    110c:	a2a1 3642      	macw %d2u,%d3l,>>,%a1@-,%d1
+    1110:	a6e1 3642      	macw %d2u,%d3l,>>,%a1@-,%a3
+    1114:	a4a1 3642      	macw %d2u,%d3l,>>,%a1@-,%d2
+    1118:	aee1 3642      	macw %d2u,%d3l,>>,%a1@-,%sp
+    111c:	a2a1 3662      	macw %d2u,%d3l,>>,%a1@-&,%d1
+    1120:	a6e1 3662      	macw %d2u,%d3l,>>,%a1@-&,%a3
+    1124:	a4a1 3662      	macw %d2u,%d3l,>>,%a1@-&,%d2
+    1128:	aee1 3662      	macw %d2u,%d3l,>>,%a1@-&,%sp
+    112c:	a293 3242      	macw %d2u,%d3l,<<,%a3@,%d1
+    1130:	a6d3 3242      	macw %d2u,%d3l,<<,%a3@,%a3
+    1134:	a493 3242      	macw %d2u,%d3l,<<,%a3@,%d2
+    1138:	aed3 3242      	macw %d2u,%d3l,<<,%a3@,%sp
+    113c:	a293 3262      	macw %d2u,%d3l,<<,%a3@&,%d1
+    1140:	a6d3 3262      	macw %d2u,%d3l,<<,%a3@&,%a3
+    1144:	a493 3262      	macw %d2u,%d3l,<<,%a3@&,%d2
+    1148:	aed3 3262      	macw %d2u,%d3l,<<,%a3@&,%sp
+    114c:	a29a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d1
+    1150:	a6da 3242      	macw %d2u,%d3l,<<,%a2@\+,%a3
+    1154:	a49a 3242      	macw %d2u,%d3l,<<,%a2@\+,%d2
+    1158:	aeda 3242      	macw %d2u,%d3l,<<,%a2@\+,%sp
+    115c:	a29a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d1
+    1160:	a6da 3262      	macw %d2u,%d3l,<<,%a2@\+&,%a3
+    1164:	a49a 3262      	macw %d2u,%d3l,<<,%a2@\+&,%d2
+    1168:	aeda 3262      	macw %d2u,%d3l,<<,%a2@\+&,%sp
+    116c:	a2ae 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d1
+    1172:	a6ee 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%a3
+    1178:	a4ae 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%d2
+    117e:	aeee 3242 000a 	macw %d2u,%d3l,<<,%fp@\(10\),%sp
+    1184:	a2ae 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d1
+    118a:	a6ee 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%a3
+    1190:	a4ae 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%d2
+    1196:	aeee 3262 000a 	macw %d2u,%d3l,<<,%fp@\(10\)&,%sp
+    119c:	a2a1 3242      	macw %d2u,%d3l,<<,%a1@-,%d1
+    11a0:	a6e1 3242      	macw %d2u,%d3l,<<,%a1@-,%a3
+    11a4:	a4a1 3242      	macw %d2u,%d3l,<<,%a1@-,%d2
+    11a8:	aee1 3242      	macw %d2u,%d3l,<<,%a1@-,%sp
+    11ac:	a2a1 3262      	macw %d2u,%d3l,<<,%a1@-&,%d1
+    11b0:	a6e1 3262      	macw %d2u,%d3l,<<,%a1@-&,%a3
+    11b4:	a4a1 3262      	macw %d2u,%d3l,<<,%a1@-&,%d2
+    11b8:	aee1 3262      	macw %d2u,%d3l,<<,%a1@-&,%sp
+    11bc:	a293 3642      	macw %d2u,%d3l,>>,%a3@,%d1
+    11c0:	a6d3 3642      	macw %d2u,%d3l,>>,%a3@,%a3
+    11c4:	a493 3642      	macw %d2u,%d3l,>>,%a3@,%d2
+    11c8:	aed3 3642      	macw %d2u,%d3l,>>,%a3@,%sp
+    11cc:	a293 3662      	macw %d2u,%d3l,>>,%a3@&,%d1
+    11d0:	a6d3 3662      	macw %d2u,%d3l,>>,%a3@&,%a3
+    11d4:	a493 3662      	macw %d2u,%d3l,>>,%a3@&,%d2
+    11d8:	aed3 3662      	macw %d2u,%d3l,>>,%a3@&,%sp
+    11dc:	a29a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d1
+    11e0:	a6da 3642      	macw %d2u,%d3l,>>,%a2@\+,%a3
+    11e4:	a49a 3642      	macw %d2u,%d3l,>>,%a2@\+,%d2
+    11e8:	aeda 3642      	macw %d2u,%d3l,>>,%a2@\+,%sp
+    11ec:	a29a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d1
+    11f0:	a6da 3662      	macw %d2u,%d3l,>>,%a2@\+&,%a3
+    11f4:	a49a 3662      	macw %d2u,%d3l,>>,%a2@\+&,%d2
+    11f8:	aeda 3662      	macw %d2u,%d3l,>>,%a2@\+&,%sp
+    11fc:	a2ae 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d1
+    1202:	a6ee 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%a3
+    1208:	a4ae 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%d2
+    120e:	aeee 3642 000a 	macw %d2u,%d3l,>>,%fp@\(10\),%sp
+    1214:	a2ae 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d1
+    121a:	a6ee 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%a3
+    1220:	a4ae 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%d2
+    1226:	aeee 3662 000a 	macw %d2u,%d3l,>>,%fp@\(10\)&,%sp
+    122c:	a2a1 3642      	macw %d2u,%d3l,>>,%a1@-,%d1
+    1230:	a6e1 3642      	macw %d2u,%d3l,>>,%a1@-,%a3
+    1234:	a4a1 3642      	macw %d2u,%d3l,>>,%a1@-,%d2
+    1238:	aee1 3642      	macw %d2u,%d3l,>>,%a1@-,%sp
+    123c:	a2a1 3662      	macw %d2u,%d3l,>>,%a1@-&,%d1
+    1240:	a6e1 3662      	macw %d2u,%d3l,>>,%a1@-&,%a3
+    1244:	a4a1 3662      	macw %d2u,%d3l,>>,%a1@-&,%d2
+    1248:	aee1 3662      	macw %d2u,%d3l,>>,%a1@-&,%sp
+    124c:	a293 f0c2      	macw %d2u,%a7u,%a3@,%d1
+    1250:	a6d3 f0c2      	macw %d2u,%a7u,%a3@,%a3
+    1254:	a493 f0c2      	macw %d2u,%a7u,%a3@,%d2
+    1258:	aed3 f0c2      	macw %d2u,%a7u,%a3@,%sp
+    125c:	a293 f0e2      	macw %d2u,%a7u,%a3@&,%d1
+    1260:	a6d3 f0e2      	macw %d2u,%a7u,%a3@&,%a3
+    1264:	a493 f0e2      	macw %d2u,%a7u,%a3@&,%d2
+    1268:	aed3 f0e2      	macw %d2u,%a7u,%a3@&,%sp
+    126c:	a29a f0c2      	macw %d2u,%a7u,%a2@\+,%d1
+    1270:	a6da f0c2      	macw %d2u,%a7u,%a2@\+,%a3
+    1274:	a49a f0c2      	macw %d2u,%a7u,%a2@\+,%d2
+    1278:	aeda f0c2      	macw %d2u,%a7u,%a2@\+,%sp
+    127c:	a29a f0e2      	macw %d2u,%a7u,%a2@\+&,%d1
+    1280:	a6da f0e2      	macw %d2u,%a7u,%a2@\+&,%a3
+    1284:	a49a f0e2      	macw %d2u,%a7u,%a2@\+&,%d2
+    1288:	aeda f0e2      	macw %d2u,%a7u,%a2@\+&,%sp
+    128c:	a2ae f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%d1
+    1292:	a6ee f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%a3
+    1298:	a4ae f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%d2
+    129e:	aeee f0c2 000a 	macw %d2u,%a7u,%fp@\(10\),%sp
+    12a4:	a2ae f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d1
+    12aa:	a6ee f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%a3
+    12b0:	a4ae f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%d2
+    12b6:	aeee f0e2 000a 	macw %d2u,%a7u,%fp@\(10\)&,%sp
+    12bc:	a2a1 f0c2      	macw %d2u,%a7u,%a1@-,%d1
+    12c0:	a6e1 f0c2      	macw %d2u,%a7u,%a1@-,%a3
+    12c4:	a4a1 f0c2      	macw %d2u,%a7u,%a1@-,%d2
+    12c8:	aee1 f0c2      	macw %d2u,%a7u,%a1@-,%sp
+    12cc:	a2a1 f0e2      	macw %d2u,%a7u,%a1@-&,%d1
+    12d0:	a6e1 f0e2      	macw %d2u,%a7u,%a1@-&,%a3
+    12d4:	a4a1 f0e2      	macw %d2u,%a7u,%a1@-&,%d2
+    12d8:	aee1 f0e2      	macw %d2u,%a7u,%a1@-&,%sp
+    12dc:	a293 f2c2      	macw %d2u,%a7u,<<,%a3@,%d1
+    12e0:	a6d3 f2c2      	macw %d2u,%a7u,<<,%a3@,%a3
+    12e4:	a493 f2c2      	macw %d2u,%a7u,<<,%a3@,%d2
+    12e8:	aed3 f2c2      	macw %d2u,%a7u,<<,%a3@,%sp
+    12ec:	a293 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d1
+    12f0:	a6d3 f2e2      	macw %d2u,%a7u,<<,%a3@&,%a3
+    12f4:	a493 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d2
+    12f8:	aed3 f2e2      	macw %d2u,%a7u,<<,%a3@&,%sp
+    12fc:	a29a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d1
+    1300:	a6da f2c2      	macw %d2u,%a7u,<<,%a2@\+,%a3
+    1304:	a49a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d2
+    1308:	aeda f2c2      	macw %d2u,%a7u,<<,%a2@\+,%sp
+    130c:	a29a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d1
+    1310:	a6da f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%a3
+    1314:	a49a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d2
+    1318:	aeda f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%sp
+    131c:	a2ae f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1
+    1322:	a6ee f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3
+    1328:	a4ae f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2
+    132e:	aeee f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp
+    1334:	a2ae f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1
+    133a:	a6ee f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3
+    1340:	a4ae f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2
+    1346:	aeee f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp
+    134c:	a2a1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d1
+    1350:	a6e1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%a3
+    1354:	a4a1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d2
+    1358:	aee1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%sp
+    135c:	a2a1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d1
+    1360:	a6e1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%a3
+    1364:	a4a1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d2
+    1368:	aee1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%sp
+    136c:	a293 f6c2      	macw %d2u,%a7u,>>,%a3@,%d1
+    1370:	a6d3 f6c2      	macw %d2u,%a7u,>>,%a3@,%a3
+    1374:	a493 f6c2      	macw %d2u,%a7u,>>,%a3@,%d2
+    1378:	aed3 f6c2      	macw %d2u,%a7u,>>,%a3@,%sp
+    137c:	a293 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d1
+    1380:	a6d3 f6e2      	macw %d2u,%a7u,>>,%a3@&,%a3
+    1384:	a493 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d2
+    1388:	aed3 f6e2      	macw %d2u,%a7u,>>,%a3@&,%sp
+    138c:	a29a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d1
+    1390:	a6da f6c2      	macw %d2u,%a7u,>>,%a2@\+,%a3
+    1394:	a49a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d2
+    1398:	aeda f6c2      	macw %d2u,%a7u,>>,%a2@\+,%sp
+    139c:	a29a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d1
+    13a0:	a6da f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%a3
+    13a4:	a49a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d2
+    13a8:	aeda f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%sp
+    13ac:	a2ae f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1
+    13b2:	a6ee f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3
+    13b8:	a4ae f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2
+    13be:	aeee f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp
+    13c4:	a2ae f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1
+    13ca:	a6ee f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3
+    13d0:	a4ae f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2
+    13d6:	aeee f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp
+    13dc:	a2a1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d1
+    13e0:	a6e1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%a3
+    13e4:	a4a1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d2
+    13e8:	aee1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%sp
+    13ec:	a2a1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d1
+    13f0:	a6e1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%a3
+    13f4:	a4a1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d2
+    13f8:	aee1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%sp
+    13fc:	a293 f2c2      	macw %d2u,%a7u,<<,%a3@,%d1
+    1400:	a6d3 f2c2      	macw %d2u,%a7u,<<,%a3@,%a3
+    1404:	a493 f2c2      	macw %d2u,%a7u,<<,%a3@,%d2
+    1408:	aed3 f2c2      	macw %d2u,%a7u,<<,%a3@,%sp
+    140c:	a293 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d1
+    1410:	a6d3 f2e2      	macw %d2u,%a7u,<<,%a3@&,%a3
+    1414:	a493 f2e2      	macw %d2u,%a7u,<<,%a3@&,%d2
+    1418:	aed3 f2e2      	macw %d2u,%a7u,<<,%a3@&,%sp
+    141c:	a29a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d1
+    1420:	a6da f2c2      	macw %d2u,%a7u,<<,%a2@\+,%a3
+    1424:	a49a f2c2      	macw %d2u,%a7u,<<,%a2@\+,%d2
+    1428:	aeda f2c2      	macw %d2u,%a7u,<<,%a2@\+,%sp
+    142c:	a29a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d1
+    1430:	a6da f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%a3
+    1434:	a49a f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%d2
+    1438:	aeda f2e2      	macw %d2u,%a7u,<<,%a2@\+&,%sp
+    143c:	a2ae f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d1
+    1442:	a6ee f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%a3
+    1448:	a4ae f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%d2
+    144e:	aeee f2c2 000a 	macw %d2u,%a7u,<<,%fp@\(10\),%sp
+    1454:	a2ae f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d1
+    145a:	a6ee f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%a3
+    1460:	a4ae f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%d2
+    1466:	aeee f2e2 000a 	macw %d2u,%a7u,<<,%fp@\(10\)&,%sp
+    146c:	a2a1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d1
+    1470:	a6e1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%a3
+    1474:	a4a1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%d2
+    1478:	aee1 f2c2      	macw %d2u,%a7u,<<,%a1@-,%sp
+    147c:	a2a1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d1
+    1480:	a6e1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%a3
+    1484:	a4a1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%d2
+    1488:	aee1 f2e2      	macw %d2u,%a7u,<<,%a1@-&,%sp
+    148c:	a293 f6c2      	macw %d2u,%a7u,>>,%a3@,%d1
+    1490:	a6d3 f6c2      	macw %d2u,%a7u,>>,%a3@,%a3
+    1494:	a493 f6c2      	macw %d2u,%a7u,>>,%a3@,%d2
+    1498:	aed3 f6c2      	macw %d2u,%a7u,>>,%a3@,%sp
+    149c:	a293 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d1
+    14a0:	a6d3 f6e2      	macw %d2u,%a7u,>>,%a3@&,%a3
+    14a4:	a493 f6e2      	macw %d2u,%a7u,>>,%a3@&,%d2
+    14a8:	aed3 f6e2      	macw %d2u,%a7u,>>,%a3@&,%sp
+    14ac:	a29a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d1
+    14b0:	a6da f6c2      	macw %d2u,%a7u,>>,%a2@\+,%a3
+    14b4:	a49a f6c2      	macw %d2u,%a7u,>>,%a2@\+,%d2
+    14b8:	aeda f6c2      	macw %d2u,%a7u,>>,%a2@\+,%sp
+    14bc:	a29a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d1
+    14c0:	a6da f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%a3
+    14c4:	a49a f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%d2
+    14c8:	aeda f6e2      	macw %d2u,%a7u,>>,%a2@\+&,%sp
+    14cc:	a2ae f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d1
+    14d2:	a6ee f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%a3
+    14d8:	a4ae f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%d2
+    14de:	aeee f6c2 000a 	macw %d2u,%a7u,>>,%fp@\(10\),%sp
+    14e4:	a2ae f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d1
+    14ea:	a6ee f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%a3
+    14f0:	a4ae f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%d2
+    14f6:	aeee f6e2 000a 	macw %d2u,%a7u,>>,%fp@\(10\)&,%sp
+    14fc:	a2a1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d1
+    1500:	a6e1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%a3
+    1504:	a4a1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%d2
+    1508:	aee1 f6c2      	macw %d2u,%a7u,>>,%a1@-,%sp
+    150c:	a2a1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d1
+    1510:	a6e1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%a3
+    1514:	a4a1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%d2
+    1518:	aee1 f6e2      	macw %d2u,%a7u,>>,%a1@-&,%sp
+    151c:	a293 1042      	macw %d2u,%d1l,%a3@,%d1
+    1520:	a6d3 1042      	macw %d2u,%d1l,%a3@,%a3
+    1524:	a493 1042      	macw %d2u,%d1l,%a3@,%d2
+    1528:	aed3 1042      	macw %d2u,%d1l,%a3@,%sp
+    152c:	a293 1062      	macw %d2u,%d1l,%a3@&,%d1
+    1530:	a6d3 1062      	macw %d2u,%d1l,%a3@&,%a3
+    1534:	a493 1062      	macw %d2u,%d1l,%a3@&,%d2
+    1538:	aed3 1062      	macw %d2u,%d1l,%a3@&,%sp
+    153c:	a29a 1042      	macw %d2u,%d1l,%a2@\+,%d1
+    1540:	a6da 1042      	macw %d2u,%d1l,%a2@\+,%a3
+    1544:	a49a 1042      	macw %d2u,%d1l,%a2@\+,%d2
+    1548:	aeda 1042      	macw %d2u,%d1l,%a2@\+,%sp
+    154c:	a29a 1062      	macw %d2u,%d1l,%a2@\+&,%d1
+    1550:	a6da 1062      	macw %d2u,%d1l,%a2@\+&,%a3
+    1554:	a49a 1062      	macw %d2u,%d1l,%a2@\+&,%d2
+    1558:	aeda 1062      	macw %d2u,%d1l,%a2@\+&,%sp
+    155c:	a2ae 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%d1
+    1562:	a6ee 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%a3
+    1568:	a4ae 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%d2
+    156e:	aeee 1042 000a 	macw %d2u,%d1l,%fp@\(10\),%sp
+    1574:	a2ae 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d1
+    157a:	a6ee 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%a3
+    1580:	a4ae 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%d2
+    1586:	aeee 1062 000a 	macw %d2u,%d1l,%fp@\(10\)&,%sp
+    158c:	a2a1 1042      	macw %d2u,%d1l,%a1@-,%d1
+    1590:	a6e1 1042      	macw %d2u,%d1l,%a1@-,%a3
+    1594:	a4a1 1042      	macw %d2u,%d1l,%a1@-,%d2
+    1598:	aee1 1042      	macw %d2u,%d1l,%a1@-,%sp
+    159c:	a2a1 1062      	macw %d2u,%d1l,%a1@-&,%d1
+    15a0:	a6e1 1062      	macw %d2u,%d1l,%a1@-&,%a3
+    15a4:	a4a1 1062      	macw %d2u,%d1l,%a1@-&,%d2
+    15a8:	aee1 1062      	macw %d2u,%d1l,%a1@-&,%sp
+    15ac:	a293 1242      	macw %d2u,%d1l,<<,%a3@,%d1
+    15b0:	a6d3 1242      	macw %d2u,%d1l,<<,%a3@,%a3
+    15b4:	a493 1242      	macw %d2u,%d1l,<<,%a3@,%d2
+    15b8:	aed3 1242      	macw %d2u,%d1l,<<,%a3@,%sp
+    15bc:	a293 1262      	macw %d2u,%d1l,<<,%a3@&,%d1
+    15c0:	a6d3 1262      	macw %d2u,%d1l,<<,%a3@&,%a3
+    15c4:	a493 1262      	macw %d2u,%d1l,<<,%a3@&,%d2
+    15c8:	aed3 1262      	macw %d2u,%d1l,<<,%a3@&,%sp
+    15cc:	a29a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d1
+    15d0:	a6da 1242      	macw %d2u,%d1l,<<,%a2@\+,%a3
+    15d4:	a49a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d2
+    15d8:	aeda 1242      	macw %d2u,%d1l,<<,%a2@\+,%sp
+    15dc:	a29a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d1
+    15e0:	a6da 1262      	macw %d2u,%d1l,<<,%a2@\+&,%a3
+    15e4:	a49a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d2
+    15e8:	aeda 1262      	macw %d2u,%d1l,<<,%a2@\+&,%sp
+    15ec:	a2ae 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1
+    15f2:	a6ee 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3
+    15f8:	a4ae 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2
+    15fe:	aeee 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp
+    1604:	a2ae 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1
+    160a:	a6ee 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3
+    1610:	a4ae 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2
+    1616:	aeee 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp
+    161c:	a2a1 1242      	macw %d2u,%d1l,<<,%a1@-,%d1
+    1620:	a6e1 1242      	macw %d2u,%d1l,<<,%a1@-,%a3
+    1624:	a4a1 1242      	macw %d2u,%d1l,<<,%a1@-,%d2
+    1628:	aee1 1242      	macw %d2u,%d1l,<<,%a1@-,%sp
+    162c:	a2a1 1262      	macw %d2u,%d1l,<<,%a1@-&,%d1
+    1630:	a6e1 1262      	macw %d2u,%d1l,<<,%a1@-&,%a3
+    1634:	a4a1 1262      	macw %d2u,%d1l,<<,%a1@-&,%d2
+    1638:	aee1 1262      	macw %d2u,%d1l,<<,%a1@-&,%sp
+    163c:	a293 1642      	macw %d2u,%d1l,>>,%a3@,%d1
+    1640:	a6d3 1642      	macw %d2u,%d1l,>>,%a3@,%a3
+    1644:	a493 1642      	macw %d2u,%d1l,>>,%a3@,%d2
+    1648:	aed3 1642      	macw %d2u,%d1l,>>,%a3@,%sp
+    164c:	a293 1662      	macw %d2u,%d1l,>>,%a3@&,%d1
+    1650:	a6d3 1662      	macw %d2u,%d1l,>>,%a3@&,%a3
+    1654:	a493 1662      	macw %d2u,%d1l,>>,%a3@&,%d2
+    1658:	aed3 1662      	macw %d2u,%d1l,>>,%a3@&,%sp
+    165c:	a29a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d1
+    1660:	a6da 1642      	macw %d2u,%d1l,>>,%a2@\+,%a3
+    1664:	a49a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d2
+    1668:	aeda 1642      	macw %d2u,%d1l,>>,%a2@\+,%sp
+    166c:	a29a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d1
+    1670:	a6da 1662      	macw %d2u,%d1l,>>,%a2@\+&,%a3
+    1674:	a49a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d2
+    1678:	aeda 1662      	macw %d2u,%d1l,>>,%a2@\+&,%sp
+    167c:	a2ae 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1
+    1682:	a6ee 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3
+    1688:	a4ae 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2
+    168e:	aeee 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp
+    1694:	a2ae 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1
+    169a:	a6ee 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3
+    16a0:	a4ae 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2
+    16a6:	aeee 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp
+    16ac:	a2a1 1642      	macw %d2u,%d1l,>>,%a1@-,%d1
+    16b0:	a6e1 1642      	macw %d2u,%d1l,>>,%a1@-,%a3
+    16b4:	a4a1 1642      	macw %d2u,%d1l,>>,%a1@-,%d2
+    16b8:	aee1 1642      	macw %d2u,%d1l,>>,%a1@-,%sp
+    16bc:	a2a1 1662      	macw %d2u,%d1l,>>,%a1@-&,%d1
+    16c0:	a6e1 1662      	macw %d2u,%d1l,>>,%a1@-&,%a3
+    16c4:	a4a1 1662      	macw %d2u,%d1l,>>,%a1@-&,%d2
+    16c8:	aee1 1662      	macw %d2u,%d1l,>>,%a1@-&,%sp
+    16cc:	a293 1242      	macw %d2u,%d1l,<<,%a3@,%d1
+    16d0:	a6d3 1242      	macw %d2u,%d1l,<<,%a3@,%a3
+    16d4:	a493 1242      	macw %d2u,%d1l,<<,%a3@,%d2
+    16d8:	aed3 1242      	macw %d2u,%d1l,<<,%a3@,%sp
+    16dc:	a293 1262      	macw %d2u,%d1l,<<,%a3@&,%d1
+    16e0:	a6d3 1262      	macw %d2u,%d1l,<<,%a3@&,%a3
+    16e4:	a493 1262      	macw %d2u,%d1l,<<,%a3@&,%d2
+    16e8:	aed3 1262      	macw %d2u,%d1l,<<,%a3@&,%sp
+    16ec:	a29a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d1
+    16f0:	a6da 1242      	macw %d2u,%d1l,<<,%a2@\+,%a3
+    16f4:	a49a 1242      	macw %d2u,%d1l,<<,%a2@\+,%d2
+    16f8:	aeda 1242      	macw %d2u,%d1l,<<,%a2@\+,%sp
+    16fc:	a29a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d1
+    1700:	a6da 1262      	macw %d2u,%d1l,<<,%a2@\+&,%a3
+    1704:	a49a 1262      	macw %d2u,%d1l,<<,%a2@\+&,%d2
+    1708:	aeda 1262      	macw %d2u,%d1l,<<,%a2@\+&,%sp
+    170c:	a2ae 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d1
+    1712:	a6ee 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%a3
+    1718:	a4ae 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%d2
+    171e:	aeee 1242 000a 	macw %d2u,%d1l,<<,%fp@\(10\),%sp
+    1724:	a2ae 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d1
+    172a:	a6ee 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%a3
+    1730:	a4ae 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%d2
+    1736:	aeee 1262 000a 	macw %d2u,%d1l,<<,%fp@\(10\)&,%sp
+    173c:	a2a1 1242      	macw %d2u,%d1l,<<,%a1@-,%d1
+    1740:	a6e1 1242      	macw %d2u,%d1l,<<,%a1@-,%a3
+    1744:	a4a1 1242      	macw %d2u,%d1l,<<,%a1@-,%d2
+    1748:	aee1 1242      	macw %d2u,%d1l,<<,%a1@-,%sp
+    174c:	a2a1 1262      	macw %d2u,%d1l,<<,%a1@-&,%d1
+    1750:	a6e1 1262      	macw %d2u,%d1l,<<,%a1@-&,%a3
+    1754:	a4a1 1262      	macw %d2u,%d1l,<<,%a1@-&,%d2
+    1758:	aee1 1262      	macw %d2u,%d1l,<<,%a1@-&,%sp
+    175c:	a293 1642      	macw %d2u,%d1l,>>,%a3@,%d1
+    1760:	a6d3 1642      	macw %d2u,%d1l,>>,%a3@,%a3
+    1764:	a493 1642      	macw %d2u,%d1l,>>,%a3@,%d2
+    1768:	aed3 1642      	macw %d2u,%d1l,>>,%a3@,%sp
+    176c:	a293 1662      	macw %d2u,%d1l,>>,%a3@&,%d1
+    1770:	a6d3 1662      	macw %d2u,%d1l,>>,%a3@&,%a3
+    1774:	a493 1662      	macw %d2u,%d1l,>>,%a3@&,%d2
+    1778:	aed3 1662      	macw %d2u,%d1l,>>,%a3@&,%sp
+    177c:	a29a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d1
+    1780:	a6da 1642      	macw %d2u,%d1l,>>,%a2@\+,%a3
+    1784:	a49a 1642      	macw %d2u,%d1l,>>,%a2@\+,%d2
+    1788:	aeda 1642      	macw %d2u,%d1l,>>,%a2@\+,%sp
+    178c:	a29a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d1
+    1790:	a6da 1662      	macw %d2u,%d1l,>>,%a2@\+&,%a3
+    1794:	a49a 1662      	macw %d2u,%d1l,>>,%a2@\+&,%d2
+    1798:	aeda 1662      	macw %d2u,%d1l,>>,%a2@\+&,%sp
+    179c:	a2ae 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d1
+    17a2:	a6ee 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%a3
+    17a8:	a4ae 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%d2
+    17ae:	aeee 1642 000a 	macw %d2u,%d1l,>>,%fp@\(10\),%sp
+    17b4:	a2ae 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d1
+    17ba:	a6ee 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%a3
+    17c0:	a4ae 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%d2
+    17c6:	aeee 1662 000a 	macw %d2u,%d1l,>>,%fp@\(10\)&,%sp
+    17cc:	a2a1 1642      	macw %d2u,%d1l,>>,%a1@-,%d1
+    17d0:	a6e1 1642      	macw %d2u,%d1l,>>,%a1@-,%a3
+    17d4:	a4a1 1642      	macw %d2u,%d1l,>>,%a1@-,%d2
+    17d8:	aee1 1642      	macw %d2u,%d1l,>>,%a1@-,%sp
+    17dc:	a2a1 1662      	macw %d2u,%d1l,>>,%a1@-&,%d1
+    17e0:	a6e1 1662      	macw %d2u,%d1l,>>,%a1@-&,%a3
+    17e4:	a4a1 1662      	macw %d2u,%d1l,>>,%a1@-&,%d2
+    17e8:	aee1 1662      	macw %d2u,%d1l,>>,%a1@-&,%sp
+    17ec:	a293 a08d      	macw %a5l,%a2u,%a3@,%d1
+    17f0:	a6d3 a08d      	macw %a5l,%a2u,%a3@,%a3
+    17f4:	a493 a08d      	macw %a5l,%a2u,%a3@,%d2
+    17f8:	aed3 a08d      	macw %a5l,%a2u,%a3@,%sp
+    17fc:	a293 a0ad      	macw %a5l,%a2u,%a3@&,%d1
+    1800:	a6d3 a0ad      	macw %a5l,%a2u,%a3@&,%a3
+    1804:	a493 a0ad      	macw %a5l,%a2u,%a3@&,%d2
+    1808:	aed3 a0ad      	macw %a5l,%a2u,%a3@&,%sp
+    180c:	a29a a08d      	macw %a5l,%a2u,%a2@\+,%d1
+    1810:	a6da a08d      	macw %a5l,%a2u,%a2@\+,%a3
+    1814:	a49a a08d      	macw %a5l,%a2u,%a2@\+,%d2
+    1818:	aeda a08d      	macw %a5l,%a2u,%a2@\+,%sp
+    181c:	a29a a0ad      	macw %a5l,%a2u,%a2@\+&,%d1
+    1820:	a6da a0ad      	macw %a5l,%a2u,%a2@\+&,%a3
+    1824:	a49a a0ad      	macw %a5l,%a2u,%a2@\+&,%d2
+    1828:	aeda a0ad      	macw %a5l,%a2u,%a2@\+&,%sp
+    182c:	a2ae a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%d1
+    1832:	a6ee a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%a3
+    1838:	a4ae a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%d2
+    183e:	aeee a08d 000a 	macw %a5l,%a2u,%fp@\(10\),%sp
+    1844:	a2ae a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d1
+    184a:	a6ee a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%a3
+    1850:	a4ae a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%d2
+    1856:	aeee a0ad 000a 	macw %a5l,%a2u,%fp@\(10\)&,%sp
+    185c:	a2a1 a08d      	macw %a5l,%a2u,%a1@-,%d1
+    1860:	a6e1 a08d      	macw %a5l,%a2u,%a1@-,%a3
+    1864:	a4a1 a08d      	macw %a5l,%a2u,%a1@-,%d2
+    1868:	aee1 a08d      	macw %a5l,%a2u,%a1@-,%sp
+    186c:	a2a1 a0ad      	macw %a5l,%a2u,%a1@-&,%d1
+    1870:	a6e1 a0ad      	macw %a5l,%a2u,%a1@-&,%a3
+    1874:	a4a1 a0ad      	macw %a5l,%a2u,%a1@-&,%d2
+    1878:	aee1 a0ad      	macw %a5l,%a2u,%a1@-&,%sp
+    187c:	a293 a28d      	macw %a5l,%a2u,<<,%a3@,%d1
+    1880:	a6d3 a28d      	macw %a5l,%a2u,<<,%a3@,%a3
+    1884:	a493 a28d      	macw %a5l,%a2u,<<,%a3@,%d2
+    1888:	aed3 a28d      	macw %a5l,%a2u,<<,%a3@,%sp
+    188c:	a293 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d1
+    1890:	a6d3 a2ad      	macw %a5l,%a2u,<<,%a3@&,%a3
+    1894:	a493 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d2
+    1898:	aed3 a2ad      	macw %a5l,%a2u,<<,%a3@&,%sp
+    189c:	a29a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d1
+    18a0:	a6da a28d      	macw %a5l,%a2u,<<,%a2@\+,%a3
+    18a4:	a49a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d2
+    18a8:	aeda a28d      	macw %a5l,%a2u,<<,%a2@\+,%sp
+    18ac:	a29a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d1
+    18b0:	a6da a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%a3
+    18b4:	a49a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d2
+    18b8:	aeda a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%sp
+    18bc:	a2ae a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1
+    18c2:	a6ee a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3
+    18c8:	a4ae a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2
+    18ce:	aeee a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp
+    18d4:	a2ae a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1
+    18da:	a6ee a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3
+    18e0:	a4ae a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2
+    18e6:	aeee a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp
+    18ec:	a2a1 a28d      	macw %a5l,%a2u,<<,%a1@-,%d1
+    18f0:	a6e1 a28d      	macw %a5l,%a2u,<<,%a1@-,%a3
+    18f4:	a4a1 a28d      	macw %a5l,%a2u,<<,%a1@-,%d2
+    18f8:	aee1 a28d      	macw %a5l,%a2u,<<,%a1@-,%sp
+    18fc:	a2a1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d1
+    1900:	a6e1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%a3
+    1904:	a4a1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d2
+    1908:	aee1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%sp
+    190c:	a293 a68d      	macw %a5l,%a2u,>>,%a3@,%d1
+    1910:	a6d3 a68d      	macw %a5l,%a2u,>>,%a3@,%a3
+    1914:	a493 a68d      	macw %a5l,%a2u,>>,%a3@,%d2
+    1918:	aed3 a68d      	macw %a5l,%a2u,>>,%a3@,%sp
+    191c:	a293 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d1
+    1920:	a6d3 a6ad      	macw %a5l,%a2u,>>,%a3@&,%a3
+    1924:	a493 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d2
+    1928:	aed3 a6ad      	macw %a5l,%a2u,>>,%a3@&,%sp
+    192c:	a29a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d1
+    1930:	a6da a68d      	macw %a5l,%a2u,>>,%a2@\+,%a3
+    1934:	a49a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d2
+    1938:	aeda a68d      	macw %a5l,%a2u,>>,%a2@\+,%sp
+    193c:	a29a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d1
+    1940:	a6da a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%a3
+    1944:	a49a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d2
+    1948:	aeda a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%sp
+    194c:	a2ae a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1
+    1952:	a6ee a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3
+    1958:	a4ae a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2
+    195e:	aeee a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp
+    1964:	a2ae a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1
+    196a:	a6ee a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3
+    1970:	a4ae a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2
+    1976:	aeee a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp
+    197c:	a2a1 a68d      	macw %a5l,%a2u,>>,%a1@-,%d1
+    1980:	a6e1 a68d      	macw %a5l,%a2u,>>,%a1@-,%a3
+    1984:	a4a1 a68d      	macw %a5l,%a2u,>>,%a1@-,%d2
+    1988:	aee1 a68d      	macw %a5l,%a2u,>>,%a1@-,%sp
+    198c:	a2a1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d1
+    1990:	a6e1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%a3
+    1994:	a4a1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d2
+    1998:	aee1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%sp
+    199c:	a293 a28d      	macw %a5l,%a2u,<<,%a3@,%d1
+    19a0:	a6d3 a28d      	macw %a5l,%a2u,<<,%a3@,%a3
+    19a4:	a493 a28d      	macw %a5l,%a2u,<<,%a3@,%d2
+    19a8:	aed3 a28d      	macw %a5l,%a2u,<<,%a3@,%sp
+    19ac:	a293 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d1
+    19b0:	a6d3 a2ad      	macw %a5l,%a2u,<<,%a3@&,%a3
+    19b4:	a493 a2ad      	macw %a5l,%a2u,<<,%a3@&,%d2
+    19b8:	aed3 a2ad      	macw %a5l,%a2u,<<,%a3@&,%sp
+    19bc:	a29a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d1
+    19c0:	a6da a28d      	macw %a5l,%a2u,<<,%a2@\+,%a3
+    19c4:	a49a a28d      	macw %a5l,%a2u,<<,%a2@\+,%d2
+    19c8:	aeda a28d      	macw %a5l,%a2u,<<,%a2@\+,%sp
+    19cc:	a29a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d1
+    19d0:	a6da a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%a3
+    19d4:	a49a a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%d2
+    19d8:	aeda a2ad      	macw %a5l,%a2u,<<,%a2@\+&,%sp
+    19dc:	a2ae a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d1
+    19e2:	a6ee a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%a3
+    19e8:	a4ae a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%d2
+    19ee:	aeee a28d 000a 	macw %a5l,%a2u,<<,%fp@\(10\),%sp
+    19f4:	a2ae a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d1
+    19fa:	a6ee a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%a3
+    1a00:	a4ae a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%d2
+    1a06:	aeee a2ad 000a 	macw %a5l,%a2u,<<,%fp@\(10\)&,%sp
+    1a0c:	a2a1 a28d      	macw %a5l,%a2u,<<,%a1@-,%d1
+    1a10:	a6e1 a28d      	macw %a5l,%a2u,<<,%a1@-,%a3
+    1a14:	a4a1 a28d      	macw %a5l,%a2u,<<,%a1@-,%d2
+    1a18:	aee1 a28d      	macw %a5l,%a2u,<<,%a1@-,%sp
+    1a1c:	a2a1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d1
+    1a20:	a6e1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%a3
+    1a24:	a4a1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%d2
+    1a28:	aee1 a2ad      	macw %a5l,%a2u,<<,%a1@-&,%sp
+    1a2c:	a293 a68d      	macw %a5l,%a2u,>>,%a3@,%d1
+    1a30:	a6d3 a68d      	macw %a5l,%a2u,>>,%a3@,%a3
+    1a34:	a493 a68d      	macw %a5l,%a2u,>>,%a3@,%d2
+    1a38:	aed3 a68d      	macw %a5l,%a2u,>>,%a3@,%sp
+    1a3c:	a293 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d1
+    1a40:	a6d3 a6ad      	macw %a5l,%a2u,>>,%a3@&,%a3
+    1a44:	a493 a6ad      	macw %a5l,%a2u,>>,%a3@&,%d2
+    1a48:	aed3 a6ad      	macw %a5l,%a2u,>>,%a3@&,%sp
+    1a4c:	a29a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d1
+    1a50:	a6da a68d      	macw %a5l,%a2u,>>,%a2@\+,%a3
+    1a54:	a49a a68d      	macw %a5l,%a2u,>>,%a2@\+,%d2
+    1a58:	aeda a68d      	macw %a5l,%a2u,>>,%a2@\+,%sp
+    1a5c:	a29a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d1
+    1a60:	a6da a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%a3
+    1a64:	a49a a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%d2
+    1a68:	aeda a6ad      	macw %a5l,%a2u,>>,%a2@\+&,%sp
+    1a6c:	a2ae a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d1
+    1a72:	a6ee a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%a3
+    1a78:	a4ae a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%d2
+    1a7e:	aeee a68d 000a 	macw %a5l,%a2u,>>,%fp@\(10\),%sp
+    1a84:	a2ae a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d1
+    1a8a:	a6ee a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%a3
+    1a90:	a4ae a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%d2
+    1a96:	aeee a6ad 000a 	macw %a5l,%a2u,>>,%fp@\(10\)&,%sp
+    1a9c:	a2a1 a68d      	macw %a5l,%a2u,>>,%a1@-,%d1
+    1aa0:	a6e1 a68d      	macw %a5l,%a2u,>>,%a1@-,%a3
+    1aa4:	a4a1 a68d      	macw %a5l,%a2u,>>,%a1@-,%d2
+    1aa8:	aee1 a68d      	macw %a5l,%a2u,>>,%a1@-,%sp
+    1aac:	a2a1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d1
+    1ab0:	a6e1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%a3
+    1ab4:	a4a1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%d2
+    1ab8:	aee1 a6ad      	macw %a5l,%a2u,>>,%a1@-&,%sp
+    1abc:	a293 300d      	macw %a5l,%d3l,%a3@,%d1
+    1ac0:	a6d3 300d      	macw %a5l,%d3l,%a3@,%a3
+    1ac4:	a493 300d      	macw %a5l,%d3l,%a3@,%d2
+    1ac8:	aed3 300d      	macw %a5l,%d3l,%a3@,%sp
+    1acc:	a293 302d      	macw %a5l,%d3l,%a3@&,%d1
+    1ad0:	a6d3 302d      	macw %a5l,%d3l,%a3@&,%a3
+    1ad4:	a493 302d      	macw %a5l,%d3l,%a3@&,%d2
+    1ad8:	aed3 302d      	macw %a5l,%d3l,%a3@&,%sp
+    1adc:	a29a 300d      	macw %a5l,%d3l,%a2@\+,%d1
+    1ae0:	a6da 300d      	macw %a5l,%d3l,%a2@\+,%a3
+    1ae4:	a49a 300d      	macw %a5l,%d3l,%a2@\+,%d2
+    1ae8:	aeda 300d      	macw %a5l,%d3l,%a2@\+,%sp
+    1aec:	a29a 302d      	macw %a5l,%d3l,%a2@\+&,%d1
+    1af0:	a6da 302d      	macw %a5l,%d3l,%a2@\+&,%a3
+    1af4:	a49a 302d      	macw %a5l,%d3l,%a2@\+&,%d2
+    1af8:	aeda 302d      	macw %a5l,%d3l,%a2@\+&,%sp
+    1afc:	a2ae 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%d1
+    1b02:	a6ee 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%a3
+    1b08:	a4ae 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%d2
+    1b0e:	aeee 300d 000a 	macw %a5l,%d3l,%fp@\(10\),%sp
+    1b14:	a2ae 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d1
+    1b1a:	a6ee 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%a3
+    1b20:	a4ae 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%d2
+    1b26:	aeee 302d 000a 	macw %a5l,%d3l,%fp@\(10\)&,%sp
+    1b2c:	a2a1 300d      	macw %a5l,%d3l,%a1@-,%d1
+    1b30:	a6e1 300d      	macw %a5l,%d3l,%a1@-,%a3
+    1b34:	a4a1 300d      	macw %a5l,%d3l,%a1@-,%d2
+    1b38:	aee1 300d      	macw %a5l,%d3l,%a1@-,%sp
+    1b3c:	a2a1 302d      	macw %a5l,%d3l,%a1@-&,%d1
+    1b40:	a6e1 302d      	macw %a5l,%d3l,%a1@-&,%a3
+    1b44:	a4a1 302d      	macw %a5l,%d3l,%a1@-&,%d2
+    1b48:	aee1 302d      	macw %a5l,%d3l,%a1@-&,%sp
+    1b4c:	a293 320d      	macw %a5l,%d3l,<<,%a3@,%d1
+    1b50:	a6d3 320d      	macw %a5l,%d3l,<<,%a3@,%a3
+    1b54:	a493 320d      	macw %a5l,%d3l,<<,%a3@,%d2
+    1b58:	aed3 320d      	macw %a5l,%d3l,<<,%a3@,%sp
+    1b5c:	a293 322d      	macw %a5l,%d3l,<<,%a3@&,%d1
+    1b60:	a6d3 322d      	macw %a5l,%d3l,<<,%a3@&,%a3
+    1b64:	a493 322d      	macw %a5l,%d3l,<<,%a3@&,%d2
+    1b68:	aed3 322d      	macw %a5l,%d3l,<<,%a3@&,%sp
+    1b6c:	a29a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d1
+    1b70:	a6da 320d      	macw %a5l,%d3l,<<,%a2@\+,%a3
+    1b74:	a49a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d2
+    1b78:	aeda 320d      	macw %a5l,%d3l,<<,%a2@\+,%sp
+    1b7c:	a29a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d1
+    1b80:	a6da 322d      	macw %a5l,%d3l,<<,%a2@\+&,%a3
+    1b84:	a49a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d2
+    1b88:	aeda 322d      	macw %a5l,%d3l,<<,%a2@\+&,%sp
+    1b8c:	a2ae 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1
+    1b92:	a6ee 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3
+    1b98:	a4ae 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2
+    1b9e:	aeee 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp
+    1ba4:	a2ae 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1
+    1baa:	a6ee 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3
+    1bb0:	a4ae 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2
+    1bb6:	aeee 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp
+    1bbc:	a2a1 320d      	macw %a5l,%d3l,<<,%a1@-,%d1
+    1bc0:	a6e1 320d      	macw %a5l,%d3l,<<,%a1@-,%a3
+    1bc4:	a4a1 320d      	macw %a5l,%d3l,<<,%a1@-,%d2
+    1bc8:	aee1 320d      	macw %a5l,%d3l,<<,%a1@-,%sp
+    1bcc:	a2a1 322d      	macw %a5l,%d3l,<<,%a1@-&,%d1
+    1bd0:	a6e1 322d      	macw %a5l,%d3l,<<,%a1@-&,%a3
+    1bd4:	a4a1 322d      	macw %a5l,%d3l,<<,%a1@-&,%d2
+    1bd8:	aee1 322d      	macw %a5l,%d3l,<<,%a1@-&,%sp
+    1bdc:	a293 360d      	macw %a5l,%d3l,>>,%a3@,%d1
+    1be0:	a6d3 360d      	macw %a5l,%d3l,>>,%a3@,%a3
+    1be4:	a493 360d      	macw %a5l,%d3l,>>,%a3@,%d2
+    1be8:	aed3 360d      	macw %a5l,%d3l,>>,%a3@,%sp
+    1bec:	a293 362d      	macw %a5l,%d3l,>>,%a3@&,%d1
+    1bf0:	a6d3 362d      	macw %a5l,%d3l,>>,%a3@&,%a3
+    1bf4:	a493 362d      	macw %a5l,%d3l,>>,%a3@&,%d2
+    1bf8:	aed3 362d      	macw %a5l,%d3l,>>,%a3@&,%sp
+    1bfc:	a29a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d1
+    1c00:	a6da 360d      	macw %a5l,%d3l,>>,%a2@\+,%a3
+    1c04:	a49a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d2
+    1c08:	aeda 360d      	macw %a5l,%d3l,>>,%a2@\+,%sp
+    1c0c:	a29a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d1
+    1c10:	a6da 362d      	macw %a5l,%d3l,>>,%a2@\+&,%a3
+    1c14:	a49a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d2
+    1c18:	aeda 362d      	macw %a5l,%d3l,>>,%a2@\+&,%sp
+    1c1c:	a2ae 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1
+    1c22:	a6ee 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3
+    1c28:	a4ae 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2
+    1c2e:	aeee 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp
+    1c34:	a2ae 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1
+    1c3a:	a6ee 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3
+    1c40:	a4ae 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2
+    1c46:	aeee 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp
+    1c4c:	a2a1 360d      	macw %a5l,%d3l,>>,%a1@-,%d1
+    1c50:	a6e1 360d      	macw %a5l,%d3l,>>,%a1@-,%a3
+    1c54:	a4a1 360d      	macw %a5l,%d3l,>>,%a1@-,%d2
+    1c58:	aee1 360d      	macw %a5l,%d3l,>>,%a1@-,%sp
+    1c5c:	a2a1 362d      	macw %a5l,%d3l,>>,%a1@-&,%d1
+    1c60:	a6e1 362d      	macw %a5l,%d3l,>>,%a1@-&,%a3
+    1c64:	a4a1 362d      	macw %a5l,%d3l,>>,%a1@-&,%d2
+    1c68:	aee1 362d      	macw %a5l,%d3l,>>,%a1@-&,%sp
+    1c6c:	a293 320d      	macw %a5l,%d3l,<<,%a3@,%d1
+    1c70:	a6d3 320d      	macw %a5l,%d3l,<<,%a3@,%a3
+    1c74:	a493 320d      	macw %a5l,%d3l,<<,%a3@,%d2
+    1c78:	aed3 320d      	macw %a5l,%d3l,<<,%a3@,%sp
+    1c7c:	a293 322d      	macw %a5l,%d3l,<<,%a3@&,%d1
+    1c80:	a6d3 322d      	macw %a5l,%d3l,<<,%a3@&,%a3
+    1c84:	a493 322d      	macw %a5l,%d3l,<<,%a3@&,%d2
+    1c88:	aed3 322d      	macw %a5l,%d3l,<<,%a3@&,%sp
+    1c8c:	a29a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d1
+    1c90:	a6da 320d      	macw %a5l,%d3l,<<,%a2@\+,%a3
+    1c94:	a49a 320d      	macw %a5l,%d3l,<<,%a2@\+,%d2
+    1c98:	aeda 320d      	macw %a5l,%d3l,<<,%a2@\+,%sp
+    1c9c:	a29a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d1
+    1ca0:	a6da 322d      	macw %a5l,%d3l,<<,%a2@\+&,%a3
+    1ca4:	a49a 322d      	macw %a5l,%d3l,<<,%a2@\+&,%d2
+    1ca8:	aeda 322d      	macw %a5l,%d3l,<<,%a2@\+&,%sp
+    1cac:	a2ae 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d1
+    1cb2:	a6ee 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%a3
+    1cb8:	a4ae 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%d2
+    1cbe:	aeee 320d 000a 	macw %a5l,%d3l,<<,%fp@\(10\),%sp
+    1cc4:	a2ae 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d1
+    1cca:	a6ee 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%a3
+    1cd0:	a4ae 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%d2
+    1cd6:	aeee 322d 000a 	macw %a5l,%d3l,<<,%fp@\(10\)&,%sp
+    1cdc:	a2a1 320d      	macw %a5l,%d3l,<<,%a1@-,%d1
+    1ce0:	a6e1 320d      	macw %a5l,%d3l,<<,%a1@-,%a3
+    1ce4:	a4a1 320d      	macw %a5l,%d3l,<<,%a1@-,%d2
+    1ce8:	aee1 320d      	macw %a5l,%d3l,<<,%a1@-,%sp
+    1cec:	a2a1 322d      	macw %a5l,%d3l,<<,%a1@-&,%d1
+    1cf0:	a6e1 322d      	macw %a5l,%d3l,<<,%a1@-&,%a3
+    1cf4:	a4a1 322d      	macw %a5l,%d3l,<<,%a1@-&,%d2
+    1cf8:	aee1 322d      	macw %a5l,%d3l,<<,%a1@-&,%sp
+    1cfc:	a293 360d      	macw %a5l,%d3l,>>,%a3@,%d1
+    1d00:	a6d3 360d      	macw %a5l,%d3l,>>,%a3@,%a3
+    1d04:	a493 360d      	macw %a5l,%d3l,>>,%a3@,%d2
+    1d08:	aed3 360d      	macw %a5l,%d3l,>>,%a3@,%sp
+    1d0c:	a293 362d      	macw %a5l,%d3l,>>,%a3@&,%d1
+    1d10:	a6d3 362d      	macw %a5l,%d3l,>>,%a3@&,%a3
+    1d14:	a493 362d      	macw %a5l,%d3l,>>,%a3@&,%d2
+    1d18:	aed3 362d      	macw %a5l,%d3l,>>,%a3@&,%sp
+    1d1c:	a29a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d1
+    1d20:	a6da 360d      	macw %a5l,%d3l,>>,%a2@\+,%a3
+    1d24:	a49a 360d      	macw %a5l,%d3l,>>,%a2@\+,%d2
+    1d28:	aeda 360d      	macw %a5l,%d3l,>>,%a2@\+,%sp
+    1d2c:	a29a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d1
+    1d30:	a6da 362d      	macw %a5l,%d3l,>>,%a2@\+&,%a3
+    1d34:	a49a 362d      	macw %a5l,%d3l,>>,%a2@\+&,%d2
+    1d38:	aeda 362d      	macw %a5l,%d3l,>>,%a2@\+&,%sp
+    1d3c:	a2ae 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d1
+    1d42:	a6ee 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%a3
+    1d48:	a4ae 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%d2
+    1d4e:	aeee 360d 000a 	macw %a5l,%d3l,>>,%fp@\(10\),%sp
+    1d54:	a2ae 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d1
+    1d5a:	a6ee 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%a3
+    1d60:	a4ae 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%d2
+    1d66:	aeee 362d 000a 	macw %a5l,%d3l,>>,%fp@\(10\)&,%sp
+    1d6c:	a2a1 360d      	macw %a5l,%d3l,>>,%a1@-,%d1
+    1d70:	a6e1 360d      	macw %a5l,%d3l,>>,%a1@-,%a3
+    1d74:	a4a1 360d      	macw %a5l,%d3l,>>,%a1@-,%d2
+    1d78:	aee1 360d      	macw %a5l,%d3l,>>,%a1@-,%sp
+    1d7c:	a2a1 362d      	macw %a5l,%d3l,>>,%a1@-&,%d1
+    1d80:	a6e1 362d      	macw %a5l,%d3l,>>,%a1@-&,%a3
+    1d84:	a4a1 362d      	macw %a5l,%d3l,>>,%a1@-&,%d2
+    1d88:	aee1 362d      	macw %a5l,%d3l,>>,%a1@-&,%sp
+    1d8c:	a293 f08d      	macw %a5l,%a7u,%a3@,%d1
+    1d90:	a6d3 f08d      	macw %a5l,%a7u,%a3@,%a3
+    1d94:	a493 f08d      	macw %a5l,%a7u,%a3@,%d2
+    1d98:	aed3 f08d      	macw %a5l,%a7u,%a3@,%sp
+    1d9c:	a293 f0ad      	macw %a5l,%a7u,%a3@&,%d1
+    1da0:	a6d3 f0ad      	macw %a5l,%a7u,%a3@&,%a3
+    1da4:	a493 f0ad      	macw %a5l,%a7u,%a3@&,%d2
+    1da8:	aed3 f0ad      	macw %a5l,%a7u,%a3@&,%sp
+    1dac:	a29a f08d      	macw %a5l,%a7u,%a2@\+,%d1
+    1db0:	a6da f08d      	macw %a5l,%a7u,%a2@\+,%a3
+    1db4:	a49a f08d      	macw %a5l,%a7u,%a2@\+,%d2
+    1db8:	aeda f08d      	macw %a5l,%a7u,%a2@\+,%sp
+    1dbc:	a29a f0ad      	macw %a5l,%a7u,%a2@\+&,%d1
+    1dc0:	a6da f0ad      	macw %a5l,%a7u,%a2@\+&,%a3
+    1dc4:	a49a f0ad      	macw %a5l,%a7u,%a2@\+&,%d2
+    1dc8:	aeda f0ad      	macw %a5l,%a7u,%a2@\+&,%sp
+    1dcc:	a2ae f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%d1
+    1dd2:	a6ee f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%a3
+    1dd8:	a4ae f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%d2
+    1dde:	aeee f08d 000a 	macw %a5l,%a7u,%fp@\(10\),%sp
+    1de4:	a2ae f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d1
+    1dea:	a6ee f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%a3
+    1df0:	a4ae f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%d2
+    1df6:	aeee f0ad 000a 	macw %a5l,%a7u,%fp@\(10\)&,%sp
+    1dfc:	a2a1 f08d      	macw %a5l,%a7u,%a1@-,%d1
+    1e00:	a6e1 f08d      	macw %a5l,%a7u,%a1@-,%a3
+    1e04:	a4a1 f08d      	macw %a5l,%a7u,%a1@-,%d2
+    1e08:	aee1 f08d      	macw %a5l,%a7u,%a1@-,%sp
+    1e0c:	a2a1 f0ad      	macw %a5l,%a7u,%a1@-&,%d1
+    1e10:	a6e1 f0ad      	macw %a5l,%a7u,%a1@-&,%a3
+    1e14:	a4a1 f0ad      	macw %a5l,%a7u,%a1@-&,%d2
+    1e18:	aee1 f0ad      	macw %a5l,%a7u,%a1@-&,%sp
+    1e1c:	a293 f28d      	macw %a5l,%a7u,<<,%a3@,%d1
+    1e20:	a6d3 f28d      	macw %a5l,%a7u,<<,%a3@,%a3
+    1e24:	a493 f28d      	macw %a5l,%a7u,<<,%a3@,%d2
+    1e28:	aed3 f28d      	macw %a5l,%a7u,<<,%a3@,%sp
+    1e2c:	a293 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d1
+    1e30:	a6d3 f2ad      	macw %a5l,%a7u,<<,%a3@&,%a3
+    1e34:	a493 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d2
+    1e38:	aed3 f2ad      	macw %a5l,%a7u,<<,%a3@&,%sp
+    1e3c:	a29a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d1
+    1e40:	a6da f28d      	macw %a5l,%a7u,<<,%a2@\+,%a3
+    1e44:	a49a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d2
+    1e48:	aeda f28d      	macw %a5l,%a7u,<<,%a2@\+,%sp
+    1e4c:	a29a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d1
+    1e50:	a6da f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%a3
+    1e54:	a49a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d2
+    1e58:	aeda f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%sp
+    1e5c:	a2ae f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1
+    1e62:	a6ee f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3
+    1e68:	a4ae f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2
+    1e6e:	aeee f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp
+    1e74:	a2ae f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1
+    1e7a:	a6ee f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3
+    1e80:	a4ae f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2
+    1e86:	aeee f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp
+    1e8c:	a2a1 f28d      	macw %a5l,%a7u,<<,%a1@-,%d1
+    1e90:	a6e1 f28d      	macw %a5l,%a7u,<<,%a1@-,%a3
+    1e94:	a4a1 f28d      	macw %a5l,%a7u,<<,%a1@-,%d2
+    1e98:	aee1 f28d      	macw %a5l,%a7u,<<,%a1@-,%sp
+    1e9c:	a2a1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d1
+    1ea0:	a6e1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%a3
+    1ea4:	a4a1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d2
+    1ea8:	aee1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%sp
+    1eac:	a293 f68d      	macw %a5l,%a7u,>>,%a3@,%d1
+    1eb0:	a6d3 f68d      	macw %a5l,%a7u,>>,%a3@,%a3
+    1eb4:	a493 f68d      	macw %a5l,%a7u,>>,%a3@,%d2
+    1eb8:	aed3 f68d      	macw %a5l,%a7u,>>,%a3@,%sp
+    1ebc:	a293 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d1
+    1ec0:	a6d3 f6ad      	macw %a5l,%a7u,>>,%a3@&,%a3
+    1ec4:	a493 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d2
+    1ec8:	aed3 f6ad      	macw %a5l,%a7u,>>,%a3@&,%sp
+    1ecc:	a29a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d1
+    1ed0:	a6da f68d      	macw %a5l,%a7u,>>,%a2@\+,%a3
+    1ed4:	a49a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d2
+    1ed8:	aeda f68d      	macw %a5l,%a7u,>>,%a2@\+,%sp
+    1edc:	a29a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d1
+    1ee0:	a6da f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%a3
+    1ee4:	a49a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d2
+    1ee8:	aeda f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%sp
+    1eec:	a2ae f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1
+    1ef2:	a6ee f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3
+    1ef8:	a4ae f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2
+    1efe:	aeee f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp
+    1f04:	a2ae f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1
+    1f0a:	a6ee f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3
+    1f10:	a4ae f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2
+    1f16:	aeee f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp
+    1f1c:	a2a1 f68d      	macw %a5l,%a7u,>>,%a1@-,%d1
+    1f20:	a6e1 f68d      	macw %a5l,%a7u,>>,%a1@-,%a3
+    1f24:	a4a1 f68d      	macw %a5l,%a7u,>>,%a1@-,%d2
+    1f28:	aee1 f68d      	macw %a5l,%a7u,>>,%a1@-,%sp
+    1f2c:	a2a1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d1
+    1f30:	a6e1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%a3
+    1f34:	a4a1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d2
+    1f38:	aee1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%sp
+    1f3c:	a293 f28d      	macw %a5l,%a7u,<<,%a3@,%d1
+    1f40:	a6d3 f28d      	macw %a5l,%a7u,<<,%a3@,%a3
+    1f44:	a493 f28d      	macw %a5l,%a7u,<<,%a3@,%d2
+    1f48:	aed3 f28d      	macw %a5l,%a7u,<<,%a3@,%sp
+    1f4c:	a293 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d1
+    1f50:	a6d3 f2ad      	macw %a5l,%a7u,<<,%a3@&,%a3
+    1f54:	a493 f2ad      	macw %a5l,%a7u,<<,%a3@&,%d2
+    1f58:	aed3 f2ad      	macw %a5l,%a7u,<<,%a3@&,%sp
+    1f5c:	a29a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d1
+    1f60:	a6da f28d      	macw %a5l,%a7u,<<,%a2@\+,%a3
+    1f64:	a49a f28d      	macw %a5l,%a7u,<<,%a2@\+,%d2
+    1f68:	aeda f28d      	macw %a5l,%a7u,<<,%a2@\+,%sp
+    1f6c:	a29a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d1
+    1f70:	a6da f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%a3
+    1f74:	a49a f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%d2
+    1f78:	aeda f2ad      	macw %a5l,%a7u,<<,%a2@\+&,%sp
+    1f7c:	a2ae f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d1
+    1f82:	a6ee f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%a3
+    1f88:	a4ae f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%d2
+    1f8e:	aeee f28d 000a 	macw %a5l,%a7u,<<,%fp@\(10\),%sp
+    1f94:	a2ae f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d1
+    1f9a:	a6ee f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%a3
+    1fa0:	a4ae f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%d2
+    1fa6:	aeee f2ad 000a 	macw %a5l,%a7u,<<,%fp@\(10\)&,%sp
+    1fac:	a2a1 f28d      	macw %a5l,%a7u,<<,%a1@-,%d1
+    1fb0:	a6e1 f28d      	macw %a5l,%a7u,<<,%a1@-,%a3
+    1fb4:	a4a1 f28d      	macw %a5l,%a7u,<<,%a1@-,%d2
+    1fb8:	aee1 f28d      	macw %a5l,%a7u,<<,%a1@-,%sp
+    1fbc:	a2a1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d1
+    1fc0:	a6e1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%a3
+    1fc4:	a4a1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%d2
+    1fc8:	aee1 f2ad      	macw %a5l,%a7u,<<,%a1@-&,%sp
+    1fcc:	a293 f68d      	macw %a5l,%a7u,>>,%a3@,%d1
+    1fd0:	a6d3 f68d      	macw %a5l,%a7u,>>,%a3@,%a3
+    1fd4:	a493 f68d      	macw %a5l,%a7u,>>,%a3@,%d2
+    1fd8:	aed3 f68d      	macw %a5l,%a7u,>>,%a3@,%sp
+    1fdc:	a293 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d1
+    1fe0:	a6d3 f6ad      	macw %a5l,%a7u,>>,%a3@&,%a3
+    1fe4:	a493 f6ad      	macw %a5l,%a7u,>>,%a3@&,%d2
+    1fe8:	aed3 f6ad      	macw %a5l,%a7u,>>,%a3@&,%sp
+    1fec:	a29a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d1
+    1ff0:	a6da f68d      	macw %a5l,%a7u,>>,%a2@\+,%a3
+    1ff4:	a49a f68d      	macw %a5l,%a7u,>>,%a2@\+,%d2
+    1ff8:	aeda f68d      	macw %a5l,%a7u,>>,%a2@\+,%sp
+    1ffc:	a29a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d1
+    2000:	a6da f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%a3
+    2004:	a49a f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%d2
+    2008:	aeda f6ad      	macw %a5l,%a7u,>>,%a2@\+&,%sp
+    200c:	a2ae f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d1
+    2012:	a6ee f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%a3
+    2018:	a4ae f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%d2
+    201e:	aeee f68d 000a 	macw %a5l,%a7u,>>,%fp@\(10\),%sp
+    2024:	a2ae f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d1
+    202a:	a6ee f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%a3
+    2030:	a4ae f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%d2
+    2036:	aeee f6ad 000a 	macw %a5l,%a7u,>>,%fp@\(10\)&,%sp
+    203c:	a2a1 f68d      	macw %a5l,%a7u,>>,%a1@-,%d1
+    2040:	a6e1 f68d      	macw %a5l,%a7u,>>,%a1@-,%a3
+    2044:	a4a1 f68d      	macw %a5l,%a7u,>>,%a1@-,%d2
+    2048:	aee1 f68d      	macw %a5l,%a7u,>>,%a1@-,%sp
+    204c:	a2a1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d1
+    2050:	a6e1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%a3
+    2054:	a4a1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%d2
+    2058:	aee1 f6ad      	macw %a5l,%a7u,>>,%a1@-&,%sp
+    205c:	a293 100d      	macw %a5l,%d1l,%a3@,%d1
+    2060:	a6d3 100d      	macw %a5l,%d1l,%a3@,%a3
+    2064:	a493 100d      	macw %a5l,%d1l,%a3@,%d2
+    2068:	aed3 100d      	macw %a5l,%d1l,%a3@,%sp
+    206c:	a293 102d      	macw %a5l,%d1l,%a3@&,%d1
+    2070:	a6d3 102d      	macw %a5l,%d1l,%a3@&,%a3
+    2074:	a493 102d      	macw %a5l,%d1l,%a3@&,%d2
+    2078:	aed3 102d      	macw %a5l,%d1l,%a3@&,%sp
+    207c:	a29a 100d      	macw %a5l,%d1l,%a2@\+,%d1
+    2080:	a6da 100d      	macw %a5l,%d1l,%a2@\+,%a3
+    2084:	a49a 100d      	macw %a5l,%d1l,%a2@\+,%d2
+    2088:	aeda 100d      	macw %a5l,%d1l,%a2@\+,%sp
+    208c:	a29a 102d      	macw %a5l,%d1l,%a2@\+&,%d1
+    2090:	a6da 102d      	macw %a5l,%d1l,%a2@\+&,%a3
+    2094:	a49a 102d      	macw %a5l,%d1l,%a2@\+&,%d2
+    2098:	aeda 102d      	macw %a5l,%d1l,%a2@\+&,%sp
+    209c:	a2ae 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%d1
+    20a2:	a6ee 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%a3
+    20a8:	a4ae 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%d2
+    20ae:	aeee 100d 000a 	macw %a5l,%d1l,%fp@\(10\),%sp
+    20b4:	a2ae 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d1
+    20ba:	a6ee 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%a3
+    20c0:	a4ae 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%d2
+    20c6:	aeee 102d 000a 	macw %a5l,%d1l,%fp@\(10\)&,%sp
+    20cc:	a2a1 100d      	macw %a5l,%d1l,%a1@-,%d1
+    20d0:	a6e1 100d      	macw %a5l,%d1l,%a1@-,%a3
+    20d4:	a4a1 100d      	macw %a5l,%d1l,%a1@-,%d2
+    20d8:	aee1 100d      	macw %a5l,%d1l,%a1@-,%sp
+    20dc:	a2a1 102d      	macw %a5l,%d1l,%a1@-&,%d1
+    20e0:	a6e1 102d      	macw %a5l,%d1l,%a1@-&,%a3
+    20e4:	a4a1 102d      	macw %a5l,%d1l,%a1@-&,%d2
+    20e8:	aee1 102d      	macw %a5l,%d1l,%a1@-&,%sp
+    20ec:	a293 120d      	macw %a5l,%d1l,<<,%a3@,%d1
+    20f0:	a6d3 120d      	macw %a5l,%d1l,<<,%a3@,%a3
+    20f4:	a493 120d      	macw %a5l,%d1l,<<,%a3@,%d2
+    20f8:	aed3 120d      	macw %a5l,%d1l,<<,%a3@,%sp
+    20fc:	a293 122d      	macw %a5l,%d1l,<<,%a3@&,%d1
+    2100:	a6d3 122d      	macw %a5l,%d1l,<<,%a3@&,%a3
+    2104:	a493 122d      	macw %a5l,%d1l,<<,%a3@&,%d2
+    2108:	aed3 122d      	macw %a5l,%d1l,<<,%a3@&,%sp
+    210c:	a29a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d1
+    2110:	a6da 120d      	macw %a5l,%d1l,<<,%a2@\+,%a3
+    2114:	a49a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d2
+    2118:	aeda 120d      	macw %a5l,%d1l,<<,%a2@\+,%sp
+    211c:	a29a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d1
+    2120:	a6da 122d      	macw %a5l,%d1l,<<,%a2@\+&,%a3
+    2124:	a49a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d2
+    2128:	aeda 122d      	macw %a5l,%d1l,<<,%a2@\+&,%sp
+    212c:	a2ae 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1
+    2132:	a6ee 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3
+    2138:	a4ae 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2
+    213e:	aeee 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp
+    2144:	a2ae 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1
+    214a:	a6ee 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3
+    2150:	a4ae 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2
+    2156:	aeee 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp
+    215c:	a2a1 120d      	macw %a5l,%d1l,<<,%a1@-,%d1
+    2160:	a6e1 120d      	macw %a5l,%d1l,<<,%a1@-,%a3
+    2164:	a4a1 120d      	macw %a5l,%d1l,<<,%a1@-,%d2
+    2168:	aee1 120d      	macw %a5l,%d1l,<<,%a1@-,%sp
+    216c:	a2a1 122d      	macw %a5l,%d1l,<<,%a1@-&,%d1
+    2170:	a6e1 122d      	macw %a5l,%d1l,<<,%a1@-&,%a3
+    2174:	a4a1 122d      	macw %a5l,%d1l,<<,%a1@-&,%d2
+    2178:	aee1 122d      	macw %a5l,%d1l,<<,%a1@-&,%sp
+    217c:	a293 160d      	macw %a5l,%d1l,>>,%a3@,%d1
+    2180:	a6d3 160d      	macw %a5l,%d1l,>>,%a3@,%a3
+    2184:	a493 160d      	macw %a5l,%d1l,>>,%a3@,%d2
+    2188:	aed3 160d      	macw %a5l,%d1l,>>,%a3@,%sp
+    218c:	a293 162d      	macw %a5l,%d1l,>>,%a3@&,%d1
+    2190:	a6d3 162d      	macw %a5l,%d1l,>>,%a3@&,%a3
+    2194:	a493 162d      	macw %a5l,%d1l,>>,%a3@&,%d2
+    2198:	aed3 162d      	macw %a5l,%d1l,>>,%a3@&,%sp
+    219c:	a29a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d1
+    21a0:	a6da 160d      	macw %a5l,%d1l,>>,%a2@\+,%a3
+    21a4:	a49a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d2
+    21a8:	aeda 160d      	macw %a5l,%d1l,>>,%a2@\+,%sp
+    21ac:	a29a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d1
+    21b0:	a6da 162d      	macw %a5l,%d1l,>>,%a2@\+&,%a3
+    21b4:	a49a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d2
+    21b8:	aeda 162d      	macw %a5l,%d1l,>>,%a2@\+&,%sp
+    21bc:	a2ae 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1
+    21c2:	a6ee 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3
+    21c8:	a4ae 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2
+    21ce:	aeee 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp
+    21d4:	a2ae 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1
+    21da:	a6ee 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3
+    21e0:	a4ae 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2
+    21e6:	aeee 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp
+    21ec:	a2a1 160d      	macw %a5l,%d1l,>>,%a1@-,%d1
+    21f0:	a6e1 160d      	macw %a5l,%d1l,>>,%a1@-,%a3
+    21f4:	a4a1 160d      	macw %a5l,%d1l,>>,%a1@-,%d2
+    21f8:	aee1 160d      	macw %a5l,%d1l,>>,%a1@-,%sp
+    21fc:	a2a1 162d      	macw %a5l,%d1l,>>,%a1@-&,%d1
+    2200:	a6e1 162d      	macw %a5l,%d1l,>>,%a1@-&,%a3
+    2204:	a4a1 162d      	macw %a5l,%d1l,>>,%a1@-&,%d2
+    2208:	aee1 162d      	macw %a5l,%d1l,>>,%a1@-&,%sp
+    220c:	a293 120d      	macw %a5l,%d1l,<<,%a3@,%d1
+    2210:	a6d3 120d      	macw %a5l,%d1l,<<,%a3@,%a3
+    2214:	a493 120d      	macw %a5l,%d1l,<<,%a3@,%d2
+    2218:	aed3 120d      	macw %a5l,%d1l,<<,%a3@,%sp
+    221c:	a293 122d      	macw %a5l,%d1l,<<,%a3@&,%d1
+    2220:	a6d3 122d      	macw %a5l,%d1l,<<,%a3@&,%a3
+    2224:	a493 122d      	macw %a5l,%d1l,<<,%a3@&,%d2
+    2228:	aed3 122d      	macw %a5l,%d1l,<<,%a3@&,%sp
+    222c:	a29a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d1
+    2230:	a6da 120d      	macw %a5l,%d1l,<<,%a2@\+,%a3
+    2234:	a49a 120d      	macw %a5l,%d1l,<<,%a2@\+,%d2
+    2238:	aeda 120d      	macw %a5l,%d1l,<<,%a2@\+,%sp
+    223c:	a29a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d1
+    2240:	a6da 122d      	macw %a5l,%d1l,<<,%a2@\+&,%a3
+    2244:	a49a 122d      	macw %a5l,%d1l,<<,%a2@\+&,%d2
+    2248:	aeda 122d      	macw %a5l,%d1l,<<,%a2@\+&,%sp
+    224c:	a2ae 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d1
+    2252:	a6ee 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%a3
+    2258:	a4ae 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%d2
+    225e:	aeee 120d 000a 	macw %a5l,%d1l,<<,%fp@\(10\),%sp
+    2264:	a2ae 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d1
+    226a:	a6ee 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%a3
+    2270:	a4ae 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%d2
+    2276:	aeee 122d 000a 	macw %a5l,%d1l,<<,%fp@\(10\)&,%sp
+    227c:	a2a1 120d      	macw %a5l,%d1l,<<,%a1@-,%d1
+    2280:	a6e1 120d      	macw %a5l,%d1l,<<,%a1@-,%a3
+    2284:	a4a1 120d      	macw %a5l,%d1l,<<,%a1@-,%d2
+    2288:	aee1 120d      	macw %a5l,%d1l,<<,%a1@-,%sp
+    228c:	a2a1 122d      	macw %a5l,%d1l,<<,%a1@-&,%d1
+    2290:	a6e1 122d      	macw %a5l,%d1l,<<,%a1@-&,%a3
+    2294:	a4a1 122d      	macw %a5l,%d1l,<<,%a1@-&,%d2
+    2298:	aee1 122d      	macw %a5l,%d1l,<<,%a1@-&,%sp
+    229c:	a293 160d      	macw %a5l,%d1l,>>,%a3@,%d1
+    22a0:	a6d3 160d      	macw %a5l,%d1l,>>,%a3@,%a3
+    22a4:	a493 160d      	macw %a5l,%d1l,>>,%a3@,%d2
+    22a8:	aed3 160d      	macw %a5l,%d1l,>>,%a3@,%sp
+    22ac:	a293 162d      	macw %a5l,%d1l,>>,%a3@&,%d1
+    22b0:	a6d3 162d      	macw %a5l,%d1l,>>,%a3@&,%a3
+    22b4:	a493 162d      	macw %a5l,%d1l,>>,%a3@&,%d2
+    22b8:	aed3 162d      	macw %a5l,%d1l,>>,%a3@&,%sp
+    22bc:	a29a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d1
+    22c0:	a6da 160d      	macw %a5l,%d1l,>>,%a2@\+,%a3
+    22c4:	a49a 160d      	macw %a5l,%d1l,>>,%a2@\+,%d2
+    22c8:	aeda 160d      	macw %a5l,%d1l,>>,%a2@\+,%sp
+    22cc:	a29a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d1
+    22d0:	a6da 162d      	macw %a5l,%d1l,>>,%a2@\+&,%a3
+    22d4:	a49a 162d      	macw %a5l,%d1l,>>,%a2@\+&,%d2
+    22d8:	aeda 162d      	macw %a5l,%d1l,>>,%a2@\+&,%sp
+    22dc:	a2ae 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d1
+    22e2:	a6ee 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%a3
+    22e8:	a4ae 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%d2
+    22ee:	aeee 160d 000a 	macw %a5l,%d1l,>>,%fp@\(10\),%sp
+    22f4:	a2ae 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d1
+    22fa:	a6ee 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%a3
+    2300:	a4ae 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%d2
+    2306:	aeee 162d 000a 	macw %a5l,%d1l,>>,%fp@\(10\)&,%sp
+    230c:	a2a1 160d      	macw %a5l,%d1l,>>,%a1@-,%d1
+    2310:	a6e1 160d      	macw %a5l,%d1l,>>,%a1@-,%a3
+    2314:	a4a1 160d      	macw %a5l,%d1l,>>,%a1@-,%d2
+    2318:	aee1 160d      	macw %a5l,%d1l,>>,%a1@-,%sp
+    231c:	a2a1 162d      	macw %a5l,%d1l,>>,%a1@-&,%d1
+    2320:	a6e1 162d      	macw %a5l,%d1l,>>,%a1@-&,%a3
+    2324:	a4a1 162d      	macw %a5l,%d1l,>>,%a1@-&,%d2
+    2328:	aee1 162d      	macw %a5l,%d1l,>>,%a1@-&,%sp
+    232c:	a293 a0c6      	macw %d6u,%a2u,%a3@,%d1
+    2330:	a6d3 a0c6      	macw %d6u,%a2u,%a3@,%a3
+    2334:	a493 a0c6      	macw %d6u,%a2u,%a3@,%d2
+    2338:	aed3 a0c6      	macw %d6u,%a2u,%a3@,%sp
+    233c:	a293 a0e6      	macw %d6u,%a2u,%a3@&,%d1
+    2340:	a6d3 a0e6      	macw %d6u,%a2u,%a3@&,%a3
+    2344:	a493 a0e6      	macw %d6u,%a2u,%a3@&,%d2
+    2348:	aed3 a0e6      	macw %d6u,%a2u,%a3@&,%sp
+    234c:	a29a a0c6      	macw %d6u,%a2u,%a2@\+,%d1
+    2350:	a6da a0c6      	macw %d6u,%a2u,%a2@\+,%a3
+    2354:	a49a a0c6      	macw %d6u,%a2u,%a2@\+,%d2
+    2358:	aeda a0c6      	macw %d6u,%a2u,%a2@\+,%sp
+    235c:	a29a a0e6      	macw %d6u,%a2u,%a2@\+&,%d1
+    2360:	a6da a0e6      	macw %d6u,%a2u,%a2@\+&,%a3
+    2364:	a49a a0e6      	macw %d6u,%a2u,%a2@\+&,%d2
+    2368:	aeda a0e6      	macw %d6u,%a2u,%a2@\+&,%sp
+    236c:	a2ae a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%d1
+    2372:	a6ee a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%a3
+    2378:	a4ae a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%d2
+    237e:	aeee a0c6 000a 	macw %d6u,%a2u,%fp@\(10\),%sp
+    2384:	a2ae a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d1
+    238a:	a6ee a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%a3
+    2390:	a4ae a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%d2
+    2396:	aeee a0e6 000a 	macw %d6u,%a2u,%fp@\(10\)&,%sp
+    239c:	a2a1 a0c6      	macw %d6u,%a2u,%a1@-,%d1
+    23a0:	a6e1 a0c6      	macw %d6u,%a2u,%a1@-,%a3
+    23a4:	a4a1 a0c6      	macw %d6u,%a2u,%a1@-,%d2
+    23a8:	aee1 a0c6      	macw %d6u,%a2u,%a1@-,%sp
+    23ac:	a2a1 a0e6      	macw %d6u,%a2u,%a1@-&,%d1
+    23b0:	a6e1 a0e6      	macw %d6u,%a2u,%a1@-&,%a3
+    23b4:	a4a1 a0e6      	macw %d6u,%a2u,%a1@-&,%d2
+    23b8:	aee1 a0e6      	macw %d6u,%a2u,%a1@-&,%sp
+    23bc:	a293 a2c6      	macw %d6u,%a2u,<<,%a3@,%d1
+    23c0:	a6d3 a2c6      	macw %d6u,%a2u,<<,%a3@,%a3
+    23c4:	a493 a2c6      	macw %d6u,%a2u,<<,%a3@,%d2
+    23c8:	aed3 a2c6      	macw %d6u,%a2u,<<,%a3@,%sp
+    23cc:	a293 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d1
+    23d0:	a6d3 a2e6      	macw %d6u,%a2u,<<,%a3@&,%a3
+    23d4:	a493 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d2
+    23d8:	aed3 a2e6      	macw %d6u,%a2u,<<,%a3@&,%sp
+    23dc:	a29a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d1
+    23e0:	a6da a2c6      	macw %d6u,%a2u,<<,%a2@\+,%a3
+    23e4:	a49a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d2
+    23e8:	aeda a2c6      	macw %d6u,%a2u,<<,%a2@\+,%sp
+    23ec:	a29a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d1
+    23f0:	a6da a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%a3
+    23f4:	a49a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d2
+    23f8:	aeda a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%sp
+    23fc:	a2ae a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1
+    2402:	a6ee a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3
+    2408:	a4ae a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2
+    240e:	aeee a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp
+    2414:	a2ae a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1
+    241a:	a6ee a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3
+    2420:	a4ae a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2
+    2426:	aeee a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp
+    242c:	a2a1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d1
+    2430:	a6e1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%a3
+    2434:	a4a1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d2
+    2438:	aee1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%sp
+    243c:	a2a1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d1
+    2440:	a6e1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%a3
+    2444:	a4a1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d2
+    2448:	aee1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%sp
+    244c:	a293 a6c6      	macw %d6u,%a2u,>>,%a3@,%d1
+    2450:	a6d3 a6c6      	macw %d6u,%a2u,>>,%a3@,%a3
+    2454:	a493 a6c6      	macw %d6u,%a2u,>>,%a3@,%d2
+    2458:	aed3 a6c6      	macw %d6u,%a2u,>>,%a3@,%sp
+    245c:	a293 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d1
+    2460:	a6d3 a6e6      	macw %d6u,%a2u,>>,%a3@&,%a3
+    2464:	a493 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d2
+    2468:	aed3 a6e6      	macw %d6u,%a2u,>>,%a3@&,%sp
+    246c:	a29a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d1
+    2470:	a6da a6c6      	macw %d6u,%a2u,>>,%a2@\+,%a3
+    2474:	a49a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d2
+    2478:	aeda a6c6      	macw %d6u,%a2u,>>,%a2@\+,%sp
+    247c:	a29a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d1
+    2480:	a6da a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%a3
+    2484:	a49a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d2
+    2488:	aeda a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%sp
+    248c:	a2ae a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1
+    2492:	a6ee a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3
+    2498:	a4ae a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2
+    249e:	aeee a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp
+    24a4:	a2ae a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1
+    24aa:	a6ee a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3
+    24b0:	a4ae a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2
+    24b6:	aeee a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp
+    24bc:	a2a1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d1
+    24c0:	a6e1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%a3
+    24c4:	a4a1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d2
+    24c8:	aee1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%sp
+    24cc:	a2a1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d1
+    24d0:	a6e1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%a3
+    24d4:	a4a1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d2
+    24d8:	aee1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%sp
+    24dc:	a293 a2c6      	macw %d6u,%a2u,<<,%a3@,%d1
+    24e0:	a6d3 a2c6      	macw %d6u,%a2u,<<,%a3@,%a3
+    24e4:	a493 a2c6      	macw %d6u,%a2u,<<,%a3@,%d2
+    24e8:	aed3 a2c6      	macw %d6u,%a2u,<<,%a3@,%sp
+    24ec:	a293 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d1
+    24f0:	a6d3 a2e6      	macw %d6u,%a2u,<<,%a3@&,%a3
+    24f4:	a493 a2e6      	macw %d6u,%a2u,<<,%a3@&,%d2
+    24f8:	aed3 a2e6      	macw %d6u,%a2u,<<,%a3@&,%sp
+    24fc:	a29a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d1
+    2500:	a6da a2c6      	macw %d6u,%a2u,<<,%a2@\+,%a3
+    2504:	a49a a2c6      	macw %d6u,%a2u,<<,%a2@\+,%d2
+    2508:	aeda a2c6      	macw %d6u,%a2u,<<,%a2@\+,%sp
+    250c:	a29a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d1
+    2510:	a6da a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%a3
+    2514:	a49a a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%d2
+    2518:	aeda a2e6      	macw %d6u,%a2u,<<,%a2@\+&,%sp
+    251c:	a2ae a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d1
+    2522:	a6ee a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%a3
+    2528:	a4ae a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%d2
+    252e:	aeee a2c6 000a 	macw %d6u,%a2u,<<,%fp@\(10\),%sp
+    2534:	a2ae a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d1
+    253a:	a6ee a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%a3
+    2540:	a4ae a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%d2
+    2546:	aeee a2e6 000a 	macw %d6u,%a2u,<<,%fp@\(10\)&,%sp
+    254c:	a2a1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d1
+    2550:	a6e1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%a3
+    2554:	a4a1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%d2
+    2558:	aee1 a2c6      	macw %d6u,%a2u,<<,%a1@-,%sp
+    255c:	a2a1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d1
+    2560:	a6e1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%a3
+    2564:	a4a1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%d2
+    2568:	aee1 a2e6      	macw %d6u,%a2u,<<,%a1@-&,%sp
+    256c:	a293 a6c6      	macw %d6u,%a2u,>>,%a3@,%d1
+    2570:	a6d3 a6c6      	macw %d6u,%a2u,>>,%a3@,%a3
+    2574:	a493 a6c6      	macw %d6u,%a2u,>>,%a3@,%d2
+    2578:	aed3 a6c6      	macw %d6u,%a2u,>>,%a3@,%sp
+    257c:	a293 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d1
+    2580:	a6d3 a6e6      	macw %d6u,%a2u,>>,%a3@&,%a3
+    2584:	a493 a6e6      	macw %d6u,%a2u,>>,%a3@&,%d2
+    2588:	aed3 a6e6      	macw %d6u,%a2u,>>,%a3@&,%sp
+    258c:	a29a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d1
+    2590:	a6da a6c6      	macw %d6u,%a2u,>>,%a2@\+,%a3
+    2594:	a49a a6c6      	macw %d6u,%a2u,>>,%a2@\+,%d2
+    2598:	aeda a6c6      	macw %d6u,%a2u,>>,%a2@\+,%sp
+    259c:	a29a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d1
+    25a0:	a6da a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%a3
+    25a4:	a49a a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%d2
+    25a8:	aeda a6e6      	macw %d6u,%a2u,>>,%a2@\+&,%sp
+    25ac:	a2ae a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d1
+    25b2:	a6ee a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%a3
+    25b8:	a4ae a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%d2
+    25be:	aeee a6c6 000a 	macw %d6u,%a2u,>>,%fp@\(10\),%sp
+    25c4:	a2ae a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d1
+    25ca:	a6ee a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%a3
+    25d0:	a4ae a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%d2
+    25d6:	aeee a6e6 000a 	macw %d6u,%a2u,>>,%fp@\(10\)&,%sp
+    25dc:	a2a1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d1
+    25e0:	a6e1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%a3
+    25e4:	a4a1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%d2
+    25e8:	aee1 a6c6      	macw %d6u,%a2u,>>,%a1@-,%sp
+    25ec:	a2a1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d1
+    25f0:	a6e1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%a3
+    25f4:	a4a1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%d2
+    25f8:	aee1 a6e6      	macw %d6u,%a2u,>>,%a1@-&,%sp
+    25fc:	a293 3046      	macw %d6u,%d3l,%a3@,%d1
+    2600:	a6d3 3046      	macw %d6u,%d3l,%a3@,%a3
+    2604:	a493 3046      	macw %d6u,%d3l,%a3@,%d2
+    2608:	aed3 3046      	macw %d6u,%d3l,%a3@,%sp
+    260c:	a293 3066      	macw %d6u,%d3l,%a3@&,%d1
+    2610:	a6d3 3066      	macw %d6u,%d3l,%a3@&,%a3
+    2614:	a493 3066      	macw %d6u,%d3l,%a3@&,%d2
+    2618:	aed3 3066      	macw %d6u,%d3l,%a3@&,%sp
+    261c:	a29a 3046      	macw %d6u,%d3l,%a2@\+,%d1
+    2620:	a6da 3046      	macw %d6u,%d3l,%a2@\+,%a3
+    2624:	a49a 3046      	macw %d6u,%d3l,%a2@\+,%d2
+    2628:	aeda 3046      	macw %d6u,%d3l,%a2@\+,%sp
+    262c:	a29a 3066      	macw %d6u,%d3l,%a2@\+&,%d1
+    2630:	a6da 3066      	macw %d6u,%d3l,%a2@\+&,%a3
+    2634:	a49a 3066      	macw %d6u,%d3l,%a2@\+&,%d2
+    2638:	aeda 3066      	macw %d6u,%d3l,%a2@\+&,%sp
+    263c:	a2ae 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%d1
+    2642:	a6ee 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%a3
+    2648:	a4ae 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%d2
+    264e:	aeee 3046 000a 	macw %d6u,%d3l,%fp@\(10\),%sp
+    2654:	a2ae 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d1
+    265a:	a6ee 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%a3
+    2660:	a4ae 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%d2
+    2666:	aeee 3066 000a 	macw %d6u,%d3l,%fp@\(10\)&,%sp
+    266c:	a2a1 3046      	macw %d6u,%d3l,%a1@-,%d1
+    2670:	a6e1 3046      	macw %d6u,%d3l,%a1@-,%a3
+    2674:	a4a1 3046      	macw %d6u,%d3l,%a1@-,%d2
+    2678:	aee1 3046      	macw %d6u,%d3l,%a1@-,%sp
+    267c:	a2a1 3066      	macw %d6u,%d3l,%a1@-&,%d1
+    2680:	a6e1 3066      	macw %d6u,%d3l,%a1@-&,%a3
+    2684:	a4a1 3066      	macw %d6u,%d3l,%a1@-&,%d2
+    2688:	aee1 3066      	macw %d6u,%d3l,%a1@-&,%sp
+    268c:	a293 3246      	macw %d6u,%d3l,<<,%a3@,%d1
+    2690:	a6d3 3246      	macw %d6u,%d3l,<<,%a3@,%a3
+    2694:	a493 3246      	macw %d6u,%d3l,<<,%a3@,%d2
+    2698:	aed3 3246      	macw %d6u,%d3l,<<,%a3@,%sp
+    269c:	a293 3266      	macw %d6u,%d3l,<<,%a3@&,%d1
+    26a0:	a6d3 3266      	macw %d6u,%d3l,<<,%a3@&,%a3
+    26a4:	a493 3266      	macw %d6u,%d3l,<<,%a3@&,%d2
+    26a8:	aed3 3266      	macw %d6u,%d3l,<<,%a3@&,%sp
+    26ac:	a29a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d1
+    26b0:	a6da 3246      	macw %d6u,%d3l,<<,%a2@\+,%a3
+    26b4:	a49a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d2
+    26b8:	aeda 3246      	macw %d6u,%d3l,<<,%a2@\+,%sp
+    26bc:	a29a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d1
+    26c0:	a6da 3266      	macw %d6u,%d3l,<<,%a2@\+&,%a3
+    26c4:	a49a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d2
+    26c8:	aeda 3266      	macw %d6u,%d3l,<<,%a2@\+&,%sp
+    26cc:	a2ae 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1
+    26d2:	a6ee 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3
+    26d8:	a4ae 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2
+    26de:	aeee 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp
+    26e4:	a2ae 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1
+    26ea:	a6ee 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3
+    26f0:	a4ae 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2
+    26f6:	aeee 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp
+    26fc:	a2a1 3246      	macw %d6u,%d3l,<<,%a1@-,%d1
+    2700:	a6e1 3246      	macw %d6u,%d3l,<<,%a1@-,%a3
+    2704:	a4a1 3246      	macw %d6u,%d3l,<<,%a1@-,%d2
+    2708:	aee1 3246      	macw %d6u,%d3l,<<,%a1@-,%sp
+    270c:	a2a1 3266      	macw %d6u,%d3l,<<,%a1@-&,%d1
+    2710:	a6e1 3266      	macw %d6u,%d3l,<<,%a1@-&,%a3
+    2714:	a4a1 3266      	macw %d6u,%d3l,<<,%a1@-&,%d2
+    2718:	aee1 3266      	macw %d6u,%d3l,<<,%a1@-&,%sp
+    271c:	a293 3646      	macw %d6u,%d3l,>>,%a3@,%d1
+    2720:	a6d3 3646      	macw %d6u,%d3l,>>,%a3@,%a3
+    2724:	a493 3646      	macw %d6u,%d3l,>>,%a3@,%d2
+    2728:	aed3 3646      	macw %d6u,%d3l,>>,%a3@,%sp
+    272c:	a293 3666      	macw %d6u,%d3l,>>,%a3@&,%d1
+    2730:	a6d3 3666      	macw %d6u,%d3l,>>,%a3@&,%a3
+    2734:	a493 3666      	macw %d6u,%d3l,>>,%a3@&,%d2
+    2738:	aed3 3666      	macw %d6u,%d3l,>>,%a3@&,%sp
+    273c:	a29a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d1
+    2740:	a6da 3646      	macw %d6u,%d3l,>>,%a2@\+,%a3
+    2744:	a49a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d2
+    2748:	aeda 3646      	macw %d6u,%d3l,>>,%a2@\+,%sp
+    274c:	a29a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d1
+    2750:	a6da 3666      	macw %d6u,%d3l,>>,%a2@\+&,%a3
+    2754:	a49a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d2
+    2758:	aeda 3666      	macw %d6u,%d3l,>>,%a2@\+&,%sp
+    275c:	a2ae 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1
+    2762:	a6ee 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3
+    2768:	a4ae 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2
+    276e:	aeee 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp
+    2774:	a2ae 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1
+    277a:	a6ee 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3
+    2780:	a4ae 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2
+    2786:	aeee 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp
+    278c:	a2a1 3646      	macw %d6u,%d3l,>>,%a1@-,%d1
+    2790:	a6e1 3646      	macw %d6u,%d3l,>>,%a1@-,%a3
+    2794:	a4a1 3646      	macw %d6u,%d3l,>>,%a1@-,%d2
+    2798:	aee1 3646      	macw %d6u,%d3l,>>,%a1@-,%sp
+    279c:	a2a1 3666      	macw %d6u,%d3l,>>,%a1@-&,%d1
+    27a0:	a6e1 3666      	macw %d6u,%d3l,>>,%a1@-&,%a3
+    27a4:	a4a1 3666      	macw %d6u,%d3l,>>,%a1@-&,%d2
+    27a8:	aee1 3666      	macw %d6u,%d3l,>>,%a1@-&,%sp
+    27ac:	a293 3246      	macw %d6u,%d3l,<<,%a3@,%d1
+    27b0:	a6d3 3246      	macw %d6u,%d3l,<<,%a3@,%a3
+    27b4:	a493 3246      	macw %d6u,%d3l,<<,%a3@,%d2
+    27b8:	aed3 3246      	macw %d6u,%d3l,<<,%a3@,%sp
+    27bc:	a293 3266      	macw %d6u,%d3l,<<,%a3@&,%d1
+    27c0:	a6d3 3266      	macw %d6u,%d3l,<<,%a3@&,%a3
+    27c4:	a493 3266      	macw %d6u,%d3l,<<,%a3@&,%d2
+    27c8:	aed3 3266      	macw %d6u,%d3l,<<,%a3@&,%sp
+    27cc:	a29a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d1
+    27d0:	a6da 3246      	macw %d6u,%d3l,<<,%a2@\+,%a3
+    27d4:	a49a 3246      	macw %d6u,%d3l,<<,%a2@\+,%d2
+    27d8:	aeda 3246      	macw %d6u,%d3l,<<,%a2@\+,%sp
+    27dc:	a29a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d1
+    27e0:	a6da 3266      	macw %d6u,%d3l,<<,%a2@\+&,%a3
+    27e4:	a49a 3266      	macw %d6u,%d3l,<<,%a2@\+&,%d2
+    27e8:	aeda 3266      	macw %d6u,%d3l,<<,%a2@\+&,%sp
+    27ec:	a2ae 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d1
+    27f2:	a6ee 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%a3
+    27f8:	a4ae 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%d2
+    27fe:	aeee 3246 000a 	macw %d6u,%d3l,<<,%fp@\(10\),%sp
+    2804:	a2ae 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d1
+    280a:	a6ee 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%a3
+    2810:	a4ae 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%d2
+    2816:	aeee 3266 000a 	macw %d6u,%d3l,<<,%fp@\(10\)&,%sp
+    281c:	a2a1 3246      	macw %d6u,%d3l,<<,%a1@-,%d1
+    2820:	a6e1 3246      	macw %d6u,%d3l,<<,%a1@-,%a3
+    2824:	a4a1 3246      	macw %d6u,%d3l,<<,%a1@-,%d2
+    2828:	aee1 3246      	macw %d6u,%d3l,<<,%a1@-,%sp
+    282c:	a2a1 3266      	macw %d6u,%d3l,<<,%a1@-&,%d1
+    2830:	a6e1 3266      	macw %d6u,%d3l,<<,%a1@-&,%a3
+    2834:	a4a1 3266      	macw %d6u,%d3l,<<,%a1@-&,%d2
+    2838:	aee1 3266      	macw %d6u,%d3l,<<,%a1@-&,%sp
+    283c:	a293 3646      	macw %d6u,%d3l,>>,%a3@,%d1
+    2840:	a6d3 3646      	macw %d6u,%d3l,>>,%a3@,%a3
+    2844:	a493 3646      	macw %d6u,%d3l,>>,%a3@,%d2
+    2848:	aed3 3646      	macw %d6u,%d3l,>>,%a3@,%sp
+    284c:	a293 3666      	macw %d6u,%d3l,>>,%a3@&,%d1
+    2850:	a6d3 3666      	macw %d6u,%d3l,>>,%a3@&,%a3
+    2854:	a493 3666      	macw %d6u,%d3l,>>,%a3@&,%d2
+    2858:	aed3 3666      	macw %d6u,%d3l,>>,%a3@&,%sp
+    285c:	a29a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d1
+    2860:	a6da 3646      	macw %d6u,%d3l,>>,%a2@\+,%a3
+    2864:	a49a 3646      	macw %d6u,%d3l,>>,%a2@\+,%d2
+    2868:	aeda 3646      	macw %d6u,%d3l,>>,%a2@\+,%sp
+    286c:	a29a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d1
+    2870:	a6da 3666      	macw %d6u,%d3l,>>,%a2@\+&,%a3
+    2874:	a49a 3666      	macw %d6u,%d3l,>>,%a2@\+&,%d2
+    2878:	aeda 3666      	macw %d6u,%d3l,>>,%a2@\+&,%sp
+    287c:	a2ae 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d1
+    2882:	a6ee 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%a3
+    2888:	a4ae 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%d2
+    288e:	aeee 3646 000a 	macw %d6u,%d3l,>>,%fp@\(10\),%sp
+    2894:	a2ae 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d1
+    289a:	a6ee 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%a3
+    28a0:	a4ae 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%d2
+    28a6:	aeee 3666 000a 	macw %d6u,%d3l,>>,%fp@\(10\)&,%sp
+    28ac:	a2a1 3646      	macw %d6u,%d3l,>>,%a1@-,%d1
+    28b0:	a6e1 3646      	macw %d6u,%d3l,>>,%a1@-,%a3
+    28b4:	a4a1 3646      	macw %d6u,%d3l,>>,%a1@-,%d2
+    28b8:	aee1 3646      	macw %d6u,%d3l,>>,%a1@-,%sp
+    28bc:	a2a1 3666      	macw %d6u,%d3l,>>,%a1@-&,%d1
+    28c0:	a6e1 3666      	macw %d6u,%d3l,>>,%a1@-&,%a3
+    28c4:	a4a1 3666      	macw %d6u,%d3l,>>,%a1@-&,%d2
+    28c8:	aee1 3666      	macw %d6u,%d3l,>>,%a1@-&,%sp
+    28cc:	a293 f0c6      	macw %d6u,%a7u,%a3@,%d1
+    28d0:	a6d3 f0c6      	macw %d6u,%a7u,%a3@,%a3
+    28d4:	a493 f0c6      	macw %d6u,%a7u,%a3@,%d2
+    28d8:	aed3 f0c6      	macw %d6u,%a7u,%a3@,%sp
+    28dc:	a293 f0e6      	macw %d6u,%a7u,%a3@&,%d1
+    28e0:	a6d3 f0e6      	macw %d6u,%a7u,%a3@&,%a3
+    28e4:	a493 f0e6      	macw %d6u,%a7u,%a3@&,%d2
+    28e8:	aed3 f0e6      	macw %d6u,%a7u,%a3@&,%sp
+    28ec:	a29a f0c6      	macw %d6u,%a7u,%a2@\+,%d1
+    28f0:	a6da f0c6      	macw %d6u,%a7u,%a2@\+,%a3
+    28f4:	a49a f0c6      	macw %d6u,%a7u,%a2@\+,%d2
+    28f8:	aeda f0c6      	macw %d6u,%a7u,%a2@\+,%sp
+    28fc:	a29a f0e6      	macw %d6u,%a7u,%a2@\+&,%d1
+    2900:	a6da f0e6      	macw %d6u,%a7u,%a2@\+&,%a3
+    2904:	a49a f0e6      	macw %d6u,%a7u,%a2@\+&,%d2
+    2908:	aeda f0e6      	macw %d6u,%a7u,%a2@\+&,%sp
+    290c:	a2ae f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%d1
+    2912:	a6ee f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%a3
+    2918:	a4ae f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%d2
+    291e:	aeee f0c6 000a 	macw %d6u,%a7u,%fp@\(10\),%sp
+    2924:	a2ae f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d1
+    292a:	a6ee f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%a3
+    2930:	a4ae f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%d2
+    2936:	aeee f0e6 000a 	macw %d6u,%a7u,%fp@\(10\)&,%sp
+    293c:	a2a1 f0c6      	macw %d6u,%a7u,%a1@-,%d1
+    2940:	a6e1 f0c6      	macw %d6u,%a7u,%a1@-,%a3
+    2944:	a4a1 f0c6      	macw %d6u,%a7u,%a1@-,%d2
+    2948:	aee1 f0c6      	macw %d6u,%a7u,%a1@-,%sp
+    294c:	a2a1 f0e6      	macw %d6u,%a7u,%a1@-&,%d1
+    2950:	a6e1 f0e6      	macw %d6u,%a7u,%a1@-&,%a3
+    2954:	a4a1 f0e6      	macw %d6u,%a7u,%a1@-&,%d2
+    2958:	aee1 f0e6      	macw %d6u,%a7u,%a1@-&,%sp
+    295c:	a293 f2c6      	macw %d6u,%a7u,<<,%a3@,%d1
+    2960:	a6d3 f2c6      	macw %d6u,%a7u,<<,%a3@,%a3
+    2964:	a493 f2c6      	macw %d6u,%a7u,<<,%a3@,%d2
+    2968:	aed3 f2c6      	macw %d6u,%a7u,<<,%a3@,%sp
+    296c:	a293 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d1
+    2970:	a6d3 f2e6      	macw %d6u,%a7u,<<,%a3@&,%a3
+    2974:	a493 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d2
+    2978:	aed3 f2e6      	macw %d6u,%a7u,<<,%a3@&,%sp
+    297c:	a29a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d1
+    2980:	a6da f2c6      	macw %d6u,%a7u,<<,%a2@\+,%a3
+    2984:	a49a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d2
+    2988:	aeda f2c6      	macw %d6u,%a7u,<<,%a2@\+,%sp
+    298c:	a29a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d1
+    2990:	a6da f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%a3
+    2994:	a49a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d2
+    2998:	aeda f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%sp
+    299c:	a2ae f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1
+    29a2:	a6ee f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3
+    29a8:	a4ae f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2
+    29ae:	aeee f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp
+    29b4:	a2ae f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1
+    29ba:	a6ee f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3
+    29c0:	a4ae f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2
+    29c6:	aeee f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp
+    29cc:	a2a1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d1
+    29d0:	a6e1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%a3
+    29d4:	a4a1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d2
+    29d8:	aee1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%sp
+    29dc:	a2a1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d1
+    29e0:	a6e1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%a3
+    29e4:	a4a1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d2
+    29e8:	aee1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%sp
+    29ec:	a293 f6c6      	macw %d6u,%a7u,>>,%a3@,%d1
+    29f0:	a6d3 f6c6      	macw %d6u,%a7u,>>,%a3@,%a3
+    29f4:	a493 f6c6      	macw %d6u,%a7u,>>,%a3@,%d2
+    29f8:	aed3 f6c6      	macw %d6u,%a7u,>>,%a3@,%sp
+    29fc:	a293 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d1
+    2a00:	a6d3 f6e6      	macw %d6u,%a7u,>>,%a3@&,%a3
+    2a04:	a493 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d2
+    2a08:	aed3 f6e6      	macw %d6u,%a7u,>>,%a3@&,%sp
+    2a0c:	a29a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d1
+    2a10:	a6da f6c6      	macw %d6u,%a7u,>>,%a2@\+,%a3
+    2a14:	a49a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d2
+    2a18:	aeda f6c6      	macw %d6u,%a7u,>>,%a2@\+,%sp
+    2a1c:	a29a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d1
+    2a20:	a6da f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%a3
+    2a24:	a49a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d2
+    2a28:	aeda f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%sp
+    2a2c:	a2ae f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1
+    2a32:	a6ee f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3
+    2a38:	a4ae f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2
+    2a3e:	aeee f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp
+    2a44:	a2ae f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1
+    2a4a:	a6ee f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3
+    2a50:	a4ae f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2
+    2a56:	aeee f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp
+    2a5c:	a2a1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d1
+    2a60:	a6e1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%a3
+    2a64:	a4a1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d2
+    2a68:	aee1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%sp
+    2a6c:	a2a1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d1
+    2a70:	a6e1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%a3
+    2a74:	a4a1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d2
+    2a78:	aee1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%sp
+    2a7c:	a293 f2c6      	macw %d6u,%a7u,<<,%a3@,%d1
+    2a80:	a6d3 f2c6      	macw %d6u,%a7u,<<,%a3@,%a3
+    2a84:	a493 f2c6      	macw %d6u,%a7u,<<,%a3@,%d2
+    2a88:	aed3 f2c6      	macw %d6u,%a7u,<<,%a3@,%sp
+    2a8c:	a293 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d1
+    2a90:	a6d3 f2e6      	macw %d6u,%a7u,<<,%a3@&,%a3
+    2a94:	a493 f2e6      	macw %d6u,%a7u,<<,%a3@&,%d2
+    2a98:	aed3 f2e6      	macw %d6u,%a7u,<<,%a3@&,%sp
+    2a9c:	a29a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d1
+    2aa0:	a6da f2c6      	macw %d6u,%a7u,<<,%a2@\+,%a3
+    2aa4:	a49a f2c6      	macw %d6u,%a7u,<<,%a2@\+,%d2
+    2aa8:	aeda f2c6      	macw %d6u,%a7u,<<,%a2@\+,%sp
+    2aac:	a29a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d1
+    2ab0:	a6da f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%a3
+    2ab4:	a49a f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%d2
+    2ab8:	aeda f2e6      	macw %d6u,%a7u,<<,%a2@\+&,%sp
+    2abc:	a2ae f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d1
+    2ac2:	a6ee f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%a3
+    2ac8:	a4ae f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%d2
+    2ace:	aeee f2c6 000a 	macw %d6u,%a7u,<<,%fp@\(10\),%sp
+    2ad4:	a2ae f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d1
+    2ada:	a6ee f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%a3
+    2ae0:	a4ae f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%d2
+    2ae6:	aeee f2e6 000a 	macw %d6u,%a7u,<<,%fp@\(10\)&,%sp
+    2aec:	a2a1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d1
+    2af0:	a6e1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%a3
+    2af4:	a4a1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%d2
+    2af8:	aee1 f2c6      	macw %d6u,%a7u,<<,%a1@-,%sp
+    2afc:	a2a1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d1
+    2b00:	a6e1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%a3
+    2b04:	a4a1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%d2
+    2b08:	aee1 f2e6      	macw %d6u,%a7u,<<,%a1@-&,%sp
+    2b0c:	a293 f6c6      	macw %d6u,%a7u,>>,%a3@,%d1
+    2b10:	a6d3 f6c6      	macw %d6u,%a7u,>>,%a3@,%a3
+    2b14:	a493 f6c6      	macw %d6u,%a7u,>>,%a3@,%d2
+    2b18:	aed3 f6c6      	macw %d6u,%a7u,>>,%a3@,%sp
+    2b1c:	a293 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d1
+    2b20:	a6d3 f6e6      	macw %d6u,%a7u,>>,%a3@&,%a3
+    2b24:	a493 f6e6      	macw %d6u,%a7u,>>,%a3@&,%d2
+    2b28:	aed3 f6e6      	macw %d6u,%a7u,>>,%a3@&,%sp
+    2b2c:	a29a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d1
+    2b30:	a6da f6c6      	macw %d6u,%a7u,>>,%a2@\+,%a3
+    2b34:	a49a f6c6      	macw %d6u,%a7u,>>,%a2@\+,%d2
+    2b38:	aeda f6c6      	macw %d6u,%a7u,>>,%a2@\+,%sp
+    2b3c:	a29a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d1
+    2b40:	a6da f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%a3
+    2b44:	a49a f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%d2
+    2b48:	aeda f6e6      	macw %d6u,%a7u,>>,%a2@\+&,%sp
+    2b4c:	a2ae f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d1
+    2b52:	a6ee f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%a3
+    2b58:	a4ae f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%d2
+    2b5e:	aeee f6c6 000a 	macw %d6u,%a7u,>>,%fp@\(10\),%sp
+    2b64:	a2ae f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d1
+    2b6a:	a6ee f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%a3
+    2b70:	a4ae f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%d2
+    2b76:	aeee f6e6 000a 	macw %d6u,%a7u,>>,%fp@\(10\)&,%sp
+    2b7c:	a2a1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d1
+    2b80:	a6e1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%a3
+    2b84:	a4a1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%d2
+    2b88:	aee1 f6c6      	macw %d6u,%a7u,>>,%a1@-,%sp
+    2b8c:	a2a1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d1
+    2b90:	a6e1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%a3
+    2b94:	a4a1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%d2
+    2b98:	aee1 f6e6      	macw %d6u,%a7u,>>,%a1@-&,%sp
+    2b9c:	a293 1046      	macw %d6u,%d1l,%a3@,%d1
+    2ba0:	a6d3 1046      	macw %d6u,%d1l,%a3@,%a3
+    2ba4:	a493 1046      	macw %d6u,%d1l,%a3@,%d2
+    2ba8:	aed3 1046      	macw %d6u,%d1l,%a3@,%sp
+    2bac:	a293 1066      	macw %d6u,%d1l,%a3@&,%d1
+    2bb0:	a6d3 1066      	macw %d6u,%d1l,%a3@&,%a3
+    2bb4:	a493 1066      	macw %d6u,%d1l,%a3@&,%d2
+    2bb8:	aed3 1066      	macw %d6u,%d1l,%a3@&,%sp
+    2bbc:	a29a 1046      	macw %d6u,%d1l,%a2@\+,%d1
+    2bc0:	a6da 1046      	macw %d6u,%d1l,%a2@\+,%a3
+    2bc4:	a49a 1046      	macw %d6u,%d1l,%a2@\+,%d2
+    2bc8:	aeda 1046      	macw %d6u,%d1l,%a2@\+,%sp
+    2bcc:	a29a 1066      	macw %d6u,%d1l,%a2@\+&,%d1
+    2bd0:	a6da 1066      	macw %d6u,%d1l,%a2@\+&,%a3
+    2bd4:	a49a 1066      	macw %d6u,%d1l,%a2@\+&,%d2
+    2bd8:	aeda 1066      	macw %d6u,%d1l,%a2@\+&,%sp
+    2bdc:	a2ae 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%d1
+    2be2:	a6ee 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%a3
+    2be8:	a4ae 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%d2
+    2bee:	aeee 1046 000a 	macw %d6u,%d1l,%fp@\(10\),%sp
+    2bf4:	a2ae 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d1
+    2bfa:	a6ee 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%a3
+    2c00:	a4ae 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%d2
+    2c06:	aeee 1066 000a 	macw %d6u,%d1l,%fp@\(10\)&,%sp
+    2c0c:	a2a1 1046      	macw %d6u,%d1l,%a1@-,%d1
+    2c10:	a6e1 1046      	macw %d6u,%d1l,%a1@-,%a3
+    2c14:	a4a1 1046      	macw %d6u,%d1l,%a1@-,%d2
+    2c18:	aee1 1046      	macw %d6u,%d1l,%a1@-,%sp
+    2c1c:	a2a1 1066      	macw %d6u,%d1l,%a1@-&,%d1
+    2c20:	a6e1 1066      	macw %d6u,%d1l,%a1@-&,%a3
+    2c24:	a4a1 1066      	macw %d6u,%d1l,%a1@-&,%d2
+    2c28:	aee1 1066      	macw %d6u,%d1l,%a1@-&,%sp
+    2c2c:	a293 1246      	macw %d6u,%d1l,<<,%a3@,%d1
+    2c30:	a6d3 1246      	macw %d6u,%d1l,<<,%a3@,%a3
+    2c34:	a493 1246      	macw %d6u,%d1l,<<,%a3@,%d2
+    2c38:	aed3 1246      	macw %d6u,%d1l,<<,%a3@,%sp
+    2c3c:	a293 1266      	macw %d6u,%d1l,<<,%a3@&,%d1
+    2c40:	a6d3 1266      	macw %d6u,%d1l,<<,%a3@&,%a3
+    2c44:	a493 1266      	macw %d6u,%d1l,<<,%a3@&,%d2
+    2c48:	aed3 1266      	macw %d6u,%d1l,<<,%a3@&,%sp
+    2c4c:	a29a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d1
+    2c50:	a6da 1246      	macw %d6u,%d1l,<<,%a2@\+,%a3
+    2c54:	a49a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d2
+    2c58:	aeda 1246      	macw %d6u,%d1l,<<,%a2@\+,%sp
+    2c5c:	a29a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d1
+    2c60:	a6da 1266      	macw %d6u,%d1l,<<,%a2@\+&,%a3
+    2c64:	a49a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d2
+    2c68:	aeda 1266      	macw %d6u,%d1l,<<,%a2@\+&,%sp
+    2c6c:	a2ae 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1
+    2c72:	a6ee 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3
+    2c78:	a4ae 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2
+    2c7e:	aeee 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp
+    2c84:	a2ae 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1
+    2c8a:	a6ee 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3
+    2c90:	a4ae 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2
+    2c96:	aeee 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp
+    2c9c:	a2a1 1246      	macw %d6u,%d1l,<<,%a1@-,%d1
+    2ca0:	a6e1 1246      	macw %d6u,%d1l,<<,%a1@-,%a3
+    2ca4:	a4a1 1246      	macw %d6u,%d1l,<<,%a1@-,%d2
+    2ca8:	aee1 1246      	macw %d6u,%d1l,<<,%a1@-,%sp
+    2cac:	a2a1 1266      	macw %d6u,%d1l,<<,%a1@-&,%d1
+    2cb0:	a6e1 1266      	macw %d6u,%d1l,<<,%a1@-&,%a3
+    2cb4:	a4a1 1266      	macw %d6u,%d1l,<<,%a1@-&,%d2
+    2cb8:	aee1 1266      	macw %d6u,%d1l,<<,%a1@-&,%sp
+    2cbc:	a293 1646      	macw %d6u,%d1l,>>,%a3@,%d1
+    2cc0:	a6d3 1646      	macw %d6u,%d1l,>>,%a3@,%a3
+    2cc4:	a493 1646      	macw %d6u,%d1l,>>,%a3@,%d2
+    2cc8:	aed3 1646      	macw %d6u,%d1l,>>,%a3@,%sp
+    2ccc:	a293 1666      	macw %d6u,%d1l,>>,%a3@&,%d1
+    2cd0:	a6d3 1666      	macw %d6u,%d1l,>>,%a3@&,%a3
+    2cd4:	a493 1666      	macw %d6u,%d1l,>>,%a3@&,%d2
+    2cd8:	aed3 1666      	macw %d6u,%d1l,>>,%a3@&,%sp
+    2cdc:	a29a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d1
+    2ce0:	a6da 1646      	macw %d6u,%d1l,>>,%a2@\+,%a3
+    2ce4:	a49a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d2
+    2ce8:	aeda 1646      	macw %d6u,%d1l,>>,%a2@\+,%sp
+    2cec:	a29a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d1
+    2cf0:	a6da 1666      	macw %d6u,%d1l,>>,%a2@\+&,%a3
+    2cf4:	a49a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d2
+    2cf8:	aeda 1666      	macw %d6u,%d1l,>>,%a2@\+&,%sp
+    2cfc:	a2ae 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1
+    2d02:	a6ee 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3
+    2d08:	a4ae 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2
+    2d0e:	aeee 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp
+    2d14:	a2ae 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1
+    2d1a:	a6ee 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3
+    2d20:	a4ae 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2
+    2d26:	aeee 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp
+    2d2c:	a2a1 1646      	macw %d6u,%d1l,>>,%a1@-,%d1
+    2d30:	a6e1 1646      	macw %d6u,%d1l,>>,%a1@-,%a3
+    2d34:	a4a1 1646      	macw %d6u,%d1l,>>,%a1@-,%d2
+    2d38:	aee1 1646      	macw %d6u,%d1l,>>,%a1@-,%sp
+    2d3c:	a2a1 1666      	macw %d6u,%d1l,>>,%a1@-&,%d1
+    2d40:	a6e1 1666      	macw %d6u,%d1l,>>,%a1@-&,%a3
+    2d44:	a4a1 1666      	macw %d6u,%d1l,>>,%a1@-&,%d2
+    2d48:	aee1 1666      	macw %d6u,%d1l,>>,%a1@-&,%sp
+    2d4c:	a293 1246      	macw %d6u,%d1l,<<,%a3@,%d1
+    2d50:	a6d3 1246      	macw %d6u,%d1l,<<,%a3@,%a3
+    2d54:	a493 1246      	macw %d6u,%d1l,<<,%a3@,%d2
+    2d58:	aed3 1246      	macw %d6u,%d1l,<<,%a3@,%sp
+    2d5c:	a293 1266      	macw %d6u,%d1l,<<,%a3@&,%d1
+    2d60:	a6d3 1266      	macw %d6u,%d1l,<<,%a3@&,%a3
+    2d64:	a493 1266      	macw %d6u,%d1l,<<,%a3@&,%d2
+    2d68:	aed3 1266      	macw %d6u,%d1l,<<,%a3@&,%sp
+    2d6c:	a29a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d1
+    2d70:	a6da 1246      	macw %d6u,%d1l,<<,%a2@\+,%a3
+    2d74:	a49a 1246      	macw %d6u,%d1l,<<,%a2@\+,%d2
+    2d78:	aeda 1246      	macw %d6u,%d1l,<<,%a2@\+,%sp
+    2d7c:	a29a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d1
+    2d80:	a6da 1266      	macw %d6u,%d1l,<<,%a2@\+&,%a3
+    2d84:	a49a 1266      	macw %d6u,%d1l,<<,%a2@\+&,%d2
+    2d88:	aeda 1266      	macw %d6u,%d1l,<<,%a2@\+&,%sp
+    2d8c:	a2ae 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d1
+    2d92:	a6ee 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%a3
+    2d98:	a4ae 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%d2
+    2d9e:	aeee 1246 000a 	macw %d6u,%d1l,<<,%fp@\(10\),%sp
+    2da4:	a2ae 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d1
+    2daa:	a6ee 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%a3
+    2db0:	a4ae 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%d2
+    2db6:	aeee 1266 000a 	macw %d6u,%d1l,<<,%fp@\(10\)&,%sp
+    2dbc:	a2a1 1246      	macw %d6u,%d1l,<<,%a1@-,%d1
+    2dc0:	a6e1 1246      	macw %d6u,%d1l,<<,%a1@-,%a3
+    2dc4:	a4a1 1246      	macw %d6u,%d1l,<<,%a1@-,%d2
+    2dc8:	aee1 1246      	macw %d6u,%d1l,<<,%a1@-,%sp
+    2dcc:	a2a1 1266      	macw %d6u,%d1l,<<,%a1@-&,%d1
+    2dd0:	a6e1 1266      	macw %d6u,%d1l,<<,%a1@-&,%a3
+    2dd4:	a4a1 1266      	macw %d6u,%d1l,<<,%a1@-&,%d2
+    2dd8:	aee1 1266      	macw %d6u,%d1l,<<,%a1@-&,%sp
+    2ddc:	a293 1646      	macw %d6u,%d1l,>>,%a3@,%d1
+    2de0:	a6d3 1646      	macw %d6u,%d1l,>>,%a3@,%a3
+    2de4:	a493 1646      	macw %d6u,%d1l,>>,%a3@,%d2
+    2de8:	aed3 1646      	macw %d6u,%d1l,>>,%a3@,%sp
+    2dec:	a293 1666      	macw %d6u,%d1l,>>,%a3@&,%d1
+    2df0:	a6d3 1666      	macw %d6u,%d1l,>>,%a3@&,%a3
+    2df4:	a493 1666      	macw %d6u,%d1l,>>,%a3@&,%d2
+    2df8:	aed3 1666      	macw %d6u,%d1l,>>,%a3@&,%sp
+    2dfc:	a29a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d1
+    2e00:	a6da 1646      	macw %d6u,%d1l,>>,%a2@\+,%a3
+    2e04:	a49a 1646      	macw %d6u,%d1l,>>,%a2@\+,%d2
+    2e08:	aeda 1646      	macw %d6u,%d1l,>>,%a2@\+,%sp
+    2e0c:	a29a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d1
+    2e10:	a6da 1666      	macw %d6u,%d1l,>>,%a2@\+&,%a3
+    2e14:	a49a 1666      	macw %d6u,%d1l,>>,%a2@\+&,%d2
+    2e18:	aeda 1666      	macw %d6u,%d1l,>>,%a2@\+&,%sp
+    2e1c:	a2ae 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d1
+    2e22:	a6ee 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%a3
+    2e28:	a4ae 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%d2
+    2e2e:	aeee 1646 000a 	macw %d6u,%d1l,>>,%fp@\(10\),%sp
+    2e34:	a2ae 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d1
+    2e3a:	a6ee 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%a3
+    2e40:	a4ae 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%d2
+    2e46:	aeee 1666 000a 	macw %d6u,%d1l,>>,%fp@\(10\)&,%sp
+    2e4c:	a2a1 1646      	macw %d6u,%d1l,>>,%a1@-,%d1
+    2e50:	a6e1 1646      	macw %d6u,%d1l,>>,%a1@-,%a3
+    2e54:	a4a1 1646      	macw %d6u,%d1l,>>,%a1@-,%d2
+    2e58:	aee1 1646      	macw %d6u,%d1l,>>,%a1@-,%sp
+    2e5c:	a2a1 1666      	macw %d6u,%d1l,>>,%a1@-&,%d1
+    2e60:	a6e1 1666      	macw %d6u,%d1l,>>,%a1@-&,%a3
+    2e64:	a4a1 1666      	macw %d6u,%d1l,>>,%a1@-&,%d2
+    2e68:	aee1 1666      	macw %d6u,%d1l,>>,%a1@-&,%sp
+    2e6c:	a649 0800      	macl %a1,%a3
+    2e70:	a649 0a00      	macl %a1,%a3,<<
+    2e74:	a649 0e00      	macl %a1,%a3,>>
+    2e78:	a649 0a00      	macl %a1,%a3,<<
+    2e7c:	a649 0e00      	macl %a1,%a3,>>
+    2e80:	a809 0800      	macl %a1,%d4
+    2e84:	a809 0a00      	macl %a1,%d4,<<
+    2e88:	a809 0e00      	macl %a1,%d4,>>
+    2e8c:	a809 0a00      	macl %a1,%d4,<<
+    2e90:	a809 0e00      	macl %a1,%d4,>>
+    2e94:	a646 0800      	macl %d6,%a3
+    2e98:	a646 0a00      	macl %d6,%a3,<<
+    2e9c:	a646 0e00      	macl %d6,%a3,>>
+    2ea0:	a646 0a00      	macl %d6,%a3,<<
+    2ea4:	a646 0e00      	macl %d6,%a3,>>
+    2ea8:	a806 0800      	macl %d6,%d4
+    2eac:	a806 0a00      	macl %d6,%d4,<<
+    2eb0:	a806 0e00      	macl %d6,%d4,>>
+    2eb4:	a806 0a00      	macl %d6,%d4,<<
+    2eb8:	a806 0e00      	macl %d6,%d4,>>
+    2ebc:	a293 b809      	macl %a1,%a3,%a3@,%d1
+    2ec0:	a6d3 b809      	macl %a1,%a3,%a3@,%a3
+    2ec4:	a493 b809      	macl %a1,%a3,%a3@,%d2
+    2ec8:	aed3 b809      	macl %a1,%a3,%a3@,%sp
+    2ecc:	a293 b829      	macl %a1,%a3,%a3@&,%d1
+    2ed0:	a6d3 b829      	macl %a1,%a3,%a3@&,%a3
+    2ed4:	a493 b829      	macl %a1,%a3,%a3@&,%d2
+    2ed8:	aed3 b829      	macl %a1,%a3,%a3@&,%sp
+    2edc:	a29a b809      	macl %a1,%a3,%a2@\+,%d1
+    2ee0:	a6da b809      	macl %a1,%a3,%a2@\+,%a3
+    2ee4:	a49a b809      	macl %a1,%a3,%a2@\+,%d2
+    2ee8:	aeda b809      	macl %a1,%a3,%a2@\+,%sp
+    2eec:	a29a b829      	macl %a1,%a3,%a2@\+&,%d1
+    2ef0:	a6da b829      	macl %a1,%a3,%a2@\+&,%a3
+    2ef4:	a49a b829      	macl %a1,%a3,%a2@\+&,%d2
+    2ef8:	aeda b829      	macl %a1,%a3,%a2@\+&,%sp
+    2efc:	a2ae b809 000a 	macl %a1,%a3,%fp@\(10\),%d1
+    2f02:	a6ee b809 000a 	macl %a1,%a3,%fp@\(10\),%a3
+    2f08:	a4ae b809 000a 	macl %a1,%a3,%fp@\(10\),%d2
+    2f0e:	aeee b809 000a 	macl %a1,%a3,%fp@\(10\),%sp
+    2f14:	a2ae b829 000a 	macl %a1,%a3,%fp@\(10\)&,%d1
+    2f1a:	a6ee b829 000a 	macl %a1,%a3,%fp@\(10\)&,%a3
+    2f20:	a4ae b829 000a 	macl %a1,%a3,%fp@\(10\)&,%d2
+    2f26:	aeee b829 000a 	macl %a1,%a3,%fp@\(10\)&,%sp
+    2f2c:	a2a1 b809      	macl %a1,%a3,%a1@-,%d1
+    2f30:	a6e1 b809      	macl %a1,%a3,%a1@-,%a3
+    2f34:	a4a1 b809      	macl %a1,%a3,%a1@-,%d2
+    2f38:	aee1 b809      	macl %a1,%a3,%a1@-,%sp
+    2f3c:	a2a1 b829      	macl %a1,%a3,%a1@-&,%d1
+    2f40:	a6e1 b829      	macl %a1,%a3,%a1@-&,%a3
+    2f44:	a4a1 b829      	macl %a1,%a3,%a1@-&,%d2
+    2f48:	aee1 b829      	macl %a1,%a3,%a1@-&,%sp
+    2f4c:	a293 ba09      	macl %a1,%a3,<<,%a3@,%d1
+    2f50:	a6d3 ba09      	macl %a1,%a3,<<,%a3@,%a3
+    2f54:	a493 ba09      	macl %a1,%a3,<<,%a3@,%d2
+    2f58:	aed3 ba09      	macl %a1,%a3,<<,%a3@,%sp
+    2f5c:	a293 ba29      	macl %a1,%a3,<<,%a3@&,%d1
+    2f60:	a6d3 ba29      	macl %a1,%a3,<<,%a3@&,%a3
+    2f64:	a493 ba29      	macl %a1,%a3,<<,%a3@&,%d2
+    2f68:	aed3 ba29      	macl %a1,%a3,<<,%a3@&,%sp
+    2f6c:	a29a ba09      	macl %a1,%a3,<<,%a2@\+,%d1
+    2f70:	a6da ba09      	macl %a1,%a3,<<,%a2@\+,%a3
+    2f74:	a49a ba09      	macl %a1,%a3,<<,%a2@\+,%d2
+    2f78:	aeda ba09      	macl %a1,%a3,<<,%a2@\+,%sp
+    2f7c:	a29a ba29      	macl %a1,%a3,<<,%a2@\+&,%d1
+    2f80:	a6da ba29      	macl %a1,%a3,<<,%a2@\+&,%a3
+    2f84:	a49a ba29      	macl %a1,%a3,<<,%a2@\+&,%d2
+    2f88:	aeda ba29      	macl %a1,%a3,<<,%a2@\+&,%sp
+    2f8c:	a2ae ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1
+    2f92:	a6ee ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3
+    2f98:	a4ae ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2
+    2f9e:	aeee ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp
+    2fa4:	a2ae ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1
+    2faa:	a6ee ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3
+    2fb0:	a4ae ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2
+    2fb6:	aeee ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp
+    2fbc:	a2a1 ba09      	macl %a1,%a3,<<,%a1@-,%d1
+    2fc0:	a6e1 ba09      	macl %a1,%a3,<<,%a1@-,%a3
+    2fc4:	a4a1 ba09      	macl %a1,%a3,<<,%a1@-,%d2
+    2fc8:	aee1 ba09      	macl %a1,%a3,<<,%a1@-,%sp
+    2fcc:	a2a1 ba29      	macl %a1,%a3,<<,%a1@-&,%d1
+    2fd0:	a6e1 ba29      	macl %a1,%a3,<<,%a1@-&,%a3
+    2fd4:	a4a1 ba29      	macl %a1,%a3,<<,%a1@-&,%d2
+    2fd8:	aee1 ba29      	macl %a1,%a3,<<,%a1@-&,%sp
+    2fdc:	a293 be09      	macl %a1,%a3,>>,%a3@,%d1
+    2fe0:	a6d3 be09      	macl %a1,%a3,>>,%a3@,%a3
+    2fe4:	a493 be09      	macl %a1,%a3,>>,%a3@,%d2
+    2fe8:	aed3 be09      	macl %a1,%a3,>>,%a3@,%sp
+    2fec:	a293 be29      	macl %a1,%a3,>>,%a3@&,%d1
+    2ff0:	a6d3 be29      	macl %a1,%a3,>>,%a3@&,%a3
+    2ff4:	a493 be29      	macl %a1,%a3,>>,%a3@&,%d2
+    2ff8:	aed3 be29      	macl %a1,%a3,>>,%a3@&,%sp
+    2ffc:	a29a be09      	macl %a1,%a3,>>,%a2@\+,%d1
+    3000:	a6da be09      	macl %a1,%a3,>>,%a2@\+,%a3
+    3004:	a49a be09      	macl %a1,%a3,>>,%a2@\+,%d2
+    3008:	aeda be09      	macl %a1,%a3,>>,%a2@\+,%sp
+    300c:	a29a be29      	macl %a1,%a3,>>,%a2@\+&,%d1
+    3010:	a6da be29      	macl %a1,%a3,>>,%a2@\+&,%a3
+    3014:	a49a be29      	macl %a1,%a3,>>,%a2@\+&,%d2
+    3018:	aeda be29      	macl %a1,%a3,>>,%a2@\+&,%sp
+    301c:	a2ae be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1
+    3022:	a6ee be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3
+    3028:	a4ae be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2
+    302e:	aeee be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp
+    3034:	a2ae be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1
+    303a:	a6ee be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3
+    3040:	a4ae be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2
+    3046:	aeee be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp
+    304c:	a2a1 be09      	macl %a1,%a3,>>,%a1@-,%d1
+    3050:	a6e1 be09      	macl %a1,%a3,>>,%a1@-,%a3
+    3054:	a4a1 be09      	macl %a1,%a3,>>,%a1@-,%d2
+    3058:	aee1 be09      	macl %a1,%a3,>>,%a1@-,%sp
+    305c:	a2a1 be29      	macl %a1,%a3,>>,%a1@-&,%d1
+    3060:	a6e1 be29      	macl %a1,%a3,>>,%a1@-&,%a3
+    3064:	a4a1 be29      	macl %a1,%a3,>>,%a1@-&,%d2
+    3068:	aee1 be29      	macl %a1,%a3,>>,%a1@-&,%sp
+    306c:	a293 ba09      	macl %a1,%a3,<<,%a3@,%d1
+    3070:	a6d3 ba09      	macl %a1,%a3,<<,%a3@,%a3
+    3074:	a493 ba09      	macl %a1,%a3,<<,%a3@,%d2
+    3078:	aed3 ba09      	macl %a1,%a3,<<,%a3@,%sp
+    307c:	a293 ba29      	macl %a1,%a3,<<,%a3@&,%d1
+    3080:	a6d3 ba29      	macl %a1,%a3,<<,%a3@&,%a3
+    3084:	a493 ba29      	macl %a1,%a3,<<,%a3@&,%d2
+    3088:	aed3 ba29      	macl %a1,%a3,<<,%a3@&,%sp
+    308c:	a29a ba09      	macl %a1,%a3,<<,%a2@\+,%d1
+    3090:	a6da ba09      	macl %a1,%a3,<<,%a2@\+,%a3
+    3094:	a49a ba09      	macl %a1,%a3,<<,%a2@\+,%d2
+    3098:	aeda ba09      	macl %a1,%a3,<<,%a2@\+,%sp
+    309c:	a29a ba29      	macl %a1,%a3,<<,%a2@\+&,%d1
+    30a0:	a6da ba29      	macl %a1,%a3,<<,%a2@\+&,%a3
+    30a4:	a49a ba29      	macl %a1,%a3,<<,%a2@\+&,%d2
+    30a8:	aeda ba29      	macl %a1,%a3,<<,%a2@\+&,%sp
+    30ac:	a2ae ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d1
+    30b2:	a6ee ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%a3
+    30b8:	a4ae ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%d2
+    30be:	aeee ba09 000a 	macl %a1,%a3,<<,%fp@\(10\),%sp
+    30c4:	a2ae ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d1
+    30ca:	a6ee ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%a3
+    30d0:	a4ae ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%d2
+    30d6:	aeee ba29 000a 	macl %a1,%a3,<<,%fp@\(10\)&,%sp
+    30dc:	a2a1 ba09      	macl %a1,%a3,<<,%a1@-,%d1
+    30e0:	a6e1 ba09      	macl %a1,%a3,<<,%a1@-,%a3
+    30e4:	a4a1 ba09      	macl %a1,%a3,<<,%a1@-,%d2
+    30e8:	aee1 ba09      	macl %a1,%a3,<<,%a1@-,%sp
+    30ec:	a2a1 ba29      	macl %a1,%a3,<<,%a1@-&,%d1
+    30f0:	a6e1 ba29      	macl %a1,%a3,<<,%a1@-&,%a3
+    30f4:	a4a1 ba29      	macl %a1,%a3,<<,%a1@-&,%d2
+    30f8:	aee1 ba29      	macl %a1,%a3,<<,%a1@-&,%sp
+    30fc:	a293 be09      	macl %a1,%a3,>>,%a3@,%d1
+    3100:	a6d3 be09      	macl %a1,%a3,>>,%a3@,%a3
+    3104:	a493 be09      	macl %a1,%a3,>>,%a3@,%d2
+    3108:	aed3 be09      	macl %a1,%a3,>>,%a3@,%sp
+    310c:	a293 be29      	macl %a1,%a3,>>,%a3@&,%d1
+    3110:	a6d3 be29      	macl %a1,%a3,>>,%a3@&,%a3
+    3114:	a493 be29      	macl %a1,%a3,>>,%a3@&,%d2
+    3118:	aed3 be29      	macl %a1,%a3,>>,%a3@&,%sp
+    311c:	a29a be09      	macl %a1,%a3,>>,%a2@\+,%d1
+    3120:	a6da be09      	macl %a1,%a3,>>,%a2@\+,%a3
+    3124:	a49a be09      	macl %a1,%a3,>>,%a2@\+,%d2
+    3128:	aeda be09      	macl %a1,%a3,>>,%a2@\+,%sp
+    312c:	a29a be29      	macl %a1,%a3,>>,%a2@\+&,%d1
+    3130:	a6da be29      	macl %a1,%a3,>>,%a2@\+&,%a3
+    3134:	a49a be29      	macl %a1,%a3,>>,%a2@\+&,%d2
+    3138:	aeda be29      	macl %a1,%a3,>>,%a2@\+&,%sp
+    313c:	a2ae be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d1
+    3142:	a6ee be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%a3
+    3148:	a4ae be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%d2
+    314e:	aeee be09 000a 	macl %a1,%a3,>>,%fp@\(10\),%sp
+    3154:	a2ae be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d1
+    315a:	a6ee be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%a3
+    3160:	a4ae be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%d2
+    3166:	aeee be29 000a 	macl %a1,%a3,>>,%fp@\(10\)&,%sp
+    316c:	a2a1 be09      	macl %a1,%a3,>>,%a1@-,%d1
+    3170:	a6e1 be09      	macl %a1,%a3,>>,%a1@-,%a3
+    3174:	a4a1 be09      	macl %a1,%a3,>>,%a1@-,%d2
+    3178:	aee1 be09      	macl %a1,%a3,>>,%a1@-,%sp
+    317c:	a2a1 be29      	macl %a1,%a3,>>,%a1@-&,%d1
+    3180:	a6e1 be29      	macl %a1,%a3,>>,%a1@-&,%a3
+    3184:	a4a1 be29      	macl %a1,%a3,>>,%a1@-&,%d2
+    3188:	aee1 be29      	macl %a1,%a3,>>,%a1@-&,%sp
+    318c:	a293 4809      	macl %a1,%d4,%a3@,%d1
+    3190:	a6d3 4809      	macl %a1,%d4,%a3@,%a3
+    3194:	a493 4809      	macl %a1,%d4,%a3@,%d2
+    3198:	aed3 4809      	macl %a1,%d4,%a3@,%sp
+    319c:	a293 4829      	macl %a1,%d4,%a3@&,%d1
+    31a0:	a6d3 4829      	macl %a1,%d4,%a3@&,%a3
+    31a4:	a493 4829      	macl %a1,%d4,%a3@&,%d2
+    31a8:	aed3 4829      	macl %a1,%d4,%a3@&,%sp
+    31ac:	a29a 4809      	macl %a1,%d4,%a2@\+,%d1
+    31b0:	a6da 4809      	macl %a1,%d4,%a2@\+,%a3
+    31b4:	a49a 4809      	macl %a1,%d4,%a2@\+,%d2
+    31b8:	aeda 4809      	macl %a1,%d4,%a2@\+,%sp
+    31bc:	a29a 4829      	macl %a1,%d4,%a2@\+&,%d1
+    31c0:	a6da 4829      	macl %a1,%d4,%a2@\+&,%a3
+    31c4:	a49a 4829      	macl %a1,%d4,%a2@\+&,%d2
+    31c8:	aeda 4829      	macl %a1,%d4,%a2@\+&,%sp
+    31cc:	a2ae 4809 000a 	macl %a1,%d4,%fp@\(10\),%d1
+    31d2:	a6ee 4809 000a 	macl %a1,%d4,%fp@\(10\),%a3
+    31d8:	a4ae 4809 000a 	macl %a1,%d4,%fp@\(10\),%d2
+    31de:	aeee 4809 000a 	macl %a1,%d4,%fp@\(10\),%sp
+    31e4:	a2ae 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%d1
+    31ea:	a6ee 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%a3
+    31f0:	a4ae 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%d2
+    31f6:	aeee 4829 000a 	macl %a1,%d4,%fp@\(10\)&,%sp
+    31fc:	a2a1 4809      	macl %a1,%d4,%a1@-,%d1
+    3200:	a6e1 4809      	macl %a1,%d4,%a1@-,%a3
+    3204:	a4a1 4809      	macl %a1,%d4,%a1@-,%d2
+    3208:	aee1 4809      	macl %a1,%d4,%a1@-,%sp
+    320c:	a2a1 4829      	macl %a1,%d4,%a1@-&,%d1
+    3210:	a6e1 4829      	macl %a1,%d4,%a1@-&,%a3
+    3214:	a4a1 4829      	macl %a1,%d4,%a1@-&,%d2
+    3218:	aee1 4829      	macl %a1,%d4,%a1@-&,%sp
+    321c:	a293 4a09      	macl %a1,%d4,<<,%a3@,%d1
+    3220:	a6d3 4a09      	macl %a1,%d4,<<,%a3@,%a3
+    3224:	a493 4a09      	macl %a1,%d4,<<,%a3@,%d2
+    3228:	aed3 4a09      	macl %a1,%d4,<<,%a3@,%sp
+    322c:	a293 4a29      	macl %a1,%d4,<<,%a3@&,%d1
+    3230:	a6d3 4a29      	macl %a1,%d4,<<,%a3@&,%a3
+    3234:	a493 4a29      	macl %a1,%d4,<<,%a3@&,%d2
+    3238:	aed3 4a29      	macl %a1,%d4,<<,%a3@&,%sp
+    323c:	a29a 4a09      	macl %a1,%d4,<<,%a2@\+,%d1
+    3240:	a6da 4a09      	macl %a1,%d4,<<,%a2@\+,%a3
+    3244:	a49a 4a09      	macl %a1,%d4,<<,%a2@\+,%d2
+    3248:	aeda 4a09      	macl %a1,%d4,<<,%a2@\+,%sp
+    324c:	a29a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d1
+    3250:	a6da 4a29      	macl %a1,%d4,<<,%a2@\+&,%a3
+    3254:	a49a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d2
+    3258:	aeda 4a29      	macl %a1,%d4,<<,%a2@\+&,%sp
+    325c:	a2ae 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1
+    3262:	a6ee 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3
+    3268:	a4ae 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2
+    326e:	aeee 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp
+    3274:	a2ae 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1
+    327a:	a6ee 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3
+    3280:	a4ae 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2
+    3286:	aeee 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp
+    328c:	a2a1 4a09      	macl %a1,%d4,<<,%a1@-,%d1
+    3290:	a6e1 4a09      	macl %a1,%d4,<<,%a1@-,%a3
+    3294:	a4a1 4a09      	macl %a1,%d4,<<,%a1@-,%d2
+    3298:	aee1 4a09      	macl %a1,%d4,<<,%a1@-,%sp
+    329c:	a2a1 4a29      	macl %a1,%d4,<<,%a1@-&,%d1
+    32a0:	a6e1 4a29      	macl %a1,%d4,<<,%a1@-&,%a3
+    32a4:	a4a1 4a29      	macl %a1,%d4,<<,%a1@-&,%d2
+    32a8:	aee1 4a29      	macl %a1,%d4,<<,%a1@-&,%sp
+    32ac:	a293 4e09      	macl %a1,%d4,>>,%a3@,%d1
+    32b0:	a6d3 4e09      	macl %a1,%d4,>>,%a3@,%a3
+    32b4:	a493 4e09      	macl %a1,%d4,>>,%a3@,%d2
+    32b8:	aed3 4e09      	macl %a1,%d4,>>,%a3@,%sp
+    32bc:	a293 4e29      	macl %a1,%d4,>>,%a3@&,%d1
+    32c0:	a6d3 4e29      	macl %a1,%d4,>>,%a3@&,%a3
+    32c4:	a493 4e29      	macl %a1,%d4,>>,%a3@&,%d2
+    32c8:	aed3 4e29      	macl %a1,%d4,>>,%a3@&,%sp
+    32cc:	a29a 4e09      	macl %a1,%d4,>>,%a2@\+,%d1
+    32d0:	a6da 4e09      	macl %a1,%d4,>>,%a2@\+,%a3
+    32d4:	a49a 4e09      	macl %a1,%d4,>>,%a2@\+,%d2
+    32d8:	aeda 4e09      	macl %a1,%d4,>>,%a2@\+,%sp
+    32dc:	a29a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d1
+    32e0:	a6da 4e29      	macl %a1,%d4,>>,%a2@\+&,%a3
+    32e4:	a49a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d2
+    32e8:	aeda 4e29      	macl %a1,%d4,>>,%a2@\+&,%sp
+    32ec:	a2ae 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1
+    32f2:	a6ee 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3
+    32f8:	a4ae 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2
+    32fe:	aeee 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp
+    3304:	a2ae 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1
+    330a:	a6ee 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3
+    3310:	a4ae 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2
+    3316:	aeee 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp
+    331c:	a2a1 4e09      	macl %a1,%d4,>>,%a1@-,%d1
+    3320:	a6e1 4e09      	macl %a1,%d4,>>,%a1@-,%a3
+    3324:	a4a1 4e09      	macl %a1,%d4,>>,%a1@-,%d2
+    3328:	aee1 4e09      	macl %a1,%d4,>>,%a1@-,%sp
+    332c:	a2a1 4e29      	macl %a1,%d4,>>,%a1@-&,%d1
+    3330:	a6e1 4e29      	macl %a1,%d4,>>,%a1@-&,%a3
+    3334:	a4a1 4e29      	macl %a1,%d4,>>,%a1@-&,%d2
+    3338:	aee1 4e29      	macl %a1,%d4,>>,%a1@-&,%sp
+    333c:	a293 4a09      	macl %a1,%d4,<<,%a3@,%d1
+    3340:	a6d3 4a09      	macl %a1,%d4,<<,%a3@,%a3
+    3344:	a493 4a09      	macl %a1,%d4,<<,%a3@,%d2
+    3348:	aed3 4a09      	macl %a1,%d4,<<,%a3@,%sp
+    334c:	a293 4a29      	macl %a1,%d4,<<,%a3@&,%d1
+    3350:	a6d3 4a29      	macl %a1,%d4,<<,%a3@&,%a3
+    3354:	a493 4a29      	macl %a1,%d4,<<,%a3@&,%d2
+    3358:	aed3 4a29      	macl %a1,%d4,<<,%a3@&,%sp
+    335c:	a29a 4a09      	macl %a1,%d4,<<,%a2@\+,%d1
+    3360:	a6da 4a09      	macl %a1,%d4,<<,%a2@\+,%a3
+    3364:	a49a 4a09      	macl %a1,%d4,<<,%a2@\+,%d2
+    3368:	aeda 4a09      	macl %a1,%d4,<<,%a2@\+,%sp
+    336c:	a29a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d1
+    3370:	a6da 4a29      	macl %a1,%d4,<<,%a2@\+&,%a3
+    3374:	a49a 4a29      	macl %a1,%d4,<<,%a2@\+&,%d2
+    3378:	aeda 4a29      	macl %a1,%d4,<<,%a2@\+&,%sp
+    337c:	a2ae 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d1
+    3382:	a6ee 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%a3
+    3388:	a4ae 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%d2
+    338e:	aeee 4a09 000a 	macl %a1,%d4,<<,%fp@\(10\),%sp
+    3394:	a2ae 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d1
+    339a:	a6ee 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%a3
+    33a0:	a4ae 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%d2
+    33a6:	aeee 4a29 000a 	macl %a1,%d4,<<,%fp@\(10\)&,%sp
+    33ac:	a2a1 4a09      	macl %a1,%d4,<<,%a1@-,%d1
+    33b0:	a6e1 4a09      	macl %a1,%d4,<<,%a1@-,%a3
+    33b4:	a4a1 4a09      	macl %a1,%d4,<<,%a1@-,%d2
+    33b8:	aee1 4a09      	macl %a1,%d4,<<,%a1@-,%sp
+    33bc:	a2a1 4a29      	macl %a1,%d4,<<,%a1@-&,%d1
+    33c0:	a6e1 4a29      	macl %a1,%d4,<<,%a1@-&,%a3
+    33c4:	a4a1 4a29      	macl %a1,%d4,<<,%a1@-&,%d2
+    33c8:	aee1 4a29      	macl %a1,%d4,<<,%a1@-&,%sp
+    33cc:	a293 4e09      	macl %a1,%d4,>>,%a3@,%d1
+    33d0:	a6d3 4e09      	macl %a1,%d4,>>,%a3@,%a3
+    33d4:	a493 4e09      	macl %a1,%d4,>>,%a3@,%d2
+    33d8:	aed3 4e09      	macl %a1,%d4,>>,%a3@,%sp
+    33dc:	a293 4e29      	macl %a1,%d4,>>,%a3@&,%d1
+    33e0:	a6d3 4e29      	macl %a1,%d4,>>,%a3@&,%a3
+    33e4:	a493 4e29      	macl %a1,%d4,>>,%a3@&,%d2
+    33e8:	aed3 4e29      	macl %a1,%d4,>>,%a3@&,%sp
+    33ec:	a29a 4e09      	macl %a1,%d4,>>,%a2@\+,%d1
+    33f0:	a6da 4e09      	macl %a1,%d4,>>,%a2@\+,%a3
+    33f4:	a49a 4e09      	macl %a1,%d4,>>,%a2@\+,%d2
+    33f8:	aeda 4e09      	macl %a1,%d4,>>,%a2@\+,%sp
+    33fc:	a29a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d1
+    3400:	a6da 4e29      	macl %a1,%d4,>>,%a2@\+&,%a3
+    3404:	a49a 4e29      	macl %a1,%d4,>>,%a2@\+&,%d2
+    3408:	aeda 4e29      	macl %a1,%d4,>>,%a2@\+&,%sp
+    340c:	a2ae 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d1
+    3412:	a6ee 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%a3
+    3418:	a4ae 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%d2
+    341e:	aeee 4e09 000a 	macl %a1,%d4,>>,%fp@\(10\),%sp
+    3424:	a2ae 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d1
+    342a:	a6ee 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%a3
+    3430:	a4ae 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%d2
+    3436:	aeee 4e29 000a 	macl %a1,%d4,>>,%fp@\(10\)&,%sp
+    343c:	a2a1 4e09      	macl %a1,%d4,>>,%a1@-,%d1
+    3440:	a6e1 4e09      	macl %a1,%d4,>>,%a1@-,%a3
+    3444:	a4a1 4e09      	macl %a1,%d4,>>,%a1@-,%d2
+    3448:	aee1 4e09      	macl %a1,%d4,>>,%a1@-,%sp
+    344c:	a2a1 4e29      	macl %a1,%d4,>>,%a1@-&,%d1
+    3450:	a6e1 4e29      	macl %a1,%d4,>>,%a1@-&,%a3
+    3454:	a4a1 4e29      	macl %a1,%d4,>>,%a1@-&,%d2
+    3458:	aee1 4e29      	macl %a1,%d4,>>,%a1@-&,%sp
+    345c:	a293 b806      	macl %d6,%a3,%a3@,%d1
+    3460:	a6d3 b806      	macl %d6,%a3,%a3@,%a3
+    3464:	a493 b806      	macl %d6,%a3,%a3@,%d2
+    3468:	aed3 b806      	macl %d6,%a3,%a3@,%sp
+    346c:	a293 b826      	macl %d6,%a3,%a3@&,%d1
+    3470:	a6d3 b826      	macl %d6,%a3,%a3@&,%a3
+    3474:	a493 b826      	macl %d6,%a3,%a3@&,%d2
+    3478:	aed3 b826      	macl %d6,%a3,%a3@&,%sp
+    347c:	a29a b806      	macl %d6,%a3,%a2@\+,%d1
+    3480:	a6da b806      	macl %d6,%a3,%a2@\+,%a3
+    3484:	a49a b806      	macl %d6,%a3,%a2@\+,%d2
+    3488:	aeda b806      	macl %d6,%a3,%a2@\+,%sp
+    348c:	a29a b826      	macl %d6,%a3,%a2@\+&,%d1
+    3490:	a6da b826      	macl %d6,%a3,%a2@\+&,%a3
+    3494:	a49a b826      	macl %d6,%a3,%a2@\+&,%d2
+    3498:	aeda b826      	macl %d6,%a3,%a2@\+&,%sp
+    349c:	a2ae b806 000a 	macl %d6,%a3,%fp@\(10\),%d1
+    34a2:	a6ee b806 000a 	macl %d6,%a3,%fp@\(10\),%a3
+    34a8:	a4ae b806 000a 	macl %d6,%a3,%fp@\(10\),%d2
+    34ae:	aeee b806 000a 	macl %d6,%a3,%fp@\(10\),%sp
+    34b4:	a2ae b826 000a 	macl %d6,%a3,%fp@\(10\)&,%d1
+    34ba:	a6ee b826 000a 	macl %d6,%a3,%fp@\(10\)&,%a3
+    34c0:	a4ae b826 000a 	macl %d6,%a3,%fp@\(10\)&,%d2
+    34c6:	aeee b826 000a 	macl %d6,%a3,%fp@\(10\)&,%sp
+    34cc:	a2a1 b806      	macl %d6,%a3,%a1@-,%d1
+    34d0:	a6e1 b806      	macl %d6,%a3,%a1@-,%a3
+    34d4:	a4a1 b806      	macl %d6,%a3,%a1@-,%d2
+    34d8:	aee1 b806      	macl %d6,%a3,%a1@-,%sp
+    34dc:	a2a1 b826      	macl %d6,%a3,%a1@-&,%d1
+    34e0:	a6e1 b826      	macl %d6,%a3,%a1@-&,%a3
+    34e4:	a4a1 b826      	macl %d6,%a3,%a1@-&,%d2
+    34e8:	aee1 b826      	macl %d6,%a3,%a1@-&,%sp
+    34ec:	a293 ba06      	macl %d6,%a3,<<,%a3@,%d1
+    34f0:	a6d3 ba06      	macl %d6,%a3,<<,%a3@,%a3
+    34f4:	a493 ba06      	macl %d6,%a3,<<,%a3@,%d2
+    34f8:	aed3 ba06      	macl %d6,%a3,<<,%a3@,%sp
+    34fc:	a293 ba26      	macl %d6,%a3,<<,%a3@&,%d1
+    3500:	a6d3 ba26      	macl %d6,%a3,<<,%a3@&,%a3
+    3504:	a493 ba26      	macl %d6,%a3,<<,%a3@&,%d2
+    3508:	aed3 ba26      	macl %d6,%a3,<<,%a3@&,%sp
+    350c:	a29a ba06      	macl %d6,%a3,<<,%a2@\+,%d1
+    3510:	a6da ba06      	macl %d6,%a3,<<,%a2@\+,%a3
+    3514:	a49a ba06      	macl %d6,%a3,<<,%a2@\+,%d2
+    3518:	aeda ba06      	macl %d6,%a3,<<,%a2@\+,%sp
+    351c:	a29a ba26      	macl %d6,%a3,<<,%a2@\+&,%d1
+    3520:	a6da ba26      	macl %d6,%a3,<<,%a2@\+&,%a3
+    3524:	a49a ba26      	macl %d6,%a3,<<,%a2@\+&,%d2
+    3528:	aeda ba26      	macl %d6,%a3,<<,%a2@\+&,%sp
+    352c:	a2ae ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1
+    3532:	a6ee ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3
+    3538:	a4ae ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2
+    353e:	aeee ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp
+    3544:	a2ae ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1
+    354a:	a6ee ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3
+    3550:	a4ae ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2
+    3556:	aeee ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp
+    355c:	a2a1 ba06      	macl %d6,%a3,<<,%a1@-,%d1
+    3560:	a6e1 ba06      	macl %d6,%a3,<<,%a1@-,%a3
+    3564:	a4a1 ba06      	macl %d6,%a3,<<,%a1@-,%d2
+    3568:	aee1 ba06      	macl %d6,%a3,<<,%a1@-,%sp
+    356c:	a2a1 ba26      	macl %d6,%a3,<<,%a1@-&,%d1
+    3570:	a6e1 ba26      	macl %d6,%a3,<<,%a1@-&,%a3
+    3574:	a4a1 ba26      	macl %d6,%a3,<<,%a1@-&,%d2
+    3578:	aee1 ba26      	macl %d6,%a3,<<,%a1@-&,%sp
+    357c:	a293 be06      	macl %d6,%a3,>>,%a3@,%d1
+    3580:	a6d3 be06      	macl %d6,%a3,>>,%a3@,%a3
+    3584:	a493 be06      	macl %d6,%a3,>>,%a3@,%d2
+    3588:	aed3 be06      	macl %d6,%a3,>>,%a3@,%sp
+    358c:	a293 be26      	macl %d6,%a3,>>,%a3@&,%d1
+    3590:	a6d3 be26      	macl %d6,%a3,>>,%a3@&,%a3
+    3594:	a493 be26      	macl %d6,%a3,>>,%a3@&,%d2
+    3598:	aed3 be26      	macl %d6,%a3,>>,%a3@&,%sp
+    359c:	a29a be06      	macl %d6,%a3,>>,%a2@\+,%d1
+    35a0:	a6da be06      	macl %d6,%a3,>>,%a2@\+,%a3
+    35a4:	a49a be06      	macl %d6,%a3,>>,%a2@\+,%d2
+    35a8:	aeda be06      	macl %d6,%a3,>>,%a2@\+,%sp
+    35ac:	a29a be26      	macl %d6,%a3,>>,%a2@\+&,%d1
+    35b0:	a6da be26      	macl %d6,%a3,>>,%a2@\+&,%a3
+    35b4:	a49a be26      	macl %d6,%a3,>>,%a2@\+&,%d2
+    35b8:	aeda be26      	macl %d6,%a3,>>,%a2@\+&,%sp
+    35bc:	a2ae be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1
+    35c2:	a6ee be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3
+    35c8:	a4ae be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2
+    35ce:	aeee be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp
+    35d4:	a2ae be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1
+    35da:	a6ee be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3
+    35e0:	a4ae be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2
+    35e6:	aeee be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp
+    35ec:	a2a1 be06      	macl %d6,%a3,>>,%a1@-,%d1
+    35f0:	a6e1 be06      	macl %d6,%a3,>>,%a1@-,%a3
+    35f4:	a4a1 be06      	macl %d6,%a3,>>,%a1@-,%d2
+    35f8:	aee1 be06      	macl %d6,%a3,>>,%a1@-,%sp
+    35fc:	a2a1 be26      	macl %d6,%a3,>>,%a1@-&,%d1
+    3600:	a6e1 be26      	macl %d6,%a3,>>,%a1@-&,%a3
+    3604:	a4a1 be26      	macl %d6,%a3,>>,%a1@-&,%d2
+    3608:	aee1 be26      	macl %d6,%a3,>>,%a1@-&,%sp
+    360c:	a293 ba06      	macl %d6,%a3,<<,%a3@,%d1
+    3610:	a6d3 ba06      	macl %d6,%a3,<<,%a3@,%a3
+    3614:	a493 ba06      	macl %d6,%a3,<<,%a3@,%d2
+    3618:	aed3 ba06      	macl %d6,%a3,<<,%a3@,%sp
+    361c:	a293 ba26      	macl %d6,%a3,<<,%a3@&,%d1
+    3620:	a6d3 ba26      	macl %d6,%a3,<<,%a3@&,%a3
+    3624:	a493 ba26      	macl %d6,%a3,<<,%a3@&,%d2
+    3628:	aed3 ba26      	macl %d6,%a3,<<,%a3@&,%sp
+    362c:	a29a ba06      	macl %d6,%a3,<<,%a2@\+,%d1
+    3630:	a6da ba06      	macl %d6,%a3,<<,%a2@\+,%a3
+    3634:	a49a ba06      	macl %d6,%a3,<<,%a2@\+,%d2
+    3638:	aeda ba06      	macl %d6,%a3,<<,%a2@\+,%sp
+    363c:	a29a ba26      	macl %d6,%a3,<<,%a2@\+&,%d1
+    3640:	a6da ba26      	macl %d6,%a3,<<,%a2@\+&,%a3
+    3644:	a49a ba26      	macl %d6,%a3,<<,%a2@\+&,%d2
+    3648:	aeda ba26      	macl %d6,%a3,<<,%a2@\+&,%sp
+    364c:	a2ae ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d1
+    3652:	a6ee ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%a3
+    3658:	a4ae ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%d2
+    365e:	aeee ba06 000a 	macl %d6,%a3,<<,%fp@\(10\),%sp
+    3664:	a2ae ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d1
+    366a:	a6ee ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%a3
+    3670:	a4ae ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%d2
+    3676:	aeee ba26 000a 	macl %d6,%a3,<<,%fp@\(10\)&,%sp
+    367c:	a2a1 ba06      	macl %d6,%a3,<<,%a1@-,%d1
+    3680:	a6e1 ba06      	macl %d6,%a3,<<,%a1@-,%a3
+    3684:	a4a1 ba06      	macl %d6,%a3,<<,%a1@-,%d2
+    3688:	aee1 ba06      	macl %d6,%a3,<<,%a1@-,%sp
+    368c:	a2a1 ba26      	macl %d6,%a3,<<,%a1@-&,%d1
+    3690:	a6e1 ba26      	macl %d6,%a3,<<,%a1@-&,%a3
+    3694:	a4a1 ba26      	macl %d6,%a3,<<,%a1@-&,%d2
+    3698:	aee1 ba26      	macl %d6,%a3,<<,%a1@-&,%sp
+    369c:	a293 be06      	macl %d6,%a3,>>,%a3@,%d1
+    36a0:	a6d3 be06      	macl %d6,%a3,>>,%a3@,%a3
+    36a4:	a493 be06      	macl %d6,%a3,>>,%a3@,%d2
+    36a8:	aed3 be06      	macl %d6,%a3,>>,%a3@,%sp
+    36ac:	a293 be26      	macl %d6,%a3,>>,%a3@&,%d1
+    36b0:	a6d3 be26      	macl %d6,%a3,>>,%a3@&,%a3
+    36b4:	a493 be26      	macl %d6,%a3,>>,%a3@&,%d2
+    36b8:	aed3 be26      	macl %d6,%a3,>>,%a3@&,%sp
+    36bc:	a29a be06      	macl %d6,%a3,>>,%a2@\+,%d1
+    36c0:	a6da be06      	macl %d6,%a3,>>,%a2@\+,%a3
+    36c4:	a49a be06      	macl %d6,%a3,>>,%a2@\+,%d2
+    36c8:	aeda be06      	macl %d6,%a3,>>,%a2@\+,%sp
+    36cc:	a29a be26      	macl %d6,%a3,>>,%a2@\+&,%d1
+    36d0:	a6da be26      	macl %d6,%a3,>>,%a2@\+&,%a3
+    36d4:	a49a be26      	macl %d6,%a3,>>,%a2@\+&,%d2
+    36d8:	aeda be26      	macl %d6,%a3,>>,%a2@\+&,%sp
+    36dc:	a2ae be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d1
+    36e2:	a6ee be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%a3
+    36e8:	a4ae be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%d2
+    36ee:	aeee be06 000a 	macl %d6,%a3,>>,%fp@\(10\),%sp
+    36f4:	a2ae be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d1
+    36fa:	a6ee be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%a3
+    3700:	a4ae be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%d2
+    3706:	aeee be26 000a 	macl %d6,%a3,>>,%fp@\(10\)&,%sp
+    370c:	a2a1 be06      	macl %d6,%a3,>>,%a1@-,%d1
+    3710:	a6e1 be06      	macl %d6,%a3,>>,%a1@-,%a3
+    3714:	a4a1 be06      	macl %d6,%a3,>>,%a1@-,%d2
+    3718:	aee1 be06      	macl %d6,%a3,>>,%a1@-,%sp
+    371c:	a2a1 be26      	macl %d6,%a3,>>,%a1@-&,%d1
+    3720:	a6e1 be26      	macl %d6,%a3,>>,%a1@-&,%a3
+    3724:	a4a1 be26      	macl %d6,%a3,>>,%a1@-&,%d2
+    3728:	aee1 be26      	macl %d6,%a3,>>,%a1@-&,%sp
+    372c:	a293 4806      	macl %d6,%d4,%a3@,%d1
+    3730:	a6d3 4806      	macl %d6,%d4,%a3@,%a3
+    3734:	a493 4806      	macl %d6,%d4,%a3@,%d2
+    3738:	aed3 4806      	macl %d6,%d4,%a3@,%sp
+    373c:	a293 4826      	macl %d6,%d4,%a3@&,%d1
+    3740:	a6d3 4826      	macl %d6,%d4,%a3@&,%a3
+    3744:	a493 4826      	macl %d6,%d4,%a3@&,%d2
+    3748:	aed3 4826      	macl %d6,%d4,%a3@&,%sp
+    374c:	a29a 4806      	macl %d6,%d4,%a2@\+,%d1
+    3750:	a6da 4806      	macl %d6,%d4,%a2@\+,%a3
+    3754:	a49a 4806      	macl %d6,%d4,%a2@\+,%d2
+    3758:	aeda 4806      	macl %d6,%d4,%a2@\+,%sp
+    375c:	a29a 4826      	macl %d6,%d4,%a2@\+&,%d1
+    3760:	a6da 4826      	macl %d6,%d4,%a2@\+&,%a3
+    3764:	a49a 4826      	macl %d6,%d4,%a2@\+&,%d2
+    3768:	aeda 4826      	macl %d6,%d4,%a2@\+&,%sp
+    376c:	a2ae 4806 000a 	macl %d6,%d4,%fp@\(10\),%d1
+    3772:	a6ee 4806 000a 	macl %d6,%d4,%fp@\(10\),%a3
+    3778:	a4ae 4806 000a 	macl %d6,%d4,%fp@\(10\),%d2
+    377e:	aeee 4806 000a 	macl %d6,%d4,%fp@\(10\),%sp
+    3784:	a2ae 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%d1
+    378a:	a6ee 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%a3
+    3790:	a4ae 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%d2
+    3796:	aeee 4826 000a 	macl %d6,%d4,%fp@\(10\)&,%sp
+    379c:	a2a1 4806      	macl %d6,%d4,%a1@-,%d1
+    37a0:	a6e1 4806      	macl %d6,%d4,%a1@-,%a3
+    37a4:	a4a1 4806      	macl %d6,%d4,%a1@-,%d2
+    37a8:	aee1 4806      	macl %d6,%d4,%a1@-,%sp
+    37ac:	a2a1 4826      	macl %d6,%d4,%a1@-&,%d1
+    37b0:	a6e1 4826      	macl %d6,%d4,%a1@-&,%a3
+    37b4:	a4a1 4826      	macl %d6,%d4,%a1@-&,%d2
+    37b8:	aee1 4826      	macl %d6,%d4,%a1@-&,%sp
+    37bc:	a293 4a06      	macl %d6,%d4,<<,%a3@,%d1
+    37c0:	a6d3 4a06      	macl %d6,%d4,<<,%a3@,%a3
+    37c4:	a493 4a06      	macl %d6,%d4,<<,%a3@,%d2
+    37c8:	aed3 4a06      	macl %d6,%d4,<<,%a3@,%sp
+    37cc:	a293 4a26      	macl %d6,%d4,<<,%a3@&,%d1
+    37d0:	a6d3 4a26      	macl %d6,%d4,<<,%a3@&,%a3
+    37d4:	a493 4a26      	macl %d6,%d4,<<,%a3@&,%d2
+    37d8:	aed3 4a26      	macl %d6,%d4,<<,%a3@&,%sp
+    37dc:	a29a 4a06      	macl %d6,%d4,<<,%a2@\+,%d1
+    37e0:	a6da 4a06      	macl %d6,%d4,<<,%a2@\+,%a3
+    37e4:	a49a 4a06      	macl %d6,%d4,<<,%a2@\+,%d2
+    37e8:	aeda 4a06      	macl %d6,%d4,<<,%a2@\+,%sp
+    37ec:	a29a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d1
+    37f0:	a6da 4a26      	macl %d6,%d4,<<,%a2@\+&,%a3
+    37f4:	a49a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d2
+    37f8:	aeda 4a26      	macl %d6,%d4,<<,%a2@\+&,%sp
+    37fc:	a2ae 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1
+    3802:	a6ee 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3
+    3808:	a4ae 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2
+    380e:	aeee 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp
+    3814:	a2ae 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1
+    381a:	a6ee 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3
+    3820:	a4ae 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2
+    3826:	aeee 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp
+    382c:	a2a1 4a06      	macl %d6,%d4,<<,%a1@-,%d1
+    3830:	a6e1 4a06      	macl %d6,%d4,<<,%a1@-,%a3
+    3834:	a4a1 4a06      	macl %d6,%d4,<<,%a1@-,%d2
+    3838:	aee1 4a06      	macl %d6,%d4,<<,%a1@-,%sp
+    383c:	a2a1 4a26      	macl %d6,%d4,<<,%a1@-&,%d1
+    3840:	a6e1 4a26      	macl %d6,%d4,<<,%a1@-&,%a3
+    3844:	a4a1 4a26      	macl %d6,%d4,<<,%a1@-&,%d2
+    3848:	aee1 4a26      	macl %d6,%d4,<<,%a1@-&,%sp
+    384c:	a293 4e06      	macl %d6,%d4,>>,%a3@,%d1
+    3850:	a6d3 4e06      	macl %d6,%d4,>>,%a3@,%a3
+    3854:	a493 4e06      	macl %d6,%d4,>>,%a3@,%d2
+    3858:	aed3 4e06      	macl %d6,%d4,>>,%a3@,%sp
+    385c:	a293 4e26      	macl %d6,%d4,>>,%a3@&,%d1
+    3860:	a6d3 4e26      	macl %d6,%d4,>>,%a3@&,%a3
+    3864:	a493 4e26      	macl %d6,%d4,>>,%a3@&,%d2
+    3868:	aed3 4e26      	macl %d6,%d4,>>,%a3@&,%sp
+    386c:	a29a 4e06      	macl %d6,%d4,>>,%a2@\+,%d1
+    3870:	a6da 4e06      	macl %d6,%d4,>>,%a2@\+,%a3
+    3874:	a49a 4e06      	macl %d6,%d4,>>,%a2@\+,%d2
+    3878:	aeda 4e06      	macl %d6,%d4,>>,%a2@\+,%sp
+    387c:	a29a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d1
+    3880:	a6da 4e26      	macl %d6,%d4,>>,%a2@\+&,%a3
+    3884:	a49a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d2
+    3888:	aeda 4e26      	macl %d6,%d4,>>,%a2@\+&,%sp
+    388c:	a2ae 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1
+    3892:	a6ee 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3
+    3898:	a4ae 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2
+    389e:	aeee 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp
+    38a4:	a2ae 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1
+    38aa:	a6ee 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3
+    38b0:	a4ae 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2
+    38b6:	aeee 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp
+    38bc:	a2a1 4e06      	macl %d6,%d4,>>,%a1@-,%d1
+    38c0:	a6e1 4e06      	macl %d6,%d4,>>,%a1@-,%a3
+    38c4:	a4a1 4e06      	macl %d6,%d4,>>,%a1@-,%d2
+    38c8:	aee1 4e06      	macl %d6,%d4,>>,%a1@-,%sp
+    38cc:	a2a1 4e26      	macl %d6,%d4,>>,%a1@-&,%d1
+    38d0:	a6e1 4e26      	macl %d6,%d4,>>,%a1@-&,%a3
+    38d4:	a4a1 4e26      	macl %d6,%d4,>>,%a1@-&,%d2
+    38d8:	aee1 4e26      	macl %d6,%d4,>>,%a1@-&,%sp
+    38dc:	a293 4a06      	macl %d6,%d4,<<,%a3@,%d1
+    38e0:	a6d3 4a06      	macl %d6,%d4,<<,%a3@,%a3
+    38e4:	a493 4a06      	macl %d6,%d4,<<,%a3@,%d2
+    38e8:	aed3 4a06      	macl %d6,%d4,<<,%a3@,%sp
+    38ec:	a293 4a26      	macl %d6,%d4,<<,%a3@&,%d1
+    38f0:	a6d3 4a26      	macl %d6,%d4,<<,%a3@&,%a3
+    38f4:	a493 4a26      	macl %d6,%d4,<<,%a3@&,%d2
+    38f8:	aed3 4a26      	macl %d6,%d4,<<,%a3@&,%sp
+    38fc:	a29a 4a06      	macl %d6,%d4,<<,%a2@\+,%d1
+    3900:	a6da 4a06      	macl %d6,%d4,<<,%a2@\+,%a3
+    3904:	a49a 4a06      	macl %d6,%d4,<<,%a2@\+,%d2
+    3908:	aeda 4a06      	macl %d6,%d4,<<,%a2@\+,%sp
+    390c:	a29a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d1
+    3910:	a6da 4a26      	macl %d6,%d4,<<,%a2@\+&,%a3
+    3914:	a49a 4a26      	macl %d6,%d4,<<,%a2@\+&,%d2
+    3918:	aeda 4a26      	macl %d6,%d4,<<,%a2@\+&,%sp
+    391c:	a2ae 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d1
+    3922:	a6ee 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%a3
+    3928:	a4ae 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%d2
+    392e:	aeee 4a06 000a 	macl %d6,%d4,<<,%fp@\(10\),%sp
+    3934:	a2ae 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d1
+    393a:	a6ee 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%a3
+    3940:	a4ae 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%d2
+    3946:	aeee 4a26 000a 	macl %d6,%d4,<<,%fp@\(10\)&,%sp
+    394c:	a2a1 4a06      	macl %d6,%d4,<<,%a1@-,%d1
+    3950:	a6e1 4a06      	macl %d6,%d4,<<,%a1@-,%a3
+    3954:	a4a1 4a06      	macl %d6,%d4,<<,%a1@-,%d2
+    3958:	aee1 4a06      	macl %d6,%d4,<<,%a1@-,%sp
+    395c:	a2a1 4a26      	macl %d6,%d4,<<,%a1@-&,%d1
+    3960:	a6e1 4a26      	macl %d6,%d4,<<,%a1@-&,%a3
+    3964:	a4a1 4a26      	macl %d6,%d4,<<,%a1@-&,%d2
+    3968:	aee1 4a26      	macl %d6,%d4,<<,%a1@-&,%sp
+    396c:	a293 4e06      	macl %d6,%d4,>>,%a3@,%d1
+    3970:	a6d3 4e06      	macl %d6,%d4,>>,%a3@,%a3
+    3974:	a493 4e06      	macl %d6,%d4,>>,%a3@,%d2
+    3978:	aed3 4e06      	macl %d6,%d4,>>,%a3@,%sp
+    397c:	a293 4e26      	macl %d6,%d4,>>,%a3@&,%d1
+    3980:	a6d3 4e26      	macl %d6,%d4,>>,%a3@&,%a3
+    3984:	a493 4e26      	macl %d6,%d4,>>,%a3@&,%d2
+    3988:	aed3 4e26      	macl %d6,%d4,>>,%a3@&,%sp
+    398c:	a29a 4e06      	macl %d6,%d4,>>,%a2@\+,%d1
+    3990:	a6da 4e06      	macl %d6,%d4,>>,%a2@\+,%a3
+    3994:	a49a 4e06      	macl %d6,%d4,>>,%a2@\+,%d2
+    3998:	aeda 4e06      	macl %d6,%d4,>>,%a2@\+,%sp
+    399c:	a29a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d1
+    39a0:	a6da 4e26      	macl %d6,%d4,>>,%a2@\+&,%a3
+    39a4:	a49a 4e26      	macl %d6,%d4,>>,%a2@\+&,%d2
+    39a8:	aeda 4e26      	macl %d6,%d4,>>,%a2@\+&,%sp
+    39ac:	a2ae 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d1
+    39b2:	a6ee 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%a3
+    39b8:	a4ae 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%d2
+    39be:	aeee 4e06 000a 	macl %d6,%d4,>>,%fp@\(10\),%sp
+    39c4:	a2ae 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d1
+    39ca:	a6ee 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%a3
+    39d0:	a4ae 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%d2
+    39d6:	aeee 4e26 000a 	macl %d6,%d4,>>,%fp@\(10\)&,%sp
+    39dc:	a2a1 4e06      	macl %d6,%d4,>>,%a1@-,%d1
+    39e0:	a6e1 4e06      	macl %d6,%d4,>>,%a1@-,%a3
+    39e4:	a4a1 4e06      	macl %d6,%d4,>>,%a1@-,%d2
+    39e8:	aee1 4e06      	macl %d6,%d4,>>,%a1@-,%sp
+    39ec:	a2a1 4e26      	macl %d6,%d4,>>,%a1@-&,%d1
+    39f0:	a6e1 4e26      	macl %d6,%d4,>>,%a1@-&,%a3
+    39f4:	a4a1 4e26      	macl %d6,%d4,>>,%a1@-&,%d2
+    39f8:	aee1 4e26      	macl %d6,%d4,>>,%a1@-&,%sp
diff --git a/gas/testsuite/gas/m68k/mcf-mac.s b/gas/testsuite/gas/m68k/mcf-mac.s
new file mode 100644
index 000000000000..5b59a106e06a
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mcf-mac.s
@@ -0,0 +1,3331 @@
+
+	.text
+
+	move.l %acc,%d2
+	move.l %acc,%a1
+
+	move.l %macsr,%a1
+	move.l %macsr,%d2
+
+	move.l %mask,%a1
+	move.l %mask,%d2
+	
+	move.l %macsr,%ccr
+	
+	move.l #0x12345678,%acc
+	move.l %d1,%acc
+	move.l %a2,%acc
+	
+	move.l #0x12345678,%macsr
+	move.l %d1,%macsr
+	move.l %a2,%macsr
+	
+	move.l #0x12345678,%mask
+	move.l %d1,%mask
+	move.l %a2,%mask
+
+	| automated from here
+				
+	mac.w %a1l,%a2u
+	mac.w %a1l,%a2u,<<
+	mac.w %a1l,%a2u,>>
+	mac.w %a1l,%a2u,#1
+	mac.w %a1l,%a2u,#-1
+	mac.w %a1l,%d3l
+	mac.w %a1l,%d3l,<<
+	mac.w %a1l,%d3l,>>
+	mac.w %a1l,%d3l,#1
+	mac.w %a1l,%d3l,#-1
+	mac.w %a1l,%a7u
+	mac.w %a1l,%a7u,<<
+	mac.w %a1l,%a7u,>>
+	mac.w %a1l,%a7u,#1
+	mac.w %a1l,%a7u,#-1
+	mac.w %a1l,%d1l
+	mac.w %a1l,%d1l,<<
+	mac.w %a1l,%d1l,>>
+	mac.w %a1l,%d1l,#1
+	mac.w %a1l,%d1l,#-1
+	mac.w %d2u,%a2u
+	mac.w %d2u,%a2u,<<
+	mac.w %d2u,%a2u,>>
+	mac.w %d2u,%a2u,#1
+	mac.w %d2u,%a2u,#-1
+	mac.w %d2u,%d3l
+	mac.w %d2u,%d3l,<<
+	mac.w %d2u,%d3l,>>
+	mac.w %d2u,%d3l,#1
+	mac.w %d2u,%d3l,#-1
+	mac.w %d2u,%a7u
+	mac.w %d2u,%a7u,<<
+	mac.w %d2u,%a7u,>>
+	mac.w %d2u,%a7u,#1
+	mac.w %d2u,%a7u,#-1
+	mac.w %d2u,%d1l
+	mac.w %d2u,%d1l,<<
+	mac.w %d2u,%d1l,>>
+	mac.w %d2u,%d1l,#1
+	mac.w %d2u,%d1l,#-1
+	mac.w %a5l,%a2u
+	mac.w %a5l,%a2u,<<
+	mac.w %a5l,%a2u,>>
+	mac.w %a5l,%a2u,#1
+	mac.w %a5l,%a2u,#-1
+	mac.w %a5l,%d3l
+	mac.w %a5l,%d3l,<<
+	mac.w %a5l,%d3l,>>
+	mac.w %a5l,%d3l,#1
+	mac.w %a5l,%d3l,#-1
+	mac.w %a5l,%a7u
+	mac.w %a5l,%a7u,<<
+	mac.w %a5l,%a7u,>>
+	mac.w %a5l,%a7u,#1
+	mac.w %a5l,%a7u,#-1
+	mac.w %a5l,%d1l
+	mac.w %a5l,%d1l,<<
+	mac.w %a5l,%d1l,>>
+	mac.w %a5l,%d1l,#1
+	mac.w %a5l,%d1l,#-1
+	mac.w %d6u,%a2u
+	mac.w %d6u,%a2u,<<
+	mac.w %d6u,%a2u,>>
+	mac.w %d6u,%a2u,#1
+	mac.w %d6u,%a2u,#-1
+	mac.w %d6u,%d3l
+	mac.w %d6u,%d3l,<<
+	mac.w %d6u,%d3l,>>
+	mac.w %d6u,%d3l,#1
+	mac.w %d6u,%d3l,#-1
+	mac.w %d6u,%a7u
+	mac.w %d6u,%a7u,<<
+	mac.w %d6u,%a7u,>>
+	mac.w %d6u,%a7u,#1
+	mac.w %d6u,%a7u,#-1
+	mac.w %d6u,%d1l
+	mac.w %d6u,%d1l,<<
+	mac.w %d6u,%d1l,>>
+	mac.w %d6u,%d1l,#1
+	mac.w %d6u,%d1l,#-1
+
+	mac.w %a1l,%a2u,(%a3),%d1
+	mac.w %a1l,%a2u,(%a3),%a3
+	mac.w %a1l,%a2u,(%a3),%d2
+	mac.w %a1l,%a2u,(%a3),%a7
+	mac.w %a1l,%a2u,(%a3)&,%d1
+	mac.w %a1l,%a2u,(%a3)&,%a3
+	mac.w %a1l,%a2u,(%a3)&,%d2
+	mac.w %a1l,%a2u,(%a3)&,%a7
+	mac.w %a1l,%a2u,(%a2)+,%d1
+	mac.w %a1l,%a2u,(%a2)+,%a3
+	mac.w %a1l,%a2u,(%a2)+,%d2
+	mac.w %a1l,%a2u,(%a2)+,%a7
+	mac.w %a1l,%a2u,(%a2)+&,%d1
+	mac.w %a1l,%a2u,(%a2)+&,%a3
+	mac.w %a1l,%a2u,(%a2)+&,%d2
+	mac.w %a1l,%a2u,(%a2)+&,%a7
+	mac.w %a1l,%a2u,10(%a6),%d1
+	mac.w %a1l,%a2u,10(%a6),%a3
+	mac.w %a1l,%a2u,10(%a6),%d2
+	mac.w %a1l,%a2u,10(%a6),%a7
+	mac.w %a1l,%a2u,10(%a6)&,%d1
+	mac.w %a1l,%a2u,10(%a6)&,%a3
+	mac.w %a1l,%a2u,10(%a6)&,%d2
+	mac.w %a1l,%a2u,10(%a6)&,%a7
+	mac.w %a1l,%a2u,-(%a1),%d1
+	mac.w %a1l,%a2u,-(%a1),%a3
+	mac.w %a1l,%a2u,-(%a1),%d2
+	mac.w %a1l,%a2u,-(%a1),%a7
+	mac.w %a1l,%a2u,-(%a1)&,%d1
+	mac.w %a1l,%a2u,-(%a1)&,%a3
+	mac.w %a1l,%a2u,-(%a1)&,%d2
+	mac.w %a1l,%a2u,-(%a1)&,%a7
+	mac.w %a1l,%a2u,<<,(%a3),%d1
+	mac.w %a1l,%a2u,<<,(%a3),%a3
+	mac.w %a1l,%a2u,<<,(%a3),%d2
+	mac.w %a1l,%a2u,<<,(%a3),%a7
+	mac.w %a1l,%a2u,<<,(%a3)&,%d1
+	mac.w %a1l,%a2u,<<,(%a3)&,%a3
+	mac.w %a1l,%a2u,<<,(%a3)&,%d2
+	mac.w %a1l,%a2u,<<,(%a3)&,%a7
+	mac.w %a1l,%a2u,<<,(%a2)+,%d1
+	mac.w %a1l,%a2u,<<,(%a2)+,%a3
+	mac.w %a1l,%a2u,<<,(%a2)+,%d2
+	mac.w %a1l,%a2u,<<,(%a2)+,%a7
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d1
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a3
+	mac.w %a1l,%a2u,<<,(%a2)+&,%d2
+	mac.w %a1l,%a2u,<<,(%a2)+&,%a7
+	mac.w %a1l,%a2u,<<,10(%a6),%d1
+	mac.w %a1l,%a2u,<<,10(%a6),%a3
+	mac.w %a1l,%a2u,<<,10(%a6),%d2
+	mac.w %a1l,%a2u,<<,10(%a6),%a7
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d1
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a3
+	mac.w %a1l,%a2u,<<,10(%a6)&,%d2
+	mac.w %a1l,%a2u,<<,10(%a6)&,%a7
+	mac.w %a1l,%a2u,<<,-(%a1),%d1
+	mac.w %a1l,%a2u,<<,-(%a1),%a3
+	mac.w %a1l,%a2u,<<,-(%a1),%d2
+	mac.w %a1l,%a2u,<<,-(%a1),%a7
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d1
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a3
+	mac.w %a1l,%a2u,<<,-(%a1)&,%d2
+	mac.w %a1l,%a2u,<<,-(%a1)&,%a7
+	mac.w %a1l,%a2u,>>,(%a3),%d1
+	mac.w %a1l,%a2u,>>,(%a3),%a3
+	mac.w %a1l,%a2u,>>,(%a3),%d2
+	mac.w %a1l,%a2u,>>,(%a3),%a7
+	mac.w %a1l,%a2u,>>,(%a3)&,%d1
+	mac.w %a1l,%a2u,>>,(%a3)&,%a3
+	mac.w %a1l,%a2u,>>,(%a3)&,%d2
+	mac.w %a1l,%a2u,>>,(%a3)&,%a7
+	mac.w %a1l,%a2u,>>,(%a2)+,%d1
+	mac.w %a1l,%a2u,>>,(%a2)+,%a3
+	mac.w %a1l,%a2u,>>,(%a2)+,%d2
+	mac.w %a1l,%a2u,>>,(%a2)+,%a7
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d1
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a3
+	mac.w %a1l,%a2u,>>,(%a2)+&,%d2
+	mac.w %a1l,%a2u,>>,(%a2)+&,%a7
+	mac.w %a1l,%a2u,>>,10(%a6),%d1
+	mac.w %a1l,%a2u,>>,10(%a6),%a3
+	mac.w %a1l,%a2u,>>,10(%a6),%d2
+	mac.w %a1l,%a2u,>>,10(%a6),%a7
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d1
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a3
+	mac.w %a1l,%a2u,>>,10(%a6)&,%d2
+	mac.w %a1l,%a2u,>>,10(%a6)&,%a7
+	mac.w %a1l,%a2u,>>,-(%a1),%d1
+	mac.w %a1l,%a2u,>>,-(%a1),%a3
+	mac.w %a1l,%a2u,>>,-(%a1),%d2
+	mac.w %a1l,%a2u,>>,-(%a1),%a7
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d1
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a3
+	mac.w %a1l,%a2u,>>,-(%a1)&,%d2
+	mac.w %a1l,%a2u,>>,-(%a1)&,%a7
+	mac.w %a1l,%a2u,#1,(%a3),%d1
+	mac.w %a1l,%a2u,#1,(%a3),%a3
+	mac.w %a1l,%a2u,#1,(%a3),%d2
+	mac.w %a1l,%a2u,#1,(%a3),%a7
+	mac.w %a1l,%a2u,#1,(%a3)&,%d1
+	mac.w %a1l,%a2u,#1,(%a3)&,%a3
+	mac.w %a1l,%a2u,#1,(%a3)&,%d2
+	mac.w %a1l,%a2u,#1,(%a3)&,%a7
+	mac.w %a1l,%a2u,#1,(%a2)+,%d1
+	mac.w %a1l,%a2u,#1,(%a2)+,%a3
+	mac.w %a1l,%a2u,#1,(%a2)+,%d2
+	mac.w %a1l,%a2u,#1,(%a2)+,%a7
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d1
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a3
+	mac.w %a1l,%a2u,#1,(%a2)+&,%d2
+	mac.w %a1l,%a2u,#1,(%a2)+&,%a7
+	mac.w %a1l,%a2u,#1,10(%a6),%d1
+	mac.w %a1l,%a2u,#1,10(%a6),%a3
+	mac.w %a1l,%a2u,#1,10(%a6),%d2
+	mac.w %a1l,%a2u,#1,10(%a6),%a7
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d1
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a3
+	mac.w %a1l,%a2u,#1,10(%a6)&,%d2
+	mac.w %a1l,%a2u,#1,10(%a6)&,%a7
+	mac.w %a1l,%a2u,#1,-(%a1),%d1
+	mac.w %a1l,%a2u,#1,-(%a1),%a3
+	mac.w %a1l,%a2u,#1,-(%a1),%d2
+	mac.w %a1l,%a2u,#1,-(%a1),%a7
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d1
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a3
+	mac.w %a1l,%a2u,#1,-(%a1)&,%d2
+	mac.w %a1l,%a2u,#1,-(%a1)&,%a7
+	mac.w %a1l,%a2u,#-1,(%a3),%d1
+	mac.w %a1l,%a2u,#-1,(%a3),%a3
+	mac.w %a1l,%a2u,#-1,(%a3),%d2
+	mac.w %a1l,%a2u,#-1,(%a3),%a7
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d1
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a3
+	mac.w %a1l,%a2u,#-1,(%a3)&,%d2
+	mac.w %a1l,%a2u,#-1,(%a3)&,%a7
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d1
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a3
+	mac.w %a1l,%a2u,#-1,(%a2)+,%d2
+	mac.w %a1l,%a2u,#-1,(%a2)+,%a7
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d1
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a3
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%d2
+	mac.w %a1l,%a2u,#-1,(%a2)+&,%a7
+	mac.w %a1l,%a2u,#-1,10(%a6),%d1
+	mac.w %a1l,%a2u,#-1,10(%a6),%a3
+	mac.w %a1l,%a2u,#-1,10(%a6),%d2
+	mac.w %a1l,%a2u,#-1,10(%a6),%a7
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d1
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a3
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%d2
+	mac.w %a1l,%a2u,#-1,10(%a6)&,%a7
+	mac.w %a1l,%a2u,#-1,-(%a1),%d1
+	mac.w %a1l,%a2u,#-1,-(%a1),%a3
+	mac.w %a1l,%a2u,#-1,-(%a1),%d2
+	mac.w %a1l,%a2u,#-1,-(%a1),%a7
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d1
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a3
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%d2
+	mac.w %a1l,%a2u,#-1,-(%a1)&,%a7
+	mac.w %a1l,%d3l,(%a3),%d1
+	mac.w %a1l,%d3l,(%a3),%a3
+	mac.w %a1l,%d3l,(%a3),%d2
+	mac.w %a1l,%d3l,(%a3),%a7
+	mac.w %a1l,%d3l,(%a3)&,%d1
+	mac.w %a1l,%d3l,(%a3)&,%a3
+	mac.w %a1l,%d3l,(%a3)&,%d2
+	mac.w %a1l,%d3l,(%a3)&,%a7
+	mac.w %a1l,%d3l,(%a2)+,%d1
+	mac.w %a1l,%d3l,(%a2)+,%a3
+	mac.w %a1l,%d3l,(%a2)+,%d2
+	mac.w %a1l,%d3l,(%a2)+,%a7
+	mac.w %a1l,%d3l,(%a2)+&,%d1
+	mac.w %a1l,%d3l,(%a2)+&,%a3
+	mac.w %a1l,%d3l,(%a2)+&,%d2
+	mac.w %a1l,%d3l,(%a2)+&,%a7
+	mac.w %a1l,%d3l,10(%a6),%d1
+	mac.w %a1l,%d3l,10(%a6),%a3
+	mac.w %a1l,%d3l,10(%a6),%d2
+	mac.w %a1l,%d3l,10(%a6),%a7
+	mac.w %a1l,%d3l,10(%a6)&,%d1
+	mac.w %a1l,%d3l,10(%a6)&,%a3
+	mac.w %a1l,%d3l,10(%a6)&,%d2
+	mac.w %a1l,%d3l,10(%a6)&,%a7
+	mac.w %a1l,%d3l,-(%a1),%d1
+	mac.w %a1l,%d3l,-(%a1),%a3
+	mac.w %a1l,%d3l,-(%a1),%d2
+	mac.w %a1l,%d3l,-(%a1),%a7
+	mac.w %a1l,%d3l,-(%a1)&,%d1
+	mac.w %a1l,%d3l,-(%a1)&,%a3
+	mac.w %a1l,%d3l,-(%a1)&,%d2
+	mac.w %a1l,%d3l,-(%a1)&,%a7
+	mac.w %a1l,%d3l,<<,(%a3),%d1
+	mac.w %a1l,%d3l,<<,(%a3),%a3
+	mac.w %a1l,%d3l,<<,(%a3),%d2
+	mac.w %a1l,%d3l,<<,(%a3),%a7
+	mac.w %a1l,%d3l,<<,(%a3)&,%d1
+	mac.w %a1l,%d3l,<<,(%a3)&,%a3
+	mac.w %a1l,%d3l,<<,(%a3)&,%d2
+	mac.w %a1l,%d3l,<<,(%a3)&,%a7
+	mac.w %a1l,%d3l,<<,(%a2)+,%d1
+	mac.w %a1l,%d3l,<<,(%a2)+,%a3
+	mac.w %a1l,%d3l,<<,(%a2)+,%d2
+	mac.w %a1l,%d3l,<<,(%a2)+,%a7
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d1
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a3
+	mac.w %a1l,%d3l,<<,(%a2)+&,%d2
+	mac.w %a1l,%d3l,<<,(%a2)+&,%a7
+	mac.w %a1l,%d3l,<<,10(%a6),%d1
+	mac.w %a1l,%d3l,<<,10(%a6),%a3
+	mac.w %a1l,%d3l,<<,10(%a6),%d2
+	mac.w %a1l,%d3l,<<,10(%a6),%a7
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d1
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a3
+	mac.w %a1l,%d3l,<<,10(%a6)&,%d2
+	mac.w %a1l,%d3l,<<,10(%a6)&,%a7
+	mac.w %a1l,%d3l,<<,-(%a1),%d1
+	mac.w %a1l,%d3l,<<,-(%a1),%a3
+	mac.w %a1l,%d3l,<<,-(%a1),%d2
+	mac.w %a1l,%d3l,<<,-(%a1),%a7
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d1
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a3
+	mac.w %a1l,%d3l,<<,-(%a1)&,%d2
+	mac.w %a1l,%d3l,<<,-(%a1)&,%a7
+	mac.w %a1l,%d3l,>>,(%a3),%d1
+	mac.w %a1l,%d3l,>>,(%a3),%a3
+	mac.w %a1l,%d3l,>>,(%a3),%d2
+	mac.w %a1l,%d3l,>>,(%a3),%a7
+	mac.w %a1l,%d3l,>>,(%a3)&,%d1
+	mac.w %a1l,%d3l,>>,(%a3)&,%a3
+	mac.w %a1l,%d3l,>>,(%a3)&,%d2
+	mac.w %a1l,%d3l,>>,(%a3)&,%a7
+	mac.w %a1l,%d3l,>>,(%a2)+,%d1
+	mac.w %a1l,%d3l,>>,(%a2)+,%a3
+	mac.w %a1l,%d3l,>>,(%a2)+,%d2
+	mac.w %a1l,%d3l,>>,(%a2)+,%a7
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d1
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a3
+	mac.w %a1l,%d3l,>>,(%a2)+&,%d2
+	mac.w %a1l,%d3l,>>,(%a2)+&,%a7
+	mac.w %a1l,%d3l,>>,10(%a6),%d1
+	mac.w %a1l,%d3l,>>,10(%a6),%a3
+	mac.w %a1l,%d3l,>>,10(%a6),%d2
+	mac.w %a1l,%d3l,>>,10(%a6),%a7
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d1
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a3
+	mac.w %a1l,%d3l,>>,10(%a6)&,%d2
+	mac.w %a1l,%d3l,>>,10(%a6)&,%a7
+	mac.w %a1l,%d3l,>>,-(%a1),%d1
+	mac.w %a1l,%d3l,>>,-(%a1),%a3
+	mac.w %a1l,%d3l,>>,-(%a1),%d2
+	mac.w %a1l,%d3l,>>,-(%a1),%a7
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d1
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a3
+	mac.w %a1l,%d3l,>>,-(%a1)&,%d2
+	mac.w %a1l,%d3l,>>,-(%a1)&,%a7
+	mac.w %a1l,%d3l,#1,(%a3),%d1
+	mac.w %a1l,%d3l,#1,(%a3),%a3
+	mac.w %a1l,%d3l,#1,(%a3),%d2
+	mac.w %a1l,%d3l,#1,(%a3),%a7
+	mac.w %a1l,%d3l,#1,(%a3)&,%d1
+	mac.w %a1l,%d3l,#1,(%a3)&,%a3
+	mac.w %a1l,%d3l,#1,(%a3)&,%d2
+	mac.w %a1l,%d3l,#1,(%a3)&,%a7
+	mac.w %a1l,%d3l,#1,(%a2)+,%d1
+	mac.w %a1l,%d3l,#1,(%a2)+,%a3
+	mac.w %a1l,%d3l,#1,(%a2)+,%d2
+	mac.w %a1l,%d3l,#1,(%a2)+,%a7
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d1
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a3
+	mac.w %a1l,%d3l,#1,(%a2)+&,%d2
+	mac.w %a1l,%d3l,#1,(%a2)+&,%a7
+	mac.w %a1l,%d3l,#1,10(%a6),%d1
+	mac.w %a1l,%d3l,#1,10(%a6),%a3
+	mac.w %a1l,%d3l,#1,10(%a6),%d2
+	mac.w %a1l,%d3l,#1,10(%a6),%a7
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d1
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a3
+	mac.w %a1l,%d3l,#1,10(%a6)&,%d2
+	mac.w %a1l,%d3l,#1,10(%a6)&,%a7
+	mac.w %a1l,%d3l,#1,-(%a1),%d1
+	mac.w %a1l,%d3l,#1,-(%a1),%a3
+	mac.w %a1l,%d3l,#1,-(%a1),%d2
+	mac.w %a1l,%d3l,#1,-(%a1),%a7
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d1
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a3
+	mac.w %a1l,%d3l,#1,-(%a1)&,%d2
+	mac.w %a1l,%d3l,#1,-(%a1)&,%a7
+	mac.w %a1l,%d3l,#-1,(%a3),%d1
+	mac.w %a1l,%d3l,#-1,(%a3),%a3
+	mac.w %a1l,%d3l,#-1,(%a3),%d2
+	mac.w %a1l,%d3l,#-1,(%a3),%a7
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d1
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a3
+	mac.w %a1l,%d3l,#-1,(%a3)&,%d2
+	mac.w %a1l,%d3l,#-1,(%a3)&,%a7
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d1
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a3
+	mac.w %a1l,%d3l,#-1,(%a2)+,%d2
+	mac.w %a1l,%d3l,#-1,(%a2)+,%a7
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d1
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a3
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%d2
+	mac.w %a1l,%d3l,#-1,(%a2)+&,%a7
+	mac.w %a1l,%d3l,#-1,10(%a6),%d1
+	mac.w %a1l,%d3l,#-1,10(%a6),%a3
+	mac.w %a1l,%d3l,#-1,10(%a6),%d2
+	mac.w %a1l,%d3l,#-1,10(%a6),%a7
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d1
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a3
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%d2
+	mac.w %a1l,%d3l,#-1,10(%a6)&,%a7
+	mac.w %a1l,%d3l,#-1,-(%a1),%d1
+	mac.w %a1l,%d3l,#-1,-(%a1),%a3
+	mac.w %a1l,%d3l,#-1,-(%a1),%d2
+	mac.w %a1l,%d3l,#-1,-(%a1),%a7
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d1
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a3
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%d2
+	mac.w %a1l,%d3l,#-1,-(%a1)&,%a7
+	mac.w %a1l,%a7u,(%a3),%d1
+	mac.w %a1l,%a7u,(%a3),%a3
+	mac.w %a1l,%a7u,(%a3),%d2
+	mac.w %a1l,%a7u,(%a3),%a7
+	mac.w %a1l,%a7u,(%a3)&,%d1
+	mac.w %a1l,%a7u,(%a3)&,%a3
+	mac.w %a1l,%a7u,(%a3)&,%d2
+	mac.w %a1l,%a7u,(%a3)&,%a7
+	mac.w %a1l,%a7u,(%a2)+,%d1
+	mac.w %a1l,%a7u,(%a2)+,%a3
+	mac.w %a1l,%a7u,(%a2)+,%d2
+	mac.w %a1l,%a7u,(%a2)+,%a7
+	mac.w %a1l,%a7u,(%a2)+&,%d1
+	mac.w %a1l,%a7u,(%a2)+&,%a3
+	mac.w %a1l,%a7u,(%a2)+&,%d2
+	mac.w %a1l,%a7u,(%a2)+&,%a7
+	mac.w %a1l,%a7u,10(%a6),%d1
+	mac.w %a1l,%a7u,10(%a6),%a3
+	mac.w %a1l,%a7u,10(%a6),%d2
+	mac.w %a1l,%a7u,10(%a6),%a7
+	mac.w %a1l,%a7u,10(%a6)&,%d1
+	mac.w %a1l,%a7u,10(%a6)&,%a3
+	mac.w %a1l,%a7u,10(%a6)&,%d2
+	mac.w %a1l,%a7u,10(%a6)&,%a7
+	mac.w %a1l,%a7u,-(%a1),%d1
+	mac.w %a1l,%a7u,-(%a1),%a3
+	mac.w %a1l,%a7u,-(%a1),%d2
+	mac.w %a1l,%a7u,-(%a1),%a7
+	mac.w %a1l,%a7u,-(%a1)&,%d1
+	mac.w %a1l,%a7u,-(%a1)&,%a3
+	mac.w %a1l,%a7u,-(%a1)&,%d2
+	mac.w %a1l,%a7u,-(%a1)&,%a7
+	mac.w %a1l,%a7u,<<,(%a3),%d1
+	mac.w %a1l,%a7u,<<,(%a3),%a3
+	mac.w %a1l,%a7u,<<,(%a3),%d2
+	mac.w %a1l,%a7u,<<,(%a3),%a7
+	mac.w %a1l,%a7u,<<,(%a3)&,%d1
+	mac.w %a1l,%a7u,<<,(%a3)&,%a3
+	mac.w %a1l,%a7u,<<,(%a3)&,%d2
+	mac.w %a1l,%a7u,<<,(%a3)&,%a7
+	mac.w %a1l,%a7u,<<,(%a2)+,%d1
+	mac.w %a1l,%a7u,<<,(%a2)+,%a3
+	mac.w %a1l,%a7u,<<,(%a2)+,%d2
+	mac.w %a1l,%a7u,<<,(%a2)+,%a7
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d1
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a3
+	mac.w %a1l,%a7u,<<,(%a2)+&,%d2
+	mac.w %a1l,%a7u,<<,(%a2)+&,%a7
+	mac.w %a1l,%a7u,<<,10(%a6),%d1
+	mac.w %a1l,%a7u,<<,10(%a6),%a3
+	mac.w %a1l,%a7u,<<,10(%a6),%d2
+	mac.w %a1l,%a7u,<<,10(%a6),%a7
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d1
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a3
+	mac.w %a1l,%a7u,<<,10(%a6)&,%d2
+	mac.w %a1l,%a7u,<<,10(%a6)&,%a7
+	mac.w %a1l,%a7u,<<,-(%a1),%d1
+	mac.w %a1l,%a7u,<<,-(%a1),%a3
+	mac.w %a1l,%a7u,<<,-(%a1),%d2
+	mac.w %a1l,%a7u,<<,-(%a1),%a7
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d1
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a3
+	mac.w %a1l,%a7u,<<,-(%a1)&,%d2
+	mac.w %a1l,%a7u,<<,-(%a1)&,%a7
+	mac.w %a1l,%a7u,>>,(%a3),%d1
+	mac.w %a1l,%a7u,>>,(%a3),%a3
+	mac.w %a1l,%a7u,>>,(%a3),%d2
+	mac.w %a1l,%a7u,>>,(%a3),%a7
+	mac.w %a1l,%a7u,>>,(%a3)&,%d1
+	mac.w %a1l,%a7u,>>,(%a3)&,%a3
+	mac.w %a1l,%a7u,>>,(%a3)&,%d2
+	mac.w %a1l,%a7u,>>,(%a3)&,%a7
+	mac.w %a1l,%a7u,>>,(%a2)+,%d1
+	mac.w %a1l,%a7u,>>,(%a2)+,%a3
+	mac.w %a1l,%a7u,>>,(%a2)+,%d2
+	mac.w %a1l,%a7u,>>,(%a2)+,%a7
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d1
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a3
+	mac.w %a1l,%a7u,>>,(%a2)+&,%d2
+	mac.w %a1l,%a7u,>>,(%a2)+&,%a7
+	mac.w %a1l,%a7u,>>,10(%a6),%d1
+	mac.w %a1l,%a7u,>>,10(%a6),%a3
+	mac.w %a1l,%a7u,>>,10(%a6),%d2
+	mac.w %a1l,%a7u,>>,10(%a6),%a7
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d1
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a3
+	mac.w %a1l,%a7u,>>,10(%a6)&,%d2
+	mac.w %a1l,%a7u,>>,10(%a6)&,%a7
+	mac.w %a1l,%a7u,>>,-(%a1),%d1
+	mac.w %a1l,%a7u,>>,-(%a1),%a3
+	mac.w %a1l,%a7u,>>,-(%a1),%d2
+	mac.w %a1l,%a7u,>>,-(%a1),%a7
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d1
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a3
+	mac.w %a1l,%a7u,>>,-(%a1)&,%d2
+	mac.w %a1l,%a7u,>>,-(%a1)&,%a7
+	mac.w %a1l,%a7u,#1,(%a3),%d1
+	mac.w %a1l,%a7u,#1,(%a3),%a3
+	mac.w %a1l,%a7u,#1,(%a3),%d2
+	mac.w %a1l,%a7u,#1,(%a3),%a7
+	mac.w %a1l,%a7u,#1,(%a3)&,%d1
+	mac.w %a1l,%a7u,#1,(%a3)&,%a3
+	mac.w %a1l,%a7u,#1,(%a3)&,%d2
+	mac.w %a1l,%a7u,#1,(%a3)&,%a7
+	mac.w %a1l,%a7u,#1,(%a2)+,%d1
+	mac.w %a1l,%a7u,#1,(%a2)+,%a3
+	mac.w %a1l,%a7u,#1,(%a2)+,%d2
+	mac.w %a1l,%a7u,#1,(%a2)+,%a7
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d1
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a3
+	mac.w %a1l,%a7u,#1,(%a2)+&,%d2
+	mac.w %a1l,%a7u,#1,(%a2)+&,%a7
+	mac.w %a1l,%a7u,#1,10(%a6),%d1
+	mac.w %a1l,%a7u,#1,10(%a6),%a3
+	mac.w %a1l,%a7u,#1,10(%a6),%d2
+	mac.w %a1l,%a7u,#1,10(%a6),%a7
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d1
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a3
+	mac.w %a1l,%a7u,#1,10(%a6)&,%d2
+	mac.w %a1l,%a7u,#1,10(%a6)&,%a7
+	mac.w %a1l,%a7u,#1,-(%a1),%d1
+	mac.w %a1l,%a7u,#1,-(%a1),%a3
+	mac.w %a1l,%a7u,#1,-(%a1),%d2
+	mac.w %a1l,%a7u,#1,-(%a1),%a7
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d1
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a3
+	mac.w %a1l,%a7u,#1,-(%a1)&,%d2
+	mac.w %a1l,%a7u,#1,-(%a1)&,%a7
+	mac.w %a1l,%a7u,#-1,(%a3),%d1
+	mac.w %a1l,%a7u,#-1,(%a3),%a3
+	mac.w %a1l,%a7u,#-1,(%a3),%d2
+	mac.w %a1l,%a7u,#-1,(%a3),%a7
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d1
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a3
+	mac.w %a1l,%a7u,#-1,(%a3)&,%d2
+	mac.w %a1l,%a7u,#-1,(%a3)&,%a7
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d1
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a3
+	mac.w %a1l,%a7u,#-1,(%a2)+,%d2
+	mac.w %a1l,%a7u,#-1,(%a2)+,%a7
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d1
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a3
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%d2
+	mac.w %a1l,%a7u,#-1,(%a2)+&,%a7
+	mac.w %a1l,%a7u,#-1,10(%a6),%d1
+	mac.w %a1l,%a7u,#-1,10(%a6),%a3
+	mac.w %a1l,%a7u,#-1,10(%a6),%d2
+	mac.w %a1l,%a7u,#-1,10(%a6),%a7
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d1
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a3
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%d2
+	mac.w %a1l,%a7u,#-1,10(%a6)&,%a7
+	mac.w %a1l,%a7u,#-1,-(%a1),%d1
+	mac.w %a1l,%a7u,#-1,-(%a1),%a3
+	mac.w %a1l,%a7u,#-1,-(%a1),%d2
+	mac.w %a1l,%a7u,#-1,-(%a1),%a7
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d1
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a3
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%d2
+	mac.w %a1l,%a7u,#-1,-(%a1)&,%a7
+	mac.w %a1l,%d1l,(%a3),%d1
+	mac.w %a1l,%d1l,(%a3),%a3
+	mac.w %a1l,%d1l,(%a3),%d2
+	mac.w %a1l,%d1l,(%a3),%a7
+	mac.w %a1l,%d1l,(%a3)&,%d1
+	mac.w %a1l,%d1l,(%a3)&,%a3
+	mac.w %a1l,%d1l,(%a3)&,%d2
+	mac.w %a1l,%d1l,(%a3)&,%a7
+	mac.w %a1l,%d1l,(%a2)+,%d1
+	mac.w %a1l,%d1l,(%a2)+,%a3
+	mac.w %a1l,%d1l,(%a2)+,%d2
+	mac.w %a1l,%d1l,(%a2)+,%a7
+	mac.w %a1l,%d1l,(%a2)+&,%d1
+	mac.w %a1l,%d1l,(%a2)+&,%a3
+	mac.w %a1l,%d1l,(%a2)+&,%d2
+	mac.w %a1l,%d1l,(%a2)+&,%a7
+	mac.w %a1l,%d1l,10(%a6),%d1
+	mac.w %a1l,%d1l,10(%a6),%a3
+	mac.w %a1l,%d1l,10(%a6),%d2
+	mac.w %a1l,%d1l,10(%a6),%a7
+	mac.w %a1l,%d1l,10(%a6)&,%d1
+	mac.w %a1l,%d1l,10(%a6)&,%a3
+	mac.w %a1l,%d1l,10(%a6)&,%d2
+	mac.w %a1l,%d1l,10(%a6)&,%a7
+	mac.w %a1l,%d1l,-(%a1),%d1
+	mac.w %a1l,%d1l,-(%a1),%a3
+	mac.w %a1l,%d1l,-(%a1),%d2
+	mac.w %a1l,%d1l,-(%a1),%a7
+	mac.w %a1l,%d1l,-(%a1)&,%d1
+	mac.w %a1l,%d1l,-(%a1)&,%a3
+	mac.w %a1l,%d1l,-(%a1)&,%d2
+	mac.w %a1l,%d1l,-(%a1)&,%a7
+	mac.w %a1l,%d1l,<<,(%a3),%d1
+	mac.w %a1l,%d1l,<<,(%a3),%a3
+	mac.w %a1l,%d1l,<<,(%a3),%d2
+	mac.w %a1l,%d1l,<<,(%a3),%a7
+	mac.w %a1l,%d1l,<<,(%a3)&,%d1
+	mac.w %a1l,%d1l,<<,(%a3)&,%a3
+	mac.w %a1l,%d1l,<<,(%a3)&,%d2
+	mac.w %a1l,%d1l,<<,(%a3)&,%a7
+	mac.w %a1l,%d1l,<<,(%a2)+,%d1
+	mac.w %a1l,%d1l,<<,(%a2)+,%a3
+	mac.w %a1l,%d1l,<<,(%a2)+,%d2
+	mac.w %a1l,%d1l,<<,(%a2)+,%a7
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d1
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a3
+	mac.w %a1l,%d1l,<<,(%a2)+&,%d2
+	mac.w %a1l,%d1l,<<,(%a2)+&,%a7
+	mac.w %a1l,%d1l,<<,10(%a6),%d1
+	mac.w %a1l,%d1l,<<,10(%a6),%a3
+	mac.w %a1l,%d1l,<<,10(%a6),%d2
+	mac.w %a1l,%d1l,<<,10(%a6),%a7
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d1
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a3
+	mac.w %a1l,%d1l,<<,10(%a6)&,%d2
+	mac.w %a1l,%d1l,<<,10(%a6)&,%a7
+	mac.w %a1l,%d1l,<<,-(%a1),%d1
+	mac.w %a1l,%d1l,<<,-(%a1),%a3
+	mac.w %a1l,%d1l,<<,-(%a1),%d2
+	mac.w %a1l,%d1l,<<,-(%a1),%a7
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d1
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a3
+	mac.w %a1l,%d1l,<<,-(%a1)&,%d2
+	mac.w %a1l,%d1l,<<,-(%a1)&,%a7
+	mac.w %a1l,%d1l,>>,(%a3),%d1
+	mac.w %a1l,%d1l,>>,(%a3),%a3
+	mac.w %a1l,%d1l,>>,(%a3),%d2
+	mac.w %a1l,%d1l,>>,(%a3),%a7
+	mac.w %a1l,%d1l,>>,(%a3)&,%d1
+	mac.w %a1l,%d1l,>>,(%a3)&,%a3
+	mac.w %a1l,%d1l,>>,(%a3)&,%d2
+	mac.w %a1l,%d1l,>>,(%a3)&,%a7
+	mac.w %a1l,%d1l,>>,(%a2)+,%d1
+	mac.w %a1l,%d1l,>>,(%a2)+,%a3
+	mac.w %a1l,%d1l,>>,(%a2)+,%d2
+	mac.w %a1l,%d1l,>>,(%a2)+,%a7
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d1
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a3
+	mac.w %a1l,%d1l,>>,(%a2)+&,%d2
+	mac.w %a1l,%d1l,>>,(%a2)+&,%a7
+	mac.w %a1l,%d1l,>>,10(%a6),%d1
+	mac.w %a1l,%d1l,>>,10(%a6),%a3
+	mac.w %a1l,%d1l,>>,10(%a6),%d2
+	mac.w %a1l,%d1l,>>,10(%a6),%a7
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d1
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a3
+	mac.w %a1l,%d1l,>>,10(%a6)&,%d2
+	mac.w %a1l,%d1l,>>,10(%a6)&,%a7
+	mac.w %a1l,%d1l,>>,-(%a1),%d1
+	mac.w %a1l,%d1l,>>,-(%a1),%a3
+	mac.w %a1l,%d1l,>>,-(%a1),%d2
+	mac.w %a1l,%d1l,>>,-(%a1),%a7
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d1
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a3
+	mac.w %a1l,%d1l,>>,-(%a1)&,%d2
+	mac.w %a1l,%d1l,>>,-(%a1)&,%a7
+	mac.w %a1l,%d1l,#1,(%a3),%d1
+	mac.w %a1l,%d1l,#1,(%a3),%a3
+	mac.w %a1l,%d1l,#1,(%a3),%d2
+	mac.w %a1l,%d1l,#1,(%a3),%a7
+	mac.w %a1l,%d1l,#1,(%a3)&,%d1
+	mac.w %a1l,%d1l,#1,(%a3)&,%a3
+	mac.w %a1l,%d1l,#1,(%a3)&,%d2
+	mac.w %a1l,%d1l,#1,(%a3)&,%a7
+	mac.w %a1l,%d1l,#1,(%a2)+,%d1
+	mac.w %a1l,%d1l,#1,(%a2)+,%a3
+	mac.w %a1l,%d1l,#1,(%a2)+,%d2
+	mac.w %a1l,%d1l,#1,(%a2)+,%a7
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d1
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a3
+	mac.w %a1l,%d1l,#1,(%a2)+&,%d2
+	mac.w %a1l,%d1l,#1,(%a2)+&,%a7
+	mac.w %a1l,%d1l,#1,10(%a6),%d1
+	mac.w %a1l,%d1l,#1,10(%a6),%a3
+	mac.w %a1l,%d1l,#1,10(%a6),%d2
+	mac.w %a1l,%d1l,#1,10(%a6),%a7
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d1
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a3
+	mac.w %a1l,%d1l,#1,10(%a6)&,%d2
+	mac.w %a1l,%d1l,#1,10(%a6)&,%a7
+	mac.w %a1l,%d1l,#1,-(%a1),%d1
+	mac.w %a1l,%d1l,#1,-(%a1),%a3
+	mac.w %a1l,%d1l,#1,-(%a1),%d2
+	mac.w %a1l,%d1l,#1,-(%a1),%a7
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d1
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a3
+	mac.w %a1l,%d1l,#1,-(%a1)&,%d2
+	mac.w %a1l,%d1l,#1,-(%a1)&,%a7
+	mac.w %a1l,%d1l,#-1,(%a3),%d1
+	mac.w %a1l,%d1l,#-1,(%a3),%a3
+	mac.w %a1l,%d1l,#-1,(%a3),%d2
+	mac.w %a1l,%d1l,#-1,(%a3),%a7
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d1
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a3
+	mac.w %a1l,%d1l,#-1,(%a3)&,%d2
+	mac.w %a1l,%d1l,#-1,(%a3)&,%a7
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d1
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a3
+	mac.w %a1l,%d1l,#-1,(%a2)+,%d2
+	mac.w %a1l,%d1l,#-1,(%a2)+,%a7
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d1
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a3
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%d2
+	mac.w %a1l,%d1l,#-1,(%a2)+&,%a7
+	mac.w %a1l,%d1l,#-1,10(%a6),%d1
+	mac.w %a1l,%d1l,#-1,10(%a6),%a3
+	mac.w %a1l,%d1l,#-1,10(%a6),%d2
+	mac.w %a1l,%d1l,#-1,10(%a6),%a7
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d1
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a3
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%d2
+	mac.w %a1l,%d1l,#-1,10(%a6)&,%a7
+	mac.w %a1l,%d1l,#-1,-(%a1),%d1
+	mac.w %a1l,%d1l,#-1,-(%a1),%a3
+	mac.w %a1l,%d1l,#-1,-(%a1),%d2
+	mac.w %a1l,%d1l,#-1,-(%a1),%a7
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d1
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a3
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%d2
+	mac.w %a1l,%d1l,#-1,-(%a1)&,%a7
+	mac.w %d2u,%a2u,(%a3),%d1
+	mac.w %d2u,%a2u,(%a3),%a3
+	mac.w %d2u,%a2u,(%a3),%d2
+	mac.w %d2u,%a2u,(%a3),%a7
+	mac.w %d2u,%a2u,(%a3)&,%d1
+	mac.w %d2u,%a2u,(%a3)&,%a3
+	mac.w %d2u,%a2u,(%a3)&,%d2
+	mac.w %d2u,%a2u,(%a3)&,%a7
+	mac.w %d2u,%a2u,(%a2)+,%d1
+	mac.w %d2u,%a2u,(%a2)+,%a3
+	mac.w %d2u,%a2u,(%a2)+,%d2
+	mac.w %d2u,%a2u,(%a2)+,%a7
+	mac.w %d2u,%a2u,(%a2)+&,%d1
+	mac.w %d2u,%a2u,(%a2)+&,%a3
+	mac.w %d2u,%a2u,(%a2)+&,%d2
+	mac.w %d2u,%a2u,(%a2)+&,%a7
+	mac.w %d2u,%a2u,10(%a6),%d1
+	mac.w %d2u,%a2u,10(%a6),%a3
+	mac.w %d2u,%a2u,10(%a6),%d2
+	mac.w %d2u,%a2u,10(%a6),%a7
+	mac.w %d2u,%a2u,10(%a6)&,%d1
+	mac.w %d2u,%a2u,10(%a6)&,%a3
+	mac.w %d2u,%a2u,10(%a6)&,%d2
+	mac.w %d2u,%a2u,10(%a6)&,%a7
+	mac.w %d2u,%a2u,-(%a1),%d1
+	mac.w %d2u,%a2u,-(%a1),%a3
+	mac.w %d2u,%a2u,-(%a1),%d2
+	mac.w %d2u,%a2u,-(%a1),%a7
+	mac.w %d2u,%a2u,-(%a1)&,%d1
+	mac.w %d2u,%a2u,-(%a1)&,%a3
+	mac.w %d2u,%a2u,-(%a1)&,%d2
+	mac.w %d2u,%a2u,-(%a1)&,%a7
+	mac.w %d2u,%a2u,<<,(%a3),%d1
+	mac.w %d2u,%a2u,<<,(%a3),%a3
+	mac.w %d2u,%a2u,<<,(%a3),%d2
+	mac.w %d2u,%a2u,<<,(%a3),%a7
+	mac.w %d2u,%a2u,<<,(%a3)&,%d1
+	mac.w %d2u,%a2u,<<,(%a3)&,%a3
+	mac.w %d2u,%a2u,<<,(%a3)&,%d2
+	mac.w %d2u,%a2u,<<,(%a3)&,%a7
+	mac.w %d2u,%a2u,<<,(%a2)+,%d1
+	mac.w %d2u,%a2u,<<,(%a2)+,%a3
+	mac.w %d2u,%a2u,<<,(%a2)+,%d2
+	mac.w %d2u,%a2u,<<,(%a2)+,%a7
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d1
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a3
+	mac.w %d2u,%a2u,<<,(%a2)+&,%d2
+	mac.w %d2u,%a2u,<<,(%a2)+&,%a7
+	mac.w %d2u,%a2u,<<,10(%a6),%d1
+	mac.w %d2u,%a2u,<<,10(%a6),%a3
+	mac.w %d2u,%a2u,<<,10(%a6),%d2
+	mac.w %d2u,%a2u,<<,10(%a6),%a7
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d1
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a3
+	mac.w %d2u,%a2u,<<,10(%a6)&,%d2
+	mac.w %d2u,%a2u,<<,10(%a6)&,%a7
+	mac.w %d2u,%a2u,<<,-(%a1),%d1
+	mac.w %d2u,%a2u,<<,-(%a1),%a3
+	mac.w %d2u,%a2u,<<,-(%a1),%d2
+	mac.w %d2u,%a2u,<<,-(%a1),%a7
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d1
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a3
+	mac.w %d2u,%a2u,<<,-(%a1)&,%d2
+	mac.w %d2u,%a2u,<<,-(%a1)&,%a7
+	mac.w %d2u,%a2u,>>,(%a3),%d1
+	mac.w %d2u,%a2u,>>,(%a3),%a3
+	mac.w %d2u,%a2u,>>,(%a3),%d2
+	mac.w %d2u,%a2u,>>,(%a3),%a7
+	mac.w %d2u,%a2u,>>,(%a3)&,%d1
+	mac.w %d2u,%a2u,>>,(%a3)&,%a3
+	mac.w %d2u,%a2u,>>,(%a3)&,%d2
+	mac.w %d2u,%a2u,>>,(%a3)&,%a7
+	mac.w %d2u,%a2u,>>,(%a2)+,%d1
+	mac.w %d2u,%a2u,>>,(%a2)+,%a3
+	mac.w %d2u,%a2u,>>,(%a2)+,%d2
+	mac.w %d2u,%a2u,>>,(%a2)+,%a7
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d1
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a3
+	mac.w %d2u,%a2u,>>,(%a2)+&,%d2
+	mac.w %d2u,%a2u,>>,(%a2)+&,%a7
+	mac.w %d2u,%a2u,>>,10(%a6),%d1
+	mac.w %d2u,%a2u,>>,10(%a6),%a3
+	mac.w %d2u,%a2u,>>,10(%a6),%d2
+	mac.w %d2u,%a2u,>>,10(%a6),%a7
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d1
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a3
+	mac.w %d2u,%a2u,>>,10(%a6)&,%d2
+	mac.w %d2u,%a2u,>>,10(%a6)&,%a7
+	mac.w %d2u,%a2u,>>,-(%a1),%d1
+	mac.w %d2u,%a2u,>>,-(%a1),%a3
+	mac.w %d2u,%a2u,>>,-(%a1),%d2
+	mac.w %d2u,%a2u,>>,-(%a1),%a7
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d1
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a3
+	mac.w %d2u,%a2u,>>,-(%a1)&,%d2
+	mac.w %d2u,%a2u,>>,-(%a1)&,%a7
+	mac.w %d2u,%a2u,#1,(%a3),%d1
+	mac.w %d2u,%a2u,#1,(%a3),%a3
+	mac.w %d2u,%a2u,#1,(%a3),%d2
+	mac.w %d2u,%a2u,#1,(%a3),%a7
+	mac.w %d2u,%a2u,#1,(%a3)&,%d1
+	mac.w %d2u,%a2u,#1,(%a3)&,%a3
+	mac.w %d2u,%a2u,#1,(%a3)&,%d2
+	mac.w %d2u,%a2u,#1,(%a3)&,%a7
+	mac.w %d2u,%a2u,#1,(%a2)+,%d1
+	mac.w %d2u,%a2u,#1,(%a2)+,%a3
+	mac.w %d2u,%a2u,#1,(%a2)+,%d2
+	mac.w %d2u,%a2u,#1,(%a2)+,%a7
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d1
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a3
+	mac.w %d2u,%a2u,#1,(%a2)+&,%d2
+	mac.w %d2u,%a2u,#1,(%a2)+&,%a7
+	mac.w %d2u,%a2u,#1,10(%a6),%d1
+	mac.w %d2u,%a2u,#1,10(%a6),%a3
+	mac.w %d2u,%a2u,#1,10(%a6),%d2
+	mac.w %d2u,%a2u,#1,10(%a6),%a7
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d1
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a3
+	mac.w %d2u,%a2u,#1,10(%a6)&,%d2
+	mac.w %d2u,%a2u,#1,10(%a6)&,%a7
+	mac.w %d2u,%a2u,#1,-(%a1),%d1
+	mac.w %d2u,%a2u,#1,-(%a1),%a3
+	mac.w %d2u,%a2u,#1,-(%a1),%d2
+	mac.w %d2u,%a2u,#1,-(%a1),%a7
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d1
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a3
+	mac.w %d2u,%a2u,#1,-(%a1)&,%d2
+	mac.w %d2u,%a2u,#1,-(%a1)&,%a7
+	mac.w %d2u,%a2u,#-1,(%a3),%d1
+	mac.w %d2u,%a2u,#-1,(%a3),%a3
+	mac.w %d2u,%a2u,#-1,(%a3),%d2
+	mac.w %d2u,%a2u,#-1,(%a3),%a7
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d1
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a3
+	mac.w %d2u,%a2u,#-1,(%a3)&,%d2
+	mac.w %d2u,%a2u,#-1,(%a3)&,%a7
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d1
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a3
+	mac.w %d2u,%a2u,#-1,(%a2)+,%d2
+	mac.w %d2u,%a2u,#-1,(%a2)+,%a7
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d1
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a3
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%d2
+	mac.w %d2u,%a2u,#-1,(%a2)+&,%a7
+	mac.w %d2u,%a2u,#-1,10(%a6),%d1
+	mac.w %d2u,%a2u,#-1,10(%a6),%a3
+	mac.w %d2u,%a2u,#-1,10(%a6),%d2
+	mac.w %d2u,%a2u,#-1,10(%a6),%a7
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d1
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a3
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%d2
+	mac.w %d2u,%a2u,#-1,10(%a6)&,%a7
+	mac.w %d2u,%a2u,#-1,-(%a1),%d1
+	mac.w %d2u,%a2u,#-1,-(%a1),%a3
+	mac.w %d2u,%a2u,#-1,-(%a1),%d2
+	mac.w %d2u,%a2u,#-1,-(%a1),%a7
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d1
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a3
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%d2
+	mac.w %d2u,%a2u,#-1,-(%a1)&,%a7
+	mac.w %d2u,%d3l,(%a3),%d1
+	mac.w %d2u,%d3l,(%a3),%a3
+	mac.w %d2u,%d3l,(%a3),%d2
+	mac.w %d2u,%d3l,(%a3),%a7
+	mac.w %d2u,%d3l,(%a3)&,%d1
+	mac.w %d2u,%d3l,(%a3)&,%a3
+	mac.w %d2u,%d3l,(%a3)&,%d2
+	mac.w %d2u,%d3l,(%a3)&,%a7
+	mac.w %d2u,%d3l,(%a2)+,%d1
+	mac.w %d2u,%d3l,(%a2)+,%a3
+	mac.w %d2u,%d3l,(%a2)+,%d2
+	mac.w %d2u,%d3l,(%a2)+,%a7
+	mac.w %d2u,%d3l,(%a2)+&,%d1
+	mac.w %d2u,%d3l,(%a2)+&,%a3
+	mac.w %d2u,%d3l,(%a2)+&,%d2
+	mac.w %d2u,%d3l,(%a2)+&,%a7
+	mac.w %d2u,%d3l,10(%a6),%d1
+	mac.w %d2u,%d3l,10(%a6),%a3
+	mac.w %d2u,%d3l,10(%a6),%d2
+	mac.w %d2u,%d3l,10(%a6),%a7
+	mac.w %d2u,%d3l,10(%a6)&,%d1
+	mac.w %d2u,%d3l,10(%a6)&,%a3
+	mac.w %d2u,%d3l,10(%a6)&,%d2
+	mac.w %d2u,%d3l,10(%a6)&,%a7
+	mac.w %d2u,%d3l,-(%a1),%d1
+	mac.w %d2u,%d3l,-(%a1),%a3
+	mac.w %d2u,%d3l,-(%a1),%d2
+	mac.w %d2u,%d3l,-(%a1),%a7
+	mac.w %d2u,%d3l,-(%a1)&,%d1
+	mac.w %d2u,%d3l,-(%a1)&,%a3
+	mac.w %d2u,%d3l,-(%a1)&,%d2
+	mac.w %d2u,%d3l,-(%a1)&,%a7
+	mac.w %d2u,%d3l,<<,(%a3),%d1
+	mac.w %d2u,%d3l,<<,(%a3),%a3
+	mac.w %d2u,%d3l,<<,(%a3),%d2
+	mac.w %d2u,%d3l,<<,(%a3),%a7
+	mac.w %d2u,%d3l,<<,(%a3)&,%d1
+	mac.w %d2u,%d3l,<<,(%a3)&,%a3
+	mac.w %d2u,%d3l,<<,(%a3)&,%d2
+	mac.w %d2u,%d3l,<<,(%a3)&,%a7
+	mac.w %d2u,%d3l,<<,(%a2)+,%d1
+	mac.w %d2u,%d3l,<<,(%a2)+,%a3
+	mac.w %d2u,%d3l,<<,(%a2)+,%d2
+	mac.w %d2u,%d3l,<<,(%a2)+,%a7
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d1
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a3
+	mac.w %d2u,%d3l,<<,(%a2)+&,%d2
+	mac.w %d2u,%d3l,<<,(%a2)+&,%a7
+	mac.w %d2u,%d3l,<<,10(%a6),%d1
+	mac.w %d2u,%d3l,<<,10(%a6),%a3
+	mac.w %d2u,%d3l,<<,10(%a6),%d2
+	mac.w %d2u,%d3l,<<,10(%a6),%a7
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d1
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a3
+	mac.w %d2u,%d3l,<<,10(%a6)&,%d2
+	mac.w %d2u,%d3l,<<,10(%a6)&,%a7
+	mac.w %d2u,%d3l,<<,-(%a1),%d1
+	mac.w %d2u,%d3l,<<,-(%a1),%a3
+	mac.w %d2u,%d3l,<<,-(%a1),%d2
+	mac.w %d2u,%d3l,<<,-(%a1),%a7
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d1
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a3
+	mac.w %d2u,%d3l,<<,-(%a1)&,%d2
+	mac.w %d2u,%d3l,<<,-(%a1)&,%a7
+	mac.w %d2u,%d3l,>>,(%a3),%d1
+	mac.w %d2u,%d3l,>>,(%a3),%a3
+	mac.w %d2u,%d3l,>>,(%a3),%d2
+	mac.w %d2u,%d3l,>>,(%a3),%a7
+	mac.w %d2u,%d3l,>>,(%a3)&,%d1
+	mac.w %d2u,%d3l,>>,(%a3)&,%a3
+	mac.w %d2u,%d3l,>>,(%a3)&,%d2
+	mac.w %d2u,%d3l,>>,(%a3)&,%a7
+	mac.w %d2u,%d3l,>>,(%a2)+,%d1
+	mac.w %d2u,%d3l,>>,(%a2)+,%a3
+	mac.w %d2u,%d3l,>>,(%a2)+,%d2
+	mac.w %d2u,%d3l,>>,(%a2)+,%a7
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d1
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a3
+	mac.w %d2u,%d3l,>>,(%a2)+&,%d2
+	mac.w %d2u,%d3l,>>,(%a2)+&,%a7
+	mac.w %d2u,%d3l,>>,10(%a6),%d1
+	mac.w %d2u,%d3l,>>,10(%a6),%a3
+	mac.w %d2u,%d3l,>>,10(%a6),%d2
+	mac.w %d2u,%d3l,>>,10(%a6),%a7
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d1
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a3
+	mac.w %d2u,%d3l,>>,10(%a6)&,%d2
+	mac.w %d2u,%d3l,>>,10(%a6)&,%a7
+	mac.w %d2u,%d3l,>>,-(%a1),%d1
+	mac.w %d2u,%d3l,>>,-(%a1),%a3
+	mac.w %d2u,%d3l,>>,-(%a1),%d2
+	mac.w %d2u,%d3l,>>,-(%a1),%a7
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d1
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a3
+	mac.w %d2u,%d3l,>>,-(%a1)&,%d2
+	mac.w %d2u,%d3l,>>,-(%a1)&,%a7
+	mac.w %d2u,%d3l,#1,(%a3),%d1
+	mac.w %d2u,%d3l,#1,(%a3),%a3
+	mac.w %d2u,%d3l,#1,(%a3),%d2
+	mac.w %d2u,%d3l,#1,(%a3),%a7
+	mac.w %d2u,%d3l,#1,(%a3)&,%d1
+	mac.w %d2u,%d3l,#1,(%a3)&,%a3
+	mac.w %d2u,%d3l,#1,(%a3)&,%d2
+	mac.w %d2u,%d3l,#1,(%a3)&,%a7
+	mac.w %d2u,%d3l,#1,(%a2)+,%d1
+	mac.w %d2u,%d3l,#1,(%a2)+,%a3
+	mac.w %d2u,%d3l,#1,(%a2)+,%d2
+	mac.w %d2u,%d3l,#1,(%a2)+,%a7
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d1
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a3
+	mac.w %d2u,%d3l,#1,(%a2)+&,%d2
+	mac.w %d2u,%d3l,#1,(%a2)+&,%a7
+	mac.w %d2u,%d3l,#1,10(%a6),%d1
+	mac.w %d2u,%d3l,#1,10(%a6),%a3
+	mac.w %d2u,%d3l,#1,10(%a6),%d2
+	mac.w %d2u,%d3l,#1,10(%a6),%a7
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d1
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a3
+	mac.w %d2u,%d3l,#1,10(%a6)&,%d2
+	mac.w %d2u,%d3l,#1,10(%a6)&,%a7
+	mac.w %d2u,%d3l,#1,-(%a1),%d1
+	mac.w %d2u,%d3l,#1,-(%a1),%a3
+	mac.w %d2u,%d3l,#1,-(%a1),%d2
+	mac.w %d2u,%d3l,#1,-(%a1),%a7
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d1
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a3
+	mac.w %d2u,%d3l,#1,-(%a1)&,%d2
+	mac.w %d2u,%d3l,#1,-(%a1)&,%a7
+	mac.w %d2u,%d3l,#-1,(%a3),%d1
+	mac.w %d2u,%d3l,#-1,(%a3),%a3
+	mac.w %d2u,%d3l,#-1,(%a3),%d2
+	mac.w %d2u,%d3l,#-1,(%a3),%a7
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d1
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a3
+	mac.w %d2u,%d3l,#-1,(%a3)&,%d2
+	mac.w %d2u,%d3l,#-1,(%a3)&,%a7
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d1
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a3
+	mac.w %d2u,%d3l,#-1,(%a2)+,%d2
+	mac.w %d2u,%d3l,#-1,(%a2)+,%a7
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d1
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a3
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%d2
+	mac.w %d2u,%d3l,#-1,(%a2)+&,%a7
+	mac.w %d2u,%d3l,#-1,10(%a6),%d1
+	mac.w %d2u,%d3l,#-1,10(%a6),%a3
+	mac.w %d2u,%d3l,#-1,10(%a6),%d2
+	mac.w %d2u,%d3l,#-1,10(%a6),%a7
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d1
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a3
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%d2
+	mac.w %d2u,%d3l,#-1,10(%a6)&,%a7
+	mac.w %d2u,%d3l,#-1,-(%a1),%d1
+	mac.w %d2u,%d3l,#-1,-(%a1),%a3
+	mac.w %d2u,%d3l,#-1,-(%a1),%d2
+	mac.w %d2u,%d3l,#-1,-(%a1),%a7
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d1
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a3
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%d2
+	mac.w %d2u,%d3l,#-1,-(%a1)&,%a7
+	mac.w %d2u,%a7u,(%a3),%d1
+	mac.w %d2u,%a7u,(%a3),%a3
+	mac.w %d2u,%a7u,(%a3),%d2
+	mac.w %d2u,%a7u,(%a3),%a7
+	mac.w %d2u,%a7u,(%a3)&,%d1
+	mac.w %d2u,%a7u,(%a3)&,%a3
+	mac.w %d2u,%a7u,(%a3)&,%d2
+	mac.w %d2u,%a7u,(%a3)&,%a7
+	mac.w %d2u,%a7u,(%a2)+,%d1
+	mac.w %d2u,%a7u,(%a2)+,%a3
+	mac.w %d2u,%a7u,(%a2)+,%d2
+	mac.w %d2u,%a7u,(%a2)+,%a7
+	mac.w %d2u,%a7u,(%a2)+&,%d1
+	mac.w %d2u,%a7u,(%a2)+&,%a3
+	mac.w %d2u,%a7u,(%a2)+&,%d2
+	mac.w %d2u,%a7u,(%a2)+&,%a7
+	mac.w %d2u,%a7u,10(%a6),%d1
+	mac.w %d2u,%a7u,10(%a6),%a3
+	mac.w %d2u,%a7u,10(%a6),%d2
+	mac.w %d2u,%a7u,10(%a6),%a7
+	mac.w %d2u,%a7u,10(%a6)&,%d1
+	mac.w %d2u,%a7u,10(%a6)&,%a3
+	mac.w %d2u,%a7u,10(%a6)&,%d2
+	mac.w %d2u,%a7u,10(%a6)&,%a7
+	mac.w %d2u,%a7u,-(%a1),%d1
+	mac.w %d2u,%a7u,-(%a1),%a3
+	mac.w %d2u,%a7u,-(%a1),%d2
+	mac.w %d2u,%a7u,-(%a1),%a7
+	mac.w %d2u,%a7u,-(%a1)&,%d1
+	mac.w %d2u,%a7u,-(%a1)&,%a3
+	mac.w %d2u,%a7u,-(%a1)&,%d2
+	mac.w %d2u,%a7u,-(%a1)&,%a7
+	mac.w %d2u,%a7u,<<,(%a3),%d1
+	mac.w %d2u,%a7u,<<,(%a3),%a3
+	mac.w %d2u,%a7u,<<,(%a3),%d2
+	mac.w %d2u,%a7u,<<,(%a3),%a7
+	mac.w %d2u,%a7u,<<,(%a3)&,%d1
+	mac.w %d2u,%a7u,<<,(%a3)&,%a3
+	mac.w %d2u,%a7u,<<,(%a3)&,%d2
+	mac.w %d2u,%a7u,<<,(%a3)&,%a7
+	mac.w %d2u,%a7u,<<,(%a2)+,%d1
+	mac.w %d2u,%a7u,<<,(%a2)+,%a3
+	mac.w %d2u,%a7u,<<,(%a2)+,%d2
+	mac.w %d2u,%a7u,<<,(%a2)+,%a7
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d1
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a3
+	mac.w %d2u,%a7u,<<,(%a2)+&,%d2
+	mac.w %d2u,%a7u,<<,(%a2)+&,%a7
+	mac.w %d2u,%a7u,<<,10(%a6),%d1
+	mac.w %d2u,%a7u,<<,10(%a6),%a3
+	mac.w %d2u,%a7u,<<,10(%a6),%d2
+	mac.w %d2u,%a7u,<<,10(%a6),%a7
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d1
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a3
+	mac.w %d2u,%a7u,<<,10(%a6)&,%d2
+	mac.w %d2u,%a7u,<<,10(%a6)&,%a7
+	mac.w %d2u,%a7u,<<,-(%a1),%d1
+	mac.w %d2u,%a7u,<<,-(%a1),%a3
+	mac.w %d2u,%a7u,<<,-(%a1),%d2
+	mac.w %d2u,%a7u,<<,-(%a1),%a7
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d1
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a3
+	mac.w %d2u,%a7u,<<,-(%a1)&,%d2
+	mac.w %d2u,%a7u,<<,-(%a1)&,%a7
+	mac.w %d2u,%a7u,>>,(%a3),%d1
+	mac.w %d2u,%a7u,>>,(%a3),%a3
+	mac.w %d2u,%a7u,>>,(%a3),%d2
+	mac.w %d2u,%a7u,>>,(%a3),%a7
+	mac.w %d2u,%a7u,>>,(%a3)&,%d1
+	mac.w %d2u,%a7u,>>,(%a3)&,%a3
+	mac.w %d2u,%a7u,>>,(%a3)&,%d2
+	mac.w %d2u,%a7u,>>,(%a3)&,%a7
+	mac.w %d2u,%a7u,>>,(%a2)+,%d1
+	mac.w %d2u,%a7u,>>,(%a2)+,%a3
+	mac.w %d2u,%a7u,>>,(%a2)+,%d2
+	mac.w %d2u,%a7u,>>,(%a2)+,%a7
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d1
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a3
+	mac.w %d2u,%a7u,>>,(%a2)+&,%d2
+	mac.w %d2u,%a7u,>>,(%a2)+&,%a7
+	mac.w %d2u,%a7u,>>,10(%a6),%d1
+	mac.w %d2u,%a7u,>>,10(%a6),%a3
+	mac.w %d2u,%a7u,>>,10(%a6),%d2
+	mac.w %d2u,%a7u,>>,10(%a6),%a7
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d1
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a3
+	mac.w %d2u,%a7u,>>,10(%a6)&,%d2
+	mac.w %d2u,%a7u,>>,10(%a6)&,%a7
+	mac.w %d2u,%a7u,>>,-(%a1),%d1
+	mac.w %d2u,%a7u,>>,-(%a1),%a3
+	mac.w %d2u,%a7u,>>,-(%a1),%d2
+	mac.w %d2u,%a7u,>>,-(%a1),%a7
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d1
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a3
+	mac.w %d2u,%a7u,>>,-(%a1)&,%d2
+	mac.w %d2u,%a7u,>>,-(%a1)&,%a7
+	mac.w %d2u,%a7u,#1,(%a3),%d1
+	mac.w %d2u,%a7u,#1,(%a3),%a3
+	mac.w %d2u,%a7u,#1,(%a3),%d2
+	mac.w %d2u,%a7u,#1,(%a3),%a7
+	mac.w %d2u,%a7u,#1,(%a3)&,%d1
+	mac.w %d2u,%a7u,#1,(%a3)&,%a3
+	mac.w %d2u,%a7u,#1,(%a3)&,%d2
+	mac.w %d2u,%a7u,#1,(%a3)&,%a7
+	mac.w %d2u,%a7u,#1,(%a2)+,%d1
+	mac.w %d2u,%a7u,#1,(%a2)+,%a3
+	mac.w %d2u,%a7u,#1,(%a2)+,%d2
+	mac.w %d2u,%a7u,#1,(%a2)+,%a7
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d1
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a3
+	mac.w %d2u,%a7u,#1,(%a2)+&,%d2
+	mac.w %d2u,%a7u,#1,(%a2)+&,%a7
+	mac.w %d2u,%a7u,#1,10(%a6),%d1
+	mac.w %d2u,%a7u,#1,10(%a6),%a3
+	mac.w %d2u,%a7u,#1,10(%a6),%d2
+	mac.w %d2u,%a7u,#1,10(%a6),%a7
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d1
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a3
+	mac.w %d2u,%a7u,#1,10(%a6)&,%d2
+	mac.w %d2u,%a7u,#1,10(%a6)&,%a7
+	mac.w %d2u,%a7u,#1,-(%a1),%d1
+	mac.w %d2u,%a7u,#1,-(%a1),%a3
+	mac.w %d2u,%a7u,#1,-(%a1),%d2
+	mac.w %d2u,%a7u,#1,-(%a1),%a7
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d1
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a3
+	mac.w %d2u,%a7u,#1,-(%a1)&,%d2
+	mac.w %d2u,%a7u,#1,-(%a1)&,%a7
+	mac.w %d2u,%a7u,#-1,(%a3),%d1
+	mac.w %d2u,%a7u,#-1,(%a3),%a3
+	mac.w %d2u,%a7u,#-1,(%a3),%d2
+	mac.w %d2u,%a7u,#-1,(%a3),%a7
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d1
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a3
+	mac.w %d2u,%a7u,#-1,(%a3)&,%d2
+	mac.w %d2u,%a7u,#-1,(%a3)&,%a7
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d1
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a3
+	mac.w %d2u,%a7u,#-1,(%a2)+,%d2
+	mac.w %d2u,%a7u,#-1,(%a2)+,%a7
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d1
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a3
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%d2
+	mac.w %d2u,%a7u,#-1,(%a2)+&,%a7
+	mac.w %d2u,%a7u,#-1,10(%a6),%d1
+	mac.w %d2u,%a7u,#-1,10(%a6),%a3
+	mac.w %d2u,%a7u,#-1,10(%a6),%d2
+	mac.w %d2u,%a7u,#-1,10(%a6),%a7
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d1
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a3
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%d2
+	mac.w %d2u,%a7u,#-1,10(%a6)&,%a7
+	mac.w %d2u,%a7u,#-1,-(%a1),%d1
+	mac.w %d2u,%a7u,#-1,-(%a1),%a3
+	mac.w %d2u,%a7u,#-1,-(%a1),%d2
+	mac.w %d2u,%a7u,#-1,-(%a1),%a7
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d1
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a3
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%d2
+	mac.w %d2u,%a7u,#-1,-(%a1)&,%a7
+	mac.w %d2u,%d1l,(%a3),%d1
+	mac.w %d2u,%d1l,(%a3),%a3
+	mac.w %d2u,%d1l,(%a3),%d2
+	mac.w %d2u,%d1l,(%a3),%a7
+	mac.w %d2u,%d1l,(%a3)&,%d1
+	mac.w %d2u,%d1l,(%a3)&,%a3
+	mac.w %d2u,%d1l,(%a3)&,%d2
+	mac.w %d2u,%d1l,(%a3)&,%a7
+	mac.w %d2u,%d1l,(%a2)+,%d1
+	mac.w %d2u,%d1l,(%a2)+,%a3
+	mac.w %d2u,%d1l,(%a2)+,%d2
+	mac.w %d2u,%d1l,(%a2)+,%a7
+	mac.w %d2u,%d1l,(%a2)+&,%d1
+	mac.w %d2u,%d1l,(%a2)+&,%a3
+	mac.w %d2u,%d1l,(%a2)+&,%d2
+	mac.w %d2u,%d1l,(%a2)+&,%a7
+	mac.w %d2u,%d1l,10(%a6),%d1
+	mac.w %d2u,%d1l,10(%a6),%a3
+	mac.w %d2u,%d1l,10(%a6),%d2
+	mac.w %d2u,%d1l,10(%a6),%a7
+	mac.w %d2u,%d1l,10(%a6)&,%d1
+	mac.w %d2u,%d1l,10(%a6)&,%a3
+	mac.w %d2u,%d1l,10(%a6)&,%d2
+	mac.w %d2u,%d1l,10(%a6)&,%a7
+	mac.w %d2u,%d1l,-(%a1),%d1
+	mac.w %d2u,%d1l,-(%a1),%a3
+	mac.w %d2u,%d1l,-(%a1),%d2
+	mac.w %d2u,%d1l,-(%a1),%a7
+	mac.w %d2u,%d1l,-(%a1)&,%d1
+	mac.w %d2u,%d1l,-(%a1)&,%a3
+	mac.w %d2u,%d1l,-(%a1)&,%d2
+	mac.w %d2u,%d1l,-(%a1)&,%a7
+	mac.w %d2u,%d1l,<<,(%a3),%d1
+	mac.w %d2u,%d1l,<<,(%a3),%a3
+	mac.w %d2u,%d1l,<<,(%a3),%d2
+	mac.w %d2u,%d1l,<<,(%a3),%a7
+	mac.w %d2u,%d1l,<<,(%a3)&,%d1
+	mac.w %d2u,%d1l,<<,(%a3)&,%a3
+	mac.w %d2u,%d1l,<<,(%a3)&,%d2
+	mac.w %d2u,%d1l,<<,(%a3)&,%a7
+	mac.w %d2u,%d1l,<<,(%a2)+,%d1
+	mac.w %d2u,%d1l,<<,(%a2)+,%a3
+	mac.w %d2u,%d1l,<<,(%a2)+,%d2
+	mac.w %d2u,%d1l,<<,(%a2)+,%a7
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d1
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a3
+	mac.w %d2u,%d1l,<<,(%a2)+&,%d2
+	mac.w %d2u,%d1l,<<,(%a2)+&,%a7
+	mac.w %d2u,%d1l,<<,10(%a6),%d1
+	mac.w %d2u,%d1l,<<,10(%a6),%a3
+	mac.w %d2u,%d1l,<<,10(%a6),%d2
+	mac.w %d2u,%d1l,<<,10(%a6),%a7
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d1
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a3
+	mac.w %d2u,%d1l,<<,10(%a6)&,%d2
+	mac.w %d2u,%d1l,<<,10(%a6)&,%a7
+	mac.w %d2u,%d1l,<<,-(%a1),%d1
+	mac.w %d2u,%d1l,<<,-(%a1),%a3
+	mac.w %d2u,%d1l,<<,-(%a1),%d2
+	mac.w %d2u,%d1l,<<,-(%a1),%a7
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d1
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a3
+	mac.w %d2u,%d1l,<<,-(%a1)&,%d2
+	mac.w %d2u,%d1l,<<,-(%a1)&,%a7
+	mac.w %d2u,%d1l,>>,(%a3),%d1
+	mac.w %d2u,%d1l,>>,(%a3),%a3
+	mac.w %d2u,%d1l,>>,(%a3),%d2
+	mac.w %d2u,%d1l,>>,(%a3),%a7
+	mac.w %d2u,%d1l,>>,(%a3)&,%d1
+	mac.w %d2u,%d1l,>>,(%a3)&,%a3
+	mac.w %d2u,%d1l,>>,(%a3)&,%d2
+	mac.w %d2u,%d1l,>>,(%a3)&,%a7
+	mac.w %d2u,%d1l,>>,(%a2)+,%d1
+	mac.w %d2u,%d1l,>>,(%a2)+,%a3
+	mac.w %d2u,%d1l,>>,(%a2)+,%d2
+	mac.w %d2u,%d1l,>>,(%a2)+,%a7
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d1
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a3
+	mac.w %d2u,%d1l,>>,(%a2)+&,%d2
+	mac.w %d2u,%d1l,>>,(%a2)+&,%a7
+	mac.w %d2u,%d1l,>>,10(%a6),%d1
+	mac.w %d2u,%d1l,>>,10(%a6),%a3
+	mac.w %d2u,%d1l,>>,10(%a6),%d2
+	mac.w %d2u,%d1l,>>,10(%a6),%a7
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d1
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a3
+	mac.w %d2u,%d1l,>>,10(%a6)&,%d2
+	mac.w %d2u,%d1l,>>,10(%a6)&,%a7
+	mac.w %d2u,%d1l,>>,-(%a1),%d1
+	mac.w %d2u,%d1l,>>,-(%a1),%a3
+	mac.w %d2u,%d1l,>>,-(%a1),%d2
+	mac.w %d2u,%d1l,>>,-(%a1),%a7
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d1
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a3
+	mac.w %d2u,%d1l,>>,-(%a1)&,%d2
+	mac.w %d2u,%d1l,>>,-(%a1)&,%a7
+	mac.w %d2u,%d1l,#1,(%a3),%d1
+	mac.w %d2u,%d1l,#1,(%a3),%a3
+	mac.w %d2u,%d1l,#1,(%a3),%d2
+	mac.w %d2u,%d1l,#1,(%a3),%a7
+	mac.w %d2u,%d1l,#1,(%a3)&,%d1
+	mac.w %d2u,%d1l,#1,(%a3)&,%a3
+	mac.w %d2u,%d1l,#1,(%a3)&,%d2
+	mac.w %d2u,%d1l,#1,(%a3)&,%a7
+	mac.w %d2u,%d1l,#1,(%a2)+,%d1
+	mac.w %d2u,%d1l,#1,(%a2)+,%a3
+	mac.w %d2u,%d1l,#1,(%a2)+,%d2
+	mac.w %d2u,%d1l,#1,(%a2)+,%a7
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d1
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a3
+	mac.w %d2u,%d1l,#1,(%a2)+&,%d2
+	mac.w %d2u,%d1l,#1,(%a2)+&,%a7
+	mac.w %d2u,%d1l,#1,10(%a6),%d1
+	mac.w %d2u,%d1l,#1,10(%a6),%a3
+	mac.w %d2u,%d1l,#1,10(%a6),%d2
+	mac.w %d2u,%d1l,#1,10(%a6),%a7
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d1
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a3
+	mac.w %d2u,%d1l,#1,10(%a6)&,%d2
+	mac.w %d2u,%d1l,#1,10(%a6)&,%a7
+	mac.w %d2u,%d1l,#1,-(%a1),%d1
+	mac.w %d2u,%d1l,#1,-(%a1),%a3
+	mac.w %d2u,%d1l,#1,-(%a1),%d2
+	mac.w %d2u,%d1l,#1,-(%a1),%a7
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d1
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a3
+	mac.w %d2u,%d1l,#1,-(%a1)&,%d2
+	mac.w %d2u,%d1l,#1,-(%a1)&,%a7
+	mac.w %d2u,%d1l,#-1,(%a3),%d1
+	mac.w %d2u,%d1l,#-1,(%a3),%a3
+	mac.w %d2u,%d1l,#-1,(%a3),%d2
+	mac.w %d2u,%d1l,#-1,(%a3),%a7
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d1
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a3
+	mac.w %d2u,%d1l,#-1,(%a3)&,%d2
+	mac.w %d2u,%d1l,#-1,(%a3)&,%a7
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d1
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a3
+	mac.w %d2u,%d1l,#-1,(%a2)+,%d2
+	mac.w %d2u,%d1l,#-1,(%a2)+,%a7
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d1
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a3
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%d2
+	mac.w %d2u,%d1l,#-1,(%a2)+&,%a7
+	mac.w %d2u,%d1l,#-1,10(%a6),%d1
+	mac.w %d2u,%d1l,#-1,10(%a6),%a3
+	mac.w %d2u,%d1l,#-1,10(%a6),%d2
+	mac.w %d2u,%d1l,#-1,10(%a6),%a7
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d1
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a3
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%d2
+	mac.w %d2u,%d1l,#-1,10(%a6)&,%a7
+	mac.w %d2u,%d1l,#-1,-(%a1),%d1
+	mac.w %d2u,%d1l,#-1,-(%a1),%a3
+	mac.w %d2u,%d1l,#-1,-(%a1),%d2
+	mac.w %d2u,%d1l,#-1,-(%a1),%a7
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d1
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a3
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%d2
+	mac.w %d2u,%d1l,#-1,-(%a1)&,%a7
+	mac.w %a5l,%a2u,(%a3),%d1
+	mac.w %a5l,%a2u,(%a3),%a3
+	mac.w %a5l,%a2u,(%a3),%d2
+	mac.w %a5l,%a2u,(%a3),%a7
+	mac.w %a5l,%a2u,(%a3)&,%d1
+	mac.w %a5l,%a2u,(%a3)&,%a3
+	mac.w %a5l,%a2u,(%a3)&,%d2
+	mac.w %a5l,%a2u,(%a3)&,%a7
+	mac.w %a5l,%a2u,(%a2)+,%d1
+	mac.w %a5l,%a2u,(%a2)+,%a3
+	mac.w %a5l,%a2u,(%a2)+,%d2
+	mac.w %a5l,%a2u,(%a2)+,%a7
+	mac.w %a5l,%a2u,(%a2)+&,%d1
+	mac.w %a5l,%a2u,(%a2)+&,%a3
+	mac.w %a5l,%a2u,(%a2)+&,%d2
+	mac.w %a5l,%a2u,(%a2)+&,%a7
+	mac.w %a5l,%a2u,10(%a6),%d1
+	mac.w %a5l,%a2u,10(%a6),%a3
+	mac.w %a5l,%a2u,10(%a6),%d2
+	mac.w %a5l,%a2u,10(%a6),%a7
+	mac.w %a5l,%a2u,10(%a6)&,%d1
+	mac.w %a5l,%a2u,10(%a6)&,%a3
+	mac.w %a5l,%a2u,10(%a6)&,%d2
+	mac.w %a5l,%a2u,10(%a6)&,%a7
+	mac.w %a5l,%a2u,-(%a1),%d1
+	mac.w %a5l,%a2u,-(%a1),%a3
+	mac.w %a5l,%a2u,-(%a1),%d2
+	mac.w %a5l,%a2u,-(%a1),%a7
+	mac.w %a5l,%a2u,-(%a1)&,%d1
+	mac.w %a5l,%a2u,-(%a1)&,%a3
+	mac.w %a5l,%a2u,-(%a1)&,%d2
+	mac.w %a5l,%a2u,-(%a1)&,%a7
+	mac.w %a5l,%a2u,<<,(%a3),%d1
+	mac.w %a5l,%a2u,<<,(%a3),%a3
+	mac.w %a5l,%a2u,<<,(%a3),%d2
+	mac.w %a5l,%a2u,<<,(%a3),%a7
+	mac.w %a5l,%a2u,<<,(%a3)&,%d1
+	mac.w %a5l,%a2u,<<,(%a3)&,%a3
+	mac.w %a5l,%a2u,<<,(%a3)&,%d2
+	mac.w %a5l,%a2u,<<,(%a3)&,%a7
+	mac.w %a5l,%a2u,<<,(%a2)+,%d1
+	mac.w %a5l,%a2u,<<,(%a2)+,%a3
+	mac.w %a5l,%a2u,<<,(%a2)+,%d2
+	mac.w %a5l,%a2u,<<,(%a2)+,%a7
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d1
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a3
+	mac.w %a5l,%a2u,<<,(%a2)+&,%d2
+	mac.w %a5l,%a2u,<<,(%a2)+&,%a7
+	mac.w %a5l,%a2u,<<,10(%a6),%d1
+	mac.w %a5l,%a2u,<<,10(%a6),%a3
+	mac.w %a5l,%a2u,<<,10(%a6),%d2
+	mac.w %a5l,%a2u,<<,10(%a6),%a7
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d1
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a3
+	mac.w %a5l,%a2u,<<,10(%a6)&,%d2
+	mac.w %a5l,%a2u,<<,10(%a6)&,%a7
+	mac.w %a5l,%a2u,<<,-(%a1),%d1
+	mac.w %a5l,%a2u,<<,-(%a1),%a3
+	mac.w %a5l,%a2u,<<,-(%a1),%d2
+	mac.w %a5l,%a2u,<<,-(%a1),%a7
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d1
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a3
+	mac.w %a5l,%a2u,<<,-(%a1)&,%d2
+	mac.w %a5l,%a2u,<<,-(%a1)&,%a7
+	mac.w %a5l,%a2u,>>,(%a3),%d1
+	mac.w %a5l,%a2u,>>,(%a3),%a3
+	mac.w %a5l,%a2u,>>,(%a3),%d2
+	mac.w %a5l,%a2u,>>,(%a3),%a7
+	mac.w %a5l,%a2u,>>,(%a3)&,%d1
+	mac.w %a5l,%a2u,>>,(%a3)&,%a3
+	mac.w %a5l,%a2u,>>,(%a3)&,%d2
+	mac.w %a5l,%a2u,>>,(%a3)&,%a7
+	mac.w %a5l,%a2u,>>,(%a2)+,%d1
+	mac.w %a5l,%a2u,>>,(%a2)+,%a3
+	mac.w %a5l,%a2u,>>,(%a2)+,%d2
+	mac.w %a5l,%a2u,>>,(%a2)+,%a7
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d1
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a3
+	mac.w %a5l,%a2u,>>,(%a2)+&,%d2
+	mac.w %a5l,%a2u,>>,(%a2)+&,%a7
+	mac.w %a5l,%a2u,>>,10(%a6),%d1
+	mac.w %a5l,%a2u,>>,10(%a6),%a3
+	mac.w %a5l,%a2u,>>,10(%a6),%d2
+	mac.w %a5l,%a2u,>>,10(%a6),%a7
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d1
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a3
+	mac.w %a5l,%a2u,>>,10(%a6)&,%d2
+	mac.w %a5l,%a2u,>>,10(%a6)&,%a7
+	mac.w %a5l,%a2u,>>,-(%a1),%d1
+	mac.w %a5l,%a2u,>>,-(%a1),%a3
+	mac.w %a5l,%a2u,>>,-(%a1),%d2
+	mac.w %a5l,%a2u,>>,-(%a1),%a7
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d1
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a3
+	mac.w %a5l,%a2u,>>,-(%a1)&,%d2
+	mac.w %a5l,%a2u,>>,-(%a1)&,%a7
+	mac.w %a5l,%a2u,#1,(%a3),%d1
+	mac.w %a5l,%a2u,#1,(%a3),%a3
+	mac.w %a5l,%a2u,#1,(%a3),%d2
+	mac.w %a5l,%a2u,#1,(%a3),%a7
+	mac.w %a5l,%a2u,#1,(%a3)&,%d1
+	mac.w %a5l,%a2u,#1,(%a3)&,%a3
+	mac.w %a5l,%a2u,#1,(%a3)&,%d2
+	mac.w %a5l,%a2u,#1,(%a3)&,%a7
+	mac.w %a5l,%a2u,#1,(%a2)+,%d1
+	mac.w %a5l,%a2u,#1,(%a2)+,%a3
+	mac.w %a5l,%a2u,#1,(%a2)+,%d2
+	mac.w %a5l,%a2u,#1,(%a2)+,%a7
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d1
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a3
+	mac.w %a5l,%a2u,#1,(%a2)+&,%d2
+	mac.w %a5l,%a2u,#1,(%a2)+&,%a7
+	mac.w %a5l,%a2u,#1,10(%a6),%d1
+	mac.w %a5l,%a2u,#1,10(%a6),%a3
+	mac.w %a5l,%a2u,#1,10(%a6),%d2
+	mac.w %a5l,%a2u,#1,10(%a6),%a7
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d1
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a3
+	mac.w %a5l,%a2u,#1,10(%a6)&,%d2
+	mac.w %a5l,%a2u,#1,10(%a6)&,%a7
+	mac.w %a5l,%a2u,#1,-(%a1),%d1
+	mac.w %a5l,%a2u,#1,-(%a1),%a3
+	mac.w %a5l,%a2u,#1,-(%a1),%d2
+	mac.w %a5l,%a2u,#1,-(%a1),%a7
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d1
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a3
+	mac.w %a5l,%a2u,#1,-(%a1)&,%d2
+	mac.w %a5l,%a2u,#1,-(%a1)&,%a7
+	mac.w %a5l,%a2u,#-1,(%a3),%d1
+	mac.w %a5l,%a2u,#-1,(%a3),%a3
+	mac.w %a5l,%a2u,#-1,(%a3),%d2
+	mac.w %a5l,%a2u,#-1,(%a3),%a7
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d1
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a3
+	mac.w %a5l,%a2u,#-1,(%a3)&,%d2
+	mac.w %a5l,%a2u,#-1,(%a3)&,%a7
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d1
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a3
+	mac.w %a5l,%a2u,#-1,(%a2)+,%d2
+	mac.w %a5l,%a2u,#-1,(%a2)+,%a7
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d1
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a3
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%d2
+	mac.w %a5l,%a2u,#-1,(%a2)+&,%a7
+	mac.w %a5l,%a2u,#-1,10(%a6),%d1
+	mac.w %a5l,%a2u,#-1,10(%a6),%a3
+	mac.w %a5l,%a2u,#-1,10(%a6),%d2
+	mac.w %a5l,%a2u,#-1,10(%a6),%a7
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d1
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a3
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%d2
+	mac.w %a5l,%a2u,#-1,10(%a6)&,%a7
+	mac.w %a5l,%a2u,#-1,-(%a1),%d1
+	mac.w %a5l,%a2u,#-1,-(%a1),%a3
+	mac.w %a5l,%a2u,#-1,-(%a1),%d2
+	mac.w %a5l,%a2u,#-1,-(%a1),%a7
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d1
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a3
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%d2
+	mac.w %a5l,%a2u,#-1,-(%a1)&,%a7
+	mac.w %a5l,%d3l,(%a3),%d1
+	mac.w %a5l,%d3l,(%a3),%a3
+	mac.w %a5l,%d3l,(%a3),%d2
+	mac.w %a5l,%d3l,(%a3),%a7
+	mac.w %a5l,%d3l,(%a3)&,%d1
+	mac.w %a5l,%d3l,(%a3)&,%a3
+	mac.w %a5l,%d3l,(%a3)&,%d2
+	mac.w %a5l,%d3l,(%a3)&,%a7
+	mac.w %a5l,%d3l,(%a2)+,%d1
+	mac.w %a5l,%d3l,(%a2)+,%a3
+	mac.w %a5l,%d3l,(%a2)+,%d2
+	mac.w %a5l,%d3l,(%a2)+,%a7
+	mac.w %a5l,%d3l,(%a2)+&,%d1
+	mac.w %a5l,%d3l,(%a2)+&,%a3
+	mac.w %a5l,%d3l,(%a2)+&,%d2
+	mac.w %a5l,%d3l,(%a2)+&,%a7
+	mac.w %a5l,%d3l,10(%a6),%d1
+	mac.w %a5l,%d3l,10(%a6),%a3
+	mac.w %a5l,%d3l,10(%a6),%d2
+	mac.w %a5l,%d3l,10(%a6),%a7
+	mac.w %a5l,%d3l,10(%a6)&,%d1
+	mac.w %a5l,%d3l,10(%a6)&,%a3
+	mac.w %a5l,%d3l,10(%a6)&,%d2
+	mac.w %a5l,%d3l,10(%a6)&,%a7
+	mac.w %a5l,%d3l,-(%a1),%d1
+	mac.w %a5l,%d3l,-(%a1),%a3
+	mac.w %a5l,%d3l,-(%a1),%d2
+	mac.w %a5l,%d3l,-(%a1),%a7
+	mac.w %a5l,%d3l,-(%a1)&,%d1
+	mac.w %a5l,%d3l,-(%a1)&,%a3
+	mac.w %a5l,%d3l,-(%a1)&,%d2
+	mac.w %a5l,%d3l,-(%a1)&,%a7
+	mac.w %a5l,%d3l,<<,(%a3),%d1
+	mac.w %a5l,%d3l,<<,(%a3),%a3
+	mac.w %a5l,%d3l,<<,(%a3),%d2
+	mac.w %a5l,%d3l,<<,(%a3),%a7
+	mac.w %a5l,%d3l,<<,(%a3)&,%d1
+	mac.w %a5l,%d3l,<<,(%a3)&,%a3
+	mac.w %a5l,%d3l,<<,(%a3)&,%d2
+	mac.w %a5l,%d3l,<<,(%a3)&,%a7
+	mac.w %a5l,%d3l,<<,(%a2)+,%d1
+	mac.w %a5l,%d3l,<<,(%a2)+,%a3
+	mac.w %a5l,%d3l,<<,(%a2)+,%d2
+	mac.w %a5l,%d3l,<<,(%a2)+,%a7
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d1
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a3
+	mac.w %a5l,%d3l,<<,(%a2)+&,%d2
+	mac.w %a5l,%d3l,<<,(%a2)+&,%a7
+	mac.w %a5l,%d3l,<<,10(%a6),%d1
+	mac.w %a5l,%d3l,<<,10(%a6),%a3
+	mac.w %a5l,%d3l,<<,10(%a6),%d2
+	mac.w %a5l,%d3l,<<,10(%a6),%a7
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d1
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a3
+	mac.w %a5l,%d3l,<<,10(%a6)&,%d2
+	mac.w %a5l,%d3l,<<,10(%a6)&,%a7
+	mac.w %a5l,%d3l,<<,-(%a1),%d1
+	mac.w %a5l,%d3l,<<,-(%a1),%a3
+	mac.w %a5l,%d3l,<<,-(%a1),%d2
+	mac.w %a5l,%d3l,<<,-(%a1),%a7
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d1
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a3
+	mac.w %a5l,%d3l,<<,-(%a1)&,%d2
+	mac.w %a5l,%d3l,<<,-(%a1)&,%a7
+	mac.w %a5l,%d3l,>>,(%a3),%d1
+	mac.w %a5l,%d3l,>>,(%a3),%a3
+	mac.w %a5l,%d3l,>>,(%a3),%d2
+	mac.w %a5l,%d3l,>>,(%a3),%a7
+	mac.w %a5l,%d3l,>>,(%a3)&,%d1
+	mac.w %a5l,%d3l,>>,(%a3)&,%a3
+	mac.w %a5l,%d3l,>>,(%a3)&,%d2
+	mac.w %a5l,%d3l,>>,(%a3)&,%a7
+	mac.w %a5l,%d3l,>>,(%a2)+,%d1
+	mac.w %a5l,%d3l,>>,(%a2)+,%a3
+	mac.w %a5l,%d3l,>>,(%a2)+,%d2
+	mac.w %a5l,%d3l,>>,(%a2)+,%a7
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d1
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a3
+	mac.w %a5l,%d3l,>>,(%a2)+&,%d2
+	mac.w %a5l,%d3l,>>,(%a2)+&,%a7
+	mac.w %a5l,%d3l,>>,10(%a6),%d1
+	mac.w %a5l,%d3l,>>,10(%a6),%a3
+	mac.w %a5l,%d3l,>>,10(%a6),%d2
+	mac.w %a5l,%d3l,>>,10(%a6),%a7
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d1
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a3
+	mac.w %a5l,%d3l,>>,10(%a6)&,%d2
+	mac.w %a5l,%d3l,>>,10(%a6)&,%a7
+	mac.w %a5l,%d3l,>>,-(%a1),%d1
+	mac.w %a5l,%d3l,>>,-(%a1),%a3
+	mac.w %a5l,%d3l,>>,-(%a1),%d2
+	mac.w %a5l,%d3l,>>,-(%a1),%a7
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d1
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a3
+	mac.w %a5l,%d3l,>>,-(%a1)&,%d2
+	mac.w %a5l,%d3l,>>,-(%a1)&,%a7
+	mac.w %a5l,%d3l,#1,(%a3),%d1
+	mac.w %a5l,%d3l,#1,(%a3),%a3
+	mac.w %a5l,%d3l,#1,(%a3),%d2
+	mac.w %a5l,%d3l,#1,(%a3),%a7
+	mac.w %a5l,%d3l,#1,(%a3)&,%d1
+	mac.w %a5l,%d3l,#1,(%a3)&,%a3
+	mac.w %a5l,%d3l,#1,(%a3)&,%d2
+	mac.w %a5l,%d3l,#1,(%a3)&,%a7
+	mac.w %a5l,%d3l,#1,(%a2)+,%d1
+	mac.w %a5l,%d3l,#1,(%a2)+,%a3
+	mac.w %a5l,%d3l,#1,(%a2)+,%d2
+	mac.w %a5l,%d3l,#1,(%a2)+,%a7
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d1
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a3
+	mac.w %a5l,%d3l,#1,(%a2)+&,%d2
+	mac.w %a5l,%d3l,#1,(%a2)+&,%a7
+	mac.w %a5l,%d3l,#1,10(%a6),%d1
+	mac.w %a5l,%d3l,#1,10(%a6),%a3
+	mac.w %a5l,%d3l,#1,10(%a6),%d2
+	mac.w %a5l,%d3l,#1,10(%a6),%a7
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d1
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a3
+	mac.w %a5l,%d3l,#1,10(%a6)&,%d2
+	mac.w %a5l,%d3l,#1,10(%a6)&,%a7
+	mac.w %a5l,%d3l,#1,-(%a1),%d1
+	mac.w %a5l,%d3l,#1,-(%a1),%a3
+	mac.w %a5l,%d3l,#1,-(%a1),%d2
+	mac.w %a5l,%d3l,#1,-(%a1),%a7
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d1
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a3
+	mac.w %a5l,%d3l,#1,-(%a1)&,%d2
+	mac.w %a5l,%d3l,#1,-(%a1)&,%a7
+	mac.w %a5l,%d3l,#-1,(%a3),%d1
+	mac.w %a5l,%d3l,#-1,(%a3),%a3
+	mac.w %a5l,%d3l,#-1,(%a3),%d2
+	mac.w %a5l,%d3l,#-1,(%a3),%a7
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d1
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a3
+	mac.w %a5l,%d3l,#-1,(%a3)&,%d2
+	mac.w %a5l,%d3l,#-1,(%a3)&,%a7
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d1
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a3
+	mac.w %a5l,%d3l,#-1,(%a2)+,%d2
+	mac.w %a5l,%d3l,#-1,(%a2)+,%a7
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d1
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a3
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%d2
+	mac.w %a5l,%d3l,#-1,(%a2)+&,%a7
+	mac.w %a5l,%d3l,#-1,10(%a6),%d1
+	mac.w %a5l,%d3l,#-1,10(%a6),%a3
+	mac.w %a5l,%d3l,#-1,10(%a6),%d2
+	mac.w %a5l,%d3l,#-1,10(%a6),%a7
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d1
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a3
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%d2
+	mac.w %a5l,%d3l,#-1,10(%a6)&,%a7
+	mac.w %a5l,%d3l,#-1,-(%a1),%d1
+	mac.w %a5l,%d3l,#-1,-(%a1),%a3
+	mac.w %a5l,%d3l,#-1,-(%a1),%d2
+	mac.w %a5l,%d3l,#-1,-(%a1),%a7
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d1
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a3
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%d2
+	mac.w %a5l,%d3l,#-1,-(%a1)&,%a7
+	mac.w %a5l,%a7u,(%a3),%d1
+	mac.w %a5l,%a7u,(%a3),%a3
+	mac.w %a5l,%a7u,(%a3),%d2
+	mac.w %a5l,%a7u,(%a3),%a7
+	mac.w %a5l,%a7u,(%a3)&,%d1
+	mac.w %a5l,%a7u,(%a3)&,%a3
+	mac.w %a5l,%a7u,(%a3)&,%d2
+	mac.w %a5l,%a7u,(%a3)&,%a7
+	mac.w %a5l,%a7u,(%a2)+,%d1
+	mac.w %a5l,%a7u,(%a2)+,%a3
+	mac.w %a5l,%a7u,(%a2)+,%d2
+	mac.w %a5l,%a7u,(%a2)+,%a7
+	mac.w %a5l,%a7u,(%a2)+&,%d1
+	mac.w %a5l,%a7u,(%a2)+&,%a3
+	mac.w %a5l,%a7u,(%a2)+&,%d2
+	mac.w %a5l,%a7u,(%a2)+&,%a7
+	mac.w %a5l,%a7u,10(%a6),%d1
+	mac.w %a5l,%a7u,10(%a6),%a3
+	mac.w %a5l,%a7u,10(%a6),%d2
+	mac.w %a5l,%a7u,10(%a6),%a7
+	mac.w %a5l,%a7u,10(%a6)&,%d1
+	mac.w %a5l,%a7u,10(%a6)&,%a3
+	mac.w %a5l,%a7u,10(%a6)&,%d2
+	mac.w %a5l,%a7u,10(%a6)&,%a7
+	mac.w %a5l,%a7u,-(%a1),%d1
+	mac.w %a5l,%a7u,-(%a1),%a3
+	mac.w %a5l,%a7u,-(%a1),%d2
+	mac.w %a5l,%a7u,-(%a1),%a7
+	mac.w %a5l,%a7u,-(%a1)&,%d1
+	mac.w %a5l,%a7u,-(%a1)&,%a3
+	mac.w %a5l,%a7u,-(%a1)&,%d2
+	mac.w %a5l,%a7u,-(%a1)&,%a7
+	mac.w %a5l,%a7u,<<,(%a3),%d1
+	mac.w %a5l,%a7u,<<,(%a3),%a3
+	mac.w %a5l,%a7u,<<,(%a3),%d2
+	mac.w %a5l,%a7u,<<,(%a3),%a7
+	mac.w %a5l,%a7u,<<,(%a3)&,%d1
+	mac.w %a5l,%a7u,<<,(%a3)&,%a3
+	mac.w %a5l,%a7u,<<,(%a3)&,%d2
+	mac.w %a5l,%a7u,<<,(%a3)&,%a7
+	mac.w %a5l,%a7u,<<,(%a2)+,%d1
+	mac.w %a5l,%a7u,<<,(%a2)+,%a3
+	mac.w %a5l,%a7u,<<,(%a2)+,%d2
+	mac.w %a5l,%a7u,<<,(%a2)+,%a7
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d1
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a3
+	mac.w %a5l,%a7u,<<,(%a2)+&,%d2
+	mac.w %a5l,%a7u,<<,(%a2)+&,%a7
+	mac.w %a5l,%a7u,<<,10(%a6),%d1
+	mac.w %a5l,%a7u,<<,10(%a6),%a3
+	mac.w %a5l,%a7u,<<,10(%a6),%d2
+	mac.w %a5l,%a7u,<<,10(%a6),%a7
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d1
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a3
+	mac.w %a5l,%a7u,<<,10(%a6)&,%d2
+	mac.w %a5l,%a7u,<<,10(%a6)&,%a7
+	mac.w %a5l,%a7u,<<,-(%a1),%d1
+	mac.w %a5l,%a7u,<<,-(%a1),%a3
+	mac.w %a5l,%a7u,<<,-(%a1),%d2
+	mac.w %a5l,%a7u,<<,-(%a1),%a7
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d1
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a3
+	mac.w %a5l,%a7u,<<,-(%a1)&,%d2
+	mac.w %a5l,%a7u,<<,-(%a1)&,%a7
+	mac.w %a5l,%a7u,>>,(%a3),%d1
+	mac.w %a5l,%a7u,>>,(%a3),%a3
+	mac.w %a5l,%a7u,>>,(%a3),%d2
+	mac.w %a5l,%a7u,>>,(%a3),%a7
+	mac.w %a5l,%a7u,>>,(%a3)&,%d1
+	mac.w %a5l,%a7u,>>,(%a3)&,%a3
+	mac.w %a5l,%a7u,>>,(%a3)&,%d2
+	mac.w %a5l,%a7u,>>,(%a3)&,%a7
+	mac.w %a5l,%a7u,>>,(%a2)+,%d1
+	mac.w %a5l,%a7u,>>,(%a2)+,%a3
+	mac.w %a5l,%a7u,>>,(%a2)+,%d2
+	mac.w %a5l,%a7u,>>,(%a2)+,%a7
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d1
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a3
+	mac.w %a5l,%a7u,>>,(%a2)+&,%d2
+	mac.w %a5l,%a7u,>>,(%a2)+&,%a7
+	mac.w %a5l,%a7u,>>,10(%a6),%d1
+	mac.w %a5l,%a7u,>>,10(%a6),%a3
+	mac.w %a5l,%a7u,>>,10(%a6),%d2
+	mac.w %a5l,%a7u,>>,10(%a6),%a7
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d1
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a3
+	mac.w %a5l,%a7u,>>,10(%a6)&,%d2
+	mac.w %a5l,%a7u,>>,10(%a6)&,%a7
+	mac.w %a5l,%a7u,>>,-(%a1),%d1
+	mac.w %a5l,%a7u,>>,-(%a1),%a3
+	mac.w %a5l,%a7u,>>,-(%a1),%d2
+	mac.w %a5l,%a7u,>>,-(%a1),%a7
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d1
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a3
+	mac.w %a5l,%a7u,>>,-(%a1)&,%d2
+	mac.w %a5l,%a7u,>>,-(%a1)&,%a7
+	mac.w %a5l,%a7u,#1,(%a3),%d1
+	mac.w %a5l,%a7u,#1,(%a3),%a3
+	mac.w %a5l,%a7u,#1,(%a3),%d2
+	mac.w %a5l,%a7u,#1,(%a3),%a7
+	mac.w %a5l,%a7u,#1,(%a3)&,%d1
+	mac.w %a5l,%a7u,#1,(%a3)&,%a3
+	mac.w %a5l,%a7u,#1,(%a3)&,%d2
+	mac.w %a5l,%a7u,#1,(%a3)&,%a7
+	mac.w %a5l,%a7u,#1,(%a2)+,%d1
+	mac.w %a5l,%a7u,#1,(%a2)+,%a3
+	mac.w %a5l,%a7u,#1,(%a2)+,%d2
+	mac.w %a5l,%a7u,#1,(%a2)+,%a7
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d1
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a3
+	mac.w %a5l,%a7u,#1,(%a2)+&,%d2
+	mac.w %a5l,%a7u,#1,(%a2)+&,%a7
+	mac.w %a5l,%a7u,#1,10(%a6),%d1
+	mac.w %a5l,%a7u,#1,10(%a6),%a3
+	mac.w %a5l,%a7u,#1,10(%a6),%d2
+	mac.w %a5l,%a7u,#1,10(%a6),%a7
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d1
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a3
+	mac.w %a5l,%a7u,#1,10(%a6)&,%d2
+	mac.w %a5l,%a7u,#1,10(%a6)&,%a7
+	mac.w %a5l,%a7u,#1,-(%a1),%d1
+	mac.w %a5l,%a7u,#1,-(%a1),%a3
+	mac.w %a5l,%a7u,#1,-(%a1),%d2
+	mac.w %a5l,%a7u,#1,-(%a1),%a7
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d1
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a3
+	mac.w %a5l,%a7u,#1,-(%a1)&,%d2
+	mac.w %a5l,%a7u,#1,-(%a1)&,%a7
+	mac.w %a5l,%a7u,#-1,(%a3),%d1
+	mac.w %a5l,%a7u,#-1,(%a3),%a3
+	mac.w %a5l,%a7u,#-1,(%a3),%d2
+	mac.w %a5l,%a7u,#-1,(%a3),%a7
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d1
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a3
+	mac.w %a5l,%a7u,#-1,(%a3)&,%d2
+	mac.w %a5l,%a7u,#-1,(%a3)&,%a7
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d1
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a3
+	mac.w %a5l,%a7u,#-1,(%a2)+,%d2
+	mac.w %a5l,%a7u,#-1,(%a2)+,%a7
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d1
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a3
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%d2
+	mac.w %a5l,%a7u,#-1,(%a2)+&,%a7
+	mac.w %a5l,%a7u,#-1,10(%a6),%d1
+	mac.w %a5l,%a7u,#-1,10(%a6),%a3
+	mac.w %a5l,%a7u,#-1,10(%a6),%d2
+	mac.w %a5l,%a7u,#-1,10(%a6),%a7
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d1
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a3
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%d2
+	mac.w %a5l,%a7u,#-1,10(%a6)&,%a7
+	mac.w %a5l,%a7u,#-1,-(%a1),%d1
+	mac.w %a5l,%a7u,#-1,-(%a1),%a3
+	mac.w %a5l,%a7u,#-1,-(%a1),%d2
+	mac.w %a5l,%a7u,#-1,-(%a1),%a7
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d1
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a3
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%d2
+	mac.w %a5l,%a7u,#-1,-(%a1)&,%a7
+	mac.w %a5l,%d1l,(%a3),%d1
+	mac.w %a5l,%d1l,(%a3),%a3
+	mac.w %a5l,%d1l,(%a3),%d2
+	mac.w %a5l,%d1l,(%a3),%a7
+	mac.w %a5l,%d1l,(%a3)&,%d1
+	mac.w %a5l,%d1l,(%a3)&,%a3
+	mac.w %a5l,%d1l,(%a3)&,%d2
+	mac.w %a5l,%d1l,(%a3)&,%a7
+	mac.w %a5l,%d1l,(%a2)+,%d1
+	mac.w %a5l,%d1l,(%a2)+,%a3
+	mac.w %a5l,%d1l,(%a2)+,%d2
+	mac.w %a5l,%d1l,(%a2)+,%a7
+	mac.w %a5l,%d1l,(%a2)+&,%d1
+	mac.w %a5l,%d1l,(%a2)+&,%a3
+	mac.w %a5l,%d1l,(%a2)+&,%d2
+	mac.w %a5l,%d1l,(%a2)+&,%a7
+	mac.w %a5l,%d1l,10(%a6),%d1
+	mac.w %a5l,%d1l,10(%a6),%a3
+	mac.w %a5l,%d1l,10(%a6),%d2
+	mac.w %a5l,%d1l,10(%a6),%a7
+	mac.w %a5l,%d1l,10(%a6)&,%d1
+	mac.w %a5l,%d1l,10(%a6)&,%a3
+	mac.w %a5l,%d1l,10(%a6)&,%d2
+	mac.w %a5l,%d1l,10(%a6)&,%a7
+	mac.w %a5l,%d1l,-(%a1),%d1
+	mac.w %a5l,%d1l,-(%a1),%a3
+	mac.w %a5l,%d1l,-(%a1),%d2
+	mac.w %a5l,%d1l,-(%a1),%a7
+	mac.w %a5l,%d1l,-(%a1)&,%d1
+	mac.w %a5l,%d1l,-(%a1)&,%a3
+	mac.w %a5l,%d1l,-(%a1)&,%d2
+	mac.w %a5l,%d1l,-(%a1)&,%a7
+	mac.w %a5l,%d1l,<<,(%a3),%d1
+	mac.w %a5l,%d1l,<<,(%a3),%a3
+	mac.w %a5l,%d1l,<<,(%a3),%d2
+	mac.w %a5l,%d1l,<<,(%a3),%a7
+	mac.w %a5l,%d1l,<<,(%a3)&,%d1
+	mac.w %a5l,%d1l,<<,(%a3)&,%a3
+	mac.w %a5l,%d1l,<<,(%a3)&,%d2
+	mac.w %a5l,%d1l,<<,(%a3)&,%a7
+	mac.w %a5l,%d1l,<<,(%a2)+,%d1
+	mac.w %a5l,%d1l,<<,(%a2)+,%a3
+	mac.w %a5l,%d1l,<<,(%a2)+,%d2
+	mac.w %a5l,%d1l,<<,(%a2)+,%a7
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d1
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a3
+	mac.w %a5l,%d1l,<<,(%a2)+&,%d2
+	mac.w %a5l,%d1l,<<,(%a2)+&,%a7
+	mac.w %a5l,%d1l,<<,10(%a6),%d1
+	mac.w %a5l,%d1l,<<,10(%a6),%a3
+	mac.w %a5l,%d1l,<<,10(%a6),%d2
+	mac.w %a5l,%d1l,<<,10(%a6),%a7
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d1
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a3
+	mac.w %a5l,%d1l,<<,10(%a6)&,%d2
+	mac.w %a5l,%d1l,<<,10(%a6)&,%a7
+	mac.w %a5l,%d1l,<<,-(%a1),%d1
+	mac.w %a5l,%d1l,<<,-(%a1),%a3
+	mac.w %a5l,%d1l,<<,-(%a1),%d2
+	mac.w %a5l,%d1l,<<,-(%a1),%a7
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d1
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a3
+	mac.w %a5l,%d1l,<<,-(%a1)&,%d2
+	mac.w %a5l,%d1l,<<,-(%a1)&,%a7
+	mac.w %a5l,%d1l,>>,(%a3),%d1
+	mac.w %a5l,%d1l,>>,(%a3),%a3
+	mac.w %a5l,%d1l,>>,(%a3),%d2
+	mac.w %a5l,%d1l,>>,(%a3),%a7
+	mac.w %a5l,%d1l,>>,(%a3)&,%d1
+	mac.w %a5l,%d1l,>>,(%a3)&,%a3
+	mac.w %a5l,%d1l,>>,(%a3)&,%d2
+	mac.w %a5l,%d1l,>>,(%a3)&,%a7
+	mac.w %a5l,%d1l,>>,(%a2)+,%d1
+	mac.w %a5l,%d1l,>>,(%a2)+,%a3
+	mac.w %a5l,%d1l,>>,(%a2)+,%d2
+	mac.w %a5l,%d1l,>>,(%a2)+,%a7
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d1
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a3
+	mac.w %a5l,%d1l,>>,(%a2)+&,%d2
+	mac.w %a5l,%d1l,>>,(%a2)+&,%a7
+	mac.w %a5l,%d1l,>>,10(%a6),%d1
+	mac.w %a5l,%d1l,>>,10(%a6),%a3
+	mac.w %a5l,%d1l,>>,10(%a6),%d2
+	mac.w %a5l,%d1l,>>,10(%a6),%a7
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d1
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a3
+	mac.w %a5l,%d1l,>>,10(%a6)&,%d2
+	mac.w %a5l,%d1l,>>,10(%a6)&,%a7
+	mac.w %a5l,%d1l,>>,-(%a1),%d1
+	mac.w %a5l,%d1l,>>,-(%a1),%a3
+	mac.w %a5l,%d1l,>>,-(%a1),%d2
+	mac.w %a5l,%d1l,>>,-(%a1),%a7
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d1
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a3
+	mac.w %a5l,%d1l,>>,-(%a1)&,%d2
+	mac.w %a5l,%d1l,>>,-(%a1)&,%a7
+	mac.w %a5l,%d1l,#1,(%a3),%d1
+	mac.w %a5l,%d1l,#1,(%a3),%a3
+	mac.w %a5l,%d1l,#1,(%a3),%d2
+	mac.w %a5l,%d1l,#1,(%a3),%a7
+	mac.w %a5l,%d1l,#1,(%a3)&,%d1
+	mac.w %a5l,%d1l,#1,(%a3)&,%a3
+	mac.w %a5l,%d1l,#1,(%a3)&,%d2
+	mac.w %a5l,%d1l,#1,(%a3)&,%a7
+	mac.w %a5l,%d1l,#1,(%a2)+,%d1
+	mac.w %a5l,%d1l,#1,(%a2)+,%a3
+	mac.w %a5l,%d1l,#1,(%a2)+,%d2
+	mac.w %a5l,%d1l,#1,(%a2)+,%a7
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d1
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a3
+	mac.w %a5l,%d1l,#1,(%a2)+&,%d2
+	mac.w %a5l,%d1l,#1,(%a2)+&,%a7
+	mac.w %a5l,%d1l,#1,10(%a6),%d1
+	mac.w %a5l,%d1l,#1,10(%a6),%a3
+	mac.w %a5l,%d1l,#1,10(%a6),%d2
+	mac.w %a5l,%d1l,#1,10(%a6),%a7
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d1
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a3
+	mac.w %a5l,%d1l,#1,10(%a6)&,%d2
+	mac.w %a5l,%d1l,#1,10(%a6)&,%a7
+	mac.w %a5l,%d1l,#1,-(%a1),%d1
+	mac.w %a5l,%d1l,#1,-(%a1),%a3
+	mac.w %a5l,%d1l,#1,-(%a1),%d2
+	mac.w %a5l,%d1l,#1,-(%a1),%a7
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d1
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a3
+	mac.w %a5l,%d1l,#1,-(%a1)&,%d2
+	mac.w %a5l,%d1l,#1,-(%a1)&,%a7
+	mac.w %a5l,%d1l,#-1,(%a3),%d1
+	mac.w %a5l,%d1l,#-1,(%a3),%a3
+	mac.w %a5l,%d1l,#-1,(%a3),%d2
+	mac.w %a5l,%d1l,#-1,(%a3),%a7
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d1
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a3
+	mac.w %a5l,%d1l,#-1,(%a3)&,%d2
+	mac.w %a5l,%d1l,#-1,(%a3)&,%a7
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d1
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a3
+	mac.w %a5l,%d1l,#-1,(%a2)+,%d2
+	mac.w %a5l,%d1l,#-1,(%a2)+,%a7
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d1
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a3
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%d2
+	mac.w %a5l,%d1l,#-1,(%a2)+&,%a7
+	mac.w %a5l,%d1l,#-1,10(%a6),%d1
+	mac.w %a5l,%d1l,#-1,10(%a6),%a3
+	mac.w %a5l,%d1l,#-1,10(%a6),%d2
+	mac.w %a5l,%d1l,#-1,10(%a6),%a7
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d1
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a3
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%d2
+	mac.w %a5l,%d1l,#-1,10(%a6)&,%a7
+	mac.w %a5l,%d1l,#-1,-(%a1),%d1
+	mac.w %a5l,%d1l,#-1,-(%a1),%a3
+	mac.w %a5l,%d1l,#-1,-(%a1),%d2
+	mac.w %a5l,%d1l,#-1,-(%a1),%a7
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d1
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a3
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%d2
+	mac.w %a5l,%d1l,#-1,-(%a1)&,%a7
+	mac.w %d6u,%a2u,(%a3),%d1
+	mac.w %d6u,%a2u,(%a3),%a3
+	mac.w %d6u,%a2u,(%a3),%d2
+	mac.w %d6u,%a2u,(%a3),%a7
+	mac.w %d6u,%a2u,(%a3)&,%d1
+	mac.w %d6u,%a2u,(%a3)&,%a3
+	mac.w %d6u,%a2u,(%a3)&,%d2
+	mac.w %d6u,%a2u,(%a3)&,%a7
+	mac.w %d6u,%a2u,(%a2)+,%d1
+	mac.w %d6u,%a2u,(%a2)+,%a3
+	mac.w %d6u,%a2u,(%a2)+,%d2
+	mac.w %d6u,%a2u,(%a2)+,%a7
+	mac.w %d6u,%a2u,(%a2)+&,%d1
+	mac.w %d6u,%a2u,(%a2)+&,%a3
+	mac.w %d6u,%a2u,(%a2)+&,%d2
+	mac.w %d6u,%a2u,(%a2)+&,%a7
+	mac.w %d6u,%a2u,10(%a6),%d1
+	mac.w %d6u,%a2u,10(%a6),%a3
+	mac.w %d6u,%a2u,10(%a6),%d2
+	mac.w %d6u,%a2u,10(%a6),%a7
+	mac.w %d6u,%a2u,10(%a6)&,%d1
+	mac.w %d6u,%a2u,10(%a6)&,%a3
+	mac.w %d6u,%a2u,10(%a6)&,%d2
+	mac.w %d6u,%a2u,10(%a6)&,%a7
+	mac.w %d6u,%a2u,-(%a1),%d1
+	mac.w %d6u,%a2u,-(%a1),%a3
+	mac.w %d6u,%a2u,-(%a1),%d2
+	mac.w %d6u,%a2u,-(%a1),%a7
+	mac.w %d6u,%a2u,-(%a1)&,%d1
+	mac.w %d6u,%a2u,-(%a1)&,%a3
+	mac.w %d6u,%a2u,-(%a1)&,%d2
+	mac.w %d6u,%a2u,-(%a1)&,%a7
+	mac.w %d6u,%a2u,<<,(%a3),%d1
+	mac.w %d6u,%a2u,<<,(%a3),%a3
+	mac.w %d6u,%a2u,<<,(%a3),%d2
+	mac.w %d6u,%a2u,<<,(%a3),%a7
+	mac.w %d6u,%a2u,<<,(%a3)&,%d1
+	mac.w %d6u,%a2u,<<,(%a3)&,%a3
+	mac.w %d6u,%a2u,<<,(%a3)&,%d2
+	mac.w %d6u,%a2u,<<,(%a3)&,%a7
+	mac.w %d6u,%a2u,<<,(%a2)+,%d1
+	mac.w %d6u,%a2u,<<,(%a2)+,%a3
+	mac.w %d6u,%a2u,<<,(%a2)+,%d2
+	mac.w %d6u,%a2u,<<,(%a2)+,%a7
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d1
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a3
+	mac.w %d6u,%a2u,<<,(%a2)+&,%d2
+	mac.w %d6u,%a2u,<<,(%a2)+&,%a7
+	mac.w %d6u,%a2u,<<,10(%a6),%d1
+	mac.w %d6u,%a2u,<<,10(%a6),%a3
+	mac.w %d6u,%a2u,<<,10(%a6),%d2
+	mac.w %d6u,%a2u,<<,10(%a6),%a7
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d1
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a3
+	mac.w %d6u,%a2u,<<,10(%a6)&,%d2
+	mac.w %d6u,%a2u,<<,10(%a6)&,%a7
+	mac.w %d6u,%a2u,<<,-(%a1),%d1
+	mac.w %d6u,%a2u,<<,-(%a1),%a3
+	mac.w %d6u,%a2u,<<,-(%a1),%d2
+	mac.w %d6u,%a2u,<<,-(%a1),%a7
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d1
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a3
+	mac.w %d6u,%a2u,<<,-(%a1)&,%d2
+	mac.w %d6u,%a2u,<<,-(%a1)&,%a7
+	mac.w %d6u,%a2u,>>,(%a3),%d1
+	mac.w %d6u,%a2u,>>,(%a3),%a3
+	mac.w %d6u,%a2u,>>,(%a3),%d2
+	mac.w %d6u,%a2u,>>,(%a3),%a7
+	mac.w %d6u,%a2u,>>,(%a3)&,%d1
+	mac.w %d6u,%a2u,>>,(%a3)&,%a3
+	mac.w %d6u,%a2u,>>,(%a3)&,%d2
+	mac.w %d6u,%a2u,>>,(%a3)&,%a7
+	mac.w %d6u,%a2u,>>,(%a2)+,%d1
+	mac.w %d6u,%a2u,>>,(%a2)+,%a3
+	mac.w %d6u,%a2u,>>,(%a2)+,%d2
+	mac.w %d6u,%a2u,>>,(%a2)+,%a7
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d1
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a3
+	mac.w %d6u,%a2u,>>,(%a2)+&,%d2
+	mac.w %d6u,%a2u,>>,(%a2)+&,%a7
+	mac.w %d6u,%a2u,>>,10(%a6),%d1
+	mac.w %d6u,%a2u,>>,10(%a6),%a3
+	mac.w %d6u,%a2u,>>,10(%a6),%d2
+	mac.w %d6u,%a2u,>>,10(%a6),%a7
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d1
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a3
+	mac.w %d6u,%a2u,>>,10(%a6)&,%d2
+	mac.w %d6u,%a2u,>>,10(%a6)&,%a7
+	mac.w %d6u,%a2u,>>,-(%a1),%d1
+	mac.w %d6u,%a2u,>>,-(%a1),%a3
+	mac.w %d6u,%a2u,>>,-(%a1),%d2
+	mac.w %d6u,%a2u,>>,-(%a1),%a7
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d1
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a3
+	mac.w %d6u,%a2u,>>,-(%a1)&,%d2
+	mac.w %d6u,%a2u,>>,-(%a1)&,%a7
+	mac.w %d6u,%a2u,#1,(%a3),%d1
+	mac.w %d6u,%a2u,#1,(%a3),%a3
+	mac.w %d6u,%a2u,#1,(%a3),%d2
+	mac.w %d6u,%a2u,#1,(%a3),%a7
+	mac.w %d6u,%a2u,#1,(%a3)&,%d1
+	mac.w %d6u,%a2u,#1,(%a3)&,%a3
+	mac.w %d6u,%a2u,#1,(%a3)&,%d2
+	mac.w %d6u,%a2u,#1,(%a3)&,%a7
+	mac.w %d6u,%a2u,#1,(%a2)+,%d1
+	mac.w %d6u,%a2u,#1,(%a2)+,%a3
+	mac.w %d6u,%a2u,#1,(%a2)+,%d2
+	mac.w %d6u,%a2u,#1,(%a2)+,%a7
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d1
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a3
+	mac.w %d6u,%a2u,#1,(%a2)+&,%d2
+	mac.w %d6u,%a2u,#1,(%a2)+&,%a7
+	mac.w %d6u,%a2u,#1,10(%a6),%d1
+	mac.w %d6u,%a2u,#1,10(%a6),%a3
+	mac.w %d6u,%a2u,#1,10(%a6),%d2
+	mac.w %d6u,%a2u,#1,10(%a6),%a7
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d1
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a3
+	mac.w %d6u,%a2u,#1,10(%a6)&,%d2
+	mac.w %d6u,%a2u,#1,10(%a6)&,%a7
+	mac.w %d6u,%a2u,#1,-(%a1),%d1
+	mac.w %d6u,%a2u,#1,-(%a1),%a3
+	mac.w %d6u,%a2u,#1,-(%a1),%d2
+	mac.w %d6u,%a2u,#1,-(%a1),%a7
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d1
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a3
+	mac.w %d6u,%a2u,#1,-(%a1)&,%d2
+	mac.w %d6u,%a2u,#1,-(%a1)&,%a7
+	mac.w %d6u,%a2u,#-1,(%a3),%d1
+	mac.w %d6u,%a2u,#-1,(%a3),%a3
+	mac.w %d6u,%a2u,#-1,(%a3),%d2
+	mac.w %d6u,%a2u,#-1,(%a3),%a7
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d1
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a3
+	mac.w %d6u,%a2u,#-1,(%a3)&,%d2
+	mac.w %d6u,%a2u,#-1,(%a3)&,%a7
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d1
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a3
+	mac.w %d6u,%a2u,#-1,(%a2)+,%d2
+	mac.w %d6u,%a2u,#-1,(%a2)+,%a7
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d1
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a3
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%d2
+	mac.w %d6u,%a2u,#-1,(%a2)+&,%a7
+	mac.w %d6u,%a2u,#-1,10(%a6),%d1
+	mac.w %d6u,%a2u,#-1,10(%a6),%a3
+	mac.w %d6u,%a2u,#-1,10(%a6),%d2
+	mac.w %d6u,%a2u,#-1,10(%a6),%a7
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d1
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a3
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%d2
+	mac.w %d6u,%a2u,#-1,10(%a6)&,%a7
+	mac.w %d6u,%a2u,#-1,-(%a1),%d1
+	mac.w %d6u,%a2u,#-1,-(%a1),%a3
+	mac.w %d6u,%a2u,#-1,-(%a1),%d2
+	mac.w %d6u,%a2u,#-1,-(%a1),%a7
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d1
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a3
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%d2
+	mac.w %d6u,%a2u,#-1,-(%a1)&,%a7
+	mac.w %d6u,%d3l,(%a3),%d1
+	mac.w %d6u,%d3l,(%a3),%a3
+	mac.w %d6u,%d3l,(%a3),%d2
+	mac.w %d6u,%d3l,(%a3),%a7
+	mac.w %d6u,%d3l,(%a3)&,%d1
+	mac.w %d6u,%d3l,(%a3)&,%a3
+	mac.w %d6u,%d3l,(%a3)&,%d2
+	mac.w %d6u,%d3l,(%a3)&,%a7
+	mac.w %d6u,%d3l,(%a2)+,%d1
+	mac.w %d6u,%d3l,(%a2)+,%a3
+	mac.w %d6u,%d3l,(%a2)+,%d2
+	mac.w %d6u,%d3l,(%a2)+,%a7
+	mac.w %d6u,%d3l,(%a2)+&,%d1
+	mac.w %d6u,%d3l,(%a2)+&,%a3
+	mac.w %d6u,%d3l,(%a2)+&,%d2
+	mac.w %d6u,%d3l,(%a2)+&,%a7
+	mac.w %d6u,%d3l,10(%a6),%d1
+	mac.w %d6u,%d3l,10(%a6),%a3
+	mac.w %d6u,%d3l,10(%a6),%d2
+	mac.w %d6u,%d3l,10(%a6),%a7
+	mac.w %d6u,%d3l,10(%a6)&,%d1
+	mac.w %d6u,%d3l,10(%a6)&,%a3
+	mac.w %d6u,%d3l,10(%a6)&,%d2
+	mac.w %d6u,%d3l,10(%a6)&,%a7
+	mac.w %d6u,%d3l,-(%a1),%d1
+	mac.w %d6u,%d3l,-(%a1),%a3
+	mac.w %d6u,%d3l,-(%a1),%d2
+	mac.w %d6u,%d3l,-(%a1),%a7
+	mac.w %d6u,%d3l,-(%a1)&,%d1
+	mac.w %d6u,%d3l,-(%a1)&,%a3
+	mac.w %d6u,%d3l,-(%a1)&,%d2
+	mac.w %d6u,%d3l,-(%a1)&,%a7
+	mac.w %d6u,%d3l,<<,(%a3),%d1
+	mac.w %d6u,%d3l,<<,(%a3),%a3
+	mac.w %d6u,%d3l,<<,(%a3),%d2
+	mac.w %d6u,%d3l,<<,(%a3),%a7
+	mac.w %d6u,%d3l,<<,(%a3)&,%d1
+	mac.w %d6u,%d3l,<<,(%a3)&,%a3
+	mac.w %d6u,%d3l,<<,(%a3)&,%d2
+	mac.w %d6u,%d3l,<<,(%a3)&,%a7
+	mac.w %d6u,%d3l,<<,(%a2)+,%d1
+	mac.w %d6u,%d3l,<<,(%a2)+,%a3
+	mac.w %d6u,%d3l,<<,(%a2)+,%d2
+	mac.w %d6u,%d3l,<<,(%a2)+,%a7
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d1
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a3
+	mac.w %d6u,%d3l,<<,(%a2)+&,%d2
+	mac.w %d6u,%d3l,<<,(%a2)+&,%a7
+	mac.w %d6u,%d3l,<<,10(%a6),%d1
+	mac.w %d6u,%d3l,<<,10(%a6),%a3
+	mac.w %d6u,%d3l,<<,10(%a6),%d2
+	mac.w %d6u,%d3l,<<,10(%a6),%a7
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d1
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a3
+	mac.w %d6u,%d3l,<<,10(%a6)&,%d2
+	mac.w %d6u,%d3l,<<,10(%a6)&,%a7
+	mac.w %d6u,%d3l,<<,-(%a1),%d1
+	mac.w %d6u,%d3l,<<,-(%a1),%a3
+	mac.w %d6u,%d3l,<<,-(%a1),%d2
+	mac.w %d6u,%d3l,<<,-(%a1),%a7
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d1
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a3
+	mac.w %d6u,%d3l,<<,-(%a1)&,%d2
+	mac.w %d6u,%d3l,<<,-(%a1)&,%a7
+	mac.w %d6u,%d3l,>>,(%a3),%d1
+	mac.w %d6u,%d3l,>>,(%a3),%a3
+	mac.w %d6u,%d3l,>>,(%a3),%d2
+	mac.w %d6u,%d3l,>>,(%a3),%a7
+	mac.w %d6u,%d3l,>>,(%a3)&,%d1
+	mac.w %d6u,%d3l,>>,(%a3)&,%a3
+	mac.w %d6u,%d3l,>>,(%a3)&,%d2
+	mac.w %d6u,%d3l,>>,(%a3)&,%a7
+	mac.w %d6u,%d3l,>>,(%a2)+,%d1
+	mac.w %d6u,%d3l,>>,(%a2)+,%a3
+	mac.w %d6u,%d3l,>>,(%a2)+,%d2
+	mac.w %d6u,%d3l,>>,(%a2)+,%a7
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d1
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a3
+	mac.w %d6u,%d3l,>>,(%a2)+&,%d2
+	mac.w %d6u,%d3l,>>,(%a2)+&,%a7
+	mac.w %d6u,%d3l,>>,10(%a6),%d1
+	mac.w %d6u,%d3l,>>,10(%a6),%a3
+	mac.w %d6u,%d3l,>>,10(%a6),%d2
+	mac.w %d6u,%d3l,>>,10(%a6),%a7
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d1
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a3
+	mac.w %d6u,%d3l,>>,10(%a6)&,%d2
+	mac.w %d6u,%d3l,>>,10(%a6)&,%a7
+	mac.w %d6u,%d3l,>>,-(%a1),%d1
+	mac.w %d6u,%d3l,>>,-(%a1),%a3
+	mac.w %d6u,%d3l,>>,-(%a1),%d2
+	mac.w %d6u,%d3l,>>,-(%a1),%a7
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d1
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a3
+	mac.w %d6u,%d3l,>>,-(%a1)&,%d2
+	mac.w %d6u,%d3l,>>,-(%a1)&,%a7
+	mac.w %d6u,%d3l,#1,(%a3),%d1
+	mac.w %d6u,%d3l,#1,(%a3),%a3
+	mac.w %d6u,%d3l,#1,(%a3),%d2
+	mac.w %d6u,%d3l,#1,(%a3),%a7
+	mac.w %d6u,%d3l,#1,(%a3)&,%d1
+	mac.w %d6u,%d3l,#1,(%a3)&,%a3
+	mac.w %d6u,%d3l,#1,(%a3)&,%d2
+	mac.w %d6u,%d3l,#1,(%a3)&,%a7
+	mac.w %d6u,%d3l,#1,(%a2)+,%d1
+	mac.w %d6u,%d3l,#1,(%a2)+,%a3
+	mac.w %d6u,%d3l,#1,(%a2)+,%d2
+	mac.w %d6u,%d3l,#1,(%a2)+,%a7
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d1
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a3
+	mac.w %d6u,%d3l,#1,(%a2)+&,%d2
+	mac.w %d6u,%d3l,#1,(%a2)+&,%a7
+	mac.w %d6u,%d3l,#1,10(%a6),%d1
+	mac.w %d6u,%d3l,#1,10(%a6),%a3
+	mac.w %d6u,%d3l,#1,10(%a6),%d2
+	mac.w %d6u,%d3l,#1,10(%a6),%a7
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d1
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a3
+	mac.w %d6u,%d3l,#1,10(%a6)&,%d2
+	mac.w %d6u,%d3l,#1,10(%a6)&,%a7
+	mac.w %d6u,%d3l,#1,-(%a1),%d1
+	mac.w %d6u,%d3l,#1,-(%a1),%a3
+	mac.w %d6u,%d3l,#1,-(%a1),%d2
+	mac.w %d6u,%d3l,#1,-(%a1),%a7
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d1
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a3
+	mac.w %d6u,%d3l,#1,-(%a1)&,%d2
+	mac.w %d6u,%d3l,#1,-(%a1)&,%a7
+	mac.w %d6u,%d3l,#-1,(%a3),%d1
+	mac.w %d6u,%d3l,#-1,(%a3),%a3
+	mac.w %d6u,%d3l,#-1,(%a3),%d2
+	mac.w %d6u,%d3l,#-1,(%a3),%a7
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d1
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a3
+	mac.w %d6u,%d3l,#-1,(%a3)&,%d2
+	mac.w %d6u,%d3l,#-1,(%a3)&,%a7
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d1
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a3
+	mac.w %d6u,%d3l,#-1,(%a2)+,%d2
+	mac.w %d6u,%d3l,#-1,(%a2)+,%a7
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d1
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a3
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%d2
+	mac.w %d6u,%d3l,#-1,(%a2)+&,%a7
+	mac.w %d6u,%d3l,#-1,10(%a6),%d1
+	mac.w %d6u,%d3l,#-1,10(%a6),%a3
+	mac.w %d6u,%d3l,#-1,10(%a6),%d2
+	mac.w %d6u,%d3l,#-1,10(%a6),%a7
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d1
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a3
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%d2
+	mac.w %d6u,%d3l,#-1,10(%a6)&,%a7
+	mac.w %d6u,%d3l,#-1,-(%a1),%d1
+	mac.w %d6u,%d3l,#-1,-(%a1),%a3
+	mac.w %d6u,%d3l,#-1,-(%a1),%d2
+	mac.w %d6u,%d3l,#-1,-(%a1),%a7
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d1
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a3
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%d2
+	mac.w %d6u,%d3l,#-1,-(%a1)&,%a7
+	mac.w %d6u,%a7u,(%a3),%d1
+	mac.w %d6u,%a7u,(%a3),%a3
+	mac.w %d6u,%a7u,(%a3),%d2
+	mac.w %d6u,%a7u,(%a3),%a7
+	mac.w %d6u,%a7u,(%a3)&,%d1
+	mac.w %d6u,%a7u,(%a3)&,%a3
+	mac.w %d6u,%a7u,(%a3)&,%d2
+	mac.w %d6u,%a7u,(%a3)&,%a7
+	mac.w %d6u,%a7u,(%a2)+,%d1
+	mac.w %d6u,%a7u,(%a2)+,%a3
+	mac.w %d6u,%a7u,(%a2)+,%d2
+	mac.w %d6u,%a7u,(%a2)+,%a7
+	mac.w %d6u,%a7u,(%a2)+&,%d1
+	mac.w %d6u,%a7u,(%a2)+&,%a3
+	mac.w %d6u,%a7u,(%a2)+&,%d2
+	mac.w %d6u,%a7u,(%a2)+&,%a7
+	mac.w %d6u,%a7u,10(%a6),%d1
+	mac.w %d6u,%a7u,10(%a6),%a3
+	mac.w %d6u,%a7u,10(%a6),%d2
+	mac.w %d6u,%a7u,10(%a6),%a7
+	mac.w %d6u,%a7u,10(%a6)&,%d1
+	mac.w %d6u,%a7u,10(%a6)&,%a3
+	mac.w %d6u,%a7u,10(%a6)&,%d2
+	mac.w %d6u,%a7u,10(%a6)&,%a7
+	mac.w %d6u,%a7u,-(%a1),%d1
+	mac.w %d6u,%a7u,-(%a1),%a3
+	mac.w %d6u,%a7u,-(%a1),%d2
+	mac.w %d6u,%a7u,-(%a1),%a7
+	mac.w %d6u,%a7u,-(%a1)&,%d1
+	mac.w %d6u,%a7u,-(%a1)&,%a3
+	mac.w %d6u,%a7u,-(%a1)&,%d2
+	mac.w %d6u,%a7u,-(%a1)&,%a7
+	mac.w %d6u,%a7u,<<,(%a3),%d1
+	mac.w %d6u,%a7u,<<,(%a3),%a3
+	mac.w %d6u,%a7u,<<,(%a3),%d2
+	mac.w %d6u,%a7u,<<,(%a3),%a7
+	mac.w %d6u,%a7u,<<,(%a3)&,%d1
+	mac.w %d6u,%a7u,<<,(%a3)&,%a3
+	mac.w %d6u,%a7u,<<,(%a3)&,%d2
+	mac.w %d6u,%a7u,<<,(%a3)&,%a7
+	mac.w %d6u,%a7u,<<,(%a2)+,%d1
+	mac.w %d6u,%a7u,<<,(%a2)+,%a3
+	mac.w %d6u,%a7u,<<,(%a2)+,%d2
+	mac.w %d6u,%a7u,<<,(%a2)+,%a7
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d1
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a3
+	mac.w %d6u,%a7u,<<,(%a2)+&,%d2
+	mac.w %d6u,%a7u,<<,(%a2)+&,%a7
+	mac.w %d6u,%a7u,<<,10(%a6),%d1
+	mac.w %d6u,%a7u,<<,10(%a6),%a3
+	mac.w %d6u,%a7u,<<,10(%a6),%d2
+	mac.w %d6u,%a7u,<<,10(%a6),%a7
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d1
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a3
+	mac.w %d6u,%a7u,<<,10(%a6)&,%d2
+	mac.w %d6u,%a7u,<<,10(%a6)&,%a7
+	mac.w %d6u,%a7u,<<,-(%a1),%d1
+	mac.w %d6u,%a7u,<<,-(%a1),%a3
+	mac.w %d6u,%a7u,<<,-(%a1),%d2
+	mac.w %d6u,%a7u,<<,-(%a1),%a7
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d1
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a3
+	mac.w %d6u,%a7u,<<,-(%a1)&,%d2
+	mac.w %d6u,%a7u,<<,-(%a1)&,%a7
+	mac.w %d6u,%a7u,>>,(%a3),%d1
+	mac.w %d6u,%a7u,>>,(%a3),%a3
+	mac.w %d6u,%a7u,>>,(%a3),%d2
+	mac.w %d6u,%a7u,>>,(%a3),%a7
+	mac.w %d6u,%a7u,>>,(%a3)&,%d1
+	mac.w %d6u,%a7u,>>,(%a3)&,%a3
+	mac.w %d6u,%a7u,>>,(%a3)&,%d2
+	mac.w %d6u,%a7u,>>,(%a3)&,%a7
+	mac.w %d6u,%a7u,>>,(%a2)+,%d1
+	mac.w %d6u,%a7u,>>,(%a2)+,%a3
+	mac.w %d6u,%a7u,>>,(%a2)+,%d2
+	mac.w %d6u,%a7u,>>,(%a2)+,%a7
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d1
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a3
+	mac.w %d6u,%a7u,>>,(%a2)+&,%d2
+	mac.w %d6u,%a7u,>>,(%a2)+&,%a7
+	mac.w %d6u,%a7u,>>,10(%a6),%d1
+	mac.w %d6u,%a7u,>>,10(%a6),%a3
+	mac.w %d6u,%a7u,>>,10(%a6),%d2
+	mac.w %d6u,%a7u,>>,10(%a6),%a7
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d1
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a3
+	mac.w %d6u,%a7u,>>,10(%a6)&,%d2
+	mac.w %d6u,%a7u,>>,10(%a6)&,%a7
+	mac.w %d6u,%a7u,>>,-(%a1),%d1
+	mac.w %d6u,%a7u,>>,-(%a1),%a3
+	mac.w %d6u,%a7u,>>,-(%a1),%d2
+	mac.w %d6u,%a7u,>>,-(%a1),%a7
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d1
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a3
+	mac.w %d6u,%a7u,>>,-(%a1)&,%d2
+	mac.w %d6u,%a7u,>>,-(%a1)&,%a7
+	mac.w %d6u,%a7u,#1,(%a3),%d1
+	mac.w %d6u,%a7u,#1,(%a3),%a3
+	mac.w %d6u,%a7u,#1,(%a3),%d2
+	mac.w %d6u,%a7u,#1,(%a3),%a7
+	mac.w %d6u,%a7u,#1,(%a3)&,%d1
+	mac.w %d6u,%a7u,#1,(%a3)&,%a3
+	mac.w %d6u,%a7u,#1,(%a3)&,%d2
+	mac.w %d6u,%a7u,#1,(%a3)&,%a7
+	mac.w %d6u,%a7u,#1,(%a2)+,%d1
+	mac.w %d6u,%a7u,#1,(%a2)+,%a3
+	mac.w %d6u,%a7u,#1,(%a2)+,%d2
+	mac.w %d6u,%a7u,#1,(%a2)+,%a7
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d1
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a3
+	mac.w %d6u,%a7u,#1,(%a2)+&,%d2
+	mac.w %d6u,%a7u,#1,(%a2)+&,%a7
+	mac.w %d6u,%a7u,#1,10(%a6),%d1
+	mac.w %d6u,%a7u,#1,10(%a6),%a3
+	mac.w %d6u,%a7u,#1,10(%a6),%d2
+	mac.w %d6u,%a7u,#1,10(%a6),%a7
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d1
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a3
+	mac.w %d6u,%a7u,#1,10(%a6)&,%d2
+	mac.w %d6u,%a7u,#1,10(%a6)&,%a7
+	mac.w %d6u,%a7u,#1,-(%a1),%d1
+	mac.w %d6u,%a7u,#1,-(%a1),%a3
+	mac.w %d6u,%a7u,#1,-(%a1),%d2
+	mac.w %d6u,%a7u,#1,-(%a1),%a7
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d1
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a3
+	mac.w %d6u,%a7u,#1,-(%a1)&,%d2
+	mac.w %d6u,%a7u,#1,-(%a1)&,%a7
+	mac.w %d6u,%a7u,#-1,(%a3),%d1
+	mac.w %d6u,%a7u,#-1,(%a3),%a3
+	mac.w %d6u,%a7u,#-1,(%a3),%d2
+	mac.w %d6u,%a7u,#-1,(%a3),%a7
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d1
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a3
+	mac.w %d6u,%a7u,#-1,(%a3)&,%d2
+	mac.w %d6u,%a7u,#-1,(%a3)&,%a7
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d1
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a3
+	mac.w %d6u,%a7u,#-1,(%a2)+,%d2
+	mac.w %d6u,%a7u,#-1,(%a2)+,%a7
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d1
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a3
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%d2
+	mac.w %d6u,%a7u,#-1,(%a2)+&,%a7
+	mac.w %d6u,%a7u,#-1,10(%a6),%d1
+	mac.w %d6u,%a7u,#-1,10(%a6),%a3
+	mac.w %d6u,%a7u,#-1,10(%a6),%d2
+	mac.w %d6u,%a7u,#-1,10(%a6),%a7
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d1
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a3
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%d2
+	mac.w %d6u,%a7u,#-1,10(%a6)&,%a7
+	mac.w %d6u,%a7u,#-1,-(%a1),%d1
+	mac.w %d6u,%a7u,#-1,-(%a1),%a3
+	mac.w %d6u,%a7u,#-1,-(%a1),%d2
+	mac.w %d6u,%a7u,#-1,-(%a1),%a7
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d1
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a3
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%d2
+	mac.w %d6u,%a7u,#-1,-(%a1)&,%a7
+	mac.w %d6u,%d1l,(%a3),%d1
+	mac.w %d6u,%d1l,(%a3),%a3
+	mac.w %d6u,%d1l,(%a3),%d2
+	mac.w %d6u,%d1l,(%a3),%a7
+	mac.w %d6u,%d1l,(%a3)&,%d1
+	mac.w %d6u,%d1l,(%a3)&,%a3
+	mac.w %d6u,%d1l,(%a3)&,%d2
+	mac.w %d6u,%d1l,(%a3)&,%a7
+	mac.w %d6u,%d1l,(%a2)+,%d1
+	mac.w %d6u,%d1l,(%a2)+,%a3
+	mac.w %d6u,%d1l,(%a2)+,%d2
+	mac.w %d6u,%d1l,(%a2)+,%a7
+	mac.w %d6u,%d1l,(%a2)+&,%d1
+	mac.w %d6u,%d1l,(%a2)+&,%a3
+	mac.w %d6u,%d1l,(%a2)+&,%d2
+	mac.w %d6u,%d1l,(%a2)+&,%a7
+	mac.w %d6u,%d1l,10(%a6),%d1
+	mac.w %d6u,%d1l,10(%a6),%a3
+	mac.w %d6u,%d1l,10(%a6),%d2
+	mac.w %d6u,%d1l,10(%a6),%a7
+	mac.w %d6u,%d1l,10(%a6)&,%d1
+	mac.w %d6u,%d1l,10(%a6)&,%a3
+	mac.w %d6u,%d1l,10(%a6)&,%d2
+	mac.w %d6u,%d1l,10(%a6)&,%a7
+	mac.w %d6u,%d1l,-(%a1),%d1
+	mac.w %d6u,%d1l,-(%a1),%a3
+	mac.w %d6u,%d1l,-(%a1),%d2
+	mac.w %d6u,%d1l,-(%a1),%a7
+	mac.w %d6u,%d1l,-(%a1)&,%d1
+	mac.w %d6u,%d1l,-(%a1)&,%a3
+	mac.w %d6u,%d1l,-(%a1)&,%d2
+	mac.w %d6u,%d1l,-(%a1)&,%a7
+	mac.w %d6u,%d1l,<<,(%a3),%d1
+	mac.w %d6u,%d1l,<<,(%a3),%a3
+	mac.w %d6u,%d1l,<<,(%a3),%d2
+	mac.w %d6u,%d1l,<<,(%a3),%a7
+	mac.w %d6u,%d1l,<<,(%a3)&,%d1
+	mac.w %d6u,%d1l,<<,(%a3)&,%a3
+	mac.w %d6u,%d1l,<<,(%a3)&,%d2
+	mac.w %d6u,%d1l,<<,(%a3)&,%a7
+	mac.w %d6u,%d1l,<<,(%a2)+,%d1
+	mac.w %d6u,%d1l,<<,(%a2)+,%a3
+	mac.w %d6u,%d1l,<<,(%a2)+,%d2
+	mac.w %d6u,%d1l,<<,(%a2)+,%a7
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d1
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a3
+	mac.w %d6u,%d1l,<<,(%a2)+&,%d2
+	mac.w %d6u,%d1l,<<,(%a2)+&,%a7
+	mac.w %d6u,%d1l,<<,10(%a6),%d1
+	mac.w %d6u,%d1l,<<,10(%a6),%a3
+	mac.w %d6u,%d1l,<<,10(%a6),%d2
+	mac.w %d6u,%d1l,<<,10(%a6),%a7
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d1
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a3
+	mac.w %d6u,%d1l,<<,10(%a6)&,%d2
+	mac.w %d6u,%d1l,<<,10(%a6)&,%a7
+	mac.w %d6u,%d1l,<<,-(%a1),%d1
+	mac.w %d6u,%d1l,<<,-(%a1),%a3
+	mac.w %d6u,%d1l,<<,-(%a1),%d2
+	mac.w %d6u,%d1l,<<,-(%a1),%a7
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d1
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a3
+	mac.w %d6u,%d1l,<<,-(%a1)&,%d2
+	mac.w %d6u,%d1l,<<,-(%a1)&,%a7
+	mac.w %d6u,%d1l,>>,(%a3),%d1
+	mac.w %d6u,%d1l,>>,(%a3),%a3
+	mac.w %d6u,%d1l,>>,(%a3),%d2
+	mac.w %d6u,%d1l,>>,(%a3),%a7
+	mac.w %d6u,%d1l,>>,(%a3)&,%d1
+	mac.w %d6u,%d1l,>>,(%a3)&,%a3
+	mac.w %d6u,%d1l,>>,(%a3)&,%d2
+	mac.w %d6u,%d1l,>>,(%a3)&,%a7
+	mac.w %d6u,%d1l,>>,(%a2)+,%d1
+	mac.w %d6u,%d1l,>>,(%a2)+,%a3
+	mac.w %d6u,%d1l,>>,(%a2)+,%d2
+	mac.w %d6u,%d1l,>>,(%a2)+,%a7
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d1
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a3
+	mac.w %d6u,%d1l,>>,(%a2)+&,%d2
+	mac.w %d6u,%d1l,>>,(%a2)+&,%a7
+	mac.w %d6u,%d1l,>>,10(%a6),%d1
+	mac.w %d6u,%d1l,>>,10(%a6),%a3
+	mac.w %d6u,%d1l,>>,10(%a6),%d2
+	mac.w %d6u,%d1l,>>,10(%a6),%a7
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d1
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a3
+	mac.w %d6u,%d1l,>>,10(%a6)&,%d2
+	mac.w %d6u,%d1l,>>,10(%a6)&,%a7
+	mac.w %d6u,%d1l,>>,-(%a1),%d1
+	mac.w %d6u,%d1l,>>,-(%a1),%a3
+	mac.w %d6u,%d1l,>>,-(%a1),%d2
+	mac.w %d6u,%d1l,>>,-(%a1),%a7
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d1
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a3
+	mac.w %d6u,%d1l,>>,-(%a1)&,%d2
+	mac.w %d6u,%d1l,>>,-(%a1)&,%a7
+	mac.w %d6u,%d1l,#1,(%a3),%d1
+	mac.w %d6u,%d1l,#1,(%a3),%a3
+	mac.w %d6u,%d1l,#1,(%a3),%d2
+	mac.w %d6u,%d1l,#1,(%a3),%a7
+	mac.w %d6u,%d1l,#1,(%a3)&,%d1
+	mac.w %d6u,%d1l,#1,(%a3)&,%a3
+	mac.w %d6u,%d1l,#1,(%a3)&,%d2
+	mac.w %d6u,%d1l,#1,(%a3)&,%a7
+	mac.w %d6u,%d1l,#1,(%a2)+,%d1
+	mac.w %d6u,%d1l,#1,(%a2)+,%a3
+	mac.w %d6u,%d1l,#1,(%a2)+,%d2
+	mac.w %d6u,%d1l,#1,(%a2)+,%a7
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d1
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a3
+	mac.w %d6u,%d1l,#1,(%a2)+&,%d2
+	mac.w %d6u,%d1l,#1,(%a2)+&,%a7
+	mac.w %d6u,%d1l,#1,10(%a6),%d1
+	mac.w %d6u,%d1l,#1,10(%a6),%a3
+	mac.w %d6u,%d1l,#1,10(%a6),%d2
+	mac.w %d6u,%d1l,#1,10(%a6),%a7
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d1
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a3
+	mac.w %d6u,%d1l,#1,10(%a6)&,%d2
+	mac.w %d6u,%d1l,#1,10(%a6)&,%a7
+	mac.w %d6u,%d1l,#1,-(%a1),%d1
+	mac.w %d6u,%d1l,#1,-(%a1),%a3
+	mac.w %d6u,%d1l,#1,-(%a1),%d2
+	mac.w %d6u,%d1l,#1,-(%a1),%a7
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d1
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a3
+	mac.w %d6u,%d1l,#1,-(%a1)&,%d2
+	mac.w %d6u,%d1l,#1,-(%a1)&,%a7
+	mac.w %d6u,%d1l,#-1,(%a3),%d1
+	mac.w %d6u,%d1l,#-1,(%a3),%a3
+	mac.w %d6u,%d1l,#-1,(%a3),%d2
+	mac.w %d6u,%d1l,#-1,(%a3),%a7
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d1
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a3
+	mac.w %d6u,%d1l,#-1,(%a3)&,%d2
+	mac.w %d6u,%d1l,#-1,(%a3)&,%a7
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d1
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a3
+	mac.w %d6u,%d1l,#-1,(%a2)+,%d2
+	mac.w %d6u,%d1l,#-1,(%a2)+,%a7
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d1
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a3
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%d2
+	mac.w %d6u,%d1l,#-1,(%a2)+&,%a7
+	mac.w %d6u,%d1l,#-1,10(%a6),%d1
+	mac.w %d6u,%d1l,#-1,10(%a6),%a3
+	mac.w %d6u,%d1l,#-1,10(%a6),%d2
+	mac.w %d6u,%d1l,#-1,10(%a6),%a7
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d1
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a3
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%d2
+	mac.w %d6u,%d1l,#-1,10(%a6)&,%a7
+	mac.w %d6u,%d1l,#-1,-(%a1),%d1
+	mac.w %d6u,%d1l,#-1,-(%a1),%a3
+	mac.w %d6u,%d1l,#-1,-(%a1),%d2
+	mac.w %d6u,%d1l,#-1,-(%a1),%a7
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d1
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a3
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%d2
+	mac.w %d6u,%d1l,#-1,-(%a1)&,%a7
+
+	mac.l %a1,%a3
+	mac.l %a1,%a3,<<
+	mac.l %a1,%a3,>>
+	mac.l %a1,%a3,#1
+	mac.l %a1,%a3,#-1
+	mac.l %a1,%d4
+	mac.l %a1,%d4,<<
+	mac.l %a1,%d4,>>
+	mac.l %a1,%d4,#1
+	mac.l %a1,%d4,#-1
+	mac.l %d6,%a3
+	mac.l %d6,%a3,<<
+	mac.l %d6,%a3,>>
+	mac.l %d6,%a3,#1
+	mac.l %d6,%a3,#-1
+	mac.l %d6,%d4
+	mac.l %d6,%d4,<<
+	mac.l %d6,%d4,>>
+	mac.l %d6,%d4,#1
+	mac.l %d6,%d4,#-1
+
+	mac.l %a1,%a3,(%a3),%d1
+	mac.l %a1,%a3,(%a3),%a3
+	mac.l %a1,%a3,(%a3),%d2
+	mac.l %a1,%a3,(%a3),%a7
+	mac.l %a1,%a3,(%a3)&,%d1
+	mac.l %a1,%a3,(%a3)&,%a3
+	mac.l %a1,%a3,(%a3)&,%d2
+	mac.l %a1,%a3,(%a3)&,%a7
+	mac.l %a1,%a3,(%a2)+,%d1
+	mac.l %a1,%a3,(%a2)+,%a3
+	mac.l %a1,%a3,(%a2)+,%d2
+	mac.l %a1,%a3,(%a2)+,%a7
+	mac.l %a1,%a3,(%a2)+&,%d1
+	mac.l %a1,%a3,(%a2)+&,%a3
+	mac.l %a1,%a3,(%a2)+&,%d2
+	mac.l %a1,%a3,(%a2)+&,%a7
+	mac.l %a1,%a3,10(%a6),%d1
+	mac.l %a1,%a3,10(%a6),%a3
+	mac.l %a1,%a3,10(%a6),%d2
+	mac.l %a1,%a3,10(%a6),%a7
+	mac.l %a1,%a3,10(%a6)&,%d1
+	mac.l %a1,%a3,10(%a6)&,%a3
+	mac.l %a1,%a3,10(%a6)&,%d2
+	mac.l %a1,%a3,10(%a6)&,%a7
+	mac.l %a1,%a3,-(%a1),%d1
+	mac.l %a1,%a3,-(%a1),%a3
+	mac.l %a1,%a3,-(%a1),%d2
+	mac.l %a1,%a3,-(%a1),%a7
+	mac.l %a1,%a3,-(%a1)&,%d1
+	mac.l %a1,%a3,-(%a1)&,%a3
+	mac.l %a1,%a3,-(%a1)&,%d2
+	mac.l %a1,%a3,-(%a1)&,%a7
+	mac.l %a1,%a3,<<,(%a3),%d1
+	mac.l %a1,%a3,<<,(%a3),%a3
+	mac.l %a1,%a3,<<,(%a3),%d2
+	mac.l %a1,%a3,<<,(%a3),%a7
+	mac.l %a1,%a3,<<,(%a3)&,%d1
+	mac.l %a1,%a3,<<,(%a3)&,%a3
+	mac.l %a1,%a3,<<,(%a3)&,%d2
+	mac.l %a1,%a3,<<,(%a3)&,%a7
+	mac.l %a1,%a3,<<,(%a2)+,%d1
+	mac.l %a1,%a3,<<,(%a2)+,%a3
+	mac.l %a1,%a3,<<,(%a2)+,%d2
+	mac.l %a1,%a3,<<,(%a2)+,%a7
+	mac.l %a1,%a3,<<,(%a2)+&,%d1
+	mac.l %a1,%a3,<<,(%a2)+&,%a3
+	mac.l %a1,%a3,<<,(%a2)+&,%d2
+	mac.l %a1,%a3,<<,(%a2)+&,%a7
+	mac.l %a1,%a3,<<,10(%a6),%d1
+	mac.l %a1,%a3,<<,10(%a6),%a3
+	mac.l %a1,%a3,<<,10(%a6),%d2
+	mac.l %a1,%a3,<<,10(%a6),%a7
+	mac.l %a1,%a3,<<,10(%a6)&,%d1
+	mac.l %a1,%a3,<<,10(%a6)&,%a3
+	mac.l %a1,%a3,<<,10(%a6)&,%d2
+	mac.l %a1,%a3,<<,10(%a6)&,%a7
+	mac.l %a1,%a3,<<,-(%a1),%d1
+	mac.l %a1,%a3,<<,-(%a1),%a3
+	mac.l %a1,%a3,<<,-(%a1),%d2
+	mac.l %a1,%a3,<<,-(%a1),%a7
+	mac.l %a1,%a3,<<,-(%a1)&,%d1
+	mac.l %a1,%a3,<<,-(%a1)&,%a3
+	mac.l %a1,%a3,<<,-(%a1)&,%d2
+	mac.l %a1,%a3,<<,-(%a1)&,%a7
+	mac.l %a1,%a3,>>,(%a3),%d1
+	mac.l %a1,%a3,>>,(%a3),%a3
+	mac.l %a1,%a3,>>,(%a3),%d2
+	mac.l %a1,%a3,>>,(%a3),%a7
+	mac.l %a1,%a3,>>,(%a3)&,%d1
+	mac.l %a1,%a3,>>,(%a3)&,%a3
+	mac.l %a1,%a3,>>,(%a3)&,%d2
+	mac.l %a1,%a3,>>,(%a3)&,%a7
+	mac.l %a1,%a3,>>,(%a2)+,%d1
+	mac.l %a1,%a3,>>,(%a2)+,%a3
+	mac.l %a1,%a3,>>,(%a2)+,%d2
+	mac.l %a1,%a3,>>,(%a2)+,%a7
+	mac.l %a1,%a3,>>,(%a2)+&,%d1
+	mac.l %a1,%a3,>>,(%a2)+&,%a3
+	mac.l %a1,%a3,>>,(%a2)+&,%d2
+	mac.l %a1,%a3,>>,(%a2)+&,%a7
+	mac.l %a1,%a3,>>,10(%a6),%d1
+	mac.l %a1,%a3,>>,10(%a6),%a3
+	mac.l %a1,%a3,>>,10(%a6),%d2
+	mac.l %a1,%a3,>>,10(%a6),%a7
+	mac.l %a1,%a3,>>,10(%a6)&,%d1
+	mac.l %a1,%a3,>>,10(%a6)&,%a3
+	mac.l %a1,%a3,>>,10(%a6)&,%d2
+	mac.l %a1,%a3,>>,10(%a6)&,%a7
+	mac.l %a1,%a3,>>,-(%a1),%d1
+	mac.l %a1,%a3,>>,-(%a1),%a3
+	mac.l %a1,%a3,>>,-(%a1),%d2
+	mac.l %a1,%a3,>>,-(%a1),%a7
+	mac.l %a1,%a3,>>,-(%a1)&,%d1
+	mac.l %a1,%a3,>>,-(%a1)&,%a3
+	mac.l %a1,%a3,>>,-(%a1)&,%d2
+	mac.l %a1,%a3,>>,-(%a1)&,%a7
+	mac.l %a1,%a3,#1,(%a3),%d1
+	mac.l %a1,%a3,#1,(%a3),%a3
+	mac.l %a1,%a3,#1,(%a3),%d2
+	mac.l %a1,%a3,#1,(%a3),%a7
+	mac.l %a1,%a3,#1,(%a3)&,%d1
+	mac.l %a1,%a3,#1,(%a3)&,%a3
+	mac.l %a1,%a3,#1,(%a3)&,%d2
+	mac.l %a1,%a3,#1,(%a3)&,%a7
+	mac.l %a1,%a3,#1,(%a2)+,%d1
+	mac.l %a1,%a3,#1,(%a2)+,%a3
+	mac.l %a1,%a3,#1,(%a2)+,%d2
+	mac.l %a1,%a3,#1,(%a2)+,%a7
+	mac.l %a1,%a3,#1,(%a2)+&,%d1
+	mac.l %a1,%a3,#1,(%a2)+&,%a3
+	mac.l %a1,%a3,#1,(%a2)+&,%d2
+	mac.l %a1,%a3,#1,(%a2)+&,%a7
+	mac.l %a1,%a3,#1,10(%a6),%d1
+	mac.l %a1,%a3,#1,10(%a6),%a3
+	mac.l %a1,%a3,#1,10(%a6),%d2
+	mac.l %a1,%a3,#1,10(%a6),%a7
+	mac.l %a1,%a3,#1,10(%a6)&,%d1
+	mac.l %a1,%a3,#1,10(%a6)&,%a3
+	mac.l %a1,%a3,#1,10(%a6)&,%d2
+	mac.l %a1,%a3,#1,10(%a6)&,%a7
+	mac.l %a1,%a3,#1,-(%a1),%d1
+	mac.l %a1,%a3,#1,-(%a1),%a3
+	mac.l %a1,%a3,#1,-(%a1),%d2
+	mac.l %a1,%a3,#1,-(%a1),%a7
+	mac.l %a1,%a3,#1,-(%a1)&,%d1
+	mac.l %a1,%a3,#1,-(%a1)&,%a3
+	mac.l %a1,%a3,#1,-(%a1)&,%d2
+	mac.l %a1,%a3,#1,-(%a1)&,%a7
+	mac.l %a1,%a3,#-1,(%a3),%d1
+	mac.l %a1,%a3,#-1,(%a3),%a3
+	mac.l %a1,%a3,#-1,(%a3),%d2
+	mac.l %a1,%a3,#-1,(%a3),%a7
+	mac.l %a1,%a3,#-1,(%a3)&,%d1
+	mac.l %a1,%a3,#-1,(%a3)&,%a3
+	mac.l %a1,%a3,#-1,(%a3)&,%d2
+	mac.l %a1,%a3,#-1,(%a3)&,%a7
+	mac.l %a1,%a3,#-1,(%a2)+,%d1
+	mac.l %a1,%a3,#-1,(%a2)+,%a3
+	mac.l %a1,%a3,#-1,(%a2)+,%d2
+	mac.l %a1,%a3,#-1,(%a2)+,%a7
+	mac.l %a1,%a3,#-1,(%a2)+&,%d1
+	mac.l %a1,%a3,#-1,(%a2)+&,%a3
+	mac.l %a1,%a3,#-1,(%a2)+&,%d2
+	mac.l %a1,%a3,#-1,(%a2)+&,%a7
+	mac.l %a1,%a3,#-1,10(%a6),%d1
+	mac.l %a1,%a3,#-1,10(%a6),%a3
+	mac.l %a1,%a3,#-1,10(%a6),%d2
+	mac.l %a1,%a3,#-1,10(%a6),%a7
+	mac.l %a1,%a3,#-1,10(%a6)&,%d1
+	mac.l %a1,%a3,#-1,10(%a6)&,%a3
+	mac.l %a1,%a3,#-1,10(%a6)&,%d2
+	mac.l %a1,%a3,#-1,10(%a6)&,%a7
+	mac.l %a1,%a3,#-1,-(%a1),%d1
+	mac.l %a1,%a3,#-1,-(%a1),%a3
+	mac.l %a1,%a3,#-1,-(%a1),%d2
+	mac.l %a1,%a3,#-1,-(%a1),%a7
+	mac.l %a1,%a3,#-1,-(%a1)&,%d1
+	mac.l %a1,%a3,#-1,-(%a1)&,%a3
+	mac.l %a1,%a3,#-1,-(%a1)&,%d2
+	mac.l %a1,%a3,#-1,-(%a1)&,%a7
+	mac.l %a1,%d4,(%a3),%d1
+	mac.l %a1,%d4,(%a3),%a3
+	mac.l %a1,%d4,(%a3),%d2
+	mac.l %a1,%d4,(%a3),%a7
+	mac.l %a1,%d4,(%a3)&,%d1
+	mac.l %a1,%d4,(%a3)&,%a3
+	mac.l %a1,%d4,(%a3)&,%d2
+	mac.l %a1,%d4,(%a3)&,%a7
+	mac.l %a1,%d4,(%a2)+,%d1
+	mac.l %a1,%d4,(%a2)+,%a3
+	mac.l %a1,%d4,(%a2)+,%d2
+	mac.l %a1,%d4,(%a2)+,%a7
+	mac.l %a1,%d4,(%a2)+&,%d1
+	mac.l %a1,%d4,(%a2)+&,%a3
+	mac.l %a1,%d4,(%a2)+&,%d2
+	mac.l %a1,%d4,(%a2)+&,%a7
+	mac.l %a1,%d4,10(%a6),%d1
+	mac.l %a1,%d4,10(%a6),%a3
+	mac.l %a1,%d4,10(%a6),%d2
+	mac.l %a1,%d4,10(%a6),%a7
+	mac.l %a1,%d4,10(%a6)&,%d1
+	mac.l %a1,%d4,10(%a6)&,%a3
+	mac.l %a1,%d4,10(%a6)&,%d2
+	mac.l %a1,%d4,10(%a6)&,%a7
+	mac.l %a1,%d4,-(%a1),%d1
+	mac.l %a1,%d4,-(%a1),%a3
+	mac.l %a1,%d4,-(%a1),%d2
+	mac.l %a1,%d4,-(%a1),%a7
+	mac.l %a1,%d4,-(%a1)&,%d1
+	mac.l %a1,%d4,-(%a1)&,%a3
+	mac.l %a1,%d4,-(%a1)&,%d2
+	mac.l %a1,%d4,-(%a1)&,%a7
+	mac.l %a1,%d4,<<,(%a3),%d1
+	mac.l %a1,%d4,<<,(%a3),%a3
+	mac.l %a1,%d4,<<,(%a3),%d2
+	mac.l %a1,%d4,<<,(%a3),%a7
+	mac.l %a1,%d4,<<,(%a3)&,%d1
+	mac.l %a1,%d4,<<,(%a3)&,%a3
+	mac.l %a1,%d4,<<,(%a3)&,%d2
+	mac.l %a1,%d4,<<,(%a3)&,%a7
+	mac.l %a1,%d4,<<,(%a2)+,%d1
+	mac.l %a1,%d4,<<,(%a2)+,%a3
+	mac.l %a1,%d4,<<,(%a2)+,%d2
+	mac.l %a1,%d4,<<,(%a2)+,%a7
+	mac.l %a1,%d4,<<,(%a2)+&,%d1
+	mac.l %a1,%d4,<<,(%a2)+&,%a3
+	mac.l %a1,%d4,<<,(%a2)+&,%d2
+	mac.l %a1,%d4,<<,(%a2)+&,%a7
+	mac.l %a1,%d4,<<,10(%a6),%d1
+	mac.l %a1,%d4,<<,10(%a6),%a3
+	mac.l %a1,%d4,<<,10(%a6),%d2
+	mac.l %a1,%d4,<<,10(%a6),%a7
+	mac.l %a1,%d4,<<,10(%a6)&,%d1
+	mac.l %a1,%d4,<<,10(%a6)&,%a3
+	mac.l %a1,%d4,<<,10(%a6)&,%d2
+	mac.l %a1,%d4,<<,10(%a6)&,%a7
+	mac.l %a1,%d4,<<,-(%a1),%d1
+	mac.l %a1,%d4,<<,-(%a1),%a3
+	mac.l %a1,%d4,<<,-(%a1),%d2
+	mac.l %a1,%d4,<<,-(%a1),%a7
+	mac.l %a1,%d4,<<,-(%a1)&,%d1
+	mac.l %a1,%d4,<<,-(%a1)&,%a3
+	mac.l %a1,%d4,<<,-(%a1)&,%d2
+	mac.l %a1,%d4,<<,-(%a1)&,%a7
+	mac.l %a1,%d4,>>,(%a3),%d1
+	mac.l %a1,%d4,>>,(%a3),%a3
+	mac.l %a1,%d4,>>,(%a3),%d2
+	mac.l %a1,%d4,>>,(%a3),%a7
+	mac.l %a1,%d4,>>,(%a3)&,%d1
+	mac.l %a1,%d4,>>,(%a3)&,%a3
+	mac.l %a1,%d4,>>,(%a3)&,%d2
+	mac.l %a1,%d4,>>,(%a3)&,%a7
+	mac.l %a1,%d4,>>,(%a2)+,%d1
+	mac.l %a1,%d4,>>,(%a2)+,%a3
+	mac.l %a1,%d4,>>,(%a2)+,%d2
+	mac.l %a1,%d4,>>,(%a2)+,%a7
+	mac.l %a1,%d4,>>,(%a2)+&,%d1
+	mac.l %a1,%d4,>>,(%a2)+&,%a3
+	mac.l %a1,%d4,>>,(%a2)+&,%d2
+	mac.l %a1,%d4,>>,(%a2)+&,%a7
+	mac.l %a1,%d4,>>,10(%a6),%d1
+	mac.l %a1,%d4,>>,10(%a6),%a3
+	mac.l %a1,%d4,>>,10(%a6),%d2
+	mac.l %a1,%d4,>>,10(%a6),%a7
+	mac.l %a1,%d4,>>,10(%a6)&,%d1
+	mac.l %a1,%d4,>>,10(%a6)&,%a3
+	mac.l %a1,%d4,>>,10(%a6)&,%d2
+	mac.l %a1,%d4,>>,10(%a6)&,%a7
+	mac.l %a1,%d4,>>,-(%a1),%d1
+	mac.l %a1,%d4,>>,-(%a1),%a3
+	mac.l %a1,%d4,>>,-(%a1),%d2
+	mac.l %a1,%d4,>>,-(%a1),%a7
+	mac.l %a1,%d4,>>,-(%a1)&,%d1
+	mac.l %a1,%d4,>>,-(%a1)&,%a3
+	mac.l %a1,%d4,>>,-(%a1)&,%d2
+	mac.l %a1,%d4,>>,-(%a1)&,%a7
+	mac.l %a1,%d4,#1,(%a3),%d1
+	mac.l %a1,%d4,#1,(%a3),%a3
+	mac.l %a1,%d4,#1,(%a3),%d2
+	mac.l %a1,%d4,#1,(%a3),%a7
+	mac.l %a1,%d4,#1,(%a3)&,%d1
+	mac.l %a1,%d4,#1,(%a3)&,%a3
+	mac.l %a1,%d4,#1,(%a3)&,%d2
+	mac.l %a1,%d4,#1,(%a3)&,%a7
+	mac.l %a1,%d4,#1,(%a2)+,%d1
+	mac.l %a1,%d4,#1,(%a2)+,%a3
+	mac.l %a1,%d4,#1,(%a2)+,%d2
+	mac.l %a1,%d4,#1,(%a2)+,%a7
+	mac.l %a1,%d4,#1,(%a2)+&,%d1
+	mac.l %a1,%d4,#1,(%a2)+&,%a3
+	mac.l %a1,%d4,#1,(%a2)+&,%d2
+	mac.l %a1,%d4,#1,(%a2)+&,%a7
+	mac.l %a1,%d4,#1,10(%a6),%d1
+	mac.l %a1,%d4,#1,10(%a6),%a3
+	mac.l %a1,%d4,#1,10(%a6),%d2
+	mac.l %a1,%d4,#1,10(%a6),%a7
+	mac.l %a1,%d4,#1,10(%a6)&,%d1
+	mac.l %a1,%d4,#1,10(%a6)&,%a3
+	mac.l %a1,%d4,#1,10(%a6)&,%d2
+	mac.l %a1,%d4,#1,10(%a6)&,%a7
+	mac.l %a1,%d4,#1,-(%a1),%d1
+	mac.l %a1,%d4,#1,-(%a1),%a3
+	mac.l %a1,%d4,#1,-(%a1),%d2
+	mac.l %a1,%d4,#1,-(%a1),%a7
+	mac.l %a1,%d4,#1,-(%a1)&,%d1
+	mac.l %a1,%d4,#1,-(%a1)&,%a3
+	mac.l %a1,%d4,#1,-(%a1)&,%d2
+	mac.l %a1,%d4,#1,-(%a1)&,%a7
+	mac.l %a1,%d4,#-1,(%a3),%d1
+	mac.l %a1,%d4,#-1,(%a3),%a3
+	mac.l %a1,%d4,#-1,(%a3),%d2
+	mac.l %a1,%d4,#-1,(%a3),%a7
+	mac.l %a1,%d4,#-1,(%a3)&,%d1
+	mac.l %a1,%d4,#-1,(%a3)&,%a3
+	mac.l %a1,%d4,#-1,(%a3)&,%d2
+	mac.l %a1,%d4,#-1,(%a3)&,%a7
+	mac.l %a1,%d4,#-1,(%a2)+,%d1
+	mac.l %a1,%d4,#-1,(%a2)+,%a3
+	mac.l %a1,%d4,#-1,(%a2)+,%d2
+	mac.l %a1,%d4,#-1,(%a2)+,%a7
+	mac.l %a1,%d4,#-1,(%a2)+&,%d1
+	mac.l %a1,%d4,#-1,(%a2)+&,%a3
+	mac.l %a1,%d4,#-1,(%a2)+&,%d2
+	mac.l %a1,%d4,#-1,(%a2)+&,%a7
+	mac.l %a1,%d4,#-1,10(%a6),%d1
+	mac.l %a1,%d4,#-1,10(%a6),%a3
+	mac.l %a1,%d4,#-1,10(%a6),%d2
+	mac.l %a1,%d4,#-1,10(%a6),%a7
+	mac.l %a1,%d4,#-1,10(%a6)&,%d1
+	mac.l %a1,%d4,#-1,10(%a6)&,%a3
+	mac.l %a1,%d4,#-1,10(%a6)&,%d2
+	mac.l %a1,%d4,#-1,10(%a6)&,%a7
+	mac.l %a1,%d4,#-1,-(%a1),%d1
+	mac.l %a1,%d4,#-1,-(%a1),%a3
+	mac.l %a1,%d4,#-1,-(%a1),%d2
+	mac.l %a1,%d4,#-1,-(%a1),%a7
+	mac.l %a1,%d4,#-1,-(%a1)&,%d1
+	mac.l %a1,%d4,#-1,-(%a1)&,%a3
+	mac.l %a1,%d4,#-1,-(%a1)&,%d2
+	mac.l %a1,%d4,#-1,-(%a1)&,%a7
+	mac.l %d6,%a3,(%a3),%d1
+	mac.l %d6,%a3,(%a3),%a3
+	mac.l %d6,%a3,(%a3),%d2
+	mac.l %d6,%a3,(%a3),%a7
+	mac.l %d6,%a3,(%a3)&,%d1
+	mac.l %d6,%a3,(%a3)&,%a3
+	mac.l %d6,%a3,(%a3)&,%d2
+	mac.l %d6,%a3,(%a3)&,%a7
+	mac.l %d6,%a3,(%a2)+,%d1
+	mac.l %d6,%a3,(%a2)+,%a3
+	mac.l %d6,%a3,(%a2)+,%d2
+	mac.l %d6,%a3,(%a2)+,%a7
+	mac.l %d6,%a3,(%a2)+&,%d1
+	mac.l %d6,%a3,(%a2)+&,%a3
+	mac.l %d6,%a3,(%a2)+&,%d2
+	mac.l %d6,%a3,(%a2)+&,%a7
+	mac.l %d6,%a3,10(%a6),%d1
+	mac.l %d6,%a3,10(%a6),%a3
+	mac.l %d6,%a3,10(%a6),%d2
+	mac.l %d6,%a3,10(%a6),%a7
+	mac.l %d6,%a3,10(%a6)&,%d1
+	mac.l %d6,%a3,10(%a6)&,%a3
+	mac.l %d6,%a3,10(%a6)&,%d2
+	mac.l %d6,%a3,10(%a6)&,%a7
+	mac.l %d6,%a3,-(%a1),%d1
+	mac.l %d6,%a3,-(%a1),%a3
+	mac.l %d6,%a3,-(%a1),%d2
+	mac.l %d6,%a3,-(%a1),%a7
+	mac.l %d6,%a3,-(%a1)&,%d1
+	mac.l %d6,%a3,-(%a1)&,%a3
+	mac.l %d6,%a3,-(%a1)&,%d2
+	mac.l %d6,%a3,-(%a1)&,%a7
+	mac.l %d6,%a3,<<,(%a3),%d1
+	mac.l %d6,%a3,<<,(%a3),%a3
+	mac.l %d6,%a3,<<,(%a3),%d2
+	mac.l %d6,%a3,<<,(%a3),%a7
+	mac.l %d6,%a3,<<,(%a3)&,%d1
+	mac.l %d6,%a3,<<,(%a3)&,%a3
+	mac.l %d6,%a3,<<,(%a3)&,%d2
+	mac.l %d6,%a3,<<,(%a3)&,%a7
+	mac.l %d6,%a3,<<,(%a2)+,%d1
+	mac.l %d6,%a3,<<,(%a2)+,%a3
+	mac.l %d6,%a3,<<,(%a2)+,%d2
+	mac.l %d6,%a3,<<,(%a2)+,%a7
+	mac.l %d6,%a3,<<,(%a2)+&,%d1
+	mac.l %d6,%a3,<<,(%a2)+&,%a3
+	mac.l %d6,%a3,<<,(%a2)+&,%d2
+	mac.l %d6,%a3,<<,(%a2)+&,%a7
+	mac.l %d6,%a3,<<,10(%a6),%d1
+	mac.l %d6,%a3,<<,10(%a6),%a3
+	mac.l %d6,%a3,<<,10(%a6),%d2
+	mac.l %d6,%a3,<<,10(%a6),%a7
+	mac.l %d6,%a3,<<,10(%a6)&,%d1
+	mac.l %d6,%a3,<<,10(%a6)&,%a3
+	mac.l %d6,%a3,<<,10(%a6)&,%d2
+	mac.l %d6,%a3,<<,10(%a6)&,%a7
+	mac.l %d6,%a3,<<,-(%a1),%d1
+	mac.l %d6,%a3,<<,-(%a1),%a3
+	mac.l %d6,%a3,<<,-(%a1),%d2
+	mac.l %d6,%a3,<<,-(%a1),%a7
+	mac.l %d6,%a3,<<,-(%a1)&,%d1
+	mac.l %d6,%a3,<<,-(%a1)&,%a3
+	mac.l %d6,%a3,<<,-(%a1)&,%d2
+	mac.l %d6,%a3,<<,-(%a1)&,%a7
+	mac.l %d6,%a3,>>,(%a3),%d1
+	mac.l %d6,%a3,>>,(%a3),%a3
+	mac.l %d6,%a3,>>,(%a3),%d2
+	mac.l %d6,%a3,>>,(%a3),%a7
+	mac.l %d6,%a3,>>,(%a3)&,%d1
+	mac.l %d6,%a3,>>,(%a3)&,%a3
+	mac.l %d6,%a3,>>,(%a3)&,%d2
+	mac.l %d6,%a3,>>,(%a3)&,%a7
+	mac.l %d6,%a3,>>,(%a2)+,%d1
+	mac.l %d6,%a3,>>,(%a2)+,%a3
+	mac.l %d6,%a3,>>,(%a2)+,%d2
+	mac.l %d6,%a3,>>,(%a2)+,%a7
+	mac.l %d6,%a3,>>,(%a2)+&,%d1
+	mac.l %d6,%a3,>>,(%a2)+&,%a3
+	mac.l %d6,%a3,>>,(%a2)+&,%d2
+	mac.l %d6,%a3,>>,(%a2)+&,%a7
+	mac.l %d6,%a3,>>,10(%a6),%d1
+	mac.l %d6,%a3,>>,10(%a6),%a3
+	mac.l %d6,%a3,>>,10(%a6),%d2
+	mac.l %d6,%a3,>>,10(%a6),%a7
+	mac.l %d6,%a3,>>,10(%a6)&,%d1
+	mac.l %d6,%a3,>>,10(%a6)&,%a3
+	mac.l %d6,%a3,>>,10(%a6)&,%d2
+	mac.l %d6,%a3,>>,10(%a6)&,%a7
+	mac.l %d6,%a3,>>,-(%a1),%d1
+	mac.l %d6,%a3,>>,-(%a1),%a3
+	mac.l %d6,%a3,>>,-(%a1),%d2
+	mac.l %d6,%a3,>>,-(%a1),%a7
+	mac.l %d6,%a3,>>,-(%a1)&,%d1
+	mac.l %d6,%a3,>>,-(%a1)&,%a3
+	mac.l %d6,%a3,>>,-(%a1)&,%d2
+	mac.l %d6,%a3,>>,-(%a1)&,%a7
+	mac.l %d6,%a3,#1,(%a3),%d1
+	mac.l %d6,%a3,#1,(%a3),%a3
+	mac.l %d6,%a3,#1,(%a3),%d2
+	mac.l %d6,%a3,#1,(%a3),%a7
+	mac.l %d6,%a3,#1,(%a3)&,%d1
+	mac.l %d6,%a3,#1,(%a3)&,%a3
+	mac.l %d6,%a3,#1,(%a3)&,%d2
+	mac.l %d6,%a3,#1,(%a3)&,%a7
+	mac.l %d6,%a3,#1,(%a2)+,%d1
+	mac.l %d6,%a3,#1,(%a2)+,%a3
+	mac.l %d6,%a3,#1,(%a2)+,%d2
+	mac.l %d6,%a3,#1,(%a2)+,%a7
+	mac.l %d6,%a3,#1,(%a2)+&,%d1
+	mac.l %d6,%a3,#1,(%a2)+&,%a3
+	mac.l %d6,%a3,#1,(%a2)+&,%d2
+	mac.l %d6,%a3,#1,(%a2)+&,%a7
+	mac.l %d6,%a3,#1,10(%a6),%d1
+	mac.l %d6,%a3,#1,10(%a6),%a3
+	mac.l %d6,%a3,#1,10(%a6),%d2
+	mac.l %d6,%a3,#1,10(%a6),%a7
+	mac.l %d6,%a3,#1,10(%a6)&,%d1
+	mac.l %d6,%a3,#1,10(%a6)&,%a3
+	mac.l %d6,%a3,#1,10(%a6)&,%d2
+	mac.l %d6,%a3,#1,10(%a6)&,%a7
+	mac.l %d6,%a3,#1,-(%a1),%d1
+	mac.l %d6,%a3,#1,-(%a1),%a3
+	mac.l %d6,%a3,#1,-(%a1),%d2
+	mac.l %d6,%a3,#1,-(%a1),%a7
+	mac.l %d6,%a3,#1,-(%a1)&,%d1
+	mac.l %d6,%a3,#1,-(%a1)&,%a3
+	mac.l %d6,%a3,#1,-(%a1)&,%d2
+	mac.l %d6,%a3,#1,-(%a1)&,%a7
+	mac.l %d6,%a3,#-1,(%a3),%d1
+	mac.l %d6,%a3,#-1,(%a3),%a3
+	mac.l %d6,%a3,#-1,(%a3),%d2
+	mac.l %d6,%a3,#-1,(%a3),%a7
+	mac.l %d6,%a3,#-1,(%a3)&,%d1
+	mac.l %d6,%a3,#-1,(%a3)&,%a3
+	mac.l %d6,%a3,#-1,(%a3)&,%d2
+	mac.l %d6,%a3,#-1,(%a3)&,%a7
+	mac.l %d6,%a3,#-1,(%a2)+,%d1
+	mac.l %d6,%a3,#-1,(%a2)+,%a3
+	mac.l %d6,%a3,#-1,(%a2)+,%d2
+	mac.l %d6,%a3,#-1,(%a2)+,%a7
+	mac.l %d6,%a3,#-1,(%a2)+&,%d1
+	mac.l %d6,%a3,#-1,(%a2)+&,%a3
+	mac.l %d6,%a3,#-1,(%a2)+&,%d2
+	mac.l %d6,%a3,#-1,(%a2)+&,%a7
+	mac.l %d6,%a3,#-1,10(%a6),%d1
+	mac.l %d6,%a3,#-1,10(%a6),%a3
+	mac.l %d6,%a3,#-1,10(%a6),%d2
+	mac.l %d6,%a3,#-1,10(%a6),%a7
+	mac.l %d6,%a3,#-1,10(%a6)&,%d1
+	mac.l %d6,%a3,#-1,10(%a6)&,%a3
+	mac.l %d6,%a3,#-1,10(%a6)&,%d2
+	mac.l %d6,%a3,#-1,10(%a6)&,%a7
+	mac.l %d6,%a3,#-1,-(%a1),%d1
+	mac.l %d6,%a3,#-1,-(%a1),%a3
+	mac.l %d6,%a3,#-1,-(%a1),%d2
+	mac.l %d6,%a3,#-1,-(%a1),%a7
+	mac.l %d6,%a3,#-1,-(%a1)&,%d1
+	mac.l %d6,%a3,#-1,-(%a1)&,%a3
+	mac.l %d6,%a3,#-1,-(%a1)&,%d2
+	mac.l %d6,%a3,#-1,-(%a1)&,%a7
+	mac.l %d6,%d4,(%a3),%d1
+	mac.l %d6,%d4,(%a3),%a3
+	mac.l %d6,%d4,(%a3),%d2
+	mac.l %d6,%d4,(%a3),%a7
+	mac.l %d6,%d4,(%a3)&,%d1
+	mac.l %d6,%d4,(%a3)&,%a3
+	mac.l %d6,%d4,(%a3)&,%d2
+	mac.l %d6,%d4,(%a3)&,%a7
+	mac.l %d6,%d4,(%a2)+,%d1
+	mac.l %d6,%d4,(%a2)+,%a3
+	mac.l %d6,%d4,(%a2)+,%d2
+	mac.l %d6,%d4,(%a2)+,%a7
+	mac.l %d6,%d4,(%a2)+&,%d1
+	mac.l %d6,%d4,(%a2)+&,%a3
+	mac.l %d6,%d4,(%a2)+&,%d2
+	mac.l %d6,%d4,(%a2)+&,%a7
+	mac.l %d6,%d4,10(%a6),%d1
+	mac.l %d6,%d4,10(%a6),%a3
+	mac.l %d6,%d4,10(%a6),%d2
+	mac.l %d6,%d4,10(%a6),%a7
+	mac.l %d6,%d4,10(%a6)&,%d1
+	mac.l %d6,%d4,10(%a6)&,%a3
+	mac.l %d6,%d4,10(%a6)&,%d2
+	mac.l %d6,%d4,10(%a6)&,%a7
+	mac.l %d6,%d4,-(%a1),%d1
+	mac.l %d6,%d4,-(%a1),%a3
+	mac.l %d6,%d4,-(%a1),%d2
+	mac.l %d6,%d4,-(%a1),%a7
+	mac.l %d6,%d4,-(%a1)&,%d1
+	mac.l %d6,%d4,-(%a1)&,%a3
+	mac.l %d6,%d4,-(%a1)&,%d2
+	mac.l %d6,%d4,-(%a1)&,%a7
+	mac.l %d6,%d4,<<,(%a3),%d1
+	mac.l %d6,%d4,<<,(%a3),%a3
+	mac.l %d6,%d4,<<,(%a3),%d2
+	mac.l %d6,%d4,<<,(%a3),%a7
+	mac.l %d6,%d4,<<,(%a3)&,%d1
+	mac.l %d6,%d4,<<,(%a3)&,%a3
+	mac.l %d6,%d4,<<,(%a3)&,%d2
+	mac.l %d6,%d4,<<,(%a3)&,%a7
+	mac.l %d6,%d4,<<,(%a2)+,%d1
+	mac.l %d6,%d4,<<,(%a2)+,%a3
+	mac.l %d6,%d4,<<,(%a2)+,%d2
+	mac.l %d6,%d4,<<,(%a2)+,%a7
+	mac.l %d6,%d4,<<,(%a2)+&,%d1
+	mac.l %d6,%d4,<<,(%a2)+&,%a3
+	mac.l %d6,%d4,<<,(%a2)+&,%d2
+	mac.l %d6,%d4,<<,(%a2)+&,%a7
+	mac.l %d6,%d4,<<,10(%a6),%d1
+	mac.l %d6,%d4,<<,10(%a6),%a3
+	mac.l %d6,%d4,<<,10(%a6),%d2
+	mac.l %d6,%d4,<<,10(%a6),%a7
+	mac.l %d6,%d4,<<,10(%a6)&,%d1
+	mac.l %d6,%d4,<<,10(%a6)&,%a3
+	mac.l %d6,%d4,<<,10(%a6)&,%d2
+	mac.l %d6,%d4,<<,10(%a6)&,%a7
+	mac.l %d6,%d4,<<,-(%a1),%d1
+	mac.l %d6,%d4,<<,-(%a1),%a3
+	mac.l %d6,%d4,<<,-(%a1),%d2
+	mac.l %d6,%d4,<<,-(%a1),%a7
+	mac.l %d6,%d4,<<,-(%a1)&,%d1
+	mac.l %d6,%d4,<<,-(%a1)&,%a3
+	mac.l %d6,%d4,<<,-(%a1)&,%d2
+	mac.l %d6,%d4,<<,-(%a1)&,%a7
+	mac.l %d6,%d4,>>,(%a3),%d1
+	mac.l %d6,%d4,>>,(%a3),%a3
+	mac.l %d6,%d4,>>,(%a3),%d2
+	mac.l %d6,%d4,>>,(%a3),%a7
+	mac.l %d6,%d4,>>,(%a3)&,%d1
+	mac.l %d6,%d4,>>,(%a3)&,%a3
+	mac.l %d6,%d4,>>,(%a3)&,%d2
+	mac.l %d6,%d4,>>,(%a3)&,%a7
+	mac.l %d6,%d4,>>,(%a2)+,%d1
+	mac.l %d6,%d4,>>,(%a2)+,%a3
+	mac.l %d6,%d4,>>,(%a2)+,%d2
+	mac.l %d6,%d4,>>,(%a2)+,%a7
+	mac.l %d6,%d4,>>,(%a2)+&,%d1
+	mac.l %d6,%d4,>>,(%a2)+&,%a3
+	mac.l %d6,%d4,>>,(%a2)+&,%d2
+	mac.l %d6,%d4,>>,(%a2)+&,%a7
+	mac.l %d6,%d4,>>,10(%a6),%d1
+	mac.l %d6,%d4,>>,10(%a6),%a3
+	mac.l %d6,%d4,>>,10(%a6),%d2
+	mac.l %d6,%d4,>>,10(%a6),%a7
+	mac.l %d6,%d4,>>,10(%a6)&,%d1
+	mac.l %d6,%d4,>>,10(%a6)&,%a3
+	mac.l %d6,%d4,>>,10(%a6)&,%d2
+	mac.l %d6,%d4,>>,10(%a6)&,%a7
+	mac.l %d6,%d4,>>,-(%a1),%d1
+	mac.l %d6,%d4,>>,-(%a1),%a3
+	mac.l %d6,%d4,>>,-(%a1),%d2
+	mac.l %d6,%d4,>>,-(%a1),%a7
+	mac.l %d6,%d4,>>,-(%a1)&,%d1
+	mac.l %d6,%d4,>>,-(%a1)&,%a3
+	mac.l %d6,%d4,>>,-(%a1)&,%d2
+	mac.l %d6,%d4,>>,-(%a1)&,%a7
+	mac.l %d6,%d4,#1,(%a3),%d1
+	mac.l %d6,%d4,#1,(%a3),%a3
+	mac.l %d6,%d4,#1,(%a3),%d2
+	mac.l %d6,%d4,#1,(%a3),%a7
+	mac.l %d6,%d4,#1,(%a3)&,%d1
+	mac.l %d6,%d4,#1,(%a3)&,%a3
+	mac.l %d6,%d4,#1,(%a3)&,%d2
+	mac.l %d6,%d4,#1,(%a3)&,%a7
+	mac.l %d6,%d4,#1,(%a2)+,%d1
+	mac.l %d6,%d4,#1,(%a2)+,%a3
+	mac.l %d6,%d4,#1,(%a2)+,%d2
+	mac.l %d6,%d4,#1,(%a2)+,%a7
+	mac.l %d6,%d4,#1,(%a2)+&,%d1
+	mac.l %d6,%d4,#1,(%a2)+&,%a3
+	mac.l %d6,%d4,#1,(%a2)+&,%d2
+	mac.l %d6,%d4,#1,(%a2)+&,%a7
+	mac.l %d6,%d4,#1,10(%a6),%d1
+	mac.l %d6,%d4,#1,10(%a6),%a3
+	mac.l %d6,%d4,#1,10(%a6),%d2
+	mac.l %d6,%d4,#1,10(%a6),%a7
+	mac.l %d6,%d4,#1,10(%a6)&,%d1
+	mac.l %d6,%d4,#1,10(%a6)&,%a3
+	mac.l %d6,%d4,#1,10(%a6)&,%d2
+	mac.l %d6,%d4,#1,10(%a6)&,%a7
+	mac.l %d6,%d4,#1,-(%a1),%d1
+	mac.l %d6,%d4,#1,-(%a1),%a3
+	mac.l %d6,%d4,#1,-(%a1),%d2
+	mac.l %d6,%d4,#1,-(%a1),%a7
+	mac.l %d6,%d4,#1,-(%a1)&,%d1
+	mac.l %d6,%d4,#1,-(%a1)&,%a3
+	mac.l %d6,%d4,#1,-(%a1)&,%d2
+	mac.l %d6,%d4,#1,-(%a1)&,%a7
+	mac.l %d6,%d4,#-1,(%a3),%d1
+	mac.l %d6,%d4,#-1,(%a3),%a3
+	mac.l %d6,%d4,#-1,(%a3),%d2
+	mac.l %d6,%d4,#-1,(%a3),%a7
+	mac.l %d6,%d4,#-1,(%a3)&,%d1
+	mac.l %d6,%d4,#-1,(%a3)&,%a3
+	mac.l %d6,%d4,#-1,(%a3)&,%d2
+	mac.l %d6,%d4,#-1,(%a3)&,%a7
+	mac.l %d6,%d4,#-1,(%a2)+,%d1
+	mac.l %d6,%d4,#-1,(%a2)+,%a3
+	mac.l %d6,%d4,#-1,(%a2)+,%d2
+	mac.l %d6,%d4,#-1,(%a2)+,%a7
+	mac.l %d6,%d4,#-1,(%a2)+&,%d1
+	mac.l %d6,%d4,#-1,(%a2)+&,%a3
+	mac.l %d6,%d4,#-1,(%a2)+&,%d2
+	mac.l %d6,%d4,#-1,(%a2)+&,%a7
+	mac.l %d6,%d4,#-1,10(%a6),%d1
+	mac.l %d6,%d4,#-1,10(%a6),%a3
+	mac.l %d6,%d4,#-1,10(%a6),%d2
+	mac.l %d6,%d4,#-1,10(%a6),%a7
+	mac.l %d6,%d4,#-1,10(%a6)&,%d1
+	mac.l %d6,%d4,#-1,10(%a6)&,%a3
+	mac.l %d6,%d4,#-1,10(%a6)&,%d2
+	mac.l %d6,%d4,#-1,10(%a6)&,%a7
+	mac.l %d6,%d4,#-1,-(%a1),%d1
+	mac.l %d6,%d4,#-1,-(%a1),%a3
+	mac.l %d6,%d4,#-1,-(%a1),%d2
+	mac.l %d6,%d4,#-1,-(%a1),%a7
+	mac.l %d6,%d4,#-1,-(%a1)&,%d1
+	mac.l %d6,%d4,#-1,-(%a1)&,%a3
+	mac.l %d6,%d4,#-1,-(%a1)&,%d2
+	mac.l %d6,%d4,#-1,-(%a1)&,%a7
diff --git a/gas/testsuite/gas/m68k/mcf-mov3q.d b/gas/testsuite/gas/m68k/mcf-mov3q.d
index 0da153a21ab8..8de1d38b6871 100644
--- a/gas/testsuite/gas/m68k/mcf-mov3q.d
+++ b/gas/testsuite/gas/m68k/mcf-mov3q.d
@@ -6,7 +6,7 @@
 
 Disassembly of section .text:
 
-00000000 <test_mov3q>:
+0+ <test_mov3q>:
    0:	a140           	mov3ql #-1,%d0
    2:	a349           	mov3ql #1,%a1
    4:	a552           	mov3ql #2,%a2@
diff --git a/gas/testsuite/gas/m68k/mode5.d b/gas/testsuite/gas/m68k/mode5.d
new file mode 100644
index 000000000000..b51346b7b5bd
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mode5.d
@@ -0,0 +1,13 @@
+#name: mode5
+#objdump: -d
+#as: 
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	2213           	movel %a3@,%d1
+   2:	2882           	movel %d2,%a4@
+   4:	2295           	movel %a5@,%a1@
+	...
diff --git a/gas/testsuite/gas/m68k/mode5.s b/gas/testsuite/gas/m68k/mode5.s
new file mode 100644
index 000000000000..27c95d90f9db
--- /dev/null
+++ b/gas/testsuite/gas/m68k/mode5.s
@@ -0,0 +1,7 @@
+
+	| Test conversion of mode 5 addressing with a zero offset into mode 2.
+	.text
+	move.l 0(%a3),%d1
+	move.l %d2,0(%a4)
+	move.l 0(%a5),0(%a1)
+	.p2align 4
diff --git a/gas/testsuite/gas/m88k/allinsn.d b/gas/testsuite/gas/m88k/allinsn.d
deleted file mode 100644
index 3d2c29e706c8..000000000000
--- a/gas/testsuite/gas/m88k/allinsn.d
+++ /dev/null
@@ -1,369 +0,0 @@
-#as:
-#objdump: -dr
-#name: allinsn
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	f4 01 70 02 	add         r0,r1,r2
-   4:	f4 22 72 03 	add.ci      r1,r2,r3
-   8:	f4 43 71 04 	add.co      r2,r3,r4
-   c:	f4 64 73 05 	add.cio     r3,r4,r5
-  10:	70 85 00 00 	add         r4,r5,0
-  14:	70 85 10 00 	add         r4,r5,0x1000
-  18:	f4 01 60 02 	addu        r0,r1,r2
-  1c:	f4 22 62 03 	addu.ci     r1,r2,r3
-  20:	f4 43 61 04 	addu.co     r2,r3,r4
-  24:	f4 64 63 05 	addu.cio    r3,r4,r5
-  28:	60 85 00 00 	addu        r4,r5,0
-  2c:	60 85 10 00 	addu        r4,r5,0x1000
-  30:	f4 01 40 02 	and         r0,r1,r2
-  34:	f4 22 44 03 	and.c       r1,r2,r3
-  38:	40 43 00 00 	and         r2,r3,0
-  3c:	40 43 10 00 	and         r2,r3,0x1000
-  40:	44 43 00 00 	and.u       r2,r3,0
-  44:	44 43 10 00 	and.u       r2,r3,0x1000
-  48:	d0 01 00 00 	bb0         0,r1,48 <.text\+0x48>
-			4a: PCR16L	\*ABS\*
-  4c:	d0 01 ff fd 	bb0         0,r1,40 <.text\+0x40>
-			4e: PCR16L	\*ABS\*
-  50:	d0 01 00 02 	bb0         0,r1,58 <.text\+0x58>
-			52: PCR16L	\*ABS\*
-  54:	d3 e1 00 00 	bb0         0x1f,r1,54 <.text\+0x54>
-			56: PCR16L	\*ABS\*
-  58:	d3 e1 ff fd 	bb0         0x1f,r1,4c <.text\+0x4c>
-			5a: PCR16L	\*ABS\*
-  5c:	d3 e1 00 02 	bb0         0x1f,r1,64 <.text\+0x64>
-			5e: PCR16L	\*ABS\*
-  60:	d4 01 00 00 	bb0.n       0,r1,60 <.text\+0x60>
-			62: PCR16L	\*ABS\*
-  64:	d8 01 00 00 	bb1         0,r1,64 <.text\+0x64>
-			66: PCR16L	\*ABS\*
-  68:	d8 01 ff fd 	bb1         0,r1,5c <.text\+0x5c>
-			6a: PCR16L	\*ABS\*
-  6c:	d8 01 00 02 	bb1         0,r1,74 <.text\+0x74>
-			6e: PCR16L	\*ABS\*
-  70:	db e1 00 00 	bb1         0x1f,r1,70 <.text\+0x70>
-			72: PCR16L	\*ABS\*
-  74:	db e1 ff fd 	bb1         0x1f,r1,68 <.text\+0x68>
-			76: PCR16L	\*ABS\*
-  78:	db e1 00 02 	bb1         0x1f,r1,80 <.text\+0x80>
-			7a: PCR16L	\*ABS\*
-  7c:	dc 01 00 00 	bb1.n       0,r1,7c <.text\+0x7c>
-			7e: PCR16L	\*ABS\*
-  80:	e8 41 00 00 	bcnd        eq0,r1,80 <.text\+0x80>
-			82: PCR16L	\*ABS\*
-  84:	e8 41 00 02 	bcnd        eq0,r1,8c <.text\+0x8c>
-			86: PCR16L	\*ABS\*
-  88:	e8 41 ff fd 	bcnd        eq0,r1,7c <.text\+0x7c>
-			8a: PCR16L	\*ABS\*
-  8c:	ec 41 00 00 	bcnd.n      eq0,r1,8c <.text\+0x8c>
-			8e: PCR16L	\*ABS\*
-  90:	ec 41 00 02 	bcnd.n      eq0,r1,98 <.text\+0x98>
-			92: PCR16L	\*ABS\*
-  94:	ec 41 ff fd 	bcnd.n      eq0,r1,88 <.text\+0x88>
-			96: PCR16L	\*ABS\*
-  98:	e9 a1 00 00 	bcnd        ne0,r1,98 <.text\+0x98>
-			9a: PCR16L	\*ABS\*
-  9c:	e9 a1 00 02 	bcnd        ne0,r1,a4 <.text\+0xa4>
-			9e: PCR16L	\*ABS\*
-  a0:	e9 a1 ff fd 	bcnd        ne0,r1,94 <.text\+0x94>
-			a2: PCR16L	\*ABS\*
-  a4:	ed a1 00 00 	bcnd.n      ne0,r1,a4 <.text\+0xa4>
-			a6: PCR16L	\*ABS\*
-  a8:	ed a1 00 02 	bcnd.n      ne0,r1,b0 <.text\+0xb0>
-			aa: PCR16L	\*ABS\*
-  ac:	ed a1 ff fd 	bcnd.n      ne0,r1,a0 <.text\+0xa0>
-			ae: PCR16L	\*ABS\*
-  b0:	e8 21 00 00 	bcnd        gt0,r1,b0 <.text\+0xb0>
-			b2: PCR16L	\*ABS\*
-  b4:	e8 21 00 02 	bcnd        gt0,r1,bc <.text\+0xbc>
-			b6: PCR16L	\*ABS\*
-  b8:	e8 21 ff fd 	bcnd        gt0,r1,ac <.text\+0xac>
-			ba: PCR16L	\*ABS\*
-  bc:	ec 21 00 00 	bcnd.n      gt0,r1,bc <.text\+0xbc>
-			be: PCR16L	\*ABS\*
-  c0:	ec 21 00 02 	bcnd.n      gt0,r1,c8 <.text\+0xc8>
-			c2: PCR16L	\*ABS\*
-  c4:	ec 21 ff fd 	bcnd.n      gt0,r1,b8 <.text\+0xb8>
-			c6: PCR16L	\*ABS\*
-  c8:	e9 81 00 00 	bcnd        lt0,r1,c8 <.text\+0xc8>
-			ca: PCR16L	\*ABS\*
-  cc:	e9 81 00 02 	bcnd        lt0,r1,d4 <.text\+0xd4>
-			ce: PCR16L	\*ABS\*
-  d0:	e9 81 ff fd 	bcnd        lt0,r1,c4 <.text\+0xc4>
-			d2: PCR16L	\*ABS\*
-  d4:	ed 81 00 00 	bcnd.n      lt0,r1,d4 <.text\+0xd4>
-			d6: PCR16L	\*ABS\*
-  d8:	ed 81 00 02 	bcnd.n      lt0,r1,e0 <.text\+0xe0>
-			da: PCR16L	\*ABS\*
-  dc:	ed 81 ff fd 	bcnd.n      lt0,r1,d0 <.text\+0xd0>
-			de: PCR16L	\*ABS\*
-  e0:	e8 61 00 00 	bcnd        ge0,r1,e0 <.text\+0xe0>
-			e2: PCR16L	\*ABS\*
-  e4:	e8 61 00 02 	bcnd        ge0,r1,ec <.text\+0xec>
-			e6: PCR16L	\*ABS\*
-  e8:	e8 61 ff fd 	bcnd        ge0,r1,dc <.text\+0xdc>
-			ea: PCR16L	\*ABS\*
-  ec:	ec 61 00 00 	bcnd.n      ge0,r1,ec <.text\+0xec>
-			ee: PCR16L	\*ABS\*
-  f0:	ec 61 00 02 	bcnd.n      ge0,r1,f8 <.text\+0xf8>
-			f2: PCR16L	\*ABS\*
-  f4:	ec 61 ff fd 	bcnd.n      ge0,r1,e8 <.text\+0xe8>
-			f6: PCR16L	\*ABS\*
-  f8:	e9 c1 00 00 	bcnd        le0,r1,f8 <.text\+0xf8>
-			fa: PCR16L	\*ABS\*
-  fc:	e9 c1 00 02 	bcnd        le0,r1,104 <.text\+0x104>
-			fe: PCR16L	\*ABS\*
- 100:	e9 c1 ff fd 	bcnd        le0,r1,f4 <.text\+0xf4>
-			102: PCR16L	\*ABS\*
- 104:	ed c1 00 00 	bcnd.n      le0,r1,104 <.text\+0x104>
-			106: PCR16L	\*ABS\*
- 108:	ed c1 00 02 	bcnd.n      le0,r1,110 <.text\+0x110>
-			10a: PCR16L	\*ABS\*
- 10c:	ed c1 ff fd 	bcnd.n      le0,r1,100 <.text\+0x100>
-			10e: PCR16L	\*ABS\*
- 110:	e8 61 00 00 	bcnd        ge0,r1,110 <.text\+0x110>
-			112: PCR16L	\*ABS\*
- 114:	e8 61 00 02 	bcnd        ge0,r1,11c <.text\+0x11c>
-			116: PCR16L	\*ABS\*
- 118:	e8 61 ff fd 	bcnd        ge0,r1,10c <.text\+0x10c>
-			11a: PCR16L	\*ABS\*
- 11c:	ec 61 00 00 	bcnd.n      ge0,r1,11c <.text\+0x11c>
-			11e: PCR16L	\*ABS\*
- 120:	ec 61 00 02 	bcnd.n      ge0,r1,128 <.text\+0x128>
-			122: PCR16L	\*ABS\*
- 124:	ec 61 ff fd 	bcnd.n      ge0,r1,118 <.text\+0x118>
-			126: PCR16L	\*ABS\*
- 128:	c0 00 00 00 	br          128 <.text\+0x128>
-			128: PCR26L	\*ABS\*
- 12c:	c3 ff ff fd 	br          120 <.text\+0x120>
-			12c: PCR26L	\*ABS\*
- 130:	c0 00 00 02 	br          138 <.text\+0x138>
-			130: PCR26L	\*ABS\*
- 134:	c4 00 00 00 	br.n        134 <.text\+0x134>
-			134: PCR26L	\*ABS\*
- 138:	c7 ff ff fd 	br.n        12c <.text\+0x12c>
-			138: PCR26L	\*ABS\*
- 13c:	c4 00 00 02 	br.n        144 <.text\+0x144>
-			13c: PCR26L	\*ABS\*
- 140:	c8 00 00 00 	bsr         140 <.text\+0x140>
-			140: PCR26L	\*ABS\*
- 144:	cb ff ff fd 	bsr         138 <.text\+0x138>
-			144: PCR26L	\*ABS\*
- 148:	c8 00 00 02 	bsr         150 <.text\+0x150>
-			148: PCR26L	\*ABS\*
- 14c:	cc 00 00 00 	bsr.n       14c <.text\+0x14c>
-			14c: PCR26L	\*ABS\*
- 150:	cf ff ff fd 	bsr.n       144 <.text\+0x144>
-			150: PCR26L	\*ABS\*
- 154:	cc 00 00 02 	bsr.n       15c <.text\+0x15c>
-			154: PCR26L	\*ABS\*
- 158:	f0 22 80 af 	clr         r1,r2,5<15>
- 15c:	f4 22 80 03 	clr         r1,r2,r3
- 160:	f0 22 80 06 	clr         r1,r2,0<6>
- 164:	f0 22 80 06 	clr         r1,r2,0<6>
- 168:	f4 01 7c 02 	cmp         r0,r1,r2
- 16c:	7c 02 00 00 	cmp         r0,r2,0
- 170:	7c 02 10 00 	cmp         r0,r2,0x1000
- 174:	f4 01 78 02 	divs        r0,r1,r2
- 178:	78 01 00 00 	divs        r0,r1,0
- 17c:	78 01 10 00 	divs        r0,r1,0x1000
- 180:	f4 01 68 02 	divu        r0,r1,r2
- 184:	68 01 00 00 	divu        r0,r1,0
- 188:	68 01 00 0a 	divu        r0,r1,0x0a
- 18c:	f0 01 91 45 	ext         r0,r1,10<5>
- 190:	f4 22 90 03 	ext         r1,r2,r3
- 194:	f0 43 90 06 	ext         r2,r3,0<6>
- 198:	f0 43 90 06 	ext         r2,r3,0<6>
- 19c:	f0 01 99 45 	extu        r0,r1,10<5>
- 1a0:	f4 22 98 03 	extu        r1,r2,r3
- 1a4:	f0 22 98 06 	extu        r1,r2,0<6>
- 1a8:	f0 22 98 06 	extu        r1,r2,0<6>
- 1ac:	84 01 28 02 	fadd.sss    r0,r1,r2
- 1b0:	84 01 28 82 	fadd.ssd    r0,r1,r2
- 1b4:	84 01 2a 02 	fadd.sds    r0,r1,r2
- 1b8:	84 01 2a 82 	fadd.sdd    r0,r1,r2
- 1bc:	84 01 28 22 	fadd.dss    r0,r1,r2
- 1c0:	84 01 28 a2 	fadd.dsd    r0,r1,r2
- 1c4:	84 01 2a 22 	fadd.dds    r0,r1,r2
- 1c8:	84 01 2a a2 	fadd.ddd    r0,r1,r2
- 1cc:	84 01 38 02 	fcmp.ss     r0,r1,r2
- 1d0:	84 01 38 82 	fcmp.sd     r0,r1,r2
- 1d4:	84 01 3a 02 	fcmp.ds     r0,r1,r2
- 1d8:	84 01 3a 82 	fcmp.dd     r0,r1,r2
- 1dc:	84 01 70 02 	fdiv.sss    r0,r1,r2
- 1e0:	84 01 70 82 	fdiv.ssd    r0,r1,r2
- 1e4:	84 01 72 02 	fdiv.sds    r0,r1,r2
- 1e8:	84 01 72 82 	fdiv.sdd    r0,r1,r2
- 1ec:	84 01 70 22 	fdiv.dss    r0,r1,r2
- 1f0:	84 01 70 a2 	fdiv.dsd    r0,r1,r2
- 1f4:	84 01 72 22 	fdiv.dds    r0,r1,r2
- 1f8:	84 01 72 a2 	fdiv.ddd    r0,r1,r2
- 1fc:	f4 20 ec 07 	ff0         r1,r7
- 200:	f4 60 e8 08 	ff1         r3,r8
- 204:	80 00 4e 40 	fldcr       r0,fcr50
- 208:	84 00 20 03 	flt.s       r0,r3
- 20c:	84 00 20 2a 	flt.d       r0,r10
- 210:	84 01 00 02 	fmul.sss    r0,r1,r2
- 214:	84 01 00 82 	fmul.ssd    r0,r1,r2
- 218:	84 01 02 02 	fmul.sds    r0,r1,r2
- 21c:	84 01 02 82 	fmul.sdd    r0,r1,r2
- 220:	84 01 00 22 	fmul.dss    r0,r1,r2
- 224:	84 01 00 a2 	fmul.dsd    r0,r1,r2
- 228:	84 01 02 22 	fmul.dds    r0,r1,r2
- 22c:	84 01 02 a2 	fmul.ddd    r0,r1,r2
- 230:	80 00 8e 40 	fstcr       r0,fcr50
- 234:	84 01 30 02 	fsub.sss    r0,r1,r2
- 238:	84 01 30 82 	fsub.ssd    r0,r1,r2
- 23c:	84 01 32 02 	fsub.sds    r0,r1,r2
- 240:	84 01 32 82 	fsub.sdd    r0,r1,r2
- 244:	84 01 30 22 	fsub.dss    r0,r1,r2
- 248:	84 01 30 a2 	fsub.dsd    r0,r1,r2
- 24c:	84 01 32 22 	fsub.dds    r0,r1,r2
- 250:	84 01 32 a2 	fsub.ddd    r0,r1,r2
- 254:	80 01 ce 41 	fxcr        r0,r1,fcr50
- 258:	84 00 48 01 	int.s       r0,r1
- 25c:	85 40 48 82 	int.d       r10,r2
- 260:	f4 00 c0 00 	jmp         r0
- 264:	f4 00 c4 0a 	jmp.n       r10
- 268:	f4 00 c8 0a 	jsr         r10
- 26c:	f4 00 cc 0d 	jsr.n       r13
- 270:	1c 01 00 00 	ld.b        r0,r1,0
- 274:	1c 01 10 00 	ld.b        r0,r1,0x1000
- 278:	0c 01 00 00 	ld.bu       r0,r1,0
- 27c:	0c 01 10 00 	ld.bu       r0,r1,0x1000
- 280:	18 01 00 00 	ld.h        r0,r1,0
- 284:	18 01 10 00 	ld.h        r0,r1,0x1000
- 288:	08 01 00 00 	ld.hu       r0,r1,0
- 28c:	08 01 10 00 	ld.hu       r0,r1,0x1000
- 290:	14 01 00 00 	ld          r0,r1,0
- 294:	14 01 10 00 	ld          r0,r1,0x1000
- 298:	10 01 00 00 	ld.d        r0,r1,0
- 29c:	10 01 10 00 	ld.d        r0,r1,0x1000
- 2a0:	f4 01 1c 02 	ld.b        r0,r1,r2
- 2a4:	f4 22 0c 03 	ld.bu       r1,r2,r3
- 2a8:	f4 43 18 04 	ld.h        r2,r3,r4
- 2ac:	f4 64 08 05 	ld.hu       r3,r4,r5
- 2b0:	f4 85 14 06 	ld          r4,r5,r6
- 2b4:	f4 a6 10 07 	ld.d        r5,r6,r7
- 2b8:	f4 c7 1d 08 	word	f4c71d08
- 2bc:	f4 e8 0d 09 	word	f4e80d09
- 2c0:	f5 09 19 01 	word	f5091901
- 2c4:	f5 21 09 02 	word	f5210902
- 2c8:	f4 22 15 03 	ld.usr      r1,r2,r3
- 2cc:	f4 43 11 04 	word	f4431104
- 2d0:	f4 01 1e 02 	word	f4011e02
- 2d4:	f4 22 0e 03 	word	f4220e03
- 2d8:	f4 43 1a 04 	ld.h        r2,r3\[r4\]
- 2dc:	f4 64 0a 05 	ld.hu       r3,r4\[r5\]
- 2e0:	f4 85 16 06 	ld          r4,r5\[r6\]
- 2e4:	f4 a6 12 07 	ld.d        r5,r6\[r7\]
- 2e8:	f4 c7 1f 08 	word	f4c71f08
- 2ec:	f4 e8 0f 09 	word	f4e80f09
- 2f0:	f5 09 1b 01 	word	f5091b01
- 2f4:	f5 21 0b 02 	word	f5210b02
- 2f8:	f4 22 17 03 	ld.usr      r1,r2\[r3\]
- 2fc:	f4 43 13 04 	word	f4431304
- 300:	f4 01 3a 02 	lda.h       r0,r1\[r2\]
- 304:	f4 22 36 03 	lda         r1,r2\[r3\]
- 308:	f4 43 32 04 	lda.d       r2,r3\[r4\]
- 30c:	80 00 41 40 	ldcr        r0,cr10
- 310:	f0 01 a1 45 	mak         r0,r1,10<5>
- 314:	f4 01 a0 02 	mak         r0,r1,r2
- 318:	f0 01 a0 06 	mak         r0,r1,0<6>
- 31c:	f0 01 a0 06 	mak         r0,r1,0<6>
- 320:	48 01 00 00 	mask        r0,r1,0
- 324:	48 01 10 00 	mask        r0,r1,0x1000
- 328:	4c 01 00 00 	mask.u      r0,r1,0
- 32c:	4c 01 10 00 	mask.u      r0,r1,0x1000
- 330:	f4 01 6c 02 	mulu        r0,r1,r2
- 334:	6c 01 00 00 	mulu        r0,r1,0
- 338:	6c 01 10 00 	mulu        r0,r1,0x1000
- 33c:	84 00 50 0a 	nint.s      r0,r10
- 340:	85 40 50 8c 	nint.d      r10,r12
- 344:	f4 01 58 02 	or          r0,r1,r2
- 348:	f4 27 5c 0a 	or.c        r1,r7,r10
- 34c:	58 04 00 00 	or          r0,r4,0
- 350:	58 04 10 00 	or          r0,r4,0x1000
- 354:	5c 01 00 00 	or.u        r0,r1,0
- 358:	5c 44 10 00 	or.u        r2,r4,0x1000
- 35c:	f0 01 a8 05 	rot         r0,r1,0<5>
- 360:	f4 44 a8 06 	rot         r2,r4,r6
- 364:	f4 00 fc 00 	rte         
- 368:	f0 01 89 45 	set         r0,r1,10<5>
- 36c:	f4 44 88 06 	set         r2,r4,r6
- 370:	f0 67 88 06 	set         r3,r7,0<6>
- 374:	f0 67 88 06 	set         r3,r7,0<6>
- 378:	2c 01 00 00 	st.b        r0,r1,0
- 37c:	2c 01 10 00 	st.b        r0,r1,0x1000
- 380:	28 01 00 00 	st.h        r0,r1,0
- 384:	28 01 10 00 	st.h        r0,r1,0x1000
- 388:	24 01 00 00 	st          r0,r1,0
- 38c:	24 01 10 00 	st          r0,r1,0x1000
- 390:	20 01 00 00 	st.d        r0,r1,0
- 394:	20 01 10 00 	st.d        r0,r1,0x1000
- 398:	f4 01 2c 02 	st.b        r0,r1,r2
- 39c:	f4 43 28 04 	st.h        r2,r3,r4
- 3a0:	f4 85 24 06 	st          r4,r5,r6
- 3a4:	f4 a6 20 07 	st.d        r5,r6,r7
- 3a8:	f4 c7 2d 08 	word	f4c72d08
- 3ac:	f5 09 29 01 	word	f5092901
- 3b0:	f4 22 25 03 	st.usr      r1,r2,r3
- 3b4:	f4 43 21 04 	word	f4432104
- 3b8:	f4 01 2e 02 	word	f4012e02
- 3bc:	f4 43 2a 04 	st.h        r2,r3\[r4\]
- 3c0:	f4 85 26 06 	st          r4,r5\[r6\]
- 3c4:	f4 a6 22 07 	st.d        r5,r6\[r7\]
- 3c8:	f4 c7 2f 08 	word	f4c72f08
- 3cc:	f5 09 2b 01 	word	f5092b01
- 3d0:	f4 22 27 03 	st.usr      r1,r2\[r3\]
- 3d4:	f4 43 23 04 	word	f4432304
- 3d8:	80 00 81 40 	stcr        r0,cr10
- 3dc:	f4 01 74 02 	sub         r0,r1,r2
- 3e0:	f4 22 76 03 	sub.ci      r1,r2,r3
- 3e4:	f4 43 75 04 	sub.co      r2,r3,r4
- 3e8:	f4 64 77 05 	sub.cio     r3,r4,r5
- 3ec:	74 85 00 00 	sub         r4,r5,0
- 3f0:	74 85 10 00 	sub         r4,r5,0x1000
- 3f4:	f4 01 64 02 	subu        r0,r1,r2
- 3f8:	f4 22 66 03 	subu.ci     r1,r2,r3
- 3fc:	f4 64 65 05 	subu.co     r3,r4,r5
- 400:	f4 85 67 06 	subu.cio    r4,r5,r6
- 404:	64 a6 00 00 	subu        r5,r6,0
- 408:	64 a6 10 00 	subu        r5,r6,0x1000
- 40c:	f0 0a d0 0a 	tb0         0,r10,0x0a
- 410:	f3 eb d0 0a 	tb0         0x1f,r11,0x0a
- 414:	f0 0a d8 0a 	tb1         0,r10,0x0a
- 418:	f3 eb d8 0a 	tb1         0x1f,r11,0x0a
- 41c:	f4 00 f8 01 	tbnd        r0,r1
- 420:	f8 07 00 00 	tbnd        r7,0
- 424:	f8 07 10 00 	tbnd        r7,0x1000
- 428:	f0 4a e8 0c 	tcnd        eq0,r10,0x0c
- 42c:	f1 a9 e8 0c 	tcnd        ne0,r9,0x0c
- 430:	f0 28 e8 07 	tcnd        gt0,r8,0x07
- 434:	f1 87 e8 01 	tcnd        lt0,r7,0x01
- 438:	f0 66 e8 23 	tcnd        ge0,r6,0x23
- 43c:	f1 c5 e8 21 	tcnd        le0,r5,0x21
- 440:	f1 44 e8 0c 	tcnd        a,r4,0x0c
- 444:	84 00 58 01 	trnc.s      r0,r1
- 448:	84 20 58 83 	trnc.d      r1,r3
- 44c:	80 03 c1 43 	xcr         r0,r3,cr10
- 450:	f4 01 00 02 	xmem.bu     r0,r1,r2
- 454:	f4 22 04 03 	xmem        r1,r2,r3
- 458:	f4 85 01 06 	word	f4850106
- 45c:	f4 a6 05 07 	xmem.usr    r5,r6,r7
- 460:	f4 43 02 04 	word	f4430204
- 464:	f4 64 06 05 	xmem        r3,r4\[r5\]
- 468:	f4 85 03 09 	word	f4850309
- 46c:	f4 a6 07 0a 	xmem.usr    r5,r6\[r10\]
- 470:	f4 01 50 02 	xor         r0,r1,r2
- 474:	f4 22 54 03 	xor.c       r1,r2,r3
- 478:	50 43 00 00 	xor         r2,r3,0
- 47c:	50 44 10 00 	xor         r2,r4,0x1000
- 480:	54 22 00 00 	xor.u       r1,r2,0
- 484:	54 43 10 00 	xor.u       r2,r3,0x1000
- 488:	f4 00 58 00 	or          r0,r0,r0
- 48c:	f4 00 58 00 	or          r0,r0,r0
diff --git a/gas/testsuite/gas/m88k/allinsn.s b/gas/testsuite/gas/m88k/allinsn.s
deleted file mode 100644
index 4a7e60a365f0..000000000000
--- a/gas/testsuite/gas/m88k/allinsn.s
+++ /dev/null
@@ -1,460 +0,0 @@
-	;; Test all instructions in the m88k instruction set.
-	;; Copyright 2001 Free Software Foundation, Inc.
-	;; Contributed by Ben Elliston (bje at redhat.com).
-
-.text
-	;; integer add
-
-	add	r0, r1, r2
-	add.ci	r1, r2, r3
-	add.co	r2, r3, r4
-	add.cio	r3, r4, r5
-	add	r4, r5, 0
-	add	r4, r5, 4096
-
-	;; unsigned integer add
-
-	addu	 r0, r1, r2
-	addu.ci	 r1, r2, r3
-	addu.co	 r2, r3, r4
-	addu.cio r3, r4, r5
-	addu	 r4, r5, 0
-	addu	 r4, r5, 4096
-
-	;; logical and
-
-	and	r0, r1, r2
-	and.c	r1, r2, r3
-	and	r2, r3, 0
-	and	r2, r3, 4096
-	and.u	r2, r3, 0
-	and.u	r2, r3, 4096
-
-	;; branch on bit clear
-
-	bb0	0, r1, 0
-	bb0	0, r1, -10
-	bb0	0, r1, 10
-	bb0	31, r1, 0
-	bb0	31, r1, -10
-	bb0	31, r1, 10
-	bb0.n	0, r1, 0
-
-	;; branch on bit set
-
-	bb1	0, r1, 0
-	bb1	0, r1, -10
-	bb1	0, r1, 10
-	bb1	31, r1, 0
-	bb1	31, r1, -10
-	bb1	31, r1, 10
-	bb1.n	0, r1, 0
-
-	;;  conditional branch
-
-	bcnd	eq0, r1, 0
-	bcnd	eq0, r1, 10
-	bcnd	eq0, r1, -10	
-	bcnd.n	eq0, r1, 0
-	bcnd.n	eq0, r1, 10
-	bcnd.n	eq0, r1, -10
-	bcnd	ne0, r1, 0
-	bcnd	ne0, r1, 10
-	bcnd	ne0, r1, -10	
-	bcnd.n	ne0, r1, 0
-	bcnd.n	ne0, r1, 10
-	bcnd.n	ne0, r1, -10
-	bcnd	gt0, r1, 0
-	bcnd	gt0, r1, 10
-	bcnd	gt0, r1, -10	
-	bcnd.n	gt0, r1, 0
-	bcnd.n	gt0, r1, 10
-	bcnd.n	gt0, r1, -10
-	bcnd	lt0, r1, 0
-	bcnd	lt0, r1, 10
-	bcnd	lt0, r1, -10	
-	bcnd.n	lt0, r1, 0
-	bcnd.n	lt0, r1, 10
-	bcnd.n	lt0, r1, -10
-	bcnd	ge0, r1, 0
-	bcnd	ge0, r1, 10
-	bcnd	ge0, r1, -10	
-	bcnd.n	ge0, r1, 0
-	bcnd.n	ge0, r1, 10
-	bcnd.n	ge0, r1, -10
-	bcnd	le0, r1, 0
-	bcnd	le0, r1, 10
-	bcnd	le0, r1, -10	
-	bcnd.n	le0, r1, 0
-	bcnd.n	le0, r1, 10
-	bcnd.n	le0, r1, -10
-	;;  using m5 field
-	bcnd	3, r1, 0
-	bcnd	3, r1, 10
-	bcnd	3, r1, -10	
-	bcnd.n	3, r1, 0
-	bcnd.n	3, r1, 10
-	bcnd.n	3, r1, -10		
-
-	;; uncoditional branch
-
-	br 0
-	br -10
-	br 10
-	br.n 0
-	br.n -10
-	br.n 10
-
-	;; branch to subroutine
-
-	bsr 0
-	bsr -10
-	bsr 10
-	bsr.n 0
-	bsr.n -10
-	bsr.n 10
-	
-	;; clear bit field
-
-	clr r1, r2, 5<15>
-	clr r1, r2, r3
-	clr r1, r2, 6
-	clr r1, r2, <6>
-
-	;; integer compare
-
-	cmp r0, r1, r2
-	cmp r0, r2, 0
-	cmp r0, r2, 4096
-
-	;; signed integer divide
-
-	div r0, r1, r2
-	div r0, r1, 0
-	div r0, r1, 4096
-
-	;; unsigned integer divide
-
-	divu r0, r1, r2
-	divu r0, r1, 0
-	divu r0, r1, 10
-
-	;; extract signed bit field
-
-	ext r0, r1, 10<5>
-	ext r1, r2, r3
-	ext r2, r3, 6
-	ext r2, r3, <6>
-
-	;; extract unsigned bit field
-
-	extu r0, r1, 10<5>
-	extu r1, r2, r3
-	extu r1, r2, 6
-	extu r1, r2, <6>
-
-	;; floating point add
-
-	fadd.sss r0, r1, r2
-	fadd.ssd r0, r1, r2
-	fadd.sds r0, r1, r2
-	fadd.sdd r0, r1, r2
-	fadd.dss r0, r1, r2
-	fadd.dsd r0, r1, r2
-	fadd.dds r0, r1, r2
-	fadd.ddd r0, r1, r2
-
-	;; floating point compare
-
-	fcmp.sss r0, r1, r2
-	fcmp.ssd r0, r1, r2
-	fcmp.sds r0, r1, r2
-	fcmp.sdd r0, r1, r2
-
-	;; floating point divide
-
-	fdiv.sss r0, r1, r2
-	fdiv.ssd r0, r1, r2
-	fdiv.sds r0, r1, r2
-	fdiv.sdd r0, r1, r2
-	fdiv.dss r0, r1, r2
-	fdiv.dsd r0, r1, r2
-	fdiv.dds r0, r1, r2
-	fdiv.ddd r0, r1, r2
-
-	;; find first bit clear
-
-	ff0 r1, r7
-
-	;; find first bit set
-
-	ff1 r3, r8
-
-	;; load from floating-point control register
-
-	fldcr r0, fcr50
-
-	;; convert integer to floating point
-
-	flt.ss r0, r3
-	flt.ds r0, r10
-
-	;; floating point multiply
-
-	fmul.sss r0, r1, r2
-	fmul.ssd r0, r1, r2
-	fmul.sds r0, r1, r2
-	fmul.sdd r0, r1, r2
-	fmul.dss r0, r1, r2
-	fmul.dsd r0, r1, r2
-	fmul.dds r0, r1, r2
-	fmul.ddd r0, r1, r2
-	
-	;; store to floating point control register
-
-	fstcr r0, fcr50
-
-	;; floating point subtract
-
-	fsub.sss r0, r1, r2
-	fsub.ssd r0, r1, r2
-	fsub.sds r0, r1, r2
-	fsub.sdd r0, r1, r2
-	fsub.dss r0, r1, r2
-	fsub.dsd r0, r1, r2
-	fsub.dds r0, r1, r2
-	fsub.ddd r0, r1, r2
-
-	;; exchange floating point control register
-
-	fxcr r0, r1, fcr50
-
-	;; round floating point to integer
-
-	int.ss r0, r1
-	int.sd r10, r2
-
-	;; unconditional jump
-
-	jmp   r0
-	jmp.n r10
-
-	;; jump to subroutine
-
-	jsr   r10
-	jsr.n r13
-
-	;; load register from memory
-
-	;; unscaled
-	ld.b    r0, r1, 0
-	ld.b    r0, r1, 4096
-	ld.bu   r0, r1, 0
-	ld.bu   r0, r1, 4096
-	ld.h    r0, r1, 0
-	ld.h    r0, r1, 4096
-	ld.hu	r0, r1, 0
-	ld.hu	r0, r1, 4096
-	ld	r0, r1, 0
-	ld	r0, r1, 4096
-	ld.d	r0, r1, 0
-	ld.d	r0, r1, 4096
-	;; unscaled
-	ld.b	  r0, r1, r2
-	ld.bu	  r1, r2, r3
-	ld.h	  r2, r3, r4
-	ld.hu 	  r3, r4, r5
-	ld	  r4, r5, r6
-	ld.d	  r5, r6, r7
-	ld.b.usr  r6, r7, r8
-	ld.bu.usr r7, r8, r9
-	ld.h.usr  r8, r9, r1
-	ld.hu.usr r9, r1, r2
-	ld.usr	  r1, r2, r3
-	ld.d.usr  r2, r3, r4
-	;; scaled
-	ld.b	  r0, r1[r2]
-	ld.bu	  r1, r2[r3]
-	ld.h	  r2, r3[r4]
-	ld.hu 	  r3, r4[r5]
-	ld	  r4, r5[r6]
-	ld.d	  r5, r6[r7]
-	ld.b.usr  r6, r7[r8]
-	ld.bu.usr r7, r8[r9]
-	ld.h.usr  r8, r9[r1]
-	ld.hu.usr r9, r1[r2]
-	ld.usr	  r1, r2[r3]
-	ld.d.usr  r2, r3[r4]
-
-	;; load address
-
-	lda.h r0, r1[r2]
-	lda   r1,r2[r3]
-	lda.d r2,r3[r4]
-
-	;; load from control register
-
-	ldcr r0, cr10
-
-	;; make bit field
-
-	mak r0, r1, 10<5>
-	mak r0, r1, r2
-	mak r0, r1, 6
-	mak r0, r1, <6>
-	
-	;; logical mask immediate
-
-	mask   r0, r1, 0
-	mask   r0, r1, 4096
-	mask.u r0, r1, 0
-	mask.u r0, r1, 4096
-
-	;; integer multiply
-
-	mul r0, r1, r2
-	mul r0, r1, 0
-	mul r0, r1, 4096
-
-	;; floating point round to nearest integer
-
-	nint.ss r0, r10
-	nint.sd r10, r12
-
-	;; logical or
-
-	or   r0, r1, r2
-	or.c r1, r7, r10
-	or   r0, r4, 0
-	or   r0, r4, 4096
-	or.u r0, r1, 0
-	or.u r2, r4, 4096
-
-	;; rotate register
-
-	rot r0, r1,<5>
-	rot r2, r4, r6
-	
-	;; return from exception
-
-	rte
-
-	;; set bit field
-
-	set r0, r1, 10<5>
-	set r2, r4, r6
-	set r3, r7, 6
-	set r3, r7, <6>
-	
-	;; store register to memory
-
-	;; unscaled
-	st.b    r0, r1, 0
-	st.b    r0, r1, 4096
-	st.h    r0, r1, 0
-	st.h    r0, r1, 4096
-	st	r0, r1, 0
-	st	r0, r1, 4096
-	st.d	r0, r1, 0
-	st.d	r0, r1, 4096
-	;; unscaled
-	st.b	  r0, r1, r2
-	st.h	  r2, r3, r4
-	st	  r4, r5, r6
-	st.d	  r5, r6, r7
-	st.b.usr  r6, r7, r8
-	st.h.usr  r8, r9, r1
-	st.usr	  r1, r2, r3
-	st.d.usr  r2, r3, r4
-	;; scaled
-	st.b	  r0, r1[r2]
-	st.h	  r2, r3[r4]
-	st	  r4, r5[r6]
-	st.d	  r5, r6[r7]
-	st.b.usr  r6, r7[r8]
-	st.h.usr  r8, r9[r1]
-	st.usr	  r1, r2[r3]
-	st.d.usr  r2, r3[r4]
-
-	;; store to control register
-
-	stcr r0, cr10
-
-	;; integer subtract
-
-	sub     r0, r1, r2
-	sub.ci  r1, r2, r3
-	sub.co  r2, r3, r4
-	sub.cio r3, r4, r5
-	sub     r4, r5, 0
-	sub	r4, r5, 4096
-
-	;; unsigned integer subtract
-
-	subu	 r0, r1, r2
-	subu.ci  r1, r2, r3
-	subu.co  r3, r4, r5
-	subu.cio r4, r5, r6
-	subu	 r5, r6, 0
-	subu	 r5, r6, 4096
-
-	;; trap on bit clear
-
-	tb0	0, r10, 10
-	tb0	31, r11, 10
-
-	;; trap on bit set
-
-	tb1	0, r10, 10
-	tb1	31, r11, 10
-
-	;; trap on bounds check
-
-	tbnd r0, r1
-	tbnd r7, 0
-	tbnd r7, 4096
-
-	;; conditional trap
-
-	tcnd  eq0, r10, 12
-	tcnd  ne0, r9, 12
-	tcnd  gt0, r8, 7
-	tcnd  lt0, r7, 1
-	tcnd  ge0, r6, 35
-	tcnd  le0, r5, 33
-	tcnd  10, r4, 12
-
-	;; truncate floating point to integer
-
-	trnc.ss r0, r1
-	trnc.sd r1, r3
-
-	;; exchange control register
-
-	xcr r0, r3, cr10
-
-	;; exchange register with memory
-
-	;; FIXME: these should assemble!
-	;; xmem.bu    r0, r1, 0
-	;; xmem.bu     r0, r1, 10
-	;; xmem	    r0, r1, 0
-	;; xmem	    r1, r2, 4096
-	xmem.bu     r0, r1, r2
-	xmem	    r1, r2, r3
-	xmem.bu.usr r4, r5, r6
-	xmem.usr    r5, r6, r7
-	xmem.bu     r2, r3[r4]
-	xmem	    r3, r4[r5]
-	xmem.bu.usr r4, r5[r9]
-	xmem.usr    r5, r6[r10]
-
-	;; logical exclusive or
-
-	xor   r0, r1, r2
-	xor.c r1, r2, r3
-	xor   r2, r3, 0
-	xor   r2, r4, 4096
-	xor.u r1, r2, 0
-	xor.u r2, r3, 4096
-	
diff --git a/gas/testsuite/gas/m88k/init.d b/gas/testsuite/gas/m88k/init.d
deleted file mode 100644
index 20838f27b37e..000000000000
--- a/gas/testsuite/gas/m88k/init.d
+++ /dev/null
@@ -1,10 +0,0 @@
-#objdump: -d --prefix-addresses
-#name: padding of .init section
-
-.*: +file format .*
-
-Disassembly of section .init:
-00000000 <.init> subu        r31,r31,0x10
-00000004 <.init\+0x4> st          r13,r31,0x20
-00000008 <.init\+0x8> or          r0,r0,r0
-0000000c <.init\+0xc> or          r0,r0,r0
diff --git a/gas/testsuite/gas/m88k/init.s b/gas/testsuite/gas/m88k/init.s
deleted file mode 100644
index 29681cb1e229..000000000000
--- a/gas/testsuite/gas/m88k/init.s
+++ /dev/null
@@ -1,5 +0,0 @@
-; Test proper padding of the .init section
-	section	 .init,"x"
-	align	 4
-	subu	 r31,r31,16
-	st	 r13,r31,32
diff --git a/gas/testsuite/gas/m88k/m88k.exp b/gas/testsuite/gas/m88k/m88k.exp
deleted file mode 100644
index 9bc3dbf3aa39..000000000000
--- a/gas/testsuite/gas/m88k/m88k.exp
+++ /dev/null
@@ -1,26 +0,0 @@
-# Copyright 2001 Free Software Foundation, Inc.
-
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
-# Tests for m88k svr3 targets
-
-if { [istarget m88*-*-sysv3] || [istarget m88*-*-coff* ] } then {
-    set testname "Proper padding of .init section"
-    run_dump_test init
-    set testname "All m88k instructions assemble and disassemble"
-    run_dump_test allinsn
-}
-
-if [info exists errorInfo] then { unset errorInfo }
diff --git a/gas/testsuite/gas/macros/badarg.l b/gas/testsuite/gas/macros/badarg.l
new file mode 100644
index 000000000000..cbf242999104
--- /dev/null
+++ b/gas/testsuite/gas/macros/badarg.l
@@ -0,0 +1,15 @@
+.*: Assembler messages:
+.*:1: Error: .*
+.*:4: Error: .*
+.*:7: Error: .*
+.*:10: Error: .*
+.*:13: Error: .*
+.*:16: Error: .*
+.*:19: Error: .*
+.*:25: Error: .*
+.*:30: Error: .*
+.*:38: Error: .*
+.*:41: Error: .*
+.*:44: Warning: .*
+.*:47: Error: .*
+.*:49: Error: .*
diff --git a/gas/testsuite/gas/macros/badarg.s b/gas/testsuite/gas/macros/badarg.s
new file mode 100644
index 000000000000..716a98f1adb0
--- /dev/null
+++ b/gas/testsuite/gas/macros/badarg.s
@@ -0,0 +1,50 @@
+	.macro
+	.endm
+
+	.macro	,arg1
+	.endm
+
+	.macro	m1,
+	.endm
+
+	.macro	m2,,
+	.endm
+
+	.macro	m3,arg1,
+	.endm
+
+	.macro	m4,,arg2
+	.endm
+
+	.macro	m5,arg,arg
+	.endm
+
+	.altmacro
+
+	.macro	m6,arg
+	 local arg
+	.endm
+
+	.macro	m7
+	 local arg
+	 local arg
+	.endm
+
+	m6
+	m7
+
+	.noaltmacro
+
+	.macro m8, arg :
+	.endm
+
+	.macro m9, arg : qual
+	.endm
+
+	.macro m10, arg : req = def
+	.endm
+
+	m10
+
+	.macro m11, arg1 : vararg, arg2
+	.endm
diff --git a/gas/testsuite/gas/macros/dot.l b/gas/testsuite/gas/macros/dot.l
new file mode 100644
index 000000000000..980de4f1d1cf
--- /dev/null
+++ b/gas/testsuite/gas/macros/dot.l
@@ -0,0 +1,22 @@
+.*: Assembler messages:
+.*:[1-9][0-9]*: Warning: attempt to redefine pseudo-op .\.macro. ignored
+.*:27: Error: unknown pseudo-op: .\.xyz.
+.*:28: Error: .*
+#...
+[ 	]*[1-9][0-9]*[ 	]+m 4, 2
+[ 	]*[1-9][0-9]*[ 	]+> \.data
+[ 	]*[1-9][0-9]*[ 	]+> labelA:labelB:labelC:labelD:x\.y\.z 4\+2
+[ 	]*[1-9][0-9]*[ 	]+>> \.align 4
+[ 	]*[1-9][0-9]*[ 	]+\?+[ 	]+0606[ 	]+>> \.byte 4\+2,4\+2
+[ 	]*[1-9][0-9]*[ 	]+\?+[ 	]+0000[ 	]+> \.skip 2
+[ 	]*[1-9][0-9]*[ 	]+> labelZ:labelY:labelX:labelW:\.xyz 4-2
+[ 	]*[1-9][0-9]*[ 	]+>> \.align 8
+[ 	]*[1-9][0-9]*[ 	]+\?+[ 	]+0202[ 	]+>> \.byte 4-2,4-2
+[ 	]*[1-9][0-9]*[ 	]+\?+[ 	]+0000 ?0000[ 	]+> \.skip 4\*2
+[ 	]*[1-9][0-9]*[ 	]+0000 ?0000[ 	]*
+[ 	]*[1-9][0-9]*[ 	]+> label9:label8:label7:label6:
+[ 	]*[1-9][0-9]*[ 	]+
+[ 	]*[1-9][0-9]*[ 	]+\.purgem \.xyz, x\.y\.z
+[ 	]*[1-9][0-9]*[ 	]+\.xyz 0
+[ 	]*[1-9][0-9]*[ 	]+(\?+[0 	]+)?x\.y\.z 0
+#pass
diff --git a/gas/testsuite/gas/macros/dot.s b/gas/testsuite/gas/macros/dot.s
new file mode 100644
index 000000000000..72ce972a2fb8
--- /dev/null
+++ b/gas/testsuite/gas/macros/dot.s
@@ -0,0 +1,28 @@
+ .altmacro
+
+ .macro x.y.z val
+  .align 4
+  .byte val, val
+ .endm
+
+ .macro .xyz val
+  .align 8
+  .byte val, val
+ .endm
+
+ .macro .macro
+ .endm
+
+label1:label2 : label3 :label4: m: .macro arg.1, arg.2
+ .data
+labelA:labelB : labelC :labelD: x.y.z arg.1+arg.2
+ .skip arg.2
+labelZ:labelY : labelX :labelW: .xyz arg.1-arg.2
+ .skip arg.1*arg.2
+label9:label8 : label7 :label6: .endm
+
+m 4, 2
+
+ .purgem .xyz, x.y.z
+ .xyz 0
+x.y.z 0
diff --git a/gas/testsuite/gas/macros/end.l b/gas/testsuite/gas/macros/end.l
new file mode 100644
index 000000000000..1675ff818367
--- /dev/null
+++ b/gas/testsuite/gas/macros/end.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:1: Warning: \.endm .* \.macro
+.*:2: Warning: \.endr .* (\.rept|\.irpc?).*(\.rept|\.irpc?).*(\.rept|\.irpc?)
diff --git a/gas/testsuite/gas/macros/end.s b/gas/testsuite/gas/macros/end.s
new file mode 100644
index 000000000000..3a136c604ab4
--- /dev/null
+++ b/gas/testsuite/gas/macros/end.s
@@ -0,0 +1,2 @@
+	.endm
+	.endr
diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp
index 19568d90120b..e175ad9a53ec 100644
--- a/gas/testsuite/gas/macros/macros.exp
+++ b/gas/testsuite/gas/macros/macros.exp
@@ -1,5 +1,18 @@
 # Run some tests of gas macros.
 
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "macros $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
 if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
     run_dump_test test1
 }
@@ -13,11 +26,17 @@ run_dump_test test3
 if { ![istarget *c54x*-*-*] && ![istarget *c4x*-*-*] } {
     run_dump_test irp
     run_dump_test rept
+    run_dump_test repeat
+    run_dump_test vararg
 }
 
-
 gas_test_error "err.s" "" "macro infinite recursion"
 
+# The tic4x-coff target fails the next test because it defines '&'
+# as its line separator character, so the expression "(0 & TFLAG_C)"
+# becomes divided up into two lines and the parser complains about
+# a missing closing parenthesis for the first line.
+setup_xfail "tic4x*-*"
 gas_test "and.s" "" "" "logical and in macro definition"
 
 case $target_triplet in {
@@ -31,12 +50,13 @@ case $target_triplet in {
 
 if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
     # FIXME: Due to macro mishandling of ONLY_STANDARD_ESCAPES.
-    setup_xfail "avr-*" "cris-*"
+    setup_xfail "avr-*" "cris-*" "crisv32-*" "msp430-*"
 
     # These fail due to NO_STRING_ESCAPES
     setup_xfail "powerpc*-*-aix*" "powerpc*-*-beos*" "powerpc*-*-macos*"
-    setup_xfail "powerpc*-*-mpw*" "powerpc*-*-pe" "powerpc*-*-*win*"
+    setup_xfail "powerpc*-*-pe" "powerpc*-*-*win*"
     setup_xfail "rs6000-*-*"
+    setup_xfail "z80-*-*"
 
     # FIXME: Due to difference in what "consecutive octets" means.
     setup_xfail "*c4x*-*-*" "*c54x*-*"
@@ -47,3 +67,24 @@ run_dump_test app1
 run_dump_test app2
 run_dump_test app3
 run_dump_test app4
+
+run_list_test badarg ""
+case $target_triplet in {
+    { *c54x*-*-* } { }
+    { *c4x*-*-* } { }
+    { h8500-*-* } { }
+    { m68*-*-* } { }
+    { m88*-*-* } { }
+    { mmix-* } { }
+    { z80-* } { }
+    default { run_list_test dot "-alm" }
+}
+run_list_test end ""
+run_list_test purge "--hash-size=8000"
+run_list_test redef ""
+
+# This test is valid only when '!' is not a comment character
+# (it is allowed to be a line comment character).
+if [string match "" [lindex [gas_run ../all/excl.s "-o /dev/null" ""] 0]] {
+    run_dump_test paren
+}
diff --git a/gas/testsuite/gas/macros/paren.d b/gas/testsuite/gas/macros/paren.d
new file mode 100644
index 000000000000..e4c097567076
--- /dev/null
+++ b/gas/testsuite/gas/macros/paren.d
@@ -0,0 +1,9 @@
+#as: -f
+#objdump: -s -j .data
+#name parenthesized macro arguments
+
+.*: .*
+
+Contents of section .data:
+ 0000 01000202 020402.. ........ ........  ................
+#pass
diff --git a/gas/testsuite/gas/macros/paren.s b/gas/testsuite/gas/macros/paren.s
new file mode 100644
index 000000000000..f8462e581cad
--- /dev/null
+++ b/gas/testsuite/gas/macros/paren.s
@@ -0,0 +1,12 @@
+ .data
+ .macro m x
+ .byte (\x)
+ .endm
+
+	m	(1)
+	m	(!1)
+	m	(1)+(1)
+	m	1+(1)
+	m	(1 + 1)
+	m	(1 + 1)*(1 + 1)
+	m	(! 0)+(! 0)
diff --git a/gas/testsuite/gas/macros/purge.l b/gas/testsuite/gas/macros/purge.l
new file mode 100644
index 000000000000..97e097b052cd
--- /dev/null
+++ b/gas/testsuite/gas/macros/purge.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*:12: Error: .*
+#...
+.*:13: Error: .*
+#...
+.*:14: Error: .*
+#...
+.*:15: Error: .*
+#...
+.*:16: Warning: .*
+.*:17: Warning: .*
diff --git a/gas/testsuite/gas/macros/purge.s b/gas/testsuite/gas/macros/purge.s
new file mode 100644
index 000000000000..f1e09f68f3b1
--- /dev/null
+++ b/gas/testsuite/gas/macros/purge.s
@@ -0,0 +1,42 @@
+ .data
+ .macro MACRO1
+ .endm
+ .macro macro2
+ .endm
+	MACRO1
+	MACRO2
+	macro1
+	macro2
+ .purgem MACRO1
+ .purgem macro2
+	MACRO1
+	MACRO2
+	macro1
+	macro2
+ .purgem macro1
+ .purgem MACRO2
+ .macro macro1
+ .endm
+ .macro MACRO2
+ .endm
+	MACRO1
+	MACRO2
+	macro1
+	macro2
+ .purgem MACRO1
+ .purgem macro2
+
+ .irpc a,ABCDEFGHIJKLMNOPQRSTUVWXYZ
+  .irpc b,ABCDEFGHIJKLMNOPQRSTUVWXYZ
+   .irpc c,ABCDEFGHIJKLMNOPQRSTUVWXYZ
+    .irpc d,ABCDEFGHIJKLMNOPQRSTUVWXYZ
+     .macro _\a\b\c\d arg1=0, arg2=0
+      .if \arg1 + \arg2
+       .purgem _\a\b\c\d
+      .endif
+     .endm
+	_\a\b\c\d 1, 2
+    .endr
+   .endr
+  .endr
+ .endr
diff --git a/gas/testsuite/gas/macros/redef.l b/gas/testsuite/gas/macros/redef.l
new file mode 100644
index 000000000000..a97cb3d83bfa
--- /dev/null
+++ b/gas/testsuite/gas/macros/redef.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:3: Error: .*
diff --git a/gas/testsuite/gas/macros/redef.s b/gas/testsuite/gas/macros/redef.s
new file mode 100644
index 000000000000..0b3290bf5808
--- /dev/null
+++ b/gas/testsuite/gas/macros/redef.s
@@ -0,0 +1,4 @@
+	.macro m
+	.endm
+	.macro m
+	.endm
diff --git a/gas/testsuite/gas/macros/repeat.d b/gas/testsuite/gas/macros/repeat.d
new file mode 100644
index 000000000000..272e441d02c6
--- /dev/null
+++ b/gas/testsuite/gas/macros/repeat.d
@@ -0,0 +1,43 @@
+#objdump: -r
+#name: nested irp/irpc/rept
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR .*
+OFFSET[ 	]+TYPE[ 	]+VALUE.*
+0+00[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irp_19
+0+04[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irp_18
+0+08[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irp_29
+0+0c[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irp_28
+0+10[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irpc_19
+0+14[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irpc_18
+0+18[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irpc_29
+0+1c[ 	]+[a-zA-Z0-9_]+[ 	]+irp_irpc_28
+0+20[ 	]+[a-zA-Z0-9_]+[ 	]+irp_rept_1
+0+24[ 	]+[a-zA-Z0-9_]+[ 	]+irp_rept_1
+0+28[ 	]+[a-zA-Z0-9_]+[ 	]+irp_rept_2
+0+2c[ 	]+[a-zA-Z0-9_]+[ 	]+irp_rept_2
+0+30[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irp_19
+0+34[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irp_18
+0+38[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irp_29
+0+3c[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irp_28
+0+40[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irpc_19
+0+44[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irpc_18
+0+48[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irpc_29
+0+4c[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_irpc_28
+0+50[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_rept_1
+0+54[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_rept_1
+0+58[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_rept_2
+0+5c[ 	]+[a-zA-Z0-9_]+[ 	]+irpc_rept_2
+0+60[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irp_9
+0+64[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irp_8
+0+68[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irp_9
+0+6c[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irp_8
+0+70[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irpc_9
+0+74[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irpc_8
+0+78[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irpc_9
+0+7c[ 	]+[a-zA-Z0-9_]+[ 	]+rept_irpc_8
+0+80[ 	]+[a-zA-Z0-9_]+[ 	]+rept_rept
+0+84[ 	]+[a-zA-Z0-9_]+[ 	]+rept_rept
+0+88[ 	]+[a-zA-Z0-9_]+[ 	]+rept_rept
+0+8c[ 	]+[a-zA-Z0-9_]+[ 	]+rept_rept
diff --git a/gas/testsuite/gas/macros/repeat.s b/gas/testsuite/gas/macros/repeat.s
new file mode 100644
index 000000000000..70329f720c15
--- /dev/null
+++ b/gas/testsuite/gas/macros/repeat.s
@@ -0,0 +1,53 @@
+	.irp	param1,1,2
+	 .irp	param2,9,8
+	  .long	irp_irp_\param1\param2
+	 .endr
+	.endr
+
+	.irp	param1,1,2
+	 .irpc	param2,98
+	  .long	irp_irpc_\param1\param2
+	 .endr
+	.endr
+
+	.irp	param1,1,2
+	 .rept	2
+	  .long	irp_rept_\param1
+	 .endr
+	.endr
+
+	.irpc	param1,12
+	 .irp	param2,9,8
+	  .long	irpc_irp_\param1\param2
+	 .endr
+	.endr
+
+	.irpc	param1,12
+	 .irpc	param2,98
+	  .long	irpc_irpc_\param1\param2
+	 .endr
+	.endr
+
+	.irpc	param1,12
+	 .rept	2
+	  .long	irpc_rept_\param1
+	 .endr
+	.endr
+
+	.rept	2
+	 .irp	param2,9,8
+	  .long	rept_irp_\param2
+	 .endr
+	.endr
+
+	.rept	2
+	 .irpc	param2,98
+	  .long	rept_irpc_\param2
+	 .endr
+	.endr
+
+	.rept	2
+	 .rept	2
+	  .long	rept_rept
+	 .endr
+	.endr
diff --git a/gas/testsuite/gas/macros/strings.d b/gas/testsuite/gas/macros/strings.d
index 4fabca2212da..f06263fd9e29 100644
--- a/gas/testsuite/gas/macros/strings.d
+++ b/gas/testsuite/gas/macros/strings.d
@@ -1,6 +1,5 @@
 #objdump: -s -j .data
 #name: strings
-
 .*: .*
 
 Contents of section .data:
diff --git a/gas/testsuite/gas/macros/vararg.d b/gas/testsuite/gas/macros/vararg.d
new file mode 100644
index 000000000000..4b943fd18fac
--- /dev/null
+++ b/gas/testsuite/gas/macros/vararg.d
@@ -0,0 +1,13 @@
+#objdump: -r
+#name: macro vararg
+
+.*: +file format .*
+
+RELOCATION RECORDS FOR .*
+OFFSET[ 	]+TYPE[ 	]+VALUE.*
+0+00[ 	]+[a-zA-Z0-9_]+[ 	]+foo1
+0+04[ 	]+[a-zA-Z0-9_]+[ 	]+foo2
+0+08[ 	]+[a-zA-Z0-9_]+[ 	]+foo3
+0+0c[ 	]+[a-zA-Z0-9_]+[ 	]+foo4
+0+10[ 	]+[a-zA-Z0-9_]+[ 	]+foo5
+0+14[ 	]+[a-zA-Z0-9_]+[ 	]+foo6
diff --git a/gas/testsuite/gas/macros/vararg.s b/gas/testsuite/gas/macros/vararg.s
new file mode 100644
index 000000000000..4bdf99a263be
--- /dev/null
+++ b/gas/testsuite/gas/macros/vararg.s
@@ -0,0 +1,10 @@
+	.macro	v1 arg1 : req, args : vararg
+	.long	foo\arg1
+	.ifnb	\args
+	v1	\args
+	.endif
+	.endm
+
+	v1	1
+	v1	2, 3
+	v1	4, 5, 6
diff --git a/gas/testsuite/gas/maxq10/bits.d b/gas/testsuite/gas/maxq10/bits.d
new file mode 100644
index 000000000000..b5f295ada14c
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/bits.d
@@ -0,0 +1,56 @@
+#objdump: -dw
+#name: call operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <foo>:
+   0:	0a ea [ 	]*MOVE C,Acc.0
+   2:	1a ea [ 	]*MOVE C,Acc.1
+   4:	2a ea [ 	]*MOVE C,Acc.2
+   6:	3a ea [ 	]*MOVE C,Acc.3
+   8:	4a ea [ 	]*MOVE C,Acc.4
+   a:	5a ea [ 	]*MOVE C,Acc.5
+   c:	6a ea [ 	]*MOVE C,Acc.6
+   e:	7a ea [ 	]*MOVE C,Acc.7
+  10:	0a da [ 	]*MOVE C,#0
+  12:	1a da [ 	]*MOVE C,#1
+  14:	0a fa  [ 	]*MOVE Acc.0,C
+  16:	1a fa  [ 	]*MOVE Acc.1,C
+  18:	2a fa [ 	]*MOVE Acc.2,C
+  1a:	3a fa  [ 	]*MOVE Acc.3,C
+  1c:	4a fa [ 	]*MOVE Acc.4,C
+  1e:	5a fa  [ 	]*MOVE Acc.5,C
+  20:	6a fa  [ 	]*MOVE Acc.6,C
+  22:	7a fa  [ 	]*MOVE Acc.7,C
+  24:	2a da [ 	]*CPL C
+  26:	0a 9a [ 	]*AND Acc.0
+  28:	1a 9a [ 	]*AND Acc.1
+  2a:	2a 9a [ 	]*AND Acc.2
+  2c:	3a 9a [ 	]*AND Acc.3
+  2e:	4a 9a [ 	]*AND Acc.4
+  30:	5a 9a [ 	]*AND Acc.5
+  32:	6a 9a [ 	]*AND Acc.6
+  34:	7a 9a [ 	]*AND Acc.7
+  36:	0a aa [ 	]*OR Acc.0
+  38:	1a aa [ 	]*OR Acc.1
+  3a:	2a aa [ 	]*OR Acc.2
+  3c:	3a aa [ 	]*OR Acc.3
+  3e:	4a aa [ 	]*OR Acc.4
+  40:	5a aa [ 	]*OR Acc.5
+  42:	6a aa [ 	]*OR Acc.6
+  44:	7a aa [ 	]*OR Acc.7
+  46:	0a ba [ 	]*XOR Acc.0
+  48:	1a ba [ 	]*XOR Acc.1
+  4a:	2a ba [ 	]*XOR Acc.2
+  4c:	3a ba [ 	]*XOR Acc.3
+  4e:	4a ba [ 	]*XOR Acc.4
+  50:	5a ba [ 	]*XOR Acc.5
+  52:	6a ba [ 	]*XOR Acc.6
+  54:	7a ba [ 	]*XOR Acc.7
+  56:	88 97 [ 	]*MOVE C , SC.1
+  58:	68 87 [ 	]*MOVE C , IMR.0
+  5a:	58 87 [ 	]*MOVE C , IC.0
+  5c:	48 87 [ 	]*MOVE C , PSF.0
+	...
diff --git a/gas/testsuite/gas/maxq10/bits.s b/gas/testsuite/gas/maxq10/bits.s
new file mode 100644
index 000000000000..075fb7f3e399
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/bits.s
@@ -0,0 +1,52 @@
+;# bits.s

+;# checks all the bit operations in MAXQ10

+

+.text

+foo:

+ MOVE C, ACC.0	

+ MOVE C, ACC.1

+ MOVE C, ACC.2

+ MOVE C, ACC.3

+ MOVE C, ACC.4

+ MOVE C, ACC.5

+ MOVE C, ACC.6

+ MOVE C, ACC.7		;8 bits on a MAXQ10 machine

+ MOVE C, #0

+ MOVE C, #1

+ MOVE ACC.0, C	

+ MOVE ACC.1, C 

+ MOVE ACC.2, C

+ MOVE ACC.3, C

+ MOVE ACC.4, C

+ MOVE ACC.5, C

+ MOVE ACC.6, C

+ MOVE ACC.7, C		;8 bits on a MAXQ10 machine

+ CPL C

+ AND ACC.0	;AND with carry

+ AND ACC.1	

+ AND ACC.2	

+ AND ACC.3	

+ AND ACC.4	

+ AND ACC.5	

+ AND ACC.6	

+ AND ACC.7	

+ OR ACC.0	;OR with carry

+ OR ACC.1	

+ OR ACC.2	

+ OR ACC.3	

+ OR ACC.4	

+ OR ACC.5	

+ OR ACC.6	

+ OR ACC.7	

+ XOR ACC.0	;XOR with carry

+ XOR ACC.1	

+ XOR ACC.2	

+ XOR ACC.3	

+ XOR ACC.4	

+ XOR ACC.5	

+ XOR ACC.6	

+ XOR ACC.7	

+ MOVE C, SC.1

+ MOVE C, IMR.0

+ MOVE C, IC.0

+ MOVE C, PSF.0		;move program status flag bit 0

diff --git a/gas/testsuite/gas/maxq10/call.d b/gas/testsuite/gas/maxq10/call.d
new file mode 100644
index 000000000000..2c3299462b53
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/call.d
@@ -0,0 +1,38 @@
+#objdump:  -dw

+#name: call operations

+

+.*: +file format .*

+

+Disassembly of section .text:

+0+000 <foo>:

+   0:	02 3d [ 	]*CALL  #02h

+   2:	04 0b [ 	]*MOVE  PFX\[0\], #04h

+   4:	28 3d [ 	]*CALL  #28h

+0+6 <SmallCall>:

+   6:	0d 8c [ 	]*RET 

+   8:	0d ac [ 	]*RET C

+   a:	0d 9c [ 	]*RET Z

+   c:	0d dc [ 	]*RET NZ

+   e:	0d cc [ 	]*RET S

+  10:	8d 8c [ 	]*RETI 

+  12:	8d ac [ 	]*RETI C

+  14:	8d 9c [ 	]*RETI Z

+  16:	8d dc [ 	]*RETI NZ

+  18:	8d cc [ 	]*RETI S

+  1a:	10 7d [ 	]*MOVE  LC\[1\], #10h

+0+1c <LoopTop>:

+  1c:	ff 3d [ 	]*CALL  #ffh

+  1e:	fe 5d [ 	]*DJNZ  LC\[1\], #feh

+  20:	10 7d [ 	]*MOVE  LC\[1\], #10h

+0+22 <LoopTop1>:

+  22:	ff 3d [ 	]*CALL  #ffh

+	...

+ 424:	00 0b [ 	]*MOVE  PFX\[0\], #00h

+ 426:	1c 5d [ 	]*DJNZ  LC\[1\], #1ch

+0+428 <LongCall>:

+ 428:	8d 8c [ 	]*RETI 

+ 42a:	8d ac [ 	]*RETI C

+ 42c:	8d 9c [ 	]*RETI Z

+ 42e:	8d dc [ 	]*RETI NZ

+ 430:	8d cc [ 	]*RETI S

+	...

diff --git a/gas/testsuite/gas/maxq10/call.s b/gas/testsuite/gas/maxq10/call.s
new file mode 100644
index 000000000000..f8b4c0f155f8
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/call.s
@@ -0,0 +1,32 @@
+;# calls.s
+;# check program flow instruction involving CALL & RET in MAXQ10
+.text
+foo:
+	Call SmallCall
+	Call LongCall
+SmallCall:
+	RET
+	RET C
+	RET Z
+	RET NZ
+	RET S 
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
+	MOVE LC[1], #10h
+LoopTop:
+	Call LoopTop
+	DJNZ LC[1], LoopTop
+	MOVE LC[1], #10h
+LoopTop1:
+	Call LoopTop1
+	.fill 0x200, 2, 0 
+	DJNZ LC[1], LoopTop
+LongCall:
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
diff --git a/gas/testsuite/gas/maxq10/data.s b/gas/testsuite/gas/maxq10/data.s
new file mode 100644
index 000000000000..36176c60e138
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data.s
@@ -0,0 +1,977 @@
+;# data.s	
+;# checks all the data transfer instructions for MAXQ10
+foo:
+;	XCH			; Not in MAXQ10
+	XCHN
+	MOVE NUL, #01h
+	MOVE NUL, AP
+	MOVE NUL, APC
+	MOVE NUL, PSF
+	MOVE NUL, IC
+	MOVE NUL, IMR
+	MOVE NUL, SC
+	MOVE NUL, IIR
+	MOVE NUL, CKCN
+	MOVE NUL, WDCN
+	MOVE NUL, A[0]		;Just Check two boundary conditions
+	MOVE NUL, A[15]   
+	MOVE NUL, ACC
+	MOVE NUL, A[AP]
+	MOVE NUL, IP
+	MOVE NUL, @SP--
+	MOVE NUL, SP
+	MOVE NUL, IV
+	MOVE NUL, LC[0]
+	MOVE NUL, LC[1]
+	MOVE NUL, @BP[OFFS++]
+	MOVE NUL, @BP[OFFS--]
+	MOVE NUL, OFFS
+	MOVE NUL, DPC
+	MOVE NUL, GR
+	MOVE NUL, GRL
+	MOVE NUL, BP
+	MOVE NUL, GRS
+	MOVE NUL, GRH
+	MOVE NUL, GRXL
+	MOVE NUL, FP
+	MOVE NUL, @DP[0]	
+	MOVE NUL, @DP[1]	
+	MOVE NUL, @DP[0]++		
+	MOVE NUL, @DP[1]++
+	MOVE NUL, @DP[0]--
+	MOVE NUL, @DP[1]--
+	MOVE AP, #01h
+	MOVE AP, APC
+	MOVE AP, PSF
+	MOVE AP, IC
+	MOVE AP, IMR
+	MOVE AP, SC
+	MOVE AP, IIR
+	MOVE AP, CKCN
+	MOVE AP, WDCN
+	MOVE AP, A[0]		;Just Check two boundary conditions
+	MOVE AP, A[15]   
+	MOVE AP, ACC
+	MOVE AP, A[AP]
+	MOVE AP, IP
+	MOVE AP, @SP--
+	MOVE AP, SP
+	MOVE AP, IV
+	MOVE AP, LC[0]
+	MOVE AP, LC[1]
+	MOVE AP, @BP[OFFS++]
+	MOVE AP, @BP[OFFS--]
+	MOVE AP, OFFS
+	MOVE AP, DPC
+	MOVE AP, GR
+	MOVE AP, GRL
+	MOVE AP, BP
+	MOVE AP, GRS
+	MOVE AP, GRH
+	MOVE AP, GRXL
+	MOVE AP, FP
+	MOVE AP, @DP[0]	
+	MOVE AP, @DP[1]	
+	MOVE AP, @DP[0]++		
+	MOVE AP, @DP[1]++
+	MOVE AP, @DP[0]--
+	MOVE AP, @DP[1]--
+	MOVE APC, #01h
+	MOVE APC, AP
+	MOVE APC, PSF
+	MOVE APC, IC
+	MOVE APC, IMR
+	MOVE APC, SC
+	MOVE APC, IIR
+	MOVE APC, CKCN
+	MOVE APC, WDCN
+	MOVE APC, A[0]		;Just Check two boundary conditions
+	MOVE APC, A[15]   
+	MOVE APC, ACC
+	MOVE APC, A[AP]
+	MOVE APC, IP
+	MOVE APC, @SP--
+	MOVE APC, SP
+	MOVE APC, IV
+	MOVE APC, LC[0]
+	MOVE APC, LC[1]
+	MOVE APC, @BP[OFFS++]
+	MOVE APC, @BP[OFFS--]
+	MOVE APC, OFFS
+	MOVE APC, DPC
+	MOVE APC, GR
+	MOVE APC, GRL
+	MOVE APC, BP
+	MOVE APC, GRS
+	MOVE APC, GRH
+	MOVE APC, GRXL
+	MOVE APC, FP
+	MOVE APC, @DP[0]	
+	MOVE APC, @DP[1]	
+	MOVE APC, @DP[0]++		
+	MOVE APC, @DP[1]++
+	MOVE APC, @DP[0]--
+	MOVE APC, @DP[1]--
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/data2.d b/gas/testsuite/gas/maxq10/data2.d
new file mode 100644
index 000000000000..d0fc20528191
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data2.d
@@ -0,0 +1,459 @@
+#objdump: -dw
+#name: 2nd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 48 [ 	]*MOVE  PSF, #01h
+   2:	08 c8 [ 	]*MOVE  PSF, AP
+   4:	18 c8 [ 	]*MOVE  PSF, APC
+   6:	58 c8 [ 	]*MOVE  PSF, IC
+   8:	68 c8 [ 	]*MOVE  PSF, IMR
+   a:	88 c8 [ 	]*MOVE  PSF, SC
+   c:	b8 c8 [ 	]*MOVE  PSF, IIR
+   e:	e8 c8 [ 	]*MOVE  PSF, CKCN
+  10:	f8 c8 [ 	]*MOVE  PSF, WDCN
+  12:	09 c8 [ 	]*MOVE  PSF, A\[0\]
+  14:	f9 c8 [ 	]*MOVE  PSF, A\[15\]
+  16:	0a c8 [ 	]*MOVE  PSF, ACC
+  18:	1a c8 [ 	]*MOVE  PSF, A\[AP\]
+  1a:	0c c8 [ 	]*MOVE  PSF, IP
+  1c:	0d c8 [ 	]*MOVE  PSF, @SP\-\-
+  1e:	1d c8 [ 	]*MOVE  PSF, SP
+  20:	2d c8 [ 	]*MOVE  PSF, IV
+  22:	6d c8 [ 	]*MOVE  PSF, LC\[0\]
+  24:	7d c8 [ 	]*MOVE  PSF, LC\[1\]
+  26:	1e c8 [ 	]*MOVE  PSF, @BP\[OFFS\+\+\]
+  28:	2e c8 [ 	]*MOVE  PSF, @BP\[OFFS\-\-\]
+  2a:	3e c8 [ 	]*MOVE  PSF, OFFS
+  2c:	4e c8 [ 	]*MOVE  PSF, DPC
+  2e:	5e c8 [ 	]*MOVE  PSF, GR
+  30:	6e c8 [ 	]*MOVE  PSF, GRL
+  32:	7e c8 [ 	]*MOVE  PSF, BP
+  34:	8e c8 [ 	]*MOVE  PSF, GRS
+  36:	9e c8 [ 	]*MOVE  PSF, GRH
+  38:	ae c8 [ 	]*MOVE  PSF, GRXL
+  3a:	be c8 [ 	]*MOVE  PSF, FP
+  3c:	0f c8 [ 	]*MOVE  PSF, @DP\[0\]
+  3e:	4f c8 [ 	]*MOVE  PSF, @DP\[1\]
+  40:	1f c8 [ 	]*MOVE  PSF, @DP\[0\]\+\+
+  42:	5f c8 [ 	]*MOVE  PSF, @DP\[1\]\+\+
+  44:	2f c8 [ 	]*MOVE  PSF, @DP\[0\]\-\-
+  46:	6f c8 [ 	]*MOVE  PSF, @DP\[1\]\-\-
+  48:	01 58 [ 	]*MOVE  IC, #01h
+  4a:	08 d8 [ 	]*MOVE  IC, AP
+  4c:	18 d8 [ 	]*MOVE  IC, APC
+  4e:	48 d8 [ 	]*MOVE  IC, PSF
+  50:	68 d8 [ 	]*MOVE  IC, IMR
+  52:	88 d8 [ 	]*MOVE  IC, SC
+  54:	b8 d8 [ 	]*MOVE  IC, IIR
+  56:	e8 d8 [ 	]*MOVE  IC, CKCN
+  58:	f8 d8 [ 	]*MOVE  IC, WDCN
+  5a:	09 d8 [ 	]*MOVE  IC, A\[0\]
+  5c:	f9 d8 [ 	]*MOVE  IC, A\[15\]
+  5e:	0a d8 [ 	]*MOVE  IC, ACC
+  60:	1a d8 [ 	]*MOVE  IC, A\[AP\]
+  62:	0c d8 [ 	]*MOVE  IC, IP
+  64:	0d d8 [ 	]*MOVE  IC, @SP\-\-
+  66:	1d d8 [ 	]*MOVE  IC, SP
+  68:	2d d8 [ 	]*MOVE  IC, IV
+  6a:	6d d8 [ 	]*MOVE  IC, LC\[0\]
+  6c:	7d d8 [ 	]*MOVE  IC, LC\[1\]
+  6e:	1e d8 [ 	]*MOVE  IC, @BP\[OFFS\+\+\]
+  70:	2e d8 [ 	]*MOVE  IC, @BP\[OFFS\-\-\]
+  72:	3e d8 [ 	]*MOVE  IC, OFFS
+  74:	4e d8 [ 	]*MOVE  IC, DPC
+  76:	5e d8 [ 	]*MOVE  IC, GR
+  78:	6e d8 [ 	]*MOVE  IC, GRL
+  7a:	7e d8 [ 	]*MOVE  IC, BP
+  7c:	8e d8 [ 	]*MOVE  IC, GRS
+  7e:	9e d8 [ 	]*MOVE  IC, GRH
+  80:	ae d8 [ 	]*MOVE  IC, GRXL
+  82:	be d8 [ 	]*MOVE  IC, FP
+  84:	0f d8 [ 	]*MOVE  IC, @DP\[0\]
+  86:	4f d8 [ 	]*MOVE  IC, @DP\[1\]
+  88:	1f d8 [ 	]*MOVE  IC, @DP\[0\]\+\+
+  8a:	5f d8 [ 	]*MOVE  IC, @DP\[1\]\+\+
+  8c:	2f d8 [ 	]*MOVE  IC, @DP\[0\]\-\-
+  8e:	6f d8 [ 	]*MOVE  IC, @DP\[1\]\-\-
+  90:	01 68 [ 	]*MOVE  IMR, #01h
+  92:	08 e8 [ 	]*MOVE  IMR, AP
+  94:	18 e8 [ 	]*MOVE  IMR, APC
+  96:	48 e8 [ 	]*MOVE  IMR, PSF
+  98:	58 e8 [ 	]*MOVE  IMR, IC
+  9a:	88 e8 [ 	]*MOVE  IMR, SC
+  9c:	b8 e8 [ 	]*MOVE  IMR, IIR
+  9e:	e8 e8 [ 	]*MOVE  IMR, CKCN
+  a0:	f8 e8 [ 	]*MOVE  IMR, WDCN
+  a2:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+  a4:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+  a6:	0a e8 [ 	]*MOVE  IMR, ACC
+  a8:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+  aa:	0c e8 [ 	]*MOVE  IMR, IP
+  ac:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+  ae:	1d e8 [ 	]*MOVE  IMR, SP
+  b0:	2d e8 [ 	]*MOVE  IMR, IV
+  b2:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+  b4:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+  b6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+  b8:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+  ba:	3e e8 [ 	]*MOVE  IMR, OFFS
+  bc:	4e e8 [ 	]*MOVE  IMR, DPC
+  be:	5e e8 [ 	]*MOVE  IMR, GR
+  c0:	6e e8 [ 	]*MOVE  IMR, GRL
+  c2:	7e e8 [ 	]*MOVE  IMR, BP
+  c4:	8e e8 [ 	]*MOVE  IMR, GRS
+  c6:	9e e8 [ 	]*MOVE  IMR, GRH
+  c8:	ae e8 [ 	]*MOVE  IMR, GRXL
+  ca:	be e8 [ 	]*MOVE  IMR, FP
+  cc:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+  ce:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+  d0:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+  d2:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+  d4:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+  d6:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+  d8:	01 09 [ 	]*MOVE  A\[0\], #01h
+  da:	08 89 [ 	]*MOVE  A\[0\], AP
+  dc:	18 89 [ 	]*MOVE  A\[0\], APC
+  de:	48 89 [ 	]*MOVE  A\[0\], PSF
+  e0:	58 89 [ 	]*MOVE  A\[0\], IC
+  e2:	68 89 [ 	]*MOVE  A\[0\], IMR
+  e4:	88 89 [ 	]*MOVE  A\[0\], SC
+  e6:	b8 89 [ 	]*MOVE  A\[0\], IIR
+  e8:	e8 89 [ 	]*MOVE  A\[0\], CKCN
+  ea:	f8 89 [ 	]*MOVE  A\[0\], WDCN
+  ec:	0a 89 [ 	]*MOVE  A\[0\], ACC
+  ee:	1a 89 [ 	]*MOVE  A\[0\], A\[AP\]
+  f0:	0c 89 [ 	]*MOVE  A\[0\], IP
+  f2:	0d 89 [ 	]*MOVE  A\[0\], @SP\-\-
+  f4:	1d 89 [ 	]*MOVE  A\[0\], SP
+  f6:	2d 89 [ 	]*MOVE  A\[0\], IV
+  f8:	6d 89 [ 	]*MOVE  A\[0\], LC\[0\]
+  fa:	7d 89 [ 	]*MOVE  A\[0\], LC\[1\]
+  fc:	1e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\+\+\]
+  fe:	2e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\-\-\]
+ 100:	3e 89 [ 	]*MOVE  A\[0\], OFFS
+ 102:	4e 89 [ 	]*MOVE  A\[0\], DPC
+ 104:	5e 89 [ 	]*MOVE  A\[0\], GR
+ 106:	6e 89 [ 	]*MOVE  A\[0\], GRL
+ 108:	7e 89 [ 	]*MOVE  A\[0\], BP
+ 10a:	8e 89 [ 	]*MOVE  A\[0\], GRS
+ 10c:	9e 89 [ 	]*MOVE  A\[0\], GRH
+ 10e:	ae 89 [ 	]*MOVE  A\[0\], GRXL
+ 110:	be 89 [ 	]*MOVE  A\[0\], FP
+ 112:	0f 89 [ 	]*MOVE  A\[0\], @DP\[0\]
+ 114:	4f 89 [ 	]*MOVE  A\[0\], @DP\[1\]
+ 116:	1f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\+\+
+ 118:	5f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\+\+
+ 11a:	2f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\-\-
+ 11c:	6f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\-\-
+ 11e:	01 0a [ 	]*MOVE  ACC, #01h
+ 120:	08 8a [ 	]*MOVE  ACC, AP
+ 122:	18 8a [ 	]*MOVE  ACC, APC
+ 124:	48 8a [ 	]*MOVE  ACC, PSF
+ 126:	58 8a [ 	]*MOVE  ACC, IC
+ 128:	68 8a [ 	]*MOVE  ACC, IMR
+ 12a:	88 8a [ 	]*MOVE  ACC, SC
+ 12c:	b8 8a [ 	]*MOVE  ACC, IIR
+ 12e:	e8 8a [ 	]*MOVE  ACC, CKCN
+ 130:	f8 8a [ 	]*MOVE  ACC, WDCN
+ 132:	09 8a [ 	]*MOVE  ACC, A\[0\]
+ 134:	f9 8a [ 	]*MOVE  ACC, A\[15\]
+ 136:	0c 8a [ 	]*MOVE  ACC, IP
+ 138:	0d 8a [ 	]*MOVE  ACC, @SP\-\-
+ 13a:	1d 8a [ 	]*MOVE  ACC, SP
+ 13c:	2d 8a [ 	]*MOVE  ACC, IV
+ 13e:	6d 8a [ 	]*MOVE  ACC, LC\[0\]
+ 140:	7d 8a [ 	]*MOVE  ACC, LC\[1\]
+ 142:	1e 8a [ 	]*MOVE  ACC, @BP\[OFFS\+\+\]
+ 144:	2e 8a [ 	]*MOVE  ACC, @BP\[OFFS\-\-\]
+ 146:	3e 8a [ 	]*MOVE  ACC, OFFS
+ 148:	4e 8a [ 	]*MOVE  ACC, DPC
+ 14a:	5e 8a [ 	]*MOVE  ACC, GR
+ 14c:	6e 8a [ 	]*MOVE  ACC, GRL
+ 14e:	7e 8a [ 	]*MOVE  ACC, BP
+ 150:	8e 8a [ 	]*MOVE  ACC, GRS
+ 152:	9e 8a [ 	]*MOVE  ACC, GRH
+ 154:	ae 8a [ 	]*MOVE  ACC, GRXL
+ 156:	be 8a [ 	]*MOVE  ACC, FP
+ 158:	0f 8a [ 	]*MOVE  ACC, @DP\[0\]
+ 15a:	4f 8a [ 	]*MOVE  ACC, @DP\[1\]
+ 15c:	1f 8a [ 	]*MOVE  ACC, @DP\[0\]\+\+
+ 15e:	5f 8a [ 	]*MOVE  ACC, @DP\[1\]\+\+
+ 160:	2f 8a [ 	]*MOVE  ACC, @DP\[0\]\-\-
+ 162:	6f 8a [ 	]*MOVE  ACC, @DP\[1\]\-\-
+ 164:	01 0d [ 	]*MOVE  @\+\+SP, #01h
+ 166:	08 8d [ 	]*MOVE  @\+\+SP, AP
+ 168:	18 8d [ 	]*MOVE  @\+\+SP, APC
+ 16a:	48 8d [ 	]*MOVE  @\+\+SP, PSF
+ 16c:	58 8d [ 	]*MOVE  @\+\+SP, IC
+ 16e:	68 8d [ 	]*MOVE  @\+\+SP, IMR
+ 170:	88 8d [ 	]*MOVE  @\+\+SP, SC
+ 172:	b8 8d [ 	]*MOVE  @\+\+SP, IIR
+ 174:	e8 8d [ 	]*MOVE  @\+\+SP, CKCN
+ 176:	f8 8d [ 	]*MOVE  @\+\+SP, WDCN
+ 178:	09 8d [ 	]*MOVE  @\+\+SP, A\[0\]
+ 17a:	f9 8d [ 	]*MOVE  @\+\+SP, A\[15\]
+ 17c:	0a 8d [ 	]*MOVE  @\+\+SP, ACC
+ 17e:	1a 8d [ 	]*MOVE  @\+\+SP, A\[AP\]
+ 180:	0c 8d [ 	]*MOVE  @\+\+SP, IP
+ 182:	1d 8d [ 	]*MOVE  @\+\+SP, SP
+ 184:	2d 8d [ 	]*MOVE  @\+\+SP, IV
+ 186:	6d 8d [ 	]*MOVE  @\+\+SP, LC\[0\]
+ 188:	7d 8d [ 	]*MOVE  @\+\+SP, LC\[1\]
+ 18a:	1e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\+\+\]
+ 18c:	2e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\-\-\]
+ 18e:	3e 8d [ 	]*MOVE  @\+\+SP, OFFS
+ 190:	4e 8d [ 	]*MOVE  @\+\+SP, DPC
+ 192:	5e 8d [ 	]*MOVE  @\+\+SP, GR
+ 194:	6e 8d [ 	]*MOVE  @\+\+SP, GRL
+ 196:	7e 8d [ 	]*MOVE  @\+\+SP, BP
+ 198:	8e 8d [ 	]*MOVE  @\+\+SP, GRS
+ 19a:	9e 8d [ 	]*MOVE  @\+\+SP, GRH
+ 19c:	ae 8d [ 	]*MOVE  @\+\+SP, GRXL
+ 19e:	be 8d [ 	]*MOVE  @\+\+SP, FP
+ 1a0:	0f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]
+ 1a2:	4f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]
+ 1a4:	1f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\+\+
+ 1a6:	5f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\+\+
+ 1a8:	2f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\-\-
+ 1aa:	6f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\-\-
+ 1ac:	01 1d [ 	]*MOVE  SP, #01h
+ 1ae:	08 9d [ 	]*MOVE  SP, AP
+ 1b0:	18 9d [ 	]*MOVE  SP, APC
+ 1b2:	48 9d [ 	]*MOVE  SP, PSF
+ 1b4:	58 9d [ 	]*MOVE  SP, IC
+ 1b6:	68 9d [ 	]*MOVE  SP, IMR
+ 1b8:	88 9d [ 	]*MOVE  SP, SC
+ 1ba:	b8 9d [ 	]*MOVE  SP, IIR
+ 1bc:	e8 9d [ 	]*MOVE  SP, CKCN
+ 1be:	f8 9d [ 	]*MOVE  SP, WDCN
+ 1c0:	09 9d [ 	]*MOVE  SP, A\[0\]
+ 1c2:	f9 9d [ 	]*MOVE  SP, A\[15\]
+ 1c4:	0a 9d [ 	]*MOVE  SP, ACC
+ 1c6:	1a 9d [ 	]*MOVE  SP, A\[AP\]
+ 1c8:	0c 9d [ 	]*MOVE  SP, IP
+ 1ca:	2d 9d [ 	]*MOVE  SP, IV
+ 1cc:	6d 9d [ 	]*MOVE  SP, LC\[0\]
+ 1ce:	7d 9d [ 	]*MOVE  SP, LC\[1\]
+ 1d0:	1e 9d [ 	]*MOVE  SP, @BP\[OFFS\+\+\]
+ 1d2:	2e 9d [ 	]*MOVE  SP, @BP\[OFFS\-\-\]
+ 1d4:	3e 9d [ 	]*MOVE  SP, OFFS
+ 1d6:	4e 9d [ 	]*MOVE  SP, DPC
+ 1d8:	5e 9d [ 	]*MOVE  SP, GR
+ 1da:	6e 9d [ 	]*MOVE  SP, GRL
+ 1dc:	7e 9d [ 	]*MOVE  SP, BP
+ 1de:	8e 9d [ 	]*MOVE  SP, GRS
+ 1e0:	9e 9d [ 	]*MOVE  SP, GRH
+ 1e2:	ae 9d [ 	]*MOVE  SP, GRXL
+ 1e4:	be 9d [ 	]*MOVE  SP, FP
+ 1e6:	0f 9d [ 	]*MOVE  SP, @DP\[0\]
+ 1e8:	4f 9d [ 	]*MOVE  SP, @DP\[1\]
+ 1ea:	1f 9d [ 	]*MOVE  SP, @DP\[0\]\+\+
+ 1ec:	5f 9d [ 	]*MOVE  SP, @DP\[1\]\+\+
+ 1ee:	2f 9d [ 	]*MOVE  SP, @DP\[0\]\-\-
+ 1f0:	6f 9d [ 	]*MOVE  SP, @DP\[1\]\-\-
+ 1f2:	01 2d [ 	]*MOVE  IV, #01h
+ 1f4:	08 ad [ 	]*MOVE  IV, AP
+ 1f6:	18 ad [ 	]*MOVE  IV, APC
+ 1f8:	48 ad [ 	]*MOVE  IV, PSF
+ 1fa:	58 ad [ 	]*MOVE  IV, IC
+ 1fc:	68 ad [ 	]*MOVE  IV, IMR
+ 1fe:	88 ad [ 	]*MOVE  IV, SC
+ 200:	b8 ad [ 	]*MOVE  IV, IIR
+ 202:	e8 ad [ 	]*MOVE  IV, CKCN
+ 204:	f8 ad [ 	]*MOVE  IV, WDCN
+ 206:	09 ad [ 	]*MOVE  IV, A\[0\]
+ 208:	f9 ad [ 	]*MOVE  IV, A\[15\]
+ 20a:	0a ad [ 	]*MOVE  IV, ACC
+ 20c:	1a ad [ 	]*MOVE  IV, A\[AP\]
+ 20e:	0c ad [ 	]*MOVE  IV, IP
+ 210:	0d ad [ 	]*MOVE  IV, @SP\-\-
+ 212:	1d ad [ 	]*MOVE  IV, SP
+ 214:	2d ad [ 	]*MOVE  IV, IV
+ 216:	6d ad [ 	]*MOVE  IV, LC\[0\]
+ 218:	7d ad [ 	]*MOVE  IV, LC\[1\]
+ 21a:	1e ad [ 	]*MOVE  IV, @BP\[OFFS\+\+\]
+ 21c:	2e ad [ 	]*MOVE  IV, @BP\[OFFS\-\-\]
+ 21e:	3e ad [ 	]*MOVE  IV, OFFS
+ 220:	4e ad [ 	]*MOVE  IV, DPC
+ 222:	5e ad [ 	]*MOVE  IV, GR
+ 224:	6e ad [ 	]*MOVE  IV, GRL
+ 226:	7e ad [ 	]*MOVE  IV, BP
+ 228:	8e ad [ 	]*MOVE  IV, GRS
+ 22a:	9e ad [ 	]*MOVE  IV, GRH
+ 22c:	ae ad [ 	]*MOVE  IV, GRXL
+ 22e:	be ad [ 	]*MOVE  IV, FP
+ 230:	0f ad [ 	]*MOVE  IV, @DP\[0\]
+ 232:	4f ad [ 	]*MOVE  IV, @DP\[1\]
+ 234:	1f ad [ 	]*MOVE  IV, @DP\[0\]\+\+
+ 236:	5f ad [ 	]*MOVE  IV, @DP\[1\]\+\+
+ 238:	2f ad [ 	]*MOVE  IV, @DP\[0\]\-\-
+ 23a:	6f ad [ 	]*MOVE  IV, @DP\[1\]\-\-
+ 23c:	01 6d [ 	]*MOVE  LC\[0\], #01h
+ 23e:	08 ed [ 	]*MOVE  LC\[0\], AP
+ 240:	18 ed [ 	]*MOVE  LC\[0\], APC
+ 242:	48 ed [ 	]*MOVE  LC\[0\], PSF
+ 244:	58 ed [ 	]*MOVE  LC\[0\], IC
+ 246:	68 ed [ 	]*MOVE  LC\[0\], IMR
+ 248:	88 ed [ 	]*MOVE  LC\[0\], SC
+ 24a:	b8 ed [ 	]*MOVE  LC\[0\], IIR
+ 24c:	e8 ed [ 	]*MOVE  LC\[0\], CKCN
+ 24e:	f8 ed [ 	]*MOVE  LC\[0\], WDCN
+ 250:	09 ed [ 	]*MOVE  LC\[0\], A\[0\]
+ 252:	f9 ed [ 	]*MOVE  LC\[0\], A\[15\]
+ 254:	0a ed [ 	]*MOVE  LC\[0\], ACC
+ 256:	1a ed [ 	]*MOVE  LC\[0\], A\[AP\]
+ 258:	0c ed [ 	]*MOVE  LC\[0\], IP
+ 25a:	0d ed [ 	]*MOVE  LC\[0\], @SP\-\-
+ 25c:	1d ed [ 	]*MOVE  LC\[0\], SP
+ 25e:	2d ed [ 	]*MOVE  LC\[0\], IV
+ 260:	1e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\+\+\]
+ 262:	2e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\-\-\]
+ 264:	3e ed [ 	]*MOVE  LC\[0\], OFFS
+ 266:	4e ed [ 	]*MOVE  LC\[0\], DPC
+ 268:	5e ed [ 	]*MOVE  LC\[0\], GR
+ 26a:	6e ed [ 	]*MOVE  LC\[0\], GRL
+ 26c:	7e ed [ 	]*MOVE  LC\[0\], BP
+ 26e:	8e ed [ 	]*MOVE  LC\[0\], GRS
+ 270:	9e ed [ 	]*MOVE  LC\[0\], GRH
+ 272:	ae ed [ 	]*MOVE  LC\[0\], GRXL
+ 274:	be ed [ 	]*MOVE  LC\[0\], FP
+ 276:	0f ed [ 	]*MOVE  LC\[0\], @DP\[0\]
+ 278:	4f ed [ 	]*MOVE  LC\[0\], @DP\[1\]
+ 27a:	1f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\+\+
+ 27c:	5f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\+\+
+ 27e:	2f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\-\-
+ 280:	6f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\-\-
+ 282:	01 0e [ 	]*MOVE  @BP\[OFFS\], #01h
+ 284:	08 8e [ 	]*MOVE  @BP\[OFFS\], AP
+ 286:	18 8e [ 	]*MOVE  @BP\[OFFS\], APC
+ 288:	48 8e [ 	]*MOVE  @BP\[OFFS\], PSF
+ 28a:	58 8e [ 	]*MOVE  @BP\[OFFS\], IC
+ 28c:	68 8e [ 	]*MOVE  @BP\[OFFS\], IMR
+ 28e:	88 8e [ 	]*MOVE  @BP\[OFFS\], SC
+ 290:	b8 8e [ 	]*MOVE  @BP\[OFFS\], IIR
+ 292:	e8 8e [ 	]*MOVE  @BP\[OFFS\], CKCN
+ 294:	f8 8e [ 	]*MOVE  @BP\[OFFS\], WDCN
+ 296:	09 8e [ 	]*MOVE  @BP\[OFFS\], A\[0\]
+ 298:	f9 8e [ 	]*MOVE  @BP\[OFFS\], A\[15\]
+ 29a:	0a 8e [ 	]*MOVE  @BP\[OFFS\], ACC
+ 29c:	1a 8e [ 	]*MOVE  @BP\[OFFS\], A\[AP\]
+ 29e:	0c 8e [ 	]*MOVE  @BP\[OFFS\], IP
+ 2a0:	0d 8e [ 	]*MOVE  @BP\[OFFS\], @SP\-\-
+ 2a2:	1d 8e [ 	]*MOVE  @BP\[OFFS\], SP
+ 2a4:	2d 8e [ 	]*MOVE  @BP\[OFFS\], IV
+ 2a6:	6d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[0\]
+ 2a8:	7d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[1\]
+ 2aa:	3e 8e [ 	]*MOVE  @BP\[OFFS\], OFFS
+ 2ac:	4e 8e [ 	]*MOVE  @BP\[OFFS\], DPC
+ 2ae:	5e 8e [ 	]*MOVE  @BP\[OFFS\], GR
+ 2b0:	6e 8e [ 	]*MOVE  @BP\[OFFS\], GRL
+ 2b2:	7e 8e [ 	]*MOVE  @BP\[OFFS\], BP
+ 2b4:	8e 8e [ 	]*MOVE  @BP\[OFFS\], GRS
+ 2b6:	9e 8e [ 	]*MOVE  @BP\[OFFS\], GRH
+ 2b8:	ae 8e [ 	]*MOVE  @BP\[OFFS\], GRXL
+ 2ba:	be 8e [ 	]*MOVE  @BP\[OFFS\], FP
+ 2bc:	0f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]
+ 2be:	4f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]
+ 2c0:	1f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\+\+
+ 2c2:	5f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\+\+
+ 2c4:	2f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\-\-
+ 2c6:	6f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\-\-
+ 2c8:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 2ca:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 2cc:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 2ce:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 2d0:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 2d2:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 2d4:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 2d6:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 2d8:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 2da:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 2dc:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 2de:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 2e0:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 2e2:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 2e4:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 2e6:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 2e8:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 2ea:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 2ec:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 2ee:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 2f0:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 2f2:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 2f4:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 2f6:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 2f8:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 2fa:	9e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRH
+ 2fc:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 2fe:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 300:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 302:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 304:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 306:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
+ 308:	01 2e [ 	]*MOVE  @BP\[\-\-OFFS\], #01h
+ 30a:	08 ae [ 	]*MOVE  @BP\[\-\-OFFS\], AP
+ 30c:	18 ae [ 	]*MOVE  @BP\[\-\-OFFS\], APC
+ 30e:	48 ae [ 	]*MOVE  @BP\[\-\-OFFS\], PSF
+ 310:	58 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IC
+ 312:	68 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IMR
+ 314:	88 ae [ 	]*MOVE  @BP\[\-\-OFFS\], SC
+ 316:	b8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IIR
+ 318:	e8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], CKCN
+ 31a:	f8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], WDCN
+ 31c:	09 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[0\]
+ 31e:	f9 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[15\]
+ 320:	0a ae [ 	]*MOVE  @BP\[\-\-OFFS\], ACC
+ 322:	1a ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[AP\]
+ 324:	0c ae [ 	]*MOVE  @BP\[\-\-OFFS\], IP
+ 326:	1d ae [ 	]*MOVE  @BP\[\-\-OFFS\], SP
+ 328:	2d ae [ 	]*MOVE  @BP\[\-\-OFFS\], IV
+ 32a:	6d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[0\]
+ 32c:	7d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[1\]
+ 32e:	3e ae [ 	]*MOVE  @BP\[\-\-OFFS\], OFFS
+ 330:	4e ae [ 	]*MOVE  @BP\[\-\-OFFS\], DPC
+ 332:	5e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GR
+ 334:	6e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRL
+ 336:	7e ae [ 	]*MOVE  @BP\[\-\-OFFS\], BP
+ 338:	8e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRS
+ 33a:	9e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRH
+ 33c:	ae ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRXL
+ 33e:	be ae [ 	]*MOVE  @BP\[\-\-OFFS\], FP
+ 340:	0f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[0\]
+ 342:	4f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[1\]
+ 344:	01 3e [ 	]*MOVE  OFFS, #01h
+ 346:	08 be [ 	]*MOVE  OFFS, AP
+ 348:	18 be [ 	]*MOVE  OFFS, APC
+ 34a:	48 be [ 	]*MOVE  OFFS, PSF
+ 34c:	58 be [ 	]*MOVE  OFFS, IC
+ 34e:	68 be [ 	]*MOVE  OFFS, IMR
+ 350:	88 be [ 	]*MOVE  OFFS, SC
+ 352:	b8 be [ 	]*MOVE  OFFS, IIR
+ 354:	e8 be [ 	]*MOVE  OFFS, CKCN
+ 356:	f8 be [ 	]*MOVE  OFFS, WDCN
+ 358:	09 be [ 	]*MOVE  OFFS, A\[0\]
+ 35a:	f9 be [ 	]*MOVE  OFFS, A\[15\]
+ 35c:	0a be [ 	]*MOVE  OFFS, ACC
+ 35e:	1a be [ 	]*MOVE  OFFS, A\[AP\]
+ 360:	0c be [ 	]*MOVE  OFFS, IP
+ 362:	0d be [ 	]*MOVE  OFFS, @SP\-\-
+ 364:	1d be [ 	]*MOVE  OFFS, SP
+ 366:	2d be [ 	]*MOVE  OFFS, IV
+ 368:	6d be [ 	]*MOVE  OFFS, LC\[0\]
+ 36a:	7d be [ 	]*MOVE  OFFS, LC\[1\]
+ 36c:	4e be [ 	]*MOVE  OFFS, DPC
+ 36e:	5e be [ 	]*MOVE  OFFS, GR
+ 370:	6e be [ 	]*MOVE  OFFS, GRL
+ 372:	7e be [ 	]*MOVE  OFFS, BP
+ 374:	8e be [ 	]*MOVE  OFFS, GRS
+ 376:	9e be [ 	]*MOVE  OFFS, GRH
+ 378:	ae be [ 	]*MOVE  OFFS, GRXL
+ 37a:	be be [ 	]*MOVE  OFFS, FP
+ 37c:	0f be [ 	]*MOVE  OFFS, @DP\[0\]
+ 37e:	4f be [ 	]*MOVE  OFFS, @DP\[1\]
+ 380:	1f be [ 	]*MOVE  OFFS, @DP\[0\]\+\+
+ 382:	5f be [ 	]*MOVE  OFFS, @DP\[1\]\+\+
+ 384:	2f be [ 	]*MOVE  OFFS, @DP\[0\]\-\-
+ 386:	6f be [ 	]*MOVE  OFFS, @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq10/data2.s b/gas/testsuite/gas/maxq10/data2.s
new file mode 100644
index 000000000000..94cc70bc59fd
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data2.s
@@ -0,0 +1,455 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/data3.d b/gas/testsuite/gas/maxq10/data3.d
new file mode 100644
index 000000000000..2b6dad4c6b93
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data3.d
@@ -0,0 +1,491 @@
+#objdump:  -dw
+#name: 3rd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4e [ 	]*MOVE  DPC, #01h
+   2:	08 ce [ 	]*MOVE  DPC, AP
+   4:	18 ce [ 	]*MOVE  DPC, APC
+   6:	48 ce [ 	]*MOVE  DPC, PSF
+   8:	58 ce [ 	]*MOVE  DPC, IC
+   a:	68 ce [ 	]*MOVE  DPC, IMR
+   c:	88 ce [ 	]*MOVE  DPC, SC
+   e:	b8 ce [ 	]*MOVE  DPC, IIR
+  10:	e8 ce [ 	]*MOVE  DPC, CKCN
+  12:	f8 ce [ 	]*MOVE  DPC, WDCN
+  14:	09 ce [ 	]*MOVE  DPC, A\[0\]
+  16:	f9 ce [ 	]*MOVE  DPC, A\[15\]
+  18:	0a ce [ 	]*MOVE  DPC, ACC
+  1a:	1a ce [ 	]*MOVE  DPC, A\[AP\]
+  1c:	0c ce [ 	]*MOVE  DPC, IP
+  1e:	0d ce [ 	]*MOVE  DPC, @SP\-\-
+  20:	1d ce [ 	]*MOVE  DPC, SP
+  22:	2d ce [ 	]*MOVE  DPC, IV
+  24:	6d ce [ 	]*MOVE  DPC, LC\[0\]
+  26:	7d ce [ 	]*MOVE  DPC, LC\[1\]
+  28:	1e ce [ 	]*MOVE  DPC, @BP\[OFFS\+\+\]
+  2a:	2e ce [ 	]*MOVE  DPC, @BP\[OFFS\-\-\]
+  2c:	3e ce [ 	]*MOVE  DPC, OFFS
+  2e:	5e ce [ 	]*MOVE  DPC, GR
+  30:	6e ce [ 	]*MOVE  DPC, GRL
+  32:	7e ce [ 	]*MOVE  DPC, BP
+  34:	8e ce [ 	]*MOVE  DPC, GRS
+  36:	9e ce [ 	]*MOVE  DPC, GRH
+  38:	ae ce [ 	]*MOVE  DPC, GRXL
+  3a:	be ce [ 	]*MOVE  DPC, FP
+  3c:	0f ce [ 	]*MOVE  DPC, @DP\[0\]
+  3e:	4f ce [ 	]*MOVE  DPC, @DP\[1\]
+  40:	1f ce [ 	]*MOVE  DPC, @DP\[0\]\+\+
+  42:	5f ce [ 	]*MOVE  DPC, @DP\[1\]\+\+
+  44:	2f ce [ 	]*MOVE  DPC, @DP\[0\]\-\-
+  46:	6f ce [ 	]*MOVE  DPC, @DP\[1\]\-\-
+  48:	01 5e [ 	]*MOVE  GR, #01h
+  4a:	08 de [ 	]*MOVE  GR, AP
+  4c:	18 de [ 	]*MOVE  GR, APC
+  4e:	48 de [ 	]*MOVE  GR, PSF
+  50:	58 de [ 	]*MOVE  GR, IC
+  52:	68 de [ 	]*MOVE  GR, IMR
+  54:	88 de [ 	]*MOVE  GR, SC
+  56:	b8 de [ 	]*MOVE  GR, IIR
+  58:	e8 de [ 	]*MOVE  GR, CKCN
+  5a:	f8 de [ 	]*MOVE  GR, WDCN
+  5c:	09 de [ 	]*MOVE  GR, A\[0\]
+  5e:	f9 de [ 	]*MOVE  GR, A\[15\]
+  60:	0a de [ 	]*MOVE  GR, ACC
+  62:	1a de [ 	]*MOVE  GR, A\[AP\]
+  64:	0c de [ 	]*MOVE  GR, IP
+  66:	0d de [ 	]*MOVE  GR, @SP\-\-
+  68:	1d de [ 	]*MOVE  GR, SP
+  6a:	2d de [ 	]*MOVE  GR, IV
+  6c:	6d de [ 	]*MOVE  GR, LC\[0\]
+  6e:	7d de [ 	]*MOVE  GR, LC\[1\]
+  70:	1e de [ 	]*MOVE  GR, @BP\[OFFS\+\+\]
+  72:	2e de [ 	]*MOVE  GR, @BP\[OFFS\-\-\]
+  74:	3e de [ 	]*MOVE  GR, OFFS
+  76:	4e de [ 	]*MOVE  GR, DPC
+  78:	6e de [ 	]*MOVE  GR, GRL
+  7a:	7e de [ 	]*MOVE  GR, BP
+  7c:	8e de [ 	]*MOVE  GR, GRS
+  7e:	9e de [ 	]*MOVE  GR, GRH
+  80:	ae de [ 	]*MOVE  GR, GRXL
+  82:	be de [ 	]*MOVE  GR, FP
+  84:	0f de [ 	]*MOVE  GR, @DP\[0\]
+  86:	4f de [ 	]*MOVE  GR, @DP\[1\]
+  88:	1f de [ 	]*MOVE  GR, @DP\[0\]\+\+
+  8a:	5f de [ 	]*MOVE  GR, @DP\[1\]\+\+
+  8c:	2f de [ 	]*MOVE  GR, @DP\[0\]\-\-
+  8e:	6f de [ 	]*MOVE  GR, @DP\[1\]\-\-
+  90:	01 6e [ 	]*MOVE  GRL, #01h
+  92:	08 ee [ 	]*MOVE  GRL, AP
+  94:	18 ee [ 	]*MOVE  GRL, APC
+  96:	48 ee [ 	]*MOVE  GRL, PSF
+  98:	58 ee [ 	]*MOVE  GRL, IC
+  9a:	68 ee [ 	]*MOVE  GRL, IMR
+  9c:	88 ee [ 	]*MOVE  GRL, SC
+  9e:	b8 ee [ 	]*MOVE  GRL, IIR
+  a0:	e8 ee [ 	]*MOVE  GRL, CKCN
+  a2:	f8 ee [ 	]*MOVE  GRL, WDCN
+  a4:	09 ee [ 	]*MOVE  GRL, A\[0\]
+  a6:	f9 ee [ 	]*MOVE  GRL, A\[15\]
+  a8:	0a ee [ 	]*MOVE  GRL, ACC
+  aa:	1a ee [ 	]*MOVE  GRL, A\[AP\]
+  ac:	0c ee [ 	]*MOVE  GRL, IP
+  ae:	0d ee [ 	]*MOVE  GRL, @SP\-\-
+  b0:	1d ee [ 	]*MOVE  GRL, SP
+  b2:	2d ee [ 	]*MOVE  GRL, IV
+  b4:	6d ee [ 	]*MOVE  GRL, LC\[0\]
+  b6:	7d ee [ 	]*MOVE  GRL, LC\[1\]
+  b8:	1e ee [ 	]*MOVE  GRL, @BP\[OFFS\+\+\]
+  ba:	2e ee [ 	]*MOVE  GRL, @BP\[OFFS\-\-\]
+  bc:	3e ee [ 	]*MOVE  GRL, OFFS
+  be:	4e ee [ 	]*MOVE  GRL, DPC
+  c0:	5e ee [ 	]*MOVE  GRL, GR
+  c2:	7e ee [ 	]*MOVE  GRL, BP
+  c4:	8e ee [ 	]*MOVE  GRL, GRS
+  c6:	9e ee [ 	]*MOVE  GRL, GRH
+  c8:	ae ee [ 	]*MOVE  GRL, GRXL
+  ca:	be ee [ 	]*MOVE  GRL, FP
+  cc:	0f ee [ 	]*MOVE  GRL, @DP\[0\]
+  ce:	4f ee [ 	]*MOVE  GRL, @DP\[1\]
+  d0:	1f ee [ 	]*MOVE  GRL, @DP\[0\]\+\+
+  d2:	5f ee [ 	]*MOVE  GRL, @DP\[1\]\+\+
+  d4:	2f ee [ 	]*MOVE  GRL, @DP\[0\]\-\-
+  d6:	6f ee [ 	]*MOVE  GRL, @DP\[1\]\-\-
+  d8:	01 7e [ 	]*MOVE  BP, #01h
+  da:	08 fe [ 	]*MOVE  BP, AP
+  dc:	18 fe [ 	]*MOVE  BP, APC
+  de:	48 fe [ 	]*MOVE  BP, PSF
+  e0:	58 fe [ 	]*MOVE  BP, IC
+  e2:	68 fe [ 	]*MOVE  BP, IMR
+  e4:	88 fe [ 	]*MOVE  BP, SC
+  e6:	b8 fe [ 	]*MOVE  BP, IIR
+  e8:	e8 fe [ 	]*MOVE  BP, CKCN
+  ea:	f8 fe [ 	]*MOVE  BP, WDCN
+  ec:	09 fe [ 	]*MOVE  BP, A\[0\]
+  ee:	f9 fe [ 	]*MOVE  BP, A\[15\]
+  f0:	0a fe [ 	]*MOVE  BP, ACC
+  f2:	1a fe [ 	]*MOVE  BP, A\[AP\]
+  f4:	0c fe [ 	]*MOVE  BP, IP
+  f6:	0d fe [ 	]*MOVE  BP, @SP\-\-
+  f8:	1d fe [ 	]*MOVE  BP, SP
+  fa:	2d fe [ 	]*MOVE  BP, IV
+  fc:	6d fe [ 	]*MOVE  BP, LC\[0\]
+  fe:	7d fe [ 	]*MOVE  BP, LC\[1\]
+ 100:	1e fe [ 	]*MOVE  BP, @BP\[OFFS\+\+\]
+ 102:	2e fe [ 	]*MOVE  BP, @BP\[OFFS\-\-\]
+ 104:	3e fe [ 	]*MOVE  BP, OFFS
+ 106:	4e fe [ 	]*MOVE  BP, DPC
+ 108:	5e fe [ 	]*MOVE  BP, GR
+ 10a:	6e fe [ 	]*MOVE  BP, GRL
+ 10c:	8e fe [ 	]*MOVE  BP, GRS
+ 10e:	9e fe [ 	]*MOVE  BP, GRH
+ 110:	ae fe [ 	]*MOVE  BP, GRXL
+ 112:	be fe [ 	]*MOVE  BP, FP
+ 114:	0f fe [ 	]*MOVE  BP, @DP\[0\]
+ 116:	4f fe [ 	]*MOVE  BP, @DP\[1\]
+ 118:	1f fe [ 	]*MOVE  BP, @DP\[0\]\+\+
+ 11a:	5f fe [ 	]*MOVE  BP, @DP\[1\]\+\+
+ 11c:	2f fe [ 	]*MOVE  BP, @DP\[0\]\-\-
+ 11e:	6f fe [ 	]*MOVE  BP, @DP\[1\]\-\-
+ 120:	01 0f [ 	]*MOVE  @DP\[0\], #01h
+ 122:	08 8f [ 	]*MOVE  @DP\[0\], AP
+ 124:	18 8f [ 	]*MOVE  @DP\[0\], APC
+ 126:	48 8f [ 	]*MOVE  @DP\[0\], PSF
+ 128:	58 8f [ 	]*MOVE  @DP\[0\], IC
+ 12a:	68 8f [ 	]*MOVE  @DP\[0\], IMR
+ 12c:	88 8f [ 	]*MOVE  @DP\[0\], SC
+ 12e:	b8 8f [ 	]*MOVE  @DP\[0\], IIR
+ 130:	e8 8f [ 	]*MOVE  @DP\[0\], CKCN
+ 132:	f8 8f [ 	]*MOVE  @DP\[0\], WDCN
+ 134:	09 8f [ 	]*MOVE  @DP\[0\], A\[0\]
+ 136:	f9 8f [ 	]*MOVE  @DP\[0\], A\[15\]
+ 138:	0a 8f [ 	]*MOVE  @DP\[0\], ACC
+ 13a:	1a 8f [ 	]*MOVE  @DP\[0\], A\[AP\]
+ 13c:	0c 8f [ 	]*MOVE  @DP\[0\], IP
+ 13e:	0d 8f [ 	]*MOVE  @DP\[0\], @SP\-\-
+ 140:	1d 8f [ 	]*MOVE  @DP\[0\], SP
+ 142:	2d 8f [ 	]*MOVE  @DP\[0\], IV
+ 144:	6d 8f [ 	]*MOVE  @DP\[0\], LC\[0\]
+ 146:	7d 8f [ 	]*MOVE  @DP\[0\], LC\[1\]
+ 148:	1e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\+\+\]
+ 14a:	2e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\-\-\]
+ 14c:	3e 8f [ 	]*MOVE  @DP\[0\], OFFS
+ 14e:	4e 8f [ 	]*MOVE  @DP\[0\], DPC
+ 150:	5e 8f [ 	]*MOVE  @DP\[0\], GR
+ 152:	6e 8f [ 	]*MOVE  @DP\[0\], GRL
+ 154:	7e 8f [ 	]*MOVE  @DP\[0\], BP
+ 156:	8e 8f [ 	]*MOVE  @DP\[0\], GRS
+ 158:	9e 8f [ 	]*MOVE  @DP\[0\], GRH
+ 15a:	ae 8f [ 	]*MOVE  @DP\[0\], GRXL
+ 15c:	be 8f [ 	]*MOVE  @DP\[0\], FP
+ 15e:	01 1f [ 	]*MOVE  @\+\+DP\[0\], #01h
+ 160:	08 9f [ 	]*MOVE  @\+\+DP\[0\], AP
+ 162:	18 9f [ 	]*MOVE  @\+\+DP\[0\], APC
+ 164:	48 9f [ 	]*MOVE  @\+\+DP\[0\], PSF
+ 166:	58 9f [ 	]*MOVE  @\+\+DP\[0\], IC
+ 168:	68 9f [ 	]*MOVE  @\+\+DP\[0\], IMR
+ 16a:	88 9f [ 	]*MOVE  @\+\+DP\[0\], SC
+ 16c:	b8 9f [ 	]*MOVE  @\+\+DP\[0\], IIR
+ 16e:	e8 9f [ 	]*MOVE  @\+\+DP\[0\], CKCN
+ 170:	f8 9f [ 	]*MOVE  @\+\+DP\[0\], WDCN
+ 172:	09 9f [ 	]*MOVE  @\+\+DP\[0\], A\[0\]
+ 174:	f9 9f [ 	]*MOVE  @\+\+DP\[0\], A\[15\]
+ 176:	0a 9f [ 	]*MOVE  @\+\+DP\[0\], ACC
+ 178:	1a 9f [ 	]*MOVE  @\+\+DP\[0\], A\[AP\]
+ 17a:	0c 9f [ 	]*MOVE  @\+\+DP\[0\], IP
+ 17c:	0d 9f [ 	]*MOVE  @\+\+DP\[0\], @SP\-\-
+ 17e:	1d 9f [ 	]*MOVE  @\+\+DP\[0\], SP
+ 180:	2d 9f [ 	]*MOVE  @\+\+DP\[0\], IV
+ 182:	6d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[0\]
+ 184:	7d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[1\]
+ 186:	1e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\+\+\]
+ 188:	2e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\-\-\]
+ 18a:	3e 9f [ 	]*MOVE  @\+\+DP\[0\], OFFS
+ 18c:	4e 9f [ 	]*MOVE  @\+\+DP\[0\], DPC
+ 18e:	5e 9f [ 	]*MOVE  @\+\+DP\[0\], GR
+ 190:	6e 9f [ 	]*MOVE  @\+\+DP\[0\], GRL
+ 192:	7e 9f [ 	]*MOVE  @\+\+DP\[0\], BP
+ 194:	8e 9f [ 	]*MOVE  @\+\+DP\[0\], GRS
+ 196:	9e 9f [ 	]*MOVE  @\+\+DP\[0\], GRH
+ 198:	ae 9f [ 	]*MOVE  @\+\+DP\[0\], GRXL
+ 19a:	be 9f [ 	]*MOVE  @\+\+DP\[0\], FP
+ 19c:	01 2f [ 	]*MOVE  @\-\-DP\[0\], #01h
+ 19e:	08 af [ 	]*MOVE  @\-\-DP\[0\], AP
+ 1a0:	18 af [ 	]*MOVE  @\-\-DP\[0\], APC
+ 1a2:	48 af [ 	]*MOVE  @\-\-DP\[0\], PSF
+ 1a4:	58 af [ 	]*MOVE  @\-\-DP\[0\], IC
+ 1a6:	68 af [ 	]*MOVE  @\-\-DP\[0\], IMR
+ 1a8:	88 af [ 	]*MOVE  @\-\-DP\[0\], SC
+ 1aa:	b8 af [ 	]*MOVE  @\-\-DP\[0\], IIR
+ 1ac:	e8 af [ 	]*MOVE  @\-\-DP\[0\], CKCN
+ 1ae:	f8 af [ 	]*MOVE  @\-\-DP\[0\], WDCN
+ 1b0:	09 af [ 	]*MOVE  @\-\-DP\[0\], A\[0\]
+ 1b2:	f9 af [ 	]*MOVE  @\-\-DP\[0\], A\[15\]
+ 1b4:	0a af [ 	]*MOVE  @\-\-DP\[0\], ACC
+ 1b6:	1a af [ 	]*MOVE  @\-\-DP\[0\], A\[AP\]
+ 1b8:	0c af [ 	]*MOVE  @\-\-DP\[0\], IP
+ 1ba:	0d af [ 	]*MOVE  @\-\-DP\[0\], @SP\-\-
+ 1bc:	1d af [ 	]*MOVE  @\-\-DP\[0\], SP
+ 1be:	2d af [ 	]*MOVE  @\-\-DP\[0\], IV
+ 1c0:	6d af [ 	]*MOVE  @\-\-DP\[0\], LC\[0\]
+ 1c2:	7d af [ 	]*MOVE  @\-\-DP\[0\], LC\[1\]
+ 1c4:	1e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\+\+\]
+ 1c6:	2e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\-\-\]
+ 1c8:	3e af [ 	]*MOVE  @\-\-DP\[0\], OFFS
+ 1ca:	4e af [ 	]*MOVE  @\-\-DP\[0\], DPC
+ 1cc:	5e af [ 	]*MOVE  @\-\-DP\[0\], GR
+ 1ce:	6e af [ 	]*MOVE  @\-\-DP\[0\], GRL
+ 1d0:	7e af [ 	]*MOVE  @\-\-DP\[0\], BP
+ 1d2:	8e af [ 	]*MOVE  @\-\-DP\[0\], GRS
+ 1d4:	9e af [ 	]*MOVE  @\-\-DP\[0\], GRH
+ 1d6:	ae af [ 	]*MOVE  @\-\-DP\[0\], GRXL
+ 1d8:	be af [ 	]*MOVE  @\-\-DP\[0\], FP
+ 1da:	01 3f [ 	]*MOVE  DP\[0\], #01h
+ 1dc:	08 bf [ 	]*MOVE  DP\[0\], AP
+ 1de:	18 bf [ 	]*MOVE  DP\[0\], APC
+ 1e0:	48 bf [ 	]*MOVE  DP\[0\], PSF
+ 1e2:	58 bf [ 	]*MOVE  DP\[0\], IC
+ 1e4:	68 bf [ 	]*MOVE  DP\[0\], IMR
+ 1e6:	88 bf [ 	]*MOVE  DP\[0\], SC
+ 1e8:	b8 bf [ 	]*MOVE  DP\[0\], IIR
+ 1ea:	e8 bf [ 	]*MOVE  DP\[0\], CKCN
+ 1ec:	f8 bf [ 	]*MOVE  DP\[0\], WDCN
+ 1ee:	09 bf [ 	]*MOVE  DP\[0\], A\[0\]
+ 1f0:	f9 bf [ 	]*MOVE  DP\[0\], A\[15\]
+ 1f2:	0a bf [ 	]*MOVE  DP\[0\], ACC
+ 1f4:	1a bf [ 	]*MOVE  DP\[0\], A\[AP\]
+ 1f6:	0c bf [ 	]*MOVE  DP\[0\], IP
+ 1f8:	0d bf [ 	]*MOVE  DP\[0\], @SP\-\-
+ 1fa:	1d bf [ 	]*MOVE  DP\[0\], SP
+ 1fc:	2d bf [ 	]*MOVE  DP\[0\], IV
+ 1fe:	6d bf [ 	]*MOVE  DP\[0\], LC\[0\]
+ 200:	7d bf [ 	]*MOVE  DP\[0\], LC\[1\]
+ 202:	1e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\+\+\]
+ 204:	2e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\-\-\]
+ 206:	3e bf [ 	]*MOVE  DP\[0\], OFFS
+ 208:	4e bf [ 	]*MOVE  DP\[0\], DPC
+ 20a:	5e bf [ 	]*MOVE  DP\[0\], GR
+ 20c:	6e bf [ 	]*MOVE  DP\[0\], GRL
+ 20e:	7e bf [ 	]*MOVE  DP\[0\], BP
+ 210:	8e bf [ 	]*MOVE  DP\[0\], GRS
+ 212:	9e bf [ 	]*MOVE  DP\[0\], GRH
+ 214:	ae bf [ 	]*MOVE  DP\[0\], GRXL
+ 216:	be bf [ 	]*MOVE  DP\[0\], FP
+ 218:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21a:	01 08 [ 	]*MOVE  AP, #01h
+ 21c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21e:	08 88 [ 	]*MOVE  AP, AP
+ 220:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 222:	18 88 [ 	]*MOVE  AP, APC
+ 224:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 226:	48 88 [ 	]*MOVE  AP, PSF
+ 228:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22a:	58 88 [ 	]*MOVE  AP, IC
+ 22c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22e:	68 88 [ 	]*MOVE  AP, IMR
+ 230:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 232:	b8 88 [ 	]*MOVE  AP, IIR
+ 234:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 236:	e8 88 [ 	]*MOVE  AP, CKCN
+ 238:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23a:	f8 88 [ 	]*MOVE  AP, WDCN
+ 23c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23e:	09 88 [ 	]*MOVE  AP, A\[0\]
+ 240:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 242:	f9 88 [ 	]*MOVE  AP, A\[15\]
+ 244:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 246:	0a 88 [ 	]*MOVE  AP, ACC
+ 248:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24a:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+ 24c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24e:	0c 88 [ 	]*MOVE  AP, IP
+ 250:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 252:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+ 254:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 256:	1d 88 [ 	]*MOVE  AP, SP
+ 258:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25a:	2d 88 [ 	]*MOVE  AP, IV
+ 25c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25e:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+ 260:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 262:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+ 264:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 266:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+ 268:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26a:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+ 26c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26e:	3e 88 [ 	]*MOVE  AP, OFFS
+ 270:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 272:	4e 88 [ 	]*MOVE  AP, DPC
+ 274:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 276:	5e 88 [ 	]*MOVE  AP, GR
+ 278:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27a:	6e 88 [ 	]*MOVE  AP, GRL
+ 27c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27e:	7e 88 [ 	]*MOVE  AP, BP
+ 280:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 282:	8e 88 [ 	]*MOVE  AP, GRS
+ 284:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 286:	9e 88 [ 	]*MOVE  AP, GRH
+ 288:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28a:	ae 88 [ 	]*MOVE  AP, GRXL
+ 28c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28e:	be 88 [ 	]*MOVE  AP, FP
+ 290:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 292:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+ 294:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 296:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+ 298:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29a:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+ 29c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29e:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+ 2a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a2:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+ 2a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a6:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+ 2a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2aa:	01 68 [ 	]*MOVE  IMR, #01h
+ 2ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ae:	08 e8 [ 	]*MOVE  IMR, AP
+ 2b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b2:	18 e8 [ 	]*MOVE  IMR, APC
+ 2b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b6:	48 e8 [ 	]*MOVE  IMR, PSF
+ 2b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ba:	58 e8 [ 	]*MOVE  IMR, IC
+ 2bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2be:	68 e8 [ 	]*MOVE  IMR, IMR
+ 2c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c2:	88 e8 [ 	]*MOVE  IMR, SC
+ 2c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c6:	b8 e8 [ 	]*MOVE  IMR, IIR
+ 2c8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ca:	f8 e8 [ 	]*MOVE  IMR, WDCN
+ 2cc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ce:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+ 2d0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d2:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+ 2d4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d6:	0a e8 [ 	]*MOVE  IMR, ACC
+ 2d8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2da:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+ 2dc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2de:	0c e8 [ 	]*MOVE  IMR, IP
+ 2e0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e2:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+ 2e4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e6:	1d e8 [ 	]*MOVE  IMR, SP
+ 2e8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ea:	2d e8 [ 	]*MOVE  IMR, IV
+ 2ec:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ee:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+ 2f0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f2:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+ 2f4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+ 2f8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fa:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+ 2fc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fe:	3e e8 [ 	]*MOVE  IMR, OFFS
+ 300:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 302:	4e e8 [ 	]*MOVE  IMR, DPC
+ 304:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 306:	5e e8 [ 	]*MOVE  IMR, GR
+ 308:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30a:	6e e8 [ 	]*MOVE  IMR, GRL
+ 30c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30e:	7e e8 [ 	]*MOVE  IMR, BP
+ 310:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 312:	8e e8 [ 	]*MOVE  IMR, GRS
+ 314:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 316:	9e e8 [ 	]*MOVE  IMR, GRH
+ 318:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31a:	ae e8 [ 	]*MOVE  IMR, GRXL
+ 31c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31e:	be e8 [ 	]*MOVE  IMR, FP
+ 320:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 322:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+ 324:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 326:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+ 328:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32a:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+ 32c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32e:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+ 330:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 332:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+ 334:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 336:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+ 338:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33a:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 33c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33e:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 340:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 342:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 344:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 346:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 348:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34a:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 34c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34e:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 350:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 352:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 354:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 356:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 358:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35a:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 35c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35e:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 360:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 362:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 364:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 366:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 368:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36a:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 36c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36e:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 370:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 372:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 374:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 376:	0d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @SP\-\-
+ 378:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37a:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 37c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37e:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 380:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 382:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 384:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 386:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 388:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38a:	1e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\+\+\]
+ 38c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38e:	2e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\-\-\]
+ 390:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 392:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 394:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 396:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 398:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39a:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 39c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39e:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 3a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a2:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 3a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a6:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 3a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3aa:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 3ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ae:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 3b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b2:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 3b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b6:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 3b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ba:	1f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\+\+
+ 3bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3be:	5f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\+\+
+ 3c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c2:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 3c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c6:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq10/data3.s b/gas/testsuite/gas/maxq10/data3.s
new file mode 100644
index 000000000000..c3cdbbb43eba
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/data3.s
@@ -0,0 +1,379 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq10/err.s b/gas/testsuite/gas/maxq10/err.s
new file mode 100644
index 000000000000..916da73a8f3a
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/err.s
@@ -0,0 +1,31 @@
+# err.s
+# some data pointer error conditions
+
+#NOT YET INCLUDED 
+
+
+
+	MOVE @++DP[0], @DP[0]++
+	MOVE @++DP[1], @DP[1]++
+	MOVE @BP[++Offs], @BP[Offs++]
+	MOVE @--DP[0], @DP[0]--
+	MOVE @--DP[1], @DP[1]--
+	MOVE @BP[--Offs], @BP[Offs--]	
+	MOVE @++DP[0], @DP[0]--
+	MOVE @++DP[1], @DP[1]--	
+	MOVE @BP[++Offs], @BP[Offs--]		
+	MOVE @--DP[0], @DP[0]++
+	MOVE @--DP[1], @DP[1]++
+	MOVE @BP[--Offs], @BP[Offs++]
+	MOVE @DP[0], @DP[0]++
+	MOVE @DP[1], @DP[1]++
+	MOVE @BP[Offs], @BP[Offs++]
+	MOVE @DP[0], @DP[0]--
+	MOVE @DP[1], @DP[1]--
+	MOVE @BP[Offs], @BP[Offs--]
+	MOVE DP[0], @DP[0]++
+	MOVE DP[0], @DP[0]--
+	MOVE DP[1], @DP[1]++
+	MOVE DP[1], @DP[1]--
+	MOVE Offs, @BP[Offs--]	
+	MOVE Offs, @BP[Offs++]
diff --git a/gas/testsuite/gas/maxq10/jump.d b/gas/testsuite/gas/maxq10/jump.d
new file mode 100644
index 000000000000..71f60e3f2e2e
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/jump.d
@@ -0,0 +1,117 @@
+#objdump: -dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <LableStart>:
+   0:	ff 0c [ 	]*JUMP  #ffh
+   2:	fe 2c [ 	]*JUMP C , #feh
+   4:	09 ac [ 	]*JUMP C , A\[0\]
+   6:	19 ac [ 	]*JUMP C , A\[1\]
+   8:	fb 6c [ 	]*JUMP NC , #fbh
+   a:	09 ec [ 	]*JUMP NC , A\[0\]
+   c:	19 ec [ 	]*JUMP NC , A\[1\]
+   e:	f8 4c [ 	]*JUMP S , #f8h
+  10:	09 cc [ 	]*JUMP S , A\[0\]
+  12:	19 cc [ 	]*JUMP S , A\[1\]
+  14:	f5 1c [ 	]*JUMP Z , #f5h
+  16:	09 9c [ 	]*JUMP Z , A\[0\]
+  18:	19 9c [ 	]*JUMP Z , A\[1\]
+  1a:	f2 5c [ 	]*JUMP NZ , #f2h
+  1c:	09 dc [ 	]*JUMP NZ , A\[0\]
+  1e:	19 dc [ 	]*JUMP NZ , A\[1\]
+  20:	ef 3c [ 	]*JUMP E , #efh
+  22:	ee 7c [ 	]*JUMP NE , #eeh
+  24:	00 7c [ 	]*JUMP NE , #00h
+
+0+026 <Lable1>:
+  26:	ff 0c [ 	]*JUMP  #ffh
+  28:	fe 2c [ 	]*JUMP C , #feh
+  2a:	09 ac [ 	]*JUMP C , A\[0\]
+  2c:	19 ac [ 	]*JUMP C , A\[1\]
+  2e:	fb 6c [ 	]*JUMP NC , #fbh
+  30:	09 ec [ 	]*JUMP NC , A\[0\]
+  32:	19 ec [ 	]*JUMP NC , A\[1\]
+  34:	f8 4c [ 	]*JUMP S , #f8h
+  36:	09 cc [ 	]*JUMP S , A\[0\]
+  38:	19 cc [ 	]*JUMP S , A\[1\]
+  3a:	f5 1c [ 	]*JUMP Z , #f5h
+  3c:	09 9c [ 	]*JUMP Z , A\[0\]
+  3e:	19 9c [ 	]*JUMP Z , A\[1\]
+  40:	f2 5c [ 	]*JUMP NZ , #f2h
+  42:	09 dc [ 	]*JUMP NZ , A\[0\]
+  44:	19 dc [ 	]*JUMP NZ , A\[1\]
+  46:	ef 3c [ 	]*JUMP E , #efh
+  48:	ee 7c [ 	]*JUMP NE , #eeh
+  4a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  4c:	c6 0c [ 	]*JUMP  #c6h
+  4e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  50:	c6 2c [ 	]*JUMP C , #c6h
+  52:	09 ac [ 	]*JUMP C , A\[0\]
+  54:	19 ac [ 	]*JUMP C , A\[1\]
+  56:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  58:	c6 6c [ 	]*JUMP NC , #c6h
+  5a:	09 ec [ 	]*JUMP NC , A\[0\]
+  5c:	19 ec [ 	]*JUMP NC , A\[1\]
+  5e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  60:	c6 1c [ 	]*JUMP Z , #c6h
+  62:	09 9c [ 	]*JUMP Z , A\[0\]
+  64:	19 9c [ 	]*JUMP Z , A\[1\]
+  66:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  68:	c6 5c [ 	]*JUMP NZ , #c6h
+  6a:	09 dc [ 	]*JUMP NZ , A\[0\]
+  6c:	19 dc [ 	]*JUMP NZ , A\[1\]
+  6e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  70:	c6 4c [ 	]*JUMP S , #c6h
+  72:	09 cc [ 	]*JUMP S , A\[0\]
+  74:	19 cc [ 	]*JUMP S , A\[1\]
+  76:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  78:	c6 3c [ 	]*JUMP E , #c6h
+  7a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  7c:	c6 7c [ 	]*JUMP NE , #c6h
+  7e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  80:	c6 0c [ 	]*JUMP  #c6h
+  82:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  84:	c6 2c [ 	]*JUMP C , #c6h
+  86:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  88:	09 ac [ 	]*JUMP C , A\[0\]
+  8a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  8c:	19 ac [ 	]*JUMP C , A\[1\]
+  8e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  90:	c6 7c [ 	]*JUMP NE , #c6h
+  92:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  94:	c6 1c [ 	]*JUMP Z , #c6h
+  96:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  98:	09 9c [ 	]*JUMP Z , A\[0\]
+  9a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  9c:	19 9c [ 	]*JUMP Z , A\[1\]
+  9e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  a0:	c6 5c [ 	]*JUMP NZ , #c6h
+  a2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a4:	09 dc [ 	]*JUMP NZ , A\[0\]
+  a6:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a8:	19 dc [ 	]*JUMP NZ , A\[1\]
+  aa:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  ac:	c6 4c [ 	]*JUMP S , #c6h
+  ae:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b0:	09 cc [ 	]*JUMP S , A\[0\]
+  b2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b4:	19 cc [ 	]*JUMP S , A\[1\]
+  b6:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  b8:	c6 6c [ 	]*JUMP NC , #c6h
+  ba:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  bc:	09 ec [ 	]*JUMP NC , A\[0\]
+  be:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  c0:	19 ec [ 	]*JUMP NC , A\[1\]
+  c2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  c4:	c6 3c [ 	]*JUMP E , #c6h
+	...
+
+0+4c6 <LongJump>:
+ 4c6:	3a da [ 	]*NOP 
+ 4c8:	3a da [ 	]*NOP 
+ 4ca:	3a da [ 	]*NOP 
+ 4cc:	3a da [ 	]*NOP 
+ 4ce:	3a da [ 	]*NOP 
+
diff --git a/gas/testsuite/gas/maxq10/jump.s b/gas/testsuite/gas/maxq10/jump.s
new file mode 100644
index 000000000000..3ce5838d7dfc
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/jump.s
@@ -0,0 +1,86 @@
+;# jump.s 
+;# Program flow instructions using JUMP
+.text
+LableStart:	
+		JUMP LableStart
+		JUMP C, LableStart
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LableStart
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP S, LableStart
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP Z, LableStart
+		JUMP Z, A[0]
+		JUMP Z, A[1]	
+		JUMP NZ, LableStart
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP E, LableStart
+		JUMP NE, LableStart
+		JUMP NE, Lable1
+
+Lable1:			
+		SJUMP Lable1		;Checking the SJUMP opcode
+		SJUMP C, Lable1
+		SJUMP C, A[0]
+		SJUMP C, A[1]
+		SJUMP NC, Lable1
+		SJUMP NC, A[0]
+		SJUMP NC, A[1]
+		SJUMP S, Lable1
+		SJUMP S, A[0]
+		SJUMP S, A[1]	
+		SJUMP Z, Lable1
+		SJUMP Z, A[0]
+		SJUMP Z, A[1]	
+		SJUMP NZ, Lable1
+		SJUMP NZ, A[0]
+		SJUMP NZ, A[1]	
+		SJUMP E, Lable1
+		SJUMP NE, Lable1
+		JUMP LongJump
+		JUMP C, LongJump
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LongJump
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP Z, LongJump
+		JUMP Z, A[0]
+		JUMP Z, A[1]
+		JUMP NZ, LongJump
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP S, LongJump
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP E, LongJump
+		JUMP NE, LongJump
+		LJUMP LongJump		;test LJUMP also
+		LJUMP C, LongJump
+		LJUMP C, A[0]
+		LJUMP C, A[1]
+		LJUMP NE, LongJump
+		LJUMP Z, LongJump
+		LJUMP Z, A[0]
+		LJUMP Z, A[1]
+		LJUMP NZ, LongJump
+		LJUMP NZ, A[0]
+		LJUMP NZ, A[1]
+		LJUMP S, LongJump
+		LJUMP S, A[0]
+		LJUMP S, A[1]
+		LJUMP NC, LongJump
+		LJUMP NC, A[0]
+		LJUMP NC, A[1]	 
+		LJUMP E, LongJump
+		.fill 0x200, 2, 0 	
+LongJump: 
+		NOP
+		NOP
+		NOP
+		NOP
+		NOP
diff --git a/gas/testsuite/gas/maxq10/logical.d b/gas/testsuite/gas/maxq10/logical.d
new file mode 100644
index 000000000000..8cad1bf7eb9e
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/logical.d
@@ -0,0 +1,25 @@
+#objdump:-dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	00 08 [ 	]*MOVE  AP, #00h
+   2:	ff 1a [ 	]*AND  #ffh
+   4:	f0 2a [ 	]*OR  #f0h
+   6:	fe 3a [ 	]*XOR  #feh
+   8:	1a 8a [ 	]*CPL 
+   a:	9a 8a [ 	]*NEG 
+   c:	2a 8a [ 	]*SLA 
+   e:	3a 8a [ 	]*SLA2 
+  10:	6a 8a [ 	]*SLA4 
+  12:	4a 8a [ 	]*RL 
+  14:	5a 8a [ 	]*RLC 
+  16:	fa 8a [ 	]*SRA 
+  18:	ea 8a [ 	]*SRA2 
+  1a:	ba 8a [ 	]*SRA4 
+  1c:	aa 8a [ 	]*SR 
+  1e:	ca 8a [ 	]*RR 
+  20:	da 8a [ 	]*RRC 
+	...
diff --git a/gas/testsuite/gas/maxq10/logical.s b/gas/testsuite/gas/maxq10/logical.s
new file mode 100644
index 000000000000..aa4202a42a72
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/logical.s
@@ -0,0 +1,23 @@
+;# logical.s
+;# Verifies all the logical operation in the file
+
+.text	
+foo:
+	MOVE AP, #00h	;Set AC[0] as the active accumulator
+	AND #FFh	;AND AC[0] with 0xFF
+	OR #F0h
+	XOR #FEh
+	CPL
+	NEG
+	SLA
+	SLA2	
+	SLA4
+	RL	
+	RLC
+	SRA
+	SRA2
+	SRA4
+	SR
+	RR
+	RRC	
+
diff --git a/gas/testsuite/gas/maxq10/math.d b/gas/testsuite/gas/maxq10/math.d
new file mode 100644
index 000000000000..34a70dd0f8d7
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/math.d
@@ -0,0 +1,41 @@
+#objdump:-dw
+#name: Math operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4a [ 	]*ADD  #01h
+   2:	02 4a [ 	]*ADD  #02h
+   4:	03 4a [ 	]*ADD  #03h
+   6:	04 4a [ 	]*ADD  #04h
+   8:	05 4a [ 	]*ADD  #05h
+   a:	09 ca [ 	]*ADD  A\[0\]
+   c:	19 ca [ 	]*ADD  A\[1\]
+   e:	29 ca [ 	]*ADD  A\[2\]
+  10:	39 ca [ 	]*ADD  A\[3\]
+  12:	49 ca [ 	]*ADD  A\[4\]
+  14:	31 6a [ 	]*ADDC  #31h
+  16:	32 6a [ 	]*ADDC  #32h
+  18:	33 6a [ 	]*ADDC  #33h
+  1a:	09 ea [ 	]*ADDC  A\[0\]
+  1c:	19 ea [ 	]*ADDC  A\[1\]
+  1e:	29 ea [ 	]*ADDC  A\[2\]
+  20:	39 ea [ 	]*ADDC  A\[3\]
+  22:	01 5a [ 	]*SUB  #01h
+  24:	02 5a [ 	]*SUB  #02h
+  26:	03 5a [ 	]*SUB  #03h
+  28:	04 5a [ 	]*SUB  #04h
+  2a:	05 5a [ 	]*SUB  #05h
+  2c:	09 da [ 	]*SUB  A\[0\]
+  2e:	19 da [ 	]*SUB  A\[1\]
+  30:	29 da [ 	]*SUB  A\[2\]
+  32:	39 da [ 	]*SUB  A\[3\]
+  34:	49 da [ 	]*SUB  A\[4\]
+  36:	31 7a [ 	]*SUBB  #31h
+  38:	32 7a [ 	]*SUBB  #32h
+  3a:	33 7a [ 	]*SUBB  #33h
+  3c:	09 fa [ 	]*SUBB  A\[0\]
+  3e:	19 fa [ 	]*SUBB  A\[1\]
+  40:	29 fa [ 	]*SUBB  A\[2\]
+  42:	39 fa [ 	]*SUBB  A\[3\]
diff --git a/gas/testsuite/gas/maxq10/math.s b/gas/testsuite/gas/maxq10/math.s
new file mode 100644
index 000000000000..b3c1bd7af31b
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/math.s
@@ -0,0 +1,39 @@
+;# math.s
+;# Implements all the math intuctions
+
+.text
+foo:	
+	ADD #01h	; add 01h to accumulator
+	ADD #02h
+	ADD #03h
+	ADD #04h
+	ADD #05h
+	ADD A[0]	; Add Active accumulator+A[0]
+	ADD A[1]
+	ADD A[2]
+	ADD A[3]
+	ADD A[4]
+	ADDC #31h
+	ADDC #32h
+	ADDC #33h
+	ADDC A[0]
+	ADDC A[1]
+	ADDC A[2]
+	ADDC A[3]
+	SUB #01h	; Substract 01h from accumulator
+	SUB #02h
+	SUB #03h
+	SUB #04h
+	SUB #05h
+	SUB A[0]	; Active accumulator-A[0]
+	SUB A[1]
+	SUB A[2]
+	SUB A[3]
+	SUB A[4]	
+	SUBB #31h
+	SUBB #32h
+	SUBB #33h
+	SUBB A[0]
+	SUBB A[1]
+	SUBB A[2]
+	SUBB A[3]
diff --git a/gas/testsuite/gas/maxq10/maxq10.exp b/gas/testsuite/gas/maxq10/maxq10.exp
new file mode 100644
index 000000000000..482bd4ca2c23
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/maxq10.exp
@@ -0,0 +1,52 @@
+#
+# MAXQ10 tests
+#
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "maxq10 $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
+proc gas_64_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help]
+}
+
+proc gas_32_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help]
+}
+
+if [expr ([istarget "maxq-*-*"] ||  [istarget "maxq-coff-*"]) && [gas_32_check]]  then {
+
+    global ASFLAGS
+    set old_ASFLAGS "$ASFLAGS"
+    set ASFLAGS "$ASFLAGS -MAXQ10"
+
+    run_dump_test "range"
+    run_dump_test "data3"
+    run_dump_test "data2"
+    run_dump_test "call"
+    run_dump_test "jump"
+    run_dump_test "logical"
+    run_dump_test "math"
+    run_dump_test "bits"
+
+    set ASFLAGS "$old_ASFLAGS"
+}
+
diff --git a/gas/testsuite/gas/maxq10/pmtest.d b/gas/testsuite/gas/maxq10/pmtest.d
new file mode 100644
index 000000000000..d4d97a444c57
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/pmtest.d
@@ -0,0 +1,21 @@
+#objdump: -dw
+#name: MaC supoprt check
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	05 13 [ 	]*MOVE  13h, #05h
+   2:	e9 53 [ 	]*MOVE  53h, #e9h
+   4:	09 e3 [ 	]*MOVE  63h, A\[0\]
+   6:	12 14 [ 	]*MOVE  14h, #12h
+   8:	12 44 [ 	]*MOVE  44h, #12h
+   a:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+   c:	09 84 [ 	]*MOVE  04h, A\[0\]
+   e:	7b 15 [ 	]*MOVE  15h, #7bh
+  10:	13 25 [ 	]*MOVE  25h, #13h
+  12:	d9 e5 [ 	]*MOVE  65h, A\[13\]
+  14:	13 15 [ 	]*MOVE  15h, #13h
+  16:	13 a5 [ 	]*MOVE  25h, 13h
+  18:	12 13 [ 	]*MOVE  13h, #12h
+	...
diff --git a/gas/testsuite/gas/maxq10/pmtest.s b/gas/testsuite/gas/maxq10/pmtest.s
new file mode 100644
index 000000000000..cce6f165c877
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/pmtest.s
@@ -0,0 +1,22 @@
+;# Peripheral(plugable) module test file 
+.text
+
+; Timer1 test module configured at mod. no. 3
+move T1CN, #05h
+move T1MD, #233
+move T1CL,A[0]
+; Timer2 module test plugged at mod. no. 4
+move T2CFG, #12h
+move T2V, #12h
+move T2C, A[0]
+
+; MAC module test plugged at 5
+move MCNT, #123
+move MA, #13h
+move MC0, A[13]
+
+;test the pm support 
+move 15h,#13h
+move 25h, 13h
+move 13h, #12h
+
diff --git a/gas/testsuite/gas/maxq10/range.d b/gas/testsuite/gas/maxq10/range.d
new file mode 100644
index 000000000000..756783ee7814
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/range.d
@@ -0,0 +1,49 @@
+#objdump: -dw
+#name: limit checks for maxq10 immediate data
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   2:	ff 09 [ 	]*MOVE  A\[0\], #ffh
+   4:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   6:	ff 08 [ 	]*MOVE  AP, #ffh
+   8:	01 09 [ 	]*MOVE  A\[0\], #01h
+   a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   c:	83 08 [ 	]*MOVE  AP, #83h
+   e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  10:	82 08 [ 	]*MOVE  AP, #82h
+  12:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  14:	81 08 [ 	]*MOVE  AP, #81h
+  16:	7d 09 [ 	]*MOVE  A\[0\], #7dh
+  18:	7e 09 [ 	]*MOVE  A\[0\], #7eh
+  1a:	80 09 [ 	]*MOVE  A\[0\], #80h
+  1c:	fe 09 [ 	]*MOVE  A\[0\], #feh
+  1e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  20:	ff 0d [ 	]*MOVE  @\+\+SP, #ffh
+  22:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  24:	82 0d [ 	]*MOVE  @\+\+SP, #82h
+  26:	fe 0d [ 	]*MOVE  @\+\+SP, #feh
+  28:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2a:	81 0d [ 	]*MOVE  @\+\+SP, #81h
+  2c:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2e:	80 0d [ 	]*MOVE  @\+\+SP, #80h
+  30:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  32:	ff 4a [ 	]*ADD  #ffh
+  34:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  36:	81 4a [ 	]*ADD  #81h
+  38:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  3a:	7f 4a [ 	]*ADD  #7fh
+  3c:	7f 4a [ 	]*ADD  #7fh
+  3e:	80 4a [ 	]*ADD  #80h
+  40:	81 4a [ 	]*ADD  #81h
+  42:	fe 4a [ 	]*ADD  #feh
+  44:	ff 4a [ 	]*ADD  #ffh
+  46:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  48:	02 4a [ 	]*ADD  #02h
+  4a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  4c:	81 4a [ 	]*ADD  #81h
+  4e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  50:	7f 4a [ 	]*ADD  #7fh
+	...
diff --git a/gas/testsuite/gas/maxq10/range.s b/gas/testsuite/gas/maxq10/range.s
new file mode 100644
index 000000000000..f3cdc9572ad6
--- /dev/null
+++ b/gas/testsuite/gas/maxq10/range.s
@@ -0,0 +1,30 @@
+;# checks the 8 bit ranges
+;# all negative values should contain a Prefix for MAXQ20
+;# immediate values with one operand for MAXQ10 skips PFX
+.text 
+	move A[0], #-1  
+	move Ap, #-1
+	move a[0], #1
+	move AP, #-125	; AP is an 8 bit register 
+	move AP, #-126
+	move AP, #-127
+	move A[0], #125		; A[0] is an 16 bit register - no pfx req. here
+	move A[0], #126
+	move A[0], #128
+	move A[0], #254	        ; ---------------
+	move @++SP, #-1		; check PFX generation for mem operands
+	move @++sp, #-126	; -
+	move @++sp, #254		; - no pFX here
+	move @++sp, #-127	; -
+	move @++sp, #-128	;--------------------------
+	Add #-1			;Check PFX gen. for single operand instructions
+	Add #-127
+	Add #-129
+	Add #127
+	Add #128
+	add #129
+	add #254
+	add #ffh
+	add #-254
+	add #-127
+	add #-129		; --------------------
diff --git a/gas/testsuite/gas/maxq20/bits.d b/gas/testsuite/gas/maxq20/bits.d
new file mode 100644
index 000000000000..23abe79f2866
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/bits.d
@@ -0,0 +1,95 @@
+#objdump: -dw
+#name: bit opp
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	0a ea [ 	]*MOVE C,Acc.0
+   2:	1a ea [ 	]*MOVE C,Acc.1
+   4:	2a ea [ 	]*MOVE C,Acc.2
+   6:	3a ea [ 	]*MOVE C,Acc.3
+   8:	4a ea [ 	]*MOVE C,Acc.4
+   a:	5a ea [ 	]*MOVE C,Acc.5
+   c:	6a ea [ 	]*MOVE C,Acc.6
+   e:	7a ea [ 	]*MOVE C,Acc.7
+  10:	8a ea [ 	]*MOVE C,Acc.8
+  12:	9a ea [ 	]*MOVE C,Acc.9
+  14:	aa ea [ 	]*MOVE C,Acc.10
+  16:	ba ea [ 	]*MOVE C,Acc.11
+  18:	ca ea [ 	]*MOVE C,Acc.12
+  1a:	da ea [ 	]*MOVE C,Acc.13
+  1c:	ea ea [ 	]*MOVE C,Acc.14
+  1e:	fa ea [ 	]*MOVE C,Acc.15
+  20:	0a da [ 	]*MOVE C,#0
+  22:	1a da [ 	]*MOVE C,#1
+  24:	0a fa [ 	]*MOVE Acc.0,C
+  26:	1a fa [ 	]*MOVE Acc.1,C
+  28:	2a fa [ 	]*MOVE Acc.2,C
+  2a:	3a fa [ 	]*MOVE Acc.3,C
+  2c:	4a fa [ 	]*MOVE Acc.4,C
+  2e:	5a fa [ 	]*MOVE Acc.5,C
+  30:	6a fa [ 	]*MOVE Acc.6,C
+  32:	7a fa [ 	]*MOVE Acc.7,C
+  34:	8a fa [ 	]*MOVE Acc.8,C
+  36:	9a fa [ 	]*MOVE Acc.9,C
+  38:	aa fa [ 	]*MOVE Acc.10,C
+  3a:	ba fa [ 	]*MOVE Acc.11,C
+  3c:	ca fa [ 	]*MOVE Acc.12,C
+  3e:	da fa [ 	]*MOVE Acc.13,C
+  40:	ea fa [ 	]*MOVE Acc.14,C
+  42:	fa fa [ 	]*MOVE Acc.15,C
+  44:	2a da [ 	]*CPL C
+  46:	0a 9a [ 	]*AND Acc.0
+  48:	1a 9a [ 	]*AND Acc.1
+  4a:	2a 9a [ 	]*AND Acc.2
+  4c:	3a 9a [ 	]*AND Acc.3
+  4e:	4a 9a [ 	]*AND Acc.4
+  50:	5a 9a [ 	]*AND Acc.5
+  52:	6a 9a [ 	]*AND Acc.6
+  54:	7a 9a [ 	]*AND Acc.7
+  56:	8a 9a [ 	]*AND Acc.8
+  58:	9a 9a [ 	]*AND Acc.9
+  5a:	aa 9a [ 	]*AND Acc.10
+  5c:	ba 9a [ 	]*AND Acc.11
+  5e:	ca 9a [ 	]*AND Acc.12
+  60:	da 9a [ 	]*AND Acc.13
+  62:	ea 9a [ 	]*AND Acc.14
+  64:	fa 9a [ 	]*AND Acc.15
+  66:	0a aa [ 	]*OR Acc.0
+  68:	1a aa [ 	]*OR Acc.1
+  6a:	2a aa [ 	]*OR Acc.2
+  6c:	3a aa [ 	]*OR Acc.3
+  6e:	4a aa [ 	]*OR Acc.4
+  70:	5a aa [ 	]*OR Acc.5
+  72:	6a aa [ 	]*OR Acc.6
+  74:	7a aa [ 	]*OR Acc.7
+  76:	8a aa [ 	]*OR Acc.8
+  78:	9a aa [ 	]*OR Acc.9
+  7a:	aa aa [ 	]*OR Acc.10
+  7c:	ba aa [ 	]*OR Acc.11
+  7e:	ca aa [ 	]*OR Acc.12
+  80:	da aa [ 	]*OR Acc.13
+  82:	ea aa [ 	]*OR Acc.14
+  84:	fa aa [ 	]*OR Acc.15
+  86:	0a ba [ 	]*XOR Acc.0
+  88:	1a ba [ 	]*XOR Acc.1
+  8a:	2a ba [ 	]*XOR Acc.2
+  8c:	3a ba [ 	]*XOR Acc.3
+  8e:	4a ba [ 	]*XOR Acc.4
+  90:	5a ba [ 	]*XOR Acc.5
+  92:	6a ba [ 	]*XOR Acc.6
+  94:	7a ba [ 	]*XOR Acc.7
+  96:	8a ba [ 	]*XOR Acc.8
+  98:	9a ba [ 	]*XOR Acc.9
+  9a:	aa ba [ 	]*XOR Acc.10
+  9c:	ba ba [ 	]*XOR Acc.11
+  9e:	ca ba [ 	]*XOR Acc.12
+  a0:	da ba [ 	]*XOR Acc.13
+  a2:	ea ba [ 	]*XOR Acc.14
+  a4:	fa ba [ 	]*XOR Acc.15
+  a6:	88 97 [ 	]*MOVE C , SC.1
+  a8:	68 87 [ 	]*MOVE C , IMR.0
+  aa:	58 87 [ 	]*MOVE C , IC.0
+  ac:	48 87 [ 	]*MOVE C , PSF.0
+	...
diff --git a/gas/testsuite/gas/maxq20/bits.s b/gas/testsuite/gas/maxq20/bits.s
new file mode 100644
index 000000000000..de14aefc0391
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/bits.s
@@ -0,0 +1,92 @@
+;# bits.s
+;# checks all the bit operations in MAXQ20
+
+.text
+foo:
+ MOVE C, ACC.0	
+ MOVE C, ACC.1
+ MOVE C, ACC.2
+ MOVE C, ACC.3
+ MOVE C, ACC.4
+ MOVE C, ACC.5
+ MOVE C, ACC.6
+ MOVE C, ACC.7		;8 bits on a MAXQ10 machine
+ MOVE C, ACC.8		
+ MOVE C, ACC.9
+ MOVE C, ACC.10
+ MOVE C, ACC.11
+ MOVE C, ACC.12
+ MOVE C, ACC.13
+ MOVE C, ACC.14
+ MOVE C, ACC.15 
+ MOVE C, #0
+ MOVE C, #1
+ MOVE ACC.0, C	
+ MOVE ACC.1, C 
+ MOVE ACC.2, C
+ MOVE ACC.3, C
+ MOVE ACC.4, C
+ MOVE ACC.5, C
+ MOVE ACC.6, C
+ MOVE ACC.7, C		;8 bits on a MAXQ10 machine
+ MOVE ACC.8, C		
+ MOVE ACC.9, C
+ MOVE ACC.10, C
+ MOVE ACC.11, C
+ MOVE ACC.12, C
+ MOVE ACC.13, C
+ MOVE ACC.14, C
+ MOVE ACC.15, C
+ CPL C
+ AND ACC.0	;AND with carry
+ AND ACC.1	
+ AND ACC.2	
+ AND ACC.3	
+ AND ACC.4	
+ AND ACC.5	
+ AND ACC.6	
+ AND ACC.7	
+ AND ACC.8	
+ AND ACC.9	
+ AND ACC.10	
+ AND ACC.11	
+ AND ACC.12	
+ AND ACC.13	
+ AND ACC.14	
+ AND ACC.15	
+ OR ACC.0	;OR with carry
+ OR ACC.1	
+ OR ACC.2	
+ OR ACC.3	
+ OR ACC.4	
+ OR ACC.5	
+ OR ACC.6	
+ OR ACC.7	
+ OR ACC.8	
+ OR ACC.9	
+ OR ACC.10	
+ OR ACC.11	
+ OR ACC.12	
+ OR ACC.13	
+ OR ACC.14	
+ OR  ACC.15	
+ XOR ACC.0	;XOR with carry
+ XOR ACC.1	
+ XOR ACC.2	
+ XOR ACC.3	
+ XOR ACC.4	
+ XOR ACC.5	
+ XOR ACC.6	
+ XOR ACC.7	
+ XOR ACC.8	
+ XOR ACC.9	
+ XOR ACC.10	
+ XOR ACC.11	 
+ XOR ACC.12	
+ XOR ACC.13	
+ XOR ACC.14	;Error condition when ACC.n and n>15
+ XOR ACC.15	
+ MOVE C, SC.1
+ MOVE C, IMR.0
+ MOVE C, IC.0
+ MOVE C, PSF.0		;move program status flag bit 0
diff --git a/gas/testsuite/gas/maxq20/call.d b/gas/testsuite/gas/maxq20/call.d
new file mode 100644
index 000000000000..a8bf775e1347
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/call.d
@@ -0,0 +1,42 @@
+#objdump: -dw
+#name: call operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	02 3d [ 	]*CALL  #02h
+   2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+   4:	28 3d [ 	]*CALL  #28h
+
+0+006 <SmallCall>:
+   6:	0d 8c [ 	]*RET 
+   8:	0d ac [ 	]*RET C
+   a:	0d 9c [ 	]*RET Z
+   c:	0d dc [ 	]*RET NZ
+   e:	0d cc [ 	]*RET S
+  10:	8d 8c [ 	]*RETI 
+  12:	8d ac [ 	]*RETI C
+  14:	8d 9c [ 	]*RETI Z
+  16:	8d dc [ 	]*RETI NZ
+  18:	8d cc [ 	]*RETI S
+  1a:	10 7d [ 	]*MOVE  LC\[1\], #10h
+
+0+01c <LoopTop>:
+  1c:	ff 3d [ 	]*CALL  #ffh
+  1e:	fe 5d [ 	]*DJNZ  LC\[1\], #feh
+  20:	10 7d [ 	]*MOVE  LC\[1\], #10h
+
+0+022 <LoopTop1>:
+  22:	ff 3d [ 	]*CALL  #ffh
+	...
+ 424:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+ 426:	1c 5d [ 	]*DJNZ  LC\[1\], #1ch
+
+0+428 <LongCall>:
+ 428:	8d 8c [ 	]*RETI 
+ 42a:	8d ac [ 	]*RETI C
+ 42c:	8d 9c [ 	]*RETI Z
+ 42e:	8d dc [ 	]*RETI NZ
+ 430:	8d cc [ 	]*RETI S
+	...
diff --git a/gas/testsuite/gas/maxq20/call.s b/gas/testsuite/gas/maxq20/call.s
new file mode 100644
index 000000000000..0762726b608f
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/call.s
@@ -0,0 +1,32 @@
+;# calls.s
+;# check program flow instruction involving CALL & RET
+.text
+foo:
+	Call SmallCall
+	Call LongCall
+SmallCall:
+	RET
+	RET C
+	RET Z
+	RET NZ
+	RET S	
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
+	MOVE LC[1], #10h
+LoopTop:
+	Call LoopTop
+	DJNZ LC[1], LoopTop
+	MOVE LC[1], #10h
+LoopTop1:
+	Call LoopTop1
+	.fill 0x200, 2, 0 
+	DJNZ LC[1], LoopTop	
+LongCall:
+	RETI
+	RETI C
+	RETI Z
+	RETI NZ
+	RETI S
diff --git a/gas/testsuite/gas/maxq20/data1.d b/gas/testsuite/gas/maxq20/data1.d
new file mode 100644
index 000000000000..e394f7a36448
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data1.d
@@ -0,0 +1,119 @@
+#objdump:-dw
+#name: 1st  Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	8a 8a [ 	]*XCH 
+   2:	7a 8a [ 	]*XCHN 
+   4:	01 76 [ 	]*MOVE  NUL, #01h
+   6:	08 f6 [ 	]*MOVE  NUL, AP
+   8:	18 f6 [ 	]*MOVE  NUL, APC
+   a:	48 f6 [ 	]*MOVE  NUL, PSF
+   c:	58 f6 [ 	]*MOVE  NUL, IC
+   e:	68 f6 [ 	]*MOVE  NUL, IMR
+  10:	88 f6 [ 	]*MOVE  NUL, SC
+  12:	b8 f6 [ 	]*MOVE  NUL, IIR
+  14:	e8 f6 [ 	]*MOVE  NUL, CKCN
+  16:	f8 f6 [ 	]*MOVE  NUL, WDCN
+  18:	09 f6 [ 	]*MOVE  NUL, A\[0\]
+  1a:	f9 f6 [ 	]*MOVE  NUL, A\[15\]
+  1c:	0a f6 [ 	]*MOVE  NUL, ACC
+  1e:	1a f6 [ 	]*MOVE  NUL, A\[AP\]
+  20:	0c f6 [ 	]*MOVE  NUL, IP
+  22:	0d f6 [ 	]*POP  NUL
+  24:	1d f6 [ 	]*MOVE  NUL, SP
+  26:	2d f6 [ 	]*MOVE  NUL, IV
+  28:	6d f6 [ 	]*MOVE  NUL, LC\[0\]
+  2a:	7d f6 [ 	]*MOVE  NUL, LC\[1\]
+  2c:	1e f6 [ 	]*MOVE  NUL, @BP\[OFFS\+\+\]
+  2e:	2e f6 [ 	]*MOVE  NUL, @BP\[OFFS\-\-\]
+  30:	3e f6 [ 	]*MOVE  NUL, OFFS
+  32:	4e f6 [ 	]*MOVE  NUL, DPC
+  34:	5e f6 [ 	]*MOVE  NUL, GR
+  36:	6e f6 [ 	]*MOVE  NUL, GRL
+  38:	7e f6 [ 	]*MOVE  NUL, BP
+  3a:	8e f6 [ 	]*MOVE  NUL, GRS
+  3c:	9e f6 [ 	]*MOVE  NUL, GRH
+  3e:	ae f6 [ 	]*MOVE  NUL, GRXL
+  40:	be f6 [ 	]*MOVE  NUL, FP
+  42:	0f f6 [ 	]*MOVE  NUL, @DP\[0\]
+  44:	4f f6 [ 	]*MOVE  NUL, @DP\[1\]
+  46:	1f f6 [ 	]*MOVE  NUL, @DP\[0\]\+\+
+  48:	5f f6 [ 	]*MOVE  NUL, @DP\[1\]\+\+
+  4a:	2f f6 [ 	]*MOVE  NUL, @DP\[0\]\-\-
+  4c:	6f f6 [ 	]*MOVE  NUL, @DP\[1\]\-\-
+  4e:	01 08 [ 	]*MOVE  AP, #01h
+  50:	18 88 [ 	]*MOVE  AP, APC
+  52:	48 88 [ 	]*MOVE  AP, PSF
+  54:	58 88 [ 	]*MOVE  AP, IC
+  56:	68 88 [ 	]*MOVE  AP, IMR
+  58:	88 88 [ 	]*MOVE  AP, SC
+  5a:	b8 88 [ 	]*MOVE  AP, IIR
+  5c:	e8 88 [ 	]*MOVE  AP, CKCN
+  5e:	f8 88 [ 	]*MOVE  AP, WDCN
+  60:	09 88 [ 	]*MOVE  AP, A\[0\]
+  62:	f9 88 [ 	]*MOVE  AP, A\[15\]
+  64:	0a 88 [ 	]*MOVE  AP, ACC
+  66:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+  68:	0c 88 [ 	]*MOVE  AP, IP
+  6a:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+  6c:	1d 88 [ 	]*MOVE  AP, SP
+  6e:	2d 88 [ 	]*MOVE  AP, IV
+  70:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+  72:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+  74:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+  76:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+  78:	3e 88 [ 	]*MOVE  AP, OFFS
+  7a:	4e 88 [ 	]*MOVE  AP, DPC
+  7c:	5e 88 [ 	]*MOVE  AP, GR
+  7e:	6e 88 [ 	]*MOVE  AP, GRL
+  80:	7e 88 [ 	]*MOVE  AP, BP
+  82:	8e 88 [ 	]*MOVE  AP, GRS
+  84:	9e 88 [ 	]*MOVE  AP, GRH
+  86:	ae 88 [ 	]*MOVE  AP, GRXL
+  88:	be 88 [ 	]*MOVE  AP, FP
+  8a:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+  8c:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+  8e:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+  90:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+  92:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+  94:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+  96:	01 18 [ 	]*MOVE  APC, #01h
+  98:	08 98 [ 	]*MOVE  APC, AP
+  9a:	48 98 [ 	]*MOVE  APC, PSF
+  9c:	58 98 [ 	]*MOVE  APC, IC
+  9e:	68 98 [ 	]*MOVE  APC, IMR
+  a0:	88 98 [ 	]*MOVE  APC, SC
+  a2:	b8 98 [ 	]*MOVE  APC, IIR
+  a4:	e8 98 [ 	]*MOVE  APC, CKCN
+  a6:	f8 98 [ 	]*MOVE  APC, WDCN
+  a8:	09 98 [ 	]*MOVE  APC, A\[0\]
+  aa:	f9 98 [ 	]*MOVE  APC, A\[15\]
+  ac:	0a 98 [ 	]*MOVE  APC, ACC
+  ae:	1a 98 [ 	]*MOVE  APC, A\[AP\]
+  b0:	0c 98 [ 	]*MOVE  APC, IP
+  b2:	0d 98 [ 	]*MOVE  APC, @SP\-\-
+  b4:	1d 98 [ 	]*MOVE  APC, SP
+  b6:	2d 98 [ 	]*MOVE  APC, IV
+  b8:	6d 98 [ 	]*MOVE  APC, LC\[0\]
+  ba:	7d 98 [ 	]*MOVE  APC, LC\[1\]
+  bc:	1e 98 [ 	]*MOVE  APC, @BP\[OFFS\+\+\]
+  be:	2e 98 [ 	]*MOVE  APC, @BP\[OFFS\-\-\]
+  c0:	3e 98 [ 	]*MOVE  APC, OFFS
+  c2:	4e 98 [ 	]*MOVE  APC, DPC
+  c4:	5e 98 [ 	]*MOVE  APC, GR
+  c6:	6e 98 [ 	]*MOVE  APC, GRL
+  c8:	7e 98 [ 	]*MOVE  APC, BP
+  ca:	8e 98 [ 	]*MOVE  APC, GRS
+  cc:	9e 98 [ 	]*MOVE  APC, GRH
+  ce:	ae 98 [ 	]*MOVE  APC, GRXL
+  d0:	be 98 [ 	]*MOVE  APC, FP
+  d2:	0f 98 [ 	]*MOVE  APC, @DP\[0\]
+  d4:	4f 98 [ 	]*MOVE  APC, @DP\[1\]
+  d6:	1f 98 [ 	]*MOVE  APC, @DP\[0\]\+\+
+  d8:	5f 98 [ 	]*MOVE  APC, @DP\[1\]\+\+
+  da:	2f 98 [ 	]*MOVE  APC, @DP\[0\]\-\-
+  dc:	6f 98 [ 	]*MOVE  APC, @DP\[1\]\-\-
+	...
diff --git a/gas/testsuite/gas/maxq20/data1.s b/gas/testsuite/gas/maxq20/data1.s
new file mode 100644
index 000000000000..a9b680ea6267
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data1.s
@@ -0,0 +1,114 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	XCH	
+	XCHN
+	MOVE NUL, #01h
+	MOVE NUL, AP
+	MOVE NUL, APC
+	MOVE NUL, PSF
+	MOVE NUL, IC
+	MOVE NUL, IMR
+	MOVE NUL, SC
+	MOVE NUL, IIR
+	MOVE NUL, CKCN
+	MOVE NUL, WDCN
+	MOVE NUL, A[0]		;Just Check two boundary conditions
+	MOVE NUL, A[15]   
+	MOVE NUL, ACC
+	MOVE NUL, A[AP]
+	MOVE NUL, IP
+	MOVE NUL, @SP--
+	MOVE NUL, SP
+	MOVE NUL, IV
+	MOVE NUL, LC[0]
+	MOVE NUL, LC[1]
+	MOVE NUL, @BP[OFFS++]
+	MOVE NUL, @BP[OFFS--]
+	MOVE NUL, OFFS
+	MOVE NUL, DPC
+	MOVE NUL, GR
+	MOVE NUL, GRL
+	MOVE NUL, BP
+	MOVE NUL, GRS
+	MOVE NUL, GRH
+	MOVE NUL, GRXL
+	MOVE NUL, FP
+	MOVE NUL, @DP[0]	
+	MOVE NUL, @DP[1]	
+	MOVE NUL, @DP[0]++		
+	MOVE NUL, @DP[1]++
+	MOVE NUL, @DP[0]--
+	MOVE NUL, @DP[1]--
+	MOVE AP, #01h
+	MOVE AP, APC
+	MOVE AP, PSF
+	MOVE AP, IC
+	MOVE AP, IMR
+	MOVE AP, SC
+	MOVE AP, IIR
+	MOVE AP, CKCN
+	MOVE AP, WDCN
+	MOVE AP, A[0]		;Just Check two boundary conditions
+	MOVE AP, A[15]   
+	MOVE AP, ACC
+	MOVE AP, A[AP]
+	MOVE AP, IP
+	MOVE AP, @SP--
+	MOVE AP, SP
+	MOVE AP, IV
+	MOVE AP, LC[0]
+	MOVE AP, LC[1]
+	MOVE AP, @BP[OFFS++]
+	MOVE AP, @BP[OFFS--]
+	MOVE AP, OFFS
+	MOVE AP, DPC
+	MOVE AP, GR
+	MOVE AP, GRL
+	MOVE AP, BP
+	MOVE AP, GRS
+	MOVE AP, GRH
+	MOVE AP, GRXL
+	MOVE AP, FP
+	MOVE AP, @DP[0]	
+	MOVE AP, @DP[1]	
+	MOVE AP, @DP[0]++		
+	MOVE AP, @DP[1]++
+	MOVE AP, @DP[0]--
+	MOVE AP, @DP[1]--
+	MOVE APC, #01h
+	MOVE APC, AP
+	MOVE APC, PSF
+	MOVE APC, IC
+	MOVE APC, IMR
+	MOVE APC, SC
+	MOVE APC, IIR
+	MOVE APC, CKCN
+	MOVE APC, WDCN
+	MOVE APC, A[0]		;Just Check two boundary conditions
+	MOVE APC, A[15]   
+	MOVE APC, ACC
+	MOVE APC, A[AP]
+	MOVE APC, IP
+	MOVE APC, @SP--
+	MOVE APC, SP
+	MOVE APC, IV
+	MOVE APC, LC[0]
+	MOVE APC, LC[1]
+	MOVE APC, @BP[OFFS++]
+	MOVE APC, @BP[OFFS--]
+	MOVE APC, OFFS
+	MOVE APC, DPC
+	MOVE APC, GR
+	MOVE APC, GRL
+	MOVE APC, BP
+	MOVE APC, GRS
+	MOVE APC, GRH
+	MOVE APC, GRXL
+	MOVE APC, FP
+	MOVE APC, @DP[0]	
+	MOVE APC, @DP[1]	
+	MOVE APC, @DP[0]++		
+	MOVE APC, @DP[1]++
+	MOVE APC, @DP[0]--
+	MOVE APC, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/data2.d b/gas/testsuite/gas/maxq20/data2.d
new file mode 100644
index 000000000000..d0fc20528191
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data2.d
@@ -0,0 +1,459 @@
+#objdump: -dw
+#name: 2nd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 48 [ 	]*MOVE  PSF, #01h
+   2:	08 c8 [ 	]*MOVE  PSF, AP
+   4:	18 c8 [ 	]*MOVE  PSF, APC
+   6:	58 c8 [ 	]*MOVE  PSF, IC
+   8:	68 c8 [ 	]*MOVE  PSF, IMR
+   a:	88 c8 [ 	]*MOVE  PSF, SC
+   c:	b8 c8 [ 	]*MOVE  PSF, IIR
+   e:	e8 c8 [ 	]*MOVE  PSF, CKCN
+  10:	f8 c8 [ 	]*MOVE  PSF, WDCN
+  12:	09 c8 [ 	]*MOVE  PSF, A\[0\]
+  14:	f9 c8 [ 	]*MOVE  PSF, A\[15\]
+  16:	0a c8 [ 	]*MOVE  PSF, ACC
+  18:	1a c8 [ 	]*MOVE  PSF, A\[AP\]
+  1a:	0c c8 [ 	]*MOVE  PSF, IP
+  1c:	0d c8 [ 	]*MOVE  PSF, @SP\-\-
+  1e:	1d c8 [ 	]*MOVE  PSF, SP
+  20:	2d c8 [ 	]*MOVE  PSF, IV
+  22:	6d c8 [ 	]*MOVE  PSF, LC\[0\]
+  24:	7d c8 [ 	]*MOVE  PSF, LC\[1\]
+  26:	1e c8 [ 	]*MOVE  PSF, @BP\[OFFS\+\+\]
+  28:	2e c8 [ 	]*MOVE  PSF, @BP\[OFFS\-\-\]
+  2a:	3e c8 [ 	]*MOVE  PSF, OFFS
+  2c:	4e c8 [ 	]*MOVE  PSF, DPC
+  2e:	5e c8 [ 	]*MOVE  PSF, GR
+  30:	6e c8 [ 	]*MOVE  PSF, GRL
+  32:	7e c8 [ 	]*MOVE  PSF, BP
+  34:	8e c8 [ 	]*MOVE  PSF, GRS
+  36:	9e c8 [ 	]*MOVE  PSF, GRH
+  38:	ae c8 [ 	]*MOVE  PSF, GRXL
+  3a:	be c8 [ 	]*MOVE  PSF, FP
+  3c:	0f c8 [ 	]*MOVE  PSF, @DP\[0\]
+  3e:	4f c8 [ 	]*MOVE  PSF, @DP\[1\]
+  40:	1f c8 [ 	]*MOVE  PSF, @DP\[0\]\+\+
+  42:	5f c8 [ 	]*MOVE  PSF, @DP\[1\]\+\+
+  44:	2f c8 [ 	]*MOVE  PSF, @DP\[0\]\-\-
+  46:	6f c8 [ 	]*MOVE  PSF, @DP\[1\]\-\-
+  48:	01 58 [ 	]*MOVE  IC, #01h
+  4a:	08 d8 [ 	]*MOVE  IC, AP
+  4c:	18 d8 [ 	]*MOVE  IC, APC
+  4e:	48 d8 [ 	]*MOVE  IC, PSF
+  50:	68 d8 [ 	]*MOVE  IC, IMR
+  52:	88 d8 [ 	]*MOVE  IC, SC
+  54:	b8 d8 [ 	]*MOVE  IC, IIR
+  56:	e8 d8 [ 	]*MOVE  IC, CKCN
+  58:	f8 d8 [ 	]*MOVE  IC, WDCN
+  5a:	09 d8 [ 	]*MOVE  IC, A\[0\]
+  5c:	f9 d8 [ 	]*MOVE  IC, A\[15\]
+  5e:	0a d8 [ 	]*MOVE  IC, ACC
+  60:	1a d8 [ 	]*MOVE  IC, A\[AP\]
+  62:	0c d8 [ 	]*MOVE  IC, IP
+  64:	0d d8 [ 	]*MOVE  IC, @SP\-\-
+  66:	1d d8 [ 	]*MOVE  IC, SP
+  68:	2d d8 [ 	]*MOVE  IC, IV
+  6a:	6d d8 [ 	]*MOVE  IC, LC\[0\]
+  6c:	7d d8 [ 	]*MOVE  IC, LC\[1\]
+  6e:	1e d8 [ 	]*MOVE  IC, @BP\[OFFS\+\+\]
+  70:	2e d8 [ 	]*MOVE  IC, @BP\[OFFS\-\-\]
+  72:	3e d8 [ 	]*MOVE  IC, OFFS
+  74:	4e d8 [ 	]*MOVE  IC, DPC
+  76:	5e d8 [ 	]*MOVE  IC, GR
+  78:	6e d8 [ 	]*MOVE  IC, GRL
+  7a:	7e d8 [ 	]*MOVE  IC, BP
+  7c:	8e d8 [ 	]*MOVE  IC, GRS
+  7e:	9e d8 [ 	]*MOVE  IC, GRH
+  80:	ae d8 [ 	]*MOVE  IC, GRXL
+  82:	be d8 [ 	]*MOVE  IC, FP
+  84:	0f d8 [ 	]*MOVE  IC, @DP\[0\]
+  86:	4f d8 [ 	]*MOVE  IC, @DP\[1\]
+  88:	1f d8 [ 	]*MOVE  IC, @DP\[0\]\+\+
+  8a:	5f d8 [ 	]*MOVE  IC, @DP\[1\]\+\+
+  8c:	2f d8 [ 	]*MOVE  IC, @DP\[0\]\-\-
+  8e:	6f d8 [ 	]*MOVE  IC, @DP\[1\]\-\-
+  90:	01 68 [ 	]*MOVE  IMR, #01h
+  92:	08 e8 [ 	]*MOVE  IMR, AP
+  94:	18 e8 [ 	]*MOVE  IMR, APC
+  96:	48 e8 [ 	]*MOVE  IMR, PSF
+  98:	58 e8 [ 	]*MOVE  IMR, IC
+  9a:	88 e8 [ 	]*MOVE  IMR, SC
+  9c:	b8 e8 [ 	]*MOVE  IMR, IIR
+  9e:	e8 e8 [ 	]*MOVE  IMR, CKCN
+  a0:	f8 e8 [ 	]*MOVE  IMR, WDCN
+  a2:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+  a4:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+  a6:	0a e8 [ 	]*MOVE  IMR, ACC
+  a8:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+  aa:	0c e8 [ 	]*MOVE  IMR, IP
+  ac:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+  ae:	1d e8 [ 	]*MOVE  IMR, SP
+  b0:	2d e8 [ 	]*MOVE  IMR, IV
+  b2:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+  b4:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+  b6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+  b8:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+  ba:	3e e8 [ 	]*MOVE  IMR, OFFS
+  bc:	4e e8 [ 	]*MOVE  IMR, DPC
+  be:	5e e8 [ 	]*MOVE  IMR, GR
+  c0:	6e e8 [ 	]*MOVE  IMR, GRL
+  c2:	7e e8 [ 	]*MOVE  IMR, BP
+  c4:	8e e8 [ 	]*MOVE  IMR, GRS
+  c6:	9e e8 [ 	]*MOVE  IMR, GRH
+  c8:	ae e8 [ 	]*MOVE  IMR, GRXL
+  ca:	be e8 [ 	]*MOVE  IMR, FP
+  cc:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+  ce:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+  d0:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+  d2:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+  d4:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+  d6:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+  d8:	01 09 [ 	]*MOVE  A\[0\], #01h
+  da:	08 89 [ 	]*MOVE  A\[0\], AP
+  dc:	18 89 [ 	]*MOVE  A\[0\], APC
+  de:	48 89 [ 	]*MOVE  A\[0\], PSF
+  e0:	58 89 [ 	]*MOVE  A\[0\], IC
+  e2:	68 89 [ 	]*MOVE  A\[0\], IMR
+  e4:	88 89 [ 	]*MOVE  A\[0\], SC
+  e6:	b8 89 [ 	]*MOVE  A\[0\], IIR
+  e8:	e8 89 [ 	]*MOVE  A\[0\], CKCN
+  ea:	f8 89 [ 	]*MOVE  A\[0\], WDCN
+  ec:	0a 89 [ 	]*MOVE  A\[0\], ACC
+  ee:	1a 89 [ 	]*MOVE  A\[0\], A\[AP\]
+  f0:	0c 89 [ 	]*MOVE  A\[0\], IP
+  f2:	0d 89 [ 	]*MOVE  A\[0\], @SP\-\-
+  f4:	1d 89 [ 	]*MOVE  A\[0\], SP
+  f6:	2d 89 [ 	]*MOVE  A\[0\], IV
+  f8:	6d 89 [ 	]*MOVE  A\[0\], LC\[0\]
+  fa:	7d 89 [ 	]*MOVE  A\[0\], LC\[1\]
+  fc:	1e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\+\+\]
+  fe:	2e 89 [ 	]*MOVE  A\[0\], @BP\[OFFS\-\-\]
+ 100:	3e 89 [ 	]*MOVE  A\[0\], OFFS
+ 102:	4e 89 [ 	]*MOVE  A\[0\], DPC
+ 104:	5e 89 [ 	]*MOVE  A\[0\], GR
+ 106:	6e 89 [ 	]*MOVE  A\[0\], GRL
+ 108:	7e 89 [ 	]*MOVE  A\[0\], BP
+ 10a:	8e 89 [ 	]*MOVE  A\[0\], GRS
+ 10c:	9e 89 [ 	]*MOVE  A\[0\], GRH
+ 10e:	ae 89 [ 	]*MOVE  A\[0\], GRXL
+ 110:	be 89 [ 	]*MOVE  A\[0\], FP
+ 112:	0f 89 [ 	]*MOVE  A\[0\], @DP\[0\]
+ 114:	4f 89 [ 	]*MOVE  A\[0\], @DP\[1\]
+ 116:	1f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\+\+
+ 118:	5f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\+\+
+ 11a:	2f 89 [ 	]*MOVE  A\[0\], @DP\[0\]\-\-
+ 11c:	6f 89 [ 	]*MOVE  A\[0\], @DP\[1\]\-\-
+ 11e:	01 0a [ 	]*MOVE  ACC, #01h
+ 120:	08 8a [ 	]*MOVE  ACC, AP
+ 122:	18 8a [ 	]*MOVE  ACC, APC
+ 124:	48 8a [ 	]*MOVE  ACC, PSF
+ 126:	58 8a [ 	]*MOVE  ACC, IC
+ 128:	68 8a [ 	]*MOVE  ACC, IMR
+ 12a:	88 8a [ 	]*MOVE  ACC, SC
+ 12c:	b8 8a [ 	]*MOVE  ACC, IIR
+ 12e:	e8 8a [ 	]*MOVE  ACC, CKCN
+ 130:	f8 8a [ 	]*MOVE  ACC, WDCN
+ 132:	09 8a [ 	]*MOVE  ACC, A\[0\]
+ 134:	f9 8a [ 	]*MOVE  ACC, A\[15\]
+ 136:	0c 8a [ 	]*MOVE  ACC, IP
+ 138:	0d 8a [ 	]*MOVE  ACC, @SP\-\-
+ 13a:	1d 8a [ 	]*MOVE  ACC, SP
+ 13c:	2d 8a [ 	]*MOVE  ACC, IV
+ 13e:	6d 8a [ 	]*MOVE  ACC, LC\[0\]
+ 140:	7d 8a [ 	]*MOVE  ACC, LC\[1\]
+ 142:	1e 8a [ 	]*MOVE  ACC, @BP\[OFFS\+\+\]
+ 144:	2e 8a [ 	]*MOVE  ACC, @BP\[OFFS\-\-\]
+ 146:	3e 8a [ 	]*MOVE  ACC, OFFS
+ 148:	4e 8a [ 	]*MOVE  ACC, DPC
+ 14a:	5e 8a [ 	]*MOVE  ACC, GR
+ 14c:	6e 8a [ 	]*MOVE  ACC, GRL
+ 14e:	7e 8a [ 	]*MOVE  ACC, BP
+ 150:	8e 8a [ 	]*MOVE  ACC, GRS
+ 152:	9e 8a [ 	]*MOVE  ACC, GRH
+ 154:	ae 8a [ 	]*MOVE  ACC, GRXL
+ 156:	be 8a [ 	]*MOVE  ACC, FP
+ 158:	0f 8a [ 	]*MOVE  ACC, @DP\[0\]
+ 15a:	4f 8a [ 	]*MOVE  ACC, @DP\[1\]
+ 15c:	1f 8a [ 	]*MOVE  ACC, @DP\[0\]\+\+
+ 15e:	5f 8a [ 	]*MOVE  ACC, @DP\[1\]\+\+
+ 160:	2f 8a [ 	]*MOVE  ACC, @DP\[0\]\-\-
+ 162:	6f 8a [ 	]*MOVE  ACC, @DP\[1\]\-\-
+ 164:	01 0d [ 	]*MOVE  @\+\+SP, #01h
+ 166:	08 8d [ 	]*MOVE  @\+\+SP, AP
+ 168:	18 8d [ 	]*MOVE  @\+\+SP, APC
+ 16a:	48 8d [ 	]*MOVE  @\+\+SP, PSF
+ 16c:	58 8d [ 	]*MOVE  @\+\+SP, IC
+ 16e:	68 8d [ 	]*MOVE  @\+\+SP, IMR
+ 170:	88 8d [ 	]*MOVE  @\+\+SP, SC
+ 172:	b8 8d [ 	]*MOVE  @\+\+SP, IIR
+ 174:	e8 8d [ 	]*MOVE  @\+\+SP, CKCN
+ 176:	f8 8d [ 	]*MOVE  @\+\+SP, WDCN
+ 178:	09 8d [ 	]*MOVE  @\+\+SP, A\[0\]
+ 17a:	f9 8d [ 	]*MOVE  @\+\+SP, A\[15\]
+ 17c:	0a 8d [ 	]*MOVE  @\+\+SP, ACC
+ 17e:	1a 8d [ 	]*MOVE  @\+\+SP, A\[AP\]
+ 180:	0c 8d [ 	]*MOVE  @\+\+SP, IP
+ 182:	1d 8d [ 	]*MOVE  @\+\+SP, SP
+ 184:	2d 8d [ 	]*MOVE  @\+\+SP, IV
+ 186:	6d 8d [ 	]*MOVE  @\+\+SP, LC\[0\]
+ 188:	7d 8d [ 	]*MOVE  @\+\+SP, LC\[1\]
+ 18a:	1e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\+\+\]
+ 18c:	2e 8d [ 	]*MOVE  @\+\+SP, @BP\[OFFS\-\-\]
+ 18e:	3e 8d [ 	]*MOVE  @\+\+SP, OFFS
+ 190:	4e 8d [ 	]*MOVE  @\+\+SP, DPC
+ 192:	5e 8d [ 	]*MOVE  @\+\+SP, GR
+ 194:	6e 8d [ 	]*MOVE  @\+\+SP, GRL
+ 196:	7e 8d [ 	]*MOVE  @\+\+SP, BP
+ 198:	8e 8d [ 	]*MOVE  @\+\+SP, GRS
+ 19a:	9e 8d [ 	]*MOVE  @\+\+SP, GRH
+ 19c:	ae 8d [ 	]*MOVE  @\+\+SP, GRXL
+ 19e:	be 8d [ 	]*MOVE  @\+\+SP, FP
+ 1a0:	0f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]
+ 1a2:	4f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]
+ 1a4:	1f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\+\+
+ 1a6:	5f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\+\+
+ 1a8:	2f 8d [ 	]*MOVE  @\+\+SP, @DP\[0\]\-\-
+ 1aa:	6f 8d [ 	]*MOVE  @\+\+SP, @DP\[1\]\-\-
+ 1ac:	01 1d [ 	]*MOVE  SP, #01h
+ 1ae:	08 9d [ 	]*MOVE  SP, AP
+ 1b0:	18 9d [ 	]*MOVE  SP, APC
+ 1b2:	48 9d [ 	]*MOVE  SP, PSF
+ 1b4:	58 9d [ 	]*MOVE  SP, IC
+ 1b6:	68 9d [ 	]*MOVE  SP, IMR
+ 1b8:	88 9d [ 	]*MOVE  SP, SC
+ 1ba:	b8 9d [ 	]*MOVE  SP, IIR
+ 1bc:	e8 9d [ 	]*MOVE  SP, CKCN
+ 1be:	f8 9d [ 	]*MOVE  SP, WDCN
+ 1c0:	09 9d [ 	]*MOVE  SP, A\[0\]
+ 1c2:	f9 9d [ 	]*MOVE  SP, A\[15\]
+ 1c4:	0a 9d [ 	]*MOVE  SP, ACC
+ 1c6:	1a 9d [ 	]*MOVE  SP, A\[AP\]
+ 1c8:	0c 9d [ 	]*MOVE  SP, IP
+ 1ca:	2d 9d [ 	]*MOVE  SP, IV
+ 1cc:	6d 9d [ 	]*MOVE  SP, LC\[0\]
+ 1ce:	7d 9d [ 	]*MOVE  SP, LC\[1\]
+ 1d0:	1e 9d [ 	]*MOVE  SP, @BP\[OFFS\+\+\]
+ 1d2:	2e 9d [ 	]*MOVE  SP, @BP\[OFFS\-\-\]
+ 1d4:	3e 9d [ 	]*MOVE  SP, OFFS
+ 1d6:	4e 9d [ 	]*MOVE  SP, DPC
+ 1d8:	5e 9d [ 	]*MOVE  SP, GR
+ 1da:	6e 9d [ 	]*MOVE  SP, GRL
+ 1dc:	7e 9d [ 	]*MOVE  SP, BP
+ 1de:	8e 9d [ 	]*MOVE  SP, GRS
+ 1e0:	9e 9d [ 	]*MOVE  SP, GRH
+ 1e2:	ae 9d [ 	]*MOVE  SP, GRXL
+ 1e4:	be 9d [ 	]*MOVE  SP, FP
+ 1e6:	0f 9d [ 	]*MOVE  SP, @DP\[0\]
+ 1e8:	4f 9d [ 	]*MOVE  SP, @DP\[1\]
+ 1ea:	1f 9d [ 	]*MOVE  SP, @DP\[0\]\+\+
+ 1ec:	5f 9d [ 	]*MOVE  SP, @DP\[1\]\+\+
+ 1ee:	2f 9d [ 	]*MOVE  SP, @DP\[0\]\-\-
+ 1f0:	6f 9d [ 	]*MOVE  SP, @DP\[1\]\-\-
+ 1f2:	01 2d [ 	]*MOVE  IV, #01h
+ 1f4:	08 ad [ 	]*MOVE  IV, AP
+ 1f6:	18 ad [ 	]*MOVE  IV, APC
+ 1f8:	48 ad [ 	]*MOVE  IV, PSF
+ 1fa:	58 ad [ 	]*MOVE  IV, IC
+ 1fc:	68 ad [ 	]*MOVE  IV, IMR
+ 1fe:	88 ad [ 	]*MOVE  IV, SC
+ 200:	b8 ad [ 	]*MOVE  IV, IIR
+ 202:	e8 ad [ 	]*MOVE  IV, CKCN
+ 204:	f8 ad [ 	]*MOVE  IV, WDCN
+ 206:	09 ad [ 	]*MOVE  IV, A\[0\]
+ 208:	f9 ad [ 	]*MOVE  IV, A\[15\]
+ 20a:	0a ad [ 	]*MOVE  IV, ACC
+ 20c:	1a ad [ 	]*MOVE  IV, A\[AP\]
+ 20e:	0c ad [ 	]*MOVE  IV, IP
+ 210:	0d ad [ 	]*MOVE  IV, @SP\-\-
+ 212:	1d ad [ 	]*MOVE  IV, SP
+ 214:	2d ad [ 	]*MOVE  IV, IV
+ 216:	6d ad [ 	]*MOVE  IV, LC\[0\]
+ 218:	7d ad [ 	]*MOVE  IV, LC\[1\]
+ 21a:	1e ad [ 	]*MOVE  IV, @BP\[OFFS\+\+\]
+ 21c:	2e ad [ 	]*MOVE  IV, @BP\[OFFS\-\-\]
+ 21e:	3e ad [ 	]*MOVE  IV, OFFS
+ 220:	4e ad [ 	]*MOVE  IV, DPC
+ 222:	5e ad [ 	]*MOVE  IV, GR
+ 224:	6e ad [ 	]*MOVE  IV, GRL
+ 226:	7e ad [ 	]*MOVE  IV, BP
+ 228:	8e ad [ 	]*MOVE  IV, GRS
+ 22a:	9e ad [ 	]*MOVE  IV, GRH
+ 22c:	ae ad [ 	]*MOVE  IV, GRXL
+ 22e:	be ad [ 	]*MOVE  IV, FP
+ 230:	0f ad [ 	]*MOVE  IV, @DP\[0\]
+ 232:	4f ad [ 	]*MOVE  IV, @DP\[1\]
+ 234:	1f ad [ 	]*MOVE  IV, @DP\[0\]\+\+
+ 236:	5f ad [ 	]*MOVE  IV, @DP\[1\]\+\+
+ 238:	2f ad [ 	]*MOVE  IV, @DP\[0\]\-\-
+ 23a:	6f ad [ 	]*MOVE  IV, @DP\[1\]\-\-
+ 23c:	01 6d [ 	]*MOVE  LC\[0\], #01h
+ 23e:	08 ed [ 	]*MOVE  LC\[0\], AP
+ 240:	18 ed [ 	]*MOVE  LC\[0\], APC
+ 242:	48 ed [ 	]*MOVE  LC\[0\], PSF
+ 244:	58 ed [ 	]*MOVE  LC\[0\], IC
+ 246:	68 ed [ 	]*MOVE  LC\[0\], IMR
+ 248:	88 ed [ 	]*MOVE  LC\[0\], SC
+ 24a:	b8 ed [ 	]*MOVE  LC\[0\], IIR
+ 24c:	e8 ed [ 	]*MOVE  LC\[0\], CKCN
+ 24e:	f8 ed [ 	]*MOVE  LC\[0\], WDCN
+ 250:	09 ed [ 	]*MOVE  LC\[0\], A\[0\]
+ 252:	f9 ed [ 	]*MOVE  LC\[0\], A\[15\]
+ 254:	0a ed [ 	]*MOVE  LC\[0\], ACC
+ 256:	1a ed [ 	]*MOVE  LC\[0\], A\[AP\]
+ 258:	0c ed [ 	]*MOVE  LC\[0\], IP
+ 25a:	0d ed [ 	]*MOVE  LC\[0\], @SP\-\-
+ 25c:	1d ed [ 	]*MOVE  LC\[0\], SP
+ 25e:	2d ed [ 	]*MOVE  LC\[0\], IV
+ 260:	1e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\+\+\]
+ 262:	2e ed [ 	]*MOVE  LC\[0\], @BP\[OFFS\-\-\]
+ 264:	3e ed [ 	]*MOVE  LC\[0\], OFFS
+ 266:	4e ed [ 	]*MOVE  LC\[0\], DPC
+ 268:	5e ed [ 	]*MOVE  LC\[0\], GR
+ 26a:	6e ed [ 	]*MOVE  LC\[0\], GRL
+ 26c:	7e ed [ 	]*MOVE  LC\[0\], BP
+ 26e:	8e ed [ 	]*MOVE  LC\[0\], GRS
+ 270:	9e ed [ 	]*MOVE  LC\[0\], GRH
+ 272:	ae ed [ 	]*MOVE  LC\[0\], GRXL
+ 274:	be ed [ 	]*MOVE  LC\[0\], FP
+ 276:	0f ed [ 	]*MOVE  LC\[0\], @DP\[0\]
+ 278:	4f ed [ 	]*MOVE  LC\[0\], @DP\[1\]
+ 27a:	1f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\+\+
+ 27c:	5f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\+\+
+ 27e:	2f ed [ 	]*MOVE  LC\[0\], @DP\[0\]\-\-
+ 280:	6f ed [ 	]*MOVE  LC\[0\], @DP\[1\]\-\-
+ 282:	01 0e [ 	]*MOVE  @BP\[OFFS\], #01h
+ 284:	08 8e [ 	]*MOVE  @BP\[OFFS\], AP
+ 286:	18 8e [ 	]*MOVE  @BP\[OFFS\], APC
+ 288:	48 8e [ 	]*MOVE  @BP\[OFFS\], PSF
+ 28a:	58 8e [ 	]*MOVE  @BP\[OFFS\], IC
+ 28c:	68 8e [ 	]*MOVE  @BP\[OFFS\], IMR
+ 28e:	88 8e [ 	]*MOVE  @BP\[OFFS\], SC
+ 290:	b8 8e [ 	]*MOVE  @BP\[OFFS\], IIR
+ 292:	e8 8e [ 	]*MOVE  @BP\[OFFS\], CKCN
+ 294:	f8 8e [ 	]*MOVE  @BP\[OFFS\], WDCN
+ 296:	09 8e [ 	]*MOVE  @BP\[OFFS\], A\[0\]
+ 298:	f9 8e [ 	]*MOVE  @BP\[OFFS\], A\[15\]
+ 29a:	0a 8e [ 	]*MOVE  @BP\[OFFS\], ACC
+ 29c:	1a 8e [ 	]*MOVE  @BP\[OFFS\], A\[AP\]
+ 29e:	0c 8e [ 	]*MOVE  @BP\[OFFS\], IP
+ 2a0:	0d 8e [ 	]*MOVE  @BP\[OFFS\], @SP\-\-
+ 2a2:	1d 8e [ 	]*MOVE  @BP\[OFFS\], SP
+ 2a4:	2d 8e [ 	]*MOVE  @BP\[OFFS\], IV
+ 2a6:	6d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[0\]
+ 2a8:	7d 8e [ 	]*MOVE  @BP\[OFFS\], LC\[1\]
+ 2aa:	3e 8e [ 	]*MOVE  @BP\[OFFS\], OFFS
+ 2ac:	4e 8e [ 	]*MOVE  @BP\[OFFS\], DPC
+ 2ae:	5e 8e [ 	]*MOVE  @BP\[OFFS\], GR
+ 2b0:	6e 8e [ 	]*MOVE  @BP\[OFFS\], GRL
+ 2b2:	7e 8e [ 	]*MOVE  @BP\[OFFS\], BP
+ 2b4:	8e 8e [ 	]*MOVE  @BP\[OFFS\], GRS
+ 2b6:	9e 8e [ 	]*MOVE  @BP\[OFFS\], GRH
+ 2b8:	ae 8e [ 	]*MOVE  @BP\[OFFS\], GRXL
+ 2ba:	be 8e [ 	]*MOVE  @BP\[OFFS\], FP
+ 2bc:	0f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]
+ 2be:	4f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]
+ 2c0:	1f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\+\+
+ 2c2:	5f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\+\+
+ 2c4:	2f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[0\]\-\-
+ 2c6:	6f 8e [ 	]*MOVE  @BP\[OFFS\], @DP\[1\]\-\-
+ 2c8:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 2ca:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 2cc:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 2ce:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 2d0:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 2d2:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 2d4:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 2d6:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 2d8:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 2da:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 2dc:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 2de:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 2e0:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 2e2:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 2e4:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 2e6:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 2e8:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 2ea:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 2ec:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 2ee:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 2f0:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 2f2:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 2f4:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 2f6:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 2f8:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 2fa:	9e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRH
+ 2fc:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 2fe:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 300:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 302:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 304:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 306:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
+ 308:	01 2e [ 	]*MOVE  @BP\[\-\-OFFS\], #01h
+ 30a:	08 ae [ 	]*MOVE  @BP\[\-\-OFFS\], AP
+ 30c:	18 ae [ 	]*MOVE  @BP\[\-\-OFFS\], APC
+ 30e:	48 ae [ 	]*MOVE  @BP\[\-\-OFFS\], PSF
+ 310:	58 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IC
+ 312:	68 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IMR
+ 314:	88 ae [ 	]*MOVE  @BP\[\-\-OFFS\], SC
+ 316:	b8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], IIR
+ 318:	e8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], CKCN
+ 31a:	f8 ae [ 	]*MOVE  @BP\[\-\-OFFS\], WDCN
+ 31c:	09 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[0\]
+ 31e:	f9 ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[15\]
+ 320:	0a ae [ 	]*MOVE  @BP\[\-\-OFFS\], ACC
+ 322:	1a ae [ 	]*MOVE  @BP\[\-\-OFFS\], A\[AP\]
+ 324:	0c ae [ 	]*MOVE  @BP\[\-\-OFFS\], IP
+ 326:	1d ae [ 	]*MOVE  @BP\[\-\-OFFS\], SP
+ 328:	2d ae [ 	]*MOVE  @BP\[\-\-OFFS\], IV
+ 32a:	6d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[0\]
+ 32c:	7d ae [ 	]*MOVE  @BP\[\-\-OFFS\], LC\[1\]
+ 32e:	3e ae [ 	]*MOVE  @BP\[\-\-OFFS\], OFFS
+ 330:	4e ae [ 	]*MOVE  @BP\[\-\-OFFS\], DPC
+ 332:	5e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GR
+ 334:	6e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRL
+ 336:	7e ae [ 	]*MOVE  @BP\[\-\-OFFS\], BP
+ 338:	8e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRS
+ 33a:	9e ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRH
+ 33c:	ae ae [ 	]*MOVE  @BP\[\-\-OFFS\], GRXL
+ 33e:	be ae [ 	]*MOVE  @BP\[\-\-OFFS\], FP
+ 340:	0f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[0\]
+ 342:	4f ae [ 	]*MOVE  @BP\[\-\-OFFS\], @DP\[1\]
+ 344:	01 3e [ 	]*MOVE  OFFS, #01h
+ 346:	08 be [ 	]*MOVE  OFFS, AP
+ 348:	18 be [ 	]*MOVE  OFFS, APC
+ 34a:	48 be [ 	]*MOVE  OFFS, PSF
+ 34c:	58 be [ 	]*MOVE  OFFS, IC
+ 34e:	68 be [ 	]*MOVE  OFFS, IMR
+ 350:	88 be [ 	]*MOVE  OFFS, SC
+ 352:	b8 be [ 	]*MOVE  OFFS, IIR
+ 354:	e8 be [ 	]*MOVE  OFFS, CKCN
+ 356:	f8 be [ 	]*MOVE  OFFS, WDCN
+ 358:	09 be [ 	]*MOVE  OFFS, A\[0\]
+ 35a:	f9 be [ 	]*MOVE  OFFS, A\[15\]
+ 35c:	0a be [ 	]*MOVE  OFFS, ACC
+ 35e:	1a be [ 	]*MOVE  OFFS, A\[AP\]
+ 360:	0c be [ 	]*MOVE  OFFS, IP
+ 362:	0d be [ 	]*MOVE  OFFS, @SP\-\-
+ 364:	1d be [ 	]*MOVE  OFFS, SP
+ 366:	2d be [ 	]*MOVE  OFFS, IV
+ 368:	6d be [ 	]*MOVE  OFFS, LC\[0\]
+ 36a:	7d be [ 	]*MOVE  OFFS, LC\[1\]
+ 36c:	4e be [ 	]*MOVE  OFFS, DPC
+ 36e:	5e be [ 	]*MOVE  OFFS, GR
+ 370:	6e be [ 	]*MOVE  OFFS, GRL
+ 372:	7e be [ 	]*MOVE  OFFS, BP
+ 374:	8e be [ 	]*MOVE  OFFS, GRS
+ 376:	9e be [ 	]*MOVE  OFFS, GRH
+ 378:	ae be [ 	]*MOVE  OFFS, GRXL
+ 37a:	be be [ 	]*MOVE  OFFS, FP
+ 37c:	0f be [ 	]*MOVE  OFFS, @DP\[0\]
+ 37e:	4f be [ 	]*MOVE  OFFS, @DP\[1\]
+ 380:	1f be [ 	]*MOVE  OFFS, @DP\[0\]\+\+
+ 382:	5f be [ 	]*MOVE  OFFS, @DP\[1\]\+\+
+ 384:	2f be [ 	]*MOVE  OFFS, @DP\[0\]\-\-
+ 386:	6f be [ 	]*MOVE  OFFS, @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq20/data2.s b/gas/testsuite/gas/maxq20/data2.s
new file mode 100644
index 000000000000..94cc70bc59fd
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data2.s
@@ -0,0 +1,455 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE PSF, #01h
+	MOVE PSF, AP
+	MOVE PSF, APC
+	MOVE PSF, IC
+	MOVE PSF, IMR
+	MOVE PSF, SC
+	MOVE PSF, IIR
+	MOVE PSF, CKCN
+	MOVE PSF, WDCN
+	MOVE PSF, A[0]		;Just Check two boundary conditions
+	MOVE PSF, A[15]   
+	MOVE PSF, ACC
+	MOVE PSF, A[AP]
+	MOVE PSF, IP
+	MOVE PSF, @SP--
+	MOVE PSF, SP
+	MOVE PSF, IV
+	MOVE PSF, LC[0]
+	MOVE PSF, LC[1]
+	MOVE PSF, @BP[OFFS++]
+	MOVE PSF, @BP[OFFS--]
+	MOVE PSF, OFFS
+	MOVE PSF, DPC
+	MOVE PSF, GR
+	MOVE PSF, GRL
+	MOVE PSF, BP
+	MOVE PSF, GRS
+	MOVE PSF, GRH
+	MOVE PSF, GRXL
+	MOVE PSF, FP
+	MOVE PSF, @DP[0]	
+	MOVE PSF, @DP[1]	
+	MOVE PSF, @DP[0]++		
+	MOVE PSF, @DP[1]++
+	MOVE PSF, @DP[0]--
+	MOVE PSF, @DP[1]--
+	MOVE IC, #01h
+	MOVE IC, AP
+	MOVE IC, APC
+	MOVE IC, PSF
+	MOVE IC, IMR
+	MOVE IC, SC
+	MOVE IC, IIR
+	MOVE IC, CKCN
+	MOVE IC, WDCN
+	MOVE IC, A[0]		;Just Check two boundary conditions
+	MOVE IC, A[15]   
+	MOVE IC, ACC
+	MOVE IC, A[AP]
+	MOVE IC, IP
+	MOVE IC, @SP--
+	MOVE IC, SP
+	MOVE IC, IV
+	MOVE IC, LC[0]
+	MOVE IC, LC[1]
+	MOVE IC, @BP[OFFS++]
+	MOVE IC, @BP[OFFS--]
+	MOVE IC, OFFS
+	MOVE IC, DPC
+	MOVE IC, GR
+	MOVE IC, GRL
+	MOVE IC, BP
+	MOVE IC, GRS
+	MOVE IC, GRH
+	MOVE IC, GRXL
+	MOVE IC, FP
+	MOVE IC, @DP[0]	
+	MOVE IC, @DP[1]	
+	MOVE IC, @DP[0]++		
+	MOVE IC, @DP[1]++
+	MOVE IC, @DP[0]--
+	MOVE IC, @DP[1]--
+	MOVE IMR, #01h
+	MOVE IMR, AP
+	MOVE IMR, APC
+	MOVE IMR, PSF
+	MOVE IMR, IC
+	MOVE IMR, SC
+	MOVE IMR, IIR
+	MOVE IMR, CKCN
+	MOVE IMR, WDCN
+	MOVE IMR, A[0]		;Just Check two boundary conditions
+	MOVE IMR, A[15]   
+	MOVE IMR, ACC
+	MOVE IMR, A[AP]
+	MOVE IMR, IP
+	MOVE IMR, @SP--
+	MOVE IMR, SP
+	MOVE IMR, IV
+	MOVE IMR, LC[0]
+	MOVE IMR, LC[1]
+	MOVE IMR, @BP[OFFS++]
+	MOVE IMR, @BP[OFFS--]
+	MOVE IMR, OFFS
+	MOVE IMR, DPC
+	MOVE IMR, GR
+	MOVE IMR, GRL
+	MOVE IMR, BP
+	MOVE IMR, GRS
+	MOVE IMR, GRH
+	MOVE IMR, GRXL
+	MOVE IMR, FP
+	MOVE IMR, @DP[0]	
+	MOVE IMR, @DP[1]	
+	MOVE IMR, @DP[0]++		
+	MOVE IMR, @DP[1]++
+	MOVE IMR, @DP[0]--
+	MOVE IMR, @DP[1]--
+	MOVE A[0], #01h
+	MOVE A[0], AP
+	MOVE A[0], APC
+	MOVE A[0], PSF
+	MOVE A[0], IC
+	MOVE A[0], IMR
+	MOVE A[0], SC
+	MOVE A[0], IIR
+	MOVE A[0], CKCN
+	MOVE A[0], WDCN
+	MOVE A[0], ACC
+	MOVE A[0], A[AP]
+	MOVE A[0], IP
+	MOVE A[0], @SP--
+	MOVE A[0], SP
+	MOVE A[0], IV
+	MOVE A[0], LC[0]
+	MOVE A[0], LC[1]
+	MOVE A[0], @BP[OFFS++]
+	MOVE A[0], @BP[OFFS--]
+	MOVE A[0], OFFS
+	MOVE A[0], DPC
+	MOVE A[0], GR
+	MOVE A[0], GRL
+	MOVE A[0], BP
+	MOVE A[0], GRS
+	MOVE A[0], GRH
+	MOVE A[0], GRXL
+	MOVE A[0], FP
+	MOVE A[0], @DP[0]	
+	MOVE A[0], @DP[1]	
+	MOVE A[0], @DP[0]++		
+	MOVE A[0], @DP[1]++
+	MOVE A[0], @DP[0]--
+	MOVE A[0], @DP[1]--
+	MOVE ACC, #01h
+	MOVE ACC, AP
+	MOVE ACC, APC
+	MOVE ACC, PSF
+	MOVE ACC, IC
+	MOVE ACC, IMR
+	MOVE ACC, SC
+	MOVE ACC, IIR
+	MOVE ACC, CKCN
+	MOVE ACC, WDCN
+	MOVE ACC, A[0]		;Just Check two boundary conditions
+	MOVE ACC, A[15]   
+	MOVE ACC, IP
+	MOVE ACC, @SP--
+	MOVE ACC, SP
+	MOVE ACC, IV
+	MOVE ACC, LC[0]
+	MOVE ACC, LC[1]
+	MOVE ACC, @BP[OFFS++]
+	MOVE ACC, @BP[OFFS--]
+	MOVE ACC, OFFS
+	MOVE ACC, DPC
+	MOVE ACC, GR
+	MOVE ACC, GRL
+	MOVE ACC, BP
+	MOVE ACC, GRS
+	MOVE ACC, GRH
+	MOVE ACC, GRXL
+	MOVE ACC, FP
+	MOVE ACC, @DP[0]	
+	MOVE ACC, @DP[1]	
+	MOVE ACC, @DP[0]++		
+	MOVE ACC, @DP[1]++
+	MOVE ACC, @DP[0]--
+	MOVE ACC, @DP[1]--
+	MOVE @++SP, #01h
+	MOVE @++SP, AP
+	MOVE @++SP, APC
+	MOVE @++SP, PSF
+	MOVE @++SP, IC
+	MOVE @++SP, IMR
+	MOVE @++SP, SC
+	MOVE @++SP, IIR
+	MOVE @++SP, CKCN
+	MOVE @++SP, WDCN
+	MOVE @++SP, A[0]		;Just Check two boundary conditions
+	MOVE @++SP, A[15]   
+	MOVE @++SP, ACC
+	MOVE @++SP, A[AP]
+	MOVE @++SP, IP
+	MOVE @++SP, SP
+	MOVE @++SP, IV
+	MOVE @++SP, LC[0]
+	MOVE @++SP, LC[1]
+	MOVE @++SP, @BP[OFFS++]
+	MOVE @++SP, @BP[OFFS--]
+	MOVE @++SP, OFFS
+	MOVE @++SP, DPC
+	MOVE @++SP, GR
+	MOVE @++SP, GRL
+	MOVE @++SP, BP
+	MOVE @++SP, GRS
+	MOVE @++SP, GRH
+	MOVE @++SP, GRXL
+	MOVE @++SP, FP
+	MOVE @++SP, @DP[0]	
+	MOVE @++SP, @DP[1]	
+	MOVE @++SP, @DP[0]++		
+	MOVE @++SP, @DP[1]++
+	MOVE @++SP, @DP[0]--
+	MOVE @++SP, @DP[1]--
+	MOVE SP, #01h
+	MOVE SP, AP
+	MOVE SP, APC
+	MOVE SP, PSF
+	MOVE SP, IC
+	MOVE SP, IMR
+	MOVE SP, SC
+	MOVE SP, IIR
+	MOVE SP, CKCN
+	MOVE SP, WDCN
+	MOVE SP, A[0]		;Just Check two boundary conditions
+	MOVE SP, A[15]   
+	MOVE SP, ACC
+	MOVE SP, A[AP]
+	MOVE SP, IP
+	MOVE SP, IV
+	MOVE SP, LC[0]
+	MOVE SP, LC[1]
+	MOVE SP, @BP[OFFS++]
+	MOVE SP, @BP[OFFS--]
+	MOVE SP, OFFS
+	MOVE SP, DPC
+	MOVE SP, GR
+	MOVE SP, GRL
+	MOVE SP, BP
+	MOVE SP, GRS
+	MOVE SP, GRH
+	MOVE SP, GRXL
+	MOVE SP, FP
+	MOVE SP, @DP[0]	
+	MOVE SP, @DP[1]	
+	MOVE SP, @DP[0]++		
+	MOVE SP, @DP[1]++
+	MOVE SP, @DP[0]--
+	MOVE SP, @DP[1]--
+	MOVE IV, #01h
+	MOVE IV, AP
+	MOVE IV, APC
+	MOVE IV, PSF
+	MOVE IV, IC
+	MOVE IV, IMR
+	MOVE IV, SC
+	MOVE IV, IIR
+	MOVE IV, CKCN
+	MOVE IV, WDCN
+	MOVE IV, A[0]		;Just Check two boundary conditions
+	MOVE IV, A[15]   
+	MOVE IV, ACC
+	MOVE IV, A[AP]
+	MOVE IV, IP
+	MOVE IV, @SP--
+	MOVE IV, SP
+	MOVE IV, IV
+	MOVE IV, LC[0]
+	MOVE IV, LC[1]
+	MOVE IV, @BP[OFFS++]
+	MOVE IV, @BP[OFFS--]
+	MOVE IV, OFFS
+	MOVE IV, DPC
+	MOVE IV, GR
+	MOVE IV, GRL
+	MOVE IV, BP
+	MOVE IV, GRS
+	MOVE IV, GRH
+	MOVE IV, GRXL
+	MOVE IV, FP
+	MOVE IV, @DP[0]	
+	MOVE IV, @DP[1]	
+	MOVE IV, @DP[0]++		
+	MOVE IV, @DP[1]++
+	MOVE IV, @DP[0]--
+	MOVE IV, @DP[1]--
+	MOVE LC[0], #01h
+	MOVE LC[0], AP
+	MOVE LC[0], APC
+	MOVE LC[0], PSF
+	MOVE LC[0], IC
+	MOVE LC[0], IMR
+	MOVE LC[0], SC
+	MOVE LC[0], IIR
+	MOVE LC[0], CKCN
+	MOVE LC[0], WDCN
+	MOVE LC[0], A[0]		;Just Check two boundary conditions
+	MOVE LC[0], A[15]   
+	MOVE LC[0], ACC
+	MOVE LC[0], A[AP]
+	MOVE LC[0], IP
+	MOVE LC[0], @SP--
+	MOVE LC[0], SP
+	MOVE LC[0], IV
+	MOVE LC[0], @BP[OFFS++]
+	MOVE LC[0], @BP[OFFS--]
+	MOVE LC[0], OFFS
+	MOVE LC[0], DPC
+	MOVE LC[0], GR
+	MOVE LC[0], GRL
+	MOVE LC[0], BP
+	MOVE LC[0], GRS
+	MOVE LC[0], GRH
+	MOVE LC[0], GRXL
+	MOVE LC[0], FP
+	MOVE LC[0], @DP[0]	
+	MOVE LC[0], @DP[1]	
+	MOVE LC[0], @DP[0]++		
+	MOVE LC[0], @DP[1]++
+	MOVE LC[0], @DP[0]--
+	MOVE LC[0], @DP[1]--
+	MOVE @BP[OFFS], #01h
+	MOVE @BP[OFFS], AP
+	MOVE @BP[OFFS], APC
+	MOVE @BP[OFFS], PSF
+	MOVE @BP[OFFS], IC
+	MOVE @BP[OFFS], IMR
+	MOVE @BP[OFFS], SC
+	MOVE @BP[OFFS], IIR
+	MOVE @BP[OFFS], CKCN
+	MOVE @BP[OFFS], WDCN
+	MOVE @BP[OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[OFFS], A[15]   
+	MOVE @BP[OFFS], ACC
+	MOVE @BP[OFFS], A[AP]
+	MOVE @BP[OFFS], IP
+	MOVE @BP[OFFS], @SP--
+	MOVE @BP[OFFS], SP
+	MOVE @BP[OFFS], IV
+	MOVE @BP[OFFS], LC[0]
+	MOVE @BP[OFFS], LC[1]
+	MOVE @BP[OFFS], OFFS
+	MOVE @BP[OFFS], DPC
+	MOVE @BP[OFFS], GR
+	MOVE @BP[OFFS], GRL
+	MOVE @BP[OFFS], BP
+	MOVE @BP[OFFS], GRS
+	MOVE @BP[OFFS], GRH
+	MOVE @BP[OFFS], GRXL
+	MOVE @BP[OFFS], FP
+	MOVE @BP[OFFS], @DP[0]	
+	MOVE @BP[OFFS], @DP[1]	
+	MOVE @BP[OFFS], @DP[0]++		
+	MOVE @BP[OFFS], @DP[1]++
+	MOVE @BP[OFFS], @DP[0]--
+	MOVE @BP[OFFS], @DP[1]--
+	MOVE @BP[++OFFS], #01h
+	MOVE @BP[++OFFS], AP
+	MOVE @BP[++OFFS], APC
+	MOVE @BP[++OFFS], PSF
+	MOVE @BP[++OFFS], IC
+	MOVE @BP[++OFFS], IMR
+	MOVE @BP[++OFFS], SC
+	MOVE @BP[++OFFS], IIR
+	MOVE @BP[++OFFS], CKCN
+	MOVE @BP[++OFFS], WDCN
+	MOVE @BP[++OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[++OFFS], A[15]   
+	MOVE @BP[++OFFS], ACC
+	MOVE @BP[++OFFS], A[AP]
+	MOVE @BP[++OFFS], IP
+	MOVE @BP[++OFFS], SP
+	MOVE @BP[++OFFS], IV
+	MOVE @BP[++OFFS], LC[0]
+	MOVE @BP[++OFFS], LC[1]
+	MOVE @BP[++OFFS], OFFS
+	MOVE @BP[++OFFS], DPC
+	MOVE @BP[++OFFS], GR
+	MOVE @BP[++OFFS], GRL
+	MOVE @BP[++OFFS], BP
+	MOVE @BP[++OFFS], GRS
+	MOVE @BP[++OFFS], GRH
+	MOVE @BP[++OFFS], GRXL
+	MOVE @BP[++OFFS], FP
+	MOVE @BP[++OFFS], @DP[0]	
+	MOVE @BP[++OFFS], @DP[1]	
+	MOVE @BP[++OFFS], @DP[0]--
+	MOVE @BP[++OFFS], @DP[1]--
+	MOVE @BP[--OFFS], #01h
+	MOVE @BP[--OFFS], AP
+	MOVE @BP[--OFFS], APC
+	MOVE @BP[--OFFS], PSF
+	MOVE @BP[--OFFS], IC
+	MOVE @BP[--OFFS], IMR
+	MOVE @BP[--OFFS], SC
+	MOVE @BP[--OFFS], IIR
+	MOVE @BP[--OFFS], CKCN
+	MOVE @BP[--OFFS], WDCN
+	MOVE @BP[--OFFS], A[0]		;Just Check two boundary conditions
+	MOVE @BP[--OFFS], A[15]   
+	MOVE @BP[--OFFS], ACC
+	MOVE @BP[--OFFS], A[AP]
+	MOVE @BP[--OFFS], IP
+	MOVE @BP[--OFFS], SP
+	MOVE @BP[--OFFS], IV
+	MOVE @BP[--OFFS], LC[0]
+	MOVE @BP[--OFFS], LC[1]
+	MOVE @BP[--OFFS], OFFS
+	MOVE @BP[--OFFS], DPC
+	MOVE @BP[--OFFS], GR
+	MOVE @BP[--OFFS], GRL
+	MOVE @BP[--OFFS], BP
+	MOVE @BP[--OFFS], GRS
+	MOVE @BP[--OFFS], GRH
+	MOVE @BP[--OFFS], GRXL
+	MOVE @BP[--OFFS], FP
+	MOVE @BP[--OFFS], @DP[0]	
+	MOVE @BP[--OFFS], @DP[1]	
+	MOVE OFFS, #01h
+	MOVE OFFS, AP
+	MOVE OFFS, APC
+	MOVE OFFS, PSF
+	MOVE OFFS, IC
+	MOVE OFFS, IMR
+	MOVE OFFS, SC
+	MOVE OFFS, IIR
+	MOVE OFFS, CKCN
+	MOVE OFFS, WDCN
+	MOVE OFFS, A[0]		;Just Check two boundary conditions
+	MOVE OFFS, A[15]   
+	MOVE OFFS, ACC
+	MOVE OFFS, A[AP]
+	MOVE OFFS, IP
+	MOVE OFFS, @SP--
+	MOVE OFFS, SP
+	MOVE OFFS, IV
+	MOVE OFFS, LC[0]
+	MOVE OFFS, LC[1]
+	MOVE OFFS, DPC
+	MOVE OFFS, GR
+	MOVE OFFS, GRL
+	MOVE OFFS, BP
+	MOVE OFFS, GRS
+	MOVE OFFS, GRH
+	MOVE OFFS, GRXL
+	MOVE OFFS, FP
+	MOVE OFFS, @DP[0]	
+	MOVE OFFS, @DP[1]	
+	MOVE OFFS, @DP[0]++		
+	MOVE OFFS, @DP[1]++
+	MOVE OFFS, @DP[0]--
+	MOVE OFFS, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/data3.d b/gas/testsuite/gas/maxq20/data3.d
new file mode 100644
index 000000000000..517abb66bc36
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data3.d
@@ -0,0 +1,491 @@
+#objdump: -dw
+#name: 3rd Move operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4e [ 	]*MOVE  DPC, #01h
+   2:	08 ce [ 	]*MOVE  DPC, AP
+   4:	18 ce [ 	]*MOVE  DPC, APC
+   6:	48 ce [ 	]*MOVE  DPC, PSF
+   8:	58 ce [ 	]*MOVE  DPC, IC
+   a:	68 ce [ 	]*MOVE  DPC, IMR
+   c:	88 ce [ 	]*MOVE  DPC, SC
+   e:	b8 ce [ 	]*MOVE  DPC, IIR
+  10:	e8 ce [ 	]*MOVE  DPC, CKCN
+  12:	f8 ce [ 	]*MOVE  DPC, WDCN
+  14:	09 ce [ 	]*MOVE  DPC, A\[0\]
+  16:	f9 ce [ 	]*MOVE  DPC, A\[15\]
+  18:	0a ce [ 	]*MOVE  DPC, ACC
+  1a:	1a ce [ 	]*MOVE  DPC, A\[AP\]
+  1c:	0c ce [ 	]*MOVE  DPC, IP
+  1e:	0d ce [ 	]*MOVE  DPC, @SP\-\-
+  20:	1d ce [ 	]*MOVE  DPC, SP
+  22:	2d ce [ 	]*MOVE  DPC, IV
+  24:	6d ce [ 	]*MOVE  DPC, LC\[0\]
+  26:	7d ce [ 	]*MOVE  DPC, LC\[1\]
+  28:	1e ce [ 	]*MOVE  DPC, @BP\[OFFS\+\+\]
+  2a:	2e ce [ 	]*MOVE  DPC, @BP\[OFFS\-\-\]
+  2c:	3e ce [ 	]*MOVE  DPC, OFFS
+  2e:	5e ce [ 	]*MOVE  DPC, GR
+  30:	6e ce [ 	]*MOVE  DPC, GRL
+  32:	7e ce [ 	]*MOVE  DPC, BP
+  34:	8e ce [ 	]*MOVE  DPC, GRS
+  36:	9e ce [ 	]*MOVE  DPC, GRH
+  38:	ae ce [ 	]*MOVE  DPC, GRXL
+  3a:	be ce [ 	]*MOVE  DPC, FP
+  3c:	0f ce [ 	]*MOVE  DPC, @DP\[0\]
+  3e:	4f ce [ 	]*MOVE  DPC, @DP\[1\]
+  40:	1f ce [ 	]*MOVE  DPC, @DP\[0\]\+\+
+  42:	5f ce [ 	]*MOVE  DPC, @DP\[1\]\+\+
+  44:	2f ce [ 	]*MOVE  DPC, @DP\[0\]\-\-
+  46:	6f ce [ 	]*MOVE  DPC, @DP\[1\]\-\-
+  48:	01 5e [ 	]*MOVE  GR, #01h
+  4a:	08 de [ 	]*MOVE  GR, AP
+  4c:	18 de [ 	]*MOVE  GR, APC
+  4e:	48 de [ 	]*MOVE  GR, PSF
+  50:	58 de [ 	]*MOVE  GR, IC
+  52:	68 de [ 	]*MOVE  GR, IMR
+  54:	88 de [ 	]*MOVE  GR, SC
+  56:	b8 de [ 	]*MOVE  GR, IIR
+  58:	e8 de [ 	]*MOVE  GR, CKCN
+  5a:	f8 de [ 	]*MOVE  GR, WDCN
+  5c:	09 de [ 	]*MOVE  GR, A\[0\]
+  5e:	f9 de [ 	]*MOVE  GR, A\[15\]
+  60:	0a de [ 	]*MOVE  GR, ACC
+  62:	1a de [ 	]*MOVE  GR, A\[AP\]
+  64:	0c de [ 	]*MOVE  GR, IP
+  66:	0d de [ 	]*MOVE  GR, @SP\-\-
+  68:	1d de [ 	]*MOVE  GR, SP
+  6a:	2d de [ 	]*MOVE  GR, IV
+  6c:	6d de [ 	]*MOVE  GR, LC\[0\]
+  6e:	7d de [ 	]*MOVE  GR, LC\[1\]
+  70:	1e de [ 	]*MOVE  GR, @BP\[OFFS\+\+\]
+  72:	2e de [ 	]*MOVE  GR, @BP\[OFFS\-\-\]
+  74:	3e de [ 	]*MOVE  GR, OFFS
+  76:	4e de [ 	]*MOVE  GR, DPC
+  78:	6e de [ 	]*MOVE  GR, GRL
+  7a:	7e de [ 	]*MOVE  GR, BP
+  7c:	8e de [ 	]*MOVE  GR, GRS
+  7e:	9e de [ 	]*MOVE  GR, GRH
+  80:	ae de [ 	]*MOVE  GR, GRXL
+  82:	be de [ 	]*MOVE  GR, FP
+  84:	0f de [ 	]*MOVE  GR, @DP\[0\]
+  86:	4f de [ 	]*MOVE  GR, @DP\[1\]
+  88:	1f de [ 	]*MOVE  GR, @DP\[0\]\+\+
+  8a:	5f de [ 	]*MOVE  GR, @DP\[1\]\+\+
+  8c:	2f de [ 	]*MOVE  GR, @DP\[0\]\-\-
+  8e:	6f de [ 	]*MOVE  GR, @DP\[1\]\-\-
+  90:	01 6e [ 	]*MOVE  GRL, #01h
+  92:	08 ee [ 	]*MOVE  GRL, AP
+  94:	18 ee [ 	]*MOVE  GRL, APC
+  96:	48 ee [ 	]*MOVE  GRL, PSF
+  98:	58 ee [ 	]*MOVE  GRL, IC
+  9a:	68 ee [ 	]*MOVE  GRL, IMR
+  9c:	88 ee [ 	]*MOVE  GRL, SC
+  9e:	b8 ee [ 	]*MOVE  GRL, IIR
+  a0:	e8 ee [ 	]*MOVE  GRL, CKCN
+  a2:	f8 ee [ 	]*MOVE  GRL, WDCN
+  a4:	09 ee [ 	]*MOVE  GRL, A\[0\]
+  a6:	f9 ee [ 	]*MOVE  GRL, A\[15\]
+  a8:	0a ee [ 	]*MOVE  GRL, ACC
+  aa:	1a ee [ 	]*MOVE  GRL, A\[AP\]
+  ac:	0c ee [ 	]*MOVE  GRL, IP
+  ae:	0d ee [ 	]*MOVE  GRL, @SP\-\-
+  b0:	1d ee [ 	]*MOVE  GRL, SP
+  b2:	2d ee [ 	]*MOVE  GRL, IV
+  b4:	6d ee [ 	]*MOVE  GRL, LC\[0\]
+  b6:	7d ee [ 	]*MOVE  GRL, LC\[1\]
+  b8:	1e ee [ 	]*MOVE  GRL, @BP\[OFFS\+\+\]
+  ba:	2e ee [ 	]*MOVE  GRL, @BP\[OFFS\-\-\]
+  bc:	3e ee [ 	]*MOVE  GRL, OFFS
+  be:	4e ee [ 	]*MOVE  GRL, DPC
+  c0:	5e ee [ 	]*MOVE  GRL, GR
+  c2:	7e ee [ 	]*MOVE  GRL, BP
+  c4:	8e ee [ 	]*MOVE  GRL, GRS
+  c6:	9e ee [ 	]*MOVE  GRL, GRH
+  c8:	ae ee [ 	]*MOVE  GRL, GRXL
+  ca:	be ee [ 	]*MOVE  GRL, FP
+  cc:	0f ee [ 	]*MOVE  GRL, @DP\[0\]
+  ce:	4f ee [ 	]*MOVE  GRL, @DP\[1\]
+  d0:	1f ee [ 	]*MOVE  GRL, @DP\[0\]\+\+
+  d2:	5f ee [ 	]*MOVE  GRL, @DP\[1\]\+\+
+  d4:	2f ee [ 	]*MOVE  GRL, @DP\[0\]\-\-
+  d6:	6f ee [ 	]*MOVE  GRL, @DP\[1\]\-\-
+  d8:	01 7e [ 	]*MOVE  BP, #01h
+  da:	08 fe [ 	]*MOVE  BP, AP
+  dc:	18 fe [ 	]*MOVE  BP, APC
+  de:	48 fe [ 	]*MOVE  BP, PSF
+  e0:	58 fe [ 	]*MOVE  BP, IC
+  e2:	68 fe [ 	]*MOVE  BP, IMR
+  e4:	88 fe [ 	]*MOVE  BP, SC
+  e6:	b8 fe [ 	]*MOVE  BP, IIR
+  e8:	e8 fe [ 	]*MOVE  BP, CKCN
+  ea:	f8 fe [ 	]*MOVE  BP, WDCN
+  ec:	09 fe [ 	]*MOVE  BP, A\[0\]
+  ee:	f9 fe [ 	]*MOVE  BP, A\[15\]
+  f0:	0a fe [ 	]*MOVE  BP, ACC
+  f2:	1a fe [ 	]*MOVE  BP, A\[AP\]
+  f4:	0c fe [ 	]*MOVE  BP, IP
+  f6:	0d fe [ 	]*MOVE  BP, @SP\-\-
+  f8:	1d fe [ 	]*MOVE  BP, SP
+  fa:	2d fe [ 	]*MOVE  BP, IV
+  fc:	6d fe [ 	]*MOVE  BP, LC\[0\]
+  fe:	7d fe [ 	]*MOVE  BP, LC\[1\]
+ 100:	1e fe [ 	]*MOVE  BP, @BP\[OFFS\+\+\]
+ 102:	2e fe [ 	]*MOVE  BP, @BP\[OFFS\-\-\]
+ 104:	3e fe [ 	]*MOVE  BP, OFFS
+ 106:	4e fe [ 	]*MOVE  BP, DPC
+ 108:	5e fe [ 	]*MOVE  BP, GR
+ 10a:	6e fe [ 	]*MOVE  BP, GRL
+ 10c:	8e fe [ 	]*MOVE  BP, GRS
+ 10e:	9e fe [ 	]*MOVE  BP, GRH
+ 110:	ae fe [ 	]*MOVE  BP, GRXL
+ 112:	be fe [ 	]*MOVE  BP, FP
+ 114:	0f fe [ 	]*MOVE  BP, @DP\[0\]
+ 116:	4f fe [ 	]*MOVE  BP, @DP\[1\]
+ 118:	1f fe [ 	]*MOVE  BP, @DP\[0\]\+\+
+ 11a:	5f fe [ 	]*MOVE  BP, @DP\[1\]\+\+
+ 11c:	2f fe [ 	]*MOVE  BP, @DP\[0\]\-\-
+ 11e:	6f fe [ 	]*MOVE  BP, @DP\[1\]\-\-
+ 120:	01 0f [ 	]*MOVE  @DP\[0\], #01h
+ 122:	08 8f [ 	]*MOVE  @DP\[0\], AP
+ 124:	18 8f [ 	]*MOVE  @DP\[0\], APC
+ 126:	48 8f [ 	]*MOVE  @DP\[0\], PSF
+ 128:	58 8f [ 	]*MOVE  @DP\[0\], IC
+ 12a:	68 8f [ 	]*MOVE  @DP\[0\], IMR
+ 12c:	88 8f [ 	]*MOVE  @DP\[0\], SC
+ 12e:	b8 8f [ 	]*MOVE  @DP\[0\], IIR
+ 130:	e8 8f [ 	]*MOVE  @DP\[0\], CKCN
+ 132:	f8 8f [ 	]*MOVE  @DP\[0\], WDCN
+ 134:	09 8f [ 	]*MOVE  @DP\[0\], A\[0\]
+ 136:	f9 8f [ 	]*MOVE  @DP\[0\], A\[15\]
+ 138:	0a 8f [ 	]*MOVE  @DP\[0\], ACC
+ 13a:	1a 8f [ 	]*MOVE  @DP\[0\], A\[AP\]
+ 13c:	0c 8f [ 	]*MOVE  @DP\[0\], IP
+ 13e:	0d 8f [ 	]*MOVE  @DP\[0\], @SP\-\-
+ 140:	1d 8f [ 	]*MOVE  @DP\[0\], SP
+ 142:	2d 8f [ 	]*MOVE  @DP\[0\], IV
+ 144:	6d 8f [ 	]*MOVE  @DP\[0\], LC\[0\]
+ 146:	7d 8f [ 	]*MOVE  @DP\[0\], LC\[1\]
+ 148:	1e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\+\+\]
+ 14a:	2e 8f [ 	]*MOVE  @DP\[0\], @BP\[OFFS\-\-\]
+ 14c:	3e 8f [ 	]*MOVE  @DP\[0\], OFFS
+ 14e:	4e 8f [ 	]*MOVE  @DP\[0\], DPC
+ 150:	5e 8f [ 	]*MOVE  @DP\[0\], GR
+ 152:	6e 8f [ 	]*MOVE  @DP\[0\], GRL
+ 154:	7e 8f [ 	]*MOVE  @DP\[0\], BP
+ 156:	8e 8f [ 	]*MOVE  @DP\[0\], GRS
+ 158:	9e 8f [ 	]*MOVE  @DP\[0\], GRH
+ 15a:	ae 8f [ 	]*MOVE  @DP\[0\], GRXL
+ 15c:	be 8f [ 	]*MOVE  @DP\[0\], FP
+ 15e:	01 1f [ 	]*MOVE  @\+\+DP\[0\], #01h
+ 160:	08 9f [ 	]*MOVE  @\+\+DP\[0\], AP
+ 162:	18 9f [ 	]*MOVE  @\+\+DP\[0\], APC
+ 164:	48 9f [ 	]*MOVE  @\+\+DP\[0\], PSF
+ 166:	58 9f [ 	]*MOVE  @\+\+DP\[0\], IC
+ 168:	68 9f [ 	]*MOVE  @\+\+DP\[0\], IMR
+ 16a:	88 9f [ 	]*MOVE  @\+\+DP\[0\], SC
+ 16c:	b8 9f [ 	]*MOVE  @\+\+DP\[0\], IIR
+ 16e:	e8 9f [ 	]*MOVE  @\+\+DP\[0\], CKCN
+ 170:	f8 9f [ 	]*MOVE  @\+\+DP\[0\], WDCN
+ 172:	09 9f [ 	]*MOVE  @\+\+DP\[0\], A\[0\]
+ 174:	f9 9f [ 	]*MOVE  @\+\+DP\[0\], A\[15\]
+ 176:	0a 9f [ 	]*MOVE  @\+\+DP\[0\], ACC
+ 178:	1a 9f [ 	]*MOVE  @\+\+DP\[0\], A\[AP\]
+ 17a:	0c 9f [ 	]*MOVE  @\+\+DP\[0\], IP
+ 17c:	0d 9f [ 	]*MOVE  @\+\+DP\[0\], @SP\-\-
+ 17e:	1d 9f [ 	]*MOVE  @\+\+DP\[0\], SP
+ 180:	2d 9f [ 	]*MOVE  @\+\+DP\[0\], IV
+ 182:	6d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[0\]
+ 184:	7d 9f [ 	]*MOVE  @\+\+DP\[0\], LC\[1\]
+ 186:	1e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\+\+\]
+ 188:	2e 9f [ 	]*MOVE  @\+\+DP\[0\], @BP\[OFFS\-\-\]
+ 18a:	3e 9f [ 	]*MOVE  @\+\+DP\[0\], OFFS
+ 18c:	4e 9f [ 	]*MOVE  @\+\+DP\[0\], DPC
+ 18e:	5e 9f [ 	]*MOVE  @\+\+DP\[0\], GR
+ 190:	6e 9f [ 	]*MOVE  @\+\+DP\[0\], GRL
+ 192:	7e 9f [ 	]*MOVE  @\+\+DP\[0\], BP
+ 194:	8e 9f [ 	]*MOVE  @\+\+DP\[0\], GRS
+ 196:	9e 9f [ 	]*MOVE  @\+\+DP\[0\], GRH
+ 198:	ae 9f [ 	]*MOVE  @\+\+DP\[0\], GRXL
+ 19a:	be 9f [ 	]*MOVE  @\+\+DP\[0\], FP
+ 19c:	01 2f [ 	]*MOVE  @\-\-DP\[0\], #01h
+ 19e:	08 af [ 	]*MOVE  @\-\-DP\[0\], AP
+ 1a0:	18 af [ 	]*MOVE  @\-\-DP\[0\], APC
+ 1a2:	48 af [ 	]*MOVE  @\-\-DP\[0\], PSF
+ 1a4:	58 af [ 	]*MOVE  @\-\-DP\[0\], IC
+ 1a6:	68 af [ 	]*MOVE  @\-\-DP\[0\], IMR
+ 1a8:	88 af [ 	]*MOVE  @\-\-DP\[0\], SC
+ 1aa:	b8 af [ 	]*MOVE  @\-\-DP\[0\], IIR
+ 1ac:	e8 af [ 	]*MOVE  @\-\-DP\[0\], CKCN
+ 1ae:	f8 af [ 	]*MOVE  @\-\-DP\[0\], WDCN
+ 1b0:	09 af [ 	]*MOVE  @\-\-DP\[0\], A\[0\]
+ 1b2:	f9 af [ 	]*MOVE  @\-\-DP\[0\], A\[15\]
+ 1b4:	0a af [ 	]*MOVE  @\-\-DP\[0\], ACC
+ 1b6:	1a af [ 	]*MOVE  @\-\-DP\[0\], A\[AP\]
+ 1b8:	0c af [ 	]*MOVE  @\-\-DP\[0\], IP
+ 1ba:	0d af [ 	]*MOVE  @\-\-DP\[0\], @SP\-\-
+ 1bc:	1d af [ 	]*MOVE  @\-\-DP\[0\], SP
+ 1be:	2d af [ 	]*MOVE  @\-\-DP\[0\], IV
+ 1c0:	6d af [ 	]*MOVE  @\-\-DP\[0\], LC\[0\]
+ 1c2:	7d af [ 	]*MOVE  @\-\-DP\[0\], LC\[1\]
+ 1c4:	1e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\+\+\]
+ 1c6:	2e af [ 	]*MOVE  @\-\-DP\[0\], @BP\[OFFS\-\-\]
+ 1c8:	3e af [ 	]*MOVE  @\-\-DP\[0\], OFFS
+ 1ca:	4e af [ 	]*MOVE  @\-\-DP\[0\], DPC
+ 1cc:	5e af [ 	]*MOVE  @\-\-DP\[0\], GR
+ 1ce:	6e af [ 	]*MOVE  @\-\-DP\[0\], GRL
+ 1d0:	7e af [ 	]*MOVE  @\-\-DP\[0\], BP
+ 1d2:	8e af [ 	]*MOVE  @\-\-DP\[0\], GRS
+ 1d4:	9e af [ 	]*MOVE  @\-\-DP\[0\], GRH
+ 1d6:	ae af [ 	]*MOVE  @\-\-DP\[0\], GRXL
+ 1d8:	be af [ 	]*MOVE  @\-\-DP\[0\], FP
+ 1da:	01 3f [ 	]*MOVE  DP\[0\], #01h
+ 1dc:	08 bf [ 	]*MOVE  DP\[0\], AP
+ 1de:	18 bf [ 	]*MOVE  DP\[0\], APC
+ 1e0:	48 bf [ 	]*MOVE  DP\[0\], PSF
+ 1e2:	58 bf [ 	]*MOVE  DP\[0\], IC
+ 1e4:	68 bf [ 	]*MOVE  DP\[0\], IMR
+ 1e6:	88 bf [ 	]*MOVE  DP\[0\], SC
+ 1e8:	b8 bf [ 	]*MOVE  DP\[0\], IIR
+ 1ea:	e8 bf [ 	]*MOVE  DP\[0\], CKCN
+ 1ec:	f8 bf [ 	]*MOVE  DP\[0\], WDCN
+ 1ee:	09 bf [ 	]*MOVE  DP\[0\], A\[0\]
+ 1f0:	f9 bf [ 	]*MOVE  DP\[0\], A\[15\]
+ 1f2:	0a bf [ 	]*MOVE  DP\[0\], ACC
+ 1f4:	1a bf [ 	]*MOVE  DP\[0\], A\[AP\]
+ 1f6:	0c bf [ 	]*MOVE  DP\[0\], IP
+ 1f8:	0d bf [ 	]*MOVE  DP\[0\], @SP\-\-
+ 1fa:	1d bf [ 	]*MOVE  DP\[0\], SP
+ 1fc:	2d bf [ 	]*MOVE  DP\[0\], IV
+ 1fe:	6d bf [ 	]*MOVE  DP\[0\], LC\[0\]
+ 200:	7d bf [ 	]*MOVE  DP\[0\], LC\[1\]
+ 202:	1e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\+\+\]
+ 204:	2e bf [ 	]*MOVE  DP\[0\], @BP\[OFFS\-\-\]
+ 206:	3e bf [ 	]*MOVE  DP\[0\], OFFS
+ 208:	4e bf [ 	]*MOVE  DP\[0\], DPC
+ 20a:	5e bf [ 	]*MOVE  DP\[0\], GR
+ 20c:	6e bf [ 	]*MOVE  DP\[0\], GRL
+ 20e:	7e bf [ 	]*MOVE  DP\[0\], BP
+ 210:	8e bf [ 	]*MOVE  DP\[0\], GRS
+ 212:	9e bf [ 	]*MOVE  DP\[0\], GRH
+ 214:	ae bf [ 	]*MOVE  DP\[0\], GRXL
+ 216:	be bf [ 	]*MOVE  DP\[0\], FP
+ 218:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21a:	01 08 [ 	]*MOVE  AP, #01h
+ 21c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 21e:	08 88 [ 	]*MOVE  AP, AP
+ 220:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 222:	18 88 [ 	]*MOVE  AP, APC
+ 224:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 226:	48 88 [ 	]*MOVE  AP, PSF
+ 228:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22a:	58 88 [ 	]*MOVE  AP, IC
+ 22c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 22e:	68 88 [ 	]*MOVE  AP, IMR
+ 230:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 232:	b8 88 [ 	]*MOVE  AP, IIR
+ 234:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 236:	e8 88 [ 	]*MOVE  AP, CKCN
+ 238:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23a:	f8 88 [ 	]*MOVE  AP, WDCN
+ 23c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 23e:	09 88 [ 	]*MOVE  AP, A\[0\]
+ 240:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 242:	f9 88 [ 	]*MOVE  AP, A\[15\]
+ 244:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 246:	0a 88 [ 	]*MOVE  AP, ACC
+ 248:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24a:	1a 88 [ 	]*MOVE  AP, A\[AP\]
+ 24c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 24e:	0c 88 [ 	]*MOVE  AP, IP
+ 250:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 252:	0d 88 [ 	]*MOVE  AP, @SP\-\-
+ 254:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 256:	1d 88 [ 	]*MOVE  AP, SP
+ 258:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25a:	2d 88 [ 	]*MOVE  AP, IV
+ 25c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 25e:	6d 88 [ 	]*MOVE  AP, LC\[0\]
+ 260:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 262:	7d 88 [ 	]*MOVE  AP, LC\[1\]
+ 264:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 266:	1e 88 [ 	]*MOVE  AP, @BP\[OFFS\+\+\]
+ 268:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26a:	2e 88 [ 	]*MOVE  AP, @BP\[OFFS\-\-\]
+ 26c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 26e:	3e 88 [ 	]*MOVE  AP, OFFS
+ 270:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 272:	4e 88 [ 	]*MOVE  AP, DPC
+ 274:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 276:	5e 88 [ 	]*MOVE  AP, GR
+ 278:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27a:	6e 88 [ 	]*MOVE  AP, GRL
+ 27c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 27e:	7e 88 [ 	]*MOVE  AP, BP
+ 280:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 282:	8e 88 [ 	]*MOVE  AP, GRS
+ 284:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 286:	9e 88 [ 	]*MOVE  AP, GRH
+ 288:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28a:	ae 88 [ 	]*MOVE  AP, GRXL
+ 28c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 28e:	be 88 [ 	]*MOVE  AP, FP
+ 290:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 292:	0f 88 [ 	]*MOVE  AP, @DP\[0\]
+ 294:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 296:	4f 88 [ 	]*MOVE  AP, @DP\[1\]
+ 298:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29a:	1f 88 [ 	]*MOVE  AP, @DP\[0\]\+\+
+ 29c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 29e:	5f 88 [ 	]*MOVE  AP, @DP\[1\]\+\+
+ 2a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a2:	2f 88 [ 	]*MOVE  AP, @DP\[0\]\-\-
+ 2a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2a6:	6f 88 [ 	]*MOVE  AP, @DP\[1\]\-\-
+ 2a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2aa:	01 68 [ 	]*MOVE  IMR, #01h
+ 2ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ae:	08 e8 [ 	]*MOVE  IMR, AP
+ 2b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b2:	18 e8 [ 	]*MOVE  IMR, APC
+ 2b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2b6:	48 e8 [ 	]*MOVE  IMR, PSF
+ 2b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ba:	58 e8 [ 	]*MOVE  IMR, IC
+ 2bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2be:	68 e8 [ 	]*MOVE  IMR, IMR
+ 2c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c2:	88 e8 [ 	]*MOVE  IMR, SC
+ 2c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2c6:	b8 e8 [ 	]*MOVE  IMR, IIR
+ 2c8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ca:	f8 e8 [ 	]*MOVE  IMR, WDCN
+ 2cc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ce:	09 e8 [ 	]*MOVE  IMR, A\[0\]
+ 2d0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d2:	f9 e8 [ 	]*MOVE  IMR, A\[15\]
+ 2d4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2d6:	0a e8 [ 	]*MOVE  IMR, ACC
+ 2d8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2da:	1a e8 [ 	]*MOVE  IMR, A\[AP\]
+ 2dc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2de:	0c e8 [ 	]*MOVE  IMR, IP
+ 2e0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e2:	0d e8 [ 	]*MOVE  IMR, @SP\-\-
+ 2e4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2e6:	1d e8 [ 	]*MOVE  IMR, SP
+ 2e8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ea:	2d e8 [ 	]*MOVE  IMR, IV
+ 2ec:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2ee:	6d e8 [ 	]*MOVE  IMR, LC\[0\]
+ 2f0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f2:	7d e8 [ 	]*MOVE  IMR, LC\[1\]
+ 2f4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2f6:	1e e8 [ 	]*MOVE  IMR, @BP\[OFFS\+\+\]
+ 2f8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fa:	2e e8 [ 	]*MOVE  IMR, @BP\[OFFS\-\-\]
+ 2fc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 2fe:	3e e8 [ 	]*MOVE  IMR, OFFS
+ 300:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 302:	4e e8 [ 	]*MOVE  IMR, DPC
+ 304:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 306:	5e e8 [ 	]*MOVE  IMR, GR
+ 308:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30a:	6e e8 [ 	]*MOVE  IMR, GRL
+ 30c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 30e:	7e e8 [ 	]*MOVE  IMR, BP
+ 310:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 312:	8e e8 [ 	]*MOVE  IMR, GRS
+ 314:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 316:	9e e8 [ 	]*MOVE  IMR, GRH
+ 318:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31a:	ae e8 [ 	]*MOVE  IMR, GRXL
+ 31c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 31e:	be e8 [ 	]*MOVE  IMR, FP
+ 320:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 322:	0f e8 [ 	]*MOVE  IMR, @DP\[0\]
+ 324:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 326:	4f e8 [ 	]*MOVE  IMR, @DP\[1\]
+ 328:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32a:	1f e8 [ 	]*MOVE  IMR, @DP\[0\]\+\+
+ 32c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 32e:	5f e8 [ 	]*MOVE  IMR, @DP\[1\]\+\+
+ 330:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 332:	2f e8 [ 	]*MOVE  IMR, @DP\[0\]\-\-
+ 334:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 336:	6f e8 [ 	]*MOVE  IMR, @DP\[1\]\-\-
+ 338:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33a:	01 1e [ 	]*MOVE  @BP\[\+\+OFFS\], #01h
+ 33c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 33e:	08 9e [ 	]*MOVE  @BP\[\+\+OFFS\], AP
+ 340:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 342:	18 9e [ 	]*MOVE  @BP\[\+\+OFFS\], APC
+ 344:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 346:	48 9e [ 	]*MOVE  @BP\[\+\+OFFS\], PSF
+ 348:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34a:	58 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IC
+ 34c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 34e:	68 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IMR
+ 350:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 352:	88 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SC
+ 354:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 356:	b8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IIR
+ 358:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35a:	e8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], CKCN
+ 35c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 35e:	f8 9e [ 	]*MOVE  @BP\[\+\+OFFS\], WDCN
+ 360:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 362:	09 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[0\]
+ 364:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 366:	f9 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[15\]
+ 368:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36a:	0a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], ACC
+ 36c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 36e:	1a 9e [ 	]*MOVE  @BP\[\+\+OFFS\], A\[AP\]
+ 370:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 372:	0c 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IP
+ 374:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 376:	0d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @SP\-\-
+ 378:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37a:	1d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], SP
+ 37c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 37e:	2d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], IV
+ 380:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 382:	6d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[0\]
+ 384:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 386:	7d 9e [ 	]*MOVE  @BP\[\+\+OFFS\], LC\[1\]
+ 388:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38a:	1e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\+\+\]
+ 38c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 38e:	2e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @BP\[OFFS\-\-\]
+ 390:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 392:	3e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], OFFS
+ 394:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 396:	4e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], DPC
+ 398:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39a:	5e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GR
+ 39c:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 39e:	6e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRL
+ 3a0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a2:	7e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], BP
+ 3a4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3a6:	8e 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRS
+ 3a8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3aa:	ae 9e [ 	]*MOVE  @BP\[\+\+OFFS\], GRXL
+ 3ac:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ae:	be 9e [ 	]*MOVE  @BP\[\+\+OFFS\], FP
+ 3b0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b2:	0f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]
+ 3b4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3b6:	4f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]
+ 3b8:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3ba:	1f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\+\+
+ 3bc:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3be:	5f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\+\+
+ 3c0:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c2:	2f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[0\]\-\-
+ 3c4:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+ 3c6:	6f 9e [ 	]*MOVE  @BP\[\+\+OFFS\], @DP\[1\]\-\-
diff --git a/gas/testsuite/gas/maxq20/data3.s b/gas/testsuite/gas/maxq20/data3.s
new file mode 100644
index 000000000000..c3cdbbb43eba
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/data3.s
@@ -0,0 +1,379 @@
+;# data.s	
+;# checks all the data transfer instructions
+foo:
+	MOVE DPC, #01h
+	MOVE DPC, AP
+	MOVE DPC, APC
+	MOVE DPC, PSF
+	MOVE DPC, IC
+	MOVE DPC, IMR
+	MOVE DPC, SC
+	MOVE DPC, IIR
+	MOVE DPC, CKCN
+	MOVE DPC, WDCN
+	MOVE DPC, A[0]		;Just Check two boundary conditions
+	MOVE DPC, A[15]   
+	MOVE DPC, ACC
+	MOVE DPC, A[AP]
+	MOVE DPC, IP
+	MOVE DPC, @SP--
+	MOVE DPC, SP
+	MOVE DPC, IV
+	MOVE DPC, LC[0]
+	MOVE DPC, LC[1]
+	MOVE DPC, @BP[OFFS++]
+	MOVE DPC, @BP[OFFS--]
+	MOVE DPC, OFFS
+	MOVE DPC, GR
+	MOVE DPC, GRL
+	MOVE DPC, BP
+	MOVE DPC, GRS
+	MOVE DPC, GRH
+	MOVE DPC, GRXL
+	MOVE DPC, FP
+	MOVE DPC, @DP[0]	
+	MOVE DPC, @DP[1]	
+	MOVE DPC, @DP[0]++		
+	MOVE DPC, @DP[1]++
+	MOVE DPC, @DP[0]--
+	MOVE DPC, @DP[1]--
+	MOVE GR, #01h
+	MOVE GR, AP
+	MOVE GR, APC
+	MOVE GR, PSF
+	MOVE GR, IC
+	MOVE GR, IMR
+	MOVE GR, SC
+	MOVE GR, IIR
+	MOVE GR, CKCN
+	MOVE GR, WDCN
+	MOVE GR, A[0]		;Just Check two boundary conditions
+	MOVE GR, A[15]   
+	MOVE GR, ACC
+	MOVE GR, A[AP]
+	MOVE GR, IP
+	MOVE GR, @SP--
+	MOVE GR, SP
+	MOVE GR, IV
+	MOVE GR, LC[0]
+	MOVE GR, LC[1]
+	MOVE GR, @BP[OFFS++]
+	MOVE GR, @BP[OFFS--]
+	MOVE GR, OFFS
+	MOVE GR, DPC
+	MOVE GR, GRL
+	MOVE GR, BP
+	MOVE GR, GRS
+	MOVE GR, GRH
+	MOVE GR, GRXL
+	MOVE GR, FP
+	MOVE GR, @DP[0]	
+	MOVE GR, @DP[1]	
+	MOVE GR, @DP[0]++		
+	MOVE GR, @DP[1]++
+	MOVE GR, @DP[0]--
+	MOVE GR, @DP[1]--
+	MOVE GRL, #01h
+	MOVE GRL, AP
+	MOVE GRL, APC
+	MOVE GRL, PSF
+	MOVE GRL, IC
+	MOVE GRL, IMR
+	MOVE GRL, SC
+	MOVE GRL, IIR
+	MOVE GRL, CKCN
+	MOVE GRL, WDCN
+	MOVE GRL, A[0]		;Just Check two boundary conditions
+	MOVE GRL, A[15]   
+	MOVE GRL, ACC
+	MOVE GRL, A[AP]
+	MOVE GRL, IP
+	MOVE GRL, @SP--
+	MOVE GRL, SP
+	MOVE GRL, IV
+	MOVE GRL, LC[0]
+	MOVE GRL, LC[1]
+	MOVE GRL, @BP[OFFS++]
+	MOVE GRL, @BP[OFFS--]
+	MOVE GRL, OFFS
+	MOVE GRL, DPC
+	MOVE GRL, GR
+	MOVE GRL, BP
+	MOVE GRL, GRS
+	MOVE GRL, GRH
+	MOVE GRL, GRXL
+	MOVE GRL, FP
+	MOVE GRL, @DP[0]	
+	MOVE GRL, @DP[1]	
+	MOVE GRL, @DP[0]++		
+	MOVE GRL, @DP[1]++
+	MOVE GRL, @DP[0]--
+	MOVE GRL, @DP[1]--
+	MOVE BP, #01h
+	MOVE BP, AP
+	MOVE BP, APC
+	MOVE BP, PSF
+	MOVE BP, IC
+	MOVE BP, IMR
+	MOVE BP, SC
+	MOVE BP, IIR
+	MOVE BP, CKCN
+	MOVE BP, WDCN
+	MOVE BP, A[0]		;Just Check two boundary conditions
+	MOVE BP, A[15]   
+	MOVE BP, ACC
+	MOVE BP, A[AP]
+	MOVE BP, IP
+	MOVE BP, @SP--
+	MOVE BP, SP
+	MOVE BP, IV
+	MOVE BP, LC[0]
+	MOVE BP, LC[1]
+	MOVE BP, @BP[OFFS++]
+	MOVE BP, @BP[OFFS--]
+	MOVE BP, OFFS
+	MOVE BP, DPC
+	MOVE BP, GR
+	MOVE BP, GRL
+	MOVE BP, GRS
+	MOVE BP, GRH
+	MOVE BP, GRXL
+	MOVE BP, FP
+	MOVE BP, @DP[0]	
+	MOVE BP, @DP[1]	
+	MOVE BP, @DP[0]++		
+	MOVE BP, @DP[1]++
+	MOVE BP, @DP[0]--
+	MOVE BP, @DP[1]--
+	MOVE @DP[0], #01h
+	MOVE @DP[0], AP
+	MOVE @DP[0], APC
+	MOVE @DP[0], PSF
+	MOVE @DP[0], IC
+	MOVE @DP[0], IMR
+	MOVE @DP[0], SC
+	MOVE @DP[0], IIR
+	MOVE @DP[0], CKCN
+	MOVE @DP[0], WDCN
+	MOVE @DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @DP[0], A[15]   
+	MOVE @DP[0], ACC
+	MOVE @DP[0], A[AP]
+	MOVE @DP[0], IP
+	MOVE @DP[0], @SP--
+	MOVE @DP[0], SP
+	MOVE @DP[0], IV
+	MOVE @DP[0], LC[0]
+	MOVE @DP[0], LC[1]
+	MOVE @DP[0], @BP[OFFS++]
+	MOVE @DP[0], @BP[OFFS--]
+	MOVE @DP[0], OFFS
+	MOVE @DP[0], DPC
+	MOVE @DP[0], GR
+	MOVE @DP[0], GRL
+	MOVE @DP[0], BP
+	MOVE @DP[0], GRS
+	MOVE @DP[0], GRH
+	MOVE @DP[0], GRXL
+	MOVE @DP[0], FP
+	MOVE @++DP[0], #01h
+	MOVE @++DP[0], AP
+	MOVE @++DP[0], APC
+	MOVE @++DP[0], PSF
+	MOVE @++DP[0], IC
+	MOVE @++DP[0], IMR
+	MOVE @++DP[0], SC
+	MOVE @++DP[0], IIR
+	MOVE @++DP[0], CKCN
+	MOVE @++DP[0], WDCN
+	MOVE @++DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @++DP[0], A[15]   
+	MOVE @++DP[0], ACC
+	MOVE @++DP[0], A[AP]
+	MOVE @++DP[0], IP
+	MOVE @++DP[0], @SP--
+	MOVE @++DP[0], SP
+	MOVE @++DP[0], IV
+	MOVE @++DP[0], LC[0]
+	MOVE @++DP[0], LC[1]
+	MOVE @++DP[0], @BP[OFFS++]
+	MOVE @++DP[0], @BP[OFFS--]
+	MOVE @++DP[0], OFFS
+	MOVE @++DP[0], DPC
+	MOVE @++DP[0], GR
+	MOVE @++DP[0], GRL
+	MOVE @++DP[0], BP
+	MOVE @++DP[0], GRS
+	MOVE @++DP[0], GRH
+	MOVE @++DP[0], GRXL
+	MOVE @++DP[0], FP
+	MOVE @--DP[0], #01h
+	MOVE @--DP[0], AP
+	MOVE @--DP[0], APC
+	MOVE @--DP[0], PSF
+	MOVE @--DP[0], IC
+	MOVE @--DP[0], IMR
+	MOVE @--DP[0], SC
+	MOVE @--DP[0], IIR
+	MOVE @--DP[0], CKCN
+	MOVE @--DP[0], WDCN
+	MOVE @--DP[0], A[0]		;Just Check two boundary conditions
+	MOVE @--DP[0], A[15]   
+	MOVE @--DP[0], ACC
+	MOVE @--DP[0], A[AP]
+	MOVE @--DP[0], IP
+	MOVE @--DP[0], @SP--
+	MOVE @--DP[0], SP
+	MOVE @--DP[0], IV
+	MOVE @--DP[0], LC[0]
+	MOVE @--DP[0], LC[1]
+	MOVE @--DP[0], @BP[OFFS++]
+	MOVE @--DP[0], @BP[OFFS--]
+	MOVE @--DP[0], OFFS
+	MOVE @--DP[0], DPC
+	MOVE @--DP[0], GR
+	MOVE @--DP[0], GRL
+	MOVE @--DP[0], BP
+	MOVE @--DP[0], GRS
+	MOVE @--DP[0], GRH
+	MOVE @--DP[0], GRXL
+	MOVE @--DP[0], FP
+	MOVE DP[0], #01h
+	MOVE DP[0], AP
+	MOVE DP[0], APC
+	MOVE DP[0], PSF
+	MOVE DP[0], IC
+	MOVE DP[0], IMR
+	MOVE DP[0], SC
+	MOVE DP[0], IIR
+	MOVE DP[0], CKCN
+	MOVE DP[0], WDCN
+	MOVE DP[0], A[0]		;Just Check two boundary conditions
+	MOVE DP[0], A[15]   
+	MOVE DP[0], ACC
+	MOVE DP[0], A[AP]
+	MOVE DP[0], IP
+	MOVE DP[0], @SP--
+	MOVE DP[0], SP
+	MOVE DP[0], IV
+	MOVE DP[0], LC[0]
+	MOVE DP[0], LC[1]
+	MOVE DP[0], @BP[OFFS++]
+	MOVE DP[0], @BP[OFFS--]
+	MOVE DP[0], OFFS
+	MOVE DP[0], DPC
+	MOVE DP[0], GR
+	MOVE DP[0], GRL
+	MOVE DP[0], BP
+	MOVE DP[0], GRS
+	MOVE DP[0], GRH
+	MOVE DP[0], GRXL
+	MOVE DP[0], FP
+	MOVE SC, #01h
+	MOVE SC, AP
+	MOVE SC, APC
+	MOVE SC, PSF
+	MOVE SC, IC
+	MOVE SC, IMR
+	MOVE SC, IIR
+	MOVE SC, CKCN
+	MOVE SC, WDCN
+	MOVE SC, A[0]		;Just Check two boundary conditions
+	MOVE SC, A[15]   
+	MOVE SC, ACC
+	MOVE SC, A[AP]
+	MOVE SC, IP
+	MOVE SC, @SP--
+	MOVE SC, SP
+	MOVE SC, IV
+	MOVE SC, LC[0]
+	MOVE SC, LC[1]
+	MOVE SC, @BP[OFFS++]
+	MOVE SC, @BP[OFFS--]
+	MOVE SC, OFFS
+	MOVE SC, DPC
+	MOVE SC, GR
+	MOVE SC, GRL
+	MOVE SC, BP
+	MOVE SC, GRS
+	MOVE SC, GRH
+	MOVE SC, GRXL
+	MOVE SC, FP
+	MOVE SC, @DP[0]	
+	MOVE SC, @DP[1]	
+	MOVE SC, @DP[0]++		
+	MOVE SC, @DP[1]++
+	MOVE SC, @DP[0]--
+	MOVE SC, @DP[1]--
+	MOVE CKCN, #01h
+	MOVE CKCN, AP
+	MOVE CKCN, APC
+	MOVE CKCN, PSF
+	MOVE CKCN, IC
+	MOVE CKCN, IMR
+	MOVE CKCN, SC
+	MOVE CKCN, IIR
+	MOVE CKCN, WDCN
+	MOVE CKCN, A[0]		;Just Check two boundary conditions
+	MOVE CKCN, A[15]   
+	MOVE CKCN, ACC
+	MOVE CKCN, A[AP]
+	MOVE CKCN, IP
+	MOVE CKCN, @SP--
+	MOVE CKCN, SP
+	MOVE CKCN, IV
+	MOVE CKCN, LC[0]
+	MOVE CKCN, LC[1]
+	MOVE CKCN, @BP[OFFS++]
+	MOVE CKCN, @BP[OFFS--]
+	MOVE CKCN, OFFS
+	MOVE CKCN, DPC
+	MOVE CKCN, GR
+	MOVE CKCN, GRL
+	MOVE CKCN, BP
+	MOVE CKCN, GRS
+	MOVE CKCN, GRH
+	MOVE CKCN, GRXL
+	MOVE CKCN, FP
+	MOVE CKCN, @DP[0]	
+	MOVE CKCN, @DP[1]	
+	MOVE CKCN, @DP[0]++		
+	MOVE CKCN, @DP[1]++
+	MOVE CKCN, @DP[0]--
+	MOVE CKCN, @DP[1]--
+	MOVE GRH, #01h
+	MOVE GRH, AP
+	MOVE GRH, APC
+	MOVE GRH, PSF
+	MOVE GRH, IC
+	MOVE GRH, IMR
+	MOVE GRH, SC
+	MOVE GRH, IIR
+	MOVE GRH, CKCN
+	MOVE GRH, WDCN
+	MOVE GRH, A[0]		;Just Check two boundary conditions
+	MOVE GRH, A[15]   
+	MOVE GRH, ACC
+	MOVE GRH, A[AP]
+	MOVE GRH, IP
+	MOVE GRH, @SP--
+	MOVE GRH, SP
+	MOVE GRH, IV
+	MOVE GRH, LC[0]
+	MOVE GRH, LC[1]
+	MOVE GRH, @BP[OFFS++]
+	MOVE GRH, @BP[OFFS--]
+	MOVE GRH, OFFS
+	MOVE GRH, DPC
+	MOVE GRH, GR
+	MOVE GRH, GRL
+	MOVE GRH, BP
+	MOVE GRH, GRS
+	MOVE GRH, GRXL
+	MOVE GRH, FP
+	MOVE GRH, @DP[0]	
+	MOVE GRH, @DP[1]	
+	MOVE GRH, @DP[0]++		
+	MOVE GRH, @DP[1]++
+	MOVE GRH, @DP[0]--
+	MOVE GRH, @DP[1]--
diff --git a/gas/testsuite/gas/maxq20/jump.d b/gas/testsuite/gas/maxq20/jump.d
new file mode 100644
index 000000000000..026d2b9429b6
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jump.d
@@ -0,0 +1,116 @@
+#objdump: -dw
+#name: Jump operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <LableStart>:
+   0:	ff 0c [ 	]*JUMP  #ffh
+   2:	fe 2c [ 	]*JUMP C , #feh
+   4:	09 ac [ 	]*JUMP C , A\[0\]
+   6:	19 ac [ 	]*JUMP C , A\[1\]
+   8:	fb 6c [ 	]*JUMP NC , #fbh
+   a:	09 ec [ 	]*JUMP NC , A\[0\]
+   c:	19 ec [ 	]*JUMP NC , A\[1\]
+   e:	f8 4c [ 	]*JUMP S , #f8h
+  10:	09 cc [ 	]*JUMP S , A\[0\]
+  12:	19 cc [ 	]*JUMP S , A\[1\]
+  14:	f5 1c [ 	]*JUMP Z , #f5h
+  16:	09 9c [ 	]*JUMP Z , A\[0\]
+  18:	19 9c [ 	]*JUMP Z , A\[1\]
+  1a:	f2 5c [ 	]*JUMP NZ , #f2h
+  1c:	09 dc [ 	]*JUMP NZ , A\[0\]
+  1e:	19 dc [ 	]*JUMP NZ , A\[1\]
+  20:	ef 3c [ 	]*JUMP E , #efh
+  22:	ee 7c [ 	]*JUMP NE , #eeh
+  24:	00 7c [ 	]*JUMP NE , #00h
+
+0+026 <Lable1>:
+  26:	ff 0c [ 	]*JUMP  #ffh
+  28:	fe 2c [ 	]*JUMP C , #feh
+  2a:	09 ac [ 	]*JUMP C , A\[0\]
+  2c:	19 ac [ 	]*JUMP C , A\[1\]
+  2e:	fb 6c [ 	]*JUMP NC , #fbh
+  30:	09 ec [ 	]*JUMP NC , A\[0\]
+  32:	19 ec [ 	]*JUMP NC , A\[1\]
+  34:	f8 4c [ 	]*JUMP S , #f8h
+  36:	09 cc [ 	]*JUMP S , A\[0\]
+  38:	19 cc [ 	]*JUMP S , A\[1\]
+  3a:	f5 1c [ 	]*JUMP Z , #f5h
+  3c:	09 9c [ 	]*JUMP Z , A\[0\]
+  3e:	19 9c [ 	]*JUMP Z , A\[1\]
+  40:	f2 5c [ 	]*JUMP NZ , #f2h
+  42:	09 dc [ 	]*JUMP NZ , A\[0\]
+  44:	19 dc [ 	]*JUMP NZ , A\[1\]
+  46:	ef 3c [ 	]*JUMP E , #efh
+  48:	ee 7c [ 	]*JUMP NE , #eeh
+  4a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  4c:	c6 0c [ 	]*JUMP  #c6h
+  4e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  50:	c6 2c [ 	]*JUMP C , #c6h
+  52:	09 ac [ 	]*JUMP C , A\[0\]
+  54:	19 ac [ 	]*JUMP C , A\[1\]
+  56:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  58:	c6 6c [ 	]*JUMP NC , #c6h
+  5a:	09 ec [ 	]*JUMP NC , A\[0\]
+  5c:	19 ec [ 	]*JUMP NC , A\[1\]
+  5e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  60:	c6 1c [ 	]*JUMP Z , #c6h
+  62:	09 9c [ 	]*JUMP Z , A\[0\]
+  64:	19 9c [ 	]*JUMP Z , A\[1\]
+  66:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  68:	c6 5c [ 	]*JUMP NZ , #c6h
+  6a:	09 dc [ 	]*JUMP NZ , A\[0\]
+  6c:	19 dc [ 	]*JUMP NZ , A\[1\]
+  6e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  70:	c6 4c [ 	]*JUMP S , #c6h
+  72:	09 cc [ 	]*JUMP S , A\[0\]
+  74:	19 cc [ 	]*JUMP S , A\[1\]
+  76:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  78:	c6 3c [ 	]*JUMP E , #c6h
+  7a:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  7c:	c6 7c [ 	]*JUMP NE , #c6h
+  7e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  80:	c6 0c [ 	]*JUMP  #c6h
+  82:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  84:	c6 2c [ 	]*JUMP C , #c6h
+  86:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  88:	09 ac [ 	]*JUMP C , A\[0\]
+  8a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  8c:	19 ac [ 	]*JUMP C , A\[1\]
+  8e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  90:	c6 7c [ 	]*JUMP NE , #c6h
+  92:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  94:	c6 1c [ 	]*JUMP Z , #c6h
+  96:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  98:	09 9c [ 	]*JUMP Z , A\[0\]
+  9a:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  9c:	19 9c [ 	]*JUMP Z , A\[1\]
+  9e:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  a0:	c6 5c [ 	]*JUMP NZ , #c6h
+  a2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a4:	09 dc [ 	]*JUMP NZ , A\[0\]
+  a6:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  a8:	19 dc [ 	]*JUMP NZ , A\[1\]
+  aa:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  ac:	c6 4c [ 	]*JUMP S , #c6h
+  ae:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b0:	09 cc [ 	]*JUMP S , A\[0\]
+  b2:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  b4:	19 cc [ 	]*JUMP S , A\[1\]
+  b6:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  b8:	c6 6c [ 	]*JUMP NC , #c6h
+  ba:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  bc:	09 ec [ 	]*JUMP NC , A\[0\]
+  be:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  c0:	19 ec [ 	]*JUMP NC , A\[1\]
+  c2:	04 0b [ 	]*MOVE  PFX\[0\], #04h
+  c4:	c6 3c [ 	]*JUMP E , #c6h
+	...
+
+0+4c6 <LongJump>:
+ 4c6:	3a da [ 	]*NOP 
+ 4c8:	3a da [ 	]*NOP 
+ 4ca:	3a da [ 	]*NOP 
+ 4cc:	3a da [ 	]*NOP 
+ 4ce:	3a da [ 	]*NOP 
diff --git a/gas/testsuite/gas/maxq20/jump.s b/gas/testsuite/gas/maxq20/jump.s
new file mode 100644
index 000000000000..7948cb005d55
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jump.s
@@ -0,0 +1,87 @@
+;# jump.s 
+;# Program flow instructions using JUMP
+.text
+LableStart:	
+		JUMP LableStart
+		JUMP C, LableStart
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LableStart
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP S, LableStart
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP Z, LableStart
+		JUMP Z, A[0]
+		JUMP Z, A[1]	
+		JUMP NZ, LableStart
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP E, LableStart
+		JUMP NE, LableStart
+		JUMP NE, Lable1
+
+Lable1:			
+		SJUMP Lable1		;Checking the SJUMP opcode
+		SJUMP C, Lable1
+		SJUMP C, A[0]
+		SJUMP C, A[1]
+		SJUMP NC, Lable1
+		SJUMP NC, A[0]
+		SJUMP NC, A[1]
+		SJUMP S, Lable1
+		SJUMP S, A[0]
+		SJUMP S, A[1]	
+		SJUMP Z, Lable1
+		SJUMP Z, A[0]
+		SJUMP Z, A[1]	
+		SJUMP NZ, Lable1
+		SJUMP NZ, A[0]
+		SJUMP NZ, A[1]	
+		SJUMP E, Lable1
+		SJUMP NE, Lable1
+		JUMP LongJump
+		JUMP C, LongJump
+		JUMP C, A[0]
+		JUMP C, A[1]
+		JUMP NC, LongJump
+		JUMP NC, A[0]
+		JUMP NC, A[1]
+		JUMP Z, LongJump
+		JUMP Z, A[0]
+		JUMP Z, A[1]
+		JUMP NZ, LongJump
+		JUMP NZ, A[0]
+		JUMP NZ, A[1]
+		JUMP S, LongJump
+		JUMP S, A[0]
+		JUMP S, A[1]	
+		JUMP E, LongJump
+		JUMP NE, LongJump
+		LJUMP LongJump		;test LJUMP also
+		LJUMP C, LongJump
+		LJUMP C, A[0]
+		LJUMP C, A[1]
+		LJUMP NE, LongJump
+		LJUMP Z, LongJump
+		LJUMP Z, A[0]
+		LJUMP Z, A[1]
+		LJUMP NZ, LongJump
+		LJUMP NZ, A[0]
+		LJUMP NZ, A[1]
+		LJUMP S, LongJump
+		LJUMP S, A[0]
+		LJUMP S, A[1]
+		LJUMP NC, LongJump
+		LJUMP NC, A[0]
+		LJUMP NC, A[1]	 
+		LJUMP E, LongJump
+		.fill 0x200, 2, 0 	
+LongJump: 
+		NOP
+		NOP
+		NOP
+		NOP
+		NOP
+	
diff --git a/gas/testsuite/gas/maxq20/jzimm.d b/gas/testsuite/gas/maxq20/jzimm.d
new file mode 100644
index 000000000000..667fa2430d4f
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jzimm.d
@@ -0,0 +1,27 @@
+#objdump: -dw
+#name: Jump immediate operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+0000 <_main>:
+   0:	03 2c [ 	]*JUMP C , #03h
+   2:	03 4c [ 	]*JUMP S , #03h
+   4:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+   6:	ff 1c [ 	]*JUMP Z , #ffh
+   8:	03 5c [ 	]*JUMP NZ , #03h
+   a:	03 2c [ 	]*JUMP C , #03h
+   c:	03 4c [ 	]*JUMP S , #03h
+   e:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+  10:	ff 1c [ 	]*JUMP Z , #ffh
+  12:	03 5c [ 	]*JUMP NZ , #03h
+  14:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  16:	03 2c [ 	]*JUMP C , #03h
+  18:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1a:	03 4c [ 	]*JUMP S , #03h
+  1c:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1e:	0f 0b [ 	]*MOVE  PFX\[0\], #0fh
+  20:	ff 1c [ 	]*JUMP Z , #ffh
+  22:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  24:	03 5c [ 	]*JUMP NZ , #03h
+	...
diff --git a/gas/testsuite/gas/maxq20/jzimm.s b/gas/testsuite/gas/maxq20/jzimm.s
new file mode 100644
index 000000000000..bf05cf4cfe5a
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/jzimm.s
@@ -0,0 +1,17 @@
+.text
+
+_main:   
+ 	        JUMP C, #03h
+                JUMP S, #03h
+                JUMP Z, #fffh
+                JUMP NZ, #03h
+
+		SJUMP C, #03h
+                SJUMP S, #03h
+                SJUMP Z, #fffh
+                SJUMP NZ, #03h
+
+		LJUMP C, #03h
+                LJUMP S, #03h
+                LJUMP Z, #fffh
+                LJUMP NZ, #03h
diff --git a/gas/testsuite/gas/maxq20/logical.d b/gas/testsuite/gas/maxq20/logical.d
new file mode 100644
index 000000000000..2f8cfd08b56c
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/logical.d
@@ -0,0 +1,25 @@
+#objdump:-dw
+#name: logical operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	00 08 [ 	]*MOVE  AP, #00h
+   2:	ff 1a [ 	]*AND  #ffh
+   4:	f0 2a [ 	]*OR  #f0h
+   6:	fe 3a [ 	]*XOR  #feh
+   8:	1a 8a [ 	]*CPL 
+   a:	9a 8a [ 	]*NEG 
+   c:	2a 8a [ 	]*SLA 
+   e:	3a 8a [ 	]*SLA2 
+  10:	6a 8a [ 	]*SLA4 
+  12:	4a 8a [ 	]*RL 
+  14:	5a 8a [ 	]*RLC 
+  16:	fa 8a [ 	]*SRA 
+  18:	ea 8a [ 	]*SRA2 
+  1a:	ba 8a [ 	]*SRA4 
+  1c:	aa 8a [ 	]*SR 
+  1e:	ca 8a [ 	]*RR 
+  20:	da 8a [ 	]*RRC 
+	...
diff --git a/gas/testsuite/gas/maxq20/logical.s b/gas/testsuite/gas/maxq20/logical.s
new file mode 100644
index 000000000000..ac023163b33f
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/logical.s
@@ -0,0 +1,22 @@
+;# logical.s
+;# Verifies all the logical operation in the file
+
+.text	
+foo:
+	MOVE AP, #00h	;Set AC[0] as the active accumulator
+	AND #FFh	;AND AC[0] with 0xFF
+	OR #F0h
+	XOR #FEh
+	CPL
+	NEG
+	SLA
+	SLA2	
+	SLA4
+	RL	
+	RLC
+	SRA
+	SRA2
+	SRA4
+	SR
+	RR
+	RRC
diff --git a/gas/testsuite/gas/maxq20/math.d b/gas/testsuite/gas/maxq20/math.d
new file mode 100644
index 000000000000..34a70dd0f8d7
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/math.d
@@ -0,0 +1,41 @@
+#objdump:-dw
+#name: Math operations
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <foo>:
+   0:	01 4a [ 	]*ADD  #01h
+   2:	02 4a [ 	]*ADD  #02h
+   4:	03 4a [ 	]*ADD  #03h
+   6:	04 4a [ 	]*ADD  #04h
+   8:	05 4a [ 	]*ADD  #05h
+   a:	09 ca [ 	]*ADD  A\[0\]
+   c:	19 ca [ 	]*ADD  A\[1\]
+   e:	29 ca [ 	]*ADD  A\[2\]
+  10:	39 ca [ 	]*ADD  A\[3\]
+  12:	49 ca [ 	]*ADD  A\[4\]
+  14:	31 6a [ 	]*ADDC  #31h
+  16:	32 6a [ 	]*ADDC  #32h
+  18:	33 6a [ 	]*ADDC  #33h
+  1a:	09 ea [ 	]*ADDC  A\[0\]
+  1c:	19 ea [ 	]*ADDC  A\[1\]
+  1e:	29 ea [ 	]*ADDC  A\[2\]
+  20:	39 ea [ 	]*ADDC  A\[3\]
+  22:	01 5a [ 	]*SUB  #01h
+  24:	02 5a [ 	]*SUB  #02h
+  26:	03 5a [ 	]*SUB  #03h
+  28:	04 5a [ 	]*SUB  #04h
+  2a:	05 5a [ 	]*SUB  #05h
+  2c:	09 da [ 	]*SUB  A\[0\]
+  2e:	19 da [ 	]*SUB  A\[1\]
+  30:	29 da [ 	]*SUB  A\[2\]
+  32:	39 da [ 	]*SUB  A\[3\]
+  34:	49 da [ 	]*SUB  A\[4\]
+  36:	31 7a [ 	]*SUBB  #31h
+  38:	32 7a [ 	]*SUBB  #32h
+  3a:	33 7a [ 	]*SUBB  #33h
+  3c:	09 fa [ 	]*SUBB  A\[0\]
+  3e:	19 fa [ 	]*SUBB  A\[1\]
+  40:	29 fa [ 	]*SUBB  A\[2\]
+  42:	39 fa [ 	]*SUBB  A\[3\]
diff --git a/gas/testsuite/gas/maxq20/math.s b/gas/testsuite/gas/maxq20/math.s
new file mode 100644
index 000000000000..b3c1bd7af31b
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/math.s
@@ -0,0 +1,39 @@
+;# math.s
+;# Implements all the math intuctions
+
+.text
+foo:	
+	ADD #01h	; add 01h to accumulator
+	ADD #02h
+	ADD #03h
+	ADD #04h
+	ADD #05h
+	ADD A[0]	; Add Active accumulator+A[0]
+	ADD A[1]
+	ADD A[2]
+	ADD A[3]
+	ADD A[4]
+	ADDC #31h
+	ADDC #32h
+	ADDC #33h
+	ADDC A[0]
+	ADDC A[1]
+	ADDC A[2]
+	ADDC A[3]
+	SUB #01h	; Substract 01h from accumulator
+	SUB #02h
+	SUB #03h
+	SUB #04h
+	SUB #05h
+	SUB A[0]	; Active accumulator-A[0]
+	SUB A[1]
+	SUB A[2]
+	SUB A[3]
+	SUB A[4]	
+	SUBB #31h
+	SUBB #32h
+	SUBB #33h
+	SUBB A[0]
+	SUBB A[1]
+	SUBB A[2]
+	SUBB A[3]
diff --git a/gas/testsuite/gas/maxq20/maxq20.exp b/gas/testsuite/gas/maxq20/maxq20.exp
new file mode 100644
index 000000000000..d2857f617b96
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/maxq20.exp
@@ -0,0 +1,55 @@
+#
+# MAXQ20 tests
+#
+proc run_list_test { name opts } {
+    global srcdir subdir
+    set testname "maxq20 $name"
+    set file $srcdir/$subdir/$name
+    gas_run ${name}.s $opts ">&dump.out"
+    if { [regexp_diff "dump.out" "${file}.l"] } then {
+	fail $testname
+	verbose "output is [file_contents "dump.out"]" 2
+	return
+    }
+    pass $testname
+}
+
+proc gas_64_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help]
+}
+
+proc gas_32_check { } {
+    global NM
+    global NMFLAGS
+    global srcdir
+
+    catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
+    return [regexp "targets:.*maxq" $nm_help]
+}
+
+
+if [expr ([istarget "maxq-*-*"] ||  [istarget "maxq-coff-*-*"]) && [gas_32_check]]  then {
+
+    global ASFLAGS
+    set old_ASFLAGS "$ASFLAGS"
+    set ASFLAGS "$ASFLAGS"
+
+    run_dump_test "range"
+    run_dump_test "data3"
+    run_dump_test "data2"
+    run_dump_test "call"
+    run_dump_test "jump"
+    run_dump_test "logical"
+    run_dump_test "math"
+    run_dump_test "bits"
+    run_dump_test "data1"
+    run_dump_test "jzimm"
+
+    set ASFLAGS "$old_ASFLAGS"
+}
+
diff --git a/gas/testsuite/gas/maxq20/pfx2.s b/gas/testsuite/gas/maxq20/pfx2.s
new file mode 100644
index 000000000000..b2fcec27218f
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pfx2.s
@@ -0,0 +1,5 @@
+.text
+	MOVE A[10], #1234h
+	MOVE A[9], #1212h
+	MOVE A[8], #1111h
+	MOVE A[7], #2222h
diff --git a/gas/testsuite/gas/maxq20/pmtest.d b/gas/testsuite/gas/maxq20/pmtest.d
new file mode 100644
index 000000000000..b93e69c7ec18
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pmtest.d
@@ -0,0 +1,25 @@
+#objdump: -dw
+#name: MaC supoprt check
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	05 13 [ 	]*MOVE  13h, #05h
+   2:	e9 53 [ 	]*MOVE  53h, #e9h
+   4:	09 e3 [ 	]*MOVE  63h, A\[0\]
+   6:	12 14 [ 	]*MOVE  14h, #12h
+   8:	12 44 [ 	]*MOVE  44h, #12h
+   a:	00 2b [ 	]*MOVE  PFX\[2\], #00h
+   c:	09 84 [ 	]*MOVE  04h, A\[0\]
+   e:	7b 15 [ 	]*MOVE  15h, #7bh
+  10:	13 25 [ 	]*MOVE  25h, #13h
+  12:	d9 e5 [ 	]*MOVE  65h, A\[13\]
+  14:	13 15 [ 	]*MOVE  15h, #13h
+  16:	13 a5 [ 	]*MOVE  25h, 13h
+  18:	12 13 [ 	]*MOVE  13h, #12h
+  1a:	12 2b [ 	]*MOVE  PFX\[2\], #12h
+  1c:	34 59 [ 	]*MOVE  A\[5\], #34h
+  1e:	04 2b [ 	]*MOVE  PFX\[2\], #04h
+  20:	d2 79 [ 	]*MOVE  A\[7\], #d2h
+	...
diff --git a/gas/testsuite/gas/maxq20/pmtest.s b/gas/testsuite/gas/maxq20/pmtest.s
new file mode 100644
index 000000000000..70b898d73e04
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pmtest.s
@@ -0,0 +1,25 @@
+;# Peripheral(plugable) module test file 
+.text
+
+; Timer1 test module configured at mod. no. 3
+move T1CN, #05h
+move T1MD, #233
+move T1CL,A[0]
+; Timer2 module test plugged at mod. no. 4
+move T2CFG, #12h
+move T2V, #12h
+move T2C, A[0]
+
+; MAC module test plugged at 5
+move MCNT, #123
+move MA, #13h
+move MC0, A[13]
+
+;test the pm support 
+move 15h,#13h
+move 25h, 13h
+move 13h, #12h
+
+move A[13], #1234h	; PFX 2 test
+move A[15], #1234
+
diff --git a/gas/testsuite/gas/maxq20/pxf0.s b/gas/testsuite/gas/maxq20/pxf0.s
new file mode 100644
index 000000000000..7672186677ac
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/pxf0.s
@@ -0,0 +1,4 @@
+.text
+	MOVE A[0],#1234h
+	MOVE A[1],4321h
+
diff --git a/gas/testsuite/gas/maxq20/range.d b/gas/testsuite/gas/maxq20/range.d
new file mode 100644
index 000000000000..3453b1ad753c
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/range.d
@@ -0,0 +1,49 @@
+#objdump:-dw
+#name: limit checks for maxq immediate data
+
+.*: +file format .*
+
+Disassembly of section .text:
+0+000 <.text>:
+   0:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   2:	ff 09 [ 	]*MOVE  A\[0\], #ffh
+   4:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   6:	ff 08 [ 	]*MOVE  AP, #ffh
+   8:	01 09 [ 	]*MOVE  A\[0\], #01h
+   a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+   c:	83 08 [ 	]*MOVE  AP, #83h
+   e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  10:	82 08 [ 	]*MOVE  AP, #82h
+  12:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  14:	81 08 [ 	]*MOVE  AP, #81h
+  16:	7d 09 [ 	]*MOVE  A\[0\], #7dh
+  18:	7e 09 [ 	]*MOVE  A\[0\], #7eh
+  1a:	80 09 [ 	]*MOVE  A\[0\], #80h
+  1c:	fe 09 [ 	]*MOVE  A\[0\], #feh
+  1e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  20:	ff 0d [ 	]*MOVE  @\+\+SP, #ffh
+  22:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  24:	82 0d [ 	]*MOVE  @\+\+SP, #82h
+  26:	fe 0d [ 	]*MOVE  @\+\+SP, #feh
+  28:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2a:	81 0d [ 	]*MOVE  @\+\+SP, #81h
+  2c:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  2e:	80 0d [ 	]*MOVE  @\+\+SP, #80h
+  30:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  32:	ff 4a [ 	]*ADD  #ffh
+  34:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  36:	81 4a [ 	]*ADD  #81h
+  38:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  3a:	7f 4a [ 	]*ADD  #7fh
+  3c:	7f 4a [ 	]*ADD  #7fh
+  3e:	80 4a [ 	]*ADD  #80h
+  40:	81 4a [ 	]*ADD  #81h
+  42:	fe 4a [ 	]*ADD  #feh
+  44:	ff 4a [ 	]*ADD  #ffh
+  46:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  48:	02 4a [ 	]*ADD  #02h
+  4a:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  4c:	81 4a [ 	]*ADD  #81h
+  4e:	ff 0b [ 	]*MOVE  PFX\[0\], #ffh
+  50:	7f 4a [ 	]*ADD  #7fh
+	...
diff --git a/gas/testsuite/gas/maxq20/range.s b/gas/testsuite/gas/maxq20/range.s
new file mode 100644
index 000000000000..f3cdc9572ad6
--- /dev/null
+++ b/gas/testsuite/gas/maxq20/range.s
@@ -0,0 +1,30 @@
+;# checks the 8 bit ranges
+;# all negative values should contain a Prefix for MAXQ20
+;# immediate values with one operand for MAXQ10 skips PFX
+.text 
+	move A[0], #-1  
+	move Ap, #-1
+	move a[0], #1
+	move AP, #-125	; AP is an 8 bit register 
+	move AP, #-126
+	move AP, #-127
+	move A[0], #125		; A[0] is an 16 bit register - no pfx req. here
+	move A[0], #126
+	move A[0], #128
+	move A[0], #254	        ; ---------------
+	move @++SP, #-1		; check PFX generation for mem operands
+	move @++sp, #-126	; -
+	move @++sp, #254		; - no pFX here
+	move @++sp, #-127	; -
+	move @++sp, #-128	;--------------------------
+	Add #-1			;Check PFX gen. for single operand instructions
+	Add #-127
+	Add #-129
+	Add #127
+	Add #128
+	add #129
+	add #254
+	add #ffh
+	add #-254
+	add #-127
+	add #-129		; --------------------
diff --git a/gas/testsuite/gas/mips/bge.d b/gas/testsuite/gas/mips/bge.d
index 189ae3f9f754..2ef285088bd9 100644
--- a/gas/testsuite/gas/mips/bge.d
+++ b/gas/testsuite/gas/mips/bge.d
@@ -52,20 +52,20 @@ Disassembly of section .text:
 0+00a8 <[^>]*> slt	at,a1,a0
 0+00ac <[^>]*> bnezl	at,0+0000 <text_label>
 0+00b0 <[^>]*> nop
-#0+00b4 <[^>]*> slt	at,a0,a1
-#0+00b8 <[^>]*> beqz	at,000000b8 <text_label\+0xb8>
-#[ 	]*b8: R_MIPS_PC16	external_label
-#0+00bc <[^>]*> nop
-#0+00c0 <[^>]*> slt	at,a1,a0
-#0+00c4 <[^>]*> bnez	at,000000c4 <text_label\+0xc4>
-#[ 	]*c4: R_MIPS_PC16	external_label
-#0+00c8 <[^>]*> nop
-#0+00cc <[^>]*> slt	at,a0,a1
-#0+00d0 <[^>]*> beqzl	at,000000d0 <text_label\+0xd0>
-#[ 	]*d0: R_MIPS_PC16	external_label
-#0+00d4 <[^>]*> nop
-#0+00d8 <[^>]*> slt	at,a1,a0
-#0+00dc <[^>]*> bnezl	at,000000dc <text_label\+0xdc>
-#[ 	]*dc: R_MIPS_PC16	external_label
-#0+00e0 <[^>]*> nop
+0+00b4 <[^>]*> slt	at,a0,a1
+0+00b8 <[^>]*> beqz	at,000000b8 <text_label\+0xb8>
+[ 	]*b8: R_MIPS_PC16	external_label
+0+00bc <[^>]*> nop
+0+00c0 <[^>]*> slt	at,a1,a0
+0+00c4 <[^>]*> bnez	at,000000c4 <text_label\+0xc4>
+[ 	]*c4: R_MIPS_PC16	external_label
+0+00c8 <[^>]*> nop
+0+00cc <[^>]*> slt	at,a0,a1
+0+00d0 <[^>]*> beqzl	at,000000d0 <text_label\+0xd0>
+[ 	]*d0: R_MIPS_PC16	external_label
+0+00d4 <[^>]*> nop
+0+00d8 <[^>]*> slt	at,a1,a0
+0+00dc <[^>]*> bnezl	at,000000dc <text_label\+0xdc>
+[ 	]*dc: R_MIPS_PC16	external_label
+0+00e0 <[^>]*> nop
 	...
diff --git a/gas/testsuite/gas/mips/bge.s b/gas/testsuite/gas/mips/bge.s
index bedab79401d5..4b4e58f6d69b 100644
--- a/gas/testsuite/gas/mips/bge.s
+++ b/gas/testsuite/gas/mips/bge.s
@@ -25,10 +25,10 @@ text_label:
 	bgtl	$4,$5,text_label
 
 # Branch to an external label.
-#	bge	$4,$5,external_label
-#	bgt	$4,$5,external_label
-#	bgel	$4,$5,external_label
-#	bgtl	$4,$5,external_label
+	bge	$4,$5,external_label
+	bgt	$4,$5,external_label
+	bgel	$4,$5,external_label
+	bgtl	$4,$5,external_label
 
 # Round to a 16 byte boundary, for ease in testing multiple targets.
 	nop
diff --git a/gas/testsuite/gas/mips/bgeu.d b/gas/testsuite/gas/mips/bgeu.d
index b367e0e756d2..4c0753b3f059 100644
--- a/gas/testsuite/gas/mips/bgeu.d
+++ b/gas/testsuite/gas/mips/bgeu.d
@@ -46,20 +46,20 @@ Disassembly of section .text:
 0+0090 <[^>]*> sltu	at,a1,a0
 0+0094 <[^>]*> bnezl	at,0+0000 <text_label>
 0+0098 <[^>]*> nop
-#0+009c <[^>]*> sltu	at,a0,a1
-#0+00a0 <[^>]*> beqz	at,000000a0 <text_label\+0xa0>
-#[ 	]*a0: R_MIPS_PC16	external_label
-#0+00a4 <[^>]*> nop
-#0+00a8 <[^>]*> sltu	at,a1,a0
-#0+00ac <[^>]*> bnez	at,000000ac <text_label\+0xac>
-#[ 	]*ac: R_MIPS_PC16	external_label
-#0+00b0 <[^>]*> nop
-#0+00b4 <[^>]*> sltu	at,a0,a1
-#0+00b8 <[^>]*> beqzl	at,000000b8 <text_label\+0xb8>
-#[ 	]*b8: R_MIPS_PC16	external_label
-#0+00bc <[^>]*> nop
-#0+00c0 <[^>]*> sltu	at,a1,a0
-#0+00c4 <[^>]*> bnezl	at,000000c4 <text_label\+0xc4>
-#[ 	]*c4: R_MIPS_PC16	external_label
-#0+00c8 <[^>]*> nop
+0+009c <[^>]*> sltu	at,a0,a1
+0+00a0 <[^>]*> beqz	at,000000a0 <text_label\+0xa0>
+[ 	]*a0: R_MIPS_PC16	external_label
+0+00a4 <[^>]*> nop
+0+00a8 <[^>]*> sltu	at,a1,a0
+0+00ac <[^>]*> bnez	at,000000ac <text_label\+0xac>
+[ 	]*ac: R_MIPS_PC16	external_label
+0+00b0 <[^>]*> nop
+0+00b4 <[^>]*> sltu	at,a0,a1
+0+00b8 <[^>]*> beqzl	at,000000b8 <text_label\+0xb8>
+[ 	]*b8: R_MIPS_PC16	external_label
+0+00bc <[^>]*> nop
+0+00c0 <[^>]*> sltu	at,a1,a0
+0+00c4 <[^>]*> bnezl	at,000000c4 <text_label\+0xc4>
+[ 	]*c4: R_MIPS_PC16	external_label
+0+00c8 <[^>]*> nop
 	...
diff --git a/gas/testsuite/gas/mips/bgeu.s b/gas/testsuite/gas/mips/bgeu.s
index 8a5244c73a60..cccd584f780a 100644
--- a/gas/testsuite/gas/mips/bgeu.s
+++ b/gas/testsuite/gas/mips/bgeu.s
@@ -23,10 +23,10 @@ text_label:
 	bgtul	$4,$5,text_label
 
 # Branch to an external label.
-#	bgeu	$4,$5,external_label
-#	bgtu	$4,$5,external_label
-#	bgeul	$4,$5,external_label
-#	bgtul	$4,$5,external_label
+	bgeu	$4,$5,external_label
+	bgtu	$4,$5,external_label
+	bgeul	$4,$5,external_label
+	bgtul	$4,$5,external_label
 
 # Round to a 16 byte boundary, for ease in testing multiple targets.
 	nop
diff --git a/gas/testsuite/gas/mips/blt.d b/gas/testsuite/gas/mips/blt.d
index fc6aa1906a66..fb2914aa07b7 100644
--- a/gas/testsuite/gas/mips/blt.d
+++ b/gas/testsuite/gas/mips/blt.d
@@ -52,20 +52,20 @@ Disassembly of section .text:
 0+00a8 <[^>]*> slt	at,a1,a0
 0+00ac <[^>]*> beqzl	at,0+0000 <text_label>
 0+00b0 <[^>]*> nop
-#0+00b4 <[^>]*> slt	at,a0,a1
-#0+00b8 <[^>]*> bnez	at,000000b8 <text_label\+0xb8>
-#[ 	]*b8: R_MIPS_PC16	external_label
-#0+00bc <[^>]*> nop
-#0+00c0 <[^>]*> slt	at,a1,a0
-#0+00c4 <[^>]*> beqz	at,000000c4 <text_label\+0xc4>
-#[ 	]*c4: R_MIPS_PC16	external_label
-#0+00c8 <[^>]*> nop
-#0+00cc <[^>]*> slt	at,a0,a1
-#0+00d0 <[^>]*> bnezl	at,000000d0 <text_label\+0xd0>
-#[ 	]*d0: R_MIPS_PC16	external_label
-#0+00d4 <[^>]*> nop
-#0+00d8 <[^>]*> slt	at,a1,a0
-#0+00dc <[^>]*> beqzl	at,000000dc <text_label\+0xdc>
-#[ 	]*dc: R_MIPS_PC16	external_label
-#0+00e0 <[^>]*> nop
+0+00b4 <[^>]*> slt	at,a0,a1
+0+00b8 <[^>]*> bnez	at,000000b8 <text_label\+0xb8>
+[ 	]*b8: R_MIPS_PC16	external_label
+0+00bc <[^>]*> nop
+0+00c0 <[^>]*> slt	at,a1,a0
+0+00c4 <[^>]*> beqz	at,000000c4 <text_label\+0xc4>
+[ 	]*c4: R_MIPS_PC16	external_label
+0+00c8 <[^>]*> nop
+0+00cc <[^>]*> slt	at,a0,a1
+0+00d0 <[^>]*> bnezl	at,000000d0 <text_label\+0xd0>
+[ 	]*d0: R_MIPS_PC16	external_label
+0+00d4 <[^>]*> nop
+0+00d8 <[^>]*> slt	at,a1,a0
+0+00dc <[^>]*> beqzl	at,000000dc <text_label\+0xdc>
+[ 	]*dc: R_MIPS_PC16	external_label
+0+00e0 <[^>]*> nop
 	...
diff --git a/gas/testsuite/gas/mips/blt.s b/gas/testsuite/gas/mips/blt.s
index cdeff16d7837..9b2ed08524f3 100644
--- a/gas/testsuite/gas/mips/blt.s
+++ b/gas/testsuite/gas/mips/blt.s
@@ -25,10 +25,10 @@ text_label:
 	blel	$4,$5,text_label
 
 # Branch to an external label.
-#	blt	$4,$5,external_label
-#	ble	$4,$5,external_label
-#	bltl	$4,$5,external_label
-#	blel	$4,$5,external_label
+	blt	$4,$5,external_label
+	ble	$4,$5,external_label
+	bltl	$4,$5,external_label
+	blel	$4,$5,external_label
 
 # Round to a 16 byte boundary, for ease in testing multiple targets.
 	nop
diff --git a/gas/testsuite/gas/mips/bltu.d b/gas/testsuite/gas/mips/bltu.d
index 945d2a4d1f5d..308afdf95d30 100644
--- a/gas/testsuite/gas/mips/bltu.d
+++ b/gas/testsuite/gas/mips/bltu.d
@@ -46,20 +46,20 @@ Disassembly of section .text:
 0+0090 <[^>]*> sltu	at,a1,a0
 0+0094 <[^>]*> beqzl	at,0+0000 <text_label>
 0+0098 <[^>]*> nop
-#0+009c <[^>]*> sltu	at,a0,a1
-#0+00a0 <[^>]*> bnez	at,000000a0 <text_label\+0xa0>
-#[ 	]*a0: R_MIPS_PC16	external_label
-#0+00a4 <[^>]*> nop
-#0+00a8 <[^>]*> sltu	at,a1,a0
-#0+00ac <[^>]*> beqz	at,000000ac <text_label\+0xac>
-#[ 	]*ac: R_MIPS_PC16	external_label
-#0+00b0 <[^>]*> nop
-#0+00b4 <[^>]*> sltu	at,a0,a1
-#0+00b8 <[^>]*> bnezl	at,000000b8 <text_label\+0xb8>
-#[ 	]*b8: R_MIPS_PC16	external_label
-#0+00bc <[^>]*> nop
-#0+00c0 <[^>]*> sltu	at,a1,a0
-#0+00c4 <[^>]*> beqzl	at,000000c4 <text_label\+0xc4>
-#[ 	]*c4: R_MIPS_PC16	external_label
-#0+00c8 <[^>]*> nop
+0+009c <[^>]*> sltu	at,a0,a1
+0+00a0 <[^>]*> bnez	at,000000a0 <text_label\+0xa0>
+[ 	]*a0: R_MIPS_PC16	external_label
+0+00a4 <[^>]*> nop
+0+00a8 <[^>]*> sltu	at,a1,a0
+0+00ac <[^>]*> beqz	at,000000ac <text_label\+0xac>
+[ 	]*ac: R_MIPS_PC16	external_label
+0+00b0 <[^>]*> nop
+0+00b4 <[^>]*> sltu	at,a0,a1
+0+00b8 <[^>]*> bnezl	at,000000b8 <text_label\+0xb8>
+[ 	]*b8: R_MIPS_PC16	external_label
+0+00bc <[^>]*> nop
+0+00c0 <[^>]*> sltu	at,a1,a0
+0+00c4 <[^>]*> beqzl	at,000000c4 <text_label\+0xc4>
+[ 	]*c4: R_MIPS_PC16	external_label
+0+00c8 <[^>]*> nop
 	...
diff --git a/gas/testsuite/gas/mips/bltu.s b/gas/testsuite/gas/mips/bltu.s
index 88034e8bc0cf..602b7b283d65 100644
--- a/gas/testsuite/gas/mips/bltu.s
+++ b/gas/testsuite/gas/mips/bltu.s
@@ -23,10 +23,10 @@ text_label:
 	bleul	$4,$5,text_label
 
 # Branch to an external label.
-#	bltu	$4,$5,external_label
-#	bleu	$4,$5,external_label
-#	bltul	$4,$5,external_label
-#	bleul	$4,$5,external_label
+	bltu	$4,$5,external_label
+	bleu	$4,$5,external_label
+	bltul	$4,$5,external_label
+	bleul	$4,$5,external_label
 
 # Round to a 16 byte boundary, for ease in testing multiple targets.
 	nop
diff --git a/gas/testsuite/gas/mips/branch-misc-2-64.d b/gas/testsuite/gas/mips/branch-misc-2-64.d
new file mode 100644
index 000000000000..0b56d976df26
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-2-64.d
@@ -0,0 +1,62 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2-64
+#source: branch-misc-2.s
+#as: -64 -non_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 04110000 	bal	0000000000000040 <x\+0x4>
+[ 	]*3c: R_MIPS_PC16	g1\+0xfffffffffffffffc
+[ 	]*3c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*3c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 04110000 	bal	0000000000000048 <x\+0xc>
+[ 	]*44: R_MIPS_PC16	g2\+0xfffffffffffffffc
+[ 	]*44: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*44: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 04110000 	bal	0000000000000050 <x\+0x14>
+[ 	]*4c: R_MIPS_PC16	g3\+0xfffffffffffffffc
+[ 	]*4c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*4c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 04110000 	bal	0000000000000058 <x\+0x1c>
+[ 	]*54: R_MIPS_PC16	g4\+0xfffffffffffffffc
+[ 	]*54: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*54: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 04110000 	bal	0000000000000060 <x\+0x24>
+[ 	]*5c: R_MIPS_PC16	g5\+0xfffffffffffffffc
+[ 	]*5c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*5c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 04110000 	bal	0000000000000068 <x\+0x2c>
+[ 	]*64: R_MIPS_PC16	g6\+0xfffffffffffffffc
+[ 	]*64: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*64: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 10000000 	b	00000000000000ac <g6\+0x4>
+[ 	]*a8: R_MIPS_PC16	x1\+0xfffffffffffffffc
+[ 	]*a8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*a8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 10000000 	b	00000000000000b4 <g6\+0xc>
+[ 	]*b0: R_MIPS_PC16	x2\+0xfffffffffffffffc
+[ 	]*b0: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*b0: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 10000000 	b	00000000000000bc <g6\+0x14>
+[ 	]*b8: R_MIPS_PC16	\.data\+0xfffffffffffffffc
+[ 	]*b8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*b8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/branch-misc-2.d b/gas/testsuite/gas/mips/branch-misc-2.d
new file mode 100644
index 000000000000..7ba5dbc24a15
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-2.d
@@ -0,0 +1,43 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2
+#as: -32 -non_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 0411ffff 	bal	0000003c <x>
+[ 	]*3c: R_MIPS_PC16	g1
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 0411ffff 	bal	00000044 <x\+0x8>
+[ 	]*44: R_MIPS_PC16	g2
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 0411ffff 	bal	0000004c <x\+0x10>
+[ 	]*4c: R_MIPS_PC16	g3
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 0411ffff 	bal	00000054 <x\+0x18>
+[ 	]*54: R_MIPS_PC16	g4
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 0411ffff 	bal	0000005c <x\+0x20>
+[ 	]*5c: R_MIPS_PC16	g5
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 0411ffff 	bal	00000064 <x\+0x28>
+[ 	]*64: R_MIPS_PC16	g6
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 1000ffff 	b	000000a8 <g6>
+[ 	]*a8: R_MIPS_PC16	x1
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 1000ffff 	b	000000b0 <g6\+0x8>
+[ 	]*b0: R_MIPS_PC16	x2
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 1000ffff 	b	000000b8 <g6\+0x10>
+[ 	]*b8: R_MIPS_PC16	\.data
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/branch-misc-2.l b/gas/testsuite/gas/mips/branch-misc-2.l
deleted file mode 100644
index a66aaa66622d..000000000000
--- a/gas/testsuite/gas/mips/branch-misc-2.l
+++ /dev/null
@@ -1,4 +0,0 @@
-.*: Assembler messages:
-.*:35: Error: Cannot branch to undefined symbol.
-.*:36: Error: Cannot branch to undefined symbol.
-.*:37: Error: Cannot branch to symbol in another section.
diff --git a/gas/testsuite/gas/mips/branch-misc-2pic-64.d b/gas/testsuite/gas/mips/branch-misc-2pic-64.d
new file mode 100644
index 000000000000..dadde8767192
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-2pic-64.d
@@ -0,0 +1,62 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2-64
+#source: branch-misc-2.s
+#as: -64 -call_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 04110000 	bal	0000000000000040 <x\+0x4>
+[ 	]*3c: R_MIPS_PC16	g1\+0xfffffffffffffffc
+[ 	]*3c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*3c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 04110000 	bal	0000000000000048 <x\+0xc>
+[ 	]*44: R_MIPS_PC16	g2\+0xfffffffffffffffc
+[ 	]*44: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*44: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 04110000 	bal	0000000000000050 <x\+0x14>
+[ 	]*4c: R_MIPS_PC16	g3\+0xfffffffffffffffc
+[ 	]*4c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*4c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 04110000 	bal	0000000000000058 <x\+0x1c>
+[ 	]*54: R_MIPS_PC16	g4\+0xfffffffffffffffc
+[ 	]*54: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*54: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 04110000 	bal	0000000000000060 <x\+0x24>
+[ 	]*5c: R_MIPS_PC16	g5\+0xfffffffffffffffc
+[ 	]*5c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*5c: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 04110000 	bal	0000000000000068 <x\+0x2c>
+[ 	]*64: R_MIPS_PC16	g6\+0xfffffffffffffffc
+[ 	]*64: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*64: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 10000000 	b	00000000000000ac <g6\+0x4>
+[ 	]*a8: R_MIPS_PC16	x1\+0xfffffffffffffffc
+[ 	]*a8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*a8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 10000000 	b	00000000000000b4 <g6\+0xc>
+[ 	]*b0: R_MIPS_PC16	x2\+0xfffffffffffffffc
+[ 	]*b0: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*b0: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 10000000 	b	00000000000000bc <g6\+0x14>
+[ 	]*b8: R_MIPS_PC16	\.data\+0xfffffffffffffffc
+[ 	]*b8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+[ 	]*b8: R_MIPS_NONE	\*ABS\*\+0xfffffffffffffffc
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/branch-misc-2pic.d b/gas/testsuite/gas/mips/branch-misc-2pic.d
new file mode 100644
index 000000000000..516b490b691c
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-2pic.d
@@ -0,0 +1,44 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic
+#source: branch-misc-2.s
+#as: -32 -call_shared
+
+# Test the backward branches to globals symbols in current file.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+003c <[^>]*> 0411ffff 	bal	0000003c <x>
+[ 	]*3c: R_MIPS_PC16	g1
+0+0040 <[^>]*> 00000000 	nop
+0+0044 <[^>]*> 0411ffff 	bal	00000044 <x\+0x8>
+[ 	]*44: R_MIPS_PC16	g2
+0+0048 <[^>]*> 00000000 	nop
+0+004c <[^>]*> 0411ffff 	bal	0000004c <x\+0x10>
+[ 	]*4c: R_MIPS_PC16	g3
+0+0050 <[^>]*> 00000000 	nop
+0+0054 <[^>]*> 0411ffff 	bal	00000054 <x\+0x18>
+[ 	]*54: R_MIPS_PC16	g4
+0+0058 <[^>]*> 00000000 	nop
+0+005c <[^>]*> 0411ffff 	bal	0000005c <x\+0x20>
+[ 	]*5c: R_MIPS_PC16	g5
+0+0060 <[^>]*> 00000000 	nop
+0+0064 <[^>]*> 0411ffff 	bal	00000064 <x\+0x28>
+[ 	]*64: R_MIPS_PC16	g6
+0+0068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0+00a8 <[^>]*> 1000ffff 	b	000000a8 <g6>
+[ 	]*a8: R_MIPS_PC16	x1
+0+00ac <[^>]*> 00000000 	nop
+0+00b0 <[^>]*> 1000ffff 	b	000000b0 <g6\+0x8>
+[ 	]*b0: R_MIPS_PC16	x2
+0+00b4 <[^>]*> 00000000 	nop
+0+00b8 <[^>]*> 1000ffff 	b	000000b8 <g6\+0x10>
+[ 	]*b8: R_MIPS_PC16	\.data
+0+00bc <[^>]*> 00000000 	nop
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/branch-misc-2pic.l b/gas/testsuite/gas/mips/branch-misc-2pic.l
deleted file mode 100644
index 3ddc97aa2209..000000000000
--- a/gas/testsuite/gas/mips/branch-misc-2pic.l
+++ /dev/null
@@ -1,10 +0,0 @@
-.*: Assembler messages:
-.*:21: Warning: Pretending global symbol used as branch target is local.
-.*:22: Warning: Pretending global symbol used as branch target is local.
-.*:23: Warning: Pretending global symbol used as branch target is local.
-.*:24: Warning: Pretending global symbol used as branch target is local.
-.*:25: Warning: Pretending global symbol used as branch target is local.
-.*:26: Warning: Pretending global symbol used as branch target is local.
-.*:35: Error: Cannot branch to undefined symbol.
-.*:36: Error: Cannot branch to undefined symbol.
-.*:37: Error: Cannot branch to symbol in another section.
diff --git a/gas/testsuite/gas/mips/branch-misc-2pic.s b/gas/testsuite/gas/mips/branch-misc-2pic.s
deleted file mode 100644
index 31672893686d..000000000000
--- a/gas/testsuite/gas/mips/branch-misc-2pic.s
+++ /dev/null
@@ -1,43 +0,0 @@
-# Source file used to test the backward branches to globals in this file.
-
-	.globl g1 .text
-	.globl g2 .text
-	.globl g3 .text
-	.globl g4 .text
-	.globl g5 .text
-	.globl g6 .text
-
-	.globl x1 .text
-
-	.text
-g1:
-	.space 20
-g2:
-	.space 20
-g3:
-	.space 20
-
-x:
-	bal	g1
-	bal	g2
-	bal	g3
-	bal	g4
-	bal	g5
-	bal	g6
-
-	.space 20
-g4:
-	.space 20
-g5:
-	.space 20
-g6:
-
-	b	x1
-	b	x2
-	b	.Ldata
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-	.space	8
-
-	.data
-.Ldata:
diff --git a/gas/testsuite/gas/mips/branch-misc-3.d b/gas/testsuite/gas/mips/branch-misc-3.d
new file mode 100644
index 000000000000..754ed20e7b53
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-3.d
@@ -0,0 +1,59 @@
+#as: -march=mips1 -32
+#objdump: -dz
+#name: MIPS coprocessor branches
+
+.*file format .*
+
+Disassembly .*:
+
+0+00 <.*>:
+.*	ctc1	a0,\$31
+.*	b	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	nop
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	b	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	nop
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	addiu	a2,a2,1
+.*	bc1t	.*
+.*	nop
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	addiu	a1,a1,1
+.*	bc1t	.*
+.*	nop
+#
+.*	ctc1	a0,\$31
+.*	addiu	a1,a1,1
+.*	addiu	a2,a2,1
+.*	bc1t	.*
+.*	addiu	a3,a3,1
+#
+.*	c\.eq\.s	\$f0,\$f2
+.*	addiu	a1,a1,1
+.*	bc1t	.*
+.*	addiu	a2,a2,1
+#
+.*	bc1t	.*
+.*	addiu	a3,a3,1
+#pass
diff --git a/gas/testsuite/gas/mips/branch-misc-3.s b/gas/testsuite/gas/mips/branch-misc-3.s
new file mode 100644
index 000000000000..7a025a7c0055
--- /dev/null
+++ b/gas/testsuite/gas/mips/branch-misc-3.s
@@ -0,0 +1,44 @@
+	# ctc1s and compares shouldn't appear in a branch delay slot.
+	ctc1	$4,$31
+	b	1f
+1:
+	ctc1	$4,$31
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	b	1f
+1:
+	c.eq.s	$f0,$f2
+	bc1t	1f
+1:
+
+	# The next three branches should have nop-filled slots.
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	bc1t	1f
+1:
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	addiu	$5,$5,1
+	bc1t	1f
+1:
+
+	# ...but a swap is possible in these three.
+	ctc1	$4,$31
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	addiu	$7,$7,1
+	bc1t	1f
+1:
+	c.eq.s	$f0,$f2
+	addiu	$5,$5,1
+	addiu	$6,$6,1
+	bc1t	1f
+1:
+	addiu	$7,$7,1
+	bc1t	1f
+1:
diff --git a/gas/testsuite/gas/mips/branch-swap.d b/gas/testsuite/gas/mips/branch-swap.d
index 74c149d2cb17..273dee99f267 100644
--- a/gas/testsuite/gas/mips/branch-swap.d
+++ b/gas/testsuite/gas/mips/branch-swap.d
@@ -1,4 +1,4 @@
-#as: -march=mips2
+#as: -march=mips2 -32
 #objdump: -dr
 #name: MIPS branch-swap
 
diff --git a/gas/testsuite/gas/mips/elempic.d b/gas/testsuite/gas/mips/elempic.d
deleted file mode 100644
index abb89425ff79..000000000000
--- a/gas/testsuite/gas/mips/elempic.d
+++ /dev/null
@@ -1,154 +0,0 @@
-#objdump: -rst -mmips:4000
-#name: MIPS empic
-#as: -mabi=o64 -membedded-pic -mips3
-#source: empic.s
-#stderr: empic.l
-
-# Check GNU-specific embedded relocs, for ELF.
-
-.*: +file format elf.*mips.*
-
-SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 (|\.text)
-0+0000000 l    d  \.data	0+0000000 (|\.data)
-0+0000000 l    d  \.bss	0+0000000 (|\.bss)
-0+0000000 l    d  \.foo	0+0000000 (|\.foo)
-0+0000000 l    d  \.reginfo	0+0000000 (|\.reginfo)
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (|\.mdebug|\.pdr)
-0+0000004 l       \.text	0+0000000 l2
-0+0000000         \*UND\*	0+0000000 g1
-0+0000000         \*UND\*	0+0000000 g2
-0+0000100 l       \.foo	0+0000000 l1
-0+0000034 l       \.text	0+0000000 l3
-0+0000098 l       \.text	0+0000000 l5
-0+0000004 l       \.foo	0+0000000 l4
-
-
-RELOCATION RECORDS FOR \[\.text\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL16_S2  g1
-0+000000c R_MIPS_GNU_REL16_S2  g2
-0+0000014 R_MIPS_GNU_REL16_S2  g2
-0+000001c R_MIPS_GNU_REL16_S2  \.foo
-0+0000024 R_MIPS_GNU_REL16_S2  \.text
-0+000002c R_MIPS_GNU_REL16_S2  \.foo
-0+0000034 R_MIPS_GNU_REL16_S2  \.text
-0+000003c R_MIPS_GNU_REL_HI16  g1
-0+0000040 R_MIPS_GNU_REL_LO16  g1
-0+0000044 R_MIPS_GNU_REL_HI16  \.foo
-0+0000048 R_MIPS_GNU_REL_LO16  \.foo
-0+0000050 R_MIPS_32         g1
-0+0000054 R_MIPS_32         \.foo
-0+0000058 R_MIPS_32         \.text
-0+000005c R_MIPS_PC32       g1
-0+0000060 R_MIPS_PC32       \.foo
-0+0000068 R_MIPS_64         g1
-0+0000070 R_MIPS_64         \.foo
-0+0000078 R_MIPS_64         \.text
-0+0000080 R_MIPS_PC64       g1
-0+0000088 R_MIPS_PC64       \.foo
-0+0000098 R_MIPS_GNU_REL16_S2  \.text
-0+000009c R_MIPS_GNU_REL16_S2  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  \.text
-0+00000a4 R_MIPS_GNU_REL_LO16  \.text
-0+00000a8 R_MIPS_GNU_REL_HI16  \.text
-0+00000ac R_MIPS_GNU_REL_LO16  \.text
-0+00000b0 R_MIPS_32         \.text
-0+00000b8 R_MIPS_64         \.text
-0+00000cc R_MIPS_GNU_REL16_S2  \.text
-0+00000d0 R_MIPS_GNU_REL16_S2  \.text
-0+00000d4 R_MIPS_GNU_REL_HI16  \.text
-0+00000d8 R_MIPS_GNU_REL_LO16  \.text
-0+00000dc R_MIPS_GNU_REL_HI16  \.text
-0+00000e0 R_MIPS_GNU_REL_LO16  \.text
-0+00000e4 R_MIPS_32         \.text
-0+00000f0 R_MIPS_64         \.text
-
-
-RELOCATION RECORDS FOR \[\.foo\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL_HI16  g1
-0+0000008 R_MIPS_GNU_REL_LO16  g1
-0+000000c R_MIPS_GNU_REL_HI16  \.foo
-0+0000010 R_MIPS_GNU_REL_LO16  \.foo
-0+0000014 R_MIPS_GNU_REL_HI16  \.text
-0+0000018 R_MIPS_GNU_REL_LO16  \.text
-0+000001c R_MIPS_GNU_REL_HI16  g1
-0+0000020 R_MIPS_GNU_REL_LO16  g1
-0+0000024 R_MIPS_GNU_REL_HI16  g1
-0+0000028 R_MIPS_GNU_REL_LO16  g1
-0+000002c R_MIPS_GNU_REL_HI16  \.foo
-0+0000030 R_MIPS_GNU_REL_LO16  \.foo
-0+0000034 R_MIPS_GNU_REL_HI16  \.text
-0+0000038 R_MIPS_GNU_REL_LO16  \.text
-0+000003c R_MIPS_32         g1
-0+0000040 R_MIPS_32         \.foo
-0+0000044 R_MIPS_32         \.text
-0+0000048 R_MIPS_PC32       g1
-0+0000050 R_MIPS_PC32       \.text
-0+0000058 R_MIPS_64         g1
-0+0000060 R_MIPS_64         \.foo
-0+0000068 R_MIPS_64         \.text
-0+0000070 R_MIPS_PC64       g1
-0+0000080 R_MIPS_PC64       \.text
-0+0000088 R_MIPS_GNU_REL_HI16  g1
-0+000008c R_MIPS_GNU_REL_LO16  g1
-0+0000090 R_MIPS_GNU_REL_HI16  \.foo
-0+0000094 R_MIPS_GNU_REL_LO16  \.foo
-0+0000098 R_MIPS_GNU_REL_HI16  \.text
-0+000009c R_MIPS_GNU_REL_LO16  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  g1
-0+00000a4 R_MIPS_GNU_REL_LO16  g1
-0+00000a8 R_MIPS_GNU_REL_HI16  \.foo
-0+00000ac R_MIPS_GNU_REL_LO16  \.foo
-0+00000b0 R_MIPS_GNU_REL_HI16  \.text
-0+00000b4 R_MIPS_GNU_REL_LO16  \.text
-0+00000b8 R_MIPS_32         g1
-0+00000bc R_MIPS_32         \.foo
-0+00000c0 R_MIPS_32         \.text
-0+00000c4 R_MIPS_PC32       g1
-0+00000cc R_MIPS_PC32       \.text
-0+00000d0 R_MIPS_64         g1
-0+00000d8 R_MIPS_64         \.foo
-0+00000e0 R_MIPS_64         \.text
-0+00000e8 R_MIPS_PC64       g1
-0+00000f8 R_MIPS_PC64       \.text
-
-Contents of section \.text:
- 0000 00000000 ffff1104 00000000 ffff0010  .*
- 0010 00000000 ffff0010 00000000 3f001104  .*
- 0020 00000000 00001104 00000000 41000010  .*
- 0030 00000000 00000010 00000000 0000033c  .*
- 0040 0c0063[26]4 0000033c 140163[26]4 d0ff03[26]4  .*
- 0050 00000000 00010000 04000000 28000000  .*
- 0060 2c010000 d0ffffff 00000000 00000000  .*
- 0070 00010000 00000000 04000000 00000000  .*
- 0080 4c000000 00000000 54010000 00000000  .*
- 0090 d0ffffff ffffffff 32000010 33000010  .*
- 00a0 0000033c d80063[26]4 0000033c e80063[26]4  .*
- 00b0 cc000000 34000000 cc000000 00000000  .*
- 00c0 34000000 00000000 00000000 32000010  .*
- 00d0 33000010 0000033c 0c0163[26]4 0000033c  .*
- 00e0 1c0163[26]4 cc000000 34000000 00000000  .*
- 00f0 cc000000 00000000 34000000 00000000  .*
-Contents of section \.reginfo:
- 0000 08000080 00000000 00000000 00000000  .*
- 0010 00000000 00000000                    .*
-Contents of section \.foo:
- 0000 00000000 0000033c 040063[26]4 0000033c  .*
- 0010 0c0163[26]4 0000033c 180063[26]4 0000033c  .*
- 0020 1c0063[26]4 0000033c 240063[26]4 0000033c  .*
- 0030 2c0163[26]4 0000033c 380063[26]4 00000000  .*
- 0040 00010000 04000000 44000000 fc000000  .*
- 0050 50000000 00000000 00000000 00000000  .*
- 0060 00010000 00000000 04000000 00000000  .*
- 0070 6c000000 00000000 fc000000 00000000  .*
- 0080 80000000 00000000 0000033c 8c0063[26]4  .*
- 0090 0000033c 940163[26]4 0000033c a00063[26]4  .*
- 00a0 0000033c a40063[26]4 0000033c ac0163[26]4  .*
- 00b0 0000033c b80063[26]4 04000000 04010000  .*
- 00c0 08000000 c4000000 00010000 d0000000  .*
- 00d0 04000000 00000000 04010000 00000000  .*
- 00e0 08000000 00000000 e8000000 00000000  .*
- 00f0 00010000 00000000 fc000000 00000000  .*
- 0100 00000000 00000000 00000000 00000000  .*
diff --git a/gas/testsuite/gas/mips/elf-rel.d b/gas/testsuite/gas/mips/elf-rel.d
index ebc30a029386..d6cee3c1b197 100644
--- a/gas/testsuite/gas/mips/elf-rel.d
+++ b/gas/testsuite/gas/mips/elf-rel.d
@@ -22,27 +22,27 @@ OFFSET [ ]+ TYPE              VALUE
 0+000002c R_MIPS_LO16       \.text
 0+0000030 R_MIPS_HI16       \.text
 0+0000048 R_MIPS_LO16       \.text
-0+0000064 R_MIPS_HI16       \.text
+0+0000034 R_MIPS_HI16       \.text
 0+000004c R_MIPS_LO16       \.text
-0+0000068 R_MIPS_HI16       \.text
+0+0000038 R_MIPS_HI16       \.text
 0+0000050 R_MIPS_LO16       \.text
-0+000006c R_MIPS_HI16       \.text
+0+000003c R_MIPS_HI16       \.text
 0+0000054 R_MIPS_LO16       \.text
-0+0000074 R_MIPS_HI16       \.text
+0+0000044 R_MIPS_HI16       \.text
 0+0000058 R_MIPS_LO16       \.text
-0+0000070 R_MIPS_HI16       \.text
+0+0000040 R_MIPS_HI16       \.text
 0+000005c R_MIPS_LO16       \.text
 0+0000060 R_MIPS_HI16       \.text
 0+0000078 R_MIPS_LO16       \.text
-0+0000034 R_MIPS_HI16       \.text
+0+0000064 R_MIPS_HI16       \.text
 0+000007c R_MIPS_LO16       \.text
-0+0000038 R_MIPS_HI16       \.text
+0+0000068 R_MIPS_HI16       \.text
 0+0000080 R_MIPS_LO16       \.text
-0+000003c R_MIPS_HI16       \.text
+0+000006c R_MIPS_HI16       \.text
 0+0000084 R_MIPS_LO16       \.text
-0+0000044 R_MIPS_HI16       \.text
+0+0000074 R_MIPS_HI16       \.text
 0+0000088 R_MIPS_LO16       \.text
-0+0000040 R_MIPS_HI16       \.text
+0+0000070 R_MIPS_HI16       \.text
 0+000008c R_MIPS_LO16       \.text
 
 
diff --git a/gas/testsuite/gas/mips/elf-rel10.d b/gas/testsuite/gas/mips/elf-rel10.d
index eb12f13689e8..8fd3b79273c9 100644
--- a/gas/testsuite/gas/mips/elf-rel10.d
+++ b/gas/testsuite/gas/mips/elf-rel10.d
@@ -24,6 +24,6 @@ Relocation section '\.rela\.text' at offset .* contains 22 entries:
 0+002c * 0+..15 * R_MIPS_GOT_OFST * 0+0000 * \.text \+ c
 0+0030 * 0+..14 * R_MIPS_GOT_PAGE * 0+0000 * \.text \+ 33221d
 0+0034 * 0+..15 * R_MIPS_GOT_OFST * 0+0000 * \.text \+ 33221d
-0+0038 * 0+..14 * R_MIPS_GOT_PAGE * 0+0000 * frob \+ 0
-0+003c * 0+..15 * R_MIPS_GOT_OFST * 0+0000 * frob \+ 0
+0+0038 * 0+..14 * R_MIPS_GOT_PAGE * 0+0000 * \.text \+ 18
+0+003c * 0+..15 * R_MIPS_GOT_OFST * 0+0000 * \.text \+ 18
 #pass
diff --git a/gas/testsuite/gas/mips/elf-rel10.s b/gas/testsuite/gas/mips/elf-rel10.s
index cda73de6c43b..c9affaf8dc3c 100644
--- a/gas/testsuite/gas/mips/elf-rel10.s
+++ b/gas/testsuite/gas/mips/elf-rel10.s
@@ -14,6 +14,7 @@ bar:
 	.end	bar
 
 	.ent	frob
+frob:	
 	lw	$4,%got_page(foo)($gp)
 	addiu	$4,$4,%got_ofst(foo)
 
diff --git a/gas/testsuite/gas/mips/elf-rel11.d b/gas/testsuite/gas/mips/elf-rel11.d
index 408795dad093..f776a8ed433f 100644
--- a/gas/testsuite/gas/mips/elf-rel11.d
+++ b/gas/testsuite/gas/mips/elf-rel11.d
@@ -7,10 +7,10 @@ Relocation section '\.rela\.text' at offset .* contains 12 entries:
 0+0000 * 0+..0000001d * R_MIPS_HIGHEST * 0+0000 * bar \+ 0
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
-0+0008 * 0+..0000001c * R_MIPS_HIGHER * 0+0000 * bar \+ 0
+0+0004 * 0+..00000005 * R_MIPS_HI16 * 0+0000 * bar \+ 0
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
-0+0004 * 0+..00000005 * R_MIPS_HI16 * 0+0000 * bar \+ 0
+0+0008 * 0+..0000001c * R_MIPS_HIGHER * 0+0000 * bar \+ 0
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
 0+000c * 0+..00000006 * R_MIPS_LO16 * 0+0000 * bar \+ 0
@@ -19,10 +19,10 @@ Relocation section '\.rela\.text' at offset .* contains 12 entries:
 0+0018 * 0+..0000001d * R_MIPS_HIGHEST * 0+0000 * bar \+ 12345678
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
-0+0020 * 0+..0000001c * R_MIPS_HIGHER * 0+0000 * bar \+ 12345678
+0+001c * 0+..00000005 * R_MIPS_HI16 * 0+0000 * bar \+ 12345678
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
-0+001c * 0+..00000005 * R_MIPS_HI16 * 0+0000 * bar \+ 12345678
+0+0020 * 0+..0000001c * R_MIPS_HIGHER * 0+0000 * bar \+ 12345678
  * Type2: R_MIPS_NONE *
  * Type3: R_MIPS_NONE *
 0+0024 * 0+..00000006 * R_MIPS_LO16 * 0+0000 * bar \+ 12345678
diff --git a/gas/testsuite/gas/mips/elf-rel19.d b/gas/testsuite/gas/mips/elf-rel19.d
index e80aa61c7075..30bbc941e3fe 100644
--- a/gas/testsuite/gas/mips/elf-rel19.d
+++ b/gas/testsuite/gas/mips/elf-rel19.d
@@ -1,5 +1,5 @@
 #objdump: -dr
-#as: -mabi=32 -KPIC
+#as: -mabi=32 -march=mips1 -KPIC
 
 .*:     file format .*
 
@@ -10,10 +10,10 @@ Disassembly of section \.text:
 # Relocation agsinst .rodata.str1.1
 #
 .*:	8f840000 	lw	a0,0\(gp\)
-			.*: R_MIPS_GOT16	\.rodata\.str1\.1
+			.*: R_MIPS_GOT16	L2
 .*:	00000000 	nop
-.*:	24840004 	addiu	a0,a0,4
-			.*: R_MIPS_LO16	\.rodata\.str1\.1
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	L2
 #
 # Relocation agsinst L2 + 2
 #
diff --git a/gas/testsuite/gas/mips/elf-rel20.d b/gas/testsuite/gas/mips/elf-rel20.d
new file mode 100644
index 000000000000..81129e3b9ff3
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel20.d
@@ -0,0 +1,15 @@
+#as: -march=mips2 -mabi=32 -KPIC
+#readelf: --relocs
+#name: MIPS ELF reloc 20
+
+Relocation section '\.rel\.text' at offset .* contains 8 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name
+0+0000 * 0+..05 * R_MIPS_HI16 * 0+0000 * foo
+0+0010 * 0+..06 * R_MIPS_LO16 * 0+0000 * foo
+0+0004 * 0+..05 * R_MIPS_HI16 * 0+0000 * foo
+0+0014 * 0+..06 * R_MIPS_LO16 * 0+0000 * foo
+0+000c * 0+..05 * R_MIPS_HI16 * 0+0000 * \.bss
+0+0018 * 0+..06 * R_MIPS_LO16 * 0+0000 * \.bss
+0+0008 * 0+..05 * R_MIPS_HI16 * 0+0000 * \.bss
+0+001c * 0+..06 * R_MIPS_LO16 * 0+0000 * \.bss
+#pass
diff --git a/gas/testsuite/gas/mips/elf-rel20.s b/gas/testsuite/gas/mips/elf-rel20.s
new file mode 100644
index 000000000000..799156d73adf
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel20.s
@@ -0,0 +1,11 @@
+	lui	$4,%hi(foo)
+	lui	$5,%hi(foo + 0x80000)
+	lui	$7,%hi(bar + 0x80000)
+	lui	$6,%hi(bar)
+	addiu	$4,$4,%lo(foo + 2)
+	addiu	$5,$5,%lo(foo + 0x80004)
+	addiu	$6,$6,%lo(bar + 2)
+	addiu	$7,$7,%lo(bar + 0x80004)
+	.section .bss
+bar:
+	.space	0x80010
diff --git a/gas/testsuite/gas/mips/elf-rel21.d b/gas/testsuite/gas/mips/elf-rel21.d
new file mode 100644
index 000000000000..31e4d2341218
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel21.d
@@ -0,0 +1,9 @@
+#as: -march=mips3 -mabi=64
+#readelf: --relocs
+#name: MIPS ELF reloc 21
+
+Relocation section '\.rela\.data' .*:
+.*
+.* R_MIPS_GPREL32 * 0+00 * \.data \+ c
+ * Type2: R_MIPS_NONE *
+ * Type3: R_MIPS_NONE *
diff --git a/gas/testsuite/gas/mips/elf-rel21.s b/gas/testsuite/gas/mips/elf-rel21.s
new file mode 100644
index 000000000000..b614b17c6b6c
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel21.s
@@ -0,0 +1,7 @@
+	.abicalls
+	.data
+	.gpword	foo
+	.8byte	bar - foo
+foo:
+	.word	0
+bar:
diff --git a/gas/testsuite/gas/mips/elf-rel22.d b/gas/testsuite/gas/mips/elf-rel22.d
new file mode 100644
index 000000000000..14ab1a8b5bd6
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel22.d
@@ -0,0 +1,9 @@
+#as: -march=mips3 -mabi=64
+#readelf: --relocs
+#name: MIPS ELF reloc 22
+
+Relocation section '\.rela\.text' .*:
+.*
+.* R_MIPS_LO16 * 0+04
+ * Type2: R_MIPS_SUB *
+ * Type3: R_MIPS_LO16 *
diff --git a/gas/testsuite/gas/mips/elf-rel22.s b/gas/testsuite/gas/mips/elf-rel22.s
new file mode 100644
index 000000000000..82a1cac04ac7
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel22.s
@@ -0,0 +1,4 @@
+	lui	$4,%lo(%neg(%lo(bar-foo)))
+foo:
+	nop
+bar:
diff --git a/gas/testsuite/gas/mips/elf-rel23.d b/gas/testsuite/gas/mips/elf-rel23.d
new file mode 100644
index 000000000000..66697821de45
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel23.d
@@ -0,0 +1,19 @@
+#as: -march=mips3 -mabi=64
+#objdump: -dr -Mgpr-names=numeric
+#name: MIPS ELF reloc 23
+
+.*: * file format elf64.*mips.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+.*:	0380282d 	move	\$5,\$28
+.*:	3c1c0000 	lui	\$28,0x0
+			.*: R_MIPS_GPREL16	foo
+			.*: R_MIPS_SUB	\*ABS\*
+			.*: R_MIPS_HI16	\*ABS\*
+.*:	279c0000 	addiu	\$28,\$28,0
+			.*: R_MIPS_GPREL16	foo
+			.*: R_MIPS_SUB	\*ABS\*
+			.*: R_MIPS_LO16	\*ABS\*
+.*:	0384e02d 	daddu	\$28,\$28,\$4
diff --git a/gas/testsuite/gas/mips/elf-rel23.s b/gas/testsuite/gas/mips/elf-rel23.s
new file mode 100644
index 000000000000..97f9b3dd8821
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel23.s
@@ -0,0 +1,6 @@
+	.abicalls
+	.globl	foo
+	.ent	foo
+foo:
+	.cpsetup $4,$5,foo
+	.end	foo
diff --git a/gas/testsuite/gas/mips/elf-rel23a.d b/gas/testsuite/gas/mips/elf-rel23a.d
new file mode 100644
index 000000000000..5b252ac78183
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel23a.d
@@ -0,0 +1,20 @@
+#source: elf-rel23.s
+#as: -march=mips3 -mabi=64 -mno-shared
+#objdump: -dr -Mgpr-names=numeric
+#name: MIPS ELF reloc 23 -mabi=64 -mno-shared
+
+.*: * file format elf64-.*mips.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+.*:	0380282d 	move	\$5,\$28
+.*:	3c1c0000 	lui	\$28,0x0
+			.*: R_MIPS_GPREL16	foo
+			.*: R_MIPS_SUB	\*ABS\*
+			.*: R_MIPS_HI16	\*ABS\*
+.*:	279c0000 	addiu	\$28,\$28,0
+			.*: R_MIPS_GPREL16	foo
+			.*: R_MIPS_SUB	\*ABS\*
+			.*: R_MIPS_LO16	\*ABS\*
+.*:	0384e02d 	daddu	\$28,\$28,\$4
diff --git a/gas/testsuite/gas/mips/elf-rel23b.d b/gas/testsuite/gas/mips/elf-rel23b.d
new file mode 100644
index 000000000000..7c02f15f5464
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel23b.d
@@ -0,0 +1,16 @@
+#source: elf-rel23.s
+#as: -march=mips3 -mabi=n32 -mno-shared
+#objdump: -dr -Mgpr-names=numeric
+#name: MIPS ELF reloc 23 -mabi=n32 -mno-shared
+
+.*: * file format elf.*mips.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+.*:	0380282d 	move	\$5,\$28
+.*:	3c1c0000 	lui	\$28,0x0
+			.*: R_MIPS_HI16	__gnu_local_gp
+.*:	279c0000 	addiu	\$28,\$28,0
+			.*: R_MIPS_LO16	__gnu_local_gp
+.*:	00000000 	nop
diff --git a/gas/testsuite/gas/mips/elf-rel24.d b/gas/testsuite/gas/mips/elf-rel24.d
new file mode 100644
index 000000000000..db12710e5047
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel24.d
@@ -0,0 +1,12 @@
+#as: -march=mips3 -mabi=64
+#readelf: --relocs
+#name: MIPS ELF reloc 24
+
+Relocation section '\.rela\.text' .*:
+.*
+.* R_MIPS_GPREL32 * 0+00 foo \+ 0
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
+.* R_MIPS_GPREL32 * 0+00 \.text \+ 10
+ * Type2: R_MIPS_64 *
+ * Type3: R_MIPS_NONE *
diff --git a/gas/testsuite/gas/mips/elf-rel24.s b/gas/testsuite/gas/mips/elf-rel24.s
new file mode 100644
index 000000000000..bc96c12df4a6
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel24.s
@@ -0,0 +1,4 @@
+	.abicalls
+	.gpdword	foo
+	.gpdword	bar
+bar:
diff --git a/gas/testsuite/gas/mips/elf-rel25.d b/gas/testsuite/gas/mips/elf-rel25.d
new file mode 100644
index 000000000000..18c48b6b8d8e
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel25.d
@@ -0,0 +1,15 @@
+#as: -march=mips1 -mabi=32
+#objdump: -dr -Mgpr-names=numeric
+#name: MIPS ELF reloc 25
+
+.*: * file format elf.*mips.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+.*:	3c1c0000 	lui	\$28,0x0
+			.*: R_MIPS_HI16	_gp_disp
+.*:	279c0000 	addiu	\$28,\$28,0
+			.*: R_MIPS_LO16	_gp_disp
+.*:	0399e021 	addu	\$28,\$28,\$25
+#pass
diff --git a/gas/testsuite/gas/mips/elf-rel25.s b/gas/testsuite/gas/mips/elf-rel25.s
new file mode 100644
index 000000000000..bfdd37739ab7
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel25.s
@@ -0,0 +1,8 @@
+	.abicalls
+	.globl	foo
+	.ent	foo
+foo:
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	.end	foo
diff --git a/gas/testsuite/gas/mips/elf-rel25a.d b/gas/testsuite/gas/mips/elf-rel25a.d
new file mode 100644
index 000000000000..a7d30a5b2301
--- /dev/null
+++ b/gas/testsuite/gas/mips/elf-rel25a.d
@@ -0,0 +1,15 @@
+#source: elf-rel25.s
+#as: -march=mips1 -mabi=32 -mno-shared
+#objdump: -dr -Mgpr-names=numeric
+#name: MIPS ELF reloc 25 -mno-shared
+
+.*: * file format elf.*mips.*
+
+Disassembly of section \.text:
+
+0+00 <.*>:
+.*:	3c1c0000 	lui	\$28,0x0
+			.*: R_MIPS_HI16	__gnu_local_gp
+.*:	279c0000 	addiu	\$28,\$28,0
+			.*: R_MIPS_LO16	__gnu_local_gp
+#pass
diff --git a/gas/testsuite/gas/mips/elf-rel7.d b/gas/testsuite/gas/mips/elf-rel7.d
index 58d0cff2f68c..48464c2f9b2a 100644
--- a/gas/testsuite/gas/mips/elf-rel7.d
+++ b/gas/testsuite/gas/mips/elf-rel7.d
@@ -6,9 +6,9 @@
 
 Disassembly of section \.text:
 0+00 <.*> lui	a0,0x0
-			0: R_MIPS_HI16	.barsec
-0+04 <.*> lw	a0,8\(a0\)
-			4: R_MIPS_LO16	.barsec
+			0: R_MIPS_HI16	bar
+0+04 <.*> lw	a0,0\(a0\)
+			4: R_MIPS_LO16	bar
 0+08 <.*> lui	a0,0x0
 			8: R_MIPS_HI16	bar
 0+0c <.*> lw	a0,4\(a0\)
diff --git a/gas/testsuite/gas/mips/elf-rel9.d b/gas/testsuite/gas/mips/elf-rel9.d
index c78a4bf86bae..1f7f1be010cf 100644
--- a/gas/testsuite/gas/mips/elf-rel9.d
+++ b/gas/testsuite/gas/mips/elf-rel9.d
@@ -45,7 +45,7 @@ Disassembly of section \.text:
 			44: R_MIPS_LO16	\.data
   48:	8f840002 	lw	\$4,2\(\$28\)
 			48: R_MIPS_GOT16	\.data
-  4c:	2484f100 	addiu	\$4,\$4,-3840
+  4c:	24840000 	addiu	\$4,\$4,0
 			4c: R_MIPS_LO16	\.data
   50:	8f840003 	lw	\$4,3\(\$28\)
 			50: R_MIPS_GOT16	\.data
diff --git a/gas/testsuite/gas/mips/elf-rel9.s b/gas/testsuite/gas/mips/elf-rel9.s
index 4768c2453363..b08cc12b4c64 100644
--- a/gas/testsuite/gas/mips/elf-rel9.s
+++ b/gas/testsuite/gas/mips/elf-rel9.s
@@ -28,7 +28,7 @@ foo:
 	addiu	$4,$4,%lo(l2 + 0xfff)
 
 	lw	$4,%got(l2 + 0x1000)($28)
-	addiu	$4,$4,%lo(l2 + 0x100)
+	addiu	$4,$4,%lo(l2 + 0x1000)
 
 	lw	$4,%got(l2 + 0x12345)($28)
 	addiu	$4,$4,%lo(l2 + 0x12345)
diff --git a/gas/testsuite/gas/mips/elfel-rel.d b/gas/testsuite/gas/mips/elfel-rel.d
index c9671f555ef5..a597212e0c43 100644
--- a/gas/testsuite/gas/mips/elfel-rel.d
+++ b/gas/testsuite/gas/mips/elfel-rel.d
@@ -23,27 +23,27 @@ OFFSET [ ]+ TYPE              VALUE
 0+000002c R_MIPS_LO16       \.text
 0+0000030 R_MIPS_HI16       \.text
 0+0000048 R_MIPS_LO16       \.text
-0+0000064 R_MIPS_HI16       \.text
+0+0000034 R_MIPS_HI16       \.text
 0+000004c R_MIPS_LO16       \.text
-0+0000068 R_MIPS_HI16       \.text
+0+0000038 R_MIPS_HI16       \.text
 0+0000050 R_MIPS_LO16       \.text
-0+000006c R_MIPS_HI16       \.text
+0+000003c R_MIPS_HI16       \.text
 0+0000054 R_MIPS_LO16       \.text
-0+0000074 R_MIPS_HI16       \.text
+0+0000044 R_MIPS_HI16       \.text
 0+0000058 R_MIPS_LO16       \.text
-0+0000070 R_MIPS_HI16       \.text
+0+0000040 R_MIPS_HI16       \.text
 0+000005c R_MIPS_LO16       \.text
 0+0000060 R_MIPS_HI16       \.text
 0+0000078 R_MIPS_LO16       \.text
-0+0000034 R_MIPS_HI16       \.text
+0+0000064 R_MIPS_HI16       \.text
 0+000007c R_MIPS_LO16       \.text
-0+0000038 R_MIPS_HI16       \.text
+0+0000068 R_MIPS_HI16       \.text
 0+0000080 R_MIPS_LO16       \.text
-0+000003c R_MIPS_HI16       \.text
+0+000006c R_MIPS_HI16       \.text
 0+0000084 R_MIPS_LO16       \.text
-0+0000044 R_MIPS_HI16       \.text
+0+0000074 R_MIPS_HI16       \.text
 0+0000088 R_MIPS_LO16       \.text
-0+0000040 R_MIPS_HI16       \.text
+0+0000070 R_MIPS_HI16       \.text
 0+000008c R_MIPS_LO16       \.text
 
 
diff --git a/gas/testsuite/gas/mips/empic.d b/gas/testsuite/gas/mips/empic.d
deleted file mode 100644
index b18d1ddf2b6b..000000000000
--- a/gas/testsuite/gas/mips/empic.d
+++ /dev/null
@@ -1,154 +0,0 @@
-#objdump: -rst -mmips:4000
-#name: MIPS empic
-#as: -mabi=o64 -membedded-pic -mips3
-#stderr: empic.l
-
-# Check GNU-specific embedded relocs, for ELF.
-
-.*: +file format elf.*mips.*
-
-SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 (|\.text)
-0+0000000 l    d  \.data	0+0000000 (|\.data)
-0+0000000 l    d  \.bss	0+0000000 (|\.bss)
-0+0000000 l    d  \.foo	0+0000000 (|\.foo)
-0+0000000 l    d  \.reginfo	0+0000000 (|\.reginfo)
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (|\.mdebug|\.pdr)
-0+0000004 l       \.text	0+0000000 l2
-0+0000000         \*UND\*	0+0000000 g1
-0+0000000         \*UND\*	0+0000000 g2
-0+0000100 l       \.foo	0+0000000 l1
-0+0000034 l       \.text	0+0000000 l3
-0+0000098 l       \.text	0+0000000 l5
-0+0000004 l       \.foo	0+0000000 l4
-
-
-RELOCATION RECORDS FOR \[\.text\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL16_S2  g1
-0+000000c R_MIPS_GNU_REL16_S2  g2
-0+0000014 R_MIPS_GNU_REL16_S2  g2
-0+000001c R_MIPS_GNU_REL16_S2  \.foo
-0+0000024 R_MIPS_GNU_REL16_S2  \.text
-0+000002c R_MIPS_GNU_REL16_S2  \.foo
-0+0000034 R_MIPS_GNU_REL16_S2  \.text
-0+000003c R_MIPS_GNU_REL_HI16  g1
-0+0000040 R_MIPS_GNU_REL_LO16  g1
-0+0000044 R_MIPS_GNU_REL_HI16  \.foo
-0+0000048 R_MIPS_GNU_REL_LO16  \.foo
-0+0000050 R_MIPS_32         g1
-0+0000054 R_MIPS_32         \.foo
-0+0000058 R_MIPS_32         \.text
-0+000005c R_MIPS_PC32       g1
-0+0000060 R_MIPS_PC32       \.foo
-0+0000068 R_MIPS_64         g1
-0+0000070 R_MIPS_64         \.foo
-0+0000078 R_MIPS_64         \.text
-0+0000080 R_MIPS_PC64       g1
-0+0000088 R_MIPS_PC64       \.foo
-0+0000098 R_MIPS_GNU_REL16_S2  \.text
-0+000009c R_MIPS_GNU_REL16_S2  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  \.text
-0+00000a4 R_MIPS_GNU_REL_LO16  \.text
-0+00000a8 R_MIPS_GNU_REL_HI16  \.text
-0+00000ac R_MIPS_GNU_REL_LO16  \.text
-0+00000b0 R_MIPS_32         \.text
-0+00000b8 R_MIPS_64         \.text
-0+00000cc R_MIPS_GNU_REL16_S2  \.text
-0+00000d0 R_MIPS_GNU_REL16_S2  \.text
-0+00000d4 R_MIPS_GNU_REL_HI16  \.text
-0+00000d8 R_MIPS_GNU_REL_LO16  \.text
-0+00000dc R_MIPS_GNU_REL_HI16  \.text
-0+00000e0 R_MIPS_GNU_REL_LO16  \.text
-0+00000e4 R_MIPS_32         \.text
-0+00000f0 R_MIPS_64         \.text
-
-
-RELOCATION RECORDS FOR \[\.foo\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL_HI16  g1
-0+0000008 R_MIPS_GNU_REL_LO16  g1
-0+000000c R_MIPS_GNU_REL_HI16  \.foo
-0+0000010 R_MIPS_GNU_REL_LO16  \.foo
-0+0000014 R_MIPS_GNU_REL_HI16  \.text
-0+0000018 R_MIPS_GNU_REL_LO16  \.text
-0+000001c R_MIPS_GNU_REL_HI16  g1
-0+0000020 R_MIPS_GNU_REL_LO16  g1
-0+0000024 R_MIPS_GNU_REL_HI16  g1
-0+0000028 R_MIPS_GNU_REL_LO16  g1
-0+000002c R_MIPS_GNU_REL_HI16  \.foo
-0+0000030 R_MIPS_GNU_REL_LO16  \.foo
-0+0000034 R_MIPS_GNU_REL_HI16  \.text
-0+0000038 R_MIPS_GNU_REL_LO16  \.text
-0+000003c R_MIPS_32         g1
-0+0000040 R_MIPS_32         \.foo
-0+0000044 R_MIPS_32         \.text
-0+0000048 R_MIPS_PC32       g1
-0+0000050 R_MIPS_PC32       \.text
-0+0000058 R_MIPS_64         g1
-0+0000060 R_MIPS_64         \.foo
-0+0000068 R_MIPS_64         \.text
-0+0000070 R_MIPS_PC64       g1
-0+0000080 R_MIPS_PC64       \.text
-0+0000088 R_MIPS_GNU_REL_HI16  g1
-0+000008c R_MIPS_GNU_REL_LO16  g1
-0+0000090 R_MIPS_GNU_REL_HI16  \.foo
-0+0000094 R_MIPS_GNU_REL_LO16  \.foo
-0+0000098 R_MIPS_GNU_REL_HI16  \.text
-0+000009c R_MIPS_GNU_REL_LO16  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  g1
-0+00000a4 R_MIPS_GNU_REL_LO16  g1
-0+00000a8 R_MIPS_GNU_REL_HI16  \.foo
-0+00000ac R_MIPS_GNU_REL_LO16  \.foo
-0+00000b0 R_MIPS_GNU_REL_HI16  \.text
-0+00000b4 R_MIPS_GNU_REL_LO16  \.text
-0+00000b8 R_MIPS_32         g1
-0+00000bc R_MIPS_32         \.foo
-0+00000c0 R_MIPS_32         \.text
-0+00000c4 R_MIPS_PC32       g1
-0+00000cc R_MIPS_PC32       \.text
-0+00000d0 R_MIPS_64         g1
-0+00000d8 R_MIPS_64         \.foo
-0+00000e0 R_MIPS_64         \.text
-0+00000e8 R_MIPS_PC64       g1
-0+00000f8 R_MIPS_PC64       \.text
-
-Contents of section \.text:
- 0000 00000000 0411ffff 00000000 1000ffff  .*
- 0010 00000000 1000ffff 00000000 0411003f  .*
- 0020 00000000 04110000 00000000 10000041  .*
- 0030 00000000 10000000 00000000 3c030000  .*
- 0040 [26]463000c 3c030000 [26]4630114 [26]403ffd0  .*
- 0050 00000000 00000100 00000004 00000028  .*
- 0060 0000012c ffffffd0 00000000 00000000  .*
- 0070 00000000 00000100 00000000 00000004  .*
- 0080 00000000 0000004c 00000000 00000154  .*
- 0090 ffffffff ffffffd0 10000032 10000033  .*
- 00a0 3c030000 [26]46300d8 3c030000 [26]46300e8  .*
- 00b0 000000cc 00000034 00000000 000000cc  .*
- 00c0 00000000 00000034 00000000 10000032  .*
- 00d0 10000033 3c030000 [26]463010c 3c030000  .*
- 00e0 [26]463011c 000000cc 00000034 00000000  .*
- 00f0 00000000 000000cc 00000000 00000034  .*
-Contents of section \.reginfo:
- 0000 80000008 00000000 00000000 00000000  .*
- 0010 00000000 00000000                    .*
-Contents of section \.foo:
- 0000 00000000 3c030000 [26]4630004 3c030000  .*
- 0010 [26]463010c 3c030000 [26]4630018 3c030000  .*
- 0020 [26]463001c 3c030000 [26]4630024 3c030000  .*
- 0030 [26]463012c 3c030000 [26]4630038 00000000  .*
- 0040 00000100 00000004 00000044 000000fc  .*
- 0050 00000050 00000000 00000000 00000000  .*
- 0060 00000000 00000100 00000000 00000004  .*
- 0070 00000000 0000006c 00000000 000000fc  .*
- 0080 00000000 00000080 3c030000 [26]463008c  .*
- 0090 3c030000 [26]4630194 3c030000 [26]46300a0  .*
- 00a0 3c030000 [26]46300a4 3c030000 [26]46301ac  .*
- 00b0 3c030000 [26]46300b8 00000004 00000104  .*
- 00c0 00000008 000000c4 00000100 000000d0  .*
- 00d0 00000000 00000004 00000000 00000104  .*
- 00e0 00000000 00000008 00000000 000000e8  .*
- 00f0 00000000 00000100 00000000 000000fc  .*
- 0100 00000000 00000000 00000000 00000000  .*
-
diff --git a/gas/testsuite/gas/mips/empic.l b/gas/testsuite/gas/mips/empic.l
deleted file mode 100644
index e53d4f230e2a..000000000000
--- a/gas/testsuite/gas/mips/empic.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*:42: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
-.*:56: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
diff --git a/gas/testsuite/gas/mips/empic.s b/gas/testsuite/gas/mips/empic.s
deleted file mode 100644
index cfb4b94cda5b..000000000000
--- a/gas/testsuite/gas/mips/empic.s
+++ /dev/null
@@ -1,119 +0,0 @@
-# Check GNU-specific embedded relocs, for ELF.
-
-	.text
-	.set noreorder
-	nop
-l2:	jal	g1		# R_MIPS_GNU_REL16_S2	g1   -1
-	nop
-	b	g2		# R_MIPS_GNU_REL16_S2	g2   -1
-	nop
-	b	g2		# R_MIPS_GNU_REL16_S2	g2   -1
-	nop
-	jal	l1		# R_MIPS_GNU_REL16_S2	.foo 3F
-	nop
-	jal	l2		# R_MIPS_GNU_REL16_S2	.text 0  or -9
-	nop
-	b	l1+8		# R_MIPS_GNU_REL16_S2	.foo 41
-	nop
-l3:
-	b	l2		# R_MIPS_GNU_REL16_S2	.text 0  or -D
-	nop
-	la	$3,g1-l3	# R_MIPS_GNU_REL_HI16   g1   0
-				# R_MIPS_GNU_REL_LO16   g1   C
-	la	$3,l1-l3	# R_MIPS_GNU_REL_HI16   .foo 0
-				# R_MIPS_GNU_REL_LO16   .foo 114
-	la	$3,l2-l3	# -30
-	.word	g1		# R_MIPS_32	g1    0
-	.word	l1		# R_MIPS_32	.foo  100
-	.word	l2		# R_MIPS_32	.text 4
-	.word	g1-l3		# R_MIPS_PC32	g1    28
-	.word	l1-l3		# R_MIPS_PC32	.foo  12C
-	.word	l2-l3		# -30
-	.align 3
-	.dword	g1		# R_MIPS_64	g1    0
-	.dword	l1		# R_MIPS_64	.foo  100
-	.dword	l2		# R_MIPS_64	.text 4
-	.dword	g1-l3		# R_MIPS_PC64	g1    4C
-	.dword	l1-l3		# R_MIPS_PC64	.foo  154
-	.dword	l2-l3		# -30
-l5:
-	b	2f		# R_MIPS_GNU_REL16_S2	.text 32
-	b	2f+4		# R_MIPS_GNU_REL16_S2	.text 33
-	la	$3,2f-l5	# R_MIPS_GNU_REL_HI16	.text 0
-	                        # R_MIPS_GNU_REL_LO16   .text D8
-	la	$3,2f+8-l5	# R_MIPS_GNU_REL_HI16	.text 0
-	                        # R_MIPS_GNU_REL_LO16   .text E8
-
-
-	.word	2f		# R_MIPS_32	.text CC
-	.word	2f-l5		# R_MIPS_PC32	.text EC  or 34
-	.dword	2f		# R_MIPS_64	.text CC
-	.dword	2f-l5		# R_MIPS_PC64	.text F8  or 34
-	nop
-2:				# at address 0xCC.
-	b	2b		# R_MIPS_GNU_REL16_S2	.text 32
-	b	2b+4		# R_MIPS_GNU_REL16_S2	.text 33
-	la	$3,2b-l5	# R_MIPS_GNU_REL_HI16	.text 0
-				# R_MIPS_GNU_REL_LO16	.text 10C
-	la	$3,2b+8-l5	# R_MIPS_GNU_REL_HI16	.text 0
-				# R_MIPS_GNU_REL_LO16	.text 11C
-	.word	2b		# R_MIPS_32	.text CC
-	.word	2b-l5		# R_MIPS_PC32	.text 11C  or 34
-	nop
-	.dword	2b		# R_MIPS_64	.text CC
-	.dword	2b-l5		# R_MIPS_PC64	.text 98  or 34
-
-# align section end to 16-byte boundary for easier testing on multiple targets
-	.p2align 4
-
-	.section ".foo","ax",@progbits
-	nop
-l4:	
-	la	$3,g1-l4
-	la	$3,l1-l4
-	la	$3,l2-l4
-	la	$3,g1-l4
-
-	dla	$3,g1-l4
-	dla	$3,l1-l4
-	dla	$3,l2-l4
-
-	.word	g1
-	.word	l1
-	.word	l2
-	.word	g1-l4
-	.word	l1-l4
-	.word	l2-l4
-	.dword	g1
-	.dword	l1
-	.dword	l2
-	.dword	g1-l4
-	.dword	l1-l4
-	.dword	l2-l4
-
-	la	$3,g1-l4+4
-	la	$3,l1-l4+4
-	la	$3,l2-l4+4
-
-	dla	$3,g1-l4+4
-	dla	$3,l1-l4+4
-	dla	$3,l2-l4+4
-
-	.word	g1+4
-	.word	l1+4
-	.word	l2+4
-	.word	g1-l4+4
-	.word	l1-l4+4
-	.word	l2-l4+4
-	.dword	g1+4
-	.dword	l1+4
-	.dword	l2+4
-	.dword	g1-l4+4
-	.dword	l1-l4+4
-	.dword	l2-l4+4
-l1:
-
-	nop
-
-# align section end to 16-byte boundary for easier testing on multiple targets
-	.p2align 4
diff --git a/gas/testsuite/gas/mips/empic2.d b/gas/testsuite/gas/mips/empic2.d
deleted file mode 100644
index de691b1be5df..000000000000
--- a/gas/testsuite/gas/mips/empic2.d
+++ /dev/null
@@ -1,279 +0,0 @@
-#objdump: --prefix-addresses -dr --show-raw-insn -mmips:4000
-#name: MIPS empic2
-#as: -mabi=o64 -membedded-pic -mips3
-
-# Check assembly of and relocs for -membedded-pic la, lw, ld, sw, sd macros.
-
-.*: +file format elf.*mips.*
-
-Disassembly of section .text:
-0+000000 <[^>]*> 00000000 	nop
-	...
-	...
-0+01000c <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*1000c: R_MIPS_GNU_REL_HI16	.text
-0+010010 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010014 <[^>]*> 6442000c 	daddiu	v0,v0,12
-[ 	]*10014: R_MIPS_GNU_REL_LO16	.text
-0+010018 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10018: R_MIPS_GNU_REL_HI16	.text
-0+01001c <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010020 <[^>]*> 64420018 	daddiu	v0,v0,24
-[ 	]*10020: R_MIPS_GNU_REL_LO16	.text
-0+010024 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10024: R_MIPS_GNU_REL_HI16	.text
-0+010028 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01002c <[^>]*> 64428028 	daddiu	v0,v0,-32728
-[ 	]*1002c: R_MIPS_GNU_REL_LO16	.text
-0+010030 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10030: R_MIPS_GNU_REL_HI16	.text
-0+010034 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010038 <[^>]*> 64428034 	daddiu	v0,v0,-32716
-[ 	]*10038: R_MIPS_GNU_REL_LO16	.text
-0+01003c <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*1003c: R_MIPS_GNU_REL_HI16	.text
-0+010040 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010044 <[^>]*> 644202ac 	daddiu	v0,v0,684
-[ 	]*10044: R_MIPS_GNU_REL_LO16	.text
-0+010048 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10048: R_MIPS_GNU_REL_HI16	.text
-0+01004c <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010050 <[^>]*> 644202b8 	daddiu	v0,v0,696
-[ 	]*10050: R_MIPS_GNU_REL_LO16	.text
-0+010054 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10054: R_MIPS_GNU_REL_HI16	e
-0+010058 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01005c <[^>]*> 64420050 	daddiu	v0,v0,80
-[ 	]*1005c: R_MIPS_GNU_REL_LO16	e
-0+010060 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10060: R_MIPS_GNU_REL_HI16	.text
-0+010064 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010068 <[^>]*> 64420060 	daddiu	v0,v0,96
-[ 	]*10068: R_MIPS_GNU_REL_LO16	.text
-0+01006c <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*1006c: R_MIPS_GNU_REL_HI16	.text
-0+010070 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010074 <[^>]*> 6442006c 	daddiu	v0,v0,108
-[ 	]*10074: R_MIPS_GNU_REL_LO16	.text
-0+010078 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10078: R_MIPS_GNU_REL_HI16	.text
-0+01007c <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010080 <[^>]*> 6442807c 	daddiu	v0,v0,-32644
-[ 	]*10080: R_MIPS_GNU_REL_LO16	.text
-0+010084 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10084: R_MIPS_GNU_REL_HI16	.text
-0+010088 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01008c <[^>]*> 64428088 	daddiu	v0,v0,-32632
-[ 	]*1008c: R_MIPS_GNU_REL_LO16	.text
-0+010090 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10090: R_MIPS_GNU_REL_HI16	.text
-0+010094 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010098 <[^>]*> 64420300 	daddiu	v0,v0,768
-[ 	]*10098: R_MIPS_GNU_REL_LO16	.text
-0+01009c <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*1009c: R_MIPS_GNU_REL_HI16	.text
-0+0100a0 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0100a4 <[^>]*> 6442030c 	daddiu	v0,v0,780
-[ 	]*100a4: R_MIPS_GNU_REL_LO16	.text
-0+0100a8 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100a8: R_MIPS_GNU_REL_HI16	e
-0+0100ac <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0100b0 <[^>]*> 644200a4 	daddiu	v0,v0,164
-[ 	]*100b0: R_MIPS_GNU_REL_LO16	e
-0+0100b4 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100b4: R_MIPS_GNU_REL_HI16	.text
-0+0100b8 <[^>]*> 644200b0 	daddiu	v0,v0,176
-[ 	]*100b8: R_MIPS_GNU_REL_LO16	.text
-0+0100bc <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100bc: R_MIPS_GNU_REL_HI16	.text
-0+0100c0 <[^>]*> 644200b8 	daddiu	v0,v0,184
-[ 	]*100c0: R_MIPS_GNU_REL_LO16	.text
-0+0100c4 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*100c4: R_MIPS_GNU_REL_HI16	.text
-0+0100c8 <[^>]*> 644280c4 	daddiu	v0,v0,-32572
-[ 	]*100c8: R_MIPS_GNU_REL_LO16	.text
-0+0100cc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*100cc: R_MIPS_GNU_REL_HI16	.text
-0+0100d0 <[^>]*> 644280cc 	daddiu	v0,v0,-32564
-[ 	]*100d0: R_MIPS_GNU_REL_LO16	.text
-0+0100d4 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*100d4: R_MIPS_GNU_REL_HI16	.text
-0+0100d8 <[^>]*> 64420340 	daddiu	v0,v0,832
-[ 	]*100d8: R_MIPS_GNU_REL_LO16	.text
-0+0100dc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*100dc: R_MIPS_GNU_REL_HI16	.text
-0+0100e0 <[^>]*> 64420348 	daddiu	v0,v0,840
-[ 	]*100e0: R_MIPS_GNU_REL_LO16	.text
-0+0100e4 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100e4: R_MIPS_GNU_REL_HI16	e
-0+0100e8 <[^>]*> 644200dc 	daddiu	v0,v0,220
-[ 	]*100e8: R_MIPS_GNU_REL_LO16	e
-0+0100ec <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100ec: R_MIPS_GNU_REL_HI16	.text
-0+0100f0 <[^>]*> 644200e8 	daddiu	v0,v0,232
-[ 	]*100f0: R_MIPS_GNU_REL_LO16	.text
-0+0100f4 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*100f4: R_MIPS_GNU_REL_HI16	.text
-0+0100f8 <[^>]*> 644200f0 	daddiu	v0,v0,240
-[ 	]*100f8: R_MIPS_GNU_REL_LO16	.text
-0+0100fc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*100fc: R_MIPS_GNU_REL_HI16	.text
-0+010100 <[^>]*> 644280fc 	daddiu	v0,v0,-32516
-[ 	]*10100: R_MIPS_GNU_REL_LO16	.text
-0+010104 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10104: R_MIPS_GNU_REL_HI16	.text
-0+010108 <[^>]*> 64428104 	daddiu	v0,v0,-32508
-[ 	]*10108: R_MIPS_GNU_REL_LO16	.text
-0+01010c <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*1010c: R_MIPS_GNU_REL_HI16	.text
-0+010110 <[^>]*> 64420378 	daddiu	v0,v0,888
-[ 	]*10110: R_MIPS_GNU_REL_LO16	.text
-0+010114 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10114: R_MIPS_GNU_REL_HI16	.text
-0+010118 <[^>]*> 64420380 	daddiu	v0,v0,896
-[ 	]*10118: R_MIPS_GNU_REL_LO16	.text
-0+01011c <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*1011c: R_MIPS_GNU_REL_HI16	e
-0+010120 <[^>]*> 64420114 	daddiu	v0,v0,276
-[ 	]*10120: R_MIPS_GNU_REL_LO16	e
-0+010124 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10124: R_MIPS_GNU_REL_HI16	.text
-0+010128 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01012c <[^>]*> 8c420124 	lw	v0,292\(v0\)
-[ 	]*1012c: R_MIPS_GNU_REL_LO16	.text
-0+010130 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10130: R_MIPS_GNU_REL_HI16	.text
-0+010134 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010138 <[^>]*> 8c420130 	lw	v0,304\(v0\)
-[ 	]*10138: R_MIPS_GNU_REL_LO16	.text
-0+01013c <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*1013c: R_MIPS_GNU_REL_HI16	.text
-0+010140 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010144 <[^>]*> 8c428140 	lw	v0,-32448\(v0\)
-[ 	]*10144: R_MIPS_GNU_REL_LO16	.text
-0+010148 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10148: R_MIPS_GNU_REL_HI16	.text
-0+01014c <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010150 <[^>]*> 8c42814c 	lw	v0,-32436\(v0\)
-[ 	]*10150: R_MIPS_GNU_REL_LO16	.text
-0+010154 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10154: R_MIPS_GNU_REL_HI16	.text
-0+010158 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01015c <[^>]*> 8c4203c4 	lw	v0,964\(v0\)
-[ 	]*1015c: R_MIPS_GNU_REL_LO16	.text
-0+010160 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10160: R_MIPS_GNU_REL_HI16	.text
-0+010164 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010168 <[^>]*> 8c4203d0 	lw	v0,976\(v0\)
-[ 	]*10168: R_MIPS_GNU_REL_LO16	.text
-0+01016c <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*1016c: R_MIPS_GNU_REL_HI16	e
-0+010170 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010174 <[^>]*> 8c420168 	lw	v0,360\(v0\)
-[ 	]*10174: R_MIPS_GNU_REL_LO16	e
-0+010178 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10178: R_MIPS_GNU_REL_HI16	.text
-0+01017c <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010180 <[^>]*> dc420178 	ld	v0,376\(v0\)
-[ 	]*10180: R_MIPS_GNU_REL_LO16	.text
-0+010184 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*10184: R_MIPS_GNU_REL_HI16	.text
-0+010188 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+01018c <[^>]*> dc420184 	ld	v0,388\(v0\)
-[ 	]*1018c: R_MIPS_GNU_REL_LO16	.text
-0+010190 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*10190: R_MIPS_GNU_REL_HI16	.text
-0+010194 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+010198 <[^>]*> dc428194 	ld	v0,-32364\(v0\)
-[ 	]*10198: R_MIPS_GNU_REL_LO16	.text
-0+01019c <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*1019c: R_MIPS_GNU_REL_HI16	.text
-0+0101a0 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0101a4 <[^>]*> dc4281a0 	ld	v0,-32352\(v0\)
-[ 	]*101a4: R_MIPS_GNU_REL_LO16	.text
-0+0101a8 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*101a8: R_MIPS_GNU_REL_HI16	.text
-0+0101ac <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0101b0 <[^>]*> dc420418 	ld	v0,1048\(v0\)
-[ 	]*101b0: R_MIPS_GNU_REL_LO16	.text
-0+0101b4 <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*101b4: R_MIPS_GNU_REL_HI16	.text
-0+0101b8 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0101bc <[^>]*> dc420424 	ld	v0,1060\(v0\)
-[ 	]*101bc: R_MIPS_GNU_REL_LO16	.text
-0+0101c0 <[^>]*> 3c020000 	lui	v0,0x0
-[ 	]*101c0: R_MIPS_GNU_REL_HI16	e
-0+0101c4 <[^>]*> 0044102d 	daddu	v0,v0,a0
-0+0101c8 <[^>]*> dc4201bc 	ld	v0,444\(v0\)
-[ 	]*101c8: R_MIPS_GNU_REL_LO16	e
-0+0101cc <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*101cc: R_MIPS_GNU_REL_HI16	.text
-0+0101d0 <[^>]*> 0024082d 	daddu	at,at,a0
-0+0101d4 <[^>]*> ac2201cc 	sw	v0,460\(at\)
-[ 	]*101d4: R_MIPS_GNU_REL_LO16	.text
-0+0101d8 <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*101d8: R_MIPS_GNU_REL_HI16	.text
-0+0101dc <[^>]*> 0024082d 	daddu	at,at,a0
-0+0101e0 <[^>]*> ac2201d8 	sw	v0,472\(at\)
-[ 	]*101e0: R_MIPS_GNU_REL_LO16	.text
-0+0101e4 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*101e4: R_MIPS_GNU_REL_HI16	.text
-0+0101e8 <[^>]*> 0024082d 	daddu	at,at,a0
-0+0101ec <[^>]*> ac2281e8 	sw	v0,-32280\(at\)
-[ 	]*101ec: R_MIPS_GNU_REL_LO16	.text
-0+0101f0 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*101f0: R_MIPS_GNU_REL_HI16	.text
-0+0101f4 <[^>]*> 0024082d 	daddu	at,at,a0
-0+0101f8 <[^>]*> ac2281f4 	sw	v0,-32268\(at\)
-[ 	]*101f8: R_MIPS_GNU_REL_LO16	.text
-0+0101fc <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*101fc: R_MIPS_GNU_REL_HI16	.text
-0+010200 <[^>]*> 0024082d 	daddu	at,at,a0
-0+010204 <[^>]*> ac22046c 	sw	v0,1132\(at\)
-[ 	]*10204: R_MIPS_GNU_REL_LO16	.text
-0+010208 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*10208: R_MIPS_GNU_REL_HI16	.text
-0+01020c <[^>]*> 0024082d 	daddu	at,at,a0
-0+010210 <[^>]*> ac220478 	sw	v0,1144\(at\)
-[ 	]*10210: R_MIPS_GNU_REL_LO16	.text
-0+010214 <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*10214: R_MIPS_GNU_REL_HI16	e
-0+010218 <[^>]*> 0024082d 	daddu	at,at,a0
-0+01021c <[^>]*> ac220210 	sw	v0,528\(at\)
-[ 	]*1021c: R_MIPS_GNU_REL_LO16	e
-0+010220 <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*10220: R_MIPS_GNU_REL_HI16	.text
-0+010224 <[^>]*> 0024082d 	daddu	at,at,a0
-0+010228 <[^>]*> fc220220 	sd	v0,544\(at\)
-[ 	]*10228: R_MIPS_GNU_REL_LO16	.text
-0+01022c <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*1022c: R_MIPS_GNU_REL_HI16	.text
-0+010230 <[^>]*> 0024082d 	daddu	at,at,a0
-0+010234 <[^>]*> fc22022c 	sd	v0,556\(at\)
-[ 	]*10234: R_MIPS_GNU_REL_LO16	.text
-0+010238 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*10238: R_MIPS_GNU_REL_HI16	.text
-0+01023c <[^>]*> 0024082d 	daddu	at,at,a0
-0+010240 <[^>]*> fc22823c 	sd	v0,-32196\(at\)
-[ 	]*10240: R_MIPS_GNU_REL_LO16	.text
-0+010244 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*10244: R_MIPS_GNU_REL_HI16	.text
-0+010248 <[^>]*> 0024082d 	daddu	at,at,a0
-0+01024c <[^>]*> fc228248 	sd	v0,-32184\(at\)
-[ 	]*1024c: R_MIPS_GNU_REL_LO16	.text
-0+010250 <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*10250: R_MIPS_GNU_REL_HI16	.text
-0+010254 <[^>]*> 0024082d 	daddu	at,at,a0
-0+010258 <[^>]*> fc2204c0 	sd	v0,1216\(at\)
-[ 	]*10258: R_MIPS_GNU_REL_LO16	.text
-0+01025c <[^>]*> 3c010001 	lui	at,0x1
-[ 	]*1025c: R_MIPS_GNU_REL_HI16	.text
-0+010260 <[^>]*> 0024082d 	daddu	at,at,a0
-0+010264 <[^>]*> fc2204cc 	sd	v0,1228\(at\)
-[ 	]*10264: R_MIPS_GNU_REL_LO16	.text
-0+010268 <[^>]*> 3c010000 	lui	at,0x0
-[ 	]*10268: R_MIPS_GNU_REL_HI16	e
-0+01026c <[^>]*> 0024082d 	daddu	at,at,a0
-0+010270 <[^>]*> fc220264 	sd	v0,612\(at\)
-[ 	]*10270: R_MIPS_GNU_REL_LO16	e
-	...
diff --git a/gas/testsuite/gas/mips/empic2.s b/gas/testsuite/gas/mips/empic2.s
deleted file mode 100644
index e63e02b2edbb..000000000000
--- a/gas/testsuite/gas/mips/empic2.s
+++ /dev/null
@@ -1,100 +0,0 @@
-# Check assembly of and relocs for -membedded-pic la, lw, ld, sw, sd macros.
-
-        .text
-        .set noreorder
-
-start:
-	nop
-
-	.globl	g1
-	.ent	g1
-i1:				# 0x00004
-g1:
-	.space 0x8000
-	nop
-	.end	g1
-
-	.globl	g2
-	.ent	g2
-i2:				# 0x08008
-g2:
-	.space 0x8000
-	nop
-	.end	g2
-
-	.globl	g3
-	.ent	g3
-i3:				# 0x1000c
-g3:
-
-	la	$2, (i1 - i3)($4)
-	la	$2, (g1 - i3)($4)
-	la	$2, (i2 - i3)($4)
-	la	$2, (g2 - i3)($4)
-	la	$2, (if - i3)($4)
-	la	$2, (gf - i3)($4)
-	la	$2, (e  - i3)($4)
-	la	$2, (i1 - g3)($4)
-	la	$2, (g1 - g3)($4)
-	la	$2, (i2 - g3)($4)
-	la	$2, (g2 - g3)($4)
-	la	$2, (if - g3)($4)
-	la	$2, (gf - g3)($4)
-	la	$2, (e  - g3)($4)
-
-	la	$2, (i1 - i3)
-	la	$2, (g1 - i3)
-	la	$2, (i2 - i3)
-	la	$2, (g2 - i3)
-	la	$2, (if - i3)
-	la	$2, (gf - i3)
-	la	$2, (e  - i3)
-	la	$2, (i1 - g3)
-	la	$2, (g1 - g3)
-	la	$2, (i2 - g3)
-	la	$2, (g2 - g3)
-	la	$2, (if - g3)
-	la	$2, (gf - g3)
-	la	$2, (e  - g3)
-
-	lw	$2, (i1 - i3)($4)
-	lw	$2, (g1 - i3)($4)
-	lw	$2, (i2 - i3)($4)
-	lw	$2, (g2 - i3)($4)
-	lw	$2, (if - i3)($4)
-	lw	$2, (gf - i3)($4)
-	lw	$2, (e  - i3)($4)
-	ld	$2, (i1 - g3)($4)
-	ld	$2, (g1 - g3)($4)
-	ld	$2, (i2 - g3)($4)
-	ld	$2, (g2 - g3)($4)
-	ld	$2, (if - g3)($4)
-	ld	$2, (gf - g3)($4)
-	ld	$2, (e  - g3)($4)
-
-	sw	$2, (i1 - i3)($4)
-	sw	$2, (g1 - i3)($4)
-	sw	$2, (i2 - i3)($4)
-	sw	$2, (g2 - i3)($4)
-	sw	$2, (if - i3)($4)
-	sw	$2, (gf - i3)($4)
-	sw	$2, (e  - i3)($4)
-	sd	$2, (i1 - g3)($4)
-	sd	$2, (g1 - g3)($4)
-	sd	$2, (i2 - g3)($4)
-	sd	$2, (g2 - g3)($4)
-	sd	$2, (if - g3)($4)
-	sd	$2, (gf - g3)($4)
-	sd	$2, (e  - g3)($4)
-
-	.end	g3
-
-	.globl	gf
-	.ent	gf
-if:
-gf:
-	nop
-	.end	gf
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-      .space  8
diff --git a/gas/testsuite/gas/mips/empic3_e.d b/gas/testsuite/gas/mips/empic3_e.d
deleted file mode 100644
index d491e47e6e61..000000000000
--- a/gas/testsuite/gas/mips/empic3_e.d
+++ /dev/null
@@ -1,47 +0,0 @@
-#objdump: --prefix-addresses -dr --show-raw-insn -mmips:4000
-#name: MIPS empic3 (external)
-#as: -mabi=o64 -membedded-pic -mips3
-
-# Check PC-relative HI/LO relocs relocs for -membedded-pic when HI and
-# LO are split over a 32K boundary.
-
-.*: +file format elf.*mips.*
-
-Disassembly of section .text:
-	...
-	...
-0000fffc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*fffc: R_MIPS_GNU_REL_HI16	ext
-00010000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*10000: R_MIPS_GNU_REL_LO16	ext
-	...
-00017ffc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*17ffc: R_MIPS_GNU_REL_HI16	ext
-00018000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*18000: R_MIPS_GNU_REL_LO16	ext
-	...
-0001fffc <[^>]*> 3c020002 	lui	v0,0x2
-[ 	]*1fffc: R_MIPS_GNU_REL_HI16	ext
-00020000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00020004 <[^>]*> 64428004 	daddiu	v0,v0,-32764
-[ 	]*20004: R_MIPS_GNU_REL_LO16	ext
-	...
-00027ffc <[^>]*> 3c020002 	lui	v0,0x2
-[ 	]*27ffc: R_MIPS_GNU_REL_HI16	ext
-00028000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00028004 <[^>]*> 64420004 	daddiu	v0,v0,4
-[ 	]*28004: R_MIPS_GNU_REL_LO16	ext
-	...
-0002fff8 <[^>]*> 3c020003 	lui	v0,0x3
-[ 	]*2fff8: R_MIPS_GNU_REL_HI16	ext
-0002fffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00030000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*30000: R_MIPS_GNU_REL_LO16	ext
-	...
-00037ff8 <[^>]*> 3c020003 	lui	v0,0x3
-[ 	]*37ff8: R_MIPS_GNU_REL_HI16	ext
-00037ffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00038000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*38000: R_MIPS_GNU_REL_LO16	ext
-	...
-	...
diff --git a/gas/testsuite/gas/mips/empic3_e.s b/gas/testsuite/gas/mips/empic3_e.s
deleted file mode 100644
index 427e8c8b1070..000000000000
--- a/gas/testsuite/gas/mips/empic3_e.s
+++ /dev/null
@@ -1,46 +0,0 @@
-# Check PC-relative HI/LO relocs for -membedded-pic when HI and LO are
-# split over a 32K boundary.
-
-        .text
-        .set noreorder
-
-	SYM_TO_TEST = ext
-
-	.globl	ext
-
-	.org	0x00000
-	.globl	g1
-g1:
-l1:
-
-	.org	0x08000
-	.globl	fn
-	.ent	fn
-fn:
-	.org	(0x10000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x18000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x20000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x28000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x30000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x38000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.end fn
-
-	.org	0x40000
-	.globl	g2
-g2:
-l2:
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-      .space  8
diff --git a/gas/testsuite/gas/mips/empic3_g1.d b/gas/testsuite/gas/mips/empic3_g1.d
deleted file mode 100644
index fde87e058776..000000000000
--- a/gas/testsuite/gas/mips/empic3_g1.d
+++ /dev/null
@@ -1,47 +0,0 @@
-#objdump: --prefix-addresses -dr --show-raw-insn -mmips:4000
-#name: MIPS empic3 (global, negative)
-#as: -mabi=o64 -membedded-pic -mips3
-
-# Check PC-relative HI/LO relocs relocs for -membedded-pic when HI and
-# LO are split over a 32K boundary.
-
-.*: +file format elf.*mips.*
-
-Disassembly of section .text:
-	...
-	...
-0000fffc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*fffc: R_MIPS_GNU_REL_HI16	.text
-00010000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*10000: R_MIPS_GNU_REL_LO16	.text
-	...
-00017ffc <[^>]*> 3c020001 	lui	v0,0x1
-[ 	]*17ffc: R_MIPS_GNU_REL_HI16	.text
-00018000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*18000: R_MIPS_GNU_REL_LO16	.text
-	...
-0001fffc <[^>]*> 3c020002 	lui	v0,0x2
-[ 	]*1fffc: R_MIPS_GNU_REL_HI16	.text
-00020000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00020004 <[^>]*> 64428004 	daddiu	v0,v0,-32764
-[ 	]*20004: R_MIPS_GNU_REL_LO16	.text
-	...
-00027ffc <[^>]*> 3c020002 	lui	v0,0x2
-[ 	]*27ffc: R_MIPS_GNU_REL_HI16	.text
-00028000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00028004 <[^>]*> 64420004 	daddiu	v0,v0,4
-[ 	]*28004: R_MIPS_GNU_REL_LO16	.text
-	...
-0002fff8 <[^>]*> 3c020003 	lui	v0,0x3
-[ 	]*2fff8: R_MIPS_GNU_REL_HI16	.text
-0002fffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00030000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*30000: R_MIPS_GNU_REL_LO16	.text
-	...
-00037ff8 <[^>]*> 3c020003 	lui	v0,0x3
-[ 	]*37ff8: R_MIPS_GNU_REL_HI16	.text
-00037ffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00038000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*38000: R_MIPS_GNU_REL_LO16	.text
-	...
-	...
diff --git a/gas/testsuite/gas/mips/empic3_g1.s b/gas/testsuite/gas/mips/empic3_g1.s
deleted file mode 100644
index cf1df44a8cf2..000000000000
--- a/gas/testsuite/gas/mips/empic3_g1.s
+++ /dev/null
@@ -1,46 +0,0 @@
-# Check PC-relative HI/LO relocs relocs for -membedded-pic when HI and
-# LO are split over a 32K boundary.
-
-        .text
-        .set noreorder
-
-	SYM_TO_TEST = g1
-
-	.globl	ext
-
-	.org	0x00000
-	.globl	g1
-g1:
-l1:
-
-	.org	0x08000
-	.globl	fn
-	.ent	fn
-fn:
-	.org	(0x10000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x18000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x20000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x28000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x30000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x38000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.end fn
-
-	.org	0x40000
-	.globl	g2
-g2:
-l2:
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-      .space  8
diff --git a/gas/testsuite/gas/mips/empic3_g2.d b/gas/testsuite/gas/mips/empic3_g2.d
deleted file mode 100644
index 08b5e4beb076..000000000000
--- a/gas/testsuite/gas/mips/empic3_g2.d
+++ /dev/null
@@ -1,47 +0,0 @@
-#objdump: --prefix-addresses -dr --show-raw-insn -mmips:4000
-#name: MIPS empic3 (global, positive)
-#as: -mabi=o64 -membedded-pic -mips3
-
-# Check PC-relative HI/LO relocs relocs for -membedded-pic when HI and
-# LO are split over a 32K boundary.
-
-.*: +file format elf.*mips.*
-
-Disassembly of section .text:
-	...
-	...
-0000fffc <[^>]*> 3c020005 	lui	v0,0x5
-[ 	]*fffc: R_MIPS_GNU_REL_HI16	.text
-00010000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*10000: R_MIPS_GNU_REL_LO16	.text
-	...
-00017ffc <[^>]*> 3c020005 	lui	v0,0x5
-[ 	]*17ffc: R_MIPS_GNU_REL_HI16	.text
-00018000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*18000: R_MIPS_GNU_REL_LO16	.text
-	...
-0001fffc <[^>]*> 3c020006 	lui	v0,0x6
-[ 	]*1fffc: R_MIPS_GNU_REL_HI16	.text
-00020000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00020004 <[^>]*> 64428004 	daddiu	v0,v0,-32764
-[ 	]*20004: R_MIPS_GNU_REL_LO16	.text
-	...
-00027ffc <[^>]*> 3c020006 	lui	v0,0x6
-[ 	]*27ffc: R_MIPS_GNU_REL_HI16	.text
-00028000 <[^>]*> 0043102d 	daddu	v0,v0,v1
-00028004 <[^>]*> 64420004 	daddiu	v0,v0,4
-[ 	]*28004: R_MIPS_GNU_REL_LO16	.text
-	...
-0002fff8 <[^>]*> 3c020007 	lui	v0,0x7
-[ 	]*2fff8: R_MIPS_GNU_REL_HI16	.text
-0002fffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00030000 <[^>]*> 64428000 	daddiu	v0,v0,-32768
-[ 	]*30000: R_MIPS_GNU_REL_LO16	.text
-	...
-00037ff8 <[^>]*> 3c020007 	lui	v0,0x7
-[ 	]*37ff8: R_MIPS_GNU_REL_HI16	.text
-00037ffc <[^>]*> 0043102d 	daddu	v0,v0,v1
-00038000 <[^>]*> 64420000 	daddiu	v0,v0,0
-[ 	]*38000: R_MIPS_GNU_REL_LO16	.text
-	...
-	...
diff --git a/gas/testsuite/gas/mips/empic3_g2.s b/gas/testsuite/gas/mips/empic3_g2.s
deleted file mode 100644
index 4c070ee04ade..000000000000
--- a/gas/testsuite/gas/mips/empic3_g2.s
+++ /dev/null
@@ -1,46 +0,0 @@
-# Check PC-relative HI/LO relocs relocs for -membedded-pic when HI and
-# LO are split over a 32K boundary.
-
-        .text
-        .set noreorder
-
-	SYM_TO_TEST = g2
-
-	.globl	ext
-
-	.org	0x00000
-	.globl	g1
-g1:
-l1:
-
-	.org	0x08000
-	.globl	fn
-	.ent	fn
-fn:
-	.org	(0x10000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x18000 - 4)
-	la	$2, SYM_TO_TEST - fn		# expands to 2 instructions
-
-	.org	(0x20000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x28000 - 4)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x30000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.org	(0x38000 - 8)
-	la	$2, (SYM_TO_TEST - fn)($3)	# expands to 3 instructions
-
-	.end fn
-
-	.org	0x40000
-	.globl	g2
-g2:
-l2:
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-      .space  8
diff --git a/gas/testsuite/gas/mips/jal-empic-elf-2.d b/gas/testsuite/gas/mips/jal-empic-elf-2.d
deleted file mode 100644
index 7e9623e5b1b9..000000000000
--- a/gas/testsuite/gas/mips/jal-empic-elf-2.d
+++ /dev/null
@@ -1,48 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: MIPS jal-empic-elf-2
-#as: -32 -membedded-pic
-
-# Test the jal macro harder with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-	\.\.\.
-	\.\.\.
-0+0018 <[^>]*> 04110002 	bal	0+0024 <g1\+0x18>
-[ 	]*18: R_MIPS_GNU_REL16_S2	.text
-0+001c <[^>]*> 00000000 	nop
-0+0020 <[^>]*> 04110002 	bal	0+002c <g1\+0x20>
-[ 	]*20: R_MIPS_GNU_REL16_S2	.text
-0+0024 <[^>]*> 00000000 	nop
-0+0028 <[^>]*> 0411ffff 	bal	0+0028 <g1\+0x1c>
-[ 	]*28: R_MIPS_GNU_REL16_S2	e1
-0+002c <[^>]*> 00000000 	nop
-0+0030 <[^>]*> 10000002 	b	0+003c <g1\+0x30>
-[ 	]*30: R_MIPS_GNU_REL16_S2	.text
-0+0034 <[^>]*> 00000000 	nop
-0+0038 <[^>]*> 10000002 	b	0+0044 <g1\+0x38>
-[ 	]*38: R_MIPS_GNU_REL16_S2	.text
-0+003c <[^>]*> 00000000 	nop
-0+0040 <[^>]*> 1000ffff 	b	0+0040 <g1\+0x34>
-[ 	]*40: R_MIPS_GNU_REL16_S2	e1
-0+0044 <[^>]*> 00000000 	nop
-0+0048 <[^>]*> 0411ffff 	bal	0+0048 <g1\+0x3c>
-[ 	]*48: R_MIPS_GNU_REL16_S2	.text
-0+004c <[^>]*> 00000000 	nop
-0+0050 <[^>]*> 0411ffff 	bal	0+0050 <g1\+0x44>
-[ 	]*50: R_MIPS_GNU_REL16_S2	.text
-0+0054 <[^>]*> 00000000 	nop
-0+0058 <[^>]*> 0411fffc 	bal	0+004c <g1\+0x40>
-[ 	]*58: R_MIPS_GNU_REL16_S2	e1
-0+005c <[^>]*> 00000000 	nop
-0+0060 <[^>]*> 04110005 	bal	0+0078 <g1\+0x6c>
-[ 	]*60: R_MIPS_GNU_REL16_S2	.text
-0+0064 <[^>]*> 00000000 	nop
-0+0068 <[^>]*> 04110005 	bal	0+0080 <g1\+0x74>
-[ 	]*68: R_MIPS_GNU_REL16_S2	.text
-0+006c <[^>]*> 00000000 	nop
-0+0070 <[^>]*> 04110002 	bal	0+007c <g1\+0x70>
-[ 	]*70: R_MIPS_GNU_REL16_S2	e1
-0+0074 <[^>]*> 00000000 	nop
-	\.\.\.
diff --git a/gas/testsuite/gas/mips/jal-empic-elf-2.s b/gas/testsuite/gas/mips/jal-empic-elf-2.s
deleted file mode 100644
index 3a175552761c..000000000000
--- a/gas/testsuite/gas/mips/jal-empic-elf-2.s
+++ /dev/null
@@ -1,28 +0,0 @@
-# Source file used to test the jal macro even harder
-	# some space so offets won't be 0.
-	.space 0xc
-
-	.globl	g1	.text
-g1:
-l1:
-	# some more space, so offset from label won't be 0.
-	.space 0xc
-
-	jal	g1			# 0x18
-	jal	l1			# 0x20
-	jal	e1			# 0x28
-
-	j	g1			# 0x30
-	j	l1			# 0x38
-	j	e1			# 0x40
-
-	jal	g1 - 0xc		# 0x48
-	jal	l1 - 0xc		# 0x50
-	jal	e1 - 0xc		# 0x58
-
-	jal	g1 + 0xc		# 0x60
-	jal	l1 + 0xc		# 0x68
-	jal	e1 + 0xc		# 0x70
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-	.space  8
diff --git a/gas/testsuite/gas/mips/jal-empic-elf-3.d b/gas/testsuite/gas/mips/jal-empic-elf-3.d
deleted file mode 100644
index 0f6a11a0a6a0..000000000000
--- a/gas/testsuite/gas/mips/jal-empic-elf-3.d
+++ /dev/null
@@ -1,24 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: MIPS jal-empic-elf-3
-#as: -32 -membedded-pic
-
-# Test the jal macro harder with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-	\.\.\.
-	\.\.\.
-0+0018 <[^>]*> 0411fffa 	bal	0+0004 <g1\-0x8>
-[ 	]*18: R_MIPS_GNU_REL16_S2	.text
-0+001c <[^>]*> 00000000 	nop
-0+0020 <[^>]*> 0411fff8 	bal	0+0004 <g1\-0x8>
-[ 	]*20: R_MIPS_GNU_REL16_S2	.text
-0+0024 <[^>]*> 00000000 	nop
-0+0028 <[^>]*> 0411fff6 	bal	0+0004 <g1\-0x8>
-[ 	]*28: R_MIPS_GNU_REL16_S2	e1
-0+002c <[^>]*> 00000000 	nop
-0+0030 <[^>]*> 0411fff4 	bal	0+0004 <g1\-0x8>
-[ 	]*30: R_MIPS_GNU_REL16_S2	e2
-0+0034 <[^>]*> 00000000 	nop
-	\.\.\.
diff --git a/gas/testsuite/gas/mips/jal-empic-elf-3.s b/gas/testsuite/gas/mips/jal-empic-elf-3.s
deleted file mode 100644
index 7043d527f8d9..000000000000
--- a/gas/testsuite/gas/mips/jal-empic-elf-3.s
+++ /dev/null
@@ -1,20 +0,0 @@
-# Source file used to test the jal macro even harder
-	# some space so offets won't be 0.
-	.space 0xc
-
-	.globl	g1	.text
-	.globl	e2	.text
-g1:
-l1:
-	# some more space, so offset from label won't be 0.
-	.space 0xc
-
-	# Hit the case where 'value == 0' in the BFD_RELOC_16_PCREL_S2
-	# handling in tc-mips.c:md_apply_fix3().
-	jal	g1 - 0x20		# 0x18
-	jal	l1 - 0x28		# 0x20
-	jal	e1 - 0x24		# 0x28
-	jal	e2 - 0x2c		# 0x30
-
-# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
-	.space  8
diff --git a/gas/testsuite/gas/mips/jal-empic-elf.d b/gas/testsuite/gas/mips/jal-empic-elf.d
deleted file mode 100644
index 25022233f125..000000000000
--- a/gas/testsuite/gas/mips/jal-empic-elf.d
+++ /dev/null
@@ -1,26 +0,0 @@
-#objdump: -dr --prefix-addresses --show-raw-insn
-#name: MIPS jal-empic-elf
-#as: -32 -membedded-pic
-#source: jal.s
-
-# Test the jal macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> 0320f809 	jalr	t9
-0+0004 <[^>]*> 00000000 	nop
-0+0008 <[^>]*> 03202009 	jalr	a0,t9
-0+000c <[^>]*> 00000000 	nop
-0+0010 <[^>]*> 0411ffff 	bal	0+0010 <text_label\+0x10>
-[ 	]*10: R_MIPS_GNU_REL16_S2	.text
-0+0014 <[^>]*> 00000000 	nop
-0+0018 <[^>]*> 0411ffff 	bal	0+0018 <text_label\+0x18>
-[ 	]*18: R_MIPS_GNU_REL16_S2	external_text_label
-0+001c <[^>]*> 00000000 	nop
-0+0020 <[^>]*> 1000ffff 	b	0+0020 <text_label\+0x20>
-[ 	]*20: R_MIPS_GNU_REL16_S2	.text
-0+0024 <[^>]*> 00000000 	nop
-0+0028 <[^>]*> 1000ffff 	b	0+0028 <text_label\+0x28>
-[ 	]*28: R_MIPS_GNU_REL16_S2	external_text_label
-0+002c <[^>]*> 00000000 	nop
diff --git a/gas/testsuite/gas/mips/jal-empic.d b/gas/testsuite/gas/mips/jal-empic.d
deleted file mode 100644
index 55e71500e1cb..000000000000
--- a/gas/testsuite/gas/mips/jal-empic.d
+++ /dev/null
@@ -1,26 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS jal-empic
-#as: -mips1 -membedded-pic
-#source: jal.s
-
-# Test the jal macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> jalr	t9
-0+0004 <[^>]*> nop
-0+0008 <[^>]*> jalr	a0,t9
-0+000c <[^>]*> nop
-0+0010 <[^>]*> bal	0+0000 <text_label>
-[ 	]*10: PCREL16	.text
-0+0014 <[^>]*> nop
-0+0018 <[^>]*> bal	0+0018 <text_label\+(0x|)18>
-[ 	]*18: PCREL16	external_text_label
-0+001c <[^>]*> nop
-0+0020 <[^>]*> b	0+0000 <text_label>
-[ 	]*20: PCREL16	.text
-0+0024 <[^>]*> nop
-0+0028 <[^>]*> b	0+0028 <text_label\+(0x|)28>
-[ 	]*28: PCREL16	external_text_label
-0+002c <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/jal-range.l b/gas/testsuite/gas/mips/jal-range.l
index 3887e1812c28..309e407c18de 100644
--- a/gas/testsuite/gas/mips/jal-range.l
+++ b/gas/testsuite/gas/mips/jal-range.l
@@ -1,4 +1,4 @@
 .*: Assembler messages:
 .*:4: Error: jump to misaligned address \(0x1\)
 .*:6: Error: jump to misaligned address \(0xfffffff\)
-.*:7: Error: jump address range overflow \(0x10000000\)
+.*:8: Error: jump to misaligned address \(0x10000003\)
diff --git a/gas/testsuite/gas/mips/jal-range.s b/gas/testsuite/gas/mips/jal-range.s
index e52f56024add..cd6cde040f56 100644
--- a/gas/testsuite/gas/mips/jal-range.s
+++ b/gas/testsuite/gas/mips/jal-range.s
@@ -1,7 +1,8 @@
-# Source file use to test border cases of jumps
+# Source file used to test misaligned targets of absolute jumps
 
 	jal	0x0
 	jal	0x1
 	jal	0xffffffc
 	jal	0xfffffff
 	jal	0x10000000
+	jal	0x10000003
diff --git a/gas/testsuite/gas/mips/la-empic.d b/gas/testsuite/gas/mips/la-empic.d
deleted file mode 100644
index 3bee77783ad9..000000000000
--- a/gas/testsuite/gas/mips/la-empic.d
+++ /dev/null
@@ -1,105 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS la-empic
-#as: -32 -mips1 -membedded-pic
-
-# Test the la macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> li	a0,0
-0+0004 <[^>]*> li	a0,1
-0+0008 <[^>]*> li	a0,0x8000
-0+000c <[^>]*> li	a0,-32768
-0+0010 <[^>]*> lui	a0,0x1
-0+0014 <[^>]*> lui	a0,0x1
-0+0018 <[^>]*> ori	a0,a0,0xa5a5
-0+001c <[^>]*> li	a0,0
-0+0020 <[^>]*> addu	a0,a0,a1
-0+0024 <[^>]*> li	a0,1
-0+0028 <[^>]*> addu	a0,a0,a1
-0+002c <[^>]*> li	a0,0x8000
-0+0030 <[^>]*> addu	a0,a0,a1
-0+0034 <[^>]*> li	a0,-32768
-0+0038 <[^>]*> addu	a0,a0,a1
-0+003c <[^>]*> lui	a0,0x1
-0+0040 <[^>]*> addu	a0,a0,a1
-0+0044 <[^>]*> lui	a0,0x1
-0+0048 <[^>]*> ori	a0,a0,0xa5a5
-0+004c <[^>]*> addu	a0,a0,a1
-0+0050 <[^>]*> addiu	a0,gp,-16384
-[ 	]*50: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0054 <[^>]*> addiu	a0,gp,0
-[ 	]*54: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0058 <[^>]*> addiu	a0,gp,0
-[ 	]*58: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+005c <[^>]*> addiu	a0,gp,0
-[ 	]*5c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+0060 <[^>]*> addiu	a0,gp,0
-[ 	]*60: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0064 <[^>]*> addiu	a0,gp,-16384
-[ 	]*64: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0068 <[^>]*> addiu	a0,gp,-15384
-[ 	]*68: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+006c <[^>]*> addiu	a0,gp,-16383
-[ 	]*6c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0070 <[^>]*> addiu	a0,gp,1
-[ 	]*70: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0074 <[^>]*> addiu	a0,gp,1
-[ 	]*74: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+0078 <[^>]*> addiu	a0,gp,1
-[ 	]*78: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+007c <[^>]*> addiu	a0,gp,1
-[ 	]*7c: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0080 <[^>]*> addiu	a0,gp,-16383
-[ 	]*80: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0084 <[^>]*> addiu	a0,gp,-15383
-[ 	]*84: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0088 <[^>]*> addiu	a0,gp,-16384
-[ 	]*88: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+008c <[^>]*> addu	a0,a0,a1
-0+0090 <[^>]*> addiu	a0,gp,0
-[ 	]*90: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0094 <[^>]*> addu	a0,a0,a1
-0+0098 <[^>]*> addiu	a0,gp,0
-[ 	]*98: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+009c <[^>]*> addu	a0,a0,a1
-0+00a0 <[^>]*> addiu	a0,gp,0
-[ 	]*a0: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00a4 <[^>]*> addu	a0,a0,a1
-0+00a8 <[^>]*> addiu	a0,gp,0
-[ 	]*a8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00ac <[^>]*> addu	a0,a0,a1
-0+00b0 <[^>]*> addiu	a0,gp,-16384
-[ 	]*b0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00b4 <[^>]*> addu	a0,a0,a1
-0+00b8 <[^>]*> addiu	a0,gp,-15384
-[ 	]*b8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00bc <[^>]*> addu	a0,a0,a1
-0+00c0 <[^>]*> addiu	a0,gp,-16383
-[ 	]*c0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+00c4 <[^>]*> addu	a0,a0,a1
-0+00c8 <[^>]*> addiu	a0,gp,1
-[ 	]*c8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+00cc <[^>]*> addu	a0,a0,a1
-0+00d0 <[^>]*> addiu	a0,gp,1
-[ 	]*d0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00d4 <[^>]*> addu	a0,a0,a1
-0+00d8 <[^>]*> addiu	a0,gp,1
-[ 	]*d8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00dc <[^>]*> addu	a0,a0,a1
-0+00e0 <[^>]*> addiu	a0,gp,1
-[ 	]*e0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00e4 <[^>]*> addu	a0,a0,a1
-0+00e8 <[^>]*> addiu	a0,gp,-16383
-[ 	]*e8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00ec <[^>]*> addu	a0,a0,a1
-0+00f0 <[^>]*> addiu	a0,gp,-15383
-[ 	]*f0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00f4 <[^>]*> addu	a0,a0,a1
-0+00f8 <[^>]*> lui	a0,0x0
-[ 	]*f8: RELHI	external_text_label
-0+00fc <[^>]*> addiu	a0,a0,252
-[ 	]*fc: RELLO	external_text_label
-0+0100 <[^>]*> li	a0,248
-	...
diff --git a/gas/testsuite/gas/mips/la-empic.s b/gas/testsuite/gas/mips/la-empic.s
deleted file mode 100644
index c6df5e3b5867..000000000000
--- a/gas/testsuite/gas/mips/la-empic.s
+++ /dev/null
@@ -1,57 +0,0 @@
-# Source file used to test the la macro with -membedded-pic
-	
-	.data
-data_label:
-	.extern big_external_data_label,1000
-	.extern small_external_data_label,1
-	.comm big_external_common,1000
-	.comm small_external_common,1
-	.lcomm big_local_common,1000
-	.lcomm small_local_common,1
-	
-	.text
-text_label:	
-	la	$4,0
-	la	$4,1
-	la	$4,0x8000
-	la	$4,-0x8000
-	la	$4,0x10000
-	la	$4,0x1a5a5
-	la	$4,0($5)
-	la	$4,1($5)
-	la	$4,0x8000($5)
-	la	$4,-0x8000($5)
-	la	$4,0x10000($5)
-	la	$4,0x1a5a5($5)
-	la	$4,data_label
-	la	$4,big_external_data_label
-	la	$4,small_external_data_label
-	la	$4,big_external_common
-	la	$4,small_external_common
-	la	$4,big_local_common
-	la	$4,small_local_common
-	la	$4,data_label+1
-	la	$4,big_external_data_label+1
-	la	$4,small_external_data_label+1
-	la	$4,big_external_common+1
-	la	$4,small_external_common+1
-	la	$4,big_local_common+1
-	la	$4,small_local_common+1
-	la	$4,data_label($5)
-	la	$4,big_external_data_label($5)
-	la	$4,small_external_data_label($5)
-	la	$4,big_external_common($5)
-	la	$4,small_external_common($5)
-	la	$4,big_local_common($5)
-	la	$4,small_local_common($5)
-	la	$4,data_label+1($5)
-	la	$4,big_external_data_label+1($5)
-	la	$4,small_external_data_label+1($5)
-	la	$4,big_external_common+1($5)
-	la	$4,small_external_common+1($5)
-	la	$4,big_local_common+1($5)
-	la	$4,small_local_common+1($5)
-
-second_text_label:	
-	la	$4,external_text_label - text_label
-	la	$4,second_text_label - text_label
diff --git a/gas/testsuite/gas/mips/lb-empic.d b/gas/testsuite/gas/mips/lb-empic.d
deleted file mode 100644
index 75cbeb345b82..000000000000
--- a/gas/testsuite/gas/mips/lb-empic.d
+++ /dev/null
@@ -1,102 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS lb-empic
-#as: -32 -mips1 -membedded-pic
-#source: lb-pic.s
-
-# Test the lb macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> lb	a0,0\(zero\)
-0+0004 <[^>]*> lb	a0,1\(zero\)
-0+0008 <[^>]*> lui	a0,0x1
-0+000c <[^>]*> lb	a0,-32768\(a0\)
-0+0010 <[^>]*> lb	a0,-32768\(zero\)
-0+0014 <[^>]*> lui	a0,0x1
-0+0018 <[^>]*> lb	a0,0\(a0\)
-0+001c <[^>]*> lui	a0,0x2
-0+0020 <[^>]*> lb	a0,-23131\(a0\)
-0+0024 <[^>]*> lb	a0,0\(a1\)
-0+0028 <[^>]*> lb	a0,1\(a1\)
-0+002c <[^>]*> lui	a0,0x1
-0+0030 <[^>]*> addu	a0,a0,a1
-0+0034 <[^>]*> lb	a0,-32768\(a0\)
-0+0038 <[^>]*> lb	a0,-32768\(a1\)
-0+003c <[^>]*> lui	a0,0x1
-0+0040 <[^>]*> addu	a0,a0,a1
-0+0044 <[^>]*> lb	a0,0\(a0\)
-0+0048 <[^>]*> lui	a0,0x2
-0+004c <[^>]*> addu	a0,a0,a1
-0+0050 <[^>]*> lb	a0,-23131\(a0\)
-0+0054 <[^>]*> lb	a0,-16384\(gp\)
-[ 	]*54: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0058 <[^>]*> lb	a0,0\(gp\)
-[ 	]*58: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+005c <[^>]*> lb	a0,0\(gp\)
-[ 	]*5c: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+0060 <[^>]*> lb	a0,0\(gp\)
-[ 	]*60: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+0064 <[^>]*> lb	a0,0\(gp\)
-[ 	]*64: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0068 <[^>]*> lb	a0,-16384\(gp\)
-[ 	]*68: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+006c <[^>]*> lb	a0,-15384\(gp\)
-[ 	]*6c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0070 <[^>]*> lb	a0,-16383\(gp\)
-[ 	]*70: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0074 <[^>]*> lb	a0,1\(gp\)
-[ 	]*74: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0078 <[^>]*> lb	a0,1\(gp\)
-[ 	]*78: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+007c <[^>]*> lb	a0,1\(gp\)
-[ 	]*7c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+0080 <[^>]*> lb	a0,1\(gp\)
-[ 	]*80: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0084 <[^>]*> lb	a0,-16383\(gp\)
-[ 	]*84: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0088 <[^>]*> lb	a0,-15383\(gp\)
-[ 	]*88: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+008c <[^>]*> addu	a0,a1,gp
-0+0090 <[^>]*> lb	a0,-16384\(a0\)
-[ 	]*90: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0094 <[^>]*> addu	a0,a1,gp
-0+0098 <[^>]*> lb	a0,0\(a0\)
-[ 	]*98: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+009c <[^>]*> addu	a0,a1,gp
-0+00a0 <[^>]*> lb	a0,0\(a0\)
-[ 	]*a0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00a4 <[^>]*> addu	a0,a1,gp
-0+00a8 <[^>]*> lb	a0,0\(a0\)
-[ 	]*a8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00ac <[^>]*> addu	a0,a1,gp
-0+00b0 <[^>]*> lb	a0,0\(a0\)
-[ 	]*b0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00b4 <[^>]*> addu	a0,a1,gp
-0+00b8 <[^>]*> lb	a0,-16384\(a0\)
-[ 	]*b8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00bc <[^>]*> addu	a0,a1,gp
-0+00c0 <[^>]*> lb	a0,-15384\(a0\)
-[ 	]*c0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00c4 <[^>]*> addu	a0,a1,gp
-0+00c8 <[^>]*> lb	a0,-16383\(a0\)
-[ 	]*c8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+00cc <[^>]*> addu	a0,a1,gp
-0+00d0 <[^>]*> lb	a0,1\(a0\)
-[ 	]*d0: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+00d4 <[^>]*> addu	a0,a1,gp
-0+00d8 <[^>]*> lb	a0,1\(a0\)
-[ 	]*d8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00dc <[^>]*> addu	a0,a1,gp
-0+00e0 <[^>]*> lb	a0,1\(a0\)
-[ 	]*e0: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00e4 <[^>]*> addu	a0,a1,gp
-0+00e8 <[^>]*> lb	a0,1\(a0\)
-[ 	]*e8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00ec <[^>]*> addu	a0,a1,gp
-0+00f0 <[^>]*> lb	a0,-16383\(a0\)
-[ 	]*f0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00f4 <[^>]*> addu	a0,a1,gp
-0+00f8 <[^>]*> lb	a0,-15383\(a0\)
-[ 	]*f8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00fc <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/lb-svr4pic-ilocks.d b/gas/testsuite/gas/mips/lb-svr4pic-ilocks.d
new file mode 100644
index 000000000000..0d7df1ce9d8c
--- /dev/null
+++ b/gas/testsuite/gas/mips/lb-svr4pic-ilocks.d
@@ -0,0 +1,154 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS lb-svr4pic-ilocks
+#as: -32 -KPIC
+#source: lb-pic.s
+
+# Test the lb macro with -KPIC.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> lb	a0,0\(zero\)
+0+0004 <[^>]*> lb	a0,1\(zero\)
+0+0008 <[^>]*> lui	a0,0x1
+0+000c <[^>]*> lb	a0,-32768\(a0\)
+0+0010 <[^>]*> lb	a0,-32768\(zero\)
+0+0014 <[^>]*> lui	a0,0x1
+0+0018 <[^>]*> lb	a0,0\(a0\)
+0+001c <[^>]*> lui	a0,0x2
+0+0020 <[^>]*> lb	a0,-23131\(a0\)
+0+0024 <[^>]*> lb	a0,0\(a1\)
+0+0028 <[^>]*> lb	a0,1\(a1\)
+0+002c <[^>]*> lui	a0,0x1
+0+0030 <[^>]*> addu	a0,a0,a1
+0+0034 <[^>]*> lb	a0,-32768\(a0\)
+0+0038 <[^>]*> lb	a0,-32768\(a1\)
+0+003c <[^>]*> lui	a0,0x1
+0+0040 <[^>]*> addu	a0,a0,a1
+0+0044 <[^>]*> lb	a0,0\(a0\)
+0+0048 <[^>]*> lui	a0,0x2
+0+004c <[^>]*> addu	a0,a0,a1
+0+0050 <[^>]*> lb	a0,-23131\(a0\)
+0+0054 <[^>]*> lw	a0,0\(gp\)
+[ 	]*54: R_MIPS_GOT16	.data
+0+0058 <[^>]*> addiu	a0,a0,0
+[ 	]*58: R_MIPS_LO16	.data
+0+005c <[^>]*> lb	a0,0\(a0\)
+0+0060 <[^>]*> lw	a0,0\(gp\)
+[ 	]*60: R_MIPS_GOT16	big_external_data_label
+0+0064 <[^>]*> lb	a0,0\(a0\)
+0+0068 <[^>]*> lw	a0,0\(gp\)
+[ 	]*68: R_MIPS_GOT16	small_external_data_label
+0+006c <[^>]*> lb	a0,0\(a0\)
+0+0070 <[^>]*> lw	a0,0\(gp\)
+[ 	]*70: R_MIPS_GOT16	big_external_common
+0+0074 <[^>]*> lb	a0,0\(a0\)
+0+0078 <[^>]*> lw	a0,0\(gp\)
+[ 	]*78: R_MIPS_GOT16	small_external_common
+0+007c <[^>]*> lb	a0,0\(a0\)
+0+0080 <[^>]*> lw	a0,0\(gp\)
+[ 	]*80: R_MIPS_GOT16	.bss
+0+0084 <[^>]*> addiu	a0,a0,0
+[ 	]*84: R_MIPS_LO16	.bss
+0+0088 <[^>]*> lb	a0,0\(a0\)
+0+008c <[^>]*> lw	a0,0\(gp\)
+[ 	]*8c: R_MIPS_GOT16	.bss
+0+0090 <[^>]*> addiu	a0,a0,1000
+[ 	]*90: R_MIPS_LO16	.bss
+0+0094 <[^>]*> lb	a0,0\(a0\)
+0+0098 <[^>]*> lw	a0,0\(gp\)
+[ 	]*98: R_MIPS_GOT16	.data
+0+009c <[^>]*> addiu	a0,a0,0
+[ 	]*9c: R_MIPS_LO16	.data
+0+00a0 <[^>]*> lb	a0,1\(a0\)
+0+00a4 <[^>]*> lw	a0,0\(gp\)
+[ 	]*a4: R_MIPS_GOT16	big_external_data_label
+0+00a8 <[^>]*> lb	a0,1\(a0\)
+0+00ac <[^>]*> lw	a0,0\(gp\)
+[ 	]*ac: R_MIPS_GOT16	small_external_data_label
+0+00b0 <[^>]*> lb	a0,1\(a0\)
+0+00b4 <[^>]*> lw	a0,0\(gp\)
+[ 	]*b4: R_MIPS_GOT16	big_external_common
+0+00b8 <[^>]*> lb	a0,1\(a0\)
+0+00bc <[^>]*> lw	a0,0\(gp\)
+[ 	]*bc: R_MIPS_GOT16	small_external_common
+0+00c0 <[^>]*> lb	a0,1\(a0\)
+0+00c4 <[^>]*> lw	a0,0\(gp\)
+[ 	]*c4: R_MIPS_GOT16	.bss
+0+00c8 <[^>]*> addiu	a0,a0,0
+[ 	]*c8: R_MIPS_LO16	.bss
+0+00cc <[^>]*> lb	a0,1\(a0\)
+0+00d0 <[^>]*> lw	a0,0\(gp\)
+[ 	]*d0: R_MIPS_GOT16	.bss
+0+00d4 <[^>]*> addiu	a0,a0,1000
+[ 	]*d4: R_MIPS_LO16	.bss
+0+00d8 <[^>]*> lb	a0,1\(a0\)
+0+00dc <[^>]*> lw	a0,0\(gp\)
+[ 	]*dc: R_MIPS_GOT16	.data
+0+00e0 <[^>]*> addiu	a0,a0,0
+[ 	]*e0: R_MIPS_LO16	.data
+0+00e4 <[^>]*> addu	a0,a0,a1
+0+00e8 <[^>]*> lb	a0,0\(a0\)
+0+00ec <[^>]*> lw	a0,0\(gp\)
+[ 	]*ec: R_MIPS_GOT16	big_external_data_label
+0+00f0 <[^>]*> addu	a0,a0,a1
+0+00f4 <[^>]*> lb	a0,0\(a0\)
+0+00f8 <[^>]*> lw	a0,0\(gp\)
+[ 	]*f8: R_MIPS_GOT16	small_external_data_label
+0+00fc <[^>]*> addu	a0,a0,a1
+0+0100 <[^>]*> lb	a0,0\(a0\)
+0+0104 <[^>]*> lw	a0,0\(gp\)
+[ 	]*104: R_MIPS_GOT16	big_external_common
+0+0108 <[^>]*> addu	a0,a0,a1
+0+010c <[^>]*> lb	a0,0\(a0\)
+0+0110 <[^>]*> lw	a0,0\(gp\)
+[ 	]*110: R_MIPS_GOT16	small_external_common
+0+0114 <[^>]*> addu	a0,a0,a1
+0+0118 <[^>]*> lb	a0,0\(a0\)
+0+011c <[^>]*> lw	a0,0\(gp\)
+[ 	]*11c: R_MIPS_GOT16	.bss
+0+0120 <[^>]*> addiu	a0,a0,0
+[ 	]*120: R_MIPS_LO16	.bss
+0+0124 <[^>]*> addu	a0,a0,a1
+0+0128 <[^>]*> lb	a0,0\(a0\)
+0+012c <[^>]*> lw	a0,0\(gp\)
+[ 	]*12c: R_MIPS_GOT16	.bss
+0+0130 <[^>]*> addiu	a0,a0,1000
+[ 	]*130: R_MIPS_LO16	.bss
+0+0134 <[^>]*> addu	a0,a0,a1
+0+0138 <[^>]*> lb	a0,0\(a0\)
+0+013c <[^>]*> lw	a0,0\(gp\)
+[ 	]*13c: R_MIPS_GOT16	.data
+0+0140 <[^>]*> addiu	a0,a0,0
+[ 	]*140: R_MIPS_LO16	.data
+0+0144 <[^>]*> addu	a0,a0,a1
+0+0148 <[^>]*> lb	a0,1\(a0\)
+0+014c <[^>]*> lw	a0,0\(gp\)
+[ 	]*14c: R_MIPS_GOT16	big_external_data_label
+0+0150 <[^>]*> addu	a0,a0,a1
+0+0154 <[^>]*> lb	a0,1\(a0\)
+0+0158 <[^>]*> lw	a0,0\(gp\)
+[ 	]*158: R_MIPS_GOT16	small_external_data_label
+0+015c <[^>]*> addu	a0,a0,a1
+0+0160 <[^>]*> lb	a0,1\(a0\)
+0+0164 <[^>]*> lw	a0,0\(gp\)
+[ 	]*164: R_MIPS_GOT16	big_external_common
+0+0168 <[^>]*> addu	a0,a0,a1
+0+016c <[^>]*> lb	a0,1\(a0\)
+0+0170 <[^>]*> lw	a0,0\(gp\)
+[ 	]*170: R_MIPS_GOT16	small_external_common
+0+0174 <[^>]*> addu	a0,a0,a1
+0+0178 <[^>]*> lb	a0,1\(a0\)
+0+017c <[^>]*> lw	a0,0\(gp\)
+[ 	]*17c: R_MIPS_GOT16	.bss
+0+0180 <[^>]*> addiu	a0,a0,0
+[ 	]*180: R_MIPS_LO16	.bss
+0+0184 <[^>]*> addu	a0,a0,a1
+0+0188 <[^>]*> lb	a0,1\(a0\)
+0+018c <[^>]*> lw	a0,0\(gp\)
+[ 	]*18c: R_MIPS_GOT16	.bss
+0+0190 <[^>]*> addiu	a0,a0,1000
+[ 	]*190: R_MIPS_LO16	.bss
+0+0194 <[^>]*> addu	a0,a0,a1
+0+0198 <[^>]*> lb	a0,1\(a0\)
+0+019c <[^>]*> nop
diff --git a/gas/testsuite/gas/mips/lb-xgot-ilocks.d b/gas/testsuite/gas/mips/lb-xgot-ilocks.d
index b2632bc4fcad..18e561f0be57 100644
--- a/gas/testsuite/gas/mips/lb-xgot-ilocks.d
+++ b/gas/testsuite/gas/mips/lb-xgot-ilocks.d
@@ -31,184 +31,172 @@ Disassembly of section \.text:
 0+0050 <.*> lb	a0,-23131\(a0\)
 0+0054 <.*> lw	a0,0\(gp\)
 			54: R_MIPS_GOT16	\.data
-0+0058 <.*> nop
-0+005c <.*> addiu	a0,a0,0
-			5c: R_MIPS_LO16	\.data
-0+0060 <.*> lb	a0,0\(a0\)
-0+0064 <.*> lui	a0,0x0
-			64: R_MIPS_GOT_HI16	big_external_data_label
-0+0068 <.*> addu	a0,a0,gp
-0+006c <.*> lw	a0,0\(a0\)
-			6c: R_MIPS_GOT_LO16	big_external_data_label
-0+0070 <.*> lb	a0,0\(a0\)
-0+0074 <.*> lui	a0,0x0
-			74: R_MIPS_GOT_HI16	small_external_data_label
-0+0078 <.*> addu	a0,a0,gp
-0+007c <.*> lw	a0,0\(a0\)
-			7c: R_MIPS_GOT_LO16	small_external_data_label
-0+0080 <.*> lb	a0,0\(a0\)
-0+0084 <.*> lui	a0,0x0
-			84: R_MIPS_GOT_HI16	big_external_common
-0+0088 <.*> addu	a0,a0,gp
-0+008c <.*> lw	a0,0\(a0\)
-			8c: R_MIPS_GOT_LO16	big_external_common
-0+0090 <.*> lb	a0,0\(a0\)
-0+0094 <.*> lui	a0,0x0
-			94: R_MIPS_GOT_HI16	small_external_common
-0+0098 <.*> addu	a0,a0,gp
-0+009c <.*> lw	a0,0\(a0\)
-			9c: R_MIPS_GOT_LO16	small_external_common
-0+00a0 <.*> lb	a0,0\(a0\)
-0+00a4 <.*> lw	a0,0\(gp\)
-			a4: R_MIPS_GOT16	\.bss
-0+00a8 <.*> nop
-0+00ac <.*> addiu	a0,a0,0
-			ac: R_MIPS_LO16	\.bss
-0+00b0 <.*> lb	a0,0\(a0\)
-0+00b4 <.*> lw	a0,0\(gp\)
-			b4: R_MIPS_GOT16	\.bss
-0+00b8 <.*> nop
-0+00bc <.*> addiu	a0,a0,1000
-			bc: R_MIPS_LO16	\.bss
-0+00c0 <.*> lb	a0,0\(a0\)
-0+00c4 <.*> lw	a0,0\(gp\)
-			c4: R_MIPS_GOT16	\.data
-0+00c8 <.*> nop
-0+00cc <.*> addiu	a0,a0,0
-			cc: R_MIPS_LO16	\.data
+0+0058 <.*> addiu	a0,a0,0
+			58: R_MIPS_LO16	\.data
+0+005c <.*> lb	a0,0\(a0\)
+0+0060 <.*> lui	a0,0x0
+			60: R_MIPS_GOT_HI16	big_external_data_label
+0+0064 <.*> addu	a0,a0,gp
+0+0068 <.*> lw	a0,0\(a0\)
+			68: R_MIPS_GOT_LO16	big_external_data_label
+0+006c <.*> lb	a0,0\(a0\)
+0+0070 <.*> lui	a0,0x0
+			70: R_MIPS_GOT_HI16	small_external_data_label
+0+0074 <.*> addu	a0,a0,gp
+0+0078 <.*> lw	a0,0\(a0\)
+			78: R_MIPS_GOT_LO16	small_external_data_label
+0+007c <.*> lb	a0,0\(a0\)
+0+0080 <.*> lui	a0,0x0
+			80: R_MIPS_GOT_HI16	big_external_common
+0+0084 <.*> addu	a0,a0,gp
+0+0088 <.*> lw	a0,0\(a0\)
+			88: R_MIPS_GOT_LO16	big_external_common
+0+008c <.*> lb	a0,0\(a0\)
+0+0090 <.*> lui	a0,0x0
+			90: R_MIPS_GOT_HI16	small_external_common
+0+0094 <.*> addu	a0,a0,gp
+0+0098 <.*> lw	a0,0\(a0\)
+			98: R_MIPS_GOT_LO16	small_external_common
+0+009c <.*> lb	a0,0\(a0\)
+0+00a0 <.*> lw	a0,0\(gp\)
+			a0: R_MIPS_GOT16	\.bss
+0+00a4 <.*> addiu	a0,a0,0
+			a4: R_MIPS_LO16	\.bss
+0+00a8 <.*> lb	a0,0\(a0\)
+0+00ac <.*> lw	a0,0\(gp\)
+			ac: R_MIPS_GOT16	\.bss
+0+00b0 <.*> addiu	a0,a0,1000
+			b0: R_MIPS_LO16	\.bss
+0+00b4 <.*> lb	a0,0\(a0\)
+0+00b8 <.*> lw	a0,0\(gp\)
+			b8: R_MIPS_GOT16	\.data
+0+00bc <.*> addiu	a0,a0,0
+			bc: R_MIPS_LO16	\.data
+0+00c0 <.*> lb	a0,1\(a0\)
+0+00c4 <.*> lui	a0,0x0
+			c4: R_MIPS_GOT_HI16	big_external_data_label
+0+00c8 <.*> addu	a0,a0,gp
+0+00cc <.*> lw	a0,0\(a0\)
+			cc: R_MIPS_GOT_LO16	big_external_data_label
 0+00d0 <.*> lb	a0,1\(a0\)
 0+00d4 <.*> lui	a0,0x0
-			d4: R_MIPS_GOT_HI16	big_external_data_label
+			d4: R_MIPS_GOT_HI16	small_external_data_label
 0+00d8 <.*> addu	a0,a0,gp
 0+00dc <.*> lw	a0,0\(a0\)
-			dc: R_MIPS_GOT_LO16	big_external_data_label
+			dc: R_MIPS_GOT_LO16	small_external_data_label
 0+00e0 <.*> lb	a0,1\(a0\)
 0+00e4 <.*> lui	a0,0x0
-			e4: R_MIPS_GOT_HI16	small_external_data_label
+			e4: R_MIPS_GOT_HI16	big_external_common
 0+00e8 <.*> addu	a0,a0,gp
 0+00ec <.*> lw	a0,0\(a0\)
-			ec: R_MIPS_GOT_LO16	small_external_data_label
+			ec: R_MIPS_GOT_LO16	big_external_common
 0+00f0 <.*> lb	a0,1\(a0\)
 0+00f4 <.*> lui	a0,0x0
-			f4: R_MIPS_GOT_HI16	big_external_common
+			f4: R_MIPS_GOT_HI16	small_external_common
 0+00f8 <.*> addu	a0,a0,gp
 0+00fc <.*> lw	a0,0\(a0\)
-			fc: R_MIPS_GOT_LO16	big_external_common
+			fc: R_MIPS_GOT_LO16	small_external_common
 0+0100 <.*> lb	a0,1\(a0\)
-0+0104 <.*> lui	a0,0x0
-			104: R_MIPS_GOT_HI16	small_external_common
-0+0108 <.*> addu	a0,a0,gp
-0+010c <.*> lw	a0,0\(a0\)
-			10c: R_MIPS_GOT_LO16	small_external_common
-0+0110 <.*> lb	a0,1\(a0\)
-0+0114 <.*> lw	a0,0\(gp\)
-			114: R_MIPS_GOT16	\.bss
-0+0118 <.*> nop
-0+011c <.*> addiu	a0,a0,0
-			11c: R_MIPS_LO16	\.bss
-0+0120 <.*> lb	a0,1\(a0\)
-0+0124 <.*> lw	a0,0\(gp\)
-			124: R_MIPS_GOT16	\.bss
-0+0128 <.*> nop
-0+012c <.*> addiu	a0,a0,1000
-			12c: R_MIPS_LO16	\.bss
-0+0130 <.*> lb	a0,1\(a0\)
-0+0134 <.*> lw	a0,0\(gp\)
-			134: R_MIPS_GOT16	\.data
-0+0138 <.*> nop
-0+013c <.*> addiu	a0,a0,0
-			13c: R_MIPS_LO16	\.data
-0+0140 <.*> addu	a0,a0,a1
-0+0144 <.*> lb	a0,0\(a0\)
-0+0148 <.*> lui	a0,0x0
-			148: R_MIPS_GOT_HI16	big_external_data_label
-0+014c <.*> addu	a0,a0,gp
-0+0150 <.*> lw	a0,0\(a0\)
-			150: R_MIPS_GOT_LO16	big_external_data_label
-0+0154 <.*> addu	a0,a0,a1
-0+0158 <.*> lb	a0,0\(a0\)
-0+015c <.*> lui	a0,0x0
-			15c: R_MIPS_GOT_HI16	small_external_data_label
-0+0160 <.*> addu	a0,a0,gp
-0+0164 <.*> lw	a0,0\(a0\)
-			164: R_MIPS_GOT_LO16	small_external_data_label
-0+0168 <.*> addu	a0,a0,a1
-0+016c <.*> lb	a0,0\(a0\)
-0+0170 <.*> lui	a0,0x0
-			170: R_MIPS_GOT_HI16	big_external_common
-0+0174 <.*> addu	a0,a0,gp
-0+0178 <.*> lw	a0,0\(a0\)
-			178: R_MIPS_GOT_LO16	big_external_common
-0+017c <.*> addu	a0,a0,a1
-0+0180 <.*> lb	a0,0\(a0\)
-0+0184 <.*> lui	a0,0x0
-			184: R_MIPS_GOT_HI16	small_external_common
-0+0188 <.*> addu	a0,a0,gp
-0+018c <.*> lw	a0,0\(a0\)
-			18c: R_MIPS_GOT_LO16	small_external_common
-0+0190 <.*> addu	a0,a0,a1
-0+0194 <.*> lb	a0,0\(a0\)
-0+0198 <.*> lw	a0,0\(gp\)
-			198: R_MIPS_GOT16	\.bss
-0+019c <.*> nop
+0+0104 <.*> lw	a0,0\(gp\)
+			104: R_MIPS_GOT16	\.bss
+0+0108 <.*> addiu	a0,a0,0
+			108: R_MIPS_LO16	\.bss
+0+010c <.*> lb	a0,1\(a0\)
+0+0110 <.*> lw	a0,0\(gp\)
+			110: R_MIPS_GOT16	\.bss
+0+0114 <.*> addiu	a0,a0,1000
+			114: R_MIPS_LO16	\.bss
+0+0118 <.*> lb	a0,1\(a0\)
+0+011c <.*> lw	a0,0\(gp\)
+			11c: R_MIPS_GOT16	\.data
+0+0120 <.*> addiu	a0,a0,0
+			120: R_MIPS_LO16	\.data
+0+0124 <.*> addu	a0,a0,a1
+0+0128 <.*> lb	a0,0\(a0\)
+0+012c <.*> lui	a0,0x0
+			12c: R_MIPS_GOT_HI16	big_external_data_label
+0+0130 <.*> addu	a0,a0,gp
+0+0134 <.*> lw	a0,0\(a0\)
+			134: R_MIPS_GOT_LO16	big_external_data_label
+0+0138 <.*> addu	a0,a0,a1
+0+013c <.*> lb	a0,0\(a0\)
+0+0140 <.*> lui	a0,0x0
+			140: R_MIPS_GOT_HI16	small_external_data_label
+0+0144 <.*> addu	a0,a0,gp
+0+0148 <.*> lw	a0,0\(a0\)
+			148: R_MIPS_GOT_LO16	small_external_data_label
+0+014c <.*> addu	a0,a0,a1
+0+0150 <.*> lb	a0,0\(a0\)
+0+0154 <.*> lui	a0,0x0
+			154: R_MIPS_GOT_HI16	big_external_common
+0+0158 <.*> addu	a0,a0,gp
+0+015c <.*> lw	a0,0\(a0\)
+			15c: R_MIPS_GOT_LO16	big_external_common
+0+0160 <.*> addu	a0,a0,a1
+0+0164 <.*> lb	a0,0\(a0\)
+0+0168 <.*> lui	a0,0x0
+			168: R_MIPS_GOT_HI16	small_external_common
+0+016c <.*> addu	a0,a0,gp
+0+0170 <.*> lw	a0,0\(a0\)
+			170: R_MIPS_GOT_LO16	small_external_common
+0+0174 <.*> addu	a0,a0,a1
+0+0178 <.*> lb	a0,0\(a0\)
+0+017c <.*> lw	a0,0\(gp\)
+			17c: R_MIPS_GOT16	\.bss
+0+0180 <.*> addiu	a0,a0,0
+			180: R_MIPS_LO16	\.bss
+0+0184 <.*> addu	a0,a0,a1
+0+0188 <.*> lb	a0,0\(a0\)
+0+018c <.*> lw	a0,0\(gp\)
+			18c: R_MIPS_GOT16	\.bss
+0+0190 <.*> addiu	a0,a0,1000
+			190: R_MIPS_LO16	\.bss
+0+0194 <.*> addu	a0,a0,a1
+0+0198 <.*> lb	a0,0\(a0\)
+0+019c <.*> lw	a0,0\(gp\)
+			19c: R_MIPS_GOT16	\.data
 0+01a0 <.*> addiu	a0,a0,0
-			1a0: R_MIPS_LO16	\.bss
+			1a0: R_MIPS_LO16	\.data
 0+01a4 <.*> addu	a0,a0,a1
-0+01a8 <.*> lb	a0,0\(a0\)
-0+01ac <.*> lw	a0,0\(gp\)
-			1ac: R_MIPS_GOT16	\.bss
-0+01b0 <.*> nop
-0+01b4 <.*> addiu	a0,a0,1000
-			1b4: R_MIPS_LO16	\.bss
+0+01a8 <.*> lb	a0,1\(a0\)
+0+01ac <.*> lui	a0,0x0
+			1ac: R_MIPS_GOT_HI16	big_external_data_label
+0+01b0 <.*> addu	a0,a0,gp
+0+01b4 <.*> lw	a0,0\(a0\)
+			1b4: R_MIPS_GOT_LO16	big_external_data_label
 0+01b8 <.*> addu	a0,a0,a1
-0+01bc <.*> lb	a0,0\(a0\)
-0+01c0 <.*> lw	a0,0\(gp\)
-			1c0: R_MIPS_GOT16	\.data
-0+01c4 <.*> nop
-0+01c8 <.*> addiu	a0,a0,0
-			1c8: R_MIPS_LO16	\.data
+0+01bc <.*> lb	a0,1\(a0\)
+0+01c0 <.*> lui	a0,0x0
+			1c0: R_MIPS_GOT_HI16	small_external_data_label
+0+01c4 <.*> addu	a0,a0,gp
+0+01c8 <.*> lw	a0,0\(a0\)
+			1c8: R_MIPS_GOT_LO16	small_external_data_label
 0+01cc <.*> addu	a0,a0,a1
 0+01d0 <.*> lb	a0,1\(a0\)
 0+01d4 <.*> lui	a0,0x0
-			1d4: R_MIPS_GOT_HI16	big_external_data_label
+			1d4: R_MIPS_GOT_HI16	big_external_common
 0+01d8 <.*> addu	a0,a0,gp
 0+01dc <.*> lw	a0,0\(a0\)
-			1dc: R_MIPS_GOT_LO16	big_external_data_label
+			1dc: R_MIPS_GOT_LO16	big_external_common
 0+01e0 <.*> addu	a0,a0,a1
 0+01e4 <.*> lb	a0,1\(a0\)
 0+01e8 <.*> lui	a0,0x0
-			1e8: R_MIPS_GOT_HI16	small_external_data_label
+			1e8: R_MIPS_GOT_HI16	small_external_common
 0+01ec <.*> addu	a0,a0,gp
 0+01f0 <.*> lw	a0,0\(a0\)
-			1f0: R_MIPS_GOT_LO16	small_external_data_label
+			1f0: R_MIPS_GOT_LO16	small_external_common
 0+01f4 <.*> addu	a0,a0,a1
 0+01f8 <.*> lb	a0,1\(a0\)
-0+01fc <.*> lui	a0,0x0
-			1fc: R_MIPS_GOT_HI16	big_external_common
-0+0200 <.*> addu	a0,a0,gp
-0+0204 <.*> lw	a0,0\(a0\)
-			204: R_MIPS_GOT_LO16	big_external_common
-0+0208 <.*> addu	a0,a0,a1
-0+020c <.*> lb	a0,1\(a0\)
-0+0210 <.*> lui	a0,0x0
-			210: R_MIPS_GOT_HI16	small_external_common
-0+0214 <.*> addu	a0,a0,gp
-0+0218 <.*> lw	a0,0\(a0\)
-			218: R_MIPS_GOT_LO16	small_external_common
-0+021c <.*> addu	a0,a0,a1
-0+0220 <.*> lb	a0,1\(a0\)
-0+0224 <.*> lw	a0,0\(gp\)
-			224: R_MIPS_GOT16	\.bss
-0+0228 <.*> nop
-0+022c <.*> addiu	a0,a0,0
-			22c: R_MIPS_LO16	\.bss
-0+0230 <.*> addu	a0,a0,a1
-0+0234 <.*> lb	a0,1\(a0\)
-0+0238 <.*> lw	a0,0\(gp\)
-			238: R_MIPS_GOT16	\.bss
-0+023c <.*> nop
-0+0240 <.*> addiu	a0,a0,1000
-			240: R_MIPS_LO16	\.bss
-0+0244 <.*> addu	a0,a0,a1
-0+0248 <.*> lb	a0,1\(a0\)
-0+024c <.*> nop
+0+01fc <.*> lw	a0,0\(gp\)
+			1fc: R_MIPS_GOT16	\.bss
+0+0200 <.*> addiu	a0,a0,0
+			200: R_MIPS_LO16	\.bss
+0+0204 <.*> addu	a0,a0,a1
+0+0208 <.*> lb	a0,1\(a0\)
+0+020c <.*> lw	a0,0\(gp\)
+			20c: R_MIPS_GOT16	\.bss
+0+0210 <.*> addiu	a0,a0,1000
+			210: R_MIPS_LO16	\.bss
+0+0214 <.*> addu	a0,a0,a1
+0+0218 <.*> lb	a0,1\(a0\)
+0+021c <.*> nop
diff --git a/gas/testsuite/gas/mips/ld-empic.d b/gas/testsuite/gas/mips/ld-empic.d
deleted file mode 100644
index 85c8358ece55..000000000000
--- a/gas/testsuite/gas/mips/ld-empic.d
+++ /dev/null
@@ -1,186 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS ld-empic
-#as: -32 -mips1 -membedded-pic --defsym EMPIC=1
-#source: ld-pic.s
-
-# Test the ld macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> lw	a0,0\(zero\)
-0+0004 <[^>]*> lw	a1,4\(zero\)
-0+0008 <[^>]*> lw	a0,1\(zero\)
-0+000c <[^>]*> lw	a1,5\(zero\)
-0+0010 <[^>]*> lui	at,0x1
-0+0014 <[^>]*> lw	a0,-32768\(at\)
-0+0018 <[^>]*> lw	a1,-32764\(at\)
-0+001c <[^>]*> lw	a0,-32768\(zero\)
-0+0020 <[^>]*> lw	a1,-32764\(zero\)
-0+0024 <[^>]*> lui	at,0x1
-0+0028 <[^>]*> lw	a0,0\(at\)
-0+002c <[^>]*> lw	a1,4\(at\)
-0+0030 <[^>]*> lui	at,0x2
-0+0034 <[^>]*> lw	a0,-23131\(at\)
-0+0038 <[^>]*> lw	a1,-23127\(at\)
-0+003c <[^>]*> nop
-0+0040 <[^>]*> lw	a0,0\(a1\)
-0+0044 <[^>]*> lw	a1,4\(a1\)
-0+0048 <[^>]*> nop
-0+004c <[^>]*> lw	a0,1\(a1\)
-0+0050 <[^>]*> lw	a1,5\(a1\)
-0+0054 <[^>]*> lui	at,0x1
-0+0058 <[^>]*> addu	at,a1,at
-0+005c <[^>]*> lw	a0,-32768\(at\)
-0+0060 <[^>]*> lw	a1,-32764\(at\)
-0+0064 <[^>]*> nop
-0+0068 <[^>]*> lw	a0,-32768\(a1\)
-0+006c <[^>]*> lw	a1,-32764\(a1\)
-0+0070 <[^>]*> lui	at,0x1
-0+0074 <[^>]*> addu	at,a1,at
-0+0078 <[^>]*> lw	a0,0\(at\)
-0+007c <[^>]*> lw	a1,4\(at\)
-0+0080 <[^>]*> lui	at,0x2
-0+0084 <[^>]*> addu	at,a1,at
-0+0088 <[^>]*> lw	a0,-23131\(at\)
-0+008c <[^>]*> lw	a1,-23127\(at\)
-0+0090 <[^>]*> lw	a0,-16384\(gp\)
-[ 	]*90: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0094 <[^>]*> lw	a1,-16380\(gp\)
-[ 	]*94: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0098 <[^>]*> lw	a0,0\(gp\)
-[ 	]*98: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+009c <[^>]*> lw	a1,4\(gp\)
-[ 	]*9c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+00a0 <[^>]*> lw	a0,0\(gp\)
-[ 	]*a0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00a4 <[^>]*> lw	a1,4\(gp\)
-[ 	]*a4: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00a8 <[^>]*> lw	a0,0\(gp\)
-[ 	]*a8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00ac <[^>]*> lw	a1,4\(gp\)
-[ 	]*ac: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00b0 <[^>]*> lw	a0,0\(gp\)
-[ 	]*b0: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00b4 <[^>]*> lw	a1,4\(gp\)
-[ 	]*b4: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00b8 <[^>]*> lw	a0,-16384\(gp\)
-[ 	]*b8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00bc <[^>]*> lw	a1,-16380\(gp\)
-[ 	]*bc: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00c0 <[^>]*> lw	a0,-15384\(gp\)
-[ 	]*c0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00c4 <[^>]*> lw	a1,-15380\(gp\)
-[ 	]*c4: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00c8 <[^>]*> lw	a0,-16383\(gp\)
-[ 	]*c8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+00cc <[^>]*> lw	a1,-16379\(gp\)
-[ 	]*cc: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+00d0 <[^>]*> lw	a0,1\(gp\)
-[ 	]*d0: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+00d4 <[^>]*> lw	a1,5\(gp\)
-[ 	]*d4: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+00d8 <[^>]*> lw	a0,1\(gp\)
-[ 	]*d8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00dc <[^>]*> lw	a1,5\(gp\)
-[ 	]*dc: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00e0 <[^>]*> lw	a0,1\(gp\)
-[ 	]*e0: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00e4 <[^>]*> lw	a1,5\(gp\)
-[ 	]*e4: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00e8 <[^>]*> lw	a0,1\(gp\)
-[ 	]*e8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00ec <[^>]*> lw	a1,5\(gp\)
-[ 	]*ec: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00f0 <[^>]*> lw	a0,-16383\(gp\)
-[ 	]*f0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00f4 <[^>]*> lw	a1,-16379\(gp\)
-[ 	]*f4: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00f8 <[^>]*> lw	a0,-15383\(gp\)
-[ 	]*f8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00fc <[^>]*> lw	a1,-15379\(gp\)
-[ 	]*fc: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0100 <[^>]*> nop
-0+0104 <[^>]*> addu	at,a1,gp
-0+0108 <[^>]*> lw	a0,-16384\(at\)
-[ 	]*108: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+010c <[^>]*> lw	a1,-16380\(at\)
-[ 	]*10c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0110 <[^>]*> nop
-0+0114 <[^>]*> addu	at,a1,gp
-0+0118 <[^>]*> lw	a0,0\(at\)
-[ 	]*118: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+011c <[^>]*> lw	a1,4\(at\)
-[ 	]*11c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0120 <[^>]*> nop
-0+0124 <[^>]*> addu	at,a1,gp
-0+0128 <[^>]*> lw	a0,0\(at\)
-[ 	]*128: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+012c <[^>]*> lw	a1,4\(at\)
-[ 	]*12c: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+0130 <[^>]*> nop
-0+0134 <[^>]*> addu	at,a1,gp
-0+0138 <[^>]*> lw	a0,0\(at\)
-[ 	]*138: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+013c <[^>]*> lw	a1,4\(at\)
-[ 	]*13c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+0140 <[^>]*> nop
-0+0144 <[^>]*> addu	at,a1,gp
-0+0148 <[^>]*> lw	a0,0\(at\)
-[ 	]*148: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+014c <[^>]*> lw	a1,4\(at\)
-[ 	]*14c: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0150 <[^>]*> nop
-0+0154 <[^>]*> addu	at,a1,gp
-0+0158 <[^>]*> lw	a0,-16384\(at\)
-[ 	]*158: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+015c <[^>]*> lw	a1,-16380\(at\)
-[ 	]*15c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0160 <[^>]*> nop
-0+0164 <[^>]*> addu	at,a1,gp
-0+0168 <[^>]*> lw	a0,-15384\(at\)
-[ 	]*168: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+016c <[^>]*> lw	a1,-15380\(at\)
-[ 	]*16c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0170 <[^>]*> nop
-0+0174 <[^>]*> addu	at,a1,gp
-0+0178 <[^>]*> lw	a0,-16383\(at\)
-[ 	]*178: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+017c <[^>]*> lw	a1,-16379\(at\)
-[ 	]*17c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0180 <[^>]*> nop
-0+0184 <[^>]*> addu	at,a1,gp
-0+0188 <[^>]*> lw	a0,1\(at\)
-[ 	]*188: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+018c <[^>]*> lw	a1,5\(at\)
-[ 	]*18c: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0190 <[^>]*> nop
-0+0194 <[^>]*> addu	at,a1,gp
-0+0198 <[^>]*> lw	a0,1\(at\)
-[ 	]*198: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+019c <[^>]*> lw	a1,5\(at\)
-[ 	]*19c: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+01a0 <[^>]*> nop
-0+01a4 <[^>]*> addu	at,a1,gp
-0+01a8 <[^>]*> lw	a0,1\(at\)
-[ 	]*1a8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+01ac <[^>]*> lw	a1,5\(at\)
-[ 	]*1ac: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+01b0 <[^>]*> nop
-0+01b4 <[^>]*> addu	at,a1,gp
-0+01b8 <[^>]*> lw	a0,1\(at\)
-[ 	]*1b8: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+01bc <[^>]*> lw	a1,5\(at\)
-[ 	]*1bc: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+01c0 <[^>]*> nop
-0+01c4 <[^>]*> addu	at,a1,gp
-0+01c8 <[^>]*> lw	a0,-16383\(at\)
-[ 	]*1c8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+01cc <[^>]*> lw	a1,-16379\(at\)
-[ 	]*1cc: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+01d0 <[^>]*> nop
-0+01d4 <[^>]*> addu	at,a1,gp
-0+01d8 <[^>]*> lw	a0,-15383\(at\)
-[ 	]*1d8: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+01dc <[^>]*> lw	a1,-15379\(at\)
-[ 	]*1dc: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
diff --git a/gas/testsuite/gas/mips/ld-pic.s b/gas/testsuite/gas/mips/ld-pic.s
index ccf52dfcb48f..994561fd74d3 100644
--- a/gas/testsuite/gas/mips/ld-pic.s
+++ b/gas/testsuite/gas/mips/ld-pic.s
@@ -54,7 +54,5 @@ data_label:
 	ld	$4,small_local_common+1($5)
 
 # Round to a 16 byte boundary, for ease in testing multiple targets.
-	.ifndef	EMPIC
 	nop
 	nop
-	.endif
diff --git a/gas/testsuite/gas/mips/ldstla-32-1.l b/gas/testsuite/gas/mips/ldstla-32-1.l
new file mode 100644
index 000000000000..264b616dd18a
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-1.l
@@ -0,0 +1,81 @@
+.*: Assembler messages:
+.*:3: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:5: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:6: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:7: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:10: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:12: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:13: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:14: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:17: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:19: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:20: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:21: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:24: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:26: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:27: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:28: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:31: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:33: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:33: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:34: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:34: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:35: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:35: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:38: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:40: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:40: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:41: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:41: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:42: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:42: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:45: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:47: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:47: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:48: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:48: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:49: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:49: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:52: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:54: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:54: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:55: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:55: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:56: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:56: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:59: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:60: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:61: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:62: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:63: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:64: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:66: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:67: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:68: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:69: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:70: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:71: Error: Number \(0x0*100000000\) larger than 32 bits
diff --git a/gas/testsuite/gas/mips/ldstla-32-1.s b/gas/testsuite/gas/mips/ldstla-32-1.s
new file mode 100644
index 000000000000..2037e33fce78
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-1.s
@@ -0,0 +1,73 @@
+
+	.text
+	ld $2, 0xfffffffeffffffff($4)
+	ld $2, 0xfffffffe00000000($4)
+	ld $2, 0xabcdef0123456789($4)
+	ld $2, 0x0123456789abcdef($4)
+	ld $2, 0x00000001ffffffff($4)
+	ld $2, 0x0000000100000000($4)
+
+	ld $2, 0xfffffffeffffffff
+	ld $2, 0xfffffffe00000000
+	ld $2, 0xabcdef0123456789
+	ld $2, 0x0123456789abcdef
+	ld $2, 0x00000001ffffffff
+	ld $2, 0x0000000100000000
+
+	sd $2, 0xfffffffeffffffff($4)
+	sd $2, 0xfffffffe00000000($4)
+	sd $2, 0xabcdef0123456789($4)
+	sd $2, 0x0123456789abcdef($4)
+	sd $2, 0x00000001ffffffff($4)
+	sd $2, 0x0000000100000000($4)
+
+	sd $2, 0xfffffffeffffffff
+	sd $2, 0xfffffffe00000000
+	sd $2, 0xabcdef0123456789
+	sd $2, 0x0123456789abcdef
+	sd $2, 0x00000001ffffffff
+	sd $2, 0x0000000100000000
+
+	lw $2, 0xfffffffeffffffff($4)
+	lw $2, 0xfffffffe00000000($4)
+	lw $2, 0xabcdef0123456789($4)
+	lw $2, 0x0123456789abcdef($4)
+	lw $2, 0x00000001ffffffff($4)
+	lw $2, 0x0000000100000000($4)
+
+	lw $2, 0xfffffffeffffffff
+	lw $2, 0xfffffffe00000000
+	lw $2, 0xabcdef0123456789
+	lw $2, 0x0123456789abcdef
+	lw $2, 0x00000001ffffffff
+	lw $2, 0x0000000100000000
+
+	sw $2, 0xfffffffeffffffff($4)
+	sw $2, 0xfffffffe00000000($4)
+	sw $2, 0xabcdef0123456789($4)
+	sw $2, 0x0123456789abcdef($4)
+	sw $2, 0x00000001ffffffff($4)
+	sw $2, 0x0000000100000000($4)
+
+	sw $2, 0xfffffffeffffffff
+	sw $2, 0xfffffffe00000000
+	sw $2, 0xabcdef0123456789
+	sw $2, 0x0123456789abcdef
+	sw $2, 0x00000001ffffffff
+	sw $2, 0x0000000100000000
+
+	la $2, 0xfffffffeffffffff($4)
+	la $2, 0xfffffffe00000000($4)
+	la $2, 0xabcdef0123456789($4)
+	la $2, 0x0123456789abcdef($4)
+	la $2, 0x00000001ffffffff($4)
+	la $2, 0x0000000100000000($4)
+
+	la $2, 0xfffffffeffffffff
+	la $2, 0xfffffffe00000000
+	la $2, 0xabcdef0123456789
+	la $2, 0x0123456789abcdef
+	la $2, 0x00000001ffffffff
+	la $2, 0x0000000100000000
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/ldstla-32-mips3-1.l b/gas/testsuite/gas/mips/ldstla-32-mips3-1.l
new file mode 100644
index 000000000000..3ac34975cce8
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-mips3-1.l
@@ -0,0 +1,101 @@
+.*: Assembler messages:
+.*:3: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:5: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:5: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:6: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:6: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:7: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:7: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:10: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:12: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:12: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:13: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:13: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:14: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:14: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:17: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:19: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:19: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:20: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:20: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:21: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:21: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:24: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:26: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:26: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:27: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:27: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:28: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:28: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:31: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:33: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:33: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:34: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:34: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:35: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:35: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:38: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:40: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:40: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:41: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:41: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:42: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:42: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:45: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:47: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:47: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:48: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:48: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:49: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:49: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:52: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:54: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:54: Error: Number \(0xabcdef0123450000\) larger than 32 bits
+.*:55: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:55: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
+.*:56: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:56: Error: Number \(0x0*200000000\) larger than 32 bits
+.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:59: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:60: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:61: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:62: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:63: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:64: Error: Number \(0x0*100000000\) larger than 32 bits
+.*:66: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
+.*:67: Error: Number \(0xfffffffe00000000\) larger than 32 bits
+.*:68: Error: Number \(0xabcdef0123456789\) larger than 32 bits
+.*:69: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
+.*:70: Error: Number \(0x0*1ffffffff\) larger than 32 bits
+.*:71: Error: Number \(0x0*100000000\) larger than 32 bits
diff --git a/gas/testsuite/gas/mips/ldstla-32-mips3-1.s b/gas/testsuite/gas/mips/ldstla-32-mips3-1.s
new file mode 100644
index 000000000000..4b3d6539cb1b
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-mips3-1.s
@@ -0,0 +1,73 @@
+	.set	mips3
+	.text
+	ld $2, 0xfffffffeffffffff($4)
+	ld $2, 0xfffffffe00000000($4)
+	ld $2, 0xabcdef0123456789($4)
+	ld $2, 0x0123456789abcdef($4)
+	ld $2, 0x00000001ffffffff($4)
+	ld $2, 0x0000000100000000($4)
+
+	ld $2, 0xfffffffeffffffff
+	ld $2, 0xfffffffe00000000
+	ld $2, 0xabcdef0123456789
+	ld $2, 0x0123456789abcdef
+	ld $2, 0x00000001ffffffff
+	ld $2, 0x0000000100000000
+
+	sd $2, 0xfffffffeffffffff($4)
+	sd $2, 0xfffffffe00000000($4)
+	sd $2, 0xabcdef0123456789($4)
+	sd $2, 0x0123456789abcdef($4)
+	sd $2, 0x00000001ffffffff($4)
+	sd $2, 0x0000000100000000($4)
+
+	sd $2, 0xfffffffeffffffff
+	sd $2, 0xfffffffe00000000
+	sd $2, 0xabcdef0123456789
+	sd $2, 0x0123456789abcdef
+	sd $2, 0x00000001ffffffff
+	sd $2, 0x0000000100000000
+
+	lw $2, 0xfffffffeffffffff($4)
+	lw $2, 0xfffffffe00000000($4)
+	lw $2, 0xabcdef0123456789($4)
+	lw $2, 0x0123456789abcdef($4)
+	lw $2, 0x00000001ffffffff($4)
+	lw $2, 0x0000000100000000($4)
+
+	lw $2, 0xfffffffeffffffff
+	lw $2, 0xfffffffe00000000
+	lw $2, 0xabcdef0123456789
+	lw $2, 0x0123456789abcdef
+	lw $2, 0x00000001ffffffff
+	lw $2, 0x0000000100000000
+
+	sw $2, 0xfffffffeffffffff($4)
+	sw $2, 0xfffffffe00000000($4)
+	sw $2, 0xabcdef0123456789($4)
+	sw $2, 0x0123456789abcdef($4)
+	sw $2, 0x00000001ffffffff($4)
+	sw $2, 0x0000000100000000($4)
+
+	sw $2, 0xfffffffeffffffff
+	sw $2, 0xfffffffe00000000
+	sw $2, 0xabcdef0123456789
+	sw $2, 0x0123456789abcdef
+	sw $2, 0x00000001ffffffff
+	sw $2, 0x0000000100000000
+
+	la $2, 0xfffffffeffffffff($4)
+	la $2, 0xfffffffe00000000($4)
+	la $2, 0xabcdef0123456789($4)
+	la $2, 0x0123456789abcdef($4)
+	la $2, 0x00000001ffffffff($4)
+	la $2, 0x0000000100000000($4)
+
+	la $2, 0xfffffffeffffffff
+	la $2, 0xfffffffe00000000
+	la $2, 0xabcdef0123456789
+	la $2, 0x0123456789abcdef
+	la $2, 0x00000001ffffffff
+	la $2, 0x0000000100000000
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/ldstla-32-mips3-shared.d b/gas/testsuite/gas/mips/ldstla-32-mips3-shared.d
new file mode 100644
index 000000000000..11bca35d6c48
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-mips3-shared.d
@@ -0,0 +1,271 @@
+#objdump: -d -mmips:4000
+#as: -KPIC -mabi=32
+#name: MIPS ld-st-la constants (ABI o32, mips3, shared)
+#source: ldstla-32-mips3.s
+
+.*: +file format elf32-.*mips
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	dc82ffff 	ld	v0,-1\(a0\)
+   4:	3c02abce 	lui	v0,0xabce
+   8:	00441021 	addu	v0,v0,a0
+   c:	dc42ef01 	ld	v0,-4351\(v0\)
+  10:	3c028000 	lui	v0,0x8000
+  14:	00441021 	addu	v0,v0,a0
+  18:	dc420000 	ld	v0,0\(v0\)
+  1c:	3c028000 	lui	v0,0x8000
+  20:	00441021 	addu	v0,v0,a0
+  24:	dc42ffff 	ld	v0,-1\(v0\)
+  28:	3c020123 	lui	v0,0x123
+  2c:	00441021 	addu	v0,v0,a0
+  30:	dc424567 	ld	v0,17767\(v0\)
+  34:	24020000 	li	v0,0
+  38:	00441021 	addu	v0,v0,a0
+  3c:	dc420000 	ld	v0,0\(v0\)
+  40:	24020000 	li	v0,0
+  44:	00441021 	addu	v0,v0,a0
+  48:	dc42ffff 	ld	v0,-1\(v0\)
+  4c:	3c02abce 	lui	v0,0xabce
+  50:	00441021 	addu	v0,v0,a0
+  54:	dc42ef01 	ld	v0,-4351\(v0\)
+  58:	3c028000 	lui	v0,0x8000
+  5c:	00441021 	addu	v0,v0,a0
+  60:	dc420000 	ld	v0,0\(v0\)
+  64:	3c028000 	lui	v0,0x8000
+  68:	00441021 	addu	v0,v0,a0
+  6c:	dc42ffff 	ld	v0,-1\(v0\)
+  70:	3c020123 	lui	v0,0x123
+  74:	00441021 	addu	v0,v0,a0
+  78:	dc424567 	ld	v0,17767\(v0\)
+  7c:	dc820000 	ld	v0,0\(a0\)
+  80:	dc02ffff 	ld	v0,-1\(zero\)
+  84:	3c02abce 	lui	v0,0xabce
+  88:	dc42ef01 	ld	v0,-4351\(v0\)
+  8c:	3c028000 	lui	v0,0x8000
+  90:	dc420000 	ld	v0,0\(v0\)
+  94:	3c028000 	lui	v0,0x8000
+  98:	dc42ffff 	ld	v0,-1\(v0\)
+  9c:	3c020123 	lui	v0,0x123
+  a0:	dc424567 	ld	v0,17767\(v0\)
+  a4:	24020000 	li	v0,0
+  a8:	dc420000 	ld	v0,0\(v0\)
+  ac:	24020000 	li	v0,0
+  b0:	dc42ffff 	ld	v0,-1\(v0\)
+  b4:	3c02abce 	lui	v0,0xabce
+  b8:	dc42ef01 	ld	v0,-4351\(v0\)
+  bc:	3c028000 	lui	v0,0x8000
+  c0:	dc420000 	ld	v0,0\(v0\)
+  c4:	3c028000 	lui	v0,0x8000
+  c8:	dc42ffff 	ld	v0,-1\(v0\)
+  cc:	3c020123 	lui	v0,0x123
+  d0:	dc424567 	ld	v0,17767\(v0\)
+  d4:	dc020000 	ld	v0,0\(zero\)
+  d8:	fc82ffff 	sd	v0,-1\(a0\)
+  dc:	3c01abce 	lui	at,0xabce
+  e0:	00240821 	addu	at,at,a0
+  e4:	fc22ef01 	sd	v0,-4351\(at\)
+  e8:	3c018000 	lui	at,0x8000
+  ec:	00240821 	addu	at,at,a0
+  f0:	fc220000 	sd	v0,0\(at\)
+  f4:	3c018000 	lui	at,0x8000
+  f8:	00240821 	addu	at,at,a0
+  fc:	fc22ffff 	sd	v0,-1\(at\)
+ 100:	3c010123 	lui	at,0x123
+ 104:	00240821 	addu	at,at,a0
+ 108:	fc224567 	sd	v0,17767\(at\)
+ 10c:	24010000 	li	at,0
+ 110:	00240821 	addu	at,at,a0
+ 114:	fc220000 	sd	v0,0\(at\)
+ 118:	24010000 	li	at,0
+ 11c:	00240821 	addu	at,at,a0
+ 120:	fc22ffff 	sd	v0,-1\(at\)
+ 124:	3c01abce 	lui	at,0xabce
+ 128:	00240821 	addu	at,at,a0
+ 12c:	fc22ef01 	sd	v0,-4351\(at\)
+ 130:	3c018000 	lui	at,0x8000
+ 134:	00240821 	addu	at,at,a0
+ 138:	fc220000 	sd	v0,0\(at\)
+ 13c:	3c018000 	lui	at,0x8000
+ 140:	00240821 	addu	at,at,a0
+ 144:	fc22ffff 	sd	v0,-1\(at\)
+ 148:	3c010123 	lui	at,0x123
+ 14c:	00240821 	addu	at,at,a0
+ 150:	fc224567 	sd	v0,17767\(at\)
+ 154:	fc820000 	sd	v0,0\(a0\)
+ 158:	fc02ffff 	sd	v0,-1\(zero\)
+ 15c:	3c01abce 	lui	at,0xabce
+ 160:	fc22ef01 	sd	v0,-4351\(at\)
+ 164:	3c018000 	lui	at,0x8000
+ 168:	fc220000 	sd	v0,0\(at\)
+ 16c:	3c018000 	lui	at,0x8000
+ 170:	fc22ffff 	sd	v0,-1\(at\)
+ 174:	3c010123 	lui	at,0x123
+ 178:	fc224567 	sd	v0,17767\(at\)
+ 17c:	24010000 	li	at,0
+ 180:	fc220000 	sd	v0,0\(at\)
+ 184:	24010000 	li	at,0
+ 188:	fc22ffff 	sd	v0,-1\(at\)
+ 18c:	3c01abce 	lui	at,0xabce
+ 190:	fc22ef01 	sd	v0,-4351\(at\)
+ 194:	3c018000 	lui	at,0x8000
+ 198:	fc220000 	sd	v0,0\(at\)
+ 19c:	3c018000 	lui	at,0x8000
+ 1a0:	fc22ffff 	sd	v0,-1\(at\)
+ 1a4:	3c010123 	lui	at,0x123
+ 1a8:	fc224567 	sd	v0,17767\(at\)
+ 1ac:	fc020000 	sd	v0,0\(zero\)
+ 1b0:	8c82ffff 	lw	v0,-1\(a0\)
+ 1b4:	3c02abce 	lui	v0,0xabce
+ 1b8:	00441021 	addu	v0,v0,a0
+ 1bc:	8c42ef01 	lw	v0,-4351\(v0\)
+ 1c0:	3c028000 	lui	v0,0x8000
+ 1c4:	00441021 	addu	v0,v0,a0
+ 1c8:	8c420000 	lw	v0,0\(v0\)
+ 1cc:	3c028000 	lui	v0,0x8000
+ 1d0:	00441021 	addu	v0,v0,a0
+ 1d4:	8c42ffff 	lw	v0,-1\(v0\)
+ 1d8:	3c020123 	lui	v0,0x123
+ 1dc:	00441021 	addu	v0,v0,a0
+ 1e0:	8c424567 	lw	v0,17767\(v0\)
+ 1e4:	24020000 	li	v0,0
+ 1e8:	00441021 	addu	v0,v0,a0
+ 1ec:	8c420000 	lw	v0,0\(v0\)
+ 1f0:	24020000 	li	v0,0
+ 1f4:	00441021 	addu	v0,v0,a0
+ 1f8:	8c42ffff 	lw	v0,-1\(v0\)
+ 1fc:	3c02abce 	lui	v0,0xabce
+ 200:	00441021 	addu	v0,v0,a0
+ 204:	8c42ef01 	lw	v0,-4351\(v0\)
+ 208:	3c028000 	lui	v0,0x8000
+ 20c:	00441021 	addu	v0,v0,a0
+ 210:	8c420000 	lw	v0,0\(v0\)
+ 214:	3c028000 	lui	v0,0x8000
+ 218:	00441021 	addu	v0,v0,a0
+ 21c:	8c42ffff 	lw	v0,-1\(v0\)
+ 220:	3c020123 	lui	v0,0x123
+ 224:	00441021 	addu	v0,v0,a0
+ 228:	8c424567 	lw	v0,17767\(v0\)
+ 22c:	8c820000 	lw	v0,0\(a0\)
+ 230:	8c02ffff 	lw	v0,-1\(zero\)
+ 234:	3c02abce 	lui	v0,0xabce
+ 238:	8c42ef01 	lw	v0,-4351\(v0\)
+ 23c:	3c028000 	lui	v0,0x8000
+ 240:	8c420000 	lw	v0,0\(v0\)
+ 244:	3c028000 	lui	v0,0x8000
+ 248:	8c42ffff 	lw	v0,-1\(v0\)
+ 24c:	3c020123 	lui	v0,0x123
+ 250:	8c424567 	lw	v0,17767\(v0\)
+ 254:	24020000 	li	v0,0
+ 258:	8c420000 	lw	v0,0\(v0\)
+ 25c:	24020000 	li	v0,0
+ 260:	8c42ffff 	lw	v0,-1\(v0\)
+ 264:	3c02abce 	lui	v0,0xabce
+ 268:	8c42ef01 	lw	v0,-4351\(v0\)
+ 26c:	3c028000 	lui	v0,0x8000
+ 270:	8c420000 	lw	v0,0\(v0\)
+ 274:	3c028000 	lui	v0,0x8000
+ 278:	8c42ffff 	lw	v0,-1\(v0\)
+ 27c:	3c020123 	lui	v0,0x123
+ 280:	8c424567 	lw	v0,17767\(v0\)
+ 284:	8c020000 	lw	v0,0\(zero\)
+ 288:	ac82ffff 	sw	v0,-1\(a0\)
+ 28c:	3c01abce 	lui	at,0xabce
+ 290:	00240821 	addu	at,at,a0
+ 294:	ac22ef01 	sw	v0,-4351\(at\)
+ 298:	3c018000 	lui	at,0x8000
+ 29c:	00240821 	addu	at,at,a0
+ 2a0:	ac220000 	sw	v0,0\(at\)
+ 2a4:	3c018000 	lui	at,0x8000
+ 2a8:	00240821 	addu	at,at,a0
+ 2ac:	ac22ffff 	sw	v0,-1\(at\)
+ 2b0:	3c010123 	lui	at,0x123
+ 2b4:	00240821 	addu	at,at,a0
+ 2b8:	ac224567 	sw	v0,17767\(at\)
+ 2bc:	24010000 	li	at,0
+ 2c0:	00240821 	addu	at,at,a0
+ 2c4:	ac220000 	sw	v0,0\(at\)
+ 2c8:	24010000 	li	at,0
+ 2cc:	00240821 	addu	at,at,a0
+ 2d0:	ac22ffff 	sw	v0,-1\(at\)
+ 2d4:	3c01abce 	lui	at,0xabce
+ 2d8:	00240821 	addu	at,at,a0
+ 2dc:	ac22ef01 	sw	v0,-4351\(at\)
+ 2e0:	3c018000 	lui	at,0x8000
+ 2e4:	00240821 	addu	at,at,a0
+ 2e8:	ac220000 	sw	v0,0\(at\)
+ 2ec:	3c018000 	lui	at,0x8000
+ 2f0:	00240821 	addu	at,at,a0
+ 2f4:	ac22ffff 	sw	v0,-1\(at\)
+ 2f8:	3c010123 	lui	at,0x123
+ 2fc:	00240821 	addu	at,at,a0
+ 300:	ac224567 	sw	v0,17767\(at\)
+ 304:	ac820000 	sw	v0,0\(a0\)
+ 308:	ac02ffff 	sw	v0,-1\(zero\)
+ 30c:	3c01abce 	lui	at,0xabce
+ 310:	ac22ef01 	sw	v0,-4351\(at\)
+ 314:	3c018000 	lui	at,0x8000
+ 318:	ac220000 	sw	v0,0\(at\)
+ 31c:	3c018000 	lui	at,0x8000
+ 320:	ac22ffff 	sw	v0,-1\(at\)
+ 324:	3c010123 	lui	at,0x123
+ 328:	ac224567 	sw	v0,17767\(at\)
+ 32c:	24010000 	li	at,0
+ 330:	ac220000 	sw	v0,0\(at\)
+ 334:	24010000 	li	at,0
+ 338:	ac22ffff 	sw	v0,-1\(at\)
+ 33c:	3c01abce 	lui	at,0xabce
+ 340:	ac22ef01 	sw	v0,-4351\(at\)
+ 344:	3c018000 	lui	at,0x8000
+ 348:	ac220000 	sw	v0,0\(at\)
+ 34c:	3c018000 	lui	at,0x8000
+ 350:	ac22ffff 	sw	v0,-1\(at\)
+ 354:	3c010123 	lui	at,0x123
+ 358:	ac224567 	sw	v0,17767\(at\)
+ 35c:	ac020000 	sw	v0,0\(zero\)
+ 360:	2482ffff 	addiu	v0,a0,-1
+ 364:	3c02abcd 	lui	v0,0xabcd
+ 368:	3442ef01 	ori	v0,v0,0xef01
+ 36c:	00441021 	addu	v0,v0,a0
+ 370:	3c028000 	lui	v0,0x8000
+ 374:	00441021 	addu	v0,v0,a0
+ 378:	3c027fff 	lui	v0,0x7fff
+ 37c:	3442ffff 	ori	v0,v0,0xffff
+ 380:	00441021 	addu	v0,v0,a0
+ 384:	3c020123 	lui	v0,0x123
+ 388:	34424567 	ori	v0,v0,0x4567
+ 38c:	00441021 	addu	v0,v0,a0
+ 390:	24820000 	addiu	v0,a0,0
+ 394:	2482ffff 	addiu	v0,a0,-1
+ 398:	3c02abcd 	lui	v0,0xabcd
+ 39c:	3442ef01 	ori	v0,v0,0xef01
+ 3a0:	00441021 	addu	v0,v0,a0
+ 3a4:	3c028000 	lui	v0,0x8000
+ 3a8:	00441021 	addu	v0,v0,a0
+ 3ac:	3c027fff 	lui	v0,0x7fff
+ 3b0:	3442ffff 	ori	v0,v0,0xffff
+ 3b4:	00441021 	addu	v0,v0,a0
+ 3b8:	3c020123 	lui	v0,0x123
+ 3bc:	34424567 	ori	v0,v0,0x4567
+ 3c0:	00441021 	addu	v0,v0,a0
+ 3c4:	24820000 	addiu	v0,a0,0
+ 3c8:	2402ffff 	li	v0,-1
+ 3cc:	3c02abcd 	lui	v0,0xabcd
+ 3d0:	3442ef01 	ori	v0,v0,0xef01
+ 3d4:	3c028000 	lui	v0,0x8000
+ 3d8:	3c027fff 	lui	v0,0x7fff
+ 3dc:	3442ffff 	ori	v0,v0,0xffff
+ 3e0:	3c020123 	lui	v0,0x123
+ 3e4:	34424567 	ori	v0,v0,0x4567
+ 3e8:	24020000 	li	v0,0
+ 3ec:	2402ffff 	li	v0,-1
+ 3f0:	3c02abcd 	lui	v0,0xabcd
+ 3f4:	3442ef01 	ori	v0,v0,0xef01
+ 3f8:	3c028000 	lui	v0,0x8000
+ 3fc:	3c027fff 	lui	v0,0x7fff
+ 400:	3442ffff 	ori	v0,v0,0xffff
+ 404:	3c020123 	lui	v0,0x123
+ 408:	34424567 	ori	v0,v0,0x4567
+ 40c:	24020000 	li	v0,0
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-32-mips3.d b/gas/testsuite/gas/mips/ldstla-32-mips3.d
new file mode 100644
index 000000000000..a6f0ed1f1793
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-mips3.d
@@ -0,0 +1,271 @@
+#objdump: -d -mmips:4000
+#as: -mabi=32
+#name: MIPS ld-st-la constants (ABI o32, mips3)
+#source: ldstla-32-mips3.s
+
+.*: +file format elf32-.*mips
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	dc82ffff 	ld	v0,-1\(a0\)
+   4:	3c02abce 	lui	v0,0xabce
+   8:	00441021 	addu	v0,v0,a0
+   c:	dc42ef01 	ld	v0,-4351\(v0\)
+  10:	3c028000 	lui	v0,0x8000
+  14:	00441021 	addu	v0,v0,a0
+  18:	dc420000 	ld	v0,0\(v0\)
+  1c:	3c028000 	lui	v0,0x8000
+  20:	00441021 	addu	v0,v0,a0
+  24:	dc42ffff 	ld	v0,-1\(v0\)
+  28:	3c020123 	lui	v0,0x123
+  2c:	00441021 	addu	v0,v0,a0
+  30:	dc424567 	ld	v0,17767\(v0\)
+  34:	24020000 	li	v0,0
+  38:	00441021 	addu	v0,v0,a0
+  3c:	dc420000 	ld	v0,0\(v0\)
+  40:	24020000 	li	v0,0
+  44:	00441021 	addu	v0,v0,a0
+  48:	dc42ffff 	ld	v0,-1\(v0\)
+  4c:	3c02abce 	lui	v0,0xabce
+  50:	00441021 	addu	v0,v0,a0
+  54:	dc42ef01 	ld	v0,-4351\(v0\)
+  58:	3c028000 	lui	v0,0x8000
+  5c:	00441021 	addu	v0,v0,a0
+  60:	dc420000 	ld	v0,0\(v0\)
+  64:	3c028000 	lui	v0,0x8000
+  68:	00441021 	addu	v0,v0,a0
+  6c:	dc42ffff 	ld	v0,-1\(v0\)
+  70:	3c020123 	lui	v0,0x123
+  74:	00441021 	addu	v0,v0,a0
+  78:	dc424567 	ld	v0,17767\(v0\)
+  7c:	dc820000 	ld	v0,0\(a0\)
+  80:	dc02ffff 	ld	v0,-1\(zero\)
+  84:	3c02abce 	lui	v0,0xabce
+  88:	dc42ef01 	ld	v0,-4351\(v0\)
+  8c:	3c028000 	lui	v0,0x8000
+  90:	dc420000 	ld	v0,0\(v0\)
+  94:	3c028000 	lui	v0,0x8000
+  98:	dc42ffff 	ld	v0,-1\(v0\)
+  9c:	3c020123 	lui	v0,0x123
+  a0:	dc424567 	ld	v0,17767\(v0\)
+  a4:	24020000 	li	v0,0
+  a8:	dc420000 	ld	v0,0\(v0\)
+  ac:	24020000 	li	v0,0
+  b0:	dc42ffff 	ld	v0,-1\(v0\)
+  b4:	3c02abce 	lui	v0,0xabce
+  b8:	dc42ef01 	ld	v0,-4351\(v0\)
+  bc:	3c028000 	lui	v0,0x8000
+  c0:	dc420000 	ld	v0,0\(v0\)
+  c4:	3c028000 	lui	v0,0x8000
+  c8:	dc42ffff 	ld	v0,-1\(v0\)
+  cc:	3c020123 	lui	v0,0x123
+  d0:	dc424567 	ld	v0,17767\(v0\)
+  d4:	dc020000 	ld	v0,0\(zero\)
+  d8:	fc82ffff 	sd	v0,-1\(a0\)
+  dc:	3c01abce 	lui	at,0xabce
+  e0:	00240821 	addu	at,at,a0
+  e4:	fc22ef01 	sd	v0,-4351\(at\)
+  e8:	3c018000 	lui	at,0x8000
+  ec:	00240821 	addu	at,at,a0
+  f0:	fc220000 	sd	v0,0\(at\)
+  f4:	3c018000 	lui	at,0x8000
+  f8:	00240821 	addu	at,at,a0
+  fc:	fc22ffff 	sd	v0,-1\(at\)
+ 100:	3c010123 	lui	at,0x123
+ 104:	00240821 	addu	at,at,a0
+ 108:	fc224567 	sd	v0,17767\(at\)
+ 10c:	24010000 	li	at,0
+ 110:	00240821 	addu	at,at,a0
+ 114:	fc220000 	sd	v0,0\(at\)
+ 118:	24010000 	li	at,0
+ 11c:	00240821 	addu	at,at,a0
+ 120:	fc22ffff 	sd	v0,-1\(at\)
+ 124:	3c01abce 	lui	at,0xabce
+ 128:	00240821 	addu	at,at,a0
+ 12c:	fc22ef01 	sd	v0,-4351\(at\)
+ 130:	3c018000 	lui	at,0x8000
+ 134:	00240821 	addu	at,at,a0
+ 138:	fc220000 	sd	v0,0\(at\)
+ 13c:	3c018000 	lui	at,0x8000
+ 140:	00240821 	addu	at,at,a0
+ 144:	fc22ffff 	sd	v0,-1\(at\)
+ 148:	3c010123 	lui	at,0x123
+ 14c:	00240821 	addu	at,at,a0
+ 150:	fc224567 	sd	v0,17767\(at\)
+ 154:	fc820000 	sd	v0,0\(a0\)
+ 158:	fc02ffff 	sd	v0,-1\(zero\)
+ 15c:	3c01abce 	lui	at,0xabce
+ 160:	fc22ef01 	sd	v0,-4351\(at\)
+ 164:	3c018000 	lui	at,0x8000
+ 168:	fc220000 	sd	v0,0\(at\)
+ 16c:	3c018000 	lui	at,0x8000
+ 170:	fc22ffff 	sd	v0,-1\(at\)
+ 174:	3c010123 	lui	at,0x123
+ 178:	fc224567 	sd	v0,17767\(at\)
+ 17c:	24010000 	li	at,0
+ 180:	fc220000 	sd	v0,0\(at\)
+ 184:	24010000 	li	at,0
+ 188:	fc22ffff 	sd	v0,-1\(at\)
+ 18c:	3c01abce 	lui	at,0xabce
+ 190:	fc22ef01 	sd	v0,-4351\(at\)
+ 194:	3c018000 	lui	at,0x8000
+ 198:	fc220000 	sd	v0,0\(at\)
+ 19c:	3c018000 	lui	at,0x8000
+ 1a0:	fc22ffff 	sd	v0,-1\(at\)
+ 1a4:	3c010123 	lui	at,0x123
+ 1a8:	fc224567 	sd	v0,17767\(at\)
+ 1ac:	fc020000 	sd	v0,0\(zero\)
+ 1b0:	8c82ffff 	lw	v0,-1\(a0\)
+ 1b4:	3c02abce 	lui	v0,0xabce
+ 1b8:	00441021 	addu	v0,v0,a0
+ 1bc:	8c42ef01 	lw	v0,-4351\(v0\)
+ 1c0:	3c028000 	lui	v0,0x8000
+ 1c4:	00441021 	addu	v0,v0,a0
+ 1c8:	8c420000 	lw	v0,0\(v0\)
+ 1cc:	3c028000 	lui	v0,0x8000
+ 1d0:	00441021 	addu	v0,v0,a0
+ 1d4:	8c42ffff 	lw	v0,-1\(v0\)
+ 1d8:	3c020123 	lui	v0,0x123
+ 1dc:	00441021 	addu	v0,v0,a0
+ 1e0:	8c424567 	lw	v0,17767\(v0\)
+ 1e4:	24020000 	li	v0,0
+ 1e8:	00441021 	addu	v0,v0,a0
+ 1ec:	8c420000 	lw	v0,0\(v0\)
+ 1f0:	24020000 	li	v0,0
+ 1f4:	00441021 	addu	v0,v0,a0
+ 1f8:	8c42ffff 	lw	v0,-1\(v0\)
+ 1fc:	3c02abce 	lui	v0,0xabce
+ 200:	00441021 	addu	v0,v0,a0
+ 204:	8c42ef01 	lw	v0,-4351\(v0\)
+ 208:	3c028000 	lui	v0,0x8000
+ 20c:	00441021 	addu	v0,v0,a0
+ 210:	8c420000 	lw	v0,0\(v0\)
+ 214:	3c028000 	lui	v0,0x8000
+ 218:	00441021 	addu	v0,v0,a0
+ 21c:	8c42ffff 	lw	v0,-1\(v0\)
+ 220:	3c020123 	lui	v0,0x123
+ 224:	00441021 	addu	v0,v0,a0
+ 228:	8c424567 	lw	v0,17767\(v0\)
+ 22c:	8c820000 	lw	v0,0\(a0\)
+ 230:	8c02ffff 	lw	v0,-1\(zero\)
+ 234:	3c02abce 	lui	v0,0xabce
+ 238:	8c42ef01 	lw	v0,-4351\(v0\)
+ 23c:	3c028000 	lui	v0,0x8000
+ 240:	8c420000 	lw	v0,0\(v0\)
+ 244:	3c028000 	lui	v0,0x8000
+ 248:	8c42ffff 	lw	v0,-1\(v0\)
+ 24c:	3c020123 	lui	v0,0x123
+ 250:	8c424567 	lw	v0,17767\(v0\)
+ 254:	24020000 	li	v0,0
+ 258:	8c420000 	lw	v0,0\(v0\)
+ 25c:	24020000 	li	v0,0
+ 260:	8c42ffff 	lw	v0,-1\(v0\)
+ 264:	3c02abce 	lui	v0,0xabce
+ 268:	8c42ef01 	lw	v0,-4351\(v0\)
+ 26c:	3c028000 	lui	v0,0x8000
+ 270:	8c420000 	lw	v0,0\(v0\)
+ 274:	3c028000 	lui	v0,0x8000
+ 278:	8c42ffff 	lw	v0,-1\(v0\)
+ 27c:	3c020123 	lui	v0,0x123
+ 280:	8c424567 	lw	v0,17767\(v0\)
+ 284:	8c020000 	lw	v0,0\(zero\)
+ 288:	ac82ffff 	sw	v0,-1\(a0\)
+ 28c:	3c01abce 	lui	at,0xabce
+ 290:	00240821 	addu	at,at,a0
+ 294:	ac22ef01 	sw	v0,-4351\(at\)
+ 298:	3c018000 	lui	at,0x8000
+ 29c:	00240821 	addu	at,at,a0
+ 2a0:	ac220000 	sw	v0,0\(at\)
+ 2a4:	3c018000 	lui	at,0x8000
+ 2a8:	00240821 	addu	at,at,a0
+ 2ac:	ac22ffff 	sw	v0,-1\(at\)
+ 2b0:	3c010123 	lui	at,0x123
+ 2b4:	00240821 	addu	at,at,a0
+ 2b8:	ac224567 	sw	v0,17767\(at\)
+ 2bc:	24010000 	li	at,0
+ 2c0:	00240821 	addu	at,at,a0
+ 2c4:	ac220000 	sw	v0,0\(at\)
+ 2c8:	24010000 	li	at,0
+ 2cc:	00240821 	addu	at,at,a0
+ 2d0:	ac22ffff 	sw	v0,-1\(at\)
+ 2d4:	3c01abce 	lui	at,0xabce
+ 2d8:	00240821 	addu	at,at,a0
+ 2dc:	ac22ef01 	sw	v0,-4351\(at\)
+ 2e0:	3c018000 	lui	at,0x8000
+ 2e4:	00240821 	addu	at,at,a0
+ 2e8:	ac220000 	sw	v0,0\(at\)
+ 2ec:	3c018000 	lui	at,0x8000
+ 2f0:	00240821 	addu	at,at,a0
+ 2f4:	ac22ffff 	sw	v0,-1\(at\)
+ 2f8:	3c010123 	lui	at,0x123
+ 2fc:	00240821 	addu	at,at,a0
+ 300:	ac224567 	sw	v0,17767\(at\)
+ 304:	ac820000 	sw	v0,0\(a0\)
+ 308:	ac02ffff 	sw	v0,-1\(zero\)
+ 30c:	3c01abce 	lui	at,0xabce
+ 310:	ac22ef01 	sw	v0,-4351\(at\)
+ 314:	3c018000 	lui	at,0x8000
+ 318:	ac220000 	sw	v0,0\(at\)
+ 31c:	3c018000 	lui	at,0x8000
+ 320:	ac22ffff 	sw	v0,-1\(at\)
+ 324:	3c010123 	lui	at,0x123
+ 328:	ac224567 	sw	v0,17767\(at\)
+ 32c:	24010000 	li	at,0
+ 330:	ac220000 	sw	v0,0\(at\)
+ 334:	24010000 	li	at,0
+ 338:	ac22ffff 	sw	v0,-1\(at\)
+ 33c:	3c01abce 	lui	at,0xabce
+ 340:	ac22ef01 	sw	v0,-4351\(at\)
+ 344:	3c018000 	lui	at,0x8000
+ 348:	ac220000 	sw	v0,0\(at\)
+ 34c:	3c018000 	lui	at,0x8000
+ 350:	ac22ffff 	sw	v0,-1\(at\)
+ 354:	3c010123 	lui	at,0x123
+ 358:	ac224567 	sw	v0,17767\(at\)
+ 35c:	ac020000 	sw	v0,0\(zero\)
+ 360:	2482ffff 	addiu	v0,a0,-1
+ 364:	3c02abcd 	lui	v0,0xabcd
+ 368:	3442ef01 	ori	v0,v0,0xef01
+ 36c:	00441021 	addu	v0,v0,a0
+ 370:	3c028000 	lui	v0,0x8000
+ 374:	00441021 	addu	v0,v0,a0
+ 378:	3c027fff 	lui	v0,0x7fff
+ 37c:	3442ffff 	ori	v0,v0,0xffff
+ 380:	00441021 	addu	v0,v0,a0
+ 384:	3c020123 	lui	v0,0x123
+ 388:	34424567 	ori	v0,v0,0x4567
+ 38c:	00441021 	addu	v0,v0,a0
+ 390:	24820000 	addiu	v0,a0,0
+ 394:	2482ffff 	addiu	v0,a0,-1
+ 398:	3c02abcd 	lui	v0,0xabcd
+ 39c:	3442ef01 	ori	v0,v0,0xef01
+ 3a0:	00441021 	addu	v0,v0,a0
+ 3a4:	3c028000 	lui	v0,0x8000
+ 3a8:	00441021 	addu	v0,v0,a0
+ 3ac:	3c027fff 	lui	v0,0x7fff
+ 3b0:	3442ffff 	ori	v0,v0,0xffff
+ 3b4:	00441021 	addu	v0,v0,a0
+ 3b8:	3c020123 	lui	v0,0x123
+ 3bc:	34424567 	ori	v0,v0,0x4567
+ 3c0:	00441021 	addu	v0,v0,a0
+ 3c4:	24820000 	addiu	v0,a0,0
+ 3c8:	2402ffff 	li	v0,-1
+ 3cc:	3c02abcd 	lui	v0,0xabcd
+ 3d0:	3442ef01 	ori	v0,v0,0xef01
+ 3d4:	3c028000 	lui	v0,0x8000
+ 3d8:	3c027fff 	lui	v0,0x7fff
+ 3dc:	3442ffff 	ori	v0,v0,0xffff
+ 3e0:	3c020123 	lui	v0,0x123
+ 3e4:	34424567 	ori	v0,v0,0x4567
+ 3e8:	24020000 	li	v0,0
+ 3ec:	2402ffff 	li	v0,-1
+ 3f0:	3c02abcd 	lui	v0,0xabcd
+ 3f4:	3442ef01 	ori	v0,v0,0xef01
+ 3f8:	3c028000 	lui	v0,0x8000
+ 3fc:	3c027fff 	lui	v0,0x7fff
+ 400:	3442ffff 	ori	v0,v0,0xffff
+ 404:	3c020123 	lui	v0,0x123
+ 408:	34424567 	ori	v0,v0,0x4567
+ 40c:	24020000 	li	v0,0
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-32-mips3.s b/gas/testsuite/gas/mips/ldstla-32-mips3.s
new file mode 100644
index 000000000000..e4e5a8fa1b94
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-32-mips3.s
@@ -0,0 +1,133 @@
+	.set	mips3
+	.text
+	ld $2, 0xffffffffffffffff($4)
+	ld $2, 0xffffffffabcdef01($4)
+	ld $2, 0xffffffff80000000($4)
+	ld $2, 0xffffffff7fffffff($4)
+	ld $2, 0xffffffff01234567($4)
+	ld $2, 0xffffffff00000000($4)
+	ld $2, 0xffffffff($4)
+	ld $2, 0xabcdef01($4)
+	ld $2, 0x80000000($4)
+	ld $2, 0x7fffffff($4)
+	ld $2, 0x01234567($4)
+	ld $2, 0x00000000($4)
+
+	ld $2, 0xffffffffffffffff
+	ld $2, 0xffffffffabcdef01
+	ld $2, 0xffffffff80000000
+	ld $2, 0xffffffff7fffffff
+	ld $2, 0xffffffff01234567
+	ld $2, 0xffffffff00000000
+	ld $2, 0xffffffff
+	ld $2, 0xabcdef01
+	ld $2, 0x80000000
+	ld $2, 0x7fffffff
+	ld $2, 0x01234567
+	ld $2, 0x00000000
+
+	sd $2, 0xffffffffffffffff($4)
+	sd $2, 0xffffffffabcdef01($4)
+	sd $2, 0xffffffff80000000($4)
+	sd $2, 0xffffffff7fffffff($4)
+	sd $2, 0xffffffff01234567($4)
+	sd $2, 0xffffffff00000000($4)
+	sd $2, 0xffffffff($4)
+	sd $2, 0xabcdef01($4)
+	sd $2, 0x80000000($4)
+	sd $2, 0x7fffffff($4)
+	sd $2, 0x01234567($4)
+	sd $2, 0x00000000($4)
+
+	sd $2, 0xffffffffffffffff
+	sd $2, 0xffffffffabcdef01
+	sd $2, 0xffffffff80000000
+	sd $2, 0xffffffff7fffffff
+	sd $2, 0xffffffff01234567
+	sd $2, 0xffffffff00000000
+	sd $2, 0xffffffff
+	sd $2, 0xabcdef01
+	sd $2, 0x80000000
+	sd $2, 0x7fffffff
+	sd $2, 0x01234567
+	sd $2, 0x00000000
+
+	lw $2, 0xffffffffffffffff($4)
+	lw $2, 0xffffffffabcdef01($4)
+	lw $2, 0xffffffff80000000($4)
+	lw $2, 0xffffffff7fffffff($4)
+	lw $2, 0xffffffff01234567($4)
+	lw $2, 0xffffffff00000000($4)
+	lw $2, 0xffffffff($4)
+	lw $2, 0xabcdef01($4)
+	lw $2, 0x80000000($4)
+	lw $2, 0x7fffffff($4)
+	lw $2, 0x01234567($4)
+	lw $2, 0x00000000($4)
+
+	lw $2, 0xffffffffffffffff
+	lw $2, 0xffffffffabcdef01
+	lw $2, 0xffffffff80000000
+	lw $2, 0xffffffff7fffffff
+	lw $2, 0xffffffff01234567
+	lw $2, 0xffffffff00000000
+	lw $2, 0xffffffff
+	lw $2, 0xabcdef01
+	lw $2, 0x80000000
+	lw $2, 0x7fffffff
+	lw $2, 0x01234567
+	lw $2, 0x00000000
+
+	sw $2, 0xffffffffffffffff($4)
+	sw $2, 0xffffffffabcdef01($4)
+	sw $2, 0xffffffff80000000($4)
+	sw $2, 0xffffffff7fffffff($4)
+	sw $2, 0xffffffff01234567($4)
+	sw $2, 0xffffffff00000000($4)
+	sw $2, 0xffffffff($4)
+	sw $2, 0xabcdef01($4)
+	sw $2, 0x80000000($4)
+	sw $2, 0x7fffffff($4)
+	sw $2, 0x01234567($4)
+	sw $2, 0x00000000($4)
+
+	sw $2, 0xffffffffffffffff
+	sw $2, 0xffffffffabcdef01
+	sw $2, 0xffffffff80000000
+	sw $2, 0xffffffff7fffffff
+	sw $2, 0xffffffff01234567
+	sw $2, 0xffffffff00000000
+	sw $2, 0xffffffff
+	sw $2, 0xabcdef01
+	sw $2, 0x80000000
+	sw $2, 0x7fffffff
+	sw $2, 0x01234567
+	sw $2, 0x00000000
+
+	la $2, 0xffffffffffffffff($4)
+	la $2, 0xffffffffabcdef01($4)
+	la $2, 0xffffffff80000000($4)
+	la $2, 0xffffffff7fffffff($4)
+	la $2, 0xffffffff01234567($4)
+	la $2, 0xffffffff00000000($4)
+	la $2, 0xffffffff($4)
+	la $2, 0xabcdef01($4)
+	la $2, 0x80000000($4)
+	la $2, 0x7fffffff($4)
+	la $2, 0x01234567($4)
+	la $2, 0x00000000($4)
+
+	la $2, 0xffffffffffffffff
+	la $2, 0xffffffffabcdef01
+	la $2, 0xffffffff80000000
+	la $2, 0xffffffff7fffffff
+	la $2, 0xffffffff01234567
+	la $2, 0xffffffff00000000
+	la $2, 0xffffffff
+	la $2, 0xabcdef01
+	la $2, 0x80000000
+	la $2, 0x7fffffff
+	la $2, 0x01234567
+	la $2, 0x00000000
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/ldstla-32-shared.d b/gas/testsuite/gas/mips/ldstla-32-shared.d
index bcb6bd6a8d7b..b9e1f139d759 100644
--- a/gas/testsuite/gas/mips/ldstla-32-shared.d
+++ b/gas/testsuite/gas/mips/ldstla-32-shared.d
@@ -1,5 +1,5 @@
 #objdump: -d
-#as: -KPIC -32
+#as: -KPIC -mabi=32
 #name: MIPS ld-st-la constants (ABI o32, shared)
 #source: ldstla-32.s
 
@@ -8,73 +8,313 @@
 Disassembly of section \.text:
 
 00000000 <\.text>:
-   0:	3c0189ac 	lui	at,0x89ac
-   4:	00610821 	addu	at,v1,at
-   8:	8c22cdef 	lw	v0,-12817\(at\)
-   c:	8c23cdf3 	lw	v1,-12813\(at\)
-  10:	3c012345 	lui	at,0x2345
-  14:	00610821 	addu	at,v1,at
-  18:	8c226789 	lw	v0,26505\(at\)
-  1c:	8c23678d 	lw	v1,26509\(at\)
-  20:	3c018000 	lui	at,0x8000
-  24:	00610821 	addu	at,v1,at
-  28:	8c220000 	lw	v0,0\(at\)
-  2c:	8c230004 	lw	v1,4\(at\)
-  30:	3c010000 	lui	at,0x0
-  34:	00610821 	addu	at,v1,at
-  38:	8c220000 	lw	v0,0\(at\)
-  3c:	8c230004 	lw	v1,4\(at\)
-  40:	3c018000 	lui	at,0x8000
-  44:	00610821 	addu	at,v1,at
-  48:	8c22ffff 	lw	v0,-1\(at\)
-  4c:	8c230003 	lw	v1,3\(at\)
-  50:	3c01abce 	lui	at,0xabce
-  54:	00610821 	addu	at,v1,at
-  58:	8c22ef01 	lw	v0,-4351\(at\)
-  5c:	8c23ef05 	lw	v1,-4347\(at\)
-  60:	3c010123 	lui	at,0x123
-  64:	00610821 	addu	at,v1,at
-  68:	8c224567 	lw	v0,17767\(at\)
-  6c:	8c23456b 	lw	v1,17771\(at\)
-  70:	3c0189ac 	lui	at,0x89ac
-  74:	00610821 	addu	at,v1,at
-  78:	ac22cdef 	sw	v0,-12817\(at\)
-  7c:	ac23cdf3 	sw	v1,-12813\(at\)
-  80:	3c012345 	lui	at,0x2345
-  84:	00610821 	addu	at,v1,at
-  88:	ac226789 	sw	v0,26505\(at\)
-  8c:	ac23678d 	sw	v1,26509\(at\)
-  90:	3c018000 	lui	at,0x8000
-  94:	00610821 	addu	at,v1,at
-  98:	ac220000 	sw	v0,0\(at\)
-  9c:	ac230004 	sw	v1,4\(at\)
-  a0:	3c010000 	lui	at,0x0
-  a4:	00610821 	addu	at,v1,at
-  a8:	ac220000 	sw	v0,0\(at\)
-  ac:	ac230004 	sw	v1,4\(at\)
-  b0:	3c018000 	lui	at,0x8000
-  b4:	00610821 	addu	at,v1,at
-  b8:	ac22ffff 	sw	v0,-1\(at\)
-  bc:	ac230003 	sw	v1,3\(at\)
-  c0:	3c01abce 	lui	at,0xabce
-  c4:	00610821 	addu	at,v1,at
-  c8:	ac22ef01 	sw	v0,-4351\(at\)
-  cc:	ac23ef05 	sw	v1,-4347\(at\)
-  d0:	3c010123 	lui	at,0x123
-  d4:	00610821 	addu	at,v1,at
-  d8:	ac224567 	sw	v0,17767\(at\)
-  dc:	ac23456b 	sw	v1,17771\(at\)
-  e0:	3c028000 	lui	v0,0x8000
-  e4:	00431021 	addu	v0,v0,v1
-  e8:	8c420000 	lw	v0,0\(v0\)
-  ec:	3c020123 	lui	v0,0x123
-  f0:	00431021 	addu	v0,v0,v1
-  f4:	8c424567 	lw	v0,17767\(v0\)
-  f8:	3c010123 	lui	at,0x123
-  fc:	00230821 	addu	at,at,v1
- 100:	ac224567 	sw	v0,17767\(at\)
- 104:	3c027fff 	lui	v0,0x7fff
- 108:	3442ffff 	ori	v0,v0,0xffff
- 10c:	3c020123 	lui	v0,0x123
- 110:	34424567 	ori	v0,v0,0x4567
+   0:	8c82ffff 	lw	v0,-1\(a0\)
+   4:	8c830003 	lw	v1,3\(a0\)
+   8:	3c01abce 	lui	at,0xabce
+   c:	00810821 	addu	at,a0,at
+  10:	8c22ef01 	lw	v0,-4351\(at\)
+  14:	8c23ef05 	lw	v1,-4347\(at\)
+  18:	3c018000 	lui	at,0x8000
+  1c:	00810821 	addu	at,a0,at
+  20:	8c220000 	lw	v0,0\(at\)
+  24:	8c230004 	lw	v1,4\(at\)
+  28:	3c018000 	lui	at,0x8000
+  2c:	00810821 	addu	at,a0,at
+  30:	8c22ffff 	lw	v0,-1\(at\)
+  34:	8c230003 	lw	v1,3\(at\)
+  38:	3c010123 	lui	at,0x123
+  3c:	00810821 	addu	at,a0,at
+  40:	8c224567 	lw	v0,17767\(at\)
+  44:	8c23456b 	lw	v1,17771\(at\)
+  48:	3c010000 	lui	at,0x0
+  4c:	00810821 	addu	at,a0,at
+  50:	8c220000 	lw	v0,0\(at\)
+  54:	8c230004 	lw	v1,4\(at\)
+  58:	3c010000 	lui	at,0x0
+  5c:	00810821 	addu	at,a0,at
+  60:	8c22ffff 	lw	v0,-1\(at\)
+  64:	8c230003 	lw	v1,3\(at\)
+  68:	3c01abce 	lui	at,0xabce
+  6c:	00810821 	addu	at,a0,at
+  70:	8c22ef01 	lw	v0,-4351\(at\)
+  74:	8c23ef05 	lw	v1,-4347\(at\)
+  78:	3c018000 	lui	at,0x8000
+  7c:	00810821 	addu	at,a0,at
+  80:	8c220000 	lw	v0,0\(at\)
+  84:	8c230004 	lw	v1,4\(at\)
+  88:	3c018000 	lui	at,0x8000
+  8c:	00810821 	addu	at,a0,at
+  90:	8c22ffff 	lw	v0,-1\(at\)
+  94:	8c230003 	lw	v1,3\(at\)
+  98:	3c010123 	lui	at,0x123
+  9c:	00810821 	addu	at,a0,at
+  a0:	8c224567 	lw	v0,17767\(at\)
+  a4:	8c23456b 	lw	v1,17771\(at\)
+  a8:	8c820000 	lw	v0,0\(a0\)
+  ac:	8c830004 	lw	v1,4\(a0\)
+  b0:	8c02ffff 	lw	v0,-1\(zero\)
+  b4:	8c030003 	lw	v1,3\(zero\)
+  b8:	3c01abce 	lui	at,0xabce
+  bc:	8c22ef01 	lw	v0,-4351\(at\)
+  c0:	8c23ef05 	lw	v1,-4347\(at\)
+  c4:	3c018000 	lui	at,0x8000
+  c8:	8c220000 	lw	v0,0\(at\)
+  cc:	8c230004 	lw	v1,4\(at\)
+  d0:	3c018000 	lui	at,0x8000
+  d4:	8c22ffff 	lw	v0,-1\(at\)
+  d8:	8c230003 	lw	v1,3\(at\)
+  dc:	3c010123 	lui	at,0x123
+  e0:	8c224567 	lw	v0,17767\(at\)
+  e4:	8c23456b 	lw	v1,17771\(at\)
+  e8:	3c010000 	lui	at,0x0
+  ec:	8c220000 	lw	v0,0\(at\)
+  f0:	8c230004 	lw	v1,4\(at\)
+  f4:	3c010000 	lui	at,0x0
+  f8:	8c22ffff 	lw	v0,-1\(at\)
+  fc:	8c230003 	lw	v1,3\(at\)
+ 100:	3c01abce 	lui	at,0xabce
+ 104:	8c22ef01 	lw	v0,-4351\(at\)
+ 108:	8c23ef05 	lw	v1,-4347\(at\)
+ 10c:	3c018000 	lui	at,0x8000
+ 110:	8c220000 	lw	v0,0\(at\)
+ 114:	8c230004 	lw	v1,4\(at\)
+ 118:	3c018000 	lui	at,0x8000
+ 11c:	8c22ffff 	lw	v0,-1\(at\)
+ 120:	8c230003 	lw	v1,3\(at\)
+ 124:	3c010123 	lui	at,0x123
+ 128:	8c224567 	lw	v0,17767\(at\)
+ 12c:	8c23456b 	lw	v1,17771\(at\)
+ 130:	8c020000 	lw	v0,0\(zero\)
+ 134:	8c030004 	lw	v1,4\(zero\)
+ 138:	ac82ffff 	sw	v0,-1\(a0\)
+ 13c:	ac830003 	sw	v1,3\(a0\)
+ 140:	3c01abce 	lui	at,0xabce
+ 144:	00810821 	addu	at,a0,at
+ 148:	ac22ef01 	sw	v0,-4351\(at\)
+ 14c:	ac23ef05 	sw	v1,-4347\(at\)
+ 150:	3c018000 	lui	at,0x8000
+ 154:	00810821 	addu	at,a0,at
+ 158:	ac220000 	sw	v0,0\(at\)
+ 15c:	ac230004 	sw	v1,4\(at\)
+ 160:	3c018000 	lui	at,0x8000
+ 164:	00810821 	addu	at,a0,at
+ 168:	ac22ffff 	sw	v0,-1\(at\)
+ 16c:	ac230003 	sw	v1,3\(at\)
+ 170:	3c010123 	lui	at,0x123
+ 174:	00810821 	addu	at,a0,at
+ 178:	ac224567 	sw	v0,17767\(at\)
+ 17c:	ac23456b 	sw	v1,17771\(at\)
+ 180:	3c010000 	lui	at,0x0
+ 184:	00810821 	addu	at,a0,at
+ 188:	ac220000 	sw	v0,0\(at\)
+ 18c:	ac230004 	sw	v1,4\(at\)
+ 190:	3c010000 	lui	at,0x0
+ 194:	00810821 	addu	at,a0,at
+ 198:	ac22ffff 	sw	v0,-1\(at\)
+ 19c:	ac230003 	sw	v1,3\(at\)
+ 1a0:	3c01abce 	lui	at,0xabce
+ 1a4:	00810821 	addu	at,a0,at
+ 1a8:	ac22ef01 	sw	v0,-4351\(at\)
+ 1ac:	ac23ef05 	sw	v1,-4347\(at\)
+ 1b0:	3c018000 	lui	at,0x8000
+ 1b4:	00810821 	addu	at,a0,at
+ 1b8:	ac220000 	sw	v0,0\(at\)
+ 1bc:	ac230004 	sw	v1,4\(at\)
+ 1c0:	3c018000 	lui	at,0x8000
+ 1c4:	00810821 	addu	at,a0,at
+ 1c8:	ac22ffff 	sw	v0,-1\(at\)
+ 1cc:	ac230003 	sw	v1,3\(at\)
+ 1d0:	3c010123 	lui	at,0x123
+ 1d4:	00810821 	addu	at,a0,at
+ 1d8:	ac224567 	sw	v0,17767\(at\)
+ 1dc:	ac23456b 	sw	v1,17771\(at\)
+ 1e0:	ac820000 	sw	v0,0\(a0\)
+ 1e4:	ac830004 	sw	v1,4\(a0\)
+ 1e8:	ac02ffff 	sw	v0,-1\(zero\)
+ 1ec:	ac030003 	sw	v1,3\(zero\)
+ 1f0:	3c01abce 	lui	at,0xabce
+ 1f4:	ac22ef01 	sw	v0,-4351\(at\)
+ 1f8:	ac23ef05 	sw	v1,-4347\(at\)
+ 1fc:	3c018000 	lui	at,0x8000
+ 200:	ac220000 	sw	v0,0\(at\)
+ 204:	ac230004 	sw	v1,4\(at\)
+ 208:	3c018000 	lui	at,0x8000
+ 20c:	ac22ffff 	sw	v0,-1\(at\)
+ 210:	ac230003 	sw	v1,3\(at\)
+ 214:	3c010123 	lui	at,0x123
+ 218:	ac224567 	sw	v0,17767\(at\)
+ 21c:	ac23456b 	sw	v1,17771\(at\)
+ 220:	3c010000 	lui	at,0x0
+ 224:	ac220000 	sw	v0,0\(at\)
+ 228:	ac230004 	sw	v1,4\(at\)
+ 22c:	3c010000 	lui	at,0x0
+ 230:	ac22ffff 	sw	v0,-1\(at\)
+ 234:	ac230003 	sw	v1,3\(at\)
+ 238:	3c01abce 	lui	at,0xabce
+ 23c:	ac22ef01 	sw	v0,-4351\(at\)
+ 240:	ac23ef05 	sw	v1,-4347\(at\)
+ 244:	3c018000 	lui	at,0x8000
+ 248:	ac220000 	sw	v0,0\(at\)
+ 24c:	ac230004 	sw	v1,4\(at\)
+ 250:	3c018000 	lui	at,0x8000
+ 254:	ac22ffff 	sw	v0,-1\(at\)
+ 258:	ac230003 	sw	v1,3\(at\)
+ 25c:	3c010123 	lui	at,0x123
+ 260:	ac224567 	sw	v0,17767\(at\)
+ 264:	ac23456b 	sw	v1,17771\(at\)
+ 268:	ac020000 	sw	v0,0\(zero\)
+ 26c:	ac030004 	sw	v1,4\(zero\)
+ 270:	8c82ffff 	lw	v0,-1\(a0\)
+ 274:	3c02abce 	lui	v0,0xabce
+ 278:	00441021 	addu	v0,v0,a0
+ 27c:	8c42ef01 	lw	v0,-4351\(v0\)
+ 280:	3c028000 	lui	v0,0x8000
+ 284:	00441021 	addu	v0,v0,a0
+ 288:	8c420000 	lw	v0,0\(v0\)
+ 28c:	3c028000 	lui	v0,0x8000
+ 290:	00441021 	addu	v0,v0,a0
+ 294:	8c42ffff 	lw	v0,-1\(v0\)
+ 298:	3c020123 	lui	v0,0x123
+ 29c:	00441021 	addu	v0,v0,a0
+ 2a0:	8c424567 	lw	v0,17767\(v0\)
+ 2a4:	24020000 	li	v0,0
+ 2a8:	00441021 	addu	v0,v0,a0
+ 2ac:	8c420000 	lw	v0,0\(v0\)
+ 2b0:	24020000 	li	v0,0
+ 2b4:	00441021 	addu	v0,v0,a0
+ 2b8:	8c42ffff 	lw	v0,-1\(v0\)
+ 2bc:	3c02abce 	lui	v0,0xabce
+ 2c0:	00441021 	addu	v0,v0,a0
+ 2c4:	8c42ef01 	lw	v0,-4351\(v0\)
+ 2c8:	3c028000 	lui	v0,0x8000
+ 2cc:	00441021 	addu	v0,v0,a0
+ 2d0:	8c420000 	lw	v0,0\(v0\)
+ 2d4:	3c028000 	lui	v0,0x8000
+ 2d8:	00441021 	addu	v0,v0,a0
+ 2dc:	8c42ffff 	lw	v0,-1\(v0\)
+ 2e0:	3c020123 	lui	v0,0x123
+ 2e4:	00441021 	addu	v0,v0,a0
+ 2e8:	8c424567 	lw	v0,17767\(v0\)
+ 2ec:	8c820000 	lw	v0,0\(a0\)
+ 2f0:	8c02ffff 	lw	v0,-1\(zero\)
+ 2f4:	3c02abce 	lui	v0,0xabce
+ 2f8:	8c42ef01 	lw	v0,-4351\(v0\)
+ 2fc:	3c028000 	lui	v0,0x8000
+ 300:	8c420000 	lw	v0,0\(v0\)
+ 304:	3c028000 	lui	v0,0x8000
+ 308:	8c42ffff 	lw	v0,-1\(v0\)
+ 30c:	3c020123 	lui	v0,0x123
+ 310:	8c424567 	lw	v0,17767\(v0\)
+ 314:	24020000 	li	v0,0
+ 318:	8c420000 	lw	v0,0\(v0\)
+ 31c:	24020000 	li	v0,0
+ 320:	8c42ffff 	lw	v0,-1\(v0\)
+ 324:	3c02abce 	lui	v0,0xabce
+ 328:	8c42ef01 	lw	v0,-4351\(v0\)
+ 32c:	3c028000 	lui	v0,0x8000
+ 330:	8c420000 	lw	v0,0\(v0\)
+ 334:	3c028000 	lui	v0,0x8000
+ 338:	8c42ffff 	lw	v0,-1\(v0\)
+ 33c:	3c020123 	lui	v0,0x123
+ 340:	8c424567 	lw	v0,17767\(v0\)
+ 344:	8c020000 	lw	v0,0\(zero\)
+ 348:	00000000 	nop
+ 34c:	ac82ffff 	sw	v0,-1\(a0\)
+ 350:	3c01abce 	lui	at,0xabce
+ 354:	00240821 	addu	at,at,a0
+ 358:	ac22ef01 	sw	v0,-4351\(at\)
+ 35c:	3c018000 	lui	at,0x8000
+ 360:	00240821 	addu	at,at,a0
+ 364:	ac220000 	sw	v0,0\(at\)
+ 368:	3c018000 	lui	at,0x8000
+ 36c:	00240821 	addu	at,at,a0
+ 370:	ac22ffff 	sw	v0,-1\(at\)
+ 374:	3c010123 	lui	at,0x123
+ 378:	00240821 	addu	at,at,a0
+ 37c:	ac224567 	sw	v0,17767\(at\)
+ 380:	24010000 	li	at,0
+ 384:	00240821 	addu	at,at,a0
+ 388:	ac220000 	sw	v0,0\(at\)
+ 38c:	24010000 	li	at,0
+ 390:	00240821 	addu	at,at,a0
+ 394:	ac22ffff 	sw	v0,-1\(at\)
+ 398:	3c01abce 	lui	at,0xabce
+ 39c:	00240821 	addu	at,at,a0
+ 3a0:	ac22ef01 	sw	v0,-4351\(at\)
+ 3a4:	3c018000 	lui	at,0x8000
+ 3a8:	00240821 	addu	at,at,a0
+ 3ac:	ac220000 	sw	v0,0\(at\)
+ 3b0:	3c018000 	lui	at,0x8000
+ 3b4:	00240821 	addu	at,at,a0
+ 3b8:	ac22ffff 	sw	v0,-1\(at\)
+ 3bc:	3c010123 	lui	at,0x123
+ 3c0:	00240821 	addu	at,at,a0
+ 3c4:	ac224567 	sw	v0,17767\(at\)
+ 3c8:	ac820000 	sw	v0,0\(a0\)
+ 3cc:	ac02ffff 	sw	v0,-1\(zero\)
+ 3d0:	3c01abce 	lui	at,0xabce
+ 3d4:	ac22ef01 	sw	v0,-4351\(at\)
+ 3d8:	3c018000 	lui	at,0x8000
+ 3dc:	ac220000 	sw	v0,0\(at\)
+ 3e0:	3c018000 	lui	at,0x8000
+ 3e4:	ac22ffff 	sw	v0,-1\(at\)
+ 3e8:	3c010123 	lui	at,0x123
+ 3ec:	ac224567 	sw	v0,17767\(at\)
+ 3f0:	24010000 	li	at,0
+ 3f4:	ac220000 	sw	v0,0\(at\)
+ 3f8:	24010000 	li	at,0
+ 3fc:	ac22ffff 	sw	v0,-1\(at\)
+ 400:	3c01abce 	lui	at,0xabce
+ 404:	ac22ef01 	sw	v0,-4351\(at\)
+ 408:	3c018000 	lui	at,0x8000
+ 40c:	ac220000 	sw	v0,0\(at\)
+ 410:	3c018000 	lui	at,0x8000
+ 414:	ac22ffff 	sw	v0,-1\(at\)
+ 418:	3c010123 	lui	at,0x123
+ 41c:	ac224567 	sw	v0,17767\(at\)
+ 420:	ac020000 	sw	v0,0\(zero\)
+ 424:	2482ffff 	addiu	v0,a0,-1
+ 428:	3c02abcd 	lui	v0,0xabcd
+ 42c:	3442ef01 	ori	v0,v0,0xef01
+ 430:	00441021 	addu	v0,v0,a0
+ 434:	3c028000 	lui	v0,0x8000
+ 438:	00441021 	addu	v0,v0,a0
+ 43c:	3c027fff 	lui	v0,0x7fff
+ 440:	3442ffff 	ori	v0,v0,0xffff
+ 444:	00441021 	addu	v0,v0,a0
+ 448:	3c020123 	lui	v0,0x123
+ 44c:	34424567 	ori	v0,v0,0x4567
+ 450:	00441021 	addu	v0,v0,a0
+ 454:	24820000 	addiu	v0,a0,0
+ 458:	2482ffff 	addiu	v0,a0,-1
+ 45c:	3c02abcd 	lui	v0,0xabcd
+ 460:	3442ef01 	ori	v0,v0,0xef01
+ 464:	00441021 	addu	v0,v0,a0
+ 468:	3c028000 	lui	v0,0x8000
+ 46c:	00441021 	addu	v0,v0,a0
+ 470:	3c027fff 	lui	v0,0x7fff
+ 474:	3442ffff 	ori	v0,v0,0xffff
+ 478:	00441021 	addu	v0,v0,a0
+ 47c:	3c020123 	lui	v0,0x123
+ 480:	34424567 	ori	v0,v0,0x4567
+ 484:	00441021 	addu	v0,v0,a0
+ 488:	24820000 	addiu	v0,a0,0
+ 48c:	2402ffff 	li	v0,-1
+ 490:	3c02abcd 	lui	v0,0xabcd
+ 494:	3442ef01 	ori	v0,v0,0xef01
+ 498:	3c028000 	lui	v0,0x8000
+ 49c:	3c027fff 	lui	v0,0x7fff
+ 4a0:	3442ffff 	ori	v0,v0,0xffff
+ 4a4:	3c020123 	lui	v0,0x123
+ 4a8:	34424567 	ori	v0,v0,0x4567
+ 4ac:	24020000 	li	v0,0
+ 4b0:	2402ffff 	li	v0,-1
+ 4b4:	3c02abcd 	lui	v0,0xabcd
+ 4b8:	3442ef01 	ori	v0,v0,0xef01
+ 4bc:	3c028000 	lui	v0,0x8000
+ 4c0:	3c027fff 	lui	v0,0x7fff
+ 4c4:	3442ffff 	ori	v0,v0,0xffff
+ 4c8:	3c020123 	lui	v0,0x123
+ 4cc:	34424567 	ori	v0,v0,0x4567
+ 4d0:	24020000 	li	v0,0
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-32.d b/gas/testsuite/gas/mips/ldstla-32.d
index 989cd7e0eb74..6c467c48bb38 100644
--- a/gas/testsuite/gas/mips/ldstla-32.d
+++ b/gas/testsuite/gas/mips/ldstla-32.d
@@ -1,5 +1,5 @@
 #objdump: -d
-#as: -32
+#as: -mabi=32
 #name: MIPS ld-st-la constants (ABI o32)
 #source: ldstla-32.s
 
@@ -8,73 +8,313 @@
 Disassembly of section \.text:
 
 00000000 <\.text>:
-   0:	3c0189ac 	lui	at,0x89ac
-   4:	00610821 	addu	at,v1,at
-   8:	8c22cdef 	lw	v0,-12817\(at\)
-   c:	8c23cdf3 	lw	v1,-12813\(at\)
-  10:	3c012345 	lui	at,0x2345
-  14:	00610821 	addu	at,v1,at
-  18:	8c226789 	lw	v0,26505\(at\)
-  1c:	8c23678d 	lw	v1,26509\(at\)
-  20:	3c018000 	lui	at,0x8000
-  24:	00610821 	addu	at,v1,at
-  28:	8c220000 	lw	v0,0\(at\)
-  2c:	8c230004 	lw	v1,4\(at\)
-  30:	3c010000 	lui	at,0x0
-  34:	00610821 	addu	at,v1,at
-  38:	8c220000 	lw	v0,0\(at\)
-  3c:	8c230004 	lw	v1,4\(at\)
-  40:	3c018000 	lui	at,0x8000
-  44:	00610821 	addu	at,v1,at
-  48:	8c22ffff 	lw	v0,-1\(at\)
-  4c:	8c230003 	lw	v1,3\(at\)
-  50:	3c01abce 	lui	at,0xabce
-  54:	00610821 	addu	at,v1,at
-  58:	8c22ef01 	lw	v0,-4351\(at\)
-  5c:	8c23ef05 	lw	v1,-4347\(at\)
-  60:	3c010123 	lui	at,0x123
-  64:	00610821 	addu	at,v1,at
-  68:	8c224567 	lw	v0,17767\(at\)
-  6c:	8c23456b 	lw	v1,17771\(at\)
-  70:	3c0189ac 	lui	at,0x89ac
-  74:	00610821 	addu	at,v1,at
-  78:	ac22cdef 	sw	v0,-12817\(at\)
-  7c:	ac23cdf3 	sw	v1,-12813\(at\)
-  80:	3c012345 	lui	at,0x2345
-  84:	00610821 	addu	at,v1,at
-  88:	ac226789 	sw	v0,26505\(at\)
-  8c:	ac23678d 	sw	v1,26509\(at\)
-  90:	3c018000 	lui	at,0x8000
-  94:	00610821 	addu	at,v1,at
-  98:	ac220000 	sw	v0,0\(at\)
-  9c:	ac230004 	sw	v1,4\(at\)
-  a0:	3c010000 	lui	at,0x0
-  a4:	00610821 	addu	at,v1,at
-  a8:	ac220000 	sw	v0,0\(at\)
-  ac:	ac230004 	sw	v1,4\(at\)
-  b0:	3c018000 	lui	at,0x8000
-  b4:	00610821 	addu	at,v1,at
-  b8:	ac22ffff 	sw	v0,-1\(at\)
-  bc:	ac230003 	sw	v1,3\(at\)
-  c0:	3c01abce 	lui	at,0xabce
-  c4:	00610821 	addu	at,v1,at
-  c8:	ac22ef01 	sw	v0,-4351\(at\)
-  cc:	ac23ef05 	sw	v1,-4347\(at\)
-  d0:	3c010123 	lui	at,0x123
-  d4:	00610821 	addu	at,v1,at
-  d8:	ac224567 	sw	v0,17767\(at\)
-  dc:	ac23456b 	sw	v1,17771\(at\)
-  e0:	3c028000 	lui	v0,0x8000
-  e4:	00431021 	addu	v0,v0,v1
-  e8:	8c420000 	lw	v0,0\(v0\)
-  ec:	3c020123 	lui	v0,0x123
-  f0:	00431021 	addu	v0,v0,v1
-  f4:	8c424567 	lw	v0,17767\(v0\)
-  f8:	3c010123 	lui	at,0x123
-  fc:	00230821 	addu	at,at,v1
- 100:	ac224567 	sw	v0,17767\(at\)
- 104:	3c027fff 	lui	v0,0x7fff
- 108:	3442ffff 	ori	v0,v0,0xffff
- 10c:	3c020123 	lui	v0,0x123
- 110:	34424567 	ori	v0,v0,0x4567
+   0:	8c82ffff 	lw	v0,-1\(a0\)
+   4:	8c830003 	lw	v1,3\(a0\)
+   8:	3c01abce 	lui	at,0xabce
+   c:	00810821 	addu	at,a0,at
+  10:	8c22ef01 	lw	v0,-4351\(at\)
+  14:	8c23ef05 	lw	v1,-4347\(at\)
+  18:	3c018000 	lui	at,0x8000
+  1c:	00810821 	addu	at,a0,at
+  20:	8c220000 	lw	v0,0\(at\)
+  24:	8c230004 	lw	v1,4\(at\)
+  28:	3c018000 	lui	at,0x8000
+  2c:	00810821 	addu	at,a0,at
+  30:	8c22ffff 	lw	v0,-1\(at\)
+  34:	8c230003 	lw	v1,3\(at\)
+  38:	3c010123 	lui	at,0x123
+  3c:	00810821 	addu	at,a0,at
+  40:	8c224567 	lw	v0,17767\(at\)
+  44:	8c23456b 	lw	v1,17771\(at\)
+  48:	3c010000 	lui	at,0x0
+  4c:	00810821 	addu	at,a0,at
+  50:	8c220000 	lw	v0,0\(at\)
+  54:	8c230004 	lw	v1,4\(at\)
+  58:	3c010000 	lui	at,0x0
+  5c:	00810821 	addu	at,a0,at
+  60:	8c22ffff 	lw	v0,-1\(at\)
+  64:	8c230003 	lw	v1,3\(at\)
+  68:	3c01abce 	lui	at,0xabce
+  6c:	00810821 	addu	at,a0,at
+  70:	8c22ef01 	lw	v0,-4351\(at\)
+  74:	8c23ef05 	lw	v1,-4347\(at\)
+  78:	3c018000 	lui	at,0x8000
+  7c:	00810821 	addu	at,a0,at
+  80:	8c220000 	lw	v0,0\(at\)
+  84:	8c230004 	lw	v1,4\(at\)
+  88:	3c018000 	lui	at,0x8000
+  8c:	00810821 	addu	at,a0,at
+  90:	8c22ffff 	lw	v0,-1\(at\)
+  94:	8c230003 	lw	v1,3\(at\)
+  98:	3c010123 	lui	at,0x123
+  9c:	00810821 	addu	at,a0,at
+  a0:	8c224567 	lw	v0,17767\(at\)
+  a4:	8c23456b 	lw	v1,17771\(at\)
+  a8:	8c820000 	lw	v0,0\(a0\)
+  ac:	8c830004 	lw	v1,4\(a0\)
+  b0:	8c02ffff 	lw	v0,-1\(zero\)
+  b4:	8c030003 	lw	v1,3\(zero\)
+  b8:	3c01abce 	lui	at,0xabce
+  bc:	8c22ef01 	lw	v0,-4351\(at\)
+  c0:	8c23ef05 	lw	v1,-4347\(at\)
+  c4:	3c018000 	lui	at,0x8000
+  c8:	8c220000 	lw	v0,0\(at\)
+  cc:	8c230004 	lw	v1,4\(at\)
+  d0:	3c018000 	lui	at,0x8000
+  d4:	8c22ffff 	lw	v0,-1\(at\)
+  d8:	8c230003 	lw	v1,3\(at\)
+  dc:	3c010123 	lui	at,0x123
+  e0:	8c224567 	lw	v0,17767\(at\)
+  e4:	8c23456b 	lw	v1,17771\(at\)
+  e8:	3c010000 	lui	at,0x0
+  ec:	8c220000 	lw	v0,0\(at\)
+  f0:	8c230004 	lw	v1,4\(at\)
+  f4:	3c010000 	lui	at,0x0
+  f8:	8c22ffff 	lw	v0,-1\(at\)
+  fc:	8c230003 	lw	v1,3\(at\)
+ 100:	3c01abce 	lui	at,0xabce
+ 104:	8c22ef01 	lw	v0,-4351\(at\)
+ 108:	8c23ef05 	lw	v1,-4347\(at\)
+ 10c:	3c018000 	lui	at,0x8000
+ 110:	8c220000 	lw	v0,0\(at\)
+ 114:	8c230004 	lw	v1,4\(at\)
+ 118:	3c018000 	lui	at,0x8000
+ 11c:	8c22ffff 	lw	v0,-1\(at\)
+ 120:	8c230003 	lw	v1,3\(at\)
+ 124:	3c010123 	lui	at,0x123
+ 128:	8c224567 	lw	v0,17767\(at\)
+ 12c:	8c23456b 	lw	v1,17771\(at\)
+ 130:	8c020000 	lw	v0,0\(zero\)
+ 134:	8c030004 	lw	v1,4\(zero\)
+ 138:	ac82ffff 	sw	v0,-1\(a0\)
+ 13c:	ac830003 	sw	v1,3\(a0\)
+ 140:	3c01abce 	lui	at,0xabce
+ 144:	00810821 	addu	at,a0,at
+ 148:	ac22ef01 	sw	v0,-4351\(at\)
+ 14c:	ac23ef05 	sw	v1,-4347\(at\)
+ 150:	3c018000 	lui	at,0x8000
+ 154:	00810821 	addu	at,a0,at
+ 158:	ac220000 	sw	v0,0\(at\)
+ 15c:	ac230004 	sw	v1,4\(at\)
+ 160:	3c018000 	lui	at,0x8000
+ 164:	00810821 	addu	at,a0,at
+ 168:	ac22ffff 	sw	v0,-1\(at\)
+ 16c:	ac230003 	sw	v1,3\(at\)
+ 170:	3c010123 	lui	at,0x123
+ 174:	00810821 	addu	at,a0,at
+ 178:	ac224567 	sw	v0,17767\(at\)
+ 17c:	ac23456b 	sw	v1,17771\(at\)
+ 180:	3c010000 	lui	at,0x0
+ 184:	00810821 	addu	at,a0,at
+ 188:	ac220000 	sw	v0,0\(at\)
+ 18c:	ac230004 	sw	v1,4\(at\)
+ 190:	3c010000 	lui	at,0x0
+ 194:	00810821 	addu	at,a0,at
+ 198:	ac22ffff 	sw	v0,-1\(at\)
+ 19c:	ac230003 	sw	v1,3\(at\)
+ 1a0:	3c01abce 	lui	at,0xabce
+ 1a4:	00810821 	addu	at,a0,at
+ 1a8:	ac22ef01 	sw	v0,-4351\(at\)
+ 1ac:	ac23ef05 	sw	v1,-4347\(at\)
+ 1b0:	3c018000 	lui	at,0x8000
+ 1b4:	00810821 	addu	at,a0,at
+ 1b8:	ac220000 	sw	v0,0\(at\)
+ 1bc:	ac230004 	sw	v1,4\(at\)
+ 1c0:	3c018000 	lui	at,0x8000
+ 1c4:	00810821 	addu	at,a0,at
+ 1c8:	ac22ffff 	sw	v0,-1\(at\)
+ 1cc:	ac230003 	sw	v1,3\(at\)
+ 1d0:	3c010123 	lui	at,0x123
+ 1d4:	00810821 	addu	at,a0,at
+ 1d8:	ac224567 	sw	v0,17767\(at\)
+ 1dc:	ac23456b 	sw	v1,17771\(at\)
+ 1e0:	ac820000 	sw	v0,0\(a0\)
+ 1e4:	ac830004 	sw	v1,4\(a0\)
+ 1e8:	ac02ffff 	sw	v0,-1\(zero\)
+ 1ec:	ac030003 	sw	v1,3\(zero\)
+ 1f0:	3c01abce 	lui	at,0xabce
+ 1f4:	ac22ef01 	sw	v0,-4351\(at\)
+ 1f8:	ac23ef05 	sw	v1,-4347\(at\)
+ 1fc:	3c018000 	lui	at,0x8000
+ 200:	ac220000 	sw	v0,0\(at\)
+ 204:	ac230004 	sw	v1,4\(at\)
+ 208:	3c018000 	lui	at,0x8000
+ 20c:	ac22ffff 	sw	v0,-1\(at\)
+ 210:	ac230003 	sw	v1,3\(at\)
+ 214:	3c010123 	lui	at,0x123
+ 218:	ac224567 	sw	v0,17767\(at\)
+ 21c:	ac23456b 	sw	v1,17771\(at\)
+ 220:	3c010000 	lui	at,0x0
+ 224:	ac220000 	sw	v0,0\(at\)
+ 228:	ac230004 	sw	v1,4\(at\)
+ 22c:	3c010000 	lui	at,0x0
+ 230:	ac22ffff 	sw	v0,-1\(at\)
+ 234:	ac230003 	sw	v1,3\(at\)
+ 238:	3c01abce 	lui	at,0xabce
+ 23c:	ac22ef01 	sw	v0,-4351\(at\)
+ 240:	ac23ef05 	sw	v1,-4347\(at\)
+ 244:	3c018000 	lui	at,0x8000
+ 248:	ac220000 	sw	v0,0\(at\)
+ 24c:	ac230004 	sw	v1,4\(at\)
+ 250:	3c018000 	lui	at,0x8000
+ 254:	ac22ffff 	sw	v0,-1\(at\)
+ 258:	ac230003 	sw	v1,3\(at\)
+ 25c:	3c010123 	lui	at,0x123
+ 260:	ac224567 	sw	v0,17767\(at\)
+ 264:	ac23456b 	sw	v1,17771\(at\)
+ 268:	ac020000 	sw	v0,0\(zero\)
+ 26c:	ac030004 	sw	v1,4\(zero\)
+ 270:	8c82ffff 	lw	v0,-1\(a0\)
+ 274:	3c02abce 	lui	v0,0xabce
+ 278:	00441021 	addu	v0,v0,a0
+ 27c:	8c42ef01 	lw	v0,-4351\(v0\)
+ 280:	3c028000 	lui	v0,0x8000
+ 284:	00441021 	addu	v0,v0,a0
+ 288:	8c420000 	lw	v0,0\(v0\)
+ 28c:	3c028000 	lui	v0,0x8000
+ 290:	00441021 	addu	v0,v0,a0
+ 294:	8c42ffff 	lw	v0,-1\(v0\)
+ 298:	3c020123 	lui	v0,0x123
+ 29c:	00441021 	addu	v0,v0,a0
+ 2a0:	8c424567 	lw	v0,17767\(v0\)
+ 2a4:	24020000 	li	v0,0
+ 2a8:	00441021 	addu	v0,v0,a0
+ 2ac:	8c420000 	lw	v0,0\(v0\)
+ 2b0:	24020000 	li	v0,0
+ 2b4:	00441021 	addu	v0,v0,a0
+ 2b8:	8c42ffff 	lw	v0,-1\(v0\)
+ 2bc:	3c02abce 	lui	v0,0xabce
+ 2c0:	00441021 	addu	v0,v0,a0
+ 2c4:	8c42ef01 	lw	v0,-4351\(v0\)
+ 2c8:	3c028000 	lui	v0,0x8000
+ 2cc:	00441021 	addu	v0,v0,a0
+ 2d0:	8c420000 	lw	v0,0\(v0\)
+ 2d4:	3c028000 	lui	v0,0x8000
+ 2d8:	00441021 	addu	v0,v0,a0
+ 2dc:	8c42ffff 	lw	v0,-1\(v0\)
+ 2e0:	3c020123 	lui	v0,0x123
+ 2e4:	00441021 	addu	v0,v0,a0
+ 2e8:	8c424567 	lw	v0,17767\(v0\)
+ 2ec:	8c820000 	lw	v0,0\(a0\)
+ 2f0:	8c02ffff 	lw	v0,-1\(zero\)
+ 2f4:	3c02abce 	lui	v0,0xabce
+ 2f8:	8c42ef01 	lw	v0,-4351\(v0\)
+ 2fc:	3c028000 	lui	v0,0x8000
+ 300:	8c420000 	lw	v0,0\(v0\)
+ 304:	3c028000 	lui	v0,0x8000
+ 308:	8c42ffff 	lw	v0,-1\(v0\)
+ 30c:	3c020123 	lui	v0,0x123
+ 310:	8c424567 	lw	v0,17767\(v0\)
+ 314:	24020000 	li	v0,0
+ 318:	8c420000 	lw	v0,0\(v0\)
+ 31c:	24020000 	li	v0,0
+ 320:	8c42ffff 	lw	v0,-1\(v0\)
+ 324:	3c02abce 	lui	v0,0xabce
+ 328:	8c42ef01 	lw	v0,-4351\(v0\)
+ 32c:	3c028000 	lui	v0,0x8000
+ 330:	8c420000 	lw	v0,0\(v0\)
+ 334:	3c028000 	lui	v0,0x8000
+ 338:	8c42ffff 	lw	v0,-1\(v0\)
+ 33c:	3c020123 	lui	v0,0x123
+ 340:	8c424567 	lw	v0,17767\(v0\)
+ 344:	8c020000 	lw	v0,0\(zero\)
+ 348:	00000000 	nop
+ 34c:	ac82ffff 	sw	v0,-1\(a0\)
+ 350:	3c01abce 	lui	at,0xabce
+ 354:	00240821 	addu	at,at,a0
+ 358:	ac22ef01 	sw	v0,-4351\(at\)
+ 35c:	3c018000 	lui	at,0x8000
+ 360:	00240821 	addu	at,at,a0
+ 364:	ac220000 	sw	v0,0\(at\)
+ 368:	3c018000 	lui	at,0x8000
+ 36c:	00240821 	addu	at,at,a0
+ 370:	ac22ffff 	sw	v0,-1\(at\)
+ 374:	3c010123 	lui	at,0x123
+ 378:	00240821 	addu	at,at,a0
+ 37c:	ac224567 	sw	v0,17767\(at\)
+ 380:	24010000 	li	at,0
+ 384:	00240821 	addu	at,at,a0
+ 388:	ac220000 	sw	v0,0\(at\)
+ 38c:	24010000 	li	at,0
+ 390:	00240821 	addu	at,at,a0
+ 394:	ac22ffff 	sw	v0,-1\(at\)
+ 398:	3c01abce 	lui	at,0xabce
+ 39c:	00240821 	addu	at,at,a0
+ 3a0:	ac22ef01 	sw	v0,-4351\(at\)
+ 3a4:	3c018000 	lui	at,0x8000
+ 3a8:	00240821 	addu	at,at,a0
+ 3ac:	ac220000 	sw	v0,0\(at\)
+ 3b0:	3c018000 	lui	at,0x8000
+ 3b4:	00240821 	addu	at,at,a0
+ 3b8:	ac22ffff 	sw	v0,-1\(at\)
+ 3bc:	3c010123 	lui	at,0x123
+ 3c0:	00240821 	addu	at,at,a0
+ 3c4:	ac224567 	sw	v0,17767\(at\)
+ 3c8:	ac820000 	sw	v0,0\(a0\)
+ 3cc:	ac02ffff 	sw	v0,-1\(zero\)
+ 3d0:	3c01abce 	lui	at,0xabce
+ 3d4:	ac22ef01 	sw	v0,-4351\(at\)
+ 3d8:	3c018000 	lui	at,0x8000
+ 3dc:	ac220000 	sw	v0,0\(at\)
+ 3e0:	3c018000 	lui	at,0x8000
+ 3e4:	ac22ffff 	sw	v0,-1\(at\)
+ 3e8:	3c010123 	lui	at,0x123
+ 3ec:	ac224567 	sw	v0,17767\(at\)
+ 3f0:	24010000 	li	at,0
+ 3f4:	ac220000 	sw	v0,0\(at\)
+ 3f8:	24010000 	li	at,0
+ 3fc:	ac22ffff 	sw	v0,-1\(at\)
+ 400:	3c01abce 	lui	at,0xabce
+ 404:	ac22ef01 	sw	v0,-4351\(at\)
+ 408:	3c018000 	lui	at,0x8000
+ 40c:	ac220000 	sw	v0,0\(at\)
+ 410:	3c018000 	lui	at,0x8000
+ 414:	ac22ffff 	sw	v0,-1\(at\)
+ 418:	3c010123 	lui	at,0x123
+ 41c:	ac224567 	sw	v0,17767\(at\)
+ 420:	ac020000 	sw	v0,0\(zero\)
+ 424:	2482ffff 	addiu	v0,a0,-1
+ 428:	3c02abcd 	lui	v0,0xabcd
+ 42c:	3442ef01 	ori	v0,v0,0xef01
+ 430:	00441021 	addu	v0,v0,a0
+ 434:	3c028000 	lui	v0,0x8000
+ 438:	00441021 	addu	v0,v0,a0
+ 43c:	3c027fff 	lui	v0,0x7fff
+ 440:	3442ffff 	ori	v0,v0,0xffff
+ 444:	00441021 	addu	v0,v0,a0
+ 448:	3c020123 	lui	v0,0x123
+ 44c:	34424567 	ori	v0,v0,0x4567
+ 450:	00441021 	addu	v0,v0,a0
+ 454:	24820000 	addiu	v0,a0,0
+ 458:	2482ffff 	addiu	v0,a0,-1
+ 45c:	3c02abcd 	lui	v0,0xabcd
+ 460:	3442ef01 	ori	v0,v0,0xef01
+ 464:	00441021 	addu	v0,v0,a0
+ 468:	3c028000 	lui	v0,0x8000
+ 46c:	00441021 	addu	v0,v0,a0
+ 470:	3c027fff 	lui	v0,0x7fff
+ 474:	3442ffff 	ori	v0,v0,0xffff
+ 478:	00441021 	addu	v0,v0,a0
+ 47c:	3c020123 	lui	v0,0x123
+ 480:	34424567 	ori	v0,v0,0x4567
+ 484:	00441021 	addu	v0,v0,a0
+ 488:	24820000 	addiu	v0,a0,0
+ 48c:	2402ffff 	li	v0,-1
+ 490:	3c02abcd 	lui	v0,0xabcd
+ 494:	3442ef01 	ori	v0,v0,0xef01
+ 498:	3c028000 	lui	v0,0x8000
+ 49c:	3c027fff 	lui	v0,0x7fff
+ 4a0:	3442ffff 	ori	v0,v0,0xffff
+ 4a4:	3c020123 	lui	v0,0x123
+ 4a8:	34424567 	ori	v0,v0,0x4567
+ 4ac:	24020000 	li	v0,0
+ 4b0:	2402ffff 	li	v0,-1
+ 4b4:	3c02abcd 	lui	v0,0xabcd
+ 4b8:	3442ef01 	ori	v0,v0,0xef01
+ 4bc:	3c028000 	lui	v0,0x8000
+ 4c0:	3c027fff 	lui	v0,0x7fff
+ 4c4:	3442ffff 	ori	v0,v0,0xffff
+ 4c8:	3c020123 	lui	v0,0x123
+ 4cc:	34424567 	ori	v0,v0,0x4567
+ 4d0:	24020000 	li	v0,0
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-32.s b/gas/testsuite/gas/mips/ldstla-32.s
index 0f363279e723..642c3d09cad7 100644
--- a/gas/testsuite/gas/mips/ldstla-32.s
+++ b/gas/testsuite/gas/mips/ldstla-32.s
@@ -1,26 +1,132 @@
 	.text
-	ld $2, 0x0123456789abcdef($3)
-	ld $2, 0xabcdef0123456789($3)
-	ld $2, 0xffffffff80000000($3)
-	ld $2, 0xffffffff00000000($3)
-	ld $2, 0xffffffff7fffffff($3)
-	ld $2, 0xabcdef01($3)
-	ld $2, 0x01234567($3)
-
-	sd $2, 0x0123456789abcdef($3)
-	sd $2, 0xabcdef0123456789($3)
-	sd $2, 0xffffffff80000000($3)
-	sd $2, 0xffffffff00000000($3)
-	sd $2, 0xffffffff7fffffff($3)
-	sd $2, 0xabcdef01($3)
-	sd $2, 0x01234567($3)
-
-	lw $2, 0xffffffff80000000($3)
-	lw $2, 0x01234567($3)
-
-	sw $2, 0x01234567($3)
+	ld $2, 0xffffffffffffffff($4)
+	ld $2, 0xffffffffabcdef01($4)
+	ld $2, 0xffffffff80000000($4)
+	ld $2, 0xffffffff7fffffff($4)
+	ld $2, 0xffffffff01234567($4)
+	ld $2, 0xffffffff00000000($4)
+	ld $2, 0xffffffff($4)
+	ld $2, 0xabcdef01($4)
+	ld $2, 0x80000000($4)
+	ld $2, 0x7fffffff($4)
+	ld $2, 0x01234567($4)
+	ld $2, 0x00000000($4)
 
+	ld $2, 0xffffffffffffffff
+	ld $2, 0xffffffffabcdef01
+	ld $2, 0xffffffff80000000
+	ld $2, 0xffffffff7fffffff
+	ld $2, 0xffffffff01234567
+	ld $2, 0xffffffff00000000
+	ld $2, 0xffffffff
+	ld $2, 0xabcdef01
+	ld $2, 0x80000000
+	ld $2, 0x7fffffff
+	ld $2, 0x01234567
+	ld $2, 0x00000000
+
+	sd $2, 0xffffffffffffffff($4)
+	sd $2, 0xffffffffabcdef01($4)
+	sd $2, 0xffffffff80000000($4)
+	sd $2, 0xffffffff7fffffff($4)
+	sd $2, 0xffffffff01234567($4)
+	sd $2, 0xffffffff00000000($4)
+	sd $2, 0xffffffff($4)
+	sd $2, 0xabcdef01($4)
+	sd $2, 0x80000000($4)
+	sd $2, 0x7fffffff($4)
+	sd $2, 0x01234567($4)
+	sd $2, 0x00000000($4)
+
+	sd $2, 0xffffffffffffffff
+	sd $2, 0xffffffffabcdef01
+	sd $2, 0xffffffff80000000
+	sd $2, 0xffffffff7fffffff
+	sd $2, 0xffffffff01234567
+	sd $2, 0xffffffff00000000
+	sd $2, 0xffffffff
+	sd $2, 0xabcdef01
+	sd $2, 0x80000000
+	sd $2, 0x7fffffff
+	sd $2, 0x01234567
+	sd $2, 0x00000000
+
+	lw $2, 0xffffffffffffffff($4)
+	lw $2, 0xffffffffabcdef01($4)
+	lw $2, 0xffffffff80000000($4)
+	lw $2, 0xffffffff7fffffff($4)
+	lw $2, 0xffffffff01234567($4)
+	lw $2, 0xffffffff00000000($4)
+	lw $2, 0xffffffff($4)
+	lw $2, 0xabcdef01($4)
+	lw $2, 0x80000000($4)
+	lw $2, 0x7fffffff($4)
+	lw $2, 0x01234567($4)
+	lw $2, 0x00000000($4)
+
+	lw $2, 0xffffffffffffffff
+	lw $2, 0xffffffffabcdef01
+	lw $2, 0xffffffff80000000
+	lw $2, 0xffffffff7fffffff
+	lw $2, 0xffffffff01234567
+	lw $2, 0xffffffff00000000
+	lw $2, 0xffffffff
+	lw $2, 0xabcdef01
+	lw $2, 0x80000000
+	lw $2, 0x7fffffff
+	lw $2, 0x01234567
+	lw $2, 0x00000000
+
+	sw $2, 0xffffffffffffffff($4)
+	sw $2, 0xffffffffabcdef01($4)
+	sw $2, 0xffffffff80000000($4)
+	sw $2, 0xffffffff7fffffff($4)
+	sw $2, 0xffffffff01234567($4)
+	sw $2, 0xffffffff00000000($4)
+	sw $2, 0xffffffff($4)
+	sw $2, 0xabcdef01($4)
+	sw $2, 0x80000000($4)
+	sw $2, 0x7fffffff($4)
+	sw $2, 0x01234567($4)
+	sw $2, 0x00000000($4)
+
+	sw $2, 0xffffffffffffffff
+	sw $2, 0xffffffffabcdef01
+	sw $2, 0xffffffff80000000
+	sw $2, 0xffffffff7fffffff
+	sw $2, 0xffffffff01234567
+	sw $2, 0xffffffff00000000
+	sw $2, 0xffffffff
+	sw $2, 0xabcdef01
+	sw $2, 0x80000000
+	sw $2, 0x7fffffff
+	sw $2, 0x01234567
+	sw $2, 0x00000000
+
+	la $2, 0xffffffffffffffff($4)
+	la $2, 0xffffffffabcdef01($4)
+	la $2, 0xffffffff80000000($4)
+	la $2, 0xffffffff7fffffff($4)
+	la $2, 0xffffffff01234567($4)
+	la $2, 0xffffffff00000000($4)
+	la $2, 0xffffffff($4)
+	la $2, 0xabcdef01($4)
+	la $2, 0x80000000($4)
+	la $2, 0x7fffffff($4)
+	la $2, 0x01234567($4)
+	la $2, 0x00000000($4)
+
+	la $2, 0xffffffffffffffff
+	la $2, 0xffffffffabcdef01
+	la $2, 0xffffffff80000000
+	la $2, 0xffffffff7fffffff
+	la $2, 0xffffffff01234567
+	la $2, 0xffffffff00000000
+	la $2, 0xffffffff
+	la $2, 0xabcdef01
+	la $2, 0x80000000
 	la $2, 0x7fffffff
 	la $2, 0x01234567
+	la $2, 0x00000000
 
 	.space 8
diff --git a/gas/testsuite/gas/mips/ldstla-eabi64.d b/gas/testsuite/gas/mips/ldstla-eabi64.d
new file mode 100644
index 000000000000..10b4784e6b9d
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-eabi64.d
@@ -0,0 +1,657 @@
+#objdump: -dr
+#as: -mabi=eabi -mips3 -G8 -EB
+#name: MIPS ld-st-la (EABI64)
+#source: ldstla-sym32.s
+
+.*file format .*
+
+Disassembly .*:
+
+0+00 <.*>:
+#
+# dla constants
+#
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x8000
+.*	lui	a0,0x8000
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0x7ff8
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0x7ff8
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0xfff8
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0xfff8
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abc
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0xdef0
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abc
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0xdef0
+.*	daddu	a0,a0,v1
+#
+# dla small_comm
+#
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	a0,a0,v1
+.*	daddiu	a0,gp,3
+.*: R_MIPS_GPREL16	small_comm
+.*	daddiu	a0,gp,3
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	a0,a0,v1
+#
+# dla big_comm
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	a0,a0,3
+.*: R_MIPS_LO16	big_comm
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	a0,a0,3
+.*: R_MIPS_LO16	big_comm
+.*	daddu	a0,a0,v1
+#
+# dla small_data
+#
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	a0,a0,v1
+.*	daddiu	a0,gp,3
+.*: R_MIPS_GPREL16	small_data
+.*	daddiu	a0,gp,3
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	a0,a0,v1
+#
+# dla big_data
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	a0,a0,3
+.*: R_MIPS_LO16	big_data
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	a0,a0,3
+.*: R_MIPS_LO16	big_data
+.*	daddu	a0,a0,v1
+#
+# dla extern
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x3
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,16384
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x3
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,16384
+.*: R_MIPS_LO16	extern
+.*	daddu	a0,a0,v1
+.*	lui	a0,0xfffd
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,-16384
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0xfffd
+.*: R_MIPS_HI16	extern
+.*	d?addiu	a0,a0,-16384
+.*: R_MIPS_LO16	extern
+.*	daddu	a0,a0,v1
+#
+# lw constants
+#
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	lw	a0,0\(a0\)
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x8000
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x8000
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x7fff
+.*	lw	a0,32760\(a0\)
+.*	lui	a0,0x7fff
+.*	daddu	a0,a0,v1
+.*	lw	a0,32760\(a0\)
+.*	li	a0,0x8000
+.*	dsll	a0,a0,0x10
+.*	lw	a0,-8\(a0\)
+.*	li	a0,0x8000
+.*	dsll	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,-8\(a0\)
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abd
+.*	dsll	a0,a0,0x10
+.*	lw	a0,-8464\(a0\)
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abd
+.*	dsll	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,-8464\(a0\)
+#
+# lw small_comm
+#
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_comm
+.*	lw	a0,3\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	a0,v1,gp
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_GPREL16	small_comm
+#
+# lw big_comm
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*	daddu	a0,a0,v1
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_LO16	big_comm
+#
+# lw small_data
+#
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_data
+.*	lw	a0,3\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	a0,v1,gp
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_GPREL16	small_data
+#
+# lw big_data
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_LO16	big_data
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*	daddu	a0,a0,v1
+.*	lw	a0,3\(a0\)
+.*: R_MIPS_LO16	big_data
+#
+# lw extern
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x3
+.*: R_MIPS_HI16	extern
+.*	lw	a0,16384\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x3
+.*: R_MIPS_HI16	extern
+.*	daddu	a0,a0,v1
+.*	lw	a0,16384\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0xfffd
+.*: R_MIPS_HI16	extern
+.*	lw	a0,-16384\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0xfffd
+.*: R_MIPS_HI16	extern
+.*	daddu	a0,a0,v1
+.*	lw	a0,-16384\(a0\)
+.*: R_MIPS_LO16	extern
+#
+# sw constants
+#
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	sw	a0,0\(at\)
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*	lui	at,0x8000
+.*	sw	a0,0\(at\)
+.*	lui	at,0x8000
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*	lui	at,0x7fff
+.*	sw	a0,32760\(at\)
+.*	lui	at,0x7fff
+.*	daddu	at,at,v1
+.*	sw	a0,32760\(at\)
+.*	li	at,0x8000
+.*	dsll	at,at,0x10
+.*	sw	a0,-8\(at\)
+.*	li	at,0x8000
+.*	dsll	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,-8\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abd
+.*	dsll	at,at,0x10
+.*	sw	a0,-8464\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abd
+.*	dsll	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,-8464\(at\)
+#
+# sw small_comm
+#
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_comm
+.*	sw	a0,3\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	at,v1,gp
+.*	sw	a0,3\(at\)
+.*: R_MIPS_GPREL16	small_comm
+#
+# sw big_comm
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	sw	a0,3\(at\)
+.*: R_MIPS_LO16	big_comm
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	daddu	at,at,v1
+.*	sw	a0,3\(at\)
+.*: R_MIPS_LO16	big_comm
+#
+# sw small_data
+#
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_data
+.*	sw	a0,3\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	at,v1,gp
+.*	sw	a0,3\(at\)
+.*: R_MIPS_GPREL16	small_data
+#
+# sw big_data
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	sw	a0,3\(at\)
+.*: R_MIPS_LO16	big_data
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	daddu	at,at,v1
+.*	sw	a0,3\(at\)
+.*: R_MIPS_LO16	big_data
+#
+# sw extern
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x3
+.*: R_MIPS_HI16	extern
+.*	sw	a0,16384\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x3
+.*: R_MIPS_HI16	extern
+.*	daddu	at,at,v1
+.*	sw	a0,16384\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0xfffd
+.*: R_MIPS_HI16	extern
+.*	sw	a0,-16384\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0xfffd
+.*: R_MIPS_HI16	extern
+.*	daddu	at,at,v1
+.*	sw	a0,-16384\(at\)
+.*: R_MIPS_LO16	extern
+#
+# usw constants
+#
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x8000
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x8000
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0x7ff8
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0x7ff8
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0xfff8
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0xfff8
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abc
+.*	dsll	at,at,0x10
+.*	ori	at,at,0xdef0
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abc
+.*	dsll	at,at,0x10
+.*	ori	at,at,0xdef0
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw small_comm
+#
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,3
+.*: R_MIPS_GPREL16	small_comm
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,3
+.*: R_MIPS_GPREL16	small_comm
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw big_comm
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	at,at,3
+.*: R_MIPS_LO16	big_comm
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*	d?addiu	at,at,3
+.*: R_MIPS_LO16	big_comm
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw small_data
+#
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,3
+.*: R_MIPS_GPREL16	small_data
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,3
+.*: R_MIPS_GPREL16	small_data
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw big_data
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	at,at,3
+.*: R_MIPS_LO16	big_data
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*	d?addiu	at,at,3
+.*: R_MIPS_LO16	big_data
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw extern
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x3
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,16384
+.*: R_MIPS_LO16	extern
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x3
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,16384
+.*: R_MIPS_LO16	extern
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0xfffd
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,-16384
+.*: R_MIPS_LO16	extern
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0xfffd
+.*: R_MIPS_HI16	extern
+.*	d?addiu	at,at,-16384
+.*: R_MIPS_LO16	extern
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# with sym32 off (has no effect for EABI64)
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	daddiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	daddiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# ...and back on again
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	daddiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*	daddiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#pass
diff --git a/gas/testsuite/gas/mips/ldstla-n32-shared.d b/gas/testsuite/gas/mips/ldstla-n32-shared.d
deleted file mode 100644
index 0d4655b0dcfb..000000000000
--- a/gas/testsuite/gas/mips/ldstla-n32-shared.d
+++ /dev/null
@@ -1,154 +0,0 @@
-#objdump: -d
-#as: -KPIC -n32
-#name: MIPS ld-st-la constants (ABI n32, shared)
-#source: ldstla-n32.s
-
-.*: +file format elf32-n.*mips
-
-Disassembly of section \.text:
-
-00000000 <\.text>:
-   0:	3c020123 	lui	v0,0x123
-   4:	3c0189ac 	lui	at,0x89ac
-   8:	64424568 	daddiu	v0,v0,17768
-   c:	0023082d 	daddu	at,at,v1
-  10:	0002103c 	dsll32	v0,v0,0x0
-  14:	0041102d 	daddu	v0,v0,at
-  18:	dc42cdef 	ld	v0,-12817\(v0\)
-  1c:	3c02abce 	lui	v0,0xabce
-  20:	3c012345 	lui	at,0x2345
-  24:	6442ef01 	daddiu	v0,v0,-4351
-  28:	0023082d 	daddu	at,at,v1
-  2c:	0002103c 	dsll32	v0,v0,0x0
-  30:	0041102d 	daddu	v0,v0,at
-  34:	dc426789 	ld	v0,26505\(v0\)
-  38:	3c028000 	lui	v0,0x8000
-  3c:	00431021 	addu	v0,v0,v1
-  40:	dc420000 	ld	v0,0\(v0\)
-  44:	3c020000 	lui	v0,0x0
-  48:	3c010000 	lui	at,0x0
-  4c:	6442ffff 	daddiu	v0,v0,-1
-  50:	0023082d 	daddu	at,at,v1
-  54:	0002103c 	dsll32	v0,v0,0x0
-  58:	0041102d 	daddu	v0,v0,at
-  5c:	dc420000 	ld	v0,0\(v0\)
-  60:	3c020000 	lui	v0,0x0
-  64:	3c01abce 	lui	at,0xabce
-  68:	64420001 	daddiu	v0,v0,1
-  6c:	0023082d 	daddu	at,at,v1
-  70:	0002103c 	dsll32	v0,v0,0x0
-  74:	0041102d 	daddu	v0,v0,at
-  78:	dc42ef01 	ld	v0,-4351\(v0\)
-  7c:	3c020123 	lui	v0,0x123
-  80:	00431021 	addu	v0,v0,v1
-  84:	dc424567 	ld	v0,17767\(v0\)
-  88:	3c010123 	lui	at,0x123
-  8c:	64214568 	daddiu	at,at,17768
-  90:	00010c38 	dsll	at,at,0x10
-  94:	642189ac 	daddiu	at,at,-30292
-  98:	00010c38 	dsll	at,at,0x10
-  9c:	0023082d 	daddu	at,at,v1
-  a0:	fc22cdef 	sd	v0,-12817\(at\)
-  a4:	3c01abce 	lui	at,0xabce
-  a8:	6421ef01 	daddiu	at,at,-4351
-  ac:	00010c38 	dsll	at,at,0x10
-  b0:	64212345 	daddiu	at,at,9029
-  b4:	00010c38 	dsll	at,at,0x10
-  b8:	0023082d 	daddu	at,at,v1
-  bc:	fc226789 	sd	v0,26505\(at\)
-  c0:	3c018000 	lui	at,0x8000
-  c4:	00230821 	addu	at,at,v1
-  c8:	fc220000 	sd	v0,0\(at\)
-  cc:	3c010000 	lui	at,0x0
-  d0:	6421ffff 	daddiu	at,at,-1
-  d4:	00010c38 	dsll	at,at,0x10
-  d8:	64210000 	daddiu	at,at,0
-  dc:	00010c38 	dsll	at,at,0x10
-  e0:	0023082d 	daddu	at,at,v1
-  e4:	fc220000 	sd	v0,0\(at\)
-  e8:	3c010000 	lui	at,0x0
-  ec:	64210001 	daddiu	at,at,1
-  f0:	00010c38 	dsll	at,at,0x10
-  f4:	6421abce 	daddiu	at,at,-21554
-  f8:	00010c38 	dsll	at,at,0x10
-  fc:	0023082d 	daddu	at,at,v1
- 100:	fc22ef01 	sd	v0,-4351\(at\)
- 104:	3c010123 	lui	at,0x123
- 108:	00230821 	addu	at,at,v1
- 10c:	fc224567 	sd	v0,17767\(at\)
- 110:	3c020123 	lui	v0,0x123
- 114:	3c0189ac 	lui	at,0x89ac
- 118:	64424568 	daddiu	v0,v0,17768
- 11c:	0023082d 	daddu	at,at,v1
- 120:	0002103c 	dsll32	v0,v0,0x0
- 124:	0041102d 	daddu	v0,v0,at
- 128:	8c42cdef 	lw	v0,-12817\(v0\)
- 12c:	3c02abce 	lui	v0,0xabce
- 130:	3c012345 	lui	at,0x2345
- 134:	6442ef01 	daddiu	v0,v0,-4351
- 138:	0023082d 	daddu	at,at,v1
- 13c:	0002103c 	dsll32	v0,v0,0x0
- 140:	0041102d 	daddu	v0,v0,at
- 144:	8c426789 	lw	v0,26505\(v0\)
- 148:	3c028000 	lui	v0,0x8000
- 14c:	00431021 	addu	v0,v0,v1
- 150:	8c420000 	lw	v0,0\(v0\)
- 154:	3c020000 	lui	v0,0x0
- 158:	3c010000 	lui	at,0x0
- 15c:	6442ffff 	daddiu	v0,v0,-1
- 160:	0023082d 	daddu	at,at,v1
- 164:	0002103c 	dsll32	v0,v0,0x0
- 168:	0041102d 	daddu	v0,v0,at
- 16c:	8c420000 	lw	v0,0\(v0\)
- 170:	3c020000 	lui	v0,0x0
- 174:	3c01abce 	lui	at,0xabce
- 178:	64420001 	daddiu	v0,v0,1
- 17c:	0023082d 	daddu	at,at,v1
- 180:	0002103c 	dsll32	v0,v0,0x0
- 184:	0041102d 	daddu	v0,v0,at
- 188:	8c42ef01 	lw	v0,-4351\(v0\)
- 18c:	3c020123 	lui	v0,0x123
- 190:	00431021 	addu	v0,v0,v1
- 194:	8c424567 	lw	v0,17767\(v0\)
- 198:	3c010123 	lui	at,0x123
- 19c:	64214568 	daddiu	at,at,17768
- 1a0:	00010c38 	dsll	at,at,0x10
- 1a4:	642189ac 	daddiu	at,at,-30292
- 1a8:	00010c38 	dsll	at,at,0x10
- 1ac:	0023082d 	daddu	at,at,v1
- 1b0:	ac22cdef 	sw	v0,-12817\(at\)
- 1b4:	3c01abce 	lui	at,0xabce
- 1b8:	6421ef01 	daddiu	at,at,-4351
- 1bc:	00010c38 	dsll	at,at,0x10
- 1c0:	64212345 	daddiu	at,at,9029
- 1c4:	00010c38 	dsll	at,at,0x10
- 1c8:	0023082d 	daddu	at,at,v1
- 1cc:	ac226789 	sw	v0,26505\(at\)
- 1d0:	3c018000 	lui	at,0x8000
- 1d4:	00230821 	addu	at,at,v1
- 1d8:	ac220000 	sw	v0,0\(at\)
- 1dc:	3c010000 	lui	at,0x0
- 1e0:	6421ffff 	daddiu	at,at,-1
- 1e4:	00010c38 	dsll	at,at,0x10
- 1e8:	64210000 	daddiu	at,at,0
- 1ec:	00010c38 	dsll	at,at,0x10
- 1f0:	0023082d 	daddu	at,at,v1
- 1f4:	ac220000 	sw	v0,0\(at\)
- 1f8:	3c010000 	lui	at,0x0
- 1fc:	64210001 	daddiu	at,at,1
- 200:	00010c38 	dsll	at,at,0x10
- 204:	6421abce 	daddiu	at,at,-21554
- 208:	00010c38 	dsll	at,at,0x10
- 20c:	0023082d 	daddu	at,at,v1
- 210:	ac22ef01 	sw	v0,-4351\(at\)
- 214:	3c010123 	lui	at,0x123
- 218:	00230821 	addu	at,at,v1
- 21c:	ac224567 	sw	v0,17767\(at\)
- 220:	3c028000 	lui	v0,0x8000
- 224:	3c020123 	lui	v0,0x123
- 228:	34424567 	ori	v0,v0,0x4567
- 22c:	3c027fff 	lui	v0,0x7fff
- 230:	3442ffff 	ori	v0,v0,0xffff
- 234:	3c020123 	lui	v0,0x123
- 238:	34424567 	ori	v0,v0,0x4567
-	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-n32.d b/gas/testsuite/gas/mips/ldstla-n32.d
deleted file mode 100644
index 9245da4c6a6c..000000000000
--- a/gas/testsuite/gas/mips/ldstla-n32.d
+++ /dev/null
@@ -1,154 +0,0 @@
-#objdump: -d
-#as: -n32
-#name: MIPS ld-st-la constants (ABI n32)
-#source: ldstla-n32.s
-
-.*: +file format elf32-n.*mips
-
-Disassembly of section \.text:
-
-00000000 <\.text>:
-   0:	3c020123 	lui	v0,0x123
-   4:	3c0189ac 	lui	at,0x89ac
-   8:	64424568 	daddiu	v0,v0,17768
-   c:	0023082d 	daddu	at,at,v1
-  10:	0002103c 	dsll32	v0,v0,0x0
-  14:	0041102d 	daddu	v0,v0,at
-  18:	dc42cdef 	ld	v0,-12817\(v0\)
-  1c:	3c02abce 	lui	v0,0xabce
-  20:	3c012345 	lui	at,0x2345
-  24:	6442ef01 	daddiu	v0,v0,-4351
-  28:	0023082d 	daddu	at,at,v1
-  2c:	0002103c 	dsll32	v0,v0,0x0
-  30:	0041102d 	daddu	v0,v0,at
-  34:	dc426789 	ld	v0,26505\(v0\)
-  38:	3c028000 	lui	v0,0x8000
-  3c:	00431021 	addu	v0,v0,v1
-  40:	dc420000 	ld	v0,0\(v0\)
-  44:	3c020000 	lui	v0,0x0
-  48:	3c010000 	lui	at,0x0
-  4c:	6442ffff 	daddiu	v0,v0,-1
-  50:	0023082d 	daddu	at,at,v1
-  54:	0002103c 	dsll32	v0,v0,0x0
-  58:	0041102d 	daddu	v0,v0,at
-  5c:	dc420000 	ld	v0,0\(v0\)
-  60:	3c020000 	lui	v0,0x0
-  64:	3c01abce 	lui	at,0xabce
-  68:	64420001 	daddiu	v0,v0,1
-  6c:	0023082d 	daddu	at,at,v1
-  70:	0002103c 	dsll32	v0,v0,0x0
-  74:	0041102d 	daddu	v0,v0,at
-  78:	dc42ef01 	ld	v0,-4351\(v0\)
-  7c:	3c020123 	lui	v0,0x123
-  80:	00431021 	addu	v0,v0,v1
-  84:	dc424567 	ld	v0,17767\(v0\)
-  88:	3c010123 	lui	at,0x123
-  8c:	64214568 	daddiu	at,at,17768
-  90:	00010c38 	dsll	at,at,0x10
-  94:	642189ac 	daddiu	at,at,-30292
-  98:	00010c38 	dsll	at,at,0x10
-  9c:	0023082d 	daddu	at,at,v1
-  a0:	fc22cdef 	sd	v0,-12817\(at\)
-  a4:	3c01abce 	lui	at,0xabce
-  a8:	6421ef01 	daddiu	at,at,-4351
-  ac:	00010c38 	dsll	at,at,0x10
-  b0:	64212345 	daddiu	at,at,9029
-  b4:	00010c38 	dsll	at,at,0x10
-  b8:	0023082d 	daddu	at,at,v1
-  bc:	fc226789 	sd	v0,26505\(at\)
-  c0:	3c018000 	lui	at,0x8000
-  c4:	00230821 	addu	at,at,v1
-  c8:	fc220000 	sd	v0,0\(at\)
-  cc:	3c010000 	lui	at,0x0
-  d0:	6421ffff 	daddiu	at,at,-1
-  d4:	00010c38 	dsll	at,at,0x10
-  d8:	64210000 	daddiu	at,at,0
-  dc:	00010c38 	dsll	at,at,0x10
-  e0:	0023082d 	daddu	at,at,v1
-  e4:	fc220000 	sd	v0,0\(at\)
-  e8:	3c010000 	lui	at,0x0
-  ec:	64210001 	daddiu	at,at,1
-  f0:	00010c38 	dsll	at,at,0x10
-  f4:	6421abce 	daddiu	at,at,-21554
-  f8:	00010c38 	dsll	at,at,0x10
-  fc:	0023082d 	daddu	at,at,v1
- 100:	fc22ef01 	sd	v0,-4351\(at\)
- 104:	3c010123 	lui	at,0x123
- 108:	00230821 	addu	at,at,v1
- 10c:	fc224567 	sd	v0,17767\(at\)
- 110:	3c020123 	lui	v0,0x123
- 114:	3c0189ac 	lui	at,0x89ac
- 118:	64424568 	daddiu	v0,v0,17768
- 11c:	0023082d 	daddu	at,at,v1
- 120:	0002103c 	dsll32	v0,v0,0x0
- 124:	0041102d 	daddu	v0,v0,at
- 128:	8c42cdef 	lw	v0,-12817\(v0\)
- 12c:	3c02abce 	lui	v0,0xabce
- 130:	3c012345 	lui	at,0x2345
- 134:	6442ef01 	daddiu	v0,v0,-4351
- 138:	0023082d 	daddu	at,at,v1
- 13c:	0002103c 	dsll32	v0,v0,0x0
- 140:	0041102d 	daddu	v0,v0,at
- 144:	8c426789 	lw	v0,26505\(v0\)
- 148:	3c028000 	lui	v0,0x8000
- 14c:	00431021 	addu	v0,v0,v1
- 150:	8c420000 	lw	v0,0\(v0\)
- 154:	3c020000 	lui	v0,0x0
- 158:	3c010000 	lui	at,0x0
- 15c:	6442ffff 	daddiu	v0,v0,-1
- 160:	0023082d 	daddu	at,at,v1
- 164:	0002103c 	dsll32	v0,v0,0x0
- 168:	0041102d 	daddu	v0,v0,at
- 16c:	8c420000 	lw	v0,0\(v0\)
- 170:	3c020000 	lui	v0,0x0
- 174:	3c01abce 	lui	at,0xabce
- 178:	64420001 	daddiu	v0,v0,1
- 17c:	0023082d 	daddu	at,at,v1
- 180:	0002103c 	dsll32	v0,v0,0x0
- 184:	0041102d 	daddu	v0,v0,at
- 188:	8c42ef01 	lw	v0,-4351\(v0\)
- 18c:	3c020123 	lui	v0,0x123
- 190:	00431021 	addu	v0,v0,v1
- 194:	8c424567 	lw	v0,17767\(v0\)
- 198:	3c010123 	lui	at,0x123
- 19c:	64214568 	daddiu	at,at,17768
- 1a0:	00010c38 	dsll	at,at,0x10
- 1a4:	642189ac 	daddiu	at,at,-30292
- 1a8:	00010c38 	dsll	at,at,0x10
- 1ac:	0023082d 	daddu	at,at,v1
- 1b0:	ac22cdef 	sw	v0,-12817\(at\)
- 1b4:	3c01abce 	lui	at,0xabce
- 1b8:	6421ef01 	daddiu	at,at,-4351
- 1bc:	00010c38 	dsll	at,at,0x10
- 1c0:	64212345 	daddiu	at,at,9029
- 1c4:	00010c38 	dsll	at,at,0x10
- 1c8:	0023082d 	daddu	at,at,v1
- 1cc:	ac226789 	sw	v0,26505\(at\)
- 1d0:	3c018000 	lui	at,0x8000
- 1d4:	00230821 	addu	at,at,v1
- 1d8:	ac220000 	sw	v0,0\(at\)
- 1dc:	3c010000 	lui	at,0x0
- 1e0:	6421ffff 	daddiu	at,at,-1
- 1e4:	00010c38 	dsll	at,at,0x10
- 1e8:	64210000 	daddiu	at,at,0
- 1ec:	00010c38 	dsll	at,at,0x10
- 1f0:	0023082d 	daddu	at,at,v1
- 1f4:	ac220000 	sw	v0,0\(at\)
- 1f8:	3c010000 	lui	at,0x0
- 1fc:	64210001 	daddiu	at,at,1
- 200:	00010c38 	dsll	at,at,0x10
- 204:	6421abce 	daddiu	at,at,-21554
- 208:	00010c38 	dsll	at,at,0x10
- 20c:	0023082d 	daddu	at,at,v1
- 210:	ac22ef01 	sw	v0,-4351\(at\)
- 214:	3c010123 	lui	at,0x123
- 218:	00230821 	addu	at,at,v1
- 21c:	ac224567 	sw	v0,17767\(at\)
- 220:	3c028000 	lui	v0,0x8000
- 224:	3c020123 	lui	v0,0x123
- 228:	34424567 	ori	v0,v0,0x4567
- 22c:	3c027fff 	lui	v0,0x7fff
- 230:	3442ffff 	ori	v0,v0,0xffff
- 234:	3c020123 	lui	v0,0x123
- 238:	34424567 	ori	v0,v0,0x4567
-	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-n32.s b/gas/testsuite/gas/mips/ldstla-n32.s
deleted file mode 100644
index 1b5d863bf9ca..000000000000
--- a/gas/testsuite/gas/mips/ldstla-n32.s
+++ /dev/null
@@ -1,35 +0,0 @@
-	.text
-	ld $2, 0x0123456789abcdef($3)
-	ld $2, 0xabcdef0123456789($3)
-	ld $2, 0xffffffff80000000($3)
-	ld $2, 0xffffffff00000000($3)
-	ld $2, 0xabcdef01($3)
-	ld $2, 0x01234567($3)
-
-	sd $2, 0x0123456789abcdef($3)
-	sd $2, 0xabcdef0123456789($3)
-	sd $2, 0xffffffff80000000($3)
-	sd $2, 0xffffffff00000000($3)
-	sd $2, 0xabcdef01($3)
-	sd $2, 0x01234567($3)
-
-	lw $2, 0x0123456789abcdef($3)
-	lw $2, 0xabcdef0123456789($3)
-	lw $2, 0xffffffff80000000($3)
-	lw $2, 0xffffffff00000000($3)
-	lw $2, 0xabcdef01($3)
-	lw $2, 0x01234567($3)
-
-	sw $2, 0x0123456789abcdef($3)
-	sw $2, 0xabcdef0123456789($3)
-	sw $2, 0xffffffff80000000($3)
-	sw $2, 0xffffffff00000000($3)
-	sw $2, 0xabcdef01($3)
-	sw $2, 0x01234567($3)
-
-	dla $2, 0xffffffff80000000
-	dla $2, 0x01234567
-	la $2, 0x7fffffff
-	la $2, 0x01234567
-
-	.space 8
diff --git a/gas/testsuite/gas/mips/ldstla-n64-shared.d b/gas/testsuite/gas/mips/ldstla-n64-shared.d
index 971e296e97e7..acbbb43f46e4 100644
--- a/gas/testsuite/gas/mips/ldstla-n64-shared.d
+++ b/gas/testsuite/gas/mips/ldstla-n64-shared.d
@@ -9,173 +9,149 @@ Disassembly of section \.text:
 
 0000000000000000 <\.text>:
    0:	3c020123 	lui	v0,0x123
-   4:	3c0189ac 	lui	at,0x89ac
-   8:	64424568 	daddiu	v0,v0,17768
-   c:	0023082d 	daddu	at,at,v1
-  10:	0002103c 	dsll32	v0,v0,0x0
-  14:	0041102d 	daddu	v0,v0,at
+   4:	34424567 	ori	v0,v0,0x4567
+   8:	00021438 	dsll	v0,v0,0x10
+   c:	344289ac 	ori	v0,v0,0x89ac
+  10:	00021438 	dsll	v0,v0,0x10
+  14:	0043102d 	daddu	v0,v0,v1
   18:	dc42cdef 	ld	v0,-12817\(v0\)
-  1c:	3c02abce 	lui	v0,0xabce
-  20:	3c012345 	lui	at,0x2345
-  24:	6442ef01 	daddiu	v0,v0,-4351
-  28:	0023082d 	daddu	at,at,v1
-  2c:	0002103c 	dsll32	v0,v0,0x0
-  30:	0041102d 	daddu	v0,v0,at
+  1c:	3c02abcd 	lui	v0,0xabcd
+  20:	3442ef01 	ori	v0,v0,0xef01
+  24:	00021438 	dsll	v0,v0,0x10
+  28:	34422345 	ori	v0,v0,0x2345
+  2c:	00021438 	dsll	v0,v0,0x10
+  30:	0043102d 	daddu	v0,v0,v1
   34:	dc426789 	ld	v0,26505\(v0\)
   38:	3c028000 	lui	v0,0x8000
   3c:	0043102d 	daddu	v0,v0,v1
   40:	dc420000 	ld	v0,0\(v0\)
-  44:	3c020000 	lui	v0,0x0
-  48:	3c010000 	lui	at,0x0
-  4c:	6442ffff 	daddiu	v0,v0,-1
-  50:	0023082d 	daddu	at,at,v1
-  54:	0002103c 	dsll32	v0,v0,0x0
-  58:	0041102d 	daddu	v0,v0,at
-  5c:	dc420000 	ld	v0,0\(v0\)
-  60:	3c028000 	lui	v0,0x8000
-  64:	0043102d 	daddu	v0,v0,v1
-  68:	dc42ffff 	ld	v0,-1\(v0\)
-  6c:	3c020000 	lui	v0,0x0
-  70:	3c01abce 	lui	at,0xabce
-  74:	64420001 	daddiu	v0,v0,1
-  78:	0023082d 	daddu	at,at,v1
-  7c:	0002103c 	dsll32	v0,v0,0x0
-  80:	0041102d 	daddu	v0,v0,at
-  84:	dc42ef01 	ld	v0,-4351\(v0\)
-  88:	3c020123 	lui	v0,0x123
-  8c:	0043102d 	daddu	v0,v0,v1
-  90:	dc424567 	ld	v0,17767\(v0\)
-  94:	3c010123 	lui	at,0x123
-  98:	64214568 	daddiu	at,at,17768
-  9c:	00010c38 	dsll	at,at,0x10
-  a0:	642189ac 	daddiu	at,at,-30292
-  a4:	00010c38 	dsll	at,at,0x10
-  a8:	0023082d 	daddu	at,at,v1
-  ac:	fc22cdef 	sd	v0,-12817\(at\)
-  b0:	3c01abce 	lui	at,0xabce
-  b4:	6421ef01 	daddiu	at,at,-4351
-  b8:	00010c38 	dsll	at,at,0x10
-  bc:	64212345 	daddiu	at,at,9029
-  c0:	00010c38 	dsll	at,at,0x10
-  c4:	0023082d 	daddu	at,at,v1
-  c8:	fc226789 	sd	v0,26505\(at\)
-  cc:	3c018000 	lui	at,0x8000
-  d0:	0023082d 	daddu	at,at,v1
-  d4:	fc220000 	sd	v0,0\(at\)
-  d8:	3c010000 	lui	at,0x0
-  dc:	6421ffff 	daddiu	at,at,-1
+  44:	2402ffff 	li	v0,-1
+  48:	0002103c 	dsll32	v0,v0,0x0
+  4c:	0043102d 	daddu	v0,v0,v1
+  50:	dc420000 	ld	v0,0\(v0\)
+  54:	3c028000 	lui	v0,0x8000
+  58:	0043102d 	daddu	v0,v0,v1
+  5c:	dc42ffff 	ld	v0,-1\(v0\)
+  60:	3402abce 	li	v0,0xabce
+  64:	00021438 	dsll	v0,v0,0x10
+  68:	0043102d 	daddu	v0,v0,v1
+  6c:	dc42ef01 	ld	v0,-4351\(v0\)
+  70:	3c020123 	lui	v0,0x123
+  74:	0043102d 	daddu	v0,v0,v1
+  78:	dc424567 	ld	v0,17767\(v0\)
+  7c:	3c010123 	lui	at,0x123
+  80:	34214567 	ori	at,at,0x4567
+  84:	00010c38 	dsll	at,at,0x10
+  88:	342189ac 	ori	at,at,0x89ac
+  8c:	00010c38 	dsll	at,at,0x10
+  90:	0023082d 	daddu	at,at,v1
+  94:	fc22cdef 	sd	v0,-12817\(at\)
+  98:	3c01abcd 	lui	at,0xabcd
+  9c:	3421ef01 	ori	at,at,0xef01
+  a0:	00010c38 	dsll	at,at,0x10
+  a4:	34212345 	ori	at,at,0x2345
+  a8:	00010c38 	dsll	at,at,0x10
+  ac:	0023082d 	daddu	at,at,v1
+  b0:	fc226789 	sd	v0,26505\(at\)
+  b4:	3c018000 	lui	at,0x8000
+  b8:	0023082d 	daddu	at,at,v1
+  bc:	fc220000 	sd	v0,0\(at\)
+  c0:	2401ffff 	li	at,-1
+  c4:	0001083c 	dsll32	at,at,0x0
+  c8:	0023082d 	daddu	at,at,v1
+  cc:	fc220000 	sd	v0,0\(at\)
+  d0:	3c018000 	lui	at,0x8000
+  d4:	0023082d 	daddu	at,at,v1
+  d8:	fc22ffff 	sd	v0,-1\(at\)
+  dc:	3401abce 	li	at,0xabce
   e0:	00010c38 	dsll	at,at,0x10
-  e4:	64210000 	daddiu	at,at,0
-  e8:	00010c38 	dsll	at,at,0x10
-  ec:	0023082d 	daddu	at,at,v1
-  f0:	fc220000 	sd	v0,0\(at\)
-  f4:	3c018000 	lui	at,0x8000
-  f8:	0023082d 	daddu	at,at,v1
-  fc:	fc22ffff 	sd	v0,-1\(at\)
- 100:	3c010000 	lui	at,0x0
- 104:	64210001 	daddiu	at,at,1
- 108:	00010c38 	dsll	at,at,0x10
- 10c:	6421abce 	daddiu	at,at,-21554
- 110:	00010c38 	dsll	at,at,0x10
- 114:	0023082d 	daddu	at,at,v1
- 118:	fc22ef01 	sd	v0,-4351\(at\)
- 11c:	3c010123 	lui	at,0x123
- 120:	0023082d 	daddu	at,at,v1
- 124:	fc224567 	sd	v0,17767\(at\)
- 128:	3c020123 	lui	v0,0x123
- 12c:	3c0189ac 	lui	at,0x89ac
- 130:	64424568 	daddiu	v0,v0,17768
- 134:	0023082d 	daddu	at,at,v1
- 138:	0002103c 	dsll32	v0,v0,0x0
- 13c:	0041102d 	daddu	v0,v0,at
- 140:	8c42cdef 	lw	v0,-12817\(v0\)
- 144:	3c02abce 	lui	v0,0xabce
- 148:	3c012345 	lui	at,0x2345
- 14c:	6442ef01 	daddiu	v0,v0,-4351
- 150:	0023082d 	daddu	at,at,v1
- 154:	0002103c 	dsll32	v0,v0,0x0
- 158:	0041102d 	daddu	v0,v0,at
- 15c:	8c426789 	lw	v0,26505\(v0\)
- 160:	3c028000 	lui	v0,0x8000
- 164:	0043102d 	daddu	v0,v0,v1
- 168:	8c420000 	lw	v0,0\(v0\)
- 16c:	3c020000 	lui	v0,0x0
- 170:	3c010000 	lui	at,0x0
- 174:	6442ffff 	daddiu	v0,v0,-1
- 178:	0023082d 	daddu	at,at,v1
- 17c:	0002103c 	dsll32	v0,v0,0x0
- 180:	0041102d 	daddu	v0,v0,at
- 184:	8c420000 	lw	v0,0\(v0\)
- 188:	3c028000 	lui	v0,0x8000
- 18c:	0043102d 	daddu	v0,v0,v1
- 190:	8c42ffff 	lw	v0,-1\(v0\)
- 194:	3c020000 	lui	v0,0x0
- 198:	3c01abce 	lui	at,0xabce
- 19c:	64420001 	daddiu	v0,v0,1
- 1a0:	0023082d 	daddu	at,at,v1
- 1a4:	0002103c 	dsll32	v0,v0,0x0
- 1a8:	0041102d 	daddu	v0,v0,at
- 1ac:	8c42ef01 	lw	v0,-4351\(v0\)
- 1b0:	3c020123 	lui	v0,0x123
- 1b4:	0043102d 	daddu	v0,v0,v1
- 1b8:	8c424567 	lw	v0,17767\(v0\)
- 1bc:	3c010123 	lui	at,0x123
- 1c0:	64214568 	daddiu	at,at,17768
- 1c4:	00010c38 	dsll	at,at,0x10
- 1c8:	642189ac 	daddiu	at,at,-30292
- 1cc:	00010c38 	dsll	at,at,0x10
- 1d0:	0023082d 	daddu	at,at,v1
- 1d4:	ac22cdef 	sw	v0,-12817\(at\)
- 1d8:	3c01abce 	lui	at,0xabce
- 1dc:	6421ef01 	daddiu	at,at,-4351
- 1e0:	00010c38 	dsll	at,at,0x10
- 1e4:	64212345 	daddiu	at,at,9029
- 1e8:	00010c38 	dsll	at,at,0x10
- 1ec:	0023082d 	daddu	at,at,v1
- 1f0:	ac226789 	sw	v0,26505\(at\)
- 1f4:	3c018000 	lui	at,0x8000
- 1f8:	0023082d 	daddu	at,at,v1
- 1fc:	ac220000 	sw	v0,0\(at\)
- 200:	3c010000 	lui	at,0x0
- 204:	6421ffff 	daddiu	at,at,-1
- 208:	00010c38 	dsll	at,at,0x10
- 20c:	64210000 	daddiu	at,at,0
- 210:	00010c38 	dsll	at,at,0x10
- 214:	0023082d 	daddu	at,at,v1
- 218:	ac220000 	sw	v0,0\(at\)
- 21c:	3c018000 	lui	at,0x8000
- 220:	0023082d 	daddu	at,at,v1
- 224:	ac22ffff 	sw	v0,-1\(at\)
- 228:	3c010000 	lui	at,0x0
- 22c:	64210001 	daddiu	at,at,1
- 230:	00010c38 	dsll	at,at,0x10
- 234:	6421abce 	daddiu	at,at,-21554
- 238:	00010c38 	dsll	at,at,0x10
- 23c:	0023082d 	daddu	at,at,v1
- 240:	ac22ef01 	sw	v0,-4351\(at\)
- 244:	3c010123 	lui	at,0x123
- 248:	0023082d 	daddu	at,at,v1
- 24c:	ac224567 	sw	v0,17767\(at\)
- 250:	3c020123 	lui	v0,0x123
- 254:	34424567 	ori	v0,v0,0x4567
- 258:	00021438 	dsll	v0,v0,0x10
- 25c:	344289ab 	ori	v0,v0,0x89ab
- 260:	00021438 	dsll	v0,v0,0x10
- 264:	3442cdef 	ori	v0,v0,0xcdef
- 268:	3c02abcd 	lui	v0,0xabcd
- 26c:	3442ef01 	ori	v0,v0,0xef01
- 270:	00021438 	dsll	v0,v0,0x10
- 274:	34422345 	ori	v0,v0,0x2345
- 278:	00021438 	dsll	v0,v0,0x10
- 27c:	34426789 	ori	v0,v0,0x6789
- 280:	3c028000 	lui	v0,0x8000
- 284:	2402ffff 	li	v0,-1
- 288:	0002103c 	dsll32	v0,v0,0x0
- 28c:	3402abcd 	li	v0,0xabcd
- 290:	00021438 	dsll	v0,v0,0x10
- 294:	3442ef01 	ori	v0,v0,0xef01
- 298:	3c027fff 	lui	v0,0x7fff
- 29c:	3442ffff 	ori	v0,v0,0xffff
- 2a0:	3c020123 	lui	v0,0x123
- 2a4:	34424567 	ori	v0,v0,0x4567
+  e4:	0023082d 	daddu	at,at,v1
+  e8:	fc22ef01 	sd	v0,-4351\(at\)
+  ec:	3c010123 	lui	at,0x123
+  f0:	0023082d 	daddu	at,at,v1
+  f4:	fc224567 	sd	v0,17767\(at\)
+  f8:	3c020123 	lui	v0,0x123
+  fc:	34424567 	ori	v0,v0,0x4567
+ 100:	00021438 	dsll	v0,v0,0x10
+ 104:	344289ac 	ori	v0,v0,0x89ac
+ 108:	00021438 	dsll	v0,v0,0x10
+ 10c:	0043102d 	daddu	v0,v0,v1
+ 110:	8c42cdef 	lw	v0,-12817\(v0\)
+ 114:	3c02abcd 	lui	v0,0xabcd
+ 118:	3442ef01 	ori	v0,v0,0xef01
+ 11c:	00021438 	dsll	v0,v0,0x10
+ 120:	34422345 	ori	v0,v0,0x2345
+ 124:	00021438 	dsll	v0,v0,0x10
+ 128:	0043102d 	daddu	v0,v0,v1
+ 12c:	8c426789 	lw	v0,26505\(v0\)
+ 130:	3c028000 	lui	v0,0x8000
+ 134:	0043102d 	daddu	v0,v0,v1
+ 138:	8c420000 	lw	v0,0\(v0\)
+ 13c:	2402ffff 	li	v0,-1
+ 140:	0002103c 	dsll32	v0,v0,0x0
+ 144:	0043102d 	daddu	v0,v0,v1
+ 148:	8c420000 	lw	v0,0\(v0\)
+ 14c:	3c028000 	lui	v0,0x8000
+ 150:	0043102d 	daddu	v0,v0,v1
+ 154:	8c42ffff 	lw	v0,-1\(v0\)
+ 158:	3402abce 	li	v0,0xabce
+ 15c:	00021438 	dsll	v0,v0,0x10
+ 160:	0043102d 	daddu	v0,v0,v1
+ 164:	8c42ef01 	lw	v0,-4351\(v0\)
+ 168:	3c020123 	lui	v0,0x123
+ 16c:	0043102d 	daddu	v0,v0,v1
+ 170:	8c424567 	lw	v0,17767\(v0\)
+ 174:	3c010123 	lui	at,0x123
+ 178:	34214567 	ori	at,at,0x4567
+ 17c:	00010c38 	dsll	at,at,0x10
+ 180:	342189ac 	ori	at,at,0x89ac
+ 184:	00010c38 	dsll	at,at,0x10
+ 188:	0023082d 	daddu	at,at,v1
+ 18c:	ac22cdef 	sw	v0,-12817\(at\)
+ 190:	3c01abcd 	lui	at,0xabcd
+ 194:	3421ef01 	ori	at,at,0xef01
+ 198:	00010c38 	dsll	at,at,0x10
+ 19c:	34212345 	ori	at,at,0x2345
+ 1a0:	00010c38 	dsll	at,at,0x10
+ 1a4:	0023082d 	daddu	at,at,v1
+ 1a8:	ac226789 	sw	v0,26505\(at\)
+ 1ac:	3c018000 	lui	at,0x8000
+ 1b0:	0023082d 	daddu	at,at,v1
+ 1b4:	ac220000 	sw	v0,0\(at\)
+ 1b8:	2401ffff 	li	at,-1
+ 1bc:	0001083c 	dsll32	at,at,0x0
+ 1c0:	0023082d 	daddu	at,at,v1
+ 1c4:	ac220000 	sw	v0,0\(at\)
+ 1c8:	3c018000 	lui	at,0x8000
+ 1cc:	0023082d 	daddu	at,at,v1
+ 1d0:	ac22ffff 	sw	v0,-1\(at\)
+ 1d4:	3401abce 	li	at,0xabce
+ 1d8:	00010c38 	dsll	at,at,0x10
+ 1dc:	0023082d 	daddu	at,at,v1
+ 1e0:	ac22ef01 	sw	v0,-4351\(at\)
+ 1e4:	3c010123 	lui	at,0x123
+ 1e8:	0023082d 	daddu	at,at,v1
+ 1ec:	ac224567 	sw	v0,17767\(at\)
+ 1f0:	3c020123 	lui	v0,0x123
+ 1f4:	34424567 	ori	v0,v0,0x4567
+ 1f8:	00021438 	dsll	v0,v0,0x10
+ 1fc:	344289ab 	ori	v0,v0,0x89ab
+ 200:	00021438 	dsll	v0,v0,0x10
+ 204:	3442cdef 	ori	v0,v0,0xcdef
+ 208:	3c02abcd 	lui	v0,0xabcd
+ 20c:	3442ef01 	ori	v0,v0,0xef01
+ 210:	00021438 	dsll	v0,v0,0x10
+ 214:	34422345 	ori	v0,v0,0x2345
+ 218:	00021438 	dsll	v0,v0,0x10
+ 21c:	34426789 	ori	v0,v0,0x6789
+ 220:	3c028000 	lui	v0,0x8000
+ 224:	2402ffff 	li	v0,-1
+ 228:	0002103c 	dsll32	v0,v0,0x0
+ 22c:	3402abcd 	li	v0,0xabcd
+ 230:	00021438 	dsll	v0,v0,0x10
+ 234:	3442ef01 	ori	v0,v0,0xef01
+ 238:	3c027fff 	lui	v0,0x7fff
+ 23c:	3442ffff 	ori	v0,v0,0xffff
+ 240:	3c020123 	lui	v0,0x123
+ 244:	34424567 	ori	v0,v0,0x4567
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-n64-sym32.d b/gas/testsuite/gas/mips/ldstla-n64-sym32.d
new file mode 100644
index 000000000000..8d30cfb511c0
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-n64-sym32.d
@@ -0,0 +1,1017 @@
+#objdump: -dr
+#as: -64 -msym32 -G8 -EB
+#name: MIPS ld-st-la with sym32
+#source: ldstla-sym32.s
+
+.*file format .*
+
+Disassembly .*:
+
+0+00 <.*>:
+#
+# dla constants
+#
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x8000
+.*	lui	a0,0x8000
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0x7ff8
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0x7ff8
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0xfff8
+.*	lui	a0,0x7fff
+.*	ori	a0,a0,0xfff8
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abc
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0xdef0
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abc
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0xdef0
+.*	daddu	a0,a0,v1
+#
+# dla small_comm
+#
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+#
+# dla big_comm
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+#
+# dla small_data
+#
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,gp,0
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+#
+# dla big_data
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+#
+# dla extern
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	a0,a0,0
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+#
+# lw constants
+#
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	lw	a0,0\(a0\)
+.*	li	a0,0xa800
+.*	dsll32	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x8000
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x8000
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*	lui	a0,0x7fff
+.*	lw	a0,32760\(a0\)
+.*	lui	a0,0x7fff
+.*	daddu	a0,a0,v1
+.*	lw	a0,32760\(a0\)
+.*	li	a0,0x8000
+.*	dsll	a0,a0,0x10
+.*	lw	a0,-8\(a0\)
+.*	li	a0,0x8000
+.*	dsll	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,-8\(a0\)
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abd
+.*	dsll	a0,a0,0x10
+.*	lw	a0,-8464\(a0\)
+.*	lui	a0,0x1234
+.*	ori	a0,a0,0x5678
+.*	dsll	a0,a0,0x10
+.*	ori	a0,a0,0x9abd
+.*	dsll	a0,a0,0x10
+.*	daddu	a0,a0,v1
+.*	lw	a0,-8464\(a0\)
+#
+# lw small_comm
+#
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# lw big_comm
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# lw small_data
+#
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,v1,gp
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# lw big_data
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# lw extern
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	a0,a0,v1
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# sw constants
+#
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	sw	a0,0\(at\)
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*	lui	at,0x8000
+.*	sw	a0,0\(at\)
+.*	lui	at,0x8000
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*	lui	at,0x7fff
+.*	sw	a0,32760\(at\)
+.*	lui	at,0x7fff
+.*	daddu	at,at,v1
+.*	sw	a0,32760\(at\)
+.*	li	at,0x8000
+.*	dsll	at,at,0x10
+.*	sw	a0,-8\(at\)
+.*	li	at,0x8000
+.*	dsll	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,-8\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abd
+.*	dsll	at,at,0x10
+.*	sw	a0,-8464\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abd
+.*	dsll	at,at,0x10
+.*	daddu	at,at,v1
+.*	sw	a0,-8464\(at\)
+#
+# sw small_comm
+#
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# sw big_comm
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# sw small_data
+#
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(gp\)
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,v1,gp
+.*	sw	a0,0\(at\)
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# sw big_data
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# sw extern
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+#
+# usw constants
+#
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	li	at,0xa800
+.*	dsll32	at,at,0x10
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x8000
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x8000
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0x7ff8
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0x7ff8
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0xfff8
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x7fff
+.*	ori	at,at,0xfff8
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abc
+.*	dsll	at,at,0x10
+.*	ori	at,at,0xdef0
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x1234
+.*	ori	at,at,0x5678
+.*	dsll	at,at,0x10
+.*	ori	at,at,0x9abc
+.*	dsll	at,at,0x10
+.*	ori	at,at,0xdef0
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw small_comm
+#
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw big_comm
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_comm\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw small_data
+#
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	daddiu	at,gp,0
+.*: R_MIPS_GPREL16	small_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw big_data
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	big_data\+0x3
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# usw extern
+#
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern\+0x34000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	d?addiu	at,at,0
+.*: R_MIPS_LO16	extern\+0xfffffffffffcc000
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddu	at,at,v1
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# with sym32 off
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HIGHEST	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,a0,0
+.*: R_MIPS_HIGHER	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll32	a0,a0,0x0
+.*	daddu	a0,a0,at
+.*	lui	a0,0x0
+.*: R_MIPS_HIGHEST	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,a0,0
+.*: R_MIPS_HIGHER	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll32	a0,a0,0x0
+.*	daddu	a0,a0,at
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HIGHEST	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	at,at,0
+.*: R_MIPS_HIGHER	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll	at,at,0x10
+.*	daddiu	at,at,0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll	at,at,0x10
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HIGHEST	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	at,at,0
+.*: R_MIPS_HIGHER	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll	at,at,0x10
+.*	daddiu	at,at,0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	dsll	at,at,0x10
+.*	daddiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#
+# ...and back on again
+#
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	a0,a0,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	a0,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lw	a0,0\(a0\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	sw	a0,0\(at\)
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	lui	at,0x0
+.*: R_MIPS_HI16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	daddiu	at,at,0
+.*: R_MIPS_LO16	extern
+.*: R_MIPS_NONE	.*
+.*: R_MIPS_NONE	.*
+.*	swl	a0,0\(at\)
+.*	swr	a0,3\(at\)
+#pass
diff --git a/gas/testsuite/gas/mips/ldstla-n64.d b/gas/testsuite/gas/mips/ldstla-n64.d
index 7068b90adc7f..4425e9c71f6f 100644
--- a/gas/testsuite/gas/mips/ldstla-n64.d
+++ b/gas/testsuite/gas/mips/ldstla-n64.d
@@ -9,173 +9,149 @@ Disassembly of section \.text:
 
 0000000000000000 <\.text>:
    0:	3c020123 	lui	v0,0x123
-   4:	3c0189ac 	lui	at,0x89ac
-   8:	64424568 	daddiu	v0,v0,17768
-   c:	0023082d 	daddu	at,at,v1
-  10:	0002103c 	dsll32	v0,v0,0x0
-  14:	0041102d 	daddu	v0,v0,at
+   4:	34424567 	ori	v0,v0,0x4567
+   8:	00021438 	dsll	v0,v0,0x10
+   c:	344289ac 	ori	v0,v0,0x89ac
+  10:	00021438 	dsll	v0,v0,0x10
+  14:	0043102d 	daddu	v0,v0,v1
   18:	dc42cdef 	ld	v0,-12817\(v0\)
-  1c:	3c02abce 	lui	v0,0xabce
-  20:	3c012345 	lui	at,0x2345
-  24:	6442ef01 	daddiu	v0,v0,-4351
-  28:	0023082d 	daddu	at,at,v1
-  2c:	0002103c 	dsll32	v0,v0,0x0
-  30:	0041102d 	daddu	v0,v0,at
+  1c:	3c02abcd 	lui	v0,0xabcd
+  20:	3442ef01 	ori	v0,v0,0xef01
+  24:	00021438 	dsll	v0,v0,0x10
+  28:	34422345 	ori	v0,v0,0x2345
+  2c:	00021438 	dsll	v0,v0,0x10
+  30:	0043102d 	daddu	v0,v0,v1
   34:	dc426789 	ld	v0,26505\(v0\)
   38:	3c028000 	lui	v0,0x8000
   3c:	0043102d 	daddu	v0,v0,v1
   40:	dc420000 	ld	v0,0\(v0\)
-  44:	3c020000 	lui	v0,0x0
-  48:	3c010000 	lui	at,0x0
-  4c:	6442ffff 	daddiu	v0,v0,-1
-  50:	0023082d 	daddu	at,at,v1
-  54:	0002103c 	dsll32	v0,v0,0x0
-  58:	0041102d 	daddu	v0,v0,at
-  5c:	dc420000 	ld	v0,0\(v0\)
-  60:	3c028000 	lui	v0,0x8000
-  64:	0043102d 	daddu	v0,v0,v1
-  68:	dc42ffff 	ld	v0,-1\(v0\)
-  6c:	3c020000 	lui	v0,0x0
-  70:	3c01abce 	lui	at,0xabce
-  74:	64420001 	daddiu	v0,v0,1
-  78:	0023082d 	daddu	at,at,v1
-  7c:	0002103c 	dsll32	v0,v0,0x0
-  80:	0041102d 	daddu	v0,v0,at
-  84:	dc42ef01 	ld	v0,-4351\(v0\)
-  88:	3c020123 	lui	v0,0x123
-  8c:	0043102d 	daddu	v0,v0,v1
-  90:	dc424567 	ld	v0,17767\(v0\)
-  94:	3c010123 	lui	at,0x123
-  98:	64214568 	daddiu	at,at,17768
-  9c:	00010c38 	dsll	at,at,0x10
-  a0:	642189ac 	daddiu	at,at,-30292
-  a4:	00010c38 	dsll	at,at,0x10
-  a8:	0023082d 	daddu	at,at,v1
-  ac:	fc22cdef 	sd	v0,-12817\(at\)
-  b0:	3c01abce 	lui	at,0xabce
-  b4:	6421ef01 	daddiu	at,at,-4351
-  b8:	00010c38 	dsll	at,at,0x10
-  bc:	64212345 	daddiu	at,at,9029
-  c0:	00010c38 	dsll	at,at,0x10
-  c4:	0023082d 	daddu	at,at,v1
-  c8:	fc226789 	sd	v0,26505\(at\)
-  cc:	3c018000 	lui	at,0x8000
-  d0:	0023082d 	daddu	at,at,v1
-  d4:	fc220000 	sd	v0,0\(at\)
-  d8:	3c010000 	lui	at,0x0
-  dc:	6421ffff 	daddiu	at,at,-1
+  44:	2402ffff 	li	v0,-1
+  48:	0002103c 	dsll32	v0,v0,0x0
+  4c:	0043102d 	daddu	v0,v0,v1
+  50:	dc420000 	ld	v0,0\(v0\)
+  54:	3c028000 	lui	v0,0x8000
+  58:	0043102d 	daddu	v0,v0,v1
+  5c:	dc42ffff 	ld	v0,-1\(v0\)
+  60:	3402abce 	li	v0,0xabce
+  64:	00021438 	dsll	v0,v0,0x10
+  68:	0043102d 	daddu	v0,v0,v1
+  6c:	dc42ef01 	ld	v0,-4351\(v0\)
+  70:	3c020123 	lui	v0,0x123
+  74:	0043102d 	daddu	v0,v0,v1
+  78:	dc424567 	ld	v0,17767\(v0\)
+  7c:	3c010123 	lui	at,0x123
+  80:	34214567 	ori	at,at,0x4567
+  84:	00010c38 	dsll	at,at,0x10
+  88:	342189ac 	ori	at,at,0x89ac
+  8c:	00010c38 	dsll	at,at,0x10
+  90:	0023082d 	daddu	at,at,v1
+  94:	fc22cdef 	sd	v0,-12817\(at\)
+  98:	3c01abcd 	lui	at,0xabcd
+  9c:	3421ef01 	ori	at,at,0xef01
+  a0:	00010c38 	dsll	at,at,0x10
+  a4:	34212345 	ori	at,at,0x2345
+  a8:	00010c38 	dsll	at,at,0x10
+  ac:	0023082d 	daddu	at,at,v1
+  b0:	fc226789 	sd	v0,26505\(at\)
+  b4:	3c018000 	lui	at,0x8000
+  b8:	0023082d 	daddu	at,at,v1
+  bc:	fc220000 	sd	v0,0\(at\)
+  c0:	2401ffff 	li	at,-1
+  c4:	0001083c 	dsll32	at,at,0x0
+  c8:	0023082d 	daddu	at,at,v1
+  cc:	fc220000 	sd	v0,0\(at\)
+  d0:	3c018000 	lui	at,0x8000
+  d4:	0023082d 	daddu	at,at,v1
+  d8:	fc22ffff 	sd	v0,-1\(at\)
+  dc:	3401abce 	li	at,0xabce
   e0:	00010c38 	dsll	at,at,0x10
-  e4:	64210000 	daddiu	at,at,0
-  e8:	00010c38 	dsll	at,at,0x10
-  ec:	0023082d 	daddu	at,at,v1
-  f0:	fc220000 	sd	v0,0\(at\)
-  f4:	3c018000 	lui	at,0x8000
-  f8:	0023082d 	daddu	at,at,v1
-  fc:	fc22ffff 	sd	v0,-1\(at\)
- 100:	3c010000 	lui	at,0x0
- 104:	64210001 	daddiu	at,at,1
- 108:	00010c38 	dsll	at,at,0x10
- 10c:	6421abce 	daddiu	at,at,-21554
- 110:	00010c38 	dsll	at,at,0x10
- 114:	0023082d 	daddu	at,at,v1
- 118:	fc22ef01 	sd	v0,-4351\(at\)
- 11c:	3c010123 	lui	at,0x123
- 120:	0023082d 	daddu	at,at,v1
- 124:	fc224567 	sd	v0,17767\(at\)
- 128:	3c020123 	lui	v0,0x123
- 12c:	3c0189ac 	lui	at,0x89ac
- 130:	64424568 	daddiu	v0,v0,17768
- 134:	0023082d 	daddu	at,at,v1
- 138:	0002103c 	dsll32	v0,v0,0x0
- 13c:	0041102d 	daddu	v0,v0,at
- 140:	8c42cdef 	lw	v0,-12817\(v0\)
- 144:	3c02abce 	lui	v0,0xabce
- 148:	3c012345 	lui	at,0x2345
- 14c:	6442ef01 	daddiu	v0,v0,-4351
- 150:	0023082d 	daddu	at,at,v1
- 154:	0002103c 	dsll32	v0,v0,0x0
- 158:	0041102d 	daddu	v0,v0,at
- 15c:	8c426789 	lw	v0,26505\(v0\)
- 160:	3c028000 	lui	v0,0x8000
- 164:	0043102d 	daddu	v0,v0,v1
- 168:	8c420000 	lw	v0,0\(v0\)
- 16c:	3c020000 	lui	v0,0x0
- 170:	3c010000 	lui	at,0x0
- 174:	6442ffff 	daddiu	v0,v0,-1
- 178:	0023082d 	daddu	at,at,v1
- 17c:	0002103c 	dsll32	v0,v0,0x0
- 180:	0041102d 	daddu	v0,v0,at
- 184:	8c420000 	lw	v0,0\(v0\)
- 188:	3c028000 	lui	v0,0x8000
- 18c:	0043102d 	daddu	v0,v0,v1
- 190:	8c42ffff 	lw	v0,-1\(v0\)
- 194:	3c020000 	lui	v0,0x0
- 198:	3c01abce 	lui	at,0xabce
- 19c:	64420001 	daddiu	v0,v0,1
- 1a0:	0023082d 	daddu	at,at,v1
- 1a4:	0002103c 	dsll32	v0,v0,0x0
- 1a8:	0041102d 	daddu	v0,v0,at
- 1ac:	8c42ef01 	lw	v0,-4351\(v0\)
- 1b0:	3c020123 	lui	v0,0x123
- 1b4:	0043102d 	daddu	v0,v0,v1
- 1b8:	8c424567 	lw	v0,17767\(v0\)
- 1bc:	3c010123 	lui	at,0x123
- 1c0:	64214568 	daddiu	at,at,17768
- 1c4:	00010c38 	dsll	at,at,0x10
- 1c8:	642189ac 	daddiu	at,at,-30292
- 1cc:	00010c38 	dsll	at,at,0x10
- 1d0:	0023082d 	daddu	at,at,v1
- 1d4:	ac22cdef 	sw	v0,-12817\(at\)
- 1d8:	3c01abce 	lui	at,0xabce
- 1dc:	6421ef01 	daddiu	at,at,-4351
- 1e0:	00010c38 	dsll	at,at,0x10
- 1e4:	64212345 	daddiu	at,at,9029
- 1e8:	00010c38 	dsll	at,at,0x10
- 1ec:	0023082d 	daddu	at,at,v1
- 1f0:	ac226789 	sw	v0,26505\(at\)
- 1f4:	3c018000 	lui	at,0x8000
- 1f8:	0023082d 	daddu	at,at,v1
- 1fc:	ac220000 	sw	v0,0\(at\)
- 200:	3c010000 	lui	at,0x0
- 204:	6421ffff 	daddiu	at,at,-1
- 208:	00010c38 	dsll	at,at,0x10
- 20c:	64210000 	daddiu	at,at,0
- 210:	00010c38 	dsll	at,at,0x10
- 214:	0023082d 	daddu	at,at,v1
- 218:	ac220000 	sw	v0,0\(at\)
- 21c:	3c018000 	lui	at,0x8000
- 220:	0023082d 	daddu	at,at,v1
- 224:	ac22ffff 	sw	v0,-1\(at\)
- 228:	3c010000 	lui	at,0x0
- 22c:	64210001 	daddiu	at,at,1
- 230:	00010c38 	dsll	at,at,0x10
- 234:	6421abce 	daddiu	at,at,-21554
- 238:	00010c38 	dsll	at,at,0x10
- 23c:	0023082d 	daddu	at,at,v1
- 240:	ac22ef01 	sw	v0,-4351\(at\)
- 244:	3c010123 	lui	at,0x123
- 248:	0023082d 	daddu	at,at,v1
- 24c:	ac224567 	sw	v0,17767\(at\)
- 250:	3c020123 	lui	v0,0x123
- 254:	34424567 	ori	v0,v0,0x4567
- 258:	00021438 	dsll	v0,v0,0x10
- 25c:	344289ab 	ori	v0,v0,0x89ab
- 260:	00021438 	dsll	v0,v0,0x10
- 264:	3442cdef 	ori	v0,v0,0xcdef
- 268:	3c02abcd 	lui	v0,0xabcd
- 26c:	3442ef01 	ori	v0,v0,0xef01
- 270:	00021438 	dsll	v0,v0,0x10
- 274:	34422345 	ori	v0,v0,0x2345
- 278:	00021438 	dsll	v0,v0,0x10
- 27c:	34426789 	ori	v0,v0,0x6789
- 280:	3c028000 	lui	v0,0x8000
- 284:	2402ffff 	li	v0,-1
- 288:	0002103c 	dsll32	v0,v0,0x0
- 28c:	3402abcd 	li	v0,0xabcd
- 290:	00021438 	dsll	v0,v0,0x10
- 294:	3442ef01 	ori	v0,v0,0xef01
- 298:	3c027fff 	lui	v0,0x7fff
- 29c:	3442ffff 	ori	v0,v0,0xffff
- 2a0:	3c020123 	lui	v0,0x123
- 2a4:	34424567 	ori	v0,v0,0x4567
+  e4:	0023082d 	daddu	at,at,v1
+  e8:	fc22ef01 	sd	v0,-4351\(at\)
+  ec:	3c010123 	lui	at,0x123
+  f0:	0023082d 	daddu	at,at,v1
+  f4:	fc224567 	sd	v0,17767\(at\)
+  f8:	3c020123 	lui	v0,0x123
+  fc:	34424567 	ori	v0,v0,0x4567
+ 100:	00021438 	dsll	v0,v0,0x10
+ 104:	344289ac 	ori	v0,v0,0x89ac
+ 108:	00021438 	dsll	v0,v0,0x10
+ 10c:	0043102d 	daddu	v0,v0,v1
+ 110:	8c42cdef 	lw	v0,-12817\(v0\)
+ 114:	3c02abcd 	lui	v0,0xabcd
+ 118:	3442ef01 	ori	v0,v0,0xef01
+ 11c:	00021438 	dsll	v0,v0,0x10
+ 120:	34422345 	ori	v0,v0,0x2345
+ 124:	00021438 	dsll	v0,v0,0x10
+ 128:	0043102d 	daddu	v0,v0,v1
+ 12c:	8c426789 	lw	v0,26505\(v0\)
+ 130:	3c028000 	lui	v0,0x8000
+ 134:	0043102d 	daddu	v0,v0,v1
+ 138:	8c420000 	lw	v0,0\(v0\)
+ 13c:	2402ffff 	li	v0,-1
+ 140:	0002103c 	dsll32	v0,v0,0x0
+ 144:	0043102d 	daddu	v0,v0,v1
+ 148:	8c420000 	lw	v0,0\(v0\)
+ 14c:	3c028000 	lui	v0,0x8000
+ 150:	0043102d 	daddu	v0,v0,v1
+ 154:	8c42ffff 	lw	v0,-1\(v0\)
+ 158:	3402abce 	li	v0,0xabce
+ 15c:	00021438 	dsll	v0,v0,0x10
+ 160:	0043102d 	daddu	v0,v0,v1
+ 164:	8c42ef01 	lw	v0,-4351\(v0\)
+ 168:	3c020123 	lui	v0,0x123
+ 16c:	0043102d 	daddu	v0,v0,v1
+ 170:	8c424567 	lw	v0,17767\(v0\)
+ 174:	3c010123 	lui	at,0x123
+ 178:	34214567 	ori	at,at,0x4567
+ 17c:	00010c38 	dsll	at,at,0x10
+ 180:	342189ac 	ori	at,at,0x89ac
+ 184:	00010c38 	dsll	at,at,0x10
+ 188:	0023082d 	daddu	at,at,v1
+ 18c:	ac22cdef 	sw	v0,-12817\(at\)
+ 190:	3c01abcd 	lui	at,0xabcd
+ 194:	3421ef01 	ori	at,at,0xef01
+ 198:	00010c38 	dsll	at,at,0x10
+ 19c:	34212345 	ori	at,at,0x2345
+ 1a0:	00010c38 	dsll	at,at,0x10
+ 1a4:	0023082d 	daddu	at,at,v1
+ 1a8:	ac226789 	sw	v0,26505\(at\)
+ 1ac:	3c018000 	lui	at,0x8000
+ 1b0:	0023082d 	daddu	at,at,v1
+ 1b4:	ac220000 	sw	v0,0\(at\)
+ 1b8:	2401ffff 	li	at,-1
+ 1bc:	0001083c 	dsll32	at,at,0x0
+ 1c0:	0023082d 	daddu	at,at,v1
+ 1c4:	ac220000 	sw	v0,0\(at\)
+ 1c8:	3c018000 	lui	at,0x8000
+ 1cc:	0023082d 	daddu	at,at,v1
+ 1d0:	ac22ffff 	sw	v0,-1\(at\)
+ 1d4:	3401abce 	li	at,0xabce
+ 1d8:	00010c38 	dsll	at,at,0x10
+ 1dc:	0023082d 	daddu	at,at,v1
+ 1e0:	ac22ef01 	sw	v0,-4351\(at\)
+ 1e4:	3c010123 	lui	at,0x123
+ 1e8:	0023082d 	daddu	at,at,v1
+ 1ec:	ac224567 	sw	v0,17767\(at\)
+ 1f0:	3c020123 	lui	v0,0x123
+ 1f4:	34424567 	ori	v0,v0,0x4567
+ 1f8:	00021438 	dsll	v0,v0,0x10
+ 1fc:	344289ab 	ori	v0,v0,0x89ab
+ 200:	00021438 	dsll	v0,v0,0x10
+ 204:	3442cdef 	ori	v0,v0,0xcdef
+ 208:	3c02abcd 	lui	v0,0xabcd
+ 20c:	3442ef01 	ori	v0,v0,0xef01
+ 210:	00021438 	dsll	v0,v0,0x10
+ 214:	34422345 	ori	v0,v0,0x2345
+ 218:	00021438 	dsll	v0,v0,0x10
+ 21c:	34426789 	ori	v0,v0,0x6789
+ 220:	3c028000 	lui	v0,0x8000
+ 224:	2402ffff 	li	v0,-1
+ 228:	0002103c 	dsll32	v0,v0,0x0
+ 22c:	3402abcd 	li	v0,0xabcd
+ 230:	00021438 	dsll	v0,v0,0x10
+ 234:	3442ef01 	ori	v0,v0,0xef01
+ 238:	3c027fff 	lui	v0,0x7fff
+ 23c:	3442ffff 	ori	v0,v0,0xffff
+ 240:	3c020123 	lui	v0,0x123
+ 244:	34424567 	ori	v0,v0,0x4567
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/ldstla-sym32.s b/gas/testsuite/gas/mips/ldstla-sym32.s
new file mode 100644
index 000000000000..d89166df97e4
--- /dev/null
+++ b/gas/testsuite/gas/mips/ldstla-sym32.s
@@ -0,0 +1,176 @@
+	dla	$4,0xa800000000000000
+	dla	$4,0xa800000000000000($3)
+	dla	$4,0xffffffff80000000
+	dla	$4,0xffffffff80000000($3)
+	dla	$4,0x000000007fff7ff8
+	dla	$4,0x000000007fff7ff8($3)
+	dla	$4,0x000000007ffffff8
+	dla	$4,0x000000007ffffff8($3)
+	dla	$4,0x123456789abcdef0
+	dla	$4,0x123456789abcdef0($3)
+
+	dla	$4,small_comm
+	dla	$4,small_comm($3)
+	dla	$4,small_comm+3
+	dla	$4,small_comm+3($3)
+
+	dla	$4,big_comm
+	dla	$4,big_comm($3)
+	dla	$4,big_comm+3
+	dla	$4,big_comm+3($3)
+
+	dla	$4,small_data
+	dla	$4,small_data($3)
+	dla	$4,small_data+3
+	dla	$4,small_data+3($3)
+
+	dla	$4,big_data
+	dla	$4,big_data($3)
+	dla	$4,big_data+3
+	dla	$4,big_data+3($3)
+
+	dla	$4,extern
+	dla	$4,extern($3)
+	dla	$4,extern + 0x34000
+	dla	$4,extern + 0x34000($3)
+	dla	$4,extern - 0x34000
+	dla	$4,extern - 0x34000($3)
+
+	lw	$4,0xa800000000000000
+	lw	$4,0xa800000000000000($3)
+	lw	$4,0xffffffff80000000
+	lw	$4,0xffffffff80000000($3)
+	lw	$4,0x000000007fff7ff8
+	lw	$4,0x000000007fff7ff8($3)
+	lw	$4,0x000000007ffffff8
+	lw	$4,0x000000007ffffff8($3)
+	lw	$4,0x123456789abcdef0
+	lw	$4,0x123456789abcdef0($3)
+
+	lw	$4,small_comm
+	lw	$4,small_comm($3)
+	lw	$4,small_comm+3
+	lw	$4,small_comm+3($3)
+
+	lw	$4,big_comm
+	lw	$4,big_comm($3)
+	lw	$4,big_comm+3
+	lw	$4,big_comm+3($3)
+
+	lw	$4,small_data
+	lw	$4,small_data($3)
+	lw	$4,small_data+3
+	lw	$4,small_data+3($3)
+
+	lw	$4,big_data
+	lw	$4,big_data($3)
+	lw	$4,big_data+3
+	lw	$4,big_data+3($3)
+
+	lw	$4,extern
+	lw	$4,extern($3)
+	lw	$4,extern + 0x34000
+	lw	$4,extern + 0x34000($3)
+	lw	$4,extern - 0x34000
+	lw	$4,extern - 0x34000($3)
+
+	sw	$4,0xa800000000000000
+	sw	$4,0xa800000000000000($3)
+	sw	$4,0xffffffff80000000
+	sw	$4,0xffffffff80000000($3)
+	sw	$4,0x000000007fff7ff8
+	sw	$4,0x000000007fff7ff8($3)
+	sw	$4,0x000000007ffffff8
+	sw	$4,0x000000007ffffff8($3)
+	sw	$4,0x123456789abcdef0
+	sw	$4,0x123456789abcdef0($3)
+
+	sw	$4,small_comm
+	sw	$4,small_comm($3)
+	sw	$4,small_comm+3
+	sw	$4,small_comm+3($3)
+
+	sw	$4,big_comm
+	sw	$4,big_comm($3)
+	sw	$4,big_comm+3
+	sw	$4,big_comm+3($3)
+
+	sw	$4,small_data
+	sw	$4,small_data($3)
+	sw	$4,small_data+3
+	sw	$4,small_data+3($3)
+
+	sw	$4,big_data
+	sw	$4,big_data($3)
+	sw	$4,big_data+3
+	sw	$4,big_data+3($3)
+
+	sw	$4,extern
+	sw	$4,extern($3)
+	sw	$4,extern + 0x34000
+	sw	$4,extern + 0x34000($3)
+	sw	$4,extern - 0x34000
+	sw	$4,extern - 0x34000($3)
+
+	usw	$4,0xa800000000000000
+	usw	$4,0xa800000000000000($3)
+	usw	$4,0xffffffff80000000
+	usw	$4,0xffffffff80000000($3)
+	usw	$4,0x000000007fff7ff8
+	usw	$4,0x000000007fff7ff8($3)
+	usw	$4,0x000000007ffffff8
+	usw	$4,0x000000007ffffff8($3)
+	usw	$4,0x123456789abcdef0
+	usw	$4,0x123456789abcdef0($3)
+
+	usw	$4,small_comm
+	usw	$4,small_comm($3)
+	usw	$4,small_comm+3
+	usw	$4,small_comm+3($3)
+
+	usw	$4,big_comm
+	usw	$4,big_comm($3)
+	usw	$4,big_comm+3
+	usw	$4,big_comm+3($3)
+
+	usw	$4,small_data
+	usw	$4,small_data($3)
+	usw	$4,small_data+3
+	usw	$4,small_data+3($3)
+
+	usw	$4,big_data
+	usw	$4,big_data($3)
+	usw	$4,big_data+3
+	usw	$4,big_data+3($3)
+
+	usw	$4,extern
+	usw	$4,extern($3)
+	usw	$4,extern + 0x34000
+	usw	$4,extern + 0x34000($3)
+	usw	$4,extern - 0x34000
+	usw	$4,extern - 0x34000($3)
+
+	.set	nosym32
+	dla	$4,extern
+	lw	$4,extern
+	sw	$4,extern
+	usw	$4,extern
+
+	.set	sym32
+	dla	$4,extern
+	lw	$4,extern
+	sw	$4,extern
+	usw	$4,extern
+
+	.section	.sdata
+	.globl	small_data
+small_data:
+	.fill	16
+
+	.data
+	.globl	big_data
+big_data:
+	.fill	16
+
+	.comm	small_comm,8
+	.comm	big_comm,16
diff --git a/gas/testsuite/gas/mips/lif-empic.d b/gas/testsuite/gas/mips/lif-empic.d
deleted file mode 100644
index f81b68d4737e..000000000000
--- a/gas/testsuite/gas/mips/lif-empic.d
+++ /dev/null
@@ -1,24 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS lifloat-empic
-#as: -32 -mips1 -membedded-pic --defsym EMPIC=1
-#source: lifloat.s
-
-# Test the li.d and li.s macros with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> addiu	at,gp,-16384
-[ 	]*0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.rdata.*
-0+0004 <[^>]*> lw	a0,0\(at\)
-0+0008 <[^>]*> lw	a1,4\(at\)
-0+000c <[^>]*> lwc1	\$f[45],-16368\(gp\)
-[ 	]*c: [A-Z0-9_]*LITERAL[A-Z0-9_]*	.lit8.*
-0+0010 <[^>]*> lwc1	\$f[45],-16364\(gp\)
-[ 	]*10: [A-Z0-9_]*LITERAL[A-Z0-9_]*	.lit8.*
-0+0014 <[^>]*> lui	a0,0x3f8f
-0+0018 <[^>]*> ori	a0,a0,0xcd36
-0+001c <[^>]*> lui	at,0x3f8f
-0+0020 <[^>]*> ori	at,at,0xcd36
-0+0024 <[^>]*> mtc1	at,\$f4
-	...
diff --git a/gas/testsuite/gas/mips/lifloat.s b/gas/testsuite/gas/mips/lifloat.s
index 3977f0e7d4e6..0760b86d3ef4 100644
--- a/gas/testsuite/gas/mips/lifloat.s
+++ b/gas/testsuite/gas/mips/lifloat.s
@@ -18,7 +18,3 @@ foo:
 	nop
 	nop
 	.endif
-	.ifdef	EMPIC
-	nop
-	nop
-	.endif
diff --git a/gas/testsuite/gas/mips/mips-abi32-pic.d b/gas/testsuite/gas/mips/mips-abi32-pic.d
index e1ed67790daf..fd18bf81e9a4 100644
--- a/gas/testsuite/gas/mips/mips-abi32-pic.d
+++ b/gas/testsuite/gas/mips/mips-abi32-pic.d
@@ -15,103 +15,85 @@ Disassembly of section .text:
   14:	3c041234 	lui	a0,0x1234
   18:	34845678 	ori	a0,a0,0x5678
   1c:	8f840000 	lw	a0,0\(gp\)
-  20:	00000000 	nop
-  24:	24840000 	addiu	a0,a0,0
-  28:	8f840000 	lw	a0,0\(gp\)
-  2c:	00000000 	nop
-  30:	24840000 	addiu	a0,a0,0
-  34:	8f840000 	lw	a0,0\(gp\)
+  20:	24840000 	addiu	a0,a0,0
+  24:	8f840000 	lw	a0,0\(gp\)
+  28:	24840000 	addiu	a0,a0,0
+  2c:	8f840000 	lw	a0,0\(gp\)
+  30:	2484015c 	addiu	a0,a0,348
+  34:	10000049 	b	15c <[^>]*>
   38:	00000000 	nop
-  3c:	248401a4 	addiu	a0,a0,420
-  40:	10000058 	b	1a4 <[^>]*>
-  44:	00000000 	nop
-  48:	8f990000 	lw	t9,0\(gp\)
-  4c:	00000000 	nop
-  50:	273901a4 	addiu	t9,t9,420
-  54:	0320f809 	jalr	t9
-  58:	00000000 	nop
-  5c:	8fbc0008 	lw	gp,8\(sp\)
-  60:	8f840000 	lw	a0,0\(gp\)
-  64:	00000000 	nop
-  68:	24840000 	addiu	a0,a0,0
-  6c:	8c840000 	lw	a0,0\(a0\)
-  70:	8f840000 	lw	a0,0\(gp\)
-  74:	00000000 	nop
-  78:	24840000 	addiu	a0,a0,0
-  7c:	8c840000 	lw	a0,0\(a0\)
-  80:	8f840000 	lw	a0,0\(gp\)
-  84:	00000000 	nop
-  88:	248401a4 	addiu	a0,a0,420
-  8c:	8c840000 	lw	a0,0\(a0\)
-  90:	8f810000 	lw	at,0\(gp\)
-  94:	00000000 	nop
-  98:	8c240000 	lw	a0,0\(at\)
-  9c:	8c250004 	lw	a1,4\(at\)
-  a0:	8f810000 	lw	at,0\(gp\)
-  a4:	00000000 	nop
-  a8:	8c240000 	lw	a0,0\(at\)
-  ac:	8c250004 	lw	a1,4\(at\)
+  3c:	8f990000 	lw	t9,0\(gp\)
+  40:	2739015c 	addiu	t9,t9,348
+  44:	0320f809 	jalr	t9
+  48:	00000000 	nop
+  4c:	8fbc0008 	lw	gp,8\(sp\)
+  50:	8f840000 	lw	a0,0\(gp\)
+  54:	24840000 	addiu	a0,a0,0
+  58:	8c840000 	lw	a0,0\(a0\)
+  5c:	8f840000 	lw	a0,0\(gp\)
+  60:	24840000 	addiu	a0,a0,0
+  64:	8c840000 	lw	a0,0\(a0\)
+  68:	8f840000 	lw	a0,0\(gp\)
+  6c:	2484015c 	addiu	a0,a0,348
+  70:	8c840000 	lw	a0,0\(a0\)
+  74:	8f810000 	lw	at,0\(gp\)
+  78:	8c240000 	lw	a0,0\(at\)
+  7c:	8c250004 	lw	a1,4\(at\)
+  80:	8f810000 	lw	at,0\(gp\)
+  84:	8c240000 	lw	a0,0\(at\)
+  88:	8c250004 	lw	a1,4\(at\)
+  8c:	8f810000 	lw	at,0\(gp\)
+  90:	8c24015c 	lw	a0,348\(at\)
+  94:	8c250160 	lw	a1,352\(at\)
+  98:	8f810000 	lw	at,0\(gp\)
+  9c:	24210000 	addiu	at,at,0
+  a0:	ac240000 	sw	a0,0\(at\)
+  a4:	8f810000 	lw	at,0\(gp\)
+  a8:	24210000 	addiu	at,at,0
+  ac:	ac240000 	sw	a0,0\(at\)
   b0:	8f810000 	lw	at,0\(gp\)
-  b4:	00000000 	nop
-  b8:	8c2401a4 	lw	a0,420\(at\)
-  bc:	8c2501a8 	lw	a1,424\(at\)
-  c0:	8f810000 	lw	at,0\(gp\)
-  c4:	00000000 	nop
-  c8:	24210000 	addiu	at,at,0
-  cc:	ac240000 	sw	a0,0\(at\)
-  d0:	8f810000 	lw	at,0\(gp\)
-  d4:	00000000 	nop
-  d8:	24210000 	addiu	at,at,0
-  dc:	ac240000 	sw	a0,0\(at\)
+  b4:	ac240000 	sw	a0,0\(at\)
+  b8:	ac250004 	sw	a1,4\(at\)
+  bc:	8f810000 	lw	at,0\(gp\)
+  c0:	ac240000 	sw	a0,0\(at\)
+  c4:	ac250004 	sw	a1,4\(at\)
+  c8:	8f810000 	lw	at,0\(gp\)
+  cc:	24210000 	addiu	at,at,0
+  d0:	80240000 	lb	a0,0\(at\)
+  d4:	90210001 	lbu	at,1\(at\)
+  d8:	00042200 	sll	a0,a0,0x8
+  dc:	00812025 	or	a0,a0,at
   e0:	8f810000 	lw	at,0\(gp\)
-  e4:	00000000 	nop
-  e8:	ac240000 	sw	a0,0\(at\)
-  ec:	ac250004 	sw	a1,4\(at\)
-  f0:	8f810000 	lw	at,0\(gp\)
-  f4:	00000000 	nop
-  f8:	ac240000 	sw	a0,0\(at\)
-  fc:	ac250004 	sw	a1,4\(at\)
+  e4:	24210000 	addiu	at,at,0
+  e8:	a0240001 	sb	a0,1\(at\)
+  ec:	00042202 	srl	a0,a0,0x8
+  f0:	a0240000 	sb	a0,0\(at\)
+  f4:	90210001 	lbu	at,1\(at\)
+  f8:	00042200 	sll	a0,a0,0x8
+  fc:	00812025 	or	a0,a0,at
  100:	8f810000 	lw	at,0\(gp\)
- 104:	00000000 	nop
- 108:	24210000 	addiu	at,at,0
- 10c:	80240000 	lb	a0,0\(at\)
- 110:	90210001 	lbu	at,1\(at\)
- 114:	00042200 	sll	a0,a0,0x8
- 118:	00812025 	or	a0,a0,at
- 11c:	8f810000 	lw	at,0\(gp\)
- 120:	00000000 	nop
- 124:	24210000 	addiu	at,at,0
- 128:	a0240001 	sb	a0,1\(at\)
- 12c:	00042202 	srl	a0,a0,0x8
- 130:	a0240000 	sb	a0,0\(at\)
- 134:	90210001 	lbu	at,1\(at\)
- 138:	00042200 	sll	a0,a0,0x8
- 13c:	00812025 	or	a0,a0,at
+ 104:	24210000 	addiu	at,at,0
+ 108:	88240000 	lwl	a0,0\(at\)
+ 10c:	98240003 	lwr	a0,3\(at\)
+ 110:	8f810000 	lw	at,0\(gp\)
+ 114:	24210000 	addiu	at,at,0
+ 118:	a8240000 	swl	a0,0\(at\)
+ 11c:	b8240003 	swr	a0,3\(at\)
+ 120:	3c043ff0 	lui	a0,0x3ff0
+ 124:	00002821 	move	a1,zero
+ 128:	8f810000 	lw	at,0\(gp\)
+ 12c:	8c240000 	lw	a0,0\(at\)
+ 130:	8c250004 	lw	a1,4\(at\)
+ 134:	3c013ff0 	lui	at,0x3ff0
+ 138:	44810800 	mtc1	at,\$f1
+ 13c:	44800000 	mtc1	zero,\$f0
  140:	8f810000 	lw	at,0\(gp\)
- 144:	00000000 	nop
- 148:	24210000 	addiu	at,at,0
- 14c:	88240000 	lwl	a0,0\(at\)
- 150:	98240003 	lwr	a0,3\(at\)
- 154:	8f810000 	lw	at,0\(gp\)
- 158:	00000000 	nop
- 15c:	24210000 	addiu	at,at,0
- 160:	a8240000 	swl	a0,0\(at\)
- 164:	b8240003 	swr	a0,3\(at\)
- 168:	3c043ff0 	lui	a0,0x3ff0
- 16c:	00002821 	move	a1,zero
- 170:	8f810000 	lw	at,0\(gp\)
- 174:	8c240000 	lw	a0,0\(at\)
- 178:	8c250004 	lw	a1,4\(at\)
- 17c:	3c013ff0 	lui	at,0x3ff0
- 180:	44810800 	mtc1	at,\$f1
- 184:	44800000 	mtc1	zero,\$f0
- 188:	8f810000 	lw	at,0\(gp\)
- 18c:	d4200008 	ldc1	\$f0,8\(at\)
- 190:	24a40064 	addiu	a0,a1,100
- 194:	2c840001 	sltiu	a0,a0,1
- 198:	24a40064 	addiu	a0,a1,100
- 19c:	0004202b 	sltu	a0,zero,a0
- 1a0:	00a02021 	move	a0,a1
+ 144:	d4200008 	ldc1	\$f0,8\(at\)
+ 148:	24a40064 	addiu	a0,a1,100
+ 14c:	2c840001 	sltiu	a0,a0,1
+ 150:	24a40064 	addiu	a0,a1,100
+ 154:	0004202b 	sltu	a0,zero,a0
+ 158:	00a02021 	move	a0,a1
 
-0+01a4 <[^>]*>:
+0+015c <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-abi32-pic2.d b/gas/testsuite/gas/mips/mips-abi32-pic2.d
index 1f3811eb3be5..412416e4f4bf 100644
--- a/gas/testsuite/gas/mips/mips-abi32-pic2.d
+++ b/gas/testsuite/gas/mips/mips-abi32-pic2.d
@@ -13,62 +13,59 @@ Disassembly of section \.text:
 0+00c <[^>]*> afbc0008 	sw	gp,8\(sp\)
 0+010 <[^>]*> 8f990000 	lw	t9,0\(gp\)
 			10: R_MIPS_GOT16	\.text
-0+014 <[^>]*> 00000000 	nop
-0+018 <[^>]*> 273900d8 	addiu	t9,t9,216
-			18: R_MIPS_LO16	\.text
-0+01c <[^>]*> 0320f809 	jalr	t9
-0+020 <[^>]*> 00000000 	nop
-0+024 <[^>]*> 8fbc0008 	lw	gp,8\(sp\)
-0+028 <[^>]*> 00000000 	nop
-0+02c <[^>]*> 0320f809 	jalr	t9
-0+030 <[^>]*> 00000000 	nop
-0+034 <[^>]*> 8fbc0008 	lw	gp,8\(sp\)
-0+038 <[^>]*> 3c1c0000 	lui	gp,0x0
-			38: R_MIPS_HI16	_gp_disp
-0+03c <[^>]*> 279c0000 	addiu	gp,gp,0
-			3c: R_MIPS_LO16	_gp_disp
-0+040 <[^>]*> 0399e021 	addu	gp,gp,t9
-0+044 <[^>]*> 3c010001 	lui	at,0x1
-0+048 <[^>]*> 003d0821 	addu	at,at,sp
-0+04c <[^>]*> ac3c8000 	sw	gp,-32768\(at\)
-0+050 <[^>]*> 8f990000 	lw	t9,0\(gp\)
-			50: R_MIPS_GOT16	\.text
-0+054 <[^>]*> 00000000 	nop
-0+058 <[^>]*> 273900d8 	addiu	t9,t9,216
-			58: R_MIPS_LO16	\.text
-0+05c <[^>]*> 0320f809 	jalr	t9
-0+060 <[^>]*> 00000000 	nop
-0+064 <[^>]*> 3c010001 	lui	at,0x1
-0+068 <[^>]*> 003d0821 	addu	at,at,sp
-0+06c <[^>]*> 8c3c8000 	lw	gp,-32768\(at\)
+0+014 <[^>]*> 273900cc 	addiu	t9,t9,204
+			14: R_MIPS_LO16	\.text
+0+018 <[^>]*> 0320f809 	jalr	t9
+0+01c <[^>]*> 00000000 	nop
+0+020 <[^>]*> 8fbc0008 	lw	gp,8\(sp\)
+0+024 <[^>]*> 00000000 	nop
+0+028 <[^>]*> 0320f809 	jalr	t9
+0+02c <[^>]*> 00000000 	nop
+0+030 <[^>]*> 8fbc0008 	lw	gp,8\(sp\)
+0+034 <[^>]*> 3c1c0000 	lui	gp,0x0
+			34: R_MIPS_HI16	_gp_disp
+0+038 <[^>]*> 279c0000 	addiu	gp,gp,0
+			38: R_MIPS_LO16	_gp_disp
+0+03c <[^>]*> 0399e021 	addu	gp,gp,t9
+0+040 <[^>]*> 3c010001 	lui	at,0x1
+0+044 <[^>]*> 003d0821 	addu	at,at,sp
+0+048 <[^>]*> ac3c8000 	sw	gp,-32768\(at\)
+0+04c <[^>]*> 8f990000 	lw	t9,0\(gp\)
+			4c: R_MIPS_GOT16	\.text
+0+050 <[^>]*> 273900cc 	addiu	t9,t9,204
+			50: R_MIPS_LO16	\.text
+0+054 <[^>]*> 0320f809 	jalr	t9
+0+058 <[^>]*> 00000000 	nop
+0+05c <[^>]*> 3c010001 	lui	at,0x1
+0+060 <[^>]*> 003d0821 	addu	at,at,sp
+0+064 <[^>]*> 8c3c8000 	lw	gp,-32768\(at\)
+0+068 <[^>]*> 00000000 	nop
+0+06c <[^>]*> 0320f809 	jalr	t9
 0+070 <[^>]*> 00000000 	nop
-0+074 <[^>]*> 0320f809 	jalr	t9
-0+078 <[^>]*> 00000000 	nop
-0+07c <[^>]*> 3c010001 	lui	at,0x1
-0+080 <[^>]*> 003d0821 	addu	at,at,sp
-0+084 <[^>]*> 8c3c8000 	lw	gp,-32768\(at\)
-0+088 <[^>]*> 3c1c0000 	lui	gp,0x0
-			88: R_MIPS_HI16	_gp_disp
-0+08c <[^>]*> 279c0000 	addiu	gp,gp,0
-			8c: R_MIPS_LO16	_gp_disp
-0+090 <[^>]*> 0399e021 	addu	gp,gp,t9
-0+094 <[^>]*> 3c010001 	lui	at,0x1
-0+098 <[^>]*> 003d0821 	addu	at,at,sp
-0+09c <[^>]*> ac3c0000 	sw	gp,0\(at\)
-0+0a0 <[^>]*> 8f990000 	lw	t9,0\(gp\)
-			a0: R_MIPS_GOT16	\.text
+0+074 <[^>]*> 3c010001 	lui	at,0x1
+0+078 <[^>]*> 003d0821 	addu	at,at,sp
+0+07c <[^>]*> 8c3c8000 	lw	gp,-32768\(at\)
+0+080 <[^>]*> 3c1c0000 	lui	gp,0x0
+			80: R_MIPS_HI16	_gp_disp
+0+084 <[^>]*> 279c0000 	addiu	gp,gp,0
+			84: R_MIPS_LO16	_gp_disp
+0+088 <[^>]*> 0399e021 	addu	gp,gp,t9
+0+08c <[^>]*> 3c010001 	lui	at,0x1
+0+090 <[^>]*> 003d0821 	addu	at,at,sp
+0+094 <[^>]*> ac3c0000 	sw	gp,0\(at\)
+0+098 <[^>]*> 8f990000 	lw	t9,0\(gp\)
+			98: R_MIPS_GOT16	\.text
+0+09c <[^>]*> 273900cc 	addiu	t9,t9,204
+			9c: R_MIPS_LO16	\.text
+0+0a0 <[^>]*> 0320f809 	jalr	t9
 0+0a4 <[^>]*> 00000000 	nop
-0+0a8 <[^>]*> 273900d8 	addiu	t9,t9,216
-			a8: R_MIPS_LO16	\.text
-0+0ac <[^>]*> 0320f809 	jalr	t9
-0+0b0 <[^>]*> 00000000 	nop
-0+0b4 <[^>]*> 3c010001 	lui	at,0x1
-0+0b8 <[^>]*> 003d0821 	addu	at,at,sp
-0+0bc <[^>]*> 8c3c0000 	lw	gp,0\(at\)
-0+0c0 <[^>]*> 00000000 	nop
-0+0c4 <[^>]*> 0320f809 	jalr	t9
-0+0c8 <[^>]*> 00000000 	nop
-0+0cc <[^>]*> 3c010001 	lui	at,0x1
-0+0d0 <[^>]*> 003d0821 	addu	at,at,sp
-0+0d4 <[^>]*> 8c3c0000 	lw	gp,0\(at\)
+0+0a8 <[^>]*> 3c010001 	lui	at,0x1
+0+0ac <[^>]*> 003d0821 	addu	at,at,sp
+0+0b0 <[^>]*> 8c3c0000 	lw	gp,0\(at\)
+0+0b4 <[^>]*> 00000000 	nop
+0+0b8 <[^>]*> 0320f809 	jalr	t9
+0+0bc <[^>]*> 00000000 	nop
+0+0c0 <[^>]*> 3c010001 	lui	at,0x1
+0+0c4 <[^>]*> 003d0821 	addu	at,at,sp
+0+0c8 <[^>]*> 8c3c0000 	lw	gp,0\(at\)
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
index 053024631615..3fb84e985870 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp32-pic.d
@@ -15,103 +15,85 @@ Disassembly of section .text:
   14:	3c041234 	lui	a0,0x1234
   18:	34845678 	ori	a0,a0,0x5678
   1c:	8f840000 	lw	a0,0\(gp\)
-  20:	00000000 	nop
-  24:	24840000 	addiu	a0,a0,0
-  28:	8f840000 	lw	a0,0\(gp\)
-  2c:	00000000 	nop
-  30:	24840000 	addiu	a0,a0,0
-  34:	8f840000 	lw	a0,0\(gp\)
+  20:	24840000 	addiu	a0,a0,0
+  24:	8f840000 	lw	a0,0\(gp\)
+  28:	24840000 	addiu	a0,a0,0
+  2c:	8f840000 	lw	a0,0\(gp\)
+  30:	2484015c 	addiu	a0,a0,348
+  34:	10000049 	b	15c <[^>]*>
   38:	00000000 	nop
-  3c:	248401a4 	addiu	a0,a0,420
-  40:	10000058 	b	1a4 <[^>]*>
-  44:	00000000 	nop
-  48:	8f990000 	lw	t9,0\(gp\)
-  4c:	00000000 	nop
-  50:	273901a4 	addiu	t9,t9,420
-  54:	0320f809 	jalr	t9
-  58:	00000000 	nop
-  5c:	8fbc0008 	lw	gp,8\(sp\)
-  60:	8f840000 	lw	a0,0\(gp\)
-  64:	00000000 	nop
-  68:	24840000 	addiu	a0,a0,0
-  6c:	8c840000 	lw	a0,0\(a0\)
-  70:	8f840000 	lw	a0,0\(gp\)
-  74:	00000000 	nop
-  78:	24840000 	addiu	a0,a0,0
-  7c:	8c840000 	lw	a0,0\(a0\)
-  80:	8f840000 	lw	a0,0\(gp\)
-  84:	00000000 	nop
-  88:	248401a4 	addiu	a0,a0,420
-  8c:	8c840000 	lw	a0,0\(a0\)
-  90:	8f810000 	lw	at,0\(gp\)
-  94:	00000000 	nop
-  98:	8c240000 	lw	a0,0\(at\)
-  9c:	8c250004 	lw	a1,4\(at\)
-  a0:	8f810000 	lw	at,0\(gp\)
-  a4:	00000000 	nop
-  a8:	8c240000 	lw	a0,0\(at\)
-  ac:	8c250004 	lw	a1,4\(at\)
+  3c:	8f990000 	lw	t9,0\(gp\)
+  40:	2739015c 	addiu	t9,t9,348
+  44:	0320f809 	jalr	t9
+  48:	00000000 	nop
+  4c:	8fbc0008 	lw	gp,8\(sp\)
+  50:	8f840000 	lw	a0,0\(gp\)
+  54:	24840000 	addiu	a0,a0,0
+  58:	8c840000 	lw	a0,0\(a0\)
+  5c:	8f840000 	lw	a0,0\(gp\)
+  60:	24840000 	addiu	a0,a0,0
+  64:	8c840000 	lw	a0,0\(a0\)
+  68:	8f840000 	lw	a0,0\(gp\)
+  6c:	2484015c 	addiu	a0,a0,348
+  70:	8c840000 	lw	a0,0\(a0\)
+  74:	8f810000 	lw	at,0\(gp\)
+  78:	8c240000 	lw	a0,0\(at\)
+  7c:	8c250004 	lw	a1,4\(at\)
+  80:	8f810000 	lw	at,0\(gp\)
+  84:	8c240000 	lw	a0,0\(at\)
+  88:	8c250004 	lw	a1,4\(at\)
+  8c:	8f810000 	lw	at,0\(gp\)
+  90:	8c24015c 	lw	a0,348\(at\)
+  94:	8c250160 	lw	a1,352\(at\)
+  98:	8f810000 	lw	at,0\(gp\)
+  9c:	24210000 	addiu	at,at,0
+  a0:	ac240000 	sw	a0,0\(at\)
+  a4:	8f810000 	lw	at,0\(gp\)
+  a8:	24210000 	addiu	at,at,0
+  ac:	ac240000 	sw	a0,0\(at\)
   b0:	8f810000 	lw	at,0\(gp\)
-  b4:	00000000 	nop
-  b8:	8c2401a4 	lw	a0,420\(at\)
-  bc:	8c2501a8 	lw	a1,424\(at\)
-  c0:	8f810000 	lw	at,0\(gp\)
-  c4:	00000000 	nop
-  c8:	24210000 	addiu	at,at,0
-  cc:	ac240000 	sw	a0,0\(at\)
-  d0:	8f810000 	lw	at,0\(gp\)
-  d4:	00000000 	nop
-  d8:	24210000 	addiu	at,at,0
-  dc:	ac240000 	sw	a0,0\(at\)
+  b4:	ac240000 	sw	a0,0\(at\)
+  b8:	ac250004 	sw	a1,4\(at\)
+  bc:	8f810000 	lw	at,0\(gp\)
+  c0:	ac240000 	sw	a0,0\(at\)
+  c4:	ac250004 	sw	a1,4\(at\)
+  c8:	8f810000 	lw	at,0\(gp\)
+  cc:	24210000 	addiu	at,at,0
+  d0:	80240000 	lb	a0,0\(at\)
+  d4:	90210001 	lbu	at,1\(at\)
+  d8:	00042200 	sll	a0,a0,0x8
+  dc:	00812025 	or	a0,a0,at
   e0:	8f810000 	lw	at,0\(gp\)
-  e4:	00000000 	nop
-  e8:	ac240000 	sw	a0,0\(at\)
-  ec:	ac250004 	sw	a1,4\(at\)
-  f0:	8f810000 	lw	at,0\(gp\)
-  f4:	00000000 	nop
-  f8:	ac240000 	sw	a0,0\(at\)
-  fc:	ac250004 	sw	a1,4\(at\)
+  e4:	24210000 	addiu	at,at,0
+  e8:	a0240001 	sb	a0,1\(at\)
+  ec:	00042202 	srl	a0,a0,0x8
+  f0:	a0240000 	sb	a0,0\(at\)
+  f4:	90210001 	lbu	at,1\(at\)
+  f8:	00042200 	sll	a0,a0,0x8
+  fc:	00812025 	or	a0,a0,at
  100:	8f810000 	lw	at,0\(gp\)
- 104:	00000000 	nop
- 108:	24210000 	addiu	at,at,0
- 10c:	80240000 	lb	a0,0\(at\)
- 110:	90210001 	lbu	at,1\(at\)
- 114:	00042200 	sll	a0,a0,0x8
- 118:	00812025 	or	a0,a0,at
- 11c:	8f810000 	lw	at,0\(gp\)
- 120:	00000000 	nop
- 124:	24210000 	addiu	at,at,0
- 128:	a0240001 	sb	a0,1\(at\)
- 12c:	00042202 	srl	a0,a0,0x8
- 130:	a0240000 	sb	a0,0\(at\)
- 134:	90210001 	lbu	at,1\(at\)
- 138:	00042200 	sll	a0,a0,0x8
- 13c:	00812025 	or	a0,a0,at
+ 104:	24210000 	addiu	at,at,0
+ 108:	88240000 	lwl	a0,0\(at\)
+ 10c:	98240003 	lwr	a0,3\(at\)
+ 110:	8f810000 	lw	at,0\(gp\)
+ 114:	24210000 	addiu	at,at,0
+ 118:	a8240000 	swl	a0,0\(at\)
+ 11c:	b8240003 	swr	a0,3\(at\)
+ 120:	3c043ff0 	lui	a0,0x3ff0
+ 124:	00002821 	move	a1,zero
+ 128:	8f810000 	lw	at,0\(gp\)
+ 12c:	8c240000 	lw	a0,0\(at\)
+ 130:	8c250004 	lw	a1,4\(at\)
+ 134:	3c013ff0 	lui	at,0x3ff0
+ 138:	44810800 	mtc1	at,\$f1
+ 13c:	44800000 	mtc1	zero,\$f0
  140:	8f810000 	lw	at,0\(gp\)
- 144:	00000000 	nop
- 148:	24210000 	addiu	at,at,0
- 14c:	88240000 	lwl	a0,0\(at\)
- 150:	98240003 	lwr	a0,3\(at\)
- 154:	8f810000 	lw	at,0\(gp\)
- 158:	00000000 	nop
- 15c:	24210000 	addiu	at,at,0
- 160:	a8240000 	swl	a0,0\(at\)
- 164:	b8240003 	swr	a0,3\(at\)
- 168:	3c043ff0 	lui	a0,0x3ff0
- 16c:	00002821 	move	a1,zero
- 170:	8f810000 	lw	at,0\(gp\)
- 174:	8c240000 	lw	a0,0\(at\)
- 178:	8c250004 	lw	a1,4\(at\)
- 17c:	3c013ff0 	lui	at,0x3ff0
- 180:	44810800 	mtc1	at,\$f1
- 184:	44800000 	mtc1	zero,\$f0
- 188:	8f810000 	lw	at,0\(gp\)
- 18c:	d4200008 	ldc1	\$f0,8\(at\)
- 190:	24a40064 	addiu	a0,a1,100
- 194:	2c840001 	sltiu	a0,a0,1
- 198:	24a40064 	addiu	a0,a1,100
- 19c:	0004202b 	sltu	a0,zero,a0
- 1a0:	00a02021 	move	a0,a1
+ 144:	d4200008 	ldc1	\$f0,8\(at\)
+ 148:	24a40064 	addiu	a0,a1,100
+ 14c:	2c840001 	sltiu	a0,a0,1
+ 150:	24a40064 	addiu	a0,a1,100
+ 154:	0004202b 	sltu	a0,zero,a0
+ 158:	00a02021 	move	a0,a1
 
-0+01a4 <[^>]*>:
+0+015c <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
index 5ed7df07e4a7..52c1701bd411 100644
--- a/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp32-fp64-pic.d
@@ -15,103 +15,85 @@ Disassembly of section .text:
   14:	3c041234 	lui	a0,0x1234
   18:	34845678 	ori	a0,a0,0x5678
   1c:	8f840000 	lw	a0,0\(gp\)
-  20:	00000000 	nop
-  24:	24840000 	addiu	a0,a0,0
-  28:	8f840000 	lw	a0,0\(gp\)
-  2c:	00000000 	nop
-  30:	24840000 	addiu	a0,a0,0
-  34:	8f840000 	lw	a0,0\(gp\)
+  20:	24840000 	addiu	a0,a0,0
+  24:	8f840000 	lw	a0,0\(gp\)
+  28:	24840000 	addiu	a0,a0,0
+  2c:	8f840000 	lw	a0,0\(gp\)
+  30:	2484015c 	addiu	a0,a0,348
+  34:	10000049 	b	15c <[^>]*>
   38:	00000000 	nop
-  3c:	248401a4 	addiu	a0,a0,420
-  40:	10000058 	b	1a4 <[^>]*>
-  44:	00000000 	nop
-  48:	8f990000 	lw	t9,0\(gp\)
-  4c:	00000000 	nop
-  50:	273901a4 	addiu	t9,t9,420
-  54:	0320f809 	jalr	t9
-  58:	00000000 	nop
-  5c:	8fbc0008 	lw	gp,8\(sp\)
-  60:	8f840000 	lw	a0,0\(gp\)
-  64:	00000000 	nop
-  68:	24840000 	addiu	a0,a0,0
-  6c:	8c840000 	lw	a0,0\(a0\)
-  70:	8f840000 	lw	a0,0\(gp\)
-  74:	00000000 	nop
-  78:	24840000 	addiu	a0,a0,0
-  7c:	8c840000 	lw	a0,0\(a0\)
-  80:	8f840000 	lw	a0,0\(gp\)
-  84:	00000000 	nop
-  88:	248401a4 	addiu	a0,a0,420
-  8c:	8c840000 	lw	a0,0\(a0\)
-  90:	8f810000 	lw	at,0\(gp\)
-  94:	00000000 	nop
-  98:	8c240000 	lw	a0,0\(at\)
-  9c:	8c250004 	lw	a1,4\(at\)
-  a0:	8f810000 	lw	at,0\(gp\)
-  a4:	00000000 	nop
-  a8:	8c240000 	lw	a0,0\(at\)
-  ac:	8c250004 	lw	a1,4\(at\)
+  3c:	8f990000 	lw	t9,0\(gp\)
+  40:	2739015c 	addiu	t9,t9,348
+  44:	0320f809 	jalr	t9
+  48:	00000000 	nop
+  4c:	8fbc0008 	lw	gp,8\(sp\)
+  50:	8f840000 	lw	a0,0\(gp\)
+  54:	24840000 	addiu	a0,a0,0
+  58:	8c840000 	lw	a0,0\(a0\)
+  5c:	8f840000 	lw	a0,0\(gp\)
+  60:	24840000 	addiu	a0,a0,0
+  64:	8c840000 	lw	a0,0\(a0\)
+  68:	8f840000 	lw	a0,0\(gp\)
+  6c:	2484015c 	addiu	a0,a0,348
+  70:	8c840000 	lw	a0,0\(a0\)
+  74:	8f810000 	lw	at,0\(gp\)
+  78:	8c240000 	lw	a0,0\(at\)
+  7c:	8c250004 	lw	a1,4\(at\)
+  80:	8f810000 	lw	at,0\(gp\)
+  84:	8c240000 	lw	a0,0\(at\)
+  88:	8c250004 	lw	a1,4\(at\)
+  8c:	8f810000 	lw	at,0\(gp\)
+  90:	8c24015c 	lw	a0,348\(at\)
+  94:	8c250160 	lw	a1,352\(at\)
+  98:	8f810000 	lw	at,0\(gp\)
+  9c:	24210000 	addiu	at,at,0
+  a0:	ac240000 	sw	a0,0\(at\)
+  a4:	8f810000 	lw	at,0\(gp\)
+  a8:	24210000 	addiu	at,at,0
+  ac:	ac240000 	sw	a0,0\(at\)
   b0:	8f810000 	lw	at,0\(gp\)
-  b4:	00000000 	nop
-  b8:	8c2401a4 	lw	a0,420\(at\)
-  bc:	8c2501a8 	lw	a1,424\(at\)
-  c0:	8f810000 	lw	at,0\(gp\)
-  c4:	00000000 	nop
-  c8:	24210000 	addiu	at,at,0
-  cc:	ac240000 	sw	a0,0\(at\)
-  d0:	8f810000 	lw	at,0\(gp\)
-  d4:	00000000 	nop
-  d8:	24210000 	addiu	at,at,0
-  dc:	ac240000 	sw	a0,0\(at\)
+  b4:	ac240000 	sw	a0,0\(at\)
+  b8:	ac250004 	sw	a1,4\(at\)
+  bc:	8f810000 	lw	at,0\(gp\)
+  c0:	ac240000 	sw	a0,0\(at\)
+  c4:	ac250004 	sw	a1,4\(at\)
+  c8:	8f810000 	lw	at,0\(gp\)
+  cc:	24210000 	addiu	at,at,0
+  d0:	80240000 	lb	a0,0\(at\)
+  d4:	90210001 	lbu	at,1\(at\)
+  d8:	00042200 	sll	a0,a0,0x8
+  dc:	00812025 	or	a0,a0,at
   e0:	8f810000 	lw	at,0\(gp\)
-  e4:	00000000 	nop
-  e8:	ac240000 	sw	a0,0\(at\)
-  ec:	ac250004 	sw	a1,4\(at\)
-  f0:	8f810000 	lw	at,0\(gp\)
-  f4:	00000000 	nop
-  f8:	ac240000 	sw	a0,0\(at\)
-  fc:	ac250004 	sw	a1,4\(at\)
+  e4:	24210000 	addiu	at,at,0
+  e8:	a0240001 	sb	a0,1\(at\)
+  ec:	00042202 	srl	a0,a0,0x8
+  f0:	a0240000 	sb	a0,0\(at\)
+  f4:	90210001 	lbu	at,1\(at\)
+  f8:	00042200 	sll	a0,a0,0x8
+  fc:	00812025 	or	a0,a0,at
  100:	8f810000 	lw	at,0\(gp\)
- 104:	00000000 	nop
- 108:	24210000 	addiu	at,at,0
- 10c:	80240000 	lb	a0,0\(at\)
- 110:	90210001 	lbu	at,1\(at\)
- 114:	00042200 	sll	a0,a0,0x8
- 118:	00812025 	or	a0,a0,at
- 11c:	8f810000 	lw	at,0\(gp\)
- 120:	00000000 	nop
- 124:	24210000 	addiu	at,at,0
- 128:	a0240001 	sb	a0,1\(at\)
- 12c:	00042202 	srl	a0,a0,0x8
- 130:	a0240000 	sb	a0,0\(at\)
- 134:	90210001 	lbu	at,1\(at\)
- 138:	00042200 	sll	a0,a0,0x8
- 13c:	00812025 	or	a0,a0,at
- 140:	8f810000 	lw	at,0\(gp\)
- 144:	00000000 	nop
- 148:	24210000 	addiu	at,at,0
- 14c:	88240000 	lwl	a0,0\(at\)
- 150:	98240003 	lwr	a0,3\(at\)
- 154:	8f810000 	lw	at,0\(gp\)
- 158:	00000000 	nop
- 15c:	24210000 	addiu	at,at,0
- 160:	a8240000 	swl	a0,0\(at\)
- 164:	b8240003 	swr	a0,3\(at\)
- 168:	3c043ff0 	lui	a0,0x3ff0
- 16c:	00002821 	move	a1,zero
- 170:	8f810000 	lw	at,0\(gp\)
- 174:	8c240000 	lw	a0,0\(at\)
- 178:	8c250004 	lw	a1,4\(at\)
- 17c:	8f810000 	lw	at,0\(gp\)
- 180:	d4200008 	ldc1	\$f0,8\(at\)
- 184:	8f810000 	lw	at,0\(gp\)
- 188:	d4200010 	ldc1	\$f0,16\(at\)
- 18c:	24a40064 	addiu	a0,a1,100
- 190:	2c840001 	sltiu	a0,a0,1
- 194:	24a40064 	addiu	a0,a1,100
- 198:	0004202b 	sltu	a0,zero,a0
- 19c:	00a02021 	move	a0,a1
- 1a0:	46231040 	add.d	\$f1,\$f2,\$f3
+ 104:	24210000 	addiu	at,at,0
+ 108:	88240000 	lwl	a0,0\(at\)
+ 10c:	98240003 	lwr	a0,3\(at\)
+ 110:	8f810000 	lw	at,0\(gp\)
+ 114:	24210000 	addiu	at,at,0
+ 118:	a8240000 	swl	a0,0\(at\)
+ 11c:	b8240003 	swr	a0,3\(at\)
+ 120:	3c043ff0 	lui	a0,0x3ff0
+ 124:	00002821 	move	a1,zero
+ 128:	8f810000 	lw	at,0\(gp\)
+ 12c:	8c240000 	lw	a0,0\(at\)
+ 130:	8c250004 	lw	a1,4\(at\)
+ 134:	8f810000 	lw	at,0\(gp\)
+ 138:	d4200008 	ldc1	\$f0,8\(at\)
+ 13c:	8f810000 	lw	at,0\(gp\)
+ 140:	d4200010 	ldc1	\$f0,16\(at\)
+ 144:	24a40064 	addiu	a0,a1,100
+ 148:	2c840001 	sltiu	a0,a0,1
+ 14c:	24a40064 	addiu	a0,a1,100
+ 150:	0004202b 	sltu	a0,zero,a0
+ 154:	00a02021 	move	a0,a1
+ 158:	46231040 	add.d	\$f1,\$f2,\$f3
 
-0+01a4 <[^>]*>:
+0+015c <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
index db6c76b1e46e..f5a8e8963942 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.d
@@ -15,138 +15,116 @@ Disassembly of section .text:
   14:	3c041234 	lui	a0,0x1234
   18:	34845678 	ori	a0,a0,0x5678
   1c:	8f840000 	lw	a0,0\(gp\)
-  20:	00000000 	nop
-  24:	24840000 	addiu	a0,a0,0
-  28:	8f840000 	lw	a0,0\(gp\)
-  2c:	00000000 	nop
-  30:	24840000 	addiu	a0,a0,0
-  34:	8f840000 	lw	a0,0\(gp\)
+  20:	24840000 	addiu	a0,a0,0
+  24:	8f840000 	lw	a0,0\(gp\)
+  28:	24840000 	addiu	a0,a0,0
+  2c:	8f840000 	lw	a0,0\(gp\)
+  30:	248401d8 	addiu	a0,a0,472
+  34:	10000068 	b	1d8 <[^>]*>
   38:	00000000 	nop
-  3c:	24840230 	addiu	a0,a0,560
-  40:	1000007b 	b	230 <[^>]*>
-  44:	00000000 	nop
-  48:	8f990000 	lw	t9,0\(gp\)
-  4c:	00000000 	nop
-  50:	27390230 	addiu	t9,t9,560
-  54:	0320f809 	jalr	t9
-  58:	00000000 	nop
-  5c:	8fbc0008 	lw	gp,8\(sp\)
-  60:	8f840000 	lw	a0,0\(gp\)
-  64:	00000000 	nop
-  68:	24840000 	addiu	a0,a0,0
-  6c:	8c840000 	lw	a0,0\(a0\)
-  70:	8f840000 	lw	a0,0\(gp\)
-  74:	00000000 	nop
+  3c:	8f990000 	lw	t9,0\(gp\)
+  40:	273901d8 	addiu	t9,t9,472
+  44:	0320f809 	jalr	t9
+  48:	00000000 	nop
+  4c:	8fbc0008 	lw	gp,8\(sp\)
+  50:	8f840000 	lw	a0,0\(gp\)
+  54:	24840000 	addiu	a0,a0,0
+  58:	8c840000 	lw	a0,0\(a0\)
+  5c:	8f840000 	lw	a0,0\(gp\)
+  60:	24840000 	addiu	a0,a0,0
+  64:	8c840000 	lw	a0,0\(a0\)
+  68:	8f840000 	lw	a0,0\(gp\)
+  6c:	248401d8 	addiu	a0,a0,472
+  70:	8c840000 	lw	a0,0\(a0\)
+  74:	8f840000 	lw	a0,0\(gp\)
   78:	24840000 	addiu	a0,a0,0
-  7c:	8c840000 	lw	a0,0\(a0\)
+  7c:	dc840000 	ld	a0,0\(a0\)
   80:	8f840000 	lw	a0,0\(gp\)
-  84:	00000000 	nop
-  88:	24840230 	addiu	a0,a0,560
-  8c:	8c840000 	lw	a0,0\(a0\)
-  90:	8f840000 	lw	a0,0\(gp\)
-  94:	00000000 	nop
-  98:	24840000 	addiu	a0,a0,0
-  9c:	dc840000 	ld	a0,0\(a0\)
-  a0:	8f840000 	lw	a0,0\(gp\)
-  a4:	00000000 	nop
-  a8:	24840000 	addiu	a0,a0,0
-  ac:	dc840000 	ld	a0,0\(a0\)
-  b0:	8f840000 	lw	a0,0\(gp\)
-  b4:	00000000 	nop
-  b8:	24840230 	addiu	a0,a0,560
-  bc:	dc840000 	ld	a0,0\(a0\)
-  c0:	8f810000 	lw	at,0\(gp\)
-  c4:	00000000 	nop
-  c8:	24210000 	addiu	at,at,0
-  cc:	ac240000 	sw	a0,0\(at\)
-  d0:	8f810000 	lw	at,0\(gp\)
-  d4:	00000000 	nop
-  d8:	24210000 	addiu	at,at,0
-  dc:	ac240000 	sw	a0,0\(at\)
+  84:	24840000 	addiu	a0,a0,0
+  88:	dc840000 	ld	a0,0\(a0\)
+  8c:	8f840000 	lw	a0,0\(gp\)
+  90:	248401d8 	addiu	a0,a0,472
+  94:	dc840000 	ld	a0,0\(a0\)
+  98:	8f810000 	lw	at,0\(gp\)
+  9c:	24210000 	addiu	at,at,0
+  a0:	ac240000 	sw	a0,0\(at\)
+  a4:	8f810000 	lw	at,0\(gp\)
+  a8:	24210000 	addiu	at,at,0
+  ac:	ac240000 	sw	a0,0\(at\)
+  b0:	8f810000 	lw	at,0\(gp\)
+  b4:	24210000 	addiu	at,at,0
+  b8:	fc240000 	sd	a0,0\(at\)
+  bc:	8f810000 	lw	at,0\(gp\)
+  c0:	24210000 	addiu	at,at,0
+  c4:	fc240000 	sd	a0,0\(at\)
+  c8:	8f810000 	lw	at,0\(gp\)
+  cc:	24210000 	addiu	at,at,0
+  d0:	80240000 	lb	a0,0\(at\)
+  d4:	90210001 	lbu	at,1\(at\)
+  d8:	00042200 	sll	a0,a0,0x8
+  dc:	00812025 	or	a0,a0,at
   e0:	8f810000 	lw	at,0\(gp\)
-  e4:	00000000 	nop
-  e8:	24210000 	addiu	at,at,0
-  ec:	fc240000 	sd	a0,0\(at\)
-  f0:	8f810000 	lw	at,0\(gp\)
-  f4:	00000000 	nop
-  f8:	24210000 	addiu	at,at,0
-  fc:	fc240000 	sd	a0,0\(at\)
+  e4:	24210000 	addiu	at,at,0
+  e8:	a0240001 	sb	a0,1\(at\)
+  ec:	00042202 	srl	a0,a0,0x8
+  f0:	a0240000 	sb	a0,0\(at\)
+  f4:	90210001 	lbu	at,1\(at\)
+  f8:	00042200 	sll	a0,a0,0x8
+  fc:	00812025 	or	a0,a0,at
  100:	8f810000 	lw	at,0\(gp\)
- 104:	00000000 	nop
- 108:	24210000 	addiu	at,at,0
- 10c:	80240000 	lb	a0,0\(at\)
- 110:	90210001 	lbu	at,1\(at\)
- 114:	00042200 	sll	a0,a0,0x8
- 118:	00812025 	or	a0,a0,at
- 11c:	8f810000 	lw	at,0\(gp\)
- 120:	00000000 	nop
- 124:	24210000 	addiu	at,at,0
- 128:	a0240001 	sb	a0,1\(at\)
- 12c:	00042202 	srl	a0,a0,0x8
- 130:	a0240000 	sb	a0,0\(at\)
- 134:	90210001 	lbu	at,1\(at\)
- 138:	00042200 	sll	a0,a0,0x8
- 13c:	00812025 	or	a0,a0,at
- 140:	8f810000 	lw	at,0\(gp\)
- 144:	00000000 	nop
- 148:	24210000 	addiu	at,at,0
- 14c:	88240000 	lwl	a0,0\(at\)
- 150:	98240003 	lwr	a0,3\(at\)
- 154:	8f810000 	lw	at,0\(gp\)
- 158:	00000000 	nop
- 15c:	24210000 	addiu	at,at,0
- 160:	a8240000 	swl	a0,0\(at\)
- 164:	b8240003 	swr	a0,3\(at\)
- 168:	3404ffc0 	li	a0,0xffc0
- 16c:	000423bc 	dsll32	a0,a0,0xe
- 170:	8f810000 	lw	at,0\(gp\)
- 174:	dc240000 	ld	a0,0\(at\)
- 178:	3c013ff0 	lui	at,0x3ff0
- 17c:	44810800 	mtc1	at,\$f1
- 180:	44800000 	mtc1	zero,\$f0
- 184:	8f810000 	lw	at,0\(gp\)
- 188:	d4200008 	ldc1	\$f0,8\(at\)
- 18c:	64a40064 	daddiu	a0,a1,100
- 190:	2c840001 	sltiu	a0,a0,1
- 194:	64a40064 	daddiu	a0,a1,100
- 198:	0004202b 	sltu	a0,zero,a0
- 19c:	00a0202d 	move	a0,a1
- 1a0:	8f840000 	lw	a0,0\(gp\)
- 1a4:	00000000 	nop
- 1a8:	24840000 	addiu	a0,a0,0
- 1ac:	8f840000 	lw	a0,0\(gp\)
- 1b0:	00000000 	nop
- 1b4:	24840000 	addiu	a0,a0,0
- 1b8:	8f810000 	lw	at,0\(gp\)
- 1bc:	00000000 	nop
- 1c0:	24210000 	addiu	at,at,0
- 1c4:	68240000 	ldl	a0,0\(at\)
- 1c8:	6c240007 	ldr	a0,7\(at\)
- 1cc:	8f810000 	lw	at,0\(gp\)
- 1d0:	00000000 	nop
- 1d4:	24210000 	addiu	at,at,0
- 1d8:	b0240000 	sdl	a0,0\(at\)
- 1dc:	b4240007 	sdr	a0,7\(at\)
- 1e0:	34018000 	li	at,0x8000
- 1e4:	00010c38 	dsll	at,at,0x10
- 1e8:	0081082a 	slt	at,a0,at
- 1ec:	10200010 	beqz	at,230 <[^>]*>
- 1f0:	00000000 	nop
- 1f4:	34018000 	li	at,0x8000
- 1f8:	00010c78 	dsll	at,at,0x11
- 1fc:	0081082b 	sltu	at,a0,at
- 200:	1020000b 	beqz	at,230 <[^>]*>
- 204:	00000000 	nop
- 208:	34018000 	li	at,0x8000
- 20c:	00010c38 	dsll	at,at,0x10
- 210:	0081082a 	slt	at,a0,at
- 214:	14200006 	bnez	at,230 <[^>]*>
- 218:	00000000 	nop
- 21c:	34018000 	li	at,0x8000
- 220:	00010c78 	dsll	at,at,0x11
- 224:	0081082b 	sltu	at,a0,at
- 228:	14200001 	bnez	at,230 <[^>]*>
- 22c:	00000000 	nop
+ 104:	24210000 	addiu	at,at,0
+ 108:	88240000 	lwl	a0,0\(at\)
+ 10c:	98240003 	lwr	a0,3\(at\)
+ 110:	8f810000 	lw	at,0\(gp\)
+ 114:	24210000 	addiu	at,at,0
+ 118:	a8240000 	swl	a0,0\(at\)
+ 11c:	b8240003 	swr	a0,3\(at\)
+ 120:	3404ffc0 	li	a0,0xffc0
+ 124:	000423bc 	dsll32	a0,a0,0xe
+ 128:	8f810000 	lw	at,0\(gp\)
+ 12c:	dc240000 	ld	a0,0\(at\)
+ 130:	3c013ff0 	lui	at,0x3ff0
+ 134:	44810800 	mtc1	at,\$f1
+ 138:	44800000 	mtc1	zero,\$f0
+ 13c:	8f810000 	lw	at,0\(gp\)
+ 140:	d4200008 	ldc1	\$f0,8\(at\)
+ 144:	64a40064 	daddiu	a0,a1,100
+ 148:	2c840001 	sltiu	a0,a0,1
+ 14c:	64a40064 	daddiu	a0,a1,100
+ 150:	0004202b 	sltu	a0,zero,a0
+ 154:	00a0202d 	move	a0,a1
+ 158:	8f840000 	lw	a0,0\(gp\)
+ 15c:	24840000 	addiu	a0,a0,0
+ 160:	8f840000 	lw	a0,0\(gp\)
+ 164:	24840000 	addiu	a0,a0,0
+ 168:	8f810000 	lw	at,0\(gp\)
+ 16c:	24210000 	addiu	at,at,0
+ 170:	68240000 	ldl	a0,0\(at\)
+ 174:	6c240007 	ldr	a0,7\(at\)
+ 178:	8f810000 	lw	at,0\(gp\)
+ 17c:	24210000 	addiu	at,at,0
+ 180:	b0240000 	sdl	a0,0\(at\)
+ 184:	b4240007 	sdr	a0,7\(at\)
+ 188:	34018000 	li	at,0x8000
+ 18c:	00010c38 	dsll	at,at,0x10
+ 190:	0081082a 	slt	at,a0,at
+ 194:	10200010 	beqz	at,1d8 <[^>]*>
+ 198:	00000000 	nop
+ 19c:	34018000 	li	at,0x8000
+ 1a0:	00010c78 	dsll	at,at,0x11
+ 1a4:	0081082b 	sltu	at,a0,at
+ 1a8:	1020000b 	beqz	at,1d8 <[^>]*>
+ 1ac:	00000000 	nop
+ 1b0:	34018000 	li	at,0x8000
+ 1b4:	00010c38 	dsll	at,at,0x10
+ 1b8:	0081082a 	slt	at,a0,at
+ 1bc:	14200006 	bnez	at,1d8 <[^>]*>
+ 1c0:	00000000 	nop
+ 1c4:	34018000 	li	at,0x8000
+ 1c8:	00010c78 	dsll	at,at,0x11
+ 1cc:	0081082b 	sltu	at,a0,at
+ 1d0:	14200001 	bnez	at,1d8 <[^>]*>
+ 1d4:	00000000 	nop
 
-0+0230 <[^>]*>:
+0+01d8 <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d b/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
index f66ea4e0fac1..2e37f6850bde 100644
--- a/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
+++ b/gas/testsuite/gas/mips/mips-gp64-fp64-pic.d
@@ -15,139 +15,117 @@ Disassembly of section .text:
   14:	3c041234 	lui	a0,0x1234
   18:	34845678 	ori	a0,a0,0x5678
   1c:	8f840000 	lw	a0,0\(gp\)
-  20:	00000000 	nop
-  24:	24840000 	addiu	a0,a0,0
-  28:	8f840000 	lw	a0,0\(gp\)
-  2c:	00000000 	nop
-  30:	24840000 	addiu	a0,a0,0
-  34:	8f840000 	lw	a0,0\(gp\)
+  20:	24840000 	addiu	a0,a0,0
+  24:	8f840000 	lw	a0,0\(gp\)
+  28:	24840000 	addiu	a0,a0,0
+  2c:	8f840000 	lw	a0,0\(gp\)
+  30:	248401dc 	addiu	a0,a0,476
+  34:	10000069 	b	1dc <[^>]*>
   38:	00000000 	nop
-  3c:	24840234 	addiu	a0,a0,564
-  40:	1000007c 	b	234 <[^>]*>
-  44:	00000000 	nop
-  48:	8f990000 	lw	t9,0\(gp\)
-  4c:	00000000 	nop
-  50:	27390234 	addiu	t9,t9,564
-  54:	0320f809 	jalr	t9
-  58:	00000000 	nop
-  5c:	8fbc0008 	lw	gp,8\(sp\)
-  60:	8f840000 	lw	a0,0\(gp\)
-  64:	00000000 	nop
-  68:	24840000 	addiu	a0,a0,0
-  6c:	8c840000 	lw	a0,0\(a0\)
-  70:	8f840000 	lw	a0,0\(gp\)
-  74:	00000000 	nop
+  3c:	8f990000 	lw	t9,0\(gp\)
+  40:	273901dc 	addiu	t9,t9,476
+  44:	0320f809 	jalr	t9
+  48:	00000000 	nop
+  4c:	8fbc0008 	lw	gp,8\(sp\)
+  50:	8f840000 	lw	a0,0\(gp\)
+  54:	24840000 	addiu	a0,a0,0
+  58:	8c840000 	lw	a0,0\(a0\)
+  5c:	8f840000 	lw	a0,0\(gp\)
+  60:	24840000 	addiu	a0,a0,0
+  64:	8c840000 	lw	a0,0\(a0\)
+  68:	8f840000 	lw	a0,0\(gp\)
+  6c:	248401dc 	addiu	a0,a0,476
+  70:	8c840000 	lw	a0,0\(a0\)
+  74:	8f840000 	lw	a0,0\(gp\)
   78:	24840000 	addiu	a0,a0,0
-  7c:	8c840000 	lw	a0,0\(a0\)
+  7c:	dc840000 	ld	a0,0\(a0\)
   80:	8f840000 	lw	a0,0\(gp\)
-  84:	00000000 	nop
-  88:	24840234 	addiu	a0,a0,564
-  8c:	8c840000 	lw	a0,0\(a0\)
-  90:	8f840000 	lw	a0,0\(gp\)
-  94:	00000000 	nop
-  98:	24840000 	addiu	a0,a0,0
-  9c:	dc840000 	ld	a0,0\(a0\)
-  a0:	8f840000 	lw	a0,0\(gp\)
-  a4:	00000000 	nop
-  a8:	24840000 	addiu	a0,a0,0
-  ac:	dc840000 	ld	a0,0\(a0\)
-  b0:	8f840000 	lw	a0,0\(gp\)
-  b4:	00000000 	nop
-  b8:	24840234 	addiu	a0,a0,564
-  bc:	dc840000 	ld	a0,0\(a0\)
-  c0:	8f810000 	lw	at,0\(gp\)
-  c4:	00000000 	nop
-  c8:	24210000 	addiu	at,at,0
-  cc:	ac240000 	sw	a0,0\(at\)
-  d0:	8f810000 	lw	at,0\(gp\)
-  d4:	00000000 	nop
-  d8:	24210000 	addiu	at,at,0
-  dc:	ac240000 	sw	a0,0\(at\)
+  84:	24840000 	addiu	a0,a0,0
+  88:	dc840000 	ld	a0,0\(a0\)
+  8c:	8f840000 	lw	a0,0\(gp\)
+  90:	248401dc 	addiu	a0,a0,476
+  94:	dc840000 	ld	a0,0\(a0\)
+  98:	8f810000 	lw	at,0\(gp\)
+  9c:	24210000 	addiu	at,at,0
+  a0:	ac240000 	sw	a0,0\(at\)
+  a4:	8f810000 	lw	at,0\(gp\)
+  a8:	24210000 	addiu	at,at,0
+  ac:	ac240000 	sw	a0,0\(at\)
+  b0:	8f810000 	lw	at,0\(gp\)
+  b4:	24210000 	addiu	at,at,0
+  b8:	fc240000 	sd	a0,0\(at\)
+  bc:	8f810000 	lw	at,0\(gp\)
+  c0:	24210000 	addiu	at,at,0
+  c4:	fc240000 	sd	a0,0\(at\)
+  c8:	8f810000 	lw	at,0\(gp\)
+  cc:	24210000 	addiu	at,at,0
+  d0:	80240000 	lb	a0,0\(at\)
+  d4:	90210001 	lbu	at,1\(at\)
+  d8:	00042200 	sll	a0,a0,0x8
+  dc:	00812025 	or	a0,a0,at
   e0:	8f810000 	lw	at,0\(gp\)
-  e4:	00000000 	nop
-  e8:	24210000 	addiu	at,at,0
-  ec:	fc240000 	sd	a0,0\(at\)
-  f0:	8f810000 	lw	at,0\(gp\)
-  f4:	00000000 	nop
-  f8:	24210000 	addiu	at,at,0
-  fc:	fc240000 	sd	a0,0\(at\)
+  e4:	24210000 	addiu	at,at,0
+  e8:	a0240001 	sb	a0,1\(at\)
+  ec:	00042202 	srl	a0,a0,0x8
+  f0:	a0240000 	sb	a0,0\(at\)
+  f4:	90210001 	lbu	at,1\(at\)
+  f8:	00042200 	sll	a0,a0,0x8
+  fc:	00812025 	or	a0,a0,at
  100:	8f810000 	lw	at,0\(gp\)
- 104:	00000000 	nop
- 108:	24210000 	addiu	at,at,0
- 10c:	80240000 	lb	a0,0\(at\)
- 110:	90210001 	lbu	at,1\(at\)
- 114:	00042200 	sll	a0,a0,0x8
- 118:	00812025 	or	a0,a0,at
- 11c:	8f810000 	lw	at,0\(gp\)
- 120:	00000000 	nop
- 124:	24210000 	addiu	at,at,0
- 128:	a0240001 	sb	a0,1\(at\)
- 12c:	00042202 	srl	a0,a0,0x8
- 130:	a0240000 	sb	a0,0\(at\)
- 134:	90210001 	lbu	at,1\(at\)
- 138:	00042200 	sll	a0,a0,0x8
- 13c:	00812025 	or	a0,a0,at
- 140:	8f810000 	lw	at,0\(gp\)
- 144:	00000000 	nop
- 148:	24210000 	addiu	at,at,0
- 14c:	88240000 	lwl	a0,0\(at\)
- 150:	98240003 	lwr	a0,3\(at\)
- 154:	8f810000 	lw	at,0\(gp\)
- 158:	00000000 	nop
- 15c:	24210000 	addiu	at,at,0
- 160:	a8240000 	swl	a0,0\(at\)
- 164:	b8240003 	swr	a0,3\(at\)
- 168:	3404ffc0 	li	a0,0xffc0
- 16c:	000423bc 	dsll32	a0,a0,0xe
- 170:	8f810000 	lw	at,0\(gp\)
- 174:	dc240000 	ld	a0,0\(at\)
- 178:	3401ffc0 	li	at,0xffc0
- 17c:	00010bbc 	dsll32	at,at,0xe
- 180:	44a10000 	dmtc1	at,\$f0
- 184:	8f810000 	lw	at,0\(gp\)
- 188:	d4200008 	ldc1	\$f0,8\(at\)
- 18c:	64a40064 	daddiu	a0,a1,100
- 190:	2c840001 	sltiu	a0,a0,1
- 194:	64a40064 	daddiu	a0,a1,100
- 198:	0004202b 	sltu	a0,zero,a0
- 19c:	00a0202d 	move	a0,a1
- 1a0:	8f840000 	lw	a0,0\(gp\)
- 1a4:	00000000 	nop
- 1a8:	24840000 	addiu	a0,a0,0
- 1ac:	8f840000 	lw	a0,0\(gp\)
- 1b0:	00000000 	nop
- 1b4:	24840000 	addiu	a0,a0,0
- 1b8:	8f810000 	lw	at,0\(gp\)
- 1bc:	00000000 	nop
- 1c0:	24210000 	addiu	at,at,0
- 1c4:	68240000 	ldl	a0,0\(at\)
- 1c8:	6c240007 	ldr	a0,7\(at\)
- 1cc:	8f810000 	lw	at,0\(gp\)
- 1d0:	00000000 	nop
- 1d4:	24210000 	addiu	at,at,0
- 1d8:	b0240000 	sdl	a0,0\(at\)
- 1dc:	b4240007 	sdr	a0,7\(at\)
- 1e0:	34018000 	li	at,0x8000
- 1e4:	00010c38 	dsll	at,at,0x10
- 1e8:	0081082a 	slt	at,a0,at
- 1ec:	10200011 	beqz	at,234 <[^>]*>
- 1f0:	00000000 	nop
- 1f4:	34018000 	li	at,0x8000
- 1f8:	00010c78 	dsll	at,at,0x11
- 1fc:	0081082b 	sltu	at,a0,at
- 200:	1020000c 	beqz	at,234 <[^>]*>
- 204:	00000000 	nop
- 208:	34018000 	li	at,0x8000
- 20c:	00010c38 	dsll	at,at,0x10
- 210:	0081082a 	slt	at,a0,at
- 214:	14200007 	bnez	at,234 <[^>]*>
- 218:	00000000 	nop
- 21c:	34018000 	li	at,0x8000
- 220:	00010c78 	dsll	at,at,0x11
- 224:	0081082b 	sltu	at,a0,at
- 228:	14200002 	bnez	at,234 <[^>]*>
- 22c:	00000000 	nop
- 230:	46231040 	add.d	\$f1,\$f2,\$f3
+ 104:	24210000 	addiu	at,at,0
+ 108:	88240000 	lwl	a0,0\(at\)
+ 10c:	98240003 	lwr	a0,3\(at\)
+ 110:	8f810000 	lw	at,0\(gp\)
+ 114:	24210000 	addiu	at,at,0
+ 118:	a8240000 	swl	a0,0\(at\)
+ 11c:	b8240003 	swr	a0,3\(at\)
+ 120:	3404ffc0 	li	a0,0xffc0
+ 124:	000423bc 	dsll32	a0,a0,0xe
+ 128:	8f810000 	lw	at,0\(gp\)
+ 12c:	dc240000 	ld	a0,0\(at\)
+ 130:	3401ffc0 	li	at,0xffc0
+ 134:	00010bbc 	dsll32	at,at,0xe
+ 138:	44a10000 	dmtc1	at,\$f0
+ 13c:	8f810000 	lw	at,0\(gp\)
+ 140:	d4200008 	ldc1	\$f0,8\(at\)
+ 144:	64a40064 	daddiu	a0,a1,100
+ 148:	2c840001 	sltiu	a0,a0,1
+ 14c:	64a40064 	daddiu	a0,a1,100
+ 150:	0004202b 	sltu	a0,zero,a0
+ 154:	00a0202d 	move	a0,a1
+ 158:	8f840000 	lw	a0,0\(gp\)
+ 15c:	24840000 	addiu	a0,a0,0
+ 160:	8f840000 	lw	a0,0\(gp\)
+ 164:	24840000 	addiu	a0,a0,0
+ 168:	8f810000 	lw	at,0\(gp\)
+ 16c:	24210000 	addiu	at,at,0
+ 170:	68240000 	ldl	a0,0\(at\)
+ 174:	6c240007 	ldr	a0,7\(at\)
+ 178:	8f810000 	lw	at,0\(gp\)
+ 17c:	24210000 	addiu	at,at,0
+ 180:	b0240000 	sdl	a0,0\(at\)
+ 184:	b4240007 	sdr	a0,7\(at\)
+ 188:	34018000 	li	at,0x8000
+ 18c:	00010c38 	dsll	at,at,0x10
+ 190:	0081082a 	slt	at,a0,at
+ 194:	10200011 	beqz	at,1dc <[^>]*>
+ 198:	00000000 	nop
+ 19c:	34018000 	li	at,0x8000
+ 1a0:	00010c78 	dsll	at,at,0x11
+ 1a4:	0081082b 	sltu	at,a0,at
+ 1a8:	1020000c 	beqz	at,1dc <[^>]*>
+ 1ac:	00000000 	nop
+ 1b0:	34018000 	li	at,0x8000
+ 1b4:	00010c38 	dsll	at,at,0x10
+ 1b8:	0081082a 	slt	at,a0,at
+ 1bc:	14200007 	bnez	at,1dc <[^>]*>
+ 1c0:	00000000 	nop
+ 1c4:	34018000 	li	at,0x8000
+ 1c8:	00010c78 	dsll	at,at,0x11
+ 1cc:	0081082b 	sltu	at,a0,at
+ 1d0:	14200002 	bnez	at,1dc <[^>]*>
+ 1d4:	00000000 	nop
+ 1d8:	46231040 	add.d	\$f1,\$f2,\$f3
 
-0+0234 <[^>]*>:
+0+01dc <[^>]*>:
 	...
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index f323d3e964d1..7843f2a9742b 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -254,7 +254,7 @@ proc mips_arch_list_matching {args} {
 	# properties actually are.
 	if { [string compare $arch default] == 0
 	     && [string length [mips_arch_properties default]] == 0} {
-	    continue;
+	    continue
 	}
 	if { [mips_arch_matches $arch $args] } {
 	    lappend l $arch
@@ -383,12 +383,14 @@ mips_arch_create sb1 	64	mips64	{ mips3d } \
 			{ -march=sb1 -mtune=sb1 } { -mmips:sb1 } \
 			{ mipsisa64sb1-*-* mipsisa64sb1el-*-* }
 
-
 #
-# And now begin the actual tests!
+# And now begin the actual tests!  VxWorks uses RELA rather than REL
+# relocations, so most of the generic dump tests will not work there.
 #
-
-if { [istarget mips*-*-*] } then {
+if { [istarget mips*-*-vxworks*] } {
+    run_dump_test "vxworks1"
+    run_dump_test "vxworks1-xgot"
+} elseif { [istarget mips*-*-*] } {
     set no_mips16 0
     set elf [expr [istarget *-*-elf*] || [istarget *-*-irix5*] || [istarget *-*-irix6* ] || [istarget *-*-linux*] || [istarget *-*-netbsd*] ]
     set ecoff [expr [istarget *-*-ecoff*] || [istarget *-*-ultrix*] || [istarget *-*-irix\[1-4\]*] ]
@@ -427,8 +429,11 @@ if { [istarget mips*-*-*] } then {
     run_dump_test_arches "blt"		[mips_arch_list_matching mips2]
     run_dump_test_arches "bltu"		[mips_arch_list_matching mips2]
     run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1]
-    run_list_test_arches "branch-misc-2" "-32 -non_shared" [mips_arch_list_matching mips1]
-    run_list_test_arches "branch-misc-2pic" "-32 -call_shared" [mips_arch_list_matching mips1]
+    run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1]
+    run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1]
+    run_dump_test_arches "branch-misc-2-64" [mips_arch_list_matching mips3]
+    run_dump_test_arches "branch-misc-2pic-64" [mips_arch_list_matching mips3]
+    run_dump_test "branch-misc-3"
     run_dump_test "branch-swap"
 
     if $ilocks {
@@ -446,24 +451,11 @@ if { [istarget mips*-*-*] } then {
     }
     if $elf { run_dump_test "jal-svr4pic" }
     if $elf { run_dump_test "jal-xgot" }
-    # LOSE: As of 2002-02-08, the jal-empic test fails for target mips-ecoff.
-    # It appears that it broke between 2000-03-11 00:00UTC and
-    # 2000-03-12 00:00 UTC.
-    if $ecoff { run_dump_test "jal-empic" }
-    if $elf {
-	run_dump_test_arches "jal-empic-elf" [mips_arch_list_matching mips1]
-	run_dump_test_arches "jal-empic-elf-2" [mips_arch_list_matching mips1]
-	run_dump_test_arches "jal-empic-elf-3" [mips_arch_list_matching mips1]
-    }
     run_list_test_arches "jal-range" "-32" [mips_arch_list_matching mips1]
     if $has_newabi { run_dump_test "jal-newabi" }
     if !$aout { run_dump_test "la" }
     if $elf { run_dump_test "la-svr4pic" }
     if $elf { run_dump_test "la-xgot" }
-    # LOSE: As of 2002-02-08, the la-empic test fails for target mips-ecoff.
-    # Not sure when it first cropped up, but may be related to addition of
-    # "la" -> "addiu" pattern in MIPS opcode table long ago.
-    if $ecoff { run_dump_test "la-empic" }
     if $elf { run_dump_test "lca-svr4pic" }
     if $elf { run_dump_test "lca-xgot" }
     if !$aout {
@@ -472,7 +464,8 @@ if { [istarget mips*-*-*] } then {
 	run_dump_test_arches "lb"	[mips_arch_list_matching !mips2]
     }
     if $elf {
-	run_dump_test_arches "lb-svr4pic" [mips_arch_list_matching mips1]
+	run_dump_test_arches "lb-svr4pic" [mips_arch_list_matching !gpr_ilocks]
+	run_dump_test_arches "lb-svr4pic-ilocks" [mips_arch_list_matching gpr_ilocks]
     }
     if $elf {
 	# Both versions specify the cpu, so we can run both regardless of
@@ -480,7 +473,6 @@ if { [istarget mips*-*-*] } then {
 	run_dump_test "lb-xgot"
 	run_dump_test "lb-xgot-ilocks"
     }
-    if $ecoff { run_dump_test "lb-empic" }
     if !$aout {
         if !$gpr_ilocks {
             run_dump_test "ld"
@@ -494,15 +486,10 @@ if { [istarget mips*-*-*] } then {
     }
     if $elf { run_dump_test "ld-svr4pic" }
     if $elf { run_dump_test "ld-xgot" }
-    if $ecoff { run_dump_test "ld-empic" }
     run_dump_test_arches "li"		[mips_arch_list_matching mips1]
     if !$aout { run_dump_test "lifloat" }
     if $elf { run_dump_test "lif-svr4pic" }
     if $elf { run_dump_test "lif-xgot" }
-    # LOSE: As of 2002-02-08, the lif-empic test fails for target mips-ecoff.
-    # It appears that it broke between 2000-03-11 00:00UTC and
-    # 2000-03-12 00:00 UTC.
-    if $ecoff { run_dump_test "lif-empic" }
     run_dump_test_arches "mips4"	[mips_arch_list_matching mips4]
     run_dump_test_arches "mips5"	[mips_arch_list_matching mips5]
     if $ilocks {
@@ -524,7 +511,6 @@ if { [istarget mips*-*-*] } then {
     run_dump_test_arches "ulh2-el"	[mips_arch_list_matching mips1]
     if $elf { run_dump_test "ulh-svr4pic" }
     if $elf { run_dump_test "ulh-xgot" }
-    if $ecoff { run_dump_test "ulh-empic" }
     if !$aout {
 	run_dump_test "ulw"
 	run_dump_test "uld"
@@ -548,6 +534,11 @@ if { [istarget mips*-*-*] } then {
 	# Check jalx handling
 	run_dump_test "mips16-jalx"
 	run_dump_test "mips-jalx"
+	# Check MIPS16 HI16/LO16 relocations
+	run_dump_test "mips16-hilo"
+	if $has_newabi {
+	    run_dump_test "mips16-hilo-n32"
+	}
     }
     run_list_test "mips-no-jalx" "-32"
     run_dump_test "delay"
@@ -557,7 +548,8 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "mips4100"
     run_dump_test "vr4111"
     run_dump_test "vr4120"
-    run_dump_test "vr4122"
+    run_dump_test "vr4120-2"
+    run_dump_test "vr4130"
     run_dump_test "vr5400"
     run_dump_test "vr5500"
     run_dump_test "rm7000"
@@ -680,18 +672,28 @@ if { [istarget mips*-*-*] } then {
 	    run_dump_test "elf-rel18"
 	}
 	run_dump_test "elf-rel19"
+	run_dump_test "elf-rel20"
+	if $has_newabi {
+	    run_dump_test "elf-rel21"
+	    run_dump_test "elf-rel22"
+	    run_dump_test "elf-rel23"
+	    run_dump_test "elf-rel23a"
+	    run_dump_test "elf-rel23b"
+	    run_dump_test "elf-rel24"
+	}
+
+	run_dump_test "elf-rel25"
+	run_dump_test "elf-rel25a"
 
-	run_dump_test "${tmips}${el}empic"
-	run_dump_test "empic2"
-	run_dump_test "empic3_e"
-	run_dump_test "empic3_g1"
-	run_dump_test "empic3_g2"
 	if { !$no_mips16 } {
 	    run_dump_test "${tmips}mips${el}16-e"
 	    run_dump_test "${tmips}mips${el}16-f"
 	}
 	run_dump_test "elf-consthilo"
 	run_dump_test "expr1"
+
+	run_list_test "tls-ill" "-32"
+	run_dump_test "tls-o32"
     }
 
     if $has_newabi {
@@ -729,12 +731,22 @@ if { [istarget mips*-*-*] } then {
     run_dump_test "hwr-names-mips64r2"
 
     run_dump_test "ldstla-32"
+    run_dump_test "ldstla-32-mips3"
     run_dump_test "ldstla-32-shared"
+    run_dump_test "ldstla-32-mips3-shared"
+    run_list_test "ldstla-32-1" "-mabi=32" \
+	"MIPS ld-st-la bad constants (ABI o32)"
+    run_list_test "ldstla-32-mips3-1" "-mabi=32" \
+	"MIPS ld-st-la bad constants (ABI o32, mips3)"
+    run_list_test "ldstla-32-1" "-KPIC -mabi=32" \
+	"MIPS ld-st-la bad constants (ABI o32, shared)"
+    run_list_test "ldstla-32-mips3-1" "-KPIC -mabi=32" \
+	"MIPS ld-st-la bad constants (ABI o32, mips3, shared)"
+    run_dump_test "ldstla-eabi64"
     if $has_newabi {
-	run_dump_test "ldstla-n32"
-	run_dump_test "ldstla-n32-shared"
 	run_dump_test "ldstla-n64"
 	run_dump_test "ldstla-n64-shared"
+	run_dump_test "ldstla-n64-sym32"
     }
 
     run_dump_test "macro-warn-1"
@@ -745,4 +757,28 @@ if { [istarget mips*-*-*] } then {
 	run_dump_test "macro-warn-1-n32"
 	run_dump_test "macro-warn-2-n32"
     }
+
+    run_dump_test "noat-1"
+    run_list_test "noat-2" ""
+    run_list_test "noat-3" ""
+    run_list_test "noat-4" ""
+    run_list_test "noat-5" ""
+    run_list_test "noat-6" ""
+    run_list_test "noat-7" ""
+
+    run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32 !sb1]
+    run_dump_test_arches "mips32-mt"	[mips_arch_list_matching mips32r2 !gpr64]
+
+    if { $elf && !$no_mips16 } {
+	run_dump_test "mips16-dwarf2"
+	if $has_newabi {
+	    run_dump_test "mips16-dwarf2-n32"
+	}
+    }
+    if { !$no_mips16 } { 
+        run_dump_test "mips16e-jrc"
+        run_dump_test "mips16e-save"
+    }
+    run_dump_test "vxworks1"
+    run_dump_test "vxworks1-xgot"
 }
diff --git a/gas/testsuite/gas/mips/mips16-dwarf2-n32.d b/gas/testsuite/gas/mips/mips16-dwarf2-n32.d
new file mode 100644
index 000000000000..e95325dfb581
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-dwarf2-n32.d
@@ -0,0 +1,30 @@
+#readelf: -r -wl
+#name: MIPS16 DWARF2 N32
+#as: -march=mips3 -mabi=n32 -mips16 -no-mdebug -g0
+#source: mips16-dwarf2.s
+
+Relocation section '\.rela\.debug_info' at offset .* contains 4 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name \+ Addend
+0+0006 * 0+..02 * R_MIPS_32 * 0+0000 * \.debug_abbrev \+ 0
+0+000c * 0+..02 * R_MIPS_32 * 0+0000 * \.debug_line \+ 0
+0+0010 * 0+..02 * R_MIPS_32 * 0+0000 * \.text \+ 0
+0+0014 * 0+..02 * R_MIPS_32 * 0+0000 * \.text \+ 910
+
+Relocation section '\.rela\.debug_line' at offset .* contains 1 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name \+ Addend
+0+0033 * 0+..02 * R_MIPS_32 * 0+0000 * .text \+ 1
+
+#...
+ Line Number Statements:
+  Extended opcode 2: set Address to 0x0
+  Copy
+  Special opcode .*: advance Address by 2 to 0x2 and Line by 1 to 2
+  Special opcode .*: advance Address by 2 to 0x4 and Line by 1 to 3
+  Special opcode .*: advance Address by 4 to 0x8 and Line by 1 to 4
+  Special opcode .*: advance Address by 2 to 0xa and Line by 1 to 5
+  Special opcode .*: advance Address by 4 to 0xe and Line by 1 to 6
+  Special opcode .*: advance Address by 4 to 0x12 and Line by 1 to 7
+  Advance PC by 2286 to 0x900
+  Special opcode .*: advance Address by 0 to 0x900 and Line by 1 to 8
+  Advance PC by 15 to 0x90f
+  Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/mips/mips16-dwarf2.d b/gas/testsuite/gas/mips/mips16-dwarf2.d
new file mode 100644
index 000000000000..bda0feb43105
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-dwarf2.d
@@ -0,0 +1,30 @@
+#readelf: -r -wl
+#name: MIPS16 DWARF2
+#as: -mabi=32 -mips16 -no-mdebug -g0
+#source: mips16-dwarf2.s
+
+Relocation section '\.rel\.debug_info' at offset .* contains 4 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name
+0+0006 * 0+..02 * R_MIPS_32 * 0+0000 * \.debug_abbrev
+0+000c * 0+..02 * R_MIPS_32 * 0+0000 * \.debug_line
+0+0010 * 0+..02 * R_MIPS_32 * 0+0000 * \.text
+0+0014 * 0+..02 * R_MIPS_32 * 0+0000 * \.text
+
+Relocation section '\.rel\.debug_line' at offset .* contains 1 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name
+0+0033 * 0+..02 * R_MIPS_32 * 0+0000 * \.text
+
+#...
+ Line Number Statements:
+  Extended opcode 2: set Address to 0x1
+  Copy
+  Special opcode .*: advance Address by 2 to 0x3 and Line by 1 to 2
+  Special opcode .*: advance Address by 2 to 0x5 and Line by 1 to 3
+  Special opcode .*: advance Address by 4 to 0x9 and Line by 1 to 4
+  Special opcode .*: advance Address by 2 to 0xb and Line by 1 to 5
+  Special opcode .*: advance Address by 4 to 0xf and Line by 1 to 6
+  Special opcode .*: advance Address by 4 to 0x13 and Line by 1 to 7
+  Advance PC by 2286 to 0x901
+  Special opcode .*: advance Address by 0 to 0x901 and Line by 1 to 8
+  Advance PC by 15 to 0x910
+  Extended opcode 1: End of Sequence
diff --git a/gas/testsuite/gas/mips/mips16-dwarf2.s b/gas/testsuite/gas/mips/mips16-dwarf2.s
new file mode 100644
index 000000000000..7c0a919a069f
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-dwarf2.s
@@ -0,0 +1,66 @@
+# Source file used to test DWARF2 information for MIPS16.
+
+	.set	mips16
+
+	.text
+.Ltext0:
+	.p2align 2
+
+	.file	1 "mips16-dwarf2.s"
+stuff:
+	.loc	1 1 0
+	nop
+	.loc	1 2 0
+	li	$2, 0
+	.loc	1 3 0
+	li	$2, 0x1234
+	.loc	1 4 0
+	lw	$2, 0f
+	.loc	1 5 0
+	lw	$2, 1f
+	.loc	1 6 0
+	b	0f
+	nop
+	.loc	1 7 0
+	b	1f
+	nop
+	.loc	1 8 0
+
+	.p2align 8
+0:
+	.space	2048
+1:
+	nop
+# align section end to 16-byte boundary for easier testing on multiple targets
+	.p2align 4
+.Letext0:
+
+	.section .debug_info,"",@progbits
+.Ldebug_info0:
+	.4byte	.Ledebug_info0 - .L1debug_info0	# length
+.L1debug_info0:
+	.2byte	2				# version
+	.4byte	.Ldebug_abbrev0			# abbrev offset
+	.byte	4				# address size
+	.uleb128 0x1				# abbrev code
+	.4byte	.Ldebug_line0			# DW_AT_stmt_list
+	.4byte	.Ltext0				# DW_AT_low_pc
+	.4byte	.Letext0			# DW_AT_high_pc
+.Ledebug_info0:
+
+	.section .debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+	.uleb128 0x1				# abbrev code
+	.uleb128 0x11				# DW_TAG_compile_unit
+	.byte	0x0				# DW_CHILDREN_no
+	.uleb128 0x10				# DW_AT_stmt_list
+	.uleb128 0x6				# DW_FORM_data4
+	.uleb128 0x11				# DW_AT_low_pc
+	.uleb128 0x1				# DW_FORM_addr
+	.uleb128 0x12				# DW_AT_high_pc
+	.uleb128 0x1				# DW_FORM_addr
+	.byte	0x0
+	.byte	0x0
+
+	.section .debug_line,"",@progbits
+.Ldebug_line0:
diff --git a/gas/testsuite/gas/mips/mips16-hilo-n32.d b/gas/testsuite/gas/mips/mips16-hilo-n32.d
new file mode 100644
index 000000000000..2e3c8a15bd63
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo-n32.d
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi n32
+#as: -mips16 -mabi=n32 -march=mips64
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+   0:	6c00      	li	a0,0
+   2:	f400 3480 	sll	a0,16
+   6:	4c00      	addiu	a0,0
+   8:	f000 6c00 	li	a0,0
+			8: R_MIPS16_HI16	\.data
+   c:	f400 3480 	sll	a0,16
+  10:	f000 4c00 	addiu	a0,0
+			10: R_MIPS16_LO16	\.data
+  14:	f000 6c00 	li	a0,0
+			14: R_MIPS16_HI16	\.data\+0x4
+  18:	f400 3480 	sll	a0,16
+  1c:	f000 4c00 	addiu	a0,0
+			1c: R_MIPS16_LO16	\.data\+0x4
+  20:	f000 6c00 	li	a0,0
+			20: R_MIPS16_HI16	big_external_data_label
+  24:	f400 3480 	sll	a0,16
+  28:	f000 4c00 	addiu	a0,0
+			28: R_MIPS16_LO16	big_external_data_label
+  2c:	f000 6c00 	li	a0,0
+			2c: R_MIPS16_HI16	small_external_data_label
+  30:	f400 3480 	sll	a0,16
+  34:	f000 4c00 	addiu	a0,0
+			34: R_MIPS16_LO16	small_external_data_label
+  38:	f000 6c00 	li	a0,0
+			38: R_MIPS16_HI16	big_external_common
+  3c:	f400 3480 	sll	a0,16
+  40:	f000 4c00 	addiu	a0,0
+			40: R_MIPS16_LO16	big_external_common
+  44:	f000 6c00 	li	a0,0
+			44: R_MIPS16_HI16	small_external_common
+  48:	f400 3480 	sll	a0,16
+  4c:	f000 4c00 	addiu	a0,0
+			4c: R_MIPS16_LO16	small_external_common
+  50:	f000 6c00 	li	a0,0
+			50: R_MIPS16_HI16	\.bss
+  54:	f400 3480 	sll	a0,16
+  58:	f000 4c00 	addiu	a0,0
+			58: R_MIPS16_LO16	\.bss
+  5c:	f000 6c00 	li	a0,0
+			5c: R_MIPS16_HI16	\.sbss
+  60:	f400 3480 	sll	a0,16
+  64:	f000 4c00 	addiu	a0,0
+			64: R_MIPS16_LO16	\.sbss
+  68:	6c00      	li	a0,0
+  6a:	f400 3480 	sll	a0,16
+  6e:	4c01      	addiu	a0,1
+  70:	f000 6c00 	li	a0,0
+			70: R_MIPS16_HI16	\.data\+0x1
+  74:	f400 3480 	sll	a0,16
+  78:	f000 4c00 	addiu	a0,0
+			78: R_MIPS16_LO16	\.data\+0x1
+  7c:	f000 6c00 	li	a0,0
+			7c: R_MIPS16_HI16	\.data\+0x5
+  80:	f400 3480 	sll	a0,16
+  84:	f000 4c00 	addiu	a0,0
+			84: R_MIPS16_LO16	\.data\+0x5
+  88:	f000 6c00 	li	a0,0
+			88: R_MIPS16_HI16	big_external_data_label\+0x1
+  8c:	f400 3480 	sll	a0,16
+  90:	f000 4c00 	addiu	a0,0
+			90: R_MIPS16_LO16	big_external_data_label\+0x1
+  94:	f000 6c00 	li	a0,0
+			94: R_MIPS16_HI16	small_external_data_label\+0x1
+  98:	f400 3480 	sll	a0,16
+  9c:	f000 4c00 	addiu	a0,0
+			9c: R_MIPS16_LO16	small_external_data_label\+0x1
+  a0:	f000 6c00 	li	a0,0
+			a0: R_MIPS16_HI16	big_external_common\+0x1
+  a4:	f400 3480 	sll	a0,16
+  a8:	f000 4c00 	addiu	a0,0
+			a8: R_MIPS16_LO16	big_external_common\+0x1
+  ac:	f000 6c00 	li	a0,0
+			ac: R_MIPS16_HI16	small_external_common\+0x1
+  b0:	f400 3480 	sll	a0,16
+  b4:	f000 4c00 	addiu	a0,0
+			b4: R_MIPS16_LO16	small_external_common\+0x1
+  b8:	f000 6c00 	li	a0,0
+			b8: R_MIPS16_HI16	\.bss\+0x1
+  bc:	f400 3480 	sll	a0,16
+  c0:	f000 4c00 	addiu	a0,0
+			c0: R_MIPS16_LO16	\.bss\+0x1
+  c4:	f000 6c00 	li	a0,0
+			c4: R_MIPS16_HI16	\.sbss\+0x1
+  c8:	f400 3480 	sll	a0,16
+  cc:	f000 4c00 	addiu	a0,0
+			cc: R_MIPS16_LO16	\.sbss\+0x1
+  d0:	6c01      	li	a0,1
+  d2:	f400 3480 	sll	a0,16
+  d6:	f010 4c00 	addiu	a0,-32768
+  da:	f000 6c00 	li	a0,0
+			da: R_MIPS16_HI16	\.data\+0x8000
+  de:	f400 3480 	sll	a0,16
+  e2:	f000 4c00 	addiu	a0,0
+			e2: R_MIPS16_LO16	\.data\+0x8000
+  e6:	f000 6c00 	li	a0,0
+			e6: R_MIPS16_HI16	\.data\+0x8004
+  ea:	f400 3480 	sll	a0,16
+  ee:	f000 4c00 	addiu	a0,0
+			ee: R_MIPS16_LO16	\.data\+0x8004
+  f2:	f000 6c00 	li	a0,0
+			f2: R_MIPS16_HI16	big_external_data_label\+0x8000
+  f6:	f400 3480 	sll	a0,16
+  fa:	f000 4c00 	addiu	a0,0
+			fa: R_MIPS16_LO16	big_external_data_label\+0x8000
+  fe:	f000 6c00 	li	a0,0
+			fe: R_MIPS16_HI16	small_external_data_label\+0x8000
+ 102:	f400 3480 	sll	a0,16
+ 106:	f000 4c00 	addiu	a0,0
+			106: R_MIPS16_LO16	small_external_data_label\+0x8000
+ 10a:	f000 6c00 	li	a0,0
+			10a: R_MIPS16_HI16	big_external_common\+0x8000
+ 10e:	f400 3480 	sll	a0,16
+ 112:	f000 4c00 	addiu	a0,0
+			112: R_MIPS16_LO16	big_external_common\+0x8000
+ 116:	f000 6c00 	li	a0,0
+			116: R_MIPS16_HI16	small_external_common\+0x8000
+ 11a:	f400 3480 	sll	a0,16
+ 11e:	f000 4c00 	addiu	a0,0
+			11e: R_MIPS16_LO16	small_external_common\+0x8000
+ 122:	f000 6c00 	li	a0,0
+			122: R_MIPS16_HI16	\.bss\+0x8000
+ 126:	f400 3480 	sll	a0,16
+ 12a:	f000 4c00 	addiu	a0,0
+			12a: R_MIPS16_LO16	\.bss\+0x8000
+ 12e:	f000 6c00 	li	a0,0
+			12e: R_MIPS16_HI16	\.sbss\+0x8000
+ 132:	f400 3480 	sll	a0,16
+ 136:	f000 4c00 	addiu	a0,0
+			136: R_MIPS16_LO16	\.sbss\+0x8000
+ 13a:	6c00      	li	a0,0
+ 13c:	f400 3480 	sll	a0,16
+ 140:	f010 4c00 	addiu	a0,-32768
+ 144:	f000 6c00 	li	a0,0
+			144: R_MIPS16_HI16	\.data\+0xffff8000
+ 148:	f400 3480 	sll	a0,16
+ 14c:	f000 4c00 	addiu	a0,0
+			14c: R_MIPS16_LO16	\.data\+0xffff8000
+ 150:	f000 6c00 	li	a0,0
+			150: R_MIPS16_HI16	\.data\+0xffff8004
+ 154:	f400 3480 	sll	a0,16
+ 158:	f000 4c00 	addiu	a0,0
+			158: R_MIPS16_LO16	\.data\+0xffff8004
+ 15c:	f000 6c00 	li	a0,0
+			15c: R_MIPS16_HI16	big_external_data_label\+0xffff8000
+ 160:	f400 3480 	sll	a0,16
+ 164:	f000 4c00 	addiu	a0,0
+			164: R_MIPS16_LO16	big_external_data_label\+0xffff8000
+ 168:	f000 6c00 	li	a0,0
+			168: R_MIPS16_HI16	small_external_data_label\+0xffff8000
+ 16c:	f400 3480 	sll	a0,16
+ 170:	f000 4c00 	addiu	a0,0
+			170: R_MIPS16_LO16	small_external_data_label\+0xffff8000
+ 174:	f000 6c00 	li	a0,0
+			174: R_MIPS16_HI16	big_external_common\+0xffff8000
+ 178:	f400 3480 	sll	a0,16
+ 17c:	f000 4c00 	addiu	a0,0
+			17c: R_MIPS16_LO16	big_external_common\+0xffff8000
+ 180:	f000 6c00 	li	a0,0
+			180: R_MIPS16_HI16	small_external_common\+0xffff8000
+ 184:	f400 3480 	sll	a0,16
+ 188:	f000 4c00 	addiu	a0,0
+			188: R_MIPS16_LO16	small_external_common\+0xffff8000
+ 18c:	f000 6c00 	li	a0,0
+			18c: R_MIPS16_HI16	\.bss\+0xffff8000
+ 190:	f400 3480 	sll	a0,16
+ 194:	f000 4c00 	addiu	a0,0
+			194: R_MIPS16_LO16	\.bss\+0xffff8000
+ 198:	f000 6c00 	li	a0,0
+			198: R_MIPS16_HI16	\.sbss\+0xffff8000
+ 19c:	f400 3480 	sll	a0,16
+ 1a0:	f000 4c00 	addiu	a0,0
+			1a0: R_MIPS16_LO16	\.sbss\+0xffff8000
+ 1a4:	6c01      	li	a0,1
+ 1a6:	f400 3480 	sll	a0,16
+ 1aa:	4c00      	addiu	a0,0
+ 1ac:	f000 6c00 	li	a0,0
+			1ac: R_MIPS16_HI16	\.data\+0x10000
+ 1b0:	f400 3480 	sll	a0,16
+ 1b4:	f000 4c00 	addiu	a0,0
+			1b4: R_MIPS16_LO16	\.data\+0x10000
+ 1b8:	f000 6c00 	li	a0,0
+			1b8: R_MIPS16_HI16	\.data\+0x10004
+ 1bc:	f400 3480 	sll	a0,16
+ 1c0:	f000 4c00 	addiu	a0,0
+			1c0: R_MIPS16_LO16	\.data\+0x10004
+ 1c4:	f000 6c00 	li	a0,0
+			1c4: R_MIPS16_HI16	big_external_data_label\+0x10000
+ 1c8:	f400 3480 	sll	a0,16
+ 1cc:	f000 4c00 	addiu	a0,0
+			1cc: R_MIPS16_LO16	big_external_data_label\+0x10000
+ 1d0:	f000 6c00 	li	a0,0
+			1d0: R_MIPS16_HI16	small_external_data_label\+0x10000
+ 1d4:	f400 3480 	sll	a0,16
+ 1d8:	f000 4c00 	addiu	a0,0
+			1d8: R_MIPS16_LO16	small_external_data_label\+0x10000
+ 1dc:	f000 6c00 	li	a0,0
+			1dc: R_MIPS16_HI16	big_external_common\+0x10000
+ 1e0:	f400 3480 	sll	a0,16
+ 1e4:	f000 4c00 	addiu	a0,0
+			1e4: R_MIPS16_LO16	big_external_common\+0x10000
+ 1e8:	f000 6c00 	li	a0,0
+			1e8: R_MIPS16_HI16	small_external_common\+0x10000
+ 1ec:	f400 3480 	sll	a0,16
+ 1f0:	f000 4c00 	addiu	a0,0
+			1f0: R_MIPS16_LO16	small_external_common\+0x10000
+ 1f4:	f000 6c00 	li	a0,0
+			1f4: R_MIPS16_HI16	\.bss\+0x10000
+ 1f8:	f400 3480 	sll	a0,16
+ 1fc:	f000 4c00 	addiu	a0,0
+			1fc: R_MIPS16_LO16	\.bss\+0x10000
+ 200:	f000 6c00 	li	a0,0
+			200: R_MIPS16_HI16	\.sbss\+0x10000
+ 204:	f400 3480 	sll	a0,16
+ 208:	f000 4c00 	addiu	a0,0
+			208: R_MIPS16_LO16	\.sbss\+0x10000
+ 20c:	6c02      	li	a0,2
+ 20e:	f400 3480 	sll	a0,16
+ 212:	f5b4 4c05 	addiu	a0,-23131
+ 216:	f000 6c00 	li	a0,0
+			216: R_MIPS16_HI16	\.data\+0x1a5a5
+ 21a:	f400 3480 	sll	a0,16
+ 21e:	f000 4c00 	addiu	a0,0
+			21e: R_MIPS16_LO16	\.data\+0x1a5a5
+ 222:	f000 6c00 	li	a0,0
+			222: R_MIPS16_HI16	\.data\+0x1a5a9
+ 226:	f400 3480 	sll	a0,16
+ 22a:	f000 4c00 	addiu	a0,0
+			22a: R_MIPS16_LO16	\.data\+0x1a5a9
+ 22e:	f000 6c00 	li	a0,0
+			22e: R_MIPS16_HI16	big_external_data_label\+0x1a5a5
+ 232:	f400 3480 	sll	a0,16
+ 236:	f000 4c00 	addiu	a0,0
+			236: R_MIPS16_LO16	big_external_data_label\+0x1a5a5
+ 23a:	f000 6c00 	li	a0,0
+			23a: R_MIPS16_HI16	small_external_data_label\+0x1a5a5
+ 23e:	f400 3480 	sll	a0,16
+ 242:	f000 4c00 	addiu	a0,0
+			242: R_MIPS16_LO16	small_external_data_label\+0x1a5a5
+ 246:	f000 6c00 	li	a0,0
+			246: R_MIPS16_HI16	big_external_common\+0x1a5a5
+ 24a:	f400 3480 	sll	a0,16
+ 24e:	f000 4c00 	addiu	a0,0
+			24e: R_MIPS16_LO16	big_external_common\+0x1a5a5
+ 252:	f000 6c00 	li	a0,0
+			252: R_MIPS16_HI16	small_external_common\+0x1a5a5
+ 256:	f400 3480 	sll	a0,16
+ 25a:	f000 4c00 	addiu	a0,0
+			25a: R_MIPS16_LO16	small_external_common\+0x1a5a5
+ 25e:	f000 6c00 	li	a0,0
+			25e: R_MIPS16_HI16	\.bss\+0x1a5a5
+ 262:	f400 3480 	sll	a0,16
+ 266:	f000 4c00 	addiu	a0,0
+			266: R_MIPS16_LO16	\.bss\+0x1a5a5
+ 26a:	f000 6c00 	li	a0,0
+			26a: R_MIPS16_HI16	\.sbss\+0x1a5a5
+ 26e:	f400 3480 	sll	a0,16
+ 272:	f000 4c00 	addiu	a0,0
+			272: R_MIPS16_LO16	\.sbss\+0x1a5a5
+ 276:	6d00      	li	a1,0
+ 278:	f400 35a0 	sll	a1,16
+ 27c:	9d80      	lw	a0,0\(a1\)
+ 27e:	f000 6d00 	li	a1,0
+			27e: R_MIPS16_HI16	\.data
+ 282:	f400 35a0 	sll	a1,16
+ 286:	f000 9d80 	lw	a0,0\(a1\)
+			286: R_MIPS16_HI16	\.data
+ 28a:	f000 6d00 	li	a1,0
+			28a: R_MIPS16_HI16	\.data\+0x4
+ 28e:	f400 35a0 	sll	a1,16
+ 292:	f000 9d80 	lw	a0,0\(a1\)
+			292: R_MIPS16_HI16	\.data\+0x4
+ 296:	f000 6d00 	li	a1,0
+			296: R_MIPS16_HI16	big_external_data_label
+ 29a:	f400 35a0 	sll	a1,16
+ 29e:	f000 9d80 	lw	a0,0\(a1\)
+			29e: R_MIPS16_LO16	big_external_data_label
+ 2a2:	f000 6d00 	li	a1,0
+			2a2: R_MIPS16_HI16	small_external_data_label
+ 2a6:	f400 35a0 	sll	a1,16
+ 2aa:	f000 9d80 	lw	a0,0\(a1\)
+			2aa: R_MIPS16_LO16	small_external_data_label
+ 2ae:	f000 6d00 	li	a1,0
+			2ae: R_MIPS16_HI16	big_external_common
+ 2b2:	f400 35a0 	sll	a1,16
+ 2b6:	f000 9d80 	lw	a0,0\(a1\)
+			2b6: R_MIPS16_LO16	big_external_common
+ 2ba:	f000 6d00 	li	a1,0
+			2ba: R_MIPS16_HI16	small_external_common
+ 2be:	f400 35a0 	sll	a1,16
+ 2c2:	f000 9d80 	lw	a0,0\(a1\)
+			2c2: R_MIPS16_LO16	small_external_common
+ 2c6:	f000 6d00 	li	a1,0
+			2c6: R_MIPS16_HI16	\.bss
+ 2ca:	f400 35a0 	sll	a1,16
+ 2ce:	f000 9d80 	lw	a0,0\(a1\)
+			2ce: R_MIPS16_LO16	\.bss
+ 2d2:	f000 6d00 	li	a1,0
+			2d2: R_MIPS16_HI16	\.sbss
+ 2d6:	f400 35a0 	sll	a1,16
+ 2da:	f000 9d80 	lw	a0,0\(a1\)
+			2da: R_MIPS16_LO16	\.sbss
+ 2de:	6d00      	li	a1,0
+ 2e0:	f400 35a0 	sll	a1,16
+ 2e4:	f000 9d81 	lw	a0,1\(a1\)
+ 2e8:	f000 6d00 	li	a1,0
+			2e8: R_MIPS16_HI16	\.data\+0x1
+ 2ec:	f400 35a0 	sll	a1,16
+ 2f0:	f000 9d80 	lw	a0,0\(a1\)
+			2f0: R_MIPS16_LO16	\.data\+0x1
+ 2f4:	f000 6d00 	li	a1,0
+			2f4: R_MIPS16_HI16	\.data\+0x5
+ 2f8:	f400 35a0 	sll	a1,16
+ 2fc:	f000 9d80 	lw	a0,0\(a1\)
+			2fc: R_MIPS16_LO16	\.data\+0x5
+ 300:	f000 6d00 	li	a1,0
+			300: R_MIPS16_HI16	big_external_data_label\+0x1
+ 304:	f400 35a0 	sll	a1,16
+ 308:	f000 9d80 	lw	a0,0\(a1\)
+			308: R_MIPS16_LO16	big_external_data_label\+0x1
+ 30c:	f000 6d00 	li	a1,0
+			30c: R_MIPS16_HI16	small_external_data_label\+0x1
+ 310:	f400 35a0 	sll	a1,16
+ 314:	f000 9d80 	lw	a0,0\(a1\)
+			314: R_MIPS16_LO16	small_external_data_label\+0x1
+ 318:	f000 6d00 	li	a1,0
+			318: R_MIPS16_HI16	big_external_common\+0x1
+ 31c:	f400 35a0 	sll	a1,16
+ 320:	f000 9d80 	lw	a0,0\(a1\)
+			320: R_MIPS16_LO16	big_external_common\+0x1
+ 324:	f000 6d00 	li	a1,0
+			324: R_MIPS16_HI16	small_external_common\+0x1
+ 328:	f400 35a0 	sll	a1,16
+ 32c:	f000 9d80 	lw	a0,0\(a1\)
+			32c: R_MIPS16_LO16	small_external_common\+0x1
+ 330:	f000 6d00 	li	a1,0
+			330: R_MIPS16_HI16	\.bss\+0x1
+ 334:	f400 35a0 	sll	a1,16
+ 338:	f000 9d80 	lw	a0,0\(a1\)
+			338: R_MIPS16_LO16	\.bss\+0x1
+ 33c:	f000 6d00 	li	a1,0
+			33c: R_MIPS16_HI16	\.sbss\+0x1
+ 340:	f400 35a0 	sll	a1,16
+ 344:	f000 9d80 	lw	a0,0\(a1\)
+			344: R_MIPS16_LO16	\.sbss\+0x1
+ 348:	6d01      	li	a1,1
+ 34a:	f400 35a0 	sll	a1,16
+ 34e:	f010 9d80 	lw	a0,-32768\(a1\)
+ 352:	f000 6d00 	li	a1,0
+			352: R_MIPS16_HI16	\.data\+0x8000
+ 356:	f400 35a0 	sll	a1,16
+ 35a:	f000 9d80 	lw	a0,0\(a1\)
+			35a: R_MIPS16_LO16	\.data\+0x8000
+ 35e:	f000 6d00 	li	a1,0
+			35e: R_MIPS16_HI16	\.data\+0x8004
+ 362:	f400 35a0 	sll	a1,16
+ 366:	f000 9d80 	lw	a0,0\(a1\)
+			366: R_MIPS16_LO16	\.data\+0x8004
+ 36a:	f000 6d00 	li	a1,0
+			36a: R_MIPS16_HI16	big_external_data_label\+0x8000
+ 36e:	f400 35a0 	sll	a1,16
+ 372:	f000 9d80 	lw	a0,0\(a1\)
+			372: R_MIPS16_LO16	big_external_data_label\+0x8000
+ 376:	f000 6d00 	li	a1,0
+			376: R_MIPS16_HI16	small_external_data_label\+0x8000
+ 37a:	f400 35a0 	sll	a1,16
+ 37e:	f000 9d80 	lw	a0,0\(a1\)
+			37e: R_MIPS16_LO16	small_external_data_label\+0x8000
+ 382:	f000 6d00 	li	a1,0
+			382: R_MIPS16_HI16	big_external_common\+0x8000
+ 386:	f400 35a0 	sll	a1,16
+ 38a:	f000 9d80 	lw	a0,0\(a1\)
+			38a: R_MIPS16_LO16	big_external_common\+0x8000
+ 38e:	f000 6d00 	li	a1,0
+			38e: R_MIPS16_HI16	small_external_common\+0x8000
+ 392:	f400 35a0 	sll	a1,16
+ 396:	f000 9d80 	lw	a0,0\(a1\)
+			396: R_MIPS16_LO16	small_external_common\+0x8000
+ 39a:	f000 6d00 	li	a1,0
+			39a: R_MIPS16_HI16	\.bss\+0x8000
+ 39e:	f400 35a0 	sll	a1,16
+ 3a2:	f000 9d80 	lw	a0,0\(a1\)
+			3a2: R_MIPS16_LO16	\.bss\+0x8000
+ 3a6:	f000 6d00 	li	a1,0
+			3a6: R_MIPS16_HI16	\.sbss\+0x8000
+ 3aa:	f400 35a0 	sll	a1,16
+ 3ae:	f000 9d80 	lw	a0,0\(a1\)
+			3ae: R_MIPS16_LO16	\.sbss\+0x8000
+ 3b2:	6d00      	li	a1,0
+ 3b4:	f400 35a0 	sll	a1,16
+ 3b8:	f010 9d80 	lw	a0,-32768\(a1\)
+ 3bc:	f000 6d00 	li	a1,0
+			3bc: R_MIPS16_HI16	\.data\+0xffff8000
+ 3c0:	f400 35a0 	sll	a1,16
+ 3c4:	f000 9d80 	lw	a0,0\(a1\)
+			3c4: R_MIPS16_LO16	\.data\+0xffff8000
+ 3c8:	f000 6d00 	li	a1,0
+			3c8: R_MIPS16_HI16	\.data\+0xffff8004
+ 3cc:	f400 35a0 	sll	a1,16
+ 3d0:	f000 9d80 	lw	a0,0\(a1\)
+			3d0: R_MIPS16_LO16	\.data\+0xffff8004
+ 3d4:	f000 6d00 	li	a1,0
+			3d4: R_MIPS16_HI16	big_external_data_label\+0xffff8000
+ 3d8:	f400 35a0 	sll	a1,16
+ 3dc:	f000 9d80 	lw	a0,0\(a1\)
+			3dc: R_MIPS16_LO16	big_external_data_label\+0xffff8000
+ 3e0:	f000 6d00 	li	a1,0
+			3e0: R_MIPS16_HI16	small_external_data_label\+0xffff8000
+ 3e4:	f400 35a0 	sll	a1,16
+ 3e8:	f000 9d80 	lw	a0,0\(a1\)
+			3e8: R_MIPS16_LO16	small_external_data_label\+0xffff8000
+ 3ec:	f000 6d00 	li	a1,0
+			3ec: R_MIPS16_HI16	big_external_common\+0xffff8000
+ 3f0:	f400 35a0 	sll	a1,16
+ 3f4:	f000 9d80 	lw	a0,0\(a1\)
+			3f4: R_MIPS16_LO16	big_external_common\+0xffff8000
+ 3f8:	f000 6d00 	li	a1,0
+			3f8: R_MIPS16_HI16	small_external_common\+0xffff8000
+ 3fc:	f400 35a0 	sll	a1,16
+ 400:	f000 9d80 	lw	a0,0\(a1\)
+			400: R_MIPS16_LO16	small_external_common\+0xffff8000
+ 404:	f000 6d00 	li	a1,0
+			404: R_MIPS16_HI16	\.bss\+0xffff8000
+ 408:	f400 35a0 	sll	a1,16
+ 40c:	f000 9d80 	lw	a0,0\(a1\)
+			40c: R_MIPS16_LO16	\.bss\+0xffff8000
+ 410:	f000 6d00 	li	a1,0
+			410: R_MIPS16_HI16	\.sbss\+0xffff8000
+ 414:	f400 35a0 	sll	a1,16
+ 418:	f000 9d80 	lw	a0,0\(a1\)
+			418: R_MIPS16_LO16	\.sbss\+0xffff8000
+ 41c:	6d01      	li	a1,1
+ 41e:	f400 35a0 	sll	a1,16
+ 422:	9d80      	lw	a0,0\(a1\)
+ 424:	f000 6d00 	li	a1,0
+			424: R_MIPS16_HI16	\.data\+0x10000
+ 428:	f400 35a0 	sll	a1,16
+ 42c:	f000 9d80 	lw	a0,0\(a1\)
+			42c: R_MIPS16_LO16	\.data\+0x10000
+ 430:	f000 6d00 	li	a1,0
+			430: R_MIPS16_HI16	\.data\+0x10004
+ 434:	f400 35a0 	sll	a1,16
+ 438:	f000 9d80 	lw	a0,0\(a1\)
+			438: R_MIPS16_LO16	\.data\+0x10004
+ 43c:	f000 6d00 	li	a1,0
+			43c: R_MIPS16_HI16	big_external_data_label\+0x10000
+ 440:	f400 35a0 	sll	a1,16
+ 444:	f000 9d80 	lw	a0,0\(a1\)
+			444: R_MIPS16_LO16	big_external_data_label\+0x10000
+ 448:	f000 6d00 	li	a1,0
+			448: R_MIPS16_HI16	small_external_data_label\+0x10000
+ 44c:	f400 35a0 	sll	a1,16
+ 450:	f000 9d80 	lw	a0,0\(a1\)
+			450: R_MIPS16_LO16	small_external_data_label\+0x10000
+ 454:	f000 6d00 	li	a1,0
+			454: R_MIPS16_HI16	big_external_common\+0x10000
+ 458:	f400 35a0 	sll	a1,16
+ 45c:	f000 9d80 	lw	a0,0\(a1\)
+			45c: R_MIPS16_LO16	big_external_common\+0x10000
+ 460:	f000 6d00 	li	a1,0
+			460: R_MIPS16_HI16	small_external_common\+0x10000
+ 464:	f400 35a0 	sll	a1,16
+ 468:	f000 9d80 	lw	a0,0\(a1\)
+			468: R_MIPS16_LO16	small_external_common\+0x10000
+ 46c:	f000 6d00 	li	a1,0
+			46c: R_MIPS16_HI16	\.bss\+0x10000
+ 470:	f400 35a0 	sll	a1,16
+ 474:	f000 9d80 	lw	a0,0\(a1\)
+			474: R_MIPS16_LO16	\.bss\+0x10000
+ 478:	f000 6d00 	li	a1,0
+			478: R_MIPS16_HI16	\.sbss\+0x10000
+ 47c:	f400 35a0 	sll	a1,16
+ 480:	f000 9d80 	lw	a0,0\(a1\)
+			480: R_MIPS16_LO16	\.sbss\+0x10000
+ 484:	6d02      	li	a1,2
+ 486:	f400 35a0 	sll	a1,16
+ 48a:	f5b4 9d85 	lw	a0,-23131\(a1\)
+ 48e:	f000 6d00 	li	a1,0
+			48e: R_MIPS16_HI16	\.data\+0x1a5a5
+ 492:	f400 35a0 	sll	a1,16
+ 496:	f000 9d80 	lw	a0,0\(a1\)
+			496: R_MIPS16_LO16	\.data\+0x1a5a5
+ 49a:	f000 6d00 	li	a1,0
+			49a: R_MIPS16_HI16	\.data\+0x1a5a9
+ 49e:	f400 35a0 	sll	a1,16
+ 4a2:	f000 9d80 	lw	a0,0\(a1\)
+			4a2: R_MIPS16_LO16	\.data\+0x1a5a9
+ 4a6:	f000 6d00 	li	a1,0
+			4a6: R_MIPS16_HI16	big_external_data_label\+0x1a5a5
+ 4aa:	f400 35a0 	sll	a1,16
+ 4ae:	f000 9d80 	lw	a0,0\(a1\)
+			4ae: R_MIPS16_LO16	big_external_data_label\+0x1a5a5
+ 4b2:	f000 6d00 	li	a1,0
+			4b2: R_MIPS16_HI16	small_external_data_label\+0x1a5a5
+ 4b6:	f400 35a0 	sll	a1,16
+ 4ba:	f000 9d80 	lw	a0,0\(a1\)
+			4ba: R_MIPS16_LO16	small_external_data_label\+0x1a5a5
+ 4be:	f000 6d00 	li	a1,0
+			4be: R_MIPS16_HI16	big_external_common\+0x1a5a5
+ 4c2:	f400 35a0 	sll	a1,16
+ 4c6:	f000 9d80 	lw	a0,0\(a1\)
+			4c6: R_MIPS16_LO16	big_external_common\+0x1a5a5
+ 4ca:	f000 6d00 	li	a1,0
+			4ca: R_MIPS16_HI16	small_external_common\+0x1a5a5
+ 4ce:	f400 35a0 	sll	a1,16
+ 4d2:	f000 9d80 	lw	a0,0\(a1\)
+			4d2: R_MIPS16_LO16	small_external_common\+0x1a5a5
+ 4d6:	f000 6d00 	li	a1,0
+			4d6: R_MIPS16_HI16	\.bss\+0x1a5a5
+ 4da:	f400 35a0 	sll	a1,16
+ 4de:	f000 9d80 	lw	a0,0\(a1\)
+			4de: R_MIPS16_LO16	\.bss\+0x1a5a5
+ 4e2:	f000 6d00 	li	a1,0
+			4e2: R_MIPS16_HI16	\.sbss\+0x1a5a5
+ 4e6:	f400 35a0 	sll	a1,16
+ 4ea:	f000 9d80 	lw	a0,0\(a1\)
+			4ea: R_MIPS16_LO16	\.sbss\+0x1a5a5
+ 4ee:	6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16-hilo.d b/gas/testsuite/gas/mips/mips16-hilo.d
new file mode 100644
index 000000000000..081993a94e5a
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo.d
@@ -0,0 +1,527 @@
+#objdump: -dr
+#name: MIPS16 lui/addi
+#as: -mips16 -mabi=32
+#source: mips16-hilo.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+0+0000 <stuff>:
+   0:	6c00      	li	a0,0
+   2:	f400 3480 	sll	a0,16
+   6:	4c00      	addiu	a0,0
+   8:	f000 6c00 	li	a0,0
+			8: R_MIPS16_HI16	\.data
+   c:	f400 3480 	sll	a0,16
+  10:	f000 4c00 	addiu	a0,0
+			10: R_MIPS16_LO16	\.data
+  14:	f000 6c00 	li	a0,0
+			14: R_MIPS16_HI16	\.data
+  18:	f400 3480 	sll	a0,16
+  1c:	f000 4c04 	addiu	a0,4
+			1c: R_MIPS16_LO16	\.data
+  20:	f000 6c00 	li	a0,0
+			20: R_MIPS16_HI16	big_external_data_label
+  24:	f400 3480 	sll	a0,16
+  28:	f000 4c00 	addiu	a0,0
+			28: R_MIPS16_LO16	big_external_data_label
+  2c:	f000 6c00 	li	a0,0
+			2c: R_MIPS16_HI16	small_external_data_label
+  30:	f400 3480 	sll	a0,16
+  34:	f000 4c00 	addiu	a0,0
+			34: R_MIPS16_LO16	small_external_data_label
+  38:	f000 6c00 	li	a0,0
+			38: R_MIPS16_HI16	big_external_common
+  3c:	f400 3480 	sll	a0,16
+  40:	f000 4c00 	addiu	a0,0
+			40: R_MIPS16_LO16	big_external_common
+  44:	f000 6c00 	li	a0,0
+			44: R_MIPS16_HI16	small_external_common
+  48:	f400 3480 	sll	a0,16
+  4c:	f000 4c00 	addiu	a0,0
+			4c: R_MIPS16_LO16	small_external_common
+  50:	f000 6c00 	li	a0,0
+			50: R_MIPS16_HI16	\.bss
+  54:	f400 3480 	sll	a0,16
+  58:	f000 4c00 	addiu	a0,0
+			58: R_MIPS16_LO16	\.bss
+  5c:	f000 6c00 	li	a0,0
+			5c: R_MIPS16_HI16	\.sbss
+  60:	f400 3480 	sll	a0,16
+  64:	f000 4c00 	addiu	a0,0
+			64: R_MIPS16_LO16	\.sbss
+  68:	6c00      	li	a0,0
+  6a:	f400 3480 	sll	a0,16
+  6e:	4c01      	addiu	a0,1
+  70:	f000 6c00 	li	a0,0
+			70: R_MIPS16_HI16	\.data
+  74:	f400 3480 	sll	a0,16
+  78:	f000 4c01 	addiu	a0,1
+			78: R_MIPS16_LO16	\.data
+  7c:	f000 6c00 	li	a0,0
+			7c: R_MIPS16_HI16	\.data
+  80:	f400 3480 	sll	a0,16
+  84:	f000 4c05 	addiu	a0,5
+			84: R_MIPS16_LO16	\.data
+  88:	f000 6c00 	li	a0,0
+			88: R_MIPS16_HI16	big_external_data_label
+  8c:	f400 3480 	sll	a0,16
+  90:	f000 4c01 	addiu	a0,1
+			90: R_MIPS16_LO16	big_external_data_label
+  94:	f000 6c00 	li	a0,0
+			94: R_MIPS16_HI16	small_external_data_label
+  98:	f400 3480 	sll	a0,16
+  9c:	f000 4c01 	addiu	a0,1
+			9c: R_MIPS16_LO16	small_external_data_label
+  a0:	f000 6c00 	li	a0,0
+			a0: R_MIPS16_HI16	big_external_common
+  a4:	f400 3480 	sll	a0,16
+  a8:	f000 4c01 	addiu	a0,1
+			a8: R_MIPS16_LO16	big_external_common
+  ac:	f000 6c00 	li	a0,0
+			ac: R_MIPS16_HI16	small_external_common
+  b0:	f400 3480 	sll	a0,16
+  b4:	f000 4c01 	addiu	a0,1
+			b4: R_MIPS16_LO16	small_external_common
+  b8:	f000 6c00 	li	a0,0
+			b8: R_MIPS16_HI16	\.bss
+  bc:	f400 3480 	sll	a0,16
+  c0:	f000 4c01 	addiu	a0,1
+			c0: R_MIPS16_LO16	\.bss
+  c4:	f000 6c00 	li	a0,0
+			c4: R_MIPS16_HI16	\.sbss
+  c8:	f400 3480 	sll	a0,16
+  cc:	f000 4c01 	addiu	a0,1
+			cc: R_MIPS16_LO16	\.sbss
+  d0:	6c01      	li	a0,1
+  d2:	f400 3480 	sll	a0,16
+  d6:	f010 4c00 	addiu	a0,-32768
+  da:	f000 6c01 	li	a0,1
+			da: R_MIPS16_HI16	\.data
+  de:	f400 3480 	sll	a0,16
+  e2:	f010 4c00 	addiu	a0,-32768
+			e2: R_MIPS16_LO16	\.data
+  e6:	f000 6c01 	li	a0,1
+			e6: R_MIPS16_HI16	\.data
+  ea:	f400 3480 	sll	a0,16
+  ee:	f010 4c04 	addiu	a0,-32764
+			ee: R_MIPS16_LO16	\.data
+  f2:	f000 6c01 	li	a0,1
+			f2: R_MIPS16_HI16	big_external_data_label
+  f6:	f400 3480 	sll	a0,16
+  fa:	f010 4c00 	addiu	a0,-32768
+			fa: R_MIPS16_LO16	big_external_data_label
+  fe:	f000 6c01 	li	a0,1
+			fe: R_MIPS16_HI16	small_external_data_label
+ 102:	f400 3480 	sll	a0,16
+ 106:	f010 4c00 	addiu	a0,-32768
+			106: R_MIPS16_LO16	small_external_data_label
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+ 112:	f010 4c00 	addiu	a0,-32768
+			112: R_MIPS16_LO16	big_external_common
+ 116:	f000 6c01 	li	a0,1
+			116: R_MIPS16_HI16	small_external_common
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+ 11e:	f010 4c00 	addiu	a0,-32768
+			11e: R_MIPS16_LO16	small_external_common
+ 122:	f000 6c01 	li	a0,1
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+ 126:	f400 3480 	sll	a0,16
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+ 132:	f400 3480 	sll	a0,16
+ 136:	f010 4c00 	addiu	a0,-32768
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+ 140:	f010 4c00 	addiu	a0,-32768
+ 144:	f000 6c00 	li	a0,0
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+ 148:	f400 3480 	sll	a0,16
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+ 150:	f000 6c00 	li	a0,0
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+ 154:	f400 3480 	sll	a0,16
+ 158:	f010 4c04 	addiu	a0,-32764
+			158: R_MIPS16_LO16	\.data
+ 15c:	f000 6c00 	li	a0,0
+			15c: R_MIPS16_HI16	big_external_data_label
+ 160:	f400 3480 	sll	a0,16
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+			164: R_MIPS16_LO16	big_external_data_label
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+ 16c:	f400 3480 	sll	a0,16
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+			170: R_MIPS16_LO16	small_external_data_label
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+ 184:	f400 3480 	sll	a0,16
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+			188: R_MIPS16_LO16	small_external_common
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+ 190:	f400 3480 	sll	a0,16
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+ 19c:	f400 3480 	sll	a0,16
+ 1a0:	f010 4c00 	addiu	a0,-32768
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+ 1aa:	4c00      	addiu	a0,0
+ 1ac:	f000 6c01 	li	a0,1
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+ 1b0:	f400 3480 	sll	a0,16
+ 1b4:	f000 4c00 	addiu	a0,0
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+ 1bc:	f400 3480 	sll	a0,16
+ 1c0:	f000 4c04 	addiu	a0,4
+			1c0: R_MIPS16_LO16	\.data
+ 1c4:	f000 6c01 	li	a0,1
+			1c4: R_MIPS16_HI16	big_external_data_label
+ 1c8:	f400 3480 	sll	a0,16
+ 1cc:	f000 4c00 	addiu	a0,0
+			1cc: R_MIPS16_LO16	big_external_data_label
+ 1d0:	f000 6c01 	li	a0,1
+			1d0: R_MIPS16_HI16	small_external_data_label
+ 1d4:	f400 3480 	sll	a0,16
+ 1d8:	f000 4c00 	addiu	a0,0
+			1d8: R_MIPS16_LO16	small_external_data_label
+ 1dc:	f000 6c01 	li	a0,1
+			1dc: R_MIPS16_HI16	big_external_common
+ 1e0:	f400 3480 	sll	a0,16
+ 1e4:	f000 4c00 	addiu	a0,0
+			1e4: R_MIPS16_LO16	big_external_common
+ 1e8:	f000 6c01 	li	a0,1
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+ 1ec:	f400 3480 	sll	a0,16
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+			1f0: R_MIPS16_LO16	small_external_common
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+ 200:	f000 6c01 	li	a0,1
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+ 204:	f400 3480 	sll	a0,16
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+ 216:	f000 6c02 	li	a0,2
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+ 226:	f400 3480 	sll	a0,16
+ 22a:	f5b4 4c09 	addiu	a0,-23127
+			22a: R_MIPS16_LO16	\.data
+ 22e:	f000 6c02 	li	a0,2
+			22e: R_MIPS16_HI16	big_external_data_label
+ 232:	f400 3480 	sll	a0,16
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+			236: R_MIPS16_LO16	big_external_data_label
+ 23a:	f000 6c02 	li	a0,2
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+ 23e:	f400 3480 	sll	a0,16
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+			242: R_MIPS16_LO16	small_external_data_label
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+			24e: R_MIPS16_LO16	big_external_common
+ 252:	f000 6c02 	li	a0,2
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+ 256:	f400 3480 	sll	a0,16
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+			25a: R_MIPS16_LO16	small_external_common
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+ 262:	f400 3480 	sll	a0,16
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+ 28a:	f000 6d00 	li	a1,0
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+			29e: R_MIPS16_LO16	big_external_data_label
+ 2a2:	f000 6d00 	li	a1,0
+			2a2: R_MIPS16_HI16	small_external_data_label
+ 2a6:	f400 35a0 	sll	a1,16
+ 2aa:	f000 9d80 	lw	a0,0\(a1\)
+			2aa: R_MIPS16_LO16	small_external_data_label
+ 2ae:	f000 6d00 	li	a1,0
+			2ae: R_MIPS16_HI16	big_external_common
+ 2b2:	f400 35a0 	sll	a1,16
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+			2b6: R_MIPS16_LO16	big_external_common
+ 2ba:	f000 6d00 	li	a1,0
+			2ba: R_MIPS16_HI16	small_external_common
+ 2be:	f400 35a0 	sll	a1,16
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+			2c2: R_MIPS16_LO16	small_external_common
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+			2ce: R_MIPS16_LO16	\.bss
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+ 2da:	f000 9d80 	lw	a0,0\(a1\)
+			2da: R_MIPS16_LO16	\.sbss
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+			2f0: R_MIPS16_LO16	\.data
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+ 2f8:	f400 35a0 	sll	a1,16
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+			2fc: R_MIPS16_LO16	\.data
+ 300:	f000 6d00 	li	a1,0
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+ 304:	f400 35a0 	sll	a1,16
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+			308: R_MIPS16_LO16	big_external_data_label
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+ 310:	f400 35a0 	sll	a1,16
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+			314: R_MIPS16_LO16	small_external_data_label
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+			318: R_MIPS16_HI16	big_external_common
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+			320: R_MIPS16_LO16	big_external_common
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+			32c: R_MIPS16_LO16	small_external_common
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+			366: R_MIPS16_LO16	\.data
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+			372: R_MIPS16_LO16	big_external_data_label
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+ 37a:	f400 35a0 	sll	a1,16
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+			37e: R_MIPS16_LO16	small_external_data_label
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+ 386:	f400 35a0 	sll	a1,16
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+			38a: R_MIPS16_LO16	big_external_common
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+ 392:	f400 35a0 	sll	a1,16
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+			396: R_MIPS16_LO16	small_external_common
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+ 3a2:	f010 9d80 	lw	a0,-32768\(a1\)
+			3a2: R_MIPS16_LO16	\.bss
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+ 3aa:	f400 35a0 	sll	a1,16
+ 3ae:	f010 9d80 	lw	a0,-32768\(a1\)
+			3ae: R_MIPS16_LO16	\.sbss
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+			3c4: R_MIPS16_LO16	\.data
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+ 3cc:	f400 35a0 	sll	a1,16
+ 3d0:	f010 9d84 	lw	a0,-32764\(a1\)
+			3d0: R_MIPS16_LO16	\.data
+ 3d4:	f000 6d00 	li	a1,0
+			3d4: R_MIPS16_HI16	big_external_data_label
+ 3d8:	f400 35a0 	sll	a1,16
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+			3dc: R_MIPS16_LO16	big_external_data_label
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+			3e0: R_MIPS16_HI16	small_external_data_label
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+			3e8: R_MIPS16_LO16	small_external_data_label
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+			3f4: R_MIPS16_LO16	big_external_common
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+			400: R_MIPS16_LO16	small_external_common
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+ 438:	f000 9d84 	lw	a0,4\(a1\)
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+ 440:	f400 35a0 	sll	a1,16
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+			444: R_MIPS16_LO16	big_external_data_label
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+			450: R_MIPS16_LO16	small_external_data_label
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+			45c: R_MIPS16_LO16	big_external_common
+ 460:	f000 6d01 	li	a1,1
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+ 492:	f400 35a0 	sll	a1,16
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+ 4a2:	f5b4 9d89 	lw	a0,-23127\(a1\)
+			4a2: R_MIPS16_LO16	\.data
+ 4a6:	f000 6d02 	li	a1,2
+			4a6: R_MIPS16_HI16	big_external_data_label
+ 4aa:	f400 35a0 	sll	a1,16
+ 4ae:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ae: R_MIPS16_LO16	big_external_data_label
+ 4b2:	f000 6d02 	li	a1,2
+			4b2: R_MIPS16_HI16	small_external_data_label
+ 4b6:	f400 35a0 	sll	a1,16
+ 4ba:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ba: R_MIPS16_LO16	small_external_data_label
+ 4be:	f000 6d02 	li	a1,2
+			4be: R_MIPS16_HI16	big_external_common
+ 4c2:	f400 35a0 	sll	a1,16
+ 4c6:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4c6: R_MIPS16_LO16	big_external_common
+ 4ca:	f000 6d02 	li	a1,2
+			4ca: R_MIPS16_HI16	small_external_common
+ 4ce:	f400 35a0 	sll	a1,16
+ 4d2:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4d2: R_MIPS16_LO16	small_external_common
+ 4d6:	f000 6d02 	li	a1,2
+			4d6: R_MIPS16_HI16	\.bss
+ 4da:	f400 35a0 	sll	a1,16
+ 4de:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4de: R_MIPS16_LO16	\.bss
+ 4e2:	f000 6d02 	li	a1,2
+			4e2: R_MIPS16_HI16	\.sbss
+ 4e6:	f400 35a0 	sll	a1,16
+ 4ea:	f5b4 9d85 	lw	a0,-23131\(a1\)
+			4ea: R_MIPS16_LO16	\.sbss
+ 4ee:	6500      	nop
diff --git a/gas/testsuite/gas/mips/mips16-hilo.s b/gas/testsuite/gas/mips/mips16-hilo.s
new file mode 100644
index 000000000000..cc1e8a01f8ca
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16-hilo.s
@@ -0,0 +1,346 @@
+# Source file used to test li/addi on MIPS16
+	
+	.set	mips16
+	
+	.data
+data_label:
+	.word	0
+data_label2:
+	.word	0
+	
+	.extern big_external_data_label,1000
+	.extern small_external_data_label,1
+	.comm big_external_common,1000
+	.comm small_external_common,1
+	.lcomm big_local_common,1000
+	.lcomm small_local_common,1
+	
+	.text
+stuff:		
+	li	$4,%hi(0)
+	sll	$4,16
+	addiu	$4,%lo(0)
+	li	$4,%hi(data_label)
+	sll	$4,16
+	addiu	$4,%lo(data_label)
+	li	$4,%hi(data_label2)
+	sll	$4,16
+	addiu	$4,%lo(data_label2)
+	li	$4,%hi(big_external_data_label)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label)
+	li	$4,%hi(small_external_data_label)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label)
+	li	$4,%hi(big_external_common)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common)
+	li	$4,%hi(small_external_common)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common)
+	li	$4,%hi(big_local_common)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common)
+	li	$4,%hi(small_local_common)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common)
+	li	$4,%hi(1)
+	sll	$4,16
+	addiu	$4,%lo(1)
+	li	$4,%hi(data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(data_label+1)
+	li	$4,%hi(data_label2+1)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+1)
+	li	$4,%hi(big_external_data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+1)
+	li	$4,%hi(small_external_data_label+1)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+1)
+	li	$4,%hi(big_external_common+1)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+1)
+	li	$4,%hi(small_external_common+1)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+1)
+	li	$4,%hi(big_local_common+1)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+1)
+	li	$4,%hi(small_local_common+1)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+1)
+	li	$4,%hi(0x8000)
+	sll	$4,16
+	addiu	$4,%lo(0x8000)
+	li	$4,%hi(data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x8000)
+	li	$4,%hi(data_label2+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x8000)
+	li	$4,%hi(big_external_data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x8000)
+	li	$4,%hi(small_external_data_label+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x8000)
+	li	$4,%hi(big_external_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x8000)
+	li	$4,%hi(small_external_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x8000)
+	li	$4,%hi(big_local_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x8000)
+	li	$4,%hi(small_local_common+0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x8000)
+	li	$4,%hi(-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(-0x8000)
+	li	$4,%hi(data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label-0x8000)
+	li	$4,%hi(data_label2-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2-0x8000)
+	li	$4,%hi(big_external_data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label-0x8000)
+	li	$4,%hi(small_external_data_label-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label-0x8000)
+	li	$4,%hi(big_external_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common-0x8000)
+	li	$4,%hi(small_external_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common-0x8000)
+	li	$4,%hi(big_local_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common-0x8000)
+	li	$4,%hi(small_local_common-0x8000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common-0x8000)
+	li	$4,%hi(0x10000)
+	sll	$4,16
+	addiu	$4,%lo(0x10000)
+	li	$4,%hi(data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x10000)
+	li	$4,%hi(data_label2+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x10000)
+	li	$4,%hi(big_external_data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x10000)
+	li	$4,%hi(small_external_data_label+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x10000)
+	li	$4,%hi(big_external_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x10000)
+	li	$4,%hi(small_external_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x10000)
+	li	$4,%hi(big_local_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x10000)
+	li	$4,%hi(small_local_common+0x10000)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x10000)
+	li	$4,%hi(0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(0x1a5a5)
+	li	$4,%hi(data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(data_label+0x1a5a5)
+	li	$4,%hi(data_label2+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(data_label2+0x1a5a5)
+	li	$4,%hi(big_external_data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_external_data_label+0x1a5a5)
+	li	$4,%hi(small_external_data_label+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_external_data_label+0x1a5a5)
+	li	$4,%hi(big_external_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_external_common+0x1a5a5)
+	li	$4,%hi(small_external_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_external_common+0x1a5a5)
+	li	$4,%hi(big_local_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(big_local_common+0x1a5a5)
+	li	$4,%hi(small_local_common+0x1a5a5)
+	sll	$4,16
+	addiu	$4,%lo(small_local_common+0x1a5a5)
+	li	$5,%hi(0)
+	sll	$5,16
+	lw	$4,%hi(0)($5)
+	li	$5,%hi(data_label)
+	sll	$5,16
+	lw	$4,%hi(data_label)($5)
+	li	$5,%hi(data_label2)
+	sll	$5,16
+	lw	$4,%hi(data_label2)($5)
+	li	$5,%hi(big_external_data_label)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label)($5)
+	li	$5,%hi(small_external_data_label)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label)($5)
+	li	$5,%hi(big_external_common)
+	sll	$5,16
+	lw	$4,%lo(big_external_common)($5)
+	li	$5,%hi(small_external_common)
+	sll	$5,16
+	lw	$4,%lo(small_external_common)($5)
+	li	$5,%hi(big_local_common)
+	sll	$5,16
+	lw	$4,%lo(big_local_common)($5)
+	li	$5,%hi(small_local_common)
+	sll	$5,16
+	lw	$4,%lo(small_local_common)($5)
+	li	$5,%hi(1)
+	sll	$5,16
+	lw	$4,%lo(1)($5)
+	li	$5,%hi(data_label+1)
+	sll	$5,16
+	lw	$4,%lo(data_label+1)($5)
+	li	$5,%hi(data_label2+1)
+	sll	$5,16
+	lw	$4,%lo(data_label2+1)($5)
+	li	$5,%hi(big_external_data_label+1)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+1)($5)
+	li	$5,%hi(small_external_data_label+1)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+1)($5)
+	li	$5,%hi(big_external_common+1)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+1)($5)
+	li	$5,%hi(small_external_common+1)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+1)($5)
+	li	$5,%hi(big_local_common+1)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+1)($5)
+	li	$5,%hi(small_local_common+1)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+1)($5)
+	li	$5,%hi(0x8000)
+	sll	$5,16
+	lw	$4,%lo(0x8000)($5)
+	li	$5,%hi(data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x8000)($5)
+	li	$5,%hi(data_label2+0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x8000)($5)
+	li	$5,%hi(big_external_data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x8000)($5)
+	li	$5,%hi(small_external_data_label+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x8000)($5)
+	li	$5,%hi(big_external_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x8000)($5)
+	li	$5,%hi(small_external_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x8000)($5)
+	li	$5,%hi(big_local_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x8000)($5)
+	li	$5,%hi(small_local_common+0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x8000)($5)
+	li	$5,%hi(-0x8000)
+	sll	$5,16
+	lw	$4,%lo(-0x8000)($5)
+	li	$5,%hi(data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label-0x8000)($5)
+	li	$5,%hi(data_label2-0x8000)
+	sll	$5,16
+	lw	$4,%lo(data_label2-0x8000)($5)
+	li	$5,%hi(big_external_data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label-0x8000)($5)
+	li	$5,%hi(small_external_data_label-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label-0x8000)($5)
+	li	$5,%hi(big_external_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common-0x8000)($5)
+	li	$5,%hi(small_external_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common-0x8000)($5)
+	li	$5,%hi(big_local_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common-0x8000)($5)
+	li	$5,%hi(small_local_common-0x8000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common-0x8000)($5)
+	li	$5,%hi(0x10000)
+	sll	$5,16
+	lw	$4,%lo(0x10000)($5)
+	li	$5,%hi(data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x10000)($5)
+	li	$5,%hi(data_label2+0x10000)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x10000)($5)
+	li	$5,%hi(big_external_data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x10000)($5)
+	li	$5,%hi(small_external_data_label+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x10000)($5)
+	li	$5,%hi(big_external_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x10000)($5)
+	li	$5,%hi(small_external_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x10000)($5)
+	li	$5,%hi(big_local_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x10000)($5)
+	li	$5,%hi(small_local_common+0x10000)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x10000)($5)
+	li	$5,%hi(0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(0x1a5a5)($5)
+	li	$5,%hi(data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(data_label+0x1a5a5)($5)
+	li	$5,%hi(data_label2+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(data_label2+0x1a5a5)($5)
+	li	$5,%hi(big_external_data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_external_data_label+0x1a5a5)($5)
+	li	$5,%hi(small_external_data_label+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_external_data_label+0x1a5a5)($5)
+	li	$5,%hi(big_external_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_external_common+0x1a5a5)($5)
+	li	$5,%hi(small_external_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_external_common+0x1a5a5)($5)
+	li	$5,%hi(big_local_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(big_local_common+0x1a5a5)($5)
+	li	$5,%hi(small_local_common+0x1a5a5)
+	sll	$5,16
+	lw	$4,%lo(small_local_common+0x1a5a5)($5)
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+	.p2align 4
diff --git a/gas/testsuite/gas/mips/mips16e-jrc.d b/gas/testsuite/gas/mips/mips16e-jrc.d
new file mode 100644
index 000000000000..a323b31359bf
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-jrc.d
@@ -0,0 +1,16 @@
+#objdump: -dr -mmips:isa32 -mmips:16
+#as: -march=mips32 -mips16 -32
+#name: mips16e jalrc/jrc
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <.text>:
+   0:[ 	]+eac0[ 	]+jalrc[ 	]+v0
+   2:[ 	]+e8a0[ 	]+jrc[ 	]+ra
+   4:[ 	]+6a01[ 	]+li[ 	]+v0,1
+   6:[ 	]+6500[ 	]+nop
+   8:[ 	]+6500[ 	]+nop
+   a:[ 	]+6500[ 	]+nop
+   c:[ 	]+6500[ 	]+nop
+   e:[ 	]+6500[ 	]+nop
diff --git a/gas/testsuite/gas/mips/mips16e-jrc.s b/gas/testsuite/gas/mips/mips16e-jrc.s
new file mode 100644
index 000000000000..02c83892fee3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-jrc.s
@@ -0,0 +1,6 @@
+# Test the generation of jalrc/jrc opcodes
+        jalr    $31,$2
+        jr      $31
+	li	$2,1
+
+        .p2align 4
diff --git a/gas/testsuite/gas/mips/mips16e-save.d b/gas/testsuite/gas/mips/mips16e-save.d
new file mode 100644
index 000000000000..6e18d8c32060
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-save.d
@@ -0,0 +1,43 @@
+#objdump: -dr -mmips:isa32 -mmips:16
+#as: -march=mips32 -mips16 -32
+#name: mips16e save/restore
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+00000000 <func>:
+   0:[ 	]+6481[ 	]+save[ 	]+8
+   2:[ 	]+64c2[ 	]+save[ 	]+16,ra
+   4:[ 	]+64a3[ 	]+save[ 	]+24,s0
+   6:[ 	]+6494[ 	]+save[ 	]+32,s1
+   8:[ 	]+64b5[ 	]+save[ 	]+40,s0-s1
+   a:[ 	]+64e6[ 	]+save[ 	]+48,ra,s0
+   c:[ 	]+64d7[ 	]+save[ 	]+56,ra,s1
+   e:[ 	]+64f8[ 	]+save[ 	]+64,ra,s0-s1
+  10:[ 	]+64f9[ 	]+save[ 	]+72,ra,s0-s1
+  12:[ 	]+64fa[ 	]+save[ 	]+80,ra,s0-s1
+  14:[ 	]+64fb[ 	]+save[ 	]+88,ra,s0-s1
+  16:[ 	]+64f0[ 	]+save[ 	]+128,ra,s0-s1
+  18:[ 	]+f010 6481[ 	]+save[ 	]+136
+  1c:[ 	]+f010 64c2[ 	]+save[ 	]+144,ra
+  20:[ 	]+f010 64b3[ 	]+save[ 	]+152,s0-s1
+  24:[ 	]+f100 6488[ 	]+save[ 	]+64,s2
+  28:[ 	]+f600 6489[ 	]+save[ 	]+72,s2-s7
+  2c:[ 	]+f700 648a[ 	]+save[ 	]+80,s2-s8
+  30:[ 	]+f700 64bb[ 	]+save[ 	]+88,s0-s8
+  34:[ 	]+f001 6488[ 	]+save[ 	]+64,a3
+  38:[ 	]+f012 6480[ 	]+save[ 	]+128,a2-a3
+  3c:[ 	]+f02b 6480[ 	]+save[ 	]+256,a0-a3
+  40:[ 	]+f024 6480[ 	]+save[ 	]+a0,256
+  44:[ 	]+f018 6480[ 	]+save[ 	]+a0-a1,128
+  48:[ 	]+f00e 6488[ 	]+save[ 	]+a0-a3,64
+  4c:[ 	]+f015 6480[ 	]+save[ 	]+a0,128,a3
+  50:[ 	]+f017 6480[ 	]+save[ 	]+a0,128,a1-a3
+  54:[ 	]+f01a 6480[ 	]+save[ 	]+a0-a1,128,a2-a3
+  58:[ 	]+f01d 6480[ 	]+save[ 	]+a0-a2,128,a3
+  5c:[ 	]+f71a 64f0[ 	]+save[ 	]+a0-a1,128,ra,s0-s8,a2-a3
+  60:[ 	]+6470[ 	]+restore[ 	]+128,ra,s0-s1
+  62:[ 	]+f010 6441[ 	]+restore[ 	]+136,ra
+  66:[ 	]+f100 6408[ 	]+restore[ 	]+64,s2
+  6a:[ 	]+f71b 6470[ 	]+restore[ 	]+128,ra,s0-s8,a0-a3
+  6e:[ 	]+6500[ 	]+nop
diff --git a/gas/testsuite/gas/mips/mips16e-save.s b/gas/testsuite/gas/mips/mips16e-save.s
new file mode 100644
index 000000000000..b982cc7afbf7
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips16e-save.s
@@ -0,0 +1,55 @@
+# Test the generation of the mips16e save instruction
+
+	.set	mips16
+	.text
+func:
+# Un-extended version
+	save	8
+	save    $31,16
+	save	$16,24
+	save	$17,32
+	save	$16-$17,40
+	save    $31,$16,48
+	save    $31,$17,56
+	save    $31,$16,$17,64
+	save    $31,$16-$17,72
+	save    80,$31,$16-$17
+	save    $31,88,$16,$17
+	save    $31,$17,128,$16
+
+# Extended version
+	save	136
+	save    $31,144
+	save	$16-$17,152
+
+	# sreg
+	save	$18,64
+	save	$18-$23,72
+	save	$18-$23,$30,80
+	save	$16-$23,$30,88
+	
+	# static areg
+	save    64,$7
+	save    128,$7,$6
+	save    256,$7,$6,$5,$4
+
+	# areg
+	save    $4,256
+	save    $4,$5,128
+	save    $4,$5,$6,$7,64
+
+	# mix areg and static areg
+	save    $4,128,$7
+	save    $4,128,$7,$6,$5
+	save    $4,$5,128,$7,$6
+	save    $4,$5,$6,128,$7
+
+	save	$4-$5,$16-$23,$30-$31,128,$6-$7
+
+	restore	$16,$17,$31,128
+	restore	$31,136
+	restore	$18,64
+	restore	$4-$5,$16-$23,$30-$31,128,$6-$7
+	
+        .p2align 4
+
diff --git a/gas/testsuite/gas/mips/mips32-dsp.d b/gas/testsuite/gas/mips/mips32-dsp.d
new file mode 100644
index 000000000000..486f630ac942
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dsp.d
@@ -0,0 +1,178 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE for MIPS32
+#as: -mdsp -32
+#stderr: mips32-dsp.l
+
+# Check MIPS DSP ASE for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c220290 	addq\.ph	zero,at,v0
+0+0004 <[^>]*> 7c430b90 	addq_s\.ph	at,v0,v1
+0+0008 <[^>]*> 7c641590 	addq_s\.w	v0,v1,a0
+0+000c <[^>]*> 7c851810 	addu\.qb	v1,a0,a1
+0+0010 <[^>]*> 7ca62110 	addu_s\.qb	a0,a1,a2
+0+0014 <[^>]*> 7cc72ad0 	subq\.ph	a1,a2,a3
+0+0018 <[^>]*> 7ce833d0 	subq_s\.ph	a2,a3,t0
+0+001c <[^>]*> 7d093dd0 	subq_s\.w	a3,t0,t1
+0+0020 <[^>]*> 7d2a4050 	subu\.qb	t0,t1,t2
+0+0024 <[^>]*> 7d4b4950 	subu_s\.qb	t1,t2,t3
+0+0028 <[^>]*> 7d6c5410 	addsc	t2,t3,t4
+0+002c <[^>]*> 7d8d5c50 	addwc	t3,t4,t5
+0+0030 <[^>]*> 7dae6490 	modsub	t4,t5,t6
+0+0034 <[^>]*> 7dc06d10 	raddu\.w\.qb	t5,t6
+0+0038 <[^>]*> 7c0f7252 	absq_s\.ph	t6,t7
+0+003c <[^>]*> 7c107c52 	absq_s\.w	t7,s0
+0+0040 <[^>]*> 7e328311 	precrq\.qb\.ph	s0,s1,s2
+0+0044 <[^>]*> 7e538d11 	precrq\.ph\.w	s1,s2,s3
+0+0048 <[^>]*> 7e749551 	precrq_rs\.ph\.w	s2,s3,s4
+0+004c <[^>]*> 7e959bd1 	precrqu_s\.qb\.ph	s3,s4,s5
+0+0050 <[^>]*> 7c15a312 	preceq\.w\.phl	s4,s5
+0+0054 <[^>]*> 7c16ab52 	preceq\.w\.phr	s5,s6
+0+0058 <[^>]*> 7c17b112 	precequ\.ph\.qbl	s6,s7
+0+005c <[^>]*> 7c18b952 	precequ\.ph\.qbr	s7,t8
+0+0060 <[^>]*> 7c19c192 	precequ\.ph\.qbla	t8,t9
+0+0064 <[^>]*> 7c1ac9d2 	precequ\.ph\.qbra	t9,k0
+0+0068 <[^>]*> 7c1bd712 	preceu\.ph\.qbl	k0,k1
+0+006c <[^>]*> 7c1cdf52 	preceu\.ph\.qbr	k1,gp
+0+0070 <[^>]*> 7c1de792 	preceu\.ph\.qbla	gp,sp
+0+0074 <[^>]*> 7c1eefd2 	preceu\.ph\.qbra	sp,s8
+0+0078 <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
+0+007c <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
+0+0080 <[^>]*> 7cfff013 	shll\.qb	s8,ra,0x7
+0+0084 <[^>]*> 7c1ff013 	shll\.qb	s8,ra,0x0
+0+0088 <[^>]*> 7c20f893 	shllv\.qb	ra,zero,at
+0+008c <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
+0+0090 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
+0+0094 <[^>]*> 7de10213 	shll\.ph	zero,at,0xf
+0+0098 <[^>]*> 7c010213 	shll\.ph	zero,at,0x0
+0+009c <[^>]*> 7c620a93 	shllv\.ph	at,v0,v1
+0+00a0 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
+0+00a4 <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
+0+00a8 <[^>]*> 7de31313 	shll_s\.ph	v0,v1,0xf
+0+00ac <[^>]*> 7c031313 	shll_s\.ph	v0,v1,0x0
+0+00b0 <[^>]*> 7ca41b93 	shllv_s\.ph	v1,a0,a1
+0+00b4 <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
+0+00b8 <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
+0+00bc <[^>]*> 7fe52513 	shll_s\.w	a0,a1,0x1f
+0+00c0 <[^>]*> 7c052513 	shll_s\.w	a0,a1,0x0
+0+00c4 <[^>]*> 7ce62d93 	shllv_s\.w	a1,a2,a3
+0+00c8 <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
+0+00cc <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
+0+00d0 <[^>]*> 7ce73053 	shrl\.qb	a2,a3,0x7
+0+00d4 <[^>]*> 7c073053 	shrl\.qb	a2,a3,0x0
+0+00d8 <[^>]*> 7d2838d3 	shrlv\.qb	a3,t0,t1
+0+00dc <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
+0+00e0 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
+0+00e4 <[^>]*> 7de94253 	shra\.ph	t0,t1,0xf
+0+00e8 <[^>]*> 7c094253 	shra\.ph	t0,t1,0x0
+0+00ec <[^>]*> 7d6a4ad3 	shrav\.ph	t1,t2,t3
+0+00f0 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
+0+00f4 <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
+0+00f8 <[^>]*> 7deb5353 	shra_r\.ph	t2,t3,0xf
+0+00fc <[^>]*> 7c0b5353 	shra_r\.ph	t2,t3,0x0
+0+0100 <[^>]*> 7dac5bd3 	shrav_r\.ph	t3,t4,t5
+0+0104 <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
+0+0108 <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
+0+010c <[^>]*> 7fed6553 	shra_r\.w	t4,t5,0x1f
+0+0110 <[^>]*> 7c0d6553 	shra_r\.w	t4,t5,0x0
+0+0114 <[^>]*> 7dee6dd3 	shrav_r\.w	t5,t6,t7
+0+0118 <[^>]*> 7df07190 	muleu_s\.ph\.qbl	t6,t7,s0
+0+011c <[^>]*> 7e1179d0 	muleu_s\.ph\.qbr	t7,s0,s1
+0+0120 <[^>]*> 7e3287d0 	mulq_rs\.ph	s0,s1,s2
+0+0124 <[^>]*> 7e538f10 	muleq_s\.w\.phl	s1,s2,s3
+0+0128 <[^>]*> 7e749750 	muleq_s\.w\.phr	s2,s3,s4
+0+012c <[^>]*> 7e7400f0 	dpau\.h\.qbl	\$ac0,s3,s4
+0+0130 <[^>]*> 7e9509f0 	dpau\.h\.qbr	\$ac1,s4,s5
+0+0134 <[^>]*> 7eb612f0 	dpsu\.h\.qbl	\$ac2,s5,s6
+0+0138 <[^>]*> 7ed71bf0 	dpsu\.h\.qbr	\$ac3,s6,s7
+0+013c <[^>]*> 7ef80130 	dpaq_s\.w\.ph	\$ac0,s7,t8
+0+0140 <[^>]*> 7f190970 	dpsq_s\.w\.ph	\$ac1,t8,t9
+0+0144 <[^>]*> 7f3a11b0 	mulsaq_s\.w\.ph	\$ac2,t9,k0
+0+0148 <[^>]*> 7f5b1b30 	dpaq_sa\.l\.w	\$ac3,k0,k1
+0+014c <[^>]*> 7f7c0370 	dpsq_sa\.l\.w	\$ac0,k1,gp
+0+0150 <[^>]*> 7f9d0d30 	maq_s\.w\.phl	\$ac1,gp,sp
+0+0154 <[^>]*> 7fbe15b0 	maq_s\.w\.phr	\$ac2,sp,s8
+0+0158 <[^>]*> 7fdf1c30 	maq_sa\.w\.phl	\$ac3,s8,ra
+0+015c <[^>]*> 7fe004b0 	maq_sa\.w\.phr	\$ac0,ra,zero
+0+0160 <[^>]*> 7c0106d2 	bitrev	zero,at
+0+0164 <[^>]*> 7c41000c 	insv	at,v0
+0+0168 <[^>]*> 7cff1092 	repl\.qb	v0,0xff
+0+016c <[^>]*> 7c001092 	repl\.qb	v0,0x0
+0+0170 <[^>]*> 7cff1092 	repl\.qb	v0,0xff
+0+0174 <[^>]*> 7c001092 	repl\.qb	v0,0x0
+0+0178 <[^>]*> 7c0418d2 	replv\.qb	v1,a0
+0+017c <[^>]*> 7dff2292 	repl\.ph	a0,511
+0+0180 <[^>]*> 7e002292 	repl\.ph	a0,-512
+0+0184 <[^>]*> 7dff2292 	repl\.ph	a0,511
+0+0188 <[^>]*> 7e002292 	repl\.ph	a0,-512
+0+018c <[^>]*> 7c062ad2 	replv\.ph	a1,a2
+0+0190 <[^>]*> 7cc70011 	cmpu\.eq\.qb	a2,a3
+0+0194 <[^>]*> 7ce80051 	cmpu\.lt\.qb	a3,t0
+0+0198 <[^>]*> 7d090091 	cmpu\.le\.qb	t0,t1
+0+019c <[^>]*> 7d4b4911 	cmpgu\.eq\.qb	t1,t2,t3
+0+01a0 <[^>]*> 7d6c5151 	cmpgu\.lt\.qb	t2,t3,t4
+0+01a4 <[^>]*> 7d8d5991 	cmpgu\.le\.qb	t3,t4,t5
+0+01a8 <[^>]*> 7d8d0211 	cmp\.eq\.ph	t4,t5
+0+01ac <[^>]*> 7dae0251 	cmp\.lt\.ph	t5,t6
+0+01b0 <[^>]*> 7dcf0291 	cmp\.le\.ph	t6,t7
+0+01b4 <[^>]*> 7e1178d1 	pick\.qb	t7,s0,s1
+0+01b8 <[^>]*> 7e3282d1 	pick\.ph	s0,s1,s2
+0+01bc <[^>]*> 7e538b91 	packrl\.ph	s1,s2,s3
+0+01c0 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
+0+01c4 <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
+0+01c8 <[^>]*> 7ff20838 	extr\.w	s2,\$ac1,0x1f
+0+01cc <[^>]*> 7c120838 	extr\.w	s2,\$ac1,0x0
+0+01d0 <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
+0+01d4 <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
+0+01d8 <[^>]*> 7ff31138 	extr_r\.w	s3,\$ac2,0x1f
+0+01dc <[^>]*> 7c131138 	extr_r\.w	s3,\$ac2,0x0
+0+01e0 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
+0+01e4 <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
+0+01e8 <[^>]*> 7ff419b8 	extr_rs\.w	s4,\$ac3,0x1f
+0+01ec <[^>]*> 7c1419b8 	extr_rs\.w	s4,\$ac3,0x0
+0+01f0 <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
+0+01f4 <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
+0+01f8 <[^>]*> 7ff503b8 	extr_s\.h	s5,\$ac0,0x1f
+0+01fc <[^>]*> 7c1503b8 	extr_s\.h	s5,\$ac0,0x0
+0+0200 <[^>]*> 7ef60bf8 	extrv_s\.h	s6,\$ac1,s7
+0+0204 <[^>]*> 7f171078 	extrv\.w	s7,\$ac2,t8
+0+0208 <[^>]*> 7f381978 	extrv_r\.w	t8,\$ac3,t9
+0+020c <[^>]*> 7f5901f8 	extrv_rs\.w	t9,\$ac0,k0
+0+0210 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
+0+0214 <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
+0+0218 <[^>]*> 7ffa08b8 	extp	k0,\$ac1,0x1f
+0+021c <[^>]*> 7c1a08b8 	extp	k0,\$ac1,0x0
+0+0220 <[^>]*> 7f9b10f8 	extpv	k1,\$ac2,gp
+0+0224 <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
+0+0228 <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
+0+022c <[^>]*> 7ffc1ab8 	extpdp	gp,\$ac3,0x1f
+0+0230 <[^>]*> 7c1c1ab8 	extpdp	gp,\$ac3,0x0
+0+0234 <[^>]*> 7fdd02f8 	extpdpv	sp,\$ac0,s8
+0+0238 <[^>]*> 7df00eb8 	shilo	\$ac1,31
+0+023c <[^>]*> 7e000eb8 	shilo	\$ac1,-32
+0+0240 <[^>]*> 7df00eb8 	shilo	\$ac1,31
+0+0244 <[^>]*> 7e000eb8 	shilo	\$ac1,-32
+0+0248 <[^>]*> 7fc016f8 	shilov	\$ac2,s8
+0+024c <[^>]*> 7fe01ff8 	mthlip	ra,\$ac3
+0+0250 <[^>]*> 00000010 	mfhi	zero
+0+0254 <[^>]*> 00200812 	mflo	at,\$ac1
+0+0258 <[^>]*> 00401011 	mthi	v0,\$ac2
+0+025c <[^>]*> 00601813 	mtlo	v1,\$ac3
+0+0260 <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
+0+0264 <[^>]*> 7c8004f8 	wrdsp	a0,0x0
+0+0268 <[^>]*> 7c81fcf8 	wrdsp	a0,0x3f
+0+026c <[^>]*> 7c8004f8 	wrdsp	a0,0x0
+0+0270 <[^>]*> 7cbffcf8 	wrdsp	a1
+0+0274 <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
+0+0278 <[^>]*> 7c0034b8 	rddsp	a2,0x0
+0+027c <[^>]*> 7c3f34b8 	rddsp	a2,0x3f
+0+0280 <[^>]*> 7c0034b8 	rddsp	a2,0x0
+0+0284 <[^>]*> 7fff3cb8 	rddsp	a3
+0+0288 <[^>]*> 7d49418a 	lbux	t0,t1\(t2\)
+0+028c <[^>]*> 7d6a490a 	lhx	t1,t2\(t3\)
+0+0290 <[^>]*> 7d8b500a 	lwx	t2,t3\(t4\)
+0+0294 <[^>]*> 041cff5a 	bposge32	0+0000 <text_label>
+0+0298 <[^>]*> 00000000 	nop
+	...
diff --git a/gas/testsuite/gas/mips/mips32-dsp.l b/gas/testsuite/gas/mips/mips32-dsp.l
new file mode 100644
index 000000000000..c7d3e7a14cfe
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dsp.l
@@ -0,0 +1,39 @@
+.*: Assembler messages:
+.*:39: Warning: DSP immediate not in range 0..7 \([0-9]*\)
+.*:42: Warning: DSP immediate not in range 0..7 \(8\)
+.*:44: Warning: DSP immediate not in range 0..15 \([0-9]*\)
+.*:47: Warning: DSP immediate not in range 0..15 \(16\)
+.*:49: Warning: DSP immediate not in range 0..15 \([0-9]*\)
+.*:52: Warning: DSP immediate not in range 0..15 \(16\)
+.*:54: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:57: Warning: DSP immediate not in range 0..31 \(32\)
+.*:59: Warning: DSP immediate not in range 0..7 \([0-9]*\)
+.*:62: Warning: DSP immediate not in range 0..7 \(8\)
+.*:64: Warning: DSP immediate not in range 0..15 \([0-9]*\)
+.*:67: Warning: DSP immediate not in range 0..15 \(16\)
+.*:69: Warning: DSP immediate not in range 0..15 \([0-9]*\)
+.*:72: Warning: DSP immediate not in range 0..15 \(16\)
+.*:74: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:77: Warning: DSP immediate not in range 0..31 \(32\)
+.*:99: Warning: DSP immediate not in range 0..255 \([0-9]*\)
+.*:102: Warning: DSP immediate not in range 0..255 \(256\)
+.*:104: Warning: DSP immediate not in range -512..511 \(-513\)
+.*:107: Warning: DSP immediate not in range -512..511 \(512\)
+.*:121: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:124: Warning: DSP immediate not in range 0..31 \(32\)
+.*:125: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:128: Warning: DSP immediate not in range 0..31 \(32\)
+.*:129: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:132: Warning: DSP immediate not in range 0..31 \(32\)
+.*:133: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:136: Warning: DSP immediate not in range 0..31 \(32\)
+.*:141: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:144: Warning: DSP immediate not in range 0..31 \(32\)
+.*:146: Warning: DSP immediate not in range 0..31 \([0-9]*\)
+.*:149: Warning: DSP immediate not in range 0..31 \(32\)
+.*:151: Warning: DSP immediate not in range -32..31 \(-33\)
+.*:154: Warning: DSP immediate not in range -32..31 \(32\)
+.*:161: Warning: DSP immediate not in range 0..63 \([0-9]*\)
+.*:164: Warning: DSP immediate not in range 0..63 \(64\)
+.*:166: Warning: DSP immediate not in range 0..63 \([0-9]*\)
+.*:169: Warning: DSP immediate not in range 0..63 \(64\)
diff --git a/gas/testsuite/gas/mips/mips32-dsp.s b/gas/testsuite/gas/mips/mips32-dsp.s
new file mode 100644
index 000000000000..aa818ce85138
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dsp.s
@@ -0,0 +1,178 @@
+# source file to test assembly of MIPS DSP ASE for MIPS32 instructions
+
+	.set noreorder
+	.set noat
+
+	.text
+text_label:
+
+	addq.ph		$0,$1,$2
+	addq_s.ph	$1,$2,$3
+	addq_s.w	$2,$3,$4
+	addu.qb		$3,$4,$5
+	addu_s.qb	$4,$5,$6
+	subq.ph		$5,$6,$7
+	subq_s.ph	$6,$7,$8
+	subq_s.w	$7,$8,$9
+	subu.qb		$8,$9,$10
+	subu_s.qb	$9,$10,$11
+	addsc		$10,$11,$12
+	addwc		$11,$12,$13
+	modsub		$12,$13,$14
+	raddu.w.qb	$13,$14
+	absq_s.ph	$14,$15
+	absq_s.w	$15,$16
+	precrq.qb.ph	$16,$17,$18
+	precrq.ph.w	$17,$18,$19
+	precrq_rs.ph.w	$18,$19,$20
+	precrqu_s.qb.ph	$19,$20,$21
+	preceq.w.phl	$20,$21
+	preceq.w.phr	$21,$22
+	precequ.ph.qbl	$22,$23
+	precequ.ph.qbr	$23,$24
+	precequ.ph.qbla	$24,$25
+	precequ.ph.qbra	$25,$26
+	preceu.ph.qbl	$26,$27
+	preceu.ph.qbr	$27,$28
+	preceu.ph.qbla	$28,$29
+	preceu.ph.qbra	$29,$30
+	shll.qb		$30,$31,-1
+	shll.qb		$30,$31,0
+	shll.qb		$30,$31,7
+	shll.qb		$30,$31,8
+	shllv.qb	$31,$0,$1
+	shll.ph		$0,$1,-1
+	shll.ph		$0,$1,0
+	shll.ph		$0,$1,15
+	shll.ph		$0,$1,16
+	shllv.ph	$1,$2,$3
+	shll_s.ph	$2,$3,-1
+	shll_s.ph	$2,$3,0
+	shll_s.ph	$2,$3,15
+	shll_s.ph	$2,$3,16
+	shllv_s.ph	$3,$4,$5
+	shll_s.w	$4,$5,-1
+	shll_s.w	$4,$5,0
+	shll_s.w	$4,$5,31
+	shll_s.w	$4,$5,32
+	shllv_s.w	$5,$6,$7
+	shrl.qb		$6,$7,-1
+	shrl.qb		$6,$7,0
+	shrl.qb		$6,$7,7
+	shrl.qb		$6,$7,8
+	shrlv.qb	$7,$8,$9
+	shra.ph		$8,$9,-1
+	shra.ph		$8,$9,0
+	shra.ph		$8,$9,15
+	shra.ph		$8,$9,16
+	shrav.ph	$9,$10,$11
+	shra_r.ph	$10,$11,-1
+	shra_r.ph	$10,$11,0
+	shra_r.ph	$10,$11,15
+	shra_r.ph	$10,$11,16
+	shrav_r.ph	$11,$12,$13
+	shra_r.w	$12,$13,-1
+	shra_r.w	$12,$13,0
+	shra_r.w	$12,$13,31
+	shra_r.w	$12,$13,32
+	shrav_r.w	$13,$14,$15
+	muleu_s.ph.qbl	$14,$15,$16
+	muleu_s.ph.qbr	$15,$16,$17
+	mulq_rs.ph	$16,$17,$18
+	muleq_s.w.phl	$17,$18,$19
+	muleq_s.w.phr	$18,$19,$20
+	dpau.h.qbl	$ac0,$19,$20
+	dpau.h.qbr	$ac1,$20,$21
+	dpsu.h.qbl	$ac2,$21,$22
+	dpsu.h.qbr	$ac3,$22,$23
+	dpaq_s.w.ph	$ac0,$23,$24
+	dpsq_s.w.ph	$ac1,$24,$25
+	mulsaq_s.w.ph	$ac2,$25,$26
+	dpaq_sa.l.w	$ac3,$26,$27
+	dpsq_sa.l.w	$ac0,$27,$28
+	maq_s.w.phl	$ac1,$28,$29
+	maq_s.w.phr	$ac2,$29,$30
+	maq_sa.w.phl	$ac3,$30,$31
+	maq_sa.w.phr	$ac0,$31,$0
+	bitrev		$0,$1
+	insv		$1,$2
+	repl.qb		$2,-1
+	repl.qb		$2,0
+	repl.qb		$2,255
+	repl.qb		$2,256
+	replv.qb	$3,$4
+	repl.ph		$4,-513
+	repl.ph		$4,-512
+	repl.ph		$4,511
+	repl.ph		$4,512
+	replv.ph	$5,$6
+	cmpu.eq.qb	$6,$7
+	cmpu.lt.qb	$7,$8
+	cmpu.le.qb	$8,$9
+	cmpgu.eq.qb	$9,$10,$11
+	cmpgu.lt.qb	$10,$11,$12
+	cmpgu.le.qb	$11,$12,$13
+	cmp.eq.ph	$12,$13
+	cmp.lt.ph	$13,$14
+	cmp.le.ph	$14,$15
+	pick.qb		$15,$16,$17
+	pick.ph		$16,$17,$18
+	packrl.ph	$17,$18,$19
+	extr.w		$18,$ac1,-1
+	extr.w		$18,$ac1,0
+	extr.w		$18,$ac1,31
+	extr.w		$18,$ac1,32
+	extr_r.w	$19,$ac2,-1
+	extr_r.w	$19,$ac2,0
+	extr_r.w	$19,$ac2,31
+	extr_r.w	$19,$ac2,32
+	extr_rs.w	$20,$ac3,-1
+	extr_rs.w	$20,$ac3,0
+	extr_rs.w	$20,$ac3,31
+	extr_rs.w	$20,$ac3,32
+	extr_s.h	$21,$ac0,-1
+	extr_s.h	$21,$ac0,0
+	extr_s.h	$21,$ac0,31
+	extr_s.h	$21,$ac0,32
+	extrv_s.h	$22,$ac1,$23
+	extrv.w		$23,$ac2,$24
+	extrv_r.w	$24,$ac3,$25
+	extrv_rs.w	$25,$ac0,$26
+	extp		$26,$ac1,-1
+	extp		$26,$ac1,0
+	extp		$26,$ac1,31
+	extp		$26,$ac1,32
+	extpv		$27,$ac2,$28
+	extpdp		$28,$ac3,-1
+	extpdp		$28,$ac3,0
+	extpdp		$28,$ac3,31
+	extpdp		$28,$ac3,32
+	extpdpv		$29,$ac0,$30
+	shilo		$ac1,-33
+	shilo		$ac1,-32
+	shilo		$ac1,31
+	shilo		$ac1,32
+	shilov		$ac2,$30
+	mthlip		$31,$ac3
+	mfhi		$0,$ac0
+	mflo		$1,$ac1
+	mthi		$2,$ac2
+	mtlo		$3,$ac3
+	wrdsp		$4,-1
+	wrdsp		$4,0
+	wrdsp		$4,63
+	wrdsp		$4,64
+	wrdsp		$5
+	rddsp		$6,-1
+	rddsp		$6,0
+	rddsp		$6,63
+	rddsp		$6,64
+	rddsp		$7
+	lbux		$8,$9($10)
+	lhx		$9,$10($11)
+	lwx		$10,$11($12)
+	bposge32	text_label
+	nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8
diff --git a/gas/testsuite/gas/mips/mips32-mt.d b/gas/testsuite/gas/mips/mips32-mt.d
new file mode 100644
index 000000000000..ffb3e975362e
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-mt.d
@@ -0,0 +1,826 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32
+#name: MIPS MT ASE for MIPS32
+#as: -mmt -32
+#stderr: mips32-mt.l
+
+# Check MIPS MT ASE for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 41600bc1 	dmt
+0+0004 <[^>]*> 417f0bc1 	dmt	ra
+0+0008 <[^>]*> 41600001 	dvpe
+0+000c <[^>]*> 41610001 	dvpe	at
+0+0010 <[^>]*> 41600be1 	emt
+0+0014 <[^>]*> 41620be1 	emt	v0
+0+0018 <[^>]*> 41600021 	evpe
+0+001c <[^>]*> 41630021 	evpe	v1
+0+0020 <[^>]*> 7ca62008 	fork	a0,a1,a2
+0+0024 <[^>]*> 7ca00009 	yield	a1
+0+0028 <[^>]*> 7ce03009 	yield	a2,a3
+0+002c <[^>]*> 41083800 	mftc0	a3,c0_badvaddr
+0+0030 <[^>]*> 41004000 	mftc0	t0,c0_index
+0+0034 <[^>]*> 41004001 	mftc0	t0,\$0,1
+0+0038 <[^>]*> 41004002 	mftc0	t0,\$0,2
+0+003c <[^>]*> 41004003 	mftc0	t0,\$0,3
+0+0040 <[^>]*> 41004004 	mftc0	t0,\$0,4
+0+0044 <[^>]*> 41004005 	mftc0	t0,\$0,5
+0+0048 <[^>]*> 41004006 	mftc0	t0,\$0,6
+0+004c <[^>]*> 41004007 	mftc0	t0,\$0,7
+0+0050 <[^>]*> 41014000 	mftc0	t0,c0_random
+0+0054 <[^>]*> 41014001 	mftc0	t0,\$1,1
+0+0058 <[^>]*> 41014002 	mftc0	t0,\$1,2
+0+005c <[^>]*> 41014003 	mftc0	t0,\$1,3
+0+0060 <[^>]*> 41014004 	mftc0	t0,\$1,4
+0+0064 <[^>]*> 41014005 	mftc0	t0,\$1,5
+0+0068 <[^>]*> 41014006 	mftc0	t0,\$1,6
+0+006c <[^>]*> 41014007 	mftc0	t0,\$1,7
+0+0070 <[^>]*> 41024000 	mftc0	t0,c0_entrylo0
+0+0074 <[^>]*> 41024001 	mftc0	t0,\$2,1
+0+0078 <[^>]*> 41024002 	mftc0	t0,\$2,2
+0+007c <[^>]*> 41024003 	mftc0	t0,\$2,3
+0+0080 <[^>]*> 41024004 	mftc0	t0,\$2,4
+0+0084 <[^>]*> 41024005 	mftc0	t0,\$2,5
+0+0088 <[^>]*> 41024006 	mftc0	t0,\$2,6
+0+008c <[^>]*> 41024007 	mftc0	t0,\$2,7
+0+0090 <[^>]*> 41034000 	mftc0	t0,c0_entrylo1
+0+0094 <[^>]*> 41034001 	mftc0	t0,\$3,1
+0+0098 <[^>]*> 41034002 	mftc0	t0,\$3,2
+0+009c <[^>]*> 41034003 	mftc0	t0,\$3,3
+0+00a0 <[^>]*> 41034004 	mftc0	t0,\$3,4
+0+00a4 <[^>]*> 41034005 	mftc0	t0,\$3,5
+0+00a8 <[^>]*> 41034006 	mftc0	t0,\$3,6
+0+00ac <[^>]*> 41034007 	mftc0	t0,\$3,7
+0+00b0 <[^>]*> 41044000 	mftc0	t0,c0_context
+0+00b4 <[^>]*> 41044001 	mftc0	t0,\$4,1
+0+00b8 <[^>]*> 41044002 	mftc0	t0,\$4,2
+0+00bc <[^>]*> 41044003 	mftc0	t0,\$4,3
+0+00c0 <[^>]*> 41044004 	mftc0	t0,\$4,4
+0+00c4 <[^>]*> 41044005 	mftc0	t0,\$4,5
+0+00c8 <[^>]*> 41044006 	mftc0	t0,\$4,6
+0+00cc <[^>]*> 41044007 	mftc0	t0,\$4,7
+0+00d0 <[^>]*> 41054000 	mftc0	t0,c0_pagemask
+0+00d4 <[^>]*> 41054001 	mftc0	t0,\$5,1
+0+00d8 <[^>]*> 41054002 	mftc0	t0,\$5,2
+0+00dc <[^>]*> 41054003 	mftc0	t0,\$5,3
+0+00e0 <[^>]*> 41054004 	mftc0	t0,\$5,4
+0+00e4 <[^>]*> 41054005 	mftc0	t0,\$5,5
+0+00e8 <[^>]*> 41054006 	mftc0	t0,\$5,6
+0+00ec <[^>]*> 41054007 	mftc0	t0,\$5,7
+0+00f0 <[^>]*> 41064000 	mftc0	t0,c0_wired
+0+00f4 <[^>]*> 41064001 	mftc0	t0,\$6,1
+0+00f8 <[^>]*> 41064002 	mftc0	t0,\$6,2
+0+00fc <[^>]*> 41064003 	mftc0	t0,\$6,3
+0+0100 <[^>]*> 41064004 	mftc0	t0,\$6,4
+0+0104 <[^>]*> 41064005 	mftc0	t0,\$6,5
+0+0108 <[^>]*> 41064006 	mftc0	t0,\$6,6
+0+010c <[^>]*> 41064007 	mftc0	t0,\$6,7
+0+0110 <[^>]*> 41074000 	mftc0	t0,\$7
+0+0114 <[^>]*> 41074001 	mftc0	t0,\$7,1
+0+0118 <[^>]*> 41074002 	mftc0	t0,\$7,2
+0+011c <[^>]*> 41074003 	mftc0	t0,\$7,3
+0+0120 <[^>]*> 41074004 	mftc0	t0,\$7,4
+0+0124 <[^>]*> 41074005 	mftc0	t0,\$7,5
+0+0128 <[^>]*> 41074006 	mftc0	t0,\$7,6
+0+012c <[^>]*> 41074007 	mftc0	t0,\$7,7
+0+0130 <[^>]*> 41084000 	mftc0	t0,c0_badvaddr
+0+0134 <[^>]*> 41084001 	mftc0	t0,\$8,1
+0+0138 <[^>]*> 41084002 	mftc0	t0,\$8,2
+0+013c <[^>]*> 41084003 	mftc0	t0,\$8,3
+0+0140 <[^>]*> 41084004 	mftc0	t0,\$8,4
+0+0144 <[^>]*> 41084005 	mftc0	t0,\$8,5
+0+0148 <[^>]*> 41084006 	mftc0	t0,\$8,6
+0+014c <[^>]*> 41084007 	mftc0	t0,\$8,7
+0+0150 <[^>]*> 41094000 	mftc0	t0,c0_count
+0+0154 <[^>]*> 41094001 	mftc0	t0,\$9,1
+0+0158 <[^>]*> 41094002 	mftc0	t0,\$9,2
+0+015c <[^>]*> 41094003 	mftc0	t0,\$9,3
+0+0160 <[^>]*> 41094004 	mftc0	t0,\$9,4
+0+0164 <[^>]*> 41094005 	mftc0	t0,\$9,5
+0+0168 <[^>]*> 41094006 	mftc0	t0,\$9,6
+0+016c <[^>]*> 41094007 	mftc0	t0,\$9,7
+0+0170 <[^>]*> 410a4000 	mftc0	t0,c0_entryhi
+0+0174 <[^>]*> 410a4001 	mftc0	t0,\$10,1
+0+0178 <[^>]*> 410a4002 	mftc0	t0,\$10,2
+0+017c <[^>]*> 410a4003 	mftc0	t0,\$10,3
+0+0180 <[^>]*> 410a4004 	mftc0	t0,\$10,4
+0+0184 <[^>]*> 410a4005 	mftc0	t0,\$10,5
+0+0188 <[^>]*> 410a4006 	mftc0	t0,\$10,6
+0+018c <[^>]*> 410a4007 	mftc0	t0,\$10,7
+0+0190 <[^>]*> 410b4000 	mftc0	t0,c0_compare
+0+0194 <[^>]*> 410b4001 	mftc0	t0,\$11,1
+0+0198 <[^>]*> 410b4002 	mftc0	t0,\$11,2
+0+019c <[^>]*> 410b4003 	mftc0	t0,\$11,3
+0+01a0 <[^>]*> 410b4004 	mftc0	t0,\$11,4
+0+01a4 <[^>]*> 410b4005 	mftc0	t0,\$11,5
+0+01a8 <[^>]*> 410b4006 	mftc0	t0,\$11,6
+0+01ac <[^>]*> 410b4007 	mftc0	t0,\$11,7
+0+01b0 <[^>]*> 410c4000 	mftc0	t0,c0_status
+0+01b4 <[^>]*> 410c4001 	mftc0	t0,\$12,1
+0+01b8 <[^>]*> 410c4002 	mftc0	t0,\$12,2
+0+01bc <[^>]*> 410c4003 	mftc0	t0,\$12,3
+0+01c0 <[^>]*> 410c4004 	mftc0	t0,\$12,4
+0+01c4 <[^>]*> 410c4005 	mftc0	t0,\$12,5
+0+01c8 <[^>]*> 410c4006 	mftc0	t0,\$12,6
+0+01cc <[^>]*> 410c4007 	mftc0	t0,\$12,7
+0+01d0 <[^>]*> 410d4000 	mftc0	t0,c0_cause
+0+01d4 <[^>]*> 410d4001 	mftc0	t0,\$13,1
+0+01d8 <[^>]*> 410d4002 	mftc0	t0,\$13,2
+0+01dc <[^>]*> 410d4003 	mftc0	t0,\$13,3
+0+01e0 <[^>]*> 410d4004 	mftc0	t0,\$13,4
+0+01e4 <[^>]*> 410d4005 	mftc0	t0,\$13,5
+0+01e8 <[^>]*> 410d4006 	mftc0	t0,\$13,6
+0+01ec <[^>]*> 410d4007 	mftc0	t0,\$13,7
+0+01f0 <[^>]*> 410e4000 	mftc0	t0,c0_epc
+0+01f4 <[^>]*> 410e4001 	mftc0	t0,\$14,1
+0+01f8 <[^>]*> 410e4002 	mftc0	t0,\$14,2
+0+01fc <[^>]*> 410e4003 	mftc0	t0,\$14,3
+0+0200 <[^>]*> 410e4004 	mftc0	t0,\$14,4
+0+0204 <[^>]*> 410e4005 	mftc0	t0,\$14,5
+0+0208 <[^>]*> 410e4006 	mftc0	t0,\$14,6
+0+020c <[^>]*> 410e4007 	mftc0	t0,\$14,7
+0+0210 <[^>]*> 410f4000 	mftc0	t0,c0_prid
+0+0214 <[^>]*> 410f4001 	mftc0	t0,\$15,1
+0+0218 <[^>]*> 410f4002 	mftc0	t0,\$15,2
+0+021c <[^>]*> 410f4003 	mftc0	t0,\$15,3
+0+0220 <[^>]*> 410f4004 	mftc0	t0,\$15,4
+0+0224 <[^>]*> 410f4005 	mftc0	t0,\$15,5
+0+0228 <[^>]*> 410f4006 	mftc0	t0,\$15,6
+0+022c <[^>]*> 410f4007 	mftc0	t0,\$15,7
+0+0230 <[^>]*> 41104000 	mftc0	t0,c0_config
+0+0234 <[^>]*> 41104001 	mftc0	t0,c0_config1
+0+0238 <[^>]*> 41104002 	mftc0	t0,c0_config2
+0+023c <[^>]*> 41104003 	mftc0	t0,c0_config3
+0+0240 <[^>]*> 41104004 	mftc0	t0,\$16,4
+0+0244 <[^>]*> 41104005 	mftc0	t0,\$16,5
+0+0248 <[^>]*> 41104006 	mftc0	t0,\$16,6
+0+024c <[^>]*> 41104007 	mftc0	t0,\$16,7
+0+0250 <[^>]*> 41114000 	mftc0	t0,c0_lladdr
+0+0254 <[^>]*> 41114001 	mftc0	t0,\$17,1
+0+0258 <[^>]*> 41114002 	mftc0	t0,\$17,2
+0+025c <[^>]*> 41114003 	mftc0	t0,\$17,3
+0+0260 <[^>]*> 41114004 	mftc0	t0,\$17,4
+0+0264 <[^>]*> 41114005 	mftc0	t0,\$17,5
+0+0268 <[^>]*> 41114006 	mftc0	t0,\$17,6
+0+026c <[^>]*> 41114007 	mftc0	t0,\$17,7
+0+0270 <[^>]*> 41124000 	mftc0	t0,c0_watchlo
+0+0274 <[^>]*> 41124001 	mftc0	t0,c0_watchlo,1
+0+0278 <[^>]*> 41124002 	mftc0	t0,c0_watchlo,2
+0+027c <[^>]*> 41124003 	mftc0	t0,c0_watchlo,3
+0+0280 <[^>]*> 41124004 	mftc0	t0,c0_watchlo,4
+0+0284 <[^>]*> 41124005 	mftc0	t0,c0_watchlo,5
+0+0288 <[^>]*> 41124006 	mftc0	t0,c0_watchlo,6
+0+028c <[^>]*> 41124007 	mftc0	t0,c0_watchlo,7
+0+0290 <[^>]*> 41134000 	mftc0	t0,c0_watchhi
+0+0294 <[^>]*> 41134001 	mftc0	t0,c0_watchhi,1
+0+0298 <[^>]*> 41134002 	mftc0	t0,c0_watchhi,2
+0+029c <[^>]*> 41134003 	mftc0	t0,c0_watchhi,3
+0+02a0 <[^>]*> 41134004 	mftc0	t0,c0_watchhi,4
+0+02a4 <[^>]*> 41134005 	mftc0	t0,c0_watchhi,5
+0+02a8 <[^>]*> 41134006 	mftc0	t0,c0_watchhi,6
+0+02ac <[^>]*> 41134007 	mftc0	t0,c0_watchhi,7
+0+02b0 <[^>]*> 41144000 	mftc0	t0,c0_xcontext
+0+02b4 <[^>]*> 41144001 	mftc0	t0,\$20,1
+0+02b8 <[^>]*> 41144002 	mftc0	t0,\$20,2
+0+02bc <[^>]*> 41144003 	mftc0	t0,\$20,3
+0+02c0 <[^>]*> 41144004 	mftc0	t0,\$20,4
+0+02c4 <[^>]*> 41144005 	mftc0	t0,\$20,5
+0+02c8 <[^>]*> 41144006 	mftc0	t0,\$20,6
+0+02cc <[^>]*> 41144007 	mftc0	t0,\$20,7
+0+02d0 <[^>]*> 41154000 	mftc0	t0,\$21
+0+02d4 <[^>]*> 41154001 	mftc0	t0,\$21,1
+0+02d8 <[^>]*> 41154002 	mftc0	t0,\$21,2
+0+02dc <[^>]*> 41154003 	mftc0	t0,\$21,3
+0+02e0 <[^>]*> 41154004 	mftc0	t0,\$21,4
+0+02e4 <[^>]*> 41154005 	mftc0	t0,\$21,5
+0+02e8 <[^>]*> 41154006 	mftc0	t0,\$21,6
+0+02ec <[^>]*> 41154007 	mftc0	t0,\$21,7
+0+02f0 <[^>]*> 41164000 	mftc0	t0,\$22
+0+02f4 <[^>]*> 41164001 	mftc0	t0,\$22,1
+0+02f8 <[^>]*> 41164002 	mftc0	t0,\$22,2
+0+02fc <[^>]*> 41164003 	mftc0	t0,\$22,3
+0+0300 <[^>]*> 41164004 	mftc0	t0,\$22,4
+0+0304 <[^>]*> 41164005 	mftc0	t0,\$22,5
+0+0308 <[^>]*> 41164006 	mftc0	t0,\$22,6
+0+030c <[^>]*> 41164007 	mftc0	t0,\$22,7
+0+0310 <[^>]*> 41174000 	mftc0	t0,c0_debug
+0+0314 <[^>]*> 41174001 	mftc0	t0,\$23,1
+0+0318 <[^>]*> 41174002 	mftc0	t0,\$23,2
+0+031c <[^>]*> 41174003 	mftc0	t0,\$23,3
+0+0320 <[^>]*> 41174004 	mftc0	t0,\$23,4
+0+0324 <[^>]*> 41174005 	mftc0	t0,\$23,5
+0+0328 <[^>]*> 41174006 	mftc0	t0,\$23,6
+0+032c <[^>]*> 41174007 	mftc0	t0,\$23,7
+0+0330 <[^>]*> 41184000 	mftc0	t0,c0_depc
+0+0334 <[^>]*> 41184001 	mftc0	t0,\$24,1
+0+0338 <[^>]*> 41184002 	mftc0	t0,\$24,2
+0+033c <[^>]*> 41184003 	mftc0	t0,\$24,3
+0+0340 <[^>]*> 41184004 	mftc0	t0,\$24,4
+0+0344 <[^>]*> 41184005 	mftc0	t0,\$24,5
+0+0348 <[^>]*> 41184006 	mftc0	t0,\$24,6
+0+034c <[^>]*> 41184007 	mftc0	t0,\$24,7
+0+0350 <[^>]*> 41194000 	mftc0	t0,c0_perfcnt
+0+0354 <[^>]*> 41194001 	mftc0	t0,c0_perfcnt,1
+0+0358 <[^>]*> 41194002 	mftc0	t0,c0_perfcnt,2
+0+035c <[^>]*> 41194003 	mftc0	t0,c0_perfcnt,3
+0+0360 <[^>]*> 41194004 	mftc0	t0,c0_perfcnt,4
+0+0364 <[^>]*> 41194005 	mftc0	t0,c0_perfcnt,5
+0+0368 <[^>]*> 41194006 	mftc0	t0,c0_perfcnt,6
+0+036c <[^>]*> 41194007 	mftc0	t0,c0_perfcnt,7
+0+0370 <[^>]*> 411a4000 	mftc0	t0,c0_errctl
+0+0374 <[^>]*> 411a4001 	mftc0	t0,\$26,1
+0+0378 <[^>]*> 411a4002 	mftc0	t0,\$26,2
+0+037c <[^>]*> 411a4003 	mftc0	t0,\$26,3
+0+0380 <[^>]*> 411a4004 	mftc0	t0,\$26,4
+0+0384 <[^>]*> 411a4005 	mftc0	t0,\$26,5
+0+0388 <[^>]*> 411a4006 	mftc0	t0,\$26,6
+0+038c <[^>]*> 411a4007 	mftc0	t0,\$26,7
+0+0390 <[^>]*> 411b4000 	mftc0	t0,c0_cacheerr
+0+0394 <[^>]*> 411b4001 	mftc0	t0,c0_cacheerr,1
+0+0398 <[^>]*> 411b4002 	mftc0	t0,c0_cacheerr,2
+0+039c <[^>]*> 411b4003 	mftc0	t0,c0_cacheerr,3
+0+03a0 <[^>]*> 411b4004 	mftc0	t0,\$27,4
+0+03a4 <[^>]*> 411b4005 	mftc0	t0,\$27,5
+0+03a8 <[^>]*> 411b4006 	mftc0	t0,\$27,6
+0+03ac <[^>]*> 411b4007 	mftc0	t0,\$27,7
+0+03b0 <[^>]*> 411c4000 	mftc0	t0,c0_taglo
+0+03b4 <[^>]*> 411c4001 	mftc0	t0,c0_datalo
+0+03b8 <[^>]*> 411c4002 	mftc0	t0,\$28,2
+0+03bc <[^>]*> 411c4003 	mftc0	t0,\$28,3
+0+03c0 <[^>]*> 411c4004 	mftc0	t0,\$28,4
+0+03c4 <[^>]*> 411c4005 	mftc0	t0,\$28,5
+0+03c8 <[^>]*> 411c4006 	mftc0	t0,\$28,6
+0+03cc <[^>]*> 411c4007 	mftc0	t0,\$28,7
+0+03d0 <[^>]*> 411d4000 	mftc0	t0,c0_taghi
+0+03d4 <[^>]*> 411d4001 	mftc0	t0,c0_datahi
+0+03d8 <[^>]*> 411d4002 	mftc0	t0,\$29,2
+0+03dc <[^>]*> 411d4003 	mftc0	t0,\$29,3
+0+03e0 <[^>]*> 411d4004 	mftc0	t0,\$29,4
+0+03e4 <[^>]*> 411d4005 	mftc0	t0,\$29,5
+0+03e8 <[^>]*> 411d4006 	mftc0	t0,\$29,6
+0+03ec <[^>]*> 411d4007 	mftc0	t0,\$29,7
+0+03f0 <[^>]*> 411e4000 	mftc0	t0,c0_errorepc
+0+03f4 <[^>]*> 411e4001 	mftc0	t0,\$30,1
+0+03f8 <[^>]*> 411e4002 	mftc0	t0,\$30,2
+0+03fc <[^>]*> 411e4003 	mftc0	t0,\$30,3
+0+0400 <[^>]*> 411e4004 	mftc0	t0,\$30,4
+0+0404 <[^>]*> 411e4005 	mftc0	t0,\$30,5
+0+0408 <[^>]*> 411e4006 	mftc0	t0,\$30,6
+0+040c <[^>]*> 411e4007 	mftc0	t0,\$30,7
+0+0410 <[^>]*> 411f4000 	mftc0	t0,c0_desave
+0+0414 <[^>]*> 411f4001 	mftc0	t0,\$31,1
+0+0418 <[^>]*> 411f4002 	mftc0	t0,\$31,2
+0+041c <[^>]*> 411f4003 	mftc0	t0,\$31,3
+0+0420 <[^>]*> 411f4004 	mftc0	t0,\$31,4
+0+0424 <[^>]*> 411f4005 	mftc0	t0,\$31,5
+0+0428 <[^>]*> 411f4006 	mftc0	t0,\$31,6
+0+042c <[^>]*> 411f4007 	mftc0	t0,\$31,7
+0+0430 <[^>]*> 410a4820 	mftgpr	t1,t2
+0+0434 <[^>]*> 41005021 	mftlo	t2
+0+0438 <[^>]*> 41005821 	mftlo	t3
+0+043c <[^>]*> 41016021 	mfthi	t4
+0+0440 <[^>]*> 41056821 	mfthi	t5,\$ac1
+0+0444 <[^>]*> 41027021 	mftacx	t6
+0+0448 <[^>]*> 410a7821 	mftacx	t7,\$ac2
+0+044c <[^>]*> 41108021 	mftdsp	s0
+0+0450 <[^>]*> 41128822 	mftc1	s1,\$f18
+0+0454 <[^>]*> 41139022 	mftc1	s2,\$f19
+0+0458 <[^>]*> 41149832 	mfthc1	s3,\$f20
+0+045c <[^>]*> 4116a032 	mfthc1	s4,\$f22
+0+0460 <[^>]*> 4116a823 	cftc1	s5,\$22
+0+0464 <[^>]*> 4117b023 	cftc1	s6,\$23
+0+0468 <[^>]*> 4118b824 	mftc2	s7,\$24
+0+046c <[^>]*> 4119c034 	mfthc2	t8,\$25
+0+0470 <[^>]*> 411ac825 	cftc2	t9,\$26
+0+0474 <[^>]*> 419ad800 	mttc0	k0,c0_cacheerr
+0+0478 <[^>]*> 419b0000 	mttc0	k1,c0_index
+0+047c <[^>]*> 419b0001 	mttc0	k1,\$0,1
+0+0480 <[^>]*> 419b0002 	mttc0	k1,\$0,2
+0+0484 <[^>]*> 419b0003 	mttc0	k1,\$0,3
+0+0488 <[^>]*> 419b0004 	mttc0	k1,\$0,4
+0+048c <[^>]*> 419b0005 	mttc0	k1,\$0,5
+0+0490 <[^>]*> 419b0006 	mttc0	k1,\$0,6
+0+0494 <[^>]*> 419b0007 	mttc0	k1,\$0,7
+0+0498 <[^>]*> 419b0800 	mttc0	k1,c0_random
+0+049c <[^>]*> 419b0801 	mttc0	k1,\$1,1
+0+04a0 <[^>]*> 419b0802 	mttc0	k1,\$1,2
+0+04a4 <[^>]*> 419b0803 	mttc0	k1,\$1,3
+0+04a8 <[^>]*> 419b0804 	mttc0	k1,\$1,4
+0+04ac <[^>]*> 419b0805 	mttc0	k1,\$1,5
+0+04b0 <[^>]*> 419b0806 	mttc0	k1,\$1,6
+0+04b4 <[^>]*> 419b0807 	mttc0	k1,\$1,7
+0+04b8 <[^>]*> 419b1000 	mttc0	k1,c0_entrylo0
+0+04bc <[^>]*> 419b1001 	mttc0	k1,\$2,1
+0+04c0 <[^>]*> 419b1002 	mttc0	k1,\$2,2
+0+04c4 <[^>]*> 419b1003 	mttc0	k1,\$2,3
+0+04c8 <[^>]*> 419b1004 	mttc0	k1,\$2,4
+0+04cc <[^>]*> 419b1005 	mttc0	k1,\$2,5
+0+04d0 <[^>]*> 419b1006 	mttc0	k1,\$2,6
+0+04d4 <[^>]*> 419b1007 	mttc0	k1,\$2,7
+0+04d8 <[^>]*> 419b1800 	mttc0	k1,c0_entrylo1
+0+04dc <[^>]*> 419b1801 	mttc0	k1,\$3,1
+0+04e0 <[^>]*> 419b1802 	mttc0	k1,\$3,2
+0+04e4 <[^>]*> 419b1803 	mttc0	k1,\$3,3
+0+04e8 <[^>]*> 419b1804 	mttc0	k1,\$3,4
+0+04ec <[^>]*> 419b1805 	mttc0	k1,\$3,5
+0+04f0 <[^>]*> 419b1806 	mttc0	k1,\$3,6
+0+04f4 <[^>]*> 419b1807 	mttc0	k1,\$3,7
+0+04f8 <[^>]*> 419b2000 	mttc0	k1,c0_context
+0+04fc <[^>]*> 419b2001 	mttc0	k1,\$4,1
+0+0500 <[^>]*> 419b2002 	mttc0	k1,\$4,2
+0+0504 <[^>]*> 419b2003 	mttc0	k1,\$4,3
+0+0508 <[^>]*> 419b2004 	mttc0	k1,\$4,4
+0+050c <[^>]*> 419b2005 	mttc0	k1,\$4,5
+0+0510 <[^>]*> 419b2006 	mttc0	k1,\$4,6
+0+0514 <[^>]*> 419b2007 	mttc0	k1,\$4,7
+0+0518 <[^>]*> 419b2800 	mttc0	k1,c0_pagemask
+0+051c <[^>]*> 419b2801 	mttc0	k1,\$5,1
+0+0520 <[^>]*> 419b2802 	mttc0	k1,\$5,2
+0+0524 <[^>]*> 419b2803 	mttc0	k1,\$5,3
+0+0528 <[^>]*> 419b2804 	mttc0	k1,\$5,4
+0+052c <[^>]*> 419b2805 	mttc0	k1,\$5,5
+0+0530 <[^>]*> 419b2806 	mttc0	k1,\$5,6
+0+0534 <[^>]*> 419b2807 	mttc0	k1,\$5,7
+0+0538 <[^>]*> 419b3000 	mttc0	k1,c0_wired
+0+053c <[^>]*> 419b3001 	mttc0	k1,\$6,1
+0+0540 <[^>]*> 419b3002 	mttc0	k1,\$6,2
+0+0544 <[^>]*> 419b3003 	mttc0	k1,\$6,3
+0+0548 <[^>]*> 419b3004 	mttc0	k1,\$6,4
+0+054c <[^>]*> 419b3005 	mttc0	k1,\$6,5
+0+0550 <[^>]*> 419b3006 	mttc0	k1,\$6,6
+0+0554 <[^>]*> 419b3007 	mttc0	k1,\$6,7
+0+0558 <[^>]*> 419b3800 	mttc0	k1,\$7
+0+055c <[^>]*> 419b3801 	mttc0	k1,\$7,1
+0+0560 <[^>]*> 419b3802 	mttc0	k1,\$7,2
+0+0564 <[^>]*> 419b3803 	mttc0	k1,\$7,3
+0+0568 <[^>]*> 419b3804 	mttc0	k1,\$7,4
+0+056c <[^>]*> 419b3805 	mttc0	k1,\$7,5
+0+0570 <[^>]*> 419b3806 	mttc0	k1,\$7,6
+0+0574 <[^>]*> 419b3807 	mttc0	k1,\$7,7
+0+0578 <[^>]*> 419b4000 	mttc0	k1,c0_badvaddr
+0+057c <[^>]*> 419b4001 	mttc0	k1,\$8,1
+0+0580 <[^>]*> 419b4002 	mttc0	k1,\$8,2
+0+0584 <[^>]*> 419b4003 	mttc0	k1,\$8,3
+0+0588 <[^>]*> 419b4004 	mttc0	k1,\$8,4
+0+058c <[^>]*> 419b4005 	mttc0	k1,\$8,5
+0+0590 <[^>]*> 419b4006 	mttc0	k1,\$8,6
+0+0594 <[^>]*> 419b4007 	mttc0	k1,\$8,7
+0+0598 <[^>]*> 419b4800 	mttc0	k1,c0_count
+0+059c <[^>]*> 419b4801 	mttc0	k1,\$9,1
+0+05a0 <[^>]*> 419b4802 	mttc0	k1,\$9,2
+0+05a4 <[^>]*> 419b4803 	mttc0	k1,\$9,3
+0+05a8 <[^>]*> 419b4804 	mttc0	k1,\$9,4
+0+05ac <[^>]*> 419b4805 	mttc0	k1,\$9,5
+0+05b0 <[^>]*> 419b4806 	mttc0	k1,\$9,6
+0+05b4 <[^>]*> 419b4807 	mttc0	k1,\$9,7
+0+05b8 <[^>]*> 419b5000 	mttc0	k1,c0_entryhi
+0+05bc <[^>]*> 419b5001 	mttc0	k1,\$10,1
+0+05c0 <[^>]*> 419b5002 	mttc0	k1,\$10,2
+0+05c4 <[^>]*> 419b5003 	mttc0	k1,\$10,3
+0+05c8 <[^>]*> 419b5004 	mttc0	k1,\$10,4
+0+05cc <[^>]*> 419b5005 	mttc0	k1,\$10,5
+0+05d0 <[^>]*> 419b5006 	mttc0	k1,\$10,6
+0+05d4 <[^>]*> 419b5007 	mttc0	k1,\$10,7
+0+05d8 <[^>]*> 419b5800 	mttc0	k1,c0_compare
+0+05dc <[^>]*> 419b5801 	mttc0	k1,\$11,1
+0+05e0 <[^>]*> 419b5802 	mttc0	k1,\$11,2
+0+05e4 <[^>]*> 419b5803 	mttc0	k1,\$11,3
+0+05e8 <[^>]*> 419b5804 	mttc0	k1,\$11,4
+0+05ec <[^>]*> 419b5805 	mttc0	k1,\$11,5
+0+05f0 <[^>]*> 419b5806 	mttc0	k1,\$11,6
+0+05f4 <[^>]*> 419b5807 	mttc0	k1,\$11,7
+0+05f8 <[^>]*> 419b6000 	mttc0	k1,c0_status
+0+05fc <[^>]*> 419b6001 	mttc0	k1,\$12,1
+0+0600 <[^>]*> 419b6002 	mttc0	k1,\$12,2
+0+0604 <[^>]*> 419b6003 	mttc0	k1,\$12,3
+0+0608 <[^>]*> 419b6004 	mttc0	k1,\$12,4
+0+060c <[^>]*> 419b6005 	mttc0	k1,\$12,5
+0+0610 <[^>]*> 419b6006 	mttc0	k1,\$12,6
+0+0614 <[^>]*> 419b6007 	mttc0	k1,\$12,7
+0+0618 <[^>]*> 419b6800 	mttc0	k1,c0_cause
+0+061c <[^>]*> 419b6801 	mttc0	k1,\$13,1
+0+0620 <[^>]*> 419b6802 	mttc0	k1,\$13,2
+0+0624 <[^>]*> 419b6803 	mttc0	k1,\$13,3
+0+0628 <[^>]*> 419b6804 	mttc0	k1,\$13,4
+0+062c <[^>]*> 419b6805 	mttc0	k1,\$13,5
+0+0630 <[^>]*> 419b6806 	mttc0	k1,\$13,6
+0+0634 <[^>]*> 419b6807 	mttc0	k1,\$13,7
+0+0638 <[^>]*> 419b7000 	mttc0	k1,c0_epc
+0+063c <[^>]*> 419b7001 	mttc0	k1,\$14,1
+0+0640 <[^>]*> 419b7002 	mttc0	k1,\$14,2
+0+0644 <[^>]*> 419b7003 	mttc0	k1,\$14,3
+0+0648 <[^>]*> 419b7004 	mttc0	k1,\$14,4
+0+064c <[^>]*> 419b7005 	mttc0	k1,\$14,5
+0+0650 <[^>]*> 419b7006 	mttc0	k1,\$14,6
+0+0654 <[^>]*> 419b7007 	mttc0	k1,\$14,7
+0+0658 <[^>]*> 419b7800 	mttc0	k1,c0_prid
+0+065c <[^>]*> 419b7801 	mttc0	k1,\$15,1
+0+0660 <[^>]*> 419b7802 	mttc0	k1,\$15,2
+0+0664 <[^>]*> 419b7803 	mttc0	k1,\$15,3
+0+0668 <[^>]*> 419b7804 	mttc0	k1,\$15,4
+0+066c <[^>]*> 419b7805 	mttc0	k1,\$15,5
+0+0670 <[^>]*> 419b7806 	mttc0	k1,\$15,6
+0+0674 <[^>]*> 419b7807 	mttc0	k1,\$15,7
+0+0678 <[^>]*> 419b8000 	mttc0	k1,c0_config
+0+067c <[^>]*> 419b8001 	mttc0	k1,c0_config1
+0+0680 <[^>]*> 419b8002 	mttc0	k1,c0_config2
+0+0684 <[^>]*> 419b8003 	mttc0	k1,c0_config3
+0+0688 <[^>]*> 419b8004 	mttc0	k1,\$16,4
+0+068c <[^>]*> 419b8005 	mttc0	k1,\$16,5
+0+0690 <[^>]*> 419b8006 	mttc0	k1,\$16,6
+0+0694 <[^>]*> 419b8007 	mttc0	k1,\$16,7
+0+0698 <[^>]*> 419b8800 	mttc0	k1,c0_lladdr
+0+069c <[^>]*> 419b8801 	mttc0	k1,\$17,1
+0+06a0 <[^>]*> 419b8802 	mttc0	k1,\$17,2
+0+06a4 <[^>]*> 419b8803 	mttc0	k1,\$17,3
+0+06a8 <[^>]*> 419b8804 	mttc0	k1,\$17,4
+0+06ac <[^>]*> 419b8805 	mttc0	k1,\$17,5
+0+06b0 <[^>]*> 419b8806 	mttc0	k1,\$17,6
+0+06b4 <[^>]*> 419b8807 	mttc0	k1,\$17,7
+0+06b8 <[^>]*> 419b9000 	mttc0	k1,c0_watchlo
+0+06bc <[^>]*> 419b9001 	mttc0	k1,c0_watchlo,1
+0+06c0 <[^>]*> 419b9002 	mttc0	k1,c0_watchlo,2
+0+06c4 <[^>]*> 419b9003 	mttc0	k1,c0_watchlo,3
+0+06c8 <[^>]*> 419b9004 	mttc0	k1,c0_watchlo,4
+0+06cc <[^>]*> 419b9005 	mttc0	k1,c0_watchlo,5
+0+06d0 <[^>]*> 419b9006 	mttc0	k1,c0_watchlo,6
+0+06d4 <[^>]*> 419b9007 	mttc0	k1,c0_watchlo,7
+0+06d8 <[^>]*> 419b9800 	mttc0	k1,c0_watchhi
+0+06dc <[^>]*> 419b9801 	mttc0	k1,c0_watchhi,1
+0+06e0 <[^>]*> 419b9802 	mttc0	k1,c0_watchhi,2
+0+06e4 <[^>]*> 419b9803 	mttc0	k1,c0_watchhi,3
+0+06e8 <[^>]*> 419b9804 	mttc0	k1,c0_watchhi,4
+0+06ec <[^>]*> 419b9805 	mttc0	k1,c0_watchhi,5
+0+06f0 <[^>]*> 419b9806 	mttc0	k1,c0_watchhi,6
+0+06f4 <[^>]*> 419b9807 	mttc0	k1,c0_watchhi,7
+0+06f8 <[^>]*> 419ba000 	mttc0	k1,c0_xcontext
+0+06fc <[^>]*> 419ba001 	mttc0	k1,\$20,1
+0+0700 <[^>]*> 419ba002 	mttc0	k1,\$20,2
+0+0704 <[^>]*> 419ba003 	mttc0	k1,\$20,3
+0+0708 <[^>]*> 419ba004 	mttc0	k1,\$20,4
+0+070c <[^>]*> 419ba005 	mttc0	k1,\$20,5
+0+0710 <[^>]*> 419ba006 	mttc0	k1,\$20,6
+0+0714 <[^>]*> 419ba007 	mttc0	k1,\$20,7
+0+0718 <[^>]*> 419ba800 	mttc0	k1,\$21
+0+071c <[^>]*> 419ba801 	mttc0	k1,\$21,1
+0+0720 <[^>]*> 419ba802 	mttc0	k1,\$21,2
+0+0724 <[^>]*> 419ba803 	mttc0	k1,\$21,3
+0+0728 <[^>]*> 419ba804 	mttc0	k1,\$21,4
+0+072c <[^>]*> 419ba805 	mttc0	k1,\$21,5
+0+0730 <[^>]*> 419ba806 	mttc0	k1,\$21,6
+0+0734 <[^>]*> 419ba807 	mttc0	k1,\$21,7
+0+0738 <[^>]*> 419bb000 	mttc0	k1,\$22
+0+073c <[^>]*> 419bb001 	mttc0	k1,\$22,1
+0+0740 <[^>]*> 419bb002 	mttc0	k1,\$22,2
+0+0744 <[^>]*> 419bb003 	mttc0	k1,\$22,3
+0+0748 <[^>]*> 419bb004 	mttc0	k1,\$22,4
+0+074c <[^>]*> 419bb005 	mttc0	k1,\$22,5
+0+0750 <[^>]*> 419bb006 	mttc0	k1,\$22,6
+0+0754 <[^>]*> 419bb007 	mttc0	k1,\$22,7
+0+0758 <[^>]*> 419bb800 	mttc0	k1,c0_debug
+0+075c <[^>]*> 419bb801 	mttc0	k1,\$23,1
+0+0760 <[^>]*> 419bb802 	mttc0	k1,\$23,2
+0+0764 <[^>]*> 419bb803 	mttc0	k1,\$23,3
+0+0768 <[^>]*> 419bb804 	mttc0	k1,\$23,4
+0+076c <[^>]*> 419bb805 	mttc0	k1,\$23,5
+0+0770 <[^>]*> 419bb806 	mttc0	k1,\$23,6
+0+0774 <[^>]*> 419bb807 	mttc0	k1,\$23,7
+0+0778 <[^>]*> 419bc000 	mttc0	k1,c0_depc
+0+077c <[^>]*> 419bc001 	mttc0	k1,\$24,1
+0+0780 <[^>]*> 419bc002 	mttc0	k1,\$24,2
+0+0784 <[^>]*> 419bc003 	mttc0	k1,\$24,3
+0+0788 <[^>]*> 419bc004 	mttc0	k1,\$24,4
+0+078c <[^>]*> 419bc005 	mttc0	k1,\$24,5
+0+0790 <[^>]*> 419bc006 	mttc0	k1,\$24,6
+0+0794 <[^>]*> 419bc007 	mttc0	k1,\$24,7
+0+0798 <[^>]*> 419bc800 	mttc0	k1,c0_perfcnt
+0+079c <[^>]*> 419bc801 	mttc0	k1,c0_perfcnt,1
+0+07a0 <[^>]*> 419bc802 	mttc0	k1,c0_perfcnt,2
+0+07a4 <[^>]*> 419bc803 	mttc0	k1,c0_perfcnt,3
+0+07a8 <[^>]*> 419bc804 	mttc0	k1,c0_perfcnt,4
+0+07ac <[^>]*> 419bc805 	mttc0	k1,c0_perfcnt,5
+0+07b0 <[^>]*> 419bc806 	mttc0	k1,c0_perfcnt,6
+0+07b4 <[^>]*> 419bc807 	mttc0	k1,c0_perfcnt,7
+0+07b8 <[^>]*> 419bd000 	mttc0	k1,c0_errctl
+0+07bc <[^>]*> 419bd001 	mttc0	k1,\$26,1
+0+07c0 <[^>]*> 419bd002 	mttc0	k1,\$26,2
+0+07c4 <[^>]*> 419bd003 	mttc0	k1,\$26,3
+0+07c8 <[^>]*> 419bd004 	mttc0	k1,\$26,4
+0+07cc <[^>]*> 419bd005 	mttc0	k1,\$26,5
+0+07d0 <[^>]*> 419bd006 	mttc0	k1,\$26,6
+0+07d4 <[^>]*> 419bd007 	mttc0	k1,\$26,7
+0+07d8 <[^>]*> 419bd800 	mttc0	k1,c0_cacheerr
+0+07dc <[^>]*> 419bd801 	mttc0	k1,c0_cacheerr,1
+0+07e0 <[^>]*> 419bd802 	mttc0	k1,c0_cacheerr,2
+0+07e4 <[^>]*> 419bd803 	mttc0	k1,c0_cacheerr,3
+0+07e8 <[^>]*> 419bd804 	mttc0	k1,\$27,4
+0+07ec <[^>]*> 419bd805 	mttc0	k1,\$27,5
+0+07f0 <[^>]*> 419bd806 	mttc0	k1,\$27,6
+0+07f4 <[^>]*> 419bd807 	mttc0	k1,\$27,7
+0+07f8 <[^>]*> 419be000 	mttc0	k1,c0_taglo
+0+07fc <[^>]*> 419be001 	mttc0	k1,c0_datalo
+0+0800 <[^>]*> 419be002 	mttc0	k1,\$28,2
+0+0804 <[^>]*> 419be003 	mttc0	k1,\$28,3
+0+0808 <[^>]*> 419be004 	mttc0	k1,\$28,4
+0+080c <[^>]*> 419be005 	mttc0	k1,\$28,5
+0+0810 <[^>]*> 419be006 	mttc0	k1,\$28,6
+0+0814 <[^>]*> 419be007 	mttc0	k1,\$28,7
+0+0818 <[^>]*> 419be800 	mttc0	k1,c0_taghi
+0+081c <[^>]*> 419be801 	mttc0	k1,c0_datahi
+0+0820 <[^>]*> 419be802 	mttc0	k1,\$29,2
+0+0824 <[^>]*> 419be803 	mttc0	k1,\$29,3
+0+0828 <[^>]*> 419be804 	mttc0	k1,\$29,4
+0+082c <[^>]*> 419be805 	mttc0	k1,\$29,5
+0+0830 <[^>]*> 419be806 	mttc0	k1,\$29,6
+0+0834 <[^>]*> 419be807 	mttc0	k1,\$29,7
+0+0838 <[^>]*> 419bf000 	mttc0	k1,c0_errorepc
+0+083c <[^>]*> 419bf001 	mttc0	k1,\$30,1
+0+0840 <[^>]*> 419bf002 	mttc0	k1,\$30,2
+0+0844 <[^>]*> 419bf003 	mttc0	k1,\$30,3
+0+0848 <[^>]*> 419bf004 	mttc0	k1,\$30,4
+0+084c <[^>]*> 419bf005 	mttc0	k1,\$30,5
+0+0850 <[^>]*> 419bf006 	mttc0	k1,\$30,6
+0+0854 <[^>]*> 419bf007 	mttc0	k1,\$30,7
+0+0858 <[^>]*> 419bf800 	mttc0	k1,c0_desave
+0+085c <[^>]*> 419bf801 	mttc0	k1,\$31,1
+0+0860 <[^>]*> 419bf802 	mttc0	k1,\$31,2
+0+0864 <[^>]*> 419bf803 	mttc0	k1,\$31,3
+0+0868 <[^>]*> 419bf804 	mttc0	k1,\$31,4
+0+086c <[^>]*> 419bf805 	mttc0	k1,\$31,5
+0+0870 <[^>]*> 419bf806 	mttc0	k1,\$31,6
+0+0874 <[^>]*> 419bf807 	mttc0	k1,\$31,7
+0+0878 <[^>]*> 419ce820 	mttgpr	gp,sp
+0+087c <[^>]*> 419d0021 	mttlo	sp
+0+0880 <[^>]*> 419e6021 	mttlo	s8,\$ac3
+0+0884 <[^>]*> 419f0821 	mtthi	ra
+0+0888 <[^>]*> 41800821 	mtthi	zero
+0+088c <[^>]*> 41811021 	mttacx	at
+0+0890 <[^>]*> 41823021 	mttacx	v0,\$ac1
+0+0894 <[^>]*> 41838021 	mttdsp	v1
+0+0898 <[^>]*> 41842822 	mttc1	a0,\$f5
+0+089c <[^>]*> 41853022 	mttc1	a1,\$f6
+0+08a0 <[^>]*> 41864032 	mtthc1	a2,\$f8
+0+08a4 <[^>]*> 41875032 	mtthc1	a3,\$f10
+0+08a8 <[^>]*> 41884823 	cttc1	t0,\$9
+0+08ac <[^>]*> 41895023 	cttc1	t1,\$10
+0+08b0 <[^>]*> 418a5824 	mttc2	t2,\$11
+0+08b4 <[^>]*> 418b6034 	mtthc2	t3,\$12
+0+08b8 <[^>]*> 418c6825 	cttc2	t4,\$13
+0+08bc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
+0+08c0 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
+0+08c4 <[^>]*> 410e6832 	mfthc1	t5,\$f14
+0+08c8 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
+0+08cc <[^>]*> 410e6834 	mfthc2	t5,\$14
+0+08d0 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
+0+08d4 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
+0+08d8 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
+0+08dc <[^>]*> 410e6820 	mftgpr	t5,t6
+0+08e0 <[^>]*> 410e6821 	mftacx	t5,\$ac3
+0+08e4 <[^>]*> 410e6822 	mftc1	t5,\$f14
+0+08e8 <[^>]*> 410e6823 	cftc1	t5,\$14
+0+08ec <[^>]*> 410e6824 	mftc2	t5,\$14
+0+08f0 <[^>]*> 410e6825 	cftc2	t5,\$14
+0+08f4 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
+0+08f8 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
+0+08fc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
+0+0900 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
+0+0904 <[^>]*> 410e6832 	mfthc1	t5,\$f14
+0+0908 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
+0+090c <[^>]*> 410e6834 	mfthc2	t5,\$14
+0+0910 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
+0+0914 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
+0+0918 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
+0+091c <[^>]*> 410e6820 	mftgpr	t5,t6
+0+0920 <[^>]*> 410e6821 	mftacx	t5,\$ac3
+0+0924 <[^>]*> 410e6822 	mftc1	t5,\$f14
+0+0928 <[^>]*> 410e6823 	cftc1	t5,\$14
+0+092c <[^>]*> 410e6824 	mftc2	t5,\$14
+0+0930 <[^>]*> 410e6825 	cftc2	t5,\$14
+0+0934 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
+0+0938 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
+0+093c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
+0+0940 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
+0+0944 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
+0+0948 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
+0+094c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
+0+0950 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
+0+0954 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
+0+0958 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
+0+095c <[^>]*> 410e6800 	mftc0	t5,c0_epc
+0+0960 <[^>]*> 410e6801 	mftc0	t5,\$14,1
+0+0964 <[^>]*> 410e6802 	mftc0	t5,\$14,2
+0+0968 <[^>]*> 410e6803 	mftc0	t5,\$14,3
+0+096c <[^>]*> 410e6804 	mftc0	t5,\$14,4
+0+0970 <[^>]*> 410e6805 	mftc0	t5,\$14,5
+0+0974 <[^>]*> 410e6806 	mftc0	t5,\$14,6
+0+0978 <[^>]*> 410e6807 	mftc0	t5,\$14,7
+0+097c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
+0+0980 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
+0+0984 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
+0+0988 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
+0+098c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
+0+0990 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
+0+0994 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
+0+0998 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
+0+099c <[^>]*> 410e6800 	mftc0	t5,c0_epc
+0+09a0 <[^>]*> 410e6801 	mftc0	t5,\$14,1
+0+09a4 <[^>]*> 410e6802 	mftc0	t5,\$14,2
+0+09a8 <[^>]*> 410e6803 	mftc0	t5,\$14,3
+0+09ac <[^>]*> 410e6804 	mftc0	t5,\$14,4
+0+09b0 <[^>]*> 410e6805 	mftc0	t5,\$14,5
+0+09b4 <[^>]*> 410e6806 	mftc0	t5,\$14,6
+0+09b8 <[^>]*> 410e6807 	mftc0	t5,\$14,7
+0+09bc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
+0+09c0 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
+0+09c4 <[^>]*> 410e6832 	mfthc1	t5,\$f14
+0+09c8 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
+0+09cc <[^>]*> 410e6834 	mfthc2	t5,\$14
+0+09d0 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
+0+09d4 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
+0+09d8 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
+0+09dc <[^>]*> 410e6820 	mftgpr	t5,t6
+0+09e0 <[^>]*> 410e6821 	mftacx	t5,\$ac3
+0+09e4 <[^>]*> 410e6822 	mftc1	t5,\$f14
+0+09e8 <[^>]*> 410e6823 	cftc1	t5,\$14
+0+09ec <[^>]*> 410e6824 	mftc2	t5,\$14
+0+09f0 <[^>]*> 410e6825 	cftc2	t5,\$14
+0+09f4 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
+0+09f8 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
+0+09fc <[^>]*> 410e6830 	mftr	t5,t6,1,0,1
+0+0a00 <[^>]*> 410e6831 	mftr	t5,t6,1,1,1
+0+0a04 <[^>]*> 410e6832 	mfthc1	t5,\$f14
+0+0a08 <[^>]*> 410e6833 	mftr	t5,t6,1,3,1
+0+0a0c <[^>]*> 410e6834 	mfthc2	t5,\$14
+0+0a10 <[^>]*> 410e6835 	mftr	t5,t6,1,5,1
+0+0a14 <[^>]*> 410e6836 	mftr	t5,t6,1,6,1
+0+0a18 <[^>]*> 410e6837 	mftr	t5,t6,1,7,1
+0+0a1c <[^>]*> 410e6820 	mftgpr	t5,t6
+0+0a20 <[^>]*> 410e6821 	mftacx	t5,\$ac3
+0+0a24 <[^>]*> 410e6822 	mftc1	t5,\$f14
+0+0a28 <[^>]*> 410e6823 	cftc1	t5,\$14
+0+0a2c <[^>]*> 410e6824 	mftc2	t5,\$14
+0+0a30 <[^>]*> 410e6825 	cftc2	t5,\$14
+0+0a34 <[^>]*> 410e6826 	mftr	t5,t6,1,6,0
+0+0a38 <[^>]*> 410e6827 	mftr	t5,t6,1,7,0
+0+0a3c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
+0+0a40 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
+0+0a44 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
+0+0a48 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
+0+0a4c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
+0+0a50 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
+0+0a54 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
+0+0a58 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
+0+0a5c <[^>]*> 410e6800 	mftc0	t5,c0_epc
+0+0a60 <[^>]*> 410e6801 	mftc0	t5,\$14,1
+0+0a64 <[^>]*> 410e6802 	mftc0	t5,\$14,2
+0+0a68 <[^>]*> 410e6803 	mftc0	t5,\$14,3
+0+0a6c <[^>]*> 410e6804 	mftc0	t5,\$14,4
+0+0a70 <[^>]*> 410e6805 	mftc0	t5,\$14,5
+0+0a74 <[^>]*> 410e6806 	mftc0	t5,\$14,6
+0+0a78 <[^>]*> 410e6807 	mftc0	t5,\$14,7
+0+0a7c <[^>]*> 410e6810 	mftr	t5,t6,0,0,1
+0+0a80 <[^>]*> 410e6811 	mftr	t5,t6,0,1,1
+0+0a84 <[^>]*> 410e6812 	mftr	t5,t6,0,2,1
+0+0a88 <[^>]*> 410e6813 	mftr	t5,t6,0,3,1
+0+0a8c <[^>]*> 410e6814 	mftr	t5,t6,0,4,1
+0+0a90 <[^>]*> 410e6815 	mftr	t5,t6,0,5,1
+0+0a94 <[^>]*> 410e6816 	mftr	t5,t6,0,6,1
+0+0a98 <[^>]*> 410e6817 	mftr	t5,t6,0,7,1
+0+0a9c <[^>]*> 410e6800 	mftc0	t5,c0_epc
+0+0aa0 <[^>]*> 410e6801 	mftc0	t5,\$14,1
+0+0aa4 <[^>]*> 410e6802 	mftc0	t5,\$14,2
+0+0aa8 <[^>]*> 410e6803 	mftc0	t5,\$14,3
+0+0aac <[^>]*> 410e6804 	mftc0	t5,\$14,4
+0+0ab0 <[^>]*> 410e6805 	mftc0	t5,\$14,5
+0+0ab4 <[^>]*> 410e6806 	mftc0	t5,\$14,6
+0+0ab8 <[^>]*> 410e6807 	mftc0	t5,\$14,7
+0+0abc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
+0+0ac0 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
+0+0ac4 <[^>]*> 418d7032 	mtthc1	t5,\$f14
+0+0ac8 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
+0+0acc <[^>]*> 418d7034 	mtthc2	t5,\$14
+0+0ad0 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
+0+0ad4 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
+0+0ad8 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
+0+0adc <[^>]*> 418d7020 	mttgpr	t5,t6
+0+0ae0 <[^>]*> 418d7021 	mttacx	t5,\$ac3
+0+0ae4 <[^>]*> 418d7022 	mttc1	t5,\$f14
+0+0ae8 <[^>]*> 418d7023 	cttc1	t5,\$14
+0+0aec <[^>]*> 418d7024 	mttc2	t5,\$14
+0+0af0 <[^>]*> 418d7025 	cttc2	t5,\$14
+0+0af4 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
+0+0af8 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
+0+0afc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
+0+0b00 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
+0+0b04 <[^>]*> 418d7032 	mtthc1	t5,\$f14
+0+0b08 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
+0+0b0c <[^>]*> 418d7034 	mtthc2	t5,\$14
+0+0b10 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
+0+0b14 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
+0+0b18 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
+0+0b1c <[^>]*> 418d7020 	mttgpr	t5,t6
+0+0b20 <[^>]*> 418d7021 	mttacx	t5,\$ac3
+0+0b24 <[^>]*> 418d7022 	mttc1	t5,\$f14
+0+0b28 <[^>]*> 418d7023 	cttc1	t5,\$14
+0+0b2c <[^>]*> 418d7024 	mttc2	t5,\$14
+0+0b30 <[^>]*> 418d7025 	cttc2	t5,\$14
+0+0b34 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
+0+0b38 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
+0+0b3c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
+0+0b40 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
+0+0b44 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
+0+0b48 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
+0+0b4c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
+0+0b50 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
+0+0b54 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
+0+0b58 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
+0+0b5c <[^>]*> 418d7000 	mttc0	t5,c0_epc
+0+0b60 <[^>]*> 418d7001 	mttc0	t5,\$14,1
+0+0b64 <[^>]*> 418d7002 	mttc0	t5,\$14,2
+0+0b68 <[^>]*> 418d7003 	mttc0	t5,\$14,3
+0+0b6c <[^>]*> 418d7004 	mttc0	t5,\$14,4
+0+0b70 <[^>]*> 418d7005 	mttc0	t5,\$14,5
+0+0b74 <[^>]*> 418d7006 	mttc0	t5,\$14,6
+0+0b78 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+0+0b7c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
+0+0b80 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
+0+0b84 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
+0+0b88 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
+0+0b8c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
+0+0b90 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
+0+0b94 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
+0+0b98 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
+0+0b9c <[^>]*> 418d7000 	mttc0	t5,c0_epc
+0+0ba0 <[^>]*> 418d7001 	mttc0	t5,\$14,1
+0+0ba4 <[^>]*> 418d7002 	mttc0	t5,\$14,2
+0+0ba8 <[^>]*> 418d7003 	mttc0	t5,\$14,3
+0+0bac <[^>]*> 418d7004 	mttc0	t5,\$14,4
+0+0bb0 <[^>]*> 418d7005 	mttc0	t5,\$14,5
+0+0bb4 <[^>]*> 418d7006 	mttc0	t5,\$14,6
+0+0bb8 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+0+0bbc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
+0+0bc0 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
+0+0bc4 <[^>]*> 418d7032 	mtthc1	t5,\$f14
+0+0bc8 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
+0+0bcc <[^>]*> 418d7034 	mtthc2	t5,\$14
+0+0bd0 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
+0+0bd4 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
+0+0bd8 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
+0+0bdc <[^>]*> 418d7020 	mttgpr	t5,t6
+0+0be0 <[^>]*> 418d7021 	mttacx	t5,\$ac3
+0+0be4 <[^>]*> 418d7022 	mttc1	t5,\$f14
+0+0be8 <[^>]*> 418d7023 	cttc1	t5,\$14
+0+0bec <[^>]*> 418d7024 	mttc2	t5,\$14
+0+0bf0 <[^>]*> 418d7025 	cttc2	t5,\$14
+0+0bf4 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
+0+0bf8 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
+0+0bfc <[^>]*> 418d7030 	mttr	t5,t6,1,0,1
+0+0c00 <[^>]*> 418d7031 	mttr	t5,t6,1,1,1
+0+0c04 <[^>]*> 418d7032 	mtthc1	t5,\$f14
+0+0c08 <[^>]*> 418d7033 	mttr	t5,t6,1,3,1
+0+0c0c <[^>]*> 418d7034 	mtthc2	t5,\$14
+0+0c10 <[^>]*> 418d7035 	mttr	t5,t6,1,5,1
+0+0c14 <[^>]*> 418d7036 	mttr	t5,t6,1,6,1
+0+0c18 <[^>]*> 418d7037 	mttr	t5,t6,1,7,1
+0+0c1c <[^>]*> 418d7020 	mttgpr	t5,t6
+0+0c20 <[^>]*> 418d7021 	mttacx	t5,\$ac3
+0+0c24 <[^>]*> 418d7022 	mttc1	t5,\$f14
+0+0c28 <[^>]*> 418d7023 	cttc1	t5,\$14
+0+0c2c <[^>]*> 418d7024 	mttc2	t5,\$14
+0+0c30 <[^>]*> 418d7025 	cttc2	t5,\$14
+0+0c34 <[^>]*> 418d7026 	mttr	t5,t6,1,6,0
+0+0c38 <[^>]*> 418d7027 	mttr	t5,t6,1,7,0
+0+0c3c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
+0+0c40 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
+0+0c44 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
+0+0c48 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
+0+0c4c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
+0+0c50 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
+0+0c54 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
+0+0c58 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
+0+0c5c <[^>]*> 418d7000 	mttc0	t5,c0_epc
+0+0c60 <[^>]*> 418d7001 	mttc0	t5,\$14,1
+0+0c64 <[^>]*> 418d7002 	mttc0	t5,\$14,2
+0+0c68 <[^>]*> 418d7003 	mttc0	t5,\$14,3
+0+0c6c <[^>]*> 418d7004 	mttc0	t5,\$14,4
+0+0c70 <[^>]*> 418d7005 	mttc0	t5,\$14,5
+0+0c74 <[^>]*> 418d7006 	mttc0	t5,\$14,6
+0+0c78 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+0+0c7c <[^>]*> 418d7010 	mttr	t5,t6,0,0,1
+0+0c80 <[^>]*> 418d7011 	mttr	t5,t6,0,1,1
+0+0c84 <[^>]*> 418d7012 	mttr	t5,t6,0,2,1
+0+0c88 <[^>]*> 418d7013 	mttr	t5,t6,0,3,1
+0+0c8c <[^>]*> 418d7014 	mttr	t5,t6,0,4,1
+0+0c90 <[^>]*> 418d7015 	mttr	t5,t6,0,5,1
+0+0c94 <[^>]*> 418d7016 	mttr	t5,t6,0,6,1
+0+0c98 <[^>]*> 418d7017 	mttr	t5,t6,0,7,1
+0+0c9c <[^>]*> 418d7000 	mttc0	t5,c0_epc
+0+0ca0 <[^>]*> 418d7001 	mttc0	t5,\$14,1
+0+0ca4 <[^>]*> 418d7002 	mttc0	t5,\$14,2
+0+0ca8 <[^>]*> 418d7003 	mttc0	t5,\$14,3
+0+0cac <[^>]*> 418d7004 	mttc0	t5,\$14,4
+0+0cb0 <[^>]*> 418d7005 	mttc0	t5,\$14,5
+0+0cb4 <[^>]*> 418d7006 	mttc0	t5,\$14,6
+0+0cb8 <[^>]*> 418d7007 	mttc0	t5,\$14,7
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-mt.l b/gas/testsuite/gas/mips/mips32-mt.l
new file mode 100644
index 000000000000..a3f32f27de12
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-mt.l
@@ -0,0 +1,257 @@
+.*: Assembler messages:
+.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:568: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:569: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:570: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:571: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:572: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:573: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:574: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:575: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:576: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:577: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:578: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:579: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:580: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:581: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:582: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:583: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:584: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:585: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:586: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:587: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:588: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:589: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:590: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:591: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:592: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:592: Warning: MT immediate not in range 0..1 \(2\)
+.*:593: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:593: Warning: MT immediate not in range 0..1 \(2\)
+.*:594: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:594: Warning: MT immediate not in range 0..1 \(2\)
+.*:595: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:595: Warning: MT immediate not in range 0..1 \(2\)
+.*:596: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:596: Warning: MT immediate not in range 0..1 \(2\)
+.*:597: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:597: Warning: MT immediate not in range 0..1 \(2\)
+.*:598: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:598: Warning: MT immediate not in range 0..1 \(2\)
+.*:599: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:599: Warning: MT immediate not in range 0..1 \(2\)
+.*:600: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:601: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:602: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:603: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:604: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:605: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:606: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:607: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:624: Warning: MT immediate not in range 0..1 \(2\)
+.*:625: Warning: MT immediate not in range 0..1 \(2\)
+.*:626: Warning: MT immediate not in range 0..1 \(2\)
+.*:627: Warning: MT immediate not in range 0..1 \(2\)
+.*:628: Warning: MT immediate not in range 0..1 \(2\)
+.*:629: Warning: MT immediate not in range 0..1 \(2\)
+.*:630: Warning: MT immediate not in range 0..1 \(2\)
+.*:631: Warning: MT immediate not in range 0..1 \(2\)
+.*:632: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:633: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:634: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:635: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:636: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:637: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:638: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:639: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:656: Warning: MT immediate not in range 0..1 \(2\)
+.*:657: Warning: MT immediate not in range 0..1 \(2\)
+.*:658: Warning: MT immediate not in range 0..1 \(2\)
+.*:659: Warning: MT immediate not in range 0..1 \(2\)
+.*:660: Warning: MT immediate not in range 0..1 \(2\)
+.*:661: Warning: MT immediate not in range 0..1 \(2\)
+.*:662: Warning: MT immediate not in range 0..1 \(2\)
+.*:663: Warning: MT immediate not in range 0..1 \(2\)
+.*:664: Warning: MT immediate not in range 0..1 \(2\)
+.*:664: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:665: Warning: MT immediate not in range 0..1 \(2\)
+.*:665: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:666: Warning: MT immediate not in range 0..1 \(2\)
+.*:666: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:667: Warning: MT immediate not in range 0..1 \(2\)
+.*:667: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:668: Warning: MT immediate not in range 0..1 \(2\)
+.*:668: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:669: Warning: MT immediate not in range 0..1 \(2\)
+.*:669: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:670: Warning: MT immediate not in range 0..1 \(2\)
+.*:670: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:671: Warning: MT immediate not in range 0..1 \(2\)
+.*:671: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:672: Warning: MT immediate not in range 0..1 \(2\)
+.*:673: Warning: MT immediate not in range 0..1 \(2\)
+.*:674: Warning: MT immediate not in range 0..1 \(2\)
+.*:675: Warning: MT immediate not in range 0..1 \(2\)
+.*:676: Warning: MT immediate not in range 0..1 \(2\)
+.*:677: Warning: MT immediate not in range 0..1 \(2\)
+.*:678: Warning: MT immediate not in range 0..1 \(2\)
+.*:679: Warning: MT immediate not in range 0..1 \(2\)
+.*:680: Warning: MT immediate not in range 0..1 \(2\)
+.*:681: Warning: MT immediate not in range 0..1 \(2\)
+.*:682: Warning: MT immediate not in range 0..1 \(2\)
+.*:683: Warning: MT immediate not in range 0..1 \(2\)
+.*:684: Warning: MT immediate not in range 0..1 \(2\)
+.*:685: Warning: MT immediate not in range 0..1 \(2\)
+.*:686: Warning: MT immediate not in range 0..1 \(2\)
+.*:687: Warning: MT immediate not in range 0..1 \(2\)
+.*:688: Warning: MT immediate not in range 0..1 \(2\)
+.*:688: Warning: MT immediate not in range 0..1 \(2\)
+.*:689: Warning: MT immediate not in range 0..1 \(2\)
+.*:689: Warning: MT immediate not in range 0..1 \(2\)
+.*:690: Warning: MT immediate not in range 0..1 \(2\)
+.*:690: Warning: MT immediate not in range 0..1 \(2\)
+.*:691: Warning: MT immediate not in range 0..1 \(2\)
+.*:691: Warning: MT immediate not in range 0..1 \(2\)
+.*:692: Warning: MT immediate not in range 0..1 \(2\)
+.*:692: Warning: MT immediate not in range 0..1 \(2\)
+.*:693: Warning: MT immediate not in range 0..1 \(2\)
+.*:693: Warning: MT immediate not in range 0..1 \(2\)
+.*:694: Warning: MT immediate not in range 0..1 \(2\)
+.*:694: Warning: MT immediate not in range 0..1 \(2\)
+.*:695: Warning: MT immediate not in range 0..1 \(2\)
+.*:695: Warning: MT immediate not in range 0..1 \(2\)
+.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:696: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:697: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:698: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:699: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:700: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:701: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:702: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:703: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:704: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:705: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:706: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:707: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:708: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:709: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:710: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:711: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:712: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:713: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:714: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:715: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:716: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:717: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:718: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:719: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:720: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:720: Warning: MT immediate not in range 0..1 \(2\)
+.*:721: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:721: Warning: MT immediate not in range 0..1 \(2\)
+.*:722: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:722: Warning: MT immediate not in range 0..1 \(2\)
+.*:723: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:723: Warning: MT immediate not in range 0..1 \(2\)
+.*:724: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:724: Warning: MT immediate not in range 0..1 \(2\)
+.*:725: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:725: Warning: MT immediate not in range 0..1 \(2\)
+.*:726: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:726: Warning: MT immediate not in range 0..1 \(2\)
+.*:727: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:727: Warning: MT immediate not in range 0..1 \(2\)
+.*:728: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:729: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:730: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:731: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:732: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:733: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:734: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:735: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:752: Warning: MT immediate not in range 0..1 \(2\)
+.*:753: Warning: MT immediate not in range 0..1 \(2\)
+.*:754: Warning: MT immediate not in range 0..1 \(2\)
+.*:755: Warning: MT immediate not in range 0..1 \(2\)
+.*:756: Warning: MT immediate not in range 0..1 \(2\)
+.*:757: Warning: MT immediate not in range 0..1 \(2\)
+.*:758: Warning: MT immediate not in range 0..1 \(2\)
+.*:759: Warning: MT immediate not in range 0..1 \(2\)
+.*:760: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:761: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:762: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:763: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:764: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:765: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:766: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:767: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:784: Warning: MT immediate not in range 0..1 \(2\)
+.*:785: Warning: MT immediate not in range 0..1 \(2\)
+.*:786: Warning: MT immediate not in range 0..1 \(2\)
+.*:787: Warning: MT immediate not in range 0..1 \(2\)
+.*:788: Warning: MT immediate not in range 0..1 \(2\)
+.*:789: Warning: MT immediate not in range 0..1 \(2\)
+.*:790: Warning: MT immediate not in range 0..1 \(2\)
+.*:791: Warning: MT immediate not in range 0..1 \(2\)
+.*:792: Warning: MT immediate not in range 0..1 \(2\)
+.*:792: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:793: Warning: MT immediate not in range 0..1 \(2\)
+.*:793: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:794: Warning: MT immediate not in range 0..1 \(2\)
+.*:794: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:795: Warning: MT immediate not in range 0..1 \(2\)
+.*:795: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:796: Warning: MT immediate not in range 0..1 \(2\)
+.*:796: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:797: Warning: MT immediate not in range 0..1 \(2\)
+.*:797: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:798: Warning: MT immediate not in range 0..1 \(2\)
+.*:798: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:799: Warning: MT immediate not in range 0..1 \(2\)
+.*:799: Warning: MT immediate not in range 0..1 \([0-9]*\)
+.*:800: Warning: MT immediate not in range 0..1 \(2\)
+.*:801: Warning: MT immediate not in range 0..1 \(2\)
+.*:802: Warning: MT immediate not in range 0..1 \(2\)
+.*:803: Warning: MT immediate not in range 0..1 \(2\)
+.*:804: Warning: MT immediate not in range 0..1 \(2\)
+.*:805: Warning: MT immediate not in range 0..1 \(2\)
+.*:806: Warning: MT immediate not in range 0..1 \(2\)
+.*:807: Warning: MT immediate not in range 0..1 \(2\)
+.*:808: Warning: MT immediate not in range 0..1 \(2\)
+.*:809: Warning: MT immediate not in range 0..1 \(2\)
+.*:810: Warning: MT immediate not in range 0..1 \(2\)
+.*:811: Warning: MT immediate not in range 0..1 \(2\)
+.*:812: Warning: MT immediate not in range 0..1 \(2\)
+.*:813: Warning: MT immediate not in range 0..1 \(2\)
+.*:814: Warning: MT immediate not in range 0..1 \(2\)
+.*:815: Warning: MT immediate not in range 0..1 \(2\)
+.*:816: Warning: MT immediate not in range 0..1 \(2\)
+.*:816: Warning: MT immediate not in range 0..1 \(2\)
+.*:817: Warning: MT immediate not in range 0..1 \(2\)
+.*:817: Warning: MT immediate not in range 0..1 \(2\)
+.*:818: Warning: MT immediate not in range 0..1 \(2\)
+.*:818: Warning: MT immediate not in range 0..1 \(2\)
+.*:819: Warning: MT immediate not in range 0..1 \(2\)
+.*:819: Warning: MT immediate not in range 0..1 \(2\)
+.*:820: Warning: MT immediate not in range 0..1 \(2\)
+.*:820: Warning: MT immediate not in range 0..1 \(2\)
+.*:821: Warning: MT immediate not in range 0..1 \(2\)
+.*:821: Warning: MT immediate not in range 0..1 \(2\)
+.*:822: Warning: MT immediate not in range 0..1 \(2\)
+.*:822: Warning: MT immediate not in range 0..1 \(2\)
+.*:823: Warning: MT immediate not in range 0..1 \(2\)
+.*:823: Warning: MT immediate not in range 0..1 \(2\)
diff --git a/gas/testsuite/gas/mips/mips32-mt.s b/gas/testsuite/gas/mips/mips32-mt.s
new file mode 100644
index 000000000000..a3d8eeda0de3
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-mt.s
@@ -0,0 +1,826 @@
+# source file to test assembly of MIPS MT ASE for MIPS32 instructions
+
+	.set noreorder
+	.set noat
+
+	.text
+text_label:
+
+	dmt
+	dmt		$31
+	dvpe
+	dvpe		$1
+	emt
+	emt		$2
+	evpe
+	evpe		$3
+	fork		$4,$5,$6
+	yield		$5
+	yield		$6,$7
+	mftc0		$7,$8
+	mftc0		$8,$0,0
+	mftc0		$8,$0,1
+	mftc0		$8,$0,2
+	mftc0		$8,$0,3
+	mftc0		$8,$0,4
+	mftc0		$8,$0,5
+	mftc0		$8,$0,6
+	mftc0		$8,$0,7
+	mftc0		$8,$1,0
+	mftc0		$8,$1,1
+	mftc0		$8,$1,2
+	mftc0		$8,$1,3
+	mftc0		$8,$1,4
+	mftc0		$8,$1,5
+	mftc0		$8,$1,6
+	mftc0		$8,$1,7
+	mftc0		$8,$2,0
+	mftc0		$8,$2,1
+	mftc0		$8,$2,2
+	mftc0		$8,$2,3
+	mftc0		$8,$2,4
+	mftc0		$8,$2,5
+	mftc0		$8,$2,6
+	mftc0		$8,$2,7
+	mftc0		$8,$3,0
+	mftc0		$8,$3,1
+	mftc0		$8,$3,2
+	mftc0		$8,$3,3
+	mftc0		$8,$3,4
+	mftc0		$8,$3,5
+	mftc0		$8,$3,6
+	mftc0		$8,$3,7
+	mftc0		$8,$4,0
+	mftc0		$8,$4,1
+	mftc0		$8,$4,2
+	mftc0		$8,$4,3
+	mftc0		$8,$4,4
+	mftc0		$8,$4,5
+	mftc0		$8,$4,6
+	mftc0		$8,$4,7
+	mftc0		$8,$5,0
+	mftc0		$8,$5,1
+	mftc0		$8,$5,2
+	mftc0		$8,$5,3
+	mftc0		$8,$5,4
+	mftc0		$8,$5,5
+	mftc0		$8,$5,6
+	mftc0		$8,$5,7
+	mftc0		$8,$6,0
+	mftc0		$8,$6,1
+	mftc0		$8,$6,2
+	mftc0		$8,$6,3
+	mftc0		$8,$6,4
+	mftc0		$8,$6,5
+	mftc0		$8,$6,6
+	mftc0		$8,$6,7
+	mftc0		$8,$7,0
+	mftc0		$8,$7,1
+	mftc0		$8,$7,2
+	mftc0		$8,$7,3
+	mftc0		$8,$7,4
+	mftc0		$8,$7,5
+	mftc0		$8,$7,6
+	mftc0		$8,$7,7
+	mftc0		$8,$8,0
+	mftc0		$8,$8,1
+	mftc0		$8,$8,2
+	mftc0		$8,$8,3
+	mftc0		$8,$8,4
+	mftc0		$8,$8,5
+	mftc0		$8,$8,6
+	mftc0		$8,$8,7
+	mftc0		$8,$9,0
+	mftc0		$8,$9,1
+	mftc0		$8,$9,2
+	mftc0		$8,$9,3
+	mftc0		$8,$9,4
+	mftc0		$8,$9,5
+	mftc0		$8,$9,6
+	mftc0		$8,$9,7
+	mftc0		$8,$10,0
+	mftc0		$8,$10,1
+	mftc0		$8,$10,2
+	mftc0		$8,$10,3
+	mftc0		$8,$10,4
+	mftc0		$8,$10,5
+	mftc0		$8,$10,6
+	mftc0		$8,$10,7
+	mftc0		$8,$11,0
+	mftc0		$8,$11,1
+	mftc0		$8,$11,2
+	mftc0		$8,$11,3
+	mftc0		$8,$11,4
+	mftc0		$8,$11,5
+	mftc0		$8,$11,6
+	mftc0		$8,$11,7
+	mftc0		$8,$12,0
+	mftc0		$8,$12,1
+	mftc0		$8,$12,2
+	mftc0		$8,$12,3
+	mftc0		$8,$12,4
+	mftc0		$8,$12,5
+	mftc0		$8,$12,6
+	mftc0		$8,$12,7
+	mftc0		$8,$13,0
+	mftc0		$8,$13,1
+	mftc0		$8,$13,2
+	mftc0		$8,$13,3
+	mftc0		$8,$13,4
+	mftc0		$8,$13,5
+	mftc0		$8,$13,6
+	mftc0		$8,$13,7
+	mftc0		$8,$14,0
+	mftc0		$8,$14,1
+	mftc0		$8,$14,2
+	mftc0		$8,$14,3
+	mftc0		$8,$14,4
+	mftc0		$8,$14,5
+	mftc0		$8,$14,6
+	mftc0		$8,$14,7
+	mftc0		$8,$15,0
+	mftc0		$8,$15,1
+	mftc0		$8,$15,2
+	mftc0		$8,$15,3
+	mftc0		$8,$15,4
+	mftc0		$8,$15,5
+	mftc0		$8,$15,6
+	mftc0		$8,$15,7
+	mftc0		$8,$16,0
+	mftc0		$8,$16,1
+	mftc0		$8,$16,2
+	mftc0		$8,$16,3
+	mftc0		$8,$16,4
+	mftc0		$8,$16,5
+	mftc0		$8,$16,6
+	mftc0		$8,$16,7
+	mftc0		$8,$17,0
+	mftc0		$8,$17,1
+	mftc0		$8,$17,2
+	mftc0		$8,$17,3
+	mftc0		$8,$17,4
+	mftc0		$8,$17,5
+	mftc0		$8,$17,6
+	mftc0		$8,$17,7
+	mftc0		$8,$18,0
+	mftc0		$8,$18,1
+	mftc0		$8,$18,2
+	mftc0		$8,$18,3
+	mftc0		$8,$18,4
+	mftc0		$8,$18,5
+	mftc0		$8,$18,6
+	mftc0		$8,$18,7
+	mftc0		$8,$19,0
+	mftc0		$8,$19,1
+	mftc0		$8,$19,2
+	mftc0		$8,$19,3
+	mftc0		$8,$19,4
+	mftc0		$8,$19,5
+	mftc0		$8,$19,6
+	mftc0		$8,$19,7
+	mftc0		$8,$20,0
+	mftc0		$8,$20,1
+	mftc0		$8,$20,2
+	mftc0		$8,$20,3
+	mftc0		$8,$20,4
+	mftc0		$8,$20,5
+	mftc0		$8,$20,6
+	mftc0		$8,$20,7
+	mftc0		$8,$21,0
+	mftc0		$8,$21,1
+	mftc0		$8,$21,2
+	mftc0		$8,$21,3
+	mftc0		$8,$21,4
+	mftc0		$8,$21,5
+	mftc0		$8,$21,6
+	mftc0		$8,$21,7
+	mftc0		$8,$22,0
+	mftc0		$8,$22,1
+	mftc0		$8,$22,2
+	mftc0		$8,$22,3
+	mftc0		$8,$22,4
+	mftc0		$8,$22,5
+	mftc0		$8,$22,6
+	mftc0		$8,$22,7
+	mftc0		$8,$23,0
+	mftc0		$8,$23,1
+	mftc0		$8,$23,2
+	mftc0		$8,$23,3
+	mftc0		$8,$23,4
+	mftc0		$8,$23,5
+	mftc0		$8,$23,6
+	mftc0		$8,$23,7
+	mftc0		$8,$24,0
+	mftc0		$8,$24,1
+	mftc0		$8,$24,2
+	mftc0		$8,$24,3
+	mftc0		$8,$24,4
+	mftc0		$8,$24,5
+	mftc0		$8,$24,6
+	mftc0		$8,$24,7
+	mftc0		$8,$25,0
+	mftc0		$8,$25,1
+	mftc0		$8,$25,2
+	mftc0		$8,$25,3
+	mftc0		$8,$25,4
+	mftc0		$8,$25,5
+	mftc0		$8,$25,6
+	mftc0		$8,$25,7
+	mftc0		$8,$26,0
+	mftc0		$8,$26,1
+	mftc0		$8,$26,2
+	mftc0		$8,$26,3
+	mftc0		$8,$26,4
+	mftc0		$8,$26,5
+	mftc0		$8,$26,6
+	mftc0		$8,$26,7
+	mftc0		$8,$27,0
+	mftc0		$8,$27,1
+	mftc0		$8,$27,2
+	mftc0		$8,$27,3
+	mftc0		$8,$27,4
+	mftc0		$8,$27,5
+	mftc0		$8,$27,6
+	mftc0		$8,$27,7
+	mftc0		$8,$28,0
+	mftc0		$8,$28,1
+	mftc0		$8,$28,2
+	mftc0		$8,$28,3
+	mftc0		$8,$28,4
+	mftc0		$8,$28,5
+	mftc0		$8,$28,6
+	mftc0		$8,$28,7
+	mftc0		$8,$29,0
+	mftc0		$8,$29,1
+	mftc0		$8,$29,2
+	mftc0		$8,$29,3
+	mftc0		$8,$29,4
+	mftc0		$8,$29,5
+	mftc0		$8,$29,6
+	mftc0		$8,$29,7
+	mftc0		$8,$30,0
+	mftc0		$8,$30,1
+	mftc0		$8,$30,2
+	mftc0		$8,$30,3
+	mftc0		$8,$30,4
+	mftc0		$8,$30,5
+	mftc0		$8,$30,6
+	mftc0		$8,$30,7
+	mftc0		$8,$31,0
+	mftc0		$8,$31,1
+	mftc0		$8,$31,2
+	mftc0		$8,$31,3
+	mftc0		$8,$31,4
+	mftc0		$8,$31,5
+	mftc0		$8,$31,6
+	mftc0		$8,$31,7
+	mftgpr		$9,$10
+	mftlo		$10
+	mftlo		$11,$ac0
+	mfthi		$12
+	mfthi		$13,$ac1
+	mftacx		$14
+	mftacx		$15,$ac2
+	mftdsp		$16
+	mftc1		$17,$f18
+	mftc1		$18,$19
+	mfthc1		$19,$f20
+	mfthc1		$20,$22
+	cftc1		$21,$22
+	cftc1		$22,$f23
+	mftc2		$23,$24
+	mfthc2		$24,$25
+	cftc2		$25,$26
+	mttc0		$26,$27
+	mttc0		$27,$0,0
+	mttc0		$27,$0,1
+	mttc0		$27,$0,2
+	mttc0		$27,$0,3
+	mttc0		$27,$0,4
+	mttc0		$27,$0,5
+	mttc0		$27,$0,6
+	mttc0		$27,$0,7
+	mttc0		$27,$1,0
+	mttc0		$27,$1,1
+	mttc0		$27,$1,2
+	mttc0		$27,$1,3
+	mttc0		$27,$1,4
+	mttc0		$27,$1,5
+	mttc0		$27,$1,6
+	mttc0		$27,$1,7
+	mttc0		$27,$2,0
+	mttc0		$27,$2,1
+	mttc0		$27,$2,2
+	mttc0		$27,$2,3
+	mttc0		$27,$2,4
+	mttc0		$27,$2,5
+	mttc0		$27,$2,6
+	mttc0		$27,$2,7
+	mttc0		$27,$3,0
+	mttc0		$27,$3,1
+	mttc0		$27,$3,2
+	mttc0		$27,$3,3
+	mttc0		$27,$3,4
+	mttc0		$27,$3,5
+	mttc0		$27,$3,6
+	mttc0		$27,$3,7
+	mttc0		$27,$4,0
+	mttc0		$27,$4,1
+	mttc0		$27,$4,2
+	mttc0		$27,$4,3
+	mttc0		$27,$4,4
+	mttc0		$27,$4,5
+	mttc0		$27,$4,6
+	mttc0		$27,$4,7
+	mttc0		$27,$5,0
+	mttc0		$27,$5,1
+	mttc0		$27,$5,2
+	mttc0		$27,$5,3
+	mttc0		$27,$5,4
+	mttc0		$27,$5,5
+	mttc0		$27,$5,6
+	mttc0		$27,$5,7
+	mttc0		$27,$6,0
+	mttc0		$27,$6,1
+	mttc0		$27,$6,2
+	mttc0		$27,$6,3
+	mttc0		$27,$6,4
+	mttc0		$27,$6,5
+	mttc0		$27,$6,6
+	mttc0		$27,$6,7
+	mttc0		$27,$7,0
+	mttc0		$27,$7,1
+	mttc0		$27,$7,2
+	mttc0		$27,$7,3
+	mttc0		$27,$7,4
+	mttc0		$27,$7,5
+	mttc0		$27,$7,6
+	mttc0		$27,$7,7
+	mttc0		$27,$8,0
+	mttc0		$27,$8,1
+	mttc0		$27,$8,2
+	mttc0		$27,$8,3
+	mttc0		$27,$8,4
+	mttc0		$27,$8,5
+	mttc0		$27,$8,6
+	mttc0		$27,$8,7
+	mttc0		$27,$9,0
+	mttc0		$27,$9,1
+	mttc0		$27,$9,2
+	mttc0		$27,$9,3
+	mttc0		$27,$9,4
+	mttc0		$27,$9,5
+	mttc0		$27,$9,6
+	mttc0		$27,$9,7
+	mttc0		$27,$10,0
+	mttc0		$27,$10,1
+	mttc0		$27,$10,2
+	mttc0		$27,$10,3
+	mttc0		$27,$10,4
+	mttc0		$27,$10,5
+	mttc0		$27,$10,6
+	mttc0		$27,$10,7
+	mttc0		$27,$11,0
+	mttc0		$27,$11,1
+	mttc0		$27,$11,2
+	mttc0		$27,$11,3
+	mttc0		$27,$11,4
+	mttc0		$27,$11,5
+	mttc0		$27,$11,6
+	mttc0		$27,$11,7
+	mttc0		$27,$12,0
+	mttc0		$27,$12,1
+	mttc0		$27,$12,2
+	mttc0		$27,$12,3
+	mttc0		$27,$12,4
+	mttc0		$27,$12,5
+	mttc0		$27,$12,6
+	mttc0		$27,$12,7
+	mttc0		$27,$13,0
+	mttc0		$27,$13,1
+	mttc0		$27,$13,2
+	mttc0		$27,$13,3
+	mttc0		$27,$13,4
+	mttc0		$27,$13,5
+	mttc0		$27,$13,6
+	mttc0		$27,$13,7
+	mttc0		$27,$14,0
+	mttc0		$27,$14,1
+	mttc0		$27,$14,2
+	mttc0		$27,$14,3
+	mttc0		$27,$14,4
+	mttc0		$27,$14,5
+	mttc0		$27,$14,6
+	mttc0		$27,$14,7
+	mttc0		$27,$15,0
+	mttc0		$27,$15,1
+	mttc0		$27,$15,2
+	mttc0		$27,$15,3
+	mttc0		$27,$15,4
+	mttc0		$27,$15,5
+	mttc0		$27,$15,6
+	mttc0		$27,$15,7
+	mttc0		$27,$16,0
+	mttc0		$27,$16,1
+	mttc0		$27,$16,2
+	mttc0		$27,$16,3
+	mttc0		$27,$16,4
+	mttc0		$27,$16,5
+	mttc0		$27,$16,6
+	mttc0		$27,$16,7
+	mttc0		$27,$17,0
+	mttc0		$27,$17,1
+	mttc0		$27,$17,2
+	mttc0		$27,$17,3
+	mttc0		$27,$17,4
+	mttc0		$27,$17,5
+	mttc0		$27,$17,6
+	mttc0		$27,$17,7
+	mttc0		$27,$18,0
+	mttc0		$27,$18,1
+	mttc0		$27,$18,2
+	mttc0		$27,$18,3
+	mttc0		$27,$18,4
+	mttc0		$27,$18,5
+	mttc0		$27,$18,6
+	mttc0		$27,$18,7
+	mttc0		$27,$19,0
+	mttc0		$27,$19,1
+	mttc0		$27,$19,2
+	mttc0		$27,$19,3
+	mttc0		$27,$19,4
+	mttc0		$27,$19,5
+	mttc0		$27,$19,6
+	mttc0		$27,$19,7
+	mttc0		$27,$20,0
+	mttc0		$27,$20,1
+	mttc0		$27,$20,2
+	mttc0		$27,$20,3
+	mttc0		$27,$20,4
+	mttc0		$27,$20,5
+	mttc0		$27,$20,6
+	mttc0		$27,$20,7
+	mttc0		$27,$21,0
+	mttc0		$27,$21,1
+	mttc0		$27,$21,2
+	mttc0		$27,$21,3
+	mttc0		$27,$21,4
+	mttc0		$27,$21,5
+	mttc0		$27,$21,6
+	mttc0		$27,$21,7
+	mttc0		$27,$22,0
+	mttc0		$27,$22,1
+	mttc0		$27,$22,2
+	mttc0		$27,$22,3
+	mttc0		$27,$22,4
+	mttc0		$27,$22,5
+	mttc0		$27,$22,6
+	mttc0		$27,$22,7
+	mttc0		$27,$23,0
+	mttc0		$27,$23,1
+	mttc0		$27,$23,2
+	mttc0		$27,$23,3
+	mttc0		$27,$23,4
+	mttc0		$27,$23,5
+	mttc0		$27,$23,6
+	mttc0		$27,$23,7
+	mttc0		$27,$24,0
+	mttc0		$27,$24,1
+	mttc0		$27,$24,2
+	mttc0		$27,$24,3
+	mttc0		$27,$24,4
+	mttc0		$27,$24,5
+	mttc0		$27,$24,6
+	mttc0		$27,$24,7
+	mttc0		$27,$25,0
+	mttc0		$27,$25,1
+	mttc0		$27,$25,2
+	mttc0		$27,$25,3
+	mttc0		$27,$25,4
+	mttc0		$27,$25,5
+	mttc0		$27,$25,6
+	mttc0		$27,$25,7
+	mttc0		$27,$26,0
+	mttc0		$27,$26,1
+	mttc0		$27,$26,2
+	mttc0		$27,$26,3
+	mttc0		$27,$26,4
+	mttc0		$27,$26,5
+	mttc0		$27,$26,6
+	mttc0		$27,$26,7
+	mttc0		$27,$27,0
+	mttc0		$27,$27,1
+	mttc0		$27,$27,2
+	mttc0		$27,$27,3
+	mttc0		$27,$27,4
+	mttc0		$27,$27,5
+	mttc0		$27,$27,6
+	mttc0		$27,$27,7
+	mttc0		$27,$28,0
+	mttc0		$27,$28,1
+	mttc0		$27,$28,2
+	mttc0		$27,$28,3
+	mttc0		$27,$28,4
+	mttc0		$27,$28,5
+	mttc0		$27,$28,6
+	mttc0		$27,$28,7
+	mttc0		$27,$29,0
+	mttc0		$27,$29,1
+	mttc0		$27,$29,2
+	mttc0		$27,$29,3
+	mttc0		$27,$29,4
+	mttc0		$27,$29,5
+	mttc0		$27,$29,6
+	mttc0		$27,$29,7
+	mttc0		$27,$30,0
+	mttc0		$27,$30,1
+	mttc0		$27,$30,2
+	mttc0		$27,$30,3
+	mttc0		$27,$30,4
+	mttc0		$27,$30,5
+	mttc0		$27,$30,6
+	mttc0		$27,$30,7
+	mttc0		$27,$31,0
+	mttc0		$27,$31,1
+	mttc0		$27,$31,2
+	mttc0		$27,$31,3
+	mttc0		$27,$31,4
+	mttc0		$27,$31,5
+	mttc0		$27,$31,6
+	mttc0		$27,$31,7
+	mttgpr		$28,$29
+	mttlo		$29
+	mttlo		$30,$ac3
+	mtthi		$31
+	mtthi		$0,$ac0
+	mttacx		$1
+	mttacx		$2,$ac1
+	mttdsp		$3
+	mttc1		$4,$f5
+	mttc1		$5,$6
+	mtthc1		$6,$f8
+	mtthc1		$7,$10
+	cttc1		$8,$9
+	cttc1		$9,$f10
+	mttc2		$10,$11
+	mtthc2		$11,$12
+	cttc2		$12,$13
+	mftr		$13,$14,-1,0,-1
+	mftr		$13,$14,-1,1,-1
+	mftr		$13,$14,-1,2,-1
+	mftr		$13,$14,-1,3,-1
+	mftr		$13,$14,-1,4,-1
+	mftr		$13,$14,-1,5,-1
+	mftr		$13,$14,-1,6,-1
+	mftr		$13,$14,-1,7,-1
+	mftr		$13,$14,-1,0,0
+	mftr		$13,$14,-1,1,0
+	mftr		$13,$14,-1,2,0
+	mftr		$13,$14,-1,3,0
+	mftr		$13,$14,-1,4,0
+	mftr		$13,$14,-1,5,0
+	mftr		$13,$14,-1,6,0
+	mftr		$13,$14,-1,7,0
+	mftr		$13,$14,-1,0,1
+	mftr		$13,$14,-1,1,1
+	mftr		$13,$14,-1,2,1
+	mftr		$13,$14,-1,3,1
+	mftr		$13,$14,-1,4,1
+	mftr		$13,$14,-1,5,1
+	mftr		$13,$14,-1,6,1
+	mftr		$13,$14,-1,7,1
+	mftr		$13,$14,-1,0,2
+	mftr		$13,$14,-1,1,2
+	mftr		$13,$14,-1,2,2
+	mftr		$13,$14,-1,3,2
+	mftr		$13,$14,-1,4,2
+	mftr		$13,$14,-1,5,2
+	mftr		$13,$14,-1,6,2
+	mftr		$13,$14,-1,7,2
+	mftr		$13,$14,0,0,-1
+	mftr		$13,$14,0,1,-1
+	mftr		$13,$14,0,2,-1
+	mftr		$13,$14,0,3,-1
+	mftr		$13,$14,0,4,-1
+	mftr		$13,$14,0,5,-1
+	mftr		$13,$14,0,6,-1
+	mftr		$13,$14,0,7,-1
+	mftr		$13,$14,0,0,0
+	mftr		$13,$14,0,1,0
+	mftr		$13,$14,0,2,0
+	mftr		$13,$14,0,3,0
+	mftr		$13,$14,0,4,0
+	mftr		$13,$14,0,5,0
+	mftr		$13,$14,0,6,0
+	mftr		$13,$14,0,7,0
+	mftr		$13,$14,0,0,1
+	mftr		$13,$14,0,1,1
+	mftr		$13,$14,0,2,1
+	mftr		$13,$14,0,3,1
+	mftr		$13,$14,0,4,1
+	mftr		$13,$14,0,5,1
+	mftr		$13,$14,0,6,1
+	mftr		$13,$14,0,7,1
+	mftr		$13,$14,0,0,2
+	mftr		$13,$14,0,1,2
+	mftr		$13,$14,0,2,2
+	mftr		$13,$14,0,3,2
+	mftr		$13,$14,0,4,2
+	mftr		$13,$14,0,5,2
+	mftr		$13,$14,0,6,2
+	mftr		$13,$14,0,7,2
+	mftr		$13,$14,1,0,-1
+	mftr		$13,$14,1,1,-1
+	mftr		$13,$14,1,2,-1
+	mftr		$13,$14,1,3,-1
+	mftr		$13,$14,1,4,-1
+	mftr		$13,$14,1,5,-1
+	mftr		$13,$14,1,6,-1
+	mftr		$13,$14,1,7,-1
+	mftr		$13,$14,1,0,0
+	mftr		$13,$14,1,1,0
+	mftr		$13,$14,1,2,0
+	mftr		$13,$14,1,3,0
+	mftr		$13,$14,1,4,0
+	mftr		$13,$14,1,5,0
+	mftr		$13,$14,1,6,0
+	mftr		$13,$14,1,7,0
+	mftr		$13,$14,1,0,1
+	mftr		$13,$14,1,1,1
+	mftr		$13,$14,1,2,1
+	mftr		$13,$14,1,3,1
+	mftr		$13,$14,1,4,1
+	mftr		$13,$14,1,5,1
+	mftr		$13,$14,1,6,1
+	mftr		$13,$14,1,7,1
+	mftr		$13,$14,1,0,2
+	mftr		$13,$14,1,1,2
+	mftr		$13,$14,1,2,2
+	mftr		$13,$14,1,3,2
+	mftr		$13,$14,1,4,2
+	mftr		$13,$14,1,5,2
+	mftr		$13,$14,1,6,2
+	mftr		$13,$14,1,7,2
+	mftr		$13,$14,2,0,-1
+	mftr		$13,$14,2,1,-1
+	mftr		$13,$14,2,2,-1
+	mftr		$13,$14,2,3,-1
+	mftr		$13,$14,2,4,-1
+	mftr		$13,$14,2,5,-1
+	mftr		$13,$14,2,6,-1
+	mftr		$13,$14,2,7,-1
+	mftr		$13,$14,2,0,0
+	mftr		$13,$14,2,1,0
+	mftr		$13,$14,2,2,0
+	mftr		$13,$14,2,3,0
+	mftr		$13,$14,2,4,0
+	mftr		$13,$14,2,5,0
+	mftr		$13,$14,2,6,0
+	mftr		$13,$14,2,7,0
+	mftr		$13,$14,2,0,1
+	mftr		$13,$14,2,1,1
+	mftr		$13,$14,2,2,1
+	mftr		$13,$14,2,3,1
+	mftr		$13,$14,2,4,1
+	mftr		$13,$14,2,5,1
+	mftr		$13,$14,2,6,1
+	mftr		$13,$14,2,7,1
+	mftr		$13,$14,2,0,2
+	mftr		$13,$14,2,1,2
+	mftr		$13,$14,2,2,2
+	mftr		$13,$14,2,3,2
+	mftr		$13,$14,2,4,2
+	mftr		$13,$14,2,5,2
+	mftr		$13,$14,2,6,2
+	mftr		$13,$14,2,7,2
+	mttr		$13,$14,-1,0,-1
+	mttr		$13,$14,-1,1,-1
+	mttr		$13,$14,-1,2,-1
+	mttr		$13,$14,-1,3,-1
+	mttr		$13,$14,-1,4,-1
+	mttr		$13,$14,-1,5,-1
+	mttr		$13,$14,-1,6,-1
+	mttr		$13,$14,-1,7,-1
+	mttr		$13,$14,-1,0,0
+	mttr		$13,$14,-1,1,0
+	mttr		$13,$14,-1,2,0
+	mttr		$13,$14,-1,3,0
+	mttr		$13,$14,-1,4,0
+	mttr		$13,$14,-1,5,0
+	mttr		$13,$14,-1,6,0
+	mttr		$13,$14,-1,7,0
+	mttr		$13,$14,-1,0,1
+	mttr		$13,$14,-1,1,1
+	mttr		$13,$14,-1,2,1
+	mttr		$13,$14,-1,3,1
+	mttr		$13,$14,-1,4,1
+	mttr		$13,$14,-1,5,1
+	mttr		$13,$14,-1,6,1
+	mttr		$13,$14,-1,7,1
+	mttr		$13,$14,-1,0,2
+	mttr		$13,$14,-1,1,2
+	mttr		$13,$14,-1,2,2
+	mttr		$13,$14,-1,3,2
+	mttr		$13,$14,-1,4,2
+	mttr		$13,$14,-1,5,2
+	mttr		$13,$14,-1,6,2
+	mttr		$13,$14,-1,7,2
+	mttr		$13,$14,0,0,-1
+	mttr		$13,$14,0,1,-1
+	mttr		$13,$14,0,2,-1
+	mttr		$13,$14,0,3,-1
+	mttr		$13,$14,0,4,-1
+	mttr		$13,$14,0,5,-1
+	mttr		$13,$14,0,6,-1
+	mttr		$13,$14,0,7,-1
+	mttr		$13,$14,0,0,0
+	mttr		$13,$14,0,1,0
+	mttr		$13,$14,0,2,0
+	mttr		$13,$14,0,3,0
+	mttr		$13,$14,0,4,0
+	mttr		$13,$14,0,5,0
+	mttr		$13,$14,0,6,0
+	mttr		$13,$14,0,7,0
+	mttr		$13,$14,0,0,1
+	mttr		$13,$14,0,1,1
+	mttr		$13,$14,0,2,1
+	mttr		$13,$14,0,3,1
+	mttr		$13,$14,0,4,1
+	mttr		$13,$14,0,5,1
+	mttr		$13,$14,0,6,1
+	mttr		$13,$14,0,7,1
+	mttr		$13,$14,0,0,2
+	mttr		$13,$14,0,1,2
+	mttr		$13,$14,0,2,2
+	mttr		$13,$14,0,3,2
+	mttr		$13,$14,0,4,2
+	mttr		$13,$14,0,5,2
+	mttr		$13,$14,0,6,2
+	mttr		$13,$14,0,7,2
+	mttr		$13,$14,1,0,-1
+	mttr		$13,$14,1,1,-1
+	mttr		$13,$14,1,2,-1
+	mttr		$13,$14,1,3,-1
+	mttr		$13,$14,1,4,-1
+	mttr		$13,$14,1,5,-1
+	mttr		$13,$14,1,6,-1
+	mttr		$13,$14,1,7,-1
+	mttr		$13,$14,1,0,0
+	mttr		$13,$14,1,1,0
+	mttr		$13,$14,1,2,0
+	mttr		$13,$14,1,3,0
+	mttr		$13,$14,1,4,0
+	mttr		$13,$14,1,5,0
+	mttr		$13,$14,1,6,0
+	mttr		$13,$14,1,7,0
+	mttr		$13,$14,1,0,1
+	mttr		$13,$14,1,1,1
+	mttr		$13,$14,1,2,1
+	mttr		$13,$14,1,3,1
+	mttr		$13,$14,1,4,1
+	mttr		$13,$14,1,5,1
+	mttr		$13,$14,1,6,1
+	mttr		$13,$14,1,7,1
+	mttr		$13,$14,1,0,2
+	mttr		$13,$14,1,1,2
+	mttr		$13,$14,1,2,2
+	mttr		$13,$14,1,3,2
+	mttr		$13,$14,1,4,2
+	mttr		$13,$14,1,5,2
+	mttr		$13,$14,1,6,2
+	mttr		$13,$14,1,7,2
+	mttr		$13,$14,2,0,-1
+	mttr		$13,$14,2,1,-1
+	mttr		$13,$14,2,2,-1
+	mttr		$13,$14,2,3,-1
+	mttr		$13,$14,2,4,-1
+	mttr		$13,$14,2,5,-1
+	mttr		$13,$14,2,6,-1
+	mttr		$13,$14,2,7,-1
+	mttr		$13,$14,2,0,0
+	mttr		$13,$14,2,1,0
+	mttr		$13,$14,2,2,0
+	mttr		$13,$14,2,3,0
+	mttr		$13,$14,2,4,0
+	mttr		$13,$14,2,5,0
+	mttr		$13,$14,2,6,0
+	mttr		$13,$14,2,7,0
+	mttr		$13,$14,2,0,1
+	mttr		$13,$14,2,1,1
+	mttr		$13,$14,2,2,1
+	mttr		$13,$14,2,3,1
+	mttr		$13,$14,2,4,1
+	mttr		$13,$14,2,5,1
+	mttr		$13,$14,2,6,1
+	mttr		$13,$14,2,7,1
+	mttr		$13,$14,2,0,2
+	mttr		$13,$14,2,1,2
+	mttr		$13,$14,2,2,2
+	mttr		$13,$14,2,3,2
+	mttr		$13,$14,2,4,2
+	mttr		$13,$14,2,5,2
+	mttr		$13,$14,2,6,2
+	mttr		$13,$14,2,7,2
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8
diff --git a/gas/testsuite/gas/mips/mips32.d b/gas/testsuite/gas/mips/mips32.d
index 503a3e533113..cb226d8f43b0 100644
--- a/gas/testsuite/gas/mips/mips32.d
+++ b/gas/testsuite/gas/mips/mips32.d
@@ -48,8 +48,9 @@ Disassembly of section .text:
 0+0098 <[^>]*> 4359e260 	wait	0x56789
 0+009c <[^>]*> 0000000d 	break
 0+00a0 <[^>]*> 0000000d 	break
-0+00a4 <[^>]*> 0048d14d 	break	0x12345
-0+00a8 <[^>]*> 7000003f 	sdbbp
+0+00a4 <[^>]*> 0345000d 	break	0x345
+0+00a8 <[^>]*> 0048d14d 	break	0x48,0x345
 0+00ac <[^>]*> 7000003f 	sdbbp
-0+00b0 <[^>]*> 7159e27f 	sdbbp	0x56789
+0+00b0 <[^>]*> 7000003f 	sdbbp
+0+00b4 <[^>]*> 7159e27f 	sdbbp	0x56789
 	...
diff --git a/gas/testsuite/gas/mips/mips32.s b/gas/testsuite/gas/mips/mips32.s
index 17c65f083c61..b3fb6fe13bf6 100644
--- a/gas/testsuite/gas/mips/mips32.s
+++ b/gas/testsuite/gas/mips/mips32.s
@@ -58,11 +58,17 @@ text_label:
       wait    0                       # disassembles without code
       wait    0x56789
 
-      # Instructions in previous ISAs or CPUs which are now slightly
-      # different.
+      # For a while break for the mips32 ISA interpreted a single argument
+      # as a 20-bit code, placing it in the opcode differently to
+      # traditional ISAs.  This turned out to cause problems, so it has
+      # been removed.  This test is to assure consistent interpretation.
       break
       break   0                       # disassembles without code
-      break   0x12345
+      break   0x345
+      break   0x48,0x345              # this still specifies a 20-bit code
+
+      # Instructions in previous ISAs or CPUs which are now slightly
+      # different.
       sdbbp
       sdbbp   0                       # disassembles without code
       sdbbp   0x56789
diff --git a/gas/testsuite/gas/mips/noat-1.d b/gas/testsuite/gas/mips/noat-1.d
new file mode 100644
index 000000000000..560fb303b96c
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-1.d
@@ -0,0 +1,15 @@
+#as: -32 -mips1
+#objdump: -dr
+
+.*: +file format .*mips
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	8f7b7fff 	lw	k1,32767\(k1\)
+   4:	00000000 	nop
+   8:	8f7b8000 	lw	k1,-32768\(k1\)
+   c:	00000000 	nop
+  10:	af7b7fff 	sw	k1,32767\(k1\)
+  14:	af7b8000 	sw	k1,-32768\(k1\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/noat-1.s b/gas/testsuite/gas/mips/noat-1.s
new file mode 100644
index 000000000000..d58ac3e65dde
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-1.s
@@ -0,0 +1,7 @@
+	.set noat
+	lw $27, 0x7fff($27)
+	lw $27, -0x8000($27)
+	sw $27, 0x7fff($27)
+	sw $27, -0x8000($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-2.l b/gas/testsuite/gas/mips/noat-2.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-2.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-2.s b/gas/testsuite/gas/mips/noat-2.s
new file mode 100644
index 000000000000..8e1a449d127a
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-2.s
@@ -0,0 +1,4 @@
+	.set noat
+	lw $27, 0x8000($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-3.l b/gas/testsuite/gas/mips/noat-3.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-3.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-3.s b/gas/testsuite/gas/mips/noat-3.s
new file mode 100644
index 000000000000..dcf1dc0d689c
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-3.s
@@ -0,0 +1,4 @@
+	.set noat
+	lw $27, -0x8001($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-4.l b/gas/testsuite/gas/mips/noat-4.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-4.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-4.s b/gas/testsuite/gas/mips/noat-4.s
new file mode 100644
index 000000000000..0bb772e41153
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-4.s
@@ -0,0 +1,4 @@
+	.set noat
+	lw $27, symbol($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-5.l b/gas/testsuite/gas/mips/noat-5.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-5.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-5.s b/gas/testsuite/gas/mips/noat-5.s
new file mode 100644
index 000000000000..9d8404502837
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-5.s
@@ -0,0 +1,4 @@
+	.set noat
+	sw $27, 0x8000($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-6.l b/gas/testsuite/gas/mips/noat-6.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-6.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-6.s b/gas/testsuite/gas/mips/noat-6.s
new file mode 100644
index 000000000000..5e2c0337329b
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-6.s
@@ -0,0 +1,4 @@
+	.set noat
+	sw $27, -0x8001($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/noat-7.l b/gas/testsuite/gas/mips/noat-7.l
new file mode 100644
index 000000000000..33402370e4cc
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-7.l
@@ -0,0 +1,2 @@
+.*\.s: Assembler messages:
+.*\.s:2: Error: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/noat-7.s b/gas/testsuite/gas/mips/noat-7.s
new file mode 100644
index 000000000000..3dc23505fd38
--- /dev/null
+++ b/gas/testsuite/gas/mips/noat-7.s
@@ -0,0 +1,4 @@
+	.set noat
+	sw $27, symbol($27)
+
+	.space 8
diff --git a/gas/testsuite/gas/mips/relax-swap1-mips1.d b/gas/testsuite/gas/mips/relax-swap1-mips1.d
index 772300b49fa6..4a0f7b35e14e 100644
--- a/gas/testsuite/gas/mips/relax-swap1-mips1.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips1.d
@@ -12,7 +12,7 @@ Disassembly of section \.text:
 0+0008 <[^>]*> lw	at,2\(gp\)
 [ 	]*8: R_MIPS_GOT16	\.text
 0+000c <[^>]*> nop
-0+0010 <[^>]*> addiu	at,at,1000
+0+0010 <[^>]*> addiu	at,at,992
 [ 	]*10: R_MIPS_LO16	\.text
 0+0014 <[^>]*> jr	at
 0+0018 <[^>]*> move	v0,a0
@@ -23,7 +23,7 @@ Disassembly of section \.text:
 0+002c <[^>]*> lw	at,2\(gp\)
 [ 	]*2c: R_MIPS_GOT16	\.text
 0+0030 <[^>]*> nop
-0+0034 <[^>]*> addiu	at,at,1000
+0+0034 <[^>]*> addiu	at,at,992
 [ 	]*34: R_MIPS_LO16	\.text
 0+0038 <[^>]*> jr	at
 0+003c <[^>]*> nop
@@ -32,7 +32,7 @@ Disassembly of section \.text:
 0+0048 <[^>]*> lw	at,2\(gp\)
 [ 	]*48: R_MIPS_GOT16	\.text
 0+004c <[^>]*> nop
-0+0050 <[^>]*> addiu	at,at,1000
+0+0050 <[^>]*> addiu	at,at,992
 [ 	]*50: R_MIPS_LO16	\.text
 0+0054 <[^>]*> jr	at
 0+0058 <[^>]*> sw	v0,0\(a0\)
@@ -45,7 +45,7 @@ Disassembly of section \.text:
 0+0074 <[^>]*> lw	at,2\(gp\)
 [ 	]*74: R_MIPS_GOT16	\.text
 0+0078 <[^>]*> nop
-0+007c <[^>]*> addiu	at,at,1000
+0+007c <[^>]*> addiu	at,at,992
 [ 	]*7c: R_MIPS_LO16	\.text
 0+0080 <[^>]*> jr	at
 0+0084 <[^>]*> nop
@@ -56,7 +56,7 @@ Disassembly of section \.text:
 0+0098 <[^>]*> lw	at,2\(gp\)
 [ 	]*98: R_MIPS_GOT16	\.text
 0+009c <[^>]*> nop
-0+00a0 <[^>]*> addiu	at,at,1000
+0+00a0 <[^>]*> addiu	at,at,992
 [ 	]*a0: R_MIPS_LO16	\.text
 0+00a4 <[^>]*> jr	at
 0+00a8 <[^>]*> move	v0,a0
@@ -69,7 +69,7 @@ Disassembly of section \.text:
 0+00c4 <[^>]*> lw	at,2\(gp\)
 [ 	]*c4: R_MIPS_GOT16	\.text
 0+00c8 <[^>]*> nop
-0+00cc <[^>]*> addiu	at,at,1000
+0+00cc <[^>]*> addiu	at,at,992
 [ 	]*cc: R_MIPS_LO16	\.text
 0+00d0 <[^>]*> jr	at
 0+00d4 <[^>]*> nop
@@ -80,7 +80,7 @@ Disassembly of section \.text:
 0+00e8 <[^>]*> lw	at,2\(gp\)
 [ 	]*e8: R_MIPS_GOT16	\.text
 0+00ec <[^>]*> nop
-0+00f0 <[^>]*> addiu	at,at,1000
+0+00f0 <[^>]*> addiu	at,at,992
 [ 	]*f0: R_MIPS_LO16	\.text
 0+00f4 <[^>]*> jr	at
 0+00f8 <[^>]*> addiu	v0,a0,1
@@ -95,7 +95,7 @@ Disassembly of section \.text:
 0+011c <[^>]*> lw	at,2\(gp\)
 [ 	]*11c: R_MIPS_GOT16	\.text
 0+0120 <[^>]*> nop
-0+0124 <[^>]*> addiu	at,at,1000
+0+0124 <[^>]*> addiu	at,at,992
 [ 	]*124: R_MIPS_LO16	\.text
 0+0128 <[^>]*> jr	at
 0+012c <[^>]*> nop
@@ -108,7 +108,7 @@ Disassembly of section \.text:
 0+0148 <[^>]*> lw	at,2\(gp\)
 [ 	]*148: R_MIPS_GOT16	\.text
 0+014c <[^>]*> nop
-0+0150 <[^>]*> addiu	at,at,1000
+0+0150 <[^>]*> addiu	at,at,992
 [ 	]*150: R_MIPS_LO16	\.text
 0+0154 <[^>]*> jr	at
 0+0158 <[^>]*> nop
@@ -119,7 +119,7 @@ Disassembly of section \.text:
 0+016c <[^>]*> lw	at,2\(gp\)
 [ 	]*16c: R_MIPS_GOT16	\.text
 0+0170 <[^>]*> nop
-0+0174 <[^>]*> addiu	at,at,1000
+0+0174 <[^>]*> addiu	at,at,992
 [ 	]*174: R_MIPS_LO16	\.text
 0+0178 <[^>]*> jr	at
 0+017c <[^>]*> sw	v0,0\(a0\)
@@ -130,7 +130,7 @@ Disassembly of section \.text:
 0+0190 <[^>]*> lw	at,2\(gp\)
 [ 	]*190: R_MIPS_GOT16	\.text
 0+0194 <[^>]*> nop
-0+0198 <[^>]*> addiu	at,at,1000
+0+0198 <[^>]*> addiu	at,at,992
 [ 	]*198: R_MIPS_LO16	\.text
 0+019c <[^>]*> jr	at
 0+01a0 <[^>]*> sw	v0,0\(a0\)
@@ -145,7 +145,7 @@ Disassembly of section \.text:
 0+01c4 <[^>]*> lw	at,2\(gp\)
 [ 	]*1c4: R_MIPS_GOT16	\.text
 0+01c8 <[^>]*> nop
-0+01cc <[^>]*> addiu	at,at,1000
+0+01cc <[^>]*> addiu	at,at,992
 [ 	]*1cc: R_MIPS_LO16	\.text
 0+01d0 <[^>]*> jr	at
 0+01d4 <[^>]*> nop
@@ -158,154 +158,152 @@ Disassembly of section \.text:
 0+01f0 <[^>]*> lw	at,2\(gp\)
 [ 	]*1f0: R_MIPS_GOT16	\.text
 0+01f4 <[^>]*> nop
-0+01f8 <[^>]*> addiu	at,at,1000
+0+01f8 <[^>]*> addiu	at,at,992
 [ 	]*1f8: R_MIPS_LO16	\.text
 0+01fc <[^>]*> jr	at
 0+0200 <[^>]*> move	a2,a3
-0+0204 <[^>]*> move	v0,a0
-0+0208 <[^>]*> bc1t	00000000 <foo>
-0+020c <[^>]*> nop
-0+0210 <[^>]*> move	v0,a0
-0+0214 <[^>]*> bc1f	0000022c <foo\+0x22c>
+0+0204 <[^>]*> bc1t	00000000 <foo>
+0+0208 <[^>]*> move	v0,a0
+0+020c <[^>]*> bc1f	00000224 <foo\+0x224>
+0+0210 <[^>]*> nop
+0+0214 <[^>]*> lw	at,2\(gp\)
+[ 	]*214: R_MIPS_GOT16	\.text
 0+0218 <[^>]*> nop
-0+021c <[^>]*> lw	at,2\(gp\)
-[ 	]*21c: R_MIPS_GOT16	\.text
-0+0220 <[^>]*> nop
-0+0224 <[^>]*> addiu	at,at,1000
-[ 	]*224: R_MIPS_LO16	\.text
-0+0228 <[^>]*> jr	at
-0+022c <[^>]*> nop
-0+0230 <[^>]*> move	v0,a0
-0+0234 <[^>]*> b	00000000 <foo>
-0+0238 <[^>]*> nop
-0+023c <[^>]*> move	v0,a0
-0+0240 <[^>]*> lw	at,2\(gp\)
-[ 	]*240: R_MIPS_GOT16	\.text
-0+0244 <[^>]*> nop
-0+0248 <[^>]*> addiu	at,at,1000
-[ 	]*248: R_MIPS_LO16	\.text
-0+024c <[^>]*> jr	at
-0+0250 <[^>]*> nop
-0+0254 <[^>]*> move	v0,a0
-0+0258 <[^>]*> b	00000000 <foo>
-0+025c <[^>]*> nop
-0+0260 <[^>]*> move	v0,a0
-0+0264 <[^>]*> lw	at,2\(gp\)
-[ 	]*264: R_MIPS_GOT16	\.text
-0+0268 <[^>]*> nop
-0+026c <[^>]*> addiu	at,at,1000
-[ 	]*26c: R_MIPS_LO16	\.text
-0+0270 <[^>]*> jr	at
-0+0274 <[^>]*> nop
-0+0278 <[^>]*> move	a2,a3
-0+027c <[^>]*> move	v0,a0
-0+0280 <[^>]*> b	00000000 <foo>
-0+0284 <[^>]*> nop
-0+0288 <[^>]*> move	a2,a3
-0+028c <[^>]*> move	v0,a0
-0+0290 <[^>]*> lw	at,2\(gp\)
-[ 	]*290: R_MIPS_GOT16	\.text
-0+0294 <[^>]*> nop
-0+0298 <[^>]*> addiu	at,at,1000
-[ 	]*298: R_MIPS_LO16	\.text
-0+029c <[^>]*> jr	at
+0+021c <[^>]*> addiu	at,at,992
+[ 	]*21c: R_MIPS_LO16	\.text
+0+0220 <[^>]*> jr	at
+0+0224 <[^>]*> move	v0,a0
+0+0228 <[^>]*> move	v0,a0
+0+022c <[^>]*> b	00000000 <foo>
+0+0230 <[^>]*> nop
+0+0234 <[^>]*> move	v0,a0
+0+0238 <[^>]*> lw	at,2\(gp\)
+[ 	]*238: R_MIPS_GOT16	\.text
+0+023c <[^>]*> nop
+0+0240 <[^>]*> addiu	at,at,992
+[ 	]*240: R_MIPS_LO16	\.text
+0+0244 <[^>]*> jr	at
+0+0248 <[^>]*> nop
+0+024c <[^>]*> move	v0,a0
+0+0250 <[^>]*> b	00000000 <foo>
+0+0254 <[^>]*> nop
+0+0258 <[^>]*> move	v0,a0
+0+025c <[^>]*> lw	at,2\(gp\)
+[ 	]*25c: R_MIPS_GOT16	\.text
+0+0260 <[^>]*> nop
+0+0264 <[^>]*> addiu	at,at,992
+[ 	]*264: R_MIPS_LO16	\.text
+0+0268 <[^>]*> jr	at
+0+026c <[^>]*> nop
+0+0270 <[^>]*> move	a2,a3
+0+0274 <[^>]*> move	v0,a0
+0+0278 <[^>]*> b	00000000 <foo>
+0+027c <[^>]*> nop
+0+0280 <[^>]*> move	a2,a3
+0+0284 <[^>]*> move	v0,a0
+0+0288 <[^>]*> lw	at,2\(gp\)
+[ 	]*288: R_MIPS_GOT16	\.text
+0+028c <[^>]*> nop
+0+0290 <[^>]*> addiu	at,at,992
+[ 	]*290: R_MIPS_LO16	\.text
+0+0294 <[^>]*> jr	at
+0+0298 <[^>]*> nop
+0+029c <[^>]*> lw	at,0\(gp\)
+[ 	]*29c: R_MIPS_GOT16	\.text
 0+02a0 <[^>]*> nop
-0+02a4 <[^>]*> lw	at,0\(gp\)
-[ 	]*2a4: R_MIPS_GOT16	\.text
-0+02a8 <[^>]*> nop
-0+02ac <[^>]*> addiu	at,at,692
-[ 	]*2ac: R_MIPS_LO16	\.text
-0+02b0 <[^>]*> sw	v0,0\(at\)
-0+02b4 <[^>]*> b	00000000 <foo>
+0+02a4 <[^>]*> addiu	at,at,684
+[ 	]*2a4: R_MIPS_LO16	\.text
+0+02a8 <[^>]*> sw	v0,0\(at\)
+0+02ac <[^>]*> b	00000000 <foo>
+0+02b0 <[^>]*> nop
+0+02b4 <[^>]*> lw	at,0\(gp\)
+[ 	]*2b4: R_MIPS_GOT16	\.text
 0+02b8 <[^>]*> nop
-0+02bc <[^>]*> lw	at,0\(gp\)
-[ 	]*2bc: R_MIPS_GOT16	\.text
-0+02c0 <[^>]*> nop
-0+02c4 <[^>]*> addiu	at,at,716
-[ 	]*2c4: R_MIPS_LO16	\.text
-0+02c8 <[^>]*> sw	v0,0\(at\)
-0+02cc <[^>]*> lw	at,2\(gp\)
-[ 	]*2cc: R_MIPS_GOT16	\.text
-0+02d0 <[^>]*> nop
-0+02d4 <[^>]*> addiu	at,at,1000
-[ 	]*2d4: R_MIPS_LO16	\.text
-0+02d8 <[^>]*> jr	at
-0+02dc <[^>]*> nop
-0+02e0 <[^>]*> lwc1	\$f0,0\(a0\)
-0+02e4 <[^>]*> b	00000000 <foo>
-0+02e8 <[^>]*> nop
-0+02ec <[^>]*> lwc1	\$f0,0\(a0\)
-0+02f0 <[^>]*> lw	at,2\(gp\)
-[ 	]*2f0: R_MIPS_GOT16	\.text
-0+02f4 <[^>]*> nop
-0+02f8 <[^>]*> addiu	at,at,1000
-[ 	]*2f8: R_MIPS_LO16	\.text
-0+02fc <[^>]*> jr	at
-0+0300 <[^>]*> nop
-0+0304 <[^>]*> cfc1	v0,\$31
-0+0308 <[^>]*> b	00000000 <foo>
-0+030c <[^>]*> nop
-0+0310 <[^>]*> cfc1	v0,\$31
-0+0314 <[^>]*> lw	at,2\(gp\)
-[ 	]*314: R_MIPS_GOT16	\.text
-0+0318 <[^>]*> nop
-0+031c <[^>]*> addiu	at,at,1000
-[ 	]*31c: R_MIPS_LO16	\.text
-0+0320 <[^>]*> jr	at
-0+0324 <[^>]*> nop
-0+0328 <[^>]*> ctc1	v0,\$31
-0+032c <[^>]*> b	00000000 <foo>
-0+0330 <[^>]*> nop
-0+0334 <[^>]*> ctc1	v0,\$31
-0+0338 <[^>]*> lw	at,2\(gp\)
-[ 	]*338: R_MIPS_GOT16	\.text
-0+033c <[^>]*> nop
-0+0340 <[^>]*> addiu	at,at,1000
-[ 	]*340: R_MIPS_LO16	\.text
-0+0344 <[^>]*> jr	at
-0+0348 <[^>]*> nop
-0+034c <[^>]*> mtc1	v0,\$f31
-0+0350 <[^>]*> b	00000000 <foo>
-0+0354 <[^>]*> nop
-0+0358 <[^>]*> mtc1	v0,\$f31
-0+035c <[^>]*> lw	at,2\(gp\)
-[ 	]*35c: R_MIPS_GOT16	\.text
-0+0360 <[^>]*> nop
-0+0364 <[^>]*> addiu	at,at,1000
-[ 	]*364: R_MIPS_LO16	\.text
-0+0368 <[^>]*> jr	at
-0+036c <[^>]*> nop
-0+0370 <[^>]*> mfhi	v0
-0+0374 <[^>]*> b	00000000 <foo>
-0+0378 <[^>]*> nop
-0+037c <[^>]*> mfhi	v0
-0+0380 <[^>]*> lw	at,2\(gp\)
-[ 	]*380: R_MIPS_GOT16	\.text
-0+0384 <[^>]*> nop
-0+0388 <[^>]*> addiu	at,at,1000
-[ 	]*388: R_MIPS_LO16	\.text
-0+038c <[^>]*> jr	at
-0+0390 <[^>]*> nop
-0+0394 <[^>]*> move	v0,a0
-0+0398 <[^>]*> jr	v0
-0+039c <[^>]*> nop
-0+03a0 <[^>]*> jr	a0
-0+03a4 <[^>]*> move	v0,a0
-0+03a8 <[^>]*> move	v0,a0
-0+03ac <[^>]*> jalr	v0
-0+03b0 <[^>]*> nop
-0+03b4 <[^>]*> jalr	a0
-0+03b8 <[^>]*> move	v0,a0
-0+03bc <[^>]*> move	v0,ra
-0+03c0 <[^>]*> jalr	v1
-0+03c4 <[^>]*> nop
-0+03c8 <[^>]*> move	ra,a0
-0+03cc <[^>]*> jalr	a1
-0+03d0 <[^>]*> nop
-0+03d4 <[^>]*> jalr	v0,v1
-0+03d8 <[^>]*> move	ra,a0
-0+03dc <[^>]*> move	v0,ra
-0+03e0 <[^>]*> jalr	v0,v1
-0+03e4 <[^>]*> nop
+0+02bc <[^>]*> addiu	at,at,708
+[ 	]*2bc: R_MIPS_LO16	\.text
+0+02c0 <[^>]*> sw	v0,0\(at\)
+0+02c4 <[^>]*> lw	at,2\(gp\)
+[ 	]*2c4: R_MIPS_GOT16	\.text
+0+02c8 <[^>]*> nop
+0+02cc <[^>]*> addiu	at,at,992
+[ 	]*2cc: R_MIPS_LO16	\.text
+0+02d0 <[^>]*> jr	at
+0+02d4 <[^>]*> nop
+0+02d8 <[^>]*> lwc1	\$f0,0\(a0\)
+0+02dc <[^>]*> b	00000000 <foo>
+0+02e0 <[^>]*> nop
+0+02e4 <[^>]*> lwc1	\$f0,0\(a0\)
+0+02e8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2e8: R_MIPS_GOT16	\.text
+0+02ec <[^>]*> nop
+0+02f0 <[^>]*> addiu	at,at,992
+[ 	]*2f0: R_MIPS_LO16	\.text
+0+02f4 <[^>]*> jr	at
+0+02f8 <[^>]*> nop
+0+02fc <[^>]*> cfc1	v0,\$31
+0+0300 <[^>]*> b	00000000 <foo>
+0+0304 <[^>]*> nop
+0+0308 <[^>]*> cfc1	v0,\$31
+0+030c <[^>]*> lw	at,2\(gp\)
+[ 	]*30c: R_MIPS_GOT16	\.text
+0+0310 <[^>]*> nop
+0+0314 <[^>]*> addiu	at,at,992
+[ 	]*314: R_MIPS_LO16	\.text
+0+0318 <[^>]*> jr	at
+0+031c <[^>]*> nop
+0+0320 <[^>]*> ctc1	v0,\$31
+0+0324 <[^>]*> b	00000000 <foo>
+0+0328 <[^>]*> nop
+0+032c <[^>]*> ctc1	v0,\$31
+0+0330 <[^>]*> lw	at,2\(gp\)
+[ 	]*330: R_MIPS_GOT16	\.text
+0+0334 <[^>]*> nop
+0+0338 <[^>]*> addiu	at,at,992
+[ 	]*338: R_MIPS_LO16	\.text
+0+033c <[^>]*> jr	at
+0+0340 <[^>]*> nop
+0+0344 <[^>]*> mtc1	v0,\$f31
+0+0348 <[^>]*> b	00000000 <foo>
+0+034c <[^>]*> nop
+0+0350 <[^>]*> mtc1	v0,\$f31
+0+0354 <[^>]*> lw	at,2\(gp\)
+[ 	]*354: R_MIPS_GOT16	\.text
+0+0358 <[^>]*> nop
+0+035c <[^>]*> addiu	at,at,992
+[ 	]*35c: R_MIPS_LO16	\.text
+0+0360 <[^>]*> jr	at
+0+0364 <[^>]*> nop
+0+0368 <[^>]*> mfhi	v0
+0+036c <[^>]*> b	00000000 <foo>
+0+0370 <[^>]*> nop
+0+0374 <[^>]*> mfhi	v0
+0+0378 <[^>]*> lw	at,2\(gp\)
+[ 	]*378: R_MIPS_GOT16	\.text
+0+037c <[^>]*> nop
+0+0380 <[^>]*> addiu	at,at,992
+[ 	]*380: R_MIPS_LO16	\.text
+0+0384 <[^>]*> jr	at
+0+0388 <[^>]*> nop
+0+038c <[^>]*> move	v0,a0
+0+0390 <[^>]*> jr	v0
+0+0394 <[^>]*> nop
+0+0398 <[^>]*> jr	a0
+0+039c <[^>]*> move	v0,a0
+0+03a0 <[^>]*> move	v0,a0
+0+03a4 <[^>]*> jalr	v0
+0+03a8 <[^>]*> nop
+0+03ac <[^>]*> jalr	a0
+0+03b0 <[^>]*> move	v0,a0
+0+03b4 <[^>]*> move	v0,ra
+0+03b8 <[^>]*> jalr	v1
+0+03bc <[^>]*> nop
+0+03c0 <[^>]*> move	ra,a0
+0+03c4 <[^>]*> jalr	a1
+0+03c8 <[^>]*> nop
+0+03cc <[^>]*> jalr	v0,v1
+0+03d0 <[^>]*> move	ra,a0
+0+03d4 <[^>]*> move	v0,ra
+0+03d8 <[^>]*> jalr	v0,v1
+0+03dc <[^>]*> nop
 	\.\.\.
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/relax-swap1-mips2.d b/gas/testsuite/gas/mips/relax-swap1-mips2.d
index 7297dd0031d3..17d010b91b2b 100644
--- a/gas/testsuite/gas/mips/relax-swap1-mips2.d
+++ b/gas/testsuite/gas/mips/relax-swap1-mips2.d
@@ -11,7 +11,7 @@ Disassembly of section \.text:
 0+0004 <[^>]*> move	v0,a0
 0+0008 <[^>]*> lw	at,2\(gp\)
 [ 	]*8: R_MIPS_GOT16	\.text
-0+000c <[^>]*> addiu	at,at,876
+0+000c <[^>]*> addiu	at,at,860
 [ 	]*c: R_MIPS_LO16	\.text
 0+0010 <[^>]*> jr	at
 0+0014 <[^>]*> move	v0,a0
@@ -19,7 +19,7 @@ Disassembly of section \.text:
 0+001c <[^>]*> lw	v0,0\(a0\)
 0+0020 <[^>]*> lw	at,2\(gp\)
 [ 	]*20: R_MIPS_GOT16	\.text
-0+0024 <[^>]*> addiu	at,at,876
+0+0024 <[^>]*> addiu	at,at,860
 [ 	]*24: R_MIPS_LO16	\.text
 0+0028 <[^>]*> jr	at
 0+002c <[^>]*> lw	v0,0\(a0\)
@@ -27,7 +27,7 @@ Disassembly of section \.text:
 0+0034 <[^>]*> sw	v0,0\(a0\)
 0+0038 <[^>]*> lw	at,2\(gp\)
 [ 	]*38: R_MIPS_GOT16	\.text
-0+003c <[^>]*> addiu	at,at,876
+0+003c <[^>]*> addiu	at,at,860
 [ 	]*3c: R_MIPS_LO16	\.text
 0+0040 <[^>]*> jr	at
 0+0044 <[^>]*> sw	v0,0\(a0\)
@@ -39,7 +39,7 @@ Disassembly of section \.text:
 0+005c <[^>]*> nop
 0+0060 <[^>]*> lw	at,2\(gp\)
 [ 	]*60: R_MIPS_GOT16	\.text
-0+0064 <[^>]*> addiu	at,at,876
+0+0064 <[^>]*> addiu	at,at,860
 [ 	]*64: R_MIPS_LO16	\.text
 0+0068 <[^>]*> jr	at
 0+006c <[^>]*> nop
@@ -49,7 +49,7 @@ Disassembly of section \.text:
 0+007c <[^>]*> nop
 0+0080 <[^>]*> lw	at,2\(gp\)
 [ 	]*80: R_MIPS_GOT16	\.text
-0+0084 <[^>]*> addiu	at,at,876
+0+0084 <[^>]*> addiu	at,at,860
 [ 	]*84: R_MIPS_LO16	\.text
 0+0088 <[^>]*> jr	at
 0+008c <[^>]*> move	v0,a0
@@ -61,7 +61,7 @@ Disassembly of section \.text:
 0+00a4 <[^>]*> nop
 0+00a8 <[^>]*> lw	at,2\(gp\)
 [ 	]*a8: R_MIPS_GOT16	\.text
-0+00ac <[^>]*> addiu	at,at,876
+0+00ac <[^>]*> addiu	at,at,860
 [ 	]*ac: R_MIPS_LO16	\.text
 0+00b0 <[^>]*> jr	at
 0+00b4 <[^>]*> nop
@@ -71,7 +71,7 @@ Disassembly of section \.text:
 0+00c4 <[^>]*> nop
 0+00c8 <[^>]*> lw	at,2\(gp\)
 [ 	]*c8: R_MIPS_GOT16	\.text
-0+00cc <[^>]*> addiu	at,at,876
+0+00cc <[^>]*> addiu	at,at,860
 [ 	]*cc: R_MIPS_LO16	\.text
 0+00d0 <[^>]*> jr	at
 0+00d4 <[^>]*> addiu	v0,a0,1
@@ -83,7 +83,7 @@ Disassembly of section \.text:
 0+00ec <[^>]*> nop
 0+00f0 <[^>]*> lw	at,2\(gp\)
 [ 	]*f0: R_MIPS_GOT16	\.text
-0+00f4 <[^>]*> addiu	at,at,876
+0+00f4 <[^>]*> addiu	at,at,860
 [ 	]*f4: R_MIPS_LO16	\.text
 0+00f8 <[^>]*> jr	at
 0+00fc <[^>]*> nop
@@ -93,7 +93,7 @@ Disassembly of section \.text:
 0+010c <[^>]*> nop
 0+0110 <[^>]*> lw	at,2\(gp\)
 [ 	]*110: R_MIPS_GOT16	\.text
-0+0114 <[^>]*> addiu	at,at,876
+0+0114 <[^>]*> addiu	at,at,860
 [ 	]*114: R_MIPS_LO16	\.text
 0+0118 <[^>]*> jr	at
 0+011c <[^>]*> lw	v0,0\(a0\)
@@ -103,7 +103,7 @@ Disassembly of section \.text:
 0+012c <[^>]*> nop
 0+0130 <[^>]*> lw	at,2\(gp\)
 [ 	]*130: R_MIPS_GOT16	\.text
-0+0134 <[^>]*> addiu	at,at,876
+0+0134 <[^>]*> addiu	at,at,860
 [ 	]*134: R_MIPS_LO16	\.text
 0+0138 <[^>]*> jr	at
 0+013c <[^>]*> sw	v0,0\(a0\)
@@ -113,7 +113,7 @@ Disassembly of section \.text:
 0+014c <[^>]*> nop
 0+0150 <[^>]*> lw	at,2\(gp\)
 [ 	]*150: R_MIPS_GOT16	\.text
-0+0154 <[^>]*> addiu	at,at,876
+0+0154 <[^>]*> addiu	at,at,860
 [ 	]*154: R_MIPS_LO16	\.text
 0+0158 <[^>]*> jr	at
 0+015c <[^>]*> sw	v0,0\(a0\)
@@ -127,7 +127,7 @@ Disassembly of section \.text:
 0+017c <[^>]*> nop
 0+0180 <[^>]*> lw	at,2\(gp\)
 [ 	]*180: R_MIPS_GOT16	\.text
-0+0184 <[^>]*> addiu	at,at,876
+0+0184 <[^>]*> addiu	at,at,860
 [ 	]*184: R_MIPS_LO16	\.text
 0+0188 <[^>]*> jr	at
 0+018c <[^>]*> nop
@@ -139,142 +139,138 @@ Disassembly of section \.text:
 0+01a4 <[^>]*> nop
 0+01a8 <[^>]*> lw	at,2\(gp\)
 [ 	]*1a8: R_MIPS_GOT16	\.text
-0+01ac <[^>]*> addiu	at,at,876
+0+01ac <[^>]*> addiu	at,at,860
 [ 	]*1ac: R_MIPS_LO16	\.text
 0+01b0 <[^>]*> jr	at
 0+01b4 <[^>]*> move	a2,a3
-0+01b8 <[^>]*> move	v0,a0
-0+01bc <[^>]*> bc1t	00000000 <foo>
-0+01c0 <[^>]*> nop
-0+01c4 <[^>]*> move	v0,a0
-0+01c8 <[^>]*> bc1f	000001dc <foo\+0x1dc>
-0+01cc <[^>]*> nop
-0+01d0 <[^>]*> lw	at,2\(gp\)
-[ 	]*1d0: R_MIPS_GOT16	\.text
-0+01d4 <[^>]*> addiu	at,at,876
-[ 	]*1d4: R_MIPS_LO16	\.text
-0+01d8 <[^>]*> jr	at
-0+01dc <[^>]*> nop
-0+01e0 <[^>]*> move	v0,a0
-0+01e4 <[^>]*> b	00000000 <foo>
-0+01e8 <[^>]*> nop
-0+01ec <[^>]*> move	v0,a0
-0+01f0 <[^>]*> lw	at,2\(gp\)
-[ 	]*1f0: R_MIPS_GOT16	\.text
-0+01f4 <[^>]*> addiu	at,at,876
-[ 	]*1f4: R_MIPS_LO16	\.text
-0+01f8 <[^>]*> jr	at
-0+01fc <[^>]*> nop
-0+0200 <[^>]*> move	v0,a0
-0+0204 <[^>]*> b	00000000 <foo>
-0+0208 <[^>]*> nop
-0+020c <[^>]*> move	v0,a0
-0+0210 <[^>]*> lw	at,2\(gp\)
-[ 	]*210: R_MIPS_GOT16	\.text
-0+0214 <[^>]*> addiu	at,at,876
-[ 	]*214: R_MIPS_LO16	\.text
-0+0218 <[^>]*> jr	at
-0+021c <[^>]*> nop
-0+0220 <[^>]*> move	a2,a3
-0+0224 <[^>]*> move	v0,a0
-0+0228 <[^>]*> b	00000000 <foo>
-0+022c <[^>]*> nop
-0+0230 <[^>]*> move	a2,a3
-0+0234 <[^>]*> move	v0,a0
-0+0238 <[^>]*> lw	at,2\(gp\)
-[ 	]*238: R_MIPS_GOT16	\.text
-0+023c <[^>]*> addiu	at,at,876
-[ 	]*23c: R_MIPS_LO16	\.text
-0+0240 <[^>]*> jr	at
-0+0244 <[^>]*> nop
-0+0248 <[^>]*> lw	at,0\(gp\)
-[ 	]*248: R_MIPS_GOT16	\.text
-0+024c <[^>]*> nop
-0+0250 <[^>]*> addiu	at,at,600
-[ 	]*250: R_MIPS_LO16	\.text
-0+0254 <[^>]*> sw	v0,0\(at\)
-0+0258 <[^>]*> b	00000000 <foo>
-0+025c <[^>]*> nop
-0+0260 <[^>]*> lw	at,0\(gp\)
+0+01b8 <[^>]*> bc1t	00000000 <foo>
+0+01bc <[^>]*> move	v0,a0
+0+01c0 <[^>]*> bc1f	000001d4 <foo\+0x1d4>
+0+01c4 <[^>]*> nop
+0+01c8 <[^>]*> lw	at,2\(gp\)
+[ 	]*1c8: R_MIPS_GOT16	\.text
+0+01cc <[^>]*> addiu	at,at,860
+[ 	]*1cc: R_MIPS_LO16	\.text
+0+01d0 <[^>]*> jr	at
+0+01d4 <[^>]*> move	v0,a0
+0+01d8 <[^>]*> move	v0,a0
+0+01dc <[^>]*> b	00000000 <foo>
+0+01e0 <[^>]*> nop
+0+01e4 <[^>]*> move	v0,a0
+0+01e8 <[^>]*> lw	at,2\(gp\)
+[ 	]*1e8: R_MIPS_GOT16	\.text
+0+01ec <[^>]*> addiu	at,at,860
+[ 	]*1ec: R_MIPS_LO16	\.text
+0+01f0 <[^>]*> jr	at
+0+01f4 <[^>]*> nop
+0+01f8 <[^>]*> move	v0,a0
+0+01fc <[^>]*> b	00000000 <foo>
+0+0200 <[^>]*> nop
+0+0204 <[^>]*> move	v0,a0
+0+0208 <[^>]*> lw	at,2\(gp\)
+[ 	]*208: R_MIPS_GOT16	\.text
+0+020c <[^>]*> addiu	at,at,860
+[ 	]*20c: R_MIPS_LO16	\.text
+0+0210 <[^>]*> jr	at
+0+0214 <[^>]*> nop
+0+0218 <[^>]*> move	a2,a3
+0+021c <[^>]*> move	v0,a0
+0+0220 <[^>]*> b	00000000 <foo>
+0+0224 <[^>]*> nop
+0+0228 <[^>]*> move	a2,a3
+0+022c <[^>]*> move	v0,a0
+0+0230 <[^>]*> lw	at,2\(gp\)
+[ 	]*230: R_MIPS_GOT16	\.text
+0+0234 <[^>]*> addiu	at,at,860
+[ 	]*234: R_MIPS_LO16	\.text
+0+0238 <[^>]*> jr	at
+0+023c <[^>]*> nop
+0+0240 <[^>]*> lw	at,0\(gp\)
+[ 	]*240: R_MIPS_GOT16	\.text
+0+0244 <[^>]*> addiu	at,at,588
+[ 	]*244: R_MIPS_LO16	\.text
+0+0248 <[^>]*> sw	v0,0\(at\)
+0+024c <[^>]*> b	00000000 <foo>
+0+0250 <[^>]*> nop
+0+0254 <[^>]*> lw	at,0\(gp\)
+[ 	]*254: R_MIPS_GOT16	\.text
+0+0258 <[^>]*> addiu	at,at,608
+[ 	]*258: R_MIPS_LO16	\.text
+0+025c <[^>]*> sw	v0,0\(at\)
+0+0260 <[^>]*> lw	at,2\(gp\)
 [ 	]*260: R_MIPS_GOT16	\.text
-0+0264 <[^>]*> nop
-0+0268 <[^>]*> addiu	at,at,624
-[ 	]*268: R_MIPS_LO16	\.text
-0+026c <[^>]*> sw	v0,0\(at\)
-0+0270 <[^>]*> lw	at,2\(gp\)
-[ 	]*270: R_MIPS_GOT16	\.text
-0+0274 <[^>]*> addiu	at,at,876
-[ 	]*274: R_MIPS_LO16	\.text
-0+0278 <[^>]*> jr	at
-0+027c <[^>]*> nop
-0+0280 <[^>]*> b	00000000 <foo>
+0+0264 <[^>]*> addiu	at,at,860
+[ 	]*264: R_MIPS_LO16	\.text
+0+0268 <[^>]*> jr	at
+0+026c <[^>]*> nop
+0+0270 <[^>]*> b	00000000 <foo>
+0+0274 <[^>]*> lwc1	\$f0,0\(a0\)
+0+0278 <[^>]*> lw	at,2\(gp\)
+[ 	]*278: R_MIPS_GOT16	\.text
+0+027c <[^>]*> addiu	at,at,860
+[ 	]*27c: R_MIPS_LO16	\.text
+0+0280 <[^>]*> jr	at
 0+0284 <[^>]*> lwc1	\$f0,0\(a0\)
-0+0288 <[^>]*> lw	at,2\(gp\)
-[ 	]*288: R_MIPS_GOT16	\.text
-0+028c <[^>]*> addiu	at,at,876
-[ 	]*28c: R_MIPS_LO16	\.text
-0+0290 <[^>]*> jr	at
-0+0294 <[^>]*> lwc1	\$f0,0\(a0\)
-0+0298 <[^>]*> cfc1	v0,\$31
-0+029c <[^>]*> b	00000000 <foo>
-0+02a0 <[^>]*> nop
-0+02a4 <[^>]*> cfc1	v0,\$31
-0+02a8 <[^>]*> lw	at,2\(gp\)
-[ 	]*2a8: R_MIPS_GOT16	\.text
-0+02ac <[^>]*> addiu	at,at,876
-[ 	]*2ac: R_MIPS_LO16	\.text
-0+02b0 <[^>]*> jr	at
-0+02b4 <[^>]*> nop
-0+02b8 <[^>]*> ctc1	v0,\$31
-0+02bc <[^>]*> b	00000000 <foo>
-0+02c0 <[^>]*> nop
-0+02c4 <[^>]*> ctc1	v0,\$31
-0+02c8 <[^>]*> lw	at,2\(gp\)
-[ 	]*2c8: R_MIPS_GOT16	\.text
-0+02cc <[^>]*> addiu	at,at,876
-[ 	]*2cc: R_MIPS_LO16	\.text
-0+02d0 <[^>]*> jr	at
-0+02d4 <[^>]*> nop
-0+02d8 <[^>]*> mtc1	v0,\$f31
-0+02dc <[^>]*> b	00000000 <foo>
-0+02e0 <[^>]*> nop
-0+02e4 <[^>]*> mtc1	v0,\$f31
-0+02e8 <[^>]*> lw	at,2\(gp\)
-[ 	]*2e8: R_MIPS_GOT16	\.text
-0+02ec <[^>]*> addiu	at,at,876
-[ 	]*2ec: R_MIPS_LO16	\.text
-0+02f0 <[^>]*> jr	at
-0+02f4 <[^>]*> nop
-0+02f8 <[^>]*> mfhi	v0
-0+02fc <[^>]*> b	00000000 <foo>
-0+0300 <[^>]*> nop
-0+0304 <[^>]*> mfhi	v0
-0+0308 <[^>]*> lw	at,2\(gp\)
-[ 	]*308: R_MIPS_GOT16	\.text
-0+030c <[^>]*> addiu	at,at,876
-[ 	]*30c: R_MIPS_LO16	\.text
-0+0310 <[^>]*> jr	at
-0+0314 <[^>]*> nop
+0+0288 <[^>]*> cfc1	v0,\$31
+0+028c <[^>]*> b	00000000 <foo>
+0+0290 <[^>]*> nop
+0+0294 <[^>]*> cfc1	v0,\$31
+0+0298 <[^>]*> lw	at,2\(gp\)
+[ 	]*298: R_MIPS_GOT16	\.text
+0+029c <[^>]*> addiu	at,at,860
+[ 	]*29c: R_MIPS_LO16	\.text
+0+02a0 <[^>]*> jr	at
+0+02a4 <[^>]*> nop
+0+02a8 <[^>]*> ctc1	v0,\$31
+0+02ac <[^>]*> b	00000000 <foo>
+0+02b0 <[^>]*> nop
+0+02b4 <[^>]*> ctc1	v0,\$31
+0+02b8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2b8: R_MIPS_GOT16	\.text
+0+02bc <[^>]*> addiu	at,at,860
+[ 	]*2bc: R_MIPS_LO16	\.text
+0+02c0 <[^>]*> jr	at
+0+02c4 <[^>]*> nop
+0+02c8 <[^>]*> mtc1	v0,\$f31
+0+02cc <[^>]*> b	00000000 <foo>
+0+02d0 <[^>]*> nop
+0+02d4 <[^>]*> mtc1	v0,\$f31
+0+02d8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2d8: R_MIPS_GOT16	\.text
+0+02dc <[^>]*> addiu	at,at,860
+[ 	]*2dc: R_MIPS_LO16	\.text
+0+02e0 <[^>]*> jr	at
+0+02e4 <[^>]*> nop
+0+02e8 <[^>]*> mfhi	v0
+0+02ec <[^>]*> b	00000000 <foo>
+0+02f0 <[^>]*> nop
+0+02f4 <[^>]*> mfhi	v0
+0+02f8 <[^>]*> lw	at,2\(gp\)
+[ 	]*2f8: R_MIPS_GOT16	\.text
+0+02fc <[^>]*> addiu	at,at,860
+[ 	]*2fc: R_MIPS_LO16	\.text
+0+0300 <[^>]*> jr	at
+0+0304 <[^>]*> nop
+0+0308 <[^>]*> move	v0,a0
+0+030c <[^>]*> jr	v0
+0+0310 <[^>]*> nop
+0+0314 <[^>]*> jr	a0
 0+0318 <[^>]*> move	v0,a0
-0+031c <[^>]*> jr	v0
-0+0320 <[^>]*> nop
-0+0324 <[^>]*> jr	a0
-0+0328 <[^>]*> move	v0,a0
+0+031c <[^>]*> move	v0,a0
+0+0320 <[^>]*> jalr	v0
+0+0324 <[^>]*> nop
+0+0328 <[^>]*> jalr	a0
 0+032c <[^>]*> move	v0,a0
-0+0330 <[^>]*> jalr	v0
-0+0334 <[^>]*> nop
-0+0338 <[^>]*> jalr	a0
-0+033c <[^>]*> move	v0,a0
-0+0340 <[^>]*> move	v0,ra
-0+0344 <[^>]*> jalr	v1
-0+0348 <[^>]*> nop
+0+0330 <[^>]*> move	v0,ra
+0+0334 <[^>]*> jalr	v1
+0+0338 <[^>]*> nop
+0+033c <[^>]*> move	ra,a0
+0+0340 <[^>]*> jalr	a1
+0+0344 <[^>]*> nop
+0+0348 <[^>]*> jalr	v0,v1
 0+034c <[^>]*> move	ra,a0
-0+0350 <[^>]*> jalr	a1
-0+0354 <[^>]*> nop
-0+0358 <[^>]*> jalr	v0,v1
-0+035c <[^>]*> move	ra,a0
-0+0360 <[^>]*> move	v0,ra
-0+0364 <[^>]*> jalr	v0,v1
-0+0368 <[^>]*> nop
+0+0350 <[^>]*> move	v0,ra
+0+0354 <[^>]*> jalr	v0,v1
+0+0358 <[^>]*> nop
 	\.\.\.
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/rol-hw.d b/gas/testsuite/gas/mips/rol-hw.d
index 347c7fb332c5..6a9b308a0d7e 100644
--- a/gas/testsuite/gas/mips/rol-hw.d
+++ b/gas/testsuite/gas/mips/rol-hw.d
@@ -1,7 +1,6 @@
 #objdump: -dr --prefix-addresses
 #name: MIPS hardware rol/ror
 #source: rol.s
-#stderr: rol-hw.l
 #as: -32
 
 # Test the rol and ror macros.
diff --git a/gas/testsuite/gas/mips/rol-hw.l b/gas/testsuite/gas/mips/rol-hw.l
deleted file mode 100644
index 19a5dc4ccd97..000000000000
--- a/gas/testsuite/gas/mips/rol-hw.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*:7: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/rol.d b/gas/testsuite/gas/mips/rol.d
index c226777c3b7c..e331b2c5068f 100644
--- a/gas/testsuite/gas/mips/rol.d
+++ b/gas/testsuite/gas/mips/rol.d
@@ -1,6 +1,5 @@
 #objdump: -dr --prefix-addresses
 #name: MIPS macro rol/ror
-#stderr: rol.l
 #as: -32
 
 # Test the rol and ror macros.
diff --git a/gas/testsuite/gas/mips/rol.l b/gas/testsuite/gas/mips/rol.l
deleted file mode 100644
index 441597e70b45..000000000000
--- a/gas/testsuite/gas/mips/rol.l
+++ /dev/null
@@ -1,13 +0,0 @@
-.*: Assembler messages:
-.*:7: Warning: Macro used \$at after "\.set noat"
-.*:8: Warning: Macro used \$at after "\.set noat"
-.*:9: Warning: Macro used \$at after "\.set noat"
-.*:10: Warning: Macro used \$at after "\.set noat"
-.*:13: Warning: Macro used \$at after "\.set noat"
-.*:14: Warning: Macro used \$at after "\.set noat"
-.*:15: Warning: Macro used \$at after "\.set noat"
-.*:16: Warning: Macro used \$at after "\.set noat"
-.*:20: Warning: Macro used \$at after "\.set noat"
-.*:21: Warning: Macro used \$at after "\.set noat"
-.*:24: Warning: Macro used \$at after "\.set noat"
-.*:25: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/rol.s b/gas/testsuite/gas/mips/rol.s
index 017c002af73b..97e2b01927de 100644
--- a/gas/testsuite/gas/mips/rol.s
+++ b/gas/testsuite/gas/mips/rol.s
@@ -1,8 +1,5 @@
 # Source file used to test the rol and ror macros.
 
-	# generate warnings for all uses of AT.
-	.set noat
-
 foo:
 	rol	$4,$5
 	rol	$4,$5,$6
diff --git a/gas/testsuite/gas/mips/rol64-hw.d b/gas/testsuite/gas/mips/rol64-hw.d
index a667f5a48693..3b34cec665b0 100644
--- a/gas/testsuite/gas/mips/rol64-hw.d
+++ b/gas/testsuite/gas/mips/rol64-hw.d
@@ -1,7 +1,6 @@
 #objdump: -dr --prefix-addresses
 #name: MIPS hardware drol/dror
 #source: rol64.s
-#stderr: rol64-hw.l
 
 # Test the drol and dror macros.
 
diff --git a/gas/testsuite/gas/mips/rol64-hw.l b/gas/testsuite/gas/mips/rol64-hw.l
deleted file mode 100644
index 19a5dc4ccd97..000000000000
--- a/gas/testsuite/gas/mips/rol64-hw.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*: Assembler messages:
-.*:7: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/rol64.d b/gas/testsuite/gas/mips/rol64.d
index dc2a0b7c0b55..081a3d8e7fe2 100644
--- a/gas/testsuite/gas/mips/rol64.d
+++ b/gas/testsuite/gas/mips/rol64.d
@@ -1,6 +1,5 @@
 #objdump: -dr --prefix-addresses
 #name: MIPS macro drol/dror
-#stderr: rol64.l
 
 # Test the drol and dror macros.
 
diff --git a/gas/testsuite/gas/mips/rol64.l b/gas/testsuite/gas/mips/rol64.l
deleted file mode 100644
index 4a4e74c40b14..000000000000
--- a/gas/testsuite/gas/mips/rol64.l
+++ /dev/null
@@ -1,27 +0,0 @@
-.*: Assembler messages:
-.*:7: Warning: Macro used \$at after "\.set noat"
-.*:8: Warning: Macro used \$at after "\.set noat"
-.*:9: Warning: Macro used \$at after "\.set noat"
-.*:11: Warning: Macro used \$at after "\.set noat"
-.*:12: Warning: Macro used \$at after "\.set noat"
-.*:13: Warning: Macro used \$at after "\.set noat"
-.*:14: Warning: Macro used \$at after "\.set noat"
-.*:15: Warning: Macro used \$at after "\.set noat"
-.*:18: Warning: Macro used \$at after "\.set noat"
-.*:19: Warning: Macro used \$at after "\.set noat"
-.*:20: Warning: Macro used \$at after "\.set noat"
-.*:22: Warning: Macro used \$at after "\.set noat"
-.*:23: Warning: Macro used \$at after "\.set noat"
-.*:24: Warning: Macro used \$at after "\.set noat"
-.*:25: Warning: Macro used \$at after "\.set noat"
-.*:26: Warning: Macro used \$at after "\.set noat"
-.*:29: Warning: Macro used \$at after "\.set noat"
-.*:30: Warning: Macro used \$at after "\.set noat"
-.*:31: Warning: Macro used \$at after "\.set noat"
-.*:32: Warning: Macro used \$at after "\.set noat"
-.*:33: Warning: Macro used \$at after "\.set noat"
-.*:35: Warning: Macro used \$at after "\.set noat"
-.*:36: Warning: Macro used \$at after "\.set noat"
-.*:37: Warning: Macro used \$at after "\.set noat"
-.*:38: Warning: Macro used \$at after "\.set noat"
-.*:39: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/rol64.s b/gas/testsuite/gas/mips/rol64.s
index 49a571736579..3f11363534a3 100644
--- a/gas/testsuite/gas/mips/rol64.s
+++ b/gas/testsuite/gas/mips/rol64.s
@@ -1,8 +1,5 @@
 # Source file used to test the drol and dror macros.
 
-	# generate warnings for all uses of AT.
-	.set noat
-
 foo:
 	drol	$4,$5
 	drol	$4,$5,$6
diff --git a/gas/testsuite/gas/mips/set-arch.d b/gas/testsuite/gas/mips/set-arch.d
index 2e04b293ad65..66e52654b9e0 100644
--- a/gas/testsuite/gas/mips/set-arch.d
+++ b/gas/testsuite/gas/mips/set-arch.d
@@ -160,207 +160,208 @@ Disassembly of section \.text:
 00000260 <[^>]*> 4359e260 	wait	0x56789
 00000264 <[^>]*> 0000000d 	break
 00000268 <[^>]*> 0000000d 	break
-0000026c <[^>]*> 0048d14d 	break	0x12345
-00000270 <[^>]*> 7000003f 	sdbbp
+0000026c <[^>]*> 0345000d 	break	0x345
+00000270 <[^>]*> 0048d14d 	break	0x48,0x345
 00000274 <[^>]*> 7000003f 	sdbbp
-00000278 <[^>]*> 7159e27f 	sdbbp	0x56789
-0000027c <[^>]*> 000000c0 	sll	zero,zero,0x3
-00000280 <[^>]*> 7ca43980 	0x7ca43980
-00000284 <[^>]*> 7ca46984 	0x7ca46984
-00000288 <[^>]*> 0100fc09 	0x100fc09
-0000028c <[^>]*> 0120a409 	0x120a409
-00000290 <[^>]*> 01000408 	0x1000408
-00000294 <[^>]*> 7c0a003b 	0x7c0a003b
-00000298 <[^>]*> 7c0b083b 	0x7c0b083b
-0000029c <[^>]*> 7c0c103b 	0x7c0c103b
-000002a0 <[^>]*> 7c0d183b 	0x7c0d183b
-000002a4 <[^>]*> 7c0e203b 	0x7c0e203b
-000002a8 <[^>]*> 7c0f283b 	0x7c0f283b
-000002ac <[^>]*> 002acf02 	0x2acf02
-000002b0 <[^>]*> 002ac902 	0x2ac902
-000002b4 <[^>]*> 0004c823 	negu	t9,a0
-000002b8 <[^>]*> 032ac846 	0x32ac846
-000002bc <[^>]*> 008ac846 	0x8ac846
+00000278 <[^>]*> 7000003f 	sdbbp
+0000027c <[^>]*> 7159e27f 	sdbbp	0x56789
+00000280 <[^>]*> 000000c0 	sll	zero,zero,0x3
+00000284 <[^>]*> 7ca43980 	0x7ca43980
+00000288 <[^>]*> 7ca46984 	0x7ca46984
+0000028c <[^>]*> 0100fc09 	0x100fc09
+00000290 <[^>]*> 0120a409 	0x120a409
+00000294 <[^>]*> 01000408 	0x1000408
+00000298 <[^>]*> 7c0a003b 	0x7c0a003b
+0000029c <[^>]*> 7c0b083b 	0x7c0b083b
+000002a0 <[^>]*> 7c0c103b 	0x7c0c103b
+000002a4 <[^>]*> 7c0d183b 	0x7c0d183b
+000002a8 <[^>]*> 7c0e203b 	0x7c0e203b
+000002ac <[^>]*> 7c0f283b 	0x7c0f283b
+000002b0 <[^>]*> 002acf02 	0x2acf02
+000002b4 <[^>]*> 002ac902 	0x2ac902
+000002b8 <[^>]*> 0004c823 	negu	t9,a0
+000002bc <[^>]*> 032ac846 	0x32ac846
 000002c0 <[^>]*> 008ac846 	0x8ac846
-000002c4 <[^>]*> 7c073c20 	0x7c073c20
-000002c8 <[^>]*> 7c0a4420 	0x7c0a4420
-000002cc <[^>]*> 7c073e20 	0x7c073e20
-000002d0 <[^>]*> 7c0a4620 	0x7c0a4620
-000002d4 <[^>]*> 055f5555 	0x55f5555
-000002d8 <[^>]*> 7c0738a0 	0x7c0738a0
-000002dc <[^>]*> 7c0a40a0 	0x7c0a40a0
-000002e0 <[^>]*> 41606000 	0x41606000
+000002c4 <[^>]*> 008ac846 	0x8ac846
+000002c8 <[^>]*> 7c073c20 	0x7c073c20
+000002cc <[^>]*> 7c0a4420 	0x7c0a4420
+000002d0 <[^>]*> 7c073e20 	0x7c073e20
+000002d4 <[^>]*> 7c0a4620 	0x7c0a4620
+000002d8 <[^>]*> 055f5555 	0x55f5555
+000002dc <[^>]*> 7c0738a0 	0x7c0738a0
+000002e0 <[^>]*> 7c0a40a0 	0x7c0a40a0
 000002e4 <[^>]*> 41606000 	0x41606000
-000002e8 <[^>]*> 416a6000 	0x416a6000
-000002ec <[^>]*> 41606020 	0x41606020
+000002e8 <[^>]*> 41606000 	0x41606000
+000002ec <[^>]*> 416a6000 	0x416a6000
 000002f0 <[^>]*> 41606020 	0x41606020
-000002f4 <[^>]*> 416a6020 	0x416a6020
-000002f8 <[^>]*> 41595000 	0x41595000
-000002fc <[^>]*> 41d95000 	0x41d95000
-00000300 <[^>]*> 44710000 	0x44710000
-00000304 <[^>]*> 44f10000 	0x44f10000
-00000308 <[^>]*> 48715555 	0x48715555
-0000030c <[^>]*> 48f15555 	0x48f15555
-00000310 <[^>]*> 70410825 	dclo	at,v0
-00000314 <[^>]*> 70831824 	dclz	v1,a0
-00000318 <[^>]*> 48232000 	dmfc2	v1,\$4
-0000031c <[^>]*> 48242800 	dmfc2	a0,\$5
-00000320 <[^>]*> 48253007 	dmfc2	a1,\$6,7
-00000324 <[^>]*> 48a63800 	dmtc2	a2,\$7
-00000328 <[^>]*> 48a74000 	dmtc2	a3,\$8
-0000032c <[^>]*> 48a84807 	dmtc2	t0,\$9,7
-00000330 <[^>]*> 00850029 	0x850029
-00000334 <[^>]*> 00a60028 	0xa60028
-00000338 <[^>]*> 00002012 	mflo	a0
-0000033c <[^>]*> 00a62029 	0xa62029
-00000340 <[^>]*> 00a62229 	0xa62229
-00000344 <[^>]*> 00a62629 	0xa62629
-00000348 <[^>]*> 00a62269 	0xa62269
-0000034c <[^>]*> 00a62669 	0xa62669
-00000350 <[^>]*> 00a62429 	0xa62429
-00000354 <[^>]*> 00a62069 	0xa62069
-00000358 <[^>]*> 00a62469 	0xa62469
-0000035c <[^>]*> 00002012 	mflo	a0
-00000360 <[^>]*> 00a62028 	0xa62028
-00000364 <[^>]*> 00a62228 	0xa62228
-00000368 <[^>]*> 00a62628 	0xa62628
-0000036c <[^>]*> 00a62268 	0xa62268
-00000370 <[^>]*> 00a62668 	0xa62668
-00000374 <[^>]*> 00a62428 	0xa62428
-00000378 <[^>]*> 00a62068 	0xa62068
-0000037c <[^>]*> 00a62468 	0xa62468
-00000380 <[^>]*> 00a62059 	0xa62059
-00000384 <[^>]*> 00a62258 	0xa62258
-00000388 <[^>]*> 00a62259 	0xa62259
-0000038c <[^>]*> 00a620d8 	0xa620d8
-00000390 <[^>]*> 00a620d9 	0xa620d9
-00000394 <[^>]*> 00a622d8 	0xa622d8
-00000398 <[^>]*> 00a622d9 	0xa622d9
-0000039c <[^>]*> 00a62158 	0xa62158
-000003a0 <[^>]*> 00a62159 	0xa62159
-000003a4 <[^>]*> 00a62358 	0xa62358
-000003a8 <[^>]*> 00a62359 	0xa62359
-000003ac <[^>]*> 00a621d8 	0xa621d8
-000003b0 <[^>]*> 00a621d9 	0xa621d9
-000003b4 <[^>]*> 00a623d8 	0xa623d8
-000003b8 <[^>]*> 00a623d9 	0xa623d9
-000003bc <[^>]*> 00252642 	0x252642
-000003c0 <[^>]*> 00c52046 	0xc52046
-000003c4 <[^>]*> 0025267a 	0x25267a
-000003c8 <[^>]*> 0025267e 	0x25267e
+000002f4 <[^>]*> 41606020 	0x41606020
+000002f8 <[^>]*> 416a6020 	0x416a6020
+000002fc <[^>]*> 41595000 	0x41595000
+00000300 <[^>]*> 41d95000 	0x41d95000
+00000304 <[^>]*> 44710000 	0x44710000
+00000308 <[^>]*> 44f10000 	0x44f10000
+0000030c <[^>]*> 48715555 	0x48715555
+00000310 <[^>]*> 48f15555 	0x48f15555
+00000314 <[^>]*> 70410825 	dclo	at,v0
+00000318 <[^>]*> 70831824 	dclz	v1,a0
+0000031c <[^>]*> 48232000 	dmfc2	v1,\$4
+00000320 <[^>]*> 48242800 	dmfc2	a0,\$5
+00000324 <[^>]*> 48253007 	dmfc2	a1,\$6,7
+00000328 <[^>]*> 48a63800 	dmtc2	a2,\$7
+0000032c <[^>]*> 48a74000 	dmtc2	a3,\$8
+00000330 <[^>]*> 48a84807 	dmtc2	t0,\$9,7
+00000334 <[^>]*> 00850029 	0x850029
+00000338 <[^>]*> 00a60028 	0xa60028
+0000033c <[^>]*> 00002012 	mflo	a0
+00000340 <[^>]*> 00a62029 	0xa62029
+00000344 <[^>]*> 00a62229 	0xa62229
+00000348 <[^>]*> 00a62629 	0xa62629
+0000034c <[^>]*> 00a62269 	0xa62269
+00000350 <[^>]*> 00a62669 	0xa62669
+00000354 <[^>]*> 00a62429 	0xa62429
+00000358 <[^>]*> 00a62069 	0xa62069
+0000035c <[^>]*> 00a62469 	0xa62469
+00000360 <[^>]*> 00002012 	mflo	a0
+00000364 <[^>]*> 00a62028 	0xa62028
+00000368 <[^>]*> 00a62228 	0xa62228
+0000036c <[^>]*> 00a62628 	0xa62628
+00000370 <[^>]*> 00a62268 	0xa62268
+00000374 <[^>]*> 00a62668 	0xa62668
+00000378 <[^>]*> 00a62428 	0xa62428
+0000037c <[^>]*> 00a62068 	0xa62068
+00000380 <[^>]*> 00a62468 	0xa62468
+00000384 <[^>]*> 00a62059 	0xa62059
+00000388 <[^>]*> 00a62258 	0xa62258
+0000038c <[^>]*> 00a62259 	0xa62259
+00000390 <[^>]*> 00a620d8 	0xa620d8
+00000394 <[^>]*> 00a620d9 	0xa620d9
+00000398 <[^>]*> 00a622d8 	0xa622d8
+0000039c <[^>]*> 00a622d9 	0xa622d9
+000003a0 <[^>]*> 00a62158 	0xa62158
+000003a4 <[^>]*> 00a62159 	0xa62159
+000003a8 <[^>]*> 00a62358 	0xa62358
+000003ac <[^>]*> 00a62359 	0xa62359
+000003b0 <[^>]*> 00a621d8 	0xa621d8
+000003b4 <[^>]*> 00a621d9 	0xa621d9
+000003b8 <[^>]*> 00a623d8 	0xa623d8
+000003bc <[^>]*> 00a623d9 	0xa623d9
+000003c0 <[^>]*> 00252642 	0x252642
+000003c4 <[^>]*> 00c52046 	0xc52046
+000003c8 <[^>]*> 0025267a 	0x25267a
 000003cc <[^>]*> 0025267e 	0x25267e
-000003d0 <[^>]*> 00c52056 	0xc52056
-000003d4 <[^>]*> 7000003f 	sdbbp
-000003d8 <[^>]*> 7000003e 	0x7000003e
-000003dc <[^>]*> 7003183d 	0x7003183d
-000003e0 <[^>]*> 7083183d 	0x7083183d
-000003e4 <[^>]*> 4004c803 	mfc0	a0,c0_perfcnt,3
-000003e8 <[^>]*> 4004c802 	mfc0	a0,c0_perfcnt,2
-000003ec <[^>]*> 4084c803 	mtc0	a0,c0_perfcnt,3
-000003f0 <[^>]*> 4084c802 	mtc0	a0,c0_perfcnt,2
-000003f4 <[^>]*> 4ac4100b 	c2	0xc4100b
-000003f8 <[^>]*> 4886208b 	0x4886208b
-000003fc <[^>]*> 4bcf218b 	c2	0x1cf218b
-00000400 <[^>]*> 4bdf310b 	c2	0x1df310b
-00000404 <[^>]*> 4ac4100c 	c2	0xc4100c
-00000408 <[^>]*> 4886208c 	0x4886208c
-0000040c <[^>]*> 4bcf218c 	c2	0x1cf218c
-00000410 <[^>]*> 4bdf310c 	c2	0x1df310c
-00000414 <[^>]*> 4ac20001 	c2	0xc20001
-00000418 <[^>]*> 48862001 	mtc2	a2,\$4,1
-0000041c <[^>]*> 4bcf3001 	c2	0x1cf3001
-00000420 <[^>]*> 4bdf2001 	c2	0x1df2001
-00000424 <[^>]*> 4ac20005 	c2	0xc20005
-00000428 <[^>]*> 48862005 	mtc2	a2,\$4,5
-0000042c <[^>]*> 4bcf3005 	c2	0x1cf3005
-00000430 <[^>]*> 4bdf2005 	c2	0x1df2005
-00000434 <[^>]*> 4ac20004 	c2	0xc20004
-00000438 <[^>]*> 48862004 	mtc2	a2,\$4,4
-0000043c <[^>]*> 4bcf3004 	c2	0x1cf3004
-00000440 <[^>]*> 4bdf2004 	c2	0x1df2004
-00000444 <[^>]*> 4ac41007 	c2	0xc41007
-00000448 <[^>]*> 48862087 	0x48862087
-0000044c <[^>]*> 4bcf2187 	c2	0x1cf2187
-00000450 <[^>]*> 4bdf3107 	c2	0x1df3107
-00000454 <[^>]*> 4ac41006 	c2	0xc41006
-00000458 <[^>]*> 48862086 	0x48862086
-0000045c <[^>]*> 4bcf2186 	c2	0x1cf2186
-00000460 <[^>]*> 4bdf3106 	c2	0x1df3106
-00000464 <[^>]*> 4ac41030 	c2	0xc41030
-00000468 <[^>]*> 488620b0 	0x488620b0
-0000046c <[^>]*> 4bcf21b0 	c2	0x1cf21b0
-00000470 <[^>]*> 4bdf3130 	c2	0x1df3130
-00000474 <[^>]*> 4ac20033 	c2	0xc20033
-00000478 <[^>]*> 48862033 	0x48862033
-0000047c <[^>]*> 4bcf3033 	c2	0x1cf3033
-00000480 <[^>]*> 4bdf2033 	c2	0x1df2033
-00000484 <[^>]*> 4ac20433 	c2	0xc20433
-00000488 <[^>]*> 48862433 	0x48862433
-0000048c <[^>]*> 4bcf3433 	c2	0x1cf3433
-00000490 <[^>]*> 4bdf2433 	c2	0x1df2433
-00000494 <[^>]*> 4ac20032 	c2	0xc20032
-00000498 <[^>]*> 48862032 	0x48862032
-0000049c <[^>]*> 4bcf3032 	c2	0x1cf3032
-000004a0 <[^>]*> 4bdf2032 	c2	0x1df2032
-000004a4 <[^>]*> 4ac20432 	c2	0xc20432
-000004a8 <[^>]*> 48862432 	0x48862432
-000004ac <[^>]*> 4bcf3432 	c2	0x1cf3432
-000004b0 <[^>]*> 4bdf2432 	c2	0x1df2432
-000004b4 <[^>]*> 4ac4100f 	c2	0xc4100f
-000004b8 <[^>]*> 4886208f 	0x4886208f
-000004bc <[^>]*> 4bcf218f 	c2	0x1cf218f
-000004c0 <[^>]*> 4bdf310f 	c2	0x1df310f
-000004c4 <[^>]*> 4ac4100e 	c2	0xc4100e
-000004c8 <[^>]*> 4886208e 	0x4886208e
-000004cc <[^>]*> 4bcf218e 	c2	0x1cf218e
-000004d0 <[^>]*> 4bdf310e 	c2	0x1df310e
-000004d4 <[^>]*> 4ac41002 	c2	0xc41002
-000004d8 <[^>]*> 48862082 	0x48862082
-000004dc <[^>]*> 4bcf2182 	c2	0x1cf2182
-000004e0 <[^>]*> 4bdf3102 	c2	0x1df3102
-000004e4 <[^>]*> 4ac41003 	c2	0xc41003
-000004e8 <[^>]*> 48862083 	0x48862083
-000004ec <[^>]*> 4bcf2183 	c2	0x1cf2183
-000004f0 <[^>]*> 4bdf3103 	c2	0x1df3103
-000004f4 <[^>]*> 4ac4100a 	c2	0xc4100a
-000004f8 <[^>]*> 4886208a 	0x4886208a
-000004fc <[^>]*> 4bcf218a 	c2	0x1cf218a
-00000500 <[^>]*> 4bdf310a 	c2	0x1df310a
-00000504 <[^>]*> 4ac4100d 	c2	0xc4100d
-00000508 <[^>]*> 4886208d 	0x4886208d
-0000050c <[^>]*> 4bcf218d 	c2	0x1cf218d
-00000510 <[^>]*> 4bdf310d 	c2	0x1df310d
-00000514 <[^>]*> 48a41018 	0x48a41018
-00000518 <[^>]*> 4984101f 	0x4984101f
-0000051c <[^>]*> 49c4101f 	0x49c4101f
-00000520 <[^>]*> 4904101f 	0x4904101f
-00000524 <[^>]*> 4944101f 	0x4944101f
-00000528 <[^>]*> 48c62090 	0x48c62090
-0000052c <[^>]*> 4bce3110 	c2	0x1ce3110
-00000530 <[^>]*> 48c62092 	0x48c62092
-00000534 <[^>]*> 4bce3112 	c2	0x1ce3112
-00000538 <[^>]*> 4bcd00a0 	c2	0x1cd00a0
-0000053c <[^>]*> 4a0000bf 	c2	0xbf
-00000540 <[^>]*> 480000bf 	0x480000bf
-00000544 <[^>]*> 490000bf 	bc2f	00000844 <[^>]*>
-00000548 <[^>]*> 4a00103e 	c2	0x103e
-0000054c <[^>]*> 4804103e 	0x4804103e
-00000550 <[^>]*> 00c52046 	0xc52046
-00000554 <[^>]*> 00252442 	0x252442
-00000558 <[^>]*> 00c52056 	0xc52056
-0000055c <[^>]*> 0025207e 	0x25207e
-00000560 <[^>]*> 002520ba 	0x2520ba
-00000564 <[^>]*> 4ca4200f 	prefx	0x4,a0\(a1\)
-00000568 <[^>]*> 42000020 	wait
+000003d0 <[^>]*> 0025267e 	0x25267e
+000003d4 <[^>]*> 00c52056 	0xc52056
+000003d8 <[^>]*> 7000003f 	sdbbp
+000003dc <[^>]*> 7000003e 	0x7000003e
+000003e0 <[^>]*> 7003183d 	0x7003183d
+000003e4 <[^>]*> 7083183d 	0x7083183d
+000003e8 <[^>]*> 4004c803 	mfc0	a0,c0_perfcnt,3
+000003ec <[^>]*> 4004c802 	mfc0	a0,c0_perfcnt,2
+000003f0 <[^>]*> 4084c803 	mtc0	a0,c0_perfcnt,3
+000003f4 <[^>]*> 4084c802 	mtc0	a0,c0_perfcnt,2
+000003f8 <[^>]*> 4ac4100b 	c2	0xc4100b
+000003fc <[^>]*> 4886208b 	0x4886208b
+00000400 <[^>]*> 4bcf218b 	c2	0x1cf218b
+00000404 <[^>]*> 4bdf310b 	c2	0x1df310b
+00000408 <[^>]*> 4ac4100c 	c2	0xc4100c
+0000040c <[^>]*> 4886208c 	0x4886208c
+00000410 <[^>]*> 4bcf218c 	c2	0x1cf218c
+00000414 <[^>]*> 4bdf310c 	c2	0x1df310c
+00000418 <[^>]*> 4ac20001 	c2	0xc20001
+0000041c <[^>]*> 48862001 	mtc2	a2,\$4,1
+00000420 <[^>]*> 4bcf3001 	c2	0x1cf3001
+00000424 <[^>]*> 4bdf2001 	c2	0x1df2001
+00000428 <[^>]*> 4ac20005 	c2	0xc20005
+0000042c <[^>]*> 48862005 	mtc2	a2,\$4,5
+00000430 <[^>]*> 4bcf3005 	c2	0x1cf3005
+00000434 <[^>]*> 4bdf2005 	c2	0x1df2005
+00000438 <[^>]*> 4ac20004 	c2	0xc20004
+0000043c <[^>]*> 48862004 	mtc2	a2,\$4,4
+00000440 <[^>]*> 4bcf3004 	c2	0x1cf3004
+00000444 <[^>]*> 4bdf2004 	c2	0x1df2004
+00000448 <[^>]*> 4ac41007 	c2	0xc41007
+0000044c <[^>]*> 48862087 	0x48862087
+00000450 <[^>]*> 4bcf2187 	c2	0x1cf2187
+00000454 <[^>]*> 4bdf3107 	c2	0x1df3107
+00000458 <[^>]*> 4ac41006 	c2	0xc41006
+0000045c <[^>]*> 48862086 	0x48862086
+00000460 <[^>]*> 4bcf2186 	c2	0x1cf2186
+00000464 <[^>]*> 4bdf3106 	c2	0x1df3106
+00000468 <[^>]*> 4ac41030 	c2	0xc41030
+0000046c <[^>]*> 488620b0 	0x488620b0
+00000470 <[^>]*> 4bcf21b0 	c2	0x1cf21b0
+00000474 <[^>]*> 4bdf3130 	c2	0x1df3130
+00000478 <[^>]*> 4ac20033 	c2	0xc20033
+0000047c <[^>]*> 48862033 	0x48862033
+00000480 <[^>]*> 4bcf3033 	c2	0x1cf3033
+00000484 <[^>]*> 4bdf2033 	c2	0x1df2033
+00000488 <[^>]*> 4ac20433 	c2	0xc20433
+0000048c <[^>]*> 48862433 	0x48862433
+00000490 <[^>]*> 4bcf3433 	c2	0x1cf3433
+00000494 <[^>]*> 4bdf2433 	c2	0x1df2433
+00000498 <[^>]*> 4ac20032 	c2	0xc20032
+0000049c <[^>]*> 48862032 	0x48862032
+000004a0 <[^>]*> 4bcf3032 	c2	0x1cf3032
+000004a4 <[^>]*> 4bdf2032 	c2	0x1df2032
+000004a8 <[^>]*> 4ac20432 	c2	0xc20432
+000004ac <[^>]*> 48862432 	0x48862432
+000004b0 <[^>]*> 4bcf3432 	c2	0x1cf3432
+000004b4 <[^>]*> 4bdf2432 	c2	0x1df2432
+000004b8 <[^>]*> 4ac4100f 	c2	0xc4100f
+000004bc <[^>]*> 4886208f 	0x4886208f
+000004c0 <[^>]*> 4bcf218f 	c2	0x1cf218f
+000004c4 <[^>]*> 4bdf310f 	c2	0x1df310f
+000004c8 <[^>]*> 4ac4100e 	c2	0xc4100e
+000004cc <[^>]*> 4886208e 	0x4886208e
+000004d0 <[^>]*> 4bcf218e 	c2	0x1cf218e
+000004d4 <[^>]*> 4bdf310e 	c2	0x1df310e
+000004d8 <[^>]*> 4ac41002 	c2	0xc41002
+000004dc <[^>]*> 48862082 	0x48862082
+000004e0 <[^>]*> 4bcf2182 	c2	0x1cf2182
+000004e4 <[^>]*> 4bdf3102 	c2	0x1df3102
+000004e8 <[^>]*> 4ac41003 	c2	0xc41003
+000004ec <[^>]*> 48862083 	0x48862083
+000004f0 <[^>]*> 4bcf2183 	c2	0x1cf2183
+000004f4 <[^>]*> 4bdf3103 	c2	0x1df3103
+000004f8 <[^>]*> 4ac4100a 	c2	0xc4100a
+000004fc <[^>]*> 4886208a 	0x4886208a
+00000500 <[^>]*> 4bcf218a 	c2	0x1cf218a
+00000504 <[^>]*> 4bdf310a 	c2	0x1df310a
+00000508 <[^>]*> 4ac4100d 	c2	0xc4100d
+0000050c <[^>]*> 4886208d 	0x4886208d
+00000510 <[^>]*> 4bcf218d 	c2	0x1cf218d
+00000514 <[^>]*> 4bdf310d 	c2	0x1df310d
+00000518 <[^>]*> 48a41018 	0x48a41018
+0000051c <[^>]*> 4984101f 	0x4984101f
+00000520 <[^>]*> 49c4101f 	0x49c4101f
+00000524 <[^>]*> 4904101f 	0x4904101f
+00000528 <[^>]*> 4944101f 	0x4944101f
+0000052c <[^>]*> 48c62090 	0x48c62090
+00000530 <[^>]*> 4bce3110 	c2	0x1ce3110
+00000534 <[^>]*> 48c62092 	0x48c62092
+00000538 <[^>]*> 4bce3112 	c2	0x1ce3112
+0000053c <[^>]*> 4bcd00a0 	c2	0x1cd00a0
+00000540 <[^>]*> 4a0000bf 	c2	0xbf
+00000544 <[^>]*> 480000bf 	0x480000bf
+00000548 <[^>]*> 490000bf 	bc2f	00000848 <[^>]*>
+0000054c <[^>]*> 4a00103e 	c2	0x103e
+00000550 <[^>]*> 4804103e 	0x4804103e
+00000554 <[^>]*> 00c52046 	0xc52046
+00000558 <[^>]*> 00252442 	0x252442
+0000055c <[^>]*> 00c52056 	0xc52056
+00000560 <[^>]*> 0025207e 	0x25207e
+00000564 <[^>]*> 002520ba 	0x2520ba
+00000568 <[^>]*> 4ca4200f 	prefx	0x4,a0\(a1\)
 0000056c <[^>]*> 42000020 	wait
-00000570 <[^>]*> 4359e260 	wait	0x56789
-00000574 <[^>]*> 00000040 	ssnop
-00000578 <[^>]*> 70831821 	clo	v1,a0
-0000057c <[^>]*> 70831825 	dclo	v1,a0
-00000580 <[^>]*> 70831820 	clz	v1,a0
-00000584 <[^>]*> 70831824 	dclz	v1,a0
-00000588 <[^>]*> 4c440005 	luxc1	\$f0,a0\(v0\)
-0000058c <[^>]*> 4c44100d 	suxc1	\$f2,a0\(v0\)
-00000590 <[^>]*> 42000008 	tlbp
-00000594 <[^>]*> 42000001 	tlbr
+00000570 <[^>]*> 42000020 	wait
+00000574 <[^>]*> 4359e260 	wait	0x56789
+00000578 <[^>]*> 00000040 	ssnop
+0000057c <[^>]*> 70831821 	clo	v1,a0
+00000580 <[^>]*> 70831825 	dclo	v1,a0
+00000584 <[^>]*> 70831820 	clz	v1,a0
+00000588 <[^>]*> 70831824 	dclz	v1,a0
+0000058c <[^>]*> 4c440005 	luxc1	\$f0,a0\(v0\)
+00000590 <[^>]*> 4c44100d 	suxc1	\$f2,a0\(v0\)
+00000594 <[^>]*> 42000008 	tlbp
+00000598 <[^>]*> 42000001 	tlbr
 	\.\.\.
diff --git a/gas/testsuite/gas/mips/set-arch.s b/gas/testsuite/gas/mips/set-arch.s
index 01a6c8329168..7f1f0c2b9dda 100644
--- a/gas/testsuite/gas/mips/set-arch.s
+++ b/gas/testsuite/gas/mips/set-arch.s
@@ -200,11 +200,17 @@ text_label:
 	wait    0                       # disassembles without code
 	wait    0x56789
 
-	# Instructions in previous ISAs or CPUs which are now slightly
-	# different.
+	# For a while break for the mips32 ISA interpreted a single argument
+	# as a 20-bit code, placing it in the opcode differently to
+	# traditional ISAs.  This turned out to cause problems, so it has
+	# been removed.  This test is to assure consistent interpretation.
 	break
 	break   0                       # disassembles without code
-	break   0x12345
+	break	0x345
+	break	0x48,0x345		# this still specifies a 20-bit code
+
+	# Instructions in previous ISAs or CPUs which are now slightly
+	# different.
 	sdbbp
 	sdbbp   0                       # disassembles without code
 	sdbbp   0x56789
diff --git a/gas/testsuite/gas/mips/telempic.d b/gas/testsuite/gas/mips/telempic.d
deleted file mode 100644
index 96bc263b6b02..000000000000
--- a/gas/testsuite/gas/mips/telempic.d
+++ /dev/null
@@ -1,155 +0,0 @@
-#objdump: -rst -mmips:4000
-#name: MIPS empic
-#as: -mabi=o64 -membedded-pic -mips3
-#source: empic.s
-#stderr: empic.l
-
-# Check GNU-specific embedded relocs, for ELF.
-
-.*: +file format elf.*mips.*
-
-SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
-0+0000004 l       \.text	0+0000000 l2
-0+0000100 l       \.foo	0+0000000 l1
-0+0000034 l       \.text	0+0000000 l3
-0+0000098 l       \.text	0+0000000 l5
-0+0000000 l    d  \.foo	0+0000000 
-0+0000004 l       \.foo	0+0000000 l4
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
-0+0000000         \*UND\*	0+0000000 g1
-0+0000000         \*UND\*	0+0000000 g2
-
-
-RELOCATION RECORDS FOR \[\.text\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL16_S2  g1
-0+000000c R_MIPS_GNU_REL16_S2  g2
-0+0000014 R_MIPS_GNU_REL16_S2  g2
-0+000001c R_MIPS_GNU_REL16_S2  \.foo
-0+0000024 R_MIPS_GNU_REL16_S2  \.text
-0+000002c R_MIPS_GNU_REL16_S2  \.foo
-0+0000034 R_MIPS_GNU_REL16_S2  \.text
-0+000003c R_MIPS_GNU_REL_HI16  g1
-0+0000040 R_MIPS_GNU_REL_LO16  g1
-0+0000044 R_MIPS_GNU_REL_HI16  \.foo
-0+0000048 R_MIPS_GNU_REL_LO16  \.foo
-0+0000050 R_MIPS_32         g1
-0+0000054 R_MIPS_32         \.foo
-0+0000058 R_MIPS_32         \.text
-0+000005c R_MIPS_PC32       g1
-0+0000060 R_MIPS_PC32       \.foo
-0+0000068 R_MIPS_64         g1
-0+0000070 R_MIPS_64         \.foo
-0+0000078 R_MIPS_64         \.text
-0+0000080 R_MIPS_PC64       g1
-0+0000088 R_MIPS_PC64       \.foo
-0+0000098 R_MIPS_GNU_REL16_S2  \.text
-0+000009c R_MIPS_GNU_REL16_S2  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  \.text
-0+00000a4 R_MIPS_GNU_REL_LO16  \.text
-0+00000a8 R_MIPS_GNU_REL_HI16  \.text
-0+00000ac R_MIPS_GNU_REL_LO16  \.text
-0+00000b0 R_MIPS_32         \.text
-0+00000b8 R_MIPS_64         \.text
-0+00000cc R_MIPS_GNU_REL16_S2  \.text
-0+00000d0 R_MIPS_GNU_REL16_S2  \.text
-0+00000d4 R_MIPS_GNU_REL_HI16  \.text
-0+00000d8 R_MIPS_GNU_REL_LO16  \.text
-0+00000dc R_MIPS_GNU_REL_HI16  \.text
-0+00000e0 R_MIPS_GNU_REL_LO16  \.text
-0+00000e4 R_MIPS_32         \.text
-0+00000f0 R_MIPS_64         \.text
-
-
-RELOCATION RECORDS FOR \[\.foo\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL_HI16  g1
-0+0000008 R_MIPS_GNU_REL_LO16  g1
-0+000000c R_MIPS_GNU_REL_HI16  \.foo
-0+0000010 R_MIPS_GNU_REL_LO16  \.foo
-0+0000014 R_MIPS_GNU_REL_HI16  \.text
-0+0000018 R_MIPS_GNU_REL_LO16  \.text
-0+000001c R_MIPS_GNU_REL_HI16  g1
-0+0000020 R_MIPS_GNU_REL_LO16  g1
-0+0000024 R_MIPS_GNU_REL_HI16  g1
-0+0000028 R_MIPS_GNU_REL_LO16  g1
-0+000002c R_MIPS_GNU_REL_HI16  \.foo
-0+0000030 R_MIPS_GNU_REL_LO16  \.foo
-0+0000034 R_MIPS_GNU_REL_HI16  \.text
-0+0000038 R_MIPS_GNU_REL_LO16  \.text
-0+000003c R_MIPS_32         g1
-0+0000040 R_MIPS_32         \.foo
-0+0000044 R_MIPS_32         \.text
-0+0000048 R_MIPS_PC32       g1
-0+0000050 R_MIPS_PC32       \.text
-0+0000058 R_MIPS_64         g1
-0+0000060 R_MIPS_64         \.foo
-0+0000068 R_MIPS_64         \.text
-0+0000070 R_MIPS_PC64       g1
-0+0000080 R_MIPS_PC64       \.text
-0+0000088 R_MIPS_GNU_REL_HI16  g1
-0+000008c R_MIPS_GNU_REL_LO16  g1
-0+0000090 R_MIPS_GNU_REL_HI16  \.foo
-0+0000094 R_MIPS_GNU_REL_LO16  \.foo
-0+0000098 R_MIPS_GNU_REL_HI16  \.text
-0+000009c R_MIPS_GNU_REL_LO16  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  g1
-0+00000a4 R_MIPS_GNU_REL_LO16  g1
-0+00000a8 R_MIPS_GNU_REL_HI16  \.foo
-0+00000ac R_MIPS_GNU_REL_LO16  \.foo
-0+00000b0 R_MIPS_GNU_REL_HI16  \.text
-0+00000b4 R_MIPS_GNU_REL_LO16  \.text
-0+00000b8 R_MIPS_32         g1
-0+00000bc R_MIPS_32         \.foo
-0+00000c0 R_MIPS_32         \.text
-0+00000c4 R_MIPS_PC32       g1
-0+00000cc R_MIPS_PC32       \.text
-0+00000d0 R_MIPS_64         g1
-0+00000d8 R_MIPS_64         \.foo
-0+00000e0 R_MIPS_64         \.text
-0+00000e8 R_MIPS_PC64       g1
-0+00000f8 R_MIPS_PC64       \.text
-
-Contents of section \.text:
- 0000 00000000 ffff1104 00000000 ffff0010  .*
- 0010 00000000 ffff0010 00000000 3f001104  .*
- 0020 00000000 00001104 00000000 41000010  .*
- 0030 00000000 00000010 00000000 0000033c  .*
- 0040 0c0063[26]4 0000033c 140163[26]4 d0ff03[26]4  .*
- 0050 00000000 00010000 04000000 28000000  .*
- 0060 2c010000 d0ffffff 00000000 00000000  .*
- 0070 00010000 00000000 04000000 00000000  .*
- 0080 4c000000 00000000 54010000 00000000  .*
- 0090 d0ffffff ffffffff 32000010 33000010  .*
- 00a0 0000033c d80063[26]4 0000033c e80063[26]4  .*
- 00b0 cc000000 34000000 cc000000 00000000  .*
- 00c0 34000000 00000000 00000000 32000010  .*
- 00d0 33000010 0000033c 0c0163[26]4 0000033c  .*
- 00e0 1c0163[26]4 cc000000 34000000 00000000  .*
- 00f0 cc000000 00000000 34000000 00000000  .*
-Contents of section \.reginfo:
- 0000 08000080 00000000 00000000 00000000  .*
- 0010 00000000 00000000                    .*
-Contents of section \.foo:
- 0000 00000000 0000033c 040063[26]4 0000033c  .*
- 0010 0c0163[26]4 0000033c 180063[26]4 0000033c  .*
- 0020 1c0063[26]4 0000033c 240063[26]4 0000033c  .*
- 0030 2c0163[26]4 0000033c 380063[26]4 00000000  .*
- 0040 00010000 04000000 44000000 fc000000  .*
- 0050 50000000 00000000 00000000 00000000  .*
- 0060 00010000 00000000 04000000 00000000  .*
- 0070 6c000000 00000000 fc000000 00000000  .*
- 0080 80000000 00000000 0000033c 8c0063[26]4  .*
- 0090 0000033c 940163[26]4 0000033c a00063[26]4  .*
- 00a0 0000033c a40063[26]4 0000033c ac0163[26]4  .*
- 00b0 0000033c b80063[26]4 04000000 04010000  .*
- 00c0 08000000 c4000000 00010000 d0000000  .*
- 00d0 04000000 00000000 04010000 00000000  .*
- 00e0 08000000 00000000 e8000000 00000000  .*
- 00f0 00010000 00000000 fc000000 00000000  .*
- 0100 00000000 00000000 00000000 00000000  .*
-
diff --git a/gas/testsuite/gas/mips/tempic.d b/gas/testsuite/gas/mips/tempic.d
deleted file mode 100644
index 07dbc966b191..000000000000
--- a/gas/testsuite/gas/mips/tempic.d
+++ /dev/null
@@ -1,155 +0,0 @@
-#objdump: -rst -mmips:4000
-#name: MIPS empic
-#as: -mabi=o64 -membedded-pic -mips3
-#source: empic.s
-#stderr: empic.l
-
-# Check GNU-specific embedded relocs, for ELF.
-
-.*: +file format elf.*mips.*
-
-SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
-0+0000004 l       \.text	0+0000000 l2
-0+0000100 l       \.foo	0+0000000 l1
-0+0000034 l       \.text	0+0000000 l3
-0+0000098 l       \.text	0+0000000 l5
-0+0000000 l    d  \.foo	0+0000000 
-0+0000004 l       \.foo	0+0000000 l4
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
-0+0000000         \*UND\*	0+0000000 g1
-0+0000000         \*UND\*	0+0000000 g2
-
-
-RELOCATION RECORDS FOR \[\.text\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL16_S2  g1
-0+000000c R_MIPS_GNU_REL16_S2  g2
-0+0000014 R_MIPS_GNU_REL16_S2  g2
-0+000001c R_MIPS_GNU_REL16_S2  \.foo
-0+0000024 R_MIPS_GNU_REL16_S2  \.text
-0+000002c R_MIPS_GNU_REL16_S2  \.foo
-0+0000034 R_MIPS_GNU_REL16_S2  \.text
-0+000003c R_MIPS_GNU_REL_HI16  g1
-0+0000040 R_MIPS_GNU_REL_LO16  g1
-0+0000044 R_MIPS_GNU_REL_HI16  \.foo
-0+0000048 R_MIPS_GNU_REL_LO16  \.foo
-0+0000050 R_MIPS_32         g1
-0+0000054 R_MIPS_32         \.foo
-0+0000058 R_MIPS_32         \.text
-0+000005c R_MIPS_PC32       g1
-0+0000060 R_MIPS_PC32       \.foo
-0+0000068 R_MIPS_64         g1
-0+0000070 R_MIPS_64         \.foo
-0+0000078 R_MIPS_64         \.text
-0+0000080 R_MIPS_PC64       g1
-0+0000088 R_MIPS_PC64       \.foo
-0+0000098 R_MIPS_GNU_REL16_S2  \.text
-0+000009c R_MIPS_GNU_REL16_S2  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  \.text
-0+00000a4 R_MIPS_GNU_REL_LO16  \.text
-0+00000a8 R_MIPS_GNU_REL_HI16  \.text
-0+00000ac R_MIPS_GNU_REL_LO16  \.text
-0+00000b0 R_MIPS_32         \.text
-0+00000b8 R_MIPS_64         \.text
-0+00000cc R_MIPS_GNU_REL16_S2  \.text
-0+00000d0 R_MIPS_GNU_REL16_S2  \.text
-0+00000d4 R_MIPS_GNU_REL_HI16  \.text
-0+00000d8 R_MIPS_GNU_REL_LO16  \.text
-0+00000dc R_MIPS_GNU_REL_HI16  \.text
-0+00000e0 R_MIPS_GNU_REL_LO16  \.text
-0+00000e4 R_MIPS_32         \.text
-0+00000f0 R_MIPS_64         \.text
-
-
-RELOCATION RECORDS FOR \[\.foo\]:
-OFFSET [ ]+ TYPE              VALUE 
-0+0000004 R_MIPS_GNU_REL_HI16  g1
-0+0000008 R_MIPS_GNU_REL_LO16  g1
-0+000000c R_MIPS_GNU_REL_HI16  \.foo
-0+0000010 R_MIPS_GNU_REL_LO16  \.foo
-0+0000014 R_MIPS_GNU_REL_HI16  \.text
-0+0000018 R_MIPS_GNU_REL_LO16  \.text
-0+000001c R_MIPS_GNU_REL_HI16  g1
-0+0000020 R_MIPS_GNU_REL_LO16  g1
-0+0000024 R_MIPS_GNU_REL_HI16  g1
-0+0000028 R_MIPS_GNU_REL_LO16  g1
-0+000002c R_MIPS_GNU_REL_HI16  \.foo
-0+0000030 R_MIPS_GNU_REL_LO16  \.foo
-0+0000034 R_MIPS_GNU_REL_HI16  \.text
-0+0000038 R_MIPS_GNU_REL_LO16  \.text
-0+000003c R_MIPS_32         g1
-0+0000040 R_MIPS_32         \.foo
-0+0000044 R_MIPS_32         \.text
-0+0000048 R_MIPS_PC32       g1
-0+0000050 R_MIPS_PC32       \.text
-0+0000058 R_MIPS_64         g1
-0+0000060 R_MIPS_64         \.foo
-0+0000068 R_MIPS_64         \.text
-0+0000070 R_MIPS_PC64       g1
-0+0000080 R_MIPS_PC64       \.text
-0+0000088 R_MIPS_GNU_REL_HI16  g1
-0+000008c R_MIPS_GNU_REL_LO16  g1
-0+0000090 R_MIPS_GNU_REL_HI16  \.foo
-0+0000094 R_MIPS_GNU_REL_LO16  \.foo
-0+0000098 R_MIPS_GNU_REL_HI16  \.text
-0+000009c R_MIPS_GNU_REL_LO16  \.text
-0+00000a0 R_MIPS_GNU_REL_HI16  g1
-0+00000a4 R_MIPS_GNU_REL_LO16  g1
-0+00000a8 R_MIPS_GNU_REL_HI16  \.foo
-0+00000ac R_MIPS_GNU_REL_LO16  \.foo
-0+00000b0 R_MIPS_GNU_REL_HI16  \.text
-0+00000b4 R_MIPS_GNU_REL_LO16  \.text
-0+00000b8 R_MIPS_32         g1
-0+00000bc R_MIPS_32         \.foo
-0+00000c0 R_MIPS_32         \.text
-0+00000c4 R_MIPS_PC32       g1
-0+00000cc R_MIPS_PC32       \.text
-0+00000d0 R_MIPS_64         g1
-0+00000d8 R_MIPS_64         \.foo
-0+00000e0 R_MIPS_64         \.text
-0+00000e8 R_MIPS_PC64       g1
-0+00000f8 R_MIPS_PC64       \.text
-
-Contents of section \.text:
- 0000 00000000 0411ffff 00000000 1000ffff  .*
- 0010 00000000 1000ffff 00000000 0411003f  .*
- 0020 00000000 04110000 00000000 10000041  .*
- 0030 00000000 10000000 00000000 3c030000  .*
- 0040 [26]463000c 3c030000 [26]4630114 [26]403ffd0  .*
- 0050 00000000 00000100 00000004 00000028  .*
- 0060 0000012c ffffffd0 00000000 00000000  .*
- 0070 00000000 00000100 00000000 00000004  .*
- 0080 00000000 0000004c 00000000 00000154  .*
- 0090 ffffffff ffffffd0 10000032 10000033  .*
- 00a0 3c030000 [26]46300d8 3c030000 [26]46300e8  .*
- 00b0 000000cc 00000034 00000000 000000cc  .*
- 00c0 00000000 00000034 00000000 10000032  .*
- 00d0 10000033 3c030000 [26]463010c 3c030000  .*
- 00e0 [26]463011c 000000cc 00000034 00000000  .*
- 00f0 00000000 000000cc 00000000 00000034  .*
-Contents of section \.reginfo:
- 0000 80000008 00000000 00000000 00000000  .*
- 0010 00000000 00000000                    .*
-Contents of section \.foo:
- 0000 00000000 3c030000 [26]4630004 3c030000  .*
- 0010 [26]463010c 3c030000 [26]4630018 3c030000  .*
- 0020 [26]463001c 3c030000 [26]4630024 3c030000  .*
- 0030 [26]463012c 3c030000 [26]4630038 00000000  .*
- 0040 00000100 00000004 00000044 000000fc  .*
- 0050 00000050 00000000 00000000 00000000  .*
- 0060 00000000 00000100 00000000 00000004  .*
- 0070 00000000 0000006c 00000000 000000fc  .*
- 0080 00000000 00000080 3c030000 [26]463008c  .*
- 0090 3c030000 [26]4630194 3c030000 [26]46300a0  .*
- 00a0 3c030000 [26]46300a4 3c030000 [26]46301ac  .*
- 00b0 3c030000 [26]46300b8 00000004 00000104  .*
- 00c0 00000008 000000c4 00000100 000000d0  .*
- 00d0 00000000 00000004 00000000 00000104  .*
- 00e0 00000000 00000008 00000000 000000e8  .*
- 00f0 00000000 00000100 00000000 000000fc  .*
- 0100 00000000 00000000 00000000 00000000  .*
-
diff --git a/gas/testsuite/gas/mips/tls-ill.l b/gas/testsuite/gas/mips/tls-ill.l
new file mode 100644
index 000000000000..1c1e73cead70
--- /dev/null
+++ b/gas/testsuite/gas/mips/tls-ill.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*:6: Error: bad expression
+.*:6: Error: illegal operands `addiu'
+.*:7: Error: bad expression
+.*:7: Error: illegal operands `addiu'
+.*:8: Error: bad expression
+.*:8: Error: missing '\)'
+.*:8: Error: illegal operands `addiu'
+.*:9: Error: bad expression
+.*:9: Error: missing '\)'
+.*:9: Error: illegal operands `addiu'
diff --git a/gas/testsuite/gas/mips/tls-ill.s b/gas/testsuite/gas/mips/tls-ill.s
new file mode 100644
index 000000000000..1632984a20b7
--- /dev/null
+++ b/gas/testsuite/gas/mips/tls-ill.s
@@ -0,0 +1,9 @@
+	.abicalls
+	.text
+
+	/* These have obvious meanings, but we don't have currently defined
+	   relocations for them.  */
+	addiu	$4,$28,%dtprel(tlsvar)
+	addiu	$4,$28,%tprel(tlsvar)
+	addiu	$4,$28,%lo(%gottprel(tlsvar))
+	addiu	$4,$28,%hi(%gottprel(tlsvar))
diff --git a/gas/testsuite/gas/mips/tls-o32.d b/gas/testsuite/gas/mips/tls-o32.d
new file mode 100644
index 000000000000..feb58ae610d4
--- /dev/null
+++ b/gas/testsuite/gas/mips/tls-o32.d
@@ -0,0 +1,55 @@
+#as: -EB -march=mips1 -mabi=32
+#objdump: -dr
+#name: MIPS ELF TLS o32
+
+dump.o:     file format elf32-.*bigmips
+
+Disassembly of section .text:
+
+00000000 <fn>:
+   0:	3c1c0000 	lui	gp,0x0
+			0: R_MIPS_HI16	_gp_disp
+   4:	279c0000 	addiu	gp,gp,0
+			4: R_MIPS_LO16	_gp_disp
+   8:	0399e021 	addu	gp,gp,t9
+   c:	27bdfff0 	addiu	sp,sp,-16
+  10:	afbe0008 	sw	s8,8\(sp\)
+  14:	03a0f021 	move	s8,sp
+  18:	afbc0000 	sw	gp,0\(sp\)
+  1c:	8f990000 	lw	t9,0\(gp\)
+			1c: R_MIPS_CALL16	__tls_get_addr
+  20:	27840000 	addiu	a0,gp,0
+			20: R_MIPS_TLS_GD	tlsvar_gd
+  24:	0320f809 	jalr	t9
+  28:	00000000 	nop
+  2c:	8fdc0000 	lw	gp,0\(s8\)
+  30:	00000000 	nop
+  34:	8f990000 	lw	t9,0\(gp\)
+			34: R_MIPS_CALL16	__tls_get_addr
+  38:	27840000 	addiu	a0,gp,0
+			38: R_MIPS_TLS_LDM	tlsvar_ld
+  3c:	0320f809 	jalr	t9
+  40:	00000000 	nop
+  44:	8fdc0000 	lw	gp,0\(s8\)
+  48:	00401021 	move	v0,v0
+  4c:	3c030000 	lui	v1,0x0
+			4c: R_MIPS_TLS_DTPREL_HI16	tlsvar_ld
+  50:	24630000 	addiu	v1,v1,0
+			50: R_MIPS_TLS_DTPREL_LO16	tlsvar_ld
+  54:	00621821 	addu	v1,v1,v0
+  58:	7c02283b 	0x7c02283b
+  5c:	8f830000 	lw	v1,0\(gp\)
+			5c: R_MIPS_TLS_GOTTPREL	tlsvar_ie
+  60:	00000000 	nop
+  64:	00621821 	addu	v1,v1,v0
+  68:	7c02283b 	0x7c02283b
+  6c:	3c030000 	lui	v1,0x0
+			6c: R_MIPS_TLS_TPREL_HI16	tlsvar_le
+  70:	34630000 	ori	v1,v1,0x0
+			70: R_MIPS_TLS_TPREL_LO16	tlsvar_le
+  74:	00621821 	addu	v1,v1,v0
+  78:	03c0e821 	move	sp,s8
+  7c:	8fbe0008 	lw	s8,8\(sp\)
+  80:	03e00008 	jr	ra
+  84:	27bd0010 	addiu	sp,sp,16
+#pass
diff --git a/gas/testsuite/gas/mips/tls-o32.s b/gas/testsuite/gas/mips/tls-o32.s
new file mode 100644
index 000000000000..a4c3e379dcfd
--- /dev/null
+++ b/gas/testsuite/gas/mips/tls-o32.s
@@ -0,0 +1,85 @@
+	.file	1 "tls.s"
+	.abicalls
+	.text
+	.align	2
+	.globl	fn
+	.ent	fn
+	.type	fn,@function
+fn:
+	.frame	$fp,16,$31
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	addiu	$sp,$sp,-16
+	sw	$fp,8($sp)
+	move	$fp,$sp
+	.cprestore	0
+
+	# General Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	jal	$25
+
+	# Local Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsldm(tlsvar_ld)
+	jal	$25
+
+	move	$2,$2		# Arbitrary instructions
+
+	lui	$3,%dtprel_hi(tlsvar_ld)
+	addiu	$3,$3,%dtprel_lo(tlsvar_ld)
+	addu	$3,$3,$2
+
+	# Initial Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lw	$3,%gottprel(tlsvar_ie)($28)
+	addu	$3,$3,$2
+
+	# Local Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lui	$3,%tprel_hi(tlsvar_le)
+	ori	$3,$3,%tprel_lo(tlsvar_le)
+	addu	$3,$3,$2
+
+	move	$sp,$fp
+	lw	$fp,8($sp)
+	addiu	$sp,$sp,16
+	j	$31
+	.end	fn
+
+	.section		.tbss,"awT",@nobits
+	.align	2
+	.global	tlsvar_gd
+	.type	tlsvar_gd,@object
+	.size	tlsvar_gd,4
+tlsvar_gd:
+	.space	4
+	.global	tlsvar_ie
+	.type	tlsvar_ie,@object
+	.size	tlsvar_ie,4
+tlsvar_ie:
+	.space	4
+
+	.section		.tdata,"awT"
+	.align	2
+	.global	tlsvar_ld
+	.hidden	tlsvar_ld
+	.type	tlsvar_ld,@object
+	.size	tlsvar_ld,4
+tlsvar_ld:
+	.word	1
+	.global	tlsvar_le
+	.hidden	tlsvar_le
+	.type	tlsvar_le,@object
+	.size	tlsvar_le,4
+tlsvar_le:
+	.word	1
diff --git a/gas/testsuite/gas/mips/tmips16-e.d b/gas/testsuite/gas/mips/tmips16-e.d
index cf62fab8d56e..b03c6bb4f04b 100644
--- a/gas/testsuite/gas/mips/tmips16-e.d
+++ b/gas/testsuite/gas/mips/tmips16-e.d
@@ -8,14 +8,14 @@
 .*: +file format elf.*mips.*
 
 SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
+0+0000000 l    d  \.text	0+0000000 (|\.text)
+0+0000000 l    d  \.data	0+0000000 (|\.data)
+0+0000000 l    d  \.bss	0+0000000 (|\.bss)
 0+0000002 l       \.text	0+0000000 0xf0 l1
 0+0000004 l       \.text	0+0000000 0xf0 L1.1
-0+0000000 l    d  foo	0+0000000 
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
+0+0000000 l    d  foo	0+0000000 (|foo)
+0+0000000 l    d  \.reginfo	0+0000000 (|\.reginfo)
+0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (|\.mdebug|\.pdr)
 0+0000000         \*UND\*	0+0000000 g1
 
 
diff --git a/gas/testsuite/gas/mips/tmips16-f.d b/gas/testsuite/gas/mips/tmips16-f.d
index d2197f034917..8e3304ca9b48 100644
--- a/gas/testsuite/gas/mips/tmips16-f.d
+++ b/gas/testsuite/gas/mips/tmips16-f.d
@@ -8,13 +8,13 @@
 .*: +file format elf.*mips.*
 
 SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
+0+0000000 l    d  \.text	0+0000000 (|\.text)
+0+0000000 l    d  \.data	0+0000000 (|\.data)
+0+0000000 l    d  \.bss	0+0000000 (|\.bss)
 0+0000002 l       \.text	0+0000000 0xf0 l1
-0+0000000 l    d  foo	0+0000000 
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
+0+0000000 l    d  foo	0+0000000 (|foo)
+0+0000000 l    d  \.reginfo	0+0000000 (|\.reginfo)
+0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (|\.mdebug|\.pdr)
 
 
 RELOCATION RECORDS FOR \[foo\]:
diff --git a/gas/testsuite/gas/mips/tmipsel16-e.d b/gas/testsuite/gas/mips/tmipsel16-e.d
index 7495811825d3..089b27ea559b 100644
--- a/gas/testsuite/gas/mips/tmipsel16-e.d
+++ b/gas/testsuite/gas/mips/tmipsel16-e.d
@@ -8,14 +8,14 @@
 .*: +file format elf.*mips.*
 
 SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
+0+0000000 l    d  \.text	0+0000000 (|\.text)
+0+0000000 l    d  \.data	0+0000000 (|\.data)
+0+0000000 l    d  \.bss	0+0000000 (|\.bss)
 0+0000002 l       \.text	0+0000000 0xf0 l1
 0+0000004 l       \.text	0+0000000 0xf0 L1.1
-0+0000000 l    d  foo	0+0000000 
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
+0+0000000 l    d  foo	0+0000000 (|foo)
+0+0000000 l    d  \.reginfo	0+0000000 (|\.reginfo)
+0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (|\.mdebug|\.pdr)
 0+0000000         \*UND\*	0+0000000 g1
 
 
diff --git a/gas/testsuite/gas/mips/tmipsel16-f.d b/gas/testsuite/gas/mips/tmipsel16-f.d
index 032a7962d16f..3c21e2d3d752 100644
--- a/gas/testsuite/gas/mips/tmipsel16-f.d
+++ b/gas/testsuite/gas/mips/tmipsel16-f.d
@@ -8,13 +8,13 @@
 .*: +file format elf.*mips.*
 
 SYMBOL TABLE:
-0+0000000 l    d  \.text	0+0000000 
-0+0000000 l    d  \.data	0+0000000 
-0+0000000 l    d  \.bss	0+0000000 
+0+0000000 l    d  \.text	0+0000000 (|\.text)
+0+0000000 l    d  \.data	0+0000000 (|\.data)
+0+0000000 l    d  \.bss	0+0000000 (|\.bss)
 0+0000002 l       \.text	0+0000000 0xf0 l1
-0+0000000 l    d  foo	0+0000000 
-0+0000000 l    d  \.reginfo	0+0000000 
-0+0000000 l    d  \.(mdebug|pdr)	0+0000000 
+0+0000000 l    d  foo	0+0000000 (|foo)
+0+0000000 l    d  \.reginfo	0+0000000 (\.reginfo)
+0+0000000 l    d  \.(mdebug|pdr)	0+0000000 (\.mdebug|\.pdr)
 
 
 RELOCATION RECORDS FOR \[foo\]:
diff --git a/gas/testsuite/gas/mips/uld2-eb.d b/gas/testsuite/gas/mips/uld2-eb.d
index 815da74b4723..8a4d37c5dfe9 100644
--- a/gas/testsuite/gas/mips/uld2-eb.d
+++ b/gas/testsuite/gas/mips/uld2-eb.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: uld2 -EB
 #source: uld2.s
-#stderr: uld2.l
 
 # Further checks of uld macro.
 # XXX: note: when 'move' is changed to use 'or' rather than daddu, the
diff --git a/gas/testsuite/gas/mips/uld2-el.d b/gas/testsuite/gas/mips/uld2-el.d
index 7b0032e0faba..e932f353c964 100644
--- a/gas/testsuite/gas/mips/uld2-el.d
+++ b/gas/testsuite/gas/mips/uld2-el.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: uld2 -EL
 #source: uld2.s
-#stderr: uld2.l
 
 # Further checks of uld macro.
 # XXX: note: when 'move' is changed to use 'or' rather than daddu, the
diff --git a/gas/testsuite/gas/mips/uld2.l b/gas/testsuite/gas/mips/uld2.l
deleted file mode 100644
index 1ab29b544b31..000000000000
--- a/gas/testsuite/gas/mips/uld2.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*:11: Warning: Macro used \$at after "\.set noat"
-.*:12: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/uld2.s b/gas/testsuite/gas/mips/uld2.s
index 5b0d99bf6071..2156136a232f 100644
--- a/gas/testsuite/gas/mips/uld2.s
+++ b/gas/testsuite/gas/mips/uld2.s
@@ -1,7 +1,5 @@
 # Source file used to test the uld macro (harder).
 	
-	.set noat
-	
 	.text
 text_label:
 
diff --git a/gas/testsuite/gas/mips/ulh-empic.d b/gas/testsuite/gas/mips/ulh-empic.d
deleted file mode 100644
index 1f1a337d78c8..000000000000
--- a/gas/testsuite/gas/mips/ulh-empic.d
+++ /dev/null
@@ -1,91 +0,0 @@
-#objdump: -dr --prefix-addresses -mmips:3000
-#name: MIPS ulh-empic
-#as: -32 -mips1 -membedded-pic
-#source: ulh-pic.s
-
-# Test the ulh macro with -membedded-pic.
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> addiu	at,gp,-16384
-[ 	]*0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0004 <[^>]*> lb	a0,[01]\(at\)
-0+0008 <[^>]*> lbu	at,[01]\(at\)
-0+000c <[^>]*> sll	a0,a0,0x8
-0+0010 <[^>]*> or	a0,a0,at
-0+0014 <[^>]*> addiu	at,gp,0
-[ 	]*14: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0018 <[^>]*> lbu	a0,[01]\(at\)
-0+001c <[^>]*> lbu	at,[01]\(at\)
-0+0020 <[^>]*> sll	a0,a0,0x8
-0+0024 <[^>]*> or	a0,a0,at
-0+0028 <[^>]*> addiu	at,gp,0
-[ 	]*28: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+002c <[^>]*> lwl	a0,[03]\(at\)
-0+0030 <[^>]*> lwr	a0,[03]\(at\)
-0+0034 <[^>]*> addiu	at,gp,0
-[ 	]*34: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+0038 <[^>]*> sb	a0,[01]\(at\)
-0+003c <[^>]*> srl	a0,a0,0x8
-0+0040 <[^>]*> sb	a0,[01]\(at\)
-0+0044 <[^>]*> lbu	at,[01]\(at\)
-0+0048 <[^>]*> sll	a0,a0,0x8
-0+004c <[^>]*> or	a0,a0,at
-0+0050 <[^>]*> addiu	at,gp,0
-[ 	]*50: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+0054 <[^>]*> swl	a0,[03]\(at\)
-0+0058 <[^>]*> swr	a0,[03]\(at\)
-0+005c <[^>]*> addiu	at,gp,-16384
-[ 	]*5c: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0060 <[^>]*> lb	a0,[01]\(at\)
-0+0064 <[^>]*> lbu	at,[01]\(at\)
-0+0068 <[^>]*> sll	a0,a0,0x8
-0+006c <[^>]*> or	a0,a0,at
-0+0070 <[^>]*> addiu	at,gp,-15384
-[ 	]*70: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+0074 <[^>]*> lbu	a0,[01]\(at\)
-0+0078 <[^>]*> lbu	at,[01]\(at\)
-0+007c <[^>]*> sll	a0,a0,0x8
-0+0080 <[^>]*> or	a0,a0,at
-0+0084 <[^>]*> addiu	at,gp,-16383
-[ 	]*84: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sdata.*
-0+0088 <[^>]*> lwl	a0,[03]\(at\)
-0+008c <[^>]*> lwr	a0,[03]\(at\)
-0+0090 <[^>]*> addiu	at,gp,1
-[ 	]*90: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_data_label
-0+0094 <[^>]*> sb	a0,[01]\(at\)
-0+0098 <[^>]*> srl	a0,a0,0x8
-0+009c <[^>]*> sb	a0,[01]\(at\)
-0+00a0 <[^>]*> lbu	at,[01]\(at\)
-0+00a4 <[^>]*> sll	a0,a0,0x8
-0+00a8 <[^>]*> or	a0,a0,at
-0+00ac <[^>]*> addiu	at,gp,1
-[ 	]*ac: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_data_label
-0+00b0 <[^>]*> swl	a0,[03]\(at\)
-0+00b4 <[^>]*> swr	a0,[03]\(at\)
-0+00b8 <[^>]*> addiu	at,gp,1
-[ 	]*b8: [A-Z0-9_]*GPREL[A-Z0-9_]*	big_external_common
-0+00bc <[^>]*> lb	a0,[01]\(at\)
-0+00c0 <[^>]*> lbu	at,[01]\(at\)
-0+00c4 <[^>]*> sll	a0,a0,0x8
-0+00c8 <[^>]*> or	a0,a0,at
-0+00cc <[^>]*> addiu	at,gp,1
-[ 	]*cc: [A-Z0-9_]*GPREL[A-Z0-9_]*	small_external_common
-0+00d0 <[^>]*> lbu	a0,[01]\(at\)
-0+00d4 <[^>]*> lbu	at,[01]\(at\)
-0+00d8 <[^>]*> sll	a0,a0,0x8
-0+00dc <[^>]*> or	a0,a0,at
-0+00e0 <[^>]*> addiu	at,gp,-16383
-[ 	]*e0: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00e4 <[^>]*> lwl	a0,[03]\(at\)
-0+00e8 <[^>]*> lwr	a0,[03]\(at\)
-0+00ec <[^>]*> addiu	at,gp,-15383
-[ 	]*ec: [A-Z0-9_]*GPREL[A-Z0-9_]*	.sbss.*
-0+00f0 <[^>]*> sb	a0,[01]\(at\)
-0+00f4 <[^>]*> srl	a0,a0,0x8
-0+00f8 <[^>]*> sb	a0,[01]\(at\)
-0+00fc <[^>]*> lbu	at,[01]\(at\)
-0+0100 <[^>]*> sll	a0,a0,0x8
-0+0104 <[^>]*> or	a0,a0,at
-	...
diff --git a/gas/testsuite/gas/mips/ulh2-eb.d b/gas/testsuite/gas/mips/ulh2-eb.d
index 9c8e84c699be..ee73ba8ca88c 100644
--- a/gas/testsuite/gas/mips/ulh2-eb.d
+++ b/gas/testsuite/gas/mips/ulh2-eb.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulh2 -EB
 #source: ulh2.s
-#stderr: ulh2.l
 
 # Further checks of ulh/ulhu macros.
 
diff --git a/gas/testsuite/gas/mips/ulh2-el.d b/gas/testsuite/gas/mips/ulh2-el.d
index e8e47e8b4198..bc61b5d2f24c 100644
--- a/gas/testsuite/gas/mips/ulh2-el.d
+++ b/gas/testsuite/gas/mips/ulh2-el.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulh2 -EL
 #source: ulh2.s
-#stderr: ulh2.l
 
 # Further checks of ulh/ulhu macros.
 
diff --git a/gas/testsuite/gas/mips/ulh2.l b/gas/testsuite/gas/mips/ulh2.l
deleted file mode 100644
index 4bab367829be..000000000000
--- a/gas/testsuite/gas/mips/ulh2.l
+++ /dev/null
@@ -1,9 +0,0 @@
-.*: Assembler messages:
-.*:8: Warning: Macro used \$at after "\.set noat"
-.*:9: Warning: Macro used \$at after "\.set noat"
-.*:11: Warning: Macro used \$at after "\.set noat"
-.*:12: Warning: Macro used \$at after "\.set noat"
-.*:14: Warning: Macro used \$at after "\.set noat"
-.*:15: Warning: Macro used \$at after "\.set noat"
-.*:17: Warning: Macro used \$at after "\.set noat"
-.*:18: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/ulh2.s b/gas/testsuite/gas/mips/ulh2.s
index 3aa1cff722e7..0c200904edce 100644
--- a/gas/testsuite/gas/mips/ulh2.s
+++ b/gas/testsuite/gas/mips/ulh2.s
@@ -1,7 +1,5 @@
 # Source file used to test the ulh and ulhu macros (harder).
 
-	.set noat
-	
 	.text
 text_label:
 
diff --git a/gas/testsuite/gas/mips/ulw2-eb-ilocks.d b/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
index 83796ef621cf..f967aa203f61 100644
--- a/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
+++ b/gas/testsuite/gas/mips/ulw2-eb-ilocks.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulw2 -EB interlocked
 #source: ulw2.s
-#stderr: ulw2.l
 
 # Further checks of ulw macro.
 # XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
diff --git a/gas/testsuite/gas/mips/ulw2-eb.d b/gas/testsuite/gas/mips/ulw2-eb.d
index 88839bd48c00..934136910138 100644
--- a/gas/testsuite/gas/mips/ulw2-eb.d
+++ b/gas/testsuite/gas/mips/ulw2-eb.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulw2 -EB non-interlocked
 #source: ulw2.s
-#stderr: ulw2.l
 
 # Further checks of ulw macro.
 # XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
diff --git a/gas/testsuite/gas/mips/ulw2-el-ilocks.d b/gas/testsuite/gas/mips/ulw2-el-ilocks.d
index cc96c620162d..5e08cef86176 100644
--- a/gas/testsuite/gas/mips/ulw2-el-ilocks.d
+++ b/gas/testsuite/gas/mips/ulw2-el-ilocks.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulw2 -EL interlocked
 #source: ulw2.s
-#stderr: ulw2.l
 
 # Further checks of ulw macro.
 # XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
diff --git a/gas/testsuite/gas/mips/ulw2-el.d b/gas/testsuite/gas/mips/ulw2-el.d
index 6abd4d042414..75bf40803e78 100644
--- a/gas/testsuite/gas/mips/ulw2-el.d
+++ b/gas/testsuite/gas/mips/ulw2-el.d
@@ -2,7 +2,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
 #name: ulw2 -EL non-interlocked
 #source: ulw2.s
-#stderr: ulw2.l
 
 # Further checks of ulw macro.
 # XXX: note: when 'move' is changed to use 'or' rather than addu/daddu, the
diff --git a/gas/testsuite/gas/mips/ulw2.l b/gas/testsuite/gas/mips/ulw2.l
deleted file mode 100644
index 1ab29b544b31..000000000000
--- a/gas/testsuite/gas/mips/ulw2.l
+++ /dev/null
@@ -1,3 +0,0 @@
-.*: Assembler messages:
-.*:11: Warning: Macro used \$at after "\.set noat"
-.*:12: Warning: Macro used \$at after "\.set noat"
diff --git a/gas/testsuite/gas/mips/ulw2.s b/gas/testsuite/gas/mips/ulw2.s
index f4373dc330c5..3e90a6b3c337 100644
--- a/gas/testsuite/gas/mips/ulw2.s
+++ b/gas/testsuite/gas/mips/ulw2.s
@@ -1,7 +1,5 @@
 # Source file used to test the ulw macro (harder).
 	
-	.set noat
-	
 	.text
 text_label:
 
diff --git a/gas/testsuite/gas/mips/vr4120-2.d b/gas/testsuite/gas/mips/vr4120-2.d
new file mode 100644
index 000000000000..ec6efd943925
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4120-2.d
@@ -0,0 +1,172 @@
+#objdump: -dz --prefix-addresses -m mips:4120
+#as: -32 -march=vr4120 -mfix-vr4120
+#name: MIPS vr4120 workarounds
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> div	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> div	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> divu	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> divu	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> ddiv	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> ddiv	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> ddivu	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> ddivu	zero,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmult	a2,a3
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmultu	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmultu	a2,a3
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a2,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a2,a3,t0
+.* <[^>]*> or	a0,a0,a1
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mtlo	a3
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mtlo	a3
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mthi	a3
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mthi	a3
+#
+# vr4181a_md1:
+#
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mult	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> multu	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> dmultu	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> mult	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> multu	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> nop
+.* <[^>]*> dmultu	a0,a1
+.* <[^>]*> or	a0,a0,a1
+#
+# vr4181a_md4:
+#
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmultu	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> div	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> divu	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> ddiv	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> ddivu	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> macc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmult	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> dmultu	a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> div	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> divu	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> ddiv	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#
+.* <[^>]*> ddivu	zero,a0,a1
+.* <[^>]*> nop
+.* <[^>]*> dmacc	a0,a1,a2
+.* <[^>]*> or	a0,a0,a1
+#...
diff --git a/gas/testsuite/gas/mips/vr4120-2.s b/gas/testsuite/gas/mips/vr4120-2.s
new file mode 100644
index 000000000000..1e5d606083ab
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4120-2.s
@@ -0,0 +1,147 @@
+# Test workarounds selected by -mfix-vr4120.
+# Note that we only work around bugs gcc may generate.
+
+r21:
+	macc	$4,$5,$6
+	div	$0,$7,$8
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	div	$0,$7,$8
+	or	$4,$5
+
+	macc	$4,$5,$6
+	divu	$0,$7,$8
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	divu	$0,$7,$8
+	or	$4,$5
+
+	macc	$4,$5,$6
+	ddiv	$0,$7,$8
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	ddiv	$0,$7,$8
+	or	$4,$5
+
+	macc	$4,$5,$6
+	ddivu	$0,$7,$8
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	ddivu	$0,$7,$8
+	or	$4,$5
+
+r23:
+	dmult	$4,$5
+	dmult	$6,$7
+	or	$4,$5
+
+	dmultu	$4,$5
+	dmultu	$6,$7
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	dmacc	$6,$7,$8
+	or	$4,$5
+
+	dmult	$4,$5
+	dmacc	$6,$7,$8
+	or	$4,$5
+
+r24:
+	macc	$4,$5,$6
+	mtlo	$7
+
+	dmacc	$4,$5,$6
+	mtlo	$7
+
+	macc	$4,$5,$6
+	mthi	$7
+
+	dmacc	$4,$5,$6
+	mthi	$7
+
+vr4181a_md1:
+	macc	$4,$5,$6
+	mult	$4,$5
+	or	$4,$5
+
+	macc	$4,$5,$6
+	multu	$4,$5
+	or	$4,$5
+
+	macc	$4,$5,$6
+	dmult	$4,$5
+	or	$4,$5
+
+	macc	$4,$5,$6
+	dmultu	$4,$5
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	mult	$4,$5
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	multu	$4,$5
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	dmult	$4,$5
+	or	$4,$5
+
+	dmacc	$4,$5,$6
+	dmultu	$4,$5
+	or	$4,$5
+
+vr4181a_md4:
+	dmult	$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	dmultu	$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	div	$0,$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	divu	$0,$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	ddiv	$0,$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	ddivu	$0,$4,$5
+	macc	$4,$5,$6
+	or	$4,$5
+
+	dmult	$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
+
+	dmultu	$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
+
+	div	$0,$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
+
+	divu	$0,$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
+
+	ddiv	$0,$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
+
+	ddivu	$0,$4,$5
+	dmacc	$4,$5,$6
+	or	$4,$5
diff --git a/gas/testsuite/gas/mips/vr4122.d b/gas/testsuite/gas/mips/vr4122.d
deleted file mode 100644
index 99e0043dd2f4..000000000000
--- a/gas/testsuite/gas/mips/vr4122.d
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -dz --prefix-addresses -m mips:4120
-#as: -32 -march=vr4120 -mfix-vr4120
-#name: MIPS vr4120 workarounds
-
-.*: +file format .*mips.*
-
-Disassembly of section .text:
-0+0000 <[^>]*> macc	a0,a1,a2
-0+0004 <[^>]*> nop
-0+0008 <[^>]*> div	zero,a3,t0
-0+000c <[^>]*> or	a0,a0,a1
-0+0010 <[^>]*> dmacc	a0,a1,a2
-0+0014 <[^>]*> nop
-0+0018 <[^>]*> div	zero,a3,t0
-0+001c <[^>]*> or	a0,a0,a1
-0+0020 <[^>]*> macc	a0,a1,a2
-0+0024 <[^>]*> nop
-0+0028 <[^>]*> divu	zero,a3,t0
-0+002c <[^>]*> or	a0,a0,a1
-0+0030 <[^>]*> dmacc	a0,a1,a2
-0+0034 <[^>]*> nop
-0+0038 <[^>]*> divu	zero,a3,t0
-0+003c <[^>]*> or	a0,a0,a1
-0+0040 <[^>]*> macc	a0,a1,a2
-0+0044 <[^>]*> nop
-0+0048 <[^>]*> ddiv	zero,a3,t0
-0+004c <[^>]*> or	a0,a0,a1
-0+0050 <[^>]*> dmacc	a0,a1,a2
-0+0054 <[^>]*> nop
-0+0058 <[^>]*> ddiv	zero,a3,t0
-0+005c <[^>]*> or	a0,a0,a1
-0+0060 <[^>]*> macc	a0,a1,a2
-0+0064 <[^>]*> nop
-0+0068 <[^>]*> ddivu	zero,a3,t0
-0+006c <[^>]*> or	a0,a0,a1
-0+0070 <[^>]*> dmacc	a0,a1,a2
-0+0074 <[^>]*> nop
-0+0078 <[^>]*> ddivu	zero,a3,t0
-0+007c <[^>]*> or	a0,a0,a1
-0+0080 <[^>]*> dmult	a0,a1
-0+0084 <[^>]*> nop
-0+0088 <[^>]*> dmult	a2,a3
-0+008c <[^>]*> or	a0,a0,a1
-0+0090 <[^>]*> dmultu	a0,a1
-0+0094 <[^>]*> nop
-0+0098 <[^>]*> dmultu	a2,a3
-0+009c <[^>]*> or	a0,a0,a1
-0+00a0 <[^>]*> dmacc	a0,a1,a2
-0+00a4 <[^>]*> nop
-0+00a8 <[^>]*> dmacc	a2,a3,t0
-0+00ac <[^>]*> or	a0,a0,a1
-0+00b0 <[^>]*> dmult	a0,a1
-0+00b4 <[^>]*> nop
-0+00b8 <[^>]*> dmacc	a2,a3,t0
-0+00bc <[^>]*> or	a0,a0,a1
-0+00c0 <[^>]*> macc	a0,a1,a2
-0+00c4 <[^>]*> nop
-0+00c8 <[^>]*> mtlo	a3
-0+00cc <[^>]*> dmacc	a0,a1,a2
-0+00d0 <[^>]*> nop
-0+00d4 <[^>]*> mtlo	a3
-0+00d8 <[^>]*> macc	a0,a1,a2
-0+00dc <[^>]*> nop
-0+00e0 <[^>]*> mthi	a3
-0+00e4 <[^>]*> dmacc	a0,a1,a2
-0+00e8 <[^>]*> nop
-0+00ec <[^>]*> mthi	a3
-#...
diff --git a/gas/testsuite/gas/mips/vr4122.s b/gas/testsuite/gas/mips/vr4122.s
deleted file mode 100644
index 4661e1a0ebd2..000000000000
--- a/gas/testsuite/gas/mips/vr4122.s
+++ /dev/null
@@ -1,65 +0,0 @@
-# Test workarounds selected by -mfix-vr4120.
-# Note that we only work around bugs gcc may generate.
-
-r21:
-	macc	$4,$5,$6
-	div	$0,$7,$8
-	or	$4,$5
-
-	dmacc	$4,$5,$6
-	div	$0,$7,$8
-	or	$4,$5
-
-	macc	$4,$5,$6
-	divu	$0,$7,$8
-	or	$4,$5
-
-	dmacc	$4,$5,$6
-	divu	$0,$7,$8
-	or	$4,$5
-
-	macc	$4,$5,$6
-	ddiv	$0,$7,$8
-	or	$4,$5
-
-	dmacc	$4,$5,$6
-	ddiv	$0,$7,$8
-	or	$4,$5
-
-	macc	$4,$5,$6
-	ddivu	$0,$7,$8
-	or	$4,$5
-
-	dmacc	$4,$5,$6
-	ddivu	$0,$7,$8
-	or	$4,$5
-
-r23:
-	dmult	$4,$5
-	dmult	$6,$7
-	or	$4,$5
-
-	dmultu	$4,$5
-	dmultu	$6,$7
-	or	$4,$5
-
-	dmacc	$4,$5,$6
-	dmacc	$6,$7,$8
-	or	$4,$5
-
-	dmult	$4,$5
-	dmacc	$6,$7,$8
-	or	$4,$5
-
-r24:
-	macc	$4,$5,$6
-	mtlo	$7
-
-	dmacc	$4,$5,$6
-	mtlo	$7
-
-	macc	$4,$5,$6
-	mthi	$7
-
-	dmacc	$4,$5,$6
-	mthi	$7
diff --git a/gas/testsuite/gas/mips/vr4130.d b/gas/testsuite/gas/mips/vr4130.d
new file mode 100644
index 000000000000..4933d4d9d290
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4130.d
@@ -0,0 +1,705 @@
+#as: -mfix-vr4130 -march=vr4130 -mabi=o64
+#objdump: -dz
+#name: MIPS VR4130 workarounds
+
+.*file format.*
+
+Disassembly.*
+
+.* <foo>:
+#
+# PART A
+#
+.*	mfhi	.*
+.*	mult	.*
+#
+.*	mflo	.*
+.*	mult	.*
+#
+# PART B
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART C
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART D
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+# PART E
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+# PART F
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	nop
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+.*	addiu	.*
+#
+# PART G
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART H
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART I
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	multu	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmultu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	div	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	divu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddiv	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddivu	.*
+#
+# PART J
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macc	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchi	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchis	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchiu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	macchius	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccs	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	maccus	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacc	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchi	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchis	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchiu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmacchius	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccs	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmaccus	.*
+#
+# PART K
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	mtlo	.*
+#
+.*	mflo	.*
+.*	mthi	.*
+#
+.*	mfhi	.*
+.*	mtlo	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mthi	.*
+
+.* <bar>:
+#
+# PART A
+#
+.*	mfhi	.*
+.*	mult	.*
+#
+.*	mflo	.*
+.*	mult	.*
+#
+# PART B
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART C
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART D
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+# PART E
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+#
+# PART F
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	bnez	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	bnez	.*
+#
+# PART G
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART H
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	nop
+.*	nop
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+.*	mfhi	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	addiu	.*
+.*	mult	.*
+#
+# PART I
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	mult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	multu	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmult	.*
+#
+.*	mflo	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	dmultu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	div	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	divu	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddiv	.*
+#
+.*	mfhi	.*
+.*	nop
+.*	nop
+.*	nop
+.*	nop
+.*	ddivu	.*
+#pass
diff --git a/gas/testsuite/gas/mips/vr4130.s b/gas/testsuite/gas/mips/vr4130.s
new file mode 100644
index 000000000000..1f1dfcf04f77
--- /dev/null
+++ b/gas/testsuite/gas/mips/vr4130.s
@@ -0,0 +1,305 @@
+	.macro	check2 insn
+	mflo	$2
+	\insn	$3,$3
+	.endm
+
+	.macro	check3 insn
+	mfhi	$2
+	\insn	$0,$3,$3
+	.endm
+
+	.macro	main func
+
+	.ent	\func
+	.type	\func,@function
+\func:
+
+	# PART A
+	#
+	# Check that mfhis and mflos in .set noreorder blocks are not
+	# considered.
+
+	.set	noreorder
+	mfhi	$2
+	.set	reorder
+	mult	$3,$3
+
+	.set	noreorder
+	mflo	$2
+	.set	reorder
+	mult	$3,$3
+
+	# PART B
+	#
+	# Check for simple instances.
+
+	mfhi	$2
+	mult	$3,$3	# 4 nops
+
+	mfhi	$2
+	addiu	$3,1
+	mult	$4,$4	# 3 nops
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	mult	$7,$7	# 0 nops
+
+	# PART C
+	#
+	# Check that no nops are inserted after the result has been read.
+
+	mfhi	$2
+	addiu	$2,1
+	addiu	$3,1
+	addiu	$4,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$2,1
+	addiu	$4,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$2,1
+	mult	$5,$5
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$2,$2
+
+	# PART D
+	#
+	# Check that we still insert the usual interlocking nops in cases
+	# where the VR4130 errata doesn't apply.
+
+	mfhi	$2
+	mult	$2,$2	# 2 nops
+
+	mfhi	$2
+	addiu	$2,1
+	mult	$3,$3	# 1 nop
+
+	mfhi	$2
+	addiu	$3,1
+	mult	$2,$2	# 1 nop
+
+	# PART E
+	#
+	# Check for branches whose targets might be affected.
+
+	mfhi	$2
+	bnez	$3,1f	# 2 nops for normal mode, 3 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	bnez	$3,1f	# 1 nop for normal mode, 2 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$3,1
+	bnez	$3,1f	# 0 nops for normal mode, 1 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$3,1
+	addiu	$3,1
+	bnez	$3,1f	# 0 nops
+
+	# PART F
+	#
+	# As above, but with no dependencies between the branch and
+	# the previous instruction.  The final branch can use the
+	# preceding addiu as its delay slot.
+
+	mfhi	$2
+	addiu	$3,1
+	bnez	$4,1f	# 1 nop for normal mode, 2 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	bnez	$5,1f	# 0 nops for normal mode, 1 for mips16
+
+	mfhi	$2
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	bnez	$6,1f	# 0 nops, fill delay slot in normal mode
+1:
+
+	# PART G
+	#
+	# Like part B, but check that intervening .set noreorders don't
+	# affect the number of nops.
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	.set	reorder
+	mult	$4,$4	# 3 nops
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	.set	reorder
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	.set	reorder
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	.set	reorder
+	mult	$5,$5	# 2 nops
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	.set	reorder
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	.set	reorder
+	mult	$6,$6	# 1 nop
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	.set	reorder
+	mult	$7,$7	# 0 nops
+
+	# PART H
+	#
+	# Like part B, but the mult occurs in a .set noreorder block.
+
+	mfhi	$2
+	.set	noreorder
+	mult	$3,$3	# 4 nops
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	mult	$4,$4	# 3 nops
+	.set	reorder
+
+	mfhi	$2
+	addiu	$3,1
+	.set	noreorder
+	addiu	$4,1
+	mult	$5,$5	# 2 nops
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	mult	$6,$6	# 1 nop
+	.set	reorder
+
+	mfhi	$2
+	.set	noreorder
+	addiu	$3,1
+	addiu	$4,1
+	addiu	$5,1
+	addiu	$6,1
+	mult	$7,$7	# 0 nops
+	.set	reorder
+
+	# PART I
+	#
+	# Check every affected multiplication and division instruction.
+
+	check2	mult
+	check2	multu
+	check2	dmult
+	check2	dmultu
+
+	check3	div
+	check3	divu
+	check3	ddiv
+	check3	ddivu
+
+	.end	\func
+	.endm
+
+	.set	nomips16
+	main	foo
+
+	# PART J
+	#
+	# Check every affected multiply-accumulate instruction.
+
+	check3	macc
+	check3	macchi
+	check3	macchis
+	check3	macchiu
+	check3	macchius
+	check3	maccs
+	check3	maccu
+	check3	maccus
+
+	check3	dmacc
+	check3	dmacchi
+	check3	dmacchis
+	check3	dmacchiu
+	check3	dmacchius
+	check3	dmaccs
+	check3	dmaccu
+	check3	dmaccus
+
+	# PART K
+	#
+	# Check that mtlo and mthi are exempt from the VR4130 errata,
+	# although the usual interlocking delay applies.
+
+	mflo	$2
+	mtlo	$3
+
+	mflo	$2
+	mthi	$3
+
+	mfhi	$2
+	mtlo	$3
+
+	mfhi	$2
+	mthi	$3
+
+	.set	mips16
+	main	bar
diff --git a/gas/testsuite/gas/mips/vr5400.d b/gas/testsuite/gas/mips/vr5400.d
index 110490a6b273..c13591cdd22d 100644
--- a/gas/testsuite/gas/mips/vr5400.d
+++ b/gas/testsuite/gas/mips/vr5400.d
@@ -119,7 +119,7 @@ Disassembly of section \.text:
 0+01bc <stuff\+0x1bc> rzu\.ob	\$f2,0xd
 0+01c0 <stuff\+0x1c0> rach\.ob	\$f2
 0+01c4 <stuff\+0x1c4> racl\.ob	\$f2
-0+01c8 <stuff\+0x1c8> bc2f	0+04c8 <stuff\+0x4c8>
+0+01c8 <stuff\+0x1c8> racm\.ob	\$f2
 0+01cc <stuff\+0x1cc> wach\.ob	\$f2
 0+01d0 <stuff\+0x1d0> wacl\.ob	\$f2,\$f4
 0+01d4 <stuff\+0x1d4> rorv	a0,a1,a2
diff --git a/gas/testsuite/gas/mips/vxworks1-el.d b/gas/testsuite/gas/mips/vxworks1-el.d
new file mode 100644
index 000000000000..3db07e4a17da
--- /dev/null
+++ b/gas/testsuite/gas/mips/vxworks1-el.d
@@ -0,0 +1,72 @@
+#as: -mips2 -mvxworks-pic -mabi=32 -EL
+#source: vxworks1.s
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+#
+# la $4,local
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+#
+# la $4,global
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	global
+#
+# lw $4,local
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# lw $4,global
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# sw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# sw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# ulw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	88240003 	lwl	a0,3\(at\)
+.*:	98240000 	lwr	a0,0\(at\)
+#
+# ulw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	88240003 	lwl	a0,3\(at\)
+.*:	98240000 	lwr	a0,0\(at\)
+#
+# usw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	a8240003 	swl	a0,3\(at\)
+.*:	b8240000 	swr	a0,0\(at\)
+#
+# usw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	a8240003 	swl	a0,3\(at\)
+.*:	b8240000 	swr	a0,0\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/vxworks1-xgot-el.d b/gas/testsuite/gas/mips/vxworks1-xgot-el.d
new file mode 100644
index 000000000000..c48d804f10d0
--- /dev/null
+++ b/gas/testsuite/gas/mips/vxworks1-xgot-el.d
@@ -0,0 +1,102 @@
+#as: -mips2 -mvxworks-pic -xgot -mabi=32 -EL
+#source: vxworks1.s
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+#
+# la $4,local
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	\.data
+#
+# la $4,global
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	global
+#
+# lw $4,local
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# lw $4,global
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# sw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# sw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# ulw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	88240003 	lwl	a0,3\(at\)
+.*:	98240000 	lwr	a0,0\(at\)
+#
+# ulw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	88240003 	lwl	a0,3\(at\)
+.*:	98240000 	lwr	a0,0\(at\)
+#
+# usw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	a8240003 	swl	a0,3\(at\)
+.*:	b8240000 	swr	a0,0\(at\)
+#
+# usw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	a8240003 	swl	a0,3\(at\)
+.*:	b8240000 	swr	a0,0\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/vxworks1-xgot.d b/gas/testsuite/gas/mips/vxworks1-xgot.d
new file mode 100644
index 000000000000..660b34e07b55
--- /dev/null
+++ b/gas/testsuite/gas/mips/vxworks1-xgot.d
@@ -0,0 +1,102 @@
+#as: -mips2 -mvxworks-pic -xgot -mabi=32 -EB
+#source: vxworks1.s
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+#
+# la $4,local
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	\.data
+#
+# la $4,global
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	global
+#
+# lw $4,local
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# lw $4,global
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	009c2021 	addu	a0,a0,gp
+.*:	8c840000 	lw	a0,0\(a0\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# sw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# sw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# ulw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	88240000 	lwl	a0,0\(at\)
+.*:	98240003 	lwr	a0,3\(at\)
+#
+# ulw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	88240000 	lwl	a0,0\(at\)
+.*:	98240003 	lwr	a0,3\(at\)
+#
+# usw $4,local
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	\.data
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	\.data
+.*:	a8240000 	swl	a0,0\(at\)
+.*:	b8240003 	swr	a0,3\(at\)
+#
+# usw $4,global
+#
+.*:	3c010000 	lui	at,0x0
+			.*: R_MIPS_GOT_HI16	global
+.*:	003c0821 	addu	at,at,gp
+.*:	8c210000 	lw	at,0\(at\)
+			.*: R_MIPS_GOT_LO16	global
+.*:	a8240000 	swl	a0,0\(at\)
+.*:	b8240003 	swr	a0,3\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/vxworks1.d b/gas/testsuite/gas/mips/vxworks1.d
new file mode 100644
index 000000000000..86d64b43a8e7
--- /dev/null
+++ b/gas/testsuite/gas/mips/vxworks1.d
@@ -0,0 +1,71 @@
+#as: -mips2 -mvxworks-pic -mabi=32 -EB
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+#
+# la $4,local
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+#
+# la $4,global
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	global
+#
+# lw $4,local
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# lw $4,global
+#
+.*:	8f840000 	lw	a0,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	8c840000 	lw	a0,0\(a0\)
+#
+# sw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# sw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	ac240000 	sw	a0,0\(at\)
+#
+# ulw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	88240000 	lwl	a0,0\(at\)
+.*:	98240003 	lwr	a0,3\(at\)
+#
+# ulw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	88240000 	lwl	a0,0\(at\)
+.*:	98240003 	lwr	a0,3\(at\)
+#
+# usw $4,local
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	\.data
+.*:	a8240000 	swl	a0,0\(at\)
+.*:	b8240003 	swr	a0,3\(at\)
+#
+# usw $4,global
+#
+.*:	8f810000 	lw	at,0\(gp\)
+			.*: R_MIPS_GOT16	global
+.*:	a8240000 	swl	a0,0\(at\)
+.*:	b8240003 	swr	a0,3\(at\)
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/vxworks1.s b/gas/testsuite/gas/mips/vxworks1.s
new file mode 100644
index 000000000000..4d670a320cd6
--- /dev/null
+++ b/gas/testsuite/gas/mips/vxworks1.s
@@ -0,0 +1,16 @@
+	la	$4,local
+	la	$4,global
+	lw	$4,local
+	lw	$4,global
+	sw	$4,local
+	sw	$4,global
+	ulw	$4,local
+	ulw	$4,global
+	usw	$4,local
+	usw	$4,global
+	.space	16
+
+	.data
+	.global global
+local:	.word	4
+global:	.word	8
diff --git a/gas/testsuite/gas/mmix/align-1.d b/gas/testsuite/gas/mmix/align-1.d
index 94acac25761b..68658df913f0 100644
--- a/gas/testsuite/gas/mmix/align-1.d
+++ b/gas/testsuite/gas/mmix/align-1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0000000000000000 l    d  \.text	0000000000000000 
-0000000000000000 l    d  \.data	0000000000000000 
-0000000000000000 l    d  \.bss	0000000000000000 
+0000000000000000 l    d  \.text	0000000000000000 (|\.text)
+0000000000000000 l    d  \.data	0000000000000000 (|\.data)
+0000000000000000 l    d  \.bss	0000000000000000 (|\.bss)
 0000000000000002 l       \.text	0000000000000000 a
 0000000000000008 l       \.text	0000000000000000 b
 0000000000000010 l       \.text	0000000000000000 c
diff --git a/gas/testsuite/gas/mmix/basep-10.d b/gas/testsuite/gas/mmix/basep-10.d
index fcf486f7477c..07c990c29285 100644
--- a/gas/testsuite/gas/mmix/basep-10.d
+++ b/gas/testsuite/gas/mmix/basep-10.d
@@ -4,12 +4,12 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+4 l       \.text	0+ w4
 0+10 l       \.text	0+ w2
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+c  w      \.text	0+ w1
 0+8  w      \.text	0+ w3
 
diff --git a/gas/testsuite/gas/mmix/basep-11.d b/gas/testsuite/gas/mmix/basep-11.d
index 81227c0ae65d..dc03ca46492f 100644
--- a/gas/testsuite/gas/mmix/basep-11.d
+++ b/gas/testsuite/gas/mmix/basep-11.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+4 l       \.text	0+ w4
 0+10 l       \.text	0+ w2
 0+c  w      \.text	0+ w1
diff --git a/gas/testsuite/gas/mmix/basep-7.d b/gas/testsuite/gas/mmix/basep-7.d
index e00139fef7ee..0cd0a13a63c8 100644
--- a/gas/testsuite/gas/mmix/basep-7.d
+++ b/gas/testsuite/gas/mmix/basep-7.d
@@ -9,9 +9,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+2a l       \*ABS\*	0+ a
 0+70 l       \*ABS\*	0+ b
 0+48 l       \*ABS\*	0+ c
diff --git a/gas/testsuite/gas/mmix/basep-8.d b/gas/testsuite/gas/mmix/basep-8.d
index 6f075945d3df..e5a1d724588d 100644
--- a/gas/testsuite/gas/mmix/basep-8.d
+++ b/gas/testsuite/gas/mmix/basep-8.d
@@ -9,9 +9,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l     O \.bss	0+4 comm_symbol3
 0+4 l     O \.bss	0+4 comm_symbol4
 0+4       O \*COM\*	0+4 comm_symbol1
diff --git a/gas/testsuite/gas/mmix/basep-9.d b/gas/testsuite/gas/mmix/basep-9.d
index d50d8a36156f..148c899b0cdb 100644
--- a/gas/testsuite/gas/mmix/basep-9.d
+++ b/gas/testsuite/gas/mmix/basep-9.d
@@ -3,12 +3,12 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l     O \.bss	0+4 comm_symbol3
 0+4 l     O \.bss	0+4 comm_symbol4
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+4       O \*COM\*	0+4 comm_symbol1
 
 RELOCATION RECORDS FOR \[\.text\]:
diff --git a/gas/testsuite/gas/mmix/builtin1.d b/gas/testsuite/gas/mmix/builtin1.d
index 1733cf42c0be..17d13bbfa685 100644
--- a/gas/testsuite/gas/mmix/builtin1.d
+++ b/gas/testsuite/gas/mmix/builtin1.d
@@ -7,9 +7,9 @@
 
 SYMBOL TABLE:
 0+14 l       \*ABS\*	0+ rJ
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/builtin2.d b/gas/testsuite/gas/mmix/builtin2.d
index f0e1c6a14378..7656cb6909c3 100644
--- a/gas/testsuite/gas/mmix/builtin2.d
+++ b/gas/testsuite/gas/mmix/builtin2.d
@@ -8,9 +8,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+14 l       \*ABS\*	0+ rJ
 0+ g     F \.text	0+ Main
 
diff --git a/gas/testsuite/gas/mmix/builtin3.d b/gas/testsuite/gas/mmix/builtin3.d
index 4c03230a7b90..74801a6d5481 100644
--- a/gas/testsuite/gas/mmix/builtin3.d
+++ b/gas/testsuite/gas/mmix/builtin3.d
@@ -9,9 +9,9 @@
 
 SYMBOL TABLE:
 0+14 l       \*ABS\*	0+ rJ
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/bz-c.d b/gas/testsuite/gas/mmix/bz-c.d
index 604325842734..24113b633d3a 100644
--- a/gas/testsuite/gas/mmix/bz-c.d
+++ b/gas/testsuite/gas/mmix/bz-c.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 ffff0000ffff0000 l       \*ABS\*	0+ i1
 ffff0000ffff0000 l       \*ABS\*	0+ i2
 0+ g     F .text	0+ Main
diff --git a/gas/testsuite/gas/mmix/comment-2.d b/gas/testsuite/gas/mmix/comment-2.d
index 553055248157..b58a0009cb28 100644
--- a/gas/testsuite/gas/mmix/comment-2.d
+++ b/gas/testsuite/gas/mmix/comment-2.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/comment-3.d b/gas/testsuite/gas/mmix/comment-3.d
index 2614051815d2..19922b84918b 100644
--- a/gas/testsuite/gas/mmix/comment-3.d
+++ b/gas/testsuite/gas/mmix/comment-3.d
@@ -3,11 +3,11 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0000000000000000 l    d  \.text	0000000000000000 
-0000000000000000 l    d  \.data	0000000000000000 
-0000000000000000 l    d  \.bss	0000000000000000 
+0000000000000000 l    d  \.text	0000000000000000 (|\.text)
+0000000000000000 l    d  \.data	0000000000000000 (|\.data)
+0000000000000000 l    d  \.bss	0000000000000000 (|\.bss)
 0000000000000000 l       \.MMIX\.reg_contents	0000000000000000 im
-0000000000000000 l    d  \.MMIX\.reg_contents	0000000000000000 
+0000000000000000 l    d  \.MMIX\.reg_contents	0000000000000000 (|\.MMIX\.reg_contents)
 
 
 RELOCATION RECORDS FOR \[\.MMIX\.reg_contents\]:
diff --git a/gas/testsuite/gas/mmix/cons-2.d b/gas/testsuite/gas/mmix/cons-2.d
index 6e354a557bd1..251d58e5523a 100644
--- a/gas/testsuite/gas/mmix/cons-2.d
+++ b/gas/testsuite/gas/mmix/cons-2.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 Contents of section \.text:
diff --git a/gas/testsuite/gas/mmix/err-byte1.s b/gas/testsuite/gas/mmix/err-byte1.s
index 28ad78e1d591..eefded3e431e 100644
--- a/gas/testsuite/gas/mmix/err-byte1.s
+++ b/gas/testsuite/gas/mmix/err-byte1.s
@@ -1,5 +1,5 @@
 % { dg-do assemble { target mmix-*-* } }
-% { dg-error "unterminated string" "" { target mmix-*-* } 10 }
+% { dg-error "unterminated string|missing closing" "" { target mmix-*-* } 10 }
 % { dg-bogus "end of file" "" { xfail mmix-*-* } 0 }
 
 # Note that the error is detected in the preformatter, before the text
diff --git a/gas/testsuite/gas/mmix/fb-1.d b/gas/testsuite/gas/mmix/fb-1.d
index 3610c71c84be..c7f1d12c0d4c 100644
--- a/gas/testsuite/gas/mmix/fb-1.d
+++ b/gas/testsuite/gas/mmix/fb-1.d
@@ -3,10 +3,10 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 
 
 RELOCATION RECORDS FOR \[\.text\]:
diff --git a/gas/testsuite/gas/mmix/fb-2.d b/gas/testsuite/gas/mmix/fb-2.d
index 5e412d51915d..74eb71fd1397 100644
--- a/gas/testsuite/gas/mmix/fb-2.d
+++ b/gas/testsuite/gas/mmix/fb-2.d
@@ -3,10 +3,10 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+10 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
 
 
diff --git a/gas/testsuite/gas/mmix/geta-c.d b/gas/testsuite/gas/mmix/geta-c.d
index 851018cb5bca..5e7bf2bbb860 100644
--- a/gas/testsuite/gas/mmix/geta-c.d
+++ b/gas/testsuite/gas/mmix/geta-c.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 ffff0000ffff0000 l       \*ABS\*	0+ i1
 ffff0000ffff0000 l       \*ABS\*	0+ i2
 0+ g     F .text	0+ Main
diff --git a/gas/testsuite/gas/mmix/greg1.d b/gas/testsuite/gas/mmix/greg1.d
index 5c45364e7a2c..fe3b5487533f 100644
--- a/gas/testsuite/gas/mmix/greg1.d
+++ b/gas/testsuite/gas/mmix/greg1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ D4
 0+4 l       \.text	0+ E6
 0+ l       \.MMIX\.reg_contents	0+ H9
@@ -15,7 +15,7 @@ SYMBOL TABLE:
 0+20 l       \.MMIX\.reg_contents	0+ C3
 0+28 l       \.MMIX\.reg_contents	0+ B1
 0+30 l       \.MMIX\.reg_contents	0+ A0
-0+0 l    d  \.MMIX\.reg_contents	0+ 
+0+0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+c g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/greg1a.d b/gas/testsuite/gas/mmix/greg1a.d
index 932f4e421a94..86ab57260557 100644
--- a/gas/testsuite/gas/mmix/greg1a.d
+++ b/gas/testsuite/gas/mmix/greg1a.d
@@ -5,9 +5,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ D4
 0+4 l       \.text	0+ E6
 0+ l       \.MMIX\.reg_contents	0+ H9
@@ -17,7 +17,7 @@ SYMBOL TABLE:
 0+30 l       \.MMIX\.reg_contents	0+ C3
 0+38 l       \.MMIX\.reg_contents	0+ B1
 0+40 l       \.MMIX\.reg_contents	0+ A0
-0+0 l    d  \.MMIX\.reg_contents	0+ 
+0+0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+c g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/greg2.d b/gas/testsuite/gas/mmix/greg2.d
index 5c45364e7a2c..fe3b5487533f 100644
--- a/gas/testsuite/gas/mmix/greg2.d
+++ b/gas/testsuite/gas/mmix/greg2.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ D4
 0+4 l       \.text	0+ E6
 0+ l       \.MMIX\.reg_contents	0+ H9
@@ -15,7 +15,7 @@ SYMBOL TABLE:
 0+20 l       \.MMIX\.reg_contents	0+ C3
 0+28 l       \.MMIX\.reg_contents	0+ B1
 0+30 l       \.MMIX\.reg_contents	0+ A0
-0+0 l    d  \.MMIX\.reg_contents	0+ 
+0+0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+c g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/greg2a.d b/gas/testsuite/gas/mmix/greg2a.d
index 1fbd88d4194f..ea8cb1e0f264 100644
--- a/gas/testsuite/gas/mmix/greg2a.d
+++ b/gas/testsuite/gas/mmix/greg2a.d
@@ -5,9 +5,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ D4
 0+4 l       \.text	0+ E6
 0+ l       \.MMIX\.reg_contents	0+ H9
@@ -17,7 +17,7 @@ SYMBOL TABLE:
 0+30 l       \.MMIX\.reg_contents	0+ C3
 0+38 l       \.MMIX\.reg_contents	0+ B1
 0+40 l       \.MMIX\.reg_contents	0+ A0
-0+0 l    d  \.MMIX\.reg_contents	0+ 
+0+0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+c g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/greg3.d b/gas/testsuite/gas/mmix/greg3.d
index 9b7661439005..fcaa4393c292 100644
--- a/gas/testsuite/gas/mmix/greg3.d
+++ b/gas/testsuite/gas/mmix/greg3.d
@@ -5,10 +5,10 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+ g       \.MMIX\.reg_contents	0+ areg
 0+c g     F \.text	0+ Main
 
diff --git a/gas/testsuite/gas/mmix/greg4.d b/gas/testsuite/gas/mmix/greg4.d
index 224794ec3881..fb5560523ee8 100644
--- a/gas/testsuite/gas/mmix/greg4.d
+++ b/gas/testsuite/gas/mmix/greg4.d
@@ -5,11 +5,11 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+4 l       \.text	0+ x
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 
 
 RELOCATION RECORDS FOR \[\.text\]:
diff --git a/gas/testsuite/gas/mmix/greg5.d b/gas/testsuite/gas/mmix/greg5.d
index 71b007eb4676..5d4bbba126e8 100644
--- a/gas/testsuite/gas/mmix/greg5.d
+++ b/gas/testsuite/gas/mmix/greg5.d
@@ -6,14 +6,14 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ t
 2000000000000004 l       \*ABS\*	0+ x
 2000000000000000 l       \*ABS\*	0+ Data_Segment
 0+ l       \.data	0+ y
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+ g     F \.text	0+ Main
 2000000000000008 g       \*ABS\*	0+ __\.MMIX\.start\.\.data
 
diff --git a/gas/testsuite/gas/mmix/greg6.d b/gas/testsuite/gas/mmix/greg6.d
index 40ec5ce7a9a8..e66e38f1e880 100644
--- a/gas/testsuite/gas/mmix/greg6.d
+++ b/gas/testsuite/gas/mmix/greg6.d
@@ -6,14 +6,14 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ t
 2000000000000004 l       \*ABS\*	0+ x
 2000000000000000 l       \*ABS\*	0+ Data_Segment
 0+ l       \.data	0+ y
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+ g     F \.text	0+ Main
 2000000000000008 g       \*ABS\*	0+ __\.MMIX\.start\.\.data
 
diff --git a/gas/testsuite/gas/mmix/greg7.d b/gas/testsuite/gas/mmix/greg7.d
index b6021e25f7f4..f4cae1886e0e 100644
--- a/gas/testsuite/gas/mmix/greg7.d
+++ b/gas/testsuite/gas/mmix/greg7.d
@@ -6,13 +6,13 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ t
 0+4 l       \*ABS\*	0+ x
 0+ l       \.text	0+ y
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+8 g     F \.text	0+ Main
 0+8 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
 
diff --git a/gas/testsuite/gas/mmix/greg8.d b/gas/testsuite/gas/mmix/greg8.d
index a8314b4b0052..c244919dc62d 100644
--- a/gas/testsuite/gas/mmix/greg8.d
+++ b/gas/testsuite/gas/mmix/greg8.d
@@ -6,13 +6,13 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ t
 0+4 l       \*ABS\*	0+ x
 0+ l       \.text	0+ y
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+8 g     F \.text	0+ Main
 0+8 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
 
diff --git a/gas/testsuite/gas/mmix/hex2.d b/gas/testsuite/gas/mmix/hex2.d
new file mode 100644
index 000000000000..345e853d2b42
--- /dev/null
+++ b/gas/testsuite/gas/mmix/hex2.d
@@ -0,0 +1,17 @@
+# objdump: -dr
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <x>:
+[ 	]+0:[ 	]+fd000000[ 	]+swym 0,0,0
+[ 	]+4:[ 	]+e309001f[ 	]+setl \$9,0x1f
+[ 	]+8:[ 	]+e3081b2f[ 	]+setl \$8,0x1b2f
+[ 	]+c:[ 	]+e307ff9f[ 	]+setl \$7,0xff9f
+[ 	]+10:[ 	]+e3061f3a[ 	]+setl \$6,0x1f3a
+[ 	]+14:[ 	]+e305001b[ 	]+setl \$5,0x1b
+[ 	]+18:[ 	]+e3041a1b[ 	]+setl \$4,0x1a1b
+[ 	]+1c:[ 	]+e303009f[ 	]+setl \$3,0x9f
+[ 	]+20:[ 	]+e302009b[ 	]+setl \$2,0x9b
+[ 	]+24:[ 	]+e301001f[ 	]+setl \$1,0x1f
+[ 	]+28:[ 	]+e300001b[ 	]+setl \$0,0x1b
diff --git a/gas/testsuite/gas/mmix/hex2.s b/gas/testsuite/gas/mmix/hex2.s
new file mode 100644
index 000000000000..ccdf0127b205
--- /dev/null
+++ b/gas/testsuite/gas/mmix/hex2.s
@@ -0,0 +1,15 @@
+x:
+ swym
+0:
+ setl $9,#1F
+1:
+ setl $8,#1B2F
+ setl $7,0xFF9F
+ setl $6,#1F3A
+9:
+ setl $5,#1B
+ setl $4,#1A1B
+ setl $3,0x9F
+ setl $2,0x9B
+ setl $1,0x1F
+ setl $0,0x1b
diff --git a/gas/testsuite/gas/mmix/is-1.d b/gas/testsuite/gas/mmix/is-1.d
index c96fa504eae8..3890b5b07861 100644
--- a/gas/testsuite/gas/mmix/is-1.d
+++ b/gas/testsuite/gas/mmix/is-1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 
 Contents of section \.text:
  0+ 00000026 0000001f 0000000d 0000001e  .*
diff --git a/gas/testsuite/gas/mmix/jump-c.d b/gas/testsuite/gas/mmix/jump-c.d
index a256687879af..d0c24374fd5f 100644
--- a/gas/testsuite/gas/mmix/jump-c.d
+++ b/gas/testsuite/gas/mmix/jump-c.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 ffff0000ffff0000 l       \*ABS\*	0+ i1
 ffff0000ffff0000 l       \*ABS\*	0+ i2
 0+ g     F .text	0+ Main
diff --git a/gas/testsuite/gas/mmix/local-1.d b/gas/testsuite/gas/mmix/local-1.d
index 2656cfd462dc..ecca83775fed 100644
--- a/gas/testsuite/gas/mmix/local-1.d
+++ b/gas/testsuite/gas/mmix/local-1.d
@@ -15,9 +15,9 @@ Idx Name          Size      VMA               LMA               File off  Algn
   2 \.bss          00000000  0000000000000000  0000000000000000  00000044  2\*\*0
                   ALLOC
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+90 l       \*REG\*	0+ reghere
 0+2d l       \*ABS\*	0+ consthere
 0+         \*UND\*	0+ extreg
diff --git a/gas/testsuite/gas/mmix/locall1.d b/gas/testsuite/gas/mmix/locall1.d
index 0921e63820b9..ead3a1a9f63a 100644
--- a/gas/testsuite/gas/mmix/locall1.d
+++ b/gas/testsuite/gas/mmix/locall1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+14 l       \.text	0+ L9
 0+18 l       \.text	0+ L12
 0+1c l       \.text	0+ L21
diff --git a/gas/testsuite/gas/mmix/mmix-err.exp b/gas/testsuite/gas/mmix/mmix-err.exp
index b9c837176e81..28e58dcbc6a1 100644
--- a/gas/testsuite/gas/mmix/mmix-err.exp
+++ b/gas/testsuite/gas/mmix/mmix-err.exp
@@ -12,7 +12,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 if { ! [istarget "mmix-*"] } {
     return
diff --git a/gas/testsuite/gas/mmix/mmix-list.exp b/gas/testsuite/gas/mmix/mmix-list.exp
index 6f62ceb9ac0a..8d2a294f7c5b 100644
--- a/gas/testsuite/gas/mmix/mmix-list.exp
+++ b/gas/testsuite/gas/mmix/mmix-list.exp
@@ -12,7 +12,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 if { ! [istarget "mmix-*"] } {
     return
diff --git a/gas/testsuite/gas/mmix/mmix.exp b/gas/testsuite/gas/mmix/mmix.exp
index 139b895f2d3c..239339376114 100644
--- a/gas/testsuite/gas/mmix/mmix.exp
+++ b/gas/testsuite/gas/mmix/mmix.exp
@@ -12,7 +12,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 if { ! [istarget "mmix-*"] } {
     return
diff --git a/gas/testsuite/gas/mmix/odd-1.d b/gas/testsuite/gas/mmix/odd-1.d
index 8cec21146762..51bc4e5693a7 100644
--- a/gas/testsuite/gas/mmix/odd-1.d
+++ b/gas/testsuite/gas/mmix/odd-1.d
@@ -5,11 +5,11 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.MMIX\.reg_contents	0+ small
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/op-0-1.d b/gas/testsuite/gas/mmix/op-0-1.d
index f76f0eace6ac..0344af330ac4 100644
--- a/gas/testsuite/gas/mmix/op-0-1.d
+++ b/gas/testsuite/gas/mmix/op-0-1.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \*ABS\*	0+ zero0
 0+ l       \*ABS\*	0+ zero1
 0+ l       \*ABS\*	0+ zero2
diff --git a/gas/testsuite/gas/mmix/op-0-1s.d b/gas/testsuite/gas/mmix/op-0-1s.d
index 1af0b8165281..d64ced85bb03 100644
--- a/gas/testsuite/gas/mmix/op-0-1s.d
+++ b/gas/testsuite/gas/mmix/op-0-1s.d
@@ -4,9 +4,9 @@
 
 .*:     file format elf64-mmix
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \*ABS\*	0+ zero0
 0+ l       \*ABS\*	0+ zero1
 0+ l       \*ABS\*	0+ zero2
diff --git a/gas/testsuite/gas/mmix/op-0-2.d b/gas/testsuite/gas/mmix/op-0-2.d
index 530e8d43b4a7..c0fb4de2f49c 100644
--- a/gas/testsuite/gas/mmix/op-0-2.d
+++ b/gas/testsuite/gas/mmix/op-0-2.d
@@ -5,9 +5,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \*ABS\*	0+ zero0
 0+ l       \*ABS\*	0+ zero1
 0+ l       \*ABS\*	0+ zero2
diff --git a/gas/testsuite/gas/mmix/prefix1.d b/gas/testsuite/gas/mmix/prefix1.d
index e82d60f08fe4..b77419355906 100644
--- a/gas/testsuite/gas/mmix/prefix1.d
+++ b/gas/testsuite/gas/mmix/prefix1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ a
 0+4 l       \.text	0+ c
 0+24 l       \.text	0+ d
diff --git a/gas/testsuite/gas/mmix/prefix2.d b/gas/testsuite/gas/mmix/prefix2.d
index 818761bc7e10..a14ffcd3736c 100644
--- a/gas/testsuite/gas/mmix/prefix2.d
+++ b/gas/testsuite/gas/mmix/prefix2.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/prefix3.d b/gas/testsuite/gas/mmix/prefix3.d
index 1b1a1ef7f1da..2ecbcc19f18b 100644
--- a/gas/testsuite/gas/mmix/prefix3.d
+++ b/gas/testsuite/gas/mmix/prefix3.d
@@ -3,14 +3,14 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+8 l       \.text	0+ someplace
 0+ l       \.text	0+ bc:h
 0+8 l       \.MMIX\.reg_contents	0+ a1
 0+ l       \.MMIX\.reg_contents	0+ ba2
-0+ l    d  \.MMIX\.reg_contents	0+ 
+0+ l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
 0+4 g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mmix/pseudo-1.d b/gas/testsuite/gas/mmix/pseudo-1.d
index e7ac99ab3269..2de00e70aa6a 100644
--- a/gas/testsuite/gas/mmix/pseudo-1.d
+++ b/gas/testsuite/gas/mmix/pseudo-1.d
@@ -5,9 +5,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 Contents of section \.text:
diff --git a/gas/testsuite/gas/mmix/pushj-c.d b/gas/testsuite/gas/mmix/pushj-c.d
index 093466b8b292..af3281de2c59 100644
--- a/gas/testsuite/gas/mmix/pushj-c.d
+++ b/gas/testsuite/gas/mmix/pushj-c.d
@@ -4,9 +4,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 ffff0000ffff0000 l       \*ABS\*	0+ i1
 ffff0000ffff0000 l       \*ABS\*	0+ i2
 0+ g     F .text	0+ Main
diff --git a/gas/testsuite/gas/mmix/pushj-cs.d b/gas/testsuite/gas/mmix/pushj-cs.d
index 7112c5d14e3f..b2ac35abc000 100644
--- a/gas/testsuite/gas/mmix/pushj-cs.d
+++ b/gas/testsuite/gas/mmix/pushj-cs.d
@@ -4,9 +4,9 @@
 
 .*:     file format elf64-mmix
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 ffff0000ffff0000 l       \*ABS\*	0+ i1
 ffff0000ffff0000 l       \*ABS\*	0+ i2
 0+ g     F .text	0+ Main
diff --git a/gas/testsuite/gas/mmix/relax1-n.d b/gas/testsuite/gas/mmix/relax1-n.d
index 4df6a566ca1e..2de7d74dbf2c 100644
--- a/gas/testsuite/gas/mmix/relax1-n.d
+++ b/gas/testsuite/gas/mmix/relax1-n.d
@@ -2,8 +2,8 @@
 #as: -no-expand -x
 #source: relax1.s
 #
-# FIXME: This test-case assumes that out-of-range errors cause relocs to
-# be emitted, rather than errors emitted.
+# This test-case assumes that out-of-range errors cause relocs to
+# be emitted, rather than errors emitted.  FIXME.
 
 .*:     file format elf64-mmix
 
diff --git a/gas/testsuite/gas/mmix/relax1-rn.d b/gas/testsuite/gas/mmix/relax1-rn.d
index 20d0b1ffa5a0..3d16c84728fb 100644
--- a/gas/testsuite/gas/mmix/relax1-rn.d
+++ b/gas/testsuite/gas/mmix/relax1-rn.d
@@ -2,8 +2,8 @@
 #as: -linkrelax -no-expand -x
 #source: relax1.s
 #
-# FIXME: This test-case assumes that out-of-range errors (still) cause
-# relocs to be emitted, rather than errors emitted.
+# This test-case assumes that out-of-range errors (still) cause
+# relocs to be emitted, rather than errors emitted.  FIXME.
 
 .*:     file format elf64-mmix
 
diff --git a/gas/testsuite/gas/mmix/relax2.s b/gas/testsuite/gas/mmix/relax2.s
index 8db8f1a05819..537cef01026b 100644
--- a/gas/testsuite/gas/mmix/relax2.s
+++ b/gas/testsuite/gas/mmix/relax2.s
@@ -1,33 +1,39 @@
 # PUSHJ stub border-cases: two with either or both stubs unreachable,
 # local symbols, ditto non-local labels, similar with three PUSHJs.
+# Note the absence of ":" on labels: because it's a symbol-character,
+# it's concatenated with the parameter macro name and parsed as "\x:".
+# This happens before gas deals with ":" as it usually does; not being
+# part of the name when ending a label at the beginning of a line.
+# (Since we're LABELS_WITHOUT_COLONS it inserts one for us, but
+# that would be disabled with --gnu-syntax.)
 
 Main	SWYM
 
 	.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12
 
 	.section .text.a\x,"ax"
-aa\x:	.space 4,0
-a\x:	.space 65536*4,0
+aa\x	.space 4,0
+a\x	.space 65536*4,0
 	PUSHJ $33,aa\x
 	PUSHJ $22,a\x
 	.space 65535*4-4*\x
 
 	.section .text.b\x,"ax"
-bbb\x:	.space 4,0
-bb\x:	.space 4,0
-b\x:	.space 65535*4
+bbb\x	.space 4,0
+bb\x	.space 4,0
+b\x	.space 65535*4
 	PUSHJ $12,bbb\x
 	PUSHJ $13,bb\x
 	PUSHJ $14,b\x
 	.space 65535*4-4*\x
 
 	.section .text.c\x,"ax"
-c\x:	PUSHJ $100,ca\x
+c\x	PUSHJ $100,ca\x
 	PUSHJ $101,cb\x
 	.space 65535*4-4*\x
 
 	.section .text.d\x,"ax"
-d\x:	PUSHJ $99,da\x
+d\x	PUSHJ $99,da\x
 	PUSHJ $98,db\x
 	PUSHJ $97,dc\x
 	.space 65535*4-4*\x
diff --git a/gas/testsuite/gas/mmix/sym-1.d b/gas/testsuite/gas/mmix/sym-1.d
index cd64ce4dd100..82e23d55b744 100644
--- a/gas/testsuite/gas/mmix/sym-1.d
+++ b/gas/testsuite/gas/mmix/sym-1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  .text	0+ 
-0+ l    d  .data	0+ 
-0+ l    d  .bss	0+ 
+0+ l    d  .text	0+ (|\.text)
+0+ l    d  .data	0+ (|\.data)
+0+ l    d  .bss	0+ (|\.bss)
 0+10 l       .text	0+ scl1
 0+14 l       .text	0+ :scl2
 0+20 l       .text	0+ endcl1
diff --git a/gas/testsuite/gas/mmix/weak1-s.d b/gas/testsuite/gas/mmix/weak1-s.d
index a92938334611..36d9a779ef08 100644
--- a/gas/testsuite/gas/mmix/weak1-s.d
+++ b/gas/testsuite/gas/mmix/weak1-s.d
@@ -6,9 +6,9 @@
 
 .*:     file format elf64-mmix
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+  w      \.text	0+ foo
 0+4 g       \.text	0+ main
 RELOCATION RECORDS FOR \[\.text\]:
diff --git a/gas/testsuite/gas/mmix/weak1.d b/gas/testsuite/gas/mmix/weak1.d
index dfe6d7c82fda..4cbea47e0d78 100644
--- a/gas/testsuite/gas/mmix/weak1.d
+++ b/gas/testsuite/gas/mmix/weak1.d
@@ -6,9 +6,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+  w      \.text	0+ foo
 0+4 g       \.text	0+ main
 
diff --git a/gas/testsuite/gas/mmix/zerop-1.d b/gas/testsuite/gas/mmix/zerop-1.d
index d39133a25b50..b6e6465e1d21 100644
--- a/gas/testsuite/gas/mmix/zerop-1.d
+++ b/gas/testsuite/gas/mmix/zerop-1.d
@@ -3,9 +3,9 @@
 .*:     file format elf64-mmix
 
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ g     F \.text	0+ Main
 
 
diff --git a/gas/testsuite/gas/mn10200/basic.exp b/gas/testsuite/gas/mn10200/basic.exp
index 041b6a2052ab..4531ac677568 100644
--- a/gas/testsuite/gas/mn10200/basic.exp
+++ b/gas/testsuite/gas/mn10200/basic.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1996 Free Software Foundation, Inc.
+# Copyright (C) 1996, 2002 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
diff --git a/gas/testsuite/gas/mn10300/am33-2.c b/gas/testsuite/gas/mn10300/am33-2.c
index 2e0001510cbe..5ec0c8eb89a3 100644
--- a/gas/testsuite/gas/mn10300/am33-2.c
+++ b/gas/testsuite/gas/mn10300/am33-2.c
@@ -13,7 +13,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
 /* Generator of tests for insns introduced in AM33 2.0.  */
diff --git a/gas/testsuite/gas/mn10300/basic.exp b/gas/testsuite/gas/mn10300/basic.exp
index 46c23d480f96..b80e006cd215 100644
--- a/gas/testsuite/gas/mn10300/basic.exp
+++ b/gas/testsuite/gas/mn10300/basic.exp
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -1817,4 +1817,5 @@ if [istarget mn10300*-*-*] then {
     run_list_test "movpc" ""
 
     run_dump_test "am33-2"
+    run_dump_test "relax"
 }
diff --git a/gas/testsuite/gas/mn10300/relax.d b/gas/testsuite/gas/mn10300/relax.d
new file mode 100644
index 000000000000..60faa6cc460e
--- /dev/null
+++ b/gas/testsuite/gas/mn10300/relax.d
@@ -0,0 +1,36 @@
+#objdump: -r 
+#name: Relaxation of conditional branches
+
+.*: +file format.*elf32-[am33lin|mn10300].*
+
+RELOCATION RECORDS FOR \[.rlcb\]:
+OFFSET   TYPE              VALUE 
+0+8003 R_MN10300_PCREL8  .L0._0\+0x00000001
+0+8005 R_MN10300_PCREL32  .L1\+0x00000001
+
+RELOCATION RECORDS FOR \[.rlfcb\]:
+OFFSET   TYPE              VALUE 
+0+8004 R_MN10300_PCREL8  .L0._1\+0x00000002
+0+8006 R_MN10300_PCREL32  .L2\+0x00000001
+
+RELOCATION RECORDS FOR \[.rscb\]:
+OFFSET   TYPE              VALUE 
+0+103 R_MN10300_PCREL8  .L0._2\+0x00000001
+0+105 R_MN10300_PCREL16  .L3\+0x00000001
+
+RELOCATION RECORDS FOR \[.rsfcb\]:
+OFFSET   TYPE              VALUE 
+0+104 R_MN10300_PCREL8  .L0._3\+0x00000002
+0+106 R_MN10300_PCREL16  .L4\+0x00000001
+
+RELOCATION RECORDS FOR \[.rsucb\]:
+OFFSET   TYPE              VALUE 
+0+104 R_MN10300_PCREL8  .L0._4\+0x00000002
+0+106 R_MN10300_PCREL16  .L5\+0x00000001
+
+RELOCATION RECORDS FOR \[.rlucb\]:
+OFFSET   TYPE              VALUE 
+0+8004 R_MN10300_PCREL8  .L0._5\+0x00000002
+0+8006 R_MN10300_PCREL32  .L6\+0x00000001
+
+
diff --git a/gas/testsuite/gas/mn10300/relax.s b/gas/testsuite/gas/mn10300/relax.s
new file mode 100644
index 000000000000..c847e97b925c
--- /dev/null
+++ b/gas/testsuite/gas/mn10300/relax.s
@@ -0,0 +1,93 @@
+	.am33_2
+	
+	.section .rlcb, "ax"
+	.global relax_long_cond_branch
+relax_long_cond_branch:
+	clr d0
+	clr d1
+.L1:	
+	add d1,d0
+	inc d1
+
+	.fill 32764, 1, 0xcb
+
+	cmp 9,d1
+	ble .L1
+	rets
+	
+
+	.section .rlfcb, "ax"
+	.global relax_long_float_cond_branch
+relax_long_float_cond_branch:
+	clr d0
+	clr d1
+.L2:
+	add d1,d0
+	inc d1
+
+	.fill 32764, 1, 0xcb
+
+	cmp 9,d1
+	fble .L2
+	rets
+
+	.section .rscb, "ax"
+	.global relax_short_cond_branch
+relax_short_cond_branch:
+	clr d0
+	clr d1
+.L3:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
+	ble .L3
+	rets
+
+	.section .rsfcb, "ax"
+	.global relax_short_float_cond_branch
+relax_short_float_cond_branch:
+	clr d0
+	clr d1
+.L4:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
+	fble .L4
+	rets
+	
+	.section .rsucb, "ax"
+	.global relax_short_uncommon_cond_branch
+relax_short_uncommon_cond_branch:
+	clr d0
+	clr d1
+.L5:
+	add d1,d0
+	inc d1
+
+	.fill 252, 1, 0xcb
+
+	cmp 9,d1
+	bvc .L5
+	rets
+
+	.section .rlucb, "ax"
+	.global relax_long_uncommon_cond_branch
+relax_long_uncommon_cond_branch:
+	clr d0
+	clr d1
+.L6:
+	add d1,d0
+	inc d1
+
+	.fill 32764, 1, 0xcb
+
+	cmp 9,d1
+	bvc .L6
+	rets
+
diff --git a/gas/testsuite/gas/mt/allinsn.d b/gas/testsuite/gas/mt/allinsn.d
new file mode 100644
index 000000000000..03db93d13959
--- /dev/null
+++ b/gas/testsuite/gas/mt/allinsn.d
@@ -0,0 +1,130 @@
+#as: -nosched
+#objdump: -dr
+#name: allinsn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <add>:
+   0:	00 00 00 00 	add R0,R0,R0
+
+00000004 <addu>:
+   4:	02 00 00 00 	addu R0,R0,R0
+
+00000008 <addi>:
+   8:	01 00 00 00 	addi R0,R0,#\$0
+
+0000000c <addui>:
+   c:	03 00 00 00 	addui R0,R0,#\$0
+
+00000010 <sub>:
+  10:	04 00 00 00 	sub R0,R0,R0
+
+00000014 <subu>:
+  14:	06 00 00 00 	subu R0,R0,R0
+
+00000018 <subi>:
+  18:	05 00 00 00 	subi R0,R0,#\$0
+
+0000001c <subui>:
+  1c:	07 00 00 00 	subui R0,R0,#\$0
+
+00000020 <and>:
+  20:	10 00 00 00 	and R0,R0,R0
+
+00000024 <andi>:
+  24:	11 00 00 00 	andi R0,R0,#\$0
+
+00000028 <or>:
+  28:	12 01 00 00 	or R0,R0,R1
+
+0000002c <ori>:
+  2c:	13 00 00 00 	ori R0,R0,#\$0
+
+00000030 <xor>:
+  30:	14 00 00 00 	xor R0,R0,R0
+
+00000034 <xori>:
+  34:	15 00 00 00 	xori R0,R0,#\$0
+
+00000038 <nand>:
+  38:	16 00 00 00 	nand R0,R0,R0
+
+0000003c <nandi>:
+  3c:	17 00 00 00 	nandi R0,R0,#\$0
+
+00000040 <nor>:
+  40:	18 00 00 00 	nor R0,R0,R0
+
+00000044 <nori>:
+  44:	19 00 00 00 	nori R0,R0,#\$0
+
+00000048 <xnor>:
+  48:	1a 00 00 00 	xnor R0,R0,R0
+
+0000004c <xnori>:
+  4c:	1b 00 00 00 	xnori R0,R0,#\$0
+
+00000050 <ldui>:
+  50:	1d 00 00 00 	ldui R0,#\$0
+
+00000054 <lsl>:
+  54:	20 00 00 00 	lsl R0,R0,R0
+
+00000058 <lsli>:
+  58:	21 00 00 00 	lsli R0,R0,#\$0
+
+0000005c <lsr>:
+  5c:	22 00 00 00 	lsr R0,R0,R0
+
+00000060 <lsri>:
+  60:	23 00 00 00 	lsri R0,R0,#\$0
+
+00000064 <asr>:
+  64:	24 00 00 00 	asr R0,R0,R0
+
+00000068 <asri>:
+  68:	25 00 00 00 	asri R0,R0,#\$0
+
+0000006c <brlt>:
+  6c:	31 00 00 00 	brlt R0,R0,6c <brlt>
+
+00000070 <brle>:
+  70:	33 00 00 00 	brle R0,R0,70 <brle>
+
+00000074 <breq>:
+  74:	35 00 00 00 	breq R0,R0,74 <breq>
+
+00000078 <jmp>:
+  78:	37 00 00 00 	jmp 78 <jmp>
+
+0000007c <jal>:
+  7c:	38 00 00 00 	jal R0,R0
+
+00000080 <ei>:
+  80:	60 00 00 00 	ei
+
+00000084 <di>:
+  84:	62 00 00 00 	di
+
+00000088 <reti>:
+  88:	66 00 00 00 	reti R0
+
+0000008c <ldw>:
+  8c:	41 00 00 00 	ldw R0,R0,#\$0
+
+00000090 <stw>:
+  90:	43 00 00 00 	stw R0,R0,#\$0
+
+00000094 <si>:
+  94:	64 00 00 00 	si R0
+
+00000098 <brne>:
+  98:	3b 00 00 00 	brne R0,R0,98 <brne>
+
+0000009c <break>:
+  9c:	68 00 00 00 	break
+
+000000a0 <nop>:
+  a0:	12 00 00 00 	nop
diff --git a/gas/testsuite/gas/mt/allinsn.s b/gas/testsuite/gas/mt/allinsn.s
new file mode 100644
index 000000000000..8d9050e60143
--- /dev/null
+++ b/gas/testsuite/gas/mt/allinsn.s
@@ -0,0 +1,166 @@
+ .data
+foodata: .word 42
+ .text
+footext:
+	.text
+	.global add
+add:
+	add  R0,R0,R0
+	.text
+	.global addu
+addu:
+	addu R0,R0,R0
+	.text
+	.global addi
+addi:
+	addi R0,R0,#0
+	.text
+	.global addui
+addui:
+	addui R0,R0,#0
+	.text
+	.global sub
+sub:
+	sub R0,R0,R0
+	.text
+	.global subu
+subu:
+	subu R0,R0,R0
+	.text
+	.global subi
+subi:
+	subi R0,R0,#0
+	.text
+	.global subui
+subui:
+	subui R0,R0,#0
+	.text
+	.global and
+and:
+	and R0,R0,R0
+	.text
+	.global andi
+andi:
+	andi R0,R0,#0
+	.text
+	.global or
+or:
+	or R0,R0,R1
+	.text
+	.global ori
+ori:
+	ori R0,R0,#0
+	.text
+	.global xor
+xor:
+	xor R0,R0,R0
+	.text
+	.global xori
+xori:
+	xori R0,R0,#0
+	.text
+	.global nand
+nand:
+	nand R0,R0,R0
+	.text
+	.global nandi
+nandi:
+	nandi R0,R0,#0
+	.text
+	.global nor
+nor:
+	nor R0,R0,R0
+	.text
+	.global nori
+nori:
+	nori R0,R0,#0
+	.text
+	.global xnor
+xnor:
+	xnor R0,R0,R0
+	.text
+	.global xnori
+xnori:
+	xnori R0,R0,#0
+	.text
+	.global ldui
+ldui:
+	ldui R0,#0
+	.text
+	.global lsl
+lsl:
+	lsl R0,R0,R0
+	.text
+	.global lsli
+lsli:
+	lsli R0,R0,#0
+	.text
+	.global lsr
+lsr:
+	lsr R0,R0,R0
+	.text
+	.global lsri
+lsri:
+	lsri R0,R0,#0
+	.text
+	.global asr
+asr:
+	asr R0,R0,R0
+	.text
+	.global asri
+asri:
+	asri R0,R0,#0
+	.text
+	.global brlt
+brlt:
+	brlt R0,R0,0
+	.text
+	.global brle
+brle:
+	brle R0,R0,0
+	.text
+	.global breq
+breq:
+	breq R0,R0,0
+	.text
+	.global jmp
+jmp:
+	jmp 0
+	.text
+	.global jal
+jal:
+	jal R0,R0
+	.text
+	.global ei
+ei:
+	ei
+	.text
+	.global di
+di:
+	di
+	.text
+	.global reti
+reti:
+	reti R0
+	.text
+	.global ldw
+ldw:
+	ldw R0,R0,#0
+	.text
+	.global stw
+stw:
+	stw R0,R0,#0
+	.text
+	.global si
+si:
+	si R0
+	.global brne
+brne:
+	brne R0,R0,0
+	.global break
+break:
+	break
+	.text
+	.global nop
+nop:
+	nop
diff --git a/gas/testsuite/gas/mt/badinsn.s b/gas/testsuite/gas/mt/badinsn.s
new file mode 100644
index 000000000000..7c817fe4ebcf
--- /dev/null
+++ b/gas/testsuite/gas/mt/badinsn.s
@@ -0,0 +1,3 @@
+; Bogus instruction mnemonic should generate an error.
+
+addcrap R1,R2,R3
diff --git a/gas/testsuite/gas/mt/badinsn1.s b/gas/testsuite/gas/mt/badinsn1.s
new file mode 100644
index 000000000000..32f487d1d194
--- /dev/null
+++ b/gas/testsuite/gas/mt/badinsn1.s
@@ -0,0 +1,3 @@
+; Extra operand should generate and error message.
+
+add R1,R2,R3,R4
diff --git a/gas/testsuite/gas/mt/badoffsethigh.s b/gas/testsuite/gas/mt/badoffsethigh.s
new file mode 100644
index 000000000000..eb293a798f4d
--- /dev/null
+++ b/gas/testsuite/gas/mt/badoffsethigh.s
@@ -0,0 +1,4 @@
+; Offset greater than #32767 should cause an error since the offset is 
+; a signed quantity.
+
+brlt R1,R2,$32768
diff --git a/gas/testsuite/gas/mt/badoffsetlow.s b/gas/testsuite/gas/mt/badoffsetlow.s
new file mode 100644
index 000000000000..1cbfb9115a36
--- /dev/null
+++ b/gas/testsuite/gas/mt/badoffsetlow.s
@@ -0,0 +1,6 @@
+; Offset less than #-32786 should cause an error since the offset is
+; a signed quantity.  Also tests expression parsing.
+
+label1: add R1,R2,R3
+label2:	add R4,R5,R6
+	brlt R7,R8, ((label1-label2)-32765) ; evaluates to -32769
diff --git a/gas/testsuite/gas/mt/badorder.s b/gas/testsuite/gas/mt/badorder.s
new file mode 100644
index 000000000000..901f31e88069
--- /dev/null
+++ b/gas/testsuite/gas/mt/badorder.s
@@ -0,0 +1,3 @@
+; Good operands in the wrong order should generate an error.
+
+addui R1, #32 R2
diff --git a/gas/testsuite/gas/mt/badreg.s b/gas/testsuite/gas/mt/badreg.s
new file mode 100644
index 000000000000..4bec7f4f11db
--- /dev/null
+++ b/gas/testsuite/gas/mt/badreg.s
@@ -0,0 +1,3 @@
+; Bad register name should generate an error.
+
+add R16,R10,R9
diff --git a/gas/testsuite/gas/mt/badsignedimmhigh.s b/gas/testsuite/gas/mt/badsignedimmhigh.s
new file mode 100644
index 000000000000..802c34d54184
--- /dev/null
+++ b/gas/testsuite/gas/mt/badsignedimmhigh.s
@@ -0,0 +1,3 @@
+; Offset greater than #32767 should cause an error.
+
+addi R1,R2,#32768
diff --git a/gas/testsuite/gas/mt/badsignedimmlow.s b/gas/testsuite/gas/mt/badsignedimmlow.s
new file mode 100644
index 000000000000..46a62981a72b
--- /dev/null
+++ b/gas/testsuite/gas/mt/badsignedimmlow.s
@@ -0,0 +1,3 @@
+; Immediate lower than #-32769 should cause an error.
+
+addi R1,R2,#-32769
diff --git a/gas/testsuite/gas/mt/badsyntax.s b/gas/testsuite/gas/mt/badsyntax.s
new file mode 100644
index 000000000000..9c8e50159f0c
--- /dev/null
+++ b/gas/testsuite/gas/mt/badsyntax.s
@@ -0,0 +1,3 @@
+; Good mnemonic with wrong operands should generate an error.
+
+add R1,R2,#0
diff --git a/gas/testsuite/gas/mt/badsyntax1.s b/gas/testsuite/gas/mt/badsyntax1.s
new file mode 100644
index 000000000000..64fd6a509589
--- /dev/null
+++ b/gas/testsuite/gas/mt/badsyntax1.s
@@ -0,0 +1,3 @@
+; Good mnemonic with too few operands should generate an error.
+
+add R1,R2
diff --git a/gas/testsuite/gas/mt/badunsignedimmhigh.s b/gas/testsuite/gas/mt/badunsignedimmhigh.s
new file mode 100644
index 000000000000..1f0200f6758d
--- /dev/null
+++ b/gas/testsuite/gas/mt/badunsignedimmhigh.s
@@ -0,0 +1,3 @@
+; Offset greater than #$FFFF should cause an error.
+
+andi R1,R2,#$10000
diff --git a/gas/testsuite/gas/mt/badunsignedimmlow.s b/gas/testsuite/gas/mt/badunsignedimmlow.s
new file mode 100644
index 000000000000..8df821515b6b
--- /dev/null
+++ b/gas/testsuite/gas/mt/badunsignedimmlow.s
@@ -0,0 +1,3 @@
+; Offset less than #0 should cause an error.
+
+andi R1,R2,#-1
diff --git a/gas/testsuite/gas/mt/errors.exp b/gas/testsuite/gas/mt/errors.exp
new file mode 100644
index 000000000000..30d217fc776d
--- /dev/null
+++ b/gas/testsuite/gas/mt/errors.exp
@@ -0,0 +1,79 @@
+# Test for error messages when a bad register name, an out of range operand, or 
+# invalid syntax is used.  Adapted from Ben Elliston's load-hazard testcase.
+
+# Run GAS and check that it emits the desired error for the test case.
+# Arguments:
+#   file -- name of the test case to assemble.
+#   testname -- a string describing the test.
+#   warnpattern -- a regular expression, suitable for use by the Tcl
+#     regexp command, to decide if the warning string was emitted by
+#     the assembler to stderr.
+
+proc mrisc1_error_test { file testname {warnpattern ""} } {
+    global comp_output
+
+    gas_run $file "" ">/dev/null"
+    verbose "output was $comp_output" 2
+
+    if {$warnpattern == ""} {
+	if {$comp_output == ""} { pass $testname } else { fail $testname }
+	return
+    }
+
+    if {[regexp "Error: $warnpattern" $comp_output]} {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+if [istarget mt-*-*] {
+    foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] {
+	set file [file tail $file]
+	switch -- $file {
+	    "badreg.s" {
+		set warnpattern "unrecognized keyword/register name *"
+	    }
+	    "badorder.s" {
+		set warnpattern "unrecognized form of instruction*"
+	    }
+	    "badsyntax.s" {
+		set warnpattern "unrecognized keyword/register name *"
+	    }
+	    "badsyntax1.s" {
+		set warnpattern "unrecognized form of instruction*"
+	    }
+	    "badoffsethigh.s" {
+		set warnpattern "Operand out of range. Must be between -32768 and 32767.*"
+	    }
+	    "badoffsetlow.s" {
+		set warnpattern "Operand out of range. Must be between -32768 and 32767.*"
+	    }
+	    "badunsignedimmhigh.s" {
+		set warnpattern "operand out of range (65536 not between 0 and 65535)*"
+	    }
+	    "badunsignedimmlow.s" {
+		set warnpattern "operand out of range (65536 not between 0 and 65535)*"
+	    }
+	    "badsignedimmhigh.s" {
+		set warnpattern "operand out of range.*"
+	    }
+	    "badsignedimmlow.s" {
+		set warnpattern "operand out of range.*"
+	    }
+	    "badinsn.s" {
+		set warnpattern "unrecognized instruction *"
+	    }
+	    "badinsn1.s" {
+		set warnpattern "junk at end of line *"
+	    }
+            default {
+                error "no expected result specified for $file"
+                return
+
+	    }
+	}
+	mrisc1_error_test $file "assembler emits error for $file" $warnpattern
+    }
+
+}
diff --git a/gas/testsuite/gas/mt/ldst.s b/gas/testsuite/gas/mt/ldst.s
new file mode 100644
index 000000000000..174bcc896576
--- /dev/null
+++ b/gas/testsuite/gas/mt/ldst.s
@@ -0,0 +1,28 @@
+; load/store tests
+
+	.data
+
+ldw_data:
+	.word 0xbabeface
+
+	.text
+
+ld_text:
+	ld	r4, r3
+	ld	r3, #8
+	ld	r5, #ld_text
+	ldh	r6, #ldh_text
+	ldh	r4, #4000
+	ldh	r5, #0x8000
+	ldh	r5, #-5
+	ldh	r5, #-0x8000
+	ldh	r0, #0xffff
+ldh_text:
+	ldw	r9, #30233000
+	ldw	r3, #ldw_data
+	ldb	r3, @[r9+r2]
+	ldb	@[r9+r3], r5	; store
+	ldb	r3, @[r8+6]
+	ldb	@[r8+7], r3	; store
+	ldw	r9, @[r14+23]
+	ldw	@[r14+10], r9	; store
diff --git a/gas/testsuite/gas/mt/misc.d b/gas/testsuite/gas/mt/misc.d
new file mode 100644
index 000000000000..aec342497bf8
--- /dev/null
+++ b/gas/testsuite/gas/mt/misc.d
@@ -0,0 +1,21 @@
+#as:
+#objdump: -dr
+#name: misc
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 12 00 00 	add R0,R1,R2
+   4:	00 12 00 00 	add R0,R1,R2
+   8:	00 23 10 00 	add R1,R2,R3
+   c:	00 33 10 00 	add R1,R3,R3
+  10:	00 56 40 00 	add R4,R5,R6
+  14:	00 89 70 00 	add R7,R8,R9
+  18:	00 bc a0 00 	add R10,R11,R12
+  1c:	00 ef d0 00 	add R13,R14,R15
+  20:	03 dc 00 01 	addui R12,R13,#\$1
+  24:	03 fe 00 01 	addui R14,R15,#\$1
+  28:	03 10 00 00 	addui R0,R1,#\$0
+  2c:	03 10 ff ff 	addui R0,R1,#\$ffff
diff --git a/gas/testsuite/gas/mt/misc.s b/gas/testsuite/gas/mt/misc.s
new file mode 100644
index 000000000000..3a7cd4ee71fa
--- /dev/null
+++ b/gas/testsuite/gas/mt/misc.s
@@ -0,0 +1,21 @@
+; Check that register names, both upper and lower case work and that
+; the spacing between the operands doesn't matter.
+
+add R0,R1,R2
+add r0,r1,r2
+add R1,R2,r3
+add R1, R3, r3
+add R4,R5,R6
+add R7,R8,R9
+add R10,R11,R12
+add R13,R14,R15
+addui fp,sp,#1
+addui ra,ira,#1
+
+; Check that the range of legal operand values is accepted.
+
+addui R0,R1,#0
+addui R0,R1,#$FFFF
+
+
+
diff --git a/gas/testsuite/gas/mt/ms1-16-003.d b/gas/testsuite/gas/mt/ms1-16-003.d
new file mode 100644
index 000000000000..f8556962f84b
--- /dev/null
+++ b/gas/testsuite/gas/mt/ms1-16-003.d
@@ -0,0 +1,33 @@
+#as: -march=ms1-16-003
+#objdump: -dr
+#name: ms1-16-003
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <iflush>:
+   0:	6a 00 00 00 	iflush
+00000004 <mul>:
+   4:	08 00 00 00 	mul R0,R0,R0
+00000008 <muli>:
+   8:	09 00 00 00 	muli R0,R0,#\$0
+0000000c <dbnz_>:
+   c:	3d 00 00 00 	dbnz R0,c <dbnz_>
+[ 	]*c: R_MS1_PC16	dbnz
+00000010 <fbcbincs>:
+  10:	f0 00 00 00 	fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000014 <mfbcbincs>:
+  14:	f4 00 00 00 	mfbcbincs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000018 <fbcbincrs>:
+  18:	f8 00 00 00 	fbcbincrs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+0000001c <mfbcbincrs>:
+  1c:	fc 00 00 00 	mfbcbincrs R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000020 <wfbinc>:
+  20:	e0 00 00 00 	wfbinc #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000024 <mwfbinc>:
+  24:	e4 00 00 00 	mwfbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000028 <wfbincr>:
+  28:	e8 00 00 00 	wfbincr R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+0000002c <mwfbincr>:
+  2c:	ec 00 00 00 	mwfbincr R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
diff --git a/gas/testsuite/gas/mt/ms1-16-003.s b/gas/testsuite/gas/mt/ms1-16-003.s
new file mode 100644
index 000000000000..516fff571754
--- /dev/null
+++ b/gas/testsuite/gas/mt/ms1-16-003.s
@@ -0,0 +1,54 @@
+	.text
+	.global iflush
+iflush:
+	iflush
+
+	.global mul
+mul:
+	mul R0, R0, R0
+	
+	.global muli
+muli:
+	muli R0, R0, #0
+
+	.global dbnz
+dbnz_:
+	dbnz	r0, dbnz
+
+	.global fbcbincs
+fbcbincs:
+	fbcbincs #0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mfbcbincs
+mfbcbincs:
+	mfbcbincs r0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	
+	.global fbcbincrs
+fbcbincrs:
+	fbcbincrs r0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mfbcbincrs
+mfbcbincrs:
+	mfbcbincrs r0, r0, #0, #0, #0, #0, #0, #0, #0
+	
+	
+	.global wfbinc
+wfbinc:
+# Documentation error.
+#	wfbinc #0, r0, #0, #0, #0, #0, #0, #0, #0, #0
+	wfbinc #0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mwfbinc
+mwfbinc:
+# Documentation error.
+#	mwfbinc r0, #0, #0, r0, #0, #0, #0, #0, #0
+	mwfbinc r0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global wfbincr
+wfbincr:
+	wfbincr r0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mwfbincr
+mwfbincr:
+	mwfbincr r0, r0, #0, #0, #0, #0, #0, #0, #0
diff --git a/gas/testsuite/gas/mt/ms2.d b/gas/testsuite/gas/mt/ms2.d
new file mode 100644
index 000000000000..877105221438
--- /dev/null
+++ b/gas/testsuite/gas/mt/ms2.d
@@ -0,0 +1,18 @@
+#as: -march=ms2
+#objdump: -dr
+#name: ms2
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <code>:
+   0:	3e 10 00 05 	loop R1,1c <label>
+   4:	3f 00 10 04 	loopi #\$10,1c <label>
+   8:	83 ff ff ff 	dfbc #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+   c:	87 ff ff 7f 	dwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$3f
+  10:	8b ff ff ff 	fbwfb #\$7,#\$7,#\$ffffffff,#\$ffffffff,#\$1,#\$1,#\$3f
+  14:	8f f0 ff ff 	dfbr #\$7,#\$7,R0,#\$7,#\$7,#\$7,#\$1,#\$3f
+  18:	12 00 00 00 	nop
+0000001c <label>:
+  1c:	f0 00 00 00 	fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
diff --git a/gas/testsuite/gas/mt/ms2.s b/gas/testsuite/gas/mt/ms2.s
new file mode 100644
index 000000000000..37efbf04b6e5
--- /dev/null
+++ b/gas/testsuite/gas/mt/ms2.s
@@ -0,0 +1,11 @@
+
+code:	
+	loop R1, label
+	loopi #16,label
+	dfbc #7,#7,#-1,#-1,#1,#1,#63
+	dwfb #7,#7,#-1,#-1,#1,#63
+	fbwfb #7,#7,#-1,#-1,#1,#1,#63
+	dfbr #7,#7,R0,#7,#7,#7,#1,#63
+	nop
+label:	 
+	fbcbincs  #0,#0,#0,#0,#0,#0,#0,#0,#0,#0
diff --git a/gas/testsuite/gas/mt/msys.d b/gas/testsuite/gas/mt/msys.d
new file mode 100644
index 000000000000..fb135dd5e7cf
--- /dev/null
+++ b/gas/testsuite/gas/mt/msys.d
@@ -0,0 +1,78 @@
+#as: -nosched
+#objdump: -dr
+#name: msys 
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+   4:	84 00 00 00 	ldfb R0,R0,#\$0
+   8:	88 00 00 00 	stfb R0,R0,#\$0
+   c:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  10:	90 00 00 00 	mfbcb R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0
+  14:	94 00 00 00 	fbcci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  18:	98 00 00 00 	fbrci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  1c:	9c 00 00 00 	fbcri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  20:	a0 00 00 00 	fbrri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  24:	a4 00 00 00 	mfbcci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  28:	a8 00 00 00 	mfbrci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  2c:	ac 00 00 00 	mfbcri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  30:	b0 00 00 00 	mfbrri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  34:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  38:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  3c:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  40:	c0 00 00 00 	cbcast #\$0,#\$0,#\$0
+  44:	c4 00 00 00 	dupcbcast #\$0,#\$0,#\$0,#\$0
+  48:	c8 00 00 00 	wfbi #\$0,#\$0,#\$0,#\$0,#\$0
+  4c:	cc 00 00 00 	wfb R0,R0,#\$0,#\$0,#\$0
+  50:	d0 00 00 00 	rcrisc R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  54:	d4 00 00 00 	fbcbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  58:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  5c:	64 00 e0 00 	si R14
+  60:	b4 00 00 40 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0
+  64:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  68:	b4 00 00 40 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0
+  6c:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  70:	64 00 e0 00 	si R14
+  74:	b8 08 00 00 	rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  78:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  7c:	b8 08 00 00 	rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  80:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  84:	64 00 e0 00 	si R14
+  88:	bc 20 00 00 	mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  8c:	bc 10 00 00 	mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  90:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  94:	bc 20 00 00 	mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  98:	bc 10 00 00 	mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  9c:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  a0:	64 00 e0 00 	si R14
+  a4:	d8 80 00 00 	rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0
+  a8:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  ac:	d8 80 00 00 	rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0
+  b0:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  b4:	64 00 e0 00 	si R14
+  b8:	80 00 80 00 	ldctxt R0,R0,#\$1,#\$0,#\$0
+  bc:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+  c0:	80 00 80 00 	ldctxt R0,R0,#\$1,#\$0,#\$0
+  c4:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+  c8:	8c 00 08 00 	fbcb R0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0
+  cc:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  d0:	c0 00 00 40 	cbcast #\$0,#\$1,#\$0
+  d4:	c0 00 00 00 	cbcast #\$0,#\$0,#\$0
+  d8:	64 00 e0 00 	si R14
+  dc:	8c 00 04 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0
+  e0:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  e4:	8c 00 04 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0
+  e8:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  ec:	64 00 e0 00 	si R14
+  f0:	8f 00 00 00 	fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  f4:	8e 00 00 00 	fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  f8:	8d 00 00 00 	fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  fc:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 100:	8f 00 00 00 	fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 104:	8e 00 00 00 	fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 108:	8d 00 00 00 	fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 10c:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 110:	dc 00 00 00 	intlvr R0,#\$0,R0,#\$0,#\$0
diff --git a/gas/testsuite/gas/mt/msys.s b/gas/testsuite/gas/mt/msys.s
new file mode 100644
index 000000000000..4ec028c8b671
--- /dev/null
+++ b/gas/testsuite/gas/mt/msys.s
@@ -0,0 +1,95 @@
+;; This file is a set of tests for the MorphoySys instructions.
+
+; Make sure that each mnemonic gives the proper opcode.  Use R0 and #0
+; for all operands so that everything but the opcode will be 0 in the
+; assembled instructions.
+
+	ldctxt R0,R0,#0,#0,#0
+	ldfb R0,R0,#0
+	stfb R0, R0, #0
+	fbcb R0,#0,#0,#0,#0,#0,#0,#0,#0
+	mfbcb R0,#0,R0,#0,#0,#0,#0,#0
+	fbcci R0,#0,#0,#0,#0,#0,#0,#0
+	fbrci R0,#0,#0,#0,#0,#0,#0,#0
+	fbcri R0,#0,#0,#0,#0,#0,#0,#0
+	fbrri R0,#0,#0,#0,#0,#0,#0,#0
+	mfbcci R0,#0,R0,#0,#0,#0,#0
+	mfbrci R0,#0,R0,#0,#0,#0,#0
+	mfbcri R0,#0,R0,#0,#0,#0,#0
+	mfbrri R0,#0,R0,#0,#0,#0,#0
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#0,#0
+	rcfbcb #0,#0,#0,#0,#0,#0,#0,#0,#0,#0
+	mrcfbcb R0,#0,#0,#0,#0,#0,#0,#0,#0
+	cbcast #0,#0,#0
+	dupcbcast #0,#0,#0,#0
+	wfbi #0,#0,#0,#0,#0
+	wfb R0,R0,#0,#0,#0
+	rcrisc R0,#0,R0,#0,#0,#0,#0,#0,#0
+	fbcbinc R0, #0, #0, #0, #0, #0, #0, #0
+	rcxmode R0, #0, #0, #0, #0, #0, #0, #0, #0
+
+; Check to make sure that the parse routines that allow predifined 
+; symbols (uppaer and lower case) to be used for some of the operands.
+
+; dup operand: dup, xx
+	si R14
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#dup,#0  ; dup = 1
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#xx,#0   ; xx = 0
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#DUP,#0 
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#XX,#0   
+
+; ball operand: all, one
+	si R14
+	rcfbcb #0,#0,#all,#0,#0,#0,#0,#0,#0,#0  ; all = 1
+	rcfbcb #0,#0,#one,#0,#0,#0,#0,#0,#0,#0  ; one = 0
+	rcfbcb #0,#0,#ALL,#0,#0,#0,#0,#0,#0,#0  
+	rcfbcb #0,#0,#ONE,#0,#0,#0,#0,#0,#0,#0  
+
+; type operand: odd, even, oe 
+	si R14
+	mrcfbcb R0,#0,#oe,#0,#0,#0,#0,#0,#0     ; oe = 2
+	mrcfbcb R0,#0,#even,#0,#0,#0,#0,#0,#0   ; even = 1
+	mrcfbcb R0,#0,#odd,#0,#0,#0,#0,#0,#0    ; odd = 0
+	mrcfbcb R0,#0,#OE,#0,#0,#0,#0,#0,#0    
+	mrcfbcb R0,#0,#EVEN,#0,#0,#0,#0,#0,#0   
+	mrcfbcb R0,#0,#ODD,#0,#0,#0,#0,#0,#0    
+
+; xmode operand: pm, xm
+	si R14
+	rcxmode R0, #0, #0, #pm, #0, #0, #0, #0, #0  ; pm = 1
+	rcxmode R0, #0, #0, #xm, #0, #0, #0, #0, #0  ; xm = 0
+	rcxmode R0, #0, #0, #PM, #0, #0, #0, #0, #0  
+	rcxmode R0, #0, #0, #XM, #0, #0, #0, #0, #0 
+
+; rc, rc1, rc2 operands: r,c
+	si R14
+        ldctxt R0,R0,#r,#0,#0            ; rc operand.  r = 1 
+        ldctxt R0,R0,#c,#0,#0            ; rc operand.  c = 0 
+        ldctxt R0,R0,#R,#0,#0            
+        ldctxt R0,R0,#C,#0,#0           
+      
+	fbcb R0,#0,#0,#0,#r,#0,#0,#0,#0  ; rc1 operand.  r = 1
+	fbcb R0,#0,#0,#0,#c,#0,#0,#0,#0  ; rc1 operand.  c = 0
+
+	cbcast #0,#r,#0                  ; rc2 operand.  r = 1
+	cbcast #0,#c,#0                  ; rc2 opearnd.  c = 0
+
+; cbrb operand: cb, rb
+	si R14
+	fbcb R0,#0,#0,#0,#0,#rb,#0,#0,#0  ; rb = 1
+	fbcb R0,#0,#0,#0,#0,#cb,#0,#0,#0  ; cb = 0
+	fbcb R0,#0,#0,#0,#0,#RB,#0,#0,#0 
+	fbcb R0,#0,#0,#0,#0,#CB,#0,#0,#0  
+
+; rbbc operand: rt, br1, br2, cs
+	si R14
+	fbcb R0,#cs,#0,#0,#0,#0,#0,#0,#0   ; cs = 3
+	fbcb R0,#br2,#0,#0,#0,#0,#0,#0,#0  ; br2 = 2
+	fbcb R0,#br1,#0,#0,#0,#0,#0,#0,#0  ; br1 = 1
+	fbcb R0,#rt,#0,#0,#0,#cb,#0,#0,#0  ; rt = 0
+	fbcb R0,#CS,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#BR2,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#BR1,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#RT,#0,#0,#0,#cb,#0,#0,#0  
+
+	intlvr R0, #0, R0, #0, #0
diff --git a/gas/testsuite/gas/mt/mt.exp b/gas/testsuite/gas/mt/mt.exp
new file mode 100644
index 000000000000..97501959a417
--- /dev/null
+++ b/gas/testsuite/gas/mt/mt.exp
@@ -0,0 +1,11 @@
+# MRISC1 assembler testsuite.
+
+if [istarget mt-*-*] {
+    #
+    run_dump_test "allinsn"
+    run_dump_test "misc"
+    run_dump_test "msys"
+    run_dump_test "ms1-16-003"
+    run_dump_test "ms2"
+    #
+}
diff --git a/gas/testsuite/gas/mt/relocs.d b/gas/testsuite/gas/mt/relocs.d
new file mode 100644
index 000000000000..2a752ba2e029
--- /dev/null
+++ b/gas/testsuite/gas/mt/relocs.d
@@ -0,0 +1,68 @@
+
+relocs.x:     file format elf32-(mrisc1|ms1)
+
+Contents of section .text:
+ 2000 00131000 3700dffc 12000000 3700fff8  ....7.......7...
+ 2010 03210000 03212215 03210001 03210000  .!...!"..!...!..
+ 2020 0321ffff 0321eeee 03210005 03210006  .!...!...!...!..
+ 2030 00675000                             .gP.            
+Contents of section .data:
+ 2134 0f000000 00000000 00000000 00000000  ................
+ 2144 00000000 00000000 00000000 00000000  ................
+ 2154 00000000 00000000 00000000 00000000  ................
+ 2164 00000000 00000000 00000000 00000000  ................
+ 2174 00000000 00000000 00000000 00000000  ................
+ 2184 00000000 00000000 00000000 00000000  ................
+ 2194 00000000 00000000 00000000 00000000  ................
+ 21a4 00000000 00000000 00000000 00000000  ................
+ 21b4 00000000 00000000 00000000 00000000  ................
+ 21c4 00000000 00000000 00000000 00000000  ................
+ 21d4 00000000 00000000 00000000 00000000  ................
+ 21e4 00000000 00000000 00000000 00000000  ................
+ 21f4 00000000 00000000 00000000 00000000  ................
+ 2204 00000000 00000000 00000000 00000000  ................
+ 2214 00020000 00000000 00000000 00000000  ................
+ 2224 00000000 00000000 00000000 00000000  ................
+ 2234 00000000 00000000 00000000 00000000  ................
+ 2244 00000000 00000000 00000000 00000000  ................
+ 2254 00000000 00000000 00000000 00000000  ................
+ 2264 00000000 00000000 00000000 00000000  ................
+ 2274 00000000 00000000 00000000 00000000  ................
+ 2284 00000000 00000000 00000000 00000000  ................
+ 2294 00000000 00000000 00000000 00000000  ................
+ 22a4 00000000 00000000 00000000 00000000  ................
+ 22b4 00000000 00000000 00000000 00000000  ................
+ 22c4 00000000 00000000 00000000 00000000  ................
+ 22d4 00000000 00000000 00000000 00000000  ................
+ 22e4 00000000 00000000 00000000 00000000  ................
+ 22f4 00000000 00000000 00000000 00000000  ................
+ 2304 00000000 00000000 00000000 00000000  ................
+ 2314 000003                               ...             
+Contents of section .stack:
+ 7ffff0 deaddead                             ....            
+Disassembly of section .text:
+
+00002000 <_start>:
+    2000:	00 13 10 00 	add R1,R1,R3
+
+00002004 <local>:
+    2004:	37 00 df fc 	jmp 0 <_start-0x2000>
+
+00002008 <none>:
+    2008:	12 00 00 00 	nop
+    200c:	37 00 ff f8 	jmp 2004 <local>
+    2010:	03 21 00 00 	addui R1,R2,#\$0
+    2014:	03 21 22 15 	addui R1,R2,#\$2215
+    2018:	03 21 00 01 	addui R1,R2,#\$1
+    201c:	03 21 00 00 	addui R1,R2,#\$0
+    2020:	03 21 ff ff 	addui R1,R2,#\$ffff
+    2024:	03 21 ee ee 	addui R1,R2,#\$eeee
+
+00002028 <dummy1>:
+    2028:	03 21 00 05 	addui R1,R2,#\$5
+
+0000202c <dummy2>:
+    202c:	03 21 00 06 	addui R1,R2,#\$6
+
+00002030 <i2>:
+    2030:	00 67 50 00 	add R5,R6,R7
diff --git a/gas/testsuite/gas/mt/relocs.exp b/gas/testsuite/gas/mt/relocs.exp
new file mode 100644
index 000000000000..076f428bc73b
--- /dev/null
+++ b/gas/testsuite/gas/mt/relocs.exp
@@ -0,0 +1,35 @@
+# Relocation test.
+# This test is special because it exercises the linker's 
+
+proc ld_test { objects ldflags dest test } {
+    set ld_output [target_link $objects $dest $ldflags]
+    if [string match "" $ld_output] then { pass $test } else { fail $test }
+}
+
+
+proc objdump_test { exec flags dest test } {
+    set objcopy [find_binutils_prog objdump]
+    verbose -log "$objcopy $flags $exec > $dest"
+    catch "exec $objcopy $flags $exec > $dest" objdump_output
+    if [string match "" $objdump_output] then { pass $test } else { fail $test }
+}
+
+proc regexp_test { file1 file2 test } {
+    if [regexp_diff $file1 $file2] then { fail $test } else { pass $test }
+}
+
+
+global srcdir subdir
+if [istarget mt-*] {
+    gas_test "relocs1.s" {-o relocs1.o} {} {assembling relocs1}
+
+    #    gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}
+    #    ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x}
+    #    objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x}
+    #    regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly}
+
+    gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}
+    ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x}
+    objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x}
+    regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly}
+}
diff --git a/gas/testsuite/gas/mt/relocs1.s b/gas/testsuite/gas/mt/relocs1.s
new file mode 100644
index 000000000000..e874d50bee3a
--- /dev/null
+++ b/gas/testsuite/gas/mt/relocs1.s
@@ -0,0 +1,31 @@
+;; This test is meant to exercise every unusual reloc supported
+;; by the mrisc port.  (Ok, so there's only one so far.  :P)
+
+	.text
+text:	
+	.global _start
+_start:	
+	add R1,R1,R3
+
+; Make sure local fixups work.
+local:
+        jmp (dummy2-dummy1)  
+
+; Test the PC16 reloc.
+none:
+	 or R0,R0,R0 ;nop to conform to scheduling restrictions
+	 jmp local                
+	                      
+; Test the %hi16 and %lo16 relocs
+addui R1,R2,#%hi16(d2)
+addui R1,R2,#%lo16(d2) 	
+addui R1,R2,#%hi16(65536)
+addui R1,R2,#%lo16(65536)
+addui R1,R2,#%hi16($FFFFEEEE)
+addui R1,R2,#%lo16($FFFFEEEE)
+
+dummy1: addui R1, R2, #5
+dummy2: addui R1, R2, #6
+
+	.data
+d1:	.byte $f
diff --git a/gas/testsuite/gas/mt/relocs2.s b/gas/testsuite/gas/mt/relocs2.s
new file mode 100644
index 000000000000..7435406595cf
--- /dev/null
+++ b/gas/testsuite/gas/mt/relocs2.s
@@ -0,0 +1,22 @@
+	.text
+	;; Put code near the top of the address space
+text:
+	.global i2
+i2:	
+	
+	add R5, R6, R7
+
+	.data
+	;; Note that the .org that follows is more or less equivalent
+	;; to a .space, since the amount specified will be treated like
+	;; padding to be added between the .data section in relocs1.s
+	;; and this one.
+	;; Note also that the two test variables (d2 & d3) are intentionally
+	;; roughly $100 apart, so that the FR9 relocation processing in
+	;; bfd/elf32-ip2k.c (ip2k_final_link_relocate) is tested a little more.
+	.org $e0
+	.global d2
+d2:	.byte 2
+	.space $100
+	.global d3
+d3:	.byte 3
diff --git a/gas/testsuite/gas/pdp11/opcode.d b/gas/testsuite/gas/pdp11/opcode.d
index 2e6a981fc74b..4b81857dc2e6 100644
--- a/gas/testsuite/gas/pdp11/opcode.d
+++ b/gas/testsuite/gas/pdp11/opcode.d
@@ -134,7 +134,7 @@ Disassembly of section .text:
  108:	7c7f [	 ]*cvtlpi
  10a:	7d80 [	 ]*med
  10c:	7dea [	 ]*xfc	52
- 10e:	7e3e [	 ]*sob	r0, 10c <start2\+0x106>
+ 10e:	7e02 [	 ]*sob	r0, 10c <start2\+0x106>
  110:	80fd [	 ]*bpl	10c <start2\+0x106>
  112:	81fc [	 ]*bmi	10c <start2\+0x106>
  114:	82fb [	 ]*bhi	10c <start2\+0x106>
diff --git a/gas/testsuite/gas/pdp11/opcode.s b/gas/testsuite/gas/pdp11/opcode.s
index c8598fb3c6bc..f7b7b3173c36 100644
--- a/gas/testsuite/gas/pdp11/opcode.s
+++ b/gas/testsuite/gas/pdp11/opcode.s
@@ -13,7 +13,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 foo:	.word	0
 bar:	.word	foo
diff --git a/gas/testsuite/gas/ppc/aix.exp b/gas/testsuite/gas/ppc/aix.exp
index dc180d52629f..9a8b2b7f40bf 100644
--- a/gas/testsuite/gas/ppc/aix.exp
+++ b/gas/testsuite/gas/ppc/aix.exp
@@ -13,7 +13,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 #
 
 #
diff --git a/gas/testsuite/gas/ppc/altivec.d b/gas/testsuite/gas/ppc/altivec.d
index ca234b1e6324..46d17d5ca331 100644
--- a/gas/testsuite/gas/ppc/altivec.d
+++ b/gas/testsuite/gas/ppc/altivec.d
@@ -2,7 +2,7 @@
 #objdump: -dr
 #name: AltiVec tests
 
-.*: +file format elf32-powerpc
+.*: +file format elf32-powerpc.*
 
 Disassembly of section \.text:
 
diff --git a/gas/testsuite/gas/ppc/astest.d b/gas/testsuite/gas/ppc/astest.d
index 758f9ce84c66..715bc4e46012 100644
--- a/gas/testsuite/gas/ppc/astest.d
+++ b/gas/testsuite/gas/ppc/astest.d
@@ -33,37 +33,41 @@ Disassembly of section \.text:
   38:	48 00 00 00 	b       38 <apfour\+0x28>
 			38: R_PPC_LOCAL24PC	a
   3c:	4b ff ff d4 	b       10 <apfour>
-
   40:	00 00 00 40 	\.long 0x40
 			40: R_PPC_ADDR32	\.text\+0x40
-
   44:	00 00 00 4c 	\.long 0x4c
 			44: R_PPC_ADDR32	\.text\+0x4c
   48:	00 00 00 00 	\.long 0x0
 			48: R_PPC_REL32	x
   4c:	00 00 00 04 	\.long 0x4
 			4c: R_PPC_REL32	x\+0x4
-	\.\.\.
+  50:	00 00 00 00 	\.long 0x0
 			50: R_PPC_REL32	z
-			54: R_PPC_REL32	y
+  54:	00 00 00 04 	\.long 0x4
+			54: R_PPC_REL32	\.data\+0x4
+  58:	00 00 00 00 	\.long 0x0
 			58: R_PPC_ADDR32	x
-			5c: R_PPC_ADDR32	y
+  5c:	00 00 00 04 	\.long 0x4
+			5c: R_PPC_ADDR32	\.data\+0x4
+  60:	00 00 00 00 	\.long 0x0
 			60: R_PPC_ADDR32	z
   64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC_ADDR32	x\+0xf+ffffffc
-  68:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-			68: R_PPC_ADDR32	y\+0xf+ffffffc
+  68:	00 00 00 00 	\.long 0x0
+			68: R_PPC_ADDR32	\.data
   6c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			6c: R_PPC_ADDR32	z\+0xf+ffffffc
   70:	ff ff ff 9c 	\.long 0xffffff9c
   74:	ff ff ff 9c 	\.long 0xffffff9c
-	\.\.\.
+  78:	00 00 00 00 	\.long 0x0
 			78: R_PPC_ADDR32	a
-			7c: R_PPC_ADDR32	b
-			80: R_PPC_ADDR32	apfour
+  7c:	00 00 00 10 	\.long 0x10
+			7c: R_PPC_ADDR32	\.text\+0x10
+  80:	00 00 00 10 	\.long 0x10
+			80: R_PPC_ADDR32	\.text\+0x10
   84:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-  88:	00 00 00 02 	\.long 0x2
-			88: R_PPC_ADDR32	apfour\+0x2
+  88:	00 00 00 12 	\.long 0x12
+			88: R_PPC_ADDR32	\.text\+0x12
   8c:	00 00 00 00 	\.long 0x0
 Disassembly of section \.data:
 
diff --git a/gas/testsuite/gas/ppc/astest2.d b/gas/testsuite/gas/ppc/astest2.d
index 273ca57bf850..e0e1943b06b9 100644
--- a/gas/testsuite/gas/ppc/astest2.d
+++ b/gas/testsuite/gas/ppc/astest2.d
@@ -29,26 +29,28 @@ Disassembly of section \.text:
   38:	48 00 00 00 	b       38 <foo\+0x38>
 			38: R_PPC_LOCAL24PC	a
   3c:	48 00 00 40 	b       7c <apfour>
-
   40:	00 00 00 40 	\.long 0x40
 			40: R_PPC_ADDR32	\.text\+0x40
-
   44:	00 00 00 4c 	\.long 0x4c
 			44: R_PPC_ADDR32	\.text\+0x4c
   48:	00 00 00 00 	\.long 0x0
 			48: R_PPC_REL32	x
   4c:	00 00 00 04 	\.long 0x4
 			4c: R_PPC_REL32	x\+0x4
-	\.\.\.
+  50:	00 00 00 00 	\.long 0x0
 			50: R_PPC_REL32	z
-			54: R_PPC_REL32	y
+  54:	00 00 00 04 	\.long 0x4
+			54: R_PPC_REL32	\.data\+0x4
+  58:	00 00 00 00 	\.long 0x0
 			58: R_PPC_ADDR32	x
-			5c: R_PPC_ADDR32	y
+  5c:	00 00 00 04 	\.long 0x4
+			5c: R_PPC_ADDR32	\.data\+0x4
+  60:	00 00 00 00 	\.long 0x0
 			60: R_PPC_ADDR32	z
   64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC_ADDR32	x\+0xf+ffffffc
-  68:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-			68: R_PPC_ADDR32	y\+0xf+ffffffc
+  68:	00 00 00 00 	\.long 0x0
+			68: R_PPC_ADDR32	\.data
   6c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			6c: R_PPC_ADDR32	z\+0xf+ffffffc
   70:	00 00 00 08 	\.long 0x8
@@ -59,12 +61,13 @@ Disassembly of section \.text:
 			78: R_PPC_ADDR32	a
 
 0+000007c <apfour>:
-	\.\.\.
-			7c: R_PPC_ADDR32	b
-			80: R_PPC_ADDR32	apfour
+  7c:	00 00 00 7c 	\.long 0x7c
+			7c: R_PPC_ADDR32	\.text\+0x7c
+  80:	00 00 00 7c 	\.long 0x7c
+			80: R_PPC_ADDR32	\.text\+0x7c
   84:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-  88:	00 00 00 02 	\.long 0x2
-			88: R_PPC_ADDR32	apfour\+0x2
+  88:	00 00 00 7e 	\.long 0x7e
+			88: R_PPC_ADDR32	\.text\+0x7e
   8c:	00 00 00 00 	\.long 0x0
   90:	60 00 00 00 	nop
   94:	40 a5 ff fc 	ble-    cr1,90 <apfour\+0x14>
diff --git a/gas/testsuite/gas/ppc/astest2_64.d b/gas/testsuite/gas/ppc/astest2_64.d
index bc3cddf22e20..356db54eccc2 100644
--- a/gas/testsuite/gas/ppc/astest2_64.d
+++ b/gas/testsuite/gas/ppc/astest2_64.d
@@ -34,16 +34,20 @@ Disassembly of section \.text:
 			40: R_PPC64_REL32	x
   44:	00 00 00 04 	\.long 0x4
 			44: R_PPC64_REL32	x\+0x4
-	\.\.\.
+  48:	00 00 00 00 	\.long 0x0
 			48: R_PPC64_REL32	z
-			4c: R_PPC64_REL32	y
+  4c:	00 00 00 04 	\.long 0x4
+			4c: R_PPC64_REL32	\.data\+0x4
+  50:	00 00 00 00 	\.long 0x0
 			50: R_PPC64_ADDR32	x
-			54: R_PPC64_ADDR32	y
+  54:	00 00 00 04 	\.long 0x4
+			54: R_PPC64_ADDR32	\.data\+0x4
+  58:	00 00 00 00 	\.long 0x0
 			58: R_PPC64_ADDR32	z
   5c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			5c: R_PPC64_ADDR32	x\+0xfffffffffffffffc
-  60:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-			60: R_PPC64_ADDR32	y\+0xfffffffffffffffc
+  60:	00 00 00 00 	\.long 0x0
+			60: R_PPC64_ADDR32	\.data
   64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC64_ADDR32	z\+0xfffffffffffffffc
   68:	00 00 00 08 	\.long 0x8
@@ -54,12 +58,13 @@ Disassembly of section \.text:
 			70: R_PPC64_ADDR32	a
 
 0000000000000074 <apfour>:
-	\.\.\.
-			74: R_PPC64_ADDR32	b
-			78: R_PPC64_ADDR32	apfour
+  74:	00 00 00 74 	\.long 0x74
+			74: R_PPC64_ADDR32	\.text\+0x74
+  78:	00 00 00 74 	\.long 0x74
+			78: R_PPC64_ADDR32	\.text\+0x74
   7c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-  80:	00 00 00 02 	\.long 0x2
-			80: R_PPC64_ADDR32	apfour\+0x2
+  80:	00 00 00 76 	\.long 0x76
+			80: R_PPC64_ADDR32	\.text\+0x76
   84:	00 00 00 00 	\.long 0x0
 Disassembly of section \.data:
 
diff --git a/gas/testsuite/gas/ppc/astest64.d b/gas/testsuite/gas/ppc/astest64.d
index d66e72c1be16..d8edf05a3397 100644
--- a/gas/testsuite/gas/ppc/astest64.d
+++ b/gas/testsuite/gas/ppc/astest64.d
@@ -38,27 +38,33 @@ Disassembly of section \.text:
 			40: R_PPC64_REL32	x
   44:	00 00 00 04 	\.long 0x4
 			44: R_PPC64_REL32	x\+0x4
-	\.\.\.
+  48:	00 00 00 00 	\.long 0x0
 			48: R_PPC64_REL32	z
-			4c: R_PPC64_REL32	y
+  4c:	00 00 00 04 	\.long 0x4
+			4c: R_PPC64_REL32	\.data\+0x4
+  50:	00 00 00 00 	\.long 0x0
 			50: R_PPC64_ADDR32	x
-			54: R_PPC64_ADDR32	y
+  54:	00 00 00 04 	\.long 0x4
+			54: R_PPC64_ADDR32	\.data\+0x4
+  58:	00 00 00 00 	\.long 0x0
 			58: R_PPC64_ADDR32	z
   5c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			5c: R_PPC64_ADDR32	x\+0xfffffffffffffffc
-  60:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-			60: R_PPC64_ADDR32	y\+0xfffffffffffffffc
+  60:	00 00 00 00 	\.long 0x0
+			60: R_PPC64_ADDR32	\.data
   64:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
 			64: R_PPC64_ADDR32	z\+0xfffffffffffffffc
   68:	ff ff ff a4 	\.long 0xffffffa4
   6c:	ff ff ff a4 	\.long 0xffffffa4
-	\.\.\.
+  70:	00 00 00 00 	\.long 0x0
 			70: R_PPC64_ADDR32	a
-			74: R_PPC64_ADDR32	b
-			78: R_PPC64_ADDR32	apfour
+  74:	00 00 00 10 	\.long 0x10
+			74: R_PPC64_ADDR32	\.text\+0x10
+  78:	00 00 00 10 	\.long 0x10
+			78: R_PPC64_ADDR32	\.text\+0x10
   7c:	ff ff ff fc 	fnmsub  f31,f31,f31,f31
-  80:	00 00 00 02 	\.long 0x2
-			80: R_PPC64_ADDR32	apfour\+0x2
+  80:	00 00 00 12 	\.long 0x12
+			80: R_PPC64_ADDR32	\.text\+0x12
   84:	00 00 00 00 	\.long 0x0
 Disassembly of section \.data:
 
diff --git a/gas/testsuite/gas/ppc/booke.d b/gas/testsuite/gas/ppc/booke.d
index a8d5c57202d0..56c7d5e3ae45 100644
--- a/gas/testsuite/gas/ppc/booke.d
+++ b/gas/testsuite/gas/ppc/booke.d
@@ -2,27 +2,27 @@
 #objdump: -dr -Mbooke
 #name: BookE tests
 
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
 
 Disassembly of section \.text:
 
 0+0000000 <start>:
    0:	24 25 00 30 	bce     1,4\*cr1\+gt,30 <branch_target_1>
    4:	24 46 00 3d 	bcel    2,4\*cr1\+eq,40 <branch_target_2>
-   8:	24 67 00 02 	bcea    3,4\*cr1\+so,0 <start>
-			8: R_PPC(64)?_ADDR14	branch_target_3
-   c:	24 88 00 03 	bcela   4,4\*cr2\+lt,0 <start>
-			c: R_PPC(64)?_ADDR14	branch_target_4
+   8:	24 67 00 52 	bcea    3,4\*cr1\+so,50 <branch_target_3>
+			8: R_PPC(64)?_ADDR14	\.text\+0x50
+   c:	24 88 00 73 	bcela   4,4\*cr2\+lt,70 <branch_target_4>
+			c: R_PPC(64)?_ADDR14	\.text\+0x70
   10:	4c a9 00 22 	bclre   5,4\*cr2\+gt
   14:	4c aa 00 23 	bclrel  5,4\*cr2\+eq
   18:	4d 0b 04 22 	bcctre  8,4\*cr2\+so
   1c:	4d 0c 04 23 	bcctrel 8,4\*cr3\+lt
   20:	58 00 00 74 	be      94 <branch_target_5>
   24:	58 00 00 89 	bel     ac <branch_target_6>
-  28:	58 00 00 02 	bea     0 <start>
-			28: R_PPC(64)?_ADDR24	branch_target_7
-  2c:	58 00 00 03 	bela    0 <start>
-			2c: R_PPC(64)?_ADDR24	branch_target_8
+  28:	58 00 00 f6 	bea     f4 <branch_target_7>
+			28: R_PPC(64)?_ADDR24	\.text\+0xf4
+  2c:	58 00 01 2b 	bela    128 <branch_target_8>
+			2c: R_PPC(64)?_ADDR24	\.text\+0x128
 
 0+0000030 <branch_target_1>:
   30:	e9 09 00 80 	lbze    r8,8\(r9\)
@@ -142,3 +142,11 @@ Disassembly of section \.text:
  1c0:	7c 00 06 ac 	mbar    
  1c4:	7c 00 06 ac 	mbar    
  1c8:	7c 20 06 ac 	mbar    1
+ 1cc:	7c 12 42 a6 	mfsprg  r0,2
+ 1d0:	7c 12 42 a6 	mfsprg  r0,2
+ 1d4:	7c 12 43 a6 	mtsprg  2,r0
+ 1d8:	7c 12 43 a6 	mtsprg  2,r0
+ 1dc:	7c 07 42 a6 	mfsprg  r0,7
+ 1e0:	7c 07 42 a6 	mfsprg  r0,7
+ 1e4:	7c 17 43 a6 	mtsprg  7,r0
+ 1e8:	7c 17 43 a6 	mtsprg  7,r0
diff --git a/gas/testsuite/gas/ppc/booke.s b/gas/testsuite/gas/ppc/booke.s
index 4c40b498ebe2..0c6cf88f66a4 100644
--- a/gas/testsuite/gas/ppc/booke.s
+++ b/gas/testsuite/gas/ppc/booke.s
@@ -134,3 +134,12 @@ branch_target_8:
 	mbar
 	mbar	0
 	mbar	1
+
+	mfsprg 0, 2
+	mfsprg2 0
+	mtsprg 2, 0
+	mtsprg2 0
+	mfsprg 0, 7
+	mfsprg7 0
+	mtsprg 7, 0
+	mtsprg7 0
diff --git a/gas/testsuite/gas/ppc/e500.d b/gas/testsuite/gas/ppc/e500.d
index 0d5f5812c55e..d338d38a236e 100644
--- a/gas/testsuite/gas/ppc/e500.d
+++ b/gas/testsuite/gas/ppc/e500.d
@@ -2,7 +2,7 @@
 #objdump: -dr -Me500
 #name: e500 tests
 
-.*: +file format elf(32)?(64)?-powerpc
+.*: +file format elf(32)?(64)?-powerpc.*
 
 Disassembly of section \.text:
 
diff --git a/gas/testsuite/gas/ppc/power4.d b/gas/testsuite/gas/ppc/power4.d
index 6094848ee5db..148e27a3b220 100644
--- a/gas/testsuite/gas/ppc/power4.d
+++ b/gas/testsuite/gas/ppc/power4.d
@@ -10,7 +10,7 @@ start address 0x0+
 
 Sections:
 Idx Name +Size +VMA +LMA +File off +Algn
- +0 \.text +0+b8 +0+ +0+ +.*
+ +0 \.text +0+c4 +0+ +0+ +.*
  +CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
  +1 \.data +0+10 +0+ +0+ +.*
  +CONTENTS, ALLOC, LOAD, DATA
@@ -19,12 +19,12 @@ Idx Name +Size +VMA +LMA +File off +Algn
  +3 \.toc +0+30 +0+ +0+ +.*
  +CONTENTS, ALLOC, LOAD, RELOC, DATA
 SYMBOL TABLE:
-0+ l +d +\.text	0+ 
-0+ l +d +\.data	0+ 
-0+ l +d +\.bss	0+ 
+0+ l +d +\.text	0+ (|\.text)
+0+ l +d +\.data	0+ (|\.data)
+0+ l +d +\.bss	0+ (|\.bss)
 0+ l +\.data	0+ dsym0
 0+8 l +\.data	0+ dsym1
-0+ l +d +\.toc	0+ 
+0+ l +d +\.toc	0+ (|\.toc)
 0+8 l +\.data	0+ usym0
 0+10 l +\.data	0+ usym1
 0+ +\*UND\*	0+ esym0
@@ -35,13 +35,13 @@ Disassembly of section \.text:
 
 0+ <\.text>:
  +0:	e0 83 00 00 	lq      r4,0\(r3\)
-			2: R_PPC64_ADDR16_LO_DS	dsym0
+			2: R_PPC64_ADDR16_LO_DS	\.data
  +4:	e0 83 00 00 	lq      r4,0\(r3\)
-			6: R_PPC64_ADDR16_LO_DS	dsym1
+			6: R_PPC64_ADDR16_LO_DS	\.data\+0x8
  +8:	e0 83 00 00 	lq      r4,0\(r3\)
-			a: R_PPC64_ADDR16_LO_DS	usym0
- +c:	e0 83 00 00 	lq      r4,0\(r3\)
-			e: R_PPC64_ADDR16_LO_DS	usym1
+			a: R_PPC64_ADDR16_LO_DS	\.data\+0x8
+ +c:	e0 83 00 10 	lq      r4,16\(r3\)
+			e: R_PPC64_ADDR16_LO_DS	\.data\+0x10
  +10:	e0 83 00 00 	lq      r4,0\(r3\)
 			12: R_PPC64_ADDR16_LO_DS	esym0
  +14:	e0 83 00 00 	lq      r4,0\(r3\)
@@ -63,15 +63,15 @@ Disassembly of section \.text:
  +34:	e0 80 00 00 	lq      r4,0\(0\)
 			36: R_PPC64_ADDR16_LO_DS	\.text
  +38:	e0 c3 00 00 	lq      r6,0\(r3\)
-			3a: R_PPC64_GOT16_DS	dsym0
+			3a: R_PPC64_GOT16_DS	\.data
  +3c:	e0 c3 00 00 	lq      r6,0\(r3\)
-			3e: R_PPC64_GOT16_LO_DS	dsym0
+			3e: R_PPC64_GOT16_LO_DS	\.data
  +40:	e0 c3 00 00 	lq      r6,0\(r3\)
-			42: R_PPC64_PLT16_LO_DS	dsym0
+			42: R_PPC64_PLT16_LO_DS	\.data
  +44:	e0 c3 00 00 	lq      r6,0\(r3\)
-			46: R_PPC64_SECTOFF_DS	dsym1
+			46: R_PPC64_SECTOFF_DS	\.data\+0x8
  +48:	e0 c3 00 00 	lq      r6,0\(r3\)
-			4a: R_PPC64_SECTOFF_LO_DS	dsym1
+			4a: R_PPC64_SECTOFF_LO_DS	\.data\+0x8
  +4c:	e0 c4 00 10 	lq      r6,16\(r4\)
  +50:	f8 c7 00 02 	stq     r6,0\(r7\)
  +54:	f8 c7 00 12 	stq     r6,16\(r7\)
@@ -82,20 +82,23 @@ Disassembly of section \.text:
  +68:	7c 6f f1 20 	mtcr    r3
  +6c:	7c 6f f1 20 	mtcr    r3
  +70:	7c 68 11 20 	mtcrf   129,r3
- +74:	7c 70 11 20 	mtcrf   1,r3
- +78:	7c 70 21 20 	mtcrf   2,r3
- +7c:	7c 70 41 20 	mtcrf   4,r3
- +80:	7c 70 81 20 	mtcrf   8,r3
- +84:	7c 71 01 20 	mtcrf   16,r3
- +88:	7c 72 01 20 	mtcrf   32,r3
- +8c:	7c 74 01 20 	mtcrf   64,r3
- +90:	7c 78 01 20 	mtcrf   128,r3
+ +74:	7c 70 11 20 	mtocrf  1,r3
+ +78:	7c 70 21 20 	mtocrf  2,r3
+ +7c:	7c 70 41 20 	mtocrf  4,r3
+ +80:	7c 70 81 20 	mtocrf  8,r3
+ +84:	7c 71 01 20 	mtocrf  16,r3
+ +88:	7c 72 01 20 	mtocrf  32,r3
+ +8c:	7c 74 01 20 	mtocrf  64,r3
+ +90:	7c 78 01 20 	mtocrf  128,r3
  +94:	7c 60 00 26 	mfcr    r3
- +98:	7c 70 10 26 	mfcr    r3,1
- +9c:	7c 70 20 26 	mfcr    r3,2
- +a0:	7c 70 40 26 	mfcr    r3,4
- +a4:	7c 70 80 26 	mfcr    r3,8
- +a8:	7c 71 00 26 	mfcr    r3,16
- +ac:	7c 72 00 26 	mfcr    r3,32
- +b0:	7c 74 00 26 	mfcr    r3,64
- +b4:	7c 78 00 26 	mfcr    r3,128
+ +98:	7c 70 10 26 	mfocrf  r3,1
+ +9c:	7c 70 20 26 	mfocrf  r3,2
+ +a0:	7c 70 40 26 	mfocrf  r3,4
+ +a4:	7c 70 80 26 	mfocrf  r3,8
+ +a8:	7c 71 00 26 	mfocrf  r3,16
+ +ac:	7c 72 00 26 	mfocrf  r3,32
+ +b0:	7c 74 00 26 	mfocrf  r3,64
+ +b4:	7c 78 00 26 	mfocrf  r3,128
+ +b8:	7c 01 17 ec 	dcbz    r1,r2
+ +bc:	7c 23 27 ec 	dcbzl   r3,r4
+ +c0:	7c 05 37 ec 	dcbz    r5,r6
diff --git a/gas/testsuite/gas/ppc/power4.s b/gas/testsuite/gas/ppc/power4.s
index 3514e63f17af..f2a162dc9539 100644
--- a/gas/testsuite/gas/ppc/power4.s
+++ b/gas/testsuite/gas/ppc/power4.s
@@ -68,6 +68,10 @@ dsym1:
 	mfcr	3,0x40
 	mfcr	3,0x80
 
+	dcbz    1, 2
+	dcbzl   3, 4
+	dcbz    5, 6
+
 	.section	".data"
 usym0:	.llong	0xcafebabe
 usym1:
diff --git a/gas/testsuite/gas/ppc/test1elf32.d b/gas/testsuite/gas/ppc/test1elf32.d
index 5654282b396a..2e76061e849e 100644
--- a/gas/testsuite/gas/ppc/test1elf32.d
+++ b/gas/testsuite/gas/ppc/test1elf32.d
@@ -16,9 +16,9 @@ Idx Name +Size +VMA +LMA +File off +Algn
   2 \.bss  +00000000  0+0000  0+0000  .*
  +ALLOC
 SYMBOL TABLE:
-0+0000 l    d  \.text	0+0000 
-0+0000 l    d  \.data	0+0000 
-0+0000 l    d  \.bss	0+0000 
+0+0000 l    d  \.text	0+0000 (|\.text)
+0+0000 l    d  \.data	0+0000 (|\.data)
+0+0000 l    d  \.bss	0+0000 (|\.bss)
 0+0000 l       \.data	0+0000 dsym0
 0+0004 l       \.data	0+0000 dsym1
 0+0004 l       \.data	0+0000 usym0
@@ -36,13 +36,13 @@ Disassembly of section \.text:
 
 0+0000 <\.text>:
    0:	80 63 00 00 	lwz     r3,0\(r3\)
-			2: R_PPC_ADDR16_LO	dsym0
-   4:	80 63 00 00 	lwz     r3,0\(r3\)
-			6: R_PPC_ADDR16_LO	dsym1
-   8:	80 63 00 00 	lwz     r3,0\(r3\)
-			a: R_PPC_ADDR16_LO	usym0
-   c:	80 63 00 00 	lwz     r3,0\(r3\)
-			e: R_PPC_ADDR16_LO	usym1
+			2: R_PPC_ADDR16_LO	\.data
+   4:	80 63 00 04 	lwz     r3,4\(r3\)
+			6: R_PPC_ADDR16_LO	\.data\+0x4
+   8:	80 63 00 04 	lwz     r3,4\(r3\)
+			a: R_PPC_ADDR16_LO	\.data\+0x4
+   c:	80 63 00 08 	lwz     r3,8\(r3\)
+			e: R_PPC_ADDR16_LO	\.data\+0x8
   10:	80 63 00 00 	lwz     r3,0\(r3\)
 			12: R_PPC_ADDR16_LO	esym0
   14:	80 63 00 00 	lwz     r3,0\(r3\)
@@ -54,11 +54,11 @@ Disassembly of section \.text:
   28:	38 60 ff fc 	li      r3,-4
   2c:	38 60 00 04 	li      r3,4
   30:	38 60 00 00 	li      r3,0
-			32: R_PPC_ADDR16_LO	dsym0
+			32: R_PPC_ADDR16_LO	\.data
   34:	38 60 00 00 	li      r3,0
-			36: R_PPC_ADDR16_HI	dsym0
+			36: R_PPC_ADDR16_HI	\.data
   38:	38 60 00 00 	li      r3,0
-			3a: R_PPC_ADDR16_HA	dsym0
+			3a: R_PPC_ADDR16_HA	\.data
   3c:	38 60 ff fc 	li      r3,-4
   40:	38 60 ff ff 	li      r3,-1
   44:	38 60 00 00 	li      r3,0
diff --git a/gas/testsuite/gas/ppc/test1elf64.d b/gas/testsuite/gas/ppc/test1elf64.d
index bfdd4e86222a..8ea8230aae91 100644
--- a/gas/testsuite/gas/ppc/test1elf64.d
+++ b/gas/testsuite/gas/ppc/test1elf64.d
@@ -18,12 +18,12 @@ Idx Name          Size      VMA               LMA               File off  Algn
   3 \.toc          00000030  0000000000000000  0000000000000000  .*
                   CONTENTS, ALLOC, LOAD, RELOC, DATA
 SYMBOL TABLE:
-0000000000000000 l    d  \.text	0000000000000000 
-0000000000000000 l    d  \.data	0000000000000000 
-0000000000000000 l    d  \.bss	0000000000000000 
+0000000000000000 l    d  \.text	0000000000000000 (|\.text)
+0000000000000000 l    d  \.data	0000000000000000 (|\.data)
+0000000000000000 l    d  \.bss	0000000000000000 (|\.bss)
 0000000000000000 l       \.data	0000000000000000 dsym0
 0000000000000008 l       \.data	0000000000000000 dsym1
-0000000000000000 l    d  \.toc	0000000000000000 
+0000000000000000 l    d  \.toc	0000000000000000 (|\.toc)
 0000000000000008 l       \.data	0000000000000000 usym0
 0000000000000010 l       \.data	0000000000000000 usym1
 0000000000000010 l       \.data	0000000000000000 datpt
@@ -41,13 +41,13 @@ Disassembly of section \.text:
 
 0000000000000000 <\.text>:
    0:	e8 63 00 00 	ld      r3,0\(r3\)
-			2: R_PPC64_ADDR16_LO_DS	dsym0
-   4:	e8 63 00 00 	ld      r3,0\(r3\)
-			6: R_PPC64_ADDR16_LO_DS	dsym1
-   8:	e8 63 00 00 	ld      r3,0\(r3\)
-			a: R_PPC64_ADDR16_LO_DS	usym0
-   c:	e8 63 00 00 	ld      r3,0\(r3\)
-			e: R_PPC64_ADDR16_LO_DS	usym1
+			2: R_PPC64_ADDR16_LO_DS	\.data
+   4:	e8 63 00 08 	ld      r3,8\(r3\)
+			6: R_PPC64_ADDR16_LO_DS	\.data\+0x8
+   8:	e8 63 00 08 	ld      r3,8\(r3\)
+			a: R_PPC64_ADDR16_LO_DS	\.data\+0x8
+   c:	e8 63 00 10 	ld      r3,16\(r3\)
+			e: R_PPC64_ADDR16_LO_DS	\.data\+0x10
   10:	e8 63 00 00 	ld      r3,0\(r3\)
 			12: R_PPC64_ADDR16_LO_DS	esym0
   14:	e8 63 00 00 	ld      r3,0\(r3\)
@@ -75,19 +75,19 @@ Disassembly of section \.text:
   48:	38 60 ff f8 	li      r3,-8
   4c:	38 60 00 08 	li      r3,8
   50:	38 60 00 00 	li      r3,0
-			52: R_PPC64_ADDR16_LO	dsym0
+			52: R_PPC64_ADDR16_LO	\.data
   54:	38 60 00 00 	li      r3,0
-			56: R_PPC64_ADDR16_HI	dsym0
+			56: R_PPC64_ADDR16_HI	\.data
   58:	38 60 00 00 	li      r3,0
-			5a: R_PPC64_ADDR16_HA	dsym0
+			5a: R_PPC64_ADDR16_HA	\.data
   5c:	38 60 00 00 	li      r3,0
-			5e: R_PPC64_ADDR16_HIGHER	dsym0
+			5e: R_PPC64_ADDR16_HIGHER	\.data
   60:	38 60 00 00 	li      r3,0
-			62: R_PPC64_ADDR16_HIGHERA	dsym0
+			62: R_PPC64_ADDR16_HIGHERA	\.data
   64:	38 60 00 00 	li      r3,0
-			66: R_PPC64_ADDR16_HIGHEST	dsym0
+			66: R_PPC64_ADDR16_HIGHEST	\.data
   68:	38 60 00 00 	li      r3,0
-			6a: R_PPC64_ADDR16_HIGHESTA	dsym0
+			6a: R_PPC64_ADDR16_HIGHESTA	\.data
   6c:	38 60 ff f8 	li      r3,-8
   70:	38 60 ff ff 	li      r3,-1
   74:	38 60 00 00 	li      r3,0
@@ -137,9 +137,15 @@ Disassembly of section \.toc:
 
 0000000000000000 <\.toc>:
 	\.\.\.
-			0: R_PPC64_ADDR64	dsym0
-			8: R_PPC64_ADDR64	dsym1
-			10: R_PPC64_ADDR64	usym0
-			18: R_PPC64_ADDR64	usym1
+			0: R_PPC64_ADDR64	\.data
+			8: R_PPC64_ADDR64	\.data\+0x8
+   c:	00 00 00 08 	\.long 0x8
+  10:	00 00 00 00 	\.long 0x0
+			10: R_PPC64_ADDR64	\.data\+0x8
+  14:	00 00 00 08 	\.long 0x8
+  18:	00 00 00 00 	\.long 0x0
+			18: R_PPC64_ADDR64	\.data\+0x10
+  1c:	00 00 00 10 	\.long 0x10
+	\.\.\.
 			20: R_PPC64_ADDR64	esym0
 			28: R_PPC64_ADDR64	esym1
diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
new file mode 100644
index 000000000000..0c38e419b82b
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -0,0 +1,477 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	5a 65 af ff [	 ]*a	%r6,4095\(%r5,%r10\)
+.*:	6a 65 af ff [	 ]*ad	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 1a [	 ]*adb	%f6,4095\(%r5,%r10\)
+.*:	b3 1a 00 69 [	 ]*adbr	%f6,%f9
+.*:	2a 69 [	 ]*adr	%f6,%f9
+.*:	7a 65 af ff [	 ]*ae	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 0a [	 ]*aeb	%f6,4095\(%r5,%r10\)
+.*:	b3 0a 00 69 [	 ]*aebr	%f6,%f9
+.*:	3a 69 [	 ]*aer	%f6,%f9
+.*:	4a 65 af ff [	 ]*ah	%r6,4095\(%r5,%r10\)
+.*:	a7 6a 80 01 [	 ]*ahi	%r6,-32767
+.*:	5e 65 af ff [	 ]*al	%r6,4095\(%r5,%r10\)
+.*:	1e 69 [	 ]*alr	%r6,%r9
+.*:	fa 58 5f ff af ff [	 ]*ap	4095\(6,%r5\),4095\(9,%r10\)
+.*:	1a 69 [	 ]*ar	%r6,%r9
+.*:	7e 65 af ff [	 ]*au	%f6,4095\(%r5,%r10\)
+.*:	3e 69 [	 ]*aur	%f6,%f9
+.*:	6e 65 af ff [	 ]*aw	%f6,4095\(%r5,%r10\)
+.*:	2e 69 [	 ]*awr	%f6,%f9
+.*:	b3 4a 00 69 [	 ]*axbr	%f6,%f9
+.*:	36 69 [	 ]*axr	%f6,%f9
+.*:	47 f5 af ff [	 ]*b	4095\(%r5,%r10\)
+.*:	b2 40 00 69 [	 ]*bakr	%r6,%r9
+.*:	45 65 af ff [	 ]*bal	%r6,4095\(%r5,%r10\)
+.*:	05 69 [	 ]*balr	%r6,%r9
+.*:	4d 65 af ff [	 ]*bas	%r6,4095\(%r5,%r10\)
+.*:	0d 69 [	 ]*basr	%r6,%r9
+.*:	0c 69 [	 ]*bassm	%r6,%r9
+.*:	47 65 af ff [	 ]*blh	4095\(%r5,%r10\)
+.*:	07 69 [	 ]*blhr	%r9
+.*:	46 65 af ff [	 ]*bct	%r6,4095\(%r5,%r10\)
+.*:	06 69 [	 ]*bctr	%r6,%r9
+.*:	47 85 af ff [	 ]*be	4095\(%r5,%r10\)
+.*:	07 89 [	 ]*ber	%r9
+.*:	47 25 af ff [	 ]*bh	4095\(%r5,%r10\)
+.*:	47 a5 af ff [	 ]*bhe	4095\(%r5,%r10\)
+.*:	07 a9 [	 ]*bher	%r9
+.*:	07 29 [	 ]*bhr	%r9
+.*:	47 45 af ff [	 ]*bl	4095\(%r5,%r10\)
+.*:	47 c5 af ff [	 ]*ble	4095\(%r5,%r10\)
+.*:	07 c9 [	 ]*bler	%r9
+.*:	47 65 af ff [	 ]*blh	4095\(%r5,%r10\)
+.*:	07 69 [	 ]*blhr	%r9
+.*:	07 49 [	 ]*blr	%r9
+.*:	47 45 af ff [	 ]*bl	4095\(%r5,%r10\)
+.*:	07 49 [	 ]*blr	%r9
+.*:	47 75 af ff [	 ]*bne	4095\(%r5,%r10\)
+.*:	07 79 [	 ]*bner	%r9
+.*:	47 d5 af ff [	 ]*bnh	4095\(%r5,%r10\)
+.*:	47 55 af ff [	 ]*bnhe	4095\(%r5,%r10\)
+.*:	07 59 [	 ]*bnher	%r9
+.*:	07 d9 [	 ]*bnhr	%r9
+.*:	47 b5 af ff [	 ]*bnl	4095\(%r5,%r10\)
+.*:	47 35 af ff [	 ]*bnle	4095\(%r5,%r10\)
+.*:	07 39 [	 ]*bnler	%r9
+.*:	47 95 af ff [	 ]*bnlh	4095\(%r5,%r10\)
+.*:	07 99 [	 ]*bnlhr	%r9
+.*:	07 b9 [	 ]*bnlr	%r9
+.*:	47 b5 af ff [	 ]*bnl	4095\(%r5,%r10\)
+.*:	07 b9 [	 ]*bnlr	%r9
+.*:	47 e5 af ff [	 ]*bno	4095\(%r5,%r10\)
+.*:	07 e9 [	 ]*bnor	%r9
+.*:	47 d5 af ff [	 ]*bnh	4095\(%r5,%r10\)
+.*:	07 d9 [	 ]*bnhr	%r9
+.*:	47 75 af ff [	 ]*bne	4095\(%r5,%r10\)
+.*:	07 79 [	 ]*bner	%r9
+.*:	47 15 af ff [	 ]*bo	4095\(%r5,%r10\)
+.*:	07 19 [	 ]*bor	%r9
+.*:	47 25 af ff [	 ]*bh	4095\(%r5,%r10\)
+.*:	07 29 [	 ]*bhr	%r9
+.*:	07 f9 [	 ]*br	%r9
+.*:	a7 95 00 00 [	 ]*bras	%r9,e2 <foo\+0xe2>
+.*:	a7 64 00 00 [	 ]*jlh	e6 <foo\+0xe6>
+.*:	a7 66 00 00 [	 ]*brct	%r6,ea <foo\+0xea>
+.*:	84 69 00 00 [	 ]*brxh	%r6,%r9,ee <foo\+0xee>
+.*:	85 69 00 00 [	 ]*brxle	%r6,%r9,f2 <foo\+0xf2>
+.*:	b2 5a 00 69 [	 ]*bsa	%r6,%r9
+.*:	b2 58 00 69 [	 ]*bsg	%r6,%r9
+.*:	0b 69 [	 ]*bsm	%r6,%r9
+.*:	86 69 5f ff [	 ]*bxh	%r6,%r9,4095\(%r5\)
+.*:	87 69 5f ff [	 ]*bxle	%r6,%r9,4095\(%r5\)
+.*:	47 85 af ff [	 ]*be	4095\(%r5,%r10\)
+.*:	07 89 [	 ]*ber	%r9
+.*:	59 65 af ff [	 ]*c	%r6,4095\(%r5,%r10\)
+.*:	69 65 af ff [	 ]*cd	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 19 [	 ]*cdb	%f6,4095\(%r5,%r10\)
+.*:	b3 19 00 69 [	 ]*cdbr	%f6,%f9
+.*:	b3 95 00 69 [	 ]*cdfbr	%r6,%f9
+.*:	b3 b5 00 69 [	 ]*cdfr	%r6,%f9
+.*:	29 69 [	 ]*cdr	%f6,%f9
+.*:	bb 69 5f ff [	 ]*cds	%r6,%r9,4095\(%r5\)
+.*:	79 65 af ff [	 ]*ce	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 09 [	 ]*ceb	%f6,4095\(%r5,%r10\)
+.*:	b3 09 00 69 [	 ]*cebr	%f6,%f9
+.*:	b3 94 00 69 [	 ]*cefbr	%r6,%f9
+.*:	b3 b4 00 69 [	 ]*cefr	%r6,%f9
+.*:	39 69 [	 ]*cer	%f6,%f9
+.*:	b2 1a 5f ff [	 ]*cfc	4095\(%r5\)
+.*:	b3 99 50 69 [	 ]*cfdbr	%f6,5,%r9
+.*:	b3 98 50 69 [	 ]*cfebr	%f6,5,%r9
+.*:	b3 9a 50 69 [	 ]*cfxbr	%f6,5,%r9
+.*:	49 65 af ff [	 ]*ch	%r6,4095\(%r5,%r10\)
+.*:	a7 6e 80 01 [	 ]*chi	%r6,-32767
+.*:	b2 41 00 69 [	 ]*cksm	%r6,%r9
+.*:	55 65 af ff [	 ]*cl	%r6,4095\(%r5,%r10\)
+.*:	d5 ff 5f ff af ff [	 ]*clc	4095\(256,%r5\),4095\(%r10\)
+.*:	0f 69 [	 ]*clcl	%r6,%r9
+.*:	a9 69 5f ff [	 ]*clcle	%r6,%r9,4095\(%r5\)
+.*:	95 ff 5f ff [	 ]*cli	4095\(%r5\),255
+.*:	bd 6a 5f ff [	 ]*clm	%r6,10,4095\(%r5\)
+.*:	15 69 [	 ]*clr	%r6,%r9
+.*:	b2 5d 00 69 [	 ]*clst	%r6,%r9
+.*:	b2 63 00 69 [	 ]*cmpsc	%r6,%r9
+.*:	f9 58 5f ff af ff [	 ]*cp	4095\(6,%r5\),4095\(9,%r10\)
+.*:	b2 4d 00 69 [	 ]*cpya	%a6,%a9
+.*:	19 69 [	 ]*cr	%r6,%r9
+.*:	ba 69 5f ff [	 ]*cs	%r6,%r9,4095\(%r5\)
+.*:	b2 30 00 00 [	 ]*csch
+.*:	b2 50 00 69 [	 ]*csp	%r6,%r9
+.*:	b2 57 00 69 [	 ]*cuse	%r6,%r9
+.*:	b2 a7 00 69 [	 ]*cutfu	%r6,%r9
+.*:	b2 a6 00 69 [	 ]*cuutf	%r6,%r9
+.*:	4f 65 af ff [	 ]*cvb	%r6,4095\(%r5,%r10\)
+.*:	4e 65 af ff [	 ]*cvd	%r6,4095\(%r5,%r10\)
+.*:	b3 49 00 69 [	 ]*cxbr	%f6,%f9
+.*:	b3 96 00 69 [	 ]*cxfbr	%r6,%f9
+.*:	b3 b6 00 69 [	 ]*cxfr	%r6,%f9
+.*:	b3 69 00 69 [	 ]*cxr	%f6,%f9
+.*:	5d 65 af ff [	 ]*d	%r6,4095\(%r5,%r10\)
+.*:	6d 65 af ff [	 ]*dd	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 1d [	 ]*ddb	%f6,4095\(%r5,%r10\)
+.*:	b3 1d 00 69 [	 ]*ddbr	%f6,%f9
+.*:	2d 69 [	 ]*ddr	%f6,%f9
+.*:	7d 65 af ff [	 ]*de	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 0d [	 ]*deb	%f6,4095\(%r5,%r10\)
+.*:	b3 0d 00 69 [	 ]*debr	%f6,%f9
+.*:	3d 69 [	 ]*der	%f6,%f9
+.*:	83 69 5f ff [	 ]*diag	%r6,%r9,4095\(%r5\)
+.*:	b3 5b 9a 65 [	 ]*didbr	%f6,%f9,%f5,10
+.*:	b3 53 9a 65 [	 ]*diebr	%f6,%f9,%f5,10
+.*:	fd 58 5f ff af ff [	 ]*dp	4095\(6,%r5\),4095\(9,%r10\)
+.*:	1d 69 [	 ]*dr	%r6,%r9
+.*:	b3 4d 00 69 [	 ]*dxbr	%f6,%f9
+.*:	b2 2d 00 60 [	 ]*dxr	%f6
+.*:	b2 4f 00 69 [	 ]*ear	%r6,%a9
+.*:	de ff 5f ff af ff [	 ]*ed	4095\(256,%r5\),4095\(%r10\)
+.*:	df ff 5f ff af ff [	 ]*edmk	4095\(256,%r5\),4095\(%r10\)
+.*:	b3 8c 00 69 [	 ]*efpc	%r6,%r9
+.*:	b2 26 00 60 [	 ]*epar	%r6
+.*:	b2 49 00 69 [	 ]*ereg	%r6,%r9
+.*:	b2 27 00 60 [	 ]*esar	%r6
+.*:	b2 4a 00 69 [	 ]*esta	%r6,%r9
+.*:	44 65 af ff [	 ]*ex	%r6,4095\(%r5,%r10\)
+.*:	b3 5f 50 69 [	 ]*fidbr	%f6,5,%f9
+.*:	b3 7f 50 69 [	 ]*fidr	%f6,5,%f9
+.*:	b3 57 50 69 [	 ]*fiebr	%f6,5,%f9
+.*:	b3 77 50 69 [	 ]*fier	%f6,5,%f9
+.*:	b3 47 50 69 [	 ]*fixbr	%f6,5,%f9
+.*:	b3 67 50 69 [	 ]*fixr	%f6,5,%f9
+.*:	24 69 [	 ]*hdr	%f6,%f9
+.*:	34 69 [	 ]*her	%f6,%f9
+.*:	b2 31 00 00 [	 ]*hsch
+.*:	b2 24 00 60 [	 ]*iac	%r6
+.*:	43 65 af ff [	 ]*ic	%r6,4095\(%r5,%r10\)
+.*:	bf 6a 5f ff [	 ]*icm	%r6,10,4095\(%r5\)
+.*:	b2 0b 00 00 [	 ]*ipk
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+.*:	b2 23 00 69 [	 ]*ivsk	%r6,%r9
+.*:	a7 f4 00 00 [	 ]*j	268 <foo\+0x268>
+.*:	a7 84 00 00 [	 ]*je	26c <foo\+0x26c>
+.*:	a7 24 00 00 [	 ]*jh	270 <foo\+0x270>
+.*:	a7 a4 00 00 [	 ]*jhe	274 <foo\+0x274>
+.*:	a7 44 00 00 [	 ]*jl	278 <foo\+0x278>
+.*:	a7 c4 00 00 [	 ]*jle	27c <foo\+0x27c>
+.*:	a7 64 00 00 [	 ]*jlh	280 <foo\+0x280>
+.*:	a7 44 00 00 [	 ]*jl	284 <foo\+0x284>
+.*:	a7 74 00 00 [	 ]*jne	288 <foo\+0x288>
+.*:	a7 d4 00 00 [	 ]*jnh	28c <foo\+0x28c>
+.*:	a7 54 00 00 [	 ]*jnhe	290 <foo\+0x290>
+.*:	a7 b4 00 00 [	 ]*jnl	294 <foo\+0x294>
+.*:	a7 34 00 00 [	 ]*jnle	298 <foo\+0x298>
+.*:	a7 94 00 00 [	 ]*jnlh	29c <foo\+0x29c>
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+.*:	a7 e4 00 00 [	 ]*jno	2a4 <foo\+0x2a4>
+.*:	a7 d4 00 00 [	 ]*jnh	2a8 <foo\+0x2a8>
+.*:	a7 74 00 00 [	 ]*jne	2ac <foo\+0x2ac>
+.*:	a7 14 00 00 [	 ]*jo	2b0 <foo\+0x2b0>
+.*:	a7 24 00 00 [	 ]*jh	2b4 <foo\+0x2b4>
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+.*:	ed 65 af ff 00 18 [	 ]*kdb	%f6,4095\(%r5,%r10\)
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+.*:	68 65 af ff [	 ]*ld	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 24 [	 ]*lde	%f6,4095\(%r5,%r10\)
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+.*:	b3 04 00 69 [	 ]*ldebr	%f6,%f9
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+.*:	78 65 af ff [	 ]*le	%f6,4095\(%r5,%r10\)
+.*:	b3 44 00 69 [	 ]*ledbr	%f6,%f9
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+.*:	21 69 [	 ]*lndr	%f6,%f9
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+.*:	31 69 [	 ]*lner	%f6,%f9
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+.*:	20 69 [	 ]*lpdr	%f6,%f9
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+.*:	30 69 [	 ]*lper	%f6,%f9
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+.*:	25 69 [	 ]*lrdr	%f6,%f9
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+.*:	22 69 [	 ]*ltdr	%f6,%f9
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+.*:	32 69 [	 ]*lter	%f6,%f9
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+.*:	b2 4b 00 69 [	 ]*lura	%r6,%r9
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+.*:	b3 75 00 60 [	 ]*lzdr	%r6
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+.*:	b3 1e 60 95 [	 ]*madbr	%f6,%f9,%f5
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+.*:	b3 0e 60 95 [	 ]*maebr	%f6,%f9,%f5
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+.*:	6c 65 af ff [	 ]*md	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 1c [	 ]*mdb	%f6,4095\(%r5,%r10\)
+.*:	b3 1c 00 69 [	 ]*mdbr	%f6,%f9
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+.*:	e8 ff 5f ff af ff [	 ]*mvcin	4095\(256,%r5\),4095\(%r10\)
+.*:	d9 69 5f ff af ff [	 ]*mvck	4095\(%r6,%r5\),4095\(%r10\),%r9
+.*:	0e 69 [	 ]*mvcl	%r6,%r9
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+.*:	eb 69 5f ff 00 8e [	 ]*mvclu	%r6,%r9,4095\(%r5\)
+.*:	da 69 5f ff af ff [	 ]*mvcp	4095\(%r6,%r5\),4095\(%r10\),%r9
+.*:	db 69 5f ff af ff [	 ]*mvcs	4095\(%r6,%r5\),4095\(%r10\),%r9
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+.*:	f1 58 5f ff af ff [	 ]*mvo	4095\(6,%r5\),4095\(9,%r10\)
+.*:	b2 54 00 69 [	 ]*mvpg	%r6,%r9
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+.*:	d3 ff 5f ff af ff [	 ]*mvz	4095\(256,%r5\),4095\(%r10\)
+.*:	b3 4c 00 69 [	 ]*mxbr	%f6,%f9
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+.*:	ed 65 af ff 00 07 [	 ]*mxdb	%f6,4095\(%r5,%r10\)
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+.*:	d4 ff 5f ff af ff [	 ]*nc	4095\(256,%r5\),4095\(%r10\)
+.*:	94 ff 5f ff [	 ]*ni	4095\(%r5\),255
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+.*:	d6 ff 5f ff af ff [	 ]*oc	4095\(256,%r5\),4095\(%r10\)
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+.*:	f2 58 5f ff af ff [	 ]*pack	4095\(6,%r5\),4095\(9,%r10\)
+.*:	b2 48 00 00 [	 ]*palb
+.*:	b2 18 5f ff [	 ]*pc	4095\(%r5\)
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+.*:	b2 3b 00 00 [	 ]*rchp
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+.*:	b2 38 00 00 [	 ]*rsch
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+.*:	b2 19 5f ff [	 ]*sac	4095\(%r5\)
+.*:	b2 79 5f ff [	 ]*sacf	4095\(%r5\)
+.*:	b2 37 00 00 [	 ]*sal
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+.*:	b2 45 00 60 [	 ]*sqer	%f6
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+.*:	b3 36 00 69 [	 ]*sqxr	%f6,%f9
+.*:	1b 69 [	 ]*sr	%r6,%r9
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+.*:	b2 5e 00 69 [	 ]*srst	%r6,%r9
+.*:	b2 25 00 60 [	 ]*ssar	%r6
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+.*:	70 65 af ff [	 ]*ste	%f6,4095\(%r5,%r10\)
+.*:	b2 9c 5f ff [	 ]*stfpc	4095\(%r5\)
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+.*:	b2 02 5f ff [	 ]*stidp	4095\(%r5\)
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+.*:	b2 46 00 69 [	 ]*stura	%r6,%r9
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+.*:	3f 69 [	 ]*sur	%f6,%f9
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+.*:	2f 69 [	 ]*swr	%f6,%f9
+.*:	b3 4b 00 69 [	 ]*sxbr	%f6,%f9
+.*:	37 69 [	 ]*sxr	%f6,%f9
+.*:	b2 4c 00 69 [	 ]*tar	%a6,%r9
+.*:	b2 2c 00 06 [	 ]*tb	%r6
+.*:	b3 51 50 69 [	 ]*tbdr	%f6,5,%f9
+.*:	b3 50 50 69 [	 ]*tbedr	%f6,5,%f9
+.*:	ed 65 af ff 00 11 [	 ]*tcdb	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 10 [	 ]*tceb	%f6,4095\(%r5,%r10\)
+.*:	ed 65 af ff 00 12 [	 ]*tcxb	%f6,4095\(%r5,%r10\)
+.*:	b3 58 00 69 [	 ]*thder	%r6,%r9
+.*:	b3 59 00 69 [	 ]*thdr	%r6,%r9
+.*:	91 ff 5f ff [	 ]*tm	4095\(%r5\),255
+.*:	a7 60 ff ff [	 ]*tmh	%r6,65535
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+.*:	a7 60 ff ff [	 ]*tmh	%r6,65535
+.*:	a7 61 ff ff [	 ]*tml	%r6,65535
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+.*:	b2 36 5f ff [	 ]*tpi	4095\(%r5\)
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+.*:	dc ff 5f ff af ff [	 ]*tr	4095\(256,%r5\),4095\(%r10\)
+.*:	99 69 5f ff [	 ]*trace	%r6,%r9,4095\(%r5\)
+.*:	01 ff [	 ]*trap2
+.*:	b2 ff 5f ff [	 ]*trap4	4095\(%r5\)
+.*:	b2 a5 00 69 [	 ]*tre	%r6,%r9
+.*:	b9 93 00 69 [	 ]*troo	%r6,%r9,0
+.*:	b9 92 00 69 [	 ]*trot	%r6,%r9,0
+.*:	dd ff 5f ff af ff [	 ]*trt	4095\(256,%r5\),4095\(%r10\)
+.*:	b9 91 00 69 [	 ]*trto	%r6,%r9,0
+.*:	b9 90 00 69 [	 ]*trtt	%r6,%r9,0
+.*:	93 00 5f ff [	 ]*ts	4095\(%r5\)
+.*:	b2 35 5f ff [	 ]*tsch	4095\(%r5\)
+.*:	f3 58 5f ff af ff [	 ]*unpk	4095\(6,%r5\),4095\(9,%r10\)
+.*:	ea ff 5f ff af ff [	 ]*unpka	4095\(256,%r5\),4095\(%r10\)
+.*:	e2 ff 5f ff af ff [	 ]*unpku	4095\(256,%r5\),4095\(%r10\)
+.*:	01 02 [	 ]*upt
+.*:	57 65 af ff [	 ]*x	%r6,4095\(%r5,%r10\)
+.*:	d7 ff 5f ff af ff [	 ]*xc	4095\(256,%r5\),4095\(%r10\)
+.*:	97 ff 5f ff [	 ]*xi	4095\(%r5\),255
+.*:	17 69 [	 ]*xr	%r6,%r9
+.*:	b2 76 00 00 [	 ]*xsch
+.*:	f8 58 5f ff af ff [	 ]*zap	4095\(6,%r5\),4095\(9,%r10\)
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
new file mode 100644
index 000000000000..314cbbb09640
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -0,0 +1,471 @@
+.text
+foo:
+	a	%r6,4095(%r5,%r10)
+	ad	%f6,4095(%r5,%r10)
+	adb	%f6,4095(%r5,%r10)
+	adbr	%f6,%f9
+	adr	%f6,%f9
+	ae	%f6,4095(%r5,%r10)
+	aeb	%f6,4095(%r5,%r10)
+	aebr	%f6,%f9
+	aer	%f6,%f9
+	ah	%r6,4095(%r5,%r10)
+	ahi	%r6,-32767
+	al	%r6,4095(%r5,%r10)
+	alr	%r6,%r9
+	ap	4095(6,%r5),4095(9,%r10)
+	ar	%r6,%r9
+	au	%f6,4095(%r5,%r10)
+	aur	%f6,%f9
+	aw	%f6,4095(%r5,%r10)
+	awr	%f6,%f9
+	axbr	%f6,%f9
+	axr	%f6,%f9
+	b	4095(%r5,%r10)
+	bakr	%r6,%r9
+	bal	%r6,4095(%r5,%r10)
+	balr	%r6,%r9
+	bas	%r6,4095(%r5,%r10)
+	basr	%r6,%r9
+	bassm	%r6,%r9
+	bc	6,4095(%r5,%r10)
+	bcr	6,%r9
+	bct	%r6,4095(%r5,%r10)
+	bctr	%r6,%r9
+	be	4095(%r5,%r10)
+	ber	%r9
+	bh	4095(%r5,%r10)
+	bhe	4095(%r5,%r10)
+	bher	%r9
+	bhr	%r9
+	bl	4095(%r5,%r10)
+	ble	4095(%r5,%r10)
+	bler	%r9
+	blh	4095(%r5,%r10)
+	blhr	%r9
+	blr	%r9
+	bm	4095(%r5,%r10)
+	bmr	%r9
+	bne	4095(%r5,%r10)
+	bner	%r9
+	bnh	4095(%r5,%r10)
+	bnhe	4095(%r5,%r10)
+	bnher	%r9
+	bnhr	%r9
+	bnl	4095(%r5,%r10)
+	bnle	4095(%r5,%r10)
+	bnler	%r9
+	bnlh	4095(%r5,%r10)
+	bnlhr	%r9
+	bnlr	%r9
+	bnm	4095(%r5,%r10)
+	bnmr	%r9
+	bno	4095(%r5,%r10)
+	bnor	%r9
+	bnp	4095(%r5,%r10)
+	bnpr	%r9
+	bnz	4095(%r5,%r10)
+	bnzr	%r9
+	bo	4095(%r5,%r10)
+	bor	%r9
+	bp	4095(%r5,%r10)
+	bpr	%r9
+	br	%r9
+	bras	%r9,.
+	brc	6,.
+	brct	6,.
+	brxh	%r6,%r9,.
+	brxle	%r6,%r9,.
+	bsa	%r6,%r9
+	bsg	%r6,%r9
+	bsm	%r6,%r9
+	bxh	%r6,%r9,4095(%r5)
+	bxle	%r6,%r9,4095(%r5)
+	bz	4095(%r5,%r10)
+	bzr	%r9
+	c	%r6,4095(%r5,%r10)
+	cd	%f6,4095(%r5,%r10)
+	cdb	%f6,4095(%r5,%r10)
+	cdbr	%f6,%f9
+	cdfbr	%r6,%f9
+	cdfr	%r6,%f9
+	cdr	%f6,%f9
+	cds	%r6,%r9,4095(%r5)
+	ce	%f6,4095(%r5,%r10)
+	ceb	%f6,4095(%r5,%r10)
+	cebr	%f6,%f9
+	cefbr	%r6,%f9
+	cefr	%r6,%f9
+	cer	%f6,%f9
+	cfc	4095(%r5)
+	cfdbr	%r6,5,%r9
+	cfebr	%r6,5,%r9
+	cfxbr	%r6,5,%r9
+	ch	%r6,4095(%r5,%r10)
+	chi	%r6,-32767
+	cksm	%r6,%r9
+	cl	%r6,4095(%r5,%r10)
+	clc	4095(256,%r5),4095(%r10)
+	clcl	%r6,%r9
+	clcle	%r6,%r9,4095(%r5)
+	cli	4095(%r5),255
+	clm	%r6,10,4095(%r5)
+	clr	%r6,%r9
+	clst	%r6,%r9
+	cmpsc	%r6,%r9
+	cp	4095(6,%r5),4095(9,%r10)
+	cpya	%a6,%a9
+	cr	%r6,%r9
+	cs	%r6,%r9,4095(%r5)
+	csch
+	csp	%r6,%r9
+	cuse	%r6,%r9
+	cutfu	%r6,%r9
+	cuutf	%r6,%r9
+	cvb	%r6,4095(%r5,%r10)
+	cvd	%r6,4095(%r5,%r10)
+	cxbr	%f6,%f9
+	cxfbr	%r6,%f9
+	cxfr	%r6,%f9
+	cxr	%f6,%f9
+	d	%r6,4095(%r5,%r10)
+	dd	%f6,4095(%r5,%r10)
+	ddb	%f6,4095(%r5,%r10)
+	ddbr	%f6,%f9
+	ddr	%f6,%f9
+	de	%f6,4095(%r5,%r10)
+	deb	%f6,4095(%r5,%r10)
+	debr	%f6,%f9
+	der	%f6,%f9
+	diag	%r6,%r9,4095(%r5)
+	didbr	%f6,%r9,%r5,10
+	diebr	%f6,%r9,%r5,10
+	dp	4095(6,%r5),4095(9,%r10)
+	dr	%r6,%r9
+	dxbr	%f6,%f9
+	dxr	%f6
+	ear	%r6,%a9
+	ed	4095(256,%r5),4095(%r10)
+	edmk	4095(256,%r5),4095(%r10)
+	efpc	%r6,%r9
+	epar	%r6
+	ereg	%r6,%r9
+	esar	%r6
+	esta	%r6,%r9
+	ex	%r6,4095(%r5,%r10)
+	fidbr	%f6,5,%f9
+	fidr	%f6,5,%f9
+	fiebr	%f6,5,%f9
+	fier	%f6,5,%f9
+	fixbr	%f6,5,%f9
+	fixr	%f6,5,%f9
+	hdr	%f6,%f9
+	her	%f6,%f9
+	hsch	
+	iac	%r6
+	ic	%r6,4095(%r5,%r10)
+	icm	%r6,10,4095(%r5)
+	ipk	
+	ipm	%r6
+	ipte	%r6,%r9
+	iske	%r6,%r9
+	ivsk	%r6,%r9
+	j	.
+	je	.
+	jh	.
+	jhe	.
+	jl	.
+	jle	.
+	jlh	.
+	jm	.
+	jne	.
+	jnh	.
+	jnhe	.
+	jnl	.
+	jnle	.
+	jnlh	.
+	jnm	.
+	jno	.
+	jnp	.
+	jnz	.
+	jo	.
+	jp	.
+	jz	.
+	kdb	%f6,4095(%r5,%r10)
+	kdbr	%f6,%f9
+	keb	%f6,4095(%r5,%r10)
+	kebr	%f6,%f9
+	kxbr	%f6,%f9
+	l	%r6,4095(%r5,%r10)
+	la	%r6,4095(%r5,%r10)
+	lae	%r6,4095(%r5,%r10)
+	lam	%a6,%a9,4095(%r5)
+	lasp	4095(%r5),4095(%r10)
+	lcdbr	%f6,%f9
+	lcdr	%f6,%f9
+	lcebr	%f6,%f9
+	lcer	%f6,%f9
+	lcr	%r6,%r9
+	lctl	%c6,%c9,4095(%r5)
+	lcxbr	%f6,%f9
+	lcxr	%f6,%f9
+	ld	%f6,4095(%r5,%r10)
+	lde	%f6,4095(%r5,%r10)
+	ldeb	%f6,4095(%r5,%r10)
+	ldebr	%f6,%f9
+	lder	%f6,%f9
+	ldr	%f6,%f9
+	ldxbr	%f6,%f9
+	ldxr	%f6,%f9
+	le	%f6,4095(%r5,%r10)
+	ledbr	%f6,%f9
+	ledr	%f6,%f9
+	ler	%f6,%f9
+	lexbr	%f6,%f9
+	lexr	%f6,%f9
+	lfpc	4095(%r5)
+	lh	%r6,4095(%r5,%r10)
+	lhi	%r6,-32767
+	lm	%r6,%r9,4095(%r5)
+	lndbr	%f6,%f9
+	lndr	%f6,%f9
+	lnebr	%f6,%f9
+	lner	%f6,%f9
+	lnr	%r6,%r9
+	lnxbr	%f6,%f9
+	lnxr	%f6,%f9
+	lpdbr	%f6,%f9
+	lpdr	%f6,%f9
+	lpebr	%f6,%f9
+	lper	%f6,%f9
+	lpr	%r6,%r9
+	lpsw	4095(%r5)
+	lpxbr	%f6,%f9
+	lpxr	%f6,%f9
+	lr	%r6,%r9
+	lra	%r6,4095(%r5,%r10)
+	lrdr	%f6,%f9
+	lrer	%f6,%f9
+	ltdbr	%f6,%f9
+	ltdr	%f6,%f9
+	ltebr	%f6,%f9
+	lter	%f6,%f9
+	ltr	%r6,%r9
+	ltxbr	%f6,%f9
+	ltxr	%f6,%f9
+	lura	%r6,%r9
+	lxd	%f6,4095(%r5,%r10)
+	lxdb	%f6,4095(%r5,%r10)
+	lxdbr	%f6,%f9
+	lxdr	%f6,%f9
+	lxe	%f6,4095(%r5,%r10)
+	lxeb	%f6,4095(%r5,%r10)
+	lxebr	%f6,%f9
+	lxer	%f6,%f9
+	lxr	%r6,%r9
+	lzdr	%r6
+	lzer	%r6
+	lzxr	%r6
+	m	%r6,4095(%r5,%r10)
+	madb	%f6,%f9,4095(%r5,%r10)
+	madbr	%f6,%f9,%f5
+	maeb	%f6,%f9,4095(%r5,%r10)
+	maebr	%f6,%f9,%f5
+	mc	4095(%r5),255
+	md	%f6,4095(%r5,%r10)
+	mdb	%f6,4095(%r5,%r10)
+	mdbr	%f6,%f9
+	mde	%f6,4095(%r5,%r10)
+	mdeb	%f6,4095(%r5,%r10)
+	mdebr	%f6,%f9
+	mder	%f6,%f9
+	mdr	%f6,%f9
+	me	%f6,4095(%r5,%r10)
+	mee	%f6,4095(%r5,%r10)
+	meeb	%f6,4095(%r5,%r10)
+	meebr	%f6,%f9
+	meer	%f6,%f9
+	mer	%f6,%f9
+	mh	%r6,4095(%r5,%r10)
+	mhi	%r6,-32767
+	mp	4095(6,%r5),4095(9,%r10)
+	mr	%r6,%r9
+	ms	%r6,4095(%r5,%r10)
+	msch	4095(%r5)
+	msdb	%f6,%f9,4095(%r5,%r10)
+	msdbr	%f6,%f9,%f5
+	mseb	%f6,%f9,4095(%r5,%r10)
+	msebr	%f6,%f9,%f5
+	msr	%r6,%r9
+	msta	%r6
+	mvc	4095(256,%r5),4095(%r10)
+	mvcdk	4095(%r5),4095(%r10)
+	mvcin	4095(256,%r5),4095(%r10)
+	mvck	4095(%r6,%r5),4095(%r10),%r9
+	mvcl	%r6,%r9
+	mvcle	%r6,%r9,4095(%r5)
+	mvclu	%r6,%r9,4095(%r5)
+	mvcp	4095(%r6,%r5),4095(%r10),%r9
+	mvcs	4095(%r6,%r5),4095(%r10),%r9
+	mvcsk	4095(%r5),4095(%r10)
+	mvi	4095(%r5),255
+	mvn	4095(256,%r5),4095(%r10)
+	mvo	4095(6,%r5),4095(9,%r10)
+	mvpg	%r6,%r9
+	mvst	%r6,%r9
+	mvz	4095(256,%r5),4095(%r10)
+	mxbr	%f6,%f9
+	mxd	%f6,4095(%r5,%r10)
+	mxdb	%f6,4095(%r5,%r10)
+	mxdbr	%f6,%f9
+	mxdr	%f6,%f9
+	mxr	%f6,%f9
+	n	%r6,4095(%r5,%r10)
+	nc	4095(256,%r5),4095(%r10)
+	ni	4095(%r5),255
+	nop	4095(%r5,%r10)
+	nopr	%r9
+	nr	%r6,%r9
+	o	%r6,4095(%r5,%r10)
+	oc	4095(256,%r5),4095(%r10)
+	oi	4095(%r5),255
+	or	%r6,%r9
+	pack	4095(6,%r5),4095(9,%r10)
+	palb
+	pc	4095(%r5)
+	pgin	%r6,%r9
+	pgout	%r6,%r9
+	pka	4095(256,%r5),4095(%r10)
+	pku	4095(256,%r5),4095(%r10)
+	plo	%r6,4095(%r5),%r9,4095(%r10)
+	pr
+	pt	%r6,%r9
+	ptlb	
+	rchp	
+	rp	4095(%r5)
+	rrbe	%r6,%r9
+	rsch	
+	s	%r6,4095(%r5,%r10)
+	sac	4095(%r5)
+	sacf	4095(%r5)
+	sal	
+	sar	%a6,%r9
+	schm	
+	sck	4095(%r5)
+	sckc	4095(%r5)
+	sckpf
+	sd	%f6,4095(%r5,%r10)
+	sdb	%f6,4095(%r5,%r10)
+	sdbr	%f6,%f9
+	sdr	%f6,%f9
+	se	%f6,4095(%r5,%r10)
+	seb	%f6,4095(%r5,%r10)
+	sebr	%f6,%f9
+	ser	%f6,%f9
+	sfpc	%r6,%r9
+	sh	%r6,4095(%r5,%r10)
+	sie	4095(%r5)
+	siga	4095(%r5)
+	sigp	%r6,%r9,4095(%r5)
+	sl	%r6,4095(%r5,%r10)
+	sla	%r6,4095(%r5)
+	slda	%r6,4095(%r5)
+	sldl	%r6,4095(%r5)
+	sll	%r6,4095(%r5)
+	slr	%r6,%r9
+	sp	4095(6,%r5),4095(9,%r10)
+	spka	4095(%r5)
+	spm	%r6
+	spt	4095(%r5)
+	spx	4095(%r5)
+	sqdb	%f6,4095(%r5,%r10)
+	sqdbr	%f6,%f9
+	sqdr	%f6
+	sqe	%f6,4095(%r5,%r10)
+	sqeb	%f6,4095(%r5,%r10)
+	sqebr	%f6,%f9
+	sqer	%f6
+	sqxbr	%f6,%f9
+	sqxr	%f6,%f9
+	sr	%r6,%r9
+	sra	%r6,4095(%r5)
+	srda	%r6,4095(%r5)
+	srdl	%r6,4095(%r5)
+	srl	%r6,4095(%r5)
+	srnm	4095(%r5)
+	srp	4095(16,%r5),4095(%r10),10
+	srst	%r6,%r9
+	ssar	%r6
+	ssch	4095(%r5)
+	sske	%r6,%r9
+	ssm	4095(%r5)
+	st	%r6,4095(%r5,%r10)
+	stam	%a6,%a9,4095(%r5)
+	stap	4095(%r5)
+	stc	%r6,4095(%r5,%r10)
+	stck	4095(%r5)
+	stckc	4095(%r5)
+	stcke	4095(%r5)
+	stcm	%r6,10,4095(%r5)
+	stcps	4095(%r5)
+	stcrw	4095(%r5)
+	stctl	%c6,%c9,4095(%r5)
+	std	%f6,4095(%r5,%r10)
+	ste	%f6,4095(%r5,%r10)
+	stfpc	4095(%r5)
+	sth	%r6,4095(%r5,%r10)
+	stidp	4095(%r5)
+	stm	%r6,%r9,4095(%r5)
+	stnsm	4095(%r5),255
+	stosm	4095(%r5),255
+	stpt	4095(%r5)
+	stpx	4095(%r5)
+	stsch	4095(%r5)
+	stsi	4095(%r5)
+	stura	%r6,%r9
+	su	%f6,4095(%r5,%r10)
+	sur	%f6,%f9
+	svc	255
+	sw	%f6,4095(%r5,%r10)
+	swr	%f6,%f9
+	sxbr	%f6,%f9
+	sxr	%f6,%f9
+	tar	%a6,%r9
+	tb	%r6
+	tbdr	%r6,5,%r9
+	tbedr	%r6,5,%r9
+	tcdb	%f6,4095(%r5,%r10)
+	tceb	%f6,4095(%r5,%r10)
+	tcxb	%f6,4095(%r5,%r10)
+	thder	%r6,%r9
+	thdr	%r6,%r9
+	tm	4095(%r5),255
+	tmh	%r6,65535
+	tml	%r6,65535
+	tmlh	%r6,65535
+	tmll	%r6,65535
+	tp	%r6,4095(%r5)
+	tpi	4095(%r5)
+	tprot	4095(%r5),4095(%r10)
+	tr	4095(256,%r5),4095(%r10)
+	trace	%r6,%r9,4095(%r5)
+	trap2
+	trap4	4095(%r5)
+	tre	%r6,%r9
+	troo	%r6,%r9
+	trot	%r6,%r9
+	trt	4095(256,%r5),4095(%r10)
+	trto	%r6,%r9
+	trtt	%r6,%r9
+	ts	4095(%r5)
+	tsch	4095(%r5)
+	unpk	4095(6,%r5),4095(9,%r10)
+	unpka	4095(256,%r5),4095(%r10)
+	unpku	4095(256,%r5),4095(%r10)
+	upt
+	x	%r6,4095(%r5,%r10)
+	xc	4095(256,%r5),4095(%r10)
+	xi	4095(%r5),255
+	xr	%r6,%r9
+	xsch
+	zap	4095(6,%r5),4095(9,%r10)
diff --git a/gas/testsuite/gas/s390/esa-operands.d b/gas/testsuite/gas/s390/esa-operands.d
new file mode 100644
index 000000000000..d1744086ba26
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-operands.d
@@ -0,0 +1,23 @@
+#name: s390 operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+   0:	01 01 [ 	]*pr
+   2:	a7 1a 80 01 [ 	]*ahi	%r1,-32767
+   6:	18 12 [ 	]*lr	%r1,%r2
+   8:	b2 5e 00 12 [ 	]*srst	%r1,%r2
+   c:	b3 5b 93 12 [ 	]*didbr	%f1,%f9,%f2,3
+  10:	ba 12 40 03 [ 	]*cs	%r1,%r2,3\(%r4\)
+  14:	84 12 00 00 [ 	]*brxh	%r1,%r2,14 <foo\+0x14>
+[ 	]*16: R_390_PC16DBL	test_rsi\+0x2
+  18:	58 13 40 02 [ 	]*l	%r1,2\(%r3,%r4\)
+  1c:	ed 10 30 02 00 1a [ 	]*adb	%f1,2\(%r3\)
+  22:	ed 24 50 03 10 1e [ 	]*madb	%f1,%f2,3\(%r4,%r5\)
+  28:	b2 33 20 01 [ 	]*ssch	1\(%r2\)
+  2c:	92 03 20 01 [ 	]*mvi	1\(%r2\),3
+  30:	d2 26 30 01 50 04 [ 	]*mvc	1\(39,%r3\),4\(%r5\)
+  36:	e5 01 20 01 40 03 [ 	]*tprot	1\(%r2\),3\(%r4\)
diff --git a/gas/testsuite/gas/s390/esa-operands.s b/gas/testsuite/gas/s390/esa-operands.s
new file mode 100644
index 000000000000..9f030e835f75
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-operands.s
@@ -0,0 +1,16 @@
+.text
+foo:
+	.insn e,0x0101
+	.insn ri,0xa70a0000,%r1,-32767
+	.insn rr,0x1800,%r1,%r2
+	.insn rre,0xb25e0000,%r1,%r2
+	.insn rrf,0xb35b0000,%f1,%f2,9,%f3
+	.insn rs,0xba000000,%r1,%r2,3(%r4)
+	.insn rsi,0x84000000,%r1,%r2,test_rsi
+	.insn rx,0x58000000,%r1,2(%r3,%r4)
+	.insn rxe,0xed000000001a,%f1,2(%r3)
+	.insn rxf,0xed000000001e,%f1,%f2,3(%r4,%r5)
+	.insn s,0xb2330000,1(%r2)
+	.insn si,0x92000000,1(%r2),3
+	.insn ss,0xd20000000000,1(2,%r3),4(%r5),6
+	.insn sse,0xe50100000000,1(%r2),3(%r4)
diff --git a/gas/testsuite/gas/s390/reloc.d b/gas/testsuite/gas/s390/esa-reloc.d
index 7b75989ae278..7b75989ae278 100644
--- a/gas/testsuite/gas/s390/reloc.d
+++ b/gas/testsuite/gas/s390/esa-reloc.d
diff --git a/gas/testsuite/gas/s390/reloc.s b/gas/testsuite/gas/s390/esa-reloc.s
index 48ba28f75ca8..48ba28f75ca8 100644
--- a/gas/testsuite/gas/s390/reloc.s
+++ b/gas/testsuite/gas/s390/esa-reloc.s
diff --git a/gas/testsuite/gas/s390/esa-z9-109.d b/gas/testsuite/gas/s390/esa-z9-109.d
new file mode 100644
index 000000000000..d2935f318303
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z9-109.d
@@ -0,0 +1,12 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	b9 93 f0 69 [	 ]*troo	%r6,%r9,15
+.*:	b9 92 f0 69 [	 ]*trot	%r6,%r9,15
+.*:	b9 91 f0 69 [	 ]*trto	%r6,%r9,15
+.*:	b9 90 f0 69 [	 ]*trtt	%r6,%r9,15
diff --git a/gas/testsuite/gas/s390/esa-z9-109.s b/gas/testsuite/gas/s390/esa-z9-109.s
new file mode 100644
index 000000000000..6f4b32eba274
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z9-109.s
@@ -0,0 +1,6 @@
+.text
+foo:
+	troo	%r6,%r9,15
+	trot	%r6,%r9,15
+	trto	%r6,%r9,15
+	trtt	%r6,%r9,15
diff --git a/gas/testsuite/gas/s390/esa-z900.d b/gas/testsuite/gas/s390/esa-z900.d
new file mode 100644
index 000000000000..f6ff0812d89d
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z900.d
@@ -0,0 +1,51 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	c0 f4 00 00 00 00 [	 ]*jg	0 \<foo\>
+.*:	c0 14 00 00 00 00 [	 ]*jgo	6 \<foo\+0x6>
+.*:	c0 24 00 00 00 00 [	 ]*jgh	c \<foo\+0xc>
+.*:	c0 24 00 00 00 00 [	 ]*jgh	12 \<foo\+0x12>
+.*:	c0 34 00 00 00 00 [	 ]*jgnle	18 \<foo\+0x18>
+.*:	c0 44 00 00 00 00 [	 ]*jgl	1e \<foo\+0x1e>
+.*:	c0 44 00 00 00 00 [	 ]*jgl	24 \<foo\+0x24>
+.*:	c0 54 00 00 00 00 [	 ]*jgnhe	2a \<foo\+0x2a>
+.*:	c0 64 00 00 00 00 [	 ]*jglh	30 \<foo\+0x30>
+.*:	c0 74 00 00 00 00 [	 ]*jgne	36 \<foo\+0x36>
+.*:	c0 74 00 00 00 00 [	 ]*jgne	3c \<foo\+0x3c>
+.*:	c0 84 00 00 00 00 [	 ]*jge	42 \<foo\+0x42>
+.*:	c0 84 00 00 00 00 [	 ]*jge	48 \<foo\+0x48>
+.*:	c0 94 00 00 00 00 [	 ]*jgnlh	4e \<foo\+0x4e>
+.*:	c0 a4 00 00 00 00 [	 ]*jghe	54 \<foo\+0x54>
+.*:	c0 b4 00 00 00 00 [	 ]*jgnl	5a \<foo\+0x5a>
+.*:	c0 b4 00 00 00 00 [	 ]*jgnl	60 \<foo\+0x60>
+.*:	c0 c4 00 00 00 00 [	 ]*jgle	66 \<foo\+0x66>
+.*:	c0 d4 00 00 00 00 [	 ]*jgnh	6c \<foo\+0x6c>
+.*:	c0 d4 00 00 00 00 [	 ]*jgnh	72 \<foo\+0x72>
+.*:	c0 e4 00 00 00 00 [	 ]*jgno	78 \<foo\+0x78>
+.*:	c0 f4 00 00 00 00 [	 ]*jg	7e \<foo\+0x7e>
+.*:	c0 65 00 00 00 00 [	 ]*brasl	%r6,84 \<foo\+0x84>
+.*:	01 0b [	 ]*tam
+.*:	01 0c [	 ]*sam24
+.*:	01 0d [	 ]*sam31
+.*:	b2 b1 5f ff [	 ]*stfl	4095\(%r5\)
+.*:	b9 1f 00 69 [	 ]*lrvr	%r6,%r9
+.*:	b9 8d 00 69 [	 ]*epsw	%r6,%r9
+.*:	b9 96 00 69 [	 ]*mlr	%r6,%r9
+.*:	b9 97 00 69 [	 ]*dlr	%r6,%r9
+.*:	b9 98 00 69 [	 ]*alcr	%r6,%r9
+.*:	b9 99 00 69 [	 ]*slbr	%r6,%r9
+.*:	c0 60 00 00 00 00 [	 ]*larl	%r6,ac \<foo\+0xac\>
+.*:	e3 65 af ff 00 1e [	 ]*lrv	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 1f [	 ]*lrvh	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 3e [	 ]*strv	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 3f [	 ]*strvh	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 96 [	 ]*ml	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 97 [	 ]*dl	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 98 [	 ]*alc	%r6,4095\(%r5,%r10\)
+.*:	e3 65 af ff 00 99 [	 ]*slb	%r6,4095\(%r5,%r10\)
+.*:	eb 69 5f ff 00 1d [	 ]*rll	%r6,%r9,4095\(%r5\)
diff --git a/gas/testsuite/gas/s390/esa-z900.s b/gas/testsuite/gas/s390/esa-z900.s
new file mode 100644
index 000000000000..815732df37c8
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z900.s
@@ -0,0 +1,45 @@
+.text
+foo:
+	brcl	15,.
+	jgo	.
+	jgh	.
+	jgp	.
+	jgnle	.
+	jgl	.
+	jgm	.
+	jgnhe	.
+	jglh	.
+	jgne	.
+	jgnz	.
+	jge	.
+	jgz	.
+	jgnlh	.
+	jghe	.
+	jgnl	.
+	jgnm	.
+	jgle	.
+	jgnh	.
+	jgnp	.
+	jgno	.
+	jg	.
+	brasl	%r6,.
+	tam
+	sam24
+	sam31
+	stfl	4095(%r5)
+	lrvr	%r6,%r9
+	epsw	%r6,%r9
+	mlr	%r6,%r9
+	dlr	%r6,%r9
+	alcr	%r6,%r9
+	slbr	%r6,%r9
+	larl	%r6,.
+	lrv	%r6,4095(%r5,%r10)
+	lrvh	%r6,4095(%r5,%r10)
+	strv	%r6,4095(%r5,%r10)
+	strvh	%r6,4095(%r5,%r10)
+	ml	%r6,4095(%r5,%r10)
+	dl	%r6,4095(%r5,%r10)
+	alc	%r6,4095(%r5,%r10)
+	slb	%r6,4095(%r5,%r10)
+	rll	%r6,%r9,4095(%r5)
diff --git a/gas/testsuite/gas/s390/esa-z990.d b/gas/testsuite/gas/s390/esa-z990.d
new file mode 100644
index 000000000000..583942ebd5fa
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z990.d
@@ -0,0 +1,13 @@
+#name: s390 opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	b9 2e 00 69 [	 ]*km	%r6,%r9
+.*:	b9 2f 00 69 [	 ]*kmc	%r6,%r9
+.*:	b9 3e 00 69 [	 ]*kimd	%r6,%r9
+.*:	b9 3f 00 69 [	 ]*klmd	%r6,%r9
+.*:	b9 1e 00 69 [	 ]*kmac	%r6,%r9
diff --git a/gas/testsuite/gas/s390/esa-z990.s b/gas/testsuite/gas/s390/esa-z990.s
new file mode 100644
index 000000000000..b06a77a8ec31
--- /dev/null
+++ b/gas/testsuite/gas/s390/esa-z990.s
@@ -0,0 +1,7 @@
+.text
+foo:
+	km	%r6,%r9
+	kmc	%r6,%r9
+	kimd	%r6,%r9
+	klmd	%r6,%r9
+	kmac	%r6,%r9
diff --git a/gas/testsuite/gas/s390/opcode.d b/gas/testsuite/gas/s390/opcode.d
deleted file mode 100644
index e96454bf4cec..000000000000
--- a/gas/testsuite/gas/s390/opcode.d
+++ /dev/null
@@ -1,425 +0,0 @@
-#name: s390 opcode
-#objdump: -drw
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-.* <foo>:
-   0:	5a 65 af ff [	 ]*a	%r6,4095\(%r5,%r10\)
-   4:	6a 65 af ff [	 ]*ad	%f6,4095\(%r5,%r10\)
-   8:	ed 65 af ff 00 1a [	 ]*adb	%f6,4095\(%r5,%r10\)
-   e:	b3 1a 00 69 [	 ]*adbr	%f6,%f9
-  12:	2a 69 [	 ]*adr	%f6,%f9
-  14:	7a 65 af ff [	 ]*ae	%f6,4095\(%r5,%r10\)
-  18:	ed 65 af ff 00 0a [	 ]*aeb	%f6,4095\(%r5,%r10\)
-  1e:	b3 0a 00 69 [	 ]*aebr	%f6,%f9
-  22:	3a 69 [	 ]*aer	%f6,%f9
-  24:	4a 65 af ff [	 ]*ah	%r6,4095\(%r5,%r10\)
-  28:	a7 6a 80 01 [	 ]*ahi	%r6,-32767
-  2c:	5e 65 af ff [	 ]*al	%r6,4095\(%r5,%r10\)
-  30:	1e 69 [	 ]*alr	%r6,%r9
-  32:	fa 58 5f ff af ff [	 ]*ap	4095\(6,%r5\),4095\(9,%r10\)
-  38:	1a 69 [	 ]*ar	%r6,%r9
-  3a:	7e 65 af ff [	 ]*au	%f6,4095\(%r5,%r10\)
-  3e:	3e 69 [	 ]*aur	%f6,%f9
-  40:	6e 65 af ff [	 ]*aw	%f6,4095\(%r5,%r10\)
-  44:	2e 69 [	 ]*awr	%f6,%f9
-  46:	b3 4a 00 69 [	 ]*axbr	%f6,%f9
-  4a:	36 69 [	 ]*axr	%f6,%f9
-  4c:	47 f5 af ff [	 ]*b	4095\(%r5,%r10\)
-  50:	b2 40 00 69 [	 ]*bakr	%r6,%r9
-  54:	45 65 af ff [	 ]*bal	%r6,4095\(%r5,%r10\)
-  58:	05 69 [	 ]*balr	%r6,%r9
-  5a:	4d 65 af ff [	 ]*bas	%r6,4095\(%r5,%r10\)
-  5e:	0d 69 [	 ]*basr	%r6,%r9
-  60:	0c 69 [	 ]*bassm	%r6,%r9
-  62:	47 65 af ff [	 ]*blh	4095\(%r5,%r10\)
-  66:	07 69 [	 ]*blhr	%r9
-  68:	46 65 af ff [	 ]*bct	%r6,4095\(%r5,%r10\)
-  6c:	06 69 [	 ]*bctr	%r6,%r9
-  6e:	47 85 af ff [	 ]*be	4095\(%r5,%r10\)
-  72:	07 89 [	 ]*ber	%r9
-  74:	47 25 af ff [	 ]*bh	4095\(%r5,%r10\)
-  78:	47 a5 af ff [	 ]*bhe	4095\(%r5,%r10\)
-  7c:	07 a9 [	 ]*bher	%r9
-  7e:	07 29 [	 ]*bhr	%r9
-  80:	47 45 af ff [	 ]*bl	4095\(%r5,%r10\)
-  84:	47 c5 af ff [	 ]*ble	4095\(%r5,%r10\)
-  88:	07 c9 [	 ]*bler	%r9
-  8a:	47 65 af ff [	 ]*blh	4095\(%r5,%r10\)
-  8e:	07 69 [	 ]*blhr	%r9
-  90:	07 49 [	 ]*blr	%r9
-  92:	47 45 af ff [	 ]*bl	4095\(%r5,%r10\)
-  96:	07 49 [	 ]*blr	%r9
-  98:	47 75 af ff [	 ]*bne	4095\(%r5,%r10\)
-  9c:	07 79 [	 ]*bner	%r9
-  9e:	47 d5 af ff [	 ]*bnh	4095\(%r5,%r10\)
-  a2:	47 55 af ff [	 ]*bnhe	4095\(%r5,%r10\)
-  a6:	07 59 [	 ]*bnher	%r9
-  a8:	07 d9 [	 ]*bnhr	%r9
-  aa:	47 b5 af ff [	 ]*bnl	4095\(%r5,%r10\)
-  ae:	47 35 af ff [	 ]*bnle	4095\(%r5,%r10\)
-  b2:	07 39 [	 ]*bnler	%r9
-  b4:	47 95 af ff [	 ]*bnlh	4095\(%r5,%r10\)
-  b8:	07 99 [	 ]*bnlhr	%r9
-  ba:	07 b9 [	 ]*bnlr	%r9
-  bc:	47 b5 af ff [	 ]*bnl	4095\(%r5,%r10\)
-  c0:	07 b9 [	 ]*bnlr	%r9
-  c2:	47 e5 af ff [	 ]*bno	4095\(%r5,%r10\)
-  c6:	07 e9 [	 ]*bnor	%r9
-  c8:	47 d5 af ff [	 ]*bnh	4095\(%r5,%r10\)
-  cc:	07 d9 [	 ]*bnhr	%r9
-  ce:	47 75 af ff [	 ]*bne	4095\(%r5,%r10\)
-  d2:	07 79 [	 ]*bner	%r9
-  d4:	47 15 af ff [	 ]*bo	4095\(%r5,%r10\)
-  d8:	07 19 [	 ]*bor	%r9
-  da:	47 25 af ff [	 ]*bh	4095\(%r5,%r10\)
-  de:	07 29 [	 ]*bhr	%r9
-  e0:	07 f9 [	 ]*br	%r9
-  e2:	a7 95 00 00 [	 ]*bras	%r9,e2 <foo\+0xe2>
-  e6:	a7 64 00 00 [	 ]*jlh	e6 <foo\+0xe6>
-  ea:	a7 66 00 00 [	 ]*brct	%r6,ea <foo\+0xea>
-  ee:	84 69 00 00 [	 ]*brxh	%r6,%r9,ee <foo\+0xee>
-  f2:	85 69 00 00 [	 ]*brxle	%r6,%r9,f2 <foo\+0xf2>
-  f6:	b2 5a 00 69 [	 ]*bsa	%r6,%r9
-  fa:	b2 58 00 69 [	 ]*bsg	%r6,%r9
-  fe:	0b 69 [	 ]*bsm	%r6,%r9
- 100:	86 69 5f ff [	 ]*bxh	%r6,%r9,4095\(%r5\)
- 104:	87 69 5f ff [	 ]*bxle	%r6,%r9,4095\(%r5\)
- 108:	47 85 af ff [	 ]*be	4095\(%r5,%r10\)
- 10c:	07 89 [	 ]*ber	%r9
- 10e:	59 65 af ff [	 ]*c	%r6,4095\(%r5,%r10\)
- 112:	69 65 af ff [	 ]*cd	%f6,4095\(%r5,%r10\)
- 116:	ed 65 af ff 00 19 [	 ]*cdb	%f6,4095\(%r5,%r10\)
- 11c:	b3 19 00 69 [	 ]*cdbr	%f6,%f9
- 120:	b3 95 00 69 [	 ]*cdfbr	%r6,%f9
- 124:	29 69 [	 ]*cdr	%f6,%f9
- 126:	bb 69 5f ff [	 ]*cds	%r6,%r9,4095\(%r5\)
- 12a:	79 65 af ff [	 ]*ce	%f6,4095\(%r5,%r10\)
- 12e:	ed 65 af ff 00 09 [	 ]*ceb	%f6,4095\(%r5,%r10\)
- 134:	b3 09 00 69 [	 ]*cebr	%f6,%f9
- 138:	b3 94 00 69 [	 ]*cefbr	%r6,%f9
- 13c:	39 69 [	 ]*cer	%f6,%f9
- 13e:	b2 1a 5f ff [	 ]*cfc	4095\(%r5\)
- 142:	b3 99 50 69 [	 ]*cfdbr	%f6,5,%r9
- 146:	b3 98 50 69 [	 ]*cfebr	%f6,5,%r9
- 14a:	b3 9a 50 69 [	 ]*cfxbr	%f6,5,%r9
- 14e:	49 65 af ff [	 ]*ch	%r6,4095\(%r5,%r10\)
- 152:	a7 6e 80 01 [	 ]*chi	%r6,-32767
- 156:	b2 41 00 69 [	 ]*cksm	%r6,%r9
- 15a:	55 65 af ff [	 ]*cl	%r6,4095\(%r5,%r10\)
- 15e:	d5 ff 5f ff af ff [	 ]*clc	4095\(256,%r5\),4095\(%r10\)
- 164:	0f 69 [	 ]*clcl	%r6,%r9
- 166:	a9 69 00 0a [	 ]*clcle	%r6,%r9,10
- 16a:	95 ff 5f ff [	 ]*cli	4095\(%r5\),255
- 16e:	bd 6a 5f ff [	 ]*clm	%r6,10,4095\(%r5\)
- 172:	15 69 [	 ]*clr	%r6,%r9
- 174:	b2 5d 00 69 [	 ]*clst	%r6,%r9
- 178:	b2 63 00 69 [	 ]*cmpsc	%r6,%r9
- 17c:	f9 58 5f ff af ff [	 ]*cp	4095\(6,%r5\),4095\(9,%r10\)
- 182:	b2 4d 00 69 [	 ]*cpya	%a6,%a9
- 186:	19 69 [	 ]*cr	%r6,%r9
- 188:	ba 69 5f ff [	 ]*cs	%r6,%r9,4095\(%r5\)
- 18c:	b2 30 00 00 [	 ]*csch
- 190:	b2 50 00 69 [	 ]*csp	%r6,%r9
- 194:	b2 57 00 69 [	 ]*cuse	%r6,%r9
- 198:	b2 a7 00 69 [	 ]*cutfu	%r6,%r9
- 19c:	b2 a6 00 69 [	 ]*cuutf	%r6,%r9
- 1a0:	4f 65 af ff [	 ]*cvb	%r6,4095\(%r5,%r10\)
- 1a4:	4e 65 af ff [	 ]*cvd	%r6,4095\(%r5,%r10\)
- 1a8:	b3 49 00 69 [	 ]*cxbr	%f6,%f9
- 1ac:	b3 96 00 69 [	 ]*cxfbr	%r6,%f9
- 1b0:	5d 65 af ff [	 ]*d	%r6,4095\(%r5,%r10\)
- 1b4:	6d 65 af ff [	 ]*dd	%f6,4095\(%r5,%r10\)
- 1b8:	ed 65 af ff 00 1d [	 ]*ddb	%f6,4095\(%r5,%r10\)
- 1be:	b3 1d 00 69 [	 ]*ddbr	%f6,%f9
- 1c2:	2d 69 [	 ]*ddr	%f6,%f9
- 1c4:	7d 65 af ff [	 ]*de	%f6,4095\(%r5,%r10\)
- 1c8:	ed 65 af ff 00 0d [	 ]*deb	%f6,4095\(%r5,%r10\)
- 1ce:	b3 0d 00 69 [	 ]*debr	%f6,%f9
- 1d2:	3d 69 [	 ]*der	%f6,%f9
- 1d4:	83 69 5f ff [	 ]*diag	%r6,%r9,4095\(%r5\)
- 1d8:	b3 5b 9a 65 [	 ]*didbr	%f6,%f9,%f5,10
- 1dc:	b3 53 9a 65 [	 ]*diebr	%f6,%f9,%f5,10
- 1e0:	fd 58 5f ff af ff [	 ]*dp	4095\(6,%r5\),4095\(9,%r10\)
- 1e6:	1d 69 [	 ]*dr	%r6,%r9
- 1e8:	b3 4d 00 69 [	 ]*dxbr	%f6,%f9
- 1ec:	b2 2d 00 60 [	 ]*dxr	%f6
- 1f0:	b2 4f 00 69 [	 ]*ear	%r6,%a9
- 1f4:	de ff 5f ff af ff [	 ]*ed	4095\(256,%r5\),4095\(%r10\)
- 1fa:	df ff 5f ff af ff [	 ]*edmk	4095\(256,%r5\),4095\(%r10\)
- 200:	b3 8c 00 69 [	 ]*efpc	%r6,%r9
- 204:	b2 26 00 60 [	 ]*epar	%r6
- 208:	b2 49 00 69 [	 ]*ereg	%r6,%r9
- 20c:	b2 27 00 60 [	 ]*esar	%r6
- 210:	b2 4a 00 69 [	 ]*esta	%r6,%r9
- 214:	44 60 5f ff [	 ]*ex	%r6,4095\(%r5\)
- 218:	b3 5f 50 69 [	 ]*fidbr	%f6,5,%f9
- 21c:	b3 57 50 69 [	 ]*fiebr	%f6,5,%f9
- 220:	b3 47 50 69 [	 ]*fixbr	%f6,5,%f9
- 224:	24 69 [	 ]*hdr	%f6,%f9
- 226:	34 69 [	 ]*her	%f6,%f9
- 228:	b2 31 00 00 [	 ]*hsch
- 22c:	b2 24 00 60 [	 ]*iac	%r6
- 230:	43 65 af ff [	 ]*ic	%r6,4095\(%r5,%r10\)
- 234:	bf 6a 5f ff [	 ]*icm	%r6,10,4095\(%r5\)
- 238:	b2 0b 00 00 [	 ]*ipk
- 23c:	b2 22 00 60 [	 ]*ipm	%r6
- 240:	b2 21 00 69 [	 ]*ipte	%r6,%r9
- 244:	b2 29 00 69 [	 ]*iske	%r6,%r9
- 248:	b2 23 00 69 [	 ]*ivsk	%r6,%r9
- 24c:	a7 f4 00 00 [	 ]*j	24c <foo\+0x24c>
- 250:	a7 84 00 00 [	 ]*je	250 <foo\+0x250>
- 254:	a7 24 00 00 [	 ]*jh	254 <foo\+0x254>
- 258:	a7 a4 00 00 [	 ]*jhe	258 <foo\+0x258>
- 25c:	a7 44 00 00 [	 ]*jl	25c <foo\+0x25c>
- 260:	a7 c4 00 00 [	 ]*jle	260 <foo\+0x260>
- 264:	a7 64 00 00 [	 ]*jlh	264 <foo\+0x264>
- 268:	a7 44 00 00 [	 ]*jl	268 <foo\+0x268>
- 26c:	a7 74 00 00 [	 ]*jne	26c <foo\+0x26c>
- 270:	a7 54 00 00 [	 ]*jnhe	270 <foo\+0x270>
- 274:	a7 b4 00 00 [	 ]*jnl	274 <foo\+0x274>
- 278:	a7 34 00 00 [	 ]*jnle	278 <foo\+0x278>
- 27c:	a7 94 00 00 [	 ]*jnlh	27c <foo\+0x27c>
- 280:	a7 b4 00 00 [	 ]*jnl	280 <foo\+0x280>
- 284:	a7 e4 00 00 [	 ]*jno	284 <foo\+0x284>
- 288:	a7 d4 00 00 [	 ]*jnh	288 <foo\+0x288>
- 28c:	a7 74 00 00 [	 ]*jne	28c <foo\+0x28c>
- 290:	a7 14 00 00 [	 ]*jo	290 <foo\+0x290>
- 294:	a7 24 00 00 [	 ]*jh	294 <foo\+0x294>
- 298:	a7 84 00 00 [	 ]*je	298 <foo\+0x298>
- 29c:	ed 65 af ff 00 18 [	 ]*kdb	%f6,4095\(%r5,%r10\)
- 2a2:	b3 18 00 69 [	 ]*kdbr	%f6,%f9
- 2a6:	ed 65 af ff 00 08 [	 ]*keb	%f6,4095\(%r5,%r10\)
- 2ac:	b3 08 00 69 [	 ]*kebr	%f6,%f9
- 2b0:	b3 48 00 69 [	 ]*kxbr	%f6,%f9
- 2b4:	58 65 af ff [	 ]*l	%r6,4095\(%r5,%r10\)
- 2b8:	41 65 af ff [	 ]*la	%r6,4095\(%r5,%r10\)
- 2bc:	51 65 af ff [	 ]*lae	%r6,4095\(%r5,%r10\)
- 2c0:	9a 69 5f ff [	 ]*lam	%a6,%a9,4095\(%r5\)
- 2c4:	e5 00 5f ff af ff [	 ]*lasp	4095\(%r5\),4095\(%r10\)
- 2ca:	b3 13 00 69 [	 ]*lcdbr	%f6,%f9
- 2ce:	23 69 [	 ]*lcdr	%f6,%f9
- 2d0:	b3 03 00 69 [	 ]*lcebr	%f6,%f9
- 2d4:	33 69 [	 ]*lcer	%f6,%f9
- 2d6:	13 69 [	 ]*lcr	%r6,%r9
- 2d8:	b7 69 5f ff [	 ]*lctl	%c6,%c9,4095\(%r5\)
- 2dc:	b3 43 00 69 [	 ]*lcxbr	%f6,%f9
- 2e0:	68 60 5f ff [	 ]*ld	%f6,4095\(%r5\)
- 2e4:	ed 60 5f ff 00 04 [	 ]*ldeb	%f6,4095\(%r5\)
- 2ea:	b3 04 00 69 [	 ]*ldebr	%f6,%f9
- 2ee:	28 69 [	 ]*ldr	%f6,%f9
- 2f0:	b3 45 00 69 [	 ]*ldxbr	%f6,%f9
- 2f4:	78 60 5f ff [	 ]*le	%f6,4095\(%r5\)
- 2f8:	b3 44 00 69 [	 ]*ledbr	%f6,%f9
- 2fc:	38 69 [	 ]*ler	%f6,%f9
- 2fe:	b3 46 00 69 [	 ]*lexbr	%f6,%f9
- 302:	b2 9d 5f ff [	 ]*lfpc	4095\(%r5\)
- 306:	48 60 5f ff [	 ]*lh	%r6,4095\(%r5\)
- 30a:	a7 68 80 01 [	 ]*lhi	%r6,-32767
- 30e:	98 69 5f ff [	 ]*lm	%r6,%r9,4095\(%r5\)
- 312:	b3 11 00 69 [	 ]*lndbr	%f6,%f9
- 316:	21 69 [	 ]*lndr	%f6,%f9
- 318:	b3 01 00 69 [	 ]*lnebr	%f6,%f9
- 31c:	31 69 [	 ]*lner	%f6,%f9
- 31e:	11 69 [	 ]*lnr	%r6,%r9
- 320:	b3 41 00 69 [	 ]*lnxbr	%f6,%f9
- 324:	b3 10 00 69 [	 ]*lpdbr	%f6,%f9
- 328:	20 69 [	 ]*lpdr	%f6,%f9
- 32a:	b3 00 00 69 [	 ]*lpebr	%f6,%f9
- 32e:	30 69 [	 ]*lper	%f6,%f9
- 330:	10 69 [	 ]*lpr	%r6,%r9
- 332:	82 00 5f ff [	 ]*lpsw	4095\(%r5\)
- 336:	b3 40 00 69 [	 ]*lpxbr	%f6,%f9
- 33a:	18 69 [	 ]*lr	%r6,%r9
- 33c:	b1 65 af ff [	 ]*lra	%r6,4095\(%r5,%r10\)
- 340:	25 69 [	 ]*lrdr	%f6,%f9
- 342:	35 69 [	 ]*lrer	%f6,%f9
- 344:	b3 12 00 69 [	 ]*ltdbr	%f6,%f9
- 348:	22 69 [	 ]*ltdr	%f6,%f9
- 34a:	b3 02 00 69 [	 ]*ltebr	%f6,%f9
- 34e:	32 69 [	 ]*lter	%f6,%f9
- 350:	12 69 [	 ]*ltr	%r6,%r9
- 352:	b3 42 00 69 [	 ]*ltxbr	%f6,%f9
- 356:	b2 4b 00 69 [	 ]*lura	%r6,%r9
- 35a:	ed 65 af ff 00 05 [	 ]*lxdb	%f6,4095\(%r5,%r10\)
- 360:	b3 05 00 69 [	 ]*lxdbr	%f6,%f9
- 364:	ed 65 af ff 00 06 [	 ]*lxeb	%f6,4095\(%r5,%r10\)
- 36a:	b3 06 00 69 [	 ]*lxebr	%f6,%f9
- 36e:	5c 65 af ff [	 ]*m	%r6,4095\(%r5,%r10\)
- 372:	ed 95 af ff 60 1e [	 ]*madb	%f6,%f9,4095\(%r5,%r10\)
- 378:	b3 1e 60 95 [	 ]*madbr	%f6,%f9,%f5
- 37c:	ed 95 af ff 60 0e [	 ]*maeb	%f6,%f9,4095\(%r5,%r10\)
- 382:	b3 0e 60 95 [	 ]*maebr	%f6,%f9,%f5
- 386:	af 06 5f ff [	 ]*mc	4095\(%r5\),6
- 38a:	6c 65 af ff [	 ]*md	%f6,4095\(%r5,%r10\)
- 38e:	ed 65 af ff 00 1c [	 ]*mdb	%f6,4095\(%r5,%r10\)
- 394:	b3 1c 00 69 [	 ]*mdbr	%f6,%f9
- 398:	ed 65 af ff 00 0c [	 ]*mdeb	%f6,4095\(%r5,%r10\)
- 39e:	b3 0c 00 69 [	 ]*mdebr	%f6,%f9
- 3a2:	2c 69 [	 ]*mdr	%f6,%f9
- 3a4:	7c 65 af ff [	 ]*me	%f6,4095\(%r5,%r10\)
- 3a8:	ed 65 af ff 00 17 [	 ]*meeb	%f6,4095\(%r5,%r10\)
- 3ae:	b3 17 00 69 [	 ]*meebr	%f6,%f9
- 3b2:	3c 69 [	 ]*mer	%f6,%f9
- 3b4:	4c 65 af ff [	 ]*mh	%r6,4095\(%r5,%r10\)
- 3b8:	a7 6c 80 01 [	 ]*mhi	%r6,-32767
- 3bc:	fc ff 5f ff af ff [	 ]*mp	4095\(16,%r5\),4095\(16,%r10\)
- 3c2:	1c 69 [	 ]*mr	%r6,%r9
- 3c4:	71 65 af ff [	 ]*ms	%r6,4095\(%r5,%r10\)
- 3c8:	b2 32 5f ff [	 ]*msch	4095\(%r5\)
- 3cc:	ed 95 af ff 60 1f [	 ]*msdb	%f6,%f9,4095\(%r5,%r10\)
- 3d2:	b3 1f 60 95 [	 ]*msdbr	%f6,%f9,%f5
- 3d6:	ed 95 af ff 60 0f [	 ]*mseb	%f6,%f9,4095\(%r5,%r10\)
- 3dc:	b3 0f 60 95 [	 ]*msebr	%f6,%f9,%f5
- 3e0:	b2 52 00 69 [	 ]*msr	%r6,%r9
- 3e4:	b2 47 00 60 [	 ]*msta	%r6
- 3e8:	d2 ff 5f ff af ff [	 ]*mvc	4095\(256,%r5\),4095\(%r10\)
- 3ee:	e5 0f 5f ff af ff [	 ]*mvcdk	4095\(%r5\),4095\(%r10\)
- 3f4:	e8 ff 5f ff af ff [	 ]*mvcin	4095\(256,%r5\),4095\(%r10\)
- 3fa:	d9 69 5f ff af ff [	 ]*mvck	4095\(%r6,%r5\),4095\(%r10\),%r9
- 400:	0e 69 [	 ]*mvcl	%r6,%r9
- 402:	a8 69 00 0a [	 ]*mvcle	%r6,%r9,10
- 406:	da 69 5f ff af ff [	 ]*mvcp	4095\(%r6,%r5\),4095\(%r10\),%r9
- 40c:	db 69 5f ff af ff [	 ]*mvcs	4095\(%r6,%r5\),4095\(%r10\),%r9
- 412:	e5 0e 5f ff af ff [	 ]*mvcsk	4095\(%r5\),4095\(%r10\)
- 418:	92 ff 5f ff [	 ]*mvi	4095\(%r5\),255
- 41c:	d1 ff 5f ff af ff [	 ]*mvn	4095\(256,%r5\),4095\(%r10\)
- 422:	f1 ff 5f ff af ff [	 ]*mvo	4095\(16,%r5\),4095\(16,%r10\)
- 428:	b2 54 00 69 [	 ]*mvpg	%r6,%r9
- 42c:	b2 55 00 69 [	 ]*mvst	%r6,%r9
- 430:	d3 ff 5f ff af ff [	 ]*mvz	4095\(256,%r5\),4095\(%r10\)
- 436:	b3 4c 00 69 [	 ]*mxbr	%f6,%f9
- 43a:	67 65 af ff [	 ]*mxd	%f6,4095\(%r5,%r10\)
- 43e:	ed 65 af ff 00 07 [	 ]*mxdb	%f6,4095\(%r5,%r10\)
- 444:	b3 07 00 69 [	 ]*mxdbr	%f6,%f9
- 448:	27 69 [	 ]*mxdr	%f6,%f9
- 44a:	26 69 [	 ]*mxr	%f6,%f9
- 44c:	54 65 af ff [	 ]*n	%r6,4095\(%r5,%r10\)
- 450:	d4 ff 5f ff af ff [	 ]*nc	4095\(256,%r5\),4095\(%r10\)
- 456:	94 ff 5f ff [	 ]*ni	4095\(%r5\),255
- 45a:	47 05 af ff [	 ]*bc	0,4095\(%r5,%r10\)
- 45e:	07 06 [	 ]*bcr	0,%r6
- 460:	14 69 [	 ]*nr	%r6,%r9
- 462:	56 65 af ff [	 ]*o	%r6,4095\(%r5,%r10\)
- 466:	d6 ff 5f ff af ff [	 ]*oc	4095\(256,%r5\),4095\(%r10\)
- 46c:	96 ff 5f ff [	 ]*oi	4095\(%r5\),255
- 470:	16 69 [	 ]*or	%r6,%r9
- 472:	f2 ff 5f ff af ff [	 ]*pack	4095\(16,%r5\),4095\(16,%r10\)
- 478:	b2 48 00 00 [	 ]*palb
- 47c:	b2 18 5f ff [	 ]*pc	4095\(%r5\)
- 480:	ee 69 5f ff af ff [	 ]*plo	%r6,4095\(%r5\),%r9,4095\(%r10\)
- 486:	01 01 [	 ]*pr
- 488:	b2 28 00 69 [	 ]*pt	%r6,%r9
- 48c:	b2 0d 00 00 [	 ]*ptlb
- 490:	b2 3b 00 00 [	 ]*rchp
- 494:	b2 77 5f ff [	 ]*rp	4095\(%r5\)
- 498:	b2 2a 00 69 [	 ]*rrbe	%r6,%r9
- 49c:	b2 38 00 00 [	 ]*rsch
- 4a0:	5b 65 af ff [	 ]*s	%r6,4095\(%r5,%r10\)
- 4a4:	b2 19 5f ff [	 ]*sac	4095\(%r5\)
- 4a8:	b2 79 5f ff [	 ]*sacf	4095\(%r5\)
- 4ac:	b2 37 00 00 [	 ]*sal
- 4b0:	b2 4e 00 69 [	 ]*sar	%a6,%r9
- 4b4:	b2 3c 00 00 [	 ]*schm
- 4b8:	b2 04 5f ff [	 ]*sck	4095\(%r5\)
- 4bc:	b2 06 5f ff [	 ]*sckc	4095\(%r5\)
- 4c0:	01 07 [	 ]*sckpf
- 4c2:	6b 65 af ff [	 ]*sd	%f6,4095\(%r5,%r10\)
- 4c6:	ed 65 af ff 00 1b [	 ]*sdb	%f6,4095\(%r5,%r10\)
- 4cc:	b3 1b 00 69 [	 ]*sdbr	%f6,%f9
- 4d0:	2b 69 [	 ]*sdr	%f6,%f9
- 4d2:	7b 65 af ff [	 ]*se	%f6,4095\(%r5,%r10\)
- 4d6:	ed 65 af ff 00 0b [	 ]*seb	%f6,4095\(%r5,%r10\)
- 4dc:	b3 0b 00 69 [	 ]*sebr	%f6,%f9
- 4e0:	3b 69 [	 ]*ser	%f6,%f9
- 4e2:	b3 84 00 69 [	 ]*sfpc	%r6,%r9
- 4e6:	4b 65 af ff [	 ]*sh	%r6,4095\(%r5,%r10\)
- 4ea:	b2 14 5f ff [	 ]*sie	4095\(%r5\)
- 4ee:	b2 74 5f ff [	 ]*siga	4095\(%r5\)
- 4f2:	ae 69 5f ff [	 ]*sigp	%r6,%r9,4095\(%r5\)
- 4f6:	5f 65 af ff [	 ]*sl	%r6,4095\(%r5,%r10\)
- 4fa:	8b 60 5f ff [	 ]*sla	%r6,4095\(%r5\)
- 4fe:	8f 60 5f ff [	 ]*slda	%r6,4095\(%r5\)
- 502:	8d 60 5f ff [	 ]*sldl	%r6,4095\(%r5\)
- 506:	89 60 5f ff [	 ]*sll	%r6,4095\(%r5\)
- 50a:	1f 69 [	 ]*slr	%r6,%r9
- 50c:	fb ff 5f ff af ff [	 ]*sp	4095\(16,%r5\),4095\(16,%r10\)
- 512:	b2 0a 5f ff [	 ]*spka	4095\(%r5\)
- 516:	04 60 [	 ]*spm	%r6
- 518:	b2 08 5f ff [	 ]*spt	4095\(%r5\)
- 51c:	b2 10 5f ff [	 ]*spx	4095\(%r5\)
- 520:	ed 65 af ff 00 15 [	 ]*sqdb	%f6,4095\(%r5,%r10\)
- 526:	b3 15 00 69 [	 ]*sqdbr	%f6,%f9
- 52a:	b2 44 00 60 [	 ]*sqdr	%f6
- 52e:	ed 65 af ff 00 14 [	 ]*sqeb	%f6,4095\(%r5,%r10\)
- 534:	b3 14 00 69 [	 ]*sqebr	%f6,%f9
- 538:	b2 45 00 60 [	 ]*sqer	%f6
- 53c:	b3 16 00 69 [	 ]*sqxbr	%f6,%f9
- 540:	1b 69 [	 ]*sr	%r6,%r9
- 542:	8a 60 5f ff [	 ]*sra	%r6,4095\(%r5\)
- 546:	8e 60 5f ff [	 ]*srda	%r6,4095\(%r5\)
- 54a:	8c 60 5f ff [	 ]*srdl	%r6,4095\(%r5\)
- 54e:	88 60 5f ff [	 ]*srl	%r6,4095\(%r5\)
- 552:	b2 99 5f ff [	 ]*srnm	4095\(%r5\)
- 556:	f0 fa 5f ff af ff [	 ]*srp	4095\(16,%r5\),4095\(%r10\),10
- 55c:	b2 5e 00 69 [	 ]*srst	%r6,%r9
- 560:	b2 25 00 60 [	 ]*ssar	%r6
- 564:	b2 33 5f ff [	 ]*ssch	4095\(%r5\)
- 568:	b2 2b 00 69 [	 ]*sske	%r6,%r9
- 56c:	80 00 5f ff [	 ]*ssm	4095\(%r5\)
- 570:	50 65 af ff [	 ]*st	%r6,4095\(%r5,%r10\)
- 574:	9b 69 5f ff [	 ]*stam	%a6,%a9,4095\(%r5\)
- 578:	b2 12 5f ff [	 ]*stap	4095\(%r5\)
- 57c:	42 65 af ff [	 ]*stc	%r6,4095\(%r5,%r10\)
- 580:	b2 05 5f ff [	 ]*stck	4095\(%r5\)
- 584:	b2 07 5f ff [	 ]*stckc	4095\(%r5\)
- 588:	be 6f 5f ff [	 ]*stcm	%r6,15,4095\(%r5\)
- 58c:	b2 3a 5f ff [	 ]*stcps	4095\(%r5\)
- 590:	b2 39 5f ff [	 ]*stcrw	4095\(%r5\)
- 594:	b6 69 5f ff [	 ]*stctl	%c6,%c9,4095\(%r5\)
- 598:	60 65 af ff [	 ]*std	%f6,4095\(%r5,%r10\)
- 59c:	70 65 af ff [	 ]*ste	%f6,4095\(%r5,%r10\)
- 5a0:	b2 9c 5f ff [	 ]*stfpc	4095\(%r5\)
- 5a4:	40 65 af ff [	 ]*sth	%r6,4095\(%r5,%r10\)
- 5a8:	b2 02 5f ff [	 ]*stidp	4095\(%r5\)
- 5ac:	90 69 5f ff [	 ]*stm	%r6,%r9,4095\(%r5\)
- 5b0:	ac ff 5f ff [	 ]*stnsm	4095\(%r5\),255
- 5b4:	ad ff 5f ff [	 ]*stosm	4095\(%r5\),255
- 5b8:	b2 09 5f ff [	 ]*stpt	4095\(%r5\)
- 5bc:	b2 11 5f ff [	 ]*stpx	4095\(%r5\)
- 5c0:	b2 34 5f ff [	 ]*stsch	4095\(%r5\)
- 5c4:	b2 7d 5f ff [	 ]*stsi	4095\(%r5\)
- 5c8:	b2 46 00 69 [	 ]*stura	%r6,%r9
- 5cc:	7f 65 af ff [	 ]*su	%f6,4095\(%r5,%r10\)
- 5d0:	3f 69 [	 ]*sur	%f6,%f9
- 5d2:	0a ff [	 ]*svc	255
- 5d4:	6f 65 af ff [	 ]*sw	%f6,4095\(%r5,%r10\)
- 5d8:	2f 69 [	 ]*swr	%f6,%f9
- 5da:	b3 4b 00 69 [	 ]*sxbr	%f6,%f9
- 5de:	37 69 [	 ]*sxr	%f6,%f9
- 5e0:	b2 4c 00 69 [	 ]*tar	%a6,%r9
- 5e4:	b2 2c 00 06 [	 ]*tb	%r6
- 5e8:	ed 65 af ff 00 11 [	 ]*tcdb	%f6,4095\(%r5,%r10\)
- 5ee:	ed 65 af ff 00 10 [	 ]*tceb	%f6,4095\(%r5,%r10\)
- 5f4:	ed 65 af ff 00 12 [	 ]*tcxb	%f6,4095\(%r5,%r10\)
- 5fa:	91 ff 5f ff [	 ]*tm	4095\(%r5\),255
- 5fe:	a7 60 ff ff [	 ]*tmh	%r6,65535
- 602:	a7 61 ff ff [	 ]*tml	%r6,65535
- 606:	b2 36 5f ff [	 ]*tpi	4095\(%r5\)
- 60a:	e5 01 5f ff af ff [	 ]*tprot	4095\(%r5\),4095\(%r10\)
- 610:	dc ff 5f ff af ff [	 ]*tr	4095\(256,%r5\),4095\(%r10\)
- 616:	99 69 5f ff [	 ]*trace	%r6,%r9,4095\(%r5\)
- 61a:	01 ff [	 ]*trap2
- 61c:	b2 ff 5f ff [	 ]*trap4	4095\(%r5\)
- 620:	dd ff 5f ff af ff [	 ]*trt	4095\(256,%r5\),4095\(%r10\)
- 626:	93 00 5f ff [	 ]*ts	4095\(%r5\)
- 62a:	b2 35 5f ff [	 ]*tsch	4095\(%r5\)
- 62e:	f3 ff 5f ff af ff [	 ]*unpk	4095\(16,%r5\),4095\(16,%r10\)
- 634:	01 02 [	 ]*upt
- 636:	57 65 af ff [	 ]*x	%r6,4095\(%r5,%r10\)
- 63a:	d7 ff 5f ff af ff [	 ]*xc	4095\(256,%r5\),4095\(%r10\)
- 640:	97 ff 5f ff [	 ]*xi	4095\(%r5\),255
- 644:	17 69 [	 ]*xr	%r6,%r9
- 646:	f8 ff 5f ff af ff [	 ]*zap	4095\(16,%r5\),4095\(16,%r10\)
diff --git a/gas/testsuite/gas/s390/opcode.s b/gas/testsuite/gas/s390/opcode.s
deleted file mode 100644
index 02354b97a651..000000000000
--- a/gas/testsuite/gas/s390/opcode.s
+++ /dev/null
@@ -1,419 +0,0 @@
-.text
-foo:
-	a	%r6,4095(%r5,%r10)
-	ad	%f6,4095(%r5,%r10)
-	adb	%f6,4095(%r5,%r10)
-	adbr	%f6,%f9
-	adr	%f6,%f9
-	ae	%f6,4095(%r5,%r10)
-	aeb	%f6,4095(%r5,%r10)
-	aebr	%f6,%f9
-	aer	%f6,%f9
-	ah	%r6,4095(%r5,%r10)
-	ahi	%r6,-32767
-	al	%r6,4095(%r5,%r10)
-	alr	%r6,%r9
-	ap	4095(6,%r5),4095(9,%r10)
-	ar	%r6,%r9
-	au	%f6,4095(%r5,%r10)
-	aur	%f6,%f9
-	aw	%f6,4095(%r5,%r10)
-	awr	%f6,%f9
-	axbr	%f6,%f9
-	axr	%f6,%f9
-	b	4095(%r5,%r10)
-	bakr	%r6,%r9
-	bal	%r6,4095(%r5,%r10)
-	balr	%r6,%r9
-	bas	%r6,4095(%r5,%r10)
-	basr	%r6,%r9
-	bassm	%r6,%r9
-	bc	6,4095(%r5,%r10)
-	bcr	6,%r9
-	bct	%r6,4095(%r5,%r10)
-	bctr	%r6,%r9
-	be	4095(%r5,%r10)
-	ber	%r9
-	bh	4095(%r5,%r10)
-	bhe	4095(%r5,%r10)
-	bher	%r9
-	bhr	%r9
-	bl	4095(%r5,%r10)
-	ble	4095(%r5,%r10)
-	bler	%r9
-	blh	4095(%r5,%r10)
-	blhr	%r9
-	blr	%r9
-	bm	4095(%r5,%r10)
-	bmr	%r9
-	bne	4095(%r5,%r10)
-	bner	%r9
-	bnh	4095(%r5,%r10)
-	bnhe	4095(%r5,%r10)
-	bnher	%r9
-	bnhr	%r9
-	bnl	4095(%r5,%r10)
-	bnle	4095(%r5,%r10)
-	bnler	%r9
-	bnlh	4095(%r5,%r10)
-	bnlhr	%r9
-	bnlr	%r9
-	bnm	4095(%r5,%r10)
-	bnmr	%r9
-	bno	4095(%r5,%r10)
-	bnor	%r9
-	bnp	4095(%r5,%r10)
-	bnpr	%r9
-	bnz	4095(%r5,%r10)
-	bnzr	%r9
-	bo	4095(%r5,%r10)
-	bor	%r9
-	bp	4095(%r5,%r10)
-	bpr	%r9
-	br	%r9
-	bras	%r9,.
-	brc	6,.
-	brct	6,.
-	brxh	%r6,%r9,.
-	brxle	%r6,%r9,.
-	bsa	%r6,%r9
-	bsg	%r6,%r9
-	bsm	%r6,%r9
-	bxh	%r6,%r9,4095(%r5)
-	bxle	%r6,%r9,4095(%r5)
-	bz	4095(%r5,%r10)
-	bzr	%r9
-	c	%r6,4095(%r5,%r10)
-	cd	%f6,4095(%r5,%r10)
-	cdb	%f6,4095(%r5,%r10)
-	cdbr	%f6,%f9
-	cdfbr	%r6,%f9
-	cdr	%f6,%f9
-	cds	%r6,%r9,4095(%r5)
-	ce	%f6,4095(%r5,%r10)
-	ceb	%f6,4095(%r5,%r10)
-	cebr	%f6,%f9
-	cefbr	%r6,%f9
-	cer	%f6,%f9
-	cfc	4095(%r5)
-	cfdbr	%f6,5,%r9
-	cfebr	%f6,5,%r9
-	cfxbr	%f6,5,%r9
-	ch	%r6,4095(%r5,%r10)
-	chi	%r6,-32767
-	cksm	%r6,%r9
-	cl	%r6,4095(%r5,%r10)
-	clc	4095(256,%r5),4095(%r10)
-	clcl	%r6,%r9
-	clcle	%r6,%r9,10
-	cli	4095(%r5),255
-	clm	%r6,10,4095(%r5)
-	clr	%r6,%r9
-	clst	%r6,%r9
-	cmpsc	%r6,%r9
-	cp	4095(6,%r5),4095(9,%r10)
-	cpya	%a6,%a9
-	cr	%r6,%r9
-	cs	%r6,%r9,4095(%r5)
-	csch
-	csp	%r6,%r9
-	cuse	%r6,%r9
-	cutfu	%r6,%r9
-	cuutf	%r6,%r9
-	cvb	%r6,4095(%r5,%r10)
-	cvd	%r6,4095(%r5,%r10)
-	cxbr	%f6,%f9
-	cxfbr	%r6,%f9
-	d	%r6,4095(%r5,%r10)
-	dd	%f6,4095(%r5,%r10)
-	ddb	%f6,4095(%r5,%r10)
-	ddbr	%f6,%f9
-	ddr	%f6,%f9
-	de	%f6,4095(%r5,%r10)
-	deb	%f6,4095(%r5,%r10)
-	debr	%f6,%f9
-	der	%f6,%f9
-	diag	%r6,%r9,4095(%r5)
-	didbr	%f6,%r9,%r5,10
-	diebr	%f6,%r9,%r5,10
-	dp	4095(6,%r5),4095(9,%r10)
-	dr	%r6,%r9
-	dxbr	%f6,%f9
-	dxr	%f6
-	ear	%r6,%a9
-	ed	4095(256,%r5),4095(%r10)
-	edmk	4095(256,%r5),4095(%r10)
-	efpc	%r6,%r9
-	epar	%r6
-	ereg	%r6,%r9
-	esar	%r6
-	esta	%r6,%r9
-	ex	%r6,4095(%r5)
-	fidbr	%r6,5,%r9
-	fiebr	%r6,5,%r9
-	fixbr	%r6,5,%r9
-	hdr	%f6,%f9
-	her	%f6,%f9
-	hsch
-	iac	%r6
-	ic	%r6,4095(%r5,%r10)
-	icm	%r6,10,4095(%r5)
-	ipk
-	ipm	%r6
-	ipte	%r6,%r9
-	iske	%r6,%r9
-	ivsk	%r6,%r9
-	j	.
-	je	.
-	jh	.
-	jhe	.
-	jl	.
-	jle	.
-	jlh	.
-	jm	.
-	jne	.
-	jnhe	.
-	jnl	.
-	jnle	.
-	jnlh	.
-	jnm	.
-	jno	.
-	jnp	.
-	jnz	.
-	jo	.
-	jp	.
-	jz	.
-	kdb	%f6,4095(%r5,%r10)
-	kdbr	%f6,%f9
-	keb	%f6,4095(%r5,%r10)
-	kebr	%f6,%f9
-	kxbr	%f6,%f9
-	l	%r6,4095(%r5,%r10)
-	la	%r6,4095(%r5,%r10)
-	lae	%r6,4095(%r5,%r10)
-	lam	%a6,%a9,4095(%r5)
-	lasp	4095(%r5),4095(%r10)
-	lcdbr	%f6,%f9
-	lcdr	%f6,%f9
-	lcebr	%f6,%f9
-	lcer	%f6,%f9
-	lcr	%r6,%r9
-	lctl	%c6,%c9,4095(%r5)
-	lcxbr	%f6,%f9
-	ld	%f6,4095(%r5)
-	ldeb	%f6,4095(%r5)
-	ldebr	%f6,%f9
-	ldr	%f6,%f9
-	ldxbr	%f6,%f9
-	le	%f6,4095(%r5)
-	ledbr	%f6,%f9
-	ler	%f6,%f9
-	lexbr	%f6,%f9
-	lfpc	4095(%r5)
-	lh	%r6,4095(%r5)
-	lhi	%r6,-32767
-	lm	%r6,%r9,4095(%r5)
-	lndbr	%f6,%f9
-	lndr	%f6,%f9
-	lnebr	%f6,%f9
-	lner	%f6,%f9
-	lnr	%r6,%r9
-	lnxbr	%f6,%f9
-	lpdbr	%f6,%f9
-	lpdr	%f6,%f9
-	lpebr	%f6,%f9
-	lper	%f6,%f9
-	lpr	%r6,%r9
-	lpsw	4095(%r5)
-	lpxbr	%f6,%f9
-	lr	%r6,%r9
-	lra	%r6,4095(%r5,%r10)
-	lrdr	%f6,%f9
-	lrer	%f6,%f9
-	ltdbr	%f6,%f9
-	ltdr	%f6,%f9
-	ltebr	%f6,%f9
-	lter	%f6,%f9
-	ltr	%r6,%r9
-	ltxbr	%f6,%f9
-	lura	%r6,%r9
-	lxdb	%f6,4095(%r5,%r10)
-	lxdbr	%f6,%f9
-	lxeb	%f6,4095(%r5,%r10)
-	lxebr	%f6,%f9
-	m	%r6,4095(%r5,%r10)
-	madb	%f6,%f9,4095(%r5,%r10)
-	madbr	%f6,%f9,%f5
-	maeb	%f6,%f9,4095(%r5,%r10)
-	maebr	%f6,%f9,%f5
-	mc	4095(%r5),6
-	md	%f6,4095(%r5,%r10)
-	mdb	%f6,4095(%f5,%f10)
-	mdbr	%f6,%f9
-	mdeb	%f6,4095(%f5,%f10)
-	mdebr	%f6,%f9
-	mdr	%f6,%f9
-	me	%f6,4095(%r5,%r10)
-	meeb	%f6,4095(%r5,%r10)
-	meebr	%f6,%f9
-	mer	%f6,%f9
-	mh	%r6,4095(%r5,%r10)
-	mhi	%r6,-32767
-	mp	4095(16,%r5),4095(16,%r10)
-	mr	%r6,%r9
-	ms	%r6,4095(%r5,%r10)
-	msch	4095(%r5)
-	msdb	%f6,%f9,4095(%r5,%r10)
-	msdbr	%f6,%f9,%f5
-	mseb	%f6,%f9,4095(%r5,%r10)
-	msebr	%f6,%f9,%f5
-	msr	%r6,%r9
-	msta	%r6
-	mvc	4095(256,%r5),4095(%r10)
-	mvcdk	4095(%r5),4095(%r10)
-	mvcin	4095(256,%r5),4095(%r10)
-	mvck	4095(%r6,%r5),4095(%r10),%r9
-	mvcl	%r6,%r9
-	mvcle	%r6,%r9,10
-	mvcp	4095(%r6,%r5),4095(%r10),%r9
-	mvcs	4095(%r6,%r5),4095(%r10),%r9
-	mvcsk	4095(%r5),4095(%r10)
-	mvi	4095(%r5),255
-	mvn	4095(256,%r5),4095(%r10)
-	mvo	4095(16,%r5),4095(16,%r10)
-	mvpg	%r6,%r9
-	mvst	%r6,%r9
-	mvz	4095(256,%r5),4095(%r10)
-	mxbr	%f6,%f9
-	mxd	%f6,4095(%r5,%r10)
-	mxdb	%f6,4095(%r5,%r10)
-	mxdbr	%f6,%f9
-	mxdr	%r6,%r9
-	mxr	%r6,%r9
-	n	%r6,4095(%r5,%r10)
-	nc	4095(256,%r5),4095(%r10)
-	ni	4095(%r5),255
-	nop	4095(%r5,%r10)
-	nopr	%r6
-	nr	%r6,%r9
-	o	%r6,4095(%r5,%r10)
-	oc	4095(256,%r5),4095(%r10)
-	oi	4095(%r5),255
-	or	%r6,%r9
-	pack	4095(16,%r5),4095(16,%r10)
-	palb
-	pc	4095(%r5)
-	plo	%r6,4095(%r5),%r9,4095(%r10)
-	pr
-	pt	%r6,%r9
-	ptlb
-	rchp
-	rp	4095(%r5)
-	rrbe	%r6,%r9
-	rsch
-	s	%r6,4095(%r5,%r10)
-	sac	4095(%r5)
-	sacf	4095(%r5)
-	sal
-	sar	%a6,%r9
-	schm
-	sck	4095(%r5)
-	sckc	4095(%r5)
-	sckpf
-	sd	%f6,4095(%r5,%r10)
-	sdb	%f6,4095(%r5,%r10)
-	sdbr	%f6,%f9
-	sdr	%f6,%f9
-	se	%f6,4095(%r5,%r10)
-	seb	%f6,4095(%r5,%r10)
-	sebr	%f6,%f9
-	ser	%r6,%r9
-	sfpc	%r6,%r9
-	sh	%r6,4095(%r5,%r10)
-	sie	4095(%r5)
-	siga	4095(%r5)
-	sigp	%r6,%r9,4095(%r5)
-	sl	%r6,4095(%r5,%r10)
-	sla	%r6,4095(%r5)
-	slda	%r6,4095(%r5)
-	sldl	%r6,4095(%r5)
-	sll	%r6,4095(%r5)
-	slr	%r6,%r9
-	sp	4095(16,%r5),4095(16,%r10)
-	spka	4095(%r5)
-	spm	%r6
-	spt	4095(%r5)
-	spx	4095(%r5)
-	sqdb	%f6,4095(%r5,%r10)
-	sqdbr	%f6,%f9
-	sqdr	%f6
-	sqeb	%f6,4095(%r5,%r10)
-	sqebr	%f6,%f9
-	sqer	%f6
-	sqxbr	%f6,%f9
-	sr	%r6,%r9
-	sra	%r6,4095(%r5)
-	srda	%r6,4095(%r5)
-	srdl	%r6,4095(%r5)
-	srl	%r6,4095(%r5)
-	srnm	4095(%r5)
-	srp	4095(16,%r5),4095(%r10),10
-	srst	%r6,%r9
-	ssar	%r6
-	ssch	4095(%r5)
-	sske	%r6,%r9
-	ssm	4095(%r5)
-	st	%r6,4095(%r5,%r10)
-	stam	%a6,%a9,4095(%r5)
-	stap	4095(%r5)
-	stc	%r6,4095(%r5,%r10)
-	stck	4095(%r5)
-	stckc	4095(%r5)
-	stcm	%r6,15,4095(%r5)
-	stcps	4095(%r5)
-	stcrw	4095(%r5)
-	stctl	%c6,%c9,4095(%r5)
-	std	%f6,4095(%r5,%r10)
-	ste	%f6,4095(%r5,%r10)
-	stfpc	4095(%r5)
-	sth	%r6,4095(%r5,%r10)
-	stidp	4095(%r5)
-	stm	%r6,%r9,4095(%r5)
-	stnsm	4095(%r5),255
-	stosm	4095(%r5),255
-	stpt	4095(%r5)
-	stpx	4095(%r5)
-	stsch	4095(%r5)
-	stsi	4095(%r5)
-	stura	%r6,%r9
-	su	%f6,4095(%r5,%r10)
-	sur	%r6,%r9
-	svc	255
-	sw	%f6,4095(%r5,%r10)
-	swr	%f6,%f9
-	sxbr	%f6,%f9
-	sxr	%r6,%r9
-	tar	%a6,%r9
-	tb	%r6
-	tcdb	%f6,4095(%r5,%r10)
-	tceb	%f6,4095(%r5,%r10)
-	tcxb	%f6,4095(%r5,%r10)
-	tm	4095(%r5),255
-	tmh	%r6,65535
-	tml	%r6,65535
-	tpi	4095(%r5)
-	tprot	4095(%r5),4095(%r10)
-	tr	4095(256,%r5),4095(%r10)
-	trace	%r6,%r9,4095(%r5)
-	trap2
-	trap4	4095(%r5)
-	trt	4095(256,%r5),4095(%r10)
-	ts	4095(%r5)
-	tsch	4095(%r5)
-	unpk	4095(16,%r5),4095(16,%r10)
-	upt
-	x	%r6,4095(%r5,%r10)
-	xc	4095(256,%r5),4095(%r10)
-	xi	4095(%r5),255
-	xr	%r6,%r9
-	zap	4095(16,%r5),4095(16,%r10)
diff --git a/gas/testsuite/gas/s390/opcode64.d b/gas/testsuite/gas/s390/opcode64.d
deleted file mode 100644
index 2f867ee5dc63..000000000000
--- a/gas/testsuite/gas/s390/opcode64.d
+++ /dev/null
@@ -1,211 +0,0 @@
-#name: s390x opcode
-#objdump: -drw
-
-.*: +file format .*
-
-Disassembly of section .text:
-
-.* <foo>:
-   0:	e3 95 af ff 00 08 [ 	]*ag	%r9,4095\(%r5,%r10\)
-   6:	e3 95 af ff 00 18 [ 	]*agf	%r9,4095\(%r5,%r10\)
-   c:	b9 18 00 96 [ 	]*agfr	%r9,%r6
-  10:	a7 9b 80 01 [ 	]*aghi	%r9,-32767
-  14:	b9 08 00 96 [ 	]*agr	%r9,%r6
-  18:	e3 95 af ff 00 98 [ 	]*alc	%r9,4095\(%r5,%r10\)
-  1e:	e3 95 af ff 00 88 [ 	]*alcg	%r9,4095\(%r5,%r10\)
-  24:	b9 88 00 96 [ 	]*alcgr	%r9,%r6
-  28:	b9 98 00 96 [ 	]*alcr	%r9,%r6
-  2c:	e3 95 af ff 00 0a [ 	]*alg	%r9,4095\(%r5,%r10\)
-  32:	e3 95 af ff 00 1a [ 	]*algf	%r9,4095\(%r5,%r10\)
-  38:	b9 1a 00 96 [ 	]*algfr	%r9,%r6
-  3c:	b9 0a 00 96 [ 	]*algr	%r9,%r6
-  40:	e3 65 af ff 00 46 [ 	]*bctg	%r6,4095\(%r5,%r10\)
-  46:	b9 46 00 69 [ 	]*bctgr	%r6,%r9
-  4a:	c0 65 00 00 00 00 [ 	]*brasl	%r6,4a <foo\+0x4a>
-  50:	c0 f4 00 00 00 00 [ 	]*jg	50 <foo\+0x50>
-  56:	a7 67 00 00 [ 	]*brctg	%r6,56 <foo\+0x56>
-  5a:	ec 69 00 00 00 44 [ 	]*brxhg	%r6,%r9,5a <foo\+0x5a>
-  60:	ec 69 00 00 00 45 [ 	]*brxlg	%r6,%r9,60 <foo\+0x60>
-  66:	eb 69 5f ff 00 44 [ 	]*bxhg	%r6,%r9,4095\(%r5\)
-  6c:	eb 69 5f ff 00 45 [ 	]*bxleg	%r6,%r9,4095\(%r5\)
-  72:	b3 a5 00 69 [ 	]*cdgbr	%r6,%r9
-  76:	b3 c5 00 69 [ 	]*cdgr	%r6,%r9
-  7a:	eb 69 5f ff 00 3e [ 	]*cdsg	%r6,%r9,4095\(%r5\)
-  80:	b3 a4 00 69 [ 	]*cegbr	%r6,%r9
-  84:	b3 c4 00 69 [ 	]*cegr	%r6,%r9
-  88:	e3 65 af ff 00 20 [ 	]*cg	%r6,4095\(%r5,%r10\)
-  8e:	b3 a9 f0 69 [ 	]*cgdbr	%f6,15,%r9
-  92:	b3 c9 90 65 [ 	]*cgdr	%f6,9,%r5
-  96:	b3 a8 f0 69 [ 	]*cgebr	%f6,15,%r9
-  9a:	b3 c8 90 65 [ 	]*cger	%f6,9,%r5
-  9e:	e3 65 af ff 00 30 [ 	]*cgf	%r6,4095\(%r5,%r10\)
-  a4:	b9 30 00 69 [ 	]*cgfr	%r6,%r9
-  a8:	a7 6f 80 01 [ 	]*cghi	%r6,-32767
-  ac:	b9 20 00 69 [ 	]*cgr	%r6,%r9
-  b0:	b3 aa f0 69 [ 	]*cgxbr	%f6,15,%r9
-  b4:	b3 ca 90 65 [ 	]*cgxr	%f6,9,%r5
-  b8:	e3 65 af ff 00 21 [ 	]*clg	%r6,4095\(%r5,%r10\)
-  be:	e3 65 af ff 00 31 [ 	]*clgf	%r6,4095\(%r5,%r10\)
-  c4:	b9 31 00 69 [ 	]*clgfr	%r6,%r9
-  c8:	b9 21 00 69 [ 	]*clgr	%r6,%r9
-  cc:	eb 6a 5f ff 00 20 [ 	]*clmh	%r6,10,4095\(%r5\)
-  d2:	eb 69 5f ff 00 30 [ 	]*csg	%r6,%r9,4095\(%r5\)
-  d8:	e3 65 af ff 00 0e [ 	]*cvbg	%r6,4095\(%r5,%r10\)
-  de:	e3 65 af ff 00 2e [ 	]*cvdg	%r6,4095\(%r5,%r10\)
-  e4:	b3 a6 00 69 [ 	]*cxgbr	%r6,%r9
-  e8:	b3 c6 00 69 [ 	]*cxgr	%r6,%r9
-  ec:	e3 65 af ff 00 97 [ 	]*dl	%r6,4095\(%r5,%r10\)
-  f2:	e3 65 af ff 00 87 [ 	]*dlg	%r6,4095\(%r5,%r10\)
-  f8:	b9 87 00 69 [ 	]*dlgr	%r6,%r9
-  fc:	b9 97 00 69 [ 	]*dlr	%r6,%r9
- 100:	e3 65 af ff 00 0d [ 	]*dsg	%r6,4095\(%r5,%r10\)
- 106:	e3 65 af ff 00 1d [ 	]*dsgf	%r6,4095\(%r5,%r10\)
- 10c:	b9 1d 00 69 [ 	]*dsgfr	%r6,%r9
- 110:	b9 0d 00 69 [ 	]*dsgr	%r6,%r9
- 114:	b9 8d 00 69 [ 	]*epsw	%r6,%r9
- 118:	b9 0e 00 69 [ 	]*eregg	%r6,%r9
- 11c:	b9 9d 00 60 [ 	]*esea	%r6
- 120:	eb 6a 5f ff 00 80 [ 	]*icmh	%r6,10,4095\(%r5\)
- 126:	a5 60 ff ff [ 	]*iihh	%r6,65535
- 12a:	a5 61 ff ff [ 	]*iihl	%r6,65535
- 12e:	a5 62 ff ff [ 	]*iilh	%r6,65535
- 132:	a5 63 ff ff [ 	]*iill	%r6,65535
- 136:	c0 f4 00 00 00 00 [ 	]*jg	136 <foo\+0x136>
- 13c:	c0 84 00 00 00 00 [ 	]*jge	13c <foo\+0x13c>
- 142:	c0 24 00 00 00 00 [ 	]*jgh	142 <foo\+0x142>
- 148:	c0 a4 00 00 00 00 [ 	]*jghe	148 <foo\+0x148>
- 14e:	c0 44 00 00 00 00 [ 	]*jgl	14e <foo\+0x14e>
- 154:	c0 c4 00 00 00 00 [ 	]*jgle	154 <foo\+0x154>
- 15a:	c0 64 00 00 00 00 [ 	]*jglh	15a <foo\+0x15a>
- 160:	c0 44 00 00 00 00 [ 	]*jgl	160 <foo\+0x160>
- 166:	c0 74 00 00 00 00 [ 	]*jgne	166 <foo\+0x166>
- 16c:	c0 d4 00 00 00 00 [ 	]*jgnh	16c <foo\+0x16c>
- 172:	c0 54 00 00 00 00 [ 	]*jgnhe	172 <foo\+0x172>
- 178:	c0 b4 00 00 00 00 [ 	]*jgnl	178 <foo\+0x178>
- 17e:	c0 34 00 00 00 00 [ 	]*jgnle	17e <foo\+0x17e>
- 184:	c0 94 00 00 00 00 [ 	]*jgnlh	184 <foo\+0x184>
- 18a:	c0 b4 00 00 00 00 [ 	]*jgnl	18a <foo\+0x18a>
- 190:	c0 e4 00 00 00 00 [ 	]*jgno	190 <foo\+0x190>
- 196:	c0 d4 00 00 00 00 [ 	]*jgnh	196 <foo\+0x196>
- 19c:	c0 74 00 00 00 00 [ 	]*jgne	19c <foo\+0x19c>
- 1a2:	c0 14 00 00 00 00 [ 	]*jgo	1a2 <foo\+0x1a2>
- 1a8:	c0 24 00 00 00 00 [ 	]*jgh	1a8 <foo\+0x1a8>
- 1ae:	c0 84 00 00 00 00 [ 	]*jge	1ae <foo\+0x1ae>
- 1b4:	c0 60 00 00 00 00 [ 	]*larl	%r6,1b4 <foo\+0x1b4>
- 1ba:	b9 13 00 69 [ 	]*lcgfr	%r6,%r9
- 1be:	b9 03 00 69 [ 	]*lcgr	%r6,%r9
- 1c2:	eb 69 5f ff 00 2f [ 	]*lctlg	%r6,%r9,4095\(%r5\)
- 1c8:	e3 65 af ff 00 04 [ 	]*lg	%r6,4095\(%r5,%r10\)
- 1ce:	e3 65 af ff 00 14 [ 	]*lgf	%r6,4095\(%r5,%r10\)
- 1d4:	b9 14 00 69 [ 	]*lgfr	%r6,%r9
- 1d8:	e3 65 af ff 00 15 [ 	]*lgh	%r6,4095\(%r5,%r10\)
- 1de:	a7 69 80 01 [ 	]*lghi	%r6,-32767
- 1e2:	b9 04 00 69 [ 	]*lgr	%r6,%r9
- 1e6:	e3 65 af ff 00 90 [ 	]*llgc	%r6,4095\(%r5,%r10\)
- 1ec:	e3 65 af ff 00 16 [ 	]*llgf	%r6,4095\(%r5,%r10\)
- 1f2:	b9 16 00 69 [ 	]*llgfr	%r6,%r9
- 1f6:	e3 65 af ff 00 91 [ 	]*llgh	%r6,4095\(%r5,%r10\)
- 1fc:	e3 65 af ff 00 17 [ 	]*llgt	%r6,4095\(%r5,%r10\)
- 202:	b9 17 00 69 [ 	]*llgtr	%r6,%r9
- 206:	a5 6c ff ff [ 	]*llihh	%r6,65535
- 20a:	a5 6d ff ff [ 	]*llihl	%r6,65535
- 20e:	a5 6e ff ff [ 	]*llilh	%r6,65535
- 212:	a5 6f ff ff [ 	]*llill	%r6,65535
- 216:	ef 69 5f ff af ff [ 	]*lmd	%r6,%r9,4095\(%r5\),4095\(%r10\)
- 21c:	eb 69 5f ff 00 04 [ 	]*lmg	%r6,%r9,4095\(%r5\)
- 222:	eb 69 5f ff 00 96 [ 	]*lmh	%r6,%r9,4095\(%r5\)
- 228:	b9 11 00 69 [ 	]*lngfr	%r6,%r9
- 22c:	b9 01 00 69 [ 	]*lngr	%r6,%r9
- 230:	b9 10 00 69 [ 	]*lpgfr	%r6,%r9
- 234:	b9 00 00 69 [ 	]*lpgr	%r6,%r9
- 238:	e3 65 af ff 00 8f [ 	]*lpq	%r6,4095\(%r5,%r10\)
- 23e:	b2 b2 5f ff [ 	]*lpswe	4095\(%r5\)
- 242:	e3 65 af ff 00 03 [ 	]*lrag	%r6,4095\(%r5,%r10\)
- 248:	e3 65 af ff 00 1e [ 	]*lrv	%r6,4095\(%r5,%r10\)
- 24e:	e3 65 af ff 00 0f [ 	]*lrvg	%r6,4095\(%r5,%r10\)
- 254:	b9 0f 00 69 [ 	]*lrvgr	%r6,%r9
- 258:	e3 65 af ff 00 1f [ 	]*lrvh	%r6,4095\(%r5,%r10\)
- 25e:	b9 1f 00 69 [ 	]*lrvr	%r6,%r9
- 262:	b9 12 00 69 [ 	]*ltgfr	%r6,%r9
- 266:	b9 02 00 69 [ 	]*ltgr	%r6,%r9
- 26a:	b9 05 00 69 [ 	]*lurag	%r6,%r9
- 26e:	b3 75 00 60 [ 	]*lzdr	%r6
- 272:	b3 74 00 60 [ 	]*lzer	%r6
- 276:	b3 76 00 60 [ 	]*lzxr	%r6
- 27a:	a7 6d 80 01 [ 	]*mghi	%r6,-32767
- 27e:	e3 65 af ff 00 96 [ 	]*ml	%r6,4095\(%r5,%r10\)
- 284:	e3 65 af ff 00 86 [ 	]*mlg	%r6,4095\(%r5,%r10\)
- 28a:	b9 86 00 69 [ 	]*mlgr	%r6,%r9
- 28e:	b9 96 00 69 [ 	]*mlr	%r6,%r9
- 292:	e3 65 af ff 00 0c [ 	]*msg	%r6,4095\(%r5,%r10\)
- 298:	e3 65 af ff 00 1c [ 	]*msgf	%r6,4095\(%r5,%r10\)
- 29e:	b9 1c 00 69 [ 	]*msgfr	%r6,%r9
- 2a2:	b9 0c 00 69 [ 	]*msgr	%r6,%r9
- 2a6:	eb 69 5f ff 00 8e [ 	]*mvclu	%r6,%r9,4095\(%r5\)
- 2ac:	e3 65 af ff 00 80 [ 	]*ng	%r6,4095\(%r5,%r10\)
- 2b2:	b9 80 00 69 [ 	]*ngr	%r6,%r9
- 2b6:	a5 64 ff ff [ 	]*nihh	%r6,65535
- 2ba:	a5 65 ff ff [ 	]*nihl	%r6,65535
- 2be:	a5 66 ff ff [ 	]*nilh	%r6,65535
- 2c2:	a5 67 ff ff [ 	]*nill	%r6,65535
- 2c6:	e3 65 af ff 00 81 [ 	]*og	%r6,4095\(%r5,%r10\)
- 2cc:	b9 81 00 69 [ 	]*ogr	%r6,%r9
- 2d0:	a5 68 ff ff [ 	]*oihh	%r6,65535
- 2d4:	a5 69 ff ff [ 	]*oihl	%r6,65535
- 2d8:	a5 6a ff ff [ 	]*oilh	%r6,65535
- 2dc:	a5 6b ff ff [ 	]*oill	%r6,65535
- 2e0:	e9 ff 5f ff af ff [ 	]*pka	4095\(256,%r5\),4095\(%r10\)
- 2e6:	e1 ff 5f ff af ff [ 	]*pku	4095\(256,%r5\),4095\(%r10\)
- 2ec:	eb 69 5f ff 00 1d [ 	]*rll	%r6,%r9,4095\(%r5\)
- 2f2:	eb 69 5f ff 00 1c [ 	]*rllg	%r6,%r9,4095\(%r5\)
- 2f8:	01 0c [ 	]*sam24
- 2fa:	01 0d [ 	]*sam31
- 2fc:	01 0e [ 	]*sam64
- 2fe:	e3 65 af ff 00 09 [ 	]*sg	%r6,4095\(%r5,%r10\)
- 304:	e3 65 af ff 00 19 [ 	]*sgf	%r6,4095\(%r5,%r10\)
- 30a:	b9 19 00 69 [ 	]*sgfr	%r6,%r9
- 30e:	b9 09 00 69 [ 	]*sgr	%r6,%r9
- 312:	eb 69 5f ff 00 0b [ 	]*slag	%r6,%r9,4095\(%r5\)
- 318:	e3 65 af ff 00 99 [ 	]*slb	%r6,4095\(%r5,%r10\)
- 31e:	e3 65 af ff 00 89 [ 	]*slbg	%r6,4095\(%r5,%r10\)
- 324:	b9 89 00 69 [ 	]*slbgr	%r6,%r9
- 328:	b9 99 00 69 [ 	]*slbr	%r6,%r9
- 32c:	e3 65 af ff 00 0b [ 	]*slg	%r6,4095\(%r5,%r10\)
- 332:	e3 65 af ff 00 1b [ 	]*slgf	%r6,4095\(%r5,%r10\)
- 338:	b9 1b 00 69 [ 	]*slgfr	%r6,%r9
- 33c:	b9 0b 00 69 [ 	]*slgr	%r6,%r9
- 340:	eb 69 5f ff 00 0d [ 	]*sllg	%r6,%r9,4095\(%r5\)
- 346:	eb 69 5f ff 00 0a [ 	]*srag	%r6,%r9,4095\(%r5\)
- 34c:	eb 69 5f ff 00 0c [ 	]*srlg	%r6,%r9,4095\(%r5\)
- 352:	b2 78 5f ff [ 	]*stcke	4095\(%r5\)
- 356:	eb 6a 5f ff 00 2c [ 	]*stcmh	%r6,10,4095\(%r5\)
- 35c:	eb 69 5f ff 00 25 [ 	]*stctg	%r6,%r9,4095\(%r5\)
- 362:	b2 b1 5f ff [ 	]*stfl	4095\(%r5\)
- 366:	e3 65 af ff 00 24 [ 	]*stg	%r6,4095\(%r5,%r10\)
- 36c:	eb 69 5f ff 00 24 [ 	]*stmg	%r6,%r9,4095\(%r5\)
- 372:	eb 69 5f ff 00 26 [ 	]*stmh	%r6,%r9,4095\(%r5\)
- 378:	e3 65 af ff 00 8e [ 	]*stpq	%r6,4095\(%r5,%r10\)
- 37e:	e5 00 5f ff 9f ff [ 	]*lasp	4095\(%r5\),4095\(%r9\)
- 384:	e3 65 af ff 00 3e [ 	]*strv	%r6,4095\(%r5,%r10\)
- 38a:	e3 65 af ff 00 2f [ 	]*strvg	%r6,4095\(%r5,%r10\)
- 390:	e3 65 af ff 00 3f [ 	]*strvh	%r6,4095\(%r5,%r10\)
- 396:	b9 25 00 69 [ 	]*sturg	%r6,%r9
- 39a:	01 0b [ 	]*tam
- 39c:	b3 51 f0 69 [ 	]*tbdr	%f6,15,%f9
- 3a0:	b3 50 f0 69 [ 	]*tbedr	%f6,15,%f9
- 3a4:	b3 58 00 69 [ 	]*thder	%r6,%r9
- 3a8:	b3 59 00 69 [ 	]*thdr	%r6,%r9
- 3ac:	a7 62 ff ff [ 	]*tmhh	%r6,65535
- 3b0:	a7 63 ff ff [ 	]*tmhl	%r6,65535
- 3b4:	a7 60 ff ff [ 	]*tmh	%r6,65535
- 3b8:	a7 61 ff ff [ 	]*tml	%r6,65535
- 3bc:	eb 69 5f ff 00 0f [ 	]*tracg	%r6,%r9,4095\(%r5\)
- 3c2:	b2 a5 00 69 [ 	]*tre	%r6,%r9
- 3c6:	b9 93 00 69 [ 	]*troo	%r6,%r9
- 3ca:	b9 92 00 69 [ 	]*trot	%r6,%r9
- 3ce:	b9 91 00 69 [ 	]*trto	%r6,%r9
- 3d2:	b9 90 00 69 [ 	]*trtt	%r6,%r9
- 3d6:	ea ff 5f ff af ff [ 	]*unpka	4095\(256,%r5\),4095\(%r10\)
- 3dc:	e2 ff 5f ff af ff [ 	]*unpku	4095\(256,%r5\),4095\(%r10\)
- 3e2:	e3 65 af ff 00 82 [ 	]*xg	%r6,4095\(%r5,%r10\)
- 3e8:	b9 82 00 69 [ 	]*xgr	%r6,%r9
diff --git a/gas/testsuite/gas/s390/opcode64.s b/gas/testsuite/gas/s390/opcode64.s
deleted file mode 100644
index 07fdad3258be..000000000000
--- a/gas/testsuite/gas/s390/opcode64.s
+++ /dev/null
@@ -1,205 +0,0 @@
-.text
-foo:
-	ag	%r9,4095(%r5,%r10)
-	agf	%r9,4095(%r5,%r10)
-	agfr	%r9,%r6
-	aghi	%r9,-32767
-	agr	%r9,%r6
-	alc	%r9,4095(%r5,%r10)
-	alcg	%r9,4095(%r5,%r10)
-	alcgr	%r9,%r6
-	alcr	%r9,%r6
-	alg	%r9,4095(%r5,%r10)
-	algf	%r9,4095(%r5,%r10)
-	algfr	%r9,%r6
-	algr	%r9,%r6
-	bctg	%r6,4095(%r5,%r10)
-	bctgr	%r6,%r9
-	brasl	%r6,.
-	brcl	15,.
-	brctg	%r6,.
-	brxhg	%r6,%r9,.
-	brxlg	%r6,%r9,.
-	bxhg	%r6,%r9,4095(%r5)
-	bxleg	%r6,%r9,4095(%r5)
-	cdgbr	%r6,%r9
-	cdgr	%r6,%r9
-	cdsg	%r6,%r9,4095(%r5)
-	cegbr	%r6,%r9
-	cegr	%r6,%r9
-	cg	%r6,4095(%r5,%r10)
-	cgdbr	%r6,15,%r9
-	cgdr	%f6,9,%r5
-	cgebr	%r6,15,%r9
-	cger	%f6,9,%r5
-	cgf	%r6,4095(%r5,%r10)
-	cgfr	%r6,%r9
-	cghi	%r6,-32767
-	cgr	%r6,%r9
-	cgxbr	%r6,15,%r9
-	cgxr	%f6,9,%r5
-	clg	%r6,4095(%r5,%r10)
-	clgf	%r6,4095(%r5,%r10)
-	clgfr	%r6,%r9
-	clgr	%r6,%r9
-	clmh	%r6,10,4095(%r5)
-	csg	%r6,%r9,4095(%r5)
-	cvbg	%r6,4095(%r5,%r10)
-	cvdg	%r6,4095(%r5,%r10)
-	cxgbr	%r6,%r9
-	cxgr	%r6,%r9
-	dl	%r6,4095(%r5,%r10)
-	dlg	%r6,4095(%r5,%r10)
-	dlgr	%r6,%r9
-	dlr	%r6,%r9
-	dsg	%r6,4095(%r5,%r10)
-	dsgf	%r6,4095(%r5,%r10)
-	dsgfr	%r6,%r9
-	dsgr	%r6,%r9
-	epsw	%r6,%r9
-	eregg	%r6,%r9
-	esea	%r6
-	icmh	%r6,10,4095(%r5)
-	iihh	%r6,65535
-	iihl	%r6,65535
-	iilh	%r6,65535
-	iill	%r6,65535
-	jg	.
-	jge	.
-	jgh	.
-	jghe	.
-	jgl	.
-	jgle	.
-	jglh	.
-	jgm	.
-	jgne	.
-	jgnh	.
-	jgnhe	.
-	jgnl	.
-	jgnle	.
-	jgnlh	.
-	jgnm	.
-	jgno	.
-	jgnp	.
-	jgnz	.
-	jgo	.
-	jgp	.
-	jgz	.
-	larl	%r6,.
-	lcgfr	%r6,%r9
-	lcgr	%r6,%r9
-	lctlg	%r6,%r9,4095(%r5)
-	lg	%r6,4095(%r5,%r10)
-	lgf	%r6,4095(%r5,%r10)
-	lgfr	%r6,%r9
-	lgh	%r6,4095(%r5,%r10)
-	lghi	%r6,-32767
-	lgr	%r6,%r9
-	llgc	%r6,4095(%r5,%r10)
-	llgf	%r6,4095(%r5,%r10)
-	llgfr	%r6,%r9
-	llgh	%r6,4095(%r5,%r10)
-	llgt	%r6,4095(%r5,%r10)
-	llgtr	%r6,%r9
-	llihh	%r6,65535
-	llihl	%r6,65535
-	llilh	%r6,65535
-	llill	%r6,65535
-	lmd	%r6,%r9,4095(%r5),4095(%r10)
-	lmg	%r6,%r9,4095(%r5)
-	lmh	%r6,%r9,4095(%r5)
-	lngfr	%r6,%r9
-	lngr	%r6,%r9
-	lpgfr	%r6,%r9
-	lpgr	%r6,%r9
-	lpq	%r6,4095(%r5,%r10)
-	lpswe	4095(%r5)
-	lrag	%r6,4095(%r5,%r10)
-	lrv	%r6,4095(%r5,%r10)
-	lrvg	%r6,4095(%r5,%r10)
-	lrvgr	%r6,%r9
-	lrvh	%r6,4095(%r5,%r10)
-	lrvr	%r6,%r9
-	ltgfr	%r6,%r9
-	ltgr	%r6,%r9
-	lurag	%r6,%r9
-	lzdr	%r6
-	lzer	%r6
-	lzxr	%r6
-	mghi	%r6,-32767
-	ml	%r6,4095(%r5,%r10)
-	mlg	%r6,4095(%r5,%r10)
-	mlgr	%r6,%r9
-	mlr	%r6,%r9
-	msg	%r6,4095(%r5,%r10)
-	msgf	%r6,4095(%r5,%r10)
-	msgfr	%r6,%r9
-	msgr	%r6,%r9
-	mvclu	%r6,%r9,4095(%r5)
-	ng	%r6,4095(%r5,%r10)
-	ngr	%r6,%r9
-	nihh	%r6,65535
-	nihl	%r6,65535
-	nilh	%r6,65535
-	nill	%r6,65535
-	og	%r6,4095(%r5,%r10)
-	ogr	%r6,%r9
-	oihh	%r6,65535
-	oihl	%r6,65535
-	oilh	%r6,65535
-	oill	%r6,65535
-	pka	4095(256,%r5),4095(%r10)
-	pku	4095(256,%r5),4095(%r10)
-	rll	%r6,%r9,4095(%r5)
-	rllg	%r6,%r9,4095(%r5)
-	sam24
-	sam31
-	sam64
-	sg	%r6,4095(%r5,%r10)
-	sgf	%r6,4095(%r5,%r10)
-	sgfr	%r6,%r9
-	sgr	%r6,%r9
-	slag	%r6,%r9,4095(%r5)
-	slb	%r6,4095(%r5,%r10)
-	slbg	%r6,4095(%r5,%r10)
-	slbgr	%r6,%r9
-	slbr	%r6,%r9
-	slg	%r6,4095(%r5,%r10)
-	slgf	%r6,4095(%r5,%r10)
-	slgfr	%r6,%r9
-	slgr	%r6,%r9
-	sllg	%r6,%r9,4095(%r5)
-	srag	%r6,%r9,4095(%r5)
-	srlg	%r6,%r9,4095(%r5)
-	stcke	4095(%r5)
-	stcmh	%r6,10,4095(%r5)
-	stctg	%r6,%r9,4095(%r5)
-	stfl	4095(%r5)
-	stg	%r6,4095(%r5,%r10)
-	stmg	%r6,%r9,4095(%r5)
-	stmh	%r6,%r9,4095(%r5)
-	stpq	%r6,4095(%r5,%r10)
-	strag	4095(%r5),4095(%r9)
-	strv	%r6,4095(%r5,%r10)
-	strvg	%r6,4095(%r5,%r10)
-	strvh	%r6,4095(%r5,%r10)
-	sturg	%r6,%r9
-	tam
-	tbdr	%r6,15,%r9
-	tbedr	%r6,15,%r9
-	thder	%r6,%r9
-	thdr	%r6,%r9
-	tmhh	%r6,65535
-	tmhl	%r6,65535
-	tmlh	%r6,65535
-	tmll	%r6,65535
-	tracg	%r6,%r9,4095(%r5)
-	tre	%r6,%r9
-	troo	%r6,%r9
-	trot	%r6,%r9
-	trto	%r6,%r9
-	trtt	%r6,%r9
-	unpka	4095(256,%r5),4095(%r10)
-	unpku	4095(256,%r5),4095(%r10)
-	xg	%r6,4095(%r5,%r10)
-	xgr	%r6,%r9
diff --git a/gas/testsuite/gas/s390/s390.exp b/gas/testsuite/gas/s390/s390.exp
index 24e98d0b8dca..3d9a4a135c80 100644
--- a/gas/testsuite/gas/s390/s390.exp
+++ b/gas/testsuite/gas/s390/s390.exp
@@ -17,19 +17,21 @@ proc run_list_test { name opts } {
 
 if [expr [istarget "s390-*-*"] ||  [istarget "s390x-*-*"]]  then {
 
-    run_dump_test "opcode"
-    run_dump_test "reloc"
-    run_dump_test "operands"
+    run_dump_test "esa-g5" "{as -m31}"
+    run_dump_test "esa-z900" "{as -m31} {as -march=z900}"
+    run_dump_test "esa-z990" "{as -m31} {as -march=z990}"
+    run_dump_test "esa-z9-109" "{as -m31} {as -march=z9-109}"
+    run_dump_test "esa-reloc" "{as -m31}"
+    run_dump_test "esa-operands" "{as -m31}"
 
 #    # PIC is only supported on ELF targets.
 #    if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"] ) } then {
 #	run_dump_test "s390pic"
 #    }
-}
-
-if [istarget "s390x-*-*"] then {
 
-    run_dump_test "opcode64"
-    run_dump_test "reloc64"
-    run_dump_test "operands64"
+    run_dump_test "zarch-z900" "{as -m64}"
+    run_dump_test "zarch-z990" "{as -m64} {as -march=z990}"
+    run_dump_test "zarch-z9-109" "{as -m64} {as -march=z9-109}"
+    run_dump_test "zarch-reloc" "{as -m64}"
+    run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
 }
diff --git a/gas/testsuite/gas/s390/zarch-operands.d b/gas/testsuite/gas/s390/zarch-operands.d
new file mode 100644
index 000000000000..f92df79356ee
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-operands.d
@@ -0,0 +1,14 @@
+#name: s390x operands
+#objdump: -dr
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+   0:	ec 12 00 00 00 45 [ 	]*brxlg	%r1,%r2,0 <foo>
+[ 	]*2: R_390_PC16DBL	test_rie\+0x2
+   6:	c0 e5 00 00 00 00 [ 	]*brasl	%r14,6 <foo\+0x6>
+[ 	]*8: R_390_PC32DBL	test_ril\+0x2
+   c:	eb 12 40 03 00 0d [ 	]*sllg	%r1,%r2,3\(%r4\)
+  12:	c8 50 20 01 40 03 [ 	]*mvcos	1\(%r2\),3\(%r4\),%r5
diff --git a/gas/testsuite/gas/s390/zarch-operands.s b/gas/testsuite/gas/s390/zarch-operands.s
new file mode 100644
index 000000000000..00b1ec7d4b7f
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-operands.s
@@ -0,0 +1,6 @@
+.text
+foo:
+	.insn rie,0xec0000000045,%r1,%r2,test_rie
+	.insn ril,0xc00500000000,%r14,test_ril
+	.insn rse,0xeb000000000d,%r1,%r2,3(%r4)
+	.insn ssf,0xc80000000000,1(%r2),3(%r4),%r5
diff --git a/gas/testsuite/gas/s390/reloc64.d b/gas/testsuite/gas/s390/zarch-reloc.d
index 7660278dd191..7660278dd191 100644
--- a/gas/testsuite/gas/s390/reloc64.d
+++ b/gas/testsuite/gas/s390/zarch-reloc.d
diff --git a/gas/testsuite/gas/s390/reloc64.s b/gas/testsuite/gas/s390/zarch-reloc.s
index d6ec22f26b66..d6ec22f26b66 100644
--- a/gas/testsuite/gas/s390/reloc64.s
+++ b/gas/testsuite/gas/s390/zarch-reloc.s
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.d b/gas/testsuite/gas/s390/zarch-z9-109.d
new file mode 100644
index 000000000000..1fce287bed61
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z9-109.d
@@ -0,0 +1,65 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	c2 69 80 00 00 00 [	 ]*afi	%r6,-2147483648
+.*:	c2 68 80 00 00 00 [	 ]*agfi	%r6,-2147483648
+.*:	c2 6b ff ff ff ff [	 ]*alfi	%r6,4294967295
+.*:	c2 6a ff ff ff ff [	 ]*algfi	%r6,4294967295
+.*:	c0 6a ff ff ff ff [	 ]*nihf	%r6,4294967295
+.*:	c0 6b ff ff ff ff [	 ]*nilf	%r6,4294967295
+.*:	c2 6d 80 00 00 00 [	 ]*cfi	%r6,-2147483648
+.*:	c2 6c 80 00 00 00 [	 ]*cgfi	%r6,-2147483648
+.*:	c2 6f ff ff ff ff [	 ]*clfi	%r6,4294967295
+.*:	c2 6e ff ff ff ff [	 ]*clgfi	%r6,4294967295
+.*:	c0 66 ff ff ff ff [	 ]*xihf	%r6,4294967295
+.*:	c0 67 ff ff ff ff [	 ]*xilf	%r6,4294967295
+.*:	c0 68 ff ff ff ff [	 ]*iihf	%r6,4294967295
+.*:	c0 69 ff ff ff ff [	 ]*iilf	%r6,4294967295
+.*:	b9 83 00 69 [	 ]*flogr	%r6,%r9
+.*:	e3 65 a0 00 80 12 [	 ]*lt	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 02 [	 ]*ltg	%r6,-524288\(%r5,%r10\)
+.*:	b9 26 00 69 [	 ]*lbr	%r6,%r9
+.*:	b9 06 00 69 [	 ]*lgbr	%r6,%r9
+.*:	b9 27 00 69 [	 ]*lhr	%r6,%r9
+.*:	b9 07 00 69 [	 ]*lghr	%r6,%r9
+.*:	c0 61 80 00 00 00 [	 ]*lgfi	%r6,-2147483648
+.*:	e3 65 a0 00 80 94 [	 ]*llc	%r6,-524288\(%r5,%r10\)
+.*:	b9 94 00 69 [	 ]*llcr	%r6,%r9
+.*:	b9 84 00 69 [	 ]*llgcr	%r6,%r9
+.*:	e3 65 a0 00 80 95 [	 ]*llh	%r6,-524288\(%r5,%r10\)
+.*:	b9 95 00 69 [	 ]*llhr	%r6,%r9
+.*:	b9 85 00 69 [	 ]*llghr	%r6,%r9
+.*:	c0 6e ff ff ff ff [	 ]*llihf	%r6,4294967295
+.*:	c0 6f ff ff ff ff [	 ]*llilf	%r6,4294967295
+.*:	c0 6c ff ff ff ff [	 ]*oihf	%r6,4294967295
+.*:	c0 6d ff ff ff ff [	 ]*oilf	%r6,4294967295
+.*:	c2 65 ff ff ff ff [	 ]*slfi	%r6,4294967295
+.*:	c2 64 ff ff ff ff [	 ]*slgfi	%r6,4294967295
+.*:	b2 b0 5f ff [	 ]*stfle	4095\(%r5\)
+.*:	b2 7c 5f ff [	 ]*stckf	4095\(%r5\)
+.*:	c8 60 5f ff af ff [	 ]*mvcos	4095\(%r5\),4095\(%r10\),%r6
+.*:	b9 aa 5f 69 [	 ]*lptea	%r6,%r9,%r5,15
+.*:	b2 2b f0 69 [	 ]*sske	%r6,%r9,15
+.*:	b9 b1 f0 69 [	 ]*cu24	%r6,%r9,15
+.*:	b2 a6 f0 69 [	 ]*cu21	%r6,%r9,15
+.*:	b9 b3 f0 69 [	 ]*cu42	%r6,%r9,15
+.*:	b9 b2 f0 69 [	 ]*cu41	%r6,%r9,15
+.*:	b2 a7 f0 69 [	 ]*cu12	%r6,%r9,15
+.*:	b9 b0 f0 69 [	 ]*cu14	%r6,%r9,15
+.*:	b3 3b 60 95 [	 ]*myr	%f6,%f9,%f5
+.*:	b3 3d 60 95 [	 ]*myhr	%f6,%f9,%f5
+.*:	b3 39 60 95 [	 ]*mylr	%f6,%f9,%f5
+.*:	ed 95 af ff 60 3b [	 ]*my	%f6,%f9,4095\(%r5,%r10\)
+.*:	ed 95 af ff 60 3d [	 ]*myh	%f6,%f9,4095\(%r5,%r10\)
+.*:	ed 95 af ff 60 39 [	 ]*myl	%f6,%f9,4095\(%r5,%r10\)
+.*:	b3 3a 60 95 [	 ]*mayr	%f6,%f9,%f5
+.*:	b3 3c 60 95 [	 ]*mayhr	%f6,%f9,%f5
+.*:	b3 38 60 95 [	 ]*maylr	%f6,%f9,%f5
+.*:	ed 95 af ff 60 3a [	 ]*may	%f6,%f9,4095\(%r5,%r10\)
+.*:	ed 95 af ff 60 3c [	 ]*mayh	%f6,%f9,4095\(%r5,%r10\)
+.*:	ed 95 af ff 60 38 [	 ]*mayl	%f6,%f9,4095\(%r5,%r10\)
diff --git a/gas/testsuite/gas/s390/zarch-z9-109.s b/gas/testsuite/gas/s390/zarch-z9-109.s
new file mode 100644
index 000000000000..1c56cb3e9fbb
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z9-109.s
@@ -0,0 +1,59 @@
+.text
+foo:
+	afi	%r6,-2147483648
+	agfi	%r6,-2147483648
+	alfi	%r6,4294967295
+	algfi	%r6,4294967295
+	nihf	%r6,4294967295
+	nilf	%r6,4294967295
+	cfi	%r6,-2147483648
+	cgfi	%r6,-2147483648
+	clfi	%r6,4294967295
+	clgfi	%r6,4294967295
+	xihf	%r6,4294967295
+	xilf	%r6,4294967295
+	iihf	%r6,4294967295
+	iilf	%r6,4294967295
+	flogr	%r6,%r9
+	lt	%r6,-524288(%r5,%r10)
+	ltg	%r6,-524288(%r5,%r10)
+	lbr	%r6,%r9
+	lgbr	%r6,%r9
+	lhr	%r6,%r9
+	lghr	%r6,%r9
+	lgfi	%r6,-2147483648
+	llc	%r6,-524288(%r5,%r10)
+	llcr	%r6,%r9
+	llgcr	%r6,%r9
+	llh	%r6,-524288(%r5,%r10)
+	llhr	%r6,%r9
+	llghr	%r6,%r9
+	llihf	%r6,4294967295
+	llilf	%r6,4294967295
+	oihf	%r6,4294967295
+	oilf	%r6,4294967295
+	slfi	%r6,4294967295
+	slgfi	%r6,4294967295
+	stfle	4095(%r5)
+	stckf	4095(%r5)
+	mvcos	4095(%r5),4095(%r10),%r6
+	lptea	%r6,%r9,%r5,15
+	sske	%r6,%r9,15
+	cu24	%r6,%r9,15
+	cu21	%r6,%r9,15
+	cu42	%r6,%r9,15
+	cu41	%r6,%r9,15
+	cu12	%r6,%r9,15
+	cu14	%r6,%r9,15
+	myr	%f6,%f9,%f5
+	myhr	%f6,%f9,%f5
+	mylr	%f6,%f9,%f5
+	my	%f6,%f9,4095(%r5,%r10)
+	myh	%f6,%f9,4095(%r5,%r10)
+	myl	%f6,%f9,4095(%r5,%r10)
+	mayr	%f6,%f9,%f5
+	mayhr	%f6,%f9,%f5
+	maylr	%f6,%f9,%f5
+	may	%f6,%f9,4095(%r5,%r10)
+	mayh	%f6,%f9,4095(%r5,%r10)
+	mayl	%f6,%f9,4095(%r5,%r10)
diff --git a/gas/testsuite/gas/s390/zarch-z900.d b/gas/testsuite/gas/s390/zarch-z900.d
new file mode 100644
index 000000000000..0f701282acf9
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z900.d
@@ -0,0 +1,152 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	e3 95 af ff 00 08 [ 	]*ag	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 18 [ 	]*agf	%r9,4095\(%r5,%r10\)
+.*:	b9 18 00 96 [ 	]*agfr	%r9,%r6
+.*:	a7 9b 80 01 [ 	]*aghi	%r9,-32767
+.*:	b9 08 00 96 [ 	]*agr	%r9,%r6
+.*:	e3 95 af ff 00 88 [ 	]*alcg	%r9,4095\(%r5,%r10\)
+.*:	b9 88 00 96 [ 	]*alcgr	%r9,%r6
+.*:	e3 95 af ff 00 0a [ 	]*alg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 1a [ 	]*algf	%r9,4095\(%r5,%r10\)
+.*:	b9 1a 00 96 [ 	]*algfr	%r9,%r6
+.*:	b9 0a 00 96 [ 	]*algr	%r9,%r6
+.*:	e3 95 af ff 00 46 [ 	]*bctg	%r9,4095\(%r5,%r10\)
+.*:	b9 46 00 96 [ 	]*bctgr	%r9,%r6
+.*:	a7 97 00 00 [	 ]*brctg	%r9,40 \<foo\+0x40\>
+.*:	ec 96 00 00 00 44 [ 	]*brxhg	%r9,%r6,44 <foo\+0x44>
+.*:	ec 96 00 00 00 45 [ 	]*brxlg	%r9,%r6,4a <foo\+0x4a>
+.*:	eb 96 5f ff 00 44 [ 	]*bxhg	%r9,%r6,4095\(%r5\)
+.*:	eb 96 5f ff 00 45 [ 	]*bxleg	%r9,%r6,4095\(%r5\)
+.*:	b3 a5 00 96 [ 	]*cdgbr	%r9,%r6
+.*:	b3 c5 00 96 [ 	]*cdgr	%r9,%r6
+.*:	eb 96 5f ff 00 3e [ 	]*cdsg	%r9,%r6,4095\(%r5\)
+.*:	b3 a4 00 96 [ 	]*cegbr	%r9,%r6
+.*:	b3 c4 00 96 [ 	]*cegr	%r9,%r6
+.*:	b3 b9 90 65 [	 ]*cfdr	%f6,9,%r5
+.*:	b3 b8 90 65 [	 ]*cfer	%f6,9,%r5
+.*:	b3 ba 90 65 [	 ]*cfxr	%f6,9,%r5
+.*:	e3 95 af ff 00 20 [ 	]*cg	%r9,4095\(%r5,%r10\)
+.*:	b3 a9 f0 65 [ 	]*cgdbr	%f6,15,%r5
+.*:	b3 c9 f0 65 [ 	]*cgdr	%f6,15,%r5
+.*:	b3 a8 f0 65 [ 	]*cgebr	%f6,15,%r5
+.*:	b3 c8 f0 65 [ 	]*cger	%f6,15,%r5
+.*:	e3 95 af ff 00 30 [ 	]*cgf	%r9,4095\(%r5,%r10\)
+.*:	b9 30 00 96 [ 	]*cgfr	%r9,%r6
+.*:	a7 9f 80 01 [ 	]*cghi	%r9,-32767
+.*:	b9 20 00 96 [ 	]*cgr	%r9,%r6
+.*:	b3 aa f0 65 [ 	]*cgxbr	%f6,15,%r5
+.*:	b3 ca f0 65 [ 	]*cgxr	%f6,15,%r5
+.*:	e3 95 af ff 00 21 [ 	]*clg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 31 [ 	]*clgf	%r9,4095\(%r5,%r10\)
+.*:	b9 31 00 96 [ 	]*clgfr	%r9,%r6
+.*:	b9 21 00 96 [ 	]*clgr	%r9,%r6
+.*:	eb 9a 5f ff 00 20 [ 	]*clmh	%r9,10,4095\(%r5\)
+.*:	eb 96 5f ff 00 30 [ 	]*csg	%r9,%r6,4095\(%r5\)
+.*:	e3 95 af ff 00 0e [ 	]*cvbg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 2e [ 	]*cvdg	%r9,4095\(%r5,%r10\)
+.*:	b3 a6 00 96 [ 	]*cxgbr	%r9,%r6
+.*:	b3 c6 00 96 [ 	]*cxgr	%r9,%r6
+.*:	e3 95 af ff 00 87 [ 	]*dlg	%r9,4095\(%r5,%r10\)
+.*:	b9 87 00 96 [ 	]*dlgr	%r9,%r6
+.*:	e3 95 af ff 00 0d [ 	]*dsg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 1d [ 	]*dsgf	%r9,4095\(%r5,%r10\)
+.*:	b9 1d 00 96 [ 	]*dsgfr	%r9,%r6
+.*:	b9 0d 00 96 [ 	]*dsgr	%r9,%r6
+.*:	b9 0e 00 96 [ 	]*eregg	%r9,%r6
+.*:	b9 9d 00 90 [ 	]*esea	%r9
+.*:	eb 9a 5f ff 00 80 [ 	]*icmh	%r9,10,4095\(%r5\)
+.*:	a5 90 ff ff [ 	]*iihh	%r9,65535
+.*:	a5 91 ff ff [ 	]*iihl	%r9,65535
+.*:	a5 92 ff ff [ 	]*iilh	%r9,65535
+.*:	a5 93 ff ff [ 	]*iill	%r9,65535
+.*:	b9 13 00 96 [ 	]*lcgfr	%r9,%r6
+.*:	b9 03 00 96 [ 	]*lcgr	%r9,%r6
+.*:	eb 96 5f ff 00 2f [ 	]*lctlg	%c9,%c6,4095\(%r5\)
+.*:	e3 95 af ff 00 04 [ 	]*lg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 14 [ 	]*lgf	%r9,4095\(%r5,%r10\)
+.*:	b9 14 00 96 [ 	]*lgfr	%r9,%r6
+.*:	e3 95 af ff 00 15 [ 	]*lgh	%r9,4095\(%r5,%r10\)
+.*:	a7 99 80 01 [ 	]*lghi	%r9,-32767
+.*:	b9 04 00 96 [ 	]*lgr	%r9,%r6
+.*:	e3 95 af ff 00 90 [ 	]*llgc	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 16 [ 	]*llgf	%r9,4095\(%r5,%r10\)
+.*:	b9 16 00 96 [ 	]*llgfr	%r9,%r6
+.*:	e3 95 af ff 00 91 [ 	]*llgh	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 17 [ 	]*llgt	%r9,4095\(%r5,%r10\)
+.*:	b9 17 00 96 [ 	]*llgtr	%r9,%r6
+.*:	a5 9c ff ff [ 	]*llihh	%r9,65535
+.*:	a5 9d ff ff [ 	]*llihl	%r9,65535
+.*:	a5 9e ff ff [ 	]*llilh	%r9,65535
+.*:	a5 9f ff ff [ 	]*llill	%r9,65535
+.*:	ef 96 5f ff af ff [ 	]*lmd	%r9,%r6,4095\(%r5\),4095\(%r10\)
+.*:	eb 96 5f ff 00 04 [ 	]*lmg	%r9,%r6,4095\(%r5\)
+.*:	eb 96 5f ff 00 96 [ 	]*lmh	%r9,%r6,4095\(%r5\)
+.*:	b9 11 00 96 [ 	]*lngfr	%r9,%r6
+.*:	b9 01 00 96 [ 	]*lngr	%r9,%r6
+.*:	b9 10 00 96 [ 	]*lpgfr	%r9,%r6
+.*:	b9 00 00 96 [ 	]*lpgr	%r9,%r6
+.*:	e3 95 af ff 00 8f [ 	]*lpq	%r9,4095\(%r5,%r10\)
+.*:	b2 b2 5f ff [ 	]*lpswe	4095\(%r5\)
+.*:	e3 95 af ff 00 03 [ 	]*lrag	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 0f [ 	]*lrvg	%r9,4095\(%r5,%r10\)
+.*:	b9 0f 00 96 [ 	]*lrvgr	%r9,%r6
+.*:	b9 12 00 96 [ 	]*ltgfr	%r9,%r6
+.*:	b9 02 00 96 [ 	]*ltgr	%r9,%r6
+.*:	b9 05 00 96 [ 	]*lurag	%r9,%r6
+.*:	a7 9d 80 01 [ 	]*mghi	%r9,-32767
+.*:	e3 95 af ff 00 86 [ 	]*mlg	%r9,4095\(%r5,%r10\)
+.*:	b9 86 00 96 [ 	]*mlgr	%r9,%r6
+.*:	e3 95 af ff 00 0c [ 	]*msg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 1c [ 	]*msgf	%r9,4095\(%r5,%r10\)
+.*:	b9 1c 00 96 [ 	]*msgfr	%r9,%r6
+.*:	b9 0c 00 96 [ 	]*msgr	%r9,%r6
+.*:	e3 95 af ff 00 80 [ 	]*ng	%r9,4095\(%r5,%r10\)
+.*:	b9 80 00 96 [ 	]*ngr	%r9,%r6
+.*:	a5 94 ff ff [ 	]*nihh	%r9,65535
+.*:	a5 95 ff ff [ 	]*nihl	%r9,65535
+.*:	a5 96 ff ff [ 	]*nilh	%r9,65535
+.*:	a5 97 ff ff [ 	]*nill	%r9,65535
+.*:	e3 95 af ff 00 81 [ 	]*og	%r9,4095\(%r5,%r10\)
+.*:	b9 81 00 96 [ 	]*ogr	%r9,%r6
+.*:	a5 98 ff ff [ 	]*oihh	%r9,65535
+.*:	a5 99 ff ff [ 	]*oihl	%r9,65535
+.*:	a5 9a ff ff [ 	]*oilh	%r9,65535
+.*:	a5 9b ff ff [ 	]*oill	%r9,65535
+.*:	eb 96 5f ff 00 1c [ 	]*rllg	%r9,%r6,4095\(%r5\)
+.*:	01 0e [ 	]*sam64
+.*:	e3 95 af ff 00 09 [ 	]*sg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 19 [ 	]*sgf	%r9,4095\(%r5,%r10\)
+.*:	b9 19 00 96 [ 	]*sgfr	%r9,%r6
+.*:	b9 09 00 96 [ 	]*sgr	%r9,%r6
+.*:	eb 96 5f ff 00 0b [ 	]*slag	%r9,%r6,4095\(%r5\)
+.*:	e3 95 af ff 00 89 [ 	]*slbg	%r9,4095\(%r5,%r10\)
+.*:	b9 89 00 96 [ 	]*slbgr	%r9,%r6
+.*:	e3 95 af ff 00 0b [ 	]*slg	%r9,4095\(%r5,%r10\)
+.*:	e3 95 af ff 00 1b [ 	]*slgf	%r9,4095\(%r5,%r10\)
+.*:	b9 1b 00 96 [ 	]*slgfr	%r9,%r6
+.*:	b9 0b 00 96 [ 	]*slgr	%r9,%r6
+.*:	eb 96 5f ff 00 0d [ 	]*sllg	%r9,%r6,4095\(%r5\)
+.*:	eb 96 5f ff 00 0a [ 	]*srag	%r9,%r6,4095\(%r5\)
+.*:	eb 96 5f ff 00 0c [ 	]*srlg	%r9,%r6,4095\(%r5\)
+.*:	eb 9a 5f ff 00 2c [ 	]*stcmh	%r9,10,4095\(%r5\)
+.*:	eb 96 5f ff 00 25 [ 	]*stctg	%c9,%c6,4095\(%r5\)
+.*:	e3 95 af ff 00 24 [ 	]*stg	%r9,4095\(%r5,%r10\)
+.*:	eb 96 5f ff 00 24 [ 	]*stmg	%r9,%r6,4095\(%r5\)
+.*:	eb 96 5f ff 00 26 [ 	]*stmh	%r9,%r6,4095\(%r5\)
+.*:	e3 95 af ff 00 8e [ 	]*stpq	%r9,4095\(%r5,%r10\)
+.*:	e5 00 5f ff 9f ff [ 	]*lasp	4095\(%r5\),4095\(%r9\)
+.*:	e3 95 af ff 00 2f [ 	]*strvg	%r9,4095\(%r5,%r10\)
+.*:	b9 25 00 96 [ 	]*sturg	%r9,%r6
+.*:	a7 92 ff ff [ 	]*tmhh	%r9,65535
+.*:	a7 93 ff ff [ 	]*tmhl	%r9,65535
+.*:	eb 96 5f ff 00 0f [ 	]*tracg	%r9,%r6,4095\(%r5\)
+.*:	e3 95 af ff 00 82 [ 	]*xg	%r9,4095\(%r5,%r10\)
+.*:	b9 82 00 96 [ 	]*xgr	%r9,%r6
+.*:	07 07 [	 ]*bcr	0,%r7
\ No newline at end of file
diff --git a/gas/testsuite/gas/s390/zarch-z900.s b/gas/testsuite/gas/s390/zarch-z900.s
new file mode 100644
index 000000000000..f5e737113c5e
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z900.s
@@ -0,0 +1,145 @@
+.text
+foo:
+	ag	%r9,4095(%r5,%r10)
+	agf	%r9,4095(%r5,%r10)
+	agfr	%r9,%r6
+	aghi	%r9,-32767
+	agr	%r9,%r6
+	alcg	%r9,4095(%r5,%r10)
+	alcgr	%r9,%r6
+	alg	%r9,4095(%r5,%r10)
+	algf	%r9,4095(%r5,%r10)
+	algfr	%r9,%r6
+	algr	%r9,%r6
+	bctg	%r9,4095(%r5,%r10)
+	bctgr	%r9,%r6
+	brctg	%r9,.
+	brxhg	%r9,%r6,.
+	brxlg	%r9,%r6,.
+	bxhg	%r9,%r6,4095(%r5)
+	bxleg	%r9,%r6,4095(%r5)
+	cdgbr	%r9,%r6
+	cdgr	%r9,%r6
+	cdsg	%r9,%r6,4095(%r5)
+	cegbr	%r9,%r6
+	cegr	%r9,%r6
+	cfdr	%f6,9,%r5
+	cfer	%f6,9,%r5
+	cfxr	%f6,9,%r5
+	cg	%r9,4095(%r5,%r10)
+	cgdbr	%f6,15,%r5
+	cgdr	%f6,15,%r5
+	cgebr	%f6,15,%r5
+	cger	%f6,15,%r5
+	cgf	%r9,4095(%r5,%r10)
+	cgfr	%r9,%r6
+	cghi	%r9,-32767
+	cgr	%r9,%r6
+	cgxbr	%f6,15,%r5
+	cgxr	%f6,15,%r5
+	clg	%r9,4095(%r5,%r10)
+	clgf	%r9,4095(%r5,%r10)
+	clgfr	%r9,%r6
+	clgr	%r9,%r6
+	clmh	%r9,10,4095(%r5)
+	csg	%r9,%r6,4095(%r5)
+	cvbg	%r9,4095(%r5,%r10)
+	cvdg	%r9,4095(%r5,%r10)
+	cxgbr	%r9,%r6
+	cxgr	%r9,%r6
+	dlg	%r9,4095(%r5,%r10)
+	dlgr	%r9,%r6
+	dsg	%r9,4095(%r5,%r10)
+	dsgf	%r9,4095(%r5,%r10)
+	dsgfr	%r9,%r6
+	dsgr	%r9,%r6
+	eregg	%r9,%r6
+	esea	%r9
+	icmh	%r9,10,4095(%r5)
+	iihh	%r9,65535
+	iihl	%r9,65535
+	iilh	%r9,65535
+	iill	%r9,65535
+	lcgfr	%r9,%r6
+	lcgr	%r9,%r6
+	lctlg	%c9,%c6,4095(%r5)
+	lg	%r9,4095(%r5,%r10)
+	lgf	%r9,4095(%r5,%r10)
+	lgfr	%r9,%r6
+	lgh	%r9,4095(%r5,%r10)
+	lghi	%r9,-32767
+	lgr	%r9,%r6
+	llgc	%r9,4095(%r5,%r10)
+	llgf	%r9,4095(%r5,%r10)
+	llgfr	%r9,%r6
+	llgh	%r9,4095(%r5,%r10)
+	llgt	%r9,4095(%r5,%r10)
+	llgtr	%r9,%r6
+	llihh	%r9,65535
+	llihl	%r9,65535
+	llilh	%r9,65535
+	llill	%r9,65535
+	lmd	%r9,%r6,4095(%r5),4095(%r10)
+	lmg	%r9,%r6,4095(%r5)
+	lmh	%r9,%r6,4095(%r5)
+	lngfr	%r9,%r6
+	lngr	%r9,%r6
+	lpgfr	%r9,%r6
+	lpgr	%r9,%r6
+	lpq	%r9,4095(%r5,%r10)
+	lpswe	4095(%r5)
+	lrag	%r9,4095(%r5,%r10)
+	lrvg	%r9,4095(%r5,%r10)
+	lrvgr	%r9,%r6
+	ltgfr	%r9,%r6
+	ltgr	%r9,%r6
+	lurag	%r9,%r6
+	mghi	%r9,-32767
+	mlg	%r9,4095(%r5,%r10)
+	mlgr	%r9,%r6
+	msg	%r9,4095(%r5,%r10)
+	msgf	%r9,4095(%r5,%r10)
+	msgfr	%r9,%r6
+	msgr	%r9,%r6
+	ng	%r9,4095(%r5,%r10)
+	ngr	%r9,%r6
+	nihh	%r9,65535
+	nihl	%r9,65535
+	nilh	%r9,65535
+	nill	%r9,65535
+	og	%r9,4095(%r5,%r10)
+	ogr	%r9,%r6
+	oihh	%r9,65535
+	oihl	%r9,65535
+	oilh	%r9,65535
+	oill	%r9,65535
+	rllg	%r9,%r6,4095(%r5)
+	sam64
+	sg	%r9,4095(%r5,%r10)
+	sgf	%r9,4095(%r5,%r10)
+	sgfr	%r9,%r6
+	sgr	%r9,%r6
+	slag	%r9,%r6,4095(%r5)
+	slbg	%r9,4095(%r5,%r10)
+	slbgr	%r9,%r6
+	slg	%r9,4095(%r5,%r10)
+	slgf	%r9,4095(%r5,%r10)
+	slgfr	%r9,%r6
+	slgr	%r9,%r6
+	sllg	%r9,%r6,4095(%r5)
+	srag	%r9,%r6,4095(%r5)
+	srlg	%r9,%r6,4095(%r5)
+	stcmh	%r9,10,4095(%r5)
+	stctg	%c9,%c6,4095(%r5)
+	stg	%r9,4095(%r5,%r10)
+	stmg	%r9,%r6,4095(%r5)
+	stmh	%r9,%r6,4095(%r5)
+	stpq	%r9,4095(%r5,%r10)
+	strag	4095(%r5),4095(%r9)
+	strvg	%r9,4095(%r5,%r10)
+	sturg	%r9,%r6
+	tmhh	%r9,65535
+	tmhl	%r9,65535
+	tracg	%r9,%r6,4095(%r5)
+	xg	%r9,4095(%r5,%r10)
+	xgr	%r9,%r6
diff --git a/gas/testsuite/gas/s390/zarch-z990.d b/gas/testsuite/gas/s390/zarch-z990.d
new file mode 100644
index 000000000000..f3d26314aa11
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z990.d
@@ -0,0 +1,132 @@
+#name: s390x opcode
+#objdump: -drw
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+.* <foo>:
+.*:	e3 65 a0 00 80 08 [	 ]*ag	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 18 [	 ]*agf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 7a [	 ]*ahy	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 98 [	 ]*alc	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 88 [	 ]*alcg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 0a [	 ]*alg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1a [	 ]*algf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 5e [	 ]*aly	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 5a [	 ]*ay	%r6,-524288\(%r5,%r10\)
+.*:	e3 60 50 00 80 46 [	 ]*bctg	%r6,-524288\(%r5\)
+.*:	eb 69 50 00 80 44 [	 ]*bxhg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 45 [	 ]*bxleg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 3e [	 ]*cdsg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 31 [	 ]*cdsy	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 20 [	 ]*cg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 30 [	 ]*cgf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 79 [	 ]*chy	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 8f [	 ]*clclu	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 21 [	 ]*clg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 31 [	 ]*clgf	%r6,-524288\(%r5,%r10\)
+.*:	eb ff 50 00 80 55 [	 ]*cliy	-524288\(%r5\),255
+.*:	eb 6f 50 00 80 20 [	 ]*clmh	%r6,15,-524288\(%r5\)
+.*:	eb 6f 50 00 80 21 [	 ]*clmy	%r6,15,-524288\(%r5\)
+.*:	e3 65 a0 00 80 55 [	 ]*cly	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 30 [	 ]*csg	%r6,%r9,-524288\(%r5\)
+.*:	b9 8a 00 69 [	 ]*cspg	%r6,%r9
+.*:	eb 69 50 00 80 14 [	 ]*csy	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 0e [	 ]*cvbg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 06 [	 ]*cvby	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 2e [	 ]*cvdg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 26 [	 ]*cvdy	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 59 [	 ]*cy	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 97 [	 ]*dl	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 87 [	 ]*dlg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 0d [	 ]*dsg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1d [	 ]*dsgf	%r6,-524288\(%r5,%r10\)
+.*:	eb 6f 50 00 80 80 [	 ]*icmh	%r6,15,-524288\(%r5\)
+.*:	eb 6f 50 00 80 81 [	 ]*icmy	%r6,15,-524288\(%r5\)
+.*:	e3 65 a0 00 80 73 [	 ]*icy	%r6,-524288\(%r5,%r10\)
+.*:	b9 8e 50 69 [	 ]*idte	%r6,%r9,%r5
+.*:	eb 69 50 00 80 9a [	 ]*lamy	%a6,%a9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 71 [	 ]*lay	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 76 [	 ]*lb	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 2f [	 ]*lctlg	%c6,%c9,-524288\(%r5\)
+.*:	ed 65 a0 00 80 65 [	 ]*ldy	%f6,-524288\(%r5,%r10\)
+.*:	ed 65 a0 00 80 64 [	 ]*ley	%f6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 04 [	 ]*lg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 77 [	 ]*lgb	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 14 [	 ]*lgf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 15 [	 ]*lgh	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 78 [	 ]*lhy	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 90 [	 ]*llgc	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 16 [	 ]*llgf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 91 [	 ]*llgh	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 17 [	 ]*llgt	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 04 [	 ]*lmg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 96 [	 ]*lmh	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 98 [	 ]*lmy	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 8f [	 ]*lpq	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 03 [	 ]*lrag	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 13 [	 ]*lray	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1e [	 ]*lrv	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 0f [	 ]*lrvg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1f [	 ]*lrvh	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 58 [	 ]*ly	%r6,-524288\(%r5,%r10\)
+.*:	ed 95 af ff 60 3e [	 ]*mad	%f6,%f9,4095\(%r5,%r10\)
+.*:	b3 3e 60 95 [	 ]*madr	%f6,%f9,%f5
+.*:	ed 95 af ff 60 2e [	 ]*mae	%f6,%f9,4095\(%r5,%r10\)
+.*:	b3 2e 60 95 [	 ]*maer	%f6,%f9,%f5
+.*:	e3 65 a0 00 80 96 [	 ]*ml	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 86 [	 ]*mlg	%r6,-524288\(%r5,%r10\)
+.*:	ed 95 af ff 60 3f [	 ]*msd	%f6,%f9,4095\(%r5,%r10\)
+.*:	b3 3f 60 95 [	 ]*msdr	%f6,%f9,%f5
+.*:	ed 95 af ff 60 2f [	 ]*mse	%f6,%f9,4095\(%r5,%r10\)
+.*:	b3 2f 60 95 [	 ]*mser	%f6,%f9,%f5
+.*:	e3 65 a0 00 80 0c [	 ]*msg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1c [	 ]*msgf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 51 [	 ]*msy	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 8e [	 ]*mvclu	%r6,%r9,-524288\(%r5\)
+.*:	eb ff 50 00 80 52 [	 ]*mviy	-524288\(%r5\),255
+.*:	e3 65 a0 00 80 80 [	 ]*ng	%r6,-524288\(%r5,%r10\)
+.*:	eb ff 50 00 80 54 [	 ]*niy	-524288\(%r5\),255
+.*:	e3 65 a0 00 80 54 [	 ]*ny	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 81 [	 ]*og	%r6,-524288\(%r5,%r10\)
+.*:	eb ff 50 00 80 56 [	 ]*oiy	-524288\(%r5\),255
+.*:	e3 65 a0 00 80 56 [	 ]*oy	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 1d [	 ]*rll	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 1c [	 ]*rllg	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 09 [	 ]*sg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 19 [	 ]*sgf	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 7b [	 ]*shy	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 0b [	 ]*slag	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 99 [	 ]*slb	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 89 [	 ]*slbg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 0b [	 ]*slg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 1b [	 ]*slgf	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 0d [	 ]*sllg	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 5f [	 ]*sly	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 0a [	 ]*srag	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 0c [	 ]*srlg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 9b [	 ]*stamy	%a6,%a9,-524288\(%r5\)
+.*:	eb 6f 50 00 80 2c [	 ]*stcmh	%r6,15,-524288\(%r5\)
+.*:	eb 6f 50 00 80 2d [	 ]*stcmy	%r6,15,-524288\(%r5\)
+.*:	eb 69 50 00 80 25 [	 ]*stctg	%c6,%c9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 72 [	 ]*stcy	%r6,-524288\(%r5,%r10\)
+.*:	ed 65 a0 00 80 67 [	 ]*stdy	%f6,-524288\(%r5,%r10\)
+.*:	ed 65 a0 00 80 66 [	 ]*stey	%f6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 24 [	 ]*stg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 70 [	 ]*sthy	%r6,-524288\(%r5,%r10\)
+.*:	eb 69 50 00 80 24 [	 ]*stmg	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 26 [	 ]*stmh	%r6,%r9,-524288\(%r5\)
+.*:	eb 69 50 00 80 90 [	 ]*stmy	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 8e [	 ]*stpq	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 3e [	 ]*strv	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 2f [	 ]*strvg	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 3f [	 ]*strvh	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 50 [	 ]*sty	%r6,-524288\(%r5,%r10\)
+.*:	e3 65 a0 00 80 5b [	 ]*sy	%r6,-524288\(%r5,%r10\)
+.*:	eb ff 50 00 80 51 [	 ]*tmy	-524288\(%r5\),255
+.*:	eb 69 50 00 80 0f [	 ]*tracg	%r6,%r9,-524288\(%r5\)
+.*:	e3 65 a0 00 80 82 [	 ]*xg	%r6,-524288\(%r5,%r10\)
+.*:	eb ff 50 00 80 57 [	 ]*xiy	-524288\(%r5\),255
+.*:	e3 65 a0 00 80 57 [	 ]*xy	%r6,-524288\(%r5,%r10\)
+.*:	07 07 [	 ]*bcr	0,%r7
diff --git a/gas/testsuite/gas/s390/zarch-z990.s b/gas/testsuite/gas/s390/zarch-z990.s
new file mode 100644
index 000000000000..3a555a98014d
--- /dev/null
+++ b/gas/testsuite/gas/s390/zarch-z990.s
@@ -0,0 +1,125 @@
+.text
+foo:
+	ag	%r6,-524288(%r5,%r10)
+	agf	%r6,-524288(%r5,%r10)
+	ahy	%r6,-524288(%r5,%r10)
+	alc	%r6,-524288(%r5,%r10)
+	alcg	%r6,-524288(%r5,%r10)
+	alg	%r6,-524288(%r5,%r10)
+	algf	%r6,-524288(%r5,%r10)
+	aly	%r6,-524288(%r5,%r10)
+	ay	%r6,-524288(%r5,%r10)
+	bctg	%r6,-524288(%r5)
+	bxhg	%r6,%r9,-524288(%r5)
+	bxleg	%r6,%r9,-524288(%r5)
+	cdsg	%r6,%r9,-524288(%r5)
+	cdsy	%r6,%r9,-524288(%r5)
+	cg	%r6,-524288(%r5,%r10)
+	cgf	%r6,-524288(%r5,%r10)
+	chy	%r6,-524288(%r5,%r10)
+	clclu	%r6,%r9,-524288(%r5)
+	clg	%r6,-524288(%r5,%r10)
+	clgf	%r6,-524288(%r5,%r10)
+	cliy	-524288(%r5),255
+	clmh	%r6,15,-524288(%r5)
+	clmy	%r6,15,-524288(%r5)
+	cly	%r6,-524288(%r5,%r10)
+	csg	%r6,%r9,-524288(%r5)
+	cspg	%r6,%r9
+	csy	%r6,%r9,-524288(%r5)
+	cvbg	%r6,-524288(%r5,%r10)
+	cvby	%r6,-524288(%r5,%r10)
+	cvdg	%r6,-524288(%r5,%r10)
+	cvdy	%r6,-524288(%r5,%r10)
+	cy	%r6,-524288(%r5,%r10)
+	dl	%r6,-524288(%r5,%r10)
+	dlg	%r6,-524288(%r5,%r10)
+	dsg	%r6,-524288(%r5,%r10)
+	dsgf	%r6,-524288(%r5,%r10)
+	icmh	%r6,15,-524288(%r5)
+	icmy	%r6,15,-524288(%r5)
+	icy	%r6,-524288(%r5,%r10)
+	idte	%r6,%r9,%r5
+	lamy	%a6,%a9,-524288(%r5)
+	lay	%r6,-524288(%r5,%r10)
+	lb	%r6,-524288(%r5,%r10)
+	lctlg	%c6,%c9,-524288(%r5)
+	ldy	%f6,-524288(%r5,%r10)
+	ley	%f6,-524288(%r5,%r10)
+	lg	%r6,-524288(%r5,%r10)
+	lgb	%r6,-524288(%r5,%r10)
+	lgf	%r6,-524288(%r5,%r10)
+	lgh	%r6,-524288(%r5,%r10)
+	lhy	%r6,-524288(%r5,%r10)
+	llgc	%r6,-524288(%r5,%r10)
+	llgf	%r6,-524288(%r5,%r10)
+	llgh	%r6,-524288(%r5,%r10)
+	llgt	%r6,-524288(%r5,%r10)
+	lmg	%r6,%r9,-524288(%r5)
+	lmh	%r6,%r9,-524288(%r5)
+	lmy	%r6,%r9,-524288(%r5)
+	lpq	%r6,-524288(%r5,%r10)
+	lrag	%r6,-524288(%r5,%r10)
+	lray	%r6,-524288(%r5,%r10)
+	lrv	%r6,-524288(%r5,%r10)
+	lrvg	%r6,-524288(%r5,%r10)
+	lrvh	%r6,-524288(%r5,%r10)
+	ly	%r6,-524288(%r5,%r10)
+	mad	%f6,%f9,4095(%r5,%r10)
+	madr	%f6,%f9,%f5
+	mae	%f6,%f9,4095(%r5,%r10)
+	maer	%f6,%f9,%f5
+	ml	%r6,-524288(%r5,%r10)
+	mlg	%r6,-524288(%r5,%r10)
+	msd	%f6,%f9,4095(%r5,%r10)
+	msdr	%f6,%f9,%f5
+	mse	%f6,%f9,4095(%r5,%r10)
+	mser	%f6,%f9,%f5
+	msg	%r6,-524288(%r5,%r10)
+	msgf	%r6,-524288(%r5,%r10)
+	msy	%r6,-524288(%r5,%r10)
+	mvclu	%r6,%r9,-524288(%r5)
+	mviy	-524288(%r5),255
+	ng	%r6,-524288(%r5,%r10)
+	niy	-524288(%r5),255
+	ny	%r6,-524288(%r5,%r10)
+	og	%r6,-524288(%r5,%r10)
+	oiy	-524288(%r5),255
+	oy	%r6,-524288(%r5,%r10)
+	rll	%r6,%r9,-524288(%r5)
+	rllg	%r6,%r9,-524288(%r5)
+	sg	%r6,-524288(%r5,%r10)
+	sgf	%r6,-524288(%r5,%r10)
+	shy	%r6,-524288(%r5,%r10)
+	slag	%r6,%r9,-524288(%r5)
+	slb	%r6,-524288(%r5,%r10)
+	slbg	%r6,-524288(%r5,%r10)
+	slg	%r6,-524288(%r5,%r10)
+	slgf	%r6,-524288(%r5,%r10)
+	sllg	%r6,%r9,-524288(%r5)
+	sly	%r6,-524288(%r5,%r10)
+	srag	%r6,%r9,-524288(%r5)
+	srlg	%r6,%r9,-524288(%r5)
+	stamy	%a6,%a9,-524288(%r5)
+	stcmh	%r6,15,-524288(%r5)
+	stcmy	%r6,15,-524288(%r5)
+	stctg	%c6,%c9,-524288(%r5)
+	stcy	%r6,-524288(%r5,%r10)
+	stdy	%f6,-524288(%r5,%r10)
+	stey	%f6,-524288(%r5,%r10)
+	stg	%r6,-524288(%r5,%r10)
+	sthy	%r6,-524288(%r5,%r10)
+	stmg	%r6,%r9,-524288(%r5)
+	stmh	%r6,%r9,-524288(%r5)
+	stmy	%r6,%r9,-524288(%r5)
+	stpq	%r6,-524288(%r5,%r10)
+	strv	%r6,-524288(%r5,%r10)
+	strvg	%r6,-524288(%r5,%r10)
+	strvh	%r6,-524288(%r5,%r10)
+	sty	%r6,-524288(%r5,%r10)
+	sy	%r6,-524288(%r5,%r10)
+	tmy	-524288(%r5),255
+	tracg	%r6,%r9,-524288(%r5)
+	xg	%r6,-524288(%r5,%r10)
+	xiy	-524288(%r5),255
+	xy	%r6,-524288(%r5,%r10)
diff --git a/gas/testsuite/gas/sh/arch/arch.exp b/gas/testsuite/gas/sh/arch/arch.exp
new file mode 100644
index 000000000000..1f378f38d082
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/arch.exp
@@ -0,0 +1,515 @@
+# Copyright (C) 2004, 2005
+# Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
+
+# Please email any bugs, comments, and/or additions to this file to:
+# binutils@sources.redhat.com
+
+# This scripts tests all available SH architectures with all the assembler
+# options related to the architecture. It ensures that those combinations
+# which should not work do not work, and that those that should work
+# produce the correct output architecture.
+#
+# It looks for files in the same directory as this file named sh*.s .
+# Each file must contain all the instructions available within
+# that architecture. The architecture name is inferred from the file name.
+#
+# The sh*.s files should NOT be hand edited. Whenever the script is run
+# (e.g. with 'make check') it creates a set of new (usually identical) files
+# in the <objdir>/gas/testsuite directory. These are compared against the
+# old ones in the testsuite. When the expected results change (or new
+# architectures are added) these new files can be used to replace the old
+# ones with no modification required.
+#
+# The script generates the architecture/option permutations automatically,
+# but it reads the expected results from the file arch_expected.txt (also
+# found in the same directory as this script).
+#
+# The arch_expected.txt file should NOT be hand edited. Whenever the script
+# is run (e.g. with 'make check') it creates a new (usually identical) file
+# named arch_results.txt in the <objdir>/gas/testsuite directory. When the
+# expected results change (or new architectures are added) this new file
+# can be used to replace arch_expected.txt with no modification required.
+
+if {[istarget sh*-*-*]} then {
+
+
+# This procedure extracts the architecture name from the objdump output.
+# If there is no architecture name (or objdump output changes significantly)
+# then the behaviour is undefined, but it will most likely return junk.
+
+proc get_sh_arch { ofile } {
+    global comp_output
+
+    objdump "-f $ofile"
+    send_log $comp_output
+
+    set comp_output [string replace $comp_output 0 \
+	    [expr [string first "architecture:" $comp_output] + 13] ""]
+
+    return [string range $comp_output 0 [expr [string first "," $comp_output] - 1]]
+}
+
+
+# This procedure runs two tests:
+#   Test 1: Check the assembler can assemble the given file with
+#           given options.
+#   Test 2: Check that the resultant architecture is as expected.
+# It also writes an entry to the arch_results.txt file.
+
+proc test_arch { file opt arch resultfile } {
+    global comp_output
+
+    set name [file tail $file]
+    set rootname [file rootname $name]
+
+    if [string equal $opt "default-options"] then {
+	gas_run $name "-o ${rootname}-#${opt}#.o" ""
+    } else {
+	gas_run $name "$opt -o ${rootname}-#${opt}#.o" ""
+    }
+
+    if [want_no_output "$rootname file should assemble with $opt"] then {
+	set result [get_sh_arch "${rootname}-#${opt}#.o"]
+	puts $resultfile [format "%-20s %-25s %s" $file $opt $result]
+
+	if {$result == $arch} then {
+	    pass "$rootname file with $opt should assemble to arch $arch"
+	    file delete "${rootname}-#${opt}#.o"
+	} else {
+	    send_log $comp_output
+	    fail "$rootname file with $opt should assemble to arch $arch"
+	}
+    } else {
+	puts $resultfile [format "%-20s %-25s ERROR" $file $opt]
+	untested "$rootname file with $opt should assemble to arch $arch"
+    }
+
+}
+
+
+# This procedure tests that a file that is not suposed to assemble
+# with a given option does, in fact, not assemble.
+# It also writes an entry to the arch_results.txt file.
+
+proc test_arch_error { file opt resultfile} {
+    global comp_output
+
+    set name [file tail $file]
+    set rootname [file rootname $name]
+
+    if [string equal $opt "default-options"] then {
+	gas_run $name "-o ${rootname}-#${opt}#.o" ""
+    } else {
+	gas_run $name "$opt -o ${rootname}-#${opt}#.o" ""
+    }
+
+    if [string match "" $comp_output] then {
+	fail "$rootname file with $opt should not assemble"
+	puts $resultfile [format "%-20s %-25s [get_sh_arch ${rootname}-#${opt}#.o]" $file $opt]
+    } else {
+	pass "$rootname file with $opt should not assemble"
+	puts $resultfile [format "%-20s %-25s ERROR" $file $opt]
+    }
+}   
+
+# These tests are not suitable for sh-coff because
+# coff does not store the architecture information.
+
+if [istarget sh*-*-elf] then {
+    global subdir srcdir
+
+    # Find all the architectures and generate the
+    # list of options we will test.
+
+    set filelist [lsort -ascii [glob "$srcdir/$subdir/sh*.s"]]
+    set optlist {"default-options" "-dsp" "-isa=any" "-isa=dsp" "-isa=fp"}
+    foreach file $filelist {
+	set arch [file rootname [file tail $file]]
+	lappend optlist "-isa=$arch" "-isa=${arch}-up"
+    }
+
+    # Initialise the results file
+
+    set outfile [open "arch_results.txt" w 0666]
+    puts $outfile "# Generated file. DO NOT EDIT"
+    puts $outfile "#"
+    puts $outfile "# This file is generated by gas/testsuite/gas/sh/arch/arch.exp ."
+    puts $outfile "# It contains the expected results of the tests."
+    puts $outfile "# If the tests are failing because the expected results"
+    puts $outfile "# have changed then run 'make check' and copy the new file"
+    puts $outfile "# from <objdir>/gas/testsuite/arch_results.txt"
+    puts $outfile "# to   <srcdir>/gas/testsuite/gas/sh/arch/arch_expected.txt ."
+    puts $outfile "# Make sure the new expected results are ALL correct."
+    puts $outfile "#"
+    puts $outfile [format "# %-18s %-25s %s" "FILE" "OPTION" "OUTPUT"]
+    puts $outfile [format "# %-18s %-25s %s" "----" "------" "------"]
+
+    # Open the expected results file and skip the header
+
+    set infile [open "$srcdir/$subdir/arch_expected.txt" r]
+    while {[gets $infile line] >= 0 && [string match {\#*} $line]} {send_log "reading '$line'\n"}
+
+    foreach file $filelist {
+	foreach opt $optlist {
+	    set name [file tail $file]
+	    set rootname [file rootname $name]
+
+	    # Decode the expected result from the file
+
+	    scan $line "%s %s %s" exfile exopt exarch
+	    send_log "exfile = '$exfile', exopt = '$exopt', exarch = '$exarch'\n"
+	    send_log "  name = '$name',   opt = '$opt'\n"
+
+	    if {[string equal $exfile $name] && [string equal $exopt $opt]} then {
+		# The expected result file makes sense and
+		# appears up-to-date (the file and options match)
+
+		if {[string equal $exarch "ERROR"]} then {
+		    test_arch_error $name $opt $outfile
+		} else {
+		    test_arch $name $opt $exarch $outfile
+		}
+	    } else {
+		# The expected result file isn't right somehow
+		# so just try any old test. This will cause
+		# many failures, but will generate the results file.
+
+		test_arch $name $opt $rootname $outfile
+	    }
+
+	    # Read the next line from the expected result file.
+	    # This is at the end because the process of skipping
+	    # the header reads the first real line
+
+	    if [gets $infile line] then {
+		send_log "reading '$line'\n"
+	    }
+	}
+    }
+
+    close $infile
+    close $outfile
+}
+
+
+#########################################################################
+# Generate one sh*.s file for each architecture defined in sh-opc.h
+# This will contain all the instructions valid on that platform
+#
+# This code produces pass or fail reports for each instruction
+# in order to ensure that problems are visible to the developer,
+# rather than just warnings hidden in the log file.
+
+# These variables will contains the architecture
+# and instruction data extracted from sh-opc.h
+array set arches {}
+set archcount 0
+array set insns {}
+set insncount 0
+
+# Pull the architecture inheritance macros out of sh-opc.h
+# Pull all the insns out of the sh-opc.h file.
+send_log "Reading sh-opc.h\n"
+send_log "--------------------------------------------------------\n"
+spawn -noecho cat "$srcdir/../../opcodes/sh-opc.h"   ;# -open doesn't seem to be reliable
+expect {
+    -re {#define\s+arch_([^ ]*)_up\s*\(([^)]*)\)} {
+	set arches($archcount) [string map {_ -} $expect_out(1,string)]
+	set arches($archcount,descendents) [string map {_ -} $expect_out(2,string)]
+	incr archcount
+	pass "Architecture arch_$expect_out(1,string) read OK"
+	exp_continue
+    }
+    # Match all 32 bit opcodes
+    -re {(?x)           # enable expanded regexp syntax
+         ^/\*           # open C comment at start of input
+         (?:\s*\S+){2}  #   2 binary words (for 32 bit opcodes)
+     \s+ ([^*]+?)       #   instruction mnemonics (must not leave comment)
+     \s* \*/            # close C comment
+     \s* \{             # open brace of data initialiser
+	 (?:[^\}]+\}){2}#   2 brace pairs (operands and nibbles)
+     \s* ,              #   comma
+     \s* arch_(\S+)_up  #   architecture name
+     \s* \|             #   literal or
+     \s* arch_op32      #   32 bit opcode indicator
+     \s* \}             # close brace of data initialiser
+	} {
+	    set insns(insn,$insncount) $expect_out(1,string)
+	    set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
+	    set insns(context,$insncount) $expect_out(0,string)
+	    incr insncount
+	    pass "Instruction '$expect_out(1,string)' read OK"
+	    exp_continue
+	}
+    # Special case: Match the repeat pseudo op
+    -re {(?x)           # enable expanded regexp syntax
+	 ^/\*           # open C comment at start of input
+     \s* repeat         #   repeat does not have a bit pattern
+     \s+ start\s+end    #   don't read fake operands as such (replaced below)
+     \s+ ([^*]+?)       #   instruction operand
+     \s* \*/            # close C comment
+     \s* \{             # open brace of data initialiser
+	 (?:[^\}]+\}){2}#   2 brace pairs (operands and nibbles)
+     \s* ,              #   comma
+     \s* arch_(\S+)_up  #   architecture name
+     \s* \}             # close brace of data initialiser
+        } {
+	    set insns(insn,$insncount) "repeat 10 20 $expect_out(1,string)"
+	    set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
+	    set insns(context,$insncount) $expect_out(0,string)
+	    incr insncount
+	    pass "Instruction '$expect_out(1,string)' read OK"
+	    exp_continue
+	}
+    # Match all 16 bit opcodes
+    -re {(?x)           # enable expanded regexp syntax
+         ^/\*           # open C comment at start of input
+     \s* \S+            #   1 binary word (for 16 bit opcodes)
+     \s+ ([^*]+?)       #   instruction mnemonics (must not leave comment)
+     \s* \*/            # close C comment
+     \s* \{             # open brace of data initialiser
+	 (?:[^\}]+\}){2}#   2 brace pairs (operands and nibbles)
+     \s* ,              #   comma
+     \s* arch_(\S+)_up  #   architecture name
+     \s* \}             # close brace of data initialiser
+	} {
+	    set insns(insn,$insncount) $expect_out(1,string)
+	    set insns(arch,$insncount) [string map {_ -} $expect_out(2,string)]
+	    set insns(context,$insncount) $expect_out(0,string)
+	    incr insncount
+	    pass "Instruction '$expect_out(1,string)' read OK"
+	    exp_continue
+	}
+    # Match all remaining possible instructions (error detection)
+    -re {(?x)           # enable expanded regexp syntax
+	 ^/\*           # open C comment at start of input
+	 (?:[^*]*(?:\*[^/])?)+ # match contents of comment allowing *
+	 \*/            # close C comment
+     \s* \{             # open brace of data initialiser
+	 (?:[^\}]+\}){2}#   2 brace pairs (operands and nibbles)
+     \s* ,              #   comma
+	 [^\}]*
+	 arch           #   look for 'arch' anywhere before closing brace
+	 [^\}]*
+	 \}             # close brace of data initialiser
+        } {
+	    fail "Found something that looks like an instruction but cannot be decoded:\n\t$expect_out(0,string)"
+	    exp_continue
+	}
+    # No match so move to next (possible) comment
+    -re {^.+?((?=/\*)|(?=\#\s*define))} exp_continue
+}
+send_log "--------------------------------------------------------\n"
+
+if {$archcount == 0} then {
+    fail "Unable to read any architectures from sh-opc.h"
+} else {
+    pass "Read architecture data from sh-opc.h"
+}
+if {$insncount == 0} then {
+    fail "Unable to read any instructions from sh-opc.h"
+} else {
+    pass "Read instruction data from sh-opc.h"
+}
+
+# Munge the insns such that they will assemble
+# Each instruction in sh-opc.h has an example format
+# with placeholders for the parameters. These placeholders
+# need to be replaced with real registers and constants
+# as appropriate in order to assemble correctly.
+for {set i 0} {$i < $insncount} {incr i} {
+    set out $insns(insn,$i)
+    if {[regexp {AY_.{3,4}_N} $insns(context,$i)] == 1} then {
+	regsub -nocase {<REG_N>} $out {r6} out
+    } else {
+	regsub -nocase {<REG_N>} $out {r4} out
+    }
+    regsub -nocase {<REG_M>} $out {r5} out
+    if {[regexp {IMM0_20BY8} $insns(context,$i)] == 1} then {
+	regsub -nocase {<imm>} $out {1024} out
+    } else {
+	regsub -nocase {<imm>} $out {4} out
+    }
+    regsub -nocase {<bdisp\d*>} $out {.+8} out
+    regsub -nocase {<disp12>} $out {2048} out
+    regsub -nocase {<disp\d*>} $out {8} out
+    regsub -nocase {Rn_BANK} $out {r1_bank} out
+    regsub -nocase {Rm_BANK} $out {r2_bank} out
+    regsub -nocase {<F_REG_N>} $out {fr1} out
+    regsub -nocase {<F_REG_M>} $out {fr2} out
+    regsub -nocase {<D_REG_N>} $out {dr2} out
+    regsub -nocase {<D_REG_M>} $out {dr4} out
+    regsub -nocase {<V_REG_N>} $out {fv0} out
+    regsub -nocase {<V_REG_M>} $out {fv4} out
+    regsub -nocase {<DX_REG_N>} $out {xd2} out
+    regsub -nocase {<DX_REG_M>} $out {xd4} out
+    regsub -nocase (XMTRX_M4) $out {xmtrx} out
+    regsub -nocase (<DSP_REG_X>) $out {x1} out
+    regsub -nocase (<DSP_REG_Y>) $out {y0} out
+    regsub -nocase (<DSP_REG_M>) $out {a1} out
+    regsub -nocase (<DSP_REG_N>) $out {m0} out
+    regsub -nocase (<REG_Axy>) $out {r1} out
+    regsub -nocase (<REG_Ayx>) $out {r3} out
+    regsub -nocase (<DSP_REG_XY>) $out {y1} out
+    regsub -nocase (<DSP_REG_YX>) $out {y1} out
+    regsub -nocase (<DSP_REG_AX>) $out {a0} out
+    regsub -nocase (<DSP_REG_AY>) $out {a0} out
+    regsub (Se) $out {x0} out
+    regsub (Sf) $out {y0} out
+    regsub (Dg) $out {m0} out
+    # Put in a dct in order to differentiate between
+    # conditional and non-conditional pabs and prnd
+    # i.e. between sh-dsp and sh4al-dsp
+    if {[regexp {PPIC} $insns(context,$i)] == 1} then {
+	set out "dct $out"
+    }
+    set insns(insn,$i) $out
+    set insns(context,$i) [string map {\n " " \r " "} $insns(context,$i)]
+}
+
+# Initialise the data structure for the inheritance
+array set archtree {}
+for {set a 0} {$a < $archcount} {incr a} {
+    set archtree($arches($a)) {}
+}
+
+# For each architecture, extract its immediate parents
+for {set a 0} {$a < $archcount} {incr a} {
+    set s $arches($a,descendents)
+    regsub -all {[\s|]+} $s { } s
+    foreach word [split $s { }] {
+	# Word should be one of arch-..., | (or), or arch-...-up
+	# We only want the -up information
+	# Note that the _ -> - translation was done above
+	if {[regexp {^arch-(.*)-up$} $word match arch] == 1} then {
+	    # $arch is the descendent of $arches($a),
+	    # so $arches($a) is the parent of $arch
+	    lappend archtree($arch) $arches($a)
+	}
+    }
+}
+
+# Propagate the inhertances through the list
+# Iterate to ensure all inheritances are found (necessary?)
+set changesmade 1
+while {$changesmade == 1} {
+    set changesmade 0
+    foreach a [array names archtree] {
+	foreach b [array names archtree] {
+	    # If arch 'a' is a parent of arch 'b' then b inherits from a
+	    if {[lsearch -exact $archtree($b) $a] != -1} then {
+		# Only add each arch if it is not already present
+		foreach arch $archtree($a) {
+		    if {[lsearch -exact $archtree($b) $arch] == -1} then {
+			lappend archtree($b) $arch
+			set changesmade 1
+		    }
+		}
+	    }
+	}
+    }
+}
+
+# Generate the assembler file for each architecture
+# Also count up how many instructions should be valid for each architecture
+array set insns_valid {}
+for {set arch 0} {$arch < $archcount} {incr arch} {
+    set insns_valid($arches($arch)) 0
+    set fd [open $arches($arch).s w 0666]
+    puts $fd "! Generated file. DO NOT EDIT.\n!"
+    puts $fd "! This file was generated by gas/testsuite/gas/sh/arch/arch.exp ."
+    puts $fd "! This file should contain every instruction valid on"
+    puts $fd "! architecture $arches($arch) but no more."
+    puts $fd "! If the tests are failing because the expected results"
+    puts $fd "! have changed then run 'make check' and copy the new file"
+    puts $fd "! from <objdir>/gas/testsuite/$arches($arch).s"
+    puts $fd "! to   <srcdir>/gas/testsuite/gas/sh/arch/$arches($arch).s ."
+    puts $fd "! Make sure there are no unexpected or missing instructions."
+    puts $fd "\n\t.section .text"
+    puts $fd "[string map {- _} $arches($arch)]:"
+    puts $fd "! Instructions introduced into $arches($arch)"
+    for {set i 0} {$i < $insncount} {incr i} {
+	if [string equal $arches($arch) $insns(arch,$i)] then {
+	    puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
+	    incr insns_valid($arches($arch))
+	}
+    }
+    puts $fd "\n! Instructions inherited from ancestors: [lsort -increasing $archtree($arches($arch))]"
+    for {set i 0} {$i < $insncount} {incr i} {
+	if {[string equal $arches($arch) $insns(arch,$i)] != 1 && [lsearch -exact $archtree($arches($arch)) $insns(arch,$i)] != -1} then {
+	    puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
+	    incr insns_valid($arches($arch))
+	}
+    }
+    close $fd
+}
+
+
+###################################################################
+# Compare the newly created sh*.s files with the existing
+# ones in the testsuite
+
+for {set arch 0} {$arch < $archcount} {incr arch} {
+    send_log "diff $srcdir/$subdir/$arches($arch).s $arches($arch).s\n"
+    catch "exec diff $srcdir/$subdir/$arches($arch).s $arches($arch).s" diff_output
+    if {[string equal $diff_output ""] == 0} then {
+	send_log $diff_output
+	fail "Check $arches($arch) architecture has not changed"
+    } else {
+	pass "Check $arches($arch) architecture has not changed"
+    }
+}
+
+
+###################################################################
+# Generate an assembler file with every instruction
+# Then use it to test how many failures there are for
+# each architecture. If this does not match the predicted value
+# then the assembler accepts too many instructions for a given
+# architecture.
+
+
+set fd [open "all_insns.s" w 0666]
+for {set i 0} {$i < $insncount} {incr i} {
+    puts $fd [format "\t%-25s ;!%s" $insns(insn,$i) $insns(context,$i)]
+}
+close $fd
+
+# Assemble the all_insns.s file for each isa and count how many failures there are
+foreach arch [array names insns_valid] {
+    set errormessages 0
+    set expected [expr $insncount - $insns_valid($arch)]
+
+    # The -Z option ensures that all error messages are output,
+    # even those from later phases of assembly (such as offset range errors)
+    send_log "$AS -Z -isa=$arch all_insns.s -o /dev/null\n"
+    spawn $AS -Z -isa=$arch all_insns.s -o /dev/null
+    expect Error: {incr errormessages; exp_continue}
+
+    if {$errormessages == $expected} then {
+	pass "$expected insns should not assemble on $arch"
+    } else {
+	if {([istarget sh*-*-coff] || [istarget sh*-hms]) && [string match {*dsp} $arch]} {
+	    xfail "$expected insns should not assemble on $arch ($errormessages did not)"
+	} else {
+	    fail "$expected insns should not assemble on $arch ($errormessages did not)"
+	}
+    }
+}
+
+
+} ;# istarget sh*-*-*
\ No newline at end of file
diff --git a/gas/testsuite/gas/sh/arch/arch_expected.txt b/gas/testsuite/gas/sh/arch/arch_expected.txt
new file mode 100644
index 000000000000..c8f0ffbb8ac9
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/arch_expected.txt
@@ -0,0 +1,912 @@
+# Generated file. DO NOT EDIT
+#
+# This file is generated by gas/testsuite/gas/sh/arch/arch.exp .
+# It contains the expected results of the tests.
+# If the tests are failing because the expected results
+# have changed then run 'make check' and copy the new file
+# from <objdir>/gas/testsuite/arch_results.txt
+# to   <srcdir>/gas/testsuite/gas/sh/arch/arch_expected.txt .
+# Make sure the new expected results are ALL correct.
+#
+# FILE               OPTION                    OUTPUT
+# ----               ------                    ------
+sh-dsp.s             default-options           ERROR
+sh-dsp.s             -dsp                      sh-dsp
+sh-dsp.s             -isa=any                  sh-dsp
+sh-dsp.s             -isa=dsp                  sh-dsp
+sh-dsp.s             -isa=fp                   ERROR
+sh-dsp.s             -isa=sh-dsp               sh-dsp
+sh-dsp.s             -isa=sh-dsp-up            sh-dsp
+sh-dsp.s             -isa=sh                   ERROR
+sh-dsp.s             -isa=sh-up                sh-dsp
+sh-dsp.s             -isa=sh2                  ERROR
+sh-dsp.s             -isa=sh2-up               sh-dsp
+sh-dsp.s             -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh-dsp.s             -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp
+sh-dsp.s             -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh-dsp.s             -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
+sh-dsp.s             -isa=sh2a-nofpu           ERROR
+sh-dsp.s             -isa=sh2a-nofpu-up        ERROR
+sh-dsp.s             -isa=sh2a-or-sh3e         ERROR
+sh-dsp.s             -isa=sh2a-or-sh3e-up      ERROR
+sh-dsp.s             -isa=sh2a-or-sh4          ERROR
+sh-dsp.s             -isa=sh2a-or-sh4-up       ERROR
+sh-dsp.s             -isa=sh2a                 ERROR
+sh-dsp.s             -isa=sh2a-up              ERROR
+sh-dsp.s             -isa=sh2e                 ERROR
+sh-dsp.s             -isa=sh2e-up              ERROR
+sh-dsp.s             -isa=sh3-dsp              sh3-dsp
+sh-dsp.s             -isa=sh3-dsp-up           sh3-dsp
+sh-dsp.s             -isa=sh3-nommu            ERROR
+sh-dsp.s             -isa=sh3-nommu-up         sh3-dsp
+sh-dsp.s             -isa=sh3                  ERROR
+sh-dsp.s             -isa=sh3-up               sh3-dsp
+sh-dsp.s             -isa=sh3e                 ERROR
+sh-dsp.s             -isa=sh3e-up              ERROR
+sh-dsp.s             -isa=sh4-nofpu            ERROR
+sh-dsp.s             -isa=sh4-nofpu-up         sh4al-dsp
+sh-dsp.s             -isa=sh4-nommu-nofpu      ERROR
+sh-dsp.s             -isa=sh4-nommu-nofpu-up   sh4al-dsp
+sh-dsp.s             -isa=sh4                  ERROR
+sh-dsp.s             -isa=sh4-up               ERROR
+sh-dsp.s             -isa=sh4a-nofpu           ERROR
+sh-dsp.s             -isa=sh4a-nofpu-up        sh4al-dsp
+sh-dsp.s             -isa=sh4a                 ERROR
+sh-dsp.s             -isa=sh4a-up              ERROR
+sh-dsp.s             -isa=sh4al-dsp            sh4al-dsp
+sh-dsp.s             -isa=sh4al-dsp-up         sh4al-dsp
+sh.s                 default-options           sh
+sh.s                 -dsp                      sh
+sh.s                 -isa=any                  sh
+sh.s                 -isa=dsp                  sh
+sh.s                 -isa=fp                   sh
+sh.s                 -isa=sh-dsp               sh-dsp
+sh.s                 -isa=sh-dsp-up            sh-dsp
+sh.s                 -isa=sh                   sh
+sh.s                 -isa=sh-up                sh
+sh.s                 -isa=sh2                  sh2
+sh.s                 -isa=sh2-up               sh2
+sh.s                 -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
+sh.s                 -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
+sh.s                 -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
+sh.s                 -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
+sh.s                 -isa=sh2a-nofpu           sh2a-nofpu
+sh.s                 -isa=sh2a-nofpu-up        sh2a-nofpu
+sh.s                 -isa=sh2a-or-sh3e         sh2a-or-sh3e
+sh.s                 -isa=sh2a-or-sh3e-up      sh2a-or-sh3e
+sh.s                 -isa=sh2a-or-sh4          sh2a-or-sh4
+sh.s                 -isa=sh2a-or-sh4-up       sh2a-or-sh4
+sh.s                 -isa=sh2a                 sh2a
+sh.s                 -isa=sh2a-up              sh2a
+sh.s                 -isa=sh2e                 sh2e
+sh.s                 -isa=sh2e-up              sh2e
+sh.s                 -isa=sh3-dsp              sh3-dsp
+sh.s                 -isa=sh3-dsp-up           sh3-dsp
+sh.s                 -isa=sh3-nommu            sh3-nommu
+sh.s                 -isa=sh3-nommu-up         sh3-nommu
+sh.s                 -isa=sh3                  sh3
+sh.s                 -isa=sh3-up               sh3
+sh.s                 -isa=sh3e                 sh3e
+sh.s                 -isa=sh3e-up              sh3e
+sh.s                 -isa=sh4-nofpu            sh4-nofpu
+sh.s                 -isa=sh4-nofpu-up         sh4-nofpu
+sh.s                 -isa=sh4-nommu-nofpu      sh4-nommu-nofpu
+sh.s                 -isa=sh4-nommu-nofpu-up   sh4-nommu-nofpu
+sh.s                 -isa=sh4                  sh4
+sh.s                 -isa=sh4-up               sh4
+sh.s                 -isa=sh4a-nofpu           sh4a-nofpu
+sh.s                 -isa=sh4a-nofpu-up        sh4a-nofpu
+sh.s                 -isa=sh4a                 sh4a
+sh.s                 -isa=sh4a-up              sh4a
+sh.s                 -isa=sh4al-dsp            sh4al-dsp
+sh.s                 -isa=sh4al-dsp-up         sh4al-dsp
+sh2.s                default-options           sh2
+sh2.s                -dsp                      sh2
+sh2.s                -isa=any                  sh2
+sh2.s                -isa=dsp                  sh2
+sh2.s                -isa=fp                   sh2
+sh2.s                -isa=sh-dsp               sh-dsp
+sh2.s                -isa=sh-dsp-up            sh-dsp
+sh2.s                -isa=sh                   ERROR
+sh2.s                -isa=sh-up                sh2
+sh2.s                -isa=sh2                  sh2
+sh2.s                -isa=sh2-up               sh2
+sh2.s                -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
+sh2.s                -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
+sh2.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
+sh2.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
+sh2.s                -isa=sh2a-nofpu           sh2a-nofpu
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+sh2.s                -isa=sh2a-or-sh3e         sh2a-or-sh3e
+sh2.s                -isa=sh2a-or-sh3e-up      sh2a-or-sh3e
+sh2.s                -isa=sh2a-or-sh4          sh2a-or-sh4
+sh2.s                -isa=sh2a-or-sh4-up       sh2a-or-sh4
+sh2.s                -isa=sh2a                 sh2a
+sh2.s                -isa=sh2a-up              sh2a
+sh2.s                -isa=sh2e                 sh2e
+sh2.s                -isa=sh2e-up              sh2e
+sh2.s                -isa=sh3-dsp              sh3-dsp
+sh2.s                -isa=sh3-dsp-up           sh3-dsp
+sh2.s                -isa=sh3-nommu            sh3-nommu
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+sh2.s                -isa=sh3                  sh3
+sh2.s                -isa=sh3-up               sh3
+sh2.s                -isa=sh3e                 sh3e
+sh2.s                -isa=sh3e-up              sh3e
+sh2.s                -isa=sh4-nofpu            sh4-nofpu
+sh2.s                -isa=sh4-nofpu-up         sh4-nofpu
+sh2.s                -isa=sh4-nommu-nofpu      sh4-nommu-nofpu
+sh2.s                -isa=sh4-nommu-nofpu-up   sh4-nommu-nofpu
+sh2.s                -isa=sh4                  sh4
+sh2.s                -isa=sh4-up               sh4
+sh2.s                -isa=sh4a-nofpu           sh4a-nofpu
+sh2.s                -isa=sh4a-nofpu-up        sh4a-nofpu
+sh2.s                -isa=sh4a                 sh4a
+sh2.s                -isa=sh4a-up              sh4a
+sh2.s                -isa=sh4al-dsp            sh4al-dsp
+sh2.s                -isa=sh4al-dsp-up         sh4al-dsp
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+sh2a-nofpu-or-sh3-nommu.s -dsp                      sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.s -isa=any                  sh2a-nofpu-or-sh3-nommu
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+sh2a-nofpu-or-sh3-nommu.s -isa=fp                   sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp               ERROR
+sh2a-nofpu-or-sh3-nommu.s -isa=sh-dsp-up            sh3-dsp
+sh2a-nofpu-or-sh3-nommu.s -isa=sh                   ERROR
+sh2a-nofpu-or-sh3-nommu.s -isa=sh-up                sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.s -isa=sh2                  ERROR
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh3-nommu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh2e                 ERROR
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh3-dsp              sh3-dsp
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh3                  sh3
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh4                  sh4
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+sh2a-nofpu-or-sh3-nommu.s -isa=sh4a-up              sh4a
+sh2a-nofpu-or-sh3-nommu.s -isa=sh4al-dsp            sh4al-dsp
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+sh2a-nofpu-or-sh4-nommu-nofpu.s default-options           sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -dsp                      sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=any                  sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=dsp                  sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=fp                   sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp               ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-dsp-up            sh4al-dsp
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh                   ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh-up                sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2                  ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2-up               sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-nofpu           sh2a-nofpu
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+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2a-or-sh3e         ERROR
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+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh2e                 ERROR
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+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-dsp              ERROR
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+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu            ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-nommu-up         sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3                  ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3-up               sh4-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e                 ERROR
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh3e-up              sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu            sh4-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nofpu-up         sh4-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu      sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-nommu-nofpu-up   sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4                  sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4-up               sh4
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+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a                 sh4a
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4a-up              sh4a
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp            sh4al-dsp
+sh2a-nofpu-or-sh4-nommu-nofpu.s -isa=sh4al-dsp-up         sh4al-dsp
+sh2a-nofpu.s         default-options           sh2a-nofpu
+sh2a-nofpu.s         -dsp                      sh2a-nofpu
+sh2a-nofpu.s         -isa=any                  sh2a-nofpu
+sh2a-nofpu.s         -isa=dsp                  sh2a-nofpu
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+sh2a-nofpu.s         -isa=sh-dsp               ERROR
+sh2a-nofpu.s         -isa=sh-dsp-up            ERROR
+sh2a-nofpu.s         -isa=sh                   ERROR
+sh2a-nofpu.s         -isa=sh-up                sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2                  ERROR
+sh2a-nofpu.s         -isa=sh2-up               sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2a-nofpu.s         -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh2a-nofpu.s         -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2a-nofpu           sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2a-nofpu-up        sh2a-nofpu
+sh2a-nofpu.s         -isa=sh2a-or-sh3e         ERROR
+sh2a-nofpu.s         -isa=sh2a-or-sh3e-up      sh2a
+sh2a-nofpu.s         -isa=sh2a-or-sh4          ERROR
+sh2a-nofpu.s         -isa=sh2a-or-sh4-up       sh2a
+sh2a-nofpu.s         -isa=sh2a                 sh2a
+sh2a-nofpu.s         -isa=sh2a-up              sh2a
+sh2a-nofpu.s         -isa=sh2e                 ERROR
+sh2a-nofpu.s         -isa=sh2e-up              sh2a
+sh2a-nofpu.s         -isa=sh3-dsp              ERROR
+sh2a-nofpu.s         -isa=sh3-dsp-up           ERROR
+sh2a-nofpu.s         -isa=sh3-nommu            ERROR
+sh2a-nofpu.s         -isa=sh3-nommu-up         ERROR
+sh2a-nofpu.s         -isa=sh3                  ERROR
+sh2a-nofpu.s         -isa=sh3-up               ERROR
+sh2a-nofpu.s         -isa=sh3e                 ERROR
+sh2a-nofpu.s         -isa=sh3e-up              ERROR
+sh2a-nofpu.s         -isa=sh4-nofpu            ERROR
+sh2a-nofpu.s         -isa=sh4-nofpu-up         ERROR
+sh2a-nofpu.s         -isa=sh4-nommu-nofpu      ERROR
+sh2a-nofpu.s         -isa=sh4-nommu-nofpu-up   ERROR
+sh2a-nofpu.s         -isa=sh4                  ERROR
+sh2a-nofpu.s         -isa=sh4-up               ERROR
+sh2a-nofpu.s         -isa=sh4a-nofpu           ERROR
+sh2a-nofpu.s         -isa=sh4a-nofpu-up        ERROR
+sh2a-nofpu.s         -isa=sh4a                 ERROR
+sh2a-nofpu.s         -isa=sh4a-up              ERROR
+sh2a-nofpu.s         -isa=sh4al-dsp            ERROR
+sh2a-nofpu.s         -isa=sh4al-dsp-up         ERROR
+sh2a-or-sh3e.s       default-options           sh2a-or-sh3e
+sh2a-or-sh3e.s       -dsp                      ERROR
+sh2a-or-sh3e.s       -isa=any                  sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=dsp                  ERROR
+sh2a-or-sh3e.s       -isa=fp                   sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh-dsp               ERROR
+sh2a-or-sh3e.s       -isa=sh-dsp-up            ERROR
+sh2a-or-sh3e.s       -isa=sh                   ERROR
+sh2a-or-sh3e.s       -isa=sh-up                sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh2                  ERROR
+sh2a-or-sh3e.s       -isa=sh2-up               sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2a-or-sh3e.s       -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh2a-or-sh3e.s       -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
+sh2a-or-sh3e.s       -isa=sh2a-nofpu           ERROR
+sh2a-or-sh3e.s       -isa=sh2a-nofpu-up        sh2a
+sh2a-or-sh3e.s       -isa=sh2a-or-sh3e         sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh2a-or-sh3e-up      sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh2a-or-sh4          sh2a-or-sh4
+sh2a-or-sh3e.s       -isa=sh2a-or-sh4-up       sh2a-or-sh4
+sh2a-or-sh3e.s       -isa=sh2a                 sh2a
+sh2a-or-sh3e.s       -isa=sh2a-up              sh2a
+sh2a-or-sh3e.s       -isa=sh2e                 ERROR
+sh2a-or-sh3e.s       -isa=sh2e-up              sh2a-or-sh3e
+sh2a-or-sh3e.s       -isa=sh3-dsp              ERROR
+sh2a-or-sh3e.s       -isa=sh3-dsp-up           ERROR
+sh2a-or-sh3e.s       -isa=sh3-nommu            ERROR
+sh2a-or-sh3e.s       -isa=sh3-nommu-up         sh3e
+sh2a-or-sh3e.s       -isa=sh3                  ERROR
+sh2a-or-sh3e.s       -isa=sh3-up               sh3e
+sh2a-or-sh3e.s       -isa=sh3e                 sh3e
+sh2a-or-sh3e.s       -isa=sh3e-up              sh3e
+sh2a-or-sh3e.s       -isa=sh4-nofpu            ERROR
+sh2a-or-sh3e.s       -isa=sh4-nofpu-up         sh4
+sh2a-or-sh3e.s       -isa=sh4-nommu-nofpu      ERROR
+sh2a-or-sh3e.s       -isa=sh4-nommu-nofpu-up   sh4
+sh2a-or-sh3e.s       -isa=sh4                  sh4
+sh2a-or-sh3e.s       -isa=sh4-up               sh4
+sh2a-or-sh3e.s       -isa=sh4a-nofpu           ERROR
+sh2a-or-sh3e.s       -isa=sh4a-nofpu-up        sh4a
+sh2a-or-sh3e.s       -isa=sh4a                 sh4a
+sh2a-or-sh3e.s       -isa=sh4a-up              sh4a
+sh2a-or-sh3e.s       -isa=sh4al-dsp            ERROR
+sh2a-or-sh3e.s       -isa=sh4al-dsp-up         ERROR
+sh2a-or-sh4.s        default-options           sh2a-or-sh4
+sh2a-or-sh4.s        -dsp                      ERROR
+sh2a-or-sh4.s        -isa=any                  sh2a-or-sh4
+sh2a-or-sh4.s        -isa=dsp                  ERROR
+sh2a-or-sh4.s        -isa=fp                   sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh-dsp               ERROR
+sh2a-or-sh4.s        -isa=sh-dsp-up            ERROR
+sh2a-or-sh4.s        -isa=sh                   ERROR
+sh2a-or-sh4.s        -isa=sh-up                sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2                  ERROR
+sh2a-or-sh4.s        -isa=sh2-up               sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2a-or-sh4.s        -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh2a-or-sh4.s        -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a-nofpu           ERROR
+sh2a-or-sh4.s        -isa=sh2a-nofpu-up        sh2a
+sh2a-or-sh4.s        -isa=sh2a-or-sh3e         ERROR
+sh2a-or-sh4.s        -isa=sh2a-or-sh3e-up      sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a-or-sh4          sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a-or-sh4-up       sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh2a                 sh2a
+sh2a-or-sh4.s        -isa=sh2a-up              sh2a
+sh2a-or-sh4.s        -isa=sh2e                 ERROR
+sh2a-or-sh4.s        -isa=sh2e-up              sh2a-or-sh4
+sh2a-or-sh4.s        -isa=sh3-dsp              ERROR
+sh2a-or-sh4.s        -isa=sh3-dsp-up           ERROR
+sh2a-or-sh4.s        -isa=sh3-nommu            ERROR
+sh2a-or-sh4.s        -isa=sh3-nommu-up         sh4
+sh2a-or-sh4.s        -isa=sh3                  ERROR
+sh2a-or-sh4.s        -isa=sh3-up               sh4
+sh2a-or-sh4.s        -isa=sh3e                 ERROR
+sh2a-or-sh4.s        -isa=sh3e-up              sh4
+sh2a-or-sh4.s        -isa=sh4-nofpu            ERROR
+sh2a-or-sh4.s        -isa=sh4-nofpu-up         sh4
+sh2a-or-sh4.s        -isa=sh4-nommu-nofpu      ERROR
+sh2a-or-sh4.s        -isa=sh4-nommu-nofpu-up   sh4
+sh2a-or-sh4.s        -isa=sh4                  sh4
+sh2a-or-sh4.s        -isa=sh4-up               sh4
+sh2a-or-sh4.s        -isa=sh4a-nofpu           ERROR
+sh2a-or-sh4.s        -isa=sh4a-nofpu-up        sh4a
+sh2a-or-sh4.s        -isa=sh4a                 sh4a
+sh2a-or-sh4.s        -isa=sh4a-up              sh4a
+sh2a-or-sh4.s        -isa=sh4al-dsp            ERROR
+sh2a-or-sh4.s        -isa=sh4al-dsp-up         ERROR
+sh2a.s               default-options           sh2a
+sh2a.s               -dsp                      ERROR
+sh2a.s               -isa=any                  sh2a
+sh2a.s               -isa=dsp                  ERROR
+sh2a.s               -isa=fp                   sh2a
+sh2a.s               -isa=sh-dsp               ERROR
+sh2a.s               -isa=sh-dsp-up            ERROR
+sh2a.s               -isa=sh                   ERROR
+sh2a.s               -isa=sh-up                sh2a
+sh2a.s               -isa=sh2                  ERROR
+sh2a.s               -isa=sh2-up               sh2a
+sh2a.s               -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2a.s               -isa=sh2a-nofpu-or-sh3-nommu-up sh2a
+sh2a.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh2a.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a
+sh2a.s               -isa=sh2a-nofpu           ERROR
+sh2a.s               -isa=sh2a-nofpu-up        sh2a
+sh2a.s               -isa=sh2a-or-sh3e         ERROR
+sh2a.s               -isa=sh2a-or-sh3e-up      sh2a
+sh2a.s               -isa=sh2a-or-sh4          ERROR
+sh2a.s               -isa=sh2a-or-sh4-up       sh2a
+sh2a.s               -isa=sh2a                 sh2a
+sh2a.s               -isa=sh2a-up              sh2a
+sh2a.s               -isa=sh2e                 ERROR
+sh2a.s               -isa=sh2e-up              sh2a
+sh2a.s               -isa=sh3-dsp              ERROR
+sh2a.s               -isa=sh3-dsp-up           ERROR
+sh2a.s               -isa=sh3-nommu            ERROR
+sh2a.s               -isa=sh3-nommu-up         ERROR
+sh2a.s               -isa=sh3                  ERROR
+sh2a.s               -isa=sh3-up               ERROR
+sh2a.s               -isa=sh3e                 ERROR
+sh2a.s               -isa=sh3e-up              ERROR
+sh2a.s               -isa=sh4-nofpu            ERROR
+sh2a.s               -isa=sh4-nofpu-up         ERROR
+sh2a.s               -isa=sh4-nommu-nofpu      ERROR
+sh2a.s               -isa=sh4-nommu-nofpu-up   ERROR
+sh2a.s               -isa=sh4                  ERROR
+sh2a.s               -isa=sh4-up               ERROR
+sh2a.s               -isa=sh4a-nofpu           ERROR
+sh2a.s               -isa=sh4a-nofpu-up        ERROR
+sh2a.s               -isa=sh4a                 ERROR
+sh2a.s               -isa=sh4a-up              ERROR
+sh2a.s               -isa=sh4al-dsp            ERROR
+sh2a.s               -isa=sh4al-dsp-up         ERROR
+sh2e.s               default-options           sh2e
+sh2e.s               -dsp                      ERROR
+sh2e.s               -isa=any                  sh2e
+sh2e.s               -isa=dsp                  ERROR
+sh2e.s               -isa=fp                   sh2e
+sh2e.s               -isa=sh-dsp               ERROR
+sh2e.s               -isa=sh-dsp-up            ERROR
+sh2e.s               -isa=sh                   ERROR
+sh2e.s               -isa=sh-up                sh2e
+sh2e.s               -isa=sh2                  ERROR
+sh2e.s               -isa=sh2-up               sh2e
+sh2e.s               -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh2e.s               -isa=sh2a-nofpu-or-sh3-nommu-up sh2a-or-sh3e
+sh2e.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh2e.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh2a-or-sh4
+sh2e.s               -isa=sh2a-nofpu           ERROR
+sh2e.s               -isa=sh2a-nofpu-up        sh2a
+sh2e.s               -isa=sh2a-or-sh3e         sh2a-or-sh3e
+sh2e.s               -isa=sh2a-or-sh3e-up      sh2a-or-sh3e
+sh2e.s               -isa=sh2a-or-sh4          sh2a-or-sh4
+sh2e.s               -isa=sh2a-or-sh4-up       sh2a-or-sh4
+sh2e.s               -isa=sh2a                 sh2a
+sh2e.s               -isa=sh2a-up              sh2a
+sh2e.s               -isa=sh2e                 sh2e
+sh2e.s               -isa=sh2e-up              sh2e
+sh2e.s               -isa=sh3-dsp              ERROR
+sh2e.s               -isa=sh3-dsp-up           ERROR
+sh2e.s               -isa=sh3-nommu            ERROR
+sh2e.s               -isa=sh3-nommu-up         sh3e
+sh2e.s               -isa=sh3                  ERROR
+sh2e.s               -isa=sh3-up               sh3e
+sh2e.s               -isa=sh3e                 sh3e
+sh2e.s               -isa=sh3e-up              sh3e
+sh2e.s               -isa=sh4-nofpu            ERROR
+sh2e.s               -isa=sh4-nofpu-up         sh4
+sh2e.s               -isa=sh4-nommu-nofpu      ERROR
+sh2e.s               -isa=sh4-nommu-nofpu-up   sh4
+sh2e.s               -isa=sh4                  sh4
+sh2e.s               -isa=sh4-up               sh4
+sh2e.s               -isa=sh4a-nofpu           ERROR
+sh2e.s               -isa=sh4a-nofpu-up        sh4a
+sh2e.s               -isa=sh4a                 sh4a
+sh2e.s               -isa=sh4a-up              sh4a
+sh2e.s               -isa=sh4al-dsp            ERROR
+sh2e.s               -isa=sh4al-dsp-up         ERROR
+sh3-dsp.s            default-options           ERROR
+sh3-dsp.s            -dsp                      sh3-dsp
+sh3-dsp.s            -isa=any                  sh3-dsp
+sh3-dsp.s            -isa=dsp                  sh3-dsp
+sh3-dsp.s            -isa=fp                   ERROR
+sh3-dsp.s            -isa=sh-dsp               ERROR
+sh3-dsp.s            -isa=sh-dsp-up            sh3-dsp
+sh3-dsp.s            -isa=sh                   ERROR
+sh3-dsp.s            -isa=sh-up                sh3-dsp
+sh3-dsp.s            -isa=sh2                  ERROR
+sh3-dsp.s            -isa=sh2-up               sh3-dsp
+sh3-dsp.s            -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh3-dsp.s            -isa=sh2a-nofpu-or-sh3-nommu-up sh3-dsp
+sh3-dsp.s            -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh3-dsp.s            -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
+sh3-dsp.s            -isa=sh2a-nofpu           ERROR
+sh3-dsp.s            -isa=sh2a-nofpu-up        ERROR
+sh3-dsp.s            -isa=sh2a-or-sh3e         ERROR
+sh3-dsp.s            -isa=sh2a-or-sh3e-up      ERROR
+sh3-dsp.s            -isa=sh2a-or-sh4          ERROR
+sh3-dsp.s            -isa=sh2a-or-sh4-up       ERROR
+sh3-dsp.s            -isa=sh2a                 ERROR
+sh3-dsp.s            -isa=sh2a-up              ERROR
+sh3-dsp.s            -isa=sh2e                 ERROR
+sh3-dsp.s            -isa=sh2e-up              ERROR
+sh3-dsp.s            -isa=sh3-dsp              sh3-dsp
+sh3-dsp.s            -isa=sh3-dsp-up           sh3-dsp
+sh3-dsp.s            -isa=sh3-nommu            ERROR
+sh3-dsp.s            -isa=sh3-nommu-up         sh3-dsp
+sh3-dsp.s            -isa=sh3                  ERROR
+sh3-dsp.s            -isa=sh3-up               sh3-dsp
+sh3-dsp.s            -isa=sh3e                 ERROR
+sh3-dsp.s            -isa=sh3e-up              ERROR
+sh3-dsp.s            -isa=sh4-nofpu            ERROR
+sh3-dsp.s            -isa=sh4-nofpu-up         sh4al-dsp
+sh3-dsp.s            -isa=sh4-nommu-nofpu      ERROR
+sh3-dsp.s            -isa=sh4-nommu-nofpu-up   sh4al-dsp
+sh3-dsp.s            -isa=sh4                  ERROR
+sh3-dsp.s            -isa=sh4-up               ERROR
+sh3-dsp.s            -isa=sh4a-nofpu           ERROR
+sh3-dsp.s            -isa=sh4a-nofpu-up        sh4al-dsp
+sh3-dsp.s            -isa=sh4a                 ERROR
+sh3-dsp.s            -isa=sh4a-up              ERROR
+sh3-dsp.s            -isa=sh4al-dsp            sh4al-dsp
+sh3-dsp.s            -isa=sh4al-dsp-up         sh4al-dsp
+sh3-nommu.s          default-options           sh3-nommu
+sh3-nommu.s          -dsp                      sh3-nommu
+sh3-nommu.s          -isa=any                  sh3-nommu
+sh3-nommu.s          -isa=dsp                  sh3-nommu
+sh3-nommu.s          -isa=fp                   sh3-nommu
+sh3-nommu.s          -isa=sh-dsp               ERROR
+sh3-nommu.s          -isa=sh-dsp-up            sh3-dsp
+sh3-nommu.s          -isa=sh                   ERROR
+sh3-nommu.s          -isa=sh-up                sh3-nommu
+sh3-nommu.s          -isa=sh2                  ERROR
+sh3-nommu.s          -isa=sh2-up               sh3-nommu
+sh3-nommu.s          -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh3-nommu.s          -isa=sh2a-nofpu-or-sh3-nommu-up sh3-nommu
+sh3-nommu.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh3-nommu.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu
+sh3-nommu.s          -isa=sh2a-nofpu           ERROR
+sh3-nommu.s          -isa=sh2a-nofpu-up        ERROR
+sh3-nommu.s          -isa=sh2a-or-sh3e         ERROR
+sh3-nommu.s          -isa=sh2a-or-sh3e-up      sh3e
+sh3-nommu.s          -isa=sh2a-or-sh4          ERROR
+sh3-nommu.s          -isa=sh2a-or-sh4-up       sh4
+sh3-nommu.s          -isa=sh2a                 ERROR
+sh3-nommu.s          -isa=sh2a-up              ERROR
+sh3-nommu.s          -isa=sh2e                 ERROR
+sh3-nommu.s          -isa=sh2e-up              sh3e
+sh3-nommu.s          -isa=sh3-dsp              sh3-dsp
+sh3-nommu.s          -isa=sh3-dsp-up           sh3-dsp
+sh3-nommu.s          -isa=sh3-nommu            sh3-nommu
+sh3-nommu.s          -isa=sh3-nommu-up         sh3-nommu
+sh3-nommu.s          -isa=sh3                  sh3
+sh3-nommu.s          -isa=sh3-up               sh3
+sh3-nommu.s          -isa=sh3e                 sh3e
+sh3-nommu.s          -isa=sh3e-up              sh3e
+sh3-nommu.s          -isa=sh4-nofpu            sh4-nofpu
+sh3-nommu.s          -isa=sh4-nofpu-up         sh4-nofpu
+sh3-nommu.s          -isa=sh4-nommu-nofpu      sh4-nommu-nofpu
+sh3-nommu.s          -isa=sh4-nommu-nofpu-up   sh4-nommu-nofpu
+sh3-nommu.s          -isa=sh4                  sh4
+sh3-nommu.s          -isa=sh4-up               sh4
+sh3-nommu.s          -isa=sh4a-nofpu           sh4a-nofpu
+sh3-nommu.s          -isa=sh4a-nofpu-up        sh4a-nofpu
+sh3-nommu.s          -isa=sh4a                 sh4a
+sh3-nommu.s          -isa=sh4a-up              sh4a
+sh3-nommu.s          -isa=sh4al-dsp            sh4al-dsp
+sh3-nommu.s          -isa=sh4al-dsp-up         sh4al-dsp
+sh3.s                default-options           sh3
+sh3.s                -dsp                      sh3
+sh3.s                -isa=any                  sh3
+sh3.s                -isa=dsp                  sh3
+sh3.s                -isa=fp                   sh3
+sh3.s                -isa=sh-dsp               ERROR
+sh3.s                -isa=sh-dsp-up            sh3-dsp
+sh3.s                -isa=sh                   ERROR
+sh3.s                -isa=sh-up                sh3
+sh3.s                -isa=sh2                  ERROR
+sh3.s                -isa=sh2-up               sh3
+sh3.s                -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh3.s                -isa=sh2a-nofpu-or-sh3-nommu-up sh3
+sh3.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh3.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu
+sh3.s                -isa=sh2a-nofpu           ERROR
+sh3.s                -isa=sh2a-nofpu-up        ERROR
+sh3.s                -isa=sh2a-or-sh3e         ERROR
+sh3.s                -isa=sh2a-or-sh3e-up      sh3e
+sh3.s                -isa=sh2a-or-sh4          ERROR
+sh3.s                -isa=sh2a-or-sh4-up       sh4
+sh3.s                -isa=sh2a                 ERROR
+sh3.s                -isa=sh2a-up              ERROR
+sh3.s                -isa=sh2e                 ERROR
+sh3.s                -isa=sh2e-up              sh3e
+sh3.s                -isa=sh3-dsp              sh3-dsp
+sh3.s                -isa=sh3-dsp-up           sh3-dsp
+sh3.s                -isa=sh3-nommu            ERROR
+sh3.s                -isa=sh3-nommu-up         sh3
+sh3.s                -isa=sh3                  sh3
+sh3.s                -isa=sh3-up               sh3
+sh3.s                -isa=sh3e                 sh3e
+sh3.s                -isa=sh3e-up              sh3e
+sh3.s                -isa=sh4-nofpu            sh4-nofpu
+sh3.s                -isa=sh4-nofpu-up         sh4-nofpu
+sh3.s                -isa=sh4-nommu-nofpu      ERROR
+sh3.s                -isa=sh4-nommu-nofpu-up   sh4-nofpu
+sh3.s                -isa=sh4                  sh4
+sh3.s                -isa=sh4-up               sh4
+sh3.s                -isa=sh4a-nofpu           sh4a-nofpu
+sh3.s                -isa=sh4a-nofpu-up        sh4a-nofpu
+sh3.s                -isa=sh4a                 sh4a
+sh3.s                -isa=sh4a-up              sh4a
+sh3.s                -isa=sh4al-dsp            sh4al-dsp
+sh3.s                -isa=sh4al-dsp-up         sh4al-dsp
+sh3e.s               default-options           sh3e
+sh3e.s               -dsp                      ERROR
+sh3e.s               -isa=any                  sh3e
+sh3e.s               -isa=dsp                  ERROR
+sh3e.s               -isa=fp                   sh3e
+sh3e.s               -isa=sh-dsp               ERROR
+sh3e.s               -isa=sh-dsp-up            ERROR
+sh3e.s               -isa=sh                   ERROR
+sh3e.s               -isa=sh-up                sh3e
+sh3e.s               -isa=sh2                  ERROR
+sh3e.s               -isa=sh2-up               sh3e
+sh3e.s               -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh3e.s               -isa=sh2a-nofpu-or-sh3-nommu-up sh3e
+sh3e.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh3e.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4
+sh3e.s               -isa=sh2a-nofpu           ERROR
+sh3e.s               -isa=sh2a-nofpu-up        ERROR
+sh3e.s               -isa=sh2a-or-sh3e         ERROR
+sh3e.s               -isa=sh2a-or-sh3e-up      sh3e
+sh3e.s               -isa=sh2a-or-sh4          ERROR
+sh3e.s               -isa=sh2a-or-sh4-up       sh4
+sh3e.s               -isa=sh2a                 ERROR
+sh3e.s               -isa=sh2a-up              ERROR
+sh3e.s               -isa=sh2e                 ERROR
+sh3e.s               -isa=sh2e-up              sh3e
+sh3e.s               -isa=sh3-dsp              ERROR
+sh3e.s               -isa=sh3-dsp-up           ERROR
+sh3e.s               -isa=sh3-nommu            ERROR
+sh3e.s               -isa=sh3-nommu-up         sh3e
+sh3e.s               -isa=sh3                  ERROR
+sh3e.s               -isa=sh3-up               sh3e
+sh3e.s               -isa=sh3e                 sh3e
+sh3e.s               -isa=sh3e-up              sh3e
+sh3e.s               -isa=sh4-nofpu            ERROR
+sh3e.s               -isa=sh4-nofpu-up         sh4
+sh3e.s               -isa=sh4-nommu-nofpu      ERROR
+sh3e.s               -isa=sh4-nommu-nofpu-up   sh4
+sh3e.s               -isa=sh4                  sh4
+sh3e.s               -isa=sh4-up               sh4
+sh3e.s               -isa=sh4a-nofpu           ERROR
+sh3e.s               -isa=sh4a-nofpu-up        sh4a
+sh3e.s               -isa=sh4a                 sh4a
+sh3e.s               -isa=sh4a-up              sh4a
+sh3e.s               -isa=sh4al-dsp            ERROR
+sh3e.s               -isa=sh4al-dsp-up         ERROR
+sh4-nofpu.s          default-options           sh4-nofpu
+sh4-nofpu.s          -dsp                      sh4-nofpu
+sh4-nofpu.s          -isa=any                  sh4-nofpu
+sh4-nofpu.s          -isa=dsp                  sh4-nofpu
+sh4-nofpu.s          -isa=fp                   sh4-nofpu
+sh4-nofpu.s          -isa=sh-dsp               ERROR
+sh4-nofpu.s          -isa=sh-dsp-up            sh4al-dsp
+sh4-nofpu.s          -isa=sh                   ERROR
+sh4-nofpu.s          -isa=sh-up                sh4-nofpu
+sh4-nofpu.s          -isa=sh2                  ERROR
+sh4-nofpu.s          -isa=sh2-up               sh4-nofpu
+sh4-nofpu.s          -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4-nofpu.s          -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nofpu
+sh4-nofpu.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4-nofpu.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nofpu
+sh4-nofpu.s          -isa=sh2a-nofpu           ERROR
+sh4-nofpu.s          -isa=sh2a-nofpu-up        ERROR
+sh4-nofpu.s          -isa=sh2a-or-sh3e         ERROR
+sh4-nofpu.s          -isa=sh2a-or-sh3e-up      sh4
+sh4-nofpu.s          -isa=sh2a-or-sh4          ERROR
+sh4-nofpu.s          -isa=sh2a-or-sh4-up       sh4
+sh4-nofpu.s          -isa=sh2a                 ERROR
+sh4-nofpu.s          -isa=sh2a-up              ERROR
+sh4-nofpu.s          -isa=sh2e                 ERROR
+sh4-nofpu.s          -isa=sh2e-up              sh4
+sh4-nofpu.s          -isa=sh3-dsp              ERROR
+sh4-nofpu.s          -isa=sh3-dsp-up           sh4al-dsp
+sh4-nofpu.s          -isa=sh3-nommu            ERROR
+sh4-nofpu.s          -isa=sh3-nommu-up         sh4-nofpu
+sh4-nofpu.s          -isa=sh3                  ERROR
+sh4-nofpu.s          -isa=sh3-up               sh4-nofpu
+sh4-nofpu.s          -isa=sh3e                 ERROR
+sh4-nofpu.s          -isa=sh3e-up              sh4
+sh4-nofpu.s          -isa=sh4-nofpu            sh4-nofpu
+sh4-nofpu.s          -isa=sh4-nofpu-up         sh4-nofpu
+sh4-nofpu.s          -isa=sh4-nommu-nofpu      ERROR
+sh4-nofpu.s          -isa=sh4-nommu-nofpu-up   sh4-nofpu
+sh4-nofpu.s          -isa=sh4                  sh4
+sh4-nofpu.s          -isa=sh4-up               sh4
+sh4-nofpu.s          -isa=sh4a-nofpu           sh4a-nofpu
+sh4-nofpu.s          -isa=sh4a-nofpu-up        sh4a-nofpu
+sh4-nofpu.s          -isa=sh4a                 sh4a
+sh4-nofpu.s          -isa=sh4a-up              sh4a
+sh4-nofpu.s          -isa=sh4al-dsp            sh4al-dsp
+sh4-nofpu.s          -isa=sh4al-dsp-up         sh4al-dsp
+sh4-nommu-nofpu.s    default-options           sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -dsp                      sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=any                  sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=dsp                  sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=fp                   sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh-dsp               ERROR
+sh4-nommu-nofpu.s    -isa=sh-dsp-up            sh4al-dsp
+sh4-nommu-nofpu.s    -isa=sh                   ERROR
+sh4-nommu-nofpu.s    -isa=sh-up                sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh2                  ERROR
+sh4-nommu-nofpu.s    -isa=sh2-up               sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu-or-sh3-nommu-up sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu           ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-nofpu-up        ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-or-sh3e         ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-or-sh3e-up      sh4
+sh4-nommu-nofpu.s    -isa=sh2a-or-sh4          ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-or-sh4-up       sh4
+sh4-nommu-nofpu.s    -isa=sh2a                 ERROR
+sh4-nommu-nofpu.s    -isa=sh2a-up              ERROR
+sh4-nommu-nofpu.s    -isa=sh2e                 ERROR
+sh4-nommu-nofpu.s    -isa=sh2e-up              sh4
+sh4-nommu-nofpu.s    -isa=sh3-dsp              ERROR
+sh4-nommu-nofpu.s    -isa=sh3-dsp-up           sh4al-dsp
+sh4-nommu-nofpu.s    -isa=sh3-nommu            ERROR
+sh4-nommu-nofpu.s    -isa=sh3-nommu-up         sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh3                  ERROR
+sh4-nommu-nofpu.s    -isa=sh3-up               sh4-nofpu
+sh4-nommu-nofpu.s    -isa=sh3e                 ERROR
+sh4-nommu-nofpu.s    -isa=sh3e-up              sh4
+sh4-nommu-nofpu.s    -isa=sh4-nofpu            sh4-nofpu
+sh4-nommu-nofpu.s    -isa=sh4-nofpu-up         sh4-nofpu
+sh4-nommu-nofpu.s    -isa=sh4-nommu-nofpu      sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh4-nommu-nofpu-up   sh4-nommu-nofpu
+sh4-nommu-nofpu.s    -isa=sh4                  sh4
+sh4-nommu-nofpu.s    -isa=sh4-up               sh4
+sh4-nommu-nofpu.s    -isa=sh4a-nofpu           sh4a-nofpu
+sh4-nommu-nofpu.s    -isa=sh4a-nofpu-up        sh4a-nofpu
+sh4-nommu-nofpu.s    -isa=sh4a                 sh4a
+sh4-nommu-nofpu.s    -isa=sh4a-up              sh4a
+sh4-nommu-nofpu.s    -isa=sh4al-dsp            sh4al-dsp
+sh4-nommu-nofpu.s    -isa=sh4al-dsp-up         sh4al-dsp
+sh4.s                default-options           sh4
+sh4.s                -dsp                      ERROR
+sh4.s                -isa=any                  sh4
+sh4.s                -isa=dsp                  ERROR
+sh4.s                -isa=fp                   sh4
+sh4.s                -isa=sh-dsp               ERROR
+sh4.s                -isa=sh-dsp-up            ERROR
+sh4.s                -isa=sh                   ERROR
+sh4.s                -isa=sh-up                sh4
+sh4.s                -isa=sh2                  ERROR
+sh4.s                -isa=sh2-up               sh4
+sh4.s                -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4.s                -isa=sh2a-nofpu-or-sh3-nommu-up sh4
+sh4.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4.s                -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4
+sh4.s                -isa=sh2a-nofpu           ERROR
+sh4.s                -isa=sh2a-nofpu-up        ERROR
+sh4.s                -isa=sh2a-or-sh3e         ERROR
+sh4.s                -isa=sh2a-or-sh3e-up      sh4
+sh4.s                -isa=sh2a-or-sh4          ERROR
+sh4.s                -isa=sh2a-or-sh4-up       sh4
+sh4.s                -isa=sh2a                 ERROR
+sh4.s                -isa=sh2a-up              ERROR
+sh4.s                -isa=sh2e                 ERROR
+sh4.s                -isa=sh2e-up              sh4
+sh4.s                -isa=sh3-dsp              ERROR
+sh4.s                -isa=sh3-dsp-up           ERROR
+sh4.s                -isa=sh3-nommu            ERROR
+sh4.s                -isa=sh3-nommu-up         sh4
+sh4.s                -isa=sh3                  ERROR
+sh4.s                -isa=sh3-up               sh4
+sh4.s                -isa=sh3e                 ERROR
+sh4.s                -isa=sh3e-up              sh4
+sh4.s                -isa=sh4-nofpu            ERROR
+sh4.s                -isa=sh4-nofpu-up         sh4
+sh4.s                -isa=sh4-nommu-nofpu      ERROR
+sh4.s                -isa=sh4-nommu-nofpu-up   sh4
+sh4.s                -isa=sh4                  sh4
+sh4.s                -isa=sh4-up               sh4
+sh4.s                -isa=sh4a-nofpu           ERROR
+sh4.s                -isa=sh4a-nofpu-up        sh4a
+sh4.s                -isa=sh4a                 sh4a
+sh4.s                -isa=sh4a-up              sh4a
+sh4.s                -isa=sh4al-dsp            ERROR
+sh4.s                -isa=sh4al-dsp-up         ERROR
+sh4a-nofpu.s         default-options           sh4a-nofpu
+sh4a-nofpu.s         -dsp                      sh4a-nofpu
+sh4a-nofpu.s         -isa=any                  sh4a-nofpu
+sh4a-nofpu.s         -isa=dsp                  sh4a-nofpu
+sh4a-nofpu.s         -isa=fp                   sh4a-nofpu
+sh4a-nofpu.s         -isa=sh-dsp               ERROR
+sh4a-nofpu.s         -isa=sh-dsp-up            sh4al-dsp
+sh4a-nofpu.s         -isa=sh                   ERROR
+sh4a-nofpu.s         -isa=sh-up                sh4a-nofpu
+sh4a-nofpu.s         -isa=sh2                  ERROR
+sh4a-nofpu.s         -isa=sh2-up               sh4a-nofpu
+sh4a-nofpu.s         -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4a-nofpu.s         -isa=sh2a-nofpu-or-sh3-nommu-up sh4a-nofpu
+sh4a-nofpu.s         -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4a-nofpu.s         -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a-nofpu
+sh4a-nofpu.s         -isa=sh2a-nofpu           ERROR
+sh4a-nofpu.s         -isa=sh2a-nofpu-up        ERROR
+sh4a-nofpu.s         -isa=sh2a-or-sh3e         ERROR
+sh4a-nofpu.s         -isa=sh2a-or-sh3e-up      sh4a
+sh4a-nofpu.s         -isa=sh2a-or-sh4          ERROR
+sh4a-nofpu.s         -isa=sh2a-or-sh4-up       sh4a
+sh4a-nofpu.s         -isa=sh2a                 ERROR
+sh4a-nofpu.s         -isa=sh2a-up              ERROR
+sh4a-nofpu.s         -isa=sh2e                 ERROR
+sh4a-nofpu.s         -isa=sh2e-up              sh4a
+sh4a-nofpu.s         -isa=sh3-dsp              ERROR
+sh4a-nofpu.s         -isa=sh3-dsp-up           sh4al-dsp
+sh4a-nofpu.s         -isa=sh3-nommu            ERROR
+sh4a-nofpu.s         -isa=sh3-nommu-up         sh4a-nofpu
+sh4a-nofpu.s         -isa=sh3                  ERROR
+sh4a-nofpu.s         -isa=sh3-up               sh4a-nofpu
+sh4a-nofpu.s         -isa=sh3e                 ERROR
+sh4a-nofpu.s         -isa=sh3e-up              sh4a
+sh4a-nofpu.s         -isa=sh4-nofpu            ERROR
+sh4a-nofpu.s         -isa=sh4-nofpu-up         sh4a-nofpu
+sh4a-nofpu.s         -isa=sh4-nommu-nofpu      ERROR
+sh4a-nofpu.s         -isa=sh4-nommu-nofpu-up   sh4a-nofpu
+sh4a-nofpu.s         -isa=sh4                  ERROR
+sh4a-nofpu.s         -isa=sh4-up               sh4a
+sh4a-nofpu.s         -isa=sh4a-nofpu           sh4a-nofpu
+sh4a-nofpu.s         -isa=sh4a-nofpu-up        sh4a-nofpu
+sh4a-nofpu.s         -isa=sh4a                 sh4a
+sh4a-nofpu.s         -isa=sh4a-up              sh4a
+sh4a-nofpu.s         -isa=sh4al-dsp            sh4al-dsp
+sh4a-nofpu.s         -isa=sh4al-dsp-up         sh4al-dsp
+sh4a.s               default-options           sh4a
+sh4a.s               -dsp                      ERROR
+sh4a.s               -isa=any                  sh4a
+sh4a.s               -isa=dsp                  ERROR
+sh4a.s               -isa=fp                   sh4a
+sh4a.s               -isa=sh-dsp               ERROR
+sh4a.s               -isa=sh-dsp-up            ERROR
+sh4a.s               -isa=sh                   ERROR
+sh4a.s               -isa=sh-up                sh4a
+sh4a.s               -isa=sh2                  ERROR
+sh4a.s               -isa=sh2-up               sh4a
+sh4a.s               -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4a.s               -isa=sh2a-nofpu-or-sh3-nommu-up sh4a
+sh4a.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4a.s               -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4a
+sh4a.s               -isa=sh2a-nofpu           ERROR
+sh4a.s               -isa=sh2a-nofpu-up        ERROR
+sh4a.s               -isa=sh2a-or-sh3e         ERROR
+sh4a.s               -isa=sh2a-or-sh3e-up      sh4a
+sh4a.s               -isa=sh2a-or-sh4          ERROR
+sh4a.s               -isa=sh2a-or-sh4-up       sh4a
+sh4a.s               -isa=sh2a                 ERROR
+sh4a.s               -isa=sh2a-up              ERROR
+sh4a.s               -isa=sh2e                 ERROR
+sh4a.s               -isa=sh2e-up              sh4a
+sh4a.s               -isa=sh3-dsp              ERROR
+sh4a.s               -isa=sh3-dsp-up           ERROR
+sh4a.s               -isa=sh3-nommu            ERROR
+sh4a.s               -isa=sh3-nommu-up         sh4a
+sh4a.s               -isa=sh3                  ERROR
+sh4a.s               -isa=sh3-up               sh4a
+sh4a.s               -isa=sh3e                 ERROR
+sh4a.s               -isa=sh3e-up              sh4a
+sh4a.s               -isa=sh4-nofpu            ERROR
+sh4a.s               -isa=sh4-nofpu-up         sh4a
+sh4a.s               -isa=sh4-nommu-nofpu      ERROR
+sh4a.s               -isa=sh4-nommu-nofpu-up   sh4a
+sh4a.s               -isa=sh4                  ERROR
+sh4a.s               -isa=sh4-up               sh4a
+sh4a.s               -isa=sh4a-nofpu           ERROR
+sh4a.s               -isa=sh4a-nofpu-up        sh4a
+sh4a.s               -isa=sh4a                 sh4a
+sh4a.s               -isa=sh4a-up              sh4a
+sh4a.s               -isa=sh4al-dsp            ERROR
+sh4a.s               -isa=sh4al-dsp-up         ERROR
+sh4al-dsp.s          default-options           ERROR
+sh4al-dsp.s          -dsp                      sh4al-dsp
+sh4al-dsp.s          -isa=any                  sh4al-dsp
+sh4al-dsp.s          -isa=dsp                  sh4al-dsp
+sh4al-dsp.s          -isa=fp                   ERROR
+sh4al-dsp.s          -isa=sh-dsp               ERROR
+sh4al-dsp.s          -isa=sh-dsp-up            sh4al-dsp
+sh4al-dsp.s          -isa=sh                   ERROR
+sh4al-dsp.s          -isa=sh-up                sh4al-dsp
+sh4al-dsp.s          -isa=sh2                  ERROR
+sh4al-dsp.s          -isa=sh2-up               sh4al-dsp
+sh4al-dsp.s          -isa=sh2a-nofpu-or-sh3-nommu ERROR
+sh4al-dsp.s          -isa=sh2a-nofpu-or-sh3-nommu-up sh4al-dsp
+sh4al-dsp.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu ERROR
+sh4al-dsp.s          -isa=sh2a-nofpu-or-sh4-nommu-nofpu-up sh4al-dsp
+sh4al-dsp.s          -isa=sh2a-nofpu           ERROR
+sh4al-dsp.s          -isa=sh2a-nofpu-up        ERROR
+sh4al-dsp.s          -isa=sh2a-or-sh3e         ERROR
+sh4al-dsp.s          -isa=sh2a-or-sh3e-up      ERROR
+sh4al-dsp.s          -isa=sh2a-or-sh4          ERROR
+sh4al-dsp.s          -isa=sh2a-or-sh4-up       ERROR
+sh4al-dsp.s          -isa=sh2a                 ERROR
+sh4al-dsp.s          -isa=sh2a-up              ERROR
+sh4al-dsp.s          -isa=sh2e                 ERROR
+sh4al-dsp.s          -isa=sh2e-up              ERROR
+sh4al-dsp.s          -isa=sh3-dsp              ERROR
+sh4al-dsp.s          -isa=sh3-dsp-up           sh4al-dsp
+sh4al-dsp.s          -isa=sh3-nommu            ERROR
+sh4al-dsp.s          -isa=sh3-nommu-up         sh4al-dsp
+sh4al-dsp.s          -isa=sh3                  ERROR
+sh4al-dsp.s          -isa=sh3-up               sh4al-dsp
+sh4al-dsp.s          -isa=sh3e                 ERROR
+sh4al-dsp.s          -isa=sh3e-up              ERROR
+sh4al-dsp.s          -isa=sh4-nofpu            ERROR
+sh4al-dsp.s          -isa=sh4-nofpu-up         sh4al-dsp
+sh4al-dsp.s          -isa=sh4-nommu-nofpu      ERROR
+sh4al-dsp.s          -isa=sh4-nommu-nofpu-up   sh4al-dsp
+sh4al-dsp.s          -isa=sh4                  ERROR
+sh4al-dsp.s          -isa=sh4-up               ERROR
+sh4al-dsp.s          -isa=sh4a-nofpu           ERROR
+sh4al-dsp.s          -isa=sh4a-nofpu-up        sh4al-dsp
+sh4al-dsp.s          -isa=sh4a                 ERROR
+sh4al-dsp.s          -isa=sh4a-up              ERROR
+sh4al-dsp.s          -isa=sh4al-dsp            sh4al-dsp
+sh4al-dsp.s          -isa=sh4al-dsp-up         sh4al-dsp
diff --git a/gas/testsuite/gas/sh/arch/sh-dsp.s b/gas/testsuite/gas/sh/arch/sh-dsp.s
new file mode 100644
index 000000000000..03b71feee9e2
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh-dsp.s
@@ -0,0 +1,270 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh_dsp:
+! Instructions introduced into sh-dsp
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh.s b/gas/testsuite/gas/sh/arch/sh.s
new file mode 100644
index 000000000000..cad2da172897
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh.s
@@ -0,0 +1,153 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh:
+! Instructions introduced into sh
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+
+! Instructions inherited from ancestors: 
diff --git a/gas/testsuite/gas/sh/arch/sh2.s b/gas/testsuite/gas/sh/arch/sh2.s
new file mode 100644
index 000000000000..66896f078245
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2.s
@@ -0,0 +1,164 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2:
+! Instructions introduced into sh2
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+
+! Instructions inherited from ancestors: sh
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
new file mode 100644
index 000000000000..b5c13c333ba3
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
@@ -0,0 +1,166 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu-or-sh3-nommu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh3-nommu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu_or_sh3_nommu:
+! Instructions introduced into sh2a-nofpu-or-sh3-nommu
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
new file mode 100644
index 000000000000..392b60b38681
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
@@ -0,0 +1,167 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh4-nommu-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu_or_sh4_nommu_nofpu:
+! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
new file mode 100644
index 000000000000..b3b06ed59b63
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
@@ -0,0 +1,219 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu:
+! Instructions introduced into sh2a-nofpu
+	ldc r5,TBR                ;!/* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	mov.b R0,@r4+             ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b @-r5,R0             ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.b @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */  {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l R0,@r4+             ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l @-r5,R0             ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */  {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w R0,@r4+             ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w @-r5,R0             ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */  {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	stc TBR,r4                ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	bclr #4, r4               ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bclr.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */  {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bld #4, r4                ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bld.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */  {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bset #4, r4               ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bset.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */  {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bst #4, r4                ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bst.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */  {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	clips.b r4                ;!/* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
+	clips.w r4                ;!/* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
+	clipu.b r4                ;!/* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
+	clipu.w r4                ;!/* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
+	divs R0,r4                ;!/* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
+	divu R0,r4                ;!/* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
+	jsr/n @r5                 ;!/* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
+	jsr/n @@(8,TBR)           ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
+	ldbank @r5,R0             ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
+	movrt r4                  ;!/* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
+	mulr R0,r4                ;!/* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
+	nott                      ;!/* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
+	resbank                   ;!/* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
+	rts/n                     ;!/* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
+	rtv/n r5                  ;!/* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
+	stbank R0,@r4             ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
+	band.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */  {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bandnot.b #4,@(2048,r4)   ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bldnot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bor.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bornot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bxor.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	movi20 #4,r4              ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */  {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
+	movi20s #1024,r4          ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */  {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
+	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
new file mode 100644
index 000000000000..5542c49e0cb6
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
@@ -0,0 +1,203 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-or-sh3e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-or-sh3e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_or_sh3e:
+! Instructions introduced into sh2a-or-sh3e
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
new file mode 100644
index 000000000000..497ad048fcbb
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
@@ -0,0 +1,231 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-or-sh4 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-or-sh4.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_or_sh4:
+! Instructions introduced into sh2a-or-sh4
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
new file mode 100644
index 000000000000..70fa023bd166
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2a.s
@@ -0,0 +1,287 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a:
+! Instructions introduced into sh2a
+	fmov.d xd4,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
+	fmov.d @(2048,r5),xd2     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */  {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
+	fmov.s fr2,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
+	fmov.s @(2048,r5),fr1     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */  {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r5,TBR                ;!/* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.b R0,@r4+             ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b @-r5,R0             ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.b @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */  {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.l R0,@r4+             ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l @-r5,R0             ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */  {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mov.w R0,@r4+             ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w @-r5,R0             ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */  {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc TBR,r4                ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+	bclr #4, r4               ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bclr.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */  {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bld #4, r4                ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bld.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */  {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bset #4, r4               ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bset.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */  {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bst #4, r4                ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bst.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */  {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	clips.b r4                ;!/* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
+	clips.w r4                ;!/* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
+	clipu.b r4                ;!/* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
+	clipu.w r4                ;!/* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
+	divs R0,r4                ;!/* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
+	divu R0,r4                ;!/* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
+	jsr/n @r5                 ;!/* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
+	jsr/n @@(8,TBR)           ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
+	ldbank @r5,R0             ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
+	movrt r4                  ;!/* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
+	mulr R0,r4                ;!/* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
+	nott                      ;!/* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
+	resbank                   ;!/* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
+	rts/n                     ;!/* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
+	rtv/n r5                  ;!/* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
+	stbank R0,@r4             ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
+	band.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */  {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bandnot.b #4,@(2048,r4)   ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bldnot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bor.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bornot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bxor.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	movi20 #4,r4              ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */  {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
+	movi20s #1024,r4          ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */  {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
+	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
diff --git a/gas/testsuite/gas/sh/arch/sh2e.s b/gas/testsuite/gas/sh/arch/sh2e.s
new file mode 100644
index 000000000000..75a11ad399bc
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh2e.s
@@ -0,0 +1,200 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2e:
+! Instructions introduced into sh2e
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
new file mode 100644
index 000000000000..3837193d4e5b
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s
@@ -0,0 +1,285 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3_dsp:
+! Instructions introduced into sh3-dsp
+
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
new file mode 100644
index 000000000000..346ffe60cd8f
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s
@@ -0,0 +1,178 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3-nommu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3-nommu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3-nommu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3_nommu:
+! Instructions introduced into sh3-nommu
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
new file mode 100644
index 000000000000..2fff52b5c288
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh3.s
@@ -0,0 +1,179 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3:
+! Instructions introduced into sh3
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
new file mode 100644
index 000000000000..6fcd064995d8
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh3e.s
@@ -0,0 +1,216 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3e:
+! Instructions introduced into sh3e
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
new file mode 100644
index 000000000000..d71b0df410a2
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
@@ -0,0 +1,192 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4_nofpu:
+! Instructions introduced into sh4-nofpu
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
new file mode 100644
index 000000000000..1caf830d84b2
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
@@ -0,0 +1,191 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4-nommu-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4-nommu-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4_nommu_nofpu:
+! Instructions introduced into sh4-nommu-nofpu
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
new file mode 100644
index 000000000000..0044f2748612
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4.s
@@ -0,0 +1,261 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4:
+! Instructions introduced into sh4
+	fipr fv4,fv0              ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
+	frchg                     ;!/* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
+	fsca FPUL,dr2             ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
+	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
+	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
new file mode 100644
index 000000000000..7c2850b441c2
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
@@ -0,0 +1,199 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4a-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4a-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4a-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4a_nofpu:
+! Instructions introduced into sh4a-nofpu
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
new file mode 100644
index 000000000000..a56c8e72b42a
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4a.s
@@ -0,0 +1,269 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4a but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4a.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4a.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4a:
+! Instructions introduced into sh4a
+	fpchg                     ;!/* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fipr fv4,fv0              ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	frchg                     ;!/* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
+	fsca FPUL,dr2             ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
new file mode 100644
index 000000000000..c2b4087e8213
--- /dev/null
+++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
@@ -0,0 +1,341 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4al-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4al-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4al-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4al_dsp:
+! Instructions introduced into sh4al-dsp
+	clrdmxy                   ;!/* 0000000010001000 clrdmxy             */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}
+	ldrc r5                   ;!/* 0100mmmm00110100 ldrc <REG_M>        */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}
+	ldrc #4                   ;!/* 10001010i8*1.... ldrc #<imm>         */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}
+	setdmx                    ;!/* 0000000010011000 setdmx              */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}
+	setdmy                    ;!/* 0000000011001000 setdmy              */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}
+	movx.w @r1,y1             ;!/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}
+	movx.w @r1+,y1            ;!/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}
+	movx.w @r1+r8,y1          ;!/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}
+	movx.w a0,@r1             ;!/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}
+	movx.w a0,@r1+            ;!/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}
+	movx.w a0,@r1+r8          ;!/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}
+	movx.l @r1,y1             ;!/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}
+	movx.l @r1+,y1            ;!/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}
+	movx.l @r1+r8,y1          ;!/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}
+	movx.l a0,@r1             ;!/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}
+	movx.l a0,@r1+            ;!/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}
+	movx.l a0,@r1+r8          ;!/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}
+	movy.w @r3,y1             ;!/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}
+	movy.w @r3+,y1            ;!/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}
+	movy.w @r3+r9,y1          ;!/* nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}
+	movy.w a0,@r3             ;!/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}
+	movy.w a0,@r3+            ;!/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}
+	movy.w a0,@r3+r9          ;!/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}
+	movy.l @r3,y1             ;!/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}
+	movy.l @r3+,y1            ;!/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}
+	movy.l @r3+r9,y1          ;!/* nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}
+	movy.l a0,@r3             ;!/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}
+	movy.l a0,@r3+            ;!/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}
+	movy.l a0,@r3+r9          ;!/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}
+	dct pabs x1,m0            ;!/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}
+	dct pabs y0,m0            ;!/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}
+	dct prnd x1,m0            ;!/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}
+	dct prnd y0,m0            ;!/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}
+	dct psub y0,x1,m0         ;!/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */  {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}
+	dct pswap x1,m0           ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */  {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
+	dct pswap y0,m0           ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */  {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
+
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	mov.l @(8,PC),r4          ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mova @(8,PC),R0           ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
diff --git a/gas/testsuite/gas/sh/basic.exp b/gas/testsuite/gas/sh/basic.exp
index 1e72ff1fdaca..093048b87dc9 100644
--- a/gas/testsuite/gas/sh/basic.exp
+++ b/gas/testsuite/gas/sh/basic.exp
@@ -13,14 +13,14 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
 
 # Written by Cygnus Support.
 
-if [istarget "sh*-*-linux-gnu"] {
+if [istarget "sh*-*-linux-*"] {
     global ASFLAGS
     set ASFLAGS "$ASFLAGS -big"
 }
@@ -131,6 +131,8 @@ if [istarget sh*-*-*] then {
     # dumped as sh4.
     if {[istarget sh*-*coff] || [istarget sh*-pe*] || [istarget sh*-rtems]} then {
 	run_dump_test "pcrel-coff"
+    } elseif {[istarget sh*-hms] } {
+	run_dump_test "pcrel-hms"
     } elseif {![istarget sh64*-*-*] && ![istarget sh5*-*-*] } {
 	# Test DSP instructions
 	run_dump_test "dsp"
@@ -147,6 +149,8 @@ if [istarget sh*-*-*] then {
 
 	    run_dump_test "sh4a-dsp"
 	    run_dump_test "sh4al-dsp"
+
+	    run_dump_test "sh2a"
 	}
 
 	run_dump_test "pic"
@@ -158,8 +162,11 @@ if [istarget sh*-*-*] then {
 
 	run_dump_test "tlsnopic"
 
-	# Test -renesas.
+	# Test --renesas.
 	run_dump_test "renesas-1"
+
+	# Test --allow-reg-prefix.
+	run_dump_test "reg-prefix"
     }
 }
 
diff --git a/gas/testsuite/gas/sh/err.exp b/gas/testsuite/gas/sh/err.exp
index d012ad4fc08d..d5ffa635bf7c 100644
--- a/gas/testsuite/gas/sh/err.exp
+++ b/gas/testsuite/gas/sh/err.exp
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # binutils@sources.redhat.com
diff --git a/gas/testsuite/gas/sh/pcrel-hms.d b/gas/testsuite/gas/sh/pcrel-hms.d
new file mode 100644
index 000000000000..12df66771932
--- /dev/null
+++ b/gas/testsuite/gas/sh/pcrel-hms.d
@@ -0,0 +1,29 @@
+#as: -big
+#source: pcrel.s
+#objdump: -d -EB
+#name: PC-relative loads
+#stderr: pcrel.l
+
+.*:     file format .*sh.*
+
+Disassembly of section .text:
+
+00000000 <code>:
+   0:	d0 04       	mov\.l	14 <litpool>,r0	! 0xffffffec
+   2:	d1 05       	mov\.l	18 <litpool\+0x4>,r1	! 0x90009
+   4:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   6:	d1 03       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   8:	c7 02       	mova	14 <litpool>,r0
+   a:	61 02       	mov\.l	@r0,r1
+   c:	d1 01       	mov\.l	14 <litpool>,r1	! 0xffffffec
+   e:	01 03       	bsrf	r1
+  10:	00 09       	nop	
+  12:	00 09       	nop	
+
+00000014 <litpool>:
+  14:	ff ff       	\.word 0xffff
+  16:	ff ec       	fmov	fr14,fr15
+  18:	00 09       	nop	
+  1a:	00 09       	nop	
+  1c:	00 09       	nop	
+  1e:	00 09       	nop	
diff --git a/gas/testsuite/gas/sh/pcrel2.d b/gas/testsuite/gas/sh/pcrel2.d
index 60a01df1cb7e..21df0aa7d2f2 100644
--- a/gas/testsuite/gas/sh/pcrel2.d
+++ b/gas/testsuite/gas/sh/pcrel2.d
@@ -8,8 +8,8 @@ Disassembly of section \.text:
 
 00000000 <code>:
    0:	8b 01       	bf	6 <foo>
-   2:	d0 02       	mov\.l	c <bar>,r0	! 0x6
-   4:	90 02       	mov\.w	c <bar>,r0	! 0x0
+   2:	d0 02       	mov\.l	c <bar>,r0	! 0x6 .*
+   4:	90 02       	mov\.w	c <bar>,r0	! 0x0 .*
 
 00000006 <foo>:
    6:	af fe       	bra	6 <foo>
diff --git a/gas/testsuite/gas/sh/reg-prefix.d b/gas/testsuite/gas/sh/reg-prefix.d
new file mode 100644
index 000000000000..1821bbce3b2b
--- /dev/null
+++ b/gas/testsuite/gas/sh/reg-prefix.d
@@ -0,0 +1,10 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#as: --allow-reg-prefix -little
+#name: SH --allow-reg-prefix option
+# Test SH register names prefixed with $:
+
+.*:     file format elf.*sh.*
+
+Disassembly of section .text:
+0x00000000 12 60       	mov\.l	@r1,r0
+
diff --git a/gas/testsuite/gas/sh/reg-prefix.s b/gas/testsuite/gas/sh/reg-prefix.s
new file mode 100644
index 000000000000..8600af126b30
--- /dev/null
+++ b/gas/testsuite/gas/sh/reg-prefix.s
@@ -0,0 +1,3 @@
+        .text
+	mov.l @r1,$r0
+
diff --git a/gas/testsuite/gas/sh/sh2a.d b/gas/testsuite/gas/sh/sh2a.d
new file mode 100644
index 000000000000..b70a3dc990ec
--- /dev/null
+++ b/gas/testsuite/gas/sh/sh2a.d
@@ -0,0 +1,68 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: SH2a new instructions
+#as: -isa=sh2a
+
+dump.o:     file format elf32-sh.*
+
+Disassembly of section .text:
+0x00000000 33 79 4f ff 	band.b	#7,@\(4095,r3\)
+0x00000004 33 79 cf ff 	bandnot.b	#7,@\(4095,r3\)
+0x00000008 33 79 0f ff 	bclr.b	#7,@\(4095,r3\)
+0x0000000c 86 37       	bclr	#7,r3
+0x0000000e 33 79 3f ff 	bld.b	#7,@\(4095,r3\)
+0x00000012 87 3f       	bld	#7,r3
+0x00000014 33 79 bf ff 	bldnot.b	#7,@\(4095,r3\)
+0x00000018 33 79 5f ff 	bor.b	#7,@\(4095,r3\)
+0x0000001c 33 79 df ff 	bornot.b	#7,@\(4095,r3\)
+0x00000020 33 79 1f ff 	bset.b	#7,@\(4095,r3\)
+0x00000024 86 3f       	bset	#7,r3
+0x00000026 33 79 2f ff 	bst.b	#7,@\(4095,r3\)
+0x0000002a 87 37       	bst	#7,r3
+0x0000002c 33 79 6f ff 	bxor.b	#7,@\(4095,r3\)
+0x00000030 43 91       	clips.b	r3
+0x00000032 43 95       	clips.w	r3
+0x00000034 43 81       	clipu.b	r3
+0x00000036 43 85       	clipu.w	r3
+0x00000038 43 94       	divs	r0,r3
+0x0000003a 43 84       	divu	r0,r3
+0x0000003c 33 31 3f ff 	fmov.s	fr3,@\(16380,r3\)
+0x00000040 33 21 3f ff 	fmov.d	dr2,@\(32760,r3\)
+0x00000044 33 31 7f ff 	fmov.s	@\(16380,r3\),fr3
+0x00000048 32 31 7f ff 	fmov.d	@\(32760,r3\),dr2
+0x0000004c 43 4b       	jsr/n	@r3
+0x0000004e 83 ff       	jsr/n	@@\(1020,tbr\)
+0x00000050 43 e5       	ldbank	@r3,r0
+0x00000052 43 4a       	ldc	r3,tbr
+0x00000054 34 31 0f ff 	mov.b	r3,@\(4095,r4\)
+0x00000058 34 31 1f ff 	mov.w	r3,@\(8190,r4\)
+0x0000005c 34 31 2f ff 	mov.l	r3,@\(16380,r4\)
+0x00000060 35 41 4f ff 	mov.b	@\(4095,r4\),r5
+0x00000064 35 41 5f ff 	mov.w	@\(8190,r4\),r5
+0x00000068 35 41 6f ff 	mov.l	@\(16380,r4\),r5
+0x0000006c 43 8b       	mov.b	r0,@r3\+
+0x0000006e 43 9b       	mov.w	r0,@r3\+
+0x00000070 43 ab       	mov.l	r0,@r3\+
+0x00000072 43 cb       	mov.b	@-r3,r0
+0x00000074 43 db       	mov.w	@-r3,r0
+0x00000076 43 eb       	mov.l	@-r3,r0
+0x00000078 03 70 ff ff 	movi20	#524287,r3
+0x0000007c 03 80 00 00 	movi20	#-524288,r3
+0x00000080 03 71 ff ff 	movi20s	#134217472,r3
+0x00000084 03 81 00 00 	movi20s	#-134217728,r3
+0x00000088 43 f1       	movml.l	r3,@-r15
+0x0000008a 43 f5       	movml.l	@r15\+,r3
+0x0000008c 43 f0       	movmu.l	r3,@-r15
+0x0000008e 43 f4       	movmu.l	@r15\+,r3
+0x00000090 03 39       	movrt	r3
+0x00000092 34 31 8f ff 	movu.b	@\(4095,r3\),r4
+0x00000096 34 31 9f ff 	movu.w	@\(8190,r3\),r4
+0x0000009a 44 80       	mulr	r0,r4
+0x0000009c 00 68       	nott	
+0x0000009e 05 83       	pref	@r5
+0x000000a0 00 5b       	resbank	
+0x000000a2 00 6b       	rts/n	
+0x000000a4 03 7b       	rtv/n	r3
+0x000000a6 44 3c       	shad	r3,r4
+0x000000a8 44 3d       	shld	r3,r4
+0x000000aa 45 e1       	stbank	r0,@r5
+0x000000ac 04 4a       	stc	tbr,r4
diff --git a/gas/testsuite/gas/sh/sh2a.s b/gas/testsuite/gas/sh/sh2a.s
new file mode 100644
index 000000000000..8ded738d19cd
--- /dev/null
+++ b/gas/testsuite/gas/sh/sh2a.s
@@ -0,0 +1,96 @@
+	.text
+
+# New instructions
+
+	band.b	#7,@(4095,r3)
+
+	bandnot.b	#7,@(4095,r3)
+
+	bclr.b	#7,@(4095,r3)
+	bclr	#7,r3
+
+	bld.b	#7,@(4095,r3)
+	bld	#7,r3
+
+	bldnot.b	#7,@(4095,r3)
+
+	bor.b	#7,@(4095,r3)
+
+	bornot.b	#7,@(4095,r3)
+
+	bset.b	#7,@(4095,r3)
+	bset	#7,r3
+
+	bst.b	#7,@(4095,r3)
+	bst	#7,r3
+
+	bxor.b	#7,@(4095,r3)
+
+	clips.b	r3
+	clips.w	r3
+	clipu.b	r3
+	clipu.w	r3
+
+	divs	r0,r3
+	divu	r0,r3
+
+	fmov.s	fr3,@(4095*4,r3)
+	fmov.d	dr2,@(4095*8,r3)
+	fmov.s	@(4095*4,r3),fr3
+	fmov.d	@(4095*8,r3),dr2
+
+	jsr/n	@r3
+	jsr/n	@@(255*4,tbr)
+
+	ldbank	@r3,r0
+
+	ldc	r3,tbr
+
+	mov.b	r3,@(4095,r4)
+	mov.w	r3,@(4095*2,r4)
+	mov.l	r3,@(4095*4,r4)
+	mov.b	@(4095,r4),r5
+	mov.w	@(4095*2,r4),r5
+	mov.l	@(4095*4,r4),r5
+
+	mov.b	r0,@r3+
+	mov.w	r0,@r3+
+	mov.l	r0,@r3+
+	mov.b	@-r3,r0
+	mov.w	@-r3,r0
+	mov.l	@-r3,r0
+
+	movi20	#524287,r3
+	movi20	#-524288,r3
+	movi20s	#524287*256,r3
+	movi20s	#-524288*256,r3
+
+	movml.l	r3,@-r15
+	movml.l	@r15+,r3
+
+	movmu.l	r3,@-r15
+	movmu.l	@r15+,r3
+
+	movrt	r3
+
+	movu.b	@(4095,r3),r4
+	movu.w	@(4095*2,r3),r4
+
+	mulr	r0,r4
+
+	nott
+
+	pref	@r5
+
+	resbank
+
+	rts/n
+
+	rtv/n	r3
+
+	shad	r3,r4
+	shld	r3,r4
+
+	stbank	r0,@r5
+
+	stc	tbr,r4
diff --git a/gas/testsuite/gas/sh/sh64/datal32-3.d b/gas/testsuite/gas/sh/sh64/datal32-3.d
index 159ed41650c1..a1e3a3ce956c 100644
--- a/gas/testsuite/gas/sh/sh64/datal32-3.d
+++ b/gas/testsuite/gas/sh/sh64/datal32-3.d
@@ -24,14 +24,14 @@ Idx Name          Size      VMA       LMA       File off  Algn
   3 \.rodata       0+10  0+  0+  0+a0  2\*\*2
                   CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ 0x04 start
 0+30 l       \.text	0+ 0x04 foo
 0+38 l       \.text	0+ 0x04 foo2
 0+40 l       \.text	0+ 0x04 foo3
-0+ l    d  \.rodata	0+ 
+0+ l    d  \.rodata	0+ (|\.rodata)
 0+48 l       \.text	0+ 0x04 foo4
 0+4 l       \.rodata	0+ myrodata1
 0+50 l       \.text	0+ 0x04 foo5
diff --git a/gas/testsuite/gas/sh/sh64/datal64-3.d b/gas/testsuite/gas/sh/sh64/datal64-3.d
index 8a056cf8f0e4..a6e81299af13 100644
--- a/gas/testsuite/gas/sh/sh64/datal64-3.d
+++ b/gas/testsuite/gas/sh/sh64/datal64-3.d
@@ -24,14 +24,14 @@ Idx Name          Size      VMA               LMA               File off  Algn
   3 \.rodata       0+10  0+  0+  0+104  2\*\*2
                   CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
 SYMBOL TABLE:
-0+ l    d  \.text	0+ 
-0+ l    d  \.data	0+ 
-0+ l    d  \.bss	0+ 
+0+ l    d  \.text	0+ (|\.text)
+0+ l    d  \.data	0+ (|\.data)
+0+ l    d  \.bss	0+ (|\.bss)
 0+ l       \.text	0+ 0x04 start
 0+58 l       \.text	0+ 0x04 foo
 0+68 l       \.text	0+ 0x04 foo2
 0+78 l       \.text	0+ 0x04 foo3
-0+ l    d  \.rodata	0+ 
+0+ l    d  \.rodata	0+ (|\.rodata)
 0+88 l       \.text	0+ 0x04 foo4
 0+4 l       \.rodata	0+ myrodata1
 0+98 l       \.text	0+ 0x04 foo5
diff --git a/gas/testsuite/gas/sh/sh64/err-dsp.s b/gas/testsuite/gas/sh/sh64/err-dsp.s
index 52173a712c82..3cee009a01b3 100644
--- a/gas/testsuite/gas/sh/sh64/err-dsp.s
+++ b/gas/testsuite/gas/sh/sh64/err-dsp.s
@@ -11,5 +11,5 @@
 	.text
 start:
 	ldc r3,mod		! { dg-error "invalid operands" }
-	ldre @(16,pc)		! { dg-error "unknown opcode" }
+	ldre @(16,pc)		! { dg-error "opcode not valid for this cpu variant" }
 	lds r4,a0		! { dg-error "invalid operands" }
diff --git a/gas/testsuite/gas/sh/sh64/localcom-1.d b/gas/testsuite/gas/sh/sh64/localcom-1.d
index 8698d5e3435e..83a91b0e9c8f 100644
--- a/gas/testsuite/gas/sh/sh64/localcom-1.d
+++ b/gas/testsuite/gas/sh/sh64/localcom-1.d
@@ -6,9 +6,9 @@
 .*:     file format .*-sh64.*
 
 SYMBOL TABLE:
-0+0 l    d  \.text	0+ 
-0+0 l    d  \.data	0+ 
-0+0 l    d  \.bss	0+ 
+0+0 l    d  \.text	0+ (|\.text)
+0+0 l    d  \.data	0+ (|\.data)
+0+0 l    d  \.bss	0+ (|\.bss)
 0+0 l       \.text	0+ start
 0+c l     O \.bss	0+4 dd
 0+c l     O \.bss	0+4 d
diff --git a/gas/testsuite/gas/sh/sh64/sh64.exp b/gas/testsuite/gas/sh/sh64/sh64.exp
index 767d2d6a36dc..d6135f1c1f8d 100644
--- a/gas/testsuite/gas/sh/sh64/sh64.exp
+++ b/gas/testsuite/gas/sh/sh64/sh64.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 2000 Free Software Foundation, Inc.
+# Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
diff --git a/gas/testsuite/gas/sh/tlsd.d b/gas/testsuite/gas/sh/tlsd.d
index 5ca4ef58dbf3..b4d75974c85e 100644
--- a/gas/testsuite/gas/sh/tlsd.d
+++ b/gas/testsuite/gas/sh/tlsd.d
@@ -11,12 +11,12 @@ Disassembly of section .text:
    2:	2f e6 [ 	]*mov\.l	r14,@-r15
    4:	4f 22 [ 	]*sts\.l	pr,@-r15
    6:	c7 14 [ 	]*mova	58 <fn\+0x58>,r0
-   8:	dc 13 [ 	]*mov\.l	58 <fn\+0x58>,r12[ 	]+! 0x0
+   8:	dc 13 [ 	]*mov\.l	58 <fn\+0x58>,r12[ 	]+! 0x0 .*
    a:	3c 0c [ 	]*add	r0,r12
    c:	6e f3 [ 	]*mov	r15,r14
-   e:	d4 04 [ 	]*mov\.l	20 <fn\+0x20>,r4[ 	]+! 0x0
+   e:	d4 04 [ 	]*mov\.l	20 <fn\+0x20>,r4[ 	]+! 0x0 .*
   10:	c7 04 [ 	]*mova	24 <fn\+0x24>,r0
-  12:	d1 04 [ 	]*mov\.l	24 <fn\+0x24>,r1[ 	]+! 0x0
+  12:	d1 04 [ 	]*mov\.l	24 <fn\+0x24>,r1[ 	]+! 0x0 .*
   14:	31 0c [ 	]*add	r0,r1
   16:	41 0b [ 	]*jsr	@r1
   18:	34 cc [ 	]*add	r12,r4
@@ -26,9 +26,9 @@ Disassembly of section .text:
 	\.\.\.
 [ 	]+20: R_SH_TLS_GD_32	foo
 [ 	]+24: R_SH_PLT32	__tls_get_addr
-  28:	d4 03 [ 	]*mov\.l	38 <fn\+0x38>,r4[ 	]+! 0x0
+  28:	d4 03 [ 	]*mov\.l	38 <fn\+0x38>,r4[ 	]+! 0x0 .*
   2a:	c7 04 [ 	]*mova	3c <fn\+0x3c>,r0
-  2c:	d1 03 [ 	]*mov\.l	3c <fn\+0x3c>,r1[ 	]+! 0x0
+  2c:	d1 03 [ 	]*mov\.l	3c <fn\+0x3c>,r1[ 	]+! 0x0 .*
   2e:	31 0c [ 	]*add	r0,r1
   30:	41 0b [ 	]*jsr	@r1
   32:	34 cc [ 	]*add	r12,r4
@@ -38,10 +38,10 @@ Disassembly of section .text:
 [ 	]+38: R_SH_TLS_LD_32	bar
 [ 	]+3c: R_SH_PLT32	__tls_get_addr
   40:	e2 01 [ 	]*mov	#1,r2
-  42:	d1 06 [ 	]*mov\.l	5c <fn\+0x5c>,r1[ 	]+! 0x0
+  42:	d1 06 [ 	]*mov\.l	5c <fn\+0x5c>,r1[ 	]+! 0x0 .*
   44:	30 1c [ 	]*add	r1,r0
   46:	20 22 [ 	]*mov\.l	r2,@r0
-  48:	d1 05 [ 	]*mov\.l	60 <fn\+0x60>,r1[ 	]+! 0x0
+  48:	d1 05 [ 	]*mov\.l	60 <fn\+0x60>,r1[ 	]+! 0x0 .*
   4a:	30 1c [ 	]*add	r1,r0
   4c:	6f e3 [ 	]*mov	r14,r15
   4e:	4f 26 [ 	]*lds\.l	@r15\+,pr
diff --git a/gas/testsuite/gas/sh/tlsnopic.d b/gas/testsuite/gas/sh/tlsnopic.d
index c987939c41cd..69131276ccee 100644
--- a/gas/testsuite/gas/sh/tlsnopic.d
+++ b/gas/testsuite/gas/sh/tlsnopic.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
    0:	2f e6 [ 	]*mov\.l	r14,@-r15
    2:	6e f3 [ 	]*mov	r15,r14
    4:	01 12 [ 	]*stc	gbr,r1
-   6:	d0 02 [ 	]*mov\.l	10 <fn\+0x10>,r0[ 	]+! 0x0
+   6:	d0 02 [ 	]*mov\.l	10 <fn\+0x10>,r0[ 	]+! 0x0 .*
    8:	30 1c [ 	]*add	r1,r0
    a:	6f e3 [ 	]*mov	r14,r15
    c:	00 0b [ 	]*rts	
diff --git a/gas/testsuite/gas/sh/tlspic.d b/gas/testsuite/gas/sh/tlspic.d
index b15e06318540..207ab1a2f4b2 100644
--- a/gas/testsuite/gas/sh/tlspic.d
+++ b/gas/testsuite/gas/sh/tlspic.d
@@ -11,9 +11,9 @@ Disassembly of section .text:
    2:	2f e6 [ 	]*mov\.l	r14,@-r15
    4:	6e f3 [ 	]*mov	r15,r14
    6:	c7 08 [ 	]*mova	28 <fn\+0x28>,r0
-   8:	dc 07 [ 	]*mov\.l	28 <fn\+0x28>,r12[ 	]+! 0x0
+   8:	dc 07 [ 	]*mov\.l	28 <fn\+0x28>,r12[ 	]+! 0x0 .*
    a:	3c 0c [ 	]*add	r0,r12
-   c:	d0 02 [ 	]*mov\.l	18 <fn\+0x18>,r0[ 	]+! 0x0
+   c:	d0 02 [ 	]*mov\.l	18 <fn\+0x18>,r0[ 	]+! 0x0 .*
    e:	01 12 [ 	]*stc	gbr,r1
   10:	00 ce [ 	]*mov\.l	@\(r0,r12\),r0
   12:	a0 03 [ 	]*bra	1c <fn\+0x1c>
diff --git a/gas/testsuite/gas/sparc/rdhpr.d b/gas/testsuite/gas/sparc/rdhpr.d
new file mode 100644
index 000000000000..fbbd76dab8ea
--- /dev/null
+++ b/gas/testsuite/gas/sparc/rdhpr.d
@@ -0,0 +1,15 @@
+#as: -64 -Av9
+#objdump: -dr
+#name: sparc64 rdhpr
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	83 48 00 00 	rdhpr  %hpstate, %g1
+   4:	85 48 40 00 	rdhpr  %htstate, %g2
+   8:	87 48 c0 00 	rdhpr  %hintp, %g3
+   c:	89 49 40 00 	rdhpr  %htba, %g4
+  10:	8b 49 80 00 	rdhpr  %hver, %g5
+  14:	8d 4f c0 00 	rdhpr  %hstick_cmpr, %g6
diff --git a/gas/testsuite/gas/sparc/rdhpr.s b/gas/testsuite/gas/sparc/rdhpr.s
new file mode 100644
index 000000000000..5e22f07f351b
--- /dev/null
+++ b/gas/testsuite/gas/sparc/rdhpr.s
@@ -0,0 +1,8 @@
+# Test rdpr
+	.text
+	rdhpr %hpstate,%g1
+	rdhpr %htstate,%g2
+	rdhpr %hintp,%g3
+	rdhpr %htba,%g4
+	rdhpr %hver,%g5
+	rdhpr %hstick_cmpr,%g6
diff --git a/gas/testsuite/gas/sparc/rdpr.d b/gas/testsuite/gas/sparc/rdpr.d
index e36ea9b5f4bb..6ddc24a4469c 100644
--- a/gas/testsuite/gas/sparc/rdpr.d
+++ b/gas/testsuite/gas/sparc/rdpr.d
@@ -23,4 +23,5 @@ Disassembly of section .text:
   34:	9d 53 40 00 	rdpr  %otherwin, %sp
   38:	9f 53 80 00 	rdpr  %wstate, %o7
   3c:	a1 53 c0 00 	rdpr  %fq, %l0
-  40:	a3 57 c0 00 	rdpr  %ver, %l1
+  40:	a3 54 00 00 	rdpr  %gl, %l1
+  44:	a5 57 c0 00 	rdpr  %ver, %l2
diff --git a/gas/testsuite/gas/sparc/rdpr.s b/gas/testsuite/gas/sparc/rdpr.s
index f44619cea4de..15660359c7a1 100644
--- a/gas/testsuite/gas/sparc/rdpr.s
+++ b/gas/testsuite/gas/sparc/rdpr.s
@@ -16,4 +16,5 @@
 	rdpr %otherwin,%o6
 	rdpr %wstate,%o7
 	rdpr %fq,%l0
-	rdpr %ver,%l1
+	rdpr %gl,%l1
+	rdpr %ver,%l2
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 4b16f394103b..a2e362dbba11 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -13,11 +13,11 @@ proc gas_64_check { } {
     global srcdir
 
     catch "exec $srcdir/lib/run $NM $NMFLAGS --help" nm_help
-    return [regexp "elf64\[_-\]sparc" $nm_help];
+    return [regexp "elf64\[_-\]sparc" $nm_help]
 }
 
 proc sparc_elf_setup { } {
-    setup_xfail "sparc*-*-*aout*" "sparc*-*-sunos4*" "sparc*-*-vxworks*"
+    setup_xfail "sparc*-*-*aout*" "sparc*-*-sunos4*"
     setup_xfail "sparc*-fujitsu-none" "sparc*-*-*n*bsd*"
     setup_xfail "sparc*-*-coff" "sparc*-*-lynxos*"
     clear_xfail "sparc64*-*-*n*bsd*"
@@ -40,13 +40,20 @@ if [istarget sparc*-*-*] {
 	run_dump_test "set64"
 	run_dump_test "synth64"
 	run_dump_test "rdpr"
+	run_dump_test "rdhpr"
 	run_dump_test "wrpr"
+	run_dump_test "wrhpr"
+	run_dump_test "window"
 	run_dump_test "reloc64"
 	run_dump_test "pcrel64"
 	run_dump_test "plt64"
     }
 }
 
+if [istarget sparc-*-vxworks*] {
+    run_dump_test "vxworks-pic"
+}
+
 if [istarget sparclet*-*-*] {
     run_dump_test "splet"
     run_dump_test "splet-2"
diff --git a/gas/testsuite/gas/sparc/vxworks-pic.d b/gas/testsuite/gas/sparc/vxworks-pic.d
new file mode 100644
index 000000000000..7e238fbdc45e
--- /dev/null
+++ b/gas/testsuite/gas/sparc/vxworks-pic.d
@@ -0,0 +1,27 @@
+#as: -KPIC
+#objdump: -dr
+#name: VxWorks PIC
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	2f 00 00 00 	sethi  %hi\(0\), %l7
+			0: R_SPARC_HI22	__GOTT_BASE__
+   4:	ee 05 e0 00 	ld  \[ %l7 \], %l7
+			4: R_SPARC_LO10	__GOTT_BASE__
+   8:	ee 05 e0 00 	ld  \[ %l7 \], %l7
+			8: R_SPARC_LO10	__GOTT_INDEX__
+   c:	03 00 00 00 	sethi  %hi\(0\), %g1
+			c: R_SPARC_HI22	__GOTT_BASE__
+  10:	82 10 60 00 	mov  %g1, %g1	! 0x0
+			10: R_SPARC_LO10	__GOTT_BASE__
+  14:	03 00 00 00 	sethi  %hi\(0\), %g1
+			14: R_SPARC_HI22	__GOTT_INDEX__
+  18:	82 10 60 00 	mov  %g1, %g1	! 0x0
+			18: R_SPARC_LO10	__GOTT_INDEX__
+  1c:	03 00 00 00 	sethi  %hi\(0\), %g1
+			1c: R_SPARC_GOT22	__GOT_BASE__
+  20:	82 10 60 00 	mov  %g1, %g1	! 0x0
+			20: R_SPARC_GOT10	__GOT_BASE__
diff --git a/gas/testsuite/gas/sparc/vxworks-pic.s b/gas/testsuite/gas/sparc/vxworks-pic.s
new file mode 100644
index 000000000000..9d49e0079043
--- /dev/null
+++ b/gas/testsuite/gas/sparc/vxworks-pic.s
@@ -0,0 +1,11 @@
+	sethi	%hi(__GOTT_BASE__), %l7
+	ld	[%l7+%lo(__GOTT_BASE__)],%l7
+	ld	[%l7+%lo(__GOTT_INDEX__)],%l7
+
+	sethi	%hi(__GOTT_BASE__), %g1
+	or	%g1, %lo(__GOTT_BASE__), %g1
+	sethi	%hi(__GOTT_INDEX__), %g1
+	or	%g1, %lo(__GOTT_INDEX__), %g1
+
+	sethi	%hi(__GOT_BASE__), %g1
+	or	%g1, %lo(__GOT_BASE__), %g1
diff --git a/gas/testsuite/gas/sparc/window.d b/gas/testsuite/gas/sparc/window.d
new file mode 100644
index 000000000000..31d3daeabcf4
--- /dev/null
+++ b/gas/testsuite/gas/sparc/window.d
@@ -0,0 +1,15 @@
+#as: -64 -Av9
+#objdump: -dr
+#name: sparc64 window
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	81 88 00 00 	saved 
+   4:	83 88 00 00 	restored 
+   8:	85 88 00 00 	allclean 
+   c:	87 88 00 00 	otherw 
+  10:	89 88 00 00 	normalw 
+  14:	8b 88 00 00 	invalw 
diff --git a/gas/testsuite/gas/sparc/window.s b/gas/testsuite/gas/sparc/window.s
new file mode 100644
index 000000000000..38c0410db9a6
--- /dev/null
+++ b/gas/testsuite/gas/sparc/window.s
@@ -0,0 +1,8 @@
+# Test window
+	.text
+	saved
+	restored
+	allclean
+	otherw
+	normalw
+	invalw
diff --git a/gas/testsuite/gas/sparc/wrhpr.d b/gas/testsuite/gas/sparc/wrhpr.d
new file mode 100644
index 000000000000..a9ec2b6bcd6d
--- /dev/null
+++ b/gas/testsuite/gas/sparc/wrhpr.d
@@ -0,0 +1,14 @@
+#as: -64 -Av9
+#objdump: -dr
+#name: sparc64 wrhpr
+
+.*: +file format .*sparc.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	81 98 40 00 	wrhpr  %g1, %hpstate
+   4:	83 98 80 00 	wrhpr  %g2, %htstate
+   8:	87 98 c0 00 	wrhpr  %g3, %hintp
+   c:	8b 99 00 00 	wrhpr  %g4, %htba
+  10:	bf 99 40 00 	wrhpr  %g5, %hstick_cmpr
diff --git a/gas/testsuite/gas/sparc/wrhpr.s b/gas/testsuite/gas/sparc/wrhpr.s
new file mode 100644
index 000000000000..838bb538ed33
--- /dev/null
+++ b/gas/testsuite/gas/sparc/wrhpr.s
@@ -0,0 +1,7 @@
+# Test wrpr
+	.text
+	wrhpr %g1,%hpstate
+	wrhpr %g2,%htstate
+	wrhpr %g3,%hintp
+	wrhpr %g4,%htba
+	wrhpr %g5,%hstick_cmpr
diff --git a/gas/testsuite/gas/sparc/wrpr.d b/gas/testsuite/gas/sparc/wrpr.d
index 1d3c80e1c5af..d0c1b35a9887 100644
--- a/gas/testsuite/gas/sparc/wrpr.d
+++ b/gas/testsuite/gas/sparc/wrpr.d
@@ -22,3 +22,4 @@ Disassembly of section .text:
   30:	99 93 40 00 	wrpr  %o5, %cleanwin
   34:	9b 93 80 00 	wrpr  %sp, %otherwin
   38:	9d 93 c0 00 	wrpr  %o7, %wstate
+  3c:	a1 94 00 00 	wrpr  %l0, %gl
diff --git a/gas/testsuite/gas/sparc/wrpr.s b/gas/testsuite/gas/sparc/wrpr.s
index 67fd4504f4f1..e32b149c9bf8 100644
--- a/gas/testsuite/gas/sparc/wrpr.s
+++ b/gas/testsuite/gas/sparc/wrpr.s
@@ -15,3 +15,4 @@
 	wrpr %o5,%cleanwin
 	wrpr %o6,%otherwin
 	wrpr %o7,%wstate
+	wrpr %l0,%gl
diff --git a/gas/testsuite/gas/symver/symver.exp b/gas/testsuite/gas/symver/symver.exp
index 161f359bb38a..075d93f90ae8 100644
--- a/gas/testsuite/gas/symver/symver.exp
+++ b/gas/testsuite/gas/symver/symver.exp
@@ -16,6 +16,8 @@ proc run_error_test { name opts } {
 
 # symver is only supported by ELF targets.
 if { ([istarget "*-*-elf*"]		
+      || [istarget "m6811-*"]
+      || [istarget "m6812-*"]
       || [istarget "*-*-linux*"])
      && ![istarget *-*-linux*aout*]
      && ![istarget *-*-linux*oldld*] } then {
diff --git a/gas/testsuite/gas/tic54x/address.d b/gas/testsuite/gas/tic54x/address.d
index b8a7ba086b03..7d49c0412758 100644
--- a/gas/testsuite/gas/tic54x/address.d
+++ b/gas/testsuite/gas/tic54x/address.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <_addressing>:
+0+00 <_addressing>:
    0:	1801.*
    1:	1881.*
    2:	1989.*
diff --git a/gas/testsuite/gas/tic54x/addrfar.d b/gas/testsuite/gas/tic54x/addrfar.d
index 9c426332d7b5..9d8ec06126f4 100644
--- a/gas/testsuite/gas/tic54x/addrfar.d
+++ b/gas/testsuite/gas/tic54x/addrfar.d
@@ -7,7 +7,7 @@
 
 Disassembly of section .text:
 
-00000000 <_addressing>:
+0+000 <_addressing>:
    0:	1801.*
    1:	1881.*
    2:	1989.*
diff --git a/gas/testsuite/gas/tic54x/align.d b/gas/testsuite/gas/tic54x/align.d
index d50f06e43934..6a39217a3e2f 100644
--- a/gas/testsuite/gas/tic54x/align.d
+++ b/gas/testsuite/gas/tic54x/align.d
@@ -4,26 +4,26 @@
 .*: +file format .*c54x.*
 
 Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         00000089  00000000  00000000  0000....  2..7
+Idx Name          Size      VMA + LMA + File off  Algn
+  0 .text         00000089  0+000  0+000  0000....  2..7
                   CONTENTS, ALLOC, LOAD, ....
-  1 .data         00000005  00000000  00000000  0000....  2..1
+  1 .data         00000005  0+000  0+000  0000....  2..1
                   CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000000  00000000  00000000  0000....  2..0
+  2 .bss          00000000  0+000  0+000  0000....  2..0
                   ALLOC
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	4160.*
    1:	0001.*
    2:	0002.*
 	...
 
-00000004 <even>:
+0+004 <even>:
    4:	0003.*
 	...
 
-00000006 <align2>:
+0+006 <align2>:
    6:	0061.*
    7:	0062.*
    8:	0063.*
@@ -31,7 +31,7 @@ Disassembly of section .text:
    a:	0065.*
 	...
 
-00000010 <align8>:
+0+010 <align8>:
   10:	0008.*
   11:	0000.*
   12:	0001.*
@@ -43,7 +43,7 @@ Disassembly of section .text:
   18:	0007.*
 	...
 
-00000080 <align128>:
+0+080 <align128>:
   80:	0004.*
   81:	0000.*
   82:	0001.*
diff --git a/gas/testsuite/gas/tic54x/all-opcodes.d b/gas/testsuite/gas/tic54x/all-opcodes.d
index ae37380e5678..7e192aa56825 100644
--- a/gas/testsuite/gas/tic54x/all-opcodes.d
+++ b/gas/testsuite/gas/tic54x/all-opcodes.d
@@ -6,7 +6,7 @@
 
 Disassembly of section .text:
 
-00000000 <start>:
+0+000 <start>:
        0:	e300.*
        1:	e304.*
        2:	e308.*
@@ -219145,7 +219145,7 @@ Disassembly of section .text:
    357ff:	6629.*
    35800:	1df8.*
    35801:	662a.*
-00035802 <testend>:
+0+035802 <testend>:
    35802:	f073.*
    35803:	5802.*
 .*35803: ARELEXT16.*
diff --git a/gas/testsuite/gas/tic54x/asg.d b/gas/testsuite/gas/tic54x/asg.d
index d49762a3e4a8..37e25160bf6f 100644
--- a/gas/testsuite/gas/tic54x/asg.d
+++ b/gas/testsuite/gas/tic54x/asg.d
@@ -5,17 +5,17 @@
 
 Disassembly of section .text:
 
-00000000 <L1>:
+0+000 <L1>:
    0:	f000.*
    1:	0064.*
 
-00000002 <L2>:
+0+002 <L2>:
    2:	1090.*
 
-00000003 <L3>:
+0+003 <L3>:
    3:	1090.*
 
-00000004 <newlabel>:
+0+004 <newlabel>:
    4:	f000.*
    5:	0000.*
    6:	f000.*
@@ -127,5 +127,5 @@ Disassembly of section .text:
   70:	0063.*
   71:	0064.*
 
-00000072 <end>:
+0+072 <end>:
   72:	0100.*
diff --git a/gas/testsuite/gas/tic54x/cons.d b/gas/testsuite/gas/tic54x/cons.d
index ebd20a8b3da8..5a6ceced2812 100644
--- a/gas/testsuite/gas/tic54x/cons.d
+++ b/gas/testsuite/gas/tic54x/cons.d
@@ -5,55 +5,55 @@
 
 Disassembly of section .text:
 
-00000000 <binary>:
+0+000 <binary>:
    0:	0003.*
    1:	0004.*
 
-00000002 <octal>:
+0+002 <octal>:
    2:	0009.*
    3:	000a.*
    4:	000b.*
 
-00000005 <hex>:
+0+005 <hex>:
    5:	000f.*
    6:	0010.*
 
-00000007 <field>:
+0+007 <field>:
    7:	6440.*
    8:	0123.*
    9:	4000.*
    a:	0000.*
    b:	1234.*
 
-0000000c <byte>:
+0+00c <byte>:
    c:	00aa.*
    d:	00bb.*
 
-0000000e <word>:
+0+00e <word>:
    e:	0ccc.*
 
-0000000f <xlong>:
+0+00f <xlong>:
    f:	0eee.*
   10:	efff.*
 	...
 
-00000012 <long>:
+0+012 <long>:
   12:	eeee.*
   13:	ffff.*
 
-00000014 <int>:
+0+014 <int>:
   14:	dddd.*
 
-00000015 <xfloat>:
+0+015 <xfloat>:
   15:	3fff.*
   16:	ffac.*
 	...
 
-00000018 <float>:
+0+018 <float>:
   18:	3fff.*
   19:	ffac.*
 
-0000001a <string>:
+0+01a <string>:
   1a:	0061.*
   1b:	0062.*
   1c:	0063.*
@@ -67,7 +67,7 @@ Disassembly of section .text:
   24:	0067.*
   25:	0030.*
 
-00000026 <pstring>:
+0+026 <pstring>:
   26:	6162.*
   27:	6364.*
   28:	6162.*
@@ -75,7 +75,7 @@ Disassembly of section .text:
   2a:	6566.*
   2b:	6700.*
 
-0000002c <DAT1>:
+0+02c <DAT1>:
   2c:	0000.*
   2d:	abcd.*
   2e:	0000.*
@@ -85,17 +85,17 @@ Disassembly of section .text:
   32:	0000.*
   33:	006f.*
 
-00000034 <xlong.0>:
+0+034 <xlong.0>:
   34:	0000.*
   35:	002c.*
   36:	aabb.*
   37:	ccdd.*
 
-00000038 <DAT2>:
+0+038 <DAT2>:
   38:	0000.*
 	...
 
-0000003a <DAT3>:
+0+03a <DAT3>:
   3a:	1234.*
   3b:	5678.*
   3c:	0000.*
diff --git a/gas/testsuite/gas/tic54x/consfar.d b/gas/testsuite/gas/tic54x/consfar.d
index 8c8a5323d57a..bdb46a29e3d6 100644
--- a/gas/testsuite/gas/tic54x/consfar.d
+++ b/gas/testsuite/gas/tic54x/consfar.d
@@ -7,55 +7,55 @@
 
 Disassembly of section .text:
 
-00000000 <binary>:
+0+000 <binary>:
    0:	0003.*
    1:	0004.*
 
-00000002 <octal>:
+0+002 <octal>:
    2:	0009.*
    3:	000a.*
    4:	000b.*
 
-00000005 <hex>:
+0+005 <hex>:
    5:	000f.*
    6:	0010.*
 
-00000007 <field>:
+0+007 <field>:
    7:	6440.*
    8:	0123.*
    9:	4000.*
    a:	0000.*
    b:	1234.*
 
-0000000c <byte>:
+0+00c <byte>:
    c:	00aa.*
    d:	00bb.*
 
-0000000e <word>:
+0+00e <word>:
    e:	0ccc.*
 
-0000000f <xlong>:
+0+00f <xlong>:
    f:	0eee.*
   10:	efff.*
 	...
 
-00000012 <long>:
+0+012 <long>:
   12:	eeee.*
   13:	ffff.*
 
-00000014 <int>:
+0+014 <int>:
   14:	dddd.*
 
-00000015 <xfloat>:
+0+015 <xfloat>:
   15:	3fff.*
   16:	ffac.*
 	...
 
-00000018 <float>:
+0+018 <float>:
   18:	3fff.*
   19:	ffac.*
 
-0000001a <string>:
+0+01a <string>:
   1a:	0061.*
   1b:	0062.*
   1c:	0063.*
@@ -69,7 +69,7 @@ Disassembly of section .text:
   24:	0067.*
   25:	0030.*
 
-00000026 <pstring>:
+0+026 <pstring>:
   26:	6162.*
   27:	6364.*
   28:	6162.*
@@ -77,7 +77,7 @@ Disassembly of section .text:
   2a:	6566.*
   2b:	6700.*
 
-0000002c <DAT1>:
+0+02c <DAT1>:
   2c:	0000.*
   2d:	abcd.*
   2e:	0000.*
@@ -87,18 +87,18 @@ Disassembly of section .text:
   32:	0000.*
   33:	006f.*
 
-00000034 <xlong.0>:
+0+034 <xlong.0>:
   34:	0000.*
 .*34: ARELEXT.*
   35:	002c.*
   36:	aabb.*
   37:	ccdd.*
 
-00000038 <DAT2>:
+0+038 <DAT2>:
   38:	0000.*
 	...
 
-0000003a <DAT3>:
+0+03a <DAT3>:
   3a:	1234.*
   3b:	5678.*
   3c:	0000.*
diff --git a/gas/testsuite/gas/tic54x/extaddr.d b/gas/testsuite/gas/tic54x/extaddr.d
index 2a396449d5a3..5537e44cc7eb 100644
--- a/gas/testsuite/gas/tic54x/extaddr.d
+++ b/gas/testsuite/gas/tic54x/extaddr.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
        0:	f062.*
        1:	0000.*
 .*1: RELEXTMS7.*
@@ -14,7 +14,7 @@ Disassembly of section .text:
 .*3: RELEXT16.*
        4:	f4e2.*
 
-00000005 <start>:
+0+005 <start>:
        5:	f881.*
        6:	0080.*
 .*5: ARELEXT.*
@@ -49,7 +49,7 @@ Disassembly of section .text:
       20:	f495.*
 	...
 
-00010080 <end>:
+0+010080 <end>:
    10080:	f881.*
    10081:	0080.*
 .*10080: ARELEXT.*
diff --git a/gas/testsuite/gas/tic54x/field.d b/gas/testsuite/gas/tic54x/field.d
index 618cb4ae2f49..60a4868904cd 100644
--- a/gas/testsuite/gas/tic54x/field.d
+++ b/gas/testsuite/gas/tic54x/field.d
@@ -5,26 +5,26 @@
 
 Disassembly of section .text:
 
-00000000 <f1>:
+0+000 <f1>:
    0:	2af0.*
    1:	5600.*
 
-00000001 <f2>:
+0+001 <f2>:
    1:	5600.*
 
-00000002 <f4>:
+0+002 <f4>:
    2:	0001.*
 
-00000003 <f5>:
+0+003 <f5>:
    3:	0000.*
    4:	4321.*
 
-00000005 <f6>:
+0+005 <f6>:
    5:	000f.*
 
-00000006 <f7>:
+0+006 <f7>:
    6:	6000.*
    7:	008a.*
 
-00000007 <f8>:
+0+007 <f8>:
    7:	008a.*
diff --git a/gas/testsuite/gas/tic54x/labels.d b/gas/testsuite/gas/tic54x/labels.d
index 42e2160a9d72..794f11ff0816 100644
--- a/gas/testsuite/gas/tic54x/labels.d
+++ b/gas/testsuite/gas/tic54x/labels.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <label1>:
+0+000 <label1>:
    0:	1000.*
    1:	0800.*
    2:	f843.*
@@ -14,50 +14,50 @@ Disassembly of section .text:
    5:	f073.*
    6:	0008.*
 
-00000007 <\$1.*>:
+0+007 <\$1.*>:
    7:	1000.*
 
-00000008 <\$2.*>:
+0+008 <\$2.*>:
    8:	0000.*
    9:	f843.*
    a:	000c.*
    b:	8000.*
 
-0000000c <\$1.*>:
+0+00c <\$1.*>:
    c:	f495.*
    d:	f495.*
 
-0000000e <lab.*>:
+0+00e <lab.*>:
    e:	f000.*
    f:	0001.*
   10:	f073.*
   11:	000e.*
 
-00000012 <lab.*>:
+0+012 <lab.*>:
   12:	f845.*
   13:	0012.*
 
-00000014 <lab.*>:
+0+014 <lab.*>:
   14:	f000.*
   15:	0003.*
   16:	f073.*
   17:	0014.*
 
-00000018 <lab.*>:
+0+018 <lab.*>:
   18:	f000.*
   19:	0004.*
   1a:	f073.*
   1b:	0018.*
 
-0000001c <after_macro>:
+0+01c <after_macro>:
   1c:	f073.*
   1d:	0014.*
 Disassembly of section new_sect:
 
-00000000 <new_section>:
+0+000 <new_section>:
    0:	f495.*
 
-00000001 <lab.7>:
+0+001 <lab.7>:
    1:	f000.*
    2:	0005.*
    3:	f495.*
@@ -65,7 +65,7 @@ Disassembly of section new_sect:
    5:	f073.*
    6:	0001.*
 
-00000007 <lab.8>:
+0+007 <lab.8>:
    7:	f000.*
    8:	0006.*
    9:	f495.*
diff --git a/gas/testsuite/gas/tic54x/loop.d b/gas/testsuite/gas/tic54x/loop.d
index f06752453f62..592564a89aad 100644
--- a/gas/testsuite/gas/tic54x/loop.d
+++ b/gas/testsuite/gas/tic54x/loop.d
@@ -5,10 +5,10 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
 	...
 
-00000001 <label>:
+0+001 <label>:
    1:	0000.*
    2:	0001.*
    3:	0002.*
diff --git a/gas/testsuite/gas/tic54x/lp.d b/gas/testsuite/gas/tic54x/lp.d
index 7eb6186f3920..8e27c9604883 100644
--- a/gas/testsuite/gas/tic54x/lp.d
+++ b/gas/testsuite/gas/tic54x/lp.d
@@ -5,6 +5,6 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	f49f.*
 
diff --git a/gas/testsuite/gas/tic54x/macro.d b/gas/testsuite/gas/tic54x/macro.d
index 531389181cdc..1a4a114f49b4 100644
--- a/gas/testsuite/gas/tic54x/macro.d
+++ b/gas/testsuite/gas/tic54x/macro.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	f000.*
    1:	0000.* 
    2:	f300.*
diff --git a/gas/testsuite/gas/tic54x/math.d b/gas/testsuite/gas/tic54x/math.d
index d2aadf8eeee2..012a0ad7e5f4 100644
--- a/gas/testsuite/gas/tic54x/math.d
+++ b/gas/testsuite/gas/tic54x/math.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	3fc9.*
    1:	0fd8.*
 	...
diff --git a/gas/testsuite/gas/tic54x/opcodes.d b/gas/testsuite/gas/tic54x/opcodes.d
index d3496bf6336c..2dab821ce302 100644
--- a/gas/testsuite/gas/tic54x/opcodes.d
+++ b/gas/testsuite/gas/tic54x/opcodes.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <_opcodes>:
+0+000 <_opcodes>:
    0:	e39a 	abdst  \*ar3\+,\*ar4\+
    1:	f485 	abs    a
    2:	f585 	abs    a,b
diff --git a/gas/testsuite/gas/tic54x/sections.d b/gas/testsuite/gas/tic54x/sections.d
index 4f85b9a0268c..d1e04b62bf44 100644
--- a/gas/testsuite/gas/tic54x/sections.d
+++ b/gas/testsuite/gas/tic54x/sections.d
@@ -4,73 +4,73 @@
 .*: +file format .*c54x.*
 
 Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .text         0000001b  00000000  00000000  0000....  2..0
+Idx Name          Size      VMA + LMA + File off  Algn
+  0 .text         0000001b  0+000  0+000  0000....  2..0
                   CONTENTS, ALLOC, LOAD, RELOC, CODE
-  1 .data         00000007  00000000  00000000  0000....  2..0
+  1 .data         00000007  0+000  0+000  0000....  2..0
                   CONTENTS, ALLOC, LOAD, DATA
-  2 .bss          00000014  00000000  00000000  0000....  2..0
+  2 .bss          00000014  0+000  0+000  0000....  2..0
                   ALLOC
-  3 newvars       00000017  00000000  00000000  0000....  2..1
+  3 newvars       00000017  0+000  0+000  0000....  2..1
                   ALLOC, BLOCK
-  4 vectors       00000002  00000000  00000000  0000....  2..0
+  4 vectors       00000002  0+000  0+000  0000....  2..0
                   CONTENTS, ALLOC, LOAD, CODE, BLOCK
-  5 clink         00000002  00000000  00000000  0000....  2..0
+  5 clink         00000002  0+000  0+000  0000....  2..0
                   CONTENTS, ALLOC, LOAD, DATA, CLINK
-  6 blksect       00000002  00000000  00000000  0000....  2..0
+  6 blksect       00000002  0+000  0+000  0000....  2..0
                   CONTENTS, ALLOC, LOAD, DATA, BLOCK
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	1234.*
 
-00000001 <add>:
+0+001 <add>:
    1:	100f.*
 
-00000002 <aloop>:
+0+002 <aloop>:
    2:	f010.*
    3:	0001.*
    4:	f842.*
    5:	0002.*
 
-00000006 <mpy>:
+0+006 <mpy>:
    6:	110a.*
 
-00000007 <mloop>:
+0+007 <mloop>:
    7:	f166.*
    8:	000a.*
    9:	f868.*
    a:	0007.*
 
-0000000b <space>:
+0+00b <space>:
 	...
 
-00000012 <bes>:
+0+012 <bes>:
 	...
 
-00000013 <spacep>:
+0+013 <spacep>:
   13:	000b.*
 
-00000014 <besp>:
+0+014 <besp>:
   14:	0012.*
 
-00000015 <pk1>:
+0+015 <pk1>:
 	...
 
-00000016 <endpk1>:
+0+016 <endpk1>:
   16:	0000.*
 	...
 
-00000018 <endpk2>:
+0+018 <endpk2>:
 	...
 
-00000019 <pk3>:
+0+019 <pk3>:
 	...
 
-0000001a <endpk3>:
+0+01a <endpk3>:
 	...
 Disassembly of section vectors:
 
-00000000 <vectors>:
+0+000 <vectors>:
    0:	f495.*
    1:	f495.*
diff --git a/gas/testsuite/gas/tic54x/set.d b/gas/testsuite/gas/tic54x/set.d
index da6c99cca315..8f661884d434 100644
--- a/gas/testsuite/gas/tic54x/set.d
+++ b/gas/testsuite/gas/tic54x/set.d
@@ -5,12 +5,12 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	7711.*
    1:	0056.* 
    2:	f000.*
    3:	0035.* 
 
-00000004 <LABEL>:
+0+004 <LABEL>:
    4:	000a.*
    5:	0035.*
diff --git a/gas/testsuite/gas/tic54x/struct.d b/gas/testsuite/gas/tic54x/struct.d
index 2cdd3343dfe1..dc05fba6dc4b 100644
--- a/gas/testsuite/gas/tic54x/struct.d
+++ b/gas/testsuite/gas/tic54x/struct.d
@@ -5,7 +5,7 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	0001.*
    1:	0002.*
    2:	8002.*
diff --git a/gas/testsuite/gas/tic54x/subsym.d b/gas/testsuite/gas/tic54x/subsym.d
index a3385ae3609b..46bcb27b9a1b 100644
--- a/gas/testsuite/gas/tic54x/subsym.d
+++ b/gas/testsuite/gas/tic54x/subsym.d
@@ -5,10 +5,10 @@
 
 Disassembly of section .text:
 
-00000000 <.text>:
+0+000 <.text>:
    0:	0018.*
 
-00000001 <label>:
+0+001 <label>:
    1:	0005.*
    2:	0005.*
    3:	0006.*
@@ -33,7 +33,7 @@ Disassembly of section .text:
   16:	0000.*
   17:	0001.*
 
-00000018 <x>:
+0+018 <x>:
   18:	0001.*
   19:	0001.*
 	...
diff --git a/gas/testsuite/gas/tic80/add.d b/gas/testsuite/gas/tic80/add.d
deleted file mode 100644
index 3dec70729da9..000000000000
--- a/gas/testsuite/gas/tic80/add.d
+++ /dev/null
@@ -1,22 +0,0 @@
-#objdump: -d
-#name: TIc80 signed and unsigned add instructions
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	0a 00 fb 62.*
-   4:	ff 3f ac 20.*
-   8:	00 40 2c 21.*
-   c:	00 10 7b 31 00 40 00 00.*
-  14:	00 10 fb 41 ff bf ff ff.*
-  1c:	00 10 bb 5a ff ff ff 7f.*
-  24:	00 10 3b 6b 00 00 00 80.*
-  2c:	0a 20 fb 62.*
-  30:	ff bf ac 20.*
-  34:	00 c0 2c 21.*
-  38:	00 30 7b 31 00 40 00 00.*
-  40:	00 30 fb 41 ff bf ff ff.*
-  48:	00 30 bb 5a ff ff ff 7f.*
-  50:	00 30 3b 6b 00 00 00 80.*
diff --git a/gas/testsuite/gas/tic80/add.lst b/gas/testsuite/gas/tic80/add.lst
deleted file mode 100644
index e12b3682aabe..000000000000
--- a/gas/testsuite/gas/tic80/add.lst
+++ /dev/null
@@ -1,34 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 20:13:33 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-add.s                                                                PAGE    1
-
-        1                     ; Test signed and unsigned addition instruction.
-        2                     ; Test boundary conditions to ensure proper handling.
-        3                     ; Note that unsigned addition still uses signed immediates.
-        4                     
-        5 00000000   62FB000A         add     r10,r11,r12             ; Register form
-        6 00000004   20AC3FFF         add     16383,r2,r4             ; Maximum positive short signed immediate
-        7 00000008   212C4000         add     -16384,r4,r4            ; Minimum negative short signed immediate
-        8 0000000C   317B1000         add     16384,r5,r6             ; Minimum positive long signed immediate
-          00000010   00004000 
-        9 00000014   41FB1000         add     -16385,r7,r8            ; Maximum negative short signed immediate
-          00000018   FFFFBFFF 
-       10 0000001C   5ABB1000         add     2147483647,r10,r11      ; Maximum positive long signed immediate
-          00000020   7FFFFFFF 
-       11 00000024   6B3B1000         add     -2147483648,r12,r13     ; Minimum positive long signed immediate
-          00000028   80000000 
-       12                     
-       13 0000002C   62FB200A         addu    r10,r11,r12             ; Register form
-       14 00000030   20ACBFFF         addu    16383,r2,r4             ; Maximum positive short signed immediate
-       15 00000034   212CC000         addu    -16384,r4,r4            ; Minimum negative short signed immediate
-       16 00000038   317B3000         addu    16384,r5,r6             ; Minimum positive long signed immediate
-          0000003C   00004000 
-       17 00000040   41FB3000         addu    -16385,r7,r8            ; Maximum negative short signed immediate
-          00000044   FFFFBFFF 
-       18 00000048   5ABB3000         addu    2147483647,r10,r11      ; Maximum positive long signed immediate
-          0000004C   7FFFFFFF 
-       19 00000050   6B3B3000         addu    -2147483648,r12,r13     ; Minimum positive long signed immediate
-          00000054   80000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/add.s b/gas/testsuite/gas/tic80/add.s
deleted file mode 100644
index 6c229ed1fe4f..000000000000
--- a/gas/testsuite/gas/tic80/add.s
+++ /dev/null
@@ -1,19 +0,0 @@
-; Test signed and unsigned addition instruction.
-; Test boundary conditions to ensure proper handling.
-; Note that unsigned addition still uses signed immediates.
-
-	add	r10,r11,r12		; Register form
-	add	16383,r2,r4		; Maximum positive short signed immediate
-	add	-16384,r4,r4		; Minimum negative short signed immediate
-	add	16384,r5,r6		; Minimum positive long signed immediate
-	add	-16385,r7,r8		; Maximum negative long signed immediate
-	add	2147483647,r10,r11	; Maximum positive long signed immediate
-	add	-2147483648,r12,r13	; Minimum negative long signed immediate
-
-	addu	r10,r11,r12		; Register form
-	addu	16383,r2,r4		; Maximum positive short signed immediate
-	addu	-16384,r4,r4		; Minimum negative short signed immediate
-	addu	16384,r5,r6		; Minimum positive long signed immediate
-	addu	-16385,r7,r8		; Maximum negative long signed immediate
-	addu	2147483647,r10,r11	; Maximum positive long signed immediate
-	addu	-2147483648,r12,r13	; Minimum negative long signed immediate
diff --git a/gas/testsuite/gas/tic80/align.d b/gas/testsuite/gas/tic80/align.d
deleted file mode 100644
index 88f961046e68..000000000000
--- a/gas/testsuite/gas/tic80/align.d
+++ /dev/null
@@ -1,19 +0,0 @@
-#objdump: -d
-#name: TIc80 .align pseudo op
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	ab 00 00 00.*
-   4:	cd 00 ef 00.*
-   8:	f1 00 00 00.*
-   c:	ee 00 00 00.*
-  10:	ac 00 00 00.*
-  14:	00 00 00 00.*
-  18:	ab 00 00 00.*
-  1c:	00 00 00 00.*
-  20:	fe 00 00 00.*
-	\.\.\.
-  30:	de ad be ef.*
diff --git a/gas/testsuite/gas/tic80/align.lst b/gas/testsuite/gas/tic80/align.lst
deleted file mode 100644
index 915415ad5755..000000000000
--- a/gas/testsuite/gas/tic80/align.lst
+++ /dev/null
@@ -1,47 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Thu Feb 27 17:02:23 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-align.s                                                              PAGE    1
-
-        1                     ;;      Test the .align directive.
-        2                     
-        3 00000000                    .text
-        4                             
-        5                             ;; This should generate 0xAB000000
-        6 00000000   AB               .byte   0xAB
-        7 00000001                    .align                  ; Should default to 4 byte alignment
-        8                     
-        9                             ;; This should generate 0xCD00EF00
-       10 00000004   CD               .byte   0xCD
-       11                             .align  2               ;  Should align to the next 2-byte boundary (pad with one null byt
-       12 00000006   EF               .byte   0xEF
-       13                             .align  1
-       14                     
-       15                             ;; This should generate 0xF1000000
-       16 00000007                    .align  4               ;  Should not affect alignment (already on 4)
-       17 00000008   F1               .byte   0xF1
-       18 00000009                    .align  4               ;  Should align to next 4 byte boundary
-       19                     
-       20                             ;; This should generate 0xEE000000 since we are already on 4 byte alignment
-       21 0000000C   EE               .byte 0xEE
-       22 0000000D                    .align  8
-       23                     
-       24                             ;; This should generate 0xAC000000 0x00000000
-       25 00000010   AC               .byte   0xAC
-       26 00000011                    .align  8
-       27                             
-       28                             ;; This should generate 0xAB000000 0x00000000 since we are at 8 byte alignment
-       29 00000018   AB               .byte   0xAB
-       30 00000019                    .align  16
-       31                     
-       32                             ;; This should generate 0xFE000000 0x00000000 0x00000000 0x00000000
-       33 00000020   FE               .byte   0xFE
-       34 00000021                    .align  16
-       35                             
-       36                             ;; This just forces the disassembler to not print ... for trailing nulls
-       37 00000030   DE               .byte 0xDE, 0xAD, 0xBE, 0xEF
-          00000031   AD       
-          00000032   BE       
-          00000033   EF       
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/align.s b/gas/testsuite/gas/tic80/align.s
deleted file mode 100644
index 02c1256f50c1..000000000000
--- a/gas/testsuite/gas/tic80/align.s
+++ /dev/null
@@ -1,37 +0,0 @@
-;;	Test the .align directive.
-
-	.text
-	
-	;; This should generate 0xAB000000
-	.byte	0xAB
-	.align			; Should default to 4 byte alignment
-
-	;; This should generate 0xCD00EF00
-	.byte	0xCD
-	.align	2		;  Should align to the next 2-byte boundary (pad with one null byte)
-	.byte	0xEF
-	.align	1
-
-	;; This should generate 0xF1000000
-	.align	4		;  Should not affect alignment (already on 4)
-	.byte	0xF1
-	.align	4		;  Should align to next 4 byte boundary
-
-	;; This should generate 0xEE000000 since we are already on 4 byte alignment
-	.byte 0xEE
-	.align	8
-
-	;; This should generate 0xAC000000 0x00000000
-	.byte	0xAC
-	.align	8
-	
-	;; This should generate 0xAB000000 0x00000000 since we are at 8 byte alignment
-	.byte	0xAB
-	.align	16
-
-	;; This should generate 0xFE000000 0x00000000 0x00000000 0x00000000
-	.byte	0xFE
-	.align	16
-	
-	;; This just forces the disassembler to not print ... for trailing nulls
-	.byte 0xDE, 0xAD, 0xBE, 0xEF
diff --git a/gas/testsuite/gas/tic80/bitnum.d b/gas/testsuite/gas/tic80/bitnum.d
deleted file mode 100644
index fcaee8b086b3..000000000000
--- a/gas/testsuite/gas/tic80/bitnum.d
+++ /dev/null
@@ -1,82 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of symbolic BITNUM values
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	0a 40 39 fa.*
-   4:	0a 40 39 f2.*
-   8:	0a 40 39 ea.*
-   c:	0a 40 39 e2.*
-  10:	0a 40 39 da.*
-  14:	0a 40 39 d2.*
-  18:	0a 40 39 ca.*
-  1c:	0a 40 39 c2.*
-  20:	0a 40 39 ba.*
-  24:	0a 40 39 b2.*
-  28:	0a 40 39 aa.*
-  2c:	0a 40 39 a2.*
-  30:	0a 40 39 9a.*
-  34:	0a 40 39 92.*
-  38:	0a 40 39 8a.*
-  3c:	0a 40 39 82.*
-  40:	0a 40 39 7a.*
-  44:	0a 40 39 72.*
-  48:	0a 40 39 6a.*
-  4c:	0a 40 39 62.*
-  50:	0a 40 39 5a.*
-  54:	0a 40 39 52.*
-  58:	0a 40 39 4a.*
-  5c:	0a 40 39 42.*
-  60:	0a 40 39 3a.*
-  64:	0a 40 39 32.*
-  68:	0a 40 39 2a.*
-  6c:	0a 40 39 22.*
-  70:	0a 40 39 1a.*
-  74:	0a 40 39 12.*
-  78:	0a 40 39 5a.*
-  7c:	0a 40 39 52.*
-  80:	0a 40 39 4a.*
-  84:	0a 40 39 42.*
-  88:	0a 40 39 3a.*
-  8c:	0a 40 39 32.*
-  90:	0a 40 39 2a.*
-  94:	0a 40 39 22.*
-  98:	0a 40 39 1a.*
-  9c:	0a 40 39 12.*
-  a0:	0a 40 39 0a.*
-  a4:	0a 40 39 02.*
-  a8:	0a 40 39 fa.*
-  ac:	0a 40 39 f2.*
-  b0:	0a 40 39 ea.*
-  b4:	0a 40 39 e2.*
-  b8:	0a 40 39 da.*
-  bc:	0a 40 39 d2.*
-  c0:	0a 40 39 ca.*
-  c4:	0a 40 39 c2.*
-  c8:	0a 40 39 ba.*
-  cc:	0a 40 39 b2.*
-  d0:	0a 40 39 aa.*
-  d4:	0a 40 39 a2.*
-  d8:	0a 40 39 9a.*
-  dc:	0a 40 39 92.*
-  e0:	0a 40 39 8a.*
-  e4:	0a 40 39 82.*
-  e8:	0a 40 39 7a.*
-  ec:	0a 40 39 72.*
-  f0:	0a 40 39 6a.*
-  f4:	0a 40 39 62.*
-  f8:	0a 40 39 5a.*
-  fc:	0a 40 39 52.*
- 100:	0a 40 39 4a.*
- 104:	0a 40 39 42.*
- 108:	0a 40 39 3a.*
- 10c:	0a 40 39 32.*
- 110:	0a 40 39 2a.*
- 114:	0a 40 39 22.*
- 118:	0a 40 39 1a.*
- 11c:	0a 40 39 12.*
- 120:	0a 40 39 0a.*
- 124:	0a 40 39 02.*
diff --git a/gas/testsuite/gas/tic80/bitnum.lst b/gas/testsuite/gas/tic80/bitnum.lst
deleted file mode 100644
index acc268bb26fa..000000000000
--- a/gas/testsuite/gas/tic80/bitnum.lst
+++ /dev/null
@@ -1,97 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 21:37:15 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-bitnum.s                                                             PAGE    1
-
-        1                     ;; Test that all the predefined symbol names for the BITNUM field
-        2                     ;; are properly accepted and translated to numeric values.  Also
-        3                     ;; verifies that they are disassembled correctly as symbolics, and
-        4                     ;; that the raw numeric values are handled correctly (stored as
-        5                     ;; the one's complement of the operand numeric value.
-        6                     
-        7 00000000   FA39400A         bbo     r10,r8,eq.b     ; (~0 & 0x1F)
-        8 00000004   F239400A         bbo     r10,r8,ne.b     ; (~1 & 0x1F)
-        9 00000008   EA39400A         bbo     r10,r8,gt.b     ; (~2 & 0x1F)
-       10 0000000C   E239400A         bbo     r10,r8,le.b     ; (~3 & 0x1F)
-       11 00000010   DA39400A         bbo     r10,r8,lt.b     ; (~4 & 0x1F)
-       12 00000014   D239400A         bbo     r10,r8,ge.b     ; (~5 & 0x1F)
-       13 00000018   CA39400A         bbo     r10,r8,hi.b     ; (~6 & 0x1F)
-       14 0000001C   C239400A         bbo     r10,r8,ls.b     ; (~7 & 0x1F)
-       15 00000020   BA39400A         bbo     r10,r8,lo.b     ; (~8 & 0x1F)
-       16 00000024   B239400A         bbo     r10,r8,hs.b     ; (~9 & 0x1F)
-       17                     
-       18 00000028   AA39400A         bbo     r10,r8,eq.h     ; (~10 & 0x1F)
-       19 0000002C   A239400A         bbo     r10,r8,ne.h     ; (~11 & 0x1F)
-       20 00000030   9A39400A         bbo     r10,r8,gt.h     ; (~12 & 0x1F)
-       21 00000034   9239400A         bbo     r10,r8,le.h     ; (~13 & 0x1F)
-       22 00000038   8A39400A         bbo     r10,r8,lt.h     ; (~14 & 0x1F)
-       23 0000003C   8239400A         bbo     r10,r8,ge.h     ; (~15 & 0x1F)
-       24 00000040   7A39400A         bbo     r10,r8,hi.h     ; (~16 & 0x1F)
-       25 00000044   7239400A         bbo     r10,r8,ls.h     ; (~17 & 0x1F)
-       26 00000048   6A39400A         bbo     r10,r8,lo.h     ; (~18 & 0x1F)
-       27 0000004C   6239400A         bbo     r10,r8,hs.h     ; (~19 & 0x1F)
-       28                     
-       29 00000050   5A39400A         bbo     r10,r8,eq.w     ; (~20 & 0x1F)
-       30 00000054   5239400A         bbo     r10,r8,ne.w     ; (~21 & 0x1F)
-       31 00000058   4A39400A         bbo     r10,r8,gt.w     ; (~22 & 0x1F)
-       32 0000005C   4239400A         bbo     r10,r8,le.w     ; (~23 & 0x1F)
-       33 00000060   3A39400A         bbo     r10,r8,lt.w     ; (~24 & 0x1F)
-       34 00000064   3239400A         bbo     r10,r8,ge.w     ; (~25 & 0x1F)
-       35 00000068   2A39400A         bbo     r10,r8,hi.w     ; (~26 & 0x1F)
-       36 0000006C   2239400A         bbo     r10,r8,ls.w     ; (~27 & 0x1F)
-       37 00000070   1A39400A         bbo     r10,r8,lo.w     ; (~28 & 0x1F)
-       38 00000074   1239400A         bbo     r10,r8,hs.w     ; (~29 & 0x1F)
-       39                     
-       40 00000078   5A39400A         bbo     r10,r8,eq.f     ; (~20 & 0x1F)
-       41 0000007C   5239400A         bbo     r10,r8,ne.f     ; (~21 & 0x1F)
-       42 00000080   4A39400A         bbo     r10,r8,gt.f     ; (~22 & 0x1F)
-       43 00000084   4239400A         bbo     r10,r8,le.f     ; (~23 & 0x1F)
-       44 00000088   3A39400A         bbo     r10,r8,lt.f     ; (~24 & 0x1F)
-       45 0000008C   3239400A         bbo     r10,r8,ge.f     ; (~25 & 0x1F)
-       46 00000090   2A39400A         bbo     r10,r8,ou.f     ; (~26 & 0x1F)
-       47 00000094   2239400A         bbo     r10,r8,in.f     ; (~27 & 0x1F)
-       48 00000098   1A39400A         bbo     r10,r8,ib.f     ; (~28 & 0x1F)
-       49 0000009C   1239400A         bbo     r10,r8,ob.f     ; (~29 & 0x1F)
-       50 000000A0   0A39400A         bbo     r10,r8,uo.f     ; (~30 & 0x1F)
-       51 000000A4   0239400A         bbo     r10,r8,or.f     ; (~31 & 0x1F)
-       52                     
-       53 000000A8   FA39400A         bbo     r10,r8,0
-       54 000000AC   F239400A         bbo     r10,r8,1
-       55 000000B0   EA39400A         bbo     r10,r8,2
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 21:37:15 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-bitnum.s                                                             PAGE    2
-
-       56 000000B4   E239400A         bbo     r10,r8,3
-       57 000000B8   DA39400A         bbo     r10,r8,4
-       58 000000BC   D239400A         bbo     r10,r8,5
-       59 000000C0   CA39400A         bbo     r10,r8,6
-       60 000000C4   C239400A         bbo     r10,r8,7
-       61 000000C8   BA39400A         bbo     r10,r8,8
-       62 000000CC   B239400A         bbo     r10,r8,9
-       63 000000D0   AA39400A         bbo     r10,r8,10
-       64 000000D4   A239400A         bbo     r10,r8,11
-       65 000000D8   9A39400A         bbo     r10,r8,12
-       66 000000DC   9239400A         bbo     r10,r8,13
-       67 000000E0   8A39400A         bbo     r10,r8,14
-       68 000000E4   8239400A         bbo     r10,r8,15
-       69 000000E8   7A39400A         bbo     r10,r8,16
-       70 000000EC   7239400A         bbo     r10,r8,17
-       71 000000F0   6A39400A         bbo     r10,r8,18
-       72 000000F4   6239400A         bbo     r10,r8,19
-       73 000000F8   5A39400A         bbo     r10,r8,20
-       74 000000FC   5239400A         bbo     r10,r8,21
-       75 00000100   4A39400A         bbo     r10,r8,22
-       76 00000104   4239400A         bbo     r10,r8,23
-       77 00000108   3A39400A         bbo     r10,r8,24
-       78 0000010C   3239400A         bbo     r10,r8,25
-       79 00000110   2A39400A         bbo     r10,r8,26
-       80 00000114   2239400A         bbo     r10,r8,27
-       81 00000118   1A39400A         bbo     r10,r8,28
-       82 0000011C   1239400A         bbo     r10,r8,29
-       83 00000120   0A39400A         bbo     r10,r8,30
-       84 00000124   0239400A         bbo     r10,r8,31
-       85                     
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/bitnum.s b/gas/testsuite/gas/tic80/bitnum.s
deleted file mode 100644
index 2526e0644ec6..000000000000
--- a/gas/testsuite/gas/tic80/bitnum.s
+++ /dev/null
@@ -1,85 +0,0 @@
-;; Test that all the predefined symbol names for the BITNUM field
-;; are properly accepted and translated to numeric values.  Also
-;; verifies that they are disassembled correctly as symbolics, and
-;; that the raw numeric values are handled correctly (stored as
-;; the one's complement of the operand numeric value.
-
-	bbo	r10,r8,eq.b	; (~0 & 0x1F)
-	bbo	r10,r8,ne.b	; (~1 & 0x1F)
-	bbo	r10,r8,gt.b	; (~2 & 0x1F)
-	bbo	r10,r8,le.b	; (~3 & 0x1F)
-	bbo	r10,r8,lt.b	; (~4 & 0x1F)
-	bbo	r10,r8,ge.b	; (~5 & 0x1F)
-	bbo	r10,r8,hi.b	; (~6 & 0x1F)
-	bbo	r10,r8,ls.b	; (~7 & 0x1F)
-	bbo	r10,r8,lo.b	; (~8 & 0x1F)
-	bbo	r10,r8,hs.b	; (~9 & 0x1F)
-
-	bbo	r10,r8,eq.h	; (~10 & 0x1F)
-	bbo	r10,r8,ne.h	; (~11 & 0x1F)
-	bbo	r10,r8,gt.h	; (~12 & 0x1F)
-	bbo	r10,r8,le.h	; (~13 & 0x1F)
-	bbo	r10,r8,lt.h	; (~14 & 0x1F)
-	bbo	r10,r8,ge.h	; (~15 & 0x1F)
-	bbo	r10,r8,hi.h	; (~16 & 0x1F)
-	bbo	r10,r8,ls.h	; (~17 & 0x1F)
-	bbo	r10,r8,lo.h	; (~18 & 0x1F)
-	bbo	r10,r8,hs.h	; (~19 & 0x1F)
-
-	bbo	r10,r8,eq.w	; (~20 & 0x1F)
-	bbo	r10,r8,ne.w	; (~21 & 0x1F)
-	bbo	r10,r8,gt.w	; (~22 & 0x1F)
-	bbo	r10,r8,le.w	; (~23 & 0x1F)
-	bbo	r10,r8,lt.w	; (~24 & 0x1F)
-	bbo	r10,r8,ge.w	; (~25 & 0x1F)
-	bbo	r10,r8,hi.w	; (~26 & 0x1F)
-	bbo	r10,r8,ls.w	; (~27 & 0x1F)
-	bbo	r10,r8,lo.w	; (~28 & 0x1F)
-	bbo	r10,r8,hs.w	; (~29 & 0x1F)
-
-	bbo	r10,r8,eq.f	; (~20 & 0x1F)
-	bbo	r10,r8,ne.f	; (~21 & 0x1F)
-	bbo	r10,r8,gt.f	; (~22 & 0x1F)
-	bbo	r10,r8,le.f	; (~23 & 0x1F)
-	bbo	r10,r8,lt.f	; (~24 & 0x1F)
-	bbo	r10,r8,ge.f	; (~25 & 0x1F)
-	bbo	r10,r8,ou.f	; (~26 & 0x1F)
-	bbo	r10,r8,in.f	; (~27 & 0x1F)
-	bbo	r10,r8,ib.f	; (~28 & 0x1F)
-	bbo	r10,r8,ob.f	; (~29 & 0x1F)
-	bbo	r10,r8,uo.f	; (~30 & 0x1F)
-	bbo	r10,r8,or.f	; (~31 & 0x1F)
-
-	bbo	r10,r8,0
-	bbo	r10,r8,1
-	bbo	r10,r8,2
-	bbo	r10,r8,3
-	bbo	r10,r8,4
-	bbo	r10,r8,5
-	bbo	r10,r8,6
-	bbo	r10,r8,7
-	bbo	r10,r8,8
-	bbo	r10,r8,9
-	bbo	r10,r8,10
-	bbo	r10,r8,11
-	bbo	r10,r8,12
-	bbo	r10,r8,13
-	bbo	r10,r8,14
-	bbo	r10,r8,15
-	bbo	r10,r8,16
-	bbo	r10,r8,17
-	bbo	r10,r8,18
-	bbo	r10,r8,19
-	bbo	r10,r8,20
-	bbo	r10,r8,21
-	bbo	r10,r8,22
-	bbo	r10,r8,23
-	bbo	r10,r8,24
-	bbo	r10,r8,25
-	bbo	r10,r8,26
-	bbo	r10,r8,27
-	bbo	r10,r8,28
-	bbo	r10,r8,29
-	bbo	r10,r8,30
-	bbo	r10,r8,31
-
diff --git a/gas/testsuite/gas/tic80/ccode.d b/gas/testsuite/gas/tic80/ccode.d
deleted file mode 100644
index b5a38aa7d05e..000000000000
--- a/gas/testsuite/gas/tic80/ccode.d
+++ /dev/null
@@ -1,32 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of symbolic condition code values
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	07 a0 79 01.*
-   4:	07 a0 79 09.*
-   8:	07 a0 79 11.*
-   c:	07 a0 79 19.*
-  10:	07 a0 79 21.*
-  14:	07 a0 79 29.*
-  18:	07 a0 79 31.*
-  1c:	07 a0 79 39.*
-  20:	07 a0 79 41.*
-  24:	07 a0 79 49.*
-  28:	07 a0 79 51.*
-  2c:	07 a0 79 59.*
-  30:	07 a0 79 61.*
-  34:	07 a0 79 69.*
-  38:	07 a0 79 71.*
-  3c:	07 a0 79 79.*
-  40:	07 a0 79 81.*
-  44:	07 a0 79 89.*
-  48:	07 a0 79 91.*
-  4c:	07 a0 79 99.*
-  50:	07 a0 79 a1.*
-  54:	07 a0 79 a9.*
-  58:	07 a0 79 b1.*
-  5c:	07 a0 79 b9.*
diff --git a/gas/testsuite/gas/tic80/ccode.lst b/gas/testsuite/gas/tic80/ccode.lst
deleted file mode 100644
index 460351c6e909..000000000000
--- a/gas/testsuite/gas/tic80/ccode.lst
+++ /dev/null
@@ -1,37 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:49 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-ccode.s                                                              PAGE    1
-
-        1                     ;; Test that all the predefined symbol names for the condition
-        2                     ;; codes are properly accepted and translated to numeric values.
-        3                     ;;  Also verifies that they are disassembled correctly as symbolics.
-        4                     
-        5 00000000   0179A007         bcnd.a  r7,r5,nev.b             ; 00000
-        6 00000004   0979A007         bcnd.a  r7,r5,gt0.b             ; 00001
-        7 00000008   1179A007         bcnd.a  r7,r5,eq0.b             ; 00010
-        8 0000000C   1979A007         bcnd.a  r7,r5,ge0.b             ; 00011
-        9 00000010   2179A007         bcnd.a  r7,r5,lt0.b             ; 00100
-       10 00000014   2979A007         bcnd.a  r7,r5,ne0.b             ; 00101
-       11 00000018   3179A007         bcnd.a  r7,r5,le0.b             ; 00110
-       12 0000001C   3979A007         bcnd.a  r7,r5,alw.b             ; 00111
-       13                     
-       14 00000020   4179A007         bcnd.a  r7,r5,nev.h             ; 01000
-       15 00000024   4979A007         bcnd.a  r7,r5,gt0.h             ; 01001
-       16 00000028   5179A007         bcnd.a  r7,r5,eq0.h             ; 01010
-       17 0000002C   5979A007         bcnd.a  r7,r5,ge0.h             ; 01011
-       18 00000030   6179A007         bcnd.a  r7,r5,lt0.h             ; 01100
-       19 00000034   6979A007         bcnd.a  r7,r5,ne0.h             ; 01101
-       20 00000038   7179A007         bcnd.a  r7,r5,le0.h             ; 01110
-       21 0000003C   7979A007         bcnd.a  r7,r5,alw.h             ; 01111
-       22                     
-       23 00000040   8179A007         bcnd.a  r7,r5,nev.w             ; 10000
-       24 00000044   8979A007         bcnd.a  r7,r5,gt0.w             ; 10001
-       25 00000048   9179A007         bcnd.a  r7,r5,eq0.w             ; 10010
-       26 0000004C   9979A007         bcnd.a  r7,r5,ge0.w             ; 10011
-       27 00000050   A179A007         bcnd.a  r7,r5,lt0.w             ; 10100
-       28 00000054   A979A007         bcnd.a  r7,r5,ne0.w             ; 10101
-       29 00000058   B179A007         bcnd.a  r7,r5,le0.w             ; 10110
-       30 0000005C   B979A007         bcnd.a  r7,r5,alw.w             ; 10111
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/ccode.s b/gas/testsuite/gas/tic80/ccode.s
deleted file mode 100644
index 9e4aac11552b..000000000000
--- a/gas/testsuite/gas/tic80/ccode.s
+++ /dev/null
@@ -1,30 +0,0 @@
-;; Test that all the predefined symbol names for the condition
-;; codes are properly accepted and translated to numeric values.
-;;  Also verifies that they are disassembled correctly as symbolics.
-
-	bcnd.a	r7,r5,nev.b		; 00000
-	bcnd.a	r7,r5,gt0.b		; 00001
-	bcnd.a	r7,r5,eq0.b		; 00010
-	bcnd.a	r7,r5,ge0.b		; 00011
-	bcnd.a	r7,r5,lt0.b		; 00100
-	bcnd.a	r7,r5,ne0.b		; 00101
-	bcnd.a	r7,r5,le0.b		; 00110
-	bcnd.a	r7,r5,alw.b		; 00111
-
-	bcnd.a	r7,r5,nev.h		; 01000
-	bcnd.a	r7,r5,gt0.h		; 01001
-	bcnd.a	r7,r5,eq0.h		; 01010
-	bcnd.a	r7,r5,ge0.h		; 01011
-	bcnd.a	r7,r5,lt0.h		; 01100
-	bcnd.a	r7,r5,ne0.h		; 01101
-	bcnd.a	r7,r5,le0.h		; 01110
-	bcnd.a	r7,r5,alw.h		; 01111
-
-	bcnd.a	r7,r5,nev.w		; 10000
-	bcnd.a	r7,r5,gt0.w		; 10001
-	bcnd.a	r7,r5,eq0.w		; 10010
-	bcnd.a	r7,r5,ge0.w		; 10011
-	bcnd.a	r7,r5,lt0.w		; 10100
-	bcnd.a	r7,r5,ne0.w		; 10101
-	bcnd.a	r7,r5,le0.w		; 10110
-	bcnd.a	r7,r5,alw.w		; 10111
diff --git a/gas/testsuite/gas/tic80/cregops.d b/gas/testsuite/gas/tic80/cregops.d
deleted file mode 100644
index 44b61e98c138..000000000000
--- a/gas/testsuite/gas/tic80/cregops.d
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -d
-#name: TIc80 control register operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	34 00 02 10.*
-   4:	39 00 02 10.*
-   8:	3a 00 02 10.*
-   c:	02 00 02 10.*
-  10:	00 05 02 10.*
-  14:	00 04 02 10.*
-  18:	01 04 02 10.*
-  1c:	0a 04 02 10.*
-  20:	0b 04 02 10.*
-  24:	0c 04 02 10.*
-  28:	0d 04 02 10.*
-  2c:	0e 04 02 10.*
-  30:	0f 04 02 10.*
-  34:	02 04 02 10.*
-  38:	03 04 02 10.*
-  3c:	04 04 02 10.*
-  40:	05 04 02 10.*
-  44:	06 04 02 10.*
-  48:	07 04 02 10.*
-  4c:	08 04 02 10.*
-  50:	09 04 02 10.*
-  54:	33 00 02 10.*
-  58:	01 00 02 10.*
-  5c:	00 00 02 10.*
-  60:	11 00 02 10.*
-  64:	14 00 02 10.*
-  68:	13 00 02 10.*
-  6c:	10 00 02 10.*
-  70:	12 00 02 10.*
-  74:	08 00 02 10.*
-  78:	06 00 02 10.*
-  7c:	00 03 02 10.*
-  80:	00 40 02 10.*
-  84:	01 40 02 10.*
-  88:	04 00 02 10.*
-  8c:	00 02 02 10.*
-  90:	01 02 02 10.*
-  94:	0a 02 02 10.*
-  98:	0b 02 02 10.*
-  9c:	0c 02 02 10.*
-  a0:	0d 02 02 10.*
-  a4:	0e 02 02 10.*
-  a8:	0f 02 02 10.*
-  ac:	02 02 02 10.*
-  b0:	03 02 02 10.*
-  b4:	04 02 02 10.*
-  b8:	05 02 02 10.*
-  bc:	06 02 02 10.*
-  c0:	07 02 02 10.*
-  c4:	08 02 02 10.*
-  c8:	09 02 02 10.*
-  cc:	31 00 02 10.*
-  d0:	30 00 02 10.*
-  d4:	02 40 02 10.*
-  d8:	0d 00 02 10.*
-  dc:	0a 00 02 10.*
-  e0:	20 00 02 10.*
-  e4:	21 00 02 10.*
-  e8:	0e 00 02 10.*
-  ec:	0f 00 02 10.*
diff --git a/gas/testsuite/gas/tic80/cregops.lst b/gas/testsuite/gas/tic80/cregops.lst
deleted file mode 100644
index 65ea57fe643f..000000000000
--- a/gas/testsuite/gas/tic80/cregops.lst
+++ /dev/null
@@ -1,76 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-cregops.s                                                            PAGE    1
-
-        1                     ;; Test that all predefined symbol names for control registers
-        2                     ;; are properly accepted and translated to numeric values.  Also
-        3                     ;; verifies that they are diassembled correctly as symbolics.
-        4                     
-        5 00000000   10020034         rdcr    ANASTAT,r2
-        6 00000004   10020039         rdcr    BRK1,r2
-        7 00000008   1002003A         rdcr    BRK2,r2
-        8 0000000C   10020002         rdcr    CONFIG,r2
-        9 00000010   10020500         rdcr    DLRU,r2
-       10 00000014   10020400         rdcr    DTAG0,r2
-       11 00000018   10020401         rdcr    DTAG1,r2
-       12 0000001C   1002040A         rdcr    DTAG10,r2
-       13 00000020   1002040B         rdcr    DTAG11,r2
-       14 00000024   1002040C         rdcr    DTAG12,r2
-       15 00000028   1002040D         rdcr    DTAG13,r2
-       16 0000002C   1002040E         rdcr    DTAG14,r2
-       17 00000030   1002040F         rdcr    DTAG15,r2
-       18 00000034   10020402         rdcr    DTAG2,r2
-       19 00000038   10020403         rdcr    DTAG3,r2
-       20 0000003C   10020404         rdcr    DTAG4,r2
-       21 00000040   10020405         rdcr    DTAG5,r2
-       22 00000044   10020406         rdcr    DTAG6,r2
-       23 00000048   10020407         rdcr    DTAG7,r2
-       24 0000004C   10020408         rdcr    DTAG8,r2
-       25 00000050   10020409         rdcr    DTAG9,r2
-       26 00000054   10020033         rdcr    ECOMCNTL,r2
-       27 00000058   10020001         rdcr    EIP,r2
-       28 0000005C   10020000         rdcr    EPC,r2
-       29 00000060   10020011         rdcr    FLTADR,r2
-       30 00000064   10020014         rdcr    FLTDTH,r2
-       31 00000068   10020013         rdcr    FLTDTL,r2
-       32 0000006C   10020010         rdcr    FLTOP,r2
-       33 00000070   10020012         rdcr    FLTTAG,r2
-       34 00000074   10020008         rdcr    FPST,r2
-       35 00000078   10020006         rdcr    IE,r2
-       36 0000007C   10020300         rdcr    ILRU,r2
-       37 00000080   10024000         rdcr    IN0P,r2
-       38 00000084   10024001         rdcr    IN1P,r2
-       39 00000088   10020004         rdcr    INTPEN,r2
-       40 0000008C   10020200         rdcr    ITAG0,r2
-       41 00000090   10020201         rdcr    ITAG1,r2
-       42 00000094   1002020A         rdcr    ITAG10,r2
-       43 00000098   1002020B         rdcr    ITAG11,r2
-       44 0000009C   1002020C         rdcr    ITAG12,r2
-       45 000000A0   1002020D         rdcr    ITAG13,r2
-       46 000000A4   1002020E         rdcr    ITAG14,r2
-       47 000000A8   1002020F         rdcr    ITAG15,r2
-       48 000000AC   10020202         rdcr    ITAG2,r2
-       49 000000B0   10020203         rdcr    ITAG3,r2
-       50 000000B4   10020204         rdcr    ITAG4,r2
-       51 000000B8   10020205         rdcr    ITAG5,r2
-       52 000000BC   10020206         rdcr    ITAG6,r2
-       53 000000C0   10020207         rdcr    ITAG7,r2
-       54 000000C4   10020208         rdcr    ITAG8,r2
-       55 000000C8   10020209         rdcr    ITAG9,r2
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:56 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-cregops.s                                                            PAGE    2
-
-       56 000000CC   10020031         rdcr    MIP,r2
-       57 000000D0   10020030         rdcr    MPC,r2
-       58 000000D4   10024002         rdcr    OUTP,r2
-       59 000000D8   1002000D         rdcr    PKTREQ,r2
-       60 000000DC   1002000A         rdcr    PPERROR,r2
-       61 000000E0   10020020         rdcr    SYSSTK,r2
-       62 000000E4   10020021         rdcr    SYSTMP,r2
-       63 000000E8   1002000E         rdcr    TCOUNT,r2
-       64 000000EC   1002000F         rdcr    TSCALE,r2
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/cregops.s b/gas/testsuite/gas/tic80/cregops.s
deleted file mode 100644
index 8a0adcf56527..000000000000
--- a/gas/testsuite/gas/tic80/cregops.s
+++ /dev/null
@@ -1,64 +0,0 @@
-;; Test that all predefined symbol names for control registers
-;; are properly accepted and translated to numeric values.  Also
-;; verifies that they are diassembled correctly as symbolics.
-
-	rdcr	ANASTAT,r2
-	rdcr	BRK1,r2
-	rdcr	BRK2,r2
-	rdcr	CONFIG,r2
-	rdcr	DLRU,r2
-	rdcr	DTAG0,r2
-	rdcr	DTAG1,r2
-	rdcr	DTAG10,r2
-	rdcr	DTAG11,r2
-	rdcr	DTAG12,r2
-	rdcr	DTAG13,r2
-	rdcr	DTAG14,r2
-	rdcr	DTAG15,r2
-	rdcr	DTAG2,r2
-	rdcr	DTAG3,r2
-	rdcr	DTAG4,r2
-	rdcr	DTAG5,r2
-	rdcr	DTAG6,r2
-	rdcr	DTAG7,r2
-	rdcr	DTAG8,r2
-	rdcr	DTAG9,r2
-	rdcr	ECOMCNTL,r2
-	rdcr	EIP,r2
-	rdcr	EPC,r2
-	rdcr	FLTADR,r2
-	rdcr	FLTDTH,r2
-	rdcr	FLTDTL,r2
-	rdcr	FLTOP,r2
-	rdcr	FLTTAG,r2
-	rdcr	FPST,r2
-	rdcr	IE,r2
-	rdcr	ILRU,r2
-	rdcr	IN0P,r2
-	rdcr	IN1P,r2
-	rdcr	INTPEN,r2
-	rdcr	ITAG0,r2
-	rdcr	ITAG1,r2
-	rdcr	ITAG10,r2
-	rdcr	ITAG11,r2
-	rdcr	ITAG12,r2
-	rdcr	ITAG13,r2
-	rdcr	ITAG14,r2
-	rdcr	ITAG15,r2
-	rdcr	ITAG2,r2
-	rdcr	ITAG3,r2
-	rdcr	ITAG4,r2
-	rdcr	ITAG5,r2
-	rdcr	ITAG6,r2
-	rdcr	ITAG7,r2
-	rdcr	ITAG8,r2
-	rdcr	ITAG9,r2
-	rdcr	MIP,r2
-	rdcr	MPC,r2
-	rdcr	OUTP,r2
-	rdcr	PKTREQ,r2
-	rdcr	PPERROR,r2
-	rdcr	SYSSTK,r2
-	rdcr	SYSTMP,r2
-	rdcr	TCOUNT,r2
-	rdcr	TSCALE,r2
diff --git a/gas/testsuite/gas/tic80/endmask.d b/gas/testsuite/gas/tic80/endmask.d
deleted file mode 100644
index 5cd084711139..000000000000
--- a/gas/testsuite/gas/tic80/endmask.d
+++ /dev/null
@@ -1,41 +0,0 @@
-#objdump: -d
-#name: TIc80 coverage of shift instruction ENDMASK field
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	05 00 c7 49.*
-   4:	25 00 c7 49.*
-   8:	45 00 c7 49.*
-   c:	65 00 c7 49.*
-  10:	85 00 c7 49.*
-  14:	a5 00 c7 49.*
-  18:	c5 00 c7 49.*
-  1c:	e5 00 c7 49.*
-  20:	05 01 c7 49.*
-  24:	25 01 c7 49.*
-  28:	45 01 c7 49.*
-  2c:	65 01 c7 49.*
-  30:	85 01 c7 49.*
-  34:	a5 01 c7 49.*
-  38:	c5 01 c7 49.*
-  3c:	e5 01 c7 49.*
-  40:	05 02 c7 49.*
-  44:	25 02 c7 49.*
-  48:	45 02 c7 49.*
-  4c:	65 02 c7 49.*
-  50:	85 02 c7 49.*
-  54:	a5 02 c7 49.*
-  58:	c5 02 c7 49.*
-  5c:	e5 02 c7 49.*
-  60:	05 03 c7 49.*
-  64:	25 03 c7 49.*
-  68:	45 03 c7 49.*
-  6c:	65 03 c7 49.*
-  70:	85 03 c7 49.*
-  74:	a5 03 c7 49.*
-  78:	c5 03 c7 49.*
-  7c:	e5 03 c7 49.*
-  80:	05 00 c7 49.*
diff --git a/gas/testsuite/gas/tic80/endmask.lst b/gas/testsuite/gas/tic80/endmask.lst
deleted file mode 100644
index 9103b33dd715..000000000000
--- a/gas/testsuite/gas/tic80/endmask.lst
+++ /dev/null
@@ -1,45 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:29 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-endmask.s                                                            PAGE    1
-
-        1                     ;; Test all possible combinations of the endmask in bits 5-9.
-        2                     ;; The mask that is used is computed as 2**bits-1 where bits
-        3                     ;; are the bits 5-9 from the instruction.  Note that 0 and 32
-        4                     ;; are treated identically, and disassembled as 0.
-        5                     
-        6 00000000   49C70005         sl.iz   5,0,r7,r9
-        7 00000004   49C70025         sl.iz   5,1,r7,r9
-        8 00000008   49C70045         sl.iz   5,2,r7,r9
-        9 0000000C   49C70065         sl.iz   5,3,r7,r9
-       10 00000010   49C70085         sl.iz   5,4,r7,r9
-       11 00000014   49C700A5         sl.iz   5,5,r7,r9
-       12 00000018   49C700C5         sl.iz   5,6,r7,r9
-       13 0000001C   49C700E5         sl.iz   5,7,r7,r9
-       14 00000020   49C70105         sl.iz   5,8,r7,r9
-       15 00000024   49C70125         sl.iz   5,9,r7,r9
-       16 00000028   49C70145         sl.iz   5,10,r7,r9
-       17 0000002C   49C70165         sl.iz   5,11,r7,r9
-       18 00000030   49C70185         sl.iz   5,12,r7,r9
-       19 00000034   49C701A5         sl.iz   5,13,r7,r9
-       20 00000038   49C701C5         sl.iz   5,14,r7,r9
-       21 0000003C   49C701E5         sl.iz   5,15,r7,r9
-       22 00000040   49C70205         sl.iz   5,16,r7,r9
-       23 00000044   49C70225         sl.iz   5,17,r7,r9
-       24 00000048   49C70245         sl.iz   5,18,r7,r9
-       25 0000004C   49C70265         sl.iz   5,19,r7,r9
-       26 00000050   49C70285         sl.iz   5,20,r7,r9
-       27 00000054   49C702A5         sl.iz   5,21,r7,r9
-       28 00000058   49C702C5         sl.iz   5,22,r7,r9
-       29 0000005C   49C702E5         sl.iz   5,23,r7,r9
-       30 00000060   49C70305         sl.iz   5,24,r7,r9
-       31 00000064   49C70325         sl.iz   5,25,r7,r9
-       32 00000068   49C70345         sl.iz   5,26,r7,r9
-       33 0000006C   49C70365         sl.iz   5,27,r7,r9
-       34 00000070   49C70385         sl.iz   5,28,r7,r9
-       35 00000074   49C703A5         sl.iz   5,29,r7,r9
-       36 00000078   49C703C5         sl.iz   5,30,r7,r9
-       37 0000007C   49C703E5         sl.iz   5,31,r7,r9
-       38 00000080   49C70005         sl.iz   5,32,r7,r9
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/endmask.s b/gas/testsuite/gas/tic80/endmask.s
deleted file mode 100644
index a36aedebafea..000000000000
--- a/gas/testsuite/gas/tic80/endmask.s
+++ /dev/null
@@ -1,38 +0,0 @@
-;; Test all possible combinations of the endmask in bits 5-9.
-;; The mask that is used is computed as 2**bits-1 where bits
-;; are the bits 5-9 from the instruction.  Note that 0 and 32
-;; are treated identically, and disassembled as 0.
-
-	sl.iz	5,0,r7,r9
-	sl.iz	5,1,r7,r9
-	sl.iz	5,2,r7,r9
-	sl.iz	5,3,r7,r9
-	sl.iz	5,4,r7,r9
-	sl.iz	5,5,r7,r9
-	sl.iz	5,6,r7,r9
-	sl.iz	5,7,r7,r9
-	sl.iz	5,8,r7,r9
-	sl.iz	5,9,r7,r9
-	sl.iz	5,10,r7,r9
-	sl.iz	5,11,r7,r9
-	sl.iz	5,12,r7,r9
-	sl.iz	5,13,r7,r9
-	sl.iz	5,14,r7,r9
-	sl.iz	5,15,r7,r9
-	sl.iz	5,16,r7,r9
-	sl.iz	5,17,r7,r9
-	sl.iz	5,18,r7,r9
-	sl.iz	5,19,r7,r9
-	sl.iz	5,20,r7,r9
-	sl.iz	5,21,r7,r9
-	sl.iz	5,22,r7,r9
-	sl.iz	5,23,r7,r9
-	sl.iz	5,24,r7,r9
-	sl.iz	5,25,r7,r9
-	sl.iz	5,26,r7,r9
-	sl.iz	5,27,r7,r9
-	sl.iz	5,28,r7,r9
-	sl.iz	5,29,r7,r9
-	sl.iz	5,30,r7,r9
-	sl.iz	5,31,r7,r9
-	sl.iz	5,32,r7,r9
diff --git a/gas/testsuite/gas/tic80/float.d b/gas/testsuite/gas/tic80/float.d
deleted file mode 100644
index 87eb85ba7c5c..000000000000
--- a/gas/testsuite/gas/tic80/float.d
+++ /dev/null
@@ -1,40 +0,0 @@
-#objdump: -d
-#name: TIc80 simple floating point operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	80 12 be 51 16 68 a9 65.*
-   8:	00 12 be 51 16 68 a9 e5.*
-  10:	00 10 be 51 9a 6d 41 19.*
-  18:	80 b0 3e 52 9a 6d 41 99.*
-  20:	00 b0 3e 52 00 00 00 00.*
-  28:	80 72 be 51 00 00 00 40.*
-  30:	00 72 be 51 00 00 00 3f.*
-  38:	00 70 be 51 00 00 80 45.*
-  40:	80 52 be 51 00 00 80 c5.*
-  48:	00 52 be 51 00 00 00 40.*
-  50:	00 50 be 51 00 00 00 40.*
-  58:	80 93 3e 40 00 00 00 40.*
-  60:	80 95 3e 40 00 00 00 40.*
-  68:	80 91 3e 40 00 00 00 40.*
-  70:	80 97 3e 40 00 00 00 40.*
-  78:	00 92 3e 40 00 00 00 40.*
-  80:	00 94 3e 40 00 00 00 40.*
-  88:	00 90 3e 40 00 00 00 40.*
-  90:	00 96 3e 40 00 00 00 40.*
-  98:	00 93 3e 40 00 00 00 40.*
-  a0:	00 95 3e 40 00 00 00 40.*
-  a8:	00 91 3e 40 00 00 00 40.*
-  b0:	00 97 3e 40 00 00 00 40.*
-  b8:	80 92 3e 40 00 00 00 40.*
-  c0:	80 94 3e 40 00 00 00 40.*
-  c8:	80 90 3e 40 00 00 00 40.*
-  d0:	80 96 3e 40 00 00 00 40.*
-  d8:	00 f2 3e 50 00 00 00 40.*
-  e0:	00 f0 3e 50 00 00 00 40.*
-  e8:	80 32 be 51 00 00 00 40.*
-  f0:	00 32 be 51 00 00 00 40.*
-  f8:	00 30 be 51 00 00 00 40.*
diff --git a/gas/testsuite/gas/tic80/float.lst b/gas/testsuite/gas/tic80/float.lst
deleted file mode 100644
index 6134590ca6e7..000000000000
--- a/gas/testsuite/gas/tic80/float.lst
+++ /dev/null
@@ -1,76 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 22:09:09 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-float.s                                                              PAGE    1
-
-        1 00000000   51BE1280         fadd.sdd        1.0E23,r6,r10   ; Immediate form
-          00000004   65A96816 
-        2 00000008   51BE1200         fadd.ssd        -1.0E23,r6,r10  ; Immediate form
-          0000000C   E5A96816 
-        3 00000010   51BE1000         fadd.sss        1.0E-23,r6,r10  ; Immediate form
-          00000014   19416D9A 
-        4 00000018   523EB080         fcmp.sd         -1.0E-23,r8,r10 ; Immediate form
-          0000001C   99416D9A 
-        5 00000020   523EB000         fcmp.ss         0.0,r8,r10      ; Immediate form
-          00000024   00000000 
-        6 00000028   51BE7280         fdiv.sdd        2.0,r6,r10      ; Immediate form
-          0000002C   40000000 
-        7 00000030   51BE7200         fdiv.ssd        0.5,r6,r10      ; Immediate form
-          00000034   3F000000 
-        8 00000038   51BE7000         fdiv.sss        4096.0,r6,r10   ; Immediate form
-          0000003C   45800000 
-        9 00000040   51BE5280         fmpy.sdd        -4096.0,r6,r10  ; Immediate form
-          00000044   C5800000 
-       10 00000048   51BE5200         fmpy.ssd        2.0,r6,r10      ; Immediate form
-          0000004C   40000000 
-       11 00000050   51BE5000         fmpy.sss        2.0,r6,r10      ; Immediate form
-          00000054   40000000 
-       12 00000058   403E9380         frndm.sd        2.0,r8          ; Immediate form
-          0000005C   40000000 
-       13 00000060   403E9580         frndm.si        2.0,r8          ; Immediate form
-          00000064   40000000 
-       14 00000068   403E9180         frndm.ss        2.0,r8          ; Immediate form
-          0000006C   40000000 
-       15 00000070   403E9780         frndm.su        2.0,r8          ; Immediate form
-          00000074   40000000 
-       16 00000078   403E9200         frndn.sd        2.0,r8          ; Immediate form
-          0000007C   40000000 
-       17 00000080   403E9400         frndn.si        2.0,r8          ; Immediate form
-          00000084   40000000 
-       18 00000088   403E9000         frndn.ss        2.0,r8          ; Immediate form
-          0000008C   40000000 
-       19 00000090   403E9600         frndn.su        2.0,r8          ; Immediate form
-          00000094   40000000 
-       20 00000098   403E9300         frndp.sd        2.0,r8          ; Immediate form
-          0000009C   40000000 
-       21 000000A0   403E9500         frndp.si        2.0,r8          ; Immediate form
-          000000A4   40000000 
-       22 000000A8   403E9100         frndp.ss        2.0,r8          ; Immediate form
-          000000AC   40000000 
-       23 000000B0   403E9700         frndp.su        2.0,r8          ; Immediate form
-          000000B4   40000000 
-       24 000000B8   403E9280         frndz.sd        2.0,r8          ; Immediate form
-          000000BC   40000000 
-       25 000000C0   403E9480         frndz.si        2.0,r8          ; Immediate form
-          000000C4   40000000 
-       26 000000C8   403E9080         frndz.ss        2.0,r8          ; Immediate form
-          000000CC   40000000 
-       27 000000D0   403E9680         frndz.su        2.0,r8          ; Immediate form
-          000000D4   40000000 
-       28 000000D8   503EF200         fsqrt.sd        2.0,r10         ; Immediate form
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 22:09:09 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-float.s                                                              PAGE    2
-
-          000000DC   40000000 
-       29 000000E0   503EF000         fsqrt.ss        2.0,r10         ; Immediate form
-          000000E4   40000000 
-       30 000000E8   51BE3280         fsub.sdd        2.0,r6,r10      ; Immediate form
-          000000EC   40000000 
-       31 000000F0   51BE3200         fsub.ssd        2.0,r6,r10      ; Immediate form
-          000000F4   40000000 
-       32 000000F8   51BE3000         fsub.sss        2.0,r6,r10      ; Immediate form
-          000000FC   40000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/float.s b/gas/testsuite/gas/tic80/float.s
deleted file mode 100644
index 98a2b7ae83d3..000000000000
--- a/gas/testsuite/gas/tic80/float.s
+++ /dev/null
@@ -1,32 +0,0 @@
-	fadd.sdd	0f1.0E23,r6,r10	; Immediate form
-	fadd.ssd	0f-1.0E23,r6,r10	; Immediate form
-	fadd.sss	0f1.0E-23,r6,r10	; Immediate form
-	fcmp.sd		0f-1.0E-23,r8,r10	; Immediate form
-	fcmp.ss		0f0.0,r8,r10	; Immediate form
-	fdiv.sdd	0f2.0,r6,r10	; Immediate form
-	fdiv.ssd	0f0.5,r6,r10	; Immediate form
-	fdiv.sss	0f4096.0,r6,r10	; Immediate form
-	fmpy.sdd	0f-4096.0,r6,r10	; Immediate form
-	fmpy.ssd	0f2.0,r6,r10	; Immediate form
-	fmpy.sss	0f2.0,r6,r10	; Immediate form
-	frndm.sd	0f2.0,r8		; Immediate form
-	frndm.si	0f2.0,r8		; Immediate form
-	frndm.ss	0f2.0,r8		; Immediate form
-	frndm.su	0f2.0,r8		; Immediate form
-	frndn.sd	0f2.0,r8		; Immediate form
-	frndn.si	0f2.0,r8		; Immediate form
-	frndn.ss	0f2.0,r8		; Immediate form
-	frndn.su	0f2.0,r8		; Immediate form
-	frndp.sd	0f2.0,r8		; Immediate form
-	frndp.si	0f2.0,r8		; Immediate form
-	frndp.ss	0f2.0,r8		; Immediate form
-	frndp.su	0f2.0,r8		; Immediate form
-	frndz.sd	0f2.0,r8		; Immediate form
-	frndz.si	0f2.0,r8		; Immediate form
-	frndz.ss	0f2.0,r8		; Immediate form
-	frndz.su	0f2.0,r8		; Immediate form
-	fsqrt.sd	0f2.0,r10		; Immediate form
-	fsqrt.ss	0f2.0,r10		; Immediate form
-	fsub.sdd	0f2.0,r6,r10	; Immediate form
-	fsub.ssd	0f2.0,r6,r10	; Immediate form
-	fsub.sss	0f2.0,r6,r10	; Immediate form
diff --git a/gas/testsuite/gas/tic80/regops.d b/gas/testsuite/gas/tic80/regops.d
deleted file mode 100644
index dd0fa85753c4..000000000000
--- a/gas/testsuite/gas/tic80/regops.d
+++ /dev/null
@@ -1,188 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	03 00 3b 29.*
-   4:	03 20 3b 29.*
-   8:	05 20 32 11.*
-   c:	05 20 32 11.*
-  10:	0a 00 33 73.*
-  14:	0a 80 32 73.*
-  18:	0a 40 32 73.*
-  1c:	0a 40 39 1a.*
-  20:	0a 60 39 fa.*
-  24:	0a 00 39 22.*
-  28:	0a 20 39 2a.*
-  2c:	04 80 b9 21.*
-  30:	04 a0 b9 21.*
-  34:	06 00 39 00.*
-  38:	06 20 39 00.*
-  3c:	0a 00 03 00.*
-  40:	06 00 38 f8.*
-  44:	06 20 38 f8.*
-  48:	07 40 30 00.*
-  4c:	03 00 3a 29.*
-  50:	08 00 b7 02.*
-  54:	08 00 b7 0a.*
-  58:	04 04 b4 41.*
-  5c:	04 24 b4 41.*
-  60:	04 44 b4 41.*
-  64:	04 64 b4 41.*
-  68:	04 04 b5 41.*
-  6c:	04 24 b5 41.*
-  70:	04 04 b6 41.*
-  74:	04 24 b6 41.*
-  78:	04 44 b6 41.*
-  7c:	04 64 b6 41.*
-  80:	05 20 30 08.*
-  84:	e3 47 71 31.*
-  88:	c2 07 71 49.*
-  8c:	02 00 3e 31.*
-  90:	02 02 3e 31.*
-  94:	82 02 3e 31.*
-  98:	22 02 3e 31.*
-  9c:	a2 02 3e 31.*
-  a0:	04 a0 be 41.*
-  a4:	84 a0 be 41.*
-  a8:	24 a0 be 41.*
-  ac:	a4 a0 be 41.*
-  b0:	02 60 3e 31.*
-  b4:	02 62 3e 31.*
-  b8:	82 62 3e 31.*
-  bc:	22 62 3e 31.*
-  c0:	a2 62 3e 31.*
-  c4:	02 40 3e 31.*
-  c8:	02 42 3e 31.*
-  cc:	82 42 3e 31.*
-  d0:	22 42 3e 31.*
-  d4:	a2 42 3e 31.*
-  d8:	42 45 3e 31.*
-  dc:	e2 47 3e 31.*
-  e0:	84 81 3e 30.*
-  e4:	84 83 3e 30.*
-  e8:	84 85 3e 30.*
-  ec:	84 87 3e 30.*
-  f0:	a2 81 3e 40.*
-  f4:	a2 83 3e 40.*
-  f8:	a2 85 3e 40.*
-  fc:	a2 87 3e 40.*
- 100:	c4 81 3e 30.*
- 104:	c4 83 3e 30.*
- 108:	e2 81 3e 40.*
- 10c:	e2 83 3e 40.*
- 110:	04 80 3e 30.*
- 114:	04 82 3e 30.*
- 118:	04 84 3e 30.*
- 11c:	04 86 3e 30.*
- 120:	22 80 3e 40.*
- 124:	22 82 3e 40.*
- 128:	22 84 3e 40.*
- 12c:	22 86 3e 40.*
- 130:	44 80 3e 30.*
- 134:	44 82 3e 30.*
- 138:	62 80 3e 40.*
- 13c:	62 82 3e 40.*
- 140:	04 81 3e 30.*
- 144:	04 83 3e 30.*
- 148:	04 85 3e 30.*
- 14c:	04 87 3e 30.*
- 150:	22 81 3e 40.*
- 154:	22 83 3e 40.*
- 158:	22 85 3e 40.*
- 15c:	22 87 3e 40.*
- 160:	44 81 3e 30.*
- 164:	44 83 3e 30.*
- 168:	62 81 3e 40.*
- 16c:	62 83 3e 40.*
- 170:	84 80 3e 30.*
- 174:	84 82 3e 30.*
- 178:	84 84 3e 30.*
- 17c:	84 86 3e 30.*
- 180:	a2 80 3e 40.*
- 184:	a2 82 3e 40.*
- 188:	a2 84 3e 40.*
- 18c:	a2 86 3e 40.*
- 190:	c4 80 3e 30.*
- 194:	c4 82 3e 30.*
- 198:	e2 80 3e 40.*
- 19c:	e2 82 3e 40.*
- 1a0:	06 e0 3e 40.*
- 1a4:	06 e2 3e 40.*
- 1a8:	26 e2 3e 40.*
- 1ac:	02 20 3e 31.*
- 1b0:	02 22 3e 31.*
- 1b4:	82 22 3e 31.*
- 1b8:	22 22 3e 31.*
- 1bc:	a2 22 3e 31.*
- 1c0:	e4 e3 31 52.*
- 1c4:	04 80 b8 41.*
- 1c8:	04 a0 b8 41.*
- 1cc:	04 00 b4 41.*
- 1d0:	04 20 b4 41.*
- 1d4:	04 40 b4 41.*
- 1d8:	04 60 b4 41.*
- 1dc:	04 00 b5 41.*
- 1e0:	04 20 b5 41.*
- 1e4:	00 00 ff 41.*
- 1e8:	01 e0 b2 18.*
- 1ec:	01 e0 b2 18.*
- 1f0:	01 c0 b3 18.*
- 1f4:	01 a0 b3 18.*
- 1f8:	01 60 b3 18.*
- 1fc:	06 80 30 20.*
- 200:	00 20 3f 29.*
- 204:	e2 03 31 52.*
- 208:	e8 07 b1 30.*
- 20c:	e4 c3 b1 30.*
- 210:	84 01 71 31.*
- 214:	84 21 71 31.*
- 218:	84 41 71 31.*
- 21c:	84 61 71 31.*
- 220:	84 81 71 31.*
- 224:	84 a1 71 31.*
- 228:	84 c1 71 31.*
- 22c:	84 e1 71 31.*
- 230:	84 09 71 31.*
- 234:	84 29 71 31.*
- 238:	84 49 71 31.*
- 23c:	84 69 71 31.*
- 240:	84 89 71 31.*
- 244:	84 a9 71 31.*
- 248:	84 c9 71 31.*
- 24c:	84 e9 71 31.*
- 250:	84 05 71 31.*
- 254:	84 25 71 31.*
- 258:	84 45 71 31.*
- 25c:	84 65 71 31.*
- 260:	84 85 71 31.*
- 264:	84 a5 71 31.*
- 268:	84 c5 71 31.*
- 26c:	84 e5 71 31.*
- 270:	04 a4 b1 41.*
- 274:	84 0d 71 31.*
- 278:	84 2d 71 31.*
- 27c:	84 4d 71 31.*
- 280:	84 6d 71 31.*
- 284:	84 8d 71 31.*
- 288:	84 ad 71 31.*
- 28c:	84 cd 71 31.*
- 290:	84 ed 71 31.*
- 294:	04 64 b1 41.*
- 298:	04 00 b6 41.*
- 29c:	04 20 b6 41.*
- 2a0:	04 40 b6 41.*
- 2a4:	04 60 b6 41.*
- 2a8:	07 40 3b 4a.*
- 2ac:	07 60 3b 4a.*
- 2b0:	08 a0 b0 21.*
- 2b4:	0a 20 30 00.*
- 2b8:	02 00 3c 01.*
- 2bc:	82 00 bc 01.*
- 2c0:	a2 00 bc 02.*
- 2c4:	06 a0 70 01.*
- 2c8:	05 20 b3 39.*
- 2cc:	07 c0 32 4a.*
diff --git a/gas/testsuite/gas/tic80/regops.lst b/gas/testsuite/gas/tic80/regops.lst
deleted file mode 100644
index f889dd1a08f5..000000000000
--- a/gas/testsuite/gas/tic80/regops.lst
+++ /dev/null
@@ -1,264 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    1
-
-        1                     ;; Simple register forms
-        2                     ;; Those instructions which also use an immediate just use a constant.
-        3                     
-        4 00000000                    .text
-        5                     
-        6 00000000   293B0003         add             r3,r4,r5
-        7 00000004   293B2003         addu            r3,r4,r5
-        8 00000008   11322005         and             r5,r4,r2
-        9 0000000C   11322005         and.tt          r5,r4,r2
-       10 00000010   7333000A         and.ff          r10,r12,r14
-       11 00000014   7332800A         and.ft          r10,r12,r14
-       12 00000018   7332400A         and.tf          r10,r12,r14
-       13 0000001C   1A39400A         bbo             r10,r8,lo.w
-       14 00000020   FA39600A         bbo.a           r10,r8,eq.b
-       15 00000024   2239000A         bbz             r10,r8,ls.w
-       16 00000028   2A39200A         bbz.a           r10,r8,hi.w
-       17 0000002C   21B98004         bcnd            r4,r6,lt0.b
-       18 00000030   21B9A004         bcnd.a          r4,r6,lt0.b
-       19 00000034   00390006         br              r6
-       20 00000038   00392006         br.a            r6
-       21 0000003C   0003000A         brcr            10
-       22 00000040   F8380006         bsr             r6,r31
-       23 00000044   F8382006         bsr.a           r6,r31
-       24 00000048   00304007         cmnd            r7
-       25 0000004C   293A0003         cmp             r3,r4,r5
-       26 00000050   02B70008         dcachec         r8(r10)
-       27 00000054   0AB70008         dcachef         r8(r10)
-       28 00000058   41B40404         dld.b           r4(r6),r8
-       29 0000005C   41B42404         dld.h           r4(r6),r8
-       30 00000060   41B44404         dld             r4(r6),r8
-       31 00000064   41B46404         dld.d           r4(r6),r8
-       32 00000068   41B50404         dld.ub          r4(r6),r8
-       33 0000006C   41B52404         dld.uh          r4(r6),r8
-       34 00000070   41B60404         dst.b           r4(r6),r8
-       35 00000074   41B62404         dst.h           r4(r6),r8
-       36 00000078   41B64404         dst             r4(r6),r8
-       37 0000007C   41B66404         dst.d           r4(r6),r8
-       38 00000080   08302005         etrap           r5
-       39 00000084   317147E3         exts            r3,31,r5,r6
-       40 00000088   497107C2         extu            r2,30,r5,r9
-       41 0000008C   313E0002         fadd.sss        r2,r4,r6
-       42 00000090   313E0202         fadd.ssd        r2,r4,r6
-       43 00000094   313E0282         fadd.sdd        r2,r4,r6
-       44 00000098   313E0222         fadd.dsd        r2,r4,r6
-       45 0000009C   313E02A2         fadd.ddd        r2,r4,r6
-       46 000000A0   41BEA004         fcmp.ss         r4,r6,r8
-       47 000000A4   41BEA084         fcmp.sd         r4,r6,r8
-       48 000000A8   41BEA024         fcmp.ds         r4,r6,r8
-       49 000000AC   41BEA0A4         fcmp.dd         r4,r6,r8
-       50 000000B0   313E6002         fdiv.sss        r2,r4,r6
-       51 000000B4   313E6202         fdiv.ssd        r2,r4,r6
-       52 000000B8   313E6282         fdiv.sdd        r2,r4,r6
-       53 000000BC   313E6222         fdiv.dsd        r2,r4,r6
-       54 000000C0   313E62A2         fdiv.ddd        r2,r4,r6
-       55 000000C4   313E4002         fmpy.sss        r2,r4,r6
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    2
-
-       56 000000C8   313E4202         fmpy.ssd        r2,r4,r6
-       57 000000CC   313E4282         fmpy.sdd        r2,r4,r6
-       58 000000D0   313E4222         fmpy.dsd        r2,r4,r6
-       59 000000D4   313E42A2         fmpy.ddd        r2,r4,r6
-       60 000000D8   313E4542         fmpy.iii        r2,r4,r6
-       61 000000DC   313E47E2         fmpy.uuu        r2,r4,r6
-       62 000000E0   303E8184         frndm.ss        r4,r6
-       63 000000E4   303E8384         frndm.sd        r4,r6
-       64 000000E8   303E8584         frndm.si        r4,r6
-       65 000000EC   303E8784         frndm.su        r4,r6
-       66 000000F0   403E81A2         frndm.ds        r2,r8
-       67 000000F4   403E83A2         frndm.dd        r2,r8
-       68 000000F8   403E85A2         frndm.di        r2,r8
-       69 000000FC   403E87A2         frndm.du        r2,r8
-       70 00000100   303E81C4         frndm.is        r4,r6
-       71 00000104   303E83C4         frndm.id        r4,r6
-       72 00000108   403E81E2         frndm.us        r2,r8
-       73 0000010C   403E83E2         frndm.ud        r2,r8
-       74 00000110   303E8004         frndn.ss        r4,r6
-       75 00000114   303E8204         frndn.sd        r4,r6
-       76 00000118   303E8404         frndn.si        r4,r6
-       77 0000011C   303E8604         frndn.su        r4,r6
-       78 00000120   403E8022         frndn.ds        r2,r8
-       79 00000124   403E8222         frndn.dd        r2,r8
-       80 00000128   403E8422         frndn.di        r2,r8
-       81 0000012C   403E8622         frndn.du        r2,r8
-       82 00000130   303E8044         frndn.is        r4,r6
-       83 00000134   303E8244         frndn.id        r4,r6
-       84 00000138   403E8062         frndn.us        r2,r8
-       85 0000013C   403E8262         frndn.ud        r2,r8
-       86 00000140   303E8104         frndp.ss        r4,r6
-       87 00000144   303E8304         frndp.sd        r4,r6
-       88 00000148   303E8504         frndp.si        r4,r6
-       89 0000014C   303E8704         frndp.su        r4,r6
-       90 00000150   403E8122         frndp.ds        r2,r8
-       91 00000154   403E8322         frndp.dd        r2,r8
-       92 00000158   403E8522         frndp.di        r2,r8
-       93 0000015C   403E8722         frndp.du        r2,r8
-       94 00000160   303E8144         frndp.is        r4,r6
-       95 00000164   303E8344         frndp.id        r4,r6
-       96 00000168   403E8162         frndp.us        r2,r8
-       97 0000016C   403E8362         frndp.ud        r2,r8
-       98 00000170   303E8084         frndz.ss        r4,r6
-       99 00000174   303E8284         frndz.sd        r4,r6
-      100 00000178   303E8484         frndz.si        r4,r6
-      101 0000017C   303E8684         frndz.su        r4,r6
-      102 00000180   403E80A2         frndz.ds        r2,r8
-      103 00000184   403E82A2         frndz.dd        r2,r8
-      104 00000188   403E84A2         frndz.di        r2,r8
-      105 0000018C   403E86A2         frndz.du        r2,r8
-      106 00000190   303E80C4         frndz.is        r4,r6
-      107 00000194   303E82C4         frndz.id        r4,r6
-      108 00000198   403E80E2         frndz.us        r2,r8
-      109 0000019C   403E82E2         frndz.ud        r2,r8
-      110 000001A0   403EE006         fsqrt.ss        r6,r8
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    3
-
-      111 000001A4   403EE206         fsqrt.sd        r6,r8
-      112 000001A8   403EE226         fsqrt.dd        r6,r8
-      113 000001AC   313E2002         fsub.sss        r2,r4,r6
-      114 000001B0   313E2202         fsub.ssd        r2,r4,r6
-      115 000001B4   313E2282         fsub.sdd        r2,r4,r6
-      116 000001B8   313E2222         fsub.dsd        r2,r4,r6
-      117 000001BC   313E22A2         fsub.ddd        r2,r4,r6
-      118 000001C0   5231E3E4         ins             r4,31,r8,r10
-      119 000001C4   41B88004         jsr             r4(r6),r8
-      120 000001C8   41B8A004         jsr.a           r4(r6),r8
-      121 000001CC   41B40004         ld.b            r4(r6),r8
-      122 000001D0   41B42004         ld.h            r4(r6),r8
-      123 000001D4   41B44004         ld              r4(r6),r8
-      124 000001D8   41B46004         ld.d            r4(r6),r8
-      125 000001DC   41B50004         ld.ub           r4(r6),r8
-      126 000001E0   41B52004         ld.uh           r4(r6),r8
-      127 000001E4   41FF0007         lmo             r7,r8
-      128 000001E8   18B2E001         or              r1,r2,r3
-      129 000001EC   18B2E001         or.tt           r1,r2,r3
-      130 000001F0   18B3C001         or.ff           r1,r2,r3
-      131 000001F4   18B3A001         or.ft           r1,r2,r3
-      132 000001F8   18B36001         or.tf           r1,r2,r3
-      133 000001FC   20308006         rdcr            r6,r4
-      134 00000200   293F2004         rmo             r4,r5
-      135 00000204   523103E2         rotl            r2,31,r8,r10
-      136 00000208   30B107E8         rotr            r8,31,r2,r6
-      137 0000020C   30B1C3E4         shl             r4,31,r2,r6
-      138 00000210   31710184         sl.dz           r4,12,r5,r6
-      139 00000214   31712184         sl.dm           r4,12,r5,r6
-      140 00000218   31714184         sl.ds           r4,12,r5,r6
-      141 0000021C   31716184         sl.ez           r4,12,r5,r6
-      142 00000220   31718184         sl.em           r4,12,r5,r6
-      143 00000224   3171A184         sl.es           r4,12,r5,r6
-      144 00000228   3171C184         sl.iz           r4,12,r5,r6
-      145 0000022C   3171E184         sl.im           r4,12,r5,r6
-      146 00000230   31710984         sli.dz          r4,12,r5,r6
-      147 00000234   31712984         sli.dm          r4,12,r5,r6
-      148 00000238   31714984         sli.ds          r4,12,r5,r6
-      149 0000023C   31716984         sli.ez          r4,12,r5,r6
-      150 00000240   31718984         sli.em          r4,12,r5,r6
-      151 00000244   3171A984         sli.es          r4,12,r5,r6
-      152 00000248   3171C984         sli.iz          r4,12,r5,r6
-      153 0000024C   3171E984         sli.im          r4,12,r5,r6
-      154 00000250   31710584         sr.dz           r4,12,r5,r6
-      155 00000254   31712584         sr.dm           r4,12,r5,r6
-      156 00000258   31714584         sr.ds           r4,12,r5,r6
-      157 0000025C   31716584         sr.ez           r4,12,r5,r6
-      158 00000260   31718584         sr.em           r4,12,r5,r6
-      159 00000264   3171A584         sr.es           r4,12,r5,r6
-      160 00000268   3171C584         sr.iz           r4,12,r5,r6
-      161 0000026C   3171E584         sr.im           r4,12,r5,r6
-      162 00000270   41B1A404         sra             r4,32,r6,r8
-      163 00000274   31710D84         sri.dz          r4,12,r5,r6
-      164 00000278   31712D84         sri.dm          r4,12,r5,r6
-      165 0000027C   31714D84         sri.ds          r4,12,r5,r6
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    4
-
-      166 00000280   31716D84         sri.ez          r4,12,r5,r6
-      167 00000284   31718D84         sri.em          r4,12,r5,r6
-      168 00000288   3171AD84         sri.es          r4,12,r5,r6
-      169 0000028C   3171CD84         sri.iz          r4,12,r5,r6
-      170 00000290   3171ED84         sri.im          r4,12,r5,r6
-      171 00000294   41B16404         srl             r4,32,r6,r8
-      172 00000298   41B60004         st.b            r4(r6),r8
-      173 0000029C   41B62004         st.h            r4(r6),r8
-      174 000002A0   41B64004         st              r4(r6),r8
-      175 000002A4   41B66004         st.d            r4(r6),r8
-      176 000002A8   4A3B4007         sub             r7,r8,r9
-      177 000002AC   4A3B6007         subu            r7,r8,r9
-      178 000002B0   21B0A008         swcr            r8,r6,r4
-      179 000002B4   0030200A         trap            r10
-      180 000002B8   013C0002         vadd.ss         r2,r4,r4
-      181 000002BC   01BC0082         vadd.sd         r2,r6,r6
-      182 000002C0   02BC00A2         vadd.dd         r2,r10,r10
-      183                     ;       vld0.s          r6
-      184                     ;       vld1.s          r7
-      185                     ;       vld0.d          r6
-      186                     ;       vld1.d          r8
-      187                     ;       vmac.sss        r7,r9,0,a3
-      188                     ;       vmac.sss        r7,r9,0,r10
-      189                     ;       vmac.sss        r7,r9,a1,a3
-      190                     ;       vmac.sss        r7,r9,a3,r10
-      191                     ;       vmac.ssd        r7,r9,0,a0
-      192                     ;       vmac.ssd        r7,r9,0,r10
-      193                     ;       vmac.ssd        r7,r9,a1,a2
-      194                     ;       vmac.ssd        r7,r9,a3,r10
-      195                     ;       vmpy.ss         r1,r3,r3
-      196                     ;       vmpy.sd         r5,r6,r6
-      197                     ;       vmpy.dd         r2,r4,r4
-      198                     ;       vmsc.sss        r7,r9,0,a0
-      199                     ;       vmsc.sss        r7,r9,0,r10
-      200                     ;       vmsc.sss        r7,r9,a0,a1
-      201                     ;       vmsc.sss        r7,r9,a3,r10
-      202                     ;       vmsc.ssd        r7,r9,0,a0
-      203                     ;       vmsc.ssd        r7,r9,0,r10
-      204                     ;       vmsc.ssd        r7,r9,a0,a1
-      205                     ;       vmsc.ssd        r7,r9,a3,r10
-      206                     ;       vmsub.ss        r6,a2,a4
-      207                     ;       vmsub.sd        r6,a2,a4
-      208                     ;       vmsub.ss        r4,a4,r6
-      209                     ;       vmsub.sd        r4,a4,r6
-      210                     ;       vrnd.si         r4,r6
-      211                     ;       vrnd.si         r4,a0
-      212                     ;       vrnd.su         r4,r6
-      213                     ;       vrnd.su         r4,a0
-      214                     ;       vrnd.ss         r4,r6
-      215                     ;       vrnd.ss         r4,a0
-      216                     ;       vrnd.sd         r4,r6
-      217                     ;       vrnd.sd         r4,a0
-      218                     ;       vrnd.di         r4,r6
-      219                     ;       vrnd.di         r4,a0
-      220                     ;       vrnd.du         r4,r6
-MVP MP Macro Assembler     Version 1.13     Mon Feb 10 17:00:24 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops.s                                                             PAGE    5
-
-      221                     ;       vrnd.du         r4,a0
-      222                     ;       vrnd.ds         r4,r6
-      223                     ;       vrnd.ds         r4,a0
-      224                     ;       vrnd.dd         r4,r6
-      225                     ;       vrnd.dd         r4,a0
-      226                     ;       vrnd.is         r4,r6
-      227                     ;       vrnd.id         r4,r6
-      228                     ;       vrnd.us         r4,r6
-      229                     ;       vrnd.ud         r4,r6
-      230                     ;       vst.s           r6
-      231                     ;       vst.d           r6
-      232                     ;       vsub.ss         r2,r4,r6
-      233                     ;       vsub.sd         r2,r4,r6
-      234                     ;       vsub.dd         r2,r4,r6
-      235 000002C4   0170A006         wrcr            r6,r5
-      236 000002C8   39B32005         xnor            r5,r6,r7
-      237 000002CC   4A32C007         xor             r7,r8,r9
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops.s b/gas/testsuite/gas/tic80/regops.s
deleted file mode 100644
index f4f93523c312..000000000000
--- a/gas/testsuite/gas/tic80/regops.s
+++ /dev/null
@@ -1,237 +0,0 @@
-;; Simple register forms
-;; Those instructions which also use an immediate just use a constant.
-
-	.text
-
-	add		r3,r4,r5
-	addu		r3,r4,r5
-	and		r5,r4,r2
-	and.tt		r5,r4,r2
-	and.ff		r10,r12,r14
-	and.ft		r10,r12,r14
-	and.tf		r10,r12,r14
-	bbo		r10,r8,lo.w
-	bbo.a		r10,r8,eq.b
-	bbz		r10,r8,ls.w
-	bbz.a		r10,r8,hi.w
-	bcnd		r4,r6,lt0.b
-	bcnd.a		r4,r6,lt0.b
-	br		r6
-	br.a		r6
-	brcr		10
-	bsr		r6,r31
-	bsr.a		r6,r31
-	cmnd		r7
-	cmp		r3,r4,r5
-	dcachec		r8(r10)
-	dcachef		r8(r10)
-	dld.b		r4(r6),r8
-	dld.h		r4(r6),r8
-	dld		r4(r6),r8
-	dld.d		r4(r6),r8
-	dld.ub		r4(r6),r8
-	dld.uh		r4(r6),r8
-	dst.b		r4(r6),r8
-	dst.h		r4(r6),r8
-	dst		r4(r6),r8
-	dst.d		r4(r6),r8
-	etrap		r5
-	exts		r3,31,r5,r6
-	extu		r2,30,r5,r9
-	fadd.sss	r2,r4,r6
-	fadd.ssd	r2,r4,r6
-	fadd.sdd	r2,r4,r6
-	fadd.dsd	r2,r4,r6
-	fadd.ddd	r2,r4,r6
-	fcmp.ss		r4,r6,r8
-	fcmp.sd		r4,r6,r8
-	fcmp.ds		r4,r6,r8
-	fcmp.dd		r4,r6,r8
-	fdiv.sss	r2,r4,r6
-	fdiv.ssd	r2,r4,r6
-	fdiv.sdd	r2,r4,r6
-	fdiv.dsd	r2,r4,r6
-	fdiv.ddd	r2,r4,r6
-	fmpy.sss	r2,r4,r6
-	fmpy.ssd	r2,r4,r6
-	fmpy.sdd	r2,r4,r6
-	fmpy.dsd	r2,r4,r6
-	fmpy.ddd	r2,r4,r6
-	fmpy.iii	r2,r4,r6
-	fmpy.uuu	r2,r4,r6
-	frndm.ss	r4,r6
-	frndm.sd	r4,r6
-	frndm.si	r4,r6
-	frndm.su	r4,r6
-	frndm.ds	r2,r8
-	frndm.dd	r2,r8
-	frndm.di	r2,r8
-	frndm.du	r2,r8
-	frndm.is	r4,r6
-	frndm.id	r4,r6
-	frndm.us	r2,r8
-	frndm.ud	r2,r8
-	frndn.ss	r4,r6
-	frndn.sd	r4,r6
-	frndn.si	r4,r6
-	frndn.su	r4,r6
-	frndn.ds	r2,r8
-	frndn.dd	r2,r8
-	frndn.di	r2,r8
-	frndn.du	r2,r8
-	frndn.is	r4,r6
-	frndn.id	r4,r6
-	frndn.us	r2,r8
-	frndn.ud	r2,r8
-	frndp.ss	r4,r6
-	frndp.sd	r4,r6
-	frndp.si	r4,r6
-	frndp.su	r4,r6
-	frndp.ds	r2,r8
-	frndp.dd	r2,r8
-	frndp.di	r2,r8
-	frndp.du	r2,r8
-	frndp.is	r4,r6
-	frndp.id	r4,r6
-	frndp.us	r2,r8
-	frndp.ud	r2,r8
-	frndz.ss	r4,r6
-	frndz.sd	r4,r6
-	frndz.si	r4,r6
-	frndz.su	r4,r6
-	frndz.ds	r2,r8
-	frndz.dd	r2,r8
-	frndz.di	r2,r8
-	frndz.du	r2,r8
-	frndz.is	r4,r6
-	frndz.id	r4,r6
-	frndz.us	r2,r8
-	frndz.ud	r2,r8
-	fsqrt.ss	r6,r8
-	fsqrt.sd	r6,r8
-	fsqrt.dd	r6,r8
-	fsub.sss	r2,r4,r6
-	fsub.ssd	r2,r4,r6
-	fsub.sdd	r2,r4,r6
-	fsub.dsd	r2,r4,r6
-	fsub.ddd	r2,r4,r6
-	ins		r4,31,r8,r10
-	jsr		r4(r6),r8
-	jsr.a		r4(r6),r8
-	ld.b		r4(r6),r8
-	ld.h		r4(r6),r8
-	ld		r4(r6),r8
-	ld.d		r4(r6),r8
-	ld.ub		r4(r6),r8
-	ld.uh		r4(r6),r8
-	lmo		r7,r8
-	or		r1,r2,r3
-	or.tt		r1,r2,r3
-	or.ff		r1,r2,r3
-	or.ft		r1,r2,r3
-	or.tf		r1,r2,r3
-	rdcr		r6,r4
-	rmo		r4,r5
-	rotl		r2,31,r8,r10
-	rotr		r8,31,r2,r6
-	shl		r4,31,r2,r6
-	sl.dz		r4,12,r5,r6
-	sl.dm		r4,12,r5,r6
-	sl.ds		r4,12,r5,r6
-	sl.ez		r4,12,r5,r6
-	sl.em		r4,12,r5,r6
-	sl.es		r4,12,r5,r6
-	sl.iz		r4,12,r5,r6
-	sl.im		r4,12,r5,r6
-	sli.dz		r4,12,r5,r6
-	sli.dm		r4,12,r5,r6
-	sli.ds		r4,12,r5,r6
-	sli.ez		r4,12,r5,r6
-	sli.em		r4,12,r5,r6
-	sli.es		r4,12,r5,r6
-	sli.iz		r4,12,r5,r6
-	sli.im		r4,12,r5,r6
-	sr.dz		r4,12,r5,r6
-	sr.dm		r4,12,r5,r6
-	sr.ds		r4,12,r5,r6
-	sr.ez		r4,12,r5,r6
-	sr.em		r4,12,r5,r6
-	sr.es		r4,12,r5,r6
-	sr.iz		r4,12,r5,r6
-	sr.im		r4,12,r5,r6
-	sra		r4,32,r6,r8
-	sri.dz		r4,12,r5,r6
-	sri.dm		r4,12,r5,r6
-	sri.ds		r4,12,r5,r6
-	sri.ez		r4,12,r5,r6
-	sri.em		r4,12,r5,r6
-	sri.es		r4,12,r5,r6
-	sri.iz		r4,12,r5,r6
-	sri.im		r4,12,r5,r6
-	srl		r4,32,r6,r8
-	st.b		r4(r6),r8
-	st.h		r4(r6),r8
-	st		r4(r6),r8
-	st.d		r4(r6),r8
-	sub		r7,r8,r9
-	subu		r7,r8,r9
-	swcr		r8,r6,r4
-	trap		r10
-	vadd.ss		r2,r4,r4
-	vadd.sd		r2,r6,r6
-	vadd.dd		r2,r10,r10
-;	vld0.s		r6
-;	vld1.s		r7
-;	vld0.d		r6
-;	vld1.d		r8
-;	vmac.sss	r7,r9,0,a3
-;	vmac.sss	r7,r9,0,r10
-;	vmac.sss	r7,r9,a1,a3
-;	vmac.sss	r7,r9,a3,r10
-;	vmac.ssd	r7,r9,0,a0
-;	vmac.ssd	r7,r9,0,r10
-;	vmac.ssd	r7,r9,a1,a2
-;	vmac.ssd	r7,r9,a3,r10
-;	vmpy.ss		r1,r3,r3
-;	vmpy.sd		r5,r6,r6
-;	vmpy.dd		r2,r4,r4
-;	vmsc.sss	r7,r9,0,a0
-;	vmsc.sss	r7,r9,0,r10
-;	vmsc.sss	r7,r9,a0,a1
-;	vmsc.sss	r7,r9,a3,r10
-;	vmsc.ssd	r7,r9,0,a0
-;	vmsc.ssd	r7,r9,0,r10
-;	vmsc.ssd	r7,r9,a0,a1
-;	vmsc.ssd	r7,r9,a3,r10
-;	vmsub.ss	r6,a2,a4
-;	vmsub.sd	r6,a2,a4
-;	vmsub.ss	r4,a4,r6
-;	vmsub.sd	r4,a4,r6
-;	vrnd.si		r4,r6
-;	vrnd.si		r4,a0
-;	vrnd.su		r4,r6
-;	vrnd.su		r4,a0
-;	vrnd.ss		r4,r6
-;	vrnd.ss		r4,a0
-;	vrnd.sd		r4,r6
-;	vrnd.sd		r4,a0
-;	vrnd.di		r4,r6
-;	vrnd.di		r4,a0
-;	vrnd.du		r4,r6
-;	vrnd.du		r4,a0
-;	vrnd.ds		r4,r6
-;	vrnd.ds		r4,a0
-;	vrnd.dd		r4,r6
-;	vrnd.dd		r4,a0
-;	vrnd.is		r4,r6
-;	vrnd.id		r4,r6
-;	vrnd.us		r4,r6
-;	vrnd.ud		r4,r6
-;	vst.s		r6
-;	vst.d		r6
-;	vsub.ss		r2,r4,r6
-;	vsub.sd		r2,r4,r6
-;	vsub.dd		r2,r4,r6
-	wrcr		r6,r5
-	xnor		r5,r6,r7
-	xor		r7,r8,r9
diff --git a/gas/testsuite/gas/tic80/regops2.d b/gas/testsuite/gas/tic80/regops2.d
deleted file mode 100644
index 0b7f4a16bf5c..000000000000
--- a/gas/testsuite/gas/tic80/regops2.d
+++ /dev/null
@@ -1,68 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with :m modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	08 80 b7 02.*
-   4:	04 00 9e 02.*
-   8:	fc 7f 9e 02.*
-   c:	00 90 b7 02 78 56 34 12.*
-  14:	00 90 b7 02 ef be ad de.*
-  1c:	08 80 b7 0a.*
-  20:	04 00 9e 0a.*
-  24:	fc 7f 9e 0a.*
-  28:	00 90 b7 0a 78 56 34 12.*
-  30:	00 90 b7 0a ef be ad de.*
-  38:	04 84 b4 41.*
-  3c:	04 a4 b4 41.*
-  40:	04 c4 b4 41.*
-  44:	04 e4 b4 41.*
-  48:	00 94 b4 41 00 00 00 e0.*
-  50:	00 b4 b4 41 00 00 00 e0.*
-  58:	00 d4 b4 41 00 00 00 e0.*
-  60:	00 f4 b4 41 00 00 00 e0.*
-  68:	04 84 b5 41.*
-  6c:	04 a4 b5 41.*
-  70:	00 94 b5 41 00 00 00 e0.*
-  78:	00 b4 b5 41 00 00 00 e0.*
-  80:	04 84 b6 41.*
-  84:	04 a4 b6 41.*
-  88:	04 c4 b6 41.*
-  8c:	04 e4 b6 41.*
-  90:	00 94 b6 41 00 00 00 e0.*
-  98:	00 b4 b6 41 00 00 00 e0.*
-  a0:	00 d4 b6 41 00 00 00 e0.*
-  a8:	00 f4 b6 41 00 00 00 e0.*
-  b0:	04 80 b4 41.*
-  b4:	04 a0 b4 41.*
-  b8:	04 c0 b4 41.*
-  bc:	04 e0 b4 41.*
-  c0:	f0 7f 92 41.*
-  c4:	f0 ff 92 41.*
-  c8:	f0 7f 93 41.*
-  cc:	f0 ff 93 41.*
-  d0:	00 90 b4 41 00 00 00 e0.*
-  d8:	00 b0 b4 41 00 00 00 e0.*
-  e0:	00 d0 b4 41 00 00 00 e0.*
-  e8:	00 f0 b4 41 00 00 00 e0.*
-  f0:	04 80 b5 41.*
-  f4:	04 a0 b5 41.*
-  f8:	f0 7f 96 41.*
-  fc:	f0 ff 96 41.*
- 100:	00 90 b5 41 00 00 00 e0.*
- 108:	00 b0 b5 41 00 00 00 e0.*
- 110:	04 80 b6 41.*
- 114:	04 a0 b6 41.*
- 118:	04 c0 b6 41.*
- 11c:	04 e0 b6 41.*
- 120:	00 7f 9a 41.*
- 124:	00 ff 9a 41.*
- 128:	00 7f 9b 41.*
- 12c:	00 ff 9b 41.*
- 130:	00 90 b6 41 00 00 00 e0.*
- 138:	00 b0 b6 41 00 00 00 e0.*
- 140:	00 d0 b6 41 00 00 00 e0.*
- 148:	00 f0 b6 41 00 00 00 e0.*
diff --git a/gas/testsuite/gas/tic80/regops2.lst b/gas/testsuite/gas/tic80/regops2.lst
deleted file mode 100644
index 651fb9716f78..000000000000
--- a/gas/testsuite/gas/tic80/regops2.lst
+++ /dev/null
@@ -1,96 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:14 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops2.s                                                            PAGE    1
-
-        1 00000000   02B78008         dcachec r8(r10:m)               ; Register form (modified)
-        2 00000004   029E0004         dcachec 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-        3 00000008   029E7FFC         dcachec -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-        4 0000000C   02B79000         dcachec 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-          00000010   12345678 
-        5 00000014   02B79000         dcachec 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-          00000018   DEADBEEF 
-        6 0000001C   0AB78008         dcachef r8(r10:m)               ; Register form (modified)
-        7 00000020   0A9E0004         dcachef 4(r10:m)                ; Short Immediate form (positive offset) (modified)
-        8 00000024   0A9E7FFC         dcachef -4(r10:m)               ; Short Immediate form (negative offset) (modified)
-        9 00000028   0AB79000         dcachef 0x12345678(r10:m)       ; Long Immediate form (positive offset) (modified)
-          0000002C   12345678 
-       10 00000030   0AB79000         dcachef 0xDEADBEEF(r10:m)       ; Long Immediate form (negative offset) (modified)
-          00000034   DEADBEEF 
-       11 00000038   41B48404         dld.b   r4(r6:m),r8             ; Register form
-       12 0000003C   41B4A404         dld.h   r4(r6:m),r8             ; Register form
-       13 00000040   41B4C404         dld     r4(r6:m),r8             ; Register form
-       14 00000044   41B4E404         dld.d   r4(r6:m),r8             ; Register form
-       15 00000048   41B49400         dld.b   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000004C   E0000000 
-       16 00000050   41B4B400         dld.h   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000054   E0000000 
-       17 00000058   41B4D400         dld     0xE0000000(r6:m),r8     ; Long Immediate form
-          0000005C   E0000000 
-       18 00000060   41B4F400         dld.d   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000064   E0000000 
-       19 00000068   41B58404         dld.ub  r4(r6:m),r8             ; Register form
-       20 0000006C   41B5A404         dld.uh  r4(r6:m),r8             ; Register form
-       21 00000070   41B59400         dld.ub  0xE0000000(r6:m),r8     ; Long Immediate form
-          00000074   E0000000 
-       22 00000078   41B5B400         dld.uh  0xE0000000(r6:m),r8     ; Long Immediate form
-          0000007C   E0000000 
-       23 00000080   41B68404         dst.b   r4(r6:m),r8             ; Register form
-       24 00000084   41B6A404         dst.h   r4(r6:m),r8             ; Register form
-       25 00000088   41B6C404         dst     r4(r6:m),r8             ; Register form
-       26 0000008C   41B6E404         dst.d   r4(r6:m),r8             ; Register form
-       27 00000090   41B69400         dst.b   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000094   E0000000 
-       28 00000098   41B6B400         dst.h   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000009C   E0000000 
-       29 000000A0   41B6D400         dst     0xE0000000(r6:m),r8     ; Long Immediate form
-          000000A4   E0000000 
-       30 000000A8   41B6F400         dst.d   0xE0000000(r6:m),r8     ; Long Immediate form
-          000000AC   E0000000 
-       31 000000B0   41B48004         ld.b    r4(r6:m),r8             ; Register form
-       32 000000B4   41B4A004         ld.h    r4(r6:m),r8             ; Register form
-       33 000000B8   41B4C004         ld      r4(r6:m),r8             ; Register form
-       34 000000BC   41B4E004         ld.d    r4(r6:m),r8             ; Register form
-       35 000000C0   41927FF0         ld.b    -16(r6:m),r8            ; Short Immediate form
-       36 000000C4   4192FFF0         ld.h    -16(r6:m),r8            ; Short Immediate form
-       37 000000C8   41937FF0         ld      -16(r6:m),r8            ; Short Immediate form
-       38 000000CC   4193FFF0         ld.d    -16(r6:m),r8            ; Short Immediate form
-       39 000000D0   41B49000         ld.b    0xE0000000(r6:m),r8     ; Long Immediate form
-          000000D4   E0000000 
-       40 000000D8   41B4B000         ld.h    0xE0000000(r6:m),r8     ; Long Immediate form
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:14 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops2.s                                                            PAGE    2
-
-          000000DC   E0000000 
-       41 000000E0   41B4D000         ld      0xE0000000(r6:m),r8     ; Long Immediate form
-          000000E4   E0000000 
-       42 000000E8   41B4F000         ld.d    0xE0000000(r6:m),r8     ; Long Immediate form
-          000000EC   E0000000 
-       43 000000F0   41B58004         ld.ub   r4(r6:m),r8             ; Register form
-       44 000000F4   41B5A004         ld.uh   r4(r6:m),r8             ; Register form
-       45 000000F8   41967FF0         ld.ub   -16(r6:m),r8            ; Short Immediate form
-       46 000000FC   4196FFF0         ld.uh   -16(r6:m),r8            ; Short Immediate form
-       47 00000100   41B59000         ld.ub   0xE0000000(r6:m),r8     ; Long Immediate form
-          00000104   E0000000 
-       48 00000108   41B5B000         ld.uh   0xE0000000(r6:m),r8     ; Long Immediate form
-          0000010C   E0000000 
-       49 00000110   41B68004         st.b    r4(r6:m),r8             ; Register form
-       50 00000114   41B6A004         st.h    r4(r6:m),r8             ; Register form
-       51 00000118   41B6C004         st      r4(r6:m),r8             ; Register form
-       52 0000011C   41B6E004         st.d    r4(r6:m),r8             ; Register form
-       53 00000120   419A7F00         st.b    -256(r6:m),r8           ; Short Immediate form
-       54 00000124   419AFF00         st.h    -256(r6:m),r8           ; Short Immediate form
-       55 00000128   419B7F00         st      -256(r6:m),r8           ; Short Immediate form
-       56 0000012C   419BFF00         st.d    -256(r6:m),r8           ; Short Immediate form
-       57 00000130   41B69000         st.b    0xE0000000(r6:m),r8     ; Long Immediate form
-          00000134   E0000000 
-       58 00000138   41B6B000         st.h    0xE0000000(r6:m),r8     ; Long Immediate form
-          0000013C   E0000000 
-       59 00000140   41B6D000         st      0xE0000000(r6:m),r8     ; Long Immediate form
-          00000144   E0000000 
-       60 00000148   41B6F000         st.d    0xE0000000(r6:m),r8     ; Long Immediate form
-          0000014C   E0000000 
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops2.s b/gas/testsuite/gas/tic80/regops2.s
deleted file mode 100644
index 18755b384671..000000000000
--- a/gas/testsuite/gas/tic80/regops2.s
+++ /dev/null
@@ -1,60 +0,0 @@
-	dcachec	r8(r10:m)		; Register form (modified)
-	dcachec	4(r10:m)		; Short Immediate form (positive offset) (modified)
-	dcachec	-4(r10:m)		; Short Immediate form (negative offset) (modified)
-	dcachec	0x12345678(r10:m)	; Long Immediate form (positive offset) (modified)
-	dcachec	0xDEADBEEF(r10:m)	; Long Immediate form (negative offset) (modified)
-	dcachef	r8(r10:m)		; Register form (modified)
-	dcachef	4(r10:m)		; Short Immediate form (positive offset) (modified)
-	dcachef	-4(r10:m)		; Short Immediate form (negative offset) (modified)
-	dcachef	0x12345678(r10:m)	; Long Immediate form (positive offset) (modified)
-	dcachef	0xDEADBEEF(r10:m)	; Long Immediate form (negative offset) (modified)
-	dld.b	r4(r6:m),r8		; Register form
-	dld.h	r4(r6:m),r8		; Register form
-	dld	r4(r6:m),r8		; Register form
-	dld.d	r4(r6:m),r8		; Register form
-	dld.b	0xE0000000(r6:m),r8	; Long Immediate form
-	dld.h	0xE0000000(r6:m),r8	; Long Immediate form
-	dld	0xE0000000(r6:m),r8	; Long Immediate form
-	dld.d	0xE0000000(r6:m),r8	; Long Immediate form
-	dld.ub	r4(r6:m),r8		; Register form
-	dld.uh	r4(r6:m),r8		; Register form
-	dld.ub	0xE0000000(r6:m),r8	; Long Immediate form
-	dld.uh	0xE0000000(r6:m),r8	; Long Immediate form
-	dst.b	r4(r6:m),r8		; Register form
-	dst.h	r4(r6:m),r8		; Register form
-	dst	r4(r6:m),r8		; Register form
-	dst.d	r4(r6:m),r8		; Register form
-	dst.b	0xE0000000(r6:m),r8	; Long Immediate form
-	dst.h	0xE0000000(r6:m),r8	; Long Immediate form
-	dst	0xE0000000(r6:m),r8	; Long Immediate form
-	dst.d	0xE0000000(r6:m),r8	; Long Immediate form
-	ld.b	r4(r6:m),r8		; Register form
-	ld.h	r4(r6:m),r8		; Register form
-	ld	r4(r6:m),r8		; Register form
-	ld.d	r4(r6:m),r8		; Register form
-	ld.b	-16(r6:m),r8		; Short Immediate form
-	ld.h	-16(r6:m),r8		; Short Immediate form
-	ld	-16(r6:m),r8		; Short Immediate form
-	ld.d	-16(r6:m),r8		; Short Immediate form
-	ld.b	0xE0000000(r6:m),r8	; Long Immediate form
-	ld.h	0xE0000000(r6:m),r8	; Long Immediate form
-	ld	0xE0000000(r6:m),r8	; Long Immediate form
-	ld.d	0xE0000000(r6:m),r8	; Long Immediate form
-	ld.ub	r4(r6:m),r8		; Register form
-	ld.uh	r4(r6:m),r8		; Register form
-	ld.ub	-16(r6:m),r8		; Short Immediate form
-	ld.uh	-16(r6:m),r8		; Short Immediate form
-	ld.ub	0xE0000000(r6:m),r8	; Long Immediate form
-	ld.uh	0xE0000000(r6:m),r8	; Long Immediate form
-	st.b	r4(r6:m),r8		; Register form
-	st.h	r4(r6:m),r8		; Register form
-	st	r4(r6:m),r8		; Register form
-	st.d	r4(r6:m),r8		; Register form
-	st.b	-256(r6:m),r8		; Short Immediate form
-	st.h	-256(r6:m),r8		; Short Immediate form
-	st	-256(r6:m),r8		; Short Immediate form
-	st.d	-256(r6:m),r8		; Short Immediate form
-	st.b	0xE0000000(r6:m),r8	; Long Immediate form
-	st.h	0xE0000000(r6:m),r8	; Long Immediate form
-	st	0xE0000000(r6:m),r8	; Long Immediate form
-	st.d	0xE0000000(r6:m),r8	; Long Immediate form
diff --git a/gas/testsuite/gas/tic80/regops3.d b/gas/testsuite/gas/tic80/regops3.d
deleted file mode 100644
index 32a30124070e..000000000000
--- a/gas/testsuite/gas/tic80/regops3.d
+++ /dev/null
@@ -1,28 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with :s modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	04 0c b4 41.*
-   4:	04 2c b4 41.*
-   8:	04 4c b4 41.*
-   c:	04 6c b4 41.*
-  10:	04 0c b5 41.*
-  14:	04 2c b5 41.*
-  18:	04 0c b6 41.*
-  1c:	04 2c b6 41.*
-  20:	04 4c b6 41.*
-  24:	04 6c b6 41.*
-  28:	04 08 b4 41.*
-  2c:	04 28 b4 41.*
-  30:	04 48 b4 41.*
-  34:	04 68 b4 41.*
-  38:	04 08 b5 41.*
-  3c:	04 28 b5 41.*
-  40:	04 08 b6 41.*
-  44:	04 28 b6 41.*
-  48:	04 48 b6 41.*
-  4c:	04 68 b6 41.*
diff --git a/gas/testsuite/gas/tic80/regops3.lst b/gas/testsuite/gas/tic80/regops3.lst
deleted file mode 100644
index d65803f1a676..000000000000
--- a/gas/testsuite/gas/tic80/regops3.lst
+++ /dev/null
@@ -1,27 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:19 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops3.s                                                            PAGE    1
-
-        1 00000000   41B40C04         dld.b   r4:s(r6),r8             ; Register form
-        2 00000004   41B42C04         dld.h   r4:s(r6),r8             ; Register form
-        3 00000008   41B44C04         dld     r4:s(r6),r8             ; Register form
-        4 0000000C   41B46C04         dld.d   r4:s(r6),r8             ; Register form
-        5 00000010   41B50C04         dld.ub  r4:s(r6),r8             ; Register form
-        6 00000014   41B52C04         dld.uh  r4:s(r6),r8             ; Register form
-        7 00000018   41B60C04         dst.b   r4:s(r6),r8             ; Register form
-        8 0000001C   41B62C04         dst.h   r4:s(r6),r8             ; Register form
-        9 00000020   41B64C04         dst     r4:s(r6),r8             ; Register form
-       10 00000024   41B66C04         dst.d   r4:s(r6),r8             ; Register form
-       11 00000028   41B40804         ld.b    r4:s(r6),r8             ; Register form
-       12 0000002C   41B42804         ld.h    r4:s(r6),r8             ; Register form
-       13 00000030   41B44804         ld      r4:s(r6),r8             ; Register form
-       14 00000034   41B46804         ld.d    r4:s(r6),r8             ; Register form
-       15 00000038   41B50804         ld.ub   r4:s(r6),r8             ; Register form
-       16 0000003C   41B52804         ld.uh   r4:s(r6),r8             ; Register form
-       17 00000040   41B60804         st.b    r4:s(r6),r8             ; Register form
-       18 00000044   41B62804         st.h    r4:s(r6),r8             ; Register form
-       19 00000048   41B64804         st      r4:s(r6),r8             ; Register form
-       20 0000004C   41B66804         st.d    r4:s(r6),r8             ; Register form
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops3.s b/gas/testsuite/gas/tic80/regops3.s
deleted file mode 100644
index 5ed87d5109ca..000000000000
--- a/gas/testsuite/gas/tic80/regops3.s
+++ /dev/null
@@ -1,20 +0,0 @@
-	dld.b	r4:s(r6),r8		; Register form
-	dld.h	r4:s(r6),r8		; Register form
-	dld	r4:s(r6),r8		; Register form
-	dld.d	r4:s(r6),r8		; Register form
-	dld.ub	r4:s(r6),r8		; Register form
-	dld.uh	r4:s(r6),r8		; Register form
-	dst.b	r4:s(r6),r8		; Register form
-	dst.h	r4:s(r6),r8		; Register form
-	dst	r4:s(r6),r8		; Register form
-	dst.d	r4:s(r6),r8		; Register form
-	ld.b	r4:s(r6),r8		; Register form
-	ld.h	r4:s(r6),r8		; Register form
-	ld	r4:s(r6),r8		; Register form
-	ld.d	r4:s(r6),r8		; Register form
-	ld.ub	r4:s(r6),r8		; Register form
-	ld.uh	r4:s(r6),r8		; Register form
-	st.b	r4:s(r6),r8		; Register form
-	st.h	r4:s(r6),r8		; Register form
-	st	r4:s(r6),r8		; Register form
-	st.d	r4:s(r6),r8		; Register form
diff --git a/gas/testsuite/gas/tic80/regops4.d b/gas/testsuite/gas/tic80/regops4.d
deleted file mode 100644
index 33607c969240..000000000000
--- a/gas/testsuite/gas/tic80/regops4.d
+++ /dev/null
@@ -1,28 +0,0 @@
-#objdump: -d
-#name: TIc80 register operands with both :m and :s modifier
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <.text>:
-   0:	04 8c b4 41.*
-   4:	04 ac b4 41.*
-   8:	04 cc b4 41.*
-   c:	04 ec b4 41.*
-  10:	04 8c b5 41.*
-  14:	04 ac b5 41.*
-  18:	04 8c b6 41.*
-  1c:	04 ac b6 41.*
-  20:	04 cc b6 41.*
-  24:	04 ec b6 41.*
-  28:	04 88 b4 41.*
-  2c:	04 a8 b4 41.*
-  30:	04 c8 b4 41.*
-  34:	04 e8 b4 41.*
-  38:	04 88 b5 41.*
-  3c:	04 a8 b5 41.*
-  40:	04 88 b6 41.*
-  44:	04 a8 b6 41.*
-  48:	04 c8 b6 41.*
-  4c:	04 e8 b6 41.*
diff --git a/gas/testsuite/gas/tic80/regops4.lst b/gas/testsuite/gas/tic80/regops4.lst
deleted file mode 100644
index 3af3c9af499c..000000000000
--- a/gas/testsuite/gas/tic80/regops4.lst
+++ /dev/null
@@ -1,27 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Wed Feb 26 14:32:25 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-regops4.s                                                            PAGE    1
-
-        1 00000000   41B48C04         dld.b   r4:s(r6:m),r8           ; Register form
-        2 00000004   41B4AC04         dld.h   r4:s(r6:m),r8           ; Register form
-        3 00000008   41B4CC04         dld     r4:s(r6:m),r8           ; Register form
-        4 0000000C   41B4EC04         dld.d   r4:s(r6:m),r8           ; Register form
-        5 00000010   41B58C04         dld.ub  r4:s(r6:m),r8           ; Register form
-        6 00000014   41B5AC04         dld.uh  r4:s(r6:m),r8           ; Register form
-        7 00000018   41B68C04         dst.b   r4:s(r6:m),r8           ; Register form
-        8 0000001C   41B6AC04         dst.h   r4:s(r6:m),r8           ; Register form
-        9 00000020   41B6CC04         dst     r4:s(r6:m),r8           ; Register form
-       10 00000024   41B6EC04         dst.d   r4:s(r6:m),r8           ; Register form
-       11 00000028   41B48804         ld.b    r4:s(r6:m),r8           ; Register form
-       12 0000002C   41B4A804         ld.h    r4:s(r6:m),r8           ; Register form
-       13 00000030   41B4C804         ld      r4:s(r6:m),r8           ; Register form
-       14 00000034   41B4E804         ld.d    r4:s(r6:m),r8           ; Register form
-       15 00000038   41B58804         ld.ub   r4:s(r6:m),r8           ; Register form
-       16 0000003C   41B5A804         ld.uh   r4:s(r6:m),r8           ; Register form
-       17 00000040   41B68804         st.b    r4:s(r6:m),r8           ; Register form
-       18 00000044   41B6A804         st.h    r4:s(r6:m),r8           ; Register form
-       19 00000048   41B6C804         st      r4:s(r6:m),r8           ; Register form
-       20 0000004C   41B6E804         st.d    r4:s(r6:m),r8           ; Register form
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/regops4.s b/gas/testsuite/gas/tic80/regops4.s
deleted file mode 100644
index 5ba77e9138e0..000000000000
--- a/gas/testsuite/gas/tic80/regops4.s
+++ /dev/null
@@ -1,20 +0,0 @@
-	dld.b	r4:s(r6:m),r8		; Register form
-	dld.h	r4:s(r6:m),r8		; Register form
-	dld	r4:s(r6:m),r8		; Register form
-	dld.d	r4:s(r6:m),r8		; Register form
-	dld.ub	r4:s(r6:m),r8		; Register form
-	dld.uh	r4:s(r6:m),r8		; Register form
-	dst.b	r4:s(r6:m),r8		; Register form
-	dst.h	r4:s(r6:m),r8		; Register form
-	dst	r4:s(r6:m),r8		; Register form
-	dst.d	r4:s(r6:m),r8		; Register form
-	ld.b	r4:s(r6:m),r8		; Register form
-	ld.h	r4:s(r6:m),r8		; Register form
-	ld	r4:s(r6:m),r8		; Register form
-	ld.d	r4:s(r6:m),r8		; Register form
-	ld.ub	r4:s(r6:m),r8		; Register form
-	ld.uh	r4:s(r6:m),r8		; Register form
-	st.b	r4:s(r6:m),r8		; Register form
-	st.h	r4:s(r6:m),r8		; Register form
-	st	r4:s(r6:m),r8		; Register form
-	st.d	r4:s(r6:m),r8		; Register form
diff --git a/gas/testsuite/gas/tic80/relocs1.c b/gas/testsuite/gas/tic80/relocs1.c
deleted file mode 100644
index 6af04b1100a0..000000000000
--- a/gas/testsuite/gas/tic80/relocs1.c
+++ /dev/null
@@ -1,28 +0,0 @@
-extern int xfunc (int y);
-
-static int sfunc (int y)
-{
-  xfunc (y);
-}
-
-int gfunc (int y)
-{
-  sfunc (y);
-}
-
-int branches (int y)
-{
-  int z;
-
-  for (z = y; z < y + 10; z++)
-    {
-      if (z & 0x1)
-	{
-	  gfunc (z);
-	}
-      else
-	{
-	  xfunc (z);
-	}
-    }
-}
diff --git a/gas/testsuite/gas/tic80/relocs1.d b/gas/testsuite/gas/tic80/relocs1.d
deleted file mode 100644
index 14ca6c9b1243..000000000000
--- a/gas/testsuite/gas/tic80/relocs1.d
+++ /dev/null
@@ -1,56 +0,0 @@
-#objdump: -d
-#name: TIc80 simple relocs, global/local funcs & branches (code)
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <_sfunc>:
-   0:	f0 ff 6c 08.*
-   4:	0c 00 59 f8.*
-   8:	00 00 59 10.*
-   c:	00 90 38 f8 00 00 00 00.*
-  14:	00 00 51 10.*
-  18:	0c 00 51 f8.*
-  1c:	1f 80 38 00.*
-  20:	10 80 6c 08.*
-
-00000024 <_gfunc>:
-  24:	f0 ff 6c 08.*
-  28:	0c 00 59 f8.*
-  2c:	00 00 59 10.*
-  30:	00 90 38 f8 00 00 00 00.*
-  38:	00 00 51 10.*
-  3c:	0c 00 51 f8.*
-  40:	1f 80 38 00.*
-  44:	10 80 6c 08.*
-
-00000048 <_branches>:
-  48:	f0 ff 6c 08.*
-  4c:	0c 00 59 f8.*
-  50:	00 00 59 10.*
-  54:	00 00 51 10.*
-  58:	04 00 59 10.*
-  5c:	00 00 51 10.*
-  60:	04 00 51 18.*
-  64:	0a 80 ac 10.*
-  68:	03 00 ba 10.*
-  6c:	12 80 a5 30.*
-  70:	04 00 51 10.*
-  74:	05 80 a4 f8.*
-  78:	00 90 38 f8 24 00 00 00.*
-  80:	04 00 51 10.*
-  84:	04 80 24 00.*
-  88:	00 90 38 f8 00 00 00 00.*
-  90:	04 00 51 10.*
-  94:	04 00 51 10.*
-  98:	01 80 ac 10.*
-  9c:	04 00 59 10.*
-  a0:	00 00 51 18.*
-  a4:	04 00 51 10.*
-  a8:	0a 80 ec 18.*
-  ac:	02 00 fa 10.*
-  b0:	f0 ff a5 38.*
-  b4:	0c 00 51 f8.*
-  b8:	1f 80 38 00.*
-  bc:	10 80 6c 08.*
diff --git a/gas/testsuite/gas/tic80/relocs1.lst b/gas/testsuite/gas/tic80/relocs1.lst
deleted file mode 100644
index 9faeb1aab4fa..000000000000
--- a/gas/testsuite/gas/tic80/relocs1.lst
+++ /dev/null
@@ -1,80 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 13:19:28 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs1.s                                                            PAGE    1
-
-        1                     ;; This is the hand hacked output of the TI C compiler for a simple
-        2                     ;; test program that contains local/global functions, local/global
-        3                     ;; function calls, and an "if" and "for" statement.
-        4                     
-        5                             .global _xfunc
-        6                     
-        7 00000000            _sfunc:
-        8 00000000   086CFFF0          addu      -16,r1,r1
-        9 00000004   F859000C          st        12(r1),r31
-       10 00000008   10590000          st        0(r1),r2
-       11 0000000C   F8389000          jsr       _xfunc(r0),r31
-          00000010   00000000 
-       12 00000014   10510000          ld        0(r1),r2
-       13 00000018   F851000C          ld        12(r1),r31
-       14 0000001C   0038801F          jsr       r31(r0),r0
-       15 00000020   086C8010          addu      16,r1,r1
-       16                     
-       17                             .global _gfunc
-       18                     
-       19 00000024            _gfunc:
-       20 00000024   086CFFF0          addu      -16,r1,r1
-       21 00000028   F859000C          st        12(r1),r31
-       22 0000002C   10590000          st        0(r1),r2
-       23 00000030   F8389000          jsr       _sfunc(r0),r31
-          00000034   00000000 
-       24 00000038   10510000          ld        0(r1),r2
-       25 0000003C   F851000C          ld        12(r1),r31
-       26 00000040   0038801F          jsr       r31(r0),r0
-       27 00000044   086C8010          addu      16,r1,r1
-       28                     
-       29                     
-       30                             .global _branches
-       31                     
-       32 00000048            _branches:
-       33 00000048   086CFFF0          addu      -16,r1,r1
-       34 0000004C   F859000C          st        12(r1),r31
-       35 00000050   10590000          st        0(r1),r2
-       36 00000054   10510000          ld        0(r1),r2
-       37 00000058   10590004          st        4(r1),r2
-       38 0000005C   10510000          ld        0(r1),r2
-       39 00000060   18510004          ld        4(r1),r3
-       40 00000064   10AC800A          addu      10,r2,r2
-       41 00000068   10BA0003          cmp       r3,r2,r2
-       42 0000006C   30A58012          bbo.a     L12,r2,ge.w
-       43 00000070            L8:
-       44 00000070   10510004          ld        4(r1),r2
-       45 00000074   F8A48005          bbz.a     L10,r2,0
-       46 00000078   F8389000          jsr       _gfunc(r0),r31
-          0000007C   00000024 
-       47 00000080   10510004          ld        4(r1),r2
-       48 00000084   00248004          br.a      L11
-       49 00000088            L10:
-       50 00000088   F8389000          jsr       _xfunc(r0),r31
-          0000008C   00000000 
-       51 00000090   10510004          ld        4(r1),r2
-MVP MP Macro Assembler     Version 1.13     Sat Feb 22 13:19:28 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs1.s                                                            PAGE    2
-
-       52 00000094            L11:
-       53 00000094   10510004          ld        4(r1),r2
-       54 00000098   10AC8001          addu      1,r2,r2
-       55 0000009C   10590004          st        4(r1),r2
-       56 000000A0   18510000          ld        0(r1),r3
-       57 000000A4   10510004          ld        4(r1),r2
-       58 000000A8   18EC800A          addu      10,r3,r3
-       59 000000AC   10FA0002          cmp       r2,r3,r2
-       60 000000B0   38A5FFF0          bbo.a     L8,r2,lt.w
-       61 000000B4            L12:
-       62 000000B4   F851000C          ld        12(r1),r31
-       63 000000B8   0038801F          jsr       r31(r0),r0
-       64 000000BC   086C8010          addu      16,r1,r1
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/relocs1.s b/gas/testsuite/gas/tic80/relocs1.s
deleted file mode 100644
index 149e3956ed23..000000000000
--- a/gas/testsuite/gas/tic80/relocs1.s
+++ /dev/null
@@ -1,66 +0,0 @@
-;; This is the hand hacked output of the TI C compiler for a simple
-;; test program that contains local/global functions, local/global
-;; function calls, and an "if" and "for" statement.
-
-	.file	   "relocs1.s"
-
-	.global	_xfunc
-
-_sfunc:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         jsr       _xfunc(r0),r31
-         ld        0(r1),r2
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
-
-	.global	_gfunc
-
-_gfunc:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         jsr       _sfunc(r0),r31
-         ld        0(r1),r2
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
-
-
-	.global	_branches
-
-_branches:
-         addu      -16,r1,r1
-         st        12(r1),r31
-         st        0(r1),r2
-         ld        0(r1),r2
-         st        4(r1),r2
-         ld        0(r1),r2
-         ld        4(r1),r3
-         addu      10,r2,r2
-         cmp       r3,r2,r2
-         bbo.a     L12,r2,ge.w
-L8:
-         ld        4(r1),r2
-         bbz.a     L10,r2,0
-         jsr       _gfunc(r0),r31
-         ld        4(r1),r2
-         br.a      L11
-L10:
-         jsr       _xfunc(r0),r31
-         ld        4(r1),r2
-L11:
-         ld        4(r1),r2
-         addu      1,r2,r2
-         st        4(r1),r2
-         ld        0(r1),r3
-         ld        4(r1),r2
-         addu      10,r3,r3
-         cmp       r2,r3,r2
-         bbo.a     L8,r2,lt.w
-L12:
-         ld        12(r1),r31
-         jsr       r31(r0),r0
-         addu      16,r1,r1
diff --git a/gas/testsuite/gas/tic80/relocs1b.d b/gas/testsuite/gas/tic80/relocs1b.d
deleted file mode 100644
index 4eb31611d2f8..000000000000
--- a/gas/testsuite/gas/tic80/relocs1b.d
+++ /dev/null
@@ -1,12 +0,0 @@
-#objdump: -r
-#source: relocs1.s
-#name: TIc80 simple relocs, global/local funcs & branches (relocs)
-
-.*: +file format .*tic80.*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET   TYPE              VALUE 
-00000010 32                _xfunc
-00000034 32                .text
-0000007c 32                .text
-0000008c 32                _xfunc
diff --git a/gas/testsuite/gas/tic80/relocs2.c b/gas/testsuite/gas/tic80/relocs2.c
deleted file mode 100644
index 3f1120c21bd1..000000000000
--- a/gas/testsuite/gas/tic80/relocs2.c
+++ /dev/null
@@ -1,41 +0,0 @@
-extern char x_char;
-extern short x_short;
-static int x_int;
-extern long x_long;
-extern float x_float;
-extern double x_double;
-extern char *x_char_p;
-
-static char s_char;
-static short s_short;
-static int s_int;
-static long s_long;
-static float s_float;
-static double s_double;
-static char *s_char_p;
-
-char g_char;
-short g_short;
-int g_int;
-long g_long;
-float g_float;
-double g_double;
-char *g_char_p;
-
-main ()
-{
-  x_char = s_char;
-  g_char = x_char;
-  x_short = s_short;
-  g_short = x_short;
-  x_int = s_int;
-  g_int = x_int;
-  x_long = s_long;
-  g_long = x_long;
-  x_float = s_float;
-  g_float = x_float;
-  x_double = s_double;
-  g_double = x_double;
-  x_char_p = s_char_p;
-  g_char_p = x_char_p;
-}
diff --git a/gas/testsuite/gas/tic80/relocs2.d b/gas/testsuite/gas/tic80/relocs2.d
deleted file mode 100644
index cf3e87ded6bd..000000000000
--- a/gas/testsuite/gas/tic80/relocs2.d
+++ /dev/null
@@ -1,37 +0,0 @@
-#objdump: -d
-#name: TIc80 simple relocs, static and global variables (code)
-
-.*: +file format .*tic80.*
-
-Disassembly of section .text:
-
-00000000 <_main>:
-   0:	00 10 34 10 24 02 00 00.*
-   8:	00 10 36 10 00 00 00 00.*
-  10:	00 10 34 10 00 00 00 00.*
-  18:	00 10 36 10 04 02 00 00.*
-  20:	00 30 34 10 24 03 00 00.*
-  28:	00 30 36 10 00 00 00 00.*
-  30:	00 30 34 10 00 00 00 00.*
-  38:	00 30 36 10 04 03 00 00.*
-  40:	00 50 34 10 34 02 00 00.*
-  48:	00 50 36 10 34 03 00 00.*
-  50:	00 50 34 10 34 03 00 00.*
-  58:	00 50 36 10 14 02 00 00.*
-  60:	00 50 34 10 f4 01 00 00.*
-  68:	00 50 36 10 00 00 00 00.*
-  70:	00 50 34 10 00 00 00 00.*
-  78:	00 50 36 10 f4 00 00 00.*
-  80:	00 50 34 10 f4 02 00 00.*
-  88:	00 50 36 10 00 00 00 00.*
-  90:	00 50 34 10 00 00 00 00.*
-  98:	00 50 36 10 14 03 00 00.*
-  a0:	00 70 34 10 e4 01 00 00.*
-  a8:	00 70 36 10 00 00 00 00.*
-  b0:	00 70 34 10 00 00 00 00.*
-  b8:	00 70 36 10 e4 02 00 00.*
-  c0:	00 50 34 10 44 03 00 00.*
-  c8:	00 50 36 10 00 00 00 00.*
-  d0:	00 50 34 10 00 00 00 00.*
-  d8:	00 50 36 10 e4 00 00 00.*
-  e0:	1f a0 38 00.*
diff --git a/gas/testsuite/gas/tic80/relocs2.lst b/gas/testsuite/gas/tic80/relocs2.lst
deleted file mode 100644
index 0690a8ce843c..000000000000
--- a/gas/testsuite/gas/tic80/relocs2.lst
+++ /dev/null
@@ -1,112 +0,0 @@
-MVP MP Macro Assembler     Version 1.13     Sun Feb 23 12:16:32 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs2.s                                                            PAGE    1
-
-        1                     ;; This is the hand hacked output of the TI C compiler for a simple
-        2                     ;; test program that contains static, global, and extern data variables.
-        3                     
-        4                             .file   "relocs2.s"
-        5                             .global _x_char
-        6                             .global _x_short
-        7                             .global _x_long
-        8                             .global _x_float
-        9                             .global _x_double
-       10                             .global _x_char_p
-       11                             .global _g_char
-       12                             .global _g_short
-       13                             .global _g_int
-       14                             .global _g_long
-       15                             .global _g_float
-       16                             .global _g_double
-       17                             .global _g_char_p
-       18                             .global _main
-       19                     
-       20 00000000            _main:
-       21 00000000   10341000          ld.b      _s_char+0(r0),r2
-          00000004   0000001C 
-       22 00000008   10361000          st.b      _x_char+0(r0),r2
-          0000000C   00000000 
-       23 00000010   10341000          ld.b      _x_char+0(r0),r2
-          00000014   00000000 
-       24 00000018   10361000          st.b      _g_char+0(r0),r2
-          0000001C   00000014 
-       25 00000020   10343000          ld.h      _s_short+0(r0),r2
-          00000024   0000003C 
-       26 00000028   10363000          st.h      _x_short+0(r0),r2
-          0000002C   00000000 
-       27 00000030   10343000          ld.h      _x_short+0(r0),r2
-          00000034   00000000 
-       28 00000038   10363000          st.h      _g_short+0(r0),r2
-          0000003C   00000034 
-       29 00000040   10345000          ld        _s_int+0(r0),r2
-          00000044   00000020 
-       30 00000048   10365000          st        _x_int+0(r0),r2
-          0000004C   00000040 
-       31 00000050   10345000          ld        _x_int+0(r0),r2
-          00000054   00000040 
-       32 00000058   10365000          st        _g_int+0(r0),r2
-          0000005C   00000018 
-       33 00000060   10345000          ld        _s_long+0(r0),r2
-          00000064   00000010 
-       34 00000068   10365000          st        _x_long+0(r0),r2
-          0000006C   00000000 
-       35 00000070   10345000          ld        _x_long+0(r0),r2
-          00000074   00000000 
-       36 00000078   10365000          st        _g_long+0(r0),r2
-          0000007C   00000004 
-       37 00000080   10345000          ld        _s_float+0(r0),r2
-          00000084   00000030 
-       38 00000088   10365000          st        _x_float+0(r0),r2
-MVP MP Macro Assembler     Version 1.13     Sun Feb 23 12:16:32 1997
-Copyright (c) 1993-1995    Texas Instruments Incorporated 
-
-relocs2.s                                                            PAGE    2
-
-          0000008C   00000000 
-       39 00000090   10345000          ld        _x_float+0(r0),r2
-          00000094   00000000 
-       40 00000098   10365000          st        _g_float+0(r0),r2
-          0000009C   00000038 
-       41 000000A0   10347000          ld.d      _s_double+0(r0),r2
-          000000A4   00000008 
-       42 000000A8   10367000          st.d      _x_double+0(r0),r2
-          000000AC   00000000 
-       43 000000B0   10347000          ld.d      _x_double+0(r0),r2
-          000000B4   00000000 
-       44 000000B8   10367000          st.d      _g_double+0(r0),r2
-          000000BC   00000028 
-       45 000000C0   10345000          ld        _s_char_p+0(r0),r2
-          000000C4   00000044 
-       46 000000C8   10365000          st        _x_char_p+0(r0),r2
-          000000CC   00000000 
-       47 000000D0   10345000          ld        _x_char_p+0(r0),r2
-          000000D4   00000000 
-       48 000000D8   10365000          st        _g_char_p+0(r0),r2
-          000000DC   00000000 
-       49 000000E0   0038A01F          jsr.a     r31(r0),r0
-       50                     
-       51                             .global _g_char_p
-       52 00000000                    .bss    _g_char_p,4,4
-       53                             .global _g_long
-       54 00000004                    .bss    _g_long,4,4
-       55 00000008                    .bss    _s_double,8,8
-       56 00000010                    .bss    _s_long,4,4
-       57                             .global _g_char
-       58 00000014                    .bss    _g_char,1,4
-       59                             .global _g_int
-       60 00000018                    .bss    _g_int,4,4
-       61 0000001C                    .bss    _s_char,1,4
-       62 00000020                    .bss    _s_int,4,4
-       63                             .global _g_double
-       64 00000028                    .bss    _g_double,8,8
-       65 00000030                    .bss    _s_float,4,4
-       66                             .global _g_short
-       67 00000034                    .bss    _g_short,2,4
-       68                             .global _g_float
-       69 00000038                    .bss    _g_float,4,4
-       70 0000003C                    .bss    _s_short,2,4
-       71 00000040                    .bss    _x_int,4,4
-       72 00000044                    .bss    _s_char_p,4,4
-
- No Errors,  No Warnings
diff --git a/gas/testsuite/gas/tic80/relocs2.s b/gas/testsuite/gas/tic80/relocs2.s
deleted file mode 100644
index e4257df86566..000000000000
--- a/gas/testsuite/gas/tic80/relocs2.s
+++ /dev/null
@@ -1,72 +0,0 @@
-;; This is the hand hacked output of the TI C compiler for a simple
-;; test program that contains static, global, and extern data variables.
-
-	.file	"relocs2.s"
-	.global	_x_char
-	.global	_x_short
-	.global	_x_long
-	.global	_x_float
-	.global	_x_double
-	.global	_x_char_p
-	.global	_g_char
-	.global	_g_short
-	.global	_g_int
-	.global	_g_long
-	.global	_g_float
-	.global	_g_double
-	.global	_g_char_p
-	.global	_main
-
-_main:
-         ld.b      _s_char+0(r0),r2
-         st.b      _x_char+0(r0),r2
-         ld.b      _x_char+0(r0),r2
-         st.b      _g_char+0(r0),r2
-         ld.h      _s_short+0(r0),r2
-         st.h      _x_short+0(r0),r2
-         ld.h      _x_short+0(r0),r2
-         st.h      _g_short+0(r0),r2
-         ld        _s_int+0(r0),r2
-         st        _x_int+0(r0),r2
-         ld        _x_int+0(r0),r2
-         st        _g_int+0(r0),r2
-         ld        _s_long+0(r0),r2
-         st        _x_long+0(r0),r2
-         ld        _x_long+0(r0),r2
-         st        _g_long+0(r0),r2
-         ld        _s_float+0(r0),r2
-         st        _x_float+0(r0),r2
-         ld        _x_float+0(r0),r2
-         st        _g_float+0(r0),r2
-         ld.d      _s_double+0(r0),r2
-         st.d      _x_double+0(r0),r2
-         ld.d      _x_double+0(r0),r2
-         st.d      _g_double+0(r0),r2
-         ld        _s_char_p+0(r0),r2
-         st        _x_char_p+0(r0),r2
-         ld        _x_char_p+0(r0),r2
-         st        _g_char_p+0(r0),r2
-         jsr.a     r31(r0),r0
-
-	.global	_g_char_p
-	.bss	_g_char_p,4,4
-	.global	_g_long
-	.bss	_g_long,4,4
-	.bss	_s_double,8,8
-	.bss	_s_long,4,4
-	.global	_g_char
-	.bss	_g_char,1,4
-	.global	_g_int
-	.bss	_g_int,4,4
-	.bss	_s_char,1,4
-	.bss	_s_int,4,4
-	.global	_g_double
-	.bss	_g_double,8,8
-	.bss	_s_float,4,4
-	.global	_g_short
-	.bss	_g_short,2,4
-	.global	_g_float
-	.bss	_g_float,4,4
-	.bss	_s_short,2,4
-	.bss	_x_int,4,4
-	.bss	_s_char_p,4,4
diff --git a/gas/testsuite/gas/tic80/relocs2b.d b/gas/testsuite/gas/tic80/relocs2b.d
deleted file mode 100644
index 604f99d90a4f..000000000000
--- a/gas/testsuite/gas/tic80/relocs2b.d
+++ /dev/null
@@ -1,38 +0,0 @@
-#objdump: -r
-#source: relocs2.s
-#name: TIc80 simple relocs, static and global variables (relocs)
-
-.*: +file format .*tic80.*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET   TYPE              VALUE 
-00000004 32                .bss\+0xffffff1c
-0000000c 32                _x_char
-00000014 32                _x_char
-0000001c 32                .bss\+0xffffff1c
-00000024 32                .bss\+0xffffff1c
-0000002c 32                _x_short
-00000034 32                _x_short
-0000003c 32                .bss\+0xffffff1c
-00000044 32                .bss\+0xffffff1c
-0000004c 32                .bss\+0xffffff1c
-00000054 32                .bss\+0xffffff1c
-0000005c 32                .bss\+0xffffff1c
-00000064 32                .bss\+0xffffff1c
-0000006c 32                _x_long
-00000074 32                _x_long
-0000007c 32                .bss\+0xffffff1c
-00000084 32                .bss\+0xffffff1c
-0000008c 32                _x_float
-00000094 32                _x_float
-0000009c 32                .bss\+0xffffff1c
-000000a4 32                .bss\+0xffffff1c
-000000ac 32                _x_double
-000000b4 32                _x_double
-000000bc 32                .bss\+0xffffff1c
-000000c4 32                .bss\+0xffffff1c
-000000cc 32                _x_char_p
-000000d4 32                _x_char_p
-000000dc 32                .bss\+0xffffff1c
-
-
diff --git a/gas/testsuite/gas/tic80/tic80.exp b/gas/testsuite/gas/tic80/tic80.exp
deleted file mode 100644
index 49c4633996f7..000000000000
--- a/gas/testsuite/gas/tic80/tic80.exp
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# TI TMS320C80 tests.
-#
-if [istarget tic80*-*-*] then {
-
-    run_dump_test "regops"
-    run_dump_test "regops2"
-    run_dump_test "regops3"
-    run_dump_test "regops4"
-    run_dump_test "cregops"
-    run_dump_test "float"
-    run_dump_test "endmask"
-    run_dump_test "bitnum"
-    run_dump_test "ccode"
-    run_dump_test "add"
-    run_dump_test "relocs1"
-    run_dump_test "relocs1b"
-    run_dump_test "relocs2"
-    run_dump_test "relocs2b"
-    run_dump_test "align"
-}
diff --git a/gas/testsuite/gas/v850/basic.exp b/gas/testsuite/gas/v850/basic.exp
index e3b0713bae82..cd03c2cc9a10 100644
--- a/gas/testsuite/gas/v850/basic.exp
+++ b/gas/testsuite/gas/v850/basic.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1996, 2003 Free Software Foundation, Inc.
+# Copyright (C) 1996, 2002, 2003, 2004 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -12,7 +12,7 @@
 # 
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -436,4 +436,5 @@ if [istarget v850*-*-*] then {
 
     gas_test_error "range.s" "-mwarn-signed-overflow" "Check for range error on byte load/store"
     run_dump_test "v850e1"
+    run_dump_test "split-lo16"
 }
diff --git a/gas/testsuite/gas/v850/split-lo16.d b/gas/testsuite/gas/v850/split-lo16.d
new file mode 100644
index 000000000000..5ed195cb087e
--- /dev/null
+++ b/gas/testsuite/gas/v850/split-lo16.d
@@ -0,0 +1,18 @@
+#objdump: -dr
+#name: V850E split LO16 tests
+#as: -mv850e
+#...
+00000000 <.*>:
+   0:	40 0e 00 00 	movhi	0, r0, r1
+			2: R_V850_HI16_S	foo
+   4:	01 16 00 00 	addi	0, r1, r2
+			6: R_V850_LO16	foo
+   8:	01 17 00 00 	ld\.b	0\[r1\],r2
+			a: R_V850_LO16	foo
+   c:	81 17 01 00 	ld\.bu	0\[r1\],r2
+			c: R_V850_LO16_SPLIT_OFFSET	foo
+  10:	a1 17 45 23 	ld\.bu	9029\[r1\],r2
+  14:	81 17 57 34 	ld\.bu	13398\[r1\],r2
+  18:	20 57 01 00 	ld.w	0\[r0\],r10
+  1c:	20 57 79 56 	ld.w	22136\[r0\],r10
+#pass
diff --git a/gas/testsuite/gas/v850/split-lo16.s b/gas/testsuite/gas/v850/split-lo16.s
new file mode 100644
index 000000000000..bb6fb666c07d
--- /dev/null
+++ b/gas/testsuite/gas/v850/split-lo16.s
@@ -0,0 +1,10 @@
+	movhi	hi(foo),r0,r1
+	addi	lo(foo),r1,r2
+	ld.b	lo(foo),r1,r2
+	ld.bu	lo(foo),r1,r2
+
+	ld.bu	lo(0x12345),r1,r2
+	ld.bu	lo(0x123456),r1,r2
+
+	ld.w lo(0)[r0], r10
+	ld.w lo(0x12345678)[r0], r10
diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d
index 9fb689b5d3c7..3f176d13c3bd 100644
--- a/gas/testsuite/gas/v850/v850e1.d
+++ b/gas/testsuite/gas/v850/v850e1.d
@@ -11,7 +11,7 @@ Disassembly of section .text:
 0x0+04 e0 1f 40 23 [ 	]*bsw	sp, gp
 0x0+08 05 02  [ 	]*callt	5
 0x0+0a e8 3f e4 00 [ 	]*clr1	r7, r8
-0x0+0e f6 17 14 1b [ 	]*cmov	nz, -10, r2, sp
+0x0+0e f6 17 14 1b [ 	]*cmov	nz, 22, r2, sp
 0x0+12 e1 17 34 1b [ 	]*cmov	nz, r1, r2, sp
 0x0+16 e0 07 44 01 [ 	]*ctret	
 0x0+1a e0 07 46 01 [ 	]*dbret	
diff --git a/gas/testsuite/gas/vax/elf-rel.d b/gas/testsuite/gas/vax/elf-rel.d
index 88e8f5ca455e..7e2df4054760 100644
--- a/gas/testsuite/gas/vax/elf-rel.d
+++ b/gas/testsuite/gas/vax/elf-rel.d
@@ -1,3 +1,4 @@
+#as: -k
 #objdump: -sr
 #name: VAX ELF relocations
 
diff --git a/gas/testsuite/gas/vax/flonum.d b/gas/testsuite/gas/vax/flonum.d
new file mode 100644
index 000000000000..38d20cda0230
--- /dev/null
+++ b/gas/testsuite/gas/vax/flonum.d
@@ -0,0 +1,12 @@
+#objdump: -sw
+#name: VAX flonum test
+
+.*:     file format .*
+
+Contents of section .data:
+ 0000 fc3e5bd3 9e401006 1641751f 5d41e23b  .*
+ 0010 5d2e5de1 9241272c 37a6ce36 b5418cb9  .*
+ 0020 287e0b24 3b40f227 c83c2bde 3f407b8f  .*
+ 0030 069ee40f 0440d61c 4ce09205 3810675c  .*
+ 0040 e3df062a 04406520 db16d80d d72f205e  .*
+ 0050 c746ae64                             .*
diff --git a/gas/testsuite/gas/vax/flonum.s b/gas/testsuite/gas/vax/flonum.s
new file mode 100644
index 000000000000..9793c38459a5
--- /dev/null
+++ b/gas/testsuite/gas/vax/flonum.s
@@ -0,0 +1,12 @@
+.data
+
+.float		0.12345
+.ffloat		1.23456
+.f_floating	2.34567
+.double		3.45678
+.dfloat		4.56789
+.d_floating	5.67890
+.gfloat		6.78901
+.g_floating	7.89012
+.hfloat		8.90123
+.h_floating	9.01234
diff --git a/gas/testsuite/gas/vax/vax.exp b/gas/testsuite/gas/vax/vax.exp
index f61906c15d31..bfe9f8aca35f 100644
--- a/gas/testsuite/gas/vax/vax.exp
+++ b/gas/testsuite/gas/vax/vax.exp
@@ -8,7 +8,7 @@ proc do_quad {} {
     set x2 0
     set x3 0
     set file "quad.s"
-    if { [istarget vax-*-*elf*] || [istarget vax-*-linux-gnu*] } then {
+    if { [istarget vax-*-*elf*] || [istarget vax-*-linux-*] } then {
 	set file "quad_elf.s"
     }
     gas_start $file "-al"
@@ -29,7 +29,9 @@ proc do_quad {} {
 if [istarget vax-*-* ] then {
     do_quad
 
-    if [istarget vax-*-*elf*] {
+    run_dump_test "flonum"
+
+    if { [istarget vax-*-*elf*] || [istarget vax-*-linux-*] } then {
 	run_dump_test "elf-rel"
     }
 }
diff --git a/gas/testsuite/gas/vtable/entry0.d b/gas/testsuite/gas/vtable/entry0.d
deleted file mode 100644
index ee0bb990276e..000000000000
--- a/gas/testsuite/gas/vtable/entry0.d
+++ /dev/null
@@ -1,10 +0,0 @@
-#objdump: -r
-#name: vtable entry0
-
-.*: +file format .*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET +TYPE +VALUE 
-0+0000010 R_.*_GNU_VTENTRY  vtbl_a
-
-
diff --git a/gas/testsuite/gas/vtable/entry0.s b/gas/testsuite/gas/vtable/entry0.s
deleted file mode 100644
index 878c44c00605..000000000000
--- a/gas/testsuite/gas/vtable/entry0.s
+++ /dev/null
@@ -1,2 +0,0 @@
- .text
- .vtable_entry vtbl_a, 16
diff --git a/gas/testsuite/gas/vtable/entry1.d b/gas/testsuite/gas/vtable/entry1.d
deleted file mode 100644
index 7fa6e4b743d1..000000000000
--- a/gas/testsuite/gas/vtable/entry1.d
+++ /dev/null
@@ -1,10 +0,0 @@
-#objdump: -r
-#name: vtable entry1
-
-.*: +file format .*
-
-RELOCATION RECORDS FOR \[.text\]:
-OFFSET +TYPE +VALUE 
-0+0000000 R_.*_GNU_VTENTRY  vtbl_a.*
-
-
diff --git a/gas/testsuite/gas/vtable/entry1.s b/gas/testsuite/gas/vtable/entry1.s
deleted file mode 100644
index 878c44c00605..000000000000
--- a/gas/testsuite/gas/vtable/entry1.s
+++ /dev/null
@@ -1,2 +0,0 @@
- .text
- .vtable_entry vtbl_a, 16
diff --git a/gas/testsuite/gas/vtable/inherit0.d b/gas/testsuite/gas/vtable/inherit0.d
deleted file mode 100644
index 62795b1ac1ea..000000000000
--- a/gas/testsuite/gas/vtable/inherit0.d
+++ /dev/null
@@ -1,10 +0,0 @@
-#objdump: -r
-#name: vtable inherit0
-
-.*: +file format .*
-
-RELOCATION RECORDS FOR \[.data\]:
-OFFSET +TYPE +VALUE 
-0+0000000 R_.*_GNU_VTINHERIT  \*ABS\*
-0+0000010 R_.*_GNU_VTINHERIT  vtbl_a
-
diff --git a/gas/testsuite/gas/vtable/inherit0.s b/gas/testsuite/gas/vtable/inherit0.s
deleted file mode 100644
index 67fad709e70b..000000000000
--- a/gas/testsuite/gas/vtable/inherit0.s
+++ /dev/null
@@ -1,13 +0,0 @@
- .data
-
- .type vtbl_a,object
-vtbl_a:
-	.space 16
- .size vtbl_a,16
- .vtable_inherit vtbl_a, 0
-
- .type vtbl_b,object
-vtbl_b:
-	.space 16
- .size vtbl_b,16
- .vtable_inherit vtbl_b, vtbl_a
diff --git a/gas/testsuite/gas/vtable/inherit1.l b/gas/testsuite/gas/vtable/inherit1.l
deleted file mode 100644
index bdd63583458d..000000000000
--- a/gas/testsuite/gas/vtable/inherit1.l
+++ /dev/null
@@ -1,6 +0,0 @@
-.*: Assembler messages:
-.*:1: Error: expected `vtbl_a' to have already been set for .vtable_inherit
-.*GAS.*
-
-
- +1.*vtable_inherit vtbl_a, 0
diff --git a/gas/testsuite/gas/vtable/inherit1.s b/gas/testsuite/gas/vtable/inherit1.s
deleted file mode 100644
index 46f2b092fe9b..000000000000
--- a/gas/testsuite/gas/vtable/inherit1.s
+++ /dev/null
@@ -1 +0,0 @@
- .vtable_inherit vtbl_a, 0
diff --git a/gas/testsuite/gas/vtable/vtable.exp b/gas/testsuite/gas/vtable/vtable.exp
deleted file mode 100644
index cb74b7a7c609..000000000000
--- a/gas/testsuite/gas/vtable/vtable.exp
+++ /dev/null
@@ -1,59 +0,0 @@
-#
-# vtable tests
-#
-proc run_list_test { name opts } {
-    global srcdir subdir
-    set testname "vtable $name"
-    set file $srcdir/$subdir/$name
-    gas_run ${name}.s $opts ">&dump.out"
-    if { [regexp_diff "dump.out" "${file}.l"] } then {
-	fail $testname
-	verbose "output is [file_contents "dump.out"]" 2
-	return
-    }
-    pass $testname
-}
-
-# These tests are not (yet) supported on some targets.
-proc vtable_setup_xfails { } {
-    setup_xfail "alpha*-*" "arc-*" "avr-*" "d30v-*"
-    setup_xfail "h8300*-*" "hppa*64*-*-*hpux*"
-    setup_xfail "i370-*" "i860-*" "i960-*" "ia64-*" "ip2k-*"
-    setup_xfail "mn10200-*" "or32-*" "sparc64*-*"
-}
-
-# Vtable bits are only supported by ELF targets.
-if { (   [istarget "*-*-elf*"] || [istarget "*-*-linux*"])
-     && ![istarget *-*-linux*aout*]
-     && ![istarget *-*-linux*ecoff*]
-     && ![istarget *-*-linux*oldld*] } then {
-
-    vtable_setup_xfails
-    run_dump_test "inherit0"
-
-    # This particular test is supposed to fail..
-    run_list_test "inherit1" "-al"
-
-    # The vtable entry results are different on Rel and Rela targets.
-    vtable_setup_xfails
-    if {[istarget "arm*-*"]
-	|| [istarget "arc-*"]
-	|| [istarget "d10v-*"]
-	|| [istarget "dlx-*"]
-	|| [istarget "i*86-*"] 
-	|| ([istarget "mips*-*"]
-	    && ! [istarget "mips64*-*-linux*"]
-	    && ! [istarget "mips*-*-irix6*"])
-	|| [istarget "m68hc*-*"] 
-	|| [istarget "or32-*"] 
-	|| [istarget "strongarm*-*"] 
-	|| [istarget "xscale*-*"] } then {
-
-	run_dump_test "entry0"
-
-    } else {
-
-	run_dump_test "entry1"
-
-    }
-}
diff --git a/gas/testsuite/gas/xc16x/add.s b/gas/testsuite/gas/xc16x/add.s
new file mode 100644
index 000000000000..bab7c0957e38
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/add.s
@@ -0,0 +1,17 @@
+.text
+xc16x_add:
+add r0,r1
+add r0,[r1]
+add r0,[r1+]
+add r0,#3
+add r0,#1234
+add r0,0xffed
+add 0xffed,r0
+
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/add_test.s b/gas/testsuite/gas/xc16x/add_test.s
new file mode 100644
index 000000000000..7924f5040c5f
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/add_test.s
@@ -0,0 +1,92 @@
+.text
+_start:
+	add r0,r1
+	add r0,r2
+	add r0,r3
+	add r0,r4
+	add r0,r5
+	add r0,r6
+	add r0,r7
+	add r0,r8
+	add r0,r9
+	add r0,r10
+	add r0,r11
+	add r0,r12
+	add r0,r13
+	add r0,r14
+	add r0,r15
+
+	add r1,r0
+	add r1,r2
+	add r1,r3
+	add r1,r4
+	add r1,r5
+	add r1,r6
+	add r1,r7
+	add r1,r8
+	add r1,r9
+	add r1,r10
+	add r1,r11
+	add r1,r12
+	add r1,r13
+	add r1,r14
+	add r1,r15
+	
+   	add r2,r0
+	add r2,r1
+	add r2,r3
+	add r2,r4
+	add r2,r5
+	add r2,r6
+	add r2,r7
+	add r2,r8
+	add r2,r9
+	add r2,r10
+	add r2,r11
+	add r2,r12
+	add r2,r13
+	add r2,r14
+	add r2,r15
+	
+	add r3,r0
+	add r3,r1
+	add r3,r2
+	add r3,r4
+	add r3,r5
+	add r3,r6
+	add r3,r7
+	add r3,r8
+	add r3,r9
+	add r3,r10
+	add r3,r11
+	add r3,r12
+	add r3,r13
+	add r3,r14
+	add r3,r15
+	
+	add r0,[r1]
+	add r0,[r1+]
+	add r0,#3
+	add r0,#0xffff
+	add r0,0xffff
+	add 0xffff,r0
+	
+	addb rl0,rh0
+	addb rl0[r0]
+	addb rl0,#3
+	addb rl0,#0xff
+	addb r0,0xff10
+	addb 0xff10,r0
+	
+	addc r0,r1
+	addc r0,[r1]
+	addc r0,#3
+	addc r0,#0xff12
+	addc r0,#0xff12
+	addc r0,0xff12
+	addc 0xff12,r0
+	
+	addcb rl0,#3
+	addcb rl0,#0xff
+	addcb r0,0xff10
+	addcb 0xff10,r0
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/addb.s b/gas/testsuite/gas/xc16x/addb.s
new file mode 100644
index 000000000000..7c7dd9449a9c
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/addb.s
@@ -0,0 +1,11 @@
+	.section .text
+	.global _fun
+xc16x_add:
+
+	addb rl0,rl1
+	addb rl0,[r1]
+	addb rl0,[r1+]
+	addb rl0,#0x2
+	addb rl0,#0x33
+	addb rl0,0x2387
+	addb 0x2387,rl0
diff --git a/gas/testsuite/gas/xc16x/addc.s b/gas/testsuite/gas/xc16x/addc.s
new file mode 100644
index 000000000000..8f33699c6438
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/addc.s
@@ -0,0 +1,11 @@
+	.section .text
+	.global _fun
+xc16x_add:
+
+	addc r0,r1
+	addc r0,[r1]
+	addc r0,[r1+]
+	addc r0,#0x34
+	addc r0,#0x3456
+	addc r0,0x2387
+	addc 0x2387,r0
diff --git a/gas/testsuite/gas/xc16x/addcb.s b/gas/testsuite/gas/xc16x/addcb.s
new file mode 100644
index 000000000000..74cfca7272a5
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/addcb.s
@@ -0,0 +1,17 @@
+	.section .text
+	.global _fun
+xc16x_add:
+
+	addcb rl0,rl1
+	addcb rl0,[r1]
+	addcb rl0,[r1+]
+	addcb rl0,#0x02
+	addcb rl0,#0x23
+	addcb 0x2387,rl0
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/and.s b/gas/testsuite/gas/xc16x/and.s
new file mode 100644
index 000000000000..14e9c7e8b689
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/and.s
@@ -0,0 +1,14 @@
+.section .text
+.global  _fun
+
+xc16x_and:
+
+	and r0,r1
+	and r0,[r1]
+	and r0,[r1+]
+	and r0,#3
+	and r0,#0xfcbe
+	and r0,0x0230
+	and 0x320,r0
+	
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/andb.s b/gas/testsuite/gas/xc16x/andb.s
new file mode 100644
index 000000000000..eee0ab82bf6b
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/andb.s
@@ -0,0 +1,10 @@
+        .section .text
+        .global _fun
+xc16x_andb:
+		andb rl0,rl1
+		andb rl0,[r1]
+		andb rl0,[r1+]
+		andb rl0,#3
+		andb rl0,#0xbe
+		andb rl0,0x0230
+		andb 0x320,rl0
diff --git a/gas/testsuite/gas/xc16x/bfldl.s b/gas/testsuite/gas/xc16x/bfldl.s
new file mode 100644
index 000000000000..7300c4ad2b04
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/bfldl.s
@@ -0,0 +1,4 @@
+  .text
+ xc16x_bfldl:
+   BFLDL r0,#0x87,#0x0e
+   BFLDH r0,#0xff,#0x0e
diff --git a/gas/testsuite/gas/xc16x/bit.s b/gas/testsuite/gas/xc16x/bit.s
new file mode 100644
index 000000000000..571e79e020df
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/bit.s
@@ -0,0 +1,11 @@
+.text
+xc16x_bit:
+bclr  r0.1
+bset  r0.1
+bmov  r0.2,r0.1
+bmovn r0.3,r0.2 
+band  r0.1,r0.4
+bor   r0.1,r0.2
+bxor  r0.1,r0.2
+bcmp  r0.1,r0.2
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/calla.s b/gas/testsuite/gas/xc16x/calla.s
new file mode 100644
index 000000000000..3604e9a95849
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/calla.s
@@ -0,0 +1,24 @@
+.text
+xc16x_calla:
+calla cc_uc,0xaaaa
+calla cc_z,0xaaaa
+calla cc_nz,0xaaaa
+calla cc_v,0xaaaa
+calla cc_nv,0xaaaa
+calla cc_n,0xaaaa
+calla cc_nn,0xaaaa
+calla cc_c,0xaaaa
+calla cc_nc,0xaaaa
+calla cc_eq,0xaaaa
+calla cc_ne,0xaaaa
+calla cc_ult,0xaaaa
+calla cc_ule,0xaaaa
+calla cc_uge,0xaaaa
+calla cc_ugt,0xaaaa
+calla cc_sle,0xaaaa
+calla cc_sge,0xaaaa
+calla cc_sgt,0xaaaa
+calla cc_net,0xaaaa
+calla cc_slt,0xaaaa	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/calli.s b/gas/testsuite/gas/xc16x/calli.s
new file mode 100644
index 000000000000..807ae1b2cd4b
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/calli.s
@@ -0,0 +1,21 @@
+.text
+xc16x_calli:
+calli cc_uc,[r1]
+calli cc_z,[r1]
+calli cc_nz,[r1]
+calli cc_v,[r1]
+calli cc_nv,[r1]
+calli cc_n,[r1]
+calli cc_nn,[r1]
+calli cc_c,[r1]
+calli cc_nc,[r1]
+calli cc_eq,[r1]
+calli cc_ne,[r1]
+calli cc_ult,[r1]
+calli cc_ule,[r1]
+calli cc_uge,[r1]
+calli cc_ugt,[r1]
+calli cc_sle,[r1]
+calli cc_sge,[r1]
+calli cc_net,[r1]
+calli cc_slt,[r1]
diff --git a/gas/testsuite/gas/xc16x/cmp.s b/gas/testsuite/gas/xc16x/cmp.s
new file mode 100644
index 000000000000..50034920db26
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/cmp.s
@@ -0,0 +1,9 @@
+.text
+xc16x_cmp:
+cmp   r0,r1
+cmp   r0,[r1]
+cmp   r0,[r1+]
+cmp   r0,#3
+cmp   r0,#0x0234
+cmp   r0,0x3452
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/cmp_test.s b/gas/testsuite/gas/xc16x/cmp_test.s
new file mode 100644
index 000000000000..932ce96ace91
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/cmp_test.s
@@ -0,0 +1,45 @@
+.text
+cmp   r0,r1
+cmp   r0,[r1]
+cmp   r0,[r1+]
+cmp   r0,#3
+cmp   r0,#0x0234
+cmp   r0,0x3452
+
+cmp   r0,r1
+cmp   r0,[r1]
+cmp   r0,[r1+]
+cmp   r0,#3
+cmp   r0,#0xcdef
+cmp   r0,0xcdef
+
+cmpb  rl0,rl1
+cmpb  rl0,[r1]
+cmpb  rl0,[r1+]
+cmpb  rl0,#3
+cmpb  rl0,#cd
+cmpb  rl0,0x0234
+
+cmpb  rl0,rl1
+cmpb  rl0,[r1]
+cmpb  rl0,[r1+]
+cmpb  rl0,#3
+cmpb  rl0,#cd
+cmpb  rl0,0xcdef
+
+cmpd1	r0,#0x0f
+cmpd1 	r0,#0x0fccb
+cmpd1	r0,0xffcb
+cmpd2	r0,#0x0f
+cmpd2 	r0,#0x0fccb
+cmpd2	r0,0xffcb
+
+cmpi1	r0,#0x0f
+cmpi1 	r0,#0x0fccb
+cmpi1	r0,0xffcb
+cmpi2	r0,#0x0f
+cmpi2 	r0,#0x0fccb
+cmpi2	r0,0xffcb
+
+
+
diff --git a/gas/testsuite/gas/xc16x/cmpb.s b/gas/testsuite/gas/xc16x/cmpb.s
new file mode 100644
index 000000000000..3dfc698b9f94
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/cmpb.s
@@ -0,0 +1,8 @@
+.text
+xc16x_cmpb:
+cmpb  rl0,rl1
+cmpb  rl0,[r1]
+cmpb  rl0,[r1+]
+cmpb  rl0,#3
+cmpb  rl0,#34
+cmpb  rl0,0x0234
diff --git a/gas/testsuite/gas/xc16x/cmpi.s b/gas/testsuite/gas/xc16x/cmpi.s
new file mode 100644
index 000000000000..813689012ff1
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/cmpi.s
@@ -0,0 +1,18 @@
+.section  .text
+.global	 _fun
+
+xc16x_cmpd:
+
+	cmpd1	r0,#0x0f
+	cmpd1 	r0,#0x0fccb
+	cmpd1	r0,0xffcb
+	cmpd2	r0,#0x0f
+	cmpd2 	r0,#0x0fccb
+	cmpd2	r0,0xffcb
+	cmpi1	r0,#0x0f
+	cmpi1 	r0,#0x0fccb
+	cmpi1	r0,0xffcb
+	cmpi2	r0,#0x0f
+	cmpi2 	r0,#0x0fccb
+	cmpi2	r0,0xffcb
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/cpl.s b/gas/testsuite/gas/xc16x/cpl.s
new file mode 100644
index 000000000000..b0d9817667f4
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/cpl.s
@@ -0,0 +1,7 @@
+       .section .text
+       .global _fun
+
+xc16x_cpl_cplb:
+
+	cpl   r0
+	cplb rl0
diff --git a/gas/testsuite/gas/xc16x/div.s b/gas/testsuite/gas/xc16x/div.s
new file mode 100644
index 000000000000..7b5ad9e064d4
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/div.s
@@ -0,0 +1,8 @@
+       .section .text
+       .global _fun
+xc16x_div:
+
+	div     r0
+	divl    r0
+	divlu  r0
+	divu   r0
diff --git a/gas/testsuite/gas/xc16x/jmpa.s b/gas/testsuite/gas/xc16x/jmpa.s
new file mode 100644
index 000000000000..732cc4719c1c
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/jmpa.s
@@ -0,0 +1,23 @@
+.text
+xc16x_jmpa:
+	jmpa cc_UC,0xaaaa
+	jmpa cc_Z,0xaaaa
+	jmpa cc_NZ,0xaaaa
+	jmpa cc_V,0xaaaa
+	jmpa cc_NV,0xaaaa
+	jmpa cc_N,0xaaaa
+	jmpa cc_NN,0xaaaa
+	jmpa cc_ULT,0xaaaa
+	jmpa cc_UGE,0xaaaa
+	jmpa cc_Z,0xaaaa
+	jmpa cc_NZ,0xaaaa
+	jmpa cc_ULT,0xaaaa
+	jmpa cc_ULE,0xaaaa
+	jmpa cc_UGE,0xaaaa
+	jmpa cc_UGT,0xaaaa
+	jmpa cc_SLE,0xaaaa
+	jmpa cc_SGE,0xaaaa
+	jmpa cc_SGT,0xaaaa
+	jmpa cc_NET,0xaaaa
+
+		
diff --git a/gas/testsuite/gas/xc16x/jmpi.s b/gas/testsuite/gas/xc16x/jmpi.s
new file mode 100644
index 000000000000..337d5fade57c
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/jmpi.s
@@ -0,0 +1,24 @@
+.section  .text
+.global   _fun
+
+xc16x_jmpi:
+
+	jmpi cc_UC, [r7]
+	jmpi cc_z,  [r7]
+	jmpi cc_NZ, [r7]
+	jmpi cc_V,  [r7]
+	jmpi cc_NV, [r7]
+	jmpi cc_N,  [r7]
+	jmpi cc_NN, [r7]
+	jmpi cc_C,  [r7]
+	jmpi cc_NC, [r7]
+	jmpi cc_EQ, [r7]
+	jmpi cc_NE, [r7]
+	jmpi cc_ULT,[r7]
+	jmpi cc_ULE,[r7]
+	jmpi cc_UGE,[r7]
+	jmpi cc_UGT,[r7]
+	jmpi cc_SLE,[r7]
+	jmpi cc_SGE,[r7]
+	jmpi cc_SGT,[r7]
+	jmpi cc_NET,[r7]
diff --git a/gas/testsuite/gas/xc16x/jmpr.s b/gas/testsuite/gas/xc16x/jmpr.s
new file mode 100644
index 000000000000..7fbdfac6f0ad
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/jmpr.s
@@ -0,0 +1,25 @@
+        .section  .text
+        .global _fun
+
+xc16x_jmpr:
+
+	jmpr cc_uc, xc16x_jmpr
+	jmpr cc_z,  xc16x_jmpr
+	jmpr cc_nz, xc16x_jmpr
+	jmpr cc_v,  xc16x_jmpr
+	jmpr cc_nv, xc16x_jmpr
+	jmpr cc_n,  xc16x_jmpr
+	jmpr cc_nn, xc16x_jmpr
+	jmpr cc_c,  xc16x_jmpr
+	jmpr cc_nc, xc16x_jmpr
+	jmpr cc_eq, xc16x_jmpr
+	jmpr cc_ne, xc16x_jmpr
+	jmpr cc_ult,xc16x_jmpr
+	jmpr cc_ule,xc16x_jmpr
+	jmpr cc_uge,xc16x_jmpr
+	jmpr cc_ugt,xc16x_jmpr
+	jmpr cc_sle,xc16x_jmpr
+	jmpr cc_sge,xc16x_jmpr
+	jmpr cc_sgt,xc16x_jmpr
+	jmpr cc_net,xc16x_jmpr
+	jmpr cc_slt,xc16x_jmpr	
diff --git a/gas/testsuite/gas/xc16x/mov.s b/gas/testsuite/gas/xc16x/mov.s
new file mode 100644
index 000000000000..164d97cf868a
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/mov.s
@@ -0,0 +1,20 @@
+        .section .text
+        .global _fun
+xc16x_mov:
+
+	mov r0,r1
+	mov r0,#02
+	mov r0,#0xfcbe
+	mov r0,[r1]
+	mov r0,[r1+]
+	mov [r0],r1
+	mov [-r0],r1
+	mov [r0],[r1]
+	mov [r0+],[r1]
+	mov [r0],[r1+]
+	mov r0,[r0+#0xffcb]
+	mov [r0+#0xffcb],r0
+	mov [r0],0xffcb
+	mov 0xffcb,[r0]
+	mov r0,0xffcb
+	mov 0xffcb,r0
diff --git a/gas/testsuite/gas/xc16x/mov_test.s b/gas/testsuite/gas/xc16x/mov_test.s
new file mode 100644
index 000000000000..a3776c1fb881
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/mov_test.s
@@ -0,0 +1,85 @@
+	.xc16x
+	mov r0,r1
+	mov r0,#02
+	mov r0,#0x0001
+	mov r0,[r1]
+	mov r0,[r1+]
+	mov [r0],r1
+	mov [-r0],r1
+	mov [r0],[r1]
+	mov [r0+],[r1]
+	mov [r0],[r1+]
+	mov r0,[r0+#0x0001]
+	mov [r0+#0x0001],r0
+	mov [r0],0x0001
+	mov 0x0001,[r0]
+	mov r0,0x0001
+	mov 0x0001,r0
+ 
+ 	mov r0,r1
+ 	mov r0,#02
+ 	mov r0,#0xffff
+ 	mov r0,[r1]
+ 	mov r0,[r1+]
+ 	mov [r0],r1
+ 	mov [-r0],r1
+ 	mov [r0],[r1]
+ 	mov [r0+],[r1]
+ 	mov [r0],[r1+]
+ 	mov r0,[r0+#0xffff]
+ 	mov [r0+#0xffff],r0
+ 	mov [r0],0xffff
+ 	mov 0xffff,[r0]
+ 	mov r0,0xffff
+	mov 0xffff,r0
+ 
+ 	movb rl0,r2
+ 	movb rl0,#0x12
+ 	movb r3,[r2]
+ 	movb rl0,[r2+]
+ 	movb [-r2],rl0
+ 	movb [r3],[r2+]
+ 	movb [r3],[r2]
+ 	movb [r2+],[r3]
+ 	movb [r2],[r3+]
+ 	movb rl0,[r3+#0x1234]
+ 	movb [r3+#0x1234],rl0
+ 	movb [r3],0x1234
+ 	movb [r3],0x1234
+ 	movb 0x1234,[r3]
+ 	movb rl0,0x12
+ 	movb 0x12,rl0
+ 	
+ 	movb rl0,r2
+ 	movb rl0,#0xff
+ 	movb r3,[r2]
+ 	movb rl0,[r2+]
+ 	movb [-r2],rl0
+ 	movb [r3],[r2+]
+ 	movb [r3],[r2]
+ 	movb [r2+],[r3]
+ 	movb [r2],[r3+]
+ 	movb rl0,[r3+#0xffff]
+ 	movb [r3+#0xffff],rl0
+ 	movb [r3],0xffff
+ 	movb [r3],0xffff
+ 	movb 0xffff,[r3]
+ 	movb rl0,0xff
+ 	movb 0xff,rl0	
+ 	
+ 	movbs  r0,rl1
+	movbs  r0,0x12
+	movbs  0x1234,rl0
+	
+	movbs  r0,rl1
+	movbs  r0,0xff
+	movbs  0xffff,rl0
+
+	movbz r2,rl0
+	movbz r0,0x1234
+	movbz 0x1234,rl0
+ 	
+	movbz r2,rl0
+	movbz r0,0xffff
+	movbz 0xffff,rl0
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/movb.s b/gas/testsuite/gas/xc16x/movb.s
new file mode 100644
index 000000000000..3050704bc9a0
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/movb.s
@@ -0,0 +1,26 @@
+	.section .text
+	.global _fun
+xc16x_movb:
+
+	movb rl0,r2
+	movb rl0,#0x12
+	movb r3,[r2]
+	movb rl0,[r2+]
+	movb [-r2],rl0
+	movb [r3],[r2+]
+	movb [r3],[r2]
+	movb [r2+],[r3]
+	movb [r2],[r3+]
+	movb rl0,[r3+#0x1234]
+	movb [r3+#0x1234],rl0
+	movb [r3],0x1234
+	movb [r3],0xeeff
+	movb 0x1234,[r3]
+	movb rl0,0x12
+	movb 0x12,rl0
+	
+	
+	
+
+	
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/movbs.s b/gas/testsuite/gas/xc16x/movbs.s
new file mode 100644
index 000000000000..36bed4d85e77
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/movbs.s
@@ -0,0 +1,8 @@
+        .section .text
+        .global  _fun
+
+xc16x_movbs:
+
+	movbs  r0,rl1
+	movbs  r0,0xff
+	movbs  0xffcb,rl0
diff --git a/gas/testsuite/gas/xc16x/movbz.s b/gas/testsuite/gas/xc16x/movbz.s
new file mode 100644
index 000000000000..8571f9634426
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/movbz.s
@@ -0,0 +1,9 @@
+	.section .text
+	.global _fun
+xc16x_movbz:
+
+	movbz r2,rl0
+	movbz r0,0x23dd
+	movbz 0x23,rl0
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/mul.s b/gas/testsuite/gas/xc16x/mul.s
new file mode 100644
index 000000000000..0e7c4beaff22
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/mul.s
@@ -0,0 +1,6 @@
+	.section .text
+	.global _fun
+xc16x_mul:
+
+	mul    r0,r1
+	mulu  r0,r1
diff --git a/gas/testsuite/gas/xc16x/neg.s b/gas/testsuite/gas/xc16x/neg.s
new file mode 100644
index 000000000000..b95824e8f723
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/neg.s
@@ -0,0 +1,6 @@
+       .section .text
+       .global  _fun
+xc16x_neg:
+
+	neg   r0
+	negb rl0
diff --git a/gas/testsuite/gas/xc16x/nop.s b/gas/testsuite/gas/xc16x/nop.s
new file mode 100644
index 000000000000..cc297e160025
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/nop.s
@@ -0,0 +1,6 @@
+        .section .text
+        .global _fun
+xc16x_nop:
+        nop
+        nop
+
diff --git a/gas/testsuite/gas/xc16x/or.s b/gas/testsuite/gas/xc16x/or.s
new file mode 100644
index 000000000000..46deeccd7d8b
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/or.s
@@ -0,0 +1,11 @@
+       .section .text
+       .global _fun
+xc16x_or:
+
+	or  r0,r1
+	or  r0,[r1]
+	or  r0,[r1+]
+	or  r0,#3
+	or  r0,#0x0234
+	or  r0,0x4536
+	or  0x4536,r0
diff --git a/gas/testsuite/gas/xc16x/orb.s b/gas/testsuite/gas/xc16x/orb.s
new file mode 100644
index 000000000000..62bfa7633210
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/orb.s
@@ -0,0 +1,10 @@
+       .section .text
+       .global _fun
+xc16x_or:
+	orb  rl0,rl1
+	orb  rl0,[r1]
+	orb  rl0,[r1+]
+	orb  rl0,#3
+	orb  rl0,#0x23
+	orb  rl0,0x0234
+	orb  0x0234,rl0
diff --git a/gas/testsuite/gas/xc16x/prior.s b/gas/testsuite/gas/xc16x/prior.s
new file mode 100644
index 000000000000..aa4bb78e5583
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/prior.s
@@ -0,0 +1,5 @@
+        .section .text
+        .global _fun
+xc16x_prior:
+
+        prior r0,r1
diff --git a/gas/testsuite/gas/xc16x/pushpop.s b/gas/testsuite/gas/xc16x/pushpop.s
new file mode 100644
index 000000000000..4fafde66db32
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/pushpop.s
@@ -0,0 +1,5 @@
+       .section .text
+       .global _fun
+xc16x_pushpop:
+	pop   r0
+	push  r0
diff --git a/gas/testsuite/gas/xc16x/ret.s b/gas/testsuite/gas/xc16x/ret.s
new file mode 100644
index 000000000000..62278a5e93ae
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/ret.s
@@ -0,0 +1,9 @@
+        .section .text
+        .global  _fun
+
+xc16x_ret:
+        ret
+        reti
+        rets
+        retp  r5
+        
diff --git a/gas/testsuite/gas/xc16x/scxt.s b/gas/testsuite/gas/xc16x/scxt.s
new file mode 100644
index 000000000000..e8a23c39756e
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/scxt.s
@@ -0,0 +1,6 @@
+        .section .text
+        .global _fun
+xc16x_scxt:
+        scxt r0,#0xffff
+        scxt r0,0xffff
+
diff --git a/gas/testsuite/gas/xc16x/shlrol.s b/gas/testsuite/gas/xc16x/shlrol.s
new file mode 100644
index 000000000000..04e6591d69e0
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/shlrol.s
@@ -0,0 +1,14 @@
+       .section .text
+       .global _fun
+xc16x_shlrol:	
+
+	shl   r0,r1
+	shl   r0,#a
+	shr   r0,r1
+	shr   r0,#a
+	rol    r0,r1
+	rol    r0,#a
+	ror    r0,r1
+	ror    r0,#a
+	ashr r0,r1
+	ashr r0,#a
diff --git a/gas/testsuite/gas/xc16x/sub.s b/gas/testsuite/gas/xc16x/sub.s
new file mode 100644
index 000000000000..5baad828e099
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/sub.s
@@ -0,0 +1,19 @@
+	.section .text
+	.global _fun
+xc16x_sub:
+
+	sub r0,r1
+	sub r0,[r1]
+	sub r0,[r1+]
+	sub r0,#0x1
+	sub r0,#0x7643
+	sub r0,0x7643
+	sub 0x7643,r0
+	
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/sub_test.s b/gas/testsuite/gas/xc16x/sub_test.s
new file mode 100644
index 000000000000..880102e650ea
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/sub_test.s
@@ -0,0 +1,70 @@
+	.text
+_start:
+	sub r0,r1
+	sub r0,[r1]
+	sub r0,[r1+]
+	sub r0,#0x1
+	sub r0,#0x7643
+	sub r0,0x7643
+	sub 0x7643,r0
+	
+	sub r1,r0
+	sub r1,[r0]
+	sub r1,[r0+]
+	sub r1,#0x1
+	sub r1,#0xCDEF
+	sub r1,0xCDEF
+	sub 0xCDEF,r1
+
+
+	subb rl0,rl1
+	subb rl0,[r1]
+	subb rl0,[r1+]
+	subb rl0,#0x1
+	subb rl0,#0x43
+	subb rl0,0x7643
+	subb 0x7643,rl0
+	
+	subb rl1,rl0
+	subb rl1,[r0]
+	subb rl1,[r0+]
+	subb rl1,#0x1
+	subb rl1,#0xCD
+	subb rl1,0xCDEF
+	subb 0xCDEF,rl1
+	
+
+
+	subc r0,r1
+	subc r0,[r1]
+	subc r0,[r1+]
+	subc r0,#0x2
+	subc r0,#0x43
+	subc r0,0x7643
+	subc 0x7643,r0
+	
+	subc r1,r0
+	subc r1,[r0]
+	subc r1,[r0+]
+	subc r1,#0xC
+	subc r1,#0xCD
+	subc r1,0xCDEF
+	subc 0xCDEF,r1
+
+	subcb rl0,rl1
+	subcb rl0,[r1]
+	subcb rl0,[r1+]
+	subcb rl0,#0x2
+	subcb rl0,#0x43
+	subcb rl0,0x7643
+	subcb 0x7643,rl0
+
+	subcb rl0,rl1
+	subcb rl0,[r1]
+	subcb rl0,[r1+]
+	subcb rl0,#0x2
+	subcb rl0,#0x43
+	subcb rl0,0x7643
+	subcb 0x7643,rl0
+	
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/subb.s b/gas/testsuite/gas/xc16x/subb.s
new file mode 100644
index 000000000000..c066a433e804
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/subb.s
@@ -0,0 +1,19 @@
+	.section .text
+	.global _fun
+xc16x_subb:
+
+	subb rl0,rl1
+	subb rl0,[r1]
+	subb rl0,[r1+]
+	subb rl0,#0x1
+	subb rl0,#0x43
+	subb rl0,0x7643
+	subb 0x7643,rl0
+	
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/subc.s b/gas/testsuite/gas/xc16x/subc.s
new file mode 100644
index 000000000000..a8af7d033b89
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/subc.s
@@ -0,0 +1,19 @@
+	.section .text
+	.global _fun
+xc16x_subc:
+
+	subc r0,r1
+	subc r0,[r1]
+	subc r0,[r1+]
+	subc r0,#0x2
+	subc r0,#0x43
+	subc r0,0x7643
+	subc 0x7643,r0
+	
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/subcb.s b/gas/testsuite/gas/xc16x/subcb.s
new file mode 100644
index 000000000000..e8911ee966dc
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/subcb.s
@@ -0,0 +1,20 @@
+	.section .text
+	.global _fun
+xc16x_subcb:
+
+	subcb rl0,rl1
+	subcb rl0,[r1]
+	subcb rl0,[r1+]
+	subcb rl0,#0x2
+	subcb rl0,#0x43
+	subcb rl0,0x7643
+	subcb 0x7643,rl0
+	
+	
+	
+	
+
+	
+	
+
+	
\ No newline at end of file
diff --git a/gas/testsuite/gas/xc16x/syscontrol1.s b/gas/testsuite/gas/xc16x/syscontrol1.s
new file mode 100644
index 000000000000..c21f07de5898
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/syscontrol1.s
@@ -0,0 +1,12 @@
+        .section .text
+        .global _fun
+xc16x_syscontrol:
+        srst
+        sbrk
+        idle
+        pwrdn
+        srvwdt
+        diswdt
+        enwdt
+        einit
+
diff --git a/gas/testsuite/gas/xc16x/syscontrol2.s b/gas/testsuite/gas/xc16x/syscontrol2.s
new file mode 100644
index 000000000000..61fb70302188
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/syscontrol2.s
@@ -0,0 +1,26 @@
+.text
+xc16x_syscontrol2:
+        extr #0x4
+        extr #0x3
+        extr #0x2
+        extr #0x1
+
+        atomic #0x4
+        atomic #0x3
+        atomic #0x2
+        atomic #0x1
+
+        extp r5,#0x4
+        extp #0x3ff,#0x4
+        extpr r5,#0x4
+        extpr #0x3ff,#0x4
+
+        exts r5,#0x4
+        exts #0x1,#0x4
+
+        extsr r5,#0x4
+        extsr #0x1,#0x4
+
+
+
+
diff --git a/gas/testsuite/gas/xc16x/trap.s b/gas/testsuite/gas/xc16x/trap.s
new file mode 100644
index 000000000000..f8dc87b52cfd
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/trap.s
@@ -0,0 +1,6 @@
+        .section .text
+        .global  _fun
+
+xc16x_trap:
+
+	trap #0x02
diff --git a/gas/testsuite/gas/xc16x/xc16x.exp b/gas/testsuite/gas/xc16x/xc16x.exp
new file mode 100644
index 000000000000..c53e65750567
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/xc16x.exp
@@ -0,0 +1,1317 @@
+#
+# Some xc16x tests
+#
+proc do_xc16x_add {} {
+    set testname "add.s: xc16x add word tests"
+    set x 0
+
+    gas_start "add.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 0001\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 0809\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 080D\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 0803\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 06F0D204\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 02F0EDFF\[^\n\]*\n"  { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 04F0EDFF\[^\n\]*\n"  { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof				    { break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_addb {} {
+    set testname "addb.s: xc16x add byte tests"
+    set x 0
+
+    gas_start "addb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 0102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 0909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 090D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 0902\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 07F03300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 03F08723\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 05F08723\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_addc {} {
+    set testname "addc.s: xc16x add with carry tests"
+    set x 0
+
+    gas_start "addc.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 1001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 1809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 180D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 16F03400\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 16F05634\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 12F08723\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 14F08723\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_addcb {} {
+    set testname "addcb.s: xc16x add byte with carry tests"
+    set x 0
+
+    gas_start "addcb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 1102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 1909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 190D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 17F00200\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 17F02300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 15F08723\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 6] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_sub {} {
+    set testname "sub.s: xc16x sub tests"
+    set x 0
+
+    gas_start "sub.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 2001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 2809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 280D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 2801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 26F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 22F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 24F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_subb {} {
+    set testname "subb.s: xc16x sub byte tests"
+    set x 0
+
+    gas_start "subb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 2102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 2909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 290D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 2901\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 27F04300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 23F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 25F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_subc {} {
+    set testname "subc.s: xc16x sub with carry tests"
+    set x 0
+
+    gas_start "subc.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 3001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 3809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 380D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 3802\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 36F04300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 32F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 34F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_subcb {} {
+    set testname "subcb.s: xc16x sub byte with carry tests"
+    set x 0
+
+    gas_start "subcb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 3102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 3909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 390D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 3902\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 37F04300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 33F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 35F04376\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_and {} {
+    set testname "and.s: xc16x and tests"
+    set x 0
+
+    gas_start "and.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 6001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 6809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 680D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 6803\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 66F0BEFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 62F03002\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 64F02003\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_andb {} {
+    set testname "andb.s: xc16x and byte tests"
+    set x 0
+
+    gas_start "andb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 6102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 6909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 690D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 6903\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 67F0BE00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 63F03002\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 65F02003\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_or {} {
+    set testname "or.s: xc16x or tests"
+    set x 0
+
+    gas_start "or.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 7001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 7809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 780D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 7803\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 76F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 72F03645\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 74F03645\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_xor {} {
+    set testname "xor.s: xc16x xor tests"
+    set x 0
+
+    gas_start "xor.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 5001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 5809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 580D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 5803\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 56F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 52F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 54F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_xorb {} {
+    set testname "xorb.s: xc16x xorb tests"
+    set x 0
+
+    gas_start "xorb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 5102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 5909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 590D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 5903\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 57F03400\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 53F00324\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 55F00324\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+    
+}
+
+proc do_xc16x_mov {} {
+    set testname "mov.s: xc16x mov tests"
+    set x 0
+
+    gas_start "mov.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 F001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 E6F00200\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 E6F0BEFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a A801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 9801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e B810\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 8810\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 C801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 D801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 E801\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 D400CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c C400CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 8400CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 9400CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0028 F2F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 002c F6F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 16] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_movb {} {
+    set testname "movb.s: xc16x movb tests"
+    set x 0
+
+    gas_start "movb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 F3F00000\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 E7F01200\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 B4020000\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 9902\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 8902\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 E932\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 C932\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 D923\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 E923\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 F4033412\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c E4033412\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 A4033412\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 A403FFEE\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0028 B4033412\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 002c F3F01200\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0030 F7F01200\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 16] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_movbs {} {
+    set testname "movbs.s: xc16x mov byte tests"
+    set x 0
+
+    gas_start "movbs.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 D020\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 D2F0FF00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 D5F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 3] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_movbz {} {
+    set testname "movbz.s: xc16x movbz tests"
+    set x 0
+
+    gas_start "movbz.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 C002\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 C2F0DD23\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 C5F02300\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 3] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_pushpop {} {
+    set testname "pushpop.s: xc16x push/pop tests"
+    set x 0
+
+    gas_start "pushpop.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 FCF0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 ECF0\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_shlrol {} {
+    set testname "shlrol.s: xc16x shift and rotate tests"
+    set x 0
+
+    gas_start "shlrol.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 4C01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 5C00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 6C01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 7C00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 0C01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 1C00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 2C01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 3C00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 AC01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 BC00\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 10] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_neg {} {
+    set testname "neg.s: xc16x neg tests"
+    set x 0
+
+    gas_start "neg.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 8100\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 A100\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+proc do_xc16x_mul {} {
+    set testname "mul.s: xc16x multiply tests"
+    set x 0
+
+    gas_start "mul.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 0B01\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 1B01\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_div {} {
+    set testname "div.s: xc16x division tests"
+    set x 0
+
+    gas_start "div.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 4B00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 6B00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 7B00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 5B00\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 4] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_jmpa {} {
+    set testname "jmpa.s: xc16x jump absolute test"
+    set x 0
+
+    gas_start "jmpa.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 EA00AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 EA20AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 EA30AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c EA40AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 EA50AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 EA60AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 EA70AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c EA80AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 EA90AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 EA20AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0028 EA30AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 002c EA80AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0030 EAF0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0034 EA90AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0038 EAE0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 003c EAB0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0040 EAD0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0044 EAA0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0048 EA10AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 19] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_jmpi {} {
+    set testname "jmpi.s: xc16x jmp immidiate tests "
+    set x 0
+
+    gas_start "jmpi.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 9C07\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 9C27\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 9C37\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 9C47\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 9C57\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 9C67\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 9C77\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 9C87\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 9C97\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 9C27\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 9C37\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 9C87\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 9CF7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001a 9C97\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c 9CE7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001e 9CB7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 9CD7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0022 9CA7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 9C17\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 19] then { pass $testname } else { fail $testname }
+}
+
+
+proc do_xc16x_jmpr {} {
+    set testname "jmpr.s: xc16x jump relative tests"
+    set x 0
+
+    gas_start "jmpr.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 0DFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 2DFE\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 3DFD\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 4DFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 5DFB\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 6DFA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 7DF9\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e 8DF8\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 9DF7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 2DF6\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 3DF5\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 8DF4\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 FDF3\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001a 9DF2\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c EDF1\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001e BDF0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 DDEF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0022 ADEE\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 1DED\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0026 CDEC\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 20] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_syscontrol1 {} {
+    set testname "syscontrol1.s: xc16x system control insrutions tests"
+    set x 0
+
+    gas_start "syscontrol1.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 B748B7B7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 8C00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 87788787\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a 97689797\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e A758A7A7\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 A55AA5A5\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 857A8585\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001a B54AB5B5\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 8] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_syscontrol2 {} {
+    set testname "syscontrol2.s: xc16x syscontrol2 tests"
+    set x 0
+
+    gas_start "syscontrol2.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 D1B0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 D1A0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 D190\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 D180\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 D130\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a D120\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c D110\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e D100\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 DC75\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 D770FF03\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 DCF5\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 D7F0FF03\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c DC35\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001e D7300100\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0022 DCB5\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 D7B00100\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 16] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_cpl {} {
+    set testname "cpl.s: xc16x compliment tests"
+    set x 0
+
+    gas_start "cpl.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 9100\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 B100\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_cmp {} {
+    set testname "cmp.s: xc16x misc tests"
+    set x 0
+
+    gas_start "cmp.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 4001\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 4809\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 480D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 4803\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 46F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 42F05234\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 6] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_cmpb {} {
+    set testname "cmpb.s: xc16x cmp byte tests"
+    set x 0
+
+    gas_start "cmpb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 4102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 4909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 490D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 4903\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 47F02200\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 43F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 6] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_cmpi {} {
+    set testname "cmpi.s: xc16x cmpi tests"
+    set x 0
+
+    gas_start "cmpi.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 A0F0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 A6F0CBFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 A2F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000a B0F0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c B6F0CBFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 B2F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 80F0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 86F0CBFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001a 82F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001e 90F0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 96F0CBFC\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 92F0CBFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 12] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_calli {} {
+    set testname "calli.s: xc16x call tests"
+    set x 0
+
+    gas_start "calli.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 AB01\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0002 AB21\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0004 AB31\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0006 AB41\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0008 AB51\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 000a AB61\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 000c AB71\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000e AB81\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 AB91\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0012 AB21\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 AB31\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0016 AB81\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 ABF1\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001a AB91\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c ABE1\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001e ABB1\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 ABD1\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0022 AB11\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 ABC1\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 19] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_calla {} {
+    set testname "calla.s: xc16x call tests"
+    set x 0
+
+    gas_start "calla.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 CA00AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 CA20AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 CA30AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c CA40AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 CA50AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 CA60AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 CA70AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 001c CA80AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0020 CA90AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0024 CA20AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0028 CA30AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 002c CA80AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0030 CAF0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0034 CA90AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0038 CAE0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 003c CAB0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0040 CAD0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0044 CAA0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 0048 CA10AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+    	    -re " +\[0-9\]+ 004c CAC0AAAA\[^\n\]*\n"   { set x [expr $x+1] }
+    	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 20] then { pass $testname } else { fail $testname }
+}
+
+
+proc do_xc16x_bit {} {
+    set testname "bit.s: xc16x bit manipulation tests"
+    set x 0
+
+    gas_start "bit.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 1EF0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 1FF0\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 4AF0F012\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 3AF0F023\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 6AF0F041\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 5AF0F021\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0014 7AF0F021\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0018 2AF0F021\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 8] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_bfldl {} {
+    set testname "bfldl.s: xc16x bitwise modify masked data tests"
+    set x 0
+
+    gas_start "bfldl.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 0AF0870E\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 1AF00EFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_ret {} {
+    set testname "ret.s: xc16x ret tests"
+    set x 0
+
+    gas_start "ret.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 CB00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 FB88\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 DB00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 EBF5\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 4] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_trap {} {
+    set testname "trap.s: xc16x add/sub tests"
+    set x 0
+
+    gas_start "trap.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 9B04\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 1] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_orb {} {
+    set testname "orb.s: xc16x or byte instructions tests"
+    set x 0
+
+    gas_start "orb.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 7102\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 7909\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 790D\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0006 7903\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0008 77F02300\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 000c 73F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0010 75F03402\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 7] then { pass $testname } else { fail $testname }
+}
+
+
+proc do_xc16x_prior {} {
+    set testname "prior.s: Determine no shift cycles tests"
+    set x 0
+
+    gas_start "prior.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 2B01\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 1] then { pass $testname } else { fail $testname }
+}
+
+proc do_xc16x_nop {} {
+    set testname "nop.s: no operation nop tests"
+    set x 0
+
+    gas_start "nop.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 CC00\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0002 CC00\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+
+proc do_xc16x_scxt {} {
+    set testname "scxt.s: push direct word to system stack tests"
+    set x 0
+
+    gas_start "scxt.s" "-al"
+
+    # Check each instruction bit pattern to verify it got
+    # assembled correctly.
+    while 1 {
+	expect {
+	    -re " +\[0-9\]+ 0000 C6F0FFFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    -re " +\[0-9\]+ 0004 D6F0FFFF\[^\n\]*\n"   { set x [expr $x+1] }
+	    timeout 				{ perror "timeout\n; break }
+	    eof					{ break }
+	}
+    }
+
+    # This was intended to do any cleanup necessary.  It kinda looks like it
+    # isn't needed, but just in case, please keep it in for now.
+    gas_finish
+
+    # Did we find what we were looking for?  If not, flunk it.
+    if [expr $x == 2] then { pass $testname } else { fail $testname }
+}
+
+
+if [istarget xc16x*-*-*] then {
+    # Test the basic xc16x instruction parser
+    do_xc16x_add
+    do_xc16x_addb
+    do_xc16x_addc
+    do_xc16x_addcb
+    do_xc16x_sub
+    do_xc16x_subb
+    do_xc16x_subc
+    do_xc16x_subcb
+    do_xc16x_and
+    do_xc16x_andb
+    do_xc16x_or
+    do_xc16x_xor
+    do_xc16x_xorb
+    do_xc16x_mov
+    do_xc16x_movb
+    do_xc16x_movbs
+    do_xc16x_movbz
+    do_xc16x_shlrol
+    do_xc16x_neg
+    do_xc16x_mul
+    do_xc16x_div
+    do_xc16x_jmpa
+    do_xc16x_jmpi
+    do_xc16x_jmpr
+    do_xc16x_syscontrol1
+    do_xc16x_syscontrol2
+    do_xc16x_cpl
+    do_xc16x_cmp
+    do_xc16x_cmpb
+    do_xc16x_cmpi
+    do_xc16x_calla
+    do_xc16x_calli
+    do_xc16x_bit
+    do_xc16x_bfldl
+    do_xc16x_ret
+    do_xc16x_trap
+    do_xc16x_orb
+    do_xc16x_prior
+    do_xc16x_nop
+    do_xc16x_scxt
+    
+}
diff --git a/gas/testsuite/gas/xc16x/xor.s b/gas/testsuite/gas/xc16x/xor.s
new file mode 100644
index 000000000000..bdc83d73e237
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/xor.s
@@ -0,0 +1,10 @@
+       .section .text
+       .global _fun
+xc16x_or:
+	xor  r0,r1
+	xor  r0,[r1]
+	xor  r0,[r1+]
+	xor  r0,#3
+	xor  r0,#0x0234
+	xor  r0,0x0234
+	xor  0x0234,r0
diff --git a/gas/testsuite/gas/xc16x/xorb.s b/gas/testsuite/gas/xc16x/xorb.s
new file mode 100644
index 000000000000..faf4a7609a75
--- /dev/null
+++ b/gas/testsuite/gas/xc16x/xorb.s
@@ -0,0 +1,10 @@
+       .section .text
+       .global _fun
+xc16x_xorb:
+	xorb  rl0,rl1
+	xorb  rl0,[r1]
+	xorb  rl0,[r1+]
+	xorb  rl0,#3
+	xorb  rl0,#0x34
+	xorb  rl0,0x2403
+	xorb  0x2403,rl0
diff --git a/gas/testsuite/gas/xtensa/all.exp b/gas/testsuite/gas/xtensa/all.exp
index e01c4a395f0b..89b3cdf1e518 100644
--- a/gas/testsuite/gas/xtensa/all.exp
+++ b/gas/testsuite/gas/xtensa/all.exp
@@ -9,7 +9,7 @@ if [istarget xtensa*-*-*] then {
     set x1 0
     while 1 {
         expect {
-            -re ":4: Error:.*too large"           { set x1 1 }
+            -re ":4: Error:.*out of range"      { set x1 1 }
             timeout                             { perror "timeout\n"; break }
             eof                                 { break }
         }
@@ -47,19 +47,7 @@ if [istarget xtensa*-*-*] then {
     objdump_finish
     if [all_ones $x1] then { pass $testname } else { fail $testname }
 
-    gas_test "entry_align.s" "" "" "Xtensa autoalign entry"
-    set testname "entry_align.s: autoalign entry"
-    objdump_start_no_subdir "a.out" "-d -j .text"
-    set x1 0
-    while 1 {
-	expect {
-	    -re "^.*4:.*entry" { set x1 1 }
-	    timeout            { perror "timeout\n"; break }
-	    eof                { break }
-	}
-    }
-    objdump_finish
-    if [all_ones $x1] then { pass $testname } else { fail $testname }
+    gas_test_error "entry_align.s" "" "Xtensa entry alignment error"
 
     gas_test "loop_misalign.s" "" "" "Xtensa Loop misalignment"
     set testname "loop_misalign.s: Force loop misalignment"
@@ -90,9 +78,9 @@ if [istarget xtensa*-*-*] then {
     objdump_finish
     if [all_ones $x1] then { pass $testname } else { fail $testname }
 
-
+    run_dump_test "short_branch_offset"
 }
 
 if [info exists errorInfo] then {
     unset errorInfo
-    }
+}
diff --git a/gas/testsuite/gas/xtensa/entry_misalign2.s b/gas/testsuite/gas/xtensa/entry_misalign2.s
index 5d48b6c59b94..5a57815ab418 100644
--- a/gas/testsuite/gas/xtensa/entry_misalign2.s
+++ b/gas/testsuite/gas/xtensa/entry_misalign2.s
@@ -1,6 +1,6 @@
-	.begin no-generics
+	.begin no-transform
 	nop.n
 l4:	
 	entry a5,16
 	mov.n a4,a5
-	.end no-generics
+	.end no-transform
diff --git a/gas/testsuite/gas/xtensa/short_branch_offset.d b/gas/testsuite/gas/xtensa/short_branch_offset.d
new file mode 100644
index 000000000000..0d95a7ca37a3
--- /dev/null
+++ b/gas/testsuite/gas/xtensa/short_branch_offset.d
@@ -0,0 +1,34 @@
+# as: --no-target-align
+# objdump: -d
+
+# Test that a short branch with a target just barely out of range does
+# not crash the assembler.
+
+.*: +file format elf32-xtensa-.*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	.*        	bnez	a2, 0x45
+   3:	.*        	nop
+   6:	.*        	nop
+   9:	.*        	nop
+   c:	.*        	nop
+   f:	.*        	nop
+  12:	.*        	nop
+  15:	.*        	nop
+  18:	.*        	nop
+  1b:	.*        	nop
+  1e:	.*        	nop
+  21:	.*        	nop
+  24:	.*        	nop
+  27:	.*        	nop
+  2a:	.*        	nop
+  2d:	.*        	nop
+  30:	.*        	nop
+  33:	.*        	nop
+  36:	.*        	nop
+  39:	.*        	nop
+  3c:	.*        	nop
+  3f:	.*        	nop
+  42:	.*        	nop
diff --git a/gas/testsuite/gas/xtensa/short_branch_offset.s b/gas/testsuite/gas/xtensa/short_branch_offset.s
new file mode 100644
index 000000000000..df2489feb620
--- /dev/null
+++ b/gas/testsuite/gas/xtensa/short_branch_offset.s
@@ -0,0 +1,24 @@
+	bnez.n	a2, .Lplus68
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+	_nop
+.Lplus68:
diff --git a/gas/testsuite/gas/z80/offset.d b/gas/testsuite/gas/z80/offset.d
new file mode 100644
index 000000000000..41499b1e3367
--- /dev/null
+++ b/gas/testsuite/gas/z80/offset.d
@@ -0,0 +1,24 @@
+#objdump: -d
+#name: instructions with offsets
+
+.*: .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+
+[ 	]+0:[ 	]+18 7e[ 	]+jr 0x0080
+[ 	]+2:[ 	]+dd 34 05[ 	]+inc \(ix\+5\)
+[ 	]+5:[ 	]+fd 35 ff[ 	]+dec \(iy\+?-1\)
+[ 	]+8:[ 	]+dd 7e 80[ 	]+ld a,\(ix\+?-128\)
+[ 	]+b:[ 	]+fd 77 7f[ 	]+ld \(iy\+127\),a
+[ 	]+e:[ 	]+10 f0[ 	]+djnz 0x0000
+[ 	]+10:[ 	]+28 02[ 	]+jr z,0x0014
+[ 	]+12:[ 	]+38 04[ 	]+jr c,0x0018
+[ 	]+14:[ 	]+20 02[ 	]+jr nz,0x0018
+[ 	]+16:[ 	]+30 fc[ 	]+jr nc,0x0014
+[ 	]+18:[ 	]+dd 36 22 09[ 	]+ld \(ix\+34\),0x09
+[ 	]+1c:[ 	]+fd 36 de f7[ 	]+ld \(iy\+?-34\),0xf7
+[ 	]+20:[ 	]+dd cb 37 1e[ 	]+rr \(ix\+55\)
+[ 	]+24:[ 	]+fd cb c9 16[ 	]+rl \(iy\+?-55\)
+#pass
diff --git a/gas/testsuite/gas/z80/offset.s b/gas/testsuite/gas/z80/offset.s
new file mode 100644
index 000000000000..6e4b33fc829e
--- /dev/null
+++ b/gas/testsuite/gas/z80/offset.s
@@ -0,0 +1,23 @@
+;;;  various instructions involving offsets
+
+	.section .text
+	.org 0
+10:
+	jr 1f
+	inc (ix+5)
+	dec (iy-1)
+	ld a,(ix-128)
+	ld (iy+127),a
+	djnz 10b
+	jr z,2f
+	jr c,3f
+2:
+	jr nz,3f
+	jr nc,2b
+3:
+	ld (ix+34),9
+	ld (iy-34),-9
+	rr (ix+55)
+	rl (iy-55)
+	.balign 0x80
+1:	
diff --git a/gas/testsuite/gas/z80/quotes.d b/gas/testsuite/gas/z80/quotes.d
new file mode 100644
index 000000000000..1915f51728fc
--- /dev/null
+++ b/gas/testsuite/gas/z80/quotes.d
@@ -0,0 +1,9 @@
+#objdump: -s -j .data
+#name: quotes
+
+.*:.*
+
+Contents of section .data:
+ 0000 73696e67 6c653a27 646f7562 6c653a22[ 	]+................
+ 0010 00657363 6170653a 5c5c08fe 3a[ 	]+................
+#pass
\ No newline at end of file
diff --git a/gas/testsuite/gas/z80/quotes.s b/gas/testsuite/gas/z80/quotes.s
new file mode 100644
index 000000000000..1b882bc3292e
--- /dev/null
+++ b/gas/testsuite/gas/z80/quotes.s
@@ -0,0 +1,11 @@
+	;; test the parsing of strings and character constants
+	section .data
+laf:	
+	defb "single:'"
+	defb 'double:"',laf
+	defb 'escape:\\'
+
+	ex af,af'
+af0:	
+	cp '9'+1
+
diff --git a/gas/testsuite/gas/z80/redef.d b/gas/testsuite/gas/z80/redef.d
new file mode 100644
index 000000000000..fed19987c3e2
--- /dev/null
+++ b/gas/testsuite/gas/z80/redef.d
@@ -0,0 +1,8 @@
+#objdump: -s -j .data
+#name: .equ redefinitions
+
+.*: .*
+
+Contents of section .data:
+ 0000 00000000 0[04]00000[04] 0[08]00000[08] 0[0c]00000[0c][ 	]+................[ 	]*
+#pass
diff --git a/gas/testsuite/gas/z80/redef.s b/gas/testsuite/gas/z80/redef.s
new file mode 100644
index 000000000000..eda6a69a8f35
--- /dev/null
+++ b/gas/testsuite/gas/z80/redef.s
@@ -0,0 +1,11 @@
+ .data
+_start:
+x: defl .-_start
+ .long x
+ .balign 4
+x: defl .-_start
+ .long x
+x: defl .-_start
+ .long x
+x: defl .-_start
+ .long x
diff --git a/gas/testsuite/gas/z80/suffix.d b/gas/testsuite/gas/z80/suffix.d
new file mode 100644
index 000000000000..c3562758a0bb
--- /dev/null
+++ b/gas/testsuite/gas/z80/suffix.d
@@ -0,0 +1,15 @@
+#objdump: -s -r -j .data
+#name: suffixes
+
+.*:.*
+
+RELOCATION RECORDS FOR \[.data\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE[ 	]*
+00000002[ 	]+r_imm16[ 	]+.data[ 	]*
+00000014[ 	]+r_imm16[ 	]+.data[ 	]*
+
+
+Contents of section .data:
+ 0000 0a000000 08020802 08020802 f203f203[ 	]+................[ 	]*
+ 0010 10b010b0 1600[ 	]+......[ 	]*
+#pass
diff --git a/gas/testsuite/gas/z80/suffix.s b/gas/testsuite/gas/z80/suffix.s
new file mode 100644
index 000000000000..5cf298b8505a
--- /dev/null
+++ b/gas/testsuite/gas/z80/suffix.s
@@ -0,0 +1,13 @@
+	.section .data
+1010:	.word 1010B
+	.word 1010b
+	.word 1010Q
+	.word 1010q
+	.word 1010O
+	.word 1010o
+	.word 1010D
+	.word 1010d
+	.word 0B010H
+	.word 0b010h
+	.word 1010f
+1010:
diff --git a/gas/testsuite/gas/z80/z80.exp b/gas/testsuite/gas/z80/z80.exp
new file mode 100644
index 000000000000..cae83f160dba
--- /dev/null
+++ b/gas/testsuite/gas/z80/z80.exp
@@ -0,0 +1,12 @@
+# run tests for target Z80.
+
+if [istarget z80-*-*] then {
+# test redefinitions
+    run_dump_test "redef"
+# test parsing of " and '
+    run_dump_test "quotes"
+# test suffixes
+    run_dump_test "suffix"
+# test assembling and disassembling instructions involving offsets
+    run_dump_test "offset"
+}
diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp
index fec27789488c..827e22f70f07 100644
--- a/gas/testsuite/lib/gas-defs.exp
+++ b/gas/testsuite/lib/gas-defs.exp
@@ -1,5 +1,5 @@
-# Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003
-# Free Software Foundation, Inc.
+# Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+# 2004, 2005 Free Software Foundation, Inc.
 
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -13,7 +13,7 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
 
 # Please email any bugs, comments, and/or additions to this file to:
 # dejagnu@gnu.org
@@ -45,7 +45,7 @@ proc gas_run { prog as_opts redir } {
     catch "exec $srcdir/lib/run $AS $ASFLAGS $as_opts $srcdir/$subdir/$prog $redir" comp_output
     set comp_output [prune_warnings $comp_output]
     verbose "output was $comp_output"
-    return [list $comp_output ""];
+    return [list $comp_output ""]
 }
 
 proc all_ones { args } {
@@ -197,6 +197,7 @@ proc is_elf_format {} {
 	 && ![istarget *-*-irix5*] \
 	 && ![istarget *-*-irix6*] \
 	 && ![istarget *-*-netbsd*] \
+	 && ![istarget *-*-openbsd*] \
 	 && ![istarget *-*-solaris2*] } {
 	return 0
     }
@@ -217,9 +218,39 @@ proc is_elf_format {} {
 	     || [istarget ns32k-*-netbsd*]) } {
     	return 0
     }
+
+    if { [istarget arm-*-openbsd*] \
+	 || [istarget i386-*-openbsd\[0-2\].*] \
+	 || [istarget i386-*-openbsd3.\[0-3\]] \
+	 || [istarget m68*-*-openbsd*] \
+	 || [istarget ns32k-*-openbsd*] \
+	 || [istarget sparc-*-openbsd\[0-2\].*] \
+	 || [istarget sparc-*-openbsd3.\[0-1\]] \
+	 || [istarget vax-*-openbsd*] } {
+	return 0
+    }
+
     return 1
 }
 
+# run_dump_tests TESTCASES EXTRA_OPTIONS
+# Wrapper for run_dump_test, which is suitable for invoking as
+#   run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+# EXTRA_OPTIONS are passed down to run_dump_test.  Honors runtest_file_p.
+# Body cribbed from dg-runtest.
+
+proc run_dump_tests { testcases {extra_options {}} } {
+    global runtests
+
+    foreach testcase $testcases {
+        # If testing specific files and this isn't one of them, skip it.
+        if ![runtest_file_p $runtests $testcase] {
+            continue
+        }
+        run_dump_test [file rootname [file tail $testcase]] $extra_options
+    }
+}
+
 
 # run_dump_test FILE (optional:) EXTRA_OPTIONS
 #
@@ -242,8 +273,10 @@ proc is_elf_format {} {
 # OPTION is the name of some option, like "name" or "objdump", and
 # VALUE is OPTION's value.  The valid options are described below.
 # Whitespace is ignored everywhere, except within VALUE.  The option
-# list ends with the first line that doesn't match the above syntax
-# (hmm, not great for error detection).
+# list ends with the first line that doesn't match the above syntax.
+# However, a line within the options that begins with a #, but doesn't
+# have a recognizable option name followed by a colon, is considered a
+# comment and entirely ignored.
 #
 # The optional EXTRA_OPTIONS argument to `run_dump_test' is a list of
 # two-element lists.  The first element of each is an option name, and
@@ -279,11 +312,46 @@ proc is_elf_format {} {
 #	Assemble the file SOURCE.s.  If omitted, this defaults to FILE.s.
 #       This is useful if several .d files want to share a .s file.
 #
+#   target: GLOBS...
+#       Run this test only on a specified list of targets.  More precisely,
+#       each glob in the space-separated list is passed to "istarget"; if
+#       it evaluates true for any of them, the test will be run, otherwise
+#       it will be marked unsupported.
+#
+#   not-target: GLOBS...
+#       Do not run this test on a specified list of targets.  Again,
+#       the each glob in the space-separated list is passed to
+#       "istarget", and the test is run if it evaluates *false* for
+#       *all* of them.  Otherwise it will be marked unsupported.
+#
+#   skip: GLOBS...
+#   not-skip: GLOBS...
+#       These are exactly the same as "not-target" and "target",
+#       respectively, except that they do nothing at all if the check
+#       fails.  They should only be used in groups, to construct a single
+#       test which is run on all targets but with variant options or
+#       expected output on some targets.  (For example, see
+#       gas/arm/inst.d and gas/arm/wince_inst.d.)
+#
 #   error: REGEX
 #	An error with message matching REGEX must be emitted for the test
 #	to pass.  The PROG, objdump, nm and objcopy options have no
 #	meaning and need not supplied if this is present.
 #
+#   warning: REGEX
+#	Expect a gas warning matching REGEX.  It is an error to issue
+#	both "error" and "warning".
+#
+#   stderr: FILE
+#       FILE contains regexp lines to be matched against the diagnostic
+#       output of the assembler.  This does not preclude the use of
+#       PROG, nm, objdump, or objcopy.
+#
+#   error-output: FILE
+#       Means the same as 'stderr', but also indicates that the assembler
+#       is expected to exit unsuccessfully (therefore PROG, objdump, nm,
+#       and objcopy have no meaning and should not be supplied).
+#
 # Each option may occur at most once.
 #
 # After the option lines come regexp lines.  `run_dump_test' calls
@@ -320,6 +388,12 @@ proc run_dump_test { name {extra_options {}} } {
     set opts(source) {}
     set opts(stderr) {}
     set opts(error) {}
+    set opts(error-output) {}
+    set opts(warning) {}
+    set opts(target) {}
+    set opts(not-target) {}
+    set opts(skip) {}
+    set opts(not-skip) {}
 
     foreach i $opt_array {
 	set opt_name [lindex $i 0]
@@ -353,79 +427,160 @@ proc run_dump_test { name {extra_options {}} } {
 	append opts($opt_name) $opt_val
     }
 
-    if {$opts(PROG) != ""} {
-	switch -- $opts(PROG) {
-	    objdump
-		{ set program objdump }
-	    nm
-		{ set program nm }
-	    objcopy
-		{ set program objcopy }
-	    readelf
-		{ set program readelf }
-	    default
-		{ perror "unrecognized program option $opts(PROG) in $file.d"
-		  unresolved $subdir/$name
-		  return }
-	}
-    } elseif { $opts(error) != "" } {
-	# It's meaningless to require an output-testing method when we
-	# expect an error.  For simplicity, we fake an arbitrary method.
-	set program "nm"
+    if { $opts(name) == "" } {
+	set testname "$subdir/$name"
     } else {
-	# Guess which program to run, by seeing which option was specified.
-	set program ""
-	foreach p {objdump objcopy nm readelf} {
-	    if {$opts($p) != ""} {
-		if {$program != ""} {
-		    perror "ambiguous dump program in $file.d"
-		    unresolved $subdir/$name
-		    return
-		} else {
-		    set program $p
+	set testname $opts(name)
+    }
+    verbose "Testing $testname"
+
+    if { (($opts(warning) != "") && ($opts(error) != "")) \
+	 || (($opts(warning) != "") && ($opts(stderr) != "")) \
+	 || (($opts(error-output) != "") && ($opts(stderr) != "")) \
+	 || (($opts(error-output) != "") && ($opts(error) != "")) \
+	 || (($opts(error-output) != "") && ($opts(warning) != "")) } {
+	perror "$testname: bad mix of stderr, error-output, error, and warning test-directives"
+	unresolved $testname
+	return
+    }
+    if { $opts(error-output) != "" } then {
+	set opts(stderr) $opts(error-output)
+    }
+
+    set program ""
+    # It's meaningless to require an output-testing method when we
+    # expect an error.
+    if { $opts(error) == "" && $opts(error-output) == "" } {
+	if {$opts(PROG) != ""} {
+	    switch -- $opts(PROG) {
+		objdump	{ set program objdump }
+		nm	{ set program nm }
+		objcopy	{ set program objcopy }
+		readelf	{ set program readelf }
+		default	{
+		    perror "unrecognized program option $opts(PROG) in $file.d"
+		    unresolved $testname
+		    return }
+	    }
+	} else {
+	    # Guess which program to run, by seeing which option was specified.
+	    foreach p {objdump objcopy nm readelf} {
+		if {$opts($p) != ""} {
+		    if {$program != ""} {
+			perror "ambiguous dump program in $file.d"
+			unresolved $testname
+			return
+		    } else {
+			set program $p
+		    }
 		}
 	    }
 	}
-	if {$program == ""} {
+	if { $program == "" && $opts(warning) == "" } {
 	    perror "dump program unspecified in $file.d"
-	    unresolved $subdir/$name
+	    unresolved $testname
 	    return
 	}
     }
 
-    set progopts1 $opts($program)
-    eval set progopts \$[string toupper $program]FLAGS
-    eval set binary \$[string toupper $program]
-    if { $opts(name) == "" } {
-	set testname "$subdir/$name"
-    } else {
-	set testname $opts(name)
+    # Handle skipping the test on specified targets.
+    # You can have both skip/not-skip and target/not-target, but you can't
+    # have both skip and not-skip, or target and not-target, in the same file.
+    if { $opts(skip) != "" } then {
+	if { $opts(not-skip) != "" } then {
+	    perror "$testname: mixing skip and not-skip directives is invalid"
+	    unresolved $testname
+	    return
+	}
+	foreach glob $opts(skip) {
+	    if {[istarget $glob]} { return }
+	}
+    }
+    if { $opts(not-skip) != "" } then {
+	set skip 1
+	foreach glob $opts(not-skip) {
+	    if {[istarget $glob]} { 
+		set skip 0
+		break
+	    }
+	}
+	if {$skip} { return }
+    }
+    if { $opts(target) != "" } then {
+	if { $opts(not-target) != "" } then {
+	    perror "$testname: mixing target and not-target directives is invalid"
+	    unresolved $testname
+	    return
+	}
+	set skip 1
+	foreach glob $opts(target) {
+	    if {[istarget $glob]} { 
+		set skip 0
+		break
+	    }
+	}
+	if {$skip} { 
+	    unsupported $testname
+	    return 
+	}
+    }
+    if { $opts(not-target) != "" } then {
+	foreach glob $opts(not-target) {
+	    if {[istarget $glob]} {
+		unsupported $testname
+		return 
+	    }
+	}
     }
 
+
     if { $opts(source) == "" } {
 	set sourcefile ${file}.s
     } else {
 	set sourcefile $srcdir/$subdir/$opts(source)
     }
 
-    send_log "$AS $ASFLAGS $opts(as) -o dump.o $sourcefile\n"
-    catch "exec $srcdir/lib/run $AS $ASFLAGS $opts(as) -o dump.o $sourcefile" comp_output
+    set cmd "$srcdir/lib/run $AS $ASFLAGS $opts(as) -o dump.o $sourcefile"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
     set comp_output [prune_warnings $comp_output]
 
-    if { ![string match "" $comp_output] || $opts(stderr) != "" } then {
-	if { $opts(stderr) == "" }  then {
-	    send_log "$comp_output\n"
-	    verbose "$comp_output" 3
+    set expmsg $opts(error)
+    if { $opts(warning) != "" } {
+	set expmsg $opts(warning)
+    }
+    if { $cmdret != 0 || $comp_output != "" || $expmsg != "" } then {
+	# If the executed program writes to stderr and stderr is not
+	# redirected, exec *always* returns failure, regardless of the
+	# program exit code.  Thankfully, we can retrieve the true
+	# return status from a special variable.  Redirection would
+	# cause a tcl-specific message to be appended, and we'd rather
+	# not deal with that if we can help it.
+	global errorCode
+	if { $cmdret != 0 && [lindex $errorCode 0] == "NONE" } {
+	    set cmdret 0
+	}
+
+	set exitstat "succeeded"
+	if { $cmdret != 0 } { set exitstat "failed" }
 
-	    if { $opts(error) != "" } {
-		verbose -log "failed with: <$comp_output>, expected: <$opts(error)>"
-		if [regexp $opts(error) $comp_output] {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	if { $opts(stderr) == "" }  then {
+	    if { [regexp $expmsg $comp_output] \
+		    && (($cmdret == 0) == ($opts(warning) != "")) } {
+		# We have the expected output from gas.
+		# Return if there's nothing more to do.
+		if { $opts(error) != "" || $program == "" } {
 		    pass $testname
 		    return
 		}
+	    } else {
+		verbose -log "$exitstat with: <$comp_output>, expected: <$expmsg>"
+
+		fail $testname
+		return
 	    }
-	    fail $testname
-	    return
 	} else {
 	    catch {write_file dump.stderr "$comp_output"} write_output
 	    if ![string match "" $write_output] then {
@@ -437,11 +592,10 @@ proc run_dump_test { name {extra_options {}} } {
 		return
 	    }
 	    set stderrfile $srcdir/$subdir/$opts(stderr)
-	    send_log "wrote pruned stderr to dump.stderr\n"
 	    verbose "wrote pruned stderr to dump.stderr" 3
 	    if { [regexp_diff "dump.stderr" "$stderrfile"] } then {
 		if { $opts(error) != "" } {
-		    verbose -log "failed with: <$comp_output>, expected: <$opts(error)>"
+		    verbose -log "$exitstat with: <$comp_output>, expected: <$opts(error)>"
 		    if [regexp $opts(error) $comp_output] {
 			pass $testname
 			return
@@ -450,10 +604,20 @@ proc run_dump_test { name {extra_options {}} } {
 		fail $testname
 		verbose "pruned stderr is [file_contents "dump.stderr"]" 2
 		return
+	    } elseif { $opts(error-output) != "" } then {
+		pass $testname
+		return
 	    }
 	}
     }
 
+    if { $program == "" } {
+	return
+    }
+    set progopts1 $opts($program)
+    eval set progopts \$[string toupper $program]FLAGS
+    eval set binary \$[string toupper $program]
+
     if { [which $binary] == 0 } {
 	untested $testname
 	return
@@ -509,15 +673,15 @@ proc slurp_options { file } {
     set ws  {[ 	]*}
     set nws {[^ 	]*}
     # whitespace is ignored anywhere except within the options list;
-    # option names are alphabetic only
-    set pat "^#${ws}(\[a-zA-Z\]*)$ws:${ws}(.*)$ws\$"
+    # option names are alphabetic plus dash
+    set pat "^#${ws}(\[a-zA-Z-\]*)$ws:${ws}(.*)$ws\$"
     while { [gets $f line] != -1 } {
 	set line [string trim $line]
 	# Whitespace here is space-tab.
 	if [regexp $pat $line xxx opt_name opt_val] {
 	    # match!
 	    lappend opt_array [list $opt_name $opt_val]
-	} else {
+	} elseif {![regexp "^#" $line ]} {
 	    break
 	}
     }
@@ -615,6 +779,7 @@ proc regexp_diff { file_1 file_2 } {
 	    } elseif [ string match "#..." $line_b ] {
 		if { [gets $file_b line_b] == $eof } {
 		    set end_2 1
+		    set diff_pass 1
 		    break
 		}
 		verbose "looking for \"^$line_b$\"" 3
diff --git a/gas/vmsconf.sh b/gas/vmsconf.sh
deleted file mode 100644
index 014538a154e6..000000000000
--- a/gas/vmsconf.sh
+++ /dev/null
@@ -1,128 +0,0 @@
-#!/bin/sh
-
-cat << 'EOF'
-$!make-gas.com
-$! Set the def dir to proper place for use in batch. Works for interactive to.
-$flnm = f$enviroment("PROCEDURE")     ! get current procedure name
-$set default 'f$parse(flnm,,,"DEVICE")''f$parse(flnm,,,"DIRECTORY")'
-$v = 'f$verify(0)'
-$!
-$!	Command file to build a GNU assembler on VMS
-$!
-$!	If you are using a version of GCC that supports global constants
-$!	you should remove the define="const=" from the gcc lines.
-$!
-$!	Caution:  Versions 1.38.1 and earlier had a bug in the handling of
-$!	some static constants. If you are using such a version of the
-$!	assembler, and you wish to compile without the "const=" hack,
-$!	you should first build this version *with* the "const="
-$!	definition, and then use that assembler to rebuild it without the
-$!	"const=" definition.  Failure to do this will result in an assembler
-$!	that will mung floating point constants.
-$!
-$!	Note: The version of gas shipped on the GCC VMS tapes has been patched
-$!	to fix the above mentioned bug.
-$!
-$	!The gcc-vms driver was modified to use `-1' quite some time ago,
-$	!so don't echo this text any more...
-$ !write sys$output "If this assembler is going to be used with GCC 1.n, you"
-$ !write sys$output "need to modify the driver to supply the -1 switch to gas."
-$ !write sys$output "This is required because of a small change in how global"
-$ !write sys$output "constant variables are handled.  Failure to include this"
-$ !write sys$output "will result in linker warning messages about mismatched
-$ !write sys$output "psect attributes."
-$!
-$ gas_host="vms"
-$ arch_indx = 1 + ((f$getsyi("CPU").ge.128).and.1)	! vax==1, alpha==2
-$ arch = f$element(arch_indx,"|","|VAX|Alpha|")
-$ if arch.eqs."VAX"
-$ then
-$  cpu_type="vax"
-$  obj_format="vms"
-$  atof="vax"
-$ else
-$  cpu_type="alpha"
-$  obj_format="evax"
-$  atof="ieee"
-$ endif
-$ emulation="generic"
-$!
-$	COPY	= "copy/noLog"
-$!
-$ C_DEFS :="""VMS"""
-$! C_DEFS :="""VMS""","""const="""
-$ C_INCLUDES	= "/Include=([],[.config],[-.include],[-.include.aout])"
-$ C_FLAGS	= "/noVerbose/Debug" + c_includes
-$!
-$!
-$ on error then  goto bail
-$ if f$search("[-.libiberty]liberty.olb").eqs.""
-$ then	@[-.libiberty]vmsbuild.com
-$	write sys$output "Now building gas."
-$ endif
-$ if "''p1'" .eqs. "LINK" then goto Link
-$!
-$!  This helps gcc 1.nn find the aout/* files.
-$!
-$ aout_dev = f$parse(flnm,,,"DEVICE")
-$ tmp = aout_dev - ":"
-$if f$trnlnm(tmp).nes."" then aout_dev = f$trnlnm(tmp)
-$ aout_dir = aout_dev+f$parse(flnm,,,"DIRECTORY")' -
-	- "GAS]" + "INCLUDE.AOUT.]" - "]["
-$assign 'aout_dir' aout/tran=conc
-$ opcode_dir = aout_dev+f$parse(flnm,,,"DIRECTORY")' -
-	- "GAS]" + "INCLUDE.OPCODE.]" - "]["
-$assign 'opcode_dir' opcode/tran=conc
-$!
-$ set verify
-$!
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]tc-'cpu_type'.obj [.config]tc-'cpu_type'.c
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]obj-'obj_format'.obj [.config]obj-'obj_format'.c
-$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]atof-'atof'.obj [.config]atof-'atof'.c
-EOF
-
-cfiles="`echo $* | sed -e 's/\.o/.c/g' -e 's!../\([^ /]*\)/\([^ /]*\.c\)![-.\1]\2!g'`"
-
-for cfile in $cfiles ; do
-  case $cfile in
-    "[-."*)
-	base=`echo $cfile | sed -e 's/\[.*\]//' -e 's/\.c$//'`
-	echo "\$ gcc 'c_flags'/Define=('C_DEFS')/Object=[]$base.obj $cfile"
-	;;
-    *)
-	echo "\$ gcc 'c_flags'/Define=('C_DEFS') $cfile"
-	;;
-  esac
-done
-
-cat << 'EOF'
-$link:
-$!'f$verify(0)'
-$ if f$trnlnm("IFILE$").nes."" then  close/noLog ifile$
-$ create gcc-as.opt
-!
-!	Linker options file for GNU assembler
-!
-$ open/Append ifile$ gcc-as.opt
-$ write ifile$ "tc-''cpu_type'.obj"
-$ write ifile$ "obj-''obj_format'.obj"
-$ write ifile$ "atof-''atof'.obj"
-$ COPY sys$input: ifile$:
-EOF
-
-for obj in $* ; do
-  # Change "foo.o" into "foo.obj".
-  echo ${obj}bj,- | sed 's!.*/!!g'
-done
-
-cat << 'EOF'
-[-.libiberty]liberty.olb/Lib
-gnu_cc:[000000]gcclib.olb/Lib,sys$library:vaxcrtl.olb/Lib
-! Tell linker exactly what psect attributes we want -- match VAXCRTL.
-psect_attr=ENVIRON,long,pic,ovr,rel,gbl,noshr,noexe,rd,wrt
-$ close ifile$
-$ set verify=(Proc,noImag)
-$ link/noMap/Exec=gcc-as.exe gcc-as.opt/Opt,version.opt/Opt
-$!
-$bail: exit $status + 0*f$verify(v)	!'f$verify(0)'
-EOF
diff --git a/gas/write.c b/gas/write.c
index 5acd6077844f..9186717c4f85 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -1,6 +1,6 @@
 /* write.c - emit .o file
    Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003
+   1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
    Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
@@ -17,8 +17,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 /* This thing should be set up to do byteordering correctly.  But...  */
 
@@ -71,13 +71,9 @@
 /* The PA needs this for PIC code generation.  */
 #define TC_VALIDATE_FIX_SUB(FIX) 1
 #else
-#ifdef BFD_ASSEMBLER
 #define TC_VALIDATE_FIX_SUB(FIX)		\
   ((FIX)->fx_r_type == BFD_RELOC_GPREL32	\
    || (FIX)->fx_r_type == BFD_RELOC_GPREL16)
-#else
-#define TC_VALIDATE_FIX_SUB(FIX) 0
-#endif
 #endif
 #endif
 
@@ -97,9 +93,8 @@
 #define MD_PCREL_FROM_SECTION(FIX, SEC) md_pcrel_from (FIX)
 #endif
 
-#ifndef WORKING_DOT_WORD
-extern const int md_short_jump_size;
-extern const int md_long_jump_size;
+#ifndef TC_FAKE_LABEL
+#define TC_FAKE_LABEL(NAME) (strcmp ((NAME), FAKE_LABEL_NAME) == 0)
 #endif
 
 /* Used to control final evaluation of expressions.  */
@@ -114,7 +109,6 @@ addressT dot_value;
 
 void print_fixup (fixS *);
 
-#ifdef BFD_ASSEMBLER
 static void renumber_sections (bfd *, asection *, PTR);
 
 /* We generally attach relocs to frag chains.  However, after we have
@@ -122,53 +116,18 @@ static void renumber_sections (bfd *, asection *, PTR);
    that must be attached to a segment.  This will include relocs added
    in md_estimate_size_for_relax, for example.  */
 static int frags_chained = 0;
-#endif
-
-#ifndef BFD_ASSEMBLER
-
-#ifndef MANY_SEGMENTS
-struct frag *text_frag_root;
-struct frag *data_frag_root;
-struct frag *bss_frag_root;
-
-struct frag *text_last_frag;	/* Last frag in segment.  */
-struct frag *data_last_frag;	/* Last frag in segment.  */
-static struct frag *bss_last_frag;	/* Last frag in segment.  */
-#endif
-
-#ifndef BFD
-static object_headers headers;
-#endif
-
-long string_byte_count;
-char *next_object_file_charP;	/* Tracks object file bytes.  */
-
-#ifndef OBJ_VMS
-int magic_number_for_object_file = DEFAULT_MAGIC_NUMBER_FOR_OBJECT_FILE;
-#endif
-
-#endif /* BFD_ASSEMBLER  */
 
 static int n_fixups;
 
-#ifdef BFD_ASSEMBLER
 #define RELOC_ENUM enum bfd_reloc_code_real
-#else
-#define RELOC_ENUM int
-#endif
 
 static fixS *fix_new_internal (fragS *, int where, int size,
 			       symbolS *add, symbolS *sub,
 			       offsetT offset, int pcrel,
 			       RELOC_ENUM r_type);
-#if defined (BFD_ASSEMBLER) || (!defined (BFD) && !defined (OBJ_VMS))
 static long fixup_segment (fixS *, segT);
-#endif
 static relax_addressT relax_align (relax_addressT addr, int align);
-#if defined (BFD_ASSEMBLER) || ! defined (BFD)
 static fragS *chain_frchains_together_1 (segT, struct frchain *);
-#endif
-#ifdef BFD_ASSEMBLER
 static void chain_frchains_together (bfd *, segT, PTR);
 static void cvt_frag_to_fill (segT, fragS *);
 static void adjust_reloc_syms (bfd *, asection *, PTR);
@@ -176,15 +135,7 @@ static void fix_segment (bfd *, asection *, PTR);
 static void write_relocs (bfd *, asection *, PTR);
 static void write_contents (bfd *, asection *, PTR);
 static void set_symtab (void);
-#endif
-#if defined (BFD_ASSEMBLER) || (! defined (BFD) && ! defined (OBJ_AOUT))
 static void merge_data_into_text (void);
-#endif
-#if ! defined (BFD_ASSEMBLER) && ! defined (BFD)
-static void cvt_frag_to_fill (object_headers *, segT, fragS *);
-static void remove_subsegs (frchainS *, int, fragS **, fragS **);
-static void relax_and_size_all_segments (void);
-#endif
 
 /* Create a fixS in obstack 'notes'.  */
 
@@ -219,9 +170,7 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
   fixP->fx_dot_value = dot_value;
   fixP->fx_pcrel = pcrel;
   fixP->fx_plt = 0;
-#if defined(NEED_FX_R_TYPE) || defined (BFD_ASSEMBLER)
   fixP->fx_r_type = r_type;
-#endif
   fixP->fx_im_disp = 0;
   fixP->fx_pcrel_adjust = 0;
   fixP->fx_bit_fixP = 0;
@@ -248,14 +197,12 @@ fix_new_internal (fragS *frag,		/* Which frag?  */
      time option.  xoxorich.  */
   {
 
-#ifdef BFD_ASSEMBLER
     fixS **seg_fix_rootP = (frags_chained
 			    ? &seg_info (now_seg)->fix_root
 			    : &frchain_now->fix_root);
     fixS **seg_fix_tailP = (frags_chained
 			    ? &seg_info (now_seg)->fix_tail
 			    : &frchain_now->fix_tail);
-#endif
 
 #ifdef REVERSE_SORT_RELOCS
 
@@ -335,16 +282,7 @@ fix_new_exp (fragS *frag,		/* Which frag?  */
     case O_symbol_rva:
       add = exp->X_add_symbol;
       off = exp->X_add_number;
-
-#if defined(BFD_ASSEMBLER)
       r_type = BFD_RELOC_RVA;
-#else
-#if defined(TC_RVA_RELOC)
-      r_type = TC_RVA_RELOC;
-#else
-      as_fatal (_("rva not supported"));
-#endif
-#endif
       break;
 
     case O_uminus:
@@ -374,11 +312,13 @@ fix_new_exp (fragS *frag,		/* Which frag?  */
 int
 generic_force_reloc (fixS *fix)
 {
-#ifdef BFD_ASSEMBLER
   if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT
       || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
     return 1;
-#endif
+
+  if (fix->fx_addsy == NULL)
+    return 0;
+
   return S_FORCE_RELOC (fix->fx_addsy, fix->fx_subsy == NULL);
 }
 
@@ -394,10 +334,6 @@ append (char **charPP, char *fromP, unsigned long length)
   *charPP += length;
 }
 
-#ifndef BFD_ASSEMBLER
-int section_alignment[SEG_MAXIMUM_ORDINAL];
-#endif
-
 /* This routine records the largest alignment seen for each segment.
    If the beginning of the segment is aligned on the worst-case
    boundary, all of the other alignments within it will work.  At
@@ -412,13 +348,9 @@ record_alignment (/* Segment to which alignment pertains.  */
 {
   if (seg == absolute_section)
     return;
-#ifdef BFD_ASSEMBLER
+
   if ((unsigned int) align > bfd_get_section_alignment (stdoutput, seg))
     bfd_set_section_alignment (stdoutput, seg, align);
-#else
-  if (align > section_alignment[(int) seg])
-    section_alignment[(int) seg] = align;
-#endif
 }
 
 int
@@ -426,15 +358,10 @@ get_recorded_alignment (segT seg)
 {
   if (seg == absolute_section)
     return 0;
-#ifdef BFD_ASSEMBLER
+
   return bfd_get_section_alignment (stdoutput, seg);
-#else
-  return section_alignment[(int) seg];
-#endif
 }
 
-#ifdef BFD_ASSEMBLER
-
 /* Reset the section indices after removing the gas created sections.  */
 
 static void
@@ -446,24 +373,17 @@ renumber_sections (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, PTR countparg)
   ++*countp;
 }
 
-#endif /* defined (BFD_ASSEMBLER)  */
-
-#if defined (BFD_ASSEMBLER) || ! defined (BFD)
-
 static fragS *
 chain_frchains_together_1 (segT section, struct frchain *frchp)
 {
   fragS dummy, *prev_frag = &dummy;
-#ifdef BFD_ASSEMBLER
   fixS fix_dummy, *prev_fix = &fix_dummy;
-#endif
 
   for (; frchp && frchp->frch_seg == section; frchp = frchp->frch_next)
     {
       prev_frag->fr_next = frchp->frch_root;
       prev_frag = frchp->frch_last;
       assert (prev_frag->fr_type != 0);
-#ifdef BFD_ASSEMBLER
       if (frchp->fix_root != (fixS *) NULL)
 	{
 	  if (seg_info (section)->fix_root == (fixS *) NULL)
@@ -472,17 +392,12 @@ chain_frchains_together_1 (segT section, struct frchain *frchp)
 	  seg_info (section)->fix_tail = frchp->fix_tail;
 	  prev_fix = frchp->fix_tail;
 	}
-#endif
     }
   assert (prev_frag->fr_type != 0);
   prev_frag->fr_next = 0;
   return prev_frag;
 }
 
-#endif
-
-#ifdef BFD_ASSEMBLER
-
 static void
 chain_frchains_together (bfd *abfd ATTRIBUTE_UNUSED,
 			 segT section,
@@ -502,28 +417,8 @@ chain_frchains_together (bfd *abfd ATTRIBUTE_UNUSED,
   frags_chained = 1;
 }
 
-#endif
-
-#if !defined (BFD) && !defined (BFD_ASSEMBLER)
-
-static void
-remove_subsegs (frchainS *head, int seg, fragS **root, fragS **last)
-{
-  *root = head->frch_root;
-  *last = chain_frchains_together_1 (seg, head);
-}
-
-#endif /* BFD  */
-
-#if defined (BFD_ASSEMBLER) || !defined (BFD)
-
-#ifdef BFD_ASSEMBLER
 static void
 cvt_frag_to_fill (segT sec ATTRIBUTE_UNUSED, fragS *fragP)
-#else
-static void
-cvt_frag_to_fill (object_headers *headersP, segT sec, fragS *fragP)
-#endif
 {
   switch (fragP->fr_type)
     {
@@ -577,11 +472,7 @@ cvt_frag_to_fill (object_headers *headersP, segT sec, fragS *fragP)
       break;
 
     case rs_machine_dependent:
-#ifdef BFD_ASSEMBLER
       md_convert_frag (stdoutput, sec, fragP);
-#else
-      md_convert_frag (headersP, sec, fragP);
-#endif
 
       assert (fragP->fr_next == NULL
 	      || ((offsetT) (fragP->fr_next->fr_address - fragP->fr_address)
@@ -616,24 +507,26 @@ cvt_frag_to_fill (object_headers *headersP, segT sec, fragS *fragP)
       BAD_CASE (fragP->fr_type);
       break;
     }
+#ifdef md_frag_check
+  md_frag_check (fragP);
+#endif
 }
 
-#endif /* defined (BFD_ASSEMBLER) || !defined (BFD)  */
-
-#ifdef BFD_ASSEMBLER
-static void relax_seg (bfd *, asection *, PTR);
+struct relax_seg_info
+{
+  int pass;
+  int changed;
+};
 
 static void
-relax_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, PTR xxx)
+relax_seg (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, void *xxx)
 {
   segment_info_type *seginfo = seg_info (sec);
+  struct relax_seg_info *info = (struct relax_seg_info *) xxx;
 
   if (seginfo && seginfo->frchainP
-      && relax_segment (seginfo->frchainP->frch_root, sec))
-    {
-      int *result = (int *) xxx;
-      *result = 1;
-    }
+      && relax_segment (seginfo->frchainP->frch_root, sec, info->pass))
+    info->changed = 1;
 }
 
 static void size_seg (bfd *, asection *, PTR);
@@ -711,12 +604,8 @@ size_seg (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 
 #ifdef DEBUG2
 static void
-dump_section_relocs (abfd, sec, stream_)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     asection *sec;
-     char *stream_;
+dump_section_relocs (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, FILE *stream)
 {
-  FILE *stream = (FILE *) stream_;
   segment_info_type *seginfo = seg_info (sec);
   fixS *fixp = seginfo->fix_root;
 
@@ -789,9 +678,10 @@ adjust_reloc_syms (bfd *abfd ATTRIBUTE_UNUSED,
 	if (fixp->fx_subsy != NULL)
 	  resolve_symbol_value (fixp->fx_subsy);
 
-	/* If this symbol is equated to an undefined symbol, convert
-           the fixup to being against that symbol.  */
-	if (symbol_equated_reloc_p (sym))
+	/* If this symbol is equated to an undefined or common symbol,
+	   convert the fixup to being against that symbol.  */
+	if (symbol_equated_reloc_p (sym)
+	    || S_IS_WEAKREFR (sym))
 	  {
 	    fixp->fx_offset += symbol_get_value_expression (sym)->X_add_number;
 	    sym = symbol_get_value_expression (sym)->X_add_symbol;
@@ -944,12 +834,12 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 	  continue;
 	}
 
-#if 0
-      /* This test is triggered inappropriately for the SH.  */
-      if (fixp->fx_where + fixp->fx_size
-	  > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
-	abort ();
-#endif
+      /*
+	This test is triggered inappropriately for the SH:
+         if (fixp->fx_where + fixp->fx_size
+	     > fixp->fx_frag->fr_fix + fixp->fx_frag->fr_offset)
+	     abort ();
+      */
 
       s = bfd_install_relocation (stdoutput, reloc,
 				  fixp->fx_frag->fr_literal,
@@ -1050,7 +940,7 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 
 #ifdef DEBUG4
   {
-    int i, j, nsyms;
+    unsigned int i, j, nsyms;
     asymbol **sympp;
     sympp = bfd_get_outsymbols (stdoutput);
     nsyms = bfd_get_symcount (stdoutput);
@@ -1079,7 +969,7 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
 
 #ifdef DEBUG3
   {
-    int i;
+    unsigned int i;
     arelent *r;
     asymbol *s;
     fprintf (stderr, "relocs for sec %s\n", sec->name);
@@ -1087,8 +977,8 @@ write_relocs (bfd *abfd, asection *sec, PTR xxx ATTRIBUTE_UNUSED)
       {
 	r = relocs[i];
 	s = *r->sym_ptr_ptr;
-	fprintf (stderr, "  reloc %2d @%08x off %4x : sym %-10s addend %x\n",
-		 i, r, r->address, s->name, r->addend);
+	fprintf (stderr, "  reloc %2d @%p off %4lx : sym %-10s addend %lx\n",
+		 i, r, (unsigned long)r->address, s->name, (unsigned long)r->addend);
       }
   }
 #endif
@@ -1189,126 +1079,17 @@ write_contents (bfd *abfd ATTRIBUTE_UNUSED,
 	}
     }
 }
-#endif
 
-#if defined(BFD_ASSEMBLER) || (!defined (BFD) && !defined(OBJ_AOUT))
 static void
 merge_data_into_text (void)
 {
-#if defined(BFD_ASSEMBLER) || defined(MANY_SEGMENTS)
   seg_info (text_section)->frchainP->frch_last->fr_next =
     seg_info (data_section)->frchainP->frch_root;
   seg_info (text_section)->frchainP->frch_last =
     seg_info (data_section)->frchainP->frch_last;
   seg_info (data_section)->frchainP = 0;
-#else
-  fixS *tmp;
-
-  text_last_frag->fr_next = data_frag_root;
-  text_last_frag = data_last_frag;
-  data_last_frag = NULL;
-  data_frag_root = NULL;
-  if (text_fix_root)
-    {
-      for (tmp = text_fix_root; tmp->fx_next; tmp = tmp->fx_next);;
-      tmp->fx_next = data_fix_root;
-      text_fix_tail = data_fix_tail;
-    }
-  else
-    text_fix_root = data_fix_root;
-  data_fix_root = NULL;
-#endif
 }
-#endif /* BFD_ASSEMBLER || (! BFD && ! OBJ_AOUT)  */
 
-#if !defined (BFD_ASSEMBLER) && !defined (BFD)
-static void
-relax_and_size_all_segments ()
-{
-  fragS *fragP;
-
-  relax_segment (text_frag_root, SEG_TEXT);
-  relax_segment (data_frag_root, SEG_DATA);
-  relax_segment (bss_frag_root, SEG_BSS);
-
-  /* Now the addresses of frags are correct within the segment.  */
-  know (text_last_frag->fr_type == rs_fill && text_last_frag->fr_offset == 0);
-  H_SET_TEXT_SIZE (&headers, text_last_frag->fr_address);
-  text_last_frag->fr_address = H_GET_TEXT_SIZE (&headers);
-
-  /* Join the 2 segments into 1 huge segment.
-     To do this, re-compute every rn_address in the SEG_DATA frags.
-     Then join the data frags after the text frags.
-
-     Determine a_data [length of data segment].  */
-  if (data_frag_root)
-    {
-      register relax_addressT slide;
-
-      know ((text_last_frag->fr_type == rs_fill)
-	    && (text_last_frag->fr_offset == 0));
-
-      H_SET_DATA_SIZE (&headers, data_last_frag->fr_address);
-      data_last_frag->fr_address = H_GET_DATA_SIZE (&headers);
-      slide = H_GET_TEXT_SIZE (&headers);	/* & in file of the data segment.  */
-#ifdef OBJ_BOUT
-#define RoundUp(N,S) (((N)+(S)-1)&-(S))
-      /* For b.out: If the data section has a strict alignment
-	 requirement, its load address in the .o file will be
-	 rounded up from the size of the text section.  These
-	 two values are *not* the same!  Similarly for the bss
-	 section....  */
-      slide = RoundUp (slide, 1 << section_alignment[SEG_DATA]);
-#endif
-
-      for (fragP = data_frag_root; fragP; fragP = fragP->fr_next)
-	fragP->fr_address += slide;
-
-      know (text_last_frag != 0);
-      text_last_frag->fr_next = data_frag_root;
-    }
-  else
-    {
-      H_SET_DATA_SIZE (&headers, 0);
-    }
-
-#ifdef OBJ_BOUT
-  /* See above comments on b.out data section address.  */
-  {
-    addressT bss_vma;
-    if (data_last_frag == 0)
-      bss_vma = H_GET_TEXT_SIZE (&headers);
-    else
-      bss_vma = data_last_frag->fr_address;
-    bss_vma = RoundUp (bss_vma, 1 << section_alignment[SEG_BSS]);
-    bss_address_frag.fr_address = bss_vma;
-  }
-#else /* ! OBJ_BOUT  */
-  bss_address_frag.fr_address = (H_GET_TEXT_SIZE (&headers) +
-				 H_GET_DATA_SIZE (&headers));
-
-#endif /* ! OBJ_BOUT  */
-
-  /* Slide all the frags.  */
-  if (bss_frag_root)
-    {
-      relax_addressT slide = bss_address_frag.fr_address;
-
-      for (fragP = bss_frag_root; fragP; fragP = fragP->fr_next)
-	fragP->fr_address += slide;
-    }
-
-  if (bss_last_frag)
-    H_SET_BSS_SIZE (&headers,
-		    bss_last_frag->fr_address - bss_frag_root->fr_address);
-  else
-    H_SET_BSS_SIZE (&headers, 0);
-}
-#endif /* ! BFD_ASSEMBLER && ! BFD  */
-
-#if defined (BFD_ASSEMBLER) || !defined (BFD)
-
-#ifdef BFD_ASSEMBLER
 static void
 set_symtab (void)
 {
@@ -1344,7 +1125,6 @@ set_symtab (void)
   assert (result);
   symbol_table_frozen = 1;
 }
-#endif
 
 /* Finish the subsegments.  After every sub-segment, we fake an
    ".align ...".  This conforms to BSD4.2 brane-damage.  We then fake
@@ -1361,11 +1141,7 @@ set_symtab (void)
   (!(FRCHAIN)->frch_next || (FRCHAIN)->frch_next->frch_seg != (SEG)	\
    ? get_recorded_alignment (SEG) : 0)
 #else
-#ifdef BFD_ASSEMBLER
 #define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 0
-#else
-#define SUB_SEGMENT_ALIGN(SEG, FRCHAIN) 2
-#endif
 #endif
 #endif
 
@@ -1386,7 +1162,6 @@ subsegs_finish (void)
       if (!had_errors ())
 	{
 	  alignment = SUB_SEGMENT_ALIGN (now_seg, frchainP);
-#ifdef BFD_ASSEMBLER
 	  if ((bfd_get_section_flags (now_seg->owner, now_seg) & SEC_MERGE)
 	      && now_seg->entsize)
 	    {
@@ -1401,7 +1176,6 @@ subsegs_finish (void)
 	      if (entalign > alignment)
 		alignment = entalign;
 	    }
-#endif
 	}
 
       if (subseg_text_p (now_seg))
@@ -1425,7 +1199,8 @@ subsegs_finish (void)
 void
 write_object_file (void)
 {
-#if ! defined (BFD_ASSEMBLER) || ! defined (WORKING_DOT_WORD)
+  struct relax_seg_info rsi;
+#ifndef WORKING_DOT_WORD
   fragS *fragP;			/* Track along all frags.  */
 #endif
 
@@ -1462,49 +1237,30 @@ write_object_file (void)
   /* From now on, we don't care about sub-segments.  Build one frag chain
      for each segment. Linked thru fr_next.  */
 
-#ifdef BFD_ASSEMBLER
   /* Remove the sections created by gas for its own purposes.  */
   {
-    asection **seclist;
     int i;
 
-    seclist = &stdoutput->sections;
-    while (*seclist)
-      {
-	if (*seclist == reg_section || *seclist == expr_section)
-	  {
-	    bfd_section_list_remove (stdoutput, seclist);
-	    stdoutput->section_count--;
-	  }
-	else
-	  seclist = &(*seclist)->next;
-      }
+    bfd_section_list_remove (stdoutput, reg_section);
+    bfd_section_list_remove (stdoutput, expr_section);
+    stdoutput->section_count -= 2;
     i = 0;
     bfd_map_over_sections (stdoutput, renumber_sections, &i);
   }
 
   bfd_map_over_sections (stdoutput, chain_frchains_together, (char *) 0);
-#else
-  remove_subsegs (frchain_root, SEG_TEXT, &text_frag_root, &text_last_frag);
-  remove_subsegs (data0_frchainP, SEG_DATA, &data_frag_root, &data_last_frag);
-  remove_subsegs (bss0_frchainP, SEG_BSS, &bss_frag_root, &bss_last_frag);
-#endif
 
   /* We have two segments. If user gave -R flag, then we must put the
      data frags into the text segment. Do this before relaxing so
      we know to take advantage of -R and make shorter addresses.  */
-#if !defined (OBJ_AOUT) || defined (BFD_ASSEMBLER)
   if (flag_readonly_data_in_text)
     {
       merge_data_into_text ();
     }
-#endif
 
-#ifdef BFD_ASSEMBLER
+  rsi.pass = 0;
   while (1)
     {
-      int changed;
-
 #ifndef WORKING_DOT_WORD
       /* We need to reset the markers in the broken word list and
 	 associated frags between calls to relax_segment (via
@@ -1525,9 +1281,10 @@ write_object_file (void)
 	}
 #endif
 
-      changed = 0;
-      bfd_map_over_sections (stdoutput, relax_seg, &changed);
-      if (!changed)
+      rsi.changed = 0;
+      bfd_map_over_sections (stdoutput, relax_seg, &rsi);
+      rsi.pass++;
+      if (!rsi.changed)
 	break;
     }
 
@@ -1541,9 +1298,6 @@ write_object_file (void)
   finalize_syms = TC_FINALIZE_SYMS_BEFORE_SIZE_SEG;
 
   bfd_map_over_sections (stdoutput, size_seg, (char *) 0);
-#else
-  relax_and_size_all_segments ();
-#endif /* BFD_ASSEMBLER  */
 
   /* Relaxation has completed.  Freeze all syms.  */
   finalize_syms = 1;
@@ -1552,64 +1306,6 @@ write_object_file (void)
   md_post_relax_hook;
 #endif
 
-#ifndef BFD_ASSEMBLER
-  /* Crawl the symbol chain.
-
-     For each symbol whose value depends on a frag, take the address of
-     that frag and subsume it into the value of the symbol.
-     After this, there is just one way to lookup a symbol value.
-     Values are left in their final state for object file emission.
-     We adjust the values of 'L' local symbols, even if we do
-     not intend to emit them to the object file, because their values
-     are needed for fix-ups.
-
-     Unless we saw a -L flag, remove all symbols that begin with 'L'
-     from the symbol chain.  (They are still pointed to by the fixes.)
-
-     Count the remaining symbols.
-     Assign a symbol number to each symbol.
-     Count the number of string-table chars we will emit.
-     Put this info into the headers as appropriate.  */
-  know (zero_address_frag.fr_address == 0);
-  string_byte_count = sizeof (string_byte_count);
-
-  obj_crawl_symbol_chain (&headers);
-
-  if (string_byte_count == sizeof (string_byte_count))
-    string_byte_count = 0;
-
-  H_SET_STRING_SIZE (&headers, string_byte_count);
-
-  /* Addresses of frags now reflect addresses we use in the object file.
-     Symbol values are correct.
-     Scan the frags, converting any ".org"s and ".align"s to ".fill"s.
-     Also converting any machine-dependent frags using md_convert_frag();  */
-  subseg_change (SEG_TEXT, 0);
-
-  for (fragP = text_frag_root; fragP; fragP = fragP->fr_next)
-    {
-      /* At this point we have linked all the frags into a single
-         chain.  However, cvt_frag_to_fill may call md_convert_frag
-         which may call fix_new.  We need to ensure that fix_new adds
-         the fixup to the right section.  */
-      if (fragP == data_frag_root)
-	subseg_change (SEG_DATA, 0);
-
-      cvt_frag_to_fill (&headers, SEG_TEXT, fragP);
-
-      /* Some assert macros don't work with # directives mixed in.  */
-#ifndef NDEBUG
-      if (!(fragP->fr_next == NULL
-#ifdef OBJ_BOUT
-	    || fragP->fr_next == data_frag_root
-#endif
-	    || ((offsetT) (fragP->fr_next->fr_address - fragP->fr_address)
-		== (fragP->fr_fix + fragP->fr_offset * fragP->fr_var))))
-	abort ();
-#endif
-    }
-#endif /* ! BFD_ASSEMBLER  */
-
 #ifndef WORKING_DOT_WORD
   {
     struct broken_word *lie;
@@ -1626,7 +1322,6 @@ write_object_file (void)
 	  exp.X_add_symbol = lie->add;
 	  exp.X_op_symbol = lie->sub;
 	  exp.X_add_number = lie->addnum;
-#ifdef BFD_ASSEMBLER
 #ifdef TC_CONS_FIX_NEW
 	  TC_CONS_FIX_NEW (lie->frag,
 			   lie->word_goes_here - lie->frag->fr_literal,
@@ -1636,23 +1331,6 @@ write_object_file (void)
 		       lie->word_goes_here - lie->frag->fr_literal,
 		       2, &exp, 0, BFD_RELOC_16);
 #endif
-#else
-#if defined(TC_SPARC) || defined(TC_A29K) || defined(NEED_FX_R_TYPE)
-	  fix_new_exp (lie->frag,
-		       lie->word_goes_here - lie->frag->fr_literal,
-		       2, &exp, 0, NO_RELOC);
-#else
-#ifdef TC_NS32K
-	  fix_new_ns32k_exp (lie->frag,
-			     lie->word_goes_here - lie->frag->fr_literal,
-			     2, &exp, 0, 0, 2, 0, 0);
-#else
-	  fix_new_exp (lie->frag,
-		       lie->word_goes_here - lie->frag->fr_literal,
-		       2, &exp, 0, 0);
-#endif /* TC_NS32K  */
-#endif /* TC_SPARC|TC_A29K|NEED_FX_R_TYPE  */
-#endif /* BFD_ASSEMBLER  */
 	  *prevP = lie->next_broken_word;
 	}
       else
@@ -1723,132 +1401,6 @@ write_object_file (void)
   }
 #endif /* not WORKING_DOT_WORD  */
 
-#ifndef BFD_ASSEMBLER
-#ifndef	OBJ_VMS
-  {				/* not vms  */
-    char *the_object_file;
-    long object_file_size;
-    /* Scan every FixS performing fixups. We had to wait until now to
-       do this because md_convert_frag() may have made some fixSs.  */
-    int trsize, drsize;
-
-    subseg_change (SEG_TEXT, 0);
-    trsize = md_reloc_size * fixup_segment (text_fix_root, SEG_TEXT);
-    subseg_change (SEG_DATA, 0);
-    drsize = md_reloc_size * fixup_segment (data_fix_root, SEG_DATA);
-    H_SET_RELOCATION_SIZE (&headers, trsize, drsize);
-
-    /* FIXME: Move this stuff into the pre-write-hook.  */
-    H_SET_MAGIC_NUMBER (&headers, magic_number_for_object_file);
-    H_SET_ENTRY_POINT (&headers, 0);
-
-    obj_pre_write_hook (&headers);	/* Extra coff stuff.  */
-
-    object_file_size = H_GET_FILE_SIZE (&headers);
-    next_object_file_charP = the_object_file = xmalloc (object_file_size);
-
-    output_file_create (out_file_name);
-
-    obj_header_append (&next_object_file_charP, &headers);
-
-    know ((next_object_file_charP - the_object_file)
-	  == H_GET_HEADER_SIZE (&headers));
-
-    /* Emit code.  */
-    for (fragP = text_frag_root; fragP; fragP = fragP->fr_next)
-      {
-	register long count;
-	register char *fill_literal;
-	register long fill_size;
-
-	PROGRESS (1);
-	know (fragP->fr_type == rs_fill);
-	append (&next_object_file_charP, fragP->fr_literal,
-		(unsigned long) fragP->fr_fix);
-	fill_literal = fragP->fr_literal + fragP->fr_fix;
-	fill_size = fragP->fr_var;
-	know (fragP->fr_offset >= 0);
-
-	for (count = fragP->fr_offset; count; count--)
-	  append (&next_object_file_charP, fill_literal,
-		  (unsigned long) fill_size);
-      }
-
-    know ((next_object_file_charP - the_object_file)
-	  == (H_GET_HEADER_SIZE (&headers)
-	      + H_GET_TEXT_SIZE (&headers)
-	      + H_GET_DATA_SIZE (&headers)));
-
-    /* Emit relocations.  */
-    obj_emit_relocations (&next_object_file_charP, text_fix_root,
-			  (relax_addressT) 0);
-    know ((next_object_file_charP - the_object_file)
-	  == (H_GET_HEADER_SIZE (&headers)
-	      + H_GET_TEXT_SIZE (&headers)
-	      + H_GET_DATA_SIZE (&headers)
-	      + H_GET_TEXT_RELOCATION_SIZE (&headers)));
-#ifdef TC_I960
-    /* Make addresses in data relocation directives relative to beginning of
-       first data fragment, not end of last text fragment:  alignment of the
-       start of the data segment may place a gap between the segments.  */
-    obj_emit_relocations (&next_object_file_charP, data_fix_root,
-			  data0_frchainP->frch_root->fr_address);
-#else /* TC_I960  */
-    obj_emit_relocations (&next_object_file_charP, data_fix_root,
-			  text_last_frag->fr_address);
-#endif /* TC_I960  */
-
-    know ((next_object_file_charP - the_object_file)
-	  == (H_GET_HEADER_SIZE (&headers)
-	      + H_GET_TEXT_SIZE (&headers)
-	      + H_GET_DATA_SIZE (&headers)
-	      + H_GET_TEXT_RELOCATION_SIZE (&headers)
-	      + H_GET_DATA_RELOCATION_SIZE (&headers)));
-
-    /* Emit line number entries.  */
-    OBJ_EMIT_LINENO (&next_object_file_charP, lineno_rootP, the_object_file);
-    know ((next_object_file_charP - the_object_file)
-	  == (H_GET_HEADER_SIZE (&headers)
-	      + H_GET_TEXT_SIZE (&headers)
-	      + H_GET_DATA_SIZE (&headers)
-	      + H_GET_TEXT_RELOCATION_SIZE (&headers)
-	      + H_GET_DATA_RELOCATION_SIZE (&headers)
-	      + H_GET_LINENO_SIZE (&headers)));
-
-    /* Emit symbols.  */
-    obj_emit_symbols (&next_object_file_charP, symbol_rootP);
-    know ((next_object_file_charP - the_object_file)
-	  == (H_GET_HEADER_SIZE (&headers)
-	      + H_GET_TEXT_SIZE (&headers)
-	      + H_GET_DATA_SIZE (&headers)
-	      + H_GET_TEXT_RELOCATION_SIZE (&headers)
-	      + H_GET_DATA_RELOCATION_SIZE (&headers)
-	      + H_GET_LINENO_SIZE (&headers)
-	      + H_GET_SYMBOL_TABLE_SIZE (&headers)));
-
-    /* Emit strings.  */
-    if (string_byte_count > 0)
-      obj_emit_strings (&next_object_file_charP);
-
-#ifdef BFD_HEADERS
-    bfd_seek (stdoutput, (file_ptr) 0, 0);
-    bfd_bwrite (the_object_file, (bfd_size_type) object_file_size, stdoutput);
-#else
-
-    /* Write the data to the file.  */
-    output_file_append (the_object_file, object_file_size, out_file_name);
-    free (the_object_file);
-#endif
-  }
-#else /* OBJ_VMS  */
-  /* Now do the VMS-dependent part of writing the object file.  */
-  vms_write_object_file (H_GET_TEXT_SIZE (&headers),
-			 H_GET_DATA_SIZE (&headers),
-			 H_GET_BSS_SIZE (&headers),
-			 text_frag_root, data_frag_root);
-#endif /* OBJ_VMS  */
-#else /* BFD_ASSEMBLER  */
-
   /* Resolve symbol values.  This needs to be done before processing
      the relocations.  */
   if (symbol_rootP)
@@ -1884,12 +1436,22 @@ write_object_file (void)
   if (symbol_rootP)
     {
       symbolS *symp;
+      bfd_boolean skip_next_symbol = FALSE;
 
       for (symp = symbol_rootP; symp; symp = symbol_next (symp))
 	{
 	  int punt = 0;
 	  const char *name;
 
+	  if (skip_next_symbol)
+	    {
+	      /* Don't do anything besides moving the value of the
+		 symbol from the GAS value-field to the BFD value-field.  */
+	      symbol_get_bfdsym (symp)->value = S_GET_VALUE (symp);
+	      skip_next_symbol = FALSE;
+	      continue;
+	    }
+
 	  if (symbol_mri_common_p (symp))
 	    {
 	      if (S_IS_EXTERNAL (symp))
@@ -1917,25 +1479,23 @@ write_object_file (void)
 
 	  /* Skip symbols which were equated to undefined or common
              symbols.  */
-	  if (symbol_equated_reloc_p (symp))
+	  if (symbol_equated_reloc_p (symp)
+	      || S_IS_WEAKREFR (symp))
 	    {
+	      const char *name = S_GET_NAME (symp);
+	      if (S_IS_COMMON (symp)
+		  && !TC_FAKE_LABEL (name)
+		  && !S_IS_WEAKREFR (symp)
+		  && (!S_IS_EXTERNAL (symp) || S_IS_LOCAL (symp)))
+		{
+		  expressionS *e = symbol_get_value_expression (symp);
+		  as_bad (_("Local symbol `%s' can't be equated to common symbol `%s'"),
+			  name, S_GET_NAME (e->X_add_symbol));
+		}
 	      symbol_remove (symp, &symbol_rootP, &symbol_lastP);
 	      continue;
 	    }
 
-	  /* So far, common symbols have been treated like undefined symbols.
-	     Put them in the common section now.  */
-	  if (S_IS_DEFINED (symp) == 0
-	      && S_GET_VALUE (symp) != 0)
-	    S_SET_SEGMENT (symp, bfd_com_section_ptr);
-#if 0
-	  printf ("symbol `%s'\n\t@%x: value=%d flags=%x seg=%s\n",
-		  S_GET_NAME (symp), symp,
-		  S_GET_VALUE (symp),
-		  symbol_get_bfdsym (symp)->flags,
-		  segment_name (S_GET_SEGMENT (symp)));
-#endif
-
 #ifdef obj_frob_symbol
 	  obj_frob_symbol (symp, punt);
 #endif
@@ -1952,11 +1512,12 @@ write_object_file (void)
 	  if (symp == abs_section_sym
 	      || (! EMIT_SECTION_SYMBOLS
 		  && symbol_section_p (symp))
-	      /* Note that S_IS_EXTERN and S_IS_LOCAL are not always
+	      /* Note that S_IS_EXTERNAL and S_IS_LOCAL are not always
 		 opposites.  Sometimes the former checks flags and the
 		 latter examines the name...  */
-	      || (!S_IS_EXTERN (symp)
-		  && (punt || S_IS_LOCAL (symp))
+	      || (!S_IS_EXTERNAL (symp)
+		  && (punt || S_IS_LOCAL (symp) ||
+		      (S_IS_WEAKREFD (symp) && ! symbol_used_p (symp)))
 		  && ! symbol_used_in_reloc_p (symp)))
 	    {
 	      symbol_remove (symp, &symbol_rootP, &symbol_lastP);
@@ -1978,6 +1539,12 @@ write_object_file (void)
 	  /* Set the value into the BFD symbol.  Up til now the value
 	     has only been kept in the gas symbolS struct.  */
 	  symbol_get_bfdsym (symp)->value = S_GET_VALUE (symp);
+
+	  /* A warning construct is a warning symbol followed by the
+	     symbol warned about.  Don't let anything object-format or
+	     target-specific muck with it; it's ready for output.  */
+	  if (symbol_get_bfdsym (symp)->flags & BSF_WARNING)
+	    skip_next_symbol = TRUE;
 	}
     }
 
@@ -2017,12 +1584,9 @@ write_object_file (void)
 #endif
 
   bfd_map_over_sections (stdoutput, write_contents, (char *) 0);
-#endif /* BFD_ASSEMBLER  */
 }
-#endif /* ! BFD  */
 
 #ifdef TC_GENERIC_RELAX_TABLE
-
 /* Relax a fragment by scanning TC_GENERIC_RELAX_TABLE.  */
 
 long
@@ -2053,12 +1617,6 @@ relax_frag (segT segment, fragS *fragP, long stretch)
       sym_frag = symbol_get_frag (symbolP);
 
 #ifndef DIFF_EXPR_OK
-#if !defined (MANY_SEGMENTS) && !defined (BFD_ASSEMBLER)
-      know ((S_GET_SEGMENT (symbolP) == SEG_ABSOLUTE)
-	    || (S_GET_SEGMENT (symbolP) == SEG_DATA)
-	    || (S_GET_SEGMENT (symbolP) == SEG_BSS)
-	    || (S_GET_SEGMENT (symbolP) == SEG_TEXT));
-#endif
       know (sym_frag != NULL);
 #endif
       know (S_GET_SEGMENT (symbolP) != absolute_section
@@ -2082,14 +1640,10 @@ relax_frag (segT segment, fragS *fragP, long stretch)
 #ifdef TC_PCREL_ADJUST
   /* Currently only the ns32k family needs this.  */
   aim += TC_PCREL_ADJUST (fragP);
-/* #else */
-  /* This machine doesn't want to use pcrel_adjust.
-     In that case, pcrel_adjust should be zero.  */
-#if 0
-  assert (fragP->fr_targ.ns32k.pcrel_adjust == 0);
-#endif
 #endif
-#ifdef md_prepare_relax_scan /* formerly called M68K_AIM_KLUDGE  */
+
+#ifdef md_prepare_relax_scan
+  /* Formerly called M68K_AIM_KLUDGE.  */
   md_prepare_relax_scan (fragP, address, aim, this_state, this_type);
 #endif
 
@@ -2161,22 +1715,22 @@ relax_align (register relax_addressT address,	/* Address now.  */
    addresses.  */
 
 int
-relax_segment (struct frag *segment_frag_root, segT segment)
+relax_segment (struct frag *segment_frag_root, segT segment, int pass)
 {
-  register struct frag *fragP;
-  register relax_addressT address;
+  unsigned long frag_count;
+  struct frag *fragP;
+  relax_addressT address;
   int ret;
 
-#if !defined (MANY_SEGMENTS) && !defined (BFD_ASSEMBLER)
-  know (segment == SEG_DATA || segment == SEG_TEXT || segment == SEG_BSS);
-#endif
   /* In case md_estimate_size_before_relax() wants to make fixSs.  */
   subseg_change (segment, 0);
 
   /* For each frag in segment: count and store  (a 1st guess of)
      fr_address.  */
   address = 0;
-  for (fragP = segment_frag_root; fragP; fragP = fragP->fr_next)
+  for (frag_count = 0, fragP = segment_frag_root;
+       fragP;
+       fragP = fragP->fr_next, frag_count ++)
     {
       fragP->relax_marker = 0;
       fragP->fr_address = address;
@@ -2252,6 +1806,7 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 
   /* Do relax().  */
   {
+    unsigned long max_iterations;
     offsetT stretch;	/* May be any size, 0 or negative.  */
     /* Cumulative number of addresses we have relaxed this pass.
        We may have relaxed more than one address.  */
@@ -2260,6 +1815,21 @@ relax_segment (struct frag *segment_frag_root, segT segment)
        grew, and another shrank.  If a branch instruction doesn't fit anymore,
        we could be scrod.  */
 
+    /* We want to prevent going into an infinite loop where one frag grows
+       depending upon the location of a symbol which is in turn moved by
+       the growing frag.  eg:
+
+         foo = .
+         .org foo+16
+         foo = .
+
+	So we dictate that this algorithm can be at most O2.  */
+    max_iterations = frag_count * frag_count;
+    /* Check for overflow.  */
+    if (max_iterations < frag_count)
+      max_iterations = frag_count;
+
+    ret = 0;
     do
       {
 	stretch = 0;
@@ -2376,20 +1946,11 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 
 		  if (symbolP)
 		    {
-#if !defined (MANY_SEGMENTS) && !defined (BFD_ASSEMBLER)
-		      know ((S_GET_SEGMENT (symbolP) == SEG_ABSOLUTE)
-			    || (S_GET_SEGMENT (symbolP) == SEG_DATA)
-			    || (S_GET_SEGMENT (symbolP) == SEG_TEXT)
-			    || S_GET_SEGMENT (symbolP) == SEG_BSS);
-		      know (symbolP->sy_frag);
-		      know (!(S_GET_SEGMENT (symbolP) == SEG_ABSOLUTE)
-			    || (symbolP->sy_frag == &zero_address_frag));
-#endif
                       /* Convert from an actual address to an octet offset
                          into the section.  Here it is assumed that the
                          section's VMA is zero, and can omit subtracting it
                          from the symbol's value to get the address offset.  */
-                      know (S_GET_SECTION (symbolP)->vma == 0);
+                      know (S_GET_SEGMENT (symbolP)->vma == 0);
 		      target += S_GET_VALUE (symbolP) * OCTETS_PER_BYTE;
 		    }
 
@@ -2398,6 +1959,26 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 		  growth = target - after;
 		  if (growth < 0)
 		    {
+		      growth = 0;
+
+		      /* Don't error on first few frag relax passes.
+			 The symbol might be an expression involving
+			 symbol values from other sections.  If those
+			 sections have not yet been processed their
+			 frags will all have zero addresses, so we
+			 will calculate incorrect values for them.  The
+			 number of passes we allow before giving an
+			 error is somewhat arbitrary.  It should be at
+			 least one, with larger values requiring
+			 increasingly contrived dependencies between
+			 frags to trigger a false error.  */
+		      if (pass < 2)
+			{
+			  /* Force another pass.  */
+			  ret = 1;
+			  break;
+			}
+
 		      /* Growth may be negative, but variable part of frag
 			 cannot have fewer than 0 chars.  That is, we can't
 			 .org backwards.  */
@@ -2409,8 +1990,8 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 		      fragP->fr_type = rs_align;
 		      fragP->fr_subtype = 0;
 		      fragP->fr_offset = 0;
-		      fragP->fr_fix = after - address;
-		      growth = stretch;
+		      fragP->fr_fix = after - was_address;
+		      break;
 		    }
 
 		  /* This is an absolute growth factor  */
@@ -2436,6 +2017,14 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 		      }
 		    else if (amount < 0)
 		      {
+			/* Don't error on first few frag relax passes.
+			   See rs_org comment for a longer explanation.  */
+			if (pass < 2)
+			  {
+			    ret = 1;
+			    break;
+			  }
+
 			as_warn_where (fragP->fr_file, fragP->fr_line,
 				       _(".space or .fill with negative value, ignored"));
 			fragP->fr_symbol = 0;
@@ -2487,12 +2076,16 @@ relax_segment (struct frag *segment_frag_root, segT segment)
 		stretch += growth;
 		stretched = 1;
 	      }
-	  }			/* For each frag in the segment.  */
+	  }
       }
-    while (stretched);		/* Until nothing further to relax.  */
-  }				/* do_relax  */
+    /* Until nothing further to relax.  */
+    while (stretched && -- max_iterations);
+
+    if (stretched)
+      as_fatal (_("Infinite loop encountered whilst attempting to compute the addresses of symbols in section %s"),
+		segment_name (segment));
+  }
 
-  ret = 0;
   for (fragP = segment_frag_root; fragP; fragP = fragP->fr_next)
     if (fragP->last_fr_address != fragP->fr_address)
       {
@@ -2502,14 +2095,12 @@ relax_segment (struct frag *segment_frag_root, segT segment)
   return ret;
 }
 
-#if defined (BFD_ASSEMBLER) || (!defined (BFD) && !defined (OBJ_VMS))
-
 /* fixup_segment()
 
    Go through all the fixS's in a segment and see which ones can be
    handled now.  (These consist of fixS where we have since discovered
    the value of a symbol, or the address of the frag involved.)
-   For each one, call md_apply_fix3 to put the fix into the frag data.
+   For each one, call md_apply_fix to put the fix into the frag data.
 
    Result is a count of how many relocation structs will be needed to
    handle the remaining fixS's that we couldn't completely handle here.
@@ -2524,13 +2115,7 @@ fixup_segment (fixS *fixP, segT this_segment)
   segT add_symbol_segment = absolute_section;
 
   if (fixP != NULL && abs_section_sym == NULL)
-    {
-#ifndef BFD_ASSEMBLER
-      abs_section_sym = &abs_symbol;
-#else
-      abs_section_sym = section_symbol (absolute_section);
-#endif
-    }
+    abs_section_sym = section_symbol (absolute_section);
 
   /* If the linker is doing the relaxing, we must not do any fixups.
 
@@ -2577,7 +2162,6 @@ fixup_segment (fixS *fixP, segT this_segment)
       if (fixP->fx_addsy != NULL
 	  && symbol_mri_common_p (fixP->fx_addsy))
 	{
-	  know (fixP->fx_addsy->sy_value.X_op == O_symbol);
 	  add_number += S_GET_VALUE (fixP->fx_addsy);
 	  fixP->fx_offset = add_number;
 	  fixP->fx_addsy
@@ -2670,9 +2254,7 @@ fixup_segment (fixS *fixP, segT this_segment)
 	      fixP->fx_addsy = NULL;
 	    }
 	  else if (add_symbol_segment != undefined_section
-#ifdef BFD_ASSEMBLER
 		   && ! bfd_is_com_section (add_symbol_segment)
-#endif
 		   && MD_APPLY_SYM_VALUE (fixP))
 	    add_number += S_GET_VALUE (fixP->fx_addsy);
 	}
@@ -2691,7 +2273,7 @@ fixup_segment (fixS *fixP, segT this_segment)
 	}
 
       if (!fixP->fx_done)
-	md_apply_fix3 (fixP, &add_number, this_segment);
+	md_apply_fix (fixP, &add_number, this_segment);
 
       if (!fixP->fx_done)
 	{
@@ -2753,8 +2335,6 @@ fixup_segment (fixS *fixP, segT this_segment)
   return seg_reloc_count;
 }
 
-#endif /* defined (BFD_ASSEMBLER) || (!defined (BFD) && !defined (OBJ_VMS)) */
-
 void
 number_to_chars_bigendian (char *buf, valueT val, int n)
 {
@@ -2812,14 +2392,8 @@ print_fixup (fixS *fixp)
   fprintf (stderr, "\n    size=%d frag=%lx where=%ld offset=%lx addnumber=%lx",
 	   fixp->fx_size, (long) fixp->fx_frag, (long) fixp->fx_where,
 	   (long) fixp->fx_offset, (long) fixp->fx_addnumber);
-#ifdef BFD_ASSEMBLER
   fprintf (stderr, "\n    %s (%d)", bfd_get_reloc_code_name (fixp->fx_r_type),
 	   fixp->fx_r_type);
-#else
-#ifdef NEED_FX_R_TYPE
-  fprintf (stderr, " r_type=%d", fixp->fx_r_type);
-#endif
-#endif
   if (fixp->fx_addsy)
     {
       fprintf (stderr, "\n   +<");
diff --git a/gas/write.h b/gas/write.h
index 0e0f59f8f70b..1f9b72dbf265 100644
--- a/gas/write.h
+++ b/gas/write.h
@@ -1,6 +1,6 @@
 /* write.h
-   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001
-   Free Software Foundation, Inc.
+   Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001,
+   2002, 2003, 2005, 2006 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -16,8 +16,8 @@
 
    You should have received a copy of the GNU General Public License
    along with GAS; see the file COPYING.  If not, write to the Free
-   Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-   02111-1307, USA.  */
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
 
 #ifndef __write_h__
 #define __write_h__
@@ -28,16 +28,6 @@
 #endif
 #endif /* TC_I960 */
 
-#ifndef BFD_ASSEMBLER
-
-#ifndef LOCAL_LABEL
-#define LOCAL_LABEL(name) (name [0] == 'L' )
-#endif
-
-#define S_LOCAL_NAME(s) (LOCAL_LABEL (S_GET_NAME (s)))
-
-#endif /* ! BFD_ASSEMBLER */
-
 /* This is the name of a fake symbol which will never appear in the
    assembler output.  S_IS_LOCAL detects it because of the \001.  */
 #ifndef FAKE_LABEL_NAME
@@ -120,15 +110,7 @@ struct fix
      processing.  */
   bit_fixS *fx_bit_fixP;
 
-#ifdef BFD_ASSEMBLER
   bfd_reloc_code_real_type fx_r_type;
-#else
-#ifdef NEED_FX_R_TYPE
-  /* Hack for machines where the type of reloc can't be
-     worked out by looking at how big it is.  */
-  int fx_r_type;
-#endif
-#endif
 
   /* This field is sort of misnamed.  It appears to be a sort of random
      scratch field, for use by the back ends.  The main gas code doesn't
@@ -165,53 +147,24 @@ typedef struct fix fixS;
 extern int finalize_syms;
 extern symbolS *abs_section_sym;
 extern addressT dot_value;
-
-#ifndef BFD_ASSEMBLER
-extern char *next_object_file_charP;
-
-#ifndef MANY_SEGMENTS
-COMMON fixS *text_fix_root, *text_fix_tail;	/* Chains fixSs.  */
-COMMON fixS *data_fix_root, *data_fix_tail;	/* Chains fixSs.  */
-COMMON fixS *bss_fix_root, *bss_fix_tail;	/* Chains fixSs.  */
-extern struct frag *text_last_frag;		/* Last frag in segment.  */
-extern struct frag *data_last_frag;		/* Last frag in segment.  */
-#endif
-COMMON fixS **seg_fix_rootP, **seg_fix_tailP;	/* -> one of above.  */
-#endif
-
 extern long string_byte_count;
 extern int section_alignment[];
 
-extern bit_fixS *bit_fix_new
-  (int size, int offset, long base_type, long base_adj, long min,
-   long max, long add);
 extern void append (char **charPP, char *fromP, unsigned long length);
 extern void record_alignment (segT seg, int align);
 extern int get_recorded_alignment (segT seg);
 extern void subsegs_finish (void);
 extern void write_object_file (void);
 extern long relax_frag (segT, fragS *, long);
-extern int relax_segment (struct frag * seg_frag_root, segT seg_type);
-
+extern int relax_segment (struct frag *, segT, int);
 extern void number_to_chars_littleendian (char *, valueT, int);
 extern void number_to_chars_bigendian (char *, valueT, int);
-
-#ifdef BFD_ASSEMBLER
 extern fixS *fix_new
   (fragS * frag, int where, int size, symbolS * add_symbol,
    offsetT offset, int pcrel, bfd_reloc_code_real_type r_type);
 extern fixS *fix_new_exp
   (fragS * frag, int where, int size, expressionS *exp, int pcrel,
    bfd_reloc_code_real_type r_type);
-#else
-extern fixS *fix_new
-  (fragS * frag, int where, int size, symbolS * add_symbol,
-   offsetT offset, int pcrel, int r_type);
-extern fixS *fix_new_exp
-  (fragS * frag, int where, int size, expressionS *exp, int pcrel,
-   int r_type);
-#endif
-
 extern void write_print_statistics (FILE *);
 
 #endif /* __write_h__ */